commit 2d2912a771a64188d74324fceb8dad2d2dbbcee2 Author: feda Date: Mon Mar 3 15:53:11 2025 +0300 initial software commit diff --git a/.mxproject b/.mxproject new file mode 100644 index 0000000..8c3bb1f --- /dev/null +++ b/.mxproject @@ -0,0 +1,24 @@ +[PreviousLibFiles] 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+ +[PreviousUsedKeilFiles] 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+HeaderPath=Drivers/STM32F7xx_HAL_Driver/Inc;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy;Middlewares/Third_Party/FatFs/src;Drivers/CMSIS/Device/ST/STM32F7xx/Include;Drivers/CMSIS/Include;Inc; +CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32F767xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +HeaderPath=../Inc +HeaderFiles=ffconf.h;bsp_driver_sd.h;sd_diskio.h;fatfs.h;fatfs_platform.h;stm32f7xx_it.h;stm32_assert.h;stm32f7xx_hal_conf.h;main.h; +SourcePath=../Src +SourceFiles=bsp_driver_sd.c;sd_diskio.c;fatfs.c;fatfs_platform.c;stm32f7xx_it.c;stm32f7xx_hal_msp.c;main.c; + +[PreviousUsedCubeIDEFiles] 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+HeaderPath=Drivers/STM32F7xx_HAL_Driver/Inc;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy;Middlewares/Third_Party/FatFs/src;Drivers/CMSIS/Device/ST/STM32F7xx/Include;Drivers/CMSIS/Include;Inc; +CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32F767xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + diff --git a/.project b/.project new file mode 100644 index 0000000..a430205 --- /dev/null +++ b/.project @@ -0,0 +1,11 @@ + + + For_stm32_2023_12_08 + + + + + + + + diff --git a/.project.bak b/.project.bak new file mode 100644 index 0000000..a430205 --- /dev/null +++ b/.project.bak @@ -0,0 +1,11 @@ + + + For_stm32_2023_12_08 + + + + + + + + diff --git a/Drivers/CMSIS/Core/Include/cmsis_armcc.h b/Drivers/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000..7d751fb --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_armclang.h b/Drivers/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000..d8031b0 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_compiler.h b/Drivers/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000..79a2cac --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Core/Include/cmsis_gcc.h b/Drivers/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000..1bd41a4 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_iccarm.h b/Drivers/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000..3c90a2c --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_version.h b/Drivers/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000..ae3f2e3 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Core/Include/core_armv8mbl.h b/Drivers/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 0000000..ec76ab2 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_armv8mml.h b/Drivers/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 0000000..2d0f106 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,2927 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm0.h b/Drivers/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 0000000..6f82227 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm0plus.h b/Drivers/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 0000000..b9377e8 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1083 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm1.h b/Drivers/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 0000000..fd1c407 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 23. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm23.h b/Drivers/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 0000000..8202a8d --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,1993 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm3.h b/Drivers/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 0000000..b0dfbd3 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1941 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm33.h b/Drivers/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 0000000..02f82e2 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3002 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm4.h b/Drivers/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000..308b868 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm7.h b/Drivers/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 0000000..ada6c2a --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_sc000.h b/Drivers/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 0000000..9086c64 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_sc300.h b/Drivers/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 0000000..665822d --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/mpu_armv7.h b/Drivers/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000..7d4b600 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Drivers/CMSIS/Core/Include/mpu_armv8.h b/Drivers/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000..99ee9f9 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Drivers/CMSIS/Core/Include/tz_context.h b/Drivers/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000..d4c1474 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c b/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c new file mode 100644 index 0000000..cde9ff0 --- /dev/null +++ b/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c @@ -0,0 +1,58 @@ +/****************************************************************************** + * @file main_s.c + * @brief Code template for secure main function + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Use CMSE intrinsics */ +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c b/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c new file mode 100644 index 0000000..298bbf7 --- /dev/null +++ b/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file tz_context.c + * @brief Context Management for Armv8-M TrustZone - Sample implementation + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h b/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h new file mode 100644 index 0000000..b2ccb1f --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h @@ -0,0 +1,544 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1)) + #define __ARM_ARCH_7A__ 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __forceinline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __wfi + +/** + \brief Wait For Event + */ +#define __WFE __wfe + +/** + \brief Send Event + */ +#define __SEV __sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + +/** + \brief Rotate Right in unsigned value (32 bit) + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + +/* ########################### Core Function Access ########################### */ + +/** + \brief Get FPSCR (Floating Point Status/Control) + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + +/** + \brief Set FPSCR (Floating Point Status/Control) + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +/** \brief Get CPSR (Current Program Status Register) + \return CPSR Register value + */ +__STATIC_INLINE uint32_t __get_CPSR(void) +{ + register uint32_t __regCPSR __ASM("cpsr"); + return(__regCPSR); +} + + +/** \brief Set CPSR (Current Program Status Register) + \param [in] cpsr CPSR value to set + */ +__STATIC_INLINE void __set_CPSR(uint32_t cpsr) +{ + register uint32_t __regCPSR __ASM("cpsr"); + __regCPSR = cpsr; +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_INLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_INLINE __ASM void __set_mode(uint32_t mode) +{ + MOV r1, lr + MSR CPSR_C, r0 + BX r1 +} + +/** \brief Get Stack Pointer + \return Stack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP(void) +{ + MOV r0, sp + BX lr +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP(uint32_t stack) +{ + MOV sp, r0 + BX lr +} + + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYSStack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP_usr(void) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV R0, SP + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV SP, R0 + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Get FPEXC (Floating Point Exception Control Register) + \return Floating Point Exception Control Register value + */ +__STATIC_INLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + return(__regfpexc); +#else + return(0); +#endif +} + +/** \brief Set FPEXC (Floating Point Exception Control Register) + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + __regfpexc = (fpexc); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) +#define __get_CP64(cp, op1, Rt, CRm) \ + do { \ + uint32_t ltmp, htmp; \ + __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \ + } while(0) + +#define __set_CP64(cp, op1, Rt, CRm) \ + do { \ + const uint64_t tmp = (Rt); \ + const uint32_t ltmp = (uint32_t)(tmp); \ + const uint32_t htmp = (uint32_t)(tmp >> 32U); \ + __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + } while(0) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE __ASM void __FPU_Enable(void) +{ + ARM + + //Permit access to VFP/NEON, registers by modifying CPACR + MRC p15,0,R1,c1,c0,2 + ORR R1,R1,#0x00F00000 + MCR p15,0,R1,c1,c0,2 + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + ISB + + //Enable VFP/NEON + VMRS R1,FPEXC + ORR R1,R1,#0x40000000 + VMSR FPEXC,R1 + + //Initialise VFP/NEON registers to 0 + MOV R2,#0 + + //Initialise D16 registers to 0 + VMOV D0, R2,R2 + VMOV D1, R2,R2 + VMOV D2, R2,R2 + VMOV D3, R2,R2 + VMOV D4, R2,R2 + VMOV D5, R2,R2 + VMOV D6, R2,R2 + VMOV D7, R2,R2 + VMOV D8, R2,R2 + VMOV D9, R2,R2 + VMOV D10,R2,R2 + VMOV D11,R2,R2 + VMOV D12,R2,R2 + VMOV D13,R2,R2 + VMOV D14,R2,R2 + VMOV D15,R2,R2 + + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 + //Initialise D32 registers to 0 + VMOV D16,R2,R2 + VMOV D17,R2,R2 + VMOV D18,R2,R2 + VMOV D19,R2,R2 + VMOV D20,R2,R2 + VMOV D21,R2,R2 + VMOV D22,R2,R2 + VMOV D23,R2,R2 + VMOV D24,R2,R2 + VMOV D25,R2,R2 + VMOV D26,R2,R2 + VMOV D27,R2,R2 + VMOV D28,R2,R2 + VMOV D29,R2,R2 + VMOV D30,R2,R2 + VMOV D31,R2,R2 + ENDIF + + //Initialise FPSCR to a known state + VMRS R2,FPSCR + LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R2,R2,R3 + VMSR FPSCR,R2 + + BX LR +} + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h b/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h new file mode 100644 index 0000000..e0de5a4 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h @@ -0,0 +1,503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __builtin_arm_wfi + +/** + \brief Wait For Event + */ +#define __WFE __builtin_arm_wfe + +/** + \brief Send Event + */ +#define __SEV __builtin_arm_sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() do {\ + __schedule_barrier();\ + __builtin_arm_isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() do {\ + __schedule_barrier();\ + __builtin_arm_dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + */ +#define __DMB() do {\ + __schedule_barrier();\ + __builtin_arm_dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/* ########################### Core Function Access ########################### */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP() +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr() +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if __ARM_NEON == 1 + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R2,FPSCR \n" + " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R2,R2,R3 \n" + " VMSR FPSCR,R2 " + ); +} + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h b/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h new file mode 100644 index 0000000..cd14cbc --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h @@ -0,0 +1,201 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include "cmsis_iccarm.h" + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef CMSIS_DEPRECATED + #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored. + #define CMSIS_DEPRECATED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h b/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h new file mode 100644 index 0000000..75e57b8 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h @@ -0,0 +1,514 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.1 + * @date 07. Sep 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] actlr Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) +{ + __set_CP(15, 0, actlr, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] cpacr Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) +{ + __set_CP(15, 0, cpacr, 1, 0, 2); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] dfsr Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) +{ + __set_CP(15, 0, dfsr, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] ifsr Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) +{ + __set_CP(15, 0, ifsr, 5, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) +{ + __set_CP(15, 0, ttbr0, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) +{ + __set_CP(15, 0, dacr, 3, 0, 0); +} + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get SCTLR + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set ACTRL + \param [in] actrl Auxiliary Control Register value to set + */ +__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) +{ + __set_CP(15, 0, actrl, 1, 0, 1); +} + +/** \brief Get ACTRL + \return Auxiliary Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTRL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] mvbar Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) +{ + __set_CP(15, 0, mvbar, 12, 0, 1); +} + +#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ + defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0 , 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +#endif + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ +// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Set CCSIDR + \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. + */ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) +{ + __set_CSSELR(value); +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 14, 2); +} + +#endif diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h b/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h new file mode 100644 index 0000000..fb1442c --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h @@ -0,0 +1,679 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + */ +#define __WFI() __ASM volatile ("wfi") + +/** + \brief Wait For Event + */ +#define __WFE() __ASM volatile ("wfe") + +/** + \brief Send Event + */ +#define __SEV() __ASM volatile ("sev") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value)); + return result; +} +#endif + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value +*/ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_get_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); + #else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); + #endif + #else + return(0U); + #endif +} + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set +*/ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_set_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); + #else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + #endif + #else + (void)fpscr; + #endif +} + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R2,FPSCR \n" + " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R2,R2,R3 \n" + " VMSR FPSCR,R2 " + ); +} + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h b/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h new file mode 100644 index 0000000..c46c397 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h @@ -0,0 +1,559 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.6 + * @date 02. March 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#pragma language=extended + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_7A__ +/* Macro already defined */ +#else + #if defined(__ARM7A__) + #define __ARM_ARCH_7A__ 1 + #endif +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif + +#ifndef __UNALIGNED_UINT16_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint16_t __iar_uint16_read(void const *ptr) + { + return *(__packed uint16_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) + { + *(__packed uint16_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint32_t __iar_uint32_read(void const *ptr) + { + return *(__packed uint32_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) + { + *(__packed uint32_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#if 0 +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma language=save + #pragma language=extended + __packed struct __iar_u32 { uint32_t v; }; + #pragma language=restore + #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __enable_irq __iar_builtin_enable_interrupt + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + #if __FPU_PRESENT + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #else + #define __get_FPSCR() ( 0 ) + #endif + + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE)) + + #define __get_CPSR() (__arm_rsr("CPSR")) + #define __get_mode() (__get_CPSR() & 0x1FU) + + #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) + #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) + + + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) + + #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + + #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) + + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #define __SSAT __iar_builtin_SSAT + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #define __USAT __iar_builtin_USAT + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if !__FPU_PRESENT + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if !__FPU_PRESENT + #define __get_FPSCR() (0) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + __IAR_FT void __set_mode(uint32_t mode) + { + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); + } + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + __IAR_FT uint32_t __get_FPEXC(void) + { + #if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); + #else + return(0); + #endif + } + + __IAR_FT void __set_FPEXC(uint32_t fpexc) + { + #if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); + #endif + } + + + #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) + #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + + +__IAR_FT uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); + return result; +} + +__IAR_FT void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); +} + +#define __get_mode() (__get_CPSR() & 0x1FU) + +__STATIC_INLINE +void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#ifdef __ARM_ADVANCED_SIMD__ + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R2,FPSCR \n" + " MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R2,R2,R3 \n" + " VMSR FPSCR,R2 \n"); +} + + + +#undef __IAR_FT +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Core_A/Include/core_ca.h b/Drivers/CMSIS/Core_A/Include/core_ca.h new file mode 100644 index 0000000..c7b451f --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/core_ca.h @@ -0,0 +1,2614 @@ +/**************************************************************************//** + * @file core_ca.h + * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 07. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CA_H_GENERIC +#define __CORE_CA_H_GENERIC + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +/* CMSIS CA definitions */ +#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA_H_DEPENDANT +#define __CORE_CA_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA_REV + #define __CA_REV 0x0000U + #warning "__CA_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TIM_PRESENT + #define __TIM_PRESENT 1U + #warning "__TIM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L2C_PRESENT + #define __L2C_PRESENT 0U + #warning "__L2C_PRESENT not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< \brief Defines 'read only' permissions */ +#else + #define __I volatile const /*!< \brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< \brief Defines 'write only' permissions */ +#define __IO volatile /*!< \brief Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ +#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ +#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + - L2C-310 Cache Controller + - Generic Interrupt Controller Distributor + - Generic Interrupt Controller Interface + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(0:4, uint32_t) + uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< \brief bit: 0 MMU enable */ + uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint32_t C:1; /*!< \brief bit: 2 Cache enable */ + RESERVED(0:2, uint32_t) + uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ + RESERVED(1:1, uint32_t) + uint32_t B:1; /*!< \brief bit: 7 Endianness model */ + RESERVED(2:2, uint32_t) + uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ + uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ + RESERVED(3:2, uint32_t) + uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ + RESERVED(4:1, uint32_t) + uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< \brief bit: 22 Alignment model */ + RESERVED(5:1, uint32_t) + uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(6:1, uint32_t) + uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ + uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ + RESERVED(7:1, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ +#if __CORTEX_A == 5 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A5 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:5, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + RESERVED(1:2, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ + uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ + uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ + uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ + RESERVED(3:9, uint32_t) + uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 7 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A7 */ + struct + { + RESERVED(0:6, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + RESERVED(1:3, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + RESERVED(3:12, uint32_t) + uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 9 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A9 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:1, uint32_t) + uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ + uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ + RESERVED(1:2, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ + uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ + RESERVED(7:22, uint32_t) + } b; +#endif + uint32_t w; /*!< \brief Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ + +#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ +#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ + +#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ +#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ + +#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ +#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ + +#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ +#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ + +#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ +#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ + +#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ +#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ + +#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ +#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ + +#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ +#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ + +#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ +#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ + +#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ + +#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ +#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ + +#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ +#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ + +#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ +#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ + uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ + uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ + uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ + uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ + uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ + uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ + uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ + uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ + uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ + uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ + uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + RESERVED(0:1, uint32_t) + uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ +#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ + +#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ +#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ +#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ + RESERVED(0:1, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(1:18, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:1, uint32_t) + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(2:18, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ + +#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ +#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ + +#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ + +#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ +#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + RESERVED(0:5, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + RESERVED(1:1, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:2, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ + +#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ +#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ + +#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ + +#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ +#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ + +/* CP15 Register ISR */ +typedef union +{ + struct + { + RESERVED(0:6, uint32_t) + uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ + RESERVED(1:23, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< \brief ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< \brief ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< \brief ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ + +/* DACR Register */ +#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ +#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ +#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ +#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ +#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param [in] field Name of the register bit field. + \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param [in] field Name of the register bit field. + \param [in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + + +/** + \brief Union type to access the L2C_310 Cache Controller. +*/ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +typedef struct +{ + __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ + __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ + RESERVED(0[0x3e], uint32_t) + __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ + __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ + RESERVED(1[0x3e], uint32_t) + __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ + __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ + __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ + RESERVED(2[0x2], uint32_t) + __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ + __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ + __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ + __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ + RESERVED(3[0x143], uint32_t) + __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ + RESERVED(4[0xf], uint32_t) + __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ + RESERVED(6[2], uint32_t) + __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ + RESERVED(5[0xc], uint32_t) + __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ + RESERVED(7[1], uint32_t) + __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ + __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ + RESERVED(8[0xc], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ + RESERVED(9[1], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ + __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ + RESERVED(10[0x40], uint32_t) + __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ + __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ + __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ + __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ + __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ + __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ + __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ + __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ + __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ + __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ + __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ + __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ + RESERVED(11[0x4], uint32_t) + __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ + __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ + RESERVED(12[0xaa], uint32_t) + __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ + __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ + RESERVED(13[0xce], uint32_t) + __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ +} L2C_310_TypeDef; + +#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ +#endif + +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5236], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ +#endif + +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Structure type to access the Private Timer +*/ +typedef struct +{ + __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register + __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register + __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register + __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register + RESERVED(0[4], uint32_t) + __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register + __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register + __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register + __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register + __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register + __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register +} Timer_Type; +#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ +#endif +#endif + + /******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - L1 Cache Functions + - L2C-310 Cache Controller Functions + - PL1 Timer Functions + - GIC Functions + - MMU Functions + ******************************************************************************/ + +/* ########################## L1 Cache functions ################################# */ + +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); + __ISB(); +} + +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); + __ISB(); +} + +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); + __ISB(); +} + +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); + __ISB(); +} + +/** \brief Invalidate entire branch predictor array +*/ +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { + __set_BPIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + +/** \brief Invalidate the whole instruction cache +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { + __set_ICIALLU(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Clean data cache line by address. +* \param [in] va Pointer to data to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { + __set_DCCMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Invalidate data cache line by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { + __set_DCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Clean and Invalidate data cache by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { + __set_DCCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Calculate log2 rounded up +* - log(0) => 0 +* - log(1) => 0 +* - log(2) => 1 +* - log(3) => 2 +* - log(4) => 2 +* - log(5) => 3 +* : : +* - log(16) => 4 +* - log(32) => 5 +* : : +* \param [in] n input value parameter +* \return log2(n) +*/ +__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) +{ + if (n < 2U) { + return 0U; + } + uint8_t log = 0U; + uint32_t t = n; + while(t > 1U) + { + log++; + t >>= 1U; + } + if (n & 1U) { log++; } + return log; +} + +/** \brief Apply cache maintenance to given cache level. +* \param [in] level cache level to be maintained +* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + uint32_t Dummy; + uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + int32_t log2_num_ways; + + Dummy = level << 1U; + /* set csselr, select ccsidr register */ + __set_CSSELR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; + num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; + log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; + log2_num_ways = __log2_up(num_ways); + if ((log2_num_ways < 0) || (log2_num_ways > 32)) { + return; // FATAL ERROR + } + shift_way = 32U - (uint32_t)log2_num_ways; + for(int32_t way = num_ways-1; way >= 0; way--) + { + for(int32_t set = num_sets-1; set >= 0; set--) + { + Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); + switch (maint) + { + case 0U: __set_DCISW(Dummy); break; + case 1U: __set_DCCSW(Dummy); break; + default: __set_DCCISW(Dummy); break; + } + } + } + __DMB(); +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { + uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0U; i<7U; i++) + { + cache_type = (clidr >> i*3U) & 0x7UL; + if ((cache_type >= 2U) && (cache_type <= 4U)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +* \deprecated Use generic L1C_CleanInvalidateCache instead. +*/ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { + L1C_CleanInvalidateCache(op); +} + +/** \brief Invalidate the whole data cache. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(0); +} + +/** \brief Clean the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { + L1C_CleanInvalidateCache(1); +} + +/** \brief Clean and invalidate the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(2); +} + +/* ########################## L2 Cache functions ################################# */ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +/** \brief Cache Sync operation by writing CACHE_SYNC register. +*/ +__STATIC_INLINE void L2C_Sync(void) +{ + L2C_310->CACHE_SYNC = 0x0; +} + +/** \brief Read cache controller cache ID from CACHE_ID register. + * \return L2C_310_TypeDef::CACHE_ID + */ +__STATIC_INLINE int L2C_GetID (void) +{ + return L2C_310->CACHE_ID; +} + +/** \brief Read cache controller cache type from CACHE_TYPE register. +* \return L2C_310_TypeDef::CACHE_TYPE +*/ +__STATIC_INLINE int L2C_GetType (void) +{ + return L2C_310->CACHE_TYPE; +} + +/** \brief Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_InvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->INV_WAY = (1U << assoc) - 1U; + while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Clean and Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Enable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Enable(void) +{ + L2C_310->CONTROL = 0; + L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; + L2C_310->DEBUG_CONTROL = 0; + L2C_310->DATA_LOCK_0_WAY = 0; + L2C_310->CACHE_SYNC = 0; + L2C_310->CONTROL = 0x01; + L2C_Sync(); +} + +/** \brief Disable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Disable(void) +{ + L2C_310->CONTROL = 0x00; + L2C_Sync(); +} + +/** \brief Invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_InvPa (void *pa) +{ + L2C_310->INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanPa (void *pa) +{ + L2C_310->CLEAN_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean and invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanInvPa (void *pa) +{ + L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} +#endif + +/* ########################## GIC functions ###################################### */ +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Enable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_EnableDistributor(void) +{ + GICDistributor->CTLR |= 1U; +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the GIC's ITARGETSR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return GICDistributor_Type::ITARGETSR +*/ +__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16U) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; + uint32_t shift = (IRQn % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt using GIC's SGIR register. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +* \param [in] filter_list Filter to be applied to determine interrupt receivers. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + for (i = 32U; i < num_irq; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + //Set target list to CPU0 + GIC_SetTarget((IRQn_Type)i, 1U); + } + //Enable distributor + GIC_EnableDistributor(); +} + +/** \brief Initialize the CPU's interrupt interface +*/ +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if(i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +#endif + +/* ########################## Generic Timer functions ############################ */ +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) + +/* PL1 Physical Timer */ +#if (__CORTEX_A == 7U) || defined(DOXYGEN) + +/** \brief Physical Timer Control register */ +typedef union +{ + struct + { + uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ + uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ + uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ + RESERVED(0:29, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CNTP_CTL_Type; + +/** \brief Configures the frequency the timer shall run at. +* \param [in] value The timer frequency in Hz. +*/ +__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) +{ + __set_CNTFRQ(value); + __ISB(); +} + +/** \brief Sets the reset value of the timer. +* \param [in] value The value the timer is loaded with. +*/ +__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) +{ + __set_CNTP_TVAL(value); + __ISB(); +} + +/** \brief Get the current counter value. +* \return Current counter value. +*/ +__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) +{ + return(__get_CNTP_TVAL()); +} + +/** \brief Get the current physical counter value. +* \return Current physical counter value. +*/ +__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) +{ + return(__get_CNTPCT()); +} + +/** \brief Set the physical compare value. +* \param [in] value New physical timer compare value. +*/ +__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) +{ + __set_CNTP_CVAL(value); + __ISB(); +} + +/** \brief Get the physical compare value. +* \return Physical compare value. +*/ +__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) +{ + return(__get_CNTP_CVAL()); +} + +/** \brief Configure the timer by setting the control value. +* \param [in] value New timer control value. +*/ +__STATIC_INLINE void PL1_SetControl(uint32_t value) +{ + __set_CNTP_CTL(value); + __ISB(); +} + +/** \brief Get the control value. +* \return Control value. +*/ +__STATIC_INLINE uint32_t PL1_GetControl(void) +{ + return(__get_CNTP_CTL()); +} +#endif + +/* Private Timer */ +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Set the load value to timers LOAD register. +* \param [in] value The load value to be set. +*/ +__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) +{ + PTIM->LOAD = value; +} + +/** \brief Get the load value from timers LOAD register. +* \return Timer_Type::LOAD +*/ +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) +{ + return(PTIM->LOAD); +} + +/** \brief Set current counter value from its COUNTER register. +*/ +__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) +{ + PTIM->COUNTER = value; +} + +/** \brief Get current counter value from timers COUNTER register. +* \result Timer_Type::COUNTER +*/ +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) +{ + return(PTIM->COUNTER); +} + +/** \brief Configure the timer using its CONTROL register. +* \param [in] value The new configuration value to be set. +*/ +__STATIC_INLINE void PTIM_SetControl(uint32_t value) +{ + PTIM->CONTROL = value; +} + +/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. +* \return Timer_Type::CONTROL +*/ +__STATIC_INLINE uint32_t PTIM_GetControl(void) +{ + return(PTIM->CONTROL); +} + +/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. +* \return 0 - flag is not set, 1- flag is set +*/ +__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) +{ + return (PTIM->ISR & 1UL); +} + +/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. +*/ +__STATIC_INLINE void PTIM_ClearEventFlag(void) +{ + PTIM->ISR = 1; +} +#endif +#endif + +/* ########################## MMU functions ###################################### */ + +#define SECTION_DESCRIPTOR (0x2) +#define SECTION_MASK (0xFFFFFFFC) + +#define SECTION_TEXCB_MASK (0xFFFF8FF3) +#define SECTION_B_SHIFT (2) +#define SECTION_C_SHIFT (3) +#define SECTION_TEX0_SHIFT (12) +#define SECTION_TEX1_SHIFT (13) +#define SECTION_TEX2_SHIFT (14) + +#define SECTION_XN_MASK (0xFFFFFFEF) +#define SECTION_XN_SHIFT (4) + +#define SECTION_DOMAIN_MASK (0xFFFFFE1F) +#define SECTION_DOMAIN_SHIFT (5) + +#define SECTION_P_MASK (0xFFFFFDFF) +#define SECTION_P_SHIFT (9) + +#define SECTION_AP_MASK (0xFFFF73FF) +#define SECTION_AP_SHIFT (10) +#define SECTION_AP2_SHIFT (15) + +#define SECTION_S_MASK (0xFFFEFFFF) +#define SECTION_S_SHIFT (16) + +#define SECTION_NG_MASK (0xFFFDFFFF) +#define SECTION_NG_SHIFT (17) + +#define SECTION_NS_MASK (0xFFF7FFFF) +#define SECTION_NS_SHIFT (19) + +#define PAGE_L1_DESCRIPTOR (0x1) +#define PAGE_L1_MASK (0xFFFFFFFC) + +#define PAGE_L2_4K_DESC (0x2) +#define PAGE_L2_4K_MASK (0xFFFFFFFD) + +#define PAGE_L2_64K_DESC (0x1) +#define PAGE_L2_64K_MASK (0xFFFFFFFC) + +#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) +#define PAGE_4K_B_SHIFT (2) +#define PAGE_4K_C_SHIFT (3) +#define PAGE_4K_TEX0_SHIFT (6) +#define PAGE_4K_TEX1_SHIFT (7) +#define PAGE_4K_TEX2_SHIFT (8) + +#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_64K_B_SHIFT (2) +#define PAGE_64K_C_SHIFT (3) +#define PAGE_64K_TEX0_SHIFT (12) +#define PAGE_64K_TEX1_SHIFT (13) +#define PAGE_64K_TEX2_SHIFT (14) + +#define PAGE_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_B_SHIFT (2) +#define PAGE_C_SHIFT (3) +#define PAGE_TEX_SHIFT (12) + +#define PAGE_XN_4K_MASK (0xFFFFFFFE) +#define PAGE_XN_4K_SHIFT (0) +#define PAGE_XN_64K_MASK (0xFFFF7FFF) +#define PAGE_XN_64K_SHIFT (15) + +#define PAGE_DOMAIN_MASK (0xFFFFFE1F) +#define PAGE_DOMAIN_SHIFT (5) + +#define PAGE_P_MASK (0xFFFFFDFF) +#define PAGE_P_SHIFT (9) + +#define PAGE_AP_MASK (0xFFFFFDCF) +#define PAGE_AP_SHIFT (4) +#define PAGE_AP2_SHIFT (9) + +#define PAGE_S_MASK (0xFFFFFBFF) +#define PAGE_S_SHIFT (10) + +#define PAGE_NG_MASK (0xFFFFF7FF) +#define PAGE_NG_SHIFT (11) + +#define PAGE_NS_MASK (0xFFFFFFF7) +#define PAGE_NS_SHIFT (3) + +#define OFFSET_1M (0x00100000) +#define OFFSET_64K (0x00010000) +#define OFFSET_4K (0x00001000) + +#define DESCRIPTOR_FAULT (0x00000000) + +/* Attributes enumerations */ + +/* Region size attributes */ +typedef enum +{ + SECTION, + PAGE_4k, + PAGE_64k, +} mmu_region_size_Type; + +/* Region type attributes */ +typedef enum +{ + NORMAL, + DEVICE, + SHARED_DEVICE, + NON_SHARED_DEVICE, + STRONGLY_ORDERED +} mmu_memory_Type; + +/* Region cacheability attributes */ +typedef enum +{ + NON_CACHEABLE, + WB_WA, + WT, + WB_NO_WA, +} mmu_cacheability_Type; + +/* Region parity check attributes */ +typedef enum +{ + ECC_DISABLED, + ECC_ENABLED, +} mmu_ecc_check_Type; + +/* Region execution attributes */ +typedef enum +{ + EXECUTE, + NON_EXECUTE, +} mmu_execute_Type; + +/* Region global attributes */ +typedef enum +{ + GLOBAL, + NON_GLOBAL, +} mmu_global_Type; + +/* Region shareability attributes */ +typedef enum +{ + NON_SHARED, + SHARED, +} mmu_shared_Type; + +/* Region security attributes */ +typedef enum +{ + SECURE, + NON_SECURE, +} mmu_secure_Type; + +/* Region access attributes */ +typedef enum +{ + NO_ACCESS, + RW, + READ, +} mmu_access_Type; + +/* Memory Region definition */ +typedef struct RegionStruct { + mmu_region_size_Type rg_t; + mmu_memory_Type mem_t; + uint8_t domain; + mmu_cacheability_Type inner_norm_t; + mmu_cacheability_Type outer_norm_t; + mmu_ecc_check_Type e_t; + mmu_execute_Type xn_t; + mmu_global_Type g_t; + mmu_secure_Type sec_t; + mmu_access_Type priv_t; + mmu_access_Type user_t; + mmu_shared_Type sh_t; + +} mmu_region_attributes_Type; + +//Following macros define the descriptors and attributes +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +/** \brief Set section execution-never attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. + + \return 0 +*/ +__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) +{ + *descriptor_l1 &= SECTION_XN_MASK; + *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); + return 0; +} + +/** \brief Set section domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Section domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= SECTION_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set section parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set section access privileges + + \param [out] descriptor_l1 L1 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l1 &= SECTION_AP_MASK; + *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; + *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; + + return 0; +} + +/** \brief Set section shareability + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) +{ + *descriptor_l1 &= SECTION_S_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); + return 0; +} + +/** \brief Set section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) +{ + *descriptor_l1 &= SECTION_NG_MASK; + *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); + return 0; +} + +/** \brief Set section Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= SECTION_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); + return 0; +} + +/* Page 4k or 64k */ +/** \brief Set 4k/64k page execution-never attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. + \param [in] page Page size: PAGE_4k, PAGE_64k, + + \return 0 +*/ +__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) +{ + if (page == PAGE_4k) + { + *descriptor_l2 &= PAGE_XN_4K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); + } + else + { + *descriptor_l2 &= PAGE_XN_64K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); + } + return 0; +} + +/** \brief Set 4k/64k page domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Page domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= PAGE_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page access privileges + + \param [out] descriptor_l2 L2 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l2 &= PAGE_AP_MASK; + *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; + *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; + + return 0; +} + +/** \brief Set 4k/64k page shareability + + \param [out] descriptor_l2 L2 descriptor. + \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) +{ + *descriptor_l2 &= PAGE_S_MASK; + *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Global attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) +{ + *descriptor_l2 &= PAGE_NG_MASK; + *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= PAGE_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); + return 0; +} + +/** \brief Set Section memory attributes + + \param [out] descriptor_l1 L1 descriptor. + \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 +*/ +__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) +{ + *descriptor_l1 &= SECTION_TEXCB_MASK; + + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); + break; + } + } + return 0; +} + +/** \brief Set 4k/64k page memory attributes + + \param [out] descriptor_l2 L2 descriptor. + \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] page Page size + + \return 0 +*/ +__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) +{ + *descriptor_l2 &= PAGE_4K_TEXCB_MASK; + + if (page == PAGE_64k) + { + //same as section + MMU_MemorySection(descriptor_l2, mem, outer, inner); + } + else + { + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); + break; + } + } + } + + return 0; +} + +/** \brief Create a L1 section descriptor + + \param [out] descriptor L1 descriptor + \param [in] reg Section attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + + MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); + MMU_XNSection(descriptor,reg.xn_t); + MMU_DomainSection(descriptor, reg.domain); + MMU_PSection(descriptor, reg.e_t); + MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1); + MMU_SharedSection(descriptor,reg.sh_t); + MMU_GlobalSection(descriptor,reg.g_t); + MMU_SecureSection(descriptor,reg.sec_t); + *descriptor &= SECTION_MASK; + *descriptor |= SECTION_DESCRIPTOR; + + return 0; +} + + +/** \brief Create a L1 and L2 4k/64k page descriptor + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg 4k/64k page attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + *descriptor2 = 0; + + switch (reg.rg_t) + { + case PAGE_4k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_4K_MASK; + *descriptor2 |= PAGE_L2_4K_DESC; + break; + + case PAGE_64k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_64K_MASK; + *descriptor2 |= PAGE_L2_64K_DESC; + break; + + case SECTION: + //error + break; + } + + return 0; +} + +/** \brief Create a 1MB Section + + \param [in] ttb Translation table base address + \param [in] base_address Section base address + \param [in] count Number of sections to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = base_address >> 20; + entry = (base_address & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +/** \brief Create a 4k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 4k base address + \param [in] count Number of 4k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i; + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFFF000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_4K; + } +} + +/** \brief Create a 64k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 64k base address + \param [in] count Number of 64k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i,j; + + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFF0000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //create 16 entries + for (j = 0; j < 16; j++) + { + //4 bytes aligned + *ttb_l2++ = entry2; + } + entry2 += OFFSET_64K; + } +} + +/** \brief Enable MMU +*/ +__STATIC_INLINE void MMU_Enable(void) +{ + // Set M bit 0 to enable the MMU + // Set AFE bit to enable simplified access permissions model + // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking + __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); + __ISB(); +} + +/** \brief Disable MMU +*/ +__STATIC_INLINE void MMU_Disable(void) +{ + // Clear M bit 0 to disable the MMU + __set_SCTLR( __get_SCTLR() & ~1); + __ISB(); +} + +/** \brief Invalidate entire unified TLB +*/ + +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ + __set_TLBIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core_A/Include/irq_ctrl.h b/Drivers/CMSIS/Core_A/Include/irq_ctrl.h new file mode 100644 index 0000000..a6d313d --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/irq_ctrl.h @@ -0,0 +1,186 @@ +/**************************************************************************//** + * @file irq_ctrl.h + * @brief Interrupt Controller API header file + * @version V1.0.0 + * @date 23. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef IRQ_CTRL_H_ +#define IRQ_CTRL_H_ + +#include + +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +/// Interrupt handler data type +typedef void (*IRQHandler_t) (void); +#endif + +#ifndef IRQN_ID_T +#define IRQN_ID_T +/// Interrupt ID number data type +typedef int32_t IRQn_ID_t; +#endif + +/* Interrupt mode bit-masks */ +#define IRQ_MODE_TRIG_Pos (0U) +#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) +#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt +#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt + +#define IRQ_MODE_TYPE_Pos (3U) +#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) +#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line +#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line + +#define IRQ_MODE_DOMAIN_Pos (4U) +#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) +#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain +#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain + +#define IRQ_MODE_CPU_Pos (5U) +#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) +#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs +#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 +#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 +#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 +#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 +#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 +#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 +#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 +#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 + +#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error + +/* Interrupt priority bit-masks */ +#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask +#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error + +/// Initialize interrupt controller. +/// \return 0 on success, -1 on error. +int32_t IRQ_Initialize (void); + +/// Register interrupt handler. +/// \param[in] irqn interrupt ID number +/// \param[in] handler interrupt handler function address +/// \return 0 on success, -1 on error. +int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); + +/// Get the registered interrupt handler. +/// \param[in] irqn interrupt ID number +/// \return registered interrupt handler function address. +IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); + +/// Enable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Enable (IRQn_ID_t irqn); + +/// Disable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Disable (IRQn_ID_t irqn); + +/// Get interrupt enable state. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is disabled, 1 - interrupt is enabled. +uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); + +/// Configure interrupt request mode. +/// \param[in] irqn interrupt ID number +/// \param[in] mode mode configuration +/// \return 0 on success, -1 on error. +int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); + +/// Get interrupt mode configuration. +/// \param[in] irqn interrupt ID number +/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. +uint32_t IRQ_GetMode (IRQn_ID_t irqn); + +/// Get ID number of current interrupt request (IRQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveIRQ (void); + +/// Get ID number of current fast interrupt request (FIQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveFIQ (void); + +/// Signal end of interrupt processing. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); + +/// Set interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPending (IRQn_ID_t irqn); + +/// Get interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is not pending, 1 - interrupt is pending. +uint32_t IRQ_GetPending (IRQn_ID_t irqn); + +/// Clear interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_ClearPending (IRQn_ID_t irqn); + +/// Set interrupt priority value. +/// \param[in] irqn interrupt ID number +/// \param[in] priority interrupt priority value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); + +/// Get interrupt priority. +/// \param[in] irqn interrupt ID number +/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriority (IRQn_ID_t irqn); + +/// Set priority masking threshold. +/// \param[in] priority priority masking threshold value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityMask (uint32_t priority); + +/// Get priority masking threshold +/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityMask (void); + +/// Set priority grouping field split point +/// \param[in] bits number of MSB bits included in the group priority field comparison +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityGroupBits (uint32_t bits); + +/// Get priority grouping field split point +/// \return current number of MSB bits included in the group priority field comparison with +/// optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityGroupBits (void); + +#endif // IRQ_CTRL_H_ diff --git a/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c b/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c new file mode 100644 index 0000000..cf08a53 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c @@ -0,0 +1,410 @@ +/**************************************************************************//** + * @file irq_ctrl_gic.c + * @brief Interrupt controller handling implementation for GIC + * @version V1.0.1 + * @date 9. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "irq_ctrl.h" + +#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U) + +/// Number of implemented interrupt lines +#ifndef IRQ_GIC_LINE_COUNT +#define IRQ_GIC_LINE_COUNT (1020U) +#endif + +static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U }; +static uint32_t IRQ_ID0; + +/// Initialize interrupt controller. +__WEAK int32_t IRQ_Initialize (void) { + uint32_t i; + + for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) { + IRQTable[i] = (IRQHandler_t)NULL; + } + GIC_Enable(); + return (0); +} + + +/// Register interrupt handler. +__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + IRQTable[irqn] = handler; + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get the registered interrupt handler. +__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) { + IRQHandler_t h; + + // Ignore CPUID field (software generated interrupts) + irqn &= 0x3FFU; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + h = IRQTable[irqn]; + } else { + h = (IRQHandler_t)0; + } + + return (h); +} + + +/// Enable interrupt. +__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EnableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Disable interrupt. +__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_DisableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt enable state. +__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) { + uint32_t enable; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + enable = GIC_GetEnableIRQ((IRQn_Type)irqn); + } else { + enable = 0U; + } + + return (enable); +} + + +/// Configure interrupt request mode. +__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) { + uint32_t val; + uint8_t cfg; + uint8_t secure; + uint8_t cpu; + int32_t status = 0; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + // Check triggering mode + val = (mode & IRQ_MODE_TRIG_Msk); + + if (val == IRQ_MODE_TRIG_LEVEL) { + cfg = 0x00U; + } else if (val == IRQ_MODE_TRIG_EDGE) { + cfg = 0x02U; + } else { + cfg = 0x00U; + status = -1; + } + + // Check interrupt type + val = mode & IRQ_MODE_TYPE_Msk; + + if (val != IRQ_MODE_TYPE_IRQ) { + status = -1; + } + + // Check interrupt domain + val = mode & IRQ_MODE_DOMAIN_Msk; + + if (val == IRQ_MODE_DOMAIN_NONSECURE) { + secure = 0U; + } else { + // Check security extensions support + val = GIC_DistributorInfo() & (1UL << 10U); + + if (val != 0U) { + // Security extensions are supported + secure = 1U; + } else { + secure = 0U; + status = -1; + } + } + + // Check interrupt CPU targets + val = mode & IRQ_MODE_CPU_Msk; + + if (val == IRQ_MODE_CPU_ALL) { + cpu = 0xFFU; + } else { + cpu = val >> IRQ_MODE_CPU_Pos; + } + + // Apply configuration if no mode error + if (status == 0) { + GIC_SetConfiguration((IRQn_Type)irqn, cfg); + GIC_SetTarget ((IRQn_Type)irqn, cpu); + + if (secure != 0U) { + GIC_SetGroup ((IRQn_Type)irqn, secure); + } + } + } + + return (status); +} + + +/// Get interrupt mode configuration. +__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) { + uint32_t mode; + uint32_t val; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + mode = IRQ_MODE_TYPE_IRQ; + + // Get trigger mode + val = GIC_GetConfiguration((IRQn_Type)irqn); + + if ((val & 2U) != 0U) { + // Corresponding interrupt is edge triggered + mode |= IRQ_MODE_TRIG_EDGE; + } else { + // Corresponding interrupt is level triggered + mode |= IRQ_MODE_TRIG_LEVEL; + } + + // Get interrupt CPU targets + mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos; + + } else { + mode = IRQ_MODE_ERROR; + } + + return (mode); +} + + +/// Get ID number of current interrupt request (IRQ). +__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) { + IRQn_ID_t irqn; + uint32_t prio; + + /* Dummy read to avoid GIC 390 errata 801120 */ + GIC_GetHighPendingIRQ(); + + irqn = GIC_AcknowledgePending(); + + __DSB(); + + /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */ + /* The following workaround code is for a single-core system. It would be */ + /* different in a multi-core system. */ + /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */ + /* so unlock it, otherwise service the interrupt as normal. */ + /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */ + /* so will not occur here. */ + + if ((irqn == 0) || (irqn >= 0x3FE)) { + /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */ + prio = GIC_GetPriority((IRQn_Type)0); + GIC_SetPriority ((IRQn_Type)0, prio); + + __DSB(); + + if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) { + /* If the ID is 0, is active and has not been seen before */ + IRQ_ID0 = 1U; + } + /* End of Workaround GIC 390 errata 733075 */ + } + + return (irqn); +} + + +/// Get ID number of current fast interrupt request (FIQ). +__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) { + return ((IRQn_ID_t)-1); +} + + +/// Signal end of interrupt processing. +__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) { + int32_t status; + IRQn_Type irq = (IRQn_Type)irqn; + + irqn &= 0x3FFU; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EndInterrupt (irq); + + if (irqn == 0) { + IRQ_ID0 = 0U; + } + + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt pending flag. +__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + +/// Get interrupt pending flag. +__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) { + uint32_t pending; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + pending = GIC_GetPendingIRQ ((IRQn_Type)irqn); + } else { + pending = 0U; + } + + return (pending & 1U); +} + + +/// Clear interrupt pending flag. +__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_ClearPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt priority value. +__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPriority ((IRQn_Type)irqn, priority); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt priority. +__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) { + uint32_t priority; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + priority = GIC_GetPriority ((IRQn_Type)irqn); + } else { + priority = IRQ_PRIORITY_ERROR; + } + + return (priority); +} + + +/// Set priority masking threshold. +__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) { + GIC_SetInterfacePriorityMask (priority); + return (0); +} + + +/// Get priority masking threshold +__WEAK uint32_t IRQ_GetPriorityMask (void) { + return GIC_GetInterfacePriorityMask(); +} + + +/// Set priority grouping field split point +__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) { + int32_t status; + + if (bits == IRQ_PRIORITY_Msk) { + bits = 7U; + } + + if (bits < 8U) { + GIC_SetBinaryPoint (7U - bits); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get priority grouping field split point +__WEAK uint32_t IRQ_GetPriorityGroupBits (void) { + uint32_t bp; + + bp = GIC_GetBinaryPoint() & 0x07U; + + return (7U - bp); +} + +#endif diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h new file mode 100644 index 0000000..effab26 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h @@ -0,0 +1,220 @@ +#ifndef _ARR_DESC_H_ +#define _ARR_DESC_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ +#include +#include /* memset() */ +#include "../util/util.h" /* CONCAT() */ + +/*--------------------------------------------------------------------------------*/ +/* Type Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * Array-descriptor struct. + */ +typedef struct ARR_DESC_struct +{ + void * data_ptr; /* Pointer to the array contents. */ + int32_t element_count; /* Number of current elements. */ + int32_t element_size; /* Size of current elements in bytes. */ + int32_t underlying_size; /* Size of underlying array in bytes. */ +} ARR_DESC_t; + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Prefix of the array variable's name when creating an array and an array + * descriptor at the same time. + */ +#define ARR_DESC_ARR_PREFIX ARR_DESC_ARR_ + +/** + * Evaluate to the array variable's name when creating an array and an array + * descriptor at the same time. + */ +#define ARR_DESC_ARR_NAME(name) \ + CONCAT(ARR_DESC_ARR_PREFIX, name) + +/** + * Define an #ARR_DESC_t by itself. + * + * @note The user must supply an array to store the data used by the + * #ARR_DESC_t. + */ +#define ARR_DESC_INTERNAL_DEFINE(name, data_ptr, \ + element_count, element_size) \ + ARR_DESC_t name = { \ + data_ptr, \ + element_count, \ + element_size, \ + element_count * element_size \ + } \ + +/** + * Define both an array and an #ARR_DESC_t that describes it. + * + * @note Use the #CURLY() macro for the content field; it provides the curly + * braces necessary for an array initialization. + */ +#define ARR_DESC_DEFINE(type, name, element_count, content) \ + type ARR_DESC_ARR_NAME(name)[element_count] = content; \ + ARR_DESC_INTERNAL_DEFINE(name, \ + &ARR_DESC_ARR_NAME(name), \ + element_count, \ + sizeof(type)) /* Note the lacking semicolon */ + +/** + * Create a #ARR_DESC_t which refers to a subset of the data in another. + * + * The new #ARR_DESC_t shares the same underlying array as the aliased + * #ARR_DESC_t, but only describes a subset of the originals values. + */ +#define ARR_DESC_DEFINE_SUBSET(name, original, element_cnt) \ + ARR_DESC_INTERNAL_DEFINE(name, \ + &ARR_DESC_ARR_NAME(original), \ + element_cnt, \ + sizeof(ARR_DESC_ARR_NAME(original)[0]) \ + ) /* Note the lacking semicolon */ + +/** + * Creat an #ARR_DESC_t which points to the data in an existing array. + * + * @param start_idx Offset in array_ptr of first element. + * @param element_cnt Number of elements to include in the #ARR_DESC_t. + * + * @example + * + * float my_floats[4] = {0.0f, 1.0f, 2.0f, 3.0f}; + * + * ARR_DESC_DEFINE_USING_ARR(my_arr_desc, my_floats, 1, 3); + * + * printf("Element 0: %f\n", ARR_DESC_ELT(float, 0, &my_arr_desc)); + * printf("Element 1: %f\n", ARR_DESC_ELT(float, 1, &my_arr_desc)); + * + * Outputs: + * + * Element 0: 1.000000 + * Element 1: 2.000000 + * + * @warning There are no checks in place to catch invalid start indices; This + * is left to the user. + */ +#define ARR_DESC_DEFINE_USING_ARR(type, name, array_ptr, start_idx, element_cnt) \ + ARR_DESC_INTERNAL_DEFINE( \ + name, \ + (type *) (array_ptr + start_idx), \ + element_cnt, \ + sizeof(type) \ + ) /* Note the lacking semicolon*/ + +/** + * Declare an #ARR_DESC_t object. + */ +#define ARR_DESC_DECLARE(name) \ + extern ARR_DESC_t name /* Note the lacking semicolon */ + +/** + * Evaluate to the number of bytes stored in the #ARR_DESC_t. + */ +#define ARR_DESC_BYTES(arr_desc_ptr) \ + ((arr_desc_ptr)->element_count * (arr_desc_ptr)->element_size) + +/** + * Set the contents of #ARR_DESC_t to value. + */ +#define ARR_DESC_MEMSET(arr_desc_ptr, value, bytes) \ + do \ + { \ + memset((arr_desc_ptr)->data_ptr, \ + value, \ + BOUND(0, \ + (arr_desc_ptr)->underlying_size, \ + bytes) \ + ); \ + } while (0) + +/** + * Perform a memcpy of 'bytes' bytes from the source #ARR_DESC_t to the + * destination #ARR_DESC_t. + */ +#define ARR_DESC_MEMCPY(arr_desc_dest_ptr, arr_desc_src_ptr, bytes) \ + do \ + { \ + memcpy((arr_desc_dest_ptr)->data_ptr, \ + (arr_desc_src_ptr)->data_ptr, \ + BOUND(0, \ + (arr_desc_dest_ptr)->underlying_size, \ + bytes)); \ + } while (0) + +/** + * Evaluate to true if the source #ARR_DESC_t contents will fit into the + * destination #ARR_DESC_t and false otherwise. + */ +#define ARR_DESC_COPYABLE(arr_desc_dest_ptr, arr_desc_src_ptr) \ + (ARR_DESC_BYTES(arr_desc_src_ptr) <= \ + (arr_desc_dest_ptr)->underlying_size) + +/** + * Copy all the data from the source #ARR_DESC_t to the destination + * #ARR_DESC_t. + * + * @note If the destination #ARR_DESC_t is too small to fit the source data the + * copy is aborted and nothing happens. + */ +#define ARR_DESC_COPY(arr_desc_dest_ptr, arr_desc_src_ptr) \ + do \ + { \ + if (ARR_DESC_COPYABLE(arr_desc_dest_ptr, \ + arr_desc_src_ptr)) \ + { \ + ARR_DESC_MEMCPY(arr_desc_dest_ptr, \ + arr_desc_src_ptr, \ + ARR_DESC_BYTES(arr_desc_src_ptr)); \ + /* Update the properties*/ \ + (arr_desc_dest_ptr)->element_count = \ + (arr_desc_src_ptr)->element_count; \ + (arr_desc_dest_ptr)->element_size = \ + (arr_desc_src_ptr)->element_size; \ + } \ + } while (0) + +/** + * Compare the data in two #ARR_DESC_t structs for the specified number of + * bytes. + */ +#define ARR_DESC_MEMCMP(arr_desc_ptr_a, arr_desc_ptr_b, bytes) \ + memcmp((arr_desc_ptr_a)->data_ptr, \ + (arr_desc_ptr_b)->data_ptr, \ + bytes) /* Note the lacking semicolon */ \ + +/** + * Zero out the contents of the #ARR_DESC_t. + */ +#define ARR_DESC_ZERO(arr_desc_ptr) \ + ARR_DESC_MEMSET(arr_desc_ptr, \ + 0, \ + (arr_desc_ptr)->underlying_size) + +/** + * Evaluate to the data address in #ARR_DESC_t at offset. + */ +#define ARR_DESC_DATA_ADDR(type, arr_desc_ptr, offset) \ + ((void*)(((type *) \ + ((arr_desc_ptr)->data_ptr)) \ + + offset)) + +/** + * Evaluate to the element in #ARR_DESC_t with type at idx. + */ +#define ARR_DESC_ELT(type, idx, arr_desc_ptr) \ + (*((type *) ARR_DESC_DATA_ADDR(type, \ + arr_desc_ptr, \ + idx))) + +#endif /* _ARR_DESC_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h new file mode 100644 index 0000000..9d0af06 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h @@ -0,0 +1,17 @@ +#ifndef _JTEST_H_ +#define _JTEST_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_fw.h" +#include "jtest_test.h" +#include "jtest_test_define.h" +#include "jtest_test_call.h" +#include "jtest_group.h" +#include "jtest_group_define.h" +#include "jtest_group_call.h" +#include "jtest_cycle.h" + +#endif /* _JTEST_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h new file mode 100644 index 0000000..1934af8 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h @@ -0,0 +1,65 @@ +#ifndef _JTEST_CYCLE_H_ +#define _JTEST_CYCLE_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_fw.h" /* JTEST_DUMP_STRF() */ +#include "jtest_systick.h" +#include "jtest_util.h" /* STR() */ + +/*--------------------------------------------------------------------------------*/ +/* Declare Module Variables */ +/*--------------------------------------------------------------------------------*/ +extern const char * JTEST_CYCLE_STRF; + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Wrap the function call, fn_call, to count execution cycles and display the + * results. + */ +/* skipp function name + param +#define JTEST_COUNT_CYCLES(fn_call) \ + do \ + { \ + uint32_t __jtest_cycle_end_count; \ + \ + JTEST_SYSTICK_RESET(SysTick); \ + JTEST_SYSTICK_START(SysTick); \ + \ + fn_call; \ + \ + __jtest_cycle_end_count = \ + JTEST_SYSTICK_VALUE(SysTick); \ + \ + JTEST_SYSTICK_RESET(SysTick); \ + JTEST_DUMP_STRF(JTEST_CYCLE_STRF, \ + STR(fn_call), \ + (JTEST_SYSTICK_INITIAL_VALUE - \ + __jtest_cycle_end_count)); \ + } while (0) +*/ +#define JTEST_COUNT_CYCLES(fn_call) \ + do \ + { \ + uint32_t __jtest_cycle_end_count; \ + \ + JTEST_SYSTICK_RESET(SysTick); \ + JTEST_SYSTICK_START(SysTick); \ + \ + fn_call; \ + \ + __jtest_cycle_end_count = \ + JTEST_SYSTICK_VALUE(SysTick); \ + \ + JTEST_SYSTICK_RESET(SysTick); \ + JTEST_DUMP_STRF(JTEST_CYCLE_STRF, \ + (JTEST_SYSTICK_INITIAL_VALUE - \ + __jtest_cycle_end_count)); \ + } while (0) + +#endif /* _JTEST_CYCLE_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h new file mode 100644 index 0000000..cbec329 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h @@ -0,0 +1,37 @@ +#ifndef _JTEST_DEFINE_H_ +#define _JTEST_DEFINE_H_ + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Makes a symbol for use as a struct name. Names made this way have two parts; + * the first parts is a prefix common to all structs of that class. The second + * is a specifier which differs for each instance of that struct type. + */ +#define JTEST_STRUCT_NAME(prefix, specifier) \ + CONCAT(prefix, specifier) + +/** + * Define a struct with type with a name generated by #JTEST_STRUCT_NAME(). + */ +#define JTEST_DEFINE_STRUCT(type, struct_name) \ + type struct_name + +/** + * Declare a struct with type with a name generated by #JTEST_STRUCT_NAME(). + */ +#define JTEST_DECLARE_STRUCT(struct_definition) \ + extern struct_definition + +/** + * Define and initialize a struct (created with JTEST_DEFINE_STRUCT()) and + * initialize it with init_values. + */ +#define JTEST_INIT_STRUCT(struct_definition, init_values) \ + struct_definition = { \ + init_values \ + } + +#endif /* _JTEST_DEFINE_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h new file mode 100644 index 0000000..13b015d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h @@ -0,0 +1,253 @@ +#ifndef _JTEST_FW_H_ +#define _JTEST_FW_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include /* int32_t */ +#include /* strcpy() */ +#include /* sprintf() */ +#include "jtest_pf.h" /* Extend JTEST_FW_t with Pass/Fail data */ +#include "jtest_group.h" + +/*--------------------------------------------------------------------------------*/ +/* Type Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * A struct used to interface with the Keil Debugger. + */ +typedef struct JTEST_FW_struct +{ + /* Action Triggers: The Keil debugger monitors these values for changes. In + * response to a change, the debugger executes code on the host. */ + volatile int32_t test_start; + volatile int32_t test_end; + volatile int32_t group_start; + volatile int32_t group_end; + volatile int32_t dump_str; + volatile int32_t dump_data; + volatile int32_t exit_fw; + + JTEST_GROUP_t * current_group_ptr; + + /* Buffers: The C-code cannot send strings and data directly to the + * debugging framework. Instead, the debugger can be told to read 128 byte + * (by default) chunks of memory. Data received in this manner requires + * post-processing to be legible.*/ + char * str_buffer; + char * data_buffer; + + /* Pass/Fail Data */ + JTEST_PF_MEMBERS; + +} JTEST_FW_t; + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Default name for the JTEST_FW struct. + * + * Define your own if you want the variable containing the #JTEST_FW_t to have + * a different name. + */ +#ifndef JTEST_FW +#define JTEST_FW JTEST_FW +#endif + +/** + * Default name for the JTEST_FW_STR_BUFFER. + * + * Define your own if you want the variable containing the char buffer to have + * a different name. + */ +#ifndef JTEST_FW_STR_BUFFER +#define JTEST_FW_STR_BUFFER JTEST_FW_STR_BUFFER +#endif + +/** + * Size of the #JTEST_FW_t, output string-buffer. + * + * If you change this value, make sure the "dump_str_fn" and "dump_data_fn" + * functions in jtest_fns.ini uses the same size. If you aren't sure, read the + * documentation Keil Debugger Command 'DISPLAY'. + */ +#define JTEST_BUF_SIZE 256 + + +/** + * The maximum number of bytes output at once using #JTEST_DUMP_STRF(). + */ +#define JTEST_STR_MAX_OUTPUT_SIZE 128 + +/** + * The maximum number of block transimissions needed to send a string from a + * buffer with JTEST_BUF_SIZE. + */ +#define JTEST_STR_MAX_OUTPUT_SEGMENTS \ + (JTEST_BUF_SIZE / JTEST_STR_MAX_OUTPUT_SIZE) + +/** + * Initialize the JTEST framework. + */ +#define JTEST_INIT() \ + do \ + { \ + JTEST_FW.str_buffer = JTEST_FW_STR_BUFFER; \ + } while (0) + +/* Debugger Action-triggering Macros */ +/*--------------------------------------------------------------------------------*/ + +/** + * Dispatch macro to trigger various actions in the Keil Debugger. + */ +#define JTEST_TRIGGER_ACTION(action_name) \ + do \ + { \ + action_name(); \ + } while (0) + +/** + * Trigger the "Test Start" action in the Keil Debugger. + */ +#define JTEST_ACT_TEST_START() \ + JTEST_TRIGGER_ACTION(test_start) + +/** + * Trigger the "Test End" action in the Keil Debugger. + */ +#define JTEST_ACT_TEST_END() \ + JTEST_TRIGGER_ACTION(test_end) + + +/** + * Trigger the "Group Start" action in the Keil Debugger. + */ +#define JTEST_ACT_GROUP_START() \ + JTEST_TRIGGER_ACTION(group_start) + +/** + * Trigger the "Group End" action in the Keil Debugger. + */ +#define JTEST_ACT_GROUP_END() \ + JTEST_TRIGGER_ACTION(group_end) + + +/** + * Fill the buffer named buf_name with value and dump it to the Keil debugger + * using action. + */ +#define JTEST_ACT_DUMP(action, buf_name, value) \ + do \ + { \ + JTEST_CLEAR_BUFFER(buf_name); \ + strcpy(JTEST_FW.buf_name, (value)); \ + JTEST_TRIGGER_ACTION(action); \ + } while (0) + +/** + * Trigger the "Exit Framework" action in the Keil Debugger. + */ +#define JTEST_ACT_EXIT_FW() \ + do \ + { \ + JTEST_TRIGGER_ACTION(exit_fw); \ + } while (0) + + +/* Buffer Manipulation Macros */ +/*--------------------------------------------------------------------------------*/ + +/** + * Clear the JTEST_FW buffer with name buf_name. + */ +#define JTEST_CLEAR_BUFFER(buf_name) \ + do \ + { \ + memset(JTEST_FW.buf_name, 0, JTEST_BUF_SIZE); \ + } while (0) + +/** + * Clear the memory needed for the JTEST_FW's string buffer. + */ +#define JTEST_CLEAR_STR_BUFFER() \ + JTEST_CLEAR_BUFFER(str_buffer) + +/** + * Clear the memory needed for the JTEST_FW's data buffer. + */ +#define JTEST_CLEAR_DATA_BUFFER() \ + JTEST_CLEAR_BUFFER(data_buffer) + +/** + * Dump the given string to the Keil Debugger. + */ +#define JTEST_DUMP_STR(string) \ + JTEST_ACT_DUMP(dump_str, str_buffer, string) + +/** + * Dump a formatted string to the Keil Debugger. + */ +#define JTEST_DUMP_STRF(format_str, ... ) \ + do \ + { \ + JTEST_CLEAR_STR_BUFFER(); \ + sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__); \ + jtest_dump_str_segments(); \ + } while (0) + +/* Pass/Fail Macros */ +/*--------------------------------------------------------------------------------*/ + +/** + * Increment the number of passed tests in #JTEST_FW. + */ +#define JTEST_FW_INC_PASSED(amount) \ + JTEST_PF_INC_PASSED(&JTEST_FW, amount) + +/** + * Increment the number of passed tests in #JTEST_FW. + */ +#define JTEST_FW_INC_FAILED(amount) \ + JTEST_PF_INC_FAILED(&JTEST_FW, amount) + +/* Manipulating the Current Group */ +/*--------------------------------------------------------------------------------*/ + +/** + * Evaluate to the current_group_ptr in #JTEST_FW. + */ +#define JTEST_CURRENT_GROUP_PTR() \ + (JTEST_FW.current_group_ptr) + +#define JTEST_SET_CURRENT_GROUP(group_ptr) \ + do \ + { \ + JTEST_CURRENT_GROUP_PTR() = group_ptr; \ + } while (0) + +/*--------------------------------------------------------------------------------*/ +/* Declare Global Variables */ +/*--------------------------------------------------------------------------------*/ +extern char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE]; +extern volatile JTEST_FW_t JTEST_FW; + +/*--------------------------------------------------------------------------------*/ +/* Function Prototypes */ +/*--------------------------------------------------------------------------------*/ +void jtest_dump_str_segments(void); + +void test_start (void); +void test_end (void); +void group_start (void); +void group_end (void); +void dump_str (void); +void dump_data (void); +void exit_fw (void); + + +#endif /* _JTEST_FW_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h new file mode 100644 index 0000000..3b37ae4 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h @@ -0,0 +1,66 @@ +#ifndef _JTEST_GROUP_H_ +#define _JTEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_pf.h" +#include "jtest_util.h" + +/*--------------------------------------------------------------------------------*/ +/* Type Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * A struct which represents a group of #JTEST_TEST_t structs. This struct is + * used to run the group of tests, and report on their outcomes. + */ +typedef struct JTEST_GROUP_struct +{ + void (* group_fn_ptr) (void); /**< Pointer to the test group */ + char * name_str; /**< Name of the group */ + + /* Extend the #JTEST_GROUP_t with Pass/Fail information.*/ + JTEST_PF_MEMBERS; +} JTEST_GROUP_t; + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Set the name of JTEST_GROUP_t. + */ +#define JTEST_GROUP_SET_NAME(group_ptr, name) \ + JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, name_str, name) + +#define JTEST_GROUP_SET_FN(group_ptr, fn_ptr) \ + JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, group_fn_ptr, fn_ptr) + +/** + * Increment the number of tests passed in the JTEST_GROUP_t pointed to by + * group_ptr. + */ +#define JTEST_GROUP_INC_PASSED(group_ptr, amount) \ + JTEST_PF_INC_PASSED(group_ptr, amount) + +/** + * Increment the number of tests failed in the JTEST_GROUP_t pointed to by + * group_ptr. + */ +#define JTEST_GROUP_INC_FAILED(group_ptr, amount) \ + JTEST_PF_INC_FAILED(group_ptr, amount) + +/** + * Reset the pass/fail information of the #JTEST_GROUP_t pointed to by + * group_ptr. + */ +#define JTEST_GROUP_RESET_PF(group_ptr) \ + do \ + { \ + JTEST_PF_RESET_PASSED(group_ptr); \ + JTEST_PF_RESET_FAILED(group_ptr); \ + } while (0) + +#endif /* _JTEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h new file mode 100644 index 0000000..d565a4c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h @@ -0,0 +1,126 @@ +#ifndef _JTEST_GROUP_CALL_H_ +#define _JTEST_GROUP_CALL_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_fw.h" +#include + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Execute the test in the #JTEST_GROUP_t struct associated witht he identifier + * group_fn. + */ +#define JTEST_GROUP_RUN(group_fn) \ + do \ + { \ + JTEST_DUMP_STR("Group Name:\n"); \ + JTEST_DUMP_STR(JTEST_GROUP_STRUCT_NAME(group_fn).name_str); \ + JTEST_GROUP_STRUCT_NAME(group_fn).group_fn_ptr(); \ + } while (0) + + +/** + * Update the enclosing #JTEST_GROUP_t's pass/fail information using the + * current #JTEST_GROUP_t's. + * + * @param group_ptr Pointer to the current #JTEST_GROUP_t. + * @param parent_ptr Pointer to the enclosing #JTEST_GROUP_t. + * + * @warning Only run this if the current #JTEST_GROUP_t is being called within + * the context of another #JTEST_GROUP_t. + */ +#define JTEST_GROUP_UPDATE_PARENT_GROUP_PF(group_ptr, parent_group_ptr) \ + do \ + { \ + JTEST_GROUP_INC_PASSED(parent_group_ptr, \ + (group_ptr)->passed); \ + JTEST_GROUP_INC_FAILED(parent_group_ptr, \ + (group_ptr)->failed); \ + } while (0) + +/** + * Update the #JTEST_FW's pass/fail information using the current + * #JTEST_GROUP_t's. + */ +#define JTEST_GROUP_UPDATE_FW_PF(group_ptr) \ + do \ + { \ + JTEST_FW_INC_PASSED((group_ptr)->passed); \ + JTEST_FW_INC_FAILED((group_ptr)->failed); \ + } while (0) + +/** + * Update the enclosing context with the current #JTEST_GROUP_t's pass/fail + * information. If this group isn't in an enclosing group, it updates the + * #JTEST_FW's pass/fail info by default. + */ +#define JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF(group_ptr, \ + parent_group_ptr) \ + do \ + { \ + /* Update the pass fail counts in the parent group */ \ + if (parent_group_ptr /* Null implies Top*/) \ + { \ + JTEST_GROUP_UPDATE_PARENT_GROUP_PF( \ + group_ptr, \ + parent_group_ptr); \ + } else { \ + JTEST_GROUP_UPDATE_FW_PF( \ + group_ptr); \ + } \ + } while (0) + +/** + * Dump the results of running the #JTEST_GROUP_t to the Keil Debugger. + */ +#define JTEST_GROUP_DUMP_RESULTS(group_ptr) \ + do \ + { \ + JTEST_DUMP_STRF( \ + "Tests Run: %" PRIu32 "\n" \ + "----------\n" \ + " Passed: %" PRIu32 "\n" \ + " Failed: %" PRIu32 "\n", \ + (group_ptr)->passed + (group_ptr)->failed, \ + (group_ptr)->passed, \ + (group_ptr)->failed); \ + } while (0) + +/** + * Call the #JTEST_GROUP_t associated with the identifier group_fn. + */ +#define JTEST_GROUP_CALL(group_fn) \ + do \ + { /* Save the current group from JTEST_FW_t before swapping */ \ + /* it to this group (in order to restore it later )*/ \ + JTEST_GROUP_t * __jtest_temp_group_ptr = \ + JTEST_CURRENT_GROUP_PTR(); \ + JTEST_SET_CURRENT_GROUP(&JTEST_GROUP_STRUCT_NAME(group_fn)); \ + \ + /* Reset this group's pass/fail count. Each group */ \ + /* should only remember counts for its last execution. */ \ + JTEST_GROUP_RESET_PF(JTEST_CURRENT_GROUP_PTR()); \ + \ + /* Run the current group */ \ + JTEST_ACT_GROUP_START(); \ + JTEST_GROUP_RUN(group_fn); \ + JTEST_ACT_GROUP_END(); \ + \ + /* Update the pass fail counts in the parent group (or FW) */ \ + JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF( \ + JTEST_CURRENT_GROUP_PTR(), \ + __jtest_temp_group_ptr); \ + \ + JTEST_GROUP_DUMP_RESULTS(JTEST_CURRENT_GROUP_PTR()); \ + \ + /* Restore the previously current group */ \ + JTEST_SET_CURRENT_GROUP(__jtest_temp_group_ptr); \ + } while (0) + +#endif /* _JTEST_GROUP_CALL_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h new file mode 100644 index 0000000..b3a86c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h @@ -0,0 +1,87 @@ +#ifndef _JTEST_GROUP_DEFINE_H_ +#define _JTEST_GROUP_DEFINE_H_ + + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_util.h" +#include "jtest_define.h" +#include "jtest_group.h" + +/* For defining macros with optional arguments */ +#include "opt_arg/opt_arg.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Prefix for all #JTEST_GROUP_t structs. + */ +#define JTEST_GROUP_STRUCT_NAME_PREFIX G_JTEST_GROUP_STRUCT_ + +/** + * Define test template used by #JTEST_GROUP_t tests. + */ +#define JTEST_GROUP_FN_TEMPLATE(group_fn) \ + void group_fn(void) + +#define JTEST_GROUP_FN_PROTOTYPE JTEST_GROUP_FN_TEMPLATE /**< Alias for + #JTEST_GROUP_FN_TEMPLATE. */ + +/** + * Evaluate to the name of the #JTEST_GROUP_t struct associated with group_fn. + */ +#define JTEST_GROUP_STRUCT_NAME(group_fn) \ + JTEST_STRUCT_NAME(JTEST_GROUP_STRUCT_NAME_PREFIX, group_fn) + +/** + * Define a #JTEST_GROUP_t struct based on the given group_fn. + */ +#define JTEST_GROUP_DEFINE_STRUCT(group_fn) \ + JTEST_DEFINE_STRUCT(JTEST_GROUP_t, \ + JTEST_GROUP_STRUCT_NAME(group_fn)) + +/** + * Declare a #JTEST_GROUP_t struct based on the given group_fn. + */ +#define JTEST_GROUP_DECLARE_STRUCT(group_fn) \ + JTEST_DECLARE_STRUCT(JTEST_GROUP_DEFINE_STRUCT(group_fn)) + +/** + * Contents needed to initialize a JTEST_GROUP_t struct. + */ +#define JTEST_GROUP_STRUCT_INIT(group_fn) \ + group_fn, \ + STR_NL(group_fn), \ + JTEST_PF_MEMBER_INIT + +/** + * Initialize the contents of a #JTEST_GROUP_t struct. + */ +#define JTEST_GROUP_INIT(group_fn) \ + JTEST_GROUP_DEFINE_STRUCT(group_fn) = { \ + JTEST_GROUP_STRUCT_INIT(group_fn) \ + } + +/* Test Definition Macro */ +/*--------------------------------------------------------------------------------*/ + +/** + * Define a #JTEST_GROUP_t object and a test function. + */ +#define JTEST_DEFINE_GROUP(group_fn) \ + JTEST_GROUP_FN_PROTOTYPE(group_fn); \ + JTEST_GROUP_INIT(group_fn); \ + JTEST_GROUP_FN_PROTOTYPE(group_fn) /* Notice the lacking semicolon */ + +/** + * Declare a #JTEST_GROUP_t object and a test function prototype. + */ +#define JTEST_DECLARE_GROUP(group_fn) \ + JTEST_GROUP_FN_PROTOTYPE(group_fn); \ + JTEST_GROUP_DECLARE_STRUCT(group_fn) /* Note the lacking semicolon */ + +#endif /* _JTEST_GROUP_DEFINE_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h new file mode 100644 index 0000000..2b005b6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h @@ -0,0 +1,85 @@ +#ifndef _JTEST_PF_H_ +#define _JTEST_PF_H_ + +/*--------------------------------------------------------------------------------*/ +/* Purpose */ +/*--------------------------------------------------------------------------------*/ +/* jtest_pf.h Contains macros useful for capturing pass/fail data. */ + + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Members that can be added to other structs to extend them pass/fail data and + * corresponding functionality. + */ +#define JTEST_PF_MEMBERS \ + uint32_t passed; \ + uint32_t failed /* Note the lacking semicolon*/ \ + +/** + * Used for initializing JTEST_PF_MEMBERS in a struct declaration. + */ +#define JTEST_PF_MEMBER_INIT \ + 0, \ + 0 + +/* Member-Incrementing Macros */ +/*--------------------------------------------------------------------------------*/ + +/** + * Dispatch macro for incrementing #JTEST_PF_MEMBERS. + * + * @param xxx Values: 'passed', 'failed' + */ +#define JTEST_PF_INC_XXX(xxx, struct_pf_ptr, amount) \ + do \ + { \ + ((struct_pf_ptr)->xxx) += (amount); \ + } while (0) + +/** + * Specialization of the #JTEST_PF_INC_XXX macro to increment the passed + * member. + */ +#define JTEST_PF_INC_PASSED(struct_pf_ptr, amount) \ + JTEST_PF_INC_XXX(passed, struct_pf_ptr, amount) + + +/** + * Specialization of the #JTEST_PF_INC_XXX macro to increment the failed + * member. + */ +#define JTEST_PF_INC_FAILED(struct_pf_ptr, amount) \ + JTEST_PF_INC_XXX(failed, struct_pf_ptr, amount) + + +/* Member-Resetting Macros */ +/*--------------------------------------------------------------------------------*/ + +/** + * Dispatch macro for setting #JTEST_PF_MEMBERS to zero. + * + * @param xxx Values: 'passed', 'failed' + */ +#define JTEST_PF_RESET_XXX(xxx, struct_pf_ptr) \ + do \ + { \ + ((struct_pf_ptr)->xxx) = UINT32_C(0); \ + } while (0) + +/** + * Specialization of #JTEST_PF_RESET_XXX for the 'passed' member. + */ +#define JTEST_PF_RESET_PASSED(struct_pf_ptr) \ + JTEST_PF_RESET_XXX(passed, struct_pf_ptr) + +/** + * Specialization of #JTEST_PF_RESET_XXX for the 'failed' member. + */ +#define JTEST_PF_RESET_FAILED(struct_pf_ptr) \ + JTEST_PF_RESET_XXX(failed, struct_pf_ptr) + +#endif /* _JTEST_PF_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h new file mode 100644 index 0000000..339ecf2 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h @@ -0,0 +1,93 @@ +#ifndef _JTEST_SYSTICK_H_ +#define _JTEST_SYSTICK_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +/* Get access to the SysTick structure. */ +#if defined ARMCM0 + #include "ARMCM0.h" +#elif defined ARMCM0P + #include "ARMCM0plus.h" +#elif defined ARMCM3 + #include "ARMCM3.h" +#elif defined ARMCM4 + #include "ARMCM4.h" +#elif defined ARMCM4_FP + #include "ARMCM4_FP.h" +#elif defined ARMCM7 + #include "ARMCM7.h" +#elif defined ARMCM7_SP + #include "ARMCM7_SP.h" +#elif defined ARMCM7_DP + #include "ARMCM7_DP.h" +#elif defined ARMSC000 + #include "ARMSC000.h" +#elif defined ARMSC300 + #include "ARMSC300.h" +#elif defined ARMv8MBL + #include "ARMv8MBL.h" +#elif defined ARMv8MML + #include "ARMv8MML.h" +#elif defined ARMv8MML_DSP + #include "ARMv8MML_DSP.h" +#elif defined ARMv8MML_SP + #include "ARMv8MML_SP.h" +#elif defined ARMv8MML_DSP_SP + #include "ARMv8MML_DSP_SP.h" +#elif defined ARMv8MML_DP + #include "ARMv8MML_DP.h" +#elif defined ARMv8MML_DSP_DP + #include "ARMv8MML_DSP_DP.h" + +#else + #warning "no appropriate header file found!" +#endif + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Initial value for the SysTick module. + * + * @note This is also the maximum value, important as SysTick is a decrementing + * counter. + */ +#define JTEST_SYSTICK_INITIAL_VALUE 0xFFFFFF + +/** + * Reset the SysTick, decrementing timer to it's maximum value and disable it. + * + * This macro should leave the SysTick timer in a state that's ready for cycle + * counting. + */ +#define JTEST_SYSTICK_RESET(systick_ptr) \ + do \ + { \ + (systick_ptr)->LOAD = JTEST_SYSTICK_INITIAL_VALUE; \ + (systick_ptr)->VAL = 1; \ + \ + /* Disable the SysTick module. */ \ + (systick_ptr)->CTRL = UINT32_C(0x000000); \ + } while (0) + +/** + * Start the SysTick timer, sourced by the processor clock. + */ +#define JTEST_SYSTICK_START(systick_ptr) \ + do \ + { \ + (systick_ptr)->CTRL = \ + SysTick_CTRL_ENABLE_Msk | \ + SysTick_CTRL_CLKSOURCE_Msk; /* Internal clk*/ \ + } while (0) + +/** + * Evaluate to the current value of the SysTick timer. + */ +#define JTEST_SYSTICK_VALUE(systick_ptr) \ + ((systick_ptr)->VAL) + +#endif /* _JTEST_SYSTICK_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h new file mode 100644 index 0000000..023145f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h @@ -0,0 +1,100 @@ +#ifndef _JTEST_TEST_H_ +#define _JTEST_TEST_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include +#include "jtest_util.h" +#include "jtest_test_ret.h" + +/*--------------------------------------------------------------------------------*/ +/* Type Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * A struct which represents a Test in the JTEST framework. This struct is + * used to enable, run, and describe the test it represents. + */ +typedef struct JTEST_TEST_struct +{ + JTEST_TEST_RET_t ( * test_fn_ptr)(void); /**< Pointer to the test function. */ + char * test_fn_str; /**< Name of the test function */ + char * fut_str; /**< Name of the function under test. */ + + /** + * Flags that govern how the #JTEST_TEST_t behaves. + */ + union { + struct { + unsigned enabled : 1; + unsigned unused : 7; + } bits; + uint8_t byte; /* Access all flags at once. */ + } flags; + +} JTEST_TEST_t; + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Assign a test function to the #JTEST_TEST_t struct. + */ +#define JTEST_TEST_SET_FN(jtest_test_ptr, fn_ptr) \ + JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, test_fn_ptr, fn_ptr) + +/** + * Specify a function under test (FUT) for the #JTEST_TEST_t struct. + */ +#define JTEST_TEST_SET_FUT(jtest_test_ptr, str) \ + JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, fut_str, str) + +/* Macros concerning JTEST_TEST_t flags */ +/*--------------------------------------------------------------------------------*/ + +#define JTEST_TEST_FLAG_SET 1 /**< Value of a set #JTEST_TEST_t flag. */ +#define JTEST_TEST_FLAG_CLR 0 /**< Value of a cleared #JTEST_TEST_t flag. */ + +/** + * Evaluate to the flag in #JTEST_TEST_t having flag_name. + */ +#define JTEST_TEST_FLAG(jtest_test_ptr, flag_name) \ + ((jtest_test_ptr)->flags.bits.flag_name) + +/** + * Dispatch macro for setting and clearing #JTEST_TEST_t flags. + * + * @param jtest_test_ptr Pointer to a #JTEST_TEST_t struct. + * @param flag_name Name of the flag to set in #JTEST_TEST_t.flags.bits + * @param xxx Vaid values: "SET" or "CLR" + * + * @note This function depends on JTEST_TEST_FLAG_SET and JTEST_TEST_FLAG_CLR. + */ +#define JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, xxx) \ + do \ + { \ + JTEST_TEST_FLAG(jtest_test_ptr, flag_name) = JTEST_TEST_FLAG_##xxx ; \ + } while (0) + +/** + * Specification of #JTEST_TEST_XXX_FLAG to set #JTEST_TEST_t flags. + */ +#define JTEST_TEST_SET_FLAG(jtest_test_ptr, flag_name) \ + JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, SET) + +/** + * Specification of #JTEST_TEST_XXX_FLAG to clear #JTEST_TEST_t flags. + */ +#define JTEST_TEST_CLR_FLAG(jtest_test_ptr, flag_name) \ + JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, CLR) + +/** + * Evaluate to true if the #JTEST_TEST_t is enabled. + */ +#define JTEST_TEST_IS_ENABLED(jtest_test_ptr) \ + (JTEST_TEST_FLAG(jtest_test_ptr, enabled) == JTEST_TEST_FLAG_SET) + +#endif /* _JTEST_TEST_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h new file mode 100644 index 0000000..9325185 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h @@ -0,0 +1,121 @@ +#ifndef _JTEST_TEST_CALL_H_ +#define _JTEST_TEST_CALL_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ +#include "jtest_test.h" +#include "jtest_test_define.h" +#include "jtest_fw.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Exectute the test in the #JTEST_TEST_t struct associated with the identifier + * test_fn and store the result in retval. + */ +#define JTEST_TEST_RUN(retval, test_fn) \ + do \ + { \ + JTEST_DUMP_STR("Test Name:\n"); \ + JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).test_fn_str); \ + JTEST_DUMP_STR("Function Under Test:\n"); \ + JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).fut_str); \ + retval = JTEST_TEST_STRUCT_NAME(test_fn).test_fn_ptr(); \ + } while (0) + +/** + * Update the enclosing #JTEST_GROUP_t's pass/fail information based on + * test_retval. + * + * @param test_retval A #JTEST_TEST_RET_enum for the current test. + * + * @warning Only use if #JTEST_TEST_t is called in the context of a + * #JTEST_GROUP_t. + */ +#define JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval) \ + do \ + { \ + /* Update enclosing JTEST_GROUP_t with pass/fail info */ \ + if (test_retval == JTEST_TEST_PASSED) \ + { \ + JTEST_GROUP_INC_PASSED(JTEST_CURRENT_GROUP_PTR(), 1); \ + } else { \ + JTEST_GROUP_INC_FAILED(JTEST_CURRENT_GROUP_PTR(), 1); \ + } \ + } while (0) + +/** + * Update the #JTEST_FW with pass/fail information based on test_retval. + * + * @param test_retval A #JTEST_TEST_RET_enum for the current test. + */ +#define JTEST_TEST_UPDATE_FW_PF(test_retval) \ + do \ + { \ + /* Update the JTEST_FW with pass/fail info */ \ + if (test_retval == JTEST_TEST_PASSED) \ + { \ + JTEST_FW_INC_PASSED( 1); \ + } else { \ + JTEST_FW_INC_FAILED(1); \ + } \ + } while (0) + +/** + * Update the enclosing JTEST_GROUP_t's pass/fail information, or the + * #JTEST_FW's if this test has no enclosing #JTEST_GROUP_t. + * + * @param test_retval A #JTEST_TEST_RET_enum for the current test. + */ +#define JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(test_retval) \ + do \ + { \ + /* Update pass-fail information */ \ + if (JTEST_CURRENT_GROUP_PTR() /* Non-null */) \ + { \ + JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval); \ + } else { \ + JTEST_TEST_UPDATE_FW_PF(test_retval); \ + } \ + } while (0) + +/** + * Dump the results of the test to the Keil Debugger. + */ +#define JTEST_TEST_DUMP_RESULTS(test_retval) \ + do \ + { \ + if (test_retval == JTEST_TEST_PASSED) \ + { \ + JTEST_DUMP_STR("Test Passed\n"); \ + } else { \ + JTEST_DUMP_STR("Test Failed\n"); \ + } \ + } while (0) + +/** + * Call the #JTEST_TEST_t assocaited with the identifier test_fn. + */ +#define JTEST_TEST_CALL(test_fn) \ + do \ + { \ + if (JTEST_TEST_IS_ENABLED(&JTEST_TEST_STRUCT_NAME(test_fn))) \ + { \ + /* Default to failure */ \ + JTEST_TEST_RET_t __jtest_test_ret = JTEST_TEST_FAILED; \ + \ + JTEST_ACT_TEST_START(); \ + JTEST_TEST_RUN(__jtest_test_ret, test_fn); \ + \ + /* Update pass-fail information */ \ + JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(__jtest_test_ret); \ + \ + JTEST_TEST_DUMP_RESULTS(__jtest_test_ret); \ + JTEST_ACT_TEST_END(); \ + } \ + } while (0) + +#endif /* _JTEST_TEST_CALL_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h new file mode 100644 index 0000000..1447dd0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h @@ -0,0 +1,133 @@ +#ifndef _JTEST_TEST_DEFINE_H_ +#define _JTEST_TEST_DEFINE_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "jtest_util.h" +#include "jtest_define.h" +#include "jtest_test.h" + +/* For defining macros with optional arguments */ +#include "opt_arg/opt_arg.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Prefix for all #JTEST_TEST_t structs. + */ +#define JTEST_TEST_STRUCT_NAME_PREFIX G_JTEST_TEST_STRUCT_ + +/** + * Define test template used by #JTEST_TEST_t tests. + */ +#define JTEST_TEST_FN_TEMPLATE(test_fn) \ + JTEST_TEST_RET_t test_fn(void) + +#define JTEST_TEST_FN_PROTOTYPE JTEST_TEST_FN_TEMPLATE /**< Alias for + * #JTEST_TEST_FN_TEMPLATE. */ + +/** + * Evaluate to the name of the #JTEST_TEST_t struct associated with test_fn. + */ +#define JTEST_TEST_STRUCT_NAME(test_fn) \ + JTEST_STRUCT_NAME(JTEST_TEST_STRUCT_NAME_PREFIX, test_fn) + +/** + * Define a #JTEST_TEST_t struct based on the given test_fn. + */ +#define JTEST_TEST_DEFINE_STRUCT(test_fn) \ + JTEST_DEFINE_STRUCT(JTEST_TEST_t, \ + JTEST_TEST_STRUCT_NAME(test_fn)) + +/** + * Declare a #JTEST_TEST_t struct based on the given test_fn. + */ +#define JTEST_TEST_DECLARE_STRUCT(test_fn) \ + JTEST_DECLARE_STRUCT(JTEST_TEST_DEFINE_STRUCT(test_fn)) + +/** + * Contents needed to initialize a JTEST_TEST_t struct. + */ +#define JTEST_TEST_STRUCT_INIT(test_fn, fut, enable) \ + test_fn, \ + STR_NL(test_fn), \ + STR_NL(fut), \ + { \ + { \ + enable, \ + 0 \ + } \ + } \ + + +/** + * Initialize the contents of a #JTEST_TEST_t struct. + */ +#define JTEST_TEST_INIT(test_fn, fut, enable) \ + JTEST_TEST_DEFINE_STRUCT(test_fn) = { \ + JTEST_TEST_STRUCT_INIT(test_fn, fut, enable) \ + } + +/* Test Definition Macro */ +/*--------------------------------------------------------------------------------*/ + +/** + * Define a #JTEST_TEST_t object and a test function. + */ +#define _JTEST_DEFINE_TEST(test_fn, fut, enable) \ + JTEST_TEST_FN_PROTOTYPE(test_fn); \ + JTEST_TEST_INIT(test_fn, fut, enable); \ + JTEST_TEST_FN_PROTOTYPE(test_fn) /* Notice the lacking semicolon */ + +/** + * Declare a #JTEST_TEST_t object and a test function prototype. + */ +#define JTEST_DECLARE_TEST(test_fn) \ + JTEST_TEST_FN_PROTOTYPE(test_fn); \ + JTEST_TEST_DECLARE_STRUCT(test_fn) /* Note the lacking semicolon */ + +/*--------------------------------------------------------------------------------*/ +/* Macros with optional arguments */ +/*--------------------------------------------------------------------------------*/ + +/* Top-level Interface */ +#define JTEST_DEFINE_TEST(...) \ + JTEST_DEFINE_TEST_(PP_NARG(__VA_ARGS__), ##__VA_ARGS__) + +/* Dispatch Macro*/ +#define JTEST_DEFINE_TEST_(N, ...) \ + SPLICE(JTEST_DEFINE_TEST_, N)(__VA_ARGS__) + +/* Default Arguments */ +#define JTEST_DEFINE_TEST_DEFAULT_FUT /* Blank */ +#define JTEST_DEFINE_TEST_DEFAULT_ENABLE \ + JTEST_TRUE /* Tests enabled by + * default. */ + +/* Dispatch Cases*/ +#define JTEST_DEFINE_TEST_1(_1) \ + _JTEST_DEFINE_TEST( \ + _1, \ + JTEST_DEFINE_TEST_DEFAULT_FUT, \ + JTEST_DEFINE_TEST_DEFAULT_ENABLE \ + ) + +#define JTEST_DEFINE_TEST_2(_1, _2) \ + _JTEST_DEFINE_TEST( \ + _1, \ + _2, \ + JTEST_DEFINE_TEST_DEFAULT_ENABLE \ + ) + +#define JTEST_DEFINE_TEST_3(_1, _2, _3) \ + _JTEST_DEFINE_TEST( \ + _1, \ + _2, \ + _3 \ + ) + +#endif /* _JTEST_TEST_DEFINE_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h new file mode 100644 index 0000000..c3176e5 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h @@ -0,0 +1,17 @@ +#ifndef _JTEST_TEST_RET_H_ +#define _JTEST_TEST_RET_H_ + +/*--------------------------------------------------------------------------------*/ +/* Type Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * Values a #JTEST_TEST_t can return. + */ +typedef enum JTEST_TEST_RET_enum +{ + JTEST_TEST_PASSED, + JTEST_TEST_FAILED +} JTEST_TEST_RET_t; + +#endif /* _JTEST_TEST_RET_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h new file mode 100644 index 0000000..3e07d2e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h @@ -0,0 +1,27 @@ +#ifndef _JTEST_UTIL_H_ +#define _JTEST_UTIL_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "util/util.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/* Define boolean values for the framework. */ +#define JTEST_TRUE 1 /**< Value used for TRUE in JTEST. */ +#define JTEST_FALSE 0 /**< Value used for FALSE in JTEST. */ + +/** + * Set the value of the attribute in the struct to by struct_ptr to value. + */ +#define JTEST_SET_STRUCT_ATTRIBUTE(struct_ptr, attribute, value) \ + do \ + { \ + (struct_ptr)->attribute = (value); \ + } while (0) + +#endif /* _JTEST_UTIL_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h new file mode 100644 index 0000000..683be1d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h @@ -0,0 +1,15 @@ +#ifndef _OPT_ARG_H_ +#define _OPT_ARG_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "pp_narg.h" +#include "splice.h" + +/* If you are Joseph Jaoudi, you have a snippet which expands into an + example. If you are not Joseph, but possess his code, study the examples. If + you have no examples, turn back contact Joseph. */ + +#endif /* _OPT_ARG_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h new file mode 100644 index 0000000..d3248f4 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h @@ -0,0 +1,25 @@ +#ifndef _PP_NARG_H_ +#define _PP_NARG_H_ + +#define PP_NARG(...) \ + PP_NARG_(__VA_ARGS__,PP_RSEQ_N()) +#define PP_NARG_(...) \ + PP_ARG_N(__VA_ARGS__) +#define PP_ARG_N( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \ + _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \ + _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \ + _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \ + _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \ + _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \ + _61,_62,_63,N,...) N +#define PP_RSEQ_N() \ + 63,62,61,60, \ + 59,58,57,56,55,54,53,52,51,50, \ + 49,48,47,46,45,44,43,42,41,40, \ + 39,38,37,36,35,34,33,32,31,30, \ + 29,28,27,26,25,24,23,22,21,20, \ + 19,18,17,16,15,14,13,12,11,10, \ + 9,8,7,6,5,4,3,2,1,0 + +#endif /* _PP_NARG_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h new file mode 100644 index 0000000..ec9142b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h @@ -0,0 +1,8 @@ +#ifndef _SPLICE_H_ +#define _SPLICE_H_ + +#define SPLICE(a,b) SPLICE_1(a,b) +#define SPLICE_1(a,b) SPLICE_2(a,b) +#define SPLICE_2(a,b) a##b + +#endif /* _SPLICE_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h new file mode 100644 index 0000000..f56e0e6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h @@ -0,0 +1,52 @@ +#ifndef _UTIL_H_ +#define _UTIL_H_ + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Convert a symbol to a string and add a 'NewLine'. + */ +#define STR_NL(x) STR1_NL(x) +#define STR1_NL(x) (STR2_NL(x)"\n") +#define STR2_NL(x) #x + +/** + * Convert a symbol to a string. + */ +#define STR(x) STR1(x) +#define STR1(x) STR2(x) +#define STR2(x) #x + +/** + * Concatenate two symbols. + */ +#define CONCAT(a, b) CONCAT1(a, b) +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a##b + + +/** + * Place curly braces around a varaible number of macro arguments. + */ +#define CURLY(...) {__VA_ARGS__} + +/** + * Place parenthesis around a variable number of macro arguments. + */ +#define PAREN(...) (__VA_ARGS__) + +/* Standard min/max macros. */ +#define MIN(x,y) (((x) < (y)) ? (x) : (y) ) +#define MAX(x,y) (((x) > (y)) ? (x) : (y) ) + +/** + * Bound value using low and high limits. + * + * Evaluate to a number in the range, endpoint inclusive. + */ +#define BOUND(low, high, value) \ + MAX(MIN(high, value), low) + +#endif /* _UTIL_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c new file mode 100644 index 0000000..24d552d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c @@ -0,0 +1,9 @@ +#include "../inc/jtest_cycle.h" +#include + +/*--------------------------------------------------------------------------------*/ +/* Define Module Variables */ +/*--------------------------------------------------------------------------------*/ + +/* const char * JTEST_CYCLE_STRF = "Running: %s\nCycles: %" PRIu32 "\n"; */ +const char * JTEST_CYCLE_STRF = "Cycles: %" PRIu32 "\n"; /* function name + parameter string skipped */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c new file mode 100644 index 0000000..c3a9bf8 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c @@ -0,0 +1,36 @@ +#include "jtest_fw.h" + +/** + * Dump the JTEST_FW.str_buffer the Keil framework in pieces. + * + * The JTEST_FW.str_buffer contains more characters than the Keil framework can + * dump at once. This function dumps them in blocks. + */ +void jtest_dump_str_segments(void) +{ + uint32_t seg_idx = 0; + uint32_t memmove_idx = 0; + uint32_t seg_cnt = + (strlen(JTEST_FW.str_buffer) / JTEST_STR_MAX_OUTPUT_SIZE) + 1; + + for( seg_idx = 0; seg_idx < seg_cnt; ++seg_idx) + { + JTEST_TRIGGER_ACTION(dump_str); + + if (seg_idx < JTEST_STR_MAX_OUTPUT_SEGMENTS) + { + memmove_idx = 0; + while (memmove_idx < (seg_cnt - seg_idx -1) ) + { + memmove( + JTEST_FW.str_buffer+ + (memmove_idx* JTEST_STR_MAX_OUTPUT_SIZE), + JTEST_FW.str_buffer+ + ((memmove_idx+1)*JTEST_STR_MAX_OUTPUT_SIZE), + JTEST_BUF_SIZE); + ++memmove_idx; + } + } + } + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c new file mode 100644 index 0000000..69d7a63 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c @@ -0,0 +1,9 @@ +#include "../inc/jtest.h" + +/*--------------------------------------------------------------------------------*/ +/* Define Global Variables */ +/*--------------------------------------------------------------------------------*/ + +char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE] = {0}; + +volatile JTEST_FW_t JTEST_FW = {0}; diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c new file mode 100644 index 0000000..a3901da --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c @@ -0,0 +1,37 @@ + +#include "jtest_fw.h" + +void test_start (void) { +// ; + JTEST_FW.test_start++; +} + +void test_end (void) { +// ; + JTEST_FW.test_end++; +} + +void group_start (void) { +// ; + JTEST_FW.group_start++; +} + +void group_end (void) { +// ; + JTEST_FW.group_end++; +} + +void dump_str (void) { +// ; + JTEST_FW.dump_str++; +} + +void dump_data (void) { +// ; + JTEST_FW.dump_data++; +} + +void exit_fw (void) { +// ; + JTEST_FW.exit_fw++; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h new file mode 100644 index 0000000..df1e998 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h @@ -0,0 +1,9 @@ +#ifndef _ALL_TESTS_H_ +#define _ALL_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(all_tests); + +#endif /* _ALL_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_templates.h new file mode 100644 index 0000000..958ef78 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_templates.h @@ -0,0 +1,267 @@ +#ifndef _BASIC_MATH_TEMPLATES_H_ +#define _BASIC_MATH_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ +#include "test_templates.h" + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Compare the outputs used by basic math tests for the function under test and + * the reference function. + */ +#define BASIC_MATH_COMPARE_INTERFACE(block_size, output_type) \ + TEST_ASSERT_BUFFERS_EQUAL( \ + basic_math_output_ref.data_ptr, \ + basic_math_output_fut.data_ptr, \ + block_size * sizeof(output_type)) + +/* + * Comparison SNR thresholds for the data types used in basic_math_tests. + */ +#define BASIC_MATH_SNR_THRESHOLD_float32_t 120 +#define BASIC_MATH_SNR_THRESHOLD_q31_t 100 +#define BASIC_MATH_SNR_THRESHOLD_q15_t 75 +#define BASIC_MATH_SNR_THRESHOLD_q7_t 25 + +/** + * Compare reference and fut outputs using SNR. + * + * @note The outputs are converted to float32_t before comparison. + */ +#define BASIC_MATH_SNR_COMPARE_INTERFACE(block_size, output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + basic_math_output_f32_ref, \ + basic_math_output_ref.data_ptr, \ + basic_math_output_f32_fut, \ + basic_math_output_fut.data_ptr, \ + block_size, \ + output_type, \ + BASIC_MATH_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + + +/** + * Compare reference and fut outputs using SNR. + * + * @note The outputs are converted to float32_t before comparison. + */ +#define BASIC_MATH_SNR_ELT1_COMPARE_INTERFACE(block_size, output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + basic_math_output_f32_ref, \ + basic_math_output_ref.data_ptr, \ + basic_math_output_f32_fut, \ + basic_math_output_fut.data_ptr, \ + 1, \ + output_type, \ + BASIC_MATH_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + + + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define ARM_abs_INPUT_INTERFACE(input, block_size) \ + PAREN(input, basic_math_output_fut.data_ptr, block_size) + +#define REF_abs_INPUT_INTERFACE(input, block_size) \ + PAREN(input, basic_math_output_ref.data_ptr, block_size) + +#define ARM_add_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_add_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \ + +#define ARM_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, block_size, basic_math_output_fut.data_ptr) \ + +#define REF_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, block_size, basic_math_output_ref.data_ptr) \ + +#define ARM_mult_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_mult_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \ + +#define ARM_negate_INPUT_INTERFACE(input, block_size) \ + PAREN(input, basic_math_output_fut.data_ptr, block_size) + +#define REF_negate_INPUT_INTERFACE(input, block_size) \ + PAREN(input, basic_math_output_ref.data_ptr, block_size) + +#define ARM_offset_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_offset_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \ + +#define ARM_shift_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_shift_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \ + +#define ARM_scale_float_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_scale_float_INPUT_INTERFACE(input, elt, block_size) \ + PAREN(input, elt, basic_math_output_ref.data_ptr, block_size) \ + +/* These two are for the fixed point functions */ +#define ARM_scale_INPUT_INTERFACE(input, elt1, elt2, block_size) \ + PAREN(input, elt1, elt2, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_scale_INPUT_INTERFACE(input, elt1, elt2, block_size) \ + PAREN(input, elt1, elt2, basic_math_output_ref.data_ptr, block_size) \ + +#define ARM_sub_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \ + +#define REF_sub_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \ + + +/*--------------------------------------------------------------------------------*/ +/* Test Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Specialization of #TEST_TEMPLATE_BUF1_BLK() for basic math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_BLK( \ + basic_math_f_all, \ + basic_math_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + BASIC_MATH_COMPARE_INTERFACE); \ + } + +/** + * Specialization of #TEST_TEMPLATE_BUF2_BLK() for basic math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF2_BLK( \ + basic_math_f_all, \ + basic_math_f_all, \ + basic_math_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + +/** + * Specialization of #TEST_TEMPLATE_BUF1_ELT1_BLK() for basic math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK(fn_name, \ + suffix, \ + input_type, \ + elt_type, \ + output_type) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_ELT1_BLK( \ + basic_math_f_all, \ + basic_math_elts, \ + basic_math_block_sizes, \ + input_type, \ + elt_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + BASIC_MATH_COMPARE_INTERFACE); \ + } + +/** + * Specialization of #TEST_TEMPLATE_BUF1_ELT2_BLK() for basic math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT2_BLK(fn_name, \ + suffix, \ + input_type, \ + elt1_type, \ + elt2_type, \ + output_type) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_ELT2_BLK( \ + basic_math_f_all, \ + basic_math_elts, \ + basic_math_elts2, \ + basic_math_block_sizes, \ + input_type, \ + elt1_type, \ + elt2_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + BASIC_MATH_COMPARE_INTERFACE); \ + } + +#endif /* _BASIC_MATH_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_data.h new file mode 100644 index 0000000..2f0b239 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_data.h @@ -0,0 +1,46 @@ +#ifndef ARM_BASIC_MATH_TEST_DATA_H +#define ARM_BASIC_MATH_TEST_DATA_H + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" +#include "arm_math.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ +#define BASIC_MATH_MAX_INPUT_ELEMENTS 32 +#define BASIC_MATH_BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Declare Variables */ +/*--------------------------------------------------------------------------------*/ + +/* Input/Output Buffers */ +ARR_DESC_DECLARE(basic_math_output_fut); +ARR_DESC_DECLARE(basic_math_output_ref); + +extern BASIC_MATH_BIGGEST_INPUT_TYPE +basic_math_output_f32_ref[BASIC_MATH_MAX_INPUT_ELEMENTS]; + +extern BASIC_MATH_BIGGEST_INPUT_TYPE +basic_math_output_f32_fut[BASIC_MATH_MAX_INPUT_ELEMENTS]; + +/* Block Sizes*/ +ARR_DESC_DECLARE(basic_math_block_sizes); + +/* Numbers */ +ARR_DESC_DECLARE(basic_math_elts); +ARR_DESC_DECLARE(basic_math_elts2); +ARR_DESC_DECLARE(basic_math_eltsf); + +/* Float Inputs */ +ARR_DESC_DECLARE(basic_math_zeros); +ARR_DESC_DECLARE(basic_math_f_2); +ARR_DESC_DECLARE(basic_math_f_15); +ARR_DESC_DECLARE(basic_math_f_32); +ARR_DESC_DECLARE(basic_math_f_all); + +#endif diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_group.h new file mode 100644 index 0000000..ece92c7 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_group.h @@ -0,0 +1,9 @@ +#ifndef _BASIC_MATH_TEST_GROUP_H_ +#define _BASIC_MATH_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(basic_math_tests); + +#endif /* _BASIC_MATH_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h new file mode 100644 index 0000000..0550444 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h @@ -0,0 +1,17 @@ +#ifndef _BASIC_MATH_TESTS_H_ +#define _BASIC_MATH_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(abs_tests); +JTEST_DECLARE_GROUP(add_tests); +JTEST_DECLARE_GROUP(dot_prod_tests); +JTEST_DECLARE_GROUP(mult_tests); +JTEST_DECLARE_GROUP(negate_tests); +JTEST_DECLARE_GROUP(offset_tests); +JTEST_DECLARE_GROUP(scale_tests); +JTEST_DECLARE_GROUP(shift_tests); +JTEST_DECLARE_GROUP(sub_tests); + +#endif /* _BASIC_MATH_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_templates.h new file mode 100644 index 0000000..3b7f22f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_templates.h @@ -0,0 +1,222 @@ +#ifndef _COMPLEX_MATH_TEMPLATES_H_ +#define _COMPLEX_MATH_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ +#include "test_templates.h" + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Compare the real outputs from the function under test and the reference + * function. + */ +#define COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size, output_type) \ + TEST_ASSERT_BUFFERS_EQUAL( \ + complex_math_output_ref_a.data_ptr, \ + complex_math_output_fut_a.data_ptr, \ + block_size * sizeof(output_type)) + +/** + * Compare the real and imaginary outputs from the function under test and the + * reference function. + */ +#define COMPLEX_MATH_COMPARE_CMPLX_INTERFACE(block_size, output_type) \ + do \ + { \ + COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size * 2, output_type); \ + } while (0) + + +/* + * Comparison SNR thresholds for the data types used in complex_math_tests. + */ +#define COMPLEX_MATH_SNR_THRESHOLD_float32_t 120 +#define COMPLEX_MATH_SNR_THRESHOLD_q31_t 100 +#define COMPLEX_MATH_SNR_THRESHOLD_q15_t 75 + +/** + * Compare reference and fut outputs using SNR. + * + * The output_suffix specifies which output buffers to use for the + * comparison. An output_suffix of 'a' expands to the following buffers: + * + * - complex_math_output_f32_ref_a + * - complex_math_output_f32_fut_a + * - complex_math_output_ref_a + * - complex_math_output_fut_a + * + * @note The outputs are converted to float32_t before comparison. + */ +#define COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \ + output_type, \ + output_suffix) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + complex_math_output_f32_ref_##output_suffix, \ + complex_math_output_ref_##output_suffix.data_ptr, \ + complex_math_output_f32_fut_##output_suffix, \ + complex_math_output_fut_##output_suffix.data_ptr, \ + block_size, \ + output_type, \ + COMPLEX_MATH_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + +/** + * Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for real outputs. + */ +#define COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE(block_size, \ + output_type) \ + COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \ + output_type, \ + a) + +/** + * Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for complex outputs. + */ +#define COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE(block_size, \ + output_type) \ + COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size * 2, \ + output_type, \ + a) + +/** + * Compare reference and fut split outputs using SNR. + * + * 'Split' refers to two separate output buffers; one for real and one for + * complex. + */ +#define COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \ + output_type, \ + a); \ + COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size, \ + output_type, \ + b); \ + } while (0) + + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define ARM_cmplx_conj_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_fut_a.data_ptr, block_size) + +#define REF_cmplx_conj_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_ref_a.data_ptr, block_size) + +#define ARM_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, block_size, \ + complex_math_output_fut_a.data_ptr, \ + complex_math_output_fut_b.data_ptr) + +#define REF_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, block_size, \ + complex_math_output_ref_a.data_ptr, \ + complex_math_output_ref_b.data_ptr) + +#define ARM_cmplx_mag_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_fut_a.data_ptr, block_size) + +#define REF_cmplx_mag_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_ref_a.data_ptr, block_size) + +#define ARM_cmplx_mag_squared_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_fut_a.data_ptr, block_size) + +#define REF_cmplx_mag_squared_INPUT_INTERFACE(input, block_size) \ + PAREN(input, complex_math_output_ref_a.data_ptr, block_size) + +#define ARM_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size) + +#define REF_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size) + +#define ARM_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size) + +#define REF_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \ + PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size) + +/*--------------------------------------------------------------------------------*/ +/* Test Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Specialization of #TEST_TEMPLATE_BUF1_BLK() for complex math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_BLK( \ + complex_math_f_all, \ + complex_math_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + +/** + * Specialization of #TEST_TEMPLATE_BUF2_BLK1() for complex math tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF2_BLK( \ + complex_math_f_all, \ + complex_math_f_all, \ + complex_math_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + +#endif /* _COMPLEX_MATH_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_data.h new file mode 100644 index 0000000..df561b4 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_data.h @@ -0,0 +1,50 @@ +#ifndef _COMPLEX_MATH_TEST_DATA_H_ +#define _COMPLEX_MATH_TEST_DATA_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" +#include "arm_math.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ +#define COMPLEX_MATH_MAX_INPUT_ELEMENTS 32 +#define COMPLEX_MATH_BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Decalare Variables */ +/*--------------------------------------------------------------------------------*/ + +/* Input/Output Buffers */ +ARR_DESC_DECLARE(complex_math_output_fut_a); +ARR_DESC_DECLARE(complex_math_output_fut_b); +ARR_DESC_DECLARE(complex_math_output_ref_a); +ARR_DESC_DECLARE(complex_math_output_ref_b); + +extern COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_ref_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +extern COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_ref_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +extern COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_fut_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +extern COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_fut_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +/* Block Sizes*/ +ARR_DESC_DECLARE(complex_math_block_sizes); + +/* Float Inputs */ +ARR_DESC_DECLARE(complex_math_zeros); +ARR_DESC_DECLARE(complex_math_f_2); +ARR_DESC_DECLARE(complex_math_f_15); +ARR_DESC_DECLARE(complex_math_f_32); +ARR_DESC_DECLARE(complex_math_f_all); + + +#endif /* _COMPLEX_MATH_TEST_DATA_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h new file mode 100644 index 0000000..5c2ea1f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h @@ -0,0 +1,9 @@ +#ifndef _COMPLEX_MATH_TEST_GROUP_H_ +#define _COMPLEX_MATH_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(complex_math_tests); + +#endif /* _COMPLEX_MATH_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h new file mode 100644 index 0000000..ab4f0ae --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h @@ -0,0 +1,14 @@ +#ifndef _COMPLEX_MATH_TESTS_H_ +#define _COMPLEX_MATH_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(cmplx_conj_tests); +JTEST_DECLARE_GROUP(cmplx_dot_prod_tests); +JTEST_DECLARE_GROUP(cmplx_mag_tests); +JTEST_DECLARE_GROUP(cmplx_mag_squared_tests); +JTEST_DECLARE_GROUP(cmplx_mult_cmplx_tests); +JTEST_DECLARE_GROUP(cmplx_mult_real_tests); + +#endif /* _COMPLEX_MATH_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h new file mode 100644 index 0000000..f7956fb --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h @@ -0,0 +1,46 @@ +#ifndef _CONTROLLER_TEMPLATES_H_ +#define _CONTROLLER_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "test_templates.h" +#include /* memcpy() */ + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Comparison SNR thresholds for the data types used in transform_tests. + */ +#define CONTROLLER_SNR_THRESHOLD_float32_t 110 +#define CONTROLLER_SNR_THRESHOLD_q31_t 100 +#define CONTROLLER_SNR_THRESHOLD_q15_t 45 + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. + */ +#define CONTROLLER_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + controller_output_f32_ref, \ + (output_type *) controller_output_ref, \ + controller_output_f32_fut, \ + (output_type *) controller_output_fut, \ + block_size, \ + output_type, \ + CONTROLLER_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + + +/*--------------------------------------------------------------------------------*/ +/* TEST Templates */ +/*--------------------------------------------------------------------------------*/ + +#endif /* _CONTROLLER_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h new file mode 100644 index 0000000..5aa63eb --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h @@ -0,0 +1,33 @@ +#ifndef _CONTROLLER_TEST_DATA_H_ +#define _CONTROLLER_TEST_DATA_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arm_math.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +#define CONTROLLER_MAX_LEN 1024 +#define CONTROLLER_MAX_COEFFS_LEN (12 * 3) +#define TRANFORM_BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Variable Declarations */ +/*--------------------------------------------------------------------------------*/ + +extern float32_t controller_output_fut[CONTROLLER_MAX_LEN]; +extern float32_t controller_output_ref[CONTROLLER_MAX_LEN]; +extern float32_t controller_output_f32_fut[CONTROLLER_MAX_LEN]; +extern float32_t controller_output_f32_ref[CONTROLLER_MAX_LEN]; +extern const float32_t controller_f32_inputs[CONTROLLER_MAX_LEN]; +extern const q31_t controller_q31_inputs[CONTROLLER_MAX_LEN]; +extern const q15_t * controller_q15_inputs; +extern const float32_t controller_f32_coeffs[CONTROLLER_MAX_COEFFS_LEN]; +extern const q31_t controller_q31_coeffs[CONTROLLER_MAX_COEFFS_LEN]; +extern const q15_t controller_q15_coeffs[CONTROLLER_MAX_COEFFS_LEN]; + +#endif /* _CONTROLLER_TEST_DATA_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h new file mode 100644 index 0000000..baead25 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h @@ -0,0 +1,9 @@ +#ifndef _CONTROLLER_TEST_GROUP_H_ +#define _CONTROLLER_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Group */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(controller_tests); + +#endif /* _CONTROLLER_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h new file mode 100644 index 0000000..41996a8 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h @@ -0,0 +1,11 @@ +#ifndef _CONTROLLER_TESTS_H_ +#define _CONTROLLER_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(pid_reset_tests); +JTEST_DECLARE_GROUP(sin_cos_tests); +JTEST_DECLARE_GROUP(pid_tests); + +#endif /* _CONTROLLER_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_templates.h new file mode 100644 index 0000000..5b49512 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_templates.h @@ -0,0 +1,102 @@ +#ifndef _FAST_MATH_TEMPLATES_H_ +#define _FAST_MATH_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "test_templates.h" +#include /* memcpy() */ + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Comparison SNR thresholds for the data types used in transform_tests. + */ +#define FAST_MATH_SNR_THRESHOLD_float32_t 95 +#define FAST_MATH_SNR_THRESHOLD_q31_t 95 +#define FAST_MATH_SNR_THRESHOLD_q15_t 45 + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. + */ +#define FAST_MATH_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + fast_math_output_f32_ref, \ + (output_type *) fast_math_output_ref, \ + fast_math_output_f32_fut, \ + (output_type *) fast_math_output_fut, \ + block_size, \ + output_type, \ + FAST_MATH_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + + +/*--------------------------------------------------------------------------------*/ +/* TEST Templates */ +/*--------------------------------------------------------------------------------*/ + +#define SQRT_TEST_TEMPLATE_ELT1(suffix) \ + \ + JTEST_DEFINE_TEST(arm_sqrt_##suffix##_test, arm_sqrt_##suffix) \ + { \ + uint32_t i; \ + \ + JTEST_COUNT_CYCLES( \ + for(i=0;i /* memcpy() */ + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** +* Comparison SNR thresholds for the data types used in transform_tests. +*/ +#define INTRINSICS_SNR_THRESHOLD_q63_t 120 +#define INTRINSICS_SNR_THRESHOLD_q31_t 95 + +/** +* Compare the outputs from the function under test and the reference +* function using SNR. +*/ +#define INTRINSICS_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + intrinsics_output_f32_ref, \ + (output_type##_t *) intrinsics_output_ref, \ + intrinsics_output_f32_fut, \ + (output_type##_t *) intrinsics_output_fut, \ + block_size, \ + output_type, \ + INTRINSICS_SNR_THRESHOLD_##output_type##_t \ + ); \ + } while (0) + + +/*--------------------------------------------------------------------------------*/ +/* TEST Templates */ +/*--------------------------------------------------------------------------------*/ + +#define INTRINSICS_TEST_TEMPLATE_ELT1(functionName, dataType) \ + \ + JTEST_DEFINE_TEST(functionName##_test, functionName) \ + { \ + uint32_t i; \ + \ + JTEST_COUNT_CYCLES( \ + for(i=0;ipData, \ + ((output_type *) &matrix_output_fut)->pData, \ + ((output_type *) &matrix_output_fut)->numRows * \ + ((output_type *) &matrix_output_ref)->numCols * \ + sizeof(output_content_type)) + +/** + * Comparison SNR thresholds for the data types used in matrix_tests. + */ +#define MATRIX_SNR_THRESHOLD 120 + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. + */ +#define MATRIX_SNR_COMPARE_INTERFACE(output_type, output_content_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + (float32_t *)matrix_output_f32_ref, \ + ((output_type *) &matrix_output_ref)->pData, \ + (float32_t *)matrix_output_f32_fut, \ + ((output_type *) &matrix_output_ref)->pData, \ + ((output_type *) &matrix_output_fut)->numRows * \ + ((output_type *) &matrix_output_ref)->numCols, \ + output_content_type, \ + MATRIX_SNR_THRESHOLD \ + ); \ + } while (0) + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. This is special for float64_t + */ +#define MATRIX_DBL_SNR_COMPARE_INTERFACE(output_type) \ + do \ + { \ + TEST_ASSERT_DBL_SNR( \ + (float64_t *)matrix_output_f32_ref, \ + (float64_t *)matrix_output_f32_fut, \ + ((output_type *) &matrix_output_fut)->numRows * \ + ((output_type *) &matrix_output_ref)->numCols, \ + MATRIX_SNR_THRESHOLD \ + ); \ + } while (0) + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define ARM_mat_add_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut) + +#define REF_mat_add_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_cmplx_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut) + +#define REF_mat_cmplx_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_inverse_INPUT_INTERFACE(input_ptr) \ + PAREN(input_ptr, (void *) &matrix_output_fut) + +#define REF_mat_inverse_INPUT_INTERFACE(input_ptr) \ + PAREN(input_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut) + +#define REF_mat_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_mult_fast_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut) + +#define REF_mat_mult_fast_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_sub_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut) + +#define REF_mat_sub_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref) + +#define ARM_mat_trans_INPUT_INTERFACE(input_ptr) \ + PAREN(input_ptr, (void *) &matrix_output_fut) + +#define REF_mat_trans_INPUT_INTERFACE(input_ptr) \ + PAREN(input_ptr, (void *) &matrix_output_ref) + +/*--------------------------------------------------------------------------------*/ +/* Dimension Validation Interfaces */ +/*--------------------------------------------------------------------------------*/ + +#define MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS(input_type, \ + matrix_a_ptr, \ + matrix_b_ptr) \ + ((((input_type) (matrix_a_ptr))->numRows == \ + ((input_type) (matrix_b_ptr))->numRows) && \ + (((input_type) (matrix_a_ptr))->numCols == \ + ((input_type) (matrix_b_ptr))->numCols)) + +#define MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS(input_type, \ + matrix_a_ptr, \ + matrix_b_ptr) \ + (((input_type) (matrix_a_ptr))->numCols == \ + ((input_type) (matrix_b_ptr))->numRows) + +#define MATRIX_TEST_VALID_SQUARE_DIMENSIONS(input_type, \ + matrix_ptr) \ + (((input_type)(matrix_ptr))->numRows == \ + ((input_type)(matrix_ptr))->numCols) + +#define MATRIX_TEST_VALID_DIMENSIONS_ALWAYS(input_type, \ + matrix_ptr) \ + (1 == 1) \ + +/*--------------------------------------------------------------------------------*/ +/* Output Configuration Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* The matrix tests assume the output matrix is always the correct size. These + * interfaces size the properly size the output matrices according to the input + * matrices and the operation at hand.*/ + +#define MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT(input_type, \ + matrix_a_ptr, \ + matrix_b_ptr) \ + do \ + { \ + ((input_type) &matrix_output_fut)->numRows = \ + ((input_type)(matrix_a_ptr))->numRows; \ + ((input_type) &matrix_output_fut)->numCols = \ + ((input_type)(matrix_a_ptr))->numCols; \ + ((input_type) &matrix_output_ref)->numRows = \ + ((input_type)(matrix_a_ptr))->numRows; \ + ((input_type) &matrix_output_ref)->numCols = \ + ((input_type)(matrix_a_ptr))->numCols; \ + } while (0) + +#define MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT(input_type, \ + matrix_a_ptr, \ + matrix_b_ptr) \ + do \ + { \ + ((input_type) &matrix_output_fut)->numRows = \ + ((input_type)(matrix_a_ptr))->numRows; \ + ((input_type) &matrix_output_fut)->numCols = \ + ((input_type)(matrix_b_ptr))->numCols; \ + ((input_type) &matrix_output_ref)->numRows = \ + ((input_type)(matrix_a_ptr))->numRows; \ + ((input_type) &matrix_output_ref)->numCols = \ + ((input_type)(matrix_b_ptr))->numCols; \ + } while (0) + +#define MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(input_type, \ + matrix_ptr) \ + do \ + { \ + ((input_type) &matrix_output_fut)->numRows = \ + ((input_type)(matrix_ptr))->numRows; \ + ((input_type) &matrix_output_fut)->numCols = \ + ((input_type)(matrix_ptr))->numCols; \ + ((input_type) &matrix_output_ref)->numRows = \ + ((input_type)(matrix_ptr))->numRows; \ + ((input_type) &matrix_output_ref)->numCols = \ + ((input_type)(matrix_ptr))->numCols; \ + } while (0) + +#define MATRIX_TEST_CONFIG_TRANSPOSE_OUTPUT(input_type, \ + matrix_ptr) \ + do \ + { \ + ((input_type) &matrix_output_fut)->numRows = \ + ((input_type)(matrix_ptr))->numCols; \ + ((input_type) &matrix_output_fut)->numCols = \ + ((input_type)(matrix_ptr))->numRows; \ + ((input_type) &matrix_output_ref)->numRows = \ + ((input_type)(matrix_ptr))->numCols; \ + ((input_type) &matrix_output_ref)->numCols = \ + ((input_type)(matrix_ptr))->numRows; \ + } while (0) + +/*--------------------------------------------------------------------------------*/ +/* TEST Templates */ +/*--------------------------------------------------------------------------------*/ + +#define MATRIX_TEST_TEMPLATE_ELT1(arr_desc_inputs, \ + input_type, \ + output_type, output_content_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + output_config_interface, \ + dim_validation_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, input_type, input, arr_desc_inputs \ + , \ + JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", \ + (int)input->numRows, \ + (int)input->numCols); \ + \ + if (dim_validation_interface(input_type, \ + input)) { \ + output_config_interface(input_type, \ + input); \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface(input), \ + ref, ref_arg_interface(input)); \ + compare_interface(output_type, \ + output_content_type); \ + } else { \ + arm_status matrix_test_retval; \ + TEST_CALL_FUT( \ + matrix_test_retval = fut, \ + fut_arg_interface(input)); \ + \ + /* If dimensions are known bad, the fut should */ \ + /* detect it. */ \ + if ( matrix_test_retval != ARM_MATH_SIZE_MISMATCH) { \ + return JTEST_TEST_FAILED; \ + } \ + }); \ + return JTEST_TEST_PASSED; \ + } while (0) + + +#define MATRIX_TEST_TEMPLATE_ELT2(arr_desc_inputs_a, \ + arr_desc_inputs_b, \ + input_type, \ + output_type, output_content_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + output_config_interface, \ + dim_validation_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_a_idx, input_type, input_a, arr_desc_inputs_a \ + , \ + input_type input_b = ARR_DESC_ELT( \ + input_type, input_a_idx, \ + &(arr_desc_inputs_b)); \ + \ + JTEST_DUMP_STRF("Matrix Dimensions: A %dx%d B %dx%d\n", \ + (int)input_a->numRows, \ + (int)input_a->numCols, \ + (int)input_b->numRows, \ + (int)input_b->numCols); \ + \ + if (dim_validation_interface(input_type, \ + input_a, \ + input_b)) { \ + \ + output_config_interface(input_type, \ + input_a, \ + input_b); \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface(input_a, input_b), \ + ref, ref_arg_interface(input_a, input_b)); \ + \ + compare_interface(output_type, output_content_type); \ + \ + } else { \ + arm_status matrix_test_retval; \ + TEST_CALL_FUT( \ + matrix_test_retval = fut, fut_arg_interface(input_a, input_b)); \ + \ + /* If dimensions are known bad, the fut should */ \ + /* detect it. */ \ + if ( matrix_test_retval != ARM_MATH_SIZE_MISMATCH) { \ + return JTEST_TEST_FAILED; \ + } \ + }); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Specialization of #MATRIX_TEST_TEMPLATE_ELT2() for matrix tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define MATRIX_DEFINE_TEST_TEMPLATE_ELT2(fn_name, suffix, \ + output_config_interface, \ + dim_validation_interface, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + MATRIX_TEST_TEMPLATE_ELT2( \ + matrix_##suffix##_a_inputs, \ + matrix_##suffix##_b_inputs, \ + arm_matrix_instance_##suffix * , \ + arm_matrix_instance_##suffix, \ + TYPE_FROM_ABBREV(suffix), \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + output_config_interface, \ + dim_validation_interface, \ + comparison_interface); \ + } \ + +/** + * Specialization of #MATRIX_TEST_TEMPLATE_ELT1() for matrix tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define MATRIX_DEFINE_TEST_TEMPLATE_ELT1(fn_name, suffix, \ + output_config_interface, \ + dim_validation_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + MATRIX_TEST_TEMPLATE_ELT1( \ + matrix_##suffix##_a_inputs, \ + arm_matrix_instance_##suffix * , \ + arm_matrix_instance_##suffix, \ + TYPE_FROM_ABBREV(suffix), \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + output_config_interface, \ + dim_validation_interface, \ + MATRIX_COMPARE_INTERFACE); \ + } \ + + +#endif /* _MATRIX_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_data.h new file mode 100644 index 0000000..5940ae3 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_data.h @@ -0,0 +1,54 @@ +#ifndef _MATRIX_TEST_DATA_H_ +#define _MATRIX_TEST_DATA_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" +#include "arm_math.h" /* float32_t */ + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ +#define MATRIX_TEST_MAX_ROWS 4 +#define MATRIX_TEST_MAX_COLS 4 +#define MATRIX_TEST_BIGGEST_INPUT_TYPE float64_t +#define MATRIX_TEST_MAX_ELTS (MATRIX_TEST_MAX_ROWS * MATRIX_TEST_MAX_COLS) +#define MATRIX_MAX_COEFFS_LEN 16 +#define MATRIX_MAX_SHIFTS_LEN 5 + +/** + * Declare the matrix inputs defined by MATRIX_DEFINE_INPUTS. + */ +#define MATRIX_DECLARE_INPUTS(suffix) \ + ARR_DESC_DECLARE(matrix_##suffix##_a_inputs); \ + ARR_DESC_DECLARE(matrix_##suffix##_b_inputs); \ + ARR_DESC_DECLARE(matrix_##suffix##_invertible_inputs) + + +/*--------------------------------------------------------------------------------*/ +/* Declare Variables */ +/*--------------------------------------------------------------------------------*/ + +/* Input/Output Buffers */ +extern arm_matrix_instance_f32 matrix_output_fut; +extern arm_matrix_instance_f32 matrix_output_ref; +extern arm_matrix_instance_f64 matrix_output_fut64; +extern arm_matrix_instance_f64 matrix_output_ref64; +extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_fut[MATRIX_TEST_MAX_ELTS]; +extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_ref[MATRIX_TEST_MAX_ELTS]; +extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_scratch[MATRIX_TEST_MAX_ELTS]; + +/* Matrix Inputs */ +MATRIX_DECLARE_INPUTS(f64); +MATRIX_DECLARE_INPUTS(f32); +MATRIX_DECLARE_INPUTS(q31); +MATRIX_DECLARE_INPUTS(q15); + +extern const float32_t matrix_f32_scale_values[MATRIX_MAX_COEFFS_LEN]; +extern const q31_t matrix_q31_scale_values[MATRIX_MAX_COEFFS_LEN]; +extern const q15_t matrix_q15_scale_values[MATRIX_MAX_COEFFS_LEN]; +extern const int32_t matrix_shift_values[MATRIX_MAX_SHIFTS_LEN]; + +#endif /* _MATRIX_TEST_DATA_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_group.h new file mode 100644 index 0000000..017b125 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_group.h @@ -0,0 +1,9 @@ +#ifndef _MATRIX_TEST_GROUP_H_ +#define _MATRIX_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(matrix_tests); + +#endif /* _MATRIX_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h new file mode 100644 index 0000000..9947c02 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h @@ -0,0 +1,17 @@ +#ifndef _MATRIX_TESTS_H_ +#define _MATRIX_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(mat_add_tests); +JTEST_DECLARE_GROUP(mat_cmplx_mult_tests); +JTEST_DECLARE_GROUP(mat_init_tests); +JTEST_DECLARE_GROUP(mat_inverse_tests); +JTEST_DECLARE_GROUP(mat_mult_tests); +JTEST_DECLARE_GROUP(mat_mult_fast_tests); +JTEST_DECLARE_GROUP(mat_sub_tests); +JTEST_DECLARE_GROUP(mat_trans_tests); +JTEST_DECLARE_GROUP(mat_scale_tests); + +#endif /* _MATRIX_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h new file mode 100644 index 0000000..ddca35c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h @@ -0,0 +1,157 @@ +#ifndef _STATISTICS_TEMPLATES_H_ +#define _STATISTICS_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "test_templates.h" + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Compare the outputs from the function under test and the reference function. + */ +#define STATISTICS_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_ASSERT_BUFFERS_EQUAL( \ + statistics_output_ref.data_ptr, \ + statistics_output_fut.data_ptr, \ + 1 * sizeof(output_type) /* All fns return one value*/ \ + ); \ + TEST_ASSERT_EQUAL( \ + statistics_idx_fut, \ + statistics_idx_ref); \ + } while (0) \ + +/* + * Comparison SNR thresholds for the data types used in statistics_tests. + */ +#define STATISTICS_SNR_THRESHOLD_float32_t 120 +#define STATISTICS_SNR_THRESHOLD_q31_t 100 +#define STATISTICS_SNR_THRESHOLD_q15_t 60 +#define STATISTICS_SNR_THRESHOLD_q7_t 30 + +/** + * Compare reference and fut outputs using SNR. + * + * @note The outputs are converted to float32_t before comparison. + */ +#define STATISTICS_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + statistics_output_f32_ref, \ + statistics_output_ref.data_ptr, \ + statistics_output_f32_fut, \ + statistics_output_fut.data_ptr, \ + 1, /* All fns return one element*/ \ + output_type, \ + STATISTICS_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + + + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define ARM_max_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, \ + statistics_output_fut.data_ptr, &statistics_idx_fut) + +#define REF_max_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, \ + statistics_output_ref.data_ptr, &statistics_idx_ref) + +#define ARM_mean_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_fut.data_ptr) + +#define REF_mean_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_ref.data_ptr) + +#define ARM_min_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, \ + statistics_output_fut.data_ptr, &statistics_idx_fut) + +#define REF_min_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, \ + statistics_output_ref.data_ptr, &statistics_idx_ref) + +#define ARM_power_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_fut.data_ptr) + +#define REF_power_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_ref.data_ptr) + +#define ARM_rms_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_fut.data_ptr) + +#define REF_rms_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_ref.data_ptr) + +#define ARM_std_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_fut.data_ptr) + +#define REF_std_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_ref.data_ptr) + +#define ARM_var_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_fut.data_ptr) + +#define REF_var_INPUT_INTERFACE(input, block_size) \ + PAREN(input, block_size, statistics_output_ref.data_ptr) + + +/*--------------------------------------------------------------------------------*/ +/* Test Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Specialization of #TEST_TEMPLATE_BUF1_BLK() for statistics tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_BLK( \ + statistics_f_all, \ + statistics_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + + +#endif /* _STATISTICS_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h new file mode 100644 index 0000000..3e1ee09 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h @@ -0,0 +1,44 @@ +#ifndef _STATISTICS_TEST_DATA_H_ +#define _STATISTICS_TEST_DATA_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" +#include "arm_math.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ +#define STATISTICS_MAX_INPUT_ELEMENTS 32 +#define STATISTICS_BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Declare Variables */ +/*--------------------------------------------------------------------------------*/ + +/* Input/Output Buffers */ +ARR_DESC_DECLARE(statistics_output_fut); +ARR_DESC_DECLARE(statistics_output_ref); +extern uint32_t statistics_idx_fut; +extern uint32_t statistics_idx_ref; + +extern STATISTICS_BIGGEST_INPUT_TYPE +statistics_output_f32_ref[STATISTICS_MAX_INPUT_ELEMENTS]; + +extern STATISTICS_BIGGEST_INPUT_TYPE +statistics_output_f32_fut[STATISTICS_MAX_INPUT_ELEMENTS]; + + +/* Block Sizes */ +ARR_DESC_DECLARE(statistics_block_sizes); + +/* Float Inputs */ +ARR_DESC_DECLARE(statistics_zeros); +ARR_DESC_DECLARE(statistics_f_2); +ARR_DESC_DECLARE(statistics_f_15); +ARR_DESC_DECLARE(statistics_f_32); +ARR_DESC_DECLARE(statistics_f_all); + +#endif /* _STATISTICS_TEST_DATA_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_group.h new file mode 100644 index 0000000..d1446ed --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_group.h @@ -0,0 +1,9 @@ +#ifndef _STATISTICS_TEST_GROUP_H_ +#define _STATISTICS_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(statistics_tests); + +#endif /* _STATISTICS_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_tests.h new file mode 100644 index 0000000..20df03e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_tests.h @@ -0,0 +1,15 @@ +#ifndef _STATISTICS_TESTS_H_ +#define _STATISTICS_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(max_tests); +JTEST_DECLARE_GROUP(mean_tests); +JTEST_DECLARE_GROUP(min_tests); +JTEST_DECLARE_GROUP(power_tests); +JTEST_DECLARE_GROUP(rms_tests); +JTEST_DECLARE_GROUP(std_tests); +JTEST_DECLARE_GROUP(var_tests); + +#endif /* _STATISTICS_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_templates.h new file mode 100644 index 0000000..bc94791 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_templates.h @@ -0,0 +1,120 @@ +#ifndef _SUPPORT_TEMPLATES_H_ +#define _SUPPORT_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "test_templates.h" + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Compare the outputs from the function under test and the reference function. + */ +#define SUPPORT_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_ASSERT_BUFFERS_EQUAL( \ + support_output_ref.data_ptr, \ + support_output_fut.data_ptr, \ + block_size * sizeof(output_type)); \ + } while (0) \ + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define ARM_copy_INPUT_INTERFACE(input, block_size) \ + PAREN(input, support_output_fut.data_ptr, block_size) + +#define REF_copy_INPUT_INTERFACE(input, block_size) \ + PAREN(input, support_output_ref.data_ptr, block_size) + +#define ARM_fill_INPUT_INTERFACE(elt, block_size) \ + PAREN(elt, support_output_fut.data_ptr, block_size) + +#define REF_fill_INPUT_INTERFACE(elt, block_size) \ + PAREN(elt, support_output_ref.data_ptr, block_size) + +#define ARM_x_to_y_INPUT_INTERFACE(input, block_size) \ + PAREN(input, support_output_fut.data_ptr, block_size) + +#define REF_x_to_y_INPUT_INTERFACE(input, block_size) \ + PAREN(input, support_output_ref.data_ptr, block_size) + +/*--------------------------------------------------------------------------------*/ +/* Test Templates */ +/*--------------------------------------------------------------------------------*/ + + +/** + * Specialization of #TEST_TEMPLATE_BUF1_BLK() for support tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define SUPPORT_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name, \ + suffix, \ + input_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_BLK( \ + support_f_all, \ + support_block_sizes, \ + input_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + +/** + * Specialization of #TEST_TEMPLATE_ELT1_BLK() for support tests. + * + * @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and + * REF_xxx_INPUT_INTERFACEs. + */ +#define SUPPORT_DEFINE_TEST_TEMPLATE_ELT1_BLK(fn_name, \ + suffix, \ + elt_type, \ + output_type, \ + comparison_interface) \ + JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test, \ + arm_##fn_name##_##suffix) \ + { \ + TEST_TEMPLATE_ELT1_BLK( \ + support_elts, \ + support_block_sizes, \ + elt_type, \ + output_type, \ + arm_##fn_name##_##suffix, \ + ARM_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + REF_##fn_name##_INPUT_INTERFACE, \ + comparison_interface); \ + } + +#endif /* _SUPPORT_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_data.h new file mode 100644 index 0000000..cc6c636 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_data.h @@ -0,0 +1,31 @@ +#ifndef ARM_SUPPORT_TEST_DATA_H +#define ARM_SUPPORT_TEST_DATA_H + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" + +/*--------------------------------------------------------------------------------*/ +/* Declare Variables */ +/*--------------------------------------------------------------------------------*/ + +/* Input/Output Buffers */ +ARR_DESC_DECLARE(support_output_fut); +ARR_DESC_DECLARE(support_output_ref); + +/* Block Sizes*/ +ARR_DESC_DECLARE(support_block_sizes); + +/* Numbers */ +ARR_DESC_DECLARE(support_elts); + +/* Float Inputs */ +ARR_DESC_DECLARE(support_zeros); +ARR_DESC_DECLARE(support_f_2); +ARR_DESC_DECLARE(support_f_15); +ARR_DESC_DECLARE(support_f_32); +ARR_DESC_DECLARE(support_f_all); + +#endif diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_group.h new file mode 100644 index 0000000..ef3a768 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_group.h @@ -0,0 +1,9 @@ +#ifndef _SUPPORT_TEST_GROUP_H_ +#define _SUPPORT_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(support_tests); + +#endif /* _SUPPORT_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_tests.h new file mode 100644 index 0000000..2eab273 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_tests.h @@ -0,0 +1,11 @@ +#ifndef _SUPPORT_TESTS_H_ +#define _SUPPORT_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(copy_tests); +JTEST_DECLARE_GROUP(fill_tests); +JTEST_DECLARE_GROUP(x_to_y_tests); + +#endif /* _SUPPORT_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/template.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/template.h new file mode 100644 index 0000000..e4577d1 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/template.h @@ -0,0 +1,88 @@ +#ifndef _TEMPLATE_H_ +#define _TEMPLATE_H_ + +/*--------------------------------------------------------------------------------*/ +/* Looping and Iteration */ +/*--------------------------------------------------------------------------------*/ + +/** + * Template for the general structure of a loop. + */ +#define TEMPLATE_LOOP(setup, loop_def, body) \ + do \ + { \ + setup; \ + loop_def { \ + body; \ + } \ + } while (0) + +/** + * Template for looping over an array-like sequence. + */ +#define TEMPLATE_DO_ARR_LIKE(iter_idx, type, \ + arr, arr_length, \ + iter_elem_setup, \ + body) \ + do \ + { \ + TEMPLATE_LOOP( \ + int iter_idx, \ + for(iter_idx = 0; iter_idx < (arr_length); ++iter_idx), \ + iter_elem_setup; \ + body); \ + } while (0) + +/** + * Template for looping over the contents of an array. + */ +#define TEMPLATE_DO_ARR(iter_idx, type, iter_elem, arr, arr_length, body) \ + do \ + { \ + TEMPLATE_DO_ARR_LIKE( \ + iter_idx, type, arr, arr_length, \ + type iter_elem = (arr)[iter_idx], \ + body); \ + } while (0) + +/** + * Template for looping over the contents of an #ARR_DESC. + */ +#define TEMPLATE_DO_ARR_DESC(iter_idx, type, iter_elem, arr_desc, body) \ + do \ + { \ + TEMPLATE_DO_ARR_LIKE( \ + iter_idx, type, arr_desc, (arr_desc).element_count, \ + type iter_elem = ARR_DESC_ELT(type, iter_idx, &(arr_desc)), \ + body); \ + } while (0) + +/*--------------------------------------------------------------------------------*/ +/* Test Definition */ +/*--------------------------------------------------------------------------------*/ + +/** + * Template for the general structure of a test. + */ +#define TEMPLATE_TEST(setup, body, teardown) \ + do \ + { \ + setup; \ + body; \ + teardown; \ + } while (0) + +/** + * Template for calling a function. + * + * @note Surround function arguments with the #PAREN() macro. + * + * @example + * void my_func(int arg1, int arg2); + * + * TEMPLATE_CALL_FN(my_func, PAREN(3, 7)); + */ +#define TEMPLATE_CALL_FN(fn, fn_args) \ + fn fn_args + +#endif /* _TEMPLATE_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h new file mode 100644 index 0000000..700bbe1 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h @@ -0,0 +1,458 @@ +#ifndef _TEST_TEMPLATES_H_ +#define _TEST_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ +#include "template.h" +#include /* memcmp() */ +#include /* PRIu32 */ +#include "math_helper.h" /* arm_snr_f32() */ + +/*--------------------------------------------------------------------------------*/ +/* Function Aliases for use in Templates. */ +/*--------------------------------------------------------------------------------*/ +#define ref_q31_t_to_float ref_q31_to_float +#define ref_q15_t_to_float ref_q15_to_float +#define ref_q7_t_to_float ref_q7_to_float +#define ref_float_to_q31_t ref_float_to_q31 +#define ref_float_to_q15_t ref_float_to_q15 +#define ref_float_to_q7_t ref_float_to_q7 +#define ref_float32_t_to_float ref_copy_f32 +#define ref_float_to_float32_t ref_copy_f32 + + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Call the function-under-test. + */ +#define TEST_CALL_FUT(fut, fut_args) \ + JTEST_COUNT_CYCLES(TEMPLATE_CALL_FN(fut, fut_args)) + +/** + * Call the reference-function. + */ +#define TEST_CALL_REF(ref, ref_args) \ + TEMPLATE_CALL_FN(ref, ref_args) + +/** + * Call the function-under-test and the reference-function. + */ +#define TEST_CALL_FUT_AND_REF(fut, fut_args, ref, ref_args) \ + do { \ + TEST_CALL_FUT(fut, fut_args); \ + TEST_CALL_REF(ref, ref_args); \ + } while (0) + +/** + * This macro eats a variable number of arguments and evaluates to a null + * statement. + */ +#define TEST_NULL_STATEMENT(...) (void) "TEST_NULL_STATEMENT" + +/** + * A function name, Usable in any template where a fut or ref name is accepted, + * that evaluates to a #TEST_NULL_STATEMENT(). + */ +#define TEST_NULL_FN TEST_NULL_STATEMENT + +/** + * Assert that buffers A and B are byte-equivalent for a number of bytes. + */ +#define TEST_ASSERT_BUFFERS_EQUAL(buf_a, buf_b, bytes) \ + do \ + { \ + if (memcmp(buf_a, buf_b, bytes) != 0) \ + { \ + return JTEST_TEST_FAILED; \ + } \ + } while (0) + +/** + * Assert that the two entities are equal. + */ +#define TEST_ASSERT_EQUAL(a, b) \ + do \ + { \ + if ((a) != (b)) \ + { \ + return JTEST_TEST_FAILED; \ + } \ + } while (0) + +/** + * Convert elements to from src_type to float. + */ +#define TEST_CONVERT_TO_FLOAT(src_ptr, dst_ptr, block_size, src_type) \ + do \ + { \ + ref_##src_type##_to_float( \ + src_ptr, \ + dst_ptr, \ + block_size); \ + } while (0) \ + +/** + * Convert elements to from float to dst_type . + */ +#define TEST_CONVERT_FLOAT_TO(src_ptr, dst_ptr, block_size, dst_type) \ + do \ + { \ + ref_float_to_##dst_type( \ + src_ptr, \ + dst_ptr, \ + block_size); \ + } while (0) \ + +/** + * Assert that the SNR between a reference and test sample is above a given + * threshold. + */ +#define TEST_ASSERT_SNR(ref_ptr, tst_ptr, block_size, threshold) \ + do \ + { \ + float32_t snr = arm_snr_f32(ref_ptr, tst_ptr, block_size); \ + if ( snr <= threshold) \ + { \ + JTEST_DUMP_STRF("SNR: %f\n", snr); \ + return JTEST_TEST_FAILED; \ + } \ + } while (0) \ + +/** + * Assert that the SNR between a reference and test sample is above a given + * threshold. Special case for float64_t + */ +#define TEST_ASSERT_DBL_SNR(ref_ptr, tst_ptr, block_size, threshold) \ + do \ + { \ + float64_t snr = arm_snr_f64(ref_ptr, tst_ptr, block_size); \ + if ( snr <= threshold) \ + { \ + JTEST_DUMP_STRF("SNR: %f\n", snr); \ + return JTEST_TEST_FAILED; \ + } \ + } while (0) \ + +/** + * Compare test and reference elements by converting to float and + * calculating an SNR. + * + * This macro is a merger of the #TEST_CONVERT_TO_FLOAT() and + * #TEST_ASSERT_SNR() macros. + */ +#define TEST_CONVERT_AND_ASSERT_SNR(ref_dst_ptr, ref_src_ptr, \ + tst_dst_ptr, tst_src_ptr, \ + block_size, \ + tst_src_type, \ + threshold) \ + do \ + { \ + TEST_CONVERT_TO_FLOAT(ref_src_ptr, \ + ref_dst_ptr, \ + block_size, \ + tst_src_type); \ + TEST_CONVERT_TO_FLOAT(tst_src_ptr, \ + tst_dst_ptr, \ + block_size, \ + tst_src_type); \ + TEST_ASSERT_SNR(ref_dst_ptr, \ + tst_dst_ptr, \ + block_size, \ + threshold); \ + } while (0) + +/** + * Execute statements only if the combination of block size, function type + * specifier, and input ARR_DESC_t are valid. + * + * @example An ARR_DESC_t that contains 64 bytes cant service a 32 element + * block size if they are extracted in float32_t increments. + * + * 8 * 32 = 256 > 64. + */ +#define TEST_DO_VALID_BLOCKSIZE(block_size, fn_type_spec, \ + input_arr_desc, body) \ + do \ + { \ + if (block_size * sizeof(fn_type_spec) <= \ + ARR_DESC_BYTES(input_arr_desc)) \ + { \ + JTEST_DUMP_STRF("Block Size: %"PRIu32"\n", block_size); \ + body; \ + } \ + } while (0) \ + +/** + * Template for tests that rely on one input buffer and a blocksize parameter. + * + * The buffer is an #ARR_DESC_t. It is iterated over and it's values are + * passed to the function under test and reference functions through their + * appropriate argument interfaces. The argument interfaces this template to + * execute structurally similar functions. + * + */ +#define TEST_TEMPLATE_BUF1_BLK(arr_desc_inputs, \ + arr_desc_block_sizes, \ + input_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \ + , \ + TEMPLATE_DO_ARR_DESC( \ + block_size_idx, uint32_t, block_size, arr_desc_block_sizes \ + , \ + void * input_data_ptr = input_ptr->data_ptr; \ + \ + TEST_DO_VALID_BLOCKSIZE( \ + block_size, input_type, input_ptr \ + , \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_data_ptr, block_size), \ + ref, ref_arg_interface( \ + input_data_ptr, block_size)); \ + \ + compare_interface(block_size, output_type)))); \ + \ + return JTEST_TEST_PASSED; \ + \ + } while (0) + +/** + * Template for tests that rely on an input buffer and an element. + * + * An element can is any thing which doesn't walk and talk like a + * sequence. Examples include numbers, and structures. + */ +#define TEST_TEMPLATE_BUF1_ELT1(arr_desc_inputs, \ + arr_desc_elts, \ + input_type, elt_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \ + , \ + TEMPLATE_DO_ARR_DESC( \ + elt_idx, elt_type, elt, arr_desc_elts \ + , \ + void * input_data_ptr = input_ptr->data_ptr; \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface(input_data_ptr, elt), \ + ref, ref_arg_interface(input_data_ptr, elt)); \ + \ + compare_interface(output_type))); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Template for tests that rely on an input buffer, an element, and a blocksize + * parameter. + */ +#define TEST_TEMPLATE_BUF1_ELT1_BLK(arr_desc_inputs, \ + arr_desc_elts, \ + arr_desc_block_sizes, \ + input_type, elt_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface); \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + inut_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \ + , \ + TEMPLATE_DO_ARR_DESC( \ + block_size_idx, uint32_t, block_size, \ + arr_desc_block_sizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + elt_idx, elt_type, elt, arr_desc_elts \ + , \ + void * input_data_ptr = input_ptr->data_ptr; \ + TEST_DO_VALID_BLOCKSIZE( \ + block_size, input_type, input_ptr, \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_data_ptr, elt, block_size), \ + ref, ref_arg_interface( \ + input_data_ptr, elt, block_size)); \ + compare_interface(block_size, output_type))))); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Template for tests that rely on an input buffer, two elements, and a blocksize + * parameter. + */ +#define TEST_TEMPLATE_BUF1_ELT2_BLK(arr_desc_inputs, \ + arr_desc_elt1s, \ + arr_desc_elt2s, \ + arr_desc_block_sizes, \ + input_type, elt1_type, \ + elt2_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + inut_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs \ + , \ + TEMPLATE_DO_ARR_DESC( \ + block_size_idx, uint32_t, block_size, \ + arr_desc_block_sizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + elt1_idx, elt1_type, elt1, arr_desc_elt1s \ + , \ + TEMPLATE_DO_ARR_DESC( \ + elt2_idx, elt2_type, elt2, arr_desc_elt2s \ + , \ + void * input_data_ptr = input_ptr->data_ptr; \ + TEST_DO_VALID_BLOCKSIZE( \ + block_size, input_type, input_ptr, \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_data_ptr, elt1, elt2, block_size), \ + ref, ref_arg_interface( \ + input_data_ptr, elt1, elt2, block_size)); \ + compare_interface(block_size, output_type)))))); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Template for tests that rely on two input buffers and a blocksize parameter. + * + * The two #ARR_DESC_t, input buffers are iterated through in parallel. The + * length of the first #ARR_DESC_t determines the length of the iteration. + */ +#define TEST_TEMPLATE_BUF2_BLK(arr_desc_inputs_a, \ + arr_desc_inputs_b, \ + arr_desc_block_sizes, \ + input_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + /* Iterate over two input arrays in parallel.*/ \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs_a \ + , \ + TEMPLATE_DO_ARR_DESC( \ + block_size_idx, uint32_t, block_size, arr_desc_block_sizes, \ + void * input_a_ptr = input_ptr->data_ptr; \ + void * input_b_ptr = ARR_DESC_ELT( \ + ARR_DESC_t *, input_idx, \ + &(arr_desc_inputs_b))->data_ptr; \ + \ + TEST_DO_VALID_BLOCKSIZE( \ + block_size, input_type, input_ptr \ + , \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_a_ptr, input_b_ptr, block_size), \ + ref, ref_arg_interface( \ + input_a_ptr, input_b_ptr, block_size)); \ + \ + compare_interface(block_size, output_type)))); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Test template that uses a single element. + */ +#define TEST_TEMPLATE_ELT1(arr_desc_elts, \ + elt_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + elt_idx, elt_type, elt, arr_desc_elts \ + , \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + elt), \ + ref, ref_arg_interface( \ + elt)); \ + /* Comparison interfaces typically accept */ \ + /* a block_size. Pass a dummy value 1.*/ \ + compare_interface(1, output_type)); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Test template that iterates over two sets of elements in parallel. + * + * The length of the first set determines the number of iteratsions. + */ +#define TEST_TEMPLATE_ELT2(arr_desc_elts_a, \ + arr_desc_elts_b, \ + elt_a_type, elt_b_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + elt_a_idx, elt_a_type, elt_a, arr_desc_elts_a \ + , \ + elt_b_type * elt_b = ARR_DESC_ELT( \ + elt_b_type, \ + elt_a_idx, \ + arr_desc_elts_b); \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + elt_a, elt_b), \ + ref, ref_arg_interface( \ + elt_a, elt_b)); \ + /* Comparison interfaces typically accept */ \ + /* a block_size. Pass a dummy value 1.*/ \ + compare_interface(1, output_type)); \ + return JTEST_TEST_PASSED; \ + } while (0) + +/** + * Test template that uses an element and a block size. + */ +#define TEST_TEMPLATE_ELT1_BLK(arr_desc_elts, \ + arr_desc_block_sizes, \ + elt_type, output_type, \ + fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + compare_interface) \ + do \ + { \ + TEMPLATE_DO_ARR_DESC( \ + block_size_idx, uint32_t, block_size, \ + arr_desc_block_sizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + elt_idx, elt_type, elt, arr_desc_elts \ + , \ + JTEST_DUMP_STRF("Block Size: %d\n", \ + (int)block_size); \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + elt, block_size), \ + ref, ref_arg_interface( \ + elt, block_size)); \ + compare_interface(block_size, output_type))); \ + return JTEST_TEST_PASSED; \ + } while (0) + +#endif /* _TEST_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_templates.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_templates.h new file mode 100644 index 0000000..c6314b5 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_templates.h @@ -0,0 +1,181 @@ +#ifndef _TRANSFORM_TEMPLATES_H_ +#define _TRANSFORM_TEMPLATES_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "test_templates.h" +#include /* memcpy() */ + +/*--------------------------------------------------------------------------------*/ +/* Group Specific Templates */ +/*--------------------------------------------------------------------------------*/ + +/** + * Comparison SNR thresholds for the data types used in transform_tests. + */ +#define TRANSFORM_SNR_THRESHOLD_float32_t 90 +#define TRANSFORM_SNR_THRESHOLD_q31_t 90 +#define TRANSFORM_SNR_THRESHOLD_q15_t 30 + +#define DCT4_TRANSFORM_SNR_THRESHOLD_float32_t 80 +#define DCT4_TRANSFORM_SNR_THRESHOLD_q31_t 75 +#define DCT4_TRANSFORM_SNR_THRESHOLD_q15_t 11 + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. + */ +#define TRANSFORM_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + transform_fft_output_f32_ref, \ + (output_type *) transform_fft_output_ref, \ + transform_fft_output_f32_fut, \ + (output_type *) transform_fft_output_fut, \ + block_size, \ + output_type, \ + TRANSFORM_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) + +/** + * Compare the outputs from the function under test and the reference + * function using SNR. + */ +#define DCT_TRANSFORM_SNR_COMPARE_INTERFACE(block_size, \ + output_type) \ + do \ + { \ + TEST_CONVERT_AND_ASSERT_SNR( \ + transform_fft_output_f32_ref, \ + (output_type *) transform_fft_output_ref, \ + transform_fft_output_f32_fut, \ + (output_type *) transform_fft_output_fut, \ + block_size, \ + output_type, \ + DCT4_TRANSFORM_SNR_THRESHOLD_##output_type \ + ); \ + } while (0) \ + +/** + * Specialization on #TRANSFORM_SNR_COMPARE_INTERFACE() to fix the block_size + * for complex datasets. + */ +#define TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE(block_size, output_type) \ + /* Complex numbers have two components*/ \ + TRANSFORM_SNR_COMPARE_INTERFACE(block_size * 2, output_type ) + +/** + * This macro copys data from the input_ptr into input arrays. + * + * Some functions modify their input data; in order to provide the same data to + * multiple tests, copies must be made so the changes from one function don't + * impact the others. + */ +#define TRANSFORM_COPY_INPUTS(input_ptr, \ + bytes) \ + do \ + { \ + memcpy( \ + transform_fft_input_fut, \ + input_ptr, \ + bytes); \ + memcpy( \ + transform_fft_input_ref, \ + input_ptr, \ + bytes); \ + } while (0) + +/** + * This macro copys data from the input_ptr into input arrays. It also creates + * symmetric input data for rfft inverse. + * + * The 4.534234f just makes the middle entry of the array semi random. It's + * actual value doesn't seem to matter much. + * + * Some functions modify their input data; in order to provide the same data to + * multiple tests, copies must be made so the changes from one function don't + * impact the others. + */ +#define TRANSFORM_PREPARE_INVERSE_INPUTS(input_ptr, \ + fftlen, input_type, bytes) \ + do \ + { \ + uint32_t i; \ + \ + memcpy( \ + transform_fft_input_fut, \ + input_ptr, \ + bytes); \ + \ + ((input_type*)transform_fft_input_fut)[1] = 0; \ + ((input_type*)transform_fft_input_fut)[fftlen + 0] = 0; \ + ((input_type*)transform_fft_input_fut)[fftlen + 1] = 0; \ + for(i=1;i>= 1; \ + *((type*)transform_fft_inplace_input_ref + i) >>= 1;} \ + } while (0) + +/** + * This macro copys data from the input_ptr into the in-place input arrays. + * + * Some functions modify their input data; in order to provide the same data to + * multiple tests, copies must be made so the changes from one function don't + * impact the others. + */ +#define TRANSFORM_PREPARE_INPLACE_INPUTS(input_ptr, \ + bytes) \ + do \ + { \ + memcpy( \ + transform_fft_inplace_input_fut, \ + input_ptr, \ + bytes); \ + memcpy( \ + transform_fft_inplace_input_ref, \ + input_ptr, \ + bytes); \ + } while (0) + + +#endif /* _TRANSFORM_TEMPLATES_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_data.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_data.h new file mode 100644 index 0000000..bda5e12 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_data.h @@ -0,0 +1,48 @@ +#ifndef _TRANSFORM_TEST_DATA_H_ +#define _TRANSFORM_TEST_DATA_H_ + +/*--------------------------------------------------------------------------------*/ +/* Includes */ +/*--------------------------------------------------------------------------------*/ + +#include "arr_desc.h" +#include "arm_math.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +#define TRANSFORM_MAX_FFT_LEN 4096 +#define TRANFORM_BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Variable Declarations */ +/*--------------------------------------------------------------------------------*/ + +/* Lengths are multiplied by 2 to accomodate complex numbers*/ +extern float32_t transform_fft_output_fut[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t transform_fft_output_ref[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t transform_fft_input_fut[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t transform_fft_input_ref[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t transform_fft_output_f32_fut[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t transform_fft_output_f32_ref[TRANSFORM_MAX_FFT_LEN * 2]; +extern float32_t * transform_fft_inplace_input_fut; +extern float32_t * transform_fft_inplace_input_ref; +extern float32_t transform_fft_f32_inputs[TRANSFORM_MAX_FFT_LEN * 2]; +extern q31_t transform_fft_q31_inputs[TRANSFORM_MAX_FFT_LEN * 2]; +extern q15_t * transform_fft_q15_inputs; +extern q15_t dct4_transform_fft_q15_inputs[TRANSFORM_MAX_FFT_LEN * 2]; + +/* FFT Lengths */ +ARR_DESC_DECLARE(transform_radix2_fftlens); +ARR_DESC_DECLARE(transform_radix4_fftlens); +ARR_DESC_DECLARE(transform_rfft_fftlens); +ARR_DESC_DECLARE(transform_rfft_fast_fftlens); +ARR_DESC_DECLARE(transform_dct_fftlens); + +/* CFFT Structs */ +ARR_DESC_DECLARE(transform_cfft_f32_structs); +ARR_DESC_DECLARE(transform_cfft_q31_structs); +ARR_DESC_DECLARE(transform_cfft_q15_structs); + +#endif /* _TRANSFORM_TEST_DATA_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_group.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_group.h new file mode 100644 index 0000000..c1c7c9e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_group.h @@ -0,0 +1,9 @@ +#ifndef _TRANSFORM_TEST_GROUP_H_ +#define _TRANSFORM_TEST_GROUP_H_ + +/*--------------------------------------------------------------------------------*/ +/* Declare Test Groups */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(transform_tests); + +#endif /* _TRANSFORM_TEST_GROUP_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_tests.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_tests.h new file mode 100644 index 0000000..874c83f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_tests.h @@ -0,0 +1,13 @@ +#ifndef _TRANSFORM_TESTS_H_ +#define _TRANSFORM_TESTS_H_ + +/*--------------------------------------------------------------------------------*/ +/* Test/Group Declarations */ +/*--------------------------------------------------------------------------------*/ +JTEST_DECLARE_GROUP(cfft_tests); +JTEST_DECLARE_GROUP(cfft_family_tests); +JTEST_DECLARE_GROUP(dct4_tests); +JTEST_DECLARE_GROUP(rfft_tests); +JTEST_DECLARE_GROUP(rfft_fast_tests); + +#endif /* _TRANSFORM_TESTS_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/type_abbrev.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/type_abbrev.h new file mode 100644 index 0000000..5909124 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/type_abbrev.h @@ -0,0 +1,37 @@ +#ifndef _TYPE_ABBREV_H_ +#define _TYPE_ABBREV_H_ + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +/** + * Expand the abbreviation for a type into the type itself. + */ +#define TYPE_FROM_ABBREV(abbrev) \ + TYPE_ABBREV_##abbrev \ + +/** + * Expand the type to an abbreviation for that type. + * + * Inverse of #TYPE_FROM_ABBREV(). + * + * @note Should be able to get a type back by writing. + * TYPE_FROM_ABBREV(ABBREV_FROM_TYPE(type)) + */ +#define ABBREV_FROM_TYPE(type) \ + TYPE_SUFFIX_##type + +#define TYPE_ABBREV_f64 float64_t +#define TYPE_ABBREV_f32 float32_t +#define TYPE_ABBREV_q31 q31_t +#define TYPE_ABBREV_q15 q15_t +#define TYPE_ABBREV_q7 q7_t + +#define TYPE_SUFFIX_float64_t f64 +#define TYPE_SUFFIX_float32_t f32 +#define TYPE_SUFFIX_q31_t q31 +#define TYPE_SUFFIX_q15_t q15 +#define TYPE_SUFFIX_q7_t q7 + +#endif /* _TYPE_ABBREV_H_ */ diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c new file mode 100644 index 0000000..ffac3df --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c @@ -0,0 +1,52 @@ +/*---------------------------------------------------------------------------- + * Name: Retarget.c + * Purpose: 'Retarget' layer for target-dependent low level functions + * Note(s): + *---------------------------------------------------------------------------- + * This file is part of the uVision/ARM development tools. + * This software may only be used under the terms of a valid, current, + * end user licence from KEIL for a compatible version of KEIL software + * development tools. Nothing else gives you the right to use this software. + * + * This software is supplied "AS IS" without warranties of any kind. + * + * Copyright (c) 2011 Keil - An ARM Company. All rights reserved. + *----------------------------------------------------------------------------*/ + +#include +#include +#include "Serial.h" + +#pragma import(__use_no_semihosting_swi) + + + +struct __FILE { int handle; /* Add whatever you need here */ }; +FILE __stdout; +FILE __stdin; + + +int fputc(int c, FILE *f) { + return (SER_PutChar(c)); +} + + +int fgetc(FILE *f) { + return (SER_GetChar()); +} + + +int ferror(FILE *f) { + /* Your implementation of ferror */ + return EOF; +} + + +void _ttywrch(int c) { + SER_PutChar(c); +} + + +void _sys_exit(int return_code) { +label: goto label; /* endless loop */ +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s new file mode 100644 index 0000000..fa814eb --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s @@ -0,0 +1,195 @@ +;/* File: startup_armv6-m.s +; * Purpose: startup file for armv7-m architecture devices. +; * Should be used with ARMCC +; * Version: V2.00 +; * Date: 16 November 2015 +; * +; */ +;/* Copyright (c) 2011 - 2014 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ +;/* +; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + BKPT #0 + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + BKPT #0 + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + +;/* +; __user_setup_stackheap() returns the: +; - heap base in r0 (if the program uses the heap) +; - stack base in sp +; - heap limit in r2 (if the program uses the heap and uses two-region memory). +; */ + EXPORT __user_setup_stackheap + +__user_setup_stackheap PROC + LDR R0, = __initial_sp + MOV SP, R0 + IF Heap_Size > 0 + LDR R2, = __heap_limit + LDR R0, = __heap_base + ELSE + MOV R0, #0 + MOV R2, #0 + ENDIF + BX LR + ENDP + + +;/* +;__user_initial_stackheap() returns the: +; - heap base in r0 +; - stack base in r1, that is, the highest address in the stack region +; - heap limit in r2 +; - stack limit in r3, that is, the lowest address in the stack region. +; */ +; +;/* DEPRICATED +; EXPORT __user_initial_stackheap +; +;__user_initial_stackheap PROC +; LDR R0, = Heap_Mem +; LDR R1, =(Stack_Mem + Stack_Size) +; LDR R2, = (Heap_Mem + Heap_Size) +; LDR R3, = Stack_Mem +; BX LR +; ENDP +; */ + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s new file mode 100644 index 0000000..899f2de --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s @@ -0,0 +1,218 @@ +;/* File: startup_armv7-m.s +; * Purpose: startup file for armv7-m architecture devices. +; * Should be used with ARMCC +; * Version: V2.00 +; * Date: 16 November 2015 +; * +; */ +;/* Copyright (c) 2011 - 2014 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ +;/* +; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + BKPT #0 + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + BKPT #0 + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + BKPT #0 + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + BKPT #0 + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + BKPT #0 + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + +;/* +; __user_setup_stackheap() returns the: +; - heap base in r0 (if the program uses the heap) +; - stack base in sp +; - heap limit in r2 (if the program uses the heap and uses two-region memory). +; */ + EXPORT __user_setup_stackheap + +__user_setup_stackheap PROC + LDR R0, = __initial_sp + MOV SP, R0 + IF Heap_Size > 0 + LDR R2, = __heap_limit + LDR R0, = __heap_base + ELSE + MOV R0, #0 + MOV R2, #0 + ENDIF + BX LR + ENDP + + +;/* +;__user_initial_stackheap() returns the: +; - heap base in r0 +; - stack base in r1, that is, the highest address in the stack region +; - heap limit in r2 +; - stack limit in r3, that is, the lowest address in the stack region. +; */ +; +;/* DEPRICATED +; EXPORT __user_initial_stackheap +; +;__user_initial_stackheap PROC +; LDR R0, = Heap_Mem +; LDR R1, =(Stack_Mem + Stack_Size) +; LDR R2, = (Heap_Mem + Heap_Size) +; LDR R3, = Stack_Mem +; BX LR +; ENDP +; */ + + ALIGN + + ENDIF + + + END diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S new file mode 100644 index 0000000..2e60478 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S @@ -0,0 +1,203 @@ +/* File: startup_armv6-m.S + * Purpose: startup file for armv6-m architecture devices. + * Should be used with ARMCLANG + * Version: V2.00 + * Date: 16 November 2015 + * + */ +/* Copyright (c) 2011 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ +/* + ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + .syntax unified + .arch armv6-m + +/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */ +.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */ + + +/* + ; Stack Configuration + ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + ; +*/ + .equ Stack_Size, 0x00000400 + + .section STACK, "w" + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size +__StackTop: /* formerly known as __initial_sp */ + + +/* + ; Heap Configuration + ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + ; +*/ + .equ Heap_Size, 0x00000C00 + + .section HEAP, "w" + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif +__HeapLimit: + + + .section RESET, "x" + .align 2 + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ +__Vectors_End: + + .equ __Vectors_Size, __Vectors_End - __Vectors + + + .text + .thumb + .align 2 + + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + .thumb_func +Reset_Handler: + bl SystemInit + bl __main + + .globl NMI_Handler + .weak NMI_Handler + .type NMI_Handler, %function + .thumb_func +NMI_Handler: + bkpt #0 + b . + + .globl HardFault_Handler + .weak HardFault_Handler + .type HardFault_Handler, %function + .thumb_func +HardFault_Handler: + bkpt #0 + b . + + .globl SVC_Handler + .weak SVC_Handler + .type SVC_Handler, %function + .thumb_func +SVC_Handler: + bkpt #0 + b . + + .globl PendSV_Handler + .weak PendSV_Handler + .type PendSV_Handler, %function + .thumb_func +PendSV_Handler: + bkpt #0 + b . + + .globl SysTick_Handler + .weak SysTick_Handler + .type SysTick_Handler, %function + .thumb_func +SysTick_Handler: + bkpt #0 + b . + + + .global __use_two_region_memory + +/* + __user_setup_stackheap() returns the: + - heap base in r0 (if the program uses the heap) + - stack base in sp + - heap limit in r2 (if the program uses the heap and uses two-region memory). + */ + .globl __user_setup_stackheap + .type __user_setup_stackheap, %function + .thumb_func +__user_setup_stackheap: + ldr r0, =__StackTop + mov sp, r0 + .if Heap_Size + ldr r0, =__HeapBase + ldr r2, =__HeapLimit + .else + mov r0, #0 + mov r2, #0 + .endif + bx lr + + +/* +__user_initial_stackheap() returns the: + - heap base in r0 + - stack base in r1, that is, the highest address in the stack region + - heap limit in r2 + - stack limit in r3, that is, the lowest address in the stack region. + */ +/* DEPRICATED + .globl __user_initial_stackheap + .type __user_initial_stackheap, %function + .thumb_func +__user_initial_stackheap: + ldr r0, = __HeapBase + ldr r1, = __StackTop + ldr r2, = __HeapLimit + ldr r3, = __StackLimit + bx lr +*/ + + .end diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S new file mode 100644 index 0000000..93ba4a9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S @@ -0,0 +1,235 @@ +/* File: startup_armv7-m.S + * Purpose: startup file for armv7-m architecture devices. + * Should be used with ARMCLANG + * Version: V2.00 + * Date: 16 November 2015 + * + */ +/* Copyright (c) 2011 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ +/* + ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + .syntax unified + .arch armv6-m + +/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */ +.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */ + + +/* + ; Stack Configuration + ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + ; +*/ + .equ Stack_Size, 0x00000400 + + .section STACK, "w" + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size +__StackTop: /* formerly known as __initial_sp */ + + +/* + ; Heap Configuration + ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + ; +*/ + .equ Heap_Size, 0x00000C00 + + .section HEAP, "w" + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif +__HeapLimit: + + + .section RESET, "x" + .align 2 + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ +__Vectors_End: + + .equ __Vectors_Size, __Vectors_End - __Vectors + + + .text + .thumb + .align 2 + + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + .thumb_func +Reset_Handler: + bl SystemInit + bl __main + + .globl NMI_Handler + .weak NMI_Handler + .type NMI_Handler, %function + .thumb_func +NMI_Handler: + bkpt #0 + b . + + .globl HardFault_Handler + .weak HardFault_Handler + .type HardFault_Handler, %function + .thumb_func +HardFault_Handler: + bkpt #0 + b . + + .globl MemManage_Handler + .weak MemManage_Handler + .type MemManage_Handler, %function + .thumb_func +MemManage_Handler: + bkpt #0 + b . + + .globl BusFault_Handler + .weak BusFault_Handler + .type BusFault_Handler, %function + .thumb_func +BusFault_Handler: + bkpt #0 + b . + + .globl UsageFault_Handler + .weak UsageFault_Handler + .type UsageFault_Handler, %function + .thumb_func +UsageFault_Handler: + bkpt #0 + b . + + .globl SVC_Handler + .weak SVC_Handler + .type SVC_Handler, %function + .thumb_func +SVC_Handler: + bkpt #0 + b . + + .globl DebugMon_Handler + .weak DebugMon_Handler + .type DebugMon_Handler, %function + .thumb_func +DebugMon_Handler: + bkpt #0 + b . + + .globl PendSV_Handler + .weak PendSV_Handler + .type PendSV_Handler, %function + .thumb_func +PendSV_Handler: + bkpt #0 + b . + + .globl SysTick_Handler + .weak SysTick_Handler + .type SysTick_Handler, %function + .thumb_func +SysTick_Handler: + bkpt #0 + b . + + + .global __use_two_region_memory + +/* + __user_setup_stackheap() returns the: + - heap base in r0 (if the program uses the heap) + - stack base in sp + - heap limit in r2 (if the program uses the heap and uses two-region memory). + */ + .globl __user_setup_stackheap + .type __user_setup_stackheap, %function + .thumb_func +__user_setup_stackheap: + ldr r0, =__StackTop + mov sp, r0 + .if Heap_Size + ldr r0, =__HeapBase + ldr r2, =__HeapLimit + .else + mov r0, #0 + mov r2, #0 + .endif + bx lr + + +/* +__user_initial_stackheap() returns the: + - heap base in r0 + - stack base in r1, that is, the highest address in the stack region + - heap limit in r2 + - stack limit in r3, that is, the lowest address in the stack region. + */ +/* DEPRICATED + .globl __user_initial_stackheap + .type __user_initial_stackheap, %function + .thumb_func +__user_initial_stackheap: + ldr r0, = __HeapBase + ldr r1, = __StackTop + ldr r2, = __HeapLimit + ldr r3, = __StackLimit + bx lr +*/ + + .end diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c new file mode 100644 index 0000000..0ab6c13 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c @@ -0,0 +1,106 @@ +/*---------------------------------------------------------------------------- + * Name: Retarget.c + * Purpose: 'Retarget' layer for target-dependent low level functions + * Note(s): + *---------------------------------------------------------------------------- + * This file is part of the uVision/ARM development tools. + * This software may only be used under the terms of a valid, current, + * end user licence from KEIL for a compatible version of KEIL software + * development tools. Nothing else gives you the right to use this software. + * + * This software is supplied "AS IS" without warranties of any kind. + * + * Copyright (c) 2012 Keil - An ARM Company. All rights reserved. + *----------------------------------------------------------------------------*/ + +#include +#include +#include + +int SER_PutChar (int c) { + + return (c); +} + +int SER_GetChar (void) { + + return (-1); +} + +/*-- GCC - Newlib runtime support --------------------------------------------*/ + +extern int __HeapBase; +extern int __HeapLimit; + +int _open (const char * path, int flags, ...) +{ + return (-1); +} + +int _close (int fd) +{ + return (-1); +} + +int _lseek (int fd, int ptr, int dir) +{ + return (0); +} + +int __attribute__((weak)) _fstat (int fd, struct stat * st) +{ + memset (st, 0, sizeof (* st)); + st->st_mode = S_IFCHR; + return (0); +} + +int _isatty (int fd) +{ + return (1); +} + +int _read (int fd, char * ptr, int len) +{ + char c; + int i; + + for (i = 0; i < len; i++) + { + c = SER_GetChar(); + if (c == 0x0D) break; + *ptr++ = c; + SER_PutChar(c); + } + return (len - i); +} + +int _write (int fd, char * ptr, int len) +{ + int i; + + for (i = 0; i < len; i++) SER_PutChar (*ptr++); + return (i); +} + +caddr_t _sbrk (int incr) +{ + static char * heap; + char * prev_heap; + + if (heap == NULL) + { + heap = (char *)&__HeapBase; + } + + prev_heap = heap; + + if ((heap + incr) > (char *)&__HeapLimit) + { + errno = ENOMEM; + return (caddr_t) -1; + } + + heap += incr; + + return (caddr_t) prev_heap; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S new file mode 100644 index 0000000..c928912 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S @@ -0,0 +1,263 @@ +/* File: startup_armv6-m.S + * Purpose: startup file for armv6-m architecture devices. + * Should be used with GCC for ARM Embedded Processors + * Version: V2.00 + * Date: 16 November 2015 + * + */ +/* Copyright (c) 2011 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00000400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000C00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + bkpt #0 + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + .end diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S new file mode 100644 index 0000000..2320877 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S @@ -0,0 +1,257 @@ +/* File: startup_armv7-m.S + * Purpose: startup file for armv7-m architecture devices. + * Should be used with GCC for ARM Embedded Processors + * Version: V2.00 + * Date: 16 November 2015 + * + */ +/* Copyright (c) 2011 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00000400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000C00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + bkpt #0 + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + .end diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S new file mode 100644 index 0000000..1826a78 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S @@ -0,0 +1,62 @@ + +#if defined (__CC_ARM) + #if (defined (ARM_MATH_CM0)) + #include "ARMCC\startup_armv6-m.s" + #elif (defined (ARM_MATH_CM0P)) + #include "ARMCC\startup_armv6-m.s" + #elif (defined (ARM_MATH_CM3)) + #include "ARMCC\startup_armv7-m.s" + #elif (defined (ARM_MATH_CM4)) + #include "ARMCC\startup_armv7-m.s" + #elif (defined (ARM_MATH_CM7)) + #include "ARMCC\startup_armv7-m.s" + #elif (defined (ARM_MATH_ARMV8MBL)) + #include "ARMCC\startup_armv6-m.s" + #elif (defined (ARM_MATH_ARMV8MML)) + #include "ARMCC\startup_armv7-m.s" + #else + #error "No appropriate startup file found!" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if (defined (ARM_MATH_CM0)) + #include "ARMCLANG\startup_armv6-m.S" + #elif (defined (ARM_MATH_CM0P)) + #include "ARMCLANG\startup_armv6-m.S" + #elif (defined (ARM_MATH_CM3)) + #include "ARMCLANG\startup_armv7-m.S" + #elif (defined (ARM_MATH_CM4)) + #include "ARMCLANG\startup_armv7-m.S" + #elif (defined (ARM_MATH_CM7)) + #include "ARMCLANG\startup_armv7-m.S" + #elif (defined (ARM_MATH_ARMV8MBL)) + #include "ARMCLANG\startup_armv6-m.S" + #elif (defined (ARM_MATH_ARMV8MML)) + #include "ARMCLANG\startup_armv7-m.S" + #else + #error "No appropriate startup file found!" + #endif + +#elif defined (__GNUC__) + #if (defined (ARM_MATH_CM0)) + #include "GCC\startup_armv6-m.S" + #elif (defined (ARM_MATH_CM0P)) + #include "GCC\startup_armv6-m.S" + #elif (defined (ARM_MATH_CM3)) + #include "GCC\startup_armv7-m.S" + #elif (defined (ARM_MATH_CM4)) + #include "GCC\startup_armv7-m.S" + #elif (defined (ARM_MATH_CM7)) + #include "GCC\startup_armv7-m.S" + #elif (defined (ARM_MATH_ARMV8MBL)) + #include "GCC\startup_armv6-m.S" + #elif (defined (ARM_MATH_ARMV8MML)) + #include "GCC\startup_armv7-m.S" + #else + #error "No appropriate startup file found!" + #endif + +#else + #error "Compiler not supported!" +#endif + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c new file mode 100644 index 0000000..b272255 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c new file mode 100644 index 0000000..791ee34 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c @@ -0,0 +1,82 @@ +/**************************************************************************//** + * @file system_ARMCM23.c + * @brief CMSIS Device System Source File for + * ARMCM23 Device Series + * @version V5.00 + * @date 21. October 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM23.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.c new file mode 100644 index 0000000..2544c43 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c new file mode 100644 index 0000000..287119c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c @@ -0,0 +1,99 @@ +/**************************************************************************//** + * @file system_ARMCM33.c + * @brief CMSIS Device System Source File for + * ARMCM33 Device Series + * @version V5.00 + * @date 02. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" +#elif defined (ARMCM33_TZ) + #include "ARMCM33_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#elif defined (ARMCM33_DSP_FP) + #include "ARMCM33_DSP_FP.h" +#elif defined (ARMCM33_DSP_FP_TZ) + #include "ARMCM33_DSP_FP_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */ + (3U << 11U*2U) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c new file mode 100644 index 0000000..cea212e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */ + (3U << 11U*2U) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c new file mode 100644 index 0000000..6a99c08 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */ + (3U << 11U*2U) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c new file mode 100644 index 0000000..7fda345 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMSC000.c + * @brief CMSIS Device System Source File for + * for ARMSC000 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMSC000.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c new file mode 100644 index 0000000..3db4ee7 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file system_ARMSC300.c + * @brief CMSIS Device System Source File for + * ARMSC300 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMSC300.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c new file mode 100644 index 0000000..8310b8f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c @@ -0,0 +1,76 @@ +/**************************************************************************//** + * @file system_ARMv8MBL.c + * @brief CMSIS Device System Source File for + * ARMv8MBL Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMv8MBL.h" + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMv8MBL.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c new file mode 100644 index 0000000..bd77100 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c @@ -0,0 +1,99 @@ +/**************************************************************************//** + * @file system_ARMv8MML.c + * @brief CMSIS Device System Source File for + * ARMv8MML Device Series + * @version V5.00 + * @date 02. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMv8MML) + #include "ARMv8MML.h" +#elif defined (ARMv8MML_DSP) + #include "ARMv8MML_DSP.h" +#elif defined (ARMv8MML_SP) + #include "ARMv8MML_SP.h" +#elif defined (ARMv8MML_DSP_SP) + #include "ARMv8MML_DSP_SP.h" +#elif defined (ARMv8MML_DP) + #include "ARMv8MML_DP.h" +#elif defined (ARMv8MML_DSP_DP) + #include "ARMv8MML_DSP_DP.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMv8MML.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */ + (3U << 11U*2U) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.c new file mode 100644 index 0000000..37d82ab --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.c @@ -0,0 +1,27 @@ + +#if (defined (ARMCM0)) + #include "system_ARMCM0.c" + +#elif (defined (ARMCM0P)) + #include "system_ARMCM0plus.c" + +#elif (defined (ARMCM3)) + #include "system_ARMCM3.c" + +#elif (defined (ARMCM4) || defined (ARMCM4_FP)) + #include "system_ARMCM4.c" + +#elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP)) + #include "system_ARMCM7.c" + +#elif defined (ARMv8MBL) + #include "system_ARMv8MBL.c" + +#elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \ + defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \ + defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) ) + #include "system_ARMv8MML.c" + +#else + #error "No appropriate system file found!" +#endif diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c new file mode 100644 index 0000000..7b7a8fd --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c @@ -0,0 +1,30 @@ +#include "jtest.h" +#include "basic_math_test_group.h" +#include "complex_math_test_group.h" +#include "controller_test_group.h" +#include "fast_math_test_group.h" +#include "filtering_test_group.h" +#include "matrix_test_group.h" +#include "statistics_test_group.h" +#include "support_test_group.h" +#include "transform_test_group.h" +#include "intrinsics_test_group.h" + +JTEST_DEFINE_GROUP(all_tests) +{ + /* + To skip a test, comment it out + */ + JTEST_GROUP_CALL(basic_math_tests); + JTEST_GROUP_CALL(complex_math_tests); + JTEST_GROUP_CALL(controller_tests); + JTEST_GROUP_CALL(fast_math_tests); + JTEST_GROUP_CALL(filtering_tests); + JTEST_GROUP_CALL(matrix_tests); + JTEST_GROUP_CALL(statistics_tests); + JTEST_GROUP_CALL(support_tests); + JTEST_GROUP_CALL(transform_tests); + JTEST_GROUP_CALL(intrinsics_tests); + + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c new file mode 100644 index 0000000..6e6bedb --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c @@ -0,0 +1,32 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_ABS_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + abs, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix)) + +JTEST_ARM_ABS_TEST(f32); +JTEST_ARM_ABS_TEST(q31); +JTEST_ARM_ABS_TEST(q15); +JTEST_ARM_ABS_TEST(q7 ); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(abs_tests) +{ + JTEST_TEST_CALL(arm_abs_f32_test); + JTEST_TEST_CALL(arm_abs_q31_test); + JTEST_TEST_CALL(arm_abs_q15_test); + JTEST_TEST_CALL(arm_abs_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c new file mode 100644 index 0000000..a2d043c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_ADD_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + add, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + BASIC_MATH_COMPARE_INTERFACE) + +JTEST_ARM_ADD_TEST(f32); +JTEST_ARM_ADD_TEST(q31); +JTEST_ARM_ADD_TEST(q15); +JTEST_ARM_ADD_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(add_tests) +{ + JTEST_TEST_CALL(arm_add_f32_test); + JTEST_TEST_CALL(arm_add_q31_test); + JTEST_TEST_CALL(arm_add_q15_test); + JTEST_TEST_CALL(arm_add_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.c new file mode 100644 index 0000000..86728f9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.c @@ -0,0 +1,101 @@ +#include "basic_math_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(BASIC_MATH_BIGGEST_INPUT_TYPE, + basic_math_output_fut, + BASIC_MATH_MAX_INPUT_ELEMENTS, + CURLY(0)); + +ARR_DESC_DEFINE(BASIC_MATH_BIGGEST_INPUT_TYPE, + basic_math_output_ref, + BASIC_MATH_MAX_INPUT_ELEMENTS, + CURLY(0)); + +BASIC_MATH_BIGGEST_INPUT_TYPE +basic_math_output_f32_ref[BASIC_MATH_MAX_INPUT_ELEMENTS]; + +BASIC_MATH_BIGGEST_INPUT_TYPE +basic_math_output_f32_fut[BASIC_MATH_MAX_INPUT_ELEMENTS]; + +/*--------------------------------------------------------------------------------*/ +/* Block Sizes */ +/*--------------------------------------------------------------------------------*/ + +/* + To change test parameter values add/remove values inside CURLY and update + the preceeding parameter to reflect the number of values inside CURLY. +*/ + +ARR_DESC_DEFINE(uint32_t, + basic_math_block_sizes, + 4, + CURLY( 2, 7, 15, 32)); + +/*--------------------------------------------------------------------------------*/ +/* Numbers */ +/*--------------------------------------------------------------------------------*/ + +/* + To change test parameter values add/remove values inside CURLY and update + the preceeding parameter to reflect the number of values inside CURLY. +*/ + +ARR_DESC_DEFINE(uint32_t, + basic_math_elts, + 4, + CURLY( 0, 1, 0x80000000, 0x7fffffff)); + +ARR_DESC_DEFINE(int8_t, + basic_math_elts2, + 5, + CURLY( 0, 3, -3, -7, 7)); + +ARR_DESC_DEFINE(float32_t, + basic_math_eltsf, + 6, + CURLY( 0.0f, 1.0f, 1.254001, -1.665584, -127.435646, 245.34634267)); + +/*--------------------------------------------------------------------------------*/ +/* Test Data */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(float32_t, + basic_math_f_32, + 32, + CURLY( + -0.432565, -1.665584, 0.125332, 0.287676, -1.146471, + 1.190915, 1.189164, -0.037633, 0.327292, 0.174639, + -0.186709, 0.725791, -0.588317, 2.183186, -0.136396, + 0.113931, 1.066768, 0.059281, -0.095648, -0.832349, + 0.294411, -1.336182, 0.714325, 1.623562, -0.691776, + 0.857997, 1.254001, -1.593730, -1.440964, 0.571148, + -0.399886, 0.689997 + )); + +/* Alias the 32 element array with wrappers that end sooner. */ +ARR_DESC_DEFINE_SUBSET(basic_math_f_15, + basic_math_f_32, + 15); + +ARR_DESC_DEFINE_SUBSET(basic_math_f_2, + basic_math_f_32, + 2); + +ARR_DESC_DEFINE(float32_t, + basic_math_zeros, + 32, + CURLY(0)); + +/* Aggregate all float datasets. */ +ARR_DESC_DEFINE(ARR_DESC_t *, + basic_math_f_all, + 4, + CURLY( + &basic_math_zeros, + &basic_math_f_2, + &basic_math_f_15, + &basic_math_f_32 + )); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c new file mode 100644 index 0000000..7b219fe --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c @@ -0,0 +1,17 @@ +#include "jtest.h" +#include "basic_math_tests.h" + +JTEST_DEFINE_GROUP(basic_math_tests) +{ + JTEST_GROUP_CALL(abs_tests); + JTEST_GROUP_CALL(add_tests); + JTEST_GROUP_CALL(dot_prod_tests); + JTEST_GROUP_CALL(mult_tests); + JTEST_GROUP_CALL(negate_tests); + JTEST_GROUP_CALL(offset_tests); + JTEST_GROUP_CALL(scale_tests); + JTEST_GROUP_CALL(shift_tests); + JTEST_GROUP_CALL(sub_tests); + + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c new file mode 100644 index 0000000..ed758a1 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_DOT_PROD_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + dot_prod, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + BASIC_MATH_SNR_ELT1_COMPARE_INTERFACE) + +JTEST_ARM_DOT_PROD_TEST(f32); +JTEST_ARM_DOT_PROD_TEST(q31); +JTEST_ARM_DOT_PROD_TEST(q15); +JTEST_ARM_DOT_PROD_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(dot_prod_tests) +{ + JTEST_TEST_CALL(arm_dot_prod_f32_test); + JTEST_TEST_CALL(arm_dot_prod_q31_test); + JTEST_TEST_CALL(arm_dot_prod_q15_test); + JTEST_TEST_CALL(arm_dot_prod_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c new file mode 100644 index 0000000..a94bf68 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MULT_TEST(suffix, compare_interface) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + mult, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + compare_interface) + +JTEST_ARM_MULT_TEST(f32, BASIC_MATH_COMPARE_INTERFACE); +JTEST_ARM_MULT_TEST(q31, BASIC_MATH_SNR_COMPARE_INTERFACE); +JTEST_ARM_MULT_TEST(q15, BASIC_MATH_COMPARE_INTERFACE); +JTEST_ARM_MULT_TEST(q7 , BASIC_MATH_COMPARE_INTERFACE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mult_tests) +{ + JTEST_TEST_CALL(arm_mult_f32_test); + JTEST_TEST_CALL(arm_mult_q31_test); + JTEST_TEST_CALL(arm_mult_q15_test); + JTEST_TEST_CALL(arm_mult_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.c new file mode 100644 index 0000000..276cdac --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.c @@ -0,0 +1,32 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_NEGATE_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + negate, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix)) + +JTEST_ARM_NEGATE_TEST(f32); +JTEST_ARM_NEGATE_TEST(q31); +JTEST_ARM_NEGATE_TEST(q15); +JTEST_ARM_NEGATE_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(negate_tests) +{ + JTEST_TEST_CALL(arm_negate_f32_test); + JTEST_TEST_CALL(arm_negate_q31_test); + JTEST_TEST_CALL(arm_negate_q15_test); + JTEST_TEST_CALL(arm_negate_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c new file mode 100644 index 0000000..4e10f78 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_OFFSET_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK( \ + offset, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix)) + +JTEST_ARM_OFFSET_TEST(f32); +JTEST_ARM_OFFSET_TEST(q31); +JTEST_ARM_OFFSET_TEST(q15); +JTEST_ARM_OFFSET_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(offset_tests) +{ + JTEST_TEST_CALL(arm_offset_f32_test); + JTEST_TEST_CALL(arm_offset_q31_test); + JTEST_TEST_CALL(arm_offset_q15_test); + JTEST_TEST_CALL(arm_offset_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c new file mode 100644 index 0000000..2839a8f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c @@ -0,0 +1,52 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + + +#define JTEST_ARM_SCALE_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT2_BLK( \ + scale, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), /*elt1_type*/ \ + int8_t, /*elt2_type*/ \ + TYPE_FROM_ABBREV(suffix)) + +/* float32_t defined separately because it has less arguments */ +JTEST_DEFINE_TEST(arm_scale_f32_test, + arm_scale_f32) +{ + TEST_TEMPLATE_BUF1_ELT1_BLK( + basic_math_f_all, + basic_math_eltsf, + basic_math_block_sizes, + float32_t, + float32_t, + float32_t, + arm_scale_f32, + ARM_scale_float_INPUT_INTERFACE, + ref_scale_f32, + REF_scale_float_INPUT_INTERFACE, + BASIC_MATH_COMPARE_INTERFACE); +} + +JTEST_ARM_SCALE_TEST(q31); +JTEST_ARM_SCALE_TEST(q15); +JTEST_ARM_SCALE_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(scale_tests) +{ + JTEST_TEST_CALL(arm_scale_f32_test); + JTEST_TEST_CALL(arm_scale_q31_test); + JTEST_TEST_CALL(arm_scale_q15_test); + JTEST_TEST_CALL(arm_scale_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c new file mode 100644 index 0000000..ed83b63 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_SHIFT_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK( \ + shift, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + int8_t, /*elt_type*/ \ + TYPE_FROM_ABBREV(suffix)) + +JTEST_ARM_SHIFT_TEST(q31); +JTEST_ARM_SHIFT_TEST(q15); +JTEST_ARM_SHIFT_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(shift_tests) +{ + JTEST_TEST_CALL(arm_shift_q31_test); + JTEST_TEST_CALL(arm_shift_q15_test); + JTEST_TEST_CALL(arm_shift_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c new file mode 100644 index 0000000..a486842 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "basic_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "basic_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_SUB_TEST(suffix) \ + BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + sub, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + BASIC_MATH_COMPARE_INTERFACE) + +JTEST_ARM_SUB_TEST(f32); +JTEST_ARM_SUB_TEST(q31); +JTEST_ARM_SUB_TEST(q15); +JTEST_ARM_SUB_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(sub_tests) +{ + JTEST_TEST_CALL(arm_sub_f32_test); + JTEST_TEST_CALL(arm_sub_q31_test); + JTEST_TEST_CALL(arm_sub_q15_test); + JTEST_TEST_CALL(arm_sub_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.c new file mode 100644 index 0000000..7fcc0bc --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_CONJ_TEST(suffix) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + cmplx_conj, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE) + +JTEST_ARM_CMPLX_CONJ_TEST(f32); +JTEST_ARM_CMPLX_CONJ_TEST(q31); +JTEST_ARM_CMPLX_CONJ_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_conj_tests) +{ + JTEST_TEST_CALL(arm_cmplx_conj_f32_test); + JTEST_TEST_CALL(arm_cmplx_conj_q31_test); + JTEST_TEST_CALL(arm_cmplx_conj_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c new file mode 100644 index 0000000..bcdaf5b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_DOT_PROD_TEST(suffix, comparison_interface) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + cmplx_dot_prod, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + comparison_interface) + +JTEST_ARM_CMPLX_DOT_PROD_TEST(f32, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE); +JTEST_ARM_CMPLX_DOT_PROD_TEST(q31, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE); +JTEST_ARM_CMPLX_DOT_PROD_TEST(q15, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_dot_prod_tests) +{ + JTEST_TEST_CALL(arm_cmplx_dot_prod_f32_test); + JTEST_TEST_CALL(arm_cmplx_dot_prod_q31_test); + JTEST_TEST_CALL(arm_cmplx_dot_prod_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c new file mode 100644 index 0000000..9ca11fc --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_MAG_SQUARED_TEST(suffix) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + cmplx_mag_squared, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + COMPLEX_MATH_COMPARE_RE_INTERFACE) + +JTEST_ARM_CMPLX_MAG_SQUARED_TEST(f32); +JTEST_ARM_CMPLX_MAG_SQUARED_TEST(q31); +JTEST_ARM_CMPLX_MAG_SQUARED_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_mag_squared_tests) +{ + JTEST_TEST_CALL(arm_cmplx_mag_squared_f32_test); + JTEST_TEST_CALL(arm_cmplx_mag_squared_q31_test); + JTEST_TEST_CALL(arm_cmplx_mag_squared_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c new file mode 100644 index 0000000..8711957 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_MAG_TEST(suffix, comparison_interface) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + cmplx_mag, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + comparison_interface) + +JTEST_ARM_CMPLX_MAG_TEST(f32, COMPLEX_MATH_COMPARE_RE_INTERFACE); +JTEST_ARM_CMPLX_MAG_TEST(q31, COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE); +JTEST_ARM_CMPLX_MAG_TEST(q15, COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_mag_tests) +{ + JTEST_TEST_CALL(arm_cmplx_mag_f32_test); + JTEST_TEST_CALL(arm_cmplx_mag_q31_test); + JTEST_TEST_CALL(arm_cmplx_mag_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c new file mode 100644 index 0000000..22c5a70 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_MULT_CMPLX_TEST(suffix) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + cmplx_mult_cmplx, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + COMPLEX_MATH_COMPARE_CMPLX_INTERFACE) + +JTEST_ARM_CMPLX_MULT_CMPLX_TEST(f32); +JTEST_ARM_CMPLX_MULT_CMPLX_TEST(q31); +JTEST_ARM_CMPLX_MULT_CMPLX_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_mult_cmplx_tests) +{ + JTEST_TEST_CALL(arm_cmplx_mult_cmplx_f32_test); + JTEST_TEST_CALL(arm_cmplx_mult_cmplx_q31_test); + JTEST_TEST_CALL(arm_cmplx_mult_cmplx_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c new file mode 100644 index 0000000..fce7b82 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "complex_math_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "complex_math_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_CMPLX_MULT_REAL_TEST(suffix, comparison_interface) \ + COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \ + cmplx_mult_real, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + comparison_interface) + +JTEST_ARM_CMPLX_MULT_REAL_TEST(f32, COMPLEX_MATH_COMPARE_CMPLX_INTERFACE); +JTEST_ARM_CMPLX_MULT_REAL_TEST(q31, COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE); +JTEST_ARM_CMPLX_MULT_REAL_TEST(q15, COMPLEX_MATH_COMPARE_CMPLX_INTERFACE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cmplx_mult_real_tests) +{ + JTEST_TEST_CALL(arm_cmplx_mult_real_f32_test); + JTEST_TEST_CALL(arm_cmplx_mult_real_q31_test); + JTEST_TEST_CALL(arm_cmplx_mult_real_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c new file mode 100644 index 0000000..396dc2f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c @@ -0,0 +1,114 @@ +#include "complex_math_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE, + complex_math_output_fut_a, + COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/, + CURLY(0)); + +ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE, + complex_math_output_fut_b, + COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/, + CURLY(0)); + +ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE, + complex_math_output_ref_a, + COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/, + CURLY(0)); + + +ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE, + complex_math_output_ref_b, + COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/, + CURLY(0)); + + +COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_ref_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_ref_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_fut_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +COMPLEX_MATH_BIGGEST_INPUT_TYPE +complex_math_output_f32_fut_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2]; + +/*--------------------------------------------------------------------------------*/ +/* Block Sizes */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(uint32_t, + complex_math_block_sizes, + 4, + CURLY(1, 2, 15, 32)); + +/*--------------------------------------------------------------------------------*/ +/* Test Data */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(float32_t, + complex_math_f_32, + 32 * 2 /*Complex data has two parts*/, + CURLY( + -0.432564811528220680 , 0.815622288876143300, + -1.665584378238097000 , 0.711908323500893280, + 0.125332306474830680 , 1.290249754932477000, + 0.287676420358548850 , 0.668600505682040320, + -1.146471350681463700 , 1.190838074243369100, + 1.190915465642998800 , -1.202457114773944000, + 1.189164201652103100 , -0.019789557768770449, + -0.037633276593317645 , -0.156717298831980680, + 0.327292361408654140 , -1.604085562001158500, + 0.174639142820924520 , 0.257304234677489860, + -0.186708577681439360 , -1.056472928081482400, + 0.725790548293302700 , 1.415141485872338600, + -0.588316543014188680 , -0.805090404196879830, + 2.183185818197101100 , 0.528743010962224870, + -0.136395883086595700 , 0.219320672667622370, + 0.113931313520809620 , -0.921901624355539130, + 1.066768211359188800 , -2.170674494305262500, + 0.059281460523605348 , -0.059187824521191180, + -0.095648405483669041 , -1.010633706474247400, + -0.832349463650022490 , 0.614463048895480980, + 0.294410816392640380 , 0.507740785341985520, + -1.336181857937804000 , 1.692429870190521400, + 0.714324551818952160 , 0.591282586924175900, + 1.623562064446270700 , -0.643595202682526120, + -0.691775701702286750 , 0.380337251713910140, + 0.857996672828262640 , -1.009115524340785000, + 1.254001421602532400 , -0.019510669530289293, + -1.593729576447476800 , -0.048220789145312269, + -1.440964431901020000 , 0.000043191841625545, + 0.571147623658177950 , -0.317859451247687890, + -0.399885577715363150 , 1.095003738787492500, + 0.689997375464345140 , -1.873990257640960800 + )); + +ARR_DESC_DEFINE_SUBSET(complex_math_f_15, + complex_math_f_32, + 15 * 2 /*Complex data has two parts*/); + +ARR_DESC_DEFINE_SUBSET(complex_math_f_2, + complex_math_f_32, + 2 * 2 /*Complex data has two parts*/); + +ARR_DESC_DEFINE(float32_t, + complex_math_zeros, + 32 * 2 /*Complex data has two parts*/, + CURLY(0)); + +/* Aggregate all float datasets */ +ARR_DESC_DEFINE(ARR_DESC_t *, + complex_math_f_all, + 4, + CURLY( + &complex_math_zeros, + &complex_math_f_2, + &complex_math_f_15, + &complex_math_f_32 + )); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.c new file mode 100644 index 0000000..38546fb --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.c @@ -0,0 +1,14 @@ +#include "jtest.h" +#include "complex_math_tests.h" + +JTEST_DEFINE_GROUP(complex_math_tests) +{ + JTEST_GROUP_CALL(cmplx_conj_tests); + JTEST_GROUP_CALL(cmplx_dot_prod_tests); + JTEST_GROUP_CALL(cmplx_mag_tests); + JTEST_GROUP_CALL(cmplx_mag_squared_tests); + JTEST_GROUP_CALL(cmplx_mult_cmplx_tests); + JTEST_GROUP_CALL(cmplx_mult_real_tests); + + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c new file mode 100644 index 0000000..661a487 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c @@ -0,0 +1,499 @@ +#include "controller_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +float32_t controller_output_fut[CONTROLLER_MAX_LEN] = {0}; +float32_t controller_output_ref[CONTROLLER_MAX_LEN] = {0}; +float32_t controller_output_f32_fut[CONTROLLER_MAX_LEN] = {0}; +float32_t controller_output_f32_ref[CONTROLLER_MAX_LEN] = {0}; + +const q31_t controller_q31_inputs[CONTROLLER_MAX_LEN] = +{ + 0xC14A5524, 0xCCABDA17, 0xAD6F5B56, 0xFDAFCE3B, 0xA9B226EB, 0x41F6F6A, + 0xA5CE38BF, 0x3A978AFA, 0xBA44B82A, 0x855C0F8, 0x3D060524, 0x93D5E570, + 0x97D7791D, 0xFFE0C38C, 0x26749841, 0xC0A6EE54, 0x218EC386, 0x39FF3726, + 0x8DC1F7CA, 0x702F2CF5, 0xC1142FF1, 0xEC1476AB, 0x15F640DD, 0xE62CCE49, + 0x3805DE7E, 0xF70871FE, 0xCF8BD360, 0x8D19A8A0, 0xD764F821, 0xA58558CF, + 0x8C0CE04D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0xB646AE24, 0x6CE00F5C, + 0xE6D48948, 0xB55BD831, 0x3B72950A, 0x9EB69530, 0x73394127, 0x773FA6F4, + 0x9805A980, 0x838DE587, 0x9CF597F4, 0xA2AD1691, 0xFA81A473, 0x7CDC7D7F, + 0x4A5190D0, 0xED895BB9, 0x8FD60F35, 0x1A21D530, 0xA0EB6DDA, 0xBDE6A516, + 0x2501A3E1, 0x5ED893C8, 0xE1E175B1, 0xACBBB2F3, 0xED350907, 0xDB140D7E, + 0xEEAE272D, 0xBE229841, 0xC18BFB88, 0xA6BB9B80, 0xBCF090E4, 0x24DB166C, + 0xF9AB7E42, 0x62DF28D1, 0xC7004665, 0xE3F56FC6, 0x419E0C75, 0x46BE9F38, + 0x2432B9B2, 0x758D83E0, 0xDCE12926, 0x3F57CB74, 0x1F4458E2, 0xF1DD639, + 0x83A1FB49, 0x173AFC76, 0x86EF7531, 0x48D32F34, 0x7D3E3063, 0x8F2FB549, + 0x5C314C9, 0x18CBEB6D, 0xA6F8B697, 0x447B9E9C, 0x2E32BA33, 0xD074D715, + 0x81ACD746, 0xE55A4E04, 0x4891860F, 0x1DA3EB4F, 0xE0E6A27F, 0x20BFDEB4, + 0xD0B3A25B, 0x40C10544, 0xC15656C, 0x15405EAE, 0x9858E3E1, 0xA36A9C4E, + 0x88BD21F9, 0xAACF7A68, 0x773665E5, 0xCEDFDF66, 0x617A9610, 0x524FC968, + 0xC2D086CD, 0x5F008079, 0x24DCA447, 0x6A4F5599, 0xB706CD4A, 0x1DE70608, + 0xA33A2EE5, 0x137E488E, 0x98061B7B, 0x4079D69D, 0xA4A897D5, 0xC4CEC8F5, + 0xD75F7883, 0x22406802, 0xF1AD70BB, 0x9D4ADD79, 0xBCBC7CE4, 0xB358C0D8, + 0x85792E47, 0xA7ADAC05, 0x3D19EEAB, 0x331AC0AF, 0x33035831, 0x13D93987, + 0xFC542094, 0x845F317E, 0xDDC4BF8B, 0x1379E50C, 0x5C20193F, 0xFDD58298, + 0x9D482B82, 0x4A6BE062, 0xDC8A757B, 0x272917C1, 0x90E1EFBC, 0x355AD882, + 0xE6F8EA35, 0x604555A1, 0x7DFFFBB, 0xF58AE216, 0x9A11B463, 0xD3541BAD, + 0xA1576756, 0x483BED8D, 0x1F05AFCC, 0xCEA63DFB, 0x55B84677, 0xFB2E04F2, + 0x787AF96C, 0x84A12CD3, 0x460A9BD, 0x9DB22DD8, 0x1A8C7F28, 0x861E452E, + 0x932D3F78, 0x7652D852, 0x73357BBA, 0xEBBB0A58, 0x62536AFA, 0x3F6B65EF, + 0x6DC57B58, 0x9EB798CE, 0xE6B0A740, 0xDFF68B47, 0x3247FB8F, 0xFFF3D302, + 0xA9FD3E40, 0x475A43D1, 0x6FF9528A, 0x2018A09D, 0x47E0F9C9, 0x4CF5F6D3, + 0x2807CE34, 0xDD6FD8ED, 0x234045D1, 0x51CEB5F9, 0x25297896, 0x6443A0FE, + 0x8F4449A9, 0xD4C3E1C6, 0xF01D52F1, 0x4E09C820, 0xF18F0810, 0xE1548689, + 0xF9DE5A1F, 0x5286DC23, 0x48AC3A4B, 0xEA0C1BE0, 0xA1B785DB, 0x7086465D, + 0x1CC10929, 0x1E1D716E, 0xED231D4C, 0x2049D108, 0xB8FF9971, 0x949CF8D4, + 0x441F1E8B, 0xC3D95372, 0x69C324B4, 0xA10BFDC9, 0xC781DE78, 0x82476137, + 0xE163DDF, 0x390DEEC2, 0xAF68CE5B, 0x8E680ABD, 0x8223A615, 0x92593380, + 0x7B1465FE, 0x865AE957, 0x930F53EB, 0xED772EF7, 0x10E916B6, 0xE3BCFA68, + 0x2ACB80BB, 0xE51C5590, 0x994714B5, 0xF30984EE, 0x59BBE1B4, 0xB4867DBC, + 0xB91C706C, 0xBC16C218, 0xA8931CD0, 0x129A66AB, 0x13171F4D, 0x62882872, + 0x4B167FD4, 0xE6902F4C, 0xFA794932, 0xD4B152C, 0xB0856EA9, 0x39466D55, + 0x3669E451, 0x8F5B9E8C, 0x877A3C6A, 0x51B956B4, 0x367EAD2A, 0x9D2C662A, + 0x78FB6880, 0x4E6D40B6, 0x4070EFDC, 0x4DF9679C, 0x20306EDB, 0xE381AAE7, + 0xA55DA748, 0x9B8B617B, 0x3E036FAD, 0x84E4C4A7, 0xD5A3F517, 0x669BA988, + 0x98FDDE8C, 0x67BD85CE, 0x34BBB46C, 0x76994800, 0x85B9D8B6, 0x6DFA2FEF, + 0x205DB5C, 0x9F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB98B61, 0xC323DDAC, + 0x31D424B4, 0xF68C0D7E, 0x162FAF9D, 0x7B2A7A99, 0xF9392693, 0xC42D12C0, + 0x8692A73E, 0xD9A1EE80, 0xDD956856, 0x44E7BDAC, 0x8D874532, 0x5F5C9DD0, + 0x5D167858, 0x8559FEA2, 0x9D821476, 0xD9654ED2, 0x594C0DC7, 0x1A87B506, + 0x3F693200, 0x7A651AB5, 0xA0CCBC8A, 0x9F9E662C, 0x78EF631, 0x2A09DA0, + 0xB088C72F, 0x92EE0D42, 0x360DCD5F, 0xF333FE48, 0x8D63CC06, 0x233A8ACB, + 0x706651ED, 0x7AA5C079, 0x262239D1, 0x3EBBEBB6, 0xA25A4F3D, 0x32581A06, + 0x6E6FD780, 0x5773F7C7, 0x75ED1DDC, 0x90DF2D15, 0xBC79A9BC, 0xB7175917, + 0x354E381C, 0x762AADD7, 0xF643DAC1, 0xF3BBF49E, 0xD2FECE7E, 0x6C8140F4, + 0xD7694875, 0x92D30822, 0xC742A7CF, 0xB792ED98, 0x121CFE24, 0xA04E1EE7, + 0x58CE268, 0x215A080, 0x316CB323, 0xFAB14A31, 0xE1C13C03, 0xFD8EF4F1, + 0xF3F446D0, 0x6C6CEA0A, 0xBBFDF9FB, 0x67242969, 0xBE55A4EB, 0x8FF5534, + 0x52F0DF1C, 0x9710ADE3, 0xD40F4A21, 0x7984E8E7, 0x419545EB, 0x993F7880, + 0xAB246B20, 0x408AABC4, 0xCBF6EA49, 0xC0894C55, 0x4CAA6398, 0xA47856E9, + 0xAF2AE47D, 0x22F55D33, 0xF0D37915, 0xD0634C72, 0xD983671, 0x2BCC5AF8, + 0x9A77D48, 0xC11B5CFA, 0xF107CD7E, 0x3A6B3593, 0xE1425F05, 0x6271812A, + 0x5B838310, 0xBD8418CA, 0x10A58792, 0x239F7137, 0xA13D5071, 0x7F9930D4, + 0xA462664F, 0x54180F8E, 0x291585BA, 0xE586B87A, 0x144B2C12, 0x98E425C7, + 0xBAA4B373, 0x18F0D03C, 0x99462AC0, 0xD8B4D2EF, 0x72473895, 0xA6BF5435, + 0xEDAD53B, 0xE0912FA6, 0x5C33F331, 0x3D93CD7, 0x4D03D752, 0x20699929, + 0xB89962F9, 0x36E781E9, 0xF58B642C, 0x5FCA69E3, 0x5960A7F4, 0xAD5AAFD0, + 0xDF18324A, 0x3DB1E5AA, 0x76BA3876, 0x1BC29AF6, 0xBCC18841, 0x73A60174, + 0x625BFF58, 0x67C57724, 0x4458E53C, 0xE157B095, 0x2B370837, 0x83DF6CE3, + 0xDD08EEFA, 0x3F52A7C2, 0x191B4785, 0x60843D82, 0xB0DE11F1, 0x105EA26C, + 0x6E1C7AA2, 0x47AADD14, 0xB6676D03, 0x3B8D4DF6, 0x737A694, 0x409521DC, + 0x744206A, 0xC722023F, 0x2BE4EAD5, 0x63E11D76, 0xCA4A09AB, 0x5CF2D2B9, + 0x31586916, 0xCDFD7D84, 0xB203F634, 0xAD7329D4, 0xC524582F, 0x2E53E6C1, + 0xBB0E019B, 0xB8538C6A, 0x6A2542D, 0x8A6A00E5, 0x119725CC, 0x5406D347, + 0x1B6FFAF1, 0xECCF71F1, 0x981117F2, 0x7167CA76, 0x74F4B880, 0x77A55F47, + 0x59EADB62, 0x4A331D95, 0xBCBBA76F, 0xA45C4D50, 0xC718D5, 0x87CE05D1, + 0x60D47AD5, 0xA5CA9C40, 0xB0061766, 0xE69B39DF, 0xBD5F1320, 0x9930EAD3, + 0xA8B38325, 0x8DD090F, 0x6A6EEF37, 0x2DF16F66, 0xAB514C7E, 0x31109C58, + 0xFD48C7FC, 0x515341CA, 0x77AB8EA6, 0x41328DAF, 0xBAF8D31E, 0xA4B31611, + 0xED37F331, 0x7A832A22, 0xA22591C7, 0x722D1F89, 0x3B19CF18, 0x261B8A4D, + 0xC3F6F6DB, 0xCF8CED61, 0x990FA250, 0xA02E72A9, 0x560DCEA2, 0xB08E67B4, + 0x3674E663, 0x97CC3852, 0xA7EB2EAC, 0xFFDE0AA8, 0xA64719A, 0x23269EDD, + 0x3C0B339E, 0x86284D40, 0x48D82ECB, 0xA4D4CCF8, 0x43631B91, 0x4BF0C248, + 0xB6497B9B, 0x6827BC58, 0xE30B7AF9, 0xA0CCBF26, 0x6C3B7B71, 0xD744B3ED, + 0xFA25D2F6, 0x4CDE642D, 0xD65B8142, 0xA6F9207F, 0xE7A207BE, 0xDB506684, + 0x44DA4780, 0x9175EA0C, 0x156104AF, 0x4155E1B0, 0x6E3A6886, 0x9DBA1EA2, + 0x5423D9C8, 0xCC024E22, 0x758F852A, 0x1DD6395, 0x2D19CBAD, 0xE164F5A1, + 0xC2084602, 0x89C274AD, 0x13CB5562, 0xD7FE2D5B, 0xE07A4EE5, 0x1672BA91, + 0x4F624CCF, 0x2E5EA4A3, 0x28FEEFAF, 0xBDDA6EF4, 0x32AFD40C, 0x99A5FB3B, + 0xDD1D73A3, 0xA342CB3E, 0xA78445F5, 0x53979C3B, 0x427D7943, 0x5221B58C, + 0xA6CE9A5E, 0xFB50ECA4, 0xBB86E36E, 0x60839F6D, 0xC5E1C2F3, 0xA1B7FB04, + 0xFBB65E0C, 0x78B80F5E, 0xFD8D972B, 0x3BF3BA90, 0x2D572D9, 0x2B5BC920, + 0xB6A0DE01, 0xD274D306, 0xC7C6C855, 0x9CAA669B, 0xB04AA641, 0x4D6B1760, + 0x3E17ED79, 0xD23241B0, 0xA4A6F957, 0xCBDE76AF, 0x4E5F9493, 0x4C215DA5, + 0x33A052B, 0x1A4D80C2, 0x40AEEBCA, 0x390D106B, 0xE9E8E018, 0x5AF3D6CF, + 0xE35E1D4, 0xC4FB1C6, 0x14B6299B, 0x8D2E25F0, 0xCCBF932A, 0xC5AC18B6, + 0x2227567D, 0x86B5CE2F, 0x26344534, 0x22C515EC, 0x2442B70D, 0xEC3721C6, + 0x34EF687D, 0x9C06323A, 0xEAF3EA60, 0x60396F52, 0xEAE78AA1, 0xC9D06CBC, + 0x6F95F6C8, 0x584CC258, 0xBA9A27BB, 0x66DF8D47, 0x9D4804EA, 0x57DD9E67, + 0xF89C7895, 0xF5336111, 0x25C122C8, 0x62742114, 0xCFBF6D26, 0xBF9F6482, + 0xE6F02CD9, 0x11083202, 0xC99E2618, 0x7EBC9351, 0x440112F1, 0xC9DFFBC1, + 0x3BF4DC25, 0xB1BA7FA0, 0x61AF9AED, 0x6B1F7D29, 0xAD865294, 0xE3E01129, + 0x7E9E77A5, 0x100435D7, 0x9FE3A71, 0x88597C81, 0x722849FA, 0x31C5A0AF, + 0xFBA178DC, 0x7F102D31, 0x5CA07864, 0x950E6F98, 0x82C34882, 0x5D041F11, + 0x8C613C57, 0xD398CFD1, 0x426F38AD, 0x5599AB1D, 0xFAFA078D, 0xAB25B413, + 0xD94B32CF, 0xB288FE38, 0x2893BB46, 0x9A0B4168, 0xA91BCA94, 0x653A5E8D, + 0x2174EBBE, 0xDEFE6415, 0x30DA429C, 0xD0C5E40C, 0xB4719AA4, 0xD29CE7A6, + 0x905957CD, 0xCD287499, 0x83CA0AA7, 0xA8385832, 0x25A0CA02, 0xC20D47A4, + 0xB562F556, 0x4BC19E4C, 0xD9E215C7, 0x27E838B4, 0xC58612F4, 0xA2827F6F, + 0xC49DCDBA, 0x679B7362, 0x4E495845, 0xCFD2F0D1, 0x395E76A0, 0x375A655E, + 0x92E2058F, 0x73F9F0CA, 0x61EFF3B3, 0x51FFD362, 0xE7410345, 0x7FDA8B3B, + 0xA219E2E8, 0x17ABE543, 0x26557412, 0x4B30084D, 0xA68E191D, 0xFE0D93DF, + 0x73EF127D, 0x4DECDDB1, 0x77FAF45F, 0xD6002898, 0x92DD0A40, 0x157F6DDF, + 0xC2A55F8E, 0x4359F924, 0xFB630C3F, 0x338B6B58, 0xB2945F75, 0x4FA23A0E, + 0x836EB8C0, 0xB3B18FD, 0x86114337, 0x24668ACB, 0x99BB82F0, 0x924C8A47, + 0xBA959701, 0x81155ABF, 0x8C612D71, 0x36074CA7, 0xD1668C41, 0xE35F58C7, + 0x7FC2802D, 0x8E6A7CF3, 0x65B07D07, 0x815F6A6B, 0x791BF0DD, 0x6E47D719, + 0xC24394C7, 0xE84A6EB, 0xF194AFEE, 0x464A2F52, 0x677579FD, 0xEBA775AE, + 0x1F6EEFF, 0x9A795237, 0x78D9D45F, 0x9D0B344D, 0xBBD34AB7, 0x2F85B12A, + 0x16C5C2AD, 0x3990985D, 0x88DF3351, 0x82811AA5, 0x6D351F41, 0x4066A69D, + 0x86B660BF, 0x6EDB4768, 0xDDD78CF0, 0xB5D74F6E, 0xE89E220C, 0x91439687, + 0x947CC9C9, 0x3857E2BD, 0x302F8AE4, 0x1DABE7F8, 0x4832D6C9, 0x37D58FCB, + 0x4EA8A711, 0xCD7BAC98, 0x19DBF8BC, 0xD8DE8DC2, 0xEAFF7E7B, 0xB7629C93, + 0x792C6E19, 0xF7009192, 0xFF88439D, 0x2E196A66, 0xEC71B78C, 0xEAF4BB3A, + 0x7C16225E, 0x668F337, 0xCBEE1608, 0x6D5B5552, 0x345DC590, 0x681209CC, + 0x7B24A819, 0xD08A1416, 0x99888FE3, 0x9FC7288A, 0x24BD8502, 0xEA1D9678, + 0x20EECA0, 0x59BEA057, 0x5ADE91EB, 0xDEA8E49D, 0xFA200E6F, 0x9149C81D, + 0xF2281E93, 0x8A5B0451, 0x67312D58, 0xE3B849F1, 0xD2217960, 0x7CDF59F3, + 0x33C775C0, 0x9EBA8799, 0x7DF9506, 0xB4E96110, 0xB8FCF3E3, 0xDEA059B2, + 0x8229B6EA, 0x316486F6, 0x43919185, 0x6C0D90F3, 0x1C6F3DF8, 0x38DB92A9, + 0x5CD41244, 0x2C9F0A7B, 0xDF4A315F, 0xF7CE9C66, 0x4C800860, 0x318D53E0, + 0xF105C20D, 0xD753E1F2, 0x750810BA, 0xA17ECCA5, 0x2010140, 0x4D884763, + 0xC2BB0DA7, 0xB2D5BA74, 0x141CECD4, 0x887FDFC3, 0xC64B53, 0x2D2A85F6, + 0x15532B45, 0x5D5CBCE1, 0xBEB9A16A, 0xA214611B, 0x9FC5AC5F, 0x11AE5DD7, + 0xA0B9A5A9, 0xFC648AF4, 0x740009AC, 0xED0E0321, 0xB8E6A61, 0x8910C544, + 0xC74F26C8, 0x9525CCF3, 0xB41AEB59, 0xE61984CE, 0x598B2197, 0xA412E59D, + 0xE1976DD4, 0xB29BBE16, 0x88FD9FB0, 0xB04006F3, 0xB45E309, 0xD5CC15F1, + 0xD9DAF630, 0xDC809335, 0x803ED52, 0xB537F5A5, 0xA994F6EB, 0xF5288568, + 0xF66FD264, 0x2EA2B3A6, 0x647619F3, 0xFFB38C7A, 0x1BC03B9, 0xB6BC3061, + 0xBF30596E, 0xBE2AD27B, 0x8AC04220, 0x641979A3, 0x9ECCBB89, 0xA144FBC1, + 0x4E8FAE26, 0x8C5A9D90, 0x299ED467, 0xD7C9C7E3, 0x1D4865ED, 0x76F31C3D, + 0xCEE81CDF, 0xB479195E, 0x6FFB3AE1, 0xDC8A398, 0x300F7364, 0xC7940AFA, + 0x3B85BE3E, 0xD98CC40D, 0xA24A3D89, 0x3A674204, 0x22888A38, 0x2E77F2D, + 0xA2841C9C, 0xCF0689C3, 0x9FE98922, 0x89335017, 0x2D6B69A7, 0xFEDB63F9, + 0x899AF4EF, 0x9F9F9B40, 0xA4BE97E8, 0xA51DAF7A, 0x16AC50D3, 0xA8D7ED6, + 0xED193443, 0x7615EF1B, 0xB0DF6A4E, 0x64FFE794, 0xE3DB2C9A, 0x7435B022, + 0x556E825C, 0x23802AF9, 0xC25098A4, 0xE75A18BB, 0x70B2A7B9, 0x7FB81BF, + 0x63EF910, 0x6C669591, 0x6574DD2B, 0xCF6E379D, 0xD2B3AFAC, 0x1E6A1101, + 0x1DE22385, 0x2338191F, 0xC69704B6, 0xCBABC599, 0x54EB4809, 0x7839BE6D, + 0xD50017DD, 0x39B1A0E1, 0x288D52D3, 0x2D52668C, 0x20D22A68, 0x4E1207D1, + 0x3FCC0EFE, 0x47F3FE64, 0x25177A90, 0xB4BFDD4D, 0xDA8DBDCE, 0x6F7275A8, + 0x6BEAA655, 0xAA1810FC, 0xE4DB593A, 0x8A4D4BC0, 0x2C402E93, 0xF1C0F7F9, + 0x6F0CC577, 0x70412414, 0x752F9DC1, 0xD82E38EA, 0xAC455F7B, 0x4DCD4EDB, + 0x92BC2696, 0xFB03F135, 0x4FCA1F8C, 0xBD5E75F6, 0x502F41B0, 0x3616D3F1, + 0x2E5B8E31, 0x2026EB19, 0x57E783D7, 0x467BBE00, 0x4703ABA3, 0x1F776B9C, + 0xE2570A84, 0xFEC7DB48, 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, + 0x99D5D8ED, 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F, + 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB, 0x56186AA1, + 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94, 0xAC18B207, 0x5FC78B3, + 0x7F10621E, 0xA769E6B2, 0xEC9F4A11, 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, + 0x73D63FED, 0xE36E9F5E, 0x8AC1DA0E, 0x3F3DB3EB, 0x738326EA, 0x35C366B1, + 0xCD476E86, 0x82F6B208, 0xF11A9FC1, 0x426AC396, 0x7E4D1B93, 0x75E4EDB7, + 0xAF3C44A7, 0x51A5EF5C, 0xFAD2463D, 0x8A5639CA, 0xC995AC78, 0xCC4BE4F6, + 0x3AFE7F8D, 0x66993D04, 0x4386FF37, 0xCBC1C6C2, 0x55A8F5EC, 0xE81A9A75, + 0x30A67E1B, 0x4A4A7D0C, 0x20F7F993, 0x1891805, 0x738976AD, 0xD426E7D6, + 0x3C5CEEBF, 0x4499187F, 0xABF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456, + 0x421BCF29, 0xF6740F9C, 0x8916BB8D, 0x3D72AAB, 0x9AD54DD7, 0x7549C6EE, + 0x7317342B, 0xA18546D4, 0x1056BDA7, 0x54BBCCCE, 0x8CE63E46, 0x5D146234, + 0x33BE6C63, 0xB250C4E5, 0x89D72335, 0x87C36BA, 0xB65530CC, 0x2DFAC48C, + 0x1663D16F, 0x59B80AA, 0x950274EA, 0x92532D4A, 0x3CEF802D, 0x492FBDA5, + 0xA63A2574, 0xEF8005C2, 0x94A18651, 0xAF627ABA, 0x6829B238, 0xA698F646, + 0xD2598516, 0x10144D36, 0xD9B1D1B9, 0xAB2ACF05, 0x5395B699, 0xA7851C75, + 0x1806C6F3, 0xAE970306, 0x3284B145, 0x98F4FE8F +}; + +/* The source data is random across the q31_t range. Accessing it by word should + remain random. */ +const q15_t * controller_q15_inputs = (q15_t *) controller_q31_inputs; + +const float32_t controller_f32_inputs[CONTROLLER_MAX_LEN] = +{ + 43.0264275639 , -17.0525215570 , -94.8488973910 , -8.1924989580 , + 7.2830326091 , 66.8368719314 , 33.9778190671 , 117.8652289772 , + -129.6077797465, -14.6420815368 , 18.0239223278 , 20.6760530292 , + 55.0375037651 , 1.8674609862 , -85.6534302408 , -33.5750364909 , + 29.2110949614 , 110.4727049460 , -94.1914619387 , -1.4084169343 , + 83.5181653041 , 47.3073514127 , -13.3420621181 , 30.3389699104 , + 12.1188124277 , 100.9730921941 , -114.0146362390, -77.5823200409 , + 37.2019034618 , 40.0026301128 , -58.3387276630 , -34.9472398600 , + -5.1169678311 , -87.7660091118 , -150.5888601131, 56.0349370503 , + 50.2168884079 , -74.2313236767 , 22.3648603560 , -6.8676387051 , + 74.8957303680 , -90.1292012823 , -55.1436241586 , -66.6732976100 , + -6.7918147615 , 7.7612697081 , 35.7892605979 , -20.0470508830 , + 41.8369017546 , -143.7378056984, -41.9127158600 , -108.3531841158, + -57.1917422289 , -124.2808828105, 38.9316388820 , -77.9212517405 , + 37.1990818377 , -28.9545952748 , -155.6371057564, 45.8088886393 , + 36.2537018275 , -6.5727656016 , -104.2070491921, 45.5583813729 , + -19.7674717059 , -80.4802190947 , -1.4444563441 , -42.2142256438 , + 36.6546339194 , -57.0866498590 , 44.4677067511 , 65.7285753407 , + -103.8158864647, 25.4348723711 , -153.5419639389, 39.3608409474 , + 49.1658103436 , 79.5570602275 , 75.2944095996 , 58.9394700746 , + -53.1018534392 , 33.4172444014 , 35.6224682287 , -64.4353396418 , + -125.8464291251, -47.6072111617 , -26.2177687594 , -12.0061322096 , + -17.7887967585 , -28.2926175090 , -62.0691715749 , 40.5098573604 , + -191.1123732593, 119.6750713043 , 19.6182375803 , -26.7615252921 , + 2.2957847015 , -108.3436451287, -50.5906164995 , -5.6360985100 , + -11.6772204201 , -84.2765293757 , -60.9317810068 , 82.0446350218 , + -70.2048296348 , 72.8738253222 , 60.2450218115 , 114.2741231228 , + 46.8180775285 , 6.9915412654 , -8.9909197429 , -78.9165936808 , + 66.4731535459 , -68.4235455651 , -79.8254597080 , -10.6308477115 , + -62.6161569330 , -55.7744410292 , -11.8408366528 , 98.1034940997 , + 35.8213741877 , -54.4694482732 , 86.9631830044 , -53.0343838122 , + -47.4898642865 , -47.2010929590 , -31.3312639685 , -23.0908245172 , + 12.0258009869 , -5.1098204703 , -9.8420230737 , -107.3328761158, + 44.6810431959 , -17.9083820345 , -60.9753512872 , -7.5915088994 , + 17.2250813329 , 57.9176125648 , 124.3004161362 , -63.1950908493 , + 120.5788885640 , -44.1734238117 , -91.7408095116 , -43.5696066595 , + -49.9560710099 , -167.8513443296, -70.9437505499 , -46.4109705355 , + -64.2264526456 , -13.9995803916 , -100.9548186356, 9.9101010575 , + -50.0615130815 , -55.7590145012 , -60.3195153388 , 61.7913378549 , + -102.0850899209, 53.2360193126 , -25.8997883369 , 75.1445512333 , + -113.8148602310, 17.8027281119 , -19.5006822722 , -44.2169628471 , + 107.5017084384 , -113.7909124666, -43.9735396033 , 7.6880981388 , + 46.7384653508 , 9.9047443751 , 81.8646964362 , 132.3812863877 , + -95.6959050236 , -68.5015813484 , 65.8586404494 , 18.5039353889 , + -30.1786166621 , -90.3098515667 , -22.9356228552 , -20.5778272423 , + -2.2127786675 , -35.4418447703 , -51.8722915974 , -107.9024439078, + -51.5940748232 , -51.7463262677 , 74.2795485984 , 94.2205022462 , + 9.7016384049 , -47.3556083155 , -36.7822314478 , -151.6455525363, + -15.7183814485 , 78.2063383182 , 0.1516414969 , 37.9304181609 , + 20.6185902740 , -22.2164106778 , 6.1160554677 , 2.4061326953 , + -111.6681824598, -60.0858917090 , 75.1698614693 , -76.5787410444 , + 28.3391655715 , -2.4946186443 , -68.0378899682 , 104.0893199171 , + -51.8319647254 , 38.8521710524 , 75.9114239564 , 73.9206172905 , + -103.2533029987, 6.9002718274 , -36.6346436319 , -25.1990926265 , + 1.5852145953 , -50.6438436795 , 21.5018844428 , -151.9305562846, + -51.7326681814 , 21.4475994143 , 42.2564011921 , -74.0520586926 , + 49.7370635809 , -13.2957534126 , 36.6746826778 , -31.7005492589 , + 148.4894964268 , 79.7890632353 , 16.8856024809 , 16.1690460177 , + 39.2665169484 , 117.2461167794 , -37.4827984831 , -47.8387803604 , + -95.7025286193 , 34.3058214285 , -124.9536456028, 56.1640195764 , + 94.3636873606 , 35.3992852810 , -38.3920852159 , -100.5738062016, + -29.7837022314 , 42.9133913996 , -34.2715618187 , -14.3589115627 , + -16.5935468750 , 20.4574192236 , -88.7897972666 , -38.6285080386 , + 53.3203422726 , 98.5991486746 , 122.7305462474 , 67.7902817187 , + 5.1764117389 , 5.0632821624 , 21.9288789574 , -78.3140512638 , + -21.2069682335 , 23.6342010925 , 34.4445769455 , 59.1346766615 , + 28.9978778000 , 39.8121180845 , -17.1650033520 , -56.9174900874 , + 17.8157086148 , -112.8801457350, -122.4019040408, 140.8669393157 , + -65.4664329639 , 40.6952775518 , 32.7260891658 , -43.2565155866 , + 19.3945751928 , -20.1815002000 , -67.6601711640 , -18.1921178207 , + -35.6802153684 , 49.9550290306 , 131.4925251016 , -31.2940938167 , + -5.2848453344 , -109.5580577933, 20.2437599390 , -8.8782958734 , + 54.1836717264 , 7.2555852190 , -3.5698316137 , -51.9236786262 , + 6.7861547980 , -104.4814551670, 45.8458629668 , 70.0890876844 , + 38.3572837740 , 61.8024165129 , 68.0176962024 , -12.8193934080 , + -21.4661610917 , -0.9377108815 , -74.2100679061 , 71.0490808147 , + 91.9813889497 , -14.5797640164 , 3.5036749129 , -138.3605478356, + -48.1501349794 , -16.0636922482 , -12.1334197606 , 15.0562207637 , + -34.0878176054 , 55.1075126157 , 97.3829871877 , 0.2053358099 , + -94.8713267382 , 51.5460954054 , 21.2966946363 , 58.1331025047 , + -23.4599044132 , -19.3315856528 , -8.4497193577 , -1.9594679356 , + -33.1906549336 , -144.6825417978, -57.1218958072 , 35.7353406097 , + 61.4666549819 , 14.6536253128 , 82.1632196866 , -44.6230161723 , + -91.1022589278 , -18.5737673927 , -136.8975612334, 56.9606788003 , + 70.7059960183 , -68.2829345081 , -10.2629800455 , -53.6385325047 , + -68.7928766204 , 88.2444688302 , 83.1412324801 , -102.9206928160, + -68.2329763159 , -69.7552955469 , 108.2132269009 , -28.2582329307 , + 5.6685898328 , -36.0392956840 , 43.3269513128 , -8.6436416796 , + -16.5054886972 , 11.5008791788 , 39.6923606683 , -28.9039554061 , + 13.5938214364 , -23.6296332202 , 49.1171161163 , 53.1636857935 , + -62.9672053166 , -54.2594757384 , 48.3838956696 , 8.0469071555 , + -33.6472086213 , -120.5381752144, 55.0880453111 , 17.8990740563 , + 144.9402232336 , 101.7886229203 , -73.3666393712 , -16.4721379138 , + -12.7447935685 , 101.8245160983 , -49.7026860415 , -15.1227790364 , + 65.7430288442 , -131.8695390036, 10.2750933946 , 90.9752774838 , + -26.5859990591 , -95.6962772568 , 76.2174589344 , 24.8796848060 , + -38.8938223046 , 54.1687774852 , -37.3585968996 , -34.6848570502 , + 33.0151011570 , -55.8345877671 , -3.9009101671 , -31.5024971691 , + -9.6863895491 , 91.8719195957 , -58.9993249744 , -25.6887030614 , + -8.0829472205 , 4.6386491741 , -71.4019697167 , -21.3734669095 , + 86.2079144404 , 79.6823974266 , -0.0910915997 , 44.8067718095 , + 58.7204020766 , 72.6856808976 , -50.3373732478 , -116.1175365534, + -15.0884909384 , 5.4593772059 , -63.6553527905 , 37.3460388205 , + -32.2399421679 , 95.7569350513 , -7.3700141964 , -56.0370832967 , + -41.7377150439 , -42.0042856519 , 12.5134312941 , 93.7845584531 , + -32.4801087157 , -33.3976050318 , -24.2252126001 , -46.3199064467 , + -20.3704610276 , 15.8571376404 , 88.9127217235 , -33.1132582267 , + -1.0005675836 , -28.1780471904 , 150.9349379135 , 38.0600520828 , + 36.4338677563 , -3.3709201641 , 29.7709773016 , 16.5064119077 , + 21.3147729463 , 110.6714300904 , 18.8406036507 , 14.8963298097 , + 50.9975960392 , 16.3991140350 , -194.0805845907, -41.6723945839 , + -74.8991127408 , -6.4587655805 , -0.6883628218 , -49.8709647175 , + 194.2265120473 , 64.3043624521 , 16.0040882780 , 68.4032551772 , + -43.4050313128 , 84.6826289824 , -28.1357565943 , 134.6895584120 , + -7.9746152680 , -95.6692886462 , -48.9444370342 , 79.4479343188 , + -50.5345228122 , 52.4800633307 , -14.7735051703 , -20.1510237050 , + 22.5049816980 , 64.4191999102 , 24.8385648232 , 99.4265041360 , + 62.0189508473 , -28.3892600378 , -109.8842008564, -79.0407483407 , + 18.3408112020 , 49.1650536089 , 31.5419844924 , -36.1160722679 , + -132.9148081329, 10.4053531567 , -129.2463715470, -43.4602207151 , + -24.2420653292 , 91.5388317556 , 21.4762248190 , -44.3810909139 , + 18.4098011282 , -45.8691164539 , -20.9831197962 , 16.2076792914 , + 66.0224147666 , -13.6794615513 , 101.2163279622 , -62.4462618603 , + 22.2040981785 , -52.3208382802 , -24.7909079016 , 58.5150375093 , + 18.8569705105 , -55.6083430939 , 131.0273367422 , -34.5209015065 , + 121.4357296573 , -77.2590299593 , -51.5929566898 , 5.0247131098 , + -23.8451707592 , -4.5912313547 , 31.1387246821 , 61.7019310824 , + 49.1912429744 , -50.5836913031 , -74.8182600630 , -21.6209317022 , + 20.9409464654 , -72.7870824583 , -28.3530746820 , -45.0794425434 , + -13.4910629905 , -62.0158772255 , -34.1421181246 , 44.2844972784 , + 8.4213193211 , 79.9349022793 , 60.0160502260 , 32.2272994080 , + -72.2893887746 , 17.3063698247 , -134.6335742431, 64.6499736261 , + 7.1411921919 , -37.5517577873 , 6.2405670930 , 117.1920927305 , + 128.7420689815 , -3.1556854963 , -13.4100422909 , -11.9336372907 , + -8.6022400553 , -102.0033506666, -78.4696575074 , 15.0765861403 , + -111.5219718576, -13.4162786508 , 38.2437013694 , 61.1637732561 , + -34.4804160003 , 107.4438003830 , -79.4193067813 , -81.1842853968 , + -26.2622970331 , 132.3205425408 , -119.1464268477, 67.3048866598 , + 103.3266736715 , -58.1865815617 , 27.6231908601 , -11.2004371750 , + 26.0340617206 , 12.5696123916 , 0.6442714420 , -30.7393043544 , + 1.5314955897 , 49.9110088250 , -106.1358721920, 51.1608329944 , + -32.8684239794 , -27.7215905745 , -11.6450303367 , -36.7731678028 , + 59.9383486599 , -4.6301990580 , 5.0361682939 , -10.5669407980 , + 124.0908762205 , 35.8305364082 , -123.6216777114, -74.2569079167 , + -56.7651776816 , 16.0736385582 , 23.5030632215 , -110.6764295938, + 44.3086821806 , 9.4452708243 , 5.3300080251 , 39.0483916714 , + 151.4550562868 , 62.8957092621 , -116.8103461233, 5.1129927759 , + -33.2252515135 , -9.4522506046 , 22.7026048372 , -15.5264414569 , + 71.2087620034 , 19.1191568332 , 50.3019546809 , -5.6096922409 , + 22.9344126462 , -7.7591876203 , 31.8949515564 , -58.4253952381 , + 66.4341297173 , -19.0583083044 , 96.7695087855 , 20.4934280047 , + 4.9544603116 , -20.8288135920 , -173.2659655408, -62.4883621640 , + -48.5528422703 , 12.1437504278 , 60.2482234666 , -19.6072312919 , + -34.6320214291 , 129.0089698963 , -50.9042160618 , 98.3952661477 , + -4.7051792479 , -13.1768910826 , 69.5138802139 , 58.5748201565 , + -45.9385652563 , 151.7952104306 , 34.2541941013 , -58.0417838381 , + 28.1480473670 , 46.4006562684 , 97.7001828545 , 4.0855607626 , + -32.6097018162 , 16.8913949959 , 105.7266202978 , -89.3978374651 , + -60.9338593128 , -41.2220734230 , 49.9393070783 , 95.0974764854 , + 49.2498366456 , 58.6214364590 , 34.1113830569 , 45.6634098874 , + -22.5356086770 , -97.1978653617 , 86.5565049535 , 70.6118545777 , + -30.6978082909 , 118.7238621666 , 14.5922386932 , 11.3449652072 , + 65.6007783405 , 82.6369678204 , -52.0390492248 , -47.0160551227 , + -95.5142448634 , 99.7162626888 , -36.5523815090 , -42.8042935534 , + 68.3566199798 , -13.8451547552 , -71.1629911780 , 36.2989433752 , + -32.4867163365 , 112.4079947071 , -75.6295117422 , 47.5276421639 , + 51.8078250755 , -26.8715188457 , -9.6291144797 , 40.1999849640 , + -38.4634033246 , 40.9764960915 , -26.1715730268 , 36.5996396515 , + -26.9924731886 , 53.7879986570 , -83.1658398348 , 23.6381378489 , + 43.8794937753 , -55.4133836419 , 90.0266130838 , 14.1036181982 , + -18.1225736715 , 85.1363181151 , -62.5970846379 , -18.5291947838 , + -25.7341986703 , -49.7061342931 , -59.0442763971 , 50.8960636803 , + -87.6471123430 , -36.7217762531 , 22.5952364054 , 11.1107885650 , + -0.5377327229 , 160.8145792630 , 73.3103441505 , 10.1656872354 , + -50.4554350397 , -57.3478171016 , -15.4201715357 , -26.9135446491 , + -4.9891264771 , -37.0226770057 , -80.9919535641 , 50.4418660876 , + -25.8517575250 , -69.9538258421 , -17.5730160671 , 15.9405836751 , + 113.9545230349 , -46.1040379057 , -94.2458635014 , -69.0338522452 , + 43.5813790265 , 107.1836101171 , -55.1012654323 , -77.1529555887 , + -33.1530320656 , -94.5582659641 , -53.6837586872 , 27.0680381378 , + 93.9385415207 , -61.0955216188 , 18.0530957225 , 7.9150142320 , + -12.1218191587 , 34.0173961457 , 40.0084937565 , 9.8119275580 , + 44.2065861274 , -1.8718514394 , 67.4740024215 , 46.7391150131 , + 207.2404815875 , 45.1635364462 , 43.3580102761 , -44.0244218674 , + 83.2387206007 , -8.6441851856 , 12.3993902588 , -22.5091685270 , + -19.8332981376 , 97.9196509289 , -76.6720306234 , 28.9740705859 , + 121.9415248016 , 9.6656982611 , -51.0996453694 , 37.3704374740 , + 74.7589840907 , -113.4066752631, 120.0029566342 , -105.3786221360, + 81.8152755619 , -13.4979932982 , -21.4680758393 , -85.1088235539 , + -65.3610798409 , -35.0444139470 , -48.0220794487 , -41.6210317362 , + 33.1212995259 , -82.1480936443 , -10.5479715135 , 76.4601917004 , + 42.1983651157 , 92.6104239912 , -42.3536237955 , -24.5644182272 , + 30.4446637772 , -90.2899420489 , 63.6723540422 , 103.0895811428 , + 64.1706769263 , -10.7069812309 , 21.8927240409 , 6.3571071738 , + 57.1457649358 , -52.9866276448 , 66.0981829072 , -29.5372056881 , + -79.2252039810 , -136.2440652798, -57.0106422562 , 86.8203548141 , + 66.4244149837 , 53.3230426111 , -66.1283059222 , -131.0402660353, + 8.0548411081 , 122.9088988100 , 1.2626894208 , -60.5059112373 , + -68.8707203082 , -6.4747987200 , 85.8411327244 , 99.9624156733 , + 90.4197864338 , -35.9630441182 , -22.9158275507 , -17.3660128776 , + 16.7845345761 , 34.7219749782 , -39.3513765878 , 1.0460702756 , + -60.9494500182 , 20.0900333387 , -85.9636743832 , 88.4400782168 , + 15.0729628728 , 61.5499846243 , 11.8579871757 , 107.8617581581 , + -42.9393027864 , -62.8422307621 , -19.0589600542 , 4.0750325807 , + -36.0651825425 , 55.7638724501 , -10.4691736080 , -55.5672537178 , + -61.2061519915 , -21.1885348576 , -131.2535612498, 24.7463552676 , + 22.9426321237 , 14.3038202264 , -138.0926317438, -59.0892900856 , + -162.5416439986, 7.1307658250 , -141.1236672256, -4.7173618068 , + -16.7741532807 , -68.2615451173 , -2.6608701102 , 84.1978109826 , + -11.3446202072 , 59.9630033088 , -1.8994925010 , -37.9301641959 , + -119.4435600954, -11.4587491646 , 12.2423215240 , -7.3169898616 , + -67.0373621128 , 36.0198843055 , 53.9791315249 , -134.5885680695, + -83.8330811965 , -16.6714816463 , -8.8498552035 , -24.0513088196 , + -22.9444328877 , -37.7961441531 , 25.1975736186 , -136.1611637464, + -5.0843464033 , -10.3939554694 , 20.7422826935 , 75.6854136623 , + 46.4179626736 , -57.0052830175 , 7.3457235521 , -51.5504447254 , + -158.4375751701, -200.2426967181, -48.1234996261 , 1.6623945527 , + 21.1746524375 , 99.4092980367 , -2.3206772903 , 45.7989166757 , + 2.0181548348 , -88.0556010969 , -59.1527212096 , 47.3607925077 , + -10.4181140309 , 56.3558125650 , -8.9799125560 , -30.0376711812 , + -36.7132904688 , 35.7785050392 , -13.0763909369 , -2.1855594714 , + 18.1550954005 , -28.6711803575 , -55.4495172398 , -2.8812973198 , + -59.9575059158 , 40.0588875786 , 57.4713686602 , -3.2835144853 , + -36.7193552111 , -64.9415131516 , -166.9555466445, -23.5556853844 , + -54.9408569587 , -35.2310451959 , 21.3345143458 , 65.7590671151 , + 51.2214538168 , 46.1271939944 , -42.2235267919 , 127.2329928299 , + 105.2391778600 , 17.6726845966 , -129.9021148044, 8.7065613044 , + -94.0987112511 , -3.5375742950 , -23.1385452379 , 60.6219530633 , + 92.5445564235 , 48.5111974469 , -52.5699309159 , -60.0634811685 , + 25.9034368684 , 140.0249495491 , 1.5918852392 , 38.0266038291 , + 17.5588710703 , 3.4294066089 , -27.6748782173 , 59.6182974489 , + -35.2924781853 , -38.6198576115 , -13.6119803198 , 7.8375587489 , + 22.7250686519 , -28.3524510951 , -34.4269062817 , 22.6464817325 , + -61.6528147860 , -5.9782002429 , 61.4730771294 , 43.5582379527 , + 55.6862408270 , 87.8745651631 , 46.3401042715 , -19.8780979663 , + 74.1272633369 , 29.8590452377 , -12.8665765140 , 34.2931401219 , + 53.9279617551 , -16.9017895140 , -70.1527553166 , -79.6367897992 , + 109.3728271017 , -129.2214826835, -53.4644539730 , -51.5654458993 , + 17.6062148433 , 3.5090251835 , 74.2615941204 , -109.3431097845, + 40.1403465151 , 28.8714561280 , 94.0868659302 , -19.0047033845 , + -60.0967410050 , -19.0998457619 , -67.2027075128 , 72.0711434846 , + -17.8737851232 , 123.7050551274 , 132.6331504104 , 25.5018761009 , + -36.7817189239 , -29.1580893235 , -6.5848563828 , 90.2868948516 , + -35.7017258498 , -68.5675432955 , -52.4888589786 , 47.1377730021 , + -7.4546621940 , -52.0657517138 , -49.0404829633 , -114.6910280126, + -117.6819819437, -32.7856729408 , 31.8232065591 , 12.1192973039 , + 35.2678513420 , -1.0336778293 , 30.7021249679 , 127.0442906046 , + -84.8457819393 , 28.9862843096 , -47.3524701726 , -126.1094998460, + -2.9700276582 , -2.4956545870 , -53.8624121141 , -85.2114117637 , + 76.9057985618 , 137.1205201755 , -19.0830817212 , 14.3407526579 , + -56.5921994449 , -25.6084873186 , -44.9470801106 , -133.3139496090, + 0.3487447576 , 33.4499716730 , 34.7126257844 , -9.3307383323 , + 27.2996276947 , 10.8765676134 , -91.1032360444 , -90.9584216222 , + 1.6981490570 , 96.8557438791 , 56.7726390913 , -44.3246449237 , + 52.3260643361 , 21.5551140465 , 27.4535327381 , 2.0072717479 , + 7.4823125629 , 77.1185863870 , 16.1372262663 , -10.7206012957 +}; + +const float32_t controller_f32_coeffs[CONTROLLER_MAX_COEFFS_LEN] = +{ + /* S->Kp, S->Ki, S->Kd; */ + 0.0000000000 , -1.0336778293 , 56.7726390913 , + 0.3487447576 , 0.0000000000 , 27.4535327381 , + -29.1580893235, 1.6981490570 , 0.0000000000 , + 0.0000000000 , 0.0000000000 , -2.4956545870 , + 0.0000000000 , 8.7065613044 , 0.0000000000 , + 0.0000000000 , 0.0000000000 , 0.0000000000 , + 18.1550954005 , -5.9782002429 , 2.0072717479 , + 33.1212995259 , -82.1480936443, -10.5479715135, + -23.6296332202, 49.1171161163 , 53.1636857935 , + 7.2830326091 , 66.8368719314 , 33.9778190671 , + 9.4452708243 , 5.3300080251 , 39.0483916714 , + 6.9915412654 , -8.9909197429 , -78.9165936808 +}; + +const q31_t controller_q31_coeffs[CONTROLLER_MAX_COEFFS_LEN] = +{ + 0x00000000, 0xFEF760E4, 0x38C5CBAD, + 0x00594756, 0x00000000, 0x1B741AB9, + 0xE2D78775, 0x01B2B9E6, 0x00000000, + 0x00000000, 0x00000000, 0xFD811CC8, + 0x00000000, 0x08B4E134, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, + 0x1227B455, 0xFA0594AB, 0x0201DC90, + 0x211F0D7C, 0xADDA1689, 0xF573B824, + 0xE85ED05B, 0x311DFB52, 0x3529E750, + 0x074874D3, 0x42D63D3D, 0x21FA525A, + 0x0971FD45, 0x05547B68, 0x270C6366, + 0x06FDD5A6, 0xF7025315, 0xB1155A1E +}; + + +const q15_t controller_q15_coeffs[CONTROLLER_MAX_COEFFS_LEN] = +{ + 0x0000, 0xFEF7, 0x38C6, + 0x0059, 0x0000, 0x1B74, + 0xE2D8, 0x01B3, 0x0000, + 0x0000, 0x0000, 0xFD81, + 0x0000, 0x08B5, 0x0000, + 0x0000, 0x0000, 0x0000, + 0x1228, 0xFA06, 0x0202, + 0x211F, 0xADDA, 0xF574, + 0xE85F, 0x311E, 0x352A, + 0x0748, 0x42D6, 0x21FA, + 0x0972, 0x0554, 0x270C, + 0x06FE, 0xF702, 0xB115 +}; diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.c new file mode 100644 index 0000000..0f9709e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.c @@ -0,0 +1,13 @@ +#include "jtest.h" +#include "controller_tests.h" + +JTEST_DEFINE_GROUP(controller_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_GROUP_CALL(pid_reset_tests); + JTEST_GROUP_CALL(pid_tests); + JTEST_GROUP_CALL(sin_cos_tests); + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c new file mode 100644 index 0000000..a930dbb --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c @@ -0,0 +1,52 @@ +#include "jtest.h" +#include "arr_desc.h" +#include "arm_math.h" +#include "type_abbrev.h" +#include "test_templates.h" + +/* Bucket of zeros. For comparison with the output of arm_pid_reset_xxx. */ +ARR_DESC_DEFINE(float32_t, zeroes, 3, CURLY(0)); + +/** + * Define a JTEST_TEST_t for the function arm_pid_reset_xxx function having + * suffix. + */ +#define ARM_PID_RESET_TEST(suffix) \ + JTEST_DEFINE_TEST(arm_pid_reset_##suffix##_test, \ + arm_pid_reset_##suffix) \ + { \ + /* Initialise the pid_instance */ \ + arm_pid_instance_##suffix pid_inst = { 0 }; \ + pid_inst.state[0] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff; \ + pid_inst.state[1] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff; \ + pid_inst.state[2] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff; \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES(arm_pid_reset_##suffix(&pid_inst)); \ + \ + /* Test correctness */ \ + TEST_ASSERT_BUFFERS_EQUAL( \ + pid_inst.state, \ + zeroes.data_ptr, \ + 3 * sizeof(TYPE_FROM_ABBREV(suffix))); \ + \ + return JTEST_TEST_PASSED; \ + } + +ARM_PID_RESET_TEST(f32); +ARM_PID_RESET_TEST(q31); +ARM_PID_RESET_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(pid_reset_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_pid_reset_f32_test); + JTEST_TEST_CALL(arm_pid_reset_q31_test); + JTEST_TEST_CALL(arm_pid_reset_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c new file mode 100644 index 0000000..2e1c56e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c @@ -0,0 +1,79 @@ +#include "jtest.h" +#include "arr_desc.h" +#include "arm_math.h" +#include "ref.h" +#include "type_abbrev.h" +#include "test_templates.h" +#include "controller_test_data.h" +#include "controller_templates.h" + +/** + * Define a JTEST_TEST_t for the function arm_pid_xxx function having + * suffix. + */ +#define ARM_PID_TEST(suffix,type) \ + JTEST_DEFINE_TEST(arm_pid_##suffix##_test, arm_pid_##suffix) \ + { \ + uint32_t i,j; \ + \ + arm_pid_instance_##suffix fut_pid_inst = { 0 }; \ + arm_pid_instance_##suffix ref_pid_inst = { 0 }; \ + \ + for(i=0;i 0 ? (x) : -(x)) + +/* + Function to test correctness of sin_cos output by comparing it with reference library +*/ +#define COMPARISON_INTERFACE(type, threshold) \ + if ( (ABS((type) sin_val_ref - (type) sin_val_fut) > \ + (type) threshold ) || \ + (ABS((type) cos_val_ref - (type) cos_val_fut) > \ + (type) threshold)) \ + { \ + JTEST_DUMP_STRF("Error: %f %f\n", \ + ABS((type) sin_val_ref - (type) sin_val_fut), \ + ABS((type) cos_val_ref - (type) cos_val_fut)); \ + return JTEST_TEST_FAILED; \ + } + +/* + Sine and cosine test function for float32_t input +*/ +JTEST_DEFINE_TEST(arm_sin_cos_f32_test, arm_sin_cos_f32) +{ + /* Test function for all input degree values */ + TEMPLATE_DO_ARR_DESC( + degree_idx, TYPE_FROM_ABBREV(f32), + degree, arm_sin_cos_degrees_f32 + , + /* Display cycle count and run test */ + JTEST_COUNT_CYCLES( + arm_sin_cos_f32( + degree, + (TYPE_FROM_ABBREV(f32) *) &sin_val_fut, + (TYPE_FROM_ABBREV(f32) *) &cos_val_fut) + ); + ref_sin_cos_f32( + degree, + (TYPE_FROM_ABBREV(f32) *) &sin_val_ref, + (TYPE_FROM_ABBREV(f32) *) &cos_val_ref); + + /* Test correctness */ + COMPARISON_INTERFACE( + TYPE_FROM_ABBREV(f32), + MAX_DELTA_f32)); + + return JTEST_TEST_PASSED; +} + + +/* + Sine and cosine test function for q31_t input +*/ +JTEST_DEFINE_TEST(arm_sin_cos_q31_test, + arm_sin_cos_q31) +{ + /* Test function for all input degree values */ + TEMPLATE_DO_ARR_DESC( + degree_idx, TYPE_FROM_ABBREV(q31), + degree, arm_sin_cos_degrees_q31 + , + /* Display cycle count and run test */ + JTEST_COUNT_CYCLES( + arm_sin_cos_q31( + degree, + (TYPE_FROM_ABBREV(q31) *) &sin_val_fut, + (TYPE_FROM_ABBREV(q31) *) &cos_val_fut) + ); + ref_sin_cos_q31( + degree, + (TYPE_FROM_ABBREV(q31) *) &sin_val_ref, + (TYPE_FROM_ABBREV(q31) *) &cos_val_ref); + + /* Convert q31 numbers to float for comparison purposes. */ + ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &sin_val_fut, &sin_val_fut, 1); + ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &cos_val_fut, &cos_val_fut, 1); + ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &sin_val_ref, &sin_val_ref, 1); + ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &cos_val_ref, &cos_val_ref, 1); + + /* Test correctness */ + COMPARISON_INTERFACE( + TYPE_FROM_ABBREV(f32), + MAX_DELTA_f32)); + + return JTEST_TEST_PASSED; +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(sin_cos_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_sin_cos_f32_test); + JTEST_TEST_CALL(arm_sin_cos_q31_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c new file mode 100644 index 0000000..50ec433 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c @@ -0,0 +1,38 @@ +#include "jtest.h" +#include "ref.h" +#include "arr_desc.h" +#include "fast_math_templates.h" +#include "fast_math_test_data.h" +#include "type_abbrev.h" + +SQRT_TEST_TEMPLATE_ELT1(q31); +SQRT_TEST_TEMPLATE_ELT1(q15); + +SIN_COS_TEST_TEMPLATE_ELT1(f32, float32_t, sin); +SIN_COS_TEST_TEMPLATE_ELT1(q31, q31_t, sin); +SIN_COS_TEST_TEMPLATE_ELT1(q15, q15_t, sin); + +SIN_COS_TEST_TEMPLATE_ELT1(f32, float32_t, cos); +SIN_COS_TEST_TEMPLATE_ELT1(q31, q31_t, cos); +SIN_COS_TEST_TEMPLATE_ELT1(q15, q15_t, cos); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(fast_math_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_sqrt_q31_test); + JTEST_TEST_CALL(arm_sqrt_q15_test); + + JTEST_TEST_CALL(arm_sin_f32_test); + JTEST_TEST_CALL(arm_sin_q31_test); + JTEST_TEST_CALL(arm_sin_q15_test); + + JTEST_TEST_CALL(arm_cos_f32_test); + JTEST_TEST_CALL(arm_cos_q31_test); + JTEST_TEST_CALL(arm_cos_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c new file mode 100644 index 0000000..cf806e3 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c @@ -0,0 +1,364 @@ +#include "fast_math_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +float32_t fast_math_output_fut[FAST_MATH_MAX_LEN] = {0}; +float32_t fast_math_output_ref[FAST_MATH_MAX_LEN] = {0}; +float32_t fast_math_output_f32_fut[FAST_MATH_MAX_LEN] = {0}; +float32_t fast_math_output_f32_ref[FAST_MATH_MAX_LEN] = {0}; + +const q31_t fast_math_q31_inputs[FAST_MATH_MAX_LEN] = +{ + 0x414A5524, 0x4CAB5A17, 0x2D6F5B56, 0x7DAF4E3B, 0x29B226EB, 0x41F6F6A , + 0x25CE38BF, 0x3A970AFA, 0x3A44382A, 0x05540F8 , 0x3D060524, 0x13D56570, + 0x17D7791D, 0x7FE0438C, 0x26741841, 0x40A66E54, 0x218E4386, 0x39FF3726, + 0x0DC177CA, 0x702F2CF5, 0x41142FF1, 0x6C1476AB, 0x15F640DD, 0x662C4E49, + 0x38055E7E, 0x770871FE, 0x4F8B5360, 0x0D1928A0, 0x57647821, 0x258558CF, + 0x0C0C604D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0x36462E24, 0x6CE00F5C, + 0x66D40948, 0x355B5831, 0x3B72150A, 0x1EB61530, 0x73394127, 0x773F26F4, + 0x18052980, 0x038D6587, 0x1CF517F4, 0x22AD1691, 0x7A812473, 0x7CDC7D7F, + 0x4A5110D0, 0x6D895BB9, 0x0FD60F35, 0x1A215530, 0x20EB6DDA, 0x3DE62516, + 0x250123E1, 0x5ED813C8, 0x61E175B1, 0x2CBB32F3, 0x6D350907, 0x5B140D7E, + 0x6EAE272D, 0x3E221841, 0x418B7B88, 0x26BB1B80, 0x3CF010E4, 0x24DB166C, + 0x79AB7E42, 0x62DF28D1, 0x47004665, 0x63F56FC6, 0x419E0C75, 0x46BE1F38, + 0x243239B2, 0x758D03E0, 0x5CE12926, 0x3F574B74, 0x1F4458E2, 0x71D5639 , + 0x03A17B49, 0x173A7C76, 0x06EF7531, 0x48D32F34, 0x7D3E3063, 0x0F2F3549, + 0x5C314C9 , 0x18CB6B6D, 0x26F83697, 0x447B1E9C, 0x2E323A33, 0x50745715, + 0x01AC5746, 0x655A4E04, 0x4891060F, 0x1DA36B4F, 0x60E6227F, 0x20BF5EB4, + 0x50B3225B, 0x40C10544, 0x415656C , 0x15405EAE, 0x185863E1, 0x236A1C4E, + 0x08BD21F9, 0x2ACF7A68, 0x773665E5, 0x4EDF5F66, 0x617A1610, 0x524F4968, + 0x42D006CD, 0x5F000079, 0x24DC2447, 0x6A4F5599, 0x37064D4A, 0x1DE70608, + 0x233A2EE5, 0x137E488E, 0x18061B7B, 0x4079569D, 0x24A817D5, 0x44CE48F5, + 0x575F7883, 0x22406802, 0x71AD70BB, 0x1D4A5D79, 0x3CBC7CE4, 0x335840D8, + 0x05792E47, 0x27AD2C05, 0x3D196EAB, 0x331A40AF, 0x33035831, 0x13D93987, + 0x7C542094, 0x045F317E, 0x5DC43F8B, 0x1379650C, 0x5C20193F, 0x7DD50298, + 0x1D482B82, 0x4A6B6062, 0x5C8A757B, 0x272917C1, 0x10E16FBC, 0x355A5882, + 0x66F86A35, 0x604555A1, 0x7DF7FBB , 0x758A6216, 0x1A113463, 0x53541BAD, + 0x21576756, 0x483B6D8D, 0x1F052FCC, 0x4EA63DFB, 0x55B84677, 0x7B2E04F2, + 0x787A796C, 0x04A12CD3, 0x46029BD , 0x1DB22DD8, 0x1A8C7F28, 0x061E452E, + 0x132D3F78, 0x76525852, 0x73357BBA, 0x6BBB0A58, 0x62536AFA, 0x3F6B65EF, + 0x6DC57B58, 0x1EB718CE, 0x66B02740, 0x5FF60B47, 0x32477B8F, 0x7FF35302, + 0x29FD3E40, 0x475A43D1, 0x6FF9528A, 0x2018209D, 0x47E079C9, 0x4CF576D3, + 0x28074E34, 0x5D6F58ED, 0x234045D1, 0x51CE35F9, 0x25297896, 0x644320FE, + 0x0F4449A9, 0x54C361C6, 0x701D52F1, 0x4E094820, 0x718F0810, 0x61540689, + 0x79DE5A1F, 0x52865C23, 0x48AC3A4B, 0x6A0C1BE0, 0x21B705DB, 0x7086465D, + 0x1CC10929, 0x1E1D716E, 0x6D231D4C, 0x20495108, 0x38FF1971, 0x149C78D4, + 0x441F1E8B, 0x43D95372, 0x69C324B4, 0x210B7DC9, 0x47815E78, 0x02476137, + 0x6163DDF , 0x390D6EC2, 0x2F684E5B, 0x0E680ABD, 0x02232615, 0x12593380, + 0x7B1465FE, 0x065A6957, 0x130F53EB, 0x6D772EF7, 0x10E916B6, 0x63BC7A68, + 0x2ACB00BB, 0x651C5590, 0x194714B5, 0x730904EE, 0x59BB61B4, 0x34867DBC, + 0x391C706C, 0x3C164218, 0x28931CD0, 0x129A66AB, 0x13171F4D, 0x62882872, + 0x4B167FD4, 0x66902F4C, 0x7A794932, 0x54B152C , 0x30856EA9, 0x39466D55, + 0x36696451, 0x0F5B1E8C, 0x077A3C6A, 0x51B956B4, 0x367E2D2A, 0x1D2C662A, + 0x78FB6880, 0x4E6D40B6, 0x40706FDC, 0x4DF9679C, 0x20306EDB, 0x63812AE7, + 0x255D2748, 0x1B8B617B, 0x3E036FAD, 0x04E444A7, 0x55A37517, 0x669B2988, + 0x18FD5E8C, 0x67BD05CE, 0x34BB346C, 0x76994800, 0x05B958B6, 0x6DFA2FEF, + 0x2055B5C , 0x1F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB90B61, 0x43235DAC, + 0x31D424B4, 0x768C0D7E, 0x162F2F9D, 0x7B2A7A99, 0x79392693, 0x442D12C0, + 0x0692273E, 0x59A16E80, 0x5D956856, 0x44E73DAC, 0x0D874532, 0x5F5C1DD0, + 0x5D167858, 0x05597EA2, 0x1D821476, 0x59654ED2, 0x594C0DC7, 0x1A873506, + 0x3F693200, 0x7A651AB5, 0x20CC3C8A, 0x1F9E662C, 0x78E7631 , 0x2A01DA0 , + 0x3088472F, 0x12EE0D42, 0x360D4D5F, 0x73337E48, 0x0D634C06, 0x233A0ACB, + 0x706651ED, 0x7AA54079, 0x262239D1, 0x3EBB6BB6, 0x225A4F3D, 0x32581A06, + 0x6E6F5780, 0x577377C7, 0x75ED1DDC, 0x10DF2D15, 0x3C7929BC, 0x37175917, + 0x354E381C, 0x762A2DD7, 0x76435AC1, 0x73BB749E, 0x52FE4E7E, 0x6C8140F4, + 0x57694875, 0x12D30822, 0x474227CF, 0x37926D98, 0x121C7E24, 0x204E1EE7, + 0x58C6268 , 0x2152080 , 0x316C3323, 0x7AB14A31, 0x61C13C03, 0x7D8E74F1, + 0x73F446D0, 0x6C6C6A0A, 0x3BFD79FB, 0x67242969, 0x3E5524EB, 0x0FF5534 , + 0x52F05F1C, 0x17102DE3, 0x540F4A21, 0x798468E7, 0x419545EB, 0x193F7880, + 0x2B246B20, 0x408A2BC4, 0x4BF66A49, 0x40894C55, 0x4CAA6398, 0x247856E9, + 0x2F2A647D, 0x22F55D33, 0x70D37915, 0x50634C72, 0x5983671 , 0x2BCC5AF8, + 0x1A77D48 , 0x411B5CFA, 0x71074D7E, 0x3A6B3593, 0x61425F05, 0x6271012A, + 0x5B830310, 0x3D8418CA, 0x10A50792, 0x239F7137, 0x213D5071, 0x7F9930D4, + 0x2462664F, 0x54180F8E, 0x291505BA, 0x6586387A, 0x144B2C12, 0x18E425C7, + 0x3AA43373, 0x18F0503C, 0x19462AC0, 0x58B452EF, 0x72473895, 0x26BF5435, + 0x6DA553B , 0x60912FA6, 0x5C337331, 0x3D93CD7 , 0x4D035752, 0x20691929, + 0x389962F9, 0x36E701E9, 0x758B642C, 0x5FCA69E3, 0x596027F4, 0x2D5A2FD0, + 0x5F18324A, 0x3DB165AA, 0x76BA3876, 0x1BC21AF6, 0x3CC10841, 0x73A60174, + 0x625B7F58, 0x67C57724, 0x4458653C, 0x61573095, 0x2B370837, 0x03DF6CE3, + 0x5D086EFA, 0x3F5227C2, 0x191B4785, 0x60843D82, 0x30DE11F1, 0x105E226C, + 0x6E1C7AA2, 0x47AA5D14, 0x36676D03, 0x3B8D4DF6, 0x7372694 , 0x409521DC, + 0x744206A , 0x4722023F, 0x2BE46AD5, 0x63E11D76, 0x4A4A09AB, 0x5CF252B9, + 0x31586916, 0x4DFD7D84, 0x32037634, 0x2D7329D4, 0x4524582F, 0x2E5366C1, + 0x3B0E019B, 0x38530C6A, 0x6A2542D , 0x0A6A00E5, 0x119725CC, 0x54065347, + 0x1B6F7AF1, 0x6CCF71F1, 0x181117F2, 0x71674A76, 0x74F43880, 0x77A55F47, + 0x59EA5B62, 0x4A331D95, 0x3CBB276F, 0x245C4D50, 0x4718D5 , 0x07CE05D1, + 0x60D47AD5, 0x25CA1C40, 0x30061766, 0x669B39DF, 0x3D5F1320, 0x19306AD3, + 0x28B30325, 0x0DD090F , 0x6A6E6F37, 0x2DF16F66, 0x2B514C7E, 0x31101C58, + 0x7D4847FC, 0x515341CA, 0x77AB0EA6, 0x41320DAF, 0x3AF8531E, 0x24B31611, + 0x6D377331, 0x7A832A22, 0x222511C7, 0x722D1F89, 0x3B194F18, 0x261B0A4D, + 0x43F676DB, 0x4F8C6D61, 0x190F2250, 0x202E72A9, 0x560D4EA2, 0x308E67B4, + 0x36746663, 0x17CC3852, 0x27EB2EAC, 0x7FDE0AA8, 0x264719A , 0x23261EDD, + 0x3C0B339E, 0x06284D40, 0x48D82ECB, 0x24D44CF8, 0x43631B91, 0x4BF04248, + 0x36497B9B, 0x68273C58, 0x630B7AF9, 0x20CC3F26, 0x6C3B7B71, 0x574433ED, + 0x7A2552F6, 0x4CDE642D, 0x565B0142, 0x26F9207F, 0x67A207BE, 0x5B506684, + 0x44DA4780, 0x11756A0C, 0x156104AF, 0x415561B0, 0x6E3A6886, 0x1DBA1EA2, + 0x542359C8, 0x4C024E22, 0x758F052A, 0x1DD6395 , 0x2D194BAD, 0x616475A1, + 0x42084602, 0x09C274AD, 0x13CB5562, 0x57FE2D5B, 0x607A4EE5, 0x16723A91, + 0x4F624CCF, 0x2E5E24A3, 0x28FE6FAF, 0x3DDA6EF4, 0x32AF540C, 0x19A57B3B, + 0x5D1D73A3, 0x23424B3E, 0x278445F5, 0x53971C3B, 0x427D7943, 0x5221358C, + 0x26CE1A5E, 0x7B506CA4, 0x3B86636E, 0x60831F6D, 0x45E142F3, 0x21B77B04, + 0x7BB65E0C, 0x78B80F5E, 0x7D8D172B, 0x3BF33A90, 0x2D572D9 , 0x2B5B4920, + 0x36A05E01, 0x52745306, 0x47C64855, 0x1CAA669B, 0x304A2641, 0x4D6B1760, + 0x3E176D79, 0x523241B0, 0x24A67957, 0x4BDE76AF, 0x4E5F1493, 0x4C215DA5, + 0x33A052B , 0x1A4D00C2, 0x40AE6BCA, 0x390D106B, 0x69E86018, 0x5AF356CF, + 0x63561D4 , 0x44F31C6 , 0x14B6299B, 0x0D2E25F0, 0x4CBF132A, 0x45AC18B6, + 0x2227567D, 0x06B54E2F, 0x26344534, 0x22C515EC, 0x2442370D, 0x6C3721C6, + 0x34EF687D, 0x1C06323A, 0x6AF36A60, 0x60396F52, 0x6AE70AA1, 0x49D06CBC, + 0x6F9576C8, 0x584C4258, 0x3A9A27BB, 0x66DF0D47, 0x1D4804EA, 0x57DD1E67, + 0x789C7895, 0x75336111, 0x25C122C8, 0x62742114, 0x4FBF6D26, 0x3F9F6482, + 0x66F02CD9, 0x11083202, 0x499E2618, 0x7EBC1351, 0x440112F1, 0x49DF7BC1, + 0x3BF45C25, 0x31BA7FA0, 0x61AF1AED, 0x6B1F7D29, 0x2D865294, 0x63E01129, + 0x7E9E77A5, 0x100435D7, 0x1FE3A71 , 0x08597C81, 0x722849FA, 0x31C520AF, + 0x7BA178DC, 0x7F102D31, 0x5CA07864, 0x150E6F98, 0x02C34882, 0x5D041F11, + 0x0C613C57, 0x53984FD1, 0x426F38AD, 0x55992B1D, 0x7AFA078D, 0x2B253413, + 0x594B32CF, 0x32887E38, 0x28933B46, 0x1A0B4168, 0x291B4A94, 0x653A5E8D, + 0x21746BBE, 0x5EFE6415, 0x30DA429C, 0x50C5640C, 0x34711AA4, 0x529C67A6, + 0x105957CD, 0x4D287499, 0x03CA0AA7, 0x28385832, 0x25A04A02, 0x420D47A4, + 0x35627556, 0x4BC11E4C, 0x59E215C7, 0x27E838B4, 0x458612F4, 0x22827F6F, + 0x449D4DBA, 0x679B7362, 0x4E495845, 0x4FD270D1, 0x395E76A0, 0x375A655E, + 0x12E2058F, 0x73F970CA, 0x61EF73B3, 0x51FF5362, 0x67410345, 0x7FDA0B3B, + 0x221962E8, 0x17AB6543, 0x26557412, 0x4B30084D, 0x268E191D, 0x7E0D13DF, + 0x73EF127D, 0x4DEC5DB1, 0x77FA745F, 0x56002898, 0x12DD0A40, 0x157F6DDF, + 0x42A55F8E, 0x43597924, 0x7B630C3F, 0x338B6B58, 0x32945F75, 0x4FA23A0E, + 0x036E38C0, 0x33B18FD , 0x06114337, 0x24660ACB, 0x19BB02F0, 0x124C0A47, + 0x3A951701, 0x01155ABF, 0x0C612D71, 0x36074CA7, 0x51660C41, 0x635F58C7, + 0x7FC2002D, 0x0E6A7CF3, 0x65B07D07, 0x015F6A6B, 0x791B70DD, 0x6E475719, + 0x424314C7, 0x68426EB , 0x71942FEE, 0x464A2F52, 0x677579FD, 0x6BA775AE, + 0x1F66EFF , 0x1A795237, 0x78D9545F, 0x1D0B344D, 0x3BD34AB7, 0x2F85312A, + 0x16C542AD, 0x3990185D, 0x08DF3351, 0x02811AA5, 0x6D351F41, 0x4066269D, + 0x06B660BF, 0x6EDB4768, 0x5DD70CF0, 0x35D74F6E, 0x689E220C, 0x11431687, + 0x147C49C9, 0x385762BD, 0x302F0AE4, 0x1DAB67F8, 0x483256C9, 0x37D50FCB, + 0x4EA82711, 0x4D7B2C98, 0x19DB78BC, 0x58DE0DC2, 0x6AFF7E7B, 0x37621C93, + 0x792C6E19, 0x77001192, 0x7F88439D, 0x2E196A66, 0x6C71378C, 0x6AF43B3A, + 0x7C16225E, 0x6687337 , 0x4BEE1608, 0x6D5B5552, 0x345D4590, 0x681209CC, + 0x7B242819, 0x508A1416, 0x19880FE3, 0x1FC7288A, 0x24BD0502, 0x6A1D1678, + 0x20E6CA0 , 0x59BE2057, 0x5ADE11EB, 0x5EA8649D, 0x7A200E6F, 0x1149481D, + 0x72281E93, 0x0A5B0451, 0x67312D58, 0x63B849F1, 0x52217960, 0x7CDF59F3, + 0x33C775C0, 0x1EBA0799, 0x7DF1506 , 0x34E96110, 0x38FC73E3, 0x5EA059B2, + 0x022936EA, 0x316406F6, 0x43911185, 0x6C0D10F3, 0x1C6F3DF8, 0x38DB12A9, + 0x5CD41244, 0x2C9F0A7B, 0x5F4A315F, 0x77CE1C66, 0x4C800860, 0x318D53E0, + 0x7105420D, 0x575361F2, 0x750810BA, 0x217E4CA5, 0x2010140 , 0x4D884763, + 0x42BB0DA7, 0x32D53A74, 0x141C6CD4, 0x087F5FC3, 0x464B53 , 0x2D2A05F6, + 0x15532B45, 0x5D5C3CE1, 0x3EB9216A, 0x2214611B, 0x1FC52C5F, 0x11AE5DD7, + 0x20B925A9, 0x7C640AF4, 0x740009AC, 0x6D0E0321, 0x38E6A61 , 0x09104544, + 0x474F26C8, 0x15254CF3, 0x341A6B59, 0x661904CE, 0x598B2197, 0x2412659D, + 0x61976DD4, 0x329B3E16, 0x08FD1FB0, 0x304006F3, 0x3456309 , 0x55CC15F1, + 0x59DA7630, 0x5C801335, 0x0036D52 , 0x353775A5, 0x299476EB, 0x75280568, + 0x766F5264, 0x2EA233A6, 0x647619F3, 0x7FB30C7A, 0x1BC03B9 , 0x36BC3061, + 0x3F30596E, 0x3E2A527B, 0x0AC04220, 0x641979A3, 0x1ECC3B89, 0x21447BC1, + 0x4E8F2E26, 0x0C5A1D90, 0x299E5467, 0x57C947E3, 0x1D4865ED, 0x76F31C3D, + 0x4EE81CDF, 0x3479195E, 0x6FFB3AE1, 0x5C82398 , 0x300F7364, 0x47940AFA, + 0x3B853E3E, 0x598C440D, 0x224A3D89, 0x3A674204, 0x22880A38, 0x2E77F2D , + 0x22841C9C, 0x4F0609C3, 0x1FE90922, 0x09335017, 0x2D6B69A7, 0x7EDB63F9, + 0x099A74EF, 0x1F9F1B40, 0x24BE17E8, 0x251D2F7A, 0x16AC50D3, 0x28D7ED6 , + 0x6D193443, 0x76156F1B, 0x30DF6A4E, 0x64FF6794, 0x63DB2C9A, 0x74353022, + 0x556E025C, 0x23802AF9, 0x425018A4, 0x675A18BB, 0x70B227B9, 0x7FB01BF , + 0x63E7910 , 0x6C661591, 0x65745D2B, 0x4F6E379D, 0x52B32FAC, 0x1E6A1101, + 0x1DE22385, 0x2338191F, 0x469704B6, 0x4BAB4599, 0x54EB4809, 0x78393E6D, + 0x550017DD, 0x39B120E1, 0x288D52D3, 0x2D52668C, 0x20D22A68, 0x4E1207D1, + 0x3FCC0EFE, 0x47F37E64, 0x25177A90, 0x34BF5D4D, 0x5A8D3DCE, 0x6F7275A8, + 0x6BEA2655, 0x2A1810FC, 0x64DB593A, 0x0A4D4BC0, 0x2C402E93, 0x71C077F9, + 0x6F0C4577, 0x70412414, 0x752F1DC1, 0x582E38EA, 0x2C455F7B, 0x4DCD4EDB, + 0x12BC2696, 0x7B037135, 0x4FCA1F8C, 0x3D5E75F6, 0x502F41B0, 0x361653F1, + 0x2E5B0E31, 0x20266B19, 0x57E703D7, 0x467B3E00, 0x47032BA3, 0x1F776B9C, + 0x62570A84, 0x7EC75B48, 0x1BD5012 , 0x7D0A2D5D, 0x7FCC29F2, 0x291304B6, + 0x19D558ED, 0x47551C8 , 0x7D12738F, 0x3ADE0892, 0x5F741997, 0x25D2E2F , + 0x2B9F2269, 0x5C134FED, 0x15E92399, 0x54437F4E, 0x272D32AB, 0x56186AA1, + 0x7E4D355C, 0x234D7836, 0x2A871760, 0x4637A94 , 0x2C183207, 0x5FC78B3 , + 0x7F10621E, 0x276966B2, 0x6C9F4A11, 0x4E3F182C, 0x62BA2EF5, 0x25F239CD, + 0x73D63FED, 0x636E1F5E, 0x0AC15A0E, 0x3F3D33EB, 0x738326EA, 0x35C366B1, + 0x4D476E86, 0x02F63208, 0x711A1FC1, 0x426A4396, 0x7E4D1B93, 0x75E46DB7, + 0x2F3C44A7, 0x51A56F5C, 0x7AD2463D, 0x0A5639CA, 0x49952C78, 0x4C4B64F6, + 0x3AFE7F8D, 0x66993D04, 0x43867F37, 0x4BC146C2, 0x55A875EC, 0x681A1A75, + 0x30A67E1B, 0x4A4A7D0C, 0x20F77993, 0x1891805 , 0x738976AD, 0x542667D6, + 0x3C5C6EBF, 0x4499187F, 0x2BF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456, + 0x421B4F29, 0x76740F9C, 0x09163B8D, 0x3D72AAB , 0x1AD54DD7, 0x754946EE, + 0x7317342B, 0x218546D4, 0x10563DA7, 0x54BB4CCE, 0x0CE63E46, 0x5D146234, + 0x33BE6C63, 0x325044E5, 0x09D72335, 0x07C36BA , 0x365530CC, 0x2DFA448C, + 0x1663516F, 0x59B00AA , 0x150274EA, 0x12532D4A, 0x3CEF002D, 0x492F3DA5, + 0x263A2574, 0x6F8005C2, 0x14A10651, 0x2F627ABA, 0x68293238, 0x26987646, + 0x52590516, 0x10144D36, 0x59B151B9, 0x2B2A4F05, 0x53953699, 0x27851C75, + 0x180646F3, 0x2E970306, 0x32843145, 0x18F4FE8F +}; + +/* The source data is random across the q31_t range. Accessing it by word should + remain random. */ +const q15_t * fast_math_q15_inputs = (q15_t *) fast_math_q31_inputs; + +const float32_t fast_math_f32_inputs[FAST_MATH_MAX_LEN] = +{ + -1.5E-07, 5.0545058, 6.1958757, 0.1884450, 3.3656774, 0.5471223, + -5.0396892, 6.2149808, 0.4206357, 5.9024140, 0.1142128, 4.2966847, + -4.9243615, 3.3560853, 5.5628775, 5.6486144, 3.9328821, 0.8662564, + -1.3684878, 1.1444261, 0.2627620, 0.6719343, 3.8732286, 5.9040643, + -2.2271110, 2.5800587, 6.1848498, 5.9412493, 4.2514839, 6.2096863, + -4.8181437, 2.1155439, 4.1618680, 1.5341357, 1.8567268, 4.2736867, + -3.3165594, 2.5861183, 3.7864876, 4.7156566, 3.6664471, 3.4670146, + -3.6666823, 3.2158594, 0.5189454, 4.5211925, 6.2590334, 2.2276047, + -6.1025991, 2.1768018, 5.5703194, 2.8569321, 2.5976403, 1.3680509, + -0.7895111, 1.9409676, 4.5622487, 4.9189303, 4.3591961, 0.0615894, + -5.2980657, 5.7951829, 4.8440482, 0.2680398, 2.3762136, 4.4254964, + -4.5836656, 1.4091744, 1.6905207, 4.2287795, 3.0001720, 3.9189258, + -1.4856273, 1.1129014, 5.2128031, 4.8187110, 5.8715002, 0.6778860, + -1.1449692, 0.6226340, 3.0772767, 1.2141962, 5.6290528, 0.6225986, + -0.2775005, 3.5015887, 4.8537297, 1.9599772, 1.1245801, 2.1297213, + -1.3203840, 3.2053828, 5.6948550, 3.9516457, 0.6379562, 2.4558128, + -0.3431663, 3.1496534, 2.7125841, 6.2678565, 5.0994494, 3.0514394, + -5.6199810, 0.8642307, 2.4504731, 5.8267510, 5.7647838, 4.4835177, + 3.8851284, 2.1569414, 5.8812331, 0.7839784, 4.5904032, 4.0619375, + 5.2348483, 2.5024810, 4.7112719, 5.2478452, 2.0260784, 3.4699621, + 6.1520498, 3.4514073, 2.0761128, 3.8922546, 2.2659464, 4.7532896, + 2.6006151, 3.0934955, 4.3652005, 6.1118673, 2.0593452, 5.2640727, + 4.6437278, 5.9952549, 0.2005758, 2.2422740, 4.1635768, 1.7687265, + 1.4475395, 4.4681525, 3.9243074, 3.7109036, 4.1496541, 0.2987948, + 2.1914796, 2.8358565, 1.5136507, 4.4927603, 5.3795520, 1.7687650, + 4.5933278, 0.8655898, 5.2572843, 0.8708603, 3.6958286, 2.3006310, + 5.0690197, 3.1653480, 3.0762120, 5.5106597, 2.2188555, 2.8239372, + 6.0540393, 0.2657649, 6.1132775, 1.1888217, 4.1916405, 3.6847088, + 4.2418564, 2.2683684, 3.8973243, 5.0966113, 0.1209983, 0.5269928, + 6.1248595, 4.0925498, 1.4529100, 2.5352096, 0.7666775, 1.6866509, + 1.6200953, 2.0839142, 0.9565145, 2.1865966, 0.7644026, 5.5552975, + 0.5923686, 5.8436176, 2.5071164, 0.2978322, 2.1511962, 4.6242118, + 4.9931353, 3.4237447, 4.3116692, 5.6148598, 0.3442670, 1.9079607, + 0.2902301, 1.2282167, 4.5249352, 4.5349096, 5.5153742, 3.6595342, + 0.4441228, 5.7977751, 5.0288862, 1.7966571, 3.4159368, 6.1875316, + 4.4967379, 5.2714014, 2.7222564, 2.9570223, 3.5230663, 1.6907520, + 4.7062218, 3.1660203, 4.0640250, 1.9336225, 0.8716326, 2.9881129, + 2.2773988, 4.9518627, 4.9027432, 4.2003861, 0.8388295, 0.1354396, + 3.5175829, 1.8901016, 5.9024853, 6.1631993, 1.8008890, 5.0317023, + 5.6304337, 3.7543702, 5.5544410, 5.9296402, 3.4504620, 4.5765894, + 3.6238793, 0.1624673, 2.8056369, 4.0608350, 3.2748147, 2.3393094, + 5.8881908, 5.2121085, 5.3349614, 2.3407017, 3.7270886, 5.4824095, + 5.8653636, 4.2000849, 1.2992148, 4.1082644, 0.4527132, 2.5555406, + 4.1904544, 5.8667713, 5.0953493, 3.0445066, 4.7547955, 2.6203864, + 6.1059115, 6.2076281, 5.4295991, 2.4434288, 2.8572272, 1.5499814, + 4.9286757, 5.5470323, 5.7410198, 3.5078076, 3.7627993, 0.9354200, + 5.6530665, 2.8299063, 1.2922774, 5.6526739, 4.7914663, 5.5448250, + 1.7903950, 4.2300036, 4.1737937, 0.7716694, 2.5592571, 1.7296789, + 4.5029688, 1.7805566, 5.6309835, 5.1935484, 2.4506089, 3.1284165, + 4.3655898, 5.2424950, 3.8304163, 3.6111801, 2.0485834, 2.8678003, + 4.4849099, 5.5568808, 4.5292698, 0.1169475, 4.2397456, 2.7552322, + 2.7509053, 0.7353640, 5.1187960, 2.0411269, 1.5470969, 2.1533307, + 2.3605433, 3.4340988, 3.5306485, 2.4870244, 2.5015301, 3.2381477, + 4.1313862, 5.9747764, 4.5386496, 2.5137752, 5.2268018, 0.8440727, + 0.3799239, 0.5293398, 0.0000000, 2.0371338, 1.8958053, 0.0733938, + 3.3923238, 0.5992443, 0.9205800, 3.9655772, 5.3992694, 6.1212150, + 3.5866836, 6.2633946, 3.4780043, 3.2387210, 2.0777367, 2.7017810, + 3.0901098, 0.4463392, 5.5778300, 0.4061048, 2.7406309, 5.1938664, + 2.4789345, 3.8545764, 5.1436714, 5.5683790, 5.8503469, 1.1987353, + 1.6247202, 5.6414565, 3.7282025, 3.1657206, 3.8503962, 5.1485818, + 3.3419582, 1.2696753, 2.8518968, 2.6886436, 6.0698884, 3.8959208, + 4.3692639, 4.5249277, 2.1796068, 3.2483466, 3.4978155, 0.9832885, + 3.5315023, 4.3655778, 2.6794992, 5.2544420, 4.5954405, 2.2621418, + 2.8539005, 2.4277593, 4.8729535, 4.6135614, 2.7035154, 4.3589760, + 5.9389515, 4.9274787, 4.4332387, 0.6869673, 2.4500066, 3.7127639, + 2.8863700, 0.3162955, 1.4368865, 5.2413645, 0.0982985, 5.4268554, + 0.4905223, 4.2037186, 3.1429204, 1.3696954, 3.5915675, 0.7677371, + 4.2170618, 3.7673071, 0.3517086, 0.3540136, 0.9581898, 0.1232828, + 2.7342886, 5.2290017, 3.8791769, 3.2680695, 5.4278441, 0.6138541, + 5.7054603, 0.6786889, 3.2483864, 0.8994758, 3.5146290, 0.0287746, + 4.8172051, 5.3325973, 5.7605579, 6.2013046, 3.1738449, 1.7053924, + 0.6330341, 3.1909083, 3.6794907, 4.7933610, 0.5212697, 4.1569315, + 3.2482749, 1.0747264, 5.8971330, 3.7101152, 2.7685894, 5.9182512, + 4.1212281, 2.8396586, 5.2759745, 3.3465722, 3.4801751, 4.2729777, + 2.3071222, 1.5035072, 3.6374836, 5.4468120, 2.5558538, 0.7075818, + 2.7887656, 1.8861142, 2.5219880, 5.2361777, 2.5360737, 2.4515477, + 2.2647672, 0.8812504, 1.6344462, 0.5454754, 2.6979830, 1.6165554, + 1.8695956, 2.6694641, 0.7490013, 3.1105972, 4.4384875, 1.5304166, + 4.9327408, 0.4655185, 2.4748426, 0.0213259, 1.3865538, 0.0081717, + 1.1886509, 0.8952537, 1.6843712, 1.0988793, 0.8711572, 3.7629093, + 5.6615138, 5.9022971, 1.3897429, 3.0327137, 2.3625475, 3.2910070, + 1.6642436, 0.4295011, 2.7415239, 1.0923508, 0.1640358, 5.9984205, + 2.7055177, 6.0416507, 4.7903915, 0.0461730, 4.2728088, 4.4356194, + 4.0534637, 3.4702651, 1.3704176, 4.8529200, 1.4327442, 2.3302118, + 5.5978709, 5.3807748, 2.5285646, 1.9981730, 3.8241692, 5.7189253, + 5.7120324, 3.7170973, 2.0896078, 5.3599569, 2.7796679, 5.6822331, + 0.2084724, 3.3453343, 4.5018856, 1.1265867, 2.1144987, 1.1794352, + 2.0227281, 2.5375066, 3.4467437, 0.3062336, 3.4729184, 1.7266910, + 1.5174002, 1.5277262, 0.9686124, 6.0093412, 5.8789338, 5.1441345, + 4.5758041, 1.1046577, 2.2642776, 1.1862024, 0.0075297, 1.9881224, + 4.3958232, 3.9285942, 3.4121603, 2.7585521, 1.8059588, 3.1520171, + 4.7849358, 4.7903511, 3.6194660, 4.6977042, 4.0560129, 0.7742111, + 3.1692252, 2.1819072, 0.5789810, 0.9289656, 1.2451370, 4.2239985, + 2.7112647, 4.3630684, 1.6134250, 0.0613154, 3.3444332, 1.7554715, + 5.9453394, 5.6953510, 2.4673100, 0.1561700, 4.2187618, 5.2600982, + 6.1041123, 0.3577199, 2.8294680, 3.6597688, 4.3142726, 4.5203293, + 4.0843265, 4.5673388, 2.3489542, 3.6541880, 0.7295941, 0.3622530, + 6.1560465, 1.7896003, 3.7383338, 6.0454361, 1.1672793, 1.2129049, + 2.1466132, 5.8615704, 2.4546365, 1.7166712, 0.9547117, 2.4951084, + 2.3544507, 0.8238180, 2.7334414, 0.5749942, 3.8618151, 0.0689837, + 3.6019012, 4.9620190, 1.4788531, 2.8149909, 3.5773830, 0.3857966, + 3.1182750, 4.0357856, 1.3902536, 5.2593808, 6.1014456, 5.3179177, + 3.1792883, 1.7522271, 4.6911344, 1.4886775, 6.0151778, 3.8972087, + 3.7715583, 1.0845061, 0.5676653, 1.6038597, 5.3945577, 5.7244031, + 4.3959286, 4.5564551, 1.4444168, 3.6194506, 5.0933266, 2.5374227, + 6.2105471, 0.5654792, 2.0165320, 3.2132771, 0.3808010, 4.5596317, + 3.4969429, 3.3260664, 5.2149334, 5.3957421, 4.9576149, 1.9970040, + 2.8413032, 4.7263877, 0.6902815, 0.6895316, 1.6957291, 3.2963937, + 6.1113470, 4.4636294, 1.9594738, 1.8312791, 5.3429527, 5.7280497, + 4.0166905, 1.6045389, 0.5571039, 5.2669152, 3.6738954, 5.9571429, + 0.3834561, 3.6734096, 1.7913869, 5.2007946, 1.2000032, 2.7804978, + 2.4718774, 5.1935175, 4.2529065, 1.3044083, 1.9987109, 0.8407592, + 4.2189258, 3.5876427, 1.0666779, 0.9277486, 2.9912971, 5.7057758, + 3.4694180, 0.2069675, 0.3384307, 5.0583614, 2.8360719, 2.4042372, + 4.9614777, 2.2888819, 3.3448533, 4.4714710, 5.4756485, 2.0652177, + 4.0848120, 6.1250762, 0.4773170, 3.6883502, 2.6005256, 1.9423615, + 1.6577182, 4.7674690, 6.2531264, 1.1722630, 4.9080805, 1.2302350, + 6.2351753, 5.0407581, 2.6654950, 4.5795867, 3.1312479, 5.0830358, + 2.2400117, 0.4602021, 3.7133088, 5.7188788, 1.2174673, 2.7166470, + 4.7071094, 0.2462034, 5.9459353, 4.7983010, 3.5111731, 1.1551193, + 3.1287047, 3.2537199, 6.2470131, 5.3711915, 6.0469623, 4.2659122, + 2.5352740, 5.8746469, 3.0126903, 1.4563896, 2.4899651, 4.4301324, + 3.5095299, 4.7540509, 6.2547920, 6.0471349, 3.3619258, 6.0561746, + 0.7264988, 0.3232592, 1.9122808, 3.6454528, 3.3361480, 5.6624574, + 3.3963785, 2.7142142, 3.4096772, 4.4762342, 0.1047703, 5.0323343, + 0.8954125, 3.0063438, 1.6137441, 2.3190715, 4.1579916, 1.0656836, + 1.7516517, 1.2454643, 1.2256706, 2.0535941, 5.5313259, 2.9600203, + 2.5382144, 1.1261446, 6.0879353, 2.5601199, 5.3060708, 3.8662016, + 2.3663172, 5.5114955, 4.9313732, 2.9213939, 5.1143679, 5.6450910, + 2.6969853, 2.1006537, 3.7488443, 5.6673754, 4.4112136, 2.3716204, + 4.6178643, 5.9948046, 3.4105954, 3.3935850, 1.9547595, 0.4475800, + 1.1434170, 0.5842667, 2.9121888, 0.0586379, 5.7492774, 4.0384655, + 0.0089162, 0.1909163, 1.3098570, 2.8586366, 0.7996361, 0.0543350, + 4.5683759, 2.2249794, 4.9036865, 2.7435946, 2.7429546, 0.3092155, + 0.3118464, 0.5723993, 3.7324447, 1.5147758, 5.2864780, 5.3860266, + 6.0545540, 3.0718480, 1.3842492, 1.4213108, 3.3727372, 4.7884765, + 2.1838288, 2.8980046, 4.0169897, 5.7637923, 1.0151904, 4.4964699, + 3.6300404, 2.7224978, 5.5558613, 2.4696170, 1.1245340, 3.9793522, + 3.9207111, 2.0605178, 5.0451799, 6.2799046, 6.1636676, 0.7981966, + 1.4592079, 0.1484872, 3.8166117, 0.6962355, 2.5601436, 5.5548184, + 3.4440198, 2.3185147, 1.3090764, 2.7705283, 6.0079576, 0.7792778, + 2.9578927, 5.3840384, 0.2726304, 4.3456090, 6.1511471, 1.7798247, + 0.8405677, 4.3057392, 5.7142715, 3.8382030, 5.6547587, 1.2153801, + 4.7401894, 2.1756202, 2.6303011, 0.9784166, 5.1459324, 3.9265103, + 4.6405120, 5.0586705, 0.4223724, 5.9739917, 3.1263686, 4.7447217, + 4.6646686, 5.2221411, 0.9833301, 2.8733554, 3.8836400, 5.8570808, + -5.2470141, 5.6261119, 3.6600718, 3.6615062, 5.3716581, 0.2190677, + -5.5632585, 2.5618482, 0.2285950, 4.6881858, 0.9728179, 0.9042027, + -3.8073530, 1.5989503, 2.0367209, 2.5245268, 2.5533189, 2.4265105, + -3.8314979, 1.0486053, 1.1818174, 0.5945707, 2.0306392, 4.8355201, + -1.4710068, 4.6518534, 4.3531065, 5.1778361, 5.2023364, 1.8432851, + -1.9438243, 3.2862931, 2.0439139, 5.2266206, 5.0912323, 3.4997233, + -1.6522518, 4.2761236, 1.4680860, 2.8678051, 2.4163051, 3.3841326, + -6.2310582, 4.7451897, 6.1603795, 1.4751828, 3.3210347, 0.3231823, + -4.7555888, 3.7823504, 5.3857498, 6.2095284, 5.8401232, 2.5730582, + -0.0021455, 3.3984387, 1.3052100, 1.3777994, 2.0471011, 0.6028680, + -4.6968925, 4.7030205, 3.4136510, 2.1245480, 5.2297066, 3.4719134, + -6.0164208, 5.6098372, 2.2399783, 3.4331443, 2.1782657, 3.9131853, + -5.0053405, 4.6864702, 0.7887674, 5.1672539, 0.1580253, 2.6039335, + -4.5955687, 4.9095176, 2.3077255, 4.6801428, 5.6062801, 1.5243220, + -0.8142818, 1.4141432, 2.1992023, 1.8038058, 5.8275790, 0.3224138, + -3.7238350, 1.0235240, 5.2678588, 1.0528164, 3.1554195, 6.2789723, + -2.2330890, 0.2957980, 1.3424690, 2.4996969, 2.0964990, 1.4426353, + -5.8818165, 4.2926017, 6.0451393, 2.7518666, 5.9083095, 0.0366581, + -3.8346722, 5.0333074, 1.4638661, 5.8588735, 4.7957215, 5.1927356, + -3.6031780, 4.9799375, 2.0674268, 1.4040530, 1.9627813, 3.6726693, + -5.2145043, 1.8250297, 2.5293238, 5.4164658, 3.8625225, 6.2278165, + -1.2798778, 5.1975080, 4.2465638, 1.5641957, 2.9894493, 2.5074636, + -3.7663816, 5.0298329, 0.6601666, 5.1612735, 5.2847013, 2.2274284, + -2.7022061, 3.5954850, 4.4034117, 4.6650751, 4.7619266, 2.4449681, + -2.6973871, 6.0088907, 3.6000853, 5.3389611 +}; diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.c new file mode 100644 index 0000000..3157d1c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.c @@ -0,0 +1,244 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +#define BIQUAD_DEFINE_TEST(suffix, instance_name, config_suffix, output_type) \ + JTEST_DEFINE_TEST(arm_biquad_cascade_##config_suffix##_##suffix##_test, \ + arm_biquad_cascade_##config_suffix##_##suffix) \ + { \ + instance_name biquad_inst_fut = { 0 }; \ + instance_name biquad_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numstages_idx, uint16_t, numStages, filtering_numstages \ + , \ + /* Initialize the BIQUAD Instances */ \ + arm_biquad_cascade_##config_suffix##_init_##suffix( \ + &biquad_inst_fut, numStages, \ + (output_type*)filtering_coeffs_b_##suffix, \ + (void *) filtering_pState); \ + \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Stages: %d\n", \ + (int)blockSize, \ + (int)numStages); \ + \ + JTEST_COUNT_CYCLES( \ + arm_biquad_cascade_##config_suffix##_##suffix( \ + &biquad_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_biquad_cascade_##config_suffix##_init_##suffix( \ + &biquad_inst_ref, numStages, \ + (output_type*)filtering_coeffs_b_##suffix, \ + (void *) filtering_pState); \ + \ + ref_biquad_cascade_##config_suffix##_##suffix( \ + &biquad_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(suffix, config_suffix, speed, output_type) \ + JTEST_DEFINE_TEST(arm_biquad_cascade_##config_suffix##speed##_##suffix##_test, \ + arm_biquad_cascade_##config_suffix##speed##_##suffix) \ + { \ + arm_biquad_casd_##config_suffix##_inst_##suffix biquad_inst_fut = { 0 }; \ + arm_biquad_casd_##config_suffix##_inst_##suffix biquad_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numstages_idx, uint16_t, numStages, filtering_numstages \ + , \ + TEMPLATE_DO_ARR_DESC( \ + postshifts_idx, uint8_t, postShift, filtering_postshifts \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Stages: %d\n" \ + "Post Shift: %d\n", \ + (int)blockSize, \ + (int)numStages, \ + (int)postShift); \ + \ + /* Initialize the BIQUAD Instances */ \ + arm_biquad_cascade_##config_suffix##_init_##suffix( \ + &biquad_inst_fut, numStages, \ + (output_type*)filtering_coeffs_b_##suffix, \ + (void *) filtering_pState, postShift); \ + \ + JTEST_COUNT_CYCLES( \ + arm_biquad_cascade_##config_suffix##speed##_##suffix( \ + &biquad_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_biquad_cascade_##config_suffix##_init_##suffix( \ + &biquad_inst_ref, numStages, \ + (output_type*)filtering_coeffs_b_##suffix, \ + (void *) filtering_pState, postShift); \ + \ + ref_biquad_cascade_##config_suffix##speed##_##suffix( \ + &biquad_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type)))); \ + \ + return JTEST_TEST_PASSED; \ + } + + +JTEST_DEFINE_TEST(arm_biquad_cas_df1_32x64_q31_test, + arm_biquad_cas_df1_32x64_q31) +{ + arm_biquad_cas_df1_32x64_ins_q31 biquad_inst_fut = { 0 }; + arm_biquad_cas_df1_32x64_ins_q31 biquad_inst_ref = { 0 }; + + TEMPLATE_DO_ARR_DESC( + blocksize_idx, uint32_t, blockSize, filtering_blocksizes + , + TEMPLATE_DO_ARR_DESC( + numstages_idx, uint16_t, numStages, filtering_numstages + , + TEMPLATE_DO_ARR_DESC( + postshifts_idx, uint8_t, postShift, filtering_postshifts + , + /* Initialize the BIQUAD Instances */ + arm_biquad_cas_df1_32x64_init_q31( + &biquad_inst_fut, numStages, + (q31_t*)filtering_coeffs_b_q31, + (void *) filtering_pState, postShift); + + /* Display test parameter values */ + JTEST_DUMP_STRF("Block Size: %d\n" + "Number of Stages: %d\n", + (int)blockSize, + (int)numStages); + + JTEST_COUNT_CYCLES( + arm_biquad_cas_df1_32x64_q31( + &biquad_inst_fut, + (void *) filtering_q31_inputs, + (void *) filtering_output_fut, + blockSize)); + + arm_biquad_cas_df1_32x64_init_q31( + &biquad_inst_ref, numStages, + (q31_t*)filtering_coeffs_b_q31, + (void *) filtering_pState, postShift); + + ref_biquad_cas_df1_32x64_q31( + &biquad_inst_ref, + (void *) filtering_q31_inputs, + (void *) filtering_output_ref, + blockSize); + + FILTERING_SNR_COMPARE_INTERFACE( + blockSize, + q31_t)))); + + return JTEST_TEST_PASSED; +} + +JTEST_DEFINE_TEST(arm_biquad_cascade_df2T_f64_test, + arm_biquad_cascade_df2T_f64) +{ + arm_biquad_cascade_df2T_instance_f64 biquad_inst_fut = { 0 }; + arm_biquad_cascade_df2T_instance_f64 biquad_inst_ref = { 0 }; + + TEMPLATE_DO_ARR_DESC( + blocksize_idx, uint32_t, blockSize, filtering_blocksizes + , + TEMPLATE_DO_ARR_DESC( + numstages_idx, uint16_t, numStages, filtering_numstages + , + /* Display test parameter values */ + JTEST_DUMP_STRF("Block Size: %d\n" + "Number of Stages: %d\n", + (int)blockSize, + (int)numStages); + + /* Initialize the BIQUAD Instances */ + arm_biquad_cascade_df2T_init_f64( + &biquad_inst_fut, numStages, + (float64_t*)filtering_coeffs_b_f64, + (void *) filtering_pState); + + JTEST_COUNT_CYCLES( + arm_biquad_cascade_df2T_f64( + &biquad_inst_fut, + (void *) filtering_f64_inputs, + (void *) filtering_output_fut, + blockSize)); + + arm_biquad_cascade_df2T_init_f64( + &biquad_inst_ref, numStages, + (float64_t*)filtering_coeffs_b_f64, + (void *) filtering_pState); + + ref_biquad_cascade_df2T_f64( + &biquad_inst_ref, + (void *) filtering_f64_inputs, + (void *) filtering_output_ref, + blockSize); + + FILTERING_DBL_SNR_COMPARE_INTERFACE( + blockSize, + float64_t))); + + return JTEST_TEST_PASSED; +} + + +BIQUAD_DEFINE_TEST(f32,arm_biquad_casd_df1_inst_f32, df1,float32_t); +BIQUAD_DEFINE_TEST(f32,arm_biquad_cascade_df2T_instance_f32,df2T,float32_t); +BIQUAD_DEFINE_TEST(f32,arm_biquad_cascade_stereo_df2T_instance_f32,stereo_df2T,float32_t); +BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q31,df1,,q31_t); +BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q15,df1,,q15_t); +BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q31,df1,_fast,q31_t); +BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q15,df1,_fast,q15_t); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(biquad_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_biquad_cascade_df1_f32_test); + JTEST_TEST_CALL(arm_biquad_cascade_df2T_f32_test); + JTEST_TEST_CALL(arm_biquad_cascade_stereo_df2T_f32_test); + JTEST_TEST_CALL(arm_biquad_cascade_df2T_f64_test); + JTEST_TEST_CALL(arm_biquad_cascade_df1_q31_test); + JTEST_TEST_CALL(arm_biquad_cascade_df1_q15_test); + JTEST_TEST_CALL(arm_biquad_cascade_df1_fast_q31_test); + JTEST_TEST_CALL(arm_biquad_cascade_df1_fast_q15_test); + JTEST_TEST_CALL(arm_biquad_cas_df1_32x64_q31_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c new file mode 100644 index 0000000..c2fdf0f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c @@ -0,0 +1,473 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +/*--------------------------------------------------------------------------------*/ +/* Header Stuff */ +/*--------------------------------------------------------------------------------*/ + +#define CONV_MAX_INPUT_ELTS 32 +#define CONV_MAX_OUTPUT_ELTS (CONV_MAX_INPUT_ELTS * 2) + +#define CONV_TEST_VALID_PARTIAL_PARAMS(input_a_len, input_b_len, \ + first_index, num_points) \ + (((((input_a_len) + (input_b_len) - 1)) >= num_points + first_index ) \ + && (num_points > 0)) + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define CONV_arm_conv_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut) + +#define CONV_ref_conv_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref) + +#define CONV_arm_conv_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_fut, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_ref_conv_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_ref, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_arm_conv_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut) + +#define CONV_ref_conv_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref) + +#define CONV_arm_conv_fast_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_fut, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_ref_conv_fast_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_ref, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_arm_conv_partial_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_fut, first_index, num_points) + +#define CONV_ref_conv_partial_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_ref, first_index, num_points) + +#define CONV_arm_conv_partial_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_fut, first_index, num_points) + +#define CONV_ref_conv_partial_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_ref, first_index, num_points) + +#define CONV_arm_conv_partial_opt_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_fut, first_index, num_points, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_ref_conv_partial_opt_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_ref, first_index, num_points, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_arm_conv_partial_fast_opt_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_fut, first_index, num_points, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CONV_ref_conv_partial_fast_opt_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len, \ + first_index, num_points) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*)filtering_output_ref, first_index, num_points, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +/*--------------------------------------------------------------------------------*/ +/* Convolution Inputs */ +/*--------------------------------------------------------------------------------*/ + +/* The following symbols alias the filtering_q31_inputs array: + * + * - filtering_q15_inputs + * - filtering_q7_inputs + * + * The aliasing conflicts with the instantiation of #ARR_DESC_t structs. + * + * These macro-level aliases allow the #CONV_DEFINE_RAND_INPUT_ARR_DESCS() macro + * to correctly select the filtering_q31_input or filtering_f32_input array, + * within a template, by type_suffix. + * + */ +#define CONV_f32_INPUTS filtering_f32_inputs +#define CONV_q31_INPUTS filtering_q31_inputs +#define CONV_q15_INPUTS filtering_q31_inputs +#define CONV_q7_INPUTS filtering_q31_inputs + +/** + * Defines #ARR_DESC_t objects that wrap existing, type-specific, common + * inputs. + */ +#define CONV_DEFINE_RAND_INPUT_ARR_DESCS(type_suffix) \ + ARR_DESC_DEFINE_USING_ARR( \ + TYPE_FROM_ABBREV(type_suffix), \ + conv_input_rand1_##type_suffix, \ + CONV_##type_suffix##_INPUTS, \ + 0, \ + CONV_MAX_INPUT_ELTS); \ + \ + ARR_DESC_DEFINE_USING_ARR( \ + TYPE_FROM_ABBREV(type_suffix), \ + conv_input_rand2_##type_suffix, \ + CONV_##type_suffix##_INPUTS, \ + 1, \ + CONV_MAX_INPUT_ELTS) /* Note the lacking semicolon */ + +CONV_DEFINE_RAND_INPUT_ARR_DESCS(f32); +CONV_DEFINE_RAND_INPUT_ARR_DESCS(q31); +CONV_DEFINE_RAND_INPUT_ARR_DESCS(q15); +CONV_DEFINE_RAND_INPUT_ARR_DESCS(q7); +ARR_DESC_DEFINE(float32_t, conv_input_zeros, CONV_MAX_INPUT_ELTS, CURLY(0)); + +/** + * Define Input #ARR_DESC_t arrays by type suffix. + * + * Taking inputs in parallel from the 'a' and 'b' arrays yields the following + * test cases (star is convolution): + * + * - zero_array * zero_array + * - zero_array * random_array + * - random_array * zero_array + * - random_array * different_random_arary + */ +#define CONV_DEFINE_ALL_INPUTS(type_suffix) \ + ARR_DESC_DEFINE(ARR_DESC_t *, \ + conv_##type_suffix##_a_inputs, \ + 4, \ + CURLY( \ + &conv_input_zeros, \ + &conv_input_zeros, \ + &conv_input_rand1_##type_suffix, \ + &conv_input_rand1_##type_suffix \ + )); \ + ARR_DESC_DEFINE(ARR_DESC_t *, \ + conv_##type_suffix##_b_inputs, \ + 4, \ + CURLY( \ + &conv_input_zeros, \ + &conv_input_rand1_##type_suffix, \ + &conv_input_zeros, \ + &conv_input_rand2_##type_suffix \ + )) /* Note the lacking semicolon */ + +CONV_DEFINE_ALL_INPUTS(f32); +CONV_DEFINE_ALL_INPUTS(q31); +CONV_DEFINE_ALL_INPUTS(q15); +CONV_DEFINE_ALL_INPUTS(q7); + +/*--------------------------------------------------------------------------------*/ +/* Convolution Lengths */ +/*--------------------------------------------------------------------------------*/ + +/* + * The conv_lens_a and conv_lens_b #ARR_DESC_t objects are accessed in parallel + * to provide convolution-length pairs. Taken in parallel they provide the + * following cases: + * + * - 1 * 1 : Shortest convolution possible. + * - 1 * 2 : Short convolution , one side is degenerate . + * - 17 * 1 : Medium convolution , one side is degenerate . + * - 15 * MAX : Longest convolution , one side is degenerate . + * MAX * MAX : Longest convolution. + */ +ARR_DESC_DEFINE(uint32_t, + conv_lens_a, + 5, + CURLY( + 1, + 1, + 17, + 15, + CONV_MAX_INPUT_ELTS + )); + +ARR_DESC_DEFINE(uint32_t, + conv_lens_b, + 5, + CURLY( + 1, + 2, + 1, + CONV_MAX_INPUT_ELTS, + CONV_MAX_INPUT_ELTS + )); + +/*--------------------------------------------------------------------------------*/ +/* Partial Indexing */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(uint32_t, + first_index_arr_desc, + 4, + CURLY( + 0, + 1, + CONV_MAX_INPUT_ELTS / 2, + CONV_MAX_INPUT_ELTS + )); + +ARR_DESC_DEFINE(uint32_t, + num_points_arr_desc, + 3, + CURLY( + 1, + CONV_MAX_OUTPUT_ELTS / 2, + CONV_MAX_OUTPUT_ELTS + )); + +/*--------------------------------------------------------------------------------*/ +/* Convolution Tests */ +/*--------------------------------------------------------------------------------*/ + +#define CONV_TEST_TEMPLATE(fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + suffix, output_type) \ + JTEST_DEFINE_TEST(fut##_tests, fut) \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, conv_##suffix##_a_inputs \ + , \ + void * input_a_ptr = input_ptr->data_ptr; \ + void * input_b_ptr = ARR_DESC_ELT( \ + ARR_DESC_t *, input_idx, \ + &(conv_##suffix##_b_inputs))->data_ptr; \ + \ + TEMPLATE_DO_ARR_DESC( \ + conv_len_idx, uint32_t, conv_len_a, conv_lens_a \ + , \ + uint32_t conv_len_b = ARR_DESC_ELT( \ + uint32_t, conv_len_idx, &(conv_lens_b)); \ + \ + JTEST_DUMP_STRF("Input A Length: %d\n" \ + "Input B Length: %d\n", \ + (int)conv_len_a, \ + (int)conv_len_b); \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_a_ptr, conv_len_a, input_b_ptr, conv_len_b), \ + ref, ref_arg_interface( \ + input_a_ptr, conv_len_a, input_b_ptr, conv_len_b)); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + conv_len_a + conv_len_b - 1, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } \ + \ + +#define CONV_PARTIAL_TEST_TEMPLATE(fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + suffix, output_type) \ + JTEST_DEFINE_TEST(fut##_tests, fut) \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, conv_##suffix##_a_inputs \ + , \ + void * input_a_ptr = input_ptr->data_ptr; \ + void * input_b_ptr = ARR_DESC_ELT( \ + ARR_DESC_t *, input_idx, \ + &(conv_##suffix##_b_inputs))->data_ptr; \ + TEMPLATE_DO_ARR_DESC( \ + conv_len_idx, uint32_t, conv_len_a, conv_lens_a \ + , \ + uint32_t conv_len_b = ARR_DESC_ELT( \ + uint32_t, conv_len_idx, &(conv_lens_b)); \ + \ + TEMPLATE_DO_ARR_DESC( \ + first_index_idx, uint32_t, first_index, \ + first_index_arr_desc \ + , \ + TEMPLATE_DO_ARR_DESC( \ + num_points_idx, uint32_t, num_points, \ + num_points_arr_desc \ + , \ + if (CONV_TEST_VALID_PARTIAL_PARAMS( \ + conv_len_a, conv_len_b, \ + first_index, num_points)) \ + { \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Input A Length: %d\n" \ + "Input B Length: %d\n" \ + "First Sample Index: %d\n" \ + "Number of Output Points: %d\n", \ + (int)conv_len_a, \ + (int)conv_len_b, \ + (int)first_index, \ + (int)num_points); \ + \ + memset(filtering_output_ref,0, \ + (2*CONV_MAX_INPUT_ELTS)*sizeof(output_type)); \ + memset(filtering_output_fut,0, \ + (2*CONV_MAX_INPUT_ELTS)*sizeof(output_type)); \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_a_ptr, conv_len_a, \ + input_b_ptr, conv_len_b, \ + first_index, num_points), \ + ref, ref_arg_interface( \ + input_a_ptr, conv_len_a, \ + input_b_ptr, conv_len_b, \ + first_index, num_points)); \ + \ + FILTERING_SNR_COMPARE_INTERFACE_OFFSET( \ + first_index, \ + num_points, \ + output_type); \ + } else { \ + /* FUT should return ARM_MATH_ARGUMENT_ERROR*/ \ + /* if first_index and num_points don't make */ \ + /* sense*/ \ + \ + arm_status conv_test_retval; \ + TEST_CALL_FUT( \ + conv_test_retval = fut, \ + fut_arg_interface( \ + input_a_ptr, conv_len_a, \ + input_b_ptr, conv_len_b, \ + first_index, num_points)); \ + \ + if (conv_test_retval != ARM_MATH_ARGUMENT_ERROR) { \ + JTEST_DUMP_STR("FUT failed to raise error."); \ + /* return JTEST_TEST_FAILED; */ \ + } \ + })))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define CONV_DEFINE_TEST(fn_name, suffix, output_type, test_template) \ + test_template( \ + arm_##fn_name##_##suffix, \ + CONV_arm_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + CONV_ref_##fn_name##_INPUT_INTERFACE, \ + suffix, \ + output_type \ + ) /* Note the lacking semicolon*/ + +/* Tests on functions without partial outputs */ +CONV_DEFINE_TEST(conv , f32, float32_t, CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv , q31, q31_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv , q15, q15_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv , q7 , q7_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_opt , q15, q15_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_opt , q7 , q7_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_fast , q31, q31_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_fast , q15, q15_t , CONV_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_fast_opt , q15, q15_t , CONV_TEST_TEMPLATE); + +/* Tests on functions with partial outputs */ +CONV_DEFINE_TEST(conv_partial , f32, float32_t, CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial , q31, q31_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial , q7 , q7_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial_fast , q31, q31_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial_fast , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial_fast_opt , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial_opt , q15, q15_t , CONV_PARTIAL_TEST_TEMPLATE); +CONV_DEFINE_TEST(conv_partial_opt , q7 , q7_t , CONV_PARTIAL_TEST_TEMPLATE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(conv_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_conv_f32_tests); + JTEST_TEST_CALL(arm_conv_q31_tests); + JTEST_TEST_CALL(arm_conv_q15_tests); + JTEST_TEST_CALL(arm_conv_q7_tests); + + JTEST_TEST_CALL(arm_conv_opt_q15_tests); + JTEST_TEST_CALL(arm_conv_opt_q7_tests); + + JTEST_TEST_CALL(arm_conv_fast_q31_tests); + JTEST_TEST_CALL(arm_conv_fast_q15_tests); + + JTEST_TEST_CALL(arm_conv_fast_opt_q15_tests); + + JTEST_TEST_CALL(arm_conv_partial_f32_tests); + JTEST_TEST_CALL(arm_conv_partial_q31_tests); + JTEST_TEST_CALL(arm_conv_partial_q15_tests); + JTEST_TEST_CALL(arm_conv_partial_q7_tests); + + JTEST_TEST_CALL(arm_conv_partial_fast_q31_tests); + JTEST_TEST_CALL(arm_conv_partial_fast_q15_tests); + + JTEST_TEST_CALL(arm_conv_partial_fast_opt_q15_tests); + + JTEST_TEST_CALL(arm_conv_partial_opt_q15_tests); + JTEST_TEST_CALL(arm_conv_partial_opt_q7_tests); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c new file mode 100644 index 0000000..689b075 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c @@ -0,0 +1,310 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +/*--------------------------------------------------------------------------------*/ +/* Header Stuff */ +/*--------------------------------------------------------------------------------*/ + +#define CORRELATE_MAX_INPUT_ELTS 32 +#define CORRELATE_MAX_OUTPUT_ELTS (CORRELATE_MAX_INPUT_ELTS * 2) + +/*--------------------------------------------------------------------------------*/ +/* Input Interfaces */ +/*--------------------------------------------------------------------------------*/ +/* + * General: + * Input interfaces provide inputs to functions inside test templates. They + * ONLY provide the inputs. The output variables should be hard coded. + * + * The input interfaces must have the following format: + * + * ARM_xxx_INPUT_INTERFACE() or + * REF_xxx_INPUT_INTERFACE() + * + * The xxx must be lowercase, and is intended to be the indentifying substring + * in the function's name. Acceptable values are 'sub' or 'add' from the + * functions arm_add_q31. + */ + +#define CORRELATE_arm_correlate_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut) + +#define CORRELATE_ref_correlate_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref) + +#define CORRELATE_arm_correlate_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_fut, \ + (void*) filtering_scratch) + +#define CORRELATE_arm_correlate_opt_q7_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_fut, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CORRELATE_ref_correlate_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_ref, \ + (void*) filtering_scratch) + +#define CORRELATE_ref_correlate_opt_q7_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_ref, \ + (void*) filtering_scratch, \ + (void*) filtering_scratch2) + +#define CORRELATE_arm_correlate_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut) + +#define CORRELATE_ref_correlate_fast_INPUT_INTERFACE(input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref) + +#define CORRELATE_arm_correlate_fast_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_fut, \ + (void*) filtering_scratch) + +#define CORRELATE_ref_correlate_fast_opt_INPUT_INTERFACE( \ + input_a, input_a_len, \ + input_b, input_b_len) \ + PAREN(input_a, input_a_len, input_b, input_b_len, \ + (void*) filtering_output_ref, \ + (void*) filtering_scratch) + +/*--------------------------------------------------------------------------------*/ +/* Convolution Inputs */ +/*--------------------------------------------------------------------------------*/ + +/* The following symbols alias the filtering_q31_inputs array: + * + * - filtering_q15_inputs + * - filtering_q7_inputs + * + * The aliasing conflicts with the instantiation of #ARR_DESC_t structs. + * + * These macro-level aliases allow the #CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS() macro + * to correctly select the filtering_q31_input or filtering_f32_input array, + * within a template, by type_suffix. + * + */ +#define CORRELATE_f32_INPUTS filtering_f32_inputs +#define CORRELATE_q31_INPUTS filtering_q31_inputs +#define CORRELATE_q15_INPUTS filtering_q31_inputs +#define CORRELATE_q7_INPUTS filtering_q31_inputs + +/** + * Defines #ARR_DESC_t objects that wrap existing, type-specific, common + * inputs. + */ +#define CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(type_suffix) \ + ARR_DESC_DEFINE_USING_ARR( \ + TYPE_FROM_ABBREV(type_suffix), \ + correlate_input_rand1_##type_suffix, \ + CORRELATE_##type_suffix##_INPUTS, \ + 0, \ + CORRELATE_MAX_INPUT_ELTS); \ + \ + ARR_DESC_DEFINE_USING_ARR( \ + TYPE_FROM_ABBREV(type_suffix), \ + correlate_input_rand2_##type_suffix, \ + CORRELATE_##type_suffix##_INPUTS, \ + 1, \ + CORRELATE_MAX_INPUT_ELTS) /* Note the lacking semicolon */ + +CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(f32); +CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q31); +CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q15); +CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q7); +ARR_DESC_DEFINE(float32_t, correlate_input_zeros, CORRELATE_MAX_INPUT_ELTS, CURLY(0)); + +/** + * Define Input #ARR_DESC_t arrays by type suffix. + * + * Taking inputs in parallel from the 'a' and 'b' arrays yields the following + * test cases (star is correlate): + * + * - zero_array * zero_array + * - zero_array * random_array + * - random_array * zero_array + * - random_array * different_random_arary + */ +#define CORRELATE_DEFINE_ALL_INPUTS(type_suffix) \ + ARR_DESC_DEFINE(ARR_DESC_t *, \ + correlate_##type_suffix##_a_inputs, \ + 4, \ + CURLY( \ + &correlate_input_zeros, \ + &correlate_input_zeros, \ + &correlate_input_rand1_##type_suffix, \ + &correlate_input_rand1_##type_suffix \ + )); \ + ARR_DESC_DEFINE(ARR_DESC_t *, \ + correlate_##type_suffix##_b_inputs, \ + 4, \ + CURLY( \ + &correlate_input_zeros, \ + &correlate_input_rand1_##type_suffix, \ + &correlate_input_zeros, \ + &correlate_input_rand2_##type_suffix \ + )) /* Note the lacking semicolon */ + +CORRELATE_DEFINE_ALL_INPUTS(f32); +CORRELATE_DEFINE_ALL_INPUTS(q31); +CORRELATE_DEFINE_ALL_INPUTS(q15); +CORRELATE_DEFINE_ALL_INPUTS(q7); + +/*--------------------------------------------------------------------------------*/ +/* Convolution Lengths */ +/*--------------------------------------------------------------------------------*/ + +/* + * The correlate_lens_a and correlate_lens_b #ARR_DESC_t objects are accessed in parallel + * to provide correlate-length pairs. Taken in parallel they provide the + * following cases: + * + * - 1 * 1 : Shortest correlate possible. + * - 1 * 2 : Short correlate , one side is degenerate. + * - 17 * 1 : Medium correlate, one side is degenerate. + * - 15 * MAX : Longest correlate. + * MAX * MAX : Longest correlate. + */ +ARR_DESC_DEFINE(uint32_t, + correlate_lens_a, + 5, + CURLY( + 1, + 1, + 17, + 15, + CORRELATE_MAX_INPUT_ELTS + )); + +ARR_DESC_DEFINE(uint32_t, + correlate_lens_b, + 5, + CURLY( + 1, + 2, + 1, + CORRELATE_MAX_INPUT_ELTS, + CORRELATE_MAX_INPUT_ELTS + )); + +/*--------------------------------------------------------------------------------*/ +/* Convolution Tests */ +/*--------------------------------------------------------------------------------*/ + +#define CORRELATE_TEST_TEMPLATE(fut, fut_arg_interface, \ + ref, ref_arg_interface, \ + suffix, output_type) \ + JTEST_DEFINE_TEST(fut##_tests, fut) \ + { \ + TEMPLATE_DO_ARR_DESC( \ + input_idx, ARR_DESC_t *, input_ptr, correlate_##suffix##_a_inputs \ + , \ + void * input_a_ptr = input_ptr->data_ptr; \ + void * input_b_ptr = ARR_DESC_ELT( \ + ARR_DESC_t *, input_idx, \ + &(correlate_##suffix##_b_inputs))->data_ptr; \ + \ + TEMPLATE_DO_ARR_DESC( \ + correlate_len_idx, uint32_t, correlate_len_a, correlate_lens_a \ + , \ + uint32_t correlate_len_b = ARR_DESC_ELT( \ + uint32_t, correlate_len_idx, &(correlate_lens_b)); \ + \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Input A Length: %d\n" \ + "Input B Length: %d\n", \ + (int)correlate_len_a, \ + (int)correlate_len_b); \ + \ + memset(filtering_output_ref,0, \ + (2*CORRELATE_MAX_INPUT_ELTS)*sizeof(output_type)); \ + memset(filtering_output_fut,0, \ + (2*CORRELATE_MAX_INPUT_ELTS)*sizeof(output_type)); \ + \ + TEST_CALL_FUT_AND_REF( \ + fut, fut_arg_interface( \ + input_a_ptr, correlate_len_a, input_b_ptr, correlate_len_b), \ + ref, ref_arg_interface( \ + input_a_ptr, correlate_len_a, input_b_ptr, correlate_len_b)); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + correlate_len_a + correlate_len_b - 2, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define CORRELATE_DEFINE_TEST(fn_name, suffix, output_type, test_template) \ + test_template( \ + arm_##fn_name##_##suffix, \ + CORRELATE_arm_##fn_name##_INPUT_INTERFACE, \ + ref_##fn_name##_##suffix, \ + CORRELATE_ref_##fn_name##_INPUT_INTERFACE, \ + suffix, \ + output_type \ + ) /* Note the lacking semicolon*/ + +/* Tests on functions without partial outputs */ +CORRELATE_DEFINE_TEST(correlate , f32, float32_t, CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate , q31, q31_t , CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate , q15, q15_t , CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate , q7 , q7_t , CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate_opt , q15, q15_t , CORRELATE_TEST_TEMPLATE); + +CORRELATE_TEST_TEMPLATE( + arm_correlate_opt_q7, + CORRELATE_arm_correlate_opt_q7_INPUT_INTERFACE, + ref_correlate_opt_q7, + CORRELATE_ref_correlate_opt_q7_INPUT_INTERFACE, + q7, + q7_t + ); + +CORRELATE_DEFINE_TEST(correlate_fast , q31, q31_t , CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate_fast , q15, q15_t , CORRELATE_TEST_TEMPLATE); +CORRELATE_DEFINE_TEST(correlate_fast_opt , q15, q15_t , CORRELATE_TEST_TEMPLATE); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(correlate_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_correlate_f32_tests); + JTEST_TEST_CALL(arm_correlate_q31_tests); + JTEST_TEST_CALL(arm_correlate_q15_tests); + JTEST_TEST_CALL(arm_correlate_q7_tests); + + JTEST_TEST_CALL(arm_correlate_opt_q15_tests); + JTEST_TEST_CALL(arm_correlate_opt_q7_tests); + + JTEST_TEST_CALL(arm_correlate_fast_q31_tests); + JTEST_TEST_CALL(arm_correlate_fast_q15_tests); + + JTEST_TEST_CALL(arm_correlate_fast_opt_q15_tests); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c new file mode 100644 index 0000000..3bd1afb --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c @@ -0,0 +1,757 @@ +#include "filtering_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +//must be max(LMS_MAX_BLOCKSIZE*2, FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_L) +float32_t filtering_output_fut[LMS_MAX_BLOCKSIZE*2] = {0}; +float32_t filtering_output_ref[LMS_MAX_BLOCKSIZE*2] = {0}; +float32_t filtering_output_f32_fut[LMS_MAX_BLOCKSIZE*2] = {0}; +float32_t filtering_output_f32_ref[LMS_MAX_BLOCKSIZE*2] = {0}; +float32_t filtering_input_lms[LMS_MAX_BLOCKSIZE*2] = {0}; +float32_t filtering_pState[LMS_MAX_BLOCKSIZE + FILTERING_MAX_NUMTAPS] = {0}; +float32_t filtering_scratch[FILTERING_MAX_BLOCKSIZE * 3] = {0}; +float32_t filtering_scratch2[FILTERING_MAX_BLOCKSIZE * 3] = {0}; +float32_t filtering_coeffs_lms[FILTERING_MAX_NUMTAPS]; + +const q31_t filtering_q31_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS] = +{ + 0xC14A5524, 0xCCABDA17, 0xAD6F5B56, 0xFDAFCE3B, 0xA9B226EB, + 0x41F6F6A, 0xA5CE38BF, 0x3A978AFA, 0xBA44B82A, 0x855C0F8, + 0x3D060524, 0x93D5E570, 0x97D7791D, 0xFFE0C38C, 0x26749841, + 0xC0A6EE54, 0x218EC386, 0x39FF3726, 0x8DC1F7CA, 0x702F2CF5, + 0xC1142FF1, 0xEC1476AB, 0x15F640DD, 0xE62CCE49, 0x3805DE7E, + 0xF70871FE, 0xCF8BD360, 0x8D19A8A0, 0xD764F821, 0xA58558CF, + 0x8C0CE04D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0xB646AE24, + 0x6CE00F5C, 0xE6D48948, 0xB55BD831, 0x3B72950A, 0x9EB69530, + 0x73394127, 0x773FA6F4, 0x9805A980, 0x838DE587, 0x9CF597F4, + 0xA2AD1691, 0xFA81A473, 0x7CDC7D7F, 0x4A5190D0, 0xED895BB9, + 0x8FD60F35, 0x1A21D530, 0xA0EB6DDA, 0xBDE6A516, 0x2501A3E1, + 0x5ED893C8, 0xE1E175B1, 0xACBBB2F3, 0xED350907, 0xDB140D7E, + 0xEEAE272D, 0xBE229841, 0xC18BFB88, 0xA6BB9B80, 0xBCF090E4, + 0x24DB166C, 0xF9AB7E42, 0x62DF28D1, 0xC7004665, 0xE3F56FC6, + 0x419E0C75, 0x46BE9F38, 0x2432B9B2, 0x758D83E0, 0xDCE12926, + 0x3F57CB74, 0x1F4458E2, 0xF1DD639, 0x83A1FB49, 0x173AFC76, + 0x86EF7531, 0x48D32F34, 0x7D3E3063, 0x8F2FB549, 0x5C314C9, + 0x18CBEB6D, 0xA6F8B697, 0x447B9E9C, 0x2E32BA33, 0xD074D715, + 0x81ACD746, 0xE55A4E04, 0x4891860F, 0x1DA3EB4F, 0xE0E6A27F, + 0x20BFDEB4, 0xD0B3A25B, 0x40C10544, 0xC15656C, 0x15405EAE, + 0x9858E3E1, 0xA36A9C4E, 0x88BD21F9, 0xAACF7A68, 0x773665E5, + 0xCEDFDF66, 0x617A9610, 0x524FC968, 0xC2D086CD, 0x5F008079, + 0x24DCA447, 0x6A4F5599, 0xB706CD4A, 0x1DE70608, 0xA33A2EE5, + 0x137E488E, 0x98061B7B, 0x4079D69D, 0xA4A897D5, 0xC4CEC8F5, + 0xD75F7883, 0x22406802, 0xF1AD70BB, 0x9D4ADD79, 0xBCBC7CE4, + 0xB358C0D8, 0x85792E47, 0xA7ADAC05, 0x3D19EEAB, 0x331AC0AF, + 0x33035831, 0x13D93987, 0xFC542094, 0x845F317E, 0xDDC4BF8B, + 0x1379E50C, 0x5C20193F, 0xFDD58298, 0x9D482B82, 0x4A6BE062, + 0xDC8A757B, 0x272917C1, 0x90E1EFBC, 0x355AD882, 0xE6F8EA35, + 0x604555A1, 0x7DFFFBB, 0xF58AE216, 0x9A11B463, 0xD3541BAD, + 0xA1576756, 0x483BED8D, 0x1F05AFCC, 0xCEA63DFB, 0x55B84677, + 0xFB2E04F2, 0x787AF96C, 0x84A12CD3, 0x460A9BD, 0x9DB22DD8, + 0x1A8C7F28, 0x861E452E, 0x932D3F78, 0x7652D852, 0x73357BBA, + 0xEBBB0A58, 0x62536AFA, 0x3F6B65EF, 0x6DC57B58, 0x9EB798CE, + 0xE6B0A740, 0xDFF68B47, 0x3247FB8F, 0xFFF3D302, 0xA9FD3E40, + 0x475A43D1, 0x6FF9528A, 0x2018A09D, 0x47E0F9C9, 0x4CF5F6D3, + 0x2807CE34, 0xDD6FD8ED, 0x234045D1, 0x51CEB5F9, 0x25297896, + 0x6443A0FE, 0x8F4449A9, 0xD4C3E1C6, 0xF01D52F1, 0x4E09C820, + 0xF18F0810, 0xE1548689, 0xF9DE5A1F, 0x5286DC23, 0x48AC3A4B, + 0xEA0C1BE0, 0xA1B785DB, 0x7086465D, 0x1CC10929, 0x1E1D716E, + 0xED231D4C, 0x2049D108, 0xB8FF9971, 0x949CF8D4, 0x441F1E8B, + 0xC3D95372, 0x69C324B4, 0xA10BFDC9, 0xC781DE78, 0x82476137, + 0xE163DDF, 0x390DEEC2, 0xAF68CE5B, 0x8E680ABD, 0x8223A615, + 0x92593380, 0x7B1465FE, 0x865AE957, 0x930F53EB, 0xED772EF7, + 0x10E916B6, 0xE3BCFA68, 0x2ACB80BB, 0xE51C5590, 0x994714B5, + 0xF30984EE, 0x59BBE1B4, 0xB4867DBC, 0xB91C706C, 0xBC16C218, + 0xA8931CD0, 0x129A66AB, 0x13171F4D, 0x62882872, 0x4B167FD4, + 0xE6902F4C, 0xFA794932, 0xD4B152C, 0xB0856EA9, 0x39466D55, + 0x3669E451, 0x8F5B9E8C, 0x877A3C6A, 0x51B956B4, 0x367EAD2A, + 0x9D2C662A, 0x78FB6880, 0x4E6D40B6, 0x4070EFDC, 0x4DF9679C, + 0x20306EDB, 0xE381AAE7, 0xA55DA748, 0x9B8B617B, 0x3E036FAD, + 0x84E4C4A7, 0xD5A3F517, 0x669BA988, 0x98FDDE8C, 0x67BD85CE, + 0x34BBB46C, 0x76994800, 0x85B9D8B6, 0x6DFA2FEF, 0x205DB5C, + 0x9F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB98B61, 0xC323DDAC, + 0x31D424B4, 0xF68C0D7E, 0x162FAF9D, 0x7B2A7A99, 0xF9392693, + 0xC42D12C0, 0x8692A73E, 0xD9A1EE80, 0xDD956856, 0x44E7BDAC, + 0x8D874532, 0x5F5C9DD0, 0x5D167858, 0x8559FEA2, 0x9D821476, + 0xD9654ED2, 0x594C0DC7, 0x1A87B506, 0x3F693200, 0x7A651AB5, + 0xA0CCBC8A, 0x9F9E662C, 0x78EF631, 0x2A09DA0, 0xB088C72F, + 0x92EE0D42, 0x360DCD5F, 0xF333FE48, 0x8D63CC06, 0x233A8ACB, + 0x706651ED, 0x7AA5C079, 0x262239D1, 0x3EBBEBB6, 0xA25A4F3D, + 0x32581A06, 0x6E6FD780, 0x5773F7C7, 0x75ED1DDC, 0x90DF2D15, + 0xBC79A9BC, 0xB7175917, 0x354E381C, 0x762AADD7, 0xF643DAC1, + 0xF3BBF49E, 0xD2FECE7E, 0x6C8140F4, 0xD7694875, 0x92D30822, + 0xC742A7CF, 0xB792ED98, 0x121CFE24, 0xA04E1EE7, 0x58CE268, + 0x215A080, 0x316CB323, 0xFAB14A31, 0xE1C13C03, 0xFD8EF4F1, + 0xF3F446D0, 0x6C6CEA0A, 0xBBFDF9FB, 0x67242969, 0xBE55A4EB, + 0x8FF5534, 0x52F0DF1C, 0x9710ADE3, 0xD40F4A21, 0x7984E8E7, + 0x419545EB, 0x993F7880, 0xAB246B20, 0x408AABC4, 0xCBF6EA49, + 0xC0894C55, 0x4CAA6398, 0xA47856E9, 0xAF2AE47D, 0x22F55D33, + 0xF0D37915, 0xD0634C72, 0xD983671, 0x2BCC5AF8, 0x9A77D48, + 0xC11B5CFA, 0xF107CD7E, 0x3A6B3593, 0xE1425F05, 0x6271812A, + 0x5B838310, 0xBD8418CA, 0x10A58792, 0x239F7137, 0xA13D5071, + 0x7F9930D4, 0xA462664F, 0x54180F8E, 0x291585BA, 0xE586B87A, + 0x144B2C12, 0x98E425C7, 0xBAA4B373, 0x18F0D03C, 0x99462AC0, + 0xD8B4D2EF, 0x72473895, 0xA6BF5435, 0xEDAD53B, 0xE0912FA6, + 0x5C33F331, 0x3D93CD7, 0x4D03D752, 0x20699929, 0xB89962F9, + 0x36E781E9, 0xF58B642C, 0x5FCA69E3, 0x5960A7F4, 0xAD5AAFD0, + 0xDF18324A, 0x3DB1E5AA, 0x76BA3876, 0x1BC29AF6, 0xBCC18841, + 0x73A60174, 0x625BFF58, 0x67C57724, 0x4458E53C, 0xE157B095, + 0x2B370837, 0x83DF6CE3, 0xDD08EEFA, 0x3F52A7C2, 0x191B4785, + 0x60843D82, 0xB0DE11F1, 0x105EA26C, 0x6E1C7AA2, 0x47AADD14, + 0xB6676D03, 0x3B8D4DF6, 0x737A694, 0x409521DC, 0x744206A, + 0xC722023F, 0x2BE4EAD5, 0x63E11D76, 0xCA4A09AB, 0x5CF2D2B9, + 0x31586916, 0xCDFD7D84, 0xB203F634, 0xAD7329D4, 0xC524582F, + 0x2E53E6C1, 0xBB0E019B, 0xB8538C6A, 0x6A2542D, 0x8A6A00E5, + 0x119725CC, 0x5406D347, 0x1B6FFAF1, 0xECCF71F1, 0x981117F2, + 0x7167CA76, 0x74F4B880, 0x77A55F47, 0x59EADB62, 0x4A331D95, + 0xBCBBA76F, 0xA45C4D50, 0xC718D5, 0x87CE05D1, 0x60D47AD5, + 0xA5CA9C40, 0xB0061766, 0xE69B39DF, 0xBD5F1320, 0x9930EAD3, + 0xA8B38325, 0x8DD090F, 0x6A6EEF37, 0x2DF16F66, 0xAB514C7E, + 0x31109C58, 0xFD48C7FC, 0x515341CA, 0x77AB8EA6, 0x41328DAF, + 0xBAF8D31E, 0xA4B31611, 0xED37F331, 0x7A832A22, 0xA22591C7, + 0x722D1F89, 0x3B19CF18, 0x261B8A4D, 0xC3F6F6DB, 0xCF8CED61, + 0x990FA250, 0xA02E72A9, 0x560DCEA2, 0xB08E67B4, 0x3674E663, + 0x97CC3852, 0xA7EB2EAC, 0xFFDE0AA8, 0xA64719A, 0x23269EDD, + 0x3C0B339E, 0x86284D40, 0x48D82ECB, 0xA4D4CCF8, 0x43631B91, + 0x4BF0C248, 0xB6497B9B, 0x6827BC58, 0xE30B7AF9, 0xA0CCBF26, + 0x6C3B7B71, 0xD744B3ED, 0xFA25D2F6, 0x4CDE642D, 0xD65B8142, + 0xA6F9207F, 0xE7A207BE, 0xDB506684, 0x44DA4780, 0x9175EA0C, + 0x156104AF, 0x4155E1B0, 0x6E3A6886, 0x9DBA1EA2, 0x5423D9C8, + 0xCC024E22, 0x758F852A, 0x1DD6395, 0x2D19CBAD, 0xE164F5A1, + 0xC2084602, 0x89C274AD, 0x13CB5562, 0xD7FE2D5B, 0xE07A4EE5, + 0x1672BA91, 0x4F624CCF, 0x2E5EA4A3, 0x28FEEFAF, 0xBDDA6EF4, + 0x32AFD40C, 0x99A5FB3B, 0xDD1D73A3, 0xA342CB3E, 0xA78445F5, + 0x53979C3B, 0x427D7943, 0x5221B58C, 0xA6CE9A5E, 0xFB50ECA4, + 0xBB86E36E, 0x60839F6D, 0xC5E1C2F3, 0xA1B7FB04, 0xFBB65E0C, + 0x78B80F5E, 0xFD8D972B, 0x3BF3BA90, 0x2D572D9, 0x2B5BC920, + 0xB6A0DE01, 0xD274D306, 0xC7C6C855, 0x9CAA669B, 0xB04AA641, + 0x4D6B1760, 0x3E17ED79, 0xD23241B0, 0xA4A6F957, 0xCBDE76AF, + 0x4E5F9493, 0x4C215DA5, 0x33A052B, 0x1A4D80C2, 0x40AEEBCA, + 0x390D106B, 0xE9E8E018, 0x5AF3D6CF, 0xE35E1D4, 0xC4FB1C6, + 0x14B6299B, 0x8D2E25F0, 0xCCBF932A, 0xC5AC18B6, 0x2227567D, + 0x86B5CE2F, 0x26344534, 0x22C515EC, 0x2442B70D, 0xEC3721C6, + 0x34EF687D, 0x9C06323A, 0xEAF3EA60, 0x60396F52, 0xEAE78AA1, + 0xC9D06CBC, 0x6F95F6C8, 0x584CC258, 0xBA9A27BB, 0x66DF8D47, + 0x9D4804EA, 0x57DD9E67, 0xF89C7895, 0xF5336111, 0x25C122C8, + 0x62742114, 0xCFBF6D26, 0xBF9F6482, 0xE6F02CD9, 0x11083202, + 0xC99E2618, 0x7EBC9351, 0x440112F1, 0xC9DFFBC1, 0x3BF4DC25, + 0xB1BA7FA0, 0x61AF9AED, 0x6B1F7D29, 0xAD865294, 0xE3E01129, + 0x7E9E77A5, 0x100435D7, 0x9FE3A71, 0x88597C81, 0x722849FA, + 0x31C5A0AF, 0xFBA178DC, 0x7F102D31, 0x5CA07864, 0x950E6F98, + 0x82C34882, 0x5D041F11, 0x8C613C57, 0xD398CFD1, 0x426F38AD, + 0x5599AB1D, 0xFAFA078D, 0xAB25B413, 0xD94B32CF, 0xB288FE38, + 0x2893BB46, 0x9A0B4168, 0xA91BCA94, 0x653A5E8D, 0x2174EBBE, + 0xDEFE6415, 0x30DA429C, 0xD0C5E40C, 0xB4719AA4, 0xD29CE7A6, + 0x905957CD, 0xCD287499, 0x83CA0AA7, 0xA8385832, 0x25A0CA02, + 0xC20D47A4, 0xB562F556, 0x4BC19E4C, 0xD9E215C7, 0x27E838B4, + 0xC58612F4, 0xA2827F6F, 0xC49DCDBA, 0x679B7362, 0x4E495845, + 0xCFD2F0D1, 0x395E76A0, 0x375A655E, 0x92E2058F, 0x73F9F0CA, + 0x61EFF3B3, 0x51FFD362, 0xE7410345, 0x7FDA8B3B, 0xA219E2E8, + 0x17ABE543, 0x26557412, 0x4B30084D, 0xA68E191D, 0xFE0D93DF, + 0x73EF127D, 0x4DECDDB1, 0x77FAF45F, 0xD6002898, 0x92DD0A40, + 0x157F6DDF, 0xC2A55F8E, 0x4359F924, 0xFB630C3F, 0x338B6B58, + 0xB2945F75, 0x4FA23A0E, 0x836EB8C0, 0xB3B18FD, 0x86114337, + 0x24668ACB, 0x99BB82F0, 0x924C8A47, 0xBA959701, 0x81155ABF, + 0x8C612D71, 0x36074CA7, 0xD1668C41, 0xE35F58C7, 0x7FC2802D, + 0x8E6A7CF3, 0x65B07D07, 0x815F6A6B, 0x791BF0DD, 0x6E47D719, + 0xC24394C7, 0xE84A6EB, 0xF194AFEE, 0x464A2F52, 0x677579FD, + 0xEBA775AE, 0x1F6EEFF, 0x9A795237, 0x78D9D45F, 0x9D0B344D, + 0xBBD34AB7, 0x2F85B12A, 0x16C5C2AD, 0x3990985D, 0x88DF3351, + 0x82811AA5, 0x6D351F41, 0x4066A69D, 0x86B660BF, 0x6EDB4768, + 0xDDD78CF0, 0xB5D74F6E, 0xE89E220C, 0x91439687, 0x947CC9C9, + 0x3857E2BD, 0x302F8AE4, 0x1DABE7F8, 0x4832D6C9, 0x37D58FCB, + 0x4EA8A711, 0xCD7BAC98, 0x19DBF8BC, 0xD8DE8DC2, 0xEAFF7E7B, + 0xB7629C93, 0x792C6E19, 0xF7009192, 0xFF88439D, 0x2E196A66, + 0xEC71B78C, 0xEAF4BB3A, 0x7C16225E, 0x668F337, 0xCBEE1608, + 0x6D5B5552, 0x345DC590, 0x681209CC, 0x7B24A819, 0xD08A1416, + 0x99888FE3, 0x9FC7288A, 0x24BD8502, 0xEA1D9678, 0x20EECA0, + 0x59BEA057, 0x5ADE91EB, 0xDEA8E49D, 0xFA200E6F, 0x9149C81D, + 0xF2281E93, 0x8A5B0451, 0x67312D58, 0xE3B849F1, 0xD2217960, + 0x7CDF59F3, 0x33C775C0, 0x9EBA8799, 0x7DF9506, 0xB4E96110, + 0xB8FCF3E3, 0xDEA059B2, 0x8229B6EA, 0x316486F6, 0x43919185, + 0x6C0D90F3, 0x1C6F3DF8, 0x38DB92A9, 0x5CD41244, 0x2C9F0A7B, + 0xDF4A315F, 0xF7CE9C66, 0x4C800860, 0x318D53E0, 0xF105C20D, + 0xD753E1F2, 0x750810BA, 0xA17ECCA5, 0x2010140, 0x4D884763, + 0xC2BB0DA7, 0xB2D5BA74, 0x141CECD4, 0x887FDFC3, 0xC64B53, + 0x2D2A85F6, 0x15532B45, 0x5D5CBCE1, 0xBEB9A16A, 0xA214611B, + 0x9FC5AC5F, 0x11AE5DD7, 0xA0B9A5A9, 0xFC648AF4, 0x740009AC, + 0xED0E0321, 0xB8E6A61, 0x8910C544, 0xC74F26C8, 0x9525CCF3, + 0xB41AEB59, 0xE61984CE, 0x598B2197, 0xA412E59D, 0xE1976DD4, + 0xB29BBE16, 0x88FD9FB0, 0xB04006F3, 0xB45E309, 0xD5CC15F1, + 0xD9DAF630, 0xDC809335, 0x803ED52, 0xB537F5A5, 0xA994F6EB, + 0xF5288568, 0xF66FD264, 0x2EA2B3A6, 0x647619F3, 0xFFB38C7A, + 0x1BC03B9, 0xB6BC3061, 0xBF30596E, 0xBE2AD27B, 0x8AC04220, + 0x641979A3, 0x9ECCBB89, 0xA144FBC1, 0x4E8FAE26, 0x8C5A9D90, + 0x299ED467, 0xD7C9C7E3, 0x1D4865ED, 0x76F31C3D, 0xCEE81CDF, + 0xB479195E, 0x6FFB3AE1, 0xDC8A398, 0x300F7364, 0xC7940AFA, + 0x3B85BE3E, 0xD98CC40D, 0xA24A3D89, 0x3A674204, 0x22888A38, + 0x2E77F2D, 0xA2841C9C, 0xCF0689C3, 0x9FE98922, 0x89335017, + 0x2D6B69A7, 0xFEDB63F9, 0x899AF4EF, 0x9F9F9B40, 0xA4BE97E8, + 0xA51DAF7A, 0x16AC50D3, 0xA8D7ED6, 0xED193443, 0x7615EF1B, + 0xB0DF6A4E, 0x64FFE794, 0xE3DB2C9A, 0x7435B022, 0x556E825C, + 0x23802AF9, 0xC25098A4, 0xE75A18BB, 0x70B2A7B9, 0x7FB81BF, + 0x63EF910, 0x6C669591, 0x6574DD2B, 0xCF6E379D, 0xD2B3AFAC, + 0x1E6A1101, 0x1DE22385, 0x2338191F, 0xC69704B6, 0xCBABC599, + 0x54EB4809, 0x7839BE6D, 0xD50017DD, 0x39B1A0E1, 0x288D52D3, + 0x2D52668C, 0x20D22A68, 0x4E1207D1, 0x3FCC0EFE, 0x47F3FE64, + 0x25177A90, 0xB4BFDD4D, 0xDA8DBDCE, 0x6F7275A8, 0x6BEAA655, + 0xAA1810FC, 0xE4DB593A, 0x8A4D4BC0, 0x2C402E93, 0xF1C0F7F9, + 0x6F0CC577, 0x70412414, 0x752F9DC1, 0xD82E38EA, 0xAC455F7B, + 0x4DCD4EDB, 0x92BC2696, 0xFB03F135, 0x4FCA1F8C, 0xBD5E75F6, + 0x502F41B0, 0x3616D3F1, 0x2E5B8E31, 0x2026EB19, 0x57E783D7, + 0x467BBE00, 0x4703ABA3, 0x1F776B9C, 0xE2570A84, 0xFEC7DB48, + 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, 0x99D5D8ED, + 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F, + 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB, + 0x56186AA1, 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94, + 0xAC18B207, 0x5FC78B3, 0x7F10621E, 0xA769E6B2, 0xEC9F4A11, + 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, 0x73D63FED, 0xE36E9F5E, + 0x8AC1DA0E, 0x3F3DB3EB, 0x738326EA, 0x35C366B1, 0xCD476E86, + 0x82F6B208, 0xF11A9FC1, 0x426AC396, 0x7E4D1B93, 0x75E4EDB7, + 0xAF3C44A7, 0x51A5EF5C, 0xFAD2463D, 0x8A5639CA, 0xC995AC78, + 0xCC4BE4F6, 0x3AFE7F8D, 0x66993D04, 0x4386FF37, 0xCBC1C6C2, + 0x55A8F5EC, 0xE81A9A75, 0x30A67E1B, 0x4A4A7D0C, 0x20F7F993, + 0x1891805, 0x738976AD, 0xD426E7D6, 0x3C5CEEBF, 0x4499187F, + 0xABF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456, 0x421BCF29, + 0xF6740F9C, 0x8916BB8D, 0x3D72AAB, 0x9AD54DD7, 0x7549C6EE, + 0x7317342B, 0xA18546D4, 0x1056BDA7, 0x54BBCCCE, 0x8CE63E46, + 0x5D146234, 0x33BE6C63, 0xB250C4E5, 0x89D72335, 0x87C36BA, + 0xB65530CC, 0x2DFAC48C, 0x1663D16F, 0x59B80AA, 0x950274EA, + 0x92532D4A, 0x3CEF802D, 0x492FBDA5, 0xA63A2574, 0xEF8005C2, + 0x94A18651, 0xAF627ABA, 0x6829B238, 0xA698F646, 0xD2598516, + 0x10144D36, 0xD9B1D1B9, 0xAB2ACF05, 0x5395B699, 0xA7851C75, + 0x1806C6F3, 0xAE970306, 0x3284B145, 0x98F4FE8F, 0xECDD35CC, + 0xDDC1EE0E, 0xC4848865, 0x925826BD, 0x4078BE39, 0x68A8561A, + 0x323045DC, 0xA933B37F, 0xBA2AEE2E, 0x4F24F65D, 0x349EE246, + 0xF97B9D0E, 0x46DC5759, 0x4529F425, 0x80D17B42, 0x8E16F709, + 0x1B42206A, 0x4934A526, 0x391BB6DE, 0xB52EF45C, 0x26C30290, + 0xCBA23CAA, 0xA501A8C3, 0xD922C4F8, 0xE8824E53, 0x6F4255DC, + 0x5960B544, 0x58BC69D6, 0xCA936323, 0xFDDF053C, 0xC2E002D6, + 0x7D750755, 0x8A3F9CD1, 0x35F8F6F8, 0xFB7BD154, 0x65CFF94F, + 0x390A58DD, 0xD97C4093, 0x501CA2A3, 0x8EA5DEBC, 0xCA93461F, + 0xE02D984C, 0x126F8517, 0x39FDD887, 0x46241AE9, 0x777E854D, + 0xE2B36349, 0x58E3FA9F, 0x971DEF1E, 0x8E156228, 0xC0E14E9, + 0xA9A01BE6, 0xB318C990, 0x971680D6, 0xA1F359CE, 0x487E23F4, + 0x7DE465B0, 0x4E4C905E, 0x2A652959, 0x116FF167, 0x5C74AAB9, + 0x467BBE00, 0x4703ABA3, 0x1F776B9C, 0xE2570A84, 0xFEC7DB48, + 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, 0x99D5D8ED, + 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F, + 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB, + 0x56186AA1, 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94, + 0xAC18B207, 0x5FC78B3, 0x7F10621E, 0xA769E6B2, 0xEC9F4A11, + 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, 0x4FEFC920, 0x28DF4EB8, + 0x29EBF45A, 0x1E350CF6 + }; + +/* The source data is random across the q31_t range. Accessing it by word should + remain random. */ +const q15_t * filtering_q15_inputs = (q15_t *) filtering_q31_inputs; +const q7_t * filtering_q7_inputs = (q7_t *) filtering_q31_inputs; + +const float32_t filtering_f32_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS] = +{ + 43.0264275639 , -17.0525215570 , -94.8488973910 , -8.1924989580 , 7.2830326091 , 66.8368719314 , 33.9778190671 , 117.8652289772 , + -129.6077797465, -14.6420815368 , 18.0239223278 , 20.6760530292 , 55.0375037651 , 1.8674609862 , -85.6534302408 , -33.5750364909 , + 29.2110949614 , 110.4727049460 , -94.1914619387 , -1.4084169343 , 83.5181653041 , 47.3073514127 , -13.3420621181 , 30.3389699104 , + 12.1188124277 , 100.9730921941 , -114.0146362390, -77.5823200409 , 37.2019034618 , 40.0026301128 , -58.3387276630 , -34.9472398600 , + -5.1169678311 , -87.7660091118 , -150.5888601131, 56.0349370503 , 50.2168884079 , -74.2313236767 , 22.3648603560 , -6.8676387051 , + 74.8957303680 , -90.1292012823 , -55.1436241586 , -66.6732976100 , -6.7918147615 , 7.7612697081 , 35.7892605979 , -20.0470508830 , + 41.8369017546 , -143.7378056984, -41.9127158600 , -108.3531841158, -57.1917422289 , -124.2808828105, 38.9316388820 , -77.9212517405 , + 37.1990818377 , -28.9545952748 , -155.6371057564, 45.8088886393 , 36.2537018275 , -6.5727656016 , -104.2070491921, 45.5583813729 , + -19.7674717059 , -80.4802190947 , -1.4444563441 , -42.2142256438 , 36.6546339194 , -57.0866498590 , 44.4677067511 , 65.7285753407 , + -103.8158864647, 25.4348723711 , -153.5419639389, 39.3608409474 , 49.1658103436 , 79.5570602275 , 75.2944095996 , 58.9394700746 , + -53.1018534392 , 33.4172444014 , 35.6224682287 , -64.4353396418 , -125.8464291251, -47.6072111617 , -26.2177687594 , -12.0061322096 , + -17.7887967585 , -28.2926175090 , -62.0691715749 , 40.5098573604 , -191.1123732593, 119.6750713043 , 19.6182375803 , -26.7615252921 , + 2.2957847015 , -108.3436451287, -50.5906164995 , -5.6360985100 , -11.6772204201 , -84.2765293757 , -60.9317810068 , 82.0446350218 , + -70.2048296348 , 72.8738253222 , 60.2450218115 , 114.2741231228 , 46.8180775285 , 6.9915412654 , -8.9909197429 , -78.9165936808 , + 66.4731535459 , -68.4235455651 , -79.8254597080 , -10.6308477115 , -62.6161569330 , -55.7744410292 , -11.8408366528 , 98.1034940997 , + 35.8213741877 , -54.4694482732 , 86.9631830044 , -53.0343838122 , -47.4898642865 , -47.2010929590 , -31.3312639685 , -23.0908245172 , + 12.0258009869 , -5.1098204703 , -9.8420230737 , -107.3328761158, 44.6810431959 , -17.9083820345 , -60.9753512872 , -7.5915088994 , + 17.2250813329 , 57.9176125648 , 124.3004161362 , -63.1950908493 , 120.5788885640 , -44.1734238117 , -91.7408095116 , -43.5696066595 , + -49.9560710099 , -167.8513443296, -70.9437505499 , -46.4109705355 , -64.2264526456 , -13.9995803916 , -100.9548186356, 9.9101010575 , + -50.0615130815 , -55.7590145012 , -60.3195153388 , 61.7913378549 , -102.0850899209, 53.2360193126 , -25.8997883369 , 75.1445512333 , + -113.8148602310, 17.8027281119 , -19.5006822722 , -44.2169628471 , 107.5017084384 , -113.7909124666, -43.9735396033 , 7.6880981388 , + 46.7384653508 , 9.9047443751 , 81.8646964362 , 132.3812863877 , -95.6959050236 , -68.5015813484 , 65.8586404494 , 18.5039353889 , + -30.1786166621 , -90.3098515667 , -22.9356228552 , -20.5778272423 , -2.2127786675 , -35.4418447703 , -51.8722915974 , -107.9024439078, + -51.5940748232 , -51.7463262677 , 74.2795485984 , 94.2205022462 , 9.7016384049 , -47.3556083155 , -36.7822314478 , -151.6455525363, + -15.7183814485 , 78.2063383182 , 0.1516414969 , 37.9304181609 , 20.6185902740 , -22.2164106778 , 6.1160554677 , 2.4061326953 , + -111.6681824598, -60.0858917090 , 75.1698614693 , -76.5787410444 , 28.3391655715 , -2.4946186443 , -68.0378899682 , 104.0893199171 , + -51.8319647254 , 38.8521710524 , 75.9114239564 , 73.9206172905 , -103.2533029987, 6.9002718274 , -36.6346436319 , -25.1990926265 , + 1.5852145953 , -50.6438436795 , 21.5018844428 , -151.9305562846, -51.7326681814 , 21.4475994143 , 42.2564011921 , -74.0520586926 , + 49.7370635809 , -13.2957534126 , 36.6746826778 , -31.7005492589 , 148.4894964268 , 79.7890632353 , 16.8856024809 , 16.1690460177 , + 39.2665169484 , 117.2461167794 , -37.4827984831 , -47.8387803604 , -95.7025286193 , 34.3058214285 , -124.9536456028, 56.1640195764 , + 94.3636873606 , 35.3992852810 , -38.3920852159 , -100.5738062016, -29.7837022314 , 42.9133913996 , -34.2715618187 , -14.3589115627 , + -16.5935468750 , 20.4574192236 , -88.7897972666 , -38.6285080386 , 53.3203422726 , 98.5991486746 , 122.7305462474 , 67.7902817187 , + 5.1764117389 , 5.0632821624 , 21.9288789574 , -78.3140512638 , -21.2069682335 , 23.6342010925 , 34.4445769455 , 59.1346766615 , + 28.9978778000 , 39.8121180845 , -17.1650033520 , -56.9174900874 , 17.8157086148 , -112.8801457350, -122.4019040408, 140.8669393157 , + -65.4664329639 , 40.6952775518 , 32.7260891658 , -43.2565155866 , 19.3945751928 , -20.1815002000 , -67.6601711640 , -18.1921178207 , + -35.6802153684 , 49.9550290306 , 131.4925251016 , -31.2940938167 , -5.2848453344 , -109.5580577933, 20.2437599390 , -8.8782958734 , + 54.1836717264 , 7.2555852190 , -3.5698316137 , -51.9236786262 , 6.7861547980 , -104.4814551670, 45.8458629668 , 70.0890876844 , + 38.3572837740 , 61.8024165129 , 68.0176962024 , -12.8193934080 , -21.4661610917 , -0.9377108815 , -74.2100679061 , 71.0490808147 , + 91.9813889497 , -14.5797640164 , 3.5036749129 , -138.3605478356, -48.1501349794 , -16.0636922482 , -12.1334197606 , 15.0562207637 , + -34.0878176054 , 55.1075126157 , 97.3829871877 , 0.2053358099 , -94.8713267382 , 51.5460954054 , 21.2966946363 , 58.1331025047 , + -23.4599044132 , -19.3315856528 , -8.4497193577 , -1.9594679356 , -33.1906549336 , -144.6825417978, -57.1218958072 , 35.7353406097 , + 61.4666549819 , 14.6536253128 , 82.1632196866 , -44.6230161723 , -91.1022589278 , -18.5737673927 , -136.8975612334, 56.9606788003 , + 70.7059960183 , -68.2829345081 , -10.2629800455 , -53.6385325047 , -68.7928766204 , 88.2444688302 , 83.1412324801 , -102.9206928160, + -68.2329763159 , -69.7552955469 , 108.2132269009 , -28.2582329307 , 5.6685898328 , -36.0392956840 , 43.3269513128 , -8.6436416796 , + -16.5054886972 , 11.5008791788 , 39.6923606683 , -28.9039554061 , 13.5938214364 , -23.6296332202 , 49.1171161163 , 53.1636857935 , + -62.9672053166 , -54.2594757384 , 48.3838956696 , 8.0469071555 , -33.6472086213 , -120.5381752144, 55.0880453111 , 17.8990740563 , + 144.9402232336 , 101.7886229203 , -73.3666393712 , -16.4721379138 , -12.7447935685 , 101.8245160983 , -49.7026860415 , -15.1227790364 , + 65.7430288442 , -131.8695390036, 10.2750933946 , 90.9752774838 , -26.5859990591 , -95.6962772568 , 76.2174589344 , 24.8796848060 , + -38.8938223046 , 54.1687774852 , -37.3585968996 , -34.6848570502 , 33.0151011570 , -55.8345877671 , -3.9009101671 , -31.5024971691 , + -9.6863895491 , 91.8719195957 , -58.9993249744 , -25.6887030614 , -8.0829472205 , 4.6386491741 , -71.4019697167 , -21.3734669095 , + 86.2079144404 , 79.6823974266 , -0.0910915997 , 44.8067718095 , 58.7204020766 , 72.6856808976 , -50.3373732478 , -116.1175365534, + -15.0884909384 , 5.4593772059 , -63.6553527905 , 37.3460388205 , -32.2399421679 , 95.7569350513 , -7.3700141964 , -56.0370832967 , + -41.7377150439 , -42.0042856519 , 12.5134312941 , 93.7845584531 , -32.4801087157 , -33.3976050318 , -24.2252126001 , -46.3199064467 , + -20.3704610276 , 15.8571376404 , 88.9127217235 , -33.1132582267 , -1.0005675836 , -28.1780471904 , 150.9349379135 , 38.0600520828 , + 36.4338677563 , -3.3709201641 , 29.7709773016 , 16.5064119077 , 21.3147729463 , 110.6714300904 , 18.8406036507 , 14.8963298097 , + 50.9975960392 , 16.3991140350 , -194.0805845907, -41.6723945839 , -74.8991127408 , -6.4587655805 , -0.6883628218 , -49.8709647175 , + 194.2265120473 , 64.3043624521 , 16.0040882780 , 68.4032551772 , -43.4050313128 , 84.6826289824 , -28.1357565943 , 134.6895584120 , + -7.9746152680 , -95.6692886462 , -48.9444370342 , 79.4479343188 , -50.5345228122 , 52.4800633307 , -14.7735051703 , -20.1510237050 , + 22.5049816980 , 64.4191999102 , 24.8385648232 , 99.4265041360 , 62.0189508473 , -28.3892600378 , -109.8842008564, -79.0407483407 , + 18.3408112020 , 49.1650536089 , 31.5419844924 , -36.1160722679 , -132.9148081329, 10.4053531567 , -129.2463715470, -43.4602207151 , + -24.2420653292 , 91.5388317556 , 21.4762248190 , -44.3810909139 , 18.4098011282 , -45.8691164539 , -20.9831197962 , 16.2076792914 , + 66.0224147666 , -13.6794615513 , 101.2163279622 , -62.4462618603 , 22.2040981785 , -52.3208382802 , -24.7909079016 , 58.5150375093 , + 18.8569705105 , -55.6083430939 , 131.0273367422 , -34.5209015065 , 121.4357296573 , -77.2590299593 , -51.5929566898 , 5.0247131098 , + -23.8451707592 , -4.5912313547 , 31.1387246821 , 61.7019310824 , 49.1912429744 , -50.5836913031 , -74.8182600630 , -21.6209317022 , + 20.9409464654 , -72.7870824583 , -28.3530746820 , -45.0794425434 , -13.4910629905 , -62.0158772255 , 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137.1205201755 , -19.0830817212 , 14.3407526579 , + -56.5921994449 , -25.6084873186 , -44.9470801106 , -133.3139496090, 0.3487447576 , 33.4499716730 , 34.7126257844 , -9.3307383323 , + 27.2996276947 , 10.8765676134 , -91.1032360444 , -90.9584216222 , 1.6981490570 , 96.8557438791 , 56.7726390913 , -44.3246449237 , + 52.3260643361 , 21.5551140465 , 27.4535327381 , 2.0072717479 , 7.4823125629 , 77.1185863870 , 16.1372262663 , -10.7206012957 , + 66.8830091413 , 49.3523828287 , 54.0855375598 , 30.8570349345 , -10.9255375390 , 62.3910624674 , 30.9238561381 , 0.3352881853 , + 72.1022806197 , -28.8319885008 , 23.3335288806 , 46.8999035980 , -67.0984424822 , -164.7917209112, 42.5767681360 , -92.4668227688 , + 43.8491734282 , -17.1126540408 , 37.4819594334 , 69.0774409673 , -39.3530526854 , -14.0693747124 , -60.2520781215 , -80.3860105519 , + 32.6689956840 , 15.3393042576 , -18.5529761307 , 97.3942151573 , -4.4462855745 , 13.7614349817 , 158.3358780719 , -44.7258299667 , + -17.7741912819 , 116.5136962268 , -33.6261057820 , 22.8344441288 , -155.1423976144, 5.7070117893 , -22.7906543902 , -45.0633909283 , + -13.9329987929 , -66.0848932507 , 1.1383038109 , 123.8386958483 , 67.6662401589 , 45.9152963554 , -27.4397697462 , 97.9596747354 , + -6.3544655181 , 29.0832146722 , 96.3468162499 , 32.4535976137 , -91.0650399301 , 2.7293262791 , 70.7853483111 , -92.3655274571 , + 69.0359217256 , 83.1530567979 , 35.8375091111 , 7.3393552348 , -95.1770165365 , 76.4905790891 , 55.6253140577 , -29.5315327050 , + -16.5935468750 , 20.4574192236 , -88.7897972666 , -38.6285080386 , 53.3203422726 , 98.5991486746 , 122.7305462474 , 67.7902817187 , + 5.1764117389 , 5.0632821624 , 21.9288789574 , -78.3140512638 , -21.2069682335 , 23.6342010925 , 34.4445769455 , 59.1346766615 , + 28.9978778000 , 39.8121180845 , -17.1650033520 , -56.9174900874 , 17.8157086148 , -112.8801457350, -122.4019040408, 140.8669393157 , + -65.4664329639 , 40.6952775518 , 32.7260891658 , -43.2565155866 , 19.3945751928 , -20.1815002000 , -67.6601711640 , -18.1921178207 , + -35.6802153684 , -19.6571455162 +}; + +/*--------------------------------------------------------------------------------*/ +/* Blocksizes */ +/*--------------------------------------------------------------------------------*/ +ARR_DESC_DEFINE(uint32_t, + filtering_blocksizes, + 5, + CURLY( + 1, 7, 14, 32, FILTERING_MAX_BLOCKSIZE)); + +ARR_DESC_DEFINE(uint32_t, + lms_blocksizes, + 3, + CURLY( + 128, 256, LMS_MAX_BLOCKSIZE)); + +ARR_DESC_DEFINE(uint16_t, + filtering_numtaps, + 5, + CURLY( + 4, 6, 14, 32, FILTERING_MAX_NUMTAPS)); + +ARR_DESC_DEFINE(uint16_t, + filtering_numtaps2, + 5, + CURLY( + 6, 12, 18, 24, 30)); + +ARR_DESC_DEFINE(uint16_t, + filtering_numstages, + 3, + CURLY( + 1, 7, FILTERING_MAX_NUMSTAGES)); + +ARR_DESC_DEFINE(uint8_t, + filtering_postshifts, + 3, + CURLY( + 0, 1, FILTERING_MAX_POSTSHIFT)); + +ARR_DESC_DEFINE(uint8_t, + filtering_Ls, + 3, + CURLY( + 1, 2, FILTERING_MAX_L)); + +ARR_DESC_DEFINE(uint8_t, + filtering_Ms, + 6, + CURLY( + 1, 2, 4, 7, 11, FILTERING_MAX_M)); + + +/*--------------------------------------------------------------------------------*/ +/* Coefficient Lists */ +/*--------------------------------------------------------------------------------*/ + +// There must be at least max( FILTERING_MAX_NUMTAPS + 2 , FILTERING_MAX_NUMSTAGES * 6 + 2) coefficients +const float32_t filtering_coeffs_f32[FILTERING_MAX_NUMSTAGES * 6 + 2] = +{ + -13.0572f, 0.0f , -97.4724f, 8.4111f , -7.2193f , -53.7577f, 22.2630f , + -1.0509f , -25.9198f, 26.5207f , -12.6697f, -78.7453f, -0.6540f , 0.3119f , + 13.4595f , -6.7225f , -4.1313f , -38.5974f, 3.2700f , -51.6191f, -22.4314f, + 0.2481f , 32.9779f , -37.6421f, 5.4469f , -7.0023f , 24.3657f , 9.9140f , + 0.2870f , -13.0499f, 29.3333f , -53.1396f, -2.7555f , 0.5377f , 35.3491f , + -3.7134f , 0.8548f , 4.7469f , -10.5865f, -2.7285f , -1.5912f , -13.3502f, + 6.8532f , -8.2304f , -8.1193f , 3.8257f , -2.1703f , 13.5727f , 14.2736f , + -0.9855f , -8.9334f , -13.8883f, 11.8430f , -2.2024f , 0.9795f , 15.6191f , + 5.2121f , 10.8102f , -9.4171f , 6.0411f , -0.9131f , 10.6992f , -3.2634f , + 7.5849f , -4.9305f , -6.0549f , -7.9409f , 1.5827f , 13.3177f , 8.6727f , + -13.2268f , 11.1239f , 0.2481f , 32.9779f , -37.6421f, 5.4469f , -13.8883f, + 11.8430f , -2.2024f , 0.9795f , 15.6191f , 0.2481f , 32.9779f , -37.6421f, + 3.2700f , -51.6191f +}; +const float64_t filtering_coeffs_f64[FILTERING_MAX_NUMSTAGES * 6 + 2] = +{ + -13.0572f, 0.0f , -97.4724f, 8.4111f , -7.2193f , -53.7577f, 22.2630f , + -1.0509f , -25.9198f, 26.5207f , -12.6697f, -78.7453f, -0.6540f , 0.3119f , + 13.4595f , -6.7225f , -4.1313f , -38.5974f, 3.2700f , -51.6191f, -22.4314f, + 0.2481f , 32.9779f , -37.6421f, 5.4469f , -7.0023f , 24.3657f , 9.9140f , + 0.2870f , -13.0499f, 29.3333f , -53.1396f, -2.7555f , 0.5377f , 35.3491f , + -3.7134f , 0.8548f , 4.7469f , -10.5865f, -2.7285f , -1.5912f , -13.3502f, + 6.8532f , -8.2304f , -8.1193f , 3.8257f , -2.1703f , 13.5727f , 14.2736f , + -0.9855f , -8.9334f , -13.8883f, 11.8430f , -2.2024f , 0.9795f , 15.6191f , + 5.2121f , 10.8102f , -9.4171f , 6.0411f , -0.9131f , 10.6992f , -3.2634f , + 7.5849f , -4.9305f , -6.0549f , -7.9409f , 1.5827f , 13.3177f , 8.6727f , + -13.2268f , 11.1239f , 0.2481f , 32.9779f , -37.6421f, 5.4469f , -13.8883f, + 11.8430f , -2.2024f , 0.9795f , 15.6191f , 0.2481f , 32.9779f , -37.6421f, + 3.2700f , -51.6191f +}; + +const float32_t filtering_coeffs_b_f32[FILTERING_MAX_NUMSTAGES * 6 + 2] = +{ + -0.0572f, 0.0f , -0.4724f, 0.4111f , -0.9999f, -0.7577f, 0.2630f , + -0.0509f, -1.0000f, 0.5207f , -0.6697f, -0.7453f, -0.6540f, 0.3119f , + 0.4595f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, -0.4314f, + 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f , + 0.2870f , -0.0499f, 0.3333f , -0.1396f, -0.7555f, 0.5377f , 0.3491f , + 0.2369f , -0.5310f, -0.5904f, 0.6263f , 0.0205f , 0.1088f , -0.2926f, + -0.4187f, -0.5094f, 0.4479f , -0.3594f, -0.3102f, 0.6748f , 0.7620f , + 0.0033f , -0.9195f, 0.3192f , -0.1705f, 0.5524f , -0.5025f, 0.4898f , + -0.0119f, -0.3982f, -0.7818f, -0.9186f, -0.0944f, 0.7228f , 0.7014f , + 0.4850f , -0.6814f, 0.4914f , -0.6286f, 0.5130f , -0.8585f, 0.3000f , + 0.6068f , 0.4978f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, + 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f , + 0.2369f , -0.5310f +}; + +const float64_t filtering_coeffs_b_f64[FILTERING_MAX_NUMSTAGES * 6 + 2] = +{ + -0.0572f, 0.0f , -0.4724f, 0.4111f , -0.9999f, -0.7577f, 0.2630f , + -0.0509f, -1.0000f, 0.5207f , -0.6697f, -0.7453f, -0.6540f, 0.3119f , + 0.4595f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, -0.4314f, + 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f , + 0.2870f , -0.0499f, 0.3333f , -0.1396f, -0.7555f, 0.5377f , 0.3491f , + 0.2369f , -0.5310f, -0.5904f, 0.6263f , 0.0205f , 0.1088f , -0.2926f, + -0.4187f, -0.5094f, 0.4479f , -0.3594f, -0.3102f, 0.6748f , 0.7620f , + 0.0033f , -0.9195f, 0.3192f , -0.1705f, 0.5524f , -0.5025f, 0.4898f , + -0.0119f, -0.3982f, -0.7818f, -0.9186f, -0.0944f, 0.7228f , 0.7014f , + 0.4850f , -0.6814f, 0.4914f , -0.6286f, 0.5130f , -0.8585f, 0.3000f , + 0.6068f , 0.4978f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, + 0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f , + 0.2369f , -0.5310f +}; + +const float32_t *filtering_coeffs_c_f32 = filtering_coeffs_b_f32 + 1; + +const q31_t filtering_coeffs_q31[FILTERING_MAX_NUMSTAGES * 6 + 2] = +{ + 0xEEDA759C, 0x00000000, 0x80000000, 0x0B0BA027, 0xF6850544, 0xB967E3EC, + 0x1D3C4F64, 0xFFFFFFFF, 0xDDF65B14, 0x22D3A62D, 0xEF5CBB89, 0x98979EE0, + 0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5, + 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690, + 0x0727234D, 0xF6CDFB14, 0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A, + 0x268530EF, 0xBA37B050, 0x7FFFFFFF, 0xEF5CBB89, 0x00000000, 0x2B4E6639, + 0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5, + 0x1D3C4F64, 0xFFFFFFFF, 0xDDF65B14, 0x22D3A62D, 0xEF5CBB89, 0x98979EE0, + 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690, + 0x0727234D, 0xF6CDFB14, 0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A, + 0xE28B1589, 0x0053690B, 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0xB967E3EC, + 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690, + 0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A, 0xFFFFFFFF, 0xDDF65B14, + 0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5, + 0x2B4E6639, 0xCE919690 +}; + +const q31_t *filtering_coeffs_b_q31 = filtering_coeffs_q31 + 1; +const q31_t *filtering_coeffs_c_q31 = filtering_coeffs_q31 + 2; + +//fourth coefficient MUST be zero for arm_biquad_cascade_df1_fast_q15 to work +//every 6th coefficient after that must also be zero +const q15_t filtering_coeffs_q15[FILTERING_MAX_NUMSTAGES * 6 + 4] = +{ + 0xBA37, 0xEEDA, 0x8000, 0x0000, 0x0B0B, 0xF685, 0xB967, + 0x1D3C, 0xFFFF, 0x0000, 0x22D3, 0xEF5C, 0x9897, + 0xFF24, 0x0068, 0x0000, 0xF72C, 0xFA93, 0xCD50, + 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91, + 0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC, + 0x2685, 0xBA37, 0x0000, 0xDDF6, 0x0000, 0x2B4E, + 0xFF24, 0x0068, 0x0000, 0xF72C, 0xFA93, 0xCD50, + 0x1D3C, 0xFFFF, 0x0000, 0x22D3, 0xEF5C, 0x9897, + 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91, + 0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC, + 0xE28B, 0x0053, 0x0000, 0xBC36, 0xE28B, 0xB967, + 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91, + 0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91, + 0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC, + 0xE28B, 0x11AC, 0x0000, +}; + +const q15_t *filtering_coeffs_b_q15 = filtering_coeffs_q15 + 2; +const q15_t *filtering_coeffs_c_q15 = filtering_coeffs_q15 + 4; + +const q7_t filtering_coeffs_q7[FILTERING_MAX_NUMSTAGES * 6 + 8] = +{ + 0xEE, 0x00, 0x80, 0x0B, 0xF6, 0xB9, + 0x1D, 0xFF, 0xDD, 0x22, 0xEF, 0x98, + 0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xCD, + 0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE, + 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE, + 0x26, 0xBA, 0x7F, 0x00, 0x80, 0x2B, + 0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xCD, + 0x1D, 0xFF, 0xDD, 0x22, 0xEF, 0x98, + 0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE, + 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE, + 0xE2, 0x00, 0x04, 0xBC, 0xE2, 0xB9, + 0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE, + 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE, + 0x26, 0xBA, 0x7F, 0x00, 0x80, 0x2B, + 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE, + 0xFA, 0xCD +}; + +const q7_t *filtering_coeffs_b_q7 = filtering_coeffs_q7 + 4; +const q7_t *filtering_coeffs_c_q7 = filtering_coeffs_q7 + 8; + +/*--------------------------------------------------------------------------------*/ +/* Tap Delay Lists */ +/*--------------------------------------------------------------------------------*/ +//const int32_t filtering_tap_delay[FILTERING_MAX_NUMTAPS] = { +// 0xEE, 0x00, 0x10, 0x0B, 0xF6, 0xD9, +// 0x1D, 0xFF, 0xDD, 0x1A, 0xEF, 0xE8, +// 0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xDD, +// 0x04, 0xEC, 0xE2, 0x00, 0x2B, 0xFE, +// 0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE, +// 0x20, 0xDF, 0x21 +//}; + +const int32_t filtering_tap_delay[FILTERING_MAX_NUMTAPS] = { + 0x00, 0x01, 0x10, 0x0B, 0x03, 0x05, + 0x1D, 0x21, 0x11, 0x1A, 0x1F, 0x07, + 0x20, 0x01, 0x10, 0x0B, 0x03, 0x05, + 0x1D, 0x21, 0x11, 0x1A, 0x1F, 0x07, + 0x00, 0x01, 0x10, 0x0B, 0x03, 0x05, + 0x1D, 0x21, 0x11 +}; + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c new file mode 100644 index 0000000..21ac7fc --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c @@ -0,0 +1,17 @@ +#include "jtest.h" +#include "filtering_tests.h" + +JTEST_DEFINE_GROUP(filtering_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_GROUP_CALL(biquad_tests); + JTEST_GROUP_CALL(conv_tests); + JTEST_GROUP_CALL(correlate_tests); + JTEST_GROUP_CALL(fir_tests); + JTEST_GROUP_CALL(iir_tests); + JTEST_GROUP_CALL(lms_tests); + + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.c new file mode 100644 index 0000000..40e52b2 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.c @@ -0,0 +1,402 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +#define FIR_DEFINE_TEST(suffix, config_suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir##config_suffix##_##suffix##_test, \ + arm_fir##config_suffix##_##suffix) \ + { \ + arm_fir_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps \ + , \ + /* Initialize the FIR Instances */ \ + arm_fir_init_##suffix( \ + &fir_inst_fut, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n", \ + (int)blockSize, \ + (int)numTaps); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir##config_suffix##_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_fir_init_##suffix( \ + &fir_inst_ref, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + ref_fir##config_suffix##_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define FIR_INTERPOLATE_DEFINE_TEST(suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir_interpolate_##suffix##_test, \ + arm_fir_interpolate_##suffix) \ + { \ + arm_fir_interpolate_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_interpolate_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps2 \ + , \ + TEMPLATE_DO_ARR_DESC( \ + L_idx, uint8_t, L, filtering_Ls \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n" \ + "Upsample factor: %d\n", \ + (int)blockSize, \ + (int)numTaps, \ + (int)L); \ + \ + /* Initialize the FIR Instances */ \ + arm_fir_interpolate_init_##suffix( \ + &fir_inst_fut, L, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir_interpolate_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_fir_interpolate_init_##suffix( \ + &fir_inst_ref, L, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + ref_fir_interpolate_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize * (uint32_t)L, \ + output_type)))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define FIR_DECIMATE_DEFINE_TEST(suffix, config_suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir_decimate##config_suffix##_##suffix##_test, \ + arm_fir_decimate##config_suffix##_##suffix) \ + { \ + arm_fir_decimate_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_decimate_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps \ + , \ + TEMPLATE_DO_ARR_DESC( \ + M_idx, uint8_t, M, filtering_Ms \ + , \ + if (blockSize % M == 0) \ + { \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n" \ + "Decimation Factor: %d\n", \ + (int)blockSize, \ + (int)numTaps, \ + (int)M); \ + \ + /* Initialize the FIR Instances */ \ + arm_fir_decimate_init_##suffix( \ + &fir_inst_fut, numTaps, M, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir_decimate##config_suffix##_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_fir_decimate_init_##suffix( \ + &fir_inst_ref, numTaps, M, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + ref_fir_decimate##config_suffix##_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize / M, \ + output_type); \ + }))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define FIR_LATTICE_DEFINE_TEST(suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir_lattice_##suffix##_test, \ + arm_fir_lattice_##suffix) \ + { \ + arm_fir_lattice_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_lattice_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numstages_idx, uint16_t, numStages, filtering_numstages \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Stages: %d\n", \ + (int)blockSize, \ + (int)numStages); \ + \ + /* Initialize the FIR Instances */ \ + arm_fir_lattice_init_##suffix( \ + &fir_inst_fut, numStages, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir_lattice_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_fir_lattice_init_##suffix( \ + &fir_inst_ref, numStages, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState); \ + \ + ref_fir_lattice_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + + +#define FIR_SPARSE_DEFINE_TEST(suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir_sparse_##suffix##_test, \ + arm_fir_sparse_##suffix) \ + { \ + arm_fir_sparse_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_sparse_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n" \ + "Tap Delay: %d\n", \ + (int)blockSize, \ + (int)numTaps, \ + (int)FILTERING_MAX_TAP_DELAY); \ + \ + /* Initialize the FIR Instances */ \ + arm_fir_sparse_init_##suffix( \ + &fir_inst_fut, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, \ + (int32_t*)filtering_tap_delay, \ + FILTERING_MAX_TAP_DELAY, blockSize); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir_sparse_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + (void *) filtering_scratch, \ + blockSize)); \ + \ + arm_fir_sparse_init_##suffix( \ + &fir_inst_ref, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, \ + (int32_t*)filtering_tap_delay, \ + FILTERING_MAX_TAP_DELAY, blockSize); \ + \ + ref_fir_sparse_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + (void *) filtering_scratch, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +#define FIR_SPARSE2_DEFINE_TEST(suffix, output_type) \ + JTEST_DEFINE_TEST(arm_fir_sparse_##suffix##_test, \ + arm_fir_sparse_##suffix) \ + { \ + arm_fir_sparse_instance_##suffix fir_inst_fut = { 0 }; \ + arm_fir_sparse_instance_##suffix fir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n" \ + "Tap Delay: %d\n", \ + (int)blockSize, \ + (int)numTaps, \ + (int)FILTERING_MAX_TAP_DELAY); \ + \ + /* Initialize the FIR Instances */ \ + arm_fir_sparse_init_##suffix( \ + &fir_inst_fut, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, \ + (int32_t*)filtering_tap_delay, \ + FILTERING_MAX_TAP_DELAY, blockSize); \ + \ + JTEST_COUNT_CYCLES( \ + arm_fir_sparse_##suffix( \ + &fir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + (void *) filtering_scratch, \ + (void *) filtering_scratch2, \ + blockSize)); \ + \ + arm_fir_sparse_init_##suffix( \ + &fir_inst_ref, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, \ + (int32_t*)filtering_tap_delay, \ + FILTERING_MAX_TAP_DELAY, blockSize); \ + \ + ref_fir_sparse_##suffix( \ + &fir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + (void *) filtering_scratch, \ + (void *) filtering_scratch2, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +FIR_DEFINE_TEST(f32,,float32_t); +FIR_DEFINE_TEST(q31,,q31_t); +FIR_DEFINE_TEST(q15,,q15_t); +FIR_DEFINE_TEST(q31,_fast,q31_t); +FIR_DEFINE_TEST(q15,_fast,q15_t); +FIR_DEFINE_TEST(q7,,q7_t); + +FIR_LATTICE_DEFINE_TEST(f32,float32_t); +FIR_LATTICE_DEFINE_TEST(q31,q31_t); +FIR_LATTICE_DEFINE_TEST(q15,q15_t); + +FIR_INTERPOLATE_DEFINE_TEST(f32,float32_t); +FIR_INTERPOLATE_DEFINE_TEST(q31,q31_t); +FIR_INTERPOLATE_DEFINE_TEST(q15,q15_t); + +FIR_DECIMATE_DEFINE_TEST(f32,,float32_t); +FIR_DECIMATE_DEFINE_TEST(q31,,q31_t); +FIR_DECIMATE_DEFINE_TEST(q15,,q15_t); +FIR_DECIMATE_DEFINE_TEST(q31,_fast,q31_t); +FIR_DECIMATE_DEFINE_TEST(q15,_fast,q15_t); + +FIR_SPARSE_DEFINE_TEST(f32,float32_t); +FIR_SPARSE_DEFINE_TEST(q31,q31_t); +FIR_SPARSE2_DEFINE_TEST(q15,q15_t); +FIR_SPARSE2_DEFINE_TEST(q7,q7_t); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(fir_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_fir_f32_test); + JTEST_TEST_CALL(arm_fir_q31_test); + JTEST_TEST_CALL(arm_fir_q15_test); + JTEST_TEST_CALL(arm_fir_q7_test); + JTEST_TEST_CALL(arm_fir_fast_q31_test); + JTEST_TEST_CALL(arm_fir_fast_q15_test); + + JTEST_TEST_CALL(arm_fir_lattice_f32_test); + JTEST_TEST_CALL(arm_fir_lattice_q31_test); + JTEST_TEST_CALL(arm_fir_lattice_q15_test); + + JTEST_TEST_CALL(arm_fir_interpolate_f32_test); + JTEST_TEST_CALL(arm_fir_interpolate_q31_test); + JTEST_TEST_CALL(arm_fir_interpolate_q15_test); + + JTEST_TEST_CALL(arm_fir_decimate_f32_test); + JTEST_TEST_CALL(arm_fir_decimate_q31_test); + JTEST_TEST_CALL(arm_fir_decimate_q15_test); + JTEST_TEST_CALL(arm_fir_decimate_fast_q31_test); + JTEST_TEST_CALL(arm_fir_decimate_fast_q15_test); + + JTEST_TEST_CALL(arm_fir_sparse_f32_test); + JTEST_TEST_CALL(arm_fir_sparse_q31_test); + JTEST_TEST_CALL(arm_fir_sparse_q15_test); + JTEST_TEST_CALL(arm_fir_sparse_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.c new file mode 100644 index 0000000..8d31c3f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.c @@ -0,0 +1,76 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +#define IIR_DEFINE_TEST(suffix, output_type) \ + JTEST_DEFINE_TEST(arm_iir_lattice_##suffix##_test, \ + arm_iir_lattice_##suffix) \ + { \ + arm_iir_lattice_instance_##suffix iir_inst_fut = { 0 }; \ + arm_iir_lattice_instance_##suffix iir_inst_ref = { 0 }; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, filtering_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numstages_idx, uint16_t, numStages, filtering_numstages \ + , \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Stages: %d\n", \ + (int)blockSize, \ + (int)numStages); \ + \ + /* Initialize the IIR Instances */ \ + arm_iir_lattice_init_##suffix( \ + &iir_inst_fut, numStages, (output_type*)filtering_coeffs_b_##suffix, \ + (output_type*)filtering_coeffs_c_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + JTEST_COUNT_CYCLES( \ + arm_iir_lattice_##suffix( \ + &iir_inst_fut, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_fut, \ + blockSize)); \ + \ + arm_iir_lattice_init_##suffix( \ + &iir_inst_ref, numStages, (output_type*)filtering_coeffs_b_##suffix, \ + (output_type*)filtering_coeffs_c_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + ref_iir_lattice_##suffix( \ + &iir_inst_ref, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_output_ref, \ + blockSize); \ + \ + FILTERING_SNR_COMPARE_INTERFACE( \ + blockSize, \ + output_type))); \ + \ + return JTEST_TEST_PASSED; \ + } + +IIR_DEFINE_TEST(f32, float32_t); +IIR_DEFINE_TEST(q31, q31_t); +IIR_DEFINE_TEST(q15, q15_t); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(iir_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_iir_lattice_f32_test); + JTEST_TEST_CALL(arm_iir_lattice_q31_test); + JTEST_TEST_CALL(arm_iir_lattice_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.c new file mode 100644 index 0000000..06e96b6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.c @@ -0,0 +1,219 @@ +#include "jtest.h" +#include "filtering_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "filtering_templates.h" +#include "type_abbrev.h" + +static const float32_t mu_f32 = 0.00854f;//1.0f; +static const float32_t mu2_f32 = 1.0f; +static const q31_t mu_q31 = 0x7fffffff; +static const q15_t mu_q15 = 0x7fff; + +#define LMS_DEFINE_TEST(suffix, config_suffix, output_type, mu) \ + JTEST_DEFINE_TEST(arm_lms##config_suffix##_##suffix##_test, \ + arm_lms##config_suffix##_##suffix) \ + { \ + arm_lms##config_suffix##_instance_##suffix lms_inst_fut = { 0 }; \ + arm_lms##config_suffix##_instance_##suffix lms_inst_ref = { 0 }; \ + arm_fir_instance_##suffix fir_inst = { 0 }; \ + uint32_t i; \ + \ + TEMPLATE_DO_ARR_DESC( \ + blocksize_idx, uint32_t, blockSize, lms_blocksizes \ + , \ + TEMPLATE_DO_ARR_DESC( \ + numtaps_idx, uint16_t, numTaps, filtering_numtaps \ + , \ + /* Initialize the FIR Instances */ \ + arm_fir_init_##suffix( \ + &fir_inst, numTaps, \ + (output_type*)filtering_coeffs_##suffix, \ + (void *) filtering_pState, blockSize); \ + \ + ref_fir_##suffix( \ + &fir_inst, \ + (void *) filtering_##suffix##_inputs, \ + (void *) filtering_input_lms, \ + blockSize); \ + \ + for(i=0;i> 6; \ + } \ + \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Number of Taps: %d\n" \ + "Post Shift: %d\n", \ + (int)blockSize, \ + (int)numTaps, \ + (int)postShift); \ + \ + /* Initialize the LMS Instances */ \ + arm_lms##config_suffix##_init_##suffix( \ + &lms_inst_fut, numTaps, \ + (output_type*)filtering_coeffs_lms, \ + (void *) filtering_pState, mu_##suffix, blockSize, postShift); \ + \ + JTEST_COUNT_CYCLES( \ + arm_lms##config_suffix##_##suffix( \ + &lms_inst_fut, \ + (void *) filtering_output_f32_fut, \ + (void *) filtering_input_lms, \ + (void *) filtering_output_fut, \ + (void *) ((output_type*)filtering_output_fut+blockSize), \ + blockSize)); \ + \ + for(i=0;i= 6010050) +asm(" .global __ARM_use_no_argv\n"); +#endif + + +void debug_init(void) +{ + uint32_t * SHCSR_ptr = (uint32_t *) 0xE000ED24; /* System Handler Control and State Register */ + *SHCSR_ptr |= 0x70000; /* Enable UsageFault, BusFault, and MemManage fault*/ +} + +int main(void) +{ + debug_init(); + + JTEST_INIT(); /* Initialize test framework. */ + + JTEST_GROUP_CALL(all_tests); /* Run all tests. */ + + JTEST_ACT_EXIT_FW(); /* Exit test framework. */ + while (1); /* Never return. */ +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c new file mode 100644 index 0000000..ef09e40 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c @@ -0,0 +1,491 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param float* Pointer to the reference buffer + * @param float* Pointer to the test buffer + * @param uint32_t total number of samples + * @return float SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10f (EnergySignal / EnergyError); + + return (SNR); + +} + + + +double arm_snr_f64(double *pRef, double *pTest, uint32_t buffSize) +{ + double EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + double SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + +/** + * @brief Provide guard bits for Input buffer + * @param q15_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param q15_t* Pointer to Ref buffer + * @param q15_t* Pointer to Test buffer + * @param uint32_t number of samples in the buffer + * @return none + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param q31_t* Pointer to Ref buffer + * @param q31_t* Pointer to Test buffer + * @param uint32_t number of samples in the buffer + * @return none + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param q31_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param q31_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param uint32_t number of additions + * @return none + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Converts Q15 to floating-point + * @param uint32_t number of samples in the buffer + * @return none + */ + +void arm_apply_guard_bits (float32_t * pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param uint32_t number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param pIn input buffer + * @param numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.c new file mode 100644 index 0000000..c536899 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.c @@ -0,0 +1,31 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_ADD_TEST(suffix) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \ + mat_add, \ + suffix, \ + MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT, \ + MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS, \ + MATRIX_COMPARE_INTERFACE) + +JTEST_ARM_MAT_ADD_TEST(f32); +JTEST_ARM_MAT_ADD_TEST(q31); +JTEST_ARM_MAT_ADD_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_add_tests) +{ + JTEST_TEST_CALL(arm_mat_add_f32_test); + JTEST_TEST_CALL(arm_mat_add_q31_test); + JTEST_TEST_CALL(arm_mat_add_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c new file mode 100644 index 0000000..50cd57e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c @@ -0,0 +1,59 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_CMPLX_MULT_TEST(suffix, comparison_interface) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \ + mat_cmplx_mult, \ + suffix, \ + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, \ + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, \ + comparison_interface) + +JTEST_ARM_MAT_CMPLX_MULT_TEST(f32, MATRIX_SNR_COMPARE_INTERFACE); +JTEST_ARM_MAT_CMPLX_MULT_TEST(q31, MATRIX_COMPARE_INTERFACE); + +/*--------------------------------------------------------------------------------*/ +/* Q15 Uses a Different interface than the others. */ +/*--------------------------------------------------------------------------------*/ + +#define ARM_mat_cmplx_mult_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, \ + (void *) &matrix_output_fut, \ + (q15_t *) matrix_output_scratch) + +JTEST_DEFINE_TEST(arm_mat_cmplx_mult_q15_test, arm_mat_cmplx_mult_q15) +{ + MATRIX_TEST_TEMPLATE_ELT2( + matrix_q15_a_inputs, + matrix_q15_b_inputs, + arm_matrix_instance_q15 * , + arm_matrix_instance_q15, + TYPE_FROM_ABBREV(q15), + arm_mat_cmplx_mult_q15, + ARM_mat_cmplx_mult_q15_INPUT_INTERFACE, + ref_mat_cmplx_mult_q15, + REF_mat_cmplx_mult_INPUT_INTERFACE, + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, + MATRIX_COMPARE_INTERFACE); +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_cmplx_mult_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_cmplx_mult_f32_test); + JTEST_TEST_CALL(arm_mat_cmplx_mult_q31_test); + JTEST_TEST_CALL(arm_mat_cmplx_mult_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.c new file mode 100644 index 0000000..7d879ee --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.c @@ -0,0 +1,58 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_INIT_TEST(suffix) \ + JTEST_DEFINE_TEST(arm_mat_init_##suffix##_test, \ + arm_mat_init_##suffix) \ + { \ + const uint16_t rows = 4; \ + const uint16_t cols = 2; \ + arm_matrix_instance_##suffix matrix = {0}; \ + /* TYPE_FROM_ABBREV(suffix) data[rows*cols] = {0}; */ \ + TYPE_FROM_ABBREV(suffix) data[4*2] = {0}; \ + \ + arm_mat_init_##suffix(&matrix, \ + rows, \ + cols, \ + data); \ + \ + JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", \ + (int)matrix.numRows, \ + (int)matrix.numCols); \ + \ + if ((matrix.numRows == rows) && \ + (matrix.numCols == cols) && \ + (matrix.pData == data)) \ + { \ + return JTEST_TEST_PASSED; \ + } \ + else \ + { \ + return JTEST_TEST_FAILED; \ + } \ + \ + } + +JTEST_ARM_MAT_INIT_TEST(f32); +JTEST_ARM_MAT_INIT_TEST(q31); +JTEST_ARM_MAT_INIT_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_init_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_init_f32_test); + JTEST_TEST_CALL(arm_mat_init_q31_test); + JTEST_TEST_CALL(arm_mat_init_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c new file mode 100644 index 0000000..372ac1d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c @@ -0,0 +1,92 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +JTEST_DEFINE_TEST(arm_mat_inverse_f32_test, arm_mat_inverse_f32) +{ + TEMPLATE_DO_ARR_DESC( + mat_idx, arm_matrix_instance_f32 *, mat_ptr, matrix_f32_invertible_inputs + , + JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", + (int)mat_ptr->numRows, + (int)mat_ptr->numCols); + + if (MATRIX_TEST_VALID_SQUARE_DIMENSIONS(arm_matrix_instance_f32 *, mat_ptr)) + { + MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f32 *, mat_ptr); + + /* arm_mat_inverse_f32() modifies its source input. Use the scratch + * buffer to store a copy of the intended input. */ + { + float32_t * original_pdata_ptr = mat_ptr->pData; + + memcpy(matrix_output_scratch, + mat_ptr->pData, + mat_ptr->numRows * mat_ptr->numCols * sizeof(float32_t)); + mat_ptr->pData = (void*) &matrix_output_scratch; + + JTEST_COUNT_CYCLES(arm_mat_inverse_f32(mat_ptr, &matrix_output_fut)); + mat_ptr->pData = original_pdata_ptr; + } + + ref_mat_inverse_f32(mat_ptr, &matrix_output_ref); + + MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_f32, + float32_t); + }); + + return JTEST_TEST_PASSED; +} + +JTEST_DEFINE_TEST(arm_mat_inverse_f64_test, arm_mat_inverse_f64) +{ + TEMPLATE_DO_ARR_DESC( + mat_idx, arm_matrix_instance_f64 *, mat_ptr, matrix_f64_invertible_inputs + , + JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", + (int)mat_ptr->numRows, + (int)mat_ptr->numCols); + + if (MATRIX_TEST_VALID_SQUARE_DIMENSIONS(arm_matrix_instance_f64 *, mat_ptr)) + { + MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f64 *, mat_ptr); + + /* arm_mat_inverse_f64() modifies its source input. Use the scratch + * buffer to store a copy of the intended input. */ + { + float64_t * original_pdata_ptr = mat_ptr->pData; + + memcpy(matrix_output_scratch, + mat_ptr->pData, + mat_ptr->numRows * mat_ptr->numCols * sizeof(float64_t)); + mat_ptr->pData = (void*) &matrix_output_scratch; + + JTEST_COUNT_CYCLES(arm_mat_inverse_f64(mat_ptr, &matrix_output_fut64)); + mat_ptr->pData = original_pdata_ptr; + } + + ref_mat_inverse_f64(mat_ptr, &matrix_output_ref64); + + MATRIX_DBL_SNR_COMPARE_INTERFACE(arm_matrix_instance_f64); + }); + + return JTEST_TEST_PASSED; +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_inverse_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_inverse_f32_test); + JTEST_TEST_CALL(arm_mat_inverse_f64_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c new file mode 100644 index 0000000..313aa04 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c @@ -0,0 +1,57 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_MULT_FAST_TEST(suffix) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \ + mat_mult_fast, \ + suffix, \ + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, \ + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, \ + MATRIX_SNR_COMPARE_INTERFACE) + +JTEST_ARM_MAT_MULT_FAST_TEST(q31); + +/*--------------------------------------------------------------------------------*/ +/* Q15 Uses a Different interface than the others. */ +/*--------------------------------------------------------------------------------*/ + +#define ARM_mat_mult_fast_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, \ + (void *) &matrix_output_fut, \ + (q15_t *) matrix_output_scratch) + +JTEST_DEFINE_TEST(arm_mat_mult_fast_q15_test, arm_mat_mult_fast_q15) +{ + MATRIX_TEST_TEMPLATE_ELT2( + matrix_q15_a_inputs, + matrix_q15_b_inputs, + arm_matrix_instance_q15 * , + arm_matrix_instance_q15, + TYPE_FROM_ABBREV(q15), + arm_mat_mult_fast_q15, + ARM_mat_mult_fast_q15_INPUT_INTERFACE, + ref_mat_mult_fast_q15, + REF_mat_mult_fast_INPUT_INTERFACE, + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, + MATRIX_SNR_COMPARE_INTERFACE); +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_mult_fast_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_mult_fast_q31_test); + JTEST_TEST_CALL(arm_mat_mult_fast_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.c new file mode 100644 index 0000000..c74bdc8 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.c @@ -0,0 +1,59 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_MULT_TEST(suffix) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \ + mat_mult, \ + suffix, \ + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, \ + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, \ + MATRIX_COMPARE_INTERFACE) + +JTEST_ARM_MAT_MULT_TEST(f32); +JTEST_ARM_MAT_MULT_TEST(q31); + +/*--------------------------------------------------------------------------------*/ +/* Q15 Uses a Different interface than the others. */ +/*--------------------------------------------------------------------------------*/ + +#define ARM_mat_mult_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \ + PAREN(input_a_ptr, input_b_ptr, \ + (void *) &matrix_output_fut, \ + (q15_t *) matrix_output_scratch) + +JTEST_DEFINE_TEST(arm_mat_mult_q15_test, arm_mat_mult_q15) +{ + MATRIX_TEST_TEMPLATE_ELT2( + matrix_q15_a_inputs, + matrix_q15_b_inputs, + arm_matrix_instance_q15 * , + arm_matrix_instance_q15, + TYPE_FROM_ABBREV(q15), + arm_mat_mult_q15, + ARM_mat_mult_q15_INPUT_INTERFACE, + ref_mat_mult_q15, + REF_mat_mult_INPUT_INTERFACE, + MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT, + MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS, + MATRIX_COMPARE_INTERFACE); +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_mult_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_mult_f32_test); + JTEST_TEST_CALL(arm_mat_mult_q31_test); + JTEST_TEST_CALL(arm_mat_mult_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.c new file mode 100644 index 0000000..63fba94 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.c @@ -0,0 +1,90 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +/* This is for the two fixed point cases */ +#define JTEST_ARM_MAT_SCALE_TEST(suffix,type) \ + JTEST_DEFINE_TEST(arm_mat_scale_##suffix##_test, arm_mat_scale_##suffix) \ + { \ + uint32_t i,j; \ + \ + TEMPLATE_DO_ARR_DESC( \ + mat_idx, arm_matrix_instance_##suffix *, \ + mat_ptr, matrix_##suffix##_b_inputs \ + , \ + MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT( \ + arm_matrix_instance_##suffix *, mat_ptr); \ + \ + for(i=0;inumRows, \ + (int)mat_ptr->numCols); \ + \ + JTEST_COUNT_CYCLES( \ + arm_mat_scale_##suffix(mat_ptr, \ + matrix_##suffix##_scale_values[i], \ + matrix_shift_values[j], \ + (arm_matrix_instance_##suffix*) &matrix_output_fut)); \ + \ + ref_mat_scale_##suffix(mat_ptr, \ + matrix_##suffix##_scale_values[i], \ + matrix_shift_values[j], \ + (arm_matrix_instance_##suffix*) &matrix_output_ref); \ + \ + MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_##suffix, \ + type); \ + } \ + }); \ + \ + return JTEST_TEST_PASSED; \ + } + +JTEST_DEFINE_TEST(arm_mat_scale_f32_test, arm_mat_scale_f32) +{ + uint32_t i; + + TEMPLATE_DO_ARR_DESC( + mat_idx, arm_matrix_instance_f32 *, mat_ptr, matrix_f32_b_inputs + , + MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f32 *, mat_ptr); + + for(i=0;inumRows, + (int)mat_ptr->numCols); + JTEST_COUNT_CYCLES(arm_mat_scale_f32(mat_ptr, matrix_f32_scale_values[i], &matrix_output_fut)); + + ref_mat_scale_f32(mat_ptr, matrix_f32_scale_values[i], &matrix_output_ref); + + MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_f32, + float32_t); + }); + + return JTEST_TEST_PASSED; +} + +JTEST_ARM_MAT_SCALE_TEST(q31,q31_t); +JTEST_ARM_MAT_SCALE_TEST(q15,q15_t); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_scale_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_scale_f32_test); + JTEST_TEST_CALL(arm_mat_scale_q31_test); + JTEST_TEST_CALL(arm_mat_scale_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c new file mode 100644 index 0000000..245c28e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c @@ -0,0 +1,34 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_SUB_TEST(suffix) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT2( \ + mat_sub, \ + suffix, \ + MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT, \ + MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS, \ + MATRIX_COMPARE_INTERFACE) + +JTEST_ARM_MAT_SUB_TEST(f32); +JTEST_ARM_MAT_SUB_TEST(q31); +JTEST_ARM_MAT_SUB_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_sub_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_sub_f32_test); + JTEST_TEST_CALL(arm_mat_sub_q31_test); + JTEST_TEST_CALL(arm_mat_sub_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.c new file mode 100644 index 0000000..e49c80b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "matrix_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "matrix_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAT_TRANS_TEST(suffix) \ + MATRIX_DEFINE_TEST_TEMPLATE_ELT1( \ + mat_trans, \ + suffix, \ + MATRIX_TEST_CONFIG_TRANSPOSE_OUTPUT, \ + MATRIX_TEST_VALID_DIMENSIONS_ALWAYS) + +JTEST_ARM_MAT_TRANS_TEST(f32); +JTEST_ARM_MAT_TRANS_TEST(q31); +JTEST_ARM_MAT_TRANS_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mat_trans_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mat_trans_f32_test); + JTEST_TEST_CALL(arm_mat_trans_q31_test); + JTEST_TEST_CALL(arm_mat_trans_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c new file mode 100644 index 0000000..033fe10 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c @@ -0,0 +1,255 @@ +#include "arm_math.h" +#include "matrix_test_data.h" +#include "type_abbrev.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_fut_data[2*MATRIX_TEST_MAX_ELTS] = {0}; +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_ref_data[2*MATRIX_TEST_MAX_ELTS] = {0}; +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_scratch[MATRIX_TEST_MAX_ELTS] = {0}; + +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_fut[MATRIX_TEST_MAX_ELTS]; +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_ref[MATRIX_TEST_MAX_ELTS]; + +arm_matrix_instance_f32 matrix_output_fut = { + 0, + 0, + (float32_t *) &matrix_output_fut_data +}; + +arm_matrix_instance_f32 matrix_output_ref = { + 0, + 0, + (float32_t *) &matrix_output_ref_data +}; + +arm_matrix_instance_f64 matrix_output_fut64 = { + 0, + 0, + (float64_t *) &matrix_output_fut_data +}; + +arm_matrix_instance_f64 matrix_output_ref64 = { + 0, + 0, + (float64_t *) &matrix_output_ref_data +}; + +/*--------------------------------------------------------------------------------*/ +/* Data Buckets */ +/*--------------------------------------------------------------------------------*/ + +/** + * Pool of random data to base matrix inputs from. + */ +float32_t matrix_f32_100_rand[100] = { + -45.0345569674258, -11.0261163038747, -14.6841428777929, + 0.0345569674258, -11.0261163038747, -14.6841428777929, + -20.3679194392227, 27.5712678608402, -12.1390617339732, + -19.8753669720509, 42.3379642103244, -23.7788252219155, + -23.7517765301667, 40.2716109915281, -25.8308714086167, + 32.1194040197959, 24.4692807074156, -1.32083675968276, + 31.1580458282477, -2.90766514824093, -6.97926086704160, + 10.2843089382083, 30.1014622769739, 44.4787189721646, + -9.60878544118853, -48.4596562348445, -31.1044984967456, + -6.41414114190809, 3.28255887994549, -26.9511839788442, + -31.5183679875864, 21.1215780433683, -47.0779722437854, + -0.913590753192006, -40.3545474831611, -45.6976198342192, + 18.6775433365315, -5.32162505701938, -14.9272896423117, + 34.4308792695389, 40.4880968679893, -27.8253265982760, + 42.8854139478045, -1.07473615999811, -36.8026707393665, + -33.1009970537296, -31.6488844262730, -19.3650527983443, + 43.9001561999887, -30.5235710432951, 47.9748378356085, + -38.2582349144194, 23.0330862855453, -16.2280590178623, + 44.2050590775485, 14.9115474956452, -13.1515403509664, + 0.850865538112700, 37.5942811492984, -27.4078219027601, + -6.11300268738968, -20.3324126781673, -1.13910261964209, + 40.0053846417662, 45.6134540229802, 23.1722385658670, + 12.5618560729690, 1.07715641721097, 5.01563428984222, + -32.9291952852141, -38.8880776559401, -18.1221698074118, + 7.85250610234389, -13.0753218879785, 7.52085950784656, + 14.7745963136307, 28.0227435151377, 31.7627708322262, + 12.2475086001227, -27.2335702183447, -24.1935304087933, + -7.58332402861928, -26.2716420228479, -38.8797244706213, + -44.0220457052844, -4.90762935690551, -41.8874231134215, + 29.4831416883453, 8.70447045314168, -6.43013158961009, + -9.12801538874479, 0.785828466111815, -4.11511718200689, + 28.0252068321138, -26.5220086627594, 4.70088922863450, + 42.9385970968730, 14.4318130193692, -29.2257707266972, + 46.3088539286913 +}; + +float64_t matrix_f64_100_rand[100] = { + -45.0345569674258, -11.0261163038747, -14.6841428777929, + 0.0345569674258, -11.0261163038747, -14.6841428777929, + -20.3679194392227, 27.5712678608402, -12.1390617339732, + -19.8753669720509, 42.3379642103244, -23.7788252219155, + -23.7517765301667, 40.2716109915281, -25.8308714086167, + 32.1194040197959, 24.4692807074156, -1.32083675968276, + 31.1580458282477, -2.90766514824093, -6.97926086704160, + 10.2843089382083, 30.1014622769739, 44.4787189721646, + -9.60878544118853, -48.4596562348445, -31.1044984967456, + -6.41414114190809, 3.28255887994549, -26.9511839788442, + -31.5183679875864, 21.1215780433683, -47.0779722437854, + -0.913590753192006, -40.3545474831611, -45.6976198342192, + 18.6775433365315, -5.32162505701938, -14.9272896423117, + 34.4308792695389, 40.4880968679893, -27.8253265982760, + 42.8854139478045, -1.07473615999811, -36.8026707393665, + -33.1009970537296, -31.6488844262730, -19.3650527983443, + 43.9001561999887, -30.5235710432951, 47.9748378356085, + -38.2582349144194, 23.0330862855453, -16.2280590178623, + 44.2050590775485, 14.9115474956452, -13.1515403509664, + 0.850865538112700, 37.5942811492984, -27.4078219027601, + -6.11300268738968, -20.3324126781673, -1.13910261964209, + 40.0053846417662, 45.6134540229802, 23.1722385658670, + 12.5618560729690, 1.07715641721097, 5.01563428984222, + -32.9291952852141, -38.8880776559401, -18.1221698074118, + 7.85250610234389, -13.0753218879785, 7.52085950784656, + 14.7745963136307, 28.0227435151377, 31.7627708322262, + 12.2475086001227, -27.2335702183447, -24.1935304087933, + -7.58332402861928, -26.2716420228479, -38.8797244706213, + -44.0220457052844, -4.90762935690551, -41.8874231134215, + 29.4831416883453, 8.70447045314168, -6.43013158961009, + -9.12801538874479, 0.785828466111815, -4.11511718200689, + 28.0252068321138, -26.5220086627594, 4.70088922863450, + 42.9385970968730, 14.4318130193692, -29.2257707266972, + 46.3088539286913 +}; + +MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_zeros[MATRIX_TEST_MAX_ELTS] = {0}; + +const float32_t matrix_f32_scale_values[MATRIX_MAX_COEFFS_LEN] = +{ + 43.0264275639 , -17.0525215570 , -94.8488973910 , -8.1924989580 , + 7.2830326091 , 66.8368719314 , 33.9778190671 , 117.8652289772 , + -129.6077797465, -14.6420815368 , 18.0239223278 , 1.0000000000 , + 55.0375037651 , 1.8674609862 , 0.00000000000 , -33.5750364909 +}; + +const q31_t matrix_q31_scale_values[MATRIX_MAX_COEFFS_LEN] = +{ + 0x0201DC90, 0x211F0D7C, 0x80000000, 0xF573B824, + 0xE85ED05B, 0x311DFB52, 0x3529E750, 0x00000000, + 0x7FFFFFFF, 0x21FA525A, 0x0971FD45, 0x05547B68, + 0x270C6366, 0x06FDD5A6, 0xF7025315, 0xB1155A1E +}; + +const q15_t matrix_q15_scale_values[MATRIX_MAX_COEFFS_LEN] = +{ + 0x0201, 0x211F, 0x8000, 0xF573, + 0xE85E, 0x311D, 0x3529, 0x0000, + 0x7FFF, 0x21FA, 0x0971, 0x0554, + 0x270C, 0x06FD, 0xF702, 0xB115 +}; + +const int32_t matrix_shift_values[MATRIX_MAX_SHIFTS_LEN] = +{ + -16, -7, 0, 7, 16 +}; + +/*--------------------------------------------------------------------------------*/ +/* Matrix Definitions */ +/*--------------------------------------------------------------------------------*/ + +/** + * Define matrices by suffix (f32, q31, q15) for use in test cases. + * + * The rand1 and rand2 suffixes get their data from the same pool of random + * data, but their starting points differ by 1 element. + * + * Makes available: + * - matrix_`suffix`_1x1_rand1/2 + * - matrix_`suffix`_1x4_rand1/2 + * - matrix_`suffix`_2x4_rand1/2 + * - matrix_`suffix`_4x4_rand1/2 + */ +#define MATRIX_DEFINE_MATRICES(suffix) \ + arm_matrix_instance_##suffix matrix_##suffix##_1x1_rand1 = \ + {1, 1, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \ + arm_matrix_instance_##suffix matrix_##suffix##_1x1_rand2 = \ + {1, 1, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \ + arm_matrix_instance_##suffix matrix_##suffix##_1x1_zeros = \ + {1, 1, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros}; \ + \ + arm_matrix_instance_##suffix matrix_##suffix##_1x4_rand1 = \ + {1, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \ + arm_matrix_instance_##suffix matrix_##suffix##_1x4_rand2 = \ + {1, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \ + arm_matrix_instance_##suffix matrix_##suffix##_1x4_zeros = \ + {1, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros}; \ + \ + arm_matrix_instance_##suffix matrix_##suffix##_2x4_rand1 = \ + {2, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \ + arm_matrix_instance_##suffix matrix_##suffix##_2x4_rand2 = \ + {2, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \ + arm_matrix_instance_##suffix matrix_##suffix##_2x4_zeros = \ + {2, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros}; \ + \ + arm_matrix_instance_##suffix matrix_##suffix##_4x4_rand1 = \ + {4, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand }; \ + arm_matrix_instance_##suffix matrix_##suffix##_4x4_rand2 = \ + {4, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \ + arm_matrix_instance_##suffix matrix_##suffix##_4x4_zeros = \ + {4, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros} + +MATRIX_DEFINE_MATRICES(f64); +MATRIX_DEFINE_MATRICES(f32); +MATRIX_DEFINE_MATRICES(q31); +MATRIX_DEFINE_MATRICES(q15); + +/*--------------------------------------------------------------------------------*/ +/* Matrix-Input Arrays */ +/*--------------------------------------------------------------------------------*/ + +/* Define Input #ARR_DESC_t by suffix. + * + * Taking inputs in parallel from the 'a' and 'b' arrays yields the following + * test cases: + * - 1x1 multiplication by zero + * - 1x1 multiplication between random numbers + * - 1x1 * 1x4 valid dimension interaction + * - 1x1 * 2x4 invalid dimension interaction + * - 2x4 * 4x4 larger valid dimension interaction + * - 4x4 * 4x4 larger valid dimension interaction + */ +#define MATRIX_DEFINE_INPUTS(suffix) \ + ARR_DESC_DEFINE(arm_matrix_instance_##suffix *, \ + matrix_##suffix##_a_inputs, \ + 6, \ + CURLY( \ + &matrix_##suffix##_1x1_rand1, \ + &matrix_##suffix##_1x1_rand1, \ + &matrix_##suffix##_1x1_rand1, \ + &matrix_##suffix##_1x1_rand1, \ + &matrix_##suffix##_2x4_rand1, \ + &matrix_##suffix##_4x4_rand1 \ + )); \ + \ + ARR_DESC_DEFINE(arm_matrix_instance_##suffix *, \ + matrix_##suffix##_b_inputs, \ + 6, \ + CURLY( \ + &matrix_##suffix##_1x1_zeros, \ + &matrix_##suffix##_1x1_rand2, \ + &matrix_##suffix##_1x4_rand2, \ + &matrix_##suffix##_2x4_rand2, \ + &matrix_##suffix##_4x4_rand2, \ + &matrix_##suffix##_4x4_rand2 \ + )); \ + \ + ARR_DESC_DEFINE(arm_matrix_instance_##suffix *, \ + matrix_##suffix##_invertible_inputs, \ + 4, \ + CURLY( \ + &matrix_##suffix##_1x1_rand1, \ + &matrix_##suffix##_1x1_rand2, \ + &matrix_##suffix##_4x4_rand1, \ + &matrix_##suffix##_4x4_rand2 \ + )) \ + +MATRIX_DEFINE_INPUTS(f64); +MATRIX_DEFINE_INPUTS(f32); +MATRIX_DEFINE_INPUTS(q31); +MATRIX_DEFINE_INPUTS(q15); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c new file mode 100644 index 0000000..c87439d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c @@ -0,0 +1,19 @@ +#include "jtest.h" +#include "matrix_tests.h" + +JTEST_DEFINE_GROUP(matrix_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_GROUP_CALL(mat_add_tests); + JTEST_GROUP_CALL(mat_cmplx_mult_tests); + JTEST_GROUP_CALL(mat_init_tests); + JTEST_GROUP_CALL(mat_inverse_tests); + JTEST_GROUP_CALL(mat_mult_tests); + JTEST_GROUP_CALL(mat_mult_fast_tests); + JTEST_GROUP_CALL(mat_sub_tests); + JTEST_GROUP_CALL(mat_trans_tests); + JTEST_GROUP_CALL(mat_scale_tests); + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c new file mode 100644 index 0000000..d60973b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c @@ -0,0 +1,36 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MAX_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + max, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_COMPARE_INTERFACE) + +JTEST_ARM_MAX_TEST(f32); +JTEST_ARM_MAX_TEST(q31); +JTEST_ARM_MAX_TEST(q15); +JTEST_ARM_MAX_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(max_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_max_f32_test); + JTEST_TEST_CALL(arm_max_q31_test); + JTEST_TEST_CALL(arm_max_q15_test); + JTEST_TEST_CALL(arm_max_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.c new file mode 100644 index 0000000..291c10a --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.c @@ -0,0 +1,36 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MEAN_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + mean, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_COMPARE_INTERFACE) + +JTEST_ARM_MEAN_TEST(f32); +JTEST_ARM_MEAN_TEST(q31); +JTEST_ARM_MEAN_TEST(q15); +JTEST_ARM_MEAN_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(mean_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_mean_f32_test); + JTEST_TEST_CALL(arm_mean_q31_test); + JTEST_TEST_CALL(arm_mean_q15_test); + JTEST_TEST_CALL(arm_mean_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c new file mode 100644 index 0000000..9d831d0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c @@ -0,0 +1,36 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_MIN_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + min, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_COMPARE_INTERFACE) + +JTEST_ARM_MIN_TEST(f32); +JTEST_ARM_MIN_TEST(q31); +JTEST_ARM_MIN_TEST(q15); +JTEST_ARM_MIN_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(min_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_min_f32_test); + JTEST_TEST_CALL(arm_min_q31_test); + JTEST_TEST_CALL(arm_min_q15_test); + JTEST_TEST_CALL(arm_min_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c new file mode 100644 index 0000000..12c30ea --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c @@ -0,0 +1,36 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_POWER_TEST(suffix, output_type) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + power, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_SNR_COMPARE_INTERFACE) + +JTEST_ARM_POWER_TEST(f32, float32_t); +JTEST_ARM_POWER_TEST(q31, q63_t); +JTEST_ARM_POWER_TEST(q15, q63_t); +JTEST_ARM_POWER_TEST(q7, q31_t); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(power_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_power_f32_test); + JTEST_TEST_CALL(arm_power_q31_test); + JTEST_TEST_CALL(arm_power_q15_test); + JTEST_TEST_CALL(arm_power_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c new file mode 100644 index 0000000..d9b1a24 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c @@ -0,0 +1,34 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_RMS_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + rms, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_SNR_COMPARE_INTERFACE) + +JTEST_ARM_RMS_TEST(f32); +JTEST_ARM_RMS_TEST(q31); +JTEST_ARM_RMS_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(rms_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_rms_f32_test); + JTEST_TEST_CALL(arm_rms_q31_test); + JTEST_TEST_CALL(arm_rms_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c new file mode 100644 index 0000000..ebf4580 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c @@ -0,0 +1,94 @@ +#include "statistics_test_data.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + + +ARR_DESC_DEFINE(STATISTICS_BIGGEST_INPUT_TYPE, + statistics_output_fut, + STATISTICS_MAX_INPUT_ELEMENTS, + CURLY(0)); + +ARR_DESC_DEFINE(STATISTICS_BIGGEST_INPUT_TYPE, + statistics_output_ref, + STATISTICS_MAX_INPUT_ELEMENTS, + CURLY(0)); + +uint32_t statistics_idx_fut = 0; +uint32_t statistics_idx_ref = 0; + +STATISTICS_BIGGEST_INPUT_TYPE +statistics_output_f32_ref[STATISTICS_MAX_INPUT_ELEMENTS]; + +STATISTICS_BIGGEST_INPUT_TYPE +statistics_output_f32_fut[STATISTICS_MAX_INPUT_ELEMENTS]; + +/*--------------------------------------------------------------------------------*/ +/* Block Sizes */ +/*--------------------------------------------------------------------------------*/ + +/* + To change test parameter values add/remove values inside CURLY and update + the preceeding parameter to reflect the number of values inside CURLY. +*/ + +ARR_DESC_DEFINE(uint32_t, + statistics_block_sizes, + 4, + CURLY(1, 2, 15, 32)); + +/*--------------------------------------------------------------------------------*/ +/* Test Data */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(float32_t, + statistics_f_32, + 32, + CURLY( + -0.0865129623056441 , -0.3331168756476194, + 0.0250664612949661 , 0.0575352840717098, + -0.2292942701362928 , 0.2381830931285998, + 0.2378328403304206 , -0.0075266553186635, + 0.0654584722817308 , 0.0349278285641849, + -0.0373417155362879 , 0.1451581096586606, + -0.1176633086028378 , 0.4366371636394202, + -0.0272791766173191 , 0.0227862627041619, + 0.2133536422718378 , 0.0118562921047211, + -0.0191296810967338 , -0.1664698927300045, + 0.0588821632785281 , -0.2672363715875608, + 0.1428649103637904 , 0.3247124128892542, + -0.1383551403404573 , 0.1715993345656525, + 0.2508002843205065 , -0.3187459152894954, + -0.2881928863802040 , 0.1142295247316356, + -0.0799771155430726 , 0.1379994750928690 + )); + + +ARR_DESC_DEFINE_SUBSET(statistics_f_31, + statistics_f_32, + 31); + +ARR_DESC_DEFINE_SUBSET(statistics_f_15, + statistics_f_32, + 15); + +ARR_DESC_DEFINE_SUBSET(statistics_f_2, + statistics_f_32, + 2); + +ARR_DESC_DEFINE(float32_t, + statistics_zeros, + 32, + CURLY(0)); + +/* Aggregate all float datasets */ +ARR_DESC_DEFINE(ARR_DESC_t *, + statistics_f_all, + 4, + CURLY( + &statistics_zeros, + &statistics_f_2, + &statistics_f_15, + &statistics_f_32 + )); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c new file mode 100644 index 0000000..6a610a6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c @@ -0,0 +1,14 @@ +#include "jtest.h" +#include "statistics_tests.h" + +JTEST_DEFINE_GROUP(statistics_tests) +{ + JTEST_GROUP_CALL(max_tests); + JTEST_GROUP_CALL(mean_tests); + JTEST_GROUP_CALL(min_tests); + JTEST_GROUP_CALL(power_tests); + JTEST_GROUP_CALL(rms_tests); + JTEST_GROUP_CALL(std_tests); + JTEST_GROUP_CALL(var_tests); + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.c new file mode 100644 index 0000000..b80ed71 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.c @@ -0,0 +1,34 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_STD_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + std, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_SNR_COMPARE_INTERFACE) + +JTEST_ARM_STD_TEST(f32); +JTEST_ARM_STD_TEST(q31); +JTEST_ARM_STD_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(std_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_std_f32_test); + JTEST_TEST_CALL(arm_std_q31_test); + JTEST_TEST_CALL(arm_std_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c new file mode 100644 index 0000000..3aa7c27 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c @@ -0,0 +1,34 @@ +#include "jtest.h" +#include "statistics_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "statistics_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_VAR_TEST(suffix) \ + STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + var, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + STATISTICS_SNR_COMPARE_INTERFACE) + +JTEST_ARM_VAR_TEST(f32); +JTEST_ARM_VAR_TEST(q31); +JTEST_ARM_VAR_TEST(q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(var_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_var_f32_test); + JTEST_TEST_CALL(arm_var_q31_test); + JTEST_TEST_CALL(arm_var_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c new file mode 100644 index 0000000..3804f63 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c @@ -0,0 +1,33 @@ +#include "jtest.h" +#include "support_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "support_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_COPY_TEST(suffix) \ + SUPPORT_DEFINE_TEST_TEMPLATE_BUF1_BLK( \ + copy, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + SUPPORT_COMPARE_INTERFACE) + +JTEST_ARM_COPY_TEST(f32); +JTEST_ARM_COPY_TEST(q31); +JTEST_ARM_COPY_TEST(q15); +JTEST_ARM_COPY_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(copy_tests) +{ + JTEST_TEST_CALL(arm_copy_f32_test); + JTEST_TEST_CALL(arm_copy_q31_test); + JTEST_TEST_CALL(arm_copy_q15_test); + JTEST_TEST_CALL(arm_copy_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.c new file mode 100644 index 0000000..fc5892d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.c @@ -0,0 +1,36 @@ +#include "jtest.h" +#include "support_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "support_templates.h" +#include "type_abbrev.h" + +#define JTEST_ARM_FILL_TEST(suffix) \ + SUPPORT_DEFINE_TEST_TEMPLATE_ELT1_BLK( \ + fill, \ + suffix, \ + TYPE_FROM_ABBREV(suffix), \ + TYPE_FROM_ABBREV(suffix), \ + SUPPORT_COMPARE_INTERFACE) + +JTEST_ARM_FILL_TEST(f32); +JTEST_ARM_FILL_TEST(q31); +JTEST_ARM_FILL_TEST(q15); +JTEST_ARM_FILL_TEST(q7); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(fill_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_fill_f32_test); + JTEST_TEST_CALL(arm_fill_q31_test); + JTEST_TEST_CALL(arm_fill_q15_test); + JTEST_TEST_CALL(arm_fill_q7_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c new file mode 100644 index 0000000..f4b5911 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c @@ -0,0 +1,85 @@ +#include "arm_math.h" +#include "support_test_data.h" + +#define MAX_INPUT_ELEMENTS 32 +#define BIGGEST_INPUT_TYPE float32_t + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(BIGGEST_INPUT_TYPE, + support_output_fut, + MAX_INPUT_ELEMENTS, + CURLY(0)); + +ARR_DESC_DEFINE(BIGGEST_INPUT_TYPE, + support_output_ref, + MAX_INPUT_ELEMENTS, + CURLY(0)); + +/*--------------------------------------------------------------------------------*/ +/* Block Sizes */ +/*--------------------------------------------------------------------------------*/ + +/* + To change test parameter values add/remove values inside CURLY and update + the preceeding parameter to reflect the number of values inside CURLY. +*/ + +ARR_DESC_DEFINE(uint32_t, + support_block_sizes, + 4, + CURLY( 2, 7, 15, 32)); + +/*--------------------------------------------------------------------------------*/ +/* Numbers */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(uint32_t, + support_elts, + 4, + CURLY( 0, 1, 0x80000000, 0x7fffffff)); + +/*--------------------------------------------------------------------------------*/ +/* Test Data */ +/*--------------------------------------------------------------------------------*/ + +ARR_DESC_DEFINE(float32_t, + support_f_32, + 32, + CURLY( + 0.24865986 , -0.13364227, -0.27233250 , -7.33488200, + 0.42190653 , 1.17435880 , -0.49824914 , 0.87883663, + 0.63066370 , 1.80275680 , -84.83916000, -2.06773800, + 7.63452500 , 1.01487610 , -0.65785825 , 1.78019030, + -0.34160388, 0.68546050 , -1.81721590 , -0.10340453, + -4.48600340, -1.69763480, -1.26022340 , -1.58457480, + 0.51993870 , 2.83526470 , -0.21502694 , -0.57690346, + -0.22945681, 0.79509383 , 0.07275216 , -2.16279080 + )); + +/* Alias the 32 element array with wrappers that end sooner. */ +ARR_DESC_DEFINE_SUBSET(support_f_15, + support_f_32, + 15); + +ARR_DESC_DEFINE_SUBSET(support_f_2, + support_f_32, + 2); + +ARR_DESC_DEFINE(float32_t, + support_zeros, + 32, + CURLY(0)); + +/* Aggregate all float datasets. */ +ARR_DESC_DEFINE(ARR_DESC_t *, + support_f_all, + 4, + CURLY( + &support_zeros, + &support_f_2, + &support_f_15, + &support_f_32 + )); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.c new file mode 100644 index 0000000..7cc2732 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.c @@ -0,0 +1,10 @@ +#include "jtest.h" +#include "support_tests.h" + +JTEST_DEFINE_GROUP(support_tests) +{ + JTEST_GROUP_CALL(copy_tests); + JTEST_GROUP_CALL(fill_tests); + JTEST_GROUP_CALL(x_to_y_tests); + return; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.c new file mode 100644 index 0000000..4667031 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.c @@ -0,0 +1,80 @@ +#include "jtest.h" +#include "support_test_data.h" +#include "arr_desc.h" +#include "arm_math.h" /* FUTs */ +#include "ref.h" /* Reference Functions */ +#include "test_templates.h" +#include "support_templates.h" +#include "type_abbrev.h" + +/* Aliases to play nicely with templates. */ +#define arm_f32_to_q31 arm_float_to_q31 +#define arm_f32_to_q15 arm_float_to_q15 +#define arm_f32_to_q7 arm_float_to_q7 +#define arm_q31_to_f32 arm_q31_to_float +#define arm_q15_to_f32 arm_q15_to_float +#define arm_q7_to_f32 arm_q7_to_float +#define ref_f32_to_q31 ref_float_to_q31 +#define ref_f32_to_q15 ref_float_to_q15 +#define ref_f32_to_q7 ref_float_to_q7 +#define ref_q31_to_f32 ref_q31_to_float +#define ref_q15_to_f32 ref_q15_to_float +#define ref_q7_to_f32 ref_q7_to_float + +#define JTEST_ARM_X_TO_Y_TEST(prefix, suffix) \ + JTEST_DEFINE_TEST(arm_##prefix##_to_##suffix##_test, \ + arm_##prefix##_to_##suffix) \ + { \ + TEST_TEMPLATE_BUF1_BLK( \ + support_f_all, \ + support_block_sizes, \ + TYPE_FROM_ABBREV(prefix), \ + TYPE_FROM_ABBREV(suffix), \ + arm_##prefix##_to_##suffix, \ + ARM_x_to_y_INPUT_INTERFACE, \ + ref_##prefix##_to_##suffix, \ + REF_x_to_y_INPUT_INTERFACE, \ + SUPPORT_COMPARE_INTERFACE); \ + } + +JTEST_ARM_X_TO_Y_TEST(f32, q31); +JTEST_ARM_X_TO_Y_TEST(f32, q15); +JTEST_ARM_X_TO_Y_TEST(f32, q7); + +JTEST_ARM_X_TO_Y_TEST(q31, f32); +JTEST_ARM_X_TO_Y_TEST(q31, q15); +JTEST_ARM_X_TO_Y_TEST(q31, q7); + +JTEST_ARM_X_TO_Y_TEST(q15, f32); +JTEST_ARM_X_TO_Y_TEST(q15, q31); +JTEST_ARM_X_TO_Y_TEST(q15, q7); + +JTEST_ARM_X_TO_Y_TEST(q7, f32); +JTEST_ARM_X_TO_Y_TEST(q7, q31); +JTEST_ARM_X_TO_Y_TEST(q7, q15); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group. */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(x_to_y_tests) +{ + /* + To skip a test, comment it out. + */ + JTEST_TEST_CALL(arm_f32_to_q31_test); + JTEST_TEST_CALL(arm_f32_to_q15_test); + JTEST_TEST_CALL(arm_f32_to_q7_test); + + JTEST_TEST_CALL(arm_q31_to_f32_test); + JTEST_TEST_CALL(arm_q31_to_q15_test); + JTEST_TEST_CALL(arm_q31_to_q7_test); + + JTEST_TEST_CALL(arm_q15_to_f32_test); + JTEST_TEST_CALL(arm_q15_to_q31_test); + JTEST_TEST_CALL(arm_q15_to_q7_test); + + JTEST_TEST_CALL(arm_q7_to_f32_test); + JTEST_TEST_CALL(arm_q7_to_q31_test); + JTEST_TEST_CALL(arm_q7_to_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.c new file mode 100644 index 0000000..d3e775e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.c @@ -0,0 +1,183 @@ +#include "jtest.h" +#include "ref.h" +#include "arr_desc.h" +#include "transform_templates.h" +#include "transform_test_data.h" +#include "type_abbrev.h" + +/*--------------------------------------------------------------------------------*/ +/* Macros and Defines */ +/*--------------------------------------------------------------------------------*/ + +#define CFFT_FN_NAME(fn_specifier, type_suffix) \ + arm_cfft_##fn_specifier##_##type_suffix \ + +#define CFFT_TEST_NAME(fn_specifier, type_suffix, config_suffix) \ + arm_cfft_##fn_specifier##_##type_suffix##_##config_suffix##_test \ + +/*--------------------------------------------------------------------------------*/ +/* Function Aliases */ +/*--------------------------------------------------------------------------------*/ + +/* These aliases allow expansions in the CFFT_FAMILY_DEFINE_TEST() template to + make sense */ +#define arm_cfft_mag_init_f32 arm_cfft_radix4_init_f32 +#define arm_cfft_mag_init_q31 arm_cfft_radix4_init_q31 +#define arm_cfft_mag_init_q15 arm_cfft_radix4_init_q15 +#define arm_cfft_mag_instance_f32 arm_cfft_radix4_instance_f32 +#define arm_cfft_mag_instance_q31 arm_cfft_radix4_instance_q31 +#define arm_cfft_mag_instance_q15 arm_cfft_radix4_instance_q15 +#define transform_mag_fftlens transform_radix4_fftlens + +/*--------------------------------------------------------------------------------*/ +/* Test Definition */ +/*--------------------------------------------------------------------------------*/ + +/** + * Defines a test for the family of CFFT transforms. + * + * The family of CFFT transforms includes: + * + * - arm_cfft_radix4_xxx + * - arm_cfft_radix2_xxx + * - arm_cfft_mag_xxx + * + * Where xxx can be f32, q31, or q15. + * + * @param fn_specifier Allowed values: radix4, radix2, mag. + * @param type_suffix Allowed values: f32, q31, q15. + * + * @param config_suffix Used to differentiate test names based configuration + * (in this case whether the ifft_flag is set or not.) + + * @param comparison_interface Macro name used to compare reference and fut + * outputs. + * + * @param output_tpe The type of variable contained in the output + * (e.g. float32_t, uint32_t, etc). + * + * @param ifft_flag Determines whether the arm_cfft_instance_xxx is configured + * for an inverse FFT. + */ +#define CFFT_FAMILY_DEFINE_TEST(fn_specifier, \ + type_suffix, \ + config_suffix, /* Delineate between test configs*/ \ + comparison_interface, \ + output_type, \ + ifft_flag) \ + JTEST_DEFINE_TEST(CFFT_TEST_NAME(fn_specifier, type_suffix, \ + config_suffix), \ + CFFT_FN_NAME(fn_specifier, type_suffix)) \ + { \ + arm_cfft_##fn_specifier##_instance_##type_suffix cfft_inst_fut; \ + arm_cfft_##fn_specifier##_instance_##type_suffix cfft_inst_ref; \ + \ + TEMPLATE_DO_ARR_DESC( \ + fftlen_idx, uint16_t, fftlen, transform_##fn_specifier##_fftlens \ + , \ + \ + /* Initialize the cfft instance */ \ + arm_cfft_##fn_specifier##_init_##type_suffix( \ + &cfft_inst_fut, fftlen, ifft_flag, (uint8_t)1); \ + arm_cfft_##fn_specifier##_init_##type_suffix( \ + &cfft_inst_ref, fftlen, ifft_flag, (uint8_t)1); \ + \ + TRANSFORM_PREPARE_INPLACE_INPUTS( \ + transform_fft_##type_suffix##_inputs, \ + fftlen * \ + sizeof(TYPE_FROM_ABBREV(type_suffix)) * \ + 2 /*complex_inputs*/); \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Inverse-transform flag: %d\n", \ + (int)fftlen, \ + (int)ifft_flag); \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES( \ + arm_cfft_##fn_specifier##_##type_suffix( \ + &cfft_inst_fut, \ + (void*) transform_fft_inplace_input_fut)); \ + \ + ref_cfft_##fn_specifier##_##type_suffix( \ + &cfft_inst_ref, \ + (void *) transform_fft_inplace_input_ref); \ + \ + /* Test correctness */ \ + comparison_interface( \ + fftlen, \ + output_type)); \ + \ + return JTEST_TEST_PASSED; \ + } + +/** + * Bulk wrapper for all tests instantiated using #CFFT_FAMILY_DEFINE_TEST(). + * + * This macro allows several test definitions to share the same config_suffix + * and ifft_flag settings. + */ +#define CFFT_FAMILY_DEFINE_ALL_TESTS(config_suffix, ifft_flag) \ + /* Radix2 tests*/ \ + CFFT_FAMILY_DEFINE_TEST(radix2, q31, config_suffix, \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \ + TYPE_FROM_ABBREV(q31), \ + ifft_flag); \ + CFFT_FAMILY_DEFINE_TEST(radix2, q15, config_suffix, \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \ + TYPE_FROM_ABBREV(q15), \ + ifft_flag); \ + /* Radix4 tests*/ \ + CFFT_FAMILY_DEFINE_TEST(radix4, q31, config_suffix, \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \ + TYPE_FROM_ABBREV(q31), \ + ifft_flag); \ + CFFT_FAMILY_DEFINE_TEST(radix4, q15, config_suffix, \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE, \ + TYPE_FROM_ABBREV(q15), \ + ifft_flag) + /* /\* Mag tests*\/ \ */ + /* CFFT_FAMILY_DEFINE_TEST(mag, f32, config_suffix, \ */ + /* TRANSFORM_SNR_COMPARE_INTERFACE, \ */ + /* TYPE_FROM_ABBREV(f32), \ */ + /* ifft_flag); \ */ + /* CFFT_FAMILY_DEFINE_TEST(mag, q31, config_suffix, \ */ + /* TRANSFORM_SNR_COMPARE_INTERFACE, \ */ + /* TYPE_FROM_ABBREV(q31), \ */ + /* ifft_flag); \ */ + /* CFFT_FAMILY_DEFINE_TEST(mag, q15, config_suffix, \ */ + /* TRANSFORM_SNR_COMPARE_INTERFACE, \ */ + /* TYPE_FROM_ABBREV(q15), \ */ + /* ifft_flag) */ + +CFFT_FAMILY_DEFINE_ALL_TESTS(forward, 0U); +CFFT_FAMILY_DEFINE_ALL_TESTS(inverse, 1U); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cfft_family_tests) +{ + /* Forward FFT tests */ + JTEST_TEST_CALL(arm_cfft_radix2_q31_forward_test); + JTEST_TEST_CALL(arm_cfft_radix2_q15_forward_test); + JTEST_TEST_CALL(arm_cfft_radix4_q31_forward_test); + JTEST_TEST_CALL(arm_cfft_radix4_q15_forward_test); + + /* Inverse FFT Tests */ + JTEST_TEST_CALL(arm_cfft_radix2_q31_inverse_test); + JTEST_TEST_CALL(arm_cfft_radix2_q15_inverse_test); + JTEST_TEST_CALL(arm_cfft_radix4_q31_inverse_test); + JTEST_TEST_CALL(arm_cfft_radix4_q15_inverse_test); + + /* Magnitude tests removed from the DSP Library. Keeping them here in case + minds are changed. */ + /* JTEST_TEST_CALL(arm_cfft_mag_f32_forward_test); */ + /* JTEST_TEST_CALL(arm_cfft_mag_q31_forward_test); */ + /* JTEST_TEST_CALL(arm_cfft_mag_q15_forward_test); */ + /* JTEST_TEST_CALL(arm_cfft_mag_f32_inverse_test); */ + /* JTEST_TEST_CALL(arm_cfft_mag_q31_inverse_test); */ + /* JTEST_TEST_CALL(arm_cfft_mag_q15_inverse_test); */ +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.c new file mode 100644 index 0000000..f26c6f6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.c @@ -0,0 +1,144 @@ +#include "jtest.h" +#include "ref.h" +#include "arr_desc.h" +#include "transform_templates.h" +#include "transform_test_data.h" + +#define CFFT_SNR_THRESHOLD 120 + +/* + CFFT function test template. Arguments are: inverse-transform flag, function + suffix (q7/q15/q31/f32) and the output type (q7_t, q15_t, q31_t, float32_t) +*/ +#define CFFT_TEST_BODY(ifft_flag, suffix, output_type) \ + do \ + { \ + /* Go through all arm_cfft_instances */ \ + TEMPLATE_DO_ARR_DESC( \ + cfft_inst_idx, const arm_cfft_instance_##suffix *, cfft_inst_ptr, \ + transform_cfft_##suffix##_structs \ + , \ + \ + TRANSFORM_PREPARE_INPLACE_INPUTS( \ + transform_fft_##suffix##_inputs, \ + cfft_inst_ptr->fftLen * \ + sizeof(output_type) * \ + 2 /*complex_inputs*/); \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Inverse-transform flag: %d\n", \ + (int)cfft_inst_ptr->fftLen, \ + (int)ifft_flag); \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES( \ + arm_cfft_##suffix(cfft_inst_ptr, \ + (void *) transform_fft_inplace_input_fut, \ + ifft_flag, /* IFFT Flag */ \ + 1)); /* Bitreverse flag */ \ + ref_cfft_##suffix(cfft_inst_ptr, \ + (void *) transform_fft_inplace_input_ref, \ + ifft_flag, /* IFFT Flag */ \ + 1); /* Bitreverse flag */ \ + \ + /* Test correctness */ \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE( \ + cfft_inst_ptr->fftLen, \ + output_type)); \ + \ + return JTEST_TEST_PASSED; \ + } while (0) + + +/* + CFFT function with downshift test template. Arguments are: inverse-transform flag, + function suffix (q7/q15/q31/f32) and the output type (q7_t, q15_t, q31_t, float32_t) +*/ +#define CFFT_DOWNSHIFT_INPUT_TEST_BODY(ifft_flag, suffix, output_type) \ + do \ + { \ + /* Go through all arm_cfft_instances */ \ + TEMPLATE_DO_ARR_DESC( \ + cfft_inst_idx, const arm_cfft_instance_##suffix *, cfft_inst_ptr, \ + transform_cfft_##suffix##_structs \ + , \ + \ + TRANSFORM_PREPARE_INPLACE_INPUTS_DOWNSHIFT( \ + transform_fft_##suffix##_inputs, \ + cfft_inst_ptr->fftLen * \ + sizeof(output_type) * \ + 2 /*complex_inputs*/, output_type); \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Inverse-transform flag: %d\n", \ + (int)cfft_inst_ptr->fftLen, \ + (int)ifft_flag); \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES( \ + arm_cfft_##suffix(cfft_inst_ptr, \ + (void *) transform_fft_inplace_input_fut, \ + ifft_flag, /* IFFT Flag */ \ + 1)); /* Bitreverse flag */ \ + ref_cfft_##suffix(cfft_inst_ptr, \ + (void *) transform_fft_inplace_input_ref, \ + ifft_flag, /* IFFT Flag */ \ + 1); /* Bitreverse flag */ \ + \ + /* Test correctness */ \ + TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE( \ + cfft_inst_ptr->fftLen, \ + output_type)); \ + \ + return JTEST_TEST_PASSED; \ + } while (0) + + +/* Test declarations */ +JTEST_DEFINE_TEST(cfft_f32_test, cfft_f32) +{ + CFFT_TEST_BODY((uint8_t) 0, f32, float32_t); +} + +JTEST_DEFINE_TEST(cfft_f32_ifft_test, cfft_f32) +{ + CFFT_TEST_BODY((uint8_t) 1, f32, float32_t); +} + +JTEST_DEFINE_TEST(cfft_q31_test, cfft_q31) +{ + CFFT_TEST_BODY((uint8_t) 0, q31, q31_t); +} + +JTEST_DEFINE_TEST(cfft_q31_ifft_test, cfft_q31) +{ + CFFT_TEST_BODY((uint8_t) 1, q31, q31_t); +} + +JTEST_DEFINE_TEST(cfft_q15_test, cfft_q15) +{ + CFFT_TEST_BODY((uint8_t) 0, q15, q15_t); +} + +JTEST_DEFINE_TEST(cfft_q15_ifft_test, cfft_q15) +{ + CFFT_TEST_BODY((uint8_t) 1, q15, q15_t); +} + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(cfft_tests) +{ + JTEST_TEST_CALL(cfft_f32_test); + JTEST_TEST_CALL(cfft_f32_ifft_test); + + JTEST_TEST_CALL(cfft_q31_test); + JTEST_TEST_CALL(cfft_q31_ifft_test); + + JTEST_TEST_CALL(cfft_q15_test); + JTEST_TEST_CALL(cfft_q15_ifft_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.c new file mode 100644 index 0000000..aae5a42 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.c @@ -0,0 +1,197 @@ +#include "jtest.h" +#include "ref.h" +#include "arm_math.h" +#include "arr_desc.h" +#include "transform_templates.h" +#include "transform_test_data.h" +#include "type_abbrev.h" +#include /* sqrtf() */ + +/*--------------------------------------------------------------------------------*/ +/* Aliases to aid macro expansion */ +/*--------------------------------------------------------------------------------*/ +#define ref_sqrt_f32(x) sqrtf(x) + +/*--------------------------------------------------------------------------------*/ +/* Test Definitions */ +/*--------------------------------------------------------------------------------*/ + +/* +DCT function test template. Arguments are: function configuration suffix +(q7/q15/q31/f32) and input type (q7_t/q15_t/q31_t/float32_t) +*/ +#define DCT4_DEFINE_TEST(suffix, input_type) \ + JTEST_DEFINE_TEST(arm_dct4_##suffix##_test, arm_dct4_##suffix) \ + { \ + CONCAT(arm_dct4_instance_,suffix) dct4_inst_fut = {0}; \ + CONCAT(arm_rfft_instance_,suffix) rfft_inst_fut = {0}; \ + CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_fut = {0}; \ + \ + CONCAT(arm_dct4_instance_,suffix) dct4_inst_ref = {0}; \ + CONCAT(arm_rfft_instance_,suffix) rfft_inst_ref = {0}; \ + CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_ref = {0}; \ + \ + /* Go through all dct lengths */ \ + TEMPLATE_DO_ARR_DESC( \ + fftlen_idx, uint16_t, fftlen, transform_dct_fftlens \ + , \ + \ + float32_t normalize_f32 = \ + ref_sqrt_f32((2.0f/(float32_t)fftlen)); \ + input_type normalize; \ + \ + /* Calculate normalized DCT4 value for input_type. */ \ + TEST_CONVERT_FLOAT_TO(&normalize_f32, &normalize, \ + 1, input_type); \ + \ + /* Initialize the DCT4, RFFT, and CFFT instances */ \ + arm_dct4_init_##suffix( \ + &dct4_inst_fut, &rfft_inst_fut, &cfft_inst_fut, \ + fftlen, \ + fftlen/2, \ + normalize); \ + \ + arm_dct4_init_##suffix( \ + &dct4_inst_ref, &rfft_inst_ref, &cfft_inst_ref, \ + fftlen, \ + fftlen/2, \ + normalize); \ + \ + memset( transform_fft_input_fut,0, \ + fftlen*sizeof(input_type)); \ + \ + TRANSFORM_PREPARE_INPLACE_INPUTS( \ + transform_fft_##suffix##_inputs, \ + fftlen * sizeof(input_type)); \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n", \ + (int)fftlen); \ + \ + /* Input provided as a scratch buffer. Inplace input is \ + * actual input. Display cycle count and run test*/ \ + JTEST_COUNT_CYCLES( \ + arm_dct4_##suffix( \ + &dct4_inst_fut, \ + (void *) transform_fft_input_fut, \ + (void *) transform_fft_inplace_input_fut)); \ + \ + memset( transform_fft_input_ref,0, \ + fftlen*sizeof(input_type)); \ + \ + /* Input provided as a scratch buffer. Inplace input is */ \ + /* actual input. */ \ + ref_dct4_##suffix( \ + &dct4_inst_ref, \ + (void *) transform_fft_input_ref, \ + (void *) transform_fft_inplace_input_ref); \ + \ + /* Test correctness */ \ + DCT_TRANSFORM_SNR_COMPARE_INTERFACE( \ + fftlen, \ + input_type)); \ + \ + return JTEST_TEST_PASSED; \ + } + +/* + DCT function test template for fixed point data. Arguments are: function + suffix (q7/q15/q31/f32), input type (q7_t/q15_t/q31_t/float32_t) and prefix + (dct_4) +*/ +#define DCT4_FIXED_POINT_DEFINE_TEST(suffix, input_type, prefix) \ + JTEST_DEFINE_TEST(arm_dct4_##suffix##_test, arm_dct4_##suffix) \ + { \ + CONCAT(arm_dct4_instance_,suffix) dct4_inst_fut = {0}; \ + CONCAT(arm_rfft_instance_,suffix) rfft_inst_fut = {0}; \ + CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_fut = {0}; \ + \ + CONCAT(arm_dct4_instance_,suffix) dct4_inst_ref = {0}; \ + CONCAT(arm_rfft_instance_,suffix) rfft_inst_ref = {0}; \ + CONCAT(arm_cfft_radix4_instance_,suffix) cfft_inst_ref = {0}; \ + \ + TEMPLATE_DO_ARR_DESC( \ + fftlen_idx, uint16_t, fftlen, transform_dct_fftlens \ + , \ + uint32_t i; \ + float32_t normalize_f32 = \ + ref_sqrt_f32((2.0f/(float32_t)fftlen)); \ + input_type normalize; \ + \ + /* Calculate normalized DCT4 value for input_type. */ \ + TEST_CONVERT_FLOAT_TO(&normalize_f32, &normalize, \ + 1, input_type); \ + \ + /* Initialize the DCT4, RFFT, and CFFT instances */ \ + arm_dct4_init_##suffix( \ + &dct4_inst_fut, &rfft_inst_fut, &cfft_inst_fut, \ + fftlen, \ + fftlen/2, \ + normalize); \ + \ + arm_dct4_init_##suffix( \ + &dct4_inst_ref, &rfft_inst_ref, &cfft_inst_ref, \ + fftlen, \ + fftlen/2, \ + normalize); \ + \ + /* Input samples need to be downscaled by 1 bit to \ + * avoid saturations in the Q31 DCT process, \ + * as the conversion from DCT2 to DCT4 involves \ + * one subtraction. \ + */ \ + for(i=0; i < fftlen; i++) \ + { \ + ((input_type*)transform_fft_inplace_input_fut)[i] = \ + prefix##transform_fft_##suffix##_inputs[i] >> 1; \ + ((input_type*)transform_fft_inplace_input_ref)[i] = \ + prefix##transform_fft_##suffix##_inputs[i] >> 1; \ + } \ + \ + memset( transform_fft_input_fut,0, \ + fftlen*sizeof(input_type)); \ + \ + /* Display test parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n", \ + (int)fftlen); \ + \ + /* Input provided as a scratch buffer. Inplace input is \ + * actual input. */ \ + JTEST_COUNT_CYCLES( \ + arm_dct4_##suffix( \ + &dct4_inst_fut, \ + (void *) transform_fft_input_fut, \ + (void *) transform_fft_inplace_input_fut)); \ + \ + memset( transform_fft_input_ref,0, \ + fftlen*sizeof(input_type)); \ + \ + /* Input provided as a scratch buffer. Inplace input is */ \ + /* actual input. */ \ + ref_dct4_##suffix( \ + &dct4_inst_ref, \ + (void *) transform_fft_input_ref, \ + (void *) transform_fft_inplace_input_ref); \ + \ + /* Test correctness */ \ + DCT_TRANSFORM_SNR_COMPARE_INTERFACE( \ + fftlen, \ + input_type)); \ + \ + return JTEST_TEST_PASSED; \ + } + +DCT4_DEFINE_TEST(f32, float32_t); +DCT4_FIXED_POINT_DEFINE_TEST(q31, q31_t,); +DCT4_FIXED_POINT_DEFINE_TEST(q15, q15_t, dct4_); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(dct4_tests) +{ + JTEST_TEST_CALL(arm_dct4_f32_test); + JTEST_TEST_CALL(arm_dct4_q31_test); + JTEST_TEST_CALL(arm_dct4_q15_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.c new file mode 100644 index 0000000..d8a8e17 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.c @@ -0,0 +1,75 @@ +#include "jtest.h" +#include "ref.h" +#include "arr_desc.h" +#include "transform_templates.h" +#include "transform_test_data.h" +#include "type_abbrev.h" + +/* +FFT fast function test template. Arguments are: function configuration suffix +(q7/q15/q31/f32) and inverse-transform flag +*/ +#define RFFT_FAST_DEFINE_TEST(config_suffix, ifft_flag) \ + JTEST_DEFINE_TEST(arm_rfft_fast_f32_##config_suffix##_test, \ + arm_fft_f32) \ + { \ + arm_rfft_fast_instance_f32 rfft_inst_fut = {{0}, 0, 0}; \ + arm_rfft_fast_instance_f32 rfft_inst_ref = {{0}, 0, 0}; \ + \ + /* Go through all FFT lengths */ \ + TEMPLATE_DO_ARR_DESC( \ + fftlen_idx, uint16_t, fftlen, transform_rfft_fast_fftlens \ + , \ + \ + /* Initialize the RFFT and CFFT Instances */ \ + arm_rfft_fast_init_f32( \ + &rfft_inst_fut, fftlen); \ + \ + arm_rfft_fast_init_f32( \ + &rfft_inst_ref, fftlen); \ + \ + TRANSFORM_COPY_INPUTS( \ + transform_fft_f32_inputs, \ + fftlen * \ + sizeof(float32_t)); \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Inverse-transform flag: %d\n", \ + (int)fftlen, \ + (int)ifft_flag); \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES( \ + arm_rfft_fast_f32( \ + &rfft_inst_fut, \ + (void *) transform_fft_input_fut, \ + (void *) transform_fft_output_fut, \ + ifft_flag)); \ + \ + ref_rfft_fast_f32( \ + &rfft_inst_ref, \ + (void *) transform_fft_input_ref, \ + (void *) transform_fft_output_ref, \ + ifft_flag); \ + \ + /* Test correctness */ \ + TRANSFORM_SNR_COMPARE_INTERFACE( \ + fftlen, \ + float32_t)); \ + \ + return JTEST_TEST_PASSED; \ + } + +RFFT_FAST_DEFINE_TEST(forward, 0U); +RFFT_FAST_DEFINE_TEST(inverse, 1U); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(rfft_fast_tests) +{ + JTEST_TEST_CALL(arm_rfft_fast_f32_forward_test); + JTEST_TEST_CALL(arm_rfft_fast_f32_inverse_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.c new file mode 100644 index 0000000..6fbc8e6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.c @@ -0,0 +1,94 @@ +#include "jtest.h" +#include "ref.h" +#include "arr_desc.h" +#include "transform_templates.h" +#include "transform_test_data.h" +#include "type_abbrev.h" + +/* + FFT function test template. Arguments are: function suffix (q7/q15/q31/f32) + function configuration suffix (same as function suffix), inverse-transform flag, + input and output type (both q7_t/q15_t/q31_t/float32_t) +*/ +#define RFFT_DEFINE_TEST(suffix, config_suffix, \ + ifft_flag, input_type, output_type) \ + JTEST_DEFINE_TEST(arm_rfft_##suffix##_##config_suffix##_test, \ + arm_rfft_##suffix) \ + { \ + CONCAT(arm_rfft_instance_, suffix) rfft_inst_fut = {0}; \ + CONCAT(arm_rfft_instance_, suffix) rfft_inst_ref = {0}; \ + \ + /* Go through all arm_rfft lengths */ \ + TEMPLATE_DO_ARR_DESC( \ + fftlen_idx, uint16_t, fftlen, transform_rfft_fftlens \ + , \ + \ + /* Initialize the RFFT and CFFT Instances */ \ + arm_rfft_init_##suffix( \ + &rfft_inst_fut, \ + (uint32_t) fftlen, ifft_flag, 1U); \ + \ + arm_rfft_init_##suffix( \ + &rfft_inst_ref, \ + (uint32_t) fftlen, ifft_flag, 1U); \ + \ + if (ifft_flag) \ + { \ + TRANSFORM_PREPARE_INVERSE_INPUTS( \ + transform_fft_##suffix##_inputs, \ + fftlen, input_type, \ + fftlen * \ + sizeof(input_type)); \ + } \ + else \ + { \ + TRANSFORM_COPY_INPUTS( \ + transform_fft_##suffix##_inputs, \ + fftlen * \ + sizeof(input_type)); \ + } \ + \ + /* Display parameter values */ \ + JTEST_DUMP_STRF("Block Size: %d\n" \ + "Inverse-transform flag: %d\n", \ + (int)fftlen, \ + (int)ifft_flag); \ + \ + /* Display cycle count and run test */ \ + JTEST_COUNT_CYCLES( \ + arm_rfft_##suffix( \ + &rfft_inst_fut, \ + (void *) transform_fft_input_fut, \ + (void *) transform_fft_output_fut)); \ + \ + ref_rfft_##suffix( \ + &rfft_inst_ref, \ + (void *) transform_fft_input_ref, \ + (void *) transform_fft_output_ref); \ + \ + /* Test correctness */ \ + TRANSFORM_SNR_COMPARE_INTERFACE( \ + fftlen, \ + output_type)); \ + \ + return JTEST_TEST_PASSED; \ + } + +RFFT_DEFINE_TEST(q31, forward, 0U, TYPE_FROM_ABBREV(q31), TYPE_FROM_ABBREV(q31)); +RFFT_DEFINE_TEST(q15, forward, 0U, TYPE_FROM_ABBREV(q15), TYPE_FROM_ABBREV(q15)); +//RFFT_DEFINE_TEST(f32, inverse, 1U, TYPE_FROM_ABBREV(f32), TYPE_FROM_ABBREV(f32)); +RFFT_DEFINE_TEST(q31, inverse, 1U, TYPE_FROM_ABBREV(q31), TYPE_FROM_ABBREV(q31)); +RFFT_DEFINE_TEST(q15, inverse, 1U, TYPE_FROM_ABBREV(q15), TYPE_FROM_ABBREV(q15)); + +/*--------------------------------------------------------------------------------*/ +/* Collect all tests in a group */ +/*--------------------------------------------------------------------------------*/ + +JTEST_DEFINE_GROUP(rfft_tests) +{ + JTEST_TEST_CALL(arm_rfft_q31_forward_test); + JTEST_TEST_CALL(arm_rfft_q15_forward_test); + //JTEST_TEST_CALL(arm_rfft_f32_inverse_test); + JTEST_TEST_CALL(arm_rfft_q31_inverse_test); + JTEST_TEST_CALL(arm_rfft_q15_inverse_test); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.c new file mode 100644 index 0000000..f071068 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.c @@ -0,0 +1,11 @@ +#include "jtest.h" +#include "transform_tests.h" + +JTEST_DEFINE_GROUP(transform_tests) +{ + JTEST_GROUP_CALL(cfft_tests); + JTEST_GROUP_CALL(cfft_family_tests); + JTEST_GROUP_CALL(rfft_tests); + JTEST_GROUP_CALL(rfft_fast_tests); + JTEST_GROUP_CALL(dct4_tests); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.c new file mode 100644 index 0000000..98987b3 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.c @@ -0,0 +1,3311 @@ +#include "transform_test_data.h" +#include "arm_const_structs.h" + +/*--------------------------------------------------------------------------------*/ +/* Input/Output Buffers */ +/*--------------------------------------------------------------------------------*/ + +float32_t transform_fft_output_fut[TRANSFORM_MAX_FFT_LEN * 2] = {0}; +float32_t transform_fft_output_ref[TRANSFORM_MAX_FFT_LEN * 2] = {0}; +float32_t transform_fft_input_fut[TRANSFORM_MAX_FFT_LEN * 2] = {0}; +float32_t transform_fft_input_ref[TRANSFORM_MAX_FFT_LEN * 2] = {0}; +float32_t transform_fft_output_f32_fut[TRANSFORM_MAX_FFT_LEN * 2] = {0}; +float32_t transform_fft_output_f32_ref[TRANSFORM_MAX_FFT_LEN * 2] = {0}; + +/* Some of the transform function modify their inputs in-place, so that they + * become the outputs. */ +float32_t * transform_fft_inplace_input_fut = transform_fft_output_fut; +float32_t * transform_fft_inplace_input_ref = transform_fft_output_ref; + +q31_t transform_fft_q31_inputs[TRANSFORM_MAX_FFT_LEN * 2] = +{ + 0xC14A5524, 0xCCABDA17, 0xAD6F5B56, 0xFDAFCE3B, 0xA9B226EB, + 0x41F6F6A, 0xA5CE38BF, 0x3A978AFA, 0xBA44B82A, 0x855C0F8, + 0x3D060524, 0x93D5E570, 0x97D7791D, 0xFFE0C38C, 0x26749841, + 0xC0A6EE54, 0x218EC386, 0x39FF3726, 0x8DC1F7CA, 0x702F2CF5, + 0xC1142FF1, 0xEC1476AB, 0x15F640DD, 0xE62CCE49, 0x3805DE7E, + 0xF70871FE, 0xCF8BD360, 0x8D19A8A0, 0xD764F821, 0xA58558CF, + 0x8C0CE04D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0xB646AE24, + 0x6CE00F5C, 0xE6D48948, 0xB55BD831, 0x3B72950A, 0x9EB69530, + 0x73394127, 0x773FA6F4, 0x9805A980, 0x838DE587, 0x9CF597F4, + 0xA2AD1691, 0xFA81A473, 0x7CDC7D7F, 0x4A5190D0, 0xED895BB9, + 0x8FD60F35, 0x1A21D530, 0xA0EB6DDA, 0xBDE6A516, 0x2501A3E1, + 0x5ED893C8, 0xE1E175B1, 0xACBBB2F3, 0xED350907, 0xDB140D7E, + 0xEEAE272D, 0xBE229841, 0xC18BFB88, 0xA6BB9B80, 0xBCF090E4, + 0x24DB166C, 0xF9AB7E42, 0x62DF28D1, 0xC7004665, 0xE3F56FC6, + 0x419E0C75, 0x46BE9F38, 0x2432B9B2, 0x758D83E0, 0xDCE12926, + 0x3F57CB74, 0x1F4458E2, 0xF1DD639, 0x83A1FB49, 0x173AFC76, + 0x86EF7531, 0x48D32F34, 0x7D3E3063, 0x8F2FB549, 0x5C314C9, + 0x18CBEB6D, 0xA6F8B697, 0x447B9E9C, 0x2E32BA33, 0xD074D715, + 0x81ACD746, 0xE55A4E04, 0x4891860F, 0x1DA3EB4F, 0xE0E6A27F, + 0x20BFDEB4, 0xD0B3A25B, 0x40C10544, 0xC15656C, 0x15405EAE, + 0x9858E3E1, 0xA36A9C4E, 0x88BD21F9, 0xAACF7A68, 0x773665E5, + 0xCEDFDF66, 0x617A9610, 0x524FC968, 0xC2D086CD, 0x5F008079, + 0x24DCA447, 0x6A4F5599, 0xB706CD4A, 0x1DE70608, 0xA33A2EE5, + 0x137E488E, 0x98061B7B, 0x4079D69D, 0xA4A897D5, 0xC4CEC8F5, + 0xD75F7883, 0x22406802, 0xF1AD70BB, 0x9D4ADD79, 0xBCBC7CE4, + 0xB358C0D8, 0x85792E47, 0xA7ADAC05, 0x3D19EEAB, 0x331AC0AF, + 0x33035831, 0x13D93987, 0xFC542094, 0x845F317E, 0xDDC4BF8B, + 0x1379E50C, 0x5C20193F, 0xFDD58298, 0x9D482B82, 0x4A6BE062, + 0xDC8A757B, 0x272917C1, 0x90E1EFBC, 0x355AD882, 0xE6F8EA35, + 0x604555A1, 0x7DFFFBB, 0xF58AE216, 0x9A11B463, 0xD3541BAD, + 0xA1576756, 0x483BED8D, 0x1F05AFCC, 0xCEA63DFB, 0x55B84677, + 0xFB2E04F2, 0x787AF96C, 0x84A12CD3, 0x460A9BD, 0x9DB22DD8, + 0x1A8C7F28, 0x861E452E, 0x932D3F78, 0x7652D852, 0x73357BBA, + 0xEBBB0A58, 0x62536AFA, 0x3F6B65EF, 0x6DC57B58, 0x9EB798CE, + 0xE6B0A740, 0xDFF68B47, 0x3247FB8F, 0xFFF3D302, 0xA9FD3E40, + 0x475A43D1, 0x6FF9528A, 0x2018A09D, 0x47E0F9C9, 0x4CF5F6D3, + 0x2807CE34, 0xDD6FD8ED, 0x234045D1, 0x51CEB5F9, 0x25297896, + 0x6443A0FE, 0x8F4449A9, 0xD4C3E1C6, 0xF01D52F1, 0x4E09C820, + 0xF18F0810, 0xE1548689, 0xF9DE5A1F, 0x5286DC23, 0x48AC3A4B, + 0xEA0C1BE0, 0xA1B785DB, 0x7086465D, 0x1CC10929, 0x1E1D716E, + 0xED231D4C, 0x2049D108, 0xB8FF9971, 0x949CF8D4, 0x441F1E8B, + 0xC3D95372, 0x69C324B4, 0xA10BFDC9, 0xC781DE78, 0x82476137, + 0xE163DDF, 0x390DEEC2, 0xAF68CE5B, 0x8E680ABD, 0x8223A615, + 0x92593380, 0x7B1465FE, 0x865AE957, 0x930F53EB, 0xED772EF7, + 0x10E916B6, 0xE3BCFA68, 0x2ACB80BB, 0xE51C5590, 0x994714B5, + 0xF30984EE, 0x59BBE1B4, 0xB4867DBC, 0xB91C706C, 0xBC16C218, + 0xA8931CD0, 0x129A66AB, 0x13171F4D, 0x62882872, 0x4B167FD4, + 0xE6902F4C, 0xFA794932, 0xD4B152C, 0xB0856EA9, 0x39466D55, + 0x3669E451, 0x8F5B9E8C, 0x877A3C6A, 0x51B956B4, 0x367EAD2A, + 0x9D2C662A, 0x78FB6880, 0x4E6D40B6, 0x4070EFDC, 0x4DF9679C, + 0x20306EDB, 0xE381AAE7, 0xA55DA748, 0x9B8B617B, 0x3E036FAD, + 0x84E4C4A7, 0xD5A3F517, 0x669BA988, 0x98FDDE8C, 0x67BD85CE, + 0x34BBB46C, 0x76994800, 0x85B9D8B6, 0x6DFA2FEF, 0x205DB5C, + 0x9F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB98B61, 0xC323DDAC, + 0x31D424B4, 0xF68C0D7E, 0x162FAF9D, 0x7B2A7A99, 0xF9392693, + 0xC42D12C0, 0x8692A73E, 0xD9A1EE80, 0xDD956856, 0x44E7BDAC, + 0x8D874532, 0x5F5C9DD0, 0x5D167858, 0x8559FEA2, 0x9D821476, + 0xD9654ED2, 0x594C0DC7, 0x1A87B506, 0x3F693200, 0x7A651AB5, + 0xA0CCBC8A, 0x9F9E662C, 0x78EF631, 0x2A09DA0, 0xB088C72F, + 0x92EE0D42, 0x360DCD5F, 0xF333FE48, 0x8D63CC06, 0x233A8ACB, + 0x706651ED, 0x7AA5C079, 0x262239D1, 0x3EBBEBB6, 0xA25A4F3D, + 0x32581A06, 0x6E6FD780, 0x5773F7C7, 0x75ED1DDC, 0x90DF2D15, + 0xBC79A9BC, 0xB7175917, 0x354E381C, 0x762AADD7, 0xF643DAC1, + 0xF3BBF49E, 0xD2FECE7E, 0x6C8140F4, 0xD7694875, 0x92D30822, + 0xC742A7CF, 0xB792ED98, 0x121CFE24, 0xA04E1EE7, 0x58CE268, + 0x215A080, 0x316CB323, 0xFAB14A31, 0xE1C13C03, 0xFD8EF4F1, + 0xF3F446D0, 0x6C6CEA0A, 0xBBFDF9FB, 0x67242969, 0xBE55A4EB, + 0x8FF5534, 0x52F0DF1C, 0x9710ADE3, 0xD40F4A21, 0x7984E8E7, + 0x419545EB, 0x993F7880, 0xAB246B20, 0x408AABC4, 0xCBF6EA49, + 0xC0894C55, 0x4CAA6398, 0xA47856E9, 0xAF2AE47D, 0x22F55D33, + 0xF0D37915, 0xD0634C72, 0xD983671, 0x2BCC5AF8, 0x9A77D48, + 0xC11B5CFA, 0xF107CD7E, 0x3A6B3593, 0xE1425F05, 0x6271812A, + 0x5B838310, 0xBD8418CA, 0x10A58792, 0x239F7137, 0xA13D5071, + 0x7F9930D4, 0xA462664F, 0x54180F8E, 0x291585BA, 0xE586B87A, + 0x144B2C12, 0x98E425C7, 0xBAA4B373, 0x18F0D03C, 0x99462AC0, + 0xD8B4D2EF, 0x72473895, 0xA6BF5435, 0xEDAD53B, 0xE0912FA6, + 0x5C33F331, 0x3D93CD7, 0x4D03D752, 0x20699929, 0xB89962F9, + 0x36E781E9, 0xF58B642C, 0x5FCA69E3, 0x5960A7F4, 0xAD5AAFD0, + 0xDF18324A, 0x3DB1E5AA, 0x76BA3876, 0x1BC29AF6, 0xBCC18841, + 0x73A60174, 0x625BFF58, 0x67C57724, 0x4458E53C, 0xE157B095, + 0x2B370837, 0x83DF6CE3, 0xDD08EEFA, 0x3F52A7C2, 0x191B4785, + 0x60843D82, 0xB0DE11F1, 0x105EA26C, 0x6E1C7AA2, 0x47AADD14, + 0xB6676D03, 0x3B8D4DF6, 0x737A694, 0x409521DC, 0x744206A, + 0xC722023F, 0x2BE4EAD5, 0x63E11D76, 0xCA4A09AB, 0x5CF2D2B9, + 0x31586916, 0xCDFD7D84, 0xB203F634, 0xAD7329D4, 0xC524582F, + 0x2E53E6C1, 0xBB0E019B, 0xB8538C6A, 0x6A2542D, 0x8A6A00E5, + 0x119725CC, 0x5406D347, 0x1B6FFAF1, 0xECCF71F1, 0x981117F2, + 0x7167CA76, 0x74F4B880, 0x77A55F47, 0x59EADB62, 0x4A331D95, + 0xBCBBA76F, 0xA45C4D50, 0xC718D5, 0x87CE05D1, 0x60D47AD5, + 0xA5CA9C40, 0xB0061766, 0xE69B39DF, 0xBD5F1320, 0x9930EAD3, + 0xA8B38325, 0x8DD090F, 0x6A6EEF37, 0x2DF16F66, 0xAB514C7E, + 0x31109C58, 0xFD48C7FC, 0x515341CA, 0x77AB8EA6, 0x41328DAF, + 0xBAF8D31E, 0xA4B31611, 0xED37F331, 0x7A832A22, 0xA22591C7, + 0x722D1F89, 0x3B19CF18, 0x261B8A4D, 0xC3F6F6DB, 0xCF8CED61, + 0x990FA250, 0xA02E72A9, 0x560DCEA2, 0xB08E67B4, 0x3674E663, + 0x97CC3852, 0xA7EB2EAC, 0xFFDE0AA8, 0xA64719A, 0x23269EDD, + 0x3C0B339E, 0x86284D40, 0x48D82ECB, 0xA4D4CCF8, 0x43631B91, + 0x4BF0C248, 0xB6497B9B, 0x6827BC58, 0xE30B7AF9, 0xA0CCBF26, + 0x6C3B7B71, 0xD744B3ED, 0xFA25D2F6, 0x4CDE642D, 0xD65B8142, + 0xA6F9207F, 0xE7A207BE, 0xDB506684, 0x44DA4780, 0x9175EA0C, + 0x156104AF, 0x4155E1B0, 0x6E3A6886, 0x9DBA1EA2, 0x5423D9C8, + 0xCC024E22, 0x758F852A, 0x1DD6395, 0x2D19CBAD, 0xE164F5A1, + 0xC2084602, 0x89C274AD, 0x13CB5562, 0xD7FE2D5B, 0xE07A4EE5, + 0x1672BA91, 0x4F624CCF, 0x2E5EA4A3, 0x28FEEFAF, 0xBDDA6EF4, + 0x32AFD40C, 0x99A5FB3B, 0xDD1D73A3, 0xA342CB3E, 0xA78445F5, + 0x53979C3B, 0x427D7943, 0x5221B58C, 0xA6CE9A5E, 0xFB50ECA4, + 0xBB86E36E, 0x60839F6D, 0xC5E1C2F3, 0xA1B7FB04, 0xFBB65E0C, + 0x78B80F5E, 0xFD8D972B, 0x3BF3BA90, 0x2D572D9, 0x2B5BC920, + 0xB6A0DE01, 0xD274D306, 0xC7C6C855, 0x9CAA669B, 0xB04AA641, + 0x4D6B1760, 0x3E17ED79, 0xD23241B0, 0xA4A6F957, 0xCBDE76AF, + 0x4E5F9493, 0x4C215DA5, 0x33A052B, 0x1A4D80C2, 0x40AEEBCA, + 0x390D106B, 0xE9E8E018, 0x5AF3D6CF, 0xE35E1D4, 0xC4FB1C6, + 0x14B6299B, 0x8D2E25F0, 0xCCBF932A, 0xC5AC18B6, 0x2227567D, + 0x86B5CE2F, 0x26344534, 0x22C515EC, 0x2442B70D, 0xEC3721C6, + 0x34EF687D, 0x9C06323A, 0xEAF3EA60, 0x60396F52, 0xEAE78AA1, + 0xC9D06CBC, 0x6F95F6C8, 0x584CC258, 0xBA9A27BB, 0x66DF8D47, + 0x9D4804EA, 0x57DD9E67, 0xF89C7895, 0xF5336111, 0x25C122C8, + 0x62742114, 0xCFBF6D26, 0xBF9F6482, 0xE6F02CD9, 0x11083202, + 0xC99E2618, 0x7EBC9351, 0x440112F1, 0xC9DFFBC1, 0x3BF4DC25, + 0xB1BA7FA0, 0x61AF9AED, 0x6B1F7D29, 0xAD865294, 0xE3E01129, + 0x7E9E77A5, 0x100435D7, 0x9FE3A71, 0x88597C81, 0x722849FA, + 0x31C5A0AF, 0xFBA178DC, 0x7F102D31, 0x5CA07864, 0x950E6F98, + 0x82C34882, 0x5D041F11, 0x8C613C57, 0xD398CFD1, 0x426F38AD, + 0x5599AB1D, 0xFAFA078D, 0xAB25B413, 0xD94B32CF, 0xB288FE38, + 0x2893BB46, 0x9A0B4168, 0xA91BCA94, 0x653A5E8D, 0x2174EBBE, + 0xDEFE6415, 0x30DA429C, 0xD0C5E40C, 0xB4719AA4, 0xD29CE7A6, + 0x905957CD, 0xCD287499, 0x83CA0AA7, 0xA8385832, 0x25A0CA02, + 0xC20D47A4, 0xB562F556, 0x4BC19E4C, 0xD9E215C7, 0x27E838B4, + 0xC58612F4, 0xA2827F6F, 0xC49DCDBA, 0x679B7362, 0x4E495845, + 0xCFD2F0D1, 0x395E76A0, 0x375A655E, 0x92E2058F, 0x73F9F0CA, + 0x61EFF3B3, 0x51FFD362, 0xE7410345, 0x7FDA8B3B, 0xA219E2E8, + 0x17ABE543, 0x26557412, 0x4B30084D, 0xA68E191D, 0xFE0D93DF, + 0x73EF127D, 0x4DECDDB1, 0x77FAF45F, 0xD6002898, 0x92DD0A40, + 0x157F6DDF, 0xC2A55F8E, 0x4359F924, 0xFB630C3F, 0x338B6B58, + 0xB2945F75, 0x4FA23A0E, 0x836EB8C0, 0xB3B18FD, 0x86114337, + 0x24668ACB, 0x99BB82F0, 0x924C8A47, 0xBA959701, 0x81155ABF, + 0x8C612D71, 0x36074CA7, 0xD1668C41, 0xE35F58C7, 0x7FC2802D, + 0x8E6A7CF3, 0x65B07D07, 0x815F6A6B, 0x791BF0DD, 0x6E47D719, + 0xC24394C7, 0xE84A6EB, 0xF194AFEE, 0x464A2F52, 0x677579FD, + 0xEBA775AE, 0x1F6EEFF, 0x9A795237, 0x78D9D45F, 0x9D0B344D, + 0xBBD34AB7, 0x2F85B12A, 0x16C5C2AD, 0x3990985D, 0x88DF3351, + 0x82811AA5, 0x6D351F41, 0x4066A69D, 0x86B660BF, 0x6EDB4768, + 0xDDD78CF0, 0xB5D74F6E, 0xE89E220C, 0x91439687, 0x947CC9C9, + 0x3857E2BD, 0x302F8AE4, 0x1DABE7F8, 0x4832D6C9, 0x37D58FCB, + 0x4EA8A711, 0xCD7BAC98, 0x19DBF8BC, 0xD8DE8DC2, 0xEAFF7E7B, + 0xB7629C93, 0x792C6E19, 0xF7009192, 0xFF88439D, 0x2E196A66, + 0xEC71B78C, 0xEAF4BB3A, 0x7C16225E, 0x668F337, 0xCBEE1608, + 0x6D5B5552, 0x345DC590, 0x681209CC, 0x7B24A819, 0xD08A1416, + 0x99888FE3, 0x9FC7288A, 0x24BD8502, 0xEA1D9678, 0x20EECA0, + 0x59BEA057, 0x5ADE91EB, 0xDEA8E49D, 0xFA200E6F, 0x9149C81D, + 0xF2281E93, 0x8A5B0451, 0x67312D58, 0xE3B849F1, 0xD2217960, + 0x7CDF59F3, 0x33C775C0, 0x9EBA8799, 0x7DF9506, 0xB4E96110, + 0xB8FCF3E3, 0xDEA059B2, 0x8229B6EA, 0x316486F6, 0x43919185, + 0x6C0D90F3, 0x1C6F3DF8, 0x38DB92A9, 0x5CD41244, 0x2C9F0A7B, + 0xDF4A315F, 0xF7CE9C66, 0x4C800860, 0x318D53E0, 0xF105C20D, + 0xD753E1F2, 0x750810BA, 0xA17ECCA5, 0x2010140, 0x4D884763, + 0xC2BB0DA7, 0xB2D5BA74, 0x141CECD4, 0x887FDFC3, 0xC64B53, + 0x2D2A85F6, 0x15532B45, 0x5D5CBCE1, 0xBEB9A16A, 0xA214611B, + 0x9FC5AC5F, 0x11AE5DD7, 0xA0B9A5A9, 0xFC648AF4, 0x740009AC, + 0xED0E0321, 0xB8E6A61, 0x8910C544, 0xC74F26C8, 0x9525CCF3, + 0xB41AEB59, 0xE61984CE, 0x598B2197, 0xA412E59D, 0xE1976DD4, + 0xB29BBE16, 0x88FD9FB0, 0xB04006F3, 0xB45E309, 0xD5CC15F1, + 0xD9DAF630, 0xDC809335, 0x803ED52, 0xB537F5A5, 0xA994F6EB, + 0xF5288568, 0xF66FD264, 0x2EA2B3A6, 0x647619F3, 0xFFB38C7A, + 0x1BC03B9, 0xB6BC3061, 0xBF30596E, 0xBE2AD27B, 0x8AC04220, + 0x641979A3, 0x9ECCBB89, 0xA144FBC1, 0x4E8FAE26, 0x8C5A9D90, + 0x299ED467, 0xD7C9C7E3, 0x1D4865ED, 0x76F31C3D, 0xCEE81CDF, + 0xB479195E, 0x6FFB3AE1, 0xDC8A398, 0x300F7364, 0xC7940AFA, + 0x3B85BE3E, 0xD98CC40D, 0xA24A3D89, 0x3A674204, 0x22888A38, + 0x2E77F2D, 0xA2841C9C, 0xCF0689C3, 0x9FE98922, 0x89335017, + 0x2D6B69A7, 0xFEDB63F9, 0x899AF4EF, 0x9F9F9B40, 0xA4BE97E8, + 0xA51DAF7A, 0x16AC50D3, 0xA8D7ED6, 0xED193443, 0x7615EF1B, + 0xB0DF6A4E, 0x64FFE794, 0xE3DB2C9A, 0x7435B022, 0x556E825C, + 0x23802AF9, 0xC25098A4, 0xE75A18BB, 0x70B2A7B9, 0x7FB81BF, + 0x63EF910, 0x6C669591, 0x6574DD2B, 0xCF6E379D, 0xD2B3AFAC, + 0x1E6A1101, 0x1DE22385, 0x2338191F, 0xC69704B6, 0xCBABC599, + 0x54EB4809, 0x7839BE6D, 0xD50017DD, 0x39B1A0E1, 0x288D52D3, + 0x2D52668C, 0x20D22A68, 0x4E1207D1, 0x3FCC0EFE, 0x47F3FE64, + 0x25177A90, 0xB4BFDD4D, 0xDA8DBDCE, 0x6F7275A8, 0x6BEAA655, + 0xAA1810FC, 0xE4DB593A, 0x8A4D4BC0, 0x2C402E93, 0xF1C0F7F9, + 0x6F0CC577, 0x70412414, 0x752F9DC1, 0xD82E38EA, 0xAC455F7B, + 0x4DCD4EDB, 0x92BC2696, 0xFB03F135, 0x4FCA1F8C, 0xBD5E75F6, + 0x502F41B0, 0x3616D3F1, 0x2E5B8E31, 0x2026EB19, 0x57E783D7, + 0x467BBE00, 0x4703ABA3, 0x1F776B9C, 0xE2570A84, 0xFEC7DB48, + 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, 0x99D5D8ED, + 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F, + 0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB, + 0x56186AA1, 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94, + 0xAC18B207, 0x5FC78B3, 0x7F10621E, 0xA769E6B2, 0xEC9F4A11, + 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, 0x73D63FED, 0xE36E9F5E, + 0x8AC1DA0E, 0x3F3DB3EB, 0x738326EA, 0x35C366B1, 0xCD476E86, + 0x82F6B208, 0xF11A9FC1, 0x426AC396, 0x7E4D1B93, 0x75E4EDB7, + 0xAF3C44A7, 0x51A5EF5C, 0xFAD2463D, 0x8A5639CA, 0xC995AC78, + 0xCC4BE4F6, 0x3AFE7F8D, 0x66993D04, 0x4386FF37, 0xCBC1C6C2, + 0x55A8F5EC, 0xE81A9A75, 0x30A67E1B, 0x4A4A7D0C, 0x20F7F993, + 0x1891805, 0x738976AD, 0xD426E7D6, 0x3C5CEEBF, 0x4499187F, + 0xABF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456, 0x421BCF29, + 0xF6740F9C, 0x8916BB8D, 0x3D72AAB, 0x9AD54DD7, 0x7549C6EE, + 0x7317342B, 0xA18546D4, 0x1056BDA7, 0x54BBCCCE, 0x8CE63E46, + 0x5D146234, 0x33BE6C63, 0xB250C4E5, 0x89D72335, 0x87C36BA, + 0xB65530CC, 0x2DFAC48C, 0x1663D16F, 0x59B80AA, 0x950274EA, + 0x92532D4A, 0x3CEF802D, 0x492FBDA5, 0xA63A2574, 0xEF8005C2, + 0x94A18651, 0xAF627ABA, 0x6829B238, 0xA698F646, 0xD2598516, + 0x10144D36, 0xD9B1D1B9, 0xAB2ACF05, 0x5395B699, 0xA7851C75, + 0x1806C6F3, 0xAE970306, 0x3284B145, 0x98F4FE8F, 0xECDD35CC, + 0xDDC1EE0E, 0xC4848865, 0x925826BD, 0x4078BE39, 0x68A8561A, + 0x323045DC, 0xA933B37F, 0xBA2AEE2E, 0x4F24F65D, 0x349EE246, + 0xF97B9D0E, 0x46DC5759, 0x4529F425, 0x80D17B42, 0x8E16F709, + 0x1B42206A, 0x4934A526, 0x391BB6DE, 0xB52EF45C, 0x26C30290, + 0xCBA23CAA, 0xA501A8C3, 0xD922C4F8, 0xE8824E53, 0x6F4255DC, + 0x5960B544, 0x58BC69D6, 0xCA936323, 0xFDDF053C, 0xC2E002D6, + 0x7D750755, 0x8A3F9CD1, 0x35F8F6F8, 0xFB7BD154, 0x65CFF94F, + 0x390A58DD, 0xD97C4093, 0x501CA2A3, 0x8EA5DEBC, 0xCA93461F, + 0xE02D984C, 0x126F8517, 0x39FDD887, 0x46241AE9, 0x777E854D, + 0xE2B36349, 0x58E3FA9F, 0x971DEF1E, 0x8E156228, 0xC0E14E9, + 0xA9A01BE6, 0xB318C990, 0x971680D6, 0xA1F359CE, 0x487E23F4, + 0x7DE465B0, 0x4E4C905E, 0x2A652959, 0x116FF167, 0x5C74AAB9, + 0x4FEFC920, 0x28DF4EB8, 0x29EBF45A, 0x1E350CF6, 0x7134F224, + 0x22CCF1B6, 0x3890ACCD, 0x9BC304F0, 0x7A37B14E, 0xF3724F9C, + 0xDAC493BE, 0x504692EB, 0x82A56D75, 0x42BC73F0, 0xADA92177, + 0x2D9D9FD2, 0x41D874F, 0xEFCFD8FE, 0x8E83A5A2, 0xB84AF0DA, + 0x65F9B035, 0x6DF4EEE0, 0x7D403714, 0x1CCB8B3A, 0x25B30F14, + 0x5384B044, 0xD21FB429, 0x2C407A2, 0x88622917, 0x92D49C25, + 0x845AA406, 0x532D7675, 0xC0B7713D, 0x30E6933B, 0xD270DE3B, + 0x78771A87, 0x1949A28, 0xAEC00040, 0x10A092F4, 0xBD9D5066, + 0xDE166CB7, 0xE8ECE4D3, 0x867417C9, 0xCF0657E4, 0xD7D550F7, + 0xCD472B6D, 0x8CD0F002, 0xD7D47B7C, 0xA2E5475F, 0x2B66B40, + 0x397A7C9F, 0x6C4BC024, 0x9FDA402, 0xD981917E, 0xA3A6C8E, + 0xC9A42042, 0xCF0D1D5B, 0x1A96C11B, 0x9271030B, 0x4BD5D13C, + 0xCDA08C03, 0x1E4B3256, 0xDBB263E, 0x94B1E758, 0x5CF0232F, + 0xC76F252E, 0x27FF7F55, 0xA55DC287, 0x72886B75, 0x38AA73C2, + 0xA5759CFB, 0xF0A75C8C, 0x7059CBE3, 0x6519FBE2, 0x8C3B4162, + 0x5A19A4DE, 0x9D93E753, 0xA9EDF8B5, 0xD68126CD, 0xEA6A7399, + 0xA73005B4, 0x45BC5168, 0xABD166BA, 0x4D0CC0DF, 0xE1376FF9, + 0x393FB309, 0xE995744E, 0xD5EF71BE, 0x66C2BF35, 0x88D62A85, + 0x14121E08, 0x7006CE98, 0x7F0A7076, 0x7DB9C751, 0xDC7056CD, + 0xC1517CD, 0x65BCE88, 0x1B0F1E71, 0x54C2DA11, 0x101BFDD8, + 0x28096AAD, 0xC365859F, 0xACE13396, 0x7CB432BC, 0xB19EA011, + 0xAD9BC7D2, 0x3AF387B1, 0xCCE30470, 0x5335FC46, 0x40D13C16, + 0xD548B4CC, 0xC476A7BD, 0x66BC0663, 0xB7C6960F, 0x12D1E821, + 0x9A536C48, 0x42641630, 0x740C9A48, 0xF61664E8, 0x3B11E69A, + 0xBD79E1F1, 0x3F930B7D, 0xD98B085D, 0x2151962F, 0xD4D7F80E, + 0x88975123, 0x5302989, 0x12F5CA2B, 0x37C29573, 0xD1D2A3A6, + 0x46DA55DA, 0x2EC8C098, 0x802A42DF, 0xD07A11E5, 0xD5BF4B16, + 0x171BCB96, 0xB5843001, 0x57BDCAA7, 0xDDD36F33, 0x633D0AA0, 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0xAC18A45C, 0x74DE3ADE, 0xD0E6FAD4, 0xE10C242E, + 0x797DF7BA, 0x812CD7B8, 0xED45B681, 0x8F6CCDE8, 0xC2376DFF, + 0xCABE35D6, 0xD450395B, 0x13493CE3, 0x870E1BF5, 0x7B0BF341, + 0xEBD572F2, 0xAE22B3F1, 0x7ED22DF8, 0xEFE826ED, 0xF147F4BD, + 0xA12DA6F2, 0xF3871967, 0xE4423B70, 0x298472D9, 0x45E03E3D, + 0x2BE705AC, 0x41E3AE6C, 0xA29DF92C, 0x54B33739, 0x8EA8F7A9, + 0xDEFF7BC9, 0x77D06961, 0x71981BA1, 0xBA5A5647, 0x4A8E0E2E, + 0x9F519F5D, 0x31BBA940, 0x3D3A0532, 0x7090F0AD, 0x8B47D658, + 0x8D198BAF, 0x9ED929B6, 0x323BB81, 0x97210404, 0x7B8790DA, + 0xD8438C25, 0xDFBB1C93, 0x2C3F415B, 0x14738C42, 0xB46C2C7A, + 0xA3627CAB, 0xFC540D08, 0xE8227979, 0x672B87FE, 0xB257C949, + 0x9C2B31FF, 0x97AAACA8, 0xC662B448, 0x5BFEFC7C, 0xC2FDEDDE, + 0xAD306CED, 0x639A2576, 0x9ECC1378, 0xA72D71B3, 0x94E11CDB, + 0x8BF14832, 0x945C1728, 0x49AE595B, 0x526DD500, 0x40A7D344, + 0x8EB1DA34, 0x731E17C5, 0xA7CF41A4, 0xCB068104, 0xC842B8E, + 0x7F5733E1, 0xAC9CB3B, 0x2E3F58C0, 0xFD8BC4F, 0xFFBCBBAA, + 0x620248F9, 0x27AC344D, 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0x75F665AD, 0x6ABADB10, + 0xAB43129, 0x26B7A5B8, 0xA321DDBD, 0x467AD732, 0x153A1AE, + 0xAD6B1842, 0xBE19B6BE, 0xC1E22C82, 0x73372EA5, 0xF9EF4AD7, + 0x24C81977, 0xD8451807, 0xCD10ADC8, 0x8FBD95E2, 0xE0789969, + 0xC77A80F2, 0xF1165BCE, 0x3488C653, 0x16F3E378, 0x8D71B29A, + 0x628EC98A, 0x40963234, 0xF918E028, 0x9A584D33, 0xC174E2FE, + 0x417C5145, 0x1C751175, 0xB21E0C12, 0x30218ECC, 0x9D7731BD, + 0xA07DBA0F, 0xE7504D39, 0x3E37F16B, 0xD3BAB050, 0x6F3DE64, + 0x1998A7BA, 0xA61A6D07, 0x424FBED7, 0xCD6B3236, 0x68E71248, + 0x58CC3DFB, 0x584FA4F5, 0xFFE8E2BD, 0x9F0E3D75, 0x788DD779, + 0x978ED891, 0x7E1BFFC8, 0xB812A1C9, 0x5CCC1A32, 0xF1A47219, + 0xD6BA6E71, 0xAFA86EB5, 0x28D128E2, 0x9EDD53B, 0x9AAB7E9C, + 0x493B76F2, 0x31C5C89, 0xCE5FC3B6, 0x974CC3F5, 0xCBBD90FB, + 0x61DE988E, 0x99B927CB, 0x972EFCCD, 0x2719AD6, 0xE06E4B29, + 0x48215B1, 0x37EDE8E4, 0xABF9F87F, 0x8BC1C626, 0x5B19EC05, + 0x212A2AE1, 0x28446975, 0x20D04126, 0xFC453267, 0x967D9524, + 0xDF1CDF8, 0xFB17DCA3, 0x11E68AC6, 0x3AD7D667, 0xD133EF43, + 0x5EC41DA3, 0x587AA639, 0x17ADAE3, 0x816DF77A, 0x37D0726A, + 0x49DC33D9, 0x6C9737E, 0xA6A2F950, 0xEC5F352C, 0x50D1E06D, + 0xC10009A6, 0x2F70F8BE, 0x382269B1, 0x4C29E7CB, 0xBD474FF3, + 0xD19A4F6, 0xC3CCE458, 0xE09B348, 0xD15A0DC5, 0x1C10D20E, + 0x4AFDED15, 0x3C109DC1, 0xD8C117F5, 0xB501DDF5, 0x39C92B5F, + 0xE76FCA13, 0x76DBAA1B, 0xB0730EBF, 0x67DD1FBC, 0xD8B87AB6, + 0xA826225B, 0xAB2F7089, 0x499FA36D, 0xF26455B, 0xDC79F8EF, + 0x987E765E, 0xA13E60C7, 0x500C7803, 0x492C871D, 0x970DE4EE, + 0xD1423DC1, 0xB66048A3, 0x804895AB, 0xC079A15F, 0x5E6FD682, + 0xE936476E, 0x8DECE38F, 0x76A011D, 0x53575B91, 0xB263D36A, + 0x8F2624C1, 0x26B34937, 0x75A7EC2F, 0xE33ED24, 0xBF1BE7C7, + 0x8D6BA785, 0x1D9FE802, 0xB8F4EC20, 0xD5C714B2, 0xC1326D06, + 0xFCA78B3F, 0xC0065015, 0xA4B9F286, 0x53F92A8B, 0xF4B02DBB, + 0xEC47E64C, 0xA29FFB12, 0xBA94FFB2, 0xB6980EB2, 0x7415C83F, + 0x93F91A24, 0x4C6F7615, 0x34431174, 0xC7D63B4, 0xB1599158, + 0xA3A01FCE, 0xBD477764, 0x6B16EC41, 0x772D8BF5, 0x90F0A785, + 0x8F72672C, 0x7AD22CDC, 0x70824998, 0x1BED16D5, 0x596E84FF, + 0x48B5B4F4, 0xB20D0B81, 0xF00F7AFF, 0x80F618DA, 0xD10AFE11, + 0xA8EA3109, 0x91BA5E43, 0x31345A01, 0xEB0EF0F8, 0xCC6E7FB5, + 0x3348AE52, 0xEBB124D9, 0x447E58B1, 0xF2A3D592, 0x7F3EE5D8, + 0xD3D7B836, 0x9C98DCD4, 0x27F0B7A0, 0xA9655FD9, 0xAB48E5F8, + 0x7F996D8E, 0xAC13B08B, 0x2530AC6D, 0xAA542552, 0xD4E6B42A, + 0x6432AA64, 0xEAC84F76, 0x41D5F959, 0xCDE91DDF, 0xA0AA485A, + 0x6453698, 0x277C18A4, 0x161A497, 0x66FECAE2, 0x1B64683, + 0x948DD228, 0x1F3C5950, 0xFFC271FB, 0x15C4DF12, 0x7C78252B, + 0x9D4EBB89, 0xE6FA1D49, 0x6B032100, 0xB65DD3CC, 0x106BC9B5, + 0xE0223D45, 0xF7779B03, 0x4B0EA0C2, 0x3CB5AAF2, 0x9A458E5F, + 0x524090ED, 0x3BB1F18F, 0xB4DD065E, 0xA8F13E4F, 0xC4949ABB, + 0xD8142D31, 0x99069DE6, 0x989D2A16, 0xC72D929, 0xA2AC5754, + 0x7E29B714, 0x6E25C15F, 0xE8777078, 0x467DDCEA, 0xF94B2ACB, + 0xDF429476, 0x69AE316, 0x363C664D, 0x85D6AA1E, 0xD727E39E, + 0x5AF440A3, 0x2F0BB16D, 0x461D52D, 0x610559B6, 0xC28066D9, + 0x3C13AE61, 0xA965B865, 0x2BCE3D4A, 0x361C4848, 0x46B94657, + 0xF2AE634D, 0xD7FD4B8B, 0x70C175D8, 0x33128DF, 0xB9718A3B, + 0x8EF80C0F, 0xAB12E738, 0x124B8055, 0x43448325, 0x9F05E427, + 0xA0A9F843, 0x57A9A3FA, 0x492EEA32, 0xE73D2B18, 0xF3113C2C, + 0x2BA9B42D, 0xFF0B320, 0x3A18CD71, 0x59804367, 0xC37F9B87, + 0xB8A990, 0xAFE9F267, 0x1892892B, 0x25B9C66D, 0x52D4056E, + 0xCC1508CA, 0xAD213DB2, 0x8B43F743, 0xAA9705AD, 0x9BC756A2, + 0x43F42526, 0x596FEE87, 0x2B8AFF32, 0x46DEDB48, 0xBF06317C, + 0x876D4CF2, 0x16951456, 0x2B051AFD, 0xFD093E9D, 0x2F113180, + 0x77BFC4C0, 0x29200C52, 0x182D384E, 0x54AE29E0, 0xF90961E8, + 0x6072B8F8, 0x3D346F4E, 0x9AA5DBA4, 0xE5E22EC6, 0x392170DA, + 0x40939B9B, 0x65B89151, 0xC54AB94, 0xAD7280BC, 0xA3D4395E, + 0x3B5754D2, 0x9E77A6A2, 0x9A737F56, 0x9B2D432D, 0x8FDDA7E7, + 0x5958516E, 0x7F52CD74, 0xC1761A50, 0x2B80C01F, 0x5AA99F54, + 0x36FAA395, 0x5DB4B3AD, 0x82024C73, 0x988CEFE0, 0xB44498C0, + 0xF9561A4, 0x280470E6, 0x6966F3A0, 0x47E374F4, 0xF00F4CFF, + 0xBC5C4DB2, 0xE287924F, 0x1ED57369, 0x484FE06D, 0xE92E6564, + 0x7429DAD2, 0x1473AF49, 0x9619E0CD, 0xE6EC2B63, 0xF7A983B5, + 0xEC43C28F, 0x4C98EBE7, 0xA61FDF89, 0xA867E5ED, 0x1088A7C, + 0xCF1CEAE8, 0x223AA207, 0x686F4F7B, 0xEBB013E1, 0xDDC01886, + 0x77478D4E, 0x2FFCEAEB, 0xFCA58846, 0x1208668E, 0x32F8252, + 0x65C9F3ED, 0xC7584B2F, 0xF3EB26B2, 0x90890270, 0x5D97ED04, + 0xF5B5B18A, 0xCF415DF9, 0x4CF4683F, 0xE2E3F29F, 0x850E4BEF, + 0xDBABF6E2, 0xBD183286, 0x2F36215C, 0xD8CA1DD3, 0x4309CC6F, + 0x9FA52446, 0xBD94348E, 0x8693D9B6, 0x61E880C2, 0xA1851D5E, + 0xAAB94F80, 0xF8919C00, 0x74D82ECA, 0x4466A1B6, 0xA0A98E8C, + 0x95B6D1D, 0xE5393A4C, 0x5A40CFFB, 0x67013370, 0x571B0FDA, + 0x9E7E805C, 0x15E32653, 0x2CFE7902, 0xA02E0906, 0xA8883783, + 0x7A68B719, 0x3402833A, 0x68BFD324, 0xE0B43DA3, 0xF9DB0F, + 0xC9510610, 0x690D30B, 0xE79AB417, 0xC917E4C0, 0x7B05CE55, + 0xE116EFDB, 0x69E3B158, 0xF91ED58D, 0x1832D16A, 0x91F4EA17, + 0x3D24C408, 0x76A2C6D0, 0x99B19825, 0x2BF52475, 0xAD49289D, + 0x66238CD7, 0xAC1571F5, 0xA2EABC02, 0x889337AE, 0x3219AFFB, + 0x104B8779, 0x810488A8, 0xAC35416A, 0x2C6DEF85, 0x2ED109F5, + 0xCC8C6732, 0x97CD8E90, 0x339F3E81, 0x91486206, 0x2708D41D, + 0x1F2B19A7, 0x51A60303, 0x5E90E440, 0xB63092C8, 0xF1031823, + 0x971A06, 0xB624F6A2, 0x58AC0181, 0xA983D599, 0xA776D877, + 0xB727FE1, 0x55AC01B1, 0x4298EA17, 0x4D6BB9AA, 0x31C55C65, + 0x6A266780, 0x4FD92256, 0x817DB37A, 0x46A14DF1, 0xEC7D9F14, + 0x98D1C1B7, 0x911DF80D, 0xBFBF24E1, 0x9B4DBC6A, 0xE1F71BA4, + 0x9EE5E44A, 0xD1868C4C, 0x6FB45D76, 0x11EC8672, 0x1CED7F0C, + 0x1524A040, 0xA49DE9D3, 0x99FF328A, 0xC392F619, 0x52A856CC, + 0xDB0B0AE6, 0x67F0162E, 0x2C20D410, 0x4E23C4D, 0x828032EA, + 0xC2E7DFFA, 0x908CF524, 0x919F61EE, 0xF001C6F, 0xA81DDF65, + 0x5EC56647, 0x28385ACF, 0xBDD764C0, 0x75C853AB, 0xDF0ADD73, + 0xEEA9C63D, 0x804949F5, 0x658ACD0A, 0xD12F3F50, 0x1FD4F7EE, + 0x7F023D80, 0xD2CB08B5, 0x477EA9A1, 0x872DB719, 0x7B8B6AE9, + 0x84F6AC4, 0x81634EB4, 0xD1A89CF, 0xB3F4F3B9, 0x3A6B024B, + 0xAA2CA2C5, 0x9C902C0C, 0xC40E4135, 0x3C6E612F, 0x11219414, + 0x1F184277, 0x11B6B30C, 0xDD8A6A5A, 0xA0D21C9D, 0x55377022, + 0xD0708FBD, 0x8D761020, 0x54FCFCFC, 0x477801BD, 0xD6919EB8, + 0x9AD29078, 0x36F8D9B8, 0xAE525B8C, 0xCA7ED140, 0x2D8F8B97, + 0xD1B79EAA, 0x2E26FB2A, 0xFB396E32, 0x399129A3, 0x28B55FA1, + 0x2ECB2CF0, 0xDF1CBF7C, 0xDE57A70D, 0x33410B33, 0x7C5759BF, + 0xF534264B, 0x16C8C221, 0x874A3A63, 0xD05808ED, 0x679674BC, + 0x24B060C9, 0x4B162B53, 0xC7D01208, 0xE753DE61, 0xFA9840E4, + 0xA4FEC439, 0x4143E13F, 0x327E9EE8, 0x319D901E, 0xC40FC209, + 0xB1E1FFFC, 0xE737D52B, 0xD074E058, 0xAD8892EE, 0x86B93396, + 0x49C13F4B, 0x60A5721C, 0xD4C4F599, 0x14B38EBB, 0x86BA655, + 0x95F4E0C, 0x4217E99A, 0xD0CA3861, 0xBDD3617B, 0xB0BDBF4D, + 0x99E3389A, 0x8200DCFA, 0xEC22C8AC, 0xBA8DDB32, 0x3F7DDFC8, + 0xC7DDC171, 0x211CF31, 0xCC31A0C7, 0x99A84F32, 0xC9FFD317, + 0x2267733A, 0xFBD05569, 0x306BC05F, 0x6E2685D5, 0x43FBF7D1, + 0x5A2DB2D3, 0xE6491D4B, 0xAD078066, 0x7CAF7AAD, 0x2B1FEBA5, + 0x3418A0EC, 0xC359E9B7, 0xB024E024, 0x58F22A6B, 0x18EEE710, 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0x2CA39696, 0xE460F7D1, 0xCA32CCB3, 0xA6D9D934, + 0xAD01079C, 0x9B07D89C, 0x226CE0A5, 0x60D67762, 0xD35A4B7B, + 0xFF0A698F, 0xDB73BF89, 0xF41FBA9A, 0xCACDF26D, 0xBF594213, + 0xCD4D3E90, 0xD12F3EB8, 0xE689D238, 0x8CD4C0CA, 0xEB3E841E, + 0xA513EF0F, 0x2DF4B65D, 0x90161625, 0x9C02AC36, 0x208F328D, + 0x12BF5D93, 0x7C8C355C, 0x3CDFCA22, 0x29381080, 0x3FF6CA14, + 0x9F269C74, 0x8A48070B, 0x3BDF51BD, 0x85932156, 0xA7B6F9FF, + 0x80554507, 0x43820D97, 0x59B7214A, 0xFC3ECC27, 0xED39DB19, + 0x2B9BDB43, 0xABD4E298, 0xC2C5953E, 0xD3DB0C09, 0x66EC81DA, + 0x7F41EDE1, 0x5146E8D7, 0x49171DF2, 0xB334BF9A, 0x3AADC9E6, + 0x56E12468, 0xA2D4B032, 0x662B1F49, 0x9C448B1F, 0xA219526C, + 0x56D66A27, 0x41609345, 0x8E685EFA, 0x392DA3A4, 0xDE58C26B, + 0x9C779FC9, 0xCA834F65, 0xA1E34DC4, 0xEC5BE6EA, 0x3737B7AB, + 0x2E9B7D0A, 0x929E96B9, 0xE38B0019, 0xC1E4115B, 0xD8141740, + 0x66977F67, 0x7D4CE4B3, 0x245AB554, 0x26F98B88, 0xEC78F24D, + 0xE1F34C1A, 0x5737AD34, 0xC1A19AC6, 0x3291E363, 0x4E824FF3, + 0xAC42BDF3, 0x7C2DACE8, 0x8D5C97F6, 0xD120875, 0xC4E5C39D, + 0xE22AE85D, 0x290FF39D, 0xD495E52A, 0x95414374, 0xD65757A6, + 0x1E7657F9, 0xF5073D56, 0xC2AA7589, 0xC166A0B3, 0xA0DF8CDE, + 0x4057EAE5, 0xBAC4DD2F, 0xB51F621F, 0xA96F90E3, 0x392B5D6F, + 0xC31E9CA1, 0xCCC02FD3, 0x5181074, 0x7BC15C18, 0xCA9232A4, + 0xD1D104E9, 0x5F0C5D3, 0x4947F6D2, 0x3C923E97, 0x6B486C35, + 0x9C8ADA96, 0x175C4D87, 0x39A1A0FE, 0x417F201B, 0xD080E114, + 0x4847B147, 0xFD634E49, 0xBC0BF4CA, 0xECABB1DF, 0x869B0263, + 0xCD797C28, 0xD2A4683, 0xD50F6A0B, 0x2CA40138, 0x8DA4EB55, + 0x5D198E5A, 0xA98DB40D, 0x96CA0E68, 0xA8D92294, 0xC4813E60, + 0x81CD6B09, 0xEBBEBF80, 0x6777688, 0xCDAF6EC5, 0xEB85653E, + 0x3BB780DD, 0x73718A21, 0x70E8A324, 0x654DE06A, 0x2CB2494A, + 0xFC1DA829, 0x64059A2F, 0x61CE9D0D, 0x5BC51CAB, 0xDF7DE6AE, + 0x1596B477, 0xB0F9EA86, 0x9D87D85B, 0x877620A7, 0x586F3AD6, + 0x96AE645E, 0x65E9D5D7, 0xDB69CEB, 0x2753EF35, 0xC226F633, + 0xBD373F9D, 0xF2A0E198, 0x4372EEC3, 0xA66F7010, 0xD30E1D18, + 0x152C0DFB, 0xEB86FC75, 0xC208FE7E, 0xB36625A4, 0xBBE2DE8, + 0xEC49F9C9, 0xCE724FFE, 0x2D509471, 0xCA6C24B6, 0x1BA93DDF, + 0xEABE9550, 0xB512D359, 0x83F76766, 0xC8267976, 0x7E50802B, + 0xE3EC2199, 0xD3269B8E, 0xC515B0CE, 0xB5752537, 0x70474BD, + 0x7F50EBE, 0xF9FC0B38, 0xD899D19C, 0x317AA41D, 0x6B706374, + 0x66479538, 0x560455A3, 0xD770DD85, 0x55BB61BD, 0x6DE6723A, + 0x3F89034B, 0x9C9650BC, 0xE569992C, 0x7B8F4D95, 0x3FB7C516, + 0x7C28C04B, 0xA12DE6B9, 0x8CFC5AFE, 0xA734A25A, 0xCF1483E8, + 0x1AB22339, 0xAA94F43F, 0x16319A1E, 0x2C9AA4D0, 0xE9D2618, + 0x790B699B, 0x3AD9C3A1, 0x55A778DA, 0x6517152F, 0x2139AB74, + 0x12F762CC, 0x4BE02E6F, 0xE69400F7, 0xDC48DCD0, 0x563DB028, + 0x32299125, 0x7C9145A9, 0xFB88067B, 0xF070F6FF, 0x3D9A42FF, + 0xC5D20DC, 0xF96F7EE1, 0xA9C209A3, 0x9A192F36, 0x3E158AD, + 0x1265DF79, 0x2E49E297, 0x99D3A002, 0xE6AFDDCB, 0x3B56751D, + 0xB248A31F, 0xE6BE0FFD, 0xBBAB635E, 0xB383C45C, 0xA9DC9F2D, + 0x735CE03F, 0x69992E32, 0xD1E6A77, 0xE38A7F46, 0xC1E59620, + 0xFAE7F99A, 0xBDFB440C, 0x9F53F99C, 0x224EA340, 0xAB5D1AF0, + 0x35F3126D, 0x99430549, 0x83E12C62, 0x6403957B, 0x7B119103, + 0xC8382BAB, 0x99A85991, 0x9BF370AF, 0xDFA83CAF, 0xDBEC2CC3, + 0x416D8EBA, 0x774E58FF, 0x29C222F, 0x3DE60561, 0xDF038931, + 0x8297C377, 0x9867C08, 0x58ADEAED, 0xD88F0856, 0x6E4C2A39, + 0x2599DF28, 0xD7A6D06A, 0x433B35BE, 0xDAD3175B, 0xC358D423, + 0x84BF4580, 0xE7D3BE65, 0x9EC8CDBA, 0xCE901946, 0xC4B4D088, + 0x98B1245D, 0xFBB0CC10, 0xE8CB9C76, 0xDE665AF2, 0x28E46D8B, + 0xF7012A56, 0xE29F8C07, 0x8BF87AFB, 0x2907C051, 0x820923CB, + 0xC3E95542, 0x6AB5559E, 0x314BD068, 0x1CEB5637, 0xD1D830D, + 0xC442D6C2, 0x5F6074F4, 0x37F08A2A, 0x21F782BE, 0xF378B1AE, + 0xB7FC74DA, 0x4ACB450F, 0x365F3092, 0xFB0C842C, 0x5DD80554, + 0x741C4F79, 0x290716E0, 0x76E56BA9, 0x10006310, 0x42A183C7, + 0x5F1FB962, 0x8DE2BA39, 0x6176B6D9, 0xFC059A44, 0x9907DE39, + 0x71A5EA7B, 0x42309616, 0x1DDE34DD, 0xF0DFA4BF, 0xF69B5E2F, + 0xD145268, 0x49A3E7B, 0x90508840, 0x861DE564, 0x904730CB, + 0xC844CD6F, 0xD5A2CEB6, 0xCE895F0D, 0x73EEE4D6, 0xEB4565CF, + 0x533ED4ED, 0xF4AAB655, 0x591BC278, 0xBD1D929D, 0x80AD7DA6, + 0x527B3C51, 0x40F627DD, 0xDA420FFD, 0xB9A6F685, 0x5F6D9BC2, + 0x4F67DE58, 0xFB5F87F0, 0x47540936, 0xB2083BC8, 0xAD48DD69, + 0x63F7CA5A, 0x28D5372D, 0x61DA54B0, 0x7DA88170, 0xA2DA7B83, + 0xE1D70E32, 0xA3ADEA46, 0x97026868, 0x60FA4303, 0xA4104416, + 0x3DB4A8CC, 0x72F0F53B, 0xFF270297, 0xD5600E97, 0xD7D25D62, + 0x46DBCAC5, 0xFD61775D, 0x93E100DB, 0xBFE0E0C0, 0x8CE51426, + 0x8216C272, 0xE7300A56, 0x5A61C30E, 0xA7667C78, 0xBD23D39B, + 0xDC425756, 0x7AE9A42B, 0x249E8C42, 0xABB91D5C, 0xBD1334D5, + 0x8BCE967D, 0x5CF89EEA, 0xDB125339, 0x225E3C4C, 0xC5DDA12, + 0xA92903F8, 0xF2F29634, 0xD2AB3419, 0x396DAE59, 0xA02C965E, + 0x450B8DEF, 0x1E4911B2, 0x4F94BA94, 0x6802E7C0, 0x779671B7, + 0xC0B06A93, 0x65BF0119, 0x3D672B7F, 0xE7E68CA, 0xF173FBF, + 0x503C50F4, 0x3D8CA779, 0xD9BC10B2, 0xE6B89F78, 0xFC04B6F2, + 0x74B0E1B4, 0x3BB8594A, 0x5866C0E6, 0x125FBE40, 0x21239465, + 0xC00E2791, 0xD7957B76, 0x331D18CA, 0x87D0C340, 0x8D7347DF, + 0x296D2AA1, 0x8EAA71DF, 0x1D477388, 0x4F666705, 0x211D2B0D, + 0xA41C0741, 0xD8F7CEEC, 0x4C6EDC5E, 0xFE5DC02A, 0xAA83AED3, + 0x9AE501A6, 0xFF82168C, 0xDC638114, 0x4C345BA0, 0xDD7E0F1D, + 0x4C072ABD, 0xFF606768, 0x3CE74279, 0x93DED13D, 0xAB7A9752, + 0xAF27666, 0x784EDE4F, 0x7F4BE8A7, 0x9A45141D, 0x69E507FF, + 0x78BAC3AC, 0xDB2A62AC, 0x52561515, 0xA9DFA9A8, 0xCC51778C, + 0x886CC6A, 0x5246AD23, 0x68A7480, 0xBC267A85, 0x1FF771F4, + 0x5199BC1E, 0xF8CCD05A, 0x7BD65764, 0xC61A33FA, 0xC9F24B8E, + 0xBC0B1D9F, 0xE43E103, 0xBE3D7AAF, 0x39154AD2, 0x941C2098, + 0x1C26174D, 0xC63D21F1, 0xFBC6D732, 0x8C43AE71, 0x1495C044, + 0x9483EE96, 0x909A94F0, 0xC1B02D9E, 0xDF9A2114, 0x2F4883E9, + 0x4806958A, 0x209A2722, 0xFE514205, 0xEB85D85F, 0xC25BED82, + 0xEB2CEABE, 0x8B2A2EDA, 0x68641725, 0x10570304, 0xE53EE68B, + 0xC43FB1C1, 0x8F763232, 0x41ECC1D0, 0xE3E44CBD, 0xA1A68EC0, + 0xDAFA770A, 0x6996A5A8, 0x38407C06, 0x4FAD77B4, 0xE30E2912, + 0x47EE2FD, 0x2CDA167F, 0x88F915F1, 0xF3DF6195, 0x530FBEDE, + 0x2CFC1C0C, 0x47B21171, 0xDEC1A586, 0x2031A43A, 0xDAAD77AD, + 0x8BE637E6, 0xA6AC1EBB, 0x6AB9F2A3, 0xBFB5ED6C, 0x15792C44, + 0xFD3AB89D, 0x27A7E24E, 0x3E76999F, 0x77EE2E6A, 0xE505F3B7, + 0x429839A6, 0x6BEE7B15, 0xF61F0084, 0xFC20752C, 0x4BF79989, + 0xC8B4F8E8, 0x46B33427, 0x9F4BA3E8, 0x41B9354D, 0xEED27E23, + 0xA7FC575F, 0x279180C5, 0x141C3A06, 0x2C2FCEF9, 0x4403AA1F, + 0xD4496B6C, 0x25C33091, 0x452C754, 0x80534A0, 0x80842F72, + 0x3DB756B1, 0xEFD010BD, 0x1DE7F9EA, 0x5F9B1769, 0x55D9839F, + 0xD5B11F46, 0x941D69AE, 0x8C4F3D35, 0xE710E268, 0x2DFBC983, + 0x5D417C19, 0x7C2561F9, 0x25415FCF, 0xF331B119, 0x235B632F, + 0x9B1463A9, 0x8249E513, 0xB6F14826, 0x1005E62C, 0x2B1B4F3E, + 0xEF793550, 0xA90F6AA2, 0x77BFECE6, 0xA6E1C13E, 0xBCB6E143, + 0x2496D0ED, 0xF4A8D5F0, 0x29C27A0C, 0x7D231D55, 0xB8526623, + 0xDDDCB82C, 0x2A18B465, 0xB5FD564D, 0xA9647CB5, 0x4300919B, + 0x9FB2B27A, 0xDB25B0D9, 0xBB5D5711, 0xAA747FC4, 0xAA831194, + 0x9603ED14, 0xAF921A0E, 0xFA1447D7, 0x8B766768, 0xE8F1C89E, + 0xB7985D4, 0x6C5C1AEE, 0x2EA66EF3, 0xD176E7D9, 0x228CD940, + 0xD90C84B4, 0x36253A66, 0xADD7AE4F, 0xF25D5CA5, 0xD34F702F, + 0xA535AA29, 0xFCF10FB, 0x3D075696, 0x63EF7EF3, 0x81554091, + 0xC7EEFC78, 0xE0DCDB21, 0x62EFF001, 0x9ACFD7CD, 0xAEBA43ED, + 0x371BA99B, 0x508B7A31, 0xFF447B05, 0xA239F5D2, 0xA5620A57, + 0xA16B995A, 0xC334401E, 0x535F51AB, 0xAEA26D82, 0x81D72269, + 0x3C0BA1D2, 0x80590850, 0x818A26AA, 0xC43E6B02, 0xF72DFB63, + 0xE7AE3F6A, 0xD31AB683, 0xB99D787A, 0x691FFB53, 0x37EA1E35, + 0xC2C9FFF8, 0x2A13F6D4, 0x4CC79564, 0x6DD5F2DE, 0xC53560B, + 0x5A562B6F, 0x3F2C49F1, 0x6953F4CC, 0x8BA12AF2, 0x98A08428, + 0xA1EF80B3, 0xA977E388, 0x1A3DD9D1, 0x687A3424, 0x2759B568, + 0xC626A765, 0x7887651E, 0xFC9005E1, 0xE84376A4, 0x387BCF66, + 0xF7AA4980, 0xBAEE372C, 0xE89CF460, 0xA275FC1A, 0xA5EF8668, + 0x899F85CE, 0x9CB086A3, 0xF16158AC, 0x4C49EBC0, 0xDCE10FAA, + 0x4B46ABDA, 0x56947FA1, 0xAD4E7245, 0x54C23373, 0x8B0B6C4D, + 0x82590F05, 0x5E292D4C, 0x277B63C5, 0x9D51D8CF, 0x86D379EF, + 0x52CBEF63, 0x7A62AF4C, 0xAC1FA33E, 0x25D454AE, 0x1CDA792D, + 0x17434813, 0x759F50A7, 0xEEB0D38A, 0xB30964A6, 0x941230A0, + 0xA464FA3C, 0x9F8685AF, 0xB9A018F4, 0x8080362, 0x2D565F63, + 0xAB60790A, 0x67252A3C, 0x1715B01D, 0x5384E7F3, 0x79299519, + 0xA9786ABE, 0x1107A1FC, 0xE0D9B037, 0x4DD34883, 0xA7D476E3, + 0x5B194AE9, 0x89E50FB1, 0xA9676565, 0xC77CF621, 0x93612BF2, + 0xE027B80, 0x359C7FBF, 0x39B166FB, 0x1F3B28DF, 0x2848DE70, + 0xFFE261DD, 0xB78D413C, 0xE011DD7B, 0x286F752B, 0x74A8D775, + 0x5E540B67, 0xFAF973F, 0xC0035501, 0xB0F16059, 0x1C981017, + 0xD4871112, 0x9745C0BC, 0x6D85B805, 0xA40253E8, 0x2B0D55CD, + 0x8FF7EDC4, 0x47EB4ECB, 0xC41A2F17, 0x41C9702F, 0x8549DEE0, + 0x865FD46C, 0x64A1F181, 0x24E64D11, 0x13337A33, 0xE8CB0924, + 0x8A2DC003, 0x113C04C7, 0x1CA62E13, 0xC360E708, 0x57DE03AB, + 0x4D8F2BB5, 0x2CE2E2A1, 0x2580C90D, 0xBF162A7C, 0xEB1490A8, + 0xBCABC2A7, 0xFBC4C25C, 0xBC83AB6A, 0x25C47DCB, 0x8FE447A9, + 0x2C0F77CF, 0x6D896845, 0x63CEF5AE, 0xB2FF0326, 0x14D71520, + 0xA1C15C8E, 0xE53550FB, 0x676B299D, 0xC20A5C14, 0xDB3EC54, + 0x359733CE, 0x8A619B1E, 0xCDB53E, 0xD285EED5, 0xA6E0181E, + 0xB81AA3EF, 0x41F8E1A2, 0xE3DEDC6D, 0x4F7CBE5B, 0x24006857, + 0xACB9B719, 0x4E725B2D, 0x8536AF54, 0x329509E7, 0x72E7C0A7, + 0xBA97CC78, 0xD822798F, 0x9DFC6780, 0x63E263CA, 0x7B2397A5, + 0xA42C0C0B, 0x1D5EC588, 0x292F1E7C, 0x2BF5A75, 0xFCD8786B, + 0x14EB1952, 0x84031982, 0xA0800A40, 0x629C9211, 0x3B17F481, + 0x50861D9D, 0x8371A304, 0xB3D21511, 0x720E2C6C, 0x5A07F87E, + 0x868F95BD, 0x8617E7B, 0xD7762105, 0x90707C5A, 0x777473F4, + 0x67737DC4, 0xC4154562, 0x1840CEB3, 0x373635EE, 0x4E6D4EBA, + 0x1736A5EC, 0x4D3E335B, 0x59FDB9A1, 0x9162B39A, 0x3F9E1502, + 0xF661B3DA, 0x77BE0255, 0x65EC8603, 0x21FCA0B, 0x55291C5C, + 0x69F57B1, 0x5DE1E0D6, 0xA6296E1D, 0x595A45F8, 0x90B166DF, + 0x61ABB34E, 0xC6D48B5B, 0xB05EF88F, 0x368B0C6E, 0x94C36250, + 0xB435D440, 0xEFB62847, 0x1473E647, 0x9A101218, 0xC7AA11BF, + 0x80C241E3, 0xAF648F26, 0xDF48753D, 0x7073509A, 0xAB52665F, + 0xD1ECCFC0, 0x7BE293F1, 0x396CA014, 0x84336AB9, 0xF9B7E448, + 0x9566C90E, 0x239F7C25, 0x91A452B3, 0x1E9A4F1C, 0xCCE286F6, + 0xF46520D6, 0x2943A671, 0xAAA30DCF, 0x28D190CE, 0x88E3D0C9, + 0x423944F0, 0x81E6712, 0x2714B6B2, 0xF927748, 0x59A5430F, + 0xCBA530A9, 0x91E12A0E, 0x92598CBE, 0xE61058F5, 0x2604B4B, + 0x4CB7C3A7, 0x43B5812F, 0xFD90660, 0xD73DF50D, 0xAD3AE409, + 0xF74D721B, 0xCC2A88D1, 0xCED79510, 0xE64714DD, 0x3BDF0A8A, + 0xC2C7B689, 0x25B387D8, 0x968DA1A2, 0x8EA5D185, 0xF05F03E1, + 0xFDDC5B50, 0x78AECEF, 0xE32FBBA2, 0xD512F0AD, 0x5410D1B5, + 0xDBFD9FFF, 0xC0F2DD4E, 0xF66F8DBA, 0xF5EBA3C8, 0x65F96FE3, + 0xF7C8962D, 0x8E48A78, 0x255BEDC7, 0xE8FD3698, 0xFD1C4903, + 0xFDE9830, 0xCDBCF434, 0x16540D39, 0x418EF731, 0xB2F80637, + 0xDFCC0C9D, 0xB53DC5BC, 0x5A68B10C, 0xC4DCB3DD, 0x8B3778F4, + 0x7788B194, 0xECBD4903, 0xFD390223, 0x79598BFB, 0xBDECB9D9, + 0x29576BE3, 0x220F82A5, 0xDBB262F6, 0x1876EF0, 0xE2D9C444, + 0x32D5ADEF, 0x5F8739ED, 0xAF427122, 0x171E7D7D, 0xA5468BB4, + 0x94451936, 0x51565032, 0x3CE3CD5, 0xF231F54, 0x98614C6E, + 0xCE18455D, 0x958D2BD2, 0xA5934FE0, 0x3543931E, 0x77D9C2FB, + 0x3D3ED736, 0x6762E077, 0xF1B052A, 0x88AF353B, 0xB2A38925, + 0x8C919686, 0x715EEAAC, 0x34BA46DD, 0xEB486F1C, 0xDF58D7CA, + 0x90B97BE6, 0x37335293, 0x499414CC, 0x7F725BAF, 0x5ABEBF8, + 0xE9344F69, 0x1C110FD, 0xA937AD4C, 0xA7CDD9C0, 0x750FD5FE, + 0x7A7B6D40, 0x41EA948A, 0xA10EE17C, 0x7689C967, 0x9F411C02, + 0x6C40C3FD, 0xA6FFC648, 0xC6D6F914, 0xA100AF92, 0x4CD97ED5, + 0x17D9CCBF, 0x915833F, 0x788D78C0, 0xC81903A3, 0x6DE5BAF0, + 0x3E4D6DCC, 0x98415810, 0xEC23B7AD, 0x822471B0, 0xD2CF5D5A, + 0xA1BACAD5, 0x40843135, 0x430135A, 0xA7655BAD, 0x7A2472BE, + 0xCC3D44CC, 0xD1BC9E10, 0x7C215C92, 0x717FA7DD, 0x7EF7D128, + 0x1BC85798, 0x7C6E19CA, 0xE3FAB7E4, 0xBC884D38, 0x3E220CA, + 0xE7AE4D8, 0xC8EDD021, 0xF3F05D3E, 0xDE302EB8, 0x40CEFF27, + 0x56C0550A, 0x96162C92, 0xC004EA48, 0xE0C29A65, 0x496AE22B, + 0xC7468E6F, 0x8E31BD1F, 0xA53763CF, 0x166CC258, 0x1A2B9CC4, + 0xDBBADE7B, 0xF8D21AC9, 0xB21CA593, 0xB92F0DEE, 0x9A4391F, + 0xCDB4D373, 0xB687B3F5, 0x877BF0A0, 0xFD7395DD, 0x1C56AA87, + 0xCA146BB9, 0x21A2314B, 0x8207A2AC, 0xAA874DC0, 0x4F404E64, + 0xB69FDE48, 0x324FD456, 0x45F19CF, 0xFC7E6D0E, 0xC8A01C04, + 0x76C63378, 0xC526F7B3, 0xFDCD2EEF, 0xFFB2F9B9, 0x2DDE75AF, + 0x5ADF2F86, 0xC9AC84D3, 0x70FF53A0, 0x3FB077C, 0xC2795B30, + 0xF5438170, 0x557D7080, 0xB784684E, 0xCD089E1D, 0x332B71B0, + 0x493C3C2A, 0x1D1DED89, 0x8240E170, 0xA7D17522, 0x48C542AD, + 0xCB357D8F, 0x21E37C1, 0x3B000B34, 0xAAAE4818, 0xCD1EB4B3, + 0x1736CA0E, 0xDDF8EA2B, 0x76E21C4C, 0x6EE99A3C, 0x27F71B20, + 0xF6AE929C, 0x3C9CAF6C, 0x5CA7DA97, 0x8EF033C5, 0x8C7EC36B, + 0x3CB1CFAD, 0x1C5ABBB7, 0xDEF7A78C, 0x9CBC4A73, 0xB3871393, + 0x8C61DF59, 0x54DF941C, 0xCDD23FE8, 0x758EAD7E, 0x49BE795B, + 0xC960C6B, 0xE9B76479, 0xC88843F7, 0x82DC3137, 0xEDEE1A1E, + 0xC6568A7D, 0x42F7F484, 0xA6115655, 0x494779B5, 0xD95FE16A, + 0xB2AB15F4, 0x64C185B3, 0x9A46066E, 0x8BAE077E, 0xBAAE323F, + 0x79A965C6, 0x764B71F0, 0x3654F6D3, 0x96B4B2AB, 0x15C2B523, + 0x720AF416, 0xE6D0F423, 0xFAE44868, 0x6E776BC2, 0x264D41A8, + 0x3FE4BEE, 0x1598B97B, 0x15A70419, 0xA13CD124, 0x751A09E2, + 0xF7F7C12B, 0x718AC211, 0x11D03CD1, 0x2F9247BE, 0x77C210E1, + 0xA2268AAB, 0x2E99F0DD, 0x949D5CC5, 0xA8A309F2, 0x749EC6BE, + 0x5BD5124A, 0x8BF599E9, 0x3919AD4F, 0xA40901C2, 0xA1D4CC03, + 0x6ADCA36F, 0x9D5CCB0F, 0x870E2A58, 0xCEBC6333, 0xB2FA28A4, + 0x579C76A, 0x444849D0, 0x33887308, 0xB3BE3C75, 0x93745501, + 0xC289F137, 0x89739C7, 0x97C73423, 0xD627FB64, 0x6EE36F05, + 0x1F4B4B98, 0xFBB7A8AC, 0x60941E62, 0xC3A8ABDC, 0x4AC5E7C9, + 0x88ACE940, 0x5AA2AE59, 0x9F10C0B7, 0x8F45920B, 0x5FDE21BE, + 0x1D47779A, 0x3ED27D8B, 0x69FF2BB1, 0xCB1409FB, 0xF27F4FFF, + 0xA19E3DDC, 0x206050FD, 0xAD98C2D5, 0x4DA4BC0C, 0x95D9B019, + 0x556ABBFA, 0xBC78B5A, 0xF0F224F8, 0xA9785F8F, 0xED1CE98C, + 0xD368072E, 0xE212ACE5, 0xBB7F76E0, 0xB02F237F, 0x6D85C5AF, + 0x31539988, 0x4312BA19, 0x1D5023A7, 0x7320504B, 0x70563ABD, + 0x2553791A, 0xE9768150, 0xC1B2AF4B, 0x3AF0FD24, 0x3818D0E8, + 0x7F356F58, 0x98A15B0D, 0xAFA943C4, 0xB2B38831, 0x2E411F37, + 0xE3D5AF87, 0x67BEEC5A, 0x825E60CC, 0x1C44D856, 0x1A59493A, + 0x13BAABCF, 0xAEAA4D44, 0x5CFF2A6E, 0xFB47865B, 0xE778E607, + 0x101500E8, 0x2C17E66A, 0xA0B30350, 0xFC649CDF, 0x8B9802D9, + 0xAB87D61A, 0x21F38439, 0xD3D11051, 0x1FDA9955, 0xCB9313B8, + 0x327D1A94, 0x35293099, 0xB803B298, 0x5B8E6883, 0xFA309C3, + 0xDFDA8B2, 0xDF89211F, 0x9918F18E, 0xF0C05CB1, 0x71D8A4B7, + 0xE681031D, 0x537012F6, 0x4DF822F2, 0x34B75C8C, 0x4429F85E, + 0x5D3C4C4D, 0xFB0FC6C7, 0x25F4ECDD, 0xB19D5EFD, 0xD70FD7CF, + 0xD95C45D5, 0xCDAC06B8, 0x9C3B963B, 0xAB2F2A9C, 0x4D3D4F7D, + 0x12692C03, 0xB1AEF97E, 0xF243EFA7, 0x78C4C8DF, 0x182D9C17, + 0x8D2AF450, 0x7596BD9B, 0xE8E7C9C2, 0x86F617F8, 0x1F37A708, + 0x3F648305, 0x27FF6DF6, 0x4D5FF17D, 0xA9541C2D, 0x9773013, + 0x78B2313C, 0x82C0B20F, 0xD36A4F02, 0x8DB2BC4F, 0x9296D8BF, + 0xA983CC7, 0x31AEE908, 0x48CD7E6F, 0x9CB1DD7F, 0xAB89D57, + 0x5156132E, 0x6345AA59, 0x8D2CB12D, 0x94D3AE56, 0xA4E91B27, + 0xEE58338, 0x8620EA15, 0x5454D04E, 0x1142ACF0, 0xCA059044, + 0x31811D8A, 0xD498290, 0xB65F1B67, 0x462745F3, 0xA899191C, + 0xB9C19F48, 0x824659FE, 0x9A257101, 0xC330F34B, 0x42109127, + 0x9DA8504B, 0x6C3A989F, 0x5F426E6C, 0x2B922D32, 0x373C66FD, + 0xAFE3418B, 0xE3788682, 0x83B46626, 0xD0106A4E, 0xFD10B903, + 0xB0F6531C, 0xC65419E0, 0x3963952B, 0xB8799DF9, 0x3EEB8C1D, + 0x5C4D3C08, 0x6DD028A6, 0xA55678A0, 0xB8247141, 0xC1267586, + 0xF6746B19, 0x46C38465, 0x483D24B, 0x99BF79DC, 0x78F778C3, + 0xAFF40193, 0x58872B07, 0x6DA7F4FA, 0x66B5CEA3, 0xDD2D8C79, + 0x2A8D289B, 0xB5789670, 0x66AEFCE3, 0x56FB52B3, 0x20FE3BE1, + 0xCCDFB492, 0xB0F263E8, 0xD0707433, 0x5E58F5DC, 0x4ABEBE63, + 0x8A45CD95, 0x97037830, 0xBDB1F1B5, 0xA1BE2990, 0x57B718FA, + 0xD50EC023, 0x810DD849, 0xE650D43F, 0x3895C77D, 0xE142C382, + 0x35551E5B, 0x3B94330, 0xE92D8A91, 0x50BC837D, 0x61499A8F, + 0x2639B468, 0xF8FF36E1, 0x74956FC6, 0xFF0F4192, 0x6BBA0C53, + 0x5B44FF85, 0xBBE4A1DF, 0x12D6CB14, 0x6C679A10, 0x3C0F554D, + 0xECBADA32, 0x8A99BA10, 0x738C03C4, 0xB8902AC3, 0x7008D470, + 0x49BC2ED9, 0xFBE19B5A, 0xA1E4879A, 0x36129694, 0x94987C3C, + 0xE54B84D8, 0x9CFAEF1E, 0x527127DC, 0xA8FCAE0, 0x8699252C, + 0xDAAD4629, 0xC41F3866, 0x2559C272, 0xB1C25848, 0x3F9B1702, + 0x7C448BF3, 0x8CCEDF5C, 0x3A37F712, 0xFB9E4F83, 0x5754E801, + 0xB38FD367, 0x780F4825, 0x959330C4, 0xF6276BE5, 0xAE3E2018, + 0x182DC907, 0x88E733F9, 0x6FF870A, 0x79EF2D01, 0x3EAC0D6D, + 0x20D4FF88, 0xAE6EB8C1, 0x80810451, 0xC228E035, 0xBD942803, + 0x3F3733F2, 0x9F8F16F6, 0xAAA65031, 0x55E839BC, 0x7EAD3461, + 0x5F5BEE8A, 0x8668BDBA, 0x399366DB, 0x2A54237E, 0x776789E, + 0x7B171AF5, 0x8C9FCB92, 0xD87465F2, 0xFA3CAAB5, 0xBA5B131E, + 0x1FD2D438, 0xDCAA9DA, 0xE1BF0AAA, 0x1EAEA8AE, 0xEB46A646, + 0x989D1EA2, 0x98E8B45F, 0x12A2415B, 0xD107D293, 0x5F54D087, + 0x95AF5C33, 0x2A12BA88, 0x6381D0FF, 0x688EA1E0, 0xACC60CA2, + 0xF19636C6, 0xD4D465E2, 0x2A50DC57, 0xFB595CCF, 0xF5C63674, + 0xB4965626, 0xB903D3D0, 0xD9581548, 0xBBD9E82E, 0xE22BCEF3, + 0x9FE759D, 0x6E8D8F4E, 0x655325D2, 0xE1986814, 0xEA2B93BF, + 0x88085C18, 0xF82BFCB0, 0x3FCF713F, 0xADE03EDC, 0x2D2DDCBC, + 0xEDE2694E, 0xF6DFB11D, 0x5CF35A5A, 0xD38C82D3, 0x52DE32CF, + 0xB88EA70E, 0xF7FB134F, 0xAEC78D1E, 0x58402C66, 0x54CD1763, + 0x78A7EB4, 0x88F49C30, 0xDC17F8C0, 0x9C49A368, 0x926E18EB, + 0x4DD461E1, 0xA6BD8F3C, 0x6D2E4C31, 0x657506D9, 0x445EF83F, + 0x77E28461, 0xF715400F, 0xBB76D1D, 0x9B670CD2, 0xCEB9EB90, + 0x7F297088, 0xD3929A52, 0x9B62909, 0x46474012, 0x3D74DFDF, + 0x46288EF0, 0xF0C51C07, 0xEC642B66, 0x3C76B83C, 0x1E72D08F, + 0x9F95DC1E, 0x106883C5, 0xB6A867BD, 0xA532C423, 0x95076036, + 0xA9DBEA73, 0xA3F8C65D, 0x799CF6BF, 0xA4508346, 0xB37CACB2, + 0xF6A07B5A, 0xA2C24137, 0x2E1D8DEF, 0xD28C26AD, 0xCE745089, + 0x3B7D9638, 0x7189CE82, 0xBC3F7850, 0x5660A9B8, 0x13895B5C, + 0xFA59A643, 0x9B0FF4AF, 0xFD2B4FD3, 0x4C0C4E52, 0x272631DE, + 0xA52FAE47, 0x65850A25, 0xD51ACF2B, 0xD206E6EB, 0x3CDC96EB, + 0xA6FF9E3A, 0xFC601E27, 0x658EF7F0, 0xB45FF508, 0x36A9A571, + 0xCE75E7E9, 0xC4BF9261, 0x3A261099, 0xF1B1CE3E, 0x3D28A165, + 0x3435D2FF, 0x70830AAE, 0x8DFE14F7, 0x3E27CDC1, 0x97BE4BA1, + 0x33F8D0E2, 0x9B2E7BCD, 0x1923B1C, 0xAA248E78, 0xFDA8AEB9, + 0x7825E511, 0xBF20B777, 0x218E4234, 0x7B5D1181, 0xA08988A0, + 0xD9009231, 0xEB15A567, 0x47E045A0, 0x3C515808, 0x35194ACB, + 0xA476304A, 0xEF738BD6, 0xD035FB8C, 0x3B2013F4, 0x4DE60F26, + 0x361431DC, 0x82ECB228, 0xAB22266, 0x4E056EEE, 0x6642D288, + 0x48D851E3, 0xE05D55D9, 0xDC2D6D4F, 0x158F7F48, 0x5D7F7D5A, + 0xC2835158, 0x793509C5, 0x479DF33C, 0xDEF0696A, 0x9FC2BECD, + 0xF4EFC675, 0xF8D1FF02, 0x493D3BD6, 0x7FA1C10F, 0x641B324D, + 0x996DBDDD, 0x24098529, 0x81CCFC35, 0x47F0BE17, 0x5E241815, + 0xF7F62788, 0x261CDAF5, 0x10CBC4B8, 0x5D6C6A7B, 0xD671AE81, + 0xB2C8DCD9, 0xD215CB7E, 0x3403AB1B, 0xA7C5999, 0x4675A50, + 0x369C560C, 0x32C619D9, 0x4FD2E12E, 0xB4A20359, 0x37E93502, + 0x5EC0CE10, 0xB374340, 0xB0DF0419, 0x5960ED4F, 0xF0A7770E, + 0x7F504F30, 0x54A92972, 0x3E9848B8, 0xCD980ABE, 0xDE69D570, + 0xA9FDFFBD, 0x9812C681, 0xDAFCCF4E, 0x2B636CB5, 0xB2B9FF2D, + 0xB9972800, 0x701231C6, 0x2E1108F8, 0x8C323A3E, 0x20A17A77, + 0xF2C6CC7, 0x44C5FD1C, 0x731622D4, 0x9BF0C91E, 0xB61CD1B1, + 0x61FA9CF2, 0x5E460518, 0xF75A1C06, 0x417CCEE2, 0xB45E0FB5, + 0x53DC30E8, 0x500CBD7F, 0xED61DAE3, 0xEFE91818, 0xB56814BA, + 0xD37D84C8, 0xD5DA9ED7, 0x5F40F92, 0xF1507FAD, 0x2CC74A65, + 0x32AA6279, 0x33731317, 0x30E09F03, 0xE1D9C403, 0xC21E638A, + 0xA7394D05, 0x3879F710, 0xDBB52C37, 0xB7780268, 0xE268E178, + 0x9F8072D3, 0x97CC035A, 0xEE65287D, 0xA197441A, 0x21C8AFA4, + 0xB81B50A9, 0xAF6ACC93, 0x7BB55B77, 0x564A0BD4, 0x17F7A6A9, + 0x36627846, 0xDCE746EA, 0xBB9762DE, 0x47B5B8F0, 0xEF5DA4AD, + 0x1922E420, 0x15F9299D, 0x243DAB0D, 0x953C67A3, 0xF3DA71D8, + 0x57122A3E, 0x423A78B, 0xC4A53000, 0xFBE92583, 0x968F3AE, + 0x61629123, 0x792FA07B, 0xBF45729D, 0x99DDD38E, 0xA14565FC, + 0x268E9E3F, 0x7EC9286, 0xCCA1D92A, 0xF06519DA, 0x22396664, + 0xD5DAC24D, 0x71BB4DD5, 0x7D329BB3, 0x401DAB69, 0x19D3E40A, + 0xB6F40F32, 0xE8D1CAF8, 0x5CD5F35D, 0x6F662316, 0xD38D1A6C, + 0xF86E720F, 0xE165D1B9, 0x1BC14E79, 0xC19FB43D, 0x891C013B, + 0x44AED4DC, 0xA7351AAC, 0x5F707A18, 0x3850148, 0x4A425E1, + 0xF7DD6EBD, 0xE0C3FD0E, 0x8266A425, 0x3BA17650, 0x48753ADB, + 0x679FA015, 0x88771712, 0x2174B185, 0x29F9A85A, 0x1560964A, + 0x198E4FCD, 0xD3410A86, 0x9186793D, 0xDAFC5C35, 0x971F4CC8, + 0x1F8F0E8B, 0x11A884F2, 0x66E6D2AC, 0xE85ECDB0, 0x86C76472, + 0xDF3B3320, 0xEEF446A6, 0x834CF19B, 0xECEA602A, 0x46C680AD, + 0x807BA92F, 0x4B3FC42B, 0xEC229845, 0x3FE389C1, 0x63E042D7, + 0x6C855119, 0x7B1ADF33, 0xE1B9CAE0, 0x62C20BAE, 0xEDF0E919, + 0xA50FC7EB, 0x2399262F, 0xD6F88130, 0xE2ADA5DB, 0x7D07BC3C, + 0x36A922F3, 0x7693B84E, 0x3015CD0C, 0x1D1047A7, 0x5D3A75A5, + 0xEE6F1CA9, 0x734BD19F, 0x3308DD73, 0xCEBBC9FA, 0xF79DD5A6, + 0xA41CF168, 0xED762FD8, 0x6642159, 0xA63C5CD6, 0xCB96A282, + 0xA29D9F5C, 0x45CC6CD4, 0x344611EF, 0xC345FE03, 0xC55ADDE0, + 0xB2B8374C, 0x14F730B1, 0x301D9266, 0xA2D98FD8, 0xBC107DF, + 0x59905EE3, 0xDB3560DF, 0x1D49F4F3, 0x785F8E0B, 0x8B116097, + 0x56154F60, 0xE312D829, 0xE0AFAE9B, 0xEAE3692E, 0x95915B8F, + 0x83BEEE75, 0x48C1C92, 0x8166D95E, 0x697FECA8, 0x135DEBF9, + 0xF83E6507, 0x11570809, 0x4862CBDE, 0x820E288D, 0x6CA59B2B, + 0x49DF6AD5, 0x86F41C43, 0xDD128A28, 0x601198A0, 0x3DDD49CB, + 0x95F3ACCE, 0x500CD9D6, 0xF54A50F2, 0x9936957B, 0x7C881875, + 0x743B055D, 0x44FD7934, 0xAF2253BB, 0xA2F4A27C, 0xBA8E1C2B, + 0xCCFA3259, 0x892FC73F, 0x283E74B4, 0x86119027, 0x87961F02, + 0x1D015187, 0xBA83B762, 0x61948B32, 0xAC741667, 0xFA9E0E39, + 0xD440D9CB, 0xED93F9F, 0x5FA97905, 0x2F5F82D8, 0x92EC7646, + 0xC60B3F9, 0xAA28822A, 0x7BA7CD3D, 0x3E41A20B, 0xDE4441A9, + 0xC75E539B, 0xD9D568C2, 0x2DCAE06, 0x7762550, 0x21C2D5EE, + 0x95CB6C94, 0xE31FC800, 0x3C03C172, 0xE166E564, 0x359C5102, + 0x7F717599, 0xBE301B47, 0xB207FA5C, 0x38B8B24B, 0xE6EFF05D, + 0x9F09D305, 0x31A27808, 0xC56D934F, 0xB440BD60, 0x52B1AAC4, + 0x78654045, 0x106A67B8, 0xF2A861E5, 0xC45D72B0, 0xA8FF8296, + 0x97F475A6, 0xDC222733, 0x7A835D7A, 0x45774E9A, 0x9E558C34, + 0x1124605D, 0x1689FED3, 0x70AB9928, 0xADBF8E55, 0x9C09EE27, + 0xF95A8C49, 0x75CD52D7, 0x4FC7275A, 0xA46C29F6, 0x747D788, + 0xA3347E5, 0x5B08AB02, 0x13CDC08C, 0xEDB65176, 0x6B36600A, + 0x26F5AD2A, 0x39949D1, 0xA1C8F6E5, 0xEBF0CEFF, 0xAB60A06B, + 0x10E522E8, 0x80E056D8, 0x1B301392, 0xDC3E0B07, 0xE10174EE, + 0x25DC4733, 0xB4E5A24A, 0x4B569CFE, 0xCCFE9F0D, 0x19BDC038, + 0xF8A0A718, 0x9944E8E0, 0x9591528, 0xBF27BDF1, 0x2C160255, + 0xF9E2F1B, 0xCE4FD96B, 0x703B2A77, 0xDB6EB2A7, 0xBFC2FA6A, + 0x11D00F81, 0x9540FD8D, 0x75849882, 0x183AC87C, 0x91DD1783, + 0xA3A0CC0D, 0x47F1CED1, 0x4DA4EE62, 0x819BA59E, 0xD5DA1DA5, + 0xDC218BF5, 0x899CC3A1, 0x1DECAD82, 0x77E193A5, 0x9F390C10, + 0xF5FCD674, 0x1E43657A, 0x6B61D25E, 0x99B9140E, 0xFEFB9CF9, + 0x6569445D, 0x14C9A2AF, 0x85A33FB1, 0xE4029ADE, 0x4FABD0FB, + 0xDE02379B, 0x65C8311F, 0x3CF60630, 0xC8B179FF, 0x9D83CE64, + 0xFF683C7E, 0x6D796948, 0x249B0AFA, 0xC5A65FDF, 0x252DA26D, + 0xFE92E52E, 0x90D081E5, 0xC5A8E180, 0xEBDB0943, 0xB0E7C78B, + 0xD5A89E4D, 0x684EE280, 0x8AAB613C, 0x6BD1547, 0xD12F7355, + 0x9C5D1363, 0x91E410A4, 0xDC841FBA, 0x703A9371, 0x79F8663, + 0x553650FC, 0x633CA726, 0x20107BD7, 0x2565F252, 0xCDD93830, + 0x3446CF7, 0x92B6B42A, 0xA070B2D1, 0x5E0384D1, 0x7CC5A19C, + 0x6890558F, 0x10D308AA, 0xDFF3016C, 0x1093AA3B, 0x8927683A, + 0x9259502B, 0x2B544B7C, 0x419B1B1A, 0x22D9E939, 0x568ECCEE, + 0x4F3CE09B, 0x8B990521, 0x8D6906A3, 0xC15DEDC4, 0x98384A4A, + 0x8F2F2652, 0xEDB9D614, 0x1D010AC3, 0xA2CDC134, 0xEEE9A9ED, + 0x241DB9A2, 0xE9DB9AE7, 0x7A788F9E, 0xBD0778B7, 0x27373539, + 0x7C6B4A4B, 0x3C7A6B37, 0xDE1C625, 0xC1256E67, 0xB8E69163, + 0xCC05D09B, 0x728A1427, 0xECAC2530, 0x1DD40BC8, 0xEFE42E56, + 0xB4266BE0, 0x9AD3F869, 0xDDFC2F60, 0xEF29B3F7, 0x7C15F90A, + 0x705C2992, 0x99AC7AEA, 0xCF1F09A0, 0xB41F14D9, 0xBF3C252C, + 0xF3483286, 0xD3AC398E, 0xB84BC93D, 0x6B780D11, 0xF682D379, + 0xB8A062C2, 0x9A003A9E, 0xF18F54FC, 0xDE81BB83, 0xE84C5234, + 0x37CB67FA, 0xDB685C6, 0xBF2BF28D, 0x8CDE583, 0x94CCD0BD, + 0x8BCAF516, 0x31BE93C2, 0x3ED4B623, 0xCD23346E, 0x8254E7A0, + 0x6091EF1F, 0x17A42562, 0xC9821677, 0x447B6623, 0x19D9356C, + 0x4A1C1953, 0xD1F3B7F9, 0x99F8388D, 0x62F22304, 0x5EDF1ECA, + 0xB6C9FC2F, 0x42968E22, 0x531BD76E, 0x25E6A95A, 0xA1669784, + 0x8B915BD2, 0xA5E21483, 0x5ABE3226, 0x605C0E15, 0xFDE713CC, + 0xFAC58D3B, 0x44FAF6E8, 0x41E2D699, 0x8EE11E34, 0xB03BE4F6, + 0x75054C0D, 0x1AF2D37, 0xF38E6829, 0xE7F2A519, 0xC9CF2CFF, + 0x996DDE8, 0x395AC493, 0x42AFF184, 0xB380B71C, 0x11AA0B90, + 0x66DC636, 0x56557CA8, 0xCB8CAA43, 0x9EBF806E, 0x63F66159, + 0xA011191D, 0x17B0AED3, 0xB9621251, 0x2B189E3, 0xD45A5D7, + 0x23009D12, 0x5DEB7918, 0xFDFB1FC8, 0x46808A73, 0x91D29330, + 0xF872C15D, 0x7BE90206, 0x257E9FCB, 0x2E52FF67, 0x1852DDF9, + 0x6A2C5C49, 0x6ACF891B, 0x29FFB0E2, 0x76E32CD2, 0x588799, + 0xD71D970E, 0x9B079EC8, 0xEBD25420, 0xDDB60276, 0x761B106F, + 0x871473C4, 0xBC697CE2, 0x5378E0E9, 0x8DAECE28, 0xE5B275FA, + 0x6E6E332, 0x853884E7, 0xD0FFF1A2, 0x722D372, 0xDD5A754D, + 0x87CDDA3C, 0xA9B629C0, 0xAB2E650D, 0x1709413D, 0xDAE63819, + 0xC60DE8CA, 0x9F344BD6, 0x8E651EF9, 0x3B6A8019, 0x95CC1296, + 0xB12DAEAB, 0x8D550156, 0xF14E85AA, 0xD2547469, 0x6336E320, + 0x223B05B9, 0xB88AD493, 0xEE14916F, 0xC78AF1FE, 0x65FC2787, + 0x778FA85F, 0xBA23A57E, 0x957EA954, 0xAE4F9577, 0x47C38D4F, + 0xDB7BCDC9, 0xBA13E42E, 0x46B01094, 0x1A15F5E4, 0x315AB789, + 0x9E44B54F, 0x8C690B2F, 0xDC4954CD, 0xF176F3FF, 0x9B154C06, + 0x112BD6D0, 0xCB120BBC, 0x11101771, 0x1F29A19D, 0xC3F8193A, + 0x805D6739, 0xE3B00ACB, 0x23DD9494, 0x4F88EBA5, 0xE6F32E0E, + 0x4B76F089, 0x43B66BEB, 0xF2420B12, 0x2CFC5E01, 0x1C68D3DC, + 0x30C1BD38, 0xF3A0FCCA, 0x2AF13CD5, 0x13E38185, 0x2DEE2A21, + 0xFC318E26, 0x1954D4B6, 0x3FB86424, 0x24D698F1, 0x4AB76D48, + 0xA9E87BD9, 0xCE1DD2F2, 0xF5904D9F, 0xF614DB18, 0xF83111D, + 0x1FB56EFD, 0x5CBD08D8, 0x2D8D4884, 0xE388C534, 0x413D5BB8, + 0xEB6D14D6, 0xAE54E361, 0xF73D926B, 0x43F27197, 0x7C50A2E5, + 0x10EDBD6C, 0xD151B569, 0x47C50C06, 0x8FD59E74, 0x551C6841, + 0x2EC2B6DC, 0x5CEAB3A9, 0x1E6A1609, 0x3FB07FED, 0xC0D5849A, + 0x6354A21B, 0xEBF18830, 0x2BB3EBBD, 0x9D4DF510, 0xBBBE1103, + 0x918D6DDF, 0x3FEE7A8B, 0x4FC47254, 0xE0E1EA65, 0xF3DDB31A, + 0xADF8DE67, 0xADA31FAF, 0x2BC0B8A2, 0x184B7432, 0xFDB2E733, + 0x236B014, 0x21062C, 0x8FAAD8D7, 0xA1DA7E44, 0x3EF7F42F, + 0xA67AAB82, 0x9238F0D8, 0x42F93C63, 0xEF0F4BA1, 0xE61DC644, + 0x994EF92C, 0x71A58613, 0x371665E5, 0x82E77BA1, 0x2FFA1DAE, + 0xFE19AAA0, 0x95C72A53, 0x6A21395F, 0xC03F853C, 0xBC7B73BC, + 0xED62A949, 0x4F7D3C52, 0xCACFB353, 0xA1629BE9, 0x16255784, + 0xAE465FC4, 0xE7FC2626, 0x5E9B0FC2, 0xD109084D, 0xE30E7B89, + 0x94CD7424, 0x6127AF6E, 0x7D08ED7, 0xFA0B9293, 0x450A112F, + 0xD0D79344, 0xA204F8B0, 0x5F825780, 0xD681148D, 0x71C6AE83, + 0x1DF62587, 0x99ABC8A6, 0xCFEE8131, 0xFCD11719, 0xD0D48B0E, + 0xCC4A710E, 0x7414791C, 0x22167734, 0xD17FE049, 0x5BF15C46, + 0x30B718E0, 0x6E85104E, 0x52F72575, 0xA17F09E1, 0xCDA7B24E, + 0xDAF7D03B, 0x3632D94B, 0xBAF4E9EE, 0x390CD998, 0x168C055E, + 0xBC2D8D0D, 0x35E9F642, 0x89757E1A, 0x2BB98011, 0xC19BCD15, + 0xEEB73587, 0x6A5194EB, 0xC2C1B4BA, 0x3C8F73FC, 0x8F075D29, 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0xC6D5F72, 0x97C35532, 0x6580493F, 0x9D31E266, 0xEF926A38, + 0xF68CF9C6, 0xF770C570, 0xCA18C06A, 0xFA2BB2, 0xFBA375DC, + 0xC2FE76ED, 0xB91611FA, 0x528A8EA5, 0x360A527, 0xF631D04B, + 0xF0C67ECF, 0x4E490A69, 0x19DB46F0, 0x497DFBF4, 0x58E490FC, + 0x24A51378, 0x186BDC14, 0x90E633A3, 0x6D6F8D95, 0x2FDE02DD, + 0x4B2714A6, 0x6FC87FE0, 0x21569667, 0xDCC31F06, 0xC9D9DFD0, + 0x830AA4A4, 0x78FBFE69, 0xDF17CD55, 0x3952AAA7, 0x9A4B5A7D, + 0xB1EBF3EF, 0x4F3BC1C9, 0xDFEEBF40, 0xAB130CC8, 0x1EB84425, + 0x4625E802, 0x20B990D6, 0x4E36869F, 0x5EEC0472, 0x29194460, + 0xCA425ECA, 0xEB0742C, 0x17D07C02, 0xF38BCA14, 0xBC9D555E, + 0xF15822E7, 0x89CF96E0, 0xAA848F9C, 0x90731AC9, 0x86EECBE3, + 0x308F3257, 0x5FF375DC, 0x1E62C041, 0xFDB6A3E7, 0xDFEBED8E, + 0x8FC77E76, 0x6973E542, 0x2AD1616C, 0x99B549C6, 0xD28CF364, + 0x88C87768, 0xECA2CFB, 0xA0D0B060, 0x42DFFD8, 0xAF80A6DE, + 0xFF323760, 0x1CB2DAAA, 0xD11DE4FC, 0xEEBF565A, 0x9C986CAC, + 0xC1C95B3F, 0x6868BF0, 0xF5604930, 0x316DD9EF, 0x1231D331, + 0x95E38E67, 0x7D30C191, 0x354804BA, 0x265EE5E, 0xC6728C70, + 0xD36F32D0, 0xBBEA0ECA, 0xD055ED76, 0x9135E317, 0x8A7B9770, + 0x4D1344B0, 0xE9F29AE3, 0x7BA303B9, 0x2C38AEC, 0x82ABCBA6, + 0x7729F177, 0x71793932, 0x6FE6E38D, 0x1F8416B, 0x147D8310, + 0x6A962FEC, 0xFE2F100E, 0x4FB1D511, 0x3D38AB33, 0x58ADC416, + 0x64B07504, 0x458CC4B4, 0x584BC93E, 0xDE49B6D1, 0x7347876, + 0x4A2C3EB6, 0xDF5DE09C, 0xBFD376DC, 0xC9F451C5, 0x5F793A0, + 0x892952A2, 0x15060767, 0xE1E3B589, 0x4D513C3F, 0xAF3D2CC7, + 0x289DAA2E, 0x8C711417, 0x62E5E006, 0x3BECED98, 0x99E73ACC, + 0xDE156054, 0x1283655B, 0x5123FC41, 0x3DE21841, 0xC032F050, + 0x94B5151F, 0xA5577757, 0xCC0C8DF, 0xBDB52821, 0xD530FAAD, + 0xD070D8FC, 0x46F5BB68, 0xB02DFF88, 0xD4923EA8, 0xC85A5622, + 0x93E834A3, 0x38E84468, 0x79408C75, 0xCCB635, 0xE76BADA2, + 0xC2296DA1, 0x711543BB, 0xF441F4A2, 0xBD18127C, 0x8385BFB9, + 0xD350D4D, 0x90FAF999, 0xABD1A695, 0xFCEE12C7, 0xF428912A, + 0xC9759F80, 0x6DB6491, 0xD1421D30, 0xBC398DC4, 0xB8E0A889, + 0xC854AA72, 0x82CAAF64, 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0xCBE90203, 0x6979F11D, + 0x251C50A4, 0xDAD9C59F, 0x5E4E5BFD, 0xCCD4DF48, 0x72BD66E, + 0xE7FB1B35, 0x75B4B83B, 0x29E9282A, 0x2590317D, 0x7835F9A1, + 0x25D3602C, 0xCFEC2E4F, 0x9CA2B0E7, 0xA4714302, 0x8F3D53C4, + 0xDE00F109, 0xC26D6273, 0x3E8DC623, 0xE3A972E2, 0xF67DF096, + 0x781682A5, 0x6C16F144, 0x49DC8D17, 0xB2EB82EA, 0x3CB93D91, + 0x44D4D3C4, 0x556040F, 0x1406DD74, 0x55FA83ED, 0x91C35357, + 0xF5A1C63, 0xA64E34D0, 0x7DF58C80, 0x62E97E52, 0xFBA1A2FE, + 0x8CB29D60, 0xDC1AEDE5, 0xB260BBF, 0x1AD9C6A6, 0xC60E9788, + 0xAD9DFA42, 0x2E422C17, 0x51CB5E86, 0xEB840466, 0x2666D5D8, + 0x7A0F7C62, 0xDE052A31, 0x6F0330C4, 0x9142D4AD, 0xDC8578C9, + 0x978F3E76, 0xEE43CB4D, 0x14E7EFC7, 0xB50B064B, 0xD7FB2900, + 0x67C4F4A3, 0x4D1193D7, 0x5091FB73, 0x3EB9C846, 0x960BE069, + 0x88250E7E, 0x94503385, 0x1C1F244A, 0xCFD72CE3, 0x8CD5F105, + 0x2B34131F, 0x60D266E2, 0x16BA806A, 0x25C25A42, 0x5FF6C068, + 0xD23A191F, 0x7AB5C53D, 0x9EA37FBB, 0xD1AD4B07, 0x40BCB39C, + 0xF45C8526, 0x80FEF5BF, 0x197D6D43, 0xD56FD4D0, 0xF39E498B, + 0xFB4F6847, 0x84DF289A, 0x2246F5CF, 0xF979B823, 0x42DCD843, + 0x1AB1BB0C, 0xABEC5FCE, 0x6E7EBC1, 0xE013DB54, 0x73BC8A04, + 0x88D0F71E, 0x4D93B6D8, 0x57B0B7CF, 0x99371728, 0x86B129E9, + 0xF4EB3DD2, 0x6956AA9D, 0x4C84AA0, 0xFD22CA10, 0x36E6915F, + 0xC830D7EA, 0x1EE1666, 0x1036A43F, 0x3FC86E7C, 0xF10F9CD2, + 0xEFF5F21B, 0xBF9082E0, 0xDD0DD00C, 0x80524F27, 0xDD5A3222, + 0xEA53B93F, 0x7FDA09AC, 0x89840C97, 0xC3A9BDCF, 0x1EC26899, + 0xEBCAF99C, 0x2EBB3226, 0x936A3254, 0x2E1E1786, 0x57E4CB9C, + 0xE5CDBE5, 0xFBA2458C, 0x48F3D0EF, 0x74FD06AB, 0x96C30795, + 0x14FEF0E9, 0x2F5FBA0C, 0x3CCEA60E, 0x7BA0354A, 0xCD7329FF, + 0xD4169550, 0x5FAA5E66, 0xF0C25CA2, 0xEBCC8065, 0x3F147D8F, + 0x5ED3293E, 0x6457117D, 0xE4CF4B98, 0x11F1E74E, 0xC13F47EC, + 0xBC7E22DC, 0x22512D19, 0x9140ACBB, 0x490D52F, 0x3E2D54C2, + 0x9FCBBC1B, 0x89646A33, 0x9FE4B65F, 0x92CE9ECC, 0xFBD59FB9, + 0xCE95DAD1, 0xBBCDE794, 0x9C0FA1C6, 0xCFD90F8B, 0x494C1770, + 0x21AD2AAE, 0x58EC00A6, 0xB0848A25, 0xEC4FEB5E, 0xFF1517EC, + 0x52871C07, 0x105E05B0, 0x178B1913, 0x18023805, 0xB16BBC6B, + 0xF8522A7F, 0xB17DEC22, 0x3808ACAC, 0xBC5B9043, 0xBEC01BA4, + 0xBC6CDA0B, 0x17906D50, 0x8422829F, 0x51C9AFB9, 0x54F78CEF, + 0x72CEEA16, 0x76A74B94, 0x7EC063E2, 0x51C65B1D, 0xD97ED9B8, + 0xDE89F034, 0xB5AEEFA0, 0xB88D3E9D, 0x9D4C57AE, 0xC8CEA9C1, + 0x941A74D3, 0x8E2FC33, 0xEDCEB551, 0xB91FA3E4, 0x8BA2261F, + 0xE558E0F2, 0xA4E81979, 0xAAE31455, 0x70B62249, 0xD48D1A67, + 0x11767EB6, 0x823DFECA, 0xC815C538, 0x2AB67EE6, 0x22FA86BA, + 0xD7A1F96C, 0xBA96E382, 0xB75B3FB7, 0xCB705FAF, 0xD1B9D3E2, + 0xD4C8DC2F, 0xF954B0A5, 0xDABE493B, 0xCA3FBB37, 0xBBDC387C, + 0xA30C87D6, 0xB5B493D5, 0x584F5615, 0x90FB6370, 0x5544A92D, + 0x980F7FA2, 0xF1459235, 0x130B11BD, 0xC7A44998, 0xFEBCA776, + 0x7943BE84, 0x72C99B04, 0x353F6042, 0x66F5C2F2, 0x9C5B2CC5, + 0x9FF06E41, 0xAC9E5492, 0xFF9A1CC8, 0x4429DE05, 0x97845307, + 0xDBA36668, 0x40BEBB2F, 0x606DBA6A, 0xDE7A4225, 0x9AF7FB71, + 0xE97A0E6C, 0x99C2AA59, 0xE00C525B, 0x5D4F9521, 0x89C5D7BB, + 0x18481C9F, 0xA27A1F59, 0x2A6267A3, 0xC467981A, 0xE04CE94D, + 0xAAB2AC1D, 0x5FD1AC86, 0x8F33E395, 0xE1FBE285, 0x636C2961, + 0xD838584E, 0x2F845D90, 0xAD52A8ED, 0x8F8C841B, 0x829A3861, + 0xAA0FF413, 0xA079F240, 0xB15D507B, 0x93722B10, 0x833AF929, + 0x4FB5B879, 0xEDD3031D, 0xE22CE740, 0x9ADF835A, 0x13A0C7A3, + 0xD5791B98, 0x99D9409F, 0x9F776A0E, 0x8665EC9F, 0x7301EF7C, + 0x9B341035, 0x59EADE7F, 0x242C1ECA, 0x20FD13FD, 0xE22DAF76, + 0x3859E84D, 0x6ED83DA, 0x54ABF391, 0xC43F4740, 0x4661F86, + 0xC6442213, 0x7FEAF294, 0xC0CAC024, 0x38B9FA9C, 0xFFF33259, + 0x1AD86335, 0xB365445F, 0x54B58378, 0xFD7AE96A, 0xE019B245, + 0xCF51C4EC, 0x604D7EE, 0x7B40C023, 0xA5E168B0, 0xD7B8C643, + 0x91C028D3, 0xCB939A6B, 0x169B0123, 0x96FF8CFA, 0xFCB3E126, + 0xB95C01B1, 0x1758BFB6, 0x50F50968, 0xF774D536, 0xC5A8BFE7, + 0xE2496BE, 0x6FB8D434, 0x3F7FEDB9, 0x9BDEE991, 0x1CBD2009, + 0x2CE74DB4, 0x1CB51025, 0xE965ECE6, 0x89100034, 0xA089E8C0, + 0x5860A65B, 0x9C4D349E, 0x54898852, 0xD07C9738, 0xBC677E89, + 0x75B5D0C1, 0xCFD435AF, 0xED550357, 0xAED9301, 0xDCD1734A, + 0xEDCD21D7, 0x69F6A592, 0xEF8009F7, 0x44374358, 0x9405770D, + 0x668AC4FA, 0x50507E61, 0x2DB19DDC, 0xA9BDD137, 0xFB722699, + 0xBC067E88, 0x88740174, 0x717CCEDC, 0x9F7F1E11, 0x389F4CC, + 0xCF4D0018, 0x24588FF1, 0x25C9F951, 0xDA660468, 0x6C09D91C, + 0xC9F788E, 0xDD4DF43F, 0x8B04484A, 0xC7F67DDB, 0xD2939F8B, + 0x96BCFDE5, 0xF6DD10D8, 0x1124A3BC, 0x7C281FBB, 0x5FAFA71B, + 0x58A9C493, 0x4747793C, 0xD3B79E72, 0x357AA675, 0x8E94A74B, + 0x1994025, 0x95D10FB8, 0x5C64AE63, 0x9E37973F, 0xFCE67009, + 0x8480F94E, 0x34DA26F7, 0x126CFB46, 0x206AAA6B, 0xBA0A6200, + 0x8DF3F67F, 0x4936802F, 0x950F62F8, 0x17E64C44, 0xC70E523E, + 0x2F910727, 0xAF7C5BC, 0x9EA24508, 0x1E945729, 0x55E48FBD, + 0x897CB57, 0x8C134FEB, 0x54E68223, 0x91912044, 0x7A461BDB, + 0xCE91309, 0x72135AF, 0xBF94D484, 0xDD752690, 0x32248D12, + 0xEA092355, 0xC24CA220, 0xE8A95D65, 0xE4E2EAE6, 0x664763E9, + 0x71F1AA47, 0x832550FF, 0xFFA73B6B, 0x96F5DFF6, 0x60CB9B66, + 0x75F29F5C, 0xF863AC8F, 0xF16993FC, 0x3503801C, 0x3D1E8B2, + 0x583CDFF6, 0x62AD49F2, 0x8261843F, 0x826EA9B6, 0x5E2EF3, + 0x8D3848EC, 0x7391A581, 0xDFC466FB, 0xB38DCBD1, 0x4145C3C0, + 0x73F322D7, 0x2B55F284, 0x6B19FBA6, 0xD9446AD1, 0x36C330C5, + 0xB71E4B29, 0xF29F504E, 0xB4FA4CFB, 0x290B6941, 0xA2197E21, + 0xF2AAE27F, 0x1A1728B5, 0xAFF5632, 0x6AEE763B, 0x2962A376, + 0x965D67E7, 0x231A8B76, 0xBD3596FC, 0xD4AE3E8D, 0x58D4D740, + 0x4EA3B6DC, 0x5479A7F5, 0x110A4791, 0x9A772A63, 0x728C4794, + 0x6D6A0801, 0x3F89D9E1, 0x326D1BC4, 0x49B3798, 0x5E2B3CA8, + 0x742C385A, 0x89450FE0, 0x24236A74, 0x81AC9891, 0x7BEF3C66, + 0xACECD674, 0x29009073, 0x94D6BDBF, 0xF2C6CDF4, 0xDBC21EE3, + 0xC65C89A4, 0x35DC5337, 0xBA281430, 0x787521B0, 0xADF8317E, + 0xD5739B77, 0x8567F3A2, 0x374E0CAC, 0x5AFFF50F, 0x9654D41, + 0x4A86EDEF, 0xE16C9A62, 0x59D15E49, 0xA69769C8, 0xA9197100, + 0x1E04CB9F, 0xA926CCB8, 0x5047C429, 0xB7E369C, 0x812F5F0A, + 0xA53EA5BA, 0x9AE5C105, 0xD4C7CC5D, 0xC99E02F9, 0x5BCDFE96, + 0xCDBAA854, 0xCF209B89, 0xBE08E9B, 0x5C73AED2, 0xBD959602, + 0x63C309AB, 0xEE289A4, 0xEDA954C9, 0x5C54F616, 0x3BC34487, + 0x47A3C772, 0xAB0084A4, 0x2CFB8D44, 0xF5F8411D, 0x43F6361D, + 0x12B8467F, 0xCDC437A5, 0xAC96A375, 0x7962CD18, 0x5D728EF4, + 0x66B11DEF, 0x73C87A6, 0xA35AEF9A, 0xC84F12F7, 0xB1EDE9B4, + 0x2F6A1752, 0xCF8DA321, 0x2E37F4E0, 0x4985F516, 0x684E49AF, + 0x56287772, 0xF74F95EF, 0xD994FF05, 0xC1D23E99, 0x81214F78, + 0xA5DF2934, 0xC2B686DB, 0xABC54017, 0x6918D067, 0x737A798C, + 0x3904B21C, 0xD4CB6EFF, 0xC256E4F8, 0x38B0CD4D, 0xE2D27089, + 0x75A00DC2, 0xDC1D5E7B, 0xE2295307, 0x2F0A683C, 0xD00AF450, + 0xE45C3252, 0xD86804C8, 0xF9628DB9, 0xEA011DB9, 0x6A67523A, + 0x488B54B3, 0xA292CDEA, 0xB1D1D89A, 0x17415325, 0x3EAD3D80, + 0x5D092525, 0xB5880E29, 0x1104A8AF, 0xBC177790, 0xEC730159, + 0x11B0A1AD, 0xB809FD7C, 0xB23FE31, 0xCCBED7C8, 0x45B7F7BF, + 0x9491B0EB, 0x1B1A90F9, 0xE34F4317, 0xF060A5B3, 0xF795EF1, + 0x8254A941, 0xC6CC30E4, 0x770FC40C, 0x17EC9C1F, 0x20DA83EF, + 0xF9CCBFC9, 0x9D0675AD, 0xACEA7EB3, 0x56326F5C, 0x74D4DF3A, + 0xA8FF9A9, 0x8F55E3E2, 0x5B0D12F1, 0x12DDB28C, 0x95FADBED, + 0x81F48694, 0xABEE8392, 0x90E96B15, 0x2C44972E, 0x4E2D3A4F, + 0xE8D34D14, 0x83C03E59, 0xDC295E2E, 0xDDEA452F, 0xC2A2A33F, + 0x617210DE, 0x69542DB0, 0x1DD96D24, 0x3E3871D0, 0x9DDDAF6C, + 0xBD326CD5, 0xD87CE143, 0xF3C79B3A, 0x7F811CCD, 0xDE1B1502, + 0x8075EA04, 0x9D09F1DC, 0x8CCBD152, 0x669F35C, 0xC9414276, + 0xA2BFFE0E, 0xF8AAE650, 0x190C1AE7, 0x2DBB4A7D, 0x575B247D, + 0x3A599D3E, 0xB09B4DFC, 0xCE4904A0, 0x63C72670, 0x15A3BD05, + 0x799B50CD, 0x19A2718C, 0x4142750D, 0x9013BE74, 0x21288938, + 0x590BD2BB, 0xE4303149, 0x46B308C0, 0xD2BB7D56, 0x1BFB248, + 0x943B2E72, 0xCAB18644, 0xFCC921C4, 0x5308C4D9, 0x9098CEE2, + 0x435B219F, 0x69F1BBE5, 0x155216D4, 0x83F2A4A5, 0xE177744D, + 0x37DF6FDE, 0x9D9EA50A, 0xDFA8D408, 0x6C72E71E, 0xEA617E3E, + 0xDAD6C13B, 0xB83A850D, 0x45F6BEB5, 0x6AFB346D, 0x400B29FB, + 0xBC8E57DE, 0xC6C1081A, 0x4F6A9545, 0xF878303F, 0xB9E519DC, + 0xCCF25FBA, 0xCAE069A5, 0xB79B082E, 0xF70BB7E7, 0xE6A5535C, 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0x9CA0073, 0x76772A47, 0xFBB63B16, 0x78F3C3B7, + 0xF118B4A6, 0x8E86A34A, 0x56693D7E, 0x381EA186, 0xCB9B430D, + 0xAD11DC36, 0x599B3370, 0x7A6B80C0, 0xF2A282DC, 0xF58F96FF, + 0x97AADB3A, 0x5AA06FD, 0x44A43553, 0xBE8097C6, 0x4CF5002D, + 0xBADE20DD, 0xFEC25B7, 0xC8B50C4E, 0xF0C899D4, 0x815F9958, + 0x77772B46, 0x7413F82A, 0x7203A939, 0xF4623F73, 0x35EE625C, + 0x2723BC68, 0x33790B09, 0xA58391E4, 0xA27C7C25, 0xBC032556, + 0x1D812AD4, 0x301BB65D, 0x22FAF223, 0xDCBB79DE, 0x78CE1CBF, + 0x570C796B, 0x17EF8909, 0x8E2C32E5, 0xB54FF82F, 0x7702F70, + 0x1C0A78C2, 0xCB3078DF, 0x7155531A, 0xEAC77450, 0xB9DC2EDF, + 0xA8B6A1A6, 0x57FC52F0, 0x6B5543E4, 0x40679BEA, 0xE46813E7, + 0x65525695, 0x6C9CD43C, 0x5E5BD786, 0x44212626, 0x847A8357, + 0x7E39813D, 0x9FE22F0E, 0x29EC985A, 0xC91CF47C, 0xB31A26AC, + 0xA4C8B43C, 0x8EAB7865, 0xF6F2F67E, 0x3F73A8DC, 0x4FAF5455, + 0xE1253CAD, 0x3001A083, 0x532DEAE4, 0x6A110DF6, 0x585D0FDE, + 0x19071CC0, 0x1A351A69, 0x2FEAD890, 0x33902499, 0xA218C193, + 0x2294A970, 0xB0544EA1, 0xC54B25F0, 0x6C89048C, 0xC8203390, + 0x237F30DA, 0xE8F10E5F, 0x6B57E331, 0x43744B6E, 0x2EEF4BB4, + 0xEBD13AA, 0xA9024B04, 0x22895C31, 0x321C459A, 0xFCEFD3EE, + 0x94772392, 0xA094B3F3, 0xC070FBB2, 0xF30ADCDF, 0x8D294C6E, + 0x89E4C299, 0x47DE058E, 0x841A807E, 0xDEA7608F, 0x3A45D7AE, + 0xFE08A063, 0xF2C65E08, 0x4C653ADB, 0x8E4BED1C, 0xC85C1323, + 0x63DF1750, 0x4EF4B72F, 0x209903A9, 0x3ECCC1C6, 0x4283795A, + 0x205AC943, 0x38B1ABE3, 0x1241AC5D, 0x7C645871, 0x747695BB, + 0x29206570, 0x31BACE6E, 0xFDEEDAC9, 0x4DEFF536, 0xCD6CFDC0, + 0xEB0FAB42, 0x7DFA5EB6, 0x8363D9BA, 0xCFCD2514, 0x69FEB823, + 0x10BDBDCD, 0xE4C27020, 0x56DCF966, 0x9C97BD95, 0xCDAB9269, + 0x8316F55E, 0xC62F7354, 0x5415281A, 0x31EBDCED, 0xCDF7A05D, + 0x5F674F71, 0xF70EE58B, 0x26037964, 0x584174B4, 0xFEA5520C, + 0xD01A8007, 0x7F2772E8, 0xC2FF1456, 0x7B2CA1FB, 0xE938BBD0, + 0xD96CCCF2, 0x9AE8088B, 0xF3A25E6B, 0x3780417E, 0xB9E2917D, + 0x95872990, 0x12D99C68, 0x2FC5DDB0, 0x55437D2B, 0xDB9C14B7, + 0x6BBE6AF9, 0xFBDC9201, 0xDCB32A70, 0x1CABF45D, 0xD8BCBF4F, + 0x271AE6A5, 0xD34B8953, 0x58BBFB3A, 0x537F049A, 0x55B51226, + 0xCD809DC9, 0x846DB4EB, 0xED476D72, 0xEFC8F8AF, 0x6AA3228D, + 0xA363F656, 0x2207127, 0xA1BBE245, 0x2AB58A00, 0x637810C9, + 0x91F61AD, 0x347D333B, 0x1E9598E3, 0x2E7BD8C6, 0x8DCE469F, + 0x73B82620, 0x9257D4E0, 0xD9580F88, 0xE8EF6D53, 0x2D9FAC45, + 0xB56E2C6, 0x9B369045, 0xB50702C6, 0x955D3700, 0x577CC21E, + 0xED02FCBA, 0x73320B99, 0xB55DE16B, 0x7F578129, 0x3F6FD052, + 0xF211A764, 0x9B7F9204, 0xC61EDC01, 0x1363AA4F, 0xEFAF1CF2, + 0xE5AF97EC, 0xEEAD4FB7, 0xF41B649, 0x373087FB, 0xE81355EB, + 0xE04FF410, 0xFD04F4F7, 0xFA269CEE, 0xBE8D7535, 0x5FC007DE, + 0xCF085F76, 0x94D7201F, 0xAF49F41D, 0x8D6E7F, 0x9D63B6ED, + 0x9A2A0877, 0xF06123D9, 0x6624C891, 0x508266E4, 0x6921EAA4, + 0xD6E69A49, 0xCDA0F920, 0xA5870B5E, 0x1A93A2CF, 0xE3A030C6, + 0x6EC03FE5, 0x37FDBDF6, 0xBEFD0BFF, 0x3D3CBD0E, 0x2DDBFD7D, + 0x8B58AE2B, 0xCAD61AF3, 0x624F4677, 0xC402CF5E, 0x431D2CC1, + 0x5C205AE5, 0xFC3B8ED4, 0x501C36DA, 0xBC9217E5, 0x6752573D, + 0x3BE702E, 0x8E06CF12, 0x81494C86, 0xB2DC2F63, 0x792EC845, + 0xC6BDEDB5, 0xB255BA4B, 0x6C66C28D, 0xD1A16904, 0x93ABFF21, + 0x94827FC4, 0x87825689, 0x314D1F33, 0xC0D8B98A, 0xC84AC57D, + 0xEBDB0F92, 0xBA4F473B, 0x61130498, 0xA534064B, 0x3DC04FBD, + 0xD0A701F2, 0xA671765D, 0x17464B7E, 0x4CCCB84, 0xC297BAED, + 0xAAF8C84A, 0x631313F, 0x8E0FD926, 0x1699F616, 0xD9808C9D, + 0x55BF5BC2, 0x27FD10B0, 0xAE975927, 0x92B3F52F, 0x9025C6B3, + 0x95E5E313, 0x4CB83334, 0xE4A1E7B8, 0x74F7D3D5, 0xDDDC42B9, + 0x5A89BEF1, 0xF66A6AE5, 0x33730C23, 0xEB7F079E, 0x742FEF19, + 0x2C68CAC5, 0x2410679F, 0x9D1632DA, 0x458F4AAD, 0x8889E6AE, + 0xA3B48216, 0xC9AF4AEC, 0xA506C8F6, 0xB6AF9E59, 0xC6340436, + 0xA6B294E, 0xF35CF92B, 0xEB3A4113, 0x98070AD1, 0x9E61E01E, + 0x58C2893A, 0xCC1F8C34, 0xCAD665A0, 0xD0414D39, 0x643BDCD8, + 0x8AF801AD, 0x9ADBB106, 0x2BD02351, 0x8F890436, 0x546747D0, + 0x6DC33C48, 0x95FA7FD6, 0x5F12C5A5, 0x5DF2761D, 0x9A9B2F8A, + 0x8C61276B, 0xACCC7F4, 0x37A5829D, 0xF1A0F1, 0xAAED57E0, + 0x180CD2A3, 0xDC393CA7, 0x504E7405, 0x89DE2F7, 0xA4D8C4EA, + 0xD8BECE01, 0xD664017C, 0xF57FA30, 0x6049928D, 0x9832E166, + 0x176AAC31, 0xA793F88A, 0xCFFA8B54, 0xA30DF1EF, 0x3B6C7611, + 0xDEFC961, 0x9BFB79F1, 0x1483D430, 0xC3A77C0C, 0x42AC1FA0, + 0xFA3605B6, 0x9A2EBDF0, 0x684D414E, 0xD9308E10, 0x64D68C19, + 0xA8A9B67B, 0xF5E7B9D4, 0xC7B70ACE, 0xA6EB6DB8, 0x8A22FBE2, + 0x3AFFDDA1, 0xFB61F7D5, 0xE057717B, 0x846D96CB, 0x20A4B400, + 0x574089BB, 0x9F3D2DBD, 0xEEDDDB4B, 0x5E64EA6B, 0x6781DC90, + 0xCFD86A6, 0xA92441CD, 0xAC5DCCD6, 0xE6BB5582, 0x32FA6B3F, + 0x3ABB8A64, 0xA49D2003, 0xA965E430, 0xEC4053BB, 0x95859D40, + 0x2672832, 0xCAC3E608, 0xF8C13A53, 0xB04EC2A3, 0x87F54941, + 0x62A3A924, 0xE0B48702, 0xE8700446, 0x95BD4B11, 0xCFCFDF9A, + 0x19F67E7D, 0x60853AC6, 0x468F963, 0x298066B9, 0xEE53E89A, + 0xFC63E607, 0x6FA101E5, 0x8B2F1F84, 0x24AE7C1C, 0x385008FF, + 0x96E75EB6, 0xF1175277, 0xE5B4A577, 0xB0C97AC, 0xC21CC45A, + 0x5C680DF8, 0xDEB046DC, 0x1487FC03, 0x1D90CE3C, 0x712563BF, + 0x65A26CD9, 0x4D094F62, 0xB5DFE29C, 0xF58B2A62, 0x9420A9DC, + 0xCEC7537F, 0xC46D1FCA, 0xAD5D7B10, 0x68777A24, 0x6C096D2, + 0xD787D72, 0xC7743F50, 0xB3D05F4D, 0x53E0A7E3, 0x9E627C6D, + 0x1AA0959F, 0xD1E00E47, 0x8874BA26, 0xCEAC0958, 0x10F67BBD, + 0x712C6597, 0x3478BD73, 0x4D6F116, 0xD30BC24B, 0xB98C565A, + 0xD7C5B116, 0xA8CDAC4F, 0x4144673, 0x848F37E3, 0xADD946EE, + 0x6F17EAE3, 0xEA0FA265, 0x41DB99E0, 0x6BCFDA5A, 0xB46ECED5, + 0xAF67610E, 0xC7E9DF2C, 0x5CC6F0C6, 0xAB2C2BA, 0x6BCC3881, + 0xE482C243, 0xD8053417, 0xFFDB6E41, 0xF13EEB84, 0xE8292661, + 0xEB9940A6, 0xF0B45F98, 0x1CA82AF4, 0xCCA7771D, 0xDD5F3CFE, + 0x58BD8E91, 0xDF9E3342, 0xA1003957, 0x4621AF52, 0xF926F465, + 0x209925AD, 0xB1C72F09, 0x3FAB8ED, 0xA15C0A17, 0xDBE73D2C, + 0xF917CE51, 0xED047661, 0x7361B752, 0x1AAA57A8, 0x31445667, + 0xFEC0FD81, 0xE3073574, 0x7D36F720, 0xF418181A, 0x1CB8758E, + 0x8E85AFBA, 0x407E9AD9, 0xF724E308, 0xD030D3ED, 0x4610418E, + 0xE799EA4D, 0xF8B68F92, 0xB84B9ACD, 0x4B8168C0, 0x9888977, + 0x216F3B3E, 0x5C49C1DB, 0x759E718D, 0x7C4309FF, 0xBF6DEE2C, + 0xE566F231, 0x774B0A7A, 0xBE55CCFF, 0x3081B8CD, 0x2284369E, + 0x2FDF7473, 0x3AF68AC7, 0x6047E9B8, 0x3743BA0E, 0x691D261, + 0xADC440E1, 0x24150207, 0xFBFE466C, 0xF767E860, 0x8157332E, + 0xFB54D774, 0x1AF34C22, 0x74E05695, 0x2101FD57, 0x2904274C, + 0xA1294E9A, 0xF43CA18F, 0x4FA79EB5, 0xAFD1C9EE, 0x6EB3953F, + 0xDDFCB3AA, 0xDB48F7BA, 0xE1742183, 0x8A78CEBD, 0x225CD669, + 0xD76B771A, 0x3520113, 0x428B2892, 0x3A5CE8DD, 0xAB4AC42C, + 0x2928BE8D, 0xC34E3031, 0x93F0CB9B, 0xB7A6FDB4, 0xEEB2B85E, + 0xC393597B, 0x9D8457EF, 0x91F0F0FA, 0xC54AEA3C, 0xC639521, + 0xB668AFE4, 0xE4CCE3CD, 0x86223A5D, 0x6A51A2EB, 0x4333C505, + 0x3233B8B7, 0x1D01F51E, 0xF0C691A6, 0x699EBC2C, 0x7FEE8DBC, + 0xCC50E42A, 0x7951DB68, 0x8CF01752, 0x33D33841, 0xB46E353A, + 0x700B65B, 0x59ACA844, 0x38631893, 0xC32D0F92, 0x6897EFDD, + 0x3F93BCDD, 0xD50E33C3, 0xD0075F1D, 0xB3CB6096, 0x875896CB, + 0x5DF6651, 0x8E2D197F, 0xCDF68F10, 0xC74018CE, 0x83E6C42A, + 0x994DEA76, 0xF932D8AF, 0x98775C2D, 0xF79CAAE5, 0xF2BEB839, + 0x7318C6DB, 0x3AFD6D85, 0x37F18BDF, 0x10194867, 0xA73B5205, + 0x3F06A1BD, 0xBC8026DF, 0x531CF753, 0xCAFAED74, 0x817C9E70, + 0x32338A3F, 0xA5177C74, 0x9A3C131F, 0x90F9AF0, 0xE9281B62, + 0xEDD87C1E, 0x16577CB0, 0x5E3F7AC3, 0x4E49E1EA, 0x495C1B67, + 0xC282F5FE, 0xF8993B1, 0x47563C68, 0x49FA0716, 0x26A55B80, + 0xDF870F8D, 0xFBB8DDA5, 0x130EA4E3, 0xB0B66F1A, 0xD7B92F0F, + 0x55FD4759, 0x6D11AC86, 0x8AB0B6F8, 0xD8C8C8B0, 0x758DA8A, + 0x9CD589F, 0xB808C0A0, 0xB2C7A3F3, 0xBA40DA44, 0x937532CF, + 0x279CFDB2, 0x545896EA, 0x387A8F38, 0xB2E5F9D0, 0x7566CA0D, + 0x51B45DC4, 0xA93B6EAE, 0x1C22D8D5, 0xEB96BD1D, 0xB8F40750, + 0xCB7DCF85, 0x188F6018, 0x95BA817E, 0xF7C19E4E, 0xAAF97DDA, + 0xE5BD967B, 0x1604352F, 0x3758C3BB, 0xE2FA13D1, 0xE3666F4E, + 0x218059EA, 0x2F4750EA, 0x2F065B46, 0x8FC4F43F, 0x2F45422F, + 0x45928A5E, 0x77055776, 0xBB8103E1, 0x160EFF29, 0xA704F79B, + 0x6655E735, 0x2C19DC79, 0xE407A7CD, 0x9F4AE1F0, 0xBED7DCE5, + 0xA870A304, 0xDC413709, 0x903181E, 0x7C1F6803, 0x44971A01, + 0xF7A81ED1, 0x5DDFB023, 0x2D90CFBB, 0x7F7A432A, 0x35F3F5B0, + 0x7D935FC5, 0x1D99E7BB, 0x8EFC82B0, 0xAB0DEF56, 0x70702FA1, + 0xCF0064DF, 0xDD9DEAA9, 0xF05F927B, 0xB483A6DD, 0x9B7388B8, + 0x2FD82389, 0xAC982F20, 0xC86AD76F, 0x15C6977C, 0xAB10A137, + 0x1433E4A0, 0x2762D44, 0x1CB5399B, 0x310A54D8, 0xD4B8623A, + 0x40FAB5F3, 0xC2D51618, 0xC1F4AF55, 0x17C18E1C, 0x4F37D33F, + 0x2DC9F168, 0xF5BB9754, 0x716FB1F4, 0x7CFB1CE8, 0x1333224D, + 0x344C13B3, 0x7798CB50, 0xB4278C76, 0xD7CC1B03, 0x168B21E5, + 0xF7D77AAB, 0x3B651846, 0x639EB0CD, 0x68EB3E8B, 0xEC82FE45, + 0x622A71DE, 0xAA05B6CB, 0x878B59B1, 0x3E7FB616, 0x1D650408, + 0xF21F8C64, 0x9BF7BF7A, 0xA0874898, 0xFE4E3C6E, 0xFA36122E, + 0x1BCDF4FB, 0xC371B365, 0x8F791BB3, 0x9833AD98, 0xE84887FC, + 0xF8988AB6, 0x180916E2, 0xB587E39C, 0xD5C884C6, 0x27B6BFEB, + 0xD8868D1E, 0x689DA503, 0x936B4EFC, 0xDE0DB3C, 0x7950FDCB, + 0xA61C81C5, 0x9F1C93B2, 0xC983179A, 0x6F847EB0, 0x6F7F899D, + 0xD270412, 0xCC255717, 0x763112A0, 0x8725C96D, 0x48BC2863, + 0x85F13BF0, 0x6D8E0251, 0xB7E66CC3, 0xA4F5829F, 0x8779F381, + 0x16A5E04F, 0x3DF42C14, 0x367F06A3, 0x3BF8666C, 0xC6649CFB, + 0x4DD9808F, 0xB4F9AFD, 0xC2642410, 0x9740E4F6, 0x8FB667BE, + 0x4D4B0D3E, 0xE9B236F7, 0x6E30550C, 0x79DA7B48, 0xE721889D, + 0x79D9B21A, 0xA06B8C2E, 0x997B1696, 0x4383FC27, 0x8B77D293, + 0x6FAE2A9F, 0xB45ED194, 0xF38E2C59, 0xEAA0D05C, 0xA3BC449A, + 0x6EB0BB4B, 0x6B242CFF, 0x7FCA0B8A, 0x47221D33, 0x4E18FE39, + 0xF4691580, 0x6D03D791, 0x3B937AC5, 0x9CB761C3, 0x42812232, + 0xFB987D6C, 0x86AD164E, 0x5D8CED49, 0x22D6D058, 0x42FADF98, + 0x9363A1B3, 0x83C6DB74, 0x7AF44F4E, 0x20086D60, 0x7A37665E, + 0xC4A29C82, 0x330F278B, 0x8750B539, 0xDD2E83D0, 0xB8E002B1, + 0xF2A9323F, 0x91B60885, 0xDE83F01D, 0xACA126, 0x2F0FADA2, + 0xC0E879A6, 0x7C715655, 0x16642BA2, 0x43B9C083, 0x95F6789D, + 0xE6576886, 0x46BEF133, 0x84199FC3, 0xC45BA082, 0x26489AC1, + 0xA4FE268A, 0x633A25B0, 0x4FCD341D, 0x8E7374B3, 0x7F8A3466, + 0xC82B53F7, 0x2E2114DC, 0x59213BE7, 0xE72A2395, 0xAC5F982B, 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0xE9D2DD1A, 0x78DA23CE, 0xCADBA5C9, 0x77015761, + 0xF5581BDF, 0xDEB4DAA0, 0xAF7E41B0, 0x71347196, 0xF8A29A93, + 0x8DA3BAE6, 0x73396AAD, 0xD4DF7765, 0x326AFF23, 0x27888A0C, + 0xE48AC062, 0xB9F18047, 0xDE9830DA, 0x8EF78C4D, 0xFBC1896E, + 0x9BB566A6, 0xB640ED13, 0x8B0D9D1E, 0xD84B471D, 0x4040EFB4, + 0xF6DF7908, 0xCB8ACF04, 0x253494DD, 0xA85F6D88, 0x1326822, + 0x61EFDFB8, 0x1C78154F, 0xB13866B1, 0x3ABE5DBB, 0xBB5907BF, + 0xA1A57FDF, 0x410549C8, 0xA9A364F4, 0x2A371B73, 0x24AC7296, + 0xA01C035C, 0xE839029C, 0x6E12051E, 0xE6A549FD, 0x345F10FF, + 0x3BB57347, 0xBDBF3A6A, 0x2A41C3C8, 0x6E0232B0, 0xAE66D42E, + 0x3BE90433, 0xE185FBF2, 0x9BCA91FE, 0xF4FFB74E, 0x142B6971, + 0xA75CD7B, 0x9B900DDD, 0xEC56B79, 0x2FE0CD8D, 0x87BE8237, + 0xB38A7226, 0xB5D8B437, 0xAAADC41D, 0x8014E227, 0x38D84DD1, + 0xEDF5294F, 0x862F0F, 0xD69F77F6, 0x409C3B68, 0x2F12B0FC, + 0x32A670B9, 0x5746EE2, 0x96B4901A, 0x57208639, 0xA282A77D, + 0xE9D9F48E, 0x651ADDA6, 0xFF5E974C, 0x37C833C, 0x41F2BD58, + 0xDFE1D009, 0x32222DA6, 0x22201781, 0x64A06BAF, 0x8F188902, + 0xA9C2A07B, 0x617C7DF7, 0x842DA704, 0x40AFDB72, 0x49625110, + 0x72484F13, 0x7340AC89, 0x6C6A2F36, 0x828EF5F9, 0x20344923, + 0x21D3304F, 0xD6EEB7C3, 0x8F99732F, 0xEBA045D5, 0x5C0065D4, + 0xEEB5E899, 0x1B079C47, 0x6198EE3B, 0x946A805F, 0x7C19F966, + 0x75E8F043, 0xFD9880BE, 0x47BF619, 0x9C001ADB, 0x7438184B, + 0xA3787EF2, 0xA461EF4E, 0xEB515D0E, 0x64EFA69D, 0xD41F3145, + 0xD08A900B, 0x495968AC, 0x746639C9, 0x43E85DCB, 0x62E55B3, + 0x6B913D8E, 0x2685D73B, 0xE4F98C19, 0xB404BD4B, 0xFEA327C5, + 0x1E0CC908, 0x71BC53EA, 0x530AAECB, 0xBD2977B, 0xB661A52, + 0x86560EE2, 0x250E2591, 0xDA57D5B3, 0x347D3C22, 0x6CE15221, + 0x6E5288EB, 0xA79875F3, 0xCA89972F, 0x36E93777, 0x257262E1, + 0xD1D4E5A4, 0xF7ED5D52, 0xECE58036, 0x644ACA69, 0xCA36DFB8, + 0x60EAB44D, 0x46FB8AB3, 0x81E6C199, 0xD5AA5C63, 0x4A7CB01D, + 0xFCC109CD, 0xD999C46B, 0x3FA4C688, 0xC95C0FBE, 0xA1E9DD3, + 0xBE9EAEF6, 0x1A3014D7, 0x729A662, 0xDC8178FD, 0x7FCAA1EF, + 0xD4005420, 0x2A904DAD, 0xEE7E52DB, 0x886C0F23, 0x12D49E10, + 0x2B3F3B39, 0x3373A6C6, 0x5D0759F5, 0x8CF5EF25, 0xCE02371C, + 0x2FFEEFDE, 0x5D9CFD69, 0x2B5BB7D0, 0x5A378EA9, 0x5BED8331, + 0x9C1A37CA, 0x702799F, 0x4D37A8EB, 0x370CEDF8, 0x43B95BE0, + 0xA0C1E534, 0x204130B2, 0x8E4995AC, 0xCF1C3C28, 0x3E901F78, + 0xB0F43C57, 0xED4B7492, 0xABD3C5CD, 0xEA95ABC4, 0xE03B739A, + 0x58388E80, 0xFDF22044, 0xF4379C7E, 0x87CFA0C, 0xAE9CA79E, + 0x41DCB004, 0x8F69512D, 0x73ED4756, 0xE215297A, 0xD931A6AD, + 0x59866B3D, 0x61825B1D, 0x4F5099E1, 0x25AE168B, 0x1272D5C6, + 0xBE071035, 0x24314F71, 0x82F4B23F, 0x6C7F3385, 0x36CF0505, + 0xB71C0E3D, 0xE9F881D0, 0x27F0C290, 0xF4BE30D7, 0x88315CE8, + 0x9E04FD20, 0xDE197591, 0xCF0D2FF4, 0x67A4C473, 0x158447BF, + 0xA4B37C88, 0x27918292, 0x5FDE3DF0, 0xE8A93C3D, 0x886287E8, + 0x746E199B, 0x9A894103, 0x7A529374, 0xA195E2AF, 0xAA3EB0C6, + 0xF70788A9, 0xCE2B7F30, 0x9C4724AA, 0x902EB7A8, 0x2CBBB407, + 0x3799651F, 0x9016E9D0, 0xD1C0ABC8, 0xC7684FDD, 0xE4670051, + 0x25B69E83, 0x1CEC9BBF, 0xD066D2B4, 0x2AD4BF14, 0x7AFBD3CF, + 0xCB8E5EFA, 0x63B67572, 0x89F7E3F3, 0x8E8D39E6, 0x60617ECD, + 0x9EECEA31, 0x59E57FAB, 0x807AFCD6, 0xFD0397B8, 0x3C57D963, + 0x9A972CF5, 0xFC47B628, 0x9CCFAA8B, 0x405869C3, 0x3CC128C1, + 0xE154C33E, 0xBE53F87D, 0xD23C7947, 0x4CBEB3BB, 0x1F068FFA, + 0x8A7D350A, 0xB822F33E, 0xFB3BB431, 0x741D2D0F, 0x81FAFE09, + 0x80B8BA3C, 0x30B4BE94, 0x4B2A2909, 0x31740925, 0xE68C0BC9, + 0x8E7F31D4, 0x29DA2599, 0xB9D267C9, 0xEDE811D2, 0x8BC7CBC3, + 0x69DDA8B6, 0x879E1212, 0xF915F0F1, 0xBBCDB1AD, 0x3A01011A, + 0x7CD005C4, 0x475FC718, 0xF03F454B, 0x7457F264, 0xB22D9DFD, + 0x569DE931, 0xB585EFEB, 0x9A183445, 0x9CB353AC, 0xE3AA9817, + 0x32E0722, 0xF0C7595E, 0x316DBD6A, 0x96D0F65C, 0xA6F0ECCE, + 0xCB8A9494, 0x5B077241, 0xD36BBC7, 0x9C4CD0F9, 0x108F5B32, + 0xC43C599A, 0x7B10108A, 0xA4106EE9, 0x3860CF99, 0x87B782C, + 0xF667524C, 0x129929C, 0xEA85C1D5, 0x1A07973E, 0xB9524891, + 0xBC02BD1F, 0xF378D7F, 0xD0BED4D7, 0x5B782DE2, 0x738681A, + 0x4BA1192C, 0x46DF1224, 0x4529AED7, 0x9B1DB01D, 0x810AA334, + 0x661982C8, 0xD3B32F94, 0xF50AC9D6, 0xCE9107C4, 0x203078BF, + 0x6B0F3B2B, 0xCF63520C, 0xACA9E5BF, 0x7FBE448E, 0x51BD1E2F, + 0xDF958295, 0x114A9693, 0x60FCBB39, 0x6669B642, 0xC490D54, + 0xD19C8DBC, 0x14CC7B2A, 0x7106D506, 0xAFDADD98, 0xAF398DF4, + 0x88AC5400, 0x1912BF0A, 0x5389D050, 0x5AF6233, 0xF10842A3, + 0x94DD7008, 0x93812804, 0xD8111DFD, 0xB7C97490, 0x7748A45E, + 0xE70A47A0, 0xC29B718E, 0x55783AEC, 0xA2789E21, 0x97488EBC, + 0xD9222F6A, 0xBF74BDD2, 0x9A983E5C, 0x6CC067D5, 0xBCFDD3B2, + 0xD7A2A5FE, 0x4733F2F5, 0xC7AA3556, 0x1CDB485D, 0x31755CA0, + 0xB9F8E9A7, 0x1346410D, 0x7D885AD7, 0xA30030D8, 0x9813B41C, + 0x8A64EFD4, 0x273F4CED, 0xFEDDC3FD, 0xF34D9687, 0x6B67F2DC, + 0x13F72B5A, 0x96445DDB, 0xAC94658B, 0x8FBF54BC, 0xA7C13389, + 0x95814EA3, 0x7823E5BC, 0x544C27DB, 0xECE6439B, 0xD1141B27, + 0x7A95ACF4, 0x806E58E7, 0xD07B5422, 0xFD0353AE, 0xC1840431, + 0x1DD89E9, 0xA102016D, 0x3730505, 0x1F91E46A, 0x3279C793, + 0xA060010D, 0x9BF86C80, 0xD0C35484, 0x33E81EF7, 0x1C4D3EA7, + 0x6C2A9935, 0xD65E2FB1, 0xBB1CA42E, 0xEA3E3609, 0x7B478C84, + 0x70C1DF93, 0xA872CA92, 0x7C025178, 0xF3B19C7D, 0x6F2BD89B, + 0x1AD7BBDC, 0x39A48FCC, 0xAB5B72E1, 0x821761B9, 0xD2368C1, + 0x20ABB349, 0x29A3F960, 0xFDB18DF1, 0xC4118A52, 0x5E28E88A, + 0x549A3386, 0xD81024CE, 0x82DAD5E0, 0xB20BCD42, 0x9DEA0D36, + 0x49A4992D, 0xAFCB2026, 0xCE7536E8, 0x2C191A65, 0x24FEE0D6, + 0xA769AB6D, 0xF47E292E, 0xCB501191, 0x6DE13907, 0xF1343277, + 0xB32AA746, 0xB055DB9E, 0x87CB8583, 0xA546A4C3, 0xF06F809C, + 0x8FE7A8AA, 0xD0E4037F, 0xD81FCF88, 0xF85830C2, 0x3D6F4840, + 0x5A43700E, 0xCD300C58, 0x3B81C27C, 0x8AF86EA8, 0xF65935FC, + 0x46367D7, 0x7FB75E63, 0xBB28A406, 0x173F982, 0xCB92DD14, + 0xAAA0B1D1, 0x1BCA8892, 0x64D21, 0xFF081A44, 0x8706E93B, + 0xB7DEFAD9, 0x4A6DEF76, 0xDA1670DF, 0x94ABCEBA, 0x465DA4C6, + 0x2484496C, 0x97BB3321, 0xEFB09CB, 0x2988AA2E, 0x2722344E, + 0x5301B744, 0xC5E16C47, 0xF7E05D01, 0xCBE7C20F, 0x4882A6EA, + 0x7168CF40, 0xA98A2747, 0x35F8E15A, 0x5FAF49F9, 0xD2008D24, + 0xCC45A63, 0x858A3255, 0xE4C095B6, 0x7074F7A5, 0x699C98FD, + 0xF0BFE2EA, 0xBDA35C64, 0xE83B891D, 0x7CD09FEA, 0xE8735FDD, + 0xFEA27F06, 0x631D71D3, 0xA08136CD, 0x42395363, 0xDCBA6E41, + 0x1562897, 0x4B1061A9, 0xB4F9640B, 0x38D24E3E, 0x76DF4423, + 0x94B5ED97, 0xFE6AB3B6, 0x6B329B8B, 0x37AFD275, 0xC9ABA12A, + 0xEC9693B, 0xD49B5585, 0xE0C2BEF7, 0x315D40A8, 0x34FBE3A, + 0xEBE81550, 0x569F6FC8, 0x5A9C8404, 0x9DBA0090, 0xFE985DE8, + 0xFF4209AE, 0x89F9E7AF, 0xF841164C, 0x6B4B8F5D, 0x95CB1085, + 0x1990660C, 0x31263B36, 0xCF8F435C, 0xDEBCF88A, 0xD1EE25C2, + 0x53D80B69, 0x9EB8F01C, 0xD682EA3C, 0xEEE79205, 0xA7EFAC65, + 0xE9AA6899, 0x3C1E197E, 0xC8ABE1E9, 0x7BEFE9CA, 0xE792E7D4, + 0xA955D60F, 0x3FE8A02F, 0xC963FDC1, 0xB3D53E43, 0xE28FFC12, + 0x7D5BECCC, 0x18E9F223, 0xBC8B0465, 0x7ED8EEFE, 0xBB90FFEE, + 0x904A9F3A, 0xBC467FF, 0x8AD43A15, 0xF3FC404A, 0x2492D5F4, + 0xBB3F5025, 0xBED0B8BF, 0x467FE6C2, 0x36E55C77, 0x8E2CAC4F, + 0xD12D325F, 0x68A4D268, 0xB1AA0895, 0x755B98FC, 0x2314C4FF, + 0xC3667346, 0x8003B9E8, 0x1185476D, 0x227B69D8, 0x5BADD019, + 0xB06567BF, 0x2B837581, 0x9E11F7, 0x158E67AE, 0x339AA6FC, + 0x8FE50AD9, 0x65902A97, 0x42917220, 0xF9AD39C, 0x2DAAD225, + 0x9673B896, 0xFAE150D6, 0xBEDE3417, 0xD233D722, 0x7E67F33C, + 0x6E150E30, 0xC856792A, 0x28EF69BA, 0xE2AC7866, 0x928D0A4A, + 0x8032C4A9, 0x3D413533, 0xC1BA5CCA, 0xD2BDAC83, 0x94198A14, + 0x3A25972F, 0x253EC030, 0x42D7A1F5, 0x97C28C1C, 0xBE4D0710, + 0x92F31B62, 0x73CA2F55, 0x15FC5417, 0xEF76B1C6, 0x655A963D, + 0xBC17C3FD, 0xD5BED3BC, 0xAB0E4857, 0x38BAD61A, 0x8C17E47F, + 0xE3C27887, 0x45D2A34, 0x6D48333A, 0xF400B767, 0x6ACF41B0, + 0x88DA15A9, 0x3FA0EAB1, 0xAF7B3786, 0x87F182FF, 0x4112A079, + 0x53360864, 0xDB5CE625, 0x630678D7, 0x63E01F17, 0x7BF658F1, + 0xB5E4F1A3, 0xB30E4393, 0x27454C31, 0x8E7E0E2, 0x2151A5F, + 0x2892E2B2, 0x92B53840, 0x1EB3D483, 0xA4273A65, 0xF0CC632, + 0x99AC2694, 0xE0A19111, 0xC7FBA613, 0x46C8F873, 0x88A27741, + 0x7E9A5972, 0xC2E76F79, 0xA5CA8180, 0xA28FF0EE, 0x2A1F7DE1, + 0xCC130B22, 0x50ECFD8A, 0xF5BAA999, 0x5FA2EC9C, 0xC1B5C5C4, + 0x90EC0E5D, 0x9C26620A, 0xA97D2935, 0xE1C08B89, 0xCB574B80, + 0xB3DE8B61, 0x1AF89CA0, 0xFD4A77DC, 0xED9485E1, 0xAF804C92, + 0x6B8EB167, 0xDCC836B6, 0x85A7FFFD, 0xD4E9A94A, 0x77DDCC31, + 0x8897B5F9, 0xA4FA88D3, 0x8ECB3E82, 0xBC175E89, 0x963A073E, + 0x547520C7, 0xEEB81BFB, 0x1D8B1867, 0x78833A4, 0xE40A0CCB, + 0xF8D5452F, 0x954BDCF6, 0xAC228FFA, 0xE6B32DF3, 0x181ED541, + 0xACE26A73, 0xF1C1440D, 0xA1B93EDD, 0xE90FF70A, 0xF6741843, + 0x4DF581AC, 0xBE785B32, 0x751509B5, 0xC30AD864, 0xC18D8A72, + 0x3BF07FD4, 0x827B4CBA, 0x7DD39A4F, 0x2CFEFE25, 0xE071F371, + 0xC0C3F6CB, 0x1FD70F85, 0xFDABDA88, 0x8F308991, 0x4CD794F9, + 0x5D18B022, 0xC13D5FC2, 0xD84337F, 0xED868BB8, 0x9904CD2, + 0x7551499C, 0x124B262, 0x5139C2A5, 0xEF56F59B, 0xE8B87B40, + 0x2F030010, 0x42D2E271, 0x4E344F3F, 0xC87CDFE1, 0x44A615C7, + 0xC32DB543, 0xCFC889E4, 0x60078825, 0x786F5917, 0x2DF9E82, + 0xEE26DA93, 0x48D0C94, 0xE97D5456, 0xF487F2EB, 0x35A47D65, + 0x183DA0CA, 0x1A7E1218, 0x8D2674C5, 0xB38D0910, 0x5D9C871C, + 0x7B463ED1, 0xBBC90FFD, 0x31DED99F, 0x5171DCFA, 0xF9413D0B, + 0x632A00FD, 0x7B6DA34C, 0xA475C597, 0x8E157360, 0x5911736B, + 0xCA19D544, 0xF487D465, 0x6E749BB9, 0x888BFB52, 0x3FDAD497, + 0xDB5D401A, 0x7015A4EC, 0xC1F571, 0xB2D7671A, 0x8203032F, + 0x5A755E9, 0x24F25BF5, 0x4D2AC51B, 0xE5950FA7, 0x20196F5B, + 0x68E90D90, 0x5D24196C, 0x9CFCD1C0, 0x745C0318, 0xEEB977E8, + 0x14AA16D, 0x80662EE1, 0x7BD55DE3, 0x35EE2B08, 0xD3E8051F, + 0x3D0EA4B5, 0xD551399E, 0x8FF94435, 0xDD4E34ED, 0x9139E4A3, + 0xE6AF7E5E, 0xE1ED4EAF, 0x638D2846, 0x7084F7EB, 0xF9705E17, + 0x2E7A89DC, 0x45855252, 0xBA8E51C7, 0x8510425C, 0xA97AF6D, + 0xF0C27DA, 0x9E00CA15, 0x3BCC0651, 0xEEC38CA9, 0x19597B08, + 0x4C68AB5D, 0x16CA41DB, 0x35EFBEF9, 0x1E441529, 0x25131FA1, + 0xC3D8483C, 0xD8650832, 0x60D271E3, 0x47C92A47, 0x9EFBB554, + 0xBF5DBFBF, 0xFF421FA2, 0x3A38F28, 0xAE4EE06B, 0x819945D1, + 0xC43101, 0xA3EE9278, 0x5BAE3EE4, 0x57ACE55E, 0xC3D95551, + 0xC00717B0, 0x38EC1B28, 0x123597, 0x6314F3F7, 0xB3F99DAB, + 0x7226CE1E, 0xE8350DE6, 0xD7C582CA, 0xBB1D38D, 0x54E656FE, + 0x400B60BD, 0x48291A06, 0x97819179, 0x850BF937, 0x93888A87, + 0xF51E684F, 0x4B111E, 0xC6B37E02, 0x6C923547, 0xEF25AF3B, + 0x8C12CE8E, 0x89296F4F, 0x3BE2C3DA, 0x8A29A35B, 0xBBE2E80C, + 0x79D0188D, 0xBD4320BC, 0xAFF4F0A9, 0x7FAE6C37, 0xCCA1777E, + 0xB06D2AE1, 0x26B6398C, 0x5A3E5876, 0xE814DF4E, 0xC43E9677, + 0x4C962CE8, 0x6C274FF8, 0x8B5A1A03, 0x963E1401, 0xD8CE0DF7, + 0x659190E7, 0x3AD63330, 0x894BFEDB, 0xEB4CF73A, 0x3731BC86, + 0x30FE0433, 0x94F5FD2, 0x8417999C, 0x337E86B8, 0xAFE08EF6, + 0x5B5F05DC, 0x8001C95F, 0x8C8092DC, 0x5EBC7995, 0xDCBE88EE, + 0x9C602950, 0xE3376596, 0x5D80E318, 0xAF3AC8C3, 0x8C7EDCC6, + 0x3E795E7, 0xDA8987AB, 0x7B7B4E3C, 0x3239CD40, 0x1B527DED, + 0xC95DEF29, 0xE40D047D, 0xE53C10C5, 0x5BAF528B, 0xA47921F9, + 0x6DCB9B0A, 0x7EA11040, 0xBBEFCCD5, 0x502F33FA, 0xAB5EBE8F, + 0xD59C448, 0x8C34FF3D, 0x4A3255A2, 0x4CFFDCB1, 0x3880A182, + 0x3499DAAF, 0xA1319450, 0xC550CCE5, 0x51026E2C, 0x73C4F05D, + 0x21F5FAAC, 0xE1C31B7D, 0xA390E6E6, 0x7B1582ED, 0xB92B4C3B, + 0x41C1128E, 0xF728F655, 0x3BC8AE16, 0x8A2A4E57, 0x9A8A7DE, + 0x86065598, 0x4328A574, 0xDBDAFC7D, 0x2C5EE98, 0xEAB5CE80, + 0xF7E8F60C, 0x7B4C3C0E, 0xE4A2F720, 0x90330B1D, 0xB6783BF2, + 0x48A8C26B, 0x847F1AAC, 0x351DB247, 0x43E84AC5, 0xAF726AA3, + 0x5CB4C059, 0x2C5784DE, 0xBA1111FB, 0x9F427968, 0xE41D29D1, + 0x2CAA8CA7, 0x764C8B63, 0xBDAA6F10, 0x280277B6, 0xE4A908B6, + 0xA6A9783, 0xD0643B01, 0x44FE52AD, 0x60B04A5, 0x194C190E, + 0xF73DA669, 0x12EE11C8, 0x2C769D96, 0x694787A4, 0x9FB03623, + 0xAC6F837C, 0xFC1E5935, 0x16246787, 0x4F94B817, 0xA3A4281F, + 0x1535252D, 0x13F8F1CB, 0xAAF6A508, 0xB38E10E, 0x7A4B238, + 0xC6A47410, 0xC864256, 0xF3C25E27, 0x94CE51D4, 0xF4ECAEEA, + 0x32684D74, 0x1AC8765, 0xDE6F6313, 0xF8C09409, 0xFB21FD21, + 0x6DB586BA, 0x241894B5, 0x65806E1F, 0x4B9D0DE7, 0x32DDDD16, + 0x3B16F0B0, 0xB56CAAF0, 0xC533ED5C, 0xADE48431, 0xB5893123, + 0xE977699C, 0xB295808B, 0x7A252898, 0xE3748392, 0x687A8ACD, + 0xB792504E, 0xBF4E2D8A, 0xB5EC4376, 0x754D9C34, 0x17BE53CC, + 0xC817A127, 0x732346E2, 0x29593976, 0x41D6AF89, 0x9072FAEC, + 0xC2B22666, 0x16A150DF, 0x4D379A36, 0xE732017F, 0xA6D12516, + 0xEA3DB9B5, 0x6E4C766B, 0xCA0ADEF5, 0x75E98F68, 0xC31687C3, + 0x62F16F66, 0x6486B129, 0xE237231B, 0xC6653007, 0x2BE06DFC, + 0x2BC32DC4, 0x9E3DD054, 0x47AA701E, 0x7741E537, 0xA09F9CD8, + 0x9D40881, 0x4F02F58, 0x6A5F31BB, 0x32BBBD23, 0x4520EB05, + 0x1DBFDD00, 0x6CCEC7D, 0x48CFC70C, 0xB41FBC13, 0x5B377E90, + 0x3B87923D, 0xC09F6D28, 0xC1CF24FB, 0xDD6BE459, 0x8B8BDD37, + 0xF7B103C8, 0xC1611360, 0xA8B8FCC8, 0xC16D4E2, 0x6AD23606, + 0x951A051, 0x6FC3B984, 0x95876867, 0xA0E1A04C, 0x8267F62C, + 0xC4B69588, 0xF53421DF, 0xC348685B, 0x59769E2B, 0x21F0FF90, + 0x2B978BB4, 0x3FDA987B, 0x216F4FFF, 0x95C68589, 0x2286F5D8, + 0x81E2702D, 0x88E2D01F, 0xE6F6B356, 0x2EA0C31, 0xA5E11CAF, + 0xE17DC578, 0x2115A0EA, 0x8DC2B323, 0xEB86957, 0xF3C7BECB, + 0xBCD805EC, 0x1121C3F5, 0xE6DEF224, 0x8EA2EE24, 0x2703D7B7, + 0x24D73574, 0x4068552C, 0xA85F5B6A, 0x65B563E, 0x4050954C, + 0xC7043820, 0x91E4A088, 0x19084C84, 0x7250FB54, 0xC1EC72, + 0x9FDB2412, 0x3B78E4E9, 0x588C2D17, 0x345C3232, 0xBC7CCB29, + 0xCB5F1F0A, 0x24EDD656, 0x7A9F0605, 0xC2EDB0E5, 0x7F01D20D, + 0x8EB211A2, 0x74AC4C1A, 0x37EDEDDB, 0x55B9AFF2, 0x100C4193, + 0x43CDF2C3, 0x9C75E7C1, 0xC43ABEFF, 0xB9704827, 0xDD4E6376, + 0xEA5FA0D3, 0xC6E14A66, 0xCB163673, 0x9515389, 0x5D3D30C5, + 0xD1FF8777, 0xC1347921, 0x21A5BAC, 0xD6CB5F87, 0xC6CE680B, + 0x46D1E5FB, 0x9B98BC15, 0x8D1446D6, 0x184659E7, 0xAAC79D5A, + 0x773E019E, 0xA1B9F814, 0x933D3D0B, 0x11DB7615, 0xC206A22A, + 0xE4EF5BA1, 0xF0EFA194, 0xDE0E6C2B, 0xBE185B42, 0xC28FDE0C, + 0xE416DD8A, 0xC636753F, 0xAFD119E, 0xB0198B17, 0x94C4115C, + 0x76EDF82A, 0x66818700, 0x6F003485, 0x993DFB2B, 0xF5A1F91E, + 0xDAB0080C, 0x7DF290D2, 0x72F65E9B, 0xBC126473, 0xF6050B10, + 0xB7380CA, 0x3352530, 0x9A403054, 0xB12581C1, 0x6F8E0370, + 0xBB5C1ED1, 0xCE738AFF, 0xE9F605DB, 0xA976BFE4, 0x68C9D107, + 0xA2BD1833, 0x545ACCE2, 0x965FBAF, 0x12D998F, 0x2C16B1CD, + 0xB20788BF, 0x96AADE36, 0xDF821415, 0xF1EBD654, 0x33F3C413, + 0xF2F2A6BF, 0x2DFB0ABA, 0x96845EC5, 0xB24622DD, 0xA83EEE5F, + 0x49DF9AF8, 0xB8DCFB8A, 0x16F7643, 0x436EFD30, 0xD90C9F8, + 0x9C10CD4E, 0x600CB15B, 0xE686606A, 0x5EC0502C, 0x23B2DCE5, + 0xDD5DE18D, 0x235A755C, 0xCB58A693, 0xACBEAFDE, 0xCA201FB5, + 0x2AE90380, 0x4F7455EC, 0xCA923312, 0x1BD202DD, 0x2D92B9E3, + 0xA2670F18, 0x831728C, 0x77D33D8C, 0x12400BDA, 0x9508A626, + 0x9253042B, 0x63C70C8C, 0x5496452F, 0x9237D610, 0x10448F3A, + 0x9303C709, 0x660D7EC, 0xDF6750F0, 0xBC4F14F2, 0x8F59720C, + 0xEE5AB051, 0xD5EC1228, 0xCC3E04CE, 0xE9E4D3B9, 0x8676FA58, + 0xF523860E, 0xF87D9BED, 0x4A6D02C9, 0xC5AD6CF0, 0x65F09045, + 0x8C620984, 0xDC40B4CD, 0x4216C291, 0x7A44C04B, 0x1E2B5D31, + 0xA0E77B7D, 0x12076C51, 0x22262FA1, 0x483B54F1, 0x2A7EF465, + 0xD1395E25, 0xB564369F, 0xC94A47A4, 0xFD678BAA, 0xECEE926A, + 0xE41A06AE, 0xE8F293C1, 0x3EB052BE, 0xD0959EF1, 0x93FF1935, + 0x4D65E4F1, 0xE87FC1F9, 0x3BD4BB2B, 0xD5F24F5B, 0x54FF70D4, + 0x968C7B60, 0x44F9BDE4, 0xF4894BDF, 0x3CFDDF7B, 0xD5CC3F10, + 0xD7F952C2, 0xEA3DCB60, 0xEFDAC96A, 0xBBF8F5EB, 0x41526813, + 0x714E3D51, 0x5E15A386, 0x1286AF4F, 0x5E1E5A3E, 0x676C9938, + 0xA716071B, 0x14D79998, 0x5CB794ED, 0xD815EDED, 0xCB1CA55A, + 0x9D6D74FD, 0xBE032C25, 0xF3FE1425, 0xC0CB5217, 0x3931A93F, + 0x82DB8222, 0xD8FF587F, 0x5AD4E8AC, 0xBCF00442, 0x4298A961, + 0x9F8CC3C2, 0x60E2347F, 0x7E090E, 0x691B735, 0x3D4C4D83, + 0x5612B097, 0x7B8DA321, 0x2C28A057, 0xF8FE8901, 0xDA39D0DD, + 0x465CE561, 0xA78756, 0x3B771E01, 0xE638B09, 0x201853B5, + 0xF934D7D2, 0xBD515A83, 0xC1B5C34E, 0x89159FA9, 0x2DDE3EBE, + 0xE27771DB, 0xB5983F05, 0xA3FD869D, 0x8ABA53CB, 0x55C8606C, + 0xDAB769C3, 0x4C4C2EAC, 0x18EE2A56, 0x88452A07, 0x9767C386, + 0x5C0418D6, 0xF79CA785, 0xF291195D, 0x9B0C286F, 0x68460BED, + 0xBF0079E5, 0x9906D932, 0x2F9E5535, 0x2A3C4947, 0xF0E240C3, + 0xE835A264, 0x43F38C0, 0x82DAADD8, 0x313612B1, 0x560D56FB, + 0x61BD734A, 0x58FD6B36, 0x2C45C40B, 0x55F70159, 0xA21A817D, + 0xAAA6FCE, 0x85BFDFB9, 0x1C71DE25, 0x56CB4C2C, 0x50FD91E5, + 0xF2340E88, 0x72BD5702, 0xB4FFBD3A, 0x1B35B171, 0xE94A34BD, + 0xC4C77575, 0x95B10420, 0x2471BC3F, 0xCB429841, 0x6DC5347F, + 0xC93CF782, 0xF1D26B2C, 0xEB2A260F, 0x67C3AE9, 0x34A56A4, + 0xF1F3D01B, 0xD8295F22, 0x7F9E5D4A, 0xE4DB3DEA, 0xE1531DCB, + 0x2C5FF857, 0x73622A7C, 0xC2691F1, 0xBC622B61, 0xE6A08C89, + 0xBA1807D4, 0x43ADBE43, 0xD90D427C, 0xC7A5C24, 0x613ED316, + 0xEC810B10, 0x1049BF74, 0x9A14C123, 0xA7B24E7E, 0x73254165, + 0x2C54081E, 0x14FF25AA, 0x7A12F3B4, 0xB4DF7C56, 0x89BFE8FC, + 0x5D5A04A6, 0xBE007173, 0x829DF863, 0x63E5E57D, 0x58F64C28, + 0x31A38144, 0xE843289B, 0xB48DFAF1, 0x2B335C2A, 0xEC3C96CE, + 0x255543F6, 0x33F17311, 0x3C60C51A, 0xE5D0D660, 0x5E162559, + 0xA2D9416, 0x9DDE4967, 0x28156A65, 0x71650796, 0x74EE54D1, + 0x3E8C19F7, 0x797C1E42, 0x2C536DFD, 0x2F3EED4D, 0x3BFC7C95, + 0x8EAEF87D, 0x18F5B02A, 0xA3532651, 0x24508E13, 0x280B9049, + 0xE4FC61CB, 0x388BA30F, 0xEC180A43, 0xBFDE77A4, 0x98CDB399, + 0xF82B586D, 0x38525AE7, 0x9D857BE8, 0xDD939D18, 0xD5CA6EBA, + 0xB70DDBA, 0xDFF43867, 0xD06AB2D0, 0xD8C78BB, 0x78F6AE4F, + 0x4C9A58CC, 0x9F9AA50E, 0x7D6A3912, 0xD897C7E4, 0x82F5939D, + 0xA4A9FFF5, 0x2CB56FDE, 0x3E082D4B, 0xB829DC58, 0xE4515CEB, + 0xCE585A33, 0x27901244, 0x68860E95, 0xE156A451, 0x9E351FE0, + 0xC69BD757, 0x4B2C4A2B, 0xD5DE5A91, 0x3557B0DE, 0x99E910B0, + 0x975BE470, 0xDB4DE130, 0xE4C6DA1D, 0xC2BC058F, 0x37544906, + 0x12CC200E, 0x54569133, 0x6586FC03, 0xF183C0CF, 0x642583E, + 0xFBE882CD, 0x8A098C35, 0xE8300988, 0xFE835E55, 0xEA74FD24, + 0xF3127AB2, 0xEE8379F2, 0x3F136FD2, 0x472AA942, 0x3BC1A7D7, + 0x5B6A8A98, 0xF039CCF3, 0x5E55425B, 0x3F801B4, 0x44556FB4, + 0xCC966D37, 0x56E32B90, 0x2BCDA2E5, 0xC70F1125, 0x8C2A015C, + 0x3D37FCA7, 0x2118A4EF, 0xCE051A9C, 0xCB84DCB9, 0x8451C9E0, + 0x4BDB1900, 0x8FC71D5D, 0xF61FD749, 0xA696D2E0, 0x6EED502A, + 0xB345CE8B, 0x76FCDA8E, 0xBE4A45F8, 0x8375E9E7, 0x625FF29B, + 0xCEC61240, 0x3876B21D, 0xBA8C8F59, 0x8CD169C6, 0x9F82251F, + 0x2E6EC495, 0x99319E, 0xB0160B46, 0x8B77EDD8, 0x6217902B, + 0x76FA6AD0, 0xB541F2BC, 0x961EA91C, 0x6F554C1F, 0xBD92328D, + 0xA9C077FD, 0x90A5311C, 0xEFE9B1FB, 0x9C84AA8C, 0x812517C3, + 0xFE71D7F4, 0xC4F6A5BF, 0x8B75A262, 0xC726EB36, 0x5F803035, + 0xCECDE2B7, 0xF61152A8, 0x78557ED1, 0x50F3BB55, 0xDD830290, + 0xB125B524, 0xC8683B0D, 0xE5FD573B, 0x48B13066, 0x62AE556E, + 0x5A637C89, 0x498D69F, 0x3F3A5BE5, 0xB98B86D7, 0x20CF4AF4, + 0xA3E55E7D, 0xEE93FC6F, 0xCCA95763, 0x5B3C5706, 0x8342B013, + 0xA0C7BDB9, 0x83D686E4, 0x6934B64, 0x324D75C3, 0x9A100C81, + 0x72E7E9AE, 0xC729A8AC, 0x9E8489E0, 0xFE5BC233, 0x64709AE9, + 0x113437BC, 0x296DEBC0, 0xC4376603, 0x9F0CD7EE, 0x6412AB97, + 0x3EECEFCD, 0x62DCD50, 0x15DFF1, 0xEEFDCF8E, 0x119849C1, + 0xDAAC93FF, 0xD531AF57, 0x82A10F47, 0xD55B7A97, 0x2F3A268B, + 0x4F1CC181, 0xAE01C1AC, 0xF3CF6F61, 0xE8BDAED5, 0x7397FD99, + 0xDD36A03C, 0x9BAED7C3, 0x51404903, 0xB9867B61, 0x3880A4FD, + 0x42B90A49, 0xA94696C1, 0x546DEA1D, 0xEE73A3DE, 0x1A4BAC37, + 0xBC6AF7AE, 0x7DD5B57B, 0xD2F121F, 0xD2BCCA1E, 0xD5DC4753, + 0xA135C08C, 0x78E97831, 0x9B91C00B, 0xFFF2C044, 0x147B797F, + 0x299CFB60, 0x71083BB, 0xB39A6C4F, 0x4814E3E1, 0xBD246AB0, + 0xBCD61250, 0x2D0870, 0xC660435C, 0xCA11681E, 0xADA4C80E, + 0x790C8875, 0x8C4F0D08, 0x48D90C74, 0xE874E9AA, 0xA8013EE8, + 0xB2D23A7A, 0xAF73A16E, 0x2485512C, 0x698E0CB2, 0x2FF566C9, + 0xC1B0C3C6, 0x2BE17C0E, 0xC42C3907, 0xD8A2EA94, 0x8991D24C, + 0x19B939F1, 0xF936F8B3, 0xA72D7EF1, 0x97EED001, 0xBF9C5156, + 0x75F08A67, 0x9AFD5756, 0x5D9D359C, 0xF905B7EC, 0x2B1553E1, + 0x9E0FD4E1, 0x8DC4814C, 0x89F28E6D, 0x14174915, 0x1F3A4217, + 0xA8F367F9, 0x93EE87C5, 0xAD70C6D8, 0xF04D465C, 0xE403D72B, + 0xA686EC0F, 0xCD3A5728, 0xA1BD007, 0x9E21E401, 0xAE8517CF, + 0x6DDB79FC, 0x8CB2C475, 0x6F71544, 0xBEAC91CF, 0x4739DC4E, + 0x6CF4F788, 0x36BAD9AC, 0xF23568D4, 0x250BAB0A, 0x4633384F, + 0x54F6F251, 0x454F9605, 0xCB1A346, 0x632E207F, 0x3017539C, + 0x174A33ED, 0xBDCFD2DE, 0xC17F3D39, 0x17B8A9A2, 0xC267FB51, + 0x9322387D, 0x348760C, 0x3C14D7E0, 0xE4E4254E, 0xCA72AA41, + 0xB6102ED3, 0x6317A3F, 0xD3B6B9F7, 0xA8C71BB7, 0x6E452957, + 0x3F896E32, 0xE38A4A58, 0x9893F432, 0x110A21D4, 0xE835FEBE, + 0x90F51080, 0xD0AC5AF, 0x4FCB9903, 0xFE547785, 0x144B285D, + 0xD0ECC753, 0xAE503BA4, 0x57CEAABC, 0x95713FE6, 0x5B0F4F86, + 0xD94BD751, 0x4017F139, 0xF60F5E1D, 0xB9A63351, 0xF7F94F6A, + 0x7E556ECC, 0xBFDB8642, 0xB70D07D, 0x351BEA77, 0xD1F3CAD, + 0xA3D7EF4D, 0x1EAA28E3, 0x98A2EA79, 0xD8647392, 0x1B896804, + 0x35CA6A08, 0x305258F, 0xE58BD955, 0xABCB6278, 0x87CF1146, + 0x13145966, 0x45BB55CD, 0x818AA368, 0xA027F11F, 0x64C427A3, + 0xEC831B99, 0xF2BD53F9, 0x7FDA7301, 0x35BE80D4, 0x5256E6FB, + 0xC97D33AE, 0x30921709, 0xC2724BEC, 0x78F5436F, 0x4F5749CD, + 0x9007F551, 0x327C31C0, 0x89782D13, 0x119AD125, 0xB1071A01, + 0x63100C70, 0x83120035, 0xA8E2E403, 0x7E213FA3, 0xBF06AAC4, + 0xBA68C4D9, 0x4B568927, 0x1DDD40F, 0x10FC10E8, 0xBBD7230A, + 0x96475640, 0x8C8E6EC1, 0x44A1134A, 0xEF0F40F0, 0x51E2A5E0, + 0x61AE6D65, 0x9DE72FD6, 0xB1711336, 0x90BEB84, 0xD610EFC6, + 0x3D231F91, 0xB5885164, 0x2CB2112C, 0x36F50789, 0x3DEF2AB9, + 0x1D9DC1DA, 0xA37DB070, 0x2AA92EB, 0x2D57ED6E, 0xD6E2C2CD, + 0xB78FC54C, 0x767A565E, 0x1D1F5AAE, 0x89F256DB, 0x716A97D, + 0x1344431D, 0xFAF015FB, 0xFED59649, 0xC479882A, 0xEEFC3D1E, + 0x840AE162, 0xD963A347, 0x75462C25, 0xDA990E07, 0x9A57DE31, + 0x74A35F20, 0x91852CD6, 0x3F16DE14, 0x5FA6A255, 0x47D00F85, + 0x1B4836C9, 0xC73D0290, 0xE301026B, 0x592068D6, 0x7C32A301, + 0x3A3C04C4, 0xB5BD3BAF, 0xB8C3BF60, 0x76723A1B, 0xD05BC35E, + 0x7679021C, 0x6298096, 0x590BA59C, 0xBB30A2F6, 0xE5F6B06C, + 0x21BD2A9E, 0xAC68D7DA, 0xEDA2ED5A, 0xA10E60FA, 0xABDBF569, + 0x17F5868E, 0x82AA8505, 0x384BD8FC, 0x68DC2746, 0x8F029C0D, + 0x3755EB11, 0xAEF4BB79, 0x453B87BA, 0x9926977F, 0x1FA1B806, + 0xC905618, 0x9BFE8E92, 0xF6F68A5A, 0xAA955D92, 0x44F57A4A, + 0x2186E272, 0x62EB01DA, 0x85A2D502, 0xB087955D, 0x26FF2BA0, + 0x8D462C04, 0xE024573B, 0x609CDBD7, 0xA99B9D19, 0xFEEB3F60, + 0x12903A0D, 0x46480C6, 0xDD0BD1B9, 0x6C60C43, 0x5E11A4FE, + 0x935E9E58, 0x8A7F6D33, 0xA505132D, 0xBB2E3E12, 0xF48633F4, + 0xF3BA8CF7, 0xC25D4EDD, 0x788672B8, 0xB2812608, 0xACB3A62, + 0x2EEB679A, 0x443A71B9, 0xC42F4B12, 0xD28B3482, 0x5571FA8A, + 0x5C0B3D55, 0x8B8619C6, 0xF564F10C, 0xD9A7C914, 0xFBD1EF46, + 0xCEABC573, 0xEC609D28, 0x5839413B, 0x5019E901, 0x248FFF30, + 0x7BFFB801, 0x7FD46584, 0x43702812, 0x3A5A0880, 0x7E3E9EDA, + 0xCA4623E3, 0x2FB87A70, 0xFE70D956, 0xCE9EB3E6, 0x9A2CD2F1, + 0x92EFB0C8, 0xC7E23873, 0x53B63A86, 0xB9D93548, 0x3C022B2, + 0xCF4F22A6, 0x981E70BC, 0x4A05F3AB, 0xD763E93B, 0x6EAF767D, + 0x4162629D, 0xD82A25E7, 0x6CDD19A3, 0x13524F68, 0xE5F23FDC, + 0xB37F311F, 0x35FD43B6, 0x36626469, 0x1E409CF6, 0xE4C04F9D, + 0xC1B58001, 0xD131078F, 0x9DE279A, 0x80B62212, 0x526405DD, + 0xC17777C1, 0x7045FCDC, 0x53862AEC, 0x5D583056, 0xEB532222, + 0x5837EA32, 0x719C06A4, 0x43D4F131, 0x577C6DDB, 0x9E5815A7, + 0x8189DDD9, 0x170F154F, 0xEF813B20, 0x4DD83A53, 0xB09A28FD, + 0x8D0DBED5, 0x1836596D, 0xC5BB2696, 0xA69FC859, 0xD6FF5E0D, + 0xCCC65761, 0xC818C6F7, 0x7A25F980, 0xF949133, 0xC515C093, + 0xA8AD04B5, 0x6768AC1C, 0xB5BE2C4A, 0x4F04616F, 0xBD28E4E3, + 0x4CCA6347, 0x5F61C031 +}; + +/* The source data is random across the q31_t range. Accessing it by word should + remain random. */ +q15_t * transform_fft_q15_inputs = (q15_t *) transform_fft_q31_inputs; + +q15_t dct4_transform_fft_q15_inputs[TRANSFORM_MAX_FFT_LEN * 2] = +{ + 0x0000, 0x2d5c, 0x54d5, 0x714b, 0x7f0d, 0x7c51, 0x6972, 0x48e4, + 0x1edf, 0xf0da, 0xc4cb, 0xa06c, 0x8874, 0x8001, 0x882a, 0x9fe2, + 0xc413, 0xf00c, 0x1e16, 0x4839, 0x68fc, 0x7c1f, 0x7f25, 0x71ab, + 0x5570, 0x2e1e, 0x00cf, 0xd367, 0xabc7, 0x8f16, 0x810d, 0x837e, + 0x9619, 0xb672, 0xe057, 0x0e58, 0x3a7c, 0x5f0a, 0x7741, 0x7ffe, + 0x781e, 0x60a7, 0x3ca4, 0x10c2, 0xe2b4, 0xb873, 0x977b, 0x8415, + 0x80c3, 0x8df6, 0xa9f6, 0xd121, 0xfe61, 0x2bd6, 0x539c, 0x7087, + 0x7ed8, 0x7cb1, 0x6a5c, 0x4a38, 0x2072, 0xf277, 0xc63d, 0xa182, + 0x890b, 0x8005, 0x879b, 0x9ed2, 0xc2a6, 0xee70, 0x1c81, 0x46e0, + 0x680c, 0x7bb7, 0x7f53, 0x7268, 0x56a3, 0x2fa0, 0x026f, 0xd4ed, + 0xad02, 0x8fdc, 0x8145, 0x8321, 0x9531, 0xb51f, 0xdec5, 0x0cba, + 0x390a, 0x5df1, 0x76a8, 0x7ff7, 0x78ab, 0x61b5, 0x3e10, 0x125e, + 0xe449, 0xb9cd, 0x986d, 0x847f, 0x8099, 0x8d3c, 0xa8c4, 0xcf9f, + 0xfcc2, 0x2a4f, 0x5260, 0x6fbf, 0x7e9d, 0x7d0c, 0x6b40, 0x4b89, + 0x2203, 0xf414, 0xc7b1, 0xa29c, 0x89a7, 0x800e, 0x8710, 0x9dc5, + 0xc13a, 0xecd5, 0x1aec, 0x4585, 0x6718, 0x7b4a, 0x7f7b, 0x7320, + 0x57d3, 0x3121, 0x040e, 0xd675, 0xae40, 0x90a7, 0x8182, 0x82c8, + 0x944f, 0xb3d0, 0xdd35, 0x0b1d, 0x3795, 0x5cd5, 0x760a, 0x7fec, + 0x7933, 0x62bf, 0x3f7a, 0x13f8, 0xe5df, 0xbb2a, 0x9964, 0x84ef, + 0x8073, 0x8c86, 0xa796, 0xce20, 0xfb23, 0x28c6, 0x5120, 0x6ef2, + 0x7e5e, 0x7d63, 0x6c21, 0x4cd7, 0x2393, 0xf5b2, 0xc927, 0xa3ba, + 0x8a47, 0x801c, 0x868b, 0x9cbd, 0xbfd1, 0xeb3b, 0x1955, 0x4427, + 0x6620, 0x7ad7, 0x7f9d, 0x73d3, 0x5900, 0x329f, 0x05ad, 0xd7ff, + 0xaf81, 0x9176, 0x81c4, 0x8274, 0x9370, 0xb284, 0xdba6, 0x097f, + 0x361d, 0x5bb5, 0x7566, 0x7fda, 0x79b6, 0x63c6, 0x40e2, 0x1592, + 0xe777, 0xbc8a, 0x9a5e, 0x8564, 0x8053, 0x8bd5, 0xa66b, 0xcca2, + 0xf983, 0x273c, 0x4fdd, 0x6e21, 0x7e19, 0x7db3, 0x6cfd, 0x4e21, + 0x2521, 0xf750, 0xca9f, 0xa4dc, 0x8aed, 0x8030, 0x860a, 0x9bb9, + 0xbe6b, 0xe9a1, 0x17bd, 0x42c6, 0x6523, 0x7a60, 0x7fbb, 0x7481, + 0x5a29, 0x341c, 0x074c, 0xd98a, 0xb0c6, 0x924a, 0x820b, 0x8226, + 0x9297, 0xb13b, 0xda18, 0x07e0, 0x34a4, 0x5a92, 0x74bf, 0x7fc4, + 0x7a34, 0x64c8, 0x4247, 0x172b, 0xe90f, 0xbdec, 0x9b5d, 0x85dd, + 0x8038, 0x8b29, 0xa544, 0xcb27, 0xf7e5, 0x25af, 0x4e97, 0x6d4b, + 0x7dcf, 0x7dff, 0x6dd5, 0x4f69, 0x26ae, 0xf8ef, 0xcc1a, 0xa601, + 0x8b97, 0x8049, 0x858f, 0x9ab9, 0xbd08, 0xe809, 0x1625, 0x4162, + 0x6422, 0x79e4, 0x7fd3, 0x752b, 0x5b4e, 0x3596, 0x08eb, 0xdb17, + 0xb20e, 0x9322, 0x8258, 0x81dd, 0x91c1, 0xaff5, 0xd88c, 0x0641, + 0x3328, 0x596a, 0x7412, 0x7fa8, 0x7aad, 0x65c6, 0x43a9, 0x18c3, + 0xeaa8, 0xbf51, 0x9c5f, 0x865c, 0x8023, 0x8a82, 0xa421, 0xc9ad, + 0xf646, 0x2422, 0x4d4d, 0x6c70, 0x7d80, 0x7e46, 0x6ea8, 0x50ad, + 0x2839, 0xfa8e, 0xcd97, 0xa72b, 0x8c46, 0x8067, 0x8518, 0x99bd, + 0xbba7, 0xe671, 0x148b, 0x3ffb, 0x631e, 0x7963, 0x7fe6, 0x75d0, + 0x5c6f, 0x370f, 0x0a89, 0xdca6, 0xb359, 0x93ff, 0x82a9, 0x8199, + 0x90f0, 0xaeb2, 0xd702, 0x04a2, 0x31aa, 0x583f, 0x7360, 0x7f88, + 0x7b21, 0x66c0, 0x4508, 0x1a5a, 0xec42, 0xc0b9, 0x9d66, 0x86e0, + 0x8012, 0x89e0, 0xa302, 0xc836, 0xf4a8, 0x2292, 0x4c01, 0x6b91, + 0x7d2c, 0x7e87, 0x6f76, 0x51ee, 0x29c3, 0xfc2d, 0xcf16, 0xa858, + 0x8cfa, 0x808b, 0x84a7, 0x98c5, 0xba4a, 0xe4da, 0x12f1, 0x3e92, + 0x6215, 0x78dc, 0x7ff4, 0x7670, 0x5d8c, 0x3884, 0x0c27, 0xde36, + 0xb4a7, 0x94e0, 0x8300, 0x815a, 0x9024, 0xad73, 0xd579, 0x0303, + 0x302a, 0x5711, 0x72aa, 0x7f61, 0x7b90, 0x67b5, 0x4664, 0x1bf0, + 0xeddd, 0xc223, 0x9e71, 0x8769, 0x8007, 0x8942, 0xa1e6, 0xc6c2, + 0xf30b, 0x2102, 0x4ab1, 0x6aae, 0x7cd2, 0x7ec3, 0x7040, 0x532b, + 0x2b4b, 0xfdcc, 0xd097, 0xa988, 0x8db3, 0x80b4, 0x843a, 0x97d1, + 0xb8ef, 0xe345, 0x1155, 0x3d27, 0x6108, 0x7851, 0x7ffc, 0x770b, + 0x5ea6, 0x39f8, 0x0dc4, 0xdfc7, 0xb5f8, 0x95c5, 0x835c, 0x8120, + 0x8f5d, 0xac37, 0xd3f2, 0x0164, 0x2ea8, 0x55de, 0x71ef, 0x7f36, + 0x7bfa, 0x68a7, 0x47be, 0x1d85, 0xef79, 0xc390, 0x9f80, 0x87f6, + 0x8001, 0x88a9, 0xa0cf, 0xc54f, 0xf16e, 0x1f70, 0x495e, 0x69c6, + 0x7c74, 0x7efa, 0x7106, 0x5465, 0x2cd1, 0xff6c, 0xd219, 0xaabc, + 0x8e70, 0x80e2, 0x83d3, 0x96e2, 0xb796, 0xe1b1, 0x0fb9, 0x3bb8, + 0x5ff7, 0x77c1, 0x7fff, 0x77a1, 0x5fbc, 0x3b69, 0x0f61, 0xe15a, + 0xb74d, 0x96af, 0x83bd, 0x80ec, 0x8e9a, 0xaaff, 0xd26d, 0xffc5, + 0x2d24, 0x54a8, 0x712f, 0x7f05, 0x7c5f, 0x6994, 0x4914, 0x1f19, + 0xf115, 0xc500, 0xa093, 0x8889, 0x8001, 0x8816, 0x9fbb, 0xc3df, + 0xefd1, 0x1ddc, 0x4808, 0x68da, 0x7c10, 0x7f2c, 0x71c6, 0x559c, + 0x2e55, 0x010a, 0xd39e, 0xabf4, 0x8f32, 0x8115, 0x8371, 0x95f7, + 0xb641, 0xe01e, 0x0e1d, 0x3a48, 0x5ee2, 0x772c, 0x7ffd, 0x7832, + 0x60cd, 0x3cd8, 0x10fd, 0xe2ee, 0xb8a4, 0x979e, 0x8423, 0x80bd, + 0x8ddb, 0xa9ca, 0xd0ea, 0xfe26, 0x2b9f, 0x536f, 0x706b, 0x7ed0, + 0x7cbf, 0x6a7c, 0x4a68, 0x20ab, 0xf2b2, 0xc672, 0xa1aa, 0x8921, + 0x8006, 0x8787, 0x9eab, 0xc272, 0xee36, 0x1c48, 0x46af, 0x67ea, + 0x7ba8, 0x7f59, 0x7282, 0x56cf, 0x2fd7, 0x02aa, 0xd525, 0xad2f, + 0x8ff9, 0x814d, 0x8314, 0x9511, 0xb4ef, 0xde8c, 0x0c80, 0x38d5, + 0x5dc9, 0x7692, 0x7ff6, 0x78bf, 0x61db, 0x3e44, 0x1298, 0xe483, + 0xb9ff, 0x9890, 0x848f, 0x8093, 0x8d22, 0xa899, 0xcf68, 0xfc87, + 0x2a17, 0x5232, 0x6fa2, 0x7e95, 0x7d19, 0x6b61, 0x4bb8, 0x223c, + 0xf44f, 0xc7e6, 0xa2c5, 0x89bd, 0x8010, 0x86fd, 0x9d9f, 0xc107, + 0xec9b, 0x1ab2, 0x4553, 0x66f5, 0x7b3a, 0x7f80, 0x7339, 0x57fe, + 0x3157, 0x0449, 0xd6ad, 0xae6d, 0x90c4, 0x818b, 0x82bc, 0x942f, + 0xb3a0, 0xdcfc, 0x0ae2, 0x375f, 0x5cad, 0x75f3, 0x7fe9, 0x7946, + 0x62e5, 0x3fae, 0x1433, 0xe619, 0xbb5c, 0x9987, 0x84ff, 0x806f, + 0x8c6d, 0xa76b, 0xcde9, 0xfae7, 0x288e, 0x50f2, 0x6ed5, 0x7e54, + 0x7d6e, 0x6c41, 0x4d06, 0x23cc, 0xf5ed, 0xc95c, 0xa3e3, 0x8a5f, + 0x801f, 0x8678, 0x9c98, 0xbf9e, 0xeb00, 0x191b, 0x43f5, 0x65fc, + 0x7ac7, 0x7fa2, 0x73ec, 0x592a, 0x32d6, 0x05e8, 0xd837, 0xafaf, + 0x9194, 0x81ce, 0x8269, 0x9351, 0xb255, 0xdb6d, 0x0944, 0x35e8, + 0x5b8c, 0x754f, 0x7fd8, 0x79c8, 0x63eb, 0x4115, 0x15cc, 0xe7b1, + 0xbcbc, 0x9a82, 0x8575, 0x804f, 0x8bbd, 0xa641, 0xcc6c, 0xf948, + 0x2703, 0x4faf, 0x6e03, 0x7e0f, 0x7dbf, 0x6d1c, 0x4e50, 0x255a, + 0xf78b, 0xcad5, 0xa505, 0x8b05, 0x8033, 0x85f8, 0x9b94, 0xbe39, + 0xe967, 0x1783, 0x4293, 0x64ff, 0x7a4f, 0x7fbf, 0x749a, 0x5a52, + 0x3452, 0x0787, 0xd9c3, 0xb0f4, 0x9268, 0x8216, 0x821b, 0x9278, + 0xb10c, 0xd9e0, 0x07a5, 0x346e, 0x5a68, 0x74a6, 0x7fc0, 0x7a46, + 0x64ec, 0x4279, 0x1765, 0xe949, 0xbe1f, 0x9b81, 0x85ef, 0x8035, + 0x8b11, 0xa51b, 0xcaf1, 0xf7aa, 0x2577, 0x4e68, 0x6d2c, 0x7dc4, + 0x7e0a, 0x6df3, 0x4f97, 0x26e6, 0xf92a, 0xcc50, 0xa62c, 0x8bb0, + 0x804d, 0x857d, 0x9a95, 0xbcd6, 0xe7cf, 0x15ea, 0x412f, 0x63fe, + 0x79d2, 0x7fd6, 0x7543, 0x5b77, 0x35cc, 0x0925, 0xdb50, 0xb23d, + 0x9341, 0x8263, 0x81d3, 0x91a3, 0xafc7, 0xd854, 0x0606, 0x32f2, + 0x5940, 0x73f9, 0x7fa4, 0x7abe, 0x65ea, 0x43db, 0x18fd, 0xeae2, + 0xbf84, 0x9c85, 0x866f, 0x8020, 0x8a6b, 0xa3f8, 0xc978, 0xf60b, + 0x23e9, 0x4d1e, 0x6c51, 0x7d74, 0x7e4f, 0x6ec5, 0x50db, 0x2871, + 0xfac9, 0xcdcd, 0xa755, 0x8c60, 0x806c, 0x8508, 0x9999, 0xbb75, + 0xe637, 0x1451, 0x3fc8, 0x62f8, 0x7950, 0x7fe8, 0x75e7, 0x5c98, + 0x3744, 0x0ac4, 0xdcdf, 0xb388, 0x941e, 0x82b5, 0x8190, 0x90d3, + 0xae85, 0xd6ca, 0x0467, 0x3173, 0x5814, 0x7347, 0x7f82, 0x7b31, + 0x66e3, 0x453a, 0x1a94, 0xec7d, 0xc0ec, 0x9d8c, 0x86f3, 0x8011, + 0x89c9, 0xa2d9, 0xc801, 0xf46d, 0x2259, 0x4bd1, 0x6b71, 0x7d1f, + 0x7e90, 0x6f93, 0x521b, 0x29fb, 0xfc68, 0xcf4c, 0xa883, 0x8d14, + 0x8090, 0x8497, 0x98a2, 0xba18, 0xe4a1, 0x12b6, 0x3e5f, 0x61ef, + 0x78c9, 0x7ff5, 0x7686, 0x5db5, 0x38b9, 0x0c61, 0xde6f, 0xb4d7, + 0x9500, 0x830d, 0x8152, 0x9007, 0xad46, 0xd541, 0x02c8, 0x2ff3, + 0x56e5, 0x7290, 0x7f5c, 0x7ba0, 0x67d8, 0x4696, 0x1c2a, 0xee17, + 0xc257, 0x9e97, 0x877d, 0x8006, 0x892c, 0xa1be, 0xc68d, 0xf2d0, + 0x20c8, 0x4a81, 0x6a8d, 0x7cc5, 0x7ecc, 0x705d, 0x5358, 0x2b82, + 0xfe08, 0xd0ce, 0xa9b4, 0x8dce, 0x80ba, 0x842b, 0x97af, 0xb8bd, + 0xe30b, 0x111b, 0x3cf3, 0x60e1, 0x783d, 0x7ffd, 0x7721, 0x5ece, + 0x3a2d, 0x0dff, 0xe000, 0xb629, 0x95e6, 0x836a, 0x8119, 0x8f41, + 0xac0b, 0xd3bb, 0x0129, 0x2e71, 0x55b2, 0x71d4, 0x7f2f, 0x7c09, + 0x68c9, 0x47ef, 0x1dbf, 0xefb3, 0xc3c4, 0x9fa7, 0x880b, 0x8001, + 0x8894, 0xa0a7, 0xc51b, 0xf133, 0x1f36, 0x492d, 0x69a5, 0x7c66, + 0x7f02, 0x7121, 0x5492, 0x2d08, 0xffa7, 0xd251, 0xaae8, 0x8e8b, + 0x80e9, 0x83c5, 0x96c1, 0xb766, 0xe177, 0x0f7f, 0x3b84, 0x5fd0, + 0x77ac, 0x7fff, 0x77b6, 0x5fe3, 0x3b9d, 0x0f9b, 0xe193, 0xb77d, + 0x96d1, 0x83cc, 0x80e5, 0x8e7e, 0xaad3, 0xd236, 0xff8a, 0x2ced, + 0x547c, 0x7114, 0x7efe, 0x7c6d, 0x69b5, 0x4945, 0x1f52, 0xf150, + 0xc534, 0xa0ba, 0x889e, 0x8001, 0x8801, 0x9f94, 0xc3ab, 0xef97, + 0x1da3, 0x47d7, 0x68b8, 0x7c02, 0x7f33, 0x71e1, 0x55c8, 0x2e8c, + 0x0145, 0xd3d6, 0xac20, 0x8f4e, 0x811c, 0x8363, 0x95d6, 0xb611, + 0xdfe5, 0x0de2, 0x3a13, 0x5eba, 0x7716, 0x7ffd, 0x7847, 0x60f4, + 0x3d0c, 0x1137, 0xe327, 0xb8d5, 0x97c0, 0x8432, 0x80b7, 0x8dc1, + 0xa99f, 0xd0b3, 0xfdeb, 0x2b67, 0x5342, 0x704f, 0x7ec8, 0x7ccc, + 0x6a9d, 0x4a98, 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0x9da0, 0xc108, 0xec9c, 0x1ab4, 0x4555 +}; + +float32_t transform_fft_f32_inputs[TRANSFORM_MAX_FFT_LEN * 2] = +{ + 43.0264275639, -17.0525215570, -94.8488973910, -8.1924989580, 7.2830326091, 66.8368719314, 33.9778190671, 117.8652289772, + -129.6077797465, -14.6420815368, 18.0239223278, 20.6760530292, 55.0375037651, 1.8674609862, -85.6534302408, -33.5750364909, + 29.2110949614, 110.4727049460, -94.1914619387, -1.4084169343, 83.5181653041, 47.3073514127, -13.3420621181, 30.3389699104, + 12.1188124277, 100.9730921941, -114.0146362390, -77.5823200409, 37.2019034618, 40.0026301128, -58.3387276630, -34.9472398600, + -5.1169678311, -87.7660091118, -150.5888601131, 56.0349370503, 50.2168884079, -74.2313236767, 22.3648603560, -6.8676387051, + 74.8957303680, -90.1292012823, -55.1436241586, -66.6732976100, -6.7918147615, 7.7612697081, 35.7892605979, -20.0470508830, + 41.8369017546, -143.7378056984, -41.9127158600, -108.3531841158, -57.1917422289, -124.2808828105, 38.9316388820, -77.9212517405, + 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+/*--------------------------------------------------------------------------------*/ +/* FFT Lengths */ +/*--------------------------------------------------------------------------------*/ + +/* + To change test parameter values add/remove values inside CURLY and update + the preceeding parameter to reflect the number of values inside CURLY. +*/ + +ARR_DESC_DEFINE(uint16_t, + transform_radix2_fftlens, + 7, + CURLY( + 16, 32, 64, 128, 256, + 512, 1024/*, 2048 , 4096 */)); + +ARR_DESC_DEFINE(uint16_t, + transform_radix4_fftlens, + 4, + CURLY( + 16, 64, 256, 1024/* , 4096 */)); + +ARR_DESC_DEFINE(uint16_t, + transform_rfft_fftlens, + 6, + CURLY( + 32, 64, 128, 256, + 512, 1024/*, 2048 , 4096, 8192*/)); + +ARR_DESC_DEFINE(uint16_t, + transform_dct_fftlens, + 3, + CURLY( + 128, 512, 2048/*, 8192*/)); + +ARR_DESC_DEFINE(uint16_t, + transform_rfft_fast_fftlens, + 7, + CURLY( + 32, 64, 128, 256, + 512, 1024, 2048)); + +/*--------------------------------------------------------------------------------*/ +/* CFFT_F32 Structs */ +/*--------------------------------------------------------------------------------*/ + +/* Uses radix2 lengths */ +ARR_DESC_DEFINE(const arm_cfft_instance_f32 *, + transform_cfft_f32_structs, + 5, + CURLY( + &arm_cfft_sR_f32_len16, + &arm_cfft_sR_f32_len32, + &arm_cfft_sR_f32_len64, + &arm_cfft_sR_f32_len128, + &arm_cfft_sR_f32_len256/*, + &arm_cfft_sR_f32_len512, */ + /* &arm_cfft_sR_f32_len1024, */ + /* &arm_cfft_sR_f32_len2048, */ + /* &arm_cfft_sR_f32_len4096 */ + )); + +/*--------------------------------------------------------------------------------*/ +/* CFFT_Q31 Structs */ +/*--------------------------------------------------------------------------------*/ + +/* Uses radix2 lengths */ +ARR_DESC_DEFINE(const arm_cfft_instance_q31 *, + transform_cfft_q31_structs, + 5, + CURLY( + &arm_cfft_sR_q31_len16, + &arm_cfft_sR_q31_len32, + &arm_cfft_sR_q31_len64, + &arm_cfft_sR_q31_len128, + &arm_cfft_sR_q31_len256/*, + &arm_cfft_sR_q31_len512, */ + /* &arm_cfft_sR_q31_len1024, */ + /* &arm_cfft_sR_q31_len2048, */ + /* &arm_cfft_sR_q31_len4096 */ + )); + +/*--------------------------------------------------------------------------------*/ +/* CFFT_q15 Structs */ +/*--------------------------------------------------------------------------------*/ + +/* Uses radix2 lengths */ +ARR_DESC_DEFINE(const arm_cfft_instance_q15 *, + transform_cfft_q15_structs, + 5, + CURLY( + &arm_cfft_sR_q15_len16, + &arm_cfft_sR_q15_len32, + &arm_cfft_sR_q15_len64, + &arm_cfft_sR_q15_len128, + &arm_cfft_sR_q15_len256/*, + &arm_cfft_sR_q15_len512, */ + /* &arm_cfft_sR_q15_len1024, */ + /* &arm_cfft_sR_q15_len2048, */ + /* &arm_cfft_sR_q15_len4096 */ + )); diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt new file mode 100644 index 0000000..eeb9c59 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt @@ -0,0 +1,163 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt new file mode 100644 index 0000000..4438b2e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt new file mode 100644 index 0000000..cb9fd3d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt new file mode 100644 index 0000000..6812151 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt new file mode 100644 index 0000000..a2d1052 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/HowTo.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/HowTo.txt new file mode 100644 index 0000000..865ac15 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/HowTo.txt @@ -0,0 +1,29 @@ + +Used board: + MPS2+. + +Used BIOS: + mbb_v121.ebf ; use this for ULINKpro + mbb_v220.ebf ; CMSIS-DAP + +Used Images: + AN382\an382_v3.txt ; Cortex-M0 + AN385\an385_v3.txt ; Cortex-M3 + AN386\an386_v3.txt ; Cortex-M4 + AN500\an500_v1.txt ; Cortex-M7 + AN505\an505_v2.txt ; Cortex-M33 (IoT Kit) + AN519\an519_v1.txt ; Cortex-M23 (IoT Kit) + +Used Debugger: + IoT Kit: + ULINKpro, JTAG, 25MHz, HW Reset + other: + ULINKpro, JTAG, 25MHz, Autodetect + +Memory Settings: + IoT Kit: + ROM: 0x10000000 + RAM: 0x38000000 + other: + ROM: 0x00000000 + RAM: 0x20000000 \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo.txt b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo.txt new file mode 100644 index 0000000..39147ab --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/HowTo.txt @@ -0,0 +1,144 @@ +HowTo DSP_Lib_TestSuite 16.12.2016 +======================================= + +This file describes the folder structure, content, prerequisites and instructions to validate the +build of the CMSIS-DSP library. This is done by processing input data sets using the DSP Library +functions executing on a target simulator or hardware. The output data sets are then compared +with the reference data set produced by unoptimized DSP functions and a Signal to Noise Ratio (SNR) +is computed. If the SNR is below a defined threshold the test is considered "passed". + + +Folder structure +---------------- + .\DSP_Lib_TestSuite Batch files for building the reference libraries and running the tests. + .\DSP_Lib_TestSuite\Common + .\DSP_Lib_TestSuite\Common\inc DSP_Lib test include files + .\DSP_Lib_TestSuite\Common\JTest JTEST Test Framework + INI files for uVision + .\DSP_Lib_TestSuite\Common\platform ARM/GCC device startup/system files + .\DSP_Lib_TestSuite\Common\src DSP_Lib test source files + .\DSP_Lib_TestSuite\DspLibTest_FVP ARM/GCC DSP_Lib test projects for Fixed Virtual Platforms + .\DSP_Lib_TestSuite\DspLibTest_MPS2 ARM/GCC DSP_Lib test projects for MPS2 + .\DSP_Lib_TestSuite\DspLibTest_Simulator ARM/GCC DSP_Lib test projects for uVision simulator + .\DSP_Lib_TestSuite\RefLibs ARM/GCC DSP_Lib reference libraries (and projects) + + + +Prerequisites +-------------- + - Python (running on Windows). Tested with ActivePython 2.7.8.10. + - Keil MDK-ARM (tested with MDK-ARM 5.22: http://www2.keil.com/mdk5) + - ULINKpro debug adapter (http://www2.keil.com/mdk5/ulink) + - MPS2 (Cortex-M Prototyping System:https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php) + - CMSIS 5.0.0 (https://github.com/ARM-software/CMSIS_5/releases/tag/5.0.0) + + +Setup +------ + - Copy DSP_Lib_TestSuite to the CMSIS installation/pack folder. + ... + .\Keil_v5\ARM\PACK\ARM\CMSIS\DSP_Lib + .\Keil_v5\ARM\PACK\ARM\CMSIS\DSP_Lib_TestSuite <- location of DSP_Lib_TestSuite + .\Keil_v5\ARM\PACK\ARM\CMSIS\Include + ... + + - remove 'read-only' tag from folder ./CMSIS/Lib + (required for rebuild of the DSP_Lib libraries) + + - open a Windows command window in folder .\CMSIS\DSP_Lib_TestSuite. + + + +How to run the tests +--------------------- + +a) build the DSP_Lib libraries: + - batch file: buildDspLibs.bat + Note: only require if the DSP_Lib source code got updated or the desired configuration is missing + buildDspLibs.bat overwrites the prebuild libraries in .\CMSIS\Lib. + Log files of the build process are generated in folder .\CMSIS\DSP_Lib/[ARM|GCC] + - run: buildDspLibs.bat in a Windows command window in folder ./CMSIS/DSP_Lib_TestSuite + buildDspLibs ARM -> builds the ARMCC libraries + buildDspLibs GCC -> builds the GCC libraries + +b) build the reference libraries: + - batch file: buildRefLibs.bat + + Log files of the build process are generated in folder .\CMSIS\DSP_Lib_TestSuite\RefLibs/[ARM|GCC] + - run: buildRefLibs.bat in a Windows command window in folder .\CMSIS\DSP_Lib_TestSuite + buildRefLibs ARM -> builds the ARMCC reference libraries + buildRefLibs GCC -> builds the GCC reference libraries + +c) running an individual test using uVision (MDK-ARM): + - batch file: runTest.bat + - run: runTest.bat in a Windows command window in folder .\CMSIS\DSP_Lib_TestSuite + runTest -> prints usage information + e.g. runTest ARM cortexM4lf Simulator -> runs the test for toolchain ARM, Cortex-M4 littel endian with FPU, uVision Simulator. + + Tests running on MPS2 requires additional steps to setup. See section 'MPS2'. + +d) parsing the test output log file + - script: parseLog.py + - run: parseLog.py python script in a Windows command window in folder .\CMSIS\DSP_Lib_TestSuite + command line options should match the invocation of the runTest executed before. + e.g: runTest ARM cortexM4lf Simulator -> python parseLog.py ARM cortexM4lf Simulator + + - check the test log + depending on your test parameters change into the required folder + .\DSP_Lib_TestSuite\DspLibTest_[FVP|MPS2|Simulator]\[ARM|GCC]\Logs + the folder will contain the following files (e.g. for a 'runTest') : + DspLibTest_Simulator.log raw result of the last test run. + DspLibTest_Simulator_cortexM4lf.log raw result of a cortexM4lf test run + DspLibTest_Simulator_cortexM4lf_build.log build result of cortexM4lf test + DspLibTest_Simulator_cortexM4lf_parsed.log parsed log of raw result of a cortexM4lf test run + DspLibTest_Simulator_cortexM4lf_time.log log how long the test took (some tests e.g. M0 take really a long time!). + 'runTest' produces files of the format: DspLibTest__... + + +Differences between the tests for FVP, MPS2, Simulator +------------------------------------------------------ + - all tests are identical except for: + 'Simulator' uses uVision with uVision simulator and generates also code coverage information + can be used for little/big endian tests + ! do not use 'Simulator' for M7 with FPU -> no uVision simulation available. + ! do not use 'Simulator' for ARMv8-M devices -> no uVision simulation available. + 'MPS2' uses uVision with ULINKpro debugger and MPS2. No code coverage information is generated. + can be used for little endian only (because of the lack of MPS2 FPGA images). + 'FVP' uses uVision with Models debugger. No code coverage information is generated. + can be used for little/big endian tests. + ! config files must be prepared. + ! uVision target for big endianess are not yet prepared. + + +Setup 'MPS2' +------------- + - load the appropriate FPGA image to the MPS2 board matching the CPU of the test builds prior to running the test + - check if ULINKpro can connect with the configured debug connection (JTAG or SWD) as this must + match the protocol implemented in the FPGA image. + + +How to select tests for "run all tests" +---------------------------------------- + - edit .\CMSIS\DSP_Lib_TestSuite\Common\src\all_tests.c + comment out all unwanted test groups. + e.g. // JTEST_GROUP_CALL(complex_math_tests); + + - edit .\CMSIS\DSP_Lib_TestSuite\Common\src\/_group.c + comment out all unwanted sub test groups. + e.g. file .\DSP_Lib_TestSuite\Common\src\basic_math_tests\basic_math_test_group.c -> // JTEST_GROUP_CALL(abs_tests); + + - edit .\CMSIS\DSP_Lib_TestSuite\Common\src\/_tests.c + comment out all unwanted tests. + e.g. file .\DSP_Lib_TestSuite\Common\src\basic_math_tests\abs_tests.c -> // JTEST_TEST_CALL(arm_abs_f32_test); + + +Notes +----- + - How to use ARM Clang (ARM Compiler 6): + in uVision 'Options for Target' tab you can select which compiler to use + by default uVision uses ARMCC V5 for Cortex-M devices and ARMCLANG V6 only for ARMv8M. + Only ARMv8M cores have been tested using ARMCLANG + + - test data used for the tests is used as provided by DSP Concepts. + + - some tests run for a very long time before they finish. This is expected + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/inc/ref.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/inc/ref.h new file mode 100644 index 0000000..4ab5c3c --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/inc/ref.h @@ -0,0 +1,1396 @@ + +#ifndef _REF_H +#define _REF_H + +#include +#include +#include "arm_math.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ +// typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ +// typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ +// typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ +// typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ +// typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ +// typedef double float64_t; + + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + REF_Q7 = 0, + REF_Q15, + REF_Q31, + REF_F32, + } dataType; + + +#define FLT_MAX 3.40282347e+38F +#define DBL_MAX 1.79769313486231571e+308 + +#define FLT_MIN 1.175494351e-38F +#define DBL_MIN 2.22507385850720138e-308 + +#define SCHAR_MIN (-128) + /* mimimum value for an object of type signed char */ +#define SCHAR_MAX 127 + /* maximum value for an object of type signed char */ +#define UCHAR_MAX 255 + /* maximum value for an object of type unsigned char */ +#define SHRT_MIN (-0x8000) + /* minimum value for an object of type short int */ +#define SHRT_MAX 0x7fff + /* maximum value for an object of type short int */ +#define USHRT_MAX 65535 + /* maximum value for an object of type unsigned short int */ +#define INT_MIN (~0x7fffffff) /* -2147483648 and 0x80000000 are unsigned */ + /* minimum value for an object of type int */ +#define INT_MAX 0x7fffffff + /* maximum value for an object of type int */ +#define UINT_MAX 0xffffffffU + /* maximum value for an object of type unsigned int */ +#define LONG_MIN (~0x7fffffffL) + /* minimum value for an object of type long int */ +#define LONG_MAX 0x7fffffffL + /* maximum value for an object of type long int */ +#define ULONG_MAX 0xffffffffUL + /* maximum value for an object of type unsigned long int */ + + /* + * Ref Lib Global Variables + */ +extern float32_t scratchArray[]; +extern arm_cfft_instance_f32 ref_cfft_sR_f32_len8192; + + /* + * Ref Lib Functions + */ + + /* + * Helper Functions + */ +q31_t ref_sat_n(q31_t num, uint32_t bits); + +q31_t ref_sat_q31(q63_t num); + +q15_t ref_sat_q15(q31_t num); + +q7_t ref_sat_q7(q15_t num); + +float32_t ref_pow(float32_t a, uint32_t b); + +extern float32_t tempMatrixArray[]; + +float32_t ref_detrm(float32_t *pSrc, float32_t *temp, uint32_t size); + +void ref_cofact(float32_t *pSrc, float32_t *pDst, float32_t *temp, uint32_t size); + +float64_t ref_detrm64(float64_t *pSrc, float64_t *temp, uint32_t size); + +void ref_cofact64(float64_t *pSrc, float64_t *pDst, float64_t *temp, uint32_t size); + + /* + * Basic Math Functions + */ +void ref_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + +void ref_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + +void ref_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + +void ref_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + +void ref_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + +void ref_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + +void ref_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + +void ref_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + +void ref_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + +void ref_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + +void ref_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + +void ref_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + +void ref_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + +void ref_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + +void ref_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + +void ref_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + +void ref_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + +void ref_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + +void ref_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + +void ref_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + +void ref_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + +void ref_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + +void ref_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + +void ref_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + +void ref_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + +void ref_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + +void ref_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /* + * Complex Math Functions + */ +void ref_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + +void ref_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + +void ref_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + +void ref_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + +void ref_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + +void ref_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + +void ref_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + +void ref_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + +void ref_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + +void ref_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /* + * Controller Functions + */ +void ref_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + +void ref_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + +float32_t ref_pid_f32( + arm_pid_instance_f32 * S, + float32_t in); + +q31_t ref_pid_q31( + arm_pid_instance_q31 * S, + q31_t in); + +q15_t ref_pid_q15( + arm_pid_instance_q15 * S, + q15_t in); + + /* + * Fast Math Functions + */ +#define ref_sin_f32(a) sinf(a) + +q31_t ref_sin_q31(q31_t x); + +q15_t ref_sin_q15(q15_t x); + +#define ref_cos_f32(a) cosf(a) + +q31_t ref_cos_q31(q31_t x); + +q15_t ref_cos_q15(q15_t x); + +arm_status ref_sqrt_q31(q31_t in, q31_t * pOut); + +arm_status ref_sqrt_q15(q15_t in, q15_t * pOut); + + /* + * Filtering Functions + */ +void ref_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + +arm_status ref_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +void ref_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + +void ref_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + +arm_status ref_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +arm_status ref_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +void ref_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + +#define ref_conv_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + pScratch1, pScratch2) \ + ref_conv_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +void ref_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + +void ref_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + +arm_status ref_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +#define ref_conv_partial_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + firstIndex, numPoints, \ + pScratch1, pScratch2) \ + ref_conv_partial_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + firstIndex, numPoints) + +arm_status ref_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +arm_status ref_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + +void ref_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + +#define ref_conv_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + pScratch1, pScratch2) \ + ref_conv_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +arm_status ref_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + +#define ref_conv_partial_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + firstIndex, numPoints, \ + pScratch1, pScratch2) \ + ref_conv_partial_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + firstIndex, numPoints) + +void ref_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + +void ref_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + +void ref_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + +void ref_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + +#define ref_correlate_opt_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + pScratch1) \ + ref_correlate_q15(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +void ref_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + +void ref_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + +void ref_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + +#define ref_correlate_opt_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst, \ + pScratch1, pScratch2) \ + ref_correlate_q7(pSrcA, srcALen, pSrcB, srcBLen, pDst) + +void ref_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + +void ref_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + +void ref_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + +void ref_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t *pSrc, + q7_t *pDst, + q7_t *pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + +void ref_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + +void ref_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + +void ref_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + +void ref_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + +void ref_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + +void ref_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + +void ref_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /* + * Matrix Functions + */ +arm_status ref_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + +arm_status ref_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + +arm_status ref_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_inverse_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst); + +arm_status ref_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + +/* Alias for testing purposes*/ +#define ref_mat_mult_fast_q31 ref_mat_mult_q31 + +arm_status ref_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + +/* Alias for testing purposes*/ +#define ref_mat_mult_fast_q15 ref_mat_mult_q15 + +arm_status ref_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scale, + int32_t shift, + arm_matrix_instance_q31 * pDst); + +arm_status ref_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scale, + int32_t shift, + arm_matrix_instance_q15 * pDst); + +arm_status ref_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + +arm_status ref_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + +arm_status ref_mat_trans_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst); + +arm_status ref_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + +arm_status ref_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + +arm_status ref_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + +arm_status ref_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + +arm_status ref_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /* + * Statistics Functions + */ +void ref_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +void ref_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +void ref_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +void ref_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +void ref_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +void ref_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +void ref_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + +void ref_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + +void ref_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +void ref_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +void ref_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +void ref_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +void ref_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +void ref_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + +void ref_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + +void ref_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +void ref_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +void ref_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +void ref_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + +void ref_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +void ref_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +void ref_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + +void ref_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +void ref_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +void ref_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /* + * Support Functions + */ +void ref_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + +void ref_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +void ref_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + +void ref_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + +void ref_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +void ref_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_q63_to_float( + q63_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +void ref_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +void ref_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void ref_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /* + * Transform Functions + */ +void ref_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void ref_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void ref_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void ref_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + +void ref_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + +void ref_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + +void ref_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + +void ref_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +void ref_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + +void ref_rfft_f32( + arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + +void ref_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + +void ref_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + +void ref_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + +void ref_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + +void ref_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + +void ref_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /* + * Intrinsics + */ +q31_t ref__QADD8(q31_t x, q31_t y); +q31_t ref__QSUB8(q31_t x, q31_t y); +q31_t ref__QADD16(q31_t x, q31_t y); +q31_t ref__SHADD16(q31_t x, q31_t y); +q31_t ref__QSUB16(q31_t x, q31_t y); +q31_t ref__SHSUB16(q31_t x, q31_t y); +q31_t ref__QASX(q31_t x, q31_t y); +q31_t ref__SHASX(q31_t x, q31_t y); +q31_t ref__QSAX(q31_t x, q31_t y); +q31_t ref__SHSAX(q31_t x, q31_t y); +q31_t ref__SMUSDX(q31_t x, q31_t y); +q31_t ref__SMUADX(q31_t x, q31_t y); +q31_t ref__QADD(q31_t x, q31_t y); +q31_t ref__QSUB(q31_t x, q31_t y); +q31_t ref__SMLAD(q31_t x, q31_t y, q31_t sum); +q31_t ref__SMLADX(q31_t x, q31_t y, q31_t sum); +q31_t ref__SMLSDX(q31_t x, q31_t y, q31_t sum); +q63_t ref__SMLALD(q31_t x, q31_t y, q63_t sum); +q63_t ref__SMLALDX(q31_t x, q31_t y, q63_t sum); +q31_t ref__SMUAD(q31_t x, q31_t y); +q31_t ref__SMUSD(q31_t x, q31_t y); +q31_t ref__SXTB16(q31_t x); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.c new file mode 100644 index 0000000..baca23f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.c @@ -0,0 +1,53 @@ +#include "ref.h" + +void ref_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 14; //16.48 + } + *result = sum; +} + +void ref_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t i; + q63_t sum = 0.0f; + + for(i=0;i> 32; + temp = temp << 1; + pDst[i] = ref_sat_q31(temp); + } +} + +void ref_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + q31_t temp; + + for(i=0;i> 15; //this comment is for JD, this is specifically 15 and not 16 like the q31 case might imply. This is because CMSIS DSP lib does it this way. No other reason. + pDst[i] = ref_sat_q15(temp); + } +} + +void ref_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + q15_t temp; + + for(i=0;i> 7; + pDst[i] = ref_sat_q7(temp); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.c new file mode 100644 index 0000000..192da1b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.c @@ -0,0 +1,53 @@ +#include "ref.h" + +void ref_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 32; + if (sign) + pDst[i] = temp >> -kShift; + else + pDst[i] = ref_sat_q31( (q63_t)temp << kShift ); + } +} + +void ref_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + int8_t kShift = 15 - shift; /* Shift to apply after scaling */ + + for(i=0;i> kShift); + } +} + +void ref_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + int8_t kShift = 7 - shift; /* Shift to apply after scaling */ + + for(i=0;i> kShift); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.c new file mode 100644 index 0000000..3bc53ad --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.c @@ -0,0 +1,73 @@ +#include "ref.h" + +void ref_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + if (shiftBits < 0) + { + for(i=0;i> -shiftBits; + } + } +} + +void ref_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + if (shiftBits < 0) + { + for(i=0;i> -shiftBits; + } + } +} + +void ref_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + if (shiftBits < 0) + { + for(i=0;i> -shiftBits; + } + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.c new file mode 100644 index 0000000..da89e95 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.c @@ -0,0 +1,57 @@ +#include "ref.h" + +void ref_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 14) - (((q63_t)pSrcA[i+1] * pSrcB[i+1]) >> 14); + sumi += (((q63_t)pSrcA[i] * pSrcB[i+1]) >> 14) + (((q63_t)pSrcA[i+1] * pSrcB[i] ) >> 14); + } + + *realResult = sumr; + *imagResult = sumi; +} + +void ref_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult) +{ + q63_t sumr, sumi; + uint32_t i; + + sumr = 0; + sumi = 0; + + for(i=0;i> 6); + *imagResult = (q31_t)(sumi >> 6); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.c new file mode 100644 index 0000000..b5ac28d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.c @@ -0,0 +1,49 @@ +#include "ref.h" + +void ref_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + + for(i=0;i> 33); + acc1 = (q31_t)(((q63_t)pSrc[i+1] * pSrc[i+1]) >> 33); + out = acc0 + acc1; + *pDst++ = (q31_t)(sqrtf((float)out / 2147483648.0f) * 2147483648.0f); + } +} + +void ref_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + q31_t acc0,acc1; + q15_t out; + + for(i=0;i> 17); + *pDst++ = (q15_t)(sqrtf((float)out / 32768.0f) * 32768.0f); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.c new file mode 100644 index 0000000..aec7bd5 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.c @@ -0,0 +1,46 @@ +#include "ref.h" + +void ref_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + + for(i=0;i> 33); + acc1 = (q31_t)(((q63_t)pSrc[i+1] * pSrc[i+1]) >> 33); + *pDst++ = acc0 + acc1; + } +} + +void ref_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + q31_t acc0,acc1; + + for(i=0;i> 17); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.c new file mode 100644 index 0000000..c7a5409 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.c @@ -0,0 +1,56 @@ +#include "ref.h" + +void ref_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + + for(i=0;i> 33; + mul2 = ((q63_t)pSrcA[i+1] * pSrcB[i+1]) >> 33; + mul3 = ((q63_t)pSrcA[i] * pSrcB[i+1]) >> 33; + mul4 = ((q63_t)pSrcA[i+1] * pSrcB[i]) >> 33; + pDst[i] = mul1 - mul2; + pDst[i+1] = mul3 + mul4; + } +} + +void ref_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t i; + q31_t mul1, mul2, mul3, mul4; + + for(i=0;i> 17; + mul2 = ((q31_t)pSrcA[i+1] * pSrcB[i+1]) >> 17; + mul3 = ((q31_t)pSrcA[i] * pSrcB[i+1]) >> 17; + mul4 = ((q31_t)pSrcA[i+1] * pSrcB[i]) >> 17; + pDst[i] = mul1 - mul2; + pDst[i+1] = mul3 + mul4; + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.c new file mode 100644 index 0000000..dc4928e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.c @@ -0,0 +1,52 @@ +#include "ref.h" + +void ref_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t i; + + for(i=0;i> 32; + tempI = ((q63_t) pSrcCmplx[2*i+1] * pSrcReal[i]) >> 32; + pCmplxDst[2*i+0] = ref_sat_n(tempR, 31) << 1; + pCmplxDst[2*i+1] = ref_sat_n(tempI, 31) << 1; + } +} + +void ref_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t i; + q31_t tempR, tempI; + + for(i=0;i> 15; + tempI = ((q31_t) pSrcCmplx[2*i+1] * pSrcReal[i]) >> 15; + pCmplxDst[2*i+0] = ref_sat_q15(tempR); + pCmplxDst[2*i+1] = ref_sat_q15(tempI); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.c new file mode 100644 index 0000000..51aa633 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.c @@ -0,0 +1,97 @@ +#include "ref.h" + +float32_t ref_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) +{ + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = S->state[2] + S->A0 * in + S->A1 * S->state[0] + S->A2 * S->state[1]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +q31_t ref_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) +{ + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +q15_t ref_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) +{ + q63_t acc; + q15_t out; + q15_t A1, A2; + +#if defined (ARM_MATH_DSP) + +#ifndef ARM_MATH_BIG_ENDIAN + A2 = S->A1 >> 16; + A1 = (q15_t)S->A1; +#else + A1 = S->A1 >> 16; + A2 = (q15_t)S->A1; +#endif + +#else + + A1 = S->A1; + A2 = S->A2; + +#endif + + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) A1 * S->state[0]; + acc += (q31_t) A2 * S->state[1]; + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = ref_sat_q15(acc >> 15); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.c new file mode 100644 index 0000000..22c91a0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.c @@ -0,0 +1,21 @@ +#include "ref.h" + +void ref_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal) +{ + //theta is given in degrees + *pSinVal = sinf(theta * 6.28318530717959f / 360.0f); + *pCosVal = cosf(theta * 6.28318530717959f / 360.0f); +} + +void ref_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal) +{ + //theta is given in the range [-1,1) to represent [-pi,pi) + *pSinVal = (q31_t)(sinf((float32_t)theta * 3.14159265358979f / 2147483648.0f) * 2147483648.0f); + *pCosVal = (q31_t)(cosf((float32_t)theta * 3.14159265358979f / 2147483648.0f) * 2147483648.0f); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.c new file mode 100644 index 0000000..ab6c98e --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.c @@ -0,0 +1,11 @@ +#include "ref.h" + +q31_t ref_cos_q31(q31_t x) +{ + return (q31_t)(cosf((float32_t)x * 6.28318530717959f / 2147483648.0f) * 2147483648.0f); +} + +q15_t ref_cos_q15(q15_t x) +{ + return (q15_t)(cosf((float32_t)x * 6.28318530717959f / 32768.0f) * 32768.0f); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.c new file mode 100644 index 0000000..3f303a5 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.c @@ -0,0 +1,11 @@ +#include "ref.h" + +q31_t ref_sin_q31(q31_t x) +{ + return (q31_t)(sinf((float32_t)x * 6.28318530717959f / 2147483648.0f) * 2147483648.0f); +} + +q15_t ref_sin_q15(q15_t x) +{ + return (q15_t)(sinf((float32_t)x * 6.28318530717959f / 32768.0f) * 32768.0f); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.c new file mode 100644 index 0000000..9dc34af --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.c @@ -0,0 +1,15 @@ +#include "ref.h" + +arm_status ref_sqrt_q31(q31_t in, q31_t * pOut) +{ + *pOut = (q31_t)(sqrtf((float32_t)in / 2147483648.0f) * 2147483648.0f); + + return ARM_MATH_SUCCESS; +} + +arm_status ref_sqrt_q15(q15_t in, q15_t * pOut) +{ + *pOut = (q15_t)(sqrtf((float32_t)in / 32768.0f) * 32768.0f); + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.c new file mode 100644 index 0000000..1fe7c54 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.c @@ -0,0 +1,713 @@ +#include "ref.h" + +void ref_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn; /* temporary input */ + float32_t d1, d2; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc = (b0 * Xn) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = (b1 * Xn + a1 * acc) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn) + (a2 * acc); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + + +void ref_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc1a, acc1b; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1a, Xn1b; /* temporary input */ + float32_t d1a, d2a, d1b, d2b; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn1a = *pIn++; //Channel a + Xn1b = *pIn++; //Channel b + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1a; + *pState++ = d2a; + *pState++ = d1b; + *pState++ = d2b; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); + +} + +void ref_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + float64_t *pIn = pSrc; /* source pointer */ + float64_t *pOut = pDst; /* destination pointer */ + float64_t *pState = S->pState; /* State pointer */ + float64_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float64_t acc; /* accumulator */ + float64_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float64_t Xn; /* temporary input */ + float64_t d1, d2; /* state variables */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc = (b0 * Xn) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = (b1 * Xn + a1 * acc) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn) + (a2 * acc); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage input is given as the output to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* Simulates the accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t Xn; /* temporary input */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stage--; + + } while (stage > 0U); +} + +void ref_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (q63_t)Xn*b0 + (q63_t)Xn1*b1 + (q63_t)Xn2*b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q63_t acc; /* accumulator */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q31_t *pState = S->pState; /* pState pointer initialization */ + q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q63_t) b0 *Xn; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) b1 *Xn1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t) b2 *Xn2; + /* acc += a1 * y[n-1] */ + acc += (q63_t) a1 *Yn1; + /* acc += a2 * y[n-2] */ + acc += (q63_t) a2 *Yn2; + + /* The result is converted to 1.31 */ + acc = acc >> lShift; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q31_t) acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + + +void ref_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t acc = 0; /* accumulator */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q31_t *pState = S->pState; /* pState pointer initialization */ + q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + mult_32x32_keep32_R(acc, b0, Xn); + multAcc_32x32_keep32_R(acc, b1, Xn1); + multAcc_32x32_keep32_R(acc, b2, Xn2); + multAcc_32x32_keep32_R(acc, a1, Yn1); + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 */ + acc <<= shift; + + /* Every time after the output is computed state should be updated. */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* Store the output in the destination buffer. */ + *pOut++ = acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q31_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (q31_t)b0*Xn + (q31_t)b1*Xn1 + (q31_t)b2*Xn2 + (q31_t)a1*Yn1 + (q31_t)a2*Yn2; + + /* The result is converted to 1.15 */ + acc = ref_sat_q15(acc >> shift); + + /* Every time after the output is computed state should be updated. */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t) acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +void ref_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q63_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (q31_t)b0*Xn + (q31_t)b1*Xn1 + (q31_t)b2*Xn2 + (q31_t)a1*Yn1 + (q31_t)a2*Yn2; + + /* The result is converted to 1.15 */ + acc = ref_sat_q15(acc >> shift); + + /* Every time after the output is computed state should be updated. */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t) acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.c new file mode 100644 index 0000000..dc1b103 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.c @@ -0,0 +1,350 @@ +#include "ref.h" + +void ref_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += pSrcB[i - j] * pSrcA[j]; + } + } + /* Store the output in the destination buffer */ + pDst[i] = sum; + } +} + +arm_status ref_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_f32(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} + +void ref_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q63_t) pSrcA[j] * (pSrcB[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t)(sum >> 31U); + } +} + +void ref_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum = (q31_t) ((((q63_t)sum << 32) + + ((q63_t)pSrcA[j] * pSrcB[i - j])) >> 32); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t)(sum << 1U); + } +} + +arm_status ref_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_q31(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} + +arm_status ref_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_fast_q31(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} + +void ref_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } +} + +arm_status ref_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } + + return ARM_MATH_SUCCESS; +} + +void ref_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum >> 15U; + } +} + +void ref_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q31_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = ref_sat_q15(sum >> 15U); + } +} + +arm_status ref_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_q15(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} + +arm_status ref_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_fast_q15(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} + + +void ref_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* loop counter */ + + /* Loop to calculate output of convolution for output length number of times */ + for (i = 0; i < srcALen + srcBLen - 1; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += (q15_t)pSrcA[j] * pSrcB[i - j]; + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t)ref_sat_q7(sum >> 7); + } +} + +arm_status ref_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + ref_conv_q7(pSrcA,srcALen,pSrcB,srcBLen,pDst); + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.c new file mode 100644 index 0000000..ff1d95b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.c @@ -0,0 +1,513 @@ +#include "ref.h" + +void ref_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + float32_t *pIn1 = pSrcA; /* inputA pointer */ + float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. + * srcB is always made to slide across srcA. + * So srcBLen is always considered as shorter or equal to srcALen + * But CORR(x, y) is reverse of CORR(y, x) + * So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer + * and a variable, inv is set to 1 + * If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs + * If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer + * If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer + * Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. + */ + + /* Calculate the length of the remaining sequence */ + tot = srcALen + srcBLen - 2U; + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + /* Initialise the pointer after zero padding */ + pDst += srcALen - srcBLen; + } + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + srcALen - 1U; + + /* Initialisation of the pointer after zero padding */ + pDst += tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((i - j < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += pIn1[j] * pIn2[-((int32_t)i - j)]; + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } +} + +void ref_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + q31_t *pIn1 = pSrcA; /* inputA pointer */ + q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate correlation for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to correlation equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q31_t)(sum >> 31U); + else + *pDst++ = (q31_t)(sum >> 31U); + } +} + +void ref_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + q31_t *pIn1 = pSrcA; /* inputA pointer */ + q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate correlation for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to correlation equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)])) >> 32); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q31_t)(sum << 1U); + else + *pDst++ = (q31_t)(sum << 1U); + } +} + +void ref_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + q15_t *pIn1 = pSrcA; /* inputA pointer */ + q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t) ref_sat_q15(sum >> 15U); + else + *pDst++ = (q15_t) ref_sat_q15(sum >> 15U); + } +} + +void ref_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + q15_t *pIn1 = pSrcA; /* inputA pointer */ + q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t)(sum >> 15U); + else + *pDst++ = (q15_t)(sum >> 15U); + } +} + +void ref_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ + q15_t *pIn1 = pSrcA; /* inputA pointer */ + q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q31_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t) ref_sat_q15(sum >> 15U); + else + *pDst++ = (q15_t) ref_sat_q15(sum >> 15U); + } +} + +void ref_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + q7_t *pIn1 = pSrcA; /* inputA pointer */ + q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]); + } + } + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q7_t) __SSAT((sum >> 7U), 8U); + else + *pDst++ = (q7_t) __SSAT((sum >> 7U), 8U); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.c new file mode 100644 index 0000000..3e72b87 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.c @@ -0,0 +1,325 @@ +#include "ref.h" + +void ref_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counters */ + float32_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;ipState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counters */ + q63_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;i> 31); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counters */ + q31_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;i> 32); + } + + /* The result is store in the destination buffer. */ + *pDst++ = (q31_t)(acc << 1); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counters */ + q63_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;i> 15); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counters */ + q31_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;i> 15); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *pStateCurnt; /* Points to the current sample of the state */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i; /* Loop counters */ + q31_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + while (blockSize > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + for(i=0;i> 7); + + /* Advance state pointer by 1 for the next sample */ + pState++; + + blockSize--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy data */ + for(i=0;ipState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t sum0; /* Accumulator */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0.0f; + + for(i=0;iM; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Decrement the loop counter */ + blkCnt--; + } + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy numTaps number of values */ + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for(i=0;iM; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 >> 31); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for(i=0;i> 32); + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 << 1); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for(i=0;iM; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = ref_sat_q15(sum0 >> 15); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + +void ref_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt; /* Loop counters */ + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + numTaps - 1U; + + /* Total number of output samples to be computed */ + blkCnt = blockSize / S->M; + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + for(i=0;iM; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = ref_sat_q15(sum0 >> 15); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = numTaps - 1U; + + /* copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} + diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.c new file mode 100644 index 0000000..8abb089 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.c @@ -0,0 +1,291 @@ +#include "ref.h" + +void ref_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + float32_t sum; /* Accumulator */ + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */ + + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + phaseLen - 1; + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + i - 1; + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum += *ptr1++ * *ptr2; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + tapCnt = phaseLen - 1U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} + +void ref_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + + /* Run the below code for Cortex-M0 */ + + q63_t sum; /* Accumulator */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */ + + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + (q31_t)phaseLen - 1; + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + i - 1; + + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Read the coefficient */ + c0 = *(ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the input sample */ + x0 = *ptr1++; + + /* Perform the multiply-accumulate */ + sum += (q63_t) x0 *c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t)(sum >> 31); + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + tapCnt = phaseLen - 1U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} + +void ref_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + q63_t sum; /* Accumulator */ + q15_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + phaseLen - 1; + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + i - 1; + + /* Loop over the polyPhase length */ + tapCnt = (uint32_t)phaseLen; + + while (tapCnt > 0U) + { + /* Read the coefficient */ + c0 = *ptr2; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the input sample */ + x0 = *ptr1++; + + /* Perform the multiply-accumulate */ + sum += (q31_t) x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result after converting to 1.15 format in the destination buffer */ + *pDst++ = ref_sat_q15(sum >> 15); + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = (uint32_t) phaseLen - 1U; + + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } + +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.c new file mode 100644 index 0000000..6466106 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.c @@ -0,0 +1,241 @@ +#include "ref.h" + +void ref_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* temporary state pointer */ + float32_t *pk; /* temporary coefficient pointer */ + float32_t fcurr, fnext, gcurr, gnext; /* temporary variables */ + uint32_t numStages = S->numStages; /* Length of the filter */ + uint32_t blkCnt, stageCnt; /* temporary variables for counts */ + + pState = &S->pState[0]; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Initialize state pointer */ + px = pState; + + /* read g0(n-1) from state buffer */ + gcurr = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext = fcurr + ((*pk) * gcurr); + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext = (fcurr * (*pk++)) + gcurr; + + /* save f0(n) in state buffer */ + *px++ = fcurr; + + /* f1(n) is saved in fcurr + for next stage processing */ + fcurr = fnext; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext = fcurr + ((*pk) * gcurr); + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext = (fcurr * (*pk++)) + gcurr; + + /* f1(n) is saved in fcurr1 + for next stage processing */ + fcurr = fnext; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr; + + blkCnt--; + } +} + +void ref_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* temporary state pointer */ + q31_t *pk; /* temporary coefficient pointer */ + q31_t fcurr, fnext, gcurr, gnext; /* temporary variables */ + uint32_t numStages = S->numStages; /* Length of the filter */ + uint32_t blkCnt, stageCnt; /* temporary variables for counts */ + + pState = &S->pState[0]; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Initialize state pointer */ + px = pState; + + /* read g0(n-1) from state buffer */ + gcurr = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr; + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr; + /* save g1(n) in state buffer */ + *px++ = fcurr; + + /* f1(n) is saved in fcurr1 + for next stage processing */ + fcurr = fnext; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr; + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr; + + /* f1(n) is saved in fcurr1 + for next stage processing */ + fcurr = fnext; + + stageCnt--; + + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr; + + blkCnt--; + + } +} + +void ref_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* temporary state pointer */ + q15_t *pk; /* temporary coefficient pointer */ + q31_t fcurnt, fnext, gcurnt, gnext; /* temporary variables */ + uint32_t numStages = S->numStages; /* Length of the filter */ + uint32_t blkCnt, stageCnt; /* temporary variables for counts */ + + pState = &S->pState[0]; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurnt = *pSrc++; + + /* Initialize coeff pointer */ + pk = (pCoeffs); + + /* Initialize state pointer */ + px = pState; + + /* read g0(n-1) from state buffer */ + gcurnt = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext = ((gcurnt * (*pk)) >> 15U) + fcurnt; + fnext = ref_sat_q15(fnext); + + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext = ((fcurnt * (*pk++)) >> 15U) + gcurnt; + gnext = ref_sat_q15(gnext); + + /* save f0(n) in state buffer */ + *px++ = (q15_t) fcurnt; + + /* f1(n) is saved in fcurnt + for next stage processing */ + fcurnt = fnext; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g1(n-1) from state buffer */ + gcurnt = *px; + + /* save g0(n-1) in state buffer */ + *px++ = (q15_t) gnext; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext = ((gcurnt * (*pk)) >> 15U) + fcurnt; + fnext = ref_sat_q15(fnext); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext = ((fcurnt * (*pk++)) >> 15U) + gcurnt; + gnext = ref_sat_q15(gnext); + + + /* f1(n) is saved in fcurnt + for next stage processing */ + fcurnt = fnext; + + stageCnt--; + + } + + /* y(n) = fN(n) */ + *pDst++ = ref_sat_q15(fcurnt); + + + blkCnt--; + + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.c new file mode 100644 index 0000000..0638313 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.c @@ -0,0 +1,485 @@ +#include "ref.h" + +void ref_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Scratch buffer pointer */ + float32_t *py = pState; /* Temporary pointers for state buffer */ + float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + float32_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + float32_t coeff = *pCoeffs++; /* Read the first coefficient value */ + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, + (int32_t *) pSrc, 1, blockSize); + + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer */ + px = pb; + + /* Working pointer for destination buffer */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = *px++ * coeff; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 1U; + + while (tapCnt > 0U) + { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer */ + px = pb; + + /* Working pointer for destination buffer */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } +} + +void ref_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Scratch buffer pointer */ + q31_t *py = pState; /* Temporary pointers for state buffer */ + q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q31_t *pOut; /* Destination pointer */ + q63_t out; /* Temporary output variable */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Filter order */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t coeff = *pCoeffs++; /* Read the first coefficient value */ + q31_t in; + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, + (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in the destination buffer */ + *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 1U; + + while (tapCnt > 0U) + { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, + blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } + + /* Working output pointer is updated */ + pOut = pDst; + + /* Output is converted into 1.31 format. */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +void ref_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pIn = pSrc; /* Working pointer for input */ + q15_t *pOut = pDst; /* Working pointer for output */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* Temporary pointers for scratch buffer */ + q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q15_t *py = pState; /* Temporary pointers for state buffer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Filter order */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q15_t coeff = *pCoeffs++; /* Read the first coefficient value */ + q31_t *pScr2 = pScratchOut; /* Working pointer for pScratchOut */ + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, delaySize, &readIndex, 1, + pb, pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) * px++ * coeff); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 1U; + + while (tapCnt > 0U) + { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, delaySize, &readIndex, 1, + pb, pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) * px++ * coeff; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ + /* Loop over the blockSize. */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16); + blkCnt--; + } +} + +void ref_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t *pSrc, + q7_t *pDst, + q7_t *pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *px; /* Scratch buffer pointer */ + q7_t *py = pState; /* Temporary pointers for state buffer */ + q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q7_t *pOut = pDst; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Filter order */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q7_t coeff = *pCoeffs++; /* Read the coefficient value */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q31_t in; + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1, + blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb, + (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + /* Loop over the blockSize */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) * px++ * coeff); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 1U; + + while (tapCnt > 0U) + { + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb, + (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + /* Loop over the blockSize */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Decrement the tap loop counter */ + tapCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ + /* Loop over the blockSize. */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.c new file mode 100644 index 0000000..ab37d5f --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.c @@ -0,0 +1,271 @@ +#include "ref.h" + +void ref_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t fcurr, fnext = 0, gcurr, gnext; /* Temporary variables for lattice stages */ + float32_t acc; /* Accumlator */ + uint32_t blkCnt, tapCnt; /* temporary variables for counts */ + float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* number of stages */ + float32_t *pState; /* State pointer */ + float32_t *pStateCurnt; /* State current pointer */ + + blkCnt = blockSize; + pState = &S->pState[0]; + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize state read pointer */ + px1 = pState; + /* Initialize state write pointer */ + px2 = pState; + /* Set accumulator to zero */ + acc = 0.0f; + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Process sample for numStages */ + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = fcurr - (*pk) * gcurr; + gnext = fnext * (*pk++) + gcurr; + + /* Output samples for last taps */ + acc += gnext * (*pv++); + *px2++ = gnext; + fcurr = fnext; + + /* Decrementing loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += fnext * (*pv); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = acc; + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCurnt = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy the data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* number of stages */ + q31_t *pState; /* State pointer */ + q31_t *pStateCurnt; /* State current pointer */ + + blkCnt = blockSize; + pState = &S->pState[0]; + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize state read pointer */ + px1 = pState; + /* Initialize state write pointer */ + px2 = pState; + /* Set accumulator to zero */ + acc = 0; + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = + ref_sat_q31(((q63_t) fcurr - + ((q31_t) (((q63_t) gcurr * (*pk)) >> 31)))); + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = + ref_sat_q31(((q63_t) gcurr + + ((q31_t) (((q63_t) fnext * (*pk++)) >> 31)))); + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q63_t) fnext *(*pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCurnt = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + uint32_t stgCnt; /* Temporary variables for counts */ + q63_t acc; /* Accumlator */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* number of stages */ + q15_t *pState; /* State pointer */ + q15_t *pStateCurnt; /* State current pointer */ + q15_t out; /* Temporary variable for output */ + + blkCnt = blockSize; + pState = &S->pState[0]; + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize state read pointer */ + px1 = pState; + /* Initialize state write pointer */ + px2 = pState; + /* Set accumulator to zero */ + acc = 0; + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - ((gcurr * (*pk)) >> 15); + fnext = ref_sat_q15(fnext); + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = ((fnext * (*pk++)) >> 15) + gcurr; + gnext = ref_sat_q15(gnext); + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) ((fnext * (*pv++))); + + out = ref_sat_q15(acc >> 15); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + /* Points to the start of the state buffer */ + pStateCurnt = &S->pState[0]; + pState = &S->pState[blockSize]; + + stgCnt = numStages; + + /* copy data */ + while (stgCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + stgCnt--; + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.c new file mode 100644 index 0000000..fee99f9 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.c @@ -0,0 +1,695 @@ +#include "ref.h" + +void ref_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, blkCnt; /* Loop counters */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w = 0.0f; /* weight factor */ + + e = 0.0f; + d = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[numTaps - 1U]); + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + sum = 0.0f; + + for(i=0;ipState[i] = pState[i]; + } +} + +void ref_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + d = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[numTaps - 1U]); + + for(blkCnt = blockSize; blkCnt > 0U; blkCnt--) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + sum = 0.0f; + + for(i=0;ienergy = energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + * start of the state buffer. This prepares the state buffer for the + * next function call. */ + for(i=0;ipState[i] = pState[i]; + } +} + +void ref_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t mu = S->mu; /* Adaptive factor */ + q31_t *px; /* Temporary pointer for state */ + q31_t *pb; /* Temporary pointer for coefficient buffer */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t e = 0; /* error of data sample */ + q31_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* temporary input */ + uint32_t uShift = (uint32_t)S->postShift + 1; + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for(blkCnt = blockSize; blkCnt > 0U; blkCnt--) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t)(*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Store the result from accumulator into the destination buffer. */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + *pOut++ = (q31_t)acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t)acc; + + *pErr++ = (q31_t)e; + + /* Weighting factor for the LMS version */ + alpha = (q31_t)(((q63_t)e * mu) >> 31); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t)(((q63_t) alpha * (*px++)) >> 32); + *pb = ref_sat_q31((q63_t)*pb + (coef << 1)); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + } + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Copy (numTaps - 1U) samples */ + tapCnt = numTaps - 1; + + /* Copy the data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t energy; /* Energy of the input */ + q63_t acc; /* Accumulator */ + q31_t e = 0, d = 0; /* error, reference data sample */ + q31_t w = 0, in; /* weight factor and state */ + q31_t x0; /* temporary variable to hold input sample */ + q63_t errorXmu; /* Temporary variables to store error and mu product and reciprocal of energy */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for(blkCnt = blockSize; blkCnt > 0U; blkCnt--) + { + + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy = (q31_t)((((q63_t)energy << 32) - (((q63_t)x0 * x0) << 1)) >> 32) & 0xffffffff; + energy = (q31_t)(((((q63_t)in * in) << 1) + ((q63_t)energy << 32)) >> 32) & 0xffffffff; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t)acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q31_t)acc; + *pErr++ = e; + + /* Calculation of product of (e * mu) */ + errorXmu = (q63_t)e * mu; + + /* Weighting factor for the normalized version */ + w = ref_sat_q31(errorXmu / (energy + DELTA_Q31)); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* coef is in 2.30 format */ + coef = (q31_t)(((q63_t)w * (*px++)) >> 32); + /* get coef in 1.31 format by left shifting */ + *pb = ref_sat_q31((q63_t)*pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState++; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q31_t)energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Loop for (numTaps - 1U) samples copy */ + tapCnt = numTaps - 1; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t mu = S->mu; /* Adaptive factor */ + q15_t *px; /* Temporary pointer for state */ + q15_t *pb; /* Temporary pointer for coefficient buffer */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q15_t e = 0; /* error of data sample */ + q15_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Teporary variable for coefficient */ + q31_t acc_l, acc_h; + int32_t lShift = 15 - (int32_t)S->postShift; /* Post shift */ + int32_t uShift = 32 - lShift; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for(blkCnt = blockSize; blkCnt > 0U; blkCnt--) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t)((q31_t)(*px++) * (*pb++)); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t)acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = ref_sat_q15(acc); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t)acc; + + /* Compute and store error */ + e = *pRef++ - (q15_t)acc; + + *pErr++ = (q15_t)e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q15_t)(((q31_t)e * mu) >> 15); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) ref_sat_q15(coef); + + /* Decrement the loop counter */ + tapCnt--; + } + } + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + start of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Copy (numTaps - 1U) samples */ + tapCnt = numTaps - 1; + + /* Copy the data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} + +void ref_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q31_t energy; /* Energy of the input */ + q63_t acc; /* Accumulator */ + q15_t e = 0, d = 0; /* error, reference data sample */ + q15_t w = 0, in; /* weight factor and state */ + q15_t x0; /* temporary variable to hold input sample */ + q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + //q31_t errorXmu; /* Temporary variables to store error and mu product and reciprocal of energy */ + q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Teporary variable for coefficient */ + q31_t acc_l, acc_h; + int32_t lShift = 15 - (int32_t)S->postShift; /* Post shift */ + int32_t uShift = 32 - lShift; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + for(blkCnt = blockSize; blkCnt > 0U; blkCnt--) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize pCoeffs pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= (((q31_t)x0 * x0) >> 15) & 0xffff; + energy += (((q31_t)in * in) >> 15) & 0xffff; + + /* Set the accumulator to zero */ + acc = 0; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q31_t)*px++ * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = ref_sat_q15(acc); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q15_t) acc; + *pErr++ = e; + +#if 0 + /* Calculation of e * mu value */ + errorXmu = (q31_t) e * mu; + + /* Calculation of (e * mu) /energy value */ + acc = errorXmu / (energy + DELTA_Q15); +#endif + + /* Calculation of 1/energy */ + postShift = arm_recip_q15((q15_t) energy + DELTA_Q15, + &oneByEnergy, S->recipTable); + + /* Calculation of e * mu value */ + errorXmu = (q15_t) (((q31_t) e * mu) >> 15); + + /* Calculation of (e * mu) * (1/energy) value */ + acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift)); + + /* Weighting factor for the normalized version */ + w = ref_sat_q15((q31_t)acc); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop over numTaps number of values */ + tapCnt = numTaps; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = *pb + (((q31_t)w * (*px++)) >> 15); + *pb++ = ref_sat_q15(coef); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q15_t)energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy (numTaps - 1U) data */ + tapCnt = numTaps - 1; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.c new file mode 100644 index 0000000..0174ccf --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.c @@ -0,0 +1,193 @@ +#include "ref.h" + +float32_t ref_detrm(float32_t *pSrc, float32_t *temp, uint32_t size) +{ + float32_t s = 1, det = 0; + int i, j, m, n, c; + + if ( size == 1 ) + { + return ( pSrc[ 0 ] ); + } + else + { + det = 0; + + for ( c = 0;c < size;c++ ) + { + m = 0; + n = 0; + + for ( i = 0;i < size;i++ ) + { + for ( j = 0;j < size;j++ ) + { + temp[ i*size + j ] = 0; + + if ( i != 0 && j != c ) + { + temp[ m*(size-1) + n ] = pSrc[ i*size + j ]; + + if ( n < ( size - 2 ) ) + { + n++; + } + else + { + n = 0; + m++; + } + } + } + } + + det += s * ( pSrc[ c ] * ref_detrm( temp, temp + size*size, size - 1 ) ); + s = -s; + } + } + + return ( det ); +} + + +void ref_cofact(float32_t *pSrc, float32_t *pDst, float32_t *temp, uint32_t size) +{ + int p, q, m, n, i, j; + + if (size == 1) + { + pDst[0] = 1; + return; + } + + for ( q = 0;q < size;q++ ) + { + for ( p = 0;p < size;p++ ) + { + m = 0; + n = 0; + + for ( i = 0;i < size;i++ ) + { + for ( j = 0;j < size;j++ ) + { + temp[ i*size + j ] = 0; + + if ( i != q && j != p ) + { + temp[ m*(size-1) + n ] = pSrc[ i*size + j ]; + + if ( n < ( size - 2 ) ) + { + n++; + } + else + { + n = 0; + m++; + } + } + } + } + + pDst[ q*size + p ] = ref_pow( -1, q + p ) * ref_detrm( temp, temp + (size-1)*(size-1), size - 1 ); + } + } +} + + + +float64_t ref_detrm64(float64_t *pSrc, float64_t *temp, uint32_t size) +{ + float64_t s = 1, det = 0; + int i, j, m, n, c; + + if ( size == 1 ) + { + return ( pSrc[ 0 ] ); + } + else + { + det = 0; + + for ( c = 0;c < size;c++ ) + { + m = 0; + n = 0; + + for ( i = 0;i < size;i++ ) + { + for ( j = 0;j < size;j++ ) + { + temp[ i*size + j ] = 0; + + if ( i != 0 && j != c ) + { + temp[ m*(size-1) + n ] = pSrc[ i*size + j ]; + + if ( n < ( size - 2 ) ) + { + n++; + } + else + { + n = 0; + m++; + } + } + } + } + + det += s * ( pSrc[ c ] * ref_detrm64( temp, temp + size*size, size - 1 ) ); + s = -s; + } + } + + return ( det ); +} + + +void ref_cofact64(float64_t *pSrc, float64_t *pDst, float64_t *temp, uint32_t size) +{ + int p, q, m, n, i, j; + + if (size == 1) + { + pDst[0] = 1; + return; + } + + for ( q = 0;q < size;q++ ) + { + for ( p = 0;p < size;p++ ) + { + m = 0; + n = 0; + + for ( i = 0;i < size;i++ ) + { + for ( j = 0;j < size;j++ ) + { + temp[ i*size + j ] = 0; + + if ( i != q && j != p ) + { + temp[ m*(size-1) + n ] = pSrc[ i*size + j ]; + + if ( n < ( size - 2 ) ) + { + n++; + } + else + { + n = 0; + m++; + } + } + } + } + + pDst[ q*size + p ] = ref_pow( -1, q + p ) * ref_detrm64( temp, temp + (size-1)*(size-1), size - 1 ); + } + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.c new file mode 100644 index 0000000..57ecf1b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.c @@ -0,0 +1,103 @@ +#include "ref.h" + +float32_t scratchArray[8192*2]; + +arm_cfft_instance_f32 ref_cfft_sR_f32_len8192 = { 8192, 0, 0, 0 }; + +q31_t ref_sat_n(q31_t num, uint32_t bits) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (bits - 1); i++) + { + posMax = posMax * 2; + } + + if (num > 0) + { + posMax = (posMax - 1); + + if (num > posMax) + { + num = posMax; + } + } + else + { + negMin = -posMax; + + if (num < negMin) + { + num = negMin; + } + } + return (num); +} + +q31_t ref_sat_q31(q63_t num) +{ + if (num > (q63_t)INT_MAX) + { + return INT_MAX; + } + else if (num < (q63_t)0xffffffff80000000ll) + { + return INT_MIN; + } + else + { + return (q31_t)num; + } +} + +q15_t ref_sat_q15(q31_t num) +{ + if (num > (q31_t)SHRT_MAX) + { + return SHRT_MAX; + } + else if (num < (q31_t)0xffff8000) + { + return SHRT_MIN; + } + else + { + return (q15_t)num; + } +} + +q7_t ref_sat_q7(q15_t num) +{ + if (num > (q15_t)SCHAR_MAX) + { + return SCHAR_MAX; + } + else if (num < (q15_t)0xff80) + { + return SCHAR_MIN; + } + else + { + return (q7_t)num; + } +} + +float32_t ref_pow(float32_t a, uint32_t b) +{ + uint32_t i; + float32_t r = a; + + for(i=1;i> 24) + ((y << 16) >> 24))), 8); + t = ref_sat_n(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = ref_sat_n(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + +} + +q31_t ref__QSUB8(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = ref_sat_n((r - s), 8); + s = ref_sat_n(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = ref_sat_n(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = ref_sat_n(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); + + return sum; +} + +q31_t ref__QADD16(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ref_sat_q15(r + s); + s = (q31_t)ref_sat_q15(((q31_t) ((x >> 16) + (y >> 16)))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + +} + +q31_t ref__SHADD16(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = (r + s) >> 1; + s = ((q31_t) (((x >> 16) + (y >> 16)) >> 1) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + +} + +q31_t ref__QSUB16(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ref_sat_q15(r - s); + s = (q31_t)ref_sat_q15(((q31_t) ((x >> 16) - (y >> 16)))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +q31_t ref__SHSUB16(q31_t x, q31_t y) +{ + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; +} + +q31_t ref__QASX(q31_t x, q31_t y) +{ + q31_t sum = 0; + q31_t xL, xH, yL, yH; + + // extract bottom halfword and sign extend + xL = (q15_t)(x & 0xffff); + // extract bottom halfword and sign extend + yL = (q15_t)(y & 0xffff); + // extract top halfword and sign extend + xH = (q15_t)(x >> 16); + // extract top halfword and sign extend + yH = (q15_t)(y >> 16); + + sum = (((q31_t)ref_sat_q15(xH + yL )) << 16) | + (((q31_t)ref_sat_q15(xL - yH )) & 0xffff); + + return sum; +} + +q31_t ref__SHASX(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = (r - (y >> 16)) / 2; + s = (((x >> 16) + s) << 15); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +q31_t ref__QSAX(q31_t x, q31_t y) +{ + q31_t sum = 0; + q31_t xL, xH, yL, yH; + + // extract bottom halfword and sign extend + xL = (q15_t)(x & 0xffff); + // extract bottom halfword and sign extend + yL = (q15_t)(y & 0xffff); + // extract top halfword and sign extend + xH = (q15_t)(x >> 16); + // extract top halfword and sign extend + yH = (q15_t)(y >> 16); + + sum = (((q31_t)ref_sat_q15(xH - yL )) << 16) | + (((q31_t)ref_sat_q15(xL + yH )) & 0xffff); + + return sum; +} + +q31_t ref__SHSAX(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = (r + (y >> 16)) / 2; + s = (((x >> 16) - s) << 15); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +q31_t ref__SMUSDX(q31_t x, q31_t y) +{ + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - ((q15_t) (x >> 16) * (q15_t) y))); +} + +q31_t ref__SMUADX(q31_t x, q31_t y) +{ + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + ((q15_t) (x >> 16) * (q15_t) y))); +} + +q31_t ref__QADD(q31_t x, q31_t y) +{ + return ref_sat_q31((q63_t) x + y); +} + +q31_t ref__QSUB(q31_t x, q31_t y) +{ + return ref_sat_q31((q63_t) x - y); +} + +q31_t ref__SMLAD(q31_t x, q31_t y, q31_t sum) +{ + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); +} + +q31_t ref__SMLADX(q31_t x, q31_t y, q31_t sum) +{ + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + ((q15_t) x * (q15_t) (y >> 16))); +} + +q31_t ref__SMLSDX(q31_t x, q31_t y, q31_t sum) +{ + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + ((q15_t) x * (q15_t) (y >> 16))); +} + +q63_t ref__SMLALD(q31_t x, q31_t y, q63_t sum) +{ + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); +} + +q63_t ref__SMLALDX(q31_t x, q31_t y, q63_t sum) +{ + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); +} + +q31_t ref__SMUAD(q31_t x, q31_t y) +{ + return (((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + +q31_t ref__SMUSD(q31_t x, q31_t y) +{ + return (-((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + +q31_t ref__SXTB16(q31_t x) +{ + return ((((x << 24) >> 24) & 0x0000FFFF) | (((x << 8) >> 8) & 0xFFFF0000)); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.c new file mode 100644 index 0000000..a6e0067 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.c @@ -0,0 +1,58 @@ +#include "ref.h" + +arm_status ref_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = pSrcA->pData[i] + pSrcB->pData[i]; + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = ref_sat_q31( (q63_t)pSrcA->pData[i] + pSrcB->pData[i]); + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = ref_sat_q15( (q31_t)pSrcA->pData[i] + pSrcB->pData[i]); + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.c new file mode 100644 index 0000000..9364619 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.c @@ -0,0 +1,118 @@ +#include "ref.h" + +arm_status ref_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + float32_t sumR,sumI; + float32_t a0,b0,c0,d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[2*(r*innerSize + i) + 0]; + b0 = pSrcA->pData[2*(r*innerSize + i) + 1]; + c0 = pSrcB->pData[2*(i*outC + c) + 0]; + d0 = pSrcB->pData[2*(i*outC + c) + 1]; + + sumR += a0 * c0 - b0 * d0; + sumI += b0 * c0 + a0 * d0; + } + + pDst->pData[2*(r*outC + c) + 0] = sumR; + pDst->pData[2*(r*outC + c) + 1] = sumI; + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + q63_t sumR,sumI; + q31_t a0,b0,c0,d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[2*(r*innerSize + i) + 0]; + b0 = pSrcA->pData[2*(r*innerSize + i) + 1]; + c0 = pSrcB->pData[2*(i*outC + c) + 0]; + d0 = pSrcB->pData[2*(i*outC + c) + 1]; + + sumR += (q63_t)a0 * c0 - (q63_t)b0 * d0; + sumI += (q63_t)b0 * c0 + (q63_t)a0 * d0; + } + + pDst->pData[2*(r*outC + c) + 0] = ref_sat_q31(sumR >> 31); + pDst->pData[2*(r*outC + c) + 1] = ref_sat_q31(sumI >> 31); + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + q63_t sumR,sumI; + q15_t a0,b0,c0,d0; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[2*(r*innerSize + i) + 0]; + b0 = pSrcA->pData[2*(r*innerSize + i) + 1]; + c0 = pSrcB->pData[2*(i*outC + c) + 0]; + d0 = pSrcB->pData[2*(i*outC + c) + 1]; + + sumR += (q31_t)a0 * c0 - (q31_t)b0 * d0; + sumI += (q31_t)b0 * c0 + (q31_t)a0 * d0; + } + + pDst->pData[2*(r*outC + c) + 0] = ref_sat_q15(sumR >> 15); + pDst->pData[2*(r*outC + c) + 1] = ref_sat_q15(sumI >> 15); + } + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.c new file mode 100644 index 0000000..74d3ccc --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.c @@ -0,0 +1,57 @@ +#include "ref.h" + +arm_status ref_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t det; + uint32_t i, size; + arm_matrix_instance_f32 tmp; + + tmp.numCols = pSrc->numCols; + tmp.numRows = pSrc->numRows; + tmp.pData = scratchArray; + + det = ref_detrm(pSrc->pData,scratchArray,pSrc->numCols); + + size = pSrc->numCols * pSrc->numCols; + + ref_cofact(pSrc->pData,scratchArray,scratchArray + size,pSrc->numCols); + + ref_mat_trans_f32(&tmp,pDst); + + for(i=0;ipData[i] /= det; + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_inverse_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + float64_t det; + uint32_t i, size; + arm_matrix_instance_f64 tmp; + + tmp.numCols = pSrc->numCols; + tmp.numRows = pSrc->numRows; + tmp.pData = (float64_t*)scratchArray; + + det = ref_detrm64(pSrc->pData,(float64_t*)scratchArray,pSrc->numCols); + + size = pSrc->numCols * pSrc->numCols; + + ref_cofact64(pSrc->pData,(float64_t*)scratchArray,(float64_t*)scratchArray + size,pSrc->numCols); + + ref_mat_trans_f64(&tmp,pDst); + + for(i=0;ipData[i] /= det; + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.c new file mode 100644 index 0000000..e9ef432 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.c @@ -0,0 +1,91 @@ +#include "ref.h" + +arm_status ref_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + float32_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[r*innerSize + i] * pSrcB->pData[i*outC + c]; + } + + pDst->pData[r*outC + c] = sum; + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + q63_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[r*innerSize + i]) * pSrcB->pData[i*outC + c]; + } + + pDst->pData[r*outC + c] = ref_sat_q31(sum >> 31); + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t r,c,i,outR,outC,innerSize; + q63_t sum; + + outR = pSrcA->numRows; + outC = pSrcB->numCols; + innerSize = pSrcA->numCols; + + for(r=0;rpData[r*innerSize + i]) * pSrcB->pData[i*outC + c]; + } + + pDst->pData[r*outC + c] = ref_sat_q15(sum >> 15); + } + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.c new file mode 100644 index 0000000..d426ad6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.c @@ -0,0 +1,64 @@ +#include "ref.h" + +arm_status ref_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + + for(i=0;ipData[i] = pSrc->pData[i] * scale; + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scale, + int32_t shift, + arm_matrix_instance_q31 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + int32_t totShift = shift + 1; + q31_t tmp; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + + for(i=0;ipData[i] * scale) >> 32; + pDst->pData[i] = ref_sat_q31((q63_t)tmp << totShift ); + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scale, + int32_t shift, + arm_matrix_instance_q15 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + int32_t totShift = 15 - shift; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + + for(i=0;ipData[i] = ref_sat_q15( ((q31_t)pSrc->pData[i] * scale) >> totShift); + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.c new file mode 100644 index 0000000..bbd23f0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.c @@ -0,0 +1,58 @@ +#include "ref.h" + +arm_status ref_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = pSrcA->pData[i] - pSrcB->pData[i]; + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = ref_sat_q31( (q63_t)pSrcA->pData[i] - pSrcB->pData[i]); + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t i; + uint32_t numSamples; /* total number of elements in the matrix */ + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + for(i=0;ipData[i] = ref_sat_q15( (q31_t)pSrcA->pData[i] - pSrcB->pData[i]); + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.c new file mode 100644 index 0000000..8cb9a8d --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.c @@ -0,0 +1,77 @@ +#include "ref.h" + +arm_status ref_mat_trans_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + uint64_t r,c; + uint64_t numR = pSrc->numRows; + uint64_t numC = pSrc->numCols; + + for(r=0;rpData[c*numR + r] = pSrc->pData[r*numC + c]; + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + uint32_t r,c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for(r=0;rpData[c*numR + r] = pSrc->pData[r*numC + c]; + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + uint32_t r,c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for(r=0;rpData[c*numR + r] = pSrc->pData[r*numC + c]; + } + } + + return ARM_MATH_SUCCESS; +} + +arm_status ref_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + uint32_t r,c; + uint32_t numR = pSrc->numRows; + uint32_t numC = pSrc->numCols; + + for(r=0;rpData[c*numR + r] = pSrc->pData[r*numC + c]; + } + } + + return ARM_MATH_SUCCESS; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.c new file mode 100644 index 0000000..02b4127 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.c @@ -0,0 +1,85 @@ +#include "ref.h" + +void ref_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + uint32_t i, ind=0; + float32_t max=-FLT_MAX; + + for(i=0;i pSrc[i]) + { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} + +void ref_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + uint32_t i, ind=0; + q31_t min=INT_MAX; + + for(i=0;i pSrc[i]) + { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} + +void ref_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + uint32_t i, ind=0; + q15_t min=SHRT_MAX; + + for(i=0;i pSrc[i]) + { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} + +void ref_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + uint32_t i, ind=0; + q7_t min=SCHAR_MAX; + + for(i=0;i pSrc[i]) + { + min = pSrc[i]; + ind = i; + } + } + *pResult = min; + *pIndex = ind; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.c new file mode 100644 index 0000000..8202e04 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.c @@ -0,0 +1,61 @@ +#include "ref.h" + +void ref_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t i; + float32_t sumsq=0; + + for(i=0;i> 14; + } + *pResult = sumsq; +} + +void ref_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t i; + q63_t sumsq=0; + + for(i=0;i> 31; + tmp2 = ref_sat_q31(tmp1); + + /* GCC M0 problem: __aeabi_f2iz(QNAN) returns not 0 */ + help_float = (sqrtf((float)tmp2 / 2147483648.0f) * 2147483648.0f); + /* Checking for a NAN value in help_float */ + if (((*((int *)(&help_float))) & 0x7FC00000) == 0x7FC00000) { + help_float = 0; + } + *pResult = (q31_t)(help_float); + +// *pResult = (q31_t)(sqrtf((float)tmp2 / 2147483648.0f) * 2147483648.0f); +} + +void ref_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t i; + q63_t sumsq=0; + q31_t tmp1; + q15_t tmp2; + + for(i=0;i> 15; + tmp2 = ref_sat_q15(tmp1); + *pResult = (q15_t)(sqrtf((float)tmp2 / 32768.0f) * 32768.0f); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.c new file mode 100644 index 0000000..c0c1ba3 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.c @@ -0,0 +1,74 @@ +#include "ref.h" + +void ref_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t i; + float32_t sum=0, sumsq=0; + + if (blockSize == 1) + { + *pResult = 0; + return; + } + + for(i=0;i> 8; + sum += in; + sumsq += (q63_t)in * in; + } + sumsq /= (q63_t)(blockSize - 1); + sum = sum * sum / (q63_t)(blockSize * (blockSize - 1)); + *pResult = (q31_t)(sqrtf((float)( (sumsq - sum) >> 15) / 2147483648.0f ) * 2147483648.0f); +} + +void ref_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t i; + q31_t sum=0; + q63_t sumsq=0; + + if (blockSize == 1) + { + *pResult = 0; + return; + } + + for(i=0;i> 15) / 32768.0f ) * 32768.0f); +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.c new file mode 100644 index 0000000..f5da3a6 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.c @@ -0,0 +1,70 @@ +#include "ref.h" + +void ref_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t i; + float32_t sum=0, sumsq=0; + + if (blockSize == 1) + { + *pResult = 0; + return; + } + + for(i=0;i> 8; + sum += in; + sumsq += (q63_t)in * in; + } + *pResult = (sumsq - sum * sum / (q31_t)blockSize) / ((q31_t)blockSize - 1) >> 15; +} + +void ref_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t i; + q31_t sum=0; + q63_t sumsq=0; + + if (blockSize == 1) + { + *pResult = 0; + return; + } + + for(i=0;i> 15; +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.c new file mode 100644 index 0000000..08089f5 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.c @@ -0,0 +1,53 @@ +#include "ref.h" + +void ref_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 16; + } +} + +void ref_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 24; + } +} + +void ref_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i> 8; + } +} + +void ref_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + + for(i=0;i 0.0f ? 0.5f : -0.5f; //round + pDst[i] = ref_sat_q31((q63_t)in); //cast and saturate + } +} + +void ref_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + float32_t in; + + for(i=0;i 0.0f ? 0.5f : -0.5f; + pDst[i] = ref_sat_q15((q31_t)in); + } +} + +void ref_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t i; + float32_t in; + + for(i=0;i 0.0f ? 0.5f : -0.5f; + pDst[i] = ref_sat_q7((q15_t)in); + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.c new file mode 100644 index 0000000..4751821 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.c @@ -0,0 +1,30 @@ +#include "ref.h" + + +;/* +;* @brief In-place bit reversal function. +;* @param[in, out] *pSrc points to the in-place buffer of unknown 32-bit data type. +;* @param[in] bitRevLen bit reversal table length +;* @param[in] *pBitRevTab points to bit reversal table. +;* @return none. +;*/ +void arm_bitreversal_32(uint32_t *pSrc, uint32_t bitRevLen, uint32_t *pBitRevTab) +{ + uint32_t a,b,i,tmp; + + for(i=0; ifftLen; + int32_t dir = (ifftFlag) ? -1 : 1; + + // decrement pointer since the original version used fortran style indexing. + data--; + + n = N << 1; + j = 1; + for (i = 1; i < n; i += 2) { + if (j > i) { + tempr = data[j]; data[j] = data[i]; data[i] = tempr; + tempr = data[j+1]; data[j+1] = data[i+1]; data[i+1] = tempr; + } + m = n >> 1; + while (m >= 2 && j > m) { + j -= m; + m >>= 1; + } + j += m; + } + mmax = 2; + while (n > mmax) { + istep = 2*mmax; + theta = -6.283185307179586f/(dir*mmax); + wtemp = sinf(0.5f*theta); + wpr = -2.0f*wtemp*wtemp; + wpi = sinf(theta); + wr = 1.0f; + wi = 0.0f; + for (m = 1; m < mmax; m += 2) { + for (i = m; i <= n; i += istep) { + j =i + mmax; + tempr = wr*data[j] - wi*data[j+1]; + tempi = wr*data[j+1] + wi*data[j]; + data[j] = data[i] - tempr; + data[j+1] = data[i+1] - tempi; + data[i] += tempr; + data[i+1] += tempi; + } + wr = (wtemp = wr)*wpr - wi*wpi + wr; + wi = wi*wpr + wtemp*wpi + wi; + } + mmax = istep; + } + + // Inverse transform is scaled by 1/N + if (ifftFlag) + { + data++; + for(i = 0; i<2*N; i++) + { + data[i] /= N; + } + } +} + +void ref_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)p1; + + for(i=0;ifftLen*2;i++) + { + //read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)p1[i] / 2147483648.0f; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, ifftFlag, bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, ifftFlag, bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, ifftFlag, bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, ifftFlag, bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, ifftFlag, bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, ifftFlag, bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, ifftFlag, bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, ifftFlag, bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, ifftFlag, bitReverseFlag); + break; + } + + if (ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)( fSrc[i] * 2147483648.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + p1[i] = (q31_t)( fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)pSrc; + + for(i=0;ifftLen*2;i++) + { + //read the q15 data, cast to float, scale down for float, place in temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for(i=0;ifftLen*2;i++) + { + //copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, ifftFlag, bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, ifftFlag, bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, ifftFlag, bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, ifftFlag, bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, ifftFlag, bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, ifftFlag, bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, ifftFlag, bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, ifftFlag, bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, ifftFlag, bitReverseFlag); + break; + } + + if (ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc) +{ + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)pSrc; + + for(i=0;ifftLen*2;i++) + { + //read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + } + + if (S->ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)pSrc; + + for(i=0;ifftLen*2;i++) + { + //read the q15 data, cast to float, scale down for float, place in temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for(i=0;ifftLen*2;i++) + { + //copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + } + + if (S->ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc) +{ + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, pSrc, S->ifftFlag, S->bitReverseFlag); + break; + } +} + +void ref_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)pSrc; + + for(i=0;ifftLen*2;i++) + { + //read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + } + + if (S->ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q31, cast to q31 + pSrc[i] = (q31_t)( fSrc[i] * 2147483648.0f / (float32_t)S->fftLen); + } + } +} + +void ref_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc) +{ + uint32_t i; + float32_t *fSrc = (float32_t*)pSrc; + + for(i=0;ifftLen*2;i++) + { + //read the q15 data, cast to float, scale down for float, place in temporary buffer + scratchArray[i] = (float32_t)pSrc[i] / 32768.0f; + } + + for(i=0;ifftLen*2;i++) + { + //copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + switch(S->fftLen) + { + case 16: + ref_cfft_f32(&arm_cfft_sR_f32_len16, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fSrc, S->ifftFlag, S->bitReverseFlag); + break; + } + + if (S->ifftFlag) + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f ); + } + } + else + { + for(i=0;ifftLen*2;i++) + { + //read the float data, scale up for q15, cast to q15 + pSrc[i] = (q15_t)( fSrc[i] * 32768.0f / (float32_t)S->fftLen); + } + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.c new file mode 100644 index 0000000..9c1f207 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.c @@ -0,0 +1,89 @@ +#include "ref.h" + +void ref_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer) +{ + uint32_t n,k; + float32_t sum; + float32_t pi_by_N = 3.14159265358979f / (float32_t)S->N; + float32_t tmp; + float32_t normalize = sqrtf(2.0f / (float32_t)S->N); + + for(k=0;kN;k++) + { + sum=0.0f; + tmp = ((float32_t)k + 0.5f)*pi_by_N; + for(n=0;nN;n++) + { + sum += pInlineBuffer[n] * cosf(tmp * ((float32_t)n + 0.5f)); + } + scratchArray[k] = normalize * sum; + } + + for(k=0;kN;k++) + { + pInlineBuffer[k] = scratchArray[k]; + } +} + +void ref_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer) +{ + arm_dct4_instance_f32 SS; + float32_t *fSrc = (float32_t*)pInlineBuffer; + uint32_t i; + + SS.N = S->N; + + for(i=0;iN;i++) + { + //read the q31 data, cast to float, scale down for float + fSrc[i] = (float32_t)pInlineBuffer[i] / 2147483648.0f; + } + + ref_dct4_f32(&SS,(float32_t*)0,fSrc); + + for(i=0;iN;i++) + { + fSrc[i] = fSrc[i] * 2147483648.0f / (float32_t)S->N ; + fSrc[i] += (fSrc[i] > 0) ? 0.5f : -0.5f; + pInlineBuffer[i] = (q31_t)fSrc[i]; + } +} + +void ref_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer) +{ + arm_dct4_instance_f32 SS; + float32_t *fSrc = (float32_t*)pInlineBuffer; + uint32_t i; + + SS.N = S->N; + + for(i=0;iN;i++) + { + //read the q15 data, cast to float, scale down for float, place in temporary buffer + scratchArray[i] = (float32_t)pInlineBuffer[i] / 32768.0f; + } + + for(i=0;iN;i++) + { + //copy from temp buffer to final buffer + fSrc[i] = scratchArray[i]; + } + + ref_dct4_f32(&SS,(float32_t*)0,fSrc); + + for(i=0;iN;i++) + { + fSrc[i] = fSrc[i] * 32768.0f / (float32_t)S->N; + fSrc[i] += (fSrc[i] > 0) ? 0.5f : -0.5f; + pInlineBuffer[i] = (q15_t)fSrc[i]; + } +} diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.c new file mode 100644 index 0000000..79738f0 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.c @@ -0,0 +1,302 @@ +#include "ref.h" +#include "arm_const_structs.h" + +void ref_rfft_f32( + arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst) +{ + uint32_t i; + + if (S->ifftFlagR) + { + for(i=0;ifftLenReal*2;i++) + { + pDst[i] = pSrc[i]; + } + } + else + { + for(i=0;ifftLenReal;i++) + { + pDst[2*i+0] = pSrc[i]; + pDst[2*i+1] = 0.0f; + } + } + + switch(S->fftLenReal) + { + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, pDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, pDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, pDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, pDst, S->ifftFlagR, S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) + { + //throw away the imaginary part which should be all zeros + for(i=0;ifftLenReal;i++) + { + pDst[i] = pDst[2*i]; + } + } +} + +void ref_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag) +{ + uint32_t i,j; + + if (ifftFlag) + { + for(i=0;ifftLenRFFT;i++) + { + pOut[i] = p[i]; + } + //unpack first sample's complex part into middle sample's real part + pOut[S->fftLenRFFT] = pOut[1]; + pOut[S->fftLenRFFT+1] = 0; + pOut[1] = 0; + j=4; + for(i = S->fftLenRFFT / 2 + 1;i < S->fftLenRFFT;i++) + { + pOut[2*i+0] = p[2*i+0 - j]; + pOut[2*i+1] = -p[2*i+1 - j]; + j+=4; + } + } + else + { + for(i=0;ifftLenRFFT;i++) + { + pOut[2*i+0] = p[i]; + pOut[2*i+1] = 0.0f; + } + } + + switch(S->fftLenRFFT) + { + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, pOut, ifftFlag, 1); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, pOut, ifftFlag, 1); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, pOut, ifftFlag, 1); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, pOut, ifftFlag, 1); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, pOut, ifftFlag, 1); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, pOut, ifftFlag, 1); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, pOut, ifftFlag, 1); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, pOut, ifftFlag, 1); + break; + } + + if (ifftFlag) + { + //throw away the imaginary part which should be all zeros + for(i=0;ifftLenRFFT;i++) + { + pOut[i] = pOut[2*i]; + } + } + else + { + //pack last sample's real part into first sample's complex part + pOut[1] = pOut[S->fftLenRFFT]; + } +} + +void ref_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst) +{ + uint32_t i; + float32_t *fDst = (float32_t*)pDst; + + if (S->ifftFlagR) + { + for(i=0;ifftLenReal*2;i++) + { + fDst[i] = (float32_t)pSrc[i] / 2147483648.0f; + } + } + else + { + for(i=0;ifftLenReal;i++) + { + fDst[2*i+0] = (float32_t)pSrc[i] / 2147483648.0f; + fDst[2*i+1] = 0.0f; + } + } + + switch(S->fftLenReal) + { + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) + { + //throw away the imaginary part which should be all zeros + for(i=0;ifftLenReal;i++) + { + //read the float data, scale up for q31, cast to q31 + pDst[i] = (q31_t)( fDst[2*i] * 2147483648.0f); + } + } + else + { + for(i=0;ifftLenReal;i++) + { + //read the float data, scale up for q31, cast to q31 + pDst[i] = (q31_t)( fDst[i] * 2147483648.0f / (float32_t)S->fftLenReal); + } + } +} + +void ref_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst) +{ + uint32_t i; + float32_t *fDst = (float32_t*)pDst; + + + if (S->ifftFlagR) + { + for(i=0;ifftLenReal*2;i++) + { + fDst[i] = (float32_t)pSrc[i] / 32768.0f; + } + } + else + { + for(i=0;ifftLenReal;i++) + { + //read the q15 data, cast to float, scale down for float + fDst[2*i+0] = (float32_t)pSrc[i] / 32768.0f; + fDst[2*i+1] = 0.0f; + } + } + + switch(S->fftLenReal) + { + case 32: + ref_cfft_f32(&arm_cfft_sR_f32_len32, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 64: + ref_cfft_f32(&arm_cfft_sR_f32_len64, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 128: + ref_cfft_f32(&arm_cfft_sR_f32_len128, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 256: + ref_cfft_f32(&arm_cfft_sR_f32_len256, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 512: + ref_cfft_f32(&arm_cfft_sR_f32_len512, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 1024: + ref_cfft_f32(&arm_cfft_sR_f32_len1024, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 2048: + ref_cfft_f32(&arm_cfft_sR_f32_len2048, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 4096: + ref_cfft_f32(&arm_cfft_sR_f32_len4096, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + + case 8192: + ref_cfft_f32(&ref_cfft_sR_f32_len8192, fDst, S->ifftFlagR, S->bitReverseFlagR); + break; + } + + if (S->ifftFlagR) + { + //throw away the imaginary part which should be all zeros + for(i=0;ifftLenReal;i++) + { + pDst[i] = (q15_t)( fDst[2*i] * 32768.0f); + } + } + else + { + for(i=0;ifftLenReal;i++) + { + pDst[i] = (q15_t)( fDst[i] * 32768.0f / (float32_t)S->fftLenReal); + } + } +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt new file mode 100644 index 0000000..7ac021f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_class_marks_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c new file mode 100644 index 0000000..e6842de --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c @@ -0,0 +1,211 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_class_marks_example_f32.c +* +* Description: Example code to calculate Minimum, Maximum +* Mean, std and variance of marks obtained in a class +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ClassMarks Class Marks Example + * + * \par Description: + * \par + * Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance + * and Matrix functions to calculate statistical values of marks obtained in a class. + * + * \note This example also demonstrates the usage of static initialization. + * + * \par Variables Description: + * \par + * \li \c testMarks_f32 points to the marks scored by 20 students in 4 subjects + * \li \c max_marks Maximum of all marks + * \li \c min_marks Minimum of all marks + * \li \c mean Mean of all marks + * \li \c var Variance of the marks + * \li \c std Standard deviation of the marks + * \li \c numStudents Total number of students in the class + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_mult_f32() + * - arm_max_f32() + * - arm_min_f32() + * - arm_mean_f32() + * - arm_std_f32() + * - arm_var_f32() + * + * Refer + * \link arm_class_marks_example_f32.c \endlink + * + */ + + +/** \example arm_class_marks_example_f32.c + */ +#include "arm_math.h" + +#define USE_STATIC_INIT + + /* ---------------------------------------------------------------------- +** Global defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES (20*4) + +/* ---------------------------------------------------------------------- +** List of Marks scored by 20 students for 4 subjects +** ------------------------------------------------------------------- */ +const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] = +{ + 42.000000, 37.000000, 81.000000, 28.000000, + 83.000000, 72.000000, 36.000000, 38.000000, + 32.000000, 51.000000, 63.000000, 64.000000, + 97.000000, 82.000000, 95.000000, 90.000000, + 66.000000, 51.000000, 54.000000, 42.000000, + 67.000000, 56.000000, 45.000000, 57.000000, + 67.000000, 69.000000, 35.000000, 52.000000, + 29.000000, 81.000000, 58.000000, 47.000000, + 38.000000, 76.000000, 100.000000, 29.000000, + 33.000000, 47.000000, 29.000000, 50.000000, + 34.000000, 41.000000, 61.000000, 46.000000, + 52.000000, 50.000000, 48.000000, 36.000000, + 47.000000, 55.000000, 44.000000, 40.000000, + 100.000000, 94.000000, 84.000000, 37.000000, + 32.000000, 71.000000, 47.000000, 77.000000, + 31.000000, 50.000000, 49.000000, 35.000000, + 63.000000, 67.000000, 40.000000, 31.000000, + 29.000000, 68.000000, 61.000000, 38.000000, + 31.000000, 28.000000, 28.000000, 76.000000, + 55.000000, 33.000000, 29.000000, 39.000000 +}; + + +/* ---------------------------------------------------------------------- +* Number of subjects X 1 +* ------------------------------------------------------------------- */ +const float32_t testUnity_f32[4] = +{ + 1.000, 1.000, 1.000, 1.000 +}; + + +/* ---------------------------------------------------------------------- +** f32 Output buffer +** ------------------------------------------------------------------- */ +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + + +/* ------------------------------------------------------------------ +* Global defines +*------------------------------------------------------------------- */ +#define NUMSTUDENTS 20 +#define NUMSUBJECTS 4 + +/* ------------------------------------------------------------------ +* Global variables +*------------------------------------------------------------------- */ + + uint32_t numStudents = 20; + uint32_t numSubjects = 4; +float32_t max_marks, min_marks, mean, std, var; + uint32_t student_num; + +/* ---------------------------------------------------------------------------------- +* Main f32 test function. It returns maximum marks secured and student number +* ------------------------------------------------------------------------------- */ + +int32_t main() +{ + +#ifndef USE_STATIC_INIT + + arm_matrix_instance_f32 srcA; + arm_matrix_instance_f32 srcB; + arm_matrix_instance_f32 dstC; + + /* Input and output matrices initializations */ + arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32); + arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32); + arm_mat_init_f32(&dstC, numStudents, 1, testOutput); + +#else + + /* Static Initializations of Input and output matrix sizes and array */ + arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32}; + arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32}; + arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput}; + +#endif + + + /* ---------------------------------------------------------------------- + *Call the Matrix multiplication process function + * ------------------------------------------------------------------- */ + arm_mat_mult_f32(&srcA, &srcB, &dstC); + + /* ---------------------------------------------------------------------- + ** Call the Max function to calculate max marks among numStudents + ** ------------------------------------------------------------------- */ + arm_max_f32(testOutput, numStudents, &max_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Min function to calculate min marks among numStudents + ** ------------------------------------------------------------------- */ + arm_min_f32(testOutput, numStudents, &min_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Mean function to calculate mean + ** ------------------------------------------------------------------- */ + arm_mean_f32(testOutput, numStudents, &mean); + + /* ---------------------------------------------------------------------- + ** Call the std function to calculate standard deviation + ** ------------------------------------------------------------------- */ + arm_std_f32(testOutput, numStudents, &std); + + /* ---------------------------------------------------------------------- + ** Call the var function to calculate variance + ** ------------------------------------------------------------------- */ + arm_var_f32(testOutput, numStudents, &var); + + while (1); /* main function does not return */ +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt new file mode 100644 index 0000000..7ef79e2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_convolution_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c new file mode 100644 index 0000000..e4665fe --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c @@ -0,0 +1,247 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_convolution_example_f32.c +* +* Description: Example code demonstrating Convolution of two input signals using fft. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ConvolutionExample Convolution Example + * + * \par Description: + * \par + * Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex + * Multiplication, and Support Functions. + * + * \par Algorithm: + * \par + * The convolution theorem states that convolution in the time domain corresponds to + * multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of + * two signals is equal to the product of their individual Fourier transforms. + * The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT). + * \par + * Two input signals, a[n] and b[n], with lengths \c n1 and \c n2 respectively, + * are zero padded so that their lengths become \c N, which is greater than or equal to (n1+n2-1) + * and is a power of 4 as FFT implementation is radix-4. + * The convolution of a[n] and b[n] is obtained by taking the FFT of the input + * signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of + * the multiplied result. + * \par + * This is denoted by the following equations: + * 
 A[k] = FFT(a[n],N)
+ * B[k] = FFT(b[n],N)
+ * conv(a[n], b[n]) = IFFT(A[k] * B[k], N)
+ * where A[k] and B[k] are the N-point FFTs of the signals a[n] + * and b[n] respectively. + * The length of the convolved signal is (n1+n2-1). + * + * \par Block Diagram: + * \par + * \image html Convolution.gif + * + * \par Variables Description: + * \par + * \li \c testInputA_f32 points to the first input sequence + * \li \c srcALen length of the first input sequence + * \li \c testInputB_f32 points to the second input sequence + * \li \c srcBLen length of the second input sequence + * \li \c outLen length of convolution output sequence, (srcALen + srcBLen - 1) + * \li \c AxB points to the output array where the product of individual FFTs of inputs is stored. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fill_f32() + * - arm_copy_f32() + * - arm_cfft_radix4_init_f32() + * - arm_cfft_radix4_f32() + * - arm_cmplx_mult_cmplx_f32() + * + * Refer + * \link arm_convolution_example_f32.c \endlink + * + */ + + +/** \example arm_convolution_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 128 +#define DELTA (0.000001f) +#define SNR_THRESHOLD 90 + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t Ak[MAX_BLOCKSIZE]; /* Input A */ +float32_t Bk[MAX_BLOCKSIZE]; /* Input B */ +float32_t AxB[MAX_BLOCKSIZE * 2]; /* Output */ + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Convolution example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +float32_t testInputA_f32[64] = +{ + -0.808920, 1.357369, 1.180861, -0.504544, 1.762637, -0.703285, + 1.696966, 0.620571, -0.151093, -0.100235, -0.872382, -0.403579, + -0.860749, -0.382648, -1.052338, 0.128113, -0.646269, 1.093377, + -2.209198, 0.471706, 0.408901, 1.266242, 0.598252, 1.176827, + -0.203421, 0.213596, -0.851964, -0.466958, 0.021841, -0.698938, + -0.604107, 0.461778, -0.318219, 0.942520, 0.577585, 0.417619, + 0.614665, 0.563679, -1.295073, -0.764437, 0.952194, -0.859222, + -0.618554, -2.268542, -1.210592, 1.655853, -2.627219, -0.994249, + -1.374704, 0.343799, 0.025619, 1.227481, -0.708031, 0.069355, + -1.845228, -1.570886, 1.010668, -1.802084, 1.630088, 1.286090, + -0.161050, -0.940794, 0.367961, 0.291907 + +}; + +float32_t testInputB_f32[64] = +{ + 0.933724, 0.046881, 1.316470, 0.438345, 0.332682, 2.094885, + 0.512081, 0.035546, 0.050894, -2.320371, 0.168711, -1.830493, + -0.444834, -1.003242, -0.531494, -1.365600, -0.155420, -0.757692, + -0.431880, -0.380021, 0.096243, -0.695835, 0.558850, -1.648962, + 0.020369, -0.363630, 0.887146, 0.845503, -0.252864, -0.330397, + 1.269131, -1.109295, -1.027876, 0.135940, 0.116721, -0.293399, + -1.349799, 0.166078, -0.802201, 0.369367, -0.964568, -2.266011, + 0.465178, 0.651222, -0.325426, 0.320245, -0.784178, -0.579456, + 0.093374, 0.604778, -0.048225, 0.376297, -0.394412, 0.578182, + -1.218141, -1.387326, 0.692462, -0.631297, 0.153137, -0.638952, + 0.635474, -0.970468, 1.334057, -0.111370 +}; + +const float testRefOutput_f32[127] = +{ + -0.818943, 1.229484, -0.533664, 1.016604, 0.341875, -1.963656, + 5.171476, 3.478033, 7.616361, 6.648384, 0.479069, 1.792012, + -1.295591, -7.447818, 0.315830, -10.657445, -2.483469, -6.524236, + -7.380591, -3.739005, -8.388957, 0.184147, -1.554888, 3.786508, + -1.684421, 5.400610, -1.578126, 7.403361, 8.315999, 2.080267, + 11.077776, 2.749673, 7.138962, 2.748762, 0.660363, 0.981552, + 1.442275, 0.552721, -2.576892, 4.703989, 0.989156, 8.759344, + -0.564825, -3.994680, 0.954710, -5.014144, 6.592329, 1.599488, + -13.979146, -0.391891, -4.453369, -2.311242, -2.948764, 1.761415, + -0.138322, 10.433007, -2.309103, 4.297153, 8.535523, 3.209462, + 8.695819, 5.569919, 2.514304, 5.582029, 2.060199, 0.642280, + 7.024616, 1.686615, -6.481756, 1.343084, -3.526451, 1.099073, + -2.965764, -0.173723, -4.111484, 6.528384, -6.965658, 1.726291, + 1.535172, 11.023435, 2.338401, -4.690188, 1.298210, 3.943885, + 8.407885, 5.168365, 0.684131, 1.559181, 1.859998, 2.852417, + 8.574070, -6.369078, 6.023458, 11.837963, -6.027632, 4.469678, + -6.799093, -2.674048, 6.250367, -6.809971, -3.459360, 9.112410, + -2.711621, -1.336678, 1.564249, -1.564297, -1.296760, 8.904013, + -3.230109, 6.878013, -7.819823, 3.369909, -1.657410, -2.007358, + -4.112825, 1.370685, -3.420525, -6.276605, 3.244873, -3.352638, + 1.545372, 0.902211, 0.197489, -1.408732, 0.523390, 0.348440, 0 +}; + + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t srcALen = 64; /* Length of Input A */ +uint32_t srcBLen = 64; /* Length of Input B */ +uint32_t outLen; /* Length of convolution output */ +float32_t snr; /* output SNR */ + +int32_t main(void) +{ + arm_status status; /* Status of the example */ + arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */ + + /* CFFT Structure instance pointer */ + arm_cfft_radix4_instance_f32 *cfft_instance_ptr = + (arm_cfft_radix4_instance_f32*) &cfft_instance; + + /* output length of convolution */ + outLen = srcALen + srcBLen - 1; + + /* Initialise the fft input buffers with all zeros */ + arm_fill_f32(0.0, Ak, MAX_BLOCKSIZE); + arm_fill_f32(0.0, Bk, MAX_BLOCKSIZE); + + /* Copy the input values to the fft input buffers */ + arm_copy_f32(testInputA_f32, Ak, MAX_BLOCKSIZE/2); + arm_copy_f32(testInputB_f32, Bk, MAX_BLOCKSIZE/2); + + /* Initialize the CFFT function to compute 64 point fft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1); + + /* Transform input a[n] from time domain to frequency domain A[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Ak); + /* Transform input b[n] from time domain to frequency domain B[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Bk); + + /* Complex Multiplication of the two input buffers in frequency domain */ + arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2); + + /* Initialize the CIFFT function to compute 64 point ifft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1); + + /* Transform the multiplication output from frequency domain to time domain, + that gives the convolved output */ + arm_cfft_radix4_f32(cfft_instance_ptr, AxB); + + /* SNR Calculation */ + snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1); + + /* Compare the SNR with threshold to test whether the + computed output is matched with the reference output values. */ + if ( snr > SNR_THRESHOLD) + { + status = ARM_MATH_SUCCESS; + } + + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c new file mode 100644 index 0000000..f615e6f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h new file mode 100644 index 0000000..5a18734 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt new file mode 100644 index 0000000..f889251 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_dotproduct_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c new file mode 100644 index 0000000..5a05071 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_dotproduct_example_f32.c +* +* Description: Example code computing dot product of two vectors. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup DotproductExample Dot Product Example + * + * \par Description: + * \par + * Demonstrates the use of the Multiply and Add functions to perform the dot product. + * The dot product of two vectors is obtained by multiplying corresponding elements + * and summing the products. + + * \par Algorithm: + * \par + * The two input vectors \c A and \c B with length \c n, are multiplied element-by-element + * and then added to obtain dot product. + * \par + * This is denoted by the following equation: + * 
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]
+ * + * \par Block Diagram: + * \par + * \image html dotProduct.gif + * + * \par Variables Description: + * \par + * \li \c srcA_buf_f32 points to first input vector + * \li \c srcB_buf_f32 points to second input vector + * \li \c testOutput stores dot product of the two input vectors. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_dotproduct_example_f32.c \endlink + * + */ + + +/** \example arm_dotproduct_example_f32.c + */ + +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Dot Product example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +/* ---------------------------------------------------------------------- +** Test input data of srcA for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcA_buf_f32[MAX_BLOCKSIZE] = +{ + -0.4325648115282207, -1.6655843782380970, 0.1253323064748307, + 0.2876764203585489, -1.1464713506814637, 1.1909154656429988, + 1.1891642016521031, -0.0376332765933176, 0.3272923614086541, + 0.1746391428209245, -0.1867085776814394, 0.7257905482933027, + -0.5883165430141887, 2.1831858181971011, -0.1363958830865957, + 0.1139313135208096, 1.0667682113591888, 0.0592814605236053, + -0.0956484054836690, -0.8323494636500225, 0.2944108163926404, + -1.3361818579378040, 0.7143245518189522, 1.6235620644462707, + -0.6917757017022868, 0.8579966728282626, 1.2540014216025324, + -1.5937295764474768, -1.4409644319010200, 0.5711476236581780, + -0.3998855777153632, 0.6899973754643451 +}; + +/* ---------------------------------------------------------------------- +** Test input data of srcB for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcB_buf_f32[MAX_BLOCKSIZE] = +{ + 1.7491401329284098, 0.1325982188803279, 0.3252281811989881, + -0.7938091410349637, 0.3149236145048914, -0.5272704888029532, + 0.9322666565031119, 1.1646643544607362, -2.0456694357357357, + -0.6443728590041911, 1.7410657940825480, 0.4867684246821860, + 1.0488288293660140, 1.4885752747099299, 1.2705014969484090, + -1.8561241921210170, 2.1343209047321410, 1.4358467535865909, + -0.9173023332875400, -1.1060770780029008, 0.8105708062681296, + 0.6985430696369063, -0.4015827425012831, 1.2687512030669628, + -0.7836083053674872, 0.2132664971465569, 0.7878984786088954, + 0.8966819356782295, -0.1869172943544062, 1.0131816724341454, + 0.2484350696132857, 0.0596083377937976 +}; + +/* Reference dot product output */ +float32_t refDotProdOut = 5.9273644806352142; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +float32_t multOutput[MAX_BLOCKSIZE]; /* Intermediate output */ +float32_t testOutput; /* Final ouput */ + +arm_status status; /* Status of the example */ + +int32_t main(void) +{ + uint32_t i; /* Loop counter */ + float32_t diff; /* Difference between reference and test outputs */ + + /* Multiplication of two input buffers */ + arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE); + + /* Accumulate the multiplication output values to + get the dot product of the two inputs */ + for(i=0; i< MAX_BLOCKSIZE; i++) + { + arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1); + } + + /* absolute value of difference between ref and test */ + diff = fabsf(refDotProdOut - testOutput); + + /* Comparison of dot product value with reference */ + if (diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + if ( status == ARM_MATH_TEST_FAILURE) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt new file mode 100644 index 0000000..37bea21 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_fft_bin_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c new file mode 100644 index 0000000..10f3e12 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c @@ -0,0 +1,308 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fft_bin_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +Test Input signal contains 10KHz signal + Uniformly distributed white noise +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_10khz[2048] = +{ +-0.865129623056441, 0.000000000000000, -2.655020678073846, 0.000000000000000, 0.600664612949661, 0.000000000000000, 0.080378093886515, 0.000000000000000, +-2.899160484012034, 0.000000000000000, 2.563004262857762, 0.000000000000000, 3.078328403304206, 0.000000000000000, 0.105906778385130, 0.000000000000000, +0.048366940168201, 0.000000000000000, -0.145696461188734, 0.000000000000000, -0.023417155362879, 0.000000000000000, 2.127729174988954, 0.000000000000000, +-1.176633086028377, 0.000000000000000, 3.690223557991855, 0.000000000000000, -0.622791766173194, 0.000000000000000, 0.722837373872203, 0.000000000000000, +2.739754205367484, 0.000000000000000, -0.062610410524552, 0.000000000000000, -0.891296810967338, 0.000000000000000, -1.845872258871811, 0.000000000000000, +1.195039415434387, 0.000000000000000, -2.177388969045026, 0.000000000000000, 1.078649103637905, 0.000000000000000, 2.570976050490193, 0.000000000000000, +-1.383551403404574, 0.000000000000000, 2.392141424058873, 0.000000000000000, 2.858002843205065, 0.000000000000000, -3.682433899725536, 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0.000000000000000, -4.192139262163992, 0.000000000000000, 3.023496047962126, 0.000000000000000, 1.149775163736637, 0.000000000000000, +2.038151304801731, 0.000000000000000, 3.016122489841263, 0.000000000000000, -4.829481812137012, 0.000000000000000, -1.668436615909279, 0.000000000000000, +0.958586784636918, 0.000000000000000, 1.550652410058678, 0.000000000000000, -1.456305257976716, 0.000000000000000, -0.079588392344731, 0.000000000000000, +-2.453213599392345, 0.000000000000000, 0.296795909127105, 0.000000000000000, -0.253426616607643, 0.000000000000000, 1.418937160028195, 0.000000000000000, +-1.672949529066915, 0.000000000000000, -1.620990298572947, 0.000000000000000, -1.085103073196045, 0.000000000000000, 0.738606361195386, 0.000000000000000, +-2.097831202853255, 0.000000000000000, 2.711952282071310, 0.000000000000000, 1.498539238246888, 0.000000000000000, 1.317457282535915, 0.000000000000000, +-0.302765938349717, 0.000000000000000, -0.044623707947201, 0.000000000000000, 2.337405215062395, 0.000000000000000, -3.980689173859100, 0.000000000000000, + + +}; + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c new file mode 100644 index 0000000..91d15b5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fft_bin_example_f32.c +* +* Description: Example code demonstrating calculation of Max energy bin of +* frequency domain of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FrequencyBin Frequency Bin Example + * + * \par Description + * \par + * Demonstrates the calculation of the maximum energy bin in the frequency + * domain of the input signal with the use of Complex FFT, Complex + * Magnitude, and Maximum functions. + * + * \par Algorithm: + * \par + * The input test signal contains a 10 kHz signal with uniformly distributed white noise. + * Calculating the FFT of the input signal will give us the maximum energy of the + * bin corresponding to the input frequency of 10 kHz. + * + * \par Block Diagram: + * \image html FFTBin.gif "Block Diagram" + * \par + * The figure below shows the time domain signal of 10 kHz signal with + * uniformly distributed white noise, and the next figure shows the input + * in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. + * \par + * \image html FFTBinInput.gif "Input signal in Time domain" + * \image html FFTBinOutput.gif "Input signal in Frequency domain" + * + * \par Variables Description: + * \par + * \li \c testInput_f32_10khz points to the input data + * \li \c testOutput points to the output data + * \li \c fftSize length of FFT + * \li \c ifftFlag flag for the selection of CFFT/CIFFT + * \li \c doBitReverse Flag for selection of normal order or bit reversed order + * \li \c refIndex reference index value at which maximum energy of bin ocuurs + * \li \c testIndex calculated index value at which maximum energy of bin ocuurs + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cfft_f32() + * - arm_cmplx_mag_f32() + * - arm_max_f32() + * + * Refer + * \link arm_fft_bin_example_f32.c \endlink + * + */ + + +/** \example arm_fft_bin_example_f32.c + */ + + +#include "arm_math.h" +#include "arm_const_structs.h" + +#define TEST_LENGTH_SAMPLES 2048 + +/* ------------------------------------------------------------------- +* External Input and Output buffer Declarations for FFT Bin Example +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; +static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; + +/* ------------------------------------------------------------------ +* Global variables for FFT Bin Example +* ------------------------------------------------------------------- */ +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; + +/* Reference index at which max energy of bin ocuurs */ +uint32_t refIndex = 213, testIndex = 0; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_status status; + float32_t maxValue; + + status = ARM_MATH_SUCCESS; + + /* Process the data through the CFFT/CIFFT module */ + arm_cfft_f32(&arm_cfft_sR_f32_len1024, testInput_f32_10khz, ifftFlag, doBitReverse); + + /* Process the data through the Complex Magnitude Module for + calculating the magnitude at each bin */ + arm_cmplx_mag_f32(testInput_f32_10khz, testOutput, fftSize); + + /* Calculates maxValue and returns corresponding BIN value */ + arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); + + if (testIndex != refIndex) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt new file mode 100644 index 0000000..9189b7c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_fir_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c new file mode 100644 index 0000000..3a95fc5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fir_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input signal contains 1000Hz + 15000 Hz +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_1kHz_15kHz[320] = +{ ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +}; + +float32_t refOutput[320] = +{ ++0.0000000000f, -0.0010797829f, -0.0007681386f, -0.0001982932f, +0.0000644313f, +0.0020854271f, +0.0036891871f, +0.0015855941f, +-0.0026280805f, -0.0075907658f, -0.0119390538f, -0.0086665968f, +0.0088981202f, +0.0430539279f, +0.0974468742f, +0.1740405600f, ++0.2681416601f, +0.3747720089f, +0.4893362230f, +0.6024154672f, +0.7058740791f, +0.7968348987f, +0.8715901940f, +0.9277881093f, ++0.9682182661f, +0.9934674267f, +1.0012052245f, +0.9925859371f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, 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-1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, -0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f +}; + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c new file mode 100644 index 0000000..3dd9f5a --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c @@ -0,0 +1,233 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library + * Title: arm_fir_example_f32.c + * + * Description: Example code demonstrating how an FIR filter can be used + * as a low pass filter. + * + * Target Processor: Cortex-M4/Cortex-M3 + * +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FIRLPF FIR Lowpass Filter Example + * + * \par Description: + * \par + * Removes high frequency signal components from the input using an FIR lowpass filter. + * The example demonstrates how to configure an FIR filter and then pass data through + * it in a block-by-block fashion. + * \image html FIRLPF_signalflow.gif + * + * \par Algorithm: + * \par + * The input signal is a sum of two sine waves: 1 kHz and 15 kHz. + * This is processed by an FIR lowpass filter with cutoff frequency 6 kHz. + * The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output. + * \par + * The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and + * a length of 29 points. + * The MATLAB code to generate the filter coefficients is shown below: + * 
+ *     h = fir1(28, 6/24);
+ *
+ * The first argument is the "order" of the filter and is always one less than the desired length. + * The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist). + * A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25. + * The CMSIS FIR filter function requires the coefficients to be in time reversed order. + * 
+ *     fliplr(h)
+ *
+ * The resulting filter coefficients and are shown below. + * Note that the filter is symmetric (a property of linear phase FIR filters) + * and the point of symmetry is sample 14. Thus the filter will have a delay of + * 14 samples for all frequencies. + * \par + * \image html FIRLPF_coeffs.gif + * \par + * The frequency response of the filter is shown next. + * The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz. + * \par + * \image html FIRLPF_response.gif + * \par + * The input signal is shown below. + * The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation. + * The two sine wave components can be clearly seen. + * \par + * \image html FIRLPF_input.gif + * \par + * The output of the filter is shown below. The 15 kHz component has been eliminated. + * \par + * \image html FIRLPF_output.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32_1kHz_15kHz points to the input data + * \li \c refOutput points to the reference output data + * \li \c testOutput points to the test output data + * \li \c firStateF32 points to state buffer + * \li \c firCoeffs32 points to coefficient buffer + * \li \c blockSize number of samples processed at a time + * \li \c numBlocks number of frames + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fir_init_f32() + * - arm_fir_f32() + * + * Refer + * \link arm_fir_example_f32.c \endlink + * + */ + + +/** \example arm_fir_example_f32.c + */ + +/* ---------------------------------------------------------------------- +** Include Files +** ------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +** Macro Defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 320 +#define SNR_THRESHOLD_F32 140.0f +#define BLOCK_SIZE 32 +#define NUM_TAPS 29 + +/* ------------------------------------------------------------------- + * The input signal and reference output (computed with MATLAB) + * are defined externally in arm_fir_lpf_data.c. + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]; +extern float32_t refOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare Test output buffer + * ------------------------------------------------------------------- */ + +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare State buffer of size (numTaps + blockSize - 1) + * ------------------------------------------------------------------- */ + +static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1]; + +/* ---------------------------------------------------------------------- +** FIR Coefficients buffer generated using fir1() MATLAB function. +** fir1(28, 6/24) +** ------------------------------------------------------------------- */ + +const float32_t firCoeffs32[NUM_TAPS] = { + -0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, + -0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, + +0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, + +0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f +}; + +/* ------------------------------------------------------------------ + * Global variables for FIR LPF Example + * ------------------------------------------------------------------- */ + +uint32_t blockSize = BLOCK_SIZE; +uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE; + +float32_t snr; + +/* ---------------------------------------------------------------------- + * FIR LPF Example + * ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_fir_instance_f32 S; + arm_status status; + float32_t *inputF32, *outputF32; + + /* Initialize input and output buffer pointers */ + inputF32 = &testInput_f32_1kHz_15kHz[0]; + outputF32 = &testOutput[0]; + + /* Call FIR init function to initialize the instance structure. */ + arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize); + + /* ---------------------------------------------------------------------- + ** Call the FIR process function for every blockSize samples + ** ------------------------------------------------------------------- */ + + for(i=0; i < numBlocks; i++) + { + arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize); + } + + /* ---------------------------------------------------------------------- + ** Compare the generated output against the reference output computed + ** in MATLAB. + ** ------------------------------------------------------------------- */ + + snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) + { + status = ARM_MATH_TEST_FAILURE; + } + else + { + status = ARM_MATH_SUCCESS; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signal does not match the reference output. + ** ------------------------------------------------------------------- */ + + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + +/** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c new file mode 100644 index 0000000..f615e6f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h new file mode 100644 index 0000000..5a18734 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt new file mode 100644 index 0000000..c2452b6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_graphic_equalizer_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c new file mode 100644 index 0000000..b6ab8c9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_graphic_equalizer_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +float32_t testRefOutput_f32[320] = { + +0.000000000000000000, 0.001898396760225296, 0.004215449094772339, 0.007432077080011368, 0.010948467999696732, 0.015026375651359558, 0.019191544502973557, 0.023574527353048325, +0.027919445186853409, 0.032277785241603851, 0.036551639437675476, 0.040732793509960175, 0.044799156486988068, 0.048710610717535019, 0.052476800978183746, 0.056059073656797409, +0.059482168406248093, 0.062726479023694992, 0.065821025520563126, 0.068763464689254761, 0.071577839553356171, 0.074270240962505341, 0.076856281608343124, 0.079344697296619415, +0.081745062023401260, 0.084067162126302719, 0.086318407207727432, 0.088509257882833481, 0.090647127479314804, 0.092742368578910828, 0.094802625477313995, 0.096837285906076431, +0.098853722214698792, 0.100859899073839190, 0.102862443774938580, 0.104867763817310330, 0.106881409883499150, 0.108908228576183320, 0.110952425748109820, 0.113017357885837550, +0.115105822682380680, 0.117219865322113040, 0.119361080229282380, 0.121530555188655850, 0.123729091137647630, 0.125957202166318890, 0.128215309232473370, 0.130503740161657330, +0.132822841405868530, 0.135173004120588300, 0.137554679065942760, 0.139968376606702800, 0.142414685338735580, 0.144894234836101530, 0.147407654672861100, 0.149955596774816510, +0.152538605034351350, 0.155157200992107390, 0.157811731100082400, 0.160502441227436070, 0.163229387253522870, 0.165992442518472670, 0.168791320174932480, 0.171625509858131410, +0.174494370818138120, 0.177397061139345170, 0.180332608520984650, 0.183299910277128220, 0.186297744512557980, 0.189324837177991870, 0.192379791289567950, 0.195461250841617580, +0.198567759245634080, 0.201697919517755510, 0.204850304871797560, 0.208023533225059510, 0.211216274648904800, 0.214427210390567780, 0.217655111104249950, 0.220898788422346120, +0.224157124757766720, 0.227429077029228210, 0.230713658034801480, 0.234009962528944020, 0.237317133694887160, 0.240634419023990630, 0.243961080908775330, 0.247296508401632310, +0.250640105456113820, 0.253991369158029560, 0.257349837571382520, 0.260715119540691380, 0.264086868613958360, 0.267464816570281980, 0.270848698914051060, 0.274238351732492450, +0.277633611112833020, 0.281034380197525020, 0.284440591931343080, 0.287852220237255100, 0.291269283741712570, 0.294691801071166990, 0.298119872808456420, 0.301553562283515930, +0.304993014782667160, 0.308438356965780260, 0.311889752745628360, 0.315347377210855480, 0.318811416625976560, 0.322282072156667710, 0.325759567320346830, 0.329244095832109450, +0.332735907286405560, 0.336235217750072480, 0.339742250740528110, 0.343257248401641850, 0.346780419349670410, 0.350311983376741410, 0.353852160274982450, 0.357401121407747270, +0.360959105193614960, 0.364526227116584780, 0.368102725595235820, 0.371688675135374070, 0.375284302979707720, 0.378889638930559160, 0.382504884153604510, 0.386130042374134060, +0.389765247702598570, 0.393410529941320420, 0.397065933793783190, 0.400731507688760760, 0.404407206922769550, 0.408093083649873730, 0.411789052188396450, 0.415495119988918300, +0.419211201369762420, 0.422937240451574330, 0.426673140376806260, 0.430418811738491060, 0.434174135327339170, 0.437938995659351350, 0.441713258624076840, 0.445496778935194020, +0.449289388954639430, 0.453090950846672060, 0.456901267170906070, 0.460720170289278030, 0.464547459036111830, 0.468382950872182850, 0.472226426005363460, 0.476077698171138760, +0.479936532676219940, 0.483802750706672670, 0.487676106393337250, 0.491556398570537570, 0.495443399995565410, 0.499336875975131990, 0.503236617892980580, 0.507142387330532070, +0.511053957045078280, 0.514971107244491580, 0.518893606960773470, 0.522821225225925450, 0.526753749698400500, 0.530690938234329220, 0.534632585942745210, 0.538578454405069350, +0.542528338730335240, 0.546481993049383160, 0.550439231097698210, 0.554399792104959490, 0.558363504707813260, 0.562330115586519240, 0.566299438476562500, 0.570271246135234830, +0.574245333671569820, 0.578221492469310760, 0.582199502736330030, 0.586179181933403020, 0.590160276740789410, 0.594142623245716090, 0.598125983029603960, 0.602110169827938080, +0.606094967573881150, 0.610080175101757050, 0.614065583795309070, 0.618050977587699890, 0.622036151587963100, 0.626020893454551700, 0.630004994571208950, 0.633988231420516970, +0.637970402836799620, 0.641951277852058410, 0.645930647850036620, 0.649908289313316350, 0.653883971273899080, 0.657857488840818410, 0.661828581243753430, 0.665797054767608640, +0.669762641191482540, 0.673725124448537830, 0.677684243768453600, 0.681639779359102250, 0.685591462999582290, 0.689539063721895220, 0.693482317030429840, 0.697420965880155560, +0.701354760676622390, 0.705283410847187040, 0.709206689149141310, 0.713124278932809830, 0.717035952955484390, 0.720941375941038130, 0.724840316921472550, 0.728732451796531680, +0.732617516070604320, 0.736495196819305420, 0.740365199744701390, 0.744227230548858640, 0.748080968856811520, 0.751926124095916750, 0.755762357264757160, 0.759589381515979770, +0.763406842947006230, 0.767214450985193250, 0.771011855453252790, 0.774798732250928880, 0.778574761003255840, 0.782339565455913540, 0.786092851310968400, 0.789834223687648770, +0.793563373386859890, 0.797279909253120420, 0.800983514636754990, 0.804673787206411360, 0.808350402861833570, 0.812012966722249980, 0.815661124885082240, 0.819294504821300510, +0.822912722826004030, 0.826515413820743560, 0.830102190375328060, 0.833672653883695600, 0.837226435542106630, 0.840763118118047710, 0.844282336533069610, 0.847783654928207400, +0.851266715675592420, 0.854731071740388870, 0.858176350593566890, 0.861602116376161580, 0.865007970482110980, 0.868393491953611370, 0.871758259832859040, 0.875101849436759950, +0.878423850983381270, 0.881723806262016300, 0.885001312941312790, 0.888255912810564040, 0.891487173736095430, 0.894694659858942030, 0.897877920418977740, 0.901036512106657030, +0.904169965535402300, 0.907277844846248630, 0.910359673202037810, 0.913415014743804930, 0.916443370282649990, 0.919444311410188670, 0.922417331486940380, 0.925361987203359600, +0.928277771919965740, 0.931164238601922990, 0.934020876884460450, 0.936847217381000520, 0.939642757177352910, 0.942407000809907910, 0.945139460265636440, 0.947839632630348210, +0.950507018715143200, 0.953141096979379650, 0.955741371959447860, 0.958307322114706040, 0.960838429629802700, 0.963334184139966960, 0.965794049203395840, 0.968217510730028150, +0.970604017376899720, 0.972953058779239650, 0.975264083594083790, 0.977536566555500030, 0.979769956320524220, 0.981963708996772770, 0.984117280691862110, 0.986230112612247470, +0.988301653414964680, 0.990331344306468960, 0.992318630218505860, 0.994262944906950000, 0.996163722127676010, 0.998020399361848830, 0.999832402914762500, 1.001599155366420700, +1.003320086747407900, 1.004994612187147100, 1.006622135639190700, 1.008202098309993700, 1.009733878076076500, 1.011216927319765100, 1.012650609016418500, 1.014034371823072400, +1.015367589890956900, 1.016649682074785200, 1.017880033701658200, 1.019058048725128200, 1.020183108747005500, 1.021254621446132700, 1.022271949797868700, 1.023234523832798000, + +}; +/* ---------------------------------------------------------------------- +** Test input - logarithmic chirp signal +** ------------------------------------------------------------------- */ + +float32_t testInput_f32[320] = + { + 0.000000000000000061, 0.002622410992047861, 0.005253663973466970, 0.007893770384930297, 0.010542741395035495, 0.013200587895525877, 0.015867320496454066, 0.018542949521290073, +0.021227485001971542, 0.023920936673895138, 0.026623313970853074, 0.029334626019908643, 0.032054881636210709, 0.034784089317753723, 0.037522257240071598, 0.040269393250875855, +0.043025504864628375, 0.045790599257054837, 0.048564683259595690, 0.051347763353792118, 0.054139845665610427, 0.056940935959702531, 0.059751039633601337, 0.062570161711849828, +0.065398306840066575, 0.068235479278943648, 0.071081682898178900, 0.073936921170339814, 0.076801197164660218, 0.079674513540768196, 0.082556872542344922, 0.085448275990715375, +0.088348725278367082, 0.091258221362398390, 0.094176764757897533, 0.097104355531246703, 0.100040993293358240, 0.102986677192832010, 0.105941405909045980, 0.108905177645166230, +0.111877990121087980, 0.114859840566297130, 0.117850725712659680, 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0.908824650189867690, 0.911507052394417540, 0.914160101029702910, 0.916783324324059180, +0.919376246902079860, 0.921938389791372770, 0.924469270430179120, 0.926968402675872660, 0.929435296814361430, 0.931869459570409790, 0.934270394118903560, 0.936637600097074200, +0.938970573617708970, 0.941268807283364040, 0.943531790201601380, 0.945759008001275100, 0.947949942849885320, 0.950104073472023970, 0.952220875168933280, 0.954299819839202090, +0.956340376000621160, 0.958342008813221960, 0.960304180103520260, 0.962226348389994210, 0.964107968909812760, 0.965948493646846980, 0.967747371360983650, 0.969504047618768740, +0.971217964825405680, 0.972888562258134030, 0.974515276101013520, 0.976097539481141750, 0.977634782506330400, 0.979126432304266880, 0.980571913063189360, 0.981970646074102120, +0.983322049774557390, 0.984625539794035220, 0.985880529000944810, 0.987086427551279730, 0.988242642938953360, 0.989348580047844540, 0.990403641205582440, 0.991407226239099710, +0.992358732531984260, 0.993257555083659870, 0.994103086570423680, 0.994894717408374870, 0.995631835818261310, 0.996313827892278070, 0.996940077662846650, 0.997509967173408010, + + }; diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c new file mode 100644 index 0000000..c263d18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c @@ -0,0 +1,411 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_graphic_equalizer_example_q31.c +* +* Description: Example showing an audio graphic equalizer constructed +* out of Biquad filters. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup GEQ5Band Graphic Audio Equalizer Example + * + * \par Description: + * \par + * This example demonstrates how a 5-band graphic equalizer can be constructed + * using the Biquad cascade functions. + * A graphic equalizer is used in audio applications to vary the tonal quality + * of the audio. + * + * \par Block Diagram: + * \par + * The design is based on a cascade of 5 filter sections. + * \image html GEQ_signalflow.gif + * Each filter section is 4th order and consists of a cascade of two Biquads. + * Each filter has a nominal gain of 0 dB (1.0 in linear units) and + * boosts or cuts signals within a specific frequency range. + * The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz. + * Each band has an adjustable boost or cut in the range of +/- 9 dB. + * For example, the band that extends from 500 to 2000 Hz has the response shown below: + * \par + * \image html GEQ_bandresponse.gif + * \par + * With 1 dB steps, each filter has a total of 19 different settings. + * The filter coefficients for all possible 19 settings were precomputed + * in MATLAB and stored in a table. With 5 different tables, there are + * a total of 5 x 19 = 95 different 4th order filters. + * All 95 responses are shown below: + * \par + * \image html GEQ_allbandresponse.gif + * \par + * Each 4th order filter has 10 coefficents for a grand total of 950 different filter + * coefficients that must be tabulated. The input and output data is in Q31 format. + * For better noise performance, the two low frequency bands are implemented using the high + * precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard + * 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp. + * \par + * \image html GEQ_inputchirp.gif + * \par + * The array bandGains specifies the gain in dB to apply in each band. + * For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be: + * \par + * \image html GEQ_outputchirp.gif + * \par + * \note The output chirp signal follows the gain or boost of each band. + * \par + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c testRefOutput_f32 points to the reference output data + * \li \c testOutput points to the test output data + * \li \c inputQ31 temporary input buffer + * \li \c outputQ31 temporary output buffer + * \li \c biquadStateBand1Q31 points to state buffer for band1 + * \li \c biquadStateBand2Q31 points to state buffer for band2 + * \li \c biquadStateBand3Q31 points to state buffer for band3 + * \li \c biquadStateBand4Q31 points to state buffer for band4 + * \li \c biquadStateBand5Q31 points to state buffer for band5 + * \li \c coeffTable points to coefficient buffer for all bands + * \li \c gainDB gain buffer which has gains applied for all the bands + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_biquad_cas_df1_32x64_init_q31() + * - arm_biquad_cas_df1_32x64_q31() + * - arm_biquad_cascade_df1_init_q31() + * - arm_biquad_cascade_df1_q31() + * - arm_scale_q31() + * - arm_scale_f32() + * - arm_float_to_q31() + * - arm_q31_to_float() + * + * Refer + * \link arm_graphic_equalizer_example_q31.c \endlink + * + */ + + +/** \example arm_graphic_equalizer_example_q31.c + */ + + +#include "arm_math.h" +#include "math_helper.h" + +/* Length of the overall data in the test */ +#define TESTLENGTH 320 + +/* Block size for the underlying processing */ +#define BLOCKSIZE 32 + +/* Total number of blocks to run */ +#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE) + +/* Number of 2nd order Biquad stages per filter */ +#define NUMSTAGES 2 + +#define SNR_THRESHOLD_F32 98 + +/* ------------------------------------------------------------------- + * External Declarations for Input and Output buffers + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32[TESTLENGTH]; +static float32_t testOutput[TESTLENGTH]; + +extern float32_t testRefOutput_f32[TESTLENGTH]; + +/* ---------------------------------------------------------------------- +** Q31 state buffers for Band1, Band2, Band3, Band4, Band5 +** ------------------------------------------------------------------- */ + +static q63_t biquadStateBand1Q31[4 * 2]; +static q63_t biquadStateBand2Q31[4 * 2]; +static q31_t biquadStateBand3Q31[4 * 2]; +static q31_t biquadStateBand4Q31[4 * 2]; +static q31_t biquadStateBand5Q31[4 * 2]; + +/* ---------------------------------------------------------------------- +** Q31 input and output buffers +** ------------------------------------------------------------------- */ + +q31_t inputQ31[BLOCKSIZE]; +q31_t outputQ31[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +** Entire coefficient table. There are 10 coefficients per 4th order Biquad +** cascade filter. The first 10 coefficients correspond to the -9 dB gain +** setting of band 1; the next 10 coefficient correspond to the -8 dB gain +** setting of band 1; and so on. There are 10*19=190 coefficients in total +** for band 1 (gains = -9, -8, -7, ..., 9). After this come the 190 coefficients +** for band 2. +** +** The coefficients are in Q29 format and require a postShift of 2. +** ------------------------------------------------------------------- */ + +const q31_t coeffTable[950] = { + + /* Band 1, -9 dB gain */ + 535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981, + /* Band 1, -8 dB gain */ + 535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778, + 535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686, + 536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972, + 536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897, + 536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716, + 536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676, + 536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017, + 536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975, + 536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777, + 537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648, + 537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803, + 537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454, + 537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806, + 537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059, + 537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409, + 537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045, + 538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151, + 538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907, + + /* Band 2, -9 dB gain */ + 531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367, + /* Band 2, -8 dB gain */ + 532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122, + 532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090, + 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------------------------------------------------------------------- */ + +int32_t main(void) +{ + float32_t *inputF32, *outputF32; + arm_biquad_cas_df1_32x64_ins_q31 S1; + arm_biquad_cas_df1_32x64_ins_q31 S2; + arm_biquad_casd_df1_inst_q31 S3; + arm_biquad_casd_df1_inst_q31 S4; + arm_biquad_casd_df1_inst_q31 S5; + int i; + int32_t status; + + inputF32 = &testInput_f32[0]; + outputF32 = &testOutput[0]; + + /* Initialize the state and coefficient buffers for all Biquad sections */ + + arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES, + (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)], + &biquadStateBand1Q31[0], 2); + + arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES, + (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)], + &biquadStateBand2Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES, + (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)], + &biquadStateBand3Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES, + (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)], + &biquadStateBand4Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES, + (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)], + &biquadStateBand5Q31[0], 2); + + + /* Call the process functions and needs to change filter coefficients + for varying the gain of each band */ + + for(i=0; i < NUMBLOCKS; i++) + { + + /* ---------------------------------------------------------------------- + ** Convert block of input data from float to Q31 + ** ------------------------------------------------------------------- */ + + arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale down by 1/8. This provides additional headroom so that the + ** graphic EQ can apply gain. + ** ------------------------------------------------------------------- */ + + arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2 + ** ------------------------------------------------------------------- */ + + arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5 + ** ------------------------------------------------------------------- */ + + arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Convert Q31 result back to float + ** ------------------------------------------------------------------- */ + + arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale back up + ** ------------------------------------------------------------------- */ + + arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + }; + + snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH); + + if (snr < SNR_THRESHOLD_F32) + { + status = ARM_MATH_TEST_FAILURE; + } + else + { + status = ARM_MATH_SUCCESS; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signal does not match the reference output. + ** ------------------------------------------------------------------- */ + + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + +/** \endlink */ + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c new file mode 100644 index 0000000..f615e6f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h new file mode 100644 index 0000000..5a18734 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt new file mode 100644 index 0000000..9062c48 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_linear_interp_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c new file mode 100644 index 0000000..309326e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c @@ -0,0 +1,23616 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_linear_interp_data.c +* +* Description: Data file used for example. Generation method described +* below +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Table generated from following MATLAB Command +* x = -pi: 0.00005 : (2*pi - 0.00005); +* y = sin(x); +* where pi value is 3.141592653589793 +* --------------------------------------------------------------------*/ + +float arm_linear_interep_table[188495] = { + + +-0.000000000000000122, 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@@ -0,0 +1,204 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_linear_interp_example_f32.c +* +* Description: Example code demonstrating usage of sin function +* and uses linear interpolation to get higher precision +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup LinearInterpExample Linear Interpolate Example + * + * CMSIS DSP Software Library -- Linear Interpolate Example + * + * Description + * This example demonstrates usage of linear interpolate modules and fast math modules. + * Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses + * linear interpolation function and results are compared to reference output. + * Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation. + * + * \par Block Diagram: + * \par + * \image html linearInterpExampleMethod1.gif "Method 1: Sine caluclation using fast math" + * \par + * \image html linearInterpExampleMethod2.gif "Method 2: Sine caluclation using interpolation function" + * + * \par Variables Description: + * \par + * \li \c testInputSin_f32 points to the input values for sine calculation + * \li \c testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function + * \li \c testOutput points to output buffer calculation from cubic interpolation + * \li \c testLinIntOutput points to output buffer calculation from linear interpolation + * \li \c snr1 Signal to noise ratio for reference and cubic interpolation output + * \li \c snr2 Signal to noise ratio for reference and linear interpolation output + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_sin_f32() + * - arm_linear_interp_f32() + * + * Refer + * \link arm_linear_interp_example_f32.c \endlink + * + */ + + +/** \example arm_linear_interp_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#define SNR_THRESHOLD 90 +#define TEST_LENGTH_SAMPLES 10 +#define XSPACING (0.00005f) + +/* ---------------------------------------------------------------------- +* Test input data for F32 SIN function +* Generated by the MATLAB rand() function +* randn('state', 0) +* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi)); +* --------------------------------------------------------------------*/ +float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] = +{ + -0.649716504673081170, -2.501723745497831200, + 0.188250329003310100, 0.432092748487532540, + -1.722010988459680800, 1.788766476323060600, + 1.786136060975809500, -0.056525543169408797, + 0.491596272728153760, 0.262309671126153390 +}; + +/*------------------------------------------------------------------------------ +* Reference out of SIN F32 function for Block Size = 10 +* Calculated from sin(testInputSin_f32) +*------------------------------------------------------------------------------*/ +float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] = +{ + -0.604960695383043530, -0.597090287967934840, + 0.187140422442966500, 0.418772124875992690, + -0.988588831792106880, 0.976338412038794010, + 0.976903856413481100, -0.056495446835214236, + 0.472033731854734240, 0.259311907228582830 +}; + +/*------------------------------------------------------------------------------ +* Method 1: Test out Buffer Calculated from Cubic Interpolation +*------------------------------------------------------------------------------*/ +float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* Method 2: Test out buffer Calculated from Linear Interpolation +*------------------------------------------------------------------------------*/ +float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* External table used for linear interpolation +*------------------------------------------------------------------------------*/ +extern float arm_linear_interep_table[188495]; + +/* ---------------------------------------------------------------------- +* Global Variables for caluclating SNR's for Method1 & Method 2 +* ------------------------------------------------------------------- */ +float32_t snr1; +float32_t snr2; + +/* ---------------------------------------------------------------------------- +* Calculation of Sine values from Cubic Interpolation and Linear interpolation +* ---------------------------------------------------------------------------- */ +int32_t main(void) +{ + uint32_t i; + arm_status status; + + arm_linear_interp_instance_f32 S = {188495, -3.141592653589793238, XSPACING, &arm_linear_interep_table[0]}; + + /*------------------------------------------------------------------------------ + * Method 1: Test out Calculated from Cubic Interpolation + *------------------------------------------------------------------------------*/ + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testOutput[i] = arm_sin_f32(testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation + *------------------------------------------------------------------------------*/ + + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * SNR calculation for method 1 + *------------------------------------------------------------------------------*/ + snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2); + + /*------------------------------------------------------------------------------ + * SNR calculation for method 2 + *------------------------------------------------------------------------------*/ + snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + if ( snr2 > snr1) + { + status = ARM_MATH_SUCCESS; + } + else + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c new file mode 100644 index 0000000..f615e6f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h new file mode 100644 index 0000000..5a18734 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt new file mode 100644 index 0000000..f45b0e0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_matrix_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c new file mode 100644 index 0000000..3d7a505 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c @@ -0,0 +1,233 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_matrix_example_f32.c +* +* Description: Example code demonstrating least square fit to data +* using matrix functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup MatrixExample Matrix Example + * + * \par Description: + * \par + * Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse + * functions to apply least squares fitting to input data. Least squares fitting is + * the procedure for finding the best-fitting curve that minimizes the sum of the + * squares of the offsets (least square error) from a given set of data. + * + * \par Algorithm: + * \par + * The linear combination of parameters considered is as follows: + * \par + * A * X = B, where \c X is the unknown value and can be estimated + * from \c A & \c B. + * \par + * The least squares estimate \c X is given by the following equation: + * \par + * X = Inverse(AT * A) * AT * B + * + * \par Block Diagram: + * \par + * \image html matrixExample.gif + * + * \par Variables Description: + * \par + * \li \c A_f32 input matrix in the linear combination equation + * \li \c B_f32 output matrix in the linear combination equation + * \li \c X_f32 unknown matrix estimated using \c A_f32 & \c B_f32 matrices + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_trans_f32() + * - arm_mat_mult_f32() + * - arm_mat_inverse_f32() + * + * Refer + * \link arm_matrix_example_f32.c \endlink + * + */ + + +/** \example arm_matrix_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#define SNR_THRESHOLD 90 + +/* -------------------------------------------------------------------------------- +* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize +* and tapSize +* --------------------------------------------------------------------------------- */ + +const float32_t B_f32[4] = +{ + 782.0, 7577.0, 470.0, 4505.0 +}; + +/* -------------------------------------------------------------------------------- +* Formula to fit is C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize +* -------------------------------------------------------------------------------- */ + +const float32_t A_f32[16] = +{ + /* Const, numTaps, blockSize, numTaps*blockSize */ + 1.0, 32.0, 4.0, 128.0, + 1.0, 32.0, 64.0, 2048.0, + 1.0, 16.0, 4.0, 64.0, + 1.0, 16.0, 64.0, 1024.0, +}; + + +/* ---------------------------------------------------------------------- +* Temporary buffers for storing intermediate values +* ------------------------------------------------------------------- */ +/* Transpose of A Buffer */ +float32_t AT_f32[16]; +/* (Transpose of A * A) Buffer */ +float32_t ATMA_f32[16]; +/* Inverse(Transpose of A * A) Buffer */ +float32_t ATMAI_f32[16]; +/* Test Output Buffer */ +float32_t X_f32[4]; + +/* ---------------------------------------------------------------------- +* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB +* ------------------------------------------------------------------- */ +const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}; + +float32_t snr; + + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_matrix_instance_f32 A; /* Matrix A Instance */ + arm_matrix_instance_f32 AT; /* Matrix AT(A transpose) instance */ + arm_matrix_instance_f32 ATMA; /* Matrix ATMA( AT multiply with A) instance */ + arm_matrix_instance_f32 ATMAI; /* Matrix ATMAI(Inverse of ATMA) instance */ + arm_matrix_instance_f32 B; /* Matrix B instance */ + arm_matrix_instance_f32 X; /* Matrix X(Unknown Matrix) instance */ + + uint32_t srcRows, srcColumns; /* Temporary variables */ + arm_status status; + + /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32); + + /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32); + + /* calculation of A transpose */ + status = arm_mat_trans_f32(&A, &AT); + + + /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32); + + /* calculation of AT Multiply with A */ + status = arm_mat_mult_f32(&AT, &A, &ATMA); + + /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32); + + /* calculation of Inverse((Transpose(A) * A) */ + status = arm_mat_inverse_f32(&ATMA, &ATMAI); + + /* calculation of (Inverse((Transpose(A) * A)) * Transpose(A)) */ + status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA); + + /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32); + + /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&X, srcRows, srcColumns, X_f32); + + /* calculation ((Inverse((Transpose(A) * A)) * Transpose(A)) * B) */ + status = arm_mat_mult_f32(&ATMA, &B, &X); + + /* Comparison of reference with test output */ + snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + if ( snr > SNR_THRESHOLD) + { + status = ARM_MATH_SUCCESS; + } + else + { + status = ARM_MATH_TEST_FAILURE; + } + + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c new file mode 100644 index 0000000..f615e6f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h new file mode 100644 index 0000000..5a18734 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt new file mode 100644 index 0000000..d202e78 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_signal_converge_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c new file mode 100644 index 0000000..3a2337d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c @@ -0,0 +1,269 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_signal_converge_data.c +* +* Description: Test input data for Floating point LMS Norm FIR filter +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input data for Floating point LMS Norm FIR filter +** Generated by the MATLAB randn() function +** ------------------------------------------------------------------- */ + +float32_t testInput_f32[1536] = +{ +-0.432565, -1.665584, 0.125332, 0.287676, -1.146471, 1.190915, 1.189164, -0.037633, +0.327292, 0.174639, -0.186709, 0.725791, -0.588317, 2.183186, -0.136396, 0.113931, +1.066768, 0.059281, -0.095648, -0.832349, 0.294411, -1.336182, 0.714325, 1.623562, +-0.691776, 0.857997, 1.254001, -1.593730, -1.440964, 0.571148, -0.399886, 0.689997, +0.815622, 0.711908, 1.290250, 0.668601, 1.190838, -1.202457, -0.019790, -0.156717, +-1.604086, 0.257304, -1.056473, 1.415141, -0.805090, 0.528743, 0.219321, -0.921902, +-2.170674, -0.059188, -1.010634, 0.614463, 0.507741, 1.692430, 0.591283, -0.643595, +0.380337, -1.009116, -0.019511, -0.048221, 0.000043, -0.317859, 1.095004, -1.873990, +0.428183, 0.895638, 0.730957, 0.577857, 0.040314, 0.677089, 0.568900, -0.255645, +-0.377469, -0.295887, -1.475135, -0.234004, 0.118445, 0.314809, 1.443508, -0.350975, +0.623234, 0.799049, 0.940890, -0.992092, 0.212035, 0.237882, -1.007763, -0.742045, +1.082295, -0.131500, 0.389880, 0.087987, -0.635465, -0.559573, 0.443653, -0.949904, +0.781182, 0.568961, -0.821714, -0.265607, -1.187777, -2.202321, 0.986337, -0.518635, +0.327368, 0.234057, 0.021466, -1.003944, -0.947146, -0.374429, -1.185886, -1.055903, +1.472480, 0.055744, -1.217317, -0.041227, -1.128344, -1.349278, -0.261102, 0.953465, +0.128644, 0.656468, -1.167819, -0.460605, -0.262440, -1.213152, -1.319437, 0.931218, +0.011245, -0.645146, 0.805729, 0.231626, -0.989760, 1.339586, 0.289502, 1.478917, +1.138028, -0.684139, -1.291936, -0.072926, -0.330599, -0.843628, 0.497770, 1.488490, +-0.546476, -0.846758, -0.246337, 0.663024, -0.854197, -1.201315, -0.119869, -0.065294, +0.485296, -0.595491, -0.149668, -0.434752, -0.079330, 1.535152, -0.606483, -1.347363, +0.469383, -0.903567, 0.035880, -0.627531, 0.535398, 0.552884, -0.203690, -2.054325, +0.132561, 1.592941, 1.018412, -1.580402, -0.078662, -0.681657, -1.024553, -1.234353, +0.288807, -0.429303, 0.055801, -0.367874, -0.464973, 0.370961, 0.728283, 2.112160, +-1.357298, -1.022610, 1.037834, -0.389800, -1.381266, 0.315543, 1.553243, 0.707894, +1.957385, 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-1.634939, -0.536325, 0.547223, 1.492603, -0.455243, -0.496416, 1.235260, +0.040926, 0.748467, 1.230764, 0.304903, 1.077771, 0.765151, -1.319580, -0.509191, +0.555116, -1.957625, -0.760453, -2.443886, -0.659366, -0.114779, 0.300079, -0.583996, +-3.073745, 1.551042, -0.407369, 1.428095, -1.353242, 0.903970, 0.541671, -0.465020 +}; + + + +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point LMS FIR filter +* FIR high pass filter with cutoff freq 9.6kHz (transition 9.6KHz to 11.52KHz) +** ------------------------------------------------------------------- */ +float32_t lmsNormCoeff_f32[32] = { +-0.004240, 0.002301, 0.008860, -0.000000, -0.019782, -0.010543, 0.032881, 0.034736, +-0.037374, -0.069586, 0.022397, 0.102169, 0.014185, -0.115908, -0.061648, 0.101018, +0.101018, -0.061648, -0.115908, 0.014185, 0.102169, 0.022397, -0.069586, -0.037374, +0.034736, 0.032881, -0.010543, -0.019782, -0.000000, 0.008860, 0.002301, -0.004240 + +}; + +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point FIR filter +* FIR low pass filter with cutoff freq 24Hz (transition 24Hz to 240Hz) +** ------------------------------------------------------------------- */ +const float32_t FIRCoeff_f32[32] = { +0.004502, 0.005074, 0.006707, 0.009356, 0.012933, 0.017303, 0.022298, 0.027717, +0.033338, 0.038930, 0.044258, 0.049098, 0.053243, 0.056519, 0.058784, 0.059941, +0.059941, 0.058784, 0.056519, 0.053243, 0.049098, 0.044258, 0.038930, 0.033338, +0.027717, 0.022298, 0.017303, 0.012933, 0.009356, 0.006707, 0.005074, 0.004502 + +}; + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c new file mode 100644 index 0000000..d984e2f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c @@ -0,0 +1,259 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_signal_converge_example_f32.c +* +* Description: Example code demonstrating convergence of an adaptive +* filter. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SignalConvergence Signal Convergence Example + * + * \par Description: + * \par + * Demonstrates the ability of an adaptive filter to "learn" the transfer function of + * a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse + * Response (FIR) Filter, and Basic Math Functions. + * + * \par Algorithm: + * \par + * The figure below illustrates the signal flow in this example. Uniformly distributed white + * noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the + * reference input of the adaptive filter (normalized LMS filter). The white noise is input + * to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter. + * The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and + * (2) the error signal which is the difference between the adaptive filter and the reference + * output of the FIR filter. Over time as the adaptive filter learns the transfer function + * of the FIR filter, the first output approaches the reference output of the FIR filter, + * and the error signal approaches zero. + * \par + * The adaptive filter converges properly even if the input signal has a large dynamic + * range (i.e., varies from small to large values). The coefficients of the adaptive filter + * are initially zero, and then converge over 1536 samples. The internal function test_signal_converge() + * implements the stopping condition. The function checks if all of the values of the error signal have a + * magnitude below a threshold DELTA. + * + * \par Block Diagram: + * \par + * \image html SignalFlow.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c firStateF32 points to FIR state buffer + * \li \c lmsStateF32 points to Normalised Least mean square FIR filter state buffer + * \li \c FIRCoeff_f32 points to coefficient buffer + * \li \c lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer + * \li \c wire1, wir2, wire3 temporary buffers + * \li \c errOutput, err_signal temporary error buffers + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_lms_norm_init_f32() + * - arm_fir_init_f32() + * - arm_fir_f32() + * - arm_lms_norm_f32() + * - arm_scale_f32() + * - arm_abs_f32() + * - arm_sub_f32() + * - arm_min_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_signal_converge_example_f32.c \endlink + * + */ + + +/** \example arm_signal_converge_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +** Global defines for the simulation +* ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 1536 +#define NUMTAPS 32 +#define BLOCKSIZE 32 +#define DELTA_ERROR 0.000001f +#define DELTA_COEFF 0.0001f +#define MU 0.5f + +#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE) + +/* ---------------------------------------------------------------------- +* Declare FIR state buffers and structure +* ------------------------------------------------------------------- */ + +float32_t firStateF32[NUMTAPS + BLOCKSIZE]; +arm_fir_instance_f32 LPF_instance; + +/* ---------------------------------------------------------------------- +* Declare LMSNorm state buffers and structure +* ------------------------------------------------------------------- */ + +float32_t lmsStateF32[NUMTAPS + BLOCKSIZE]; +float32_t errOutput[TEST_LENGTH_SAMPLES]; +arm_lms_norm_instance_f32 lmsNorm_instance; + + +/* ---------------------------------------------------------------------- +* Function Declarations for Signal Convergence Example +* ------------------------------------------------------------------- */ + +arm_status test_signal_converge_example( void ); + + +/* ---------------------------------------------------------------------- +* Internal functions +* ------------------------------------------------------------------- */ +arm_status test_signal_converge(float32_t* err_signal, + uint32_t blockSize); + +void getinput(float32_t* input, + uint32_t fr_cnt, + uint32_t blockSize); + +/* ---------------------------------------------------------------------- +* External Declarations for FIR F32 module Test +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32[TEST_LENGTH_SAMPLES]; +extern float32_t lmsNormCoeff_f32[32]; +extern const float32_t FIRCoeff_f32[32]; +extern arm_lms_norm_instance_f32 lmsNorm_instance; + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ + +float32_t wire1[BLOCKSIZE]; +float32_t wire2[BLOCKSIZE]; +float32_t wire3[BLOCKSIZE]; +float32_t err_signal[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Signal converge test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_status status; + uint32_t index; + float32_t minValue; + + /* Initialize the LMSNorm data structure */ + arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE); + + /* Initialize the FIR data structure */ + arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + * Loop over the frames of data and execute each of the processing + * functions in the system. + * ------------------------------------------------------------------- */ + + for(i=0; i < NUMFRAMES; i++) + { + /* Read the input data - uniformly distributed random noise - into wire1 */ + arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE); + + /* Execute the FIR processing function. Input wire1 and output wire2 */ + arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE); + + /* Execute the LMS Norm processing function*/ + + arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */ + wire1, /* Input signal */ + wire2, /* Reference Signal */ + wire3, /* Converged Signal */ + err_signal, /* Error Signal, this will become small as the signal converges */ + BLOCKSIZE); /* BlockSize */ + + /* apply overall gain */ + arm_scale_f32(wire3, 5, wire3, BLOCKSIZE); /* in-place buffer */ + } + + status = ARM_MATH_SUCCESS; + + /* ------------------------------------------------------------------------------- + * Test whether the error signal has reached towards 0. + * ----------------------------------------------------------------------------- */ + + arm_abs_f32(err_signal, err_signal, BLOCKSIZE); + arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index); + + if (minValue > DELTA_ERROR) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + * Test whether the filter coefficients have converged. + * ------------------------------------------------------------------- */ + + arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + + arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index); + + if (minValue > DELTA_COEFF) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + * Loop here if the signals did not pass the convergence check. + * This denotes a test failure + * ------------------------------------------------------------------- */ + + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c new file mode 100644 index 0000000..f615e6f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h new file mode 100644 index 0000000..5a18734 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt new file mode 100644 index 0000000..84bd3fd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_sin_cos_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c new file mode 100644 index 0000000..7e2eb00 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.3 +* +* Project: CMSIS DSP Library +* Title: arm_sin_cos_example_f32.c +* +* Description: Example code demonstrating sin and cos calculation of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SinCosExample SineCosine Example + * + * \par Description: + * \par + * Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector + * Multiplication, and Vector Addition functions. + * + * \par Algorithm: + * \par + * Mathematically, the Pythagorean trignometric identity is defined by the following equation: + * 
sin(x) * sin(x) + cos(x) * cos(x) = 1
+ * where \c x is the angle in radians. + * + * \par Block Diagram: + * \par + * \image html sinCos.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32 array of input angle in radians + * \li \c testOutput stores sum of the squares of sine and cosine values of input angle + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cos_f32() + * - arm_sin_f32() + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_sin_cos_example_f32.c \endlink + * + */ + + +/** \example arm_sin_cos_example_f32.c + */ + +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.0001f) + + +/* ---------------------------------------------------------------------- +* Test input data for Floating point sin_cos example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +const float32_t testInput_f32[MAX_BLOCKSIZE] = +{ + -1.244916875853235400, -4.793533929171324800, 0.360705030233248850, 0.827929644170887320, -3.299532218312426900, 3.427441903227623800, 3.422401784294607700, -0.108308165334010680, + 0.941943896490312180, 0.502609575000365850, -0.537345278736373500, 2.088817392965764500, -1.693168684143455700, 6.283185307179590700, -0.392545884746175080, 0.327893095115825040, + 3.070147440456292300, 0.170611405884662230, -0.275275082396073010, -2.395492805446796300, 0.847311163536506600, -3.845517018083148800, 2.055818378415868300, 4.672594161978930800, + -1.990923030266425800, 2.469305197656249500, 3.609002606064021000, -4.586736582331667500, -4.147080139136136300, 1.643756718868359500, -1.150866392366494800, 1.985805026477433800 + + +}; + +const float32_t testRefOutput_f32 = 1.000000000; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t testOutput; +float32_t cosOutput; +float32_t sinOutput; +float32_t cosSquareOutput; +float32_t sinSquareOutput; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +arm_status status; + +int32_t main(void) +{ + float32_t diff; + uint32_t i; + + for(i=0; i< blockSize; i++) + { + cosOutput = arm_cos_f32(testInput_f32[i]); + sinOutput = arm_sin_f32(testInput_f32[i]); + + arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1); + arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1); + + arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(testRefOutput_f32 - testOutput); + + /* Comparison of sin_cos value with reference */ + if (diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + if ( status == ARM_MATH_TEST_FAILURE) + { + while (1); + } + + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt new file mode 100644 index 0000000..4dc03b8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_variance_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c new file mode 100644 index 0000000..78a0681 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c @@ -0,0 +1,204 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_variance_example_f32.c +* +* Description: Example code demonstrating variance calculation of input sequence. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup VarianceExample Variance Example + * + * \par Description: + * \par + * Demonstrates the use of Basic Math and Support Functions to calculate the variance of an + * input sequence with N samples. Uniformly distributed white noise is taken as input. + * + * \par Algorithm: + * \par + * The variance of a sequence is the mean of the squared deviation of the sequence from its mean. + * \par + * This is denoted by the following equation: + * 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
+ * where, x[n] is the input sequence, N is the number of input samples, and + * x' is the mean value of the input sequence, x[n]. + * \par + * The mean value x' is defined as: + * 
 x' = (x[0] + x[1] + ... + x[n-1]) / N
+ * + * \par Block Diagram: + * \par + * \image html Variance.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c wire1, \c wir2, \c wire3 temporary buffers + * \li \c blockSize number of samples processed at a time + * \li \c refVarianceOut reference variance value + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_dot_prod_f32() + * - arm_mult_f32() + * - arm_sub_f32() + * - arm_fill_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_variance_example_f32.c \endlink + * + */ + + +/** \example arm_variance_example_f32.c + */ +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t wire1[MAX_BLOCKSIZE]; +float32_t wire2[MAX_BLOCKSIZE]; +float32_t wire3[MAX_BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Variance example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +float32_t testInput_f32[32] = +{ + -0.432564811528221, -1.665584378238097, 0.125332306474831, 0.287676420358549, + -1.146471350681464, 1.190915465642999, 1.189164201652103, -0.037633276593318, + 0.327292361408654, 0.174639142820925, -0.186708577681439, 0.725790548293303, + -0.588316543014189, 2.183185818197101, -0.136395883086596, 0.113931313520810, + 1.066768211359189, 0.059281460523605, -0.095648405483669, -0.832349463650022, + 0.294410816392640, -1.336181857937804, 0.714324551818952, 1.623562064446271, + -0.691775701702287, 0.857996672828263, 1.254001421602532, -1.593729576447477, + -1.440964431901020, 0.571147623658178, -0.399885577715363, 0.689997375464345 + +}; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t refVarianceOut = 0.903941793931839; + +/* ---------------------------------------------------------------------- +* Variance calculation test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + arm_status status; + float32_t mean, oneByBlockSize; + float32_t variance; + float32_t diff; + + status = ARM_MATH_SUCCESS; + + /* Calculation of mean value of input */ + + /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + + /* Fill wire1 buffer with 1.0 value */ + arm_fill_f32(1.0, wire1, blockSize); + + /* Calculate the dot product of wire1 and wire2 */ + /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */ + arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize); + + /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + arm_mult_f32(&mean, &oneByBlockSize, &mean, 1); + + + /* Calculation of variance value of input */ + + /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + + /* Fill wire2 with mean value x' */ + arm_fill_f32(mean, wire2, blockSize); + + /* wire3 contains (x-x') */ + arm_sub_f32(testInput_f32, wire2, wire3, blockSize); + + /* wire2 contains (x-x') */ + arm_copy_f32(wire3, wire2, blockSize); + + /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + arm_dot_prod_f32(wire2, wire3, blockSize, &variance); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize - 1); + + /* Calculation of variance */ + arm_mult_f32(&variance, &oneByBlockSize, &variance, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(refVarianceOut - variance); + + /* Comparison of variance value with reference */ + if (diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Include/arm_common_tables.h b/Drivers/CMSIS/DSP/Include/arm_common_tables.h new file mode 100644 index 0000000..233f623 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/Drivers/CMSIS/DSP/Include/arm_const_structs.h b/Drivers/CMSIS/DSP/Include/arm_const_structs.h new file mode 100644 index 0000000..677073e --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/Drivers/CMSIS/DSP/Include/arm_math.h b/Drivers/CMSIS/DSP/Include/arm_math.h new file mode 100644 index 0000000..997aeae --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c new file mode 100644 index 0000000..69b2bfc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c @@ -0,0 +1,153 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_f32.c + * Description: Floating-point vector absolute value + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicAbs Vector Absolute Value + * + * Computes the absolute value of a vector on an element-by-element basis. + * + * 
+ *     pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.
+ *
+ * + * The functions support in-place computation allowing the source and + * destination pointers to reference the same memory buffer. + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t in1, in2, in3, in4; /* temporary variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = |A| */ + /* Calculate absolute and then store the results in the destination buffer. */ + /* read sample from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + + /* find absolute value */ + in1 = fabsf(in1); + + /* read sample from source */ + in4 = *(pSrc + 3); + + /* find absolute value */ + in2 = fabsf(in2); + + /* read sample from source */ + *pDst = in1; + + /* find absolute value */ + in3 = fabsf(in3); + + /* find absolute value */ + in4 = fabsf(in4); + + /* store result to destination */ + *(pDst + 1) = in2; + + /* store result to destination */ + *(pDst + 2) = in3; + + /* store result to destination */ + *(pDst + 3) = in4; + + + /* Update source pointer to process next sampels */ + pSrc += 4U; + + /* Update destination pointer to process next sampels */ + pDst += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + /* Calculate absolute and then store the results in the destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c new file mode 100644 index 0000000..4bed8cc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c @@ -0,0 +1,167 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q15.c + * Description: Q15 vector absolute value + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *simd; + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1; /* Input value1 */ + q15_t in2; /* Input value2 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + simd = __SIMD32_CONST(pDst); + while (blkCnt > 0U) + { + /* C = |A| */ + /* Read two inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + + + /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */ +#ifndef ARM_MATH_BIG_ENDIAN + *simd++ = + __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), + ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16); + +#else + + + *simd++ = + __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), + ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + + +#ifndef ARM_MATH_BIG_ENDIAN + + *simd++ = + __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), + ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16); + +#else + + + *simd++ = + __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), + ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + pDst = (q15_t *)simd; + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = |A| */ + /* Read the input */ + in1 = *pSrc++; + + /* Calculate absolute value of input and then store the result in the destination buffer. */ + *pDst++ = (in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + q15_t in; /* Temporary input variable */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = |A| */ + /* Read the input */ + in = *pSrc++; + + /* Calculate absolute value of input and then store the result in the destination buffer. */ + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + * @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c new file mode 100644 index 0000000..25cd036 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q31.c + * Description: Q31 vector absolute value + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + + +/** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + q31_t in; /* Input value */ + +#if defined (ARM_MATH_DSP) + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t in1, in2, in3, in4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = |A| */ + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + *pDst++ = (in1 > 0) ? in1 : (q31_t)__QSUB(0, in1); + *pDst++ = (in2 > 0) ? in2 : (q31_t)__QSUB(0, in2); + *pDst++ = (in3 > 0) ? in3 : (q31_t)__QSUB(0, in3); + *pDst++ = (in4 > 0) ? in4 : (q31_t)__QSUB(0, in4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c new file mode 100644 index 0000000..1ab2a1c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q7.c + * Description: Q7 vector absolute value + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * \par Conditions for optimum performance + * Input and output buffers should be aligned by 32-bit + * + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + q7_t in; /* Input value1 */ + +#if defined (ARM_MATH_DSP) + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t in1, in2, in3, in4; /* temporary input variables */ + q31_t out1, out2, out3, out4; /* temporary output variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = |A| */ + /* Read inputs */ + in1 = (q31_t) * pSrc; + in2 = (q31_t) * (pSrc + 1); + in3 = (q31_t) * (pSrc + 2); + + /* find absolute value */ + out1 = (in1 > 0) ? in1 : (q31_t)__QSUB8(0, in1); + + /* read input */ + in4 = (q31_t) * (pSrc + 3); + + /* find absolute value */ + out2 = (in2 > 0) ? in2 : (q31_t)__QSUB8(0, in2); + + /* store result to destination */ + *pDst = (q7_t) out1; + + /* find absolute value */ + out3 = (in3 > 0) ? in3 : (q31_t)__QSUB8(0, in3); + + /* find absolute value */ + out4 = (in4 > 0) ? in4 : (q31_t)__QSUB8(0, in4); + + /* store result to destination */ + *(pDst + 1) = (q7_t) out2; + + /* store result to destination */ + *(pDst + 2) = (q7_t) out3; + + /* store result to destination */ + *(pDst + 3) = (q7_t) out4; + + /* update pointers to process next samples */ + pSrc += 4U; + pDst += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; +#else + + /* Run the below code for Cortex-M0 */ + blkCnt = blockSize; + +#endif /* #define ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0U) + { + /* C = |A| */ + /* Read the input */ + in = *pSrc++; + + /* Store the Absolute result in the destination buffer */ + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? 0x7f : -in); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c new file mode 100644 index 0000000..4d1ac4d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_f32.c + * Description: Floating-point vector addition + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicAdd Vector Addition + * + * Element-by-element addition of two vectors. + * + * 
+ *     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */ + float32_t inB1, inB2, inB3, inB4; /* temporary input variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + + /* read four inputs from sourceA and four inputs from sourceB */ + inA1 = *pSrcA; + inB1 = *pSrcB; + inA2 = *(pSrcA + 1); + inB2 = *(pSrcB + 1); + inA3 = *(pSrcA + 2); + inB3 = *(pSrcB + 2); + inA4 = *(pSrcA + 3); + inB4 = *(pSrcB + 3); + + /* C = A + B */ + /* add and store result to destination */ + *pDst = inA1 + inB1; + *(pDst + 1) = inA2 + inB2; + *(pDst + 2) = inA3 + inB3; + *(pDst + 3) = inA4 + inB4; + + /* update pointers to process next samples */ + pSrcA += 4U; + pSrcB += 4U; + pDst += 4U; + + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c new file mode 100644 index 0000000..2a14c29 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q15.c + * Description: Q15 vector addition + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inB1, inB2; + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + inA1 = *__SIMD32(pSrcA)++; + inA2 = *__SIMD32(pSrcA)++; + inB1 = *__SIMD32(pSrcB)++; + inB2 = *__SIMD32(pSrcB)++; + + *__SIMD32(pDst)++ = __QADD16(inA1, inB1); + *__SIMD32(pDst)++ = __QADD16(inA2, inB2); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + +} + +/** + * @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c new file mode 100644 index 0000000..7503e1a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q31.c + * Description: Q31 vector addition + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + + +/** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inA3, inA4; + q31_t inB1, inB2, inB3, inB4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + inA1 = *pSrcA++; + inA2 = *pSrcA++; + inB1 = *pSrcB++; + inB2 = *pSrcB++; + + inA3 = *pSrcA++; + inA4 = *pSrcA++; + inB3 = *pSrcB++; + inB4 = *pSrcB++; + + *pDst++ = __QADD(inA1, inB1); + *pDst++ = __QADD(inA2, inB2); + *pDst++ = __QADD(inA3, inB3); + *pDst++ = __QADD(inA4, inB4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + * @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c new file mode 100644 index 0000000..fee1865 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q7.c + * Description: Q7 vector addition + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + +} + +/** + * @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c new file mode 100644 index 0000000..6c7aae1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_f32.c + * Description: Floating-point dot product + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup dot_prod Vector Dot Product + * + * Computes the dot product of two vectors. + * The vectors are multiplied element-by-element and then summed. + * + * 
+ *     sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + +void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ + float32_t sum = 0.0f; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer */ + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + /* Store the result back in the destination buffer */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c new file mode 100644 index 0000000..6a48242 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q15.c + * Description: Q15 dot product + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these + * results are added to a 64-bit accumulator in 34.30 format. + * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator + * there is no risk of overflow. + * The return result is in 34.30 format. + */ + +void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + q63_t sum = 0; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); + sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the results in a temporary buffer. */ + sum = __SMLALD(*pSrcA++, *pSrcB++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the results in a temporary buffer. */ + sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Store the result in the destination buffer in 34.30 format */ + *result = sum; + +} + +/** + * @} end of dot_prod group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c new file mode 100644 index 0000000..e739879 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q31.c + * Description: Q31 dot product + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these + * are truncated to 2.48 format by discarding the lower 14 bits. + * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + * There are 15 guard bits in the accumulator and there is no risk of overflow as long as + * the length of the vectors is less than 2^16 elements. + * The return result is in 16.48 format. + */ + +void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + q63_t sum = 0; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inA3, inA4; + q31_t inB1, inB2, inB3, inB4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + inA1 = *pSrcA++; + inA2 = *pSrcA++; + inA3 = *pSrcA++; + inA4 = *pSrcA++; + inB1 = *pSrcB++; + inB2 = *pSrcB++; + inB3 = *pSrcB++; + inB4 = *pSrcB++; + + sum += ((q63_t) inA1 * inB1) >> 14U; + sum += ((q63_t) inA2 * inB2) >> 14U; + sum += ((q63_t) inA3 * inB3) >> 14U; + sum += ((q63_t) inA4 * inB4) >> 14U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the result in the destination buffer in 16.48 format */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c new file mode 100644 index 0000000..ef08038 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q7.c + * Description: Q7 dot product + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these + * results are added to an accumulator in 18.14 format. + * Nonsaturating additions are used and there is no danger of wrap around as long as + * the vectors are less than 2^18 elements long. + * The return result is in 18.14 format. + */ + +void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ + uint32_t blkCnt; /* loop counter */ + + q31_t sum = 0; /* Temporary variables to store output */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q31_t input1, input2; /* Temporary variables to store input */ + q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */ + + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* read 4 samples at a time from sourceA */ + input1 = *__SIMD32(pSrcA)++; + /* read 4 samples at a time from sourceB */ + input2 = *__SIMD32(pSrcB)++; + + /* extract two q7_t samples to q15_t samples */ + inA1 = __SXTB16(__ROR(input1, 8)); + /* extract reminaing two samples */ + inA2 = __SXTB16(input1); + /* extract two q7_t samples to q15_t samples */ + inB1 = __SXTB16(__ROR(input2, 8)); + /* extract reminaing two samples */ + inB2 = __SXTB16(input2); + + /* multiply and accumulate two samples at a time */ + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Dot product and then store the results in a temporary buffer. */ + sum = __SMLAD(*pSrcA++, *pSrcB++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Dot product and then store the results in a temporary buffer. */ + sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + + /* Store the result in the destination buffer in 18.14 format */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c new file mode 100644 index 0000000..334e32b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_f32.c + * Description: Floating-point vector multiplication + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicMult Vector Multiplication + * + * Element-by-element multiplication of two vectors. + * + * 
+ *     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ +#if defined (ARM_MATH_DSP) + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t inA1, inA2, inA3, inA4; /* temporary input variables */ + float32_t inB1, inB2, inB3, inB4; /* temporary input variables */ + float32_t out1, out2, out3, out4; /* temporary output variables */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the results in output buffer */ + /* read sample from sourceA */ + inA1 = *pSrcA; + /* read sample from sourceB */ + inB1 = *pSrcB; + /* read sample from sourceA */ + inA2 = *(pSrcA + 1); + /* read sample from sourceB */ + inB2 = *(pSrcB + 1); + + /* out = sourceA * sourceB */ + out1 = inA1 * inB1; + + /* read sample from sourceA */ + inA3 = *(pSrcA + 2); + /* read sample from sourceB */ + inB3 = *(pSrcB + 2); + + /* out = sourceA * sourceB */ + out2 = inA2 * inB2; + + /* read sample from sourceA */ + inA4 = *(pSrcA + 3); + + /* store result to destination buffer */ + *pDst = out1; + + /* read sample from sourceB */ + inB4 = *(pSrcB + 3); + + /* out = sourceA * sourceB */ + out3 = inA3 * inB3; + + /* store result to destination buffer */ + *(pDst + 1) = out2; + + /* out = sourceA * sourceB */ + out4 = inA4 * inB4; + /* store result to destination buffer */ + *(pDst + 2) = out3; + /* store result to destination buffer */ + *(pDst + 3) = out4; + + + /* update pointers to process next samples */ + pSrcA += 4U; + pSrcB += 4U; + pDst += 4U; + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the results in output buffer */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c new file mode 100644 index 0000000..f3039d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c @@ -0,0 +1,142 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q15.c + * Description: Q15 vector multiplication + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + + +/** + * @brief Q15 vector multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inB1, inB2; /* temporary input variables */ + q15_t out1, out2, out3, out4; /* temporary output variables */ + q31_t mul1, mul2, mul3, mul4; /* temporary variables */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* read two samples at a time from sourceA */ + inA1 = *__SIMD32(pSrcA)++; + /* read two samples at a time from sourceB */ + inB1 = *__SIMD32(pSrcB)++; + /* read two samples at a time from sourceA */ + inA2 = *__SIMD32(pSrcA)++; + /* read two samples at a time from sourceB */ + inB2 = *__SIMD32(pSrcB)++; + + /* multiply mul = sourceA * sourceB */ + mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); + mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2); + + /* saturate result to 16 bit */ + out1 = (q15_t) __SSAT(mul1 >> 15, 16); + out2 = (q15_t) __SSAT(mul2 >> 15, 16); + out3 = (q15_t) __SSAT(mul3 >> 15, 16); + out4 = (q15_t) __SSAT(mul4 >> 15, 16); + + /* store the result */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); + *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); + *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c new file mode 100644 index 0000000..93f0c73 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q31.c + * Description: Q31 vector multiplication + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inA3, inA4; /* temporary input variables */ + q31_t inB1, inB2, inB3, inB4; /* temporary input variables */ + q31_t out1, out2, out3, out4; /* temporary output variables */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and then store the results in the destination buffer. */ + inA1 = *pSrcA++; + inA2 = *pSrcA++; + inA3 = *pSrcA++; + inA4 = *pSrcA++; + inB1 = *pSrcB++; + inB2 = *pSrcB++; + inB3 = *pSrcB++; + inB4 = *pSrcB++; + + out1 = ((q63_t) inA1 * inB1) >> 32; + out2 = ((q63_t) inA2 * inB2) >> 32; + out3 = ((q63_t) inA3 * inB3) >> 32; + out4 = ((q63_t) inA4 * inB4) >> 32; + + out1 = __SSAT(out1, 31); + out2 = __SSAT(out2, 31); + out3 = __SSAT(out3, 31); + out4 = __SSAT(out4, 31); + + *pDst++ = out1 << 1U; + *pDst++ = out2 << 1U; + *pDst++ = out3 << 1U; + *pDst++ = out4 << 1U; + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and then store the results in the destination buffer. */ + inA1 = *pSrcA++; + inB1 = *pSrcB++; + out1 = ((q63_t) inA1 * inB1) >> 32; + out1 = __SSAT(out1, 31); + *pDst++ = out1 << 1U; + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and then store the results in the destination buffer. */ + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ +} + +/** + * @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c new file mode 100644 index 0000000..e5a8f24 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c @@ -0,0 +1,115 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q7.c + * Description: Q7 vector multiplication + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Q7 vector multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t out1, out2, out3, out4; /* Temporary variables to store the product */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the results in temporary variables */ + out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Store the results of 4 inputs in the destination buffer in single cycle by packing */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c new file mode 100644 index 0000000..d463885 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_f32.c + * Description: Negates floating-point vectors + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup negate Vector Negate + * + * Negates the elements of a vector. + * + * 
+ *     pDst[n] = -pSrc[n],   0 <= n < blockSize.
+ *
+ * + * The functions support in-place computation allowing the source and + * destination pointers to reference the same memory buffer. + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t in1, in2, in3, in4; /* temporary variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* read inputs from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + /* negate the input */ + in1 = -in1; + in2 = -in2; + in3 = -in3; + in4 = -in4; + + /* store the result to destination */ + *pDst = in1; + *(pDst + 1) = in2; + *(pDst + 2) = in3; + *(pDst + 3) = in4; + + /* update pointers to process next samples */ + pSrc += 4U; + pDst += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c new file mode 100644 index 0000000..0820f30 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q15.c + * Description: Negates Q15 vectors + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * \par Conditions for optimum performance + * Input and output buffers should be aligned by 32-bit + * + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + q15_t in; + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q31_t in1, in2; /* Temporary variables */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = -A */ + /* Read two inputs at a time */ + in1 = _SIMD32_OFFSET(pSrc); + in2 = _SIMD32_OFFSET(pSrc + 2); + + /* negate two samples at a time */ + in1 = __QSUB16(0, in1); + + /* negate two samples at a time */ + in2 = __QSUB16(0, in2); + + /* store the result to destination 2 samples at a time */ + _SIMD32_OFFSET(pDst) = in1; + /* store the result to destination 2 samples at a time */ + _SIMD32_OFFSET(pDst + 2) = in2; + + + /* update pointers to process next samples */ + pSrc += 4U; + pDst += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = -A */ + /* Negate and then store the result in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c new file mode 100644 index 0000000..ab5985a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q31.c + * Description: Negates Q31 vectors + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t in; /* Temporary variable */ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t in1, in2, in3, in4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + *pDst++ = __QSUB(0, in1); + *pDst++ = __QSUB(0, in2); + *pDst++ = __QSUB(0, in3); + *pDst++ = __QSUB(0, in4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = -A */ + /* Negate and then store the result in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c new file mode 100644 index 0000000..b225c5e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c @@ -0,0 +1,113 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q7.c + * Description: Negates Q7 vectors + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + q7_t in; + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t input; /* Input values1-4 */ + q31_t zero = 0x00000000; + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = -A */ + /* Read four inputs */ + input = *__SIMD32(pSrc)++; + + /* Store the Negated results in the destination buffer in a single cycle by packing the results */ + *__SIMD32(pDst)++ = __QSUB8(zero, input); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ \ + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? 0x7f : -in; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c new file mode 100644 index 0000000..c35fe8e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_f32.c + * Description: Floating-point vector offset + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup offset Vector Offset + * + * Adds a constant offset to each element of a vector. + * + * 
+ *     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.
+ *
+ * + * The functions support in-place computation allowing the source and + * destination pointers to reference the same memory buffer. + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + +void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t in1, in2, in3, in4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + /* read samples from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + + /* add offset to input */ + in1 = in1 + offset; + + /* read samples from source */ + in3 = *(pSrc + 2); + + /* add offset to input */ + in2 = in2 + offset; + + /* read samples from source */ + in4 = *(pSrc + 3); + + /* add offset to input */ + in3 = in3 + offset; + + /* store result to destination */ + *pDst = in1; + + /* add offset to input */ + in4 = in4 + offset; + + /* store result to destination */ + *(pDst + 1) = in2; + + /* store result to destination */ + *(pDst + 2) = in3; + + /* store result to destination */ + *(pDst + 3) = in4; + + /* update pointers to process next samples */ + pSrc += 4U; + pDst += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of offset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c new file mode 100644 index 0000000..4c16224 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q15.c + * Description: Q15 vector offset + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t offset_packed; /* Offset packed to 32 bit */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PKHBT(offset, offset, 16); + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer, 2 samples at a time. */ + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __QADD16(*pSrc++, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + * @} end of offset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c new file mode 100644 index 0000000..0b0ee32 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q31.c + * Description: Q31 vector offset + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t in1, in2, in3, in4; + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + *pDst++ = __QADD(in1, offset); + *pDst++ = __QADD(in2, offset); + *pDst++ = __QADD(in3, offset); + *pDst++ = __QADD(in4, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = __QADD(*pSrc++, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + * @} end of offset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c new file mode 100644 index 0000000..5b98951 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q7.c + * Description: Q7 vector offset + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t offset_packed; /* Offset packed to 32 bit */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PACKq7(offset, offset, offset, offset); + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */ + *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + * @} end of offset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c new file mode 100644 index 0000000..0fc3204 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c @@ -0,0 +1,157 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_f32.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup scale Vector Scale + * + * Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + * + * 
+ *     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.
+ *
+ * + * In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + * a fractional multiplication scaleFract and an arithmetic shift shift. + * The shift allows the gain of the scaling operation to exceed 1.0. + * The algorithm used with fixed-point data is: + * + * 
+ *     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.
+ *
+ * + * The overall scale factor applied to the fixed-point data is + * 
+ *     scale = scaleFract * 2^shift.
+ *
+ * + * The functions support in-place computation allowing the source and destination + * pointers to reference the same memory buffer. + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + +void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t in1, in2, in3, in4; /* temporary variabels */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A * scale */ + /* Scale the input and then store the results in the destination buffer. */ + /* read input samples from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + + /* multiply with scaling factor */ + in1 = in1 * scale; + + /* read input sample from source */ + in3 = *(pSrc + 2); + + /* multiply with scaling factor */ + in2 = in2 * scale; + + /* read input sample from source */ + in4 = *(pSrc + 3); + + /* multiply with scaling factor */ + in3 = in3 * scale; + in4 = in4 * scale; + /* store the result to destination */ + *pDst = in1; + *(pDst + 1) = in2; + *(pDst + 2) = in3; + *(pDst + 3) = in4; + + /* update pointers to process next samples */ + pSrc += 4U; + pDst += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of scale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c new file mode 100644 index 0000000..f1d3063 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c @@ -0,0 +1,150 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q15.c + * Description: Multiplies a Q15 vector by a scalar + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.15 format. + * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ + + +void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = 15 - shift; /* shift to apply after scaling */ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q15_t in1, in2, in3, in4; + q31_t inA1, inA2; /* Temporary variables */ + q31_t out1, out2, out3, out4; + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* Reading 2 inputs from memory */ + inA1 = *__SIMD32(pSrc)++; + inA2 = *__SIMD32(pSrc)++; + + /* C = A * scale */ + /* Scale the inputs and then store the 2 results in the destination buffer + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) inA1 * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) inA2 * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store the result to destination */ + *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16); + *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + * @} end of scale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c new file mode 100644 index 0000000..dcc7bbe --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c @@ -0,0 +1,227 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q31.c + * Description: Multiplies a Q31 vector by a scalar + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.31 format. + * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. + */ + +void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = shift + 1; /* Shift to apply after scaling */ + int8_t sign = (kShift & 0x80); + uint32_t blkCnt; /* loop counter */ + q31_t in, out; + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q31_t in1, in2, in3, in4; /* temporary input variables */ + q31_t out1, out2, out3, out4; /* temporary output variabels */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + if (sign == 0U) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* read four inputs from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + /* multiply input with scaler value */ + in1 = ((q63_t) in1 * scaleFract) >> 32; + in2 = ((q63_t) in2 * scaleFract) >> 32; + in3 = ((q63_t) in3 * scaleFract) >> 32; + in4 = ((q63_t) in4 * scaleFract) >> 32; + + /* apply shifting */ + out1 = in1 << kShift; + out2 = in2 << kShift; + + /* saturate the results. */ + if (in1 != (out1 >> kShift)) + out1 = 0x7FFFFFFF ^ (in1 >> 31); + + if (in2 != (out2 >> kShift)) + out2 = 0x7FFFFFFF ^ (in2 >> 31); + + out3 = in3 << kShift; + out4 = in4 << kShift; + + *pDst = out1; + *(pDst + 1) = out2; + + if (in3 != (out3 >> kShift)) + out3 = 0x7FFFFFFF ^ (in3 >> 31); + + if (in4 != (out4 >> kShift)) + out4 = 0x7FFFFFFF ^ (in4 >> 31); + + /* Store result destination */ + *(pDst + 2) = out3; + *(pDst + 3) = out4; + + /* Update pointers to process next sampels */ + pSrc += 4U; + pDst += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + } + else + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* read four inputs from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + /* multiply input with scaler value */ + in1 = ((q63_t) in1 * scaleFract) >> 32; + in2 = ((q63_t) in2 * scaleFract) >> 32; + in3 = ((q63_t) in3 * scaleFract) >> 32; + in4 = ((q63_t) in4 * scaleFract) >> 32; + + /* apply shifting */ + out1 = in1 >> -kShift; + out2 = in2 >> -kShift; + + out3 = in3 >> -kShift; + out4 = in4 >> -kShift; + + /* Store result destination */ + *pDst = out1; + *(pDst + 1) = out2; + + *(pDst + 2) = out3; + *(pDst + 3) = out4; + + /* Update pointers to process next sampels */ + pSrc += 4U; + pDst += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + } + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + if (sign == 0) + { + while (blkCnt > 0U) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + + out = in << kShift; + + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + + *pDst++ = out; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + + out = in >> -kShift; + + *pDst++ = out; + + /* Decrement the loop counter */ + blkCnt--; + } + + } +} + +/** + * @} end of scale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c new file mode 100644 index 0000000..8c90396 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q7.c + * Description: Multiplies a Q7 vector by a scalar + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.7 format. + * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. + */ + +void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = 7 - shift; /* shift to apply after scaling */ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* Reading 4 inputs from memory */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* C = A * scale */ + /* Scale the inputs and then store the results in the temporary variables. */ + out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8)); + out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8)); + out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8)); + out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8)); + + /* Packing the individual outputs into 32bit and storing in + * destination buffer in single write */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + * @} end of scale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c new file mode 100644 index 0000000..9462ad7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c @@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q15.c + * Description: Shifts the elements of a Q15 vector by a specified number of bits + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup shift + * @{ + */ + +/** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign; /* Sign of shiftBits */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1, in2; /* Temporary variables */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* Read 2 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + /* C = A << shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), + __SSAT((in2 << shiftBits), 16), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), + __SSAT((in1 << shiftBits), 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), + __SSAT((in2 << shiftBits), 16), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), + __SSAT((in1 << shiftBits), 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + /* Shift and then store the results in the destination buffer. */ + *pDst++ = __SSAT((*pSrc++ << shiftBits), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* Read 2 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + /* Shift and then store the results in the destination buffer. */ + *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + * @} end of shift group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c new file mode 100644 index 0000000..12490a1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q31.c + * Description: Shifts the elements of a Q31 vector by a specified number of bits + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ +/** + * @defgroup shift Vector Shift + * + * Shifts the elements of a fixed-point vector by a specified number of bits. + * There are separate functions for Q7, Q15, and Q31 data types. + * The underlying algorithm used is: + * + * 
+ *     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.
+ *
+ * + * If shift is positive then the elements of the vector are shifted to the left. + * If shift is negative then the elements of the vector are shifted to the right. + * + * The functions support in-place computation allowing the source and destination + * pointers to reference the same memory buffer. + */ + +/** + * @addtogroup shift + * @{ + */ + +/** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_DSP) + + q31_t in1, in2, in3, in4; /* Temporary input variables */ + q31_t out1, out2, out3, out4; /* Temporary output variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + + if (sign == 0U) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + /* Shift the input and then store the results in the destination buffer. */ + in1 = *pSrc; + in2 = *(pSrc + 1); + out1 = in1 << shiftBits; + in3 = *(pSrc + 2); + out2 = in2 << shiftBits; + in4 = *(pSrc + 3); + if (in1 != (out1 >> shiftBits)) + out1 = 0x7FFFFFFF ^ (in1 >> 31); + + if (in2 != (out2 >> shiftBits)) + out2 = 0x7FFFFFFF ^ (in2 >> 31); + + *pDst = out1; + out3 = in3 << shiftBits; + *(pDst + 1) = out2; + out4 = in4 << shiftBits; + + if (in3 != (out3 >> shiftBits)) + out3 = 0x7FFFFFFF ^ (in3 >> 31); + + if (in4 != (out4 >> shiftBits)) + out4 = 0x7FFFFFFF ^ (in4 >> 31); + + *(pDst + 2) = out3; + *(pDst + 3) = out4; + + /* Update destination pointer to process next sampels */ + pSrc += 4U; + pDst += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + /* Shift the input and then store the results in the destination buffer. */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + *pDst = (in1 >> -shiftBits); + *(pDst + 1) = (in2 >> -shiftBits); + *(pDst + 2) = (in3 >> -shiftBits); + *(pDst + 3) = (in4 >> -shiftBits); + + + pSrc += 4U; + pDst += 4U; + + blkCnt--; + } + + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = A (>> or <<) shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (sign == 0U) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + + +} + +/** + * @} end of shift group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c new file mode 100644 index 0000000..6f40431 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c @@ -0,0 +1,208 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q7.c + * Description: Processing function for the Q7 Shifting + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup shift + * @{ + */ + + +/** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * \par Conditions for optimum performance + * Input and output buffers should be aligned by 32-bit + * + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated. + */ + +void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign; /* Sign of shiftBits */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1; /* Input value1 */ + q7_t in2; /* Input value2 */ + q7_t in3; /* Input value3 */ + q7_t in4; /* Input value4 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + /* Read 4 inputs */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ + *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8), + __SSAT((in2 << shiftBits), 8), + __SSAT((in3 << shiftBits), 8), + __SSAT((in4 << shiftBits), 8)); + /* Update source pointer to process next sampels */ + pSrc += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + shiftBits = -shiftBits; + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + /* Read 4 inputs */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ + *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits), + (in3 >> shiftBits), (in4 >> shiftBits)); + + + pSrc += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + in1 = *pSrc++; + *pDst++ = (in1 >> shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#endif /* #if defined (ARM_MATH_DSP) */ +} + +/** + * @} end of shift group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c new file mode 100644 index 0000000..6d56fa7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_f32.c + * Description: Floating-point vector subtraction. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicSub Vector Subtraction + * + * Element-by-element subtraction of two vectors. + * + * 
+ *     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicSub + * @{ + */ + + +/** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t inA1, inA2, inA3, inA4; /* temporary variables */ + float32_t inB1, inB2, inB3, inB4; /* temporary variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + /* Read 4 input samples from sourceA and sourceB */ + inA1 = *pSrcA; + inB1 = *pSrcB; + inA2 = *(pSrcA + 1); + inB2 = *(pSrcB + 1); + inA3 = *(pSrcA + 2); + inB3 = *(pSrcB + 2); + inA4 = *(pSrcA + 3); + inB4 = *(pSrcB + 3); + + /* dst = srcA - srcB */ + /* subtract and store the result */ + *pDst = inA1 - inB1; + *(pDst + 1) = inA2 - inB2; + *(pDst + 2) = inA3 - inB3; + *(pDst + 3) = inA4 - inB4; + + + /* Update pointers to process next sampels */ + pSrcA += 4U; + pSrcB += 4U; + pDst += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c new file mode 100644 index 0000000..643f933 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q15.c + * Description: Q15 vector subtraction + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2; + q31_t inB1, inB2; + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer two samples at a time. */ + inA1 = *__SIMD32(pSrcA)++; + inA2 = *__SIMD32(pSrcA)++; + inB1 = *__SIMD32(pSrcB)++; + inB2 = *__SIMD32(pSrcB)++; + + *__SIMD32(pDst)++ = __QSUB16(inA1, inB1); + *__SIMD32(pDst)++ = __QSUB16(inA2, inB2); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + +} + +/** + * @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c new file mode 100644 index 0000000..1c83aae --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q31.c + * Description: Q31 vector subtraction + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inA3, inA4; + q31_t inB1, inB2, inB3, inB4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + inA1 = *pSrcA++; + inA2 = *pSrcA++; + inB1 = *pSrcB++; + inB2 = *pSrcB++; + + inA3 = *pSrcA++; + inA4 = *pSrcA++; + inB3 = *pSrcB++; + inB4 = *pSrcB++; + + *pDst++ = __QSUB(inA1, inB1); + *pDst++ = __QSUB(inA2, inB2); + *pDst++ = __QSUB(inA3, inB3); + *pDst++ = __QSUB(inA4, inB4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + * @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c new file mode 100644 index 0000000..8f8e111 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q7.c + * Description: Q7 vector subtraction + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer 4 samples at a time. */ + *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + +} + +/** + * @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c b/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c new file mode 100644 index 0000000..bb5c15a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c @@ -0,0 +1,22176 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + * @ingroup ComplexFFT + */ + +/** + * @addtogroup CFFT_CIFFT Complex FFT Tables + * @{ + */ + +/** +* \par +* Pseudo code for Generation of Bit reversal Table is +* \par +* 
for(l=1;l <= N/4;l++)
+* {
+*   for(i=0;i> 1;
+*  }
+* \par +* where N = 4096 logN2 = 12 +* \par +* N is the maximum FFT Size supported +*/ + +/* +* @brief Table for bit reversal process +*/ +const uint16_t armBitRevTable[1024] = { + 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, 0x80, 0x480, 0x280, + 0x680, 0x180, 0x580, 0x380, 0x780, 0x40, 0x440, 0x240, 0x640, 0x140, + 0x540, 0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, 0x5c0, 0x3c0, + 0x7c0, 0x20, 0x420, 0x220, 0x620, 0x120, 0x520, 0x320, 0x720, 0xa0, + 0x4a0, 0x2a0, 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460, 0x260, + 0x660, 0x160, 0x560, 0x360, 0x760, 0xe0, 0x4e0, 0x2e0, 0x6e0, 0x1e0, + 0x5e0, 0x3e0, 0x7e0, 0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310, + 0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590, 0x390, 0x790, 0x50, + 0x450, 0x250, 0x650, 0x150, 0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0, + 0x6d0, 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230, 0x630, 0x130, + 0x530, 0x330, 0x730, 0xb0, 0x4b0, 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, + 0x7b0, 0x70, 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, 0xf0, + 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, 0x7f0, 0x8, 0x408, 0x208, + 0x608, 0x108, 0x508, 0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188, + 0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648, 0x148, 0x548, 0x348, + 0x748, 0xc8, 0x4c8, 0x2c8, 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28, + 0x428, 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8, 0x4a8, 0x2a8, + 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, 0x68, 0x468, 0x268, 0x668, 0x168, + 0x568, 0x368, 0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, 0x3e8, + 0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118, 0x518, 0x318, 0x718, 0x98, + 0x498, 0x298, 0x698, 0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258, + 0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8, 0x2d8, 0x6d8, 0x1d8, + 0x5d8, 0x3d8, 0x7d8, 0x38, 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, + 0x738, 0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, 0x7b8, 0x78, + 0x478, 0x278, 0x678, 0x178, 0x578, 0x378, 0x778, 0xf8, 0x4f8, 0x2f8, + 0x6f8, 0x1f8, 0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604, 0x104, + 0x504, 0x304, 0x704, 0x84, 0x484, 0x284, 0x684, 0x184, 0x584, 0x384, + 0x784, 0x44, 0x444, 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4, + 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, 0x24, 0x424, 0x224, + 0x624, 0x124, 0x524, 0x324, 0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, + 0x5a4, 0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164, 0x564, 0x364, + 0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4, 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14, + 0x414, 0x214, 0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494, 0x294, + 0x694, 0x194, 0x594, 0x394, 0x794, 0x54, 0x454, 0x254, 0x654, 0x154, + 0x554, 0x354, 0x754, 0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4, + 0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534, 0x334, 0x734, 0xb4, + 0x4b4, 0x2b4, 0x6b4, 0x1b4, 0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274, + 0x674, 0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4, 0x6f4, 0x1f4, + 0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c, 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, + 0x70c, 0x8c, 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, 0x4c, + 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, 0x74c, 0xcc, 0x4cc, 0x2cc, + 0x6cc, 0x1cc, 0x5cc, 0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c, + 0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac, 0x1ac, 0x5ac, 0x3ac, + 0x7ac, 0x6c, 0x46c, 0x26c, 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec, + 0x4ec, 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c, 0x41c, 0x21c, + 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, 0x9c, 0x49c, 0x29c, 0x69c, 0x19c, + 0x59c, 0x39c, 0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, 0x35c, + 0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, 0x5dc, 0x3dc, 0x7dc, 0x3c, + 0x43c, 0x23c, 0x63c, 0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc, + 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c, 0x27c, 0x67c, 0x17c, + 0x57c, 0x37c, 0x77c, 0xfc, 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, + 0x7fc, 0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, 0x702, 0x82, + 0x482, 0x282, 0x682, 0x182, 0x582, 0x382, 0x782, 0x42, 0x442, 0x242, + 0x642, 0x142, 0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2, 0x1c2, + 0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222, 0x622, 0x122, 0x522, 0x322, + 0x722, 0xa2, 0x4a2, 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62, + 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, 0xe2, 0x4e2, 0x2e2, + 0x6e2, 0x1e2, 0x5e2, 0x3e2, 0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112, + 0x512, 0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192, 0x592, 0x392, + 0x792, 0x52, 0x452, 0x252, 0x652, 0x152, 0x552, 0x352, 0x752, 0xd2, + 0x4d2, 0x2d2, 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432, 0x232, + 0x632, 0x132, 0x532, 0x332, 0x732, 0xb2, 0x4b2, 0x2b2, 0x6b2, 0x1b2, + 0x5b2, 0x3b2, 0x7b2, 0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372, + 0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, 0x3f2, 0x7f2, 0xa, + 0x40a, 0x20a, 0x60a, 0x10a, 0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a, + 0x68a, 0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a, 0x64a, 0x14a, + 0x54a, 0x34a, 0x74a, 0xca, 0x4ca, 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, + 0x7ca, 0x2a, 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, 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0x566, 0x366, 0x766, 0xe6, 0x4e6, 0x2e6, 0x6e6, 0x1e6, 0x5e6, 0x3e6, + 0x7e6, 0x16, 0x416, 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x96, + 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, 0x56, 0x456, 0x256, + 0x656, 0x156, 0x556, 0x356, 0x756, 0xd6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, + 0x5d6, 0x3d6, 0x7d6, 0x36, 0x436, 0x236, 0x636, 0x136, 0x536, 0x336, + 0x736, 0xb6, 0x4b6, 0x2b6, 0x6b6, 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x76, + 0x476, 0x276, 0x676, 0x176, 0x576, 0x376, 0x776, 0xf6, 0x4f6, 0x2f6, + 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0xe, 0x40e, 0x20e, 0x60e, 0x10e, + 0x50e, 0x30e, 0x70e, 0x8e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e, + 0x78e, 0x4e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, 0x34e, 0x74e, 0xce, + 0x4ce, 0x2ce, 0x6ce, 0x1ce, 0x5ce, 0x3ce, 0x7ce, 0x2e, 0x42e, 0x22e, + 0x62e, 0x12e, 0x52e, 0x32e, 0x72e, 0xae, 0x4ae, 0x2ae, 0x6ae, 0x1ae, + 0x5ae, 0x3ae, 0x7ae, 0x6e, 0x46e, 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, + 0x76e, 0xee, 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, 0x1e, + 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, 0x71e, 0x9e, 0x49e, 0x29e, + 0x69e, 0x19e, 0x59e, 0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e, + 0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de, 0x1de, 0x5de, 0x3de, + 0x7de, 0x3e, 0x43e, 0x23e, 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe, + 0x4be, 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e, 0x47e, 0x27e, + 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, 0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, + 0x5fe, 0x3fe, 0x7fe, 0x1 +}; + + +/* +* @brief Floating-point Twiddle factors Table Generation +*/ + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 16 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float32_t twiddleCoef_16[32] = { + 1.000000000f, 0.000000000f, + 0.923879533f, 0.382683432f, + 0.707106781f, 0.707106781f, + 0.382683432f, 0.923879533f, + 0.000000000f, 1.000000000f, + -0.382683432f, 0.923879533f, + -0.707106781f, 0.707106781f, + -0.923879533f, 0.382683432f, + -1.000000000f, 0.000000000f, + -0.923879533f, -0.382683432f, + -0.707106781f, -0.707106781f, + -0.382683432f, -0.923879533f, + -0.000000000f, -1.000000000f, + 0.382683432f, -0.923879533f, + 0.707106781f, -0.707106781f, + 0.923879533f, -0.382683432f +}; + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 32 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float32_t twiddleCoef_32[64] = { + 1.000000000f, 0.000000000f, + 0.980785280f, 0.195090322f, + 0.923879533f, 0.382683432f, + 0.831469612f, 0.555570233f, + 0.707106781f, 0.707106781f, + 0.555570233f, 0.831469612f, + 0.382683432f, 0.923879533f, + 0.195090322f, 0.980785280f, + 0.000000000f, 1.000000000f, + -0.195090322f, 0.980785280f, + -0.382683432f, 0.923879533f, + -0.555570233f, 0.831469612f, + -0.707106781f, 0.707106781f, + -0.831469612f, 0.555570233f, + -0.923879533f, 0.382683432f, + -0.980785280f, 0.195090322f, + -1.000000000f, 0.000000000f, + -0.980785280f, -0.195090322f, + -0.923879533f, -0.382683432f, + -0.831469612f, -0.555570233f, + -0.707106781f, -0.707106781f, + -0.555570233f, -0.831469612f, + -0.382683432f, -0.923879533f, + -0.195090322f, -0.980785280f, + -0.000000000f, -1.000000000f, + 0.195090322f, -0.980785280f, + 0.382683432f, -0.923879533f, + 0.555570233f, -0.831469612f, + 0.707106781f, -0.707106781f, + 0.831469612f, -0.555570233f, + 0.923879533f, -0.382683432f, + 0.980785280f, -0.195090322f +}; + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 64 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float32_t twiddleCoef_64[128] = { + 1.000000000f, 0.000000000f, + 0.995184727f, 0.098017140f, + 0.980785280f, 0.195090322f, + 0.956940336f, 0.290284677f, + 0.923879533f, 0.382683432f, + 0.881921264f, 0.471396737f, + 0.831469612f, 0.555570233f, + 0.773010453f, 0.634393284f, + 0.707106781f, 0.707106781f, + 0.634393284f, 0.773010453f, + 0.555570233f, 0.831469612f, + 0.471396737f, 0.881921264f, + 0.382683432f, 0.923879533f, + 0.290284677f, 0.956940336f, + 0.195090322f, 0.980785280f, + 0.098017140f, 0.995184727f, + 0.000000000f, 1.000000000f, + -0.098017140f, 0.995184727f, + -0.195090322f, 0.980785280f, + -0.290284677f, 0.956940336f, + -0.382683432f, 0.923879533f, + -0.471396737f, 0.881921264f, + -0.555570233f, 0.831469612f, + -0.634393284f, 0.773010453f, + -0.707106781f, 0.707106781f, + -0.773010453f, 0.634393284f, + -0.831469612f, 0.555570233f, + -0.881921264f, 0.471396737f, + -0.923879533f, 0.382683432f, + -0.956940336f, 0.290284677f, + -0.980785280f, 0.195090322f, + -0.995184727f, 0.098017140f, + -1.000000000f, 0.000000000f, + -0.995184727f, -0.098017140f, + -0.980785280f, -0.195090322f, + -0.956940336f, -0.290284677f, + -0.923879533f, -0.382683432f, + -0.881921264f, -0.471396737f, + -0.831469612f, -0.555570233f, + -0.773010453f, -0.634393284f, + -0.707106781f, -0.707106781f, + -0.634393284f, -0.773010453f, + -0.555570233f, -0.831469612f, + -0.471396737f, -0.881921264f, + -0.382683432f, -0.923879533f, + -0.290284677f, -0.956940336f, + -0.195090322f, -0.980785280f, + -0.098017140f, -0.995184727f, + -0.000000000f, -1.000000000f, + 0.098017140f, -0.995184727f, + 0.195090322f, -0.980785280f, + 0.290284677f, -0.956940336f, + 0.382683432f, -0.923879533f, + 0.471396737f, -0.881921264f, + 0.555570233f, -0.831469612f, + 0.634393284f, -0.773010453f, + 0.707106781f, -0.707106781f, + 0.773010453f, -0.634393284f, + 0.831469612f, -0.555570233f, + 0.881921264f, -0.471396737f, + 0.923879533f, -0.382683432f, + 0.956940336f, -0.290284677f, + 0.980785280f, -0.195090322f, + 0.995184727f, -0.098017140f +}; + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 128 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ + +const float32_t twiddleCoef_128[256] = { + 1.000000000f, 0.000000000f, + 0.998795456f, 0.049067674f, + 0.995184727f, 0.098017140f, + 0.989176510f, 0.146730474f, + 0.980785280f, 0.195090322f, + 0.970031253f, 0.242980180f, + 0.956940336f, 0.290284677f, + 0.941544065f, 0.336889853f, + 0.923879533f, 0.382683432f, + 0.903989293f, 0.427555093f, + 0.881921264f, 0.471396737f, + 0.857728610f, 0.514102744f, + 0.831469612f, 0.555570233f, + 0.803207531f, 0.595699304f, + 0.773010453f, 0.634393284f, + 0.740951125f, 0.671558955f, + 0.707106781f, 0.707106781f, + 0.671558955f, 0.740951125f, + 0.634393284f, 0.773010453f, + 0.595699304f, 0.803207531f, + 0.555570233f, 0.831469612f, + 0.514102744f, 0.857728610f, + 0.471396737f, 0.881921264f, + 0.427555093f, 0.903989293f, + 0.382683432f, 0.923879533f, + 0.336889853f, 0.941544065f, + 0.290284677f, 0.956940336f, + 0.242980180f, 0.970031253f, + 0.195090322f, 0.980785280f, + 0.146730474f, 0.989176510f, + 0.098017140f, 0.995184727f, + 0.049067674f, 0.998795456f, + 0.000000000f, 1.000000000f, + -0.049067674f, 0.998795456f, + -0.098017140f, 0.995184727f, + -0.146730474f, 0.989176510f, + -0.195090322f, 0.980785280f, + -0.242980180f, 0.970031253f, + -0.290284677f, 0.956940336f, + -0.336889853f, 0.941544065f, + -0.382683432f, 0.923879533f, + -0.427555093f, 0.903989293f, + -0.471396737f, 0.881921264f, + -0.514102744f, 0.857728610f, + -0.555570233f, 0.831469612f, + -0.595699304f, 0.803207531f, + -0.634393284f, 0.773010453f, + -0.671558955f, 0.740951125f, + -0.707106781f, 0.707106781f, + -0.740951125f, 0.671558955f, + -0.773010453f, 0.634393284f, + -0.803207531f, 0.595699304f, + -0.831469612f, 0.555570233f, + -0.857728610f, 0.514102744f, + -0.881921264f, 0.471396737f, + -0.903989293f, 0.427555093f, + -0.923879533f, 0.382683432f, + -0.941544065f, 0.336889853f, + -0.956940336f, 0.290284677f, + -0.970031253f, 0.242980180f, + -0.980785280f, 0.195090322f, + -0.989176510f, 0.146730474f, + -0.995184727f, 0.098017140f, + -0.998795456f, 0.049067674f, + -1.000000000f, 0.000000000f, + -0.998795456f, -0.049067674f, + -0.995184727f, -0.098017140f, + -0.989176510f, -0.146730474f, + -0.980785280f, -0.195090322f, + -0.970031253f, -0.242980180f, + -0.956940336f, -0.290284677f, + -0.941544065f, -0.336889853f, + -0.923879533f, -0.382683432f, + -0.903989293f, -0.427555093f, + -0.881921264f, -0.471396737f, + -0.857728610f, -0.514102744f, + -0.831469612f, -0.555570233f, + -0.803207531f, -0.595699304f, + -0.773010453f, -0.634393284f, + -0.740951125f, -0.671558955f, + -0.707106781f, -0.707106781f, + -0.671558955f, -0.740951125f, + -0.634393284f, -0.773010453f, + -0.595699304f, -0.803207531f, + -0.555570233f, -0.831469612f, + -0.514102744f, -0.857728610f, + -0.471396737f, -0.881921264f, + -0.427555093f, -0.903989293f, + -0.382683432f, -0.923879533f, + -0.336889853f, -0.941544065f, + -0.290284677f, -0.956940336f, + -0.242980180f, -0.970031253f, + -0.195090322f, -0.980785280f, + -0.146730474f, -0.989176510f, + -0.098017140f, -0.995184727f, + -0.049067674f, -0.998795456f, + -0.000000000f, -1.000000000f, + 0.049067674f, -0.998795456f, + 0.098017140f, -0.995184727f, + 0.146730474f, -0.989176510f, + 0.195090322f, -0.980785280f, + 0.242980180f, -0.970031253f, + 0.290284677f, -0.956940336f, + 0.336889853f, -0.941544065f, + 0.382683432f, -0.923879533f, + 0.427555093f, -0.903989293f, + 0.471396737f, -0.881921264f, + 0.514102744f, -0.857728610f, + 0.555570233f, -0.831469612f, + 0.595699304f, -0.803207531f, + 0.634393284f, -0.773010453f, + 0.671558955f, -0.740951125f, + 0.707106781f, -0.707106781f, + 0.740951125f, -0.671558955f, + 0.773010453f, -0.634393284f, + 0.803207531f, -0.595699304f, + 0.831469612f, -0.555570233f, + 0.857728610f, -0.514102744f, + 0.881921264f, -0.471396737f, + 0.903989293f, -0.427555093f, + 0.923879533f, -0.382683432f, + 0.941544065f, -0.336889853f, + 0.956940336f, -0.290284677f, + 0.970031253f, -0.242980180f, + 0.980785280f, -0.195090322f, + 0.989176510f, -0.146730474f, + 0.995184727f, -0.098017140f, + 0.998795456f, -0.049067674f +}; + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 256 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float32_t twiddleCoef_256[512] = { + 1.000000000f, 0.000000000f, + 0.999698819f, 0.024541229f, + 0.998795456f, 0.049067674f, + 0.997290457f, 0.073564564f, + 0.995184727f, 0.098017140f, + 0.992479535f, 0.122410675f, + 0.989176510f, 0.146730474f, + 0.985277642f, 0.170961889f, + 0.980785280f, 0.195090322f, + 0.975702130f, 0.219101240f, + 0.970031253f, 0.242980180f, + 0.963776066f, 0.266712757f, + 0.956940336f, 0.290284677f, + 0.949528181f, 0.313681740f, + 0.941544065f, 0.336889853f, + 0.932992799f, 0.359895037f, + 0.923879533f, 0.382683432f, + 0.914209756f, 0.405241314f, + 0.903989293f, 0.427555093f, + 0.893224301f, 0.449611330f, + 0.881921264f, 0.471396737f, + 0.870086991f, 0.492898192f, + 0.857728610f, 0.514102744f, + 0.844853565f, 0.534997620f, + 0.831469612f, 0.555570233f, + 0.817584813f, 0.575808191f, + 0.803207531f, 0.595699304f, + 0.788346428f, 0.615231591f, + 0.773010453f, 0.634393284f, + 0.757208847f, 0.653172843f, + 0.740951125f, 0.671558955f, + 0.724247083f, 0.689540545f, + 0.707106781f, 0.707106781f, + 0.689540545f, 0.724247083f, + 0.671558955f, 0.740951125f, + 0.653172843f, 0.757208847f, + 0.634393284f, 0.773010453f, + 0.615231591f, 0.788346428f, + 0.595699304f, 0.803207531f, + 0.575808191f, 0.817584813f, + 0.555570233f, 0.831469612f, + 0.534997620f, 0.844853565f, + 0.514102744f, 0.857728610f, + 0.492898192f, 0.870086991f, + 0.471396737f, 0.881921264f, + 0.449611330f, 0.893224301f, + 0.427555093f, 0.903989293f, + 0.405241314f, 0.914209756f, + 0.382683432f, 0.923879533f, + 0.359895037f, 0.932992799f, + 0.336889853f, 0.941544065f, + 0.313681740f, 0.949528181f, + 0.290284677f, 0.956940336f, + 0.266712757f, 0.963776066f, + 0.242980180f, 0.970031253f, + 0.219101240f, 0.975702130f, + 0.195090322f, 0.980785280f, + 0.170961889f, 0.985277642f, + 0.146730474f, 0.989176510f, + 0.122410675f, 0.992479535f, + 0.098017140f, 0.995184727f, + 0.073564564f, 0.997290457f, + 0.049067674f, 0.998795456f, + 0.024541229f, 0.999698819f, + 0.000000000f, 1.000000000f, + -0.024541229f, 0.999698819f, + -0.049067674f, 0.998795456f, + -0.073564564f, 0.997290457f, + -0.098017140f, 0.995184727f, + -0.122410675f, 0.992479535f, + -0.146730474f, 0.989176510f, + -0.170961889f, 0.985277642f, + -0.195090322f, 0.980785280f, + -0.219101240f, 0.975702130f, + -0.242980180f, 0.970031253f, + -0.266712757f, 0.963776066f, + -0.290284677f, 0.956940336f, + -0.313681740f, 0.949528181f, + -0.336889853f, 0.941544065f, + -0.359895037f, 0.932992799f, + -0.382683432f, 0.923879533f, + -0.405241314f, 0.914209756f, + -0.427555093f, 0.903989293f, + -0.449611330f, 0.893224301f, + -0.471396737f, 0.881921264f, + -0.492898192f, 0.870086991f, + -0.514102744f, 0.857728610f, + -0.534997620f, 0.844853565f, + -0.555570233f, 0.831469612f, + -0.575808191f, 0.817584813f, + -0.595699304f, 0.803207531f, + -0.615231591f, 0.788346428f, + -0.634393284f, 0.773010453f, + -0.653172843f, 0.757208847f, + -0.671558955f, 0.740951125f, + -0.689540545f, 0.724247083f, + -0.707106781f, 0.707106781f, + -0.724247083f, 0.689540545f, + -0.740951125f, 0.671558955f, + -0.757208847f, 0.653172843f, + -0.773010453f, 0.634393284f, + -0.788346428f, 0.615231591f, + -0.803207531f, 0.595699304f, + -0.817584813f, 0.575808191f, + -0.831469612f, 0.555570233f, + -0.844853565f, 0.534997620f, + -0.857728610f, 0.514102744f, + -0.870086991f, 0.492898192f, + -0.881921264f, 0.471396737f, + -0.893224301f, 0.449611330f, + -0.903989293f, 0.427555093f, + -0.914209756f, 0.405241314f, + -0.923879533f, 0.382683432f, + -0.932992799f, 0.359895037f, + -0.941544065f, 0.336889853f, + -0.949528181f, 0.313681740f, + -0.956940336f, 0.290284677f, + -0.963776066f, 0.266712757f, + -0.970031253f, 0.242980180f, + -0.975702130f, 0.219101240f, + -0.980785280f, 0.195090322f, + -0.985277642f, 0.170961889f, + -0.989176510f, 0.146730474f, + -0.992479535f, 0.122410675f, + -0.995184727f, 0.098017140f, + -0.997290457f, 0.073564564f, + -0.998795456f, 0.049067674f, + -0.999698819f, 0.024541229f, + -1.000000000f, 0.000000000f, + -0.999698819f, -0.024541229f, + -0.998795456f, -0.049067674f, + -0.997290457f, -0.073564564f, + -0.995184727f, -0.098017140f, + -0.992479535f, -0.122410675f, + -0.989176510f, -0.146730474f, + -0.985277642f, -0.170961889f, + -0.980785280f, -0.195090322f, + -0.975702130f, -0.219101240f, + -0.970031253f, -0.242980180f, + -0.963776066f, -0.266712757f, + -0.956940336f, -0.290284677f, + -0.949528181f, -0.313681740f, + -0.941544065f, -0.336889853f, + -0.932992799f, -0.359895037f, + -0.923879533f, -0.382683432f, + -0.914209756f, -0.405241314f, + -0.903989293f, -0.427555093f, + -0.893224301f, -0.449611330f, + -0.881921264f, -0.471396737f, + -0.870086991f, -0.492898192f, + -0.857728610f, -0.514102744f, + -0.844853565f, -0.534997620f, + -0.831469612f, -0.555570233f, + -0.817584813f, -0.575808191f, + -0.803207531f, -0.595699304f, + -0.788346428f, -0.615231591f, + -0.773010453f, -0.634393284f, + -0.757208847f, -0.653172843f, + -0.740951125f, -0.671558955f, + -0.724247083f, -0.689540545f, + -0.707106781f, -0.707106781f, + -0.689540545f, -0.724247083f, + -0.671558955f, -0.740951125f, + -0.653172843f, -0.757208847f, + -0.634393284f, -0.773010453f, + -0.615231591f, -0.788346428f, + -0.595699304f, -0.803207531f, + -0.575808191f, -0.817584813f, + -0.555570233f, -0.831469612f, + -0.534997620f, -0.844853565f, + -0.514102744f, -0.857728610f, + -0.492898192f, -0.870086991f, + -0.471396737f, -0.881921264f, + -0.449611330f, -0.893224301f, + -0.427555093f, -0.903989293f, + -0.405241314f, -0.914209756f, + -0.382683432f, -0.923879533f, + -0.359895037f, -0.932992799f, + -0.336889853f, -0.941544065f, + -0.313681740f, -0.949528181f, + -0.290284677f, -0.956940336f, + -0.266712757f, -0.963776066f, + -0.242980180f, -0.970031253f, + -0.219101240f, -0.975702130f, + -0.195090322f, -0.980785280f, + -0.170961889f, -0.985277642f, + -0.146730474f, -0.989176510f, + -0.122410675f, -0.992479535f, + -0.098017140f, -0.995184727f, + -0.073564564f, -0.997290457f, + -0.049067674f, -0.998795456f, + -0.024541229f, -0.999698819f, + -0.000000000f, -1.000000000f, + 0.024541229f, -0.999698819f, + 0.049067674f, -0.998795456f, + 0.073564564f, -0.997290457f, + 0.098017140f, -0.995184727f, + 0.122410675f, -0.992479535f, + 0.146730474f, -0.989176510f, + 0.170961889f, -0.985277642f, + 0.195090322f, -0.980785280f, + 0.219101240f, -0.975702130f, + 0.242980180f, -0.970031253f, + 0.266712757f, -0.963776066f, + 0.290284677f, -0.956940336f, + 0.313681740f, -0.949528181f, + 0.336889853f, -0.941544065f, + 0.359895037f, -0.932992799f, + 0.382683432f, -0.923879533f, + 0.405241314f, -0.914209756f, + 0.427555093f, -0.903989293f, + 0.449611330f, -0.893224301f, + 0.471396737f, -0.881921264f, + 0.492898192f, -0.870086991f, + 0.514102744f, -0.857728610f, + 0.534997620f, -0.844853565f, + 0.555570233f, -0.831469612f, + 0.575808191f, -0.817584813f, + 0.595699304f, -0.803207531f, + 0.615231591f, -0.788346428f, + 0.634393284f, -0.773010453f, + 0.653172843f, -0.757208847f, + 0.671558955f, -0.740951125f, + 0.689540545f, -0.724247083f, + 0.707106781f, -0.707106781f, + 0.724247083f, -0.689540545f, + 0.740951125f, -0.671558955f, + 0.757208847f, -0.653172843f, + 0.773010453f, -0.634393284f, + 0.788346428f, -0.615231591f, + 0.803207531f, -0.595699304f, + 0.817584813f, -0.575808191f, + 0.831469612f, -0.555570233f, + 0.844853565f, -0.534997620f, + 0.857728610f, -0.514102744f, + 0.870086991f, -0.492898192f, + 0.881921264f, -0.471396737f, + 0.893224301f, -0.449611330f, + 0.903989293f, -0.427555093f, + 0.914209756f, -0.405241314f, + 0.923879533f, -0.382683432f, + 0.932992799f, -0.359895037f, + 0.941544065f, -0.336889853f, + 0.949528181f, -0.313681740f, + 0.956940336f, -0.290284677f, + 0.963776066f, -0.266712757f, + 0.970031253f, -0.242980180f, + 0.975702130f, -0.219101240f, + 0.980785280f, -0.195090322f, + 0.985277642f, -0.170961889f, + 0.989176510f, -0.146730474f, + 0.992479535f, -0.122410675f, + 0.995184727f, -0.098017140f, + 0.997290457f, -0.073564564f, + 0.998795456f, -0.049067674f, + 0.999698819f, -0.024541229f +}; + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 512 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float32_t twiddleCoef_512[1024] = { + 1.000000000f, 0.000000000f, + 0.999924702f, 0.012271538f, + 0.999698819f, 0.024541229f, + 0.999322385f, 0.036807223f, + 0.998795456f, 0.049067674f, + 0.998118113f, 0.061320736f, + 0.997290457f, 0.073564564f, + 0.996312612f, 0.085797312f, + 0.995184727f, 0.098017140f, + 0.993906970f, 0.110222207f, + 0.992479535f, 0.122410675f, + 0.990902635f, 0.134580709f, + 0.989176510f, 0.146730474f, + 0.987301418f, 0.158858143f, + 0.985277642f, 0.170961889f, + 0.983105487f, 0.183039888f, + 0.980785280f, 0.195090322f, + 0.978317371f, 0.207111376f, + 0.975702130f, 0.219101240f, + 0.972939952f, 0.231058108f, + 0.970031253f, 0.242980180f, + 0.966976471f, 0.254865660f, + 0.963776066f, 0.266712757f, + 0.960430519f, 0.278519689f, + 0.956940336f, 0.290284677f, + 0.953306040f, 0.302005949f, + 0.949528181f, 0.313681740f, + 0.945607325f, 0.325310292f, + 0.941544065f, 0.336889853f, + 0.937339012f, 0.348418680f, + 0.932992799f, 0.359895037f, + 0.928506080f, 0.371317194f, + 0.923879533f, 0.382683432f, + 0.919113852f, 0.393992040f, + 0.914209756f, 0.405241314f, + 0.909167983f, 0.416429560f, + 0.903989293f, 0.427555093f, + 0.898674466f, 0.438616239f, + 0.893224301f, 0.449611330f, + 0.887639620f, 0.460538711f, + 0.881921264f, 0.471396737f, + 0.876070094f, 0.482183772f, + 0.870086991f, 0.492898192f, + 0.863972856f, 0.503538384f, + 0.857728610f, 0.514102744f, + 0.851355193f, 0.524589683f, + 0.844853565f, 0.534997620f, + 0.838224706f, 0.545324988f, + 0.831469612f, 0.555570233f, + 0.824589303f, 0.565731811f, + 0.817584813f, 0.575808191f, + 0.810457198f, 0.585797857f, + 0.803207531f, 0.595699304f, + 0.795836905f, 0.605511041f, + 0.788346428f, 0.615231591f, + 0.780737229f, 0.624859488f, + 0.773010453f, 0.634393284f, + 0.765167266f, 0.643831543f, + 0.757208847f, 0.653172843f, + 0.749136395f, 0.662415778f, + 0.740951125f, 0.671558955f, + 0.732654272f, 0.680600998f, + 0.724247083f, 0.689540545f, + 0.715730825f, 0.698376249f, + 0.707106781f, 0.707106781f, + 0.698376249f, 0.715730825f, + 0.689540545f, 0.724247083f, + 0.680600998f, 0.732654272f, + 0.671558955f, 0.740951125f, + 0.662415778f, 0.749136395f, + 0.653172843f, 0.757208847f, + 0.643831543f, 0.765167266f, + 0.634393284f, 0.773010453f, + 0.624859488f, 0.780737229f, + 0.615231591f, 0.788346428f, + 0.605511041f, 0.795836905f, + 0.595699304f, 0.803207531f, + 0.585797857f, 0.810457198f, + 0.575808191f, 0.817584813f, + 0.565731811f, 0.824589303f, + 0.555570233f, 0.831469612f, + 0.545324988f, 0.838224706f, + 0.534997620f, 0.844853565f, + 0.524589683f, 0.851355193f, + 0.514102744f, 0.857728610f, + 0.503538384f, 0.863972856f, + 0.492898192f, 0.870086991f, + 0.482183772f, 0.876070094f, + 0.471396737f, 0.881921264f, + 0.460538711f, 0.887639620f, + 0.449611330f, 0.893224301f, + 0.438616239f, 0.898674466f, + 0.427555093f, 0.903989293f, + 0.416429560f, 0.909167983f, + 0.405241314f, 0.914209756f, + 0.393992040f, 0.919113852f, + 0.382683432f, 0.923879533f, + 0.371317194f, 0.928506080f, + 0.359895037f, 0.932992799f, + 0.348418680f, 0.937339012f, + 0.336889853f, 0.941544065f, + 0.325310292f, 0.945607325f, + 0.313681740f, 0.949528181f, + 0.302005949f, 0.953306040f, + 0.290284677f, 0.956940336f, + 0.278519689f, 0.960430519f, + 0.266712757f, 0.963776066f, + 0.254865660f, 0.966976471f, + 0.242980180f, 0.970031253f, + 0.231058108f, 0.972939952f, + 0.219101240f, 0.975702130f, + 0.207111376f, 0.978317371f, + 0.195090322f, 0.980785280f, + 0.183039888f, 0.983105487f, + 0.170961889f, 0.985277642f, + 0.158858143f, 0.987301418f, + 0.146730474f, 0.989176510f, + 0.134580709f, 0.990902635f, + 0.122410675f, 0.992479535f, + 0.110222207f, 0.993906970f, + 0.098017140f, 0.995184727f, + 0.085797312f, 0.996312612f, + 0.073564564f, 0.997290457f, + 0.061320736f, 0.998118113f, + 0.049067674f, 0.998795456f, + 0.036807223f, 0.999322385f, + 0.024541229f, 0.999698819f, + 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0.998118113f, -0.061320736f, + 0.998795456f, -0.049067674f, + 0.999322385f, -0.036807223f, + 0.999698819f, -0.024541229f, + 0.999924702f, -0.012271538f +}; +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 1024 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float32_t twiddleCoef_1024[2048] = { + 1.000000000f, 0.000000000f, + 0.999981175f, 0.006135885f, + 0.999924702f, 0.012271538f, + 0.999830582f, 0.018406730f, + 0.999698819f, 0.024541229f, + 0.999529418f, 0.030674803f, + 0.999322385f, 0.036807223f, + 0.999077728f, 0.042938257f, + 0.998795456f, 0.049067674f, + 0.998475581f, 0.055195244f, + 0.998118113f, 0.061320736f, + 0.997723067f, 0.067443920f, + 0.997290457f, 0.073564564f, + 0.996820299f, 0.079682438f, + 0.996312612f, 0.085797312f, + 0.995767414f, 0.091908956f, + 0.995184727f, 0.098017140f, + 0.994564571f, 0.104121634f, + 0.993906970f, 0.110222207f, + 0.993211949f, 0.116318631f, + 0.992479535f, 0.122410675f, + 0.991709754f, 0.128498111f, + 0.990902635f, 0.134580709f, + 0.990058210f, 0.140658239f, + 0.989176510f, 0.146730474f, + 0.988257568f, 0.152797185f, + 0.987301418f, 0.158858143f, + 0.986308097f, 0.164913120f, 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0.999529418f, -0.030674803f, + 0.999698819f, -0.024541229f, + 0.999830582f, -0.018406730f, + 0.999924702f, -0.012271538f, + 0.999981175f, -0.006135885f +}; + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 2048 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float32_t twiddleCoef_2048[4096] = { + 1.000000000f, 0.000000000f, + 0.999995294f, 0.003067957f, + 0.999981175f, 0.006135885f, + 0.999957645f, 0.009203755f, + 0.999924702f, 0.012271538f, + 0.999882347f, 0.015339206f, + 0.999830582f, 0.018406730f, + 0.999769405f, 0.021474080f, + 0.999698819f, 0.024541229f, + 0.999618822f, 0.027608146f, + 0.999529418f, 0.030674803f, + 0.999430605f, 0.033741172f, + 0.999322385f, 0.036807223f, + 0.999204759f, 0.039872928f, + 0.999077728f, 0.042938257f, + 0.998941293f, 0.046003182f, + 0.998795456f, 0.049067674f, + 0.998640218f, 0.052131705f, + 0.998475581f, 0.055195244f, + 0.998301545f, 0.058258265f, + 0.998118113f, 0.061320736f, + 0.997925286f, 0.064382631f, + 0.997723067f, 0.067443920f, + 0.997511456f, 0.070504573f, + 0.997290457f, 0.073564564f, + 0.997060070f, 0.076623861f, + 0.996820299f, 0.079682438f, + 0.996571146f, 0.082740265f, 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0.999882347f, -0.015339206f, + 0.999924702f, -0.012271538f, + 0.999957645f, -0.009203755f, + 0.999981175f, -0.006135885f, + 0.999995294f, -0.003067957f +}; + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 4096 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float32_t twiddleCoef_4096[8192] = { + 1.000000000f, 0.000000000f, + 0.999998823f, 0.001533980f, + 0.999995294f, 0.003067957f, + 0.999989411f, 0.004601926f, + 0.999981175f, 0.006135885f, + 0.999970586f, 0.007669829f, + 0.999957645f, 0.009203755f, + 0.999942350f, 0.010737659f, + 0.999924702f, 0.012271538f, + 0.999904701f, 0.013805389f, + 0.999882347f, 0.015339206f, + 0.999857641f, 0.016872988f, + 0.999830582f, 0.018406730f, + 0.999801170f, 0.019940429f, + 0.999769405f, 0.021474080f, + 0.999735288f, 0.023007681f, + 0.999698819f, 0.024541229f, + 0.999659997f, 0.026074718f, + 0.999618822f, 0.027608146f, + 0.999575296f, 0.029141509f, + 0.999529418f, 0.030674803f, + 0.999481187f, 0.032208025f, + 0.999430605f, 0.033741172f, + 0.999377670f, 0.035274239f, + 0.999322385f, 0.036807223f, + 0.999264747f, 0.038340120f, + 0.999204759f, 0.039872928f, + 0.999142419f, 0.041405641f, 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0.998301545f, -0.058258265f, + 0.998389737f, -0.056726821f, + 0.998475581f, -0.055195244f, + 0.998559074f, -0.053663538f, + 0.998640218f, -0.052131705f, + 0.998719012f, -0.050599749f, + 0.998795456f, -0.049067674f, + 0.998869550f, -0.047535484f, + 0.998941293f, -0.046003182f, + 0.999010686f, -0.044470772f, + 0.999077728f, -0.042938257f, + 0.999142419f, -0.041405641f, + 0.999204759f, -0.039872928f, + 0.999264747f, -0.038340120f, + 0.999322385f, -0.036807223f, + 0.999377670f, -0.035274239f, + 0.999430605f, -0.033741172f, + 0.999481187f, -0.032208025f, + 0.999529418f, -0.030674803f, + 0.999575296f, -0.029141509f, + 0.999618822f, -0.027608146f, + 0.999659997f, -0.026074718f, + 0.999698819f, -0.024541229f, + 0.999735288f, -0.023007681f, + 0.999769405f, -0.021474080f, + 0.999801170f, -0.019940429f, + 0.999830582f, -0.018406730f, + 0.999857641f, -0.016872988f, + 0.999882347f, -0.015339206f, + 0.999904701f, -0.013805389f, + 0.999924702f, -0.012271538f, + 0.999942350f, -0.010737659f, + 0.999957645f, -0.009203755f, + 0.999970586f, -0.007669829f, + 0.999981175f, -0.006135885f, + 0.999989411f, -0.004601926f, + 0.999995294f, -0.003067957f, + 0.999998823f, -0.001533980f +}; + +/* +* @brief Q31 Twiddle factors Table +*/ + + +/** +* \par +* Example code for Q31 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 16 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to Q31(Fixed point 1.31): +* round(twiddleCoefQ31(i) * pow(2, 31)) +* +*/ +const q31_t twiddleCoef_16_q31[24] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3 +}; + +/** +* \par +* Example code for Q31 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 32 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to Q31(Fixed point 1.31): +* round(twiddleCoefQ31(i) * pow(2, 31)) +* +*/ +const q31_t twiddleCoef_32_q31[48] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xB8E31319, (q31_t)0x9592675B, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xE70747C3, (q31_t)0x8275A0C0 +}; + +/** +* \par +* Example code for Q31 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 64 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to Q31(Fixed point 1.31): +* round(twiddleCoefQ31(i) * pow(2, 31)) +* +*/ +const q31_t twiddleCoef_64_q31[96] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xF3742CA1, (q31_t)0x809DC970 +}; + +/** +* \par +* Example code for Q31 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 128 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to Q31(Fixed point 1.31): +* round(twiddleCoefQ31(i) * pow(2, 31)) +* +*/ +const q31_t twiddleCoef_128_q31[192] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4C3FDFF3, + (q31_t)0x66CF811F, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3C56BA70, + (q31_t)0x70E2CBC6, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2B1F34EB, + (q31_t)0x78848413, (q31_t)0x25280C5D, (q31_t)0x7A7D055B, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x18F8B83C, + (q31_t)0x7D8A5F3F, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0647D97C, + (q31_t)0x7FD8878D, (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF3742CA1, + (q31_t)0x7F62368F, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE0E60684, + (q31_t)0x7C29FBEE, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xCF043AB2, + (q31_t)0x7641AF3C, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xBE31E19B, + (q31_t)0x6DCA0D14, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xAECC336B, + (q31_t)0x62F201AC, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA1288376, + (q31_t)0x55F5A4D2, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9592675B, + (q31_t)0x471CECE6, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8C4A142F, + (q31_t)0x36BA2013, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8582FAA4, + (q31_t)0x25280C5D, (q31_t)0x83D60411, (q31_t)0x1F19F97B, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x8162AA03, + (q31_t)0x12C8106E, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF9B82683, (q31_t)0x80277872 +}; + +/** +* \par +* Example code for Q31 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 256 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to Q31(Fixed point 1.31): +* round(twiddleCoefQ31(i) * pow(2, 31)) +* +*/ +const q31_t twiddleCoef_256_q31[384] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5CB420DF, + (q31_t)0x5842DD54, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x55F5A4D2, + (q31_t)0x5ED77C89, (q31_t)0x539B2AEF, (q31_t)0x60EC3830, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4EBFE8A4, + (q31_t)0x64E88926, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x447ACD50, (q31_t)0x6C242960, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3F1749B7, + (q31_t)0x6F5F02B1, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x36BA2013, + (q31_t)0x73B5EBD0, (q31_t)0x33DEF287, (q31_t)0x7504D345, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2E110A62, + (q31_t)0x776C4EDB, (q31_t)0x2B1F34EB, (q31_t)0x78848413, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1C0B826A, + (q31_t)0x7CE3CEB1, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x12C8106E, + (q31_t)0x7E9D55FC, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x096A9049, + (q31_t)0x7FA736B4, (q31_t)0x0647D97C, (q31_t)0x7FD8878D, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xFCDBD541, (q31_t)0x7FF62182, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF6956FB6, + (q31_t)0x7FA736B4, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xED37EF91, + (q31_t)0x7E9D55FC, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE3F47D95, + (q31_t)0x7CE3CEB1, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xD7D946D7, (q31_t)0x798A23B1, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD1EEF59E, + (q31_t)0x776C4EDB, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xC945DFEC, + (q31_t)0x73B5EBD0, (q31_t)0xC67322CD, (q31_t)0x72552C84, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC0E8B648, + (q31_t)0x6F5F02B1, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xB64BEACC, (q31_t)0x68A69E81, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB140175B, + (q31_t)0x64E88926, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAA0A5B2D, + (q31_t)0x5ED77C89, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA34BDF20, + (q31_t)0x5842DD54, (q31_t)0xA1288376, (q31_t)0x55F5A4D2, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9759617E, + (q31_t)0x49B41533, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9235F2EB, + (q31_t)0x41CE1E64, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8DAAD37B, + (q31_t)0x398CDD32, (q31_t)0x8C4A142F, (q31_t)0x36BA2013, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8893B124, (q31_t)0x2E110A62, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8675DC4E, + (q31_t)0x2826B928, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x83D60411, + (q31_t)0x1F19F97B, (q31_t)0x831C314E, (q31_t)0x1C0B826A, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x81E26C16, + (q31_t)0x15E21444, (q31_t)0x8162AA03, (q31_t)0x12C8106E, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x8058C94C, (q31_t)0x096A9049, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8009DE7D, + (q31_t)0x03242ABF, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80277872, + (q31_t)0xF9B82683, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D +}; + +/** +* \par +* Example code for Q31 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 512 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to Q31(Fixed point 1.31): +* round(twiddleCoefQ31(i) * pow(2, 31)) +* +*/ +const q31_t twiddleCoef_512_q31[768] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6E96A99C, + (q31_t)0x4073F21D, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C242960, + (q31_t)0x447ACD50, (q31_t)0x6B4AF278, (q31_t)0x45CD358F, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x698C246C, + (q31_t)0x4869E664, (q31_t)0x68A69E81, (q31_t)0x49B41533, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x63EF328F, + (q31_t)0x4FFB654D, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x60EC3830, + (q31_t)0x539B2AEF, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5DC79D7C, + (q31_t)0x571DEEF9, (q31_t)0x5CB420DF, (q31_t)0x5842DD54, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x59646497, (q31_t)0x5B9D1153, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x571DEEF9, + (q31_t)0x5DC79D7C, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x539B2AEF, + (q31_t)0x60EC3830, (q31_t)0x5269126E, (q31_t)0x61F1003E, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4FFB654D, + (q31_t)0x63EF328F, (q31_t)0x4EBFE8A4, (q31_t)0x64E88926, + (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4C3FDFF3, + (q31_t)0x66CF811F, (q31_t)0x4AFB6C97, (q31_t)0x67BD0FBC, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x4869E664, + (q31_t)0x698C246C, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x447ACD50, + (q31_t)0x6C242960, (q31_t)0x4325C135, (q31_t)0x6CF934FB, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x4073F21D, + (q31_t)0x6E96A99C, (q31_t)0x3F1749B7, (q31_t)0x6F5F02B1, + (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3C56BA70, + (q31_t)0x70E2CBC6, (q31_t)0x3AF2EEB7, (q31_t)0x719E2CD2, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x382493B0, + (q31_t)0x7307C3D0, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0, + (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x33DEF287, + (q31_t)0x7504D345, (q31_t)0x326E54C7, (q31_t)0x75A585CF, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2F875262, + (q31_t)0x76D94988, (q31_t)0x2E110A62, (q31_t)0x776C4EDB, + (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2B1F34EB, + (q31_t)0x78848413, (q31_t)0x29A3C484, (q31_t)0x7909A92C, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x26A82185, + (q31_t)0x7A05EEAD, (q31_t)0x25280C5D, (q31_t)0x7A7D055B, + (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x2223A4C5, + (q31_t)0x7B5D039D, (q31_t)0x209F701C, (q31_t)0x7BC5E28F, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1D934FE5, + (q31_t)0x7C894BDD, (q31_t)0x1C0B826A, (q31_t)0x7CE3CEB1, + (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x18F8B83C, + (q31_t)0x7D8A5F3F, (q31_t)0x176DD9DE, (q31_t)0x7DD6668E, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x145576B1, + (q31_t)0x7E5FE493, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC, + (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x0FAB272B, + (q31_t)0x7F0991C3, (q31_t)0x0E1BC2E3, (q31_t)0x7F3857F5, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0AFB6805, + (q31_t)0x7F872BF3, (q31_t)0x096A9049, (q31_t)0x7FA736B4, + (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x0647D97C, + (q31_t)0x7FD8878D, (q31_t)0x04B6195D, (q31_t)0x7FE9CBC0, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x01921D1F, + (q31_t)0x7FFD885A, (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFCDBD541, + (q31_t)0x7FF62182, (q31_t)0xFB49E6A2, (q31_t)0x7FE9CBC0, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF826A461, + (q31_t)0x7FC25596, (q31_t)0xF6956FB6, (q31_t)0x7FA736B4, + (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF3742CA1, + (q31_t)0x7F62368F, (q31_t)0xF1E43D1C, (q31_t)0x7F3857F5, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xEEC60F31, + (q31_t)0x7ED5E5C6, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC, + (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEA1DEBBB, + (q31_t)0x7E1D93E9, (q31_t)0xE8922621, (q31_t)0x7DD6668E, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE57D5FDA, + (q31_t)0x7D3980EC, (q31_t)0xE3F47D95, (q31_t)0x7CE3CEB1, + (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE0E60684, + (q31_t)0x7C29FBEE, (q31_t)0xDF608FE3, (q31_t)0x7BC5E28F, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDC597781, + (q31_t)0x7AEF6323, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B, + (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD7D946D7, + (q31_t)0x798A23B1, (q31_t)0xD65C3B7B, (q31_t)0x7909A92C, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD3670445, + (q31_t)0x77FAB988, (q31_t)0xD1EEF59E, (q31_t)0x776C4EDB, + (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xCF043AB2, + (q31_t)0x7641AF3C, (q31_t)0xCD91AB38, (q31_t)0x75A585CF, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCAB26FA9, + (q31_t)0x745F9DD1, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0, + (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC67322CD, + (q31_t)0x72552C84, (q31_t)0xC50D1148, (q31_t)0x719E2CD2, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC247CD5A, + (q31_t)0x70231099, (q31_t)0xC0E8B648, (q31_t)0x6F5F02B1, + (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBE31E19B, + (q31_t)0x6DCA0D14, (q31_t)0xBCDA3ECA, (q31_t)0x6CF934FB, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBA32CA70, + (q31_t)0x6B4AF278, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB64BEACC, + (q31_t)0x68A69E81, (q31_t)0xB5049368, (q31_t)0x67BD0FBC, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB27E9D3B, + (q31_t)0x65DDFBD3, (q31_t)0xB140175B, (q31_t)0x64E88926, + (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAECC336B, + (q31_t)0x62F201AC, (q31_t)0xAD96ED91, (q31_t)0x61F1003E, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAB35F5B5, + (q31_t)0x5FE3B38D, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89, + (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA7BD22AB, + (q31_t)0x5CB420DF, (q31_t)0xA69B9B68, (q31_t)0x5B9D1153, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA462EEAC, + (q31_t)0x59646497, (q31_t)0xA34BDF20, (q31_t)0x5842DD54, + (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA1288376, + (q31_t)0x55F5A4D2, (q31_t)0xA01C4C72, (q31_t)0x54CA0A4A, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9E0EFFC1, + (q31_t)0x5269126E, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94, + (q31_t)0x9C10CD70, (q31_t)0x4FFB654D, (q31_t)0x9B1776D9, + (q31_t)0x4EBFE8A4, (q31_t)0x9A22042C, (q31_t)0x4D8162C4, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9842F043, + (q31_t)0x4AFB6C97, (q31_t)0x9759617E, (q31_t)0x49B41533, + (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x9592675B, + (q31_t)0x471CECE6, (q31_t)0x94B50D87, (q31_t)0x45CD358F, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9306CB04, + (q31_t)0x4325C135, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64, + (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x90A0FD4E, + (q31_t)0x3F1749B7, (q31_t)0x8FDCEF66, (q31_t)0x3DB832A5, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8E61D32D, + (q31_t)0x3AF2EEB7, (q31_t)0x8DAAD37B, (q31_t)0x398CDD32, + (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8C4A142F, + (q31_t)0x36BA2013, (q31_t)0x8BA0622F, (q31_t)0x354D9056, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8A5A7A30, + (q31_t)0x326E54C7, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x8893B124, + (q31_t)0x2E110A62, (q31_t)0x88054677, (q31_t)0x2C98FBBA, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x86F656D3, + (q31_t)0x29A3C484, (q31_t)0x8675DC4E, (q31_t)0x2826B928, + (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x8582FAA4, + (q31_t)0x25280C5D, (q31_t)0x85109CDC, (q31_t)0x23A6887E, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x843A1D70, + (q31_t)0x209F701C, (q31_t)0x83D60411, (q31_t)0x1F19F97B, + (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x831C314E, + (q31_t)0x1C0B826A, (q31_t)0x82C67F13, (q31_t)0x1A82A025, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x82299971, + (q31_t)0x176DD9DE, (q31_t)0x81E26C16, (q31_t)0x15E21444, + (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x8162AA03, + (q31_t)0x12C8106E, (q31_t)0x812A1A39, (q31_t)0x1139F0CE, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80C7A80A, + (q31_t)0x0E1BC2E3, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x8058C94C, + (q31_t)0x096A9049, (q31_t)0x803DAA69, (q31_t)0x07D95B9E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80163440, + (q31_t)0x04B6195D, (q31_t)0x8009DE7D, (q31_t)0x03242ABF, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80163440, + (q31_t)0xFB49E6A2, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8058C94C, + (q31_t)0xF6956FB6, (q31_t)0x8078D40D, (q31_t)0xF50497FA, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80C7A80A, + (q31_t)0xF1E43D1C, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82299971, + (q31_t)0xE8922621, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x831C314E, + (q31_t)0xE3F47D95, (q31_t)0x8376B422, (q31_t)0xE26CB01A, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x843A1D70, + (q31_t)0xDF608FE3, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x85FA1152, (q31_t)0xD957DE7A, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86F656D3, + (q31_t)0xD65C3B7B, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8893B124, + (q31_t)0xD1EEF59E, (q31_t)0x8926B677, (q31_t)0xD078AD9D, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A5A7A30, + (q31_t)0xCD91AB38, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E61D32D, + (q31_t)0xC50D1148, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x90A0FD4E, + (q31_t)0xC0E8B648, (q31_t)0x91695663, (q31_t)0xBF8C0DE2, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9306CB04, + (q31_t)0xBCDA3ECA, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x9673DB94, (q31_t)0xB796199B, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x9842F043, + (q31_t)0xB5049368, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9B1776D9, + (q31_t)0xB140175B, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9E0EFFC1, + (q31_t)0xAD96ED91, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA2386283, (q31_t)0xA8E21106, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA462EEAC, + (q31_t)0xA69B9B68, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA7BD22AB, + (q31_t)0xA34BDF20, (q31_t)0xA8E21106, (q31_t)0xA2386283, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAB35F5B5, + (q31_t)0xA01C4C72, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB27E9D3B, + (q31_t)0x9A22042C, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB64BEACC, + (q31_t)0x9759617E, (q31_t)0xB796199B, (q31_t)0x9673DB94, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBA32CA70, + (q31_t)0x94B50D87, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5 +}; + +/** +* \par +* Example code for Q31 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 1024 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to Q31(Fixed point 1.31): +* round(twiddleCoefQ31(i) * pow(2, 31)) +* +*/ +const q31_t twiddleCoef_1024_q31[1536] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2191B4, + (q31_t)0x0EE38765, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7ED5E5C6, + (q31_t)0x1139F0CE, (q31_t)0x7EBA3A39, (q31_t)0x120116D4, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E7F3956, + (q31_t)0x138EDBB0, (q31_t)0x7E5FE493, (q31_t)0x145576B1, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7DFA98A7, (q31_t)0x16A81305, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DB0FDF7, + (q31_t)0x183366E8, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D3980EC, + (q31_t)0x1A82A025, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CB72724, + (q31_t)0x1CCF8CB3, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B920B89, + (q31_t)0x2161B39F, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7AEF6323, + (q31_t)0x23A6887E, (q31_t)0x7AB6CBA3, (q31_t)0x24677757, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A4210D8, + (q31_t)0x25E845B5, (q31_t)0x7A05EEAD, (q31_t)0x26A82185, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x794A7C11, (q31_t)0x28E5714A, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78C7ABA1, + (q31_t)0x2A61B101, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x77FAB988, + (q31_t)0x2C98FBBA, (q31_t)0x77B417DF, (q31_t)0x2D553AFB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x77235F2D, + (q31_t)0x2ECC681E, (q31_t)0x76D94988, (q31_t)0x2F875262, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x75F42C0A, (q31_t)0x31B54A5D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7555BD4B, + (q31_t)0x3326E2C2, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x745F9DD1, + (q31_t)0x354D9056, (q31_t)0x740B53FA, (q31_t)0x36041AD9, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x735F6626, + (q31_t)0x376F9E46, (q31_t)0x7307C3D0, (q31_t)0x382493B0, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x71FA3948, (q31_t)0x3A402DD1, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x71410804, + (q31_t)0x3BA51E29, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70231099, + (q31_t)0x3DB832A5, (q31_t)0x6FC19385, (q31_t)0x3E680B2C, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6EFB5F12, + (q31_t)0x3FC5EC97, (q31_t)0x6E96A99C, (q31_t)0x4073F21D, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6D6227FA, (q31_t)0x427A41D0, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C8F351C, + (q31_t)0x43D09AEC, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B4AF278, + (q31_t)0x45CD358F, (q31_t)0x6ADCC964, (q31_t)0x46756827, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x69FD614A, + (q31_t)0x47C3C22E, (q31_t)0x698C246C, (q31_t)0x4869E664, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x683257AA, (q31_t)0x4A581C9D, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x6746C7D7, + (q31_t)0x4B9E038F, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x65DDFBD3, + (q31_t)0x4D8162C4, (q31_t)0x6563BF92, (q31_t)0x4E210617, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x646C59BF, + (q31_t)0x4F5E08E3, (q31_t)0x63EF328F, (q31_t)0x4FFB654D, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x6271FA69, (q31_t)0x51CED46E, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x616F146B, + (q31_t)0x53028517, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x5FE3B38D, + (q31_t)0x54CA0A4A, (q31_t)0x5F5E0DB3, (q31_t)0x556040E2, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5E50015D, + (q31_t)0x568A34A9, (q31_t)0x5DC79D7C, (q31_t)0x571DEEF9, + (q31_t)0x5D3E5236, (q31_t)0x57B0D256, (q31_t)0x5CB420DF, + (q31_t)0x5842DD54, (q31_t)0x5C290ACC, (q31_t)0x58D40E8C, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5B1035CF, + (q31_t)0x59F3DE12, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x59F3DE12, (q31_t)0x5B1035CF, (q31_t)0x59646497, + (q31_t)0x5B9D1153, (q31_t)0x58D40E8C, (q31_t)0x5C290ACC, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x57B0D256, + (q31_t)0x5D3E5236, (q31_t)0x571DEEF9, (q31_t)0x5DC79D7C, + (q31_t)0x568A34A9, (q31_t)0x5E50015D, (q31_t)0x55F5A4D2, + (q31_t)0x5ED77C89, (q31_t)0x556040E2, (q31_t)0x5F5E0DB3, + (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x5433027D, + (q31_t)0x60686CCE, (q31_t)0x539B2AEF, (q31_t)0x60EC3830, + (q31_t)0x53028517, (q31_t)0x616F146B, (q31_t)0x5269126E, + (q31_t)0x61F1003E, (q31_t)0x51CED46E, (q31_t)0x6271FA69, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x5097FC5E, + (q31_t)0x637114CC, (q31_t)0x4FFB654D, (q31_t)0x63EF328F, + (q31_t)0x4F5E08E3, (q31_t)0x646C59BF, (q31_t)0x4EBFE8A4, + (q31_t)0x64E88926, (q31_t)0x4E210617, (q31_t)0x6563BF92, + (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4CE10034, + (q31_t)0x66573CBB, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F, + (q31_t)0x4B9E038F, (q31_t)0x6746C7D7, (q31_t)0x4AFB6C97, + (q31_t)0x67BD0FBC, (q31_t)0x4A581C9D, (q31_t)0x683257AA, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x490F57EE, + (q31_t)0x6919E320, (q31_t)0x4869E664, (q31_t)0x698C246C, + (q31_t)0x47C3C22E, (q31_t)0x69FD614A, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x46756827, (q31_t)0x6ADCC964, + (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x452456BC, + (q31_t)0x6BB812D0, (q31_t)0x447ACD50, (q31_t)0x6C242960, + (q31_t)0x43D09AEC, (q31_t)0x6C8F351C, (q31_t)0x4325C135, + (q31_t)0x6CF934FB, (q31_t)0x427A41D0, (q31_t)0x6D6227FA, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x4121589A, + (q31_t)0x6E30E349, (q31_t)0x4073F21D, (q31_t)0x6E96A99C, + (q31_t)0x3FC5EC97, (q31_t)0x6EFB5F12, (q31_t)0x3F1749B7, + (q31_t)0x6F5F02B1, (q31_t)0x3E680B2C, (q31_t)0x6FC19385, + (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3D07C1D5, + (q31_t)0x708378FE, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x3BA51E29, (q31_t)0x71410804, (q31_t)0x3AF2EEB7, + (q31_t)0x719E2CD2, (q31_t)0x3A402DD1, (q31_t)0x71FA3948, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x38D8FE93, + (q31_t)0x72AF05A6, (q31_t)0x382493B0, (q31_t)0x7307C3D0, + (q31_t)0x376F9E46, (q31_t)0x735F6626, (q31_t)0x36BA2013, + (q31_t)0x73B5EBD0, (q31_t)0x36041AD9, (q31_t)0x740B53FA, + (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x3496824F, + (q31_t)0x74B2C883, (q31_t)0x33DEF287, (q31_t)0x7504D345, + (q31_t)0x3326E2C2, (q31_t)0x7555BD4B, (q31_t)0x326E54C7, + (q31_t)0x75A585CF, (q31_t)0x31B54A5D, (q31_t)0x75F42C0A, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x3041C760, + (q31_t)0x768E0EA5, (q31_t)0x2F875262, (q31_t)0x76D94988, + (q31_t)0x2ECC681E, (q31_t)0x77235F2D, (q31_t)0x2E110A62, + (q31_t)0x776C4EDB, (q31_t)0x2D553AFB, (q31_t)0x77B417DF, + (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2BDC4E6F, + (q31_t)0x78403328, (q31_t)0x2B1F34EB, (q31_t)0x78848413, + (q31_t)0x2A61B101, (q31_t)0x78C7ABA1, (q31_t)0x29A3C484, + (q31_t)0x7909A92C, (q31_t)0x28E5714A, (q31_t)0x794A7C11, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x27679DF4, + (q31_t)0x79C89F6D, (q31_t)0x26A82185, (q31_t)0x7A05EEAD, + (q31_t)0x25E845B5, (q31_t)0x7A4210D8, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x24677757, (q31_t)0x7AB6CBA3, + (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x22E541AE, + (q31_t)0x7B26CB4F, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D, + (q31_t)0x2161B39F, (q31_t)0x7B920B89, (q31_t)0x209F701C, + (q31_t)0x7BC5E28F, (q31_t)0x1FDCDC1A, (q31_t)0x7BF88830, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1E56CA1E, + (q31_t)0x7C5A3D4F, (q31_t)0x1D934FE5, (q31_t)0x7C894BDD, + (q31_t)0x1CCF8CB3, (q31_t)0x7CB72724, (q31_t)0x1C0B826A, + (q31_t)0x7CE3CEB1, (q31_t)0x1B4732EF, (q31_t)0x7D0F4218, + (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x19BDCBF2, + (q31_t)0x7D628AC5, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x183366E8, (q31_t)0x7DB0FDF7, (q31_t)0x176DD9DE, + (q31_t)0x7DD6668E, (q31_t)0x16A81305, (q31_t)0x7DFA98A7, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x151BDF85, + (q31_t)0x7E3F57FE, (q31_t)0x145576B1, (q31_t)0x7E5FE493, + (q31_t)0x138EDBB0, (q31_t)0x7E7F3956, (q31_t)0x12C8106E, + (q31_t)0x7E9D55FC, (q31_t)0x120116D4, (q31_t)0x7EBA3A39, + (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x1072A047, + (q31_t)0x7EF0585F, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3, + (q31_t)0x0EE38765, (q31_t)0x7F2191B4, (q31_t)0x0E1BC2E3, + (q31_t)0x7F3857F5, (q31_t)0x0D53DB92, (q31_t)0x7F4DE450, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0BC3AC35, + (q31_t)0x7F754E7F, (q31_t)0x0AFB6805, (q31_t)0x7F872BF3, + (q31_t)0x0A3308BC, (q31_t)0x7F97CEBC, (q31_t)0x096A9049, + (q31_t)0x7FA736B4, (q31_t)0x08A2009A, (q31_t)0x7FB563B2, + (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x0710A344, + (q31_t)0x7FCE0C3E, (q31_t)0x0647D97C, (q31_t)0x7FD8878D, + (q31_t)0x057F0034, (q31_t)0x7FE1C76B, (q31_t)0x04B6195D, + (q31_t)0x7FE9CBC0, (q31_t)0x03ED26E6, (q31_t)0x7FF09477, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x025B26D7, + (q31_t)0x7FFA72D1, (q31_t)0x01921D1F, (q31_t)0x7FFD885A, + (q31_t)0x00C90F88, (q31_t)0x7FFF6216, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xFF36F078, (q31_t)0x7FFF6216, + (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFDA4D928, + (q31_t)0x7FFA72D1, (q31_t)0xFCDBD541, (q31_t)0x7FF62182, + (q31_t)0xFC12D919, (q31_t)0x7FF09477, (q31_t)0xFB49E6A2, + (q31_t)0x7FE9CBC0, (q31_t)0xFA80FFCB, (q31_t)0x7FE1C76B, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF8EF5CBB, + (q31_t)0x7FCE0C3E, (q31_t)0xF826A461, (q31_t)0x7FC25596, + (q31_t)0xF75DFF65, (q31_t)0x7FB563B2, (q31_t)0xF6956FB6, + (q31_t)0x7FA736B4, (q31_t)0xF5CCF743, (q31_t)0x7F97CEBC, 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+ (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB98A97D8, + (q31_t)0x9523369B, (q31_t)0xBA32CA70, (q31_t)0x94B50D87, + (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD85BE2F, + (q31_t)0x929DD805, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF8C0DE2, + (q31_t)0x91695663, (q31_t)0xC03A1368, (q31_t)0x9104A0ED, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC197F4D3, + (q31_t)0x903E6C7A, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5BFD22E, + (q31_t)0x8E05C6B7, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7DB6C50, + (q31_t)0x8CF83C30, (q31_t)0xC89061BA, (q31_t)0x8CA099D9, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9FBE527, + (q31_t)0x8BF4AC05, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCE4AB5A2, + (q31_t)0x8A0BD3F5, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD078AD9D, + (q31_t)0x8926B677, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD2AAC504, + (q31_t)0x884BE820, (q31_t)0xD3670445, (q31_t)0x88054677, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD59E4EFE, (q31_t)0x8738545E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD71A8EB5, + (q31_t)0x86B583EE, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD957DE7A, + (q31_t)0x85FA1152, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB9888A8, + (q31_t)0x8549345C, (q31_t)0xDC597781, (q31_t)0x85109CDC, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xDE9E4C60, (q31_t)0x846DF476, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE02323E5, + (q31_t)0x840777CF, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE26CB01A, + (q31_t)0x8376B422, (q31_t)0xE330734C, (q31_t)0x8348D8DB, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4B8CD10, + (q31_t)0x82F0BDE8, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xE7CC9917, (q31_t)0x824F0208, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE957ECFB, + (q31_t)0x82056758, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFF36F078, (q31_t)0x80009DE9 +}; + +/** +* \par +* Example code for Q31 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 2048 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to Q31(Fixed point 1.31): +* round(twiddleCoefQ31(i) * pow(2, 31)) +* +*/ +const q31_t twiddleCoef_2048_q31[3072] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFD885, + (q31_t)0x006487E3, (q31_t)0x7FFF6216, (q31_t)0x00C90F88, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FFC250F, (q31_t)0x01F6A296, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF871A1, + (q31_t)0x02BFA9A4, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF09477, + (q31_t)0x03ED26E6, (q31_t)0x7FED5790, (q31_t)0x0451A176, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE5F108, + (q31_t)0x051A8E5C, (q31_t)0x7FE1C76B, (q31_t)0x057F0034, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FD37152, (q31_t)0x06AC406F, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC85853, + (q31_t)0x077501BE, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB563B2, + (q31_t)0x08A2009A, (q31_t)0x7FAE7494, (q31_t)0x09064B3A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F9FAA15, + (q31_t)0x09CECF89, (q31_t)0x7F97CEBC, (q31_t)0x0A3308BC, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F7E648B, (q31_t)0x0B5F8D9F, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F6BE9D4, + (q31_t)0x0C27C389, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F4DE450, + (q31_t)0x0D53DB92, (q31_t)0x7F434563, (q31_t)0x0DB7D376, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2D1C0E, + (q31_t)0x0E7FA99D, (q31_t)0x7F2191B4, (q31_t)0x0EE38765, + (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7EFD1C3C, (q31_t)0x100EE8AD, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE34635, + (q31_t)0x10D64DBC, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EBA3A39, + (q31_t)0x120116D4, (q31_t)0x7EABEF2C, (q31_t)0x1264994E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E8E6EB1, + (q31_t)0x132B7BF9, (q31_t)0x7E7F3956, (q31_t)0x138EDBB0, + (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E4FC53E, (q31_t)0x14B8B17F, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E2E9CDF, + (q31_t)0x157F0086, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7DFA98A7, + (q31_t)0x16A81305, (q31_t)0x7DE8A670, (q31_t)0x170AFD8D, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DC3D90D, + (q31_t)0x17D0A7BB, (q31_t)0x7DB0FDF7, (q31_t)0x183366E8, + (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D769BB5, (q31_t)0x195B49E9, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D4E2C7E, + (q31_t)0x1A203E1B, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D0F4218, + (q31_t)0x1B4732EF, (q31_t)0x7CF9AEF0, (q31_t)0x1BA96334, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CCDA168, + (q31_t)0x1C6D9053, (q31_t)0x7CB72724, (q31_t)0x1CCF8CB3, + (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C71EAF8, (q31_t)0x1DF5163F, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4242F2, + (q31_t)0x1EB86B46, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7BF88830, + (q31_t)0x1FDCDC1A, (q31_t)0x7BDF5B94, (q31_t)0x203E300D, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BAC1D31, + (q31_t)0x21009C0B, (q31_t)0x7B920B89, (q31_t)0x2161B39F, + (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7B420D7A, (q31_t)0x22847DDF, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B0B3D2C, + (q31_t)0x2345EFF7, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AB6CBA3, + (q31_t)0x24677757, (q31_t)0x7A9A0E4F, (q31_t)0x24C7CD32, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A5FB0D8, + (q31_t)0x2588349D, (q31_t)0x7A4210D8, (q31_t)0x25E845B5, + (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x79E76CA6, (q31_t)0x2707EBC6, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79A98715, + (q31_t)0x27C737D2, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x794A7C11, + (q31_t)0x28E5714A, (q31_t)0x792A37FE, (q31_t)0x2944A7A2, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78E8CFB1, + (q31_t)0x2A02C7B8, (q31_t)0x78C7ABA1, (q31_t)0x2A61B101, + (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x786280BF, (q31_t)0x2B7DCF17, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x781D9B64, + (q31_t)0x2C3AB2B9, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x77D78DAA, (q31_t)0x2CF72939, (q31_t)0x77B417DF, + (q31_t)0x2D553AFB, (q31_t)0x7790583D, (q31_t)0x2DB330C7, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7747FBCE, + (q31_t)0x2E6EC792, (q31_t)0x77235F2D, (q31_t)0x2ECC681E, + (q31_t)0x76FE790E, (q31_t)0x2F29EBCC, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x76B3D0B3, (q31_t)0x2FE49BA6, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x76680376, + (q31_t)0x309ED555, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x761B1211, (q31_t)0x3158970D, (q31_t)0x75F42C0A, + (q31_t)0x31B54A5D, (q31_t)0x75CCFD42, (q31_t)0x3211DF03, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x757DC5CA, + (q31_t)0x32CAAB6F, (q31_t)0x7555BD4B, (q31_t)0x3326E2C2, + (q31_t)0x752D6C6C, (q31_t)0x3382FA88, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x74DBF1EF, (q31_t)0x343ACA87, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x7489571B, + (q31_t)0x34F219A7, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x74359CBD, (q31_t)0x35A8E624, (q31_t)0x740B53FA, + (q31_t)0x36041AD9, (q31_t)0x73E0C3A3, (q31_t)0x365F2E3B, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x738ACC9E, + (q31_t)0x3714F02A, (q31_t)0x735F6626, (q31_t)0x376F9E46, + (q31_t)0x7333B883, (q31_t)0x37CA2A30, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72DB8828, (q31_t)0x387EDA8E, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72823C66, + (q31_t)0x3932FF87, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x7227D61C, (q31_t)0x39E6975D, (q31_t)0x71FA3948, + (q31_t)0x3A402DD1, (q31_t)0x71CC5626, (q31_t)0x3A99A057, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x716FBD68, + (q31_t)0x3B4C18BA, (q31_t)0x71410804, (q31_t)0x3BA51E29, + (q31_t)0x71120CC5, (q31_t)0x3BFDFECD, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70B34524, (q31_t)0x3CAF50DA, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70536771, + (q31_t)0x3D600D2B, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6FF27496, (q31_t)0x3E10320D, (q31_t)0x6FC19385, + (q31_t)0x3E680B2C, (q31_t)0x6F906D84, (q31_t)0x3EBFBDCC, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6F2D532C, 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(q31_t)0x835FA00E, + (q31_t)0xE2CE88B2, (q31_t)0x8376B422, (q31_t)0xE26CB01A, + (q31_t)0x838E1507, (q31_t)0xE20AE9C1, (q31_t)0x83A5C2B0, + (q31_t)0xE1A935E1, (q31_t)0x83BDBD0D, (q31_t)0xE14794B9, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x83EE97AC, + (q31_t)0xE0848B7F, (q31_t)0x840777CF, (q31_t)0xE02323E5, + (q31_t)0x8420A46B, (q31_t)0xDFC1CFF2, (q31_t)0x843A1D70, + (q31_t)0xDF608FE3, (q31_t)0x8453E2CE, (q31_t)0xDEFF63F4, + (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x84885257, + (q31_t)0xDE3D4963, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A, + (q31_t)0x84BDF285, (q31_t)0xDD7B8220, (q31_t)0x84D934B0, + (q31_t)0xDD1ABE51, (q31_t)0x84F4C2D3, (q31_t)0xDCBA1008, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x852CC2BA, + (q31_t)0xDBF8F4F8, (q31_t)0x8549345C, (q31_t)0xDB9888A8, + (q31_t)0x8565F1B0, (q31_t)0xDB3832CD, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x85A04F28, (q31_t)0xDA77CB62, + (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85DBDA91, + (q31_t)0xD9B7C093, (q31_t)0x85FA1152, (q31_t)0xD957DE7A, + (q31_t)0x86189359, (q31_t)0xD8F81439, (q31_t)0x86376092, + (q31_t)0xD898620C, (q31_t)0x865678EA, (q31_t)0xD838C82D, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86958AAB, + (q31_t)0xD779DE46, (q31_t)0x86B583EE, (q31_t)0xD71A8EB5, + (q31_t)0x86D5C802, (q31_t)0xD6BB585D, (q31_t)0x86F656D3, + (q31_t)0xD65C3B7B, (q31_t)0x8717304E, (q31_t)0xD5FD3847, + (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x8759C2EF, + (q31_t)0xD53F7FDA, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x879D7F40, (q31_t)0xD48230E8, (q31_t)0x87BFCCD7, + (q31_t)0xD423B190, (q31_t)0x87E2649B, (q31_t)0xD3C54D46, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x88287255, + (q31_t)0xD308D6C6, (q31_t)0x884BE820, (q31_t)0xD2AAC504, + (q31_t)0x886FA7C2, (q31_t)0xD24CCF38, (q31_t)0x8893B124, + (q31_t)0xD1EEF59E, (q31_t)0x88B80431, (q31_t)0xD191386D, + (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x890186F1, + (q31_t)0xD0D61433, (q31_t)0x8926B677, (q31_t)0xD078AD9D, + (q31_t)0x894C2F4C, (q31_t)0xD01B6459, (q31_t)0x8971F15A, + (q31_t)0xCFBE389F, (q31_t)0x8997FC89, (q31_t)0xCF612AAA, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x89E4EDEE, + (q31_t)0xCEA768F2, (q31_t)0x8A0BD3F5, (q31_t)0xCE4AB5A2, + (q31_t)0x8A3302BD, (q31_t)0xCDEE20FC, (q31_t)0x8A5A7A30, + (q31_t)0xCD91AB38, (q31_t)0x8A823A35, (q31_t)0xCD355490, + (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8AD29393, + (q31_t)0xCC7D0577, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78, + (q31_t)0x8B240E10, (q31_t)0xCBC53578, (q31_t)0x8B4D377C, + (q31_t)0xCB697DB0, (q31_t)0x8B76A8E4, (q31_t)0xCB0DE658, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BCA6342, + (q31_t)0xCA5719DB, (q31_t)0x8BF4AC05, (q31_t)0xC9FBE527, + (q31_t)0x8C1F3C5C, (q31_t)0xC9A0D1C4, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8C753361, (q31_t)0xC8EB0FD6, + (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CCC477D, + (q31_t)0xC835D5D0, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50, + (q31_t)0x8D2477D8, (q31_t)0xC7812571, (q31_t)0x8D50FA59, + (q31_t)0xC727016C, (q31_t)0x8D7DC399, (q31_t)0xC6CD0079, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8DD829E4, + (q31_t)0xC61968A2, (q31_t)0x8E05C6B7, (q31_t)0xC5BFD22E, + (q31_t)0x8E33A9D9, (q31_t)0xC5665FA8, (q31_t)0x8E61D32D, + (q31_t)0xC50D1148, (q31_t)0x8E904298, (q31_t)0xC4B3E746, + (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8EEDF33B, + (q31_t)0xC4020132, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x8F4CBADB, (q31_t)0xC350AF25, (q31_t)0x8F7C8701, + (q31_t)0xC2F83E2A, (q31_t)0x8FAC988E, (q31_t)0xC29FF2D4, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x900D8B69, + (q31_t)0xC1EFCDF2, (q31_t)0x903E6C7A, (q31_t)0xC197F4D3, + (q31_t)0x906F927B, (q31_t)0xC1404233, (q31_t)0x90A0FD4E, + (q31_t)0xC0E8B648, (q31_t)0x90D2ACD3, (q31_t)0xC0915147, + (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x9136D97D, + (q31_t)0xBFE2FCDF, (q31_t)0x91695663, (q31_t)0xBF8C0DE2, + (q31_t)0x919C1780, (q31_t)0xBF3546A8, (q31_t)0x91CF1CB6, + (q31_t)0xBEDEA765, (q31_t)0x920265E4, (q31_t)0xBE88304F, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9269C3AC, + (q31_t)0xBDDBBB7F, (q31_t)0x929DD805, (q31_t)0xBD85BE2F, + (q31_t)0x92D22FD8, (q31_t)0xBD2FE9E1, (q31_t)0x9306CB04, + (q31_t)0xBCDA3ECA, (q31_t)0x933BA968, (q31_t)0xBC84BD1E, + (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93A62F56, + (q31_t)0xBBDA36DC, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF, + (q31_t)0x9411C09D, (q31_t)0xBB3058C0, (q31_t)0x9447ED2F, + (q31_t)0xBADBA943, (q31_t)0x947E5C32, (q31_t)0xBA87246C, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x94EC010B, + (q31_t)0xB9DE9B83, (q31_t)0x9523369B, (q31_t)0xB98A97D8, + (q31_t)0x955AAE17, (q31_t)0xB936BFA3, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x95CA6246, (q31_t)0xB88F926C, + (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x963B1C85, + (q31_t)0xB7E9157A, (q31_t)0x9673DB94, (q31_t)0xB796199B, + (q31_t)0x96ACDBBD, (q31_t)0xB7434A67, (q31_t)0x96E61CDF, + (q31_t)0xB6F0A811, (q31_t)0x971F9ED6, (q31_t)0xB69E32CD, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x979364B5, + (q31_t)0xB5F9D042, (q31_t)0x97CDA855, (q31_t)0xB5A7E362, + (q31_t)0x98082C3B, (q31_t)0xB556245E, (q31_t)0x9842F043, + (q31_t)0xB5049368, (q31_t)0x987DF449, (q31_t)0xB4B330B2, + (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x98F4BBBC, + (q31_t)0xB410F6D2, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x996C816F, (q31_t)0xB36F784E, (q31_t)0x99A8C344, + (q31_t)0xB31EFFCB, (q31_t)0x99E5443A, (q31_t)0xB2CEB6B5, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A5F02F5, + (q31_t)0xB22EB392, (q31_t)0x9A9C406D, (q31_t)0xB1DEF9E8, + (q31_t)0x9AD9BC71, (q31_t)0xB18F7070, (q31_t)0x9B1776D9, + (q31_t)0xB140175B, (q31_t)0x9B556F80, (q31_t)0xB0F0EEDA, + (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9BD21AF2, + (q31_t)0xB0533055, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2, + (q31_t)0x9C4FBD92, (q31_t)0xAFB63667, (q31_t)0x9C8EEB33, + (q31_t)0xAF6803A1, (q31_t)0x9CCE562B, (q31_t)0xAF1A0293, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D4DE384, + (q31_t)0xAE7E965B, (q31_t)0x9D8E0596, (q31_t)0xAE312B91, + (q31_t)0x9DCE6462, (q31_t)0xADE3F33E, (q31_t)0x9E0EFFC1, + (q31_t)0xAD96ED91, (q31_t)0x9E4FD789, (q31_t)0xAD4A1ABA, + (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9ED23BB9, + (q31_t)0xACB10E4A, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510, + (q31_t)0x9F558FB0, (q31_t)0xAC18CF68, (q31_t)0x9F979331, + (q31_t)0xABCCFD82, (q31_t)0x9FD9D22A, (q31_t)0xAB815F8C, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA05F01E1, + (q31_t)0xAAEAC02B, (q31_t)0xA0A1F24C, (q31_t)0xAA9FBF1D, + (q31_t)0xA0E51D8C, (q31_t)0xAA54F2B9, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA16C23E1, (q31_t)0xA9BFF8A8, + (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA1F41391, + (q31_t)0xA92BD366, (q31_t)0xA2386283, (q31_t)0xA8E21106, + (q31_t)0xA27CEB4F, (q31_t)0xA8988463, (q31_t)0xA2C1ADC9, + (q31_t)0xA84F2DA9, (q31_t)0xA306A9C7, (q31_t)0xA8060D08, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3914DA7, + (q31_t)0xA7746EC0, (q31_t)0xA3D6F533, (q31_t)0xA72BF173, + (q31_t)0xA41CD598, (q31_t)0xA6E3AAF2, (q31_t)0xA462EEAC, + (q31_t)0xA69B9B68, (q31_t)0xA4A94042, (q31_t)0xA653C302, + (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA5368C4B, + (q31_t)0xA5C4B855, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xA5C4B855, (q31_t)0xA5368C4B, (q31_t)0xA60C21ED, + (q31_t)0xA4EFCA31, (q31_t)0xA653C302, (q31_t)0xA4A94042, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA6E3AAF2, + (q31_t)0xA41CD598, (q31_t)0xA72BF173, (q31_t)0xA3D6F533, + (q31_t)0xA7746EC0, (q31_t)0xA3914DA7, (q31_t)0xA7BD22AB, + (q31_t)0xA34BDF20, (q31_t)0xA8060D08, (q31_t)0xA306A9C7, + (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8988463, + (q31_t)0xA27CEB4F, (q31_t)0xA8E21106, (q31_t)0xA2386283, + (q31_t)0xA92BD366, (q31_t)0xA1F41391, (q31_t)0xA975CB56, + (q31_t)0xA1AFFEA2, (q31_t)0xA9BFF8A8, (q31_t)0xA16C23E1, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA54F2B9, + (q31_t)0xA0E51D8C, (q31_t)0xAA9FBF1D, (q31_t)0xA0A1F24C, + (q31_t)0xAAEAC02B, (q31_t)0xA05F01E1, (q31_t)0xAB35F5B5, + (q31_t)0xA01C4C72, (q31_t)0xAB815F8C, (q31_t)0x9FD9D22A, + (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC18CF68, + (q31_t)0x9F558FB0, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0, + (q31_t)0xACB10E4A, (q31_t)0x9ED23BB9, (q31_t)0xACFD7AE8, + (q31_t)0x9E90EB94, (q31_t)0xAD4A1ABA, (q31_t)0x9E4FD789, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xADE3F33E, + (q31_t)0x9DCE6462, (q31_t)0xAE312B91, (q31_t)0x9D8E0596, + (q31_t)0xAE7E965B, (q31_t)0x9D4DE384, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xAF1A0293, (q31_t)0x9CCE562B, + (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xAFB63667, + (q31_t)0x9C4FBD92, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70, + (q31_t)0xB0533055, (q31_t)0x9BD21AF2, (q31_t)0xB0A1F71C, + (q31_t)0x9B93A640, (q31_t)0xB0F0EEDA, (q31_t)0x9B556F80, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB18F7070, + (q31_t)0x9AD9BC71, (q31_t)0xB1DEF9E8, (q31_t)0x9A9C406D, + (q31_t)0xB22EB392, (q31_t)0x9A5F02F5, (q31_t)0xB27E9D3B, + (q31_t)0x9A22042C, (q31_t)0xB2CEB6B5, (q31_t)0x99E5443A, + (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB36F784E, + (q31_t)0x996C816F, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB410F6D2, (q31_t)0x98F4BBBC, (q31_t)0xB461FC70, + (q31_t)0x98B93828, (q31_t)0xB4B330B2, (q31_t)0x987DF449, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB556245E, + (q31_t)0x98082C3B, (q31_t)0xB5A7E362, (q31_t)0x97CDA855, + (q31_t)0xB5F9D042, (q31_t)0x979364B5, (q31_t)0xB64BEACC, + (q31_t)0x9759617E, (q31_t)0xB69E32CD, (q31_t)0x971F9ED6, + (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB7434A67, + (q31_t)0x96ACDBBD, (q31_t)0xB796199B, (q31_t)0x9673DB94, + (q31_t)0xB7E9157A, (q31_t)0x963B1C85, (q31_t)0xB83C3DD1, + (q31_t)0x96029EB5, (q31_t)0xB88F926C, (q31_t)0x95CA6246, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB936BFA3, + (q31_t)0x955AAE17, (q31_t)0xB98A97D8, (q31_t)0x9523369B, + (q31_t)0xB9DE9B83, (q31_t)0x94EC010B, (q31_t)0xBA32CA70, + (q31_t)0x94B50D87, (q31_t)0xBA87246C, (q31_t)0x947E5C32, + (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB3058C0, + (q31_t)0x9411C09D, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC2F6513, + (q31_t)0x9370CAE4, (q31_t)0xBC84BD1E, (q31_t)0x933BA968, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD2FE9E1, + (q31_t)0x92D22FD8, (q31_t)0xBD85BE2F, (q31_t)0x929DD805, + (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBE88304F, (q31_t)0x920265E4, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF3546A8, + (q31_t)0x919C1780, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC03A1368, + (q31_t)0x9104A0ED, (q31_t)0xC0915147, (q31_t)0x90D2ACD3, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1404233, + (q31_t)0x906F927B, (q31_t)0xC197F4D3, (q31_t)0x903E6C7A, + (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC29FF2D4, (q31_t)0x8FAC988E, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC350AF25, + (q31_t)0x8F4CBADB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC45AE1D7, + (q31_t)0x8EBEF7FB, (q31_t)0xC4B3E746, (q31_t)0x8E904298, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5665FA8, + (q31_t)0x8E33A9D9, (q31_t)0xC5BFD22E, (q31_t)0x8E05C6B7, + (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC6CD0079, (q31_t)0x8D7DC399, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7812571, + (q31_t)0x8D2477D8, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC89061BA, + (q31_t)0x8CA099D9, (q31_t)0xC8EB0FD6, (q31_t)0x8C753361, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9A0D1C4, + (q31_t)0x8C1F3C5C, (q31_t)0xC9FBE527, (q31_t)0x8BF4AC05, + (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCB0DE658, (q31_t)0x8B76A8E4, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCBC53578, + (q31_t)0x8B240E10, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCD91D3D, + (q31_t)0x8AAA42B4, (q31_t)0xCD355490, (q31_t)0x8A823A35, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDEE20FC, + (q31_t)0x8A3302BD, (q31_t)0xCE4AB5A2, (q31_t)0x8A0BD3F5, + (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xCF612AAA, (q31_t)0x8997FC89, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD01B6459, + (q31_t)0x894C2F4C, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD13397E1, + (q31_t)0x88DCA0D3, (q31_t)0xD191386D, (q31_t)0x88B80431, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD24CCF38, + (q31_t)0x886FA7C2, (q31_t)0xD2AAC504, (q31_t)0x884BE820, + (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD3C54D46, (q31_t)0x87E2649B, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD48230E8, + (q31_t)0x879D7F40, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD59E4EFE, + (q31_t)0x8738545E, (q31_t)0xD5FD3847, (q31_t)0x8717304E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD6BB585D, + (q31_t)0x86D5C802, (q31_t)0xD71A8EB5, (q31_t)0x86B583EE, + (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD838C82D, (q31_t)0x865678EA, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8F81439, + (q31_t)0x86189359, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xDA17BA4A, + (q31_t)0x85BDEF27, (q31_t)0xDA77CB62, (q31_t)0x85A04F28, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB3832CD, + (q31_t)0x8565F1B0, (q31_t)0xDB9888A8, (q31_t)0x8549345C, + (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDCBA1008, (q31_t)0x84F4C2D3, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD7B8220, + (q31_t)0x84BDF285, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE9E4C60, + (q31_t)0x846DF476, (q31_t)0xDEFF63F4, (q31_t)0x8453E2CE, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDFC1CFF2, + (q31_t)0x8420A46B, (q31_t)0xE02323E5, (q31_t)0x840777CF, + (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE14794B9, (q31_t)0x83BDBD0D, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE20AE9C1, + (q31_t)0x838E1507, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE330734C, + (q31_t)0x8348D8DB, (q31_t)0xE3926FAC, (q31_t)0x83325E97, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4569CCB, + (q31_t)0x8306510F, (q31_t)0xE4B8CD10, (q31_t)0x82F0BDE8, + (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE5DFC1E4, (q31_t)0x82B1D381, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6A4B616, + (q31_t)0x8289644A, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE7CC9917, + (q31_t)0x824F0208, (q31_t)0xE82F5844, (q31_t)0x823C26F2, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8F50273, + (q31_t)0x8217598F, (q31_t)0xE957ECFB, (q31_t)0x82056758, + (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEA80FF79, (q31_t)0x81D16320, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB474E80, + (q31_t)0x81B03AC1, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC71244F, + (q31_t)0x8180C6A9, (q31_t)0xECD48406, (q31_t)0x8171914E, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED9B66B2, + (q31_t)0x815410D3, (q31_t)0xEDFEE92B, (q31_t)0x8145C5C6, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xEF29B243, (q31_t)0x811CB9CA, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFF11752, + (q31_t)0x8102E3C3, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF11C789A, + (q31_t)0x80DE6E4C, (q31_t)0xF1805662, (q31_t)0x80D2E3F1, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2482C89, + (q31_t)0x80BCBA9C, (q31_t)0xF2AC246D, (q31_t)0x80B21BAF, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF3D83C76, (q31_t)0x8094162B, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF4A07260, + (q31_t)0x80819B74, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF5CCF743, + (q31_t)0x80683143, (q31_t)0xF6313076, (q31_t)0x806055EA, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6F9B4C5, + (q31_t)0x80518B6B, (q31_t)0xF75DFF65, (q31_t)0x804A9C4D, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF88AFE41, (q31_t)0x8037A7AC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF953BF90, + (q31_t)0x802C8EAD, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA80FFCB, + (q31_t)0x801E3894, (q31_t)0xFAE571A4, (q31_t)0x801A0EF7, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFBAE5E89, + (q31_t)0x8012A86F, (q31_t)0xFC12D919, (q31_t)0x800F6B88, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFD40565B, (q31_t)0x80078E5E, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE095D69, + (q31_t)0x8003DAF0, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF36F078, + (q31_t)0x80009DE9, (q31_t)0xFF9B781D, (q31_t)0x8000277A +}; + +/** +* \par +* Example code for Q31 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 4096 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to Q31(Fixed point 1.31): +* round(twiddleCoefQ31(i) * pow(2, 31)) +* +*/ +const q31_t twiddleCoef_4096_q31[6144] = +{ + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFF621, + (q31_t)0x003243F5, (q31_t)0x7FFFD885, (q31_t)0x006487E3, + (q31_t)0x7FFFA72C, (q31_t)0x0096CBC1, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFF0942, (q31_t)0x00FB532F, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFE1C64, + (q31_t)0x015FDA03, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFCE093, (q31_t)0x01C45FFE, (q31_t)0x7FFC250F, + (q31_t)0x01F6A296, (q31_t)0x7FFB55CE, (q31_t)0x0228E4E1, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF97C17, + (q31_t)0x028D6870, (q31_t)0x7FF871A1, (q31_t)0x02BFA9A4, + (q31_t)0x7FF7536F, (q31_t)0x02F1EA6B, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF4DBD8, (q31_t)0x03566A96, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF21553, + (q31_t)0x03BAE8B1, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FEEFFE1, (q31_t)0x041F647F, (q31_t)0x7FED5790, + (q31_t)0x0451A176, (q31_t)0x7FEB9B85, (q31_t)0x0483DDC3, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE7E840, + (q31_t)0x04E8543D, (q31_t)0x7FE5F108, (q31_t)0x051A8E5C, + (q31_t)0x7FE3E616, (q31_t)0x054CC7B0, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FDF9508, (q31_t)0x05B137DF, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FDAF518, + (q31_t)0x0615A48A, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FD6064B, (q31_t)0x067A0D75, (q31_t)0x7FD37152, + (q31_t)0x06AC406F, (q31_t)0x7FD0C8A3, (q31_t)0x06DE7261, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FCB3C23, + (q31_t)0x0742D310, (q31_t)0x7FC85853, (q31_t)0x077501BE, + (q31_t)0x7FC560CF, (q31_t)0x07A72F45, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FBF36A9, (q31_t)0x080B86C1, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB8BDB7, + (q31_t)0x086FD947, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FB1F5FC, (q31_t)0x08D42698, (q31_t)0x7FAE7494, + (q31_t)0x09064B3A, (q31_t)0x7FAADF7C, (q31_t)0x09386E77, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7FA37A3C, + (q31_t)0x099CB0A7, (q31_t)0x7F9FAA15, (q31_t)0x09CECF89, + (q31_t)0x7F9BC63F, (q31_t)0x0A00ECE8, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F93C38C, (q31_t)0x0A6522FE, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F8B7226, + (q31_t)0x0AC952AA, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F82D214, (q31_t)0x0B2D7BAE, (q31_t)0x7F7E648B, + (q31_t)0x0B5F8D9F, (q31_t)0x7F79E35A, (q31_t)0x0B919DCE, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F70A5FD, + (q31_t)0x0BF5B8CB, (q31_t)0x7F6BE9D4, (q31_t)0x0C27C389, + (q31_t)0x7F671A04, (q31_t)0x0C59CC67, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F5D3F75, (q31_t)0x0CBDD865, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F531654, + (q31_t)0x0D21DC87, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + (q31_t)0x7F489EAA, (q31_t)0x0D85D88F, (q31_t)0x7F434563, + (q31_t)0x0DB7D376, (q31_t)0x7F3DD87C, (q31_t)0x0DE9CC3F, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F32C3D0, + (q31_t)0x0E4DB75B, (q31_t)0x7F2D1C0E, (q31_t)0x0E7FA99D, + (q31_t)0x7F2760AF, (q31_t)0x0EB199A3, (q31_t)0x7F2191B4, + (q31_t)0x0EE38765, (q31_t)0x7F1BAF1E, (q31_t)0x0F1572DC, + (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0FAF24, + (q31_t)0x0F7942C6, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7F0360CB, (q31_t)0x0FDD0925, (q31_t)0x7EFD1C3C, + (q31_t)0x100EE8AD, (q31_t)0x7EF6C418, (q31_t)0x1040C5BB, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE9D913, + (q31_t)0x10A4784A, (q31_t)0x7EE34635, (q31_t)0x10D64DBC, + (q31_t)0x7EDC9FC6, (q31_t)0x11082096, (q31_t)0x7ED5E5C6, + (q31_t)0x1139F0CE, (q31_t)0x7ECF1837, (q31_t)0x116BBE5F, + (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EC1426F, + (q31_t)0x11CF516A, (q31_t)0x7EBA3A39, (q31_t)0x120116D4, + (q31_t)0x7EB31E77, (q31_t)0x1232D978, (q31_t)0x7EABEF2C, + (q31_t)0x1264994E, (q31_t)0x7EA4AC58, (q31_t)0x1296564D, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E95EC19, + (q31_t)0x12F9C7AA, (q31_t)0x7E8E6EB1, (q31_t)0x132B7BF9, + (q31_t)0x7E86DDC5, (q31_t)0x135D2D53, (q31_t)0x7E7F3956, + (q31_t)0x138EDBB0, (q31_t)0x7E778165, (q31_t)0x13C0870A, + (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E67D702, + (q31_t)0x1423D492, (q31_t)0x7E5FE493, (q31_t)0x145576B1, + (q31_t)0x7E57DEA6, (q31_t)0x148715AD, (q31_t)0x7E4FC53E, + (q31_t)0x14B8B17F, (q31_t)0x7E47985B, (q31_t)0x14EA4A1F, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E37042A, + (q31_t)0x154D71AA, (q31_t)0x7E2E9CDF, (q31_t)0x157F0086, + (q31_t)0x7E26221E, (q31_t)0x15B08C11, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7E14F242, (q31_t)0x16139917, + (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7E03749F, + (q31_t)0x1676987F, (q31_t)0x7DFA98A7, (q31_t)0x16A81305, + (q31_t)0x7DF1A942, (q31_t)0x16D98A0C, (q31_t)0x7DE8A670, + (q31_t)0x170AFD8D, (q31_t)0x7DDF9034, (q31_t)0x173C6D80, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DCD2981, + (q31_t)0x179F429F, (q31_t)0x7DC3D90D, (q31_t)0x17D0A7BB, + (q31_t)0x7DBA7534, (q31_t)0x1802092C, (q31_t)0x7DB0FDF7, + (q31_t)0x183366E8, (q31_t)0x7DA77359, (q31_t)0x1864C0E9, + (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D9423FB, + (q31_t)0x18C7699B, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7D808727, (q31_t)0x192A0303, (q31_t)0x7D769BB5, + (q31_t)0x195B49E9, (q31_t)0x7D6C9CE9, (q31_t)0x198C8CE6, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D58654C, + (q31_t)0x19EF0706, (q31_t)0x7D4E2C7E, (q31_t)0x1A203E1B, + (q31_t)0x7D43E05E, (q31_t)0x1A517127, (q31_t)0x7D3980EC, + (q31_t)0x1A82A025, (q31_t)0x7D2F0E2A, (q31_t)0x1AB3CB0C, + (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D19EEBE, + (q31_t)0x1B161479, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF, + (q31_t)0x7D048228, (q31_t)0x1B784D30, (q31_t)0x7CF9AEF0, + (q31_t)0x1BA96334, (q31_t)0x7CEEC873, (q31_t)0x1BDA74F5, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CD8C1AD, + (q31_t)0x1C3C8B8C, (q31_t)0x7CCDA168, (q31_t)0x1C6D9053, + (q31_t)0x7CC26DE5, (q31_t)0x1C9E90B8, (q31_t)0x7CB72724, + (q31_t)0x1CCF8CB3, (q31_t)0x7CABCD27, (q31_t)0x1D00843C, + (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C94DF82, + (q31_t)0x1D6265DD, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5, + (q31_t)0x7C7DA504, (q31_t)0x1DC4355D, (q31_t)0x7C71EAF8, + (q31_t)0x1DF5163F, (q31_t)0x7C661DBB, (q31_t)0x1E25F281, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4E49B6, + (q31_t)0x1E879D0C, (q31_t)0x7C4242F2, (q31_t)0x1EB86B46, + (q31_t)0x7C362904, (q31_t)0x1EE934C2, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7C1DBBB2, (q31_t)0x1F4AB967, + (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7C0501D1, + (q31_t)0x1FAC2ABF, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A, + (q31_t)0x7BEBFB70, (q31_t)0x200D888C, (q31_t)0x7BDF5B94, + (q31_t)0x203E300D, (q31_t)0x7BD2A89E, (q31_t)0x206ED295, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BB9096A, + (q31_t)0x20D0089B, (q31_t)0x7BAC1D31, (q31_t)0x21009C0B, + (q31_t)0x7B9F1DE5, (q31_t)0x21312A65, (q31_t)0x7B920B89, + (q31_t)0x2161B39F, (q31_t)0x7B84E61E, (q31_t)0x219237B4, + (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B6A6227, + (q31_t)0x21F3304E, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7B4F920E, (q31_t)0x225413F8, (q31_t)0x7B420D7A, + (q31_t)0x22847DDF, (q31_t)0x7B3475E4, (q31_t)0x22B4E274, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B190DBB, + (q31_t)0x23159B87, (q31_t)0x7B0B3D2C, (q31_t)0x2345EFF7, + (q31_t)0x7AFD59A3, (q31_t)0x23763EF7, (q31_t)0x7AEF6323, + (q31_t)0x23A6887E, (q31_t)0x7AE159AE, (q31_t)0x23D6CC86, + (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AC50DEB, + (q31_t)0x243743FA, (q31_t)0x7AB6CBA3, (q31_t)0x24677757, + (q31_t)0x7AA8766E, (q31_t)0x2497A517, (q31_t)0x7A9A0E4F, + (q31_t)0x24C7CD32, (q31_t)0x7A8B9348, (q31_t)0x24F7EFA1, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A6E648A, + (q31_t)0x2558235E, (q31_t)0x7A5FB0D8, (q31_t)0x2588349D, + (q31_t)0x7A50EA46, (q31_t)0x25B84012, (q31_t)0x7A4210D8, + (q31_t)0x25E845B5, (q31_t)0x7A33248F, (q31_t)0x26184581, + (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A151377, + (q31_t)0x26783370, (q31_t)0x7A05EEAD, (q31_t)0x26A82185, + (q31_t)0x79F6B711, (q31_t)0x26D809A5, (q31_t)0x79E76CA6, + (q31_t)0x2707EBC6, (q31_t)0x79D80F6F, (q31_t)0x2737C7E3, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79B91CA4, + (q31_t)0x27976DF1, (q31_t)0x79A98715, (q31_t)0x27C737D2, + (q31_t)0x7999DEC3, (q31_t)0x27F6FB92, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x797A55E0, (q31_t)0x2856708C, + (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x795A820E, + (q31_t)0x28B5CCA5, (q31_t)0x794A7C11, (q31_t)0x28E5714A, + (q31_t)0x793A6360, (q31_t)0x29150FA1, (q31_t)0x792A37FE, + (q31_t)0x2944A7A2, (q31_t)0x7919F9EB, (q31_t)0x29743945, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78F945C3, + (q31_t)0x29D34958, (q31_t)0x78E8CFB1, (q31_t)0x2A02C7B8, + (q31_t)0x78D846FB, (q31_t)0x2A323F9D, (q31_t)0x78C7ABA1, + (q31_t)0x2A61B101, (q31_t)0x78B6FDA8, (q31_t)0x2A911BDB, + (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x789569DE, + (q31_t)0x2AEFDDD8, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x78738BB3, (q31_t)0x2B4E8558, (q31_t)0x786280BF, + (q31_t)0x2B7DCF17, (q31_t)0x7851633B, (q31_t)0x2BAD1221, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x782EF08B, + (q31_t)0x2C0B83F9, (q31_t)0x781D9B64, (q31_t)0x2C3AB2B9, + (q31_t)0x780C33B8, (q31_t)0x2C69DAA6, (q31_t)0x77FAB988, + (q31_t)0x2C98FBBA, (q31_t)0x77E92CD8, (q31_t)0x2CC815ED, + (q31_t)0x77D78DAA, (q31_t)0x2CF72939, (q31_t)0x77C5DC01, + (q31_t)0x2D263595, (q31_t)0x77B417DF, (q31_t)0x2D553AFB, + (q31_t)0x77A24148, (q31_t)0x2D843963, (q31_t)0x7790583D, + (q31_t)0x2DB330C7, (q31_t)0x777E5CC3, (q31_t)0x2DE2211E, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x775A2E88, + (q31_t)0x2E3FEC8B, (q31_t)0x7747FBCE, (q31_t)0x2E6EC792, + (q31_t)0x7735B6AE, (q31_t)0x2E9D9B70, (q31_t)0x77235F2D, + (q31_t)0x2ECC681E, (q31_t)0x7710F54B, (q31_t)0x2EFB2D94, + (q31_t)0x76FE790E, (q31_t)0x2F29EBCC, (q31_t)0x76EBEA77, + (q31_t)0x2F58A2BD, (q31_t)0x76D94988, (q31_t)0x2F875262, + (q31_t)0x76C69646, (q31_t)0x2FB5FAB2, (q31_t)0x76B3D0B3, + (q31_t)0x2FE49BA6, (q31_t)0x76A0F8D2, (q31_t)0x30133538, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x767B1230, + (q31_t)0x30705217, (q31_t)0x76680376, (q31_t)0x309ED555, + (q31_t)0x7654E279, (q31_t)0x30CD5114, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x762E69C3, (q31_t)0x312A31F8, + (q31_t)0x761B1211, (q31_t)0x3158970D, (q31_t)0x7607A827, + (q31_t)0x3186F487, (q31_t)0x75F42C0A, (q31_t)0x31B54A5D, + (q31_t)0x75E09DBD, (q31_t)0x31E39889, (q31_t)0x75CCFD42, + (q31_t)0x3211DF03, (q31_t)0x75B94A9C, (q31_t)0x32401DC5, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7591AEDD, + (q31_t)0x329C8402, (q31_t)0x757DC5CA, (q31_t)0x32CAAB6F, + (q31_t)0x7569CA98, (q31_t)0x32F8CB07, (q31_t)0x7555BD4B, + (q31_t)0x3326E2C2, (q31_t)0x75419DE6, (q31_t)0x3354F29A, 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(q31_t)0x81B03AC1, (q31_t)0xEB474E80, (q31_t)0x81B867A4, + (q31_t)0xEB15B5E0, (q31_t)0x81C0A801, (q31_t)0xEAE4207A, + (q31_t)0x81C8FBD5, (q31_t)0xEAB28E55, (q31_t)0x81D16320, + (q31_t)0xEA80FF79, (q31_t)0x81D9DDE1, (q31_t)0xEA4F73EE, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x81EB0DBD, + (q31_t)0xE9EC66E8, (q31_t)0x81F3C2D7, (q31_t)0xE9BAE57C, + (q31_t)0x81FC8B60, (q31_t)0xE9896780, (q31_t)0x82056758, + (q31_t)0xE957ECFB, (q31_t)0x820E56BE, (q31_t)0xE92675F4, + (q31_t)0x8217598F, (q31_t)0xE8F50273, (q31_t)0x82206FCB, + (q31_t)0xE8C3927F, (q31_t)0x82299971, (q31_t)0xE8922621, + (q31_t)0x8232D67E, (q31_t)0xE860BD60, (q31_t)0x823C26F2, + (q31_t)0xE82F5844, (q31_t)0x82458ACB, (q31_t)0xE7FDF6D3, + (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x82588CA6, + (q31_t)0xE79B3F16, (q31_t)0x82622AA5, (q31_t)0xE769E8D8, + (q31_t)0x826BDC04, (q31_t)0xE7389664, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x827F78D8, (q31_t)0xE6D5FCFC, + (q31_t)0x8289644A, (q31_t)0xE6A4B616, (q31_t)0x82936316, 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(q31_t)0xE1A935E1, + (q31_t)0x83B1B649, (q31_t)0xE17862F3, (q31_t)0x83BDBD0D, + (q31_t)0xE14794B9, (q31_t)0x83C9D6FB, (q31_t)0xE116CB3D, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x83E2444D, + (q31_t)0xE0B54698, (q31_t)0x83EE97AC, (q31_t)0xE0848B7F, + (q31_t)0x83FAFE2E, (q31_t)0xE053D541, (q31_t)0x840777CF, + (q31_t)0xE02323E5, (q31_t)0x8414048F, (q31_t)0xDFF27773, + (q31_t)0x8420A46B, (q31_t)0xDFC1CFF2, (q31_t)0x842D5761, + (q31_t)0xDF912D6A, (q31_t)0x843A1D70, (q31_t)0xDF608FE3, + (q31_t)0x8446F695, (q31_t)0xDF2FF764, (q31_t)0x8453E2CE, + (q31_t)0xDEFF63F4, (q31_t)0x8460E21A, (q31_t)0xDECED59B, + (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x847B19E1, + (q31_t)0xDE6DC84B, (q31_t)0x84885257, (q31_t)0xDE3D4963, + (q31_t)0x84959DD9, (q31_t)0xDE0CCFB1, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x84B06DF1, (q31_t)0xDDABEC07, + (q31_t)0x84BDF285, (q31_t)0xDD7B8220, (q31_t)0x84CB8A1B, + (q31_t)0xDD4B1D8B, (q31_t)0x84D934B0, (q31_t)0xDD1ABE51, + (q31_t)0x84E6F244, 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(q31_t)0xE4E9EB86, (q31_t)0x82E61141, + (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE54C34F3, + (q31_t)0x82D0F1D5, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13, + (q31_t)0xE5AE8ED8, (q31_t)0x82BC1FA1, (q31_t)0xE5DFC1E4, + (q31_t)0x82B1D381, (q31_t)0xE610F8F9, (q31_t)0x82A79AB3, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6737319, + (q31_t)0x82936316, (q31_t)0xE6A4B616, (q31_t)0x8289644A, + (q31_t)0xE6D5FCFC, (q31_t)0x827F78D8, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xE7389664, (q31_t)0x826BDC04, + (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE79B3F16, + (q31_t)0x82588CA6, (q31_t)0xE7CC9917, (q31_t)0x824F0208, + (q31_t)0xE7FDF6D3, (q31_t)0x82458ACB, (q31_t)0xE82F5844, + (q31_t)0x823C26F2, (q31_t)0xE860BD60, (q31_t)0x8232D67E, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8C3927F, + (q31_t)0x82206FCB, (q31_t)0xE8F50273, (q31_t)0x8217598F, + (q31_t)0xE92675F4, (q31_t)0x820E56BE, (q31_t)0xE957ECFB, + (q31_t)0x82056758, (q31_t)0xE9896780, (q31_t)0x81FC8B60, + (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xE9EC66E8, + (q31_t)0x81EB0DBD, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEA4F73EE, (q31_t)0x81D9DDE1, (q31_t)0xEA80FF79, + (q31_t)0x81D16320, (q31_t)0xEAB28E55, (q31_t)0x81C8FBD5, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB15B5E0, + (q31_t)0x81B867A4, (q31_t)0xEB474E80, (q31_t)0x81B03AC1, + (q31_t)0xEB78EA52, (q31_t)0x81A82159, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEBDC2B6D, (q31_t)0x819828FD, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC3F78F5, + (q31_t)0x81887E9A, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xECA2D2AC, (q31_t)0x8179223A, (q31_t)0xECD48406, + (q31_t)0x8171914E, (q31_t)0xED063855, (q31_t)0x816A13E6, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED69A9B2, + (q31_t)0x815B53A8, (q31_t)0xED9B66B2, (q31_t)0x815410D3, + (q31_t)0xEDCD2687, (q31_t)0x814CE188, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEE30AE95, (q31_t)0x813EBD90, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEE9441A0, + (q31_t)0x8130E7C8, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEEF7DF6A, (q31_t)0x81236039, (q31_t)0xEF29B243, + (q31_t)0x811CB9CA, (q31_t)0xEF5B87B5, (q31_t)0x811626EC, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFBF3A44, + (q31_t)0x81093BE8, (q31_t)0xEFF11752, (q31_t)0x8102E3C3, + (q31_t)0xF022F6DA, (q31_t)0x80FC9F35, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF086BD39, (q31_t)0x80F050DB, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF0EA8D23, + (q31_t)0x80E450E2, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF14E665C, (q31_t)0x80D89F51, (q31_t)0xF1805662, + (q31_t)0x80D2E3F1, (q31_t)0xF1B248A5, (q31_t)0x80CD3C2F, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF21633C0, + (q31_t)0x80C22783, (q31_t)0xF2482C89, (q31_t)0x80BCBA9C, + (q31_t)0xF27A2770, (q31_t)0x80B76155, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF2DE2378, (q31_t)0x80ACE9AB, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF342279A, + (q31_t)0x80A2C08B, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF3A63398, (q31_t)0x8098E5FB, (q31_t)0xF3D83C76, + (q31_t)0x8094162B, (q31_t)0xF40A4734, (q31_t)0x808F5A02, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF46E6231, + (q31_t)0x80861CA5, (q31_t)0xF4A07260, (q31_t)0x80819B74, + (q31_t)0xF4D28451, (q31_t)0x807D2DEB, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF536AD55, (q31_t)0x80748DD9, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF59ADD01, + (q31_t)0x806C3C73, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF5FF1317, (q31_t)0x806439C0, (q31_t)0xF6313076, + (q31_t)0x806055EA, (q31_t)0xF6634F58, (q31_t)0x805C85C3, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6C79188, + (q31_t)0x80552083, (q31_t)0xF6F9B4C5, (q31_t)0x80518B6B, + (q31_t)0xF72BD967, (q31_t)0x804E0A03, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF79026B8, (q31_t)0x80474248, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF7F4793E, + (q31_t)0x8040C956, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF858D0BA, (q31_t)0x803A9F31, (q31_t)0xF88AFE41, + (q31_t)0x8037A7AC, (q31_t)0xF8BD2CEF, (q31_t)0x8034C3DC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9218D9E, + (q31_t)0x802F375C, (q31_t)0xF953BF90, (q31_t)0x802C8EAD, + (q31_t)0xF985F28A, (q31_t)0x8029F9B4, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xF9EA5B75, (q31_t)0x80250AE7, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA4EC820, + (q31_t)0x80206AF8, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFAB3384F, (q31_t)0x801C19E9, (q31_t)0xFAE571A4, + (q31_t)0x801A0EF7, (q31_t)0xFB17ABC2, (q31_t)0x801817BF, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFB7C223C, + (q31_t)0x8014647A, (q31_t)0xFBAE5E89, (q31_t)0x8012A86F, + (q31_t)0xFBE09B80, (q31_t)0x8011001E, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFC45174E, (q31_t)0x800DEAAC, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCA99569, + (q31_t)0x800B2427, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFD0E1594, (q31_t)0x8008AC90, (q31_t)0xFD40565B, + (q31_t)0x80078E5E, (q31_t)0xFD72978F, (q31_t)0x800683E8, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFDD71B1E, + (q31_t)0x8004AA31, (q31_t)0xFE095D69, (q31_t)0x8003DAF0, + (q31_t)0xFE3BA001, (q31_t)0x80031F6C, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFEA025FC, (q31_t)0x8001E39B, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF04ACD0, + (q31_t)0x8000F6BD, (q31_t)0xFF36F078, (q31_t)0x80009DE9, + (q31_t)0xFF69343E, (q31_t)0x800058D3, (q31_t)0xFF9B781D, + (q31_t)0x8000277A, (q31_t)0xFFCDBC0A, (q31_t)0x800009DE +}; + + + +/* +* @brief q15 Twiddle factors Table +*/ + + +/** +* \par +* Example code for q15 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 16 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to q15(Fixed point 1.15): +* round(twiddleCoefq15(i) * pow(2, 15)) +* +*/ +const q15_t twiddleCoef_16_q15[24] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xCF04, (q15_t)0x89BE +}; + +/** +* \par +* Example code for q15 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 32 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to q15(Fixed point 1.15): +* round(twiddleCoefq15(i) * pow(2, 15)) +* +*/ +const q15_t twiddleCoef_32_q15[48] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7D8A, (q15_t)0x18F8, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x6A6D, (q15_t)0x471C, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x471C, (q15_t)0x6A6D, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x18F8, (q15_t)0x7D8A, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xE707, (q15_t)0x7D8A, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xB8E3, (q15_t)0x6A6D, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x9592, (q15_t)0x471C, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8275, (q15_t)0x18F8, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x8275, (q15_t)0xE707, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0x9592, (q15_t)0xB8E3, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xB8E3, (q15_t)0x9592, + (q15_t)0xCF04, (q15_t)0x89BE, + (q15_t)0xE707, (q15_t)0x8275 +}; + +/** +* \par +* Example code for q15 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 64 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to q15(Fixed point 1.15): +* round(twiddleCoefq15(i) * pow(2, 15)) +* +*/ +const q15_t twiddleCoef_64_q15[96] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7F62, (q15_t)0x0C8B, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7A7D, (q15_t)0x2528, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x70E2, (q15_t)0x3C56, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x62F2, (q15_t)0x5133, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5133, (q15_t)0x62F2, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x3C56, (q15_t)0x70E2, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2528, (q15_t)0x7A7D, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x0C8B, (q15_t)0x7F62, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF374, (q15_t)0x7F62, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xDAD7, (q15_t)0x7A7D, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC3A9, (q15_t)0x70E2, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xAECC, (q15_t)0x62F2, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0x9D0D, (q15_t)0x5133, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x8F1D, (q15_t)0x3C56, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8582, (q15_t)0x2528, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x809D, (q15_t)0x0C8B, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x809D, (q15_t)0xF374, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8582, (q15_t)0xDAD7, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8F1D, (q15_t)0xC3A9, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9D0D, (q15_t)0xAECC, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAECC, (q15_t)0x9D0D, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xC3A9, (q15_t)0x8F1D, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xDAD7, (q15_t)0x8582, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xF374, (q15_t)0x809D +}; + +/** +* \par +* Example code for q15 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 128 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to q15(Fixed point 1.15): +* round(twiddleCoefq15(i) * pow(2, 15)) +* +*/ +const q15_t twiddleCoef_128_q15[192] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FD8, (q15_t)0x0647, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7E9D, (q15_t)0x12C8, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7C29, (q15_t)0x1F19, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7884, (q15_t)0x2B1F, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x73B5, (q15_t)0x36BA, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6DCA, (q15_t)0x41CE, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x66CF, (q15_t)0x4C3F, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x5ED7, (q15_t)0x55F5, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x55F5, (q15_t)0x5ED7, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4C3F, (q15_t)0x66CF, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x41CE, (q15_t)0x6DCA, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x36BA, (q15_t)0x73B5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2B1F, (q15_t)0x7884, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x1F19, (q15_t)0x7C29, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x12C8, (q15_t)0x7E9D, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0647, (q15_t)0x7FD8, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF9B8, (q15_t)0x7FD8, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xED37, (q15_t)0x7E9D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE0E6, (q15_t)0x7C29, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD4E0, (q15_t)0x7884, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC945, (q15_t)0x73B5, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xBE31, (q15_t)0x6DCA, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB3C0, (q15_t)0x66CF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAA0A, (q15_t)0x5ED7, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA128, (q15_t)0x55F5, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9930, (q15_t)0x4C3F, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9235, (q15_t)0x41CE, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8C4A, (q15_t)0x36BA, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x877B, (q15_t)0x2B1F, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x83D6, (q15_t)0x1F19, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8162, (q15_t)0x12C8, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8027, (q15_t)0x0647, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8027, (q15_t)0xF9B8, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x8162, (q15_t)0xED37, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x83D6, (q15_t)0xE0E6, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x877B, (q15_t)0xD4E0, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8C4A, (q15_t)0xC945, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x9235, (q15_t)0xBE31, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9930, (q15_t)0xB3C0, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0xA128, (q15_t)0xAA0A, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAA0A, (q15_t)0xA128, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB3C0, (q15_t)0x9930, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBE31, (q15_t)0x9235, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC945, (q15_t)0x8C4A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD4E0, (q15_t)0x877B, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xE0E6, (q15_t)0x83D6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xED37, (q15_t)0x8162, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF9B8, (q15_t)0x8027 +}; + +/** +* \par +* Example code for q15 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 256 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to q15(Fixed point 1.15): +* round(twiddleCoefq15(i) * pow(2, 15)) +* +*/ +const q15_t twiddleCoef_256_q15[384] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FF6, (q15_t)0x0324, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FA7, (q15_t)0x096A, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F09, (q15_t)0x0FAB, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E1D, (q15_t)0x15E2, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7CE3, (q15_t)0x1C0B, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7B5D, (q15_t)0x2223, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x798A, (q15_t)0x2826, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x776C, (q15_t)0x2E11, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x7504, (q15_t)0x33DE, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7255, (q15_t)0x398C, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6F5F, (q15_t)0x3F17, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6C24, (q15_t)0x447A, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x68A6, (q15_t)0x49B4, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x64E8, (q15_t)0x4EBF, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x60EC, (q15_t)0x539B, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5CB4, (q15_t)0x5842, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5842, (q15_t)0x5CB4, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x539B, (q15_t)0x60EC, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4EBF, (q15_t)0x64E8, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x49B4, (q15_t)0x68A6, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x447A, (q15_t)0x6C24, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x3F17, (q15_t)0x6F5F, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x398C, (q15_t)0x7255, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x33DE, (q15_t)0x7504, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2E11, (q15_t)0x776C, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2826, (q15_t)0x798A, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2223, (q15_t)0x7B5D, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1C0B, (q15_t)0x7CE3, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x15E2, (q15_t)0x7E1D, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x0FAB, (q15_t)0x7F09, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x096A, (q15_t)0x7FA7, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0324, (q15_t)0x7FF6, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFCDB, (q15_t)0x7FF6, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF695, (q15_t)0x7FA7, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF054, (q15_t)0x7F09, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEA1D, (q15_t)0x7E1D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE3F4, (q15_t)0x7CE3, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDDDC, (q15_t)0x7B5D, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD7D9, (q15_t)0x798A, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD1EE, (q15_t)0x776C, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCC21, (q15_t)0x7504, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC673, (q15_t)0x7255, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC0E8, (q15_t)0x6F5F, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBB85, (q15_t)0x6C24, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB64B, (q15_t)0x68A6, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB140, (q15_t)0x64E8, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAC64, (q15_t)0x60EC, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA7BD, (q15_t)0x5CB4, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA34B, (q15_t)0x5842, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0x9F13, (q15_t)0x539B, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9B17, (q15_t)0x4EBF, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9759, (q15_t)0x49B4, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x93DB, (q15_t)0x447A, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x90A0, (q15_t)0x3F17, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8DAA, (q15_t)0x398C, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8AFB, (q15_t)0x33DE, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8893, (q15_t)0x2E11, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8675, (q15_t)0x2826, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x84A2, (q15_t)0x2223, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x831C, (q15_t)0x1C0B, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x81E2, (q15_t)0x15E2, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x80F6, (q15_t)0x0FAB, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8058, (q15_t)0x096A, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8009, (q15_t)0x0324, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8009, (q15_t)0xFCDB, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8058, (q15_t)0xF695, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80F6, (q15_t)0xF054, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81E2, (q15_t)0xEA1D, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x831C, (q15_t)0xE3F4, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x84A2, (q15_t)0xDDDC, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8675, (q15_t)0xD7D9, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8893, (q15_t)0xD1EE, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8AFB, (q15_t)0xCC21, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8DAA, (q15_t)0xC673, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x90A0, (q15_t)0xC0E8, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x93DB, (q15_t)0xBB85, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9759, (q15_t)0xB64B, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9B17, (q15_t)0xB140, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9F13, (q15_t)0xAC64, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA34B, (q15_t)0xA7BD, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA7BD, (q15_t)0xA34B, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAC64, (q15_t)0x9F13, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB140, (q15_t)0x9B17, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB64B, (q15_t)0x9759, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBB85, (q15_t)0x93DB, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xC0E8, (q15_t)0x90A0, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC673, (q15_t)0x8DAA, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCC21, (q15_t)0x8AFB, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD1EE, (q15_t)0x8893, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD7D9, (q15_t)0x8675, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDDDC, (q15_t)0x84A2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE3F4, (q15_t)0x831C, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xEA1D, (q15_t)0x81E2, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xF054, (q15_t)0x80F6, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF695, (q15_t)0x8058, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFCDB, (q15_t)0x8009 +}; + +/** +* \par +* Example code for q15 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 512 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to q15(Fixed point 1.15): +* round(twiddleCoefq15(i) * pow(2, 15)) +* +*/ +const q15_t twiddleCoef_512_q15[768] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFD, (q15_t)0x0192, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FE9, (q15_t)0x04B6, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FC2, (q15_t)0x07D9, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F87, (q15_t)0x0AFB, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F38, (q15_t)0x0E1B, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7ED5, (q15_t)0x1139, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E5F, (q15_t)0x1455, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DD6, (q15_t)0x176D, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D39, (q15_t)0x1A82, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7C89, (q15_t)0x1D93, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BC5, (q15_t)0x209F, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7AEF, (q15_t)0x23A6, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A05, (q15_t)0x26A8, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x7909, (q15_t)0x29A3, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x77FA, (q15_t)0x2C98, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x76D9, (q15_t)0x2F87, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75A5, (q15_t)0x326E, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x745F, (q15_t)0x354D, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7307, (q15_t)0x3824, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x719E, (q15_t)0x3AF2, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7023, (q15_t)0x3DB8, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6E96, (q15_t)0x4073, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6CF9, (q15_t)0x4325, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6B4A, (q15_t)0x45CD, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x698C, (q15_t)0x4869, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x67BD, (q15_t)0x4AFB, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x65DD, (q15_t)0x4D81, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x63EF, (q15_t)0x4FFB, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x61F1, (q15_t)0x5269, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x5FE3, (q15_t)0x54CA, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5DC7, (q15_t)0x571D, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5B9D, (q15_t)0x5964, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5964, (q15_t)0x5B9D, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x571D, (q15_t)0x5DC7, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x54CA, (q15_t)0x5FE3, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5269, (q15_t)0x61F1, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4FFB, (q15_t)0x63EF, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4D81, (q15_t)0x65DD, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4AFB, (q15_t)0x67BD, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4869, (q15_t)0x698C, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x45CD, (q15_t)0x6B4A, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4325, (q15_t)0x6CF9, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4073, (q15_t)0x6E96, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3DB8, (q15_t)0x7023, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3AF2, (q15_t)0x719E, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3824, (q15_t)0x7307, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x354D, (q15_t)0x745F, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x326E, (q15_t)0x75A5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2F87, (q15_t)0x76D9, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2C98, (q15_t)0x77FA, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x29A3, (q15_t)0x7909, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x26A8, (q15_t)0x7A05, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x23A6, (q15_t)0x7AEF, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x209F, (q15_t)0x7BC5, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1D93, (q15_t)0x7C89, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1A82, (q15_t)0x7D39, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x176D, (q15_t)0x7DD6, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x1455, (q15_t)0x7E5F, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1139, (q15_t)0x7ED5, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0E1B, (q15_t)0x7F38, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0AFB, (q15_t)0x7F87, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x07D9, (q15_t)0x7FC2, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x04B6, (q15_t)0x7FE9, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x0192, (q15_t)0x7FFD, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFE6D, (q15_t)0x7FFD, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFB49, (q15_t)0x7FE9, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF826, (q15_t)0x7FC2, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF504, (q15_t)0x7F87, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF1E4, (q15_t)0x7F38, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEEC6, (q15_t)0x7ED5, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEBAA, (q15_t)0x7E5F, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE892, (q15_t)0x7DD6, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE57D, (q15_t)0x7D39, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE26C, (q15_t)0x7C89, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDF60, (q15_t)0x7BC5, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDC59, (q15_t)0x7AEF, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD957, (q15_t)0x7A05, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD65C, (q15_t)0x7909, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD367, (q15_t)0x77FA, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD078, (q15_t)0x76D9, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCD91, (q15_t)0x75A5, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCAB2, (q15_t)0x745F, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC7DB, (q15_t)0x7307, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC50D, (q15_t)0x719E, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC247, (q15_t)0x7023, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xBF8C, (q15_t)0x6E96, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBCDA, (q15_t)0x6CF9, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBA32, (q15_t)0x6B4A, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB796, (q15_t)0x698C, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB504, (q15_t)0x67BD, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB27E, (q15_t)0x65DD, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB004, (q15_t)0x63EF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAD96, (q15_t)0x61F1, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAB35, (q15_t)0x5FE3, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA8E2, (q15_t)0x5DC7, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA69B, (q15_t)0x5B9D, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA462, (q15_t)0x5964, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA238, (q15_t)0x571D, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA01C, (q15_t)0x54CA, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E0E, (q15_t)0x5269, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C10, (q15_t)0x4FFB, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A22, (q15_t)0x4D81, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9842, (q15_t)0x4AFB, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x9673, (q15_t)0x4869, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x94B5, (q15_t)0x45CD, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9306, (q15_t)0x4325, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9169, (q15_t)0x4073, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x8FDC, (q15_t)0x3DB8, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8E61, (q15_t)0x3AF2, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8CF8, (q15_t)0x3824, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BA0, (q15_t)0x354D, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8A5A, (q15_t)0x326E, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8926, (q15_t)0x2F87, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x8805, (q15_t)0x2C98, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x86F6, (q15_t)0x29A3, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x85FA, (q15_t)0x26A8, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8510, (q15_t)0x23A6, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x843A, (q15_t)0x209F, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x8376, (q15_t)0x1D93, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82C6, (q15_t)0x1A82, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8229, (q15_t)0x176D, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81A0, (q15_t)0x1455, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x812A, (q15_t)0x1139, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80C7, (q15_t)0x0E1B, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8078, (q15_t)0x0AFB, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x803D, (q15_t)0x07D9, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8016, (q15_t)0x04B6, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8002, (q15_t)0x0192, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8002, (q15_t)0xFE6D, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x8016, (q15_t)0xFB49, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x803D, (q15_t)0xF826, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8078, (q15_t)0xF504, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80C7, (q15_t)0xF1E4, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x812A, (q15_t)0xEEC6, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81A0, (q15_t)0xEBAA, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8229, (q15_t)0xE892, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x82C6, (q15_t)0xE57D, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8376, (q15_t)0xE26C, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x843A, (q15_t)0xDF60, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x8510, (q15_t)0xDC59, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85FA, (q15_t)0xD957, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86F6, (q15_t)0xD65C, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8805, (q15_t)0xD367, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x8926, (q15_t)0xD078, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A5A, (q15_t)0xCD91, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8BA0, (q15_t)0xCAB2, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CF8, (q15_t)0xC7DB, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E61, (q15_t)0xC50D, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8FDC, (q15_t)0xC247, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9169, (q15_t)0xBF8C, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9306, (q15_t)0xBCDA, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x94B5, (q15_t)0xBA32, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9673, (q15_t)0xB796, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9842, (q15_t)0xB504, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9A22, (q15_t)0xB27E, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9C10, (q15_t)0xB004, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9E0E, (q15_t)0xAD96, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0xA01C, (q15_t)0xAB35, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA238, (q15_t)0xA8E2, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA462, (q15_t)0xA69B, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA69B, (q15_t)0xA462, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA8E2, (q15_t)0xA238, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAB35, (q15_t)0xA01C, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAD96, (q15_t)0x9E0E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB004, (q15_t)0x9C10, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB27E, (q15_t)0x9A22, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB504, (q15_t)0x9842, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB796, (q15_t)0x9673, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBA32, (q15_t)0x94B5, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBCDA, (q15_t)0x9306, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBF8C, (q15_t)0x9169, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC247, (q15_t)0x8FDC, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC50D, (q15_t)0x8E61, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC7DB, (q15_t)0x8CF8, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCAB2, (q15_t)0x8BA0, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCD91, (q15_t)0x8A5A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD078, (q15_t)0x8926, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD367, (q15_t)0x8805, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD65C, (q15_t)0x86F6, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD957, (q15_t)0x85FA, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDC59, (q15_t)0x8510, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDF60, (q15_t)0x843A, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE26C, (q15_t)0x8376, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE57D, (q15_t)0x82C6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE892, (q15_t)0x8229, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEBAA, (q15_t)0x81A0, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEEC6, (q15_t)0x812A, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF1E4, (q15_t)0x80C7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF504, (q15_t)0x8078, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF826, (q15_t)0x803D, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFB49, (q15_t)0x8016, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFE6D, (q15_t)0x8002 +}; + +/** +* \par +* Example code for q15 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 1024 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to q15(Fixed point 1.15): +* round(twiddleCoefq15(i) * pow(2, 15)) +* +*/ +const q15_t twiddleCoef_1024_q15[1536] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x00C9, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFA, (q15_t)0x025B, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF0, (q15_t)0x03ED, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE1, (q15_t)0x057F, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FCE, (q15_t)0x0710, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FB5, (q15_t)0x08A2, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F97, (q15_t)0x0A33, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F75, (q15_t)0x0BC3, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F4D, (q15_t)0x0D53, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F21, (q15_t)0x0EE3, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EF0, (q15_t)0x1072, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EBA, (q15_t)0x1201, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E7F, (q15_t)0x138E, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E3F, (q15_t)0x151B, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DFA, (q15_t)0x16A8, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DB0, (q15_t)0x1833, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D62, (q15_t)0x19BD, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D0F, (q15_t)0x1B47, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CB7, (q15_t)0x1CCF, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C5A, (q15_t)0x1E56, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BF8, (q15_t)0x1FDC, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7B92, (q15_t)0x2161, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B26, (q15_t)0x22E5, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AB6, (q15_t)0x2467, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A42, (q15_t)0x25E8, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79C8, (q15_t)0x2767, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x794A, (q15_t)0x28E5, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78C7, (q15_t)0x2A61, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7840, (q15_t)0x2BDC, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77B4, (q15_t)0x2D55, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7723, (q15_t)0x2ECC, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x768E, (q15_t)0x3041, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75F4, (q15_t)0x31B5, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x7555, (q15_t)0x3326, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74B2, (q15_t)0x3496, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x740B, (q15_t)0x3604, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x735F, (q15_t)0x376F, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72AF, (q15_t)0x38D8, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x71FA, (q15_t)0x3A40, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x7141, (q15_t)0x3BA5, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7083, (q15_t)0x3D07, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FC1, (q15_t)0x3E68, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6EFB, (q15_t)0x3FC5, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E30, (q15_t)0x4121, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D62, (q15_t)0x427A, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6C8F, (q15_t)0x43D0, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BB8, (q15_t)0x4524, + (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6ADC, (q15_t)0x4675, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x69FD, (q15_t)0x47C3, + (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6919, (q15_t)0x490F, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x6832, (q15_t)0x4A58, + (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6746, (q15_t)0x4B9E, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6657, (q15_t)0x4CE1, + (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x6563, (q15_t)0x4E21, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x646C, (q15_t)0x4F5E, + (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x6371, (q15_t)0x5097, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x6271, (q15_t)0x51CE, + (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x616F, (q15_t)0x5302, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x6068, (q15_t)0x5433, + (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5F5E, (q15_t)0x5560, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E50, (q15_t)0x568A, + (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D3E, (q15_t)0x57B0, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C29, (q15_t)0x58D4, + (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B10, (q15_t)0x59F3, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x59F3, (q15_t)0x5B10, + (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x58D4, (q15_t)0x5C29, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57B0, (q15_t)0x5D3E, + (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x568A, (q15_t)0x5E50, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x5560, (q15_t)0x5F5E, + (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x5433, (q15_t)0x6068, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5302, (q15_t)0x616F, + (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x51CE, (q15_t)0x6271, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x5097, (q15_t)0x6371, + (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4F5E, (q15_t)0x646C, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E21, (q15_t)0x6563, + (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4CE1, (q15_t)0x6657, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4B9E, (q15_t)0x6746, + (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4A58, (q15_t)0x6832, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x490F, (q15_t)0x6919, + (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x47C3, (q15_t)0x69FD, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x4675, (q15_t)0x6ADC, + (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4524, (q15_t)0x6BB8, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x43D0, (q15_t)0x6C8F, + (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x427A, (q15_t)0x6D62, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4121, (q15_t)0x6E30, + (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x3FC5, (q15_t)0x6EFB, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3E68, (q15_t)0x6FC1, + (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D07, (q15_t)0x7083, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BA5, (q15_t)0x7141, + (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A40, (q15_t)0x71FA, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x38D8, (q15_t)0x72AF, + (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x376F, 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(q15_t)0xAA9F, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA1AF, (q15_t)0xA975, + (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA2C1, (q15_t)0xA84F, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA3D6, (q15_t)0xA72B, + (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4EF, (q15_t)0xA60C, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA60C, (q15_t)0xA4EF, + (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA72B, (q15_t)0xA3D6, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA84F, (q15_t)0xA2C1, + (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA975, (q15_t)0xA1AF, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA9F, (q15_t)0xA0A1, + (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xABCC, (q15_t)0x9F97, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACFD, (q15_t)0x9E90, + (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xAE31, (q15_t)0x9D8E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF68, (q15_t)0x9C8E, + (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB0A1, (q15_t)0x9B93, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB1DE, (q15_t)0x9A9C, + (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB31E, (q15_t)0x99A8, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB461, (q15_t)0x98B9, + (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB5A7, (q15_t)0x97CD, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB6F0, (q15_t)0x96E6, + (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB83C, (q15_t)0x9602, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB98A, (q15_t)0x9523, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBADB, (q15_t)0x9447, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBC2F, (q15_t)0x9370, + (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD85, (q15_t)0x929D, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBEDE, (q15_t)0x91CF, + (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xC03A, (q15_t)0x9104, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC197, (q15_t)0x903E, + (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC2F8, (q15_t)0x8F7C, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC45A, (q15_t)0x8EBE, + (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC5BF, (q15_t)0x8E05, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC727, (q15_t)0x8D50, + (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC890, (q15_t)0x8CA0, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9FB, (q15_t)0x8BF4, + (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB69, (q15_t)0x8B4D, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCCD9, (q15_t)0x8AAA, + (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCE4A, (q15_t)0x8A0B, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCFBE, (q15_t)0x8971, + (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD133, (q15_t)0x88DC, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD2AA, (q15_t)0x884B, + (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD423, (q15_t)0x87BF, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD59E, (q15_t)0x8738, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD71A, (q15_t)0x86B5, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD898, (q15_t)0x8637, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xDA17, (q15_t)0x85BD, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB98, (q15_t)0x8549, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDD1A, (q15_t)0x84D9, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE9E, (q15_t)0x846D, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xE023, (q15_t)0x8407, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE1A9, (q15_t)0x83A5, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE330, (q15_t)0x8348, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE4B8, (q15_t)0x82F0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE642, (q15_t)0x829D, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE7CC, (q15_t)0x824F, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE957, (q15_t)0x8205, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEAE4, (q15_t)0x81C0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC71, (q15_t)0x8180, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEDFE, (q15_t)0x8145, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF8D, (q15_t)0x810F, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF11C, (q15_t)0x80DE, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF2AC, (q15_t)0x80B2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF43C, (q15_t)0x808A, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF5CC, (q15_t)0x8068, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF75D, (q15_t)0x804A, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF8EF, (q15_t)0x8031, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA80, (q15_t)0x801E, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFC12, (q15_t)0x800F, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFDA4, (q15_t)0x8005, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFF36, (q15_t)0x8000 +}; + +/** +* \par +* Example code for q15 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 2048 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to q15(Fixed point 1.15): +* round(twiddleCoefq15(i) * pow(2, 15)) +* +*/ +const q15_t twiddleCoef_2048_q15[3072] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0064, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFE, (q15_t)0x012D, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01F6, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF8, (q15_t)0x02BF, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF3, (q15_t)0x0388, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FED, (q15_t)0x0451, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE5, (q15_t)0x051A, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDD, (q15_t)0x05E3, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD3, (q15_t)0x06AC, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FC8, (q15_t)0x0775, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBC, (q15_t)0x083D, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FAE, (q15_t)0x0906, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F9F, (q15_t)0x09CE, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F8F, (q15_t)0x0A97, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F7E, (q15_t)0x0B5F, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F6B, (q15_t)0x0C27, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F58, (q15_t)0x0CEF, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F43, (q15_t)0x0DB7, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F2D, (q15_t)0x0E7F, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F15, (q15_t)0x0F47, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EFD, (q15_t)0x100E, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE3, (q15_t)0x10D6, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EC8, (q15_t)0x119D, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EAB, (q15_t)0x1264, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E8E, (q15_t)0x132B, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E6F, (q15_t)0x13F2, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E4F, (q15_t)0x14B8, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E2E, (q15_t)0x157F, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E0C, (q15_t)0x1645, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DE8, (q15_t)0x170A, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DC3, (q15_t)0x17D0, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7D9D, (q15_t)0x1896, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D76, (q15_t)0x195B, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D4E, (q15_t)0x1A20, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D24, (q15_t)0x1AE4, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7CF9, (q15_t)0x1BA9, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CCD, (q15_t)0x1C6D, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CA0, (q15_t)0x1D31, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C71, (q15_t)0x1DF5, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C42, (q15_t)0x1EB8, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C11, (q15_t)0x1F7B, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BDF, (q15_t)0x203E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BAC, (q15_t)0x2100, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B77, (q15_t)0x21C2, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B42, (q15_t)0x2284, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B0B, (q15_t)0x2345, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AD3, (q15_t)0x2407, + (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7A9A, (q15_t)0x24C7, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A5F, (q15_t)0x2588, + (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A24, (q15_t)0x2648, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79E7, (q15_t)0x2707, + (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79A9, (q15_t)0x27C7, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x796A, (q15_t)0x2886, + (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x792A, (q15_t)0x2944, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78E8, (q15_t)0x2A02, + (q15_t)0x78C7, (q15_t)0x2A61, (q15_t)0x78A6, (q15_t)0x2AC0, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7862, (q15_t)0x2B7D, + (q15_t)0x7840, (q15_t)0x2BDC, (q15_t)0x781D, (q15_t)0x2C3A, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77D7, (q15_t)0x2CF7, + (q15_t)0x77B4, (q15_t)0x2D55, (q15_t)0x7790, (q15_t)0x2DB3, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7747, (q15_t)0x2E6E, + (q15_t)0x7723, (q15_t)0x2ECC, (q15_t)0x76FE, (q15_t)0x2F29, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x76B3, (q15_t)0x2FE4, + (q15_t)0x768E, (q15_t)0x3041, (q15_t)0x7668, (q15_t)0x309E, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x761B, (q15_t)0x3158, + (q15_t)0x75F4, (q15_t)0x31B5, (q15_t)0x75CC, (q15_t)0x3211, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x757D, (q15_t)0x32CA, + (q15_t)0x7555, (q15_t)0x3326, (q15_t)0x752D, (q15_t)0x3382, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74DB, (q15_t)0x343A, + (q15_t)0x74B2, (q15_t)0x3496, (q15_t)0x7489, (q15_t)0x34F2, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x7435, (q15_t)0x35A8, + (q15_t)0x740B, (q15_t)0x3604, (q15_t)0x73E0, (q15_t)0x365F, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x738A, (q15_t)0x3714, + (q15_t)0x735F, (q15_t)0x376F, (q15_t)0x7333, (q15_t)0x37CA, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72DB, (q15_t)0x387E, + (q15_t)0x72AF, (q15_t)0x38D8, (q15_t)0x7282, (q15_t)0x3932, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x7227, (q15_t)0x39E6, + (q15_t)0x71FA, (q15_t)0x3A40, (q15_t)0x71CC, (q15_t)0x3A99, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x716F, (q15_t)0x3B4C, + (q15_t)0x7141, (q15_t)0x3BA5, (q15_t)0x7112, (q15_t)0x3BFD, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x70B3, (q15_t)0x3CAF, + (q15_t)0x7083, (q15_t)0x3D07, (q15_t)0x7053, (q15_t)0x3D60, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FF2, (q15_t)0x3E10, + (q15_t)0x6FC1, (q15_t)0x3E68, (q15_t)0x6F90, (q15_t)0x3EBF, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6F2D, (q15_t)0x3F6E, + (q15_t)0x6EFB, (q15_t)0x3FC5, (q15_t)0x6EC9, (q15_t)0x401D, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E63, (q15_t)0x40CA, + (q15_t)0x6E30, (q15_t)0x4121, (q15_t)0x6DFD, (q15_t)0x4177, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D96, (q15_t)0x4224, + (q15_t)0x6D62, (q15_t)0x427A, (q15_t)0x6D2D, (q15_t)0x42D0, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6CC4, (q15_t)0x437B, + (q15_t)0x6C8F, (q15_t)0x43D0, (q15_t)0x6C59, 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(q15_t)0x8332, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE456, (q15_t)0x8306, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE51B, (q15_t)0x82DB, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5DF, (q15_t)0x82B1, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE6A4, (q15_t)0x8289, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE769, (q15_t)0x8262, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE82F, (q15_t)0x823C, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8F5, (q15_t)0x8217, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE9BA, (q15_t)0x81F3, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA80, (q15_t)0x81D1, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB47, (q15_t)0x81B0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC0D, (q15_t)0x8190, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECD4, (q15_t)0x8171, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED9B, (q15_t)0x8154, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE62, (q15_t)0x8137, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF29, (q15_t)0x811C, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFF1, (q15_t)0x8102, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF0B8, (q15_t)0x80EA, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF180, (q15_t)0x80D2, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF248, (q15_t)0x80BC, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF310, (q15_t)0x80A7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3D8, (q15_t)0x8094, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF4A0, (q15_t)0x8081, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF568, (q15_t)0x8070, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF631, (q15_t)0x8060, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6F9, (q15_t)0x8051, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF7C2, (q15_t)0x8043, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF88A, (q15_t)0x8037, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF953, (q15_t)0x802C, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA1C, (q15_t)0x8022, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAE5, (q15_t)0x801A, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFBAE, (q15_t)0x8012, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC77, (q15_t)0x800C, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD40, (q15_t)0x8007, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFE09, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFED2, (q15_t)0x8001, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000 +}; + +/** +* \par +* Example code for q15 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)
+* {
+*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 4096 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to q15(Fixed point 1.15): +* round(twiddleCoefq15(i) * pow(2, 15)) +* +*/ +const q15_t twiddleCoef_4096_q15[6144] = +{ + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0032, + (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0096, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x00FB, + (q15_t)0x7FFE, (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x015F, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01C4, + (q15_t)0x7FFC, (q15_t)0x01F6, (q15_t)0x7FFB, (q15_t)0x0228, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF9, (q15_t)0x028D, + (q15_t)0x7FF8, (q15_t)0x02BF, (q15_t)0x7FF7, (q15_t)0x02F1, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF4, (q15_t)0x0356, + (q15_t)0x7FF3, (q15_t)0x0388, (q15_t)0x7FF2, (q15_t)0x03BA, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FEE, (q15_t)0x041F, + (q15_t)0x7FED, (q15_t)0x0451, (q15_t)0x7FEB, (q15_t)0x0483, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE7, (q15_t)0x04E8, + (q15_t)0x7FE5, (q15_t)0x051A, (q15_t)0x7FE3, (q15_t)0x054C, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDF, (q15_t)0x05B1, + (q15_t)0x7FDD, (q15_t)0x05E3, (q15_t)0x7FDA, (q15_t)0x0615, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD6, (q15_t)0x067A, + (q15_t)0x7FD3, (q15_t)0x06AC, (q15_t)0x7FD0, (q15_t)0x06DE, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FCB, (q15_t)0x0742, + (q15_t)0x7FC8, (q15_t)0x0775, (q15_t)0x7FC5, (q15_t)0x07A7, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBF, (q15_t)0x080B, + (q15_t)0x7FBC, (q15_t)0x083D, (q15_t)0x7FB8, (q15_t)0x086F, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FB1, (q15_t)0x08D4, + (q15_t)0x7FAE, (q15_t)0x0906, (q15_t)0x7FAA, (q15_t)0x0938, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7FA3, (q15_t)0x099C, + (q15_t)0x7F9F, (q15_t)0x09CE, (q15_t)0x7F9B, (q15_t)0x0A00, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F93, (q15_t)0x0A65, + (q15_t)0x7F8F, (q15_t)0x0A97, (q15_t)0x7F8B, (q15_t)0x0AC9, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F82, (q15_t)0x0B2D, + (q15_t)0x7F7E, (q15_t)0x0B5F, (q15_t)0x7F79, (q15_t)0x0B91, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F70, (q15_t)0x0BF5, + (q15_t)0x7F6B, (q15_t)0x0C27, (q15_t)0x7F67, (q15_t)0x0C59, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F5D, (q15_t)0x0CBD, + (q15_t)0x7F58, (q15_t)0x0CEF, (q15_t)0x7F53, (q15_t)0x0D21, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F48, (q15_t)0x0D85, + (q15_t)0x7F43, (q15_t)0x0DB7, (q15_t)0x7F3D, (q15_t)0x0DE9, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F32, (q15_t)0x0E4D, + (q15_t)0x7F2D, (q15_t)0x0E7F, (q15_t)0x7F27, (q15_t)0x0EB1, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F1B, (q15_t)0x0F15, + (q15_t)0x7F15, (q15_t)0x0F47, (q15_t)0x7F0F, (q15_t)0x0F79, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7F03, (q15_t)0x0FDD, + (q15_t)0x7EFD, (q15_t)0x100E, (q15_t)0x7EF6, (q15_t)0x1040, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE9, (q15_t)0x10A4, + (q15_t)0x7EE3, (q15_t)0x10D6, (q15_t)0x7EDC, (q15_t)0x1108, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7ECF, (q15_t)0x116B, + (q15_t)0x7EC8, (q15_t)0x119D, (q15_t)0x7EC1, (q15_t)0x11CF, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EB3, (q15_t)0x1232, + (q15_t)0x7EAB, (q15_t)0x1264, (q15_t)0x7EA4, (q15_t)0x1296, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E95, (q15_t)0x12F9, + (q15_t)0x7E8E, (q15_t)0x132B, (q15_t)0x7E86, (q15_t)0x135D, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E77, (q15_t)0x13C0, + (q15_t)0x7E6F, (q15_t)0x13F2, (q15_t)0x7E67, (q15_t)0x1423, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E57, (q15_t)0x1487, + (q15_t)0x7E4F, (q15_t)0x14B8, (q15_t)0x7E47, (q15_t)0x14EA, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E37, (q15_t)0x154D, + (q15_t)0x7E2E, (q15_t)0x157F, (q15_t)0x7E26, (q15_t)0x15B0, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E14, (q15_t)0x1613, + (q15_t)0x7E0C, (q15_t)0x1645, (q15_t)0x7E03, (q15_t)0x1676, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DF1, (q15_t)0x16D9, + (q15_t)0x7DE8, (q15_t)0x170A, (q15_t)0x7DDF, (q15_t)0x173C, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DCD, (q15_t)0x179F, + (q15_t)0x7DC3, (q15_t)0x17D0, (q15_t)0x7DBA, (q15_t)0x1802, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7DA7, (q15_t)0x1864, + (q15_t)0x7D9D, (q15_t)0x1896, (q15_t)0x7D94, (q15_t)0x18C7, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D80, (q15_t)0x192A, + (q15_t)0x7D76, (q15_t)0x195B, (q15_t)0x7D6C, (q15_t)0x198C, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D58, (q15_t)0x19EF, + (q15_t)0x7D4E, (q15_t)0x1A20, (q15_t)0x7D43, (q15_t)0x1A51, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D2F, (q15_t)0x1AB3, + (q15_t)0x7D24, (q15_t)0x1AE4, (q15_t)0x7D19, (q15_t)0x1B16, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7D04, (q15_t)0x1B78, + (q15_t)0x7CF9, (q15_t)0x1BA9, (q15_t)0x7CEE, (q15_t)0x1BDA, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CD8, (q15_t)0x1C3C, + (q15_t)0x7CCD, (q15_t)0x1C6D, (q15_t)0x7CC2, (q15_t)0x1C9E, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CAB, (q15_t)0x1D00, + (q15_t)0x7CA0, (q15_t)0x1D31, (q15_t)0x7C94, (q15_t)0x1D62, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C7D, (q15_t)0x1DC4, + (q15_t)0x7C71, (q15_t)0x1DF5, (q15_t)0x7C66, (q15_t)0x1E25, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C4E, (q15_t)0x1E87, + (q15_t)0x7C42, (q15_t)0x1EB8, (q15_t)0x7C36, (q15_t)0x1EE9, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C1D, (q15_t)0x1F4A, + (q15_t)0x7C11, (q15_t)0x1F7B, (q15_t)0x7C05, (q15_t)0x1FAC, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BEB, (q15_t)0x200D, + (q15_t)0x7BDF, (q15_t)0x203E, (q15_t)0x7BD2, (q15_t)0x206E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BB9, (q15_t)0x20D0, + (q15_t)0x7BAC, (q15_t)0x2100, (q15_t)0x7B9F, (q15_t)0x2131, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B84, (q15_t)0x2192, + (q15_t)0x7B77, (q15_t)0x21C2, (q15_t)0x7B6A, (q15_t)0x21F3, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B4F, (q15_t)0x2254, + (q15_t)0x7B42, (q15_t)0x2284, (q15_t)0x7B34, (q15_t)0x22B4, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B19, (q15_t)0x2315, + (q15_t)0x7B0B, (q15_t)0x2345, (q15_t)0x7AFD, (q15_t)0x2376, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AE1, (q15_t)0x23D6, + (q15_t)0x7AD3, (q15_t)0x2407, (q15_t)0x7AC5, (q15_t)0x2437, + (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7AA8, (q15_t)0x2497, + (q15_t)0x7A9A, (q15_t)0x24C7, (q15_t)0x7A8B, (q15_t)0x24F7, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A6E, (q15_t)0x2558, + (q15_t)0x7A5F, (q15_t)0x2588, (q15_t)0x7A50, (q15_t)0x25B8, + (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A33, (q15_t)0x2618, + (q15_t)0x7A24, (q15_t)0x2648, (q15_t)0x7A15, (q15_t)0x2678, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79F6, (q15_t)0x26D8, + (q15_t)0x79E7, (q15_t)0x2707, (q15_t)0x79D8, (q15_t)0x2737, + (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79B9, (q15_t)0x2797, + (q15_t)0x79A9, (q15_t)0x27C7, (q15_t)0x7999, (q15_t)0x27F6, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x797A, (q15_t)0x2856, + (q15_t)0x796A, (q15_t)0x2886, (q15_t)0x795A, (q15_t)0x28B5, + (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x793A, (q15_t)0x2915, + (q15_t)0x792A, (q15_t)0x2944, (q15_t)0x7919, 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(q15_t)0x8816, + (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD396, (q15_t)0x87F3, + (q15_t)0xD3C5, (q15_t)0x87E2, (q15_t)0xD3F4, (q15_t)0x87D1, + (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD452, (q15_t)0x87AE, + (q15_t)0xD482, (q15_t)0x879D, (q15_t)0xD4B1, (q15_t)0x878C, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD510, (q15_t)0x876A, + (q15_t)0xD53F, (q15_t)0x8759, (q15_t)0xD56E, (q15_t)0x8749, + (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5CD, (q15_t)0x8727, + (q15_t)0xD5FD, (q15_t)0x8717, (q15_t)0xD62C, (q15_t)0x8706, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD68B, (q15_t)0x86E6, + (q15_t)0xD6BB, (q15_t)0x86D5, (q15_t)0xD6EA, (q15_t)0x86C5, + (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD74A, (q15_t)0x86A5, + (q15_t)0xD779, (q15_t)0x8695, (q15_t)0xD7A9, (q15_t)0x8685, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD809, (q15_t)0x8666, + (q15_t)0xD838, (q15_t)0x8656, (q15_t)0xD868, (q15_t)0x8646, + (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8C8, (q15_t)0x8627, + (q15_t)0xD8F8, (q15_t)0x8618, (q15_t)0xD927, (q15_t)0x8609, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD987, (q15_t)0x85EA, + (q15_t)0xD9B7, (q15_t)0x85DB, (q15_t)0xD9E7, (q15_t)0x85CC, + (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA47, (q15_t)0x85AF, + (q15_t)0xDA77, (q15_t)0x85A0, (q15_t)0xDAA7, (q15_t)0x8591, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB08, (q15_t)0x8574, + (q15_t)0xDB38, (q15_t)0x8565, (q15_t)0xDB68, (q15_t)0x8557, + (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBC8, (q15_t)0x853A, + (q15_t)0xDBF8, (q15_t)0x852C, (q15_t)0xDC29, (q15_t)0x851E, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDC89, (q15_t)0x8502, + (q15_t)0xDCBA, (q15_t)0x84F4, (q15_t)0xDCEA, (q15_t)0x84E6, + (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD4B, (q15_t)0x84CB, + (q15_t)0xDD7B, (q15_t)0x84BD, (q15_t)0xDDAB, (q15_t)0x84B0, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE0C, (q15_t)0x8495, + (q15_t)0xDE3D, (q15_t)0x8488, (q15_t)0xDE6D, (q15_t)0x847B, + (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDECE, (q15_t)0x8460, + (q15_t)0xDEFF, (q15_t)0x8453, (q15_t)0xDF2F, (q15_t)0x8446, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDF91, (q15_t)0x842D, + (q15_t)0xDFC1, (q15_t)0x8420, (q15_t)0xDFF2, (q15_t)0x8414, + (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE053, (q15_t)0x83FA, + (q15_t)0xE084, (q15_t)0x83EE, (q15_t)0xE0B5, (q15_t)0x83E2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE116, (q15_t)0x83C9, + (q15_t)0xE147, (q15_t)0x83BD, (q15_t)0xE178, (q15_t)0x83B1, + (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE1DA, (q15_t)0x8399, + (q15_t)0xE20A, (q15_t)0x838E, (q15_t)0xE23B, (q15_t)0x8382, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE29D, (q15_t)0x836B, + (q15_t)0xE2CE, (q15_t)0x835F, (q15_t)0xE2FF, (q15_t)0x8354, + (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE361, (q15_t)0x833D, + (q15_t)0xE392, (q15_t)0x8332, (q15_t)0xE3C3, (q15_t)0x8327, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE425, (q15_t)0x8311, + (q15_t)0xE456, (q15_t)0x8306, (q15_t)0xE487, (q15_t)0x82FB, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE4E9, (q15_t)0x82E6, + (q15_t)0xE51B, (q15_t)0x82DB, (q15_t)0xE54C, (q15_t)0x82D0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5AE, (q15_t)0x82BC, + (q15_t)0xE5DF, (q15_t)0x82B1, (q15_t)0xE610, (q15_t)0x82A7, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE673, (q15_t)0x8293, + (q15_t)0xE6A4, (q15_t)0x8289, (q15_t)0xE6D5, (q15_t)0x827F, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE738, (q15_t)0x826B, + (q15_t)0xE769, (q15_t)0x8262, (q15_t)0xE79B, (q15_t)0x8258, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE7FD, (q15_t)0x8245, + (q15_t)0xE82F, (q15_t)0x823C, (q15_t)0xE860, (q15_t)0x8232, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8C3, (q15_t)0x8220, + (q15_t)0xE8F5, (q15_t)0x8217, (q15_t)0xE926, (q15_t)0x820E, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE989, (q15_t)0x81FC, + (q15_t)0xE9BA, (q15_t)0x81F3, (q15_t)0xE9EC, (q15_t)0x81EB, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA4F, (q15_t)0x81D9, + (q15_t)0xEA80, (q15_t)0x81D1, (q15_t)0xEAB2, (q15_t)0x81C8, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB15, (q15_t)0x81B8, + (q15_t)0xEB47, (q15_t)0x81B0, (q15_t)0xEB78, (q15_t)0x81A8, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEBDC, (q15_t)0x8198, + (q15_t)0xEC0D, (q15_t)0x8190, (q15_t)0xEC3F, (q15_t)0x8188, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECA2, (q15_t)0x8179, + (q15_t)0xECD4, (q15_t)0x8171, (q15_t)0xED06, (q15_t)0x816A, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED69, (q15_t)0x815B, + (q15_t)0xED9B, (q15_t)0x8154, (q15_t)0xEDCD, (q15_t)0x814C, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE30, (q15_t)0x813E, + (q15_t)0xEE62, (q15_t)0x8137, (q15_t)0xEE94, (q15_t)0x8130, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEEF7, (q15_t)0x8123, + (q15_t)0xEF29, (q15_t)0x811C, (q15_t)0xEF5B, (q15_t)0x8116, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFBF, (q15_t)0x8109, + (q15_t)0xEFF1, (q15_t)0x8102, (q15_t)0xF022, (q15_t)0x80FC, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF086, (q15_t)0x80F0, + (q15_t)0xF0B8, (q15_t)0x80EA, (q15_t)0xF0EA, (q15_t)0x80E4, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF14E, (q15_t)0x80D8, + (q15_t)0xF180, (q15_t)0x80D2, (q15_t)0xF1B2, (q15_t)0x80CD, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF216, (q15_t)0x80C2, + (q15_t)0xF248, (q15_t)0x80BC, (q15_t)0xF27A, (q15_t)0x80B7, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF2DE, (q15_t)0x80AC, + (q15_t)0xF310, (q15_t)0x80A7, (q15_t)0xF342, (q15_t)0x80A2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3A6, (q15_t)0x8098, + (q15_t)0xF3D8, (q15_t)0x8094, (q15_t)0xF40A, (q15_t)0x808F, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF46E, (q15_t)0x8086, + (q15_t)0xF4A0, (q15_t)0x8081, (q15_t)0xF4D2, (q15_t)0x807D, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF536, (q15_t)0x8074, + (q15_t)0xF568, (q15_t)0x8070, (q15_t)0xF59A, (q15_t)0x806C, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF5FF, (q15_t)0x8064, + (q15_t)0xF631, (q15_t)0x8060, (q15_t)0xF663, (q15_t)0x805C, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6C7, (q15_t)0x8055, + (q15_t)0xF6F9, (q15_t)0x8051, (q15_t)0xF72B, (q15_t)0x804E, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF790, (q15_t)0x8047, + (q15_t)0xF7C2, (q15_t)0x8043, (q15_t)0xF7F4, (q15_t)0x8040, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF858, (q15_t)0x803A, + (q15_t)0xF88A, (q15_t)0x8037, (q15_t)0xF8BD, (q15_t)0x8034, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF921, (q15_t)0x802F, + (q15_t)0xF953, (q15_t)0x802C, (q15_t)0xF985, (q15_t)0x8029, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xF9EA, (q15_t)0x8025, + (q15_t)0xFA1C, (q15_t)0x8022, (q15_t)0xFA4E, (q15_t)0x8020, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAB3, (q15_t)0x801C, + (q15_t)0xFAE5, (q15_t)0x801A, (q15_t)0xFB17, (q15_t)0x8018, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFB7C, (q15_t)0x8014, + (q15_t)0xFBAE, (q15_t)0x8012, (q15_t)0xFBE0, (q15_t)0x8011, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC45, (q15_t)0x800D, + (q15_t)0xFC77, (q15_t)0x800C, (q15_t)0xFCA9, (q15_t)0x800B, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD0E, (q15_t)0x8008, + (q15_t)0xFD40, (q15_t)0x8007, (q15_t)0xFD72, (q15_t)0x8006, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFDD7, (q15_t)0x8004, + (q15_t)0xFE09, (q15_t)0x8003, (q15_t)0xFE3B, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFEA0, (q15_t)0x8001, + (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFF04, (q15_t)0x8000, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF69, (q15_t)0x8000, + (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFFCD, (q15_t)0x8000 +}; + + +/** +* @} end of CFFT_CIFFT group +*/ + +/* +* @brief Q15 table for reciprocal +*/ +const q15_t ALIGN4 armRecipTableQ15[64] = { + 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0, + 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82, + 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484, + 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0, + 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E, + 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255, + 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6, + 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978, + 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8, + 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255, + 0x41CC, 0x4146, 0x40C2, 0x4040 +}; + +/* +* @brief Q31 table for reciprocal +*/ +const q31_t armRecipTableQ31[64] = { + 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928, + 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3, + 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519, + 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB, + 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318, + 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0, + 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D, + 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96, + 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2, + 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426, + 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102 +}; + +const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH] = +{ + /* 8x2, size 20 */ + 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112 +}; + +const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH] = +{ + /* 8x4, size 48 */ + 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208, + 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208, + 152,224, 176,208, 184,232, 216,240, 200,224, 232,240 +}; + +const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH] = +{ + /* radix 8, size 56 */ + 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200, + 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400, + 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480, + 368,424, 376,488, 440,496 +}; + +const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] = +{ + /* 8x2, size 208 */ + 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768, + 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520, + 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776, + 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320, + 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400, + 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584, + 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600, + 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608, + 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864, + 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808, + 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832, + 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008, + 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008 +}; + +const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] = +{ + /* 8x4, size 440 */ + 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640, + 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768, + 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384, + 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984, + 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608, + 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736, + 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864, + 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992, + 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104, + 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720, + 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160, + 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936, + 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048, + 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808, + 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544, + 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880, + 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496, + 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120, + 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552, + 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824, + 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672, + 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016, + 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640, + 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432, + 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936, + 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960, + 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648, + 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936, + 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928, + 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840, + 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888, + 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032, + 1960,1968, 2008,2032, 1992,2016, 2024,2032 +}; + +const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] = +{ + /* radix 8, size 448 */ + 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576, + 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152, + 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216, + 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280, + 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344, + 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408, + 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472, + 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544, + 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120, + 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696, + 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272, + 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848, + 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416, + 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992, + 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576, + 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152, + 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728, + 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808, + 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384, + 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960, + 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536, + 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136, + 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224, + 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328, + 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416, + 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520, + 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616, + 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744, + 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872, + 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000, + 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176, + 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368, + 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560, + 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888, + 3448,3952, 3512,4016, 3576,4080 +}; + +const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH] = +{ + /* 8x2, size 1800 */ + 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048, + 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048, + 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696, + 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648, + 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248, + 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200, + 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800, + 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752, + 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352, + 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304, + 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936, + 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856, + 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488, + 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408, + 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040, + 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960, + 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592, + 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096, + 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544, + 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080, + 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400, + 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120, + 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656, + 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168, + 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696, + 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208, + 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736, + 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272, + 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480, + 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312, + 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848, + 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280, + 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888, + 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288, + 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928, + 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464, + 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592, + 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504, + 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040, + 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136, + 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088, + 2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816, + 2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576, + 2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664, + 2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264, + 2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800, + 2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304, + 2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840, + 2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376, + 2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392, + 2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344, + 2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944, + 2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480, + 2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016, + 2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032, + 2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984, + 2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584, + 2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632, + 3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632, + 3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168, + 3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704, + 3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208, + 3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744, + 3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248, + 3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784, + 3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320, + 3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824, + 3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360, + 3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896, + 3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400, + 3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936, + 3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440, + 3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976, + 3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512, + 3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016, + 3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552, + 3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088, + 3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592, + 4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128, + 4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160, + 4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176, + 4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712, + 4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216, + 4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752, + 4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416, + 4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304, + 4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624, + 4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296, + 4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680, + 4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208, + 4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400, + 4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808, + 4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688, + 4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976, + 4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160, + 4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344, + 4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728, + 4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736, + 5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928, + 5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872, + 5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672, + 5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208, + 5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456, + 5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248, + 5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784, + 5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448, + 5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824, + 5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240, + 5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504, + 5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168, + 5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264, + 5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456, + 5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552, + 5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312, + 5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576, + 5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248, + 5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504, + 5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360, + 6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624, + 6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384, + 6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264, + 6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664, + 6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520, + 6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280, + 6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536, + 6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048, + 6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752, + 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992, + 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280, + 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856, + 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024, + 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624, + 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104, + 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664, + 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280, + 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688, + 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952, + 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456, + 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864, + 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784, + 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048, + 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728, + 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096, + 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112, + 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984, + 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160, + 8112,8136, 8120,8168, 8136,8160, 8152,8176 +}; + +const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH] = +{ + /* 8x2, size 3808 */ + 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024, + 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824, + 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752, + 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680, + 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576, + 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376, + 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304, + 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232, + 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048, + 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928, + 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856, + 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784, + 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712, + 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480, + 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408, + 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336, + 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264, + 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064, + 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960, + 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792, + 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496, + 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328, + 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032, + 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928, + 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856, + 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560, + 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392, + 1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096, + 1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240, + 1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600, + 1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432, + 1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136, + 1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968, + 1768,8064, 1776,12160, 1784,16256, 1792,3136, 1800,4544, 1808,8640, + 1816,12736, 1824,3264, 1832,5056, 1840,9152, 1848,13248, 1856,3392, + 1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176, + 1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008, + 1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712, + 2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096, + 2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712, + 2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480, + 2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248, + 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080, + 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784, + 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248, + 2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288, + 2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128, + 2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824, + 2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656, + 2536,7752, 2544,11848, 2552,15944, 2560,6144, 2568,4232, 2576,8328, + 2584,12424, 2592,6272, 2600,4744, 2608,8840, 2616,12936, 2624,6400, + 2632,5256, 2640,9352, 2648,13448, 2656,6528, 2664,5768, 2672,9864, + 2680,13960, 2688,6152, 2696,6280, 2704,10376, 2712,14472, 2720,6280, + 2728,6792, 2736,10888, 2744,14984, 2752,3208, 2760,7304, 2768,11400, + 2776,15496, 2784,3720, 2792,7816, 2800,11912, 2808,16008, 2816,7168, + 2824,4296, 2832,8392, 2840,12488, 2848,7296, 2856,4808, 2864,8904, + 2872,13000, 2880,7424, 2888,5320, 2896,9416, 2904,13512, 2912,7552, + 2920,5832, 2928,9928, 2936,14024, 2944,7176, 2952,6344, 2960,10440, + 2968,14536, 2976,7304, 2984,6856, 2992,10952, 3000,15048, 3008,3272, + 3016,7368, 3024,11464, 3032,15560, 3040,3784, 3048,7880, 3056,11976, + 3064,16072, 3072,4160, 3080,4360, 3088,8456, 3096,12552, 3104,4288, + 3112,4872, 3120,8968, 3128,13064, 3136,4416, 3144,5384, 3152,9480, + 3160,13576, 3168,4544, 3176,5896, 3184,9992, 3192,14088, 3200,4168, + 3208,6408, 3216,10504, 3224,14600, 3232,4296, 3240,6920, 3248,11016, + 3256,15112, 3264,3336, 3272,7432, 3280,11528, 3288,15624, 3296,3848, + 3304,7944, 3312,12040, 3320,16136, 3328,5184, 3336,4424, 3344,8520, + 3352,12616, 3360,5312, 3368,4936, 3376,9032, 3384,13128, 3392,5440, + 3400,5448, 3408,9544, 3416,13640, 3424,5568, 3432,5960, 3440,10056, + 3448,14152, 3456,5192, 3464,6472, 3472,10568, 3480,14664, 3488,5320, + 3496,6984, 3504,11080, 3512,15176, 3520,5448, 3528,7496, 3536,11592, + 3544,15688, 3552,3912, 3560,8008, 3568,12104, 3576,16200, 3584,6208, + 3592,4488, 3600,8584, 3608,12680, 3616,6336, 3624,5000, 3632,9096, + 3640,13192, 3648,6464, 3656,5512, 3664,9608, 3672,13704, 3680,6592, + 3688,6024, 3696,10120, 3704,14216, 3712,6216, 3720,6536, 3728,10632, + 3736,14728, 3744,6344, 3752,7048, 3760,11144, 3768,15240, 3776,6472, + 3784,7560, 3792,11656, 3800,15752, 3808,3976, 3816,8072, 3824,12168, + 3832,16264, 3840,7232, 3848,4552, 3856,8648, 3864,12744, 3872,7360, + 3880,5064, 3888,9160, 3896,13256, 3904,7488, 3912,5576, 3920,9672, + 3928,13768, 3936,7616, 3944,6088, 3952,10184, 3960,14280, 3968,7240, + 3976,6600, 3984,10696, 3992,14792, 4000,7368, 4008,7112, 4016,11208, + 4024,15304, 4032,7496, 4040,7624, 4048,11720, 4056,15816, 4064,7624, + 4072,8136, 4080,12232, 4088,16328, 4096,8192, 4104,4112, 4112,8208, + 4120,12304, 4128,8320, 4136,4624, 4144,8720, 4152,12816, 4160,8448, + 4168,5136, 4176,9232, 4184,13328, 4192,8576, 4200,5648, 4208,9744, + 4216,13840, 4224,8200, 4232,6160, 4240,10256, 4248,14352, 4256,8328, + 4264,6672, 4272,10768, 4280,14864, 4288,8456, 4296,7184, 4304,11280, + 4312,15376, 4320,8584, 4328,7696, 4336,11792, 4344,15888, 4352,9216, + 4360,9232, 4368,8272, 4376,12368, 4384,9344, 4392,4688, 4400,8784, + 4408,12880, 4416,9472, 4424,5200, 4432,9296, 4440,13392, 4448,9600, + 4456,5712, 4464,9808, 4472,13904, 4480,9224, 4488,6224, 4496,10320, + 4504,14416, 4512,9352, 4520,6736, 4528,10832, 4536,14928, 4544,9480, + 4552,7248, 4560,11344, 4568,15440, 4576,9608, 4584,7760, 4592,11856, + 4600,15952, 4608,10240, 4616,10256, 4624,8336, 4632,12432, 4640,10368, + 4648,4752, 4656,8848, 4664,12944, 4672,10496, 4680,5264, 4688,9360, + 4696,13456, 4704,10624, 4712,5776, 4720,9872, 4728,13968, 4736,10248, + 4744,6288, 4752,10384, 4760,14480, 4768,10376, 4776,6800, 4784,10896, + 4792,14992, 4800,10504, 4808,7312, 4816,11408, 4824,15504, 4832,10632, + 4840,7824, 4848,11920, 4856,16016, 4864,11264, 4872,11280, 4880,8400, + 4888,12496, 4896,11392, 4904,11408, 4912,8912, 4920,13008, 4928,11520, + 4936,5328, 4944,9424, 4952,13520, 4960,11648, 4968,5840, 4976,9936, + 4984,14032, 4992,11272, 5000,6352, 5008,10448, 5016,14544, 5024,11400, + 5032,6864, 5040,10960, 5048,15056, 5056,11528, 5064,7376, 5072,11472, + 5080,15568, 5088,11656, 5096,7888, 5104,11984, 5112,16080, 5120,8256, + 5128,8272, 5136,8464, 5144,12560, 5152,8384, 5160,8400, 5168,8976, + 5176,13072, 5184,8512, 5192,5392, 5200,9488, 5208,13584, 5216,8640, + 5224,5904, 5232,10000, 5240,14096, 5248,8264, 5256,6416, 5264,10512, + 5272,14608, 5280,8392, 5288,6928, 5296,11024, 5304,15120, 5312,8520, + 5320,7440, 5328,11536, 5336,15632, 5344,8648, 5352,7952, 5360,12048, + 5368,16144, 5376,9280, 5384,9296, 5392,8528, 5400,12624, 5408,9408, + 5416,9424, 5424,9040, 5432,13136, 5440,9536, 5448,5456, 5456,9552, + 5464,13648, 5472,9664, 5480,5968, 5488,10064, 5496,14160, 5504,9288, + 5512,6480, 5520,10576, 5528,14672, 5536,9416, 5544,6992, 5552,11088, + 5560,15184, 5568,9544, 5576,7504, 5584,11600, 5592,15696, 5600,9672, + 5608,8016, 5616,12112, 5624,16208, 5632,10304, 5640,10320, 5648,8592, + 5656,12688, 5664,10432, 5672,10448, 5680,9104, 5688,13200, 5696,10560, + 5704,10576, 5712,9616, 5720,13712, 5728,10688, 5736,6032, 5744,10128, + 5752,14224, 5760,10312, 5768,6544, 5776,10640, 5784,14736, 5792,10440, + 5800,7056, 5808,11152, 5816,15248, 5824,10568, 5832,7568, 5840,11664, + 5848,15760, 5856,10696, 5864,8080, 5872,12176, 5880,16272, 5888,11328, + 5896,11344, 5904,8656, 5912,12752, 5920,11456, 5928,11472, 5936,9168, + 5944,13264, 5952,11584, 5960,11600, 5968,9680, 5976,13776, 5984,11712, + 5992,6096, 6000,10192, 6008,14288, 6016,11336, 6024,6608, 6032,10704, + 6040,14800, 6048,11464, 6056,7120, 6064,11216, 6072,15312, 6080,11592, + 6088,7632, 6096,11728, 6104,15824, 6112,11720, 6120,8144, 6128,12240, + 6136,16336, 6144,12288, 6152,12304, 6160,8216, 6168,12312, 6176,12416, + 6184,12432, 6192,8728, 6200,12824, 6208,12544, 6216,12560, 6224,9240, + 6232,13336, 6240,12672, 6248,12688, 6256,9752, 6264,13848, 6272,12296, + 6280,12312, 6288,10264, 6296,14360, 6304,12424, 6312,6680, 6320,10776, + 6328,14872, 6336,12552, 6344,7192, 6352,11288, 6360,15384, 6368,12680, + 6376,7704, 6384,11800, 6392,15896, 6400,13312, 6408,13328, 6416,8280, + 6424,12376, 6432,13440, 6440,13456, 6448,8792, 6456,12888, 6464,13568, + 6472,13584, 6480,9304, 6488,13400, 6496,13696, 6504,13712, 6512,9816, + 6520,13912, 6528,13320, 6536,13336, 6544,10328, 6552,14424, 6560,13448, + 6568,6744, 6576,10840, 6584,14936, 6592,13576, 6600,7256, 6608,11352, + 6616,15448, 6624,13704, 6632,7768, 6640,11864, 6648,15960, 6656,14336, + 6664,14352, 6672,8344, 6680,12440, 6688,14464, 6696,14480, 6704,8856, + 6712,12952, 6720,14592, 6728,14608, 6736,9368, 6744,13464, 6752,14720, + 6760,14736, 6768,9880, 6776,13976, 6784,14344, 6792,14360, 6800,10392, + 6808,14488, 6816,14472, 6824,14488, 6832,10904, 6840,15000, 6848,14600, + 6856,7320, 6864,11416, 6872,15512, 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15784,15792, 15800,16304, 15848,15856, + 15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000, + 15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160, + 15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264, + 15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048, + 16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184, + 16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264, + 16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208, + 16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352, + 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368, + 16328,16352, 16360,16368 +}; + +const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH] = +{ + /* radix 8, size 4032 */ + 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512, + 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184, + 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 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14320,28376, + 14328,32472, 14368,16664, 14376,20760, 14384,24856, 14392,28952, + 14432,17176, 14440,21272, 14448,25368, 14456,29464, 14496,17688, + 14504,21784, 14512,25880, 14520,29976, 14560,18200, 14568,22296, + 14576,26392, 14584,30488, 14624,18712, 14632,22808, 14640,26904, + 14648,31000, 14680,15128, 14688,19224, 14696,23320, 14704,27416, + 14712,31512, 14744,15640, 14752,19736, 14760,23832, 14768,27928, + 14776,32024, 14808,16152, 14816,20248, 14824,24344, 14832,28440, + 14840,32536, 14880,16728, 14888,20824, 14896,24920, 14904,29016, + 14944,17240, 14952,21336, 14960,25432, 14968,29528, 15008,17752, + 15016,21848, 15024,25944, 15032,30040, 15072,18264, 15080,22360, + 15088,26456, 15096,30552, 15136,18776, 15144,22872, 15152,26968, + 15160,31064, 15200,19288, 15208,23384, 15216,27480, 15224,31576, + 15256,15704, 15264,19800, 15272,23896, 15280,27992, 15288,32088, + 15320,16216, 15328,20312, 15336,24408, 15344,28504, 15352,32600, + 15392,16792, 15400,20888, 15408,24984, 15416,29080, 15456,17304, + 15464,21400, 15472,25496, 15480,29592, 15520,17816, 15528,21912, + 15536,26008, 15544,30104, 15584,18328, 15592,22424, 15600,26520, + 15608,30616, 15648,18840, 15656,22936, 15664,27032, 15672,31128, + 15712,19352, 15720,23448, 15728,27544, 15736,31640, 15776,19864, + 15784,23960, 15792,28056, 15800,32152, 15832,16280, 15840,20376, + 15848,24472, 15856,28568, 15864,32664, 15904,16856, 15912,20952, + 15920,25048, 15928,29144, 15968,17368, 15976,21464, 15984,25560, + 15992,29656, 16032,17880, 16040,21976, 16048,26072, 16056,30168, + 16096,18392, 16104,22488, 16112,26584, 16120,30680, 16160,18904, + 16168,23000, 16176,27096, 16184,31192, 16224,19416, 16232,23512, + 16240,27608, 16248,31704, 16288,19928, 16296,24024, 16304,28120, + 16312,32216, 16352,20440, 16360,24536, 16368,28632, 16376,32728, + 16424,20512, 16432,24608, 16440,28704, 16480,16928, 16488,21024, + 16496,25120, 16504,29216, 16544,17440, 16552,21536, 16560,25632, + 16568,29728, 16608,17952, 16616,22048, 16624,26144, 16632,30240, + 16672,18464, 16680,22560, 16688,26656, 16696,30752, 16736,18976, + 16744,23072, 16752,27168, 16760,31264, 16800,19488, 16808,23584, + 16816,27680, 16824,31776, 16864,20000, 16872,24096, 16880,28192, + 16888,32288, 16936,20576, 16944,24672, 16952,28768, 17000,21088, + 17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696, + 17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304, + 17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040, + 17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648, + 17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256, + 17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152, + 17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856, + 17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592, + 17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200, + 17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808, + 17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416, + 17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312, + 18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240, + 18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848, + 18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456, + 18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192, + 18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864, + 18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792, + 18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496, + 18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328, + 18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936, + 18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544, + 18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440, + 19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368, + 19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072, + 19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904, + 19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512, + 19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408, + 19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112, + 19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040, + 19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968, + 19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576, + 19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472, + 20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176, + 20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104, + 20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032, + 20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736, + 20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224, + 20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152, + 20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080, + 20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784, + 20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776, + 21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800, + 21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728, + 21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656, + 21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360, + 21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768, + 21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696, + 21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400, + 21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328, + 22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416, + 22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760, + 22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464, + 22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392, + 22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480, + 22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920, + 22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848, + 22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552, + 23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960, + 23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080, + 23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104, + 23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096, + 23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536, + 23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656, + 23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680, + 24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088, + 24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208, + 24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648, + 24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648, + 24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768, + 24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208, + 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808, + 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248, + 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368, + 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384, + 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824, + 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424, + 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376, + 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496, + 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024, + 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464, + 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576, + 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528, + 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640, + 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688, + 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216, + 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752, + 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312, + 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864, + 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928, + 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504, + 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632, + 32248,32696 +}; + + +const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH] = +{ + /* radix 4, size 12 */ + 8,64, 16,32, 24,96, 40,80, 56,112, 88,104 +}; + +const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH] = +{ + /* 4x2, size 24 */ + 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144, + 88,208, 104,176, 120,240, 152,200, 184,232 +}; + +const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH] = +{ + /* radix 4, size 56 */ + 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352, + 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432, + 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472 +}; + +const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH] = +{ + /* 4x2, size 112 */ + 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192, + 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608, + 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912, + 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624, + 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968, + 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984 +}; + +const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH] = +{ + /* radix 4, size 240 */ + 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640, + 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320, + 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960, + 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672, + 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376, + 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040, + 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912, + 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488, + 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456, + 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520, + 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928, + 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832, + 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816, + 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976 +}; + +const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH] = +{ + /* 4x2, size 480 */ + 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280, + 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640, + 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944, + 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648, + 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216, + 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960, + 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616, + 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184, + 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976, + 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400, + 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784, + 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064, + 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344, + 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728, + 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152, + 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920, + 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024, + 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376, + 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480, + 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696, + 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824, + 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312, + 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464, + 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912, + 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624, + 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008, + 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072, + 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928, + 3512,3800, 3576,4056, 3704,3896, 3832,4024 +}; + +const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH] = +{ + /* radix 4, size 992 */ + 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, + 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, + 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, + 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, + 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, + 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, + 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, + 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, + 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, + 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, + 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, + 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, + 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, + 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, + 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, + 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, + 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, + 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, + 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, + 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, + 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, + 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, + 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, + 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, + 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, + 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, + 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, + 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, + 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, + 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, + 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, + 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, + 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, + 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, + 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, + 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, + 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, + 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, + 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, + 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, + 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, + 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, + 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, + 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, + 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, + 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, + 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, + 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, + 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, + 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, + 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, + 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, + 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, + 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, + 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, + 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, + 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, + 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, + 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, + 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, + 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, + 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, + 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, + 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, + 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, + 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, + 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, + 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, + 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 +}; + +const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH] = +{ + /* 4x2, size 1984 */ + 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, + 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, + 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, + 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, + 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, + 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, + 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, + 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, + 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, + 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, + 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, + 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, + 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, + 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, + 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, + 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, + 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, + 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, + 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, + 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, + 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, + 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, + 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, + 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, + 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, + 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, + 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, + 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, + 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, + 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, + 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, + 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, + 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, + 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, + 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, + 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, + 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, + 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, + 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, + 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, + 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, + 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, + 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, + 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, + 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, + 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, + 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, + 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, + 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, + 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, + 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, + 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, + 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, + 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, + 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, + 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, + 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, + 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, + 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, + 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, + 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, + 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, + 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, + 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, + 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, + 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, + 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, + 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, + 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, + 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, + 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, + 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, + 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, + 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664, + 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248, + 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272, + 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392, + 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736, + 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952, + 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648, + 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992, + 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016, + 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424, + 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008, + 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888, + 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680, + 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264, + 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240, + 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264, + 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848, + 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728, + 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520, + 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104, + 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080, + 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392, + 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976, + 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856, + 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648, + 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232, + 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112, + 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328, + 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864, + 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560, + 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632, + 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096, + 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528, + 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600, + 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064, + 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832, + 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296, + 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368, + 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272, + 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736, + 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600, + 8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064, + 8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136, + 8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400, + 8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960, + 8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608, + 9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240, + 9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312, + 9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824, + 9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616, + 9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128, + 9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200, + 9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560, + 9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072, + 10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816, + 10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328, + 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840, + 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584, + 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048, + 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504, + 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992, + 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688, + 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296, + 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952, + 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672, + 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232, + 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080, + 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848, + 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336, + 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616, + 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152, + 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024, + 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280, + 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680, + 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576, + 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344, + 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184, + 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248 +}; + +const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH] = +{ + /* radix 4, size 4032 */ + 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, + 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, + 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, + 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, + 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, + 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, + 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, + 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, + 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, + 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, + 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, + 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, + 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, + 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, + 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, + 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, + 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, + 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, + 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, + 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, + 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, + 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, + 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, + 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, + 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976, + 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144, + 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288, + 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576, + 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432, + 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720, + 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888, + 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032, + 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088, + 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944, + 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232, + 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400, + 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544, + 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256, + 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496, + 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784, + 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376, + 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232, + 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152, + 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008, + 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296, + 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888, + 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744, + 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896, + 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560, + 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728, + 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392, + 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680, + 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312, + 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976, + 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432, + 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288, + 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576, + 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480, + 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720, + 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312, + 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840, + 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896, + 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136, + 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424, + 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016, + 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872, + 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024, + 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688, + 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856, + 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144, + 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808, + 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440, + 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104, + 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560, + 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224, + 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416, + 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464, + 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752, + 4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344, + 4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584, + 4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640, + 4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168, + 4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760, + 4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000, + 4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288, + 4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960, + 4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624, + 4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792, + 4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456, + 4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376, + 4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424, + 4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016, + 5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256, + 5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544, + 5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832, + 5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496, + 5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472, + 5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712, + 5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152, + 5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816, + 5480,23200, 5488,15008, 5496,31392, 5512,18080, 5520,9888, 5528,26272, + 5536,5792, 5544,22176, 5552,13984, 5560,30368, 5576,20128, 5584,11936, + 5592,28320, 5600,7840, 5608,24224, 5616,16032, 5624,32416, 5640,16800, + 5648,8608, 5656,24992, 5672,20896, 5680,12704, 5688,29088, 5704,18848, + 5712,10656, 5720,27040, 5728,6560, 5736,22944, 5744,14752, 5752,31136, + 5768,17824, 5776,9632, 5784,26016, 5800,21920, 5808,13728, 5816,30112, + 5832,19872, 5840,11680, 5848,28064, 5856,7584, 5864,23968, 5872,15776, + 5880,32160, 5896,17312, 5904,9120, 5912,25504, 5928,21408, 5936,13216, + 5944,29600, 5960,19360, 5968,11168, 5976,27552, 5984,7072, 5992,23456, + 6000,15264, 6008,31648, 6024,18336, 6032,10144, 6040,26528, 6056,22432, + 6064,14240, 6072,30624, 6088,20384, 6096,12192, 6104,28576, 6112,8096, + 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28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, + 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, + 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, + 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, + 31480,32120, 31736,32632, 32248,32504 +}; + +/** +* \par +* Example code for Floating-point RFFT Twiddle factors Generation: +* \par +* 
TW = exp(2*pi*i*[0:L/2-1]/L - pi/2*i).'
+* \par +* Real and Imag values are in interleaved fashion +*/ +const float32_t twiddleCoef_rfft_32[32] = { + 0.000000000f, 1.000000000f, + 0.195090322f, 0.980785280f, + 0.382683432f, 0.923879533f, + 0.555570233f, 0.831469612f, + 0.707106781f, 0.707106781f, + 0.831469612f, 0.555570233f, + 0.923879533f, 0.382683432f, + 0.980785280f, 0.195090322f, + 1.000000000f, 0.000000000f, + 0.980785280f, -0.195090322f, + 0.923879533f, -0.382683432f, + 0.831469612f, -0.555570233f, + 0.707106781f, -0.707106781f, + 0.555570233f, -0.831469612f, + 0.382683432f, -0.923879533f, + 0.195090322f, -0.980785280f +}; + +const float32_t twiddleCoef_rfft_64[64] = { + 0.000000000000000f, 1.000000000000000f, + 0.098017140329561f, 0.995184726672197f, + 0.195090322016128f, 0.980785280403230f, + 0.290284677254462f, 0.956940335732209f, + 0.382683432365090f, 0.923879532511287f, + 0.471396736825998f, 0.881921264348355f, + 0.555570233019602f, 0.831469612302545f, + 0.634393284163645f, 0.773010453362737f, + 0.707106781186547f, 0.707106781186548f, + 0.773010453362737f, 0.634393284163645f, + 0.831469612302545f, 0.555570233019602f, + 0.881921264348355f, 0.471396736825998f, + 0.923879532511287f, 0.382683432365090f, + 0.956940335732209f, 0.290284677254462f, + 0.980785280403230f, 0.195090322016128f, + 0.995184726672197f, 0.098017140329561f, + 1.000000000000000f, 0.000000000000000f, + 0.995184726672197f, -0.098017140329561f, + 0.980785280403230f, -0.195090322016128f, + 0.956940335732209f, -0.290284677254462f, + 0.923879532511287f, -0.382683432365090f, + 0.881921264348355f, -0.471396736825998f, + 0.831469612302545f, -0.555570233019602f, + 0.773010453362737f, -0.634393284163645f, + 0.707106781186548f, -0.707106781186547f, + 0.634393284163645f, -0.773010453362737f, + 0.555570233019602f, -0.831469612302545f, + 0.471396736825998f, -0.881921264348355f, + 0.382683432365090f, -0.923879532511287f, + 0.290284677254462f, -0.956940335732209f, + 0.195090322016129f, -0.980785280403230f, + 0.098017140329561f, -0.995184726672197f +}; + +const float32_t twiddleCoef_rfft_128[128] = { + 0.000000000f, 1.000000000f, + 0.049067674f, 0.998795456f, + 0.098017140f, 0.995184727f, + 0.146730474f, 0.989176510f, + 0.195090322f, 0.980785280f, + 0.242980180f, 0.970031253f, + 0.290284677f, 0.956940336f, + 0.336889853f, 0.941544065f, + 0.382683432f, 0.923879533f, + 0.427555093f, 0.903989293f, + 0.471396737f, 0.881921264f, + 0.514102744f, 0.857728610f, + 0.555570233f, 0.831469612f, + 0.595699304f, 0.803207531f, + 0.634393284f, 0.773010453f, + 0.671558955f, 0.740951125f, + 0.707106781f, 0.707106781f, + 0.740951125f, 0.671558955f, + 0.773010453f, 0.634393284f, + 0.803207531f, 0.595699304f, + 0.831469612f, 0.555570233f, + 0.857728610f, 0.514102744f, + 0.881921264f, 0.471396737f, + 0.903989293f, 0.427555093f, + 0.923879533f, 0.382683432f, + 0.941544065f, 0.336889853f, + 0.956940336f, 0.290284677f, + 0.970031253f, 0.242980180f, + 0.980785280f, 0.195090322f, + 0.989176510f, 0.146730474f, + 0.995184727f, 0.098017140f, + 0.998795456f, 0.049067674f, + 1.000000000f, 0.000000000f, + 0.998795456f, -0.049067674f, + 0.995184727f, -0.098017140f, + 0.989176510f, -0.146730474f, + 0.980785280f, -0.195090322f, + 0.970031253f, -0.242980180f, + 0.956940336f, -0.290284677f, + 0.941544065f, -0.336889853f, + 0.923879533f, -0.382683432f, + 0.903989293f, -0.427555093f, + 0.881921264f, -0.471396737f, + 0.857728610f, -0.514102744f, + 0.831469612f, -0.555570233f, + 0.803207531f, -0.595699304f, + 0.773010453f, -0.634393284f, + 0.740951125f, -0.671558955f, + 0.707106781f, -0.707106781f, + 0.671558955f, -0.740951125f, + 0.634393284f, -0.773010453f, + 0.595699304f, -0.803207531f, + 0.555570233f, -0.831469612f, + 0.514102744f, -0.857728610f, + 0.471396737f, -0.881921264f, + 0.427555093f, -0.903989293f, + 0.382683432f, -0.923879533f, + 0.336889853f, -0.941544065f, + 0.290284677f, -0.956940336f, + 0.242980180f, -0.970031253f, + 0.195090322f, -0.980785280f, + 0.146730474f, -0.989176510f, + 0.098017140f, -0.995184727f, + 0.049067674f, -0.998795456f +}; + +const float32_t twiddleCoef_rfft_256[256] = { + 0.000000000f, 1.000000000f, + 0.024541229f, 0.999698819f, + 0.049067674f, 0.998795456f, + 0.073564564f, 0.997290457f, + 0.098017140f, 0.995184727f, + 0.122410675f, 0.992479535f, + 0.146730474f, 0.989176510f, + 0.170961889f, 0.985277642f, + 0.195090322f, 0.980785280f, + 0.219101240f, 0.975702130f, + 0.242980180f, 0.970031253f, + 0.266712757f, 0.963776066f, + 0.290284677f, 0.956940336f, + 0.313681740f, 0.949528181f, + 0.336889853f, 0.941544065f, + 0.359895037f, 0.932992799f, + 0.382683432f, 0.923879533f, + 0.405241314f, 0.914209756f, + 0.427555093f, 0.903989293f, + 0.449611330f, 0.893224301f, + 0.471396737f, 0.881921264f, + 0.492898192f, 0.870086991f, + 0.514102744f, 0.857728610f, + 0.534997620f, 0.844853565f, + 0.555570233f, 0.831469612f, + 0.575808191f, 0.817584813f, + 0.595699304f, 0.803207531f, + 0.615231591f, 0.788346428f, + 0.634393284f, 0.773010453f, + 0.653172843f, 0.757208847f, + 0.671558955f, 0.740951125f, + 0.689540545f, 0.724247083f, + 0.707106781f, 0.707106781f, + 0.724247083f, 0.689540545f, + 0.740951125f, 0.671558955f, + 0.757208847f, 0.653172843f, + 0.773010453f, 0.634393284f, + 0.788346428f, 0.615231591f, + 0.803207531f, 0.595699304f, + 0.817584813f, 0.575808191f, + 0.831469612f, 0.555570233f, + 0.844853565f, 0.534997620f, + 0.857728610f, 0.514102744f, + 0.870086991f, 0.492898192f, + 0.881921264f, 0.471396737f, + 0.893224301f, 0.449611330f, + 0.903989293f, 0.427555093f, + 0.914209756f, 0.405241314f, + 0.923879533f, 0.382683432f, + 0.932992799f, 0.359895037f, + 0.941544065f, 0.336889853f, + 0.949528181f, 0.313681740f, + 0.956940336f, 0.290284677f, + 0.963776066f, 0.266712757f, + 0.970031253f, 0.242980180f, + 0.975702130f, 0.219101240f, + 0.980785280f, 0.195090322f, + 0.985277642f, 0.170961889f, + 0.989176510f, 0.146730474f, + 0.992479535f, 0.122410675f, + 0.995184727f, 0.098017140f, + 0.997290457f, 0.073564564f, + 0.998795456f, 0.049067674f, + 0.999698819f, 0.024541229f, + 1.000000000f, 0.000000000f, + 0.999698819f, -0.024541229f, + 0.998795456f, -0.049067674f, + 0.997290457f, -0.073564564f, + 0.995184727f, -0.098017140f, + 0.992479535f, -0.122410675f, + 0.989176510f, -0.146730474f, + 0.985277642f, -0.170961889f, + 0.980785280f, -0.195090322f, + 0.975702130f, -0.219101240f, + 0.970031253f, -0.242980180f, + 0.963776066f, -0.266712757f, + 0.956940336f, -0.290284677f, + 0.949528181f, -0.313681740f, + 0.941544065f, -0.336889853f, + 0.932992799f, -0.359895037f, + 0.923879533f, -0.382683432f, + 0.914209756f, -0.405241314f, + 0.903989293f, -0.427555093f, + 0.893224301f, -0.449611330f, + 0.881921264f, -0.471396737f, + 0.870086991f, -0.492898192f, + 0.857728610f, -0.514102744f, + 0.844853565f, -0.534997620f, + 0.831469612f, -0.555570233f, + 0.817584813f, -0.575808191f, + 0.803207531f, -0.595699304f, + 0.788346428f, -0.615231591f, + 0.773010453f, -0.634393284f, + 0.757208847f, -0.653172843f, + 0.740951125f, -0.671558955f, + 0.724247083f, -0.689540545f, + 0.707106781f, -0.707106781f, + 0.689540545f, -0.724247083f, + 0.671558955f, -0.740951125f, + 0.653172843f, -0.757208847f, + 0.634393284f, -0.773010453f, + 0.615231591f, -0.788346428f, + 0.595699304f, -0.803207531f, + 0.575808191f, -0.817584813f, + 0.555570233f, -0.831469612f, + 0.534997620f, -0.844853565f, + 0.514102744f, -0.857728610f, + 0.492898192f, -0.870086991f, + 0.471396737f, -0.881921264f, + 0.449611330f, -0.893224301f, + 0.427555093f, -0.903989293f, + 0.405241314f, -0.914209756f, + 0.382683432f, -0.923879533f, + 0.359895037f, -0.932992799f, + 0.336889853f, -0.941544065f, + 0.313681740f, -0.949528181f, + 0.290284677f, -0.956940336f, + 0.266712757f, -0.963776066f, + 0.242980180f, -0.970031253f, + 0.219101240f, -0.975702130f, + 0.195090322f, -0.980785280f, + 0.170961889f, -0.985277642f, + 0.146730474f, -0.989176510f, + 0.122410675f, -0.992479535f, + 0.098017140f, -0.995184727f, + 0.073564564f, -0.997290457f, + 0.049067674f, -0.998795456f, + 0.024541229f, -0.999698819f +}; + +const float32_t twiddleCoef_rfft_512[512] = { + 0.000000000f, 1.000000000f, + 0.012271538f, 0.999924702f, + 0.024541229f, 0.999698819f, + 0.036807223f, 0.999322385f, + 0.049067674f, 0.998795456f, + 0.061320736f, 0.998118113f, + 0.073564564f, 0.997290457f, + 0.085797312f, 0.996312612f, + 0.098017140f, 0.995184727f, + 0.110222207f, 0.993906970f, + 0.122410675f, 0.992479535f, + 0.134580709f, 0.990902635f, + 0.146730474f, 0.989176510f, + 0.158858143f, 0.987301418f, + 0.170961889f, 0.985277642f, + 0.183039888f, 0.983105487f, + 0.195090322f, 0.980785280f, + 0.207111376f, 0.978317371f, + 0.219101240f, 0.975702130f, + 0.231058108f, 0.972939952f, + 0.242980180f, 0.970031253f, + 0.254865660f, 0.966976471f, + 0.266712757f, 0.963776066f, + 0.278519689f, 0.960430519f, + 0.290284677f, 0.956940336f, + 0.302005949f, 0.953306040f, + 0.313681740f, 0.949528181f, + 0.325310292f, 0.945607325f, + 0.336889853f, 0.941544065f, + 0.348418680f, 0.937339012f, + 0.359895037f, 0.932992799f, + 0.371317194f, 0.928506080f, + 0.382683432f, 0.923879533f, + 0.393992040f, 0.919113852f, + 0.405241314f, 0.914209756f, + 0.416429560f, 0.909167983f, + 0.427555093f, 0.903989293f, + 0.438616239f, 0.898674466f, + 0.449611330f, 0.893224301f, + 0.460538711f, 0.887639620f, + 0.471396737f, 0.881921264f, + 0.482183772f, 0.876070094f, + 0.492898192f, 0.870086991f, + 0.503538384f, 0.863972856f, + 0.514102744f, 0.857728610f, + 0.524589683f, 0.851355193f, + 0.534997620f, 0.844853565f, + 0.545324988f, 0.838224706f, + 0.555570233f, 0.831469612f, + 0.565731811f, 0.824589303f, + 0.575808191f, 0.817584813f, + 0.585797857f, 0.810457198f, + 0.595699304f, 0.803207531f, + 0.605511041f, 0.795836905f, + 0.615231591f, 0.788346428f, + 0.624859488f, 0.780737229f, + 0.634393284f, 0.773010453f, + 0.643831543f, 0.765167266f, + 0.653172843f, 0.757208847f, + 0.662415778f, 0.749136395f, + 0.671558955f, 0.740951125f, + 0.680600998f, 0.732654272f, + 0.689540545f, 0.724247083f, + 0.698376249f, 0.715730825f, + 0.707106781f, 0.707106781f, + 0.715730825f, 0.698376249f, + 0.724247083f, 0.689540545f, + 0.732654272f, 0.680600998f, + 0.740951125f, 0.671558955f, + 0.749136395f, 0.662415778f, + 0.757208847f, 0.653172843f, + 0.765167266f, 0.643831543f, + 0.773010453f, 0.634393284f, + 0.780737229f, 0.624859488f, + 0.788346428f, 0.615231591f, + 0.795836905f, 0.605511041f, + 0.803207531f, 0.595699304f, + 0.810457198f, 0.585797857f, + 0.817584813f, 0.575808191f, + 0.824589303f, 0.565731811f, + 0.831469612f, 0.555570233f, + 0.838224706f, 0.545324988f, + 0.844853565f, 0.534997620f, + 0.851355193f, 0.524589683f, + 0.857728610f, 0.514102744f, + 0.863972856f, 0.503538384f, + 0.870086991f, 0.492898192f, + 0.876070094f, 0.482183772f, + 0.881921264f, 0.471396737f, + 0.887639620f, 0.460538711f, + 0.893224301f, 0.449611330f, + 0.898674466f, 0.438616239f, + 0.903989293f, 0.427555093f, + 0.909167983f, 0.416429560f, + 0.914209756f, 0.405241314f, + 0.919113852f, 0.393992040f, + 0.923879533f, 0.382683432f, + 0.928506080f, 0.371317194f, + 0.932992799f, 0.359895037f, + 0.937339012f, 0.348418680f, + 0.941544065f, 0.336889853f, + 0.945607325f, 0.325310292f, + 0.949528181f, 0.313681740f, + 0.953306040f, 0.302005949f, + 0.956940336f, 0.290284677f, + 0.960430519f, 0.278519689f, + 0.963776066f, 0.266712757f, + 0.966976471f, 0.254865660f, + 0.970031253f, 0.242980180f, + 0.972939952f, 0.231058108f, + 0.975702130f, 0.219101240f, + 0.978317371f, 0.207111376f, + 0.980785280f, 0.195090322f, + 0.983105487f, 0.183039888f, + 0.985277642f, 0.170961889f, + 0.987301418f, 0.158858143f, + 0.989176510f, 0.146730474f, + 0.990902635f, 0.134580709f, + 0.992479535f, 0.122410675f, + 0.993906970f, 0.110222207f, + 0.995184727f, 0.098017140f, + 0.996312612f, 0.085797312f, + 0.997290457f, 0.073564564f, + 0.998118113f, 0.061320736f, + 0.998795456f, 0.049067674f, + 0.999322385f, 0.036807223f, + 0.999698819f, 0.024541229f, + 0.999924702f, 0.012271538f, + 1.000000000f, 0.000000000f, + 0.999924702f, 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-0.999801170f, + 0.018406730f, -0.999830582f, + 0.016872988f, -0.999857641f, + 0.015339206f, -0.999882347f, + 0.013805389f, -0.999904701f, + 0.012271538f, -0.999924702f, + 0.010737659f, -0.999942350f, + 0.009203755f, -0.999957645f, + 0.007669829f, -0.999970586f, + 0.006135885f, -0.999981175f, + 0.004601926f, -0.999989411f, + 0.003067957f, -0.999995294f, + 0.001533980f, -0.999998823f +}; + + +/** + * \par + * Example code for the generation of the floating-point sine table: + * 
+ * tableSize = 512;
+ * for(n = 0; n < (tableSize + 1); n++)
+ * {
+ *	sinTable[n]=sin(2*pi*n/tableSize);
+ * }
+ * \par + * where pi value is 3.14159265358979 + */ + +const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = { + 0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f, + 0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f, + 0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f, + 0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f, + 0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f, + 0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f, + 0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f, + 0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f, + 0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f, + 0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f, + 0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f, + 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0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f, + 0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f, + 0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f, + 0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f, + 0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f, + 0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f, + 0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f, + -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f, + -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f, + -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f, + -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f, + -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f, + -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f, + 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-0.94560733f, + -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f, + -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f, + -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f, + -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f, + -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f, + -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f, + -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f, + -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f, + -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f, + -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f, + -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f, + -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f, + -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f, + -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f, + -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f, + -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f, + -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f, + -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f, + -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f, + -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f, + -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f, + -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f, + -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f, + -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f, + -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f, + -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f, + -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f, + -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f, + -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f, + -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f, + -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f +}; + +/** + * \par + * Table values are in Q31 (1.31 fixed-point format) and generation is done in + * three steps. First, generate sin values in floating point: + * 
+ * tableSize = 512;
+ * for(n = 0; n < (tableSize + 1); n++)
+ * {
+ *	sinTable[n]= sin(2*pi*n/tableSize);
+ * }
+ * where pi value is 3.14159265358979 + * \par + * Second, convert floating-point to Q31 (Fixed point): + * (sinTable[i] * pow(2, 31)) + * \par + * Finally, round to the nearest integer value: + * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); + */ +const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1] = { + 0L, 26352928L, 52701887L, 79042909L, 105372028L, 131685278L, 157978697L, + 184248325L, 210490206L, 236700388L, 262874923L, 289009871L, 315101295L, + 341145265L, 367137861L, 393075166L, 418953276L, 444768294L, 470516330L, + 496193509L, 521795963L, 547319836L, 572761285L, 598116479L, 623381598L, + 648552838L, 673626408L, 698598533L, 723465451L, 748223418L, 772868706L, + 797397602L, 821806413L, 846091463L, 870249095L, 894275671L, 918167572L, + 941921200L, 965532978L, 988999351L, 1012316784L, 1035481766L, 1058490808L, + 1081340445L, 1104027237L, 1126547765L, 1148898640L, 1171076495L, 1193077991L, + 1214899813L, 1236538675L, 1257991320L, 1279254516L, 1300325060L, 1321199781L, + 1341875533L, 1362349204L, 1382617710L, 1402678000L, 1422527051L, 1442161874L, + 1461579514L, 1480777044L, 1499751576L, 1518500250L, 1537020244L, 1555308768L, + 1573363068L, 1591180426L, 1608758157L, 1626093616L, 1643184191L, 1660027308L, + 1676620432L, 1692961062L, 1709046739L, 1724875040L, 1740443581L, 1755750017L, + 1770792044L, 1785567396L, 1800073849L, 1814309216L, 1828271356L, 1841958164L, + 1855367581L, 1868497586L, 1881346202L, 1893911494L, 1906191570L, 1918184581L, + 1929888720L, 1941302225L, 1952423377L, 1963250501L, 1973781967L, 1984016189L, + 1993951625L, 2003586779L, 2012920201L, 2021950484L, 2030676269L, 2039096241L, + 2047209133L, 2055013723L, 2062508835L, 2069693342L, 2076566160L, 2083126254L, + 2089372638L, 2095304370L, 2100920556L, 2106220352L, 2111202959L, 2115867626L, + 2120213651L, 2124240380L, 2127947206L, 2131333572L, 2134398966L, 2137142927L, + 2139565043L, 2141664948L, 2143442326L, 2144896910L, 2146028480L, 2146836866L, + 2147321946L, 2147483647L, 2147321946L, 2146836866L, 2146028480L, 2144896910L, + 2143442326L, 2141664948L, 2139565043L, 2137142927L, 2134398966L, 2131333572L, + 2127947206L, 2124240380L, 2120213651L, 2115867626L, 2111202959L, 2106220352L, + 2100920556L, 2095304370L, 2089372638L, 2083126254L, 2076566160L, 2069693342L, + 2062508835L, 2055013723L, 2047209133L, 2039096241L, 2030676269L, 2021950484L, + 2012920201L, 2003586779L, 1993951625L, 1984016189L, 1973781967L, 1963250501L, + 1952423377L, 1941302225L, 1929888720L, 1918184581L, 1906191570L, 1893911494L, + 1881346202L, 1868497586L, 1855367581L, 1841958164L, 1828271356L, 1814309216L, + 1800073849L, 1785567396L, 1770792044L, 1755750017L, 1740443581L, 1724875040L, + 1709046739L, 1692961062L, 1676620432L, 1660027308L, 1643184191L, 1626093616L, + 1608758157L, 1591180426L, 1573363068L, 1555308768L, 1537020244L, 1518500250L, + 1499751576L, 1480777044L, 1461579514L, 1442161874L, 1422527051L, 1402678000L, + 1382617710L, 1362349204L, 1341875533L, 1321199781L, 1300325060L, 1279254516L, + 1257991320L, 1236538675L, 1214899813L, 1193077991L, 1171076495L, 1148898640L, + 1126547765L, 1104027237L, 1081340445L, 1058490808L, 1035481766L, 1012316784L, + 988999351L, 965532978L, 941921200L, 918167572L, 894275671L, 870249095L, + 846091463L, 821806413L, 797397602L, 772868706L, 748223418L, 723465451L, + 698598533L, 673626408L, 648552838L, 623381598L, 598116479L, 572761285L, + 547319836L, 521795963L, 496193509L, 470516330L, 444768294L, 418953276L, + 393075166L, 367137861L, 341145265L, 315101295L, 289009871L, 262874923L, + 236700388L, 210490206L, 184248325L, 157978697L, 131685278L, 105372028L, + 79042909L, 52701887L, 26352928L, 0L, -26352928L, -52701887L, -79042909L, + -105372028L, -131685278L, -157978697L, -184248325L, -210490206L, -236700388L, + -262874923L, -289009871L, -315101295L, -341145265L, -367137861L, -393075166L, + -418953276L, -444768294L, -470516330L, -496193509L, -521795963L, -547319836L, + -572761285L, -598116479L, -623381598L, -648552838L, -673626408L, -698598533L, + -723465451L, -748223418L, -772868706L, -797397602L, -821806413L, -846091463L, + -870249095L, -894275671L, -918167572L, -941921200L, -965532978L, -988999351L, + -1012316784L, -1035481766L, -1058490808L, -1081340445L, -1104027237L, + -1126547765L, -1148898640L, -1171076495L, -1193077991L, -1214899813L, + -1236538675L, -1257991320L, -1279254516L, -1300325060L, -1321199781L, + -1341875533L, -1362349204L, -1382617710L, -1402678000L, -1422527051L, + -1442161874L, -1461579514L, -1480777044L, -1499751576L, -1518500250L, + -1537020244L, -1555308768L, -1573363068L, -1591180426L, -1608758157L, + -1626093616L, -1643184191L, -1660027308L, -1676620432L, -1692961062L, + -1709046739L, -1724875040L, -1740443581L, -1755750017L, -1770792044L, + -1785567396L, -1800073849L, -1814309216L, -1828271356L, -1841958164L, + -1855367581L, -1868497586L, -1881346202L, -1893911494L, -1906191570L, + -1918184581L, -1929888720L, -1941302225L, -1952423377L, -1963250501L, + -1973781967L, -1984016189L, -1993951625L, -2003586779L, -2012920201L, + -2021950484L, -2030676269L, -2039096241L, -2047209133L, -2055013723L, + -2062508835L, -2069693342L, -2076566160L, -2083126254L, -2089372638L, + -2095304370L, -2100920556L, -2106220352L, -2111202959L, -2115867626L, + -2120213651L, -2124240380L, -2127947206L, -2131333572L, -2134398966L, + -2137142927L, -2139565043L, -2141664948L, -2143442326L, -2144896910L, + -2146028480L, -2146836866L, -2147321946L, (q31_t)0x80000000, -2147321946L, + -2146836866L, -2146028480L, -2144896910L, -2143442326L, -2141664948L, + -2139565043L, -2137142927L, -2134398966L, -2131333572L, -2127947206L, + -2124240380L, -2120213651L, -2115867626L, -2111202959L, -2106220352L, + -2100920556L, -2095304370L, -2089372638L, -2083126254L, -2076566160L, + -2069693342L, -2062508835L, -2055013723L, -2047209133L, -2039096241L, + -2030676269L, -2021950484L, -2012920201L, -2003586779L, -1993951625L, + -1984016189L, -1973781967L, -1963250501L, -1952423377L, -1941302225L, + -1929888720L, -1918184581L, -1906191570L, -1893911494L, -1881346202L, + -1868497586L, -1855367581L, -1841958164L, -1828271356L, -1814309216L, + -1800073849L, -1785567396L, -1770792044L, -1755750017L, -1740443581L, + -1724875040L, -1709046739L, -1692961062L, -1676620432L, -1660027308L, + -1643184191L, -1626093616L, -1608758157L, -1591180426L, -1573363068L, + -1555308768L, -1537020244L, -1518500250L, -1499751576L, -1480777044L, + -1461579514L, -1442161874L, -1422527051L, -1402678000L, -1382617710L, + -1362349204L, -1341875533L, -1321199781L, -1300325060L, -1279254516L, + -1257991320L, -1236538675L, -1214899813L, -1193077991L, -1171076495L, + -1148898640L, -1126547765L, -1104027237L, -1081340445L, -1058490808L, + -1035481766L, -1012316784L, -988999351L, -965532978L, -941921200L, + -918167572L, -894275671L, -870249095L, -846091463L, -821806413L, -797397602L, + -772868706L, -748223418L, -723465451L, -698598533L, -673626408L, -648552838L, + -623381598L, -598116479L, -572761285L, -547319836L, -521795963L, -496193509L, + -470516330L, -444768294L, -418953276L, -393075166L, -367137861L, -341145265L, + -315101295L, -289009871L, -262874923L, -236700388L, -210490206L, -184248325L, + -157978697L, -131685278L, -105372028L, -79042909L, -52701887L, -26352928L, 0 +}; + +/** + * \par + * Table values are in Q15 (1.15 fixed-point format) and generation is done in + * three steps. First, generate sin values in floating point: + * 
+ * tableSize = 512;
+ * for(n = 0; n < (tableSize + 1); n++)
+ * {
+ *	sinTable[n]= sin(2*pi*n/tableSize);
+ * }
+ * where pi value is 3.14159265358979 + * \par + * Second, convert floating-point to Q15 (Fixed point): + * (sinTable[i] * pow(2, 15)) + * \par + * Finally, round to the nearest integer value: + * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); + */ +const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1] = { + 0, 402, 804, 1206, 1608, 2009, 2411, 2811, 3212, 3612, 4011, 4410, 4808, + 5205, 5602, 5998, 6393, 6787, 7180, 7571, 7962, 8351, 8740, 9127, 9512, + 9896, 10279, 10660, 11039, 11417, 11793, 12167, 12540, 12910, 13279, + 13646, 14010, 14373, 14733, 15091, 15447, 15800, 16151, 16500, 16846, + 17190, 17531, 17869, 18205, 18538, 18868, 19195, 19520, 19841, 20160, + 20475, 20788, 21097, 21403, 21706, 22006, 22302, 22595, 22884, 23170, + 23453, 23732, 24008, 24279, 24548, 24812, 25073, 25330, 25583, 25833, + 26078, 26320, 26557, 26791, 27020, 27246, 27467, 27684, 27897, 28106, + 28311, 28511, 28707, 28899, 29086, 29269, 29448, 29622, 29792, 29957, + 30118, 30274, 30425, 30572, 30715, 30853, 30986, 31114, 31238, 31357, + 31471, 31581, 31686, 31786, 31881, 31972, 32058, 32138, 32214, 32286, + 32352, 32413, 32470, 32522, 32568, 32610, 32647, 32679, 32706, 32729, + 32746, 32758, 32766, 32767, 32766, 32758, 32746, 32729, 32706, 32679, + 32647, 32610, 32568, 32522, 32470, 32413, 32352, 32286, 32214, 32138, + 32058, 31972, 31881, 31786, 31686, 31581, 31471, 31357, 31238, 31114, + 30986, 30853, 30715, 30572, 30425, 30274, 30118, 29957, 29792, 29622, + 29448, 29269, 29086, 28899, 28707, 28511, 28311, 28106, 27897, 27684, + 27467, 27246, 27020, 26791, 26557, 26320, 26078, 25833, 25583, 25330, + 25073, 24812, 24548, 24279, 24008, 23732, 23453, 23170, 22884, 22595, + 22302, 22006, 21706, 21403, 21097, 20788, 20475, 20160, 19841, 19520, + 19195, 18868, 18538, 18205, 17869, 17531, 17190, 16846, 16500, 16151, + 15800, 15447, 15091, 14733, 14373, 14010, 13646, 13279, 12910, 12540, + 12167, 11793, 11417, 11039, 10660, 10279, 9896, 9512, 9127, 8740, 8351, + 7962, 7571, 7180, 6787, 6393, 5998, 5602, 5205, 4808, 4410, 4011, 3612, + 3212, 2811, 2411, 2009, 1608, 1206, 804, 402, 0, -402, -804, -1206, + -1608, -2009, -2411, -2811, -3212, -3612, -4011, -4410, -4808, -5205, + -5602, -5998, -6393, -6787, -7180, -7571, -7962, -8351, -8740, -9127, + -9512, -9896, -10279, -10660, -11039, -11417, -11793, -12167, -12540, + -12910, -13279, -13646, -14010, -14373, -14733, -15091, -15447, -15800, + -16151, -16500, -16846, -17190, -17531, -17869, -18205, -18538, -18868, + -19195, -19520, -19841, -20160, -20475, -20788, -21097, -21403, -21706, + -22006, -22302, -22595, -22884, -23170, -23453, -23732, -24008, -24279, + -24548, -24812, -25073, -25330, -25583, -25833, -26078, -26320, -26557, + -26791, -27020, -27246, -27467, -27684, -27897, -28106, -28311, -28511, + -28707, -28899, -29086, -29269, -29448, -29622, -29792, -29957, -30118, + -30274, -30425, -30572, -30715, -30853, -30986, -31114, -31238, -31357, + -31471, -31581, -31686, -31786, -31881, -31972, -32058, -32138, -32214, + -32286, -32352, -32413, -32470, -32522, -32568, -32610, -32647, -32679, + -32706, -32729, -32746, -32758, -32766, -32768, -32766, -32758, -32746, + -32729, -32706, -32679, -32647, -32610, -32568, -32522, -32470, -32413, + -32352, -32286, -32214, -32138, -32058, -31972, -31881, -31786, -31686, + -31581, -31471, -31357, -31238, -31114, -30986, -30853, -30715, -30572, + -30425, -30274, -30118, -29957, -29792, -29622, -29448, -29269, -29086, + -28899, -28707, -28511, -28311, -28106, -27897, -27684, -27467, -27246, + -27020, -26791, -26557, -26320, -26078, -25833, -25583, -25330, -25073, + -24812, -24548, -24279, -24008, -23732, -23453, -23170, -22884, -22595, + -22302, -22006, -21706, -21403, -21097, -20788, -20475, -20160, -19841, + -19520, -19195, -18868, -18538, -18205, -17869, -17531, -17190, -16846, + -16500, -16151, -15800, -15447, -15091, -14733, -14373, -14010, -13646, + -13279, -12910, -12540, -12167, -11793, -11417, -11039, -10660, -10279, + -9896, -9512, -9127, -8740, -8351, -7962, -7571, -7180, -6787, -6393, + -5998, -5602, -5205, -4808, -4410, -4011, -3612, -3212, -2811, -2411, + -2009, -1608, -1206, -804, -402, 0 +}; diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c b/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c new file mode 100644 index 0000000..96808d3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c @@ -0,0 +1,379 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.c + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() or arm_rfft_f32() functions. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_const_structs.h" + +/* Floating-point structs */ +const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { + 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE_16_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { + 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { + 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { + 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { + 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { + 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { + 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { + 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { + 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE_4096_TABLE_LENGTH +}; + +/* Fixed-point structs */ +const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = { + 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; + +const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = { + 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; + +const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = { + 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; + +const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = { + 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; + +const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = { + 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; + +const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = { + 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; + +const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = { + 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; + +const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = { + 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; + +const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = { + 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; + +const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = { + 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; + +const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = { + 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; + +const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = { + 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; + +const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = { + 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; + +const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = { + 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; + +const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = { + 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; + +const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = { + 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; + +const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = { + 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; + +const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = { + 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; + +/* Structure for real-value inputs */ +/* Floating-point structs */ +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len32 = { + { 16, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_16_TABLE_LENGTH }, + 32U, + (float32_t *)twiddleCoef_rfft_32 +}; + +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len64 = { + { 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH }, + 64U, + (float32_t *)twiddleCoef_rfft_64 +}; + +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len128 = { + { 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH }, + 128U, + (float32_t *)twiddleCoef_rfft_128 +}; + +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len256 = { + { 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH }, + 256U, + (float32_t *)twiddleCoef_rfft_256 +}; + +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len512 = { + { 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH }, + 512U, + (float32_t *)twiddleCoef_rfft_512 +}; + +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len1024 = { + { 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH }, + 1024U, + (float32_t *)twiddleCoef_rfft_1024 +}; + +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len2048 = { + { 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH }, + 2048U, + (float32_t *)twiddleCoef_rfft_2048 +}; + +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len4096 = { + { 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH }, + 4096U, + (float32_t *)twiddleCoef_rfft_4096 +}; + +/* Fixed-point structs */ +/* q31_t */ +extern const q31_t realCoefAQ31[8192]; +extern const q31_t realCoefBQ31[8192]; + +const arm_rfft_instance_q31 arm_rfft_sR_q31_len32 = { + 32U, + 0, + 1, + 256U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len16 +}; + +const arm_rfft_instance_q31 arm_rfft_sR_q31_len64 = { + 64U, + 0, + 1, + 128U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len32 +}; + +const arm_rfft_instance_q31 arm_rfft_sR_q31_len128 = { + 128U, + 0, + 1, + 64U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len64 +}; + +const arm_rfft_instance_q31 arm_rfft_sR_q31_len256 = { + 256U, + 0, + 1, + 32U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len128 +}; + +const arm_rfft_instance_q31 arm_rfft_sR_q31_len512 = { + 512U, + 0, + 1, + 16U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len256 +}; + +const arm_rfft_instance_q31 arm_rfft_sR_q31_len1024 = { + 1024U, + 0, + 1, + 8U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len512 +}; + +const arm_rfft_instance_q31 arm_rfft_sR_q31_len2048 = { + 2048U, + 0, + 1, + 4U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len1024 +}; + +const arm_rfft_instance_q31 arm_rfft_sR_q31_len4096 = { + 4096U, + 0, + 1, + 2U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len2048 +}; + +const arm_rfft_instance_q31 arm_rfft_sR_q31_len8192 = { + 8192U, + 0, + 1, + 1U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len4096 +}; + +/* q15_t */ +extern const q15_t realCoefAQ15[8192]; +extern const q15_t realCoefBQ15[8192]; + +const arm_rfft_instance_q15 arm_rfft_sR_q15_len32 = { + 32U, + 0, + 1, + 256U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len16 +}; + +const arm_rfft_instance_q15 arm_rfft_sR_q15_len64 = { + 64U, + 0, + 1, + 128U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len32 +}; + +const arm_rfft_instance_q15 arm_rfft_sR_q15_len128 = { + 128U, + 0, + 1, + 64U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len64 +}; + +const arm_rfft_instance_q15 arm_rfft_sR_q15_len256 = { + 256U, + 0, + 1, + 32U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len128 +}; + +const arm_rfft_instance_q15 arm_rfft_sR_q15_len512 = { + 512U, + 0, + 1, + 16U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len256 +}; + +const arm_rfft_instance_q15 arm_rfft_sR_q15_len1024 = { + 1024U, + 0, + 1, + 8U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len512 +}; + +const arm_rfft_instance_q15 arm_rfft_sR_q15_len2048 = { + 2048U, + 0, + 1, + 4U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len1024 +}; + +const arm_rfft_instance_q15 arm_rfft_sR_q15_len4096 = { + 4096U, + 0, + 1, + 2U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len2048 +}; + +const arm_rfft_instance_q15 arm_rfft_sR_q15_len8192 = { + 8192U, + 0, + 1, + 1U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len4096 +}; diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c new file mode 100644 index 0000000..29e74bc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_f32.c + * Description: Floating-point complex conjugate + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" + +/** + * @ingroup groupCmplxMath + */ + +/** + * @defgroup cmplx_conj Complex Conjugate + * + * Conjugates the elements of a complex data vector. + * + * The pSrc points to the source data and + * pDst points to the where the result should be written. + * numSamples specifies the number of complex samples + * and the data in each array is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * Each array has a total of 2*numSamples values. + * The underlying algorithm is used: + * + * 
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief  Floating-point complex conjugate.
+ * @param  *pSrc points to the input vector
+ * @param  *pDst points to the output vector
+ * @param  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t inR1, inR2, inR3, inR4;
+  float32_t inI1, inI2, inI3, inI4;
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* read real input samples */
+    inR1 = pSrc[0];
+    /* store real samples to destination */
+    pDst[0] = inR1;
+    inR2 = pSrc[2];
+    pDst[2] = inR2;
+    inR3 = pSrc[4];
+    pDst[4] = inR3;
+    inR4 = pSrc[6];
+    pDst[6] = inR4;
+
+    /* read imaginary input samples */
+    inI1 = pSrc[1];
+    inI2 = pSrc[3];
+
+    /* conjugate input */
+    inI1 = -inI1;
+
+    /* read imaginary input samples */
+    inI3 = pSrc[5];
+
+    /* conjugate input */
+    inI2 = -inI2;
+
+    /* read imaginary input samples */
+    inI4 = pSrc[7];
+
+    /* conjugate input */
+    inI3 = -inI3;
+
+    /* store imaginary samples to destination */
+    pDst[1] = inI1;
+    pDst[3] = inI2;
+
+    /* conjugate input */
+    inI4 = -inI4;
+
+    /* store imaginary samples to destination */
+    pDst[5] = inI3;
+
+    /* increment source pointer by 8 to process next sampels */
+    pSrc += 8U;
+
+    /* store imaginary sample to destination */
+    pDst[7] = inI4;
+
+    /* increment destination pointer by 8 to store next samples */
+    pDst += 8U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* realOut + j (imagOut) = realIn + j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
new file mode 100644
index 0000000..1e371bd
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_conj_q15.c
+ * Description:  Q15 complex conjugate
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief  Q15 complex conjugate.
+ * @param  *pSrc points to the input vector
+ * @param  *pDst points to the output vector
+ * @param  numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in1, in2, in3, in4;
+  q31_t zero = 0;
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    in1 = *__SIMD32(pSrc)++;
+    in2 = *__SIMD32(pSrc)++;
+    in3 = *__SIMD32(pSrc)++;
+    in4 = *__SIMD32(pSrc)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    in1 = __QASX(zero, in1);
+    in2 = __QASX(zero, in2);
+    in3 = __QASX(zero, in3);
+    in4 = __QASX(zero, in4);
+
+#else
+
+    in1 = __QSAX(zero, in1);
+    in2 = __QSAX(zero, in2);
+    in3 = __QSAX(zero, in3);
+    in4 = __QSAX(zero, in4);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+    in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);
+    in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);
+    in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);
+    in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);
+
+    *__SIMD32(pDst)++ = in1;
+    *__SIMD32(pDst)++ = in2;
+    *__SIMD32(pDst)++ = in3;
+    *__SIMD32(pDst)++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  q15_t in;
+
+  /* Run the below code for Cortex-M0 */
+
+  while (numSamples > 0U)
+  {
+    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
new file mode 100644
index 0000000..af14414
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_conj_q31.c
+ * Description:  Q31 complex conjugate
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief  Q31 complex conjugate.
+ * @param  *pSrc points to the input vector
+ * @param  *pDst points to the output vector
+ * @param  numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in;                                      /* Input value */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t inR1, inR2, inR3, inR4;                  /* Temporary real variables */
+  q31_t inI1, inI2, inI3, inI4;                  /* Temporary imaginary variables */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    /* read real input sample */
+    inR1 = pSrc[0];
+    /* store real input sample */
+    pDst[0] = inR1;
+
+    /* read imaginary input sample */
+    inI1 = pSrc[1];
+
+    /* read real input sample */
+    inR2 = pSrc[2];
+    /* store real input sample */
+    pDst[2] = inR2;
+
+    /* read imaginary input sample */
+    inI2 = pSrc[3];
+
+    /* negate imaginary input sample */
+    inI1 = __QSUB(0, inI1);
+
+    /* read real input sample */
+    inR3 = pSrc[4];
+    /* store real input sample */
+    pDst[4] = inR3;
+
+    /* read imaginary input sample */
+    inI3 = pSrc[5];
+
+    /* negate imaginary input sample */
+    inI2 = __QSUB(0, inI2);
+
+    /* read real input sample */
+    inR4 = pSrc[6];
+    /* store real input sample */
+    pDst[6] = inR4;
+
+    /* negate imaginary input sample */
+    inI3 = __QSUB(0, inI3);
+
+    /* store imaginary input sample */
+    inI4 = pSrc[7];
+
+    /* store imaginary input samples */
+    pDst[1] = inI1;
+
+    /* negate imaginary input sample */
+    inI4 = __QSUB(0, inI4);
+
+    /* store imaginary input samples */
+    pDst[3] = inI2;
+
+    /* increment source pointer by 8 to proecess next samples */
+    pSrc += 8U;
+
+    /* store imaginary input samples */
+    pDst[5] = inI3;
+    pDst[7] = inI4;
+
+    /* increment destination pointer by 8 to process next samples */
+    pDst += 8U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
new file mode 100644
index 0000000..aac177f
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
@@ -0,0 +1,191 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_dot_prod_f32.c
+ * Description:  Floating-point complex dot product
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_dot_prod Complex Dot Product
+ *
+ * Computes the dot product of two complex vectors.
+ * The vectors are multiplied element-by-element and then summed.
+ *
+ * The pSrcA points to the first complex input vector and
+ * pSrcB points to the second complex input vector.
+ * numSamples specifies the number of complex samples
+ * and the data in each array is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * Each array has a total of 2*numSamples values.
+ *
+ * The underlying algorithm is used:
+ * 
+ * realResult=0;
+ * imagResult=0;
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief  Floating-point complex dot product
+ * @param  *pSrcA points to the first input vector
+ * @param  *pSrcB points to the second input vector
+ * @param  numSamples number of complex samples in each vector
+ * @param  *realResult real part of the result returned here
+ * @param  *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult)
+{
+  float32_t real_sum = 0.0f, imag_sum = 0.0f;    /* Temporary result storage */
+  float32_t a0,b0,c0,d0;
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples & 0x3U;
+
+  while (blkCnt > 0U)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (numSamples > 0U)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+
+      /* Decrement the loop counter */
+      numSamples--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  /* Store the real and imaginary results in the destination buffers */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
new file mode 100644
index 0000000..efe72a2
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_dot_prod_q15.c
+ * Description:  Processing function for the Q15 Complex Dot product
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief  Q15 complex dot product
+ * @param  *pSrcA points to the first input vector
+ * @param  *pSrcB points to the second input vector
+ * @param  numSamples number of complex samples in each vector
+ * @param  *realResult real part of the result returned here
+ * @param  *imagResult imaginary part of the result returned here
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.
+ * These are accumulated in a 64-bit accumulator with 34.30 precision.
+ * As a final step, the accumulators are converted to 8.24 format.
+ * The return results realResult and imagResult are in 8.24 format.
+ */
+
+void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+  q15_t a0,b0,c0,d0;
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += (q31_t)a0 * c0;
+      imag_sum += (q31_t)a0 * d0;
+      real_sum -= (q31_t)b0 * d0;
+      imag_sum += (q31_t)b0 * c0;
+
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += (q31_t)a0 * c0;
+      imag_sum += (q31_t)a0 * d0;
+      real_sum -= (q31_t)b0 * d0;
+      imag_sum += (q31_t)b0 * c0;
+
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += (q31_t)a0 * c0;
+      imag_sum += (q31_t)a0 * d0;
+      real_sum -= (q31_t)b0 * d0;
+      imag_sum += (q31_t)b0 * c0;
+
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += (q31_t)a0 * c0;
+      imag_sum += (q31_t)a0 * d0;
+      real_sum -= (q31_t)b0 * d0;
+      imag_sum += (q31_t)b0 * c0;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += (q31_t)a0 * c0;
+      imag_sum += (q31_t)a0 * d0;
+      real_sum -= (q31_t)b0 * d0;
+      imag_sum += (q31_t)b0 * c0;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (numSamples > 0U)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += a0 * c0;
+      imag_sum += a0 * d0;
+      real_sum -= b0 * d0;
+      imag_sum += b0 * c0;
+
+
+      /* Decrement the loop counter */
+      numSamples--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  /* Store the real and imaginary results in 8.24 format  */
+  /* Convert real data in 34.30 to 8.24 by 6 right shifts */
+  *realResult = (q31_t) (real_sum >> 6);
+  /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
+  *imagResult = (q31_t) (imag_sum >> 6);
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
new file mode 100644
index 0000000..dfd3a4b
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
@@ -0,0 +1,175 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_dot_prod_q31.c
+ * Description:  Q31 complex dot product
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief  Q31 complex dot product
+ * @param  *pSrcA points to the first input vector
+ * @param  *pSrcB points to the second input vector
+ * @param  numSamples number of complex samples in each vector
+ * @param  *realResult real part of the result returned here
+ * @param  *imagResult imaginary part of the result returned here
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.
+ * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.
+ * Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768.
+ * The return results realResult and imagResult are in 16.48 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+  q31_t a0,b0,c0,d0;
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+  /* If the numSamples  is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (numSamples > 0U)
+  {
+      a0 = *pSrcA++;
+      b0 = *pSrcA++;
+      c0 = *pSrcB++;
+      d0 = *pSrcB++;
+
+      real_sum += ((q63_t)a0 * c0) >> 14;
+      imag_sum += ((q63_t)a0 * d0) >> 14;
+      real_sum -= ((q63_t)b0 * d0) >> 14;
+      imag_sum += ((q63_t)b0 * c0) >> 14;
+
+      /* Decrement the loop counter */
+      numSamples--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  /* Store the real and imaginary results in 16.48 format  */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
new file mode 100644
index 0000000..6c8be8f
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mag_f32.c
+ * Description:  Floating-point complex magnitude
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_mag Complex Magnitude
+ *
+ * Computes the magnitude of the elements of a complex data vector.
+ *
+ * The pSrc points to the source data and
+ * pDst points to the where the result should be written.
+ * numSamples specifies the number of complex samples
+ * in the input array and the data is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The input array has a total of 2*numSamples values;
+ * the output array has a total of numSamples values.
+ * The underlying algorithm is used:
+ *
+ * 
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+/**
+ * @brief Floating-point complex magnitude.
+ * @param[in]       *pSrc points to complex input buffer
+ * @param[out]      *pDst points to real output buffer
+ * @param[in]       numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ */
+
+
+void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t realIn, imagIn;                      /* Temporary variables to hold input values */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (numSamples > 0U)
+  {
+    /* out = sqrt((real * real) + (imag * imag)) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
new file mode 100644
index 0000000..445c996
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mag_q15.c
+ * Description:  Q15 complex magnitude
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+
+
+/**
+ * @brief  Q15 complex magnitude
+ * @param  *pSrc points to the complex input vector
+ * @param  *pDst points to the real output vector
+ * @param  numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.
+ */
+
+void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in1, in2, in3, in4;
+  q31_t acc2, acc3;
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    in2 = *__SIMD32(pSrc)++;
+    in3 = *__SIMD32(pSrc)++;
+    in4 = *__SIMD32(pSrc)++;
+
+    acc0 = __SMUAD(in1, in1);
+    acc1 = __SMUAD(in2, in2);
+    acc2 = __SMUAD(in3, in3);
+    acc3 = __SMUAD(in4, in4);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);
+    arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);
+    arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);
+    arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    acc0 = __SMUAD(in1, in1);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t real, imag;                              /* Temporary variables to hold input values */
+
+  while (numSamples > 0U)
+  {
+    /* out = sqrt(real * real + imag * imag) */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
new file mode 100644
index 0000000..c1fdfdf
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
@@ -0,0 +1,173 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mag_q31.c
+ * Description:  Q31 complex magnitude
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+
+/**
+ * @brief  Q31 complex magnitude
+ * @param  *pSrc points to the complex input vector
+ * @param  *pDst points to the real output vector
+ * @param  numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to hold input values */
+  q31_t acc0, acc1;                              /* Accumulators */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t real1, real2, imag1, imag2;              /* Temporary variables to hold input values */
+  q31_t out1, out2, out3, out4;                  /* Accumulators */
+  q63_t mul1, mul2, mul3, mul4;                  /* Temporary variables */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* read complex input from source buffer */
+    real1 = pSrc[0];
+    imag1 = pSrc[1];
+    real2 = pSrc[2];
+    imag2 = pSrc[3];
+
+    /* calculate power of input values */
+    mul1 = (q63_t) real1 *real1;
+    mul2 = (q63_t) imag1 *imag1;
+    mul3 = (q63_t) real2 *real2;
+    mul4 = (q63_t) imag2 *imag2;
+
+    /* get the result to 3.29 format */
+    out1 = (q31_t) (mul1 >> 33);
+    out2 = (q31_t) (mul2 >> 33);
+    out3 = (q31_t) (mul3 >> 33);
+    out4 = (q31_t) (mul4 >> 33);
+
+    /* add real and imaginary accumulators */
+    out1 = out1 + out2;
+    out3 = out3 + out4;
+
+    /* read complex input from source buffer */
+    real1 = pSrc[4];
+    imag1 = pSrc[5];
+    real2 = pSrc[6];
+    imag2 = pSrc[7];
+
+    /* calculate square root */
+    arm_sqrt_q31(out1, &pDst[0]);
+
+    /* calculate power of input values */
+    mul1 = (q63_t) real1 *real1;
+
+    /* calculate square root */
+    arm_sqrt_q31(out3, &pDst[1]);
+
+    /* calculate power of input values */
+    mul2 = (q63_t) imag1 *imag1;
+    mul3 = (q63_t) real2 *real2;
+    mul4 = (q63_t) imag2 *imag2;
+
+    /* get the result to 3.29 format */
+    out1 = (q31_t) (mul1 >> 33);
+    out2 = (q31_t) (mul2 >> 33);
+    out3 = (q31_t) (mul3 >> 33);
+    out4 = (q31_t) (mul4 >> 33);
+
+    /* add real and imaginary accumulators */
+    out1 = out1 + out2;
+    out3 = out3 + out4;
+
+    /* calculate square root */
+    arm_sqrt_q31(out1, &pDst[2]);
+
+    /* increment destination by 8 to process next samples */
+    pSrc += 8U;
+
+    /* calculate square root */
+    arm_sqrt_q31(out3, &pDst[3]);
+
+    /* increment destination by 4 to process next samples */
+    pDst += 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
new file mode 100644
index 0000000..a7a34a3
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mag_squared_f32.c
+ * Description:  Floating-point complex magnitude squared
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_mag_squared Complex Magnitude Squared
+ *
+ * Computes the magnitude squared of the elements of a complex data vector.
+ *
+ * The pSrc points to the source data and
+ * pDst points to the where the result should be written.
+ * numSamples specifies the number of complex samples
+ * in the input array and the data is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The input array has a total of 2*numSamples values;
+ * the output array has a total of numSamples values.
+ *
+ * The underlying algorithm is used:
+ *
+ * 
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+
+/**
+ * @brief  Floating-point complex magnitude squared
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t real, imag;                          /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+  float32_t real1, real2, real3, real4;          /* Temporary variables to hold real values */
+  float32_t imag1, imag2, imag3, imag4;          /* Temporary variables to hold imaginary values */
+  float32_t mul1, mul2, mul3, mul4;              /* Temporary variables */
+  float32_t mul5, mul6, mul7, mul8;              /* Temporary variables */
+  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output values */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    /* read real input sample from source buffer */
+    real1 = pSrc[0];
+    /* read imaginary input sample from source buffer */
+    imag1 = pSrc[1];
+
+    /* calculate power of real value */
+    mul1 = real1 * real1;
+
+    /* read real input sample from source buffer */
+    real2 = pSrc[2];
+
+    /* calculate power of imaginary value */
+    mul2 = imag1 * imag1;
+
+    /* read imaginary input sample from source buffer */
+    imag2 = pSrc[3];
+
+    /* calculate power of real value */
+    mul3 = real2 * real2;
+
+    /* read real input sample from source buffer */
+    real3 = pSrc[4];
+
+    /* calculate power of imaginary value */
+    mul4 = imag2 * imag2;
+
+    /* read imaginary input sample from source buffer */
+    imag3 = pSrc[5];
+
+    /* calculate power of real value */
+    mul5 = real3 * real3;
+    /* calculate power of imaginary value */
+    mul6 = imag3 * imag3;
+
+    /* read real input sample from source buffer */
+    real4 = pSrc[6];
+
+    /* accumulate real and imaginary powers */
+    out1 = mul1 + mul2;
+
+    /* read imaginary input sample from source buffer */
+    imag4 = pSrc[7];
+
+    /* accumulate real and imaginary powers */
+    out2 = mul3 + mul4;
+
+    /* calculate power of real value */
+    mul7 = real4 * real4;
+    /* calculate power of imaginary value */
+    mul8 = imag4 * imag4;
+
+    /* store output to destination */
+    pDst[0] = out1;
+
+    /* accumulate real and imaginary powers */
+    out3 = mul5 + mul6;
+
+    /* store output to destination */
+    pDst[1] = out2;
+
+    /* accumulate real and imaginary powers */
+    out4 = mul7 + mul8;
+
+    /* store output to destination */
+    pDst[2] = out3;
+
+    /* increment destination pointer by 8 to process next samples */
+    pSrc += 8U;
+
+    /* store output to destination */
+    pDst[3] = out4;
+
+    /* increment destination pointer by 4 to process next samples */
+    pDst += 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    /* out = (real * real) + (imag * imag) */
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
new file mode 100644
index 0000000..7876cdc
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mag_squared_q15.c
+ * Description:  Q15 complex magnitude squared
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+/**
+ * @brief  Q15 complex magnitude squared
+ * @param  *pSrc points to the complex input vector
+ * @param  *pDst points to the real output vector
+ * @param  numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
+ */
+
+void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in1, in2, in3, in4;
+  q31_t acc2, acc3;
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    in2 = *__SIMD32(pSrc)++;
+    in3 = *__SIMD32(pSrc)++;
+    in4 = *__SIMD32(pSrc)++;
+
+    acc0 = __SMUAD(in1, in1);
+    acc1 = __SMUAD(in2, in2);
+    acc2 = __SMUAD(in3, in3);
+    acc3 = __SMUAD(in4, in4);
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (acc0 >> 17);
+    *pDst++ = (q15_t) (acc1 >> 17);
+    *pDst++ = (q15_t) (acc2 >> 17);
+    *pDst++ = (q15_t) (acc3 >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    acc0 = __SMUAD(in1, in1);
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (acc0 >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t real, imag;                              /* Temporary variables to store real and imaginary values */
+
+  while (numSamples > 0U)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
new file mode 100644
index 0000000..b9c0c0c
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mag_squared_q31.c
+ * Description:  Q31 complex magnitude squared
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+
+/**
+ * @brief  Q31 complex magnitude squared
+ * @param  *pSrc points to the complex input vector
+ * @param  *pDst points to the real output vector
+ * @param  numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to store real and imaginary values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (numSamples > 0U)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
new file mode 100644
index 0000000..90af35a
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
@@ -0,0 +1,196 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mult_cmplx_f32.c
+ * Description:  Floating-point complex-by-complex multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication
+ *
+ * Multiplies a complex vector by another complex vector and generates a complex result.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The parameter numSamples represents the number of complex
+ * samples processed.  The complex arrays have a total of 2*numSamples
+ * real values.
+ *
+ * The underlying algorithm is used:
+ *
+ * 
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+
+/**
+ * @brief  Floating-point complex-by-complex multiplication
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[out]  *pDst  points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t a1, b1, c1, d1;                      /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counters */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t a2, b2, c2, d2;                      /* Temporary variables to store real and imaginary values */
+  float32_t acc1, acc2, acc3, acc4;
+
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a1 = *pSrcA;                /* A[2 * i] */
+    c1 = *pSrcB;                /* B[2 * i] */
+
+    b1 = *(pSrcA + 1);          /* A[2 * i + 1] */
+    acc1 = a1 * c1;             /* acc1 = A[2 * i] * B[2 * i] */
+
+    a2 = *(pSrcA + 2);          /* A[2 * i + 2] */
+    acc2 = (b1 * c1);           /* acc2 = A[2 * i + 1] * B[2 * i] */
+
+    d1 = *(pSrcB + 1);          /* B[2 * i + 1] */
+    c2 = *(pSrcB + 2);          /* B[2 * i + 2] */
+    acc1 -= b1 * d1;            /* acc1 =      A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+    d2 = *(pSrcB + 3);          /* B[2 * i + 3] */
+    acc3 = a2 * c2;             /* acc3 =       A[2 * i + 2] * B[2 * i + 2] */
+
+    b2 = *(pSrcA + 3);          /* A[2 * i + 3] */
+    acc2 += (a1 * d1);          /* acc2 =      A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
+
+    a1 = *(pSrcA + 4);          /* A[2 * i + 4] */
+    acc4 = (a2 * d2);           /* acc4 =   A[2 * i + 2] * B[2 * i + 3] */
+
+    c1 = *(pSrcB + 4);          /* B[2 * i + 4] */
+    acc3 -= (b2 * d2);          /* acc3 =       A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */
+    *pDst = acc1;               /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+    b1 = *(pSrcA + 5);          /* A[2 * i + 5] */
+    acc4 += b2 * c2;            /* acc4 =   A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */
+
+    *(pDst + 1) = acc2;         /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1]  */
+    acc1 = (a1 * c1);
+
+    d1 = *(pSrcB + 5);
+    acc2 = (b1 * c1);
+
+    *(pDst + 2) = acc3;
+    *(pDst + 3) = acc4;
+
+    a2 = *(pSrcA + 6);
+    acc1 -= (b1 * d1);
+
+    c2 = *(pSrcB + 6);
+    acc2 += (a1 * d1);
+
+    b2 = *(pSrcA + 7);
+    acc3 = (a2 * c2);
+
+    d2 = *(pSrcB + 7);
+    acc4 = (b2 * c2);
+
+    *(pDst + 4) = acc1;
+    pSrcA += 8U;
+
+    acc3 -= (b2 * d2);
+    acc4 += (a2 * d2);
+
+    *(pDst + 5) = acc2;
+    pSrcB += 8U;
+
+    *(pDst + 6) = acc3;
+    *(pDst + 7) = acc4;
+
+    pDst += 8U;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a1 = *pSrcA++;
+    b1 = *pSrcA++;
+    c1 = *pSrcB++;
+    d1 = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a1 * c1) - (b1 * d1);
+    *pDst++ = (a1 * d1) + (b1 * c1);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
new file mode 100644
index 0000000..1dce470
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
@@ -0,0 +1,181 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mult_cmplx_q15.c
+ * Description:  Q15 complex-by-complex multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+/**
+ * @brief  Q15 complex-by-complex multiplication
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[out]  *pDst  points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (numSamples > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    numSamples--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
new file mode 100644
index 0000000..2eed4e8
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
@@ -0,0 +1,314 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mult_cmplx_q31.c
+ * Description:  Q31 complex-by-complex multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+
+/**
+ * @brief  Q31 complex-by-complex multiplication
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[out]  *pDst  points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counters */
+  q31_t mul1, mul2, mul3, mul4;
+  q31_t out1, out2;
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 1U;
+
+  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.
+   ** a second loop below computes the remaining 1 sample. */
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x2U;
+
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
new file mode 100644
index 0000000..6f45804
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
@@ -0,0 +1,213 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mult_real_f32.c
+ * Description:  Floating-point complex by real multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup CmplxByRealMult Complex-by-Real Multiplication
+ *
+ * Multiplies a complex vector by a real vector and generates a complex result.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The parameter numSamples represents the number of complex
+ * samples processed.  The complex arrays have a total of 2*numSamples
+ * real values while the real array has a total of numSamples
+ * real values.
+ *
+ * The underlying algorithm is used:
+ *
+ * 
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief  Floating-point complex-by-real multiplication
+ * @param[in]  *pSrcCmplx points to the complex input vector
+ * @param[in]  *pSrcReal points to the real input vector
+ * @param[out]  *pCmplxDst points to the complex output vector
+ * @param[in]  numSamples number of samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  float32_t in;                                  /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counters */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t inA1, inA2, inA3, inA4;              /* Temporary variables to hold input data */
+  float32_t inA5, inA6, inA7, inA8;              /* Temporary variables to hold input data */
+  float32_t inB1, inB2, inB3, inB4;              /* Temporary variables to hold input data */
+  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output data */
+  float32_t out5, out6, out7, out8;              /* Temporary variables to hold output data */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read input from complex input buffer */
+    inA1 = pSrcCmplx[0];
+    inA2 = pSrcCmplx[1];
+    /* read input from real input buffer */
+    inB1 = pSrcReal[0];
+
+    /* read input from complex input buffer */
+    inA3 = pSrcCmplx[2];
+
+    /* multiply complex buffer real input with real buffer input */
+    out1 = inA1 * inB1;
+
+    /* read input from complex input buffer */
+    inA4 = pSrcCmplx[3];
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out2 = inA2 * inB1;
+
+    /* read input from real input buffer */
+    inB2 = pSrcReal[1];
+    /* read input from complex input buffer */
+    inA5 = pSrcCmplx[4];
+
+    /* multiply complex buffer real input with real buffer input */
+    out3 = inA3 * inB2;
+
+    /* read input from complex input buffer */
+    inA6 = pSrcCmplx[5];
+    /* read input from real input buffer */
+    inB3 = pSrcReal[2];
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out4 = inA4 * inB2;
+
+    /* read input from complex input buffer */
+    inA7 = pSrcCmplx[6];
+
+    /* multiply complex buffer real input with real buffer input */
+    out5 = inA5 * inB3;
+
+    /* read input from complex input buffer */
+    inA8 = pSrcCmplx[7];
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out6 = inA6 * inB3;
+
+    /* read input from real input buffer */
+    inB4 = pSrcReal[3];
+
+    /* store result to destination bufer */
+    pCmplxDst[0] = out1;
+
+    /* multiply complex buffer real input with real buffer input */
+    out7 = inA7 * inB4;
+
+    /* store result to destination bufer */
+    pCmplxDst[1] = out2;
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out8 = inA8 * inB4;
+
+    /* store result to destination bufer */
+    pCmplxDst[2] = out3;
+    pCmplxDst[3] = out4;
+    pCmplxDst[4] = out5;
+
+    /* incremnet complex input buffer by 8 to process next samples */
+    pSrcCmplx += 8U;
+
+    /* store result to destination bufer */
+    pCmplxDst[5] = out6;
+
+    /* increment real input buffer by 4 to process next samples */
+    pSrcReal += 4U;
+
+    /* store result to destination bufer */
+    pCmplxDst[6] = out7;
+    pCmplxDst[7] = out8;
+
+    /* increment destination buffer by 8 to process next sampels */
+    pCmplxDst += 8U;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
new file mode 100644
index 0000000..abafc3b
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
@@ -0,0 +1,191 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mult_real_q15.c
+ * Description:  Q15 complex by real multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief  Q15 complex-by-real multiplication
+ * @param[in]  *pSrcCmplx points to the complex input vector
+ * @param[in]  *pSrcReal points to the real input vector
+ * @param[out]  *pCmplxDst points to the complex output vector
+ * @param[in]  numSamples number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q15_t in;                                      /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+  q31_t inA1, inA2;                              /* Temporary variables to hold input data */
+  q31_t inB1;                                    /* Temporary variables to hold input data */
+  q15_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */
+  q31_t mul1, mul2, mul3, mul4;                  /* Temporary variables to hold intermediate data */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read complex number both real and imaginary from complex input buffer */
+    inA1 = *__SIMD32(pSrcCmplx)++;
+    /* read two real values at a time from real input buffer */
+    inB1 = *__SIMD32(pSrcReal)++;
+    /* read complex number both real and imaginary from complex input buffer */
+    inA2 = *__SIMD32(pSrcCmplx)++;
+
+    /* multiply complex number with real numbers */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+    /* saturate the result */
+    out1 = (q15_t) __SSAT(mul1 >> 15U, 16);
+    out2 = (q15_t) __SSAT(mul2 >> 15U, 16);
+    out3 = (q15_t) __SSAT(mul3 >> 15U, 16);
+    out4 = (q15_t) __SSAT(mul4 >> 15U, 16);
+
+    /* pack real and imaginary outputs and store them to destination */
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+    inA1 = *__SIMD32(pSrcCmplx)++;
+    inB1 = *__SIMD32(pSrcReal)++;
+    inA2 = *__SIMD32(pSrcCmplx)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+    out1 = (q15_t) __SSAT(mul1 >> 15U, 16);
+    out2 = (q15_t) __SSAT(mul2 >> 15U, 16);
+    out3 = (q15_t) __SSAT(mul3 >> 15U, 16);
+    out4 = (q15_t) __SSAT(mul4 >> 15U, 16);
+
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (numSamples > 0U)
+  {
+    /* realOut = realA * realB.            */
+    /* imagOut = imagA * realB.                */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
new file mode 100644
index 0000000..aaa3ec0
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
@@ -0,0 +1,211 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mult_real_q31.c
+ * Description:  Q31 complex by real multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief  Q31 complex-by-real multiplication
+ * @param[in]  *pSrcCmplx points to the complex input vector
+ * @param[in]  *pSrcReal points to the real input vector
+ * @param[out]  *pCmplxDst points to the complex output vector
+ * @param[in]  numSamples number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q31_t inA1;                                    /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+  q31_t inA2, inA3, inA4;                        /* Temporary variables to hold input data */
+  q31_t inB1, inB2;                              /* Temporary variabels to hold input data */
+  q31_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read real input from complex input buffer */
+    inA1 = *pSrcCmplx++;
+    inA2 = *pSrcCmplx++;
+    /* read input from real input bufer */
+    inB1 = *pSrcReal++;
+    inB2 = *pSrcReal++;
+    /* read imaginary input from complex input buffer */
+    inA3 = *pSrcCmplx++;
+    inA4 = *pSrcCmplx++;
+
+    /* multiply complex input with real input */
+    out1 = ((q63_t) inA1 * inB1) >> 32;
+    out2 = ((q63_t) inA2 * inB1) >> 32;
+    out3 = ((q63_t) inA3 * inB2) >> 32;
+    out4 = ((q63_t) inA4 * inB2) >> 32;
+
+    /* sature the result */
+    out1 = __SSAT(out1, 31);
+    out2 = __SSAT(out2, 31);
+    out3 = __SSAT(out3, 31);
+    out4 = __SSAT(out4, 31);
+
+    /* get result in 1.31 format */
+    out1 = out1 << 1;
+    out2 = out2 << 1;
+    out3 = out3 << 1;
+    out4 = out4 << 1;
+
+    /* store the result to destination buffer */
+    *pCmplxDst++ = out1;
+    *pCmplxDst++ = out2;
+    *pCmplxDst++ = out3;
+    *pCmplxDst++ = out4;
+
+    /* read real input from complex input buffer */
+    inA1 = *pSrcCmplx++;
+    inA2 = *pSrcCmplx++;
+    /* read input from real input bufer */
+    inB1 = *pSrcReal++;
+    inB2 = *pSrcReal++;
+    /* read imaginary input from complex input buffer */
+    inA3 = *pSrcCmplx++;
+    inA4 = *pSrcCmplx++;
+
+    /* multiply complex input with real input */
+    out1 = ((q63_t) inA1 * inB1) >> 32;
+    out2 = ((q63_t) inA2 * inB1) >> 32;
+    out3 = ((q63_t) inA3 * inB2) >> 32;
+    out4 = ((q63_t) inA4 * inB2) >> 32;
+
+    /* sature the result */
+    out1 = __SSAT(out1, 31);
+    out2 = __SSAT(out2, 31);
+    out3 = __SSAT(out3, 31);
+    out4 = __SSAT(out4, 31);
+
+    /* get result in 1.31 format */
+    out1 = out1 << 1;
+    out2 = out2 << 1;
+    out3 = out3 << 1;
+    out4 = out4 << 1;
+
+    /* store the result to destination buffer */
+    *pCmplxDst++ = out1;
+    *pCmplxDst++ = out2;
+    *pCmplxDst++ = out3;
+    *pCmplxDst++ = out4;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read real input from complex input buffer */
+    inA1 = *pSrcCmplx++;
+    inA2 = *pSrcCmplx++;
+    /* read input from real input bufer */
+    inB1 = *pSrcReal++;
+
+    /* multiply complex input with real input */
+    out1 = ((q63_t) inA1 * inB1) >> 32;
+    out2 = ((q63_t) inA2 * inB1) >> 32;
+
+    /* sature the result */
+    out1 = __SSAT(out1, 31);
+    out2 = __SSAT(out2, 31);
+
+    /* get result in 1.31 format */
+    out1 = out1 << 1;
+    out2 = out2 << 1;
+
+    /* store the result to destination buffer */
+    *pCmplxDst++ = out1;
+    *pCmplxDst++ = out2;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (numSamples > 0U)
+  {
+    /* realOut = realA * realB.            */
+    /* imagReal = imagA * realB.               */
+    inA1 = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c
new file mode 100644
index 0000000..e729500
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_pid_init_f32.c
+ * Description:  Floating-point PID Control initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state & 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The resetStateFlag specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: A0, A1 A2
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag)
+{
+
+  /* Derived coefficient A0 */
+  S->A0 = S->Kp + S->Ki + S->Kd;
+
+  /* Derived coefficient A1 */
+  S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if (resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3U * sizeof(float32_t));
+  }
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c
new file mode 100644
index 0000000..0f83f35
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_pid_init_q15.c
+ * Description:  Q15 PID Control initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @details
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The resetStateFlag specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: A0, A1 A2
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag)
+{
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficients and pack into A1 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+  S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
+
+#else
+
+  S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+  /* Check whether state needs reset or not */
+  if (resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3U * sizeof(q15_t));
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;                                    /*to store the sum */
+
+  /* Derived coefficient A0 */
+  temp = S->Kp + S->Ki + S->Kd;
+  S->A0 = (q15_t) __SSAT(temp, 16);
+
+  /* Derived coefficients and pack into A1 */
+  temp = -(S->Kd + S->Kd + S->Kp);
+  S->A1 = (q15_t) __SSAT(temp, 16);
+  S->A2 = S->Kd;
+
+
+
+  /* Check whether state needs reset or not */
+  if (resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3U * sizeof(q15_t));
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c
new file mode 100644
index 0000000..ce2936e
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c
@@ -0,0 +1,95 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_pid_init_q31.c
+ * Description:  Q31 PID Control initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The resetStateFlag specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: A0, A1 A2
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag)
+{
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficient A1 */
+  S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;
+
+  /* Derived coefficient A0 */
+  temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
+  S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
+
+  /* Derived coefficient A1 */
+  temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
+  S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if (resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3U * sizeof(q31_t));
+  }
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c
new file mode 100644
index 0000000..acc1709
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_pid_reset_f32.c
+ * Description:  Floating-point PID Control reset function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief  Reset function for the floating-point PID Control.
+* @param[in] *S	Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3U * sizeof(float32_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c
new file mode 100644
index 0000000..59c4416
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c
@@ -0,0 +1,52 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_pid_reset_q15.c
+ * Description:  Q15 PID Control reset function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief  Reset function for the Q15 PID Control.
+* @param[in] *S		Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S)
+{
+  /* Reset state to zero, The size will be always 3 samples */
+  memset(S->state, 0, 3U * sizeof(q15_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c
new file mode 100644
index 0000000..7112a77
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_pid_reset_q31.c
+ * Description:  Q31 PID Control reset function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief  Reset function for the Q31 PID Control.
+* @param[in] *S	Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3U * sizeof(q31_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c
new file mode 100644
index 0000000..2aff091
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_sin_cos_f32.c
+ * Description:  Sine and Cosine calculation for floating-point values
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup SinCos Sine Cosine
+ *
+ * Computes the trigonometric sine and cosine values using a combination of table lookup
+ * and linear interpolation.
+ * There are separate functions for Q31 and floating-point data types.
+ * The input to the floating-point version is in degrees while the
+ * fixed-point Q31 have a scaled input with the range
+ * [-1 0.9999] mapping to [-180 +180] degrees.
+ *
+ * The floating point function also allows values that are out of the usual range. When this happens, the function will
+ * take extra time to adjust the input value to the range of [-180 180].
+ *
+ * The result is accurate to 5 digits after the decimal point.
+ *
+ * The implementation is based on table lookup using 360 values together with linear interpolation.
+ * The steps used are:
+ *  -# Calculation of the nearest integer table index.
+ *  -# Compute the fractional portion (fract) of the input.
+ *  -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.
+ *  -# Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).
+ *  -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.
+ *  -# Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)).
+ */
+
+ /**
+ * @addtogroup SinCos
+ * @{
+ */
+
+/**
+ * @brief  Floating-point sin_cos function.
+ * @param[in]  theta    input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+void arm_sin_cos_f32(
+                      float32_t theta,
+                      float32_t * pSinVal,
+                      float32_t * pCosVal)
+{
+    float32_t fract, in;                             /* Temporary variables for input, output */
+    uint16_t indexS, indexC;                         /* Index variable */
+    float32_t f1, f2, d1, d2;                        /* Two nearest output values */
+    float32_t findex, Dn, Df, temp;
+
+    /* input x is in degrees */
+    /* Scale the input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */
+    in = theta * 0.00277777777778f;
+
+    if (in < 0.0f)
+    {
+        in = -in;
+    }
+
+    in = in - (int32_t)in;
+
+    /* Calculation of index of the table */
+    findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+    indexS = ((uint16_t)findex) & 0x1ff;
+    indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff;
+
+    /* fractional value calculation */
+    fract = findex - (float32_t) indexS;
+
+    /* Read two nearest values of input value from the cos & sin tables */
+    f1 = sinTable_f32[indexC+0];
+    f2 = sinTable_f32[indexC+1];
+    d1 = -sinTable_f32[indexS+0];
+    d2 = -sinTable_f32[indexS+1];
+
+    temp = (1.0f - fract) * f1 + fract * f2;
+
+    Dn = 0.0122718463030f; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
+    Df = f2 - f1;          // delta between the values of the functions
+
+    temp = Dn *(d1 + d2) - 2 * Df;
+    temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn);
+    temp = fract * temp + d1 * Dn;
+
+    /* Calculation of cosine value */
+    *pCosVal = fract * temp + f1;
+
+    /* Read two nearest values of input value from the cos & sin tables */
+    f1 = sinTable_f32[indexS+0];
+    f2 = sinTable_f32[indexS+1];
+    d1 = sinTable_f32[indexC+0];
+    d2 = sinTable_f32[indexC+1];
+
+    temp = (1.0f - fract) * f1 + fract * f2;
+
+    Df = f2 - f1; // delta between the values of the functions
+    temp = Dn*(d1 + d2) - 2*Df;
+    temp = fract*temp + (3*Df - (d2 + 2*d1)*Dn);
+    temp = fract*temp + d1*Dn;
+
+    /* Calculation of sine value */
+    *pSinVal = fract*temp + f1;
+
+    if (theta < 0.0f)
+    {
+        *pSinVal = -*pSinVal;
+    }
+}
+/**
+ * @} end of SinCos group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c
new file mode 100644
index 0000000..c1c33ec
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_sin_cos_q31.c
+ * Description:  Cosine & Sine calculation for Q31 values
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupController
+ */
+
+ /**
+ * @addtogroup SinCos
+ * @{
+ */
+
+/**
+ * @brief  Q31 sin_cos function.
+ * @param[in]  theta    scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ *
+ * The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].
+ *
+ */
+
+void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal)
+{
+  q31_t fract;                                 /* Temporary variables for input, output */
+  uint16_t indexS, indexC;                     /* Index variable */
+  q31_t f1, f2, d1, d2;                        /* Two nearest output values */
+  q31_t Dn, Df;
+  q63_t temp;
+
+  /* Calculate the nearest index */
+  indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT;
+  indexC = (indexS + 128) & 0x1ff;
+
+  /* Calculation of fractional value */
+  fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8;
+
+  /* Read two nearest values of input value from the cos & sin tables */
+  f1 = sinTable_q31[indexC+0];
+  f2 = sinTable_q31[indexC+1];
+  d1 = -sinTable_q31[indexS+0];
+  d2 = -sinTable_q31[indexS+1];
+
+  Dn = 0x1921FB5; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
+  Df = f2 - f1; // delta between the values of the functions
+  temp = Dn*((q63_t)d1 + d2);
+  temp = temp - ((q63_t)Df << 32);
+  temp = (q63_t)fract*(temp >> 31);
+  temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
+  temp = (q63_t)fract*(temp >> 31);
+  temp = temp + (q63_t)d1*Dn;
+  temp = (q63_t)fract*(temp >> 31);
+
+  /* Calculation of cosine value */
+  *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
+
+  /* Read two nearest values of input value from the cos & sin tables */
+  f1 = sinTable_q31[indexS+0];
+  f2 = sinTable_q31[indexS+1];
+  d1 = sinTable_q31[indexC+0];
+  d2 = sinTable_q31[indexC+1];
+
+  Df = f2 - f1; // delta between the values of the functions
+  temp = Dn*((q63_t)d1 + d2);
+  temp = temp - ((q63_t)Df << 32);
+  temp = (q63_t)fract*(temp >> 31);
+  temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
+  temp = (q63_t)fract*(temp >> 31);
+  temp = temp + (q63_t)d1*Dn;
+  temp = (q63_t)fract*(temp >> 31);
+
+  /* Calculation of sine value */
+  *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
+}
+
+/**
+ * @} end of SinCos group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c
new file mode 100644
index 0000000..44efbd5
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c
@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cos_f32.c
+ * Description:  Fast cosine calculation for floating-point values
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @defgroup cos Cosine
+ *
+ * Computes the trigonometric cosine function using a combination of table lookup
+ * and linear interpolation.  There are separate functions for
+ * Q15, Q31, and floating-point data types.
+ * The input to the floating-point version is in radians and in the range [0 2*pi) while the
+ * fixed-point Q15 and Q31 have a scaled input with the range
+ * [0 +0.9999] mapping to [0 2*pi).  The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *
+ * The implementation is based on table lookup using 256 values together with linear interpolation.
+ * The steps used are:
+ *  -# Calculation of the nearest integer table index
+ *  -# Compute the fractional portion (fract) of the table index.
+ *  -# The final result equals (1.0f-fract)*a + fract*b;
+ *
+ * where
+ * 
+ *    b=Table[index+0];
+ *    c=Table[index+1];
+ * 

+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+ * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+float32_t arm_cos_f32(
+  float32_t x)
+{
+  float32_t cosVal, fract, in;                   /* Temporary variables for input, output */
+  uint16_t index;                                /* Index variable */
+  float32_t a, b;                                /* Two nearest output values */
+  int32_t n;
+  float32_t findex;
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */
+  in = x * 0.159154943092f + 0.25f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if (in < 0.0f)
+  {
+    n--;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+  index = ((uint16_t)findex) & 0x1ff;
+
+  /* fractional value calculation */
+  fract = findex - (float32_t) index;
+
+  /* Read two nearest values of input value from the cos table */
+  a = sinTable_f32[index];
+  b = sinTable_f32[index+1];
+
+  /* Linear interpolation process */
+  cosVal = (1.0f-fract)*a + fract*b;
+
+  /* Return the output value */
+  return (cosVal);
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c
new file mode 100644
index 0000000..036c5d7
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cos_q15.c
+ * Description:  Fast cosine calculation for Q15 values
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  cos(x).
+ *
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q15_t arm_cos_q15(
+  q15_t x)
+{
+  q15_t cosVal;                                  /* Temporary variables for input, output */
+  int32_t index;                                 /* Index variables */
+  q15_t a, b;                                    /* Four nearest output values */
+  q15_t fract;                                   /* Temporary values for fractional values */
+
+  /* add 0.25 (pi/2) to read sine table */
+  x = (uint16_t)x + 0x2000;
+  if (x < 0)
+  {   /* convert negative numbers to corresponding positive ones */
+      x = (uint16_t)x + 0x8000;
+  }
+
+  /* Calculate the nearest index */
+  index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
+
+  /* Calculation of fractional value */
+  fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
+
+  /* Read two nearest values of input value from the sin table */
+  a = sinTable_q15[index];
+  b = sinTable_q15[index+1];
+
+  /* Linear interpolation process */
+  cosVal = (q31_t)(0x8000-fract)*a >> 16;
+  cosVal = (q15_t)((((q31_t)cosVal << 16) + ((q31_t)fract*b)) >> 16);
+
+  return cosVal << 1;
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c
new file mode 100644
index 0000000..105addb
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cos_q31.c
+ * Description:  Fast cosine calculation for Q31 values
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  cos(x).
+ *
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q31_t arm_cos_q31(
+  q31_t x)
+{
+  q31_t cosVal;                                  /* Temporary variables for input, output */
+  int32_t index;                                 /* Index variables */
+  q31_t a, b;                                    /* Four nearest output values */
+  q31_t fract;                                   /* Temporary values for fractional values */
+
+  /* add 0.25 (pi/2) to read sine table */
+  x = (uint32_t)x + 0x20000000;
+  if (x < 0)
+  {   /* convert negative numbers to corresponding positive ones */
+      x = (uint32_t)x + 0x80000000;
+  }
+
+  /* Calculate the nearest index */
+  index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
+
+  /* Calculation of fractional value */
+  fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
+
+  /* Read two nearest values of input value from the sin table */
+  a = sinTable_q31[index];
+  b = sinTable_q31[index+1];
+
+  /* Linear interpolation process */
+  cosVal = (q63_t)(0x80000000-fract)*a >> 32;
+  cosVal = (q31_t)((((q63_t)cosVal << 32) + ((q63_t)fract*b)) >> 32);
+
+  return cosVal << 1;
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c
new file mode 100644
index 0000000..3fb5153
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_sin_f32.c
+ * Description:  Fast sine calculation for floating-point values
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include 
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @defgroup sin Sine
+ *
+ * Computes the trigonometric sine function using a combination of table lookup
+ * and linear interpolation.  There are separate functions for
+ * Q15, Q31, and floating-point data types.
+ * The input to the floating-point version is in radians and in the range [0 2*pi) while the
+ * fixed-point Q15 and Q31 have a scaled input with the range
+ * [0 +0.9999] mapping to [0 2*pi).  The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *
+ * The implementation is based on table lookup using 256 values together with linear interpolation.
+ * The steps used are:
+ *  -# Calculation of the nearest integer table index
+ *  -# Compute the fractional portion (fract) of the table index.
+ *  -# The final result equals (1.0f-fract)*a + fract*b;
+ *
+ * where
+ * 
+ *    b=Table[index+0];
+ *    c=Table[index+1];
+ * 

+ */
+
+/**
+ * @addtogroup sin
+ * @{
+ */
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return  sin(x).
+ */
+
+float32_t arm_sin_f32(
+  float32_t x)
+{
+  float32_t sinVal, fract, in;                           /* Temporary variables for input, output */
+  uint16_t index;                                        /* Index variable */
+  float32_t a, b;                                        /* Two nearest output values */
+  int32_t n;
+  float32_t findex;
+
+  /* Special case for small negative inputs */
+  if ((x < 0.0f) && (x >= -1.9e-7f)) {
+     return x;
+  }
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+  in = x * 0.159154943092f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if (x < 0.0f)
+  {
+    n--;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+
+  index = ((uint16_t)findex) & 0x1ff;
+
+  /* fractional value calculation */
+  fract = findex - (float32_t) index;
+
+  /* Read two nearest values of input value from the sin table */
+  a = sinTable_f32[index];
+  b = sinTable_f32[index+1];
+
+  /* Linear interpolation process */
+  sinVal = (1.0f-fract)*a + fract*b;
+
+  /* Return the output value */
+  return (sinVal);
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c
new file mode 100644
index 0000000..9eecaa9
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_sin_q15.c
+ * Description:  Fast sine calculation for Q15 values
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup sin
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  sin(x).
+ *
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi).
+ */
+
+q15_t arm_sin_q15(
+  q15_t x)
+{
+  q15_t sinVal;                                  /* Temporary variables for input, output */
+  int32_t index;                                 /* Index variables */
+  q15_t a, b;                                    /* Four nearest output values */
+  q15_t fract;                                   /* Temporary values for fractional values */
+
+  /* Calculate the nearest index */
+  index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
+
+  /* Calculation of fractional value */
+  fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
+
+  /* Read two nearest values of input value from the sin table */
+  a = sinTable_q15[index];
+  b = sinTable_q15[index+1];
+
+  /* Linear interpolation process */
+  sinVal = (q31_t)(0x8000-fract)*a >> 16;
+  sinVal = (q15_t)((((q31_t)sinVal << 16) + ((q31_t)fract*b)) >> 16);
+
+  return sinVal << 1;
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c
new file mode 100644
index 0000000..2119016
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c
@@ -0,0 +1,75 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_sin_q31.c
+ * Description:  Fast sine calculation for Q31 values
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup sin
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  sin(x).
+ *
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). */
+
+q31_t arm_sin_q31(
+  q31_t x)
+{
+  q31_t sinVal;                                  /* Temporary variables for input, output */
+  int32_t index;                                 /* Index variables */
+  q31_t a, b;                                    /* Four nearest output values */
+  q31_t fract;                                   /* Temporary values for fractional values */
+
+  /* Calculate the nearest index */
+  index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
+
+  /* Calculation of fractional value */
+  fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
+
+  /* Read two nearest values of input value from the sin table */
+  a = sinTable_q31[index];
+  b = sinTable_q31[index+1];
+
+  /* Linear interpolation process */
+  sinVal = (q63_t)(0x80000000-fract)*a >> 32;
+  sinVal = (q31_t)((((q63_t)sinVal << 32) + ((q63_t)fract*b)) >> 32);
+
+  return sinVal << 1;
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c
new file mode 100644
index 0000000..83e4ddd
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_sqrt_q15.c
+ * Description:  Q15 square root function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+   * and ARM_MATH_ARGUMENT_ERROR if the input is negative.  For
+   * negative inputs, the function returns *pOut = 0.
+   */
+
+arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut)
+{
+  q15_t number, temp1, var1, signBits1, half;
+  q31_t bits_val1;
+  float32_t temp_float1;
+  union
+  {
+    q31_t fracval;
+    float32_t floatval;
+  } tempconv;
+
+  number = in;
+
+  /* If the input is a positive number then compute the signBits. */
+  if (number > 0)
+  {
+    signBits1 = __CLZ(number) - 17;
+
+    /* Shift by the number of signBits1 */
+    if ((signBits1 % 2) == 0)
+    {
+      number = number << signBits1;
+    }
+    else
+    {
+      number = number << (signBits1 - 1);
+    }
+
+    /* Calculate half value of the number */
+    half = number >> 1;
+    /* Store the number for later use */
+    temp1 = number;
+
+    /* Convert to float */
+    temp_float1 = number * 3.051757812500000e-005f;
+    /*Store as integer */
+    tempconv.floatval = temp_float1;
+    bits_val1 = tempconv.fracval;
+    /* Subtract the shifted value from the magic number to give intial guess */
+    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  /* gives initial guess */
+    /* Store as float */
+    tempconv.fracval = bits_val1;
+    temp_float1 = tempconv.floatval;
+    /* Convert to integer format */
+    var1 = (q31_t) (temp_float1 * 16384);
+
+    /* 1st iteration */
+    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+                                     ((q15_t)
+                                      ((((q15_t)
+                                         (((q31_t) var1 * var1) >> 15)) *
+                                        (q31_t) half) >> 15))) >> 15)) << 2;
+    /* 2nd iteration */
+    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+                                     ((q15_t)
+                                      ((((q15_t)
+                                         (((q31_t) var1 * var1) >> 15)) *
+                                        (q31_t) half) >> 15))) >> 15)) << 2;
+    /* 3rd iteration */
+    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+                                     ((q15_t)
+                                      ((((q15_t)
+                                         (((q31_t) var1 * var1) >> 15)) *
+                                        (q31_t) half) >> 15))) >> 15)) << 2;
+
+    /* Multiply the inverse square root with the original value */
+    var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1;
+
+    /* Shift the output down accordingly */
+    if ((signBits1 % 2) == 0)
+    {
+      var1 = var1 >> (signBits1 / 2);
+    }
+    else
+    {
+      var1 = var1 >> ((signBits1 - 1) / 2);
+    }
+    *pOut = var1;
+
+    return (ARM_MATH_SUCCESS);
+  }
+  /* If the number is a negative number then store zero as its square root value */
+  else
+  {
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+}
+
+/**
+ * @} end of SQRT group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c
new file mode 100644
index 0000000..de8c35f
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_sqrt_q31.c
+ * Description:  Q31 square root function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief Q31 square root function.
+ * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out]  *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+ * and ARM_MATH_ARGUMENT_ERROR if the input is negative.  For
+ * negative inputs, the function returns *pOut = 0.
+ */
+
+arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut)
+{
+  q31_t number, temp1, bits_val1, var1, signBits1, half;
+  float32_t temp_float1;
+  union
+  {
+      q31_t fracval;
+      float32_t floatval;
+  } tempconv;
+
+  number = in;
+
+  /* If the input is a positive number then compute the signBits. */
+  if (number > 0)
+  {
+    signBits1 = __CLZ(number) - 1;
+
+    /* Shift by the number of signBits1 */
+    if ((signBits1 % 2) == 0)
+    {
+      number = number << signBits1;
+    }
+    else
+    {
+      number = number << (signBits1 - 1);
+    }
+
+    /* Calculate half value of the number */
+    half = number >> 1;
+    /* Store the number for later use */
+    temp1 = number;
+
+    /*Convert to float */
+    temp_float1 = number * 4.6566128731e-010f;
+    /*Store as integer */
+    tempconv.floatval = temp_float1;
+    bits_val1 = tempconv.fracval;
+    /* Subtract the shifted value from the magic number to give intial guess */
+    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  /* gives initial guess */
+    /* Store as float */
+    tempconv.fracval = bits_val1;
+    temp_float1 = tempconv.floatval;
+    /* Convert to integer format */
+    var1 = (q31_t) (temp_float1 * 1073741824);
+
+    /* 1st iteration */
+    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+                                     ((q31_t)
+                                      ((((q31_t)
+                                         (((q63_t) var1 * var1) >> 31)) *
+                                        (q63_t) half) >> 31))) >> 31)) << 2;
+    /* 2nd iteration */
+    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+                                     ((q31_t)
+                                      ((((q31_t)
+                                         (((q63_t) var1 * var1) >> 31)) *
+                                        (q63_t) half) >> 31))) >> 31)) << 2;
+    /* 3rd iteration */
+    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+                                     ((q31_t)
+                                      ((((q31_t)
+                                         (((q63_t) var1 * var1) >> 31)) *
+                                        (q63_t) half) >> 31))) >> 31)) << 2;
+
+    /* Multiply the inverse square root with the original value */
+    var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1;
+
+    /* Shift the output down accordingly */
+    if ((signBits1 % 2) == 0)
+    {
+      var1 = var1 >> (signBits1 / 2);
+    }
+    else
+    {
+      var1 = var1 >> ((signBits1 - 1) / 2);
+    }
+    *pOut = var1;
+
+    return (ARM_MATH_SUCCESS);
+  }
+  /* If the number is a negative number then store zero as its square root value */
+  else
+  {
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+}
+
+/**
+ * @} end of SQRT group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
new file mode 100644
index 0000000..8a29213
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df1_32x64_init_q31.c
+ * Description:  High precision Q31 Biquad cascade filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1_32x64
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S           	points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in]     numStages     number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs      points to the filter coefficients.
+ * @param[in]     *pState       points to the state buffer.
+ * @param[in]     postShift     Shift to be applied after the accumulator.  Varies according to the coefficients format.
+ * @return        none
+ *
+ * Coefficient and State Ordering:
+ *
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ * 
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * 

+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState points to state variables array and size of each state variable is 1.63 format.
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ * The state variables are arranged in the state array as:
+ * 
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * 

+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q63_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1_32x64 group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
new file mode 100644
index 0000000..d241f76
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
@@ -0,0 +1,549 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df1_32x64_q31.c
+ * Description:  High precision Q31 Biquad cascade filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter
+ *
+ * This function implements a high precision Biquad cascade filter which operates on
+ * Q31 data values.  The filter coefficients are in 1.31 format and the state variables
+ * are in 1.63 format.  The double precision state variables reduce quantization noise
+ * in the filter and provide a cleaner output.
+ * These filters are particularly useful when implementing filters in which the
+ * singularities are close to the unit circle.  This is common for low pass or high
+ * pass filters with very low cutoff frequencies.
+ *
+ * The function operates on blocks of input and output data
+ * and each call to the function processes blockSize samples through
+ * the filter. pSrc and pDst points to input and output arrays
+ * containing blockSize Q31 values.
+ *
+ * \par Algorithm
+ * Each Biquad stage implements a second order filter using the difference equation:
+ * 
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * 

+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ * \image html Biquad.gif "Single Biquad filter stage"
+ * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+ * Pay careful attention to the sign of the feedback coefficients.
+ * Some design tools use the difference equation
+ * 
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+ * 

+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+ *
+ * \par
+ * Higher order filters are realized as a cascade of second order sections.
+ * numStages refers to the number of second order stages used.
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+ *
+ * \par
+ * The pState points to state variables array .
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision.
+ * The state variables are arranged in the array as:
+ * 
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * 

+ *
+ * \par
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values of data in 1.63 format.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ *
+ * \par Init Function
+ * There is also an associated initialization function which performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * For example, to statically initialize the filter instance structure use
+ * 
+ *     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
+ * 

+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below.
+ * \par Fixed-Point Behavior
+ * Care must be taken while using Biquad Cascade 32x64 filter function.
+ * Following issues must be considered:
+ * - Scaling of coefficients
+ * - Filter gain
+ * - Overflow and saturation
+ *
+ * \par
+ * Filter coefficients are represented as fractional values and
+ * restricted to lie in the range [-1 +1).
+ * The processing function has an additional scaling parameter postShift
+ * which allows the filter coefficients to exceed the range [+1 -1).
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ * This essentially scales the filter coefficients by 2^postShift.
+ * For example, to realize the coefficients
+ * 
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}
+ * 

+ * set the Coefficient array to:
+ * 
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}
+ * 

+ * and set postShift=1
+ *
+ * \par
+ * The second thing to keep in mind is the gain through the filter.
+ * The frequency response of a Biquad filter is a function of its coefficients.
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+ *
+ * \par
+ * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.
+ * This is described in the function specific documentation below.
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1_32x64
+ * @{
+ */
+
+/**
+ * @details
+
+ * @param[in]  *S points to an instance of the high precision Q31 Biquad cascade filter.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to
+ * 1.31 format by discarding the low 32 bits.
+ *
+ * \par
+ * Two related functions are provided in the CMSIS DSP library.
+ * arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.
+ * arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q63_t *pState = S->pState;                     /*  state pointer initialization  */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q63_t acc;                                     /*  accumulator                   */
+  q31_t Xn1, Xn2;                                /*  Input Filter state variables        */
+  q63_t Yn1, Yn2;                                /*  Output Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+  q31_t acc_l, acc_h;                            /*  temporary output               */
+  uint32_t uShift = ((uint32_t) S->postShift + 1U);
+  uint32_t lShift = 32U - uShift;                /*  Shift to be applied to the output */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = (q31_t) (pState[0]);
+    Xn2 = (q31_t) (pState[1]);
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /* The variable acc hold output value that is being computed and
+     * stored in the destination buffer
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+     */
+
+    sample = blockSize >> 2U;
+
+    /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (sample > 0U)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut = acc_h;
+
+      /* Read the second input into Xn2, to reuse the value */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc +=  b1 * x[n-1] */
+      acc = (q63_t) Xn *b1;
+
+      /* acc =  b0 * x[n] */
+      acc += (q63_t) Xn2 *b0;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn1 *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Read the third input into Xn1, to reuse the value */
+      Xn1 = *pIn++;
+
+      /* The result is converted to 1.31 */
+      /* Store the output in the destination buffer. */
+      *(pOut + 1U) = acc_h;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn1 *b0;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn2 *b1;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *(pOut + 2U) = acc_h;
+
+      /* Read the fourth input into Xn, to reuse the value */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *(pOut + 3U) = acc_h;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* update output pointer */
+      pOut += 4U;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3U);
+
+    while (sample > 0U)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = acc_h;
+      /* Yn1 = acc << shift; */
+
+      /* Store the output in the destination buffer in 1.31 format. */
+/*      *pOut++ = (q31_t) (acc >> (32 - shift));  */
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = (q63_t) Xn1;
+    *pState++ = (q63_t) Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while (--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* The variable acc hold output value that is being computed and
+     * stored in the destination buffer
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+     */
+
+    sample = blockSize;
+
+    while (sample > 0U)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = acc_h;
+
+      /* Yn1 = acc << shift; */
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      /* *pOut++ = (q31_t) (acc >> (32 - shift)); */
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = (q63_t) Xn1;
+    *pState++ = (q63_t) Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while (--stage);
+
+#endif /*    #if defined (ARM_MATH_DSP)     */
+}
+
+  /**
+   * @} end of BiquadCascadeDF1_32x64 group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
new file mode 100644
index 0000000..658e395
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
@@ -0,0 +1,412 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df1_f32.c
+ * Description:  Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure
+ *
+ * This set of functions implements arbitrary order recursive (IIR) filters.
+ * The filters are implemented as a cascade of second order Biquad sections.
+ * The functions support Q15, Q31 and floating-point data types.
+ * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.
+ *
+ * The functions operate on blocks of input and output data and each call to the function
+ * processes blockSize samples through the filter.
+ * pSrc points to the array of input data and
+ * pDst points to the array of output data.
+ * Both arrays contain blockSize values.
+ *
+ * \par Algorithm
+ * Each Biquad stage implements a second order filter using the difference equation:
+ * 
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * 

+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ * \image html Biquad.gif "Single Biquad filter stage"
+ * Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+ * Pay careful attention to the sign of the feedback coefficients.
+ * Some design tools use the difference equation
+ * 
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+ * 

+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+ *
+ * \par
+ * Higher order filters are realized as a cascade of second order sections.
+ * numStages refers to the number of second order stages used.
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+ *
+ * \par
+ * The pState points to state variables array.
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ * The state variables are arranged in the pState array as:
+ * 
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * 

+ *
+ * \par
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values.
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Init Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * 
+ *     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
+ *     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
+ *     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
+ * 

+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.
+ * Following issues must be considered:
+ * - Scaling of coefficients
+ * - Filter gain
+ * - Overflow and saturation
+ *
+ * \par
+ * Scaling of coefficients: 
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range [-1 +1).
+ * The fixed-point functions have an additional scaling parameter postShift
+ * which allow the filter coefficients to exceed the range [+1 -1).
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ * This essentially scales the filter coefficients by 2^postShift.
+ * For example, to realize the coefficients
+ * 
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}
+ * 

+ * set the pCoeffs array to:
+ * 
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}
+ * 

+ * and set postShift=1
+ *
+ * \par
+ * Filter gain: 
+ * The frequency response of a Biquad filter is a function of its coefficients.
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+ *
+ * \par
+ * Overflow and saturation: 
+ * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+ * @param[in]  *pSrc      points to the block of input data.
+ * @param[out] *pDst      points to the block of output data.
+ * @param[in]  blockSize  number of samples to process per call.
+ * @return     none.
+ *
+ */
+
+void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /*  source pointer            */
+  float32_t *pOut = pDst;                        /*  destination pointer       */
+  float32_t *pState = S->pState;                 /*  pState pointer            */
+  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+  float32_t acc;                                 /*  Simulates the accumulator */
+  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+  float32_t Xn1, Xn2, Yn1, Yn2;                  /*  Filter pState variables   */
+  float32_t Xn;                                  /*  temporary input           */
+  uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:
+     *
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]
+     */
+
+    sample = blockSize >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (sample > 0U)
+    {
+      /* Read the first input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the third input */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as: */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    sample = blockSize & 0x3U;
+
+    while (sample > 0U)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while (stage > 0U);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]
+     */
+
+    sample = blockSize;
+
+    while (sample > 0U)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while (stage > 0U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+
+  /**
+   * @} end of BiquadCascadeDF1 group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
new file mode 100644
index 0000000..2a08968
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
@@ -0,0 +1,273 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df1_fast_q15.c
+ * Description:  Fast processing function for the Q15 Biquad cascade filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in]  blockSize number of samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).
+ * The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.
+ *
+ * \par
+ * Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure.
+ *
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q31_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (int32_t) (15 - S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = S->numStages;         /*  Stage loop counter                           */
+
+
+
+  do
+  {
+
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = *__SIMD32(pState)++;
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = *__SIMD32(pState)--;
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:
+     *
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+     */
+    sample = blockSize >> 1U;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.
+     ** a second loop below computes the remaining 1 sample. */
+    while (sample > 0U)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+      /* acc =  b1 * x[n-1] + acc +=  b2 * x[n-2] + out */
+      acc = __SMLAD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
+      acc = __SMLAD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc0 =  b1 * x[n-1] , acc0 +=  b2 * x[n-2] + out */
+      acc = __SMLAD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
+      acc = __SMLAD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+
+    if ((blockSize & 0x1U) != 0U)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN */
+
+      /* acc =  b1 * x[n-1], acc +=  b2 * x[n-2] + out */
+      acc = __SMLAD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
+      acc = __SMLAD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN */
+
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer.  */
+    /*  Subsequent (numStages - 1) occur in-place in the output buffer  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while (stage > 0U);
+}
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
new file mode 100644
index 0000000..5e41faa
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
@@ -0,0 +1,292 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df1_fast_q31.c
+ * Description:  Processing function for the Q31 Fast Biquad cascade DirectFormI(DF1) filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in]  *S        points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data.
+ * @param[in]  blockSize number of samples to process per call.
+ * @return     none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function
+ * arm_biquad_cascade_df1_init_q31() to initialize filter structure.
+ *
+ * \par
+ * Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.  Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure.
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t acc = 0;                                 /*  accumulator                   */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q31_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variables acc ... acc3 hold output values that are being computed:
+     *
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+     */
+
+    sample = blockSize >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (sample > 0U)
+    {
+      /* Read the input */
+      Xn = *pIn;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      /*acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);*/
+      mult_32x32_keep32_R(acc, b1, Xn1);
+      /* acc +=  b1 * x[n-1] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, b0, Xn);
+      /* acc +=  b[2] * x[n-2] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, b2, Xn2);
+      /* acc +=  a1 * y[n-1] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, a1, Yn1);
+      /* acc +=  a2 * y[n-2] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Read the second input */
+      Xn2 = *(pIn + 1U);
+
+      /* Store the output in the destination buffer. */
+      *pOut = Yn2;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      /*acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);*/
+      mult_32x32_keep32_R(acc, b0, Xn2);
+      /* acc +=  b1 * x[n-1] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, b1, Xn);
+      /* acc +=  b[2] * x[n-2] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, b2, Xn1);
+      /* acc +=  a1 * y[n-1] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, a1, Yn2);
+      /* acc +=  a2 * y[n-2] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Read the third input  */
+      Xn1 = *(pIn + 2U);
+
+      /* Store the output in the destination buffer. */
+      *(pOut + 1U) = Yn1;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      /*acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);*/
+      mult_32x32_keep32_R(acc, b0, Xn1);
+      /* acc +=  b1 * x[n-1] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, b1, Xn2);
+      /* acc +=  b[2] * x[n-2] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, b2, Xn);
+      /* acc +=  a1 * y[n-1] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, a1, Yn1);
+      /* acc +=  a2 * y[n-2] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Read the forth input */
+      Xn = *(pIn + 3U);
+
+      /* Store the output in the destination buffer. */
+      *(pOut + 2U) = Yn2;
+      pIn += 4U;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      /*acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/
+      mult_32x32_keep32_R(acc, b0, Xn);
+      /* acc +=  b1 * x[n-1] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, b1, Xn1);
+      /* acc +=  b[2] * x[n-2] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, b2, Xn2);
+      /* acc +=  a1 * y[n-1] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, a1, Yn2);
+      /* acc +=  a2 * y[n-2] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      Xn2 = Xn1;
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Xn1 = Xn     */
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *(pOut + 3U) = Yn1;
+      pOut += 4U;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3U);
+
+   while (sample > 0U)
+   {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      /*acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/
+      mult_32x32_keep32_R(acc, b0, Xn);
+      /* acc +=  b1 * x[n-1] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, b1, Xn1);
+      /* acc +=  b[2] * x[n-2] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, b2, Xn2);
+      /* acc +=  a1 * y[n-1] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, a1, Yn1);
+      /* acc +=  a2 * y[n-2] */
+      /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
+      multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+      /* The result is converted to 1.31  */
+      acc = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = acc;
+
+      /* decrement the loop counter */
+      sample--;
+   }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while (--stage);
+}
+
+/**
+  * @} end of BiquadCascadeDF1 group
+  */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
new file mode 100644
index 0000000..147c8c5
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
@@ -0,0 +1,97 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df1_init_f32.c
+ * Description:  Floating-point Biquad cascade DirectFormI(DF1) filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ * @brief  Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients array.
+ * @param[in]     *pState      points to the state array.
+ * @return        none
+ *
+ *
+ * Coefficient and State Ordering:
+ *
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ * 
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * 

+ *
+ * \par
+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState is a pointer to state array.
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ * The state variables are arranged in the pState array as:
+ * 
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * 

+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ *
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
new file mode 100644
index 0000000..dd46fb4
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df1_init_q15.c
+ * Description:  Q15 Biquad cascade DirectFormI(DF1) filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @param[in]     postShift    Shift to be applied to the accumulator result. Varies according to the coefficients format
+ * @return        none
+ *
+ * Coefficient and State Ordering:
+ *
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ * 
+ *     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
+ * 

+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on.  The pCoeffs array contains a total of 6*numStages values.
+ * The zero coefficient between b1 and b2 facilities  use of 16-bit SIMD instructions on the Cortex-M4.
+ *
+ * \par
+ * The state variables are stored in the array pState.
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ * The state variables are arranged in the pState array as:
+ * 
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * 

+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
new file mode 100644
index 0000000..10fb6bc
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df1_init_q31.c
+ * Description:  Q31 Biquad cascade DirectFormI(DF1) filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients buffer.
+ * @param[in]     *pState      points to the state buffer.
+ * @param[in]     postShift    Shift to be applied after the accumulator.  Varies according to the coefficients format
+ * @return        none
+ *
+ * Coefficient and State Ordering:
+ *
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ * 
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * 

+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState points to state variables array.
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ * The state variables are arranged in the pState array as:
+ * 
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * 

+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
new file mode 100644
index 0000000..c524756
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
@@ -0,0 +1,398 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df1_q15.c
+ * Description:  Processing function for the Q15 Biquad cascade DirectFormI(DF1) filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in]  blockSize number of samples to process per call.
+ * @return none.
+ *
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits.
+ * Finally, the result is saturated to 1.15 format.
+ *
+ * \par
+ * Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q31_t acc_l, acc_h;
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+  int32_t uShift = (32 - lShift);
+
+  do
+  {
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = *__SIMD32(pState)++;
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = *__SIMD32(pState)--;
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:
+     *
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+     */
+    sample = blockSize >> 1U;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.
+     ** a second loop below computes the remaining 1 sample. */
+    while (sample > 0U)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] +  a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      out = __SSAT(out, 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      out = __SSAT(out, 16);
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+
+    if ((blockSize & 0x1U) != 0U)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN */
+
+      /* acc =  b1 * x[n-1] + b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      out = __SSAT(out, 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN */
+
+    }
+
+    /*  The first stage goes from the input wire to the output wire.  */
+    /*  Subsequent numStages occur in-place in the output wire  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while (stage > 0U);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q15_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q15_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q15_t Xn;                                      /*  temporary input               */
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    pCoeffs++;  // skip the 0 coefficient
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+     */
+
+    sample = blockSize;
+
+    while (sample > 0U)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q31_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q31_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q31_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q31_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q15_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while (--stage);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
new file mode 100644
index 0000000..da367ec
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
@@ -0,0 +1,392 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df1_q31.c
+ * Description:  Processing function for the Q31 Biquad cascade filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter.
+ * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]  *pSrc      points to the block of input data.
+ * @param[out] *pDst      points to the block of output data.
+ * @param[in]  blockSize  number of samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to
+ * 1.31 format by discarding the low 32 bits.
+ *
+ * \par
+ * Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q63_t acc;                                     /*  accumulator                   */
+  uint32_t uShift = ((uint32_t) S->postShift + 1U);
+  uint32_t lShift = 32U - uShift;                /*  Shift to be applied to the output */
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+#if defined (ARM_MATH_DSP)
+
+  q31_t acc_l, acc_h;                            /*  temporary output variables    */
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:
+     *
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+     */
+
+    sample = blockSize >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (sample > 0U)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn2;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn1;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Read the third input  */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn1;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn2;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3U);
+
+    while (sample > 0U)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> lShift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while (--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+     */
+
+    sample = blockSize;
+
+    while (sample > 0U)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> lShift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while (--stage);
+
+#endif /*  #if defined (ARM_MATH_DSP) */
+}
+
+
+
+
+/**
+  * @} end of BiquadCascadeDF1 group
+  */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
new file mode 100644
index 0000000..3f1ce03
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
@@ -0,0 +1,590 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df2T_f32.c
+ * Description:  Processing function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+*
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+* The filters are implemented as a cascade of second order Biquad sections.
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+* Only floating-point data is supported.
+*
+* This function operate on blocks of input and output data and each call to the function
+* processes blockSize samples through the filter.
+* pSrc points to the array of input data and
+* pDst points to the array of output data.
+* Both arrays contain blockSize values.
+*
+* \par Algorithm
+* Each Biquad stage implements a second order filter using the difference equation:
+* 
+*    y[n] = b0 * x[n] + d1
+*    d1 = b1 * x[n] + a1 * y[n] + d2
+*    d2 = b2 * x[n] + a2 * y[n]
+* 

+* where d1 and d2 represent the two state values.
+*
+* \par
+* A Biquad filter using a transposed Direct Form II structure is shown below.
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+* Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.
+* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+* Pay careful attention to the sign of the feedback coefficients.
+* Some design tools flip the sign of the feedback coefficients:
+* 
+*    y[n] = b0 * x[n] + d1;
+*    d1 = b1 * x[n] - a1 * y[n] + d2;
+*    d2 = b2 * x[n] - a2 * y[n];
+* 

+* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+*
+* \par
+* Higher order filters are realized as a cascade of second order sections.
+* numStages refers to the number of second order stages used.
+* For example, an 8th order filter would be realized with numStages=4 second order stages.
+* A 9th order filter would be realized with numStages=5 second order stages with the
+* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+*
+* \par
+* pState points to the state variable array.
+* Each Biquad stage has 2 state variables d1 and d2.
+* The state variables are arranged in the pState array as:
+* 
+*     {d11, d12, d21, d22, ...}
+* 

+* where d1x refers to the state variables for the first Biquad and
+* d2x refers to the state variables for the second Biquad.
+* The state array has a total length of 2*numStages values.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+*
+* \par
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+* That is why the Direct Form I structure supports Q15 and Q31 data types.
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+*
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+*
+* \par Init Functions
+* There is also an associated initialization function.
+* The initialization function performs following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* For example, to statically initialize the instance structure use
+* 
+*     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+* 

+* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.
+* pCoeffs is the address of the coefficient buffer;
+*
+*/
+
+/**
+* @addtogroup BiquadCascadeDF2T
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+* @param[in]  *S        points to an instance of the filter data structure.
+* @param[in]  *pSrc     points to the block of input data.
+* @param[out] *pDst     points to the block of output data
+* @param[in]  blockSize number of samples to process.
+* @return none.
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_df2T_f32(
+const arm_biquad_cascade_df2T_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+
+   float32_t *pIn = pSrc;                         /*  source pointer            */
+   float32_t *pOut = pDst;                        /*  destination pointer       */
+   float32_t *pState = S->pState;                 /*  State pointer             */
+   float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+   float32_t acc1;                                /*  accumulator               */
+   float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+   float32_t Xn1;                                 /*  temporary input           */
+   float32_t d1, d2;                              /*  state variables           */
+   uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+#if defined(ARM_MATH_CM7)
+
+   float32_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8;   /*  Input State variables     */
+   float32_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
+   float32_t acc2, acc3, acc4, acc5, acc6, acc7;  /*  Simulates the accumulator */
+   float32_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
+
+   do
+   {
+      /* Reading the coefficients */
+      b0 = pCoeffs[0];
+      b1 = pCoeffs[1];
+      b2 = pCoeffs[2];
+      a1 = pCoeffs[3];
+      /* Apply loop unrolling and compute 16 output values simultaneously. */
+      sample = blockSize >> 4U;
+      a2 = pCoeffs[4];
+
+      /*Reading the state values */
+      d1 = pState[0];
+      d2 = pState[1];
+
+      pCoeffs += 5U;
+
+
+      /* First part of the processing with loop unrolling.  Compute 16 outputs at a time.
+       ** a second loop below computes the remaining 1 to 15 samples. */
+      while (sample > 0U) {
+
+         /* y[n] = b0 * x[n] + d1 */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         /* d2 = b2 * x[n] + a2 * y[n] */
+
+         /* Read the first 2 inputs. 2 cycles */
+         Xn1  = pIn[0 ];
+         Xn2  = pIn[1 ];
+
+         /* Sample 1. 5 cycles */
+         Xn3  = pIn[2 ];
+         acc1 = b0 * Xn1 + d1;
+
+         Xn4  = pIn[3 ];
+         d1 = b1 * Xn1 + d2;
+
+         Xn5  = pIn[4 ];
+         d2 = b2 * Xn1;
+
+         Xn6  = pIn[5 ];
+         d1 += a1 * acc1;
+
+         Xn7  = pIn[6 ];
+         d2 += a2 * acc1;
+
+         /* Sample 2. 5 cycles */
+         Xn8  = pIn[7 ];
+         acc2 = b0 * Xn2 + d1;
+
+         Xn9  = pIn[8 ];
+         d1 = b1 * Xn2 + d2;
+
+         Xn10 = pIn[9 ];
+         d2 = b2 * Xn2;
+
+         Xn11 = pIn[10];
+         d1 += a1 * acc2;
+
+         Xn12 = pIn[11];
+         d2 += a2 * acc2;
+
+         /* Sample 3. 5 cycles */
+         Xn13 = pIn[12];
+         acc3 = b0 * Xn3 + d1;
+
+         Xn14 = pIn[13];
+         d1 = b1 * Xn3 + d2;
+
+         Xn15 = pIn[14];
+         d2 = b2 * Xn3;
+
+         Xn16 = pIn[15];
+         d1 += a1 * acc3;
+
+         pIn += 16;
+         d2 += a2 * acc3;
+
+         /* Sample 4. 5 cycles */
+         acc4 = b0 * Xn4 + d1;
+         d1 = b1 * Xn4 + d2;
+         d2 = b2 * Xn4;
+         d1 += a1 * acc4;
+         d2 += a2 * acc4;
+
+         /* Sample 5. 5 cycles */
+         acc5 = b0 * Xn5 + d1;
+         d1 = b1 * Xn5 + d2;
+         d2 = b2 * Xn5;
+         d1 += a1 * acc5;
+         d2 += a2 * acc5;
+
+         /* Sample 6. 5 cycles */
+         acc6 = b0 * Xn6 + d1;
+         d1 = b1 * Xn6 + d2;
+         d2 = b2 * Xn6;
+         d1 += a1 * acc6;
+         d2 += a2 * acc6;
+
+         /* Sample 7. 5 cycles */
+         acc7 = b0 * Xn7 + d1;
+         d1 = b1 * Xn7 + d2;
+         d2 = b2 * Xn7;
+         d1 += a1 * acc7;
+         d2 += a2 * acc7;
+
+         /* Sample 8. 5 cycles */
+         acc8 = b0 * Xn8 + d1;
+         d1 = b1 * Xn8 + d2;
+         d2 = b2 * Xn8;
+         d1 += a1 * acc8;
+         d2 += a2 * acc8;
+
+         /* Sample 9. 5 cycles */
+         acc9 = b0 * Xn9 + d1;
+         d1 = b1 * Xn9 + d2;
+         d2 = b2 * Xn9;
+         d1 += a1 * acc9;
+         d2 += a2 * acc9;
+
+         /* Sample 10. 5 cycles */
+         acc10 = b0 * Xn10 + d1;
+         d1 = b1 * Xn10 + d2;
+         d2 = b2 * Xn10;
+         d1 += a1 * acc10;
+         d2 += a2 * acc10;
+
+         /* Sample 11. 5 cycles */
+         acc11 = b0 * Xn11 + d1;
+         d1 = b1 * Xn11 + d2;
+         d2 = b2 * Xn11;
+         d1 += a1 * acc11;
+         d2 += a2 * acc11;
+
+         /* Sample 12. 5 cycles */
+         acc12 = b0 * Xn12 + d1;
+         d1 = b1 * Xn12 + d2;
+         d2 = b2 * Xn12;
+         d1 += a1 * acc12;
+         d2 += a2 * acc12;
+
+         /* Sample 13. 5 cycles */
+         acc13 = b0 * Xn13 + d1;
+         d1 = b1 * Xn13 + d2;
+         d2 = b2 * Xn13;
+
+         pOut[0 ] = acc1 ;
+         d1 += a1 * acc13;
+
+         pOut[1 ] = acc2 ;
+         d2 += a2 * acc13;
+
+         /* Sample 14. 5 cycles */
+         pOut[2 ] = acc3 ;
+         acc14 = b0 * Xn14 + d1;
+
+         pOut[3 ] = acc4 ;
+         d1 = b1 * Xn14 + d2;
+
+         pOut[4 ] = acc5 ;
+         d2 = b2 * Xn14;
+
+         pOut[5 ] = acc6 ;
+         d1 += a1 * acc14;
+
+         pOut[6 ] = acc7 ;
+         d2 += a2 * acc14;
+
+         /* Sample 15. 5 cycles */
+         pOut[7 ] = acc8 ;
+         pOut[8 ] = acc9 ;
+         acc15 = b0 * Xn15 + d1;
+
+         pOut[9 ] = acc10;
+         d1 = b1 * Xn15 + d2;
+
+         pOut[10] = acc11;
+         d2 = b2 * Xn15;
+
+         pOut[11] = acc12;
+         d1 += a1 * acc15;
+
+         pOut[12] = acc13;
+         d2 += a2 * acc15;
+
+         /* Sample 16. 5 cycles */
+         pOut[13] = acc14;
+         acc16 = b0 * Xn16 + d1;
+
+         pOut[14] = acc15;
+         d1 = b1 * Xn16 + d2;
+
+         pOut[15] = acc16;
+         d2 = b2 * Xn16;
+
+         sample--;
+         d1 += a1 * acc16;
+
+         pOut += 16;
+         d2 += a2 * acc16;
+      }
+
+      sample = blockSize & 0xFu;
+      while (sample > 0U) {
+         Xn1 = *pIn;
+         acc1 = b0 * Xn1 + d1;
+
+         pIn++;
+         d1 = b1 * Xn1 + d2;
+
+         *pOut = acc1;
+         d2 = b2 * Xn1;
+
+         pOut++;
+         d1 += a1 * acc1;
+
+         sample--;
+         d2 += a2 * acc1;
+      }
+
+      /* Store the updated state variables back into the state array */
+      pState[0] = d1;
+      /* The current stage input is given as the output to the next stage */
+      pIn = pDst;
+
+      pState[1] = d2;
+      /* decrement the loop counter */
+      stage--;
+
+      pState += 2U;
+
+      /*Reset the output working pointer */
+      pOut = pDst;
+
+   } while (stage > 0U);
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+   /* Run the below code for Cortex-M0 */
+
+   do
+   {
+      /* Reading the coefficients */
+      b0 = *pCoeffs++;
+      b1 = *pCoeffs++;
+      b2 = *pCoeffs++;
+      a1 = *pCoeffs++;
+      a2 = *pCoeffs++;
+
+      /*Reading the state values */
+      d1 = pState[0];
+      d2 = pState[1];
+
+
+      sample = blockSize;
+
+      while (sample > 0U)
+      {
+         /* Read the input */
+         Xn1 = *pIn++;
+
+         /* y[n] = b0 * x[n] + d1 */
+         acc1 = (b0 * Xn1) + d1;
+
+         /* Store the result in the accumulator in the destination buffer. */
+         *pOut++ = acc1;
+
+         /* Every time after the output is computed state should be updated. */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
+
+         /* d2 = b2 * x[n] + a2 * y[n] */
+         d2 = (b2 * Xn1) + (a2 * acc1);
+
+         /* decrement the loop counter */
+         sample--;
+      }
+
+      /* Store the updated state variables back into the state array */
+      *pState++ = d1;
+      *pState++ = d2;
+
+      /* The current stage input is given as the output to the next stage */
+      pIn = pDst;
+
+      /*Reset the output working pointer */
+      pOut = pDst;
+
+      /* decrement the loop counter */
+      stage--;
+
+   } while (stage > 0U);
+
+#else
+
+   float32_t Xn2, Xn3, Xn4;                  	  /*  Input State variables     */
+   float32_t acc2, acc3, acc4;              		  /*  accumulator               */
+
+
+   float32_t p0, p1, p2, p3, p4, A1;
+
+   /* Run the below code for Cortex-M4 and Cortex-M3 */
+   do
+   {
+      /* Reading the coefficients */
+      b0 = *pCoeffs++;
+      b1 = *pCoeffs++;
+      b2 = *pCoeffs++;
+      a1 = *pCoeffs++;
+      a2 = *pCoeffs++;
+
+
+      /*Reading the state values */
+      d1 = pState[0];
+      d2 = pState[1];
+
+      /* Apply loop unrolling and compute 4 output values simultaneously. */
+      sample = blockSize >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+      while (sample > 0U) {
+
+         /* y[n] = b0 * x[n] + d1 */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         /* d2 = b2 * x[n] + a2 * y[n] */
+
+         /* Read the four inputs */
+         Xn1 = pIn[0];
+         Xn2 = pIn[1];
+         Xn3 = pIn[2];
+         Xn4 = pIn[3];
+         pIn += 4;
+
+         p0 = b0 * Xn1;
+         p1 = b1 * Xn1;
+         acc1 = p0 + d1;
+         p0 = b0 * Xn2;
+         p3 = a1 * acc1;
+         p2 = b2 * Xn1;
+         A1 = p1 + p3;
+         p4 = a2 * acc1;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         p1 = b1 * Xn2;
+         acc2 = p0 + d1;
+         p0 = b0 * Xn3;
+         p3 = a1 * acc2;
+         p2 = b2 * Xn2;
+         A1 = p1 + p3;
+         p4 = a2 * acc2;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         p1 = b1 * Xn3;
+         acc3 = p0 + d1;
+         p0 = b0 * Xn4;
+         p3 = a1 * acc3;
+         p2 = b2 * Xn3;
+         A1 = p1 + p3;
+         p4 = a2 * acc3;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         acc4 = p0 + d1;
+         p1 = b1 * Xn4;
+         p3 = a1 * acc4;
+         p2 = b2 * Xn4;
+         A1 = p1 + p3;
+         p4 = a2 * acc4;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         pOut[0] = acc1;
+         pOut[1] = acc2;
+         pOut[2] = acc3;
+         pOut[3] = acc4;
+		 pOut += 4;
+
+         sample--;
+      }
+
+      sample = blockSize & 0x3U;
+      while (sample > 0U) {
+         Xn1 = *pIn++;
+
+         p0 = b0 * Xn1;
+         p1 = b1 * Xn1;
+         acc1 = p0 + d1;
+         p3 = a1 * acc1;
+         p2 = b2 * Xn1;
+         A1 = p1 + p3;
+         p4 = a2 * acc1;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         *pOut++ = acc1;
+
+         sample--;
+      }
+
+      /* Store the updated state variables back into the state array */
+      *pState++ = d1;
+      *pState++ = d2;
+
+      /* The current stage input is given as the output to the next stage */
+      pIn = pDst;
+
+      /*Reset the output working pointer */
+      pOut = pDst;
+
+      /* decrement the loop counter */
+      stage--;
+
+   } while (stage > 0U);
+
+#endif
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+   * @} end of BiquadCascadeDF2T group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
new file mode 100644
index 0000000..8f8a830
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
@@ -0,0 +1,590 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df2T_f64.c
+ * Description:  Processing function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+*
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+* The filters are implemented as a cascade of second order Biquad sections.
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+* Only floating-point data is supported.
+*
+* This function operate on blocks of input and output data and each call to the function
+* processes blockSize samples through the filter.
+* pSrc points to the array of input data and
+* pDst points to the array of output data.
+* Both arrays contain blockSize values.
+*
+* \par Algorithm
+* Each Biquad stage implements a second order filter using the difference equation:
+* 
+*    y[n] = b0 * x[n] + d1
+*    d1 = b1 * x[n] + a1 * y[n] + d2
+*    d2 = b2 * x[n] + a2 * y[n]
+* 

+* where d1 and d2 represent the two state values.
+*
+* \par
+* A Biquad filter using a transposed Direct Form II structure is shown below.
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+* Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.
+* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+* Pay careful attention to the sign of the feedback coefficients.
+* Some design tools flip the sign of the feedback coefficients:
+* 
+*    y[n] = b0 * x[n] + d1;
+*    d1 = b1 * x[n] - a1 * y[n] + d2;
+*    d2 = b2 * x[n] - a2 * y[n];
+* 

+* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+*
+* \par
+* Higher order filters are realized as a cascade of second order sections.
+* numStages refers to the number of second order stages used.
+* For example, an 8th order filter would be realized with numStages=4 second order stages.
+* A 9th order filter would be realized with numStages=5 second order stages with the
+* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+*
+* \par
+* pState points to the state variable array.
+* Each Biquad stage has 2 state variables d1 and d2.
+* The state variables are arranged in the pState array as:
+* 
+*     {d11, d12, d21, d22, ...}
+* 

+* where d1x refers to the state variables for the first Biquad and
+* d2x refers to the state variables for the second Biquad.
+* The state array has a total length of 2*numStages values.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+*
+* \par
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+* That is why the Direct Form I structure supports Q15 and Q31 data types.
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+*
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+*
+* \par Init Functions
+* There is also an associated initialization function.
+* The initialization function performs following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* For example, to statically initialize the instance structure use
+* 
+*     arm_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};
+* 

+* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.
+* pCoeffs is the address of the coefficient buffer;
+*
+*/
+
+/**
+* @addtogroup BiquadCascadeDF2T
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+* @param[in]  *S        points to an instance of the filter data structure.
+* @param[in]  *pSrc     points to the block of input data.
+* @param[out] *pDst     points to the block of output data
+* @param[in]  blockSize number of samples to process.
+* @return none.
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_df2T_f64(
+const arm_biquad_cascade_df2T_instance_f64 * S,
+float64_t * pSrc,
+float64_t * pDst,
+uint32_t blockSize)
+{
+
+   float64_t *pIn = pSrc;                         /*  source pointer            */
+   float64_t *pOut = pDst;                        /*  destination pointer       */
+   float64_t *pState = S->pState;                 /*  State pointer             */
+   float64_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+   float64_t acc1;                                /*  accumulator               */
+   float64_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+   float64_t Xn1;                                 /*  temporary input           */
+   float64_t d1, d2;                              /*  state variables           */
+   uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+#if defined(ARM_MATH_CM7)
+
+   float64_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8;   /*  Input State variables     */
+   float64_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
+   float64_t acc2, acc3, acc4, acc5, acc6, acc7;  /*  Simulates the accumulator */
+   float64_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
+
+   do
+   {
+      /* Reading the coefficients */
+      b0 = pCoeffs[0];
+      b1 = pCoeffs[1];
+      b2 = pCoeffs[2];
+      a1 = pCoeffs[3];
+      /* Apply loop unrolling and compute 16 output values simultaneously. */
+      sample = blockSize >> 4U;
+      a2 = pCoeffs[4];
+
+      /*Reading the state values */
+      d1 = pState[0];
+      d2 = pState[1];
+
+      pCoeffs += 5U;
+
+
+      /* First part of the processing with loop unrolling.  Compute 16 outputs at a time.
+       ** a second loop below computes the remaining 1 to 15 samples. */
+      while (sample > 0U) {
+
+         /* y[n] = b0 * x[n] + d1 */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         /* d2 = b2 * x[n] + a2 * y[n] */
+
+         /* Read the first 2 inputs. 2 cycles */
+         Xn1  = pIn[0 ];
+         Xn2  = pIn[1 ];
+
+         /* Sample 1. 5 cycles */
+         Xn3  = pIn[2 ];
+         acc1 = b0 * Xn1 + d1;
+
+         Xn4  = pIn[3 ];
+         d1 = b1 * Xn1 + d2;
+
+         Xn5  = pIn[4 ];
+         d2 = b2 * Xn1;
+
+         Xn6  = pIn[5 ];
+         d1 += a1 * acc1;
+
+         Xn7  = pIn[6 ];
+         d2 += a2 * acc1;
+
+         /* Sample 2. 5 cycles */
+         Xn8  = pIn[7 ];
+         acc2 = b0 * Xn2 + d1;
+
+         Xn9  = pIn[8 ];
+         d1 = b1 * Xn2 + d2;
+
+         Xn10 = pIn[9 ];
+         d2 = b2 * Xn2;
+
+         Xn11 = pIn[10];
+         d1 += a1 * acc2;
+
+         Xn12 = pIn[11];
+         d2 += a2 * acc2;
+
+         /* Sample 3. 5 cycles */
+         Xn13 = pIn[12];
+         acc3 = b0 * Xn3 + d1;
+
+         Xn14 = pIn[13];
+         d1 = b1 * Xn3 + d2;
+
+         Xn15 = pIn[14];
+         d2 = b2 * Xn3;
+
+         Xn16 = pIn[15];
+         d1 += a1 * acc3;
+
+         pIn += 16;
+         d2 += a2 * acc3;
+
+         /* Sample 4. 5 cycles */
+         acc4 = b0 * Xn4 + d1;
+         d1 = b1 * Xn4 + d2;
+         d2 = b2 * Xn4;
+         d1 += a1 * acc4;
+         d2 += a2 * acc4;
+
+         /* Sample 5. 5 cycles */
+         acc5 = b0 * Xn5 + d1;
+         d1 = b1 * Xn5 + d2;
+         d2 = b2 * Xn5;
+         d1 += a1 * acc5;
+         d2 += a2 * acc5;
+
+         /* Sample 6. 5 cycles */
+         acc6 = b0 * Xn6 + d1;
+         d1 = b1 * Xn6 + d2;
+         d2 = b2 * Xn6;
+         d1 += a1 * acc6;
+         d2 += a2 * acc6;
+
+         /* Sample 7. 5 cycles */
+         acc7 = b0 * Xn7 + d1;
+         d1 = b1 * Xn7 + d2;
+         d2 = b2 * Xn7;
+         d1 += a1 * acc7;
+         d2 += a2 * acc7;
+
+         /* Sample 8. 5 cycles */
+         acc8 = b0 * Xn8 + d1;
+         d1 = b1 * Xn8 + d2;
+         d2 = b2 * Xn8;
+         d1 += a1 * acc8;
+         d2 += a2 * acc8;
+
+         /* Sample 9. 5 cycles */
+         acc9 = b0 * Xn9 + d1;
+         d1 = b1 * Xn9 + d2;
+         d2 = b2 * Xn9;
+         d1 += a1 * acc9;
+         d2 += a2 * acc9;
+
+         /* Sample 10. 5 cycles */
+         acc10 = b0 * Xn10 + d1;
+         d1 = b1 * Xn10 + d2;
+         d2 = b2 * Xn10;
+         d1 += a1 * acc10;
+         d2 += a2 * acc10;
+
+         /* Sample 11. 5 cycles */
+         acc11 = b0 * Xn11 + d1;
+         d1 = b1 * Xn11 + d2;
+         d2 = b2 * Xn11;
+         d1 += a1 * acc11;
+         d2 += a2 * acc11;
+
+         /* Sample 12. 5 cycles */
+         acc12 = b0 * Xn12 + d1;
+         d1 = b1 * Xn12 + d2;
+         d2 = b2 * Xn12;
+         d1 += a1 * acc12;
+         d2 += a2 * acc12;
+
+         /* Sample 13. 5 cycles */
+         acc13 = b0 * Xn13 + d1;
+         d1 = b1 * Xn13 + d2;
+         d2 = b2 * Xn13;
+
+         pOut[0 ] = acc1 ;
+         d1 += a1 * acc13;
+
+         pOut[1 ] = acc2 ;
+         d2 += a2 * acc13;
+
+         /* Sample 14. 5 cycles */
+         pOut[2 ] = acc3 ;
+         acc14 = b0 * Xn14 + d1;
+
+         pOut[3 ] = acc4 ;
+         d1 = b1 * Xn14 + d2;
+
+         pOut[4 ] = acc5 ;
+         d2 = b2 * Xn14;
+
+         pOut[5 ] = acc6 ;
+         d1 += a1 * acc14;
+
+         pOut[6 ] = acc7 ;
+         d2 += a2 * acc14;
+
+         /* Sample 15. 5 cycles */
+         pOut[7 ] = acc8 ;
+         pOut[8 ] = acc9 ;
+         acc15 = b0 * Xn15 + d1;
+
+         pOut[9 ] = acc10;
+         d1 = b1 * Xn15 + d2;
+
+         pOut[10] = acc11;
+         d2 = b2 * Xn15;
+
+         pOut[11] = acc12;
+         d1 += a1 * acc15;
+
+         pOut[12] = acc13;
+         d2 += a2 * acc15;
+
+         /* Sample 16. 5 cycles */
+         pOut[13] = acc14;
+         acc16 = b0 * Xn16 + d1;
+
+         pOut[14] = acc15;
+         d1 = b1 * Xn16 + d2;
+
+         pOut[15] = acc16;
+         d2 = b2 * Xn16;
+
+         sample--;
+         d1 += a1 * acc16;
+
+         pOut += 16;
+         d2 += a2 * acc16;
+      }
+
+      sample = blockSize & 0xFu;
+      while (sample > 0U) {
+         Xn1 = *pIn;
+         acc1 = b0 * Xn1 + d1;
+
+         pIn++;
+         d1 = b1 * Xn1 + d2;
+
+         *pOut = acc1;
+         d2 = b2 * Xn1;
+
+         pOut++;
+         d1 += a1 * acc1;
+
+         sample--;
+         d2 += a2 * acc1;
+      }
+
+      /* Store the updated state variables back into the state array */
+      pState[0] = d1;
+      /* The current stage input is given as the output to the next stage */
+      pIn = pDst;
+
+      pState[1] = d2;
+      /* decrement the loop counter */
+      stage--;
+
+      pState += 2U;
+
+      /*Reset the output working pointer */
+      pOut = pDst;
+
+   } while (stage > 0U);
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+   /* Run the below code for Cortex-M0 */
+
+   do
+   {
+      /* Reading the coefficients */
+      b0 = *pCoeffs++;
+      b1 = *pCoeffs++;
+      b2 = *pCoeffs++;
+      a1 = *pCoeffs++;
+      a2 = *pCoeffs++;
+
+      /*Reading the state values */
+      d1 = pState[0];
+      d2 = pState[1];
+
+
+      sample = blockSize;
+
+      while (sample > 0U)
+      {
+         /* Read the input */
+         Xn1 = *pIn++;
+
+         /* y[n] = b0 * x[n] + d1 */
+         acc1 = (b0 * Xn1) + d1;
+
+         /* Store the result in the accumulator in the destination buffer. */
+         *pOut++ = acc1;
+
+         /* Every time after the output is computed state should be updated. */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
+
+         /* d2 = b2 * x[n] + a2 * y[n] */
+         d2 = (b2 * Xn1) + (a2 * acc1);
+
+         /* decrement the loop counter */
+         sample--;
+      }
+
+      /* Store the updated state variables back into the state array */
+      *pState++ = d1;
+      *pState++ = d2;
+
+      /* The current stage input is given as the output to the next stage */
+      pIn = pDst;
+
+      /*Reset the output working pointer */
+      pOut = pDst;
+
+      /* decrement the loop counter */
+      stage--;
+
+   } while (stage > 0U);
+
+#else
+
+   float64_t Xn2, Xn3, Xn4;                  	  /*  Input State variables     */
+   float64_t acc2, acc3, acc4;              		  /*  accumulator               */
+
+
+   float64_t p0, p1, p2, p3, p4, A1;
+
+   /* Run the below code for Cortex-M4 and Cortex-M3 */
+   do
+   {
+      /* Reading the coefficients */
+      b0 = *pCoeffs++;
+      b1 = *pCoeffs++;
+      b2 = *pCoeffs++;
+      a1 = *pCoeffs++;
+      a2 = *pCoeffs++;
+
+
+      /*Reading the state values */
+      d1 = pState[0];
+      d2 = pState[1];
+
+      /* Apply loop unrolling and compute 4 output values simultaneously. */
+      sample = blockSize >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+      while (sample > 0U) {
+
+         /* y[n] = b0 * x[n] + d1 */
+         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+         /* d2 = b2 * x[n] + a2 * y[n] */
+
+         /* Read the four inputs */
+         Xn1 = pIn[0];
+         Xn2 = pIn[1];
+         Xn3 = pIn[2];
+         Xn4 = pIn[3];
+         pIn += 4;
+
+         p0 = b0 * Xn1;
+         p1 = b1 * Xn1;
+         acc1 = p0 + d1;
+         p0 = b0 * Xn2;
+         p3 = a1 * acc1;
+         p2 = b2 * Xn1;
+         A1 = p1 + p3;
+         p4 = a2 * acc1;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         p1 = b1 * Xn2;
+         acc2 = p0 + d1;
+         p0 = b0 * Xn3;
+         p3 = a1 * acc2;
+         p2 = b2 * Xn2;
+         A1 = p1 + p3;
+         p4 = a2 * acc2;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         p1 = b1 * Xn3;
+         acc3 = p0 + d1;
+         p0 = b0 * Xn4;
+         p3 = a1 * acc3;
+         p2 = b2 * Xn3;
+         A1 = p1 + p3;
+         p4 = a2 * acc3;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         acc4 = p0 + d1;
+         p1 = b1 * Xn4;
+         p3 = a1 * acc4;
+         p2 = b2 * Xn4;
+         A1 = p1 + p3;
+         p4 = a2 * acc4;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         pOut[0] = acc1;
+         pOut[1] = acc2;
+         pOut[2] = acc3;
+         pOut[3] = acc4;
+				 pOut += 4;
+
+         sample--;
+      }
+
+      sample = blockSize & 0x3U;
+      while (sample > 0U) {
+         Xn1 = *pIn++;
+
+         p0 = b0 * Xn1;
+         p1 = b1 * Xn1;
+         acc1 = p0 + d1;
+         p3 = a1 * acc1;
+         p2 = b2 * Xn1;
+         A1 = p1 + p3;
+         p4 = a2 * acc1;
+         d1 = A1 + d2;
+         d2 = p2 + p4;
+
+         *pOut++ = acc1;
+
+         sample--;
+      }
+
+      /* Store the updated state variables back into the state array */
+      *pState++ = d1;
+      *pState++ = d2;
+
+      /* The current stage input is given as the output to the next stage */
+      pIn = pDst;
+
+      /*Reset the output working pointer */
+      pOut = pDst;
+
+      /* decrement the loop counter */
+      stage--;
+
+   } while (stage > 0U);
+
+#endif
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+   * @} end of BiquadCascadeDF2T group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
new file mode 100644
index 0000000..6dfc985
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
@@ -0,0 +1,89 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df2T_init_f32.c
+ * Description:  Initialization function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF2T
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the filter data structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @return        none
+ *
+ * Coefficient and State Ordering:
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ * 
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * 

+ *
+ * \par
+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState is a pointer to state array.
+ * Each Biquad stage has 2 state variables d1, and d2.
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ * The state array has a total length of 2*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 2 * numStages */
+  memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
new file mode 100644
index 0000000..8141da5
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
@@ -0,0 +1,89 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_df2T_init_f64.c
+ * Description:  Initialization function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF2T
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the filter data structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @return        none
+ *
+ * Coefficient and State Ordering:
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ * 
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * 

+ *
+ * \par
+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState is a pointer to state array.
+ * Each Biquad stage has 2 state variables d1, and d2.
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ * The state array has a total length of 2*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 2 * numStages */
+  memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float64_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
new file mode 100644
index 0000000..36084e5
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
@@ -0,0 +1,670 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_stereo_df2T_f32.c
+ * Description:  Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+*
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+* The filters are implemented as a cascade of second order Biquad sections.
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+* Only floating-point data is supported.
+*
+* This function operate on blocks of input and output data and each call to the function
+* processes blockSize samples through the filter.
+* pSrc points to the array of input data and
+* pDst points to the array of output data.
+* Both arrays contain blockSize values.
+*
+* \par Algorithm
+* Each Biquad stage implements a second order filter using the difference equation:
+* 
+*    y[n] = b0 * x[n] + d1
+*    d1 = b1 * x[n] + a1 * y[n] + d2
+*    d2 = b2 * x[n] + a2 * y[n]
+* 

+* where d1 and d2 represent the two state values.
+*
+* \par
+* A Biquad filter using a transposed Direct Form II structure is shown below.
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+* Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.
+* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+* Pay careful attention to the sign of the feedback coefficients.
+* Some design tools flip the sign of the feedback coefficients:
+* 
+*    y[n] = b0 * x[n] + d1;
+*    d1 = b1 * x[n] - a1 * y[n] + d2;
+*    d2 = b2 * x[n] - a2 * y[n];
+* 

+* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+*
+* \par
+* Higher order filters are realized as a cascade of second order sections.
+* numStages refers to the number of second order stages used.
+* For example, an 8th order filter would be realized with numStages=4 second order stages.
+* A 9th order filter would be realized with numStages=5 second order stages with the
+* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+*
+* \par
+* pState points to the state variable array.
+* Each Biquad stage has 2 state variables d1 and d2.
+* The state variables are arranged in the pState array as:
+* 
+*     {d11, d12, d21, d22, ...}
+* 

+* where d1x refers to the state variables for the first Biquad and
+* d2x refers to the state variables for the second Biquad.
+* The state array has a total length of 2*numStages values.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+*
+* \par
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+* That is why the Direct Form I structure supports Q15 and Q31 data types.
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+*
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+*
+* \par Init Functions
+* There is also an associated initialization function.
+* The initialization function performs following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* For example, to statically initialize the instance structure use
+* 
+*     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+* 

+* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.
+* pCoeffs is the address of the coefficient buffer;
+*
+*/
+
+/**
+* @addtogroup BiquadCascadeDF2T
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+* @param[in]  *S        points to an instance of the filter data structure.
+* @param[in]  *pSrc     points to the block of input data.
+* @param[out] *pDst     points to the block of output data
+* @param[in]  blockSize number of samples to process.
+* @return none.
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_stereo_df2T_f32(
+const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+
+    float32_t *pIn = pSrc;                         /*  source pointer            */
+    float32_t *pOut = pDst;                        /*  destination pointer       */
+    float32_t *pState = S->pState;                 /*  State pointer             */
+    float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+    float32_t acc1a, acc1b;                        /*  accumulator               */
+    float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+    float32_t Xn1a, Xn1b;                          /*  temporary input           */
+    float32_t d1a, d2a, d1b, d2b;                  /*  state variables           */
+    uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+#if defined(ARM_MATH_CM7)
+
+    float32_t Xn2a, Xn3a, Xn4a, Xn5a, Xn6a, Xn7a, Xn8a;         /*  Input State variables     */
+    float32_t Xn2b, Xn3b, Xn4b, Xn5b, Xn6b, Xn7b, Xn8b;         /*  Input State variables     */
+    float32_t acc2a, acc3a, acc4a, acc5a, acc6a, acc7a, acc8a;  /*  Simulates the accumulator */
+    float32_t acc2b, acc3b, acc4b, acc5b, acc6b, acc7b, acc8b;  /*  Simulates the accumulator */
+
+    do
+    {
+        /* Reading the coefficients */
+        b0 = pCoeffs[0];
+        b1 = pCoeffs[1];
+        b2 = pCoeffs[2];
+        a1 = pCoeffs[3];
+        /* Apply loop unrolling and compute 8 output values simultaneously. */
+        sample = blockSize >> 3U;
+        a2 = pCoeffs[4];
+
+        /*Reading the state values */
+        d1a = pState[0];
+        d2a = pState[1];
+        d1b = pState[2];
+        d2b = pState[3];
+
+        pCoeffs += 5U;
+
+        /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.
+        ** a second loop below computes the remaining 1 to 7 samples. */
+        while (sample > 0U) {
+
+            /* y[n] = b0 * x[n] + d1 */
+            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+            /* d2 = b2 * x[n] + a2 * y[n] */
+
+            /* Read the first 2 inputs. 2 cycles */
+            Xn1a  = pIn[0 ];
+            Xn1b  = pIn[1 ];
+
+            /* Sample 1. 5 cycles */
+            Xn2a  = pIn[2 ];
+            acc1a = b0 * Xn1a + d1a;
+
+            Xn2b  = pIn[3 ];
+            d1a = b1 * Xn1a + d2a;
+
+            Xn3a  = pIn[4 ];
+            d2a = b2 * Xn1a;
+
+            Xn3b  = pIn[5 ];
+            d1a += a1 * acc1a;
+
+            Xn4a  = pIn[6 ];
+            d2a += a2 * acc1a;
+
+            /* Sample 2. 5 cycles */
+            Xn4b  = pIn[7 ];
+            acc1b = b0 * Xn1b + d1b;
+
+            Xn5a  = pIn[8 ];
+            d1b = b1 * Xn1b + d2b;
+
+            Xn5b = pIn[9 ];
+            d2b = b2 * Xn1b;
+
+            Xn6a = pIn[10];
+            d1b += a1 * acc1b;
+
+            Xn6b = pIn[11];
+            d2b += a2 * acc1b;
+
+            /* Sample 3. 5 cycles */
+            Xn7a = pIn[12];
+            acc2a = b0 * Xn2a + d1a;
+
+            Xn7b = pIn[13];
+            d1a = b1 * Xn2a + d2a;
+
+            Xn8a = pIn[14];
+            d2a = b2 * Xn2a;
+
+            Xn8b = pIn[15];
+            d1a += a1 * acc2a;
+
+            pIn += 16;
+            d2a += a2 * acc2a;
+
+            /* Sample 4. 5 cycles */
+            acc2b = b0 * Xn2b + d1b;
+            d1b = b1 * Xn2b + d2b;
+            d2b = b2 * Xn2b;
+            d1b += a1 * acc2b;
+            d2b += a2 * acc2b;
+
+            /* Sample 5. 5 cycles */
+            acc3a = b0 * Xn3a + d1a;
+            d1a = b1 * Xn3a + d2a;
+            d2a = b2 * Xn3a;
+            d1a += a1 * acc3a;
+            d2a += a2 * acc3a;
+
+            /* Sample 6. 5 cycles */
+            acc3b = b0 * Xn3b + d1b;
+            d1b = b1 * Xn3b + d2b;
+            d2b = b2 * Xn3b;
+            d1b += a1 * acc3b;
+            d2b += a2 * acc3b;
+
+            /* Sample 7. 5 cycles */
+            acc4a = b0 * Xn4a + d1a;
+            d1a = b1 * Xn4a + d2a;
+            d2a = b2 * Xn4a;
+            d1a += a1 * acc4a;
+            d2a += a2 * acc4a;
+
+            /* Sample 8. 5 cycles */
+            acc4b = b0 * Xn4b + d1b;
+            d1b = b1 * Xn4b + d2b;
+            d2b = b2 * Xn4b;
+            d1b += a1 * acc4b;
+            d2b += a2 * acc4b;
+
+            /* Sample 9. 5 cycles */
+            acc5a = b0 * Xn5a + d1a;
+            d1a = b1 * Xn5a + d2a;
+            d2a = b2 * Xn5a;
+            d1a += a1 * acc5a;
+            d2a += a2 * acc5a;
+
+            /* Sample 10. 5 cycles */
+            acc5b = b0 * Xn5b + d1b;
+            d1b = b1 * Xn5b + d2b;
+            d2b = b2 * Xn5b;
+            d1b += a1 * acc5b;
+            d2b += a2 * acc5b;
+
+            /* Sample 11. 5 cycles */
+            acc6a = b0 * Xn6a + d1a;
+            d1a = b1 * Xn6a + d2a;
+            d2a = b2 * Xn6a;
+            d1a += a1 * acc6a;
+            d2a += a2 * acc6a;
+
+            /* Sample 12. 5 cycles */
+            acc6b = b0 * Xn6b + d1b;
+            d1b = b1 * Xn6b + d2b;
+            d2b = b2 * Xn6b;
+            d1b += a1 * acc6b;
+            d2b += a2 * acc6b;
+
+            /* Sample 13. 5 cycles */
+            acc7a = b0 * Xn7a + d1a;
+            d1a = b1 * Xn7a + d2a;
+
+            pOut[0 ] = acc1a ;
+            d2a = b2 * Xn7a;
+
+            pOut[1 ] = acc1b ;
+            d1a += a1 * acc7a;
+
+            pOut[2 ] = acc2a ;
+            d2a += a2 * acc7a;
+
+            /* Sample 14. 5 cycles */
+            pOut[3 ] = acc2b ;
+            acc7b = b0 * Xn7b + d1b;
+
+            pOut[4 ] = acc3a ;
+            d1b = b1 * Xn7b + d2b;
+
+            pOut[5 ] = acc3b ;
+            d2b = b2 * Xn7b;
+
+            pOut[6 ] = acc4a ;
+            d1b += a1 * acc7b;
+
+            pOut[7 ] = acc4b ;
+            d2b += a2 * acc7b;
+
+            /* Sample 15. 5 cycles */
+            pOut[8 ] = acc5a ;
+            acc8a = b0 * Xn8a + d1a;
+
+            pOut[9 ] = acc5b;
+            d1a = b1 * Xn8a + d2a;
+
+            pOut[10] = acc6a;
+            d2a = b2 * Xn8a;
+
+            pOut[11] = acc6b;
+            d1a += a1 * acc8a;
+
+            pOut[12] = acc7a;
+            d2a += a2 * acc8a;
+
+            /* Sample 16. 5 cycles */
+            pOut[13] = acc7b;
+            acc8b = b0 * Xn8b + d1b;
+
+            pOut[14] = acc8a;
+            d1b = b1 * Xn8b + d2b;
+
+            pOut[15] = acc8b;
+            d2b = b2 * Xn8b;
+
+            sample--;
+            d1b += a1 * acc8b;
+
+            pOut += 16;
+            d2b += a2 * acc8b;
+        }
+
+        sample = blockSize & 0x7U;
+        while (sample > 0U) {
+            /* Read the input */
+            Xn1a = *pIn++; //Channel a
+            Xn1b = *pIn++; //Channel b
+
+            /* y[n] = b0 * x[n] + d1 */
+            acc1a = (b0 * Xn1a) + d1a;
+            acc1b = (b0 * Xn1b) + d1b;
+
+            /* Store the result in the accumulator in the destination buffer. */
+            *pOut++ = acc1a;
+            *pOut++ = acc1b;
+
+            /* Every time after the output is computed state should be updated. */
+            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+            d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+            d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+            /* d2 = b2 * x[n] + a2 * y[n] */
+            d2a = (b2 * Xn1a) + (a2 * acc1a);
+            d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+            sample--;
+        }
+
+        /* Store the updated state variables back into the state array */
+        pState[0] = d1a;
+        pState[1] = d2a;
+
+        pState[2] = d1b;
+        pState[3] = d2b;
+
+        /* The current stage input is given as the output to the next stage */
+        pIn = pDst;
+        /* decrement the loop counter */
+        stage--;
+
+        pState += 4U;
+        /*Reset the output working pointer */
+        pOut = pDst;
+
+    } while (stage > 0U);
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+    /* Run the below code for Cortex-M0 */
+
+    do
+    {
+        /* Reading the coefficients */
+        b0 = *pCoeffs++;
+        b1 = *pCoeffs++;
+        b2 = *pCoeffs++;
+        a1 = *pCoeffs++;
+        a2 = *pCoeffs++;
+
+        /*Reading the state values */
+        d1a = pState[0];
+        d2a = pState[1];
+        d1b = pState[2];
+        d2b = pState[3];
+
+
+        sample = blockSize;
+
+        while (sample > 0U)
+        {
+            /* Read the input */
+            Xn1a = *pIn++; //Channel a
+            Xn1b = *pIn++; //Channel b
+
+            /* y[n] = b0 * x[n] + d1 */
+            acc1a = (b0 * Xn1a) + d1a;
+            acc1b = (b0 * Xn1b) + d1b;
+
+            /* Store the result in the accumulator in the destination buffer. */
+            *pOut++ = acc1a;
+            *pOut++ = acc1b;
+
+            /* Every time after the output is computed state should be updated. */
+            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+            d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+            d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+            /* d2 = b2 * x[n] + a2 * y[n] */
+            d2a = (b2 * Xn1a) + (a2 * acc1a);
+            d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+            /* decrement the loop counter */
+            sample--;
+        }
+
+        /* Store the updated state variables back into the state array */
+        *pState++ = d1a;
+        *pState++ = d2a;
+        *pState++ = d1b;
+        *pState++ = d2b;
+
+        /* The current stage input is given as the output to the next stage */
+        pIn = pDst;
+
+        /*Reset the output working pointer */
+        pOut = pDst;
+
+        /* decrement the loop counter */
+        stage--;
+
+    } while (stage > 0U);
+
+#else
+
+    float32_t Xn2a, Xn3a, Xn4a;                          /*  Input State variables     */
+    float32_t Xn2b, Xn3b, Xn4b;                          /*  Input State variables     */
+    float32_t acc2a, acc3a, acc4a;                       /*  accumulator               */
+    float32_t acc2b, acc3b, acc4b;                       /*  accumulator               */
+    float32_t p0a, p1a, p2a, p3a, p4a, A1a;
+    float32_t p0b, p1b, p2b, p3b, p4b, A1b;
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    do
+    {
+        /* Reading the coefficients */
+        b0 = *pCoeffs++;
+        b1 = *pCoeffs++;
+        b2 = *pCoeffs++;
+        a1 = *pCoeffs++;
+        a2 = *pCoeffs++;
+
+        /*Reading the state values */
+        d1a = pState[0];
+        d2a = pState[1];
+        d1b = pState[2];
+        d2b = pState[3];
+
+        /* Apply loop unrolling and compute 4 output values simultaneously. */
+        sample = blockSize >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+        ** a second loop below computes the remaining 1 to 3 samples. */
+        while (sample > 0U) {
+
+            /* y[n] = b0 * x[n] + d1 */
+            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+            /* d2 = b2 * x[n] + a2 * y[n] */
+
+            /* Read the four inputs */
+            Xn1a = pIn[0];
+            Xn1b = pIn[1];
+            Xn2a = pIn[2];
+            Xn2b = pIn[3];
+            Xn3a = pIn[4];
+            Xn3b = pIn[5];
+            Xn4a = pIn[6];
+            Xn4b = pIn[7];
+            pIn += 8;
+
+            p0a = b0 * Xn1a;
+            p0b = b0 * Xn1b;
+            p1a = b1 * Xn1a;
+            p1b = b1 * Xn1b;
+            acc1a = p0a + d1a;
+            acc1b = p0b + d1b;
+            p0a = b0 * Xn2a;
+            p0b = b0 * Xn2b;
+            p3a = a1 * acc1a;
+            p3b = a1 * acc1b;
+            p2a = b2 * Xn1a;
+            p2b = b2 * Xn1b;
+            A1a = p1a + p3a;
+            A1b = p1b + p3b;
+            p4a = a2 * acc1a;
+            p4b = a2 * acc1b;
+            d1a = A1a + d2a;
+            d1b = A1b + d2b;
+            d2a = p2a + p4a;
+            d2b = p2b + p4b;
+
+            p1a = b1 * Xn2a;
+            p1b = b1 * Xn2b;
+            acc2a = p0a + d1a;
+            acc2b = p0b + d1b;
+            p0a = b0 * Xn3a;
+            p0b = b0 * Xn3b;
+            p3a = a1 * acc2a;
+            p3b = a1 * acc2b;
+            p2a = b2 * Xn2a;
+            p2b = b2 * Xn2b;
+            A1a = p1a + p3a;
+            A1b = p1b + p3b;
+            p4a = a2 * acc2a;
+            p4b = a2 * acc2b;
+            d1a = A1a + d2a;
+            d1b = A1b + d2b;
+            d2a = p2a + p4a;
+            d2b = p2b + p4b;
+
+            p1a = b1 * Xn3a;
+            p1b = b1 * Xn3b;
+            acc3a = p0a + d1a;
+            acc3b = p0b + d1b;
+            p0a = b0 * Xn4a;
+            p0b = b0 * Xn4b;
+            p3a = a1 * acc3a;
+            p3b = a1 * acc3b;
+            p2a = b2 * Xn3a;
+            p2b = b2 * Xn3b;
+            A1a = p1a + p3a;
+            A1b = p1b + p3b;
+            p4a = a2 * acc3a;
+            p4b = a2 * acc3b;
+            d1a = A1a + d2a;
+            d1b = A1b + d2b;
+            d2a = p2a + p4a;
+            d2b = p2b + p4b;
+
+            acc4a = p0a + d1a;
+            acc4b = p0b + d1b;
+            p1a = b1 * Xn4a;
+            p1b = b1 * Xn4b;
+            p3a = a1 * acc4a;
+            p3b = a1 * acc4b;
+            p2a = b2 * Xn4a;
+            p2b = b2 * Xn4b;
+            A1a = p1a + p3a;
+            A1b = p1b + p3b;
+            p4a = a2 * acc4a;
+            p4b = a2 * acc4b;
+            d1a = A1a + d2a;
+            d1b = A1b + d2b;
+            d2a = p2a + p4a;
+            d2b = p2b + p4b;
+
+            pOut[0] = acc1a;
+            pOut[1] = acc1b;
+            pOut[2] = acc2a;
+            pOut[3] = acc2b;
+            pOut[4] = acc3a;
+            pOut[5] = acc3b;
+            pOut[6] = acc4a;
+            pOut[7] = acc4b;
+            pOut += 8;
+
+            sample--;
+        }
+
+        sample = blockSize & 0x3U;
+        while (sample > 0U) {
+            Xn1a = *pIn++;
+            Xn1b = *pIn++;
+
+            p0a = b0 * Xn1a;
+            p0b = b0 * Xn1b;
+            p1a = b1 * Xn1a;
+            p1b = b1 * Xn1b;
+            acc1a = p0a + d1a;
+            acc1b = p0b + d1b;
+            p3a = a1 * acc1a;
+            p3b = a1 * acc1b;
+            p2a = b2 * Xn1a;
+            p2b = b2 * Xn1b;
+            A1a = p1a + p3a;
+            A1b = p1b + p3b;
+            p4a = a2 * acc1a;
+            p4b = a2 * acc1b;
+            d1a = A1a + d2a;
+            d1b = A1b + d2b;
+            d2a = p2a + p4a;
+            d2b = p2b + p4b;
+
+            *pOut++ = acc1a;
+            *pOut++ = acc1b;
+
+            sample--;
+        }
+
+        /* Store the updated state variables back into the state array */
+        *pState++ = d1a;
+        *pState++ = d2a;
+        *pState++ = d1b;
+        *pState++ = d2b;
+
+        /* The current stage input is given as the output to the next stage */
+        pIn = pDst;
+
+        /*Reset the output working pointer */
+        pOut = pDst;
+
+        /* decrement the loop counter */
+        stage--;
+
+    } while (stage > 0U);
+
+#endif
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+   * @} end of BiquadCascadeDF2T group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
new file mode 100644
index 0000000..b847c6e
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
@@ -0,0 +1,89 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_biquad_cascade_stereo_df2T_init_f32.c
+ * Description:  Initialization function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF2T
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the filter data structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @return        none
+ *
+ * Coefficient and State Ordering:
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ * 
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * 

+ *
+ * \par
+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState is a pointer to state array.
+ * Each Biquad stage has 2 state variables d1, and d2 for each channel.
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ * The state array has a total length of 2*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c
new file mode 100644
index 0000000..906f7ab
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c
@@ -0,0 +1,635 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_f32.c
+ * Description:  Convolution of floating-point sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup Conv Convolution
+ *
+ * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.
+ * Convolution is similar to correlation and is frequently used in filtering and data analysis.
+ * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.
+ * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.
+ *
+ * \par Algorithm
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.
+ * Then the convolution
+ *
+ * 
+ *                   c[n] = a[n] * b[n]
+ * 

+ *
+ * \par
+ * is defined as
+ * \image html ConvolutionEquation.gif
+ * \par
+ * Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2.
+ * pSrcA points to the first input vector of length srcALen and
+ * pSrcB points to the second input vector of length srcBLen.
+ * The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.
+ *
+ * \par
+ * Conceptually, when two signals a[n] and b[n] are convolved,
+ * the signal b[n] slides over a[n].
+ * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.
+ *
+ * \par
+ * Note that convolution is a commutative operation:
+ *
+ * 
+ *                   a[n] * b[n] = b[n] * a[n].
+ * 

+ *
+ * \par
+ * This means that switching the A and B arguments to the convolution functions has no effect.
+ *
+ * Fixed-Point Behavior
+ *
+ * \par
+ * Convolution requires summing up a large number of intermediate products.
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
+ * Refer to the function specific documentation below for further details of the particular algorithm used.
+ *
+ *
+ * Fast Versions
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * Opt Versions
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counters */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally
+   * divided into three stages according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first stage of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.
+   * In the third stage of the algorithm, the multiplications decrease by one
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]
+   * sum = x[0] * y[1] + x[1] * y[0]
+   * ....
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* x[1] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* x[2] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* x[3] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+  /* -------------------
+   * Stage2 process
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4 */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += x0 * c0;
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += x1 * c0;
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += x2 * c0;
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 += x3 * c0;
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px + 1U);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 += x0 * c0;
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px + 2U);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 += x1 * c0;
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px + 3U);
+        px += 4U;
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 += x2 * c0;
+
+
+      } while (--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+      *pOut++ = acc1;
+      *pOut++ = acc2;
+      *pOut++ = acc3;
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+   * ....
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+   * sum +=  x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  py = pSrc2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0U; i < ((srcALen + srcBLen) - 1U); i++)
+  {
+    /* Initialize sum with zero to carry out MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0U; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if ((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[i - j];
+      }
+    }
+    /* Store the output in the destination buffer */
+    pDst[i] = sum;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP)        */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
new file mode 100644
index 0000000..26c37f0
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
@@ -0,0 +1,531 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_fast_opt_q15.c
+ * Description:  Fast Q15 Convolution
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results
+ * but provides only a single guard bit. There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  uint32_t tapCnt;                               /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif	/*	#ifdef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* Pointer to take end of scratch2 buffer */
+  pScr2 = pScratch2 + srcBLen - 1;
+
+  /* points to smaller length sequence */
+  px = pIn2;
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcBLen >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+
+  /* Copy smaller length input sequence in reverse order into second scratch buffer */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Initialze temporary scratch pointer */
+  pScr1 = pScratch1;
+
+  /* Assuming scratch1 buffer is aligned by 32-bit */
+  /* Fill (srcBLen - 1U) zeros in scratch1 buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1U);
+
+  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr1, srcALen);
+
+  /* Update pointers */
+  pScr1 += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcALen >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1U);
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1U) >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1U) % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* Temporary pointer for scratch2 */
+  py = pScratch2;
+
+
+  /* Initialization of pIn2 pointer */
+  pIn2 = py;
+
+  /* First part of the processing with loop unrolling process 4 data points at a time.
+   ** a second loop below process for the remaining 1 to 3 samples. */
+
+  /* Actual convolution process starts here */
+  blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2U;
+
+    while (tapCnt > 0U)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2U);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x1, y1, acc0);
+      acc2 = __SMLAD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = _SIMD32_OFFSET(pScr1);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x2, y2, acc0);
+      acc2 = __SMLAD(x1, y2, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+      acc1 = __SMLADX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr1 + 2U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+
+#else
+
+      /* Read four samples from smaller buffer */
+	  a = *pIn2;
+	  b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+
+	  a = *(pIn2 + 2);
+	  b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLAD(x1, y1, acc0);
+
+      acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+	  a = *pScr1;
+	  b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLAD(x2, y2, acc0);
+
+      acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      acc1 = __SMLADX(x3, y2, acc1);
+
+	  a = *(pScr1 + 2);
+	  b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      /* update scratch pointers */
+      pIn2 += 4U;
+      pScr1 += 4U;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4U;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3U;
+
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2);
+      acc1 += (*pScr1++ * *pIn2);
+      acc2 += (*pScr1++ * *pIn2);
+      acc3 += (*pScr1++ * *pIn2++);
+
+      pScr1 -= 3U;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 4U;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+  /* Calculate convolution for remaining samples of Bigger length sequence */
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1U;
+
+    while (tapCnt > 0U)
+    {
+
+      acc0 += (*pScr1++ * *pIn2++);
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1U;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.
+     ** Then store the output in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 1U;
+
+  }
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c
new file mode 100644
index 0000000..16b0424
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c
@@ -0,0 +1,1398 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_fast_q15.c
+ * Description:  Fast Q15 Convolution
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results
+ * but provides only a single guard bit. There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally
+   * divided into three stages according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first stage of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.
+   * In the third stage of the algorithm, the multiplications decrease by one
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]
+   * sum = x[0] * y[1] + x[1] * y[0]
+   * ....
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while ((count < 4U) && (blockSize1 > 0U))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between
+     * inputA samples and inputB samples */
+    k = count;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD
+     * So, py is incremented by 1 */
+    py = py + 1U;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1U);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  py = pSrc2;
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+
+  /* --------------------
+   * Stage2 process
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4 */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      py = py - 1U;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+	  px+= 2U;
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+		px += 4U;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while (--k);
+
+      /* For the next MAC operations, SIMD is not used
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      if (k == 1U)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if (k == 2U)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+		px += 2U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if (k == 3U)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+		px += 3U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+   * ....
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+   * sum +=  x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  pIn2 = pSrc2 - 1U;
+  py = pIn2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2U;
+
+  while ((j > 0U) && (blockSize3 > 0U))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD
+     * So, py is incremented by 1 */
+    py = py + 1U;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4U;
+
+    while (k > 0U)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1U;
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+  q15_t a, b;
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally
+   * divided into three stages according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first stage of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.
+   * In the third stage of the algorithm, the multiplications decrease by one
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]
+   * sum = x[0] * y[1] + x[1] * y[0]
+   * ....
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while ((count < 4U) && (blockSize1 > 0U))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between
+     * inputA samples and inputB samples */
+    k = count;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1U);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  py = pSrc2;
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+
+  /* --------------------
+   * Stage2 process
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4 */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      py = py - 1U;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+	  a = *px++;
+	  b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x0 = __PKHBT(a, b, 16);
+	  a = *px;
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *px;
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x2 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(b, a, 16);
+
+#else
+
+	  x2 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5], x[6] */
+	  a = *(px + 2);
+	  b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x0 = __PKHBT(a, b, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+		px += 4U;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while (--k);
+
+      /* For the next MAC operations, SIMD is not used
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      if (k == 1U)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+		a = *px;
+		b = *(px+1);
+		px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if (k == 2U)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+		px += 2U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if (k == 3U)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+		a = *(px+2);
+		b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 3U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+	  *pOut++ = (q15_t)(acc0 >> 15);
+	  *pOut++ = (q15_t)(acc1 >> 15);
+	  *pOut++ = (q15_t)(acc2 >> 15);
+	  *pOut++ = (q15_t)(acc3 >> 15);
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+   * ....
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+   * sum +=  x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  pIn2 = pSrc2 - 1U;
+  py = pIn2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2U;
+
+  while ((j > 0U) && (blockSize3 > 0U))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while (k > 0U)
+    {
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4U;
+
+    while (k > 0U)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1U;
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c
new file mode 100644
index 0000000..bc57221
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c
@@ -0,0 +1,565 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_fast_q31.c
+ * Description:  Fast Q31 Convolution
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ *
+ * \par
+ * See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally
+   * divided into three stages according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first stage of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.
+   * In the third stage of the algorithm, the multiplications decrease by one
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]
+   * sum = x[0] * y[1] + x[1] * y[0]
+   * ....
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[1] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[2] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[3] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+  /* -------------------
+   * Stage2 process
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4 */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[srcBLen - 3] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[srcBLen - 3] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[srcBLen - 3] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while (--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 << 1);
+      *pOut++ = (q31_t) (acc1 << 1);
+      *pOut++ = (q31_t) (acc2 << 1);
+      *pOut++ = (q31_t) (acc3 << 1);
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+   * ....
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+   * sum +=  x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  py = pSrc2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c
new file mode 100644
index 0000000..47f6f84
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c
@@ -0,0 +1,533 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_opt_q15.c
+ * Description:  Convolution of Q15 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ *
+ * \par
+ * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  uint32_t tapCnt;                               /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* pointer to take end of scratch2 buffer */
+  pScr2 = pScratch2 + srcBLen - 1;
+
+  /* points to smaller length sequence */
+  px = pIn2;
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcBLen >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  /* Copy smaller length input sequence in reverse order into second scratch buffer */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Initialze temporary scratch pointer */
+  pScr1 = pScratch1;
+
+  /* Assuming scratch1 buffer is aligned by 32-bit */
+  /* Fill (srcBLen - 1U) zeros in scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1U);
+
+  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr1, srcALen);
+
+  /* Update pointers */
+  pScr1 += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcALen >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1U);
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1U) >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1U) % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif
+
+  /* Temporary pointer for scratch2 */
+  py = pScratch2;
+
+
+  /* Initialization of pIn2 pointer */
+  pIn2 = py;
+
+  /* First part of the processing with loop unrolling process 4 data points at a time.
+   ** a second loop below process for the remaining 1 to 3 samples. */
+
+  /* Actual convolution process starts here */
+  blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2U;
+
+    while (tapCnt > 0U)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2U);
+
+      /* multiply and accumlate */
+      acc0 = __SMLALD(x1, y1, acc0);
+      acc2 = __SMLALD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = _SIMD32_OFFSET(pScr1);
+
+      /* multiply and accumlate */
+      acc0 = __SMLALD(x2, y2, acc0);
+      acc2 = __SMLALD(x1, y2, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr1 + 2U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#else
+
+      /* Read four samples from smaller buffer */
+	  a = *pIn2;
+	  b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+
+	  a = *(pIn2 + 2);
+	  b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLALD(x1, y1, acc0);
+
+      acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+	  a = *pScr1;
+	  b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLALD(x2, y2, acc0);
+
+      acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+	  a = *(pScr1 + 2);
+	  b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      pIn2 += 4U;
+      pScr1 += 4U;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4U;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3U;
+
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2);
+      acc1 += (*pScr1++ * *pIn2);
+      acc2 += (*pScr1++ * *pIn2);
+      acc3 += (*pScr1++ * *pIn2++);
+
+      pScr1 -= 3U;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 4U;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+  /* Calculate convolution for remaining samples of Bigger length sequence */
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1U;
+
+    while (tapCnt > 0U)
+    {
+
+      /* Read next two samples from scratch1 buffer */
+      acc0 += (*pScr1++ * *pIn2++);
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1U;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.
+     ** Then store the output in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 1U;
+
+  }
+
+}
+
+
+/**
+ * @} end of Conv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c
new file mode 100644
index 0000000..1dc2e49
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c
@@ -0,0 +1,423 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_opt_q7.c
+ * Description:  Convolution of Q7 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ *
+ */
+
+void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
+  q15_t x4;                                      /* Temporary input variable */
+  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
+  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
+  q7_t *px;                                      /* Temporary input1 pointer */
+  q15_t *py;                                     /* Temporary input2 pointer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3, y1;                          /* Temporary input variables */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t out0, out1, out2, out3;                   /* temporary variables */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* pointer to take end of scratch2 buffer */
+  pScr2 = pScratch2;
+
+  /* points to smaller length sequence */
+  px = pIn2 + srcBLen - 1;
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcBLen >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Initialze temporary scratch pointer */
+  pScr1 = pScratch1;
+
+  /* Fill (srcBLen - 1U) zeros in scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1U);
+
+  /* Copy (srcALen) samples in scratch buffer */
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcALen >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1U);
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1U) >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1U) % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif
+
+  /* Temporary pointer for scratch2 */
+  py = pScratch2;
+
+  /* Initialization of pIn2 pointer */
+  pIn2 = (q7_t *) py;
+
+  pScr2 = py;
+
+  /* Actual convolution process starts here */
+  blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2U;
+
+    while (tapCnt > 0U)
+    {
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x1, y1, acc0);
+      acc2 = __SMLAD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2 + 2U);
+
+      acc0 = __SMLAD(x2, y1, acc0);
+
+      acc2 = __SMLAD(x1, y1, acc2);
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      pScr2 += 4U;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4U;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3U;
+
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2);
+      acc1 += (*pScr1++ * *pScr2);
+      acc2 += (*pScr1++ * *pScr2);
+      acc3 += (*pScr1++ * *pScr2++);
+
+      pScr1 -= 3U;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    out0 = (q7_t) (__SSAT(acc0 >> 7U, 8));
+    out1 = (q7_t) (__SSAT(acc1 >> 7U, 8));
+    out2 = (q7_t) (__SSAT(acc2 >> 7U, 8));
+    out3 = (q7_t) (__SSAT(acc3 >> 7U, 8));
+
+    *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 4U;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+  /* Calculate convolution for remaining samples of Bigger length sequence */
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1U;
+
+    while (tapCnt > 0U)
+    {
+      acc0 += (*pScr1++ * *pScr2++);
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1U;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 1U;
+
+  }
+
+}
+
+
+/**
+ * @} end of Conv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c
new file mode 100644
index 0000000..9eae124
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c
@@ -0,0 +1,678 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_partial_f32.c
+ * Description:  Partial convolution of floating-point sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup PartialConv Partial Convolution
+ *
+ * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.
+ * Each function has two additional arguments.
+ * firstIndex specifies the starting index of the subset of output samples.
+ * numPoints is the number of output samples to compute.
+ * The function computes the output in the range
+ * [firstIndex, ..., firstIndex+numPoints-1].
+ * The output array pDst contains numPoints values.
+ *
+ * The allowable range of output indices is [0 srcALen+srcBLen-2].
+ * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.
+ * Otherwise the functions return ARM_MATH_SUCCESS.
+ * \note Refer arm_conv_f32() for details on fixed point behavior.
+ *
+ *
+ * Fast Versions
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15 of partial convolution.  Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * Opt Versions
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the location where the output result is written.
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count = 0U, blkCnt, check;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = ((int32_t) check - blockSize3) -
+      (blockSize1 + (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally
+     * divided into three stages according to the number of multiplications that has to be
+     * taken place between inputA samples and inputB samples. In the first stage of the
+     * algorithm, the multiplications increase by one for every iteration.
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.
+     * In the third stage of the algorithm, the multiplications decrease by one
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------
+     * Initializations of stage1
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]
+     * sum = x[0] * y[1] + x[1] * y[0]
+     * ....
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed.
+       Since the partial convolution starts from from firstIndex
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1U + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc1 = pIn2 + firstIndex;
+    py = pSrc1;
+
+    /* ------------------------
+     * Stage1 process
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while (blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* x[1] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* x[2] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* x[3] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc1;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------
+     * Initializations of stage2
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+     * ....
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+     */
+
+    /* Working pointer of inputA */
+    if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0U;
+
+    /* -------------------
+     * Stage2 process
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+     * So, to loop unroll over blockSize2,
+     * srcBLen should be greater than or equal to 4 */
+    if (srcBLen >= 4U)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+      while (blkCnt > 0U)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0.0f;
+        acc1 = 0.0f;
+        acc2 = 0.0f;
+        acc3 = 0.0f;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += x0 * c0;
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += x1 * c0;
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += x2 * c0;
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 += x3 * c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += x1 * c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += x2 * c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += x3 * c0;
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 += x0 * c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += x2 * c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += x3 * c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += x0 * c0;
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 += x1 * c0;
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 += x3 * c0;
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 += x0 * c0;
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 += x1 * c0;
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 += x2 * c0;
+
+
+        } while (--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4U;
+
+        while (k > 0U)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += x0 * c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += x1 * c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += x2 * c0;
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += x3 * c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = acc0;
+        *pOut++ = acc1;
+        *pOut++ = acc2;
+        *pOut++ = acc3;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count += 4U;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulates */
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4U;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------
+     * Initializations of stage3
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+     * ....
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+     * sum +=  x[srcALen-1] * y[srcBLen-1]
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1U;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    py = pSrc2;
+
+    while (blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0.0f;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0U; j <= i; j++)
+      {
+        /* Check the array limitations for inputs */
+        if ((((i - j) < srcBLen) && (j < srcALen)))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += pIn1[j] * pIn2[i - j];
+        }
+      }
+      /* Store the output in the destination buffer */
+      pDst[i] = sum;
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
new file mode 100644
index 0000000..f469d1f
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
@@ -0,0 +1,756 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_partial_fast_opt_q15.c
+ * Description:  Fast Q15 Partial convolution
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the location where the output result is written.
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;
+
+  uint32_t tapCnt;                               /* loop count */
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+
+    /* Copy smaller length input sequence in reverse order into second scratch buffer */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Assuming scratch1 buffer is aligned by 32-bit */
+    /* Fill (srcBLen - 1U) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1U);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+    /* Copy (srcALen) samples in scratch buffer */
+    arm_copy_q15(pIn1, pScr1, srcALen);
+
+    /* Update pointers */
+    pScr1 += srcALen;
+
+    /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+    /* Update pointer */
+    pScr1 += (srcBLen - 1U);
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* First part of the processing with loop unrolling process 4 data points at a time.
+     ** a second loop below process for the remaining 1 to 3 samples. */
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* Read next two samples from scratch1 buffer */
+      x2 = *__SIMD32(pScr1)++;
+
+      tapCnt = (srcBLen) >> 2U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pIn2);
+        y2 = _SIMD32_OFFSET(pIn2 + 2U);
+
+        /* multiply and accumlate */
+        acc0 = __SMLAD(x1, y1, acc0);
+        acc2 = __SMLAD(x2, y1, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        /* multiply and accumlate */
+        acc1 = __SMLADX(x3, y1, acc1);
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = _SIMD32_OFFSET(pScr1);
+
+        /* multiply and accumlate */
+        acc0 = __SMLAD(x2, y2, acc0);
+
+        acc2 = __SMLAD(x1, y2, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x1, x2, 0);
+#else
+        x3 = __PKHBT(x2, x1, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y1, acc3);
+        acc1 = __SMLADX(x3, y2, acc1);
+
+        x2 = _SIMD32_OFFSET(pScr1 + 2U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y2, acc3);
+
+        /* update scratch pointers */
+        pIn2 += 4U;
+        pScr1 += 4U;
+
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4U;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3U;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4U;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* Read two samples from smaller buffer */
+        y1 = *__SIMD32(pIn2)++;
+
+        acc0 = __SMLAD(x1, y1, acc0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1U;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while (tapCnt > 0U)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* The result is in 2.30 format.  Convert to 1.15 with saturation.
+       ** Then store the output in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1U;
+
+    }
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;                             /* Status variable */
+  uint32_t tapCnt;                               /* loop count */
+  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */
+  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */
+
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1U) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1U);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = (srcBLen - 1U) >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = (srcBLen - 1U) % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x10 = *pScr1++;
+      x11 = *pScr1++;
+
+      /* Read next two samples from scratch1 buffer */
+      x20 = *pScr1++;
+      x21 = *pScr1++;
+
+      tapCnt = (srcBLen) >> 2U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2;
+        y11 = *(pIn2 + 1U);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+        acc2 += (q31_t) x20 *y10;
+        acc2 += (q31_t) x21 *y11;
+
+        /* multiply and accumlate */
+        acc1 += (q31_t) x11 *y10;
+        acc1 += (q31_t) x20 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1;
+        x11 = *(pScr1 + 1U);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x21 *y10;
+        acc3 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch2 buffer */
+        y10 = *(pIn2 + 2U);
+        y11 = *(pIn2 + 3U);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x20 *y10;
+        acc0 += (q31_t) x21 *y11;
+        acc2 += (q31_t) x10 *y10;
+        acc2 += (q31_t) x11 *y11;
+        acc1 += (q31_t) x21 *y10;
+        acc1 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x20 = *(pScr1 + 2);
+        x21 = *(pScr1 + 3);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x11 *y10;
+        acc3 += (q31_t) x20 *y11;
+
+        /* update scratch pointers */
+        pIn2 += 4U;
+        pScr1 += 4U;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4U;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3U;
+
+      while (tapCnt > 0U)
+      {
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3U;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = __SSAT((acc0 >> 15), 16);
+      *pOut++ = __SSAT((acc1 >> 15), 16);
+      *pOut++ = __SSAT((acc2 >> 15), 16);
+      *pOut++ = __SSAT((acc3 >> 15), 16);
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4U;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1++;
+        x11 = *pScr1++;
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2++;
+        y11 = *pIn2++;
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1U;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while (tapCnt > 0U)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1U;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
new file mode 100644
index 0000000..0d4486a
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
@@ -0,0 +1,1494 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_partial_fast_q15.c
+ * Description:  Fast Q15 Partial convolution
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the location where the output result is written.
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+
+arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >=srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally
+     * divided into three stages according to the number of multiplications that has to be
+     * taken place between inputA samples and inputB samples. In the first stage of the
+     * algorithm, the multiplications increase by one for every iteration.
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.
+     * In the third stage of the algorithm, the multiplications decrease by one
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------
+     * Initializations of stage1
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]
+     * sum = x[0] * y[1] + x[1] * y[0]
+     * ....
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed.
+       Since the partial convolution starts from firstIndex
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1U + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------
+     * Stage1 process
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while ((count < 4U) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between
+       * inputA samples and inputB samples */
+      k = count;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while (blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD
+       * So, py is incremented by 1 */
+      py = py + 1U;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1U;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------
+     * Initializations of stage2
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+     * ....
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+     */
+
+    /* Working pointer of inputA */
+    if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    py = pSrc2;
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 0U;
+
+
+    /* --------------------
+     * Stage2 process
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+     * So, to loop unroll over blockSize2,
+     * srcBLen should be greater than or equal to 4 */
+    if (srcBLen >= 4U)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+      while (blkCnt > 0U)
+      {
+      py = py - 1U;
+
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+
+        /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+        /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+	  px+= 2U;
+
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read the last two inputB samples using SIMD:
+           * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+          acc0 = __SMLADX(x0, c0, acc0);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+          acc1 = __SMLADX(x1, c0, acc1);
+
+          /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+          /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+          acc2 = __SMLADX(x2, c0, acc2);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+          acc3 = __SMLADX(x3, c0, acc3);
+
+          /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+          acc0 = __SMLADX(x2, c0, acc0);
+
+          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+          acc1 = __SMLADX(x3, c0, acc1);
+
+          /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+          /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+		px += 4U;
+
+          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+          acc2 = __SMLADX(x0, c0, acc2);
+
+          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+          acc3 = __SMLADX(x1, c0, acc3);
+
+        } while (--k);
+
+        /* For the next MAC operations, SIMD is not used
+         * So, the 16 bit pointer if inputB, py is updated */
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4U;
+
+        if (k == 1U)
+        {
+          /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLAD(x0, c0, acc0);
+          acc1 = __SMLAD(x1, c0, acc1);
+          acc2 = __SMLADX(x1, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        if (k == 2U)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+          /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+		px += 2U;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+        }
+
+        if (k == 3U)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+          /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+          /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+		px += 3U;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x1, c0, acc0);
+          acc1 = __SMLAD(x2, c0, acc1);
+          acc2 = __SMLADX(x2, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
+
+#else
+
+        *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4U;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4U;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------
+     * Initializations of stage3
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+     * ....
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+     * sum +=  x[srcALen-1] * y[srcBLen-1]
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1U;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    pIn2 = pSrc2 - 1U;
+    py = pIn2;
+
+    /* -------------------
+     * Stage3 process
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2U;
+
+    while ((j > 0U) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD
+       * So, py is incremented by 1 */
+      py = py + 1U;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1U;
+
+    while (blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+  q15_t a, b;
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >=srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = ((int32_t) check - blockSize3) -
+      (blockSize1 + (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally
+     * divided into three stages according to the number of multiplications that has to be
+     * taken place between inputA samples and inputB samples. In the first stage of the
+     * algorithm, the multiplications increase by one for every iteration.
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.
+     * In the third stage of the algorithm, the multiplications decrease by one
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------
+     * Initializations of stage1
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]
+     * sum = x[0] * y[1] + x[1] * y[0]
+     * ....
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed.
+       Since the partial convolution starts from firstIndex
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1U + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------
+     * Stage1 process
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+  while ((count < 4U) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between
+       * inputA samples and inputB samples */
+      k = count;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+  while (blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1U;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------
+     * Initializations of stage2
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+     * ....
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+     */
+
+    /* Working pointer of inputA */
+    if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    py = pSrc2;
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 0U;
+
+
+    /* --------------------
+     * Stage2 process
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+     * So, to loop unroll over blockSize2,
+     * srcBLen should be greater than or equal to 4 */
+    if (srcBLen >= 4U)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+      while (blkCnt > 0U)
+      {
+      py = py - 1U;
+
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+      /* read x[0], x[1] samples */
+	  a = *px++;
+	  b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x0 = __PKHBT(a, b, 16);
+	  a = *px;
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *px;
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x2 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(b, a, 16);
+
+#else
+
+	  x2 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5], x[6] */
+	  a = *(px + 2);
+	  b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x0 = __PKHBT(a, b, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+		px += 4U;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while (--k);
+
+      /* For the next MAC operations, SIMD is not used
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      if (k == 1U)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+		a = *px;
+		b = *(px+1);
+		px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if (k == 2U)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+		px += 2U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if (k == 3U)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+		a = *(px+2);
+		b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 3U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+	  *pOut++ = (q15_t)(acc0 >> 15);
+	  *pOut++ = (q15_t)(acc1 >> 15);
+	  *pOut++ = (q15_t)(acc2 >> 15);
+	  *pOut++ = (q15_t)(acc3 >> 15);
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4U;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4U;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------
+     * Initializations of stage3
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+     * ....
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+     * sum +=  x[srcALen-1] * y[srcBLen-1]
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1U;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    pIn2 = pSrc2 - 1U;
+    py = pIn2;
+
+    /* -------------------
+     * Stage3 process
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2U;
+
+    while ((j > 0U) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1U;
+
+  while (blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#endif /*     #ifndef UNALIGNED_SUPPORT_DISABLE      */
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
new file mode 100644
index 0000000..e845947
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
@@ -0,0 +1,620 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_partial_fast_q31.c
+ * Description:  Fast Q31 Partial convolution
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the location where the output result is written.
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par
+ * See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
+ */
+
+arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally
+     * divided into three stages according to the number of multiplications that has to be
+     * taken place between inputA samples and inputB samples. In the first stage of the
+     * algorithm, the multiplications increase by one for every iteration.
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.
+     * In the third stage of the algorithm, the multiplications decrease by one
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------
+     * Initializations of stage1
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]
+     * sum = x[0] * y[1] + x[1] * y[0]
+     * ....
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed.
+       Since the partial convolution starts from firstIndex
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1U + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------
+     * Stage1 process
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while (blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[1] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[2] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[3] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------
+     * Initializations of stage2
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+     * ....
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+     */
+
+    /* Working pointer of inputA */
+    if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0U;
+
+    /* -------------------
+     * Stage2 process
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+     * So, to loop unroll over blockSize2,
+     * srcBLen should be greater than or equal to 4 */
+    if (srcBLen >= 4U)
+    {
+      /* Loop unroll over blockSize2 */
+      blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+      while (blkCnt > 0U)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+        } while (--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4U;
+
+        while (k > 0U)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 << 1);
+        *pOut++ = (q31_t) (acc1 << 1);
+        *pOut++ = (q31_t) (acc2 << 1);
+        *pOut++ = (q31_t) (acc3 << 1);
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4U;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4U;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------
+     * Initializations of stage3
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+     * ....
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+     * sum +=  x[srcALen-1] * y[srcBLen-1]
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1U;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    py = pSrc2;
+
+    /* -------------------
+     * Stage3 process
+     * ------------------*/
+
+    while (blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
new file mode 100644
index 0000000..78dd548
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
@@ -0,0 +1,753 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_partial_opt_q15.c
+ * Description:  Partial convolution of Q15 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the location where the output result is written.
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *	In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;                             /* Status variable */
+  uint32_t tapCnt;                               /* loop count */
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1U) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1U);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+    /* Copy (srcALen) samples in scratch buffer */
+    arm_copy_q15(pIn1, pScr1, srcALen);
+
+    /* Update pointers */
+    pScr1 += srcALen;
+
+    /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+    /* Update pointer */
+    pScr1 += (srcBLen - 1U);
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* Read next two samples from scratch1 buffer */
+      x2 = *__SIMD32(pScr1)++;
+
+      tapCnt = (srcBLen) >> 2U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pIn2);
+        y2 = _SIMD32_OFFSET(pIn2 + 2U);
+
+        /* multiply and accumlate */
+        acc0 = __SMLALD(x1, y1, acc0);
+        acc2 = __SMLALD(x2, y1, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        /* multiply and accumlate */
+        acc1 = __SMLALDX(x3, y1, acc1);
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = _SIMD32_OFFSET(pScr1);
+
+        /* multiply and accumlate */
+        acc0 = __SMLALD(x2, y2, acc0);
+        acc2 = __SMLALD(x1, y2, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x1, x2, 0);
+#else
+        x3 = __PKHBT(x2, x1, 0);
+#endif
+
+        acc3 = __SMLALDX(x3, y1, acc3);
+        acc1 = __SMLALDX(x3, y2, acc1);
+
+        x2 = _SIMD32_OFFSET(pScr1 + 2U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        acc3 = __SMLALDX(x3, y2, acc3);
+
+        /* update scratch pointers */
+        pIn2 += 4U;
+        pScr1 += 4U;
+
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4U;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3U;
+
+      while (tapCnt > 0U)
+      {
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3U;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4U;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* Read two samples from smaller buffer */
+        y1 = *__SIMD32(pIn2)++;
+
+        acc0 = __SMLALD(x1, y1, acc0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1U;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while (tapCnt > 0U)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1U;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;                             /* Status variable */
+  uint32_t tapCnt;                               /* loop count */
+  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */
+  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */
+
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1U) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1U);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = (srcBLen - 1U) >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = (srcBLen - 1U) % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x10 = *pScr1++;
+      x11 = *pScr1++;
+
+      /* Read next two samples from scratch1 buffer */
+      x20 = *pScr1++;
+      x21 = *pScr1++;
+
+      tapCnt = (srcBLen) >> 2U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2;
+        y11 = *(pIn2 + 1U);
+
+        /* multiply and accumlate */
+        acc0 += (q63_t) x10 *y10;
+        acc0 += (q63_t) x11 *y11;
+        acc2 += (q63_t) x20 *y10;
+        acc2 += (q63_t) x21 *y11;
+
+        /* multiply and accumlate */
+        acc1 += (q63_t) x11 *y10;
+        acc1 += (q63_t) x20 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1;
+        x11 = *(pScr1 + 1U);
+
+        /* multiply and accumlate */
+        acc3 += (q63_t) x21 *y10;
+        acc3 += (q63_t) x10 *y11;
+
+        /* Read next two samples from scratch2 buffer */
+        y10 = *(pIn2 + 2U);
+        y11 = *(pIn2 + 3U);
+
+        /* multiply and accumlate */
+        acc0 += (q63_t) x20 *y10;
+        acc0 += (q63_t) x21 *y11;
+        acc2 += (q63_t) x10 *y10;
+        acc2 += (q63_t) x11 *y11;
+        acc1 += (q63_t) x21 *y10;
+        acc1 += (q63_t) x10 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x20 = *(pScr1 + 2);
+        x21 = *(pScr1 + 3);
+
+        /* multiply and accumlate */
+        acc3 += (q63_t) x11 *y10;
+        acc3 += (q63_t) x20 *y11;
+
+        /* update scratch pointers */
+        pIn2 += 4U;
+        pScr1 += 4U;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4U;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3U;
+
+      while (tapCnt > 0U)
+      {
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3U;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = __SSAT((acc0 >> 15), 16);
+      *pOut++ = __SSAT((acc1 >> 15), 16);
+      *pOut++ = __SSAT((acc2 >> 15), 16);
+      *pOut++ = __SSAT((acc3 >> 15), 16);
+
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4U;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1++;
+        x11 = *pScr1++;
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2++;
+        y11 = *pIn2++;
+
+        /* multiply and accumlate */
+        acc0 += (q63_t) x10 *y10;
+        acc0 += (q63_t) x11 *y11;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1U;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while (tapCnt > 0U)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1U;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
new file mode 100644
index 0000000..351c290
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
@@ -0,0 +1,791 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_partial_opt_q7.c
+ * Description:  Partial convolution of Q7 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the location where the output result is written.
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @param[in]      *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]      *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ *
+ *
+ */
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
+  q15_t x4;                                      /* Temporary input variable */
+  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
+  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
+  q7_t *px;                                      /* Temporary input1 pointer */
+  q15_t *py;                                     /* Temporary input2 pointer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3, y1;                          /* Temporary input variables */
+  arm_status status;
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t out0, out1, out2, out3;                   /* temporary variables */
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2;
+
+    /* points to smaller length sequence */
+    px = pIn2 + srcBLen - 1;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1U) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1U);
+
+    /* Copy (srcALen) samples in scratch buffer */
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+    /* Update pointer */
+    pScr1 += (srcBLen - 1U);
+
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = (q7_t *) py;
+
+    pScr2 = py;
+
+    pOut = pDst + firstIndex;
+
+    pScratch1 += firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* Read next two samples from scratch1 buffer */
+      x2 = *__SIMD32(pScr1)++;
+
+      tapCnt = (srcBLen) >> 2U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pScr2);
+
+        /* multiply and accumlate */
+        acc0 = __SMLAD(x1, y1, acc0);
+        acc2 = __SMLAD(x2, y1, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        /* multiply and accumlate */
+        acc1 = __SMLADX(x3, y1, acc1);
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x1, x2, 0);
+#else
+        x3 = __PKHBT(x2, x1, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y1, acc3);
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pScr2 + 2U);
+
+        acc0 = __SMLAD(x2, y1, acc0);
+
+        acc2 = __SMLAD(x1, y1, acc2);
+
+        acc1 = __SMLADX(x3, y1, acc1);
+
+        x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y1, acc3);
+
+        pScr2 += 4U;
+
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4U;
+
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2);
+        acc1 += (*pScr1++ * *pScr2);
+        acc2 += (*pScr1++ * *pScr2);
+        acc3 += (*pScr1++ * *pScr2++);
+
+        pScr1 -= 3U;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      out0 = (q7_t) (__SSAT(acc0 >> 7U, 8));
+      out1 = (q7_t) (__SSAT(acc1 >> 7U, 8));
+      out2 = (q7_t) (__SSAT(acc2 >> 7U, 8));
+      out3 = (q7_t) (__SSAT(acc3 >> 7U, 8));
+
+      *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 4U;
+
+    }
+
+    blkCnt = (numPoints) & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* Read two samples from smaller buffer */
+        y1 = *__SIMD32(pScr2)++;
+
+        acc0 = __SMLAD(x1, y1, acc0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1U;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while (tapCnt > 0U)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 1U;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+
+  }
+
+  return (status);
+
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
+  q15_t x4;                                      /* Temporary input variable */
+  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
+  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
+  q7_t *px;                                      /* Temporary input1 pointer */
+  q15_t *py;                                     /* Temporary input2 pointer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  arm_status status;
+  q7_t *pOut = pDst;                             /* output pointer */
+  q15_t x10, x11, x20, x21;                      /* Temporary input variables */
+  q15_t y10, y11;                                /* Temporary input variables */
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2;
+
+    /* points to smaller length sequence */
+    px = pIn2 + srcBLen - 1;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1U) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1U);
+
+    /* Copy (srcALen) samples in scratch buffer */
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = (srcBLen - 1U) >> 2U;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.
+     ** No loop unrolling is used. */
+    k = (srcBLen - 1U) % 0x4U;
+
+    while (k > 0U)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = (q7_t *) py;
+
+    pScr2 = py;
+
+    pOut = pDst + firstIndex;
+
+    pScratch1 += firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x10 = *pScr1++;
+      x11 = *pScr1++;
+
+      /* Read next two samples from scratch1 buffer */
+      x20 = *pScr1++;
+      x21 = *pScr1++;
+
+      tapCnt = (srcBLen) >> 2U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read four samples from smaller buffer */
+        y10 = *pScr2;
+        y11 = *(pScr2 + 1U);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+        acc2 += (q31_t) x20 *y10;
+        acc2 += (q31_t) x21 *y11;
+
+
+        acc1 += (q31_t) x11 *y10;
+        acc1 += (q31_t) x20 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1;
+        x11 = *(pScr1 + 1U);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x21 *y10;
+        acc3 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch2 buffer */
+        y10 = *(pScr2 + 2U);
+        y11 = *(pScr2 + 3U);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x20 *y10;
+        acc0 += (q31_t) x21 *y11;
+        acc2 += (q31_t) x10 *y10;
+        acc2 += (q31_t) x11 *y11;
+        acc1 += (q31_t) x21 *y10;
+        acc1 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x20 = *(pScr1 + 2);
+        x21 = *(pScr1 + 3);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x11 *y10;
+        acc3 += (q31_t) x20 *y11;
+
+        /* update scratch pointers */
+
+        pScr1 += 4U;
+        pScr2 += 4U;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4U;
+
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2);
+        acc1 += (*pScr1++ * *pScr2);
+        acc2 += (*pScr1++ * *pScr2);
+        acc3 += (*pScr1++ * *pScr2++);
+
+        pScr1 -= 3U;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+      *pOut++ = (q7_t) (__SSAT(acc1 >> 7U, 8));
+      *pOut++ = (q7_t) (__SSAT(acc2 >> 7U, 8));
+      *pOut++ = (q7_t) (__SSAT(acc3 >> 7U, 8));
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 4U;
+
+    }
+
+    blkCnt = (numPoints) & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while (blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1++;
+        x11 = *pScr1++;
+
+        /* Read two samples from smaller buffer */
+        y10 = *pScr2++;
+        y11 = *pScr2++;
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1U;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while (tapCnt > 0U)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 1U;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  return (status);
+
+}
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c
new file mode 100644
index 0000000..43d2b35
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c
@@ -0,0 +1,795 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_partial_q15.c
+ * Description:  Partial convolution of Q15 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the location where the output result is written.
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary input variables */
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally
+     * divided into three stages according to the number of multiplications that has to be
+     * taken place between inputA samples and inputB samples. In the first stage of the
+     * algorithm, the multiplications increase by one for every iteration.
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.
+     * In the third stage of the algorithm, the multiplications decrease by one
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------
+     * Initializations of stage1
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]
+     * sum = x[0] * y[1] + x[1] * y[0]
+     * ....
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed.
+       Since the partial convolution starts from firstIndex
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1U + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------
+     * Stage1 process
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while ((count < 4U) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between
+       * inputA samples and inputB samples */
+      k = count;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while (blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD
+       * So, py is incremented by 1 */
+      py = py + 1U;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1U;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------
+     * Initializations of stage2
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+     * ....
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+     */
+
+    /* Working pointer of inputA */
+    if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    py = pSrc2;
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 0U;
+
+
+  /* --------------------
+   * Stage2 process
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4 */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      py = py - 1U;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+      px+= 2U;
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLALDX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLALDX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLALDX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLALDX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLALDX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLALDX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+        px += 4U;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLALDX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLALDX(x1, c0, acc3);
+
+      } while (--k);
+
+      /* For the next MAC operations, SIMD is not used
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      if (k == 1U)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+        px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if (k == 2U)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+        px += 2U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+      }
+
+      if (k == 3U)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+
+        c0 = *(py-1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+        px += 3U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+      {
+        px = pIn1 + firstIndex - srcBLen + 1 + count;
+      }
+      else
+      {
+        px = pIn1 + count;
+      }
+      py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4U;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------
+     * Initializations of stage3
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+     * ....
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+     * sum +=  x[srcALen-1] * y[srcBLen-1]
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1U;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    pIn2 = pSrc2 - 1U;
+    py = pIn2;
+
+    /* -------------------
+     * Stage3 process
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2U;
+
+    while ((j > 0U) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD
+       * So, py is incremented by 1 */
+      py = py + 1U;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1U;
+
+    while (blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q15_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if (((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /* #if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c
new file mode 100644
index 0000000..3a108e0
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c
@@ -0,0 +1,616 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_partial_q31.c
+ * Description:  Partial convolution of Q31 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the location where the output result is written.
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2;                   /* Accumulator                  */
+  q31_t x0, x1, x2, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally
+     * divided into three stages according to the number of multiplications that has to be
+     * taken place between inputA samples and inputB samples. In the first stage of the
+     * algorithm, the multiplications increase by one for every iteration.
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.
+     * In the third stage of the algorithm, the multiplications decrease by one
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------
+     * Initializations of stage1
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]
+     * sum = x[0] * y[1] + x[1] * y[0]
+     * ....
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed.
+       Since the partial convolution starts from firstIndex
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1U + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------
+     * Stage1 process
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while (blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[1] * y[srcBLen - 2] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[2] * y[srcBLen - 3] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[3] * y[srcBLen - 4] */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------
+     * Initializations of stage2
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+     * ....
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+     */
+
+    /* Working pointer of inputA */
+    if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0U;
+
+    /* -------------------
+     * Stage2 process
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+     * So, to loop unroll over blockSize2,
+     * srcBLen should be greater than or equal to 4 */
+    if (srcBLen >= 4U)
+    {
+      /* Loop unroll over blkCnt */
+
+      blkCnt = blockSize2 / 3;
+      while (blkCnt > 0U)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+
+        /* read x[0], x[1] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+
+        /* Apply loop unrolling and compute 3 MACs simultaneously. */
+        k = srcBLen / 3;
+
+        /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py);
+
+          /* Read x[2] sample */
+          x2 = *(px);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += (q63_t) x2 *c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py - 1U);
+
+          /* Read x[3] sample */
+          x0 = *(px + 1U);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += (q63_t) x1 *c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += (q63_t) x2 *c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += (q63_t) x0 *c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py - 2U);
+
+          /* Read x[4] sample */
+          x1 = *(px + 2U);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += (q63_t) x2 *c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += (q63_t) x0 *c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += (q63_t) x1 *c0;
+
+
+          px += 3U;
+
+          py -= 3U;
+
+        } while (--k);
+
+        /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen - (3 * (srcBLen / 3));
+
+        while (k > 0U)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += (q63_t) x2 *c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 >> 31);
+        *pOut++ = (q31_t) (acc1 >> 31);
+        *pOut++ = (q31_t) (acc2 >> 31);
+
+        /* Increment the pointer pIn1 index, count by 3 */
+        count += 3U;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+       ** No loop unrolling is used. */
+      blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4U;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------
+     * Initializations of stage3
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+     * ....
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+     * sum +=  x[srcALen-1] * y[srcBLen-1]
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.
+       The blockSize3 variable holds the number of MAC operations performed */
+    count = srcBLen - 1U;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    py = pSrc2;
+
+    /* -------------------
+     * Stage3 process
+     * ------------------*/
+
+    while (blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q31_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if (((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q31_t) (sum >> 31U);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*    #if defined (ARM_MATH_DSP)      */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c
new file mode 100644
index 0000000..cb4c562
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c
@@ -0,0 +1,750 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_partial_q7.c
+ * Description:  Partial convolution of Q7 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the location where the output result is written.
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par
+ * Refer the function arm_conv_partial_opt_q7() for a faster implementation of this function.
+ *
+ */
+
+arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;
+  q15_t in1, in2;
+  q7_t x0, x1, x2, x3, c0, c1;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter */
+  arm_status status;
+
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if (srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally
+     * divided into three stages according to the number of multiplications that has to be
+     * taken place between inputA samples and inputB samples. In the first stage of the
+     * algorithm, the multiplications increase by one for every iteration.
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.
+     * In the third stage of the algorithm, the multiplications decrease by one
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------
+     * Initializations of stage1
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]
+     * sum = x[0] * y[1] + x[1] * y[0]
+     * ....
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed.
+       Since the partial convolution starts from from firstIndex
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1U + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------
+     * Stage1 process
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while (blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* x[0] , x[1] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 1] , y[srcBLen - 2] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[0] * y[srcBLen - 1] */
+        /* x[1] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* x[2] , x[3] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 3] , y[srcBLen - 4] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[2] * y[srcBLen - 3] */
+        /* x[3] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------
+     * Initializations of stage2
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+     * ....
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+     */
+
+    /* Working pointer of inputA */
+    if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+    {
+      px = pIn1 + firstIndex - srcBLen + 1;
+    }
+    else
+    {
+      px = pIn1;
+    }
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0U;
+
+    /* -------------------
+     * Stage2 process
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+     * So, to loop unroll over blockSize2,
+     * srcBLen should be greater than or equal to 4 */
+    if (srcBLen >= 4U)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+      while (blkCnt > 0U)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 2] sample */
+          c1 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* x[0] and x[1] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[1] and x[2] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 4] sample */
+          c1 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[4] and x[5] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* x[5] and x[6] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+        } while (--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4U;
+
+        while (k > 0U)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += ((q31_t) x0 * c0);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += ((q31_t) x1 * c0);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += ((q31_t) x2 * c0);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += ((q31_t) x3 * c0);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4U;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while (k > 0U)
+        {
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4U;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Increment the pointer pIn1 index, count by 1 */
+ 	    count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while (blkCnt > 0U)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while (k > 0U)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+        {
+          px = pIn1 + firstIndex - srcBLen + 1 + count;
+        }
+        else
+        {
+          px = pIn1 + count;
+        }
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------
+     * Initializations of stage3
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+     * ....
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+     * sum +=  x[srcALen-1] * y[srcBLen-1]
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1U;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1U);
+    py = pSrc2;
+
+    /* -------------------
+     * Stage3 process
+     * ------------------*/
+
+    while (blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = count % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB;                            /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if (((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*  #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c
new file mode 100644
index 0000000..c6721e0
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c
@@ -0,0 +1,722 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_q15.c
+ * Description:  Convolution of Q15 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function arm_conv_opt_q15() for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally
+   * divided into three stages according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first stage of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.
+   * In the third stage of the algorithm, the multiplications decrease by one
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]
+   * sum = x[0] * y[1] + x[1] * y[0]
+   * ....
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while ((count < 4U) && (blockSize1 > 0U))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between
+     * inputA samples and inputB samples */
+    k = count;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD
+     * So, py is incremented by 1 */
+    py = py + 1U;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1U);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  py = pSrc2;
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+
+  /* --------------------
+   * Stage2 process
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4 */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      py = py - 1U;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+      px+= 2U;
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLALDX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLALDX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLALDX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLALDX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLALDX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLALDX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+        px += 4U;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLALDX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLALDX(x1, c0, acc3);
+
+      } while (--k);
+
+      /* For the next MAC operations, SIMD is not used
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      if (k == 1U)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+        px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if (k == 2U)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+        px += 2U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+      }
+
+      if (k == 3U)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+
+        c0 = *(py-1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+        px += 3U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+       /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+   * ....
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+   * sum +=  x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  blockSize3 = srcBLen - 1U;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  pIn2 = pSrc2 - 1U;
+  py = pIn2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2U;
+
+  while ((j > 0U) && (blockSize3 > 0U))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD
+     * So, py is incremented by 1 */
+    py = py + 1U;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4U;
+
+    while (k > 0U)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1U;
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* input pointer */
+  q15_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if (((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q31_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U);
+  }
+
+#endif /* #if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c
new file mode 100644
index 0000000..14e5f86
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c
@@ -0,0 +1,553 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_q31.c
+ * Description:  Convolution of Q31 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q63_t sum;                                     /* Accumulator */
+  q63_t acc0, acc1, acc2;                        /* Accumulator */
+  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (q31_t *) pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = (q31_t *) pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally
+   * divided into three stages according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first stage of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.
+   * In the third stage of the algorithm, the multiplications decrease by one
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]
+   * sum = x[0] * y[1] + x[1] * y[0]
+   * ....
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[1] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[2] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[3] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+  /* -------------------
+   * Stage2 process
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4 */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll by 3 */
+    blkCnt = blockSize2 / 3;
+
+    while (blkCnt > 0U)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+
+      /* Apply loop unrolling and compute 3 MACs simultaneously. */
+      k = srcBLen / 3;
+
+      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py);
+
+        /* Read x[3] sample */
+        x2 = *(px);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py - 1U);
+
+        /* Read x[4] sample */
+        x0 = *(px + 1U);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x0 * c0);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py - 2U);
+
+        /* Read x[5] sample */
+        x1 = *(px + 2U);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x1 * c0);
+
+        /* update scratch pointers */
+        px += 3U;
+        py -= 3U;
+
+      } while (--k);
+
+      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen - (3 * (srcBLen / 3));
+
+      while (k > 0U)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 >> 31);
+      *pOut++ = (q31_t) (acc1 >> 31);
+      *pOut++ = (q31_t) (acc2 >> 31);
+
+      /* Increment the pointer pIn1 index, count by 3 */
+      count += 3U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+   * ....
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+   * sum +=  x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  py = pSrc2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* input pointer */
+  q31_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if (((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q31_t) (sum >> 31U);
+  }
+
+#endif /*     #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c
new file mode 100644
index 0000000..6c4dd3c
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c
@@ -0,0 +1,678 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_conv_q7.c
+ * Description:  Convolution of Q7 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ *
+ * \par
+ * Refer the function arm_conv_opt_q7() for a faster implementation of this function.
+ *
+ */
+
+void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* Temporary variables to hold state and coefficient values */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;                          /* Temporary input variables */
+  q15_t in1, in2;                                /* Temporary input variables */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally
+   * divided into three stages according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first stage of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.
+   * In the third stage of the algorithm, the multiplications decrease by one
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = (srcALen - srcBLen) + 1U;
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]
+   * sum = x[0] * y[1] + x[1] * y[0]
+   * ....
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+      /* y[srcBLen - 1] , y[srcBLen - 2] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+      /* x[0] * y[srcBLen - 1] */
+      /* x[1] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+      /* y[srcBLen - 3] , y[srcBLen - 4] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+      /* x[2] * y[srcBLen - 3] */
+      /* x[3] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+  /* -------------------
+   * Stage2 process
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4 */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 2] sample */
+        c1 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 4] sample */
+        c1 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while (--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+      *pOut++ = (q7_t) (__SSAT(acc1 >> 7U, 8));
+      *pOut++ = (q7_t) (__SSAT(acc2 >> 7U, 8));
+      *pOut++ = (q7_t) (__SSAT(acc3 >> 7U, 8));
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+   * ....
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+   * sum +=  x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1U));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1U);
+  py = pSrc2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+      /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+      /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* input pointer */
+  q7_t *pIn2 = pSrcB;                            /* coefficient pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if (((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q15_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U);
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP)        */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c
new file mode 100644
index 0000000..9451887
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c
@@ -0,0 +1,727 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_correlate_f32.c
+ * Description:  Correlation of floating-point sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup Corr Correlation
+ *
+ * Correlation is a mathematical operation that is similar to convolution.
+ * As with convolution, correlation uses two signals to produce a third signal.
+ * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.
+ * Correlation is commonly used to measure the similarity between two signals.
+ * It has applications in pattern recognition, cryptanalysis, and searching.
+ * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.
+ * Fast versions of the Q15 and Q31 functions are also provided.
+ *
+ * \par Algorithm
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.
+ * The convolution of the two signals is denoted by
+ * 
+ *                   c[n] = a[n] * b[n]
+ * 

+ * In correlation, one of the signals is flipped in time
+ * 
+ *                   c[n] = a[n] * b[-n]
+ * 

+ *
+ * \par
+ * and this is mathematically defined as
+ * \image html CorrelateEquation.gif
+ * \par
+ * The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen.
+ * The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2).
+ * The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.
+ *
+ * Note
+ * \par
+ * The pDst should be initialized to all zeros before being used.
+ *
+ * Fixed-Point Behavior
+ * \par
+ * Correlation requires summing up a large number of intermediate products.
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
+ * Refer to the function specific documentation below for further details of the particular algorithm used.
+ *
+ *
+ * Fast Versions
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * Opt Versions
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in]  *pSrcA points to the first input sequence.
+ * @param[in]  srcALen length of the first input sequence.
+ * @param[in]  *pSrcB points to the second input sequence.
+ * @param[in]  srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1;                              /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulators */
+  float32_t x0, x1, x2, x3, c0;                  /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0U, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counters */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,
+   * we assume zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2U * srcALen) - 1U;
+
+    /* When srcALen > srcBLen, zero padding has to be done to srcB
+     * to make their lengths equal.
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+    //while (j > 0U)
+    //{
+    //  /* Zero is stored in the destination buffer */
+    //  *pOut++ = 0.0f;
+
+    //  /* Decrement the loop counter */
+    //  j--;
+    //}
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally
+   * divided into three parts according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first part of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second part of the algorithm, srcBLen number of multiplications are done.
+   * In the third part of the algorithm, the multiplications decrease by one
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]
+   * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]
+   * ....
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1U);
+  py = pSrc1;
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += *px++ * *py++;
+      /* x[1] * y[srcBLen - 3] */
+      sum += *px++ * *py++;
+      /* x[2] * y[srcBLen - 2] */
+      sum += *px++ * *py++;
+      /* x[3] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+  /* -------------------
+   * Stage2 process
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[3] * y[0] */
+        acc3 += x3 * c0;
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[1] */
+        acc3 += x0 * c0;
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[2] */
+        acc3 += x1 * c0;
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[3] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[3] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[3] */
+        acc3 += x2 * c0;
+
+
+      } while (--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = acc0;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = acc1;
+      pOut += inc;
+
+      *pOut = acc2;
+      pOut += inc;
+
+      *pOut = acc3;
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * ....
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+   * sum +=  x[srcALen-1] * y[0]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1U;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1U));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB + (srcBLen - 1U);      /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i = 0U, j;                            /* loop counters */
+  uint32_t inv = 0U;                             /* Reverse order flag */
+  uint32_t tot = 0U;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two
+   * inputs of same length. But to improve the performance, we assume zeroes
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2U);
+
+  if (srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if (srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1U);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0U; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0U; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if ((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[-((int32_t) i - j)];
+      }
+    }
+    /* Store the output in the destination buffer */
+    if (inv == 1)
+      *pDst-- = sum;
+    else
+      *pDst++ = sum;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
new file mode 100644
index 0000000..baebc49
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
@@ -0,0 +1,500 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_correlate_fast_opt_q15.c
+ * Description:  Fast Q15 Correlation
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *  In this case input, output, scratch buffers should be aligned by 32-bit
+ *
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t x1, x2, x3;                              /* temporary variables for holding input and coefficient values */
+  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  uint32_t tapCnt;
+  q31_t y1, y2;
+  q15_t *pScr;                                   /* Intermediate pointers        */
+  q15_t *pOut = pDst;                            /* output pointer               */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2U * srcALen) - 1U;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB
+     * to make their lengths equal.
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  pScr = pScratch;
+
+  /* Fill (srcBLen - 1U) zeros in scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1U));
+
+  /* Update temporary scratch pointer */
+  pScr += (srcBLen - 1U);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr, srcALen);
+
+  /* Update pointers */
+  pScr += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = srcALen >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (j > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  j = srcALen % 0x4U;
+
+  while (j > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1U));
+
+  /* Update pointer */
+  pScr += (srcBLen - 1U);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = (srcBLen - 1U) >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (j > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  j = (srcBLen - 1U) % 0x4U;
+
+  while (j > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+  /* Temporary pointer for scratch2 */
+  py = pIn2;
+
+
+  /* Actual correlation process starts here */
+  blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read four samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr)++;
+
+    /* Read next four samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr)++;
+
+    tapCnt = (srcBLen) >> 2U;
+
+    while (tapCnt > 0U)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2U);
+
+      acc0 = __SMLAD(x1, y1, acc0);
+
+      acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      x1 = _SIMD32_OFFSET(pScr);
+
+      acc0 = __SMLAD(x2, y2, acc0);
+
+      acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      acc1 = __SMLADX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr + 2U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+#else
+
+      /* Read four samples from smaller buffer */
+      a = *pIn2;
+      b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+
+      a = *(pIn2 + 2);
+      b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLAD(x1, y1, acc0);
+
+      acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      a = *pScr;
+      b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLAD(x2, y2, acc0);
+
+      acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      acc1 = __SMLADX(x3, y2, acc1);
+
+      a = *(pScr + 2);
+      b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+      pIn2 += 4U;
+
+      pScr += 4U;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr -= 4U;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3U;
+
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2);
+      acc1 += (*pScr++ * *pIn2);
+      acc2 += (*pScr++ * *pIn2);
+      acc3 += (*pScr++ * *pIn2++);
+
+      pScr -= 3U;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+    *pOut = (__SSAT(acc0 >> 15U, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc1 >> 15U, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc2 >> 15U, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc3 >> 15U, 16));
+    pOut += inc;
+
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 4U;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+  /* Calculate correlation for remaining samples of Bigger length sequence */
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1U;
+
+    while (tapCnt > 0U)
+    {
+
+      acc0 += (*pScr++ * *pIn2++);
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1U;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+
+    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 1U;
+
+  }
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c
new file mode 100644
index 0000000..7b676d0
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c
@@ -0,0 +1,1307 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_correlate_fast_q15.c
+ * Description:  Fast Q15 Correlation
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0U, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2U * srcALen) - 1U;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB
+     * to make their lengths equal.
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally
+   * divided into three parts according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first part of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second part of the algorithm, srcBLen number of multiplications are done.
+   * In the third part of the algorithm, the multiplications decrease by one
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+   * ....
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1U);
+  py = pSrc1;
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+  /* -------------------
+   * Stage2 process
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px + 1);
+	  px += 2U;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:
+         * y[0] and y[1] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLAD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px + 1);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLAD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLAD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLAD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLAD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px + 2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px + 3);
+		px += 4U;
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLAD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLAD(x1, c0, acc3);
+
+      } while (--k);
+
+      /* For the next MAC operations, SIMD is not used
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      if (k == 1U)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if (k == 2U)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+		px += 2U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+      }
+
+      if (k == 3U)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py)++;
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+
+        c0 = (*py);
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = _SIMD32_OFFSET(px + 2);
+		px += 3U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (acc0 >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (acc1 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc2 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc3 >> 15);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * ....
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+   * sum +=  x[srcALen-1] * y[0]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1U;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0U, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  q15_t a, b;
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2U * srcALen) - 1U;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB
+     * to make their lengths equal.
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally
+   * divided into three parts according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first part of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second part of the algorithm, srcBLen number of multiplications are done.
+   * In the third part of the algorithm, the multiplications decrease by one
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+   * ....
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1U);
+  py = pSrc1;
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+  /* -------------------
+   * Stage2 process
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x0 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+	  px += 2U;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:
+         * y[0] and y[1] */
+		  a = *py;
+		  b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		  c0 = __PKHBT(a, b, 16);
+
+#else
+
+		  c0 = __PKHBT(b, a, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLAD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(x1, c0, acc1);
+
+        /* Read x[2], x[3], x[4] */
+	  	a = *px;
+	  	b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x2 = __PKHBT(a, b, 16);
+	  	a = *(px + 2);
+	  	x3 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x2 = __PKHBT(b, a, 16);
+	  	a = *(px + 2);
+	  	x3 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLAD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLAD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+		  a = *(py + 2);
+		  b = *(py + 3);
+
+		  py += 4U;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		  c0 = __PKHBT(a, b, 16);
+
+#else
+
+		  c0 = __PKHBT(b, a, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLAD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLAD(x3, c0, acc1);
+
+        /* Read x[4], x[5], x[6] */
+	  	a = *(px + 2);
+	  	b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x0 = __PKHBT(a, b, 16);
+	  	a = *(px + 4);
+	  	x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x0 = __PKHBT(b, a, 16);
+	  	a = *(px + 4);
+	  	x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 4U;
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLAD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLAD(x1, c0, acc3);
+
+      } while (--k);
+
+      /* For the next MAC operations, SIMD is not used
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      if (k == 1U)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+		a = *px;
+		b = *(px + 1);
+
+		px++;;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+		x3 = __PKHBT(b, a, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if (k == 2U)
+      {
+        /* Read y[4], y[5] */
+		  a = *py;
+		  b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		  c0 = __PKHBT(a, b, 16);
+
+#else
+
+		  c0 = __PKHBT(b, a, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  	a = *px;
+	  	b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x3 = __PKHBT(a, b, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x3 = __PKHBT(b, a, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 2U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+      }
+
+      if (k == 3U)
+      {
+        /* Read y[4], y[5] */
+		  a = *py;
+		  b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		  c0 = __PKHBT(a, b, 16);
+
+#else
+
+		  c0 = __PKHBT(b, a, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		py += 2U;
+
+        /* Read x[7], x[8], x[9] */
+	  	a = *px;
+	  	b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x3 = __PKHBT(a, b, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x3 = __PKHBT(b, a, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+
+        c0 = (*py);
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+		b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+		x3 = __PKHBT(b, a, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 3U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (acc0 >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (acc1 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc2 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc3 >> 15);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * ....
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+   * sum +=  x[srcALen-1] * y[0]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1U;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#endif /*   #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c
new file mode 100644
index 0000000..53373ac
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c
@@ -0,0 +1,600 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_correlate_fast_q31.c
+ * Description:  Fast Q31 Correlation
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ *
+ * \par
+ * See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0U, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2U * srcALen) - 1U;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB
+     * to make their lengths equal.
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally
+   * divided into three parts according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first part of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second part of the algorithm, srcBLen number of multiplications are done.
+   * In the third part of the algorithm, the multiplications decrease by one
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+   * ....
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1U);
+  py = pSrc1;
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[1] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[3] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+  /* -------------------
+   * Stage2 process
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4 */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[3] * y[0] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[3] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[3] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[3] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while (--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 << 1);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc3 << 1);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * ....
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+   * sum +=  x[srcALen-1] * y[0]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1U;
+
+  /* Working pointer of inputA */
+  pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1U;
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c
new file mode 100644
index 0000000..c021b05
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c
@@ -0,0 +1,501 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_correlate_opt_q15.c
+ * Description:  Correlation of Q15 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *	In this case input, output, scratch buffers should be aligned by 32-bit
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+
+void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t x1, x2, x3;                              /* temporary variables for holding input1 and input2 values */
+  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */
+  int32_t inc = 1;                               /* output pointer increment     */
+  uint32_t tapCnt;
+  q31_t y1, y2;
+  q15_t *pScr;                                   /* Intermediate pointers        */
+  q15_t *pOut = pDst;                            /* output pointer               */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2U * srcALen) - 1U;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB
+     * to make their lengths equal.
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  pScr = pScratch;
+
+  /* Fill (srcBLen - 1U) zeros in scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1U));
+
+  /* Update temporary scratch pointer */
+  pScr += (srcBLen - 1U);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr, srcALen);
+
+  /* Update pointers */
+  //pIn1 += srcALen;
+  pScr += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = srcALen >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (j > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  j = srcALen % 0x4U;
+
+  while (j > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1U));
+
+  /* Update pointer */
+  pScr += (srcBLen - 1U);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = (srcBLen - 1U) >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (j > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  j = (srcBLen - 1U) % 0x4U;
+
+  while (j > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* Temporary pointer for scratch2 */
+  py = pIn2;
+
+
+  /* Actual correlation process starts here */
+  blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read four samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr)++;
+
+    /* Read next four samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr)++;
+
+    tapCnt = (srcBLen) >> 2U;
+
+    while (tapCnt > 0U)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2U);
+
+      acc0 = __SMLALD(x1, y1, acc0);
+
+      acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+      x1 = _SIMD32_OFFSET(pScr);
+
+      acc0 = __SMLALD(x2, y2, acc0);
+
+      acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr + 2U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#else
+
+      /* Read four samples from smaller buffer */
+	  a = *pIn2;
+	  b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+
+	  a = *(pIn2 + 2);
+	  b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLALD(x1, y1, acc0);
+
+      acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+	  a = *pScr;
+	  b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLALD(x2, y2, acc0);
+
+      acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+	  a = *(pScr + 2);
+	  b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      pIn2 += 4U;
+
+      pScr += 4U;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr -= 4U;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3U;
+
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2);
+      acc1 += (*pScr++ * *pIn2);
+      acc2 += (*pScr++ * *pIn2);
+      acc3 += (*pScr++ * *pIn2++);
+
+      pScr -= 3U;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+    *pOut = (__SSAT(acc0 >> 15U, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc1 >> 15U, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc2 >> 15U, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc3 >> 15U, 16));
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 4U;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+  /* Calculate correlation for remaining samples of Bigger length sequence */
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1U;
+
+    while (tapCnt > 0U)
+    {
+
+      acc0 += (*pScr++ * *pIn2++);
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1U;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 1U;
+
+  }
+
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c
new file mode 100644
index 0000000..dbffd5d
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c
@@ -0,0 +1,452 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_correlate_opt_q7.c
+ * Description:  Correlation of Q7 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
+ *
+ *
+ */
+
+
+
+void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+  q7_t *pOut = pDst;                             /* output pointer                */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch */
+  q7_t *pIn1;                                    /* inputA pointer                */
+  q7_t *pIn2;                                    /* inputB pointer                */
+  q15_t *py;                                     /* Intermediate inputB pointer   */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
+  uint32_t j, k = 0U, blkCnt;                    /* loop counter                  */
+  int32_t inc = 1;                               /* output pointer increment          */
+  uint32_t outBlockSize;                         /* loop counter                  */
+  q15_t x4;                                      /* Temporary input variable      */
+  uint32_t tapCnt;                               /* loop counter                  */
+  q31_t x1, x2, x3, y1;                          /* Temporary input variables     */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2U * srcALen) - 1U;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB
+     * to make their lengths equal.
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+
+  /* Copy (srcBLen) samples in scratch buffer */
+  k = srcBLen >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Fill (srcBLen - 1U) zeros in scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1U);
+
+  /* Copy (srcALen) samples in scratch buffer */
+  k = srcALen >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1U);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1U) >> 2U;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1U) % 0x4U;
+
+  while (k > 0U)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* Temporary pointer for second sequence */
+  py = pScratch2;
+
+  /* Initialization of pScr2 pointer */
+  pScr2 = pScratch2;
+
+  /* Actual correlation process starts here */
+  blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2U;
+
+    while (tapCnt > 0U)
+    {
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x1, y1, acc0);
+      acc2 = __SMLAD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2 + 2U);
+
+      acc0 = __SMLAD(x2, y1, acc0);
+
+      acc2 = __SMLAD(x1, y1, acc2);
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      pScr2 += 4U;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4U;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3U;
+
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2);
+      acc1 += (*pScr1++ * *pScr2);
+      acc2 += (*pScr1++ * *pScr2);
+      acc3 += (*pScr1++ * *pScr2++);
+
+      pScr1 -= 3U;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8));
+    pOut += inc;
+    *pOut = (q7_t) (__SSAT(acc1 >> 7U, 8));
+    pOut += inc;
+    *pOut = (q7_t) (__SSAT(acc2 >> 7U, 8));
+    pOut += inc;
+    *pOut = (q7_t) (__SSAT(acc3 >> 7U, 8));
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 4U;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+  /* Calculate correlation for remaining samples of Bigger length sequence */
+  while (blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1U;
+
+    while (tapCnt > 0U)
+    {
+      acc0 += (*pScr1++ * *pScr2++);
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1U;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while (tapCnt > 0U)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8));
+
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 1U;
+
+  }
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c
new file mode 100644
index 0000000..fdff6db
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c
@@ -0,0 +1,707 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_correlate_q15.c
+ * Description:  Correlation of Q15 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0U, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2U * srcALen) - 1U;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB
+     * to make their lengths equal.
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally
+   * divided into three parts according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first part of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second part of the algorithm, srcBLen number of multiplications are done.
+   * In the third part of the algorithm, the multiplications decrease by one
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+   * ....
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1U);
+  py = pSrc1;
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+  /* -------------------
+   * Stage2 process
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px + 1);
+      px += 2U;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:
+         * y[0] and y[1] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLALD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLALD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px + 1);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLALD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLALD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLALD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLALD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px + 2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px + 3);
+
+        px += 4U;
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLALD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLALD(x1, c0, acc3);
+
+      } while (--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      if (k == 1U)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+        px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if (k == 2U)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+        px += 2U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+      }
+
+      if (k == 3U)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py)++;
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+
+        c0 = (*py);
+
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16U;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[10] */
+        x3 = _SIMD32_OFFSET(px + 2);
+        px += 3U;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
+      pOut += inc;
+
+      /* Increment the count by 4 as 4 output values are computed */
+      count += 4U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment count by 1, as one output value is computed */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * ....
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+   * sum +=  x[srcALen-1] * y[0]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1U;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q15_t *pIn2 = pSrcB + (srcBLen - 1U);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0U, j;                            /* loop counters */
+  uint32_t inv = 0U;                             /* Reverse order flag */
+  uint32_t tot = 0U;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two
+   * inputs of same length. But to improve the performance, we include zeroes
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2U);
+
+  if (srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if (srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1U);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0U; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0U; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if ((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if (inv == 1)
+      *pDst-- = (q15_t) __SSAT((sum >> 15U), 16U);
+    else
+      *pDst++ = (q15_t) __SSAT((sum >> 15U), 16U);
+  }
+
+#endif /* #if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c
new file mode 100644
index 0000000..f2e946a
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c
@@ -0,0 +1,653 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_correlate_q31.c
+ * Description:  Correlation of Q31 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2;                   /* Accumulators                  */
+  q31_t x0, x1, x2, c0;                          /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0U, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2U * srcALen) - 1U;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB
+     * to make their lengths equal.
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally
+   * divided into three parts according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first part of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second part of the algorithm, srcBLen number of multiplications are done.
+   * In the third part of the algorithm, the multiplications decrease by one
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+   * ....
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1U);
+  py = pSrc1;
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[1] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[3] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+  /* -------------------
+   * Stage2 process
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4 */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll by 3 */
+    blkCnt = blockSize2 / 3;
+
+    while (blkCnt > 0U)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+
+      /* Apply loop unrolling and compute 3 MACs simultaneously. */
+      k = srcBLen / 3;
+
+      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py);
+
+        /* Read x[2] sample */
+        x2 = *(px);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Read y[1] sample */
+        c0 = *(py + 1U);
+
+        /* Read x[3] sample */
+        x0 = *(px + 1U);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += ((q63_t) x0 * c0);
+
+        /* Read y[2] sample */
+        c0 = *(py + 2U);
+
+        /* Read x[4] sample */
+        x1 = *(px + 2U);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += ((q63_t) x1 * c0);
+
+        /* update scratch pointers */
+        px += 3U;
+        py += 3U;
+
+      } while (--k);
+
+      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen - (3 * (srcBLen / 3));
+
+      while (k > 0U)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 >> 31);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 >> 31);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 3 */
+      count += 3U;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * ....
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+   * sum +=  x[srcALen-1] * y[0]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1U;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1U));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q31_t *pIn2 = pSrcB + (srcBLen - 1U);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0U, j;                            /* loop counters */
+  uint32_t inv = 0U;                             /* Reverse order flag */
+  uint32_t tot = 0U;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two
+   * inputs of same length. But to improve the performance, we include zeroes
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted
+   * using correlation but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2U);
+
+  if (srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if (srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1U);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate correlation for output length number of times */
+  for (i = 0U; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to correlation equation */
+    for (j = 0U; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if ((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if (inv == 1)
+      *pDst-- = (q31_t) (sum >> 31U);
+    else
+      *pDst++ = (q31_t) (sum >> 31U);
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c
new file mode 100644
index 0000000..f8b1df5
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c
@@ -0,0 +1,778 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_correlate_q7.c
+ * Description:  Correlation of Q7 sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
+ *
+ * \par
+ * Refer the function arm_correlate_opt_q7() for a faster implementation of this function.
+ *
+ */
+
+void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer               */
+  q7_t *pIn2;                                    /* inputB pointer               */
+  q7_t *pOut = pDst;                             /* output pointer               */
+  q7_t *px;                                      /* Intermediate inputA pointer  */
+  q7_t *py;                                      /* Intermediate inputB pointer  */
+  q7_t *pSrc1;                                   /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t input1, input2;                          /* temporary variables */
+  q15_t in1, in2;                                /* temporary variables */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0U, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if (srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2U * srcALen) - 1U;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB
+     * to make their lengths equal.
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally
+   * divided into three parts according to the number of multiplications that has to be
+   * taken place between inputA samples and inputB samples. In the first part of the
+   * algorithm, the multiplications increase by one for every iteration.
+   * In the second part of the algorithm, srcBLen number of multiplications are done.
+   * In the third part of the algorithm, the multiplications decrease by one
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1U;
+  blockSize2 = srcALen - (srcBLen - 1U);
+  blockSize3 = blockSize1;
+
+  /* --------------------------
+   * Initializations of stage1
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+   * ....
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = 1U;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1U);
+  py = pSrc1;
+
+  /* ------------------------
+   * Stage1 process
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while (blockSize1 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 4] , y[srcBLen - 3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[0] * y[srcBLen - 4] */
+      /* x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 2] , y[srcBLen - 1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[2] * y[srcBLen - 2] */
+      /* x[3] * y[srcBLen - 1] */
+      sum = __SMLAD(input1, input2, sum);
+
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q31_t) ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------
+   * Initializations of stage2
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+   * ....
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0U;
+
+  /* -------------------
+   * Stage2 process
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+   * So, to loop unroll over blockSize2,
+   * srcBLen should be greater than or equal to 4 */
+  if (srcBLen >= 4U)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *px++;
+      x1 = *px++;
+      x2 = *px++;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *py++;
+        /* Read y[1] sample */
+        c1 = *py++;
+
+        /* Read x[3] sample */
+        x3 = *px++;
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[0] and y[1] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[0] * y[0] + x[1] * y[1]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[2] * y[0] + x[3] * y[1]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[3] * y[0] + x[4] * y[1]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[2] sample */
+        c0 = *py++;
+        /* Read y[3] sample */
+        c1 = *py++;
+
+        /* Read x[5] sample */
+        x1 = *px++;
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[2] and y[3] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[2] * y[2] + x[3] * y[3]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[3] * y[2] + x[4] * y[3]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[4] * y[2] + x[5] * y[3]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *px++;
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[5] * y[2] + x[6] * y[3]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while (--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Read y[4] sample */
+        c0 = *py++;
+
+        /* Read x[7] sample */
+        x3 = *px++;
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
+      pOut += inc;
+
+	  count += 4U;
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2U;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while (k > 0U)
+      {
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4U;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+	  count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while (blkCnt > 0U)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while (k > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------
+   * Initializations of stage3
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+   * ....
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+   * sum +=  x[srcALen-1] * y[0]
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1U;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1U));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------
+   * Stage3 process
+   * ------------------*/
+
+  while (blockSize3 > 0U)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while (k > 0U)
+    {
+      /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2]  */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[0] , y[1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[2] , y[3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.
+     ** No loop unrolling is used. */
+    k = count % 0x4U;
+
+    while (k > 0U)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB + (srcBLen - 1U);           /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i = 0U, j;                            /* loop counters */
+  uint32_t inv = 0U;                             /* Reverse order flag */
+  uint32_t tot = 0U;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two
+   * inputs of same length. But to improve the performance, we include zeroes
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2U);
+
+  if (srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if (srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1U);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0U; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0U; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if ((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if (inv == 1)
+      *pDst-- = (q7_t) __SSAT((sum >> 7U), 8U);
+    else
+      *pDst++ = (q7_t) __SSAT((sum >> 7U), 8U);
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c
new file mode 100644
index 0000000..fd8e237
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c
@@ -0,0 +1,512 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_decimate_f32.c
+ * Description:  FIR decimation for floating-point sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator
+ *
+ * These functions combine an FIR filter together with a decimator.
+ * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.
+ * Conceptually, the functions are equivalent to the block diagram below:
+ * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"
+ * When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized
+ * cutoff frequency of 1/M in order to prevent aliasing distortion.
+ * The user of the function is responsible for providing the filter coefficients.
+ *
+ * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.
+ * Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the
+ * samples output by the decimator are computed.
+ * The functions operate on blocks of input and output data.
+ * pSrc points to an array of blockSize input values and
+ * pDst points to an array of blockSize/M output values.
+ * In order to have an integer number of output samples blockSize
+ * must always be a multiple of the decimation factor M.
+ *
+ * The library provides separate functions for Q15, Q31 and floating-point data types.
+ *
+ * \par Algorithm:
+ * The FIR portion of the algorithm uses the standard form filter:
+ * 
+ *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ * 

+ * where, b[n] are the filter coefficients.
+ * \par
+ * The pCoeffs points to a coefficient array of size numTaps.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * \par
+ * pState points to a state array of size numTaps + blockSize - 1.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * 
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ * 

+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * - Checks to make sure that the size of the input is a multiple of the decimation factor.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * 
+ *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};
+ *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};
+ *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};
+ * 

+ * where M is the decimation factor; numTaps is the number of filter coefficients in the filter;
+ * pCoeffs is the address of the coefficient buffer;
+ * pState is the address of the state buffer.
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S        points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t sum0;                                /* Accumulator */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+#if defined (ARM_MATH_DSP)
+
+  uint32_t blkCntN4;
+  float32_t *px0, *px1, *px2, *px3;
+  float32_t acc0, acc1, acc2, acc3;
+  float32_t x1, x2, x3;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1U);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 4;
+  blkCntN4 = outBlockSize - (4 * blkCnt);
+
+  while (blkCnt > 0U)
+  {
+    /* Copy 4 * decimation factor number of new input samples into the state buffer */
+    i = 4 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /* Set accumulators to zero */
+    acc0 = 0.0f;
+    acc1 = 0.0f;
+    acc2 = 0.0f;
+    acc3 = 0.0f;
+
+    /* Initialize state pointer for all the samples */
+    px0 = pState;
+    px1 = pState + S->M;
+    px2 = pState + 2 * S->M;
+    px3 = pState + 3 * S->M;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+
+    while (tapCnt > 0U)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample for acc0 */
+      x0 = *(px0++);
+      /* Read x[n-numTaps-1] sample for acc1 */
+      x1 = *(px1++);
+      /* Read x[n-numTaps-1] sample for acc2 */
+      x2 = *(px2++);
+      /* Read x[n-numTaps-1] sample for acc3 */
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch  state variables for acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + 4 * S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = acc0;
+    *pDst++ = acc1;
+    *pDst++ = acc2;
+    *pDst++ = acc3;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while (blkCntN4 > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCntN4--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1U) >> 2;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1U) % 0x04U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1U);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1U);
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP)        */
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
new file mode 100644
index 0000000..684640e
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
@@ -0,0 +1,586 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_decimate_fast_q15.c
+ * Description:  Fast Q15 FIR Decimator
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *	In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
+ *
+ * \par
+ * Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ * Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_fir_decimate_init_q15() to initialize the filter structure.
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */
+  q31_t sum0;                                    /* Accumulators */
+  q31_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1U);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+  while (blkCnt > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLAD(x0, c0, acc0);
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+
+  while (blkCntN3 > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c1 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c1, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1U) % 0x04U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+#else
+
+
+void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */
+  q31_t sum0;                                    /* Accumulators */
+  q31_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1U);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+  while (blkCnt > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-3]  coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while (blkCntN3 > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] and sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] and  sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3]  coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1U) % 0x04U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
new file mode 100644
index 0000000..46b7d3d
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
@@ -0,0 +1,339 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_decimate_fast_q31.c
+ * Description:  Fast Q31 FIR Decimator
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
+ *
+ * \par
+ * Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
+ * Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_fir_decimate_init_q31() to initialize the filter structure.
+ */
+
+void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q31_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+  uint32_t blkCntN2;
+  q31_t x1;
+  q31_t acc0, acc1;
+  q31_t *px0, *px1;
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1U);
+
+  /* Total number of output samples to be computed */
+
+  blkCnt = outBlockSize / 2;
+  blkCntN2 = outBlockSize - (2 * blkCnt);
+
+  while (blkCnt > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+    px1 = pState + S->M;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb);
+
+      /* Read x[n-numTaps-1] for sample 0 sample 1 */
+      x0 = *(px0);
+      x1 = *(px1);
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb + 1U);
+
+      /* Read x[n-numTaps-2]  for sample 0 sample 1  */
+      x0 = *(px0 + 1U);
+      x1 = *(px1 + 1U);
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb + 2U);
+
+      /* Read x[n-numTaps-3]  for sample 0 sample 1 */
+      x0 = *(px0 + 2U);
+      x1 = *(px1 + 2U);
+      pb += 4U;
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb - 1U);
+
+      /* Read x[n-numTaps-4] for sample 0 sample 1 */
+      x0 = *(px0 + 3U);
+      x1 = *(px1 + 3U);
+
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* update state pointers */
+      px0 += 4U;
+      px1 += 4U;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px0++);
+      x1 = *(px1++);
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+    *pDst++ = (q31_t) (acc1 << 1);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while (blkCntN2 > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 << 1);
+
+    /* Decrement the loop counter */
+    blkCntN2--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1U) % 0x04U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
new file mode 100644
index 0000000..45797dc
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
@@ -0,0 +1,105 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_decimate_init_f32.c
+ * Description:  Floating-point FIR Decimator initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps  number of coefficients in the filter.
+ * @param[in] M  decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32().
+ * M is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if ((blockSize % M) != 0U)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear state buffer and size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation Factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
new file mode 100644
index 0000000..7314711
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_decimate_init_q15.c
+ * Description:  Initialization function for the Q15 FIR Decimator
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps  number of coefficients in the filter.
+ * @param[in] M  decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples
+ * to the call arm_fir_decimate_q15().
+ * M is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if ((blockSize % M) != 0U)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size of buffer is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
new file mode 100644
index 0000000..f6f3fb2
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
@@ -0,0 +1,105 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_decimate_init_q31.c
+ * Description:  Initialization function for Q31 FIR Decimation filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps  number of coefficients in the filter.
+ * @param[in] M  decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31().
+ * M is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if ((blockSize % M) != 0U)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c
new file mode 100644
index 0000000..56f12fb
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c
@@ -0,0 +1,684 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_decimate_q15.c
+ * Description:  Q15 FIR Decimator
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+#if defined (ARM_MATH_DSP)
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  q63_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1U);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+  while (blkCnt > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLALD(x0, c0, acc0);
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+
+  while (blkCntN3 > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c1 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c1, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1U) % 0x04U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+#else
+
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  q63_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1U);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+  while (blkCnt > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while (blkCntN3 > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] and sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] and  sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3]  coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1U) % 0x04U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#else
+
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1U);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q31_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /*Store filter output , smlad will return the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+}
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c
new file mode 100644
index 0000000..6a13cb5
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c
@@ -0,0 +1,299 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_decimate_q31.c
+ * Description:  Q31 FIR Decimator
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ *
+ * \par
+ * Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q63_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1U);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while (tapCnt > 0U)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1U) % 0x04U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1U);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while (--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c
new file mode 100644
index 0000000..812f9df
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c
@@ -0,0 +1,985 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_f32.c
+ * Description:  Floating-point FIR filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup FIR Finite Impulse Response (FIR) Filters
+*
+* This set of functions implements Finite Impulse Response (FIR) filters
+* for Q7, Q15, Q31, and floating-point data types.  Fast versions of Q15 and Q31 are also provided.
+* The functions operate on blocks of input and output data and each call to the function processes
+* blockSize samples through the filter.  pSrc and
+* pDst points to input and output arrays containing blockSize values.
+*
+* \par Algorithm:
+* The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.
+* Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n].
+* 
+*    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+* 

+* \par
+* \image html FIR.gif "Finite Impulse Response filter"
+* \par
+* pCoeffs points to a coefficient array of size numTaps.
+* Coefficients are stored in time reversed order.
+* \par
+* 
+*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+* 

+* \par
+* pState points to a state array of size numTaps + blockSize - 1.
+* Samples in the state buffer are stored in the following order.
+* \par
+* 
+*    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+* 

+* \par
+* Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1.
+* The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,
+* to be avoided and yields a significant speed improvement.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+* There are separate instance structure declarations for each of the 4 supported data types.
+*
+* \par Initialization Functions
+* There is also an associated initialization function for each data type.
+* The initialization function performs the following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numTaps, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* The code below statically initializes each of the 4 different data type filter instance structures
+* 
+*arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};
+* 

+*
+* where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;
+* pCoeffs is the address of the coefficient buffer.
+*
+* \par Fixed-Point Behavior
+* Care must be taken when using the fixed-point versions of the FIR filter functions.
+* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+* Refer to the function specific documentation below for usage guidelines.
+*/
+
+/**
+* @addtogroup FIR
+* @{
+*/
+
+/**
+*
+* @param[in]  *S points to an instance of the floating-point FIR filter structure.
+* @param[in]  *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data.
+* @param[in]  blockSize number of samples to process per call.
+* @return     none.
+*
+*/
+
+#if defined(ARM_MATH_CM7)
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+   float32_t *pState = S->pState;                 /* State pointer */
+   float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+   float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+   float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+   float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;     /* Accumulators */
+   float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0;  /* Temporary variables to hold state and coefficient values */
+   uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+   uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+   /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+   /* pStateCurnt points to the location where the new input data should be written */
+   pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+   /* Apply loop unrolling and compute 8 output values simultaneously.
+    * The variables acc0 ... acc7 hold output values that are being computed:
+    *
+    *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+    *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+    *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+    *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]
+    */
+   blkCnt = blockSize >> 3;
+
+   /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.
+   ** a second loop below computes the remaining 1 to 7 samples. */
+   while (blkCnt > 0U)
+   {
+      /* Copy four new input samples into the state buffer */
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+      acc4 = 0.0f;
+      acc5 = 0.0f;
+      acc6 = 0.0f;
+      acc7 = 0.0f;
+
+      /* Initialize state pointer */
+      px = pState;
+
+      /* Initialize coeff pointer */
+      pb = (pCoeffs);
+
+      /* This is separated from the others to avoid
+       * a call to __aeabi_memmove which would be slower
+       */
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+
+      /* Read the first seven samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+      x0 = *px++;
+      x1 = *px++;
+      x2 = *px++;
+      x3 = *px++;
+      x4 = *px++;
+      x5 = *px++;
+      x6 = *px++;
+
+      /* Loop unrolling.  Process 8 taps at a time. */
+      tapCnt = numTaps >> 3U;
+
+      /* Loop over the number of taps.  Unroll by a factor of 8.
+       ** Repeat until we've computed numTaps-8 coefficients. */
+      while (tapCnt > 0U)
+      {
+         /* Read the b[numTaps-1] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-3] sample */
+         x7 = *(px++);
+
+         /* acc0 +=  b[numTaps-1] * x[n-numTaps] */
+         acc0 += x0 * c0;
+
+         /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */
+         acc1 += x1 * c0;
+
+         /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */
+         acc2 += x2 * c0;
+
+         /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */
+         acc3 += x3 * c0;
+
+         /* acc4 +=  b[numTaps-1] * x[n-numTaps-4] */
+         acc4 += x4 * c0;
+
+         /* acc1 +=  b[numTaps-1] * x[n-numTaps-5] */
+         acc5 += x5 * c0;
+
+         /* acc2 +=  b[numTaps-1] * x[n-numTaps-6] */
+         acc6 += x6 * c0;
+
+         /* acc3 +=  b[numTaps-1] * x[n-numTaps-7] */
+         acc7 += x7 * c0;
+
+         /* Read the b[numTaps-2] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-4] sample */
+         x0 = *(px++);
+
+         /* Perform the multiply-accumulate */
+         acc0 += x1 * c0;
+         acc1 += x2 * c0;
+         acc2 += x3 * c0;
+         acc3 += x4 * c0;
+         acc4 += x5 * c0;
+         acc5 += x6 * c0;
+         acc6 += x7 * c0;
+         acc7 += x0 * c0;
+
+         /* Read the b[numTaps-3] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-5] sample */
+         x1 = *(px++);
+
+         /* Perform the multiply-accumulates */
+         acc0 += x2 * c0;
+         acc1 += x3 * c0;
+         acc2 += x4 * c0;
+         acc3 += x5 * c0;
+         acc4 += x6 * c0;
+         acc5 += x7 * c0;
+         acc6 += x0 * c0;
+         acc7 += x1 * c0;
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x2 = *(px++);
+
+         /* Perform the multiply-accumulates */
+         acc0 += x3 * c0;
+         acc1 += x4 * c0;
+         acc2 += x5 * c0;
+         acc3 += x6 * c0;
+         acc4 += x7 * c0;
+         acc5 += x0 * c0;
+         acc6 += x1 * c0;
+         acc7 += x2 * c0;
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x3 = *(px++);
+         /* Perform the multiply-accumulates */
+         acc0 += x4 * c0;
+         acc1 += x5 * c0;
+         acc2 += x6 * c0;
+         acc3 += x7 * c0;
+         acc4 += x0 * c0;
+         acc5 += x1 * c0;
+         acc6 += x2 * c0;
+         acc7 += x3 * c0;
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x4 = *(px++);
+
+         /* Perform the multiply-accumulates */
+         acc0 += x5 * c0;
+         acc1 += x6 * c0;
+         acc2 += x7 * c0;
+         acc3 += x0 * c0;
+         acc4 += x1 * c0;
+         acc5 += x2 * c0;
+         acc6 += x3 * c0;
+         acc7 += x4 * c0;
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x5 = *(px++);
+
+         /* Perform the multiply-accumulates */
+         acc0 += x6 * c0;
+         acc1 += x7 * c0;
+         acc2 += x0 * c0;
+         acc3 += x1 * c0;
+         acc4 += x2 * c0;
+         acc5 += x3 * c0;
+         acc6 += x4 * c0;
+         acc7 += x5 * c0;
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x6 = *(px++);
+
+         /* Perform the multiply-accumulates */
+         acc0 += x7 * c0;
+         acc1 += x0 * c0;
+         acc2 += x1 * c0;
+         acc3 += x2 * c0;
+         acc4 += x3 * c0;
+         acc5 += x4 * c0;
+         acc6 += x5 * c0;
+         acc7 += x6 * c0;
+
+         tapCnt--;
+      }
+
+      /* If the filter length is not a multiple of 8, compute the remaining filter taps */
+      tapCnt = numTaps % 0x8U;
+
+      while (tapCnt > 0U)
+      {
+         /* Read coefficients */
+         c0 = *(pb++);
+
+         /* Fetch 1 state variable */
+         x7 = *(px++);
+
+         /* Perform the multiply-accumulates */
+         acc0 += x0 * c0;
+         acc1 += x1 * c0;
+         acc2 += x2 * c0;
+         acc3 += x3 * c0;
+         acc4 += x4 * c0;
+         acc5 += x5 * c0;
+         acc6 += x6 * c0;
+         acc7 += x7 * c0;
+
+         /* Reuse the present sample states for next sample */
+         x0 = x1;
+         x1 = x2;
+         x2 = x3;
+         x3 = x4;
+         x4 = x5;
+         x5 = x6;
+         x6 = x7;
+
+         /* Decrement the loop counter */
+         tapCnt--;
+      }
+
+      /* Advance the state pointer by 8 to process the next group of 8 samples */
+      pState = pState + 8;
+
+      /* The results in the 8 accumulators, store in the destination buffer. */
+      *pDst++ = acc0;
+      *pDst++ = acc1;
+      *pDst++ = acc2;
+      *pDst++ = acc3;
+      *pDst++ = acc4;
+      *pDst++ = acc5;
+      *pDst++ = acc6;
+      *pDst++ = acc7;
+
+      blkCnt--;
+   }
+
+   /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+   blkCnt = blockSize % 0x8U;
+
+   while (blkCnt > 0U)
+   {
+      /* Copy one sample at a time into state buffer */
+      *pStateCurnt++ = *pSrc++;
+
+      /* Set the accumulator to zero */
+      acc0 = 0.0f;
+
+      /* Initialize state pointer */
+      px = pState;
+
+      /* Initialize Coefficient pointer */
+      pb = (pCoeffs);
+
+      i = numTaps;
+
+      /* Perform the multiply-accumulates */
+      do
+      {
+         acc0 += *px++ * *pb++;
+         i--;
+
+      } while (i > 0U);
+
+      /* The result is store in the destination buffer. */
+      *pDst++ = acc0;
+
+      /* Advance state pointer by 1 for the next sample */
+      pState = pState + 1;
+
+      blkCnt--;
+   }
+
+   /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+   /* Points to the start of the state buffer */
+   pStateCurnt = S->pState;
+
+   tapCnt = (numTaps - 1U) >> 2U;
+
+   /* copy data */
+   while (tapCnt > 0U)
+   {
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+   }
+
+   /* Calculate remaining number of copies */
+   tapCnt = (numTaps - 1U) % 0x4U;
+
+   /* Copy the remaining q31_t data */
+   while (tapCnt > 0U)
+   {
+      *pStateCurnt++ = *pState++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+   }
+}
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+   float32_t *pState = S->pState;                 /* State pointer */
+   float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+   float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+   float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+   uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+   uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+   /* Run the below code for Cortex-M0 */
+
+   float32_t acc;
+
+   /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+   /* pStateCurnt points to the location where the new input data should be written */
+   pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+   /* Initialize blkCnt with blockSize */
+   blkCnt = blockSize;
+
+   while (blkCnt > 0U)
+   {
+      /* Copy one sample at a time into state buffer */
+      *pStateCurnt++ = *pSrc++;
+
+      /* Set the accumulator to zero */
+      acc = 0.0f;
+
+      /* Initialize state pointer */
+      px = pState;
+
+      /* Initialize Coefficient pointer */
+      pb = pCoeffs;
+
+      i = numTaps;
+
+      /* Perform the multiply-accumulates */
+      do
+      {
+         /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+         acc += *px++ * *pb++;
+         i--;
+
+      } while (i > 0U);
+
+      /* The result is store in the destination buffer. */
+      *pDst++ = acc;
+
+      /* Advance state pointer by 1 for the next sample */
+      pState = pState + 1;
+
+      blkCnt--;
+   }
+
+   /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+   /* Points to the start of the state buffer */
+   pStateCurnt = S->pState;
+
+   /* Copy numTaps number of values */
+   tapCnt = numTaps - 1U;
+
+   /* Copy data */
+   while (tapCnt > 0U)
+   {
+      *pStateCurnt++ = *pState++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+   }
+
+}
+
+#else
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+   float32_t *pState = S->pState;                 /* State pointer */
+   float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+   float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+   float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+   float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;     /* Accumulators */
+   float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0;  /* Temporary variables to hold state and coefficient values */
+   uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+   uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+   float32_t p0,p1,p2,p3,p4,p5,p6,p7;             /* Temporary product values */
+
+   /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+   /* pStateCurnt points to the location where the new input data should be written */
+   pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+   /* Apply loop unrolling and compute 8 output values simultaneously.
+    * The variables acc0 ... acc7 hold output values that are being computed:
+    *
+    *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+    *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+    *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+    *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]
+    */
+   blkCnt = blockSize >> 3;
+
+   /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.
+   ** a second loop below computes the remaining 1 to 7 samples. */
+   while (blkCnt > 0U)
+   {
+      /* Copy four new input samples into the state buffer */
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+      acc4 = 0.0f;
+      acc5 = 0.0f;
+      acc6 = 0.0f;
+      acc7 = 0.0f;
+
+      /* Initialize state pointer */
+      px = pState;
+
+      /* Initialize coeff pointer */
+      pb = (pCoeffs);
+
+      /* This is separated from the others to avoid
+       * a call to __aeabi_memmove which would be slower
+       */
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+      *pStateCurnt++ = *pSrc++;
+
+      /* Read the first seven samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+      x0 = *px++;
+      x1 = *px++;
+      x2 = *px++;
+      x3 = *px++;
+      x4 = *px++;
+      x5 = *px++;
+      x6 = *px++;
+
+      /* Loop unrolling.  Process 8 taps at a time. */
+      tapCnt = numTaps >> 3U;
+
+      /* Loop over the number of taps.  Unroll by a factor of 8.
+       ** Repeat until we've computed numTaps-8 coefficients. */
+      while (tapCnt > 0U)
+      {
+         /* Read the b[numTaps-1] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-3] sample */
+         x7 = *(px++);
+
+         /* acc0 +=  b[numTaps-1] * x[n-numTaps] */
+         p0 = x0 * c0;
+
+         /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */
+         p1 = x1 * c0;
+
+         /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */
+         p2 = x2 * c0;
+
+         /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */
+         p3 = x3 * c0;
+
+         /* acc4 +=  b[numTaps-1] * x[n-numTaps-4] */
+         p4 = x4 * c0;
+
+         /* acc1 +=  b[numTaps-1] * x[n-numTaps-5] */
+         p5 = x5 * c0;
+
+         /* acc2 +=  b[numTaps-1] * x[n-numTaps-6] */
+         p6 = x6 * c0;
+
+         /* acc3 +=  b[numTaps-1] * x[n-numTaps-7] */
+         p7 = x7 * c0;
+
+         /* Read the b[numTaps-2] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-4] sample */
+         x0 = *(px++);
+
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+
+         /* Perform the multiply-accumulate */
+         p0 = x1 * c0;
+         p1 = x2 * c0;
+         p2 = x3 * c0;
+         p3 = x4 * c0;
+         p4 = x5 * c0;
+         p5 = x6 * c0;
+         p6 = x7 * c0;
+         p7 = x0 * c0;
+
+         /* Read the b[numTaps-3] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-5] sample */
+         x1 = *(px++);
+
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */
+         p0 = x2 * c0;
+         p1 = x3 * c0;
+         p2 = x4 * c0;
+         p3 = x5 * c0;
+         p4 = x6 * c0;
+         p5 = x7 * c0;
+         p6 = x0 * c0;
+         p7 = x1 * c0;
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x2 = *(px++);
+
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */
+         p0 = x3 * c0;
+         p1 = x4 * c0;
+         p2 = x5 * c0;
+         p3 = x6 * c0;
+         p4 = x7 * c0;
+         p5 = x0 * c0;
+         p6 = x1 * c0;
+         p7 = x2 * c0;
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x3 = *(px++);
+
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */
+         p0 = x4 * c0;
+         p1 = x5 * c0;
+         p2 = x6 * c0;
+         p3 = x7 * c0;
+         p4 = x0 * c0;
+         p5 = x1 * c0;
+         p6 = x2 * c0;
+         p7 = x3 * c0;
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x4 = *(px++);
+
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */
+         p0 = x5 * c0;
+         p1 = x6 * c0;
+         p2 = x7 * c0;
+         p3 = x0 * c0;
+         p4 = x1 * c0;
+         p5 = x2 * c0;
+         p6 = x3 * c0;
+         p7 = x4 * c0;
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x5 = *(px++);
+
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */
+         p0 = x6 * c0;
+         p1 = x7 * c0;
+         p2 = x0 * c0;
+         p3 = x1 * c0;
+         p4 = x2 * c0;
+         p5 = x3 * c0;
+         p6 = x4 * c0;
+         p7 = x5 * c0;
+
+         /* Read the b[numTaps-4] coefficient */
+         c0 = *(pb++);
+
+         /* Read x[n-numTaps-6] sample */
+         x6 = *(px++);
+
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Perform the multiply-accumulates */
+         p0 = x7 * c0;
+         p1 = x0 * c0;
+         p2 = x1 * c0;
+         p3 = x2 * c0;
+         p4 = x3 * c0;
+         p5 = x4 * c0;
+         p6 = x5 * c0;
+         p7 = x6 * c0;
+
+         tapCnt--;
+
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+      }
+
+      /* If the filter length is not a multiple of 8, compute the remaining filter taps */
+      tapCnt = numTaps % 0x8U;
+
+      while (tapCnt > 0U)
+      {
+         /* Read coefficients */
+         c0 = *(pb++);
+
+         /* Fetch 1 state variable */
+         x7 = *(px++);
+
+         /* Perform the multiply-accumulates */
+         p0 = x0 * c0;
+         p1 = x1 * c0;
+         p2 = x2 * c0;
+         p3 = x3 * c0;
+         p4 = x4 * c0;
+         p5 = x5 * c0;
+         p6 = x6 * c0;
+         p7 = x7 * c0;
+
+         /* Reuse the present sample states for next sample */
+         x0 = x1;
+         x1 = x2;
+         x2 = x3;
+         x3 = x4;
+         x4 = x5;
+         x5 = x6;
+         x6 = x7;
+
+         acc0 += p0;
+         acc1 += p1;
+         acc2 += p2;
+         acc3 += p3;
+         acc4 += p4;
+         acc5 += p5;
+         acc6 += p6;
+         acc7 += p7;
+
+         /* Decrement the loop counter */
+         tapCnt--;
+      }
+
+      /* Advance the state pointer by 8 to process the next group of 8 samples */
+      pState = pState + 8;
+
+      /* The results in the 8 accumulators, store in the destination buffer. */
+      *pDst++ = acc0;
+      *pDst++ = acc1;
+      *pDst++ = acc2;
+      *pDst++ = acc3;
+      *pDst++ = acc4;
+      *pDst++ = acc5;
+      *pDst++ = acc6;
+      *pDst++ = acc7;
+
+      blkCnt--;
+   }
+
+   /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+   blkCnt = blockSize % 0x8U;
+
+   while (blkCnt > 0U)
+   {
+      /* Copy one sample at a time into state buffer */
+      *pStateCurnt++ = *pSrc++;
+
+      /* Set the accumulator to zero */
+      acc0 = 0.0f;
+
+      /* Initialize state pointer */
+      px = pState;
+
+      /* Initialize Coefficient pointer */
+      pb = (pCoeffs);
+
+      i = numTaps;
+
+      /* Perform the multiply-accumulates */
+      do
+      {
+         acc0 += *px++ * *pb++;
+         i--;
+
+      } while (i > 0U);
+
+      /* The result is store in the destination buffer. */
+      *pDst++ = acc0;
+
+      /* Advance state pointer by 1 for the next sample */
+      pState = pState + 1;
+
+      blkCnt--;
+   }
+
+   /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+   /* Points to the start of the state buffer */
+   pStateCurnt = S->pState;
+
+   tapCnt = (numTaps - 1U) >> 2U;
+
+   /* copy data */
+   while (tapCnt > 0U)
+   {
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+      *pStateCurnt++ = *pState++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+   }
+
+   /* Calculate remaining number of copies */
+   tapCnt = (numTaps - 1U) % 0x4U;
+
+   /* Copy the remaining q31_t data */
+   while (tapCnt > 0U)
+   {
+      *pStateCurnt++ = *pState++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+   }
+}
+
+#endif
+
+/**
+* @} end of FIR group
+*/
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c
new file mode 100644
index 0000000..35e431b
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c
@@ -0,0 +1,333 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_fast_q15.c
+ * Description:  Q15 Fast FIR filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
+ *
+ * \par
+ * Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_fir_init_q15() to initialize the filter structure.
+ */
+
+void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.
+   * The variables acc0 ... acc3 hold output values that are being computed:
+   *
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]
+   */
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* Copy four new input samples into the state buffer.
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+    px = pState;
+
+    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *__SIMD32(px)++;
+
+    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+    x2 = *__SIMD32(px)++;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+    tapCnt = numTaps >> 2;
+
+    while (tapCnt > 0)
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLAD(x2, c0, acc2);
+
+      /* pack  x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = _SIMD32_OFFSET(px);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLADX(x1, c0, acc1);
+
+      /* pack  x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLADX(x1, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLAD(x2, c0, acc0);
+
+      /* Read state x[n-N-6], x[n-N-7] with offset */
+      x2 = _SIMD32_OFFSET(px + 2U);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLAD(x0, c0, acc2);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLADX(x1, c0, acc1);
+
+      /* pack  x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLADX(x1, c0, acc3);
+
+      /* Update state pointer for next state reading */
+      px += 4U;
+
+      /* Decrement tap count */
+      tapCnt--;
+
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+     ** This is always be 2 taps since the filter length is even. */
+    if ((numTaps & 0x3U) != 0U)
+    {
+
+      /* Read last two coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLAD(x0, c0, acc0);
+      acc2 = __SMLAD(x2, c0, acc2);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read last state variables */
+      x0 = *__SIMD32(px);
+
+      /* Perform the multiply-accumulates */
+      acc1 = __SMLADX(x1, c0, acc1);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* Perform the multiply-accumulates */
+      acc3 = __SMLADX(x1, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+  while (blkCnt > 0U)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px = pState;
+    pb = pCoeffs;
+
+    tapCnt = numTaps >> 1U;
+
+    do
+    {
+
+      acc0 += (q31_t) * px++ * *pb++;
+	  acc0 += (q31_t) * px++ * *pb++;
+
+      tapCnt--;
+    }
+    while (tapCnt > 0U);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1U) >> 2;
+
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1U) % 0x4U;
+
+  /* copy remaining data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c
new file mode 100644
index 0000000..bd9c686
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c
@@ -0,0 +1,293 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_fast_q31.c
+ * Description:  Processing function for the Q31 Fast FIR filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q31 structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ *
+ * \par
+ * Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.  Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_fir_init_q31() to initialize the filter structure.
+ */
+
+IAR_ONLY_LOW_OPTIMIZATION_ENTER
+void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.
+   * The variables acc0 ... acc3 hold output values that are being computed:
+   *
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while (i > 0U)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *pb;
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *px;
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      multAcc_32x32_keep32_R(acc0, x0, c0);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      multAcc_32x32_keep32_R(acc1, x1, c0);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      multAcc_32x32_keep32_R(acc2, x2, c0);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      multAcc_32x32_keep32_R(acc3, x3, c0);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb + 1U);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px + 1U);
+
+      /* Perform the multiply-accumulates */
+      multAcc_32x32_keep32_R(acc0, x1, c0);
+      multAcc_32x32_keep32_R(acc1, x2, c0);
+      multAcc_32x32_keep32_R(acc2, x3, c0);
+      multAcc_32x32_keep32_R(acc3, x0, c0);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb + 2U);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px + 2U);
+
+      /* Perform the multiply-accumulates */
+      multAcc_32x32_keep32_R(acc0, x2, c0);
+      multAcc_32x32_keep32_R(acc1, x3, c0);
+      multAcc_32x32_keep32_R(acc2, x0, c0);
+      multAcc_32x32_keep32_R(acc3, x1, c0);
+
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb + 3U);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px + 3U);
+
+      /* Perform the multiply-accumulates */
+      multAcc_32x32_keep32_R(acc0, x3, c0);
+      multAcc_32x32_keep32_R(acc1, x0, c0);
+      multAcc_32x32_keep32_R(acc2, x1, c0);
+      multAcc_32x32_keep32_R(acc3, x2, c0);
+
+      /* update coefficient pointer */
+      pb += 4U;
+      px += 4U;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4U);
+    while (i > 0U)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      multAcc_32x32_keep32_R(acc0, x0, c0);
+      multAcc_32x32_keep32_R(acc1, x1, c0);
+      multAcc_32x32_keep32_R(acc2, x2, c0);
+      multAcc_32x32_keep32_R(acc3, x3, c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.31
+     ** Then store the 4 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+    *pDst++ = (q31_t) (acc1 << 1);
+    *pDst++ = (q31_t) (acc2 << 1);
+    *pDst++ = (q31_t) (acc3 << 1);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4U;
+
+  while (blkCnt > 0U)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      multAcc_32x32_keep32_R(acc0, (*px++), (*(pb++)));
+      i--;
+    } while (i > 0U);
+
+    /* The result is in 2.30 format.  Convert to 1.31
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1U);
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+
+}
+IAR_ONLY_LOW_OPTIMIZATION_EXIT
+/**
+ * @} end of FIR group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c
new file mode 100644
index 0000000..25fcb01
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_init_f32.c
+ * Description:  Floating-point FIR filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.
+ * @param[in]     *pCoeffs points to the filter coefficients buffer.
+ * @param[in]     *pState points to the state buffer.
+ * @param[in] 	  blockSize number of samples that are processed per call.
+ * @return 		  none.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32().
+ */
+
+void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c
new file mode 100644
index 0000000..a5638d5
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_init_q15.c
+ * Description:  Q15 FIR filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in,out]  *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] 	   numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in]      *pCoeffs points to the filter coefficients buffer.
+ * @param[in]      *pState points to the state buffer.
+ * @param[in]      blockSize is number of samples processed per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not greater than or equal to 4 and even.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * Note that numTaps must be even and greater than or equal to 4.
+ * To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero.
+ * For example, to implement a filter with numTaps=3 and coefficients
+ * 
+ *     {0.3, -0.8, 0.3}
+ * 

+ * set numTaps=4 and use the coefficients:
+ * 
+ *     {0.3, -0.8, 0.3, 0}.
+ * 

+ * Similarly, to implement a two point filter
+ * 
+ *     {0.3, -0.3}
+ * 

+ * set numTaps=4 and use the coefficients:
+ * 
+ *     {0.3, -0.3, 0, 0}.
+ * 

+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3  and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15().
+ */
+
+arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* The Number of filter coefficients in the filter must be even and at least 4 */
+  if (numTaps & 0x1U)
+  {
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps ) */
+    memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  status = ARM_MATH_SUCCESS;
+
+  return (status);
+
+#endif /*  #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c
new file mode 100644
index 0000000..2367a65
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_init_q31.c
+ * Description:  Q31 FIR filter initialization function.
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.
+ * @param[in] 	  *pState points to the state buffer.
+ * @param[in] 	  blockSize number of samples that are processed per call.
+ * @return        none.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31().
+ */
+
+void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
+  memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1U)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c
new file mode 100644
index 0000000..5a91fb8
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c
@@ -0,0 +1,82 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_init_q7.c
+ * Description:  Q7 FIR filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+/**
+ * @param[in,out] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.
+ * @param[in]     *pState points to the state buffer.
+ * @param[in]     blockSize number of samples that are processed per call.
+ * @return     	  none
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7().
+ */
+
+void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize)
+{
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c
new file mode 100644
index 0000000..5f9d19c
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c
@@ -0,0 +1,569 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_interpolate_f32.c
+ * Description:  Floating-point FIR interpolation sequences
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator
+ *
+ * These functions combine an upsampler (zero stuffer) and an FIR filter.
+ * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.
+ * Conceptually, the functions are equivalent to the block diagram below:
+ * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"
+ * After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized
+ * cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum.
+ * The user of the function is responsible for providing the filter coefficients.
+ *
+ * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.
+ * The upsampler inserts L-1 zeros between each sample.
+ * Instead of multiplying by these zero values, the FIR filter is designed to skip them.
+ * This leads to an efficient implementation without any wasted effort.
+ * The functions operate on blocks of input and output data.
+ * pSrc points to an array of blockSize input values and
+ * pDst points to an array of blockSize*L output values.
+ *
+ * The library provides separate functions for Q15, Q31, and floating-point data types.
+ *
+ * \par Algorithm:
+ * The functions use a polyphase filter structure:
+ * 
+ *    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]
+ *    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]
+ *    ...
+ *    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]
+ * 

+ * This approach is more efficient than straightforward upsample-then-filter algorithms.
+ * With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter.
+ * \par
+ * pCoeffs points to a coefficient array of size numTaps.
+ * numTaps must be a multiple of the interpolation factor L and this is checked by the
+ * initialization functions.
+ * Internally, the function divides the FIR filter's impulse response into shorter filters of length
+ * phaseLength=numTaps/L.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * \par
+ * pState points to a state array of size blockSize + phaseLength - 1.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * 
+ *    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}
+ * 

+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * 
+ * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};
+ * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};
+ * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};
+ * 

+ * where L is the interpolation factor; phaseLength=numTaps/L is the
+ * length of each of the shorter FIR filters used internally,
+ * pCoeffs is the address of the coefficient buffer;
+ * pState is the address of the state buffer.
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc     points to the block of input data.
+ * @param[out] *pDst    points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
+  float32_t sum0;                                /* Accumulators */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+  float32_t acc0, acc1, acc2, acc3;
+  float32_t x1, x2, x3;
+  uint32_t blkCntN4;
+  float32_t c1, c2, c3;
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1U);
+
+  /* Initialise  blkCnt */
+  blkCnt = blockSize / 4;
+  blkCntN4 = blockSize - (4 * blkCnt);
+
+  /* Samples loop unrolled by 4 */
+  while (blkCnt > 0U)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1U;
+
+    /* Loop over the Interpolation factor. */
+    i = (S->L);
+
+    while (i > 0U)
+    {
+      /* Set accumulator to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2U;
+
+      x0 = *(ptr1++);
+      x1 = *(ptr1++);
+      x2 = *(ptr1++);
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read the input sample */
+        x3 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x0 * c0;
+        acc1 += x1 * c0;
+        acc2 += x2 * c0;
+        acc3 += x3 * c0;
+
+        /* Read the coefficient */
+        c1 = *(ptr2 + S->L);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x1 * c1;
+        acc1 += x2 * c1;
+        acc2 += x3 * c1;
+        acc3 += x0 * c1;
+
+        /* Read the coefficient */
+        c2 = *(ptr2 + S->L * 2);
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x2 * c2;
+        acc1 += x3 * c2;
+        acc2 += x0 * c2;
+        acc3 += x1 * c2;
+
+        /* Read the coefficient */
+        c3 = *(ptr2 + S->L * 3);
+
+        /* Read the input sample */
+        x2 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x3 * c3;
+        acc1 += x0 * c3;
+        acc2 += x1 * c3;
+        acc3 += x2 * c3;
+
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.
+         * So instead of multiplying zeros with coefficients,
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += 4 * S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read the input sample */
+        x3 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x0 * c0;
+        acc1 += x1 * c0;
+        acc2 += x2 * c0;
+        acc3 += x3 * c0;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* update states for next sample processing */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst = acc0;
+      *(pDst + S->L) = acc1;
+      *(pDst + 2 * S->L) = acc2;
+      *(pDst + 3 * S->L) = acc3;
+
+      pDst++;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 4;
+
+    pDst += S->L * 3;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+
+  while (blkCntN4 > 0U)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1U;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while (i > 0U)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2U;
+      while (tapCnt > 0U)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.
+         * So instead of multiplying zeros with coefficients,
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4U;
+
+      while (tapCnt > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum0 += *(ptr1++) * (*ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum0;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCntN4--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1U) >> 2U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1U) % 0x04U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
+
+
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1U);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while (blkCnt > 0U)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while (i > 0U)
+    {
+      /* Set accumulator to zero */
+      sum = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1U);
+
+      /* Loop over the polyPhase length */
+      tapCnt = phaseLen;
+
+      while (tapCnt > 0U)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *ptr1++ * *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1U;
+
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+
+
+ /**
+  * @} end of FIR_Interpolate group
+  */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
new file mode 100644
index 0000000..415c8da
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_interpolate_init_f32.c
+ * Description:  Floating-point FIR interpolator initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+ * @param[in]     L         upsample factor.
+ * @param[in]     numTaps   number of filter coefficients in the filter.
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+ * @param[in]     *pState   points to the state buffer.
+ * @param[in]     blockSize number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ * 

+ * The length of the filter numTaps must be a multiple of the interpolation factor L.
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length (numTaps/L)+blockSize-1 words
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32().
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if ((numTaps % L) != 0U)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize +
+            ((uint32_t) S->phaseLength - 1U)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**
+  * @} end of FIR_Interpolate group
+  */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
new file mode 100644
index 0000000..6dce943
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
@@ -0,0 +1,108 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_interpolate_init_q15.c
+ * Description:  Q15 FIR interpolator initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+ * @param[in]     L         upsample factor.
+ * @param[in]     numTaps   number of filter coefficients in the filter.
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+ * @param[in]     *pState   points to the state buffer.
+ * @param[in]     blockSize number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ * 

+ * The length of the filter numTaps must be a multiple of the interpolation factor L.
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length (numTaps/L)+blockSize-1 words
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15().
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if ((numTaps % L) != 0U)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**
+  * @} end of FIR_Interpolate group
+  */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
new file mode 100644
index 0000000..9875aa8
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_interpolate_init_q31.c
+ * Description:  Q31 FIR interpolator initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+
+/**
+ * @brief  Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+ * @param[in]     L         upsample factor.
+ * @param[in]     numTaps   number of filter coefficients in the filter.
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+ * @param[in]     *pState   points to the state buffer.
+ * @param[in]     blockSize number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ * 

+ * The length of the filter numTaps must be a multiple of the interpolation factor L.
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length (numTaps/L)+blockSize-1 words
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31().
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if ((numTaps % L) != 0U)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**
+  * @} end of FIR_Interpolate group
+  */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c
new file mode 100644
index 0000000..1cedd25
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c
@@ -0,0 +1,496 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_interpolate_q15.c
+ * Description:  Q15 FIR interpolation
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc     points to the block of input data.
+ * @param[out] *pDst    points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer                                            */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
+  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
+  q63_t sum0;                                    /* Accumulators                                             */
+  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j, tapCnt;                 /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+  uint32_t blkCntN2;
+  q63_t acc0, acc1;
+  q15_t x1;
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Initialise  blkCnt */
+  blkCnt = blockSize / 2;
+  blkCntN2 = blockSize - (2 * blkCnt);
+
+  /* Samples loop unrolled by 2 */
+  while (blkCnt > 0U)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1U;
+
+    /* Loop over the Interpolation factor. */
+    i = (S->L);
+
+    while (i > 0U)
+    {
+      /* Set accumulator to zero */
+      acc0 = 0;
+      acc1 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2U;
+
+      x0 = *(ptr1++);
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 2);
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 3);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.
+         * So instead of multiplying zeros with coefficients,
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += 4 * S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* update states for next sample processing */
+        x0 = x1;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst = (q15_t) (__SSAT((acc0 >> 15), 16));
+      *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+      pDst++;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 2;
+
+    pDst += S->L;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blkCntN2;
+
+  /* Loop over the blockSize. */
+  while (blkCnt > 0U)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1U;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while (i > 0U)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2;
+      while (tapCnt > 0U)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.
+         * So instead of multiplying zeros with coefficients,
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen & 0x3U;
+
+      while (tapCnt > 0U)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete.
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = ((uint32_t) phaseLen - 1U) >> 2U;
+
+  /* copy data */
+  while (i > 0U)
+  {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+    *pStateCurnt++ = *pState++;
+	*pStateCurnt++ = *pState++;
+	*pStateCurnt++ = *pState++;
+	*pStateCurnt++ = *pState++;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+	/* Decrement the loop counter */
+    i--;
+  }
+
+  i = ((uint32_t) phaseLen - 1U) % 0x04U;
+
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer                                            */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
+  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
+  q63_t sum;                                     /* Accumulator */
+  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, tapCnt;                    /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1U);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while (blkCnt > 0U)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while (i > 0U)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1U);
+
+      /* Loop over the polyPhase length */
+      tapCnt = (uint32_t) phaseLen;
+
+      while (tapCnt > 0U)
+      {
+        /* Read the coefficient */
+        c0 = *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) x0 * c0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Store the result after converting to 1.15 format in the destination buffer */
+      *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (uint32_t) phaseLen - 1U;
+
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+}
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+
+ /**
+  * @} end of FIR_Interpolate group
+  */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c
new file mode 100644
index 0000000..2c0f522
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c
@@ -0,0 +1,492 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_interpolate_q31.c
+ * Description:  Q31 FIR interpolation
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S        points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] *pSrc     points to the block of input data.
+ * @param[out] *pDst    points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L).
+ * since numTaps/L additions occur per output sample.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
+  q63_t sum0;                                    /* Accumulators */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+  uint32_t blkCntN2;
+  q63_t acc0, acc1;
+  q31_t x1;
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Initialise  blkCnt */
+  blkCnt = blockSize / 2;
+  blkCntN2 = blockSize - (2 * blkCnt);
+
+  /* Samples loop unrolled by 2 */
+  while (blkCnt > 0U)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1U;
+
+    /* Loop over the Interpolation factor. */
+    i = (S->L);
+
+    while (i > 0U)
+    {
+      /* Set accumulator to zero */
+      acc0 = 0;
+      acc1 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2U;
+
+      x0 = *(ptr1++);
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 2);
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 3);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.
+         * So instead of multiplying zeros with coefficients,
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += 4 * S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4U;
+
+      while (tapCnt > 0U)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* update states for next sample processing */
+        x0 = x1;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst = (q31_t) (acc0 >> 31);
+      *(pDst + S->L) = (q31_t) (acc1 >> 31);
+
+
+      pDst++;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 2;
+
+    pDst += S->L;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blkCntN2;
+
+  /* Loop over the blockSize. */
+  while (blkCnt > 0U)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1U;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while (i > 0U)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2;
+      while (tapCnt > 0U)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.
+         * So instead of multiplying zeros with coefficients,
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen & 0x3U;
+
+      while (tapCnt > 0U)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum0 >> 31);
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1U) >> 2U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1U) % 0x04U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+
+#else
+
+void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sum;                                     /* Accumulator */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while (blkCnt > 0U)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while (i > 0U)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1U);
+
+      tapCnt = phaseLen;
+
+      while (tapCnt > 0U)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum >> 31);
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+ /**
+  * @} end of FIR_Interpolate group
+  */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c
new file mode 100644
index 0000000..1b6d0fb
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c
@@ -0,0 +1,494 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_lattice_f32.c
+ * Description:  Processing function for the floating-point FIR Lattice filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters
+ *
+ * This set of functions implements Finite Impulse Response (FIR) lattice filters
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a
+ * variety of adaptive filter applications.  The filter structure is feedforward and
+ * the net impulse response is finite length.
+ * The functions operate on blocks
+ * of input and output data and each call to the function processes
+ * blockSize samples through the filter.  pSrc and
+ * pDst point to input and output arrays containing blockSize values.
+ *
+ * \par Algorithm:
+ * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"
+ * The following difference equation is implemented:
+ * 
+ *    f0[n] = g0[n] = x[n]
+ *    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M
+ *    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M
+ *    y[n] = fM[n]
+ * 

+ * \par
+ * pCoeffs points to tha array of reflection coefficients of size numStages.
+ * Reflection Coefficients are stored in the following order.
+ * \par
+ * 
+ *    {k1, k2, ..., kM}
+ * 

+ * where M is number of stages
+ * \par
+ * pState points to a state array of size numStages.
+ * The state variables (g values) hold previous inputs and are stored in the following order.
+ * 
+ *    {g0[n], g1[n], g2[n] ...gM-1[n]}
+ * 

+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
+ * 
+ *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};
+ *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};
+ *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};
+ * 

+ * \par
+ * where numStages is the number of stages in the filter; pState is the address of the state buffer;
+ * pCoeffs is the address of the coefficient buffer.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState;                             /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* temporary state pointer */
+  float32_t *pk;                                 /* temporary coefficient pointer */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t fcurr1, fnext1, gcurr1, gnext1;      /* temporary variables for first sample in loop unrolling */
+  float32_t fcurr2, fnext2, gnext2;              /* temporary variables for second sample in loop unrolling */
+  float32_t fcurr3, fnext3, gnext3;              /* temporary variables for third sample in loop unrolling */
+  float32_t fcurr4, fnext4, gnext4;              /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  gcurr1 = 0.0f;
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurr1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk)) + gcurr1;
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = fcurr2 + ((*pk) * fcurr1);
+    gnext2 = (fcurr2 * (*pk)) + fcurr1;
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurr3 = *pSrc++;
+    fcurr4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer
+       which will be used for next four samples processing */
+    *px++ = fcurr4;
+
+    /* Process third sample for first tap */
+    fnext3 = fcurr3 + ((*pk) * fcurr2);
+    gnext3 = (fcurr3 * (*pk)) + fcurr2;
+
+    /* Process fourth sample for first tap */
+    fnext4 = fcurr4 + ((*pk) * fcurr3);
+    gnext4 = (fcurr4 * (*pk++)) + fcurr3;
+
+    /* Update of f values for next coefficient set processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+    fcurr3 = fnext3;
+    fcurr4 = fnext4;
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1U) >> 2U;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while (stageCnt > 0U)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g2(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g3(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 5th, 9th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 5th, 9th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1U) % 0x4U;
+
+    while (stageCnt > 0U)
+    {
+      gcurr1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Update of f values for next coefficient set processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+      fcurr3 = fnext3;
+      fcurr4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = fcurr2;
+    *pDst++ = fcurr3;
+    *pDst++ = fcurr4;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurr1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1U);
+
+    /* stage loop */
+    while (stageCnt > 0U)
+    {
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* f1(n) is saved in fcurr1
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t fcurr, fnext, gcurr, gnext;          /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = pCoeffs;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = fcurr + ((*pk) * gcurr);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (fcurr * (*pk++)) + gcurr;
+
+    /* save f0(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1U);
+
+    /* stage loop */
+    while (stageCnt > 0U)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = fcurr + ((*pk) * gcurr);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+
+      /* f1(n) is saved in fcurr1
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
new file mode 100644
index 0000000..55520eb
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
@@ -0,0 +1,71 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_lattice_init_f32.c
+ * Description:  Floating-point FIR Lattice filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
new file mode 100644
index 0000000..59cf496
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
@@ -0,0 +1,71 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_lattice_init_q15.c
+ * Description:  Q15 FIR Lattice filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
new file mode 100644
index 0000000..abdd76f
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
@@ -0,0 +1,71 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_lattice_init_q31.c
+ * Description:  Q31 FIR lattice filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c
new file mode 100644
index 0000000..fb95ab6
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c
@@ -0,0 +1,524 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_lattice_q15.c
+ * Description:  Q15 FIR lattice filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in]  *S        points to an instance of the Q15 FIR lattice structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* temporary state pointer */
+  q15_t *pk;                                     /* temporary coefficient pointer */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1;    /* temporary variables for first sample in loop unrolling */
+  q31_t fcurnt2, fnext2, gnext2;                 /* temporary variables for second sample in loop unrolling */
+  q31_t fcurnt3, fnext3, gnext3;                 /* temporary variables for third sample in loop unrolling */
+  q31_t fcurnt4, fnext4, gnext4;                 /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+    fcurnt2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurnt1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15U) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15U) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15U) + fcurnt2;
+    fnext2 = __SSAT(fnext2, 16);
+
+    gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15U) + fcurnt1;
+    gnext2 = __SSAT(gnext2, 16);
+
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurnt3 = *pSrc++;
+    fcurnt4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer
+       which is used for next four samples processing */
+    *px++ = (q15_t) fcurnt4;
+
+    /* Process third sample for first tap */
+    fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15U) + fcurnt3;
+    fnext3 = __SSAT(fnext3, 16);
+    gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15U) + fcurnt2;
+    gnext3 = __SSAT(gnext3, 16);
+
+    /* Process fourth sample for first tap */
+    fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15U) + fcurnt4;
+    fnext4 = __SSAT(fnext4, 16);
+    gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15U) + fcurnt3;
+    gnext4 = __SSAT(gnext4, 16);
+
+    /* Update of f values for next coefficient set processing */
+    fcurnt1 = fnext1;
+    fcurnt2 = fnext2;
+    fcurnt3 = fnext3;
+    fcurnt4 = fnext4;
+
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1U) >> 2;
+
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while (stageCnt > 0U)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f1(n) = f0(n) +  K1 * g0(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15U) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      /* fnext4 = fcurnt4 + (*pk) * gnext3; */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15U) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15U) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15U) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15U) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15U) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15U) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15U) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15U) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15U) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15U) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15U) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15U) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15U) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15U) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15U) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15U) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 5th, 9th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 5th, 9th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15U) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15U) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15U) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1U) % 0x4U;
+
+    while (stageCnt > 0U)
+    {
+      gcurnt1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15U) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15U) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15U) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15U) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15U) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15U) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Update of f values for next coefficient set processing */
+      fcurnt1 = fnext1;
+      fcurnt2 = fnext2;
+      fcurnt3 = fnext3;
+      fcurnt4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurnt1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15U) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15U) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* save g1(n) in state buffer */
+    *px++ = (q15_t) fcurnt1;
+
+    /* f1(n) is saved in fcurnt1
+       for next stage processing */
+    fcurnt1 = fnext1;
+
+    stageCnt = (numStages - 1U);
+
+    /* stage loop */
+    while (stageCnt > 0U)
+    {
+      /* read g2(n) from state buffer */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15U) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15U) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* f1(n) is saved in fcurnt1
+         for next stage processing */
+      fcurnt1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt1, 16);
+
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurnt, fnext, gcurnt, gnext;            /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* f0(n) = x(n) */
+    fcurnt = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurnt = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = ((gcurnt * (*pk)) >> 15U) + fcurnt;
+    fnext = __SSAT(fnext, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = ((fcurnt * (*pk++)) >> 15U) + gcurnt;
+    gnext = __SSAT(gnext, 16);
+
+    /* save f0(n) in state buffer */
+    *px++ = (q15_t) fcurnt;
+
+    /* f1(n) is saved in fcurnt
+       for next stage processing */
+    fcurnt = fnext;
+
+    stageCnt = (numStages - 1U);
+
+    /* stage loop */
+    while (stageCnt > 0U)
+    {
+      /* read g1(n-1) from state buffer */
+      gcurnt = *px;
+
+      /* save g0(n-1) in state buffer */
+      *px++ = (q15_t) gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = ((gcurnt * (*pk)) >> 15U) + fcurnt;
+      fnext = __SSAT(fnext, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = ((fcurnt * (*pk++)) >> 15U) + gcurnt;
+      gnext = __SSAT(gnext, 16);
+
+
+      /* f1(n) is saved in fcurnt
+         for next stage processing */
+      fcurnt = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt, 16);
+
+
+    blkCnt--;
+
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c
new file mode 100644
index 0000000..9d52bbc
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c
@@ -0,0 +1,341 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_lattice_q31.c
+ * Description:  Q31 FIR lattice filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.
+ */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* temporary state pointer */
+  q31_t *pk;                                     /* temporary coefficient pointer */
+  q31_t fcurr1, fnext1, gcurr1 = 0, gnext1;      /* temporary variables for first sample in loop unrolling */
+  q31_t fcurr2, fnext2, gnext2;                  /* temporary variables for second sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+  q31_t k;
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 1U;
+
+  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.
+     a second loop below computes the remaining 1 sample. */
+  while (blkCnt > 0U)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* f0(n) = x(n) */
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n - 1) from state buffer */
+    gcurr1 = *px;
+
+    /* Read the reflection coefficient */
+    k = *pk++;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+    fnext1 = fcurr1 + (fnext1 << 1U);
+    gnext1 = gcurr1 + (gnext1 << 1U);
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext2 = (q31_t) (((q63_t) fcurr1 * k) >> 32);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+    fnext2 = fcurr2 + (fnext2 << 1U);
+    gnext2 = fcurr1 + (gnext2 << 1U);
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr2;
+
+    /* f1(n) is saved in fcurr1
+       for next stage processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+
+    stageCnt = (numStages - 1U);
+
+    /* stage loop */
+    while (stageCnt > 0U)
+    {
+
+      /* Read the reflection coefficient */
+      k = *pk++;
+
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext2;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+      fnext2 = (q31_t) (((q63_t) gnext1 * k) >> 32);
+
+      fnext1 = fcurr1 + (fnext1 << 1U);
+      fnext2 = fcurr2 + (fnext2 << 1U);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+      gnext2 = gnext1 + (gnext2 << 1U);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+      gnext1 = gcurr1 + (gnext1 << 1U);
+
+      /* f1(n) is saved in fcurr1
+         for next stage processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = fcurr2;
+
+    blkCnt--;
+
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x2U;
+
+  while (blkCnt > 0U)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n - 1) from state buffer */
+    gcurr1 = *px;
+
+    /* Read the reflection coefficient */
+    k = *pk++;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+    fnext1 = fcurr1 + (fnext1 << 1U);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+    gnext1 = gcurr1 + (gnext1 << 1U);
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1U);
+
+    /* stage loop */
+    while (stageCnt > 0U)
+    {
+      /* Read the reflection coefficient */
+      k = *pk++;
+
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+      fnext1 = fcurr1 + (fnext1 << 1U);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+      gnext1 = gcurr1 + (gnext1 << 1U);
+
+      /* f1(n) is saved in fcurr1
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+
+}
+
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* temporary state pointer */
+  q31_t *pk;                                     /* temporary coefficient pointer */
+  q31_t fcurr, fnext, gcurr, gnext;              /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+    /* save g1(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr1
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1U);
+
+    /* stage loop */
+    while (stageCnt > 0U)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+
+      /* f1(n) is saved in fcurr1
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+}
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c
new file mode 100644
index 0000000..a979783
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c
@@ -0,0 +1,679 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_q15.c
+ * Description:  Q15 FIR filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in]  blockSize number of samples to process per call.
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *	In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function.
+ */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.
+   * The variables acc0 ... acc3 hold output values that are being computed:
+   *
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]
+   */
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* Copy four new input samples into the state buffer.
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = _SIMD32_OFFSET(px1);
+
+    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+    x1 = _SIMD32_OFFSET(px1 + 1U);
+
+    px1 += 2U;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    tapCnt = numTaps >> 2;
+
+    while (tapCnt > 0U)
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Read state x[n-N-2], x[n-N-3] */
+      x2 = _SIMD32_OFFSET(px1);
+
+      /* Read state x[n-N-3], x[n-N-4] */
+      x3 = _SIMD32_OFFSET(px1 + 1U);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLALD(x3, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLALD(x2, c0, acc0);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLALD(x3, c0, acc1);
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = _SIMD32_OFFSET(px1 + 2U);
+
+      /* Read state x[n-N-5], x[n-N-6] */
+      x1 = _SIMD32_OFFSET(px1 + 3U);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLALD(x0, c0, acc2);
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLALD(x1, c0, acc3);
+
+      px1 += 4U;
+
+      tapCnt--;
+
+    }
+
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+     ** This is always be 2 taps since the filter length is even. */
+    if ((numTaps & 0x3U) != 0U)
+    {
+      /* Read 2 coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Fetch 4 state variables */
+      x2 = _SIMD32_OFFSET(px1);
+
+      x3 = _SIMD32_OFFSET(px1 + 1U);
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      px1 += 2U;
+
+      acc1 = __SMLALD(x1, c0, acc1);
+      acc2 = __SMLALD(x2, c0, acc2);
+      acc3 = __SMLALD(x3, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+  while (blkCnt > 0U)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = pCoeffs;
+
+    tapCnt = numTaps >> 1;
+
+    do
+    {
+
+      c0 = *__SIMD32(pb)++;
+      x0 = *__SIMD32(px1)++;
+
+      acc0 = __SMLALD(x0, c0, acc0);
+      tapCnt--;
+    }
+    while (tapCnt > 0U);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1U) >> 2;
+
+  while (tapCnt > 0U)
+  {
+
+    /* Copy state values to start of state buffer */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1U) % 0x4U;
+
+  /* copy remaining data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+#else /* UNALIGNED_SUPPORT_DISABLE */
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.
+   * The variables acc0 ... acc3 hold output values that are being computed:
+   *
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]
+   */
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* Copy four new input samples into the state buffer.
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+    px = pState;
+
+    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *__SIMD32(px)++;
+
+    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+    x2 = *__SIMD32(px)++;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.
+     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+    tapCnt = numTaps >> 2;
+
+    while (tapCnt > 0)
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* pack  x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = _SIMD32_OFFSET(px);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLALDX(x1, c0, acc1);
+
+      /* pack  x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLALDX(x1, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLALD(x2, c0, acc0);
+
+      /* Read state x[n-N-6], x[n-N-7] with offset */
+      x2 = _SIMD32_OFFSET(px + 2U);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLALD(x0, c0, acc2);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLALDX(x1, c0, acc1);
+
+      /* pack  x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLALDX(x1, c0, acc3);
+
+      /* Update state pointer for next state reading */
+      px += 4U;
+
+      /* Decrement tap count */
+      tapCnt--;
+
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+     ** This is always be 2 taps since the filter length is even. */
+    if ((numTaps & 0x3U) != 0U)
+    {
+
+      /* Read last two coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLALD(x0, c0, acc0);
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read last state variables */
+      x0 = *__SIMD32(px);
+
+      /* Perform the multiply-accumulates */
+      acc1 = __SMLALDX(x1, c0, acc1);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* Perform the multiply-accumulates */
+      acc3 = __SMLALDX(x1, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+  while (blkCnt > 0U)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px = pState;
+    pb = pCoeffs;
+
+    tapCnt = numTaps >> 1U;
+
+    do
+    {
+      acc0 += (q31_t) * px++ * *pb++;
+	  acc0 += (q31_t) * px++ * *pb++;
+      tapCnt--;
+    }
+    while (tapCnt > 0U);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1U) >> 2;
+
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1U) % 0x4U;
+
+  /* copy remaining data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#else /* ARM_MATH_CM0_FAMILY */
+
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of nTaps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q31_t) * px++ * *pb++;
+      tapCnt--;
+    } while (tapCnt > 0U);
+
+    /* The result is in 2.30 format.  Convert to 1.15
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT((acc >> 15U), 16);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = (numTaps - 1U);
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+
+
+/**
+ * @} end of FIR group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c
new file mode 100644
index 0000000..b0a2723
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c
@@ -0,0 +1,353 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_q31.c
+ * Description:  Q31 FIR filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t x0, x1, x2;                              /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc0, acc1, acc2;                        /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt, tapCntN3;          /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.
+   * The variables acc0 ... acc3 hold output values that are being computed:
+   *
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]
+   */
+  blkCnt = blockSize / 3;
+  blockSize = blockSize - (3 * blkCnt);
+
+  tapCnt = numTaps / 3;
+  tapCntN3 = numTaps - (3 * tapCnt);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* Copy three new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:
+     *  x[n-numTaps], x[n-numTaps-1] */
+    x0 = *(px++);
+    x1 = *(px++);
+
+    /* Loop unrolling.  Process 3 taps at a time. */
+    i = tapCnt;
+
+    while (i > 0U)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *pb;
+
+      /* Read x[n-numTaps-2] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x0 * c0);
+      acc1 += ((q63_t) x1 * c0);
+      acc2 += ((q63_t) x2 * c0);
+
+      /* Read the coefficient and state */
+      c0 = *(pb + 1U);
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x1 * c0);
+      acc1 += ((q63_t) x2 * c0);
+      acc2 += ((q63_t) x0 * c0);
+
+      /* Read the coefficient and state */
+      c0 = *(pb + 2U);
+      x1 = *(px++);
+
+      /* update coefficient pointer */
+      pb += 3U;
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x2 * c0);
+      acc1 += ((q63_t) x0 * c0);
+      acc2 += ((q63_t) x1 * c0);
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 3, compute the remaining filter taps */
+
+    i = tapCntN3;
+
+    while (i > 0U)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x0 * c0);
+      acc1 += ((q63_t) x1 * c0);
+      acc2 += ((q63_t) x2 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 3 to process the next group of 3 samples */
+    pState = pState + 3;
+
+    /* The results in the 3 accumulators are in 2.30 format.  Convert to 1.31
+     ** Then store the 3 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31U);
+    *pDst++ = (q31_t) (acc1 >> 31U);
+    *pDst++ = (q31_t) (acc2 >> 31U);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 3, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+
+  while (blockSize > 0U)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q63_t) * (px++) * (*(pb++));
+      i--;
+    } while (i > 0U);
+
+    /* The result is in 2.62 format.  Convert to 1.31
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31U);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blockSize--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1U) % 0x4U;
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Length of the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q63_t) * px++ * *pb++;
+      i--;
+    } while (i > 0U);
+
+    /* The result is in 2.62 format.  Convert to 1.31
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc >> 31U);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = numTaps - 1U;
+
+  /* Copy the data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+
+#endif /*  #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c
new file mode 100644
index 0000000..4f795d7
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c
@@ -0,0 +1,385 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_q7.c
+ * Description:  Q7 FIR filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in]   *S points to an instance of the Q7 FIR filter structure.
+ * @param[in]   *pSrc points to the block of input data.
+ * @param[out]  *pDst points to the block of output data.
+ * @param[in]   blockSize number of samples to process per call.
+ * @return 	none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is converted to 18.7 format by discarding the low 7 bits.
+ * Finally, the result is truncated to 1.7 format.
+ */
+
+void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+  q7_t x0, x1, x2, x3;                           /* Temporary variables to hold state */
+  q7_t c0;                                       /* Temporary variable to hold coefficient value */
+  q7_t *px;                                      /* Temporary pointer for state */
+  q7_t *pb;                                      /* Temporary pointer for coefficient buffer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.
+   * The variables acc0 ... acc3 hold output values that are being computed:
+   *
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while (i > 0U)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *pb;
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *px;
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 += ((q15_t) x0 * c0);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 += ((q15_t) x1 * c0);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 += ((q15_t) x2 * c0);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb + 1U);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px + 1U);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x1 * c0);
+      acc1 += ((q15_t) x2 * c0);
+      acc2 += ((q15_t) x3 * c0);
+      acc3 += ((q15_t) x0 * c0);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb + 2U);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px + 2U);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x2 * c0);
+      acc1 += ((q15_t) x3 * c0);
+      acc2 += ((q15_t) x0 * c0);
+      acc3 += ((q15_t) x1 * c0);
+
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb + 3U);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px + 3U);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x3 * c0);
+      acc1 += ((q15_t) x0 * c0);
+      acc2 += ((q15_t) x1 * c0);
+      acc3 += ((q15_t) x2 * c0);
+
+      /* update coefficient pointer */
+      pb += 4U;
+      px += 4U;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4U);
+    while (i > 0U)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x0 * c0);
+      acc1 += ((q15_t) x1 * c0);
+      acc2 += ((q15_t) x2 * c0);
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31
+     ** Then store the 4 outputs in the destination buffer. */
+    acc0 = __SSAT((acc0 >> 7U), 8);
+    *pDst++ = acc0;
+    acc1 = __SSAT((acc1 >> 7U), 8);
+    *pDst++ = acc1;
+    acc2 = __SSAT((acc2 >> 7U), 8);
+    *pDst++ = acc2;
+    acc3 = __SSAT((acc3 >> 7U), 8);
+    *pDst++ = acc3;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4U;
+
+  while (blkCnt > 0U)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q15_t) * (px++) * (*(pb++));
+      i--;
+    } while (i > 0U);
+
+    /* The result is in 2.14 format.  Convert to 1.7
+     ** Then store the output in the destination buffer. */
+    *pDst++ = __SSAT((acc0 >> 7U), 8);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1U) % 0x4U;
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px, *pb;                                 /* Temporary pointers to state and coeff */
+  q31_t acc = 0;                                 /* Accumlator */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1U);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  /* Perform filtering upto BlockSize - BlockSize%4  */
+  while (blkCnt > 0U)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer of type q7 */
+    px = pState;
+
+    /* Initialize coeff pointer of type q7 */
+    pb = pCoeffs;
+
+
+    i = numTaps;
+
+    while (i > 0U)
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q15_t) * px++ * *pb++;
+      i--;
+    }
+
+    /* Store the 1.7 format filter output in destination buffer */
+    *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
+
+    /* Advance the state pointer by 1 to process the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+   ** This prepares the state buffer for the next function call. */
+
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1U);
+
+  /* Copy q7_t data */
+  while (i > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    i--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c
new file mode 100644
index 0000000..fe9aacd
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c
@@ -0,0 +1,433 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_sparse_f32.c
+ * Description:  Floating-point sparse FIR filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters
+ *
+ * This group of functions implements sparse FIR filters.
+ * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.
+ * Sparse filters are used for simulating reflections in communications and audio applications.
+ *
+ * There are separate functions for Q7, Q15, Q31, and floating-point data types.
+ * The functions operate on blocks  of input and output data and each call to the function processes
+ * blockSize samples through the filter.  pSrc and
+ * pDst points to input and output arrays respectively containing blockSize values.
+ *
+ * \par Algorithm:
+ * The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients.
+ * This is in addition to the coefficient array b.
+ * The implementation essentially skips the multiplications by zero and leads to an efficient realization.
+ * 
+ *     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]
+ * 

+ * \par
+ * \image html FIRSparse.gif "Sparse FIR filter.  b[n] represents the filter coefficients"
+ * \par
+ * pCoeffs points to a coefficient array of size numTaps;
+ * pTapDelay points to an array of nonzero indices and is also of size numTaps;
+ * pState points to a state array of size maxDelay + blockSize, where
+ * maxDelay is the largest offset value that is ever used in the pTapDelay array.
+ * Some of the processing functions also require temporary working buffers.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 4 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 4 different data type filter instance structures
+ * 
+ *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ * 

+ * \par
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+ * @param[in]  *pSrc       points to the block of input data.
+ * @param[out] *pDst       points to the block of output data
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize   number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* Scratch buffer pointer */
+  float32_t *py = pState;                        /* Temporary pointers for state buffer */
+  float32_t *pb = pScratchIn;                    /* Temporary pointers for scratch buffer */
+  float32_t *pOut;                               /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter  */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  float32_t coeff = *pCoeffs++;                  /* Read the first coefficient value */
+
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer */
+  px = pb;
+
+  /* Working pointer for destination buffer */
+  pOut = pDst;
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2U;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2U;
+
+  while (tapCnt > 0U)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2U;
+
+    while (blkCnt > 0U)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if (readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+	/* Compute last tap without the final read of pTapDelay */
+
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+											 blockSize);
+
+	/* Working pointer for the scratch buffer */
+	px = pb;
+
+	/* Working pointer for destination buffer */
+	pOut = pDst;
+
+	/* Loop over the blockSize. Unroll by a factor of 4.
+	 * Compute 4 MACS at a time. */
+	blkCnt = blockSize >> 2U;
+
+	while (blkCnt > 0U)
+	{
+		/* Perform Multiply-Accumulate */
+		*pOut++ += *px++ * coeff;
+		*pOut++ += *px++ * coeff;
+		*pOut++ += *px++ * coeff;
+		*pOut++ += *px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+	/* If the blockSize is not a multiple of 4,
+	 * compute the remaining samples */
+	blkCnt = blockSize % 0x4U;
+
+	while (blkCnt > 0U)
+	{
+		/* Perform Multiply-Accumulate */
+		*pOut++ += *px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2U;
+
+  while (tapCnt > 0U)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while (blkCnt > 0U)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if (readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+	/* Compute last tap without the final read of pTapDelay */
+
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+											 blockSize);
+
+	/* Working pointer for the scratch buffer */
+	px = pb;
+
+	/* Working pointer for destination buffer */
+	pOut = pDst;
+
+	blkCnt = blockSize;
+
+	while (blkCnt > 0U)
+	{
+		/* Perform Multiply-Accumulate */
+		*pOut++ += *px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+#endif /*   #if defined (ARM_MATH_DSP)        */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
new file mode 100644
index 0000000..191f8bb
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
@@ -0,0 +1,95 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_sparse_init_f32.c
+ * Description:  Floating-point sparse FIR filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ *
+ * Description:
+ * \par
+ * pCoeffs holds the filter coefficients and has length numTaps.
+ * pState holds the filter's state variables and must be of length
+ * maxDelay + blockSize, where maxDelay
+ * is the maximum number of delay line values.
+ * blockSize is the
+ * number of samples processed by the arm_fir_sparse_f32() function.
+ */
+
+void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0U;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
new file mode 100644
index 0000000..297c5fa
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
@@ -0,0 +1,95 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_sparse_init_q15.c
+ * Description:  Q15 sparse FIR filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ *
+ * Description:
+ * \par
+ * pCoeffs holds the filter coefficients and has length numTaps.
+ * pState holds the filter's state variables and must be of length
+ * maxDelay + blockSize, where maxDelay
+ * is the maximum number of delay line values.
+ * blockSize is the
+ * number of words processed by arm_fir_sparse_q15() function.
+ */
+
+void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0U;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
new file mode 100644
index 0000000..3eb8d47
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_sparse_init_q31.c
+ * Description:  Q31 sparse FIR filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ *
+ * Description:
+ * \par
+ * pCoeffs holds the filter coefficients and has length numTaps.
+ * pState holds the filter's state variables and must be of length
+ * maxDelay + blockSize, where maxDelay
+ * is the maximum number of delay line values.
+ * blockSize is the number of words processed by arm_fir_sparse_q31() function.
+ */
+
+void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0U;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
new file mode 100644
index 0000000..c2cb7b0
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
@@ -0,0 +1,95 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_sparse_init_q7.c
+ * Description:  Q7 sparse FIR filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ *
+ * Description:
+ * \par
+ * pCoeffs holds the filter coefficients and has length numTaps.
+ * pState holds the filter's state variables and must be of length
+ * maxDelay + blockSize, where maxDelay
+ * is the maximum number of delay line values.
+ * blockSize is the
+ * number of samples processed by the arm_fir_sparse_q7() function.
+ */
+
+void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0U;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c
new file mode 100644
index 0000000..663b6e0
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c
@@ -0,0 +1,470 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_sparse_q15.c
+ * Description:  Q15 sparse FIR filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+ * @param[in]  *pSrc        points to the block of input data.
+ * @param[out] *pDst        points to the block of output data
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize    number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.
+ * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.
+ * If the accumulator result overflows it will wrap around rather than saturate.
+ * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
+ */
+
+
+void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pIn = pSrc;                             /* Working pointer for input */
+  q15_t *pOut = pDst;                            /* Working pointer for output */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* Temporary pointers for scratch buffer */
+  q15_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q15_t *py = pState;                            /* Temporary pointers for state buffer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q15_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for pScratchOut */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2;                                /* Temporary variables */
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2U;
+
+  while (tapCnt > 0U)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while (blkCnt > 0U)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if (readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+	/* Compute last tap without the final read of pTapDelay */
+
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_q15(py, delaySize, &readIndex, 1,
+											 pb, pb, blockSize, 1, blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pScratchOut = pScr2;
+
+	/* Loop over the blockSize. Unroll by a factor of 4.
+	 * Compute 4 MACS at a time. */
+	blkCnt = blockSize >> 2;
+
+	while (blkCnt > 0U)
+	{
+		/* Perform Multiply-Accumulate */
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+	/* If the blockSize is not a multiple of 4,
+	 * compute the remaining samples */
+	blkCnt = blockSize % 0x4U;
+
+	while (blkCnt > 0U)
+	{
+		/* Perform Multiply-Accumulate */
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+  /* All the output values are in pScratchOut buffer.
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while (blkCnt > 0U)
+  {
+    in1 = *pScr2++;
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    in1 = *pScr2++;
+
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+    blkCnt--;
+
+  }
+
+  /* If the blockSize is not a multiple of 4,
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2U;
+
+  while (tapCnt > 0U)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    blkCnt = blockSize;
+
+    while (blkCnt > 0U)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if (readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+	/* Compute last tap without the final read of pTapDelay */
+
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_q15(py, delaySize, &readIndex, 1,
+											 pb, pb, blockSize, 1, blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pScratchOut = pScr2;
+
+	blkCnt = blockSize;
+
+	while (blkCnt > 0U)
+	{
+		/* Perform Multiply-Accumulate */
+		*pScratchOut++ += (q31_t) * px++ * coeff;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+  /* All the output values are in pScratchOut buffer.
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c
new file mode 100644
index 0000000..3fd3da0
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c
@@ -0,0 +1,450 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_sparse_q31.c
+ * Description:  Q31 sparse FIR filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+ * @param[in]  *pSrc       points to the block of input data.
+ * @param[out] *pDst       points to the block of output data
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize   number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The 1.31 x 1.31 multiplications are truncated to 2.30 format.
+ * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.
+ * If the accumulator result overflows, it wraps around rather than saturate.
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
+ */
+
+void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* Scratch buffer pointer */
+  q31_t *py = pState;                            /* Temporary pointers for state buffer */
+  q31_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q31_t *pOut;                                   /* Destination pointer */
+  q63_t out;                                     /* Temporary output variable */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q31_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t in;
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pOut = pDst;
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2U;
+
+  while (tapCnt > 0U)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while (blkCnt > 0U)
+    {
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if (readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+	/* Compute last tap without the final read of pTapDelay */
+
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+											 blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pOut = pDst;
+
+	/* Loop over the blockSize. Unroll by a factor of 4.
+	 * Compute 4 MACS at a time. */
+	blkCnt = blockSize >> 2;
+
+	while (blkCnt > 0U)
+	{
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+	/* If the blockSize is not a multiple of 4,
+	 * compute the remaining samples */
+	blkCnt = blockSize % 0x4U;
+
+	while (blkCnt > 0U)
+	{
+		/* Perform Multiply-Accumulate */
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  /* Loop over the blockSize. Unroll by a factor of 4.
+   * process 4 output samples at a time. */
+  blkCnt = blockSize >> 2;
+
+  while (blkCnt > 0U)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,
+   * process the remaining output samples */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2U;
+
+  while (tapCnt > 0U)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while (blkCnt > 0U)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if (readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+	/* Compute last tap without the final read of pTapDelay */
+
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+											 blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pOut = pDst;
+
+	blkCnt = blockSize;
+
+	while (blkCnt > 0U)
+	{
+		/* Perform Multiply-Accumulate */
+		out = *pOut;
+		out += ((q63_t) * px++ * coeff) >> 32;
+		*pOut++ = (q31_t) (out);
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c
new file mode 100644
index 0000000..252ba95
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c
@@ -0,0 +1,469 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fir_sparse_q7.c
+ * Description:  Q7 sparse FIR filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+ * @param[in]  *pSrc        points to the block of input data.
+ * @param[out] *pDst        points to the block of output data
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize    number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is then converted to 18.7 format by discarding the low 7 bits.
+ * Finally, the result is truncated to 1.7 format.
+ */
+
+void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px;                                      /* Scratch buffer pointer */
+  q7_t *py = pState;                             /* Temporary pointers for state buffer */
+  q7_t *pb = pScratchIn;                         /* Temporary pointers for scratch buffer */
+  q7_t *pOut = pDst;                             /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q7_t coeff = *pCoeffs++;                       /* Read the coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for scratch buffer of output values */
+  q31_t in;
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t in1, in2, in3, in4;
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2U;
+
+  while (tapCnt > 0U)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while (blkCnt > 0U)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if (readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+	/* Compute last tap without the final read of pTapDelay */
+
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+											(int32_t) blockSize, 1, blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pScratchOut = pScr2;
+
+	/* Loop over the blockSize. Unroll by a factor of 4.
+	 * Compute 4 MACS at a time. */
+	blkCnt = blockSize >> 2;
+
+	while (blkCnt > 0U)
+	{
+		/* Perform Multiply-Accumulate */
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+	/* If the blockSize is not a multiple of 4,
+	 * compute the remaining samples */
+	blkCnt = blockSize % 0x4U;
+
+	while (blkCnt > 0U)
+	{
+		/* Perform Multiply-Accumulate */
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+  /* All the output values are in pScratchOut buffer.
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while (blkCnt > 0U)
+  {
+    in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if (readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 2U;
+
+  while (tapCnt > 0U)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize */
+    blkCnt = blockSize;
+
+    while (blkCnt > 0U)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if (readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+	/* Compute last tap without the final read of pTapDelay */
+
+	/* Working pointer for state buffer is updated */
+	py = pState;
+
+	/* blockSize samples are read from the state buffer */
+	arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+											(int32_t) blockSize, 1, blockSize);
+
+	/* Working pointer for the scratch buffer of state values */
+	px = pb;
+
+	/* Working pointer for scratch buffer of output values */
+	pScratchOut = pScr2;
+
+	/* Loop over the blockSize */
+	blkCnt = blockSize;
+
+	while (blkCnt > 0U)
+	{
+		/* Perform Multiply-Accumulate */
+		in = *pScratchOut + ((q31_t) * px++ * coeff);
+		*pScratchOut++ = in;
+
+		/* Decrement the loop counter */
+		blkCnt--;
+	}
+
+  /* All the output values are in pScratchOut buffer.
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c
new file mode 100644
index 0000000..7cccd4a
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c
@@ -0,0 +1,435 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_iir_lattice_f32.c
+ * Description:  Floating-point IIR Lattice filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters
+ *
+ * This set of functions implements lattice filters
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a
+ * variety of adaptive filter applications.  The filter structure has feedforward and
+ * feedback components and the net impulse response is infinite length.
+ * The functions operate on blocks
+ * of input and output data and each call to the function processes
+ * blockSize samples through the filter.  pSrc and
+ * pDst point to input and output arrays containing blockSize values.
+
+ * \par Algorithm:
+ * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"
+ * 
+ *    fN(n)   =  x(n)
+ *    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1
+ *    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1
+ *    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)
+ * 

+ * \par
+ * pkCoeffs points to array of reflection coefficients of size numStages.
+ * Reflection coefficients are stored in time-reversed order.
+ * \par
+ * 
+ *    {kN, kN-1, ....k1}
+ * 

+ * pvCoeffs points to the array of ladder coefficients of size (numStages+1).
+ * Ladder coefficients are stored in time-reversed order.
+ * \par
+ * 
+ *    {vN, vN-1, ...v0}
+ * 

+ * pState points to a state array of size numStages + blockSize.
+ * The state variables shown in the figure above (the g values) are stored in the pState array.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+  *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
+ * 
+ *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ * 

+ * \par
+ * where numStages is the number of stages in the filter; pState points to the state buffer array;
+ * pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t fnext1, gcurr1, gnext;               /* Temporary variables for lattice stages */
+  float32_t acc;                                 /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
+  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  float32_t *pState;                             /* State pointer */
+  float32_t *pStateCurnt;                        /* State current pointer */
+  float32_t k1, k2;
+  float32_t v1, v2, v3, v4;
+  float32_t gcurr2;
+  float32_t fnext2;
+
+  /* initialise loop count */
+  blkCnt = blockSize;
+
+  /* initialise state pointer */
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while (blkCnt > 0U)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fnext2 = *pSrc++;
+
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+
+    /* Set accumulator to zero */
+    acc = 0.0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages) >> 2;
+
+    while (tapCnt > 0U)
+    {
+      /* Read gN-1(n-1) from state buffer */
+      gcurr1 = *px1;
+
+      /* read reflection coefficient kN */
+      k1 = *pk;
+
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext1 = fnext2 - (k1 * gcurr1);
+
+      /* read ladder coefficient vN */
+      v1 = *pv;
+
+      /* read next reflection coefficient kN-1 */
+      k2 = *(pk + 1U);
+
+      /* Read gN-2(n-1) from state buffer */
+      gcurr2 = *(px1 + 1U);
+
+      /* read next ladder coefficient vN-1 */
+      v2 = *(pv + 1U);
+
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext2 = fnext1 - (k2 * gcurr2);
+
+      /* gN(n)   = kN * fN-1(n) + gN-1(n-1) */
+      gnext = gcurr1 + (k1 * fnext1);
+
+      /* read reflection coefficient kN-2 */
+      k1 = *(pk + 2U);
+
+      /* write gN(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* Read gN-3(n-1) from state buffer */
+      gcurr1 = *(px1 + 2U);
+
+      /* y(n) += gN(n) * vN  */
+      acc += (gnext * v1);
+
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fnext1 = fnext2 - (k1 * gcurr1);
+
+      /* gN-1(n)   = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = gcurr2 + (k2 * fnext2);
+
+      /* Read gN-4(n-1) from state buffer */
+      gcurr2 = *(px1 + 3U);
+
+      /* y(n) += gN-1(n) * vN-1  */
+      acc += (gnext * v2);
+
+      /* read reflection coefficient kN-3 */
+      k2 = *(pk + 3U);
+
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext2 = fnext1 - (k2 * gcurr2);
+
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = gcurr1 + (k1 * fnext1);
+
+      /* read ladder coefficient vN-2 */
+      v3 = *(pv + 2U);
+
+      /* y(n) += gN-2(n) * vN-2  */
+      acc += (gnext * v3);
+
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* update pointer */
+      pk += 4U;
+
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = (fnext2 * k2) + gcurr2;
+
+      /* read next ladder coefficient vN-3 */
+      v4 = *(pv + 3U);
+
+      /* y(n) += gN-4(n) * vN-4  */
+      acc += (gnext * v4);
+
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* update pointers */
+      px1 += 4U;
+      pv += 4U;
+
+      tapCnt--;
+
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages) % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      gcurr1 = *px1++;
+      /* Process sample for last taps */
+      fnext1 = fnext2 - ((*pk) * gcurr1);
+      gnext = (fnext1 * (*pk++)) + gcurr1;
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fnext2 = fnext1;
+
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext2 * (*pv));
+
+    *px2++ = fnext2;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1U;
+
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4U;
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+#else
+
+void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t fcurr, fnext = 0, gcurr, gnext;      /* Temporary variables for lattice stages */
+  float32_t acc;                                 /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
+  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  float32_t *pState;                             /* State pointer */
+  float32_t *pStateCurnt;                        /* State current pointer */
+
+
+  /* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while (blkCnt > 0U)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0.0f;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for numStages */
+    tapCnt = numStages;
+
+    while (tapCnt > 0U)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - ((*pk) * gcurr);
+      gnext = (fnext * (*pk++)) + gcurr;
+
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      /* Decrementing loop counter */
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext * (*pv));
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1U;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
new file mode 100644
index 0000000..f20a21b
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_iir_lattice_init_f32.c
+ * Description:  Floating-point IIR lattice filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+  /**
+   * @} end of IIR_Lattice group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
new file mode 100644
index 0000000..6cae944
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_iir_lattice_init_q15.c
+ * Description:  Q15 IIR lattice filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+  /**
+   * @brief Initialization function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process per call.
+   * @return none.
+   */
+
+void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
new file mode 100644
index 0000000..fe9869e
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_iir_lattice_init_q31.c
+ * Description:  Initialization function for the Q31 IIR lattice filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c
new file mode 100644
index 0000000..9c70b68
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c
@@ -0,0 +1,452 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_iir_lattice_q15.c
+ * Description:  Q15 IIR lattice filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurr, fnext, gcurr = 0, gnext;          /* Temporary variables for lattice stages */
+  q15_t gnext1, gnext2;                          /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+  q31_t v;                                       /* Temporary variable for ladder coefficient */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+	q15_t v1, v2;
+#endif
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while (blkCnt > 0U)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+    fnext = __SSAT(fnext, 16);
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+    gnext = __SSAT(gnext, 16);
+    /* write gN(n) into state for next sample processing */
+    *px2++ = (q15_t) gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += (q31_t) ((gnext * (*pv++)));
+
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1U) >> 2;
+
+    while (tapCnt > 0U)
+    {
+
+      /* Process sample for 2nd, 6th ...taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 2nd, 6th .. taps */
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-1(n) into state */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-2(n) into state */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-1 and vN-2 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      v = *__SIMD32(pv)++;
+
+#else
+
+	  v1 = *pv++;
+	  v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  v = __PKHBT(v1, v2, 16);
+
+#else
+
+	  v = __PKHBT(v2, v1, 16);
+
+#endif	/* 	#ifndef ARM_MATH_BIG_ENDIAN		*/
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+      /* Pack gN-1(n) and gN-2(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write  gN-3(n) for the next sample process */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write      gN-4(n) for the next sample process */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-3 and vN-4 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      v = *__SIMD32(pv)++;
+
+#else
+
+	  v1 = *pv++;
+	  v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  v = __PKHBT(v1, v2, 16);
+
+#else
+
+	  v = __PKHBT(v2, v1, 16);
+
+#endif	/* #ifndef ARM_MATH_BIG_ENDIAN	 */
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+      /* Pack gN-3(n) and gN-4(n) */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1U) % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples for last taps */
+      acc += (q31_t) (((q31_t) gnext * (*pv++)));
+      *px2++ = (q15_t) gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) (((q31_t) fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1U;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = (numStages >> 2U);
+
+  /* copy data */
+  while (stgCnt > 0U)
+  {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+#endif /*	#ifndef UNALIGNED_SUPPORT_DISABLE */
+
+    /* Decrement the loop counter */
+    stgCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  stgCnt = (numStages) % 0x4U;
+
+  /* copy data */
+  while (stgCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while (blkCnt > 0U)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while (tapCnt > 0U)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext = fcurr - ((gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext = ((fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples */
+      /* y(n) += gN(n) * vN */
+      acc += (q31_t) ((gnext * (*pv++)));
+      /* write gN(n) into state for next sample processing */
+      *px2++ = (q15_t) gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) ((fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1U;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = numStages;
+
+  /* copy data */
+  while (stgCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c
new file mode 100644
index 0000000..736cbc0
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c
@@ -0,0 +1,338 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_iir_lattice_q31.c
+ * Description:  Q31 IIR lattice filter processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.
+ */
+
+void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q31_t *px1, *px2, *pk, *pv;                    /* Temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pStateCurnt;                            /* State current pointer */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Sample processing */
+  while (blkCnt > 0U)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+    /* write gN-1(n-1) into state for next sample processing */
+    *px2++ = gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += ((q63_t) gnext * *pv++);
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1U) >> 2;
+
+    while (tapCnt > 0U)
+    {
+
+      /* Process sample for 2nd, 6th .. taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-4(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1U) % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* Output samples for last taps */
+      acc += ((q63_t) gnext * *pv++);
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31U);
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1U;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4U;
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  };
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  /* Sample processing */
+  while (blkCnt > 0U)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while (tapCnt > 0U)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext =
+        clip_q63_to_q31(((q63_t) fcurr -
+                         ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext =
+        clip_q63_to_q31(((q63_t) gcurr +
+                         ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
+      /* Output samples */
+      /* y(n) += gN(n) * vN  */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n-1) into state for next sample processing */
+      *px2++ = gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31U);
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1U;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c
new file mode 100644
index 0000000..3975f00
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c
@@ -0,0 +1,430 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_f32.c
+ * Description:  Processing function for the floating-point LMS filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup LMS Least Mean Square (LMS) Filters
+ *
+ * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.
+ * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.
+ * Adaptive filters are often used in communication systems, equalizers, and noise removal.
+ * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.
+ * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.
+ *
+ * An LMS filter consists of two components as shown below.
+ * The first component is a standard transversal or FIR filter.
+ * The second component is a coefficient update mechanism.
+ * The LMS filter has two input signals.
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
+ * This "error signal" tends towards zero as the filter adapts.
+ * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.
+ * \image html LMS.gif "Internal structure of the Least Mean Square filter"
+ *
+ * The functions operate on blocks of data and each call to the function processes
+ * blockSize samples through the filter.
+ * pSrc points to input signal, pRef points to reference signal,
+ * pOut points to output signal and pErr points to error signal.
+ * All arrays contain blockSize values.
+ *
+ * The functions operate on a block-by-block basis.
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
+ *
+ * \par Algorithm:
+ * The output signal y[n] is computed by a standard FIR filter:
+ * 
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ * 

+ *
+ * \par
+ * The error signal equals the difference between the reference signal d[n] and the filter output:
+ * 
+ *     e[n] = d[n] - y[n].
+ * 

+ *
+ * \par
+ * After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis:
+ * 
+ *     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1
+ * 

+ * where mu is the step size and controls the rate of coefficient convergence.
+ *\par
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * \par
+ * pState points to a state array of size numTaps + blockSize - 1.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * 
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ * 

+ * \par
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
+ * to be avoided and yields a significant speed improvement.
+ * The state variables are updated after each block of data is processed.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter and
+ * coefficient and state arrays cannot be shared among instances.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * 
+ *    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};
+ *    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};
+ *    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};
+ * 

+ * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;
+ * pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.
+ *
+ * \par Fixed-Point Behavior:
+ * Care must be taken when using the Q15 and Q31 versions of the LMS filter.
+ * The following issues must be considered:
+ * - Scaling of coefficients
+ * - Overflow and saturation
+ *
+ * \par Scaling of Coefficients:
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range [-1 +1).
+ * The fixed-point functions have an additional scaling parameter postShift.
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ * This essentially scales the filter coefficients by 2^postShift and
+ * allows the filter coefficients to exceed the range [+1 -1).
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.
+ *
+ * \par Overflow and Saturation:
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
+ * described separately as part of the function specific documentation below.
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+/**
+ * @details
+ * This function operates on floating-point data types.
+ *
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[in]  *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in]  blockSize number of samples to process.
+ * @return     none.
+ */
+
+void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w = 0.0f;                            /* weight factor */
+
+  e = 0.0f;
+  d = 0.0f;
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  blkCnt = blockSize;
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while (blkCnt > 0U)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for the updating filter coefficients */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+     satrt of the state buffer. This prepares the state buffer for the
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1U) samples copy */
+  tapCnt = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1U) % 0x4U;
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (blkCnt > 0U)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Weighting factor for the LMS version */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+   * start of the state buffer. This prepares the state buffer for the
+   * next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1U) samples  */
+  tapCnt = (numTaps - 1U);
+
+  /* Copy the data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+   * @} end of LMS group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c
new file mode 100644
index 0000000..73158bb
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c
@@ -0,0 +1,83 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_init_f32.c
+ * Description:  Floating-point LMS filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+/**
+ * \par Description:
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32().
+ */
+
+void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps */
+  memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c
new file mode 100644
index 0000000..001287d
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_init_q15.c
+ * Description:  Q15 LMS filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+/**
+* @brief Initialization function for the Q15 LMS filter.
+* @param[in] *S points to an instance of the Q15 LMS filter structure.
+* @param[in] numTaps  number of filter coefficients.
+* @param[in] *pCoeffs points to the coefficient buffer.
+* @param[in] *pState points to the state buffer.
+* @param[in] mu step size that controls filter coefficient updates.
+* @param[in] blockSize number of samples to process.
+* @param[in] postShift bit shift applied to coefficients.
+* @return    none.
+*
+* \par Description:
+* pCoeffs points to the array of filter coefficients stored in time reversed order:
+* 
+*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+* 

+* The initial filter coefficients serve as a starting point for the adaptive filter.
+* pState points to the array of state variables and size of array is
+* numTaps+blockSize-1 samples, where blockSize is the number of
+* input samples processed by each call to arm_lms_q15().
+*/
+
+void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c
new file mode 100644
index 0000000..7d95d97
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_init_q31.c
+ * Description:  Q31 LMS filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+ *
+ * \par Description:
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * pState points to an array of length numTaps+blockSize-1 samples,
+ * where blockSize is the number of input samples processed by each call to
+ * arm_lms_q31().
+ */
+
+void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1U)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c
new file mode 100644
index 0000000..a365b33
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c
@@ -0,0 +1,454 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_norm_f32.c
+ * Description:  Processing function for the floating-point Normalised LMS
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup LMS_NORM Normalized LMS Filters
+ *
+ * This set of functions implements a commonly used adaptive filter.
+ * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization
+ * factor which increases the adaptation rate of the filter.
+ * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.
+ *
+ * A normalized least mean square (NLMS) filter consists of two components as shown below.
+ * The first component is a standard transversal or FIR filter.
+ * The second component is a coefficient update mechanism.
+ * The NLMS filter has two input signals.
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
+ * This "error signal" tends towards zero as the filter adapts.
+ * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.
+ * \image html LMS.gif "Internal structure of the NLMS adaptive filter"
+ *
+ * The functions operate on blocks of data and each call to the function processes
+ * blockSize samples through the filter.
+ * pSrc points to input signal, pRef points to reference signal,
+ * pOut points to output signal and pErr points to error signal.
+ * All arrays contain blockSize values.
+ *
+ * The functions operate on a block-by-block basis.
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
+ *
+ * \par Algorithm:
+ * The output signal y[n] is computed by a standard FIR filter:
+ * 
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ * 

+ *
+ * \par
+ * The error signal equals the difference between the reference signal d[n] and the filter output:
+ * 
+ *     e[n] = d[n] - y[n].
+ * 

+ *
+ * \par
+ * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:
+ * 
+ *    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.
+ * 

+ * The filter coefficients b[k] are then updated on a sample-by-sample basis:
+ * 
+ *     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1
+ * 

+ * where mu is the step size and controls the rate of coefficient convergence.
+ *\par
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * \par
+ * pState points to a state array of size numTaps + blockSize - 1.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * 
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ * 

+ * \par
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
+ * to be avoided and yields a significant speed improvement.
+ * The state variables are updated after each block of data is processed.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter and
+ * coefficient and state arrays cannot be shared among instances.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero.
+ * For Q7, Q15, and Q31 the following fields must also be initialized;
+ * recipTable, postShift
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ * \par Fixed-Point Behavior:
+ * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.
+ * The following issues must be considered:
+ * - Scaling of coefficients
+ * - Overflow and saturation
+ *
+ * \par Scaling of Coefficients:
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range [-1 +1).
+ * The fixed-point functions have an additional scaling parameter postShift.
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ * This essentially scales the filter coefficients by 2^postShift and
+ * allows the filter coefficients to exceed the range [+1 -1).
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.
+ *
+ * \par Overflow and Saturation:
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
+ * described separately as part of the function specific documentation below.
+ */
+
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t energy;                              /* Energy of the input */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w, x0, in;                           /* weight factor, temporary variable to hold input sample and state */
+
+  /* Initializations of error,  difference, Coefficient update */
+  e = 0.0f;
+  d = 0.0f;
+  w = 0.0f;
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while (blkCnt > 0U)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+     satrt of the state buffer. This prepares the state buffer for the
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1U)/4 samples copy */
+  tapCnt = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1U) % 0x4U;
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (blkCnt > 0U)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCcoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+     satrt of the state buffer. This prepares the state buffer for the
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy (numTaps - 1U) samples  */
+  tapCnt = (numTaps - 1U);
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+   * @} end of LMS_NORM group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c
new file mode 100644
index 0000000..49272f8
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_norm_init_f32.c
+ * Description:  Floating-point NLMS filter initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   *
+ * \par Description:
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * pState points to an array of length numTaps+blockSize-1 samples,
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_f32().
+ */
+
+void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialise Energy to zero */
+  S->energy = 0.0f;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0.0f;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c
new file mode 100644
index 0000000..0624222
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c
@@ -0,0 +1,100 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_norm_init_q15.c
+ * Description:  Q15 NLMS initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * pState points to the array of state variables and size of array is
+ * numTaps+blockSize-1 samples, where blockSize is the number of input samples processed
+ * by each call to arm_lms_norm_q15().
+ */
+
+void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = (q15_t *) armRecipTableQ15;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c
new file mode 100644
index 0000000..4f70408
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_norm_init_q31.c
+ * Description:  Q31 NLMS initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ * 
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * 

+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * pState points to an array of length numTaps+blockSize-1 samples,
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_q31().
+ */
+
+void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1  */
+  memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = (q31_t *) armRecipTableQ31;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c
new file mode 100644
index 0000000..00bde39
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c
@@ -0,0 +1,428 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_norm_q15.c
+ * Description:  Q15 NLMS filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+/**
+* @brief Processing function for Q15 normalized LMS filter.
+* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[in] *pRef points to the block of reference data.
+* @param[out] *pOut points to the block of output data.
+* @param[out] *pErr points to the block of error data.
+* @param[in] blockSize number of samples to process.
+* @return none.
+*
+* Scaling and Overflow Behavior:
+* \par
+* The function is implemented using a 64-bit internal accumulator.
+* Both coefficients and state variables are represented in 1.15 format and
+* multiplications yield a 2.30 result. The 2.30 intermediate results are
+* accumulated in a 64-bit accumulator in 34.30 format.
+* There is no risk of internal overflow with this approach and the full
+* precision of intermediate multiplications is preserved. After all additions
+* have been performed, the accumulator is truncated to 34.15 format by
+* discarding low 15 bits. Lastly, the accumulator is saturated to yield a
+* result in 1.15 format.
+*
+* \par
+* 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+*
+ */
+
+void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q31_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0, d = 0;                            /* error, reference data sample */
+  q15_t w = 0, in;                               /* weight factor and state */
+  q15_t x0;                                      /* temporary variable to hold input sample */
+  //uint32_t shift = (uint32_t) S->postShift + 1U; /* Shift to be applied to the output */
+  q15_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q15_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Teporary variable for coefficient */
+  q31_t acc_l, acc_h;
+  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */
+  int32_t uShift = (32 - lShift);
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while (blkCnt > 0U)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while (tapCnt > 0U)
+    {
+
+      /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+      acc += (((q31_t) * px++ * (*pb++)));
+      acc += (((q31_t) * px++ * (*pb++)));
+      acc += (((q31_t) * px++ * (*pb++)));
+      acc += (((q31_t) * px++ * (*pb++)));
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16U);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while (tapCnt > 0U)
+    {
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+     satrt of the state buffer. This prepares the state buffer for the
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1U) >> 2;
+
+  while (tapCnt > 0U)
+  {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+#endif
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1U) % 0x4U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (blkCnt > 0U)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16U);
+
+    /* Converting the result to 1.15 format */
+    //acc = __SSAT((acc >> (16U - shift)), 16U);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+     satrt of the state buffer. This prepares the state buffer for the
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* copy (numTaps - 1U) data */
+  tapCnt = (numTaps - 1U);
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+
+/**
+   * @} end of LMS_NORM group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c
new file mode 100644
index 0000000..bc65fa6
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c
@@ -0,0 +1,419 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_norm_q31.c
+ * Description:  Processing function for the Q31 NLMS filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+/**
+* @brief Processing function for Q31 normalized LMS filter.
+* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[in] *pRef points to the block of reference data.
+* @param[out] *pOut points to the block of output data.
+* @param[out] *pErr points to the block of error data.
+* @param[in] blockSize number of samples to process.
+* @return none.
+*
+* Scaling and Overflow Behavior:
+* \par
+* The function is implemented using an internal 64-bit accumulator.
+* The accumulator has a 2.62 format and maintains full precision of the intermediate
+* multiplication results but provides only a single guard bit.
+* Thus, if the accumulator result overflows it wraps around rather than clip.
+* In order to avoid overflows completely the input signal must be scaled down by
+* log2(numTaps) bits. The reference signal should not be scaled down.
+* After all multiply-accumulates are performed, the 2.62 accumulator is shifted
+* and saturated to 1.31 format to yield the final result.
+* The output signal and error signal are in 1.31 format.
+*
+* \par
+* 	In this filter, filter coefficients are updated for each sample and the
+* updation of filter cofficients are saturted.
+*
+*/
+
+void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0, d = 0;                            /* error, reference data sample */
+  q31_t w = 0, in;                               /* weight factor and state */
+  q31_t x0;                                      /* temporary variable to hold input sample */
+//  uint32_t shift = 32U - ((uint32_t) S->postShift + 1U);        /* Shift to be applied to the output */
+  q31_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q31_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Temporary variable for coef */
+  q31_t acc_l, acc_h;                            /*  temporary input */
+  uint32_t uShift = ((uint32_t) S->postShift + 1U);
+  uint32_t lShift = 32U - uShift;                /*  Shift to be applied to the output */
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while (blkCnt > 0U)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy = (q31_t) ((((q63_t) energy << 32) -
+                       (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift = arm_recip_q31(energy + DELTA_Q31,
+                              &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+     satrt of the state buffer. This prepares the state buffer for the
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1U) samples copy */
+  tapCnt = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1U) % 0x4U;
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (blkCnt > 0U)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy =
+      (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Converting the result to 1.31 format */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+
+    //acc = (q31_t) (acc >> shift);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift =
+      arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+     start of the state buffer. This prepares the state buffer for the
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop for (numTaps - 1U) samples copy */
+  tapCnt = (numTaps - 1U);
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c
new file mode 100644
index 0000000..8d5226e
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c
@@ -0,0 +1,368 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_q15.c
+ * Description:  Processing function for the Q15 LMS filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par Scaling and Overflow Behavior:
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+ *
+ */
+
+void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  q15_t *px;                                     /* Temporary pointer for state */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0;                                   /* error of data sample */
+  q15_t alpha;                                   /* Intermediate constant for taps update */
+  q31_t coef;                                    /* Teporary variable for coefficient */
+  q31_t acc_l, acc_h;
+  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */
+  int32_t uShift = (32 - lShift);
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2U;
+
+    while (tapCnt > 0U)
+    {
+      /* acc +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2U;
+
+    /* Update filter coefficients */
+    while (tapCnt > 0U)
+    {
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+     satrt of the state buffer. This prepares the state buffer for the
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1U) >> 2;
+
+  while (tapCnt > 0U)
+  {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+#else
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+#endif
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1U) % 0x4U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) ((q31_t) (*px++) * (*pb++));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+     start of the state buffer. This prepares the state buffer for the
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1U) samples  */
+  tapCnt = (numTaps - 1U);
+
+  /* Copy the data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+   * @} end of LMS group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c
new file mode 100644
index 0000000..66b2a91
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c
@@ -0,0 +1,357 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_lms_q31.c
+ * Description:  Processing function for the Q31 LMS filter
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[in]  *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in]  blockSize number of samples to process.
+ * @return     none.
+ *
+ * \par Scaling and Overflow Behavior:
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate
+ * multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clips.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(numTaps) bits.
+ * The reference signal should not be scaled down.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is shifted
+ * and saturated to 1.31 format to yield the final result.
+ * The output signal and error signal are in 1.31 format.
+ *
+ * \par
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+ */
+
+void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0;                                   /* error of data sample */
+  q31_t alpha;                                   /* Intermediate constant for taps update */
+  q31_t coef;                                    /* Temporary variable for coef */
+  q31_t acc_l, acc_h;                            /*  temporary input */
+  uint32_t uShift = ((uint32_t) S->postShift + 1U);
+  uint32_t lShift = 32U - uShift;                /*  Shift to be applied to the output */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while (blkCnt > 0U)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      /* acc +=  b[N] * x[n-N] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-1] * x[n-N-1] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-2] * x[n-N-2] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-3] * x[n-N-3] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while (tapCnt > 0U)
+    {
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4U;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+     satrt of the state buffer. This prepares the state buffer for the
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1U) samples copy */
+  tapCnt = (numTaps - 1U) >> 2U;
+
+  /* copy data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1U) % 0x4U;
+
+  /* Copy the remaining q31_t data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while (blkCnt > 0U)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Store the result from accumulator into the destination buffer. */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Weighting factor for the LMS version */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while (tapCnt > 0U)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the
+     start of the state buffer. This prepares the state buffer for the
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1U) samples  */
+  tapCnt = (numTaps - 1U);
+
+  /* Copy the data */
+  while (tapCnt > 0U)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+   * @} end of LMS group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c
new file mode 100644
index 0000000..9b609be
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c
@@ -0,0 +1,196 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_add_f32.c
+ * Description:  Floating-point matrix addition
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixAdd Matrix Addition
+ *
+ * Adds two matrices.
+ * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"
+ *
+ * The functions check to make sure that
+ * pSrcA, pSrcB, and pDst have the same
+ * number of rows and columns.
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer   */
+
+#if defined (ARM_MATH_DSP)
+
+  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */
+
+#endif //      #if defined (ARM_MATH_DSP)
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#if defined (ARM_MATH_DSP)
+
+    /* Loop unrolling */
+    blkCnt = numSamples >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* out = sourceA + sourceB */
+      out1 = inA1 + inB1;
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* out = sourceA + sourceB */
+      out2 = inA2 + inB2;
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* out = sourceA + sourceB */
+      out1 = inA1 + inB1;
+
+      /* out = sourceA + sourceB */
+      out2 = inA2 + inB2;
+
+      /* Store result in destination */
+      pOut[2] = out1;
+
+      /* Store result in destination */
+      pOut[3] = out2;
+
+
+      /* update pointers to process next sampels */
+      pIn1 += 4U;
+      pIn2 += 4U;
+      pOut += 4U;
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4U;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) + (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c
new file mode 100644
index 0000000..e6737fa
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_add_q15.c
+ * Description:  Q15 matrix addition
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix addition  */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
+
+#if defined (ARM_MATH_DSP)
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop unrolling */
+    blkCnt = (uint32_t) numSamples >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = (uint32_t) numSamples % 0x4U;
+
+    /* q15 pointers of input and output are initialized */
+
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = (uint32_t) numSamples;
+
+
+    /* q15 pointers of input and output are initialized */
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c
new file mode 100644
index 0000000..4119563
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c
@@ -0,0 +1,195 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_add_q31.c
+ * Description:  Q31 matrix addition
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t inA1, inB1;                              /* temporary variables */
+
+#if defined (ARM_MATH_DSP)
+
+  q31_t inA2, inB2;                              /* temporary variables */
+  q31_t out1, out2;                              /* temporary variables */
+
+#endif //      #if defined (ARM_MATH_DSP)
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#if defined (ARM_MATH_DSP)
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2U;
+
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* Add and saturate */
+      out1 = __QADD(inA1, inB1);
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* Add and saturate */
+      out2 = __QADD(inA2, inB2);
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* Add and saturate */
+      out1 = __QADD(inA1, inB1);
+      out2 = __QADD(inA2, inB2);
+
+      /* Store result in destination */
+      pOut[2] = out1;
+      pOut[3] = out2;
+
+      /* update pointers to process next sampels */
+      pIn1 += 4U;
+      pIn2 += 4U;
+      pOut += 4U;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4U;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      inA1 = *pIn1++;
+      inB1 = *pIn2++;
+
+      inA1 = __QADD(inA1, inB1);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+
+      *pOut++ = inA1;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
new file mode 100644
index 0000000..9b2f532
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
@@ -0,0 +1,272 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_cmplx_mult_f32.c
+ * Description:  Floating-point matrix multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup CmplxMatrixMult  Complex Matrix Multiplication
+ *
+ * Complex Matrix multiplication is only defined if the number of columns of the
+ * first matrix equals the number of rows of the second matrix.
+ * Multiplying an M x N matrix with an N x P matrix results
+ * in an M x P matrix.
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of
+ * pSrcA and pSrcB are equal; and (2) that the size of the output
+ * matrix equals the outer dimensions of pSrcA and pSrcB.
+ */
+
+
+/**
+ * @addtogroup CmplxMatrixMult
+ * @{
+ */
+
+/**
+ * @brief Floating-point Complex matrix multiplication.
+ * @param[in]       *pSrcA points to the first input complex matrix structure
+ * @param[in]       *pSrcB points to the second input complex matrix structure
+ * @param[out]      *pDst points to output complex matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  float32_t sumReal1, sumImag1;                  /* accumulator */
+  float32_t a0, b0, c0, d0;
+  float32_t a1, b1, c1, d1;
+  float32_t sumReal2, sumImag2;                  /* accumulator */
+
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0U, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + 2 * i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0U;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sumReal1 = 0.0f;
+        sumImag1 = 0.0f;
+
+        sumReal2 = 0.0f;
+        sumImag2 = 0.0f;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* matrix multiplication        */
+        while (colCnt > 0U)
+        {
+
+          /* Reading real part of complex matrix A */
+          a0 = *pIn1;
+
+          /* Reading real part of complex matrix B */
+          c0 = *pIn2;
+
+          /* Reading imaginary part of complex matrix A */
+          b0 = *(pIn1 + 1U);
+
+          /* Reading imaginary part of complex matrix B */
+          d0 = *(pIn2 + 1U);
+
+          sumReal1 += a0 * c0;
+          sumImag1 += b0 * c0;
+
+          pIn1 += 2U;
+          pIn2 += 2 * numColsB;
+
+          sumReal2 -= b0 * d0;
+          sumImag2 += a0 * d0;
+
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+          a1 = *pIn1;
+          c1 = *pIn2;
+
+          b1 = *(pIn1 + 1U);
+          d1 = *(pIn2 + 1U);
+
+          sumReal1 += a1 * c1;
+          sumImag1 += b1 * c1;
+
+          pIn1 += 2U;
+          pIn2 += 2 * numColsB;
+
+          sumReal2 -= b1 * d1;
+          sumImag2 += a1 * d1;
+
+          a0 = *pIn1;
+          c0 = *pIn2;
+
+          b0 = *(pIn1 + 1U);
+          d0 = *(pIn2 + 1U);
+
+          sumReal1 += a0 * c0;
+          sumImag1 += b0 * c0;
+
+          pIn1 += 2U;
+          pIn2 += 2 * numColsB;
+
+          sumReal2 -= b0 * d0;
+          sumImag2 += a0 * d0;
+
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+          a1 = *pIn1;
+          c1 = *pIn2;
+
+          b1 = *(pIn1 + 1U);
+          d1 = *(pIn2 + 1U);
+
+          sumReal1 += a1 * c1;
+          sumImag1 += b1 * c1;
+
+          pIn1 += 2U;
+          pIn2 += 2 * numColsB;
+
+          sumReal2 -= b1 * d1;
+          sumImag2 += a1 * d1;
+
+          /* Decrement the loop count */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4U;
+
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          a1 = *pIn1;
+          c1 = *pIn2;
+
+          b1 = *(pIn1 + 1U);
+          d1 = *(pIn2 + 1U);
+
+          sumReal1 += a1 * c1;
+          sumImag1 += b1 * c1;
+
+          pIn1 += 2U;
+          pIn2 += 2 * numColsB;
+
+          sumReal2 -= b1 * d1;
+          sumImag2 += a1 * d1;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        sumReal1 += sumReal2;
+        sumImag1 += sumImag2;
+
+        /* Store the result in the destination buffer */
+        *px++ = sumReal1;
+        *px++ = sumImag1;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + 2U * j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while (col > 0U);
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + 2 * numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
new file mode 100644
index 0000000..b1578a5
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
@@ -0,0 +1,413 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cmplx_mat_mult_q15.c
+ * Description:  Q15 complex matrix multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup CmplxMatrixMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 Complex matrix multiplication
+ * @param[in]       *pSrcA points to the first input complex matrix structure
+ * @param[in]       *pSrcB points to the second input complex matrix structure
+ * @param[out]      *pDst points to output complex matrix structure
+ * @param[in]		*pScratch points to the array for storing intermediate results
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * \par Conditions for optimum performance
+ *  Input, output and state buffers should be aligned by 32-bit
+ *
+ * \par Restrictions
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ *	In this case input, output, scratch buffers should be aligned by 32-bit
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to
+ * 1.15 format.
+ *
+ * \par
+ * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function.
+ *
+ */
+
+
+
+
+arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch)
+{
+  /* accumulator */
+  q15_t *pSrcBT = pScratch;                      /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0U, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+  q63_t sumReal, sumImag;
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  q15_t in;                                      /* Temporary variable to hold the input value */
+  q15_t a, b, c, d;
+#else
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q31_t prod1, prod2;
+  q31_t pSourceA, pSourceB;
+#endif
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while (col > 0U)
+      {
+#ifdef UNALIGNED_SUPPORT_DISABLE
+        /* Read two elements from the row */
+        in = *pInB++;
+        *px = in;
+        in = *pInB++;
+        px[1] = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Read two elements from the row */
+        in = *pInB++;
+        *px = in;
+        in = *pInB++;
+        px[1] = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Read two elements from the row */
+        in = *pInB++;
+        *px = in;
+        in = *pInB++;
+        px[1] = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Read two elements from the row */
+        in = *pInB++;
+        *px = in;
+        in = *pInB++;
+        px[1] = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4U;
+
+      while (col > 0U)
+      {
+        /* Read two elements from the row */
+        in = *pInB++;
+        *px = in;
+        in = *pInB++;
+        px[1] = in;
+#else
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        *__SIMD32(px) = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        *__SIMD32(px) = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        *__SIMD32(px) = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        *__SIMD32(px) = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4U;
+
+      while (col > 0U)
+      {
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        *__SIMD32(px) = in;
+#endif
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB * 2;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i = i + 2U;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0U;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sumReal = 0;
+        sumImag = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 1;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i * 2;
+
+
+        /* matrix multiplication */
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+          /* read real and imag values from pSrcA buffer */
+          a = *pInA;
+          b = *(pInA + 1U);
+          /* read real and imag values from pSrcB buffer */
+          c = *pInB;
+          d = *(pInB + 1U);
+
+          /* Multiply and Accumlates */
+          sumReal += (q31_t) a *c;
+          sumImag += (q31_t) a *d;
+          sumReal -= (q31_t) b *d;
+          sumImag += (q31_t) b *c;
+
+          /* read next real and imag values from pSrcA buffer */
+          a = *(pInA + 2U);
+          b = *(pInA + 3U);
+          /* read next real and imag values from pSrcB buffer */
+          c = *(pInB + 2U);
+          d = *(pInB + 3U);
+
+          /* update pointer */
+          pInA += 4U;
+
+          /* Multiply and Accumlates */
+          sumReal += (q31_t) a *c;
+          sumImag += (q31_t) a *d;
+          sumReal -= (q31_t) b *d;
+          sumImag += (q31_t) b *c;
+          /* update pointer */
+          pInB += 4U;
+#else
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          pSourceA = *__SIMD32(pInA)++;
+          pSourceB = *__SIMD32(pInB)++;
+
+          /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+          prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+          prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+          prod2 = __SMUADX(pSourceA, pSourceB);
+          sumReal += (q63_t) prod1;
+          sumImag += (q63_t) prod2;
+
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          pSourceA = *__SIMD32(pInA)++;
+          pSourceB = *__SIMD32(pInB)++;
+
+          /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+          prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+          prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+          prod2 = __SMUADX(pSourceA, pSourceB);
+          sumReal += (q63_t) prod1;
+          sumImag += (q63_t) prod2;
+
+#endif /*      #ifdef UNALIGNED_SUPPORT_DISABLE */
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process odd column samples */
+        if ((numColsA & 0x1U) > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          a = *pInA++;
+          b = *pInA++;
+          c = *pInB++;
+          d = *pInB++;
+
+          /* Multiply and Accumlates */
+          sumReal += (q31_t) a *c;
+          sumImag += (q31_t) a *d;
+          sumReal -= (q31_t) b *d;
+          sumImag += (q31_t) b *c;
+
+#else
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          pSourceA = *__SIMD32(pInA)++;
+          pSourceB = *__SIMD32(pInB)++;
+
+          /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+          prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+          prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+          prod2 = __SMUADX(pSourceA, pSourceB);
+          sumReal += (q63_t) prod1;
+          sumImag += (q63_t) prod2;
+
+#endif /*      #ifdef UNALIGNED_SUPPORT_DISABLE */
+
+        }
+
+        /* Saturate and store the result in the destination buffer */
+
+        *px++ = (q15_t) (__SSAT(sumReal >> 15, 16));
+        *px++ = (q15_t) (__SSAT(sumImag >> 15, 16));
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while (col > 0U);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
new file mode 100644
index 0000000..a05440e
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
@@ -0,0 +1,282 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_cmplx_mult_q31.c
+ * Description:  Floating-point matrix multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup CmplxMatrixMult
+ * @{
+ */
+
+/**
+ * @brief Q31 Complex matrix multiplication
+ * @param[in]       *pSrcA points to the first input complex matrix structure
+ * @param[in]       *pSrcB points to the second input complex matrix structure
+ * @param[out]      *pDst points to output complex matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate
+ * multiplication results but provides only a single guard bit. There is no saturation
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and
+ * distorts the result. The input signals should be scaled down to avoid intermediate
+ * overflows. The input is thus scaled down by log2(numColsA) bits
+ * to avoid overflows, as a total of numColsA additions are performed internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ *
+ */
+
+arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  q63_t sumReal1, sumImag1;                      /* accumulator */
+  q31_t a0, b0, c0, d0;
+  q31_t a1, b1, c1, d1;
+
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0U, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + 2 * i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0U;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sumReal1 = 0.0;
+        sumImag1 = 0.0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* matrix multiplication        */
+        while (colCnt > 0U)
+        {
+
+          /* Reading real part of complex matrix A */
+          a0 = *pIn1;
+
+          /* Reading real part of complex matrix B */
+          c0 = *pIn2;
+
+          /* Reading imaginary part of complex matrix A */
+          b0 = *(pIn1 + 1U);
+
+          /* Reading imaginary part of complex matrix B */
+          d0 = *(pIn2 + 1U);
+
+          /* Multiply and Accumlates */
+          sumReal1 += (q63_t) a0 *c0;
+          sumImag1 += (q63_t) b0 *c0;
+
+          /* update pointers */
+          pIn1 += 2U;
+          pIn2 += 2 * numColsB;
+
+          /* Multiply and Accumlates */
+          sumReal1 -= (q63_t) b0 *d0;
+          sumImag1 += (q63_t) a0 *d0;
+
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          a1 = *pIn1;
+          c1 = *pIn2;
+          b1 = *(pIn1 + 1U);
+          d1 = *(pIn2 + 1U);
+
+          /* Multiply and Accumlates */
+          sumReal1 += (q63_t) a1 *c1;
+          sumImag1 += (q63_t) b1 *c1;
+
+          /* update pointers */
+          pIn1 += 2U;
+          pIn2 += 2 * numColsB;
+
+          /* Multiply and Accumlates */
+          sumReal1 -= (q63_t) b1 *d1;
+          sumImag1 += (q63_t) a1 *d1;
+
+          a0 = *pIn1;
+          c0 = *pIn2;
+
+          b0 = *(pIn1 + 1U);
+          d0 = *(pIn2 + 1U);
+
+          /* Multiply and Accumlates */
+          sumReal1 += (q63_t) a0 *c0;
+          sumImag1 += (q63_t) b0 *c0;
+
+          /* update pointers */
+          pIn1 += 2U;
+          pIn2 += 2 * numColsB;
+
+          /* Multiply and Accumlates */
+          sumReal1 -= (q63_t) b0 *d0;
+          sumImag1 += (q63_t) a0 *d0;
+
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+          a1 = *pIn1;
+          c1 = *pIn2;
+
+          b1 = *(pIn1 + 1U);
+          d1 = *(pIn2 + 1U);
+
+          /* Multiply and Accumlates */
+          sumReal1 += (q63_t) a1 *c1;
+          sumImag1 += (q63_t) b1 *c1;
+
+          /* update pointers */
+          pIn1 += 2U;
+          pIn2 += 2 * numColsB;
+
+          /* Multiply and Accumlates */
+          sumReal1 -= (q63_t) b1 *d1;
+          sumImag1 += (q63_t) a1 *d1;
+
+          /* Decrement the loop count */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4U;
+
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          a1 = *pIn1;
+          c1 = *pIn2;
+
+          b1 = *(pIn1 + 1U);
+          d1 = *(pIn2 + 1U);
+
+          /* Multiply and Accumlates */
+          sumReal1 += (q63_t) a1 *c1;
+          sumImag1 += (q63_t) b1 *c1;
+
+          /* update pointers */
+          pIn1 += 2U;
+          pIn2 += 2 * numColsB;
+
+          /* Multiply and Accumlates */
+          sumReal1 -= (q63_t) b1 *d1;
+          sumImag1 += (q63_t) a1 *d1;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = (q31_t) clip_q63_to_q31(sumReal1 >> 31);
+        *px++ = (q31_t) clip_q63_to_q31(sumImag1 >> 31);
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + 2U * j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while (col > 0U);
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + 2 * numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c
new file mode 100644
index 0000000..34399c7
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_init_f32.c
+ * Description:  Floating-point matrix initialization
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInit Matrix Initialization
+ *
+ * Initializes the underlying matrix data structure.
+ * The functions set the numRows,
+ * numCols, and pData fields
+ * of the matrix data structure.
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+/**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	   points to the matrix data array.
+   * @return        none
+   */
+
+void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c
new file mode 100644
index 0000000..6be7387
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c
@@ -0,0 +1,67 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_init_q15.c
+ * Description:  Q15 matrix initialization
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	   points to the matrix data array.
+   * @return        none
+   */
+
+void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c
new file mode 100644
index 0000000..c8a0839
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_init_q31.c
+ * Description:  Q31 matrix initialization
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInit Matrix Initialization
+ *
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	   points to the matrix data array.
+   * @return        none
+   */
+
+void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c
new file mode 100644
index 0000000..c0f8fc4
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c
@@ -0,0 +1,691 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_inverse_f32.c
+ * Description:  Floating-point matrix inverse
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInv Matrix Inverse
+ *
+ * Computes the inverse of a matrix.
+ *
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant
+ * is non-zero). The function checks that the input and output matrices are square and of the
+ * same size.
+ *
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix
+ * inversion of floating-point matrices.
+ *
+ * \par Algorithm
+ * The Gauss-Jordan method is used to find the inverse.
+ * The algorithm performs a sequence of elementary row-operations until it
+ * reduces the input matrix to an identity matrix. Applying the same sequence
+ * of elementary row-operations to an identity matrix yields the inverse matrix.
+ * If the input matrix is singular, then the algorithm terminates and returns error status
+ * ARM_MATH_SINGULAR.
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"
+ */
+
+/**
+ * @addtogroup MatrixInv
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in]       *pSrc points to input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns
+ * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size
+ * of the output matrix does not match the size of the input matrix.
+ * If the input matrix is found to be singular (non-invertible), then the function returns
+ * ARM_MATH_SINGULAR.  Otherwise, the function returns ARM_MATH_SUCCESS.
+ */
+
+arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */
+  float32_t *pOutT1, *pOutT2;                    /* Temporary output data matrix pointer */
+  float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */
+  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */
+  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */
+
+#if defined (ARM_MATH_DSP)
+  float32_t maxC;                                /* maximum value in the column */
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t Xchg, in = 0.0f, in1;                /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------
+	 * Matrix Inverse can be solved using elementary row operations.
+	 *
+	 *	Gauss-Jordan Method:
+	 *
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an
+	 *        augmented matrix as follows:
+	 *				        _ 	      	       _         _	       _
+	 *					   |  a11  a12 | 1   0  |       |  X11 X12  |
+	 *					   |           |        |   =   |           |
+	 *					   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|
+	 *
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.
+	 *
+	 *		3. Begin with the first row. Let i = 1.
+	 *
+	 *	    4. Check to see if the pivot for column i is the greatest of the column.
+	 *		   The pivot is the element of the main diagonal that is on the current row.
+	 *		   For instance, if working with row i, then the pivot element is aii.
+	 *		   If the pivot is not the most significant of the columns, exchange that row with a row
+	 *		   below it that does contain the most significant value in column i. If the most
+	 *         significant value of the column is zero, then an inverse to that matrix does not exist.
+	 *		   The most significant value of the column is the absolute maximum.
+	 *
+	 *	    5. Divide every element of row i by the pivot.
+	 *
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and
+	 *		   a multiple of row i so that each new element in column i below row i is zero.
+	 *
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+	 *		   for every element below and above the main diagonal.
+	 *
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).
+	 *		   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pOutT1 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while (rowCnt > 0U)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while (j > 0U)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pOutT1++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1U;
+      while (j > 0U)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0U;
+
+    while (loopCnt > 0U)
+    {
+      /* Check if the pivot element is zero..
+       * If it is zero then interchange the row with non zero row below.
+       * If there is no non zero element to replace in the rows below,
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points
+       * to the pivot element of the particular row  */
+      pOutT1 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Grab the most significant value from column l */
+      maxC = 0;
+      for (i = l; i < numRows; i++)
+      {
+        maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
+        pInT1 += numCols;
+      }
+
+      /* Update the status if the matrix is singular */
+      if (maxC == 0.0f)
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Restore pInT1  */
+      pInT1 = pIn;
+
+      /* Destination pointer modifier */
+      k = 1U;
+
+      /* Check if the pivot element is the most significant of the column */
+      if ( (in > 0.0f ? in : -in) != maxC)
+      {
+        /* Loop over the number rows present below */
+        i = numRows - (l + 1U);
+
+        while (i > 0U)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pOutT2 = pOutT1 + (numCols * k);
+
+          /* Look for the most significant element to
+           * replace in the rows below */
+          if ((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
+          {
+            /* Loop over number of columns
+             * to the right of the pilot element */
+            j = numCols - l;
+
+            while (j > 0U)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Loop over number of columns of the destination matrix */
+            j = numCols;
+
+            while (j > 0U)
+            {
+              /* Exchange the row elements of the destination matrix */
+              Xchg = *pOutT2;
+              *pOutT2++ = *pOutT1;
+              *pOutT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1U;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+
+          /* Decrement the loop counter */
+          i--;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if ((flag != 1U) && (in == 0.0f))
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *pPivotRowIn;
+
+      /* Loop over number of columns
+       * to the right of the pilot element */
+      j = (numCols - l);
+
+      while (j > 0U)
+      {
+        /* Divide each element of the row of the input matrix
+         * by the pivot element */
+        in1 = *pInT1;
+        *pInT1++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Loop over number of columns of the destination matrix */
+      j = numCols;
+
+      while (j > 0U)
+      {
+        /* Divide each element of the row of the destination matrix
+         * by the pivot element */
+        in1 = *pInT2;
+        *pInT2++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      /* index used to check for pivot element */
+      i = 0U;
+
+      /* Loop over number of rows */
+      /*  to be replaced by the sum of that row and a multiple of row i */
+      k = numRows;
+
+      while (k > 0U)
+      {
+        /* Check for the pivot element */
+        if (i == l)
+        {
+          /* If the processing element is the pivot element,
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,
+             to replace the elements in the input matrix */
+          j = (numCols - l);
+
+          while (j > 0U)
+          {
+            /* Replace the element by the sum of that row
+               and a multiple of the reference row  */
+            in1 = *pInT1;
+            *pInT1++ = in1 - (in * *pPRT_in++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+          /* Loop over the number of columns to
+             replace the elements in the destination matrix */
+          j = numCols;
+
+          while (j > 0U)
+          {
+            /* Replace the element by the sum of that row
+               and a multiple of the reference row  */
+            in1 = *pInT2;
+            *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+        }
+
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+
+        /* Decrement the loop counter */
+        k--;
+
+        /* Increment the pivot index */
+        i++;
+      }
+
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t Xchg, in = 0.0f;                     /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------
+	 * Matrix Inverse can be solved using elementary row operations.
+	 *
+	 *	Gauss-Jordan Method:
+	 *
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an
+	 *        augmented matrix as follows:
+	 *				        _  _	      _	    _	   _   _         _	       _
+	 *					   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |
+	 *					   |  |            | | |        |   |   =   |           |
+	 *					   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|
+	 *
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.
+	 *
+	 *		3. Begin with the first row. Let i = 1.
+	 *
+	 *	    4. Check to see if the pivot for row i is zero.
+	 *		   The pivot is the element of the main diagonal that is on the current row.
+	 *		   For instance, if working with row i, then the pivot element is aii.
+	 *		   If the pivot is zero, exchange that row with a row below it that does not
+	 *		   contain a zero in column i. If this is not possible, then an inverse
+	 *		   to that matrix does not exist.
+	 *
+	 *	    5. Divide every element of row i by the pivot.
+	 *
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and
+	 *		   a multiple of row i so that each new element in column i below row i is zero.
+	 *
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+	 *		   for every element below and above the main diagonal.
+	 *
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, src).
+	 *		   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pOutT1 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while (rowCnt > 0U)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while (j > 0U)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pOutT1++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1U;
+      while (j > 0U)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0U;
+    //for(loopCnt = 0U; loopCnt < numCols; loopCnt++)
+    while (loopCnt > 0U)
+    {
+      /* Check if the pivot element is zero..
+       * If it is zero then interchange the row with non zero row below.
+       * If there is no non zero element to replace in the rows below,
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points
+       * to the pivot element of the particular row  */
+      pOutT1 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1U;
+
+      /* Check if the pivot element is zero */
+      if (*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        for (i = (l + 1U); i < numRows; i++)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pOutT2 = pOutT1 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to
+           * replace in the rows below */
+          if (*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns
+             * to the right of the pilot element */
+            for (j = 0U; j < (numCols - l); j++)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+            }
+
+            for (j = 0U; j < numCols; j++)
+            {
+              Xchg = *pOutT2;
+              *pOutT2++ = *pOutT1;
+              *pOutT1++ = Xchg;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1U;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if ((flag != 1U) && (in == 0.0f))
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pOutT1 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns
+       * to the right of the pilot element */
+      for (j = 0U; j < (numCols - l); j++)
+      {
+        /* Divide each element of the row of the input matrix
+         * by the pivot element */
+        *pInT1 = *pInT1 / in;
+        pInT1++;
+      }
+      for (j = 0U; j < numCols; j++)
+      {
+        /* Divide each element of the row of the destination matrix
+         * by the pivot element */
+        *pOutT1 = *pOutT1 / in;
+        pOutT1++;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pOutT1 = pOut;
+
+      for (i = 0U; i < numRows; i++)
+      {
+        /* Check for the pivot element */
+        if (i == l)
+        {
+          /* If the processing element is the pivot element,
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+          pOutT1 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,
+             to replace the elements in the input matrix */
+          for (j = 0U; j < (numCols - l); j++)
+          {
+            /* Replace the element by the sum of that row
+               and a multiple of the reference row  */
+            *pInT1 = *pInT1 - (in * *pPRT_in++);
+            pInT1++;
+          }
+          /* Loop over the number of columns to
+             replace the elements in the destination matrix */
+          for (j = 0U; j < numCols; j++)
+          {
+            /* Replace the element by the sum of that row
+               and a multiple of the reference row  */
+            *pOutT1 = *pOutT1 - (in * *pPRT_pDst++);
+            pOutT1++;
+          }
+
+        }
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+      }
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+    if ((flag != 1U) && (in == 0.0f))
+    {
+      pIn = pSrc->pData;
+      for (i = 0; i < numRows * numCols; i++)
+      {
+        if (pIn[i] != 0.0f)
+            break;
+      }
+
+      if (i == numRows * numCols)
+        status = ARM_MATH_SINGULAR;
+    }
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixInv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c
new file mode 100644
index 0000000..441376b
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c
@@ -0,0 +1,691 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_inverse_f64.c
+ * Description:  Floating-point matrix inverse
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInv Matrix Inverse
+ *
+ * Computes the inverse of a matrix.
+ *
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant
+ * is non-zero). The function checks that the input and output matrices are square and of the
+ * same size.
+ *
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix
+ * inversion of floating-point matrices.
+ *
+ * \par Algorithm
+ * The Gauss-Jordan method is used to find the inverse.
+ * The algorithm performs a sequence of elementary row-operations until it
+ * reduces the input matrix to an identity matrix. Applying the same sequence
+ * of elementary row-operations to an identity matrix yields the inverse matrix.
+ * If the input matrix is singular, then the algorithm terminates and returns error status
+ * ARM_MATH_SINGULAR.
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"
+ */
+
+/**
+ * @addtogroup MatrixInv
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in]       *pSrc points to input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns
+ * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size
+ * of the output matrix does not match the size of the input matrix.
+ * If the input matrix is found to be singular (non-invertible), then the function returns
+ * ARM_MATH_SINGULAR.  Otherwise, the function returns ARM_MATH_SUCCESS.
+ */
+
+arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * pSrc,
+  arm_matrix_instance_f64 * pDst)
+{
+  float64_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float64_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float64_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */
+  float64_t *pOutT1, *pOutT2;                    /* Temporary output data matrix pointer */
+  float64_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */
+  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */
+  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */
+
+#if defined (ARM_MATH_DSP)
+  float64_t maxC;                                /* maximum value in the column */
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float64_t Xchg, in = 0.0f, in1;                /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------
+	 * Matrix Inverse can be solved using elementary row operations.
+	 *
+	 *	Gauss-Jordan Method:
+	 *
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an
+	 *        augmented matrix as follows:
+	 *				        _ 	      	       _         _	       _
+	 *					   |  a11  a12 | 1   0  |       |  X11 X12  |
+	 *					   |           |        |   =   |           |
+	 *					   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|
+	 *
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.
+	 *
+	 *		3. Begin with the first row. Let i = 1.
+	 *
+	 *	    4. Check to see if the pivot for column i is the greatest of the column.
+	 *		   The pivot is the element of the main diagonal that is on the current row.
+	 *		   For instance, if working with row i, then the pivot element is aii.
+	 *		   If the pivot is not the most significant of the columns, exchange that row with a row
+	 *		   below it that does contain the most significant value in column i. If the most
+	 *         significant value of the column is zero, then an inverse to that matrix does not exist.
+	 *		   The most significant value of the column is the absolute maximum.
+	 *
+	 *	    5. Divide every element of row i by the pivot.
+	 *
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and
+	 *		   a multiple of row i so that each new element in column i below row i is zero.
+	 *
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+	 *		   for every element below and above the main diagonal.
+	 *
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).
+	 *		   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pOutT1 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while (rowCnt > 0U)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while (j > 0U)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pOutT1++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1U;
+      while (j > 0U)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0U;
+
+    while (loopCnt > 0U)
+    {
+      /* Check if the pivot element is zero..
+       * If it is zero then interchange the row with non zero row below.
+       * If there is no non zero element to replace in the rows below,
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points
+       * to the pivot element of the particular row  */
+      pOutT1 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Grab the most significant value from column l */
+      maxC = 0;
+      for (i = l; i < numRows; i++)
+      {
+        maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
+        pInT1 += numCols;
+      }
+
+      /* Update the status if the matrix is singular */
+      if (maxC == 0.0f)
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Restore pInT1  */
+      pInT1 = pIn;
+
+      /* Destination pointer modifier */
+      k = 1U;
+
+      /* Check if the pivot element is the most significant of the column */
+      if ( (in > 0.0f ? in : -in) != maxC)
+      {
+        /* Loop over the number rows present below */
+        i = numRows - (l + 1U);
+
+        while (i > 0U)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pOutT2 = pOutT1 + (numCols * k);
+
+          /* Look for the most significant element to
+           * replace in the rows below */
+          if ((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
+          {
+            /* Loop over number of columns
+             * to the right of the pilot element */
+            j = numCols - l;
+
+            while (j > 0U)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Loop over number of columns of the destination matrix */
+            j = numCols;
+
+            while (j > 0U)
+            {
+              /* Exchange the row elements of the destination matrix */
+              Xchg = *pOutT2;
+              *pOutT2++ = *pOutT1;
+              *pOutT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1U;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+
+          /* Decrement the loop counter */
+          i--;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if ((flag != 1U) && (in == 0.0f))
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *pPivotRowIn;
+
+      /* Loop over number of columns
+       * to the right of the pilot element */
+      j = (numCols - l);
+
+      while (j > 0U)
+      {
+        /* Divide each element of the row of the input matrix
+         * by the pivot element */
+        in1 = *pInT1;
+        *pInT1++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Loop over number of columns of the destination matrix */
+      j = numCols;
+
+      while (j > 0U)
+      {
+        /* Divide each element of the row of the destination matrix
+         * by the pivot element */
+        in1 = *pInT2;
+        *pInT2++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      /* index used to check for pivot element */
+      i = 0U;
+
+      /* Loop over number of rows */
+      /*  to be replaced by the sum of that row and a multiple of row i */
+      k = numRows;
+
+      while (k > 0U)
+      {
+        /* Check for the pivot element */
+        if (i == l)
+        {
+          /* If the processing element is the pivot element,
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,
+             to replace the elements in the input matrix */
+          j = (numCols - l);
+
+          while (j > 0U)
+          {
+            /* Replace the element by the sum of that row
+               and a multiple of the reference row  */
+            in1 = *pInT1;
+            *pInT1++ = in1 - (in * *pPRT_in++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+          /* Loop over the number of columns to
+             replace the elements in the destination matrix */
+          j = numCols;
+
+          while (j > 0U)
+          {
+            /* Replace the element by the sum of that row
+               and a multiple of the reference row  */
+            in1 = *pInT2;
+            *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+        }
+
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+
+        /* Decrement the loop counter */
+        k--;
+
+        /* Increment the pivot index */
+        i++;
+      }
+
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float64_t Xchg, in = 0.0f;                     /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------
+	 * Matrix Inverse can be solved using elementary row operations.
+	 *
+	 *	Gauss-Jordan Method:
+	 *
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an
+	 *        augmented matrix as follows:
+	 *				        _  _	      _	    _	   _   _         _	       _
+	 *					   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |
+	 *					   |  |            | | |        |   |   =   |           |
+	 *					   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|
+	 *
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.
+	 *
+	 *		3. Begin with the first row. Let i = 1.
+	 *
+	 *	    4. Check to see if the pivot for row i is zero.
+	 *		   The pivot is the element of the main diagonal that is on the current row.
+	 *		   For instance, if working with row i, then the pivot element is aii.
+	 *		   If the pivot is zero, exchange that row with a row below it that does not
+	 *		   contain a zero in column i. If this is not possible, then an inverse
+	 *		   to that matrix does not exist.
+	 *
+	 *	    5. Divide every element of row i by the pivot.
+	 *
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and
+	 *		   a multiple of row i so that each new element in column i below row i is zero.
+	 *
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+	 *		   for every element below and above the main diagonal.
+	 *
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, src).
+	 *		   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pOutT1 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while (rowCnt > 0U)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while (j > 0U)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pOutT1++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1U;
+      while (j > 0U)
+      {
+        *pOutT1++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0U;
+    //for(loopCnt = 0U; loopCnt < numCols; loopCnt++)
+    while (loopCnt > 0U)
+    {
+      /* Check if the pivot element is zero..
+       * If it is zero then interchange the row with non zero row below.
+       * If there is no non zero element to replace in the rows below,
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points
+       * to the pivot element of the particular row  */
+      pOutT1 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1U;
+
+      /* Check if the pivot element is zero */
+      if (*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        for (i = (l + 1U); i < numRows; i++)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pOutT2 = pOutT1 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to
+           * replace in the rows below */
+          if (*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns
+             * to the right of the pilot element */
+            for (j = 0U; j < (numCols - l); j++)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+            }
+
+            for (j = 0U; j < numCols; j++)
+            {
+              Xchg = *pOutT2;
+              *pOutT2++ = *pOutT1;
+              *pOutT1++ = Xchg;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1U;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if ((flag != 1U) && (in == 0.0f))
+      {
+        return ARM_MATH_SINGULAR;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pOutT1 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns
+       * to the right of the pilot element */
+      for (j = 0U; j < (numCols - l); j++)
+      {
+        /* Divide each element of the row of the input matrix
+         * by the pivot element */
+        *pInT1 = *pInT1 / in;
+        pInT1++;
+      }
+      for (j = 0U; j < numCols; j++)
+      {
+        /* Divide each element of the row of the destination matrix
+         * by the pivot element */
+        *pOutT1 = *pOutT1 / in;
+        pOutT1++;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pOutT1 = pOut;
+
+      for (i = 0U; i < numRows; i++)
+      {
+        /* Check for the pivot element */
+        if (i == l)
+        {
+          /* If the processing element is the pivot element,
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+          pOutT1 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,
+             to replace the elements in the input matrix */
+          for (j = 0U; j < (numCols - l); j++)
+          {
+            /* Replace the element by the sum of that row
+               and a multiple of the reference row  */
+            *pInT1 = *pInT1 - (in * *pPRT_in++);
+            pInT1++;
+          }
+          /* Loop over the number of columns to
+             replace the elements in the destination matrix */
+          for (j = 0U; j < numCols; j++)
+          {
+            /* Replace the element by the sum of that row
+               and a multiple of the reference row  */
+            *pOutT1 = *pOutT1 - (in * *pPRT_pDst++);
+            pOutT1++;
+          }
+
+        }
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+      }
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+    if ((flag != 1U) && (in == 0.0f))
+    {
+      pIn = pSrc->pData;
+      for (i = 0; i < numRows * numCols; i++)
+      {
+        if (pIn[i] != 0.0f)
+            break;
+      }
+
+      if (i == numRows * numCols)
+        status = ARM_MATH_SINGULAR;
+    }
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixInv group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c
new file mode 100644
index 0000000..fa9f03f
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c
@@ -0,0 +1,274 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_mult_f32.c
+ * Description:  Floating-point matrix multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixMult Matrix Multiplication
+ *
+ * Multiplies two matrices.
+ *
+ * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"
+
+ * Matrix multiplication is only defined if the number of columns of the
+ * first matrix equals the number of rows of the second matrix.
+ * Multiplying an M x N matrix with an N x P matrix results
+ * in an M x P matrix.
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of
+ * pSrcA and pSrcB are equal; and (2) that the size of the output
+ * matrix equals the outer dimensions of pSrcA and pSrcB.
+ */
+
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix multiplication.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t in1, in2, in3, in4;
+  uint16_t col, i = 0U, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0U;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2U;
+
+        /* matrix multiplication        */
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          in3 = *pIn2;
+          pIn2 += numColsB;
+          in1 = pIn1[0];
+          in2 = pIn1[1];
+          sum += in1 * in3;
+          in4 = *pIn2;
+          pIn2 += numColsB;
+          sum += in2 * in4;
+
+          in3 = *pIn2;
+          pIn2 += numColsB;
+          in1 = pIn1[2];
+          in2 = pIn1[3];
+          sum += in1 * in3;
+          in4 = *pIn2;
+          pIn2 += numColsB;
+          sum += in2 * in4;
+          pIn1 += 4U;
+
+          /* Decrement the loop count */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4U;
+
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while (col > 0U);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pInB = pSrcB->pData;                /* input data matrix pointer B */
+  uint16_t col, i = 0U, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pInA with each column in pInB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while (col > 0U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
new file mode 100644
index 0000000..796df88
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
@@ -0,0 +1,525 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_mult_fast_q15.c
+ * Description:  Q15 matrix multiplication (fast variant)
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @param[in]       *pState points to the array for storing intermediate results
+ * @return          The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The difference between the function arm_mat_mult_q15() and this fast variant is that
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.
+ * The result of each 1.15 x 1.15 multiplication is truncated to
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
+ * format. Finally, the accumulator is saturated and converted to a 1.15 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides
+ * less precision since it discards the low 16 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down one of the input matrices by log2(numColsA) bits to
+ * avoid overflows, as a total of numColsA additions are computed internally for each
+ * output element.
+ *
+ * \par
+ * See arm_mat_mult_q15() for a slower implementation of this function
+ * which uses 64-bit accumulation to provide higher precision.
+ */
+
+arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState)
+{
+  q31_t sum;                                     /* accumulator */
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint32_t col, i = 0U, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q31_t inA1, inA2, inB1, inB2;
+  q31_t sum2, sum3, sum4;
+  q15_t *pInA2, *pInB2, *px2;
+  uint32_t j = 0;
+
+#else
+
+  q15_t in;                                      /* Temporary variable to hold the input value */
+  q15_t inA1, inA2, inB1, inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while (col > 0U)
+      {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+#else
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4U;
+
+      while (col > 0U)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0U;
+    px = pDst->pData;
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    /* Process two rows from matrix A at a time and output two rows at a time */
+    row = row >> 1;
+    px2 = px + numColsB;
+#endif
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    while (row > 0U)
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+      /* Process two (transposed) columns from matrix B at a time */
+      col = col >> 1;
+      j = 0;
+#endif
+
+      /* column loop */
+      while (col > 0U)
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pInA to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+        sum2 = 0;
+        sum3 = 0;
+        sum4 = 0;
+        pInB  = pSrcBT + j;
+        pInA2 = pInA + numColsA;
+        pInB2 = pInB + numRowsB;
+
+        /* Read in two elements at once - alows dual MAC instruction */
+        colCnt = numColsA >> 1;
+#else
+        colCnt = numColsA >> 2;
+#endif
+
+        /* matrix multiplication */
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+          inA1 = *__SIMD32(pInA)++;
+          inB1 = *__SIMD32(pInB)++;
+          inA2 = *__SIMD32(pInA2)++;
+          inB2 = *__SIMD32(pInB2)++;
+
+          sum  = __SMLAD(inA1, inB1, sum);
+          sum2 = __SMLAD(inA1, inB2, sum2);
+          sum3 = __SMLAD(inA2, inB1, sum3);
+          sum4 = __SMLAD(inA2, inB2, sum4);
+
+#else
+
+          inA1 = *pInA;
+          inB1 = *pInB;
+          sum += inA1 * inB1;
+
+          inA2 = pInA[1];
+          inB2 = pInB[1];
+          sum += inA2 * inB2;
+
+          inA1 = pInA[2];
+          inB1 = pInB[2];
+          sum += inA1 * inB1;
+
+          inA2 = pInA[3];
+          inB2 = pInB[3];
+          sum += inA2 * inB2;
+
+          pInA += 4;
+          pInB += 4;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process odd column samples */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+        if (numColsA & 1U) {
+          inA1 = *pInA++;
+          inB1 = *pInB++;
+          inA2 = *pInA2++;
+          inB2 = *pInB2++;
+          sum  += inA1 * inB1;
+          sum2 += inA1 * inB2;
+          sum3 += inA2 * inB1;
+          sum4 += inA2 * inB2;
+        }
+#else
+        colCnt = numColsA % 0x4U;
+
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += (q31_t) (*pInA++) * (*pInB++);
+
+          colCnt--;
+        }
+#endif
+
+        /* Saturate and store the result in the destination buffer */
+        *px++  = (q15_t) (sum >> 15);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+        *px++  = (q15_t) (sum2 >> 15);
+        *px2++ = (q15_t) (sum3 >> 15);
+        *px2++ = (q15_t) (sum4 >> 15);
+        j += numRowsB * 2;
+#endif
+
+        /* Decrement the column loop counter */
+        col--;
+
+      }
+
+      i = i + numColsA;
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+      i = i + numColsA;
+      px = px2 + (numColsB & 1U);
+      px2 = px + numColsB;
+#endif
+
+      /* Decrement the row loop counter */
+      row--;
+
+    }
+
+    /* Compute any remaining odd row/column below */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    /* Compute remaining output column */
+    if (numColsB & 1U) {
+
+      /* Avoid redundant computation of last element */
+      row = numRowsA & (~0x1);
+
+      /* Point to remaining unfilled column in output matrix */
+      px = pDst->pData+numColsB-1;
+      pInA = pSrcA->pData;
+
+      /* row loop */
+      while (row > 0)
+      {
+
+        /* point to last column in matrix B */
+        pInB  = pSrcBT + numRowsB*(numColsB-1);
+
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum  = 0;
+
+        /* Compute 4 columns at once */
+        colCnt = numColsA >> 2;
+
+        /* matrix multiplication */
+        while (colCnt > 0U)
+        {
+          inA1 = *__SIMD32(pInA)++;
+          inA2 = *__SIMD32(pInA)++;
+          inB1 = *__SIMD32(pInB)++;
+          inB2 = *__SIMD32(pInB)++;
+
+          sum  = __SMLAD(inA1, inB1, sum);
+          sum  = __SMLAD(inA2, inB2, sum);
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        colCnt = numColsA & 3U;
+        while (colCnt > 0U) {
+          sum += (q31_t) (*pInA++) * (*pInB++);
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px  = (q15_t) (sum  >> 15);
+        px += numColsB;
+
+        /* Decrement the row loop counter */
+        row--;
+      }
+    }
+
+    /* Compute remaining output row */
+    if (numRowsA & 1U) {
+
+      /* point to last row in output matrix */
+      px = pDst->pData+(numColsB)*(numRowsA-1);
+
+      pInB  = pSrcBT;
+      col = numColsB;
+      i = 0U;
+
+      /* col loop */
+      while (col > 0)
+      {
+
+        /* point to last row in matrix A */
+        pInA = pSrcA->pData + (numRowsA-1)*numColsA;
+
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum  = 0;
+
+        /* Compute 4 columns at once */
+        colCnt = numColsA >> 2;
+
+        /* matrix multiplication */
+        while (colCnt > 0U)
+        {
+          inA1 = *__SIMD32(pInA)++;
+          inA2 = *__SIMD32(pInA)++;
+          inB1 = *__SIMD32(pInB)++;
+          inB2 = *__SIMD32(pInB)++;
+
+          sum  = __SMLAD(inA1, inB1, sum);
+          sum  = __SMLAD(inA2, inB2, sum);
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        colCnt = numColsA & 3U;
+        while (colCnt > 0U) {
+          sum += (q31_t) (*pInA++) * (*pInB++);
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++  = (q15_t) (sum  >> 15);
+
+        /* Decrement the col loop counter */
+        col--;
+      }
+    }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
new file mode 100644
index 0000000..bff3177
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_mult_fast_q31.c
+ * Description:  Q31 matrix multiplication (fast variant)
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return          The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The difference between the function arm_mat_mult_q31() and this fast variant is that
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.
+ * The result of each 1.31 x 1.31 multiplication is truncated to
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
+ * format. Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides
+ * less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down one of the input matrices by log2(numColsA) bits to
+ * avoid overflows, as a total of numColsA additions are computed internally for each
+ * output element.
+ *
+ * \par
+ * See arm_mat_mult_q31() for a slower implementation of this function
+ * which uses 64-bit accumulation to provide higher precision.
+ */
+
+arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint32_t col, i = 0U, j, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+  q31_t inA1, inB1;
+
+#if defined (ARM_MATH_DSP)
+
+  q31_t sum2, sum3, sum4;
+  q31_t inA2, inB2;
+  q31_t *pInA2;
+  q31_t *px2;
+
+#endif
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    px = pDst->pData;
+
+#if defined (ARM_MATH_DSP)
+    row = row >> 1;
+    px2 = px + numColsB;
+#endif
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    while (row > 0U)
+    {
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set
+       ** to the starting address of the pSrcB data */
+      pInB = pSrcB->pData;
+
+      j = 0U;
+
+#if defined (ARM_MATH_DSP)
+      col = col >> 1;
+#endif
+
+      /* column loop */
+      while (col > 0U)
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate data pointers */
+        pInA = pSrcA->pData + i;
+        pInB  = pSrcB->pData + j;
+
+#if defined (ARM_MATH_DSP)
+        sum2 = 0;
+        sum3 = 0;
+        sum4 = 0;
+        pInA2 = pInA + numColsA;
+        colCnt = numColsA;
+#else
+        colCnt = numColsA >> 2;
+#endif
+
+        /* matrix multiplication */
+        while (colCnt > 0U)
+        {
+
+#if defined (ARM_MATH_DSP)
+          inA1 = *pInA++;
+          inB1 = pInB[0];
+          inA2 = *pInA2++;
+          inB2 = pInB[1];
+          pInB += numColsB;
+
+          sum  = __SMMLA(inA1, inB1, sum);
+          sum2 = __SMMLA(inA1, inB2, sum2);
+          sum3 = __SMMLA(inA2, inB1, sum3);
+          sum4 = __SMMLA(inA2, inB2, sum4);
+#else
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          inB1 = *pInB;
+          pInB += numColsB;
+          inA1 = pInA[0];
+          sum = __SMMLA(inA1, inB1, sum);
+
+          inB1 = *pInB;
+          pInB += numColsB;
+          inA1 = pInA[1];
+          sum = __SMMLA(inA1, inB1, sum);
+
+          inB1 = *pInB;
+          pInB += numColsB;
+          inA1 = pInA[2];
+          sum = __SMMLA(inA1, inB1, sum);
+
+          inB1 = *pInB;
+          pInB += numColsB;
+          inA1 = pInA[3];
+          sum = __SMMLA(inA1, inB1, sum);
+
+          pInA += 4U;
+#endif
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+#ifdef ARM_MATH_CM0_FAMILY
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here. */
+        colCnt = numColsA % 0x4U;
+        while (colCnt > 0U)
+        {
+          sum = __SMMLA(*pInA++, *pInB, sum);
+          pInB += numColsB;
+          colCnt--;
+        }
+        j++;
+#endif
+
+        /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+        *px++  = sum << 1;
+
+#if defined (ARM_MATH_DSP)
+        *px++  = sum2 << 1;
+        *px2++ = sum3 << 1;
+        *px2++ = sum4 << 1;
+        j += 2;
+#endif
+
+        /* Decrement the column loop counter */
+        col--;
+
+      }
+
+      i = i + numColsA;
+
+#if defined (ARM_MATH_DSP)
+      i = i + numColsA;
+      px = px2 + (numColsB & 1U);
+      px2 = px + numColsB;
+#endif
+
+      /* Decrement the row loop counter */
+      row--;
+
+    }
+
+    /* Compute any remaining odd row/column below */
+
+#if defined (ARM_MATH_DSP)
+
+    /* Compute remaining output column */
+    if (numColsB & 1U) {
+
+      /* Avoid redundant computation of last element */
+      row = numRowsA & (~0x1);
+
+      /* Point to remaining unfilled column in output matrix */
+      px = pDst->pData+numColsB-1;
+      pInA = pSrcA->pData;
+
+      /* row loop */
+      while (row > 0)
+      {
+
+        /* point to last column in matrix B */
+        pInB  = pSrcB->pData + numColsB-1;
+
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum  = 0;
+
+        /* Compute 4 columns at once */
+        colCnt = numColsA >> 2;
+
+        /* matrix multiplication */
+        while (colCnt > 0U)
+        {
+          inA1 = *pInA++;
+          inA2 = *pInA++;
+          inB1 = *pInB;
+          pInB += numColsB;
+          inB2 = *pInB;
+          pInB += numColsB;
+          sum = __SMMLA(inA1, inB1, sum);
+          sum = __SMMLA(inA2, inB2, sum);
+
+          inA1 = *pInA++;
+          inA2 = *pInA++;
+          inB1 = *pInB;
+          pInB += numColsB;
+          inB2 = *pInB;
+          pInB += numColsB;
+          sum = __SMMLA(inA1, inB1, sum);
+          sum = __SMMLA(inA2, inB2, sum);
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        colCnt = numColsA & 3U;
+        while (colCnt > 0U) {
+          sum = __SMMLA(*pInA++, *pInB, sum);
+          pInB += numColsB;
+          colCnt--;
+        }
+
+        /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+        *px = sum << 1;
+        px += numColsB;
+
+        /* Decrement the row loop counter */
+        row--;
+      }
+    }
+
+    /* Compute remaining output row */
+    if (numRowsA & 1U) {
+
+      /* point to last row in output matrix */
+      px = pDst->pData+(numColsB)*(numRowsA-1);
+
+      col = numColsB;
+      i = 0U;
+
+      /* col loop */
+      while (col > 0)
+      {
+
+        /* point to last row in matrix A */
+        pInA = pSrcA->pData + (numRowsA-1)*numColsA;
+        pInB  = pSrcB->pData + i;
+
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum  = 0;
+
+        /* Compute 4 columns at once */
+        colCnt = numColsA >> 2;
+
+        /* matrix multiplication */
+        while (colCnt > 0U)
+        {
+          inA1 = *pInA++;
+          inA2 = *pInA++;
+          inB1 = *pInB;
+          pInB += numColsB;
+          inB2 = *pInB;
+          pInB += numColsB;
+          sum = __SMMLA(inA1, inB1, sum);
+          sum = __SMMLA(inA2, inB2, sum);
+
+          inA1 = *pInA++;
+          inA2 = *pInA++;
+          inB1 = *pInB;
+          pInB += numColsB;
+          inB2 = *pInB;
+          pInB += numColsB;
+          sum = __SMMLA(inA1, inB1, sum);
+          sum = __SMMLA(inA2, inB2, sum);
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        colCnt = numColsA & 3U;
+        while (colCnt > 0U) {
+          sum = __SMMLA(*pInA++, *pInB, sum);
+          pInB += numColsB;
+          colCnt--;
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px++ = sum << 1;
+        i++;
+
+        /* Decrement the col loop counter */
+        col--;
+      }
+    }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c
new file mode 100644
index 0000000..abd55bd
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c
@@ -0,0 +1,457 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_mult_q15.c
+ * Description:  Q15 matrix multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @param[in]       *pState points to the array for storing intermediate results (Unused)
+ * @return          The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to
+ * 1.15 format.
+ *
+ * \par
+ * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ */
+
+arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState)
+{
+  q63_t sum;                                     /* accumulator */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0U, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q31_t pSourceA1, pSourceB1, pSourceA2, pSourceB2;
+
+#else
+
+  q15_t in;                                      /* Temporary variable to hold the input value */
+  q15_t inA1, inB1, inA2, inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while (col > 0U)
+      {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+#else
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+       /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4U;
+
+      while (col > 0U)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0U;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+
+        /* matrix multiplication */
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          pSourceA1 = *__SIMD32(pInA)++;
+          pSourceB1 = *__SIMD32(pInB)++;
+
+          pSourceA2 = *__SIMD32(pInA)++;
+          pSourceB2 = *__SIMD32(pInB)++;
+
+          /* Multiply and Accumlates */
+          sum = __SMLALD(pSourceA1, pSourceB1, sum);
+          sum = __SMLALD(pSourceA2, pSourceB2, sum);
+
+#else
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          inA1 = *pInA++;
+          inB1 = *pInB++;
+          inA2 = *pInA++;
+          /* Multiply and Accumlates */
+          sum += inA1 * inB1;
+          inB2 = *pInB++;
+
+          inA1 = *pInA++;
+          inB1 = *pInB++;
+          /* Multiply and Accumlates */
+          sum += inA2 * inB2;
+          inA2 = *pInA++;
+          inB2 = *pInB++;
+
+          /* Multiply and Accumlates */
+          sum += inA1 * inB1;
+          sum += inA2 * inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process remaining column samples */
+        colCnt = numColsA & 3U;
+
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pInA++ * *pInB++;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px = (q15_t) (__SSAT((sum >> 15), 16));
+        px++;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while (col > 0U);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0U, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q31_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
+        /* Saturate and store the result in the destination buffer */
+        *px++ = (q15_t) __SSAT((sum >> 15), 16);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while (col > 0U);
+
+      /* Update the pointer pSrcA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c
new file mode 100644
index 0000000..2ce3637
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c
@@ -0,0 +1,282 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_mult_q31.c
+ * Description:  Q31 matrix multiplication
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate
+ * multiplication results but provides only a single guard bit. There is no saturation
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and
+ * distorts the result. The input signals should be scaled down to avoid intermediate
+ * overflows. The input is thus scaled down by log2(numColsA) bits
+ * to avoid overflows, as a total of numColsA additions are performed internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ *
+ */
+
+arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0U, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+  q31_t a0, a1, a2, a3, b0, b1, b2, b3;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0U;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+
+        /* matrix multiplication */
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          b0 = *pIn2;
+          pIn2 += numColsB;
+
+          a0 = *pIn1++;
+          a1 = *pIn1++;
+
+          b1 = *pIn2;
+          pIn2 += numColsB;
+          b2 = *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) a0 *b0;
+          sum += (q63_t) a1 *b1;
+
+          a2 = *pIn1++;
+          a3 = *pIn1++;
+
+          b3 = *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) a2 *b2;
+          sum += (q63_t) a3 *b3;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4U;
+
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) (sum >> 31);
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = (pSrcB->pData) + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while (col > 0U);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  uint16_t col, i = 0U, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while (colCnt > 0U)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) clip_q63_to_q31(sum >> 31);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while (col > 0U);
+
+#endif
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c
new file mode 100644
index 0000000..3e4f5f7
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_scale_f32.c
+ * Description:  Multiplies a floating-point matrix by a scalar
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixScale Matrix Scale
+ *
+ * Multiplies a matrix by a scalar.  This is accomplished by multiplying each element in the
+ * matrix by the scalar.  For example:
+ * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"
+ *
+ * The function checks to make sure that the input and output matrices are of the same size.
+ *
+ * In the fixed-point Q15 and Q31 functions, scale is represented by
+ * a fractional multiplication scaleFract and an arithmetic shift shift.
+ * The shift allows the gain of the scaling operation to exceed 1.0.
+ * The overall scale factor applied to the fixed-point data is
+ * 
+ *     scale = scaleFract * 2^shift.
+ * 

+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in]       *pSrc points to input matrix structure
+ * @param[in]       scale scale factor to be applied
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ */
+
+arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#if defined (ARM_MATH_DSP)
+
+  float32_t in1, in2, in3, in4;                  /* temporary variables */
+  float32_t out1, out2, out3, out4;              /* temporary variables */
+
+#endif //      #if defined (ARM_MATH_DSP)
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#if defined (ARM_MATH_DSP)
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* Scaling and results are stored in the destination buffer. */
+      in1 = pIn[0];
+      in2 = pIn[1];
+      in3 = pIn[2];
+      in4 = pIn[3];
+
+      out1 = in1 * scale;
+      out2 = in2 * scale;
+      out3 = in3 * scale;
+      out4 = in4 * scale;
+
+
+      pOut[0] = out1;
+      pOut[1] = out2;
+      pOut[2] = out3;
+      pOut[3] = out4;
+
+      /* update pointers to process next sampels */
+      pIn += 4U;
+      pOut += 4U;
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4U;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* The results are stored in the destination buffer. */
+      *pOut++ = (*pIn++) * scale;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c
new file mode 100644
index 0000000..4eff925
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c
@@ -0,0 +1,171 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_scale_q15.c
+ * Description:  Multiplies a Q15 matrix by a scalar
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in]       *pSrc points to input matrix
+ * @param[in]       scaleFract fractional portion of the scale factor
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The input data *pSrc and scaleFract are in 1.15 format.
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
+ */
+
+arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = 15 - shift;                 /* total shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#if defined (ARM_MATH_DSP)
+
+  q15_t in1, in2, in3, in4;
+  q31_t out1, out2, out3, out4;
+  q31_t inA1, inA2;
+
+#endif //     #if defined (ARM_MATH_DSP)
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch */
+  if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif //    #ifdef ARM_MATH_MATRIX_CHECK
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#if defined (ARM_MATH_DSP)
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      /* Reading 2 inputs from memory */
+      inA1 = _SIMD32_OFFSET(pIn);
+      inA2 = _SIMD32_OFFSET(pIn + 2);
+
+      /* C = A * scale */
+      /* Scale the inputs and then store the 2 results in the destination buffer
+       * in single cycle by packing the outputs */
+      out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+      out2 = (q31_t) ((q15_t) inA1 * scaleFract);
+      out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+      out4 = (q31_t) ((q15_t) inA2 * scaleFract);
+
+      out1 = out1 >> totShift;
+      inA1 = _SIMD32_OFFSET(pIn + 4);
+      out2 = out2 >> totShift;
+      inA2 = _SIMD32_OFFSET(pIn + 6);
+      out3 = out3 >> totShift;
+      out4 = out4 >> totShift;
+
+      in1 = (q15_t) (__SSAT(out1, 16));
+      in2 = (q15_t) (__SSAT(out2, 16));
+      in3 = (q15_t) (__SSAT(out3, 16));
+      in4 = (q15_t) (__SSAT(out4, 16));
+
+      _SIMD32_OFFSET(pOut) = __PKHBT(in2, in1, 16);
+      _SIMD32_OFFSET(pOut + 2) = __PKHBT(in4, in3, 16);
+
+      /* update pointers to process next sampels */
+      pIn += 4U;
+      pOut += 4U;
+
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4U;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c
new file mode 100644
index 0000000..1b2b373
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c
@@ -0,0 +1,191 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_scale_q31.c
+ * Description:  Multiplies a Q31 matrix by a scalar
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in]       *pSrc points to input matrix
+ * @param[in]       scaleFract fractional portion of the scale factor
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The input data *pSrc and scaleFract are in 1.31 format.
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
+ */
+
+arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = shift + 1;                  /* shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix scaling      */
+  q31_t in1, in2, out1;                          /* temporary variabels */
+
+#if defined (ARM_MATH_DSP)
+
+  q31_t in3, in4, out2, out3, out4;              /* temporary variables */
+
+#endif //      #ifndef ARM_MAT_CM0
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch  */
+  if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif //    #ifdef ARM_MATH_MATRIX_CHECK
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#if defined (ARM_MATH_DSP)
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Read values from input */
+      in1 = *pIn;
+      in2 = *(pIn + 1);
+      in3 = *(pIn + 2);
+      in4 = *(pIn + 3);
+
+      /* multiply input with scaler value */
+      in1 = ((q63_t) in1 * scaleFract) >> 32;
+      in2 = ((q63_t) in2 * scaleFract) >> 32;
+      in3 = ((q63_t) in3 * scaleFract) >> 32;
+      in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+      /* apply shifting */
+      out1 = in1 << totShift;
+      out2 = in2 << totShift;
+
+      /* saturate the results. */
+      if (in1 != (out1 >> totShift))
+        out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+      if (in2 != (out2 >> totShift))
+        out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+      out3 = in3 << totShift;
+      out4 = in4 << totShift;
+
+      *pOut = out1;
+      *(pOut + 1) = out2;
+
+      if (in3 != (out3 >> totShift))
+        out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+      if (in4 != (out4 >> totShift))
+        out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+
+      *(pOut + 2) = out3;
+      *(pOut + 3) = out4;
+
+      /* update pointers to process next sampels */
+      pIn += 4U;
+      pOut += 4U;
+
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4U;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      in1 = *pIn++;
+
+      in2 = ((q63_t) in1 * scaleFract) >> 32;
+
+      out1 = in2 << totShift;
+
+      if (in2 != (out1 >> totShift))
+        out1 = 0x7FFFFFFF ^ (in2 >> 31);
+
+      *pOut++ = out1;
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c
new file mode 100644
index 0000000..42eaadb
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c
@@ -0,0 +1,197 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_sub_f32.c
+ * Description:  Floating-point matrix subtraction
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixSub Matrix Subtraction
+ *
+ * Subtract two matrices.
+ * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"
+ *
+ * The functions check to make sure that
+ * pSrcA, pSrcB, and pDst have the same
+ * number of rows and columns.
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer  */
+
+#if defined (ARM_MATH_DSP)
+
+  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */
+
+#endif //      #if defined (ARM_MATH_DSP)
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#if defined (ARM_MATH_DSP)
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* out = sourceA - sourceB */
+      out1 = inA1 - inB1;
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* out = sourceA - sourceB */
+      out2 = inA2 - inB2;
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* out = sourceA - sourceB */
+      out1 = inA1 - inB1;
+
+
+      /* out = sourceA - sourceB */
+      out2 = inA2 - inB2;
+
+      /* Store result in destination */
+      pOut[2] = out1;
+
+      /* Store result in destination */
+      pOut[3] = out2;
+
+
+      /* update pointers to process next sampels */
+      pIn1 += 4U;
+      pIn2 += 4U;
+      pOut += 4U;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4U;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) - (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c
new file mode 100644
index 0000000..07818dc
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_sub_q15.c
+ * Description:  Q15 Matrix subtraction
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix subtraction.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix subtraction  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if ((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#if defined (ARM_MATH_DSP)
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Apply loop unrolling */
+    blkCnt = numSamples >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4U;
+
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c
new file mode 100644
index 0000000..ebfd09d
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c
@@ -0,0 +1,196 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_sub_q31.c
+ * Description:  Q31 matrix subtraction
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix subtraction.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     		The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+
+arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t inA1, inB1;                              /* temporary variables */
+
+#if defined (ARM_MATH_DSP)
+
+  q31_t inA2, inB2;                              /* temporary variables */
+  q31_t out1, out2;                              /* temporary variables */
+
+#endif //      #if defined (ARM_MATH_DSP)
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition  */
+  if ((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#if defined (ARM_MATH_DSP)
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2U;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* Subtract and saturate */
+      out1 = __QSUB(inA1, inB1);
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* Subtract and saturate */
+      out2 = __QSUB(inA2, inB2);
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* Subtract and saturate */
+      out1 = __QSUB(inA1, inB1);
+
+      /* Subtract and saturate */
+      out2 = __QSUB(inA2, inB2);
+
+      /* Store result in destination */
+      pOut[2] = out1;
+      pOut[3] = out2;
+
+      /* update pointers to process next samples */
+      pIn1 += 4U;
+      pIn2 += 4U;
+      pOut += 4U;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4U;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+    while (blkCnt > 0U)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      inA1 = *pIn1++;
+      inB1 = *pIn2++;
+
+      inA1 = __QSUB(inA1, inB1);
+
+      *pOut++ = inA1;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c
new file mode 100644
index 0000000..aaedb9d
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c
@@ -0,0 +1,206 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_trans_f32.c
+ * Description:  Floating-point matrix transpose
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @defgroup MatrixTrans Matrix Transpose
+ *
+ * Tranposes a matrix.
+ * Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix.
+ * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/**
+  * @brief Floating-point matrix transpose.
+  * @param[in]  *pSrc points to the input matrix
+  * @param[out] *pDst points to the output matrix
+  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+  * or ARM_MATH_SUCCESS based on the outcome of size checking.
+  */
+
+
+arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of rows */
+  uint16_t nColumns = pSrc->numCols;             /* number of columns */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0U, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Loop Unrolling */
+      blkCnt = nColumns >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while (blkCnt > 0U)        /* column loop */
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4U;
+
+      while (blkCnt > 0U)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0U, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while (col > 0U)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);          /* row loop end  */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c
new file mode 100644
index 0000000..817210c
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c
@@ -0,0 +1,272 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_trans_q15.c
+ * Description:  Q15 matrix transpose
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/*
+ * @brief Q15 matrix transpose.
+ * @param[in]  *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pSrcA = pSrc->pData;                    /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns */
+  uint16_t col, row = nRows, i = 0U;             /* row and column loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q31_t in;                                      /* variable to hold temporary output  */
+
+#else
+
+  q15_t in;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = nColumns >> 2U;
+
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while (col > 0U)
+      {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pSrcA)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read two elements from the row */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        in = *__SIMD32(pSrcA)++;
+
+#else
+
+        in = *__SIMD32(pSrcA)++;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+#else
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      col = nColumns % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+      while (col > 0U)
+      {
+        /* Read and store the input element in the destination */
+        *pOut = *pSrcA++;
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while (row > 0U);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c
new file mode 100644
index 0000000..9f94938
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c
@@ -0,0 +1,198 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mat_trans_q31.c
+ * Description:  Q31 matrix transpose
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/*
+  * @brief Q31 matrix transpose.
+  * @param[in]  *pSrc points to the input matrix
+  * @param[out] *pDst points to the output matrix
+  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+  * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer  */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer  */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns  */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0U, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      blkCnt = nColumns >> 2U;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while (blkCnt > 0U)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4U;
+
+      while (blkCnt > 0U)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0U, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while (col > 0U)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    }
+    while (row > 0U);            /* row loop end */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c
new file mode 100644
index 0000000..3a77a9f
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c
@@ -0,0 +1,170 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_max_f32.c
+ * Description:  Maximum value of a floating-point vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup Max Maximum
+ *
+ * Computes the maximum value of an array of data.
+ * The function returns both the maximum value and its position within the array.
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t maxVal1, maxVal2, out;               /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0U;
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1U) >> 2U;
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1U;
+    }
+
+    /* compare for the maximum value */
+    if (out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2U;
+    }
+
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3U;
+    }
+
+    /* compare for the maximum value */
+    if (out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4U;
+    }
+
+    count += 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1U) is not multiple of 4 */
+  blkCnt = (blockSize - 1U) % 4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  float32_t maxVal1, out;                        /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the maximum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c
new file mode 100644
index 0000000..c2fead2
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_max_q15.c
+ * Description:  Maximum value of a Q15 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0U;
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1U) >> 2U;
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1U;
+    }
+
+    /* compare for the maximum value */
+    if (out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2U;
+    }
+
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3U;
+    }
+
+    /* compare for the maximum value */
+    if (out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4U;
+    }
+
+    count += 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1U) is not multiple of 4 */
+  blkCnt = (blockSize - 1U) % 4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  q15_t maxVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the maximum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c
new file mode 100644
index 0000000..5e90693
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_max_q31.c
+ * Description:  Maximum value of a Q31 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0U;
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1U) >> 2U;
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1U;
+    }
+
+    /* compare for the maximum value */
+    if (out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2U;
+    }
+
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3U;
+    }
+
+    /* compare for the maximum value */
+    if (out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4U;
+    }
+
+    count += 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1U) is not multiple of 4 */
+  blkCnt = (blockSize - 1U) % 4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  q31_t maxVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the maximum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c
new file mode 100644
index 0000000..6cd6f60
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_max_q7.c
+ * Description:  Maximum value of a Q7 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t maxVal1, maxVal2, out;                    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0U;
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1U) >> 2U;
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1U;
+    }
+
+    /* compare for the maximum value */
+    if (out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2U;
+    }
+
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3U;
+    }
+
+    /* compare for the maximum value */
+    if (out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4U;
+    }
+
+    count += 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1U) is not multiple of 4 */
+  blkCnt = (blockSize - 1U) % 4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  q7_t maxVal1, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if (out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the maximum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c
new file mode 100644
index 0000000..8a59188
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mean_f32.c
+ * Description:  Mean value of a floating-point vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup mean Mean
+ *
+ * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.
+ * The underlying algorithm is used:
+ *
+ * 
+ * 	Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;
+ * 

+ *
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+
+/**
+ * @brief Mean value of a floating-point vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult mean value returned here
+ * @return none.
+ */
+
+void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    sum += in1;
+    sum += in2;
+    sum += in3;
+    sum += in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = sum / (float32_t) blockSize;
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c
new file mode 100644
index 0000000..9ef0914
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mean_q15.c
+ * Description:  Mean value of a Q15 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+
+/**
+ * @brief Mean value of a Q15 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.15 format and is accumulated in a 32-bit
+ * accumulator in 17.15 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.
+ *
+ */
+
+void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16U) >> 16U);
+    sum +=  (in >> 16U);
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16U) >> 16U);
+    sum +=  (in >> 16U);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q15_t) (sum / (q31_t)blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c
new file mode 100644
index 0000000..def314a
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mean_q31.c
+ * Description:  Mean value of a Q31 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+
+/**
+ * @brief Mean value of a Q31 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *\par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.31 format and is accumulated in a 64-bit
+ * accumulator in 33.31 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is truncated to yield a result of 1.31 format.
+ *
+ */
+
+void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    sum += in1;
+    sum += in2;
+    sum += in3;
+    sum += in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q31_t) (sum / (int32_t) blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c
new file mode 100644
index 0000000..ae60869
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_mean_q7.c
+ * Description:  Mean value of a Q7 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+
+/**
+ * @brief Mean value of a Q7 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.7 format and is accumulated in a 32-bit
+ * accumulator in 25.7 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is truncated to yield a result of 1.7 format.
+ *
+ */
+
+void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in = *__SIMD32(pSrc)++;
+
+    sum += ((in << 24U) >> 24U);
+    sum += ((in << 16U) >> 24U);
+    sum += ((in <<  8U) >> 24U);
+    sum +=  (in >> 24U);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q7_t) (sum / (int32_t) blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c
new file mode 100644
index 0000000..6ef11f9
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c
@@ -0,0 +1,170 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_min_f32.c
+ * Description:  Minimum value of a floating-point vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup Min Minimum
+ *
+ * Computes the minimum value of an array of data.
+ * The function returns both the minimum value and its position within the array.
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult minimum value returned here
+ * @param[out]      *pIndex index of minimum value returned here
+ * @return none.
+ */
+
+void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t minVal1, minVal2, out;               /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0U;
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1U) >> 2U;
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1U;
+    }
+
+    /* compare for the minimum value */
+    if (out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2U;
+    }
+
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3U;
+    }
+
+    /* compare for the minimum value */
+    if (out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4U;
+    }
+
+    count += 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1U) is not multiple of 4 */
+  blkCnt = (blockSize - 1U) % 4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  float32_t minVal1, out;                        /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the minimum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c
new file mode 100644
index 0000000..aa7e424
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c
@@ -0,0 +1,163 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_min_q15.c
+ * Description:  Minimum value of a Q15 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult minimum value returned here
+ * @param[out]      *pIndex index of minimum value returned here
+ * @return none.
+ */
+
+void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0U;
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1U) >> 2U;
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1U;
+    }
+
+    /* compare for the minimum value */
+    if (out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2U;
+    }
+
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3U;
+    }
+
+    /* compare for the minimum value */
+    if (out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4U;
+    }
+
+    count += 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1U) is not multiple of 4 */
+  blkCnt = (blockSize - 1U) % 4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  q15_t minVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the minimum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c
new file mode 100644
index 0000000..57dd195
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c
@@ -0,0 +1,163 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_min_q31.c
+ * Description:  Minimum value of a Q31 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult minimum value returned here
+ * @param[out]      *pIndex index of minimum value returned here
+ * @return none.
+ */
+
+void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0U;
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1U) >> 2U;
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1U;
+    }
+
+    /* compare for the minimum value */
+    if (out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2U;
+    }
+
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3U;
+    }
+
+    /* compare for the minimum value */
+    if (out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4U;
+    }
+
+    count += 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1U) is not multiple of 4 */
+  blkCnt = (blockSize - 1U) % 4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  q31_t minVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the minimum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c
new file mode 100644
index 0000000..ac96603
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c
@@ -0,0 +1,163 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_min_q7.c
+ * Description:  Minimum value of a Q7 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult minimum value returned here
+ * @param[out]      *pIndex index of minimum value returned here
+ * @return none.
+ */
+
+void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t minVal1, minVal2, out;                    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0U;
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1U) >> 2U;
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1U;
+    }
+
+    /* compare for the minimum value */
+    if (out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2U;
+    }
+
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3U;
+    }
+
+    /* compare for the minimum value */
+    if (out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4U;
+    }
+
+    count += 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1U) is not multiple of 4 */
+  blkCnt = (blockSize - 1U) % 4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  q7_t minVal1, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0U;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if (out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the minimum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c
new file mode 100644
index 0000000..bfe4dd3
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_power_f32.c
+ * Description:  Sum of the squares of the elements of a floating-point vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup power Power
+ *
+ * Calculates the sum of the squares of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ * 
+ * 	Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];
+ * 

+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+
+/**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult sum of the squares value returned here
+ * @return none.
+ *
+ */
+
+
+void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* accumulator */
+  float32_t in;                                  /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* compute power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result to the destination */
+  *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c
new file mode 100644
index 0000000..fbe73d1
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c
@@ -0,0 +1,138 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_power_q15.c
+ * Description:  Sum of the squares of the elements of a Q15 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 34.30 format.
+ *
+ */
+
+void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in32;                                    /* Temporary variable to store input value */
+  q15_t in16;                                    /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in16 = *pSrc++;
+    sum = __SMLALD(in16, in16, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  /* Store the results in 34.30 format  */
+  *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c
new file mode 100644
index 0000000..498face
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_power_q31.c
+ * Description:  Sum of the squares of the elements of a Q31 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.31 format.
+ * Intermediate multiplication yields a 2.62 format, and this
+ * result is truncated to 2.48 format by discarding the lower 14 bits.
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
+ * With 15 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 16.48 format.
+ *
+ */
+
+void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  q31_t in;
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14U;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14U;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14U;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the results in 16.48 format  */
+  *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c
new file mode 100644
index 0000000..3b8335a
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_power_q7.c
+ * Description:  Sum of the squares of the elements of a Q7 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.7 format.
+ * Intermediate multiplication yields a 2.14 format, and this
+ * result is added without saturation to an accumulator in 18.14 format.
+ * With 17 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 18.14 format.
+ *
+ */
+
+void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  q7_t in;                                       /* Temporary variable to store input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t input1;                                  /* Temporary variable to store packed input */
+  q31_t in1, in2;                                /* Temporary variables to store input */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* Reading two inputs of pSrc vector and packing */
+    input1 = *__SIMD32(pSrc)++;
+
+    in1 = __SXTB16(__ROR(input1, 8));
+    in2 = __SXTB16(input1);
+
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* calculate power and accumulate to accumulator */
+    sum = __SMLAD(in1, in1, sum);
+    sum = __SMLAD(in2, in2, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q15_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result in 18.14 format  */
+  *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c
new file mode 100644
index 0000000..3089d40
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_rms_f32.c
+ * Description:  Root mean square value of an array of F32 type
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup RMS Root mean square (RMS)
+ *
+ *
+ * Calculates the Root Mean Sqaure of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ * 
+ * 	Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+ * 

+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+
+/**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult rms value returned here
+ * @return none.
+ *
+ */
+
+void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Accumulator */
+  float32_t in;                                  /* Tempoprary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Rms and store the result in the destination */
+  arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c
new file mode 100644
index 0000000..7cc2e12
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c
@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_rms_q15.c
+ * Description:  Root Mean Square of the elements of a Q15 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+/**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult rms value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ *
+ */
+
+void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* temporary variable to store the input value */
+  q15_t in1;                                     /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  /* Store the result in the destination */
+  arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult);
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  /* Store the result in the destination */
+  arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c
new file mode 100644
index 0000000..7cb9149
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_rms_q31.c
+ * Description:  Root Mean Square of the elements of a Q31 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult rms value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, and intermediate multiplication
+ * yields a 2.62 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows, it wraps around and distorts the result.
+ * In order to avoid overflows completely, the input signal must be scaled down by
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
+ *
+ */
+
+void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+  q31_t in;                                      /* Temporary variable to store the input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2, in3, in4;                      /* Temporary input variables */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.
+   ** a second loop below computes the remaining 1 to 7 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum */
+    /* read two samples from source buffer */
+    in1 = pSrc[0];
+    in2 = pSrc[1];
+
+    /* calculate power and accumulate to accumulator */
+    sum += (q63_t) in1 *in1;
+    sum += (q63_t) in2 *in2;
+
+    /* read two samples from source buffer */
+    in3 = pSrc[2];
+    in4 = pSrc[3];
+
+    /* calculate power and accumulate to accumulator */
+    sum += (q63_t) in3 *in3;
+    sum += (q63_t) in4 *in4;
+
+
+    /* update source buffer to process next samples */
+    pSrc += 4U;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
+  /* Compute Rms and store the result in the destination vector */
+  arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult);
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c
new file mode 100644
index 0000000..e082fc6
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c
@@ -0,0 +1,186 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_std_f32.c
+ * Description:  Standard deviation of the elements of a floating-point vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup STD Standard deviation
+ *
+ * Calculates the standard deviation of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ * 
+ *   Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
+ *
+ *     where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+ *
+ *                     sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+ * 

+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+
+/**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult standard deviation value returned here
+ * @return none.
+ */
+
+void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
+  float32_t in;                                  /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+#if defined (ARM_MATH_DSP)
+  float32_t meanOfSquares, mean, squareOfMean;   /* Temporary variables */
+#else
+  float32_t squareOfSum;                         /* Square of Sum */
+  float32_t var;                                 /* Temporary varaince storage */
+#endif
+
+  if (blockSize == 1U)
+  {
+    *pResult = 0;
+    return;
+  }
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+  /* Compute mean of all input values */
+  mean = sum / (float32_t) blockSize;
+
+  /* Compute square of mean */
+  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+                                  ((float32_t) blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += in * in;
+
+    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+    /* Compute Sum of the input samples
+     * and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute the square of sum */
+  squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+  /* Compute the variance */
+  var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32(var, pResult);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c
new file mode 100644
index 0000000..e3626d8
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c
@@ -0,0 +1,174 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_std_q15.c
+ * Description:  Standard deviation of an array of Q15 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+/**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult standard deviation value returned here
+ * @return none.
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ */
+
+void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q31_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  uint32_t blkCnt;                               /* loop counter */
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+#if defined (ARM_MATH_DSP)
+  q31_t in;                                      /* input value */
+  q15_t in1;                                     /* input value */
+#else
+  q15_t in;                                      /* input value */
+#endif
+
+  if (blockSize == 1U)
+  {
+    *pResult = 0;
+    return;
+  }
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16U) >> 16U);
+    sum +=  (in >> 16U);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16U) >> 16U);
+    sum +=  (in >> 16U);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+    sum += in1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1U));
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1U)));
+
+  /* mean of the squares minus the square of the mean. */
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15U, 16U), pResult);
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1U));
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1U)));
+
+  /* mean of the squares minus the square of the mean. */
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15U, 16U), pResult);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c
new file mode 100644
index 0000000..806a90e
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_std_q31.c
+ * Description:  Standard deviation of an array of Q31 type.
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+/**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult standard deviation value returned here
+ * @return none.
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, which is then downshifted by 8 bits
+ * which yields 1.23, and intermediate multiplication yields a 2.46 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a 16 guard bits.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.
+ * After division, internal variables should be Q18.46
+ * Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value.
+ *
+ */
+
+void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q63_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q31_t in;                                      /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+
+  if (blockSize == 1U)
+  {
+    *pResult = 0;
+    return;
+  }
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++ >> 8U;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8U;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8U;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8U;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++ >> 8U;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1U);
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++ >> 8U;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  /* Compute square of mean */
+  squareOfMean = sum * sum / (q63_t)(blockSize * (blockSize - 1U));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_q31((meanOfSquares - squareOfMean) >> 15U, pResult);
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c
new file mode 100644
index 0000000..a366f5c
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c
@@ -0,0 +1,181 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_var_f32.c
+ * Description:  Variance of the elements of a floating-point vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup variance  Variance
+ *
+ * Calculates the variance of the elements in the input vector.
+ * The underlying algorithm used is the direct method sometimes referred to as the two-pass method:
+ *
+ * 
+ *   Result = sum(element - meanOfElements)^2) / numElement - 1
+ *
+ *     where, meanOfElements = ( pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] ) / blockSize
+ *
+ * 

+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+
+/**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult variance value returned here
+ * @return none.
+ */
+
+void arm_var_f32(
+                 float32_t * pSrc,
+                 uint32_t blockSize,
+                 float32_t * pResult)
+{
+    float32_t fMean, fValue;
+    uint32_t blkCnt;            /* loop counter */
+    float32_t * pInput = pSrc;
+    float32_t sum = 0.0f;
+    float32_t fSum = 0.0f;
+    #if defined(ARM_MATH_DSP)
+    float32_t in1, in2, in3, in4;
+    #endif
+
+    if (blockSize <= 1U)
+    {
+        *pResult = 0;
+        return;
+    }
+
+    #if defined(ARM_MATH_DSP)
+        /* Run the below code for Cortex-M4 and Cortex-M7 */
+
+        /*loop Unrolling */
+        blkCnt = blockSize >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+        ** a second loop below computes the remaining 1 to 3 samples. */
+        while (blkCnt > 0U)
+        {
+            /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+            in1 = *pInput++;
+            in2 = *pInput++;
+            in3 = *pInput++;
+            in4 = *pInput++;
+
+            sum += in1;
+            sum += in2;
+            sum += in3;
+            sum += in4;
+
+            /* Decrement the loop counter */
+            blkCnt--;
+        }
+
+        /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+        ** No loop unrolling is used. */
+        blkCnt = blockSize % 0x4U;
+
+    #else
+        /* Run the below code for Cortex-M0 or Cortex-M3 */
+
+        /* Loop over blockSize number of values */
+        blkCnt = blockSize;
+
+    #endif
+
+    while (blkCnt > 0U)
+    {
+        /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+        sum += *pInput++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+    }
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+    fMean = sum / (float32_t) blockSize;
+
+    pInput = pSrc;
+
+    #if defined(ARM_MATH_DSP)
+
+        /*loop Unrolling */
+        blkCnt = blockSize >> 2U;
+
+        /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+        ** a second loop below computes the remaining 1 to 3 samples. */
+        while (blkCnt > 0U)
+        {
+            fValue = *pInput++ - fMean;
+            fSum += fValue * fValue;
+            fValue = *pInput++ - fMean;
+            fSum += fValue * fValue;
+            fValue = *pInput++ - fMean;
+            fSum += fValue * fValue;
+            fValue = *pInput++ - fMean;
+            fSum += fValue * fValue;
+
+            /* Decrement the loop counter */
+            blkCnt--;
+        }
+
+        blkCnt = blockSize % 0x4U;
+    #else
+        /* Run the below code for Cortex-M0 or Cortex-M3 */
+
+        /* Loop over blockSize number of values */
+        blkCnt = blockSize;
+    #endif
+
+    while (blkCnt > 0U)
+    {
+        fValue = *pInput++ - fMean;
+        fSum += fValue * fValue;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+    }
+
+    /* Variance */
+    *pResult = fSum / (float32_t)(blockSize - 1.0f);
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c
new file mode 100644
index 0000000..ff9972a
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c
@@ -0,0 +1,172 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_var_q15.c
+ * Description:  Variance of an array of Q15 type
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+/**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult variance value returned here
+ * @return none.
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ */
+
+void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q31_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  uint32_t blkCnt;                               /* loop counter */
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+#if defined (ARM_MATH_DSP)
+  q31_t in;                                      /* input value */
+  q15_t in1;                                     /* input value */
+#else
+  q15_t in;                                      /* input value */
+#endif
+
+  if (blockSize == 1U)
+  {
+    *pResult = 0;
+    return;
+  }
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16U) >> 16U);
+    sum +=  (in >> 16U);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16U) >> 16U);
+    sum +=  (in >> 16U);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+    sum += in1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1U));
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1U)));
+
+  /* mean of the squares minus the square of the mean. */
+  *pResult = (meanOfSquares - squareOfMean) >> 15U;
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1U));
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1U)));
+
+  /* mean of the squares minus the square of the mean. */
+  *pResult = (meanOfSquares - squareOfMean) >> 15;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c
new file mode 100644
index 0000000..08e80fe
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_var_q31.c
+ * Description:  Variance of an array of Q31 type
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+/**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult variance value returned here
+ * @return none.
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, which is then downshifted by 8 bits
+ * which yields 1.23, and intermediate multiplication yields a 2.46 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a 16 guard bits.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.
+ * After division, internal variables should be Q18.46
+ * Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value.
+ *
+ */
+
+void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q63_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q31_t in;                                      /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+
+  if (blockSize == 1U)
+  {
+    *pResult = 0;
+    return;
+  }
+
+#if defined (ARM_MATH_DSP)
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++ >> 8U;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8U;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8U;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++ >> 8U;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++ >> 8U;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1U);
+
+#else
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++ >> 8U;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  /* Compute square of mean */
+  squareOfMean = sum * sum / (q63_t)(blockSize * (blockSize - 1U));
+
+  /* Compute standard deviation and then store the result to the destination */
+  *pResult = (meanOfSquares - squareOfMean) >> 15U;
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c
new file mode 100644
index 0000000..13245b6
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_copy_f32.c
+ * Description:  Copies the elements of a floating-point vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup copy Vector Copy
+ *
+ * Copies sample by sample from source vector to destination vector.
+ *
+ * 
+ * 	pDst[n] = pSrc[n];   0 <= n < blockSize.
+ * 

+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in]       *pSrc points to input vector
+ * @param[out]      *pDst points to output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+
+void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c
new file mode 100644
index 0000000..28b60d9
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c
@@ -0,0 +1,102 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_copy_q15.c
+ * Description:  Copies the elements of a Q15 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+/**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in]       *pSrc points to input vector
+ * @param[out]      *pDst points to output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = A */
+    /* Read two inputs */
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c
new file mode 100644
index 0000000..b0bdd05
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_copy_q31.c
+ * Description:  Copies the elements of a Q31 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in]       *pSrc points to input vector
+ * @param[out]      *pDst points to output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = A */
+    /* Copy and then store the values in the destination buffer */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c
new file mode 100644
index 0000000..a3afa36
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c
@@ -0,0 +1,103 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_copy_q7.c
+ * Description:  Copies the elements of a Q7 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in]       *pSrc points to input vector
+ * @param[out]      *pDst points to output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    /* 4 samples are copied and stored at a time using SIMD */
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+  while (blkCnt > 0U)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c
new file mode 100644
index 0000000..5a70608
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fill_f32.c
+ * Description:  Fills a constant value into a floating-point vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup Fill Vector Fill
+ *
+ * Fills the destination vector with a constant value.
+ *
+ * 
+ * 	pDst[n] = value;   0 <= n < blockSize.
+ * 

+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in]       value input value to be filled
+ * @param[out]      *pDst points to output vector
+ * @param[in]       blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+
+void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1 = value;
+  float32_t in2 = value;
+  float32_t in3 = value;
+  float32_t in4 = value;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+  while (blkCnt > 0U)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c
new file mode 100644
index 0000000..8f27def
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c
@@ -0,0 +1,108 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fill_q15.c
+ * Description:  Fills a constant value into a Q15 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in]       value input value to be filled
+ * @param[out]      *pDst points to output vector
+ * @param[in]       blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* Packing two 16 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PKHBT(value, value, 16U);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c
new file mode 100644
index 0000000..3769f4d
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fill_q31.c
+ * Description:  Fills a constant value into a Q31 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in]       value input value to be filled
+ * @param[out]      *pDst points to output vector
+ * @param[in]       blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1 = value;
+  q31_t in2 = value;
+  q31_t in3 = value;
+  q31_t in4 = value;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c
new file mode 100644
index 0000000..fa718b7
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c
@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_fill_q7.c
+ * Description:  Fills a constant value into a Q7 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in]       value input value to be filled
+ * @param[out]      *pDst points to output vector
+ * @param[in]       blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* Packing four 8 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PACKq7(value, value, value, value);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c
new file mode 100644
index 0000000..b652e7c
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_float_to_q15.c
+ * Description:  Converts the elements of the floating-point vector to Q15 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in]       *pSrc points to the floating-point input vector
+ * @param[out]      *pDst points to the Q15 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ * \par
+ * The equation used for the conversion process is:
+ * 
+ * 	pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.
+ * 

+ * \par Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ * \note
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ *
+ */
+
+
+void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c
new file mode 100644
index 0000000..7ce1402
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c
@@ -0,0 +1,199 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_float_to_q31.c
+ * Description:  Converts the elements of the floating-point vector to Q31 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup float_to_x  Convert 32-bit floating point value
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in]       *pSrc points to the floating-point input vector
+ * @param[out]      *pDst points to the Q31 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ *\par Description:
+ * \par
+ * The equation used for the conversion process is:
+ *
+ * 
+ * 	pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.
+ * 

+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ *
+ * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ */
+
+
+void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 32768 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c
new file mode 100644
index 0000000..7fd3f2c
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c
@@ -0,0 +1,191 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_float_to_q7.c
+ * Description:  Converts the elements of the floating-point vector to Q7 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in]       *pSrc points to the floating-point input vector
+ * @param[out]      *pDst points to the Q7 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ *\par Description:
+ * \par
+ * The equation used for the conversion process is:
+ * 
+ * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.
+ * 

+ * \par Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ * \note
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ */
+
+
+void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+  while (blkCnt > 0U)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0.0f ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while (blkCnt > 0U)
+  {
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c
new file mode 100644
index 0000000..442ba9f
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_q15_to_float.c
+ * Description:  Converts the elements of the Q15 vector to floating-point vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q15_to_x  Convert 16-bit Integer value
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+
+
+
+/**
+ * @brief  Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in]       *pSrc points to the Q15 input vector
+ * @param[out]      *pDst points to the floating-point output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * 
+ * 	pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.
+ * 

+ *
+ */
+
+
+void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c
new file mode 100644
index 0000000..2dff322
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_q15_to_q31.c
+ * Description:  Converts the elements of the Q15 vector to Q31 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in]       *pSrc points to the Q15 input vector
+ * @param[out]      *pDst points to the Q31 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * 
+ * 	pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.
+ * 

+ *
+ */
+
+
+void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2;
+  q31_t out1, out2, out3, out4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    in1 = *__SIMD32(pIn)++;
+    in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* extract lower 16 bits to 32 bit result */
+    out1 = in1 << 16U;
+    /* extract upper 16 bits to 32 bit result */
+    out2 = in1 & 0xFFFF0000;
+    /* extract lower 16 bits to 32 bit result */
+    out3 = in2 << 16U;
+    /* extract upper 16 bits to 32 bit result */
+    out4 = in2 & 0xFFFF0000;
+
+#else
+
+    /* extract upper 16 bits to 32 bit result */
+    out1 = in1 & 0xFFFF0000;
+    /* extract lower 16 bits to 32 bit result */
+    out2 = in1 << 16U;
+    /* extract upper 16 bits to 32 bit result */
+    out3 = in2 & 0xFFFF0000;
+    /* extract lower 16 bits to 32 bit result */
+    out4 = in2 << 16U;
+
+#endif //      #ifndef ARM_MATH_BIG_ENDIAN
+
+    *pDst++ = out1;
+    *pDst++ = out2;
+    *pDst++ = out3;
+    *pDst++ = out4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 16;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c
new file mode 100644
index 0000000..26a35e7
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_q15_to_q7.c
+ * Description:  Converts the elements of the Q15 vector to Q7 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in]       *pSrc points to the Q15 input vector
+ * @param[out]      *pDst points to the Q7 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * 
+ * 	pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.
+ * 

+ *
+ */
+
+
+void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2;
+  q31_t out1, out2;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    in1 = *__SIMD32(pIn)++;
+    in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __PKHTB(in2, in1, 16);
+    out2 = __PKHBT(in2, in1, 16);
+
+#else
+
+    out1 = __PKHTB(in1, in2, 16);
+    out2 = __PKHBT(in1, in2, 16);
+
+#endif //      #ifndef ARM_MATH_BIG_ENDIAN
+
+    /* rotate packed value by 24 */
+    out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);
+
+    /* anding with 0xff00ff00 to get two 8 bit values */
+    out1 = out1 & 0xFF00FF00;
+    /* anding with 0x00ff00ff to get two 8 bit values */
+    out2 = out2 & 0x00FF00FF;
+
+    /* oring two values(contains two 8 bit values) to get four packed 8 bit values */
+    out1 = out1 | out2;
+
+    /* store 4 samples at a time to destiantion buffer */
+    *__SIMD32(pDst)++ = out1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c
new file mode 100644
index 0000000..b15d90e
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_q31_to_float.c
+ * Description:  Converts the elements of the Q31 vector to floating-point vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q31_to_x  Convert 32-bit Integer value
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in]       *pSrc points to the Q31 input vector
+ * @param[out]      *pDst points to the floating-point output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * 
+ * 	pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.
+ * 

+ *
+ */
+
+
+void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c
new file mode 100644
index 0000000..2fd305b
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_q31_to_q15.c
+ * Description:  Converts the elements of the Q31 vector to Q15 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in]       *pSrc points to the Q31 input vector
+ * @param[out]      *pDst points to the Q15 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * 
+ * 	pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.
+ * 

+ *
+ */
+
+
+void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+  q31_t out1, out2;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    in1 = *pIn++;
+    in2 = *pIn++;
+    in3 = *pIn++;
+    in4 = *pIn++;
+
+    /* pack two higher 16-bit values from two 32-bit values */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __PKHTB(in2, in1, 16);
+    out2 = __PKHTB(in4, in3, 16);
+
+#else
+
+    out1 = __PKHTB(in1, in2, 16);
+    out2 = __PKHTB(in3, in4, 16);
+
+#endif //      #ifdef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = out1;
+    *__SIMD32(pDst)++ = out2;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c
new file mode 100644
index 0000000..6586861
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_q31_to_q7.c
+ * Description:  Converts the elements of the Q31 vector to Q7 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in]       *pSrc points to the Q31 input vector
+ * @param[out]      *pDst points to the Q7 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * 
+ * 	pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.
+ * 

+ *
+ */
+
+
+void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+  q7_t out1, out2, out3, out4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    in1 = *pIn++;
+    in2 = *pIn++;
+    in3 = *pIn++;
+    in4 = *pIn++;
+
+    out1 = (q7_t) (in1 >> 24);
+    out2 = (q7_t) (in2 >> 24);
+    out3 = (q7_t) (in3 >> 24);
+    out4 = (q7_t) (in4 >> 24);
+
+    *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c
new file mode 100644
index 0000000..d866501
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_q7_to_float.c
+ * Description:  Converts the elements of the Q7 vector to floating-point vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q7_to_x  Convert 8-bit Integer value
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in]       *pSrc points to the Q7 input vector
+ * @param[out]      *pDst points to the floating-point output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * 
+ * 	pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.
+ * 

+ *
+ */
+
+
+void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c
new file mode 100644
index 0000000..5bc5a56
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_q7_to_q15.c
+ * Description:  Converts the elements of the Q7 vector to Q15 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+
+
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in]       *pSrc points to the Q7 input vector
+ * @param[out]      *pDst points to the Q15 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * 
+ * 	pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.
+ * 

+ *
+ */
+
+
+void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+  q31_t in;
+  q31_t in1, in2;
+  q31_t out1, out2;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    in = *__SIMD32(pIn)++;
+
+    /* rotatate in by 8 and extend two q7_t values to q15_t values */
+    in1 = __SXTB16(__ROR(in, 8));
+
+    /* extend remainig two q7_t values to q15_t values */
+    in2 = __SXTB16(in);
+
+    in1 = in1 << 8U;
+    in2 = in2 << 8U;
+
+    in1 = in1 & 0xFF00FF00;
+    in2 = in2 & 0xFF00FF00;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out2 = __PKHTB(in1, in2, 16);
+    out1 = __PKHBT(in2, in1, 16);
+
+#else
+
+    out1 = __PKHTB(in1, in2, 16);
+    out2 = __PKHBT(in2, in1, 16);
+
+#endif
+
+    *__SIMD32(pDst)++ = out1;
+    *__SIMD32(pDst)++ = out2;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) * pIn++ << 8;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c
new file mode 100644
index 0000000..abbda7f
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_q7_to_q31.c
+ * Description:  Converts the elements of the Q7 vector to Q31 vector
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in]       *pSrc points to the Q7 input vector
+ * @param[out]      *pDst points to the Q31 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * 
+ * 	pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.
+ * 

+ *
+ */
+
+
+void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#if defined (ARM_MATH_DSP)
+
+  q31_t in;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    in = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+    *pDst++ = (in & 0xFF000000);
+
+#else
+
+    *pDst++ = (in & 0xFF000000);
+    *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+
+#endif //              #ifndef ARM_MATH_BIG_ENDIAN
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+  while (blkCnt > 0U)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 24;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c
new file mode 100644
index 0000000..3119769
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c
@@ -0,0 +1,230 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_bitreversal.c
+ * Description:  Bitreversal functions
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/*
+* @brief  In-place bit reversal function.
+* @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.
+* @param[in]      fftSize      length of the FFT.
+* @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+* @param[in]      *pBitRevTab  points to the bit reversal table.
+* @return none.
+*/
+
+void arm_bitreversal_f32(
+float32_t * pSrc,
+uint16_t fftSize,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab)
+{
+   uint16_t fftLenBy2, fftLenBy2p1;
+   uint16_t i, j;
+   float32_t in;
+
+   /*  Initializations */
+   j = 0U;
+   fftLenBy2 = fftSize >> 1U;
+   fftLenBy2p1 = (fftSize >> 1U) + 1U;
+
+   /* Bit Reversal Implementation */
+   for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U)
+   {
+      if (i < j)
+      {
+         /*  pSrc[i] <-> pSrc[j]; */
+         in = pSrc[2U * i];
+         pSrc[2U * i] = pSrc[2U * j];
+         pSrc[2U * j] = in;
+
+         /*  pSrc[i+1U] <-> pSrc[j+1U] */
+         in = pSrc[(2U * i) + 1U];
+         pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U];
+         pSrc[(2U * j) + 1U] = in;
+
+         /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+         in = pSrc[2U * (i + fftLenBy2p1)];
+         pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)];
+         pSrc[2U * (j + fftLenBy2p1)] = in;
+
+         /*  pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */
+         in = pSrc[(2U * (i + fftLenBy2p1)) + 1U];
+         pSrc[(2U * (i + fftLenBy2p1)) + 1U] =
+         pSrc[(2U * (j + fftLenBy2p1)) + 1U];
+         pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in;
+
+      }
+
+      /*  pSrc[i+1U] <-> pSrc[j+1U] */
+      in = pSrc[2U * (i + 1U)];
+      pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)];
+      pSrc[2U * (j + fftLenBy2)] = in;
+
+      /*  pSrc[i+2U] <-> pSrc[j+2U] */
+      in = pSrc[(2U * (i + 1U)) + 1U];
+      pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U];
+      pSrc[(2U * (j + fftLenBy2)) + 1U] = in;
+
+      /*  Reading the index for the bit reversal */
+      j = *pBitRevTab;
+
+      /*  Updating the bit reversal index depending on the fft length  */
+      pBitRevTab += bitRevFactor;
+   }
+}
+
+
+
+/*
+* @brief  In-place bit reversal function.
+* @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.
+* @param[in]      fftLen       length of the FFT.
+* @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+* @param[in]      *pBitRevTab  points to bit reversal table.
+* @return none.
+*/
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTable)
+{
+   uint32_t fftLenBy2, fftLenBy2p1, i, j;
+   q31_t in;
+
+   /*  Initializations      */
+   j = 0U;
+   fftLenBy2 = fftLen / 2U;
+   fftLenBy2p1 = (fftLen / 2U) + 1U;
+
+   /* Bit Reversal Implementation */
+   for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U)
+   {
+      if (i < j)
+      {
+         /*  pSrc[i] <-> pSrc[j]; */
+         in = pSrc[2U * i];
+         pSrc[2U * i] = pSrc[2U * j];
+         pSrc[2U * j] = in;
+
+         /*  pSrc[i+1U] <-> pSrc[j+1U] */
+         in = pSrc[(2U * i) + 1U];
+         pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U];
+         pSrc[(2U * j) + 1U] = in;
+
+         /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+         in = pSrc[2U * (i + fftLenBy2p1)];
+         pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)];
+         pSrc[2U * (j + fftLenBy2p1)] = in;
+
+         /*  pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */
+         in = pSrc[(2U * (i + fftLenBy2p1)) + 1U];
+         pSrc[(2U * (i + fftLenBy2p1)) + 1U] =
+         pSrc[(2U * (j + fftLenBy2p1)) + 1U];
+         pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in;
+
+      }
+
+      /*  pSrc[i+1U] <-> pSrc[j+1U] */
+      in = pSrc[2U * (i + 1U)];
+      pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)];
+      pSrc[2U * (j + fftLenBy2)] = in;
+
+      /*  pSrc[i+2U] <-> pSrc[j+2U] */
+      in = pSrc[(2U * (i + 1U)) + 1U];
+      pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U];
+      pSrc[(2U * (j + fftLenBy2)) + 1U] = in;
+
+      /*  Reading the index for the bit reversal */
+      j = *pBitRevTable;
+
+      /*  Updating the bit reversal index depending on the fft length */
+      pBitRevTable += bitRevFactor;
+   }
+}
+
+
+
+/*
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen       length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+   * @param[in]      *pBitRevTab  points to bit reversal table.
+   * @return none.
+*/
+
+void arm_bitreversal_q15(
+q15_t * pSrc16,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab)
+{
+   q31_t *pSrc = (q31_t *) pSrc16;
+   q31_t in;
+   uint32_t fftLenBy2, fftLenBy2p1;
+   uint32_t i, j;
+
+   /*  Initializations */
+   j = 0U;
+   fftLenBy2 = fftLen / 2U;
+   fftLenBy2p1 = (fftLen / 2U) + 1U;
+
+   /* Bit Reversal Implementation */
+   for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U)
+   {
+      if (i < j)
+      {
+         /*  pSrc[i] <-> pSrc[j]; */
+         /*  pSrc[i+1U] <-> pSrc[j+1U] */
+         in = pSrc[i];
+         pSrc[i] = pSrc[j];
+         pSrc[j] = in;
+
+         /*  pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1];  */
+         /*  pSrc[i + fftLenBy2p1+1U] <-> pSrc[j + fftLenBy2p1+1U] */
+         in = pSrc[i + fftLenBy2p1];
+         pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
+         pSrc[j + fftLenBy2p1] = in;
+      }
+
+      /*  pSrc[i+1U] <-> pSrc[j+fftLenBy2];         */
+      /*  pSrc[i+2] <-> pSrc[j+fftLenBy2+1U]  */
+      in = pSrc[i + 1U];
+      pSrc[i + 1U] = pSrc[j + fftLenBy2];
+      pSrc[j + fftLenBy2] = in;
+
+      /*  Reading the index for the bit reversal */
+      j = *pBitRevTab;
+
+      /*  Updating the bit reversal index depending on the fft length  */
+      pBitRevTab += bitRevFactor;
+   }
+}
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S
new file mode 100644
index 0000000..cde264c
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S
@@ -0,0 +1,216 @@
+;/* ----------------------------------------------------------------------
+; * Project:      CMSIS DSP Library
+; * Title:        arm_bitreversal2.S
+; * Description:  arm_bitreversal_32 function done in assembly for maximum speed.
+; *               Called after doing an fft to reorder the output.
+; *               The function is loop unrolled by 2. arm_bitreversal_16 as well.
+; *
+; * $Date:        27. January 2017
+; * $Revision:    V.1.5.1
+; *
+; * Target Processor: Cortex-M cores
+; * -------------------------------------------------------------------- */
+;/*
+; * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+#if   defined ( __CC_ARM )     /* Keil */
+    #define CODESECT AREA     ||.text||, CODE, READONLY, ALIGN=2
+    #define LABEL
+#elif defined ( __IASMARM__ )  /* IAR */
+    #define CODESECT SECTION `.text`:CODE
+    #define PROC
+    #define LABEL
+    #define ENDP
+    #define EXPORT PUBLIC
+#elif defined ( __CSMC__ )	   /* Cosmic */
+	#define	CODESECT	switch .text
+	#define THUMB
+	#define EXPORT	xdef
+	#define PROC	:
+	#define LABEL	:
+	#define ENDP
+	#define arm_bitreversal_32 _arm_bitreversal_32
+#elif defined ( __TI_ARM__ )   /* TI ARM */
+    #define THUMB    .thumb
+    #define CODESECT .text
+    #define EXPORT   .global
+    #define PROC     : .asmfunc
+    #define LABEL    :
+    #define ENDP     .endasmfunc
+    #define END
+#elif defined ( __GNUC__ )     /* GCC */
+    #define THUMB .thumb
+    #define CODESECT .section .text
+    #define EXPORT .global
+    #define PROC :
+    #define LABEL :
+    #define ENDP
+    #define END
+
+    .syntax unified
+#endif
+
+	CODESECT
+	THUMB
+
+;/*
+;* @brief  In-place bit reversal function.
+;* @param[in, out] *pSrc        points to the in-place buffer of unknown 32-bit data type.
+;* @param[in]      bitRevLen    bit reversal table length
+;* @param[in]      *pBitRevTab  points to bit reversal table.
+;* @return none.
+;*/
+	EXPORT arm_bitreversal_32
+	EXPORT arm_bitreversal_16
+
+#if   defined ( __CC_ARM )     /* Keil */
+#elif defined ( __IASMARM__ )  /* IAR */
+#elif defined ( __CSMC__ )	   /* Cosmic */
+#elif defined ( __TI_ARM__ )   /* TI ARM */
+#elif defined ( __GNUC__ )     /* GCC */
+	.type   arm_bitreversal_16, %function
+	.type   arm_bitreversal_32, %function
+#endif
+
+#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS) || defined(ARM_MATH_ARMV8MBL)
+
+arm_bitreversal_32 PROC
+	ADDS     r3,r1,#1
+	PUSH     {r4-r6}
+	ADDS     r1,r2,#0
+	LSRS     r3,r3,#1
+arm_bitreversal_32_0 LABEL
+	LDRH     r2,[r1,#2]
+	LDRH     r6,[r1,#0]
+	ADD      r2,r0,r2
+	ADD      r6,r0,r6
+	LDR      r5,[r2,#0]
+	LDR      r4,[r6,#0]
+	STR      r5,[r6,#0]
+	STR      r4,[r2,#0]
+	LDR      r5,[r2,#4]
+	LDR      r4,[r6,#4]
+	STR      r5,[r6,#4]
+	STR      r4,[r2,#4]
+	ADDS     r1,r1,#4
+	SUBS     r3,r3,#1
+	BNE      arm_bitreversal_32_0
+	POP      {r4-r6}
+	BX       lr
+	ENDP
+
+arm_bitreversal_16 PROC
+	ADDS     r3,r1,#1
+	PUSH     {r4-r6}
+	ADDS     r1,r2,#0
+	LSRS     r3,r3,#1
+arm_bitreversal_16_0 LABEL
+	LDRH     r2,[r1,#2]
+	LDRH     r6,[r1,#0]
+    LSRS     r2,r2,#1
+    LSRS     r6,r6,#1
+	ADD      r2,r0,r2
+	ADD      r6,r0,r6
+	LDR      r5,[r2,#0]
+	LDR      r4,[r6,#0]
+	STR      r5,[r6,#0]
+	STR      r4,[r2,#0]
+	ADDS     r1,r1,#4
+	SUBS     r3,r3,#1
+	BNE      arm_bitreversal_16_0
+	POP      {r4-r6}
+	BX       lr
+	ENDP
+
+#else
+
+arm_bitreversal_32 PROC
+	ADDS     r3,r1,#1
+	CMP      r3,#1
+	IT       LS
+	BXLS     lr
+	PUSH     {r4-r9}
+	ADDS     r1,r2,#2
+	LSRS     r3,r3,#2
+arm_bitreversal_32_0 LABEL       ;/* loop unrolled by 2 */
+	LDRH     r8,[r1,#4]
+	LDRH     r9,[r1,#2]
+	LDRH     r2,[r1,#0]
+	LDRH     r12,[r1,#-2]
+	ADD      r8,r0,r8
+	ADD      r9,r0,r9
+	ADD      r2,r0,r2
+	ADD      r12,r0,r12
+	LDR      r7,[r9,#0]
+	LDR      r6,[r8,#0]
+	LDR      r5,[r2,#0]
+	LDR      r4,[r12,#0]
+	STR      r6,[r9,#0]
+	STR      r7,[r8,#0]
+	STR      r5,[r12,#0]
+	STR      r4,[r2,#0]
+	LDR      r7,[r9,#4]
+	LDR      r6,[r8,#4]
+	LDR      r5,[r2,#4]
+	LDR      r4,[r12,#4]
+	STR      r6,[r9,#4]
+	STR      r7,[r8,#4]
+	STR      r5,[r12,#4]
+	STR      r4,[r2,#4]
+	ADDS     r1,r1,#8
+	SUBS     r3,r3,#1
+	BNE      arm_bitreversal_32_0
+	POP      {r4-r9}
+	BX       lr
+	ENDP
+
+arm_bitreversal_16 PROC
+	ADDS     r3,r1,#1
+	CMP      r3,#1
+	IT       LS
+	BXLS     lr
+	PUSH     {r4-r9}
+	ADDS     r1,r2,#2
+	LSRS     r3,r3,#2
+arm_bitreversal_16_0 LABEL       ;/* loop unrolled by 2 */
+	LDRH     r8,[r1,#4]
+	LDRH     r9,[r1,#2]
+	LDRH     r2,[r1,#0]
+	LDRH     r12,[r1,#-2]
+	ADD      r8,r0,r8,LSR #1
+	ADD      r9,r0,r9,LSR #1
+	ADD      r2,r0,r2,LSR #1
+	ADD      r12,r0,r12,LSR #1
+	LDR      r7,[r9,#0]
+	LDR      r6,[r8,#0]
+	LDR      r5,[r2,#0]
+	LDR      r4,[r12,#0]
+	STR      r6,[r9,#0]
+	STR      r7,[r8,#0]
+	STR      r5,[r12,#0]
+	STR      r4,[r2,#0]
+	ADDS     r1,r1,#8
+	SUBS     r3,r3,#1
+	BNE      arm_bitreversal_16_0
+	POP      {r4-r9}
+	BX       lr
+	ENDP
+
+#endif
+
+	END
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c
new file mode 100644
index 0000000..2593202
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c
@@ -0,0 +1,620 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_f32.c
+ * Description:  Combined Radix Decimation in Frequency CFFT Floating point processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern void arm_radix8_butterfly_f32(
+    float32_t * pSrc,
+    uint16_t fftLen,
+    const float32_t * pCoef,
+    uint16_t twidCoefModifier);
+
+extern void arm_bitreversal_32(
+    uint32_t * pSrc,
+    const uint16_t bitRevLen,
+    const uint16_t * pBitRevTable);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @defgroup ComplexFFT Complex FFT Functions
+*
+* \par
+* The Fast Fourier Transform (FFT) is an efficient algorithm for computing the
+* Discrete Fourier Transform (DFT).  The FFT can be orders of magnitude faster
+* than the DFT, especially for long lengths.
+* The algorithms described in this section
+* operate on complex data.  A separate set of functions is devoted to handling
+* of real sequences.
+* \par
+* There are separate algorithms for handling floating-point, Q15, and Q31 data
+* types.  The algorithms available for each data type are described next.
+* \par
+* The FFT functions operate in-place.  That is, the array holding the input data
+* will also be used to hold the corresponding result.  The input data is complex
+* and contains 2*fftLen interleaved values as shown below.
+* 
 {real[0], imag[0], real[1], imag[1],..} 

+* The FFT result will be contained in the same array and the frequency domain
+* values will have the same interleaving.
+*
+* \par Floating-point
+* The floating-point complex FFT uses a mixed-radix algorithm.  Multiple radix-8
+* stages are performed along with a single radix-2 or radix-4 stage, as needed.
+* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
+* a different twiddle factor table.
+* \par
+* The function uses the standard FFT definition and output values may grow by a
+* factor of fftLen when computing the forward transform.  The
+* inverse transform includes a scale of 1/fftLen as part of the
+* calculation and this matches the textbook definition of the inverse FFT.
+* \par
+* Pre-initialized data structures containing twiddle factors and bit reversal
+* tables are provided and defined in arm_const_structs.h.  Include
+* this header in your function and then pass one of the constant structures as
+* an argument to arm_cfft_f32.  For example:
+* \par
+* arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1)
+* \par
+* computes a 64-point inverse complex FFT including bit reversal.
+* The data structures are treated as constant data and not modified during the
+* calculation.  The same data structure can be reused for multiple transforms
+* including mixing forward and inverse transforms.
+* \par
+* Earlier releases of the library provided separate radix-2 and radix-4
+* algorithms that operated on floating-point data.  These functions are still
+* provided but are deprecated.  The older functions are slower and less general
+* than the new functions.
+* \par
+* An example of initialization of the constants for the arm_cfft_f32 function follows:
+* \code
+* const static arm_cfft_instance_f32 *S;
+* ...
+*   switch (length) {
+*     case 16:
+*       S = &arm_cfft_sR_f32_len16;
+*       break;
+*     case 32:
+*       S = &arm_cfft_sR_f32_len32;
+*       break;
+*     case 64:
+*       S = &arm_cfft_sR_f32_len64;
+*       break;
+*     case 128:
+*       S = &arm_cfft_sR_f32_len128;
+*       break;
+*     case 256:
+*       S = &arm_cfft_sR_f32_len256;
+*       break;
+*     case 512:
+*       S = &arm_cfft_sR_f32_len512;
+*       break;
+*     case 1024:
+*       S = &arm_cfft_sR_f32_len1024;
+*       break;
+*     case 2048:
+*       S = &arm_cfft_sR_f32_len2048;
+*       break;
+*     case 4096:
+*       S = &arm_cfft_sR_f32_len4096;
+*       break;
+*   }
+* \endcode
+* \par Q15 and Q31
+* The floating-point complex FFT uses a mixed-radix algorithm.  Multiple radix-4
+* stages are performed along with a single radix-2 stage, as needed.
+* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
+* a different twiddle factor table.
+* \par
+* The function uses the standard FFT definition and output values may grow by a
+* factor of fftLen when computing the forward transform.  The
+* inverse transform includes a scale of 1/fftLen as part of the
+* calculation and this matches the textbook definition of the inverse FFT.
+* \par
+* Pre-initialized data structures containing twiddle factors and bit reversal
+* tables are provided and defined in arm_const_structs.h.  Include
+* this header in your function and then pass one of the constant structures as
+* an argument to arm_cfft_q31.  For example:
+* \par
+* arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1)
+* \par
+* computes a 64-point inverse complex FFT including bit reversal.
+* The data structures are treated as constant data and not modified during the
+* calculation.  The same data structure can be reused for multiple transforms
+* including mixing forward and inverse transforms.
+* \par
+* Earlier releases of the library provided separate radix-2 and radix-4
+* algorithms that operated on floating-point data.  These functions are still
+* provided but are deprecated.  The older functions are slower and less general
+* than the new functions.
+* \par
+* An example of initialization of the constants for the arm_cfft_q31 function follows:
+* \code
+* const static arm_cfft_instance_q31 *S;
+* ...
+*   switch (length) {
+*     case 16:
+*       S = &arm_cfft_sR_q31_len16;
+*       break;
+*     case 32:
+*       S = &arm_cfft_sR_q31_len32;
+*       break;
+*     case 64:
+*       S = &arm_cfft_sR_q31_len64;
+*       break;
+*     case 128:
+*       S = &arm_cfft_sR_q31_len128;
+*       break;
+*     case 256:
+*       S = &arm_cfft_sR_q31_len256;
+*       break;
+*     case 512:
+*       S = &arm_cfft_sR_q31_len512;
+*       break;
+*     case 1024:
+*       S = &arm_cfft_sR_q31_len1024;
+*       break;
+*     case 2048:
+*       S = &arm_cfft_sR_q31_len2048;
+*       break;
+*     case 4096:
+*       S = &arm_cfft_sR_q31_len4096;
+*       break;
+*   }
+* \endcode
+*
+*/
+
+void arm_cfft_radix8by2_f32( arm_cfft_instance_f32 * S, float32_t * p1)
+{
+    uint32_t    L  = S->fftLen;
+    float32_t * pCol1, * pCol2, * pMid1, * pMid2;
+    float32_t * p2 = p1 + L;
+    const float32_t * tw = (float32_t *) S->pTwiddle;
+    float32_t t1[4], t2[4], t3[4], t4[4], twR, twI;
+    float32_t m0, m1, m2, m3;
+    uint32_t l;
+
+    pCol1 = p1;
+    pCol2 = p2;
+
+    //    Define new length
+    L >>= 1;
+    //    Initialize mid pointers
+    pMid1 = p1 + L;
+    pMid2 = p2 + L;
+
+    // do two dot Fourier transform
+    for ( l = L >> 2; l > 0; l-- )
+    {
+        t1[0] = p1[0];
+        t1[1] = p1[1];
+        t1[2] = p1[2];
+        t1[3] = p1[3];
+
+        t2[0] = p2[0];
+        t2[1] = p2[1];
+        t2[2] = p2[2];
+        t2[3] = p2[3];
+
+        t3[0] = pMid1[0];
+        t3[1] = pMid1[1];
+        t3[2] = pMid1[2];
+        t3[3] = pMid1[3];
+
+        t4[0] = pMid2[0];
+        t4[1] = pMid2[1];
+        t4[2] = pMid2[2];
+        t4[3] = pMid2[3];
+
+        *p1++ = t1[0] + t2[0];
+        *p1++ = t1[1] + t2[1];
+        *p1++ = t1[2] + t2[2];
+        *p1++ = t1[3] + t2[3];    // col 1
+
+        t2[0] = t1[0] - t2[0];
+        t2[1] = t1[1] - t2[1];
+        t2[2] = t1[2] - t2[2];
+        t2[3] = t1[3] - t2[3];    // for col 2
+
+        *pMid1++ = t3[0] + t4[0];
+        *pMid1++ = t3[1] + t4[1];
+        *pMid1++ = t3[2] + t4[2];
+        *pMid1++ = t3[3] + t4[3]; // col 1
+
+        t4[0] = t4[0] - t3[0];
+        t4[1] = t4[1] - t3[1];
+        t4[2] = t4[2] - t3[2];
+        t4[3] = t4[3] - t3[3];    // for col 2
+
+        twR = *tw++;
+        twI = *tw++;
+
+        // multiply by twiddle factors
+        m0 = t2[0] * twR;
+        m1 = t2[1] * twI;
+        m2 = t2[1] * twR;
+        m3 = t2[0] * twI;
+
+        // R  =  R  *  Tr - I * Ti
+        *p2++ = m0 + m1;
+        // I  =  I  *  Tr + R * Ti
+        *p2++ = m2 - m3;
+
+        // use vertical symmetry
+        //  0.9988 - 0.0491i <==> -0.0491 - 0.9988i
+        m0 = t4[0] * twI;
+        m1 = t4[1] * twR;
+        m2 = t4[1] * twI;
+        m3 = t4[0] * twR;
+
+        *pMid2++ = m0 - m1;
+        *pMid2++ = m2 + m3;
+
+        twR = *tw++;
+        twI = *tw++;
+
+        m0 = t2[2] * twR;
+        m1 = t2[3] * twI;
+        m2 = t2[3] * twR;
+        m3 = t2[2] * twI;
+
+        *p2++ = m0 + m1;
+        *p2++ = m2 - m3;
+
+        m0 = t4[2] * twI;
+        m1 = t4[3] * twR;
+        m2 = t4[3] * twI;
+        m3 = t4[2] * twR;
+
+        *pMid2++ = m0 - m1;
+        *pMid2++ = m2 + m3;
+    }
+
+    // first col
+    arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 2U);
+    // second col
+    arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 2U);
+}
+
+void arm_cfft_radix8by4_f32( arm_cfft_instance_f32 * S, float32_t * p1)
+{
+    uint32_t    L  = S->fftLen >> 1;
+    float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4;
+    const float32_t *tw2, *tw3, *tw4;
+    float32_t * p2 = p1 + L;
+    float32_t * p3 = p2 + L;
+    float32_t * p4 = p3 + L;
+    float32_t t2[4], t3[4], t4[4], twR, twI;
+    float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1;
+    float32_t m0, m1, m2, m3;
+    uint32_t l, twMod2, twMod3, twMod4;
+
+    pCol1 = p1;         // points to real values by default
+    pCol2 = p2;
+    pCol3 = p3;
+    pCol4 = p4;
+    pEnd1 = p2 - 1;     // points to imaginary values by default
+    pEnd2 = p3 - 1;
+    pEnd3 = p4 - 1;
+    pEnd4 = pEnd3 + L;
+
+    tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle;
+
+    L >>= 1;
+
+    // do four dot Fourier transform
+
+    twMod2 = 2;
+    twMod3 = 4;
+    twMod4 = 6;
+
+    // TOP
+    p1ap3_0 = p1[0] + p3[0];
+    p1sp3_0 = p1[0] - p3[0];
+    p1ap3_1 = p1[1] + p3[1];
+    p1sp3_1 = p1[1] - p3[1];
+
+    // col 2
+    t2[0] = p1sp3_0 + p2[1] - p4[1];
+    t2[1] = p1sp3_1 - p2[0] + p4[0];
+    // col 3
+    t3[0] = p1ap3_0 - p2[0] - p4[0];
+    t3[1] = p1ap3_1 - p2[1] - p4[1];
+    // col 4
+    t4[0] = p1sp3_0 - p2[1] + p4[1];
+    t4[1] = p1sp3_1 + p2[0] - p4[0];
+    // col 1
+    *p1++ = p1ap3_0 + p2[0] + p4[0];
+    *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+    // Twiddle factors are ones
+    *p2++ = t2[0];
+    *p2++ = t2[1];
+    *p3++ = t3[0];
+    *p3++ = t3[1];
+    *p4++ = t4[0];
+    *p4++ = t4[1];
+
+    tw2 += twMod2;
+    tw3 += twMod3;
+    tw4 += twMod4;
+
+    for (l = (L - 2) >> 1; l > 0; l-- )
+    {
+        // TOP
+        p1ap3_0 = p1[0] + p3[0];
+        p1sp3_0 = p1[0] - p3[0];
+        p1ap3_1 = p1[1] + p3[1];
+        p1sp3_1 = p1[1] - p3[1];
+        // col 2
+        t2[0] = p1sp3_0 + p2[1] - p4[1];
+        t2[1] = p1sp3_1 - p2[0] + p4[0];
+        // col 3
+        t3[0] = p1ap3_0 - p2[0] - p4[0];
+        t3[1] = p1ap3_1 - p2[1] - p4[1];
+        // col 4
+        t4[0] = p1sp3_0 - p2[1] + p4[1];
+        t4[1] = p1sp3_1 + p2[0] - p4[0];
+        // col 1 - top
+        *p1++ = p1ap3_0 + p2[0] + p4[0];
+        *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+        // BOTTOM
+        p1ap3_1 = pEnd1[-1] + pEnd3[-1];
+        p1sp3_1 = pEnd1[-1] - pEnd3[-1];
+        p1ap3_0 = pEnd1[0] + pEnd3[0];
+        p1sp3_0 = pEnd1[0] - pEnd3[0];
+        // col 2
+        t2[2] = pEnd2[0]  - pEnd4[0] + p1sp3_1;
+        t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1];
+        // col 3
+        t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1];
+        t3[3] = p1ap3_0 - pEnd2[0]  - pEnd4[0];
+        // col 4
+        t4[2] = pEnd2[0]  - pEnd4[0]  - p1sp3_1;
+        t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0;
+        // col 1 - Bottom
+        *pEnd1-- = p1ap3_0 + pEnd2[0] + pEnd4[0];
+        *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1];
+
+        // COL 2
+        // read twiddle factors
+        twR = *tw2++;
+        twI = *tw2++;
+        // multiply by twiddle factors
+        //  let    Z1 = a + i(b),   Z2 = c + i(d)
+        //   =>  Z1 * Z2  =  (a*c - b*d) + i(b*c + a*d)
+
+        // Top
+        m0 = t2[0] * twR;
+        m1 = t2[1] * twI;
+        m2 = t2[1] * twR;
+        m3 = t2[0] * twI;
+
+        *p2++ = m0 + m1;
+        *p2++ = m2 - m3;
+        // use vertical symmetry col 2
+        // 0.9997 - 0.0245i  <==>  0.0245 - 0.9997i
+        // Bottom
+        m0 = t2[3] * twI;
+        m1 = t2[2] * twR;
+        m2 = t2[2] * twI;
+        m3 = t2[3] * twR;
+
+        *pEnd2-- = m0 - m1;
+        *pEnd2-- = m2 + m3;
+
+        // COL 3
+        twR = tw3[0];
+        twI = tw3[1];
+        tw3 += twMod3;
+        // Top
+        m0 = t3[0] * twR;
+        m1 = t3[1] * twI;
+        m2 = t3[1] * twR;
+        m3 = t3[0] * twI;
+
+        *p3++ = m0 + m1;
+        *p3++ = m2 - m3;
+        // use vertical symmetry col 3
+        // 0.9988 - 0.0491i  <==>  -0.9988 - 0.0491i
+        // Bottom
+        m0 = -t3[3] * twR;
+        m1 = t3[2] * twI;
+        m2 = t3[2] * twR;
+        m3 = t3[3] * twI;
+
+        *pEnd3-- = m0 - m1;
+        *pEnd3-- = m3 - m2;
+
+        // COL 4
+        twR = tw4[0];
+        twI = tw4[1];
+        tw4 += twMod4;
+        // Top
+        m0 = t4[0] * twR;
+        m1 = t4[1] * twI;
+        m2 = t4[1] * twR;
+        m3 = t4[0] * twI;
+
+        *p4++ = m0 + m1;
+        *p4++ = m2 - m3;
+        // use vertical symmetry col 4
+        // 0.9973 - 0.0736i  <==>  -0.0736 + 0.9973i
+        // Bottom
+        m0 = t4[3] * twI;
+        m1 = t4[2] * twR;
+        m2 = t4[2] * twI;
+        m3 = t4[3] * twR;
+
+        *pEnd4-- = m0 - m1;
+        *pEnd4-- = m2 + m3;
+    }
+
+    //MIDDLE
+    // Twiddle factors are
+    //  1.0000  0.7071-0.7071i  -1.0000i  -0.7071-0.7071i
+    p1ap3_0 = p1[0] + p3[0];
+    p1sp3_0 = p1[0] - p3[0];
+    p1ap3_1 = p1[1] + p3[1];
+    p1sp3_1 = p1[1] - p3[1];
+
+    // col 2
+    t2[0] = p1sp3_0 + p2[1] - p4[1];
+    t2[1] = p1sp3_1 - p2[0] + p4[0];
+    // col 3
+    t3[0] = p1ap3_0 - p2[0] - p4[0];
+    t3[1] = p1ap3_1 - p2[1] - p4[1];
+    // col 4
+    t4[0] = p1sp3_0 - p2[1] + p4[1];
+    t4[1] = p1sp3_1 + p2[0] - p4[0];
+    // col 1 - Top
+    *p1++ = p1ap3_0 + p2[0] + p4[0];
+    *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+    // COL 2
+    twR = tw2[0];
+    twI = tw2[1];
+
+    m0 = t2[0] * twR;
+    m1 = t2[1] * twI;
+    m2 = t2[1] * twR;
+    m3 = t2[0] * twI;
+
+    *p2++ = m0 + m1;
+    *p2++ = m2 - m3;
+    // COL 3
+    twR = tw3[0];
+    twI = tw3[1];
+
+    m0 = t3[0] * twR;
+    m1 = t3[1] * twI;
+    m2 = t3[1] * twR;
+    m3 = t3[0] * twI;
+
+    *p3++ = m0 + m1;
+    *p3++ = m2 - m3;
+    // COL 4
+    twR = tw4[0];
+    twI = tw4[1];
+
+    m0 = t4[0] * twR;
+    m1 = t4[1] * twI;
+    m2 = t4[1] * twR;
+    m3 = t4[0] * twI;
+
+    *p4++ = m0 + m1;
+    *p4++ = m2 - m3;
+
+    // first col
+    arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 4U);
+    // second col
+    arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 4U);
+    // third col
+    arm_radix8_butterfly_f32( pCol3, L, (float32_t *) S->pTwiddle, 4U);
+    // fourth col
+    arm_radix8_butterfly_f32( pCol4, L, (float32_t *) S->pTwiddle, 4U);
+}
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief       Processing function for the floating-point complex FFT.
+* @param[in]      *S    points to an instance of the floating-point CFFT structure.
+* @param[in, out] *p1   points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return none.
+*/
+
+void arm_cfft_f32(
+    const arm_cfft_instance_f32 * S,
+    float32_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag)
+{
+    uint32_t  L = S->fftLen, l;
+    float32_t invL, * pSrc;
+
+    if (ifftFlag == 1U)
+    {
+        /*  Conjugate input data  */
+        pSrc = p1 + 1;
+        for(l=0; lpTwiddle, 1);
+        break;
+    }
+
+    if ( bitReverseFlag )
+        arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);
+
+    if (ifftFlag == 1U)
+    {
+        invL = 1.0f/(float32_t)L;
+        /*  Conjugate and scale output data */
+        pSrc = p1;
+        for(l=0; l2*fftLen. Processing occurs in-place.
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return none.
+*/
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15 * S,
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag)
+{
+    uint32_t L = S->fftLen;
+
+    if (ifftFlag == 1U)
+    {
+        switch (L)
+        {
+        case 16:
+        case 64:
+        case 256:
+        case 1024:
+        case 4096:
+            arm_radix4_butterfly_inverse_q15  ( p1, L, (q15_t*)S->pTwiddle, 1 );
+            break;
+
+        case 32:
+        case 128:
+        case 512:
+        case 2048:
+            arm_cfft_radix4by2_inverse_q15  ( p1, L, S->pTwiddle );
+            break;
+        }
+    }
+    else
+    {
+        switch (L)
+        {
+        case 16:
+        case 64:
+        case 256:
+        case 1024:
+        case 4096:
+            arm_radix4_butterfly_q15  ( p1, L, (q15_t*)S->pTwiddle, 1 );
+            break;
+
+        case 32:
+        case 128:
+        case 512:
+        case 2048:
+            arm_cfft_radix4by2_q15  ( p1, L, S->pTwiddle );
+            break;
+        }
+    }
+
+    if ( bitReverseFlag )
+        arm_bitreversal_16((uint16_t*)p1,S->bitRevLength,S->pBitRevTable);
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
+void arm_cfft_radix4by2_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    const q15_t * pCoef)
+{
+    uint32_t i;
+    uint32_t n2;
+    q15_t p0, p1, p2, p3;
+#if defined (ARM_MATH_DSP)
+    q31_t T, S, R;
+    q31_t coeff, out1, out2;
+    const q15_t *pC = pCoef;
+    q15_t *pSi = pSrc;
+    q15_t *pSl = pSrc + fftLen;
+#else
+    uint32_t ia, l;
+    q15_t xt, yt, cosVal, sinVal;
+#endif
+
+    n2 = fftLen >> 1;
+
+#if defined (ARM_MATH_DSP)
+
+    for (i = n2; i > 0; i--)
+    {
+        coeff = _SIMD32_OFFSET(pC);
+        pC += 2;
+
+        T = _SIMD32_OFFSET(pSi);
+        T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
+
+        S = _SIMD32_OFFSET(pSl);
+        S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
+        pSi += 2;
+
+    #ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(coeff, R) >> 16;
+        out2 = __SMUSDX(coeff, R);
+
+    #else
+
+        out1 = __SMUSDX(R, coeff) >> 16U;
+        out2 = __SMUAD(coeff, R);
+
+    #endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSl) =
+        (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSl += 2;
+    }
+
+#else //    #if defined (ARM_MATH_DSP)
+
+    ia = 0;
+    for (i = 0; i < n2; i++)
+    {
+        cosVal = pCoef[ia * 2];
+        sinVal = pCoef[(ia * 2) + 1];
+        ia++;
+
+        l = i + n2;
+
+        xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U);
+        pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U;
+
+        yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U);
+        pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U;
+
+        pSrc[2U * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+                  ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+        pSrc[2U * l + 1U] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+                       ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+    }
+
+#endif //    #if defined (ARM_MATH_DSP)
+
+    // first col
+    arm_radix4_butterfly_q15( pSrc, n2, (q15_t*)pCoef, 2U);
+    // second col
+    arm_radix4_butterfly_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U);
+
+    for (i = 0; i < fftLen >> 1; i++)
+    {
+        p0 = pSrc[4*i+0];
+        p1 = pSrc[4*i+1];
+        p2 = pSrc[4*i+2];
+        p3 = pSrc[4*i+3];
+
+        p0 <<= 1;
+        p1 <<= 1;
+        p2 <<= 1;
+        p3 <<= 1;
+
+        pSrc[4*i+0] = p0;
+        pSrc[4*i+1] = p1;
+        pSrc[4*i+2] = p2;
+        pSrc[4*i+3] = p3;
+    }
+}
+
+void arm_cfft_radix4by2_inverse_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    const q15_t * pCoef)
+{
+    uint32_t i;
+    uint32_t n2;
+    q15_t p0, p1, p2, p3;
+#if defined (ARM_MATH_DSP)
+    q31_t T, S, R;
+    q31_t coeff, out1, out2;
+    const q15_t *pC = pCoef;
+    q15_t *pSi = pSrc;
+    q15_t *pSl = pSrc + fftLen;
+#else
+    uint32_t ia, l;
+    q15_t xt, yt, cosVal, sinVal;
+#endif
+
+    n2 = fftLen >> 1;
+
+#if defined (ARM_MATH_DSP)
+
+    for (i = n2; i > 0; i--)
+    {
+        coeff = _SIMD32_OFFSET(pC);
+        pC += 2;
+
+        T = _SIMD32_OFFSET(pSi);
+        T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
+
+        S = _SIMD32_OFFSET(pSl);
+        S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
+        pSi += 2;
+
+    #ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(coeff, R) >> 16;
+        out2 = __SMUADX(coeff, R);
+    #else
+
+        out1 = __SMUADX(R, coeff) >> 16U;
+        out2 = __SMUSD(__QSUB(0, coeff), R);
+
+    #endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSl) =
+        (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSl += 2;
+    }
+
+#else //    #if defined (ARM_MATH_DSP)
+
+    ia = 0;
+    for (i = 0; i < n2; i++)
+    {
+        cosVal = pCoef[ia * 2];
+        sinVal = pCoef[(ia * 2) + 1];
+        ia++;
+
+        l = i + n2;
+        xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U);
+        pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U;
+
+        yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U);
+        pSrc[2 * i + 1] =
+          ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U;
+
+        pSrc[2U * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+        pSrc[2U * l + 1U] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+    }
+
+#endif //    #if defined (ARM_MATH_DSP)
+
+    // first col
+    arm_radix4_butterfly_inverse_q15( pSrc, n2, (q15_t*)pCoef, 2U);
+    // second col
+    arm_radix4_butterfly_inverse_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U);
+
+    for (i = 0; i < fftLen >> 1; i++)
+    {
+        p0 = pSrc[4*i+0];
+        p1 = pSrc[4*i+1];
+        p2 = pSrc[4*i+2];
+        p3 = pSrc[4*i+3];
+
+        p0 <<= 1;
+        p1 <<= 1;
+        p2 <<= 1;
+        p3 <<= 1;
+
+        pSrc[4*i+0] = p0;
+        pSrc[4*i+1] = p1;
+        pSrc[4*i+2] = p2;
+        pSrc[4*i+3] = p3;
+    }
+}
+
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c
new file mode 100644
index 0000000..934a3fc
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c
@@ -0,0 +1,252 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_q31.c
+ * Description:  Combined Radix Decimation in Frequency CFFT fixed point processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+extern void arm_radix4_butterfly_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pCoef,
+    uint32_t twidCoefModifier);
+
+extern void arm_radix4_butterfly_inverse_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pCoef,
+    uint32_t twidCoefModifier);
+
+extern void arm_bitreversal_32(
+    uint32_t * pSrc,
+    const uint16_t bitRevLen,
+    const uint16_t * pBitRevTable);
+
+void arm_cfft_radix4by2_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    const q31_t * pCoef);
+
+void arm_cfft_radix4by2_inverse_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    const q31_t * pCoef);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief       Processing function for the fixed-point complex FFT in Q31 format.
+* @param[in]      *S    points to an instance of the fixed-point CFFT structure.
+* @param[in, out] *p1   points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return none.
+*/
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31 * S,
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag)
+{
+    uint32_t L = S->fftLen;
+
+    if (ifftFlag == 1U)
+    {
+        switch (L)
+        {
+        case 16:
+        case 64:
+        case 256:
+        case 1024:
+        case 4096:
+            arm_radix4_butterfly_inverse_q31  ( p1, L, (q31_t*)S->pTwiddle, 1 );
+            break;
+
+        case 32:
+        case 128:
+        case 512:
+        case 2048:
+            arm_cfft_radix4by2_inverse_q31  ( p1, L, S->pTwiddle );
+            break;
+        }
+    }
+    else
+    {
+        switch (L)
+        {
+        case 16:
+        case 64:
+        case 256:
+        case 1024:
+        case 4096:
+            arm_radix4_butterfly_q31  ( p1, L, (q31_t*)S->pTwiddle, 1 );
+            break;
+
+        case 32:
+        case 128:
+        case 512:
+        case 2048:
+            arm_cfft_radix4by2_q31  ( p1, L, S->pTwiddle );
+            break;
+        }
+    }
+
+    if ( bitReverseFlag )
+        arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
+void arm_cfft_radix4by2_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    const q31_t * pCoef)
+{
+    uint32_t i, l;
+    uint32_t n2, ia;
+    q31_t xt, yt, cosVal, sinVal;
+    q31_t p0, p1;
+
+    n2 = fftLen >> 1;
+    ia = 0;
+    for (i = 0; i < n2; i++)
+    {
+        cosVal = pCoef[2*ia];
+        sinVal = pCoef[2*ia + 1];
+        ia++;
+
+        l = i + n2;
+        xt = (pSrc[2 * i] >> 2) - (pSrc[2 * l] >> 2);
+        pSrc[2 * i] = (pSrc[2 * i] >> 2) + (pSrc[2 * l] >> 2);
+
+        yt = (pSrc[2 * i + 1] >> 2) - (pSrc[2 * l + 1] >> 2);
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2) + (pSrc[2 * i + 1] >> 2);
+
+        mult_32x32_keep32_R(p0, xt, cosVal);
+        mult_32x32_keep32_R(p1, yt, cosVal);
+        multAcc_32x32_keep32_R(p0, yt, sinVal);
+        multSub_32x32_keep32_R(p1, xt, sinVal);
+
+        pSrc[2U * l] = p0 << 1;
+        pSrc[2U * l + 1U] = p1 << 1;
+
+    }
+
+    // first col
+    arm_radix4_butterfly_q31( pSrc, n2, (q31_t*)pCoef, 2U);
+    // second col
+    arm_radix4_butterfly_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2U);
+
+    for (i = 0; i < fftLen >> 1; i++)
+    {
+        p0 = pSrc[4*i+0];
+        p1 = pSrc[4*i+1];
+        xt = pSrc[4*i+2];
+        yt = pSrc[4*i+3];
+
+        p0 <<= 1;
+        p1 <<= 1;
+        xt <<= 1;
+        yt <<= 1;
+
+        pSrc[4*i+0] = p0;
+        pSrc[4*i+1] = p1;
+        pSrc[4*i+2] = xt;
+        pSrc[4*i+3] = yt;
+    }
+
+}
+
+void arm_cfft_radix4by2_inverse_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    const q31_t * pCoef)
+{
+    uint32_t i, l;
+    uint32_t n2, ia;
+    q31_t xt, yt, cosVal, sinVal;
+    q31_t p0, p1;
+
+    n2 = fftLen >> 1;
+    ia = 0;
+    for (i = 0; i < n2; i++)
+    {
+        cosVal = pCoef[2*ia];
+        sinVal = pCoef[2*ia + 1];
+        ia++;
+
+        l = i + n2;
+        xt = (pSrc[2 * i] >> 2) - (pSrc[2 * l] >> 2);
+        pSrc[2 * i] = (pSrc[2 * i] >> 2) + (pSrc[2 * l] >> 2);
+
+        yt = (pSrc[2 * i + 1] >> 2) - (pSrc[2 * l + 1] >> 2);
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2) + (pSrc[2 * i + 1] >> 2);
+
+        mult_32x32_keep32_R(p0, xt, cosVal);
+        mult_32x32_keep32_R(p1, yt, cosVal);
+        multSub_32x32_keep32_R(p0, yt, sinVal);
+        multAcc_32x32_keep32_R(p1, xt, sinVal);
+
+        pSrc[2U * l] = p0 << 1;
+        pSrc[2U * l + 1U] = p1 << 1;
+
+    }
+
+    // first col
+    arm_radix4_butterfly_inverse_q31( pSrc, n2, (q31_t*)pCoef, 2U);
+    // second col
+    arm_radix4_butterfly_inverse_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2U);
+
+    for (i = 0; i < fftLen >> 1; i++)
+    {
+        p0 = pSrc[4*i+0];
+        p1 = pSrc[4*i+1];
+        xt = pSrc[4*i+2];
+        yt = pSrc[4*i+3];
+
+        p0 <<= 1;
+        p1 <<= 1;
+        xt <<= 1;
+        yt <<= 1;
+
+        pSrc[4*i+0] = p0;
+        pSrc[4*i+1] = p1;
+        pSrc[4*i+2] = xt;
+        pSrc[4*i+3] = yt;
+    }
+}
+
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c
new file mode 100644
index 0000000..45bcc3b
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c
@@ -0,0 +1,472 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix2_f32.c
+ * Description:  Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier,
+  float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+    float32_t * pSrc,
+    uint16_t fftSize,
+    uint16_t bitRevFactor,
+    uint16_t * pBitRevTab);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Radix-2 CFFT/CIFFT.
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in]      *S    points to an instance of the floating-point Radix-2 CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix2_f32(
+const arm_cfft_radix2_instance_f32 * S,
+float32_t * pSrc)
+{
+
+   if (S->ifftFlag == 1U)
+   {
+      /*  Complex IFFT radix-2  */
+      arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+      S->twidCoefModifier, S->onebyfftLen);
+   }
+   else
+   {
+      /*  Complex FFT radix-2  */
+      arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+      S->twidCoefModifier);
+   }
+
+   if (S->bitReverseFlag == 1U)
+   {
+      /*  Bit Reversal */
+      arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+   }
+
+}
+
+
+/**
+* @} end of ComplexFFT group
+*/
+
+
+
+/* ----------------------------------------------------------------------
+** Internal helper function used by the FFTs
+** ------------------------------------------------------------------- */
+
+/*
+* @brief  Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+* @param[in]      fftLen           length of the FFT.
+* @param[in]      *pCoef           points to the twiddle coefficient buffer.
+* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix2_butterfly_f32(
+float32_t * pSrc,
+uint32_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+   uint32_t i, j, k, l;
+   uint32_t n1, n2, ia;
+   float32_t xt, yt, cosVal, sinVal;
+   float32_t p0, p1, p2, p3;
+   float32_t a0, a1;
+
+#if defined (ARM_MATH_DSP)
+
+   /*  Initializations for the first stage */
+   n2 = fftLen >> 1;
+   ia = 0;
+   i = 0;
+
+   // loop for groups
+   for (k = n2; k > 0; k--)
+   {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+
+      /*  Twiddle coefficients index modifier */
+      ia += twidCoefModifier;
+
+      /*  index calculation for the input as, */
+      /*  pSrc[i + 0], pSrc[i + fftLen/1] */
+      l = i + n2;
+
+      /*  Butterfly implementation */
+      a0 = pSrc[2 * i] + pSrc[2 * l];
+      xt = pSrc[2 * i] - pSrc[2 * l];
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+      p0 = xt * cosVal;
+      p1 = yt * sinVal;
+      p2 = yt * cosVal;
+      p3 = xt * sinVal;
+
+      pSrc[2 * i]     = a0;
+      pSrc[2 * i + 1] = a1;
+
+      pSrc[2 * l]     = p0 + p1;
+      pSrc[2 * l + 1] = p2 - p3;
+
+      i++;
+   }                             // groups loop end
+
+   twidCoefModifier <<= 1U;
+
+   // loop for stage
+   for (k = n2; k > 2; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups
+      j = 0;
+      do
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia += twidCoefModifier;
+
+         // loop for butterfly
+         i = j;
+         do
+         {
+            l = i + n2;
+            a0 = pSrc[2 * i] + pSrc[2 * l];
+            xt = pSrc[2 * i] - pSrc[2 * l];
+
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+            p0 = xt * cosVal;
+            p1 = yt * sinVal;
+            p2 = yt * cosVal;
+            p3 = xt * sinVal;
+
+            pSrc[2 * i] = a0;
+            pSrc[2 * i + 1] = a1;
+
+            pSrc[2 * l]     = p0 + p1;
+            pSrc[2 * l + 1] = p2 - p3;
+
+            i += n1;
+         } while ( i < fftLen );                        // butterfly loop end
+         j++;
+      } while ( j < n2);                          // groups loop end
+      twidCoefModifier <<= 1U;
+   }                             // stages loop end
+
+   // loop for butterfly
+   for (i = 0; i < fftLen; i += 2)
+   {
+      a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+      xt = pSrc[2 * i] - pSrc[2 * i + 2];
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+      a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+
+      pSrc[2 * i] = a0;
+      pSrc[2 * i + 1] = a1;
+      pSrc[2 * i + 2] = xt;
+      pSrc[2 * i + 3] = yt;
+   }                             // groups loop end
+
+#else
+
+   n2 = fftLen;
+
+   // loop for stage
+   for (k = fftLen; k > 1; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups
+      j = 0;
+      do
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia += twidCoefModifier;
+
+         // loop for butterfly
+         i = j;
+         do
+         {
+            l = i + n2;
+            a0 = pSrc[2 * i] + pSrc[2 * l];
+            xt = pSrc[2 * i] - pSrc[2 * l];
+
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+            p0 = xt * cosVal;
+            p1 = yt * sinVal;
+            p2 = yt * cosVal;
+            p3 = xt * sinVal;
+
+            pSrc[2 * i] = a0;
+            pSrc[2 * i + 1] = a1;
+
+            pSrc[2 * l]     = p0 + p1;
+            pSrc[2 * l + 1] = p2 - p3;
+
+            i += n1;
+         } while (i < fftLen);
+         j++;
+      } while (j < n2);
+      twidCoefModifier <<= 1U;
+   }
+
+#endif //    #if defined (ARM_MATH_DSP)
+
+}
+
+
+void arm_radix2_butterfly_inverse_f32(
+float32_t * pSrc,
+uint32_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier,
+float32_t onebyfftLen)
+{
+
+   uint32_t i, j, k, l;
+   uint32_t n1, n2, ia;
+   float32_t xt, yt, cosVal, sinVal;
+   float32_t p0, p1, p2, p3;
+   float32_t a0, a1;
+
+#if defined (ARM_MATH_DSP)
+
+   n2 = fftLen >> 1;
+   ia = 0;
+
+   // loop for groups
+   for (i = 0; i < n2; i++)
+   {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia += twidCoefModifier;
+
+      l = i + n2;
+      a0 = pSrc[2 * i] + pSrc[2 * l];
+      xt = pSrc[2 * i] - pSrc[2 * l];
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+      p0 = xt * cosVal;
+      p1 = yt * sinVal;
+      p2 = yt * cosVal;
+      p3 = xt * sinVal;
+
+      pSrc[2 * i] = a0;
+      pSrc[2 * i + 1] = a1;
+
+      pSrc[2 * l]     = p0 - p1;
+      pSrc[2 * l + 1] = p2 + p3;
+   }                             // groups loop end
+
+   twidCoefModifier <<= 1U;
+
+   // loop for stage
+   for (k = fftLen / 2; k > 2; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups
+      j = 0;
+      do
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia += twidCoefModifier;
+
+         // loop for butterfly
+         i = j;
+         do
+         {
+            l = i + n2;
+            a0 = pSrc[2 * i] + pSrc[2 * l];
+            xt = pSrc[2 * i] - pSrc[2 * l];
+
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+            p0 = xt * cosVal;
+            p1 = yt * sinVal;
+            p2 = yt * cosVal;
+            p3 = xt * sinVal;
+
+            pSrc[2 * i] = a0;
+            pSrc[2 * i + 1] = a1;
+
+            pSrc[2 * l]     = p0 - p1;
+            pSrc[2 * l + 1] = p2 + p3;
+
+            i += n1;
+         } while ( i < fftLen );                 // butterfly loop end
+         j++;
+      } while (j < n2);                      // groups loop end
+
+      twidCoefModifier <<= 1U;
+   }                             // stages loop end
+
+   // loop for butterfly
+   for (i = 0; i < fftLen; i += 2)
+   {
+      a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+      xt = pSrc[2 * i] - pSrc[2 * i + 2];
+
+      a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+      yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+
+      p0 = a0 * onebyfftLen;
+      p2 = xt * onebyfftLen;
+      p1 = a1 * onebyfftLen;
+      p3 = yt * onebyfftLen;
+
+      pSrc[2 * i] = p0;
+      pSrc[2 * i + 1] = p1;
+      pSrc[2 * i + 2] = p2;
+      pSrc[2 * i + 3] = p3;
+   }                             // butterfly loop end
+
+#else
+
+   n2 = fftLen;
+
+   // loop for stage
+   for (k = fftLen; k > 2; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups
+      j = 0;
+      do
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia = ia + twidCoefModifier;
+
+         // loop for butterfly
+         i = j;
+         do
+         {
+            l = i + n2;
+            a0 = pSrc[2 * i] + pSrc[2 * l];
+            xt = pSrc[2 * i] - pSrc[2 * l];
+
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+            p0 = xt * cosVal;
+            p1 = yt * sinVal;
+            p2 = yt * cosVal;
+            p3 = xt * sinVal;
+
+            pSrc[2 * i] = a0;
+            pSrc[2 * i + 1] = a1;
+
+            pSrc[2 * l]     = p0 - p1;
+            pSrc[2 * l + 1] = p2 + p3;
+
+            i += n1;
+         } while ( i < fftLen );                    // butterfly loop end
+         j++;
+      } while ( j < n2 );                      // groups loop end
+
+      twidCoefModifier = twidCoefModifier << 1U;
+   }                             // stages loop end
+
+   n1 = n2;
+   n2 = n2 >> 1;
+
+   // loop for butterfly
+   for (i = 0; i < fftLen; i += n1)
+   {
+      l = i + n2;
+
+      a0 = pSrc[2 * i] + pSrc[2 * l];
+      xt = pSrc[2 * i] - pSrc[2 * l];
+
+      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+
+      p0 = a0 * onebyfftLen;
+      p2 = xt * onebyfftLen;
+      p1 = a1 * onebyfftLen;
+      p3 = yt * onebyfftLen;
+
+      pSrc[2 * i] = p0;
+      pSrc[2U * l] = p2;
+
+      pSrc[2 * i + 1] = p1;
+      pSrc[2U * l + 1U] = p3;
+   }                             // butterfly loop end
+
+#endif //      #if defined (ARM_MATH_DSP)
+
+}
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
new file mode 100644
index 0000000..0f423eb
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix2_init_f32.c
+ * Description:  Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief  Initialization function for the floating-point CFFT/CIFFT.
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in]     fftLen         length of the FFT.
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (float32_t *) twiddleCoef;
+
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+
+  case 4096U:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.000244140625;
+    break;
+
+  case 2048U:
+    /*  Initializations of structure parameters for 2048 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 2U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 2U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.00048828125;
+    break;
+
+  case 1024U:
+    /*  Initializations of structure parameters for 1024 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.0009765625f;
+    break;
+
+  case 512U:
+    /*  Initializations of structure parameters for 512 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 8U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 8U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.001953125;
+    break;
+
+  case 256U:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16U;
+    S->bitRevFactor = 16U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    S->onebyfftLen = 0.00390625f;
+    break;
+
+  case 128U:
+    /*  Initializations of structure parameters for 128 point FFT */
+    S->twidCoefModifier = 32U;
+    S->bitRevFactor = 32U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+    S->onebyfftLen = 0.0078125;
+    break;
+
+  case 64U:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64U;
+    S->bitRevFactor = 64U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    S->onebyfftLen = 0.015625f;
+    break;
+
+  case 32U:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 128U;
+    S->bitRevFactor = 128U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+    S->onebyfftLen = 0.03125;
+    break;
+
+  case 16U:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256U;
+    S->bitRevFactor = 256U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    S->onebyfftLen = 0.0625f;
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
new file mode 100644
index 0000000..54f4e84
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix2_init_q15.c
+ * Description:  Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the Q15 CFFT/CIFFT.
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
+* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
+* @param[in]     fftLen         length of the FFT.
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q15_t *) twiddleCoef_4096_q15;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+  case 4096U:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+    break;
+
+  case 2048U:
+    /*  Initializations of structure parameters for 2048 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 2U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 2U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+
+    break;
+
+  case 1024U:
+    /*  Initializations of structure parameters for 1024 point FFT */
+    S->twidCoefModifier = 4U;
+    S->bitRevFactor = 4U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+    break;
+
+  case 512U:
+    /*  Initializations of structure parameters for 512 point FFT */
+    S->twidCoefModifier = 8U;
+    S->bitRevFactor = 8U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+
+    break;
+
+  case 256U:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16U;
+    S->bitRevFactor = 16U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+    break;
+
+  case 128U:
+    /*  Initializations of structure parameters for 128 point FFT */
+    S->twidCoefModifier = 32U;
+    S->bitRevFactor = 32U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+
+    break;
+
+  case 64U:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64U;
+    S->bitRevFactor = 64U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+    break;
+
+  case 32U:
+    /*  Initializations of structure parameters for 32 point FFT */
+    S->twidCoefModifier = 128U;
+    S->bitRevFactor = 128U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+
+    break;
+
+  case 16U:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256U;
+    S->bitRevFactor = 256U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
new file mode 100644
index 0000000..41ad965
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
@@ -0,0 +1,174 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix2_init_q31.c
+ * Description:  Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+*
+* @brief  Initialization function for the Q31 CFFT/CIFFT.
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
+* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.
+* @param[in]     fftLen         length of the FFT.
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q31_t *) twiddleCoef_4096_q31;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of Instance structure depending on the FFT length */
+  switch (S->fftLen)
+  {
+    /*  Initializations of structure parameters for 4096 point FFT */
+  case 4096U:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    break;
+
+    /*  Initializations of structure parameters for 2048 point FFT */
+  case 2048U:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 2U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 2U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+    break;
+
+    /*  Initializations of structure parameters for 1024 point FFT */
+  case 1024U:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    break;
+
+    /*  Initializations of structure parameters for 512 point FFT */
+  case 512U:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 8U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 8U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+    break;
+
+  case 256U:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16U;
+    S->bitRevFactor = 16U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    break;
+
+  case 128U:
+    /*  Initializations of structure parameters for 128 point FFT */
+    S->twidCoefModifier = 32U;
+    S->bitRevFactor = 32U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+    break;
+
+  case 64U:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64U;
+    S->bitRevFactor = 64U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    break;
+
+  case 32U:
+    /*  Initializations of structure parameters for 32 point FFT */
+    S->twidCoefModifier = 128U;
+    S->bitRevFactor = 128U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+    break;
+
+  case 16U:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256U;
+    S->bitRevFactor = 256U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c
new file mode 100644
index 0000000..c7a9bdf
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c
@@ -0,0 +1,729 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix2_q15.c
+ * Description:  Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier);
+
+void arm_bitreversal_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Processing function for the fixed-point CFFT/CIFFT.
+ * @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
+ * @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+ * @return none.
+ */
+
+void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc)
+{
+
+  if (S->ifftFlag == 1U)
+  {
+    arm_radix2_butterfly_inverse_q15(pSrc, S->fftLen,
+                                     S->pTwiddle, S->twidCoefModifier);
+  }
+  else
+  {
+    arm_radix2_butterfly_q15(pSrc, S->fftLen,
+                             S->pTwiddle, S->twidCoefModifier);
+  }
+
+  arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+void arm_radix2_butterfly_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+#if defined (ARM_MATH_DSP)
+
+  unsigned i, j, k, l;
+  unsigned n1, n2, ia;
+  q15_t in;
+  q31_t T, S, R;
+  q31_t coeff, out1, out2;
+
+  //N = fftLen;
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups
+  for (i = 0; i < n2; i++)
+  {
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2U));
+
+    ia = ia + twidCoefModifier;
+
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 1;
+    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 1;
+    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUAD(coeff, R) >> 16;
+    out2 = __SMUSDX(coeff, R);
+
+#else
+
+    out1 = __SMUSDX(R, coeff) >> 16U;
+    out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2U * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2U));
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly
+    i++;
+    l++;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 1;
+    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 1;
+    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUAD(coeff, R) >> 16;
+    out2 = __SMUSDX(coeff, R);
+
+#else
+
+    out1 = __SMUSDX(R, coeff) >> 16U;
+    out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2U * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+  }                             // groups loop end
+
+  twidCoefModifier = twidCoefModifier << 1U;
+
+  // loop for stage
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups
+    for (j = 0; j < n2; j++)
+    {
+      coeff = _SIMD32_OFFSET(pCoef + (ia * 2U));
+
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(coeff, R) >> 16;
+        out2 = __SMUSDX(coeff, R);
+
+#else
+
+        out1 = __SMUSDX(R, coeff) >> 16U;
+        out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2U * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        i += n1;
+
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(coeff, R) >> 16;
+        out2 = __SMUSDX(coeff, R);
+
+#else
+
+        out1 = __SMUSDX(R, coeff) >> 16U;
+        out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2U * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+      }                         // butterfly loop end
+
+    }                           // groups loop end
+
+    twidCoefModifier = twidCoefModifier << 1U;
+  }                             // stages loop end
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  coeff = _SIMD32_OFFSET(pCoef + (ia * 2U));
+
+  ia = ia + twidCoefModifier;
+
+  // loop for butterfly
+  for (i = 0; i < fftLen; i += n1)
+  {
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2U * l)) = R;
+
+    i += n1;
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2U * l)) = R;
+
+  }                             // groups loop end
+
+
+#else
+
+  unsigned i, j, k, l;
+  unsigned n1, n2, ia;
+  q15_t xt, yt, cosVal, sinVal;
+
+
+  //N = fftLen;
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups
+  for (j = 0; j < n2; j++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+      xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U);
+      pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U;
+
+      yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U);
+      pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U;
+
+      pSrc[2U * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+      pSrc[2U * l + 1U] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+    }                           // butterfly loop end
+
+  }                             // groups loop end
+
+  twidCoefModifier = twidCoefModifier << 1U;
+
+  // loop for stage
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U;
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U;
+
+        pSrc[2U * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+        pSrc[2U * l + 1U] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+      }                         // butterfly loop end
+
+    }                           // groups loop end
+
+    twidCoefModifier = twidCoefModifier << 1U;
+  }                             // stages loop end
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups
+  for (j = 0; j < n2; j++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+      pSrc[2U * l] = xt;
+
+      pSrc[2U * l + 1U] = yt;
+
+    }                           // butterfly loop end
+
+  }                             // groups loop end
+
+  twidCoefModifier = twidCoefModifier << 1U;
+
+#endif //             #if defined (ARM_MATH_DSP)
+
+}
+
+
+void arm_radix2_butterfly_inverse_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+#if defined (ARM_MATH_DSP)
+
+  unsigned i, j, k, l;
+  unsigned n1, n2, ia;
+  q15_t in;
+  q31_t T, S, R;
+  q31_t coeff, out1, out2;
+
+  //N = fftLen;
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups
+  for (i = 0; i < n2; i++)
+  {
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2U));
+
+    ia = ia + twidCoefModifier;
+
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 1;
+    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 1;
+    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUSD(coeff, R) >> 16;
+    out2 = __SMUADX(coeff, R);
+#else
+
+    out1 = __SMUADX(R, coeff) >> 16U;
+    out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2U * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2U));
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly
+    i++;
+    l++;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 1;
+    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 1;
+    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUSD(coeff, R) >> 16;
+    out2 = __SMUADX(coeff, R);
+#else
+
+    out1 = __SMUADX(R, coeff) >> 16U;
+    out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2U * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+  }                             // groups loop end
+
+  twidCoefModifier = twidCoefModifier << 1U;
+
+  // loop for stage
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups
+    for (j = 0; j < n2; j++)
+    {
+      coeff = _SIMD32_OFFSET(pCoef + (ia * 2U));
+
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(coeff, R) >> 16;
+        out2 = __SMUADX(coeff, R);
+
+#else
+
+        out1 = __SMUADX(R, coeff) >> 16U;
+        out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2U * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        i += n1;
+
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(coeff, R) >> 16;
+        out2 = __SMUADX(coeff, R);
+#else
+
+        out1 = __SMUADX(R, coeff) >> 16U;
+        out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2U * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+      }                         // butterfly loop end
+
+    }                           // groups loop end
+
+    twidCoefModifier = twidCoefModifier << 1U;
+  }                             // stages loop end
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups
+  for (j = 0; j < n2; j++)
+  {
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2U));
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+
+      T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+      S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+      R = __QSUB16(T, S);
+
+      _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+      _SIMD32_OFFSET(pSrc + (2U * l)) = R;
+
+    }                           // butterfly loop end
+
+  }                             // groups loop end
+
+  twidCoefModifier = twidCoefModifier << 1U;
+
+#else
+
+
+  unsigned i, j, k, l;
+  unsigned n1, n2, ia;
+  q15_t xt, yt, cosVal, sinVal;
+
+  //N = fftLen;
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups
+  for (j = 0; j < n2; j++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+      xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U);
+      pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U;
+
+      yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U);
+      pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U;
+
+      pSrc[2U * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+      pSrc[2U * l + 1U] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+    }                           // butterfly loop end
+
+  }                             // groups loop end
+
+  twidCoefModifier = twidCoefModifier << 1U;
+
+  // loop for stage
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U;
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U;
+
+        pSrc[2U * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+        pSrc[2U * l + 1U] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+      }                         // butterfly loop end
+
+    }                           // groups loop end
+
+    twidCoefModifier = twidCoefModifier << 1U;
+  }                             // stages loop end
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  cosVal = pCoef[ia * 2];
+  sinVal = pCoef[(ia * 2) + 1];
+
+  ia = ia + twidCoefModifier;
+
+  // loop for butterfly
+  for (i = 0; i < fftLen; i += n1)
+  {
+    l = i + n2;
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+    pSrc[2U * l] = xt;
+
+    pSrc[2U * l + 1U] = yt;
+
+  }                             // groups loop end
+
+
+#endif //             #if defined (ARM_MATH_DSP)
+
+}
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c
new file mode 100644
index 0000000..e69400c
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c
@@ -0,0 +1,338 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix2_q31.c
+ * Description:  Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint16_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the fixed-point CFFT/CIFFT.
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
+* @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix2_q31(
+const arm_cfft_radix2_instance_q31 * S,
+q31_t * pSrc)
+{
+
+   if (S->ifftFlag == 1U)
+   {
+      arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen,
+      S->pTwiddle, S->twidCoefModifier);
+   }
+   else
+   {
+      arm_radix2_butterfly_q31(pSrc, S->fftLen,
+      S->pTwiddle, S->twidCoefModifier);
+   }
+
+   arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
+void arm_radix2_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+   unsigned i, j, k, l, m;
+   unsigned n1, n2, ia;
+   q31_t xt, yt, cosVal, sinVal;
+   q31_t p0, p1;
+
+   //N = fftLen;
+   n2 = fftLen;
+
+   n1 = n2;
+   n2 = n2 >> 1;
+   ia = 0;
+
+   // loop for groups
+   for (i = 0; i < n2; i++)
+   {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      l = i + n2;
+      xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U);
+      pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U;
+
+      yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U);
+      pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U;
+
+      mult_32x32_keep32_R(p0, xt, cosVal);
+      mult_32x32_keep32_R(p1, yt, cosVal);
+      multAcc_32x32_keep32_R(p0, yt, sinVal);
+      multSub_32x32_keep32_R(p1, xt, sinVal);
+
+      pSrc[2U * l] = p0;
+      pSrc[2U * l + 1U] = p1;
+
+   }                             // groups loop end
+
+   twidCoefModifier <<= 1U;
+
+   // loop for stage
+   for (k = fftLen / 2; k > 2; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups
+      for (j = 0; j < n2; j++)
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia = ia + twidCoefModifier;
+
+         // loop for butterfly
+         i = j;
+         m = fftLen / n1;
+         do
+         {
+            l = i + n2;
+            xt = pSrc[2 * i] - pSrc[2 * l];
+            pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U;
+
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U;
+
+            mult_32x32_keep32_R(p0, xt, cosVal);
+            mult_32x32_keep32_R(p1, yt, cosVal);
+            multAcc_32x32_keep32_R(p0, yt, sinVal);
+            multSub_32x32_keep32_R(p1, xt, sinVal);
+
+            pSrc[2U * l] = p0;
+            pSrc[2U * l + 1U] = p1;
+            i += n1;
+            m--;
+         } while ( m > 0);                   // butterfly loop end
+
+      }                           // groups loop end
+
+      twidCoefModifier <<= 1U;
+   }                             // stages loop end
+
+   n1 = n2;
+   n2 = n2 >> 1;
+   ia = 0;
+
+   cosVal = pCoef[ia * 2];
+   sinVal = pCoef[(ia * 2) + 1];
+   ia = ia + twidCoefModifier;
+
+   // loop for butterfly
+   for (i = 0; i < fftLen; i += n1)
+   {
+      l = i + n2;
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+      pSrc[2U * l] = xt;
+
+      pSrc[2U * l + 1U] = yt;
+
+      i += n1;
+      l = i + n2;
+
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+      pSrc[2U * l] = xt;
+
+      pSrc[2U * l + 1U] = yt;
+
+   }                             // butterfly loop end
+
+}
+
+
+void arm_radix2_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+   unsigned i, j, k, l;
+   unsigned n1, n2, ia;
+   q31_t xt, yt, cosVal, sinVal;
+   q31_t p0, p1;
+
+   //N = fftLen;
+   n2 = fftLen;
+
+   n1 = n2;
+   n2 = n2 >> 1;
+   ia = 0;
+
+   // loop for groups
+   for (i = 0; i < n2; i++)
+   {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      l = i + n2;
+      xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U);
+      pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U;
+
+      yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U);
+      pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U;
+
+      mult_32x32_keep32_R(p0, xt, cosVal);
+      mult_32x32_keep32_R(p1, yt, cosVal);
+      multSub_32x32_keep32_R(p0, yt, sinVal);
+      multAcc_32x32_keep32_R(p1, xt, sinVal);
+
+      pSrc[2U * l] = p0;
+      pSrc[2U * l + 1U] = p1;
+   }                             // groups loop end
+
+   twidCoefModifier = twidCoefModifier << 1U;
+
+   // loop for stage
+   for (k = fftLen / 2; k > 2; k = k >> 1)
+   {
+      n1 = n2;
+      n2 = n2 >> 1;
+      ia = 0;
+
+      // loop for groups
+      for (j = 0; j < n2; j++)
+      {
+         cosVal = pCoef[ia * 2];
+         sinVal = pCoef[(ia * 2) + 1];
+         ia = ia + twidCoefModifier;
+
+         // loop for butterfly
+         for (i = j; i < fftLen; i += n1)
+         {
+            l = i + n2;
+            xt = pSrc[2 * i] - pSrc[2 * l];
+            pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U;
+
+            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+            pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U;
+
+            mult_32x32_keep32_R(p0, xt, cosVal);
+            mult_32x32_keep32_R(p1, yt, cosVal);
+            multSub_32x32_keep32_R(p0, yt, sinVal);
+            multAcc_32x32_keep32_R(p1, xt, sinVal);
+
+            pSrc[2U * l] = p0;
+            pSrc[2U * l + 1U] = p1;
+         }                         // butterfly loop end
+
+      }                           // groups loop end
+
+      twidCoefModifier = twidCoefModifier << 1U;
+   }                             // stages loop end
+
+   n1 = n2;
+   n2 = n2 >> 1;
+   ia = 0;
+
+   cosVal = pCoef[ia * 2];
+   sinVal = pCoef[(ia * 2) + 1];
+   ia = ia + twidCoefModifier;
+
+   // loop for butterfly
+   for (i = 0; i < fftLen; i += n1)
+   {
+      l = i + n2;
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+      pSrc[2U * l] = xt;
+
+      pSrc[2U * l + 1U] = yt;
+
+      i += n1;
+      l = i + n2;
+
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+      pSrc[2U * l] = xt;
+
+      pSrc[2U * l + 1U] = yt;
+
+   }                             // butterfly loop end
+
+}
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c
new file mode 100644
index 0000000..dbbcca7
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c
@@ -0,0 +1,1209 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix4_f32.c
+ * Description:  Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+extern void arm_bitreversal_f32(
+float32_t * pSrc,
+uint16_t fftSize,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+void arm_radix4_butterfly_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier);
+
+void arm_radix4_butterfly_inverse_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier,
+float32_t onebyfftLen);
+
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in]      *S    points to an instance of the floating-point Radix-4 CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc)
+{
+   if (S->ifftFlag == 1U)
+   {
+      /*  Complex IFFT radix-4  */
+      arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen);
+   }
+   else
+   {
+      /*  Complex FFT radix-4  */
+      arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier);
+   }
+
+   if (S->bitReverseFlag == 1U)
+   {
+      /*  Bit Reversal */
+      arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+   }
+
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
+/* ----------------------------------------------------------------------
+ * Internal helper function used by the FFTs
+ * ---------------------------------------------------------------------- */
+
+/*
+* @brief  Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+* @param[in]      fftLen           length of the FFT.
+* @param[in]      *pCoef           points to the twiddle coefficient buffer.
+* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix4_butterfly_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+   float32_t co1, co2, co3, si1, si2, si3;
+   uint32_t ia1, ia2, ia3;
+   uint32_t i0, i1, i2, i3;
+   uint32_t n1, n2, j, k;
+
+#if defined (ARM_MATH_DSP)
+
+   /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+   float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+   float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+   Ybminusd;
+   float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+   float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+   float32_t *ptr1;
+   float32_t p0,p1,p2,p3,p4,p5;
+   float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+   /*  Initializations for the first stage */
+   n2 = fftLen;
+   n1 = n2;
+
+   /* n2 = fftLen/4 */
+   n2 >>= 2U;
+   i0 = 0U;
+   ia1 = 0U;
+
+   j = n2;
+
+   /*  Calculation of first stage */
+   do
+   {
+      /*  index calculation for the input as, */
+      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+      i1 = i0 + n2;
+      i2 = i1 + n2;
+      i3 = i2 + n2;
+
+      xaIn = pSrc[(2U * i0)];
+      yaIn = pSrc[(2U * i0) + 1U];
+
+      xbIn = pSrc[(2U * i1)];
+      ybIn = pSrc[(2U * i1) + 1U];
+
+      xcIn = pSrc[(2U * i2)];
+      ycIn = pSrc[(2U * i2) + 1U];
+
+      xdIn = pSrc[(2U * i3)];
+      ydIn = pSrc[(2U * i3) + 1U];
+
+      /* xa + xc */
+      Xaplusc = xaIn + xcIn;
+      /* xb + xd */
+      Xbplusd = xbIn + xdIn;
+      /* ya + yc */
+      Yaplusc = yaIn + ycIn;
+      /* yb + yd */
+      Ybplusd = ybIn + ydIn;
+
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      co2 = pCoef[ia2 * 2U];
+      si2 = pCoef[(ia2 * 2U) + 1U];
+
+      /* xa - xc */
+      Xaminusc = xaIn - xcIn;
+      /* xb - xd */
+      Xbminusd = xbIn - xdIn;
+      /* ya - yc */
+      Yaminusc = yaIn - ycIn;
+      /* yb - yd */
+      Ybminusd = ybIn - ydIn;
+
+      /* xa' = xa + xb + xc + xd */
+      pSrc[(2U * i0)] = Xaplusc + Xbplusd;
+      /* ya' = ya + yb + yc + yd */
+      pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd;
+
+      /* (xa - xc) + (yb - yd) */
+      Xb12C_out = (Xaminusc + Ybminusd);
+      /* (ya - yc) + (xb - xd) */
+      Yb12C_out = (Yaminusc - Xbminusd);
+      /* (xa + xc) - (xb + xd) */
+      Xc12C_out = (Xaplusc - Xbplusd);
+      /* (ya + yc) - (yb + yd) */
+      Yc12C_out = (Yaplusc - Ybplusd);
+      /* (xa - xc) - (yb - yd) */
+      Xd12C_out = (Xaminusc - Ybminusd);
+      /* (ya - yc) + (xb - xd) */
+      Yd12C_out = (Xbminusd + Yaminusc);
+
+      co1 = pCoef[ia1 * 2U];
+      si1 = pCoef[(ia1 * 2U) + 1U];
+
+      /*  index calculation for the coefficients */
+      ia3 = ia2 + ia1;
+      co3 = pCoef[ia3 * 2U];
+      si3 = pCoef[(ia3 * 2U) + 1U];
+
+      Xb12_out = Xb12C_out * co1;
+      Yb12_out = Yb12C_out * co1;
+      Xc12_out = Xc12C_out * co2;
+      Yc12_out = Yc12C_out * co2;
+      Xd12_out = Xd12C_out * co3;
+      Yd12_out = Yd12C_out * co3;
+
+      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+      //Xb12_out -= Yb12C_out * si1;
+      p0 = Yb12C_out * si1;
+      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+      //Yb12_out += Xb12C_out * si1;
+      p1 = Xb12C_out * si1;
+      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+      //Xc12_out -= Yc12C_out * si2;
+      p2 = Yc12C_out * si2;
+      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+      //Yc12_out += Xc12C_out * si2;
+      p3 = Xc12C_out * si2;
+      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+      //Xd12_out -= Yd12C_out * si3;
+      p4 = Yd12C_out * si3;
+      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+      //Yd12_out += Xd12C_out * si3;
+      p5 = Xd12C_out * si3;
+
+      Xb12_out += p0;
+      Yb12_out -= p1;
+      Xc12_out += p2;
+      Yc12_out -= p3;
+      Xd12_out += p4;
+      Yd12_out -= p5;
+
+      /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+      pSrc[2U * i1] = Xc12_out;
+
+      /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+      pSrc[(2U * i1) + 1U] = Yc12_out;
+
+      /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+      pSrc[2U * i2] = Xb12_out;
+
+      /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+      pSrc[(2U * i2) + 1U] = Yb12_out;
+
+      /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+      pSrc[2U * i3] = Xd12_out;
+
+      /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+      pSrc[(2U * i3) + 1U] = Yd12_out;
+
+      /*  Twiddle coefficients index modifier */
+      ia1 += twidCoefModifier;
+
+      /*  Updating input index */
+      i0++;
+
+   }
+   while (--j);
+
+   twidCoefModifier <<= 2U;
+
+   /*  Calculation of second stage to excluding last stage */
+   for (k = fftLen >> 2U; k > 4U; k >>= 2U)
+   {
+      /*  Initializations for the first stage */
+      n1 = n2;
+      n2 >>= 2U;
+      ia1 = 0U;
+
+      /*  Calculation of first stage */
+      j = 0;
+      do
+      {
+         /*  index calculation for the coefficients */
+         ia2 = ia1 + ia1;
+         ia3 = ia2 + ia1;
+         co1 = pCoef[ia1 * 2U];
+         si1 = pCoef[(ia1 * 2U) + 1U];
+         co2 = pCoef[ia2 * 2U];
+         si2 = pCoef[(ia2 * 2U) + 1U];
+         co3 = pCoef[ia3 * 2U];
+         si3 = pCoef[(ia3 * 2U) + 1U];
+
+         /*  Twiddle coefficients index modifier */
+         ia1 += twidCoefModifier;
+
+         i0 = j;
+         do
+         {
+            /*  index calculation for the input as, */
+            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+            i1 = i0 + n2;
+            i2 = i1 + n2;
+            i3 = i2 + n2;
+
+            xaIn = pSrc[(2U * i0)];
+            yaIn = pSrc[(2U * i0) + 1U];
+
+            xbIn = pSrc[(2U * i1)];
+            ybIn = pSrc[(2U * i1) + 1U];
+
+            xcIn = pSrc[(2U * i2)];
+            ycIn = pSrc[(2U * i2) + 1U];
+
+            xdIn = pSrc[(2U * i3)];
+            ydIn = pSrc[(2U * i3) + 1U];
+
+            /* xa - xc */
+            Xaminusc = xaIn - xcIn;
+            /* (xb - xd) */
+            Xbminusd = xbIn - xdIn;
+            /* ya - yc */
+            Yaminusc = yaIn - ycIn;
+            /* (yb - yd) */
+            Ybminusd = ybIn - ydIn;
+
+            /* xa + xc */
+            Xaplusc = xaIn + xcIn;
+            /* xb + xd */
+            Xbplusd = xbIn + xdIn;
+            /* ya + yc */
+            Yaplusc = yaIn + ycIn;
+            /* yb + yd */
+            Ybplusd = ybIn + ydIn;
+
+            /* (xa - xc) + (yb - yd) */
+            Xb12C_out = (Xaminusc + Ybminusd);
+            /* (ya - yc) -  (xb - xd) */
+            Yb12C_out = (Yaminusc - Xbminusd);
+            /* xa + xc -(xb + xd) */
+            Xc12C_out = (Xaplusc - Xbplusd);
+            /* (ya + yc) - (yb + yd) */
+            Yc12C_out = (Yaplusc - Ybplusd);
+            /* (xa - xc) - (yb - yd) */
+            Xd12C_out = (Xaminusc - Ybminusd);
+            /* (ya - yc) +  (xb - xd) */
+            Yd12C_out = (Xbminusd + Yaminusc);
+
+            pSrc[(2U * i0)] = Xaplusc + Xbplusd;
+            pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd;
+
+            Xb12_out = Xb12C_out * co1;
+            Yb12_out = Yb12C_out * co1;
+            Xc12_out = Xc12C_out * co2;
+            Yc12_out = Yc12C_out * co2;
+            Xd12_out = Xd12C_out * co3;
+            Yd12_out = Yd12C_out * co3;
+
+            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+            //Xb12_out -= Yb12C_out * si1;
+            p0 = Yb12C_out * si1;
+            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+            //Yb12_out += Xb12C_out * si1;
+            p1 = Xb12C_out * si1;
+            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+            //Xc12_out -= Yc12C_out * si2;
+            p2 = Yc12C_out * si2;
+            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+            //Yc12_out += Xc12C_out * si2;
+            p3 = Xc12C_out * si2;
+            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+            //Xd12_out -= Yd12C_out * si3;
+            p4 = Yd12C_out * si3;
+            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+            //Yd12_out += Xd12C_out * si3;
+            p5 = Xd12C_out * si3;
+
+            Xb12_out += p0;
+            Yb12_out -= p1;
+            Xc12_out += p2;
+            Yc12_out -= p3;
+            Xd12_out += p4;
+            Yd12_out -= p5;
+
+            /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+            pSrc[2U * i1] = Xc12_out;
+
+            /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+            pSrc[(2U * i1) + 1U] = Yc12_out;
+
+            /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+            pSrc[2U * i2] = Xb12_out;
+
+            /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+            pSrc[(2U * i2) + 1U] = Yb12_out;
+
+            /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+            pSrc[2U * i3] = Xd12_out;
+
+            /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+            pSrc[(2U * i3) + 1U] = Yd12_out;
+
+            i0 += n1;
+         } while (i0 < fftLen);
+         j++;
+      } while (j <= (n2 - 1U));
+      twidCoefModifier <<= 2U;
+   }
+
+   j = fftLen >> 2;
+   ptr1 = &pSrc[0];
+
+   /*  Calculations of last stage */
+   do
+   {
+      xaIn = ptr1[0];
+      yaIn = ptr1[1];
+      xbIn = ptr1[2];
+      ybIn = ptr1[3];
+      xcIn = ptr1[4];
+      ycIn = ptr1[5];
+      xdIn = ptr1[6];
+      ydIn = ptr1[7];
+
+      /* xa + xc */
+      Xaplusc = xaIn + xcIn;
+
+      /* xa - xc */
+      Xaminusc = xaIn - xcIn;
+
+      /* ya + yc */
+      Yaplusc = yaIn + ycIn;
+
+      /* ya - yc */
+      Yaminusc = yaIn - ycIn;
+
+      /* xb + xd */
+      Xbplusd = xbIn + xdIn;
+
+      /* yb + yd */
+      Ybplusd = ybIn + ydIn;
+
+      /* (xb-xd) */
+      Xbminusd = xbIn - xdIn;
+
+      /* (yb-yd) */
+      Ybminusd = ybIn - ydIn;
+
+      /* xa' = xa + xb + xc + xd */
+      a0 = (Xaplusc + Xbplusd);
+      /* ya' = ya + yb + yc + yd */
+      a1 = (Yaplusc + Ybplusd);
+      /* xc' = (xa-xb+xc-xd) */
+      a2 = (Xaplusc - Xbplusd);
+      /* yc' = (ya-yb+yc-yd) */
+      a3 = (Yaplusc - Ybplusd);
+      /* xb' = (xa+yb-xc-yd) */
+      a4 = (Xaminusc + Ybminusd);
+      /* yb' = (ya-xb-yc+xd) */
+      a5 = (Yaminusc - Xbminusd);
+      /* xd' = (xa-yb-xc+yd)) */
+      a6 = (Xaminusc - Ybminusd);
+      /* yd' = (ya+xb-yc-xd) */
+      a7 = (Xbminusd + Yaminusc);
+
+      ptr1[0] = a0;
+      ptr1[1] = a1;
+      ptr1[2] = a2;
+      ptr1[3] = a3;
+      ptr1[4] = a4;
+      ptr1[5] = a5;
+      ptr1[6] = a6;
+      ptr1[7] = a7;
+
+      /* increment pointer by 8 */
+      ptr1 += 8U;
+   } while (--j);
+
+#else
+
+   float32_t t1, t2, r1, r2, s1, s2;
+
+   /* Run the below code for Cortex-M0 */
+
+   /*  Initializations for the fft calculation */
+   n2 = fftLen;
+   n1 = n2;
+   for (k = fftLen; k > 1U; k >>= 2U)
+   {
+      /*  Initializations for the fft calculation */
+      n1 = n2;
+      n2 >>= 2U;
+      ia1 = 0U;
+
+      /*  FFT Calculation */
+      j = 0;
+      do
+      {
+         /*  index calculation for the coefficients */
+         ia2 = ia1 + ia1;
+         ia3 = ia2 + ia1;
+         co1 = pCoef[ia1 * 2U];
+         si1 = pCoef[(ia1 * 2U) + 1U];
+         co2 = pCoef[ia2 * 2U];
+         si2 = pCoef[(ia2 * 2U) + 1U];
+         co3 = pCoef[ia3 * 2U];
+         si3 = pCoef[(ia3 * 2U) + 1U];
+
+         /*  Twiddle coefficients index modifier */
+         ia1 = ia1 + twidCoefModifier;
+
+         i0 = j;
+         do
+         {
+            /*  index calculation for the input as, */
+            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+            i1 = i0 + n2;
+            i2 = i1 + n2;
+            i3 = i2 + n2;
+
+            /* xa + xc */
+            r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)];
+
+            /* xa - xc */
+            r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)];
+
+            /* ya + yc */
+            s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U];
+
+            /* ya - yc */
+            s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U];
+
+            /* xb + xd */
+            t1 = pSrc[2U * i1] + pSrc[2U * i3];
+
+            /* xa' = xa + xb + xc + xd */
+            pSrc[2U * i0] = r1 + t1;
+
+            /* xa + xc -(xb + xd) */
+            r1 = r1 - t1;
+
+            /* yb + yd */
+            t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U];
+
+            /* ya' = ya + yb + yc + yd */
+            pSrc[(2U * i0) + 1U] = s1 + t2;
+
+            /* (ya + yc) - (yb + yd) */
+            s1 = s1 - t2;
+
+            /* (yb - yd) */
+            t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U];
+
+            /* (xb - xd) */
+            t2 = pSrc[2U * i1] - pSrc[2U * i3];
+
+            /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+            pSrc[2U * i1] = (r1 * co2) + (s1 * si2);
+
+            /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+            pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2);
+
+            /* (xa - xc) + (yb - yd) */
+            r1 = r2 + t1;
+
+            /* (xa - xc) - (yb - yd) */
+            r2 = r2 - t1;
+
+            /* (ya - yc) -  (xb - xd) */
+            s1 = s2 - t2;
+
+            /* (ya - yc) +  (xb - xd) */
+            s2 = s2 + t2;
+
+            /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+            pSrc[2U * i2] = (r1 * co1) + (s1 * si1);
+
+            /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+            pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1);
+
+            /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+            pSrc[2U * i3] = (r2 * co3) + (s2 * si3);
+
+            /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+            pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3);
+
+            i0 += n1;
+         } while ( i0 < fftLen);
+         j++;
+      } while (j <= (n2 - 1U));
+      twidCoefModifier <<= 2U;
+   }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/*
+* @brief  Core function for the floating-point CIFFT butterfly process.
+* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+* @param[in]      fftLen           length of the FFT.
+* @param[in]      *pCoef           points to twiddle coefficient buffer.
+* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @param[in]      onebyfftLen      value of 1/fftLen.
+* @return none.
+*/
+
+void arm_radix4_butterfly_inverse_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier,
+float32_t onebyfftLen)
+{
+   float32_t co1, co2, co3, si1, si2, si3;
+   uint32_t ia1, ia2, ia3;
+   uint32_t i0, i1, i2, i3;
+   uint32_t n1, n2, j, k;
+
+#if defined (ARM_MATH_DSP)
+
+   float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+   float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+   Ybminusd;
+   float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+   float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+   float32_t *ptr1;
+   float32_t p0,p1,p2,p3,p4,p5,p6,p7;
+   float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+
+   /*  Initializations for the first stage */
+   n2 = fftLen;
+   n1 = n2;
+
+   /* n2 = fftLen/4 */
+   n2 >>= 2U;
+   i0 = 0U;
+   ia1 = 0U;
+
+   j = n2;
+
+   /*  Calculation of first stage */
+   do
+   {
+      /*  index calculation for the input as, */
+      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+      i1 = i0 + n2;
+      i2 = i1 + n2;
+      i3 = i2 + n2;
+
+      /*  Butterfly implementation */
+      xaIn = pSrc[(2U * i0)];
+      yaIn = pSrc[(2U * i0) + 1U];
+
+      xcIn = pSrc[(2U * i2)];
+      ycIn = pSrc[(2U * i2) + 1U];
+
+      xbIn = pSrc[(2U * i1)];
+      ybIn = pSrc[(2U * i1) + 1U];
+
+      xdIn = pSrc[(2U * i3)];
+      ydIn = pSrc[(2U * i3) + 1U];
+
+      /* xa + xc */
+      Xaplusc = xaIn + xcIn;
+      /* xb + xd */
+      Xbplusd = xbIn + xdIn;
+      /* ya + yc */
+      Yaplusc = yaIn + ycIn;
+      /* yb + yd */
+      Ybplusd = ybIn + ydIn;
+
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      co2 = pCoef[ia2 * 2U];
+      si2 = pCoef[(ia2 * 2U) + 1U];
+
+      /* xa - xc */
+      Xaminusc = xaIn - xcIn;
+      /* xb - xd */
+      Xbminusd = xbIn - xdIn;
+      /* ya - yc */
+      Yaminusc = yaIn - ycIn;
+      /* yb - yd */
+      Ybminusd = ybIn - ydIn;
+
+      /* xa' = xa + xb + xc + xd */
+      pSrc[(2U * i0)] = Xaplusc + Xbplusd;
+
+      /* ya' = ya + yb + yc + yd */
+      pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd;
+
+      /* (xa - xc) - (yb - yd) */
+      Xb12C_out = (Xaminusc - Ybminusd);
+      /* (ya - yc) + (xb - xd) */
+      Yb12C_out = (Yaminusc + Xbminusd);
+      /* (xa + xc) - (xb + xd) */
+      Xc12C_out = (Xaplusc - Xbplusd);
+      /* (ya + yc) - (yb + yd) */
+      Yc12C_out = (Yaplusc - Ybplusd);
+      /* (xa - xc) + (yb - yd) */
+      Xd12C_out = (Xaminusc + Ybminusd);
+      /* (ya - yc) - (xb - xd) */
+      Yd12C_out = (Yaminusc - Xbminusd);
+
+      co1 = pCoef[ia1 * 2U];
+      si1 = pCoef[(ia1 * 2U) + 1U];
+
+      /*  index calculation for the coefficients */
+      ia3 = ia2 + ia1;
+      co3 = pCoef[ia3 * 2U];
+      si3 = pCoef[(ia3 * 2U) + 1U];
+
+      Xb12_out = Xb12C_out * co1;
+      Yb12_out = Yb12C_out * co1;
+      Xc12_out = Xc12C_out * co2;
+      Yc12_out = Yc12C_out * co2;
+      Xd12_out = Xd12C_out * co3;
+      Yd12_out = Yd12C_out * co3;
+
+      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+      //Xb12_out -= Yb12C_out * si1;
+      p0 = Yb12C_out * si1;
+      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+      //Yb12_out += Xb12C_out * si1;
+      p1 = Xb12C_out * si1;
+      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+      //Xc12_out -= Yc12C_out * si2;
+      p2 = Yc12C_out * si2;
+      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+      //Yc12_out += Xc12C_out * si2;
+      p3 = Xc12C_out * si2;
+      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+      //Xd12_out -= Yd12C_out * si3;
+      p4 = Yd12C_out * si3;
+      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+      //Yd12_out += Xd12C_out * si3;
+      p5 = Xd12C_out * si3;
+
+      Xb12_out -= p0;
+      Yb12_out += p1;
+      Xc12_out -= p2;
+      Yc12_out += p3;
+      Xd12_out -= p4;
+      Yd12_out += p5;
+
+      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+      pSrc[2U * i1] = Xc12_out;
+
+      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+      pSrc[(2U * i1) + 1U] = Yc12_out;
+
+      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+      pSrc[2U * i2] = Xb12_out;
+
+      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+      pSrc[(2U * i2) + 1U] = Yb12_out;
+
+      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+      pSrc[2U * i3] = Xd12_out;
+
+      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+      pSrc[(2U * i3) + 1U] = Yd12_out;
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      /*  Updating input index */
+      i0 = i0 + 1U;
+
+   } while (--j);
+
+   twidCoefModifier <<= 2U;
+
+   /*  Calculation of second stage to excluding last stage */
+   for (k = fftLen >> 2U; k > 4U; k >>= 2U)
+   {
+      /*  Initializations for the first stage */
+      n1 = n2;
+      n2 >>= 2U;
+      ia1 = 0U;
+
+      /*  Calculation of first stage */
+      j = 0;
+      do
+      {
+         /*  index calculation for the coefficients */
+         ia2 = ia1 + ia1;
+         ia3 = ia2 + ia1;
+         co1 = pCoef[ia1 * 2U];
+         si1 = pCoef[(ia1 * 2U) + 1U];
+         co2 = pCoef[ia2 * 2U];
+         si2 = pCoef[(ia2 * 2U) + 1U];
+         co3 = pCoef[ia3 * 2U];
+         si3 = pCoef[(ia3 * 2U) + 1U];
+
+         /*  Twiddle coefficients index modifier */
+         ia1 = ia1 + twidCoefModifier;
+
+         i0 = j;
+         do
+         {
+            /*  index calculation for the input as, */
+            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+            i1 = i0 + n2;
+            i2 = i1 + n2;
+            i3 = i2 + n2;
+
+            xaIn = pSrc[(2U * i0)];
+            yaIn = pSrc[(2U * i0) + 1U];
+
+            xbIn = pSrc[(2U * i1)];
+            ybIn = pSrc[(2U * i1) + 1U];
+
+            xcIn = pSrc[(2U * i2)];
+            ycIn = pSrc[(2U * i2) + 1U];
+
+            xdIn = pSrc[(2U * i3)];
+            ydIn = pSrc[(2U * i3) + 1U];
+
+            /* xa - xc */
+            Xaminusc = xaIn - xcIn;
+            /* (xb - xd) */
+            Xbminusd = xbIn - xdIn;
+            /* ya - yc */
+            Yaminusc = yaIn - ycIn;
+            /* (yb - yd) */
+            Ybminusd = ybIn - ydIn;
+
+            /* xa + xc */
+            Xaplusc = xaIn + xcIn;
+            /* xb + xd */
+            Xbplusd = xbIn + xdIn;
+            /* ya + yc */
+            Yaplusc = yaIn + ycIn;
+            /* yb + yd */
+            Ybplusd = ybIn + ydIn;
+
+            /* (xa - xc) - (yb - yd) */
+            Xb12C_out = (Xaminusc - Ybminusd);
+            /* (ya - yc) +  (xb - xd) */
+            Yb12C_out = (Yaminusc + Xbminusd);
+            /* xa + xc -(xb + xd) */
+            Xc12C_out = (Xaplusc - Xbplusd);
+            /* (ya + yc) - (yb + yd) */
+            Yc12C_out = (Yaplusc - Ybplusd);
+            /* (xa - xc) + (yb - yd) */
+            Xd12C_out = (Xaminusc + Ybminusd);
+            /* (ya - yc) -  (xb - xd) */
+            Yd12C_out = (Yaminusc - Xbminusd);
+
+            pSrc[(2U * i0)] = Xaplusc + Xbplusd;
+            pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd;
+
+            Xb12_out = Xb12C_out * co1;
+            Yb12_out = Yb12C_out * co1;
+            Xc12_out = Xc12C_out * co2;
+            Yc12_out = Yc12C_out * co2;
+            Xd12_out = Xd12C_out * co3;
+            Yd12_out = Yd12C_out * co3;
+
+            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+            //Xb12_out -= Yb12C_out * si1;
+            p0 = Yb12C_out * si1;
+            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+            //Yb12_out += Xb12C_out * si1;
+            p1 = Xb12C_out * si1;
+            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+            //Xc12_out -= Yc12C_out * si2;
+            p2 = Yc12C_out * si2;
+            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+            //Yc12_out += Xc12C_out * si2;
+            p3 = Xc12C_out * si2;
+            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+            //Xd12_out -= Yd12C_out * si3;
+            p4 = Yd12C_out * si3;
+            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+            //Yd12_out += Xd12C_out * si3;
+            p5 = Xd12C_out * si3;
+
+            Xb12_out -= p0;
+            Yb12_out += p1;
+            Xc12_out -= p2;
+            Yc12_out += p3;
+            Xd12_out -= p4;
+            Yd12_out += p5;
+
+            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+            pSrc[2U * i1] = Xc12_out;
+
+            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+            pSrc[(2U * i1) + 1U] = Yc12_out;
+
+            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+            pSrc[2U * i2] = Xb12_out;
+
+            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+            pSrc[(2U * i2) + 1U] = Yb12_out;
+
+            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+            pSrc[2U * i3] = Xd12_out;
+
+            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+            pSrc[(2U * i3) + 1U] = Yd12_out;
+
+            i0 += n1;
+         } while (i0 < fftLen);
+         j++;
+      } while (j <= (n2 - 1U));
+      twidCoefModifier <<= 2U;
+   }
+   /*  Initializations of last stage */
+
+   j = fftLen >> 2;
+   ptr1 = &pSrc[0];
+
+   /*  Calculations of last stage */
+   do
+   {
+      xaIn = ptr1[0];
+      yaIn = ptr1[1];
+      xbIn = ptr1[2];
+      ybIn = ptr1[3];
+      xcIn = ptr1[4];
+      ycIn = ptr1[5];
+      xdIn = ptr1[6];
+      ydIn = ptr1[7];
+
+      /*  Butterfly implementation */
+      /* xa + xc */
+      Xaplusc = xaIn + xcIn;
+
+      /* xa - xc */
+      Xaminusc = xaIn - xcIn;
+
+      /* ya + yc */
+      Yaplusc = yaIn + ycIn;
+
+      /* ya - yc */
+      Yaminusc = yaIn - ycIn;
+
+      /* xb + xd */
+      Xbplusd = xbIn + xdIn;
+
+      /* yb + yd */
+      Ybplusd = ybIn + ydIn;
+
+      /* (xb-xd) */
+      Xbminusd = xbIn - xdIn;
+
+      /* (yb-yd) */
+      Ybminusd = ybIn - ydIn;
+
+      /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+      a0 = (Xaplusc + Xbplusd);
+      /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+      a1 = (Yaplusc + Ybplusd);
+      /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+      a2 = (Xaplusc - Xbplusd);
+      /* yc' = (ya-yb+yc-yd) * onebyfftLen  */
+      a3 = (Yaplusc - Ybplusd);
+      /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+      a4 = (Xaminusc - Ybminusd);
+      /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+      a5 = (Yaminusc + Xbminusd);
+      /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+      a6 = (Xaminusc + Ybminusd);
+      /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+      a7 = (Yaminusc - Xbminusd);
+
+      p0 = a0 * onebyfftLen;
+      p1 = a1 * onebyfftLen;
+      p2 = a2 * onebyfftLen;
+      p3 = a3 * onebyfftLen;
+      p4 = a4 * onebyfftLen;
+      p5 = a5 * onebyfftLen;
+      p6 = a6 * onebyfftLen;
+      p7 = a7 * onebyfftLen;
+
+      /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+      ptr1[0] = p0;
+      /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+      ptr1[1] = p1;
+      /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+      ptr1[2] = p2;
+      /* yc' = (ya-yb+yc-yd) * onebyfftLen  */
+      ptr1[3] = p3;
+      /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+      ptr1[4] = p4;
+      /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+      ptr1[5] = p5;
+      /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+      ptr1[6] = p6;
+      /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+      ptr1[7] = p7;
+
+      /* increment source pointer by 8 for next calculations */
+      ptr1 = ptr1 + 8U;
+
+   } while (--j);
+
+#else
+
+   float32_t t1, t2, r1, r2, s1, s2;
+
+   /* Run the below code for Cortex-M0 */
+
+   /*  Initializations for the first stage */
+   n2 = fftLen;
+   n1 = n2;
+
+   /*  Calculation of first stage */
+   for (k = fftLen; k > 4U; k >>= 2U)
+   {
+      /*  Initializations for the first stage */
+      n1 = n2;
+      n2 >>= 2U;
+      ia1 = 0U;
+
+      /*  Calculation of first stage */
+      j = 0;
+      do
+      {
+         /*  index calculation for the coefficients */
+         ia2 = ia1 + ia1;
+         ia3 = ia2 + ia1;
+         co1 = pCoef[ia1 * 2U];
+         si1 = pCoef[(ia1 * 2U) + 1U];
+         co2 = pCoef[ia2 * 2U];
+         si2 = pCoef[(ia2 * 2U) + 1U];
+         co3 = pCoef[ia3 * 2U];
+         si3 = pCoef[(ia3 * 2U) + 1U];
+
+         /*  Twiddle coefficients index modifier */
+         ia1 = ia1 + twidCoefModifier;
+
+         i0 = j;
+         do
+         {
+            /*  index calculation for the input as, */
+            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+            i1 = i0 + n2;
+            i2 = i1 + n2;
+            i3 = i2 + n2;
+
+            /* xa + xc */
+            r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)];
+
+            /* xa - xc */
+            r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)];
+
+            /* ya + yc */
+            s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U];
+
+            /* ya - yc */
+            s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U];
+
+            /* xb + xd */
+            t1 = pSrc[2U * i1] + pSrc[2U * i3];
+
+            /* xa' = xa + xb + xc + xd */
+            pSrc[2U * i0] = r1 + t1;
+
+            /* xa + xc -(xb + xd) */
+            r1 = r1 - t1;
+
+            /* yb + yd */
+            t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U];
+
+            /* ya' = ya + yb + yc + yd */
+            pSrc[(2U * i0) + 1U] = s1 + t2;
+
+            /* (ya + yc) - (yb + yd) */
+            s1 = s1 - t2;
+
+            /* (yb - yd) */
+            t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U];
+
+            /* (xb - xd) */
+            t2 = pSrc[2U * i1] - pSrc[2U * i3];
+
+            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+            pSrc[2U * i1] = (r1 * co2) - (s1 * si2);
+
+            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+            pSrc[(2U * i1) + 1U] = (s1 * co2) + (r1 * si2);
+
+            /* (xa - xc) - (yb - yd) */
+            r1 = r2 - t1;
+
+            /* (xa - xc) + (yb - yd) */
+            r2 = r2 + t1;
+
+            /* (ya - yc) +  (xb - xd) */
+            s1 = s2 + t2;
+
+            /* (ya - yc) -  (xb - xd) */
+            s2 = s2 - t2;
+
+            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+            pSrc[2U * i2] = (r1 * co1) - (s1 * si1);
+
+            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+            pSrc[(2U * i2) + 1U] = (s1 * co1) + (r1 * si1);
+
+            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+            pSrc[2U * i3] = (r2 * co3) - (s2 * si3);
+
+            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+            pSrc[(2U * i3) + 1U] = (s2 * co3) + (r2 * si3);
+
+            i0 += n1;
+         } while ( i0 < fftLen);
+         j++;
+      } while (j <= (n2 - 1U));
+      twidCoefModifier <<= 2U;
+   }
+   /*  Initializations of last stage */
+   n1 = n2;
+   n2 >>= 2U;
+
+   /*  Calculations of last stage */
+   for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1)
+   {
+      /*  index calculation for the input as, */
+      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+      i1 = i0 + n2;
+      i2 = i1 + n2;
+      i3 = i2 + n2;
+
+      /*  Butterfly implementation */
+      /* xa + xc */
+      r1 = pSrc[2U * i0] + pSrc[2U * i2];
+
+      /* xa - xc */
+      r2 = pSrc[2U * i0] - pSrc[2U * i2];
+
+      /* ya + yc */
+      s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U];
+
+      /* ya - yc */
+      s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U];
+
+      /* xc + xd */
+      t1 = pSrc[2U * i1] + pSrc[2U * i3];
+
+      /* xa' = xa + xb + xc + xd */
+      pSrc[2U * i0] = (r1 + t1) * onebyfftLen;
+
+      /* (xa + xb) - (xc + xd) */
+      r1 = r1 - t1;
+
+      /* yb + yd */
+      t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U];
+
+      /* ya' = ya + yb + yc + yd */
+      pSrc[(2U * i0) + 1U] = (s1 + t2) * onebyfftLen;
+
+      /* (ya + yc) - (yb + yd) */
+      s1 = s1 - t2;
+
+      /* (yb-yd) */
+      t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U];
+
+      /* (xb-xd) */
+      t2 = pSrc[2U * i1] - pSrc[2U * i3];
+
+      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+      pSrc[2U * i1] = r1 * onebyfftLen;
+
+      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+      pSrc[(2U * i1) + 1U] = s1 * onebyfftLen;
+
+      /* (xa - xc) - (yb-yd) */
+      r1 = r2 - t1;
+
+      /* (xa - xc) + (yb-yd) */
+      r2 = r2 + t1;
+
+      /* (ya - yc) + (xb-xd) */
+      s1 = s2 + t2;
+
+      /* (ya - yc) - (xb-xd) */
+      s2 = s2 - t2;
+
+      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+      pSrc[2U * i2] = r1 * onebyfftLen;
+
+      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+      pSrc[(2U * i2) + 1U] = s1 * onebyfftLen;
+
+      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+      pSrc[2U * i3] = r2 * onebyfftLen;
+
+      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+      pSrc[(2U * i3) + 1U] = s2 * onebyfftLen;
+   }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+}
+
+
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
new file mode 100644
index 0000000..5383771
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix4_init_f32.c
+ * Description:  Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief  Initialization function for the floating-point CFFT/CIFFT.
+* @deprecated Do not use this function.  It has been superceded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in]     fftLen         length of the FFT.
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (float32_t *) twiddleCoef;
+
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+
+  case 4096U:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.000244140625;
+    break;
+
+  case 1024U:
+    /*  Initializations of structure parameters for 1024 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.0009765625f;
+    break;
+
+
+  case 256U:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16U;
+    S->bitRevFactor = 16U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    S->onebyfftLen = 0.00390625f;
+    break;
+
+  case 64U:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64U;
+    S->bitRevFactor = 64U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    S->onebyfftLen = 0.015625f;
+    break;
+
+  case 16U:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256U;
+    S->bitRevFactor = 256U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    S->onebyfftLen = 0.0625f;
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
new file mode 100644
index 0000000..b2e38b4
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix4_init_q15.c
+ * Description:  Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+* @brief Initialization function for the Q15 CFFT/CIFFT.
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
+* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
+* @param[in]     fftLen         length of the FFT.
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q15_t *) twiddleCoef_4096_q15;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+  case 4096U:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+    break;
+
+  case 1024U:
+    /*  Initializations of structure parameters for 1024 point FFT */
+    S->twidCoefModifier = 4U;
+    S->bitRevFactor = 4U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+    break;
+
+  case 256U:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16U;
+    S->bitRevFactor = 16U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+    break;
+
+  case 64U:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64U;
+    S->bitRevFactor = 64U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+    break;
+
+  case 16U:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256U;
+    S->bitRevFactor = 256U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
new file mode 100644
index 0000000..9c11754
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix4_init_q31.c
+ * Description:  Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+*
+* @brief  Initialization function for the Q31 CFFT/CIFFT.
+* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
+* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.
+* @param[in]     fftLen         length of the FFT.
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q31_t *) twiddleCoef_4096_q31;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of Instance structure depending on the FFT length */
+  switch (S->fftLen)
+  {
+    /*  Initializations of structure parameters for 4096 point FFT */
+  case 4096U:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    break;
+
+    /*  Initializations of structure parameters for 1024 point FFT */
+  case 1024U:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4U;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4U;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    break;
+
+  case 256U:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16U;
+    S->bitRevFactor = 16U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    break;
+
+  case 64U:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64U;
+    S->bitRevFactor = 64U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    break;
+
+  case 16U:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256U;
+    S->bitRevFactor = 256U;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c
new file mode 100644
index 0000000..140fa53
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c
@@ -0,0 +1,1910 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix4_q15.c
+ * Description:  This file has function definition of Radix-4 FFT & IFFT function and
+ *               In-place bit reversal using bit reversal table
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+
+void arm_radix4_butterfly_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_inverse_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier);
+
+void arm_bitreversal_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+ * @details
+ * @brief Processing function for the Q15 CFFT/CIFFT.
+ * @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
+ * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ *
+ * \par Input and output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different FFT sizes.
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:
+ * \par
+ * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"
+ * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"
+ */
+
+void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc)
+{
+  if (S->ifftFlag == 1U)
+  {
+    /*  Complex IFFT radix-4  */
+    arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier);
+  }
+  else
+  {
+    /*  Complex FFT radix-4  */
+    arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier);
+  }
+
+  if (S->bitReverseFlag == 1U)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+/*
+* Radix-4 FFT algorithm used is :
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 FFT:
+* Wn = co1 + j * (- si1)
+* W2n = co2 + j * (- si2)
+* W3n = co3 + j * (- si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
+*
+*/
+
+/**
+ * @brief  Core function for the Q15 CFFT butterfly process.
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+ * @param[in]      fftLen           length of the FFT.
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_radix4_butterfly_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  uint32_t n1, n2, ic, i0, j, k;
+
+  q15_t *ptr1;
+  q15_t *pSi0;
+  q15_t *pSi1;
+  q15_t *pSi2;
+  q15_t *pSi3;
+
+  q31_t xaya, xbyb, xcyc, xdyd;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2U;
+
+  /* Index for twiddle coefficient */
+  ic = 0U;
+
+  /* Index for input read and output write */
+  j = n2;
+
+  pSi0 = pSrc16;
+  pSi1 = pSi0 + 2 * n2;
+  pSi2 = pSi1 + 2 * n2;
+  pSi3 = pSi2 + 2 * n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = _SIMD32_OFFSET(pSi0);
+    T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
+    T = __SHADD16(T, 0); // it turns out doing this twice is 2 cycles, the alternative takes 3 cycles
+    //in = ((int16_t) (T & 0xFFFF)) >> 2;       // alternative code that takes 3 cycles
+    //T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* Read yc (real), xc(imag) input */
+    S = _SIMD32_OFFSET(pSi2);
+    S = __SHADD16(S, 0);
+    S = __SHADD16(S, 0);
+
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = _SIMD32_OFFSET(pSi1);
+    T = __SHADD16(T, 0);
+    T = __SHADD16(T, 0);
+
+    /* Read yd (real), xd(imag) input */
+    U = _SIMD32_OFFSET(pSi3);
+    U = __SHADD16(U, 0);
+    U = __SHADD16(U, 0);
+
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    _SIMD32_OFFSET(pSi0) = __SHADD16(R, T);
+    pSi0 += 2;
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = _SIMD32_OFFSET(pCoef16 + (4U * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUAD(C2, R) >> 16U;
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUSDX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUSDX(R, C2) >> 16U;
+    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = _SIMD32_OFFSET(pSi1);
+    T = __SHADD16(T, 0);
+    T = __SHADD16(T, 0);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    _SIMD32_OFFSET(pSi1) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+    pSi1 += 2;
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = _SIMD32_OFFSET(pSi3);
+    U = __SHADD16(U, 0);
+    U = __SHADD16(U, 0);
+
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QSAX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QASX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = _SIMD32_OFFSET(pCoef16 + (2U * ic));
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = __SMUAD(C1, S) >> 16U;
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = __SMUSDX(C1, S);
+
+#else
+
+    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out1 = __SMUSDX(S, C1) >> 16U;
+    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    _SIMD32_OFFSET(pSi2) =
+      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+    pSi2 += 2;
+
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = _SIMD32_OFFSET(pCoef16 + (6U * ic));
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = __SMUAD(C3, R) >> 16U;
+    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = __SMUSDX(C3, R);
+
+#else
+
+    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out1 = __SMUSDX(R, C3) >> 16U;
+    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    _SIMD32_OFFSET(pSi3) =
+      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+    pSi3 += 2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+  } while (--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2U;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4U; k > 4U; k >>= 2U)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2U;
+    ic = 0U;
+
+    for (j = 0U; j <= (n2 - 1U); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = _SIMD32_OFFSET(pCoef16 + (2U * ic));
+      C2 = _SIMD32_OFFSET(pCoef16 + (4U * ic));
+      C3 = _SIMD32_OFFSET(pCoef16 + (6U * ic));
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      pSi0 = pSrc16 + 2 * j;
+      pSi1 = pSi0 + 2 * n2;
+      pSi2 = pSi1 + 2 * n2;
+      pSi3 = pSi2 + 2 * n2;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = _SIMD32_OFFSET(pSi0);
+
+        /* Read yc (real), xc(imag) input */
+        S = _SIMD32_OFFSET(pSi2);
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSi1);
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSi3);
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        out1 = __SHADD16(out1, 0);
+        _SIMD32_OFFSET(pSi0) = out1;
+        pSi0 += 2 * n1;
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = __SMUAD(C2, R) >> 16U;
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUSDX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUSDX(R, C2) >> 16U;
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSi1);
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        _SIMD32_OFFSET(pSi1) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi1 += 2 * n1;
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSi3);
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHSAX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUAD(C1, S) >> 16U;
+        out2 = __SMUSDX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHASX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSDX(S, C1) >> 16U;
+        out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        _SIMD32_OFFSET(pSi2) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi2 += 2 * n1;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(C3, R) >> 16U;
+        out2 = __SMUSDX(C3, R);
+
+#else
+
+        out1 = __SMUSDX(R, C3) >> 16U;
+        out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+        _SIMD32_OFFSET(pSi3) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi3 += 2 * n1;
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2U;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+
+  ptr1 = &pSrc16[0];
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  do
+  {
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD32(ptr1)++;
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD32(ptr1)++;
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD32(ptr1)++;
+
+    /* Read xd (real), yd(imag) input */
+    xdyd = *__SIMD32(ptr1)++;
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(xaya, xcyc);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8U;
+
+
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(xaya, xcyc);
+
+    /* Read yd (real), xd(imag) input */
+    /* T = packed( (yb - yd), (xb - xd))  */
+    U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+#else
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  } while (--j);
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2U;
+
+  /* Index for twiddle coefficient */
+  ic = 0U;
+
+  /* Index for input read and output write */
+  i0 = 0U;
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2U] >> 2U;
+    T1 = pSrc16[(i0 * 2U) + 1U] >> 2U;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2U] >> 2U;
+    S1 = pSrc16[(i2 * 2U) + 1U] >> 2U;
+
+    /* R0 = (ya + yc) */
+    R0 = __SSAT(T0 + S0, 16U);
+    /* R1 = (xa + xc) */
+    R1 = __SSAT(T1 + S1, 16U);
+
+    /* S0 = (ya - yc) */
+    S0 = __SSAT(T0 - S0, 16);
+    /* S1 = (xa - xc) */
+    S1 = __SSAT(T1 - S1, 16);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2U] >> 2U;
+    T1 = pSrc16[(i1 * 2U) + 1U] >> 2U;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2U] >> 2U;
+    U1 = pSrc16[(i3 * 2U) + 1] >> 2U;
+
+    /* T0 = (yb + yd) */
+    T0 = __SSAT(T0 + U0, 16U);
+    /* T1 = (xb + xd) */
+    T1 = __SSAT(T1 + U1, 16U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* ya' = ya + yb + yc + yd */
+    /* xa' = xa + xb + xc + xd */
+    pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U);
+    pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U);
+
+    /* R0 = (ya + yc) - (yb + yd) */
+    /* R1 = (xa + xc) - (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16U);
+    R1 = __SSAT(R1 - T1, 16U);
+
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2U * ic * 2U];
+    Si2 = pCoef16[(2U * ic * 2U) + 1];
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U);
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 =  xb */
+    T0 = pSrc16[i1 * 2U] >> 2;
+    T1 = pSrc16[(i1 * 2U) + 1] >> 2;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2U] = out1;
+    pSrc16[(i1 * 2U) + 1] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd */
+    U0 = pSrc16[i3 * 2U] >> 2;
+    U1 = pSrc16[(i3 * 2U) + 1] >> 2;
+    /* T0 = yb-yd */
+    T0 = __SSAT(T0 - U0, 16);
+    /* T1 = xb-xd */
+    T1 = __SSAT(T1 - U1, 16);
+
+    /* R1 = (ya-yc) + (xb- xd),  R0 = (xa-xc) - (yb-yd)) */
+    R0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16);
+    R1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
+    S0 = (q15_t) __SSAT(((q31_t) S0 + T1), 16U);
+    S1 = (q15_t) __SSAT(((q31_t) S1 - T0), 16U);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2U];
+    Si1 = pCoef16[(ic * 2U) + 1];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = (q15_t) ((Si1 * S1 + Co1 * S0) >> 16);
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16);
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2U] = out1;
+    pSrc16[(i2 * 2U) + 1] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3U * (ic * 2U)];
+    Si3 = pCoef16[(3U * (ic * 2U)) + 1];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U);
+    /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2U] = out1;
+    pSrc16[(i3 * 2U) + 1] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1U;
+
+  } while (--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2U;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4U; k > 4U; k >>= 2U)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2U;
+    ic = 0U;
+
+    for (j = 0U; j <= (n2 - 1U); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2U];
+      Si1 = pCoef16[(ic * 2U) + 1U];
+      Co2 = pCoef16[2U * (ic * 2U)];
+      Si2 = pCoef16[(2U * (ic * 2U)) + 1U];
+      Co3 = pCoef16[3U * (ic * 2U)];
+      Si3 = pCoef16[(3U * (ic * 2U)) + 1U];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2U];
+        T1 = pSrc16[(i0 * 2U) + 1U];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2U];
+        S1 = pSrc16[(i2 * 2U) + 1U];
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16);
+        R1 = __SSAT(T1 + S1, 16);
+
+        /* S0 = (ya - yc), S1 =(xa - xc) */
+        S0 = __SSAT(T0 - S0, 16);
+        S1 = __SSAT(T1 - S1, 16);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2U];
+        T1 = pSrc16[(i1 * 2U) + 1U];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2U];
+        U1 = pSrc16[(i3 * 2U) + 1U];
+
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16);
+        T1 = __SSAT(T1 + U1, 16);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = ((R0 >> 1U) + (T0 >> 1U)) >> 1U;
+        out2 = ((R1 >> 1U) + (T1 >> 1U)) >> 1U;
+
+        pSrc16[i0 * 2U] = out1;
+        pSrc16[(2U * i0) + 1U] = out2;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1U) - (T0 >> 1U);
+        R1 = (R1 >> 1U) - (T1 >> 1U);
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U);
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2U];
+        T1 = pSrc16[(i1 * 2U) + 1U];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2U] = out1;
+        pSrc16[(i1 * 2U) + 1U] = out2;
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2U];
+        U1 = pSrc16[(i3 * 2U) + 1U];
+
+        /* T0 = yb-yd, T1 = xb-xd */
+        T0 = __SSAT(T0 - U0, 16);
+        T1 = __SSAT(T1 - U1, 16);
+
+        /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
+        R0 = (S0 >> 1U) - (T1 >> 1U);
+        R1 = (S1 >> 1U) + (T0 >> 1U);
+
+        /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
+        S0 = (S0 >> 1U) + (T1 >> 1U);
+        S1 = (S1 >> 1U) - (T0 >> 1U);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (q15_t) ((Co1 * S0 + Si1 * S1) >> 16U);
+
+        out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16U);
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        pSrc16[i2 * 2U] = out1;
+        pSrc16[(i2 * 2U) + 1U] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U);
+
+        out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U);
+        /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+        pSrc16[i3 * 2U] = out1;
+        pSrc16[(i3 * 2U) + 1U] = out2;
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2U;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2U;
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2U];
+    T1 = pSrc16[(i0 * 2U) + 1U];
+
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2U];
+    S1 = pSrc16[(i2 * 2U) + 1U];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16U);
+    R1 = __SSAT(T1 + S1, 16U);
+
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16U);
+    S1 = __SSAT(T1 - S1, 16U);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2U];
+    T1 = pSrc16[(i1 * 2U) + 1U];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2U];
+    U1 = pSrc16[(i3 * 2U) + 1U];
+
+    /* T0 = (yb + yd), T1 = (xb + xd)) */
+    T0 = __SSAT(T0 + U0, 16U);
+    T1 = __SSAT(T1 + U1, 16U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U);
+    pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1U) - (T0 >> 1U);
+    R1 = (R1 >> 1U) - (T1 >> 1U);
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2U];
+    T1 = pSrc16[(i1 * 2U) + 1U];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2U] = R0;
+    pSrc16[(i1 * 2U) + 1U] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2U];
+    U1 = pSrc16[(i3 * 2U) + 1U];
+    /* T0 = (yb - yd), T1 = (xb - xd)  */
+    T0 = __SSAT(T0 - U0, 16U);
+    T1 = __SSAT(T1 - U1, 16U);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc16[i2 * 2U] = (S0 >> 1U) + (T1 >> 1U);
+    pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc16[i3 * 2U] = (S0 >> 1U) - (T1 >> 1U);
+    pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U);
+
+  }
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+
+/**
+ * @brief  Core function for the Q15 CIFFT butterfly process.
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+ * @param[in]      fftLen           length of the FFT.
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+/*
+* Radix-4 IFFT algorithm used is :
+*
+* CIFFT uses same twiddle coefficients as CFFT function
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]
+*
+*
+* IFFT is implemented with following changes in equations from FFT
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 IFFT:
+* Wn = co1 + j * (si1)
+* W2n = co2 + j * (si2)
+* W3n = co3 + j * (si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)
+*
+*/
+
+void arm_radix4_butterfly_inverse_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  uint32_t n1, n2, ic, i0, j, k;
+
+  q15_t *ptr1;
+  q15_t *pSi0;
+  q15_t *pSi1;
+  q15_t *pSi2;
+  q15_t *pSi3;
+
+  q31_t xaya, xbyb, xcyc, xdyd;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2U;
+
+  /* Index for twiddle coefficient */
+  ic = 0U;
+
+  /* Index for input read and output write */
+  j = n2;
+
+  pSi0 = pSrc16;
+  pSi1 = pSi0 + 2 * n2;
+  pSi2 = pSi1 + 2 * n2;
+  pSi3 = pSi2 + 2 * n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = _SIMD32_OFFSET(pSi0);
+    T = __SHADD16(T, 0);
+    T = __SHADD16(T, 0);
+
+    /* Read yc (real), xc(imag) input */
+    S = _SIMD32_OFFSET(pSi2);
+    S = __SHADD16(S, 0);
+    S = __SHADD16(S, 0);
+
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = _SIMD32_OFFSET(pSi1);
+    T = __SHADD16(T, 0);
+    T = __SHADD16(T, 0);
+
+    /* Read yd (real), xd(imag) input */
+    U = _SIMD32_OFFSET(pSi3);
+    U = __SHADD16(U, 0);
+    U = __SHADD16(U, 0);
+
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    _SIMD32_OFFSET(pSi0) = __SHADD16(R, T);
+    pSi0 += 2;
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = _SIMD32_OFFSET(pCoef16 + (4U * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUSD(C2, R) >> 16U;
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUADX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUADX(C2, R) >> 16U;
+    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = _SIMD32_OFFSET(pSi1);
+    T = __SHADD16(T, 0);
+    T = __SHADD16(T, 0);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    _SIMD32_OFFSET(pSi1) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+    pSi1 += 2;
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = _SIMD32_OFFSET(pSi3);
+    U = __SHADD16(U, 0);
+    U = __SHADD16(U, 0);
+
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+    S = __QASX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QSAX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = _SIMD32_OFFSET(pCoef16 + (2U * ic));
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = __SMUSD(C1, S) >> 16U;
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = __SMUADX(C1, S);
+
+#else
+
+    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out1 = __SMUADX(C1, S) >> 16U;
+    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    _SIMD32_OFFSET(pSi2) =
+      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+    pSi2 += 2;
+
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = _SIMD32_OFFSET(pCoef16 + (6U * ic));
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = __SMUSD(C3, R) >> 16U;
+    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = __SMUADX(C3, R);
+
+#else
+
+    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out1 = __SMUADX(C3, R) >> 16U;
+    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    _SIMD32_OFFSET(pSi3) =
+      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+    pSi3 += 2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+  } while (--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2U;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4U; k > 4U; k >>= 2U)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2U;
+    ic = 0U;
+
+    for (j = 0U; j <= (n2 - 1U); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = _SIMD32_OFFSET(pCoef16 + (2U * ic));
+      C2 = _SIMD32_OFFSET(pCoef16 + (4U * ic));
+      C3 = _SIMD32_OFFSET(pCoef16 + (6U * ic));
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      pSi0 = pSrc16 + 2 * j;
+      pSi1 = pSi0 + 2 * n2;
+      pSi2 = pSi1 + 2 * n2;
+      pSi3 = pSi2 + 2 * n2;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = _SIMD32_OFFSET(pSi0);
+
+        /* Read yc (real), xc(imag) input */
+        S = _SIMD32_OFFSET(pSi2);
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSi1);
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSi3);
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        out1 = __SHADD16(out1, 0);
+        _SIMD32_OFFSET(pSi0) = out1;
+        pSi0 += 2 * n1;
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = __SMUSD(C2, R) >> 16U;
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUADX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUADX(R, C2) >> 16U;
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSi1);
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        _SIMD32_OFFSET(pSi1) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi1 += 2 * n1;
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSi3);
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHASX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSD(C1, S) >> 16U;
+        out2 = __SMUADX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHSAX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUADX(S, C1) >> 16U;
+        out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        _SIMD32_OFFSET(pSi2) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi2 += 2 * n1;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(C3, R) >> 16U;
+        out2 = __SMUADX(C3, R);
+
+#else
+
+        out1 = __SMUADX(C3, R) >> 16U;
+        out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+        _SIMD32_OFFSET(pSi3) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+        pSi3 += 2 * n1;
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2U;
+  }
+  /* end of middle stage process */
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+
+  ptr1 = &pSrc16[0];
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  do
+  {
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD32(ptr1)++;
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD32(ptr1)++;
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD32(ptr1)++;
+
+    /* Read xd (real), yd(imag) input */
+    xdyd = *__SIMD32(ptr1)++;
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(xaya, xcyc);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8U;
+
+
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(xaya, xcyc);
+
+    /* Read yd (real), xd(imag) input */
+    /* T = packed( (yb - yd), (xb - xd))  */
+    U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#else
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  } while (--j);
+
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2U;
+
+  /* Index for twiddle coefficient */
+  ic = 0U;
+
+  /* Index for input read and output write */
+  i0 = 0U;
+
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  Start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2U] >> 2U;
+    T1 = pSrc16[(i0 * 2U) + 1U] >> 2U;
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2U] >> 2U;
+    S1 = pSrc16[(i2 * 2U) + 1U] >> 2U;
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16U);
+    R1 = __SSAT(T1 + S1, 16U);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16U);
+    S1 = __SSAT(T1 - S1, 16U);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2U] >> 2U;
+    T1 = pSrc16[(i1 * 2U) + 1U] >> 2U;
+    /* Read yd (real), xd(imag) input */
+    /* input is down scale by 4 to avoid overflow */
+    U0 = pSrc16[i3 * 2U] >> 2U;
+    U1 = pSrc16[(i3 * 2U) + 1U] >> 2U;
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16U);
+    T1 = __SSAT(T1 + U1, 16U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U);
+    pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16U);
+    R1 = __SSAT(R1 - T1, 16U);
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2U * ic * 2U];
+    Si2 = pCoef16[(2U * ic * 2U) + 1U];
+    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16U);
+    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16U);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 = xb */
+    T0 = pSrc16[i1 * 2U] >> 2U;
+    T1 = pSrc16[(i1 * 2U) + 1U] >> 2U;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2U] = out1;
+    pSrc16[(i1 * 2U) + 1U] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd) */
+    U0 = pSrc16[i3 * 2U] >> 2U;
+    U1 = pSrc16[(i3 * 2U) + 1U] >> 2U;
+
+    /* T0 = yb-yd, T1 = xb-xd) */
+    T0 = __SSAT(T0 - U0, 16U);
+    T1 = __SSAT(T1 - U1, 16U);
+    /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+    R0 = (q15_t) __SSAT((q31_t) (S0 + T1), 16);
+    R1 = (q15_t) __SSAT((q31_t) (S1 - T0), 16);
+    /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+    S0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16);
+    S1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2U];
+    Si1 = pCoef16[(ic * 2U) + 1U];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U);
+    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U);
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2U] = out1;
+    pSrc16[(i2 * 2U) + 1U] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3U * ic * 2U];
+    Si3 = pCoef16[(3U * ic * 2U) + 1U];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+    out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U);
+    /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+    out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2U] = out1;
+    pSrc16[(i3 * 2U) + 1U] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1U;
+
+  } while (--j);
+
+  /*  End of first stage process */
+
+  /* data is in 4.11(q11) format */
+
+
+  /*  Start of Middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2U;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4U; k > 4U; k >>= 2U)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2U;
+    ic = 0U;
+
+    for (j = 0U; j <= (n2 - 1U); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2U];
+      Si1 = pCoef16[(ic * 2U) + 1U];
+      Co2 = pCoef16[2U * ic * 2U];
+      Si2 = pCoef16[2U * ic * 2U + 1U];
+      Co3 = pCoef16[3U * ic * 2U];
+      Si3 = pCoef16[(3U * ic * 2U) + 1U];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2U];
+        T1 = pSrc16[(i0 * 2U) + 1U];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2U];
+        S1 = pSrc16[(i2 * 2U) + 1U];
+
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16U);
+        R1 = __SSAT(T1 + S1, 16U);
+        /* S0 = (ya - yc), S1 = (xa - xc) */
+        S0 = __SSAT(T0 - S0, 16U);
+        S1 = __SSAT(T1 - S1, 16U);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2U];
+        T1 = pSrc16[(i1 * 2U) + 1U];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2U];
+        U1 = pSrc16[(i3 * 2U) + 1U];
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16U);
+        T1 = __SSAT(T1 + U1, 16U);
+
+        /*  writing the butterfly processed i0 sample */
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        pSrc16[i0 * 2U] = ((R0 >> 1U) + (T0 >> 1U)) >> 1U;
+        pSrc16[(i0 * 2U) + 1U] = ((R1 >> 1U) + (T1 >> 1U)) >> 1U;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1U) - (T0 >> 1U);
+        R1 = (R1 >> 1U) - (T1 >> 1U);
+
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16);
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2U];
+        T1 = pSrc16[(i1 * 2U) + 1U];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2U] = out1;
+        pSrc16[(i1 * 2U) + 1U] = out2;
+
+        /*  Butterfly calculations */
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2U];
+        U1 = pSrc16[(i3 * 2U) + 1U];
+
+        /* T0 = yb-yd, T1 = xb-xd) */
+        T0 = __SSAT(T0 - U0, 16U);
+        T1 = __SSAT(T1 - U1, 16U);
+
+        /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+        R0 = (S0 >> 1U) + (T1 >> 1U);
+        R1 = (S1 >> 1U) - (T0 >> 1U);
+
+        /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+        S0 = (S0 >> 1U) - (T1 >> 1U);
+        S1 = (S1 >> 1U) + (T0 >> 1U);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U);
+        out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U);
+        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+        pSrc16[i2 * 2U] = out1;
+        pSrc16[(i2 * 2U) + 1U] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U);
+
+        out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U);
+        /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+        /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+        pSrc16[i3 * 2U] = out1;
+        pSrc16[(i3 * 2U) + 1U] = out2;
+
+
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2U;
+  }
+  /*  End of Middle stages process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point   */
+  /* data is in 6.10(q10) format for the 64 point  */
+  /* data is in 4.12(q12) format for the 16 point  */
+
+  /* start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2U;
+
+  /*  Butterfly implementation */
+  for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2U];
+    T1 = pSrc16[(i0 * 2U) + 1U];
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2U];
+    S1 = pSrc16[(i2 * 2U) + 1U];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16U);
+    R1 = __SSAT(T1 + S1, 16U);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16U);
+    S1 = __SSAT(T1 - S1, 16U);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2U];
+    T1 = pSrc16[(i1 * 2U) + 1U];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2U];
+    U1 = pSrc16[(i3 * 2U) + 1U];
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16U);
+    T1 = __SSAT(T1 + U1, 16U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U);
+    pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1U) - (T0 >> 1U);
+    R1 = (R1 >> 1U) - (T1 >> 1U);
+
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2U];
+    T1 = pSrc16[(i1 * 2U) + 1U];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2U] = R0;
+    pSrc16[(i1 * 2U) + 1U] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2U];
+    U1 = pSrc16[(i3 * 2U) + 1U];
+    /* T0 = (yb - yd), T1 = (xb - xd) */
+    T0 = __SSAT(T0 - U0, 16U);
+    T1 = __SSAT(T1 - U1, 16U);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc16[i2 * 2U] = (S0 >> 1U) - (T1 >> 1U);
+    pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U);
+
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc16[i3 * 2U] = (S0 >> 1U) + (T1 >> 1U);
+    pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U);
+  }
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c
new file mode 100644
index 0000000..35025bb
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c
@@ -0,0 +1,1389 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix4_q31.c
+ * Description:  This file has function definition of Radix-4 FFT & IFFT function and
+ *               In-place bit reversal using bit reversal table
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+void arm_radix4_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Processing function for the Q31 CFFT/CIFFT.
+ * @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
+ * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+ * @return none.
+ *
+ * \par Input and output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different FFT sizes.
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:
+ * \par
+ * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"
+ * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"
+ *
+ */
+
+void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc)
+{
+  if (S->ifftFlag == 1U)
+  {
+    /* Complex IFFT radix-4 */
+    arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier);
+  }
+  else
+  {
+    /* Complex FFT radix-4 */
+    arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier);
+  }
+
+  if (S->bitReverseFlag == 1U)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+/*
+* Radix-4 FFT algorithm used is :
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 FFT:
+* Wn = co1 + j * (- si1)
+* W2n = co2 + j * (- si2)
+* W3n = co3 + j * (- si3)
+*
+*  Butterfly implementation:
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
+*
+*/
+
+/**
+ * @brief  Core function for the Q31 CFFT butterfly process.
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+ * @param[in]      fftLen           length of the FFT.
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_radix4_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+#if defined(ARM_MATH_CM7)
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+  q31_t xa, xb, xc, xd;
+  q31_t ya, yb, yc, yd;
+  q31_t xa_out, xb_out, xc_out, xd_out;
+  q31_t ya_out, yb_out, yc_out, yd_out;
+
+  q31_t *ptr1;
+  q63_t xaya, xbyb, xcyc, xdyd;
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+
+  /* start of first stage process */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2U;
+  i0 = 0U;
+  ia1 = 0U;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[(2U * i0)] >> 4U) + (pSrc[(2U * i2)] >> 4U);
+    /* xa - xc */
+    r2 = (pSrc[2U * i0] >> 4U) - (pSrc[2U * i2] >> 4U);
+
+    /* xb + xd */
+    t1 = (pSrc[2U * i1] >> 4U) + (pSrc[2U * i3] >> 4U);
+
+    /* ya + yc */
+    s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U);
+    /* ya - yc */
+    s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2U * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U);
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2U * i0) + 1U] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U);
+    /* xb - xd */
+    t2 = (pSrc[2U * i1] >> 4U) - (pSrc[2U * i3] >> 4U);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2U * ia1;
+    co2 = pCoef[ia2 * 2U];
+    si2 = pCoef[(ia2 * 2U) + 1U];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U;
+
+    /* (xa - xc) + (yb - yd) */
+    r1 = r2 + t1;
+    /* (xa - xc) - (yb - yd) */
+    r2 = r2 - t1;
+
+    /* (ya - yc) - (xb - xd) */
+    s1 = s2 - t2;
+    /* (ya - yc) + (xb - xd) */
+    s2 = s2 + t2;
+
+    co1 = pCoef[ia1 * 2U];
+    si1 = pCoef[(ia1 * 2U) + 1U];
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3U * ia1;
+    co3 = pCoef[ia3 * 2U];
+    si3 = pCoef[(ia3 * 2U) + 1U];
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1U;
+
+  } while (--j);
+
+  /* end of first stage process */
+
+  /* data is in 5.27(q27) format */
+
+
+  /* start of Middle stages process */
+
+
+  /* each stage in middle stages provides two down scaling of the input */
+
+  twidCoefModifier <<= 2U;
+
+
+  for (k = fftLen / 4U; k > 4U; k >>= 2U)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2U;
+    ia1 = 0U;
+
+    /*  Calculation of first stage */
+    for (j = 0U; j <= (n2 - 1U); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2U];
+      si1 = pCoef[(ia1 * 2U) + 1U];
+      co2 = pCoef[ia2 * 2U];
+      si2 = pCoef[(ia2 * 2U) + 1U];
+      co3 = pCoef[ia3 * 2U];
+      si3 = pCoef[(ia3 * 2U) + 1U];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2U * i0] + pSrc[2U * i2];
+        /* xa - xc */
+        r2 = pSrc[2U * i0] - pSrc[2U * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U];
+        /* ya - yc */
+        s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U];
+
+        /* xb + xd */
+        t1 = pSrc[2U * i1] + pSrc[2U * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2U * i0] = (r1 + t1) >> 2U;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U];
+        /* (xb - xd) */
+        t2 = pSrc[2U * i1] - pSrc[2U * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1U;
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1U;
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U;
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U;
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U;
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U;
+      }
+    }
+    twidCoefModifier <<= 2U;
+  }
+#else
+  uint32_t n1, n2, ia1, ia2, ia3, i0, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+  q31_t xa, xb, xc, xd;
+  q31_t ya, yb, yc, yd;
+  q31_t xa_out, xb_out, xc_out, xd_out;
+  q31_t ya_out, yb_out, yc_out, yd_out;
+
+  q31_t *ptr1;
+  q31_t *pSi0;
+  q31_t *pSi1;
+  q31_t *pSi2;
+  q31_t *pSi3;
+  q63_t xaya, xbyb, xcyc, xdyd;
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+
+  /* start of first stage process */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2U;
+
+  ia1 = 0U;
+
+  j = n2;
+
+  pSi0 = pSrc;
+  pSi1 = pSi0 + 2 * n2;
+  pSi2 = pSi1 + 2 * n2;
+  pSi3 = pSi2 + 2 * n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSi0[0] >> 4U) + (pSi2[0] >> 4U);
+    /* xa - xc */
+    r2 = (pSi0[0] >> 4U) - (pSi2[0] >> 4U);
+
+    /* xb + xd */
+    t1 = (pSi1[0] >> 4U) + (pSi3[0] >> 4U);
+
+    /* ya + yc */
+    s1 = (pSi0[1] >> 4U) + (pSi2[1] >> 4U);
+    /* ya - yc */
+    s2 = (pSi0[1] >> 4U) - (pSi2[1] >> 4U);
+
+    /* xa' = xa + xb + xc + xd */
+    *pSi0++ = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSi1[1] >> 4U) + (pSi3[1] >> 4U);
+
+    /* ya' = ya + yb + yc + yd */
+    *pSi0++ = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSi1[1] >> 4U) - (pSi3[1] >> 4U);
+    /* xb - xd */
+    t2 = (pSi1[0] >> 4U) - (pSi3[0] >> 4U);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2U * ia1;
+    co2 = pCoef[ia2 * 2U];
+    si2 = pCoef[(ia2 * 2U) + 1U];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    *pSi1++ = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    *pSi1++ = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U;
+
+    /* (xa - xc) + (yb - yd) */
+    r1 = r2 + t1;
+    /* (xa - xc) - (yb - yd) */
+    r2 = r2 - t1;
+
+    /* (ya - yc) - (xb - xd) */
+    s1 = s2 - t2;
+    /* (ya - yc) + (xb - xd) */
+    s2 = s2 + t2;
+
+    co1 = pCoef[ia1 * 2U];
+    si1 = pCoef[(ia1 * 2U) + 1U];
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    *pSi2++ = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    *pSi2++ = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3U * ia1;
+    co3 = pCoef[ia3 * 2U];
+    si3 = pCoef[(ia3 * 2U) + 1U];
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    *pSi3++ = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    *pSi3++ = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+  } while (--j);
+
+  /* end of first stage process */
+
+  /* data is in 5.27(q27) format */
+
+
+  /* start of Middle stages process */
+
+
+  /* each stage in middle stages provides two down scaling of the input */
+
+  twidCoefModifier <<= 2U;
+
+
+  for (k = fftLen / 4U; k > 4U; k >>= 2U)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2U;
+    ia1 = 0U;
+
+    /*  Calculation of first stage */
+    for (j = 0U; j <= (n2 - 1U); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2U];
+      si1 = pCoef[(ia1 * 2U) + 1U];
+      co2 = pCoef[ia2 * 2U];
+      si2 = pCoef[(ia2 * 2U) + 1U];
+      co3 = pCoef[ia3 * 2U];
+      si3 = pCoef[(ia3 * 2U) + 1U];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      pSi0 = pSrc + 2 * j;
+      pSi1 = pSi0 + 2 * n2;
+      pSi2 = pSi1 + 2 * n2;
+      pSi3 = pSi2 + 2 * n2;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSi0[0] + pSi2[0];
+
+        /* xa - xc */
+        r2 = pSi0[0] - pSi2[0];
+
+
+        /* ya + yc */
+        s1 = pSi0[1] + pSi2[1];
+
+        /* ya - yc */
+        s2 = pSi0[1] - pSi2[1];
+
+
+        /* xb + xd */
+        t1 = pSi1[0] + pSi3[0];
+
+
+        /* xa' = xa + xb + xc + xd */
+        pSi0[0] = (r1 + t1) >> 2U;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSi1[1] + pSi3[1];
+
+        /* ya' = ya + yb + yc + yd */
+        pSi0[1] = (s1 + t2) >> 2U;
+        pSi0 += 2 * n1;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSi1[1] - pSi3[1];
+
+        /* (xb - xd) */
+        t2 = pSi1[0] - pSi3[0];
+
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSi1[0] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1U;
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSi1[1] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1U;
+        pSi1 += 2 * n1;
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSi2[0] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U;
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSi2[1] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U;
+        pSi2 += 2 * n1;
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSi3[0] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U;
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSi3[1] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U;
+        pSi3 += 2 * n1;
+      }
+    }
+    twidCoefModifier <<= 2U;
+  }
+#endif
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* start of Last stage process */
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+  ptr1 = &pSrc[0];
+
+  /*  Calculations of last stage */
+  do
+  {
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    xa = (q31_t) xaya;
+    ya = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    xb = (q31_t) xbyb;
+    yb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    xc = (q31_t) xcyc;
+    yc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    xd = (q31_t) xdyd;
+    yd = (q31_t) (xdyd >> 32);
+
+#else
+
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    ya = (q31_t) xaya;
+    xa = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    yb = (q31_t) xbyb;
+    xb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    yc = (q31_t) xcyc;
+    xc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    yd = (q31_t) xdyd;
+    xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+    /* xa' = xa + xb + xc + xd */
+    xa_out = xa + xb + xc + xd;
+
+    /* ya' = ya + yb + yc + yd */
+    ya_out = ya + yb + yc + yd;
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8U;
+
+    /* writing xa' and ya' */
+    *ptr1++ = xa_out;
+    *ptr1++ = ya_out;
+
+    xc_out = (xa - xb + xc - xd);
+    yc_out = (ya - yb + yc - yd);
+
+    /* writing xc' and yc' */
+    *ptr1++ = xc_out;
+    *ptr1++ = yc_out;
+
+    xb_out = (xa + yb - xc - yd);
+    yb_out = (ya - xb - yc + xd);
+
+    /* writing xb' and yb' */
+    *ptr1++ = xb_out;
+    *ptr1++ = yb_out;
+
+    xd_out = (xa - yb - xc + yd);
+    yd_out = (ya + xb - yc - xd);
+
+    /* writing xd' and yd' */
+    *ptr1++ = xd_out;
+    *ptr1++ = yd_out;
+
+
+  } while (--j);
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+
+}
+
+
+/**
+ * @brief  Core function for the Q31 CIFFT butterfly process.
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+ * @param[in]      fftLen           length of the FFT.
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+
+/*
+* Radix-4 IFFT algorithm used is :
+*
+* CIFFT uses same twiddle coefficients as CFFT Function
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]
+*
+*
+* IFFT is implemented with following changes in equations from FFT
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 IFFT:
+* Wn = co1 + j * (si1)
+* W2n = co2 + j * (si2)
+* W3n = co3 + j * (si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)
+*
+*/
+
+void arm_radix4_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+#if defined(ARM_MATH_CM7)
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+  q31_t xa, xb, xc, xd;
+  q31_t ya, yb, yc, yd;
+  q31_t xa_out, xb_out, xc_out, xd_out;
+  q31_t ya_out, yb_out, yc_out, yd_out;
+
+  q31_t *ptr1;
+  q63_t xaya, xbyb, xcyc, xdyd;
+
+  /* input is be 1.31(q31) format for all FFT sizes */
+  /* Total process is divided into three stages */
+  /* process first stage, middle stages, & last stage */
+
+  /* Start of first stage process */
+
+  /* Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2U;
+  i0 = 0U;
+  ia1 = 0U;
+
+  j = n2;
+
+  do
+  {
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[2U * i0] >> 4U) + (pSrc[2U * i2] >> 4U);
+    /* xa - xc */
+    r2 = (pSrc[2U * i0] >> 4U) - (pSrc[2U * i2] >> 4U);
+
+    /* xb + xd */
+    t1 = (pSrc[2U * i1] >> 4U) + (pSrc[2U * i3] >> 4U);
+
+    /* ya + yc */
+    s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U);
+    /* ya - yc */
+    s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2U * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U);
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2U * i0) + 1U] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U);
+    /* xb - xd */
+    t2 = (pSrc[2U * i1] >> 4U) - (pSrc[2U * i3] >> 4U);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2U * ia1;
+    co2 = pCoef[ia2 * 2U];
+    si2 = pCoef[(ia2 * 2U) + 1U];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[2U * i1 + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U;
+
+    /* (xa - xc) - (yb - yd) */
+    r1 = r2 - t1;
+    /* (xa - xc) + (yb - yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb - xd) */
+    s1 = s2 + t2;
+    /* (ya - yc) - (xb - xd) */
+    s2 = s2 - t2;
+
+    co1 = pCoef[ia1 * 2U];
+    si1 = pCoef[(ia1 * 2U) + 1U];
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3U * ia1;
+    co3 = pCoef[ia3 * 2U];
+    si3 = pCoef[(ia3 * 2U) + 1U];
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1U;
+
+  } while (--j);
+
+  /* data is in 5.27(q27) format */
+  /* each stage provides two down scaling of the input */
+
+
+  /* Start of Middle stages process */
+
+  twidCoefModifier <<= 2U;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4U; k > 4U; k >>= 2U)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2U;
+    ia1 = 0U;
+
+    for (j = 0; j <= (n2 - 1U); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2U];
+      si1 = pCoef[(ia1 * 2U) + 1U];
+      co2 = pCoef[ia2 * 2U];
+      si2 = pCoef[(ia2 * 2U) + 1U];
+      co3 = pCoef[ia3 * 2U];
+      si3 = pCoef[(ia3 * 2U) + 1U];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2U * i0] + pSrc[2U * i2];
+        /* xa - xc */
+        r2 = pSrc[2U * i0] - pSrc[2U * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U];
+        /* ya - yc */
+        s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U];
+
+        /* xb + xd */
+        t1 = pSrc[2U * i1] + pSrc[2U * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2U * i0] = (r1 + t1) >> 2U;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+        /* yb + yd */
+        t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U];
+        /* (xb - xd) */
+        t2 = pSrc[2U * i1] - pSrc[2U * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32U)) -
+                         ((int32_t) (((q63_t) s1 * si2) >> 32U))) >> 1U;
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2U * i1) + 1U] =
+          (((int32_t) (((q63_t) s1 * co2) >> 32U)) +
+           ((int32_t) (((q63_t) r1 * si2) >> 32U))) >> 1U;
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U;
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U;
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[(2U * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U;
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U;
+      }
+    }
+    twidCoefModifier <<= 2U;
+  }
+#else
+  uint32_t n1, n2, ia1, ia2, ia3, i0, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+  q31_t xa, xb, xc, xd;
+  q31_t ya, yb, yc, yd;
+  q31_t xa_out, xb_out, xc_out, xd_out;
+  q31_t ya_out, yb_out, yc_out, yd_out;
+
+  q31_t *ptr1;
+  q31_t *pSi0;
+  q31_t *pSi1;
+  q31_t *pSi2;
+  q31_t *pSi3;
+  q63_t xaya, xbyb, xcyc, xdyd;
+
+  /* input is be 1.31(q31) format for all FFT sizes */
+  /* Total process is divided into three stages */
+  /* process first stage, middle stages, & last stage */
+
+  /* Start of first stage process */
+
+  /* Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2U;
+
+  ia1 = 0U;
+
+  j = n2;
+
+  pSi0 = pSrc;
+  pSi1 = pSi0 + 2 * n2;
+  pSi2 = pSi1 + 2 * n2;
+  pSi3 = pSi2 + 2 * n2;
+
+  do
+  {
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSi0[0] >> 4U) + (pSi2[0] >> 4U);
+    /* xa - xc */
+    r2 = (pSi0[0] >> 4U) - (pSi2[0] >> 4U);
+
+    /* xb + xd */
+    t1 = (pSi1[0] >> 4U) + (pSi3[0] >> 4U);
+
+    /* ya + yc */
+    s1 = (pSi0[1] >> 4U) + (pSi2[1] >> 4U);
+    /* ya - yc */
+    s2 = (pSi0[1] >> 4U) - (pSi2[1] >> 4U);
+
+    /* xa' = xa + xb + xc + xd */
+    *pSi0++ = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSi1[1] >> 4U) + (pSi3[1] >> 4U);
+    /* ya' = ya + yb + yc + yd */
+    *pSi0++ = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSi1[1] >> 4U) - (pSi3[1] >> 4U);
+    /* xb - xd */
+    t2 = (pSi1[0] >> 4U) - (pSi3[0] >> 4U);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2U * ia1;
+    co2 = pCoef[ia2 * 2U];
+    si2 = pCoef[(ia2 * 2U) + 1U];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    *pSi1++ = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    *pSi1++ = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U;
+
+    /* (xa - xc) - (yb - yd) */
+    r1 = r2 - t1;
+    /* (xa - xc) + (yb - yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb - xd) */
+    s1 = s2 + t2;
+    /* (ya - yc) - (xb - xd) */
+    s2 = s2 - t2;
+
+    co1 = pCoef[ia1 * 2U];
+    si1 = pCoef[(ia1 * 2U) + 1U];
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    *pSi2++ = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    *pSi2++ = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3U * ia1;
+    co3 = pCoef[ia3 * 2U];
+    si3 = pCoef[(ia3 * 2U) + 1U];
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    *pSi3++ = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    *pSi3++ = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+  } while (--j);
+
+  /* data is in 5.27(q27) format */
+  /* each stage provides two down scaling of the input */
+
+
+  /* Start of Middle stages process */
+
+  twidCoefModifier <<= 2U;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4U; k > 4U; k >>= 2U)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2U;
+    ia1 = 0U;
+
+    for (j = 0; j <= (n2 - 1U); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2U];
+      si1 = pCoef[(ia1 * 2U) + 1U];
+      co2 = pCoef[ia2 * 2U];
+      si2 = pCoef[(ia2 * 2U) + 1U];
+      co3 = pCoef[ia3 * 2U];
+      si3 = pCoef[(ia3 * 2U) + 1U];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      pSi0 = pSrc + 2 * j;
+      pSi1 = pSi0 + 2 * n2;
+      pSi2 = pSi1 + 2 * n2;
+      pSi3 = pSi2 + 2 * n2;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSi0[0] + pSi2[0];
+
+        /* xa - xc */
+        r2 = pSi0[0] - pSi2[0];
+
+
+        /* ya + yc */
+        s1 = pSi0[1] + pSi2[1];
+
+        /* ya - yc */
+        s2 = pSi0[1] - pSi2[1];
+
+
+        /* xb + xd */
+        t1 = pSi1[0] + pSi3[0];
+
+
+        /* xa' = xa + xb + xc + xd */
+        pSi0[0] = (r1 + t1) >> 2U;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+        /* yb + yd */
+        t2 = pSi1[1] + pSi3[1];
+
+        /* ya' = ya + yb + yc + yd */
+        pSi0[1] = (s1 + t2) >> 2U;
+        pSi0 += 2 * n1;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSi1[1] - pSi3[1];
+
+        /* (xb - xd) */
+        t2 = pSi1[0] - pSi3[0];
+
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSi1[0] = (((int32_t) (((q63_t) r1 * co2) >> 32U)) -
+                         ((int32_t) (((q63_t) s1 * si2) >> 32U))) >> 1U;
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSi1[1] =
+
+          (((int32_t) (((q63_t) s1 * co2) >> 32U)) +
+           ((int32_t) (((q63_t) r1 * si2) >> 32U))) >> 1U;
+        pSi1 += 2 * n1;
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSi2[0] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U;
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSi2[1] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U;
+        pSi2 += 2 * n1;
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSi3[0] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U;
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSi3[1] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U;
+        pSi3 += 2 * n1;
+      }
+    }
+    twidCoefModifier <<= 2U;
+  }
+#endif
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* Start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+  ptr1 = &pSrc[0];
+
+  /*  Calculations of last stage */
+  do
+  {
+#ifndef ARM_MATH_BIG_ENDIAN
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    xa = (q31_t) xaya;
+    ya = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    xb = (q31_t) xbyb;
+    yb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    xc = (q31_t) xcyc;
+    yc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    xd = (q31_t) xdyd;
+    yd = (q31_t) (xdyd >> 32);
+
+#else
+
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    ya = (q31_t) xaya;
+    xa = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    yb = (q31_t) xbyb;
+    xb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    yc = (q31_t) xcyc;
+    xc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    yd = (q31_t) xdyd;
+    xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+    /* xa' = xa + xb + xc + xd */
+    xa_out = xa + xb + xc + xd;
+
+    /* ya' = ya + yb + yc + yd */
+    ya_out = ya + yb + yc + yd;
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8U;
+
+    /* writing xa' and ya' */
+    *ptr1++ = xa_out;
+    *ptr1++ = ya_out;
+
+    xc_out = (xa - xb + xc - xd);
+    yc_out = (ya - yb + yc - yd);
+
+    /* writing xc' and yc' */
+    *ptr1++ = xc_out;
+    *ptr1++ = yc_out;
+
+    xb_out = (xa - yb - xc + yd);
+    yb_out = (ya + xb - yc - xd);
+
+    /* writing xb' and yb' */
+    *ptr1++ = xb_out;
+    *ptr1++ = yb_out;
+
+    xd_out = (xa + yb - xc - yd);
+    yd_out = (ya - xb - yc + xd);
+
+    /* writing xd' and yd' */
+    *ptr1++ = xd_out;
+    *ptr1++ = yd_out;
+
+  } while (--j);
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+}
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c
new file mode 100644
index 0000000..69ed5a6
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c
@@ -0,0 +1,285 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_radix8_f32.c
+ * Description:  Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+
+/* ----------------------------------------------------------------------
+ * Internal helper function used by the FFTs
+ * -------------------------------------------------------------------- */
+
+/*
+* @brief  Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+* @param[in]      fftLen           length of the FFT.
+* @param[in]      *pCoef           points to the twiddle coefficient buffer.
+* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix8_butterfly_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+const float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+   uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7;
+   uint32_t i1, i2, i3, i4, i5, i6, i7, i8;
+   uint32_t id;
+   uint32_t n1, n2, j;
+
+   float32_t r1, r2, r3, r4, r5, r6, r7, r8;
+   float32_t t1, t2;
+   float32_t s1, s2, s3, s4, s5, s6, s7, s8;
+   float32_t p1, p2, p3, p4;
+   float32_t co2, co3, co4, co5, co6, co7, co8;
+   float32_t si2, si3, si4, si5, si6, si7, si8;
+   const float32_t C81 = 0.70710678118f;
+
+   n2 = fftLen;
+
+   do
+   {
+      n1 = n2;
+      n2 = n2 >> 3;
+      i1 = 0;
+
+      do
+      {
+         i2 = i1 + n2;
+         i3 = i2 + n2;
+         i4 = i3 + n2;
+         i5 = i4 + n2;
+         i6 = i5 + n2;
+         i7 = i6 + n2;
+         i8 = i7 + n2;
+         r1 = pSrc[2 * i1] + pSrc[2 * i5];
+         r5 = pSrc[2 * i1] - pSrc[2 * i5];
+         r2 = pSrc[2 * i2] + pSrc[2 * i6];
+         r6 = pSrc[2 * i2] - pSrc[2 * i6];
+         r3 = pSrc[2 * i3] + pSrc[2 * i7];
+         r7 = pSrc[2 * i3] - pSrc[2 * i7];
+         r4 = pSrc[2 * i4] + pSrc[2 * i8];
+         r8 = pSrc[2 * i4] - pSrc[2 * i8];
+         t1 = r1 - r3;
+         r1 = r1 + r3;
+         r3 = r2 - r4;
+         r2 = r2 + r4;
+         pSrc[2 * i1] = r1 + r2;
+         pSrc[2 * i5] = r1 - r2;
+         r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+         s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+         r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+         s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+         s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+         s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+         r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+         s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+         t2 = r1 - s3;
+         r1 = r1 + s3;
+         s3 = r2 - r4;
+         r2 = r2 + r4;
+         pSrc[2 * i1 + 1] = r1 + r2;
+         pSrc[2 * i5 + 1] = r1 - r2;
+         pSrc[2 * i3]     = t1 + s3;
+         pSrc[2 * i7]     = t1 - s3;
+         pSrc[2 * i3 + 1] = t2 - r3;
+         pSrc[2 * i7 + 1] = t2 + r3;
+         r1 = (r6 - r8) * C81;
+         r6 = (r6 + r8) * C81;
+         r2 = (s6 - s8) * C81;
+         s6 = (s6 + s8) * C81;
+         t1 = r5 - r1;
+         r5 = r5 + r1;
+         r8 = r7 - r6;
+         r7 = r7 + r6;
+         t2 = s5 - r2;
+         s5 = s5 + r2;
+         s8 = s7 - s6;
+         s7 = s7 + s6;
+         pSrc[2 * i2]     = r5 + s7;
+         pSrc[2 * i8]     = r5 - s7;
+         pSrc[2 * i6]     = t1 + s8;
+         pSrc[2 * i4]     = t1 - s8;
+         pSrc[2 * i2 + 1] = s5 - r7;
+         pSrc[2 * i8 + 1] = s5 + r7;
+         pSrc[2 * i6 + 1] = t2 - r8;
+         pSrc[2 * i4 + 1] = t2 + r8;
+
+         i1 += n1;
+      } while (i1 < fftLen);
+
+      if (n2 < 8)
+         break;
+
+      ia1 = 0;
+      j = 1;
+
+      do
+      {
+         /*  index calculation for the coefficients */
+         id  = ia1 + twidCoefModifier;
+         ia1 = id;
+         ia2 = ia1 + id;
+         ia3 = ia2 + id;
+         ia4 = ia3 + id;
+         ia5 = ia4 + id;
+         ia6 = ia5 + id;
+         ia7 = ia6 + id;
+
+         co2 = pCoef[2 * ia1];
+         co3 = pCoef[2 * ia2];
+         co4 = pCoef[2 * ia3];
+         co5 = pCoef[2 * ia4];
+         co6 = pCoef[2 * ia5];
+         co7 = pCoef[2 * ia6];
+         co8 = pCoef[2 * ia7];
+         si2 = pCoef[2 * ia1 + 1];
+         si3 = pCoef[2 * ia2 + 1];
+         si4 = pCoef[2 * ia3 + 1];
+         si5 = pCoef[2 * ia4 + 1];
+         si6 = pCoef[2 * ia5 + 1];
+         si7 = pCoef[2 * ia6 + 1];
+         si8 = pCoef[2 * ia7 + 1];
+
+         i1 = j;
+
+         do
+         {
+            /*  index calculation for the input */
+            i2 = i1 + n2;
+            i3 = i2 + n2;
+            i4 = i3 + n2;
+            i5 = i4 + n2;
+            i6 = i5 + n2;
+            i7 = i6 + n2;
+            i8 = i7 + n2;
+            r1 = pSrc[2 * i1] + pSrc[2 * i5];
+            r5 = pSrc[2 * i1] - pSrc[2 * i5];
+            r2 = pSrc[2 * i2] + pSrc[2 * i6];
+            r6 = pSrc[2 * i2] - pSrc[2 * i6];
+            r3 = pSrc[2 * i3] + pSrc[2 * i7];
+            r7 = pSrc[2 * i3] - pSrc[2 * i7];
+            r4 = pSrc[2 * i4] + pSrc[2 * i8];
+            r8 = pSrc[2 * i4] - pSrc[2 * i8];
+            t1 = r1 - r3;
+            r1 = r1 + r3;
+            r3 = r2 - r4;
+            r2 = r2 + r4;
+            pSrc[2 * i1] = r1 + r2;
+            r2 = r1 - r2;
+            s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+            s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+            s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+            s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+            s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+            s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+            s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+            s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+            t2 = s1 - s3;
+            s1 = s1 + s3;
+            s3 = s2 - s4;
+            s2 = s2 + s4;
+            r1 = t1 + s3;
+            t1 = t1 - s3;
+            pSrc[2 * i1 + 1] = s1 + s2;
+            s2 = s1 - s2;
+            s1 = t2 - r3;
+            t2 = t2 + r3;
+            p1 = co5 * r2;
+            p2 = si5 * s2;
+            p3 = co5 * s2;
+            p4 = si5 * r2;
+            pSrc[2 * i5]     = p1 + p2;
+            pSrc[2 * i5 + 1] = p3 - p4;
+            p1 = co3 * r1;
+            p2 = si3 * s1;
+            p3 = co3 * s1;
+            p4 = si3 * r1;
+            pSrc[2 * i3]     = p1 + p2;
+            pSrc[2 * i3 + 1] = p3 - p4;
+            p1 = co7 * t1;
+            p2 = si7 * t2;
+            p3 = co7 * t2;
+            p4 = si7 * t1;
+            pSrc[2 * i7]     = p1 + p2;
+            pSrc[2 * i7 + 1] = p3 - p4;
+            r1 = (r6 - r8) * C81;
+            r6 = (r6 + r8) * C81;
+            s1 = (s6 - s8) * C81;
+            s6 = (s6 + s8) * C81;
+            t1 = r5 - r1;
+            r5 = r5 + r1;
+            r8 = r7 - r6;
+            r7 = r7 + r6;
+            t2 = s5 - s1;
+            s5 = s5 + s1;
+            s8 = s7 - s6;
+            s7 = s7 + s6;
+            r1 = r5 + s7;
+            r5 = r5 - s7;
+            r6 = t1 + s8;
+            t1 = t1 - s8;
+            s1 = s5 - r7;
+            s5 = s5 + r7;
+            s6 = t2 - r8;
+            t2 = t2 + r8;
+            p1 = co2 * r1;
+            p2 = si2 * s1;
+            p3 = co2 * s1;
+            p4 = si2 * r1;
+            pSrc[2 * i2]     = p1 + p2;
+            pSrc[2 * i2 + 1] = p3 - p4;
+            p1 = co8 * r5;
+            p2 = si8 * s5;
+            p3 = co8 * s5;
+            p4 = si8 * r5;
+            pSrc[2 * i8]     = p1 + p2;
+            pSrc[2 * i8 + 1] = p3 - p4;
+            p1 = co6 * r6;
+            p2 = si6 * s6;
+            p3 = co6 * s6;
+            p4 = si6 * r6;
+            pSrc[2 * i6]     = p1 + p2;
+            pSrc[2 * i6 + 1] = p3 - p4;
+            p1 = co4 * t1;
+            p2 = si4 * t2;
+            p3 = co4 * t2;
+            p4 = si4 * t1;
+            pSrc[2 * i4]     = p1 + p2;
+            pSrc[2 * i4 + 1] = p3 - p4;
+
+            i1 += n1;
+         } while (i1 < fftLen);
+
+         j++;
+      } while (j < n2);
+
+      twidCoefModifier <<= 3;
+   } while (n2 > 7);
+}
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c
new file mode 100644
index 0000000..ccb3c52
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c
@@ -0,0 +1,449 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_dct4_f32.c
+ * Description:  Processing function of DCT4 & IDCT4 F32
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @defgroup DCT4_IDCT4 DCT Type IV Functions
+ * Representation of signals by minimum number of values is important for storage and transmission.
+ * The possibility of large discontinuity between the beginning and end of a period of a signal
+ * in DFT can be avoided by extending the signal so that it is even-symmetric.
+ * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the
+ * spectrum and is very widely used in signal and image coding applications.
+ * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.
+ * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.
+ *
+ * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.
+ * Reordering of the input data makes the computation of DCT just a problem of
+ * computing the DFT of a real signal with a few additional operations.
+ * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.
+ *
+ * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.
+ * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.
+ * DCT2 implementation can be described in the following steps:
+ * - Re-ordering input
+ * - Calculating Real FFT
+ * - Multiplication of weights and Real FFT output and getting real part from the product.
+ *
+ * This process is explained by the block diagram below:
+ * \image html DCT4.gif "Discrete Cosine Transform - type-IV"
+ *
+ * \par Algorithm:
+ * The N-point type-IV DCT is defined as a real, linear transformation by the formula:
+ * \image html DCT4Equation.gif
+ * where k = 0,1,2,.....N-1
+ *\par
+ * Its inverse is defined as follows:
+ * \image html IDCT4Equation.gif
+ * where n = 0,1,2,.....N-1
+ *\par
+ * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).
+ * The symmetry of the transform matrix indicates that the fast algorithms for the forward
+ * and inverse transform computation are identical.
+ * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.
+ *
+ * \par Lengths supported by the transform:
+ *  As DCT4 internally uses Real FFT, it supports all the lengths 128, 512, 2048 and 8192.
+ * The library provides separate functions for Q15, Q31, and floating-point data types.
+ * \par Instance Structure
+ * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.
+ * A separate instance structure must be defined for each transform.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Manually initialize the instance structure as follows:
+ * 
+ *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ * 

+ * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;
+ * \c normalize is normalizing factor used and is equal to sqrt(2/N);
+ * \c pTwiddle points to the twiddle factor table;
+ * \c pCosFactor points to the cosFactor table;
+ * \c pRfft points to the real FFT instance;
+ * \c pCfft points to the complex FFT instance;
+ * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()
+ * and arm_rfft_f32() respectively for details regarding static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the DCT4 transform functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in]       *pState        points to state buffer.
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  float32_t *weights = S->pTwiddle;              /* Pointer to the Weights table */
+  float32_t *cosFact = S->pCosFactor;            /* Pointer to the cos factors table */
+  float32_t *pS1, *pS2, *pbuff;                  /* Temporary pointers for input buffer and pState buffer */
+  float32_t in;                                  /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+   * along with some pre-processing and post-processing.
+   * Computational procedure is explained as follows:
+   * (a) Pre-processing involves multiplying input with cos factor,
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+   *              where,
+   *                 r(n) -- output of preprocessing
+   *                 u(n) -- input to preprocessing(actual Source buffer)
+   * (b) Calculation of DCT2 using FFT is divided into three steps:
+   *                  Step1: Re-ordering of even and odd elements of input.
+   *                  Step2: Calculating FFT of the re-ordered input.
+   *                  Step3: Taking the real part of the product of FFT output and weights.
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+   *                        where,
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
+  arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------
+   * Step1: Re-ordering of even and odd elements as,
+   *             pState[i] =  pInlineBuffer[2*i] and
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1U);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2U;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+
+  /* ---------------------------------------------------------
+   *     Step2: Calculate RFFT for N-point input
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------
+	 *  Step3: Multiply the FFT output with the weights.
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1U) >> 2U;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1U) % 0x4U;
+
+  while (i > 0U)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2U;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+
+  /* ---------------------------------------------------------
+   *     Step2: Calculate RFFT for N-point input
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------
+	 *  Step3: Multiply the FFT output with the weights.
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1U);
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+   * @} end of DCT4_IDCT4 group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c
new file mode 100644
index 0000000..19b46f5
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c
@@ -0,0 +1,16513 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_dct4_init_f32.c
+ * Description:  Initialization function of DCT-4 & IDCT4 F32
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup DCT4_IDCT4
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4_Table DCT Type IV Tables
+ * @{
+ */
+
+/*
+* @brief  Weights Table
+*/
+
+/**
+ * \par
+ * Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))

+ * \par
+ * C command to generate the table
+ * 
+ * for(i = 0; i< N; i++)
+ * {
+ *    weights[2*i]= cos(i*c);
+ *    weights[(2*i)+1]= -sin(i * c);
+ * } 

+ * \par
+ * Where N is the Number of weights to be calculated and c is pi/(2*N)
+ * \par
+ * In the tables below the real and imaginary values are placed alternatively, hence the
+ * array length is 2*N.
+ */
+
+static const float32_t Weights_128[256] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
+  -0.012271538285719925f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,
+  -0.036807222941358832f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,
+  -0.061320736302208578f,
+  0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,
+  -0.085797312344439894f,
+  0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,
+  -0.110222207293883060f,
+  0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,
+  -0.134580708507126170f,
+  0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,
+  -0.158858143333861450f,
+  0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,
+  -0.183039887955140950f,
+  0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,
+  -0.207111376192218560f,
+  0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,
+  -0.231058108280671110f,
+  0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,
+  -0.254865659604514570f,
+  0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,
+  -0.278519689385053060f,
+  0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,
+  -0.302005949319228080f,
+  0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,
+  -0.325310292162262930f,
+  0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,
+  -0.348418680249434560f,
+  0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,
+  -0.371317193951837540f,
+  0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,
+  -0.393992040061048100f,
+  0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,
+  -0.416429560097637150f,
+  0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,
+  -0.438616238538527660f,
+  0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,
+  -0.460538710958240010f,
+  0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,
+  -0.482183772079122720f,
+  0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,
+  -0.503538383725717580f,
+  0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,
+  -0.524589682678468950f,
+  0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,
+  -0.545324988422046460f,
+  0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,
+  -0.565731810783613120f,
+  0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,
+  -0.585797857456438860f,
+  0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,
+  -0.605511041404325550f,
+  0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,
+  -0.624859488142386340f,
+  0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,
+  -0.643831542889791390f,
+  0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f,
+  -0.662415777590171780f,
+  0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f,
+  -0.680600997795453020f,
+  0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f,
+  -0.698376249408972920f,
+  0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f,
+  -0.715730825283818590f,
+  0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f,
+  -0.732654271672412820f,
+  0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f,
+  -0.749136394523459260f,
+  0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f,
+  -0.765167265622458960f,
+  0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f,
+  -0.780737228572094380f,
+  0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f,
+  -0.795836904608883460f,
+  0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f,
+  -0.810457198252594770f,
+  0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f,
+  -0.824589302785025290f,
+  0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f,
+  -0.838224705554837970f,
+  0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f,
+  -0.851355193105265200f,
+  0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f,
+  -0.863972856121586700f,
+  0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f,
+  -0.876070094195406600f,
+  0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f,
+  -0.887639620402853930f,
+  0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f,
+  -0.898674465693953820f,
+  0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f,
+  -0.909167983090522270f,
+  0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f,
+  -0.919113851690057770f,
+  0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f,
+  -0.928506080473215480f,
+  0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f,
+  -0.937339011912574960f,
+  0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f,
+  -0.945607325380521280f,
+  0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f,
+  -0.953306040354193750f,
+  0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f,
+  -0.960430519415565790f,
+  0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f,
+  -0.966976471044852070f,
+  0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f,
+  -0.972939952205560070f,
+  0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f,
+  -0.978317370719627650f,
+  0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f,
+  -0.983105487431216290f,
+  0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f,
+  -0.987301418157858430f,
+  0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f,
+  -0.990902635427780010f,
+  0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f,
+  -0.993906970002356060f,
+  0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f,
+  -0.996312612182778000f,
+  0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f,
+  -0.998118112900149180f,
+  0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f,
+  -0.999322384588349540f,
+  0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f,
+  -0.999924701839144500f
+};
+
+static const float32_t Weights_512[1024] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f,
+  -0.003067956762965976f,
+  0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f,
+  -0.009203754782059819f,
+  0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f,
+  -0.015339206284988100f,
+  0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f,
+  -0.021474080275469508f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f,
+  -0.027608145778965740f,
+  0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f,
+  -0.033741171851377580f,
+  0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f,
+  -0.039872927587739811f,
+  0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f,
+  -0.046003182130914623f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f,
+  -0.052131704680283324f,
+  0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f,
+  -0.058258264500435752f,
+  0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f,
+  -0.064382630929857465f,
+  0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f,
+  -0.070504573389613856f,
+  0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f,
+  -0.076623861392031492f,
+  0.996820299291165670f, -0.079682437971430126f, 0.996571145790554840f,
+  -0.082740264549375692f,
+  0.996312612182778000f, -0.085797312344439894f, 0.996044700901251970f,
+  -0.088853552582524600f,
+  0.995767414467659820f, -0.091908956497132724f, 0.995480755491926940f,
+  -0.094963495329638992f,
+  0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f,
+  -0.101069862754827820f,
+  0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f,
+  -0.107172424956808840f,
+  0.993906970002356060f, -0.110222207293883060f, 0.993564135520595300f,
+  -0.113270952177564350f,
+  0.993211949234794500f, -0.116318630911904750f, 0.992850414459865100f,
+  -0.119365214810991350f,
+  0.992479534598709970f, -0.122410675199216200f, 0.992099313142191800f,
+  -0.125454983411546230f,
+  0.991709753669099530f, -0.128498110793793170f, 0.991310859846115440f,
+  -0.131540028702883120f,
+  0.990902635427780010f, -0.134580708507126170f, 0.990485084256457090f,
+  -0.137620121586486040f,
+  0.990058210262297120f, -0.140658239332849210f, 0.989622017463200890f,
+  -0.143695033150294470f,
+  0.989176509964781010f, -0.146730474455361750f, 0.988721691960323780f,
+  -0.149764534677321510f,
+  0.988257567730749460f, -0.152797185258443440f, 0.987784141644572180f,
+  -0.155828397654265230f,
+  0.987301418157858430f, -0.158858143333861450f, 0.986809401814185530f,
+  -0.161886393780111830f,
+  0.986308097244598670f, -0.164913120489969890f, 0.985797509167567480f,
+  -0.167938294974731170f,
+  0.985277642388941220f, -0.170961888760301220f, 0.984748501801904210f,
+  -0.173983873387463820f,
+  0.984210092386929030f, -0.177004220412148750f, 0.983662419211730250f,
+  -0.180022901405699510f,
+  0.983105487431216290f, -0.183039887955140950f, 0.982539302287441240f,
+  -0.186055151663446630f,
+  0.981963869109555240f, -0.189068664149806190f, 0.981379193313754560f,
+  -0.192080397049892440f,
+  0.980785280403230430f, -0.195090322016128250f, 0.980182135968117430f,
+  -0.198098410717953560f,
+  0.979569765685440520f, -0.201104634842091900f, 0.978948175319062200f,
+  -0.204108966092816870f,
+  0.978317370719627650f, -0.207111376192218560f, 0.977677357824509930f,
+  -0.210111836880469610f,
+  0.977028142657754390f, -0.213110319916091360f, 0.976369731330021140f,
+  -0.216106797076219520f,
+  0.975702130038528570f, -0.219101240156869800f, 0.975025345066994120f,
+  -0.222093620973203510f,
+  0.974339382785575860f, -0.225083911359792830f, 0.973644249650811980f,
+  -0.228072083170885730f,
+  0.972939952205560180f, -0.231058108280671110f, 0.972226497078936270f,
+  -0.234041958583543430f,
+  0.971503890986251780f, -0.237023605994367200f, 0.970772140728950350f,
+  -0.240003022448741500f,
+  0.970031253194543970f, -0.242980179903263870f, 0.969281235356548530f,
+  -0.245955050335794590f,
+  0.968522094274417380f, -0.248927605745720150f, 0.967753837093475510f,
+  -0.251897818154216970f,
+  0.966976471044852070f, -0.254865659604514570f, 0.966190003445412500f,
+  -0.257831102162158990f,
+  0.965394441697689400f, -0.260794117915275510f, 0.964589793289812760f,
+  -0.263754678974831350f,
+  0.963776065795439840f, -0.266712757474898370f, 0.962953266873683880f,
+  -0.269668325572915090f,
+  0.962121404269041580f, -0.272621355449948980f, 0.961280485811320640f,
+  -0.275571819310958140f,
+  0.960430519415565790f, -0.278519689385053060f, 0.959571513081984520f,
+  -0.281464937925757940f,
+  0.958703474895871600f, -0.284407537211271880f, 0.957826413027532910f,
+  -0.287347459544729510f,
+  0.956940335732208820f, -0.290284677254462330f, 0.956045251349996410f,
+  -0.293219162694258630f,
+  0.955141168305770780f, -0.296150888243623790f, 0.954228095109105670f,
+  -0.299079826308040480f,
+  0.953306040354193860f, -0.302005949319228080f, 0.952375012719765880f,
+  -0.304929229735402370f,
+  0.951435020969008340f, -0.307849640041534870f, 0.950486073949481700f,
+  -0.310767152749611470f,
+  0.949528180593036670f, -0.313681740398891520f, 0.948561349915730270f,
+  -0.316593375556165850f,
+  0.947585591017741090f, -0.319502030816015690f, 0.946600913083283530f,
+  -0.322407678801069850f,
+  0.945607325380521280f, -0.325310292162262930f, 0.944604837261480260f,
+  -0.328209843579092500f,
+  0.943593458161960390f, -0.331106305759876430f, 0.942573197601446870f,
+  -0.333999651442009380f,
+  0.941544065183020810f, -0.336889853392220050f, 0.940506070593268300f,
+  -0.339776884406826850f,
+  0.939459223602189920f, -0.342660717311994380f, 0.938403534063108060f,
+  -0.345541324963989090f,
+  0.937339011912574960f, -0.348418680249434560f, 0.936265667170278260f,
+  -0.351292756085567090f,
+  0.935183509938947610f, -0.354163525420490340f, 0.934092550404258980f,
+  -0.357030961233429980f,
+  0.932992798834738960f, -0.359895036534988110f, 0.931884265581668150f,
+  -0.362755724367397230f,
+  0.930766961078983710f, -0.365612997804773850f, 0.929640895843181330f,
+  -0.368466829953372320f,
+  0.928506080473215590f, -0.371317193951837540f, 0.927362525650401110f,
+  -0.374164062971457930f,
+  0.926210242138311380f, -0.377007410216418260f, 0.925049240782677580f,
+  -0.379847208924051160f,
+  0.923879532511286740f, -0.382683432365089780f, 0.922701128333878630f,
+  -0.385516053843918850f,
+  0.921514039342042010f, -0.388345046698826250f, 0.920318276709110590f,
+  -0.391170384302253870f,
+  0.919113851690057770f, -0.393992040061048100f, 0.917900775621390500f,
+  -0.396809987416710310f,
+  0.916679059921042700f, -0.399624199845646790f, 0.915448716088267830f,
+  -0.402434650859418430f,
+  0.914209755703530690f, -0.405241314004989860f, 0.912962190428398210f,
+  -0.408044162864978690f,
+  0.911706032005429880f, -0.410843171057903910f, 0.910441292258067250f,
+  -0.413638312238434500f,
+  0.909167983090522380f, -0.416429560097637150f, 0.907886116487666260f,
+  -0.419216888363223910f,
+  0.906595704514915330f, -0.422000270799799680f, 0.905296759318118820f,
+  -0.424779681209108810f,
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+  -0.996571145790554840f,
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+  -0.997060070339482960f,
+  0.073564563599667454f, -0.997290456678690210f, 0.070504573389614009f,
+  -0.997511456140303450f,
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+  -0.997925286198596000f,
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+  -0.998301544933892890f,
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+  -0.998640218180265270f,
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+  -0.998941293186856870f,
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+  -0.999204758618363890f,
+  0.036807222941358991f, -0.999322384588349540f, 0.033741171851377642f,
+  -0.999430604555461730f,
+  0.030674803176636581f, -0.999529417501093140f, 0.027608145778965820f,
+  -0.999618822495178640f,
+  0.024541228522912264f, -0.999698818696204250f, 0.021474080275469605f,
+  -0.999769405351215280f,
+  0.018406729905804820f, -0.999830581795823400f, 0.015339206284988220f,
+  -0.999882347454212560f,
+  0.012271538285719944f, -0.999924701839144500f, 0.009203754782059960f,
+  -0.999957644551963900f,
+  0.006135884649154515f, -0.999981175282601110f, 0.003067956762966138f,
+  -0.999995293809576190f
+};
+
+static const float32_t Weights_2048[4096] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999999705862882230f,
+  -0.000766990318742704f,
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+  -0.002300969151425805f,
+  0.999995293809576190f, -0.003067956762965976f, 0.999992646580707190f,
+  -0.003834942569706228f,
+  0.999989411081928400f, -0.004601926120448571f, 0.999985587315143200f,
+  -0.005368906963996343f,
+  0.999981175282601110f, -0.006135884649154475f, 0.999976174986897610f,
+  -0.006902858724729756f,
+  0.999970586430974140f, -0.007669828739531097f, 0.999964409618118280f,
+  -0.008436794242369799f,
+  0.999957644551963900f, -0.009203754782059819f, 0.999950291236490480f,
+  -0.009970709907418031f,
+  0.999942349676023910f, -0.010737659167264491f, 0.999933819875236000f,
+  -0.011504602110422714f,
+  0.999924701839144500f, -0.012271538285719925f, 0.999914995573113470f,
+  -0.013038467241987334f,
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+  -0.014572301692779064f,
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+  -0.016106101853537287f,
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+  -0.017639864115082053f,
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+  -0.022240887414024961f,
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+  -0.054429407010919133f,
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+  -0.999964409618118280f,
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+  -0.999976174986897610f,
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+  -0.999985587315143200f,
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+  -0.999997352766978210f,
+  0.001533980186284766f, -0.999998823451701880f, 0.000766990318742846f,
+  -0.999999705862882230f
+};
+
+static const float32_t Weights_8192[16384] = {
+  1.000000000000000000f, -0.000000000000000000f, 0.999999981616429330f,
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+    -0.000958737845553301f,
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+    -0.001342232786374338f,
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+    -0.001725727529795126f,
+  0.999998161643486980f, -0.001917474809855419f, 0.999997775588762350f,
+    -0.002109222019415644f,
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+    -0.002492716198835908f,
+  0.999996396822294350f, -0.002684463154595962f, 0.999995863699429940f,
+    -0.002876210011655979f,
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+    -0.003259703401475973f,
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+    -0.003643196311896068f,
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+    -0.011696336806357838f,
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+    -0.013230198300209835f,
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+    -0.013613658950295740f,
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+    -0.013997117598240367f,
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+    -0.014380574187649006f,
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+    -0.014764028662127246f,
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+    -0.019365296864179156f,
+  0.999808743426610520f, -0.019557008148029083f, 0.999804975037232870f,
+    -0.019748718712823729f,
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+    -0.020132137657052594f,
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+    -0.020898966606708137f,
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+    -0.021282376499358387f,
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+    -0.021665783262040078f,
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+    -0.024732917918276223f,
+  0.999689333741033640f, -0.024924606404281468f, 0.999684536129782140f,
+    -0.025116293973880186f,
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+    -0.027033117717008431f,
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+  0.017639864115082195f, -0.999844405492175240f, 0.017448146028360704f,
+    -0.999847769513025900f,
+  0.017256427300120978f, -0.999851096772332190f, 0.017064707937411529f,
+    -0.999854387269971890f,
+  0.016872987947281773f, -0.999857641005823860f, 0.016681267336780482f,
+    -0.999860857979768540f,
+  0.016489546112956454f, -0.999864038191687680f, 0.016297824282859176f,
+    -0.999867181641464380f,
+  0.016106101853537263f, -0.999870288328982950f, 0.015914378832040249f,
+    -0.999873358254129260f,
+  0.015722655225417017f, -0.999876391416790410f, 0.015530931040716478f,
+    -0.999879387816854930f,
+  0.015339206284988220f, -0.999882347454212560f, 0.015147480965280975f,
+    -0.999885270328754520f,
+  0.014955755088644378f, -0.999888156440373320f, 0.014764028662127416f,
+    -0.999891005788962950f,
+  0.014572301692779104f, -0.999893818374418490f, 0.014380574187649138f,
+    -0.999896594196636680f,
+  0.014188846153786343f, -0.999899333255515390f, 0.013997117598240459f,
+    -0.999902035550953920f,
+  0.013805388528060349f, -0.999904701082852900f, 0.013613658950295789f,
+    -0.999907329851114300f,
+  0.013421928871995907f, -0.999909921855641540f, 0.013230198300209845f,
+    -0.999912477096339240f,
+  0.013038467241987433f, -0.999914995573113470f, 0.012846735704377631f,
+    -0.999917477285871770f,
+  0.012655003694430301f, -0.999919922234522750f, 0.012463271219194662f,
+    -0.999922330418976490f,
+  0.012271538285719944f, -0.999924701839144500f, 0.012079804901056066f,
+    -0.999927036494939640f,
+  0.011888071072252072f, -0.999929334386276070f, 0.011696336806357907f,
+    -0.999931595513069200f,
+  0.011504602110422875f, -0.999933819875236000f, 0.011312866991496287f,
+    -0.999936007472694620f,
+  0.011121131456628141f, -0.999938158305364590f, 0.010929395512867561f,
+    -0.999940272373166960f,
+  0.010737659167264572f, -0.999942349676023910f, 0.010545922426868548f,
+    -0.999944390213859060f,
+  0.010354185298728884f, -0.999946393986597460f, 0.010162447789895645f,
+    -0.999948360994165400f,
+  0.009970709907418029f, -0.999950291236490480f, 0.009778971658346134f,
+    -0.999952184713501780f,
+  0.009587233049729183f, -0.999954041425129780f, 0.009395494088617302f,
+    -0.999955861371306100f,
+  0.009203754782059960f, -0.999957644551963900f, 0.009012015137106642f,
+    -0.999959390967037450f,
+  0.008820275160807512f, -0.999961100616462820f, 0.008628534860211857f,
+    -0.999962773500176930f,
+  0.008436794242369860f, -0.999964409618118280f, 0.008245053314331058f,
+    -0.999966008970226920f,
+  0.008053312083144991f, -0.999967571556443780f, 0.007861570555861883f,
+    -0.999969097376711580f,
+  0.007669828739531077f, -0.999970586430974140f, 0.007478086641202815f,
+    -0.999972038719176730f,
+  0.007286344267926684f, -0.999973454241265940f, 0.007094601626752279f,
+    -0.999974832997189810f,
+  0.006902858724729877f, -0.999976174986897610f, 0.006711115568908869f,
+    -0.999977480210339940f,
+  0.006519372166339549f, -0.999978748667468830f, 0.006327628524071549f,
+    -0.999979980358237650f,
+  0.006135884649154515f, -0.999981175282601110f, 0.005944140548638765f,
+    -0.999982333440515350f,
+  0.005752396229573737f, -0.999983454831937730f, 0.005560651699009764f,
+    -0.999984539456826970f,
+  0.005368906963996303f, -0.999985587315143200f, 0.005177162031583702f,
+    -0.999986598406848000f,
+  0.004985416908821652f, -0.999987572731904080f, 0.004793671602759852f,
+    -0.999988510290275690f,
+  0.004601926120448672f, -0.999989411081928400f, 0.004410180468937601f,
+    -0.999990275106828920f,
+  0.004218434655277024f, -0.999991102364945590f, 0.004026688686516664f,
+    -0.999991892856248010f,
+  0.003834942569706248f, -0.999992646580707190f, 0.003643196311896179f,
+    -0.999993363538295150f,
+  0.003451449920135975f, -0.999994043728985820f, 0.003259703401476044f,
+    -0.999994687152754080f,
+  0.003067956762966138f, -0.999995293809576190f, 0.002876210011656010f,
+    -0.999995863699429940f,
+  0.002684463154596083f, -0.999996396822294350f, 0.002492716198835898f,
+    -0.999996893178149880f,
+  0.002300969151425887f, -0.999997352766978210f, 0.002109222019415816f,
+    -0.999997775588762350f,
+  0.001917474809855460f, -0.999998161643486980f, 0.001725727529795258f,
+    -0.999998510931137790f,
+  0.001533980186284766f, -0.999998823451701880f, 0.001342232786374430f,
+    -0.999999099205167830f,
+  0.001150485337113809f, -0.999999338191525530f, 0.000958737845553352f,
+    -0.999999540410766110f,
+  0.000766990318742846f, -0.999999705862882230f, 0.000575242763732077f,
+    -0.999999834547867670f,
+  0.000383495187571497f, -0.999999926465717890f, 0.000191747597310674f,
+    -0.999999981616429330f
+};
+
+/**
+* \par
+* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))

+* \par
+* C command to generate the table
+* \par
+* 
 for(i = 0; i< N; i++)
+* {
+*    cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* } 

+* \par
+* where N is the number of factors to generate and c is pi/(2*N)
+*/
+static const float32_t cos_factors_128[128] = {
+  0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
+  0.999077727752645360f,
+  0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
+  0.995767414467659820f,
+  0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
+  0.990058210262297120f,
+  0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
+  0.981963869109555240f,
+  0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
+  0.971503890986251780f,
+  0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
+  0.958703474895871600f,
+  0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
+  0.943593458161960390f,
+  0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
+  0.926210242138311380f,
+  0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
+  0.906595704514915330f,
+  0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
+  0.884797098430937790f,
+  0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
+  0.860866938637767310f,
+  0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
+  0.834862874986380010f,
+  0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
+  0.806847553543799330f,
+  0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
+  0.776888465673232440f,
+  0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
+  0.745057785441466060f,
+  0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
+  0.711432195745216430f,
+  0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
+  0.676092703575316030f,
+  0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
+  0.639124444863775730f,
+  0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
+  0.600616479383868970f,
+  0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
+  0.560661576197336030f,
+  0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
+  0.519355990165589530f,
+  0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
+  0.476799230063322250f,
+  0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
+  0.433093818853152010f,
+  0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
+  0.388345046698826300f,
+  0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
+  0.342660717311994380f,
+  0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
+  0.296150888243623960f,
+  0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
+  0.248927605745720260f,
+  0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
+  0.201104634842091960f,
+  0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
+  0.152797185258443410f,
+  0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
+  0.104121633872054730f,
+  0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
+  0.055195244349690031f,
+  0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
+  0.006135884649154515f
+};
+
+static const float32_t cos_factors_512[512] = {
+  0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
+  0.999942349676023910f,
+  0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
+  0.999735288260561680f,
+  0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
+  0.999377670388002850f,
+  0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
+  0.998869549914283560f,
+  0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
+  0.998211003360478190f,
+  0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
+  0.997402129901275300f,
+  0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
+  0.996443051350042630f,
+  0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,
+  0.995333912140482280f,
+  0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
+  0.994074879304879370f,
+  0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
+  0.992666142448948020f,
+  0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
+  0.991107913723276890f,
+  0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
+  0.989400427791380380f,
+  0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
+  0.987543941794359230f,
+  0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
+  0.985538735312176060f,
+  0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,
+  0.983385110321551180f,
+  0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,
+  0.981083391150486710f,
+  0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,
+  0.978633924429423210f,
+  0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,
+  0.976037079039039020f,
+  0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,
+  0.973293246054698250f,
+  0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,
+  0.970402838687555500f,
+  0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,
+  0.967366292222328510f,
+  0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,
+  0.964184063951745830f,
+  0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,
+  0.960856633107679660f,
+  0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,
+  0.957384500788975860f,
+  0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,
+  0.953768189885990330f,
+  0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,
+  0.950008245001843000f,
+  0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,
+  0.946105232370403450f,
+  0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,
+  0.942059739771017310f,
+  0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,
+  0.937872376439989890f,
+  0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,
+  0.933543772978836170f,
+  0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,
+  0.929074581259315860f,
+  0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,
+  0.924465474325262600f,
+  0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,
+  0.919717146291227360f,
+  0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,
+  0.914830312237946200f,
+  0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,
+  0.909805708104652220f,
+  0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,
+  0.904644090578246240f,
+  0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,
+  0.899346236979341570f,
+  0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,
+  0.893912945145203250f,
+  0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,
+  0.888345033309596350f,
+  0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,
+  0.882643339979562790f,
+  0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,
+  0.876808723809145650f,
+  0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,
+  0.870842063470078980f,
+  0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,
+  0.864744257519462380f,
+  0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,
+  0.858516224264442740f,
+  0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,
+  0.852158901623919830f,
+  0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,
+  0.845673246987299070f,
+  0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,
+  0.839060237070312740f,
+  0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,
+  0.832320867767929680f,
+  0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,
+  0.825456154004377550f,
+  0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,
+  0.818467129580298660f,
+  0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,
+  0.811354847017063730f,
+  0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,
+  0.804120377398265810f,
+  0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,
+  0.796764810208418830f,
+  0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,
+  0.789289253168885650f,
+  0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,
+  0.781694832071059390f,
+  0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,
+  0.773982690606822900f,
+  0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,
+  0.766153990196312920f,
+  0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,
+  0.758209909813015280f,
+  0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,
+  0.750151645806215070f,
+  0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,
+  0.741980411720831070f,
+  0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,
+  0.733697438114660370f,
+  0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,
+  0.725303972373060770f,
+  0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,
+  0.716801278521099540f,
+  0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,
+  0.708190637033195400f,
+  0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,
+  0.699473344640283770f,
+  0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f,
+  0.690650714134534720f,
+  0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,
+  0.681724074171649820f,
+  0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f,
+  0.672694769070772970f,
+  0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f,
+  0.663564158612039880f,
+  0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f,
+  0.654333617831800550f,
+  0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f,
+  0.645004536815544040f,
+  0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,
+  0.635578320488556230f,
+  0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,
+  0.626056388404343520f,
+  0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,
+  0.616440174530853650f,
+  0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,
+  0.606731127034524480f,
+  0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,
+  0.596930708062196500f,
+  0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,
+  0.587040393520918080f,
+  0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,
+  0.577061672855679550f,
+  0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f,
+  0.566996048825108680f,
+  0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,
+  0.556845037275160100f,
+  0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,
+  0.546610166910834860f,
+  0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,
+  0.536292979065963180f,
+  0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,
+  0.525895027471084740f,
+  0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,
+  0.515417878019463150f,
+  0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,
+  0.504863108531267480f,
+  0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,
+  0.494232308515959730f,
+  0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,
+  0.483527078932918740f,
+  0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,
+  0.472749031950342900f,
+  0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,
+  0.461899790702462840f,
+  0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f,
+  0.450980989045103810f,
+  0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f,
+  0.439994271309633260f,
+  0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f,
+  0.428941292055329550f,
+  0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f,
+  0.417823715820212380f,
+  0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f,
+  0.406643216870369140f,
+  0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,
+  0.395401478947816300f,
+  0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,
+  0.384100195016935040f,
+  0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,
+  0.372741067009515810f,
+  0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,
+  0.361325805568454340f,
+  0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,
+  0.349856129790135030f,
+  0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,
+  0.338333766965541290f,
+  0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,
+  0.326760452320131790f,
+  0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f,
+  0.315137928752522440f,
+  0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f,
+  0.303467946572011370f,
+  0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f,
+  0.291752263234989370f,
+  0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f,
+  0.279992643080273380f,
+  0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,
+  0.268190857063403180f,
+  0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,
+  0.256348682489942910f,
+  0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,
+  0.244467902747824210f,
+  0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,
+  0.232550307038775330f,
+  0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,
+  0.220597690108873650f,
+  0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,
+  0.208611851978263460f,
+  0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,
+  0.196594597670080220f,
+  0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,
+  0.184547736938619640f,
+  0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,
+  0.172473083996796030f,
+  0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,
+  0.160372457242928400f,
+  0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,
+  0.148247678986896200f,
+  0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,
+  0.136100575175706200f,
+  0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,
+  0.123932975118512200f,
+  0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,
+  0.111746711211126660f,
+  0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,
+  0.099543618660069444f,
+  0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,
+  0.087325535206192226f,
+  0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,
+  0.075094300847921291f,
+  0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,
+  0.062851757564161420f,
+  0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,
+  0.050599749036899337f,
+  0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,
+  0.038340120373552791f,
+  0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,
+  0.026074717829104040f,
+  0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,
+  0.013805388528060349f,
+  0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
+  0.001533980186284766f
+};
+
+static const float32_t cos_factors_2048[2048] = {
+  0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,
+  0.999996396822294350f,
+  0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
+  0.999983454831937730f,
+  0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
+  0.999961100616462820f,
+  0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
+  0.999929334386276070f,
+  0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,
+  0.999888156440373320f,
+  0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f,
+  0.999837567166337090f,
+  0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f,
+  0.999777567040332940f,
+  0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,
+  0.999708156627104880f,
+  0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,
+  0.999629336579970110f,
+  0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f,
+  0.999541107640812940f,
+  0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,
+  0.999443470640077770f,
+  0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,
+  0.999336426496761240f,
+  0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,
+  0.999219976218403530f,
+  0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f,
+  0.999094120901079070f,
+  0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f,
+  0.998958861729386080f,
+  0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f,
+  0.998814199976435390f,
+  0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f,
+  0.998660137003838490f,
+  0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,
+  0.998496674261694640f,
+  0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f,
+  0.998323813288577560f,
+  0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f,
+  0.998141555711520520f,
+  0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f,
+  0.997949903246001190f,
+  0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f,
+  0.997748857695925690f,
+  0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f,
+  0.997538420953611340f,
+  0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f,
+  0.997318594999768600f,
+  0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f,
+  0.997089381903483400f,
+  0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f,
+  0.996850783822196610f,
+  0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f,
+  0.996602803001684130f,
+  0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f,
+  0.996345441776035900f,
+  0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f,
+  0.996078702567633980f,
+  0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f,
+  0.995802587887129160f,
+  0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f,
+  0.995517100333418110f,
+  0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f,
+  0.995222242593618360f,
+  0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f,
+  0.994918017443043200f,
+  0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f,
+  0.994604427745175660f,
+  0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f,
+  0.994281476451641550f,
+  0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f,
+  0.993949166602181130f,
+  0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f,
+  0.993607501324621610f,
+  0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f,
+  0.993256483834846440f,
+  0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f,
+  0.992896117436765980f,
+  0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f,
+  0.992526405522286100f,
+  0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f,
+  0.992147351571276090f,
+  0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f,
+  0.991758959151536110f,
+  0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f,
+  0.991361231918763460f,
+  0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f,
+  0.990954173616518500f,
+  0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f,
+  0.990537788076188750f,
+  0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f,
+  0.990112079216953770f,
+  0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f,
+  0.989677051045747210f,
+  0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f,
+  0.989232707657220050f,
+  0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f,
+  0.988779053233701520f,
+  0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f,
+  0.988316092045159690f,
+  0.988198898074717610f, 0.988081122772324070f, 0.987962766207263420f,
+  0.987843828449161740f,
+  0.987724309567986960f, 0.987604209634049160f, 0.987483528717999710f,
+  0.987362266890832400f,
+  0.987240424223882250f, 0.987118000788826280f, 0.986994996657682980f,
+  0.986871411902812470f,
+  0.986747246596916590f, 0.986622500813038480f, 0.986497174624562880f,
+  0.986371268105216030f,
+  0.986244781329065460f, 0.986117714370520090f, 0.985990067304330140f,
+  0.985861840205586980f,
+  0.985733033149723490f, 0.985603646212513400f, 0.985473679470071810f,
+  0.985343132998854790f,
+  0.985212006875659350f, 0.985080301177623800f, 0.984948015982227030f,
+  0.984815151367289140f,
+  0.984681707410970940f, 0.984547684191773960f, 0.984413081788540700f,
+  0.984277900280454370f,
+  0.984142139747038570f, 0.984005800268157870f, 0.983868881924017220f,
+  0.983731384795162090f,
+  0.983593308962478650f, 0.983454654507193270f, 0.983315421510872810f,
+  0.983175610055424420f,
+  0.983035220223095640f, 0.982894252096474070f, 0.982752705758487830f,
+  0.982610581292404750f,
+  0.982467878781833170f, 0.982324598310721280f, 0.982180739963357090f,
+  0.982036303824369020f,
+  0.981891289978725100f, 0.981745698511732990f, 0.981599529509040720f,
+  0.981452783056635520f,
+  0.981305459240844670f, 0.981157558148334830f, 0.981009079866112630f,
+  0.980860024481523870f,
+  0.980710392082253970f, 0.980560182756327840f, 0.980409396592109910f,
+  0.980258033678303550f,
+  0.980106094103951770f, 0.979953577958436740f, 0.979800485331479790f,
+  0.979646816313141210f,
+  0.979492570993820810f, 0.979337749464256780f, 0.979182351815526930f,
+  0.979026378139047580f,
+  0.978869828526574120f, 0.978712703070200420f, 0.978555001862359550f,
+  0.978396724995823090f,
+  0.978237872563701090f, 0.978078444659442380f, 0.977918441376834370f,
+  0.977757862810002760f,
+  0.977596709053411890f, 0.977434980201864260f, 0.977272676350500860f,
+  0.977109797594800880f,
+  0.976946344030581670f, 0.976782315753998650f, 0.976617712861545640f,
+  0.976452535450054060f,
+  0.976286783616693630f, 0.976120457458971910f, 0.975953557074734300f,
+  0.975786082562163930f,
+  0.975618034019781750f, 0.975449411546446380f, 0.975280215241354220f,
+  0.975110445204038890f,
+  0.974940101534371830f, 0.974769184332561770f, 0.974597693699155050f,
+  0.974425629735034990f,
+  0.974252992541422500f, 0.974079782219875680f, 0.973905998872289570f,
+  0.973731642600896400f,
+  0.973556713508265560f, 0.973381211697303290f, 0.973205137271252800f,
+  0.973028490333694210f,
+  0.972851270988544180f, 0.972673479340056430f, 0.972495115492821190f,
+  0.972316179551765300f,
+  0.972136671622152230f, 0.971956591809581720f, 0.971775940219990140f,
+  0.971594716959650160f,
+  0.971412922135170940f, 0.971230555853497380f, 0.971047618221911100f,
+  0.970864109348029470f,
+  0.970680029339806130f, 0.970495378305530560f, 0.970310156353828110f,
+  0.970124363593660280f,
+  0.969938000134323960f, 0.969751066085452140f, 0.969563561557013180f,
+  0.969375486659311280f,
+  0.969186841502985950f, 0.968997626199012420f, 0.968807840858700970f,
+  0.968617485593697540f,
+  0.968426560515983190f, 0.968235065737874320f, 0.968043001372022260f,
+  0.967850367531413620f,
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+  0.394344486828079650f,
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+  0.391523293167972350f,
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+  0.385869876937555310f,
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+  0.383037707579352130f,
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+  0.380201932924366050f,
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+  0.374519674523293210f,
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+  0.371673244260786630f,
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+  0.368823315668153960f,
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+  0.365969915570008910f,
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+  0.360252808318756830f,
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+  0.357389154977241000f,
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+  0.354522137752887430f,
+  0.353804861001772160f, 0.353087376116372530f, 0.352369683518766630f,
+  0.351651783631154680f,
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+  0.348778119628908420f,
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+  0.345901172794169100f,
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+  0.343020970205855540f,
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+  0.340137538973531880f,
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+  0.337250906237150650f,
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+  0.334361099166798900f,
+  0.333638154596370920f, 0.332915013755212650f, 0.332191677068729320f,
+  0.331468144962440920f,
+  0.330744417861982890f, 0.330020496193105530f, 0.329296380381672800f,
+  0.328572070853663690f,
+  0.327847568035170960f, 0.327122872352400510f, 0.326397984231672660f,
+  0.325672904099419900f,
+  0.324947632382188430f, 0.324222169506637130f, 0.323496515899536760f,
+  0.322770671987770710f,
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+  0.319865401835630610f,
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+  0.316957120988508150f,
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+  0.314045856820250820f,
+  0.313317577844809070f, 0.312589114552708660f, 0.311860467372486130f,
+  0.311131636732785270f,
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+  0.308214488155861220f,
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+  0.305294438546791720f,
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+  0.302371515390196130f,
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+  0.299445746197739950f,
+  0.298713862433100390f, 0.297981802942791920f, 0.297249568157465890f,
+  0.296517158507877410f,
+  0.295784574424884370f, 0.295051816339446720f, 0.294318884682627570f,
+  0.293585779885591310f,
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+  0.290651637922133220f,
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+  0.287714760234765280f,
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+  0.272990304331329980f,
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+  0.270037593686750510f,
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+  0.267082341345496350f,
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+  0.261164322860466590f,
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+  0.258201612419334870f,
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+  0.255236471686291820f,
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+  0.252268928570370810f,
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+  0.249299011003218300f,
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+  0.246326746938829060f,
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+  0.243352164353284880f,
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+  0.240375291244489500f,
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+  0.237396155631906550f,
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+  0.234414785556295250f,
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+  0.231431209079445730f,
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+  0.228445454283916550f,
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+  0.225457549272768540f,
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+  0.222467522169301990f,
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+  0.216481214278216900f,
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+  0.213484989836008080f,
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+  0.210486755991769890f,
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+  0.207486540966020700f,
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+  0.204484372997927180f,
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+  0.201480280345037820f,
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+  0.198474291283016360f,
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+  0.195466434105377090f,
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+  0.192456737123216840f,
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+  0.186431937076041640f,
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+  0.183416890718739230f,
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+  0.180400117971807270f,
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+  0.177381647230260200f,
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+  0.174361506905093830f,
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+  0.171339725423019260f,
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+  0.168316331226194910f,
+  0.167560234024823590f, 0.166804038252083870f, 0.166047744352825850f,
+  0.165291352771957970f,
+  0.164534863954446110f, 0.163778278345312690f, 0.163021596389637810f,
+  0.162264818532558110f,
+  0.161507945219266150f, 0.160750976895011390f, 0.159993914005098350f,
+  0.159236756994887850f,
+  0.158479506309796100f, 0.157722162395293690f, 0.156964725696906750f,
+  0.156207196660216040f,
+  0.155449575730855880f, 0.154691863354515400f, 0.153934059976937460f,
+  0.153176166043917870f,
+  0.152418182001306500f, 0.151660108295005400f, 0.150901945370970040f,
+  0.150143693675208330f,
+  0.149385353653779810f, 0.148626925752796540f, 0.147868410418422360f,
+  0.147109808096871850f,
+  0.146351119234411440f, 0.145592344277358450f, 0.144833483672080240f,
+  0.144074537864995330f,
+  0.143315507302571590f, 0.142556392431327340f, 0.141797193697830530f,
+  0.141037911548697770f,
+  0.140278546430595420f, 0.139519098790238600f, 0.138759569074390380f,
+  0.137999957729862760f,
+  0.137240265203515700f, 0.136480491942256310f, 0.135720638393040080f,
+  0.134960705002868830f,
+  0.134200692218792020f, 0.133440600487905820f, 0.132680430257352130f,
+  0.131920181974319760f,
+  0.131159856086043410f, 0.130399453039802740f, 0.129638973282923540f,
+  0.128878417262776660f,
+  0.128117785426777150f, 0.127357078222385570f, 0.126596296097105960f,
+  0.125835439498487020f,
+  0.125074508874121300f, 0.124313504671644300f, 0.123552427338735370f,
+  0.122791277323116900f,
+  0.122030055072553410f, 0.121268761034852550f, 0.120507395657864240f,
+  0.119745959389479630f,
+  0.118984452677632520f, 0.118222875970297250f, 0.117461229715489990f,
+  0.116699514361267840f,
+  0.115937730355727850f, 0.115175878147008180f, 0.114413958183287050f,
+  0.113651970912781920f,
+  0.112889916783750470f, 0.112127796244489750f, 0.111365609743335190f,
+  0.110603357728661910f,
+  0.109841040648882680f, 0.109078658952449240f, 0.108316213087851300f,
+  0.107553703503615710f,
+  0.106791130648307380f, 0.106028494970528530f, 0.105265796918917650f,
+  0.104503036942150550f,
+  0.103740215488939480f, 0.102977333008032250f, 0.102214389948213370f,
+  0.101451386758302160f,
+  0.100688323887153970f, 0.099925201783659226f, 0.099162020896742573f,
+  0.098398781675363881f,
+  0.097635484568517339f, 0.096872130025230527f, 0.096108718494565468f,
+  0.095345250425617742f,
+  0.094581726267515473f, 0.093818146469420494f, 0.093054511480527333f,
+  0.092290821750062355f,
+  0.091527077727284981f, 0.090763279861485704f, 0.089999428601987341f,
+  0.089235524398144139f,
+  0.088471567699340822f, 0.087707558954993645f, 0.086943498614549489f,
+  0.086179387127484922f,
+  0.085415224943307277f, 0.084651012511553700f, 0.083886750281790226f,
+  0.083122438703613077f,
+  0.082358078226646619f, 0.081593669300544638f, 0.080829212374989468f,
+  0.080064707899690932f,
+  0.079300156324387569f, 0.078535558098845590f, 0.077770913672857989f,
+  0.077006223496245585f,
+  0.076241488018856149f, 0.075476707690563416f, 0.074711882961268378f,
+  0.073947014280897269f,
+  0.073182102099402888f, 0.072417146866763538f, 0.071652149032982254f,
+  0.070887109048087787f,
+  0.070122027362133646f, 0.069356904425197236f, 0.068591740687380900f,
+  0.067826536598810966f,
+  0.067061292609636836f, 0.066296009170032283f, 0.065530686730193397f,
+  0.064765325740339871f,
+  0.063999926650714078f, 0.063234489911580136f, 0.062469015973224969f,
+  0.061703505285957416f,
+  0.060937958300107238f, 0.060172375466026218f, 0.059406757234087247f,
+  0.058641104054683348f,
+  0.057875416378229017f, 0.057109694655158132f, 0.056343939335925283f,
+  0.055578150871004817f,
+  0.054812329710889909f, 0.054046476306093640f, 0.053280591107148056f,
+  0.052514674564603257f,
+  0.051748727129028414f, 0.050982749251010900f, 0.050216741381155325f,
+  0.049450703970084824f,
+  0.048684637468439020f, 0.047918542326875327f, 0.047152418996068000f,
+  0.046386267926707213f,
+  0.045620089569500123f, 0.044853884375169933f, 0.044087652794454979f,
+  0.043321395278109784f,
+  0.042555112276904117f, 0.041788804241622082f, 0.041022471623063397f,
+  0.040256114872041358f,
+  0.039489734439384118f, 0.038723330775933762f, 0.037956904332545366f,
+  0.037190455560088091f,
+  0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f,
+  0.034124446197403423f,
+  0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f,
+  0.031058115642434700f,
+  0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f,
+  0.027991492756653365f,
+  0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f,
+  0.024924606404281485f,
+  0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f,
+  0.021857485452021874f,
+  0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f,
+  0.018790158768784596f,
+  0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f,
+  0.015722655225417017f,
+  0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f,
+  0.012655003694430301f,
+  0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f,
+  0.009587233049729183f,
+  0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f,
+  0.006519372166339549f,
+  0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f,
+  0.003451449920135975f,
+  0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,
+  0.000383495187571497f
+};
+
+static const float32_t cos_factors_8192[8192] = {
+  1.999999990808214700f, 1.999999917273932200f, 1.999999770205369800f,
+    1.999999549602533100f,
+  1.999999255465430200f, 1.999998887794072000f, 1.999998446588471700f,
+    1.999997931848645600f,
+  1.999997343574612800f, 1.999996681766395000f, 1.999995946424016200f,
+    1.999995137547503600f,
+  1.999994255136887000f, 1.999993299192198700f, 1.999992269713474200f,
+    1.999991166700750800f,
+  1.999989990154069600f, 1.999988740073473500f, 1.999987416459008600f,
+    1.999986019310723500f,
+  1.999984548628669600f, 1.999983004412901000f, 1.999981386663474400f,
+    1.999979695380449400f,
+  1.999977930563888100f, 1.999976092213855400f, 1.999974180330418700f,
+    1.999972194913648900f,
+  1.999970135963618400f, 1.999968003480403000f, 1.999965797464081200f,
+    1.999963517914734100f,
+  1.999961164832445800f, 1.999958738217302300f, 1.999956238069392900f,
+    1.999953664388809800f,
+  1.999951017175647600f, 1.999948296430003500f, 1.999945502151977600f,
+    1.999942634341672600f,
+  1.999939692999193900f, 1.999936678124649700f, 1.999933589718150700f,
+    1.999930427779810900f,
+  1.999927192309745900f, 1.999923883308075200f, 1.999920500774920300f,
+    1.999917044710405500f,
+  1.999913515114657900f, 1.999909911987807200f, 1.999906235329986100f,
+    1.999902485141329400f,
+  1.999898661421975400f, 1.999894764172064600f, 1.999890793391740000f,
+    1.999886749081147800f,
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+    0.167200278397683750f,
+  0.166818122599813570f, 0.166435960668517400f, 0.166053792617847200f,
+    0.165671618461853270f,
+  0.165289438214587970f, 0.164907251890102520f, 0.164525059502448390f,
+    0.164142861065678550f,
+  0.163760656593844480f, 0.163378446100999640f, 0.162996229601196390f,
+    0.162614007108487250f,
+  0.162231778636926370f, 0.161849544200566300f, 0.161467303813461580f,
+    0.161085057489665670f,
+  0.160702805243232240f, 0.160320547088216470f, 0.159938283038672050f,
+    0.159556013108654580f,
+  0.159173737312218650f, 0.158791455663418930f, 0.158409168176311760f,
+    0.158026874864951870f,
+  0.157644575743395960f, 0.157262270825699210f, 0.156879960125918730f,
+    0.156497643658110590f,
+  0.156115321436331000f, 0.155732993474637760f, 0.155350659787087090f,
+    0.154968320387737170f,
+  0.154585975290645110f, 0.154203624509868190f, 0.153821268059465250f,
+    0.153438905953493550f,
+  0.153056538206012340f, 0.152674164831079730f, 0.152291785842754070f,
+    0.151909401255095250f,
+  0.151527011082161540f, 0.151144615338013210f, 0.150762214036709470f,
+    0.150379807192309620f,
+  0.149997394818874590f, 0.149614976930463660f, 0.149232553541138180f,
+    0.148850124664957870f,
+  0.148467690315984390f, 0.148085250508278370f, 0.147702805255900570f,
+    0.147320354572913260f,
+  0.146937898473377210f, 0.146555436971355090f, 0.146172970080908520f,
+    0.145790497816099230f,
+  0.145408020190990560f, 0.145025537219644170f, 0.144643048916123810f,
+    0.144260555294492000f,
+  0.143878056368811510f, 0.143495552153146630f, 0.143113042661560050f,
+    0.142730527908116440f,
+  0.142348007906879320f, 0.141965482671912420f, 0.141582952217280980f,
+    0.141200416557048680f,
+  0.140817875705281120f, 0.140435329676042390f, 0.140052778483398480f,
+    0.139670222141414250f,
+  0.139287660664154770f, 0.138905094065686600f, 0.138522522360074780f,
+    0.138139945561386200f,
+  0.137757363683686740f, 0.137374776741042340f, 0.136992184747520560f,
+    0.136609587717187310f,
+  0.136226985664110460f, 0.135844378602356760f, 0.135461766545993150f,
+    0.135079149509088060f,
+  0.134696527505708320f, 0.134313900549922760f, 0.133931268655799020f,
+    0.133548631837404950f,
+  0.133165990108809860f, 0.132783343484081580f, 0.132400691977289760f,
+    0.132018035602502530f,
+  0.131635374373789940f, 0.131252708305220960f, 0.130870037410864640f,
+    0.130487361704791580f,
+  0.130104681201070800f, 0.129721995913773260f, 0.129339305856968730f,
+    0.128956611044727220f,
+  0.128573911491120210f, 0.128191207210217570f, 0.127808498216091110f,
+    0.127425784522811530f,
+  0.127043066144449680f, 0.126660343095077900f, 0.126277615388766920f,
+    0.125894883039589430f,
+  0.125512146061616980f, 0.125129404468921260f, 0.124746658275575490f,
+    0.124363907495651240f,
+  0.123981152143222060f, 0.123598392232359880f, 0.123215627777138580f,
+    0.122832858791630880f,
+  0.122450085289909640f, 0.122067307286049230f, 0.121684524794122440f,
+    0.121301737828203960f,
+  0.120918946402367330f, 0.120536150530686250f, 0.120153350227235940f,
+    0.119770545506089950f,
+  0.119387736381323830f, 0.119004922867011920f, 0.118622104977228730f,
+    0.118239282726050290f,
+  0.117856456127550970f, 0.117473625195807100f, 0.117090789944893860f,
+    0.116707950388886520f,
+  0.116325106541861910f, 0.115942258417895240f, 0.115559406031063570f,
+    0.115176549395442460f,
+  0.114793688525109290f, 0.114410823434140360f, 0.114027954136612060f,
+    0.113645080646602280f,
+  0.113262202978187320f, 0.112879321145445350f, 0.112496435162453430f,
+    0.112113545043288730f,
+  0.111730650802029900f, 0.111347752452754000f, 0.110964850009539970f,
+    0.110581943486465610f,
+  0.110199032897608850f, 0.109816118257049110f, 0.109433199578864170f,
+    0.109050276877133770f,
+  0.108667350165936400f, 0.108284419459350770f, 0.107901484771457020f,
+    0.107518546116333660f,
+  0.107135603508061170f, 0.106752656960718350f, 0.106369706488385940f,
+    0.105986752105143480f,
+  0.105603793825070680f, 0.105220831662248700f, 0.104837865630757090f,
+    0.104454895744677270f,
+  0.104071922018089540f, 0.103688944465074300f, 0.103305963099713400f,
+    0.102922977936087120f,
+  0.102539988988277600f, 0.102156996270365800f, 0.101773999796432830f,
+    0.101390999580561250f,
+  0.101007995636832020f, 0.100624987979327970f, 0.100241976622130760f,
+    0.099858961579322170f,
+  0.099475942864985456f, 0.099092920493202258f, 0.098709894478056073f,
+    0.098326864833628791f,
+  0.097943831574004214f, 0.097560794713264939f, 0.097177754265493674f,
+    0.096794710244774623f,
+  0.096411662665190329f, 0.096028611540825232f, 0.095645556885762609f,
+    0.095262498714085819f,
+  0.094879437039879722f, 0.094496371877227495f, 0.094113303240214247f,
+    0.093730231142923864f,
+  0.093347155599440373f, 0.092964076623849271f, 0.092580994230234359f,
+    0.092197908432681386f,
+  0.091814819245274432f, 0.091431726682099479f, 0.091048630757241303f,
+    0.090665531484784803f,
+  0.090282428878816323f, 0.089899322953420582f, 0.089516213722684160f,
+    0.089133101200692441f,
+  0.088749985401530951f, 0.088366866339286629f, 0.087983744028044805f,
+    0.087600618481892656f,
+  0.087217489714916191f, 0.086834357741201490f, 0.086451222574836131f,
+    0.086068084229906014f,
+  0.085684942720498897f, 0.085301798060701386f, 0.084918650264600160f,
+    0.084535499346283349f,
+  0.084152345319837438f, 0.083769188199350780f, 0.083386027998910095f,
+    0.083002864732603973f,
+  0.082619698414519799f, 0.082236529058745025f, 0.081853356679368619f,
+    0.081470181290477811f,
+  0.081087002906161790f, 0.080703821540508452f, 0.080320637207605849f,
+    0.079937449921543474f,
+  0.079554259696409127f, 0.079171066546292510f, 0.078787870485282088f,
+    0.078404671527466441f,
+  0.078021469686935602f, 0.077638264977777913f, 0.077255057414083589f,
+    0.076871847009941652f,
+  0.076488633779441206f, 0.076105417736672773f, 0.075722198895725248f,
+    0.075338977270689375f,
+  0.074955752875654230f, 0.074572525724710764f, 0.074189295831948693f,
+    0.073806063211457842f,
+  0.073422827877329483f, 0.073039589843653177f, 0.072656349124520389f,
+    0.072273105734021334f,
+  0.071889859686246352f, 0.071506610995287156f, 0.071123359675233852f,
+    0.070740105740178361f,
+  0.070356849204211397f, 0.069973590081423773f, 0.069590328385907715f,
+    0.069207064131753759f,
+  0.068823797333054326f, 0.068440528003900616f, 0.068057256158383886f,
+    0.067673981810596848f,
+  0.067290704974630494f, 0.066907425664577733f, 0.066524143894529736f,
+    0.066140859678579578f,
+  0.065757573030819083f, 0.065374283965340146f, 0.064990992496236119f,
+    0.064607698637598646f,
+  0.064224402403521202f, 0.063841103808096086f, 0.063457802865415636f,
+    0.063074499589573618f,
+  0.062691193994662109f, 0.062307886094775049f, 0.061924575904005130f,
+    0.061541263436445129f,
+  0.061157948706189229f, 0.060774631727329942f, 0.060391312513961619f,
+    0.060007991080177375f,
+  0.059624667440070382f, 0.059241341607735261f, 0.058858013597264912f,
+    0.058474683422754095f,
+  0.058091351098295878f, 0.057708016637985186f, 0.057324680055915692f,
+    0.056941341366181127f,
+  0.056558000582876661f, 0.056174657720095743f, 0.055791312791933681f,
+    0.055407965812484541f,
+  0.055024616795842439f, 0.054641265756102911f, 0.054257912707359794f,
+    0.053874557663708772f,
+  0.053491200639244271f, 0.053107841648060788f, 0.052724480704254229f,
+    0.052341117821918783f,
+  0.051957753015150501f, 0.051574386298044173f, 0.051191017684694640f,
+    0.050807647189198162f,
+  0.050424274825649297f, 0.050040900608144430f, 0.049657524550778251f,
+    0.049274146667647289f,
+  0.048890766972846805f, 0.048507385480472134f, 0.048124002204620014f,
+    0.047740617159385448f,
+  0.047357230358865306f, 0.046973841817155179f, 0.046590451548350717f,
+    0.046207059566548990f,
+  0.045823665885845313f, 0.045440270520336883f, 0.045056873484119603f,
+    0.044673474791289434f,
+  0.044290074455943754f, 0.043906672492178188f, 0.043523268914090238f,
+    0.043139863735776100f,
+  0.042756456971332048f, 0.042373048634855741f, 0.041989638740443119f,
+    0.041606227302191955f,
+  0.041222814334198304f, 0.040839399850560058f, 0.040455983865373815f,
+    0.040072566392736257f,
+  0.039689147446745419f, 0.039305727041497644f, 0.038922305191091085f,
+    0.038538881909622631f,
+  0.038155457211189216f, 0.037772031109889144f, 0.037388603619819022f,
+    0.037005174755077273f,
+  0.036621744529761024f, 0.036238312957967478f, 0.035854880053795196f,
+    0.035471445831341021f,
+  0.035088010304703626f, 0.034704573487980395f, 0.034321135395268765f,
+    0.033937696040667535f,
+  0.033554255438273790f, 0.033170813602186440f, 0.032787370546502645f,
+    0.032403926285321405f,
+  0.032020480832740429f, 0.031637034202857461f, 0.031253586409771626f,
+    0.030870137467580314f,
+  0.030486687390382738f, 0.030103236192276818f, 0.029719783887360508f,
+    0.029336330489733147f,
+  0.028952876013492331f, 0.028569420472737472f, 0.028185963881566689f,
+    0.027802506254078142f,
+  0.027419047604371360f, 0.027035587946544135f, 0.026652127294696067f,
+    0.026268665662925468f,
+  0.025885203065330677f, 0.025501739516011413f, 0.025118275029065638f,
+    0.024734809618593138f,
+  0.024351343298691951f, 0.023967876083461924f, 0.023584407987001611f,
+    0.023200939023409587f,
+  0.022817469206785804f, 0.022433998551228459f, 0.022050527070837558f,
+    0.021667054779711814f,
+  0.021283581691949955f, 0.020900107821652084f, 0.020516633182916549f,
+    0.020133157789843505f,
+  0.019749681656531803f, 0.019366204797080316f, 0.018982727225589285f,
+    0.018599248956157190f,
+  0.018215770002884327f, 0.017832290379869671f, 0.017448810101212228f,
+    0.017065329181012358f,
+  0.016681847633368677f, 0.016298365472381587f, 0.015914882712149747f,
+    0.015531399366773606f,
+  0.015147915450352307f, 0.014764430976985016f, 0.014380945960772247f,
+    0.013997460415812761f,
+  0.013613974356207112f, 0.013230487796054543f, 0.012847000749454314f,
+    0.012463513230507034f,
+  0.012080025253311559f, 0.011696536831968529f, 0.011313047980577277f,
+    0.010929558713237145f,
+  0.010546069044048827f, 0.010162578987111254f, 0.009779088556525145f,
+    0.009395597766389905f,
+  0.009012106630804949f, 0.008628615163871038f, 0.008245123379687167f,
+    0.007861631292354124f,
+  0.007478138915970929f, 0.007094646264638386f, 0.006711153352455981f,
+    0.006327660193523208f,
+  0.005944166801940901f, 0.005560673191808128f, 0.005177179377225743f,
+    0.004793685372293270f,
+  0.004410191191110246f, 0.004026696847777542f, 0.003643202356394263f,
+    0.003259707731061291f,
+  0.002876212985878184f, 0.002492718134944503f, 0.002109223192361147f,
+    0.001725728172227238f,
+  0.001342233088643682f, 0.000958737955710053f, 0.000575242787525925f,
+    0.000191747598192208f
+};
+
+/**
+ * @} end of DCT4_IDCT4_Table group
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in]     N			 length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.
+ * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingF32Table.gif
+ */
+
+arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize)
+{
+  /*  Initialize the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  float32_t *twiddlePtr[4] =
+    { (float32_t *) Weights_128, (float32_t *) Weights_512,
+    (float32_t *) Weights_2048, (float32_t *) Weights_8192
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  float32_t *pCosFactor[4] =
+    { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
+    (float32_t *) cos_factors_2048, (float32_t *) cos_factors_8192
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 8192U:
+    S->pTwiddle = twiddlePtr[3];
+    S->pCosFactor = pCosFactor[3];
+    break;
+  case 2048U:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512U:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128U:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0U, 1U);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c
new file mode 100644
index 0000000..d3401bc
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c
@@ -0,0 +1,4280 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_dct4_init_q15.c
+ * Description:  Initialization function of DCT-4 & IDCT4 Q15
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup DCT4_IDCT4
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4_Table DCT Type IV Tables
+ * @{
+ */
+
+/*
+* @brief  Weights Table
+*/
+
+/**
+ * \par
+ * Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))

+ * \par
+ * C command to generate the table
+ * 
+ * for(i = 0; i< N; i++)
+ * {
+ *   weights[2*i]= cos(i*c);
+ *   weights[(2*i)+1]= -sin(i * c);
+ * } 

+ * \par
+ * where N is the Number of weights to be calculated and c is pi/(2*N)
+ * \par
+ * Converted the output to q15 format by multiplying with 2^31 and saturated if required.
+ * \par
+ * In the tables below the real and imaginary values are placed alternatively, hence the
+ * array length is 2*N.
+ */
+
+static const q15_t ALIGN4 WeightsQ15_128[256] = {
+  (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7fe9, (q15_t)0xfb4a,
+  (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f87, (q15_t)0xf505,
+  (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7ed5, (q15_t)0xeec7,
+  (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7dd6, (q15_t)0xe893,
+  (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7c89, (q15_t)0xe26d,
+  (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7aef, (q15_t)0xdc5a,
+  (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7909, (q15_t)0xd65d,
+  (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x76d9, (q15_t)0xd079,
+  (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x745f, (q15_t)0xcab3,
+  (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x719e, (q15_t)0xc50e,
+  (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6e96, (q15_t)0xbf8d,
+  (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6b4a, (q15_t)0xba33,
+  (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x67bd, (q15_t)0xb505,
+  (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x63ef, (q15_t)0xb005,
+  (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x5fe3, (q15_t)0xab36,
+  (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5b9d, (q15_t)0xa69c,
+  (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x571d, (q15_t)0xa239,
+  (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5269, (q15_t)0x9e0f,
+  (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4d81, (q15_t)0x9a23,
+  (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x4869, (q15_t)0x9674,
+  (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4325, (q15_t)0x9307,
+  (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3db8, (q15_t)0x8fdd,
+  (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3824, (q15_t)0x8cf9,
+  (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x326e, (q15_t)0x8a5b,
+  (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2c98, (q15_t)0x8806,
+  (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x26a8, (q15_t)0x85fb,
+  (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x209f, (q15_t)0x843b,
+  (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1a82, (q15_t)0x82c7,
+  (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x1455, (q15_t)0x81a1,
+  (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1139, (q15_t)0x812b, (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xe1b, (q15_t)0x80c8,
+  (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xafb, (q15_t)0x8079, (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x7d9, (q15_t)0x803e,
+  (q15_t)0x647, (q15_t)0x8028, (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x324, (q15_t)0x800a, (q15_t)0x192, (q15_t)0x8003
+};
+
+static const q15_t ALIGN4 WeightsQ15_512[1024] = {
+  (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7ffe, (q15_t)0xfed3,
+  (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff8, (q15_t)0xfd41,
+  (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fed, (q15_t)0xfbaf,
+  (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fdd, (q15_t)0xfa1d,
+  (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fc8, (q15_t)0xf88b,
+  (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fae, (q15_t)0xf6fa,
+  (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f8f, (q15_t)0xf569,
+  (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f6b, (q15_t)0xf3d9,
+  (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f43, (q15_t)0xf249,
+  (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f15, (q15_t)0xf0b9,
+  (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7ee3, (q15_t)0xef2a,
+  (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eab, (q15_t)0xed9c,
+  (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e6f, (q15_t)0xec0e,
+  (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e2e, (q15_t)0xea81,
+  (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7de8, (q15_t)0xe8f6,
+  (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7d9d, (q15_t)0xe76a,
+  (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d4e, (q15_t)0xe5e0,
+  (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7cf9, (q15_t)0xe457,
+  (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7ca0, (q15_t)0xe2cf,
+  (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c42, (q15_t)0xe148,
+  (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bdf, (q15_t)0xdfc2,
+  (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b77, (q15_t)0xde3e,
+  (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b0b, (q15_t)0xdcbb,
+  (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7a9a, (q15_t)0xdb39,
+  (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a24, (q15_t)0xd9b8,
+  (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79a9, (q15_t)0xd839,
+  (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x792a, (q15_t)0xd6bc,
+  (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78a6, (q15_t)0xd540,
+  (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x781d, (q15_t)0xd3c6,
+  (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x7790, (q15_t)0xd24d,
+  (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x76fe, (q15_t)0xd0d7,
+  (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x7668, (q15_t)0xcf62,
+  (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75cc, (q15_t)0xcdef,
+  (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x752d, (q15_t)0xcc7e,
+  (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x7489, (q15_t)0xcb0e,
+  (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x73e0, (q15_t)0xc9a1,
+  (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x7333, (q15_t)0xc836,
+  (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x72db, (q15_t)0xc782, (q15_t)0x72af, (q15_t)0xc728, (q15_t)0x7282, (q15_t)0xc6ce,
+  (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x7227, (q15_t)0xc61a, (q15_t)0x71fa, (q15_t)0xc5c0, (q15_t)0x71cc, (q15_t)0xc567,
+  (q15_t)0x719e, (q15_t)0xc50e, (q15_t)0x716f, (q15_t)0xc4b4, (q15_t)0x7141, (q15_t)0xc45b, (q15_t)0x7112, (q15_t)0xc403,
+  (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x70b3, (q15_t)0xc351, (q15_t)0x7083, (q15_t)0xc2f9, (q15_t)0x7053, (q15_t)0xc2a0,
+  (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x6ff2, (q15_t)0xc1f0, (q15_t)0x6fc1, (q15_t)0xc198, (q15_t)0x6f90, (q15_t)0xc141,
+  (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6f2d, (q15_t)0xc092, (q15_t)0x6efb, (q15_t)0xc03b, (q15_t)0x6ec9, (q15_t)0xbfe3,
+  (q15_t)0x6e96, (q15_t)0xbf8d, (q15_t)0x6e63, (q15_t)0xbf36, (q15_t)0x6e30, (q15_t)0xbedf, (q15_t)0x6dfd, (q15_t)0xbe89,
+  (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6d96, (q15_t)0xbddc, (q15_t)0x6d62, (q15_t)0xbd86, (q15_t)0x6d2d, (q15_t)0xbd30,
+  (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6cc4, (q15_t)0xbc85, (q15_t)0x6c8f, (q15_t)0xbc30, (q15_t)0x6c59, (q15_t)0xbbdb,
+  (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6bee, (q15_t)0xbb31, (q15_t)0x6bb8, (q15_t)0xbadc, (q15_t)0x6b81, (q15_t)0xba88,
+  (q15_t)0x6b4a, (q15_t)0xba33, (q15_t)0x6b13, (q15_t)0xb9df, (q15_t)0x6adc, (q15_t)0xb98b, (q15_t)0x6aa5, (q15_t)0xb937,
+  (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x6a35, (q15_t)0xb890, (q15_t)0x69fd, (q15_t)0xb83d, (q15_t)0x69c4, (q15_t)0xb7ea,
+  (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x6953, (q15_t)0xb744, (q15_t)0x6919, (q15_t)0xb6f1, (q15_t)0x68e0, (q15_t)0xb69f,
+  (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x686c, (q15_t)0xb5fa, (q15_t)0x6832, (q15_t)0xb5a8, (q15_t)0x67f7, (q15_t)0xb557,
+  (q15_t)0x67bd, (q15_t)0xb505, (q15_t)0x6782, (q15_t)0xb4b4, (q15_t)0x6746, (q15_t)0xb462, (q15_t)0x670b, (q15_t)0xb411,
+  (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x6693, (q15_t)0xb370, (q15_t)0x6657, (q15_t)0xb31f, (q15_t)0x661a, (q15_t)0xb2cf,
+  (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x65a0, (q15_t)0xb22f, (q15_t)0x6563, (q15_t)0xb1df, (q15_t)0x6526, (q15_t)0xb190,
+  (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x64aa, (q15_t)0xb0f1, (q15_t)0x646c, (q15_t)0xb0a2, (q15_t)0x642d, (q15_t)0xb054,
+  (q15_t)0x63ef, (q15_t)0xb005, (q15_t)0x63b0, (q15_t)0xafb7, (q15_t)0x6371, (q15_t)0xaf69, (q15_t)0x6331, (q15_t)0xaf1b,
+  (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x62b2, (q15_t)0xae7f, (q15_t)0x6271, (q15_t)0xae32, (q15_t)0x6231, (q15_t)0xade4,
+  (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x61b0, (q15_t)0xad4b, (q15_t)0x616f, (q15_t)0xacfe, (q15_t)0x612d, (q15_t)0xacb2,
+  (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x60aa, (q15_t)0xac19, (q15_t)0x6068, (q15_t)0xabcd, (q15_t)0x6026, (q15_t)0xab82,
+  (q15_t)0x5fe3, (q15_t)0xab36, (q15_t)0x5fa0, (q15_t)0xaaeb, (q15_t)0x5f5e, (q15_t)0xaaa0, (q15_t)0x5f1a, (q15_t)0xaa55,
+  (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5e93, (q15_t)0xa9c0, (q15_t)0x5e50, (q15_t)0xa976, (q15_t)0x5e0b, (q15_t)0xa92c,
+  (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5d83, (q15_t)0xa899, (q15_t)0x5d3e, (q15_t)0xa850, (q15_t)0x5cf9, (q15_t)0xa807,
+  (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5c6e, (q15_t)0xa775, (q15_t)0x5c29, (q15_t)0xa72c, (q15_t)0x5be3, (q15_t)0xa6e4,
+  (q15_t)0x5b9d, (q15_t)0xa69c, (q15_t)0x5b56, (q15_t)0xa654, (q15_t)0x5b10, (q15_t)0xa60d, (q15_t)0x5ac9, (q15_t)0xa5c5,
+  (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5a3b, (q15_t)0xa537, (q15_t)0x59f3, (q15_t)0xa4f0, (q15_t)0x59ac, (q15_t)0xa4aa,
+  (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x591c, (q15_t)0xa41d, (q15_t)0x58d4, (q15_t)0xa3d7, (q15_t)0x588b, (q15_t)0xa392,
+  (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x57f9, (q15_t)0xa307, (q15_t)0x57b0, (q15_t)0xa2c2, (q15_t)0x5767, (q15_t)0xa27d,
+  (q15_t)0x571d, (q15_t)0xa239, (q15_t)0x56d4, (q15_t)0xa1f5, (q15_t)0x568a, (q15_t)0xa1b0, (q15_t)0x5640, (q15_t)0xa16d,
+  (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x55ab, (q15_t)0xa0e6, (q15_t)0x5560, (q15_t)0xa0a2, (q15_t)0x5515, (q15_t)0xa060,
+  (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x547e, (q15_t)0x9fda, (q15_t)0x5433, (q15_t)0x9f98, (q15_t)0x53e7, (q15_t)0x9f56,
+  (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x534e, (q15_t)0x9ed3, (q15_t)0x5302, (q15_t)0x9e91, (q15_t)0x52b5, (q15_t)0x9e50,
+  (q15_t)0x5269, (q15_t)0x9e0f, (q15_t)0x521c, (q15_t)0x9dcf, (q15_t)0x51ce, (q15_t)0x9d8f, (q15_t)0x5181, (q15_t)0x9d4e,
+  (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x50e5, (q15_t)0x9ccf, (q15_t)0x5097, (q15_t)0x9c8f, (q15_t)0x5049, (q15_t)0x9c50,
+  (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4fac, (q15_t)0x9bd3, (q15_t)0x4f5e, (q15_t)0x9b94, (q15_t)0x4f0f, (q15_t)0x9b56,
+  (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4e70, (q15_t)0x9ada, (q15_t)0x4e21, (q15_t)0x9a9d, (q15_t)0x4dd1, (q15_t)0x9a60,
+  (q15_t)0x4d81, (q15_t)0x9a23, (q15_t)0x4d31, (q15_t)0x99e6, (q15_t)0x4ce1, (q15_t)0x99a9, (q15_t)0x4c90, (q15_t)0x996d,
+  (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4bef, (q15_t)0x98f5, (q15_t)0x4b9e, (q15_t)0x98ba, (q15_t)0x4b4c, (q15_t)0x987e,
+  (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x4aa9, (q15_t)0x9809, (q15_t)0x4a58, (q15_t)0x97ce, (q15_t)0x4a06, (q15_t)0x9794,
+  (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x4961, (q15_t)0x9720, (q15_t)0x490f, (q15_t)0x96e7, (q15_t)0x48bc, (q15_t)0x96ad,
+  (q15_t)0x4869, (q15_t)0x9674, (q15_t)0x4816, (q15_t)0x963c, (q15_t)0x47c3, (q15_t)0x9603, (q15_t)0x4770, (q15_t)0x95cb,
+  (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x46c9, (q15_t)0x955b, (q15_t)0x4675, (q15_t)0x9524, (q15_t)0x4621, (q15_t)0x94ed,
+  (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x4578, (q15_t)0x947f, (q15_t)0x4524, (q15_t)0x9448, (q15_t)0x44cf, (q15_t)0x9412,
+  (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4425, (q15_t)0x93a7, (q15_t)0x43d0, (q15_t)0x9371, (q15_t)0x437b, (q15_t)0x933c,
+  (q15_t)0x4325, (q15_t)0x9307, (q15_t)0x42d0, (q15_t)0x92d3, (q15_t)0x427a, (q15_t)0x929e, (q15_t)0x4224, (q15_t)0x926a,
+  (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x4177, (q15_t)0x9203, (q15_t)0x4121, (q15_t)0x91d0, (q15_t)0x40ca, (q15_t)0x919d,
+  (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x401d, (q15_t)0x9137, (q15_t)0x3fc5, (q15_t)0x9105, (q15_t)0x3f6e, (q15_t)0x90d3,
+  (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e10, (q15_t)0x900e,
+  (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3caf, (q15_t)0x8f4d,
+  (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b4c, (q15_t)0x8e91,
+  (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x39e6, (q15_t)0x8dd9,
+  (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x387e, (q15_t)0x8d25,
+  (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3714, (q15_t)0x8c76,
+  (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35a8, (q15_t)0x8bcb,
+  (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x343a, (q15_t)0x8b25,
+  (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x32ca, (q15_t)0x8a83,
+  (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x3158, (q15_t)0x89e5,
+  (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x2fe4, (q15_t)0x894d,
+  (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2e6e, (q15_t)0x88b9,
+  (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2cf7, (q15_t)0x8829,
+  (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2b7d, (q15_t)0x879e,
+  (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a02, (q15_t)0x8718,
+  (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x2886, (q15_t)0x8696,
+  (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x2707, (q15_t)0x8619,
+  (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x2588, (q15_t)0x85a1,
+  (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x2407, (q15_t)0x852d,
+  (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x2284, (q15_t)0x84be,
+  (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x2100, (q15_t)0x8454,
+  (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1f7b, (q15_t)0x83ef,
+  (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1df5, (q15_t)0x838f,
+  (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1c6d, (q15_t)0x8333,
+  (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1ae4, (q15_t)0x82dc,
+  (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x195b, (q15_t)0x828a,
+  (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x17d0, (q15_t)0x823d,
+  (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x1645, (q15_t)0x81f4,
+  (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x14b8, (q15_t)0x81b1,
+  (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x132b, (q15_t)0x8172,
+  (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x119d, (q15_t)0x8138,
+  (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x100e, (q15_t)0x8103,
+  (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xe7f, (q15_t)0x80d3,
+  (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xcef, (q15_t)0x80a8,
+  (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xb5f, (q15_t)0x8082,
+  (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa33, (q15_t)0x8069, (q15_t)0x9ce, (q15_t)0x8061,
+  (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x83d, (q15_t)0x8044,
+  (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x775, (q15_t)0x8038, (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6ac, (q15_t)0x802d,
+  (q15_t)0x647, (q15_t)0x8028, (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x51a, (q15_t)0x801b,
+  (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x451, (q15_t)0x8013, (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x388, (q15_t)0x800d,
+  (q15_t)0x324, (q15_t)0x800a, (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x1f6, (q15_t)0x8004,
+  (q15_t)0x192, (q15_t)0x8003, (q15_t)0x12d, (q15_t)0x8002, (q15_t)0xc9, (q15_t)0x8001, (q15_t)0x64, (q15_t)0x8001
+};
+
+static const q15_t ALIGN4 WeightsQ15_2048[4096] = {
+  (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffb5,
+  (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff51,
+  (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeec,
+  (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffd, (q15_t)0xfe88,
+  (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe23,
+  (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffa, (q15_t)0xfdbe,
+  (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff8, (q15_t)0xfd5a,
+  (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff6, (q15_t)0xfcf5,
+  (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfc91,
+  (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc2c,
+  (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbc8,
+  (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7fea, (q15_t)0xfb64,
+  (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe6, (q15_t)0xfaff,
+  (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe2, (q15_t)0xfa9b,
+  (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fde, (q15_t)0xfa36,
+  (q15_t)0x7fdd, (q15_t)0xfa1d, (q15_t)0x7fdc, (q15_t)0xfa04, (q15_t)0x7fda, (q15_t)0xf9eb, (q15_t)0x7fd9, (q15_t)0xf9d2,
+  (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd7, (q15_t)0xf9a0, (q15_t)0x7fd6, (q15_t)0xf986, (q15_t)0x7fd4, (q15_t)0xf96d,
+  (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fd2, (q15_t)0xf93b, (q15_t)0x7fd0, (q15_t)0xf922, (q15_t)0x7fcf, (q15_t)0xf909,
+  (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fcc, (q15_t)0xf8d7, (q15_t)0x7fcb, (q15_t)0xf8be, (q15_t)0x7fc9, (q15_t)0xf8a5,
+  (q15_t)0x7fc8, (q15_t)0xf88b, (q15_t)0x7fc6, (q15_t)0xf872, (q15_t)0x7fc5, (q15_t)0xf859, (q15_t)0x7fc3, (q15_t)0xf840,
+  (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fc0, (q15_t)0xf80e, (q15_t)0x7fbf, (q15_t)0xf7f5, (q15_t)0x7fbd, (q15_t)0xf7dc,
+  (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fba, (q15_t)0xf7aa, (q15_t)0x7fb8, (q15_t)0xf791, (q15_t)0x7fb7, (q15_t)0xf778,
+  (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fb3, (q15_t)0xf745, (q15_t)0x7fb1, (q15_t)0xf72c, (q15_t)0x7fb0, (q15_t)0xf713,
+  (q15_t)0x7fae, (q15_t)0xf6fa, (q15_t)0x7fac, (q15_t)0xf6e1, (q15_t)0x7faa, (q15_t)0xf6c8, (q15_t)0x7fa9, (q15_t)0xf6af,
+  (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7fa5, (q15_t)0xf67d, (q15_t)0x7fa3, (q15_t)0xf664, (q15_t)0x7fa1, (q15_t)0xf64b,
+  (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f9d, (q15_t)0xf619, (q15_t)0x7f9b, (q15_t)0xf600, (q15_t)0x7f99, (q15_t)0xf5e7,
+  (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f95, (q15_t)0xf5b4, (q15_t)0x7f93, (q15_t)0xf59b, (q15_t)0x7f91, (q15_t)0xf582,
+  (q15_t)0x7f8f, (q15_t)0xf569, (q15_t)0x7f8d, (q15_t)0xf550, (q15_t)0x7f8b, (q15_t)0xf537, (q15_t)0x7f89, (q15_t)0xf51e,
+  (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f85, (q15_t)0xf4ec, (q15_t)0x7f82, (q15_t)0xf4d3, (q15_t)0x7f80, (q15_t)0xf4ba,
+  (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f7c, (q15_t)0xf488, (q15_t)0x7f79, (q15_t)0xf46f, (q15_t)0x7f77, (q15_t)0xf456,
+  (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f72, (q15_t)0xf424, (q15_t)0x7f70, (q15_t)0xf40b, (q15_t)0x7f6e, (q15_t)0xf3f2,
+  (q15_t)0x7f6b, (q15_t)0xf3d9, (q15_t)0x7f69, (q15_t)0xf3c0, (q15_t)0x7f67, (q15_t)0xf3a7, (q15_t)0x7f64, (q15_t)0xf38e,
+  (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f5f, (q15_t)0xf35c, (q15_t)0x7f5d, (q15_t)0xf343, (q15_t)0x7f5a, (q15_t)0xf32a,
+  (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f55, (q15_t)0xf2f8, (q15_t)0x7f53, (q15_t)0xf2df, (q15_t)0x7f50, (q15_t)0xf2c6,
+  (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f4b, (q15_t)0xf294, (q15_t)0x7f48, (q15_t)0xf27b, (q15_t)0x7f45, (q15_t)0xf262,
+  (q15_t)0x7f43, (q15_t)0xf249, (q15_t)0x7f40, (q15_t)0xf230, (q15_t)0x7f3d, (q15_t)0xf217, (q15_t)0x7f3b, (q15_t)0xf1fe,
+  (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f35, (q15_t)0xf1cc, (q15_t)0x7f32, (q15_t)0xf1b3, (q15_t)0x7f2f, (q15_t)0xf19a,
+  (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f2a, (q15_t)0xf168, (q15_t)0x7f27, (q15_t)0xf14f, (q15_t)0x7f24, (q15_t)0xf136,
+  (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f1e, (q15_t)0xf104, (q15_t)0x7f1b, (q15_t)0xf0eb, (q15_t)0x7f18, (q15_t)0xf0d2,
+  (q15_t)0x7f15, (q15_t)0xf0b9, (q15_t)0x7f12, (q15_t)0xf0a0, (q15_t)0x7f0f, (q15_t)0xf087, (q15_t)0x7f0c, (q15_t)0xf06e,
+  (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7f06, (q15_t)0xf03c, (q15_t)0x7f03, (q15_t)0xf023, (q15_t)0x7f00, (q15_t)0xf00b,
+  (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7ef9, (q15_t)0xefd9, (q15_t)0x7ef6, (q15_t)0xefc0, (q15_t)0x7ef3, (q15_t)0xefa7,
+  (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7eed, (q15_t)0xef75, (q15_t)0x7ee9, (q15_t)0xef5c, (q15_t)0x7ee6, (q15_t)0xef43,
+  (q15_t)0x7ee3, (q15_t)0xef2a, (q15_t)0x7edf, (q15_t)0xef11, (q15_t)0x7edc, (q15_t)0xeef8, (q15_t)0x7ed9, (q15_t)0xeedf,
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+  (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7ec4, (q15_t)0xee4a, (q15_t)0x7ec1, (q15_t)0xee31, (q15_t)0x7ebd, (q15_t)0xee18,
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+  (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e99, (q15_t)0xed20, (q15_t)0x7e95, (q15_t)0xed07, (q15_t)0x7e92, (q15_t)0xecee,
+  (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e8a, (q15_t)0xecbc, (q15_t)0x7e86, (q15_t)0xeca3, (q15_t)0x7e83, (q15_t)0xec8a,
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+  (q15_t)0x7e6f, (q15_t)0xec0e, (q15_t)0x7e6b, (q15_t)0xebf5, (q15_t)0x7e67, (q15_t)0xebdd, (q15_t)0x7e63, (q15_t)0xebc4,
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+  (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e4b, (q15_t)0xeb2f, (q15_t)0x7e47, (q15_t)0xeb16, (q15_t)0x7e43, (q15_t)0xeafd,
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+  (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7df6, (q15_t)0xe940, (q15_t)0x7df1, (q15_t)0xe927, (q15_t)0x7ded, (q15_t)0xe90e,
+  (q15_t)0x7de8, (q15_t)0xe8f6, (q15_t)0x7de4, (q15_t)0xe8dd, (q15_t)0x7ddf, (q15_t)0xe8c4, (q15_t)0x7dda, (q15_t)0xe8ab,
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+  (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7dbf, (q15_t)0xe817, (q15_t)0x7dba, (q15_t)0xe7fe, (q15_t)0x7db5, (q15_t)0xe7e6,
+  (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7dac, (q15_t)0xe7b4, (q15_t)0x7da7, (q15_t)0xe79c, (q15_t)0x7da2, (q15_t)0xe783,
+  (q15_t)0x7d9d, (q15_t)0xe76a, (q15_t)0x7d98, (q15_t)0xe752, (q15_t)0x7d94, (q15_t)0xe739, (q15_t)0x7d8f, (q15_t)0xe720,
+  (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d85, (q15_t)0xe6ef, (q15_t)0x7d80, (q15_t)0xe6d6, (q15_t)0x7d7b, (q15_t)0xe6be,
+  (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d71, (q15_t)0xe68d, (q15_t)0x7d6c, (q15_t)0xe674, (q15_t)0x7d67, (q15_t)0xe65b,
+  (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d5d, (q15_t)0xe62a, (q15_t)0x7d58, (q15_t)0xe611, (q15_t)0x7d53, (q15_t)0xe5f9,
+  (q15_t)0x7d4e, (q15_t)0xe5e0, (q15_t)0x7d49, (q15_t)0xe5c8, (q15_t)0x7d43, (q15_t)0xe5af, (q15_t)0x7d3e, (q15_t)0xe596,
+  (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d34, (q15_t)0xe565, (q15_t)0x7d2f, (q15_t)0xe54d, (q15_t)0x7d29, (q15_t)0xe534,
+  (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d1f, (q15_t)0xe503, (q15_t)0x7d19, (q15_t)0xe4ea, (q15_t)0x7d14, (q15_t)0xe4d2,
+  (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7d09, (q15_t)0xe4a1, (q15_t)0x7d04, (q15_t)0xe488, (q15_t)0x7cff, (q15_t)0xe470,
+  (q15_t)0x7cf9, (q15_t)0xe457, (q15_t)0x7cf4, (q15_t)0xe43f, (q15_t)0x7cee, (q15_t)0xe426, (q15_t)0x7ce9, (q15_t)0xe40e,
+  (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7cde, (q15_t)0xe3dc, (q15_t)0x7cd8, (q15_t)0xe3c4, (q15_t)0x7cd3, (q15_t)0xe3ab,
+  (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7cc8, (q15_t)0xe37a, (q15_t)0x7cc2, (q15_t)0xe362, (q15_t)0x7cbc, (q15_t)0xe349,
+  (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7cb1, (q15_t)0xe318, (q15_t)0x7cab, (q15_t)0xe300, (q15_t)0x7ca6, (q15_t)0xe2e8,
+  (q15_t)0x7ca0, (q15_t)0xe2cf, (q15_t)0x7c9a, (q15_t)0xe2b7, (q15_t)0x7c94, (q15_t)0xe29e, (q15_t)0x7c8f, (q15_t)0xe286,
+  (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c83, (q15_t)0xe255, (q15_t)0x7c7d, (q15_t)0xe23c, (q15_t)0x7c77, (q15_t)0xe224,
+  (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c6c, (q15_t)0xe1f3, (q15_t)0x7c66, (q15_t)0xe1db, (q15_t)0x7c60, (q15_t)0xe1c2,
+  (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c54, (q15_t)0xe191, (q15_t)0x7c4e, (q15_t)0xe179, (q15_t)0x7c48, (q15_t)0xe160,
+  (q15_t)0x7c42, (q15_t)0xe148, (q15_t)0x7c3c, (q15_t)0xe130, (q15_t)0x7c36, (q15_t)0xe117, (q15_t)0x7c30, (q15_t)0xe0ff,
+  (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c23, (q15_t)0xe0ce, (q15_t)0x7c1d, (q15_t)0xe0b6, (q15_t)0x7c17, (q15_t)0xe09d,
+  (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7c0b, (q15_t)0xe06d, (q15_t)0x7c05, (q15_t)0xe054, (q15_t)0x7bfe, (q15_t)0xe03c,
+  (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bf2, (q15_t)0xe00b, (q15_t)0x7beb, (q15_t)0xdff3, (q15_t)0x7be5, (q15_t)0xdfdb,
+  (q15_t)0x7bdf, (q15_t)0xdfc2, (q15_t)0x7bd9, (q15_t)0xdfaa, (q15_t)0x7bd2, (q15_t)0xdf92, (q15_t)0x7bcc, (q15_t)0xdf79,
+  (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bbf, (q15_t)0xdf49, (q15_t)0x7bb9, (q15_t)0xdf30, (q15_t)0x7bb2, (q15_t)0xdf18,
+  (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7ba5, (q15_t)0xdee8, (q15_t)0x7b9f, (q15_t)0xdecf, (q15_t)0x7b98, (q15_t)0xdeb7,
+  (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b8b, (q15_t)0xde87, (q15_t)0x7b84, (q15_t)0xde6e, (q15_t)0x7b7e, (q15_t)0xde56,
+  (q15_t)0x7b77, (q15_t)0xde3e, (q15_t)0x7b71, (q15_t)0xde26, (q15_t)0x7b6a, (q15_t)0xde0d, (q15_t)0x7b63, (q15_t)0xddf5,
+  (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b56, (q15_t)0xddc5, (q15_t)0x7b4f, (q15_t)0xddac, (q15_t)0x7b48, (q15_t)0xdd94,
+  (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b3b, (q15_t)0xdd64, (q15_t)0x7b34, (q15_t)0xdd4c, (q15_t)0x7b2d, (q15_t)0xdd33,
+  (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b1f, (q15_t)0xdd03, (q15_t)0x7b19, (q15_t)0xdceb, (q15_t)0x7b12, (q15_t)0xdcd3,
+  (q15_t)0x7b0b, (q15_t)0xdcbb, (q15_t)0x7b04, (q15_t)0xdca2, (q15_t)0x7afd, (q15_t)0xdc8a, (q15_t)0x7af6, (q15_t)0xdc72,
+  (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7ae8, (q15_t)0xdc42, (q15_t)0x7ae1, (q15_t)0xdc2a, (q15_t)0x7ada, (q15_t)0xdc12,
+  (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7acc, (q15_t)0xdbe1, (q15_t)0x7ac5, (q15_t)0xdbc9, (q15_t)0x7abd, (q15_t)0xdbb1,
+  (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7aaf, (q15_t)0xdb81, (q15_t)0x7aa8, (q15_t)0xdb69, (q15_t)0x7aa1, (q15_t)0xdb51,
+  (q15_t)0x7a9a, (q15_t)0xdb39, (q15_t)0x7a92, (q15_t)0xdb21, (q15_t)0x7a8b, (q15_t)0xdb09, (q15_t)0x7a84, (q15_t)0xdaf1,
+  (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a75, (q15_t)0xdac0, (q15_t)0x7a6e, (q15_t)0xdaa8, (q15_t)0x7a67, (q15_t)0xda90,
+  (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a58, (q15_t)0xda60, (q15_t)0x7a50, (q15_t)0xda48, (q15_t)0x7a49, (q15_t)0xda30,
+  (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a3a, (q15_t)0xda00, (q15_t)0x7a33, (q15_t)0xd9e8, (q15_t)0x7a2b, (q15_t)0xd9d0,
+  (q15_t)0x7a24, (q15_t)0xd9b8, (q15_t)0x7a1c, (q15_t)0xd9a0, (q15_t)0x7a15, (q15_t)0xd988, (q15_t)0x7a0d, (q15_t)0xd970,
+  (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x79fe, (q15_t)0xd940, (q15_t)0x79f6, (q15_t)0xd928, (q15_t)0x79ef, (q15_t)0xd911,
+  (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79df, (q15_t)0xd8e1, (q15_t)0x79d8, (q15_t)0xd8c9, (q15_t)0x79d0, (q15_t)0xd8b1,
+  (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79c0, (q15_t)0xd881, (q15_t)0x79b9, (q15_t)0xd869, (q15_t)0x79b1, (q15_t)0xd851,
+  (q15_t)0x79a9, (q15_t)0xd839, (q15_t)0x79a1, (q15_t)0xd821, (q15_t)0x7999, (q15_t)0xd80a, (q15_t)0x7992, (q15_t)0xd7f2,
+  (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7982, (q15_t)0xd7c2, (q15_t)0x797a, (q15_t)0xd7aa, (q15_t)0x7972, (q15_t)0xd792,
+  (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x7962, (q15_t)0xd763, (q15_t)0x795a, (q15_t)0xd74b, (q15_t)0x7952, (q15_t)0xd733,
+  (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x7942, (q15_t)0xd703, (q15_t)0x793a, (q15_t)0xd6eb, (q15_t)0x7932, (q15_t)0xd6d4,
+  (q15_t)0x792a, (q15_t)0xd6bc, (q15_t)0x7922, (q15_t)0xd6a4, (q15_t)0x7919, (q15_t)0xd68c, (q15_t)0x7911, (q15_t)0xd675,
+  (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x7901, (q15_t)0xd645, (q15_t)0x78f9, (q15_t)0xd62d, (q15_t)0x78f1, (q15_t)0xd615,
+  (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78e0, (q15_t)0xd5e6, (q15_t)0x78d8, (q15_t)0xd5ce, (q15_t)0x78cf, (q15_t)0xd5b7,
+  (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78bf, (q15_t)0xd587, (q15_t)0x78b6, (q15_t)0xd56f, (q15_t)0x78ae, (q15_t)0xd558,
+  (q15_t)0x78a6, (q15_t)0xd540, (q15_t)0x789d, (q15_t)0xd528, (q15_t)0x7895, (q15_t)0xd511, (q15_t)0x788c, (q15_t)0xd4f9,
+  (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x787c, (q15_t)0xd4ca, (q15_t)0x7873, (q15_t)0xd4b2, (q15_t)0x786b, (q15_t)0xd49a,
+  (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7859, (q15_t)0xd46b, (q15_t)0x7851, (q15_t)0xd453, (q15_t)0x7848, (q15_t)0xd43c,
+  (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x7837, (q15_t)0xd40d, (q15_t)0x782e, (q15_t)0xd3f5, (q15_t)0x7826, (q15_t)0xd3dd,
+  (q15_t)0x781d, (q15_t)0xd3c6, (q15_t)0x7814, (q15_t)0xd3ae, (q15_t)0x780c, (q15_t)0xd397, (q15_t)0x7803, (q15_t)0xd37f,
+  (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77f1, (q15_t)0xd350, (q15_t)0x77e9, (q15_t)0xd338, (q15_t)0x77e0, (q15_t)0xd321,
+  (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77ce, (q15_t)0xd2f2, (q15_t)0x77c5, (q15_t)0xd2da, (q15_t)0x77bc, (q15_t)0xd2c3,
+  (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x77ab, (q15_t)0xd294, (q15_t)0x77a2, (q15_t)0xd27c, (q15_t)0x7799, (q15_t)0xd265,
+  (q15_t)0x7790, (q15_t)0xd24d, (q15_t)0x7787, (q15_t)0xd236, (q15_t)0x777e, (q15_t)0xd21e, (q15_t)0x7775, (q15_t)0xd207,
+  (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x7763, (q15_t)0xd1d8, (q15_t)0x775a, (q15_t)0xd1c1, (q15_t)0x7751, (q15_t)0xd1a9,
+  (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x773e, (q15_t)0xd17a, (q15_t)0x7735, (q15_t)0xd163, (q15_t)0x772c, (q15_t)0xd14b,
+  (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x771a, (q15_t)0xd11d, (q15_t)0x7710, (q15_t)0xd105, (q15_t)0x7707, (q15_t)0xd0ee,
+  (q15_t)0x76fe, (q15_t)0xd0d7, (q15_t)0x76f5, (q15_t)0xd0bf, (q15_t)0x76eb, (q15_t)0xd0a8, (q15_t)0x76e2, (q15_t)0xd091,
+  (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76cf, (q15_t)0xd062, (q15_t)0x76c6, (q15_t)0xd04b, (q15_t)0x76bd, (q15_t)0xd033,
+  (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x76aa, (q15_t)0xd005, (q15_t)0x76a0, (q15_t)0xcfed, (q15_t)0x7697, (q15_t)0xcfd6,
+  (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x7684, (q15_t)0xcfa7, (q15_t)0x767b, (q15_t)0xcf90, (q15_t)0x7671, (q15_t)0xcf79,
+  (q15_t)0x7668, (q15_t)0xcf62, (q15_t)0x765e, (q15_t)0xcf4a, (q15_t)0x7654, (q15_t)0xcf33, (q15_t)0x764b, (q15_t)0xcf1c,
+  (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x7638, (q15_t)0xceee, (q15_t)0x762e, (q15_t)0xced6, (q15_t)0x7624, (q15_t)0xcebf,
+  (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x7611, (q15_t)0xce91, (q15_t)0x7607, (q15_t)0xce7a, (q15_t)0x75fd, (q15_t)0xce62,
+  (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75ea, (q15_t)0xce34, (q15_t)0x75e0, (q15_t)0xce1d, (q15_t)0x75d6, (q15_t)0xce06,
+  (q15_t)0x75cc, (q15_t)0xcdef, (q15_t)0x75c3, (q15_t)0xcdd8, (q15_t)0x75b9, (q15_t)0xcdc0, (q15_t)0x75af, (q15_t)0xcda9,
+  (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x759b, (q15_t)0xcd7b, (q15_t)0x7591, (q15_t)0xcd64, (q15_t)0x7587, (q15_t)0xcd4d,
+  (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x7573, (q15_t)0xcd1f, (q15_t)0x7569, (q15_t)0xcd08, (q15_t)0x755f, (q15_t)0xccf1,
+  (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x754b, (q15_t)0xccc3, (q15_t)0x7541, (q15_t)0xccac, (q15_t)0x7537, (q15_t)0xcc95,
+  (q15_t)0x752d, (q15_t)0xcc7e, (q15_t)0x7523, (q15_t)0xcc67, (q15_t)0x7519, (q15_t)0xcc50, (q15_t)0x750f, (q15_t)0xcc39,
+  (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x74fa, (q15_t)0xcc0b, (q15_t)0x74f0, (q15_t)0xcbf4, (q15_t)0x74e6, (q15_t)0xcbdd,
+  (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74d1, (q15_t)0xcbaf, (q15_t)0x74c7, (q15_t)0xcb98, (q15_t)0x74bd, (q15_t)0xcb81,
+  (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x74a8, (q15_t)0xcb53, (q15_t)0x749e, (q15_t)0xcb3c, (q15_t)0x7493, (q15_t)0xcb25,
+  (q15_t)0x7489, (q15_t)0xcb0e, (q15_t)0x747e, (q15_t)0xcaf8, (q15_t)0x7474, (q15_t)0xcae1, (q15_t)0x746a, (q15_t)0xcaca,
+  (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x7455, (q15_t)0xca9c, (q15_t)0x744a, (q15_t)0xca85, (q15_t)0x7440, (q15_t)0xca6e,
+  (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x742b, (q15_t)0xca41, (q15_t)0x7420, (q15_t)0xca2a, (q15_t)0x7415, (q15_t)0xca13,
+  (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x7400, (q15_t)0xc9e6, (q15_t)0x73f6, (q15_t)0xc9cf, (q15_t)0x73eb, (q15_t)0xc9b8,
+  (q15_t)0x73e0, (q15_t)0xc9a1, (q15_t)0x73d6, (q15_t)0xc98b, (q15_t)0x73cb, (q15_t)0xc974, (q15_t)0x73c0, (q15_t)0xc95d,
+  (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x73ab, (q15_t)0xc930, (q15_t)0x73a0, (q15_t)0xc919, (q15_t)0x7395, (q15_t)0xc902,
+  (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x737f, (q15_t)0xc8d5, (q15_t)0x7375, (q15_t)0xc8be, (q15_t)0x736a, (q15_t)0xc8a8,
+  (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x7354, (q15_t)0xc87a, (q15_t)0x7349, (q15_t)0xc864, (q15_t)0x733e, (q15_t)0xc84d,
+  (q15_t)0x7333, (q15_t)0xc836, (q15_t)0x7328, (q15_t)0xc820, (q15_t)0x731d, (q15_t)0xc809, (q15_t)0x7312, (q15_t)0xc7f3,
+  (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x72fc, (q15_t)0xc7c5, (q15_t)0x72f1, (q15_t)0xc7af, (q15_t)0x72e6, (q15_t)0xc798,
+  (q15_t)0x72db, (q15_t)0xc782, (q15_t)0x72d0, (q15_t)0xc76b, (q15_t)0x72c5, (q15_t)0xc755, (q15_t)0x72ba, (q15_t)0xc73e,
+  (q15_t)0x72af, (q15_t)0xc728, (q15_t)0x72a3, (q15_t)0xc711, (q15_t)0x7298, (q15_t)0xc6fa, (q15_t)0x728d, (q15_t)0xc6e4,
+  (q15_t)0x7282, (q15_t)0xc6ce, (q15_t)0x7276, (q15_t)0xc6b7, (q15_t)0x726b, (q15_t)0xc6a1, (q15_t)0x7260, (q15_t)0xc68a,
+  (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x7249, (q15_t)0xc65d, (q15_t)0x723e, (q15_t)0xc647, (q15_t)0x7233, (q15_t)0xc630,
+  (q15_t)0x7227, (q15_t)0xc61a, (q15_t)0x721c, (q15_t)0xc603, (q15_t)0x7211, (q15_t)0xc5ed, (q15_t)0x7205, (q15_t)0xc5d7,
+  (q15_t)0x71fa, (q15_t)0xc5c0, (q15_t)0x71ee, (q15_t)0xc5aa, (q15_t)0x71e3, (q15_t)0xc594, (q15_t)0x71d7, (q15_t)0xc57d,
+  (q15_t)0x71cc, (q15_t)0xc567, (q15_t)0x71c0, (q15_t)0xc551, (q15_t)0x71b5, (q15_t)0xc53a, (q15_t)0x71a9, (q15_t)0xc524,
+  (q15_t)0x719e, (q15_t)0xc50e, (q15_t)0x7192, (q15_t)0xc4f7, (q15_t)0x7186, (q15_t)0xc4e1, (q15_t)0x717b, (q15_t)0xc4cb,
+  (q15_t)0x716f, (q15_t)0xc4b4, (q15_t)0x7164, (q15_t)0xc49e, (q15_t)0x7158, (q15_t)0xc488, (q15_t)0x714c, (q15_t)0xc472,
+  (q15_t)0x7141, (q15_t)0xc45b, (q15_t)0x7135, (q15_t)0xc445, (q15_t)0x7129, (q15_t)0xc42f, (q15_t)0x711d, (q15_t)0xc419,
+  (q15_t)0x7112, (q15_t)0xc403, (q15_t)0x7106, (q15_t)0xc3ec, (q15_t)0x70fa, (q15_t)0xc3d6, (q15_t)0x70ee, (q15_t)0xc3c0,
+  (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x70d6, (q15_t)0xc394, (q15_t)0x70cb, (q15_t)0xc37d, (q15_t)0x70bf, (q15_t)0xc367,
+  (q15_t)0x70b3, (q15_t)0xc351, (q15_t)0x70a7, (q15_t)0xc33b, (q15_t)0x709b, (q15_t)0xc325, (q15_t)0x708f, (q15_t)0xc30f,
+  (q15_t)0x7083, (q15_t)0xc2f9, (q15_t)0x7077, (q15_t)0xc2e3, (q15_t)0x706b, (q15_t)0xc2cd, (q15_t)0x705f, (q15_t)0xc2b7,
+  (q15_t)0x7053, (q15_t)0xc2a0, (q15_t)0x7047, (q15_t)0xc28a, (q15_t)0x703b, (q15_t)0xc274, (q15_t)0x702f, (q15_t)0xc25e,
+  (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x7016, (q15_t)0xc232, (q15_t)0x700a, (q15_t)0xc21c, (q15_t)0x6ffe, (q15_t)0xc206,
+  (q15_t)0x6ff2, (q15_t)0xc1f0, (q15_t)0x6fe6, (q15_t)0xc1da, (q15_t)0x6fda, (q15_t)0xc1c4, (q15_t)0x6fcd, (q15_t)0xc1ae,
+  (q15_t)0x6fc1, (q15_t)0xc198, (q15_t)0x6fb5, (q15_t)0xc183, (q15_t)0x6fa9, (q15_t)0xc16d, (q15_t)0x6f9c, (q15_t)0xc157,
+  (q15_t)0x6f90, (q15_t)0xc141, (q15_t)0x6f84, (q15_t)0xc12b, (q15_t)0x6f77, (q15_t)0xc115, (q15_t)0x6f6b, (q15_t)0xc0ff,
+  (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6f52, (q15_t)0xc0d3, (q15_t)0x6f46, (q15_t)0xc0bd, (q15_t)0x6f39, (q15_t)0xc0a8,
+  (q15_t)0x6f2d, (q15_t)0xc092, (q15_t)0x6f20, (q15_t)0xc07c, (q15_t)0x6f14, (q15_t)0xc066, (q15_t)0x6f07, (q15_t)0xc050,
+  (q15_t)0x6efb, (q15_t)0xc03b, (q15_t)0x6eee, (q15_t)0xc025, (q15_t)0x6ee2, (q15_t)0xc00f, (q15_t)0x6ed5, (q15_t)0xbff9,
+  (q15_t)0x6ec9, (q15_t)0xbfe3, (q15_t)0x6ebc, (q15_t)0xbfce, (q15_t)0x6eaf, (q15_t)0xbfb8, (q15_t)0x6ea3, (q15_t)0xbfa2,
+  (q15_t)0x6e96, (q15_t)0xbf8d, (q15_t)0x6e89, (q15_t)0xbf77, (q15_t)0x6e7d, (q15_t)0xbf61, (q15_t)0x6e70, (q15_t)0xbf4b,
+  (q15_t)0x6e63, (q15_t)0xbf36, (q15_t)0x6e57, (q15_t)0xbf20, (q15_t)0x6e4a, (q15_t)0xbf0a, (q15_t)0x6e3d, (q15_t)0xbef5,
+  (q15_t)0x6e30, (q15_t)0xbedf, (q15_t)0x6e24, (q15_t)0xbeca, (q15_t)0x6e17, (q15_t)0xbeb4, (q15_t)0x6e0a, (q15_t)0xbe9e,
+  (q15_t)0x6dfd, (q15_t)0xbe89, (q15_t)0x6df0, (q15_t)0xbe73, (q15_t)0x6de3, (q15_t)0xbe5e, (q15_t)0x6dd6, (q15_t)0xbe48,
+  (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6dbd, (q15_t)0xbe1d, (q15_t)0x6db0, (q15_t)0xbe07, (q15_t)0x6da3, (q15_t)0xbdf2,
+  (q15_t)0x6d96, (q15_t)0xbddc, (q15_t)0x6d89, (q15_t)0xbdc7, (q15_t)0x6d7c, (q15_t)0xbdb1, (q15_t)0x6d6f, (q15_t)0xbd9c,
+  (q15_t)0x6d62, (q15_t)0xbd86, (q15_t)0x6d55, (q15_t)0xbd71, (q15_t)0x6d48, (q15_t)0xbd5b, (q15_t)0x6d3a, (q15_t)0xbd46,
+  (q15_t)0x6d2d, (q15_t)0xbd30, (q15_t)0x6d20, (q15_t)0xbd1b, (q15_t)0x6d13, (q15_t)0xbd06, (q15_t)0x6d06, (q15_t)0xbcf0,
+  (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6cec, (q15_t)0xbcc5, (q15_t)0x6cde, (q15_t)0xbcb0, (q15_t)0x6cd1, (q15_t)0xbc9b,
+  (q15_t)0x6cc4, (q15_t)0xbc85, (q15_t)0x6cb7, (q15_t)0xbc70, (q15_t)0x6ca9, (q15_t)0xbc5b, (q15_t)0x6c9c, (q15_t)0xbc45,
+  (q15_t)0x6c8f, (q15_t)0xbc30, (q15_t)0x6c81, (q15_t)0xbc1b, (q15_t)0x6c74, (q15_t)0xbc05, (q15_t)0x6c67, (q15_t)0xbbf0,
+  (q15_t)0x6c59, (q15_t)0xbbdb, (q15_t)0x6c4c, (q15_t)0xbbc5, (q15_t)0x6c3f, (q15_t)0xbbb0, (q15_t)0x6c31, (q15_t)0xbb9b,
+  (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6c16, (q15_t)0xbb70, (q15_t)0x6c09, (q15_t)0xbb5b, (q15_t)0x6bfb, (q15_t)0xbb46,
+  (q15_t)0x6bee, (q15_t)0xbb31, (q15_t)0x6be0, (q15_t)0xbb1c, (q15_t)0x6bd3, (q15_t)0xbb06, (q15_t)0x6bc5, (q15_t)0xbaf1,
+  (q15_t)0x6bb8, (q15_t)0xbadc, (q15_t)0x6baa, (q15_t)0xbac7, (q15_t)0x6b9c, (q15_t)0xbab2, (q15_t)0x6b8f, (q15_t)0xba9d,
+  (q15_t)0x6b81, (q15_t)0xba88, (q15_t)0x6b73, (q15_t)0xba73, (q15_t)0x6b66, (q15_t)0xba5d, (q15_t)0x6b58, (q15_t)0xba48,
+  (q15_t)0x6b4a, (q15_t)0xba33, (q15_t)0x6b3d, (q15_t)0xba1e, (q15_t)0x6b2f, (q15_t)0xba09, (q15_t)0x6b21, (q15_t)0xb9f4,
+  (q15_t)0x6b13, (q15_t)0xb9df, (q15_t)0x6b06, (q15_t)0xb9ca, (q15_t)0x6af8, (q15_t)0xb9b5, (q15_t)0x6aea, (q15_t)0xb9a0,
+  (q15_t)0x6adc, (q15_t)0xb98b, (q15_t)0x6ace, (q15_t)0xb976, (q15_t)0x6ac1, (q15_t)0xb961, (q15_t)0x6ab3, (q15_t)0xb94c,
+  (q15_t)0x6aa5, (q15_t)0xb937, (q15_t)0x6a97, (q15_t)0xb922, (q15_t)0x6a89, (q15_t)0xb90d, (q15_t)0x6a7b, (q15_t)0xb8f8,
+  (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x6a5f, (q15_t)0xb8cf, (q15_t)0x6a51, (q15_t)0xb8ba, (q15_t)0x6a43, (q15_t)0xb8a5,
+  (q15_t)0x6a35, (q15_t)0xb890, (q15_t)0x6a27, (q15_t)0xb87b, (q15_t)0x6a19, (q15_t)0xb866, (q15_t)0x6a0b, (q15_t)0xb852,
+  (q15_t)0x69fd, (q15_t)0xb83d, (q15_t)0x69ef, (q15_t)0xb828, (q15_t)0x69e1, (q15_t)0xb813, (q15_t)0x69d3, (q15_t)0xb7fe,
+  (q15_t)0x69c4, (q15_t)0xb7ea, (q15_t)0x69b6, (q15_t)0xb7d5, (q15_t)0x69a8, (q15_t)0xb7c0, (q15_t)0x699a, (q15_t)0xb7ab,
+  (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x697d, (q15_t)0xb782, (q15_t)0x696f, (q15_t)0xb76d, (q15_t)0x6961, (q15_t)0xb758,
+  (q15_t)0x6953, (q15_t)0xb744, (q15_t)0x6944, (q15_t)0xb72f, (q15_t)0x6936, (q15_t)0xb71a, (q15_t)0x6928, (q15_t)0xb706,
+  (q15_t)0x6919, (q15_t)0xb6f1, (q15_t)0x690b, (q15_t)0xb6dd, (q15_t)0x68fd, (q15_t)0xb6c8, (q15_t)0x68ee, (q15_t)0xb6b3,
+  (q15_t)0x68e0, (q15_t)0xb69f, (q15_t)0x68d1, (q15_t)0xb68a, (q15_t)0x68c3, (q15_t)0xb676, (q15_t)0x68b5, (q15_t)0xb661,
+  (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x6898, (q15_t)0xb638, (q15_t)0x6889, (q15_t)0xb623, (q15_t)0x687b, (q15_t)0xb60f,
+  (q15_t)0x686c, (q15_t)0xb5fa, (q15_t)0x685e, (q15_t)0xb5e6, (q15_t)0x684f, (q15_t)0xb5d1, (q15_t)0x6840, (q15_t)0xb5bd,
+  (q15_t)0x6832, (q15_t)0xb5a8, (q15_t)0x6823, (q15_t)0xb594, (q15_t)0x6815, (q15_t)0xb57f, (q15_t)0x6806, (q15_t)0xb56b,
+  (q15_t)0x67f7, (q15_t)0xb557, (q15_t)0x67e9, (q15_t)0xb542, (q15_t)0x67da, (q15_t)0xb52e, (q15_t)0x67cb, (q15_t)0xb519,
+  (q15_t)0x67bd, (q15_t)0xb505, (q15_t)0x67ae, (q15_t)0xb4f1, (q15_t)0x679f, (q15_t)0xb4dc, (q15_t)0x6790, (q15_t)0xb4c8,
+  (q15_t)0x6782, (q15_t)0xb4b4, (q15_t)0x6773, (q15_t)0xb49f, (q15_t)0x6764, (q15_t)0xb48b, (q15_t)0x6755, (q15_t)0xb477,
+  (q15_t)0x6746, (q15_t)0xb462, (q15_t)0x6737, (q15_t)0xb44e, (q15_t)0x6729, (q15_t)0xb43a, (q15_t)0x671a, (q15_t)0xb426,
+  (q15_t)0x670b, (q15_t)0xb411, (q15_t)0x66fc, (q15_t)0xb3fd, (q15_t)0x66ed, (q15_t)0xb3e9, (q15_t)0x66de, (q15_t)0xb3d5,
+  (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x66c0, (q15_t)0xb3ac, (q15_t)0x66b1, (q15_t)0xb398, (q15_t)0x66a2, (q15_t)0xb384,
+  (q15_t)0x6693, (q15_t)0xb370, (q15_t)0x6684, (q15_t)0xb35c, (q15_t)0x6675, (q15_t)0xb348, (q15_t)0x6666, (q15_t)0xb334,
+  (q15_t)0x6657, (q15_t)0xb31f, (q15_t)0x6648, (q15_t)0xb30b, (q15_t)0x6639, (q15_t)0xb2f7, (q15_t)0x6629, (q15_t)0xb2e3,
+  (q15_t)0x661a, (q15_t)0xb2cf, (q15_t)0x660b, (q15_t)0xb2bb, (q15_t)0x65fc, (q15_t)0xb2a7, (q15_t)0x65ed, (q15_t)0xb293,
+  (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x65ce, (q15_t)0xb26b, (q15_t)0x65bf, (q15_t)0xb257, (q15_t)0x65b0, (q15_t)0xb243,
+  (q15_t)0x65a0, (q15_t)0xb22f, (q15_t)0x6591, (q15_t)0xb21b, (q15_t)0x6582, (q15_t)0xb207, (q15_t)0x6573, (q15_t)0xb1f3,
+  (q15_t)0x6563, (q15_t)0xb1df, (q15_t)0x6554, (q15_t)0xb1cc, (q15_t)0x6545, (q15_t)0xb1b8, (q15_t)0x6535, (q15_t)0xb1a4,
+  (q15_t)0x6526, (q15_t)0xb190, (q15_t)0x6516, (q15_t)0xb17c, (q15_t)0x6507, (q15_t)0xb168, (q15_t)0x64f7, (q15_t)0xb154,
+  (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x64d9, (q15_t)0xb12d, (q15_t)0x64c9, (q15_t)0xb119, (q15_t)0x64ba, (q15_t)0xb105,
+  (q15_t)0x64aa, (q15_t)0xb0f1, (q15_t)0x649b, (q15_t)0xb0de, (q15_t)0x648b, (q15_t)0xb0ca, (q15_t)0x647b, (q15_t)0xb0b6,
+  (q15_t)0x646c, (q15_t)0xb0a2, (q15_t)0x645c, (q15_t)0xb08f, (q15_t)0x644d, (q15_t)0xb07b, (q15_t)0x643d, (q15_t)0xb067,
+  (q15_t)0x642d, (q15_t)0xb054, (q15_t)0x641e, (q15_t)0xb040, (q15_t)0x640e, (q15_t)0xb02c, (q15_t)0x63fe, (q15_t)0xb019,
+  (q15_t)0x63ef, (q15_t)0xb005, (q15_t)0x63df, (q15_t)0xaff1, (q15_t)0x63cf, (q15_t)0xafde, (q15_t)0x63c0, (q15_t)0xafca,
+  (q15_t)0x63b0, (q15_t)0xafb7, (q15_t)0x63a0, (q15_t)0xafa3, (q15_t)0x6390, (q15_t)0xaf90, (q15_t)0x6380, (q15_t)0xaf7c,
+  (q15_t)0x6371, (q15_t)0xaf69, (q15_t)0x6361, (q15_t)0xaf55, (q15_t)0x6351, (q15_t)0xaf41, (q15_t)0x6341, (q15_t)0xaf2e,
+  (q15_t)0x6331, (q15_t)0xaf1b, (q15_t)0x6321, (q15_t)0xaf07, (q15_t)0x6311, (q15_t)0xaef4, (q15_t)0x6301, (q15_t)0xaee0,
+  (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x62e2, (q15_t)0xaeb9, (q15_t)0x62d2, (q15_t)0xaea6, (q15_t)0x62c2, (q15_t)0xae92,
+  (q15_t)0x62b2, (q15_t)0xae7f, (q15_t)0x62a2, (q15_t)0xae6c, (q15_t)0x6292, (q15_t)0xae58, (q15_t)0x6282, (q15_t)0xae45,
+  (q15_t)0x6271, (q15_t)0xae32, (q15_t)0x6261, (q15_t)0xae1e, (q15_t)0x6251, (q15_t)0xae0b, (q15_t)0x6241, (q15_t)0xadf8,
+  (q15_t)0x6231, (q15_t)0xade4, (q15_t)0x6221, (q15_t)0xadd1, (q15_t)0x6211, (q15_t)0xadbe, (q15_t)0x6201, (q15_t)0xadab,
+  (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x61e0, (q15_t)0xad84, (q15_t)0x61d0, (q15_t)0xad71, (q15_t)0x61c0, (q15_t)0xad5e,
+  (q15_t)0x61b0, (q15_t)0xad4b, (q15_t)0x619f, (q15_t)0xad37, (q15_t)0x618f, (q15_t)0xad24, (q15_t)0x617f, (q15_t)0xad11,
+  (q15_t)0x616f, (q15_t)0xacfe, (q15_t)0x615e, (q15_t)0xaceb, (q15_t)0x614e, (q15_t)0xacd8, (q15_t)0x613e, (q15_t)0xacc5,
+  (q15_t)0x612d, (q15_t)0xacb2, (q15_t)0x611d, (q15_t)0xac9e, (q15_t)0x610d, (q15_t)0xac8b, (q15_t)0x60fc, (q15_t)0xac78,
+  (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x60db, (q15_t)0xac52, (q15_t)0x60cb, (q15_t)0xac3f, (q15_t)0x60ba, (q15_t)0xac2c,
+  (q15_t)0x60aa, (q15_t)0xac19, (q15_t)0x6099, (q15_t)0xac06, (q15_t)0x6089, (q15_t)0xabf3, (q15_t)0x6078, (q15_t)0xabe0,
+  (q15_t)0x6068, (q15_t)0xabcd, (q15_t)0x6057, (q15_t)0xabbb, (q15_t)0x6047, (q15_t)0xaba8, (q15_t)0x6036, (q15_t)0xab95,
+  (q15_t)0x6026, (q15_t)0xab82, (q15_t)0x6015, (q15_t)0xab6f, (q15_t)0x6004, (q15_t)0xab5c, (q15_t)0x5ff4, (q15_t)0xab49,
+  (q15_t)0x5fe3, (q15_t)0xab36, (q15_t)0x5fd3, (q15_t)0xab24, (q15_t)0x5fc2, (q15_t)0xab11, (q15_t)0x5fb1, (q15_t)0xaafe,
+  (q15_t)0x5fa0, (q15_t)0xaaeb, (q15_t)0x5f90, (q15_t)0xaad8, (q15_t)0x5f7f, (q15_t)0xaac6, (q15_t)0x5f6e, (q15_t)0xaab3,
+  (q15_t)0x5f5e, (q15_t)0xaaa0, (q15_t)0x5f4d, (q15_t)0xaa8e, (q15_t)0x5f3c, (q15_t)0xaa7b, (q15_t)0x5f2b, (q15_t)0xaa68,
+  (q15_t)0x5f1a, (q15_t)0xaa55, (q15_t)0x5f0a, (q15_t)0xaa43, (q15_t)0x5ef9, (q15_t)0xaa30, (q15_t)0x5ee8, (q15_t)0xaa1d,
+  (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5ec6, (q15_t)0xa9f8, (q15_t)0x5eb5, (q15_t)0xa9e6, (q15_t)0x5ea4, (q15_t)0xa9d3,
+  (q15_t)0x5e93, (q15_t)0xa9c0, (q15_t)0x5e82, (q15_t)0xa9ae, (q15_t)0x5e71, (q15_t)0xa99b, (q15_t)0x5e60, (q15_t)0xa989,
+  (q15_t)0x5e50, (q15_t)0xa976, (q15_t)0x5e3f, (q15_t)0xa964, (q15_t)0x5e2d, (q15_t)0xa951, (q15_t)0x5e1c, (q15_t)0xa93f,
+  (q15_t)0x5e0b, (q15_t)0xa92c, (q15_t)0x5dfa, (q15_t)0xa91a, (q15_t)0x5de9, (q15_t)0xa907, (q15_t)0x5dd8, (q15_t)0xa8f5,
+  (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5db6, (q15_t)0xa8d0, (q15_t)0x5da5, (q15_t)0xa8be, (q15_t)0x5d94, (q15_t)0xa8ab,
+  (q15_t)0x5d83, (q15_t)0xa899, (q15_t)0x5d71, (q15_t)0xa887, (q15_t)0x5d60, (q15_t)0xa874, (q15_t)0x5d4f, (q15_t)0xa862,
+  (q15_t)0x5d3e, (q15_t)0xa850, (q15_t)0x5d2d, (q15_t)0xa83d, (q15_t)0x5d1b, (q15_t)0xa82b, (q15_t)0x5d0a, (q15_t)0xa819,
+  (q15_t)0x5cf9, (q15_t)0xa807, (q15_t)0x5ce8, (q15_t)0xa7f4, (q15_t)0x5cd6, (q15_t)0xa7e2, (q15_t)0x5cc5, (q15_t)0xa7d0,
+  (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5ca2, (q15_t)0xa7ab, (q15_t)0x5c91, (q15_t)0xa799, (q15_t)0x5c80, (q15_t)0xa787,
+  (q15_t)0x5c6e, (q15_t)0xa775, (q15_t)0x5c5d, (q15_t)0xa763, (q15_t)0x5c4b, (q15_t)0xa751, (q15_t)0x5c3a, (q15_t)0xa73f,
+  (q15_t)0x5c29, (q15_t)0xa72c, (q15_t)0x5c17, (q15_t)0xa71a, (q15_t)0x5c06, (q15_t)0xa708, (q15_t)0x5bf4, (q15_t)0xa6f6,
+  (q15_t)0x5be3, (q15_t)0xa6e4, (q15_t)0x5bd1, (q15_t)0xa6d2, (q15_t)0x5bc0, (q15_t)0xa6c0, (q15_t)0x5bae, (q15_t)0xa6ae,
+  (q15_t)0x5b9d, (q15_t)0xa69c, (q15_t)0x5b8b, (q15_t)0xa68a, (q15_t)0x5b79, (q15_t)0xa678, (q15_t)0x5b68, (q15_t)0xa666,
+  (q15_t)0x5b56, (q15_t)0xa654, (q15_t)0x5b45, (q15_t)0xa642, (q15_t)0x5b33, (q15_t)0xa630, (q15_t)0x5b21, (q15_t)0xa61f,
+  (q15_t)0x5b10, (q15_t)0xa60d, (q15_t)0x5afe, (q15_t)0xa5fb, (q15_t)0x5aec, (q15_t)0xa5e9, (q15_t)0x5adb, (q15_t)0xa5d7,
+  (q15_t)0x5ac9, (q15_t)0xa5c5, (q15_t)0x5ab7, (q15_t)0xa5b3, (q15_t)0x5aa5, (q15_t)0xa5a2, (q15_t)0x5a94, (q15_t)0xa590,
+  (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5a70, (q15_t)0xa56c, (q15_t)0x5a5e, (q15_t)0xa55b, (q15_t)0x5a4d, (q15_t)0xa549,
+  (q15_t)0x5a3b, (q15_t)0xa537, (q15_t)0x5a29, (q15_t)0xa525, (q15_t)0x5a17, (q15_t)0xa514, (q15_t)0x5a05, (q15_t)0xa502,
+  (q15_t)0x59f3, (q15_t)0xa4f0, (q15_t)0x59e1, (q15_t)0xa4df, (q15_t)0x59d0, (q15_t)0xa4cd, (q15_t)0x59be, (q15_t)0xa4bb,
+  (q15_t)0x59ac, (q15_t)0xa4aa, (q15_t)0x599a, (q15_t)0xa498, (q15_t)0x5988, (q15_t)0xa487, (q15_t)0x5976, (q15_t)0xa475,
+  (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x5952, (q15_t)0xa452, (q15_t)0x5940, (q15_t)0xa440, (q15_t)0x592e, (q15_t)0xa42f,
+  (q15_t)0x591c, (q15_t)0xa41d, (q15_t)0x590a, (q15_t)0xa40c, (q15_t)0x58f8, (q15_t)0xa3fa, (q15_t)0x58e6, (q15_t)0xa3e9,
+  (q15_t)0x58d4, (q15_t)0xa3d7, (q15_t)0x58c1, (q15_t)0xa3c6, (q15_t)0x58af, (q15_t)0xa3b5, (q15_t)0x589d, (q15_t)0xa3a3,
+  (q15_t)0x588b, (q15_t)0xa392, (q15_t)0x5879, (q15_t)0xa380, (q15_t)0x5867, (q15_t)0xa36f, (q15_t)0x5855, (q15_t)0xa35e,
+  (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x5830, (q15_t)0xa33b, (q15_t)0x581e, (q15_t)0xa32a, (q15_t)0x580c, (q15_t)0xa318,
+  (q15_t)0x57f9, (q15_t)0xa307, (q15_t)0x57e7, (q15_t)0xa2f6, (q15_t)0x57d5, (q15_t)0xa2e5, (q15_t)0x57c3, (q15_t)0xa2d3,
+  (q15_t)0x57b0, (q15_t)0xa2c2, (q15_t)0x579e, (q15_t)0xa2b1, (q15_t)0x578c, (q15_t)0xa2a0, (q15_t)0x5779, (q15_t)0xa28f,
+  (q15_t)0x5767, (q15_t)0xa27d, (q15_t)0x5755, (q15_t)0xa26c, (q15_t)0x5742, (q15_t)0xa25b, (q15_t)0x5730, (q15_t)0xa24a,
+  (q15_t)0x571d, (q15_t)0xa239, (q15_t)0x570b, (q15_t)0xa228, (q15_t)0x56f9, (q15_t)0xa217, (q15_t)0x56e6, (q15_t)0xa206,
+  (q15_t)0x56d4, (q15_t)0xa1f5, (q15_t)0x56c1, (q15_t)0xa1e4, (q15_t)0x56af, (q15_t)0xa1d3, (q15_t)0x569c, (q15_t)0xa1c1,
+  (q15_t)0x568a, (q15_t)0xa1b0, (q15_t)0x5677, (q15_t)0xa1a0, (q15_t)0x5665, (q15_t)0xa18f, (q15_t)0x5652, (q15_t)0xa17e,
+  (q15_t)0x5640, (q15_t)0xa16d, (q15_t)0x562d, (q15_t)0xa15c, (q15_t)0x561a, (q15_t)0xa14b, (q15_t)0x5608, (q15_t)0xa13a,
+  (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x55e3, (q15_t)0xa118, (q15_t)0x55d0, (q15_t)0xa107, (q15_t)0x55bd, (q15_t)0xa0f6,
+  (q15_t)0x55ab, (q15_t)0xa0e6, (q15_t)0x5598, (q15_t)0xa0d5, (q15_t)0x5585, (q15_t)0xa0c4, (q15_t)0x5572, (q15_t)0xa0b3,
+  (q15_t)0x5560, (q15_t)0xa0a2, (q15_t)0x554d, (q15_t)0xa092, (q15_t)0x553a, (q15_t)0xa081, (q15_t)0x5528, (q15_t)0xa070,
+  (q15_t)0x5515, (q15_t)0xa060, (q15_t)0x5502, (q15_t)0xa04f, (q15_t)0x54ef, (q15_t)0xa03e, (q15_t)0x54dc, (q15_t)0xa02d,
+  (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x54b7, (q15_t)0xa00c, (q15_t)0x54a4, (q15_t)0x9ffc, (q15_t)0x5491, (q15_t)0x9feb,
+  (q15_t)0x547e, (q15_t)0x9fda, (q15_t)0x546b, (q15_t)0x9fca, (q15_t)0x5458, (q15_t)0x9fb9, (q15_t)0x5445, (q15_t)0x9fa9,
+  (q15_t)0x5433, (q15_t)0x9f98, (q15_t)0x5420, (q15_t)0x9f88, (q15_t)0x540d, (q15_t)0x9f77, (q15_t)0x53fa, (q15_t)0x9f67,
+  (q15_t)0x53e7, (q15_t)0x9f56, (q15_t)0x53d4, (q15_t)0x9f46, (q15_t)0x53c1, (q15_t)0x9f35, (q15_t)0x53ae, (q15_t)0x9f25,
+  (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5388, (q15_t)0x9f04, (q15_t)0x5375, (q15_t)0x9ef3, (q15_t)0x5362, (q15_t)0x9ee3,
+  (q15_t)0x534e, (q15_t)0x9ed3, (q15_t)0x533b, (q15_t)0x9ec2, (q15_t)0x5328, (q15_t)0x9eb2, (q15_t)0x5315, (q15_t)0x9ea2,
+  (q15_t)0x5302, (q15_t)0x9e91, (q15_t)0x52ef, (q15_t)0x9e81, (q15_t)0x52dc, (q15_t)0x9e71, (q15_t)0x52c9, (q15_t)0x9e61,
+  (q15_t)0x52b5, (q15_t)0x9e50, (q15_t)0x52a2, (q15_t)0x9e40, (q15_t)0x528f, (q15_t)0x9e30, (q15_t)0x527c, (q15_t)0x9e20,
+  (q15_t)0x5269, (q15_t)0x9e0f, (q15_t)0x5255, (q15_t)0x9dff, (q15_t)0x5242, (q15_t)0x9def, (q15_t)0x522f, (q15_t)0x9ddf,
+  (q15_t)0x521c, (q15_t)0x9dcf, (q15_t)0x5208, (q15_t)0x9dbf, (q15_t)0x51f5, (q15_t)0x9daf, (q15_t)0x51e2, (q15_t)0x9d9f,
+  (q15_t)0x51ce, (q15_t)0x9d8f, (q15_t)0x51bb, (q15_t)0x9d7e, (q15_t)0x51a8, (q15_t)0x9d6e, (q15_t)0x5194, (q15_t)0x9d5e,
+  (q15_t)0x5181, (q15_t)0x9d4e, (q15_t)0x516e, (q15_t)0x9d3e, (q15_t)0x515a, (q15_t)0x9d2e, (q15_t)0x5147, (q15_t)0x9d1e,
+  (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x5120, (q15_t)0x9cff, (q15_t)0x510c, (q15_t)0x9cef, (q15_t)0x50f9, (q15_t)0x9cdf,
+  (q15_t)0x50e5, (q15_t)0x9ccf, (q15_t)0x50d2, (q15_t)0x9cbf, (q15_t)0x50bf, (q15_t)0x9caf, (q15_t)0x50ab, (q15_t)0x9c9f,
+  (q15_t)0x5097, (q15_t)0x9c8f, (q15_t)0x5084, (q15_t)0x9c80, (q15_t)0x5070, (q15_t)0x9c70, (q15_t)0x505d, (q15_t)0x9c60,
+  (q15_t)0x5049, (q15_t)0x9c50, (q15_t)0x5036, (q15_t)0x9c40, (q15_t)0x5022, (q15_t)0x9c31, (q15_t)0x500f, (q15_t)0x9c21,
+  (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4fe7, (q15_t)0x9c02, (q15_t)0x4fd4, (q15_t)0x9bf2, (q15_t)0x4fc0, (q15_t)0x9be2,
+  (q15_t)0x4fac, (q15_t)0x9bd3, (q15_t)0x4f99, (q15_t)0x9bc3, (q15_t)0x4f85, (q15_t)0x9bb3, (q15_t)0x4f71, (q15_t)0x9ba4,
+  (q15_t)0x4f5e, (q15_t)0x9b94, (q15_t)0x4f4a, (q15_t)0x9b85, (q15_t)0x4f36, (q15_t)0x9b75, (q15_t)0x4f22, (q15_t)0x9b65,
+  (q15_t)0x4f0f, (q15_t)0x9b56, (q15_t)0x4efb, (q15_t)0x9b46, (q15_t)0x4ee7, (q15_t)0x9b37, (q15_t)0x4ed3, (q15_t)0x9b27,
+  (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4eac, (q15_t)0x9b09, (q15_t)0x4e98, (q15_t)0x9af9, (q15_t)0x4e84, (q15_t)0x9aea,
+  (q15_t)0x4e70, (q15_t)0x9ada, (q15_t)0x4e5c, (q15_t)0x9acb, (q15_t)0x4e48, (q15_t)0x9abb, (q15_t)0x4e34, (q15_t)0x9aac,
+  (q15_t)0x4e21, (q15_t)0x9a9d, (q15_t)0x4e0d, (q15_t)0x9a8d, (q15_t)0x4df9, (q15_t)0x9a7e, (q15_t)0x4de5, (q15_t)0x9a6f,
+  (q15_t)0x4dd1, (q15_t)0x9a60, (q15_t)0x4dbd, (q15_t)0x9a50, (q15_t)0x4da9, (q15_t)0x9a41, (q15_t)0x4d95, (q15_t)0x9a32,
+  (q15_t)0x4d81, (q15_t)0x9a23, (q15_t)0x4d6d, (q15_t)0x9a13, (q15_t)0x4d59, (q15_t)0x9a04, (q15_t)0x4d45, (q15_t)0x99f5,
+  (q15_t)0x4d31, (q15_t)0x99e6, (q15_t)0x4d1d, (q15_t)0x99d7, (q15_t)0x4d09, (q15_t)0x99c7, (q15_t)0x4cf5, (q15_t)0x99b8,
+  (q15_t)0x4ce1, (q15_t)0x99a9, (q15_t)0x4ccc, (q15_t)0x999a, (q15_t)0x4cb8, (q15_t)0x998b, (q15_t)0x4ca4, (q15_t)0x997c,
+  (q15_t)0x4c90, (q15_t)0x996d, (q15_t)0x4c7c, (q15_t)0x995e, (q15_t)0x4c68, (q15_t)0x994f, (q15_t)0x4c54, (q15_t)0x9940,
+  (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4c2b, (q15_t)0x9922, (q15_t)0x4c17, (q15_t)0x9913, (q15_t)0x4c03, (q15_t)0x9904,
+  (q15_t)0x4bef, (q15_t)0x98f5, (q15_t)0x4bda, (q15_t)0x98e6, (q15_t)0x4bc6, (q15_t)0x98d7, (q15_t)0x4bb2, (q15_t)0x98c9,
+  (q15_t)0x4b9e, (q15_t)0x98ba, (q15_t)0x4b89, (q15_t)0x98ab, (q15_t)0x4b75, (q15_t)0x989c, (q15_t)0x4b61, (q15_t)0x988d,
+  (q15_t)0x4b4c, (q15_t)0x987e, (q15_t)0x4b38, (q15_t)0x9870, (q15_t)0x4b24, (q15_t)0x9861, (q15_t)0x4b0f, (q15_t)0x9852,
+  (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x4ae7, (q15_t)0x9835, (q15_t)0x4ad2, (q15_t)0x9826, (q15_t)0x4abe, (q15_t)0x9817,
+  (q15_t)0x4aa9, (q15_t)0x9809, (q15_t)0x4a95, (q15_t)0x97fa, (q15_t)0x4a81, (q15_t)0x97eb, (q15_t)0x4a6c, (q15_t)0x97dd,
+  (q15_t)0x4a58, (q15_t)0x97ce, (q15_t)0x4a43, (q15_t)0x97c0, (q15_t)0x4a2f, (q15_t)0x97b1, (q15_t)0x4a1a, (q15_t)0x97a2,
+  (q15_t)0x4a06, (q15_t)0x9794, (q15_t)0x49f1, (q15_t)0x9785, (q15_t)0x49dd, (q15_t)0x9777, (q15_t)0x49c8, (q15_t)0x9768,
+  (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x499f, (q15_t)0x974b, (q15_t)0x498a, (q15_t)0x973d, (q15_t)0x4976, (q15_t)0x972f,
+  (q15_t)0x4961, (q15_t)0x9720, (q15_t)0x494d, (q15_t)0x9712, (q15_t)0x4938, (q15_t)0x9703, (q15_t)0x4923, (q15_t)0x96f5,
+  (q15_t)0x490f, (q15_t)0x96e7, (q15_t)0x48fa, (q15_t)0x96d8, (q15_t)0x48e6, (q15_t)0x96ca, (q15_t)0x48d1, (q15_t)0x96bc,
+  (q15_t)0x48bc, (q15_t)0x96ad, (q15_t)0x48a8, (q15_t)0x969f, (q15_t)0x4893, (q15_t)0x9691, (q15_t)0x487e, (q15_t)0x9683,
+  (q15_t)0x4869, (q15_t)0x9674, (q15_t)0x4855, (q15_t)0x9666, (q15_t)0x4840, (q15_t)0x9658, (q15_t)0x482b, (q15_t)0x964a,
+  (q15_t)0x4816, (q15_t)0x963c, (q15_t)0x4802, (q15_t)0x962d, (q15_t)0x47ed, (q15_t)0x961f, (q15_t)0x47d8, (q15_t)0x9611,
+  (q15_t)0x47c3, (q15_t)0x9603, (q15_t)0x47ae, (q15_t)0x95f5, (q15_t)0x479a, (q15_t)0x95e7, (q15_t)0x4785, (q15_t)0x95d9,
+  (q15_t)0x4770, (q15_t)0x95cb, (q15_t)0x475b, (q15_t)0x95bd, (q15_t)0x4746, (q15_t)0x95af, (q15_t)0x4731, (q15_t)0x95a1,
+  (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x4708, (q15_t)0x9585, (q15_t)0x46f3, (q15_t)0x9577, (q15_t)0x46de, (q15_t)0x9569,
+  (q15_t)0x46c9, (q15_t)0x955b, (q15_t)0x46b4, (q15_t)0x954d, (q15_t)0x469f, (q15_t)0x953f, (q15_t)0x468a, (q15_t)0x9532,
+  (q15_t)0x4675, (q15_t)0x9524, (q15_t)0x4660, (q15_t)0x9516, (q15_t)0x464b, (q15_t)0x9508, (q15_t)0x4636, (q15_t)0x94fa,
+  (q15_t)0x4621, (q15_t)0x94ed, (q15_t)0x460c, (q15_t)0x94df, (q15_t)0x45f7, (q15_t)0x94d1, (q15_t)0x45e2, (q15_t)0x94c3,
+  (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x45b8, (q15_t)0x94a8, (q15_t)0x45a3, (q15_t)0x949a, (q15_t)0x458d, (q15_t)0x948d,
+  (q15_t)0x4578, (q15_t)0x947f, (q15_t)0x4563, (q15_t)0x9471, (q15_t)0x454e, (q15_t)0x9464, (q15_t)0x4539, (q15_t)0x9456,
+  (q15_t)0x4524, (q15_t)0x9448, (q15_t)0x450f, (q15_t)0x943b, (q15_t)0x44fa, (q15_t)0x942d, (q15_t)0x44e4, (q15_t)0x9420,
+  (q15_t)0x44cf, (q15_t)0x9412, (q15_t)0x44ba, (q15_t)0x9405, (q15_t)0x44a5, (q15_t)0x93f7, (q15_t)0x4490, (q15_t)0x93ea,
+  (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4465, (q15_t)0x93cf, (q15_t)0x4450, (q15_t)0x93c1, (q15_t)0x443b, (q15_t)0x93b4,
+  (q15_t)0x4425, (q15_t)0x93a7, (q15_t)0x4410, (q15_t)0x9399, (q15_t)0x43fb, (q15_t)0x938c, (q15_t)0x43e5, (q15_t)0x937f,
+  (q15_t)0x43d0, (q15_t)0x9371, (q15_t)0x43bb, (q15_t)0x9364, (q15_t)0x43a5, (q15_t)0x9357, (q15_t)0x4390, (q15_t)0x9349,
+  (q15_t)0x437b, (q15_t)0x933c, (q15_t)0x4365, (q15_t)0x932f, (q15_t)0x4350, (q15_t)0x9322, (q15_t)0x433b, (q15_t)0x9314,
+  (q15_t)0x4325, (q15_t)0x9307, (q15_t)0x4310, (q15_t)0x92fa, (q15_t)0x42fa, (q15_t)0x92ed, (q15_t)0x42e5, (q15_t)0x92e0,
+  (q15_t)0x42d0, (q15_t)0x92d3, (q15_t)0x42ba, (q15_t)0x92c6, (q15_t)0x42a5, (q15_t)0x92b8, (q15_t)0x428f, (q15_t)0x92ab,
+  (q15_t)0x427a, (q15_t)0x929e, (q15_t)0x4264, (q15_t)0x9291, (q15_t)0x424f, (q15_t)0x9284, (q15_t)0x4239, (q15_t)0x9277,
+  (q15_t)0x4224, (q15_t)0x926a, (q15_t)0x420e, (q15_t)0x925d, (q15_t)0x41f9, (q15_t)0x9250, (q15_t)0x41e3, (q15_t)0x9243,
+  (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x41b8, (q15_t)0x922a, (q15_t)0x41a2, (q15_t)0x921d, (q15_t)0x418d, (q15_t)0x9210,
+  (q15_t)0x4177, (q15_t)0x9203, (q15_t)0x4162, (q15_t)0x91f6, (q15_t)0x414c, (q15_t)0x91e9, (q15_t)0x4136, (q15_t)0x91dc,
+  (q15_t)0x4121, (q15_t)0x91d0, (q15_t)0x410b, (q15_t)0x91c3, (q15_t)0x40f6, (q15_t)0x91b6, (q15_t)0x40e0, (q15_t)0x91a9,
+  (q15_t)0x40ca, (q15_t)0x919d, (q15_t)0x40b5, (q15_t)0x9190, (q15_t)0x409f, (q15_t)0x9183, (q15_t)0x4089, (q15_t)0x9177,
+  (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x405e, (q15_t)0x915d, (q15_t)0x4048, (q15_t)0x9151, (q15_t)0x4032, (q15_t)0x9144,
+  (q15_t)0x401d, (q15_t)0x9137, (q15_t)0x4007, (q15_t)0x912b, (q15_t)0x3ff1, (q15_t)0x911e, (q15_t)0x3fdb, (q15_t)0x9112,
+  (q15_t)0x3fc5, (q15_t)0x9105, (q15_t)0x3fb0, (q15_t)0x90f9, (q15_t)0x3f9a, (q15_t)0x90ec, (q15_t)0x3f84, (q15_t)0x90e0,
+  (q15_t)0x3f6e, (q15_t)0x90d3, (q15_t)0x3f58, (q15_t)0x90c7, (q15_t)0x3f43, (q15_t)0x90ba, (q15_t)0x3f2d, (q15_t)0x90ae,
+  (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3f01, (q15_t)0x9095, (q15_t)0x3eeb, (q15_t)0x9089, (q15_t)0x3ed5, (q15_t)0x907c,
+  (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3ea9, (q15_t)0x9064, (q15_t)0x3e93, (q15_t)0x9057, (q15_t)0x3e7d, (q15_t)0x904b,
+  (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e52, (q15_t)0x9033, (q15_t)0x3e3c, (q15_t)0x9026, (q15_t)0x3e26, (q15_t)0x901a,
+  (q15_t)0x3e10, (q15_t)0x900e, (q15_t)0x3dfa, (q15_t)0x9002, (q15_t)0x3de4, (q15_t)0x8ff6, (q15_t)0x3dce, (q15_t)0x8fea,
+  (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3da2, (q15_t)0x8fd1, (q15_t)0x3d8c, (q15_t)0x8fc5, (q15_t)0x3d76, (q15_t)0x8fb9,
+  (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d49, (q15_t)0x8fa1, (q15_t)0x3d33, (q15_t)0x8f95, (q15_t)0x3d1d, (q15_t)0x8f89,
+  (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3cf1, (q15_t)0x8f71, (q15_t)0x3cdb, (q15_t)0x8f65, (q15_t)0x3cc5, (q15_t)0x8f59,
+  (q15_t)0x3caf, (q15_t)0x8f4d, (q15_t)0x3c99, (q15_t)0x8f41, (q15_t)0x3c83, (q15_t)0x8f35, (q15_t)0x3c6c, (q15_t)0x8f2a,
+  (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3c40, (q15_t)0x8f12, (q15_t)0x3c2a, (q15_t)0x8f06, (q15_t)0x3c14, (q15_t)0x8efa,
+  (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3be7, (q15_t)0x8ee3, (q15_t)0x3bd1, (q15_t)0x8ed7, (q15_t)0x3bbb, (q15_t)0x8ecb,
+  (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b8e, (q15_t)0x8eb4, (q15_t)0x3b78, (q15_t)0x8ea8, (q15_t)0x3b62, (q15_t)0x8e9c,
+  (q15_t)0x3b4c, (q15_t)0x8e91, (q15_t)0x3b35, (q15_t)0x8e85, (q15_t)0x3b1f, (q15_t)0x8e7a, (q15_t)0x3b09, (q15_t)0x8e6e,
+  (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3adc, (q15_t)0x8e57, (q15_t)0x3ac6, (q15_t)0x8e4b, (q15_t)0x3aaf, (q15_t)0x8e40,
+  (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a83, (q15_t)0x8e29, (q15_t)0x3a6c, (q15_t)0x8e1d, (q15_t)0x3a56, (q15_t)0x8e12,
+  (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x3a29, (q15_t)0x8dfb, (q15_t)0x3a13, (q15_t)0x8def, (q15_t)0x39fd, (q15_t)0x8de4,
+  (q15_t)0x39e6, (q15_t)0x8dd9, (q15_t)0x39d0, (q15_t)0x8dcd, (q15_t)0x39b9, (q15_t)0x8dc2, (q15_t)0x39a3, (q15_t)0x8db7,
+  (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3976, (q15_t)0x8da0, (q15_t)0x395f, (q15_t)0x8d95, (q15_t)0x3949, (q15_t)0x8d8a,
+  (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x391c, (q15_t)0x8d73, (q15_t)0x3906, (q15_t)0x8d68, (q15_t)0x38ef, (q15_t)0x8d5d,
+  (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x38c2, (q15_t)0x8d46, (q15_t)0x38ab, (q15_t)0x8d3b, (q15_t)0x3895, (q15_t)0x8d30,
+  (q15_t)0x387e, (q15_t)0x8d25, (q15_t)0x3868, (q15_t)0x8d1a, (q15_t)0x3851, (q15_t)0x8d0f, (q15_t)0x383b, (q15_t)0x8d04,
+  (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x380d, (q15_t)0x8cee, (q15_t)0x37f7, (q15_t)0x8ce3, (q15_t)0x37e0, (q15_t)0x8cd8,
+  (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x37b3, (q15_t)0x8cc2, (q15_t)0x379c, (q15_t)0x8cb7, (q15_t)0x3786, (q15_t)0x8cac,
+  (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3758, (q15_t)0x8c96, (q15_t)0x3742, (q15_t)0x8c8b, (q15_t)0x372b, (q15_t)0x8c81,
+  (q15_t)0x3714, (q15_t)0x8c76, (q15_t)0x36fe, (q15_t)0x8c6b, (q15_t)0x36e7, (q15_t)0x8c60, (q15_t)0x36d0, (q15_t)0x8c55,
+  (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x36a3, (q15_t)0x8c40, (q15_t)0x368c, (q15_t)0x8c35, (q15_t)0x3675, (q15_t)0x8c2a,
+  (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3648, (q15_t)0x8c15, (q15_t)0x3631, (q15_t)0x8c0a, (q15_t)0x361a, (q15_t)0x8c00,
+  (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35ed, (q15_t)0x8beb, (q15_t)0x35d6, (q15_t)0x8be0, (q15_t)0x35bf, (q15_t)0x8bd5,
+  (q15_t)0x35a8, (q15_t)0x8bcb, (q15_t)0x3592, (q15_t)0x8bc0, (q15_t)0x357b, (q15_t)0x8bb6, (q15_t)0x3564, (q15_t)0x8bab,
+  (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x3536, (q15_t)0x8b96, (q15_t)0x351f, (q15_t)0x8b8c, (q15_t)0x3508, (q15_t)0x8b82,
+  (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x34db, (q15_t)0x8b6d, (q15_t)0x34c4, (q15_t)0x8b62, (q15_t)0x34ad, (q15_t)0x8b58,
+  (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x347f, (q15_t)0x8b43, (q15_t)0x3468, (q15_t)0x8b39, (q15_t)0x3451, (q15_t)0x8b2f,
+  (q15_t)0x343a, (q15_t)0x8b25, (q15_t)0x3423, (q15_t)0x8b1a, (q15_t)0x340c, (q15_t)0x8b10, (q15_t)0x33f5, (q15_t)0x8b06,
+  (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x33c7, (q15_t)0x8af1, (q15_t)0x33b0, (q15_t)0x8ae7, (q15_t)0x3399, (q15_t)0x8add,
+  (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x336b, (q15_t)0x8ac9, (q15_t)0x3354, (q15_t)0x8abf, (q15_t)0x333d, (q15_t)0x8ab5,
+  (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x330f, (q15_t)0x8aa1, (q15_t)0x32f8, (q15_t)0x8a97, (q15_t)0x32e1, (q15_t)0x8a8d,
+  (q15_t)0x32ca, (q15_t)0x8a83, (q15_t)0x32b3, (q15_t)0x8a79, (q15_t)0x329c, (q15_t)0x8a6f, (q15_t)0x3285, (q15_t)0x8a65,
+  (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3257, (q15_t)0x8a51, (q15_t)0x3240, (q15_t)0x8a47, (q15_t)0x3228, (q15_t)0x8a3d,
+  (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x31fa, (q15_t)0x8a2a, (q15_t)0x31e3, (q15_t)0x8a20, (q15_t)0x31cc, (q15_t)0x8a16,
+  (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x319e, (q15_t)0x8a03, (q15_t)0x3186, (q15_t)0x89f9, (q15_t)0x316f, (q15_t)0x89ef,
+  (q15_t)0x3158, (q15_t)0x89e5, (q15_t)0x3141, (q15_t)0x89dc, (q15_t)0x312a, (q15_t)0x89d2, (q15_t)0x3112, (q15_t)0x89c8,
+  (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x30e4, (q15_t)0x89b5, (q15_t)0x30cd, (q15_t)0x89ac, (q15_t)0x30b6, (q15_t)0x89a2,
+  (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3087, (q15_t)0x898f, (q15_t)0x3070, (q15_t)0x8985, (q15_t)0x3059, (q15_t)0x897c,
+  (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x302a, (q15_t)0x8969, (q15_t)0x3013, (q15_t)0x8960, (q15_t)0x2ffb, (q15_t)0x8956,
+  (q15_t)0x2fe4, (q15_t)0x894d, (q15_t)0x2fcd, (q15_t)0x8943, (q15_t)0x2fb5, (q15_t)0x893a, (q15_t)0x2f9e, (q15_t)0x8931,
+  (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f6f, (q15_t)0x891e, (q15_t)0x2f58, (q15_t)0x8915, (q15_t)0x2f41, (q15_t)0x890b,
+  (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2f12, (q15_t)0x88f9, (q15_t)0x2efb, (q15_t)0x88f0, (q15_t)0x2ee3, (q15_t)0x88e6,
+  (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2eb5, (q15_t)0x88d4, (q15_t)0x2e9d, (q15_t)0x88cb, (q15_t)0x2e86, (q15_t)0x88c2,
+  (q15_t)0x2e6e, (q15_t)0x88b9, (q15_t)0x2e57, (q15_t)0x88af, (q15_t)0x2e3f, (q15_t)0x88a6, (q15_t)0x2e28, (q15_t)0x889d,
+  (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2df9, (q15_t)0x888b, (q15_t)0x2de2, (q15_t)0x8882, (q15_t)0x2dca, (q15_t)0x8879,
+  (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2d9b, (q15_t)0x8867, (q15_t)0x2d84, (q15_t)0x885e, (q15_t)0x2d6c, (q15_t)0x8855,
+  (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2d3d, (q15_t)0x8844, (q15_t)0x2d26, (q15_t)0x883b, (q15_t)0x2d0e, (q15_t)0x8832,
+  (q15_t)0x2cf7, (q15_t)0x8829, (q15_t)0x2cdf, (q15_t)0x8820, (q15_t)0x2cc8, (q15_t)0x8817, (q15_t)0x2cb0, (q15_t)0x880f,
+  (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c81, (q15_t)0x87fd, (q15_t)0x2c69, (q15_t)0x87f4, (q15_t)0x2c52, (q15_t)0x87ec,
+  (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2c23, (q15_t)0x87da, (q15_t)0x2c0b, (q15_t)0x87d2, (q15_t)0x2bf3, (q15_t)0x87c9,
+  (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2bc4, (q15_t)0x87b8, (q15_t)0x2bad, (q15_t)0x87af, (q15_t)0x2b95, (q15_t)0x87a7,
+  (q15_t)0x2b7d, (q15_t)0x879e, (q15_t)0x2b66, (q15_t)0x8795, (q15_t)0x2b4e, (q15_t)0x878d, (q15_t)0x2b36, (q15_t)0x8784,
+  (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2b07, (q15_t)0x8774, (q15_t)0x2aef, (q15_t)0x876b, (q15_t)0x2ad8, (q15_t)0x8763,
+  (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2aa8, (q15_t)0x8752, (q15_t)0x2a91, (q15_t)0x874a, (q15_t)0x2a79, (q15_t)0x8741,
+  (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a49, (q15_t)0x8731, (q15_t)0x2a32, (q15_t)0x8728, (q15_t)0x2a1a, (q15_t)0x8720,
+  (q15_t)0x2a02, (q15_t)0x8718, (q15_t)0x29eb, (q15_t)0x870f, (q15_t)0x29d3, (q15_t)0x8707, (q15_t)0x29bb, (q15_t)0x86ff,
+  (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x298b, (q15_t)0x86ef, (q15_t)0x2974, (q15_t)0x86e7, (q15_t)0x295c, (q15_t)0x86de,
+  (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x292c, (q15_t)0x86ce, (q15_t)0x2915, (q15_t)0x86c6, (q15_t)0x28fd, (q15_t)0x86be,
+  (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x28cd, (q15_t)0x86ae, (q15_t)0x28b5, (q15_t)0x86a6, (q15_t)0x289d, (q15_t)0x869e,
+  (q15_t)0x2886, (q15_t)0x8696, (q15_t)0x286e, (q15_t)0x868e, (q15_t)0x2856, (q15_t)0x8686, (q15_t)0x283e, (q15_t)0x867e,
+  (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x280e, (q15_t)0x866e, (q15_t)0x27f6, (q15_t)0x8667, (q15_t)0x27df, (q15_t)0x865f,
+  (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x27af, (q15_t)0x864f, (q15_t)0x2797, (q15_t)0x8647, (q15_t)0x277f, (q15_t)0x8640,
+  (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x274f, (q15_t)0x8630, (q15_t)0x2737, (q15_t)0x8628, (q15_t)0x271f, (q15_t)0x8621,
+  (q15_t)0x2707, (q15_t)0x8619, (q15_t)0x26ef, (q15_t)0x8611, (q15_t)0x26d8, (q15_t)0x860a, (q15_t)0x26c0, (q15_t)0x8602,
+  (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x2690, (q15_t)0x85f3, (q15_t)0x2678, (q15_t)0x85eb, (q15_t)0x2660, (q15_t)0x85e4,
+  (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x2630, (q15_t)0x85d5, (q15_t)0x2618, (q15_t)0x85cd, (q15_t)0x2600, (q15_t)0x85c6,
+  (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x25d0, (q15_t)0x85b7, (q15_t)0x25b8, (q15_t)0x85b0, (q15_t)0x25a0, (q15_t)0x85a8,
+  (q15_t)0x2588, (q15_t)0x85a1, (q15_t)0x2570, (q15_t)0x8599, (q15_t)0x2558, (q15_t)0x8592, (q15_t)0x2540, (q15_t)0x858b,
+  (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x250f, (q15_t)0x857c, (q15_t)0x24f7, (q15_t)0x8575, (q15_t)0x24df, (q15_t)0x856e,
+  (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x24af, (q15_t)0x855f, (q15_t)0x2497, (q15_t)0x8558, (q15_t)0x247f, (q15_t)0x8551,
+  (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x244f, (q15_t)0x8543, (q15_t)0x2437, (q15_t)0x853b, (q15_t)0x241f, (q15_t)0x8534,
+  (q15_t)0x2407, (q15_t)0x852d, (q15_t)0x23ee, (q15_t)0x8526, (q15_t)0x23d6, (q15_t)0x851f, (q15_t)0x23be, (q15_t)0x8518,
+  (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x238e, (q15_t)0x850a, (q15_t)0x2376, (q15_t)0x8503, (q15_t)0x235e, (q15_t)0x84fc,
+  (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x232d, (q15_t)0x84ee, (q15_t)0x2315, (q15_t)0x84e7, (q15_t)0x22fd, (q15_t)0x84e1,
+  (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x22cd, (q15_t)0x84d3, (q15_t)0x22b4, (q15_t)0x84cc, (q15_t)0x229c, (q15_t)0x84c5,
+  (q15_t)0x2284, (q15_t)0x84be, (q15_t)0x226c, (q15_t)0x84b8, (q15_t)0x2254, (q15_t)0x84b1, (q15_t)0x223b, (q15_t)0x84aa,
+  (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x220b, (q15_t)0x849d, (q15_t)0x21f3, (q15_t)0x8496, (q15_t)0x21da, (q15_t)0x848f,
+  (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x21aa, (q15_t)0x8482, (q15_t)0x2192, (q15_t)0x847c, (q15_t)0x2179, (q15_t)0x8475,
+  (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x2149, (q15_t)0x8468, (q15_t)0x2131, (q15_t)0x8461, (q15_t)0x2118, (q15_t)0x845b,
+  (q15_t)0x2100, (q15_t)0x8454, (q15_t)0x20e8, (q15_t)0x844e, (q15_t)0x20d0, (q15_t)0x8447, (q15_t)0x20b7, (q15_t)0x8441,
+  (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x2087, (q15_t)0x8434, (q15_t)0x206e, (q15_t)0x842e, (q15_t)0x2056, (q15_t)0x8427,
+  (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x2025, (q15_t)0x841b, (q15_t)0x200d, (q15_t)0x8415, (q15_t)0x1ff5, (q15_t)0x840e,
+  (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1fc4, (q15_t)0x8402, (q15_t)0x1fac, (q15_t)0x83fb, (q15_t)0x1f93, (q15_t)0x83f5,
+  (q15_t)0x1f7b, (q15_t)0x83ef, (q15_t)0x1f63, (q15_t)0x83e9, (q15_t)0x1f4a, (q15_t)0x83e3, (q15_t)0x1f32, (q15_t)0x83dd,
+  (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1f01, (q15_t)0x83d0, (q15_t)0x1ee9, (q15_t)0x83ca, (q15_t)0x1ed0, (q15_t)0x83c4,
+  (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1ea0, (q15_t)0x83b8, (q15_t)0x1e87, (q15_t)0x83b2, (q15_t)0x1e6f, (q15_t)0x83ac,
+  (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1e3e, (q15_t)0x83a0, (q15_t)0x1e25, (q15_t)0x839a, (q15_t)0x1e0d, (q15_t)0x8394,
+  (q15_t)0x1df5, (q15_t)0x838f, (q15_t)0x1ddc, (q15_t)0x8389, (q15_t)0x1dc4, (q15_t)0x8383, (q15_t)0x1dab, (q15_t)0x837d,
+  (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d7a, (q15_t)0x8371, (q15_t)0x1d62, (q15_t)0x836c, (q15_t)0x1d49, (q15_t)0x8366,
+  (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1d18, (q15_t)0x835a, (q15_t)0x1d00, (q15_t)0x8355, (q15_t)0x1ce8, (q15_t)0x834f,
+  (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1cb7, (q15_t)0x8344, (q15_t)0x1c9e, (q15_t)0x833e, (q15_t)0x1c86, (q15_t)0x8338,
+  (q15_t)0x1c6d, (q15_t)0x8333, (q15_t)0x1c55, (q15_t)0x832d, (q15_t)0x1c3c, (q15_t)0x8328, (q15_t)0x1c24, (q15_t)0x8322,
+  (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1bf2, (q15_t)0x8317, (q15_t)0x1bda, (q15_t)0x8312, (q15_t)0x1bc1, (q15_t)0x830c,
+  (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1b90, (q15_t)0x8301, (q15_t)0x1b78, (q15_t)0x82fc, (q15_t)0x1b5f, (q15_t)0x82f7,
+  (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1b2e, (q15_t)0x82ec, (q15_t)0x1b16, (q15_t)0x82e7, (q15_t)0x1afd, (q15_t)0x82e1,
+  (q15_t)0x1ae4, (q15_t)0x82dc, (q15_t)0x1acc, (q15_t)0x82d7, (q15_t)0x1ab3, (q15_t)0x82d1, (q15_t)0x1a9b, (q15_t)0x82cc,
+  (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a6a, (q15_t)0x82c2, (q15_t)0x1a51, (q15_t)0x82bd, (q15_t)0x1a38, (q15_t)0x82b7,
+  (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x1a07, (q15_t)0x82ad, (q15_t)0x19ef, (q15_t)0x82a8, (q15_t)0x19d6, (q15_t)0x82a3,
+  (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x19a5, (q15_t)0x8299, (q15_t)0x198c, (q15_t)0x8294, (q15_t)0x1973, (q15_t)0x828f,
+  (q15_t)0x195b, (q15_t)0x828a, (q15_t)0x1942, (q15_t)0x8285, (q15_t)0x192a, (q15_t)0x8280, (q15_t)0x1911, (q15_t)0x827b,
+  (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x18e0, (q15_t)0x8271, (q15_t)0x18c7, (q15_t)0x826c, (q15_t)0x18ae, (q15_t)0x8268,
+  (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x187d, (q15_t)0x825e, (q15_t)0x1864, (q15_t)0x8259, (q15_t)0x184c, (q15_t)0x8254,
+  (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x181a, (q15_t)0x824b, (q15_t)0x1802, (q15_t)0x8246, (q15_t)0x17e9, (q15_t)0x8241,
+  (q15_t)0x17d0, (q15_t)0x823d, (q15_t)0x17b7, (q15_t)0x8238, (q15_t)0x179f, (q15_t)0x8233, (q15_t)0x1786, (q15_t)0x822f,
+  (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x1755, (q15_t)0x8226, (q15_t)0x173c, (q15_t)0x8221, (q15_t)0x1723, (q15_t)0x821c,
+  (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x16f2, (q15_t)0x8213, (q15_t)0x16d9, (q15_t)0x820f, (q15_t)0x16c0, (q15_t)0x820a,
+  (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x168f, (q15_t)0x8201, (q15_t)0x1676, (q15_t)0x81fd, (q15_t)0x165d, (q15_t)0x81f9,
+  (q15_t)0x1645, (q15_t)0x81f4, (q15_t)0x162c, (q15_t)0x81f0, (q15_t)0x1613, (q15_t)0x81ec, (q15_t)0x15fa, (q15_t)0x81e7,
+  (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x15c9, (q15_t)0x81df, (q15_t)0x15b0, (q15_t)0x81da, (q15_t)0x1597, (q15_t)0x81d6,
+  (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x1566, (q15_t)0x81ce, (q15_t)0x154d, (q15_t)0x81c9, (q15_t)0x1534, (q15_t)0x81c5,
+  (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x1503, (q15_t)0x81bd, (q15_t)0x14ea, (q15_t)0x81b9, (q15_t)0x14d1, (q15_t)0x81b5,
+  (q15_t)0x14b8, (q15_t)0x81b1, (q15_t)0x149f, (q15_t)0x81ad, (q15_t)0x1487, (q15_t)0x81a9, (q15_t)0x146e, (q15_t)0x81a5,
+  (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x143c, (q15_t)0x819d, (q15_t)0x1423, (q15_t)0x8199, (q15_t)0x140b, (q15_t)0x8195,
+  (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x13d9, (q15_t)0x818d, (q15_t)0x13c0, (q15_t)0x8189, (q15_t)0x13a7, (q15_t)0x8185,
+  (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x1376, (q15_t)0x817d, (q15_t)0x135d, (q15_t)0x817a, (q15_t)0x1344, (q15_t)0x8176,
+  (q15_t)0x132b, (q15_t)0x8172, (q15_t)0x1312, (q15_t)0x816e, (q15_t)0x12f9, (q15_t)0x816b, (q15_t)0x12e0, (q15_t)0x8167,
+  (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x12af, (q15_t)0x815f, (q15_t)0x1296, (q15_t)0x815c, (q15_t)0x127d, (q15_t)0x8158,
+  (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x124b, (q15_t)0x8151, (q15_t)0x1232, (q15_t)0x814d, (q15_t)0x1219, (q15_t)0x814a,
+  (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x11e8, (q15_t)0x8143, (q15_t)0x11cf, (q15_t)0x813f, (q15_t)0x11b6, (q15_t)0x813c,
+  (q15_t)0x119d, (q15_t)0x8138, (q15_t)0x1184, (q15_t)0x8135, (q15_t)0x116b, (q15_t)0x8131, (q15_t)0x1152, (q15_t)0x812e,
+  (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x1121, (q15_t)0x8127, (q15_t)0x1108, (q15_t)0x8124, (q15_t)0x10ef, (q15_t)0x8121,
+  (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x10bd, (q15_t)0x811a, (q15_t)0x10a4, (q15_t)0x8117, (q15_t)0x108b, (q15_t)0x8113,
+  (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x1059, (q15_t)0x810d, (q15_t)0x1040, (q15_t)0x810a, (q15_t)0x1027, (q15_t)0x8107,
+  (q15_t)0x100e, (q15_t)0x8103, (q15_t)0xff5, (q15_t)0x8100, (q15_t)0xfdd, (q15_t)0x80fd, (q15_t)0xfc4, (q15_t)0x80fa,
+  (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xf92, (q15_t)0x80f4, (q15_t)0xf79, (q15_t)0x80f1, (q15_t)0xf60, (q15_t)0x80ee,
+  (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xf2e, (q15_t)0x80e8, (q15_t)0xf15, (q15_t)0x80e5, (q15_t)0xefc, (q15_t)0x80e2,
+  (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xeca, (q15_t)0x80dc, (q15_t)0xeb1, (q15_t)0x80d9, (q15_t)0xe98, (q15_t)0x80d6,
+  (q15_t)0xe7f, (q15_t)0x80d3, (q15_t)0xe66, (q15_t)0x80d1, (q15_t)0xe4d, (q15_t)0x80ce, (q15_t)0xe34, (q15_t)0x80cb,
+  (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xe02, (q15_t)0x80c5, (q15_t)0xde9, (q15_t)0x80c3, (q15_t)0xdd0, (q15_t)0x80c0,
+  (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xd9e, (q15_t)0x80bb, (q15_t)0xd85, (q15_t)0x80b8, (q15_t)0xd6c, (q15_t)0x80b5,
+  (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xd3a, (q15_t)0x80b0, (q15_t)0xd21, (q15_t)0x80ad, (q15_t)0xd08, (q15_t)0x80ab,
+  (q15_t)0xcef, (q15_t)0x80a8, (q15_t)0xcd6, (q15_t)0x80a6, (q15_t)0xcbd, (q15_t)0x80a3, (q15_t)0xca4, (q15_t)0x80a1,
+  (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc72, (q15_t)0x809c, (q15_t)0xc59, (q15_t)0x8099, (q15_t)0xc40, (q15_t)0x8097,
+  (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xc0e, (q15_t)0x8092, (q15_t)0xbf5, (q15_t)0x8090, (q15_t)0xbdc, (q15_t)0x808e,
+  (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xbaa, (q15_t)0x8089, (q15_t)0xb91, (q15_t)0x8087, (q15_t)0xb78, (q15_t)0x8084,
+  (q15_t)0xb5f, (q15_t)0x8082, (q15_t)0xb46, (q15_t)0x8080, (q15_t)0xb2d, (q15_t)0x807e, (q15_t)0xb14, (q15_t)0x807b,
+  (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xae2, (q15_t)0x8077, (q15_t)0xac9, (q15_t)0x8075, (q15_t)0xab0, (q15_t)0x8073,
+  (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa7e, (q15_t)0x806f, (q15_t)0xa65, (q15_t)0x806d, (q15_t)0xa4c, (q15_t)0x806b,
+  (q15_t)0xa33, (q15_t)0x8069, (q15_t)0xa19, (q15_t)0x8067, (q15_t)0xa00, (q15_t)0x8065, (q15_t)0x9e7, (q15_t)0x8063,
+  (q15_t)0x9ce, (q15_t)0x8061, (q15_t)0x9b5, (q15_t)0x805f, (q15_t)0x99c, (q15_t)0x805d, (q15_t)0x983, (q15_t)0x805b,
+  (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x951, (q15_t)0x8057, (q15_t)0x938, (q15_t)0x8056, (q15_t)0x91f, (q15_t)0x8054,
+  (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8ed, (q15_t)0x8050, (q15_t)0x8d4, (q15_t)0x804f, (q15_t)0x8bb, (q15_t)0x804d,
+  (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x888, (q15_t)0x8049, (q15_t)0x86f, (q15_t)0x8048, (q15_t)0x856, (q15_t)0x8046,
+  (q15_t)0x83d, (q15_t)0x8044, (q15_t)0x824, (q15_t)0x8043, (q15_t)0x80b, (q15_t)0x8041, (q15_t)0x7f2, (q15_t)0x8040,
+  (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x7c0, (q15_t)0x803d, (q15_t)0x7a7, (q15_t)0x803b, (q15_t)0x78e, (q15_t)0x803a,
+  (q15_t)0x775, (q15_t)0x8038, (q15_t)0x75b, (q15_t)0x8037, (q15_t)0x742, (q15_t)0x8035, (q15_t)0x729, (q15_t)0x8034,
+  (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6f7, (q15_t)0x8031, (q15_t)0x6de, (q15_t)0x8030, (q15_t)0x6c5, (q15_t)0x802e,
+  (q15_t)0x6ac, (q15_t)0x802d, (q15_t)0x693, (q15_t)0x802c, (q15_t)0x67a, (q15_t)0x802a, (q15_t)0x660, (q15_t)0x8029,
+  (q15_t)0x647, (q15_t)0x8028, (q15_t)0x62e, (q15_t)0x8027, (q15_t)0x615, (q15_t)0x8026, (q15_t)0x5fc, (q15_t)0x8024,
+  (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x5ca, (q15_t)0x8022, (q15_t)0x5b1, (q15_t)0x8021, (q15_t)0x598, (q15_t)0x8020,
+  (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x565, (q15_t)0x801e, (q15_t)0x54c, (q15_t)0x801d, (q15_t)0x533, (q15_t)0x801c,
+  (q15_t)0x51a, (q15_t)0x801b, (q15_t)0x501, (q15_t)0x801a, (q15_t)0x4e8, (q15_t)0x8019, (q15_t)0x4cf, (q15_t)0x8018,
+  (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x49c, (q15_t)0x8016, (q15_t)0x483, (q15_t)0x8015, (q15_t)0x46a, (q15_t)0x8014,
+  (q15_t)0x451, (q15_t)0x8013, (q15_t)0x438, (q15_t)0x8012, (q15_t)0x41f, (q15_t)0x8012, (q15_t)0x406, (q15_t)0x8011,
+  (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x3d4, (q15_t)0x800f, (q15_t)0x3ba, (q15_t)0x800e, (q15_t)0x3a1, (q15_t)0x800e,
+  (q15_t)0x388, (q15_t)0x800d, (q15_t)0x36f, (q15_t)0x800c, (q15_t)0x356, (q15_t)0x800c, (q15_t)0x33d, (q15_t)0x800b,
+  (q15_t)0x324, (q15_t)0x800a, (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2d8, (q15_t)0x8009,
+  (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x274, (q15_t)0x8007,
+  (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x242, (q15_t)0x8006, (q15_t)0x228, (q15_t)0x8005, (q15_t)0x20f, (q15_t)0x8005,
+  (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1ab, (q15_t)0x8003,
+  (q15_t)0x192, (q15_t)0x8003, (q15_t)0x178, (q15_t)0x8003, (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x146, (q15_t)0x8002,
+  (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x114, (q15_t)0x8002, (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xe2, (q15_t)0x8001,
+  (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xaf, (q15_t)0x8001, (q15_t)0x96, (q15_t)0x8001, (q15_t)0x7d, (q15_t)0x8001,
+  (q15_t)0x64, (q15_t)0x8001, (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x32, (q15_t)0x8001, (q15_t)0x19, (q15_t)0x8001
+};
+
+static const q15_t ALIGN4 WeightsQ15_8192[16384] = {
+  (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xfffa, (q15_t)0x7fff, (q15_t)0xfff4, (q15_t)0x7fff, (q15_t)0xffee,
+  (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffe1, (q15_t)0x7fff, (q15_t)0xffdb, (q15_t)0x7fff, (q15_t)0xffd5,
+  (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffc8, (q15_t)0x7fff, (q15_t)0xffc2, (q15_t)0x7fff, (q15_t)0xffbb,
+  (q15_t)0x7fff, (q15_t)0xffb5, (q15_t)0x7fff, (q15_t)0xffaf, (q15_t)0x7fff, (q15_t)0xffa9, (q15_t)0x7fff, (q15_t)0xffa2,
+  (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff96, (q15_t)0x7fff, (q15_t)0xff8f, (q15_t)0x7fff, (q15_t)0xff89,
+  (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff7d, (q15_t)0x7fff, (q15_t)0xff76, (q15_t)0x7fff, (q15_t)0xff70,
+  (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff63, (q15_t)0x7fff, (q15_t)0xff5d, (q15_t)0x7fff, (q15_t)0xff57,
+  (q15_t)0x7fff, (q15_t)0xff51, (q15_t)0x7fff, (q15_t)0xff4a, (q15_t)0x7fff, (q15_t)0xff44, (q15_t)0x7fff, (q15_t)0xff3e,
+  (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff31, (q15_t)0x7fff, (q15_t)0xff2b, (q15_t)0x7fff, (q15_t)0xff25,
+  (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff18, (q15_t)0x7fff, (q15_t)0xff12, (q15_t)0x7fff, (q15_t)0xff0b,
+  (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeff, (q15_t)0x7ffe, (q15_t)0xfef9, (q15_t)0x7ffe, (q15_t)0xfef2,
+  (q15_t)0x7ffe, (q15_t)0xfeec, (q15_t)0x7ffe, (q15_t)0xfee6, (q15_t)0x7ffe, (q15_t)0xfedf, (q15_t)0x7ffe, (q15_t)0xfed9,
+  (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfecd, (q15_t)0x7ffe, (q15_t)0xfec6, (q15_t)0x7ffe, (q15_t)0xfec0,
+  (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfeb3, (q15_t)0x7ffe, (q15_t)0xfead, (q15_t)0x7ffe, (q15_t)0xfea7,
+  (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffe, (q15_t)0xfe9a, (q15_t)0x7ffd, (q15_t)0xfe94, (q15_t)0x7ffd, (q15_t)0xfe8e,
+  (q15_t)0x7ffd, (q15_t)0xfe88, (q15_t)0x7ffd, (q15_t)0xfe81, (q15_t)0x7ffd, (q15_t)0xfe7b, (q15_t)0x7ffd, (q15_t)0xfe75,
+  (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe68, (q15_t)0x7ffd, (q15_t)0xfe62, (q15_t)0x7ffd, (q15_t)0xfe5c,
+  (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffd, (q15_t)0xfe4f, (q15_t)0x7ffd, (q15_t)0xfe49, (q15_t)0x7ffc, (q15_t)0xfe42,
+  (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe36, (q15_t)0x7ffc, (q15_t)0xfe30, (q15_t)0x7ffc, (q15_t)0xfe29,
+  (q15_t)0x7ffc, (q15_t)0xfe23, (q15_t)0x7ffc, (q15_t)0xfe1d, (q15_t)0x7ffc, (q15_t)0xfe16, (q15_t)0x7ffc, (q15_t)0xfe10,
+  (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffc, (q15_t)0xfe04, (q15_t)0x7ffb, (q15_t)0xfdfd, (q15_t)0x7ffb, (q15_t)0xfdf7,
+  (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdea, (q15_t)0x7ffb, (q15_t)0xfde4, (q15_t)0x7ffb, (q15_t)0xfdde,
+  (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffb, (q15_t)0xfdd1, (q15_t)0x7ffb, (q15_t)0xfdcb, (q15_t)0x7ffb, (q15_t)0xfdc5,
+  (q15_t)0x7ffa, (q15_t)0xfdbe, (q15_t)0x7ffa, (q15_t)0xfdb8, (q15_t)0x7ffa, (q15_t)0xfdb2, (q15_t)0x7ffa, (q15_t)0xfdac,
+  (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ffa, (q15_t)0xfd9f, (q15_t)0x7ffa, (q15_t)0xfd99, (q15_t)0x7ffa, (q15_t)0xfd93,
+  (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd86, (q15_t)0x7ff9, (q15_t)0xfd80, (q15_t)0x7ff9, (q15_t)0xfd79,
+  (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff9, (q15_t)0xfd6d, (q15_t)0x7ff9, (q15_t)0xfd67, (q15_t)0x7ff9, (q15_t)0xfd60,
+  (q15_t)0x7ff8, (q15_t)0xfd5a, (q15_t)0x7ff8, (q15_t)0xfd54, (q15_t)0x7ff8, (q15_t)0xfd4d, (q15_t)0x7ff8, (q15_t)0xfd47,
+  (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff8, (q15_t)0xfd3b, (q15_t)0x7ff8, (q15_t)0xfd34, (q15_t)0x7ff8, (q15_t)0xfd2e,
+  (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd21, (q15_t)0x7ff7, (q15_t)0xfd1b, (q15_t)0x7ff7, (q15_t)0xfd15,
+  (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff7, (q15_t)0xfd08, (q15_t)0x7ff7, (q15_t)0xfd02, (q15_t)0x7ff6, (q15_t)0xfcfc,
+  (q15_t)0x7ff6, (q15_t)0xfcf5, (q15_t)0x7ff6, (q15_t)0xfcef, (q15_t)0x7ff6, (q15_t)0xfce9, (q15_t)0x7ff6, (q15_t)0xfce3,
+  (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcd6, (q15_t)0x7ff5, (q15_t)0xfcd0, (q15_t)0x7ff5, (q15_t)0xfcc9,
+  (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff5, (q15_t)0xfcbd, (q15_t)0x7ff5, (q15_t)0xfcb7, (q15_t)0x7ff5, (q15_t)0xfcb0,
+  (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfca4, (q15_t)0x7ff4, (q15_t)0xfc9e, (q15_t)0x7ff4, (q15_t)0xfc97,
+  (q15_t)0x7ff4, (q15_t)0xfc91, (q15_t)0x7ff4, (q15_t)0xfc8b, (q15_t)0x7ff3, (q15_t)0xfc84, (q15_t)0x7ff3, (q15_t)0xfc7e,
+  (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff3, (q15_t)0xfc72, (q15_t)0x7ff3, (q15_t)0xfc6b, (q15_t)0x7ff2, (q15_t)0xfc65,
+  (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc58, (q15_t)0x7ff2, (q15_t)0xfc52, (q15_t)0x7ff2, (q15_t)0xfc4c,
+  (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc3f, (q15_t)0x7ff1, (q15_t)0xfc39, (q15_t)0x7ff1, (q15_t)0xfc33,
+  (q15_t)0x7ff1, (q15_t)0xfc2c, (q15_t)0x7ff1, (q15_t)0xfc26, (q15_t)0x7ff0, (q15_t)0xfc20, (q15_t)0x7ff0, (q15_t)0xfc1a,
+  (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7ff0, (q15_t)0xfc0d, (q15_t)0x7ff0, (q15_t)0xfc07, (q15_t)0x7fef, (q15_t)0xfc01,
+  (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fef, (q15_t)0xfbf4, (q15_t)0x7fef, (q15_t)0xfbee, (q15_t)0x7fef, (q15_t)0xfbe7,
+  (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbdb, (q15_t)0x7fee, (q15_t)0xfbd5, (q15_t)0x7fee, (q15_t)0xfbce,
+  (q15_t)0x7fee, (q15_t)0xfbc8, (q15_t)0x7fed, (q15_t)0xfbc2, (q15_t)0x7fed, (q15_t)0xfbbb, (q15_t)0x7fed, (q15_t)0xfbb5,
+  (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fed, (q15_t)0xfba9, (q15_t)0x7fec, (q15_t)0xfba2, (q15_t)0x7fec, (q15_t)0xfb9c,
+  (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7fec, (q15_t)0xfb8f, (q15_t)0x7fec, (q15_t)0xfb89, (q15_t)0x7feb, (q15_t)0xfb83,
+  (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7feb, (q15_t)0xfb76, (q15_t)0x7feb, (q15_t)0xfb70, (q15_t)0x7fea, (q15_t)0xfb6a,
+  (q15_t)0x7fea, (q15_t)0xfb64, (q15_t)0x7fea, (q15_t)0xfb5d, (q15_t)0x7fea, (q15_t)0xfb57, (q15_t)0x7fea, (q15_t)0xfb51,
+  (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe9, (q15_t)0xfb44, (q15_t)0x7fe9, (q15_t)0xfb3e, (q15_t)0x7fe9, (q15_t)0xfb38,
+  (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe8, (q15_t)0xfb2b, (q15_t)0x7fe8, (q15_t)0xfb25, (q15_t)0x7fe8, (q15_t)0xfb1e,
+  (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe7, (q15_t)0xfb12, (q15_t)0x7fe7, (q15_t)0xfb0c, (q15_t)0x7fe7, (q15_t)0xfb05,
+  (q15_t)0x7fe6, (q15_t)0xfaff, (q15_t)0x7fe6, (q15_t)0xfaf9, (q15_t)0x7fe6, (q15_t)0xfaf3, (q15_t)0x7fe6, (q15_t)0xfaec,
+  (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe5, (q15_t)0xfae0, (q15_t)0x7fe5, (q15_t)0xfad9, (q15_t)0x7fe5, (q15_t)0xfad3,
+  (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe4, (q15_t)0xfac7, (q15_t)0x7fe4, (q15_t)0xfac0, (q15_t)0x7fe4, (q15_t)0xfaba,
+  (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe3, (q15_t)0xfaad, (q15_t)0x7fe3, (q15_t)0xfaa7, (q15_t)0x7fe3, (q15_t)0xfaa1,
+  (q15_t)0x7fe2, (q15_t)0xfa9b, (q15_t)0x7fe2, (q15_t)0xfa94, (q15_t)0x7fe2, (q15_t)0xfa8e, (q15_t)0x7fe2, (q15_t)0xfa88,
+  (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe1, (q15_t)0xfa7b, (q15_t)0x7fe1, (q15_t)0xfa75, (q15_t)0x7fe0, (q15_t)0xfa6f,
+  (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fe0, (q15_t)0xfa62, (q15_t)0x7fe0, (q15_t)0xfa5c, (q15_t)0x7fdf, (q15_t)0xfa56,
+  (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fdf, (q15_t)0xfa49, (q15_t)0x7fdf, (q15_t)0xfa43, (q15_t)0x7fde, (q15_t)0xfa3c,
+  (q15_t)0x7fde, (q15_t)0xfa36, (q15_t)0x7fde, (q15_t)0xfa30, (q15_t)0x7fdd, (q15_t)0xfa2a, (q15_t)0x7fdd, (q15_t)0xfa23,
+  (q15_t)0x7fdd, (q15_t)0xfa1d, (q15_t)0x7fdd, (q15_t)0xfa17, (q15_t)0x7fdc, (q15_t)0xfa11, (q15_t)0x7fdc, (q15_t)0xfa0a,
+  (q15_t)0x7fdc, (q15_t)0xfa04, (q15_t)0x7fdb, (q15_t)0xf9fe, (q15_t)0x7fdb, (q15_t)0xf9f7, (q15_t)0x7fdb, (q15_t)0xf9f1,
+  (q15_t)0x7fda, (q15_t)0xf9eb, (q15_t)0x7fda, (q15_t)0xf9e5, (q15_t)0x7fda, (q15_t)0xf9de, (q15_t)0x7fda, (q15_t)0xf9d8,
+  (q15_t)0x7fd9, (q15_t)0xf9d2, (q15_t)0x7fd9, (q15_t)0xf9cb, (q15_t)0x7fd9, (q15_t)0xf9c5, (q15_t)0x7fd8, (q15_t)0xf9bf,
+  (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd8, (q15_t)0xf9b2, (q15_t)0x7fd7, (q15_t)0xf9ac, (q15_t)0x7fd7, (q15_t)0xf9a6,
+  (q15_t)0x7fd7, (q15_t)0xf9a0, (q15_t)0x7fd6, (q15_t)0xf999, (q15_t)0x7fd6, (q15_t)0xf993, (q15_t)0x7fd6, (q15_t)0xf98d,
+  (q15_t)0x7fd6, (q15_t)0xf986, (q15_t)0x7fd5, (q15_t)0xf980, (q15_t)0x7fd5, (q15_t)0xf97a, (q15_t)0x7fd5, (q15_t)0xf974,
+  (q15_t)0x7fd4, (q15_t)0xf96d, (q15_t)0x7fd4, (q15_t)0xf967, (q15_t)0x7fd4, (q15_t)0xf961, (q15_t)0x7fd3, (q15_t)0xf95b,
+  (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fd3, (q15_t)0xf94e, (q15_t)0x7fd2, (q15_t)0xf948, (q15_t)0x7fd2, (q15_t)0xf941,
+  (q15_t)0x7fd2, (q15_t)0xf93b, (q15_t)0x7fd1, (q15_t)0xf935, (q15_t)0x7fd1, (q15_t)0xf92f, (q15_t)0x7fd1, (q15_t)0xf928,
+  (q15_t)0x7fd0, (q15_t)0xf922, (q15_t)0x7fd0, (q15_t)0xf91c, (q15_t)0x7fd0, (q15_t)0xf916, (q15_t)0x7fcf, (q15_t)0xf90f,
+  (q15_t)0x7fcf, (q15_t)0xf909, (q15_t)0x7fcf, (q15_t)0xf903, (q15_t)0x7fce, (q15_t)0xf8fc, (q15_t)0x7fce, (q15_t)0xf8f6,
+  (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fcd, (q15_t)0xf8ea, (q15_t)0x7fcd, (q15_t)0xf8e3, (q15_t)0x7fcd, (q15_t)0xf8dd,
+  (q15_t)0x7fcc, (q15_t)0xf8d7, (q15_t)0x7fcc, (q15_t)0xf8d0, (q15_t)0x7fcb, (q15_t)0xf8ca, (q15_t)0x7fcb, (q15_t)0xf8c4,
+  (q15_t)0x7fcb, (q15_t)0xf8be, (q15_t)0x7fca, (q15_t)0xf8b7, (q15_t)0x7fca, (q15_t)0xf8b1, (q15_t)0x7fca, (q15_t)0xf8ab,
+  (q15_t)0x7fc9, (q15_t)0xf8a5, (q15_t)0x7fc9, (q15_t)0xf89e, (q15_t)0x7fc9, (q15_t)0xf898, (q15_t)0x7fc8, (q15_t)0xf892,
+  (q15_t)0x7fc8, (q15_t)0xf88b, (q15_t)0x7fc7, (q15_t)0xf885, (q15_t)0x7fc7, (q15_t)0xf87f, (q15_t)0x7fc7, (q15_t)0xf879,
+  (q15_t)0x7fc6, (q15_t)0xf872, (q15_t)0x7fc6, (q15_t)0xf86c, (q15_t)0x7fc6, (q15_t)0xf866, (q15_t)0x7fc5, (q15_t)0xf860,
+  (q15_t)0x7fc5, (q15_t)0xf859, (q15_t)0x7fc5, (q15_t)0xf853, (q15_t)0x7fc4, (q15_t)0xf84d, (q15_t)0x7fc4, (q15_t)0xf846,
+  (q15_t)0x7fc3, (q15_t)0xf840, (q15_t)0x7fc3, (q15_t)0xf83a, (q15_t)0x7fc3, (q15_t)0xf834, (q15_t)0x7fc2, (q15_t)0xf82d,
+  (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fc1, (q15_t)0xf821, (q15_t)0x7fc1, (q15_t)0xf81b, (q15_t)0x7fc1, (q15_t)0xf814,
+  (q15_t)0x7fc0, (q15_t)0xf80e, (q15_t)0x7fc0, (q15_t)0xf808, (q15_t)0x7fc0, (q15_t)0xf802, (q15_t)0x7fbf, (q15_t)0xf7fb,
+  (q15_t)0x7fbf, (q15_t)0xf7f5, (q15_t)0x7fbe, (q15_t)0xf7ef, (q15_t)0x7fbe, (q15_t)0xf7e8, (q15_t)0x7fbe, (q15_t)0xf7e2,
+  (q15_t)0x7fbd, (q15_t)0xf7dc, (q15_t)0x7fbd, (q15_t)0xf7d6, (q15_t)0x7fbc, (q15_t)0xf7cf, (q15_t)0x7fbc, (q15_t)0xf7c9,
+  (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fbb, (q15_t)0xf7bd, (q15_t)0x7fbb, (q15_t)0xf7b6, (q15_t)0x7fba, (q15_t)0xf7b0,
+  (q15_t)0x7fba, (q15_t)0xf7aa, (q15_t)0x7fb9, (q15_t)0xf7a3, (q15_t)0x7fb9, (q15_t)0xf79d, (q15_t)0x7fb9, (q15_t)0xf797,
+  (q15_t)0x7fb8, (q15_t)0xf791, (q15_t)0x7fb8, (q15_t)0xf78a, (q15_t)0x7fb7, (q15_t)0xf784, (q15_t)0x7fb7, (q15_t)0xf77e,
+  (q15_t)0x7fb7, (q15_t)0xf778, (q15_t)0x7fb6, (q15_t)0xf771, (q15_t)0x7fb6, (q15_t)0xf76b, (q15_t)0x7fb5, (q15_t)0xf765,
+  (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fb4, (q15_t)0xf758, (q15_t)0x7fb4, (q15_t)0xf752, (q15_t)0x7fb4, (q15_t)0xf74c,
+  (q15_t)0x7fb3, (q15_t)0xf745, (q15_t)0x7fb3, (q15_t)0xf73f, (q15_t)0x7fb2, (q15_t)0xf739, (q15_t)0x7fb2, (q15_t)0xf733,
+  (q15_t)0x7fb1, (q15_t)0xf72c, (q15_t)0x7fb1, (q15_t)0xf726, (q15_t)0x7fb1, (q15_t)0xf720, (q15_t)0x7fb0, (q15_t)0xf71a,
+  (q15_t)0x7fb0, (q15_t)0xf713, (q15_t)0x7faf, (q15_t)0xf70d, (q15_t)0x7faf, (q15_t)0xf707, (q15_t)0x7fae, (q15_t)0xf700,
+  (q15_t)0x7fae, (q15_t)0xf6fa, (q15_t)0x7fae, (q15_t)0xf6f4, (q15_t)0x7fad, (q15_t)0xf6ee, (q15_t)0x7fad, (q15_t)0xf6e7,
+  (q15_t)0x7fac, (q15_t)0xf6e1, (q15_t)0x7fac, (q15_t)0xf6db, (q15_t)0x7fab, (q15_t)0xf6d5, (q15_t)0x7fab, (q15_t)0xf6ce,
+  (q15_t)0x7faa, (q15_t)0xf6c8, (q15_t)0x7faa, (q15_t)0xf6c2, (q15_t)0x7fa9, (q15_t)0xf6bc, (q15_t)0x7fa9, (q15_t)0xf6b5,
+  (q15_t)0x7fa9, (q15_t)0xf6af, (q15_t)0x7fa8, (q15_t)0xf6a9, (q15_t)0x7fa8, (q15_t)0xf6a2, (q15_t)0x7fa7, (q15_t)0xf69c,
+  (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7fa6, (q15_t)0xf690, (q15_t)0x7fa6, (q15_t)0xf689, (q15_t)0x7fa5, (q15_t)0xf683,
+  (q15_t)0x7fa5, (q15_t)0xf67d, (q15_t)0x7fa4, (q15_t)0xf677, (q15_t)0x7fa4, (q15_t)0xf670, (q15_t)0x7fa3, (q15_t)0xf66a,
+  (q15_t)0x7fa3, (q15_t)0xf664, (q15_t)0x7fa3, (q15_t)0xf65e, (q15_t)0x7fa2, (q15_t)0xf657, (q15_t)0x7fa2, (q15_t)0xf651,
+  (q15_t)0x7fa1, (q15_t)0xf64b, (q15_t)0x7fa1, (q15_t)0xf644, (q15_t)0x7fa0, (q15_t)0xf63e, (q15_t)0x7fa0, (q15_t)0xf638,
+  (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f9f, (q15_t)0xf62b, (q15_t)0x7f9e, (q15_t)0xf625, (q15_t)0x7f9e, (q15_t)0xf61f,
+  (q15_t)0x7f9d, (q15_t)0xf619, (q15_t)0x7f9d, (q15_t)0xf612, (q15_t)0x7f9c, (q15_t)0xf60c, (q15_t)0x7f9c, (q15_t)0xf606,
+  (q15_t)0x7f9b, (q15_t)0xf600, (q15_t)0x7f9b, (q15_t)0xf5f9, (q15_t)0x7f9a, (q15_t)0xf5f3, (q15_t)0x7f9a, (q15_t)0xf5ed,
+  (q15_t)0x7f99, (q15_t)0xf5e7, (q15_t)0x7f99, (q15_t)0xf5e0, (q15_t)0x7f98, (q15_t)0xf5da, (q15_t)0x7f98, (q15_t)0xf5d4,
+  (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f97, (q15_t)0xf5c7, (q15_t)0x7f96, (q15_t)0xf5c1, (q15_t)0x7f96, (q15_t)0xf5bb,
+  (q15_t)0x7f95, (q15_t)0xf5b4, (q15_t)0x7f95, (q15_t)0xf5ae, (q15_t)0x7f94, (q15_t)0xf5a8, (q15_t)0x7f94, (q15_t)0xf5a2,
+  (q15_t)0x7f93, (q15_t)0xf59b, (q15_t)0x7f93, (q15_t)0xf595, (q15_t)0x7f92, (q15_t)0xf58f, (q15_t)0x7f92, (q15_t)0xf589,
+  (q15_t)0x7f91, (q15_t)0xf582, (q15_t)0x7f91, (q15_t)0xf57c, (q15_t)0x7f90, (q15_t)0xf576, (q15_t)0x7f90, (q15_t)0xf570,
+  (q15_t)0x7f8f, (q15_t)0xf569, (q15_t)0x7f8f, (q15_t)0xf563, (q15_t)0x7f8e, (q15_t)0xf55d, (q15_t)0x7f8e, (q15_t)0xf556,
+  (q15_t)0x7f8d, (q15_t)0xf550, (q15_t)0x7f8d, (q15_t)0xf54a, (q15_t)0x7f8c, (q15_t)0xf544, (q15_t)0x7f8b, (q15_t)0xf53d,
+  (q15_t)0x7f8b, (q15_t)0xf537, (q15_t)0x7f8a, (q15_t)0xf531, (q15_t)0x7f8a, (q15_t)0xf52b, (q15_t)0x7f89, (q15_t)0xf524,
+  (q15_t)0x7f89, (q15_t)0xf51e, (q15_t)0x7f88, (q15_t)0xf518, (q15_t)0x7f88, (q15_t)0xf512, (q15_t)0x7f87, (q15_t)0xf50b,
+  (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f86, (q15_t)0xf4ff, (q15_t)0x7f86, (q15_t)0xf4f9, (q15_t)0x7f85, (q15_t)0xf4f2,
+  (q15_t)0x7f85, (q15_t)0xf4ec, (q15_t)0x7f84, (q15_t)0xf4e6, (q15_t)0x7f83, (q15_t)0xf4e0, (q15_t)0x7f83, (q15_t)0xf4d9,
+  (q15_t)0x7f82, (q15_t)0xf4d3, (q15_t)0x7f82, (q15_t)0xf4cd, (q15_t)0x7f81, (q15_t)0xf4c6, (q15_t)0x7f81, (q15_t)0xf4c0,
+  (q15_t)0x7f80, (q15_t)0xf4ba, (q15_t)0x7f80, (q15_t)0xf4b4, (q15_t)0x7f7f, (q15_t)0xf4ad, (q15_t)0x7f7e, (q15_t)0xf4a7,
+  (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f7d, (q15_t)0xf49b, (q15_t)0x7f7d, (q15_t)0xf494, (q15_t)0x7f7c, (q15_t)0xf48e,
+  (q15_t)0x7f7c, (q15_t)0xf488, (q15_t)0x7f7b, (q15_t)0xf482, (q15_t)0x7f7b, (q15_t)0xf47b, (q15_t)0x7f7a, (q15_t)0xf475,
+  (q15_t)0x7f79, (q15_t)0xf46f, (q15_t)0x7f79, (q15_t)0xf469, (q15_t)0x7f78, (q15_t)0xf462, (q15_t)0x7f78, (q15_t)0xf45c,
+  (q15_t)0x7f77, (q15_t)0xf456, (q15_t)0x7f77, (q15_t)0xf450, (q15_t)0x7f76, (q15_t)0xf449, (q15_t)0x7f75, (q15_t)0xf443,
+  (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f74, (q15_t)0xf437, (q15_t)0x7f74, (q15_t)0xf430, (q15_t)0x7f73, (q15_t)0xf42a,
+  (q15_t)0x7f72, (q15_t)0xf424, (q15_t)0x7f72, (q15_t)0xf41e, (q15_t)0x7f71, (q15_t)0xf417, (q15_t)0x7f71, (q15_t)0xf411,
+  (q15_t)0x7f70, (q15_t)0xf40b, (q15_t)0x7f70, (q15_t)0xf405, (q15_t)0x7f6f, (q15_t)0xf3fe, (q15_t)0x7f6e, (q15_t)0xf3f8,
+  (q15_t)0x7f6e, (q15_t)0xf3f2, (q15_t)0x7f6d, (q15_t)0xf3ec, (q15_t)0x7f6d, (q15_t)0xf3e5, (q15_t)0x7f6c, (q15_t)0xf3df,
+  (q15_t)0x7f6b, (q15_t)0xf3d9, (q15_t)0x7f6b, (q15_t)0xf3d2, (q15_t)0x7f6a, (q15_t)0xf3cc, (q15_t)0x7f6a, (q15_t)0xf3c6,
+  (q15_t)0x7f69, (q15_t)0xf3c0, (q15_t)0x7f68, (q15_t)0xf3b9, (q15_t)0x7f68, (q15_t)0xf3b3, (q15_t)0x7f67, (q15_t)0xf3ad,
+  (q15_t)0x7f67, (q15_t)0xf3a7, (q15_t)0x7f66, (q15_t)0xf3a0, (q15_t)0x7f65, (q15_t)0xf39a, (q15_t)0x7f65, (q15_t)0xf394,
+  (q15_t)0x7f64, (q15_t)0xf38e, (q15_t)0x7f64, (q15_t)0xf387, (q15_t)0x7f63, (q15_t)0xf381, (q15_t)0x7f62, (q15_t)0xf37b,
+  (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f61, (q15_t)0xf36e, (q15_t)0x7f60, (q15_t)0xf368, (q15_t)0x7f60, (q15_t)0xf362,
+  (q15_t)0x7f5f, (q15_t)0xf35c, (q15_t)0x7f5f, (q15_t)0xf355, (q15_t)0x7f5e, (q15_t)0xf34f, (q15_t)0x7f5d, (q15_t)0xf349,
+  (q15_t)0x7f5d, (q15_t)0xf343, (q15_t)0x7f5c, (q15_t)0xf33c, (q15_t)0x7f5b, (q15_t)0xf336, (q15_t)0x7f5b, (q15_t)0xf330,
+  (q15_t)0x7f5a, (q15_t)0xf32a, (q15_t)0x7f5a, (q15_t)0xf323, (q15_t)0x7f59, (q15_t)0xf31d, (q15_t)0x7f58, (q15_t)0xf317,
+  (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f57, (q15_t)0xf30a, (q15_t)0x7f56, (q15_t)0xf304, (q15_t)0x7f56, (q15_t)0xf2fe,
+  (q15_t)0x7f55, (q15_t)0xf2f8, (q15_t)0x7f55, (q15_t)0xf2f1, (q15_t)0x7f54, (q15_t)0xf2eb, (q15_t)0x7f53, (q15_t)0xf2e5,
+  (q15_t)0x7f53, (q15_t)0xf2df, (q15_t)0x7f52, (q15_t)0xf2d8, (q15_t)0x7f51, (q15_t)0xf2d2, (q15_t)0x7f51, (q15_t)0xf2cc,
+  (q15_t)0x7f50, (q15_t)0xf2c6, (q15_t)0x7f4f, (q15_t)0xf2bf, (q15_t)0x7f4f, (q15_t)0xf2b9, (q15_t)0x7f4e, (q15_t)0xf2b3,
+  (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f4d, (q15_t)0xf2a6, (q15_t)0x7f4c, (q15_t)0xf2a0, (q15_t)0x7f4b, (q15_t)0xf29a,
+  (q15_t)0x7f4b, (q15_t)0xf294, (q15_t)0x7f4a, (q15_t)0xf28d, (q15_t)0x7f49, (q15_t)0xf287, (q15_t)0x7f49, (q15_t)0xf281,
+  (q15_t)0x7f48, (q15_t)0xf27b, (q15_t)0x7f47, (q15_t)0xf274, (q15_t)0x7f47, (q15_t)0xf26e, (q15_t)0x7f46, (q15_t)0xf268,
+  (q15_t)0x7f45, (q15_t)0xf262, (q15_t)0x7f45, (q15_t)0xf25b, (q15_t)0x7f44, (q15_t)0xf255, (q15_t)0x7f43, (q15_t)0xf24f,
+  (q15_t)0x7f43, (q15_t)0xf249, (q15_t)0x7f42, (q15_t)0xf242, (q15_t)0x7f41, (q15_t)0xf23c, (q15_t)0x7f41, (q15_t)0xf236,
+  (q15_t)0x7f40, (q15_t)0xf230, (q15_t)0x7f3f, (q15_t)0xf229, (q15_t)0x7f3f, (q15_t)0xf223, (q15_t)0x7f3e, (q15_t)0xf21d,
+  (q15_t)0x7f3d, (q15_t)0xf217, (q15_t)0x7f3d, (q15_t)0xf210, (q15_t)0x7f3c, (q15_t)0xf20a, (q15_t)0x7f3b, (q15_t)0xf204,
+  (q15_t)0x7f3b, (q15_t)0xf1fe, (q15_t)0x7f3a, (q15_t)0xf1f7, (q15_t)0x7f39, (q15_t)0xf1f1, (q15_t)0x7f39, (q15_t)0xf1eb,
+  (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f37, (q15_t)0xf1de, (q15_t)0x7f36, (q15_t)0xf1d8, (q15_t)0x7f36, (q15_t)0xf1d2,
+  (q15_t)0x7f35, (q15_t)0xf1cc, (q15_t)0x7f34, (q15_t)0xf1c6, (q15_t)0x7f34, (q15_t)0xf1bf, (q15_t)0x7f33, (q15_t)0xf1b9,
+  (q15_t)0x7f32, (q15_t)0xf1b3, (q15_t)0x7f32, (q15_t)0xf1ad, (q15_t)0x7f31, (q15_t)0xf1a6, (q15_t)0x7f30, (q15_t)0xf1a0,
+  (q15_t)0x7f2f, (q15_t)0xf19a, (q15_t)0x7f2f, (q15_t)0xf194, (q15_t)0x7f2e, (q15_t)0xf18d, (q15_t)0x7f2d, (q15_t)0xf187,
+  (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f2c, (q15_t)0xf17b, (q15_t)0x7f2b, (q15_t)0xf174, (q15_t)0x7f2a, (q15_t)0xf16e,
+  (q15_t)0x7f2a, (q15_t)0xf168, (q15_t)0x7f29, (q15_t)0xf162, (q15_t)0x7f28, (q15_t)0xf15b, (q15_t)0x7f28, (q15_t)0xf155,
+  (q15_t)0x7f27, (q15_t)0xf14f, (q15_t)0x7f26, (q15_t)0xf149, (q15_t)0x7f25, (q15_t)0xf142, (q15_t)0x7f25, (q15_t)0xf13c,
+  (q15_t)0x7f24, (q15_t)0xf136, (q15_t)0x7f23, (q15_t)0xf130, (q15_t)0x7f23, (q15_t)0xf129, (q15_t)0x7f22, (q15_t)0xf123,
+  (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f20, (q15_t)0xf117, (q15_t)0x7f20, (q15_t)0xf110, (q15_t)0x7f1f, (q15_t)0xf10a,
+  (q15_t)0x7f1e, (q15_t)0xf104, (q15_t)0x7f1d, (q15_t)0xf0fe, (q15_t)0x7f1d, (q15_t)0xf0f8, (q15_t)0x7f1c, (q15_t)0xf0f1,
+  (q15_t)0x7f1b, (q15_t)0xf0eb, (q15_t)0x7f1a, (q15_t)0xf0e5, (q15_t)0x7f1a, (q15_t)0xf0df, (q15_t)0x7f19, (q15_t)0xf0d8,
+  (q15_t)0x7f18, (q15_t)0xf0d2, (q15_t)0x7f17, (q15_t)0xf0cc, (q15_t)0x7f17, (q15_t)0xf0c6, (q15_t)0x7f16, (q15_t)0xf0bf,
+  (q15_t)0x7f15, (q15_t)0xf0b9, (q15_t)0x7f14, (q15_t)0xf0b3, (q15_t)0x7f14, (q15_t)0xf0ad, (q15_t)0x7f13, (q15_t)0xf0a6,
+  (q15_t)0x7f12, (q15_t)0xf0a0, (q15_t)0x7f11, (q15_t)0xf09a, (q15_t)0x7f11, (q15_t)0xf094, (q15_t)0x7f10, (q15_t)0xf08d,
+  (q15_t)0x7f0f, (q15_t)0xf087, (q15_t)0x7f0e, (q15_t)0xf081, (q15_t)0x7f0e, (q15_t)0xf07b, (q15_t)0x7f0d, (q15_t)0xf075,
+  (q15_t)0x7f0c, (q15_t)0xf06e, (q15_t)0x7f0b, (q15_t)0xf068, (q15_t)0x7f0b, (q15_t)0xf062, (q15_t)0x7f0a, (q15_t)0xf05c,
+  (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7f08, (q15_t)0xf04f, (q15_t)0x7f08, (q15_t)0xf049, (q15_t)0x7f07, (q15_t)0xf043,
+  (q15_t)0x7f06, (q15_t)0xf03c, (q15_t)0x7f05, (q15_t)0xf036, (q15_t)0x7f04, (q15_t)0xf030, (q15_t)0x7f04, (q15_t)0xf02a,
+  (q15_t)0x7f03, (q15_t)0xf023, (q15_t)0x7f02, (q15_t)0xf01d, (q15_t)0x7f01, (q15_t)0xf017, (q15_t)0x7f01, (q15_t)0xf011,
+  (q15_t)0x7f00, (q15_t)0xf00b, (q15_t)0x7eff, (q15_t)0xf004, (q15_t)0x7efe, (q15_t)0xeffe, (q15_t)0x7efd, (q15_t)0xeff8,
+  (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7efc, (q15_t)0xefeb, (q15_t)0x7efb, (q15_t)0xefe5, (q15_t)0x7efa, (q15_t)0xefdf,
+  (q15_t)0x7ef9, (q15_t)0xefd9, (q15_t)0x7ef9, (q15_t)0xefd2, (q15_t)0x7ef8, (q15_t)0xefcc, (q15_t)0x7ef7, (q15_t)0xefc6,
+  (q15_t)0x7ef6, (q15_t)0xefc0, (q15_t)0x7ef5, (q15_t)0xefb9, (q15_t)0x7ef5, (q15_t)0xefb3, (q15_t)0x7ef4, (q15_t)0xefad,
+  (q15_t)0x7ef3, (q15_t)0xefa7, (q15_t)0x7ef2, (q15_t)0xefa1, (q15_t)0x7ef1, (q15_t)0xef9a, (q15_t)0x7ef1, (q15_t)0xef94,
+  (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7eef, (q15_t)0xef88, (q15_t)0x7eee, (q15_t)0xef81, (q15_t)0x7eed, (q15_t)0xef7b,
+  (q15_t)0x7eed, (q15_t)0xef75, (q15_t)0x7eec, (q15_t)0xef6f, (q15_t)0x7eeb, (q15_t)0xef68, (q15_t)0x7eea, (q15_t)0xef62,
+  (q15_t)0x7ee9, (q15_t)0xef5c, (q15_t)0x7ee9, (q15_t)0xef56, (q15_t)0x7ee8, (q15_t)0xef50, (q15_t)0x7ee7, (q15_t)0xef49,
+  (q15_t)0x7ee6, (q15_t)0xef43, (q15_t)0x7ee5, (q15_t)0xef3d, (q15_t)0x7ee4, (q15_t)0xef37, (q15_t)0x7ee4, (q15_t)0xef30,
+  (q15_t)0x7ee3, (q15_t)0xef2a, (q15_t)0x7ee2, (q15_t)0xef24, (q15_t)0x7ee1, (q15_t)0xef1e, (q15_t)0x7ee0, (q15_t)0xef18,
+  (q15_t)0x7edf, (q15_t)0xef11, (q15_t)0x7edf, (q15_t)0xef0b, (q15_t)0x7ede, (q15_t)0xef05, (q15_t)0x7edd, (q15_t)0xeeff,
+  (q15_t)0x7edc, (q15_t)0xeef8, (q15_t)0x7edb, (q15_t)0xeef2, (q15_t)0x7eda, (q15_t)0xeeec, (q15_t)0x7eda, (q15_t)0xeee6,
+  (q15_t)0x7ed9, (q15_t)0xeedf, (q15_t)0x7ed8, (q15_t)0xeed9, (q15_t)0x7ed7, (q15_t)0xeed3, (q15_t)0x7ed6, (q15_t)0xeecd,
+  (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ed5, (q15_t)0xeec0, (q15_t)0x7ed4, (q15_t)0xeeba, (q15_t)0x7ed3, (q15_t)0xeeb4,
+  (q15_t)0x7ed2, (q15_t)0xeeae, (q15_t)0x7ed1, (q15_t)0xeea7, (q15_t)0x7ed0, (q15_t)0xeea1, (q15_t)0x7ecf, (q15_t)0xee9b,
+  (q15_t)0x7ecf, (q15_t)0xee95, (q15_t)0x7ece, (q15_t)0xee8f, (q15_t)0x7ecd, (q15_t)0xee88, (q15_t)0x7ecc, (q15_t)0xee82,
+  (q15_t)0x7ecb, (q15_t)0xee7c, (q15_t)0x7eca, (q15_t)0xee76, (q15_t)0x7ec9, (q15_t)0xee6f, (q15_t)0x7ec9, (q15_t)0xee69,
+  (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7ec7, (q15_t)0xee5d, (q15_t)0x7ec6, (q15_t)0xee57, (q15_t)0x7ec5, (q15_t)0xee50,
+  (q15_t)0x7ec4, (q15_t)0xee4a, (q15_t)0x7ec3, (q15_t)0xee44, (q15_t)0x7ec3, (q15_t)0xee3e, (q15_t)0x7ec2, (q15_t)0xee37,
+  (q15_t)0x7ec1, (q15_t)0xee31, (q15_t)0x7ec0, (q15_t)0xee2b, (q15_t)0x7ebf, (q15_t)0xee25, (q15_t)0x7ebe, (q15_t)0xee1f,
+  (q15_t)0x7ebd, (q15_t)0xee18, (q15_t)0x7ebc, (q15_t)0xee12, (q15_t)0x7ebb, (q15_t)0xee0c, (q15_t)0x7ebb, (q15_t)0xee06,
+  (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eb9, (q15_t)0xedf9, (q15_t)0x7eb8, (q15_t)0xedf3, (q15_t)0x7eb7, (q15_t)0xeded,
+  (q15_t)0x7eb6, (q15_t)0xede7, (q15_t)0x7eb5, (q15_t)0xede0, (q15_t)0x7eb4, (q15_t)0xedda, (q15_t)0x7eb4, (q15_t)0xedd4,
+  (q15_t)0x7eb3, (q15_t)0xedce, (q15_t)0x7eb2, (q15_t)0xedc7, (q15_t)0x7eb1, (q15_t)0xedc1, (q15_t)0x7eb0, (q15_t)0xedbb,
+  (q15_t)0x7eaf, (q15_t)0xedb5, (q15_t)0x7eae, (q15_t)0xedaf, (q15_t)0x7ead, (q15_t)0xeda8, (q15_t)0x7eac, (q15_t)0xeda2,
+  (q15_t)0x7eab, (q15_t)0xed9c, (q15_t)0x7eab, (q15_t)0xed96, (q15_t)0x7eaa, (q15_t)0xed8f, (q15_t)0x7ea9, (q15_t)0xed89,
+  (q15_t)0x7ea8, (q15_t)0xed83, (q15_t)0x7ea7, (q15_t)0xed7d, (q15_t)0x7ea6, (q15_t)0xed77, (q15_t)0x7ea5, (q15_t)0xed70,
+  (q15_t)0x7ea4, (q15_t)0xed6a, (q15_t)0x7ea3, (q15_t)0xed64, (q15_t)0x7ea2, (q15_t)0xed5e, (q15_t)0x7ea1, (q15_t)0xed58,
+  (q15_t)0x7ea1, (q15_t)0xed51, (q15_t)0x7ea0, (q15_t)0xed4b, (q15_t)0x7e9f, (q15_t)0xed45, (q15_t)0x7e9e, (q15_t)0xed3f,
+  (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e9c, (q15_t)0xed32, (q15_t)0x7e9b, (q15_t)0xed2c, (q15_t)0x7e9a, (q15_t)0xed26,
+  (q15_t)0x7e99, (q15_t)0xed20, (q15_t)0x7e98, (q15_t)0xed19, (q15_t)0x7e97, (q15_t)0xed13, (q15_t)0x7e96, (q15_t)0xed0d,
+  (q15_t)0x7e95, (q15_t)0xed07, (q15_t)0x7e94, (q15_t)0xed01, (q15_t)0x7e94, (q15_t)0xecfa, (q15_t)0x7e93, (q15_t)0xecf4,
+  (q15_t)0x7e92, (q15_t)0xecee, (q15_t)0x7e91, (q15_t)0xece8, (q15_t)0x7e90, (q15_t)0xece1, (q15_t)0x7e8f, (q15_t)0xecdb,
+  (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e8d, (q15_t)0xeccf, (q15_t)0x7e8c, (q15_t)0xecc9, (q15_t)0x7e8b, (q15_t)0xecc2,
+  (q15_t)0x7e8a, (q15_t)0xecbc, (q15_t)0x7e89, (q15_t)0xecb6, (q15_t)0x7e88, (q15_t)0xecb0, (q15_t)0x7e87, (q15_t)0xecaa,
+  (q15_t)0x7e86, (q15_t)0xeca3, (q15_t)0x7e85, (q15_t)0xec9d, (q15_t)0x7e84, (q15_t)0xec97, (q15_t)0x7e84, (q15_t)0xec91,
+  (q15_t)0x7e83, (q15_t)0xec8a, (q15_t)0x7e82, (q15_t)0xec84, (q15_t)0x7e81, (q15_t)0xec7e, (q15_t)0x7e80, (q15_t)0xec78,
+  (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e7e, (q15_t)0xec6b, (q15_t)0x7e7d, (q15_t)0xec65, (q15_t)0x7e7c, (q15_t)0xec5f,
+  (q15_t)0x7e7b, (q15_t)0xec59, (q15_t)0x7e7a, (q15_t)0xec53, (q15_t)0x7e79, (q15_t)0xec4c, (q15_t)0x7e78, (q15_t)0xec46,
+  (q15_t)0x7e77, (q15_t)0xec40, (q15_t)0x7e76, (q15_t)0xec3a, (q15_t)0x7e75, (q15_t)0xec34, (q15_t)0x7e74, (q15_t)0xec2d,
+  (q15_t)0x7e73, (q15_t)0xec27, (q15_t)0x7e72, (q15_t)0xec21, (q15_t)0x7e71, (q15_t)0xec1b, (q15_t)0x7e70, (q15_t)0xec15,
+  (q15_t)0x7e6f, (q15_t)0xec0e, (q15_t)0x7e6e, (q15_t)0xec08, (q15_t)0x7e6d, (q15_t)0xec02, (q15_t)0x7e6c, (q15_t)0xebfc,
+  (q15_t)0x7e6b, (q15_t)0xebf5, (q15_t)0x7e6a, (q15_t)0xebef, (q15_t)0x7e69, (q15_t)0xebe9, (q15_t)0x7e68, (q15_t)0xebe3,
+  (q15_t)0x7e67, (q15_t)0xebdd, (q15_t)0x7e66, (q15_t)0xebd6, (q15_t)0x7e65, (q15_t)0xebd0, (q15_t)0x7e64, (q15_t)0xebca,
+  (q15_t)0x7e63, (q15_t)0xebc4, (q15_t)0x7e62, (q15_t)0xebbe, (q15_t)0x7e61, (q15_t)0xebb7, (q15_t)0x7e60, (q15_t)0xebb1,
+  (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e5e, (q15_t)0xeba5, (q15_t)0x7e5d, (q15_t)0xeb9f, (q15_t)0x7e5c, (q15_t)0xeb98,
+  (q15_t)0x7e5b, (q15_t)0xeb92, (q15_t)0x7e5a, (q15_t)0xeb8c, (q15_t)0x7e59, (q15_t)0xeb86, (q15_t)0x7e58, (q15_t)0xeb80,
+  (q15_t)0x7e57, (q15_t)0xeb79, (q15_t)0x7e56, (q15_t)0xeb73, (q15_t)0x7e55, (q15_t)0xeb6d, (q15_t)0x7e54, (q15_t)0xeb67,
+  (q15_t)0x7e53, (q15_t)0xeb61, (q15_t)0x7e52, (q15_t)0xeb5a, (q15_t)0x7e51, (q15_t)0xeb54, (q15_t)0x7e50, (q15_t)0xeb4e,
+  (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e4e, (q15_t)0xeb42, (q15_t)0x7e4d, (q15_t)0xeb3b, (q15_t)0x7e4c, (q15_t)0xeb35,
+  (q15_t)0x7e4b, (q15_t)0xeb2f, (q15_t)0x7e4a, (q15_t)0xeb29, (q15_t)0x7e49, (q15_t)0xeb23, (q15_t)0x7e48, (q15_t)0xeb1c,
+  (q15_t)0x7e47, (q15_t)0xeb16, (q15_t)0x7e46, (q15_t)0xeb10, (q15_t)0x7e45, (q15_t)0xeb0a, (q15_t)0x7e44, (q15_t)0xeb04,
+  (q15_t)0x7e43, (q15_t)0xeafd, (q15_t)0x7e42, (q15_t)0xeaf7, (q15_t)0x7e41, (q15_t)0xeaf1, (q15_t)0x7e40, (q15_t)0xeaeb,
+  (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e3e, (q15_t)0xeade, (q15_t)0x7e3d, (q15_t)0xead8, (q15_t)0x7e3c, (q15_t)0xead2,
+  (q15_t)0x7e3b, (q15_t)0xeacc, (q15_t)0x7e3a, (q15_t)0xeac6, (q15_t)0x7e39, (q15_t)0xeabf, (q15_t)0x7e38, (q15_t)0xeab9,
+  (q15_t)0x7e37, (q15_t)0xeab3, (q15_t)0x7e35, (q15_t)0xeaad, (q15_t)0x7e34, (q15_t)0xeaa7, (q15_t)0x7e33, (q15_t)0xeaa0,
+  (q15_t)0x7e32, (q15_t)0xea9a, (q15_t)0x7e31, (q15_t)0xea94, (q15_t)0x7e30, (q15_t)0xea8e, (q15_t)0x7e2f, (q15_t)0xea88,
+  (q15_t)0x7e2e, (q15_t)0xea81, (q15_t)0x7e2d, (q15_t)0xea7b, (q15_t)0x7e2c, (q15_t)0xea75, (q15_t)0x7e2b, (q15_t)0xea6f,
+  (q15_t)0x7e2a, (q15_t)0xea69, (q15_t)0x7e29, (q15_t)0xea63, (q15_t)0x7e28, (q15_t)0xea5c, (q15_t)0x7e27, (q15_t)0xea56,
+  (q15_t)0x7e26, (q15_t)0xea50, (q15_t)0x7e25, (q15_t)0xea4a, (q15_t)0x7e24, (q15_t)0xea44, (q15_t)0x7e22, (q15_t)0xea3d,
+  (q15_t)0x7e21, (q15_t)0xea37, (q15_t)0x7e20, (q15_t)0xea31, (q15_t)0x7e1f, (q15_t)0xea2b, (q15_t)0x7e1e, (q15_t)0xea25,
+  (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e1c, (q15_t)0xea18, (q15_t)0x7e1b, (q15_t)0xea12, (q15_t)0x7e1a, (q15_t)0xea0c,
+  (q15_t)0x7e19, (q15_t)0xea06, (q15_t)0x7e18, (q15_t)0xe9ff, (q15_t)0x7e17, (q15_t)0xe9f9, (q15_t)0x7e16, (q15_t)0xe9f3,
+  (q15_t)0x7e14, (q15_t)0xe9ed, (q15_t)0x7e13, (q15_t)0xe9e7, (q15_t)0x7e12, (q15_t)0xe9e1, (q15_t)0x7e11, (q15_t)0xe9da,
+  (q15_t)0x7e10, (q15_t)0xe9d4, (q15_t)0x7e0f, (q15_t)0xe9ce, (q15_t)0x7e0e, (q15_t)0xe9c8, (q15_t)0x7e0d, (q15_t)0xe9c2,
+  (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7e0b, (q15_t)0xe9b5, (q15_t)0x7e0a, (q15_t)0xe9af, (q15_t)0x7e08, (q15_t)0xe9a9,
+  (q15_t)0x7e07, (q15_t)0xe9a3, (q15_t)0x7e06, (q15_t)0xe99c, (q15_t)0x7e05, (q15_t)0xe996, (q15_t)0x7e04, (q15_t)0xe990,
+  (q15_t)0x7e03, (q15_t)0xe98a, (q15_t)0x7e02, (q15_t)0xe984, (q15_t)0x7e01, (q15_t)0xe97e, (q15_t)0x7e00, (q15_t)0xe977,
+  (q15_t)0x7dff, (q15_t)0xe971, (q15_t)0x7dfd, (q15_t)0xe96b, (q15_t)0x7dfc, (q15_t)0xe965, (q15_t)0x7dfb, (q15_t)0xe95f,
+  (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7df9, (q15_t)0xe952, (q15_t)0x7df8, (q15_t)0xe94c, (q15_t)0x7df7, (q15_t)0xe946,
+  (q15_t)0x7df6, (q15_t)0xe940, (q15_t)0x7df5, (q15_t)0xe93a, (q15_t)0x7df3, (q15_t)0xe933, (q15_t)0x7df2, (q15_t)0xe92d,
+  (q15_t)0x7df1, (q15_t)0xe927, (q15_t)0x7df0, (q15_t)0xe921, (q15_t)0x7def, (q15_t)0xe91b, (q15_t)0x7dee, (q15_t)0xe914,
+  (q15_t)0x7ded, (q15_t)0xe90e, (q15_t)0x7dec, (q15_t)0xe908, (q15_t)0x7dea, (q15_t)0xe902, (q15_t)0x7de9, (q15_t)0xe8fc,
+  (q15_t)0x7de8, (q15_t)0xe8f6, (q15_t)0x7de7, (q15_t)0xe8ef, (q15_t)0x7de6, (q15_t)0xe8e9, (q15_t)0x7de5, (q15_t)0xe8e3,
+  (q15_t)0x7de4, (q15_t)0xe8dd, (q15_t)0x7de2, (q15_t)0xe8d7, (q15_t)0x7de1, (q15_t)0xe8d0, (q15_t)0x7de0, (q15_t)0xe8ca,
+  (q15_t)0x7ddf, (q15_t)0xe8c4, (q15_t)0x7dde, (q15_t)0xe8be, (q15_t)0x7ddd, (q15_t)0xe8b8, (q15_t)0x7ddc, (q15_t)0xe8b2,
+  (q15_t)0x7dda, (q15_t)0xe8ab, (q15_t)0x7dd9, (q15_t)0xe8a5, (q15_t)0x7dd8, (q15_t)0xe89f, (q15_t)0x7dd7, (q15_t)0xe899,
+  (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dd5, (q15_t)0xe88c, (q15_t)0x7dd4, (q15_t)0xe886, (q15_t)0x7dd2, (q15_t)0xe880,
+  (q15_t)0x7dd1, (q15_t)0xe87a, (q15_t)0x7dd0, (q15_t)0xe874, (q15_t)0x7dcf, (q15_t)0xe86e, (q15_t)0x7dce, (q15_t)0xe867,
+  (q15_t)0x7dcd, (q15_t)0xe861, (q15_t)0x7dcc, (q15_t)0xe85b, (q15_t)0x7dca, (q15_t)0xe855, (q15_t)0x7dc9, (q15_t)0xe84f,
+  (q15_t)0x7dc8, (q15_t)0xe849, (q15_t)0x7dc7, (q15_t)0xe842, (q15_t)0x7dc6, (q15_t)0xe83c, (q15_t)0x7dc5, (q15_t)0xe836,
+  (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7dc2, (q15_t)0xe82a, (q15_t)0x7dc1, (q15_t)0xe823, (q15_t)0x7dc0, (q15_t)0xe81d,
+  (q15_t)0x7dbf, (q15_t)0xe817, (q15_t)0x7dbd, (q15_t)0xe811, (q15_t)0x7dbc, (q15_t)0xe80b, (q15_t)0x7dbb, (q15_t)0xe805,
+  (q15_t)0x7dba, (q15_t)0xe7fe, (q15_t)0x7db9, (q15_t)0xe7f8, (q15_t)0x7db8, (q15_t)0xe7f2, (q15_t)0x7db6, (q15_t)0xe7ec,
+  (q15_t)0x7db5, (q15_t)0xe7e6, (q15_t)0x7db4, (q15_t)0xe7e0, (q15_t)0x7db3, (q15_t)0xe7d9, (q15_t)0x7db2, (q15_t)0xe7d3,
+  (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7daf, (q15_t)0xe7c7, (q15_t)0x7dae, (q15_t)0xe7c1, (q15_t)0x7dad, (q15_t)0xe7bb,
+  (q15_t)0x7dac, (q15_t)0xe7b4, (q15_t)0x7dab, (q15_t)0xe7ae, (q15_t)0x7da9, (q15_t)0xe7a8, (q15_t)0x7da8, (q15_t)0xe7a2,
+  (q15_t)0x7da7, (q15_t)0xe79c, (q15_t)0x7da6, (q15_t)0xe796, (q15_t)0x7da5, (q15_t)0xe78f, (q15_t)0x7da3, (q15_t)0xe789,
+  (q15_t)0x7da2, (q15_t)0xe783, (q15_t)0x7da1, (q15_t)0xe77d, (q15_t)0x7da0, (q15_t)0xe777, (q15_t)0x7d9f, (q15_t)0xe771,
+  (q15_t)0x7d9d, (q15_t)0xe76a, (q15_t)0x7d9c, (q15_t)0xe764, (q15_t)0x7d9b, (q15_t)0xe75e, (q15_t)0x7d9a, (q15_t)0xe758,
+  (q15_t)0x7d98, (q15_t)0xe752, (q15_t)0x7d97, (q15_t)0xe74c, (q15_t)0x7d96, (q15_t)0xe745, (q15_t)0x7d95, (q15_t)0xe73f,
+  (q15_t)0x7d94, (q15_t)0xe739, (q15_t)0x7d92, (q15_t)0xe733, (q15_t)0x7d91, (q15_t)0xe72d, (q15_t)0x7d90, (q15_t)0xe727,
+  (q15_t)0x7d8f, (q15_t)0xe720, (q15_t)0x7d8e, (q15_t)0xe71a, (q15_t)0x7d8c, (q15_t)0xe714, (q15_t)0x7d8b, (q15_t)0xe70e,
+  (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d89, (q15_t)0xe702, (q15_t)0x7d87, (q15_t)0xe6fb, (q15_t)0x7d86, (q15_t)0xe6f5,
+  (q15_t)0x7d85, (q15_t)0xe6ef, (q15_t)0x7d84, (q15_t)0xe6e9, (q15_t)0x7d82, (q15_t)0xe6e3, (q15_t)0x7d81, (q15_t)0xe6dd,
+  (q15_t)0x7d80, (q15_t)0xe6d6, (q15_t)0x7d7f, (q15_t)0xe6d0, (q15_t)0x7d7e, (q15_t)0xe6ca, (q15_t)0x7d7c, (q15_t)0xe6c4,
+  (q15_t)0x7d7b, (q15_t)0xe6be, (q15_t)0x7d7a, (q15_t)0xe6b8, (q15_t)0x7d79, (q15_t)0xe6b2, (q15_t)0x7d77, (q15_t)0xe6ab,
+  (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d75, (q15_t)0xe69f, (q15_t)0x7d74, (q15_t)0xe699, (q15_t)0x7d72, (q15_t)0xe693,
+  (q15_t)0x7d71, (q15_t)0xe68d, (q15_t)0x7d70, (q15_t)0xe686, (q15_t)0x7d6f, (q15_t)0xe680, (q15_t)0x7d6d, (q15_t)0xe67a,
+  (q15_t)0x7d6c, (q15_t)0xe674, (q15_t)0x7d6b, (q15_t)0xe66e, (q15_t)0x7d6a, (q15_t)0xe668, (q15_t)0x7d68, (q15_t)0xe661,
+  (q15_t)0x7d67, (q15_t)0xe65b, (q15_t)0x7d66, (q15_t)0xe655, (q15_t)0x7d65, (q15_t)0xe64f, (q15_t)0x7d63, (q15_t)0xe649,
+  (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d61, (q15_t)0xe63d, (q15_t)0x7d60, (q15_t)0xe636, (q15_t)0x7d5e, (q15_t)0xe630,
+  (q15_t)0x7d5d, (q15_t)0xe62a, (q15_t)0x7d5c, (q15_t)0xe624, (q15_t)0x7d5a, (q15_t)0xe61e, (q15_t)0x7d59, (q15_t)0xe618,
+  (q15_t)0x7d58, (q15_t)0xe611, (q15_t)0x7d57, (q15_t)0xe60b, (q15_t)0x7d55, (q15_t)0xe605, (q15_t)0x7d54, (q15_t)0xe5ff,
+  (q15_t)0x7d53, (q15_t)0xe5f9, (q15_t)0x7d52, (q15_t)0xe5f3, (q15_t)0x7d50, (q15_t)0xe5ed, (q15_t)0x7d4f, (q15_t)0xe5e6,
+  (q15_t)0x7d4e, (q15_t)0xe5e0, (q15_t)0x7d4c, (q15_t)0xe5da, (q15_t)0x7d4b, (q15_t)0xe5d4, (q15_t)0x7d4a, (q15_t)0xe5ce,
+  (q15_t)0x7d49, (q15_t)0xe5c8, (q15_t)0x7d47, (q15_t)0xe5c2, (q15_t)0x7d46, (q15_t)0xe5bb, (q15_t)0x7d45, (q15_t)0xe5b5,
+  (q15_t)0x7d43, (q15_t)0xe5af, (q15_t)0x7d42, (q15_t)0xe5a9, (q15_t)0x7d41, (q15_t)0xe5a3, (q15_t)0x7d3f, (q15_t)0xe59d,
+  (q15_t)0x7d3e, (q15_t)0xe596, (q15_t)0x7d3d, (q15_t)0xe590, (q15_t)0x7d3c, (q15_t)0xe58a, (q15_t)0x7d3a, (q15_t)0xe584,
+  (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d38, (q15_t)0xe578, (q15_t)0x7d36, (q15_t)0xe572, (q15_t)0x7d35, (q15_t)0xe56b,
+  (q15_t)0x7d34, (q15_t)0xe565, (q15_t)0x7d32, (q15_t)0xe55f, (q15_t)0x7d31, (q15_t)0xe559, (q15_t)0x7d30, (q15_t)0xe553,
+  (q15_t)0x7d2f, (q15_t)0xe54d, (q15_t)0x7d2d, (q15_t)0xe547, (q15_t)0x7d2c, (q15_t)0xe540, (q15_t)0x7d2b, (q15_t)0xe53a,
+  (q15_t)0x7d29, (q15_t)0xe534, (q15_t)0x7d28, (q15_t)0xe52e, (q15_t)0x7d27, (q15_t)0xe528, (q15_t)0x7d25, (q15_t)0xe522,
+  (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d23, (q15_t)0xe515, (q15_t)0x7d21, (q15_t)0xe50f, (q15_t)0x7d20, (q15_t)0xe509,
+  (q15_t)0x7d1f, (q15_t)0xe503, (q15_t)0x7d1d, (q15_t)0xe4fd, (q15_t)0x7d1c, (q15_t)0xe4f7, (q15_t)0x7d1b, (q15_t)0xe4f1,
+  (q15_t)0x7d19, (q15_t)0xe4ea, (q15_t)0x7d18, (q15_t)0xe4e4, (q15_t)0x7d17, (q15_t)0xe4de, (q15_t)0x7d15, (q15_t)0xe4d8,
+  (q15_t)0x7d14, (q15_t)0xe4d2, (q15_t)0x7d13, (q15_t)0xe4cc, (q15_t)0x7d11, (q15_t)0xe4c6, (q15_t)0x7d10, (q15_t)0xe4bf,
+  (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7d0d, (q15_t)0xe4b3, (q15_t)0x7d0c, (q15_t)0xe4ad, (q15_t)0x7d0b, (q15_t)0xe4a7,
+  (q15_t)0x7d09, (q15_t)0xe4a1, (q15_t)0x7d08, (q15_t)0xe49b, (q15_t)0x7d07, (q15_t)0xe494, (q15_t)0x7d05, (q15_t)0xe48e,
+  (q15_t)0x7d04, (q15_t)0xe488, (q15_t)0x7d03, (q15_t)0xe482, (q15_t)0x7d01, (q15_t)0xe47c, (q15_t)0x7d00, (q15_t)0xe476,
+  (q15_t)0x7cff, (q15_t)0xe470, (q15_t)0x7cfd, (q15_t)0xe46a, (q15_t)0x7cfc, (q15_t)0xe463, (q15_t)0x7cfb, (q15_t)0xe45d,
+  (q15_t)0x7cf9, (q15_t)0xe457, (q15_t)0x7cf8, (q15_t)0xe451, (q15_t)0x7cf6, (q15_t)0xe44b, (q15_t)0x7cf5, (q15_t)0xe445,
+  (q15_t)0x7cf4, (q15_t)0xe43f, (q15_t)0x7cf2, (q15_t)0xe438, (q15_t)0x7cf1, (q15_t)0xe432, (q15_t)0x7cf0, (q15_t)0xe42c,
+  (q15_t)0x7cee, (q15_t)0xe426, (q15_t)0x7ced, (q15_t)0xe420, (q15_t)0x7cec, (q15_t)0xe41a, (q15_t)0x7cea, (q15_t)0xe414,
+  (q15_t)0x7ce9, (q15_t)0xe40e, (q15_t)0x7ce7, (q15_t)0xe407, (q15_t)0x7ce6, (q15_t)0xe401, (q15_t)0x7ce5, (q15_t)0xe3fb,
+  (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7ce2, (q15_t)0xe3ef, (q15_t)0x7ce1, (q15_t)0xe3e9, (q15_t)0x7cdf, (q15_t)0xe3e3,
+  (q15_t)0x7cde, (q15_t)0xe3dc, (q15_t)0x7cdc, (q15_t)0xe3d6, (q15_t)0x7cdb, (q15_t)0xe3d0, (q15_t)0x7cda, (q15_t)0xe3ca,
+  (q15_t)0x7cd8, (q15_t)0xe3c4, (q15_t)0x7cd7, (q15_t)0xe3be, (q15_t)0x7cd5, (q15_t)0xe3b8, (q15_t)0x7cd4, (q15_t)0xe3b2,
+  (q15_t)0x7cd3, (q15_t)0xe3ab, (q15_t)0x7cd1, (q15_t)0xe3a5, (q15_t)0x7cd0, (q15_t)0xe39f, (q15_t)0x7ccf, (q15_t)0xe399,
+  (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7ccc, (q15_t)0xe38d, (q15_t)0x7cca, (q15_t)0xe387, (q15_t)0x7cc9, (q15_t)0xe381,
+  (q15_t)0x7cc8, (q15_t)0xe37a, (q15_t)0x7cc6, (q15_t)0xe374, (q15_t)0x7cc5, (q15_t)0xe36e, (q15_t)0x7cc3, (q15_t)0xe368,
+  (q15_t)0x7cc2, (q15_t)0xe362, (q15_t)0x7cc1, (q15_t)0xe35c, (q15_t)0x7cbf, (q15_t)0xe356, (q15_t)0x7cbe, (q15_t)0xe350,
+  (q15_t)0x7cbc, (q15_t)0xe349, (q15_t)0x7cbb, (q15_t)0xe343, (q15_t)0x7cb9, (q15_t)0xe33d, (q15_t)0x7cb8, (q15_t)0xe337,
+  (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7cb5, (q15_t)0xe32b, (q15_t)0x7cb4, (q15_t)0xe325, (q15_t)0x7cb2, (q15_t)0xe31f,
+  (q15_t)0x7cb1, (q15_t)0xe318, (q15_t)0x7cb0, (q15_t)0xe312, (q15_t)0x7cae, (q15_t)0xe30c, (q15_t)0x7cad, (q15_t)0xe306,
+  (q15_t)0x7cab, (q15_t)0xe300, (q15_t)0x7caa, (q15_t)0xe2fa, (q15_t)0x7ca8, (q15_t)0xe2f4, (q15_t)0x7ca7, (q15_t)0xe2ee,
+  (q15_t)0x7ca6, (q15_t)0xe2e8, (q15_t)0x7ca4, (q15_t)0xe2e1, (q15_t)0x7ca3, (q15_t)0xe2db, (q15_t)0x7ca1, (q15_t)0xe2d5,
+  (q15_t)0x7ca0, (q15_t)0xe2cf, (q15_t)0x7c9e, (q15_t)0xe2c9, (q15_t)0x7c9d, (q15_t)0xe2c3, (q15_t)0x7c9c, (q15_t)0xe2bd,
+  (q15_t)0x7c9a, (q15_t)0xe2b7, (q15_t)0x7c99, (q15_t)0xe2b0, (q15_t)0x7c97, (q15_t)0xe2aa, (q15_t)0x7c96, (q15_t)0xe2a4,
+  (q15_t)0x7c94, (q15_t)0xe29e, (q15_t)0x7c93, (q15_t)0xe298, (q15_t)0x7c91, (q15_t)0xe292, (q15_t)0x7c90, (q15_t)0xe28c,
+  (q15_t)0x7c8f, (q15_t)0xe286, (q15_t)0x7c8d, (q15_t)0xe280, (q15_t)0x7c8c, (q15_t)0xe279, (q15_t)0x7c8a, (q15_t)0xe273,
+  (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c87, (q15_t)0xe267, (q15_t)0x7c86, (q15_t)0xe261, (q15_t)0x7c84, (q15_t)0xe25b,
+  (q15_t)0x7c83, (q15_t)0xe255, (q15_t)0x7c82, (q15_t)0xe24f, (q15_t)0x7c80, (q15_t)0xe249, (q15_t)0x7c7f, (q15_t)0xe242,
+  (q15_t)0x7c7d, (q15_t)0xe23c, (q15_t)0x7c7c, (q15_t)0xe236, (q15_t)0x7c7a, (q15_t)0xe230, (q15_t)0x7c79, (q15_t)0xe22a,
+  (q15_t)0x7c77, (q15_t)0xe224, (q15_t)0x7c76, (q15_t)0xe21e, (q15_t)0x7c74, (q15_t)0xe218, (q15_t)0x7c73, (q15_t)0xe212,
+  (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c70, (q15_t)0xe205, (q15_t)0x7c6e, (q15_t)0xe1ff, (q15_t)0x7c6d, (q15_t)0xe1f9,
+  (q15_t)0x7c6c, (q15_t)0xe1f3, (q15_t)0x7c6a, (q15_t)0xe1ed, (q15_t)0x7c69, (q15_t)0xe1e7, (q15_t)0x7c67, (q15_t)0xe1e1,
+  (q15_t)0x7c66, (q15_t)0xe1db, (q15_t)0x7c64, (q15_t)0xe1d4, (q15_t)0x7c63, (q15_t)0xe1ce, (q15_t)0x7c61, (q15_t)0xe1c8,
+  (q15_t)0x7c60, (q15_t)0xe1c2, (q15_t)0x7c5e, (q15_t)0xe1bc, (q15_t)0x7c5d, (q15_t)0xe1b6, (q15_t)0x7c5b, (q15_t)0xe1b0,
+  (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c58, (q15_t)0xe1a4, (q15_t)0x7c57, (q15_t)0xe19e, (q15_t)0x7c55, (q15_t)0xe197,
+  (q15_t)0x7c54, (q15_t)0xe191, (q15_t)0x7c52, (q15_t)0xe18b, (q15_t)0x7c51, (q15_t)0xe185, (q15_t)0x7c4f, (q15_t)0xe17f,
+  (q15_t)0x7c4e, (q15_t)0xe179, (q15_t)0x7c4c, (q15_t)0xe173, (q15_t)0x7c4b, (q15_t)0xe16d, (q15_t)0x7c49, (q15_t)0xe167,
+  (q15_t)0x7c48, (q15_t)0xe160, (q15_t)0x7c46, (q15_t)0xe15a, (q15_t)0x7c45, (q15_t)0xe154, (q15_t)0x7c43, (q15_t)0xe14e,
+  (q15_t)0x7c42, (q15_t)0xe148, (q15_t)0x7c40, (q15_t)0xe142, (q15_t)0x7c3f, (q15_t)0xe13c, (q15_t)0x7c3d, (q15_t)0xe136,
+  (q15_t)0x7c3c, (q15_t)0xe130, (q15_t)0x7c3a, (q15_t)0xe12a, (q15_t)0x7c39, (q15_t)0xe123, (q15_t)0x7c37, (q15_t)0xe11d,
+  (q15_t)0x7c36, (q15_t)0xe117, (q15_t)0x7c34, (q15_t)0xe111, (q15_t)0x7c33, (q15_t)0xe10b, (q15_t)0x7c31, (q15_t)0xe105,
+  (q15_t)0x7c30, (q15_t)0xe0ff, (q15_t)0x7c2e, (q15_t)0xe0f9, (q15_t)0x7c2d, (q15_t)0xe0f3, (q15_t)0x7c2b, (q15_t)0xe0ed,
+  (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c28, (q15_t)0xe0e0, (q15_t)0x7c26, (q15_t)0xe0da, (q15_t)0x7c25, (q15_t)0xe0d4,
+  (q15_t)0x7c23, (q15_t)0xe0ce, (q15_t)0x7c22, (q15_t)0xe0c8, (q15_t)0x7c20, (q15_t)0xe0c2, (q15_t)0x7c1f, (q15_t)0xe0bc,
+  (q15_t)0x7c1d, (q15_t)0xe0b6, (q15_t)0x7c1c, (q15_t)0xe0b0, (q15_t)0x7c1a, (q15_t)0xe0aa, (q15_t)0x7c19, (q15_t)0xe0a3,
+  (q15_t)0x7c17, (q15_t)0xe09d, (q15_t)0x7c16, (q15_t)0xe097, (q15_t)0x7c14, (q15_t)0xe091, (q15_t)0x7c12, (q15_t)0xe08b,
+  (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7c0f, (q15_t)0xe07f, (q15_t)0x7c0e, (q15_t)0xe079, (q15_t)0x7c0c, (q15_t)0xe073,
+  (q15_t)0x7c0b, (q15_t)0xe06d, (q15_t)0x7c09, (q15_t)0xe067, (q15_t)0x7c08, (q15_t)0xe061, (q15_t)0x7c06, (q15_t)0xe05a,
+  (q15_t)0x7c05, (q15_t)0xe054, (q15_t)0x7c03, (q15_t)0xe04e, (q15_t)0x7c01, (q15_t)0xe048, (q15_t)0x7c00, (q15_t)0xe042,
+  (q15_t)0x7bfe, (q15_t)0xe03c, (q15_t)0x7bfd, (q15_t)0xe036, (q15_t)0x7bfb, (q15_t)0xe030, (q15_t)0x7bfa, (q15_t)0xe02a,
+  (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bf6, (q15_t)0xe01e, (q15_t)0x7bf5, (q15_t)0xe017, (q15_t)0x7bf3, (q15_t)0xe011,
+  (q15_t)0x7bf2, (q15_t)0xe00b, (q15_t)0x7bf0, (q15_t)0xe005, (q15_t)0x7bef, (q15_t)0xdfff, (q15_t)0x7bed, (q15_t)0xdff9,
+  (q15_t)0x7beb, (q15_t)0xdff3, (q15_t)0x7bea, (q15_t)0xdfed, (q15_t)0x7be8, (q15_t)0xdfe7, (q15_t)0x7be7, (q15_t)0xdfe1,
+  (q15_t)0x7be5, (q15_t)0xdfdb, (q15_t)0x7be4, (q15_t)0xdfd5, (q15_t)0x7be2, (q15_t)0xdfce, (q15_t)0x7be0, (q15_t)0xdfc8,
+  (q15_t)0x7bdf, (q15_t)0xdfc2, (q15_t)0x7bdd, (q15_t)0xdfbc, (q15_t)0x7bdc, (q15_t)0xdfb6, (q15_t)0x7bda, (q15_t)0xdfb0,
+  (q15_t)0x7bd9, (q15_t)0xdfaa, (q15_t)0x7bd7, (q15_t)0xdfa4, (q15_t)0x7bd5, (q15_t)0xdf9e, (q15_t)0x7bd4, (q15_t)0xdf98,
+  (q15_t)0x7bd2, (q15_t)0xdf92, (q15_t)0x7bd1, (q15_t)0xdf8c, (q15_t)0x7bcf, (q15_t)0xdf86, (q15_t)0x7bcd, (q15_t)0xdf7f,
+  (q15_t)0x7bcc, (q15_t)0xdf79, (q15_t)0x7bca, (q15_t)0xdf73, (q15_t)0x7bc9, (q15_t)0xdf6d, (q15_t)0x7bc7, (q15_t)0xdf67,
+  (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bc4, (q15_t)0xdf5b, (q15_t)0x7bc2, (q15_t)0xdf55, (q15_t)0x7bc1, (q15_t)0xdf4f,
+  (q15_t)0x7bbf, (q15_t)0xdf49, (q15_t)0x7bbd, (q15_t)0xdf43, (q15_t)0x7bbc, (q15_t)0xdf3d, (q15_t)0x7bba, (q15_t)0xdf37,
+  (q15_t)0x7bb9, (q15_t)0xdf30, (q15_t)0x7bb7, (q15_t)0xdf2a, (q15_t)0x7bb5, (q15_t)0xdf24, (q15_t)0x7bb4, (q15_t)0xdf1e,
+  (q15_t)0x7bb2, (q15_t)0xdf18, (q15_t)0x7bb0, (q15_t)0xdf12, (q15_t)0x7baf, (q15_t)0xdf0c, (q15_t)0x7bad, (q15_t)0xdf06,
+  (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7baa, (q15_t)0xdefa, (q15_t)0x7ba8, (q15_t)0xdef4, (q15_t)0x7ba7, (q15_t)0xdeee,
+  (q15_t)0x7ba5, (q15_t)0xdee8, (q15_t)0x7ba3, (q15_t)0xdee2, (q15_t)0x7ba2, (q15_t)0xdedb, (q15_t)0x7ba0, (q15_t)0xded5,
+  (q15_t)0x7b9f, (q15_t)0xdecf, (q15_t)0x7b9d, (q15_t)0xdec9, (q15_t)0x7b9b, (q15_t)0xdec3, (q15_t)0x7b9a, (q15_t)0xdebd,
+  (q15_t)0x7b98, (q15_t)0xdeb7, (q15_t)0x7b96, (q15_t)0xdeb1, (q15_t)0x7b95, (q15_t)0xdeab, (q15_t)0x7b93, (q15_t)0xdea5,
+  (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b90, (q15_t)0xde99, (q15_t)0x7b8e, (q15_t)0xde93, (q15_t)0x7b8d, (q15_t)0xde8d,
+  (q15_t)0x7b8b, (q15_t)0xde87, (q15_t)0x7b89, (q15_t)0xde80, (q15_t)0x7b88, (q15_t)0xde7a, (q15_t)0x7b86, (q15_t)0xde74,
+  (q15_t)0x7b84, (q15_t)0xde6e, (q15_t)0x7b83, (q15_t)0xde68, (q15_t)0x7b81, (q15_t)0xde62, (q15_t)0x7b7f, (q15_t)0xde5c,
+  (q15_t)0x7b7e, (q15_t)0xde56, (q15_t)0x7b7c, (q15_t)0xde50, (q15_t)0x7b7a, (q15_t)0xde4a, (q15_t)0x7b79, (q15_t)0xde44,
+  (q15_t)0x7b77, (q15_t)0xde3e, (q15_t)0x7b76, (q15_t)0xde38, (q15_t)0x7b74, (q15_t)0xde32, (q15_t)0x7b72, (q15_t)0xde2c,
+  (q15_t)0x7b71, (q15_t)0xde26, (q15_t)0x7b6f, (q15_t)0xde1f, (q15_t)0x7b6d, (q15_t)0xde19, (q15_t)0x7b6c, (q15_t)0xde13,
+  (q15_t)0x7b6a, (q15_t)0xde0d, (q15_t)0x7b68, (q15_t)0xde07, (q15_t)0x7b67, (q15_t)0xde01, (q15_t)0x7b65, (q15_t)0xddfb,
+  (q15_t)0x7b63, (q15_t)0xddf5, (q15_t)0x7b62, (q15_t)0xddef, (q15_t)0x7b60, (q15_t)0xdde9, (q15_t)0x7b5e, (q15_t)0xdde3,
+  (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b5b, (q15_t)0xddd7, (q15_t)0x7b59, (q15_t)0xddd1, (q15_t)0x7b57, (q15_t)0xddcb,
+  (q15_t)0x7b56, (q15_t)0xddc5, (q15_t)0x7b54, (q15_t)0xddbf, (q15_t)0x7b52, (q15_t)0xddb9, (q15_t)0x7b51, (q15_t)0xddb2,
+  (q15_t)0x7b4f, (q15_t)0xddac, (q15_t)0x7b4d, (q15_t)0xdda6, (q15_t)0x7b4c, (q15_t)0xdda0, (q15_t)0x7b4a, (q15_t)0xdd9a,
+  (q15_t)0x7b48, (q15_t)0xdd94, (q15_t)0x7b47, (q15_t)0xdd8e, (q15_t)0x7b45, (q15_t)0xdd88, (q15_t)0x7b43, (q15_t)0xdd82,
+  (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b40, (q15_t)0xdd76, (q15_t)0x7b3e, (q15_t)0xdd70, (q15_t)0x7b3c, (q15_t)0xdd6a,
+  (q15_t)0x7b3b, (q15_t)0xdd64, (q15_t)0x7b39, (q15_t)0xdd5e, (q15_t)0x7b37, (q15_t)0xdd58, (q15_t)0x7b36, (q15_t)0xdd52,
+  (q15_t)0x7b34, (q15_t)0xdd4c, (q15_t)0x7b32, (q15_t)0xdd46, (q15_t)0x7b31, (q15_t)0xdd40, (q15_t)0x7b2f, (q15_t)0xdd39,
+  (q15_t)0x7b2d, (q15_t)0xdd33, (q15_t)0x7b2b, (q15_t)0xdd2d, (q15_t)0x7b2a, (q15_t)0xdd27, (q15_t)0x7b28, (q15_t)0xdd21,
+  (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b25, (q15_t)0xdd15, (q15_t)0x7b23, (q15_t)0xdd0f, (q15_t)0x7b21, (q15_t)0xdd09,
+  (q15_t)0x7b1f, (q15_t)0xdd03, (q15_t)0x7b1e, (q15_t)0xdcfd, (q15_t)0x7b1c, (q15_t)0xdcf7, (q15_t)0x7b1a, (q15_t)0xdcf1,
+  (q15_t)0x7b19, (q15_t)0xdceb, (q15_t)0x7b17, (q15_t)0xdce5, (q15_t)0x7b15, (q15_t)0xdcdf, (q15_t)0x7b13, (q15_t)0xdcd9,
+  (q15_t)0x7b12, (q15_t)0xdcd3, (q15_t)0x7b10, (q15_t)0xdccd, (q15_t)0x7b0e, (q15_t)0xdcc7, (q15_t)0x7b0c, (q15_t)0xdcc1,
+  (q15_t)0x7b0b, (q15_t)0xdcbb, (q15_t)0x7b09, (q15_t)0xdcb5, (q15_t)0x7b07, (q15_t)0xdcae, (q15_t)0x7b06, (q15_t)0xdca8,
+  (q15_t)0x7b04, (q15_t)0xdca2, (q15_t)0x7b02, (q15_t)0xdc9c, (q15_t)0x7b00, (q15_t)0xdc96, (q15_t)0x7aff, (q15_t)0xdc90,
+  (q15_t)0x7afd, (q15_t)0xdc8a, (q15_t)0x7afb, (q15_t)0xdc84, (q15_t)0x7af9, (q15_t)0xdc7e, (q15_t)0x7af8, (q15_t)0xdc78,
+  (q15_t)0x7af6, (q15_t)0xdc72, (q15_t)0x7af4, (q15_t)0xdc6c, (q15_t)0x7af2, (q15_t)0xdc66, (q15_t)0x7af1, (q15_t)0xdc60,
+  (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7aed, (q15_t)0xdc54, (q15_t)0x7aeb, (q15_t)0xdc4e, (q15_t)0x7aea, (q15_t)0xdc48,
+  (q15_t)0x7ae8, (q15_t)0xdc42, (q15_t)0x7ae6, (q15_t)0xdc3c, (q15_t)0x7ae4, (q15_t)0xdc36, (q15_t)0x7ae3, (q15_t)0xdc30,
+  (q15_t)0x7ae1, (q15_t)0xdc2a, (q15_t)0x7adf, (q15_t)0xdc24, (q15_t)0x7add, (q15_t)0xdc1e, (q15_t)0x7adc, (q15_t)0xdc18,
+  (q15_t)0x7ada, (q15_t)0xdc12, (q15_t)0x7ad8, (q15_t)0xdc0c, (q15_t)0x7ad6, (q15_t)0xdc06, (q15_t)0x7ad5, (q15_t)0xdbff,
+  (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7ad1, (q15_t)0xdbf3, (q15_t)0x7acf, (q15_t)0xdbed, (q15_t)0x7acd, (q15_t)0xdbe7,
+  (q15_t)0x7acc, (q15_t)0xdbe1, (q15_t)0x7aca, (q15_t)0xdbdb, (q15_t)0x7ac8, (q15_t)0xdbd5, (q15_t)0x7ac6, (q15_t)0xdbcf,
+  (q15_t)0x7ac5, (q15_t)0xdbc9, (q15_t)0x7ac3, (q15_t)0xdbc3, (q15_t)0x7ac1, (q15_t)0xdbbd, (q15_t)0x7abf, (q15_t)0xdbb7,
+  (q15_t)0x7abd, (q15_t)0xdbb1, (q15_t)0x7abc, (q15_t)0xdbab, (q15_t)0x7aba, (q15_t)0xdba5, (q15_t)0x7ab8, (q15_t)0xdb9f,
+  (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7ab5, (q15_t)0xdb93, (q15_t)0x7ab3, (q15_t)0xdb8d, (q15_t)0x7ab1, (q15_t)0xdb87,
+  (q15_t)0x7aaf, (q15_t)0xdb81, (q15_t)0x7aad, (q15_t)0xdb7b, (q15_t)0x7aac, (q15_t)0xdb75, (q15_t)0x7aaa, (q15_t)0xdb6f,
+  (q15_t)0x7aa8, (q15_t)0xdb69, (q15_t)0x7aa6, (q15_t)0xdb63, (q15_t)0x7aa4, (q15_t)0xdb5d, (q15_t)0x7aa3, (q15_t)0xdb57,
+  (q15_t)0x7aa1, (q15_t)0xdb51, (q15_t)0x7a9f, (q15_t)0xdb4b, (q15_t)0x7a9d, (q15_t)0xdb45, (q15_t)0x7a9b, (q15_t)0xdb3f,
+  (q15_t)0x7a9a, (q15_t)0xdb39, (q15_t)0x7a98, (q15_t)0xdb33, (q15_t)0x7a96, (q15_t)0xdb2d, (q15_t)0x7a94, (q15_t)0xdb27,
+  (q15_t)0x7a92, (q15_t)0xdb21, (q15_t)0x7a91, (q15_t)0xdb1b, (q15_t)0x7a8f, (q15_t)0xdb15, (q15_t)0x7a8d, (q15_t)0xdb0f,
+  (q15_t)0x7a8b, (q15_t)0xdb09, (q15_t)0x7a89, (q15_t)0xdb03, (q15_t)0x7a87, (q15_t)0xdafd, (q15_t)0x7a86, (q15_t)0xdaf7,
+  (q15_t)0x7a84, (q15_t)0xdaf1, (q15_t)0x7a82, (q15_t)0xdaea, (q15_t)0x7a80, (q15_t)0xdae4, (q15_t)0x7a7e, (q15_t)0xdade,
+  (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a7b, (q15_t)0xdad2, (q15_t)0x7a79, (q15_t)0xdacc, (q15_t)0x7a77, (q15_t)0xdac6,
+  (q15_t)0x7a75, (q15_t)0xdac0, (q15_t)0x7a73, (q15_t)0xdaba, (q15_t)0x7a72, (q15_t)0xdab4, (q15_t)0x7a70, (q15_t)0xdaae,
+  (q15_t)0x7a6e, (q15_t)0xdaa8, (q15_t)0x7a6c, (q15_t)0xdaa2, (q15_t)0x7a6a, (q15_t)0xda9c, (q15_t)0x7a68, (q15_t)0xda96,
+  (q15_t)0x7a67, (q15_t)0xda90, (q15_t)0x7a65, (q15_t)0xda8a, (q15_t)0x7a63, (q15_t)0xda84, (q15_t)0x7a61, (q15_t)0xda7e,
+  (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a5d, (q15_t)0xda72, (q15_t)0x7a5c, (q15_t)0xda6c, (q15_t)0x7a5a, (q15_t)0xda66,
+  (q15_t)0x7a58, (q15_t)0xda60, (q15_t)0x7a56, (q15_t)0xda5a, (q15_t)0x7a54, (q15_t)0xda54, (q15_t)0x7a52, (q15_t)0xda4e,
+  (q15_t)0x7a50, (q15_t)0xda48, (q15_t)0x7a4f, (q15_t)0xda42, (q15_t)0x7a4d, (q15_t)0xda3c, (q15_t)0x7a4b, (q15_t)0xda36,
+  (q15_t)0x7a49, (q15_t)0xda30, (q15_t)0x7a47, (q15_t)0xda2a, (q15_t)0x7a45, (q15_t)0xda24, (q15_t)0x7a43, (q15_t)0xda1e,
+  (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a40, (q15_t)0xda12, (q15_t)0x7a3e, (q15_t)0xda0c, (q15_t)0x7a3c, (q15_t)0xda06,
+  (q15_t)0x7a3a, (q15_t)0xda00, (q15_t)0x7a38, (q15_t)0xd9fa, (q15_t)0x7a36, (q15_t)0xd9f4, (q15_t)0x7a35, (q15_t)0xd9ee,
+  (q15_t)0x7a33, (q15_t)0xd9e8, (q15_t)0x7a31, (q15_t)0xd9e2, (q15_t)0x7a2f, (q15_t)0xd9dc, (q15_t)0x7a2d, (q15_t)0xd9d6,
+  (q15_t)0x7a2b, (q15_t)0xd9d0, (q15_t)0x7a29, (q15_t)0xd9ca, (q15_t)0x7a27, (q15_t)0xd9c4, (q15_t)0x7a26, (q15_t)0xd9be,
+  (q15_t)0x7a24, (q15_t)0xd9b8, (q15_t)0x7a22, (q15_t)0xd9b2, (q15_t)0x7a20, (q15_t)0xd9ac, (q15_t)0x7a1e, (q15_t)0xd9a6,
+  (q15_t)0x7a1c, (q15_t)0xd9a0, (q15_t)0x7a1a, (q15_t)0xd99a, (q15_t)0x7a18, (q15_t)0xd994, (q15_t)0x7a16, (q15_t)0xd98e,
+  (q15_t)0x7a15, (q15_t)0xd988, (q15_t)0x7a13, (q15_t)0xd982, (q15_t)0x7a11, (q15_t)0xd97c, (q15_t)0x7a0f, (q15_t)0xd976,
+  (q15_t)0x7a0d, (q15_t)0xd970, (q15_t)0x7a0b, (q15_t)0xd96a, (q15_t)0x7a09, (q15_t)0xd964, (q15_t)0x7a07, (q15_t)0xd95e,
+  (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x7a04, (q15_t)0xd952, (q15_t)0x7a02, (q15_t)0xd94c, (q15_t)0x7a00, (q15_t)0xd946,
+  (q15_t)0x79fe, (q15_t)0xd940, (q15_t)0x79fc, (q15_t)0xd93a, (q15_t)0x79fa, (q15_t)0xd934, (q15_t)0x79f8, (q15_t)0xd92e,
+  (q15_t)0x79f6, (q15_t)0xd928, (q15_t)0x79f4, (q15_t)0xd922, (q15_t)0x79f2, (q15_t)0xd91c, (q15_t)0x79f0, (q15_t)0xd917,
+  (q15_t)0x79ef, (q15_t)0xd911, (q15_t)0x79ed, (q15_t)0xd90b, (q15_t)0x79eb, (q15_t)0xd905, (q15_t)0x79e9, (q15_t)0xd8ff,
+  (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79e5, (q15_t)0xd8f3, (q15_t)0x79e3, (q15_t)0xd8ed, (q15_t)0x79e1, (q15_t)0xd8e7,
+  (q15_t)0x79df, (q15_t)0xd8e1, (q15_t)0x79dd, (q15_t)0xd8db, (q15_t)0x79db, (q15_t)0xd8d5, (q15_t)0x79d9, (q15_t)0xd8cf,
+  (q15_t)0x79d8, (q15_t)0xd8c9, (q15_t)0x79d6, (q15_t)0xd8c3, (q15_t)0x79d4, (q15_t)0xd8bd, (q15_t)0x79d2, (q15_t)0xd8b7,
+  (q15_t)0x79d0, (q15_t)0xd8b1, (q15_t)0x79ce, (q15_t)0xd8ab, (q15_t)0x79cc, (q15_t)0xd8a5, (q15_t)0x79ca, (q15_t)0xd89f,
+  (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79c6, (q15_t)0xd893, (q15_t)0x79c4, (q15_t)0xd88d, (q15_t)0x79c2, (q15_t)0xd887,
+  (q15_t)0x79c0, (q15_t)0xd881, (q15_t)0x79be, (q15_t)0xd87b, (q15_t)0x79bc, (q15_t)0xd875, (q15_t)0x79bb, (q15_t)0xd86f,
+  (q15_t)0x79b9, (q15_t)0xd869, (q15_t)0x79b7, (q15_t)0xd863, (q15_t)0x79b5, (q15_t)0xd85d, (q15_t)0x79b3, (q15_t)0xd857,
+  (q15_t)0x79b1, (q15_t)0xd851, (q15_t)0x79af, (q15_t)0xd84b, (q15_t)0x79ad, (q15_t)0xd845, (q15_t)0x79ab, (q15_t)0xd83f,
+  (q15_t)0x79a9, (q15_t)0xd839, (q15_t)0x79a7, (q15_t)0xd833, (q15_t)0x79a5, (q15_t)0xd82d, (q15_t)0x79a3, (q15_t)0xd827,
+  (q15_t)0x79a1, (q15_t)0xd821, (q15_t)0x799f, (q15_t)0xd81b, (q15_t)0x799d, (q15_t)0xd815, (q15_t)0x799b, (q15_t)0xd80f,
+  (q15_t)0x7999, (q15_t)0xd80a, (q15_t)0x7997, (q15_t)0xd804, (q15_t)0x7995, (q15_t)0xd7fe, (q15_t)0x7993, (q15_t)0xd7f8,
+  (q15_t)0x7992, (q15_t)0xd7f2, (q15_t)0x7990, (q15_t)0xd7ec, (q15_t)0x798e, (q15_t)0xd7e6, (q15_t)0x798c, (q15_t)0xd7e0,
+  (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7988, (q15_t)0xd7d4, (q15_t)0x7986, (q15_t)0xd7ce, (q15_t)0x7984, (q15_t)0xd7c8,
+  (q15_t)0x7982, (q15_t)0xd7c2, (q15_t)0x7980, (q15_t)0xd7bc, (q15_t)0x797e, (q15_t)0xd7b6, (q15_t)0x797c, (q15_t)0xd7b0,
+  (q15_t)0x797a, (q15_t)0xd7aa, (q15_t)0x7978, (q15_t)0xd7a4, (q15_t)0x7976, (q15_t)0xd79e, (q15_t)0x7974, (q15_t)0xd798,
+  (q15_t)0x7972, (q15_t)0xd792, (q15_t)0x7970, (q15_t)0xd78c, (q15_t)0x796e, (q15_t)0xd786, (q15_t)0x796c, (q15_t)0xd780,
+  (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x7968, (q15_t)0xd774, (q15_t)0x7966, (q15_t)0xd76e, (q15_t)0x7964, (q15_t)0xd768,
+  (q15_t)0x7962, (q15_t)0xd763, (q15_t)0x7960, (q15_t)0xd75d, (q15_t)0x795e, (q15_t)0xd757, (q15_t)0x795c, (q15_t)0xd751,
+  (q15_t)0x795a, (q15_t)0xd74b, (q15_t)0x7958, (q15_t)0xd745, (q15_t)0x7956, (q15_t)0xd73f, (q15_t)0x7954, (q15_t)0xd739,
+  (q15_t)0x7952, (q15_t)0xd733, (q15_t)0x7950, (q15_t)0xd72d, (q15_t)0x794e, (q15_t)0xd727, (q15_t)0x794c, (q15_t)0xd721,
+  (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x7948, (q15_t)0xd715, (q15_t)0x7946, (q15_t)0xd70f, (q15_t)0x7944, (q15_t)0xd709,
+  (q15_t)0x7942, (q15_t)0xd703, (q15_t)0x7940, (q15_t)0xd6fd, (q15_t)0x793e, (q15_t)0xd6f7, (q15_t)0x793c, (q15_t)0xd6f1,
+  (q15_t)0x793a, (q15_t)0xd6eb, (q15_t)0x7938, (q15_t)0xd6e5, (q15_t)0x7936, (q15_t)0xd6e0, (q15_t)0x7934, (q15_t)0xd6da,
+  (q15_t)0x7932, (q15_t)0xd6d4, (q15_t)0x7930, (q15_t)0xd6ce, (q15_t)0x792e, (q15_t)0xd6c8, (q15_t)0x792c, (q15_t)0xd6c2,
+  (q15_t)0x792a, (q15_t)0xd6bc, (q15_t)0x7928, (q15_t)0xd6b6, (q15_t)0x7926, (q15_t)0xd6b0, (q15_t)0x7924, (q15_t)0xd6aa,
+  (q15_t)0x7922, (q15_t)0xd6a4, (q15_t)0x7920, (q15_t)0xd69e, (q15_t)0x791e, (q15_t)0xd698, (q15_t)0x791c, (q15_t)0xd692,
+  (q15_t)0x7919, (q15_t)0xd68c, (q15_t)0x7917, (q15_t)0xd686, (q15_t)0x7915, (q15_t)0xd680, (q15_t)0x7913, (q15_t)0xd67a,
+  (q15_t)0x7911, (q15_t)0xd675, (q15_t)0x790f, (q15_t)0xd66f, (q15_t)0x790d, (q15_t)0xd669, (q15_t)0x790b, (q15_t)0xd663,
+  (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x7907, (q15_t)0xd657, (q15_t)0x7905, (q15_t)0xd651, (q15_t)0x7903, (q15_t)0xd64b,
+  (q15_t)0x7901, (q15_t)0xd645, (q15_t)0x78ff, (q15_t)0xd63f, (q15_t)0x78fd, (q15_t)0xd639, (q15_t)0x78fb, (q15_t)0xd633,
+  (q15_t)0x78f9, (q15_t)0xd62d, (q15_t)0x78f7, (q15_t)0xd627, (q15_t)0x78f5, (q15_t)0xd621, (q15_t)0x78f3, (q15_t)0xd61b,
+  (q15_t)0x78f1, (q15_t)0xd615, (q15_t)0x78ee, (q15_t)0xd610, (q15_t)0x78ec, (q15_t)0xd60a, (q15_t)0x78ea, (q15_t)0xd604,
+  (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78e6, (q15_t)0xd5f8, (q15_t)0x78e4, (q15_t)0xd5f2, (q15_t)0x78e2, (q15_t)0xd5ec,
+  (q15_t)0x78e0, (q15_t)0xd5e6, (q15_t)0x78de, (q15_t)0xd5e0, (q15_t)0x78dc, (q15_t)0xd5da, (q15_t)0x78da, (q15_t)0xd5d4,
+  (q15_t)0x78d8, (q15_t)0xd5ce, (q15_t)0x78d6, (q15_t)0xd5c8, (q15_t)0x78d4, (q15_t)0xd5c2, (q15_t)0x78d2, (q15_t)0xd5bc,
+  (q15_t)0x78cf, (q15_t)0xd5b7, (q15_t)0x78cd, (q15_t)0xd5b1, (q15_t)0x78cb, (q15_t)0xd5ab, (q15_t)0x78c9, (q15_t)0xd5a5,
+  (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78c5, (q15_t)0xd599, (q15_t)0x78c3, (q15_t)0xd593, (q15_t)0x78c1, (q15_t)0xd58d,
+  (q15_t)0x78bf, (q15_t)0xd587, (q15_t)0x78bd, (q15_t)0xd581, (q15_t)0x78bb, (q15_t)0xd57b, (q15_t)0x78b9, (q15_t)0xd575,
+  (q15_t)0x78b6, (q15_t)0xd56f, (q15_t)0x78b4, (q15_t)0xd569, (q15_t)0x78b2, (q15_t)0xd564, (q15_t)0x78b0, (q15_t)0xd55e,
+  (q15_t)0x78ae, (q15_t)0xd558, (q15_t)0x78ac, (q15_t)0xd552, (q15_t)0x78aa, (q15_t)0xd54c, (q15_t)0x78a8, (q15_t)0xd546,
+  (q15_t)0x78a6, (q15_t)0xd540, (q15_t)0x78a4, (q15_t)0xd53a, (q15_t)0x78a2, (q15_t)0xd534, (q15_t)0x789f, (q15_t)0xd52e,
+  (q15_t)0x789d, (q15_t)0xd528, (q15_t)0x789b, (q15_t)0xd522, (q15_t)0x7899, (q15_t)0xd51c, (q15_t)0x7897, (q15_t)0xd517,
+  (q15_t)0x7895, (q15_t)0xd511, (q15_t)0x7893, (q15_t)0xd50b, (q15_t)0x7891, (q15_t)0xd505, (q15_t)0x788f, (q15_t)0xd4ff,
+  (q15_t)0x788c, (q15_t)0xd4f9, (q15_t)0x788a, (q15_t)0xd4f3, (q15_t)0x7888, (q15_t)0xd4ed, (q15_t)0x7886, (q15_t)0xd4e7,
+  (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x7882, (q15_t)0xd4db, (q15_t)0x7880, (q15_t)0xd4d5, (q15_t)0x787e, (q15_t)0xd4d0,
+  (q15_t)0x787c, (q15_t)0xd4ca, (q15_t)0x7879, (q15_t)0xd4c4, (q15_t)0x7877, (q15_t)0xd4be, (q15_t)0x7875, (q15_t)0xd4b8,
+  (q15_t)0x7873, (q15_t)0xd4b2, (q15_t)0x7871, (q15_t)0xd4ac, (q15_t)0x786f, (q15_t)0xd4a6, (q15_t)0x786d, (q15_t)0xd4a0,
+  (q15_t)0x786b, (q15_t)0xd49a, (q15_t)0x7868, (q15_t)0xd494, (q15_t)0x7866, (q15_t)0xd48f, (q15_t)0x7864, (q15_t)0xd489,
+  (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7860, (q15_t)0xd47d, (q15_t)0x785e, (q15_t)0xd477, (q15_t)0x785c, (q15_t)0xd471,
+  (q15_t)0x7859, (q15_t)0xd46b, (q15_t)0x7857, (q15_t)0xd465, (q15_t)0x7855, (q15_t)0xd45f, (q15_t)0x7853, (q15_t)0xd459,
+  (q15_t)0x7851, (q15_t)0xd453, (q15_t)0x784f, (q15_t)0xd44e, (q15_t)0x784d, (q15_t)0xd448, (q15_t)0x784a, (q15_t)0xd442,
+  (q15_t)0x7848, (q15_t)0xd43c, (q15_t)0x7846, (q15_t)0xd436, (q15_t)0x7844, (q15_t)0xd430, (q15_t)0x7842, (q15_t)0xd42a,
+  (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x783e, (q15_t)0xd41e, (q15_t)0x783b, (q15_t)0xd418, (q15_t)0x7839, (q15_t)0xd412,
+  (q15_t)0x7837, (q15_t)0xd40d, (q15_t)0x7835, (q15_t)0xd407, (q15_t)0x7833, (q15_t)0xd401, (q15_t)0x7831, (q15_t)0xd3fb,
+  (q15_t)0x782e, (q15_t)0xd3f5, (q15_t)0x782c, (q15_t)0xd3ef, (q15_t)0x782a, (q15_t)0xd3e9, (q15_t)0x7828, (q15_t)0xd3e3,
+  (q15_t)0x7826, (q15_t)0xd3dd, (q15_t)0x7824, (q15_t)0xd3d7, (q15_t)0x7821, (q15_t)0xd3d2, (q15_t)0x781f, (q15_t)0xd3cc,
+  (q15_t)0x781d, (q15_t)0xd3c6, (q15_t)0x781b, (q15_t)0xd3c0, (q15_t)0x7819, (q15_t)0xd3ba, (q15_t)0x7817, (q15_t)0xd3b4,
+  (q15_t)0x7814, (q15_t)0xd3ae, (q15_t)0x7812, (q15_t)0xd3a8, (q15_t)0x7810, (q15_t)0xd3a2, (q15_t)0x780e, (q15_t)0xd39d,
+  (q15_t)0x780c, (q15_t)0xd397, (q15_t)0x780a, (q15_t)0xd391, (q15_t)0x7807, (q15_t)0xd38b, (q15_t)0x7805, (q15_t)0xd385,
+  (q15_t)0x7803, (q15_t)0xd37f, (q15_t)0x7801, (q15_t)0xd379, (q15_t)0x77ff, (q15_t)0xd373, (q15_t)0x77fc, (q15_t)0xd36d,
+  (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77f8, (q15_t)0xd362, (q15_t)0x77f6, (q15_t)0xd35c, (q15_t)0x77f4, (q15_t)0xd356,
+  (q15_t)0x77f1, (q15_t)0xd350, (q15_t)0x77ef, (q15_t)0xd34a, (q15_t)0x77ed, (q15_t)0xd344, (q15_t)0x77eb, (q15_t)0xd33e,
+  (q15_t)0x77e9, (q15_t)0xd338, (q15_t)0x77e6, (q15_t)0xd333, (q15_t)0x77e4, (q15_t)0xd32d, (q15_t)0x77e2, (q15_t)0xd327,
+  (q15_t)0x77e0, (q15_t)0xd321, (q15_t)0x77de, (q15_t)0xd31b, (q15_t)0x77db, (q15_t)0xd315, (q15_t)0x77d9, (q15_t)0xd30f,
+  (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77d5, (q15_t)0xd303, (q15_t)0x77d3, (q15_t)0xd2fe, (q15_t)0x77d0, (q15_t)0xd2f8,
+  (q15_t)0x77ce, (q15_t)0xd2f2, (q15_t)0x77cc, (q15_t)0xd2ec, (q15_t)0x77ca, (q15_t)0xd2e6, (q15_t)0x77c8, (q15_t)0xd2e0,
+  (q15_t)0x77c5, (q15_t)0xd2da, (q15_t)0x77c3, (q15_t)0xd2d4, (q15_t)0x77c1, (q15_t)0xd2cf, (q15_t)0x77bf, (q15_t)0xd2c9,
+  (q15_t)0x77bc, (q15_t)0xd2c3, (q15_t)0x77ba, (q15_t)0xd2bd, (q15_t)0x77b8, (q15_t)0xd2b7, (q15_t)0x77b6, (q15_t)0xd2b1,
+  (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x77b1, (q15_t)0xd2a5, (q15_t)0x77af, (q15_t)0xd2a0, (q15_t)0x77ad, (q15_t)0xd29a,
+  (q15_t)0x77ab, (q15_t)0xd294, (q15_t)0x77a8, (q15_t)0xd28e, (q15_t)0x77a6, (q15_t)0xd288, (q15_t)0x77a4, (q15_t)0xd282,
+  (q15_t)0x77a2, (q15_t)0xd27c, (q15_t)0x77a0, (q15_t)0xd276, (q15_t)0x779d, (q15_t)0xd271, (q15_t)0x779b, (q15_t)0xd26b,
+  (q15_t)0x7799, (q15_t)0xd265, (q15_t)0x7797, (q15_t)0xd25f, (q15_t)0x7794, (q15_t)0xd259, (q15_t)0x7792, (q15_t)0xd253,
+  (q15_t)0x7790, (q15_t)0xd24d, (q15_t)0x778e, (q15_t)0xd247, (q15_t)0x778b, (q15_t)0xd242, (q15_t)0x7789, (q15_t)0xd23c,
+  (q15_t)0x7787, (q15_t)0xd236, (q15_t)0x7785, (q15_t)0xd230, (q15_t)0x7782, (q15_t)0xd22a, (q15_t)0x7780, (q15_t)0xd224,
+  (q15_t)0x777e, (q15_t)0xd21e, (q15_t)0x777c, (q15_t)0xd219, (q15_t)0x7779, (q15_t)0xd213, (q15_t)0x7777, (q15_t)0xd20d,
+  (q15_t)0x7775, (q15_t)0xd207, (q15_t)0x7773, (q15_t)0xd201, (q15_t)0x7770, (q15_t)0xd1fb, (q15_t)0x776e, (q15_t)0xd1f5,
+  (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x776a, (q15_t)0xd1ea, (q15_t)0x7767, (q15_t)0xd1e4, (q15_t)0x7765, (q15_t)0xd1de,
+  (q15_t)0x7763, (q15_t)0xd1d8, (q15_t)0x7760, (q15_t)0xd1d2, (q15_t)0x775e, (q15_t)0xd1cc, (q15_t)0x775c, (q15_t)0xd1c6,
+  (q15_t)0x775a, (q15_t)0xd1c1, (q15_t)0x7757, (q15_t)0xd1bb, (q15_t)0x7755, (q15_t)0xd1b5, (q15_t)0x7753, (q15_t)0xd1af,
+  (q15_t)0x7751, (q15_t)0xd1a9, (q15_t)0x774e, (q15_t)0xd1a3, (q15_t)0x774c, (q15_t)0xd19d, (q15_t)0x774a, (q15_t)0xd198,
+  (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x7745, (q15_t)0xd18c, (q15_t)0x7743, (q15_t)0xd186, (q15_t)0x7741, (q15_t)0xd180,
+  (q15_t)0x773e, (q15_t)0xd17a, (q15_t)0x773c, (q15_t)0xd174, (q15_t)0x773a, (q15_t)0xd16f, (q15_t)0x7738, (q15_t)0xd169,
+  (q15_t)0x7735, (q15_t)0xd163, (q15_t)0x7733, (q15_t)0xd15d, (q15_t)0x7731, (q15_t)0xd157, (q15_t)0x772e, (q15_t)0xd151,
+  (q15_t)0x772c, (q15_t)0xd14b, (q15_t)0x772a, (q15_t)0xd146, (q15_t)0x7727, (q15_t)0xd140, (q15_t)0x7725, (q15_t)0xd13a,
+  (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x7721, (q15_t)0xd12e, (q15_t)0x771e, (q15_t)0xd128, (q15_t)0x771c, (q15_t)0xd123,
+  (q15_t)0x771a, (q15_t)0xd11d, (q15_t)0x7717, (q15_t)0xd117, (q15_t)0x7715, (q15_t)0xd111, (q15_t)0x7713, (q15_t)0xd10b,
+  (q15_t)0x7710, (q15_t)0xd105, (q15_t)0x770e, (q15_t)0xd0ff, (q15_t)0x770c, (q15_t)0xd0fa, (q15_t)0x770a, (q15_t)0xd0f4,
+  (q15_t)0x7707, (q15_t)0xd0ee, (q15_t)0x7705, (q15_t)0xd0e8, (q15_t)0x7703, (q15_t)0xd0e2, (q15_t)0x7700, (q15_t)0xd0dc,
+  (q15_t)0x76fe, (q15_t)0xd0d7, (q15_t)0x76fc, (q15_t)0xd0d1, (q15_t)0x76f9, (q15_t)0xd0cb, (q15_t)0x76f7, (q15_t)0xd0c5,
+  (q15_t)0x76f5, (q15_t)0xd0bf, (q15_t)0x76f2, (q15_t)0xd0b9, (q15_t)0x76f0, (q15_t)0xd0b4, (q15_t)0x76ee, (q15_t)0xd0ae,
+  (q15_t)0x76eb, (q15_t)0xd0a8, (q15_t)0x76e9, (q15_t)0xd0a2, (q15_t)0x76e7, (q15_t)0xd09c, (q15_t)0x76e4, (q15_t)0xd096,
+  (q15_t)0x76e2, (q15_t)0xd091, (q15_t)0x76e0, (q15_t)0xd08b, (q15_t)0x76dd, (q15_t)0xd085, (q15_t)0x76db, (q15_t)0xd07f,
+  (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76d6, (q15_t)0xd073, (q15_t)0x76d4, (q15_t)0xd06e, (q15_t)0x76d2, (q15_t)0xd068,
+  (q15_t)0x76cf, (q15_t)0xd062, (q15_t)0x76cd, (q15_t)0xd05c, (q15_t)0x76cb, (q15_t)0xd056, (q15_t)0x76c8, (q15_t)0xd050,
+  (q15_t)0x76c6, (q15_t)0xd04b, (q15_t)0x76c4, (q15_t)0xd045, (q15_t)0x76c1, (q15_t)0xd03f, (q15_t)0x76bf, (q15_t)0xd039,
+  (q15_t)0x76bd, (q15_t)0xd033, (q15_t)0x76ba, (q15_t)0xd02d, (q15_t)0x76b8, (q15_t)0xd028, (q15_t)0x76b6, (q15_t)0xd022,
+  (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x76b1, (q15_t)0xd016, (q15_t)0x76af, (q15_t)0xd010, (q15_t)0x76ac, (q15_t)0xd00a,
+  (q15_t)0x76aa, (q15_t)0xd005, (q15_t)0x76a8, (q15_t)0xcfff, (q15_t)0x76a5, (q15_t)0xcff9, (q15_t)0x76a3, (q15_t)0xcff3,
+  (q15_t)0x76a0, (q15_t)0xcfed, (q15_t)0x769e, (q15_t)0xcfe7, (q15_t)0x769c, (q15_t)0xcfe2, (q15_t)0x7699, (q15_t)0xcfdc,
+  (q15_t)0x7697, (q15_t)0xcfd6, (q15_t)0x7695, (q15_t)0xcfd0, (q15_t)0x7692, (q15_t)0xcfca, (q15_t)0x7690, (q15_t)0xcfc5,
+  (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x768b, (q15_t)0xcfb9, (q15_t)0x7689, (q15_t)0xcfb3, (q15_t)0x7686, (q15_t)0xcfad,
+  (q15_t)0x7684, (q15_t)0xcfa7, (q15_t)0x7682, (q15_t)0xcfa2, (q15_t)0x767f, (q15_t)0xcf9c, (q15_t)0x767d, (q15_t)0xcf96,
+  (q15_t)0x767b, (q15_t)0xcf90, (q15_t)0x7678, (q15_t)0xcf8a, (q15_t)0x7676, (q15_t)0xcf85, (q15_t)0x7673, (q15_t)0xcf7f,
+  (q15_t)0x7671, (q15_t)0xcf79, (q15_t)0x766f, (q15_t)0xcf73, (q15_t)0x766c, (q15_t)0xcf6d, (q15_t)0x766a, (q15_t)0xcf67,
+  (q15_t)0x7668, (q15_t)0xcf62, (q15_t)0x7665, (q15_t)0xcf5c, (q15_t)0x7663, (q15_t)0xcf56, (q15_t)0x7660, (q15_t)0xcf50,
+  (q15_t)0x765e, (q15_t)0xcf4a, (q15_t)0x765c, (q15_t)0xcf45, (q15_t)0x7659, (q15_t)0xcf3f, (q15_t)0x7657, (q15_t)0xcf39,
+  (q15_t)0x7654, (q15_t)0xcf33, (q15_t)0x7652, (q15_t)0xcf2d, (q15_t)0x7650, (q15_t)0xcf28, (q15_t)0x764d, (q15_t)0xcf22,
+  (q15_t)0x764b, (q15_t)0xcf1c, (q15_t)0x7648, (q15_t)0xcf16, (q15_t)0x7646, (q15_t)0xcf10, (q15_t)0x7644, (q15_t)0xcf0b,
+  (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x763f, (q15_t)0xceff, (q15_t)0x763c, (q15_t)0xcef9, (q15_t)0x763a, (q15_t)0xcef3,
+  (q15_t)0x7638, (q15_t)0xceee, (q15_t)0x7635, (q15_t)0xcee8, (q15_t)0x7633, (q15_t)0xcee2, (q15_t)0x7630, (q15_t)0xcedc,
+  (q15_t)0x762e, (q15_t)0xced6, (q15_t)0x762b, (q15_t)0xced1, (q15_t)0x7629, (q15_t)0xcecb, (q15_t)0x7627, (q15_t)0xcec5,
+  (q15_t)0x7624, (q15_t)0xcebf, (q15_t)0x7622, (q15_t)0xceb9, (q15_t)0x761f, (q15_t)0xceb4, (q15_t)0x761d, (q15_t)0xceae,
+  (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x7618, (q15_t)0xcea2, (q15_t)0x7616, (q15_t)0xce9c, (q15_t)0x7613, (q15_t)0xce97,
+  (q15_t)0x7611, (q15_t)0xce91, (q15_t)0x760e, (q15_t)0xce8b, (q15_t)0x760c, (q15_t)0xce85, (q15_t)0x760a, (q15_t)0xce7f,
+  (q15_t)0x7607, (q15_t)0xce7a, (q15_t)0x7605, (q15_t)0xce74, (q15_t)0x7602, (q15_t)0xce6e, (q15_t)0x7600, (q15_t)0xce68,
+  (q15_t)0x75fd, (q15_t)0xce62, (q15_t)0x75fb, (q15_t)0xce5d, (q15_t)0x75f9, (q15_t)0xce57, (q15_t)0x75f6, (q15_t)0xce51,
+  (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75f1, (q15_t)0xce45, (q15_t)0x75ef, (q15_t)0xce40, (q15_t)0x75ec, (q15_t)0xce3a,
+  (q15_t)0x75ea, (q15_t)0xce34, (q15_t)0x75e7, (q15_t)0xce2e, (q15_t)0x75e5, (q15_t)0xce28, (q15_t)0x75e3, (q15_t)0xce23,
+  (q15_t)0x75e0, (q15_t)0xce1d, (q15_t)0x75de, (q15_t)0xce17, (q15_t)0x75db, (q15_t)0xce11, (q15_t)0x75d9, (q15_t)0xce0c,
+  (q15_t)0x75d6, (q15_t)0xce06, (q15_t)0x75d4, (q15_t)0xce00, (q15_t)0x75d1, (q15_t)0xcdfa, (q15_t)0x75cf, (q15_t)0xcdf4,
+  (q15_t)0x75cc, (q15_t)0xcdef, (q15_t)0x75ca, (q15_t)0xcde9, (q15_t)0x75c8, (q15_t)0xcde3, (q15_t)0x75c5, (q15_t)0xcddd,
+  (q15_t)0x75c3, (q15_t)0xcdd8, (q15_t)0x75c0, (q15_t)0xcdd2, (q15_t)0x75be, (q15_t)0xcdcc, (q15_t)0x75bb, (q15_t)0xcdc6,
+  (q15_t)0x75b9, (q15_t)0xcdc0, (q15_t)0x75b6, (q15_t)0xcdbb, (q15_t)0x75b4, (q15_t)0xcdb5, (q15_t)0x75b1, (q15_t)0xcdaf,
+  (q15_t)0x75af, (q15_t)0xcda9, (q15_t)0x75ac, (q15_t)0xcda3, (q15_t)0x75aa, (q15_t)0xcd9e, (q15_t)0x75a7, (q15_t)0xcd98,
+  (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x75a3, (q15_t)0xcd8c, (q15_t)0x75a0, (q15_t)0xcd87, (q15_t)0x759e, (q15_t)0xcd81,
+  (q15_t)0x759b, (q15_t)0xcd7b, (q15_t)0x7599, (q15_t)0xcd75, (q15_t)0x7596, (q15_t)0xcd70, (q15_t)0x7594, (q15_t)0xcd6a,
+  (q15_t)0x7591, (q15_t)0xcd64, (q15_t)0x758f, (q15_t)0xcd5e, (q15_t)0x758c, (q15_t)0xcd58, (q15_t)0x758a, (q15_t)0xcd53,
+  (q15_t)0x7587, (q15_t)0xcd4d, (q15_t)0x7585, (q15_t)0xcd47, (q15_t)0x7582, (q15_t)0xcd41, (q15_t)0x7580, (q15_t)0xcd3c,
+  (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x757b, (q15_t)0xcd30, (q15_t)0x7578, (q15_t)0xcd2a, (q15_t)0x7576, (q15_t)0xcd25,
+  (q15_t)0x7573, (q15_t)0xcd1f, (q15_t)0x7571, (q15_t)0xcd19, (q15_t)0x756e, (q15_t)0xcd13, (q15_t)0x756c, (q15_t)0xcd0d,
+  (q15_t)0x7569, (q15_t)0xcd08, (q15_t)0x7567, (q15_t)0xcd02, (q15_t)0x7564, (q15_t)0xccfc, (q15_t)0x7562, (q15_t)0xccf6,
+  (q15_t)0x755f, (q15_t)0xccf1, (q15_t)0x755d, (q15_t)0xcceb, (q15_t)0x755a, (q15_t)0xcce5, (q15_t)0x7558, (q15_t)0xccdf,
+  (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x7553, (q15_t)0xccd4, (q15_t)0x7550, (q15_t)0xccce, (q15_t)0x754e, (q15_t)0xccc8,
+  (q15_t)0x754b, (q15_t)0xccc3, (q15_t)0x7549, (q15_t)0xccbd, (q15_t)0x7546, (q15_t)0xccb7, (q15_t)0x7544, (q15_t)0xccb1,
+  (q15_t)0x7541, (q15_t)0xccac, (q15_t)0x753f, (q15_t)0xcca6, (q15_t)0x753c, (q15_t)0xcca0, (q15_t)0x753a, (q15_t)0xcc9a,
+  (q15_t)0x7537, (q15_t)0xcc95, (q15_t)0x7535, (q15_t)0xcc8f, (q15_t)0x7532, (q15_t)0xcc89, (q15_t)0x752f, (q15_t)0xcc83,
+  (q15_t)0x752d, (q15_t)0xcc7e, (q15_t)0x752a, (q15_t)0xcc78, (q15_t)0x7528, (q15_t)0xcc72, (q15_t)0x7525, (q15_t)0xcc6c,
+  (q15_t)0x7523, (q15_t)0xcc67, (q15_t)0x7520, (q15_t)0xcc61, (q15_t)0x751e, (q15_t)0xcc5b, (q15_t)0x751b, (q15_t)0xcc55,
+  (q15_t)0x7519, (q15_t)0xcc50, (q15_t)0x7516, (q15_t)0xcc4a, (q15_t)0x7514, (q15_t)0xcc44, (q15_t)0x7511, (q15_t)0xcc3e,
+  (q15_t)0x750f, (q15_t)0xcc39, (q15_t)0x750c, (q15_t)0xcc33, (q15_t)0x7509, (q15_t)0xcc2d, (q15_t)0x7507, (q15_t)0xcc27,
+  (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x7502, (q15_t)0xcc1c, (q15_t)0x74ff, (q15_t)0xcc16, (q15_t)0x74fd, (q15_t)0xcc10,
+  (q15_t)0x74fa, (q15_t)0xcc0b, (q15_t)0x74f8, (q15_t)0xcc05, (q15_t)0x74f5, (q15_t)0xcbff, (q15_t)0x74f2, (q15_t)0xcbf9,
+  (q15_t)0x74f0, (q15_t)0xcbf4, (q15_t)0x74ed, (q15_t)0xcbee, (q15_t)0x74eb, (q15_t)0xcbe8, (q15_t)0x74e8, (q15_t)0xcbe2,
+  (q15_t)0x74e6, (q15_t)0xcbdd, (q15_t)0x74e3, (q15_t)0xcbd7, (q15_t)0x74e1, (q15_t)0xcbd1, (q15_t)0x74de, (q15_t)0xcbcb,
+  (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74d9, (q15_t)0xcbc0, (q15_t)0x74d6, (q15_t)0xcbba, (q15_t)0x74d4, (q15_t)0xcbb5,
+  (q15_t)0x74d1, (q15_t)0xcbaf, (q15_t)0x74cf, (q15_t)0xcba9, (q15_t)0x74cc, (q15_t)0xcba3, (q15_t)0x74c9, (q15_t)0xcb9e,
+  (q15_t)0x74c7, (q15_t)0xcb98, (q15_t)0x74c4, (q15_t)0xcb92, (q15_t)0x74c2, (q15_t)0xcb8c, (q15_t)0x74bf, (q15_t)0xcb87,
+  (q15_t)0x74bd, (q15_t)0xcb81, (q15_t)0x74ba, (q15_t)0xcb7b, (q15_t)0x74b7, (q15_t)0xcb75, (q15_t)0x74b5, (q15_t)0xcb70,
+  (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x74b0, (q15_t)0xcb64, (q15_t)0x74ad, (q15_t)0xcb5f, (q15_t)0x74ab, (q15_t)0xcb59,
+  (q15_t)0x74a8, (q15_t)0xcb53, (q15_t)0x74a5, (q15_t)0xcb4d, (q15_t)0x74a3, (q15_t)0xcb48, (q15_t)0x74a0, (q15_t)0xcb42,
+  (q15_t)0x749e, (q15_t)0xcb3c, (q15_t)0x749b, (q15_t)0xcb36, (q15_t)0x7498, (q15_t)0xcb31, (q15_t)0x7496, (q15_t)0xcb2b,
+  (q15_t)0x7493, (q15_t)0xcb25, (q15_t)0x7491, (q15_t)0xcb20, (q15_t)0x748e, (q15_t)0xcb1a, (q15_t)0x748b, (q15_t)0xcb14,
+  (q15_t)0x7489, (q15_t)0xcb0e, (q15_t)0x7486, (q15_t)0xcb09, (q15_t)0x7484, (q15_t)0xcb03, (q15_t)0x7481, (q15_t)0xcafd,
+  (q15_t)0x747e, (q15_t)0xcaf8, (q15_t)0x747c, (q15_t)0xcaf2, (q15_t)0x7479, (q15_t)0xcaec, (q15_t)0x7477, (q15_t)0xcae6,
+  (q15_t)0x7474, (q15_t)0xcae1, (q15_t)0x7471, (q15_t)0xcadb, (q15_t)0x746f, (q15_t)0xcad5, (q15_t)0x746c, (q15_t)0xcad0,
+  (q15_t)0x746a, (q15_t)0xcaca, (q15_t)0x7467, (q15_t)0xcac4, (q15_t)0x7464, (q15_t)0xcabe, (q15_t)0x7462, (q15_t)0xcab9,
+  (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x745c, (q15_t)0xcaad, (q15_t)0x745a, (q15_t)0xcaa8, (q15_t)0x7457, (q15_t)0xcaa2,
+  (q15_t)0x7455, (q15_t)0xca9c, (q15_t)0x7452, (q15_t)0xca96, (q15_t)0x744f, (q15_t)0xca91, (q15_t)0x744d, (q15_t)0xca8b,
+  (q15_t)0x744a, (q15_t)0xca85, (q15_t)0x7448, (q15_t)0xca80, (q15_t)0x7445, (q15_t)0xca7a, (q15_t)0x7442, (q15_t)0xca74,
+  (q15_t)0x7440, (q15_t)0xca6e, (q15_t)0x743d, (q15_t)0xca69, (q15_t)0x743a, (q15_t)0xca63, (q15_t)0x7438, (q15_t)0xca5d,
+  (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x7432, (q15_t)0xca52, (q15_t)0x7430, (q15_t)0xca4c, (q15_t)0x742d, (q15_t)0xca46,
+  (q15_t)0x742b, (q15_t)0xca41, (q15_t)0x7428, (q15_t)0xca3b, (q15_t)0x7425, (q15_t)0xca35, (q15_t)0x7423, (q15_t)0xca30,
+  (q15_t)0x7420, (q15_t)0xca2a, (q15_t)0x741d, (q15_t)0xca24, (q15_t)0x741b, (q15_t)0xca1f, (q15_t)0x7418, (q15_t)0xca19,
+  (q15_t)0x7415, (q15_t)0xca13, (q15_t)0x7413, (q15_t)0xca0d, (q15_t)0x7410, (q15_t)0xca08, (q15_t)0x740d, (q15_t)0xca02,
+  (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x7408, (q15_t)0xc9f7, (q15_t)0x7406, (q15_t)0xc9f1, (q15_t)0x7403, (q15_t)0xc9eb,
+  (q15_t)0x7400, (q15_t)0xc9e6, (q15_t)0x73fe, (q15_t)0xc9e0, (q15_t)0x73fb, (q15_t)0xc9da, (q15_t)0x73f8, (q15_t)0xc9d5,
+  (q15_t)0x73f6, (q15_t)0xc9cf, (q15_t)0x73f3, (q15_t)0xc9c9, (q15_t)0x73f0, (q15_t)0xc9c3, (q15_t)0x73ee, (q15_t)0xc9be,
+  (q15_t)0x73eb, (q15_t)0xc9b8, (q15_t)0x73e8, (q15_t)0xc9b2, (q15_t)0x73e6, (q15_t)0xc9ad, (q15_t)0x73e3, (q15_t)0xc9a7,
+  (q15_t)0x73e0, (q15_t)0xc9a1, (q15_t)0x73de, (q15_t)0xc99c, (q15_t)0x73db, (q15_t)0xc996, (q15_t)0x73d8, (q15_t)0xc990,
+  (q15_t)0x73d6, (q15_t)0xc98b, (q15_t)0x73d3, (q15_t)0xc985, (q15_t)0x73d0, (q15_t)0xc97f, (q15_t)0x73ce, (q15_t)0xc97a,
+  (q15_t)0x73cb, (q15_t)0xc974, (q15_t)0x73c8, (q15_t)0xc96e, (q15_t)0x73c6, (q15_t)0xc968, (q15_t)0x73c3, (q15_t)0xc963,
+  (q15_t)0x73c0, (q15_t)0xc95d, (q15_t)0x73bd, (q15_t)0xc957, (q15_t)0x73bb, (q15_t)0xc952, (q15_t)0x73b8, (q15_t)0xc94c,
+  (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x73b3, (q15_t)0xc941, (q15_t)0x73b0, (q15_t)0xc93b, (q15_t)0x73ad, (q15_t)0xc935,
+  (q15_t)0x73ab, (q15_t)0xc930, (q15_t)0x73a8, (q15_t)0xc92a, (q15_t)0x73a5, (q15_t)0xc924, (q15_t)0x73a3, (q15_t)0xc91f,
+  (q15_t)0x73a0, (q15_t)0xc919, (q15_t)0x739d, (q15_t)0xc913, (q15_t)0x739b, (q15_t)0xc90e, (q15_t)0x7398, (q15_t)0xc908,
+  (q15_t)0x7395, (q15_t)0xc902, (q15_t)0x7392, (q15_t)0xc8fd, (q15_t)0x7390, (q15_t)0xc8f7, (q15_t)0x738d, (q15_t)0xc8f1,
+  (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x7388, (q15_t)0xc8e6, (q15_t)0x7385, (q15_t)0xc8e0, (q15_t)0x7382, (q15_t)0xc8db,
+  (q15_t)0x737f, (q15_t)0xc8d5, (q15_t)0x737d, (q15_t)0xc8cf, (q15_t)0x737a, (q15_t)0xc8ca, (q15_t)0x7377, (q15_t)0xc8c4,
+  (q15_t)0x7375, (q15_t)0xc8be, (q15_t)0x7372, (q15_t)0xc8b9, (q15_t)0x736f, (q15_t)0xc8b3, (q15_t)0x736c, (q15_t)0xc8ad,
+  (q15_t)0x736a, (q15_t)0xc8a8, (q15_t)0x7367, (q15_t)0xc8a2, (q15_t)0x7364, (q15_t)0xc89c, (q15_t)0x7362, (q15_t)0xc897,
+  (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x735c, (q15_t)0xc88b, (q15_t)0x7359, (q15_t)0xc886, (q15_t)0x7357, (q15_t)0xc880,
+  (q15_t)0x7354, (q15_t)0xc87a, (q15_t)0x7351, (q15_t)0xc875, (q15_t)0x734f, (q15_t)0xc86f, (q15_t)0x734c, (q15_t)0xc869,
+  (q15_t)0x7349, (q15_t)0xc864, (q15_t)0x7346, (q15_t)0xc85e, (q15_t)0x7344, (q15_t)0xc858, (q15_t)0x7341, (q15_t)0xc853,
+  (q15_t)0x733e, (q15_t)0xc84d, (q15_t)0x733b, (q15_t)0xc847, (q15_t)0x7339, (q15_t)0xc842, (q15_t)0x7336, (q15_t)0xc83c,
+  (q15_t)0x7333, (q15_t)0xc836, (q15_t)0x7330, (q15_t)0xc831, (q15_t)0x732e, (q15_t)0xc82b, (q15_t)0x732b, (q15_t)0xc825,
+  (q15_t)0x7328, (q15_t)0xc820, (q15_t)0x7326, (q15_t)0xc81a, (q15_t)0x7323, (q15_t)0xc814, (q15_t)0x7320, (q15_t)0xc80f,
+  (q15_t)0x731d, (q15_t)0xc809, (q15_t)0x731b, (q15_t)0xc803, (q15_t)0x7318, (q15_t)0xc7fe, (q15_t)0x7315, (q15_t)0xc7f8,
+  (q15_t)0x7312, (q15_t)0xc7f3, (q15_t)0x7310, (q15_t)0xc7ed, (q15_t)0x730d, (q15_t)0xc7e7, (q15_t)0x730a, (q15_t)0xc7e2,
+  (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x7305, (q15_t)0xc7d6, (q15_t)0x7302, (q15_t)0xc7d1, (q15_t)0x72ff, (q15_t)0xc7cb,
+  (q15_t)0x72fc, (q15_t)0xc7c5, (q15_t)0x72f9, (q15_t)0xc7c0, (q15_t)0x72f7, (q15_t)0xc7ba, (q15_t)0x72f4, (q15_t)0xc7b4,
+  (q15_t)0x72f1, (q15_t)0xc7af, (q15_t)0x72ee, (q15_t)0xc7a9, (q15_t)0x72ec, (q15_t)0xc7a3, (q15_t)0x72e9, (q15_t)0xc79e,
+  (q15_t)0x72e6, (q15_t)0xc798, (q15_t)0x72e3, (q15_t)0xc793, (q15_t)0x72e1, (q15_t)0xc78d, (q15_t)0x72de, (q15_t)0xc787,
+  (q15_t)0x72db, (q15_t)0xc782, (q15_t)0x72d8, (q15_t)0xc77c, (q15_t)0x72d5, (q15_t)0xc776, (q15_t)0x72d3, (q15_t)0xc771,
+  (q15_t)0x72d0, (q15_t)0xc76b, (q15_t)0x72cd, (q15_t)0xc765, (q15_t)0x72ca, (q15_t)0xc760, (q15_t)0x72c8, (q15_t)0xc75a,
+  (q15_t)0x72c5, (q15_t)0xc755, (q15_t)0x72c2, (q15_t)0xc74f, (q15_t)0x72bf, (q15_t)0xc749, (q15_t)0x72bc, (q15_t)0xc744,
+  (q15_t)0x72ba, (q15_t)0xc73e, (q15_t)0x72b7, (q15_t)0xc738, (q15_t)0x72b4, (q15_t)0xc733, (q15_t)0x72b1, (q15_t)0xc72d,
+  (q15_t)0x72af, (q15_t)0xc728, (q15_t)0x72ac, (q15_t)0xc722, (q15_t)0x72a9, (q15_t)0xc71c, (q15_t)0x72a6, (q15_t)0xc717,
+  (q15_t)0x72a3, (q15_t)0xc711, (q15_t)0x72a1, (q15_t)0xc70b, (q15_t)0x729e, (q15_t)0xc706, (q15_t)0x729b, (q15_t)0xc700,
+  (q15_t)0x7298, (q15_t)0xc6fa, (q15_t)0x7295, (q15_t)0xc6f5, (q15_t)0x7293, (q15_t)0xc6ef, (q15_t)0x7290, (q15_t)0xc6ea,
+  (q15_t)0x728d, (q15_t)0xc6e4, (q15_t)0x728a, (q15_t)0xc6de, (q15_t)0x7287, (q15_t)0xc6d9, (q15_t)0x7285, (q15_t)0xc6d3,
+  (q15_t)0x7282, (q15_t)0xc6ce, (q15_t)0x727f, (q15_t)0xc6c8, (q15_t)0x727c, (q15_t)0xc6c2, (q15_t)0x7279, (q15_t)0xc6bd,
+  (q15_t)0x7276, (q15_t)0xc6b7, (q15_t)0x7274, (q15_t)0xc6b1, (q15_t)0x7271, (q15_t)0xc6ac, (q15_t)0x726e, (q15_t)0xc6a6,
+  (q15_t)0x726b, (q15_t)0xc6a1, (q15_t)0x7268, (q15_t)0xc69b, (q15_t)0x7266, (q15_t)0xc695, (q15_t)0x7263, (q15_t)0xc690,
+  (q15_t)0x7260, (q15_t)0xc68a, (q15_t)0x725d, (q15_t)0xc684, (q15_t)0x725a, (q15_t)0xc67f, (q15_t)0x7257, (q15_t)0xc679,
+  (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x7252, (q15_t)0xc66e, (q15_t)0x724f, (q15_t)0xc668, (q15_t)0x724c, (q15_t)0xc663,
+  (q15_t)0x7249, (q15_t)0xc65d, (q15_t)0x7247, (q15_t)0xc658, (q15_t)0x7244, (q15_t)0xc652, (q15_t)0x7241, (q15_t)0xc64c,
+  (q15_t)0x723e, (q15_t)0xc647, (q15_t)0x723b, (q15_t)0xc641, (q15_t)0x7238, (q15_t)0xc63c, (q15_t)0x7236, (q15_t)0xc636,
+  (q15_t)0x7233, (q15_t)0xc630, (q15_t)0x7230, (q15_t)0xc62b, (q15_t)0x722d, (q15_t)0xc625, (q15_t)0x722a, (q15_t)0xc620,
+  (q15_t)0x7227, (q15_t)0xc61a, (q15_t)0x7224, (q15_t)0xc614, (q15_t)0x7222, (q15_t)0xc60f, (q15_t)0x721f, (q15_t)0xc609,
+  (q15_t)0x721c, (q15_t)0xc603, (q15_t)0x7219, (q15_t)0xc5fe, (q15_t)0x7216, (q15_t)0xc5f8, (q15_t)0x7213, (q15_t)0xc5f3,
+  (q15_t)0x7211, (q15_t)0xc5ed, (q15_t)0x720e, (q15_t)0xc5e7, (q15_t)0x720b, (q15_t)0xc5e2, (q15_t)0x7208, (q15_t)0xc5dc,
+  (q15_t)0x7205, (q15_t)0xc5d7, (q15_t)0x7202, (q15_t)0xc5d1, (q15_t)0x71ff, (q15_t)0xc5cc, (q15_t)0x71fd, (q15_t)0xc5c6,
+  (q15_t)0x71fa, (q15_t)0xc5c0, (q15_t)0x71f7, (q15_t)0xc5bb, (q15_t)0x71f4, (q15_t)0xc5b5, (q15_t)0x71f1, (q15_t)0xc5b0,
+  (q15_t)0x71ee, (q15_t)0xc5aa, (q15_t)0x71eb, (q15_t)0xc5a4, (q15_t)0x71e9, (q15_t)0xc59f, (q15_t)0x71e6, (q15_t)0xc599,
+  (q15_t)0x71e3, (q15_t)0xc594, (q15_t)0x71e0, (q15_t)0xc58e, (q15_t)0x71dd, (q15_t)0xc588, (q15_t)0x71da, (q15_t)0xc583,
+  (q15_t)0x71d7, (q15_t)0xc57d, (q15_t)0x71d4, (q15_t)0xc578, (q15_t)0x71d2, (q15_t)0xc572, (q15_t)0x71cf, (q15_t)0xc56c,
+  (q15_t)0x71cc, (q15_t)0xc567, (q15_t)0x71c9, (q15_t)0xc561, (q15_t)0x71c6, (q15_t)0xc55c, (q15_t)0x71c3, (q15_t)0xc556,
+  (q15_t)0x71c0, (q15_t)0xc551, (q15_t)0x71bd, (q15_t)0xc54b, (q15_t)0x71bb, (q15_t)0xc545, (q15_t)0x71b8, (q15_t)0xc540,
+  (q15_t)0x71b5, (q15_t)0xc53a, (q15_t)0x71b2, (q15_t)0xc535, (q15_t)0x71af, (q15_t)0xc52f, (q15_t)0x71ac, (q15_t)0xc529,
+  (q15_t)0x71a9, (q15_t)0xc524, (q15_t)0x71a6, (q15_t)0xc51e, (q15_t)0x71a3, (q15_t)0xc519, (q15_t)0x71a1, (q15_t)0xc513,
+  (q15_t)0x719e, (q15_t)0xc50e, (q15_t)0x719b, (q15_t)0xc508, (q15_t)0x7198, (q15_t)0xc502, (q15_t)0x7195, (q15_t)0xc4fd,
+  (q15_t)0x7192, (q15_t)0xc4f7, (q15_t)0x718f, (q15_t)0xc4f2, (q15_t)0x718c, (q15_t)0xc4ec, (q15_t)0x7189, (q15_t)0xc4e7,
+  (q15_t)0x7186, (q15_t)0xc4e1, (q15_t)0x7184, (q15_t)0xc4db, (q15_t)0x7181, (q15_t)0xc4d6, (q15_t)0x717e, (q15_t)0xc4d0,
+  (q15_t)0x717b, (q15_t)0xc4cb, (q15_t)0x7178, (q15_t)0xc4c5, (q15_t)0x7175, (q15_t)0xc4c0, (q15_t)0x7172, (q15_t)0xc4ba,
+  (q15_t)0x716f, (q15_t)0xc4b4, (q15_t)0x716c, (q15_t)0xc4af, (q15_t)0x7169, (q15_t)0xc4a9, (q15_t)0x7167, (q15_t)0xc4a4,
+  (q15_t)0x7164, (q15_t)0xc49e, (q15_t)0x7161, (q15_t)0xc499, (q15_t)0x715e, (q15_t)0xc493, (q15_t)0x715b, (q15_t)0xc48d,
+  (q15_t)0x7158, (q15_t)0xc488, (q15_t)0x7155, (q15_t)0xc482, (q15_t)0x7152, (q15_t)0xc47d, (q15_t)0x714f, (q15_t)0xc477,
+  (q15_t)0x714c, (q15_t)0xc472, (q15_t)0x7149, (q15_t)0xc46c, (q15_t)0x7146, (q15_t)0xc467, (q15_t)0x7143, (q15_t)0xc461,
+  (q15_t)0x7141, (q15_t)0xc45b, (q15_t)0x713e, (q15_t)0xc456, (q15_t)0x713b, (q15_t)0xc450, (q15_t)0x7138, (q15_t)0xc44b,
+  (q15_t)0x7135, (q15_t)0xc445, (q15_t)0x7132, (q15_t)0xc440, (q15_t)0x712f, (q15_t)0xc43a, (q15_t)0x712c, (q15_t)0xc434,
+  (q15_t)0x7129, (q15_t)0xc42f, (q15_t)0x7126, (q15_t)0xc429, (q15_t)0x7123, (q15_t)0xc424, (q15_t)0x7120, (q15_t)0xc41e,
+  (q15_t)0x711d, (q15_t)0xc419, (q15_t)0x711a, (q15_t)0xc413, (q15_t)0x7117, (q15_t)0xc40e, (q15_t)0x7114, (q15_t)0xc408,
+  (q15_t)0x7112, (q15_t)0xc403, (q15_t)0x710f, (q15_t)0xc3fd, (q15_t)0x710c, (q15_t)0xc3f7, (q15_t)0x7109, (q15_t)0xc3f2,
+  (q15_t)0x7106, (q15_t)0xc3ec, (q15_t)0x7103, (q15_t)0xc3e7, (q15_t)0x7100, (q15_t)0xc3e1, (q15_t)0x70fd, (q15_t)0xc3dc,
+  (q15_t)0x70fa, (q15_t)0xc3d6, (q15_t)0x70f7, (q15_t)0xc3d1, (q15_t)0x70f4, (q15_t)0xc3cb, (q15_t)0x70f1, (q15_t)0xc3c5,
+  (q15_t)0x70ee, (q15_t)0xc3c0, (q15_t)0x70eb, (q15_t)0xc3ba, (q15_t)0x70e8, (q15_t)0xc3b5, (q15_t)0x70e5, (q15_t)0xc3af,
+  (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x70df, (q15_t)0xc3a4, (q15_t)0x70dc, (q15_t)0xc39f, (q15_t)0x70d9, (q15_t)0xc399,
+  (q15_t)0x70d6, (q15_t)0xc394, (q15_t)0x70d3, (q15_t)0xc38e, (q15_t)0x70d1, (q15_t)0xc389, (q15_t)0x70ce, (q15_t)0xc383,
+  (q15_t)0x70cb, (q15_t)0xc37d, (q15_t)0x70c8, (q15_t)0xc378, (q15_t)0x70c5, (q15_t)0xc372, (q15_t)0x70c2, (q15_t)0xc36d,
+  (q15_t)0x70bf, (q15_t)0xc367, (q15_t)0x70bc, (q15_t)0xc362, (q15_t)0x70b9, (q15_t)0xc35c, (q15_t)0x70b6, (q15_t)0xc357,
+  (q15_t)0x70b3, (q15_t)0xc351, (q15_t)0x70b0, (q15_t)0xc34c, (q15_t)0x70ad, (q15_t)0xc346, (q15_t)0x70aa, (q15_t)0xc341,
+  (q15_t)0x70a7, (q15_t)0xc33b, (q15_t)0x70a4, (q15_t)0xc336, (q15_t)0x70a1, (q15_t)0xc330, (q15_t)0x709e, (q15_t)0xc32a,
+  (q15_t)0x709b, (q15_t)0xc325, (q15_t)0x7098, (q15_t)0xc31f, (q15_t)0x7095, (q15_t)0xc31a, (q15_t)0x7092, (q15_t)0xc314,
+  (q15_t)0x708f, (q15_t)0xc30f, (q15_t)0x708c, (q15_t)0xc309, (q15_t)0x7089, (q15_t)0xc304, (q15_t)0x7086, (q15_t)0xc2fe,
+  (q15_t)0x7083, (q15_t)0xc2f9, (q15_t)0x7080, (q15_t)0xc2f3, (q15_t)0x707d, (q15_t)0xc2ee, (q15_t)0x707a, (q15_t)0xc2e8,
+  (q15_t)0x7077, (q15_t)0xc2e3, (q15_t)0x7074, (q15_t)0xc2dd, (q15_t)0x7071, (q15_t)0xc2d8, (q15_t)0x706e, (q15_t)0xc2d2,
+  (q15_t)0x706b, (q15_t)0xc2cd, (q15_t)0x7068, (q15_t)0xc2c7, (q15_t)0x7065, (q15_t)0xc2c2, (q15_t)0x7062, (q15_t)0xc2bc,
+  (q15_t)0x705f, (q15_t)0xc2b7, (q15_t)0x705c, (q15_t)0xc2b1, (q15_t)0x7059, (q15_t)0xc2ab, (q15_t)0x7056, (q15_t)0xc2a6,
+  (q15_t)0x7053, (q15_t)0xc2a0, (q15_t)0x7050, (q15_t)0xc29b, (q15_t)0x704d, (q15_t)0xc295, (q15_t)0x704a, (q15_t)0xc290,
+  (q15_t)0x7047, (q15_t)0xc28a, (q15_t)0x7044, (q15_t)0xc285, (q15_t)0x7041, (q15_t)0xc27f, (q15_t)0x703e, (q15_t)0xc27a,
+  (q15_t)0x703b, (q15_t)0xc274, (q15_t)0x7038, (q15_t)0xc26f, (q15_t)0x7035, (q15_t)0xc269, (q15_t)0x7032, (q15_t)0xc264,
+  (q15_t)0x702f, (q15_t)0xc25e, (q15_t)0x702c, (q15_t)0xc259, (q15_t)0x7029, (q15_t)0xc253, (q15_t)0x7026, (q15_t)0xc24e,
+  (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x7020, (q15_t)0xc243, (q15_t)0x701d, (q15_t)0xc23d, (q15_t)0x7019, (q15_t)0xc238,
+  (q15_t)0x7016, (q15_t)0xc232, (q15_t)0x7013, (q15_t)0xc22d, (q15_t)0x7010, (q15_t)0xc227, (q15_t)0x700d, (q15_t)0xc222,
+  (q15_t)0x700a, (q15_t)0xc21c, (q15_t)0x7007, (q15_t)0xc217, (q15_t)0x7004, (q15_t)0xc211, (q15_t)0x7001, (q15_t)0xc20c,
+  (q15_t)0x6ffe, (q15_t)0xc206, (q15_t)0x6ffb, (q15_t)0xc201, (q15_t)0x6ff8, (q15_t)0xc1fb, (q15_t)0x6ff5, (q15_t)0xc1f6,
+  (q15_t)0x6ff2, (q15_t)0xc1f0, (q15_t)0x6fef, (q15_t)0xc1eb, (q15_t)0x6fec, (q15_t)0xc1e5, (q15_t)0x6fe9, (q15_t)0xc1e0,
+  (q15_t)0x6fe6, (q15_t)0xc1da, (q15_t)0x6fe3, (q15_t)0xc1d5, (q15_t)0x6fe0, (q15_t)0xc1cf, (q15_t)0x6fdd, (q15_t)0xc1ca,
+  (q15_t)0x6fda, (q15_t)0xc1c4, (q15_t)0x6fd6, (q15_t)0xc1bf, (q15_t)0x6fd3, (q15_t)0xc1b9, (q15_t)0x6fd0, (q15_t)0xc1b4,
+  (q15_t)0x6fcd, (q15_t)0xc1ae, (q15_t)0x6fca, (q15_t)0xc1a9, (q15_t)0x6fc7, (q15_t)0xc1a3, (q15_t)0x6fc4, (q15_t)0xc19e,
+  (q15_t)0x6fc1, (q15_t)0xc198, (q15_t)0x6fbe, (q15_t)0xc193, (q15_t)0x6fbb, (q15_t)0xc18d, (q15_t)0x6fb8, (q15_t)0xc188,
+  (q15_t)0x6fb5, (q15_t)0xc183, (q15_t)0x6fb2, (q15_t)0xc17d, (q15_t)0x6faf, (q15_t)0xc178, (q15_t)0x6fac, (q15_t)0xc172,
+  (q15_t)0x6fa9, (q15_t)0xc16d, (q15_t)0x6fa5, (q15_t)0xc167, (q15_t)0x6fa2, (q15_t)0xc162, (q15_t)0x6f9f, (q15_t)0xc15c,
+  (q15_t)0x6f9c, (q15_t)0xc157, (q15_t)0x6f99, (q15_t)0xc151, (q15_t)0x6f96, (q15_t)0xc14c, (q15_t)0x6f93, (q15_t)0xc146,
+  (q15_t)0x6f90, (q15_t)0xc141, (q15_t)0x6f8d, (q15_t)0xc13b, (q15_t)0x6f8a, (q15_t)0xc136, (q15_t)0x6f87, (q15_t)0xc130,
+  (q15_t)0x6f84, (q15_t)0xc12b, (q15_t)0x6f81, (q15_t)0xc125, (q15_t)0x6f7d, (q15_t)0xc120, (q15_t)0x6f7a, (q15_t)0xc11a,
+  (q15_t)0x6f77, (q15_t)0xc115, (q15_t)0x6f74, (q15_t)0xc10f, (q15_t)0x6f71, (q15_t)0xc10a, (q15_t)0x6f6e, (q15_t)0xc105,
+  (q15_t)0x6f6b, (q15_t)0xc0ff, (q15_t)0x6f68, (q15_t)0xc0fa, (q15_t)0x6f65, (q15_t)0xc0f4, (q15_t)0x6f62, (q15_t)0xc0ef,
+  (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6f5b, (q15_t)0xc0e4, (q15_t)0x6f58, (q15_t)0xc0de, (q15_t)0x6f55, (q15_t)0xc0d9,
+  (q15_t)0x6f52, (q15_t)0xc0d3, (q15_t)0x6f4f, (q15_t)0xc0ce, (q15_t)0x6f4c, (q15_t)0xc0c8, (q15_t)0x6f49, (q15_t)0xc0c3,
+  (q15_t)0x6f46, (q15_t)0xc0bd, (q15_t)0x6f43, (q15_t)0xc0b8, (q15_t)0x6f3f, (q15_t)0xc0b3, (q15_t)0x6f3c, (q15_t)0xc0ad,
+  (q15_t)0x6f39, (q15_t)0xc0a8, (q15_t)0x6f36, (q15_t)0xc0a2, (q15_t)0x6f33, (q15_t)0xc09d, (q15_t)0x6f30, (q15_t)0xc097,
+  (q15_t)0x6f2d, (q15_t)0xc092, (q15_t)0x6f2a, (q15_t)0xc08c, (q15_t)0x6f27, (q15_t)0xc087, (q15_t)0x6f23, (q15_t)0xc081,
+  (q15_t)0x6f20, (q15_t)0xc07c, (q15_t)0x6f1d, (q15_t)0xc077, (q15_t)0x6f1a, (q15_t)0xc071, (q15_t)0x6f17, (q15_t)0xc06c,
+  (q15_t)0x6f14, (q15_t)0xc066, (q15_t)0x6f11, (q15_t)0xc061, (q15_t)0x6f0e, (q15_t)0xc05b, (q15_t)0x6f0b, (q15_t)0xc056,
+  (q15_t)0x6f07, (q15_t)0xc050, (q15_t)0x6f04, (q15_t)0xc04b, (q15_t)0x6f01, (q15_t)0xc045, (q15_t)0x6efe, (q15_t)0xc040,
+  (q15_t)0x6efb, (q15_t)0xc03b, (q15_t)0x6ef8, (q15_t)0xc035, (q15_t)0x6ef5, (q15_t)0xc030, (q15_t)0x6ef1, (q15_t)0xc02a,
+  (q15_t)0x6eee, (q15_t)0xc025, (q15_t)0x6eeb, (q15_t)0xc01f, (q15_t)0x6ee8, (q15_t)0xc01a, (q15_t)0x6ee5, (q15_t)0xc014,
+  (q15_t)0x6ee2, (q15_t)0xc00f, (q15_t)0x6edf, (q15_t)0xc00a, (q15_t)0x6edc, (q15_t)0xc004, (q15_t)0x6ed8, (q15_t)0xbfff,
+  (q15_t)0x6ed5, (q15_t)0xbff9, (q15_t)0x6ed2, (q15_t)0xbff4, (q15_t)0x6ecf, (q15_t)0xbfee, (q15_t)0x6ecc, (q15_t)0xbfe9,
+  (q15_t)0x6ec9, (q15_t)0xbfe3, (q15_t)0x6ec6, (q15_t)0xbfde, (q15_t)0x6ec2, (q15_t)0xbfd9, (q15_t)0x6ebf, (q15_t)0xbfd3,
+  (q15_t)0x6ebc, (q15_t)0xbfce, (q15_t)0x6eb9, (q15_t)0xbfc8, (q15_t)0x6eb6, (q15_t)0xbfc3, (q15_t)0x6eb3, (q15_t)0xbfbd,
+  (q15_t)0x6eaf, (q15_t)0xbfb8, (q15_t)0x6eac, (q15_t)0xbfb3, (q15_t)0x6ea9, (q15_t)0xbfad, (q15_t)0x6ea6, (q15_t)0xbfa8,
+  (q15_t)0x6ea3, (q15_t)0xbfa2, (q15_t)0x6ea0, (q15_t)0xbf9d, (q15_t)0x6e9c, (q15_t)0xbf97, (q15_t)0x6e99, (q15_t)0xbf92,
+  (q15_t)0x6e96, (q15_t)0xbf8d, (q15_t)0x6e93, (q15_t)0xbf87, (q15_t)0x6e90, (q15_t)0xbf82, (q15_t)0x6e8d, (q15_t)0xbf7c,
+  (q15_t)0x6e89, (q15_t)0xbf77, (q15_t)0x6e86, (q15_t)0xbf71, (q15_t)0x6e83, (q15_t)0xbf6c, (q15_t)0x6e80, (q15_t)0xbf67,
+  (q15_t)0x6e7d, (q15_t)0xbf61, (q15_t)0x6e7a, (q15_t)0xbf5c, (q15_t)0x6e76, (q15_t)0xbf56, (q15_t)0x6e73, (q15_t)0xbf51,
+  (q15_t)0x6e70, (q15_t)0xbf4b, (q15_t)0x6e6d, (q15_t)0xbf46, (q15_t)0x6e6a, (q15_t)0xbf41, (q15_t)0x6e67, (q15_t)0xbf3b,
+  (q15_t)0x6e63, (q15_t)0xbf36, (q15_t)0x6e60, (q15_t)0xbf30, (q15_t)0x6e5d, (q15_t)0xbf2b, (q15_t)0x6e5a, (q15_t)0xbf26,
+  (q15_t)0x6e57, (q15_t)0xbf20, (q15_t)0x6e53, (q15_t)0xbf1b, (q15_t)0x6e50, (q15_t)0xbf15, (q15_t)0x6e4d, (q15_t)0xbf10,
+  (q15_t)0x6e4a, (q15_t)0xbf0a, (q15_t)0x6e47, (q15_t)0xbf05, (q15_t)0x6e44, (q15_t)0xbf00, (q15_t)0x6e40, (q15_t)0xbefa,
+  (q15_t)0x6e3d, (q15_t)0xbef5, (q15_t)0x6e3a, (q15_t)0xbeef, (q15_t)0x6e37, (q15_t)0xbeea, (q15_t)0x6e34, (q15_t)0xbee5,
+  (q15_t)0x6e30, (q15_t)0xbedf, (q15_t)0x6e2d, (q15_t)0xbeda, (q15_t)0x6e2a, (q15_t)0xbed4, (q15_t)0x6e27, (q15_t)0xbecf,
+  (q15_t)0x6e24, (q15_t)0xbeca, (q15_t)0x6e20, (q15_t)0xbec4, (q15_t)0x6e1d, (q15_t)0xbebf, (q15_t)0x6e1a, (q15_t)0xbeb9,
+  (q15_t)0x6e17, (q15_t)0xbeb4, (q15_t)0x6e14, (q15_t)0xbeae, (q15_t)0x6e10, (q15_t)0xbea9, (q15_t)0x6e0d, (q15_t)0xbea4,
+  (q15_t)0x6e0a, (q15_t)0xbe9e, (q15_t)0x6e07, (q15_t)0xbe99, (q15_t)0x6e04, (q15_t)0xbe93, (q15_t)0x6e00, (q15_t)0xbe8e,
+  (q15_t)0x6dfd, (q15_t)0xbe89, (q15_t)0x6dfa, (q15_t)0xbe83, (q15_t)0x6df7, (q15_t)0xbe7e, (q15_t)0x6df3, (q15_t)0xbe78,
+  (q15_t)0x6df0, (q15_t)0xbe73, (q15_t)0x6ded, (q15_t)0xbe6e, (q15_t)0x6dea, (q15_t)0xbe68, (q15_t)0x6de7, (q15_t)0xbe63,
+  (q15_t)0x6de3, (q15_t)0xbe5e, (q15_t)0x6de0, (q15_t)0xbe58, (q15_t)0x6ddd, (q15_t)0xbe53, (q15_t)0x6dda, (q15_t)0xbe4d,
+  (q15_t)0x6dd6, (q15_t)0xbe48, (q15_t)0x6dd3, (q15_t)0xbe43, (q15_t)0x6dd0, (q15_t)0xbe3d, (q15_t)0x6dcd, (q15_t)0xbe38,
+  (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6dc6, (q15_t)0xbe2d, (q15_t)0x6dc3, (q15_t)0xbe28, (q15_t)0x6dc0, (q15_t)0xbe22,
+  (q15_t)0x6dbd, (q15_t)0xbe1d, (q15_t)0x6db9, (q15_t)0xbe17, (q15_t)0x6db6, (q15_t)0xbe12, (q15_t)0x6db3, (q15_t)0xbe0d,
+  (q15_t)0x6db0, (q15_t)0xbe07, (q15_t)0x6dac, (q15_t)0xbe02, (q15_t)0x6da9, (q15_t)0xbdfd, (q15_t)0x6da6, (q15_t)0xbdf7,
+  (q15_t)0x6da3, (q15_t)0xbdf2, (q15_t)0x6d9f, (q15_t)0xbdec, (q15_t)0x6d9c, (q15_t)0xbde7, (q15_t)0x6d99, (q15_t)0xbde2,
+  (q15_t)0x6d96, (q15_t)0xbddc, (q15_t)0x6d92, (q15_t)0xbdd7, (q15_t)0x6d8f, (q15_t)0xbdd1, (q15_t)0x6d8c, (q15_t)0xbdcc,
+  (q15_t)0x6d89, (q15_t)0xbdc7, (q15_t)0x6d85, (q15_t)0xbdc1, (q15_t)0x6d82, (q15_t)0xbdbc, (q15_t)0x6d7f, (q15_t)0xbdb7,
+  (q15_t)0x6d7c, (q15_t)0xbdb1, (q15_t)0x6d78, (q15_t)0xbdac, (q15_t)0x6d75, (q15_t)0xbda6, (q15_t)0x6d72, (q15_t)0xbda1,
+  (q15_t)0x6d6f, (q15_t)0xbd9c, (q15_t)0x6d6b, (q15_t)0xbd96, (q15_t)0x6d68, (q15_t)0xbd91, (q15_t)0x6d65, (q15_t)0xbd8c,
+  (q15_t)0x6d62, (q15_t)0xbd86, (q15_t)0x6d5e, (q15_t)0xbd81, (q15_t)0x6d5b, (q15_t)0xbd7c, (q15_t)0x6d58, (q15_t)0xbd76,
+  (q15_t)0x6d55, (q15_t)0xbd71, (q15_t)0x6d51, (q15_t)0xbd6b, (q15_t)0x6d4e, (q15_t)0xbd66, (q15_t)0x6d4b, (q15_t)0xbd61,
+  (q15_t)0x6d48, (q15_t)0xbd5b, (q15_t)0x6d44, (q15_t)0xbd56, (q15_t)0x6d41, (q15_t)0xbd51, (q15_t)0x6d3e, (q15_t)0xbd4b,
+  (q15_t)0x6d3a, (q15_t)0xbd46, (q15_t)0x6d37, (q15_t)0xbd40, (q15_t)0x6d34, (q15_t)0xbd3b, (q15_t)0x6d31, (q15_t)0xbd36,
+  (q15_t)0x6d2d, (q15_t)0xbd30, (q15_t)0x6d2a, (q15_t)0xbd2b, (q15_t)0x6d27, (q15_t)0xbd26, (q15_t)0x6d23, (q15_t)0xbd20,
+  (q15_t)0x6d20, (q15_t)0xbd1b, (q15_t)0x6d1d, (q15_t)0xbd16, (q15_t)0x6d1a, (q15_t)0xbd10, (q15_t)0x6d16, (q15_t)0xbd0b,
+  (q15_t)0x6d13, (q15_t)0xbd06, (q15_t)0x6d10, (q15_t)0xbd00, (q15_t)0x6d0c, (q15_t)0xbcfb, (q15_t)0x6d09, (q15_t)0xbcf5,
+  (q15_t)0x6d06, (q15_t)0xbcf0, (q15_t)0x6d03, (q15_t)0xbceb, (q15_t)0x6cff, (q15_t)0xbce5, (q15_t)0x6cfc, (q15_t)0xbce0,
+  (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6cf5, (q15_t)0xbcd5, (q15_t)0x6cf2, (q15_t)0xbcd0, (q15_t)0x6cef, (q15_t)0xbccb,
+  (q15_t)0x6cec, (q15_t)0xbcc5, (q15_t)0x6ce8, (q15_t)0xbcc0, (q15_t)0x6ce5, (q15_t)0xbcbb, (q15_t)0x6ce2, (q15_t)0xbcb5,
+  (q15_t)0x6cde, (q15_t)0xbcb0, (q15_t)0x6cdb, (q15_t)0xbcab, (q15_t)0x6cd8, (q15_t)0xbca5, (q15_t)0x6cd4, (q15_t)0xbca0,
+  (q15_t)0x6cd1, (q15_t)0xbc9b, (q15_t)0x6cce, (q15_t)0xbc95, (q15_t)0x6cca, (q15_t)0xbc90, (q15_t)0x6cc7, (q15_t)0xbc8b,
+  (q15_t)0x6cc4, (q15_t)0xbc85, (q15_t)0x6cc1, (q15_t)0xbc80, (q15_t)0x6cbd, (q15_t)0xbc7b, (q15_t)0x6cba, (q15_t)0xbc75,
+  (q15_t)0x6cb7, (q15_t)0xbc70, (q15_t)0x6cb3, (q15_t)0xbc6b, (q15_t)0x6cb0, (q15_t)0xbc65, (q15_t)0x6cad, (q15_t)0xbc60,
+  (q15_t)0x6ca9, (q15_t)0xbc5b, (q15_t)0x6ca6, (q15_t)0xbc55, (q15_t)0x6ca3, (q15_t)0xbc50, (q15_t)0x6c9f, (q15_t)0xbc4b,
+  (q15_t)0x6c9c, (q15_t)0xbc45, (q15_t)0x6c99, (q15_t)0xbc40, (q15_t)0x6c95, (q15_t)0xbc3b, (q15_t)0x6c92, (q15_t)0xbc35,
+  (q15_t)0x6c8f, (q15_t)0xbc30, (q15_t)0x6c8b, (q15_t)0xbc2b, (q15_t)0x6c88, (q15_t)0xbc25, (q15_t)0x6c85, (q15_t)0xbc20,
+  (q15_t)0x6c81, (q15_t)0xbc1b, (q15_t)0x6c7e, (q15_t)0xbc15, (q15_t)0x6c7b, (q15_t)0xbc10, (q15_t)0x6c77, (q15_t)0xbc0b,
+  (q15_t)0x6c74, (q15_t)0xbc05, (q15_t)0x6c71, (q15_t)0xbc00, (q15_t)0x6c6d, (q15_t)0xbbfb, (q15_t)0x6c6a, (q15_t)0xbbf5,
+  (q15_t)0x6c67, (q15_t)0xbbf0, (q15_t)0x6c63, (q15_t)0xbbeb, (q15_t)0x6c60, (q15_t)0xbbe5, (q15_t)0x6c5d, (q15_t)0xbbe0,
+  (q15_t)0x6c59, (q15_t)0xbbdb, (q15_t)0x6c56, (q15_t)0xbbd5, (q15_t)0x6c53, (q15_t)0xbbd0, (q15_t)0x6c4f, (q15_t)0xbbcb,
+  (q15_t)0x6c4c, (q15_t)0xbbc5, (q15_t)0x6c49, (q15_t)0xbbc0, (q15_t)0x6c45, (q15_t)0xbbbb, (q15_t)0x6c42, (q15_t)0xbbb5,
+  (q15_t)0x6c3f, (q15_t)0xbbb0, (q15_t)0x6c3b, (q15_t)0xbbab, (q15_t)0x6c38, (q15_t)0xbba6, (q15_t)0x6c34, (q15_t)0xbba0,
+  (q15_t)0x6c31, (q15_t)0xbb9b, (q15_t)0x6c2e, (q15_t)0xbb96, (q15_t)0x6c2a, (q15_t)0xbb90, (q15_t)0x6c27, (q15_t)0xbb8b,
+  (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6c20, (q15_t)0xbb80, (q15_t)0x6c1d, (q15_t)0xbb7b, (q15_t)0x6c1a, (q15_t)0xbb76,
+  (q15_t)0x6c16, (q15_t)0xbb70, (q15_t)0x6c13, (q15_t)0xbb6b, (q15_t)0x6c0f, (q15_t)0xbb66, (q15_t)0x6c0c, (q15_t)0xbb61,
+  (q15_t)0x6c09, (q15_t)0xbb5b, (q15_t)0x6c05, (q15_t)0xbb56, (q15_t)0x6c02, (q15_t)0xbb51, (q15_t)0x6bff, (q15_t)0xbb4b,
+  (q15_t)0x6bfb, (q15_t)0xbb46, (q15_t)0x6bf8, (q15_t)0xbb41, (q15_t)0x6bf5, (q15_t)0xbb3b, (q15_t)0x6bf1, (q15_t)0xbb36,
+  (q15_t)0x6bee, (q15_t)0xbb31, (q15_t)0x6bea, (q15_t)0xbb2c, (q15_t)0x6be7, (q15_t)0xbb26, (q15_t)0x6be4, (q15_t)0xbb21,
+  (q15_t)0x6be0, (q15_t)0xbb1c, (q15_t)0x6bdd, (q15_t)0xbb16, (q15_t)0x6bd9, (q15_t)0xbb11, (q15_t)0x6bd6, (q15_t)0xbb0c,
+  (q15_t)0x6bd3, (q15_t)0xbb06, (q15_t)0x6bcf, (q15_t)0xbb01, (q15_t)0x6bcc, (q15_t)0xbafc, (q15_t)0x6bc9, (q15_t)0xbaf7,
+  (q15_t)0x6bc5, (q15_t)0xbaf1, (q15_t)0x6bc2, (q15_t)0xbaec, (q15_t)0x6bbe, (q15_t)0xbae7, (q15_t)0x6bbb, (q15_t)0xbae1,
+  (q15_t)0x6bb8, (q15_t)0xbadc, (q15_t)0x6bb4, (q15_t)0xbad7, (q15_t)0x6bb1, (q15_t)0xbad2, (q15_t)0x6bad, (q15_t)0xbacc,
+  (q15_t)0x6baa, (q15_t)0xbac7, (q15_t)0x6ba7, (q15_t)0xbac2, (q15_t)0x6ba3, (q15_t)0xbabc, (q15_t)0x6ba0, (q15_t)0xbab7,
+  (q15_t)0x6b9c, (q15_t)0xbab2, (q15_t)0x6b99, (q15_t)0xbaad, (q15_t)0x6b96, (q15_t)0xbaa7, (q15_t)0x6b92, (q15_t)0xbaa2,
+  (q15_t)0x6b8f, (q15_t)0xba9d, (q15_t)0x6b8b, (q15_t)0xba97, (q15_t)0x6b88, (q15_t)0xba92, (q15_t)0x6b85, (q15_t)0xba8d,
+  (q15_t)0x6b81, (q15_t)0xba88, (q15_t)0x6b7e, (q15_t)0xba82, (q15_t)0x6b7a, (q15_t)0xba7d, (q15_t)0x6b77, (q15_t)0xba78,
+  (q15_t)0x6b73, (q15_t)0xba73, (q15_t)0x6b70, (q15_t)0xba6d, (q15_t)0x6b6d, (q15_t)0xba68, (q15_t)0x6b69, (q15_t)0xba63,
+  (q15_t)0x6b66, (q15_t)0xba5d, (q15_t)0x6b62, (q15_t)0xba58, (q15_t)0x6b5f, (q15_t)0xba53, (q15_t)0x6b5c, (q15_t)0xba4e,
+  (q15_t)0x6b58, (q15_t)0xba48, (q15_t)0x6b55, (q15_t)0xba43, (q15_t)0x6b51, (q15_t)0xba3e, (q15_t)0x6b4e, (q15_t)0xba39,
+  (q15_t)0x6b4a, (q15_t)0xba33, (q15_t)0x6b47, (q15_t)0xba2e, (q15_t)0x6b44, (q15_t)0xba29, (q15_t)0x6b40, (q15_t)0xba23,
+  (q15_t)0x6b3d, (q15_t)0xba1e, (q15_t)0x6b39, (q15_t)0xba19, (q15_t)0x6b36, (q15_t)0xba14, (q15_t)0x6b32, (q15_t)0xba0e,
+  (q15_t)0x6b2f, (q15_t)0xba09, (q15_t)0x6b2c, (q15_t)0xba04, (q15_t)0x6b28, (q15_t)0xb9ff, (q15_t)0x6b25, (q15_t)0xb9f9,
+  (q15_t)0x6b21, (q15_t)0xb9f4, (q15_t)0x6b1e, (q15_t)0xb9ef, (q15_t)0x6b1a, (q15_t)0xb9ea, (q15_t)0x6b17, (q15_t)0xb9e4,
+  (q15_t)0x6b13, (q15_t)0xb9df, (q15_t)0x6b10, (q15_t)0xb9da, (q15_t)0x6b0d, (q15_t)0xb9d5, (q15_t)0x6b09, (q15_t)0xb9cf,
+  (q15_t)0x6b06, (q15_t)0xb9ca, (q15_t)0x6b02, (q15_t)0xb9c5, (q15_t)0x6aff, (q15_t)0xb9c0, (q15_t)0x6afb, (q15_t)0xb9ba,
+  (q15_t)0x6af8, (q15_t)0xb9b5, (q15_t)0x6af4, (q15_t)0xb9b0, (q15_t)0x6af1, (q15_t)0xb9ab, (q15_t)0x6aee, (q15_t)0xb9a5,
+  (q15_t)0x6aea, (q15_t)0xb9a0, (q15_t)0x6ae7, (q15_t)0xb99b, (q15_t)0x6ae3, (q15_t)0xb996, (q15_t)0x6ae0, (q15_t)0xb990,
+  (q15_t)0x6adc, (q15_t)0xb98b, (q15_t)0x6ad9, (q15_t)0xb986, (q15_t)0x6ad5, (q15_t)0xb981, (q15_t)0x6ad2, (q15_t)0xb97b,
+  (q15_t)0x6ace, (q15_t)0xb976, (q15_t)0x6acb, (q15_t)0xb971, (q15_t)0x6ac8, (q15_t)0xb96c, (q15_t)0x6ac4, (q15_t)0xb966,
+  (q15_t)0x6ac1, (q15_t)0xb961, (q15_t)0x6abd, (q15_t)0xb95c, (q15_t)0x6aba, (q15_t)0xb957, (q15_t)0x6ab6, (q15_t)0xb951,
+  (q15_t)0x6ab3, (q15_t)0xb94c, (q15_t)0x6aaf, (q15_t)0xb947, (q15_t)0x6aac, (q15_t)0xb942, (q15_t)0x6aa8, (q15_t)0xb93c,
+  (q15_t)0x6aa5, (q15_t)0xb937, (q15_t)0x6aa1, (q15_t)0xb932, (q15_t)0x6a9e, (q15_t)0xb92d, (q15_t)0x6a9a, (q15_t)0xb928,
+  (q15_t)0x6a97, (q15_t)0xb922, (q15_t)0x6a93, (q15_t)0xb91d, (q15_t)0x6a90, (q15_t)0xb918, (q15_t)0x6a8c, (q15_t)0xb913,
+  (q15_t)0x6a89, (q15_t)0xb90d, (q15_t)0x6a86, (q15_t)0xb908, (q15_t)0x6a82, (q15_t)0xb903, (q15_t)0x6a7f, (q15_t)0xb8fe,
+  (q15_t)0x6a7b, (q15_t)0xb8f8, (q15_t)0x6a78, (q15_t)0xb8f3, (q15_t)0x6a74, (q15_t)0xb8ee, (q15_t)0x6a71, (q15_t)0xb8e9,
+  (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x6a6a, (q15_t)0xb8de, (q15_t)0x6a66, (q15_t)0xb8d9, (q15_t)0x6a63, (q15_t)0xb8d4,
+  (q15_t)0x6a5f, (q15_t)0xb8cf, (q15_t)0x6a5c, (q15_t)0xb8c9, (q15_t)0x6a58, (q15_t)0xb8c4, (q15_t)0x6a55, (q15_t)0xb8bf,
+  (q15_t)0x6a51, (q15_t)0xb8ba, (q15_t)0x6a4e, (q15_t)0xb8b5, (q15_t)0x6a4a, (q15_t)0xb8af, (q15_t)0x6a47, (q15_t)0xb8aa,
+  (q15_t)0x6a43, (q15_t)0xb8a5, (q15_t)0x6a40, (q15_t)0xb8a0, (q15_t)0x6a3c, (q15_t)0xb89b, (q15_t)0x6a39, (q15_t)0xb895,
+  (q15_t)0x6a35, (q15_t)0xb890, (q15_t)0x6a32, (q15_t)0xb88b, (q15_t)0x6a2e, (q15_t)0xb886, (q15_t)0x6a2b, (q15_t)0xb880,
+  (q15_t)0x6a27, (q15_t)0xb87b, (q15_t)0x6a24, (q15_t)0xb876, (q15_t)0x6a20, (q15_t)0xb871, (q15_t)0x6a1d, (q15_t)0xb86c,
+  (q15_t)0x6a19, (q15_t)0xb866, (q15_t)0x6a16, (q15_t)0xb861, (q15_t)0x6a12, (q15_t)0xb85c, (q15_t)0x6a0e, (q15_t)0xb857,
+  (q15_t)0x6a0b, (q15_t)0xb852, (q15_t)0x6a07, (q15_t)0xb84c, (q15_t)0x6a04, (q15_t)0xb847, (q15_t)0x6a00, (q15_t)0xb842,
+  (q15_t)0x69fd, (q15_t)0xb83d, (q15_t)0x69f9, (q15_t)0xb838, (q15_t)0x69f6, (q15_t)0xb832, (q15_t)0x69f2, (q15_t)0xb82d,
+  (q15_t)0x69ef, (q15_t)0xb828, (q15_t)0x69eb, (q15_t)0xb823, (q15_t)0x69e8, (q15_t)0xb81e, (q15_t)0x69e4, (q15_t)0xb818,
+  (q15_t)0x69e1, (q15_t)0xb813, (q15_t)0x69dd, (q15_t)0xb80e, (q15_t)0x69da, (q15_t)0xb809, (q15_t)0x69d6, (q15_t)0xb804,
+  (q15_t)0x69d3, (q15_t)0xb7fe, (q15_t)0x69cf, (q15_t)0xb7f9, (q15_t)0x69cb, (q15_t)0xb7f4, (q15_t)0x69c8, (q15_t)0xb7ef,
+  (q15_t)0x69c4, (q15_t)0xb7ea, (q15_t)0x69c1, (q15_t)0xb7e4, (q15_t)0x69bd, (q15_t)0xb7df, (q15_t)0x69ba, (q15_t)0xb7da,
+  (q15_t)0x69b6, (q15_t)0xb7d5, (q15_t)0x69b3, (q15_t)0xb7d0, (q15_t)0x69af, (q15_t)0xb7ca, (q15_t)0x69ac, (q15_t)0xb7c5,
+  (q15_t)0x69a8, (q15_t)0xb7c0, (q15_t)0x69a5, (q15_t)0xb7bb, (q15_t)0x69a1, (q15_t)0xb7b6, (q15_t)0x699d, (q15_t)0xb7b1,
+  (q15_t)0x699a, (q15_t)0xb7ab, (q15_t)0x6996, (q15_t)0xb7a6, (q15_t)0x6993, (q15_t)0xb7a1, (q15_t)0x698f, (q15_t)0xb79c,
+  (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x6988, (q15_t)0xb791, (q15_t)0x6985, (q15_t)0xb78c, (q15_t)0x6981, (q15_t)0xb787,
+  (q15_t)0x697d, (q15_t)0xb782, (q15_t)0x697a, (q15_t)0xb77d, (q15_t)0x6976, (q15_t)0xb778, (q15_t)0x6973, (q15_t)0xb772,
+  (q15_t)0x696f, (q15_t)0xb76d, (q15_t)0x696c, (q15_t)0xb768, (q15_t)0x6968, (q15_t)0xb763, (q15_t)0x6964, (q15_t)0xb75e,
+  (q15_t)0x6961, (q15_t)0xb758, (q15_t)0x695d, (q15_t)0xb753, (q15_t)0x695a, (q15_t)0xb74e, (q15_t)0x6956, (q15_t)0xb749,
+  (q15_t)0x6953, (q15_t)0xb744, (q15_t)0x694f, (q15_t)0xb73f, (q15_t)0x694b, (q15_t)0xb739, (q15_t)0x6948, (q15_t)0xb734,
+  (q15_t)0x6944, (q15_t)0xb72f, (q15_t)0x6941, (q15_t)0xb72a, (q15_t)0x693d, (q15_t)0xb725, (q15_t)0x693a, (q15_t)0xb720,
+  (q15_t)0x6936, (q15_t)0xb71a, (q15_t)0x6932, (q15_t)0xb715, (q15_t)0x692f, (q15_t)0xb710, (q15_t)0x692b, (q15_t)0xb70b,
+  (q15_t)0x6928, (q15_t)0xb706, (q15_t)0x6924, (q15_t)0xb701, (q15_t)0x6921, (q15_t)0xb6fb, (q15_t)0x691d, (q15_t)0xb6f6,
+  (q15_t)0x6919, (q15_t)0xb6f1, (q15_t)0x6916, (q15_t)0xb6ec, (q15_t)0x6912, (q15_t)0xb6e7, (q15_t)0x690f, (q15_t)0xb6e2,
+  (q15_t)0x690b, (q15_t)0xb6dd, (q15_t)0x6907, (q15_t)0xb6d7, (q15_t)0x6904, (q15_t)0xb6d2, (q15_t)0x6900, (q15_t)0xb6cd,
+  (q15_t)0x68fd, (q15_t)0xb6c8, (q15_t)0x68f9, (q15_t)0xb6c3, (q15_t)0x68f5, (q15_t)0xb6be, (q15_t)0x68f2, (q15_t)0xb6b8,
+  (q15_t)0x68ee, (q15_t)0xb6b3, (q15_t)0x68eb, (q15_t)0xb6ae, (q15_t)0x68e7, (q15_t)0xb6a9, (q15_t)0x68e3, (q15_t)0xb6a4,
+  (q15_t)0x68e0, (q15_t)0xb69f, (q15_t)0x68dc, (q15_t)0xb69a, (q15_t)0x68d9, (q15_t)0xb694, (q15_t)0x68d5, (q15_t)0xb68f,
+  (q15_t)0x68d1, (q15_t)0xb68a, (q15_t)0x68ce, (q15_t)0xb685, (q15_t)0x68ca, (q15_t)0xb680, (q15_t)0x68c7, (q15_t)0xb67b,
+  (q15_t)0x68c3, (q15_t)0xb676, (q15_t)0x68bf, (q15_t)0xb670, (q15_t)0x68bc, (q15_t)0xb66b, (q15_t)0x68b8, (q15_t)0xb666,
+  (q15_t)0x68b5, (q15_t)0xb661, (q15_t)0x68b1, (q15_t)0xb65c, (q15_t)0x68ad, (q15_t)0xb657, (q15_t)0x68aa, (q15_t)0xb652,
+  (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x68a3, (q15_t)0xb647, (q15_t)0x689f, (q15_t)0xb642, (q15_t)0x689b, (q15_t)0xb63d,
+  (q15_t)0x6898, (q15_t)0xb638, (q15_t)0x6894, (q15_t)0xb633, (q15_t)0x6890, (q15_t)0xb62e, (q15_t)0x688d, (q15_t)0xb628,
+  (q15_t)0x6889, (q15_t)0xb623, (q15_t)0x6886, (q15_t)0xb61e, (q15_t)0x6882, (q15_t)0xb619, (q15_t)0x687e, (q15_t)0xb614,
+  (q15_t)0x687b, (q15_t)0xb60f, (q15_t)0x6877, (q15_t)0xb60a, (q15_t)0x6873, (q15_t)0xb605, (q15_t)0x6870, (q15_t)0xb5ff,
+  (q15_t)0x686c, (q15_t)0xb5fa, (q15_t)0x6868, (q15_t)0xb5f5, (q15_t)0x6865, (q15_t)0xb5f0, (q15_t)0x6861, (q15_t)0xb5eb,
+  (q15_t)0x685e, (q15_t)0xb5e6, (q15_t)0x685a, (q15_t)0xb5e1, (q15_t)0x6856, (q15_t)0xb5dc, (q15_t)0x6853, (q15_t)0xb5d6,
+  (q15_t)0x684f, (q15_t)0xb5d1, (q15_t)0x684b, (q15_t)0xb5cc, (q15_t)0x6848, (q15_t)0xb5c7, (q15_t)0x6844, (q15_t)0xb5c2,
+  (q15_t)0x6840, (q15_t)0xb5bd, (q15_t)0x683d, (q15_t)0xb5b8, (q15_t)0x6839, (q15_t)0xb5b3, (q15_t)0x6835, (q15_t)0xb5ae,
+  (q15_t)0x6832, (q15_t)0xb5a8, (q15_t)0x682e, (q15_t)0xb5a3, (q15_t)0x682b, (q15_t)0xb59e, (q15_t)0x6827, (q15_t)0xb599,
+  (q15_t)0x6823, (q15_t)0xb594, (q15_t)0x6820, (q15_t)0xb58f, (q15_t)0x681c, (q15_t)0xb58a, (q15_t)0x6818, (q15_t)0xb585,
+  (q15_t)0x6815, (q15_t)0xb57f, (q15_t)0x6811, (q15_t)0xb57a, (q15_t)0x680d, (q15_t)0xb575, (q15_t)0x680a, (q15_t)0xb570,
+  (q15_t)0x6806, (q15_t)0xb56b, (q15_t)0x6802, (q15_t)0xb566, (q15_t)0x67ff, (q15_t)0xb561, (q15_t)0x67fb, (q15_t)0xb55c,
+  (q15_t)0x67f7, (q15_t)0xb557, (q15_t)0x67f4, (q15_t)0xb552, (q15_t)0x67f0, (q15_t)0xb54c, (q15_t)0x67ec, (q15_t)0xb547,
+  (q15_t)0x67e9, (q15_t)0xb542, (q15_t)0x67e5, (q15_t)0xb53d, (q15_t)0x67e1, (q15_t)0xb538, (q15_t)0x67de, (q15_t)0xb533,
+  (q15_t)0x67da, (q15_t)0xb52e, (q15_t)0x67d6, (q15_t)0xb529, (q15_t)0x67d3, (q15_t)0xb524, (q15_t)0x67cf, (q15_t)0xb51f,
+  (q15_t)0x67cb, (q15_t)0xb519, (q15_t)0x67c8, (q15_t)0xb514, (q15_t)0x67c4, (q15_t)0xb50f, (q15_t)0x67c0, (q15_t)0xb50a,
+  (q15_t)0x67bd, (q15_t)0xb505, (q15_t)0x67b9, (q15_t)0xb500, (q15_t)0x67b5, (q15_t)0xb4fb, (q15_t)0x67b2, (q15_t)0xb4f6,
+  (q15_t)0x67ae, (q15_t)0xb4f1, (q15_t)0x67aa, (q15_t)0xb4ec, (q15_t)0x67a6, (q15_t)0xb4e7, (q15_t)0x67a3, (q15_t)0xb4e1,
+  (q15_t)0x679f, (q15_t)0xb4dc, (q15_t)0x679b, (q15_t)0xb4d7, (q15_t)0x6798, (q15_t)0xb4d2, (q15_t)0x6794, (q15_t)0xb4cd,
+  (q15_t)0x6790, (q15_t)0xb4c8, (q15_t)0x678d, (q15_t)0xb4c3, (q15_t)0x6789, (q15_t)0xb4be, (q15_t)0x6785, (q15_t)0xb4b9,
+  (q15_t)0x6782, (q15_t)0xb4b4, (q15_t)0x677e, (q15_t)0xb4af, (q15_t)0x677a, (q15_t)0xb4aa, (q15_t)0x6776, (q15_t)0xb4a4,
+  (q15_t)0x6773, (q15_t)0xb49f, (q15_t)0x676f, (q15_t)0xb49a, (q15_t)0x676b, (q15_t)0xb495, (q15_t)0x6768, (q15_t)0xb490,
+  (q15_t)0x6764, (q15_t)0xb48b, (q15_t)0x6760, (q15_t)0xb486, (q15_t)0x675d, (q15_t)0xb481, (q15_t)0x6759, (q15_t)0xb47c,
+  (q15_t)0x6755, (q15_t)0xb477, (q15_t)0x6751, (q15_t)0xb472, (q15_t)0x674e, (q15_t)0xb46d, (q15_t)0x674a, (q15_t)0xb468,
+  (q15_t)0x6746, (q15_t)0xb462, (q15_t)0x6743, (q15_t)0xb45d, (q15_t)0x673f, (q15_t)0xb458, (q15_t)0x673b, (q15_t)0xb453,
+  (q15_t)0x6737, (q15_t)0xb44e, (q15_t)0x6734, (q15_t)0xb449, (q15_t)0x6730, (q15_t)0xb444, (q15_t)0x672c, (q15_t)0xb43f,
+  (q15_t)0x6729, (q15_t)0xb43a, (q15_t)0x6725, (q15_t)0xb435, (q15_t)0x6721, (q15_t)0xb430, (q15_t)0x671d, (q15_t)0xb42b,
+  (q15_t)0x671a, (q15_t)0xb426, (q15_t)0x6716, (q15_t)0xb421, (q15_t)0x6712, (q15_t)0xb41c, (q15_t)0x670e, (q15_t)0xb417,
+  (q15_t)0x670b, (q15_t)0xb411, (q15_t)0x6707, (q15_t)0xb40c, (q15_t)0x6703, (q15_t)0xb407, (q15_t)0x6700, (q15_t)0xb402,
+  (q15_t)0x66fc, (q15_t)0xb3fd, (q15_t)0x66f8, (q15_t)0xb3f8, (q15_t)0x66f4, (q15_t)0xb3f3, (q15_t)0x66f1, (q15_t)0xb3ee,
+  (q15_t)0x66ed, (q15_t)0xb3e9, (q15_t)0x66e9, (q15_t)0xb3e4, (q15_t)0x66e5, (q15_t)0xb3df, (q15_t)0x66e2, (q15_t)0xb3da,
+  (q15_t)0x66de, (q15_t)0xb3d5, (q15_t)0x66da, (q15_t)0xb3d0, (q15_t)0x66d6, (q15_t)0xb3cb, (q15_t)0x66d3, (q15_t)0xb3c6,
+  (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x66cb, (q15_t)0xb3bc, (q15_t)0x66c8, (q15_t)0xb3b7, (q15_t)0x66c4, (q15_t)0xb3b1,
+  (q15_t)0x66c0, (q15_t)0xb3ac, (q15_t)0x66bc, (q15_t)0xb3a7, (q15_t)0x66b9, (q15_t)0xb3a2, (q15_t)0x66b5, (q15_t)0xb39d,
+  (q15_t)0x66b1, (q15_t)0xb398, (q15_t)0x66ad, (q15_t)0xb393, (q15_t)0x66aa, (q15_t)0xb38e, (q15_t)0x66a6, (q15_t)0xb389,
+  (q15_t)0x66a2, (q15_t)0xb384, (q15_t)0x669e, (q15_t)0xb37f, (q15_t)0x669b, (q15_t)0xb37a, (q15_t)0x6697, (q15_t)0xb375,
+  (q15_t)0x6693, (q15_t)0xb370, (q15_t)0x668f, (q15_t)0xb36b, (q15_t)0x668b, (q15_t)0xb366, (q15_t)0x6688, (q15_t)0xb361,
+  (q15_t)0x6684, (q15_t)0xb35c, (q15_t)0x6680, (q15_t)0xb357, (q15_t)0x667c, (q15_t)0xb352, (q15_t)0x6679, (q15_t)0xb34d,
+  (q15_t)0x6675, (q15_t)0xb348, (q15_t)0x6671, (q15_t)0xb343, (q15_t)0x666d, (q15_t)0xb33e, (q15_t)0x666a, (q15_t)0xb339,
+  (q15_t)0x6666, (q15_t)0xb334, (q15_t)0x6662, (q15_t)0xb32f, (q15_t)0x665e, (q15_t)0xb32a, (q15_t)0x665b, (q15_t)0xb325,
+  (q15_t)0x6657, (q15_t)0xb31f, (q15_t)0x6653, (q15_t)0xb31a, (q15_t)0x664f, (q15_t)0xb315, (q15_t)0x664b, (q15_t)0xb310,
+  (q15_t)0x6648, (q15_t)0xb30b, (q15_t)0x6644, (q15_t)0xb306, (q15_t)0x6640, (q15_t)0xb301, (q15_t)0x663c, (q15_t)0xb2fc,
+  (q15_t)0x6639, (q15_t)0xb2f7, (q15_t)0x6635, (q15_t)0xb2f2, (q15_t)0x6631, (q15_t)0xb2ed, (q15_t)0x662d, (q15_t)0xb2e8,
+  (q15_t)0x6629, (q15_t)0xb2e3, (q15_t)0x6626, (q15_t)0xb2de, (q15_t)0x6622, (q15_t)0xb2d9, (q15_t)0x661e, (q15_t)0xb2d4,
+  (q15_t)0x661a, (q15_t)0xb2cf, (q15_t)0x6616, (q15_t)0xb2ca, (q15_t)0x6613, (q15_t)0xb2c5, (q15_t)0x660f, (q15_t)0xb2c0,
+  (q15_t)0x660b, (q15_t)0xb2bb, (q15_t)0x6607, (q15_t)0xb2b6, (q15_t)0x6603, (q15_t)0xb2b1, (q15_t)0x6600, (q15_t)0xb2ac,
+  (q15_t)0x65fc, (q15_t)0xb2a7, (q15_t)0x65f8, (q15_t)0xb2a2, (q15_t)0x65f4, (q15_t)0xb29d, (q15_t)0x65f0, (q15_t)0xb298,
+  (q15_t)0x65ed, (q15_t)0xb293, (q15_t)0x65e9, (q15_t)0xb28e, (q15_t)0x65e5, (q15_t)0xb289, (q15_t)0x65e1, (q15_t)0xb284,
+  (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x65da, (q15_t)0xb27a, (q15_t)0x65d6, (q15_t)0xb275, (q15_t)0x65d2, (q15_t)0xb270,
+  (q15_t)0x65ce, (q15_t)0xb26b, (q15_t)0x65ca, (q15_t)0xb266, (q15_t)0x65c7, (q15_t)0xb261, (q15_t)0x65c3, (q15_t)0xb25c,
+  (q15_t)0x65bf, (q15_t)0xb257, (q15_t)0x65bb, (q15_t)0xb252, (q15_t)0x65b7, (q15_t)0xb24d, (q15_t)0x65b4, (q15_t)0xb248,
+  (q15_t)0x65b0, (q15_t)0xb243, (q15_t)0x65ac, (q15_t)0xb23e, (q15_t)0x65a8, (q15_t)0xb239, (q15_t)0x65a4, (q15_t)0xb234,
+  (q15_t)0x65a0, (q15_t)0xb22f, (q15_t)0x659d, (q15_t)0xb22a, (q15_t)0x6599, (q15_t)0xb225, (q15_t)0x6595, (q15_t)0xb220,
+  (q15_t)0x6591, (q15_t)0xb21b, (q15_t)0x658d, (q15_t)0xb216, (q15_t)0x658a, (q15_t)0xb211, (q15_t)0x6586, (q15_t)0xb20c,
+  (q15_t)0x6582, (q15_t)0xb207, (q15_t)0x657e, (q15_t)0xb202, (q15_t)0x657a, (q15_t)0xb1fd, (q15_t)0x6576, (q15_t)0xb1f8,
+  (q15_t)0x6573, (q15_t)0xb1f3, (q15_t)0x656f, (q15_t)0xb1ee, (q15_t)0x656b, (q15_t)0xb1e9, (q15_t)0x6567, (q15_t)0xb1e4,
+  (q15_t)0x6563, (q15_t)0xb1df, (q15_t)0x655f, (q15_t)0xb1da, (q15_t)0x655c, (q15_t)0xb1d6, (q15_t)0x6558, (q15_t)0xb1d1,
+  (q15_t)0x6554, (q15_t)0xb1cc, (q15_t)0x6550, (q15_t)0xb1c7, (q15_t)0x654c, (q15_t)0xb1c2, (q15_t)0x6548, (q15_t)0xb1bd,
+  (q15_t)0x6545, (q15_t)0xb1b8, (q15_t)0x6541, (q15_t)0xb1b3, (q15_t)0x653d, (q15_t)0xb1ae, (q15_t)0x6539, (q15_t)0xb1a9,
+  (q15_t)0x6535, (q15_t)0xb1a4, (q15_t)0x6531, (q15_t)0xb19f, (q15_t)0x652d, (q15_t)0xb19a, (q15_t)0x652a, (q15_t)0xb195,
+  (q15_t)0x6526, (q15_t)0xb190, (q15_t)0x6522, (q15_t)0xb18b, (q15_t)0x651e, (q15_t)0xb186, (q15_t)0x651a, (q15_t)0xb181,
+  (q15_t)0x6516, (q15_t)0xb17c, (q15_t)0x6513, (q15_t)0xb177, (q15_t)0x650f, (q15_t)0xb172, (q15_t)0x650b, (q15_t)0xb16d,
+  (q15_t)0x6507, (q15_t)0xb168, (q15_t)0x6503, (q15_t)0xb163, (q15_t)0x64ff, (q15_t)0xb15e, (q15_t)0x64fb, (q15_t)0xb159,
+  (q15_t)0x64f7, (q15_t)0xb154, (q15_t)0x64f4, (q15_t)0xb14f, (q15_t)0x64f0, (q15_t)0xb14a, (q15_t)0x64ec, (q15_t)0xb146,
+  (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x64e4, (q15_t)0xb13c, (q15_t)0x64e0, (q15_t)0xb137, (q15_t)0x64dc, (q15_t)0xb132,
+  (q15_t)0x64d9, (q15_t)0xb12d, (q15_t)0x64d5, (q15_t)0xb128, (q15_t)0x64d1, (q15_t)0xb123, (q15_t)0x64cd, (q15_t)0xb11e,
+  (q15_t)0x64c9, (q15_t)0xb119, (q15_t)0x64c5, (q15_t)0xb114, (q15_t)0x64c1, (q15_t)0xb10f, (q15_t)0x64bd, (q15_t)0xb10a,
+  (q15_t)0x64ba, (q15_t)0xb105, (q15_t)0x64b6, (q15_t)0xb100, (q15_t)0x64b2, (q15_t)0xb0fb, (q15_t)0x64ae, (q15_t)0xb0f6,
+  (q15_t)0x64aa, (q15_t)0xb0f1, (q15_t)0x64a6, (q15_t)0xb0ec, (q15_t)0x64a2, (q15_t)0xb0e8, (q15_t)0x649e, (q15_t)0xb0e3,
+  (q15_t)0x649b, (q15_t)0xb0de, (q15_t)0x6497, (q15_t)0xb0d9, (q15_t)0x6493, (q15_t)0xb0d4, (q15_t)0x648f, (q15_t)0xb0cf,
+  (q15_t)0x648b, (q15_t)0xb0ca, (q15_t)0x6487, (q15_t)0xb0c5, (q15_t)0x6483, (q15_t)0xb0c0, (q15_t)0x647f, (q15_t)0xb0bb,
+  (q15_t)0x647b, (q15_t)0xb0b6, (q15_t)0x6478, (q15_t)0xb0b1, (q15_t)0x6474, (q15_t)0xb0ac, (q15_t)0x6470, (q15_t)0xb0a7,
+  (q15_t)0x646c, (q15_t)0xb0a2, (q15_t)0x6468, (q15_t)0xb09e, (q15_t)0x6464, (q15_t)0xb099, (q15_t)0x6460, (q15_t)0xb094,
+  (q15_t)0x645c, (q15_t)0xb08f, (q15_t)0x6458, (q15_t)0xb08a, (q15_t)0x6454, (q15_t)0xb085, (q15_t)0x6451, (q15_t)0xb080,
+  (q15_t)0x644d, (q15_t)0xb07b, (q15_t)0x6449, (q15_t)0xb076, (q15_t)0x6445, (q15_t)0xb071, (q15_t)0x6441, (q15_t)0xb06c,
+  (q15_t)0x643d, (q15_t)0xb067, (q15_t)0x6439, (q15_t)0xb062, (q15_t)0x6435, (q15_t)0xb05e, (q15_t)0x6431, (q15_t)0xb059,
+  (q15_t)0x642d, (q15_t)0xb054, (q15_t)0x6429, (q15_t)0xb04f, (q15_t)0x6426, (q15_t)0xb04a, (q15_t)0x6422, (q15_t)0xb045,
+  (q15_t)0x641e, (q15_t)0xb040, (q15_t)0x641a, (q15_t)0xb03b, (q15_t)0x6416, (q15_t)0xb036, (q15_t)0x6412, (q15_t)0xb031,
+  (q15_t)0x640e, (q15_t)0xb02c, (q15_t)0x640a, (q15_t)0xb027, (q15_t)0x6406, (q15_t)0xb023, (q15_t)0x6402, (q15_t)0xb01e,
+  (q15_t)0x63fe, (q15_t)0xb019, (q15_t)0x63fa, (q15_t)0xb014, (q15_t)0x63f7, (q15_t)0xb00f, (q15_t)0x63f3, (q15_t)0xb00a,
+  (q15_t)0x63ef, (q15_t)0xb005, (q15_t)0x63eb, (q15_t)0xb000, (q15_t)0x63e7, (q15_t)0xaffb, (q15_t)0x63e3, (q15_t)0xaff6,
+  (q15_t)0x63df, (q15_t)0xaff1, (q15_t)0x63db, (q15_t)0xafed, (q15_t)0x63d7, (q15_t)0xafe8, (q15_t)0x63d3, (q15_t)0xafe3,
+  (q15_t)0x63cf, (q15_t)0xafde, (q15_t)0x63cb, (q15_t)0xafd9, (q15_t)0x63c7, (q15_t)0xafd4, (q15_t)0x63c3, (q15_t)0xafcf,
+  (q15_t)0x63c0, (q15_t)0xafca, (q15_t)0x63bc, (q15_t)0xafc5, (q15_t)0x63b8, (q15_t)0xafc1, (q15_t)0x63b4, (q15_t)0xafbc,
+  (q15_t)0x63b0, (q15_t)0xafb7, (q15_t)0x63ac, (q15_t)0xafb2, (q15_t)0x63a8, (q15_t)0xafad, (q15_t)0x63a4, (q15_t)0xafa8,
+  (q15_t)0x63a0, (q15_t)0xafa3, (q15_t)0x639c, (q15_t)0xaf9e, (q15_t)0x6398, (q15_t)0xaf99, (q15_t)0x6394, (q15_t)0xaf94,
+  (q15_t)0x6390, (q15_t)0xaf90, (q15_t)0x638c, (q15_t)0xaf8b, (q15_t)0x6388, (q15_t)0xaf86, (q15_t)0x6384, (q15_t)0xaf81,
+  (q15_t)0x6380, (q15_t)0xaf7c, (q15_t)0x637c, (q15_t)0xaf77, (q15_t)0x6378, (q15_t)0xaf72, (q15_t)0x6375, (q15_t)0xaf6d,
+  (q15_t)0x6371, (q15_t)0xaf69, (q15_t)0x636d, (q15_t)0xaf64, (q15_t)0x6369, (q15_t)0xaf5f, (q15_t)0x6365, (q15_t)0xaf5a,
+  (q15_t)0x6361, (q15_t)0xaf55, (q15_t)0x635d, (q15_t)0xaf50, (q15_t)0x6359, (q15_t)0xaf4b, (q15_t)0x6355, (q15_t)0xaf46,
+  (q15_t)0x6351, (q15_t)0xaf41, (q15_t)0x634d, (q15_t)0xaf3d, (q15_t)0x6349, (q15_t)0xaf38, (q15_t)0x6345, (q15_t)0xaf33,
+  (q15_t)0x6341, (q15_t)0xaf2e, (q15_t)0x633d, (q15_t)0xaf29, (q15_t)0x6339, (q15_t)0xaf24, (q15_t)0x6335, (q15_t)0xaf1f,
+  (q15_t)0x6331, (q15_t)0xaf1b, (q15_t)0x632d, (q15_t)0xaf16, (q15_t)0x6329, (q15_t)0xaf11, (q15_t)0x6325, (q15_t)0xaf0c,
+  (q15_t)0x6321, (q15_t)0xaf07, (q15_t)0x631d, (q15_t)0xaf02, (q15_t)0x6319, (q15_t)0xaefd, (q15_t)0x6315, (q15_t)0xaef8,
+  (q15_t)0x6311, (q15_t)0xaef4, (q15_t)0x630d, (q15_t)0xaeef, (q15_t)0x6309, (q15_t)0xaeea, (q15_t)0x6305, (q15_t)0xaee5,
+  (q15_t)0x6301, (q15_t)0xaee0, (q15_t)0x62fd, (q15_t)0xaedb, (q15_t)0x62f9, (q15_t)0xaed6, (q15_t)0x62f5, (q15_t)0xaed2,
+  (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x62ee, (q15_t)0xaec8, (q15_t)0x62ea, (q15_t)0xaec3, (q15_t)0x62e6, (q15_t)0xaebe,
+  (q15_t)0x62e2, (q15_t)0xaeb9, (q15_t)0x62de, (q15_t)0xaeb4, (q15_t)0x62da, (q15_t)0xaeb0, (q15_t)0x62d6, (q15_t)0xaeab,
+  (q15_t)0x62d2, (q15_t)0xaea6, (q15_t)0x62ce, (q15_t)0xaea1, (q15_t)0x62ca, (q15_t)0xae9c, (q15_t)0x62c6, (q15_t)0xae97,
+  (q15_t)0x62c2, (q15_t)0xae92, (q15_t)0x62be, (q15_t)0xae8e, (q15_t)0x62ba, (q15_t)0xae89, (q15_t)0x62b6, (q15_t)0xae84,
+  (q15_t)0x62b2, (q15_t)0xae7f, (q15_t)0x62ae, (q15_t)0xae7a, (q15_t)0x62aa, (q15_t)0xae75, (q15_t)0x62a6, (q15_t)0xae71,
+  (q15_t)0x62a2, (q15_t)0xae6c, (q15_t)0x629e, (q15_t)0xae67, (q15_t)0x629a, (q15_t)0xae62, (q15_t)0x6296, (q15_t)0xae5d,
+  (q15_t)0x6292, (q15_t)0xae58, (q15_t)0x628e, (q15_t)0xae54, (q15_t)0x628a, (q15_t)0xae4f, (q15_t)0x6286, (q15_t)0xae4a,
+  (q15_t)0x6282, (q15_t)0xae45, (q15_t)0x627e, (q15_t)0xae40, (q15_t)0x627a, (q15_t)0xae3b, (q15_t)0x6275, (q15_t)0xae37,
+  (q15_t)0x6271, (q15_t)0xae32, (q15_t)0x626d, (q15_t)0xae2d, (q15_t)0x6269, (q15_t)0xae28, (q15_t)0x6265, (q15_t)0xae23,
+  (q15_t)0x6261, (q15_t)0xae1e, (q15_t)0x625d, (q15_t)0xae1a, (q15_t)0x6259, (q15_t)0xae15, (q15_t)0x6255, (q15_t)0xae10,
+  (q15_t)0x6251, (q15_t)0xae0b, (q15_t)0x624d, (q15_t)0xae06, (q15_t)0x6249, (q15_t)0xae01, (q15_t)0x6245, (q15_t)0xadfd,
+  (q15_t)0x6241, (q15_t)0xadf8, (q15_t)0x623d, (q15_t)0xadf3, (q15_t)0x6239, (q15_t)0xadee, (q15_t)0x6235, (q15_t)0xade9,
+  (q15_t)0x6231, (q15_t)0xade4, (q15_t)0x622d, (q15_t)0xade0, (q15_t)0x6229, (q15_t)0xaddb, (q15_t)0x6225, (q15_t)0xadd6,
+  (q15_t)0x6221, (q15_t)0xadd1, (q15_t)0x621d, (q15_t)0xadcc, (q15_t)0x6219, (q15_t)0xadc8, (q15_t)0x6215, (q15_t)0xadc3,
+  (q15_t)0x6211, (q15_t)0xadbe, (q15_t)0x620d, (q15_t)0xadb9, (q15_t)0x6209, (q15_t)0xadb4, (q15_t)0x6205, (q15_t)0xadaf,
+  (q15_t)0x6201, (q15_t)0xadab, (q15_t)0x61fd, (q15_t)0xada6, (q15_t)0x61f9, (q15_t)0xada1, (q15_t)0x61f5, (q15_t)0xad9c,
+  (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x61ec, (q15_t)0xad93, (q15_t)0x61e8, (q15_t)0xad8e, (q15_t)0x61e4, (q15_t)0xad89,
+  (q15_t)0x61e0, (q15_t)0xad84, (q15_t)0x61dc, (q15_t)0xad7f, (q15_t)0x61d8, (q15_t)0xad7b, (q15_t)0x61d4, (q15_t)0xad76,
+  (q15_t)0x61d0, (q15_t)0xad71, (q15_t)0x61cc, (q15_t)0xad6c, (q15_t)0x61c8, (q15_t)0xad67, (q15_t)0x61c4, (q15_t)0xad63,
+  (q15_t)0x61c0, (q15_t)0xad5e, (q15_t)0x61bc, (q15_t)0xad59, (q15_t)0x61b8, (q15_t)0xad54, (q15_t)0x61b4, (q15_t)0xad4f,
+  (q15_t)0x61b0, (q15_t)0xad4b, (q15_t)0x61ac, (q15_t)0xad46, (q15_t)0x61a8, (q15_t)0xad41, (q15_t)0x61a3, (q15_t)0xad3c,
+  (q15_t)0x619f, (q15_t)0xad37, (q15_t)0x619b, (q15_t)0xad33, (q15_t)0x6197, (q15_t)0xad2e, (q15_t)0x6193, (q15_t)0xad29,
+  (q15_t)0x618f, (q15_t)0xad24, (q15_t)0x618b, (q15_t)0xad1f, (q15_t)0x6187, (q15_t)0xad1b, (q15_t)0x6183, (q15_t)0xad16,
+  (q15_t)0x617f, (q15_t)0xad11, (q15_t)0x617b, (q15_t)0xad0c, (q15_t)0x6177, (q15_t)0xad08, (q15_t)0x6173, (q15_t)0xad03,
+  (q15_t)0x616f, (q15_t)0xacfe, (q15_t)0x616b, (q15_t)0xacf9, (q15_t)0x6166, (q15_t)0xacf4, (q15_t)0x6162, (q15_t)0xacf0,
+  (q15_t)0x615e, (q15_t)0xaceb, (q15_t)0x615a, (q15_t)0xace6, (q15_t)0x6156, (q15_t)0xace1, (q15_t)0x6152, (q15_t)0xacdd,
+  (q15_t)0x614e, (q15_t)0xacd8, (q15_t)0x614a, (q15_t)0xacd3, (q15_t)0x6146, (q15_t)0xacce, (q15_t)0x6142, (q15_t)0xacc9,
+  (q15_t)0x613e, (q15_t)0xacc5, (q15_t)0x613a, (q15_t)0xacc0, (q15_t)0x6135, (q15_t)0xacbb, (q15_t)0x6131, (q15_t)0xacb6,
+  (q15_t)0x612d, (q15_t)0xacb2, (q15_t)0x6129, (q15_t)0xacad, (q15_t)0x6125, (q15_t)0xaca8, (q15_t)0x6121, (q15_t)0xaca3,
+  (q15_t)0x611d, (q15_t)0xac9e, (q15_t)0x6119, (q15_t)0xac9a, (q15_t)0x6115, (q15_t)0xac95, (q15_t)0x6111, (q15_t)0xac90,
+  (q15_t)0x610d, (q15_t)0xac8b, (q15_t)0x6108, (q15_t)0xac87, (q15_t)0x6104, (q15_t)0xac82, (q15_t)0x6100, (q15_t)0xac7d,
+  (q15_t)0x60fc, (q15_t)0xac78, (q15_t)0x60f8, (q15_t)0xac74, (q15_t)0x60f4, (q15_t)0xac6f, (q15_t)0x60f0, (q15_t)0xac6a,
+  (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x60e8, (q15_t)0xac61, (q15_t)0x60e4, (q15_t)0xac5c, (q15_t)0x60df, (q15_t)0xac57,
+  (q15_t)0x60db, (q15_t)0xac52, (q15_t)0x60d7, (q15_t)0xac4e, (q15_t)0x60d3, (q15_t)0xac49, (q15_t)0x60cf, (q15_t)0xac44,
+  (q15_t)0x60cb, (q15_t)0xac3f, (q15_t)0x60c7, (q15_t)0xac3b, (q15_t)0x60c3, (q15_t)0xac36, (q15_t)0x60bf, (q15_t)0xac31,
+  (q15_t)0x60ba, (q15_t)0xac2c, (q15_t)0x60b6, (q15_t)0xac28, (q15_t)0x60b2, (q15_t)0xac23, (q15_t)0x60ae, (q15_t)0xac1e,
+  (q15_t)0x60aa, (q15_t)0xac19, (q15_t)0x60a6, (q15_t)0xac15, (q15_t)0x60a2, (q15_t)0xac10, (q15_t)0x609e, (q15_t)0xac0b,
+  (q15_t)0x6099, (q15_t)0xac06, (q15_t)0x6095, (q15_t)0xac02, (q15_t)0x6091, (q15_t)0xabfd, (q15_t)0x608d, (q15_t)0xabf8,
+  (q15_t)0x6089, (q15_t)0xabf3, (q15_t)0x6085, (q15_t)0xabef, (q15_t)0x6081, (q15_t)0xabea, (q15_t)0x607d, (q15_t)0xabe5,
+  (q15_t)0x6078, (q15_t)0xabe0, (q15_t)0x6074, (q15_t)0xabdc, (q15_t)0x6070, (q15_t)0xabd7, (q15_t)0x606c, (q15_t)0xabd2,
+  (q15_t)0x6068, (q15_t)0xabcd, (q15_t)0x6064, (q15_t)0xabc9, (q15_t)0x6060, (q15_t)0xabc4, (q15_t)0x605c, (q15_t)0xabbf,
+  (q15_t)0x6057, (q15_t)0xabbb, (q15_t)0x6053, (q15_t)0xabb6, (q15_t)0x604f, (q15_t)0xabb1, (q15_t)0x604b, (q15_t)0xabac,
+  (q15_t)0x6047, (q15_t)0xaba8, (q15_t)0x6043, (q15_t)0xaba3, (q15_t)0x603f, (q15_t)0xab9e, (q15_t)0x603a, (q15_t)0xab99,
+  (q15_t)0x6036, (q15_t)0xab95, (q15_t)0x6032, (q15_t)0xab90, (q15_t)0x602e, (q15_t)0xab8b, (q15_t)0x602a, (q15_t)0xab87,
+  (q15_t)0x6026, (q15_t)0xab82, (q15_t)0x6022, (q15_t)0xab7d, (q15_t)0x601d, (q15_t)0xab78, (q15_t)0x6019, (q15_t)0xab74,
+  (q15_t)0x6015, (q15_t)0xab6f, (q15_t)0x6011, (q15_t)0xab6a, (q15_t)0x600d, (q15_t)0xab66, (q15_t)0x6009, (q15_t)0xab61,
+  (q15_t)0x6004, (q15_t)0xab5c, (q15_t)0x6000, (q15_t)0xab57, (q15_t)0x5ffc, (q15_t)0xab53, (q15_t)0x5ff8, (q15_t)0xab4e,
+  (q15_t)0x5ff4, (q15_t)0xab49, (q15_t)0x5ff0, (q15_t)0xab45, (q15_t)0x5fec, (q15_t)0xab40, (q15_t)0x5fe7, (q15_t)0xab3b,
+  (q15_t)0x5fe3, (q15_t)0xab36, (q15_t)0x5fdf, (q15_t)0xab32, (q15_t)0x5fdb, (q15_t)0xab2d, (q15_t)0x5fd7, (q15_t)0xab28,
+  (q15_t)0x5fd3, (q15_t)0xab24, (q15_t)0x5fce, (q15_t)0xab1f, (q15_t)0x5fca, (q15_t)0xab1a, (q15_t)0x5fc6, (q15_t)0xab16,
+  (q15_t)0x5fc2, (q15_t)0xab11, (q15_t)0x5fbe, (q15_t)0xab0c, (q15_t)0x5fba, (q15_t)0xab07, (q15_t)0x5fb5, (q15_t)0xab03,
+  (q15_t)0x5fb1, (q15_t)0xaafe, (q15_t)0x5fad, (q15_t)0xaaf9, (q15_t)0x5fa9, (q15_t)0xaaf5, (q15_t)0x5fa5, (q15_t)0xaaf0,
+  (q15_t)0x5fa0, (q15_t)0xaaeb, (q15_t)0x5f9c, (q15_t)0xaae7, (q15_t)0x5f98, (q15_t)0xaae2, (q15_t)0x5f94, (q15_t)0xaadd,
+  (q15_t)0x5f90, (q15_t)0xaad8, (q15_t)0x5f8c, (q15_t)0xaad4, (q15_t)0x5f87, (q15_t)0xaacf, (q15_t)0x5f83, (q15_t)0xaaca,
+  (q15_t)0x5f7f, (q15_t)0xaac6, (q15_t)0x5f7b, (q15_t)0xaac1, (q15_t)0x5f77, (q15_t)0xaabc, (q15_t)0x5f72, (q15_t)0xaab8,
+  (q15_t)0x5f6e, (q15_t)0xaab3, (q15_t)0x5f6a, (q15_t)0xaaae, (q15_t)0x5f66, (q15_t)0xaaaa, (q15_t)0x5f62, (q15_t)0xaaa5,
+  (q15_t)0x5f5e, (q15_t)0xaaa0, (q15_t)0x5f59, (q15_t)0xaa9c, (q15_t)0x5f55, (q15_t)0xaa97, (q15_t)0x5f51, (q15_t)0xaa92,
+  (q15_t)0x5f4d, (q15_t)0xaa8e, (q15_t)0x5f49, (q15_t)0xaa89, (q15_t)0x5f44, (q15_t)0xaa84, (q15_t)0x5f40, (q15_t)0xaa7f,
+  (q15_t)0x5f3c, (q15_t)0xaa7b, (q15_t)0x5f38, (q15_t)0xaa76, (q15_t)0x5f34, (q15_t)0xaa71, (q15_t)0x5f2f, (q15_t)0xaa6d,
+  (q15_t)0x5f2b, (q15_t)0xaa68, (q15_t)0x5f27, (q15_t)0xaa63, (q15_t)0x5f23, (q15_t)0xaa5f, (q15_t)0x5f1f, (q15_t)0xaa5a,
+  (q15_t)0x5f1a, (q15_t)0xaa55, (q15_t)0x5f16, (q15_t)0xaa51, (q15_t)0x5f12, (q15_t)0xaa4c, (q15_t)0x5f0e, (q15_t)0xaa47,
+  (q15_t)0x5f0a, (q15_t)0xaa43, (q15_t)0x5f05, (q15_t)0xaa3e, (q15_t)0x5f01, (q15_t)0xaa39, (q15_t)0x5efd, (q15_t)0xaa35,
+  (q15_t)0x5ef9, (q15_t)0xaa30, (q15_t)0x5ef5, (q15_t)0xaa2b, (q15_t)0x5ef0, (q15_t)0xaa27, (q15_t)0x5eec, (q15_t)0xaa22,
+  (q15_t)0x5ee8, (q15_t)0xaa1d, (q15_t)0x5ee4, (q15_t)0xaa19, (q15_t)0x5edf, (q15_t)0xaa14, (q15_t)0x5edb, (q15_t)0xaa10,
+  (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5ed3, (q15_t)0xaa06, (q15_t)0x5ecf, (q15_t)0xaa02, (q15_t)0x5eca, (q15_t)0xa9fd,
+  (q15_t)0x5ec6, (q15_t)0xa9f8, (q15_t)0x5ec2, (q15_t)0xa9f4, (q15_t)0x5ebe, (q15_t)0xa9ef, (q15_t)0x5eb9, (q15_t)0xa9ea,
+  (q15_t)0x5eb5, (q15_t)0xa9e6, (q15_t)0x5eb1, (q15_t)0xa9e1, (q15_t)0x5ead, (q15_t)0xa9dc, (q15_t)0x5ea9, (q15_t)0xa9d8,
+  (q15_t)0x5ea4, (q15_t)0xa9d3, (q15_t)0x5ea0, (q15_t)0xa9ce, (q15_t)0x5e9c, (q15_t)0xa9ca, (q15_t)0x5e98, (q15_t)0xa9c5,
+  (q15_t)0x5e93, (q15_t)0xa9c0, (q15_t)0x5e8f, (q15_t)0xa9bc, (q15_t)0x5e8b, (q15_t)0xa9b7, (q15_t)0x5e87, (q15_t)0xa9b3,
+  (q15_t)0x5e82, (q15_t)0xa9ae, (q15_t)0x5e7e, (q15_t)0xa9a9, (q15_t)0x5e7a, (q15_t)0xa9a5, (q15_t)0x5e76, (q15_t)0xa9a0,
+  (q15_t)0x5e71, (q15_t)0xa99b, (q15_t)0x5e6d, (q15_t)0xa997, (q15_t)0x5e69, (q15_t)0xa992, (q15_t)0x5e65, (q15_t)0xa98d,
+  (q15_t)0x5e60, (q15_t)0xa989, (q15_t)0x5e5c, (q15_t)0xa984, (q15_t)0x5e58, (q15_t)0xa980, (q15_t)0x5e54, (q15_t)0xa97b,
+  (q15_t)0x5e50, (q15_t)0xa976, (q15_t)0x5e4b, (q15_t)0xa972, (q15_t)0x5e47, (q15_t)0xa96d, (q15_t)0x5e43, (q15_t)0xa968,
+  (q15_t)0x5e3f, (q15_t)0xa964, (q15_t)0x5e3a, (q15_t)0xa95f, (q15_t)0x5e36, (q15_t)0xa95b, (q15_t)0x5e32, (q15_t)0xa956,
+  (q15_t)0x5e2d, (q15_t)0xa951, (q15_t)0x5e29, (q15_t)0xa94d, (q15_t)0x5e25, (q15_t)0xa948, (q15_t)0x5e21, (q15_t)0xa943,
+  (q15_t)0x5e1c, (q15_t)0xa93f, (q15_t)0x5e18, (q15_t)0xa93a, (q15_t)0x5e14, (q15_t)0xa936, (q15_t)0x5e10, (q15_t)0xa931,
+  (q15_t)0x5e0b, (q15_t)0xa92c, (q15_t)0x5e07, (q15_t)0xa928, (q15_t)0x5e03, (q15_t)0xa923, (q15_t)0x5dff, (q15_t)0xa91e,
+  (q15_t)0x5dfa, (q15_t)0xa91a, (q15_t)0x5df6, (q15_t)0xa915, (q15_t)0x5df2, (q15_t)0xa911, (q15_t)0x5dee, (q15_t)0xa90c,
+  (q15_t)0x5de9, (q15_t)0xa907, (q15_t)0x5de5, (q15_t)0xa903, (q15_t)0x5de1, (q15_t)0xa8fe, (q15_t)0x5ddc, (q15_t)0xa8fa,
+  (q15_t)0x5dd8, (q15_t)0xa8f5, (q15_t)0x5dd4, (q15_t)0xa8f0, (q15_t)0x5dd0, (q15_t)0xa8ec, (q15_t)0x5dcb, (q15_t)0xa8e7,
+  (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5dc3, (q15_t)0xa8de, (q15_t)0x5dbf, (q15_t)0xa8d9, (q15_t)0x5dba, (q15_t)0xa8d5,
+  (q15_t)0x5db6, (q15_t)0xa8d0, (q15_t)0x5db2, (q15_t)0xa8cc, (q15_t)0x5dad, (q15_t)0xa8c7, (q15_t)0x5da9, (q15_t)0xa8c2,
+  (q15_t)0x5da5, (q15_t)0xa8be, (q15_t)0x5da1, (q15_t)0xa8b9, (q15_t)0x5d9c, (q15_t)0xa8b5, (q15_t)0x5d98, (q15_t)0xa8b0,
+  (q15_t)0x5d94, (q15_t)0xa8ab, (q15_t)0x5d8f, (q15_t)0xa8a7, (q15_t)0x5d8b, (q15_t)0xa8a2, (q15_t)0x5d87, (q15_t)0xa89e,
+  (q15_t)0x5d83, (q15_t)0xa899, (q15_t)0x5d7e, (q15_t)0xa894, (q15_t)0x5d7a, (q15_t)0xa890, (q15_t)0x5d76, (q15_t)0xa88b,
+  (q15_t)0x5d71, (q15_t)0xa887, (q15_t)0x5d6d, (q15_t)0xa882, (q15_t)0x5d69, (q15_t)0xa87d, (q15_t)0x5d65, (q15_t)0xa879,
+  (q15_t)0x5d60, (q15_t)0xa874, (q15_t)0x5d5c, (q15_t)0xa870, (q15_t)0x5d58, (q15_t)0xa86b, (q15_t)0x5d53, (q15_t)0xa867,
+  (q15_t)0x5d4f, (q15_t)0xa862, (q15_t)0x5d4b, (q15_t)0xa85d, (q15_t)0x5d46, (q15_t)0xa859, (q15_t)0x5d42, (q15_t)0xa854,
+  (q15_t)0x5d3e, (q15_t)0xa850, (q15_t)0x5d3a, (q15_t)0xa84b, (q15_t)0x5d35, (q15_t)0xa847, (q15_t)0x5d31, (q15_t)0xa842,
+  (q15_t)0x5d2d, (q15_t)0xa83d, (q15_t)0x5d28, (q15_t)0xa839, (q15_t)0x5d24, (q15_t)0xa834, (q15_t)0x5d20, (q15_t)0xa830,
+  (q15_t)0x5d1b, (q15_t)0xa82b, (q15_t)0x5d17, (q15_t)0xa827, (q15_t)0x5d13, (q15_t)0xa822, (q15_t)0x5d0e, (q15_t)0xa81d,
+  (q15_t)0x5d0a, (q15_t)0xa819, (q15_t)0x5d06, (q15_t)0xa814, (q15_t)0x5d01, (q15_t)0xa810, (q15_t)0x5cfd, (q15_t)0xa80b,
+  (q15_t)0x5cf9, (q15_t)0xa807, (q15_t)0x5cf5, (q15_t)0xa802, (q15_t)0x5cf0, (q15_t)0xa7fd, (q15_t)0x5cec, (q15_t)0xa7f9,
+  (q15_t)0x5ce8, (q15_t)0xa7f4, (q15_t)0x5ce3, (q15_t)0xa7f0, (q15_t)0x5cdf, (q15_t)0xa7eb, (q15_t)0x5cdb, (q15_t)0xa7e7,
+  (q15_t)0x5cd6, (q15_t)0xa7e2, (q15_t)0x5cd2, (q15_t)0xa7de, (q15_t)0x5cce, (q15_t)0xa7d9, (q15_t)0x5cc9, (q15_t)0xa7d4,
+  (q15_t)0x5cc5, (q15_t)0xa7d0, (q15_t)0x5cc1, (q15_t)0xa7cb, (q15_t)0x5cbc, (q15_t)0xa7c7, (q15_t)0x5cb8, (q15_t)0xa7c2,
+  (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5caf, (q15_t)0xa7b9, (q15_t)0x5cab, (q15_t)0xa7b5, (q15_t)0x5ca7, (q15_t)0xa7b0,
+  (q15_t)0x5ca2, (q15_t)0xa7ab, (q15_t)0x5c9e, (q15_t)0xa7a7, (q15_t)0x5c9a, (q15_t)0xa7a2, (q15_t)0x5c95, (q15_t)0xa79e,
+  (q15_t)0x5c91, (q15_t)0xa799, (q15_t)0x5c8d, (q15_t)0xa795, (q15_t)0x5c88, (q15_t)0xa790, (q15_t)0x5c84, (q15_t)0xa78c,
+  (q15_t)0x5c80, (q15_t)0xa787, (q15_t)0x5c7b, (q15_t)0xa783, (q15_t)0x5c77, (q15_t)0xa77e, (q15_t)0x5c73, (q15_t)0xa779,
+  (q15_t)0x5c6e, (q15_t)0xa775, (q15_t)0x5c6a, (q15_t)0xa770, (q15_t)0x5c66, (q15_t)0xa76c, (q15_t)0x5c61, (q15_t)0xa767,
+  (q15_t)0x5c5d, (q15_t)0xa763, (q15_t)0x5c58, (q15_t)0xa75e, (q15_t)0x5c54, (q15_t)0xa75a, (q15_t)0x5c50, (q15_t)0xa755,
+  (q15_t)0x5c4b, (q15_t)0xa751, (q15_t)0x5c47, (q15_t)0xa74c, (q15_t)0x5c43, (q15_t)0xa748, (q15_t)0x5c3e, (q15_t)0xa743,
+  (q15_t)0x5c3a, (q15_t)0xa73f, (q15_t)0x5c36, (q15_t)0xa73a, (q15_t)0x5c31, (q15_t)0xa735, (q15_t)0x5c2d, (q15_t)0xa731,
+  (q15_t)0x5c29, (q15_t)0xa72c, (q15_t)0x5c24, (q15_t)0xa728, (q15_t)0x5c20, (q15_t)0xa723, (q15_t)0x5c1b, (q15_t)0xa71f,
+  (q15_t)0x5c17, (q15_t)0xa71a, (q15_t)0x5c13, (q15_t)0xa716, (q15_t)0x5c0e, (q15_t)0xa711, (q15_t)0x5c0a, (q15_t)0xa70d,
+  (q15_t)0x5c06, (q15_t)0xa708, (q15_t)0x5c01, (q15_t)0xa704, (q15_t)0x5bfd, (q15_t)0xa6ff, (q15_t)0x5bf9, (q15_t)0xa6fb,
+  (q15_t)0x5bf4, (q15_t)0xa6f6, (q15_t)0x5bf0, (q15_t)0xa6f2, (q15_t)0x5beb, (q15_t)0xa6ed, (q15_t)0x5be7, (q15_t)0xa6e9,
+  (q15_t)0x5be3, (q15_t)0xa6e4, (q15_t)0x5bde, (q15_t)0xa6e0, (q15_t)0x5bda, (q15_t)0xa6db, (q15_t)0x5bd6, (q15_t)0xa6d7,
+  (q15_t)0x5bd1, (q15_t)0xa6d2, (q15_t)0x5bcd, (q15_t)0xa6ce, (q15_t)0x5bc8, (q15_t)0xa6c9, (q15_t)0x5bc4, (q15_t)0xa6c5,
+  (q15_t)0x5bc0, (q15_t)0xa6c0, (q15_t)0x5bbb, (q15_t)0xa6bc, (q15_t)0x5bb7, (q15_t)0xa6b7, (q15_t)0x5bb2, (q15_t)0xa6b3,
+  (q15_t)0x5bae, (q15_t)0xa6ae, (q15_t)0x5baa, (q15_t)0xa6aa, (q15_t)0x5ba5, (q15_t)0xa6a5, (q15_t)0x5ba1, (q15_t)0xa6a1,
+  (q15_t)0x5b9d, (q15_t)0xa69c, (q15_t)0x5b98, (q15_t)0xa698, (q15_t)0x5b94, (q15_t)0xa693, (q15_t)0x5b8f, (q15_t)0xa68f,
+  (q15_t)0x5b8b, (q15_t)0xa68a, (q15_t)0x5b87, (q15_t)0xa686, (q15_t)0x5b82, (q15_t)0xa681, (q15_t)0x5b7e, (q15_t)0xa67d,
+  (q15_t)0x5b79, (q15_t)0xa678, (q15_t)0x5b75, (q15_t)0xa674, (q15_t)0x5b71, (q15_t)0xa66f, (q15_t)0x5b6c, (q15_t)0xa66b,
+  (q15_t)0x5b68, (q15_t)0xa666, (q15_t)0x5b63, (q15_t)0xa662, (q15_t)0x5b5f, (q15_t)0xa65d, (q15_t)0x5b5b, (q15_t)0xa659,
+  (q15_t)0x5b56, (q15_t)0xa654, (q15_t)0x5b52, (q15_t)0xa650, (q15_t)0x5b4d, (q15_t)0xa64b, (q15_t)0x5b49, (q15_t)0xa647,
+  (q15_t)0x5b45, (q15_t)0xa642, (q15_t)0x5b40, (q15_t)0xa63e, (q15_t)0x5b3c, (q15_t)0xa639, (q15_t)0x5b37, (q15_t)0xa635,
+  (q15_t)0x5b33, (q15_t)0xa630, (q15_t)0x5b2f, (q15_t)0xa62c, (q15_t)0x5b2a, (q15_t)0xa627, (q15_t)0x5b26, (q15_t)0xa623,
+  (q15_t)0x5b21, (q15_t)0xa61f, (q15_t)0x5b1d, (q15_t)0xa61a, (q15_t)0x5b19, (q15_t)0xa616, (q15_t)0x5b14, (q15_t)0xa611,
+  (q15_t)0x5b10, (q15_t)0xa60d, (q15_t)0x5b0b, (q15_t)0xa608, (q15_t)0x5b07, (q15_t)0xa604, (q15_t)0x5b02, (q15_t)0xa5ff,
+  (q15_t)0x5afe, (q15_t)0xa5fb, (q15_t)0x5afa, (q15_t)0xa5f6, (q15_t)0x5af5, (q15_t)0xa5f2, (q15_t)0x5af1, (q15_t)0xa5ed,
+  (q15_t)0x5aec, (q15_t)0xa5e9, (q15_t)0x5ae8, (q15_t)0xa5e4, (q15_t)0x5ae4, (q15_t)0xa5e0, (q15_t)0x5adf, (q15_t)0xa5dc,
+  (q15_t)0x5adb, (q15_t)0xa5d7, (q15_t)0x5ad6, (q15_t)0xa5d3, (q15_t)0x5ad2, (q15_t)0xa5ce, (q15_t)0x5acd, (q15_t)0xa5ca,
+  (q15_t)0x5ac9, (q15_t)0xa5c5, (q15_t)0x5ac5, (q15_t)0xa5c1, (q15_t)0x5ac0, (q15_t)0xa5bc, (q15_t)0x5abc, (q15_t)0xa5b8,
+  (q15_t)0x5ab7, (q15_t)0xa5b3, (q15_t)0x5ab3, (q15_t)0xa5af, (q15_t)0x5aae, (q15_t)0xa5aa, (q15_t)0x5aaa, (q15_t)0xa5a6,
+  (q15_t)0x5aa5, (q15_t)0xa5a2, (q15_t)0x5aa1, (q15_t)0xa59d, (q15_t)0x5a9d, (q15_t)0xa599, (q15_t)0x5a98, (q15_t)0xa594,
+  (q15_t)0x5a94, (q15_t)0xa590, (q15_t)0x5a8f, (q15_t)0xa58b, (q15_t)0x5a8b, (q15_t)0xa587, (q15_t)0x5a86, (q15_t)0xa582,
+  (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5a7e, (q15_t)0xa57a, (q15_t)0x5a79, (q15_t)0xa575, (q15_t)0x5a75, (q15_t)0xa571,
+  (q15_t)0x5a70, (q15_t)0xa56c, (q15_t)0x5a6c, (q15_t)0xa568, (q15_t)0x5a67, (q15_t)0xa563, (q15_t)0x5a63, (q15_t)0xa55f,
+  (q15_t)0x5a5e, (q15_t)0xa55b, (q15_t)0x5a5a, (q15_t)0xa556, (q15_t)0x5a56, (q15_t)0xa552, (q15_t)0x5a51, (q15_t)0xa54d,
+  (q15_t)0x5a4d, (q15_t)0xa549, (q15_t)0x5a48, (q15_t)0xa544, (q15_t)0x5a44, (q15_t)0xa540, (q15_t)0x5a3f, (q15_t)0xa53b,
+  (q15_t)0x5a3b, (q15_t)0xa537, (q15_t)0x5a36, (q15_t)0xa533, (q15_t)0x5a32, (q15_t)0xa52e, (q15_t)0x5a2d, (q15_t)0xa52a,
+  (q15_t)0x5a29, (q15_t)0xa525, (q15_t)0x5a24, (q15_t)0xa521, (q15_t)0x5a20, (q15_t)0xa51c, (q15_t)0x5a1c, (q15_t)0xa518,
+  (q15_t)0x5a17, (q15_t)0xa514, (q15_t)0x5a13, (q15_t)0xa50f, (q15_t)0x5a0e, (q15_t)0xa50b, (q15_t)0x5a0a, (q15_t)0xa506,
+  (q15_t)0x5a05, (q15_t)0xa502, (q15_t)0x5a01, (q15_t)0xa4fe, (q15_t)0x59fc, (q15_t)0xa4f9, (q15_t)0x59f8, (q15_t)0xa4f5,
+  (q15_t)0x59f3, (q15_t)0xa4f0, (q15_t)0x59ef, (q15_t)0xa4ec, (q15_t)0x59ea, (q15_t)0xa4e7, (q15_t)0x59e6, (q15_t)0xa4e3,
+  (q15_t)0x59e1, (q15_t)0xa4df, (q15_t)0x59dd, (q15_t)0xa4da, (q15_t)0x59d9, (q15_t)0xa4d6, (q15_t)0x59d4, (q15_t)0xa4d1,
+  (q15_t)0x59d0, (q15_t)0xa4cd, (q15_t)0x59cb, (q15_t)0xa4c9, (q15_t)0x59c7, (q15_t)0xa4c4, (q15_t)0x59c2, (q15_t)0xa4c0,
+  (q15_t)0x59be, (q15_t)0xa4bb, (q15_t)0x59b9, (q15_t)0xa4b7, (q15_t)0x59b5, (q15_t)0xa4b3, (q15_t)0x59b0, (q15_t)0xa4ae,
+  (q15_t)0x59ac, (q15_t)0xa4aa, (q15_t)0x59a7, (q15_t)0xa4a5, (q15_t)0x59a3, (q15_t)0xa4a1, (q15_t)0x599e, (q15_t)0xa49d,
+  (q15_t)0x599a, (q15_t)0xa498, (q15_t)0x5995, (q15_t)0xa494, (q15_t)0x5991, (q15_t)0xa48f, (q15_t)0x598c, (q15_t)0xa48b,
+  (q15_t)0x5988, (q15_t)0xa487, (q15_t)0x5983, (q15_t)0xa482, (q15_t)0x597f, (q15_t)0xa47e, (q15_t)0x597a, (q15_t)0xa479,
+  (q15_t)0x5976, (q15_t)0xa475, (q15_t)0x5971, (q15_t)0xa471, (q15_t)0x596d, (q15_t)0xa46c, (q15_t)0x5968, (q15_t)0xa468,
+  (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x595f, (q15_t)0xa45f, (q15_t)0x595b, (q15_t)0xa45b, (q15_t)0x5956, (q15_t)0xa456,
+  (q15_t)0x5952, (q15_t)0xa452, (q15_t)0x594d, (q15_t)0xa44e, (q15_t)0x5949, (q15_t)0xa449, (q15_t)0x5944, (q15_t)0xa445,
+  (q15_t)0x5940, (q15_t)0xa440, (q15_t)0x593b, (q15_t)0xa43c, (q15_t)0x5937, (q15_t)0xa438, (q15_t)0x5932, (q15_t)0xa433,
+  (q15_t)0x592e, (q15_t)0xa42f, (q15_t)0x5929, (q15_t)0xa42a, (q15_t)0x5925, (q15_t)0xa426, (q15_t)0x5920, (q15_t)0xa422,
+  (q15_t)0x591c, (q15_t)0xa41d, (q15_t)0x5917, (q15_t)0xa419, (q15_t)0x5913, (q15_t)0xa415, (q15_t)0x590e, (q15_t)0xa410,
+  (q15_t)0x590a, (q15_t)0xa40c, (q15_t)0x5905, (q15_t)0xa407, (q15_t)0x5901, (q15_t)0xa403, (q15_t)0x58fc, (q15_t)0xa3ff,
+  (q15_t)0x58f8, (q15_t)0xa3fa, (q15_t)0x58f3, (q15_t)0xa3f6, (q15_t)0x58ef, (q15_t)0xa3f2, (q15_t)0x58ea, (q15_t)0xa3ed,
+  (q15_t)0x58e6, (q15_t)0xa3e9, (q15_t)0x58e1, (q15_t)0xa3e5, (q15_t)0x58dd, (q15_t)0xa3e0, (q15_t)0x58d8, (q15_t)0xa3dc,
+  (q15_t)0x58d4, (q15_t)0xa3d7, (q15_t)0x58cf, (q15_t)0xa3d3, (q15_t)0x58cb, (q15_t)0xa3cf, (q15_t)0x58c6, (q15_t)0xa3ca,
+  (q15_t)0x58c1, (q15_t)0xa3c6, (q15_t)0x58bd, (q15_t)0xa3c2, (q15_t)0x58b8, (q15_t)0xa3bd, (q15_t)0x58b4, (q15_t)0xa3b9,
+  (q15_t)0x58af, (q15_t)0xa3b5, (q15_t)0x58ab, (q15_t)0xa3b0, (q15_t)0x58a6, (q15_t)0xa3ac, (q15_t)0x58a2, (q15_t)0xa3a8,
+  (q15_t)0x589d, (q15_t)0xa3a3, (q15_t)0x5899, (q15_t)0xa39f, (q15_t)0x5894, (q15_t)0xa39a, (q15_t)0x5890, (q15_t)0xa396,
+  (q15_t)0x588b, (q15_t)0xa392, (q15_t)0x5887, (q15_t)0xa38d, (q15_t)0x5882, (q15_t)0xa389, (q15_t)0x587d, (q15_t)0xa385,
+  (q15_t)0x5879, (q15_t)0xa380, (q15_t)0x5874, (q15_t)0xa37c, (q15_t)0x5870, (q15_t)0xa378, (q15_t)0x586b, (q15_t)0xa373,
+  (q15_t)0x5867, (q15_t)0xa36f, (q15_t)0x5862, (q15_t)0xa36b, (q15_t)0x585e, (q15_t)0xa366, (q15_t)0x5859, (q15_t)0xa362,
+  (q15_t)0x5855, (q15_t)0xa35e, (q15_t)0x5850, (q15_t)0xa359, (q15_t)0x584b, (q15_t)0xa355, (q15_t)0x5847, (q15_t)0xa351,
+  (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x583e, (q15_t)0xa348, (q15_t)0x5839, (q15_t)0xa344, (q15_t)0x5835, (q15_t)0xa33f,
+  (q15_t)0x5830, (q15_t)0xa33b, (q15_t)0x582c, (q15_t)0xa337, (q15_t)0x5827, (q15_t)0xa332, (q15_t)0x5822, (q15_t)0xa32e,
+  (q15_t)0x581e, (q15_t)0xa32a, (q15_t)0x5819, (q15_t)0xa325, (q15_t)0x5815, (q15_t)0xa321, (q15_t)0x5810, (q15_t)0xa31d,
+  (q15_t)0x580c, (q15_t)0xa318, (q15_t)0x5807, (q15_t)0xa314, (q15_t)0x5803, (q15_t)0xa310, (q15_t)0x57fe, (q15_t)0xa30b,
+  (q15_t)0x57f9, (q15_t)0xa307, (q15_t)0x57f5, (q15_t)0xa303, (q15_t)0x57f0, (q15_t)0xa2ff, (q15_t)0x57ec, (q15_t)0xa2fa,
+  (q15_t)0x57e7, (q15_t)0xa2f6, (q15_t)0x57e3, (q15_t)0xa2f2, (q15_t)0x57de, (q15_t)0xa2ed, (q15_t)0x57d9, (q15_t)0xa2e9,
+  (q15_t)0x57d5, (q15_t)0xa2e5, (q15_t)0x57d0, (q15_t)0xa2e0, (q15_t)0x57cc, (q15_t)0xa2dc, (q15_t)0x57c7, (q15_t)0xa2d8,
+  (q15_t)0x57c3, (q15_t)0xa2d3, (q15_t)0x57be, (q15_t)0xa2cf, (q15_t)0x57b9, (q15_t)0xa2cb, (q15_t)0x57b5, (q15_t)0xa2c6,
+  (q15_t)0x57b0, (q15_t)0xa2c2, (q15_t)0x57ac, (q15_t)0xa2be, (q15_t)0x57a7, (q15_t)0xa2ba, (q15_t)0x57a3, (q15_t)0xa2b5,
+  (q15_t)0x579e, (q15_t)0xa2b1, (q15_t)0x5799, (q15_t)0xa2ad, (q15_t)0x5795, (q15_t)0xa2a8, (q15_t)0x5790, (q15_t)0xa2a4,
+  (q15_t)0x578c, (q15_t)0xa2a0, (q15_t)0x5787, (q15_t)0xa29b, (q15_t)0x5783, (q15_t)0xa297, (q15_t)0x577e, (q15_t)0xa293,
+  (q15_t)0x5779, (q15_t)0xa28f, (q15_t)0x5775, (q15_t)0xa28a, (q15_t)0x5770, (q15_t)0xa286, (q15_t)0x576c, (q15_t)0xa282,
+  (q15_t)0x5767, (q15_t)0xa27d, (q15_t)0x5762, (q15_t)0xa279, (q15_t)0x575e, (q15_t)0xa275, (q15_t)0x5759, (q15_t)0xa271,
+  (q15_t)0x5755, (q15_t)0xa26c, (q15_t)0x5750, (q15_t)0xa268, (q15_t)0x574b, (q15_t)0xa264, (q15_t)0x5747, (q15_t)0xa25f,
+  (q15_t)0x5742, (q15_t)0xa25b, (q15_t)0x573e, (q15_t)0xa257, (q15_t)0x5739, (q15_t)0xa253, (q15_t)0x5734, (q15_t)0xa24e,
+  (q15_t)0x5730, (q15_t)0xa24a, (q15_t)0x572b, (q15_t)0xa246, (q15_t)0x5727, (q15_t)0xa241, (q15_t)0x5722, (q15_t)0xa23d,
+  (q15_t)0x571d, (q15_t)0xa239, (q15_t)0x5719, (q15_t)0xa235, (q15_t)0x5714, (q15_t)0xa230, (q15_t)0x5710, (q15_t)0xa22c,
+  (q15_t)0x570b, (q15_t)0xa228, (q15_t)0x5706, (q15_t)0xa224, (q15_t)0x5702, (q15_t)0xa21f, (q15_t)0x56fd, (q15_t)0xa21b,
+  (q15_t)0x56f9, (q15_t)0xa217, (q15_t)0x56f4, (q15_t)0xa212, (q15_t)0x56ef, (q15_t)0xa20e, (q15_t)0x56eb, (q15_t)0xa20a,
+  (q15_t)0x56e6, (q15_t)0xa206, (q15_t)0x56e2, (q15_t)0xa201, (q15_t)0x56dd, (q15_t)0xa1fd, (q15_t)0x56d8, (q15_t)0xa1f9,
+  (q15_t)0x56d4, (q15_t)0xa1f5, (q15_t)0x56cf, (q15_t)0xa1f0, (q15_t)0x56ca, (q15_t)0xa1ec, (q15_t)0x56c6, (q15_t)0xa1e8,
+  (q15_t)0x56c1, (q15_t)0xa1e4, (q15_t)0x56bd, (q15_t)0xa1df, (q15_t)0x56b8, (q15_t)0xa1db, (q15_t)0x56b3, (q15_t)0xa1d7,
+  (q15_t)0x56af, (q15_t)0xa1d3, (q15_t)0x56aa, (q15_t)0xa1ce, (q15_t)0x56a5, (q15_t)0xa1ca, (q15_t)0x56a1, (q15_t)0xa1c6,
+  (q15_t)0x569c, (q15_t)0xa1c1, (q15_t)0x5698, (q15_t)0xa1bd, (q15_t)0x5693, (q15_t)0xa1b9, (q15_t)0x568e, (q15_t)0xa1b5,
+  (q15_t)0x568a, (q15_t)0xa1b0, (q15_t)0x5685, (q15_t)0xa1ac, (q15_t)0x5680, (q15_t)0xa1a8, (q15_t)0x567c, (q15_t)0xa1a4,
+  (q15_t)0x5677, (q15_t)0xa1a0, (q15_t)0x5673, (q15_t)0xa19b, (q15_t)0x566e, (q15_t)0xa197, (q15_t)0x5669, (q15_t)0xa193,
+  (q15_t)0x5665, (q15_t)0xa18f, (q15_t)0x5660, (q15_t)0xa18a, (q15_t)0x565b, (q15_t)0xa186, (q15_t)0x5657, (q15_t)0xa182,
+  (q15_t)0x5652, (q15_t)0xa17e, (q15_t)0x564d, (q15_t)0xa179, (q15_t)0x5649, (q15_t)0xa175, (q15_t)0x5644, (q15_t)0xa171,
+  (q15_t)0x5640, (q15_t)0xa16d, (q15_t)0x563b, (q15_t)0xa168, (q15_t)0x5636, (q15_t)0xa164, (q15_t)0x5632, (q15_t)0xa160,
+  (q15_t)0x562d, (q15_t)0xa15c, (q15_t)0x5628, (q15_t)0xa157, (q15_t)0x5624, (q15_t)0xa153, (q15_t)0x561f, (q15_t)0xa14f,
+  (q15_t)0x561a, (q15_t)0xa14b, (q15_t)0x5616, (q15_t)0xa147, (q15_t)0x5611, (q15_t)0xa142, (q15_t)0x560c, (q15_t)0xa13e,
+  (q15_t)0x5608, (q15_t)0xa13a, (q15_t)0x5603, (q15_t)0xa136, (q15_t)0x55fe, (q15_t)0xa131, (q15_t)0x55fa, (q15_t)0xa12d,
+  (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x55f0, (q15_t)0xa125, (q15_t)0x55ec, (q15_t)0xa121, (q15_t)0x55e7, (q15_t)0xa11c,
+  (q15_t)0x55e3, (q15_t)0xa118, (q15_t)0x55de, (q15_t)0xa114, (q15_t)0x55d9, (q15_t)0xa110, (q15_t)0x55d5, (q15_t)0xa10b,
+  (q15_t)0x55d0, (q15_t)0xa107, (q15_t)0x55cb, (q15_t)0xa103, (q15_t)0x55c7, (q15_t)0xa0ff, (q15_t)0x55c2, (q15_t)0xa0fb,
+  (q15_t)0x55bd, (q15_t)0xa0f6, (q15_t)0x55b9, (q15_t)0xa0f2, (q15_t)0x55b4, (q15_t)0xa0ee, (q15_t)0x55af, (q15_t)0xa0ea,
+  (q15_t)0x55ab, (q15_t)0xa0e6, (q15_t)0x55a6, (q15_t)0xa0e1, (q15_t)0x55a1, (q15_t)0xa0dd, (q15_t)0x559d, (q15_t)0xa0d9,
+  (q15_t)0x5598, (q15_t)0xa0d5, (q15_t)0x5593, (q15_t)0xa0d1, (q15_t)0x558f, (q15_t)0xa0cc, (q15_t)0x558a, (q15_t)0xa0c8,
+  (q15_t)0x5585, (q15_t)0xa0c4, (q15_t)0x5581, (q15_t)0xa0c0, (q15_t)0x557c, (q15_t)0xa0bc, (q15_t)0x5577, (q15_t)0xa0b7,
+  (q15_t)0x5572, (q15_t)0xa0b3, (q15_t)0x556e, (q15_t)0xa0af, (q15_t)0x5569, (q15_t)0xa0ab, (q15_t)0x5564, (q15_t)0xa0a7,
+  (q15_t)0x5560, (q15_t)0xa0a2, (q15_t)0x555b, (q15_t)0xa09e, (q15_t)0x5556, (q15_t)0xa09a, (q15_t)0x5552, (q15_t)0xa096,
+  (q15_t)0x554d, (q15_t)0xa092, (q15_t)0x5548, (q15_t)0xa08e, (q15_t)0x5544, (q15_t)0xa089, (q15_t)0x553f, (q15_t)0xa085,
+  (q15_t)0x553a, (q15_t)0xa081, (q15_t)0x5536, (q15_t)0xa07d, (q15_t)0x5531, (q15_t)0xa079, (q15_t)0x552c, (q15_t)0xa074,
+  (q15_t)0x5528, (q15_t)0xa070, (q15_t)0x5523, (q15_t)0xa06c, (q15_t)0x551e, (q15_t)0xa068, (q15_t)0x5519, (q15_t)0xa064,
+  (q15_t)0x5515, (q15_t)0xa060, (q15_t)0x5510, (q15_t)0xa05b, (q15_t)0x550b, (q15_t)0xa057, (q15_t)0x5507, (q15_t)0xa053,
+  (q15_t)0x5502, (q15_t)0xa04f, (q15_t)0x54fd, (q15_t)0xa04b, (q15_t)0x54f9, (q15_t)0xa046, (q15_t)0x54f4, (q15_t)0xa042,
+  (q15_t)0x54ef, (q15_t)0xa03e, (q15_t)0x54ea, (q15_t)0xa03a, (q15_t)0x54e6, (q15_t)0xa036, (q15_t)0x54e1, (q15_t)0xa032,
+  (q15_t)0x54dc, (q15_t)0xa02d, (q15_t)0x54d8, (q15_t)0xa029, (q15_t)0x54d3, (q15_t)0xa025, (q15_t)0x54ce, (q15_t)0xa021,
+  (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x54c5, (q15_t)0xa019, (q15_t)0x54c0, (q15_t)0xa014, (q15_t)0x54bb, (q15_t)0xa010,
+  (q15_t)0x54b7, (q15_t)0xa00c, (q15_t)0x54b2, (q15_t)0xa008, (q15_t)0x54ad, (q15_t)0xa004, (q15_t)0x54a9, (q15_t)0xa000,
+  (q15_t)0x54a4, (q15_t)0x9ffc, (q15_t)0x549f, (q15_t)0x9ff7, (q15_t)0x549a, (q15_t)0x9ff3, (q15_t)0x5496, (q15_t)0x9fef,
+  (q15_t)0x5491, (q15_t)0x9feb, (q15_t)0x548c, (q15_t)0x9fe7, (q15_t)0x5488, (q15_t)0x9fe3, (q15_t)0x5483, (q15_t)0x9fde,
+  (q15_t)0x547e, (q15_t)0x9fda, (q15_t)0x5479, (q15_t)0x9fd6, (q15_t)0x5475, (q15_t)0x9fd2, (q15_t)0x5470, (q15_t)0x9fce,
+  (q15_t)0x546b, (q15_t)0x9fca, (q15_t)0x5467, (q15_t)0x9fc6, (q15_t)0x5462, (q15_t)0x9fc1, (q15_t)0x545d, (q15_t)0x9fbd,
+  (q15_t)0x5458, (q15_t)0x9fb9, (q15_t)0x5454, (q15_t)0x9fb5, (q15_t)0x544f, (q15_t)0x9fb1, (q15_t)0x544a, (q15_t)0x9fad,
+  (q15_t)0x5445, (q15_t)0x9fa9, (q15_t)0x5441, (q15_t)0x9fa4, (q15_t)0x543c, (q15_t)0x9fa0, (q15_t)0x5437, (q15_t)0x9f9c,
+  (q15_t)0x5433, (q15_t)0x9f98, (q15_t)0x542e, (q15_t)0x9f94, (q15_t)0x5429, (q15_t)0x9f90, (q15_t)0x5424, (q15_t)0x9f8c,
+  (q15_t)0x5420, (q15_t)0x9f88, (q15_t)0x541b, (q15_t)0x9f83, (q15_t)0x5416, (q15_t)0x9f7f, (q15_t)0x5411, (q15_t)0x9f7b,
+  (q15_t)0x540d, (q15_t)0x9f77, (q15_t)0x5408, (q15_t)0x9f73, (q15_t)0x5403, (q15_t)0x9f6f, (q15_t)0x53fe, (q15_t)0x9f6b,
+  (q15_t)0x53fa, (q15_t)0x9f67, (q15_t)0x53f5, (q15_t)0x9f62, (q15_t)0x53f0, (q15_t)0x9f5e, (q15_t)0x53eb, (q15_t)0x9f5a,
+  (q15_t)0x53e7, (q15_t)0x9f56, (q15_t)0x53e2, (q15_t)0x9f52, (q15_t)0x53dd, (q15_t)0x9f4e, (q15_t)0x53d8, (q15_t)0x9f4a,
+  (q15_t)0x53d4, (q15_t)0x9f46, (q15_t)0x53cf, (q15_t)0x9f41, (q15_t)0x53ca, (q15_t)0x9f3d, (q15_t)0x53c5, (q15_t)0x9f39,
+  (q15_t)0x53c1, (q15_t)0x9f35, (q15_t)0x53bc, (q15_t)0x9f31, (q15_t)0x53b7, (q15_t)0x9f2d, (q15_t)0x53b2, (q15_t)0x9f29,
+  (q15_t)0x53ae, (q15_t)0x9f25, (q15_t)0x53a9, (q15_t)0x9f21, (q15_t)0x53a4, (q15_t)0x9f1c, (q15_t)0x539f, (q15_t)0x9f18,
+  (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5396, (q15_t)0x9f10, (q15_t)0x5391, (q15_t)0x9f0c, (q15_t)0x538c, (q15_t)0x9f08,
+  (q15_t)0x5388, (q15_t)0x9f04, (q15_t)0x5383, (q15_t)0x9f00, (q15_t)0x537e, (q15_t)0x9efc, (q15_t)0x5379, (q15_t)0x9ef8,
+  (q15_t)0x5375, (q15_t)0x9ef3, (q15_t)0x5370, (q15_t)0x9eef, (q15_t)0x536b, (q15_t)0x9eeb, (q15_t)0x5366, (q15_t)0x9ee7,
+  (q15_t)0x5362, (q15_t)0x9ee3, (q15_t)0x535d, (q15_t)0x9edf, (q15_t)0x5358, (q15_t)0x9edb, (q15_t)0x5353, (q15_t)0x9ed7,
+  (q15_t)0x534e, (q15_t)0x9ed3, (q15_t)0x534a, (q15_t)0x9ecf, (q15_t)0x5345, (q15_t)0x9ecb, (q15_t)0x5340, (q15_t)0x9ec6,
+  (q15_t)0x533b, (q15_t)0x9ec2, (q15_t)0x5337, (q15_t)0x9ebe, (q15_t)0x5332, (q15_t)0x9eba, (q15_t)0x532d, (q15_t)0x9eb6,
+  (q15_t)0x5328, (q15_t)0x9eb2, (q15_t)0x5323, (q15_t)0x9eae, (q15_t)0x531f, (q15_t)0x9eaa, (q15_t)0x531a, (q15_t)0x9ea6,
+  (q15_t)0x5315, (q15_t)0x9ea2, (q15_t)0x5310, (q15_t)0x9e9e, (q15_t)0x530c, (q15_t)0x9e9a, (q15_t)0x5307, (q15_t)0x9e95,
+  (q15_t)0x5302, (q15_t)0x9e91, (q15_t)0x52fd, (q15_t)0x9e8d, (q15_t)0x52f8, (q15_t)0x9e89, (q15_t)0x52f4, (q15_t)0x9e85,
+  (q15_t)0x52ef, (q15_t)0x9e81, (q15_t)0x52ea, (q15_t)0x9e7d, (q15_t)0x52e5, (q15_t)0x9e79, (q15_t)0x52e1, (q15_t)0x9e75,
+  (q15_t)0x52dc, (q15_t)0x9e71, (q15_t)0x52d7, (q15_t)0x9e6d, (q15_t)0x52d2, (q15_t)0x9e69, (q15_t)0x52cd, (q15_t)0x9e65,
+  (q15_t)0x52c9, (q15_t)0x9e61, (q15_t)0x52c4, (q15_t)0x9e5d, (q15_t)0x52bf, (q15_t)0x9e58, (q15_t)0x52ba, (q15_t)0x9e54,
+  (q15_t)0x52b5, (q15_t)0x9e50, (q15_t)0x52b1, (q15_t)0x9e4c, (q15_t)0x52ac, (q15_t)0x9e48, (q15_t)0x52a7, (q15_t)0x9e44,
+  (q15_t)0x52a2, (q15_t)0x9e40, (q15_t)0x529d, (q15_t)0x9e3c, (q15_t)0x5299, (q15_t)0x9e38, (q15_t)0x5294, (q15_t)0x9e34,
+  (q15_t)0x528f, (q15_t)0x9e30, (q15_t)0x528a, (q15_t)0x9e2c, (q15_t)0x5285, (q15_t)0x9e28, (q15_t)0x5281, (q15_t)0x9e24,
+  (q15_t)0x527c, (q15_t)0x9e20, (q15_t)0x5277, (q15_t)0x9e1c, (q15_t)0x5272, (q15_t)0x9e18, (q15_t)0x526d, (q15_t)0x9e14,
+  (q15_t)0x5269, (q15_t)0x9e0f, (q15_t)0x5264, (q15_t)0x9e0b, (q15_t)0x525f, (q15_t)0x9e07, (q15_t)0x525a, (q15_t)0x9e03,
+  (q15_t)0x5255, (q15_t)0x9dff, (q15_t)0x5251, (q15_t)0x9dfb, (q15_t)0x524c, (q15_t)0x9df7, (q15_t)0x5247, (q15_t)0x9df3,
+  (q15_t)0x5242, (q15_t)0x9def, (q15_t)0x523d, (q15_t)0x9deb, (q15_t)0x5238, (q15_t)0x9de7, (q15_t)0x5234, (q15_t)0x9de3,
+  (q15_t)0x522f, (q15_t)0x9ddf, (q15_t)0x522a, (q15_t)0x9ddb, (q15_t)0x5225, (q15_t)0x9dd7, (q15_t)0x5220, (q15_t)0x9dd3,
+  (q15_t)0x521c, (q15_t)0x9dcf, (q15_t)0x5217, (q15_t)0x9dcb, (q15_t)0x5212, (q15_t)0x9dc7, (q15_t)0x520d, (q15_t)0x9dc3,
+  (q15_t)0x5208, (q15_t)0x9dbf, (q15_t)0x5203, (q15_t)0x9dbb, (q15_t)0x51ff, (q15_t)0x9db7, (q15_t)0x51fa, (q15_t)0x9db3,
+  (q15_t)0x51f5, (q15_t)0x9daf, (q15_t)0x51f0, (q15_t)0x9dab, (q15_t)0x51eb, (q15_t)0x9da7, (q15_t)0x51e6, (q15_t)0x9da3,
+  (q15_t)0x51e2, (q15_t)0x9d9f, (q15_t)0x51dd, (q15_t)0x9d9b, (q15_t)0x51d8, (q15_t)0x9d97, (q15_t)0x51d3, (q15_t)0x9d93,
+  (q15_t)0x51ce, (q15_t)0x9d8f, (q15_t)0x51c9, (q15_t)0x9d8b, (q15_t)0x51c5, (q15_t)0x9d86, (q15_t)0x51c0, (q15_t)0x9d82,
+  (q15_t)0x51bb, (q15_t)0x9d7e, (q15_t)0x51b6, (q15_t)0x9d7a, (q15_t)0x51b1, (q15_t)0x9d76, (q15_t)0x51ac, (q15_t)0x9d72,
+  (q15_t)0x51a8, (q15_t)0x9d6e, (q15_t)0x51a3, (q15_t)0x9d6a, (q15_t)0x519e, (q15_t)0x9d66, (q15_t)0x5199, (q15_t)0x9d62,
+  (q15_t)0x5194, (q15_t)0x9d5e, (q15_t)0x518f, (q15_t)0x9d5a, (q15_t)0x518b, (q15_t)0x9d56, (q15_t)0x5186, (q15_t)0x9d52,
+  (q15_t)0x5181, (q15_t)0x9d4e, (q15_t)0x517c, (q15_t)0x9d4a, (q15_t)0x5177, (q15_t)0x9d46, (q15_t)0x5172, (q15_t)0x9d42,
+  (q15_t)0x516e, (q15_t)0x9d3e, (q15_t)0x5169, (q15_t)0x9d3a, (q15_t)0x5164, (q15_t)0x9d36, (q15_t)0x515f, (q15_t)0x9d32,
+  (q15_t)0x515a, (q15_t)0x9d2e, (q15_t)0x5155, (q15_t)0x9d2a, (q15_t)0x5150, (q15_t)0x9d26, (q15_t)0x514c, (q15_t)0x9d22,
+  (q15_t)0x5147, (q15_t)0x9d1e, (q15_t)0x5142, (q15_t)0x9d1a, (q15_t)0x513d, (q15_t)0x9d16, (q15_t)0x5138, (q15_t)0x9d12,
+  (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x512e, (q15_t)0x9d0b, (q15_t)0x512a, (q15_t)0x9d07, (q15_t)0x5125, (q15_t)0x9d03,
+  (q15_t)0x5120, (q15_t)0x9cff, (q15_t)0x511b, (q15_t)0x9cfb, (q15_t)0x5116, (q15_t)0x9cf7, (q15_t)0x5111, (q15_t)0x9cf3,
+  (q15_t)0x510c, (q15_t)0x9cef, (q15_t)0x5108, (q15_t)0x9ceb, (q15_t)0x5103, (q15_t)0x9ce7, (q15_t)0x50fe, (q15_t)0x9ce3,
+  (q15_t)0x50f9, (q15_t)0x9cdf, (q15_t)0x50f4, (q15_t)0x9cdb, (q15_t)0x50ef, (q15_t)0x9cd7, (q15_t)0x50ea, (q15_t)0x9cd3,
+  (q15_t)0x50e5, (q15_t)0x9ccf, (q15_t)0x50e1, (q15_t)0x9ccb, (q15_t)0x50dc, (q15_t)0x9cc7, (q15_t)0x50d7, (q15_t)0x9cc3,
+  (q15_t)0x50d2, (q15_t)0x9cbf, (q15_t)0x50cd, (q15_t)0x9cbb, (q15_t)0x50c8, (q15_t)0x9cb7, (q15_t)0x50c3, (q15_t)0x9cb3,
+  (q15_t)0x50bf, (q15_t)0x9caf, (q15_t)0x50ba, (q15_t)0x9cab, (q15_t)0x50b5, (q15_t)0x9ca7, (q15_t)0x50b0, (q15_t)0x9ca3,
+  (q15_t)0x50ab, (q15_t)0x9c9f, (q15_t)0x50a6, (q15_t)0x9c9b, (q15_t)0x50a1, (q15_t)0x9c97, (q15_t)0x509c, (q15_t)0x9c93,
+  (q15_t)0x5097, (q15_t)0x9c8f, (q15_t)0x5093, (q15_t)0x9c8b, (q15_t)0x508e, (q15_t)0x9c88, (q15_t)0x5089, (q15_t)0x9c84,
+  (q15_t)0x5084, (q15_t)0x9c80, (q15_t)0x507f, (q15_t)0x9c7c, (q15_t)0x507a, (q15_t)0x9c78, (q15_t)0x5075, (q15_t)0x9c74,
+  (q15_t)0x5070, (q15_t)0x9c70, (q15_t)0x506c, (q15_t)0x9c6c, (q15_t)0x5067, (q15_t)0x9c68, (q15_t)0x5062, (q15_t)0x9c64,
+  (q15_t)0x505d, (q15_t)0x9c60, (q15_t)0x5058, (q15_t)0x9c5c, (q15_t)0x5053, (q15_t)0x9c58, (q15_t)0x504e, (q15_t)0x9c54,
+  (q15_t)0x5049, (q15_t)0x9c50, (q15_t)0x5044, (q15_t)0x9c4c, (q15_t)0x503f, (q15_t)0x9c48, (q15_t)0x503b, (q15_t)0x9c44,
+  (q15_t)0x5036, (q15_t)0x9c40, (q15_t)0x5031, (q15_t)0x9c3d, (q15_t)0x502c, (q15_t)0x9c39, (q15_t)0x5027, (q15_t)0x9c35,
+  (q15_t)0x5022, (q15_t)0x9c31, (q15_t)0x501d, (q15_t)0x9c2d, (q15_t)0x5018, (q15_t)0x9c29, (q15_t)0x5013, (q15_t)0x9c25,
+  (q15_t)0x500f, (q15_t)0x9c21, (q15_t)0x500a, (q15_t)0x9c1d, (q15_t)0x5005, (q15_t)0x9c19, (q15_t)0x5000, (q15_t)0x9c15,
+  (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4ff6, (q15_t)0x9c0d, (q15_t)0x4ff1, (q15_t)0x9c09, (q15_t)0x4fec, (q15_t)0x9c06,
+  (q15_t)0x4fe7, (q15_t)0x9c02, (q15_t)0x4fe2, (q15_t)0x9bfe, (q15_t)0x4fdd, (q15_t)0x9bfa, (q15_t)0x4fd9, (q15_t)0x9bf6,
+  (q15_t)0x4fd4, (q15_t)0x9bf2, (q15_t)0x4fcf, (q15_t)0x9bee, (q15_t)0x4fca, (q15_t)0x9bea, (q15_t)0x4fc5, (q15_t)0x9be6,
+  (q15_t)0x4fc0, (q15_t)0x9be2, (q15_t)0x4fbb, (q15_t)0x9bde, (q15_t)0x4fb6, (q15_t)0x9bda, (q15_t)0x4fb1, (q15_t)0x9bd7,
+  (q15_t)0x4fac, (q15_t)0x9bd3, (q15_t)0x4fa7, (q15_t)0x9bcf, (q15_t)0x4fa2, (q15_t)0x9bcb, (q15_t)0x4f9e, (q15_t)0x9bc7,
+  (q15_t)0x4f99, (q15_t)0x9bc3, (q15_t)0x4f94, (q15_t)0x9bbf, (q15_t)0x4f8f, (q15_t)0x9bbb, (q15_t)0x4f8a, (q15_t)0x9bb7,
+  (q15_t)0x4f85, (q15_t)0x9bb3, (q15_t)0x4f80, (q15_t)0x9baf, (q15_t)0x4f7b, (q15_t)0x9bac, (q15_t)0x4f76, (q15_t)0x9ba8,
+  (q15_t)0x4f71, (q15_t)0x9ba4, (q15_t)0x4f6c, (q15_t)0x9ba0, (q15_t)0x4f67, (q15_t)0x9b9c, (q15_t)0x4f62, (q15_t)0x9b98,
+  (q15_t)0x4f5e, (q15_t)0x9b94, (q15_t)0x4f59, (q15_t)0x9b90, (q15_t)0x4f54, (q15_t)0x9b8c, (q15_t)0x4f4f, (q15_t)0x9b88,
+  (q15_t)0x4f4a, (q15_t)0x9b85, (q15_t)0x4f45, (q15_t)0x9b81, (q15_t)0x4f40, (q15_t)0x9b7d, (q15_t)0x4f3b, (q15_t)0x9b79,
+  (q15_t)0x4f36, (q15_t)0x9b75, (q15_t)0x4f31, (q15_t)0x9b71, (q15_t)0x4f2c, (q15_t)0x9b6d, (q15_t)0x4f27, (q15_t)0x9b69,
+  (q15_t)0x4f22, (q15_t)0x9b65, (q15_t)0x4f1d, (q15_t)0x9b62, (q15_t)0x4f18, (q15_t)0x9b5e, (q15_t)0x4f14, (q15_t)0x9b5a,
+  (q15_t)0x4f0f, (q15_t)0x9b56, (q15_t)0x4f0a, (q15_t)0x9b52, (q15_t)0x4f05, (q15_t)0x9b4e, (q15_t)0x4f00, (q15_t)0x9b4a,
+  (q15_t)0x4efb, (q15_t)0x9b46, (q15_t)0x4ef6, (q15_t)0x9b43, (q15_t)0x4ef1, (q15_t)0x9b3f, (q15_t)0x4eec, (q15_t)0x9b3b,
+  (q15_t)0x4ee7, (q15_t)0x9b37, (q15_t)0x4ee2, (q15_t)0x9b33, (q15_t)0x4edd, (q15_t)0x9b2f, (q15_t)0x4ed8, (q15_t)0x9b2b,
+  (q15_t)0x4ed3, (q15_t)0x9b27, (q15_t)0x4ece, (q15_t)0x9b24, (q15_t)0x4ec9, (q15_t)0x9b20, (q15_t)0x4ec4, (q15_t)0x9b1c,
+  (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4eba, (q15_t)0x9b14, (q15_t)0x4eb6, (q15_t)0x9b10, (q15_t)0x4eb1, (q15_t)0x9b0c,
+  (q15_t)0x4eac, (q15_t)0x9b09, (q15_t)0x4ea7, (q15_t)0x9b05, (q15_t)0x4ea2, (q15_t)0x9b01, (q15_t)0x4e9d, (q15_t)0x9afd,
+  (q15_t)0x4e98, (q15_t)0x9af9, (q15_t)0x4e93, (q15_t)0x9af5, (q15_t)0x4e8e, (q15_t)0x9af1, (q15_t)0x4e89, (q15_t)0x9aed,
+  (q15_t)0x4e84, (q15_t)0x9aea, (q15_t)0x4e7f, (q15_t)0x9ae6, (q15_t)0x4e7a, (q15_t)0x9ae2, (q15_t)0x4e75, (q15_t)0x9ade,
+  (q15_t)0x4e70, (q15_t)0x9ada, (q15_t)0x4e6b, (q15_t)0x9ad6, (q15_t)0x4e66, (q15_t)0x9ad3, (q15_t)0x4e61, (q15_t)0x9acf,
+  (q15_t)0x4e5c, (q15_t)0x9acb, (q15_t)0x4e57, (q15_t)0x9ac7, (q15_t)0x4e52, (q15_t)0x9ac3, (q15_t)0x4e4d, (q15_t)0x9abf,
+  (q15_t)0x4e48, (q15_t)0x9abb, (q15_t)0x4e43, (q15_t)0x9ab8, (q15_t)0x4e3e, (q15_t)0x9ab4, (q15_t)0x4e39, (q15_t)0x9ab0,
+  (q15_t)0x4e34, (q15_t)0x9aac, (q15_t)0x4e2f, (q15_t)0x9aa8, (q15_t)0x4e2a, (q15_t)0x9aa4, (q15_t)0x4e26, (q15_t)0x9aa1,
+  (q15_t)0x4e21, (q15_t)0x9a9d, (q15_t)0x4e1c, (q15_t)0x9a99, (q15_t)0x4e17, (q15_t)0x9a95, (q15_t)0x4e12, (q15_t)0x9a91,
+  (q15_t)0x4e0d, (q15_t)0x9a8d, (q15_t)0x4e08, (q15_t)0x9a8a, (q15_t)0x4e03, (q15_t)0x9a86, (q15_t)0x4dfe, (q15_t)0x9a82,
+  (q15_t)0x4df9, (q15_t)0x9a7e, (q15_t)0x4df4, (q15_t)0x9a7a, (q15_t)0x4def, (q15_t)0x9a76, (q15_t)0x4dea, (q15_t)0x9a73,
+  (q15_t)0x4de5, (q15_t)0x9a6f, (q15_t)0x4de0, (q15_t)0x9a6b, (q15_t)0x4ddb, (q15_t)0x9a67, (q15_t)0x4dd6, (q15_t)0x9a63,
+  (q15_t)0x4dd1, (q15_t)0x9a60, (q15_t)0x4dcc, (q15_t)0x9a5c, (q15_t)0x4dc7, (q15_t)0x9a58, (q15_t)0x4dc2, (q15_t)0x9a54,
+  (q15_t)0x4dbd, (q15_t)0x9a50, (q15_t)0x4db8, (q15_t)0x9a4c, (q15_t)0x4db3, (q15_t)0x9a49, (q15_t)0x4dae, (q15_t)0x9a45,
+  (q15_t)0x4da9, (q15_t)0x9a41, (q15_t)0x4da4, (q15_t)0x9a3d, (q15_t)0x4d9f, (q15_t)0x9a39, (q15_t)0x4d9a, (q15_t)0x9a36,
+  (q15_t)0x4d95, (q15_t)0x9a32, (q15_t)0x4d90, (q15_t)0x9a2e, (q15_t)0x4d8b, (q15_t)0x9a2a, (q15_t)0x4d86, (q15_t)0x9a26,
+  (q15_t)0x4d81, (q15_t)0x9a23, (q15_t)0x4d7c, (q15_t)0x9a1f, (q15_t)0x4d77, (q15_t)0x9a1b, (q15_t)0x4d72, (q15_t)0x9a17,
+  (q15_t)0x4d6d, (q15_t)0x9a13, (q15_t)0x4d68, (q15_t)0x9a10, (q15_t)0x4d63, (q15_t)0x9a0c, (q15_t)0x4d5e, (q15_t)0x9a08,
+  (q15_t)0x4d59, (q15_t)0x9a04, (q15_t)0x4d54, (q15_t)0x9a00, (q15_t)0x4d4f, (q15_t)0x99fd, (q15_t)0x4d4a, (q15_t)0x99f9,
+  (q15_t)0x4d45, (q15_t)0x99f5, (q15_t)0x4d40, (q15_t)0x99f1, (q15_t)0x4d3b, (q15_t)0x99ed, (q15_t)0x4d36, (q15_t)0x99ea,
+  (q15_t)0x4d31, (q15_t)0x99e6, (q15_t)0x4d2c, (q15_t)0x99e2, (q15_t)0x4d27, (q15_t)0x99de, (q15_t)0x4d22, (q15_t)0x99da,
+  (q15_t)0x4d1d, (q15_t)0x99d7, (q15_t)0x4d18, (q15_t)0x99d3, (q15_t)0x4d13, (q15_t)0x99cf, (q15_t)0x4d0e, (q15_t)0x99cb,
+  (q15_t)0x4d09, (q15_t)0x99c7, (q15_t)0x4d04, (q15_t)0x99c4, (q15_t)0x4cff, (q15_t)0x99c0, (q15_t)0x4cfa, (q15_t)0x99bc,
+  (q15_t)0x4cf5, (q15_t)0x99b8, (q15_t)0x4cf0, (q15_t)0x99b5, (q15_t)0x4ceb, (q15_t)0x99b1, (q15_t)0x4ce6, (q15_t)0x99ad,
+  (q15_t)0x4ce1, (q15_t)0x99a9, (q15_t)0x4cdb, (q15_t)0x99a5, (q15_t)0x4cd6, (q15_t)0x99a2, (q15_t)0x4cd1, (q15_t)0x999e,
+  (q15_t)0x4ccc, (q15_t)0x999a, (q15_t)0x4cc7, (q15_t)0x9996, (q15_t)0x4cc2, (q15_t)0x9993, (q15_t)0x4cbd, (q15_t)0x998f,
+  (q15_t)0x4cb8, (q15_t)0x998b, (q15_t)0x4cb3, (q15_t)0x9987, (q15_t)0x4cae, (q15_t)0x9984, (q15_t)0x4ca9, (q15_t)0x9980,
+  (q15_t)0x4ca4, (q15_t)0x997c, (q15_t)0x4c9f, (q15_t)0x9978, (q15_t)0x4c9a, (q15_t)0x9975, (q15_t)0x4c95, (q15_t)0x9971,
+  (q15_t)0x4c90, (q15_t)0x996d, (q15_t)0x4c8b, (q15_t)0x9969, (q15_t)0x4c86, (q15_t)0x9965, (q15_t)0x4c81, (q15_t)0x9962,
+  (q15_t)0x4c7c, (q15_t)0x995e, (q15_t)0x4c77, (q15_t)0x995a, (q15_t)0x4c72, (q15_t)0x9956, (q15_t)0x4c6d, (q15_t)0x9953,
+  (q15_t)0x4c68, (q15_t)0x994f, (q15_t)0x4c63, (q15_t)0x994b, (q15_t)0x4c5e, (q15_t)0x9947, (q15_t)0x4c59, (q15_t)0x9944,
+  (q15_t)0x4c54, (q15_t)0x9940, (q15_t)0x4c4f, (q15_t)0x993c, (q15_t)0x4c49, (q15_t)0x9938, (q15_t)0x4c44, (q15_t)0x9935,
+  (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4c3a, (q15_t)0x992d, (q15_t)0x4c35, (q15_t)0x992a, (q15_t)0x4c30, (q15_t)0x9926,
+  (q15_t)0x4c2b, (q15_t)0x9922, (q15_t)0x4c26, (q15_t)0x991e, (q15_t)0x4c21, (q15_t)0x991b, (q15_t)0x4c1c, (q15_t)0x9917,
+  (q15_t)0x4c17, (q15_t)0x9913, (q15_t)0x4c12, (q15_t)0x990f, (q15_t)0x4c0d, (q15_t)0x990c, (q15_t)0x4c08, (q15_t)0x9908,
+  (q15_t)0x4c03, (q15_t)0x9904, (q15_t)0x4bfe, (q15_t)0x9900, (q15_t)0x4bf9, (q15_t)0x98fd, (q15_t)0x4bf4, (q15_t)0x98f9,
+  (q15_t)0x4bef, (q15_t)0x98f5, (q15_t)0x4be9, (q15_t)0x98f2, (q15_t)0x4be4, (q15_t)0x98ee, (q15_t)0x4bdf, (q15_t)0x98ea,
+  (q15_t)0x4bda, (q15_t)0x98e6, (q15_t)0x4bd5, (q15_t)0x98e3, (q15_t)0x4bd0, (q15_t)0x98df, (q15_t)0x4bcb, (q15_t)0x98db,
+  (q15_t)0x4bc6, (q15_t)0x98d7, (q15_t)0x4bc1, (q15_t)0x98d4, (q15_t)0x4bbc, (q15_t)0x98d0, (q15_t)0x4bb7, (q15_t)0x98cc,
+  (q15_t)0x4bb2, (q15_t)0x98c9, (q15_t)0x4bad, (q15_t)0x98c5, (q15_t)0x4ba8, (q15_t)0x98c1, (q15_t)0x4ba3, (q15_t)0x98bd,
+  (q15_t)0x4b9e, (q15_t)0x98ba, (q15_t)0x4b98, (q15_t)0x98b6, (q15_t)0x4b93, (q15_t)0x98b2, (q15_t)0x4b8e, (q15_t)0x98af,
+  (q15_t)0x4b89, (q15_t)0x98ab, (q15_t)0x4b84, (q15_t)0x98a7, (q15_t)0x4b7f, (q15_t)0x98a3, (q15_t)0x4b7a, (q15_t)0x98a0,
+  (q15_t)0x4b75, (q15_t)0x989c, (q15_t)0x4b70, (q15_t)0x9898, (q15_t)0x4b6b, (q15_t)0x9895, (q15_t)0x4b66, (q15_t)0x9891,
+  (q15_t)0x4b61, (q15_t)0x988d, (q15_t)0x4b5c, (q15_t)0x988a, (q15_t)0x4b56, (q15_t)0x9886, (q15_t)0x4b51, (q15_t)0x9882,
+  (q15_t)0x4b4c, (q15_t)0x987e, (q15_t)0x4b47, (q15_t)0x987b, (q15_t)0x4b42, (q15_t)0x9877, (q15_t)0x4b3d, (q15_t)0x9873,
+  (q15_t)0x4b38, (q15_t)0x9870, (q15_t)0x4b33, (q15_t)0x986c, (q15_t)0x4b2e, (q15_t)0x9868, (q15_t)0x4b29, (q15_t)0x9865,
+  (q15_t)0x4b24, (q15_t)0x9861, (q15_t)0x4b1f, (q15_t)0x985d, (q15_t)0x4b19, (q15_t)0x985a, (q15_t)0x4b14, (q15_t)0x9856,
+  (q15_t)0x4b0f, (q15_t)0x9852, (q15_t)0x4b0a, (q15_t)0x984e, (q15_t)0x4b05, (q15_t)0x984b, (q15_t)0x4b00, (q15_t)0x9847,
+  (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x4af6, (q15_t)0x9840, (q15_t)0x4af1, (q15_t)0x983c, (q15_t)0x4aec, (q15_t)0x9838,
+  (q15_t)0x4ae7, (q15_t)0x9835, (q15_t)0x4ae1, (q15_t)0x9831, (q15_t)0x4adc, (q15_t)0x982d, (q15_t)0x4ad7, (q15_t)0x982a,
+  (q15_t)0x4ad2, (q15_t)0x9826, (q15_t)0x4acd, (q15_t)0x9822, (q15_t)0x4ac8, (q15_t)0x981f, (q15_t)0x4ac3, (q15_t)0x981b,
+  (q15_t)0x4abe, (q15_t)0x9817, (q15_t)0x4ab9, (q15_t)0x9814, (q15_t)0x4ab4, (q15_t)0x9810, (q15_t)0x4aae, (q15_t)0x980c,
+  (q15_t)0x4aa9, (q15_t)0x9809, (q15_t)0x4aa4, (q15_t)0x9805, (q15_t)0x4a9f, (q15_t)0x9801, (q15_t)0x4a9a, (q15_t)0x97fe,
+  (q15_t)0x4a95, (q15_t)0x97fa, (q15_t)0x4a90, (q15_t)0x97f6, (q15_t)0x4a8b, (q15_t)0x97f3, (q15_t)0x4a86, (q15_t)0x97ef,
+  (q15_t)0x4a81, (q15_t)0x97eb, (q15_t)0x4a7b, (q15_t)0x97e8, (q15_t)0x4a76, (q15_t)0x97e4, (q15_t)0x4a71, (q15_t)0x97e0,
+  (q15_t)0x4a6c, (q15_t)0x97dd, (q15_t)0x4a67, (q15_t)0x97d9, (q15_t)0x4a62, (q15_t)0x97d5, (q15_t)0x4a5d, (q15_t)0x97d2,
+  (q15_t)0x4a58, (q15_t)0x97ce, (q15_t)0x4a52, (q15_t)0x97cb, (q15_t)0x4a4d, (q15_t)0x97c7, (q15_t)0x4a48, (q15_t)0x97c3,
+  (q15_t)0x4a43, (q15_t)0x97c0, (q15_t)0x4a3e, (q15_t)0x97bc, (q15_t)0x4a39, (q15_t)0x97b8, (q15_t)0x4a34, (q15_t)0x97b5,
+  (q15_t)0x4a2f, (q15_t)0x97b1, (q15_t)0x4a2a, (q15_t)0x97ad, (q15_t)0x4a24, (q15_t)0x97aa, (q15_t)0x4a1f, (q15_t)0x97a6,
+  (q15_t)0x4a1a, (q15_t)0x97a2, (q15_t)0x4a15, (q15_t)0x979f, (q15_t)0x4a10, (q15_t)0x979b, (q15_t)0x4a0b, (q15_t)0x9798,
+  (q15_t)0x4a06, (q15_t)0x9794, (q15_t)0x4a01, (q15_t)0x9790, (q15_t)0x49fb, (q15_t)0x978d, (q15_t)0x49f6, (q15_t)0x9789,
+  (q15_t)0x49f1, (q15_t)0x9785, (q15_t)0x49ec, (q15_t)0x9782, (q15_t)0x49e7, (q15_t)0x977e, (q15_t)0x49e2, (q15_t)0x977a,
+  (q15_t)0x49dd, (q15_t)0x9777, (q15_t)0x49d8, (q15_t)0x9773, (q15_t)0x49d2, (q15_t)0x9770, (q15_t)0x49cd, (q15_t)0x976c,
+  (q15_t)0x49c8, (q15_t)0x9768, (q15_t)0x49c3, (q15_t)0x9765, (q15_t)0x49be, (q15_t)0x9761, (q15_t)0x49b9, (q15_t)0x975d,
+  (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x49ae, (q15_t)0x9756, (q15_t)0x49a9, (q15_t)0x9753, (q15_t)0x49a4, (q15_t)0x974f,
+  (q15_t)0x499f, (q15_t)0x974b, (q15_t)0x499a, (q15_t)0x9748, (q15_t)0x4995, (q15_t)0x9744, (q15_t)0x4990, (q15_t)0x9741,
+  (q15_t)0x498a, (q15_t)0x973d, (q15_t)0x4985, (q15_t)0x9739, (q15_t)0x4980, (q15_t)0x9736, (q15_t)0x497b, (q15_t)0x9732,
+  (q15_t)0x4976, (q15_t)0x972f, (q15_t)0x4971, (q15_t)0x972b, (q15_t)0x496c, (q15_t)0x9727, (q15_t)0x4966, (q15_t)0x9724,
+  (q15_t)0x4961, (q15_t)0x9720, (q15_t)0x495c, (q15_t)0x971d, (q15_t)0x4957, (q15_t)0x9719, (q15_t)0x4952, (q15_t)0x9715,
+  (q15_t)0x494d, (q15_t)0x9712, (q15_t)0x4948, (q15_t)0x970e, (q15_t)0x4942, (q15_t)0x970b, (q15_t)0x493d, (q15_t)0x9707,
+  (q15_t)0x4938, (q15_t)0x9703, (q15_t)0x4933, (q15_t)0x9700, (q15_t)0x492e, (q15_t)0x96fc, (q15_t)0x4929, (q15_t)0x96f9,
+  (q15_t)0x4923, (q15_t)0x96f5, (q15_t)0x491e, (q15_t)0x96f1, (q15_t)0x4919, (q15_t)0x96ee, (q15_t)0x4914, (q15_t)0x96ea,
+  (q15_t)0x490f, (q15_t)0x96e7, (q15_t)0x490a, (q15_t)0x96e3, (q15_t)0x4905, (q15_t)0x96df, (q15_t)0x48ff, (q15_t)0x96dc,
+  (q15_t)0x48fa, (q15_t)0x96d8, (q15_t)0x48f5, (q15_t)0x96d5, (q15_t)0x48f0, (q15_t)0x96d1, (q15_t)0x48eb, (q15_t)0x96ce,
+  (q15_t)0x48e6, (q15_t)0x96ca, (q15_t)0x48e0, (q15_t)0x96c6, (q15_t)0x48db, (q15_t)0x96c3, (q15_t)0x48d6, (q15_t)0x96bf,
+  (q15_t)0x48d1, (q15_t)0x96bc, (q15_t)0x48cc, (q15_t)0x96b8, (q15_t)0x48c7, (q15_t)0x96b5, (q15_t)0x48c1, (q15_t)0x96b1,
+  (q15_t)0x48bc, (q15_t)0x96ad, (q15_t)0x48b7, (q15_t)0x96aa, (q15_t)0x48b2, (q15_t)0x96a6, (q15_t)0x48ad, (q15_t)0x96a3,
+  (q15_t)0x48a8, (q15_t)0x969f, (q15_t)0x48a2, (q15_t)0x969c, (q15_t)0x489d, (q15_t)0x9698, (q15_t)0x4898, (q15_t)0x9694,
+  (q15_t)0x4893, (q15_t)0x9691, (q15_t)0x488e, (q15_t)0x968d, (q15_t)0x4888, (q15_t)0x968a, (q15_t)0x4883, (q15_t)0x9686,
+  (q15_t)0x487e, (q15_t)0x9683, (q15_t)0x4879, (q15_t)0x967f, (q15_t)0x4874, (q15_t)0x967b, (q15_t)0x486f, (q15_t)0x9678,
+  (q15_t)0x4869, (q15_t)0x9674, (q15_t)0x4864, (q15_t)0x9671, (q15_t)0x485f, (q15_t)0x966d, (q15_t)0x485a, (q15_t)0x966a,
+  (q15_t)0x4855, (q15_t)0x9666, (q15_t)0x484f, (q15_t)0x9663, (q15_t)0x484a, (q15_t)0x965f, (q15_t)0x4845, (q15_t)0x965b,
+  (q15_t)0x4840, (q15_t)0x9658, (q15_t)0x483b, (q15_t)0x9654, (q15_t)0x4836, (q15_t)0x9651, (q15_t)0x4830, (q15_t)0x964d,
+  (q15_t)0x482b, (q15_t)0x964a, (q15_t)0x4826, (q15_t)0x9646, (q15_t)0x4821, (q15_t)0x9643, (q15_t)0x481c, (q15_t)0x963f,
+  (q15_t)0x4816, (q15_t)0x963c, (q15_t)0x4811, (q15_t)0x9638, (q15_t)0x480c, (q15_t)0x9635, (q15_t)0x4807, (q15_t)0x9631,
+  (q15_t)0x4802, (q15_t)0x962d, (q15_t)0x47fc, (q15_t)0x962a, (q15_t)0x47f7, (q15_t)0x9626, (q15_t)0x47f2, (q15_t)0x9623,
+  (q15_t)0x47ed, (q15_t)0x961f, (q15_t)0x47e8, (q15_t)0x961c, (q15_t)0x47e2, (q15_t)0x9618, (q15_t)0x47dd, (q15_t)0x9615,
+  (q15_t)0x47d8, (q15_t)0x9611, (q15_t)0x47d3, (q15_t)0x960e, (q15_t)0x47ce, (q15_t)0x960a, (q15_t)0x47c8, (q15_t)0x9607,
+  (q15_t)0x47c3, (q15_t)0x9603, (q15_t)0x47be, (q15_t)0x9600, (q15_t)0x47b9, (q15_t)0x95fc, (q15_t)0x47b4, (q15_t)0x95f9,
+  (q15_t)0x47ae, (q15_t)0x95f5, (q15_t)0x47a9, (q15_t)0x95f2, (q15_t)0x47a4, (q15_t)0x95ee, (q15_t)0x479f, (q15_t)0x95ea,
+  (q15_t)0x479a, (q15_t)0x95e7, (q15_t)0x4794, (q15_t)0x95e3, (q15_t)0x478f, (q15_t)0x95e0, (q15_t)0x478a, (q15_t)0x95dc,
+  (q15_t)0x4785, (q15_t)0x95d9, (q15_t)0x4780, (q15_t)0x95d5, (q15_t)0x477a, (q15_t)0x95d2, (q15_t)0x4775, (q15_t)0x95ce,
+  (q15_t)0x4770, (q15_t)0x95cb, (q15_t)0x476b, (q15_t)0x95c7, (q15_t)0x4765, (q15_t)0x95c4, (q15_t)0x4760, (q15_t)0x95c0,
+  (q15_t)0x475b, (q15_t)0x95bd, (q15_t)0x4756, (q15_t)0x95b9, (q15_t)0x4751, (q15_t)0x95b6, (q15_t)0x474b, (q15_t)0x95b2,
+  (q15_t)0x4746, (q15_t)0x95af, (q15_t)0x4741, (q15_t)0x95ab, (q15_t)0x473c, (q15_t)0x95a8, (q15_t)0x4737, (q15_t)0x95a4,
+  (q15_t)0x4731, (q15_t)0x95a1, (q15_t)0x472c, (q15_t)0x959d, (q15_t)0x4727, (q15_t)0x959a, (q15_t)0x4722, (q15_t)0x9596,
+  (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x4717, (q15_t)0x958f, (q15_t)0x4712, (q15_t)0x958c, (q15_t)0x470d, (q15_t)0x9588,
+  (q15_t)0x4708, (q15_t)0x9585, (q15_t)0x4702, (q15_t)0x9581, (q15_t)0x46fd, (q15_t)0x957e, (q15_t)0x46f8, (q15_t)0x957a,
+  (q15_t)0x46f3, (q15_t)0x9577, (q15_t)0x46ed, (q15_t)0x9574, (q15_t)0x46e8, (q15_t)0x9570, (q15_t)0x46e3, (q15_t)0x956d,
+  (q15_t)0x46de, (q15_t)0x9569, (q15_t)0x46d8, (q15_t)0x9566, (q15_t)0x46d3, (q15_t)0x9562, (q15_t)0x46ce, (q15_t)0x955f,
+  (q15_t)0x46c9, (q15_t)0x955b, (q15_t)0x46c4, (q15_t)0x9558, (q15_t)0x46be, (q15_t)0x9554, (q15_t)0x46b9, (q15_t)0x9551,
+  (q15_t)0x46b4, (q15_t)0x954d, (q15_t)0x46af, (q15_t)0x954a, (q15_t)0x46a9, (q15_t)0x9546, (q15_t)0x46a4, (q15_t)0x9543,
+  (q15_t)0x469f, (q15_t)0x953f, (q15_t)0x469a, (q15_t)0x953c, (q15_t)0x4694, (q15_t)0x9538, (q15_t)0x468f, (q15_t)0x9535,
+  (q15_t)0x468a, (q15_t)0x9532, (q15_t)0x4685, (q15_t)0x952e, (q15_t)0x467f, (q15_t)0x952b, (q15_t)0x467a, (q15_t)0x9527,
+  (q15_t)0x4675, (q15_t)0x9524, (q15_t)0x4670, (q15_t)0x9520, (q15_t)0x466a, (q15_t)0x951d, (q15_t)0x4665, (q15_t)0x9519,
+  (q15_t)0x4660, (q15_t)0x9516, (q15_t)0x465b, (q15_t)0x9512, (q15_t)0x4655, (q15_t)0x950f, (q15_t)0x4650, (q15_t)0x950c,
+  (q15_t)0x464b, (q15_t)0x9508, (q15_t)0x4646, (q15_t)0x9505, (q15_t)0x4640, (q15_t)0x9501, (q15_t)0x463b, (q15_t)0x94fe,
+  (q15_t)0x4636, (q15_t)0x94fa, (q15_t)0x4631, (q15_t)0x94f7, (q15_t)0x462b, (q15_t)0x94f3, (q15_t)0x4626, (q15_t)0x94f0,
+  (q15_t)0x4621, (q15_t)0x94ed, (q15_t)0x461c, (q15_t)0x94e9, (q15_t)0x4616, (q15_t)0x94e6, (q15_t)0x4611, (q15_t)0x94e2,
+  (q15_t)0x460c, (q15_t)0x94df, (q15_t)0x4607, (q15_t)0x94db, (q15_t)0x4601, (q15_t)0x94d8, (q15_t)0x45fc, (q15_t)0x94d4,
+  (q15_t)0x45f7, (q15_t)0x94d1, (q15_t)0x45f2, (q15_t)0x94ce, (q15_t)0x45ec, (q15_t)0x94ca, (q15_t)0x45e7, (q15_t)0x94c7,
+  (q15_t)0x45e2, (q15_t)0x94c3, (q15_t)0x45dd, (q15_t)0x94c0, (q15_t)0x45d7, (q15_t)0x94bc, (q15_t)0x45d2, (q15_t)0x94b9,
+  (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x45c7, (q15_t)0x94b2, (q15_t)0x45c2, (q15_t)0x94af, (q15_t)0x45bd, (q15_t)0x94ab,
+  (q15_t)0x45b8, (q15_t)0x94a8, (q15_t)0x45b2, (q15_t)0x94a4, (q15_t)0x45ad, (q15_t)0x94a1, (q15_t)0x45a8, (q15_t)0x949e,
+  (q15_t)0x45a3, (q15_t)0x949a, (q15_t)0x459d, (q15_t)0x9497, (q15_t)0x4598, (q15_t)0x9493, (q15_t)0x4593, (q15_t)0x9490,
+  (q15_t)0x458d, (q15_t)0x948d, (q15_t)0x4588, (q15_t)0x9489, (q15_t)0x4583, (q15_t)0x9486, (q15_t)0x457e, (q15_t)0x9482,
+  (q15_t)0x4578, (q15_t)0x947f, (q15_t)0x4573, (q15_t)0x947b, (q15_t)0x456e, (q15_t)0x9478, (q15_t)0x4569, (q15_t)0x9475,
+  (q15_t)0x4563, (q15_t)0x9471, (q15_t)0x455e, (q15_t)0x946e, (q15_t)0x4559, (q15_t)0x946a, (q15_t)0x4553, (q15_t)0x9467,
+  (q15_t)0x454e, (q15_t)0x9464, (q15_t)0x4549, (q15_t)0x9460, (q15_t)0x4544, (q15_t)0x945d, (q15_t)0x453e, (q15_t)0x9459,
+  (q15_t)0x4539, (q15_t)0x9456, (q15_t)0x4534, (q15_t)0x9453, (q15_t)0x452e, (q15_t)0x944f, (q15_t)0x4529, (q15_t)0x944c,
+  (q15_t)0x4524, (q15_t)0x9448, (q15_t)0x451f, (q15_t)0x9445, (q15_t)0x4519, (q15_t)0x9442, (q15_t)0x4514, (q15_t)0x943e,
+  (q15_t)0x450f, (q15_t)0x943b, (q15_t)0x4509, (q15_t)0x9437, (q15_t)0x4504, (q15_t)0x9434, (q15_t)0x44ff, (q15_t)0x9431,
+  (q15_t)0x44fa, (q15_t)0x942d, (q15_t)0x44f4, (q15_t)0x942a, (q15_t)0x44ef, (q15_t)0x9427, (q15_t)0x44ea, (q15_t)0x9423,
+  (q15_t)0x44e4, (q15_t)0x9420, (q15_t)0x44df, (q15_t)0x941c, (q15_t)0x44da, (q15_t)0x9419, (q15_t)0x44d4, (q15_t)0x9416,
+  (q15_t)0x44cf, (q15_t)0x9412, (q15_t)0x44ca, (q15_t)0x940f, (q15_t)0x44c5, (q15_t)0x940b, (q15_t)0x44bf, (q15_t)0x9408,
+  (q15_t)0x44ba, (q15_t)0x9405, (q15_t)0x44b5, (q15_t)0x9401, (q15_t)0x44af, (q15_t)0x93fe, (q15_t)0x44aa, (q15_t)0x93fb,
+  (q15_t)0x44a5, (q15_t)0x93f7, (q15_t)0x449f, (q15_t)0x93f4, (q15_t)0x449a, (q15_t)0x93f1, (q15_t)0x4495, (q15_t)0x93ed,
+  (q15_t)0x4490, (q15_t)0x93ea, (q15_t)0x448a, (q15_t)0x93e6, (q15_t)0x4485, (q15_t)0x93e3, (q15_t)0x4480, (q15_t)0x93e0,
+  (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4475, (q15_t)0x93d9, (q15_t)0x4470, (q15_t)0x93d6, (q15_t)0x446a, (q15_t)0x93d2,
+  (q15_t)0x4465, (q15_t)0x93cf, (q15_t)0x4460, (q15_t)0x93cc, (q15_t)0x445a, (q15_t)0x93c8, (q15_t)0x4455, (q15_t)0x93c5,
+  (q15_t)0x4450, (q15_t)0x93c1, (q15_t)0x444b, (q15_t)0x93be, (q15_t)0x4445, (q15_t)0x93bb, (q15_t)0x4440, (q15_t)0x93b7,
+  (q15_t)0x443b, (q15_t)0x93b4, (q15_t)0x4435, (q15_t)0x93b1, (q15_t)0x4430, (q15_t)0x93ad, (q15_t)0x442b, (q15_t)0x93aa,
+  (q15_t)0x4425, (q15_t)0x93a7, (q15_t)0x4420, (q15_t)0x93a3, (q15_t)0x441b, (q15_t)0x93a0, (q15_t)0x4415, (q15_t)0x939d,
+  (q15_t)0x4410, (q15_t)0x9399, (q15_t)0x440b, (q15_t)0x9396, (q15_t)0x4405, (q15_t)0x9393, (q15_t)0x4400, (q15_t)0x938f,
+  (q15_t)0x43fb, (q15_t)0x938c, (q15_t)0x43f5, (q15_t)0x9389, (q15_t)0x43f0, (q15_t)0x9385, (q15_t)0x43eb, (q15_t)0x9382,
+  (q15_t)0x43e5, (q15_t)0x937f, (q15_t)0x43e0, (q15_t)0x937b, (q15_t)0x43db, (q15_t)0x9378, (q15_t)0x43d5, (q15_t)0x9375,
+  (q15_t)0x43d0, (q15_t)0x9371, (q15_t)0x43cb, (q15_t)0x936e, (q15_t)0x43c5, (q15_t)0x936b, (q15_t)0x43c0, (q15_t)0x9367,
+  (q15_t)0x43bb, (q15_t)0x9364, (q15_t)0x43b5, (q15_t)0x9361, (q15_t)0x43b0, (q15_t)0x935d, (q15_t)0x43ab, (q15_t)0x935a,
+  (q15_t)0x43a5, (q15_t)0x9357, (q15_t)0x43a0, (q15_t)0x9353, (q15_t)0x439b, (q15_t)0x9350, (q15_t)0x4395, (q15_t)0x934d,
+  (q15_t)0x4390, (q15_t)0x9349, (q15_t)0x438b, (q15_t)0x9346, (q15_t)0x4385, (q15_t)0x9343, (q15_t)0x4380, (q15_t)0x933f,
+  (q15_t)0x437b, (q15_t)0x933c, (q15_t)0x4375, (q15_t)0x9339, (q15_t)0x4370, (q15_t)0x9336, (q15_t)0x436b, (q15_t)0x9332,
+  (q15_t)0x4365, (q15_t)0x932f, (q15_t)0x4360, (q15_t)0x932c, (q15_t)0x435b, (q15_t)0x9328, (q15_t)0x4355, (q15_t)0x9325,
+  (q15_t)0x4350, (q15_t)0x9322, (q15_t)0x434b, (q15_t)0x931e, (q15_t)0x4345, (q15_t)0x931b, (q15_t)0x4340, (q15_t)0x9318,
+  (q15_t)0x433b, (q15_t)0x9314, (q15_t)0x4335, (q15_t)0x9311, (q15_t)0x4330, (q15_t)0x930e, (q15_t)0x432b, (q15_t)0x930b,
+  (q15_t)0x4325, (q15_t)0x9307, (q15_t)0x4320, (q15_t)0x9304, (q15_t)0x431b, (q15_t)0x9301, (q15_t)0x4315, (q15_t)0x92fd,
+  (q15_t)0x4310, (q15_t)0x92fa, (q15_t)0x430b, (q15_t)0x92f7, (q15_t)0x4305, (q15_t)0x92f4, (q15_t)0x4300, (q15_t)0x92f0,
+  (q15_t)0x42fa, (q15_t)0x92ed, (q15_t)0x42f5, (q15_t)0x92ea, (q15_t)0x42f0, (q15_t)0x92e6, (q15_t)0x42ea, (q15_t)0x92e3,
+  (q15_t)0x42e5, (q15_t)0x92e0, (q15_t)0x42e0, (q15_t)0x92dd, (q15_t)0x42da, (q15_t)0x92d9, (q15_t)0x42d5, (q15_t)0x92d6,
+  (q15_t)0x42d0, (q15_t)0x92d3, (q15_t)0x42ca, (q15_t)0x92cf, (q15_t)0x42c5, (q15_t)0x92cc, (q15_t)0x42c0, (q15_t)0x92c9,
+  (q15_t)0x42ba, (q15_t)0x92c6, (q15_t)0x42b5, (q15_t)0x92c2, (q15_t)0x42af, (q15_t)0x92bf, (q15_t)0x42aa, (q15_t)0x92bc,
+  (q15_t)0x42a5, (q15_t)0x92b8, (q15_t)0x429f, (q15_t)0x92b5, (q15_t)0x429a, (q15_t)0x92b2, (q15_t)0x4295, (q15_t)0x92af,
+  (q15_t)0x428f, (q15_t)0x92ab, (q15_t)0x428a, (q15_t)0x92a8, (q15_t)0x4284, (q15_t)0x92a5, (q15_t)0x427f, (q15_t)0x92a2,
+  (q15_t)0x427a, (q15_t)0x929e, (q15_t)0x4274, (q15_t)0x929b, (q15_t)0x426f, (q15_t)0x9298, (q15_t)0x426a, (q15_t)0x9295,
+  (q15_t)0x4264, (q15_t)0x9291, (q15_t)0x425f, (q15_t)0x928e, (q15_t)0x425a, (q15_t)0x928b, (q15_t)0x4254, (q15_t)0x9288,
+  (q15_t)0x424f, (q15_t)0x9284, (q15_t)0x4249, (q15_t)0x9281, (q15_t)0x4244, (q15_t)0x927e, (q15_t)0x423f, (q15_t)0x927b,
+  (q15_t)0x4239, (q15_t)0x9277, (q15_t)0x4234, (q15_t)0x9274, (q15_t)0x422f, (q15_t)0x9271, (q15_t)0x4229, (q15_t)0x926e,
+  (q15_t)0x4224, (q15_t)0x926a, (q15_t)0x421e, (q15_t)0x9267, (q15_t)0x4219, (q15_t)0x9264, (q15_t)0x4214, (q15_t)0x9261,
+  (q15_t)0x420e, (q15_t)0x925d, (q15_t)0x4209, (q15_t)0x925a, (q15_t)0x4203, (q15_t)0x9257, (q15_t)0x41fe, (q15_t)0x9254,
+  (q15_t)0x41f9, (q15_t)0x9250, (q15_t)0x41f3, (q15_t)0x924d, (q15_t)0x41ee, (q15_t)0x924a, (q15_t)0x41e9, (q15_t)0x9247,
+  (q15_t)0x41e3, (q15_t)0x9243, (q15_t)0x41de, (q15_t)0x9240, (q15_t)0x41d8, (q15_t)0x923d, (q15_t)0x41d3, (q15_t)0x923a,
+  (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x41c8, (q15_t)0x9233, (q15_t)0x41c3, (q15_t)0x9230, (q15_t)0x41bd, (q15_t)0x922d,
+  (q15_t)0x41b8, (q15_t)0x922a, (q15_t)0x41b3, (q15_t)0x9226, (q15_t)0x41ad, (q15_t)0x9223, (q15_t)0x41a8, (q15_t)0x9220,
+  (q15_t)0x41a2, (q15_t)0x921d, (q15_t)0x419d, (q15_t)0x9219, (q15_t)0x4198, (q15_t)0x9216, (q15_t)0x4192, (q15_t)0x9213,
+  (q15_t)0x418d, (q15_t)0x9210, (q15_t)0x4188, (q15_t)0x920d, (q15_t)0x4182, (q15_t)0x9209, (q15_t)0x417d, (q15_t)0x9206,
+  (q15_t)0x4177, (q15_t)0x9203, (q15_t)0x4172, (q15_t)0x9200, (q15_t)0x416d, (q15_t)0x91fc, (q15_t)0x4167, (q15_t)0x91f9,
+  (q15_t)0x4162, (q15_t)0x91f6, (q15_t)0x415c, (q15_t)0x91f3, (q15_t)0x4157, (q15_t)0x91f0, (q15_t)0x4152, (q15_t)0x91ec,
+  (q15_t)0x414c, (q15_t)0x91e9, (q15_t)0x4147, (q15_t)0x91e6, (q15_t)0x4141, (q15_t)0x91e3, (q15_t)0x413c, (q15_t)0x91e0,
+  (q15_t)0x4136, (q15_t)0x91dc, (q15_t)0x4131, (q15_t)0x91d9, (q15_t)0x412c, (q15_t)0x91d6, (q15_t)0x4126, (q15_t)0x91d3,
+  (q15_t)0x4121, (q15_t)0x91d0, (q15_t)0x411b, (q15_t)0x91cc, (q15_t)0x4116, (q15_t)0x91c9, (q15_t)0x4111, (q15_t)0x91c6,
+  (q15_t)0x410b, (q15_t)0x91c3, (q15_t)0x4106, (q15_t)0x91c0, (q15_t)0x4100, (q15_t)0x91bc, (q15_t)0x40fb, (q15_t)0x91b9,
+  (q15_t)0x40f6, (q15_t)0x91b6, (q15_t)0x40f0, (q15_t)0x91b3, (q15_t)0x40eb, (q15_t)0x91b0, (q15_t)0x40e5, (q15_t)0x91ad,
+  (q15_t)0x40e0, (q15_t)0x91a9, (q15_t)0x40da, (q15_t)0x91a6, (q15_t)0x40d5, (q15_t)0x91a3, (q15_t)0x40d0, (q15_t)0x91a0,
+  (q15_t)0x40ca, (q15_t)0x919d, (q15_t)0x40c5, (q15_t)0x9199, (q15_t)0x40bf, (q15_t)0x9196, (q15_t)0x40ba, (q15_t)0x9193,
+  (q15_t)0x40b5, (q15_t)0x9190, (q15_t)0x40af, (q15_t)0x918d, (q15_t)0x40aa, (q15_t)0x918a, (q15_t)0x40a4, (q15_t)0x9186,
+  (q15_t)0x409f, (q15_t)0x9183, (q15_t)0x4099, (q15_t)0x9180, (q15_t)0x4094, (q15_t)0x917d, (q15_t)0x408f, (q15_t)0x917a,
+  (q15_t)0x4089, (q15_t)0x9177, (q15_t)0x4084, (q15_t)0x9173, (q15_t)0x407e, (q15_t)0x9170, (q15_t)0x4079, (q15_t)0x916d,
+  (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x406e, (q15_t)0x9167, (q15_t)0x4069, (q15_t)0x9164, (q15_t)0x4063, (q15_t)0x9160,
+  (q15_t)0x405e, (q15_t)0x915d, (q15_t)0x4058, (q15_t)0x915a, (q15_t)0x4053, (q15_t)0x9157, (q15_t)0x404d, (q15_t)0x9154,
+  (q15_t)0x4048, (q15_t)0x9151, (q15_t)0x4043, (q15_t)0x914d, (q15_t)0x403d, (q15_t)0x914a, (q15_t)0x4038, (q15_t)0x9147,
+  (q15_t)0x4032, (q15_t)0x9144, (q15_t)0x402d, (q15_t)0x9141, (q15_t)0x4027, (q15_t)0x913e, (q15_t)0x4022, (q15_t)0x913a,
+  (q15_t)0x401d, (q15_t)0x9137, (q15_t)0x4017, (q15_t)0x9134, (q15_t)0x4012, (q15_t)0x9131, (q15_t)0x400c, (q15_t)0x912e,
+  (q15_t)0x4007, (q15_t)0x912b, (q15_t)0x4001, (q15_t)0x9128, (q15_t)0x3ffc, (q15_t)0x9124, (q15_t)0x3ff6, (q15_t)0x9121,
+  (q15_t)0x3ff1, (q15_t)0x911e, (q15_t)0x3fec, (q15_t)0x911b, (q15_t)0x3fe6, (q15_t)0x9118, (q15_t)0x3fe1, (q15_t)0x9115,
+  (q15_t)0x3fdb, (q15_t)0x9112, (q15_t)0x3fd6, (q15_t)0x910f, (q15_t)0x3fd0, (q15_t)0x910b, (q15_t)0x3fcb, (q15_t)0x9108,
+  (q15_t)0x3fc5, (q15_t)0x9105, (q15_t)0x3fc0, (q15_t)0x9102, (q15_t)0x3fbb, (q15_t)0x90ff, (q15_t)0x3fb5, (q15_t)0x90fc,
+  (q15_t)0x3fb0, (q15_t)0x90f9, (q15_t)0x3faa, (q15_t)0x90f5, (q15_t)0x3fa5, (q15_t)0x90f2, (q15_t)0x3f9f, (q15_t)0x90ef,
+  (q15_t)0x3f9a, (q15_t)0x90ec, (q15_t)0x3f94, (q15_t)0x90e9, (q15_t)0x3f8f, (q15_t)0x90e6, (q15_t)0x3f89, (q15_t)0x90e3,
+  (q15_t)0x3f84, (q15_t)0x90e0, (q15_t)0x3f7f, (q15_t)0x90dd, (q15_t)0x3f79, (q15_t)0x90d9, (q15_t)0x3f74, (q15_t)0x90d6,
+  (q15_t)0x3f6e, (q15_t)0x90d3, (q15_t)0x3f69, (q15_t)0x90d0, (q15_t)0x3f63, (q15_t)0x90cd, (q15_t)0x3f5e, (q15_t)0x90ca,
+  (q15_t)0x3f58, (q15_t)0x90c7, (q15_t)0x3f53, (q15_t)0x90c4, (q15_t)0x3f4d, (q15_t)0x90c1, (q15_t)0x3f48, (q15_t)0x90bd,
+  (q15_t)0x3f43, (q15_t)0x90ba, (q15_t)0x3f3d, (q15_t)0x90b7, (q15_t)0x3f38, (q15_t)0x90b4, (q15_t)0x3f32, (q15_t)0x90b1,
+  (q15_t)0x3f2d, (q15_t)0x90ae, (q15_t)0x3f27, (q15_t)0x90ab, (q15_t)0x3f22, (q15_t)0x90a8, (q15_t)0x3f1c, (q15_t)0x90a5,
+  (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3f11, (q15_t)0x909e, (q15_t)0x3f0c, (q15_t)0x909b, (q15_t)0x3f06, (q15_t)0x9098,
+  (q15_t)0x3f01, (q15_t)0x9095, (q15_t)0x3efb, (q15_t)0x9092, (q15_t)0x3ef6, (q15_t)0x908f, (q15_t)0x3ef1, (q15_t)0x908c,
+  (q15_t)0x3eeb, (q15_t)0x9089, (q15_t)0x3ee6, (q15_t)0x9086, (q15_t)0x3ee0, (q15_t)0x9083, (q15_t)0x3edb, (q15_t)0x907f,
+  (q15_t)0x3ed5, (q15_t)0x907c, (q15_t)0x3ed0, (q15_t)0x9079, (q15_t)0x3eca, (q15_t)0x9076, (q15_t)0x3ec5, (q15_t)0x9073,
+  (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3eba, (q15_t)0x906d, (q15_t)0x3eb4, (q15_t)0x906a, (q15_t)0x3eaf, (q15_t)0x9067,
+  (q15_t)0x3ea9, (q15_t)0x9064, (q15_t)0x3ea4, (q15_t)0x9061, (q15_t)0x3e9e, (q15_t)0x905e, (q15_t)0x3e99, (q15_t)0x905b,
+  (q15_t)0x3e93, (q15_t)0x9057, (q15_t)0x3e8e, (q15_t)0x9054, (q15_t)0x3e88, (q15_t)0x9051, (q15_t)0x3e83, (q15_t)0x904e,
+  (q15_t)0x3e7d, (q15_t)0x904b, (q15_t)0x3e78, (q15_t)0x9048, (q15_t)0x3e73, (q15_t)0x9045, (q15_t)0x3e6d, (q15_t)0x9042,
+  (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e62, (q15_t)0x903c, (q15_t)0x3e5d, (q15_t)0x9039, (q15_t)0x3e57, (q15_t)0x9036,
+  (q15_t)0x3e52, (q15_t)0x9033, (q15_t)0x3e4c, (q15_t)0x9030, (q15_t)0x3e47, (q15_t)0x902d, (q15_t)0x3e41, (q15_t)0x902a,
+  (q15_t)0x3e3c, (q15_t)0x9026, (q15_t)0x3e36, (q15_t)0x9023, (q15_t)0x3e31, (q15_t)0x9020, (q15_t)0x3e2b, (q15_t)0x901d,
+  (q15_t)0x3e26, (q15_t)0x901a, (q15_t)0x3e20, (q15_t)0x9017, (q15_t)0x3e1b, (q15_t)0x9014, (q15_t)0x3e15, (q15_t)0x9011,
+  (q15_t)0x3e10, (q15_t)0x900e, (q15_t)0x3e0a, (q15_t)0x900b, (q15_t)0x3e05, (q15_t)0x9008, (q15_t)0x3dff, (q15_t)0x9005,
+  (q15_t)0x3dfa, (q15_t)0x9002, (q15_t)0x3df4, (q15_t)0x8fff, (q15_t)0x3def, (q15_t)0x8ffc, (q15_t)0x3de9, (q15_t)0x8ff9,
+  (q15_t)0x3de4, (q15_t)0x8ff6, (q15_t)0x3dde, (q15_t)0x8ff3, (q15_t)0x3dd9, (q15_t)0x8ff0, (q15_t)0x3dd3, (q15_t)0x8fed,
+  (q15_t)0x3dce, (q15_t)0x8fea, (q15_t)0x3dc8, (q15_t)0x8fe7, (q15_t)0x3dc3, (q15_t)0x8fe3, (q15_t)0x3dbd, (q15_t)0x8fe0,
+  (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3db2, (q15_t)0x8fda, (q15_t)0x3dad, (q15_t)0x8fd7, (q15_t)0x3da7, (q15_t)0x8fd4,
+  (q15_t)0x3da2, (q15_t)0x8fd1, (q15_t)0x3d9c, (q15_t)0x8fce, (q15_t)0x3d97, (q15_t)0x8fcb, (q15_t)0x3d91, (q15_t)0x8fc8,
+  (q15_t)0x3d8c, (q15_t)0x8fc5, (q15_t)0x3d86, (q15_t)0x8fc2, (q15_t)0x3d81, (q15_t)0x8fbf, (q15_t)0x3d7b, (q15_t)0x8fbc,
+  (q15_t)0x3d76, (q15_t)0x8fb9, (q15_t)0x3d70, (q15_t)0x8fb6, (q15_t)0x3d6b, (q15_t)0x8fb3, (q15_t)0x3d65, (q15_t)0x8fb0,
+  (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d5a, (q15_t)0x8faa, (q15_t)0x3d55, (q15_t)0x8fa7, (q15_t)0x3d4f, (q15_t)0x8fa4,
+  (q15_t)0x3d49, (q15_t)0x8fa1, (q15_t)0x3d44, (q15_t)0x8f9e, (q15_t)0x3d3e, (q15_t)0x8f9b, (q15_t)0x3d39, (q15_t)0x8f98,
+  (q15_t)0x3d33, (q15_t)0x8f95, (q15_t)0x3d2e, (q15_t)0x8f92, (q15_t)0x3d28, (q15_t)0x8f8f, (q15_t)0x3d23, (q15_t)0x8f8c,
+  (q15_t)0x3d1d, (q15_t)0x8f89, (q15_t)0x3d18, (q15_t)0x8f86, (q15_t)0x3d12, (q15_t)0x8f83, (q15_t)0x3d0d, (q15_t)0x8f80,
+  (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3d02, (q15_t)0x8f7a, (q15_t)0x3cfc, (q15_t)0x8f77, (q15_t)0x3cf7, (q15_t)0x8f74,
+  (q15_t)0x3cf1, (q15_t)0x8f71, (q15_t)0x3cec, (q15_t)0x8f6e, (q15_t)0x3ce6, (q15_t)0x8f6b, (q15_t)0x3ce1, (q15_t)0x8f68,
+  (q15_t)0x3cdb, (q15_t)0x8f65, (q15_t)0x3cd6, (q15_t)0x8f62, (q15_t)0x3cd0, (q15_t)0x8f5f, (q15_t)0x3cca, (q15_t)0x8f5c,
+  (q15_t)0x3cc5, (q15_t)0x8f59, (q15_t)0x3cbf, (q15_t)0x8f56, (q15_t)0x3cba, (q15_t)0x8f53, (q15_t)0x3cb4, (q15_t)0x8f50,
+  (q15_t)0x3caf, (q15_t)0x8f4d, (q15_t)0x3ca9, (q15_t)0x8f4a, (q15_t)0x3ca4, (q15_t)0x8f47, (q15_t)0x3c9e, (q15_t)0x8f44,
+  (q15_t)0x3c99, (q15_t)0x8f41, (q15_t)0x3c93, (q15_t)0x8f3e, (q15_t)0x3c8e, (q15_t)0x8f3b, (q15_t)0x3c88, (q15_t)0x8f38,
+  (q15_t)0x3c83, (q15_t)0x8f35, (q15_t)0x3c7d, (q15_t)0x8f32, (q15_t)0x3c77, (q15_t)0x8f2f, (q15_t)0x3c72, (q15_t)0x8f2d,
+  (q15_t)0x3c6c, (q15_t)0x8f2a, (q15_t)0x3c67, (q15_t)0x8f27, (q15_t)0x3c61, (q15_t)0x8f24, (q15_t)0x3c5c, (q15_t)0x8f21,
+  (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3c51, (q15_t)0x8f1b, (q15_t)0x3c4b, (q15_t)0x8f18, (q15_t)0x3c46, (q15_t)0x8f15,
+  (q15_t)0x3c40, (q15_t)0x8f12, (q15_t)0x3c3b, (q15_t)0x8f0f, (q15_t)0x3c35, (q15_t)0x8f0c, (q15_t)0x3c2f, (q15_t)0x8f09,
+  (q15_t)0x3c2a, (q15_t)0x8f06, (q15_t)0x3c24, (q15_t)0x8f03, (q15_t)0x3c1f, (q15_t)0x8f00, (q15_t)0x3c19, (q15_t)0x8efd,
+  (q15_t)0x3c14, (q15_t)0x8efa, (q15_t)0x3c0e, (q15_t)0x8ef7, (q15_t)0x3c09, (q15_t)0x8ef4, (q15_t)0x3c03, (q15_t)0x8ef1,
+  (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3bf8, (q15_t)0x8eec, (q15_t)0x3bf2, (q15_t)0x8ee9, (q15_t)0x3bed, (q15_t)0x8ee6,
+  (q15_t)0x3be7, (q15_t)0x8ee3, (q15_t)0x3be2, (q15_t)0x8ee0, (q15_t)0x3bdc, (q15_t)0x8edd, (q15_t)0x3bd7, (q15_t)0x8eda,
+  (q15_t)0x3bd1, (q15_t)0x8ed7, (q15_t)0x3bcc, (q15_t)0x8ed4, (q15_t)0x3bc6, (q15_t)0x8ed1, (q15_t)0x3bc0, (q15_t)0x8ece,
+  (q15_t)0x3bbb, (q15_t)0x8ecb, (q15_t)0x3bb5, (q15_t)0x8ec8, (q15_t)0x3bb0, (q15_t)0x8ec5, (q15_t)0x3baa, (q15_t)0x8ec2,
+  (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b9f, (q15_t)0x8ebd, (q15_t)0x3b99, (q15_t)0x8eba, (q15_t)0x3b94, (q15_t)0x8eb7,
+  (q15_t)0x3b8e, (q15_t)0x8eb4, (q15_t)0x3b89, (q15_t)0x8eb1, (q15_t)0x3b83, (q15_t)0x8eae, (q15_t)0x3b7e, (q15_t)0x8eab,
+  (q15_t)0x3b78, (q15_t)0x8ea8, (q15_t)0x3b73, (q15_t)0x8ea5, (q15_t)0x3b6d, (q15_t)0x8ea2, (q15_t)0x3b67, (q15_t)0x8e9f,
+  (q15_t)0x3b62, (q15_t)0x8e9c, (q15_t)0x3b5c, (q15_t)0x8e99, (q15_t)0x3b57, (q15_t)0x8e97, (q15_t)0x3b51, (q15_t)0x8e94,
+  (q15_t)0x3b4c, (q15_t)0x8e91, (q15_t)0x3b46, (q15_t)0x8e8e, (q15_t)0x3b40, (q15_t)0x8e8b, (q15_t)0x3b3b, (q15_t)0x8e88,
+  (q15_t)0x3b35, (q15_t)0x8e85, (q15_t)0x3b30, (q15_t)0x8e82, (q15_t)0x3b2a, (q15_t)0x8e7f, (q15_t)0x3b25, (q15_t)0x8e7c,
+  (q15_t)0x3b1f, (q15_t)0x8e7a, (q15_t)0x3b19, (q15_t)0x8e77, (q15_t)0x3b14, (q15_t)0x8e74, (q15_t)0x3b0e, (q15_t)0x8e71,
+  (q15_t)0x3b09, (q15_t)0x8e6e, (q15_t)0x3b03, (q15_t)0x8e6b, (q15_t)0x3afe, (q15_t)0x8e68, (q15_t)0x3af8, (q15_t)0x8e65,
+  (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3aed, (q15_t)0x8e5f, (q15_t)0x3ae7, (q15_t)0x8e5d, (q15_t)0x3ae2, (q15_t)0x8e5a,
+  (q15_t)0x3adc, (q15_t)0x8e57, (q15_t)0x3ad7, (q15_t)0x8e54, (q15_t)0x3ad1, (q15_t)0x8e51, (q15_t)0x3acb, (q15_t)0x8e4e,
+  (q15_t)0x3ac6, (q15_t)0x8e4b, (q15_t)0x3ac0, (q15_t)0x8e48, (q15_t)0x3abb, (q15_t)0x8e45, (q15_t)0x3ab5, (q15_t)0x8e43,
+  (q15_t)0x3aaf, (q15_t)0x8e40, (q15_t)0x3aaa, (q15_t)0x8e3d, (q15_t)0x3aa4, (q15_t)0x8e3a, (q15_t)0x3a9f, (q15_t)0x8e37,
+  (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a94, (q15_t)0x8e31, (q15_t)0x3a8e, (q15_t)0x8e2e, (q15_t)0x3a88, (q15_t)0x8e2c,
+  (q15_t)0x3a83, (q15_t)0x8e29, (q15_t)0x3a7d, (q15_t)0x8e26, (q15_t)0x3a78, (q15_t)0x8e23, (q15_t)0x3a72, (q15_t)0x8e20,
+  (q15_t)0x3a6c, (q15_t)0x8e1d, (q15_t)0x3a67, (q15_t)0x8e1a, (q15_t)0x3a61, (q15_t)0x8e17, (q15_t)0x3a5c, (q15_t)0x8e15,
+  (q15_t)0x3a56, (q15_t)0x8e12, (q15_t)0x3a50, (q15_t)0x8e0f, (q15_t)0x3a4b, (q15_t)0x8e0c, (q15_t)0x3a45, (q15_t)0x8e09,
+  (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x3a3a, (q15_t)0x8e03, (q15_t)0x3a34, (q15_t)0x8e01, (q15_t)0x3a2f, (q15_t)0x8dfe,
+  (q15_t)0x3a29, (q15_t)0x8dfb, (q15_t)0x3a24, (q15_t)0x8df8, (q15_t)0x3a1e, (q15_t)0x8df5, (q15_t)0x3a19, (q15_t)0x8df2,
+  (q15_t)0x3a13, (q15_t)0x8def, (q15_t)0x3a0d, (q15_t)0x8ded, (q15_t)0x3a08, (q15_t)0x8dea, (q15_t)0x3a02, (q15_t)0x8de7,
+  (q15_t)0x39fd, (q15_t)0x8de4, (q15_t)0x39f7, (q15_t)0x8de1, (q15_t)0x39f1, (q15_t)0x8dde, (q15_t)0x39ec, (q15_t)0x8ddc,
+  (q15_t)0x39e6, (q15_t)0x8dd9, (q15_t)0x39e0, (q15_t)0x8dd6, (q15_t)0x39db, (q15_t)0x8dd3, (q15_t)0x39d5, (q15_t)0x8dd0,
+  (q15_t)0x39d0, (q15_t)0x8dcd, (q15_t)0x39ca, (q15_t)0x8dca, (q15_t)0x39c4, (q15_t)0x8dc8, (q15_t)0x39bf, (q15_t)0x8dc5,
+  (q15_t)0x39b9, (q15_t)0x8dc2, (q15_t)0x39b4, (q15_t)0x8dbf, (q15_t)0x39ae, (q15_t)0x8dbc, (q15_t)0x39a8, (q15_t)0x8db9,
+  (q15_t)0x39a3, (q15_t)0x8db7, (q15_t)0x399d, (q15_t)0x8db4, (q15_t)0x3998, (q15_t)0x8db1, (q15_t)0x3992, (q15_t)0x8dae,
+  (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3987, (q15_t)0x8da9, (q15_t)0x3981, (q15_t)0x8da6, (q15_t)0x397c, (q15_t)0x8da3,
+  (q15_t)0x3976, (q15_t)0x8da0, (q15_t)0x3970, (q15_t)0x8d9d, (q15_t)0x396b, (q15_t)0x8d9a, (q15_t)0x3965, (q15_t)0x8d98,
+  (q15_t)0x395f, (q15_t)0x8d95, (q15_t)0x395a, (q15_t)0x8d92, (q15_t)0x3954, (q15_t)0x8d8f, (q15_t)0x394f, (q15_t)0x8d8c,
+  (q15_t)0x3949, (q15_t)0x8d8a, (q15_t)0x3943, (q15_t)0x8d87, (q15_t)0x393e, (q15_t)0x8d84, (q15_t)0x3938, (q15_t)0x8d81,
+  (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x392d, (q15_t)0x8d7b, (q15_t)0x3927, (q15_t)0x8d79, (q15_t)0x3922, (q15_t)0x8d76,
+  (q15_t)0x391c, (q15_t)0x8d73, (q15_t)0x3916, (q15_t)0x8d70, (q15_t)0x3911, (q15_t)0x8d6d, (q15_t)0x390b, (q15_t)0x8d6b,
+  (q15_t)0x3906, (q15_t)0x8d68, (q15_t)0x3900, (q15_t)0x8d65, (q15_t)0x38fa, (q15_t)0x8d62, (q15_t)0x38f5, (q15_t)0x8d5f,
+  (q15_t)0x38ef, (q15_t)0x8d5d, (q15_t)0x38e9, (q15_t)0x8d5a, (q15_t)0x38e4, (q15_t)0x8d57, (q15_t)0x38de, (q15_t)0x8d54,
+  (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x38d3, (q15_t)0x8d4f, (q15_t)0x38cd, (q15_t)0x8d4c, (q15_t)0x38c8, (q15_t)0x8d49,
+  (q15_t)0x38c2, (q15_t)0x8d46, (q15_t)0x38bc, (q15_t)0x8d44, (q15_t)0x38b7, (q15_t)0x8d41, (q15_t)0x38b1, (q15_t)0x8d3e,
+  (q15_t)0x38ab, (q15_t)0x8d3b, (q15_t)0x38a6, (q15_t)0x8d38, (q15_t)0x38a0, (q15_t)0x8d36, (q15_t)0x389b, (q15_t)0x8d33,
+  (q15_t)0x3895, (q15_t)0x8d30, (q15_t)0x388f, (q15_t)0x8d2d, (q15_t)0x388a, (q15_t)0x8d2b, (q15_t)0x3884, (q15_t)0x8d28,
+  (q15_t)0x387e, (q15_t)0x8d25, (q15_t)0x3879, (q15_t)0x8d22, (q15_t)0x3873, (q15_t)0x8d1f, (q15_t)0x386d, (q15_t)0x8d1d,
+  (q15_t)0x3868, (q15_t)0x8d1a, (q15_t)0x3862, (q15_t)0x8d17, (q15_t)0x385d, (q15_t)0x8d14, (q15_t)0x3857, (q15_t)0x8d12,
+  (q15_t)0x3851, (q15_t)0x8d0f, (q15_t)0x384c, (q15_t)0x8d0c, (q15_t)0x3846, (q15_t)0x8d09, (q15_t)0x3840, (q15_t)0x8d07,
+  (q15_t)0x383b, (q15_t)0x8d04, (q15_t)0x3835, (q15_t)0x8d01, (q15_t)0x382f, (q15_t)0x8cfe, (q15_t)0x382a, (q15_t)0x8cfb,
+  (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x381e, (q15_t)0x8cf6, (q15_t)0x3819, (q15_t)0x8cf3, (q15_t)0x3813, (q15_t)0x8cf0,
+  (q15_t)0x380d, (q15_t)0x8cee, (q15_t)0x3808, (q15_t)0x8ceb, (q15_t)0x3802, (q15_t)0x8ce8, (q15_t)0x37fd, (q15_t)0x8ce5,
+  (q15_t)0x37f7, (q15_t)0x8ce3, (q15_t)0x37f1, (q15_t)0x8ce0, (q15_t)0x37ec, (q15_t)0x8cdd, (q15_t)0x37e6, (q15_t)0x8cda,
+  (q15_t)0x37e0, (q15_t)0x8cd8, (q15_t)0x37db, (q15_t)0x8cd5, (q15_t)0x37d5, (q15_t)0x8cd2, (q15_t)0x37cf, (q15_t)0x8cd0,
+  (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x37c4, (q15_t)0x8cca, (q15_t)0x37be, (q15_t)0x8cc7, (q15_t)0x37b9, (q15_t)0x8cc5,
+  (q15_t)0x37b3, (q15_t)0x8cc2, (q15_t)0x37ad, (q15_t)0x8cbf, (q15_t)0x37a8, (q15_t)0x8cbc, (q15_t)0x37a2, (q15_t)0x8cba,
+  (q15_t)0x379c, (q15_t)0x8cb7, (q15_t)0x3797, (q15_t)0x8cb4, (q15_t)0x3791, (q15_t)0x8cb1, (q15_t)0x378b, (q15_t)0x8caf,
+  (q15_t)0x3786, (q15_t)0x8cac, (q15_t)0x3780, (q15_t)0x8ca9, (q15_t)0x377a, (q15_t)0x8ca7, (q15_t)0x3775, (q15_t)0x8ca4,
+  (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3769, (q15_t)0x8c9e, (q15_t)0x3764, (q15_t)0x8c9c, (q15_t)0x375e, (q15_t)0x8c99,
+  (q15_t)0x3758, (q15_t)0x8c96, (q15_t)0x3753, (q15_t)0x8c94, (q15_t)0x374d, (q15_t)0x8c91, (q15_t)0x3747, (q15_t)0x8c8e,
+  (q15_t)0x3742, (q15_t)0x8c8b, (q15_t)0x373c, (q15_t)0x8c89, (q15_t)0x3736, (q15_t)0x8c86, (q15_t)0x3731, (q15_t)0x8c83,
+  (q15_t)0x372b, (q15_t)0x8c81, (q15_t)0x3725, (q15_t)0x8c7e, (q15_t)0x3720, (q15_t)0x8c7b, (q15_t)0x371a, (q15_t)0x8c78,
+  (q15_t)0x3714, (q15_t)0x8c76, (q15_t)0x370f, (q15_t)0x8c73, (q15_t)0x3709, (q15_t)0x8c70, (q15_t)0x3703, (q15_t)0x8c6e,
+  (q15_t)0x36fe, (q15_t)0x8c6b, (q15_t)0x36f8, (q15_t)0x8c68, (q15_t)0x36f2, (q15_t)0x8c65, (q15_t)0x36ed, (q15_t)0x8c63,
+  (q15_t)0x36e7, (q15_t)0x8c60, (q15_t)0x36e1, (q15_t)0x8c5d, (q15_t)0x36dc, (q15_t)0x8c5b, (q15_t)0x36d6, (q15_t)0x8c58,
+  (q15_t)0x36d0, (q15_t)0x8c55, (q15_t)0x36cb, (q15_t)0x8c53, (q15_t)0x36c5, (q15_t)0x8c50, (q15_t)0x36bf, (q15_t)0x8c4d,
+  (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x36b4, (q15_t)0x8c48, (q15_t)0x36ae, (q15_t)0x8c45, (q15_t)0x36a9, (q15_t)0x8c43,
+  (q15_t)0x36a3, (q15_t)0x8c40, (q15_t)0x369d, (q15_t)0x8c3d, (q15_t)0x3698, (q15_t)0x8c3a, (q15_t)0x3692, (q15_t)0x8c38,
+  (q15_t)0x368c, (q15_t)0x8c35, (q15_t)0x3686, (q15_t)0x8c32, (q15_t)0x3681, (q15_t)0x8c30, (q15_t)0x367b, (q15_t)0x8c2d,
+  (q15_t)0x3675, (q15_t)0x8c2a, (q15_t)0x3670, (q15_t)0x8c28, (q15_t)0x366a, (q15_t)0x8c25, (q15_t)0x3664, (q15_t)0x8c22,
+  (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3659, (q15_t)0x8c1d, (q15_t)0x3653, (q15_t)0x8c1a, (q15_t)0x364e, (q15_t)0x8c18,
+  (q15_t)0x3648, (q15_t)0x8c15, (q15_t)0x3642, (q15_t)0x8c12, (q15_t)0x363d, (q15_t)0x8c10, (q15_t)0x3637, (q15_t)0x8c0d,
+  (q15_t)0x3631, (q15_t)0x8c0a, (q15_t)0x362b, (q15_t)0x8c08, (q15_t)0x3626, (q15_t)0x8c05, (q15_t)0x3620, (q15_t)0x8c02,
+  (q15_t)0x361a, (q15_t)0x8c00, (q15_t)0x3615, (q15_t)0x8bfd, (q15_t)0x360f, (q15_t)0x8bfa, (q15_t)0x3609, (q15_t)0x8bf8,
+  (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35fe, (q15_t)0x8bf3, (q15_t)0x35f8, (q15_t)0x8bf0, (q15_t)0x35f3, (q15_t)0x8bed,
+  (q15_t)0x35ed, (q15_t)0x8beb, (q15_t)0x35e7, (q15_t)0x8be8, (q15_t)0x35e1, (q15_t)0x8be5, (q15_t)0x35dc, (q15_t)0x8be3,
+  (q15_t)0x35d6, (q15_t)0x8be0, (q15_t)0x35d0, (q15_t)0x8bdd, (q15_t)0x35cb, (q15_t)0x8bdb, (q15_t)0x35c5, (q15_t)0x8bd8,
+  (q15_t)0x35bf, (q15_t)0x8bd5, (q15_t)0x35ba, (q15_t)0x8bd3, (q15_t)0x35b4, (q15_t)0x8bd0, (q15_t)0x35ae, (q15_t)0x8bce,
+  (q15_t)0x35a8, (q15_t)0x8bcb, (q15_t)0x35a3, (q15_t)0x8bc8, (q15_t)0x359d, (q15_t)0x8bc6, (q15_t)0x3597, (q15_t)0x8bc3,
+  (q15_t)0x3592, (q15_t)0x8bc0, (q15_t)0x358c, (q15_t)0x8bbe, (q15_t)0x3586, (q15_t)0x8bbb, (q15_t)0x3580, (q15_t)0x8bb8,
+  (q15_t)0x357b, (q15_t)0x8bb6, (q15_t)0x3575, (q15_t)0x8bb3, (q15_t)0x356f, (q15_t)0x8bb1, (q15_t)0x356a, (q15_t)0x8bae,
+  (q15_t)0x3564, (q15_t)0x8bab, (q15_t)0x355e, (q15_t)0x8ba9, (q15_t)0x3558, (q15_t)0x8ba6, (q15_t)0x3553, (q15_t)0x8ba4,
+  (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x3547, (q15_t)0x8b9e, (q15_t)0x3542, (q15_t)0x8b9c, (q15_t)0x353c, (q15_t)0x8b99,
+  (q15_t)0x3536, (q15_t)0x8b96, (q15_t)0x3530, (q15_t)0x8b94, (q15_t)0x352b, (q15_t)0x8b91, (q15_t)0x3525, (q15_t)0x8b8f,
+  (q15_t)0x351f, (q15_t)0x8b8c, (q15_t)0x351a, (q15_t)0x8b89, (q15_t)0x3514, (q15_t)0x8b87, (q15_t)0x350e, (q15_t)0x8b84,
+  (q15_t)0x3508, (q15_t)0x8b82, (q15_t)0x3503, (q15_t)0x8b7f, (q15_t)0x34fd, (q15_t)0x8b7c, (q15_t)0x34f7, (q15_t)0x8b7a,
+  (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x34ec, (q15_t)0x8b75, (q15_t)0x34e6, (q15_t)0x8b72, (q15_t)0x34e0, (q15_t)0x8b6f,
+  (q15_t)0x34db, (q15_t)0x8b6d, (q15_t)0x34d5, (q15_t)0x8b6a, (q15_t)0x34cf, (q15_t)0x8b68, (q15_t)0x34ca, (q15_t)0x8b65,
+  (q15_t)0x34c4, (q15_t)0x8b62, (q15_t)0x34be, (q15_t)0x8b60, (q15_t)0x34b8, (q15_t)0x8b5d, (q15_t)0x34b3, (q15_t)0x8b5b,
+  (q15_t)0x34ad, (q15_t)0x8b58, (q15_t)0x34a7, (q15_t)0x8b55, (q15_t)0x34a1, (q15_t)0x8b53, (q15_t)0x349c, (q15_t)0x8b50,
+  (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x3490, (q15_t)0x8b4b, (q15_t)0x348b, (q15_t)0x8b49, (q15_t)0x3485, (q15_t)0x8b46,
+  (q15_t)0x347f, (q15_t)0x8b43, (q15_t)0x3479, (q15_t)0x8b41, (q15_t)0x3474, (q15_t)0x8b3e, (q15_t)0x346e, (q15_t)0x8b3c,
+  (q15_t)0x3468, (q15_t)0x8b39, (q15_t)0x3462, (q15_t)0x8b37, (q15_t)0x345d, (q15_t)0x8b34, (q15_t)0x3457, (q15_t)0x8b31,
+  (q15_t)0x3451, (q15_t)0x8b2f, (q15_t)0x344b, (q15_t)0x8b2c, (q15_t)0x3446, (q15_t)0x8b2a, (q15_t)0x3440, (q15_t)0x8b27,
+  (q15_t)0x343a, (q15_t)0x8b25, (q15_t)0x3435, (q15_t)0x8b22, (q15_t)0x342f, (q15_t)0x8b1f, (q15_t)0x3429, (q15_t)0x8b1d,
+  (q15_t)0x3423, (q15_t)0x8b1a, (q15_t)0x341e, (q15_t)0x8b18, (q15_t)0x3418, (q15_t)0x8b15, (q15_t)0x3412, (q15_t)0x8b13,
+  (q15_t)0x340c, (q15_t)0x8b10, (q15_t)0x3407, (q15_t)0x8b0e, (q15_t)0x3401, (q15_t)0x8b0b, (q15_t)0x33fb, (q15_t)0x8b08,
+  (q15_t)0x33f5, (q15_t)0x8b06, (q15_t)0x33f0, (q15_t)0x8b03, (q15_t)0x33ea, (q15_t)0x8b01, (q15_t)0x33e4, (q15_t)0x8afe,
+  (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x33d9, (q15_t)0x8af9, (q15_t)0x33d3, (q15_t)0x8af7, (q15_t)0x33cd, (q15_t)0x8af4,
+  (q15_t)0x33c7, (q15_t)0x8af1, (q15_t)0x33c2, (q15_t)0x8aef, (q15_t)0x33bc, (q15_t)0x8aec, (q15_t)0x33b6, (q15_t)0x8aea,
+  (q15_t)0x33b0, (q15_t)0x8ae7, (q15_t)0x33ab, (q15_t)0x8ae5, (q15_t)0x33a5, (q15_t)0x8ae2, (q15_t)0x339f, (q15_t)0x8ae0,
+  (q15_t)0x3399, (q15_t)0x8add, (q15_t)0x3394, (q15_t)0x8adb, (q15_t)0x338e, (q15_t)0x8ad8, (q15_t)0x3388, (q15_t)0x8ad6,
+  (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x337d, (q15_t)0x8ad1, (q15_t)0x3377, (q15_t)0x8ace, (q15_t)0x3371, (q15_t)0x8acb,
+  (q15_t)0x336b, (q15_t)0x8ac9, (q15_t)0x3366, (q15_t)0x8ac6, (q15_t)0x3360, (q15_t)0x8ac4, (q15_t)0x335a, (q15_t)0x8ac1,
+  (q15_t)0x3354, (q15_t)0x8abf, (q15_t)0x334f, (q15_t)0x8abc, (q15_t)0x3349, (q15_t)0x8aba, (q15_t)0x3343, (q15_t)0x8ab7,
+  (q15_t)0x333d, (q15_t)0x8ab5, (q15_t)0x3338, (q15_t)0x8ab2, (q15_t)0x3332, (q15_t)0x8ab0, (q15_t)0x332c, (q15_t)0x8aad,
+  (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x3321, (q15_t)0x8aa8, (q15_t)0x331b, (q15_t)0x8aa6, (q15_t)0x3315, (q15_t)0x8aa3,
+  (q15_t)0x330f, (q15_t)0x8aa1, (q15_t)0x330a, (q15_t)0x8a9e, (q15_t)0x3304, (q15_t)0x8a9c, (q15_t)0x32fe, (q15_t)0x8a99,
+  (q15_t)0x32f8, (q15_t)0x8a97, (q15_t)0x32f3, (q15_t)0x8a94, (q15_t)0x32ed, (q15_t)0x8a92, (q15_t)0x32e7, (q15_t)0x8a8f,
+  (q15_t)0x32e1, (q15_t)0x8a8d, (q15_t)0x32db, (q15_t)0x8a8a, (q15_t)0x32d6, (q15_t)0x8a88, (q15_t)0x32d0, (q15_t)0x8a85,
+  (q15_t)0x32ca, (q15_t)0x8a83, (q15_t)0x32c4, (q15_t)0x8a80, (q15_t)0x32bf, (q15_t)0x8a7e, (q15_t)0x32b9, (q15_t)0x8a7b,
+  (q15_t)0x32b3, (q15_t)0x8a79, (q15_t)0x32ad, (q15_t)0x8a76, (q15_t)0x32a8, (q15_t)0x8a74, (q15_t)0x32a2, (q15_t)0x8a71,
+  (q15_t)0x329c, (q15_t)0x8a6f, (q15_t)0x3296, (q15_t)0x8a6c, (q15_t)0x3290, (q15_t)0x8a6a, (q15_t)0x328b, (q15_t)0x8a67,
+  (q15_t)0x3285, (q15_t)0x8a65, (q15_t)0x327f, (q15_t)0x8a62, (q15_t)0x3279, (q15_t)0x8a60, (q15_t)0x3274, (q15_t)0x8a5d,
+  (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3268, (q15_t)0x8a59, (q15_t)0x3262, (q15_t)0x8a56, (q15_t)0x325d, (q15_t)0x8a54,
+  (q15_t)0x3257, (q15_t)0x8a51, (q15_t)0x3251, (q15_t)0x8a4f, (q15_t)0x324b, (q15_t)0x8a4c, (q15_t)0x3245, (q15_t)0x8a4a,
+  (q15_t)0x3240, (q15_t)0x8a47, (q15_t)0x323a, (q15_t)0x8a45, (q15_t)0x3234, (q15_t)0x8a42, (q15_t)0x322e, (q15_t)0x8a40,
+  (q15_t)0x3228, (q15_t)0x8a3d, (q15_t)0x3223, (q15_t)0x8a3b, (q15_t)0x321d, (q15_t)0x8a38, (q15_t)0x3217, (q15_t)0x8a36,
+  (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x320c, (q15_t)0x8a31, (q15_t)0x3206, (q15_t)0x8a2f, (q15_t)0x3200, (q15_t)0x8a2c,
+  (q15_t)0x31fa, (q15_t)0x8a2a, (q15_t)0x31f4, (q15_t)0x8a27, (q15_t)0x31ef, (q15_t)0x8a25, (q15_t)0x31e9, (q15_t)0x8a22,
+  (q15_t)0x31e3, (q15_t)0x8a20, (q15_t)0x31dd, (q15_t)0x8a1d, (q15_t)0x31d8, (q15_t)0x8a1b, (q15_t)0x31d2, (q15_t)0x8a19,
+  (q15_t)0x31cc, (q15_t)0x8a16, (q15_t)0x31c6, (q15_t)0x8a14, (q15_t)0x31c0, (q15_t)0x8a11, (q15_t)0x31bb, (q15_t)0x8a0f,
+  (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x31af, (q15_t)0x8a0a, (q15_t)0x31a9, (q15_t)0x8a07, (q15_t)0x31a3, (q15_t)0x8a05,
+  (q15_t)0x319e, (q15_t)0x8a03, (q15_t)0x3198, (q15_t)0x8a00, (q15_t)0x3192, (q15_t)0x89fe, (q15_t)0x318c, (q15_t)0x89fb,
+  (q15_t)0x3186, (q15_t)0x89f9, (q15_t)0x3181, (q15_t)0x89f6, (q15_t)0x317b, (q15_t)0x89f4, (q15_t)0x3175, (q15_t)0x89f2,
+  (q15_t)0x316f, (q15_t)0x89ef, (q15_t)0x3169, (q15_t)0x89ed, (q15_t)0x3164, (q15_t)0x89ea, (q15_t)0x315e, (q15_t)0x89e8,
+  (q15_t)0x3158, (q15_t)0x89e5, (q15_t)0x3152, (q15_t)0x89e3, (q15_t)0x314c, (q15_t)0x89e1, (q15_t)0x3147, (q15_t)0x89de,
+  (q15_t)0x3141, (q15_t)0x89dc, (q15_t)0x313b, (q15_t)0x89d9, (q15_t)0x3135, (q15_t)0x89d7, (q15_t)0x312f, (q15_t)0x89d5,
+  (q15_t)0x312a, (q15_t)0x89d2, (q15_t)0x3124, (q15_t)0x89d0, (q15_t)0x311e, (q15_t)0x89cd, (q15_t)0x3118, (q15_t)0x89cb,
+  (q15_t)0x3112, (q15_t)0x89c8, (q15_t)0x310d, (q15_t)0x89c6, (q15_t)0x3107, (q15_t)0x89c4, (q15_t)0x3101, (q15_t)0x89c1,
+  (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x30f5, (q15_t)0x89bc, (q15_t)0x30f0, (q15_t)0x89ba, (q15_t)0x30ea, (q15_t)0x89b8,
+  (q15_t)0x30e4, (q15_t)0x89b5, (q15_t)0x30de, (q15_t)0x89b3, (q15_t)0x30d8, (q15_t)0x89b0, (q15_t)0x30d3, (q15_t)0x89ae,
+  (q15_t)0x30cd, (q15_t)0x89ac, (q15_t)0x30c7, (q15_t)0x89a9, (q15_t)0x30c1, (q15_t)0x89a7, (q15_t)0x30bb, (q15_t)0x89a4,
+  (q15_t)0x30b6, (q15_t)0x89a2, (q15_t)0x30b0, (q15_t)0x89a0, (q15_t)0x30aa, (q15_t)0x899d, (q15_t)0x30a4, (q15_t)0x899b,
+  (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3099, (q15_t)0x8996, (q15_t)0x3093, (q15_t)0x8994, (q15_t)0x308d, (q15_t)0x8991,
+  (q15_t)0x3087, (q15_t)0x898f, (q15_t)0x3081, (q15_t)0x898d, (q15_t)0x307b, (q15_t)0x898a, (q15_t)0x3076, (q15_t)0x8988,
+  (q15_t)0x3070, (q15_t)0x8985, (q15_t)0x306a, (q15_t)0x8983, (q15_t)0x3064, (q15_t)0x8981, (q15_t)0x305e, (q15_t)0x897e,
+  (q15_t)0x3059, (q15_t)0x897c, (q15_t)0x3053, (q15_t)0x897a, (q15_t)0x304d, (q15_t)0x8977, (q15_t)0x3047, (q15_t)0x8975,
+  (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x303b, (q15_t)0x8970, (q15_t)0x3036, (q15_t)0x896e, (q15_t)0x3030, (q15_t)0x896b,
+  (q15_t)0x302a, (q15_t)0x8969, (q15_t)0x3024, (q15_t)0x8967, (q15_t)0x301e, (q15_t)0x8964, (q15_t)0x3019, (q15_t)0x8962,
+  (q15_t)0x3013, (q15_t)0x8960, (q15_t)0x300d, (q15_t)0x895d, (q15_t)0x3007, (q15_t)0x895b, (q15_t)0x3001, (q15_t)0x8958,
+  (q15_t)0x2ffb, (q15_t)0x8956, (q15_t)0x2ff6, (q15_t)0x8954, (q15_t)0x2ff0, (q15_t)0x8951, (q15_t)0x2fea, (q15_t)0x894f,
+  (q15_t)0x2fe4, (q15_t)0x894d, (q15_t)0x2fde, (q15_t)0x894a, (q15_t)0x2fd8, (q15_t)0x8948, (q15_t)0x2fd3, (q15_t)0x8946,
+  (q15_t)0x2fcd, (q15_t)0x8943, (q15_t)0x2fc7, (q15_t)0x8941, (q15_t)0x2fc1, (q15_t)0x893f, (q15_t)0x2fbb, (q15_t)0x893c,
+  (q15_t)0x2fb5, (q15_t)0x893a, (q15_t)0x2fb0, (q15_t)0x8938, (q15_t)0x2faa, (q15_t)0x8935, (q15_t)0x2fa4, (q15_t)0x8933,
+  (q15_t)0x2f9e, (q15_t)0x8931, (q15_t)0x2f98, (q15_t)0x892e, (q15_t)0x2f92, (q15_t)0x892c, (q15_t)0x2f8d, (q15_t)0x892a,
+  (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f81, (q15_t)0x8925, (q15_t)0x2f7b, (q15_t)0x8923, (q15_t)0x2f75, (q15_t)0x8920,
+  (q15_t)0x2f6f, (q15_t)0x891e, (q15_t)0x2f6a, (q15_t)0x891c, (q15_t)0x2f64, (q15_t)0x8919, (q15_t)0x2f5e, (q15_t)0x8917,
+  (q15_t)0x2f58, (q15_t)0x8915, (q15_t)0x2f52, (q15_t)0x8912, (q15_t)0x2f4c, (q15_t)0x8910, (q15_t)0x2f47, (q15_t)0x890e,
+  (q15_t)0x2f41, (q15_t)0x890b, (q15_t)0x2f3b, (q15_t)0x8909, (q15_t)0x2f35, (q15_t)0x8907, (q15_t)0x2f2f, (q15_t)0x8904,
+  (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2f24, (q15_t)0x8900, (q15_t)0x2f1e, (q15_t)0x88fd, (q15_t)0x2f18, (q15_t)0x88fb,
+  (q15_t)0x2f12, (q15_t)0x88f9, (q15_t)0x2f0c, (q15_t)0x88f6, (q15_t)0x2f06, (q15_t)0x88f4, (q15_t)0x2f01, (q15_t)0x88f2,
+  (q15_t)0x2efb, (q15_t)0x88f0, (q15_t)0x2ef5, (q15_t)0x88ed, (q15_t)0x2eef, (q15_t)0x88eb, (q15_t)0x2ee9, (q15_t)0x88e9,
+  (q15_t)0x2ee3, (q15_t)0x88e6, (q15_t)0x2edd, (q15_t)0x88e4, (q15_t)0x2ed8, (q15_t)0x88e2, (q15_t)0x2ed2, (q15_t)0x88df,
+  (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2ec6, (q15_t)0x88db, (q15_t)0x2ec0, (q15_t)0x88d9, (q15_t)0x2eba, (q15_t)0x88d6,
+  (q15_t)0x2eb5, (q15_t)0x88d4, (q15_t)0x2eaf, (q15_t)0x88d2, (q15_t)0x2ea9, (q15_t)0x88cf, (q15_t)0x2ea3, (q15_t)0x88cd,
+  (q15_t)0x2e9d, (q15_t)0x88cb, (q15_t)0x2e97, (q15_t)0x88c8, (q15_t)0x2e91, (q15_t)0x88c6, (q15_t)0x2e8c, (q15_t)0x88c4,
+  (q15_t)0x2e86, (q15_t)0x88c2, (q15_t)0x2e80, (q15_t)0x88bf, (q15_t)0x2e7a, (q15_t)0x88bd, (q15_t)0x2e74, (q15_t)0x88bb,
+  (q15_t)0x2e6e, (q15_t)0x88b9, (q15_t)0x2e68, (q15_t)0x88b6, (q15_t)0x2e63, (q15_t)0x88b4, (q15_t)0x2e5d, (q15_t)0x88b2,
+  (q15_t)0x2e57, (q15_t)0x88af, (q15_t)0x2e51, (q15_t)0x88ad, (q15_t)0x2e4b, (q15_t)0x88ab, (q15_t)0x2e45, (q15_t)0x88a9,
+  (q15_t)0x2e3f, (q15_t)0x88a6, (q15_t)0x2e3a, (q15_t)0x88a4, (q15_t)0x2e34, (q15_t)0x88a2, (q15_t)0x2e2e, (q15_t)0x88a0,
+  (q15_t)0x2e28, (q15_t)0x889d, (q15_t)0x2e22, (q15_t)0x889b, (q15_t)0x2e1c, (q15_t)0x8899, (q15_t)0x2e16, (q15_t)0x8896,
+  (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2e0b, (q15_t)0x8892, (q15_t)0x2e05, (q15_t)0x8890, (q15_t)0x2dff, (q15_t)0x888d,
+  (q15_t)0x2df9, (q15_t)0x888b, (q15_t)0x2df3, (q15_t)0x8889, (q15_t)0x2ded, (q15_t)0x8887, (q15_t)0x2de7, (q15_t)0x8884,
+  (q15_t)0x2de2, (q15_t)0x8882, (q15_t)0x2ddc, (q15_t)0x8880, (q15_t)0x2dd6, (q15_t)0x887e, (q15_t)0x2dd0, (q15_t)0x887b,
+  (q15_t)0x2dca, (q15_t)0x8879, (q15_t)0x2dc4, (q15_t)0x8877, (q15_t)0x2dbe, (q15_t)0x8875, (q15_t)0x2db9, (q15_t)0x8872,
+  (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2dad, (q15_t)0x886e, (q15_t)0x2da7, (q15_t)0x886c, (q15_t)0x2da1, (q15_t)0x8869,
+  (q15_t)0x2d9b, (q15_t)0x8867, (q15_t)0x2d95, (q15_t)0x8865, (q15_t)0x2d8f, (q15_t)0x8863, (q15_t)0x2d8a, (q15_t)0x8860,
+  (q15_t)0x2d84, (q15_t)0x885e, (q15_t)0x2d7e, (q15_t)0x885c, (q15_t)0x2d78, (q15_t)0x885a, (q15_t)0x2d72, (q15_t)0x8858,
+  (q15_t)0x2d6c, (q15_t)0x8855, (q15_t)0x2d66, (q15_t)0x8853, (q15_t)0x2d60, (q15_t)0x8851, (q15_t)0x2d5b, (q15_t)0x884f,
+  (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2d4f, (q15_t)0x884a, (q15_t)0x2d49, (q15_t)0x8848, (q15_t)0x2d43, (q15_t)0x8846,
+  (q15_t)0x2d3d, (q15_t)0x8844, (q15_t)0x2d37, (q15_t)0x8841, (q15_t)0x2d31, (q15_t)0x883f, (q15_t)0x2d2c, (q15_t)0x883d,
+  (q15_t)0x2d26, (q15_t)0x883b, (q15_t)0x2d20, (q15_t)0x8838, (q15_t)0x2d1a, (q15_t)0x8836, (q15_t)0x2d14, (q15_t)0x8834,
+  (q15_t)0x2d0e, (q15_t)0x8832, (q15_t)0x2d08, (q15_t)0x8830, (q15_t)0x2d02, (q15_t)0x882d, (q15_t)0x2cfd, (q15_t)0x882b,
+  (q15_t)0x2cf7, (q15_t)0x8829, (q15_t)0x2cf1, (q15_t)0x8827, (q15_t)0x2ceb, (q15_t)0x8825, (q15_t)0x2ce5, (q15_t)0x8822,
+  (q15_t)0x2cdf, (q15_t)0x8820, (q15_t)0x2cd9, (q15_t)0x881e, (q15_t)0x2cd3, (q15_t)0x881c, (q15_t)0x2ccd, (q15_t)0x881a,
+  (q15_t)0x2cc8, (q15_t)0x8817, (q15_t)0x2cc2, (q15_t)0x8815, (q15_t)0x2cbc, (q15_t)0x8813, (q15_t)0x2cb6, (q15_t)0x8811,
+  (q15_t)0x2cb0, (q15_t)0x880f, (q15_t)0x2caa, (q15_t)0x880c, (q15_t)0x2ca4, (q15_t)0x880a, (q15_t)0x2c9e, (q15_t)0x8808,
+  (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c93, (q15_t)0x8804, (q15_t)0x2c8d, (q15_t)0x8801, (q15_t)0x2c87, (q15_t)0x87ff,
+  (q15_t)0x2c81, (q15_t)0x87fd, (q15_t)0x2c7b, (q15_t)0x87fb, (q15_t)0x2c75, (q15_t)0x87f9, (q15_t)0x2c6f, (q15_t)0x87f6,
+  (q15_t)0x2c69, (q15_t)0x87f4, (q15_t)0x2c63, (q15_t)0x87f2, (q15_t)0x2c5e, (q15_t)0x87f0, (q15_t)0x2c58, (q15_t)0x87ee,
+  (q15_t)0x2c52, (q15_t)0x87ec, (q15_t)0x2c4c, (q15_t)0x87e9, (q15_t)0x2c46, (q15_t)0x87e7, (q15_t)0x2c40, (q15_t)0x87e5,
+  (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2c34, (q15_t)0x87e1, (q15_t)0x2c2e, (q15_t)0x87df, (q15_t)0x2c29, (q15_t)0x87dc,
+  (q15_t)0x2c23, (q15_t)0x87da, (q15_t)0x2c1d, (q15_t)0x87d8, (q15_t)0x2c17, (q15_t)0x87d6, (q15_t)0x2c11, (q15_t)0x87d4,
+  (q15_t)0x2c0b, (q15_t)0x87d2, (q15_t)0x2c05, (q15_t)0x87cf, (q15_t)0x2bff, (q15_t)0x87cd, (q15_t)0x2bf9, (q15_t)0x87cb,
+  (q15_t)0x2bf3, (q15_t)0x87c9, (q15_t)0x2bee, (q15_t)0x87c7, (q15_t)0x2be8, (q15_t)0x87c5, (q15_t)0x2be2, (q15_t)0x87c2,
+  (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2bd6, (q15_t)0x87be, (q15_t)0x2bd0, (q15_t)0x87bc, (q15_t)0x2bca, (q15_t)0x87ba,
+  (q15_t)0x2bc4, (q15_t)0x87b8, (q15_t)0x2bbe, (q15_t)0x87b6, (q15_t)0x2bb8, (q15_t)0x87b3, (q15_t)0x2bb2, (q15_t)0x87b1,
+  (q15_t)0x2bad, (q15_t)0x87af, (q15_t)0x2ba7, (q15_t)0x87ad, (q15_t)0x2ba1, (q15_t)0x87ab, (q15_t)0x2b9b, (q15_t)0x87a9,
+  (q15_t)0x2b95, (q15_t)0x87a7, (q15_t)0x2b8f, (q15_t)0x87a4, (q15_t)0x2b89, (q15_t)0x87a2, (q15_t)0x2b83, (q15_t)0x87a0,
+  (q15_t)0x2b7d, (q15_t)0x879e, (q15_t)0x2b77, (q15_t)0x879c, (q15_t)0x2b71, (q15_t)0x879a, (q15_t)0x2b6c, (q15_t)0x8798,
+  (q15_t)0x2b66, (q15_t)0x8795, (q15_t)0x2b60, (q15_t)0x8793, (q15_t)0x2b5a, (q15_t)0x8791, (q15_t)0x2b54, (q15_t)0x878f,
+  (q15_t)0x2b4e, (q15_t)0x878d, (q15_t)0x2b48, (q15_t)0x878b, (q15_t)0x2b42, (q15_t)0x8789, (q15_t)0x2b3c, (q15_t)0x8787,
+  (q15_t)0x2b36, (q15_t)0x8784, (q15_t)0x2b30, (q15_t)0x8782, (q15_t)0x2b2b, (q15_t)0x8780, (q15_t)0x2b25, (q15_t)0x877e,
+  (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2b19, (q15_t)0x877a, (q15_t)0x2b13, (q15_t)0x8778, (q15_t)0x2b0d, (q15_t)0x8776,
+  (q15_t)0x2b07, (q15_t)0x8774, (q15_t)0x2b01, (q15_t)0x8771, (q15_t)0x2afb, (q15_t)0x876f, (q15_t)0x2af5, (q15_t)0x876d,
+  (q15_t)0x2aef, (q15_t)0x876b, (q15_t)0x2ae9, (q15_t)0x8769, (q15_t)0x2ae4, (q15_t)0x8767, (q15_t)0x2ade, (q15_t)0x8765,
+  (q15_t)0x2ad8, (q15_t)0x8763, (q15_t)0x2ad2, (q15_t)0x8761, (q15_t)0x2acc, (q15_t)0x875e, (q15_t)0x2ac6, (q15_t)0x875c,
+  (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2aba, (q15_t)0x8758, (q15_t)0x2ab4, (q15_t)0x8756, (q15_t)0x2aae, (q15_t)0x8754,
+  (q15_t)0x2aa8, (q15_t)0x8752, (q15_t)0x2aa2, (q15_t)0x8750, (q15_t)0x2a9c, (q15_t)0x874e, (q15_t)0x2a97, (q15_t)0x874c,
+  (q15_t)0x2a91, (q15_t)0x874a, (q15_t)0x2a8b, (q15_t)0x8747, (q15_t)0x2a85, (q15_t)0x8745, (q15_t)0x2a7f, (q15_t)0x8743,
+  (q15_t)0x2a79, (q15_t)0x8741, (q15_t)0x2a73, (q15_t)0x873f, (q15_t)0x2a6d, (q15_t)0x873d, (q15_t)0x2a67, (q15_t)0x873b,
+  (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a5b, (q15_t)0x8737, (q15_t)0x2a55, (q15_t)0x8735, (q15_t)0x2a4f, (q15_t)0x8733,
+  (q15_t)0x2a49, (q15_t)0x8731, (q15_t)0x2a44, (q15_t)0x872e, (q15_t)0x2a3e, (q15_t)0x872c, (q15_t)0x2a38, (q15_t)0x872a,
+  (q15_t)0x2a32, (q15_t)0x8728, (q15_t)0x2a2c, (q15_t)0x8726, (q15_t)0x2a26, (q15_t)0x8724, (q15_t)0x2a20, (q15_t)0x8722,
+  (q15_t)0x2a1a, (q15_t)0x8720, (q15_t)0x2a14, (q15_t)0x871e, (q15_t)0x2a0e, (q15_t)0x871c, (q15_t)0x2a08, (q15_t)0x871a,
+  (q15_t)0x2a02, (q15_t)0x8718, (q15_t)0x29fc, (q15_t)0x8716, (q15_t)0x29f6, (q15_t)0x8714, (q15_t)0x29f0, (q15_t)0x8712,
+  (q15_t)0x29eb, (q15_t)0x870f, (q15_t)0x29e5, (q15_t)0x870d, (q15_t)0x29df, (q15_t)0x870b, (q15_t)0x29d9, (q15_t)0x8709,
+  (q15_t)0x29d3, (q15_t)0x8707, (q15_t)0x29cd, (q15_t)0x8705, (q15_t)0x29c7, (q15_t)0x8703, (q15_t)0x29c1, (q15_t)0x8701,
+  (q15_t)0x29bb, (q15_t)0x86ff, (q15_t)0x29b5, (q15_t)0x86fd, (q15_t)0x29af, (q15_t)0x86fb, (q15_t)0x29a9, (q15_t)0x86f9,
+  (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x299d, (q15_t)0x86f5, (q15_t)0x2997, (q15_t)0x86f3, (q15_t)0x2991, (q15_t)0x86f1,
+  (q15_t)0x298b, (q15_t)0x86ef, (q15_t)0x2986, (q15_t)0x86ed, (q15_t)0x2980, (q15_t)0x86eb, (q15_t)0x297a, (q15_t)0x86e9,
+  (q15_t)0x2974, (q15_t)0x86e7, (q15_t)0x296e, (q15_t)0x86e4, (q15_t)0x2968, (q15_t)0x86e2, (q15_t)0x2962, (q15_t)0x86e0,
+  (q15_t)0x295c, (q15_t)0x86de, (q15_t)0x2956, (q15_t)0x86dc, (q15_t)0x2950, (q15_t)0x86da, (q15_t)0x294a, (q15_t)0x86d8,
+  (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x293e, (q15_t)0x86d4, (q15_t)0x2938, (q15_t)0x86d2, (q15_t)0x2932, (q15_t)0x86d0,
+  (q15_t)0x292c, (q15_t)0x86ce, (q15_t)0x2926, (q15_t)0x86cc, (q15_t)0x2920, (q15_t)0x86ca, (q15_t)0x291b, (q15_t)0x86c8,
+  (q15_t)0x2915, (q15_t)0x86c6, (q15_t)0x290f, (q15_t)0x86c4, (q15_t)0x2909, (q15_t)0x86c2, (q15_t)0x2903, (q15_t)0x86c0,
+  (q15_t)0x28fd, (q15_t)0x86be, (q15_t)0x28f7, (q15_t)0x86bc, (q15_t)0x28f1, (q15_t)0x86ba, (q15_t)0x28eb, (q15_t)0x86b8,
+  (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x28df, (q15_t)0x86b4, (q15_t)0x28d9, (q15_t)0x86b2, (q15_t)0x28d3, (q15_t)0x86b0,
+  (q15_t)0x28cd, (q15_t)0x86ae, (q15_t)0x28c7, (q15_t)0x86ac, (q15_t)0x28c1, (q15_t)0x86aa, (q15_t)0x28bb, (q15_t)0x86a8,
+  (q15_t)0x28b5, (q15_t)0x86a6, (q15_t)0x28af, (q15_t)0x86a4, (q15_t)0x28a9, (q15_t)0x86a2, (q15_t)0x28a3, (q15_t)0x86a0,
+  (q15_t)0x289d, (q15_t)0x869e, (q15_t)0x2898, (q15_t)0x869c, (q15_t)0x2892, (q15_t)0x869a, (q15_t)0x288c, (q15_t)0x8698,
+  (q15_t)0x2886, (q15_t)0x8696, (q15_t)0x2880, (q15_t)0x8694, (q15_t)0x287a, (q15_t)0x8692, (q15_t)0x2874, (q15_t)0x8690,
+  (q15_t)0x286e, (q15_t)0x868e, (q15_t)0x2868, (q15_t)0x868c, (q15_t)0x2862, (q15_t)0x868a, (q15_t)0x285c, (q15_t)0x8688,
+  (q15_t)0x2856, (q15_t)0x8686, (q15_t)0x2850, (q15_t)0x8684, (q15_t)0x284a, (q15_t)0x8682, (q15_t)0x2844, (q15_t)0x8680,
+  (q15_t)0x283e, (q15_t)0x867e, (q15_t)0x2838, (q15_t)0x867c, (q15_t)0x2832, (q15_t)0x867a, (q15_t)0x282c, (q15_t)0x8678,
+  (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x2820, (q15_t)0x8674, (q15_t)0x281a, (q15_t)0x8672, (q15_t)0x2814, (q15_t)0x8670,
+  (q15_t)0x280e, (q15_t)0x866e, (q15_t)0x2808, (q15_t)0x866d, (q15_t)0x2802, (q15_t)0x866b, (q15_t)0x27fc, (q15_t)0x8669,
+  (q15_t)0x27f6, (q15_t)0x8667, (q15_t)0x27f1, (q15_t)0x8665, (q15_t)0x27eb, (q15_t)0x8663, (q15_t)0x27e5, (q15_t)0x8661,
+  (q15_t)0x27df, (q15_t)0x865f, (q15_t)0x27d9, (q15_t)0x865d, (q15_t)0x27d3, (q15_t)0x865b, (q15_t)0x27cd, (q15_t)0x8659,
+  (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x27c1, (q15_t)0x8655, (q15_t)0x27bb, (q15_t)0x8653, (q15_t)0x27b5, (q15_t)0x8651,
+  (q15_t)0x27af, (q15_t)0x864f, (q15_t)0x27a9, (q15_t)0x864d, (q15_t)0x27a3, (q15_t)0x864b, (q15_t)0x279d, (q15_t)0x8649,
+  (q15_t)0x2797, (q15_t)0x8647, (q15_t)0x2791, (q15_t)0x8645, (q15_t)0x278b, (q15_t)0x8644, (q15_t)0x2785, (q15_t)0x8642,
+  (q15_t)0x277f, (q15_t)0x8640, (q15_t)0x2779, (q15_t)0x863e, (q15_t)0x2773, (q15_t)0x863c, (q15_t)0x276d, (q15_t)0x863a,
+  (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x2761, (q15_t)0x8636, (q15_t)0x275b, (q15_t)0x8634, (q15_t)0x2755, (q15_t)0x8632,
+  (q15_t)0x274f, (q15_t)0x8630, (q15_t)0x2749, (q15_t)0x862e, (q15_t)0x2743, (q15_t)0x862c, (q15_t)0x273d, (q15_t)0x862a,
+  (q15_t)0x2737, (q15_t)0x8628, (q15_t)0x2731, (q15_t)0x8627, (q15_t)0x272b, (q15_t)0x8625, (q15_t)0x2725, (q15_t)0x8623,
+  (q15_t)0x271f, (q15_t)0x8621, (q15_t)0x2719, (q15_t)0x861f, (q15_t)0x2713, (q15_t)0x861d, (q15_t)0x270d, (q15_t)0x861b,
+  (q15_t)0x2707, (q15_t)0x8619, (q15_t)0x2701, (q15_t)0x8617, (q15_t)0x26fb, (q15_t)0x8615, (q15_t)0x26f5, (q15_t)0x8613,
+  (q15_t)0x26ef, (q15_t)0x8611, (q15_t)0x26e9, (q15_t)0x8610, (q15_t)0x26e4, (q15_t)0x860e, (q15_t)0x26de, (q15_t)0x860c,
+  (q15_t)0x26d8, (q15_t)0x860a, (q15_t)0x26d2, (q15_t)0x8608, (q15_t)0x26cc, (q15_t)0x8606, (q15_t)0x26c6, (q15_t)0x8604,
+  (q15_t)0x26c0, (q15_t)0x8602, (q15_t)0x26ba, (q15_t)0x8600, (q15_t)0x26b4, (q15_t)0x85fe, (q15_t)0x26ae, (q15_t)0x85fc,
+  (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x26a2, (q15_t)0x85f9, (q15_t)0x269c, (q15_t)0x85f7, (q15_t)0x2696, (q15_t)0x85f5,
+  (q15_t)0x2690, (q15_t)0x85f3, (q15_t)0x268a, (q15_t)0x85f1, (q15_t)0x2684, (q15_t)0x85ef, (q15_t)0x267e, (q15_t)0x85ed,
+  (q15_t)0x2678, (q15_t)0x85eb, (q15_t)0x2672, (q15_t)0x85ea, (q15_t)0x266c, (q15_t)0x85e8, (q15_t)0x2666, (q15_t)0x85e6,
+  (q15_t)0x2660, (q15_t)0x85e4, (q15_t)0x265a, (q15_t)0x85e2, (q15_t)0x2654, (q15_t)0x85e0, (q15_t)0x264e, (q15_t)0x85de,
+  (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x2642, (q15_t)0x85da, (q15_t)0x263c, (q15_t)0x85d9, (q15_t)0x2636, (q15_t)0x85d7,
+  (q15_t)0x2630, (q15_t)0x85d5, (q15_t)0x262a, (q15_t)0x85d3, (q15_t)0x2624, (q15_t)0x85d1, (q15_t)0x261e, (q15_t)0x85cf,
+  (q15_t)0x2618, (q15_t)0x85cd, (q15_t)0x2612, (q15_t)0x85cb, (q15_t)0x260c, (q15_t)0x85ca, (q15_t)0x2606, (q15_t)0x85c8,
+  (q15_t)0x2600, (q15_t)0x85c6, (q15_t)0x25fa, (q15_t)0x85c4, (q15_t)0x25f4, (q15_t)0x85c2, (q15_t)0x25ee, (q15_t)0x85c0,
+  (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x25e2, (q15_t)0x85bd, (q15_t)0x25dc, (q15_t)0x85bb, (q15_t)0x25d6, (q15_t)0x85b9,
+  (q15_t)0x25d0, (q15_t)0x85b7, (q15_t)0x25ca, (q15_t)0x85b5, (q15_t)0x25c4, (q15_t)0x85b3, (q15_t)0x25be, (q15_t)0x85b1,
+  (q15_t)0x25b8, (q15_t)0x85b0, (q15_t)0x25b2, (q15_t)0x85ae, (q15_t)0x25ac, (q15_t)0x85ac, (q15_t)0x25a6, (q15_t)0x85aa,
+  (q15_t)0x25a0, (q15_t)0x85a8, (q15_t)0x259a, (q15_t)0x85a6, (q15_t)0x2594, (q15_t)0x85a4, (q15_t)0x258e, (q15_t)0x85a3,
+  (q15_t)0x2588, (q15_t)0x85a1, (q15_t)0x2582, (q15_t)0x859f, (q15_t)0x257c, (q15_t)0x859d, (q15_t)0x2576, (q15_t)0x859b,
+  (q15_t)0x2570, (q15_t)0x8599, (q15_t)0x256a, (q15_t)0x8598, (q15_t)0x2564, (q15_t)0x8596, (q15_t)0x255e, (q15_t)0x8594,
+  (q15_t)0x2558, (q15_t)0x8592, (q15_t)0x2552, (q15_t)0x8590, (q15_t)0x254c, (q15_t)0x858e, (q15_t)0x2546, (q15_t)0x858d,
+  (q15_t)0x2540, (q15_t)0x858b, (q15_t)0x253a, (q15_t)0x8589, (q15_t)0x2534, (q15_t)0x8587, (q15_t)0x252e, (q15_t)0x8585,
+  (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x2522, (q15_t)0x8582, (q15_t)0x251c, (q15_t)0x8580, (q15_t)0x2516, (q15_t)0x857e,
+  (q15_t)0x250f, (q15_t)0x857c, (q15_t)0x2509, (q15_t)0x857a, (q15_t)0x2503, (q15_t)0x8579, (q15_t)0x24fd, (q15_t)0x8577,
+  (q15_t)0x24f7, (q15_t)0x8575, (q15_t)0x24f1, (q15_t)0x8573, (q15_t)0x24eb, (q15_t)0x8571, (q15_t)0x24e5, (q15_t)0x856f,
+  (q15_t)0x24df, (q15_t)0x856e, (q15_t)0x24d9, (q15_t)0x856c, (q15_t)0x24d3, (q15_t)0x856a, (q15_t)0x24cd, (q15_t)0x8568,
+  (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x24c1, (q15_t)0x8565, (q15_t)0x24bb, (q15_t)0x8563, (q15_t)0x24b5, (q15_t)0x8561,
+  (q15_t)0x24af, (q15_t)0x855f, (q15_t)0x24a9, (q15_t)0x855d, (q15_t)0x24a3, (q15_t)0x855c, (q15_t)0x249d, (q15_t)0x855a,
+  (q15_t)0x2497, (q15_t)0x8558, (q15_t)0x2491, (q15_t)0x8556, (q15_t)0x248b, (q15_t)0x8554, (q15_t)0x2485, (q15_t)0x8553,
+  (q15_t)0x247f, (q15_t)0x8551, (q15_t)0x2479, (q15_t)0x854f, (q15_t)0x2473, (q15_t)0x854d, (q15_t)0x246d, (q15_t)0x854b,
+  (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x2461, (q15_t)0x8548, (q15_t)0x245b, (q15_t)0x8546, (q15_t)0x2455, (q15_t)0x8544,
+  (q15_t)0x244f, (q15_t)0x8543, (q15_t)0x2449, (q15_t)0x8541, (q15_t)0x2443, (q15_t)0x853f, (q15_t)0x243d, (q15_t)0x853d,
+  (q15_t)0x2437, (q15_t)0x853b, (q15_t)0x2431, (q15_t)0x853a, (q15_t)0x242b, (q15_t)0x8538, (q15_t)0x2425, (q15_t)0x8536,
+  (q15_t)0x241f, (q15_t)0x8534, (q15_t)0x2419, (q15_t)0x8533, (q15_t)0x2413, (q15_t)0x8531, (q15_t)0x240d, (q15_t)0x852f,
+  (q15_t)0x2407, (q15_t)0x852d, (q15_t)0x2401, (q15_t)0x852b, (q15_t)0x23fa, (q15_t)0x852a, (q15_t)0x23f4, (q15_t)0x8528,
+  (q15_t)0x23ee, (q15_t)0x8526, (q15_t)0x23e8, (q15_t)0x8524, (q15_t)0x23e2, (q15_t)0x8523, (q15_t)0x23dc, (q15_t)0x8521,
+  (q15_t)0x23d6, (q15_t)0x851f, (q15_t)0x23d0, (q15_t)0x851d, (q15_t)0x23ca, (q15_t)0x851c, (q15_t)0x23c4, (q15_t)0x851a,
+  (q15_t)0x23be, (q15_t)0x8518, (q15_t)0x23b8, (q15_t)0x8516, (q15_t)0x23b2, (q15_t)0x8515, (q15_t)0x23ac, (q15_t)0x8513,
+  (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x23a0, (q15_t)0x850f, (q15_t)0x239a, (q15_t)0x850e, (q15_t)0x2394, (q15_t)0x850c,
+  (q15_t)0x238e, (q15_t)0x850a, (q15_t)0x2388, (q15_t)0x8508, (q15_t)0x2382, (q15_t)0x8507, (q15_t)0x237c, (q15_t)0x8505,
+  (q15_t)0x2376, (q15_t)0x8503, (q15_t)0x2370, (q15_t)0x8501, (q15_t)0x236a, (q15_t)0x8500, (q15_t)0x2364, (q15_t)0x84fe,
+  (q15_t)0x235e, (q15_t)0x84fc, (q15_t)0x2358, (q15_t)0x84fa, (q15_t)0x2352, (q15_t)0x84f9, (q15_t)0x234b, (q15_t)0x84f7,
+  (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x233f, (q15_t)0x84f4, (q15_t)0x2339, (q15_t)0x84f2, (q15_t)0x2333, (q15_t)0x84f0,
+  (q15_t)0x232d, (q15_t)0x84ee, (q15_t)0x2327, (q15_t)0x84ed, (q15_t)0x2321, (q15_t)0x84eb, (q15_t)0x231b, (q15_t)0x84e9,
+  (q15_t)0x2315, (q15_t)0x84e7, (q15_t)0x230f, (q15_t)0x84e6, (q15_t)0x2309, (q15_t)0x84e4, (q15_t)0x2303, (q15_t)0x84e2,
+  (q15_t)0x22fd, (q15_t)0x84e1, (q15_t)0x22f7, (q15_t)0x84df, (q15_t)0x22f1, (q15_t)0x84dd, (q15_t)0x22eb, (q15_t)0x84db,
+  (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x22df, (q15_t)0x84d8, (q15_t)0x22d9, (q15_t)0x84d6, (q15_t)0x22d3, (q15_t)0x84d5,
+  (q15_t)0x22cd, (q15_t)0x84d3, (q15_t)0x22c7, (q15_t)0x84d1, (q15_t)0x22c0, (q15_t)0x84cf, (q15_t)0x22ba, (q15_t)0x84ce,
+  (q15_t)0x22b4, (q15_t)0x84cc, (q15_t)0x22ae, (q15_t)0x84ca, (q15_t)0x22a8, (q15_t)0x84c9, (q15_t)0x22a2, (q15_t)0x84c7,
+  (q15_t)0x229c, (q15_t)0x84c5, (q15_t)0x2296, (q15_t)0x84c4, (q15_t)0x2290, (q15_t)0x84c2, (q15_t)0x228a, (q15_t)0x84c0,
+  (q15_t)0x2284, (q15_t)0x84be, (q15_t)0x227e, (q15_t)0x84bd, (q15_t)0x2278, (q15_t)0x84bb, (q15_t)0x2272, (q15_t)0x84b9,
+  (q15_t)0x226c, (q15_t)0x84b8, (q15_t)0x2266, (q15_t)0x84b6, (q15_t)0x2260, (q15_t)0x84b4, (q15_t)0x225a, (q15_t)0x84b3,
+  (q15_t)0x2254, (q15_t)0x84b1, (q15_t)0x224e, (q15_t)0x84af, (q15_t)0x2247, (q15_t)0x84ae, (q15_t)0x2241, (q15_t)0x84ac,
+  (q15_t)0x223b, (q15_t)0x84aa, (q15_t)0x2235, (q15_t)0x84a9, (q15_t)0x222f, (q15_t)0x84a7, (q15_t)0x2229, (q15_t)0x84a5,
+  (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x221d, (q15_t)0x84a2, (q15_t)0x2217, (q15_t)0x84a0, (q15_t)0x2211, (q15_t)0x849e,
+  (q15_t)0x220b, (q15_t)0x849d, (q15_t)0x2205, (q15_t)0x849b, (q15_t)0x21ff, (q15_t)0x8499, (q15_t)0x21f9, (q15_t)0x8498,
+  (q15_t)0x21f3, (q15_t)0x8496, (q15_t)0x21ed, (q15_t)0x8494, (q15_t)0x21e7, (q15_t)0x8493, (q15_t)0x21e1, (q15_t)0x8491,
+  (q15_t)0x21da, (q15_t)0x848f, (q15_t)0x21d4, (q15_t)0x848e, (q15_t)0x21ce, (q15_t)0x848c, (q15_t)0x21c8, (q15_t)0x848a,
+  (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x21bc, (q15_t)0x8487, (q15_t)0x21b6, (q15_t)0x8486, (q15_t)0x21b0, (q15_t)0x8484,
+  (q15_t)0x21aa, (q15_t)0x8482, (q15_t)0x21a4, (q15_t)0x8481, (q15_t)0x219e, (q15_t)0x847f, (q15_t)0x2198, (q15_t)0x847d,
+  (q15_t)0x2192, (q15_t)0x847c, (q15_t)0x218c, (q15_t)0x847a, (q15_t)0x2186, (q15_t)0x8478, (q15_t)0x2180, (q15_t)0x8477,
+  (q15_t)0x2179, (q15_t)0x8475, (q15_t)0x2173, (q15_t)0x8473, (q15_t)0x216d, (q15_t)0x8472, (q15_t)0x2167, (q15_t)0x8470,
+  (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x215b, (q15_t)0x846d, (q15_t)0x2155, (q15_t)0x846b, (q15_t)0x214f, (q15_t)0x846a,
+  (q15_t)0x2149, (q15_t)0x8468, (q15_t)0x2143, (q15_t)0x8466, (q15_t)0x213d, (q15_t)0x8465, (q15_t)0x2137, (q15_t)0x8463,
+  (q15_t)0x2131, (q15_t)0x8461, (q15_t)0x212b, (q15_t)0x8460, (q15_t)0x2125, (q15_t)0x845e, (q15_t)0x211e, (q15_t)0x845d,
+  (q15_t)0x2118, (q15_t)0x845b, (q15_t)0x2112, (q15_t)0x8459, (q15_t)0x210c, (q15_t)0x8458, (q15_t)0x2106, (q15_t)0x8456,
+  (q15_t)0x2100, (q15_t)0x8454, (q15_t)0x20fa, (q15_t)0x8453, (q15_t)0x20f4, (q15_t)0x8451, (q15_t)0x20ee, (q15_t)0x8450,
+  (q15_t)0x20e8, (q15_t)0x844e, (q15_t)0x20e2, (q15_t)0x844c, (q15_t)0x20dc, (q15_t)0x844b, (q15_t)0x20d6, (q15_t)0x8449,
+  (q15_t)0x20d0, (q15_t)0x8447, (q15_t)0x20c9, (q15_t)0x8446, (q15_t)0x20c3, (q15_t)0x8444, (q15_t)0x20bd, (q15_t)0x8443,
+  (q15_t)0x20b7, (q15_t)0x8441, (q15_t)0x20b1, (q15_t)0x843f, (q15_t)0x20ab, (q15_t)0x843e, (q15_t)0x20a5, (q15_t)0x843c,
+  (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x2099, (q15_t)0x8439, (q15_t)0x2093, (q15_t)0x8437, (q15_t)0x208d, (q15_t)0x8436,
+  (q15_t)0x2087, (q15_t)0x8434, (q15_t)0x2081, (q15_t)0x8433, (q15_t)0x207a, (q15_t)0x8431, (q15_t)0x2074, (q15_t)0x842f,
+  (q15_t)0x206e, (q15_t)0x842e, (q15_t)0x2068, (q15_t)0x842c, (q15_t)0x2062, (q15_t)0x842b, (q15_t)0x205c, (q15_t)0x8429,
+  (q15_t)0x2056, (q15_t)0x8427, (q15_t)0x2050, (q15_t)0x8426, (q15_t)0x204a, (q15_t)0x8424, (q15_t)0x2044, (q15_t)0x8423,
+  (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x2038, (q15_t)0x8420, (q15_t)0x2032, (q15_t)0x841e, (q15_t)0x202b, (q15_t)0x841c,
+  (q15_t)0x2025, (q15_t)0x841b, (q15_t)0x201f, (q15_t)0x8419, (q15_t)0x2019, (q15_t)0x8418, (q15_t)0x2013, (q15_t)0x8416,
+  (q15_t)0x200d, (q15_t)0x8415, (q15_t)0x2007, (q15_t)0x8413, (q15_t)0x2001, (q15_t)0x8411, (q15_t)0x1ffb, (q15_t)0x8410,
+  (q15_t)0x1ff5, (q15_t)0x840e, (q15_t)0x1fef, (q15_t)0x840d, (q15_t)0x1fe9, (q15_t)0x840b, (q15_t)0x1fe2, (q15_t)0x840a,
+  (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1fd6, (q15_t)0x8406, (q15_t)0x1fd0, (q15_t)0x8405, (q15_t)0x1fca, (q15_t)0x8403,
+  (q15_t)0x1fc4, (q15_t)0x8402, (q15_t)0x1fbe, (q15_t)0x8400, (q15_t)0x1fb8, (q15_t)0x83ff, (q15_t)0x1fb2, (q15_t)0x83fd,
+  (q15_t)0x1fac, (q15_t)0x83fb, (q15_t)0x1fa6, (q15_t)0x83fa, (q15_t)0x1f9f, (q15_t)0x83f8, (q15_t)0x1f99, (q15_t)0x83f7,
+  (q15_t)0x1f93, (q15_t)0x83f5, (q15_t)0x1f8d, (q15_t)0x83f4, (q15_t)0x1f87, (q15_t)0x83f2, (q15_t)0x1f81, (q15_t)0x83f1,
+  (q15_t)0x1f7b, (q15_t)0x83ef, (q15_t)0x1f75, (q15_t)0x83ee, (q15_t)0x1f6f, (q15_t)0x83ec, (q15_t)0x1f69, (q15_t)0x83ea,
+  (q15_t)0x1f63, (q15_t)0x83e9, (q15_t)0x1f5d, (q15_t)0x83e7, (q15_t)0x1f56, (q15_t)0x83e6, (q15_t)0x1f50, (q15_t)0x83e4,
+  (q15_t)0x1f4a, (q15_t)0x83e3, (q15_t)0x1f44, (q15_t)0x83e1, (q15_t)0x1f3e, (q15_t)0x83e0, (q15_t)0x1f38, (q15_t)0x83de,
+  (q15_t)0x1f32, (q15_t)0x83dd, (q15_t)0x1f2c, (q15_t)0x83db, (q15_t)0x1f26, (q15_t)0x83da, (q15_t)0x1f20, (q15_t)0x83d8,
+  (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1f13, (q15_t)0x83d5, (q15_t)0x1f0d, (q15_t)0x83d3, (q15_t)0x1f07, (q15_t)0x83d2,
+  (q15_t)0x1f01, (q15_t)0x83d0, (q15_t)0x1efb, (q15_t)0x83cf, (q15_t)0x1ef5, (q15_t)0x83cd, (q15_t)0x1eef, (q15_t)0x83cc,
+  (q15_t)0x1ee9, (q15_t)0x83ca, (q15_t)0x1ee3, (q15_t)0x83c9, (q15_t)0x1edd, (q15_t)0x83c7, (q15_t)0x1ed6, (q15_t)0x83c6,
+  (q15_t)0x1ed0, (q15_t)0x83c4, (q15_t)0x1eca, (q15_t)0x83c3, (q15_t)0x1ec4, (q15_t)0x83c1, (q15_t)0x1ebe, (q15_t)0x83c0,
+  (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1eb2, (q15_t)0x83bd, (q15_t)0x1eac, (q15_t)0x83bb, (q15_t)0x1ea6, (q15_t)0x83ba,
+  (q15_t)0x1ea0, (q15_t)0x83b8, (q15_t)0x1e99, (q15_t)0x83b7, (q15_t)0x1e93, (q15_t)0x83b5, (q15_t)0x1e8d, (q15_t)0x83b4,
+  (q15_t)0x1e87, (q15_t)0x83b2, (q15_t)0x1e81, (q15_t)0x83b1, (q15_t)0x1e7b, (q15_t)0x83af, (q15_t)0x1e75, (q15_t)0x83ae,
+  (q15_t)0x1e6f, (q15_t)0x83ac, (q15_t)0x1e69, (q15_t)0x83ab, (q15_t)0x1e62, (q15_t)0x83a9, (q15_t)0x1e5c, (q15_t)0x83a8,
+  (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1e50, (q15_t)0x83a5, (q15_t)0x1e4a, (q15_t)0x83a3, (q15_t)0x1e44, (q15_t)0x83a2,
+  (q15_t)0x1e3e, (q15_t)0x83a0, (q15_t)0x1e38, (q15_t)0x839f, (q15_t)0x1e32, (q15_t)0x839d, (q15_t)0x1e2c, (q15_t)0x839c,
+  (q15_t)0x1e25, (q15_t)0x839a, (q15_t)0x1e1f, (q15_t)0x8399, (q15_t)0x1e19, (q15_t)0x8397, (q15_t)0x1e13, (q15_t)0x8396,
+  (q15_t)0x1e0d, (q15_t)0x8394, (q15_t)0x1e07, (q15_t)0x8393, (q15_t)0x1e01, (q15_t)0x8392, (q15_t)0x1dfb, (q15_t)0x8390,
+  (q15_t)0x1df5, (q15_t)0x838f, (q15_t)0x1dee, (q15_t)0x838d, (q15_t)0x1de8, (q15_t)0x838c, (q15_t)0x1de2, (q15_t)0x838a,
+  (q15_t)0x1ddc, (q15_t)0x8389, (q15_t)0x1dd6, (q15_t)0x8387, (q15_t)0x1dd0, (q15_t)0x8386, (q15_t)0x1dca, (q15_t)0x8384,
+  (q15_t)0x1dc4, (q15_t)0x8383, (q15_t)0x1dbe, (q15_t)0x8381, (q15_t)0x1db7, (q15_t)0x8380, (q15_t)0x1db1, (q15_t)0x837e,
+  (q15_t)0x1dab, (q15_t)0x837d, (q15_t)0x1da5, (q15_t)0x837c, (q15_t)0x1d9f, (q15_t)0x837a, (q15_t)0x1d99, (q15_t)0x8379,
+  (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d8d, (q15_t)0x8376, (q15_t)0x1d87, (q15_t)0x8374, (q15_t)0x1d80, (q15_t)0x8373,
+  (q15_t)0x1d7a, (q15_t)0x8371, (q15_t)0x1d74, (q15_t)0x8370, (q15_t)0x1d6e, (q15_t)0x836f, (q15_t)0x1d68, (q15_t)0x836d,
+  (q15_t)0x1d62, (q15_t)0x836c, (q15_t)0x1d5c, (q15_t)0x836a, (q15_t)0x1d56, (q15_t)0x8369, (q15_t)0x1d50, (q15_t)0x8367,
+  (q15_t)0x1d49, (q15_t)0x8366, (q15_t)0x1d43, (q15_t)0x8364, (q15_t)0x1d3d, (q15_t)0x8363, (q15_t)0x1d37, (q15_t)0x8362,
+  (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1d2b, (q15_t)0x835f, (q15_t)0x1d25, (q15_t)0x835d, (q15_t)0x1d1f, (q15_t)0x835c,
+  (q15_t)0x1d18, (q15_t)0x835a, (q15_t)0x1d12, (q15_t)0x8359, (q15_t)0x1d0c, (q15_t)0x8358, (q15_t)0x1d06, (q15_t)0x8356,
+  (q15_t)0x1d00, (q15_t)0x8355, (q15_t)0x1cfa, (q15_t)0x8353, (q15_t)0x1cf4, (q15_t)0x8352, (q15_t)0x1cee, (q15_t)0x8350,
+  (q15_t)0x1ce8, (q15_t)0x834f, (q15_t)0x1ce1, (q15_t)0x834e, (q15_t)0x1cdb, (q15_t)0x834c, (q15_t)0x1cd5, (q15_t)0x834b,
+  (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1cc9, (q15_t)0x8348, (q15_t)0x1cc3, (q15_t)0x8347, (q15_t)0x1cbd, (q15_t)0x8345,
+  (q15_t)0x1cb7, (q15_t)0x8344, (q15_t)0x1cb0, (q15_t)0x8342, (q15_t)0x1caa, (q15_t)0x8341, (q15_t)0x1ca4, (q15_t)0x833f,
+  (q15_t)0x1c9e, (q15_t)0x833e, (q15_t)0x1c98, (q15_t)0x833d, (q15_t)0x1c92, (q15_t)0x833b, (q15_t)0x1c8c, (q15_t)0x833a,
+  (q15_t)0x1c86, (q15_t)0x8338, (q15_t)0x1c7f, (q15_t)0x8337, (q15_t)0x1c79, (q15_t)0x8336, (q15_t)0x1c73, (q15_t)0x8334,
+  (q15_t)0x1c6d, (q15_t)0x8333, (q15_t)0x1c67, (q15_t)0x8331, (q15_t)0x1c61, (q15_t)0x8330, (q15_t)0x1c5b, (q15_t)0x832f,
+  (q15_t)0x1c55, (q15_t)0x832d, (q15_t)0x1c4e, (q15_t)0x832c, (q15_t)0x1c48, (q15_t)0x832b, (q15_t)0x1c42, (q15_t)0x8329,
+  (q15_t)0x1c3c, (q15_t)0x8328, (q15_t)0x1c36, (q15_t)0x8326, (q15_t)0x1c30, (q15_t)0x8325, (q15_t)0x1c2a, (q15_t)0x8324,
+  (q15_t)0x1c24, (q15_t)0x8322, (q15_t)0x1c1d, (q15_t)0x8321, (q15_t)0x1c17, (q15_t)0x831f, (q15_t)0x1c11, (q15_t)0x831e,
+  (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1c05, (q15_t)0x831b, (q15_t)0x1bff, (q15_t)0x831a, (q15_t)0x1bf9, (q15_t)0x8319,
+  (q15_t)0x1bf2, (q15_t)0x8317, (q15_t)0x1bec, (q15_t)0x8316, (q15_t)0x1be6, (q15_t)0x8314, (q15_t)0x1be0, (q15_t)0x8313,
+  (q15_t)0x1bda, (q15_t)0x8312, (q15_t)0x1bd4, (q15_t)0x8310, (q15_t)0x1bce, (q15_t)0x830f, (q15_t)0x1bc8, (q15_t)0x830e,
+  (q15_t)0x1bc1, (q15_t)0x830c, (q15_t)0x1bbb, (q15_t)0x830b, (q15_t)0x1bb5, (q15_t)0x830a, (q15_t)0x1baf, (q15_t)0x8308,
+  (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1ba3, (q15_t)0x8305, (q15_t)0x1b9d, (q15_t)0x8304, (q15_t)0x1b96, (q15_t)0x8303,
+  (q15_t)0x1b90, (q15_t)0x8301, (q15_t)0x1b8a, (q15_t)0x8300, (q15_t)0x1b84, (q15_t)0x82ff, (q15_t)0x1b7e, (q15_t)0x82fd,
+  (q15_t)0x1b78, (q15_t)0x82fc, (q15_t)0x1b72, (q15_t)0x82fb, (q15_t)0x1b6c, (q15_t)0x82f9, (q15_t)0x1b65, (q15_t)0x82f8,
+  (q15_t)0x1b5f, (q15_t)0x82f7, (q15_t)0x1b59, (q15_t)0x82f5, (q15_t)0x1b53, (q15_t)0x82f4, (q15_t)0x1b4d, (q15_t)0x82f3,
+  (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1b41, (q15_t)0x82f0, (q15_t)0x1b3a, (q15_t)0x82ef, (q15_t)0x1b34, (q15_t)0x82ed,
+  (q15_t)0x1b2e, (q15_t)0x82ec, (q15_t)0x1b28, (q15_t)0x82eb, (q15_t)0x1b22, (q15_t)0x82e9, (q15_t)0x1b1c, (q15_t)0x82e8,
+  (q15_t)0x1b16, (q15_t)0x82e7, (q15_t)0x1b0f, (q15_t)0x82e5, (q15_t)0x1b09, (q15_t)0x82e4, (q15_t)0x1b03, (q15_t)0x82e3,
+  (q15_t)0x1afd, (q15_t)0x82e1, (q15_t)0x1af7, (q15_t)0x82e0, (q15_t)0x1af1, (q15_t)0x82df, (q15_t)0x1aeb, (q15_t)0x82dd,
+  (q15_t)0x1ae4, (q15_t)0x82dc, (q15_t)0x1ade, (q15_t)0x82db, (q15_t)0x1ad8, (q15_t)0x82d9, (q15_t)0x1ad2, (q15_t)0x82d8,
+  (q15_t)0x1acc, (q15_t)0x82d7, (q15_t)0x1ac6, (q15_t)0x82d5, (q15_t)0x1ac0, (q15_t)0x82d4, (q15_t)0x1ab9, (q15_t)0x82d3,
+  (q15_t)0x1ab3, (q15_t)0x82d1, (q15_t)0x1aad, (q15_t)0x82d0, (q15_t)0x1aa7, (q15_t)0x82cf, (q15_t)0x1aa1, (q15_t)0x82ce,
+  (q15_t)0x1a9b, (q15_t)0x82cc, (q15_t)0x1a95, (q15_t)0x82cb, (q15_t)0x1a8e, (q15_t)0x82ca, (q15_t)0x1a88, (q15_t)0x82c8,
+  (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a7c, (q15_t)0x82c6, (q15_t)0x1a76, (q15_t)0x82c4, (q15_t)0x1a70, (q15_t)0x82c3,
+  (q15_t)0x1a6a, (q15_t)0x82c2, (q15_t)0x1a63, (q15_t)0x82c1, (q15_t)0x1a5d, (q15_t)0x82bf, (q15_t)0x1a57, (q15_t)0x82be,
+  (q15_t)0x1a51, (q15_t)0x82bd, (q15_t)0x1a4b, (q15_t)0x82bb, (q15_t)0x1a45, (q15_t)0x82ba, (q15_t)0x1a3e, (q15_t)0x82b9,
+  (q15_t)0x1a38, (q15_t)0x82b7, (q15_t)0x1a32, (q15_t)0x82b6, (q15_t)0x1a2c, (q15_t)0x82b5, (q15_t)0x1a26, (q15_t)0x82b4,
+  (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x1a1a, (q15_t)0x82b1, (q15_t)0x1a13, (q15_t)0x82b0, (q15_t)0x1a0d, (q15_t)0x82ae,
+  (q15_t)0x1a07, (q15_t)0x82ad, (q15_t)0x1a01, (q15_t)0x82ac, (q15_t)0x19fb, (q15_t)0x82ab, (q15_t)0x19f5, (q15_t)0x82a9,
+  (q15_t)0x19ef, (q15_t)0x82a8, (q15_t)0x19e8, (q15_t)0x82a7, (q15_t)0x19e2, (q15_t)0x82a6, (q15_t)0x19dc, (q15_t)0x82a4,
+  (q15_t)0x19d6, (q15_t)0x82a3, (q15_t)0x19d0, (q15_t)0x82a2, (q15_t)0x19ca, (q15_t)0x82a0, (q15_t)0x19c3, (q15_t)0x829f,
+  (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x19b7, (q15_t)0x829d, (q15_t)0x19b1, (q15_t)0x829b, (q15_t)0x19ab, (q15_t)0x829a,
+  (q15_t)0x19a5, (q15_t)0x8299, (q15_t)0x199f, (q15_t)0x8298, (q15_t)0x1998, (q15_t)0x8296, (q15_t)0x1992, (q15_t)0x8295,
+  (q15_t)0x198c, (q15_t)0x8294, (q15_t)0x1986, (q15_t)0x8293, (q15_t)0x1980, (q15_t)0x8291, (q15_t)0x197a, (q15_t)0x8290,
+  (q15_t)0x1973, (q15_t)0x828f, (q15_t)0x196d, (q15_t)0x828e, (q15_t)0x1967, (q15_t)0x828c, (q15_t)0x1961, (q15_t)0x828b,
+  (q15_t)0x195b, (q15_t)0x828a, (q15_t)0x1955, (q15_t)0x8289, (q15_t)0x194e, (q15_t)0x8287, (q15_t)0x1948, (q15_t)0x8286,
+  (q15_t)0x1942, (q15_t)0x8285, (q15_t)0x193c, (q15_t)0x8284, (q15_t)0x1936, (q15_t)0x8282, (q15_t)0x1930, (q15_t)0x8281,
+  (q15_t)0x192a, (q15_t)0x8280, (q15_t)0x1923, (q15_t)0x827f, (q15_t)0x191d, (q15_t)0x827e, (q15_t)0x1917, (q15_t)0x827c,
+  (q15_t)0x1911, (q15_t)0x827b, (q15_t)0x190b, (q15_t)0x827a, (q15_t)0x1905, (q15_t)0x8279, (q15_t)0x18fe, (q15_t)0x8277,
+  (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x18f2, (q15_t)0x8275, (q15_t)0x18ec, (q15_t)0x8274, (q15_t)0x18e6, (q15_t)0x8272,
+  (q15_t)0x18e0, (q15_t)0x8271, (q15_t)0x18d9, (q15_t)0x8270, (q15_t)0x18d3, (q15_t)0x826f, (q15_t)0x18cd, (q15_t)0x826e,
+  (q15_t)0x18c7, (q15_t)0x826c, (q15_t)0x18c1, (q15_t)0x826b, (q15_t)0x18bb, (q15_t)0x826a, (q15_t)0x18b4, (q15_t)0x8269,
+  (q15_t)0x18ae, (q15_t)0x8268, (q15_t)0x18a8, (q15_t)0x8266, (q15_t)0x18a2, (q15_t)0x8265, (q15_t)0x189c, (q15_t)0x8264,
+  (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x188f, (q15_t)0x8261, (q15_t)0x1889, (q15_t)0x8260, (q15_t)0x1883, (q15_t)0x825f,
+  (q15_t)0x187d, (q15_t)0x825e, (q15_t)0x1877, (q15_t)0x825d, (q15_t)0x1871, (q15_t)0x825b, (q15_t)0x186a, (q15_t)0x825a,
+  (q15_t)0x1864, (q15_t)0x8259, (q15_t)0x185e, (q15_t)0x8258, (q15_t)0x1858, (q15_t)0x8257, (q15_t)0x1852, (q15_t)0x8255,
+  (q15_t)0x184c, (q15_t)0x8254, (q15_t)0x1845, (q15_t)0x8253, (q15_t)0x183f, (q15_t)0x8252, (q15_t)0x1839, (q15_t)0x8251,
+  (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x182d, (q15_t)0x824e, (q15_t)0x1827, (q15_t)0x824d, (q15_t)0x1820, (q15_t)0x824c,
+  (q15_t)0x181a, (q15_t)0x824b, (q15_t)0x1814, (q15_t)0x824a, (q15_t)0x180e, (q15_t)0x8248, (q15_t)0x1808, (q15_t)0x8247,
+  (q15_t)0x1802, (q15_t)0x8246, (q15_t)0x17fb, (q15_t)0x8245, (q15_t)0x17f5, (q15_t)0x8244, (q15_t)0x17ef, (q15_t)0x8243,
+  (q15_t)0x17e9, (q15_t)0x8241, (q15_t)0x17e3, (q15_t)0x8240, (q15_t)0x17dd, (q15_t)0x823f, (q15_t)0x17d6, (q15_t)0x823e,
+  (q15_t)0x17d0, (q15_t)0x823d, (q15_t)0x17ca, (q15_t)0x823b, (q15_t)0x17c4, (q15_t)0x823a, (q15_t)0x17be, (q15_t)0x8239,
+  (q15_t)0x17b7, (q15_t)0x8238, (q15_t)0x17b1, (q15_t)0x8237, (q15_t)0x17ab, (q15_t)0x8236, (q15_t)0x17a5, (q15_t)0x8234,
+  (q15_t)0x179f, (q15_t)0x8233, (q15_t)0x1799, (q15_t)0x8232, (q15_t)0x1792, (q15_t)0x8231, (q15_t)0x178c, (q15_t)0x8230,
+  (q15_t)0x1786, (q15_t)0x822f, (q15_t)0x1780, (q15_t)0x822e, (q15_t)0x177a, (q15_t)0x822c, (q15_t)0x1774, (q15_t)0x822b,
+  (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x1767, (q15_t)0x8229, (q15_t)0x1761, (q15_t)0x8228, (q15_t)0x175b, (q15_t)0x8227,
+  (q15_t)0x1755, (q15_t)0x8226, (q15_t)0x174e, (q15_t)0x8224, (q15_t)0x1748, (q15_t)0x8223, (q15_t)0x1742, (q15_t)0x8222,
+  (q15_t)0x173c, (q15_t)0x8221, (q15_t)0x1736, (q15_t)0x8220, (q15_t)0x1730, (q15_t)0x821f, (q15_t)0x1729, (q15_t)0x821e,
+  (q15_t)0x1723, (q15_t)0x821c, (q15_t)0x171d, (q15_t)0x821b, (q15_t)0x1717, (q15_t)0x821a, (q15_t)0x1711, (q15_t)0x8219,
+  (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x1704, (q15_t)0x8217, (q15_t)0x16fe, (q15_t)0x8216, (q15_t)0x16f8, (q15_t)0x8214,
+  (q15_t)0x16f2, (q15_t)0x8213, (q15_t)0x16ec, (q15_t)0x8212, (q15_t)0x16e5, (q15_t)0x8211, (q15_t)0x16df, (q15_t)0x8210,
+  (q15_t)0x16d9, (q15_t)0x820f, (q15_t)0x16d3, (q15_t)0x820e, (q15_t)0x16cd, (q15_t)0x820d, (q15_t)0x16c6, (q15_t)0x820b,
+  (q15_t)0x16c0, (q15_t)0x820a, (q15_t)0x16ba, (q15_t)0x8209, (q15_t)0x16b4, (q15_t)0x8208, (q15_t)0x16ae, (q15_t)0x8207,
+  (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x16a1, (q15_t)0x8205, (q15_t)0x169b, (q15_t)0x8204, (q15_t)0x1695, (q15_t)0x8203,
+  (q15_t)0x168f, (q15_t)0x8201, (q15_t)0x1689, (q15_t)0x8200, (q15_t)0x1682, (q15_t)0x81ff, (q15_t)0x167c, (q15_t)0x81fe,
+  (q15_t)0x1676, (q15_t)0x81fd, (q15_t)0x1670, (q15_t)0x81fc, (q15_t)0x166a, (q15_t)0x81fb, (q15_t)0x1664, (q15_t)0x81fa,
+  (q15_t)0x165d, (q15_t)0x81f9, (q15_t)0x1657, (q15_t)0x81f8, (q15_t)0x1651, (q15_t)0x81f6, (q15_t)0x164b, (q15_t)0x81f5,
+  (q15_t)0x1645, (q15_t)0x81f4, (q15_t)0x163e, (q15_t)0x81f3, (q15_t)0x1638, (q15_t)0x81f2, (q15_t)0x1632, (q15_t)0x81f1,
+  (q15_t)0x162c, (q15_t)0x81f0, (q15_t)0x1626, (q15_t)0x81ef, (q15_t)0x161f, (q15_t)0x81ee, (q15_t)0x1619, (q15_t)0x81ed,
+  (q15_t)0x1613, (q15_t)0x81ec, (q15_t)0x160d, (q15_t)0x81ea, (q15_t)0x1607, (q15_t)0x81e9, (q15_t)0x1601, (q15_t)0x81e8,
+  (q15_t)0x15fa, (q15_t)0x81e7, (q15_t)0x15f4, (q15_t)0x81e6, (q15_t)0x15ee, (q15_t)0x81e5, (q15_t)0x15e8, (q15_t)0x81e4,
+  (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x15db, (q15_t)0x81e2, (q15_t)0x15d5, (q15_t)0x81e1, (q15_t)0x15cf, (q15_t)0x81e0,
+  (q15_t)0x15c9, (q15_t)0x81df, (q15_t)0x15c3, (q15_t)0x81de, (q15_t)0x15bc, (q15_t)0x81dc, (q15_t)0x15b6, (q15_t)0x81db,
+  (q15_t)0x15b0, (q15_t)0x81da, (q15_t)0x15aa, (q15_t)0x81d9, (q15_t)0x15a4, (q15_t)0x81d8, (q15_t)0x159d, (q15_t)0x81d7,
+  (q15_t)0x1597, (q15_t)0x81d6, (q15_t)0x1591, (q15_t)0x81d5, (q15_t)0x158b, (q15_t)0x81d4, (q15_t)0x1585, (q15_t)0x81d3,
+  (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x1578, (q15_t)0x81d1, (q15_t)0x1572, (q15_t)0x81d0, (q15_t)0x156c, (q15_t)0x81cf,
+  (q15_t)0x1566, (q15_t)0x81ce, (q15_t)0x1560, (q15_t)0x81cd, (q15_t)0x1559, (q15_t)0x81cc, (q15_t)0x1553, (q15_t)0x81cb,
+  (q15_t)0x154d, (q15_t)0x81c9, (q15_t)0x1547, (q15_t)0x81c8, (q15_t)0x1541, (q15_t)0x81c7, (q15_t)0x153a, (q15_t)0x81c6,
+  (q15_t)0x1534, (q15_t)0x81c5, (q15_t)0x152e, (q15_t)0x81c4, (q15_t)0x1528, (q15_t)0x81c3, (q15_t)0x1522, (q15_t)0x81c2,
+  (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x1515, (q15_t)0x81c0, (q15_t)0x150f, (q15_t)0x81bf, (q15_t)0x1509, (q15_t)0x81be,
+  (q15_t)0x1503, (q15_t)0x81bd, (q15_t)0x14fc, (q15_t)0x81bc, (q15_t)0x14f6, (q15_t)0x81bb, (q15_t)0x14f0, (q15_t)0x81ba,
+  (q15_t)0x14ea, (q15_t)0x81b9, (q15_t)0x14e4, (q15_t)0x81b8, (q15_t)0x14dd, (q15_t)0x81b7, (q15_t)0x14d7, (q15_t)0x81b6,
+  (q15_t)0x14d1, (q15_t)0x81b5, (q15_t)0x14cb, (q15_t)0x81b4, (q15_t)0x14c5, (q15_t)0x81b3, (q15_t)0x14be, (q15_t)0x81b2,
+  (q15_t)0x14b8, (q15_t)0x81b1, (q15_t)0x14b2, (q15_t)0x81b0, (q15_t)0x14ac, (q15_t)0x81af, (q15_t)0x14a6, (q15_t)0x81ae,
+  (q15_t)0x149f, (q15_t)0x81ad, (q15_t)0x1499, (q15_t)0x81ac, (q15_t)0x1493, (q15_t)0x81ab, (q15_t)0x148d, (q15_t)0x81aa,
+  (q15_t)0x1487, (q15_t)0x81a9, (q15_t)0x1480, (q15_t)0x81a8, (q15_t)0x147a, (q15_t)0x81a7, (q15_t)0x1474, (q15_t)0x81a6,
+  (q15_t)0x146e, (q15_t)0x81a5, (q15_t)0x1468, (q15_t)0x81a4, (q15_t)0x1461, (q15_t)0x81a3, (q15_t)0x145b, (q15_t)0x81a2,
+  (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x144f, (q15_t)0x81a0, (q15_t)0x1449, (q15_t)0x819f, (q15_t)0x1442, (q15_t)0x819e,
+  (q15_t)0x143c, (q15_t)0x819d, (q15_t)0x1436, (q15_t)0x819c, (q15_t)0x1430, (q15_t)0x819b, (q15_t)0x142a, (q15_t)0x819a,
+  (q15_t)0x1423, (q15_t)0x8199, (q15_t)0x141d, (q15_t)0x8198, (q15_t)0x1417, (q15_t)0x8197, (q15_t)0x1411, (q15_t)0x8196,
+  (q15_t)0x140b, (q15_t)0x8195, (q15_t)0x1404, (q15_t)0x8194, (q15_t)0x13fe, (q15_t)0x8193, (q15_t)0x13f8, (q15_t)0x8192,
+  (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x13eb, (q15_t)0x8190, (q15_t)0x13e5, (q15_t)0x818f, (q15_t)0x13df, (q15_t)0x818e,
+  (q15_t)0x13d9, (q15_t)0x818d, (q15_t)0x13d3, (q15_t)0x818c, (q15_t)0x13cc, (q15_t)0x818b, (q15_t)0x13c6, (q15_t)0x818a,
+  (q15_t)0x13c0, (q15_t)0x8189, (q15_t)0x13ba, (q15_t)0x8188, (q15_t)0x13b4, (q15_t)0x8187, (q15_t)0x13ad, (q15_t)0x8186,
+  (q15_t)0x13a7, (q15_t)0x8185, (q15_t)0x13a1, (q15_t)0x8184, (q15_t)0x139b, (q15_t)0x8183, (q15_t)0x1395, (q15_t)0x8182,
+  (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x1388, (q15_t)0x8180, (q15_t)0x1382, (q15_t)0x817f, (q15_t)0x137c, (q15_t)0x817e,
+  (q15_t)0x1376, (q15_t)0x817d, (q15_t)0x136f, (q15_t)0x817c, (q15_t)0x1369, (q15_t)0x817c, (q15_t)0x1363, (q15_t)0x817b,
+  (q15_t)0x135d, (q15_t)0x817a, (q15_t)0x1356, (q15_t)0x8179, (q15_t)0x1350, (q15_t)0x8178, (q15_t)0x134a, (q15_t)0x8177,
+  (q15_t)0x1344, (q15_t)0x8176, (q15_t)0x133e, (q15_t)0x8175, (q15_t)0x1337, (q15_t)0x8174, (q15_t)0x1331, (q15_t)0x8173,
+  (q15_t)0x132b, (q15_t)0x8172, (q15_t)0x1325, (q15_t)0x8171, (q15_t)0x131f, (q15_t)0x8170, (q15_t)0x1318, (q15_t)0x816f,
+  (q15_t)0x1312, (q15_t)0x816e, (q15_t)0x130c, (q15_t)0x816d, (q15_t)0x1306, (q15_t)0x816c, (q15_t)0x12ff, (q15_t)0x816c,
+  (q15_t)0x12f9, (q15_t)0x816b, (q15_t)0x12f3, (q15_t)0x816a, (q15_t)0x12ed, (q15_t)0x8169, (q15_t)0x12e7, (q15_t)0x8168,
+  (q15_t)0x12e0, (q15_t)0x8167, (q15_t)0x12da, (q15_t)0x8166, (q15_t)0x12d4, (q15_t)0x8165, (q15_t)0x12ce, (q15_t)0x8164,
+  (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x12c1, (q15_t)0x8162, (q15_t)0x12bb, (q15_t)0x8161, (q15_t)0x12b5, (q15_t)0x8160,
+  (q15_t)0x12af, (q15_t)0x815f, (q15_t)0x12a8, (q15_t)0x815f, (q15_t)0x12a2, (q15_t)0x815e, (q15_t)0x129c, (q15_t)0x815d,
+  (q15_t)0x1296, (q15_t)0x815c, (q15_t)0x1290, (q15_t)0x815b, (q15_t)0x1289, (q15_t)0x815a, (q15_t)0x1283, (q15_t)0x8159,
+  (q15_t)0x127d, (q15_t)0x8158, (q15_t)0x1277, (q15_t)0x8157, (q15_t)0x1271, (q15_t)0x8156, (q15_t)0x126a, (q15_t)0x8155,
+  (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x125e, (q15_t)0x8154, (q15_t)0x1258, (q15_t)0x8153, (q15_t)0x1251, (q15_t)0x8152,
+  (q15_t)0x124b, (q15_t)0x8151, (q15_t)0x1245, (q15_t)0x8150, (q15_t)0x123f, (q15_t)0x814f, (q15_t)0x1239, (q15_t)0x814e,
+  (q15_t)0x1232, (q15_t)0x814d, (q15_t)0x122c, (q15_t)0x814c, (q15_t)0x1226, (q15_t)0x814c, (q15_t)0x1220, (q15_t)0x814b,
+  (q15_t)0x1219, (q15_t)0x814a, (q15_t)0x1213, (q15_t)0x8149, (q15_t)0x120d, (q15_t)0x8148, (q15_t)0x1207, (q15_t)0x8147,
+  (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x11fa, (q15_t)0x8145, (q15_t)0x11f4, (q15_t)0x8145, (q15_t)0x11ee, (q15_t)0x8144,
+  (q15_t)0x11e8, (q15_t)0x8143, (q15_t)0x11e1, (q15_t)0x8142, (q15_t)0x11db, (q15_t)0x8141, (q15_t)0x11d5, (q15_t)0x8140,
+  (q15_t)0x11cf, (q15_t)0x813f, (q15_t)0x11c9, (q15_t)0x813e, (q15_t)0x11c2, (q15_t)0x813d, (q15_t)0x11bc, (q15_t)0x813d,
+  (q15_t)0x11b6, (q15_t)0x813c, (q15_t)0x11b0, (q15_t)0x813b, (q15_t)0x11a9, (q15_t)0x813a, (q15_t)0x11a3, (q15_t)0x8139,
+  (q15_t)0x119d, (q15_t)0x8138, (q15_t)0x1197, (q15_t)0x8137, (q15_t)0x1191, (q15_t)0x8137, (q15_t)0x118a, (q15_t)0x8136,
+  (q15_t)0x1184, (q15_t)0x8135, (q15_t)0x117e, (q15_t)0x8134, (q15_t)0x1178, (q15_t)0x8133, (q15_t)0x1171, (q15_t)0x8132,
+  (q15_t)0x116b, (q15_t)0x8131, (q15_t)0x1165, (q15_t)0x8131, (q15_t)0x115f, (q15_t)0x8130, (q15_t)0x1159, (q15_t)0x812f,
+  (q15_t)0x1152, (q15_t)0x812e, (q15_t)0x114c, (q15_t)0x812d, (q15_t)0x1146, (q15_t)0x812c, (q15_t)0x1140, (q15_t)0x812b,
+  (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x1133, (q15_t)0x812a, (q15_t)0x112d, (q15_t)0x8129, (q15_t)0x1127, (q15_t)0x8128,
+  (q15_t)0x1121, (q15_t)0x8127, (q15_t)0x111a, (q15_t)0x8126, (q15_t)0x1114, (q15_t)0x8126, (q15_t)0x110e, (q15_t)0x8125,
+  (q15_t)0x1108, (q15_t)0x8124, (q15_t)0x1101, (q15_t)0x8123, (q15_t)0x10fb, (q15_t)0x8122, (q15_t)0x10f5, (q15_t)0x8121,
+  (q15_t)0x10ef, (q15_t)0x8121, (q15_t)0x10e8, (q15_t)0x8120, (q15_t)0x10e2, (q15_t)0x811f, (q15_t)0x10dc, (q15_t)0x811e,
+  (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x10d0, (q15_t)0x811c, (q15_t)0x10c9, (q15_t)0x811c, (q15_t)0x10c3, (q15_t)0x811b,
+  (q15_t)0x10bd, (q15_t)0x811a, (q15_t)0x10b7, (q15_t)0x8119, (q15_t)0x10b0, (q15_t)0x8118, (q15_t)0x10aa, (q15_t)0x8117,
+  (q15_t)0x10a4, (q15_t)0x8117, (q15_t)0x109e, (q15_t)0x8116, (q15_t)0x1098, (q15_t)0x8115, (q15_t)0x1091, (q15_t)0x8114,
+  (q15_t)0x108b, (q15_t)0x8113, (q15_t)0x1085, (q15_t)0x8113, (q15_t)0x107f, (q15_t)0x8112, (q15_t)0x1078, (q15_t)0x8111,
+  (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x106c, (q15_t)0x810f, (q15_t)0x1066, (q15_t)0x810f, (q15_t)0x105f, (q15_t)0x810e,
+  (q15_t)0x1059, (q15_t)0x810d, (q15_t)0x1053, (q15_t)0x810c, (q15_t)0x104d, (q15_t)0x810b, (q15_t)0x1047, (q15_t)0x810b,
+  (q15_t)0x1040, (q15_t)0x810a, (q15_t)0x103a, (q15_t)0x8109, (q15_t)0x1034, (q15_t)0x8108, (q15_t)0x102e, (q15_t)0x8107,
+  (q15_t)0x1027, (q15_t)0x8107, (q15_t)0x1021, (q15_t)0x8106, (q15_t)0x101b, (q15_t)0x8105, (q15_t)0x1015, (q15_t)0x8104,
+  (q15_t)0x100e, (q15_t)0x8103, (q15_t)0x1008, (q15_t)0x8103, (q15_t)0x1002, (q15_t)0x8102, (q15_t)0xffc, (q15_t)0x8101,
+  (q15_t)0xff5, (q15_t)0x8100, (q15_t)0xfef, (q15_t)0x80ff, (q15_t)0xfe9, (q15_t)0x80ff, (q15_t)0xfe3, (q15_t)0x80fe,
+  (q15_t)0xfdd, (q15_t)0x80fd, (q15_t)0xfd6, (q15_t)0x80fc, (q15_t)0xfd0, (q15_t)0x80fc, (q15_t)0xfca, (q15_t)0x80fb,
+  (q15_t)0xfc4, (q15_t)0x80fa, (q15_t)0xfbd, (q15_t)0x80f9, (q15_t)0xfb7, (q15_t)0x80f8, (q15_t)0xfb1, (q15_t)0x80f8,
+  (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xfa4, (q15_t)0x80f6, (q15_t)0xf9e, (q15_t)0x80f5, (q15_t)0xf98, (q15_t)0x80f5,
+  (q15_t)0xf92, (q15_t)0x80f4, (q15_t)0xf8b, (q15_t)0x80f3, (q15_t)0xf85, (q15_t)0x80f2, (q15_t)0xf7f, (q15_t)0x80f2,
+  (q15_t)0xf79, (q15_t)0x80f1, (q15_t)0xf73, (q15_t)0x80f0, (q15_t)0xf6c, (q15_t)0x80ef, (q15_t)0xf66, (q15_t)0x80ef,
+  (q15_t)0xf60, (q15_t)0x80ee, (q15_t)0xf5a, (q15_t)0x80ed, (q15_t)0xf53, (q15_t)0x80ec, (q15_t)0xf4d, (q15_t)0x80ec,
+  (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xf41, (q15_t)0x80ea, (q15_t)0xf3a, (q15_t)0x80e9, (q15_t)0xf34, (q15_t)0x80e9,
+  (q15_t)0xf2e, (q15_t)0x80e8, (q15_t)0xf28, (q15_t)0x80e7, (q15_t)0xf21, (q15_t)0x80e6, (q15_t)0xf1b, (q15_t)0x80e6,
+  (q15_t)0xf15, (q15_t)0x80e5, (q15_t)0xf0f, (q15_t)0x80e4, (q15_t)0xf08, (q15_t)0x80e3, (q15_t)0xf02, (q15_t)0x80e3,
+  (q15_t)0xefc, (q15_t)0x80e2, (q15_t)0xef6, (q15_t)0x80e1, (q15_t)0xef0, (q15_t)0x80e0, (q15_t)0xee9, (q15_t)0x80e0,
+  (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xedd, (q15_t)0x80de, (q15_t)0xed7, (q15_t)0x80dd, (q15_t)0xed0, (q15_t)0x80dd,
+  (q15_t)0xeca, (q15_t)0x80dc, (q15_t)0xec4, (q15_t)0x80db, (q15_t)0xebe, (q15_t)0x80db, (q15_t)0xeb7, (q15_t)0x80da,
+  (q15_t)0xeb1, (q15_t)0x80d9, (q15_t)0xeab, (q15_t)0x80d8, (q15_t)0xea5, (q15_t)0x80d8, (q15_t)0xe9e, (q15_t)0x80d7,
+  (q15_t)0xe98, (q15_t)0x80d6, (q15_t)0xe92, (q15_t)0x80d6, (q15_t)0xe8c, (q15_t)0x80d5, (q15_t)0xe85, (q15_t)0x80d4,
+  (q15_t)0xe7f, (q15_t)0x80d3, (q15_t)0xe79, (q15_t)0x80d3, (q15_t)0xe73, (q15_t)0x80d2, (q15_t)0xe6c, (q15_t)0x80d1,
+  (q15_t)0xe66, (q15_t)0x80d1, (q15_t)0xe60, (q15_t)0x80d0, (q15_t)0xe5a, (q15_t)0x80cf, (q15_t)0xe53, (q15_t)0x80ce,
+  (q15_t)0xe4d, (q15_t)0x80ce, (q15_t)0xe47, (q15_t)0x80cd, (q15_t)0xe41, (q15_t)0x80cc, (q15_t)0xe3a, (q15_t)0x80cc,
+  (q15_t)0xe34, (q15_t)0x80cb, (q15_t)0xe2e, (q15_t)0x80ca, (q15_t)0xe28, (q15_t)0x80ca, (q15_t)0xe22, (q15_t)0x80c9,
+  (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xe15, (q15_t)0x80c7, (q15_t)0xe0f, (q15_t)0x80c7, (q15_t)0xe09, (q15_t)0x80c6,
+  (q15_t)0xe02, (q15_t)0x80c5, (q15_t)0xdfc, (q15_t)0x80c5, (q15_t)0xdf6, (q15_t)0x80c4, (q15_t)0xdf0, (q15_t)0x80c3,
+  (q15_t)0xde9, (q15_t)0x80c3, (q15_t)0xde3, (q15_t)0x80c2, (q15_t)0xddd, (q15_t)0x80c1, (q15_t)0xdd7, (q15_t)0x80c1,
+  (q15_t)0xdd0, (q15_t)0x80c0, (q15_t)0xdca, (q15_t)0x80bf, (q15_t)0xdc4, (q15_t)0x80bf, (q15_t)0xdbe, (q15_t)0x80be,
+  (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xdb1, (q15_t)0x80bd, (q15_t)0xdab, (q15_t)0x80bc, (q15_t)0xda5, (q15_t)0x80bb,
+  (q15_t)0xd9e, (q15_t)0x80bb, (q15_t)0xd98, (q15_t)0x80ba, (q15_t)0xd92, (q15_t)0x80b9, (q15_t)0xd8c, (q15_t)0x80b9,
+  (q15_t)0xd85, (q15_t)0x80b8, (q15_t)0xd7f, (q15_t)0x80b7, (q15_t)0xd79, (q15_t)0x80b7, (q15_t)0xd73, (q15_t)0x80b6,
+  (q15_t)0xd6c, (q15_t)0x80b5, (q15_t)0xd66, (q15_t)0x80b5, (q15_t)0xd60, (q15_t)0x80b4, (q15_t)0xd5a, (q15_t)0x80b3,
+  (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xd4d, (q15_t)0x80b2, (q15_t)0xd47, (q15_t)0x80b1, (q15_t)0xd41, (q15_t)0x80b1,
+  (q15_t)0xd3a, (q15_t)0x80b0, (q15_t)0xd34, (q15_t)0x80af, (q15_t)0xd2e, (q15_t)0x80af, (q15_t)0xd28, (q15_t)0x80ae,
+  (q15_t)0xd21, (q15_t)0x80ad, (q15_t)0xd1b, (q15_t)0x80ad, (q15_t)0xd15, (q15_t)0x80ac, (q15_t)0xd0f, (q15_t)0x80ab,
+  (q15_t)0xd08, (q15_t)0x80ab, (q15_t)0xd02, (q15_t)0x80aa, (q15_t)0xcfc, (q15_t)0x80aa, (q15_t)0xcf6, (q15_t)0x80a9,
+  (q15_t)0xcef, (q15_t)0x80a8, (q15_t)0xce9, (q15_t)0x80a8, (q15_t)0xce3, (q15_t)0x80a7, (q15_t)0xcdd, (q15_t)0x80a6,
+  (q15_t)0xcd6, (q15_t)0x80a6, (q15_t)0xcd0, (q15_t)0x80a5, (q15_t)0xcca, (q15_t)0x80a5, (q15_t)0xcc4, (q15_t)0x80a4,
+  (q15_t)0xcbd, (q15_t)0x80a3, (q15_t)0xcb7, (q15_t)0x80a3, (q15_t)0xcb1, (q15_t)0x80a2, (q15_t)0xcab, (q15_t)0x80a1,
+  (q15_t)0xca4, (q15_t)0x80a1, (q15_t)0xc9e, (q15_t)0x80a0, (q15_t)0xc98, (q15_t)0x80a0, (q15_t)0xc92, (q15_t)0x809f,
+  (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc85, (q15_t)0x809e, (q15_t)0xc7f, (q15_t)0x809d, (q15_t)0xc79, (q15_t)0x809c,
+  (q15_t)0xc72, (q15_t)0x809c, (q15_t)0xc6c, (q15_t)0x809b, (q15_t)0xc66, (q15_t)0x809b, (q15_t)0xc60, (q15_t)0x809a,
+  (q15_t)0xc59, (q15_t)0x8099, (q15_t)0xc53, (q15_t)0x8099, (q15_t)0xc4d, (q15_t)0x8098, (q15_t)0xc47, (q15_t)0x8098,
+  (q15_t)0xc40, (q15_t)0x8097, (q15_t)0xc3a, (q15_t)0x8096, (q15_t)0xc34, (q15_t)0x8096, (q15_t)0xc2e, (q15_t)0x8095,
+  (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xc21, (q15_t)0x8094, (q15_t)0xc1b, (q15_t)0x8093, (q15_t)0xc14, (q15_t)0x8093,
+  (q15_t)0xc0e, (q15_t)0x8092, (q15_t)0xc08, (q15_t)0x8092, (q15_t)0xc02, (q15_t)0x8091, (q15_t)0xbfb, (q15_t)0x8090,
+  (q15_t)0xbf5, (q15_t)0x8090, (q15_t)0xbef, (q15_t)0x808f, (q15_t)0xbe9, (q15_t)0x808f, (q15_t)0xbe2, (q15_t)0x808e,
+  (q15_t)0xbdc, (q15_t)0x808e, (q15_t)0xbd6, (q15_t)0x808d, (q15_t)0xbd0, (q15_t)0x808c, (q15_t)0xbc9, (q15_t)0x808c,
+  (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xbbd, (q15_t)0x808b, (q15_t)0xbb7, (q15_t)0x808a, (q15_t)0xbb0, (q15_t)0x8089,
+  (q15_t)0xbaa, (q15_t)0x8089, (q15_t)0xba4, (q15_t)0x8088, (q15_t)0xb9e, (q15_t)0x8088, (q15_t)0xb97, (q15_t)0x8087,
+  (q15_t)0xb91, (q15_t)0x8087, (q15_t)0xb8b, (q15_t)0x8086, (q15_t)0xb85, (q15_t)0x8085, (q15_t)0xb7e, (q15_t)0x8085,
+  (q15_t)0xb78, (q15_t)0x8084, (q15_t)0xb72, (q15_t)0x8084, (q15_t)0xb6c, (q15_t)0x8083, (q15_t)0xb65, (q15_t)0x8083,
+  (q15_t)0xb5f, (q15_t)0x8082, (q15_t)0xb59, (q15_t)0x8082, (q15_t)0xb53, (q15_t)0x8081, (q15_t)0xb4c, (q15_t)0x8080,
+  (q15_t)0xb46, (q15_t)0x8080, (q15_t)0xb40, (q15_t)0x807f, (q15_t)0xb3a, (q15_t)0x807f, (q15_t)0xb33, (q15_t)0x807e,
+  (q15_t)0xb2d, (q15_t)0x807e, (q15_t)0xb27, (q15_t)0x807d, (q15_t)0xb20, (q15_t)0x807d, (q15_t)0xb1a, (q15_t)0x807c,
+  (q15_t)0xb14, (q15_t)0x807b, (q15_t)0xb0e, (q15_t)0x807b, (q15_t)0xb07, (q15_t)0x807a, (q15_t)0xb01, (q15_t)0x807a,
+  (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xaf5, (q15_t)0x8079, (q15_t)0xaee, (q15_t)0x8078, (q15_t)0xae8, (q15_t)0x8078,
+  (q15_t)0xae2, (q15_t)0x8077, (q15_t)0xadc, (q15_t)0x8077, (q15_t)0xad5, (q15_t)0x8076, (q15_t)0xacf, (q15_t)0x8076,
+  (q15_t)0xac9, (q15_t)0x8075, (q15_t)0xac3, (q15_t)0x8075, (q15_t)0xabc, (q15_t)0x8074, (q15_t)0xab6, (q15_t)0x8073,
+  (q15_t)0xab0, (q15_t)0x8073, (q15_t)0xaaa, (q15_t)0x8072, (q15_t)0xaa3, (q15_t)0x8072, (q15_t)0xa9d, (q15_t)0x8071,
+  (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa90, (q15_t)0x8070, (q15_t)0xa8a, (q15_t)0x8070, (q15_t)0xa84, (q15_t)0x806f,
+  (q15_t)0xa7e, (q15_t)0x806f, (q15_t)0xa77, (q15_t)0x806e, (q15_t)0xa71, (q15_t)0x806e, (q15_t)0xa6b, (q15_t)0x806d,
+  (q15_t)0xa65, (q15_t)0x806d, (q15_t)0xa5e, (q15_t)0x806c, (q15_t)0xa58, (q15_t)0x806c, (q15_t)0xa52, (q15_t)0x806b,
+  (q15_t)0xa4c, (q15_t)0x806b, (q15_t)0xa45, (q15_t)0x806a, (q15_t)0xa3f, (q15_t)0x806a, (q15_t)0xa39, (q15_t)0x8069,
+  (q15_t)0xa33, (q15_t)0x8069, (q15_t)0xa2c, (q15_t)0x8068, (q15_t)0xa26, (q15_t)0x8068, (q15_t)0xa20, (q15_t)0x8067,
+  (q15_t)0xa19, (q15_t)0x8067, (q15_t)0xa13, (q15_t)0x8066, (q15_t)0xa0d, (q15_t)0x8066, (q15_t)0xa07, (q15_t)0x8065,
+  (q15_t)0xa00, (q15_t)0x8065, (q15_t)0x9fa, (q15_t)0x8064, (q15_t)0x9f4, (q15_t)0x8064, (q15_t)0x9ee, (q15_t)0x8063,
+  (q15_t)0x9e7, (q15_t)0x8063, (q15_t)0x9e1, (q15_t)0x8062, (q15_t)0x9db, (q15_t)0x8062, (q15_t)0x9d5, (q15_t)0x8061,
+  (q15_t)0x9ce, (q15_t)0x8061, (q15_t)0x9c8, (q15_t)0x8060, (q15_t)0x9c2, (q15_t)0x8060, (q15_t)0x9bc, (q15_t)0x805f,
+  (q15_t)0x9b5, (q15_t)0x805f, (q15_t)0x9af, (q15_t)0x805e, (q15_t)0x9a9, (q15_t)0x805e, (q15_t)0x9a2, (q15_t)0x805d,
+  (q15_t)0x99c, (q15_t)0x805d, (q15_t)0x996, (q15_t)0x805d, (q15_t)0x990, (q15_t)0x805c, (q15_t)0x989, (q15_t)0x805c,
+  (q15_t)0x983, (q15_t)0x805b, (q15_t)0x97d, (q15_t)0x805b, (q15_t)0x977, (q15_t)0x805a, (q15_t)0x970, (q15_t)0x805a,
+  (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x964, (q15_t)0x8059, (q15_t)0x95e, (q15_t)0x8058, (q15_t)0x957, (q15_t)0x8058,
+  (q15_t)0x951, (q15_t)0x8057, (q15_t)0x94b, (q15_t)0x8057, (q15_t)0x944, (q15_t)0x8057, (q15_t)0x93e, (q15_t)0x8056,
+  (q15_t)0x938, (q15_t)0x8056, (q15_t)0x932, (q15_t)0x8055, (q15_t)0x92b, (q15_t)0x8055, (q15_t)0x925, (q15_t)0x8054,
+  (q15_t)0x91f, (q15_t)0x8054, (q15_t)0x919, (q15_t)0x8053, (q15_t)0x912, (q15_t)0x8053, (q15_t)0x90c, (q15_t)0x8052,
+  (q15_t)0x906, (q15_t)0x8052, (q15_t)0x900, (q15_t)0x8052, (q15_t)0x8f9, (q15_t)0x8051, (q15_t)0x8f3, (q15_t)0x8051,
+  (q15_t)0x8ed, (q15_t)0x8050, (q15_t)0x8e6, (q15_t)0x8050, (q15_t)0x8e0, (q15_t)0x804f, (q15_t)0x8da, (q15_t)0x804f,
+  (q15_t)0x8d4, (q15_t)0x804f, (q15_t)0x8cd, (q15_t)0x804e, (q15_t)0x8c7, (q15_t)0x804e, (q15_t)0x8c1, (q15_t)0x804d,
+  (q15_t)0x8bb, (q15_t)0x804d, (q15_t)0x8b4, (q15_t)0x804c, (q15_t)0x8ae, (q15_t)0x804c, (q15_t)0x8a8, (q15_t)0x804c,
+  (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x89b, (q15_t)0x804b, (q15_t)0x895, (q15_t)0x804a, (q15_t)0x88f, (q15_t)0x804a,
+  (q15_t)0x888, (q15_t)0x8049, (q15_t)0x882, (q15_t)0x8049, (q15_t)0x87c, (q15_t)0x8049, (q15_t)0x876, (q15_t)0x8048,
+  (q15_t)0x86f, (q15_t)0x8048, (q15_t)0x869, (q15_t)0x8047, (q15_t)0x863, (q15_t)0x8047, (q15_t)0x85d, (q15_t)0x8047,
+  (q15_t)0x856, (q15_t)0x8046, (q15_t)0x850, (q15_t)0x8046, (q15_t)0x84a, (q15_t)0x8045, (q15_t)0x843, (q15_t)0x8045,
+  (q15_t)0x83d, (q15_t)0x8044, (q15_t)0x837, (q15_t)0x8044, (q15_t)0x831, (q15_t)0x8044, (q15_t)0x82a, (q15_t)0x8043,
+  (q15_t)0x824, (q15_t)0x8043, (q15_t)0x81e, (q15_t)0x8042, (q15_t)0x818, (q15_t)0x8042, (q15_t)0x811, (q15_t)0x8042,
+  (q15_t)0x80b, (q15_t)0x8041, (q15_t)0x805, (q15_t)0x8041, (q15_t)0x7fe, (q15_t)0x8040, (q15_t)0x7f8, (q15_t)0x8040,
+  (q15_t)0x7f2, (q15_t)0x8040, (q15_t)0x7ec, (q15_t)0x803f, (q15_t)0x7e5, (q15_t)0x803f, (q15_t)0x7df, (q15_t)0x803f,
+  (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x7d3, (q15_t)0x803e, (q15_t)0x7cc, (q15_t)0x803d, (q15_t)0x7c6, (q15_t)0x803d,
+  (q15_t)0x7c0, (q15_t)0x803d, (q15_t)0x7ba, (q15_t)0x803c, (q15_t)0x7b3, (q15_t)0x803c, (q15_t)0x7ad, (q15_t)0x803b,
+  (q15_t)0x7a7, (q15_t)0x803b, (q15_t)0x7a0, (q15_t)0x803b, (q15_t)0x79a, (q15_t)0x803a, (q15_t)0x794, (q15_t)0x803a,
+  (q15_t)0x78e, (q15_t)0x803a, (q15_t)0x787, (q15_t)0x8039, (q15_t)0x781, (q15_t)0x8039, (q15_t)0x77b, (q15_t)0x8039,
+  (q15_t)0x775, (q15_t)0x8038, (q15_t)0x76e, (q15_t)0x8038, (q15_t)0x768, (q15_t)0x8037, (q15_t)0x762, (q15_t)0x8037,
+  (q15_t)0x75b, (q15_t)0x8037, (q15_t)0x755, (q15_t)0x8036, (q15_t)0x74f, (q15_t)0x8036, (q15_t)0x749, (q15_t)0x8036,
+  (q15_t)0x742, (q15_t)0x8035, (q15_t)0x73c, (q15_t)0x8035, (q15_t)0x736, (q15_t)0x8035, (q15_t)0x730, (q15_t)0x8034,
+  (q15_t)0x729, (q15_t)0x8034, (q15_t)0x723, (q15_t)0x8033, (q15_t)0x71d, (q15_t)0x8033, (q15_t)0x716, (q15_t)0x8033,
+  (q15_t)0x710, (q15_t)0x8032, (q15_t)0x70a, (q15_t)0x8032, (q15_t)0x704, (q15_t)0x8032, (q15_t)0x6fd, (q15_t)0x8031,
+  (q15_t)0x6f7, (q15_t)0x8031, (q15_t)0x6f1, (q15_t)0x8031, (q15_t)0x6ea, (q15_t)0x8030, (q15_t)0x6e4, (q15_t)0x8030,
+  (q15_t)0x6de, (q15_t)0x8030, (q15_t)0x6d8, (q15_t)0x802f, (q15_t)0x6d1, (q15_t)0x802f, (q15_t)0x6cb, (q15_t)0x802f,
+  (q15_t)0x6c5, (q15_t)0x802e, (q15_t)0x6bf, (q15_t)0x802e, (q15_t)0x6b8, (q15_t)0x802e, (q15_t)0x6b2, (q15_t)0x802d,
+  (q15_t)0x6ac, (q15_t)0x802d, (q15_t)0x6a5, (q15_t)0x802d, (q15_t)0x69f, (q15_t)0x802c, (q15_t)0x699, (q15_t)0x802c,
+  (q15_t)0x693, (q15_t)0x802c, (q15_t)0x68c, (q15_t)0x802b, (q15_t)0x686, (q15_t)0x802b, (q15_t)0x680, (q15_t)0x802b,
+  (q15_t)0x67a, (q15_t)0x802a, (q15_t)0x673, (q15_t)0x802a, (q15_t)0x66d, (q15_t)0x802a, (q15_t)0x667, (q15_t)0x802a,
+  (q15_t)0x660, (q15_t)0x8029, (q15_t)0x65a, (q15_t)0x8029, (q15_t)0x654, (q15_t)0x8029, (q15_t)0x64e, (q15_t)0x8028,
+  (q15_t)0x647, (q15_t)0x8028, (q15_t)0x641, (q15_t)0x8028, (q15_t)0x63b, (q15_t)0x8027, (q15_t)0x635, (q15_t)0x8027,
+  (q15_t)0x62e, (q15_t)0x8027, (q15_t)0x628, (q15_t)0x8026, (q15_t)0x622, (q15_t)0x8026, (q15_t)0x61b, (q15_t)0x8026,
+  (q15_t)0x615, (q15_t)0x8026, (q15_t)0x60f, (q15_t)0x8025, (q15_t)0x609, (q15_t)0x8025, (q15_t)0x602, (q15_t)0x8025,
+  (q15_t)0x5fc, (q15_t)0x8024, (q15_t)0x5f6, (q15_t)0x8024, (q15_t)0x5ef, (q15_t)0x8024, (q15_t)0x5e9, (q15_t)0x8023,
+  (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x5dd, (q15_t)0x8023, (q15_t)0x5d6, (q15_t)0x8023, (q15_t)0x5d0, (q15_t)0x8022,
+  (q15_t)0x5ca, (q15_t)0x8022, (q15_t)0x5c4, (q15_t)0x8022, (q15_t)0x5bd, (q15_t)0x8021, (q15_t)0x5b7, (q15_t)0x8021,
+  (q15_t)0x5b1, (q15_t)0x8021, (q15_t)0x5aa, (q15_t)0x8021, (q15_t)0x5a4, (q15_t)0x8020, (q15_t)0x59e, (q15_t)0x8020,
+  (q15_t)0x598, (q15_t)0x8020, (q15_t)0x591, (q15_t)0x8020, (q15_t)0x58b, (q15_t)0x801f, (q15_t)0x585, (q15_t)0x801f,
+  (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x578, (q15_t)0x801e, (q15_t)0x572, (q15_t)0x801e, (q15_t)0x56c, (q15_t)0x801e,
+  (q15_t)0x565, (q15_t)0x801e, (q15_t)0x55f, (q15_t)0x801d, (q15_t)0x559, (q15_t)0x801d, (q15_t)0x553, (q15_t)0x801d,
+  (q15_t)0x54c, (q15_t)0x801d, (q15_t)0x546, (q15_t)0x801c, (q15_t)0x540, (q15_t)0x801c, (q15_t)0x539, (q15_t)0x801c,
+  (q15_t)0x533, (q15_t)0x801c, (q15_t)0x52d, (q15_t)0x801b, (q15_t)0x527, (q15_t)0x801b, (q15_t)0x520, (q15_t)0x801b,
+  (q15_t)0x51a, (q15_t)0x801b, (q15_t)0x514, (q15_t)0x801a, (q15_t)0x50d, (q15_t)0x801a, (q15_t)0x507, (q15_t)0x801a,
+  (q15_t)0x501, (q15_t)0x801a, (q15_t)0x4fb, (q15_t)0x8019, (q15_t)0x4f4, (q15_t)0x8019, (q15_t)0x4ee, (q15_t)0x8019,
+  (q15_t)0x4e8, (q15_t)0x8019, (q15_t)0x4e2, (q15_t)0x8018, (q15_t)0x4db, (q15_t)0x8018, (q15_t)0x4d5, (q15_t)0x8018,
+  (q15_t)0x4cf, (q15_t)0x8018, (q15_t)0x4c8, (q15_t)0x8017, (q15_t)0x4c2, (q15_t)0x8017, (q15_t)0x4bc, (q15_t)0x8017,
+  (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x4af, (q15_t)0x8016, (q15_t)0x4a9, (q15_t)0x8016, (q15_t)0x4a3, (q15_t)0x8016,
+  (q15_t)0x49c, (q15_t)0x8016, (q15_t)0x496, (q15_t)0x8016, (q15_t)0x490, (q15_t)0x8015, (q15_t)0x48a, (q15_t)0x8015,
+  (q15_t)0x483, (q15_t)0x8015, (q15_t)0x47d, (q15_t)0x8015, (q15_t)0x477, (q15_t)0x8014, (q15_t)0x471, (q15_t)0x8014,
+  (q15_t)0x46a, (q15_t)0x8014, (q15_t)0x464, (q15_t)0x8014, (q15_t)0x45e, (q15_t)0x8014, (q15_t)0x457, (q15_t)0x8013,
+  (q15_t)0x451, (q15_t)0x8013, (q15_t)0x44b, (q15_t)0x8013, (q15_t)0x445, (q15_t)0x8013, (q15_t)0x43e, (q15_t)0x8013,
+  (q15_t)0x438, (q15_t)0x8012, (q15_t)0x432, (q15_t)0x8012, (q15_t)0x42b, (q15_t)0x8012, (q15_t)0x425, (q15_t)0x8012,
+  (q15_t)0x41f, (q15_t)0x8012, (q15_t)0x419, (q15_t)0x8011, (q15_t)0x412, (q15_t)0x8011, (q15_t)0x40c, (q15_t)0x8011,
+  (q15_t)0x406, (q15_t)0x8011, (q15_t)0x3ff, (q15_t)0x8011, (q15_t)0x3f9, (q15_t)0x8010, (q15_t)0x3f3, (q15_t)0x8010,
+  (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x3e6, (q15_t)0x8010, (q15_t)0x3e0, (q15_t)0x8010, (q15_t)0x3da, (q15_t)0x800f,
+  (q15_t)0x3d4, (q15_t)0x800f, (q15_t)0x3cd, (q15_t)0x800f, (q15_t)0x3c7, (q15_t)0x800f, (q15_t)0x3c1, (q15_t)0x800f,
+  (q15_t)0x3ba, (q15_t)0x800e, (q15_t)0x3b4, (q15_t)0x800e, (q15_t)0x3ae, (q15_t)0x800e, (q15_t)0x3a8, (q15_t)0x800e,
+  (q15_t)0x3a1, (q15_t)0x800e, (q15_t)0x39b, (q15_t)0x800e, (q15_t)0x395, (q15_t)0x800d, (q15_t)0x38e, (q15_t)0x800d,
+  (q15_t)0x388, (q15_t)0x800d, (q15_t)0x382, (q15_t)0x800d, (q15_t)0x37c, (q15_t)0x800d, (q15_t)0x375, (q15_t)0x800c,
+  (q15_t)0x36f, (q15_t)0x800c, (q15_t)0x369, (q15_t)0x800c, (q15_t)0x362, (q15_t)0x800c, (q15_t)0x35c, (q15_t)0x800c,
+  (q15_t)0x356, (q15_t)0x800c, (q15_t)0x350, (q15_t)0x800b, (q15_t)0x349, (q15_t)0x800b, (q15_t)0x343, (q15_t)0x800b,
+  (q15_t)0x33d, (q15_t)0x800b, (q15_t)0x337, (q15_t)0x800b, (q15_t)0x330, (q15_t)0x800b, (q15_t)0x32a, (q15_t)0x800b,
+  (q15_t)0x324, (q15_t)0x800a, (q15_t)0x31d, (q15_t)0x800a, (q15_t)0x317, (q15_t)0x800a, (q15_t)0x311, (q15_t)0x800a,
+  (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x304, (q15_t)0x800a, (q15_t)0x2fe, (q15_t)0x8009, (q15_t)0x2f8, (q15_t)0x8009,
+  (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2eb, (q15_t)0x8009, (q15_t)0x2e5, (q15_t)0x8009, (q15_t)0x2df, (q15_t)0x8009,
+  (q15_t)0x2d8, (q15_t)0x8009, (q15_t)0x2d2, (q15_t)0x8008, (q15_t)0x2cc, (q15_t)0x8008, (q15_t)0x2c5, (q15_t)0x8008,
+  (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2b9, (q15_t)0x8008, (q15_t)0x2b3, (q15_t)0x8008, (q15_t)0x2ac, (q15_t)0x8008,
+  (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x2a0, (q15_t)0x8007, (q15_t)0x299, (q15_t)0x8007, (q15_t)0x293, (q15_t)0x8007,
+  (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x287, (q15_t)0x8007, (q15_t)0x280, (q15_t)0x8007, (q15_t)0x27a, (q15_t)0x8007,
+  (q15_t)0x274, (q15_t)0x8007, (q15_t)0x26d, (q15_t)0x8006, (q15_t)0x267, (q15_t)0x8006, (q15_t)0x261, (q15_t)0x8006,
+  (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x254, (q15_t)0x8006, (q15_t)0x24e, (q15_t)0x8006, (q15_t)0x248, (q15_t)0x8006,
+  (q15_t)0x242, (q15_t)0x8006, (q15_t)0x23b, (q15_t)0x8005, (q15_t)0x235, (q15_t)0x8005, (q15_t)0x22f, (q15_t)0x8005,
+  (q15_t)0x228, (q15_t)0x8005, (q15_t)0x222, (q15_t)0x8005, (q15_t)0x21c, (q15_t)0x8005, (q15_t)0x216, (q15_t)0x8005,
+  (q15_t)0x20f, (q15_t)0x8005, (q15_t)0x209, (q15_t)0x8005, (q15_t)0x203, (q15_t)0x8005, (q15_t)0x1fc, (q15_t)0x8004,
+  (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1f0, (q15_t)0x8004, (q15_t)0x1ea, (q15_t)0x8004, (q15_t)0x1e3, (q15_t)0x8004,
+  (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1d7, (q15_t)0x8004, (q15_t)0x1d0, (q15_t)0x8004, (q15_t)0x1ca, (q15_t)0x8004,
+  (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1be, (q15_t)0x8004, (q15_t)0x1b7, (q15_t)0x8003, (q15_t)0x1b1, (q15_t)0x8003,
+  (q15_t)0x1ab, (q15_t)0x8003, (q15_t)0x1a4, (q15_t)0x8003, (q15_t)0x19e, (q15_t)0x8003, (q15_t)0x198, (q15_t)0x8003,
+  (q15_t)0x192, (q15_t)0x8003, (q15_t)0x18b, (q15_t)0x8003, (q15_t)0x185, (q15_t)0x8003, (q15_t)0x17f, (q15_t)0x8003,
+  (q15_t)0x178, (q15_t)0x8003, (q15_t)0x172, (q15_t)0x8003, (q15_t)0x16c, (q15_t)0x8003, (q15_t)0x166, (q15_t)0x8002,
+  (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x159, (q15_t)0x8002, (q15_t)0x153, (q15_t)0x8002, (q15_t)0x14d, (q15_t)0x8002,
+  (q15_t)0x146, (q15_t)0x8002, (q15_t)0x140, (q15_t)0x8002, (q15_t)0x13a, (q15_t)0x8002, (q15_t)0x133, (q15_t)0x8002,
+  (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x127, (q15_t)0x8002, (q15_t)0x121, (q15_t)0x8002, (q15_t)0x11a, (q15_t)0x8002,
+  (q15_t)0x114, (q15_t)0x8002, (q15_t)0x10e, (q15_t)0x8002, (q15_t)0x107, (q15_t)0x8002, (q15_t)0x101, (q15_t)0x8002,
+  (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xf5, (q15_t)0x8001, (q15_t)0xee, (q15_t)0x8001, (q15_t)0xe8, (q15_t)0x8001,
+  (q15_t)0xe2, (q15_t)0x8001, (q15_t)0xdb, (q15_t)0x8001, (q15_t)0xd5, (q15_t)0x8001, (q15_t)0xcf, (q15_t)0x8001,
+  (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xc2, (q15_t)0x8001, (q15_t)0xbc, (q15_t)0x8001, (q15_t)0xb6, (q15_t)0x8001,
+  (q15_t)0xaf, (q15_t)0x8001, (q15_t)0xa9, (q15_t)0x8001, (q15_t)0xa3, (q15_t)0x8001, (q15_t)0x9d, (q15_t)0x8001,
+  (q15_t)0x96, (q15_t)0x8001, (q15_t)0x90, (q15_t)0x8001, (q15_t)0x8a, (q15_t)0x8001, (q15_t)0x83, (q15_t)0x8001,
+  (q15_t)0x7d, (q15_t)0x8001, (q15_t)0x77, (q15_t)0x8001, (q15_t)0x71, (q15_t)0x8001, (q15_t)0x6a, (q15_t)0x8001,
+  (q15_t)0x64, (q15_t)0x8001, (q15_t)0x5e, (q15_t)0x8001, (q15_t)0x57, (q15_t)0x8001, (q15_t)0x51, (q15_t)0x8001,
+  (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x45, (q15_t)0x8001, (q15_t)0x3e, (q15_t)0x8001, (q15_t)0x38, (q15_t)0x8001,
+  (q15_t)0x32, (q15_t)0x8001, (q15_t)0x2b, (q15_t)0x8001, (q15_t)0x25, (q15_t)0x8001, (q15_t)0x1f, (q15_t)0x8001,
+  (q15_t)0x19, (q15_t)0x8001, (q15_t)0x12, (q15_t)0x8001, (q15_t)0xc, (q15_t)0x8001, (q15_t)0x6, (q15_t)0x8001
+};
+
+
+/**
+* \par
+* cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 

+* \par
+* C command to generate the table
+* 
+* for(i = 0; i< N; i++)
+* {
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* } 

+* \par
+* where N is the number of factors to generate and c is pi/(2*N)
+* \par
+* Then converted to q15 format by multiplying with 2^31 and saturated if required.
+
+*/
+
+static const q15_t ALIGN4 cos_factorsQ15_128[128] = {
+  (q15_t)0x7fff, (q15_t)0x7ffa, (q15_t)0x7ff0, (q15_t)0x7fe1, (q15_t)0x7fce, (q15_t)0x7fb5, (q15_t)0x7f97, (q15_t)0x7f75,
+  (q15_t)0x7f4d, (q15_t)0x7f21, (q15_t)0x7ef0, (q15_t)0x7eba, (q15_t)0x7e7f, (q15_t)0x7e3f, (q15_t)0x7dfa, (q15_t)0x7db0,
+  (q15_t)0x7d62, (q15_t)0x7d0f, (q15_t)0x7cb7, (q15_t)0x7c5a, (q15_t)0x7bf8, (q15_t)0x7b92, (q15_t)0x7b26, (q15_t)0x7ab6,
+  (q15_t)0x7a42, (q15_t)0x79c8, (q15_t)0x794a, (q15_t)0x78c7, (q15_t)0x7840, (q15_t)0x77b4, (q15_t)0x7723, (q15_t)0x768e,
+  (q15_t)0x75f4, (q15_t)0x7555, (q15_t)0x74b2, (q15_t)0x740b, (q15_t)0x735f, (q15_t)0x72af, (q15_t)0x71fa, (q15_t)0x7141,
+  (q15_t)0x7083, (q15_t)0x6fc1, (q15_t)0x6efb, (q15_t)0x6e30, (q15_t)0x6d62, (q15_t)0x6c8f, (q15_t)0x6bb8, (q15_t)0x6adc,
+  (q15_t)0x69fd, (q15_t)0x6919, (q15_t)0x6832, (q15_t)0x6746, (q15_t)0x6657, (q15_t)0x6563, (q15_t)0x646c, (q15_t)0x6371,
+  (q15_t)0x6271, (q15_t)0x616f, (q15_t)0x6068, (q15_t)0x5f5e, (q15_t)0x5e50, (q15_t)0x5d3e, (q15_t)0x5c29, (q15_t)0x5b10,
+  (q15_t)0x59f3, (q15_t)0x58d4, (q15_t)0x57b0, (q15_t)0x568a, (q15_t)0x5560, (q15_t)0x5433, (q15_t)0x5302, (q15_t)0x51ce,
+  (q15_t)0x5097, (q15_t)0x4f5e, (q15_t)0x4e21, (q15_t)0x4ce1, (q15_t)0x4b9e, (q15_t)0x4a58, (q15_t)0x490f, (q15_t)0x47c3,
+  (q15_t)0x4675, (q15_t)0x4524, (q15_t)0x43d0, (q15_t)0x427a, (q15_t)0x4121, (q15_t)0x3fc5, (q15_t)0x3e68, (q15_t)0x3d07,
+  (q15_t)0x3ba5, (q15_t)0x3a40, (q15_t)0x38d8, (q15_t)0x376f, (q15_t)0x3604, (q15_t)0x3496, (q15_t)0x3326, (q15_t)0x31b5,
+  (q15_t)0x3041, (q15_t)0x2ecc, (q15_t)0x2d55, (q15_t)0x2bdc, (q15_t)0x2a61, (q15_t)0x28e5, (q15_t)0x2767, (q15_t)0x25e8,
+  (q15_t)0x2467, (q15_t)0x22e5, (q15_t)0x2161, (q15_t)0x1fdc, (q15_t)0x1e56, (q15_t)0x1ccf, (q15_t)0x1b47, (q15_t)0x19bd,
+  (q15_t)0x1833, (q15_t)0x16a8, (q15_t)0x151b, (q15_t)0x138e, (q15_t)0x1201, (q15_t)0x1072, (q15_t)0xee3, (q15_t)0xd53,
+  (q15_t)0xbc3, (q15_t)0xa33, (q15_t)0x8a2, (q15_t)0x710, (q15_t)0x57f, (q15_t)0x3ed, (q15_t)0x25b, (q15_t)0xc9
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_512[512] = {
+  (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ff9, (q15_t)0x7ff7,
+  (q15_t)0x7ff4, (q15_t)0x7ff2, (q15_t)0x7fee, (q15_t)0x7feb, (q15_t)0x7fe7, (q15_t)0x7fe3, (q15_t)0x7fdf, (q15_t)0x7fda,
+  (q15_t)0x7fd6, (q15_t)0x7fd0, (q15_t)0x7fcb, (q15_t)0x7fc5, (q15_t)0x7fbf, (q15_t)0x7fb8, (q15_t)0x7fb1, (q15_t)0x7faa,
+  (q15_t)0x7fa3, (q15_t)0x7f9b, (q15_t)0x7f93, (q15_t)0x7f8b, (q15_t)0x7f82, (q15_t)0x7f79, (q15_t)0x7f70, (q15_t)0x7f67,
+  (q15_t)0x7f5d, (q15_t)0x7f53, (q15_t)0x7f48, (q15_t)0x7f3d, (q15_t)0x7f32, (q15_t)0x7f27, (q15_t)0x7f1b, (q15_t)0x7f0f,
+  (q15_t)0x7f03, (q15_t)0x7ef6, (q15_t)0x7ee9, (q15_t)0x7edc, (q15_t)0x7ecf, (q15_t)0x7ec1, (q15_t)0x7eb3, (q15_t)0x7ea4,
+  (q15_t)0x7e95, (q15_t)0x7e86, (q15_t)0x7e77, (q15_t)0x7e67, (q15_t)0x7e57, (q15_t)0x7e47, (q15_t)0x7e37, (q15_t)0x7e26,
+  (q15_t)0x7e14, (q15_t)0x7e03, (q15_t)0x7df1, (q15_t)0x7ddf, (q15_t)0x7dcd, (q15_t)0x7dba, (q15_t)0x7da7, (q15_t)0x7d94,
+  (q15_t)0x7d80, (q15_t)0x7d6c, (q15_t)0x7d58, (q15_t)0x7d43, (q15_t)0x7d2f, (q15_t)0x7d19, (q15_t)0x7d04, (q15_t)0x7cee,
+  (q15_t)0x7cd8, (q15_t)0x7cc2, (q15_t)0x7cab, (q15_t)0x7c94, (q15_t)0x7c7d, (q15_t)0x7c66, (q15_t)0x7c4e, (q15_t)0x7c36,
+  (q15_t)0x7c1d, (q15_t)0x7c05, (q15_t)0x7beb, (q15_t)0x7bd2, (q15_t)0x7bb9, (q15_t)0x7b9f, (q15_t)0x7b84, (q15_t)0x7b6a,
+  (q15_t)0x7b4f, (q15_t)0x7b34, (q15_t)0x7b19, (q15_t)0x7afd, (q15_t)0x7ae1, (q15_t)0x7ac5, (q15_t)0x7aa8, (q15_t)0x7a8b,
+  (q15_t)0x7a6e, (q15_t)0x7a50, (q15_t)0x7a33, (q15_t)0x7a15, (q15_t)0x79f6, (q15_t)0x79d8, (q15_t)0x79b9, (q15_t)0x7999,
+  (q15_t)0x797a, (q15_t)0x795a, (q15_t)0x793a, (q15_t)0x7919, (q15_t)0x78f9, (q15_t)0x78d8, (q15_t)0x78b6, (q15_t)0x7895,
+  (q15_t)0x7873, (q15_t)0x7851, (q15_t)0x782e, (q15_t)0x780c, (q15_t)0x77e9, (q15_t)0x77c5, (q15_t)0x77a2, (q15_t)0x777e,
+  (q15_t)0x775a, (q15_t)0x7735, (q15_t)0x7710, (q15_t)0x76eb, (q15_t)0x76c6, (q15_t)0x76a0, (q15_t)0x767b, (q15_t)0x7654,
+  (q15_t)0x762e, (q15_t)0x7607, (q15_t)0x75e0, (q15_t)0x75b9, (q15_t)0x7591, (q15_t)0x7569, (q15_t)0x7541, (q15_t)0x7519,
+  (q15_t)0x74f0, (q15_t)0x74c7, (q15_t)0x749e, (q15_t)0x7474, (q15_t)0x744a, (q15_t)0x7420, (q15_t)0x73f6, (q15_t)0x73cb,
+  (q15_t)0x73a0, (q15_t)0x7375, (q15_t)0x7349, (q15_t)0x731d, (q15_t)0x72f1, (q15_t)0x72c5, (q15_t)0x7298, (q15_t)0x726b,
+  (q15_t)0x723e, (q15_t)0x7211, (q15_t)0x71e3, (q15_t)0x71b5, (q15_t)0x7186, (q15_t)0x7158, (q15_t)0x7129, (q15_t)0x70fa,
+  (q15_t)0x70cb, (q15_t)0x709b, (q15_t)0x706b, (q15_t)0x703b, (q15_t)0x700a, (q15_t)0x6fda, (q15_t)0x6fa9, (q15_t)0x6f77,
+  (q15_t)0x6f46, (q15_t)0x6f14, (q15_t)0x6ee2, (q15_t)0x6eaf, (q15_t)0x6e7d, (q15_t)0x6e4a, (q15_t)0x6e17, (q15_t)0x6de3,
+  (q15_t)0x6db0, (q15_t)0x6d7c, (q15_t)0x6d48, (q15_t)0x6d13, (q15_t)0x6cde, (q15_t)0x6ca9, (q15_t)0x6c74, (q15_t)0x6c3f,
+  (q15_t)0x6c09, (q15_t)0x6bd3, (q15_t)0x6b9c, (q15_t)0x6b66, (q15_t)0x6b2f, (q15_t)0x6af8, (q15_t)0x6ac1, (q15_t)0x6a89,
+  (q15_t)0x6a51, (q15_t)0x6a19, (q15_t)0x69e1, (q15_t)0x69a8, (q15_t)0x696f, (q15_t)0x6936, (q15_t)0x68fd, (q15_t)0x68c3,
+  (q15_t)0x6889, (q15_t)0x684f, (q15_t)0x6815, (q15_t)0x67da, (q15_t)0x679f, (q15_t)0x6764, (q15_t)0x6729, (q15_t)0x66ed,
+  (q15_t)0x66b1, (q15_t)0x6675, (q15_t)0x6639, (q15_t)0x65fc, (q15_t)0x65bf, (q15_t)0x6582, (q15_t)0x6545, (q15_t)0x6507,
+  (q15_t)0x64c9, (q15_t)0x648b, (q15_t)0x644d, (q15_t)0x640e, (q15_t)0x63cf, (q15_t)0x6390, (q15_t)0x6351, (q15_t)0x6311,
+  (q15_t)0x62d2, (q15_t)0x6292, (q15_t)0x6251, (q15_t)0x6211, (q15_t)0x61d0, (q15_t)0x618f, (q15_t)0x614e, (q15_t)0x610d,
+  (q15_t)0x60cb, (q15_t)0x6089, (q15_t)0x6047, (q15_t)0x6004, (q15_t)0x5fc2, (q15_t)0x5f7f, (q15_t)0x5f3c, (q15_t)0x5ef9,
+  (q15_t)0x5eb5, (q15_t)0x5e71, (q15_t)0x5e2d, (q15_t)0x5de9, (q15_t)0x5da5, (q15_t)0x5d60, (q15_t)0x5d1b, (q15_t)0x5cd6,
+  (q15_t)0x5c91, (q15_t)0x5c4b, (q15_t)0x5c06, (q15_t)0x5bc0, (q15_t)0x5b79, (q15_t)0x5b33, (q15_t)0x5aec, (q15_t)0x5aa5,
+  (q15_t)0x5a5e, (q15_t)0x5a17, (q15_t)0x59d0, (q15_t)0x5988, (q15_t)0x5940, (q15_t)0x58f8, (q15_t)0x58af, (q15_t)0x5867,
+  (q15_t)0x581e, (q15_t)0x57d5, (q15_t)0x578c, (q15_t)0x5742, (q15_t)0x56f9, (q15_t)0x56af, (q15_t)0x5665, (q15_t)0x561a,
+  (q15_t)0x55d0, (q15_t)0x5585, (q15_t)0x553a, (q15_t)0x54ef, (q15_t)0x54a4, (q15_t)0x5458, (q15_t)0x540d, (q15_t)0x53c1,
+  (q15_t)0x5375, (q15_t)0x5328, (q15_t)0x52dc, (q15_t)0x528f, (q15_t)0x5242, (q15_t)0x51f5, (q15_t)0x51a8, (q15_t)0x515a,
+  (q15_t)0x510c, (q15_t)0x50bf, (q15_t)0x5070, (q15_t)0x5022, (q15_t)0x4fd4, (q15_t)0x4f85, (q15_t)0x4f36, (q15_t)0x4ee7,
+  (q15_t)0x4e98, (q15_t)0x4e48, (q15_t)0x4df9, (q15_t)0x4da9, (q15_t)0x4d59, (q15_t)0x4d09, (q15_t)0x4cb8, (q15_t)0x4c68,
+  (q15_t)0x4c17, (q15_t)0x4bc6, (q15_t)0x4b75, (q15_t)0x4b24, (q15_t)0x4ad2, (q15_t)0x4a81, (q15_t)0x4a2f, (q15_t)0x49dd,
+  (q15_t)0x498a, (q15_t)0x4938, (q15_t)0x48e6, (q15_t)0x4893, (q15_t)0x4840, (q15_t)0x47ed, (q15_t)0x479a, (q15_t)0x4746,
+  (q15_t)0x46f3, (q15_t)0x469f, (q15_t)0x464b, (q15_t)0x45f7, (q15_t)0x45a3, (q15_t)0x454e, (q15_t)0x44fa, (q15_t)0x44a5,
+  (q15_t)0x4450, (q15_t)0x43fb, (q15_t)0x43a5, (q15_t)0x4350, (q15_t)0x42fa, (q15_t)0x42a5, (q15_t)0x424f, (q15_t)0x41f9,
+  (q15_t)0x41a2, (q15_t)0x414c, (q15_t)0x40f6, (q15_t)0x409f, (q15_t)0x4048, (q15_t)0x3ff1, (q15_t)0x3f9a, (q15_t)0x3f43,
+  (q15_t)0x3eeb, (q15_t)0x3e93, (q15_t)0x3e3c, (q15_t)0x3de4, (q15_t)0x3d8c, (q15_t)0x3d33, (q15_t)0x3cdb, (q15_t)0x3c83,
+  (q15_t)0x3c2a, (q15_t)0x3bd1, (q15_t)0x3b78, (q15_t)0x3b1f, (q15_t)0x3ac6, (q15_t)0x3a6c, (q15_t)0x3a13, (q15_t)0x39b9,
+  (q15_t)0x395f, (q15_t)0x3906, (q15_t)0x38ab, (q15_t)0x3851, (q15_t)0x37f7, (q15_t)0x379c, (q15_t)0x3742, (q15_t)0x36e7,
+  (q15_t)0x368c, (q15_t)0x3631, (q15_t)0x35d6, (q15_t)0x357b, (q15_t)0x351f, (q15_t)0x34c4, (q15_t)0x3468, (q15_t)0x340c,
+  (q15_t)0x33b0, (q15_t)0x3354, (q15_t)0x32f8, (q15_t)0x329c, (q15_t)0x3240, (q15_t)0x31e3, (q15_t)0x3186, (q15_t)0x312a,
+  (q15_t)0x30cd, (q15_t)0x3070, (q15_t)0x3013, (q15_t)0x2fb5, (q15_t)0x2f58, (q15_t)0x2efb, (q15_t)0x2e9d, (q15_t)0x2e3f,
+  (q15_t)0x2de2, (q15_t)0x2d84, (q15_t)0x2d26, (q15_t)0x2cc8, (q15_t)0x2c69, (q15_t)0x2c0b, (q15_t)0x2bad, (q15_t)0x2b4e,
+  (q15_t)0x2aef, (q15_t)0x2a91, (q15_t)0x2a32, (q15_t)0x29d3, (q15_t)0x2974, (q15_t)0x2915, (q15_t)0x28b5, (q15_t)0x2856,
+  (q15_t)0x27f6, (q15_t)0x2797, (q15_t)0x2737, (q15_t)0x26d8, (q15_t)0x2678, (q15_t)0x2618, (q15_t)0x25b8, (q15_t)0x2558,
+  (q15_t)0x24f7, (q15_t)0x2497, (q15_t)0x2437, (q15_t)0x23d6, (q15_t)0x2376, (q15_t)0x2315, (q15_t)0x22b4, (q15_t)0x2254,
+  (q15_t)0x21f3, (q15_t)0x2192, (q15_t)0x2131, (q15_t)0x20d0, (q15_t)0x206e, (q15_t)0x200d, (q15_t)0x1fac, (q15_t)0x1f4a,
+  (q15_t)0x1ee9, (q15_t)0x1e87, (q15_t)0x1e25, (q15_t)0x1dc4, (q15_t)0x1d62, (q15_t)0x1d00, (q15_t)0x1c9e, (q15_t)0x1c3c,
+  (q15_t)0x1bda, (q15_t)0x1b78, (q15_t)0x1b16, (q15_t)0x1ab3, (q15_t)0x1a51, (q15_t)0x19ef, (q15_t)0x198c, (q15_t)0x192a,
+  (q15_t)0x18c7, (q15_t)0x1864, (q15_t)0x1802, (q15_t)0x179f, (q15_t)0x173c, (q15_t)0x16d9, (q15_t)0x1676, (q15_t)0x1613,
+  (q15_t)0x15b0, (q15_t)0x154d, (q15_t)0x14ea, (q15_t)0x1487, (q15_t)0x1423, (q15_t)0x13c0, (q15_t)0x135d, (q15_t)0x12f9,
+  (q15_t)0x1296, (q15_t)0x1232, (q15_t)0x11cf, (q15_t)0x116b, (q15_t)0x1108, (q15_t)0x10a4, (q15_t)0x1040, (q15_t)0xfdd,
+  (q15_t)0xf79, (q15_t)0xf15, (q15_t)0xeb1, (q15_t)0xe4d, (q15_t)0xde9, (q15_t)0xd85, (q15_t)0xd21, (q15_t)0xcbd,
+  (q15_t)0xc59, (q15_t)0xbf5, (q15_t)0xb91, (q15_t)0xb2d, (q15_t)0xac9, (q15_t)0xa65, (q15_t)0xa00, (q15_t)0x99c,
+  (q15_t)0x938, (q15_t)0x8d4, (q15_t)0x86f, (q15_t)0x80b, (q15_t)0x7a7, (q15_t)0x742, (q15_t)0x6de, (q15_t)0x67a,
+  (q15_t)0x615, (q15_t)0x5b1, (q15_t)0x54c, (q15_t)0x4e8, (q15_t)0x483, (q15_t)0x41f, (q15_t)0x3ba, (q15_t)0x356,
+  (q15_t)0x2f1, (q15_t)0x28d, (q15_t)0x228, (q15_t)0x1c4, (q15_t)0x15f, (q15_t)0xfb, (q15_t)0x96, (q15_t)0x32
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_2048[2048] = {
+  (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
+  (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd,
+  (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa,
+  (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6,
+  (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff1, (q15_t)0x7ff0,
+  (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7fea,
+  (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe3, (q15_t)0x7fe2,
+  (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fda, (q15_t)0x7fd9,
+  (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd0, (q15_t)0x7fce,
+  (q15_t)0x7fcd, (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc4, (q15_t)0x7fc3,
+  (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fbe, (q15_t)0x7fbc, (q15_t)0x7fbb, (q15_t)0x7fb9, (q15_t)0x7fb7, (q15_t)0x7fb6,
+  (q15_t)0x7fb4, (q15_t)0x7fb2, (q15_t)0x7fb1, (q15_t)0x7faf, (q15_t)0x7fad, (q15_t)0x7fab, (q15_t)0x7fa9, (q15_t)0x7fa8,
+  (q15_t)0x7fa6, (q15_t)0x7fa4, (q15_t)0x7fa2, (q15_t)0x7fa0, (q15_t)0x7f9e, (q15_t)0x7f9c, (q15_t)0x7f9a, (q15_t)0x7f98,
+  (q15_t)0x7f96, (q15_t)0x7f94, (q15_t)0x7f92, (q15_t)0x7f90, (q15_t)0x7f8e, (q15_t)0x7f8c, (q15_t)0x7f8a, (q15_t)0x7f88,
+  (q15_t)0x7f86, (q15_t)0x7f83, (q15_t)0x7f81, (q15_t)0x7f7f, (q15_t)0x7f7d, (q15_t)0x7f7b, (q15_t)0x7f78, (q15_t)0x7f76,
+  (q15_t)0x7f74, (q15_t)0x7f71, (q15_t)0x7f6f, (q15_t)0x7f6d, (q15_t)0x7f6a, (q15_t)0x7f68, (q15_t)0x7f65, (q15_t)0x7f63,
+  (q15_t)0x7f60, (q15_t)0x7f5e, (q15_t)0x7f5b, (q15_t)0x7f59, (q15_t)0x7f56, (q15_t)0x7f54, (q15_t)0x7f51, (q15_t)0x7f4f,
+  (q15_t)0x7f4c, (q15_t)0x7f49, (q15_t)0x7f47, (q15_t)0x7f44, (q15_t)0x7f41, (q15_t)0x7f3f, (q15_t)0x7f3c, (q15_t)0x7f39,
+  (q15_t)0x7f36, (q15_t)0x7f34, (q15_t)0x7f31, (q15_t)0x7f2e, (q15_t)0x7f2b, (q15_t)0x7f28, (q15_t)0x7f25, (q15_t)0x7f23,
+  (q15_t)0x7f20, (q15_t)0x7f1d, (q15_t)0x7f1a, (q15_t)0x7f17, (q15_t)0x7f14, (q15_t)0x7f11, (q15_t)0x7f0e, (q15_t)0x7f0b,
+  (q15_t)0x7f08, (q15_t)0x7f04, (q15_t)0x7f01, (q15_t)0x7efe, (q15_t)0x7efb, (q15_t)0x7ef8, (q15_t)0x7ef5, (q15_t)0x7ef1,
+  (q15_t)0x7eee, (q15_t)0x7eeb, (q15_t)0x7ee8, (q15_t)0x7ee4, (q15_t)0x7ee1, (q15_t)0x7ede, (q15_t)0x7eda, (q15_t)0x7ed7,
+  (q15_t)0x7ed4, (q15_t)0x7ed0, (q15_t)0x7ecd, (q15_t)0x7ec9, (q15_t)0x7ec6, (q15_t)0x7ec3, (q15_t)0x7ebf, (q15_t)0x7ebb,
+  (q15_t)0x7eb8, (q15_t)0x7eb4, (q15_t)0x7eb1, (q15_t)0x7ead, (q15_t)0x7eaa, (q15_t)0x7ea6, (q15_t)0x7ea2, (q15_t)0x7e9f,
+  (q15_t)0x7e9b, (q15_t)0x7e97, (q15_t)0x7e94, (q15_t)0x7e90, (q15_t)0x7e8c, (q15_t)0x7e88, (q15_t)0x7e84, (q15_t)0x7e81,
+  (q15_t)0x7e7d, (q15_t)0x7e79, (q15_t)0x7e75, (q15_t)0x7e71, (q15_t)0x7e6d, (q15_t)0x7e69, (q15_t)0x7e65, (q15_t)0x7e61,
+  (q15_t)0x7e5d, (q15_t)0x7e59, (q15_t)0x7e55, (q15_t)0x7e51, (q15_t)0x7e4d, (q15_t)0x7e49, (q15_t)0x7e45, (q15_t)0x7e41,
+  (q15_t)0x7e3d, (q15_t)0x7e39, (q15_t)0x7e34, (q15_t)0x7e30, (q15_t)0x7e2c, (q15_t)0x7e28, (q15_t)0x7e24, (q15_t)0x7e1f,
+  (q15_t)0x7e1b, (q15_t)0x7e17, (q15_t)0x7e12, (q15_t)0x7e0e, (q15_t)0x7e0a, (q15_t)0x7e05, (q15_t)0x7e01, (q15_t)0x7dfc,
+  (q15_t)0x7df8, (q15_t)0x7df3, (q15_t)0x7def, (q15_t)0x7dea, (q15_t)0x7de6, (q15_t)0x7de1, (q15_t)0x7ddd, (q15_t)0x7dd8,
+  (q15_t)0x7dd4, (q15_t)0x7dcf, (q15_t)0x7dca, (q15_t)0x7dc6, (q15_t)0x7dc1, (q15_t)0x7dbc, (q15_t)0x7db8, (q15_t)0x7db3,
+  (q15_t)0x7dae, (q15_t)0x7da9, (q15_t)0x7da5, (q15_t)0x7da0, (q15_t)0x7d9b, (q15_t)0x7d96, (q15_t)0x7d91, (q15_t)0x7d8c,
+  (q15_t)0x7d87, (q15_t)0x7d82, (q15_t)0x7d7e, (q15_t)0x7d79, (q15_t)0x7d74, (q15_t)0x7d6f, (q15_t)0x7d6a, (q15_t)0x7d65,
+  (q15_t)0x7d60, (q15_t)0x7d5a, (q15_t)0x7d55, (q15_t)0x7d50, (q15_t)0x7d4b, (q15_t)0x7d46, (q15_t)0x7d41, (q15_t)0x7d3c,
+  (q15_t)0x7d36, (q15_t)0x7d31, (q15_t)0x7d2c, (q15_t)0x7d27, (q15_t)0x7d21, (q15_t)0x7d1c, (q15_t)0x7d17, (q15_t)0x7d11,
+  (q15_t)0x7d0c, (q15_t)0x7d07, (q15_t)0x7d01, (q15_t)0x7cfc, (q15_t)0x7cf6, (q15_t)0x7cf1, (q15_t)0x7cec, (q15_t)0x7ce6,
+  (q15_t)0x7ce1, (q15_t)0x7cdb, (q15_t)0x7cd5, (q15_t)0x7cd0, (q15_t)0x7cca, (q15_t)0x7cc5, (q15_t)0x7cbf, (q15_t)0x7cb9,
+  (q15_t)0x7cb4, (q15_t)0x7cae, (q15_t)0x7ca8, (q15_t)0x7ca3, (q15_t)0x7c9d, (q15_t)0x7c97, (q15_t)0x7c91, (q15_t)0x7c8c,
+  (q15_t)0x7c86, (q15_t)0x7c80, (q15_t)0x7c7a, (q15_t)0x7c74, (q15_t)0x7c6e, (q15_t)0x7c69, (q15_t)0x7c63, (q15_t)0x7c5d,
+  (q15_t)0x7c57, (q15_t)0x7c51, (q15_t)0x7c4b, (q15_t)0x7c45, (q15_t)0x7c3f, (q15_t)0x7c39, (q15_t)0x7c33, (q15_t)0x7c2d,
+  (q15_t)0x7c26, (q15_t)0x7c20, (q15_t)0x7c1a, (q15_t)0x7c14, (q15_t)0x7c0e, (q15_t)0x7c08, (q15_t)0x7c01, (q15_t)0x7bfb,
+  (q15_t)0x7bf5, (q15_t)0x7bef, (q15_t)0x7be8, (q15_t)0x7be2, (q15_t)0x7bdc, (q15_t)0x7bd5, (q15_t)0x7bcf, (q15_t)0x7bc9,
+  (q15_t)0x7bc2, (q15_t)0x7bbc, (q15_t)0x7bb5, (q15_t)0x7baf, (q15_t)0x7ba8, (q15_t)0x7ba2, (q15_t)0x7b9b, (q15_t)0x7b95,
+  (q15_t)0x7b8e, (q15_t)0x7b88, (q15_t)0x7b81, (q15_t)0x7b7a, (q15_t)0x7b74, (q15_t)0x7b6d, (q15_t)0x7b67, (q15_t)0x7b60,
+  (q15_t)0x7b59, (q15_t)0x7b52, (q15_t)0x7b4c, (q15_t)0x7b45, (q15_t)0x7b3e, (q15_t)0x7b37, (q15_t)0x7b31, (q15_t)0x7b2a,
+  (q15_t)0x7b23, (q15_t)0x7b1c, (q15_t)0x7b15, (q15_t)0x7b0e, (q15_t)0x7b07, (q15_t)0x7b00, (q15_t)0x7af9, (q15_t)0x7af2,
+  (q15_t)0x7aeb, (q15_t)0x7ae4, (q15_t)0x7add, (q15_t)0x7ad6, (q15_t)0x7acf, (q15_t)0x7ac8, (q15_t)0x7ac1, (q15_t)0x7aba,
+  (q15_t)0x7ab3, (q15_t)0x7aac, (q15_t)0x7aa4, (q15_t)0x7a9d, (q15_t)0x7a96, (q15_t)0x7a8f, (q15_t)0x7a87, (q15_t)0x7a80,
+  (q15_t)0x7a79, (q15_t)0x7a72, (q15_t)0x7a6a, (q15_t)0x7a63, (q15_t)0x7a5c, (q15_t)0x7a54, (q15_t)0x7a4d, (q15_t)0x7a45,
+  (q15_t)0x7a3e, (q15_t)0x7a36, (q15_t)0x7a2f, (q15_t)0x7a27, (q15_t)0x7a20, (q15_t)0x7a18, (q15_t)0x7a11, (q15_t)0x7a09,
+  (q15_t)0x7a02, (q15_t)0x79fa, (q15_t)0x79f2, (q15_t)0x79eb, (q15_t)0x79e3, (q15_t)0x79db, (q15_t)0x79d4, (q15_t)0x79cc,
+  (q15_t)0x79c4, (q15_t)0x79bc, (q15_t)0x79b5, (q15_t)0x79ad, (q15_t)0x79a5, (q15_t)0x799d, (q15_t)0x7995, (q15_t)0x798e,
+  (q15_t)0x7986, (q15_t)0x797e, (q15_t)0x7976, (q15_t)0x796e, (q15_t)0x7966, (q15_t)0x795e, (q15_t)0x7956, (q15_t)0x794e,
+  (q15_t)0x7946, (q15_t)0x793e, (q15_t)0x7936, (q15_t)0x792e, (q15_t)0x7926, (q15_t)0x791e, (q15_t)0x7915, (q15_t)0x790d,
+  (q15_t)0x7905, (q15_t)0x78fd, (q15_t)0x78f5, (q15_t)0x78ec, (q15_t)0x78e4, (q15_t)0x78dc, (q15_t)0x78d4, (q15_t)0x78cb,
+  (q15_t)0x78c3, (q15_t)0x78bb, (q15_t)0x78b2, (q15_t)0x78aa, (q15_t)0x78a2, (q15_t)0x7899, (q15_t)0x7891, (q15_t)0x7888,
+  (q15_t)0x7880, (q15_t)0x7877, (q15_t)0x786f, (q15_t)0x7866, (q15_t)0x785e, (q15_t)0x7855, (q15_t)0x784d, (q15_t)0x7844,
+  (q15_t)0x783b, (q15_t)0x7833, (q15_t)0x782a, (q15_t)0x7821, (q15_t)0x7819, (q15_t)0x7810, (q15_t)0x7807, (q15_t)0x77ff,
+  (q15_t)0x77f6, (q15_t)0x77ed, (q15_t)0x77e4, (q15_t)0x77db, (q15_t)0x77d3, (q15_t)0x77ca, (q15_t)0x77c1, (q15_t)0x77b8,
+  (q15_t)0x77af, (q15_t)0x77a6, (q15_t)0x779d, (q15_t)0x7794, (q15_t)0x778b, (q15_t)0x7782, (q15_t)0x7779, (q15_t)0x7770,
+  (q15_t)0x7767, (q15_t)0x775e, (q15_t)0x7755, (q15_t)0x774c, (q15_t)0x7743, (q15_t)0x773a, (q15_t)0x7731, (q15_t)0x7727,
+  (q15_t)0x771e, (q15_t)0x7715, (q15_t)0x770c, (q15_t)0x7703, (q15_t)0x76f9, (q15_t)0x76f0, (q15_t)0x76e7, (q15_t)0x76dd,
+  (q15_t)0x76d4, (q15_t)0x76cb, (q15_t)0x76c1, (q15_t)0x76b8, (q15_t)0x76af, (q15_t)0x76a5, (q15_t)0x769c, (q15_t)0x7692,
+  (q15_t)0x7689, (q15_t)0x767f, (q15_t)0x7676, (q15_t)0x766c, (q15_t)0x7663, (q15_t)0x7659, (q15_t)0x7650, (q15_t)0x7646,
+  (q15_t)0x763c, (q15_t)0x7633, (q15_t)0x7629, (q15_t)0x761f, (q15_t)0x7616, (q15_t)0x760c, (q15_t)0x7602, (q15_t)0x75f9,
+  (q15_t)0x75ef, (q15_t)0x75e5, (q15_t)0x75db, (q15_t)0x75d1, (q15_t)0x75c8, (q15_t)0x75be, (q15_t)0x75b4, (q15_t)0x75aa,
+  (q15_t)0x75a0, (q15_t)0x7596, (q15_t)0x758c, (q15_t)0x7582, (q15_t)0x7578, (q15_t)0x756e, (q15_t)0x7564, (q15_t)0x755a,
+  (q15_t)0x7550, (q15_t)0x7546, (q15_t)0x753c, (q15_t)0x7532, (q15_t)0x7528, (q15_t)0x751e, (q15_t)0x7514, (q15_t)0x7509,
+  (q15_t)0x74ff, (q15_t)0x74f5, (q15_t)0x74eb, (q15_t)0x74e1, (q15_t)0x74d6, (q15_t)0x74cc, (q15_t)0x74c2, (q15_t)0x74b7,
+  (q15_t)0x74ad, (q15_t)0x74a3, (q15_t)0x7498, (q15_t)0x748e, (q15_t)0x7484, (q15_t)0x7479, (q15_t)0x746f, (q15_t)0x7464,
+  (q15_t)0x745a, (q15_t)0x744f, (q15_t)0x7445, (q15_t)0x743a, (q15_t)0x7430, (q15_t)0x7425, (q15_t)0x741b, (q15_t)0x7410,
+  (q15_t)0x7406, (q15_t)0x73fb, (q15_t)0x73f0, (q15_t)0x73e6, (q15_t)0x73db, (q15_t)0x73d0, (q15_t)0x73c6, (q15_t)0x73bb,
+  (q15_t)0x73b0, (q15_t)0x73a5, (q15_t)0x739b, (q15_t)0x7390, (q15_t)0x7385, (q15_t)0x737a, (q15_t)0x736f, (q15_t)0x7364,
+  (q15_t)0x7359, (q15_t)0x734f, (q15_t)0x7344, (q15_t)0x7339, (q15_t)0x732e, (q15_t)0x7323, (q15_t)0x7318, (q15_t)0x730d,
+  (q15_t)0x7302, (q15_t)0x72f7, (q15_t)0x72ec, (q15_t)0x72e1, (q15_t)0x72d5, (q15_t)0x72ca, (q15_t)0x72bf, (q15_t)0x72b4,
+  (q15_t)0x72a9, (q15_t)0x729e, (q15_t)0x7293, (q15_t)0x7287, (q15_t)0x727c, (q15_t)0x7271, (q15_t)0x7266, (q15_t)0x725a,
+  (q15_t)0x724f, (q15_t)0x7244, (q15_t)0x7238, (q15_t)0x722d, (q15_t)0x7222, (q15_t)0x7216, (q15_t)0x720b, (q15_t)0x71ff,
+  (q15_t)0x71f4, (q15_t)0x71e9, (q15_t)0x71dd, (q15_t)0x71d2, (q15_t)0x71c6, (q15_t)0x71bb, (q15_t)0x71af, (q15_t)0x71a3,
+  (q15_t)0x7198, (q15_t)0x718c, (q15_t)0x7181, (q15_t)0x7175, (q15_t)0x7169, (q15_t)0x715e, (q15_t)0x7152, (q15_t)0x7146,
+  (q15_t)0x713b, (q15_t)0x712f, (q15_t)0x7123, (q15_t)0x7117, (q15_t)0x710c, (q15_t)0x7100, (q15_t)0x70f4, (q15_t)0x70e8,
+  (q15_t)0x70dc, (q15_t)0x70d1, (q15_t)0x70c5, (q15_t)0x70b9, (q15_t)0x70ad, (q15_t)0x70a1, (q15_t)0x7095, (q15_t)0x7089,
+  (q15_t)0x707d, (q15_t)0x7071, (q15_t)0x7065, (q15_t)0x7059, (q15_t)0x704d, (q15_t)0x7041, (q15_t)0x7035, (q15_t)0x7029,
+  (q15_t)0x701d, (q15_t)0x7010, (q15_t)0x7004, (q15_t)0x6ff8, (q15_t)0x6fec, (q15_t)0x6fe0, (q15_t)0x6fd3, (q15_t)0x6fc7,
+  (q15_t)0x6fbb, (q15_t)0x6faf, (q15_t)0x6fa2, (q15_t)0x6f96, (q15_t)0x6f8a, (q15_t)0x6f7d, (q15_t)0x6f71, (q15_t)0x6f65,
+  (q15_t)0x6f58, (q15_t)0x6f4c, (q15_t)0x6f3f, (q15_t)0x6f33, (q15_t)0x6f27, (q15_t)0x6f1a, (q15_t)0x6f0e, (q15_t)0x6f01,
+  (q15_t)0x6ef5, (q15_t)0x6ee8, (q15_t)0x6edc, (q15_t)0x6ecf, (q15_t)0x6ec2, (q15_t)0x6eb6, (q15_t)0x6ea9, (q15_t)0x6e9c,
+  (q15_t)0x6e90, (q15_t)0x6e83, (q15_t)0x6e76, (q15_t)0x6e6a, (q15_t)0x6e5d, (q15_t)0x6e50, (q15_t)0x6e44, (q15_t)0x6e37,
+  (q15_t)0x6e2a, (q15_t)0x6e1d, (q15_t)0x6e10, (q15_t)0x6e04, (q15_t)0x6df7, (q15_t)0x6dea, (q15_t)0x6ddd, (q15_t)0x6dd0,
+  (q15_t)0x6dc3, (q15_t)0x6db6, (q15_t)0x6da9, (q15_t)0x6d9c, (q15_t)0x6d8f, (q15_t)0x6d82, (q15_t)0x6d75, (q15_t)0x6d68,
+  (q15_t)0x6d5b, (q15_t)0x6d4e, (q15_t)0x6d41, (q15_t)0x6d34, (q15_t)0x6d27, (q15_t)0x6d1a, (q15_t)0x6d0c, (q15_t)0x6cff,
+  (q15_t)0x6cf2, (q15_t)0x6ce5, (q15_t)0x6cd8, (q15_t)0x6cca, (q15_t)0x6cbd, (q15_t)0x6cb0, (q15_t)0x6ca3, (q15_t)0x6c95,
+  (q15_t)0x6c88, (q15_t)0x6c7b, (q15_t)0x6c6d, (q15_t)0x6c60, (q15_t)0x6c53, (q15_t)0x6c45, (q15_t)0x6c38, (q15_t)0x6c2a,
+  (q15_t)0x6c1d, (q15_t)0x6c0f, (q15_t)0x6c02, (q15_t)0x6bf5, (q15_t)0x6be7, (q15_t)0x6bd9, (q15_t)0x6bcc, (q15_t)0x6bbe,
+  (q15_t)0x6bb1, (q15_t)0x6ba3, (q15_t)0x6b96, (q15_t)0x6b88, (q15_t)0x6b7a, (q15_t)0x6b6d, (q15_t)0x6b5f, (q15_t)0x6b51,
+  (q15_t)0x6b44, (q15_t)0x6b36, (q15_t)0x6b28, (q15_t)0x6b1a, (q15_t)0x6b0d, (q15_t)0x6aff, (q15_t)0x6af1, (q15_t)0x6ae3,
+  (q15_t)0x6ad5, (q15_t)0x6ac8, (q15_t)0x6aba, (q15_t)0x6aac, (q15_t)0x6a9e, (q15_t)0x6a90, (q15_t)0x6a82, (q15_t)0x6a74,
+  (q15_t)0x6a66, (q15_t)0x6a58, (q15_t)0x6a4a, (q15_t)0x6a3c, (q15_t)0x6a2e, (q15_t)0x6a20, (q15_t)0x6a12, (q15_t)0x6a04,
+  (q15_t)0x69f6, (q15_t)0x69e8, (q15_t)0x69da, (q15_t)0x69cb, (q15_t)0x69bd, (q15_t)0x69af, (q15_t)0x69a1, (q15_t)0x6993,
+  (q15_t)0x6985, (q15_t)0x6976, (q15_t)0x6968, (q15_t)0x695a, (q15_t)0x694b, (q15_t)0x693d, (q15_t)0x692f, (q15_t)0x6921,
+  (q15_t)0x6912, (q15_t)0x6904, (q15_t)0x68f5, (q15_t)0x68e7, (q15_t)0x68d9, (q15_t)0x68ca, (q15_t)0x68bc, (q15_t)0x68ad,
+  (q15_t)0x689f, (q15_t)0x6890, (q15_t)0x6882, (q15_t)0x6873, (q15_t)0x6865, (q15_t)0x6856, (q15_t)0x6848, (q15_t)0x6839,
+  (q15_t)0x682b, (q15_t)0x681c, (q15_t)0x680d, (q15_t)0x67ff, (q15_t)0x67f0, (q15_t)0x67e1, (q15_t)0x67d3, (q15_t)0x67c4,
+  (q15_t)0x67b5, (q15_t)0x67a6, (q15_t)0x6798, (q15_t)0x6789, (q15_t)0x677a, (q15_t)0x676b, (q15_t)0x675d, (q15_t)0x674e,
+  (q15_t)0x673f, (q15_t)0x6730, (q15_t)0x6721, (q15_t)0x6712, (q15_t)0x6703, (q15_t)0x66f4, (q15_t)0x66e5, (q15_t)0x66d6,
+  (q15_t)0x66c8, (q15_t)0x66b9, (q15_t)0x66aa, (q15_t)0x669b, (q15_t)0x668b, (q15_t)0x667c, (q15_t)0x666d, (q15_t)0x665e,
+  (q15_t)0x664f, (q15_t)0x6640, (q15_t)0x6631, (q15_t)0x6622, (q15_t)0x6613, (q15_t)0x6603, (q15_t)0x65f4, (q15_t)0x65e5,
+  (q15_t)0x65d6, (q15_t)0x65c7, (q15_t)0x65b7, (q15_t)0x65a8, (q15_t)0x6599, (q15_t)0x658a, (q15_t)0x657a, (q15_t)0x656b,
+  (q15_t)0x655c, (q15_t)0x654c, (q15_t)0x653d, (q15_t)0x652d, (q15_t)0x651e, (q15_t)0x650f, (q15_t)0x64ff, (q15_t)0x64f0,
+  (q15_t)0x64e0, (q15_t)0x64d1, (q15_t)0x64c1, (q15_t)0x64b2, (q15_t)0x64a2, (q15_t)0x6493, (q15_t)0x6483, (q15_t)0x6474,
+  (q15_t)0x6464, (q15_t)0x6454, (q15_t)0x6445, (q15_t)0x6435, (q15_t)0x6426, (q15_t)0x6416, (q15_t)0x6406, (q15_t)0x63f7,
+  (q15_t)0x63e7, (q15_t)0x63d7, (q15_t)0x63c7, (q15_t)0x63b8, (q15_t)0x63a8, (q15_t)0x6398, (q15_t)0x6388, (q15_t)0x6378,
+  (q15_t)0x6369, (q15_t)0x6359, (q15_t)0x6349, (q15_t)0x6339, (q15_t)0x6329, (q15_t)0x6319, (q15_t)0x6309, (q15_t)0x62f9,
+  (q15_t)0x62ea, (q15_t)0x62da, (q15_t)0x62ca, (q15_t)0x62ba, (q15_t)0x62aa, (q15_t)0x629a, (q15_t)0x628a, (q15_t)0x627a,
+  (q15_t)0x6269, (q15_t)0x6259, (q15_t)0x6249, (q15_t)0x6239, (q15_t)0x6229, (q15_t)0x6219, (q15_t)0x6209, (q15_t)0x61f9,
+  (q15_t)0x61e8, (q15_t)0x61d8, (q15_t)0x61c8, (q15_t)0x61b8, (q15_t)0x61a8, (q15_t)0x6197, (q15_t)0x6187, (q15_t)0x6177,
+  (q15_t)0x6166, (q15_t)0x6156, (q15_t)0x6146, (q15_t)0x6135, (q15_t)0x6125, (q15_t)0x6115, (q15_t)0x6104, (q15_t)0x60f4,
+  (q15_t)0x60e4, (q15_t)0x60d3, (q15_t)0x60c3, (q15_t)0x60b2, (q15_t)0x60a2, (q15_t)0x6091, (q15_t)0x6081, (q15_t)0x6070,
+  (q15_t)0x6060, (q15_t)0x604f, (q15_t)0x603f, (q15_t)0x602e, (q15_t)0x601d, (q15_t)0x600d, (q15_t)0x5ffc, (q15_t)0x5fec,
+  (q15_t)0x5fdb, (q15_t)0x5fca, (q15_t)0x5fba, (q15_t)0x5fa9, (q15_t)0x5f98, (q15_t)0x5f87, (q15_t)0x5f77, (q15_t)0x5f66,
+  (q15_t)0x5f55, (q15_t)0x5f44, (q15_t)0x5f34, (q15_t)0x5f23, (q15_t)0x5f12, (q15_t)0x5f01, (q15_t)0x5ef0, (q15_t)0x5edf,
+  (q15_t)0x5ecf, (q15_t)0x5ebe, (q15_t)0x5ead, (q15_t)0x5e9c, (q15_t)0x5e8b, (q15_t)0x5e7a, (q15_t)0x5e69, (q15_t)0x5e58,
+  (q15_t)0x5e47, (q15_t)0x5e36, (q15_t)0x5e25, (q15_t)0x5e14, (q15_t)0x5e03, (q15_t)0x5df2, (q15_t)0x5de1, (q15_t)0x5dd0,
+  (q15_t)0x5dbf, (q15_t)0x5dad, (q15_t)0x5d9c, (q15_t)0x5d8b, (q15_t)0x5d7a, (q15_t)0x5d69, (q15_t)0x5d58, (q15_t)0x5d46,
+  (q15_t)0x5d35, (q15_t)0x5d24, (q15_t)0x5d13, (q15_t)0x5d01, (q15_t)0x5cf0, (q15_t)0x5cdf, (q15_t)0x5cce, (q15_t)0x5cbc,
+  (q15_t)0x5cab, (q15_t)0x5c9a, (q15_t)0x5c88, (q15_t)0x5c77, (q15_t)0x5c66, (q15_t)0x5c54, (q15_t)0x5c43, (q15_t)0x5c31,
+  (q15_t)0x5c20, (q15_t)0x5c0e, (q15_t)0x5bfd, (q15_t)0x5beb, (q15_t)0x5bda, (q15_t)0x5bc8, (q15_t)0x5bb7, (q15_t)0x5ba5,
+  (q15_t)0x5b94, (q15_t)0x5b82, (q15_t)0x5b71, (q15_t)0x5b5f, (q15_t)0x5b4d, (q15_t)0x5b3c, (q15_t)0x5b2a, (q15_t)0x5b19,
+  (q15_t)0x5b07, (q15_t)0x5af5, (q15_t)0x5ae4, (q15_t)0x5ad2, (q15_t)0x5ac0, (q15_t)0x5aae, (q15_t)0x5a9d, (q15_t)0x5a8b,
+  (q15_t)0x5a79, (q15_t)0x5a67, (q15_t)0x5a56, (q15_t)0x5a44, (q15_t)0x5a32, (q15_t)0x5a20, (q15_t)0x5a0e, (q15_t)0x59fc,
+  (q15_t)0x59ea, (q15_t)0x59d9, (q15_t)0x59c7, (q15_t)0x59b5, (q15_t)0x59a3, (q15_t)0x5991, (q15_t)0x597f, (q15_t)0x596d,
+  (q15_t)0x595b, (q15_t)0x5949, (q15_t)0x5937, (q15_t)0x5925, (q15_t)0x5913, (q15_t)0x5901, (q15_t)0x58ef, (q15_t)0x58dd,
+  (q15_t)0x58cb, (q15_t)0x58b8, (q15_t)0x58a6, (q15_t)0x5894, (q15_t)0x5882, (q15_t)0x5870, (q15_t)0x585e, (q15_t)0x584b,
+  (q15_t)0x5839, (q15_t)0x5827, (q15_t)0x5815, (q15_t)0x5803, (q15_t)0x57f0, (q15_t)0x57de, (q15_t)0x57cc, (q15_t)0x57b9,
+  (q15_t)0x57a7, (q15_t)0x5795, (q15_t)0x5783, (q15_t)0x5770, (q15_t)0x575e, (q15_t)0x574b, (q15_t)0x5739, (q15_t)0x5727,
+  (q15_t)0x5714, (q15_t)0x5702, (q15_t)0x56ef, (q15_t)0x56dd, (q15_t)0x56ca, (q15_t)0x56b8, (q15_t)0x56a5, (q15_t)0x5693,
+  (q15_t)0x5680, (q15_t)0x566e, (q15_t)0x565b, (q15_t)0x5649, (q15_t)0x5636, (q15_t)0x5624, (q15_t)0x5611, (q15_t)0x55fe,
+  (q15_t)0x55ec, (q15_t)0x55d9, (q15_t)0x55c7, (q15_t)0x55b4, (q15_t)0x55a1, (q15_t)0x558f, (q15_t)0x557c, (q15_t)0x5569,
+  (q15_t)0x5556, (q15_t)0x5544, (q15_t)0x5531, (q15_t)0x551e, (q15_t)0x550b, (q15_t)0x54f9, (q15_t)0x54e6, (q15_t)0x54d3,
+  (q15_t)0x54c0, (q15_t)0x54ad, (q15_t)0x549a, (q15_t)0x5488, (q15_t)0x5475, (q15_t)0x5462, (q15_t)0x544f, (q15_t)0x543c,
+  (q15_t)0x5429, (q15_t)0x5416, (q15_t)0x5403, (q15_t)0x53f0, (q15_t)0x53dd, (q15_t)0x53ca, (q15_t)0x53b7, (q15_t)0x53a4,
+  (q15_t)0x5391, (q15_t)0x537e, (q15_t)0x536b, (q15_t)0x5358, (q15_t)0x5345, (q15_t)0x5332, (q15_t)0x531f, (q15_t)0x530c,
+  (q15_t)0x52f8, (q15_t)0x52e5, (q15_t)0x52d2, (q15_t)0x52bf, (q15_t)0x52ac, (q15_t)0x5299, (q15_t)0x5285, (q15_t)0x5272,
+  (q15_t)0x525f, (q15_t)0x524c, (q15_t)0x5238, (q15_t)0x5225, (q15_t)0x5212, (q15_t)0x51ff, (q15_t)0x51eb, (q15_t)0x51d8,
+  (q15_t)0x51c5, (q15_t)0x51b1, (q15_t)0x519e, (q15_t)0x518b, (q15_t)0x5177, (q15_t)0x5164, (q15_t)0x5150, (q15_t)0x513d,
+  (q15_t)0x512a, (q15_t)0x5116, (q15_t)0x5103, (q15_t)0x50ef, (q15_t)0x50dc, (q15_t)0x50c8, (q15_t)0x50b5, (q15_t)0x50a1,
+  (q15_t)0x508e, (q15_t)0x507a, (q15_t)0x5067, (q15_t)0x5053, (q15_t)0x503f, (q15_t)0x502c, (q15_t)0x5018, (q15_t)0x5005,
+  (q15_t)0x4ff1, (q15_t)0x4fdd, (q15_t)0x4fca, (q15_t)0x4fb6, (q15_t)0x4fa2, (q15_t)0x4f8f, (q15_t)0x4f7b, (q15_t)0x4f67,
+  (q15_t)0x4f54, (q15_t)0x4f40, (q15_t)0x4f2c, (q15_t)0x4f18, (q15_t)0x4f05, (q15_t)0x4ef1, (q15_t)0x4edd, (q15_t)0x4ec9,
+  (q15_t)0x4eb6, (q15_t)0x4ea2, (q15_t)0x4e8e, (q15_t)0x4e7a, (q15_t)0x4e66, (q15_t)0x4e52, (q15_t)0x4e3e, (q15_t)0x4e2a,
+  (q15_t)0x4e17, (q15_t)0x4e03, (q15_t)0x4def, (q15_t)0x4ddb, (q15_t)0x4dc7, (q15_t)0x4db3, (q15_t)0x4d9f, (q15_t)0x4d8b,
+  (q15_t)0x4d77, (q15_t)0x4d63, (q15_t)0x4d4f, (q15_t)0x4d3b, (q15_t)0x4d27, (q15_t)0x4d13, (q15_t)0x4cff, (q15_t)0x4ceb,
+  (q15_t)0x4cd6, (q15_t)0x4cc2, (q15_t)0x4cae, (q15_t)0x4c9a, (q15_t)0x4c86, (q15_t)0x4c72, (q15_t)0x4c5e, (q15_t)0x4c49,
+  (q15_t)0x4c35, (q15_t)0x4c21, (q15_t)0x4c0d, (q15_t)0x4bf9, (q15_t)0x4be4, (q15_t)0x4bd0, (q15_t)0x4bbc, (q15_t)0x4ba8,
+  (q15_t)0x4b93, (q15_t)0x4b7f, (q15_t)0x4b6b, (q15_t)0x4b56, (q15_t)0x4b42, (q15_t)0x4b2e, (q15_t)0x4b19, (q15_t)0x4b05,
+  (q15_t)0x4af1, (q15_t)0x4adc, (q15_t)0x4ac8, (q15_t)0x4ab4, (q15_t)0x4a9f, (q15_t)0x4a8b, (q15_t)0x4a76, (q15_t)0x4a62,
+  (q15_t)0x4a4d, (q15_t)0x4a39, (q15_t)0x4a24, (q15_t)0x4a10, (q15_t)0x49fb, (q15_t)0x49e7, (q15_t)0x49d2, (q15_t)0x49be,
+  (q15_t)0x49a9, (q15_t)0x4995, (q15_t)0x4980, (q15_t)0x496c, (q15_t)0x4957, (q15_t)0x4942, (q15_t)0x492e, (q15_t)0x4919,
+  (q15_t)0x4905, (q15_t)0x48f0, (q15_t)0x48db, (q15_t)0x48c7, (q15_t)0x48b2, (q15_t)0x489d, (q15_t)0x4888, (q15_t)0x4874,
+  (q15_t)0x485f, (q15_t)0x484a, (q15_t)0x4836, (q15_t)0x4821, (q15_t)0x480c, (q15_t)0x47f7, (q15_t)0x47e2, (q15_t)0x47ce,
+  (q15_t)0x47b9, (q15_t)0x47a4, (q15_t)0x478f, (q15_t)0x477a, (q15_t)0x4765, (q15_t)0x4751, (q15_t)0x473c, (q15_t)0x4727,
+  (q15_t)0x4712, (q15_t)0x46fd, (q15_t)0x46e8, (q15_t)0x46d3, (q15_t)0x46be, (q15_t)0x46a9, (q15_t)0x4694, (q15_t)0x467f,
+  (q15_t)0x466a, (q15_t)0x4655, (q15_t)0x4640, (q15_t)0x462b, (q15_t)0x4616, (q15_t)0x4601, (q15_t)0x45ec, (q15_t)0x45d7,
+  (q15_t)0x45c2, (q15_t)0x45ad, (q15_t)0x4598, (q15_t)0x4583, (q15_t)0x456e, (q15_t)0x4559, (q15_t)0x4544, (q15_t)0x452e,
+  (q15_t)0x4519, (q15_t)0x4504, (q15_t)0x44ef, (q15_t)0x44da, (q15_t)0x44c5, (q15_t)0x44af, (q15_t)0x449a, (q15_t)0x4485,
+  (q15_t)0x4470, (q15_t)0x445a, (q15_t)0x4445, (q15_t)0x4430, (q15_t)0x441b, (q15_t)0x4405, (q15_t)0x43f0, (q15_t)0x43db,
+  (q15_t)0x43c5, (q15_t)0x43b0, (q15_t)0x439b, (q15_t)0x4385, (q15_t)0x4370, (q15_t)0x435b, (q15_t)0x4345, (q15_t)0x4330,
+  (q15_t)0x431b, (q15_t)0x4305, (q15_t)0x42f0, (q15_t)0x42da, (q15_t)0x42c5, (q15_t)0x42af, (q15_t)0x429a, (q15_t)0x4284,
+  (q15_t)0x426f, (q15_t)0x425a, (q15_t)0x4244, (q15_t)0x422f, (q15_t)0x4219, (q15_t)0x4203, (q15_t)0x41ee, (q15_t)0x41d8,
+  (q15_t)0x41c3, (q15_t)0x41ad, (q15_t)0x4198, (q15_t)0x4182, (q15_t)0x416d, (q15_t)0x4157, (q15_t)0x4141, (q15_t)0x412c,
+  (q15_t)0x4116, (q15_t)0x4100, (q15_t)0x40eb, (q15_t)0x40d5, (q15_t)0x40bf, (q15_t)0x40aa, (q15_t)0x4094, (q15_t)0x407e,
+  (q15_t)0x4069, (q15_t)0x4053, (q15_t)0x403d, (q15_t)0x4027, (q15_t)0x4012, (q15_t)0x3ffc, (q15_t)0x3fe6, (q15_t)0x3fd0,
+  (q15_t)0x3fbb, (q15_t)0x3fa5, (q15_t)0x3f8f, (q15_t)0x3f79, (q15_t)0x3f63, (q15_t)0x3f4d, (q15_t)0x3f38, (q15_t)0x3f22,
+  (q15_t)0x3f0c, (q15_t)0x3ef6, (q15_t)0x3ee0, (q15_t)0x3eca, (q15_t)0x3eb4, (q15_t)0x3e9e, (q15_t)0x3e88, (q15_t)0x3e73,
+  (q15_t)0x3e5d, (q15_t)0x3e47, (q15_t)0x3e31, (q15_t)0x3e1b, (q15_t)0x3e05, (q15_t)0x3def, (q15_t)0x3dd9, (q15_t)0x3dc3,
+  (q15_t)0x3dad, (q15_t)0x3d97, (q15_t)0x3d81, (q15_t)0x3d6b, (q15_t)0x3d55, (q15_t)0x3d3e, (q15_t)0x3d28, (q15_t)0x3d12,
+  (q15_t)0x3cfc, (q15_t)0x3ce6, (q15_t)0x3cd0, (q15_t)0x3cba, (q15_t)0x3ca4, (q15_t)0x3c8e, (q15_t)0x3c77, (q15_t)0x3c61,
+  (q15_t)0x3c4b, (q15_t)0x3c35, (q15_t)0x3c1f, (q15_t)0x3c09, (q15_t)0x3bf2, (q15_t)0x3bdc, (q15_t)0x3bc6, (q15_t)0x3bb0,
+  (q15_t)0x3b99, (q15_t)0x3b83, (q15_t)0x3b6d, (q15_t)0x3b57, (q15_t)0x3b40, (q15_t)0x3b2a, (q15_t)0x3b14, (q15_t)0x3afe,
+  (q15_t)0x3ae7, (q15_t)0x3ad1, (q15_t)0x3abb, (q15_t)0x3aa4, (q15_t)0x3a8e, (q15_t)0x3a78, (q15_t)0x3a61, (q15_t)0x3a4b,
+  (q15_t)0x3a34, (q15_t)0x3a1e, (q15_t)0x3a08, (q15_t)0x39f1, (q15_t)0x39db, (q15_t)0x39c4, (q15_t)0x39ae, (q15_t)0x3998,
+  (q15_t)0x3981, (q15_t)0x396b, (q15_t)0x3954, (q15_t)0x393e, (q15_t)0x3927, (q15_t)0x3911, (q15_t)0x38fa, (q15_t)0x38e4,
+  (q15_t)0x38cd, (q15_t)0x38b7, (q15_t)0x38a0, (q15_t)0x388a, (q15_t)0x3873, (q15_t)0x385d, (q15_t)0x3846, (q15_t)0x382f,
+  (q15_t)0x3819, (q15_t)0x3802, (q15_t)0x37ec, (q15_t)0x37d5, (q15_t)0x37be, (q15_t)0x37a8, (q15_t)0x3791, (q15_t)0x377a,
+  (q15_t)0x3764, (q15_t)0x374d, (q15_t)0x3736, (q15_t)0x3720, (q15_t)0x3709, (q15_t)0x36f2, (q15_t)0x36dc, (q15_t)0x36c5,
+  (q15_t)0x36ae, (q15_t)0x3698, (q15_t)0x3681, (q15_t)0x366a, (q15_t)0x3653, (q15_t)0x363d, (q15_t)0x3626, (q15_t)0x360f,
+  (q15_t)0x35f8, (q15_t)0x35e1, (q15_t)0x35cb, (q15_t)0x35b4, (q15_t)0x359d, (q15_t)0x3586, (q15_t)0x356f, (q15_t)0x3558,
+  (q15_t)0x3542, (q15_t)0x352b, (q15_t)0x3514, (q15_t)0x34fd, (q15_t)0x34e6, (q15_t)0x34cf, (q15_t)0x34b8, (q15_t)0x34a1,
+  (q15_t)0x348b, (q15_t)0x3474, (q15_t)0x345d, (q15_t)0x3446, (q15_t)0x342f, (q15_t)0x3418, (q15_t)0x3401, (q15_t)0x33ea,
+  (q15_t)0x33d3, (q15_t)0x33bc, (q15_t)0x33a5, (q15_t)0x338e, (q15_t)0x3377, (q15_t)0x3360, (q15_t)0x3349, (q15_t)0x3332,
+  (q15_t)0x331b, (q15_t)0x3304, (q15_t)0x32ed, (q15_t)0x32d6, (q15_t)0x32bf, (q15_t)0x32a8, (q15_t)0x3290, (q15_t)0x3279,
+  (q15_t)0x3262, (q15_t)0x324b, (q15_t)0x3234, (q15_t)0x321d, (q15_t)0x3206, (q15_t)0x31ef, (q15_t)0x31d8, (q15_t)0x31c0,
+  (q15_t)0x31a9, (q15_t)0x3192, (q15_t)0x317b, (q15_t)0x3164, (q15_t)0x314c, (q15_t)0x3135, (q15_t)0x311e, (q15_t)0x3107,
+  (q15_t)0x30f0, (q15_t)0x30d8, (q15_t)0x30c1, (q15_t)0x30aa, (q15_t)0x3093, (q15_t)0x307b, (q15_t)0x3064, (q15_t)0x304d,
+  (q15_t)0x3036, (q15_t)0x301e, (q15_t)0x3007, (q15_t)0x2ff0, (q15_t)0x2fd8, (q15_t)0x2fc1, (q15_t)0x2faa, (q15_t)0x2f92,
+  (q15_t)0x2f7b, (q15_t)0x2f64, (q15_t)0x2f4c, (q15_t)0x2f35, (q15_t)0x2f1e, (q15_t)0x2f06, (q15_t)0x2eef, (q15_t)0x2ed8,
+  (q15_t)0x2ec0, (q15_t)0x2ea9, (q15_t)0x2e91, (q15_t)0x2e7a, (q15_t)0x2e63, (q15_t)0x2e4b, (q15_t)0x2e34, (q15_t)0x2e1c,
+  (q15_t)0x2e05, (q15_t)0x2ded, (q15_t)0x2dd6, (q15_t)0x2dbe, (q15_t)0x2da7, (q15_t)0x2d8f, (q15_t)0x2d78, (q15_t)0x2d60,
+  (q15_t)0x2d49, (q15_t)0x2d31, (q15_t)0x2d1a, (q15_t)0x2d02, (q15_t)0x2ceb, (q15_t)0x2cd3, (q15_t)0x2cbc, (q15_t)0x2ca4,
+  (q15_t)0x2c8d, (q15_t)0x2c75, (q15_t)0x2c5e, (q15_t)0x2c46, (q15_t)0x2c2e, (q15_t)0x2c17, (q15_t)0x2bff, (q15_t)0x2be8,
+  (q15_t)0x2bd0, (q15_t)0x2bb8, (q15_t)0x2ba1, (q15_t)0x2b89, (q15_t)0x2b71, (q15_t)0x2b5a, (q15_t)0x2b42, (q15_t)0x2b2b,
+  (q15_t)0x2b13, (q15_t)0x2afb, (q15_t)0x2ae4, (q15_t)0x2acc, (q15_t)0x2ab4, (q15_t)0x2a9c, (q15_t)0x2a85, (q15_t)0x2a6d,
+  (q15_t)0x2a55, (q15_t)0x2a3e, (q15_t)0x2a26, (q15_t)0x2a0e, (q15_t)0x29f6, (q15_t)0x29df, (q15_t)0x29c7, (q15_t)0x29af,
+  (q15_t)0x2997, (q15_t)0x2980, (q15_t)0x2968, (q15_t)0x2950, (q15_t)0x2938, (q15_t)0x2920, (q15_t)0x2909, (q15_t)0x28f1,
+  (q15_t)0x28d9, (q15_t)0x28c1, (q15_t)0x28a9, (q15_t)0x2892, (q15_t)0x287a, (q15_t)0x2862, (q15_t)0x284a, (q15_t)0x2832,
+  (q15_t)0x281a, (q15_t)0x2802, (q15_t)0x27eb, (q15_t)0x27d3, (q15_t)0x27bb, (q15_t)0x27a3, (q15_t)0x278b, (q15_t)0x2773,
+  (q15_t)0x275b, (q15_t)0x2743, (q15_t)0x272b, (q15_t)0x2713, (q15_t)0x26fb, (q15_t)0x26e4, (q15_t)0x26cc, (q15_t)0x26b4,
+  (q15_t)0x269c, (q15_t)0x2684, (q15_t)0x266c, (q15_t)0x2654, (q15_t)0x263c, (q15_t)0x2624, (q15_t)0x260c, (q15_t)0x25f4,
+  (q15_t)0x25dc, (q15_t)0x25c4, (q15_t)0x25ac, (q15_t)0x2594, (q15_t)0x257c, (q15_t)0x2564, (q15_t)0x254c, (q15_t)0x2534,
+  (q15_t)0x251c, (q15_t)0x2503, (q15_t)0x24eb, (q15_t)0x24d3, (q15_t)0x24bb, (q15_t)0x24a3, (q15_t)0x248b, (q15_t)0x2473,
+  (q15_t)0x245b, (q15_t)0x2443, (q15_t)0x242b, (q15_t)0x2413, (q15_t)0x23fa, (q15_t)0x23e2, (q15_t)0x23ca, (q15_t)0x23b2,
+  (q15_t)0x239a, (q15_t)0x2382, (q15_t)0x236a, (q15_t)0x2352, (q15_t)0x2339, (q15_t)0x2321, (q15_t)0x2309, (q15_t)0x22f1,
+  (q15_t)0x22d9, (q15_t)0x22c0, (q15_t)0x22a8, (q15_t)0x2290, (q15_t)0x2278, (q15_t)0x2260, (q15_t)0x2247, (q15_t)0x222f,
+  (q15_t)0x2217, (q15_t)0x21ff, (q15_t)0x21e7, (q15_t)0x21ce, (q15_t)0x21b6, (q15_t)0x219e, (q15_t)0x2186, (q15_t)0x216d,
+  (q15_t)0x2155, (q15_t)0x213d, (q15_t)0x2125, (q15_t)0x210c, (q15_t)0x20f4, (q15_t)0x20dc, (q15_t)0x20c3, (q15_t)0x20ab,
+  (q15_t)0x2093, (q15_t)0x207a, (q15_t)0x2062, (q15_t)0x204a, (q15_t)0x2032, (q15_t)0x2019, (q15_t)0x2001, (q15_t)0x1fe9,
+  (q15_t)0x1fd0, (q15_t)0x1fb8, (q15_t)0x1f9f, (q15_t)0x1f87, (q15_t)0x1f6f, (q15_t)0x1f56, (q15_t)0x1f3e, (q15_t)0x1f26,
+  (q15_t)0x1f0d, (q15_t)0x1ef5, (q15_t)0x1edd, (q15_t)0x1ec4, (q15_t)0x1eac, (q15_t)0x1e93, (q15_t)0x1e7b, (q15_t)0x1e62,
+  (q15_t)0x1e4a, (q15_t)0x1e32, (q15_t)0x1e19, (q15_t)0x1e01, (q15_t)0x1de8, (q15_t)0x1dd0, (q15_t)0x1db7, (q15_t)0x1d9f,
+  (q15_t)0x1d87, (q15_t)0x1d6e, (q15_t)0x1d56, (q15_t)0x1d3d, (q15_t)0x1d25, (q15_t)0x1d0c, (q15_t)0x1cf4, (q15_t)0x1cdb,
+  (q15_t)0x1cc3, (q15_t)0x1caa, (q15_t)0x1c92, (q15_t)0x1c79, (q15_t)0x1c61, (q15_t)0x1c48, (q15_t)0x1c30, (q15_t)0x1c17,
+  (q15_t)0x1bff, (q15_t)0x1be6, (q15_t)0x1bce, (q15_t)0x1bb5, (q15_t)0x1b9d, (q15_t)0x1b84, (q15_t)0x1b6c, (q15_t)0x1b53,
+  (q15_t)0x1b3a, (q15_t)0x1b22, (q15_t)0x1b09, (q15_t)0x1af1, (q15_t)0x1ad8, (q15_t)0x1ac0, (q15_t)0x1aa7, (q15_t)0x1a8e,
+  (q15_t)0x1a76, (q15_t)0x1a5d, (q15_t)0x1a45, (q15_t)0x1a2c, (q15_t)0x1a13, (q15_t)0x19fb, (q15_t)0x19e2, (q15_t)0x19ca,
+  (q15_t)0x19b1, (q15_t)0x1998, (q15_t)0x1980, (q15_t)0x1967, (q15_t)0x194e, (q15_t)0x1936, (q15_t)0x191d, (q15_t)0x1905,
+  (q15_t)0x18ec, (q15_t)0x18d3, (q15_t)0x18bb, (q15_t)0x18a2, (q15_t)0x1889, (q15_t)0x1871, (q15_t)0x1858, (q15_t)0x183f,
+  (q15_t)0x1827, (q15_t)0x180e, (q15_t)0x17f5, (q15_t)0x17dd, (q15_t)0x17c4, (q15_t)0x17ab, (q15_t)0x1792, (q15_t)0x177a,
+  (q15_t)0x1761, (q15_t)0x1748, (q15_t)0x1730, (q15_t)0x1717, (q15_t)0x16fe, (q15_t)0x16e5, (q15_t)0x16cd, (q15_t)0x16b4,
+  (q15_t)0x169b, (q15_t)0x1682, (q15_t)0x166a, (q15_t)0x1651, (q15_t)0x1638, (q15_t)0x161f, (q15_t)0x1607, (q15_t)0x15ee,
+  (q15_t)0x15d5, (q15_t)0x15bc, (q15_t)0x15a4, (q15_t)0x158b, (q15_t)0x1572, (q15_t)0x1559, (q15_t)0x1541, (q15_t)0x1528,
+  (q15_t)0x150f, (q15_t)0x14f6, (q15_t)0x14dd, (q15_t)0x14c5, (q15_t)0x14ac, (q15_t)0x1493, (q15_t)0x147a, (q15_t)0x1461,
+  (q15_t)0x1449, (q15_t)0x1430, (q15_t)0x1417, (q15_t)0x13fe, (q15_t)0x13e5, (q15_t)0x13cc, (q15_t)0x13b4, (q15_t)0x139b,
+  (q15_t)0x1382, (q15_t)0x1369, (q15_t)0x1350, (q15_t)0x1337, (q15_t)0x131f, (q15_t)0x1306, (q15_t)0x12ed, (q15_t)0x12d4,
+  (q15_t)0x12bb, (q15_t)0x12a2, (q15_t)0x1289, (q15_t)0x1271, (q15_t)0x1258, (q15_t)0x123f, (q15_t)0x1226, (q15_t)0x120d,
+  (q15_t)0x11f4, (q15_t)0x11db, (q15_t)0x11c2, (q15_t)0x11a9, (q15_t)0x1191, (q15_t)0x1178, (q15_t)0x115f, (q15_t)0x1146,
+  (q15_t)0x112d, (q15_t)0x1114, (q15_t)0x10fb, (q15_t)0x10e2, (q15_t)0x10c9, (q15_t)0x10b0, (q15_t)0x1098, (q15_t)0x107f,
+  (q15_t)0x1066, (q15_t)0x104d, (q15_t)0x1034, (q15_t)0x101b, (q15_t)0x1002, (q15_t)0xfe9, (q15_t)0xfd0, (q15_t)0xfb7,
+  (q15_t)0xf9e, (q15_t)0xf85, (q15_t)0xf6c, (q15_t)0xf53, (q15_t)0xf3a, (q15_t)0xf21, (q15_t)0xf08, (q15_t)0xef0,
+  (q15_t)0xed7, (q15_t)0xebe, (q15_t)0xea5, (q15_t)0xe8c, (q15_t)0xe73, (q15_t)0xe5a, (q15_t)0xe41, (q15_t)0xe28,
+  (q15_t)0xe0f, (q15_t)0xdf6, (q15_t)0xddd, (q15_t)0xdc4, (q15_t)0xdab, (q15_t)0xd92, (q15_t)0xd79, (q15_t)0xd60,
+  (q15_t)0xd47, (q15_t)0xd2e, (q15_t)0xd15, (q15_t)0xcfc, (q15_t)0xce3, (q15_t)0xcca, (q15_t)0xcb1, (q15_t)0xc98,
+  (q15_t)0xc7f, (q15_t)0xc66, (q15_t)0xc4d, (q15_t)0xc34, (q15_t)0xc1b, (q15_t)0xc02, (q15_t)0xbe9, (q15_t)0xbd0,
+  (q15_t)0xbb7, (q15_t)0xb9e, (q15_t)0xb85, (q15_t)0xb6c, (q15_t)0xb53, (q15_t)0xb3a, (q15_t)0xb20, (q15_t)0xb07,
+  (q15_t)0xaee, (q15_t)0xad5, (q15_t)0xabc, (q15_t)0xaa3, (q15_t)0xa8a, (q15_t)0xa71, (q15_t)0xa58, (q15_t)0xa3f,
+  (q15_t)0xa26, (q15_t)0xa0d, (q15_t)0x9f4, (q15_t)0x9db, (q15_t)0x9c2, (q15_t)0x9a9, (q15_t)0x990, (q15_t)0x977,
+  (q15_t)0x95e, (q15_t)0x944, (q15_t)0x92b, (q15_t)0x912, (q15_t)0x8f9, (q15_t)0x8e0, (q15_t)0x8c7, (q15_t)0x8ae,
+  (q15_t)0x895, (q15_t)0x87c, (q15_t)0x863, (q15_t)0x84a, (q15_t)0x831, (q15_t)0x818, (q15_t)0x7fe, (q15_t)0x7e5,
+  (q15_t)0x7cc, (q15_t)0x7b3, (q15_t)0x79a, (q15_t)0x781, (q15_t)0x768, (q15_t)0x74f, (q15_t)0x736, (q15_t)0x71d,
+  (q15_t)0x704, (q15_t)0x6ea, (q15_t)0x6d1, (q15_t)0x6b8, (q15_t)0x69f, (q15_t)0x686, (q15_t)0x66d, (q15_t)0x654,
+  (q15_t)0x63b, (q15_t)0x622, (q15_t)0x609, (q15_t)0x5ef, (q15_t)0x5d6, (q15_t)0x5bd, (q15_t)0x5a4, (q15_t)0x58b,
+  (q15_t)0x572, (q15_t)0x559, (q15_t)0x540, (q15_t)0x527, (q15_t)0x50d, (q15_t)0x4f4, (q15_t)0x4db, (q15_t)0x4c2,
+  (q15_t)0x4a9, (q15_t)0x490, (q15_t)0x477, (q15_t)0x45e, (q15_t)0x445, (q15_t)0x42b, (q15_t)0x412, (q15_t)0x3f9,
+  (q15_t)0x3e0, (q15_t)0x3c7, (q15_t)0x3ae, (q15_t)0x395, (q15_t)0x37c, (q15_t)0x362, (q15_t)0x349, (q15_t)0x330,
+  (q15_t)0x317, (q15_t)0x2fe, (q15_t)0x2e5, (q15_t)0x2cc, (q15_t)0x2b3, (q15_t)0x299, (q15_t)0x280, (q15_t)0x267,
+  (q15_t)0x24e, (q15_t)0x235, (q15_t)0x21c, (q15_t)0x203, (q15_t)0x1ea, (q15_t)0x1d0, (q15_t)0x1b7, (q15_t)0x19e,
+  (q15_t)0x185, (q15_t)0x16c, (q15_t)0x153, (q15_t)0x13a, (q15_t)0x121, (q15_t)0x107, (q15_t)0xee, (q15_t)0xd5,
+  (q15_t)0xbc, (q15_t)0xa3, (q15_t)0x8a, (q15_t)0x71, (q15_t)0x57, (q15_t)0x3e, (q15_t)0x25, (q15_t)0xc
+
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_8192[8192] = {
+  (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
+  (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
+  (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
+  (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
+  (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
+  (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe,
+  (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe,
+  (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd,
+  (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc,
+  (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc,
+  (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb,
+  (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa,
+  (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9,
+  (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8,
+  (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7,
+  (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6,
+  (q15_t)0x7ff6, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4,
+  (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3,
+  (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2,
+  (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff0, (q15_t)0x7ff0,
+  (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef,
+  (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fed,
+  (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7feb,
+  (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fe9,
+  (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8,
+  (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6,
+  (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4,
+  (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe1,
+  (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdf,
+  (q15_t)0x7fdf, (q15_t)0x7fdf, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fdd, (q15_t)0x7fdd,
+  (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb,
+  (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd8, (q15_t)0x7fd8,
+  (q15_t)0x7fd8, (q15_t)0x7fd8, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd6, (q15_t)0x7fd6,
+  (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd3, (q15_t)0x7fd3,
+  (q15_t)0x7fd3, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd0,
+  (q15_t)0x7fd0, (q15_t)0x7fd0, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fce, (q15_t)0x7fce, (q15_t)0x7fce,
+  (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcb, (q15_t)0x7fcb,
+  (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc8, (q15_t)0x7fc8,
+  (q15_t)0x7fc8, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc6, (q15_t)0x7fc5, (q15_t)0x7fc5,
+  (q15_t)0x7fc5, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc3, (q15_t)0x7fc3, (q15_t)0x7fc2, (q15_t)0x7fc2,
+  (q15_t)0x7fc2, (q15_t)0x7fc1, (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fbf, (q15_t)0x7fbf,
+  (q15_t)0x7fbf, (q15_t)0x7fbe, (q15_t)0x7fbe, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbc, (q15_t)0x7fbc,
+  (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fba, (q15_t)0x7fba, (q15_t)0x7fb9, (q15_t)0x7fb9, (q15_t)0x7fb8,
+  (q15_t)0x7fb8, (q15_t)0x7fb8, (q15_t)0x7fb7, (q15_t)0x7fb7, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb5,
+  (q15_t)0x7fb5, (q15_t)0x7fb4, (q15_t)0x7fb4, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb2, (q15_t)0x7fb2,
+  (q15_t)0x7fb1, (q15_t)0x7fb1, (q15_t)0x7fb0, (q15_t)0x7fb0, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7fae,
+  (q15_t)0x7fae, (q15_t)0x7fad, (q15_t)0x7fad, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fab, (q15_t)0x7fab,
+  (q15_t)0x7faa, (q15_t)0x7faa, (q15_t)0x7fa9, (q15_t)0x7fa9, (q15_t)0x7fa8, (q15_t)0x7fa8, (q15_t)0x7fa7, (q15_t)0x7fa7,
+  (q15_t)0x7fa6, (q15_t)0x7fa6, (q15_t)0x7fa6, (q15_t)0x7fa5, (q15_t)0x7fa5, (q15_t)0x7fa4, (q15_t)0x7fa4, (q15_t)0x7fa3,
+  (q15_t)0x7fa3, (q15_t)0x7fa2, (q15_t)0x7fa2, (q15_t)0x7fa1, (q15_t)0x7fa1, (q15_t)0x7fa0, (q15_t)0x7fa0, (q15_t)0x7f9f,
+  (q15_t)0x7f9f, (q15_t)0x7f9e, (q15_t)0x7f9e, (q15_t)0x7f9d, (q15_t)0x7f9d, (q15_t)0x7f9c, (q15_t)0x7f9c, (q15_t)0x7f9c,
+  (q15_t)0x7f9b, (q15_t)0x7f9b, (q15_t)0x7f9a, (q15_t)0x7f9a, (q15_t)0x7f99, (q15_t)0x7f99, (q15_t)0x7f98, (q15_t)0x7f98,
+  (q15_t)0x7f97, (q15_t)0x7f97, (q15_t)0x7f96, (q15_t)0x7f96, (q15_t)0x7f95, (q15_t)0x7f95, (q15_t)0x7f94, (q15_t)0x7f94,
+  (q15_t)0x7f93, (q15_t)0x7f92, (q15_t)0x7f92, (q15_t)0x7f91, (q15_t)0x7f91, (q15_t)0x7f90, (q15_t)0x7f90, (q15_t)0x7f8f,
+  (q15_t)0x7f8f, (q15_t)0x7f8e, (q15_t)0x7f8e, (q15_t)0x7f8d, (q15_t)0x7f8d, (q15_t)0x7f8c, (q15_t)0x7f8c, (q15_t)0x7f8b,
+  (q15_t)0x7f8b, (q15_t)0x7f8a, (q15_t)0x7f8a, (q15_t)0x7f89, (q15_t)0x7f89, (q15_t)0x7f88, (q15_t)0x7f87, (q15_t)0x7f87,
+  (q15_t)0x7f86, (q15_t)0x7f86, (q15_t)0x7f85, (q15_t)0x7f85, (q15_t)0x7f84, (q15_t)0x7f84, (q15_t)0x7f83, (q15_t)0x7f83,
+  (q15_t)0x7f82, (q15_t)0x7f81, (q15_t)0x7f81, (q15_t)0x7f80, (q15_t)0x7f80, (q15_t)0x7f7f, (q15_t)0x7f7f, (q15_t)0x7f7e,
+  (q15_t)0x7f7e, (q15_t)0x7f7d, (q15_t)0x7f7c, (q15_t)0x7f7c, (q15_t)0x7f7b, (q15_t)0x7f7b, (q15_t)0x7f7a, (q15_t)0x7f7a,
+  (q15_t)0x7f79, (q15_t)0x7f79, (q15_t)0x7f78, (q15_t)0x7f77, (q15_t)0x7f77, (q15_t)0x7f76, (q15_t)0x7f76, (q15_t)0x7f75,
+  (q15_t)0x7f75, (q15_t)0x7f74, (q15_t)0x7f73, (q15_t)0x7f73, (q15_t)0x7f72, (q15_t)0x7f72, (q15_t)0x7f71, (q15_t)0x7f70,
+  (q15_t)0x7f70, (q15_t)0x7f6f, (q15_t)0x7f6f, (q15_t)0x7f6e, (q15_t)0x7f6d, (q15_t)0x7f6d, (q15_t)0x7f6c, (q15_t)0x7f6c,
+  (q15_t)0x7f6b, (q15_t)0x7f6b, (q15_t)0x7f6a, (q15_t)0x7f69, (q15_t)0x7f69, (q15_t)0x7f68, (q15_t)0x7f68, (q15_t)0x7f67,
+  (q15_t)0x7f66, (q15_t)0x7f66, (q15_t)0x7f65, (q15_t)0x7f64, (q15_t)0x7f64, (q15_t)0x7f63, (q15_t)0x7f63, (q15_t)0x7f62,
+  (q15_t)0x7f61, (q15_t)0x7f61, (q15_t)0x7f60, (q15_t)0x7f60, (q15_t)0x7f5f, (q15_t)0x7f5e, (q15_t)0x7f5e, (q15_t)0x7f5d,
+  (q15_t)0x7f5c, (q15_t)0x7f5c, (q15_t)0x7f5b, (q15_t)0x7f5b, (q15_t)0x7f5a, (q15_t)0x7f59, (q15_t)0x7f59, (q15_t)0x7f58,
+  (q15_t)0x7f57, (q15_t)0x7f57, (q15_t)0x7f56, (q15_t)0x7f55, (q15_t)0x7f55, (q15_t)0x7f54, (q15_t)0x7f54, (q15_t)0x7f53,
+  (q15_t)0x7f52, (q15_t)0x7f52, (q15_t)0x7f51, (q15_t)0x7f50, (q15_t)0x7f50, (q15_t)0x7f4f, (q15_t)0x7f4e, (q15_t)0x7f4e,
+  (q15_t)0x7f4d, (q15_t)0x7f4c, (q15_t)0x7f4c, (q15_t)0x7f4b, (q15_t)0x7f4a, (q15_t)0x7f4a, (q15_t)0x7f49, (q15_t)0x7f48,
+  (q15_t)0x7f48, (q15_t)0x7f47, (q15_t)0x7f46, (q15_t)0x7f46, (q15_t)0x7f45, (q15_t)0x7f44, (q15_t)0x7f44, (q15_t)0x7f43,
+  (q15_t)0x7f42, (q15_t)0x7f42, (q15_t)0x7f41, (q15_t)0x7f40, (q15_t)0x7f40, (q15_t)0x7f3f, (q15_t)0x7f3e, (q15_t)0x7f3e,
+  (q15_t)0x7f3d, (q15_t)0x7f3c, (q15_t)0x7f3c, (q15_t)0x7f3b, (q15_t)0x7f3a, (q15_t)0x7f3a, (q15_t)0x7f39, (q15_t)0x7f38,
+  (q15_t)0x7f37, (q15_t)0x7f37, (q15_t)0x7f36, (q15_t)0x7f35, (q15_t)0x7f35, (q15_t)0x7f34, (q15_t)0x7f33, (q15_t)0x7f33,
+  (q15_t)0x7f32, (q15_t)0x7f31, (q15_t)0x7f31, (q15_t)0x7f30, (q15_t)0x7f2f, (q15_t)0x7f2e, (q15_t)0x7f2e, (q15_t)0x7f2d,
+  (q15_t)0x7f2c, (q15_t)0x7f2c, (q15_t)0x7f2b, (q15_t)0x7f2a, (q15_t)0x7f29, (q15_t)0x7f29, (q15_t)0x7f28, (q15_t)0x7f27,
+  (q15_t)0x7f27, (q15_t)0x7f26, (q15_t)0x7f25, (q15_t)0x7f24, (q15_t)0x7f24, (q15_t)0x7f23, (q15_t)0x7f22, (q15_t)0x7f21,
+  (q15_t)0x7f21, (q15_t)0x7f20, (q15_t)0x7f1f, (q15_t)0x7f1f, (q15_t)0x7f1e, (q15_t)0x7f1d, (q15_t)0x7f1c, (q15_t)0x7f1c,
+  (q15_t)0x7f1b, (q15_t)0x7f1a, (q15_t)0x7f19, (q15_t)0x7f19, (q15_t)0x7f18, (q15_t)0x7f17, (q15_t)0x7f16, (q15_t)0x7f16,
+  (q15_t)0x7f15, (q15_t)0x7f14, (q15_t)0x7f13, (q15_t)0x7f13, (q15_t)0x7f12, (q15_t)0x7f11, (q15_t)0x7f10, (q15_t)0x7f10,
+  (q15_t)0x7f0f, (q15_t)0x7f0e, (q15_t)0x7f0d, (q15_t)0x7f0d, (q15_t)0x7f0c, (q15_t)0x7f0b, (q15_t)0x7f0a, (q15_t)0x7f09,
+  (q15_t)0x7f09, (q15_t)0x7f08, (q15_t)0x7f07, (q15_t)0x7f06, (q15_t)0x7f06, (q15_t)0x7f05, (q15_t)0x7f04, (q15_t)0x7f03,
+  (q15_t)0x7f02, (q15_t)0x7f02, (q15_t)0x7f01, (q15_t)0x7f00, (q15_t)0x7eff, (q15_t)0x7eff, (q15_t)0x7efe, (q15_t)0x7efd,
+  (q15_t)0x7efc, (q15_t)0x7efb, (q15_t)0x7efb, (q15_t)0x7efa, (q15_t)0x7ef9, (q15_t)0x7ef8, (q15_t)0x7ef7, (q15_t)0x7ef7,
+  (q15_t)0x7ef6, (q15_t)0x7ef5, (q15_t)0x7ef4, (q15_t)0x7ef3, (q15_t)0x7ef3, (q15_t)0x7ef2, (q15_t)0x7ef1, (q15_t)0x7ef0,
+  (q15_t)0x7eef, (q15_t)0x7eef, (q15_t)0x7eee, (q15_t)0x7eed, (q15_t)0x7eec, (q15_t)0x7eeb, (q15_t)0x7eeb, (q15_t)0x7eea,
+  (q15_t)0x7ee9, (q15_t)0x7ee8, (q15_t)0x7ee7, (q15_t)0x7ee6, (q15_t)0x7ee6, (q15_t)0x7ee5, (q15_t)0x7ee4, (q15_t)0x7ee3,
+  (q15_t)0x7ee2, (q15_t)0x7ee2, (q15_t)0x7ee1, (q15_t)0x7ee0, (q15_t)0x7edf, (q15_t)0x7ede, (q15_t)0x7edd, (q15_t)0x7edd,
+  (q15_t)0x7edc, (q15_t)0x7edb, (q15_t)0x7eda, (q15_t)0x7ed9, (q15_t)0x7ed8, (q15_t)0x7ed8, (q15_t)0x7ed7, (q15_t)0x7ed6,
+  (q15_t)0x7ed5, (q15_t)0x7ed4, (q15_t)0x7ed3, (q15_t)0x7ed2, (q15_t)0x7ed2, (q15_t)0x7ed1, (q15_t)0x7ed0, (q15_t)0x7ecf,
+  (q15_t)0x7ece, (q15_t)0x7ecd, (q15_t)0x7ecc, (q15_t)0x7ecc, (q15_t)0x7ecb, (q15_t)0x7eca, (q15_t)0x7ec9, (q15_t)0x7ec8,
+  (q15_t)0x7ec7, (q15_t)0x7ec6, (q15_t)0x7ec6, (q15_t)0x7ec5, (q15_t)0x7ec4, (q15_t)0x7ec3, (q15_t)0x7ec2, (q15_t)0x7ec1,
+  (q15_t)0x7ec0, (q15_t)0x7ebf, (q15_t)0x7ebf, (q15_t)0x7ebe, (q15_t)0x7ebd, (q15_t)0x7ebc, (q15_t)0x7ebb, (q15_t)0x7eba,
+  (q15_t)0x7eb9, (q15_t)0x7eb8, (q15_t)0x7eb8, (q15_t)0x7eb7, (q15_t)0x7eb6, (q15_t)0x7eb5, (q15_t)0x7eb4, (q15_t)0x7eb3,
+  (q15_t)0x7eb2, (q15_t)0x7eb1, (q15_t)0x7eb0, (q15_t)0x7eaf, (q15_t)0x7eaf, (q15_t)0x7eae, (q15_t)0x7ead, (q15_t)0x7eac,
+  (q15_t)0x7eab, (q15_t)0x7eaa, (q15_t)0x7ea9, (q15_t)0x7ea8, (q15_t)0x7ea7, (q15_t)0x7ea6, (q15_t)0x7ea6, (q15_t)0x7ea5,
+  (q15_t)0x7ea4, (q15_t)0x7ea3, (q15_t)0x7ea2, (q15_t)0x7ea1, (q15_t)0x7ea0, (q15_t)0x7e9f, (q15_t)0x7e9e, (q15_t)0x7e9d,
+  (q15_t)0x7e9c, (q15_t)0x7e9b, (q15_t)0x7e9b, (q15_t)0x7e9a, (q15_t)0x7e99, (q15_t)0x7e98, (q15_t)0x7e97, (q15_t)0x7e96,
+  (q15_t)0x7e95, (q15_t)0x7e94, (q15_t)0x7e93, (q15_t)0x7e92, (q15_t)0x7e91, (q15_t)0x7e90, (q15_t)0x7e8f, (q15_t)0x7e8e,
+  (q15_t)0x7e8d, (q15_t)0x7e8d, (q15_t)0x7e8c, (q15_t)0x7e8b, (q15_t)0x7e8a, (q15_t)0x7e89, (q15_t)0x7e88, (q15_t)0x7e87,
+  (q15_t)0x7e86, (q15_t)0x7e85, (q15_t)0x7e84, (q15_t)0x7e83, (q15_t)0x7e82, (q15_t)0x7e81, (q15_t)0x7e80, (q15_t)0x7e7f,
+  (q15_t)0x7e7e, (q15_t)0x7e7d, (q15_t)0x7e7c, (q15_t)0x7e7b, (q15_t)0x7e7a, (q15_t)0x7e79, (q15_t)0x7e78, (q15_t)0x7e77,
+  (q15_t)0x7e77, (q15_t)0x7e76, (q15_t)0x7e75, (q15_t)0x7e74, (q15_t)0x7e73, (q15_t)0x7e72, (q15_t)0x7e71, (q15_t)0x7e70,
+  (q15_t)0x7e6f, (q15_t)0x7e6e, (q15_t)0x7e6d, (q15_t)0x7e6c, (q15_t)0x7e6b, (q15_t)0x7e6a, (q15_t)0x7e69, (q15_t)0x7e68,
+  (q15_t)0x7e67, (q15_t)0x7e66, (q15_t)0x7e65, (q15_t)0x7e64, (q15_t)0x7e63, (q15_t)0x7e62, (q15_t)0x7e61, (q15_t)0x7e60,
+  (q15_t)0x7e5f, (q15_t)0x7e5e, (q15_t)0x7e5d, (q15_t)0x7e5c, (q15_t)0x7e5b, (q15_t)0x7e5a, (q15_t)0x7e59, (q15_t)0x7e58,
+  (q15_t)0x7e57, (q15_t)0x7e56, (q15_t)0x7e55, (q15_t)0x7e54, (q15_t)0x7e53, (q15_t)0x7e52, (q15_t)0x7e51, (q15_t)0x7e50,
+  (q15_t)0x7e4f, (q15_t)0x7e4e, (q15_t)0x7e4d, (q15_t)0x7e4c, (q15_t)0x7e4b, (q15_t)0x7e4a, (q15_t)0x7e49, (q15_t)0x7e48,
+  (q15_t)0x7e47, (q15_t)0x7e46, (q15_t)0x7e45, (q15_t)0x7e43, (q15_t)0x7e42, (q15_t)0x7e41, (q15_t)0x7e40, (q15_t)0x7e3f,
+  (q15_t)0x7e3e, (q15_t)0x7e3d, (q15_t)0x7e3c, (q15_t)0x7e3b, (q15_t)0x7e3a, (q15_t)0x7e39, (q15_t)0x7e38, (q15_t)0x7e37,
+  (q15_t)0x7e36, (q15_t)0x7e35, (q15_t)0x7e34, (q15_t)0x7e33, (q15_t)0x7e32, (q15_t)0x7e31, (q15_t)0x7e30, (q15_t)0x7e2f,
+  (q15_t)0x7e2e, (q15_t)0x7e2d, (q15_t)0x7e2b, (q15_t)0x7e2a, (q15_t)0x7e29, (q15_t)0x7e28, (q15_t)0x7e27, (q15_t)0x7e26,
+  (q15_t)0x7e25, (q15_t)0x7e24, (q15_t)0x7e23, (q15_t)0x7e22, (q15_t)0x7e21, (q15_t)0x7e20, (q15_t)0x7e1f, (q15_t)0x7e1e,
+  (q15_t)0x7e1d, (q15_t)0x7e1b, (q15_t)0x7e1a, (q15_t)0x7e19, (q15_t)0x7e18, (q15_t)0x7e17, (q15_t)0x7e16, (q15_t)0x7e15,
+  (q15_t)0x7e14, (q15_t)0x7e13, (q15_t)0x7e12, (q15_t)0x7e11, (q15_t)0x7e10, (q15_t)0x7e0e, (q15_t)0x7e0d, (q15_t)0x7e0c,
+  (q15_t)0x7e0b, (q15_t)0x7e0a, (q15_t)0x7e09, (q15_t)0x7e08, (q15_t)0x7e07, (q15_t)0x7e06, (q15_t)0x7e05, (q15_t)0x7e04,
+  (q15_t)0x7e02, (q15_t)0x7e01, (q15_t)0x7e00, (q15_t)0x7dff, (q15_t)0x7dfe, (q15_t)0x7dfd, (q15_t)0x7dfc, (q15_t)0x7dfb,
+  (q15_t)0x7dfa, (q15_t)0x7df8, (q15_t)0x7df7, (q15_t)0x7df6, (q15_t)0x7df5, (q15_t)0x7df4, (q15_t)0x7df3, (q15_t)0x7df2,
+  (q15_t)0x7df1, (q15_t)0x7def, (q15_t)0x7dee, (q15_t)0x7ded, (q15_t)0x7dec, (q15_t)0x7deb, (q15_t)0x7dea, (q15_t)0x7de9,
+  (q15_t)0x7de8, (q15_t)0x7de6, (q15_t)0x7de5, (q15_t)0x7de4, (q15_t)0x7de3, (q15_t)0x7de2, (q15_t)0x7de1, (q15_t)0x7de0,
+  (q15_t)0x7dde, (q15_t)0x7ddd, (q15_t)0x7ddc, (q15_t)0x7ddb, (q15_t)0x7dda, (q15_t)0x7dd9, (q15_t)0x7dd8, (q15_t)0x7dd6,
+  (q15_t)0x7dd5, (q15_t)0x7dd4, (q15_t)0x7dd3, (q15_t)0x7dd2, (q15_t)0x7dd1, (q15_t)0x7dd0, (q15_t)0x7dce, (q15_t)0x7dcd,
+  (q15_t)0x7dcc, (q15_t)0x7dcb, (q15_t)0x7dca, (q15_t)0x7dc9, (q15_t)0x7dc7, (q15_t)0x7dc6, (q15_t)0x7dc5, (q15_t)0x7dc4,
+  (q15_t)0x7dc3, (q15_t)0x7dc2, (q15_t)0x7dc0, (q15_t)0x7dbf, (q15_t)0x7dbe, (q15_t)0x7dbd, (q15_t)0x7dbc, (q15_t)0x7dbb,
+  (q15_t)0x7db9, (q15_t)0x7db8, (q15_t)0x7db7, (q15_t)0x7db6, (q15_t)0x7db5, (q15_t)0x7db3, (q15_t)0x7db2, (q15_t)0x7db1,
+  (q15_t)0x7db0, (q15_t)0x7daf, (q15_t)0x7dae, (q15_t)0x7dac, (q15_t)0x7dab, (q15_t)0x7daa, (q15_t)0x7da9, (q15_t)0x7da8,
+  (q15_t)0x7da6, (q15_t)0x7da5, (q15_t)0x7da4, (q15_t)0x7da3, (q15_t)0x7da2, (q15_t)0x7da0, (q15_t)0x7d9f, (q15_t)0x7d9e,
+  (q15_t)0x7d9d, (q15_t)0x7d9c, (q15_t)0x7d9a, (q15_t)0x7d99, (q15_t)0x7d98, (q15_t)0x7d97, (q15_t)0x7d95, (q15_t)0x7d94,
+  (q15_t)0x7d93, (q15_t)0x7d92, (q15_t)0x7d91, (q15_t)0x7d8f, (q15_t)0x7d8e, (q15_t)0x7d8d, (q15_t)0x7d8c, (q15_t)0x7d8a,
+  (q15_t)0x7d89, (q15_t)0x7d88, (q15_t)0x7d87, (q15_t)0x7d86, (q15_t)0x7d84, (q15_t)0x7d83, (q15_t)0x7d82, (q15_t)0x7d81,
+  (q15_t)0x7d7f, (q15_t)0x7d7e, (q15_t)0x7d7d, (q15_t)0x7d7c, (q15_t)0x7d7a, (q15_t)0x7d79, (q15_t)0x7d78, (q15_t)0x7d77,
+  (q15_t)0x7d75, (q15_t)0x7d74, (q15_t)0x7d73, (q15_t)0x7d72, (q15_t)0x7d70, (q15_t)0x7d6f, (q15_t)0x7d6e, (q15_t)0x7d6d,
+  (q15_t)0x7d6b, (q15_t)0x7d6a, (q15_t)0x7d69, (q15_t)0x7d68, (q15_t)0x7d66, (q15_t)0x7d65, (q15_t)0x7d64, (q15_t)0x7d63,
+  (q15_t)0x7d61, (q15_t)0x7d60, (q15_t)0x7d5f, (q15_t)0x7d5e, (q15_t)0x7d5c, (q15_t)0x7d5b, (q15_t)0x7d5a, (q15_t)0x7d59,
+  (q15_t)0x7d57, (q15_t)0x7d56, (q15_t)0x7d55, (q15_t)0x7d53, (q15_t)0x7d52, (q15_t)0x7d51, (q15_t)0x7d50, (q15_t)0x7d4e,
+  (q15_t)0x7d4d, (q15_t)0x7d4c, (q15_t)0x7d4a, (q15_t)0x7d49, (q15_t)0x7d48, (q15_t)0x7d47, (q15_t)0x7d45, (q15_t)0x7d44,
+  (q15_t)0x7d43, (q15_t)0x7d41, (q15_t)0x7d40, (q15_t)0x7d3f, (q15_t)0x7d3e, (q15_t)0x7d3c, (q15_t)0x7d3b, (q15_t)0x7d3a,
+  (q15_t)0x7d38, (q15_t)0x7d37, (q15_t)0x7d36, (q15_t)0x7d34, (q15_t)0x7d33, (q15_t)0x7d32, (q15_t)0x7d31, (q15_t)0x7d2f,
+  (q15_t)0x7d2e, (q15_t)0x7d2d, (q15_t)0x7d2b, (q15_t)0x7d2a, (q15_t)0x7d29, (q15_t)0x7d27, (q15_t)0x7d26, (q15_t)0x7d25,
+  (q15_t)0x7d23, (q15_t)0x7d22, (q15_t)0x7d21, (q15_t)0x7d1f, (q15_t)0x7d1e, (q15_t)0x7d1d, (q15_t)0x7d1b, (q15_t)0x7d1a,
+  (q15_t)0x7d19, (q15_t)0x7d17, (q15_t)0x7d16, (q15_t)0x7d15, (q15_t)0x7d13, (q15_t)0x7d12, (q15_t)0x7d11, (q15_t)0x7d0f,
+  (q15_t)0x7d0e, (q15_t)0x7d0d, (q15_t)0x7d0b, (q15_t)0x7d0a, (q15_t)0x7d09, (q15_t)0x7d07, (q15_t)0x7d06, (q15_t)0x7d05,
+  (q15_t)0x7d03, (q15_t)0x7d02, (q15_t)0x7d01, (q15_t)0x7cff, (q15_t)0x7cfe, (q15_t)0x7cfd, (q15_t)0x7cfb, (q15_t)0x7cfa,
+  (q15_t)0x7cf9, (q15_t)0x7cf7, (q15_t)0x7cf6, (q15_t)0x7cf4, (q15_t)0x7cf3, (q15_t)0x7cf2, (q15_t)0x7cf0, (q15_t)0x7cef,
+  (q15_t)0x7cee, (q15_t)0x7cec, (q15_t)0x7ceb, (q15_t)0x7ce9, (q15_t)0x7ce8, (q15_t)0x7ce7, (q15_t)0x7ce5, (q15_t)0x7ce4,
+  (q15_t)0x7ce3, (q15_t)0x7ce1, (q15_t)0x7ce0, (q15_t)0x7cde, (q15_t)0x7cdd, (q15_t)0x7cdc, (q15_t)0x7cda, (q15_t)0x7cd9,
+  (q15_t)0x7cd8, (q15_t)0x7cd6, (q15_t)0x7cd5, (q15_t)0x7cd3, (q15_t)0x7cd2, (q15_t)0x7cd1, (q15_t)0x7ccf, (q15_t)0x7cce,
+  (q15_t)0x7ccc, (q15_t)0x7ccb, (q15_t)0x7cca, (q15_t)0x7cc8, (q15_t)0x7cc7, (q15_t)0x7cc5, (q15_t)0x7cc4, (q15_t)0x7cc3,
+  (q15_t)0x7cc1, (q15_t)0x7cc0, (q15_t)0x7cbe, (q15_t)0x7cbd, (q15_t)0x7cbc, (q15_t)0x7cba, (q15_t)0x7cb9, (q15_t)0x7cb7,
+  (q15_t)0x7cb6, (q15_t)0x7cb5, (q15_t)0x7cb3, (q15_t)0x7cb2, (q15_t)0x7cb0, (q15_t)0x7caf, (q15_t)0x7cad, (q15_t)0x7cac,
+  (q15_t)0x7cab, (q15_t)0x7ca9, (q15_t)0x7ca8, (q15_t)0x7ca6, (q15_t)0x7ca5, (q15_t)0x7ca3, (q15_t)0x7ca2, (q15_t)0x7ca1,
+  (q15_t)0x7c9f, (q15_t)0x7c9e, (q15_t)0x7c9c, (q15_t)0x7c9b, (q15_t)0x7c99, (q15_t)0x7c98, (q15_t)0x7c97, (q15_t)0x7c95,
+  (q15_t)0x7c94, (q15_t)0x7c92, (q15_t)0x7c91, (q15_t)0x7c8f, (q15_t)0x7c8e, (q15_t)0x7c8c, (q15_t)0x7c8b, (q15_t)0x7c8a,
+  (q15_t)0x7c88, (q15_t)0x7c87, (q15_t)0x7c85, (q15_t)0x7c84, (q15_t)0x7c82, (q15_t)0x7c81, (q15_t)0x7c7f, (q15_t)0x7c7e,
+  (q15_t)0x7c7c, (q15_t)0x7c7b, (q15_t)0x7c79, (q15_t)0x7c78, (q15_t)0x7c77, (q15_t)0x7c75, (q15_t)0x7c74, (q15_t)0x7c72,
+  (q15_t)0x7c71, (q15_t)0x7c6f, (q15_t)0x7c6e, (q15_t)0x7c6c, (q15_t)0x7c6b, (q15_t)0x7c69, (q15_t)0x7c68, (q15_t)0x7c66,
+  (q15_t)0x7c65, (q15_t)0x7c63, (q15_t)0x7c62, (q15_t)0x7c60, (q15_t)0x7c5f, (q15_t)0x7c5d, (q15_t)0x7c5c, (q15_t)0x7c5a,
+  (q15_t)0x7c59, (q15_t)0x7c58, (q15_t)0x7c56, (q15_t)0x7c55, (q15_t)0x7c53, (q15_t)0x7c52, (q15_t)0x7c50, (q15_t)0x7c4f,
+  (q15_t)0x7c4d, (q15_t)0x7c4c, (q15_t)0x7c4a, (q15_t)0x7c49, (q15_t)0x7c47, (q15_t)0x7c46, (q15_t)0x7c44, (q15_t)0x7c43,
+  (q15_t)0x7c41, (q15_t)0x7c3f, (q15_t)0x7c3e, (q15_t)0x7c3c, (q15_t)0x7c3b, (q15_t)0x7c39, (q15_t)0x7c38, (q15_t)0x7c36,
+  (q15_t)0x7c35, (q15_t)0x7c33, (q15_t)0x7c32, (q15_t)0x7c30, (q15_t)0x7c2f, (q15_t)0x7c2d, (q15_t)0x7c2c, (q15_t)0x7c2a,
+  (q15_t)0x7c29, (q15_t)0x7c27, (q15_t)0x7c26, (q15_t)0x7c24, (q15_t)0x7c23, (q15_t)0x7c21, (q15_t)0x7c20, (q15_t)0x7c1e,
+  (q15_t)0x7c1c, (q15_t)0x7c1b, (q15_t)0x7c19, (q15_t)0x7c18, (q15_t)0x7c16, (q15_t)0x7c15, (q15_t)0x7c13, (q15_t)0x7c12,
+  (q15_t)0x7c10, (q15_t)0x7c0f, (q15_t)0x7c0d, (q15_t)0x7c0b, (q15_t)0x7c0a, (q15_t)0x7c08, (q15_t)0x7c07, (q15_t)0x7c05,
+  (q15_t)0x7c04, (q15_t)0x7c02, (q15_t)0x7c01, (q15_t)0x7bff, (q15_t)0x7bfd, (q15_t)0x7bfc, (q15_t)0x7bfa, (q15_t)0x7bf9,
+  (q15_t)0x7bf7, (q15_t)0x7bf6, (q15_t)0x7bf4, (q15_t)0x7bf3, (q15_t)0x7bf1, (q15_t)0x7bef, (q15_t)0x7bee, (q15_t)0x7bec,
+  (q15_t)0x7beb, (q15_t)0x7be9, (q15_t)0x7be8, (q15_t)0x7be6, (q15_t)0x7be4, (q15_t)0x7be3, (q15_t)0x7be1, (q15_t)0x7be0,
+  (q15_t)0x7bde, (q15_t)0x7bdc, (q15_t)0x7bdb, (q15_t)0x7bd9, (q15_t)0x7bd8, (q15_t)0x7bd6, (q15_t)0x7bd5, (q15_t)0x7bd3,
+  (q15_t)0x7bd1, (q15_t)0x7bd0, (q15_t)0x7bce, (q15_t)0x7bcd, (q15_t)0x7bcb, (q15_t)0x7bc9, (q15_t)0x7bc8, (q15_t)0x7bc6,
+  (q15_t)0x7bc5, (q15_t)0x7bc3, (q15_t)0x7bc1, (q15_t)0x7bc0, (q15_t)0x7bbe, (q15_t)0x7bbd, (q15_t)0x7bbb, (q15_t)0x7bb9,
+  (q15_t)0x7bb8, (q15_t)0x7bb6, (q15_t)0x7bb5, (q15_t)0x7bb3, (q15_t)0x7bb1, (q15_t)0x7bb0, (q15_t)0x7bae, (q15_t)0x7bac,
+  (q15_t)0x7bab, (q15_t)0x7ba9, (q15_t)0x7ba8, (q15_t)0x7ba6, (q15_t)0x7ba4, (q15_t)0x7ba3, (q15_t)0x7ba1, (q15_t)0x7b9f,
+  (q15_t)0x7b9e, (q15_t)0x7b9c, (q15_t)0x7b9b, (q15_t)0x7b99, (q15_t)0x7b97, (q15_t)0x7b96, (q15_t)0x7b94, (q15_t)0x7b92,
+  (q15_t)0x7b91, (q15_t)0x7b8f, (q15_t)0x7b8d, (q15_t)0x7b8c, (q15_t)0x7b8a, (q15_t)0x7b89, (q15_t)0x7b87, (q15_t)0x7b85,
+  (q15_t)0x7b84, (q15_t)0x7b82, (q15_t)0x7b80, (q15_t)0x7b7f, (q15_t)0x7b7d, (q15_t)0x7b7b, (q15_t)0x7b7a, (q15_t)0x7b78,
+  (q15_t)0x7b76, (q15_t)0x7b75, (q15_t)0x7b73, (q15_t)0x7b71, (q15_t)0x7b70, (q15_t)0x7b6e, (q15_t)0x7b6c, (q15_t)0x7b6b,
+  (q15_t)0x7b69, (q15_t)0x7b67, (q15_t)0x7b66, (q15_t)0x7b64, (q15_t)0x7b62, (q15_t)0x7b61, (q15_t)0x7b5f, (q15_t)0x7b5d,
+  (q15_t)0x7b5c, (q15_t)0x7b5a, (q15_t)0x7b58, (q15_t)0x7b57, (q15_t)0x7b55, (q15_t)0x7b53, (q15_t)0x7b52, (q15_t)0x7b50,
+  (q15_t)0x7b4e, (q15_t)0x7b4d, (q15_t)0x7b4b, (q15_t)0x7b49, (q15_t)0x7b47, (q15_t)0x7b46, (q15_t)0x7b44, (q15_t)0x7b42,
+  (q15_t)0x7b41, (q15_t)0x7b3f, (q15_t)0x7b3d, (q15_t)0x7b3c, (q15_t)0x7b3a, (q15_t)0x7b38, (q15_t)0x7b37, (q15_t)0x7b35,
+  (q15_t)0x7b33, (q15_t)0x7b31, (q15_t)0x7b30, (q15_t)0x7b2e, (q15_t)0x7b2c, (q15_t)0x7b2b, (q15_t)0x7b29, (q15_t)0x7b27,
+  (q15_t)0x7b25, (q15_t)0x7b24, (q15_t)0x7b22, (q15_t)0x7b20, (q15_t)0x7b1f, (q15_t)0x7b1d, (q15_t)0x7b1b, (q15_t)0x7b19,
+  (q15_t)0x7b18, (q15_t)0x7b16, (q15_t)0x7b14, (q15_t)0x7b13, (q15_t)0x7b11, (q15_t)0x7b0f, (q15_t)0x7b0d, (q15_t)0x7b0c,
+  (q15_t)0x7b0a, (q15_t)0x7b08, (q15_t)0x7b06, (q15_t)0x7b05, (q15_t)0x7b03, (q15_t)0x7b01, (q15_t)0x7aff, (q15_t)0x7afe,
+  (q15_t)0x7afc, (q15_t)0x7afa, (q15_t)0x7af8, (q15_t)0x7af7, (q15_t)0x7af5, (q15_t)0x7af3, (q15_t)0x7af2, (q15_t)0x7af0,
+  (q15_t)0x7aee, (q15_t)0x7aec, (q15_t)0x7aeb, (q15_t)0x7ae9, (q15_t)0x7ae7, (q15_t)0x7ae5, (q15_t)0x7ae3, (q15_t)0x7ae2,
+  (q15_t)0x7ae0, (q15_t)0x7ade, (q15_t)0x7adc, (q15_t)0x7adb, (q15_t)0x7ad9, (q15_t)0x7ad7, (q15_t)0x7ad5, (q15_t)0x7ad4,
+  (q15_t)0x7ad2, (q15_t)0x7ad0, (q15_t)0x7ace, (q15_t)0x7acd, (q15_t)0x7acb, (q15_t)0x7ac9, (q15_t)0x7ac7, (q15_t)0x7ac5,
+  (q15_t)0x7ac4, (q15_t)0x7ac2, (q15_t)0x7ac0, (q15_t)0x7abe, (q15_t)0x7abd, (q15_t)0x7abb, (q15_t)0x7ab9, (q15_t)0x7ab7,
+  (q15_t)0x7ab5, (q15_t)0x7ab4, (q15_t)0x7ab2, (q15_t)0x7ab0, (q15_t)0x7aae, (q15_t)0x7aac, (q15_t)0x7aab, (q15_t)0x7aa9,
+  (q15_t)0x7aa7, (q15_t)0x7aa5, (q15_t)0x7aa3, (q15_t)0x7aa2, (q15_t)0x7aa0, (q15_t)0x7a9e, (q15_t)0x7a9c, (q15_t)0x7a9a,
+  (q15_t)0x7a99, (q15_t)0x7a97, (q15_t)0x7a95, (q15_t)0x7a93, (q15_t)0x7a91, (q15_t)0x7a90, (q15_t)0x7a8e, (q15_t)0x7a8c,
+  (q15_t)0x7a8a, (q15_t)0x7a88, (q15_t)0x7a87, (q15_t)0x7a85, (q15_t)0x7a83, (q15_t)0x7a81, (q15_t)0x7a7f, (q15_t)0x7a7d,
+  (q15_t)0x7a7c, (q15_t)0x7a7a, (q15_t)0x7a78, (q15_t)0x7a76, (q15_t)0x7a74, (q15_t)0x7a72, (q15_t)0x7a71, (q15_t)0x7a6f,
+  (q15_t)0x7a6d, (q15_t)0x7a6b, (q15_t)0x7a69, (q15_t)0x7a67, (q15_t)0x7a66, (q15_t)0x7a64, (q15_t)0x7a62, (q15_t)0x7a60,
+  (q15_t)0x7a5e, (q15_t)0x7a5c, (q15_t)0x7a5b, (q15_t)0x7a59, (q15_t)0x7a57, (q15_t)0x7a55, (q15_t)0x7a53, (q15_t)0x7a51,
+  (q15_t)0x7a4f, (q15_t)0x7a4e, (q15_t)0x7a4c, (q15_t)0x7a4a, (q15_t)0x7a48, (q15_t)0x7a46, (q15_t)0x7a44, (q15_t)0x7a42,
+  (q15_t)0x7a41, (q15_t)0x7a3f, (q15_t)0x7a3d, (q15_t)0x7a3b, (q15_t)0x7a39, (q15_t)0x7a37, (q15_t)0x7a35, (q15_t)0x7a34,
+  (q15_t)0x7a32, (q15_t)0x7a30, (q15_t)0x7a2e, (q15_t)0x7a2c, (q15_t)0x7a2a, (q15_t)0x7a28, (q15_t)0x7a26, (q15_t)0x7a25,
+  (q15_t)0x7a23, (q15_t)0x7a21, (q15_t)0x7a1f, (q15_t)0x7a1d, (q15_t)0x7a1b, (q15_t)0x7a19, (q15_t)0x7a17, (q15_t)0x7a16,
+  (q15_t)0x7a14, (q15_t)0x7a12, (q15_t)0x7a10, (q15_t)0x7a0e, (q15_t)0x7a0c, (q15_t)0x7a0a, (q15_t)0x7a08, (q15_t)0x7a06,
+  (q15_t)0x7a04, (q15_t)0x7a03, (q15_t)0x7a01, (q15_t)0x79ff, (q15_t)0x79fd, (q15_t)0x79fb, (q15_t)0x79f9, (q15_t)0x79f7,
+  (q15_t)0x79f5, (q15_t)0x79f3, (q15_t)0x79f1, (q15_t)0x79f0, (q15_t)0x79ee, (q15_t)0x79ec, (q15_t)0x79ea, (q15_t)0x79e8,
+  (q15_t)0x79e6, (q15_t)0x79e4, (q15_t)0x79e2, (q15_t)0x79e0, (q15_t)0x79de, (q15_t)0x79dc, (q15_t)0x79da, (q15_t)0x79d9,
+  (q15_t)0x79d7, (q15_t)0x79d5, (q15_t)0x79d3, (q15_t)0x79d1, (q15_t)0x79cf, (q15_t)0x79cd, (q15_t)0x79cb, (q15_t)0x79c9,
+  (q15_t)0x79c7, (q15_t)0x79c5, (q15_t)0x79c3, (q15_t)0x79c1, (q15_t)0x79bf, (q15_t)0x79bd, (q15_t)0x79bc, (q15_t)0x79ba,
+  (q15_t)0x79b8, (q15_t)0x79b6, (q15_t)0x79b4, (q15_t)0x79b2, (q15_t)0x79b0, (q15_t)0x79ae, (q15_t)0x79ac, (q15_t)0x79aa,
+  (q15_t)0x79a8, (q15_t)0x79a6, (q15_t)0x79a4, (q15_t)0x79a2, (q15_t)0x79a0, (q15_t)0x799e, (q15_t)0x799c, (q15_t)0x799a,
+  (q15_t)0x7998, (q15_t)0x7996, (q15_t)0x7994, (q15_t)0x7992, (q15_t)0x7991, (q15_t)0x798f, (q15_t)0x798d, (q15_t)0x798b,
+  (q15_t)0x7989, (q15_t)0x7987, (q15_t)0x7985, (q15_t)0x7983, (q15_t)0x7981, (q15_t)0x797f, (q15_t)0x797d, (q15_t)0x797b,
+  (q15_t)0x7979, (q15_t)0x7977, (q15_t)0x7975, (q15_t)0x7973, (q15_t)0x7971, (q15_t)0x796f, (q15_t)0x796d, (q15_t)0x796b,
+  (q15_t)0x7969, (q15_t)0x7967, (q15_t)0x7965, (q15_t)0x7963, (q15_t)0x7961, (q15_t)0x795f, (q15_t)0x795d, (q15_t)0x795b,
+  (q15_t)0x7959, (q15_t)0x7957, (q15_t)0x7955, (q15_t)0x7953, (q15_t)0x7951, (q15_t)0x794f, (q15_t)0x794d, (q15_t)0x794b,
+  (q15_t)0x7949, (q15_t)0x7947, (q15_t)0x7945, (q15_t)0x7943, (q15_t)0x7941, (q15_t)0x793f, (q15_t)0x793d, (q15_t)0x793b,
+  (q15_t)0x7939, (q15_t)0x7937, (q15_t)0x7935, (q15_t)0x7933, (q15_t)0x7931, (q15_t)0x792f, (q15_t)0x792d, (q15_t)0x792b,
+  (q15_t)0x7929, (q15_t)0x7927, (q15_t)0x7925, (q15_t)0x7923, (q15_t)0x7921, (q15_t)0x791f, (q15_t)0x791d, (q15_t)0x791a,
+  (q15_t)0x7918, (q15_t)0x7916, (q15_t)0x7914, (q15_t)0x7912, (q15_t)0x7910, (q15_t)0x790e, (q15_t)0x790c, (q15_t)0x790a,
+  (q15_t)0x7908, (q15_t)0x7906, (q15_t)0x7904, (q15_t)0x7902, (q15_t)0x7900, (q15_t)0x78fe, (q15_t)0x78fc, (q15_t)0x78fa,
+  (q15_t)0x78f8, (q15_t)0x78f6, (q15_t)0x78f4, (q15_t)0x78f2, (q15_t)0x78f0, (q15_t)0x78ed, (q15_t)0x78eb, (q15_t)0x78e9,
+  (q15_t)0x78e7, (q15_t)0x78e5, (q15_t)0x78e3, (q15_t)0x78e1, (q15_t)0x78df, (q15_t)0x78dd, (q15_t)0x78db, (q15_t)0x78d9,
+  (q15_t)0x78d7, (q15_t)0x78d5, (q15_t)0x78d3, (q15_t)0x78d1, (q15_t)0x78ce, (q15_t)0x78cc, (q15_t)0x78ca, (q15_t)0x78c8,
+  (q15_t)0x78c6, (q15_t)0x78c4, (q15_t)0x78c2, (q15_t)0x78c0, (q15_t)0x78be, (q15_t)0x78bc, (q15_t)0x78ba, (q15_t)0x78b8,
+  (q15_t)0x78b5, (q15_t)0x78b3, (q15_t)0x78b1, (q15_t)0x78af, (q15_t)0x78ad, (q15_t)0x78ab, (q15_t)0x78a9, (q15_t)0x78a7,
+  (q15_t)0x78a5, (q15_t)0x78a3, (q15_t)0x78a0, (q15_t)0x789e, (q15_t)0x789c, (q15_t)0x789a, (q15_t)0x7898, (q15_t)0x7896,
+  (q15_t)0x7894, (q15_t)0x7892, (q15_t)0x7890, (q15_t)0x788e, (q15_t)0x788b, (q15_t)0x7889, (q15_t)0x7887, (q15_t)0x7885,
+  (q15_t)0x7883, (q15_t)0x7881, (q15_t)0x787f, (q15_t)0x787d, (q15_t)0x787a, (q15_t)0x7878, (q15_t)0x7876, (q15_t)0x7874,
+  (q15_t)0x7872, (q15_t)0x7870, (q15_t)0x786e, (q15_t)0x786c, (q15_t)0x7869, (q15_t)0x7867, (q15_t)0x7865, (q15_t)0x7863,
+  (q15_t)0x7861, (q15_t)0x785f, (q15_t)0x785d, (q15_t)0x785b, (q15_t)0x7858, (q15_t)0x7856, (q15_t)0x7854, (q15_t)0x7852,
+  (q15_t)0x7850, (q15_t)0x784e, (q15_t)0x784c, (q15_t)0x7849, (q15_t)0x7847, (q15_t)0x7845, (q15_t)0x7843, (q15_t)0x7841,
+  (q15_t)0x783f, (q15_t)0x783c, (q15_t)0x783a, (q15_t)0x7838, (q15_t)0x7836, (q15_t)0x7834, (q15_t)0x7832, (q15_t)0x7830,
+  (q15_t)0x782d, (q15_t)0x782b, (q15_t)0x7829, (q15_t)0x7827, (q15_t)0x7825, (q15_t)0x7823, (q15_t)0x7820, (q15_t)0x781e,
+  (q15_t)0x781c, (q15_t)0x781a, (q15_t)0x7818, (q15_t)0x7816, (q15_t)0x7813, (q15_t)0x7811, (q15_t)0x780f, (q15_t)0x780d,
+  (q15_t)0x780b, (q15_t)0x7808, (q15_t)0x7806, (q15_t)0x7804, (q15_t)0x7802, (q15_t)0x7800, (q15_t)0x77fe, (q15_t)0x77fb,
+  (q15_t)0x77f9, (q15_t)0x77f7, (q15_t)0x77f5, (q15_t)0x77f3, (q15_t)0x77f0, (q15_t)0x77ee, (q15_t)0x77ec, (q15_t)0x77ea,
+  (q15_t)0x77e8, (q15_t)0x77e5, (q15_t)0x77e3, (q15_t)0x77e1, (q15_t)0x77df, (q15_t)0x77dd, (q15_t)0x77da, (q15_t)0x77d8,
+  (q15_t)0x77d6, (q15_t)0x77d4, (q15_t)0x77d2, (q15_t)0x77cf, (q15_t)0x77cd, (q15_t)0x77cb, (q15_t)0x77c9, (q15_t)0x77c6,
+  (q15_t)0x77c4, (q15_t)0x77c2, (q15_t)0x77c0, (q15_t)0x77be, (q15_t)0x77bb, (q15_t)0x77b9, (q15_t)0x77b7, (q15_t)0x77b5,
+  (q15_t)0x77b2, (q15_t)0x77b0, (q15_t)0x77ae, (q15_t)0x77ac, (q15_t)0x77aa, (q15_t)0x77a7, (q15_t)0x77a5, (q15_t)0x77a3,
+  (q15_t)0x77a1, (q15_t)0x779e, (q15_t)0x779c, (q15_t)0x779a, (q15_t)0x7798, (q15_t)0x7795, (q15_t)0x7793, (q15_t)0x7791,
+  (q15_t)0x778f, (q15_t)0x778c, (q15_t)0x778a, (q15_t)0x7788, (q15_t)0x7786, (q15_t)0x7783, (q15_t)0x7781, (q15_t)0x777f,
+  (q15_t)0x777d, (q15_t)0x777a, (q15_t)0x7778, (q15_t)0x7776, (q15_t)0x7774, (q15_t)0x7771, (q15_t)0x776f, (q15_t)0x776d,
+  (q15_t)0x776b, (q15_t)0x7768, (q15_t)0x7766, (q15_t)0x7764, (q15_t)0x7762, (q15_t)0x775f, (q15_t)0x775d, (q15_t)0x775b,
+  (q15_t)0x7759, (q15_t)0x7756, (q15_t)0x7754, (q15_t)0x7752, (q15_t)0x774f, (q15_t)0x774d, (q15_t)0x774b, (q15_t)0x7749,
+  (q15_t)0x7746, (q15_t)0x7744, (q15_t)0x7742, (q15_t)0x773f, (q15_t)0x773d, (q15_t)0x773b, (q15_t)0x7739, (q15_t)0x7736,
+  (q15_t)0x7734, (q15_t)0x7732, (q15_t)0x772f, (q15_t)0x772d, (q15_t)0x772b, (q15_t)0x7729, (q15_t)0x7726, (q15_t)0x7724,
+  (q15_t)0x7722, (q15_t)0x771f, (q15_t)0x771d, (q15_t)0x771b, (q15_t)0x7719, (q15_t)0x7716, (q15_t)0x7714, (q15_t)0x7712,
+  (q15_t)0x770f, (q15_t)0x770d, (q15_t)0x770b, (q15_t)0x7708, (q15_t)0x7706, (q15_t)0x7704, (q15_t)0x7701, (q15_t)0x76ff,
+  (q15_t)0x76fd, (q15_t)0x76fa, (q15_t)0x76f8, (q15_t)0x76f6, (q15_t)0x76f4, (q15_t)0x76f1, (q15_t)0x76ef, (q15_t)0x76ed,
+  (q15_t)0x76ea, (q15_t)0x76e8, (q15_t)0x76e6, (q15_t)0x76e3, (q15_t)0x76e1, (q15_t)0x76df, (q15_t)0x76dc, (q15_t)0x76da,
+  (q15_t)0x76d8, (q15_t)0x76d5, (q15_t)0x76d3, (q15_t)0x76d1, (q15_t)0x76ce, (q15_t)0x76cc, (q15_t)0x76ca, (q15_t)0x76c7,
+  (q15_t)0x76c5, (q15_t)0x76c3, (q15_t)0x76c0, (q15_t)0x76be, (q15_t)0x76bc, (q15_t)0x76b9, (q15_t)0x76b7, (q15_t)0x76b4,
+  (q15_t)0x76b2, (q15_t)0x76b0, (q15_t)0x76ad, (q15_t)0x76ab, (q15_t)0x76a9, (q15_t)0x76a6, (q15_t)0x76a4, (q15_t)0x76a2,
+  (q15_t)0x769f, (q15_t)0x769d, (q15_t)0x769b, (q15_t)0x7698, (q15_t)0x7696, (q15_t)0x7693, (q15_t)0x7691, (q15_t)0x768f,
+  (q15_t)0x768c, (q15_t)0x768a, (q15_t)0x7688, (q15_t)0x7685, (q15_t)0x7683, (q15_t)0x7681, (q15_t)0x767e, (q15_t)0x767c,
+  (q15_t)0x7679, (q15_t)0x7677, (q15_t)0x7675, (q15_t)0x7672, (q15_t)0x7670, (q15_t)0x766d, (q15_t)0x766b, (q15_t)0x7669,
+  (q15_t)0x7666, (q15_t)0x7664, (q15_t)0x7662, (q15_t)0x765f, (q15_t)0x765d, (q15_t)0x765a, (q15_t)0x7658, (q15_t)0x7656,
+  (q15_t)0x7653, (q15_t)0x7651, (q15_t)0x764e, (q15_t)0x764c, (q15_t)0x764a, (q15_t)0x7647, (q15_t)0x7645, (q15_t)0x7642,
+  (q15_t)0x7640, (q15_t)0x763e, (q15_t)0x763b, (q15_t)0x7639, (q15_t)0x7636, (q15_t)0x7634, (q15_t)0x7632, (q15_t)0x762f,
+  (q15_t)0x762d, (q15_t)0x762a, (q15_t)0x7628, (q15_t)0x7625, (q15_t)0x7623, (q15_t)0x7621, (q15_t)0x761e, (q15_t)0x761c,
+  (q15_t)0x7619, (q15_t)0x7617, (q15_t)0x7615, (q15_t)0x7612, (q15_t)0x7610, (q15_t)0x760d, (q15_t)0x760b, (q15_t)0x7608,
+  (q15_t)0x7606, (q15_t)0x7604, (q15_t)0x7601, (q15_t)0x75ff, (q15_t)0x75fc, (q15_t)0x75fa, (q15_t)0x75f7, (q15_t)0x75f5,
+  (q15_t)0x75f2, (q15_t)0x75f0, (q15_t)0x75ee, (q15_t)0x75eb, (q15_t)0x75e9, (q15_t)0x75e6, (q15_t)0x75e4, (q15_t)0x75e1,
+  (q15_t)0x75df, (q15_t)0x75dc, (q15_t)0x75da, (q15_t)0x75d8, (q15_t)0x75d5, (q15_t)0x75d3, (q15_t)0x75d0, (q15_t)0x75ce,
+  (q15_t)0x75cb, (q15_t)0x75c9, (q15_t)0x75c6, (q15_t)0x75c4, (q15_t)0x75c1, (q15_t)0x75bf, (q15_t)0x75bc, (q15_t)0x75ba,
+  (q15_t)0x75b8, (q15_t)0x75b5, (q15_t)0x75b3, (q15_t)0x75b0, (q15_t)0x75ae, (q15_t)0x75ab, (q15_t)0x75a9, (q15_t)0x75a6,
+  (q15_t)0x75a4, (q15_t)0x75a1, (q15_t)0x759f, (q15_t)0x759c, (q15_t)0x759a, (q15_t)0x7597, (q15_t)0x7595, (q15_t)0x7592,
+  (q15_t)0x7590, (q15_t)0x758d, (q15_t)0x758b, (q15_t)0x7588, (q15_t)0x7586, (q15_t)0x7584, (q15_t)0x7581, (q15_t)0x757f,
+  (q15_t)0x757c, (q15_t)0x757a, (q15_t)0x7577, (q15_t)0x7575, (q15_t)0x7572, (q15_t)0x7570, (q15_t)0x756d, (q15_t)0x756b,
+  (q15_t)0x7568, (q15_t)0x7566, (q15_t)0x7563, (q15_t)0x7561, (q15_t)0x755e, (q15_t)0x755c, (q15_t)0x7559, (q15_t)0x7556,
+  (q15_t)0x7554, (q15_t)0x7551, (q15_t)0x754f, (q15_t)0x754c, (q15_t)0x754a, (q15_t)0x7547, (q15_t)0x7545, (q15_t)0x7542,
+  (q15_t)0x7540, (q15_t)0x753d, (q15_t)0x753b, (q15_t)0x7538, (q15_t)0x7536, (q15_t)0x7533, (q15_t)0x7531, (q15_t)0x752e,
+  (q15_t)0x752c, (q15_t)0x7529, (q15_t)0x7527, (q15_t)0x7524, (q15_t)0x7522, (q15_t)0x751f, (q15_t)0x751c, (q15_t)0x751a,
+  (q15_t)0x7517, (q15_t)0x7515, (q15_t)0x7512, (q15_t)0x7510, (q15_t)0x750d, (q15_t)0x750b, (q15_t)0x7508, (q15_t)0x7506,
+  (q15_t)0x7503, (q15_t)0x7501, (q15_t)0x74fe, (q15_t)0x74fb, (q15_t)0x74f9, (q15_t)0x74f6, (q15_t)0x74f4, (q15_t)0x74f1,
+  (q15_t)0x74ef, (q15_t)0x74ec, (q15_t)0x74ea, (q15_t)0x74e7, (q15_t)0x74e4, (q15_t)0x74e2, (q15_t)0x74df, (q15_t)0x74dd,
+  (q15_t)0x74da, (q15_t)0x74d8, (q15_t)0x74d5, (q15_t)0x74d2, (q15_t)0x74d0, (q15_t)0x74cd, (q15_t)0x74cb, (q15_t)0x74c8,
+  (q15_t)0x74c6, (q15_t)0x74c3, (q15_t)0x74c0, (q15_t)0x74be, (q15_t)0x74bb, (q15_t)0x74b9, (q15_t)0x74b6, (q15_t)0x74b4,
+  (q15_t)0x74b1, (q15_t)0x74ae, (q15_t)0x74ac, (q15_t)0x74a9, (q15_t)0x74a7, (q15_t)0x74a4, (q15_t)0x74a1, (q15_t)0x749f,
+  (q15_t)0x749c, (q15_t)0x749a, (q15_t)0x7497, (q15_t)0x7495, (q15_t)0x7492, (q15_t)0x748f, (q15_t)0x748d, (q15_t)0x748a,
+  (q15_t)0x7488, (q15_t)0x7485, (q15_t)0x7482, (q15_t)0x7480, (q15_t)0x747d, (q15_t)0x747b, (q15_t)0x7478, (q15_t)0x7475,
+  (q15_t)0x7473, (q15_t)0x7470, (q15_t)0x746d, (q15_t)0x746b, (q15_t)0x7468, (q15_t)0x7466, (q15_t)0x7463, (q15_t)0x7460,
+  (q15_t)0x745e, (q15_t)0x745b, (q15_t)0x7459, (q15_t)0x7456, (q15_t)0x7453, (q15_t)0x7451, (q15_t)0x744e, (q15_t)0x744b,
+  (q15_t)0x7449, (q15_t)0x7446, (q15_t)0x7444, (q15_t)0x7441, (q15_t)0x743e, (q15_t)0x743c, (q15_t)0x7439, (q15_t)0x7436,
+  (q15_t)0x7434, (q15_t)0x7431, (q15_t)0x742f, (q15_t)0x742c, (q15_t)0x7429, (q15_t)0x7427, (q15_t)0x7424, (q15_t)0x7421,
+  (q15_t)0x741f, (q15_t)0x741c, (q15_t)0x7419, (q15_t)0x7417, (q15_t)0x7414, (q15_t)0x7411, (q15_t)0x740f, (q15_t)0x740c,
+  (q15_t)0x740a, (q15_t)0x7407, (q15_t)0x7404, (q15_t)0x7402, (q15_t)0x73ff, (q15_t)0x73fc, (q15_t)0x73fa, (q15_t)0x73f7,
+  (q15_t)0x73f4, (q15_t)0x73f2, (q15_t)0x73ef, (q15_t)0x73ec, (q15_t)0x73ea, (q15_t)0x73e7, (q15_t)0x73e4, (q15_t)0x73e2,
+  (q15_t)0x73df, (q15_t)0x73dc, (q15_t)0x73da, (q15_t)0x73d7, (q15_t)0x73d4, (q15_t)0x73d2, (q15_t)0x73cf, (q15_t)0x73cc,
+  (q15_t)0x73ca, (q15_t)0x73c7, (q15_t)0x73c4, (q15_t)0x73c1, (q15_t)0x73bf, (q15_t)0x73bc, (q15_t)0x73b9, (q15_t)0x73b7,
+  (q15_t)0x73b4, (q15_t)0x73b1, (q15_t)0x73af, (q15_t)0x73ac, (q15_t)0x73a9, (q15_t)0x73a7, (q15_t)0x73a4, (q15_t)0x73a1,
+  (q15_t)0x739f, (q15_t)0x739c, (q15_t)0x7399, (q15_t)0x7396, (q15_t)0x7394, (q15_t)0x7391, (q15_t)0x738e, (q15_t)0x738c,
+  (q15_t)0x7389, (q15_t)0x7386, (q15_t)0x7384, (q15_t)0x7381, (q15_t)0x737e, (q15_t)0x737b, (q15_t)0x7379, (q15_t)0x7376,
+  (q15_t)0x7373, (q15_t)0x7371, (q15_t)0x736e, (q15_t)0x736b, (q15_t)0x7368, (q15_t)0x7366, (q15_t)0x7363, (q15_t)0x7360,
+  (q15_t)0x735e, (q15_t)0x735b, (q15_t)0x7358, (q15_t)0x7355, (q15_t)0x7353, (q15_t)0x7350, (q15_t)0x734d, (q15_t)0x734a,
+  (q15_t)0x7348, (q15_t)0x7345, (q15_t)0x7342, (q15_t)0x7340, (q15_t)0x733d, (q15_t)0x733a, (q15_t)0x7337, (q15_t)0x7335,
+  (q15_t)0x7332, (q15_t)0x732f, (q15_t)0x732c, (q15_t)0x732a, (q15_t)0x7327, (q15_t)0x7324, (q15_t)0x7321, (q15_t)0x731f,
+  (q15_t)0x731c, (q15_t)0x7319, (q15_t)0x7316, (q15_t)0x7314, (q15_t)0x7311, (q15_t)0x730e, (q15_t)0x730b, (q15_t)0x7309,
+  (q15_t)0x7306, (q15_t)0x7303, (q15_t)0x7300, (q15_t)0x72fe, (q15_t)0x72fb, (q15_t)0x72f8, (q15_t)0x72f5, (q15_t)0x72f3,
+  (q15_t)0x72f0, (q15_t)0x72ed, (q15_t)0x72ea, (q15_t)0x72e8, (q15_t)0x72e5, (q15_t)0x72e2, (q15_t)0x72df, (q15_t)0x72dc,
+  (q15_t)0x72da, (q15_t)0x72d7, (q15_t)0x72d4, (q15_t)0x72d1, (q15_t)0x72cf, (q15_t)0x72cc, (q15_t)0x72c9, (q15_t)0x72c6,
+  (q15_t)0x72c3, (q15_t)0x72c1, (q15_t)0x72be, (q15_t)0x72bb, (q15_t)0x72b8, (q15_t)0x72b5, (q15_t)0x72b3, (q15_t)0x72b0,
+  (q15_t)0x72ad, (q15_t)0x72aa, (q15_t)0x72a8, (q15_t)0x72a5, (q15_t)0x72a2, (q15_t)0x729f, (q15_t)0x729c, (q15_t)0x729a,
+  (q15_t)0x7297, (q15_t)0x7294, (q15_t)0x7291, (q15_t)0x728e, (q15_t)0x728c, (q15_t)0x7289, (q15_t)0x7286, (q15_t)0x7283,
+  (q15_t)0x7280, (q15_t)0x727e, (q15_t)0x727b, (q15_t)0x7278, (q15_t)0x7275, (q15_t)0x7272, (q15_t)0x726f, (q15_t)0x726d,
+  (q15_t)0x726a, (q15_t)0x7267, (q15_t)0x7264, (q15_t)0x7261, (q15_t)0x725f, (q15_t)0x725c, (q15_t)0x7259, (q15_t)0x7256,
+  (q15_t)0x7253, (q15_t)0x7250, (q15_t)0x724e, (q15_t)0x724b, (q15_t)0x7248, (q15_t)0x7245, (q15_t)0x7242, (q15_t)0x723f,
+  (q15_t)0x723d, (q15_t)0x723a, (q15_t)0x7237, (q15_t)0x7234, (q15_t)0x7231, (q15_t)0x722e, (q15_t)0x722c, (q15_t)0x7229,
+  (q15_t)0x7226, (q15_t)0x7223, (q15_t)0x7220, (q15_t)0x721d, (q15_t)0x721b, (q15_t)0x7218, (q15_t)0x7215, (q15_t)0x7212,
+  (q15_t)0x720f, (q15_t)0x720c, (q15_t)0x7209, (q15_t)0x7207, (q15_t)0x7204, (q15_t)0x7201, (q15_t)0x71fe, (q15_t)0x71fb,
+  (q15_t)0x71f8, (q15_t)0x71f5, (q15_t)0x71f3, (q15_t)0x71f0, (q15_t)0x71ed, (q15_t)0x71ea, (q15_t)0x71e7, (q15_t)0x71e4,
+  (q15_t)0x71e1, (q15_t)0x71df, (q15_t)0x71dc, (q15_t)0x71d9, (q15_t)0x71d6, (q15_t)0x71d3, (q15_t)0x71d0, (q15_t)0x71cd,
+  (q15_t)0x71ca, (q15_t)0x71c8, (q15_t)0x71c5, (q15_t)0x71c2, (q15_t)0x71bf, (q15_t)0x71bc, (q15_t)0x71b9, (q15_t)0x71b6,
+  (q15_t)0x71b3, (q15_t)0x71b0, (q15_t)0x71ae, (q15_t)0x71ab, (q15_t)0x71a8, (q15_t)0x71a5, (q15_t)0x71a2, (q15_t)0x719f,
+  (q15_t)0x719c, (q15_t)0x7199, (q15_t)0x7196, (q15_t)0x7194, (q15_t)0x7191, (q15_t)0x718e, (q15_t)0x718b, (q15_t)0x7188,
+  (q15_t)0x7185, (q15_t)0x7182, (q15_t)0x717f, (q15_t)0x717c, (q15_t)0x7179, (q15_t)0x7177, (q15_t)0x7174, (q15_t)0x7171,
+  (q15_t)0x716e, (q15_t)0x716b, (q15_t)0x7168, (q15_t)0x7165, (q15_t)0x7162, (q15_t)0x715f, (q15_t)0x715c, (q15_t)0x7159,
+  (q15_t)0x7156, (q15_t)0x7154, (q15_t)0x7151, (q15_t)0x714e, (q15_t)0x714b, (q15_t)0x7148, (q15_t)0x7145, (q15_t)0x7142,
+  (q15_t)0x713f, (q15_t)0x713c, (q15_t)0x7139, (q15_t)0x7136, (q15_t)0x7133, (q15_t)0x7130, (q15_t)0x712d, (q15_t)0x712b,
+  (q15_t)0x7128, (q15_t)0x7125, (q15_t)0x7122, (q15_t)0x711f, (q15_t)0x711c, (q15_t)0x7119, (q15_t)0x7116, (q15_t)0x7113,
+  (q15_t)0x7110, (q15_t)0x710d, (q15_t)0x710a, (q15_t)0x7107, (q15_t)0x7104, (q15_t)0x7101, (q15_t)0x70fe, (q15_t)0x70fb,
+  (q15_t)0x70f8, (q15_t)0x70f6, (q15_t)0x70f3, (q15_t)0x70f0, (q15_t)0x70ed, (q15_t)0x70ea, (q15_t)0x70e7, (q15_t)0x70e4,
+  (q15_t)0x70e1, (q15_t)0x70de, (q15_t)0x70db, (q15_t)0x70d8, (q15_t)0x70d5, (q15_t)0x70d2, (q15_t)0x70cf, (q15_t)0x70cc,
+  (q15_t)0x70c9, (q15_t)0x70c6, (q15_t)0x70c3, (q15_t)0x70c0, (q15_t)0x70bd, (q15_t)0x70ba, (q15_t)0x70b7, (q15_t)0x70b4,
+  (q15_t)0x70b1, (q15_t)0x70ae, (q15_t)0x70ab, (q15_t)0x70a8, (q15_t)0x70a5, (q15_t)0x70a2, (q15_t)0x709f, (q15_t)0x709c,
+  (q15_t)0x7099, (q15_t)0x7096, (q15_t)0x7093, (q15_t)0x7090, (q15_t)0x708d, (q15_t)0x708a, (q15_t)0x7087, (q15_t)0x7084,
+  (q15_t)0x7081, (q15_t)0x707e, (q15_t)0x707b, (q15_t)0x7078, (q15_t)0x7075, (q15_t)0x7072, (q15_t)0x706f, (q15_t)0x706c,
+  (q15_t)0x7069, (q15_t)0x7066, (q15_t)0x7063, (q15_t)0x7060, (q15_t)0x705d, (q15_t)0x705a, (q15_t)0x7057, (q15_t)0x7054,
+  (q15_t)0x7051, (q15_t)0x704e, (q15_t)0x704b, (q15_t)0x7048, (q15_t)0x7045, (q15_t)0x7042, (q15_t)0x703f, (q15_t)0x703c,
+  (q15_t)0x7039, (q15_t)0x7036, (q15_t)0x7033, (q15_t)0x7030, (q15_t)0x702d, (q15_t)0x702a, (q15_t)0x7027, (q15_t)0x7024,
+  (q15_t)0x7021, (q15_t)0x701e, (q15_t)0x701b, (q15_t)0x7018, (q15_t)0x7015, (q15_t)0x7012, (q15_t)0x700f, (q15_t)0x700c,
+  (q15_t)0x7009, (q15_t)0x7006, (q15_t)0x7003, (q15_t)0x7000, (q15_t)0x6ffd, (q15_t)0x6ffa, (q15_t)0x6ff7, (q15_t)0x6ff3,
+  (q15_t)0x6ff0, (q15_t)0x6fed, (q15_t)0x6fea, (q15_t)0x6fe7, (q15_t)0x6fe4, (q15_t)0x6fe1, (q15_t)0x6fde, (q15_t)0x6fdb,
+  (q15_t)0x6fd8, (q15_t)0x6fd5, (q15_t)0x6fd2, (q15_t)0x6fcf, (q15_t)0x6fcc, (q15_t)0x6fc9, (q15_t)0x6fc6, (q15_t)0x6fc3,
+  (q15_t)0x6fc0, (q15_t)0x6fbc, (q15_t)0x6fb9, (q15_t)0x6fb6, (q15_t)0x6fb3, (q15_t)0x6fb0, (q15_t)0x6fad, (q15_t)0x6faa,
+  (q15_t)0x6fa7, (q15_t)0x6fa4, (q15_t)0x6fa1, (q15_t)0x6f9e, (q15_t)0x6f9b, (q15_t)0x6f98, (q15_t)0x6f95, (q15_t)0x6f91,
+  (q15_t)0x6f8e, (q15_t)0x6f8b, (q15_t)0x6f88, (q15_t)0x6f85, (q15_t)0x6f82, (q15_t)0x6f7f, (q15_t)0x6f7c, (q15_t)0x6f79,
+  (q15_t)0x6f76, (q15_t)0x6f73, (q15_t)0x6f70, (q15_t)0x6f6c, (q15_t)0x6f69, (q15_t)0x6f66, (q15_t)0x6f63, (q15_t)0x6f60,
+  (q15_t)0x6f5d, (q15_t)0x6f5a, (q15_t)0x6f57, (q15_t)0x6f54, (q15_t)0x6f51, (q15_t)0x6f4d, (q15_t)0x6f4a, (q15_t)0x6f47,
+  (q15_t)0x6f44, (q15_t)0x6f41, (q15_t)0x6f3e, (q15_t)0x6f3b, (q15_t)0x6f38, (q15_t)0x6f35, (q15_t)0x6f31, (q15_t)0x6f2e,
+  (q15_t)0x6f2b, (q15_t)0x6f28, (q15_t)0x6f25, (q15_t)0x6f22, (q15_t)0x6f1f, (q15_t)0x6f1c, (q15_t)0x6f19, (q15_t)0x6f15,
+  (q15_t)0x6f12, (q15_t)0x6f0f, (q15_t)0x6f0c, (q15_t)0x6f09, (q15_t)0x6f06, (q15_t)0x6f03, (q15_t)0x6f00, (q15_t)0x6efc,
+  (q15_t)0x6ef9, (q15_t)0x6ef6, (q15_t)0x6ef3, (q15_t)0x6ef0, (q15_t)0x6eed, (q15_t)0x6eea, (q15_t)0x6ee7, (q15_t)0x6ee3,
+  (q15_t)0x6ee0, (q15_t)0x6edd, (q15_t)0x6eda, (q15_t)0x6ed7, (q15_t)0x6ed4, (q15_t)0x6ed1, (q15_t)0x6ecd, (q15_t)0x6eca,
+  (q15_t)0x6ec7, (q15_t)0x6ec4, (q15_t)0x6ec1, (q15_t)0x6ebe, (q15_t)0x6eba, (q15_t)0x6eb7, (q15_t)0x6eb4, (q15_t)0x6eb1,
+  (q15_t)0x6eae, (q15_t)0x6eab, (q15_t)0x6ea8, (q15_t)0x6ea4, (q15_t)0x6ea1, (q15_t)0x6e9e, (q15_t)0x6e9b, (q15_t)0x6e98,
+  (q15_t)0x6e95, (q15_t)0x6e91, (q15_t)0x6e8e, (q15_t)0x6e8b, (q15_t)0x6e88, (q15_t)0x6e85, (q15_t)0x6e82, (q15_t)0x6e7e,
+  (q15_t)0x6e7b, (q15_t)0x6e78, (q15_t)0x6e75, (q15_t)0x6e72, (q15_t)0x6e6f, (q15_t)0x6e6b, (q15_t)0x6e68, (q15_t)0x6e65,
+  (q15_t)0x6e62, (q15_t)0x6e5f, (q15_t)0x6e5b, (q15_t)0x6e58, (q15_t)0x6e55, (q15_t)0x6e52, (q15_t)0x6e4f, (q15_t)0x6e4c,
+  (q15_t)0x6e48, (q15_t)0x6e45, (q15_t)0x6e42, (q15_t)0x6e3f, (q15_t)0x6e3c, (q15_t)0x6e38, (q15_t)0x6e35, (q15_t)0x6e32,
+  (q15_t)0x6e2f, (q15_t)0x6e2c, (q15_t)0x6e28, (q15_t)0x6e25, (q15_t)0x6e22, (q15_t)0x6e1f, (q15_t)0x6e1c, (q15_t)0x6e18,
+  (q15_t)0x6e15, (q15_t)0x6e12, (q15_t)0x6e0f, (q15_t)0x6e0c, (q15_t)0x6e08, (q15_t)0x6e05, (q15_t)0x6e02, (q15_t)0x6dff,
+  (q15_t)0x6dfb, (q15_t)0x6df8, (q15_t)0x6df5, (q15_t)0x6df2, (q15_t)0x6def, (q15_t)0x6deb, (q15_t)0x6de8, (q15_t)0x6de5,
+  (q15_t)0x6de2, (q15_t)0x6ddf, (q15_t)0x6ddb, (q15_t)0x6dd8, (q15_t)0x6dd5, (q15_t)0x6dd2, (q15_t)0x6dce, (q15_t)0x6dcb,
+  (q15_t)0x6dc8, (q15_t)0x6dc5, (q15_t)0x6dc1, (q15_t)0x6dbe, (q15_t)0x6dbb, (q15_t)0x6db8, (q15_t)0x6db5, (q15_t)0x6db1,
+  (q15_t)0x6dae, (q15_t)0x6dab, (q15_t)0x6da8, (q15_t)0x6da4, (q15_t)0x6da1, (q15_t)0x6d9e, (q15_t)0x6d9b, (q15_t)0x6d97,
+  (q15_t)0x6d94, (q15_t)0x6d91, (q15_t)0x6d8e, (q15_t)0x6d8a, (q15_t)0x6d87, (q15_t)0x6d84, (q15_t)0x6d81, (q15_t)0x6d7d,
+  (q15_t)0x6d7a, (q15_t)0x6d77, (q15_t)0x6d74, (q15_t)0x6d70, (q15_t)0x6d6d, (q15_t)0x6d6a, (q15_t)0x6d67, (q15_t)0x6d63,
+  (q15_t)0x6d60, (q15_t)0x6d5d, (q15_t)0x6d59, (q15_t)0x6d56, (q15_t)0x6d53, (q15_t)0x6d50, (q15_t)0x6d4c, (q15_t)0x6d49,
+  (q15_t)0x6d46, (q15_t)0x6d43, (q15_t)0x6d3f, (q15_t)0x6d3c, (q15_t)0x6d39, (q15_t)0x6d36, (q15_t)0x6d32, (q15_t)0x6d2f,
+  (q15_t)0x6d2c, (q15_t)0x6d28, (q15_t)0x6d25, (q15_t)0x6d22, (q15_t)0x6d1f, (q15_t)0x6d1b, (q15_t)0x6d18, (q15_t)0x6d15,
+  (q15_t)0x6d11, (q15_t)0x6d0e, (q15_t)0x6d0b, (q15_t)0x6d08, (q15_t)0x6d04, (q15_t)0x6d01, (q15_t)0x6cfe, (q15_t)0x6cfa,
+  (q15_t)0x6cf7, (q15_t)0x6cf4, (q15_t)0x6cf0, (q15_t)0x6ced, (q15_t)0x6cea, (q15_t)0x6ce7, (q15_t)0x6ce3, (q15_t)0x6ce0,
+  (q15_t)0x6cdd, (q15_t)0x6cd9, (q15_t)0x6cd6, (q15_t)0x6cd3, (q15_t)0x6ccf, (q15_t)0x6ccc, (q15_t)0x6cc9, (q15_t)0x6cc5,
+  (q15_t)0x6cc2, (q15_t)0x6cbf, (q15_t)0x6cbc, (q15_t)0x6cb8, (q15_t)0x6cb5, (q15_t)0x6cb2, (q15_t)0x6cae, (q15_t)0x6cab,
+  (q15_t)0x6ca8, (q15_t)0x6ca4, (q15_t)0x6ca1, (q15_t)0x6c9e, (q15_t)0x6c9a, (q15_t)0x6c97, (q15_t)0x6c94, (q15_t)0x6c90,
+  (q15_t)0x6c8d, (q15_t)0x6c8a, (q15_t)0x6c86, (q15_t)0x6c83, (q15_t)0x6c80, (q15_t)0x6c7c, (q15_t)0x6c79, (q15_t)0x6c76,
+  (q15_t)0x6c72, (q15_t)0x6c6f, (q15_t)0x6c6c, (q15_t)0x6c68, (q15_t)0x6c65, (q15_t)0x6c62, (q15_t)0x6c5e, (q15_t)0x6c5b,
+  (q15_t)0x6c58, (q15_t)0x6c54, (q15_t)0x6c51, (q15_t)0x6c4e, (q15_t)0x6c4a, (q15_t)0x6c47, (q15_t)0x6c44, (q15_t)0x6c40,
+  (q15_t)0x6c3d, (q15_t)0x6c39, (q15_t)0x6c36, (q15_t)0x6c33, (q15_t)0x6c2f, (q15_t)0x6c2c, (q15_t)0x6c29, (q15_t)0x6c25,
+  (q15_t)0x6c22, (q15_t)0x6c1f, (q15_t)0x6c1b, (q15_t)0x6c18, (q15_t)0x6c15, (q15_t)0x6c11, (q15_t)0x6c0e, (q15_t)0x6c0a,
+  (q15_t)0x6c07, (q15_t)0x6c04, (q15_t)0x6c00, (q15_t)0x6bfd, (q15_t)0x6bfa, (q15_t)0x6bf6, (q15_t)0x6bf3, (q15_t)0x6bef,
+  (q15_t)0x6bec, (q15_t)0x6be9, (q15_t)0x6be5, (q15_t)0x6be2, (q15_t)0x6bdf, (q15_t)0x6bdb, (q15_t)0x6bd8, (q15_t)0x6bd4,
+  (q15_t)0x6bd1, (q15_t)0x6bce, (q15_t)0x6bca, (q15_t)0x6bc7, (q15_t)0x6bc3, (q15_t)0x6bc0, (q15_t)0x6bbd, (q15_t)0x6bb9,
+  (q15_t)0x6bb6, (q15_t)0x6bb2, (q15_t)0x6baf, (q15_t)0x6bac, (q15_t)0x6ba8, (q15_t)0x6ba5, (q15_t)0x6ba1, (q15_t)0x6b9e,
+  (q15_t)0x6b9b, (q15_t)0x6b97, (q15_t)0x6b94, (q15_t)0x6b90, (q15_t)0x6b8d, (q15_t)0x6b8a, (q15_t)0x6b86, (q15_t)0x6b83,
+  (q15_t)0x6b7f, (q15_t)0x6b7c, (q15_t)0x6b79, (q15_t)0x6b75, (q15_t)0x6b72, (q15_t)0x6b6e, (q15_t)0x6b6b, (q15_t)0x6b68,
+  (q15_t)0x6b64, (q15_t)0x6b61, (q15_t)0x6b5d, (q15_t)0x6b5a, (q15_t)0x6b56, (q15_t)0x6b53, (q15_t)0x6b50, (q15_t)0x6b4c,
+  (q15_t)0x6b49, (q15_t)0x6b45, (q15_t)0x6b42, (q15_t)0x6b3e, (q15_t)0x6b3b, (q15_t)0x6b38, (q15_t)0x6b34, (q15_t)0x6b31,
+  (q15_t)0x6b2d, (q15_t)0x6b2a, (q15_t)0x6b26, (q15_t)0x6b23, (q15_t)0x6b20, (q15_t)0x6b1c, (q15_t)0x6b19, (q15_t)0x6b15,
+  (q15_t)0x6b12, (q15_t)0x6b0e, (q15_t)0x6b0b, (q15_t)0x6b07, (q15_t)0x6b04, (q15_t)0x6b01, (q15_t)0x6afd, (q15_t)0x6afa,
+  (q15_t)0x6af6, (q15_t)0x6af3, (q15_t)0x6aef, (q15_t)0x6aec, (q15_t)0x6ae8, (q15_t)0x6ae5, (q15_t)0x6ae1, (q15_t)0x6ade,
+  (q15_t)0x6adb, (q15_t)0x6ad7, (q15_t)0x6ad4, (q15_t)0x6ad0, (q15_t)0x6acd, (q15_t)0x6ac9, (q15_t)0x6ac6, (q15_t)0x6ac2,
+  (q15_t)0x6abf, (q15_t)0x6abb, (q15_t)0x6ab8, (q15_t)0x6ab4, (q15_t)0x6ab1, (q15_t)0x6aae, (q15_t)0x6aaa, (q15_t)0x6aa7,
+  (q15_t)0x6aa3, (q15_t)0x6aa0, (q15_t)0x6a9c, (q15_t)0x6a99, (q15_t)0x6a95, (q15_t)0x6a92, (q15_t)0x6a8e, (q15_t)0x6a8b,
+  (q15_t)0x6a87, (q15_t)0x6a84, (q15_t)0x6a80, (q15_t)0x6a7d, (q15_t)0x6a79, (q15_t)0x6a76, (q15_t)0x6a72, (q15_t)0x6a6f,
+  (q15_t)0x6a6b, (q15_t)0x6a68, (q15_t)0x6a64, (q15_t)0x6a61, (q15_t)0x6a5d, (q15_t)0x6a5a, (q15_t)0x6a56, (q15_t)0x6a53,
+  (q15_t)0x6a4f, (q15_t)0x6a4c, (q15_t)0x6a48, (q15_t)0x6a45, (q15_t)0x6a41, (q15_t)0x6a3e, (q15_t)0x6a3a, (q15_t)0x6a37,
+  (q15_t)0x6a33, (q15_t)0x6a30, (q15_t)0x6a2c, (q15_t)0x6a29, (q15_t)0x6a25, (q15_t)0x6a22, (q15_t)0x6a1e, (q15_t)0x6a1b,
+  (q15_t)0x6a17, (q15_t)0x6a14, (q15_t)0x6a10, (q15_t)0x6a0d, (q15_t)0x6a09, (q15_t)0x6a06, (q15_t)0x6a02, (q15_t)0x69ff,
+  (q15_t)0x69fb, (q15_t)0x69f8, (q15_t)0x69f4, (q15_t)0x69f1, (q15_t)0x69ed, (q15_t)0x69e9, (q15_t)0x69e6, (q15_t)0x69e2,
+  (q15_t)0x69df, (q15_t)0x69db, (q15_t)0x69d8, (q15_t)0x69d4, (q15_t)0x69d1, (q15_t)0x69cd, (q15_t)0x69ca, (q15_t)0x69c6,
+  (q15_t)0x69c3, (q15_t)0x69bf, (q15_t)0x69bc, (q15_t)0x69b8, (q15_t)0x69b4, (q15_t)0x69b1, (q15_t)0x69ad, (q15_t)0x69aa,
+  (q15_t)0x69a6, (q15_t)0x69a3, (q15_t)0x699f, (q15_t)0x699c, (q15_t)0x6998, (q15_t)0x6995, (q15_t)0x6991, (q15_t)0x698d,
+  (q15_t)0x698a, (q15_t)0x6986, (q15_t)0x6983, (q15_t)0x697f, (q15_t)0x697c, (q15_t)0x6978, (q15_t)0x6975, (q15_t)0x6971,
+  (q15_t)0x696d, (q15_t)0x696a, (q15_t)0x6966, (q15_t)0x6963, (q15_t)0x695f, (q15_t)0x695c, (q15_t)0x6958, (q15_t)0x6954,
+  (q15_t)0x6951, (q15_t)0x694d, (q15_t)0x694a, (q15_t)0x6946, (q15_t)0x6943, (q15_t)0x693f, (q15_t)0x693b, (q15_t)0x6938,
+  (q15_t)0x6934, (q15_t)0x6931, (q15_t)0x692d, (q15_t)0x692a, (q15_t)0x6926, (q15_t)0x6922, (q15_t)0x691f, (q15_t)0x691b,
+  (q15_t)0x6918, (q15_t)0x6914, (q15_t)0x6910, (q15_t)0x690d, (q15_t)0x6909, (q15_t)0x6906, (q15_t)0x6902, (q15_t)0x68fe,
+  (q15_t)0x68fb, (q15_t)0x68f7, (q15_t)0x68f4, (q15_t)0x68f0, (q15_t)0x68ec, (q15_t)0x68e9, (q15_t)0x68e5, (q15_t)0x68e2,
+  (q15_t)0x68de, (q15_t)0x68da, (q15_t)0x68d7, (q15_t)0x68d3, (q15_t)0x68d0, (q15_t)0x68cc, (q15_t)0x68c8, (q15_t)0x68c5,
+  (q15_t)0x68c1, (q15_t)0x68be, (q15_t)0x68ba, (q15_t)0x68b6, (q15_t)0x68b3, (q15_t)0x68af, (q15_t)0x68ac, (q15_t)0x68a8,
+  (q15_t)0x68a4, (q15_t)0x68a1, (q15_t)0x689d, (q15_t)0x6899, (q15_t)0x6896, (q15_t)0x6892, (q15_t)0x688f, (q15_t)0x688b,
+  (q15_t)0x6887, (q15_t)0x6884, (q15_t)0x6880, (q15_t)0x687c, (q15_t)0x6879, (q15_t)0x6875, (q15_t)0x6872, (q15_t)0x686e,
+  (q15_t)0x686a, (q15_t)0x6867, (q15_t)0x6863, (q15_t)0x685f, (q15_t)0x685c, (q15_t)0x6858, (q15_t)0x6854, (q15_t)0x6851,
+  (q15_t)0x684d, (q15_t)0x684a, (q15_t)0x6846, (q15_t)0x6842, (q15_t)0x683f, (q15_t)0x683b, (q15_t)0x6837, (q15_t)0x6834,
+  (q15_t)0x6830, (q15_t)0x682c, (q15_t)0x6829, (q15_t)0x6825, (q15_t)0x6821, (q15_t)0x681e, (q15_t)0x681a, (q15_t)0x6816,
+  (q15_t)0x6813, (q15_t)0x680f, (q15_t)0x680b, (q15_t)0x6808, (q15_t)0x6804, (q15_t)0x6800, (q15_t)0x67fd, (q15_t)0x67f9,
+  (q15_t)0x67f5, (q15_t)0x67f2, (q15_t)0x67ee, (q15_t)0x67ea, (q15_t)0x67e7, (q15_t)0x67e3, (q15_t)0x67df, (q15_t)0x67dc,
+  (q15_t)0x67d8, (q15_t)0x67d4, (q15_t)0x67d1, (q15_t)0x67cd, (q15_t)0x67c9, (q15_t)0x67c6, (q15_t)0x67c2, (q15_t)0x67be,
+  (q15_t)0x67bb, (q15_t)0x67b7, (q15_t)0x67b3, (q15_t)0x67b0, (q15_t)0x67ac, (q15_t)0x67a8, (q15_t)0x67a5, (q15_t)0x67a1,
+  (q15_t)0x679d, (q15_t)0x679a, (q15_t)0x6796, (q15_t)0x6792, (q15_t)0x678e, (q15_t)0x678b, (q15_t)0x6787, (q15_t)0x6783,
+  (q15_t)0x6780, (q15_t)0x677c, (q15_t)0x6778, (q15_t)0x6775, (q15_t)0x6771, (q15_t)0x676d, (q15_t)0x6769, (q15_t)0x6766,
+  (q15_t)0x6762, (q15_t)0x675e, (q15_t)0x675b, (q15_t)0x6757, (q15_t)0x6753, (q15_t)0x6750, (q15_t)0x674c, (q15_t)0x6748,
+  (q15_t)0x6744, (q15_t)0x6741, (q15_t)0x673d, (q15_t)0x6739, (q15_t)0x6736, (q15_t)0x6732, (q15_t)0x672e, (q15_t)0x672a,
+  (q15_t)0x6727, (q15_t)0x6723, (q15_t)0x671f, (q15_t)0x671c, (q15_t)0x6718, (q15_t)0x6714, (q15_t)0x6710, (q15_t)0x670d,
+  (q15_t)0x6709, (q15_t)0x6705, (q15_t)0x6701, (q15_t)0x66fe, (q15_t)0x66fa, (q15_t)0x66f6, (q15_t)0x66f3, (q15_t)0x66ef,
+  (q15_t)0x66eb, (q15_t)0x66e7, (q15_t)0x66e4, (q15_t)0x66e0, (q15_t)0x66dc, (q15_t)0x66d8, (q15_t)0x66d5, (q15_t)0x66d1,
+  (q15_t)0x66cd, (q15_t)0x66c9, (q15_t)0x66c6, (q15_t)0x66c2, (q15_t)0x66be, (q15_t)0x66ba, (q15_t)0x66b7, (q15_t)0x66b3,
+  (q15_t)0x66af, (q15_t)0x66ab, (q15_t)0x66a8, (q15_t)0x66a4, (q15_t)0x66a0, (q15_t)0x669c, (q15_t)0x6699, (q15_t)0x6695,
+  (q15_t)0x6691, (q15_t)0x668d, (q15_t)0x668a, (q15_t)0x6686, (q15_t)0x6682, (q15_t)0x667e, (q15_t)0x667b, (q15_t)0x6677,
+  (q15_t)0x6673, (q15_t)0x666f, (q15_t)0x666b, (q15_t)0x6668, (q15_t)0x6664, (q15_t)0x6660, (q15_t)0x665c, (q15_t)0x6659,
+  (q15_t)0x6655, (q15_t)0x6651, (q15_t)0x664d, (q15_t)0x664a, (q15_t)0x6646, (q15_t)0x6642, (q15_t)0x663e, (q15_t)0x663a,
+  (q15_t)0x6637, (q15_t)0x6633, (q15_t)0x662f, (q15_t)0x662b, (q15_t)0x6627, (q15_t)0x6624, (q15_t)0x6620, (q15_t)0x661c,
+  (q15_t)0x6618, (q15_t)0x6615, (q15_t)0x6611, (q15_t)0x660d, (q15_t)0x6609, (q15_t)0x6605, (q15_t)0x6602, (q15_t)0x65fe,
+  (q15_t)0x65fa, (q15_t)0x65f6, (q15_t)0x65f2, (q15_t)0x65ef, (q15_t)0x65eb, (q15_t)0x65e7, (q15_t)0x65e3, (q15_t)0x65df,
+  (q15_t)0x65dc, (q15_t)0x65d8, (q15_t)0x65d4, (q15_t)0x65d0, (q15_t)0x65cc, (q15_t)0x65c9, (q15_t)0x65c5, (q15_t)0x65c1,
+  (q15_t)0x65bd, (q15_t)0x65b9, (q15_t)0x65b5, (q15_t)0x65b2, (q15_t)0x65ae, (q15_t)0x65aa, (q15_t)0x65a6, (q15_t)0x65a2,
+  (q15_t)0x659f, (q15_t)0x659b, (q15_t)0x6597, (q15_t)0x6593, (q15_t)0x658f, (q15_t)0x658b, (q15_t)0x6588, (q15_t)0x6584,
+  (q15_t)0x6580, (q15_t)0x657c, (q15_t)0x6578, (q15_t)0x6574, (q15_t)0x6571, (q15_t)0x656d, (q15_t)0x6569, (q15_t)0x6565,
+  (q15_t)0x6561, (q15_t)0x655d, (q15_t)0x655a, (q15_t)0x6556, (q15_t)0x6552, (q15_t)0x654e, (q15_t)0x654a, (q15_t)0x6546,
+  (q15_t)0x6543, (q15_t)0x653f, (q15_t)0x653b, (q15_t)0x6537, (q15_t)0x6533, (q15_t)0x652f, (q15_t)0x652c, (q15_t)0x6528,
+  (q15_t)0x6524, (q15_t)0x6520, (q15_t)0x651c, (q15_t)0x6518, (q15_t)0x6514, (q15_t)0x6511, (q15_t)0x650d, (q15_t)0x6509,
+  (q15_t)0x6505, (q15_t)0x6501, (q15_t)0x64fd, (q15_t)0x64f9, (q15_t)0x64f6, (q15_t)0x64f2, (q15_t)0x64ee, (q15_t)0x64ea,
+  (q15_t)0x64e6, (q15_t)0x64e2, (q15_t)0x64de, (q15_t)0x64db, (q15_t)0x64d7, (q15_t)0x64d3, (q15_t)0x64cf, (q15_t)0x64cb,
+  (q15_t)0x64c7, (q15_t)0x64c3, (q15_t)0x64bf, (q15_t)0x64bc, (q15_t)0x64b8, (q15_t)0x64b4, (q15_t)0x64b0, (q15_t)0x64ac,
+  (q15_t)0x64a8, (q15_t)0x64a4, (q15_t)0x64a0, (q15_t)0x649c, (q15_t)0x6499, (q15_t)0x6495, (q15_t)0x6491, (q15_t)0x648d,
+  (q15_t)0x6489, (q15_t)0x6485, (q15_t)0x6481, (q15_t)0x647d, (q15_t)0x6479, (q15_t)0x6476, (q15_t)0x6472, (q15_t)0x646e,
+  (q15_t)0x646a, (q15_t)0x6466, (q15_t)0x6462, (q15_t)0x645e, (q15_t)0x645a, (q15_t)0x6456, (q15_t)0x6453, (q15_t)0x644f,
+  (q15_t)0x644b, (q15_t)0x6447, (q15_t)0x6443, (q15_t)0x643f, (q15_t)0x643b, (q15_t)0x6437, (q15_t)0x6433, (q15_t)0x642f,
+  (q15_t)0x642b, (q15_t)0x6428, (q15_t)0x6424, (q15_t)0x6420, (q15_t)0x641c, (q15_t)0x6418, (q15_t)0x6414, (q15_t)0x6410,
+  (q15_t)0x640c, (q15_t)0x6408, (q15_t)0x6404, (q15_t)0x6400, (q15_t)0x63fc, (q15_t)0x63f9, (q15_t)0x63f5, (q15_t)0x63f1,
+  (q15_t)0x63ed, (q15_t)0x63e9, (q15_t)0x63e5, (q15_t)0x63e1, (q15_t)0x63dd, (q15_t)0x63d9, (q15_t)0x63d5, (q15_t)0x63d1,
+  (q15_t)0x63cd, (q15_t)0x63c9, (q15_t)0x63c5, (q15_t)0x63c1, (q15_t)0x63be, (q15_t)0x63ba, (q15_t)0x63b6, (q15_t)0x63b2,
+  (q15_t)0x63ae, (q15_t)0x63aa, (q15_t)0x63a6, (q15_t)0x63a2, (q15_t)0x639e, (q15_t)0x639a, (q15_t)0x6396, (q15_t)0x6392,
+  (q15_t)0x638e, (q15_t)0x638a, (q15_t)0x6386, (q15_t)0x6382, (q15_t)0x637e, (q15_t)0x637a, (q15_t)0x6377, (q15_t)0x6373,
+  (q15_t)0x636f, (q15_t)0x636b, (q15_t)0x6367, (q15_t)0x6363, (q15_t)0x635f, (q15_t)0x635b, (q15_t)0x6357, (q15_t)0x6353,
+  (q15_t)0x634f, (q15_t)0x634b, (q15_t)0x6347, (q15_t)0x6343, (q15_t)0x633f, (q15_t)0x633b, (q15_t)0x6337, (q15_t)0x6333,
+  (q15_t)0x632f, (q15_t)0x632b, (q15_t)0x6327, (q15_t)0x6323, (q15_t)0x631f, (q15_t)0x631b, (q15_t)0x6317, (q15_t)0x6313,
+  (q15_t)0x630f, (q15_t)0x630b, (q15_t)0x6307, (q15_t)0x6303, (q15_t)0x62ff, (q15_t)0x62fb, (q15_t)0x62f7, (q15_t)0x62f3,
+  (q15_t)0x62f0, (q15_t)0x62ec, (q15_t)0x62e8, (q15_t)0x62e4, (q15_t)0x62e0, (q15_t)0x62dc, (q15_t)0x62d8, (q15_t)0x62d4,
+  (q15_t)0x62d0, (q15_t)0x62cc, (q15_t)0x62c8, (q15_t)0x62c4, (q15_t)0x62c0, (q15_t)0x62bc, (q15_t)0x62b8, (q15_t)0x62b4,
+  (q15_t)0x62b0, (q15_t)0x62ac, (q15_t)0x62a8, (q15_t)0x62a4, (q15_t)0x62a0, (q15_t)0x629c, (q15_t)0x6298, (q15_t)0x6294,
+  (q15_t)0x6290, (q15_t)0x628c, (q15_t)0x6288, (q15_t)0x6284, (q15_t)0x6280, (q15_t)0x627c, (q15_t)0x6278, (q15_t)0x6273,
+  (q15_t)0x626f, (q15_t)0x626b, (q15_t)0x6267, (q15_t)0x6263, (q15_t)0x625f, (q15_t)0x625b, (q15_t)0x6257, (q15_t)0x6253,
+  (q15_t)0x624f, (q15_t)0x624b, (q15_t)0x6247, (q15_t)0x6243, (q15_t)0x623f, (q15_t)0x623b, (q15_t)0x6237, (q15_t)0x6233,
+  (q15_t)0x622f, (q15_t)0x622b, (q15_t)0x6227, (q15_t)0x6223, (q15_t)0x621f, (q15_t)0x621b, (q15_t)0x6217, (q15_t)0x6213,
+  (q15_t)0x620f, (q15_t)0x620b, (q15_t)0x6207, (q15_t)0x6203, (q15_t)0x61ff, (q15_t)0x61fb, (q15_t)0x61f7, (q15_t)0x61f3,
+  (q15_t)0x61ee, (q15_t)0x61ea, (q15_t)0x61e6, (q15_t)0x61e2, (q15_t)0x61de, (q15_t)0x61da, (q15_t)0x61d6, (q15_t)0x61d2,
+  (q15_t)0x61ce, (q15_t)0x61ca, (q15_t)0x61c6, (q15_t)0x61c2, (q15_t)0x61be, (q15_t)0x61ba, (q15_t)0x61b6, (q15_t)0x61b2,
+  (q15_t)0x61ae, (q15_t)0x61aa, (q15_t)0x61a6, (q15_t)0x61a1, (q15_t)0x619d, (q15_t)0x6199, (q15_t)0x6195, (q15_t)0x6191,
+  (q15_t)0x618d, (q15_t)0x6189, (q15_t)0x6185, (q15_t)0x6181, (q15_t)0x617d, (q15_t)0x6179, (q15_t)0x6175, (q15_t)0x6171,
+  (q15_t)0x616d, (q15_t)0x6168, (q15_t)0x6164, (q15_t)0x6160, (q15_t)0x615c, (q15_t)0x6158, (q15_t)0x6154, (q15_t)0x6150,
+  (q15_t)0x614c, (q15_t)0x6148, (q15_t)0x6144, (q15_t)0x6140, (q15_t)0x613c, (q15_t)0x6137, (q15_t)0x6133, (q15_t)0x612f,
+  (q15_t)0x612b, (q15_t)0x6127, (q15_t)0x6123, (q15_t)0x611f, (q15_t)0x611b, (q15_t)0x6117, (q15_t)0x6113, (q15_t)0x610f,
+  (q15_t)0x610a, (q15_t)0x6106, (q15_t)0x6102, (q15_t)0x60fe, (q15_t)0x60fa, (q15_t)0x60f6, (q15_t)0x60f2, (q15_t)0x60ee,
+  (q15_t)0x60ea, (q15_t)0x60e6, (q15_t)0x60e1, (q15_t)0x60dd, (q15_t)0x60d9, (q15_t)0x60d5, (q15_t)0x60d1, (q15_t)0x60cd,
+  (q15_t)0x60c9, (q15_t)0x60c5, (q15_t)0x60c1, (q15_t)0x60bc, (q15_t)0x60b8, (q15_t)0x60b4, (q15_t)0x60b0, (q15_t)0x60ac,
+  (q15_t)0x60a8, (q15_t)0x60a4, (q15_t)0x60a0, (q15_t)0x609c, (q15_t)0x6097, (q15_t)0x6093, (q15_t)0x608f, (q15_t)0x608b,
+  (q15_t)0x6087, (q15_t)0x6083, (q15_t)0x607f, (q15_t)0x607b, (q15_t)0x6076, (q15_t)0x6072, (q15_t)0x606e, (q15_t)0x606a,
+  (q15_t)0x6066, (q15_t)0x6062, (q15_t)0x605e, (q15_t)0x6059, (q15_t)0x6055, (q15_t)0x6051, (q15_t)0x604d, (q15_t)0x6049,
+  (q15_t)0x6045, (q15_t)0x6041, (q15_t)0x603c, (q15_t)0x6038, (q15_t)0x6034, (q15_t)0x6030, (q15_t)0x602c, (q15_t)0x6028,
+  (q15_t)0x6024, (q15_t)0x601f, (q15_t)0x601b, (q15_t)0x6017, (q15_t)0x6013, (q15_t)0x600f, (q15_t)0x600b, (q15_t)0x6007,
+  (q15_t)0x6002, (q15_t)0x5ffe, (q15_t)0x5ffa, (q15_t)0x5ff6, (q15_t)0x5ff2, (q15_t)0x5fee, (q15_t)0x5fe9, (q15_t)0x5fe5,
+  (q15_t)0x5fe1, (q15_t)0x5fdd, (q15_t)0x5fd9, (q15_t)0x5fd5, (q15_t)0x5fd0, (q15_t)0x5fcc, (q15_t)0x5fc8, (q15_t)0x5fc4,
+  (q15_t)0x5fc0, (q15_t)0x5fbc, (q15_t)0x5fb7, (q15_t)0x5fb3, (q15_t)0x5faf, (q15_t)0x5fab, (q15_t)0x5fa7, (q15_t)0x5fa3,
+  (q15_t)0x5f9e, (q15_t)0x5f9a, (q15_t)0x5f96, (q15_t)0x5f92, (q15_t)0x5f8e, (q15_t)0x5f8a, (q15_t)0x5f85, (q15_t)0x5f81,
+  (q15_t)0x5f7d, (q15_t)0x5f79, (q15_t)0x5f75, (q15_t)0x5f70, (q15_t)0x5f6c, (q15_t)0x5f68, (q15_t)0x5f64, (q15_t)0x5f60,
+  (q15_t)0x5f5b, (q15_t)0x5f57, (q15_t)0x5f53, (q15_t)0x5f4f, (q15_t)0x5f4b, (q15_t)0x5f46, (q15_t)0x5f42, (q15_t)0x5f3e,
+  (q15_t)0x5f3a, (q15_t)0x5f36, (q15_t)0x5f31, (q15_t)0x5f2d, (q15_t)0x5f29, (q15_t)0x5f25, (q15_t)0x5f21, (q15_t)0x5f1c,
+  (q15_t)0x5f18, (q15_t)0x5f14, (q15_t)0x5f10, (q15_t)0x5f0c, (q15_t)0x5f07, (q15_t)0x5f03, (q15_t)0x5eff, (q15_t)0x5efb,
+  (q15_t)0x5ef7, (q15_t)0x5ef2, (q15_t)0x5eee, (q15_t)0x5eea, (q15_t)0x5ee6, (q15_t)0x5ee2, (q15_t)0x5edd, (q15_t)0x5ed9,
+  (q15_t)0x5ed5, (q15_t)0x5ed1, (q15_t)0x5ecc, (q15_t)0x5ec8, (q15_t)0x5ec4, (q15_t)0x5ec0, (q15_t)0x5ebc, (q15_t)0x5eb7,
+  (q15_t)0x5eb3, (q15_t)0x5eaf, (q15_t)0x5eab, (q15_t)0x5ea6, (q15_t)0x5ea2, (q15_t)0x5e9e, (q15_t)0x5e9a, (q15_t)0x5e95,
+  (q15_t)0x5e91, (q15_t)0x5e8d, (q15_t)0x5e89, (q15_t)0x5e85, (q15_t)0x5e80, (q15_t)0x5e7c, (q15_t)0x5e78, (q15_t)0x5e74,
+  (q15_t)0x5e6f, (q15_t)0x5e6b, (q15_t)0x5e67, (q15_t)0x5e63, (q15_t)0x5e5e, (q15_t)0x5e5a, (q15_t)0x5e56, (q15_t)0x5e52,
+  (q15_t)0x5e4d, (q15_t)0x5e49, (q15_t)0x5e45, (q15_t)0x5e41, (q15_t)0x5e3c, (q15_t)0x5e38, (q15_t)0x5e34, (q15_t)0x5e30,
+  (q15_t)0x5e2b, (q15_t)0x5e27, (q15_t)0x5e23, (q15_t)0x5e1f, (q15_t)0x5e1a, (q15_t)0x5e16, (q15_t)0x5e12, (q15_t)0x5e0e,
+  (q15_t)0x5e09, (q15_t)0x5e05, (q15_t)0x5e01, (q15_t)0x5dfd, (q15_t)0x5df8, (q15_t)0x5df4, (q15_t)0x5df0, (q15_t)0x5deb,
+  (q15_t)0x5de7, (q15_t)0x5de3, (q15_t)0x5ddf, (q15_t)0x5dda, (q15_t)0x5dd6, (q15_t)0x5dd2, (q15_t)0x5dce, (q15_t)0x5dc9,
+  (q15_t)0x5dc5, (q15_t)0x5dc1, (q15_t)0x5dbc, (q15_t)0x5db8, (q15_t)0x5db4, (q15_t)0x5db0, (q15_t)0x5dab, (q15_t)0x5da7,
+  (q15_t)0x5da3, (q15_t)0x5d9e, (q15_t)0x5d9a, (q15_t)0x5d96, (q15_t)0x5d92, (q15_t)0x5d8d, (q15_t)0x5d89, (q15_t)0x5d85,
+  (q15_t)0x5d80, (q15_t)0x5d7c, (q15_t)0x5d78, (q15_t)0x5d74, (q15_t)0x5d6f, (q15_t)0x5d6b, (q15_t)0x5d67, (q15_t)0x5d62,
+  (q15_t)0x5d5e, (q15_t)0x5d5a, (q15_t)0x5d55, (q15_t)0x5d51, (q15_t)0x5d4d, (q15_t)0x5d49, (q15_t)0x5d44, (q15_t)0x5d40,
+  (q15_t)0x5d3c, (q15_t)0x5d37, (q15_t)0x5d33, (q15_t)0x5d2f, (q15_t)0x5d2a, (q15_t)0x5d26, (q15_t)0x5d22, (q15_t)0x5d1e,
+  (q15_t)0x5d19, (q15_t)0x5d15, (q15_t)0x5d11, (q15_t)0x5d0c, (q15_t)0x5d08, (q15_t)0x5d04, (q15_t)0x5cff, (q15_t)0x5cfb,
+  (q15_t)0x5cf7, (q15_t)0x5cf2, (q15_t)0x5cee, (q15_t)0x5cea, (q15_t)0x5ce5, (q15_t)0x5ce1, (q15_t)0x5cdd, (q15_t)0x5cd8,
+  (q15_t)0x5cd4, (q15_t)0x5cd0, (q15_t)0x5ccb, (q15_t)0x5cc7, (q15_t)0x5cc3, (q15_t)0x5cbe, (q15_t)0x5cba, (q15_t)0x5cb6,
+  (q15_t)0x5cb1, (q15_t)0x5cad, (q15_t)0x5ca9, (q15_t)0x5ca4, (q15_t)0x5ca0, (q15_t)0x5c9c, (q15_t)0x5c97, (q15_t)0x5c93,
+  (q15_t)0x5c8f, (q15_t)0x5c8a, (q15_t)0x5c86, (q15_t)0x5c82, (q15_t)0x5c7d, (q15_t)0x5c79, (q15_t)0x5c75, (q15_t)0x5c70,
+  (q15_t)0x5c6c, (q15_t)0x5c68, (q15_t)0x5c63, (q15_t)0x5c5f, (q15_t)0x5c5b, (q15_t)0x5c56, (q15_t)0x5c52, (q15_t)0x5c4e,
+  (q15_t)0x5c49, (q15_t)0x5c45, (q15_t)0x5c41, (q15_t)0x5c3c, (q15_t)0x5c38, (q15_t)0x5c33, (q15_t)0x5c2f, (q15_t)0x5c2b,
+  (q15_t)0x5c26, (q15_t)0x5c22, (q15_t)0x5c1e, (q15_t)0x5c19, (q15_t)0x5c15, (q15_t)0x5c11, (q15_t)0x5c0c, (q15_t)0x5c08,
+  (q15_t)0x5c03, (q15_t)0x5bff, (q15_t)0x5bfb, (q15_t)0x5bf6, (q15_t)0x5bf2, (q15_t)0x5bee, (q15_t)0x5be9, (q15_t)0x5be5,
+  (q15_t)0x5be0, (q15_t)0x5bdc, (q15_t)0x5bd8, (q15_t)0x5bd3, (q15_t)0x5bcf, (q15_t)0x5bcb, (q15_t)0x5bc6, (q15_t)0x5bc2,
+  (q15_t)0x5bbd, (q15_t)0x5bb9, (q15_t)0x5bb5, (q15_t)0x5bb0, (q15_t)0x5bac, (q15_t)0x5ba8, (q15_t)0x5ba3, (q15_t)0x5b9f,
+  (q15_t)0x5b9a, (q15_t)0x5b96, (q15_t)0x5b92, (q15_t)0x5b8d, (q15_t)0x5b89, (q15_t)0x5b84, (q15_t)0x5b80, (q15_t)0x5b7c,
+  (q15_t)0x5b77, (q15_t)0x5b73, (q15_t)0x5b6e, (q15_t)0x5b6a, (q15_t)0x5b66, (q15_t)0x5b61, (q15_t)0x5b5d, (q15_t)0x5b58,
+  (q15_t)0x5b54, (q15_t)0x5b50, (q15_t)0x5b4b, (q15_t)0x5b47, (q15_t)0x5b42, (q15_t)0x5b3e, (q15_t)0x5b3a, (q15_t)0x5b35,
+  (q15_t)0x5b31, (q15_t)0x5b2c, (q15_t)0x5b28, (q15_t)0x5b24, (q15_t)0x5b1f, (q15_t)0x5b1b, (q15_t)0x5b16, (q15_t)0x5b12,
+  (q15_t)0x5b0e, (q15_t)0x5b09, (q15_t)0x5b05, (q15_t)0x5b00, (q15_t)0x5afc, (q15_t)0x5af7, (q15_t)0x5af3, (q15_t)0x5aef,
+  (q15_t)0x5aea, (q15_t)0x5ae6, (q15_t)0x5ae1, (q15_t)0x5add, (q15_t)0x5ad8, (q15_t)0x5ad4, (q15_t)0x5ad0, (q15_t)0x5acb,
+  (q15_t)0x5ac7, (q15_t)0x5ac2, (q15_t)0x5abe, (q15_t)0x5ab9, (q15_t)0x5ab5, (q15_t)0x5ab1, (q15_t)0x5aac, (q15_t)0x5aa8,
+  (q15_t)0x5aa3, (q15_t)0x5a9f, (q15_t)0x5a9a, (q15_t)0x5a96, (q15_t)0x5a92, (q15_t)0x5a8d, (q15_t)0x5a89, (q15_t)0x5a84,
+  (q15_t)0x5a80, (q15_t)0x5a7b, (q15_t)0x5a77, (q15_t)0x5a72, (q15_t)0x5a6e, (q15_t)0x5a6a, (q15_t)0x5a65, (q15_t)0x5a61,
+  (q15_t)0x5a5c, (q15_t)0x5a58, (q15_t)0x5a53, (q15_t)0x5a4f, (q15_t)0x5a4a, (q15_t)0x5a46, (q15_t)0x5a41, (q15_t)0x5a3d,
+  (q15_t)0x5a39, (q15_t)0x5a34, (q15_t)0x5a30, (q15_t)0x5a2b, (q15_t)0x5a27, (q15_t)0x5a22, (q15_t)0x5a1e, (q15_t)0x5a19,
+  (q15_t)0x5a15, (q15_t)0x5a10, (q15_t)0x5a0c, (q15_t)0x5a07, (q15_t)0x5a03, (q15_t)0x59ff, (q15_t)0x59fa, (q15_t)0x59f6,
+  (q15_t)0x59f1, (q15_t)0x59ed, (q15_t)0x59e8, (q15_t)0x59e4, (q15_t)0x59df, (q15_t)0x59db, (q15_t)0x59d6, (q15_t)0x59d2,
+  (q15_t)0x59cd, (q15_t)0x59c9, (q15_t)0x59c4, (q15_t)0x59c0, (q15_t)0x59bb, (q15_t)0x59b7, (q15_t)0x59b2, (q15_t)0x59ae,
+  (q15_t)0x59a9, (q15_t)0x59a5, (q15_t)0x59a1, (q15_t)0x599c, (q15_t)0x5998, (q15_t)0x5993, (q15_t)0x598f, (q15_t)0x598a,
+  (q15_t)0x5986, (q15_t)0x5981, (q15_t)0x597d, (q15_t)0x5978, (q15_t)0x5974, (q15_t)0x596f, (q15_t)0x596b, (q15_t)0x5966,
+  (q15_t)0x5962, (q15_t)0x595d, (q15_t)0x5959, (q15_t)0x5954, (q15_t)0x5950, (q15_t)0x594b, (q15_t)0x5947, (q15_t)0x5942,
+  (q15_t)0x593e, (q15_t)0x5939, (q15_t)0x5935, (q15_t)0x5930, (q15_t)0x592c, (q15_t)0x5927, (q15_t)0x5923, (q15_t)0x591e,
+  (q15_t)0x591a, (q15_t)0x5915, (q15_t)0x5911, (q15_t)0x590c, (q15_t)0x5908, (q15_t)0x5903, (q15_t)0x58fe, (q15_t)0x58fa,
+  (q15_t)0x58f5, (q15_t)0x58f1, (q15_t)0x58ec, (q15_t)0x58e8, (q15_t)0x58e3, (q15_t)0x58df, (q15_t)0x58da, (q15_t)0x58d6,
+  (q15_t)0x58d1, (q15_t)0x58cd, (q15_t)0x58c8, (q15_t)0x58c4, (q15_t)0x58bf, (q15_t)0x58bb, (q15_t)0x58b6, (q15_t)0x58b2,
+  (q15_t)0x58ad, (q15_t)0x58a9, (q15_t)0x58a4, (q15_t)0x589f, (q15_t)0x589b, (q15_t)0x5896, (q15_t)0x5892, (q15_t)0x588d,
+  (q15_t)0x5889, (q15_t)0x5884, (q15_t)0x5880, (q15_t)0x587b, (q15_t)0x5877, (q15_t)0x5872, (q15_t)0x586e, (q15_t)0x5869,
+  (q15_t)0x5864, (q15_t)0x5860, (q15_t)0x585b, (q15_t)0x5857, (q15_t)0x5852, (q15_t)0x584e, (q15_t)0x5849, (q15_t)0x5845,
+  (q15_t)0x5840, (q15_t)0x583c, (q15_t)0x5837, (q15_t)0x5832, (q15_t)0x582e, (q15_t)0x5829, (q15_t)0x5825, (q15_t)0x5820,
+  (q15_t)0x581c, (q15_t)0x5817, (q15_t)0x5813, (q15_t)0x580e, (q15_t)0x5809, (q15_t)0x5805, (q15_t)0x5800, (q15_t)0x57fc,
+  (q15_t)0x57f7, (q15_t)0x57f3, (q15_t)0x57ee, (q15_t)0x57e9, (q15_t)0x57e5, (q15_t)0x57e0, (q15_t)0x57dc, (q15_t)0x57d7,
+  (q15_t)0x57d3, (q15_t)0x57ce, (q15_t)0x57c9, (q15_t)0x57c5, (q15_t)0x57c0, (q15_t)0x57bc, (q15_t)0x57b7, (q15_t)0x57b3,
+  (q15_t)0x57ae, (q15_t)0x57a9, (q15_t)0x57a5, (q15_t)0x57a0, (q15_t)0x579c, (q15_t)0x5797, (q15_t)0x5793, (q15_t)0x578e,
+  (q15_t)0x5789, (q15_t)0x5785, (q15_t)0x5780, (q15_t)0x577c, (q15_t)0x5777, (q15_t)0x5772, (q15_t)0x576e, (q15_t)0x5769,
+  (q15_t)0x5765, (q15_t)0x5760, (q15_t)0x575c, (q15_t)0x5757, (q15_t)0x5752, (q15_t)0x574e, (q15_t)0x5749, (q15_t)0x5745,
+  (q15_t)0x5740, (q15_t)0x573b, (q15_t)0x5737, (q15_t)0x5732, (q15_t)0x572e, (q15_t)0x5729, (q15_t)0x5724, (q15_t)0x5720,
+  (q15_t)0x571b, (q15_t)0x5717, (q15_t)0x5712, (q15_t)0x570d, (q15_t)0x5709, (q15_t)0x5704, (q15_t)0x56ff, (q15_t)0x56fb,
+  (q15_t)0x56f6, (q15_t)0x56f2, (q15_t)0x56ed, (q15_t)0x56e8, (q15_t)0x56e4, (q15_t)0x56df, (q15_t)0x56db, (q15_t)0x56d6,
+  (q15_t)0x56d1, (q15_t)0x56cd, (q15_t)0x56c8, (q15_t)0x56c4, (q15_t)0x56bf, (q15_t)0x56ba, (q15_t)0x56b6, (q15_t)0x56b1,
+  (q15_t)0x56ac, (q15_t)0x56a8, (q15_t)0x56a3, (q15_t)0x569f, (q15_t)0x569a, (q15_t)0x5695, (q15_t)0x5691, (q15_t)0x568c,
+  (q15_t)0x5687, (q15_t)0x5683, (q15_t)0x567e, (q15_t)0x5679, (q15_t)0x5675, (q15_t)0x5670, (q15_t)0x566c, (q15_t)0x5667,
+  (q15_t)0x5662, (q15_t)0x565e, (q15_t)0x5659, (q15_t)0x5654, (q15_t)0x5650, (q15_t)0x564b, (q15_t)0x5646, (q15_t)0x5642,
+  (q15_t)0x563d, (q15_t)0x5639, (q15_t)0x5634, (q15_t)0x562f, (q15_t)0x562b, (q15_t)0x5626, (q15_t)0x5621, (q15_t)0x561d,
+  (q15_t)0x5618, (q15_t)0x5613, (q15_t)0x560f, (q15_t)0x560a, (q15_t)0x5605, (q15_t)0x5601, (q15_t)0x55fc, (q15_t)0x55f7,
+  (q15_t)0x55f3, (q15_t)0x55ee, (q15_t)0x55ea, (q15_t)0x55e5, (q15_t)0x55e0, (q15_t)0x55dc, (q15_t)0x55d7, (q15_t)0x55d2,
+  (q15_t)0x55ce, (q15_t)0x55c9, (q15_t)0x55c4, (q15_t)0x55c0, (q15_t)0x55bb, (q15_t)0x55b6, (q15_t)0x55b2, (q15_t)0x55ad,
+  (q15_t)0x55a8, (q15_t)0x55a4, (q15_t)0x559f, (q15_t)0x559a, (q15_t)0x5596, (q15_t)0x5591, (q15_t)0x558c, (q15_t)0x5588,
+  (q15_t)0x5583, (q15_t)0x557e, (q15_t)0x5579, (q15_t)0x5575, (q15_t)0x5570, (q15_t)0x556b, (q15_t)0x5567, (q15_t)0x5562,
+  (q15_t)0x555d, (q15_t)0x5559, (q15_t)0x5554, (q15_t)0x554f, (q15_t)0x554b, (q15_t)0x5546, (q15_t)0x5541, (q15_t)0x553d,
+  (q15_t)0x5538, (q15_t)0x5533, (q15_t)0x552f, (q15_t)0x552a, (q15_t)0x5525, (q15_t)0x5520, (q15_t)0x551c, (q15_t)0x5517,
+  (q15_t)0x5512, (q15_t)0x550e, (q15_t)0x5509, (q15_t)0x5504, (q15_t)0x5500, (q15_t)0x54fb, (q15_t)0x54f6, (q15_t)0x54f2,
+  (q15_t)0x54ed, (q15_t)0x54e8, (q15_t)0x54e3, (q15_t)0x54df, (q15_t)0x54da, (q15_t)0x54d5, (q15_t)0x54d1, (q15_t)0x54cc,
+  (q15_t)0x54c7, (q15_t)0x54c2, (q15_t)0x54be, (q15_t)0x54b9, (q15_t)0x54b4, (q15_t)0x54b0, (q15_t)0x54ab, (q15_t)0x54a6,
+  (q15_t)0x54a2, (q15_t)0x549d, (q15_t)0x5498, (q15_t)0x5493, (q15_t)0x548f, (q15_t)0x548a, (q15_t)0x5485, (q15_t)0x5480,
+  (q15_t)0x547c, (q15_t)0x5477, (q15_t)0x5472, (q15_t)0x546e, (q15_t)0x5469, (q15_t)0x5464, (q15_t)0x545f, (q15_t)0x545b,
+  (q15_t)0x5456, (q15_t)0x5451, (q15_t)0x544d, (q15_t)0x5448, (q15_t)0x5443, (q15_t)0x543e, (q15_t)0x543a, (q15_t)0x5435,
+  (q15_t)0x5430, (q15_t)0x542b, (q15_t)0x5427, (q15_t)0x5422, (q15_t)0x541d, (q15_t)0x5418, (q15_t)0x5414, (q15_t)0x540f,
+  (q15_t)0x540a, (q15_t)0x5406, (q15_t)0x5401, (q15_t)0x53fc, (q15_t)0x53f7, (q15_t)0x53f3, (q15_t)0x53ee, (q15_t)0x53e9,
+  (q15_t)0x53e4, (q15_t)0x53e0, (q15_t)0x53db, (q15_t)0x53d6, (q15_t)0x53d1, (q15_t)0x53cd, (q15_t)0x53c8, (q15_t)0x53c3,
+  (q15_t)0x53be, (q15_t)0x53ba, (q15_t)0x53b5, (q15_t)0x53b0, (q15_t)0x53ab, (q15_t)0x53a7, (q15_t)0x53a2, (q15_t)0x539d,
+  (q15_t)0x5398, (q15_t)0x5394, (q15_t)0x538f, (q15_t)0x538a, (q15_t)0x5385, (q15_t)0x5380, (q15_t)0x537c, (q15_t)0x5377,
+  (q15_t)0x5372, (q15_t)0x536d, (q15_t)0x5369, (q15_t)0x5364, (q15_t)0x535f, (q15_t)0x535a, (q15_t)0x5356, (q15_t)0x5351,
+  (q15_t)0x534c, (q15_t)0x5347, (q15_t)0x5343, (q15_t)0x533e, (q15_t)0x5339, (q15_t)0x5334, (q15_t)0x532f, (q15_t)0x532b,
+  (q15_t)0x5326, (q15_t)0x5321, (q15_t)0x531c, (q15_t)0x5318, (q15_t)0x5313, (q15_t)0x530e, (q15_t)0x5309, (q15_t)0x5304,
+  (q15_t)0x5300, (q15_t)0x52fb, (q15_t)0x52f6, (q15_t)0x52f1, (q15_t)0x52ec, (q15_t)0x52e8, (q15_t)0x52e3, (q15_t)0x52de,
+  (q15_t)0x52d9, (q15_t)0x52d5, (q15_t)0x52d0, (q15_t)0x52cb, (q15_t)0x52c6, (q15_t)0x52c1, (q15_t)0x52bd, (q15_t)0x52b8,
+  (q15_t)0x52b3, (q15_t)0x52ae, (q15_t)0x52a9, (q15_t)0x52a5, (q15_t)0x52a0, (q15_t)0x529b, (q15_t)0x5296, (q15_t)0x5291,
+  (q15_t)0x528d, (q15_t)0x5288, (q15_t)0x5283, (q15_t)0x527e, (q15_t)0x5279, (q15_t)0x5275, (q15_t)0x5270, (q15_t)0x526b,
+  (q15_t)0x5266, (q15_t)0x5261, (q15_t)0x525d, (q15_t)0x5258, (q15_t)0x5253, (q15_t)0x524e, (q15_t)0x5249, (q15_t)0x5244,
+  (q15_t)0x5240, (q15_t)0x523b, (q15_t)0x5236, (q15_t)0x5231, (q15_t)0x522c, (q15_t)0x5228, (q15_t)0x5223, (q15_t)0x521e,
+  (q15_t)0x5219, (q15_t)0x5214, (q15_t)0x520f, (q15_t)0x520b, (q15_t)0x5206, (q15_t)0x5201, (q15_t)0x51fc, (q15_t)0x51f7,
+  (q15_t)0x51f3, (q15_t)0x51ee, (q15_t)0x51e9, (q15_t)0x51e4, (q15_t)0x51df, (q15_t)0x51da, (q15_t)0x51d6, (q15_t)0x51d1,
+  (q15_t)0x51cc, (q15_t)0x51c7, (q15_t)0x51c2, (q15_t)0x51bd, (q15_t)0x51b9, (q15_t)0x51b4, (q15_t)0x51af, (q15_t)0x51aa,
+  (q15_t)0x51a5, (q15_t)0x51a0, (q15_t)0x519c, (q15_t)0x5197, (q15_t)0x5192, (q15_t)0x518d, (q15_t)0x5188, (q15_t)0x5183,
+  (q15_t)0x517e, (q15_t)0x517a, (q15_t)0x5175, (q15_t)0x5170, (q15_t)0x516b, (q15_t)0x5166, (q15_t)0x5161, (q15_t)0x515d,
+  (q15_t)0x5158, (q15_t)0x5153, (q15_t)0x514e, (q15_t)0x5149, (q15_t)0x5144, (q15_t)0x513f, (q15_t)0x513b, (q15_t)0x5136,
+  (q15_t)0x5131, (q15_t)0x512c, (q15_t)0x5127, (q15_t)0x5122, (q15_t)0x511d, (q15_t)0x5119, (q15_t)0x5114, (q15_t)0x510f,
+  (q15_t)0x510a, (q15_t)0x5105, (q15_t)0x5100, (q15_t)0x50fb, (q15_t)0x50f7, (q15_t)0x50f2, (q15_t)0x50ed, (q15_t)0x50e8,
+  (q15_t)0x50e3, (q15_t)0x50de, (q15_t)0x50d9, (q15_t)0x50d4, (q15_t)0x50d0, (q15_t)0x50cb, (q15_t)0x50c6, (q15_t)0x50c1,
+  (q15_t)0x50bc, (q15_t)0x50b7, (q15_t)0x50b2, (q15_t)0x50ad, (q15_t)0x50a9, (q15_t)0x50a4, (q15_t)0x509f, (q15_t)0x509a,
+  (q15_t)0x5095, (q15_t)0x5090, (q15_t)0x508b, (q15_t)0x5086, (q15_t)0x5082, (q15_t)0x507d, (q15_t)0x5078, (q15_t)0x5073,
+  (q15_t)0x506e, (q15_t)0x5069, (q15_t)0x5064, (q15_t)0x505f, (q15_t)0x505a, (q15_t)0x5056, (q15_t)0x5051, (q15_t)0x504c,
+  (q15_t)0x5047, (q15_t)0x5042, (q15_t)0x503d, (q15_t)0x5038, (q15_t)0x5033, (q15_t)0x502e, (q15_t)0x5029, (q15_t)0x5025,
+  (q15_t)0x5020, (q15_t)0x501b, (q15_t)0x5016, (q15_t)0x5011, (q15_t)0x500c, (q15_t)0x5007, (q15_t)0x5002, (q15_t)0x4ffd,
+  (q15_t)0x4ff8, (q15_t)0x4ff4, (q15_t)0x4fef, (q15_t)0x4fea, (q15_t)0x4fe5, (q15_t)0x4fe0, (q15_t)0x4fdb, (q15_t)0x4fd6,
+  (q15_t)0x4fd1, (q15_t)0x4fcc, (q15_t)0x4fc7, (q15_t)0x4fc2, (q15_t)0x4fbe, (q15_t)0x4fb9, (q15_t)0x4fb4, (q15_t)0x4faf,
+  (q15_t)0x4faa, (q15_t)0x4fa5, (q15_t)0x4fa0, (q15_t)0x4f9b, (q15_t)0x4f96, (q15_t)0x4f91, (q15_t)0x4f8c, (q15_t)0x4f87,
+  (q15_t)0x4f82, (q15_t)0x4f7e, (q15_t)0x4f79, (q15_t)0x4f74, (q15_t)0x4f6f, (q15_t)0x4f6a, (q15_t)0x4f65, (q15_t)0x4f60,
+  (q15_t)0x4f5b, (q15_t)0x4f56, (q15_t)0x4f51, (q15_t)0x4f4c, (q15_t)0x4f47, (q15_t)0x4f42, (q15_t)0x4f3d, (q15_t)0x4f39,
+  (q15_t)0x4f34, (q15_t)0x4f2f, (q15_t)0x4f2a, (q15_t)0x4f25, (q15_t)0x4f20, (q15_t)0x4f1b, (q15_t)0x4f16, (q15_t)0x4f11,
+  (q15_t)0x4f0c, (q15_t)0x4f07, (q15_t)0x4f02, (q15_t)0x4efd, (q15_t)0x4ef8, (q15_t)0x4ef3, (q15_t)0x4eee, (q15_t)0x4ee9,
+  (q15_t)0x4ee5, (q15_t)0x4ee0, (q15_t)0x4edb, (q15_t)0x4ed6, (q15_t)0x4ed1, (q15_t)0x4ecc, (q15_t)0x4ec7, (q15_t)0x4ec2,
+  (q15_t)0x4ebd, (q15_t)0x4eb8, (q15_t)0x4eb3, (q15_t)0x4eae, (q15_t)0x4ea9, (q15_t)0x4ea4, (q15_t)0x4e9f, (q15_t)0x4e9a,
+  (q15_t)0x4e95, (q15_t)0x4e90, (q15_t)0x4e8b, (q15_t)0x4e86, (q15_t)0x4e81, (q15_t)0x4e7c, (q15_t)0x4e78, (q15_t)0x4e73,
+  (q15_t)0x4e6e, (q15_t)0x4e69, (q15_t)0x4e64, (q15_t)0x4e5f, (q15_t)0x4e5a, (q15_t)0x4e55, (q15_t)0x4e50, (q15_t)0x4e4b,
+  (q15_t)0x4e46, (q15_t)0x4e41, (q15_t)0x4e3c, (q15_t)0x4e37, (q15_t)0x4e32, (q15_t)0x4e2d, (q15_t)0x4e28, (q15_t)0x4e23,
+  (q15_t)0x4e1e, (q15_t)0x4e19, (q15_t)0x4e14, (q15_t)0x4e0f, (q15_t)0x4e0a, (q15_t)0x4e05, (q15_t)0x4e00, (q15_t)0x4dfb,
+  (q15_t)0x4df6, (q15_t)0x4df1, (q15_t)0x4dec, (q15_t)0x4de7, (q15_t)0x4de2, (q15_t)0x4ddd, (q15_t)0x4dd8, (q15_t)0x4dd3,
+  (q15_t)0x4dce, (q15_t)0x4dc9, (q15_t)0x4dc4, (q15_t)0x4dbf, (q15_t)0x4dba, (q15_t)0x4db5, (q15_t)0x4db0, (q15_t)0x4dab,
+  (q15_t)0x4da6, (q15_t)0x4da1, (q15_t)0x4d9c, (q15_t)0x4d97, (q15_t)0x4d92, (q15_t)0x4d8d, (q15_t)0x4d88, (q15_t)0x4d83,
+  (q15_t)0x4d7e, (q15_t)0x4d79, (q15_t)0x4d74, (q15_t)0x4d6f, (q15_t)0x4d6a, (q15_t)0x4d65, (q15_t)0x4d60, (q15_t)0x4d5b,
+  (q15_t)0x4d56, (q15_t)0x4d51, (q15_t)0x4d4c, (q15_t)0x4d47, (q15_t)0x4d42, (q15_t)0x4d3d, (q15_t)0x4d38, (q15_t)0x4d33,
+  (q15_t)0x4d2e, (q15_t)0x4d29, (q15_t)0x4d24, (q15_t)0x4d1f, (q15_t)0x4d1a, (q15_t)0x4d15, (q15_t)0x4d10, (q15_t)0x4d0b,
+  (q15_t)0x4d06, (q15_t)0x4d01, (q15_t)0x4cfc, (q15_t)0x4cf7, (q15_t)0x4cf2, (q15_t)0x4ced, (q15_t)0x4ce8, (q15_t)0x4ce3,
+  (q15_t)0x4cde, (q15_t)0x4cd9, (q15_t)0x4cd4, (q15_t)0x4ccf, (q15_t)0x4cca, (q15_t)0x4cc5, (q15_t)0x4cc0, (q15_t)0x4cbb,
+  (q15_t)0x4cb6, (q15_t)0x4cb1, (q15_t)0x4cac, (q15_t)0x4ca7, (q15_t)0x4ca2, (q15_t)0x4c9d, (q15_t)0x4c98, (q15_t)0x4c93,
+  (q15_t)0x4c8e, (q15_t)0x4c88, (q15_t)0x4c83, (q15_t)0x4c7e, (q15_t)0x4c79, (q15_t)0x4c74, (q15_t)0x4c6f, (q15_t)0x4c6a,
+  (q15_t)0x4c65, (q15_t)0x4c60, (q15_t)0x4c5b, (q15_t)0x4c56, (q15_t)0x4c51, (q15_t)0x4c4c, (q15_t)0x4c47, (q15_t)0x4c42,
+  (q15_t)0x4c3d, (q15_t)0x4c38, (q15_t)0x4c33, (q15_t)0x4c2e, (q15_t)0x4c29, (q15_t)0x4c24, (q15_t)0x4c1f, (q15_t)0x4c1a,
+  (q15_t)0x4c14, (q15_t)0x4c0f, (q15_t)0x4c0a, (q15_t)0x4c05, (q15_t)0x4c00, (q15_t)0x4bfb, (q15_t)0x4bf6, (q15_t)0x4bf1,
+  (q15_t)0x4bec, (q15_t)0x4be7, (q15_t)0x4be2, (q15_t)0x4bdd, (q15_t)0x4bd8, (q15_t)0x4bd3, (q15_t)0x4bce, (q15_t)0x4bc9,
+  (q15_t)0x4bc4, (q15_t)0x4bbe, (q15_t)0x4bb9, (q15_t)0x4bb4, (q15_t)0x4baf, (q15_t)0x4baa, (q15_t)0x4ba5, (q15_t)0x4ba0,
+  (q15_t)0x4b9b, (q15_t)0x4b96, (q15_t)0x4b91, (q15_t)0x4b8c, (q15_t)0x4b87, (q15_t)0x4b82, (q15_t)0x4b7d, (q15_t)0x4b77,
+  (q15_t)0x4b72, (q15_t)0x4b6d, (q15_t)0x4b68, (q15_t)0x4b63, (q15_t)0x4b5e, (q15_t)0x4b59, (q15_t)0x4b54, (q15_t)0x4b4f,
+  (q15_t)0x4b4a, (q15_t)0x4b45, (q15_t)0x4b40, (q15_t)0x4b3b, (q15_t)0x4b35, (q15_t)0x4b30, (q15_t)0x4b2b, (q15_t)0x4b26,
+  (q15_t)0x4b21, (q15_t)0x4b1c, (q15_t)0x4b17, (q15_t)0x4b12, (q15_t)0x4b0d, (q15_t)0x4b08, (q15_t)0x4b03, (q15_t)0x4afd,
+  (q15_t)0x4af8, (q15_t)0x4af3, (q15_t)0x4aee, (q15_t)0x4ae9, (q15_t)0x4ae4, (q15_t)0x4adf, (q15_t)0x4ada, (q15_t)0x4ad5,
+  (q15_t)0x4ad0, (q15_t)0x4acb, (q15_t)0x4ac5, (q15_t)0x4ac0, (q15_t)0x4abb, (q15_t)0x4ab6, (q15_t)0x4ab1, (q15_t)0x4aac,
+  (q15_t)0x4aa7, (q15_t)0x4aa2, (q15_t)0x4a9d, (q15_t)0x4a97, (q15_t)0x4a92, (q15_t)0x4a8d, (q15_t)0x4a88, (q15_t)0x4a83,
+  (q15_t)0x4a7e, (q15_t)0x4a79, (q15_t)0x4a74, (q15_t)0x4a6f, (q15_t)0x4a6a, (q15_t)0x4a64, (q15_t)0x4a5f, (q15_t)0x4a5a,
+  (q15_t)0x4a55, (q15_t)0x4a50, (q15_t)0x4a4b, (q15_t)0x4a46, (q15_t)0x4a41, (q15_t)0x4a3b, (q15_t)0x4a36, (q15_t)0x4a31,
+  (q15_t)0x4a2c, (q15_t)0x4a27, (q15_t)0x4a22, (q15_t)0x4a1d, (q15_t)0x4a18, (q15_t)0x4a12, (q15_t)0x4a0d, (q15_t)0x4a08,
+  (q15_t)0x4a03, (q15_t)0x49fe, (q15_t)0x49f9, (q15_t)0x49f4, (q15_t)0x49ef, (q15_t)0x49e9, (q15_t)0x49e4, (q15_t)0x49df,
+  (q15_t)0x49da, (q15_t)0x49d5, (q15_t)0x49d0, (q15_t)0x49cb, (q15_t)0x49c6, (q15_t)0x49c0, (q15_t)0x49bb, (q15_t)0x49b6,
+  (q15_t)0x49b1, (q15_t)0x49ac, (q15_t)0x49a7, (q15_t)0x49a2, (q15_t)0x499c, (q15_t)0x4997, (q15_t)0x4992, (q15_t)0x498d,
+  (q15_t)0x4988, (q15_t)0x4983, (q15_t)0x497e, (q15_t)0x4978, (q15_t)0x4973, (q15_t)0x496e, (q15_t)0x4969, (q15_t)0x4964,
+  (q15_t)0x495f, (q15_t)0x495a, (q15_t)0x4954, (q15_t)0x494f, (q15_t)0x494a, (q15_t)0x4945, (q15_t)0x4940, (q15_t)0x493b,
+  (q15_t)0x4936, (q15_t)0x4930, (q15_t)0x492b, (q15_t)0x4926, (q15_t)0x4921, (q15_t)0x491c, (q15_t)0x4917, (q15_t)0x4911,
+  (q15_t)0x490c, (q15_t)0x4907, (q15_t)0x4902, (q15_t)0x48fd, (q15_t)0x48f8, (q15_t)0x48f2, (q15_t)0x48ed, (q15_t)0x48e8,
+  (q15_t)0x48e3, (q15_t)0x48de, (q15_t)0x48d9, (q15_t)0x48d3, (q15_t)0x48ce, (q15_t)0x48c9, (q15_t)0x48c4, (q15_t)0x48bf,
+  (q15_t)0x48ba, (q15_t)0x48b4, (q15_t)0x48af, (q15_t)0x48aa, (q15_t)0x48a5, (q15_t)0x48a0, (q15_t)0x489b, (q15_t)0x4895,
+  (q15_t)0x4890, (q15_t)0x488b, (q15_t)0x4886, (q15_t)0x4881, (q15_t)0x487c, (q15_t)0x4876, (q15_t)0x4871, (q15_t)0x486c,
+  (q15_t)0x4867, (q15_t)0x4862, (q15_t)0x485c, (q15_t)0x4857, (q15_t)0x4852, (q15_t)0x484d, (q15_t)0x4848, (q15_t)0x4843,
+  (q15_t)0x483d, (q15_t)0x4838, (q15_t)0x4833, (q15_t)0x482e, (q15_t)0x4829, (q15_t)0x4823, (q15_t)0x481e, (q15_t)0x4819,
+  (q15_t)0x4814, (q15_t)0x480f, (q15_t)0x4809, (q15_t)0x4804, (q15_t)0x47ff, (q15_t)0x47fa, (q15_t)0x47f5, (q15_t)0x47ef,
+  (q15_t)0x47ea, (q15_t)0x47e5, (q15_t)0x47e0, (q15_t)0x47db, (q15_t)0x47d5, (q15_t)0x47d0, (q15_t)0x47cb, (q15_t)0x47c6,
+  (q15_t)0x47c1, (q15_t)0x47bb, (q15_t)0x47b6, (q15_t)0x47b1, (q15_t)0x47ac, (q15_t)0x47a7, (q15_t)0x47a1, (q15_t)0x479c,
+  (q15_t)0x4797, (q15_t)0x4792, (q15_t)0x478d, (q15_t)0x4787, (q15_t)0x4782, (q15_t)0x477d, (q15_t)0x4778, (q15_t)0x4773,
+  (q15_t)0x476d, (q15_t)0x4768, (q15_t)0x4763, (q15_t)0x475e, (q15_t)0x4758, (q15_t)0x4753, (q15_t)0x474e, (q15_t)0x4749,
+  (q15_t)0x4744, (q15_t)0x473e, (q15_t)0x4739, (q15_t)0x4734, (q15_t)0x472f, (q15_t)0x4729, (q15_t)0x4724, (q15_t)0x471f,
+  (q15_t)0x471a, (q15_t)0x4715, (q15_t)0x470f, (q15_t)0x470a, (q15_t)0x4705, (q15_t)0x4700, (q15_t)0x46fa, (q15_t)0x46f5,
+  (q15_t)0x46f0, (q15_t)0x46eb, (q15_t)0x46e6, (q15_t)0x46e0, (q15_t)0x46db, (q15_t)0x46d6, (q15_t)0x46d1, (q15_t)0x46cb,
+  (q15_t)0x46c6, (q15_t)0x46c1, (q15_t)0x46bc, (q15_t)0x46b6, (q15_t)0x46b1, (q15_t)0x46ac, (q15_t)0x46a7, (q15_t)0x46a1,
+  (q15_t)0x469c, (q15_t)0x4697, (q15_t)0x4692, (q15_t)0x468d, (q15_t)0x4687, (q15_t)0x4682, (q15_t)0x467d, (q15_t)0x4678,
+  (q15_t)0x4672, (q15_t)0x466d, (q15_t)0x4668, (q15_t)0x4663, (q15_t)0x465d, (q15_t)0x4658, (q15_t)0x4653, (q15_t)0x464e,
+  (q15_t)0x4648, (q15_t)0x4643, (q15_t)0x463e, (q15_t)0x4639, (q15_t)0x4633, (q15_t)0x462e, (q15_t)0x4629, (q15_t)0x4624,
+  (q15_t)0x461e, (q15_t)0x4619, (q15_t)0x4614, (q15_t)0x460e, (q15_t)0x4609, (q15_t)0x4604, (q15_t)0x45ff, (q15_t)0x45f9,
+  (q15_t)0x45f4, (q15_t)0x45ef, (q15_t)0x45ea, (q15_t)0x45e4, (q15_t)0x45df, (q15_t)0x45da, (q15_t)0x45d5, (q15_t)0x45cf,
+  (q15_t)0x45ca, (q15_t)0x45c5, (q15_t)0x45c0, (q15_t)0x45ba, (q15_t)0x45b5, (q15_t)0x45b0, (q15_t)0x45aa, (q15_t)0x45a5,
+  (q15_t)0x45a0, (q15_t)0x459b, (q15_t)0x4595, (q15_t)0x4590, (q15_t)0x458b, (q15_t)0x4586, (q15_t)0x4580, (q15_t)0x457b,
+  (q15_t)0x4576, (q15_t)0x4570, (q15_t)0x456b, (q15_t)0x4566, (q15_t)0x4561, (q15_t)0x455b, (q15_t)0x4556, (q15_t)0x4551,
+  (q15_t)0x454b, (q15_t)0x4546, (q15_t)0x4541, (q15_t)0x453c, (q15_t)0x4536, (q15_t)0x4531, (q15_t)0x452c, (q15_t)0x4526,
+  (q15_t)0x4521, (q15_t)0x451c, (q15_t)0x4517, (q15_t)0x4511, (q15_t)0x450c, (q15_t)0x4507, (q15_t)0x4501, (q15_t)0x44fc,
+  (q15_t)0x44f7, (q15_t)0x44f2, (q15_t)0x44ec, (q15_t)0x44e7, (q15_t)0x44e2, (q15_t)0x44dc, (q15_t)0x44d7, (q15_t)0x44d2,
+  (q15_t)0x44cd, (q15_t)0x44c7, (q15_t)0x44c2, (q15_t)0x44bd, (q15_t)0x44b7, (q15_t)0x44b2, (q15_t)0x44ad, (q15_t)0x44a7,
+  (q15_t)0x44a2, (q15_t)0x449d, (q15_t)0x4497, (q15_t)0x4492, (q15_t)0x448d, (q15_t)0x4488, (q15_t)0x4482, (q15_t)0x447d,
+  (q15_t)0x4478, (q15_t)0x4472, (q15_t)0x446d, (q15_t)0x4468, (q15_t)0x4462, (q15_t)0x445d, (q15_t)0x4458, (q15_t)0x4452,
+  (q15_t)0x444d, (q15_t)0x4448, (q15_t)0x4443, (q15_t)0x443d, (q15_t)0x4438, (q15_t)0x4433, (q15_t)0x442d, (q15_t)0x4428,
+  (q15_t)0x4423, (q15_t)0x441d, (q15_t)0x4418, (q15_t)0x4413, (q15_t)0x440d, (q15_t)0x4408, (q15_t)0x4403, (q15_t)0x43fd,
+  (q15_t)0x43f8, (q15_t)0x43f3, (q15_t)0x43ed, (q15_t)0x43e8, (q15_t)0x43e3, (q15_t)0x43dd, (q15_t)0x43d8, (q15_t)0x43d3,
+  (q15_t)0x43cd, (q15_t)0x43c8, (q15_t)0x43c3, (q15_t)0x43bd, (q15_t)0x43b8, (q15_t)0x43b3, (q15_t)0x43ad, (q15_t)0x43a8,
+  (q15_t)0x43a3, (q15_t)0x439d, (q15_t)0x4398, (q15_t)0x4393, (q15_t)0x438d, (q15_t)0x4388, (q15_t)0x4383, (q15_t)0x437d,
+  (q15_t)0x4378, (q15_t)0x4373, (q15_t)0x436d, (q15_t)0x4368, (q15_t)0x4363, (q15_t)0x435d, (q15_t)0x4358, (q15_t)0x4353,
+  (q15_t)0x434d, (q15_t)0x4348, (q15_t)0x4343, (q15_t)0x433d, (q15_t)0x4338, (q15_t)0x4333, (q15_t)0x432d, (q15_t)0x4328,
+  (q15_t)0x4323, (q15_t)0x431d, (q15_t)0x4318, (q15_t)0x4313, (q15_t)0x430d, (q15_t)0x4308, (q15_t)0x4302, (q15_t)0x42fd,
+  (q15_t)0x42f8, (q15_t)0x42f2, (q15_t)0x42ed, (q15_t)0x42e8, (q15_t)0x42e2, (q15_t)0x42dd, (q15_t)0x42d8, (q15_t)0x42d2,
+  (q15_t)0x42cd, (q15_t)0x42c8, (q15_t)0x42c2, (q15_t)0x42bd, (q15_t)0x42b7, (q15_t)0x42b2, (q15_t)0x42ad, (q15_t)0x42a7,
+  (q15_t)0x42a2, (q15_t)0x429d, (q15_t)0x4297, (q15_t)0x4292, (q15_t)0x428d, (q15_t)0x4287, (q15_t)0x4282, (q15_t)0x427c,
+  (q15_t)0x4277, (q15_t)0x4272, (q15_t)0x426c, (q15_t)0x4267, (q15_t)0x4262, (q15_t)0x425c, (q15_t)0x4257, (q15_t)0x4251,
+  (q15_t)0x424c, (q15_t)0x4247, (q15_t)0x4241, (q15_t)0x423c, (q15_t)0x4237, (q15_t)0x4231, (q15_t)0x422c, (q15_t)0x4226,
+  (q15_t)0x4221, (q15_t)0x421c, (q15_t)0x4216, (q15_t)0x4211, (q15_t)0x420c, (q15_t)0x4206, (q15_t)0x4201, (q15_t)0x41fb,
+  (q15_t)0x41f6, (q15_t)0x41f1, (q15_t)0x41eb, (q15_t)0x41e6, (q15_t)0x41e0, (q15_t)0x41db, (q15_t)0x41d6, (q15_t)0x41d0,
+  (q15_t)0x41cb, (q15_t)0x41c6, (q15_t)0x41c0, (q15_t)0x41bb, (q15_t)0x41b5, (q15_t)0x41b0, (q15_t)0x41ab, (q15_t)0x41a5,
+  (q15_t)0x41a0, (q15_t)0x419a, (q15_t)0x4195, (q15_t)0x4190, (q15_t)0x418a, (q15_t)0x4185, (q15_t)0x417f, (q15_t)0x417a,
+  (q15_t)0x4175, (q15_t)0x416f, (q15_t)0x416a, (q15_t)0x4164, (q15_t)0x415f, (q15_t)0x415a, (q15_t)0x4154, (q15_t)0x414f,
+  (q15_t)0x4149, (q15_t)0x4144, (q15_t)0x413f, (q15_t)0x4139, (q15_t)0x4134, (q15_t)0x412e, (q15_t)0x4129, (q15_t)0x4124,
+  (q15_t)0x411e, (q15_t)0x4119, (q15_t)0x4113, (q15_t)0x410e, (q15_t)0x4108, (q15_t)0x4103, (q15_t)0x40fe, (q15_t)0x40f8,
+  (q15_t)0x40f3, (q15_t)0x40ed, (q15_t)0x40e8, (q15_t)0x40e3, (q15_t)0x40dd, (q15_t)0x40d8, (q15_t)0x40d2, (q15_t)0x40cd,
+  (q15_t)0x40c8, (q15_t)0x40c2, (q15_t)0x40bd, (q15_t)0x40b7, (q15_t)0x40b2, (q15_t)0x40ac, (q15_t)0x40a7, (q15_t)0x40a2,
+  (q15_t)0x409c, (q15_t)0x4097, (q15_t)0x4091, (q15_t)0x408c, (q15_t)0x4086, (q15_t)0x4081, (q15_t)0x407c, (q15_t)0x4076,
+  (q15_t)0x4071, (q15_t)0x406b, (q15_t)0x4066, (q15_t)0x4060, (q15_t)0x405b, (q15_t)0x4056, (q15_t)0x4050, (q15_t)0x404b,
+  (q15_t)0x4045, (q15_t)0x4040, (q15_t)0x403a, (q15_t)0x4035, (q15_t)0x4030, (q15_t)0x402a, (q15_t)0x4025, (q15_t)0x401f,
+  (q15_t)0x401a, (q15_t)0x4014, (q15_t)0x400f, (q15_t)0x4009, (q15_t)0x4004, (q15_t)0x3fff, (q15_t)0x3ff9, (q15_t)0x3ff4,
+  (q15_t)0x3fee, (q15_t)0x3fe9, (q15_t)0x3fe3, (q15_t)0x3fde, (q15_t)0x3fd8, (q15_t)0x3fd3, (q15_t)0x3fce, (q15_t)0x3fc8,
+  (q15_t)0x3fc3, (q15_t)0x3fbd, (q15_t)0x3fb8, (q15_t)0x3fb2, (q15_t)0x3fad, (q15_t)0x3fa7, (q15_t)0x3fa2, (q15_t)0x3f9d,
+  (q15_t)0x3f97, (q15_t)0x3f92, (q15_t)0x3f8c, (q15_t)0x3f87, (q15_t)0x3f81, (q15_t)0x3f7c, (q15_t)0x3f76, (q15_t)0x3f71,
+  (q15_t)0x3f6b, (q15_t)0x3f66, (q15_t)0x3f61, (q15_t)0x3f5b, (q15_t)0x3f56, (q15_t)0x3f50, (q15_t)0x3f4b, (q15_t)0x3f45,
+  (q15_t)0x3f40, (q15_t)0x3f3a, (q15_t)0x3f35, (q15_t)0x3f2f, (q15_t)0x3f2a, (q15_t)0x3f24, (q15_t)0x3f1f, (q15_t)0x3f1a,
+  (q15_t)0x3f14, (q15_t)0x3f0f, (q15_t)0x3f09, (q15_t)0x3f04, (q15_t)0x3efe, (q15_t)0x3ef9, (q15_t)0x3ef3, (q15_t)0x3eee,
+  (q15_t)0x3ee8, (q15_t)0x3ee3, (q15_t)0x3edd, (q15_t)0x3ed8, (q15_t)0x3ed2, (q15_t)0x3ecd, (q15_t)0x3ec7, (q15_t)0x3ec2,
+  (q15_t)0x3ebd, (q15_t)0x3eb7, (q15_t)0x3eb2, (q15_t)0x3eac, (q15_t)0x3ea7, (q15_t)0x3ea1, (q15_t)0x3e9c, (q15_t)0x3e96,
+  (q15_t)0x3e91, (q15_t)0x3e8b, (q15_t)0x3e86, (q15_t)0x3e80, (q15_t)0x3e7b, (q15_t)0x3e75, (q15_t)0x3e70, (q15_t)0x3e6a,
+  (q15_t)0x3e65, (q15_t)0x3e5f, (q15_t)0x3e5a, (q15_t)0x3e54, (q15_t)0x3e4f, (q15_t)0x3e49, (q15_t)0x3e44, (q15_t)0x3e3e,
+  (q15_t)0x3e39, (q15_t)0x3e33, (q15_t)0x3e2e, (q15_t)0x3e28, (q15_t)0x3e23, (q15_t)0x3e1d, (q15_t)0x3e18, (q15_t)0x3e12,
+  (q15_t)0x3e0d, (q15_t)0x3e07, (q15_t)0x3e02, (q15_t)0x3dfc, (q15_t)0x3df7, (q15_t)0x3df1, (q15_t)0x3dec, (q15_t)0x3de6,
+  (q15_t)0x3de1, (q15_t)0x3ddb, (q15_t)0x3dd6, (q15_t)0x3dd0, (q15_t)0x3dcb, (q15_t)0x3dc5, (q15_t)0x3dc0, (q15_t)0x3dba,
+  (q15_t)0x3db5, (q15_t)0x3daf, (q15_t)0x3daa, (q15_t)0x3da4, (q15_t)0x3d9f, (q15_t)0x3d99, (q15_t)0x3d94, (q15_t)0x3d8e,
+  (q15_t)0x3d89, (q15_t)0x3d83, (q15_t)0x3d7e, (q15_t)0x3d78, (q15_t)0x3d73, (q15_t)0x3d6d, (q15_t)0x3d68, (q15_t)0x3d62,
+  (q15_t)0x3d5d, (q15_t)0x3d57, (q15_t)0x3d52, (q15_t)0x3d4c, (q15_t)0x3d47, (q15_t)0x3d41, (q15_t)0x3d3c, (q15_t)0x3d36,
+  (q15_t)0x3d31, (q15_t)0x3d2b, (q15_t)0x3d26, (q15_t)0x3d20, (q15_t)0x3d1b, (q15_t)0x3d15, (q15_t)0x3d10, (q15_t)0x3d0a,
+  (q15_t)0x3d04, (q15_t)0x3cff, (q15_t)0x3cf9, (q15_t)0x3cf4, (q15_t)0x3cee, (q15_t)0x3ce9, (q15_t)0x3ce3, (q15_t)0x3cde,
+  (q15_t)0x3cd8, (q15_t)0x3cd3, (q15_t)0x3ccd, (q15_t)0x3cc8, (q15_t)0x3cc2, (q15_t)0x3cbd, (q15_t)0x3cb7, (q15_t)0x3cb2,
+  (q15_t)0x3cac, (q15_t)0x3ca7, (q15_t)0x3ca1, (q15_t)0x3c9b, (q15_t)0x3c96, (q15_t)0x3c90, (q15_t)0x3c8b, (q15_t)0x3c85,
+  (q15_t)0x3c80, (q15_t)0x3c7a, (q15_t)0x3c75, (q15_t)0x3c6f, (q15_t)0x3c6a, (q15_t)0x3c64, (q15_t)0x3c5f, (q15_t)0x3c59,
+  (q15_t)0x3c53, (q15_t)0x3c4e, (q15_t)0x3c48, (q15_t)0x3c43, (q15_t)0x3c3d, (q15_t)0x3c38, (q15_t)0x3c32, (q15_t)0x3c2d,
+  (q15_t)0x3c27, (q15_t)0x3c22, (q15_t)0x3c1c, (q15_t)0x3c16, (q15_t)0x3c11, (q15_t)0x3c0b, (q15_t)0x3c06, (q15_t)0x3c00,
+  (q15_t)0x3bfb, (q15_t)0x3bf5, (q15_t)0x3bf0, (q15_t)0x3bea, (q15_t)0x3be5, (q15_t)0x3bdf, (q15_t)0x3bd9, (q15_t)0x3bd4,
+  (q15_t)0x3bce, (q15_t)0x3bc9, (q15_t)0x3bc3, (q15_t)0x3bbe, (q15_t)0x3bb8, (q15_t)0x3bb3, (q15_t)0x3bad, (q15_t)0x3ba7,
+  (q15_t)0x3ba2, (q15_t)0x3b9c, (q15_t)0x3b97, (q15_t)0x3b91, (q15_t)0x3b8c, (q15_t)0x3b86, (q15_t)0x3b80, (q15_t)0x3b7b,
+  (q15_t)0x3b75, (q15_t)0x3b70, (q15_t)0x3b6a, (q15_t)0x3b65, (q15_t)0x3b5f, (q15_t)0x3b5a, (q15_t)0x3b54, (q15_t)0x3b4e,
+  (q15_t)0x3b49, (q15_t)0x3b43, (q15_t)0x3b3e, (q15_t)0x3b38, (q15_t)0x3b33, (q15_t)0x3b2d, (q15_t)0x3b27, (q15_t)0x3b22,
+  (q15_t)0x3b1c, (q15_t)0x3b17, (q15_t)0x3b11, (q15_t)0x3b0c, (q15_t)0x3b06, (q15_t)0x3b00, (q15_t)0x3afb, (q15_t)0x3af5,
+  (q15_t)0x3af0, (q15_t)0x3aea, (q15_t)0x3ae4, (q15_t)0x3adf, (q15_t)0x3ad9, (q15_t)0x3ad4, (q15_t)0x3ace, (q15_t)0x3ac9,
+  (q15_t)0x3ac3, (q15_t)0x3abd, (q15_t)0x3ab8, (q15_t)0x3ab2, (q15_t)0x3aad, (q15_t)0x3aa7, (q15_t)0x3aa2, (q15_t)0x3a9c,
+  (q15_t)0x3a96, (q15_t)0x3a91, (q15_t)0x3a8b, (q15_t)0x3a86, (q15_t)0x3a80, (q15_t)0x3a7a, (q15_t)0x3a75, (q15_t)0x3a6f,
+  (q15_t)0x3a6a, (q15_t)0x3a64, (q15_t)0x3a5e, (q15_t)0x3a59, (q15_t)0x3a53, (q15_t)0x3a4e, (q15_t)0x3a48, (q15_t)0x3a42,
+  (q15_t)0x3a3d, (q15_t)0x3a37, (q15_t)0x3a32, (q15_t)0x3a2c, (q15_t)0x3a26, (q15_t)0x3a21, (q15_t)0x3a1b, (q15_t)0x3a16,
+  (q15_t)0x3a10, (q15_t)0x3a0b, (q15_t)0x3a05, (q15_t)0x39ff, (q15_t)0x39fa, (q15_t)0x39f4, (q15_t)0x39ee, (q15_t)0x39e9,
+  (q15_t)0x39e3, (q15_t)0x39de, (q15_t)0x39d8, (q15_t)0x39d2, (q15_t)0x39cd, (q15_t)0x39c7, (q15_t)0x39c2, (q15_t)0x39bc,
+  (q15_t)0x39b6, (q15_t)0x39b1, (q15_t)0x39ab, (q15_t)0x39a6, (q15_t)0x39a0, (q15_t)0x399a, (q15_t)0x3995, (q15_t)0x398f,
+  (q15_t)0x398a, (q15_t)0x3984, (q15_t)0x397e, (q15_t)0x3979, (q15_t)0x3973, (q15_t)0x396d, (q15_t)0x3968, (q15_t)0x3962,
+  (q15_t)0x395d, (q15_t)0x3957, (q15_t)0x3951, (q15_t)0x394c, (q15_t)0x3946, (q15_t)0x3941, (q15_t)0x393b, (q15_t)0x3935,
+  (q15_t)0x3930, (q15_t)0x392a, (q15_t)0x3924, (q15_t)0x391f, (q15_t)0x3919, (q15_t)0x3914, (q15_t)0x390e, (q15_t)0x3908,
+  (q15_t)0x3903, (q15_t)0x38fd, (q15_t)0x38f7, (q15_t)0x38f2, (q15_t)0x38ec, (q15_t)0x38e7, (q15_t)0x38e1, (q15_t)0x38db,
+  (q15_t)0x38d6, (q15_t)0x38d0, (q15_t)0x38ca, (q15_t)0x38c5, (q15_t)0x38bf, (q15_t)0x38ba, (q15_t)0x38b4, (q15_t)0x38ae,
+  (q15_t)0x38a9, (q15_t)0x38a3, (q15_t)0x389d, (q15_t)0x3898, (q15_t)0x3892, (q15_t)0x388c, (q15_t)0x3887, (q15_t)0x3881,
+  (q15_t)0x387c, (q15_t)0x3876, (q15_t)0x3870, (q15_t)0x386b, (q15_t)0x3865, (q15_t)0x385f, (q15_t)0x385a, (q15_t)0x3854,
+  (q15_t)0x384e, (q15_t)0x3849, (q15_t)0x3843, (q15_t)0x383d, (q15_t)0x3838, (q15_t)0x3832, (q15_t)0x382d, (q15_t)0x3827,
+  (q15_t)0x3821, (q15_t)0x381c, (q15_t)0x3816, (q15_t)0x3810, (q15_t)0x380b, (q15_t)0x3805, (q15_t)0x37ff, (q15_t)0x37fa,
+  (q15_t)0x37f4, (q15_t)0x37ee, (q15_t)0x37e9, (q15_t)0x37e3, (q15_t)0x37dd, (q15_t)0x37d8, (q15_t)0x37d2, (q15_t)0x37cc,
+  (q15_t)0x37c7, (q15_t)0x37c1, (q15_t)0x37bc, (q15_t)0x37b6, (q15_t)0x37b0, (q15_t)0x37ab, (q15_t)0x37a5, (q15_t)0x379f,
+  (q15_t)0x379a, (q15_t)0x3794, (q15_t)0x378e, (q15_t)0x3789, (q15_t)0x3783, (q15_t)0x377d, (q15_t)0x3778, (q15_t)0x3772,
+  (q15_t)0x376c, (q15_t)0x3767, (q15_t)0x3761, (q15_t)0x375b, (q15_t)0x3756, (q15_t)0x3750, (q15_t)0x374a, (q15_t)0x3745,
+  (q15_t)0x373f, (q15_t)0x3739, (q15_t)0x3734, (q15_t)0x372e, (q15_t)0x3728, (q15_t)0x3723, (q15_t)0x371d, (q15_t)0x3717,
+  (q15_t)0x3712, (q15_t)0x370c, (q15_t)0x3706, (q15_t)0x3701, (q15_t)0x36fb, (q15_t)0x36f5, (q15_t)0x36f0, (q15_t)0x36ea,
+  (q15_t)0x36e4, (q15_t)0x36df, (q15_t)0x36d9, (q15_t)0x36d3, (q15_t)0x36ce, (q15_t)0x36c8, (q15_t)0x36c2, (q15_t)0x36bc,
+  (q15_t)0x36b7, (q15_t)0x36b1, (q15_t)0x36ab, (q15_t)0x36a6, (q15_t)0x36a0, (q15_t)0x369a, (q15_t)0x3695, (q15_t)0x368f,
+  (q15_t)0x3689, (q15_t)0x3684, (q15_t)0x367e, (q15_t)0x3678, (q15_t)0x3673, (q15_t)0x366d, (q15_t)0x3667, (q15_t)0x3662,
+  (q15_t)0x365c, (q15_t)0x3656, (q15_t)0x3650, (q15_t)0x364b, (q15_t)0x3645, (q15_t)0x363f, (q15_t)0x363a, (q15_t)0x3634,
+  (q15_t)0x362e, (q15_t)0x3629, (q15_t)0x3623, (q15_t)0x361d, (q15_t)0x3618, (q15_t)0x3612, (q15_t)0x360c, (q15_t)0x3606,
+  (q15_t)0x3601, (q15_t)0x35fb, (q15_t)0x35f5, (q15_t)0x35f0, (q15_t)0x35ea, (q15_t)0x35e4, (q15_t)0x35df, (q15_t)0x35d9,
+  (q15_t)0x35d3, (q15_t)0x35cd, (q15_t)0x35c8, (q15_t)0x35c2, (q15_t)0x35bc, (q15_t)0x35b7, (q15_t)0x35b1, (q15_t)0x35ab,
+  (q15_t)0x35a6, (q15_t)0x35a0, (q15_t)0x359a, (q15_t)0x3594, (q15_t)0x358f, (q15_t)0x3589, (q15_t)0x3583, (q15_t)0x357e,
+  (q15_t)0x3578, (q15_t)0x3572, (q15_t)0x356c, (q15_t)0x3567, (q15_t)0x3561, (q15_t)0x355b, (q15_t)0x3556, (q15_t)0x3550,
+  (q15_t)0x354a, (q15_t)0x3544, (q15_t)0x353f, (q15_t)0x3539, (q15_t)0x3533, (q15_t)0x352e, (q15_t)0x3528, (q15_t)0x3522,
+  (q15_t)0x351c, (q15_t)0x3517, (q15_t)0x3511, (q15_t)0x350b, (q15_t)0x3506, (q15_t)0x3500, (q15_t)0x34fa, (q15_t)0x34f4,
+  (q15_t)0x34ef, (q15_t)0x34e9, (q15_t)0x34e3, (q15_t)0x34de, (q15_t)0x34d8, (q15_t)0x34d2, (q15_t)0x34cc, (q15_t)0x34c7,
+  (q15_t)0x34c1, (q15_t)0x34bb, (q15_t)0x34b6, (q15_t)0x34b0, (q15_t)0x34aa, (q15_t)0x34a4, (q15_t)0x349f, (q15_t)0x3499,
+  (q15_t)0x3493, (q15_t)0x348d, (q15_t)0x3488, (q15_t)0x3482, (q15_t)0x347c, (q15_t)0x3476, (q15_t)0x3471, (q15_t)0x346b,
+  (q15_t)0x3465, (q15_t)0x3460, (q15_t)0x345a, (q15_t)0x3454, (q15_t)0x344e, (q15_t)0x3449, (q15_t)0x3443, (q15_t)0x343d,
+  (q15_t)0x3437, (q15_t)0x3432, (q15_t)0x342c, (q15_t)0x3426, (q15_t)0x3420, (q15_t)0x341b, (q15_t)0x3415, (q15_t)0x340f,
+  (q15_t)0x340a, (q15_t)0x3404, (q15_t)0x33fe, (q15_t)0x33f8, (q15_t)0x33f3, (q15_t)0x33ed, (q15_t)0x33e7, (q15_t)0x33e1,
+  (q15_t)0x33dc, (q15_t)0x33d6, (q15_t)0x33d0, (q15_t)0x33ca, (q15_t)0x33c5, (q15_t)0x33bf, (q15_t)0x33b9, (q15_t)0x33b3,
+  (q15_t)0x33ae, (q15_t)0x33a8, (q15_t)0x33a2, (q15_t)0x339c, (q15_t)0x3397, (q15_t)0x3391, (q15_t)0x338b, (q15_t)0x3385,
+  (q15_t)0x3380, (q15_t)0x337a, (q15_t)0x3374, (q15_t)0x336e, (q15_t)0x3369, (q15_t)0x3363, (q15_t)0x335d, (q15_t)0x3357,
+  (q15_t)0x3352, (q15_t)0x334c, (q15_t)0x3346, (q15_t)0x3340, (q15_t)0x333b, (q15_t)0x3335, (q15_t)0x332f, (q15_t)0x3329,
+  (q15_t)0x3324, (q15_t)0x331e, (q15_t)0x3318, (q15_t)0x3312, (q15_t)0x330c, (q15_t)0x3307, (q15_t)0x3301, (q15_t)0x32fb,
+  (q15_t)0x32f5, (q15_t)0x32f0, (q15_t)0x32ea, (q15_t)0x32e4, (q15_t)0x32de, (q15_t)0x32d9, (q15_t)0x32d3, (q15_t)0x32cd,
+  (q15_t)0x32c7, (q15_t)0x32c2, (q15_t)0x32bc, (q15_t)0x32b6, (q15_t)0x32b0, (q15_t)0x32aa, (q15_t)0x32a5, (q15_t)0x329f,
+  (q15_t)0x3299, (q15_t)0x3293, (q15_t)0x328e, (q15_t)0x3288, (q15_t)0x3282, (q15_t)0x327c, (q15_t)0x3276, (q15_t)0x3271,
+  (q15_t)0x326b, (q15_t)0x3265, (q15_t)0x325f, (q15_t)0x325a, (q15_t)0x3254, (q15_t)0x324e, (q15_t)0x3248, (q15_t)0x3243,
+  (q15_t)0x323d, (q15_t)0x3237, (q15_t)0x3231, (q15_t)0x322b, (q15_t)0x3226, (q15_t)0x3220, (q15_t)0x321a, (q15_t)0x3214,
+  (q15_t)0x320e, (q15_t)0x3209, (q15_t)0x3203, (q15_t)0x31fd, (q15_t)0x31f7, (q15_t)0x31f2, (q15_t)0x31ec, (q15_t)0x31e6,
+  (q15_t)0x31e0, (q15_t)0x31da, (q15_t)0x31d5, (q15_t)0x31cf, (q15_t)0x31c9, (q15_t)0x31c3, (q15_t)0x31bd, (q15_t)0x31b8,
+  (q15_t)0x31b2, (q15_t)0x31ac, (q15_t)0x31a6, (q15_t)0x31a1, (q15_t)0x319b, (q15_t)0x3195, (q15_t)0x318f, (q15_t)0x3189,
+  (q15_t)0x3184, (q15_t)0x317e, (q15_t)0x3178, (q15_t)0x3172, (q15_t)0x316c, (q15_t)0x3167, (q15_t)0x3161, (q15_t)0x315b,
+  (q15_t)0x3155, (q15_t)0x314f, (q15_t)0x314a, (q15_t)0x3144, (q15_t)0x313e, (q15_t)0x3138, (q15_t)0x3132, (q15_t)0x312d,
+  (q15_t)0x3127, (q15_t)0x3121, (q15_t)0x311b, (q15_t)0x3115, (q15_t)0x3110, (q15_t)0x310a, (q15_t)0x3104, (q15_t)0x30fe,
+  (q15_t)0x30f8, (q15_t)0x30f3, (q15_t)0x30ed, (q15_t)0x30e7, (q15_t)0x30e1, (q15_t)0x30db, (q15_t)0x30d6, (q15_t)0x30d0,
+  (q15_t)0x30ca, (q15_t)0x30c4, (q15_t)0x30be, (q15_t)0x30b8, (q15_t)0x30b3, (q15_t)0x30ad, (q15_t)0x30a7, (q15_t)0x30a1,
+  (q15_t)0x309b, (q15_t)0x3096, (q15_t)0x3090, (q15_t)0x308a, (q15_t)0x3084, (q15_t)0x307e, (q15_t)0x3079, (q15_t)0x3073,
+  (q15_t)0x306d, (q15_t)0x3067, (q15_t)0x3061, (q15_t)0x305b, (q15_t)0x3056, (q15_t)0x3050, (q15_t)0x304a, (q15_t)0x3044,
+  (q15_t)0x303e, (q15_t)0x3039, (q15_t)0x3033, (q15_t)0x302d, (q15_t)0x3027, (q15_t)0x3021, (q15_t)0x301b, (q15_t)0x3016,
+  (q15_t)0x3010, (q15_t)0x300a, (q15_t)0x3004, (q15_t)0x2ffe, (q15_t)0x2ff8, (q15_t)0x2ff3, (q15_t)0x2fed, (q15_t)0x2fe7,
+  (q15_t)0x2fe1, (q15_t)0x2fdb, (q15_t)0x2fd6, (q15_t)0x2fd0, (q15_t)0x2fca, (q15_t)0x2fc4, (q15_t)0x2fbe, (q15_t)0x2fb8,
+  (q15_t)0x2fb3, (q15_t)0x2fad, (q15_t)0x2fa7, (q15_t)0x2fa1, (q15_t)0x2f9b, (q15_t)0x2f95, (q15_t)0x2f90, (q15_t)0x2f8a,
+  (q15_t)0x2f84, (q15_t)0x2f7e, (q15_t)0x2f78, (q15_t)0x2f72, (q15_t)0x2f6d, (q15_t)0x2f67, (q15_t)0x2f61, (q15_t)0x2f5b,
+  (q15_t)0x2f55, (q15_t)0x2f4f, (q15_t)0x2f4a, (q15_t)0x2f44, (q15_t)0x2f3e, (q15_t)0x2f38, (q15_t)0x2f32, (q15_t)0x2f2c,
+  (q15_t)0x2f27, (q15_t)0x2f21, (q15_t)0x2f1b, (q15_t)0x2f15, (q15_t)0x2f0f, (q15_t)0x2f09, (q15_t)0x2f03, (q15_t)0x2efe,
+  (q15_t)0x2ef8, (q15_t)0x2ef2, (q15_t)0x2eec, (q15_t)0x2ee6, (q15_t)0x2ee0, (q15_t)0x2edb, (q15_t)0x2ed5, (q15_t)0x2ecf,
+  (q15_t)0x2ec9, (q15_t)0x2ec3, (q15_t)0x2ebd, (q15_t)0x2eb7, (q15_t)0x2eb2, (q15_t)0x2eac, (q15_t)0x2ea6, (q15_t)0x2ea0,
+  (q15_t)0x2e9a, (q15_t)0x2e94, (q15_t)0x2e8e, (q15_t)0x2e89, (q15_t)0x2e83, (q15_t)0x2e7d, (q15_t)0x2e77, (q15_t)0x2e71,
+  (q15_t)0x2e6b, (q15_t)0x2e65, (q15_t)0x2e60, (q15_t)0x2e5a, (q15_t)0x2e54, (q15_t)0x2e4e, (q15_t)0x2e48, (q15_t)0x2e42,
+  (q15_t)0x2e3c, (q15_t)0x2e37, (q15_t)0x2e31, (q15_t)0x2e2b, (q15_t)0x2e25, (q15_t)0x2e1f, (q15_t)0x2e19, (q15_t)0x2e13,
+  (q15_t)0x2e0e, (q15_t)0x2e08, (q15_t)0x2e02, (q15_t)0x2dfc, (q15_t)0x2df6, (q15_t)0x2df0, (q15_t)0x2dea, (q15_t)0x2de5,
+  (q15_t)0x2ddf, (q15_t)0x2dd9, (q15_t)0x2dd3, (q15_t)0x2dcd, (q15_t)0x2dc7, (q15_t)0x2dc1, (q15_t)0x2dbb, (q15_t)0x2db6,
+  (q15_t)0x2db0, (q15_t)0x2daa, (q15_t)0x2da4, (q15_t)0x2d9e, (q15_t)0x2d98, (q15_t)0x2d92, (q15_t)0x2d8d, (q15_t)0x2d87,
+  (q15_t)0x2d81, (q15_t)0x2d7b, (q15_t)0x2d75, (q15_t)0x2d6f, (q15_t)0x2d69, (q15_t)0x2d63, (q15_t)0x2d5e, (q15_t)0x2d58,
+  (q15_t)0x2d52, (q15_t)0x2d4c, (q15_t)0x2d46, (q15_t)0x2d40, (q15_t)0x2d3a, (q15_t)0x2d34, (q15_t)0x2d2f, (q15_t)0x2d29,
+  (q15_t)0x2d23, (q15_t)0x2d1d, (q15_t)0x2d17, (q15_t)0x2d11, (q15_t)0x2d0b, (q15_t)0x2d05, (q15_t)0x2cff, (q15_t)0x2cfa,
+  (q15_t)0x2cf4, (q15_t)0x2cee, (q15_t)0x2ce8, (q15_t)0x2ce2, (q15_t)0x2cdc, (q15_t)0x2cd6, (q15_t)0x2cd0, (q15_t)0x2ccb,
+  (q15_t)0x2cc5, (q15_t)0x2cbf, (q15_t)0x2cb9, (q15_t)0x2cb3, (q15_t)0x2cad, (q15_t)0x2ca7, (q15_t)0x2ca1, (q15_t)0x2c9b,
+  (q15_t)0x2c96, (q15_t)0x2c90, (q15_t)0x2c8a, (q15_t)0x2c84, (q15_t)0x2c7e, (q15_t)0x2c78, (q15_t)0x2c72, (q15_t)0x2c6c,
+  (q15_t)0x2c66, (q15_t)0x2c61, (q15_t)0x2c5b, (q15_t)0x2c55, (q15_t)0x2c4f, (q15_t)0x2c49, (q15_t)0x2c43, (q15_t)0x2c3d,
+  (q15_t)0x2c37, (q15_t)0x2c31, (q15_t)0x2c2b, (q15_t)0x2c26, (q15_t)0x2c20, (q15_t)0x2c1a, (q15_t)0x2c14, (q15_t)0x2c0e,
+  (q15_t)0x2c08, (q15_t)0x2c02, (q15_t)0x2bfc, (q15_t)0x2bf6, (q15_t)0x2bf0, (q15_t)0x2beb, (q15_t)0x2be5, (q15_t)0x2bdf,
+  (q15_t)0x2bd9, (q15_t)0x2bd3, (q15_t)0x2bcd, (q15_t)0x2bc7, (q15_t)0x2bc1, (q15_t)0x2bbb, (q15_t)0x2bb5, (q15_t)0x2bb0,
+  (q15_t)0x2baa, (q15_t)0x2ba4, (q15_t)0x2b9e, (q15_t)0x2b98, (q15_t)0x2b92, (q15_t)0x2b8c, (q15_t)0x2b86, (q15_t)0x2b80,
+  (q15_t)0x2b7a, (q15_t)0x2b74, (q15_t)0x2b6f, (q15_t)0x2b69, (q15_t)0x2b63, (q15_t)0x2b5d, (q15_t)0x2b57, (q15_t)0x2b51,
+  (q15_t)0x2b4b, (q15_t)0x2b45, (q15_t)0x2b3f, (q15_t)0x2b39, (q15_t)0x2b33, (q15_t)0x2b2d, (q15_t)0x2b28, (q15_t)0x2b22,
+  (q15_t)0x2b1c, (q15_t)0x2b16, (q15_t)0x2b10, (q15_t)0x2b0a, (q15_t)0x2b04, (q15_t)0x2afe, (q15_t)0x2af8, (q15_t)0x2af2,
+  (q15_t)0x2aec, (q15_t)0x2ae6, (q15_t)0x2ae1, (q15_t)0x2adb, (q15_t)0x2ad5, (q15_t)0x2acf, (q15_t)0x2ac9, (q15_t)0x2ac3,
+  (q15_t)0x2abd, (q15_t)0x2ab7, (q15_t)0x2ab1, (q15_t)0x2aab, (q15_t)0x2aa5, (q15_t)0x2a9f, (q15_t)0x2a99, (q15_t)0x2a94,
+  (q15_t)0x2a8e, (q15_t)0x2a88, (q15_t)0x2a82, (q15_t)0x2a7c, (q15_t)0x2a76, (q15_t)0x2a70, (q15_t)0x2a6a, (q15_t)0x2a64,
+  (q15_t)0x2a5e, (q15_t)0x2a58, (q15_t)0x2a52, (q15_t)0x2a4c, (q15_t)0x2a47, (q15_t)0x2a41, (q15_t)0x2a3b, (q15_t)0x2a35,
+  (q15_t)0x2a2f, (q15_t)0x2a29, (q15_t)0x2a23, (q15_t)0x2a1d, (q15_t)0x2a17, (q15_t)0x2a11, (q15_t)0x2a0b, (q15_t)0x2a05,
+  (q15_t)0x29ff, (q15_t)0x29f9, (q15_t)0x29f3, (q15_t)0x29ee, (q15_t)0x29e8, (q15_t)0x29e2, (q15_t)0x29dc, (q15_t)0x29d6,
+  (q15_t)0x29d0, (q15_t)0x29ca, (q15_t)0x29c4, (q15_t)0x29be, (q15_t)0x29b8, (q15_t)0x29b2, (q15_t)0x29ac, (q15_t)0x29a6,
+  (q15_t)0x29a0, (q15_t)0x299a, (q15_t)0x2994, (q15_t)0x298e, (q15_t)0x2989, (q15_t)0x2983, (q15_t)0x297d, (q15_t)0x2977,
+  (q15_t)0x2971, (q15_t)0x296b, (q15_t)0x2965, (q15_t)0x295f, (q15_t)0x2959, (q15_t)0x2953, (q15_t)0x294d, (q15_t)0x2947,
+  (q15_t)0x2941, (q15_t)0x293b, (q15_t)0x2935, (q15_t)0x292f, (q15_t)0x2929, (q15_t)0x2923, (q15_t)0x291d, (q15_t)0x2918,
+  (q15_t)0x2912, (q15_t)0x290c, (q15_t)0x2906, (q15_t)0x2900, (q15_t)0x28fa, (q15_t)0x28f4, (q15_t)0x28ee, (q15_t)0x28e8,
+  (q15_t)0x28e2, (q15_t)0x28dc, (q15_t)0x28d6, (q15_t)0x28d0, (q15_t)0x28ca, (q15_t)0x28c4, (q15_t)0x28be, (q15_t)0x28b8,
+  (q15_t)0x28b2, (q15_t)0x28ac, (q15_t)0x28a6, (q15_t)0x28a0, (q15_t)0x289a, (q15_t)0x2895, (q15_t)0x288f, (q15_t)0x2889,
+  (q15_t)0x2883, (q15_t)0x287d, (q15_t)0x2877, (q15_t)0x2871, (q15_t)0x286b, (q15_t)0x2865, (q15_t)0x285f, (q15_t)0x2859,
+  (q15_t)0x2853, (q15_t)0x284d, (q15_t)0x2847, (q15_t)0x2841, (q15_t)0x283b, (q15_t)0x2835, (q15_t)0x282f, (q15_t)0x2829,
+  (q15_t)0x2823, (q15_t)0x281d, (q15_t)0x2817, (q15_t)0x2811, (q15_t)0x280b, (q15_t)0x2805, (q15_t)0x27ff, (q15_t)0x27f9,
+  (q15_t)0x27f3, (q15_t)0x27ee, (q15_t)0x27e8, (q15_t)0x27e2, (q15_t)0x27dc, (q15_t)0x27d6, (q15_t)0x27d0, (q15_t)0x27ca,
+  (q15_t)0x27c4, (q15_t)0x27be, (q15_t)0x27b8, (q15_t)0x27b2, (q15_t)0x27ac, (q15_t)0x27a6, (q15_t)0x27a0, (q15_t)0x279a,
+  (q15_t)0x2794, (q15_t)0x278e, (q15_t)0x2788, (q15_t)0x2782, (q15_t)0x277c, (q15_t)0x2776, (q15_t)0x2770, (q15_t)0x276a,
+  (q15_t)0x2764, (q15_t)0x275e, (q15_t)0x2758, (q15_t)0x2752, (q15_t)0x274c, (q15_t)0x2746, (q15_t)0x2740, (q15_t)0x273a,
+  (q15_t)0x2734, (q15_t)0x272e, (q15_t)0x2728, (q15_t)0x2722, (q15_t)0x271c, (q15_t)0x2716, (q15_t)0x2710, (q15_t)0x270a,
+  (q15_t)0x2704, (q15_t)0x26fe, (q15_t)0x26f8, (q15_t)0x26f2, (q15_t)0x26ec, (q15_t)0x26e7, (q15_t)0x26e1, (q15_t)0x26db,
+  (q15_t)0x26d5, (q15_t)0x26cf, (q15_t)0x26c9, (q15_t)0x26c3, (q15_t)0x26bd, (q15_t)0x26b7, (q15_t)0x26b1, (q15_t)0x26ab,
+  (q15_t)0x26a5, (q15_t)0x269f, (q15_t)0x2699, (q15_t)0x2693, (q15_t)0x268d, (q15_t)0x2687, (q15_t)0x2681, (q15_t)0x267b,
+  (q15_t)0x2675, (q15_t)0x266f, (q15_t)0x2669, (q15_t)0x2663, (q15_t)0x265d, (q15_t)0x2657, (q15_t)0x2651, (q15_t)0x264b,
+  (q15_t)0x2645, (q15_t)0x263f, (q15_t)0x2639, (q15_t)0x2633, (q15_t)0x262d, (q15_t)0x2627, (q15_t)0x2621, (q15_t)0x261b,
+  (q15_t)0x2615, (q15_t)0x260f, (q15_t)0x2609, (q15_t)0x2603, (q15_t)0x25fd, (q15_t)0x25f7, (q15_t)0x25f1, (q15_t)0x25eb,
+  (q15_t)0x25e5, (q15_t)0x25df, (q15_t)0x25d9, (q15_t)0x25d3, (q15_t)0x25cd, (q15_t)0x25c7, (q15_t)0x25c1, (q15_t)0x25bb,
+  (q15_t)0x25b5, (q15_t)0x25af, (q15_t)0x25a9, (q15_t)0x25a3, (q15_t)0x259d, (q15_t)0x2597, (q15_t)0x2591, (q15_t)0x258b,
+  (q15_t)0x2585, (q15_t)0x257f, (q15_t)0x2579, (q15_t)0x2573, (q15_t)0x256d, (q15_t)0x2567, (q15_t)0x2561, (q15_t)0x255b,
+  (q15_t)0x2555, (q15_t)0x254f, (q15_t)0x2549, (q15_t)0x2543, (q15_t)0x253d, (q15_t)0x2537, (q15_t)0x2531, (q15_t)0x252b,
+  (q15_t)0x2525, (q15_t)0x251f, (q15_t)0x2519, (q15_t)0x2513, (q15_t)0x250c, (q15_t)0x2506, (q15_t)0x2500, (q15_t)0x24fa,
+  (q15_t)0x24f4, (q15_t)0x24ee, (q15_t)0x24e8, (q15_t)0x24e2, (q15_t)0x24dc, (q15_t)0x24d6, (q15_t)0x24d0, (q15_t)0x24ca,
+  (q15_t)0x24c4, (q15_t)0x24be, (q15_t)0x24b8, (q15_t)0x24b2, (q15_t)0x24ac, (q15_t)0x24a6, (q15_t)0x24a0, (q15_t)0x249a,
+  (q15_t)0x2494, (q15_t)0x248e, (q15_t)0x2488, (q15_t)0x2482, (q15_t)0x247c, (q15_t)0x2476, (q15_t)0x2470, (q15_t)0x246a,
+  (q15_t)0x2464, (q15_t)0x245e, (q15_t)0x2458, (q15_t)0x2452, (q15_t)0x244c, (q15_t)0x2446, (q15_t)0x2440, (q15_t)0x243a,
+  (q15_t)0x2434, (q15_t)0x242e, (q15_t)0x2428, (q15_t)0x2422, (q15_t)0x241c, (q15_t)0x2416, (q15_t)0x2410, (q15_t)0x240a,
+  (q15_t)0x2404, (q15_t)0x23fd, (q15_t)0x23f7, (q15_t)0x23f1, (q15_t)0x23eb, (q15_t)0x23e5, (q15_t)0x23df, (q15_t)0x23d9,
+  (q15_t)0x23d3, (q15_t)0x23cd, (q15_t)0x23c7, (q15_t)0x23c1, (q15_t)0x23bb, (q15_t)0x23b5, (q15_t)0x23af, (q15_t)0x23a9,
+  (q15_t)0x23a3, (q15_t)0x239d, (q15_t)0x2397, (q15_t)0x2391, (q15_t)0x238b, (q15_t)0x2385, (q15_t)0x237f, (q15_t)0x2379,
+  (q15_t)0x2373, (q15_t)0x236d, (q15_t)0x2367, (q15_t)0x2361, (q15_t)0x235b, (q15_t)0x2355, (q15_t)0x234e, (q15_t)0x2348,
+  (q15_t)0x2342, (q15_t)0x233c, (q15_t)0x2336, (q15_t)0x2330, (q15_t)0x232a, (q15_t)0x2324, (q15_t)0x231e, (q15_t)0x2318,
+  (q15_t)0x2312, (q15_t)0x230c, (q15_t)0x2306, (q15_t)0x2300, (q15_t)0x22fa, (q15_t)0x22f4, (q15_t)0x22ee, (q15_t)0x22e8,
+  (q15_t)0x22e2, (q15_t)0x22dc, (q15_t)0x22d6, (q15_t)0x22d0, (q15_t)0x22ca, (q15_t)0x22c4, (q15_t)0x22bd, (q15_t)0x22b7,
+  (q15_t)0x22b1, (q15_t)0x22ab, (q15_t)0x22a5, (q15_t)0x229f, (q15_t)0x2299, (q15_t)0x2293, (q15_t)0x228d, (q15_t)0x2287,
+  (q15_t)0x2281, (q15_t)0x227b, (q15_t)0x2275, (q15_t)0x226f, (q15_t)0x2269, (q15_t)0x2263, (q15_t)0x225d, (q15_t)0x2257,
+  (q15_t)0x2251, (q15_t)0x224a, (q15_t)0x2244, (q15_t)0x223e, (q15_t)0x2238, (q15_t)0x2232, (q15_t)0x222c, (q15_t)0x2226,
+  (q15_t)0x2220, (q15_t)0x221a, (q15_t)0x2214, (q15_t)0x220e, (q15_t)0x2208, (q15_t)0x2202, (q15_t)0x21fc, (q15_t)0x21f6,
+  (q15_t)0x21f0, (q15_t)0x21ea, (q15_t)0x21e4, (q15_t)0x21dd, (q15_t)0x21d7, (q15_t)0x21d1, (q15_t)0x21cb, (q15_t)0x21c5,
+  (q15_t)0x21bf, (q15_t)0x21b9, (q15_t)0x21b3, (q15_t)0x21ad, (q15_t)0x21a7, (q15_t)0x21a1, (q15_t)0x219b, (q15_t)0x2195,
+  (q15_t)0x218f, (q15_t)0x2189, (q15_t)0x2183, (q15_t)0x217c, (q15_t)0x2176, (q15_t)0x2170, (q15_t)0x216a, (q15_t)0x2164,
+  (q15_t)0x215e, (q15_t)0x2158, (q15_t)0x2152, (q15_t)0x214c, (q15_t)0x2146, (q15_t)0x2140, (q15_t)0x213a, (q15_t)0x2134,
+  (q15_t)0x212e, (q15_t)0x2128, (q15_t)0x2121, (q15_t)0x211b, (q15_t)0x2115, (q15_t)0x210f, (q15_t)0x2109, (q15_t)0x2103,
+  (q15_t)0x20fd, (q15_t)0x20f7, (q15_t)0x20f1, (q15_t)0x20eb, (q15_t)0x20e5, (q15_t)0x20df, (q15_t)0x20d9, (q15_t)0x20d3,
+  (q15_t)0x20cc, (q15_t)0x20c6, (q15_t)0x20c0, (q15_t)0x20ba, (q15_t)0x20b4, (q15_t)0x20ae, (q15_t)0x20a8, (q15_t)0x20a2,
+  (q15_t)0x209c, (q15_t)0x2096, (q15_t)0x2090, (q15_t)0x208a, (q15_t)0x2084, (q15_t)0x207e, (q15_t)0x2077, (q15_t)0x2071,
+  (q15_t)0x206b, (q15_t)0x2065, (q15_t)0x205f, (q15_t)0x2059, (q15_t)0x2053, (q15_t)0x204d, (q15_t)0x2047, (q15_t)0x2041,
+  (q15_t)0x203b, (q15_t)0x2035, (q15_t)0x202e, (q15_t)0x2028, (q15_t)0x2022, (q15_t)0x201c, (q15_t)0x2016, (q15_t)0x2010,
+  (q15_t)0x200a, (q15_t)0x2004, (q15_t)0x1ffe, (q15_t)0x1ff8, (q15_t)0x1ff2, (q15_t)0x1fec, (q15_t)0x1fe5, (q15_t)0x1fdf,
+  (q15_t)0x1fd9, (q15_t)0x1fd3, (q15_t)0x1fcd, (q15_t)0x1fc7, (q15_t)0x1fc1, (q15_t)0x1fbb, (q15_t)0x1fb5, (q15_t)0x1faf,
+  (q15_t)0x1fa9, (q15_t)0x1fa3, (q15_t)0x1f9c, (q15_t)0x1f96, (q15_t)0x1f90, (q15_t)0x1f8a, (q15_t)0x1f84, (q15_t)0x1f7e,
+  (q15_t)0x1f78, (q15_t)0x1f72, (q15_t)0x1f6c, (q15_t)0x1f66, (q15_t)0x1f60, (q15_t)0x1f59, (q15_t)0x1f53, (q15_t)0x1f4d,
+  (q15_t)0x1f47, (q15_t)0x1f41, (q15_t)0x1f3b, (q15_t)0x1f35, (q15_t)0x1f2f, (q15_t)0x1f29, (q15_t)0x1f23, (q15_t)0x1f1d,
+  (q15_t)0x1f16, (q15_t)0x1f10, (q15_t)0x1f0a, (q15_t)0x1f04, (q15_t)0x1efe, (q15_t)0x1ef8, (q15_t)0x1ef2, (q15_t)0x1eec,
+  (q15_t)0x1ee6, (q15_t)0x1ee0, (q15_t)0x1ed9, (q15_t)0x1ed3, (q15_t)0x1ecd, (q15_t)0x1ec7, (q15_t)0x1ec1, (q15_t)0x1ebb,
+  (q15_t)0x1eb5, (q15_t)0x1eaf, (q15_t)0x1ea9, (q15_t)0x1ea3, (q15_t)0x1e9c, (q15_t)0x1e96, (q15_t)0x1e90, (q15_t)0x1e8a,
+  (q15_t)0x1e84, (q15_t)0x1e7e, (q15_t)0x1e78, (q15_t)0x1e72, (q15_t)0x1e6c, (q15_t)0x1e66, (q15_t)0x1e5f, (q15_t)0x1e59,
+  (q15_t)0x1e53, (q15_t)0x1e4d, (q15_t)0x1e47, (q15_t)0x1e41, (q15_t)0x1e3b, (q15_t)0x1e35, (q15_t)0x1e2f, (q15_t)0x1e29,
+  (q15_t)0x1e22, (q15_t)0x1e1c, (q15_t)0x1e16, (q15_t)0x1e10, (q15_t)0x1e0a, (q15_t)0x1e04, (q15_t)0x1dfe, (q15_t)0x1df8,
+  (q15_t)0x1df2, (q15_t)0x1deb, (q15_t)0x1de5, (q15_t)0x1ddf, (q15_t)0x1dd9, (q15_t)0x1dd3, (q15_t)0x1dcd, (q15_t)0x1dc7,
+  (q15_t)0x1dc1, (q15_t)0x1dbb, (q15_t)0x1db4, (q15_t)0x1dae, (q15_t)0x1da8, (q15_t)0x1da2, (q15_t)0x1d9c, (q15_t)0x1d96,
+  (q15_t)0x1d90, (q15_t)0x1d8a, (q15_t)0x1d84, (q15_t)0x1d7d, (q15_t)0x1d77, (q15_t)0x1d71, (q15_t)0x1d6b, (q15_t)0x1d65,
+  (q15_t)0x1d5f, (q15_t)0x1d59, (q15_t)0x1d53, (q15_t)0x1d4c, (q15_t)0x1d46, (q15_t)0x1d40, (q15_t)0x1d3a, (q15_t)0x1d34,
+  (q15_t)0x1d2e, (q15_t)0x1d28, (q15_t)0x1d22, (q15_t)0x1d1c, (q15_t)0x1d15, (q15_t)0x1d0f, (q15_t)0x1d09, (q15_t)0x1d03,
+  (q15_t)0x1cfd, (q15_t)0x1cf7, (q15_t)0x1cf1, (q15_t)0x1ceb, (q15_t)0x1ce4, (q15_t)0x1cde, (q15_t)0x1cd8, (q15_t)0x1cd2,
+  (q15_t)0x1ccc, (q15_t)0x1cc6, (q15_t)0x1cc0, (q15_t)0x1cba, (q15_t)0x1cb3, (q15_t)0x1cad, (q15_t)0x1ca7, (q15_t)0x1ca1,
+  (q15_t)0x1c9b, (q15_t)0x1c95, (q15_t)0x1c8f, (q15_t)0x1c89, (q15_t)0x1c83, (q15_t)0x1c7c, (q15_t)0x1c76, (q15_t)0x1c70,
+  (q15_t)0x1c6a, (q15_t)0x1c64, (q15_t)0x1c5e, (q15_t)0x1c58, (q15_t)0x1c51, (q15_t)0x1c4b, (q15_t)0x1c45, (q15_t)0x1c3f,
+  (q15_t)0x1c39, (q15_t)0x1c33, (q15_t)0x1c2d, (q15_t)0x1c27, (q15_t)0x1c20, (q15_t)0x1c1a, (q15_t)0x1c14, (q15_t)0x1c0e,
+  (q15_t)0x1c08, (q15_t)0x1c02, (q15_t)0x1bfc, (q15_t)0x1bf6, (q15_t)0x1bef, (q15_t)0x1be9, (q15_t)0x1be3, (q15_t)0x1bdd,
+  (q15_t)0x1bd7, (q15_t)0x1bd1, (q15_t)0x1bcb, (q15_t)0x1bc4, (q15_t)0x1bbe, (q15_t)0x1bb8, (q15_t)0x1bb2, (q15_t)0x1bac,
+  (q15_t)0x1ba6, (q15_t)0x1ba0, (q15_t)0x1b9a, (q15_t)0x1b93, (q15_t)0x1b8d, (q15_t)0x1b87, (q15_t)0x1b81, (q15_t)0x1b7b,
+  (q15_t)0x1b75, (q15_t)0x1b6f, (q15_t)0x1b68, (q15_t)0x1b62, (q15_t)0x1b5c, (q15_t)0x1b56, (q15_t)0x1b50, (q15_t)0x1b4a,
+  (q15_t)0x1b44, (q15_t)0x1b3d, (q15_t)0x1b37, (q15_t)0x1b31, (q15_t)0x1b2b, (q15_t)0x1b25, (q15_t)0x1b1f, (q15_t)0x1b19,
+  (q15_t)0x1b13, (q15_t)0x1b0c, (q15_t)0x1b06, (q15_t)0x1b00, (q15_t)0x1afa, (q15_t)0x1af4, (q15_t)0x1aee, (q15_t)0x1ae8,
+  (q15_t)0x1ae1, (q15_t)0x1adb, (q15_t)0x1ad5, (q15_t)0x1acf, (q15_t)0x1ac9, (q15_t)0x1ac3, (q15_t)0x1abd, (q15_t)0x1ab6,
+  (q15_t)0x1ab0, (q15_t)0x1aaa, (q15_t)0x1aa4, (q15_t)0x1a9e, (q15_t)0x1a98, (q15_t)0x1a91, (q15_t)0x1a8b, (q15_t)0x1a85,
+  (q15_t)0x1a7f, (q15_t)0x1a79, (q15_t)0x1a73, (q15_t)0x1a6d, (q15_t)0x1a66, (q15_t)0x1a60, (q15_t)0x1a5a, (q15_t)0x1a54,
+  (q15_t)0x1a4e, (q15_t)0x1a48, (q15_t)0x1a42, (q15_t)0x1a3b, (q15_t)0x1a35, (q15_t)0x1a2f, (q15_t)0x1a29, (q15_t)0x1a23,
+  (q15_t)0x1a1d, (q15_t)0x1a17, (q15_t)0x1a10, (q15_t)0x1a0a, (q15_t)0x1a04, (q15_t)0x19fe, (q15_t)0x19f8, (q15_t)0x19f2,
+  (q15_t)0x19eb, (q15_t)0x19e5, (q15_t)0x19df, (q15_t)0x19d9, (q15_t)0x19d3, (q15_t)0x19cd, (q15_t)0x19c7, (q15_t)0x19c0,
+  (q15_t)0x19ba, (q15_t)0x19b4, (q15_t)0x19ae, (q15_t)0x19a8, (q15_t)0x19a2, (q15_t)0x199b, (q15_t)0x1995, (q15_t)0x198f,
+  (q15_t)0x1989, (q15_t)0x1983, (q15_t)0x197d, (q15_t)0x1977, (q15_t)0x1970, (q15_t)0x196a, (q15_t)0x1964, (q15_t)0x195e,
+  (q15_t)0x1958, (q15_t)0x1952, (q15_t)0x194b, (q15_t)0x1945, (q15_t)0x193f, (q15_t)0x1939, (q15_t)0x1933, (q15_t)0x192d,
+  (q15_t)0x1926, (q15_t)0x1920, (q15_t)0x191a, (q15_t)0x1914, (q15_t)0x190e, (q15_t)0x1908, (q15_t)0x1901, (q15_t)0x18fb,
+  (q15_t)0x18f5, (q15_t)0x18ef, (q15_t)0x18e9, (q15_t)0x18e3, (q15_t)0x18dc, (q15_t)0x18d6, (q15_t)0x18d0, (q15_t)0x18ca,
+  (q15_t)0x18c4, (q15_t)0x18be, (q15_t)0x18b8, (q15_t)0x18b1, (q15_t)0x18ab, (q15_t)0x18a5, (q15_t)0x189f, (q15_t)0x1899,
+  (q15_t)0x1893, (q15_t)0x188c, (q15_t)0x1886, (q15_t)0x1880, (q15_t)0x187a, (q15_t)0x1874, (q15_t)0x186e, (q15_t)0x1867,
+  (q15_t)0x1861, (q15_t)0x185b, (q15_t)0x1855, (q15_t)0x184f, (q15_t)0x1848, (q15_t)0x1842, (q15_t)0x183c, (q15_t)0x1836,
+  (q15_t)0x1830, (q15_t)0x182a, (q15_t)0x1823, (q15_t)0x181d, (q15_t)0x1817, (q15_t)0x1811, (q15_t)0x180b, (q15_t)0x1805,
+  (q15_t)0x17fe, (q15_t)0x17f8, (q15_t)0x17f2, (q15_t)0x17ec, (q15_t)0x17e6, (q15_t)0x17e0, (q15_t)0x17d9, (q15_t)0x17d3,
+  (q15_t)0x17cd, (q15_t)0x17c7, (q15_t)0x17c1, (q15_t)0x17bb, (q15_t)0x17b4, (q15_t)0x17ae, (q15_t)0x17a8, (q15_t)0x17a2,
+  (q15_t)0x179c, (q15_t)0x1795, (q15_t)0x178f, (q15_t)0x1789, (q15_t)0x1783, (q15_t)0x177d, (q15_t)0x1777, (q15_t)0x1770,
+  (q15_t)0x176a, (q15_t)0x1764, (q15_t)0x175e, (q15_t)0x1758, (q15_t)0x1752, (q15_t)0x174b, (q15_t)0x1745, (q15_t)0x173f,
+  (q15_t)0x1739, (q15_t)0x1733, (q15_t)0x172c, (q15_t)0x1726, (q15_t)0x1720, (q15_t)0x171a, (q15_t)0x1714, (q15_t)0x170e,
+  (q15_t)0x1707, (q15_t)0x1701, (q15_t)0x16fb, (q15_t)0x16f5, (q15_t)0x16ef, (q15_t)0x16e8, (q15_t)0x16e2, (q15_t)0x16dc,
+  (q15_t)0x16d6, (q15_t)0x16d0, (q15_t)0x16ca, (q15_t)0x16c3, (q15_t)0x16bd, (q15_t)0x16b7, (q15_t)0x16b1, (q15_t)0x16ab,
+  (q15_t)0x16a4, (q15_t)0x169e, (q15_t)0x1698, (q15_t)0x1692, (q15_t)0x168c, (q15_t)0x1686, (q15_t)0x167f, (q15_t)0x1679,
+  (q15_t)0x1673, (q15_t)0x166d, (q15_t)0x1667, (q15_t)0x1660, (q15_t)0x165a, (q15_t)0x1654, (q15_t)0x164e, (q15_t)0x1648,
+  (q15_t)0x1642, (q15_t)0x163b, (q15_t)0x1635, (q15_t)0x162f, (q15_t)0x1629, (q15_t)0x1623, (q15_t)0x161c, (q15_t)0x1616,
+  (q15_t)0x1610, (q15_t)0x160a, (q15_t)0x1604, (q15_t)0x15fd, (q15_t)0x15f7, (q15_t)0x15f1, (q15_t)0x15eb, (q15_t)0x15e5,
+  (q15_t)0x15de, (q15_t)0x15d8, (q15_t)0x15d2, (q15_t)0x15cc, (q15_t)0x15c6, (q15_t)0x15c0, (q15_t)0x15b9, (q15_t)0x15b3,
+  (q15_t)0x15ad, (q15_t)0x15a7, (q15_t)0x15a1, (q15_t)0x159a, (q15_t)0x1594, (q15_t)0x158e, (q15_t)0x1588, (q15_t)0x1582,
+  (q15_t)0x157b, (q15_t)0x1575, (q15_t)0x156f, (q15_t)0x1569, (q15_t)0x1563, (q15_t)0x155c, (q15_t)0x1556, (q15_t)0x1550,
+  (q15_t)0x154a, (q15_t)0x1544, (q15_t)0x153d, (q15_t)0x1537, (q15_t)0x1531, (q15_t)0x152b, (q15_t)0x1525, (q15_t)0x151e,
+  (q15_t)0x1518, (q15_t)0x1512, (q15_t)0x150c, (q15_t)0x1506, (q15_t)0x14ff, (q15_t)0x14f9, (q15_t)0x14f3, (q15_t)0x14ed,
+  (q15_t)0x14e7, (q15_t)0x14e0, (q15_t)0x14da, (q15_t)0x14d4, (q15_t)0x14ce, (q15_t)0x14c8, (q15_t)0x14c1, (q15_t)0x14bb,
+  (q15_t)0x14b5, (q15_t)0x14af, (q15_t)0x14a9, (q15_t)0x14a2, (q15_t)0x149c, (q15_t)0x1496, (q15_t)0x1490, (q15_t)0x148a,
+  (q15_t)0x1483, (q15_t)0x147d, (q15_t)0x1477, (q15_t)0x1471, (q15_t)0x146b, (q15_t)0x1464, (q15_t)0x145e, (q15_t)0x1458,
+  (q15_t)0x1452, (q15_t)0x144c, (q15_t)0x1445, (q15_t)0x143f, (q15_t)0x1439, (q15_t)0x1433, (q15_t)0x142d, (q15_t)0x1426,
+  (q15_t)0x1420, (q15_t)0x141a, (q15_t)0x1414, (q15_t)0x140e, (q15_t)0x1407, (q15_t)0x1401, (q15_t)0x13fb, (q15_t)0x13f5,
+  (q15_t)0x13ef, (q15_t)0x13e8, (q15_t)0x13e2, (q15_t)0x13dc, (q15_t)0x13d6, (q15_t)0x13d0, (q15_t)0x13c9, (q15_t)0x13c3,
+  (q15_t)0x13bd, (q15_t)0x13b7, (q15_t)0x13b1, (q15_t)0x13aa, (q15_t)0x13a4, (q15_t)0x139e, (q15_t)0x1398, (q15_t)0x1391,
+  (q15_t)0x138b, (q15_t)0x1385, (q15_t)0x137f, (q15_t)0x1379, (q15_t)0x1372, (q15_t)0x136c, (q15_t)0x1366, (q15_t)0x1360,
+  (q15_t)0x135a, (q15_t)0x1353, (q15_t)0x134d, (q15_t)0x1347, (q15_t)0x1341, (q15_t)0x133b, (q15_t)0x1334, (q15_t)0x132e,
+  (q15_t)0x1328, (q15_t)0x1322, (q15_t)0x131b, (q15_t)0x1315, (q15_t)0x130f, (q15_t)0x1309, (q15_t)0x1303, (q15_t)0x12fc,
+  (q15_t)0x12f6, (q15_t)0x12f0, (q15_t)0x12ea, (q15_t)0x12e4, (q15_t)0x12dd, (q15_t)0x12d7, (q15_t)0x12d1, (q15_t)0x12cb,
+  (q15_t)0x12c4, (q15_t)0x12be, (q15_t)0x12b8, (q15_t)0x12b2, (q15_t)0x12ac, (q15_t)0x12a5, (q15_t)0x129f, (q15_t)0x1299,
+  (q15_t)0x1293, (q15_t)0x128d, (q15_t)0x1286, (q15_t)0x1280, (q15_t)0x127a, (q15_t)0x1274, (q15_t)0x126d, (q15_t)0x1267,
+  (q15_t)0x1261, (q15_t)0x125b, (q15_t)0x1255, (q15_t)0x124e, (q15_t)0x1248, (q15_t)0x1242, (q15_t)0x123c, (q15_t)0x1235,
+  (q15_t)0x122f, (q15_t)0x1229, (q15_t)0x1223, (q15_t)0x121d, (q15_t)0x1216, (q15_t)0x1210, (q15_t)0x120a, (q15_t)0x1204,
+  (q15_t)0x11fd, (q15_t)0x11f7, (q15_t)0x11f1, (q15_t)0x11eb, (q15_t)0x11e5, (q15_t)0x11de, (q15_t)0x11d8, (q15_t)0x11d2,
+  (q15_t)0x11cc, (q15_t)0x11c5, (q15_t)0x11bf, (q15_t)0x11b9, (q15_t)0x11b3, (q15_t)0x11ad, (q15_t)0x11a6, (q15_t)0x11a0,
+  (q15_t)0x119a, (q15_t)0x1194, (q15_t)0x118d, (q15_t)0x1187, (q15_t)0x1181, (q15_t)0x117b, (q15_t)0x1175, (q15_t)0x116e,
+  (q15_t)0x1168, (q15_t)0x1162, (q15_t)0x115c, (q15_t)0x1155, (q15_t)0x114f, (q15_t)0x1149, (q15_t)0x1143, (q15_t)0x113d,
+  (q15_t)0x1136, (q15_t)0x1130, (q15_t)0x112a, (q15_t)0x1124, (q15_t)0x111d, (q15_t)0x1117, (q15_t)0x1111, (q15_t)0x110b,
+  (q15_t)0x1105, (q15_t)0x10fe, (q15_t)0x10f8, (q15_t)0x10f2, (q15_t)0x10ec, (q15_t)0x10e5, (q15_t)0x10df, (q15_t)0x10d9,
+  (q15_t)0x10d3, (q15_t)0x10cc, (q15_t)0x10c6, (q15_t)0x10c0, (q15_t)0x10ba, (q15_t)0x10b4, (q15_t)0x10ad, (q15_t)0x10a7,
+  (q15_t)0x10a1, (q15_t)0x109b, (q15_t)0x1094, (q15_t)0x108e, (q15_t)0x1088, (q15_t)0x1082, (q15_t)0x107b, (q15_t)0x1075,
+  (q15_t)0x106f, (q15_t)0x1069, (q15_t)0x1063, (q15_t)0x105c, (q15_t)0x1056, (q15_t)0x1050, (q15_t)0x104a, (q15_t)0x1043,
+  (q15_t)0x103d, (q15_t)0x1037, (q15_t)0x1031, (q15_t)0x102a, (q15_t)0x1024, (q15_t)0x101e, (q15_t)0x1018, (q15_t)0x1012,
+  (q15_t)0x100b, (q15_t)0x1005, (q15_t)0xfff, (q15_t)0xff9, (q15_t)0xff2, (q15_t)0xfec, (q15_t)0xfe6, (q15_t)0xfe0,
+  (q15_t)0xfd9, (q15_t)0xfd3, (q15_t)0xfcd, (q15_t)0xfc7, (q15_t)0xfc0, (q15_t)0xfba, (q15_t)0xfb4, (q15_t)0xfae,
+  (q15_t)0xfa8, (q15_t)0xfa1, (q15_t)0xf9b, (q15_t)0xf95, (q15_t)0xf8f, (q15_t)0xf88, (q15_t)0xf82, (q15_t)0xf7c,
+  (q15_t)0xf76, (q15_t)0xf6f, (q15_t)0xf69, (q15_t)0xf63, (q15_t)0xf5d, (q15_t)0xf56, (q15_t)0xf50, (q15_t)0xf4a,
+  (q15_t)0xf44, (q15_t)0xf3e, (q15_t)0xf37, (q15_t)0xf31, (q15_t)0xf2b, (q15_t)0xf25, (q15_t)0xf1e, (q15_t)0xf18,
+  (q15_t)0xf12, (q15_t)0xf0c, (q15_t)0xf05, (q15_t)0xeff, (q15_t)0xef9, (q15_t)0xef3, (q15_t)0xeec, (q15_t)0xee6,
+  (q15_t)0xee0, (q15_t)0xeda, (q15_t)0xed3, (q15_t)0xecd, (q15_t)0xec7, (q15_t)0xec1, (q15_t)0xeba, (q15_t)0xeb4,
+  (q15_t)0xeae, (q15_t)0xea8, (q15_t)0xea1, (q15_t)0xe9b, (q15_t)0xe95, (q15_t)0xe8f, (q15_t)0xe89, (q15_t)0xe82,
+  (q15_t)0xe7c, (q15_t)0xe76, (q15_t)0xe70, (q15_t)0xe69, (q15_t)0xe63, (q15_t)0xe5d, (q15_t)0xe57, (q15_t)0xe50,
+  (q15_t)0xe4a, (q15_t)0xe44, (q15_t)0xe3e, (q15_t)0xe37, (q15_t)0xe31, (q15_t)0xe2b, (q15_t)0xe25, (q15_t)0xe1e,
+  (q15_t)0xe18, (q15_t)0xe12, (q15_t)0xe0c, (q15_t)0xe05, (q15_t)0xdff, (q15_t)0xdf9, (q15_t)0xdf3, (q15_t)0xdec,
+  (q15_t)0xde6, (q15_t)0xde0, (q15_t)0xdda, (q15_t)0xdd3, (q15_t)0xdcd, (q15_t)0xdc7, (q15_t)0xdc1, (q15_t)0xdba,
+  (q15_t)0xdb4, (q15_t)0xdae, (q15_t)0xda8, (q15_t)0xda1, (q15_t)0xd9b, (q15_t)0xd95, (q15_t)0xd8f, (q15_t)0xd88,
+  (q15_t)0xd82, (q15_t)0xd7c, (q15_t)0xd76, (q15_t)0xd6f, (q15_t)0xd69, (q15_t)0xd63, (q15_t)0xd5d, (q15_t)0xd56,
+  (q15_t)0xd50, (q15_t)0xd4a, (q15_t)0xd44, (q15_t)0xd3d, (q15_t)0xd37, (q15_t)0xd31, (q15_t)0xd2b, (q15_t)0xd24,
+  (q15_t)0xd1e, (q15_t)0xd18, (q15_t)0xd12, (q15_t)0xd0b, (q15_t)0xd05, (q15_t)0xcff, (q15_t)0xcf9, (q15_t)0xcf2,
+  (q15_t)0xcec, (q15_t)0xce6, (q15_t)0xce0, (q15_t)0xcd9, (q15_t)0xcd3, (q15_t)0xccd, (q15_t)0xcc7, (q15_t)0xcc0,
+  (q15_t)0xcba, (q15_t)0xcb4, (q15_t)0xcae, (q15_t)0xca7, (q15_t)0xca1, (q15_t)0xc9b, (q15_t)0xc95, (q15_t)0xc8e,
+  (q15_t)0xc88, (q15_t)0xc82, (q15_t)0xc7c, (q15_t)0xc75, (q15_t)0xc6f, (q15_t)0xc69, (q15_t)0xc63, (q15_t)0xc5c,
+  (q15_t)0xc56, (q15_t)0xc50, (q15_t)0xc4a, (q15_t)0xc43, (q15_t)0xc3d, (q15_t)0xc37, (q15_t)0xc31, (q15_t)0xc2a,
+  (q15_t)0xc24, (q15_t)0xc1e, (q15_t)0xc18, (q15_t)0xc11, (q15_t)0xc0b, (q15_t)0xc05, (q15_t)0xbff, (q15_t)0xbf8,
+  (q15_t)0xbf2, (q15_t)0xbec, (q15_t)0xbe6, (q15_t)0xbdf, (q15_t)0xbd9, (q15_t)0xbd3, (q15_t)0xbcd, (q15_t)0xbc6,
+  (q15_t)0xbc0, (q15_t)0xbba, (q15_t)0xbb4, (q15_t)0xbad, (q15_t)0xba7, (q15_t)0xba1, (q15_t)0xb9b, (q15_t)0xb94,
+  (q15_t)0xb8e, (q15_t)0xb88, (q15_t)0xb81, (q15_t)0xb7b, (q15_t)0xb75, (q15_t)0xb6f, (q15_t)0xb68, (q15_t)0xb62,
+  (q15_t)0xb5c, (q15_t)0xb56, (q15_t)0xb4f, (q15_t)0xb49, (q15_t)0xb43, (q15_t)0xb3d, (q15_t)0xb36, (q15_t)0xb30,
+  (q15_t)0xb2a, (q15_t)0xb24, (q15_t)0xb1d, (q15_t)0xb17, (q15_t)0xb11, (q15_t)0xb0b, (q15_t)0xb04, (q15_t)0xafe,
+  (q15_t)0xaf8, (q15_t)0xaf2, (q15_t)0xaeb, (q15_t)0xae5, (q15_t)0xadf, (q15_t)0xad8, (q15_t)0xad2, (q15_t)0xacc,
+  (q15_t)0xac6, (q15_t)0xabf, (q15_t)0xab9, (q15_t)0xab3, (q15_t)0xaad, (q15_t)0xaa6, (q15_t)0xaa0, (q15_t)0xa9a,
+  (q15_t)0xa94, (q15_t)0xa8d, (q15_t)0xa87, (q15_t)0xa81, (q15_t)0xa7b, (q15_t)0xa74, (q15_t)0xa6e, (q15_t)0xa68,
+  (q15_t)0xa62, (q15_t)0xa5b, (q15_t)0xa55, (q15_t)0xa4f, (q15_t)0xa48, (q15_t)0xa42, (q15_t)0xa3c, (q15_t)0xa36,
+  (q15_t)0xa2f, (q15_t)0xa29, (q15_t)0xa23, (q15_t)0xa1d, (q15_t)0xa16, (q15_t)0xa10, (q15_t)0xa0a, (q15_t)0xa04,
+  (q15_t)0x9fd, (q15_t)0x9f7, (q15_t)0x9f1, (q15_t)0x9eb, (q15_t)0x9e4, (q15_t)0x9de, (q15_t)0x9d8, (q15_t)0x9d1,
+  (q15_t)0x9cb, (q15_t)0x9c5, (q15_t)0x9bf, (q15_t)0x9b8, (q15_t)0x9b2, (q15_t)0x9ac, (q15_t)0x9a6, (q15_t)0x99f,
+  (q15_t)0x999, (q15_t)0x993, (q15_t)0x98d, (q15_t)0x986, (q15_t)0x980, (q15_t)0x97a, (q15_t)0x973, (q15_t)0x96d,
+  (q15_t)0x967, (q15_t)0x961, (q15_t)0x95a, (q15_t)0x954, (q15_t)0x94e, (q15_t)0x948, (q15_t)0x941, (q15_t)0x93b,
+  (q15_t)0x935, (q15_t)0x92f, (q15_t)0x928, (q15_t)0x922, (q15_t)0x91c, (q15_t)0x915, (q15_t)0x90f, (q15_t)0x909,
+  (q15_t)0x903, (q15_t)0x8fc, (q15_t)0x8f6, (q15_t)0x8f0, (q15_t)0x8ea, (q15_t)0x8e3, (q15_t)0x8dd, (q15_t)0x8d7,
+  (q15_t)0x8d1, (q15_t)0x8ca, (q15_t)0x8c4, (q15_t)0x8be, (q15_t)0x8b7, (q15_t)0x8b1, (q15_t)0x8ab, (q15_t)0x8a5,
+  (q15_t)0x89e, (q15_t)0x898, (q15_t)0x892, (q15_t)0x88c, (q15_t)0x885, (q15_t)0x87f, (q15_t)0x879, (q15_t)0x872,
+  (q15_t)0x86c, (q15_t)0x866, (q15_t)0x860, (q15_t)0x859, (q15_t)0x853, (q15_t)0x84d, (q15_t)0x847, (q15_t)0x840,
+  (q15_t)0x83a, (q15_t)0x834, (q15_t)0x82e, (q15_t)0x827, (q15_t)0x821, (q15_t)0x81b, (q15_t)0x814, (q15_t)0x80e,
+  (q15_t)0x808, (q15_t)0x802, (q15_t)0x7fb, (q15_t)0x7f5, (q15_t)0x7ef, (q15_t)0x7e9, (q15_t)0x7e2, (q15_t)0x7dc,
+  (q15_t)0x7d6, (q15_t)0x7cf, (q15_t)0x7c9, (q15_t)0x7c3, (q15_t)0x7bd, (q15_t)0x7b6, (q15_t)0x7b0, (q15_t)0x7aa,
+  (q15_t)0x7a4, (q15_t)0x79d, (q15_t)0x797, (q15_t)0x791, (q15_t)0x78a, (q15_t)0x784, (q15_t)0x77e, (q15_t)0x778,
+  (q15_t)0x771, (q15_t)0x76b, (q15_t)0x765, (q15_t)0x75f, (q15_t)0x758, (q15_t)0x752, (q15_t)0x74c, (q15_t)0x745,
+  (q15_t)0x73f, (q15_t)0x739, (q15_t)0x733, (q15_t)0x72c, (q15_t)0x726, (q15_t)0x720, (q15_t)0x71a, (q15_t)0x713,
+  (q15_t)0x70d, (q15_t)0x707, (q15_t)0x700, (q15_t)0x6fa, (q15_t)0x6f4, (q15_t)0x6ee, (q15_t)0x6e7, (q15_t)0x6e1,
+  (q15_t)0x6db, (q15_t)0x6d5, (q15_t)0x6ce, (q15_t)0x6c8, (q15_t)0x6c2, (q15_t)0x6bb, (q15_t)0x6b5, (q15_t)0x6af,
+  (q15_t)0x6a9, (q15_t)0x6a2, (q15_t)0x69c, (q15_t)0x696, (q15_t)0x690, (q15_t)0x689, (q15_t)0x683, (q15_t)0x67d,
+  (q15_t)0x676, (q15_t)0x670, (q15_t)0x66a, (q15_t)0x664, (q15_t)0x65d, (q15_t)0x657, (q15_t)0x651, (q15_t)0x64a,
+  (q15_t)0x644, (q15_t)0x63e, (q15_t)0x638, (q15_t)0x631, (q15_t)0x62b, (q15_t)0x625, (q15_t)0x61f, (q15_t)0x618,
+  (q15_t)0x612, (q15_t)0x60c, (q15_t)0x605, (q15_t)0x5ff, (q15_t)0x5f9, (q15_t)0x5f3, (q15_t)0x5ec, (q15_t)0x5e6,
+  (q15_t)0x5e0, (q15_t)0x5da, (q15_t)0x5d3, (q15_t)0x5cd, (q15_t)0x5c7, (q15_t)0x5c0, (q15_t)0x5ba, (q15_t)0x5b4,
+  (q15_t)0x5ae, (q15_t)0x5a7, (q15_t)0x5a1, (q15_t)0x59b, (q15_t)0x594, (q15_t)0x58e, (q15_t)0x588, (q15_t)0x582,
+  (q15_t)0x57b, (q15_t)0x575, (q15_t)0x56f, (q15_t)0x569, (q15_t)0x562, (q15_t)0x55c, (q15_t)0x556, (q15_t)0x54f,
+  (q15_t)0x549, (q15_t)0x543, (q15_t)0x53d, (q15_t)0x536, (q15_t)0x530, (q15_t)0x52a, (q15_t)0x523, (q15_t)0x51d,
+  (q15_t)0x517, (q15_t)0x511, (q15_t)0x50a, (q15_t)0x504, (q15_t)0x4fe, (q15_t)0x4f8, (q15_t)0x4f1, (q15_t)0x4eb,
+  (q15_t)0x4e5, (q15_t)0x4de, (q15_t)0x4d8, (q15_t)0x4d2, (q15_t)0x4cc, (q15_t)0x4c5, (q15_t)0x4bf, (q15_t)0x4b9,
+  (q15_t)0x4b2, (q15_t)0x4ac, (q15_t)0x4a6, (q15_t)0x4a0, (q15_t)0x499, (q15_t)0x493, (q15_t)0x48d, (q15_t)0x487,
+  (q15_t)0x480, (q15_t)0x47a, (q15_t)0x474, (q15_t)0x46d, (q15_t)0x467, (q15_t)0x461, (q15_t)0x45b, (q15_t)0x454,
+  (q15_t)0x44e, (q15_t)0x448, (q15_t)0x441, (q15_t)0x43b, (q15_t)0x435, (q15_t)0x42f, (q15_t)0x428, (q15_t)0x422,
+  (q15_t)0x41c, (q15_t)0x415, (q15_t)0x40f, (q15_t)0x409, (q15_t)0x403, (q15_t)0x3fc, (q15_t)0x3f6, (q15_t)0x3f0,
+  (q15_t)0x3ea, (q15_t)0x3e3, (q15_t)0x3dd, (q15_t)0x3d7, (q15_t)0x3d0, (q15_t)0x3ca, (q15_t)0x3c4, (q15_t)0x3be,
+  (q15_t)0x3b7, (q15_t)0x3b1, (q15_t)0x3ab, (q15_t)0x3a4, (q15_t)0x39e, (q15_t)0x398, (q15_t)0x392, (q15_t)0x38b,
+  (q15_t)0x385, (q15_t)0x37f, (q15_t)0x378, (q15_t)0x372, (q15_t)0x36c, (q15_t)0x366, (q15_t)0x35f, (q15_t)0x359,
+  (q15_t)0x353, (q15_t)0x34c, (q15_t)0x346, (q15_t)0x340, (q15_t)0x33a, (q15_t)0x333, (q15_t)0x32d, (q15_t)0x327,
+  (q15_t)0x321, (q15_t)0x31a, (q15_t)0x314, (q15_t)0x30e, (q15_t)0x307, (q15_t)0x301, (q15_t)0x2fb, (q15_t)0x2f5,
+  (q15_t)0x2ee, (q15_t)0x2e8, (q15_t)0x2e2, (q15_t)0x2db, (q15_t)0x2d5, (q15_t)0x2cf, (q15_t)0x2c9, (q15_t)0x2c2,
+  (q15_t)0x2bc, (q15_t)0x2b6, (q15_t)0x2af, (q15_t)0x2a9, (q15_t)0x2a3, (q15_t)0x29d, (q15_t)0x296, (q15_t)0x290,
+  (q15_t)0x28a, (q15_t)0x283, (q15_t)0x27d, (q15_t)0x277, (q15_t)0x271, (q15_t)0x26a, (q15_t)0x264, (q15_t)0x25e,
+  (q15_t)0x258, (q15_t)0x251, (q15_t)0x24b, (q15_t)0x245, (q15_t)0x23e, (q15_t)0x238, (q15_t)0x232, (q15_t)0x22c,
+  (q15_t)0x225, (q15_t)0x21f, (q15_t)0x219, (q15_t)0x212, (q15_t)0x20c, (q15_t)0x206, (q15_t)0x200, (q15_t)0x1f9,
+  (q15_t)0x1f3, (q15_t)0x1ed, (q15_t)0x1e6, (q15_t)0x1e0, (q15_t)0x1da, (q15_t)0x1d4, (q15_t)0x1cd, (q15_t)0x1c7,
+  (q15_t)0x1c1, (q15_t)0x1ba, (q15_t)0x1b4, (q15_t)0x1ae, (q15_t)0x1a8, (q15_t)0x1a1, (q15_t)0x19b, (q15_t)0x195,
+  (q15_t)0x18e, (q15_t)0x188, (q15_t)0x182, (q15_t)0x17c, (q15_t)0x175, (q15_t)0x16f, (q15_t)0x169, (q15_t)0x162,
+  (q15_t)0x15c, (q15_t)0x156, (q15_t)0x150, (q15_t)0x149, (q15_t)0x143, (q15_t)0x13d, (q15_t)0x137, (q15_t)0x130,
+  (q15_t)0x12a, (q15_t)0x124, (q15_t)0x11d, (q15_t)0x117, (q15_t)0x111, (q15_t)0x10b, (q15_t)0x104, (q15_t)0xfe,
+  (q15_t)0xf8, (q15_t)0xf1, (q15_t)0xeb, (q15_t)0xe5, (q15_t)0xdf, (q15_t)0xd8, (q15_t)0xd2, (q15_t)0xcc,
+  (q15_t)0xc5, (q15_t)0xbf, (q15_t)0xb9, (q15_t)0xb3, (q15_t)0xac, (q15_t)0xa6, (q15_t)0xa0, (q15_t)0x99,
+  (q15_t)0x93, (q15_t)0x8d, (q15_t)0x87, (q15_t)0x80, (q15_t)0x7a, (q15_t)0x74, (q15_t)0x6d, (q15_t)0x67,
+  (q15_t)0x61, (q15_t)0x5b, (q15_t)0x54, (q15_t)0x4e, (q15_t)0x48, (q15_t)0x41, (q15_t)0x3b, (q15_t)0x35,
+  (q15_t)0x2f, (q15_t)0x28, (q15_t)0x22, (q15_t)0x1c, (q15_t)0x15, (q15_t)0xf, (q15_t)0x9, (q15_t)0x3
+};
+
+/**
+ * @} end of DCT4_IDCT4_Table group
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return  	  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.
+ * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingQ15Table.gif
+ */
+
+arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q15_t *twiddlePtr[4] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
+    (q15_t *) WeightsQ15_2048, (q15_t *) WeightsQ15_8192
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q15_t *pCosFactor[4] =
+    { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
+    (q15_t *) cos_factorsQ15_2048, (q15_t *) cos_factorsQ15_8192
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 8192U:
+    S->pTwiddle = twiddlePtr[3];
+    S->pCosFactor = pCosFactor[3];
+    break;
+  case 2048U:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512U:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128U:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_q15(S->pRfft, S->N, 0U, 1U);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c
new file mode 100644
index 0000000..5873a33
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c
@@ -0,0 +1,7686 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_dct4_init_q31.c
+ * Description:  Initialization function of DCT-4 & IDCT4 Q31
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup DCT4_IDCT4
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4_Table DCT Type IV Tables
+ * @{
+ */
+
+/*
+* @brief  Weights Table
+*/
+
+/**
+ * \par
+ * Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))

+ * \par
+ * C command to generate the table
+ * 
+ * for(i = 0; i< N; i++)
+ * {
+ *   weights[2*i]= cos(i*c);
+ *   weights[(2*i)+1]= -sin(i * c);
+ * } 

+ * \par
+ * where N is the Number of weights to be calculated and c is pi/(2*N)
+ * \par
+ * Convert the output to q31 format by multiplying with 2^31 and saturated if required.
+ * \par
+ * In the tables below the real and imaginary values are placed alternatively, hence the
+ * array length is 2*N.
+ */
+
+static const q31_t WeightsQ31_128[256] = {
+  (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3,
+  (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f872bf3, (q31_t)0xf50497fb,
+  (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31,
+  (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7dd6668f, (q31_t)0xe8922622,
+  (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7c894bde, (q31_t)0xe26cb01b,
+  (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7aef6323, (q31_t)0xdc597781,
+  (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x7909a92d, (q31_t)0xd65c3b7b,
+  (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x76d94989, (q31_t)0xd078ad9e,
+  (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x745f9dd1, (q31_t)0xcab26fa9,
+  (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x719e2cd2, (q31_t)0xc50d1149,
+  (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3,
+  (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6b4af279, (q31_t)0xba32ca71,
+  (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x67bd0fbd, (q31_t)0xb5049368,
+  (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x63ef3290, (q31_t)0xb0049ab3,
+  (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5,
+  (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5b9d1154, (q31_t)0xa69b9b68,
+  (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x571deefa, (q31_t)0xa2386284,
+  (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x5269126e, (q31_t)0x9e0effc1,
+  (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4d8162c4, (q31_t)0x9a22042d,
+  (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4869e665, (q31_t)0x9673db94,
+  (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4325c135, (q31_t)0x9306cb04,
+  (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3db832a6, (q31_t)0x8fdcef66,
+  (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x382493b0, (q31_t)0x8cf83c30,
+  (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x326e54c7, (q31_t)0x8a5a7a31,
+  (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2c98fbba, (q31_t)0x88054677,
+  (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x26a82186, (q31_t)0x85fa1153,
+  (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x209f701c, (q31_t)0x843a1d70,
+  (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1a82a026, (q31_t)0x82c67f14,
+  (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x145576b1, (q31_t)0x81a01b6d,
+  (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a,
+  (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x7d95b9e, (q31_t)0x803daa6a,
+  (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x1921d20, (q31_t)0x800277a6
+};
+
+static const q31_t WeightsQ31_512[1024] = {
+  (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f,
+  (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff871a2, (q31_t)0xfd40565c,
+  (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fed5791, (q31_t)0xfbae5e89,
+  (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157,
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+  (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77,
+  (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f434563, (q31_t)0xf2482c8a,
+  (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401,
+  (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7ee34636, (q31_t)0xef29b243,
+  (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eabef2c, (q31_t)0xed9b66b2,
+  (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8,
+  (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a,
+  (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7de8a670, (q31_t)0xe8f50273,
+  (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8,
+  (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d769bb5, (q31_t)0xe6a4b616, (q31_t)0x7d628ac6, (q31_t)0xe642340d, (q31_t)0x7d4e2c7f, (q31_t)0xe5dfc1e5,
+  (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7d24881b, (q31_t)0xe51b0e2a, (q31_t)0x7d0f4218, (q31_t)0xe4b8cd11, (q31_t)0x7cf9aef0, (q31_t)0xe4569ccb,
+  (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7cb72724, (q31_t)0xe330734d, (q31_t)0x7ca05ff1, (q31_t)0xe2ce88b3,
+  (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c71eaf9, (q31_t)0xe20ae9c1, (q31_t)0x7c5a3d50, (q31_t)0xe1a935e2, (q31_t)0x7c4242f2, (q31_t)0xe14794ba,
+  (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7c116853, (q31_t)0xe0848b7f, (q31_t)0x7bf88830, (q31_t)0xe02323e5, (q31_t)0x7bdf5b94, (q31_t)0xdfc1cff3,
+  (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7bac1d31, (q31_t)0xdeff63f4, (q31_t)0x7b920b89, (q31_t)0xde9e4c60, (q31_t)0x7b77ada8, (q31_t)0xde3d4964,
+  (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7b420d7a, (q31_t)0xdd7b8220, (q31_t)0x7b26cb4f, (q31_t)0xdd1abe51, (q31_t)0x7b0b3d2c, (q31_t)0xdcba1008,
+  (q31_t)0x7aef6323, (q31_t)0xdc597781, (q31_t)0x7ad33d45, (q31_t)0xdbf8f4f8, (q31_t)0x7ab6cba4, (q31_t)0xdb9888a8, (q31_t)0x7a9a0e50, (q31_t)0xdb3832cd,
+  (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a5fb0d8, (q31_t)0xda77cb63, (q31_t)0x7a4210d8, (q31_t)0xda17ba4a, (q31_t)0x7a24256f, (q31_t)0xd9b7c094,
+  (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x79e76ca7, (q31_t)0xd8f81439, (q31_t)0x79c89f6e, (q31_t)0xd898620c, (q31_t)0x79a98715, (q31_t)0xd838c82d,
+  (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x796a7554, (q31_t)0xd779de47, (q31_t)0x794a7c12, (q31_t)0xd71a8eb5, (q31_t)0x792a37fe, (q31_t)0xd6bb585e,
+  (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, (q31_t)0x78e8cfb2, (q31_t)0xd5fd3848, (q31_t)0x78c7aba2, (q31_t)0xd59e4eff, (q31_t)0x78a63d11, (q31_t)0xd53f7fda,
+  (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x786280bf, (q31_t)0xd48230e9, (q31_t)0x78403329, (q31_t)0xd423b191, (q31_t)0x781d9b65, (q31_t)0xd3c54d47,
+  (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x77d78daa, (q31_t)0xd308d6c7, (q31_t)0x77b417df, (q31_t)0xd2aac504, (q31_t)0x7790583e, (q31_t)0xd24ccf39,
+  (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x7747fbce, (q31_t)0xd191386e, (q31_t)0x77235f2d, (q31_t)0xd13397e2, (q31_t)0x76fe790e, (q31_t)0xd0d61434,
+  (q31_t)0x76d94989, (q31_t)0xd078ad9e, (q31_t)0x76b3d0b4, (q31_t)0xd01b6459, (q31_t)0x768e0ea6, (q31_t)0xcfbe389f, (q31_t)0x76680376, (q31_t)0xcf612aaa,
+  (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x761b1211, (q31_t)0xcea768f2, (q31_t)0x75f42c0b, (q31_t)0xce4ab5a2, (q31_t)0x75ccfd42, (q31_t)0xcdee20fc,
+  (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x757dc5ca, (q31_t)0xcd355491, (q31_t)0x7555bd4c, (q31_t)0xccd91d3d, (q31_t)0x752d6c6c, (q31_t)0xcc7d0578,
+  (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x74dbf1ef, (q31_t)0xcbc53579, (q31_t)0x74b2c884, (q31_t)0xcb697db0, (q31_t)0x7489571c, (q31_t)0xcb0de658,
+  (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, (q31_t)0x74359cbd, (q31_t)0xca5719db, (q31_t)0x740b53fb, (q31_t)0xc9fbe527, (q31_t)0x73e0c3a3, (q31_t)0xc9a0d1c5,
+  (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x738acc9e, (q31_t)0xc8eb0fd6, (q31_t)0x735f6626, (q31_t)0xc89061ba, (q31_t)0x7333b883, (q31_t)0xc835d5d0,
+  (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72db8828, (q31_t)0xc7812572, (q31_t)0x72af05a7, (q31_t)0xc727016d, (q31_t)0x72823c67, (q31_t)0xc6cd0079,
+  (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x7227d61c, (q31_t)0xc61968a2, (q31_t)0x71fa3949, (q31_t)0xc5bfd22e, (q31_t)0x71cc5626, (q31_t)0xc5665fa9,
+  (q31_t)0x719e2cd2, (q31_t)0xc50d1149, (q31_t)0x716fbd68, (q31_t)0xc4b3e746, (q31_t)0x71410805, (q31_t)0xc45ae1d7, (q31_t)0x71120cc5, (q31_t)0xc4020133,
+  (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x70b34525, (q31_t)0xc350af26, (q31_t)0x708378ff, (q31_t)0xc2f83e2a, (q31_t)0x70536771, (q31_t)0xc29ff2d4,
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+  (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6f2d532c, (q31_t)0xc0915148, (q31_t)0x6efb5f12, (q31_t)0xc03a1368, (q31_t)0x6ec92683, (q31_t)0xbfe2fcdf,
+  (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, (q31_t)0x6e63e87f, (q31_t)0xbf3546a8, (q31_t)0x6e30e34a, (q31_t)0xbedea765, (q31_t)0x6dfd9a1c, (q31_t)0xbe88304f,
+  (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6d963c54, (q31_t)0xbddbbb7f, (q31_t)0x6d6227fa, (q31_t)0xbd85be30, (q31_t)0x6d2dd027, (q31_t)0xbd2fe9e2,
+  (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6cc45698, (q31_t)0xbc84bd1f, (q31_t)0x6c8f351c, (q31_t)0xbc2f6513, (q31_t)0x6c59d0a9, (q31_t)0xbbda36dd,
+  (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6bee3f62, (q31_t)0xbb3058c0, (q31_t)0x6bb812d1, (q31_t)0xbadba943, (q31_t)0x6b81a3cd, (q31_t)0xba87246d,
+  (q31_t)0x6b4af279, (q31_t)0xba32ca71, (q31_t)0x6b13fef5, (q31_t)0xb9de9b83, (q31_t)0x6adcc964, (q31_t)0xb98a97d8, (q31_t)0x6aa551e9, (q31_t)0xb936bfa4,
+  (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x6a359db9, (q31_t)0xb88f926d, (q31_t)0x69fd614a, (q31_t)0xb83c3dd1, (q31_t)0x69c4e37a, (q31_t)0xb7e9157a,
+  (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x69532442, (q31_t)0xb7434a67, (q31_t)0x6919e320, (q31_t)0xb6f0a812, (q31_t)0x68e06129, (q31_t)0xb69e32cd,
+  (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x686c9b4b, (q31_t)0xb5f9d043, (q31_t)0x683257ab, (q31_t)0xb5a7e362, (q31_t)0x67f7d3c5, (q31_t)0xb556245e,
+  (q31_t)0x67bd0fbd, (q31_t)0xb5049368, (q31_t)0x67820bb7, (q31_t)0xb4b330b3, (q31_t)0x6746c7d8, (q31_t)0xb461fc70, (q31_t)0x670b4444, (q31_t)0xb410f6d3,
+  (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x66937e91, (q31_t)0xb36f784f, (q31_t)0x66573cbb, (q31_t)0xb31effcc, (q31_t)0x661abbc5, (q31_t)0xb2ceb6b5,
+  (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x65a0fd0b, (q31_t)0xb22eb392, (q31_t)0x6563bf92, (q31_t)0xb1def9e9, (q31_t)0x6526438f, (q31_t)0xb18f7071,
+  (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x64aa907f, (q31_t)0xb0f0eeda, (q31_t)0x646c59bf, (q31_t)0xb0a1f71d, (q31_t)0x642de50d, (q31_t)0xb0533055,
+  (q31_t)0x63ef3290, (q31_t)0xb0049ab3, (q31_t)0x63b0426d, (q31_t)0xafb63667, (q31_t)0x637114cc, (q31_t)0xaf6803a2, (q31_t)0x6331a9d4, (q31_t)0xaf1a0293,
+  (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x62b21c7b, (q31_t)0xae7e965b, (q31_t)0x6271fa69, (q31_t)0xae312b92, (q31_t)0x62319b9d, (q31_t)0xade3f33e,
+  (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x61b02876, (q31_t)0xad4a1aba, (q31_t)0x616f146c, (q31_t)0xacfd7ae8, (q31_t)0x612dc447, (q31_t)0xacb10e4b,
+  (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x60aa7050, (q31_t)0xac18cf69, (q31_t)0x60686ccf, (q31_t)0xabccfd83, (q31_t)0x60262dd6, (q31_t)0xab815f8d,
+  (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, (q31_t)0x5fa0fe1f, (q31_t)0xaaeac02c, (q31_t)0x5f5e0db3, (q31_t)0xaa9fbf1e, (q31_t)0x5f1ae274, (q31_t)0xaa54f2ba,
+  (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5e93dc1f, (q31_t)0xa9bff8a8, (q31_t)0x5e50015d, (q31_t)0xa975cb57, (q31_t)0x5e0bec6e, (q31_t)0xa92bd367,
+  (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5d8314b1, (q31_t)0xa8988463, (q31_t)0x5d3e5237, (q31_t)0xa84f2daa, (q31_t)0x5cf95638, (q31_t)0xa8060d08,
+  (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5c6eb258, (q31_t)0xa7746ec0, (q31_t)0x5c290acc, (q31_t)0xa72bf174, (q31_t)0x5be32a67, (q31_t)0xa6e3aaf2,
+  (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, (q31_t)0x5b56bfbd, (q31_t)0xa653c303, (q31_t)0x5b1035cf, (q31_t)0xa60c21ee, (q31_t)0x5ac973b5, (q31_t)0xa5c4b855,
+  (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x5a3b47ab, (q31_t)0xa5368c4b, (q31_t)0x59f3de12, (q31_t)0xa4efca31, (q31_t)0x59ac3cfd, (q31_t)0xa4a94043,
+  (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x591c550e, (q31_t)0xa41cd599, (q31_t)0x58d40e8c, (q31_t)0xa3d6f534, (q31_t)0x588b9140, (q31_t)0xa3914da8,
+  (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x57f9f2f8, (q31_t)0xa306a9c8, (q31_t)0x57b0d256, (q31_t)0xa2c1adc9, (q31_t)0x57677b9d, (q31_t)0xa27ceb4f,
+  (q31_t)0x571deefa, (q31_t)0xa2386284, (q31_t)0x56d42c99, (q31_t)0xa1f41392, (q31_t)0x568a34a9, (q31_t)0xa1affea3, (q31_t)0x56400758, (q31_t)0xa16c23e1,
+  (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x55ab0d46, (q31_t)0xa0e51d8c, (q31_t)0x556040e2, (q31_t)0xa0a1f24d, (q31_t)0x55153fd4, (q31_t)0xa05f01e1,
+  (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x547ea073, (q31_t)0x9fd9d22a, (q31_t)0x5433027d, (q31_t)0x9f979331, (q31_t)0x53e73097, (q31_t)0x9f558fb0,
+  (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x534ef1b5, (q31_t)0x9ed23bb9, (q31_t)0x53028518, (q31_t)0x9e90eb94, (q31_t)0x52b5e546, (q31_t)0x9e4fd78a,
+  (q31_t)0x5269126e, (q31_t)0x9e0effc1, (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x51ced46e, (q31_t)0x9d8e0597, (q31_t)0x518169a5, (q31_t)0x9d4de385,
+  (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x5049c999, (q31_t)0x9c4fbd93,
+  (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f0f1126, (q31_t)0x9b556f81,
+  (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5,
+  (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4c9087b1, (q31_t)0x996c816f,
+  (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b4ccf4d, (q31_t)0x987df449,
+  (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a062fbd, (q31_t)0x979364b5,
+  (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x48bcb599, (q31_t)0x96acdbbe,
+  (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47706d93, (q31_t)0x95ca6247,
+  (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x4621647d, (q31_t)0x94ec010b,
+  (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x44cfa740, (q31_t)0x9411c09e,
+  (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x437b42e1, (q31_t)0x933ba968,
+  (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x42244481, (q31_t)0x9269c3ac,
+  (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x40cab958, (q31_t)0x919c1781,
+  (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4,
+  (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e10320d, (q31_t)0x900d8b69,
+  (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3caf50da, (q31_t)0x8f4cbadb,
+  (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b4c18ba, (q31_t)0x8e904298,
+  (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x3a99a057, (q31_t)0x8e33a9da, (q31_t)0x3a402dd2, (q31_t)0x8e05c6b7, (q31_t)0x39e6975e, (q31_t)0x8dd829e4,
+  (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x3932ff87, (q31_t)0x8d7dc399, (q31_t)0x38d8fe93, (q31_t)0x8d50fa59, (q31_t)0x387eda8e, (q31_t)0x8d2477d8,
+  (q31_t)0x382493b0, (q31_t)0x8cf83c30, (q31_t)0x37ca2a30, (q31_t)0x8ccc477d, (q31_t)0x376f9e46, (q31_t)0x8ca099da, (q31_t)0x3714f02a, (q31_t)0x8c753362,
+  (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x365f2e3b, (q31_t)0x8c1f3c5d, (q31_t)0x36041ad9, (q31_t)0x8bf4ac05, (q31_t)0x35a8e625, (q31_t)0x8bca6343,
+  (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x34f219a8, (q31_t)0x8b76a8e4, (q31_t)0x34968250, (q31_t)0x8b4d377c, (q31_t)0x343aca87, (q31_t)0x8b240e11,
+  (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x3382fa88, (q31_t)0x8ad29394, (q31_t)0x3326e2c3, (q31_t)0x8aaa42b4, (q31_t)0x32caab6f, (q31_t)0x8a823a36,
+  (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, (q31_t)0x3211df04, (q31_t)0x8a3302be, (q31_t)0x31b54a5e, (q31_t)0x8a0bd3f5, (q31_t)0x3158970e, (q31_t)0x89e4edef,
+  (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x309ed556, (q31_t)0x8997fc8a, (q31_t)0x3041c761, (q31_t)0x8971f15a, (q31_t)0x2fe49ba7, (q31_t)0x894c2f4c,
+  (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2f29ebcc, (q31_t)0x890186f2, (q31_t)0x2ecc681e, (q31_t)0x88dca0d3, (q31_t)0x2e6ec792, (q31_t)0x88b80432,
+  (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2db330c7, (q31_t)0x886fa7c2, (q31_t)0x2d553afc, (q31_t)0x884be821, (q31_t)0x2cf72939, (q31_t)0x88287256,
+  (q31_t)0x2c98fbba, (q31_t)0x88054677, (q31_t)0x2c3ab2b9, (q31_t)0x87e2649b, (q31_t)0x2bdc4e6f, (q31_t)0x87bfccd7, (q31_t)0x2b7dcf17, (q31_t)0x879d7f41,
+  (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a02c7b8, (q31_t)0x8717304e,
+  (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x288621b9, (q31_t)0x86958aac,
+  (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x2707ebc7, (q31_t)0x86189359,
+  (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x2588349d, (q31_t)0x85a04f28,
+  (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x24070b08, (q31_t)0x852cc2bb,
+  (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22847de0, (q31_t)0x84bdf286,
+  (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x21009c0c, (q31_t)0x8453e2cf,
+  (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1f7b7481, (q31_t)0x83ee97ad,
+  (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1df5163f, (q31_t)0x838e1507,
+  (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1c6d9053, (q31_t)0x83325e97,
+  (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5,
+  (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x195b49ea, (q31_t)0x8289644b,
+  (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x17d0a7bc, (q31_t)0x823c26f3,
+  (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x16451a83, (q31_t)0x81f3c2d7,
+  (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x14b8b17f, (q31_t)0x81b03ac2,
+  (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x132b7bf9, (q31_t)0x8171914e,
+  (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x119d8941, (q31_t)0x8137c8e6,
+  (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x100ee8ad, (q31_t)0x8102e3c4,
+  (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2,
+  (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xcefdb76, (q31_t)0x80a7cb49,
+  (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xb5f8d9f, (q31_t)0x80819b74,
+  (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0x9cecf89, (q31_t)0x806055eb,
+  (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x83db0a7, (q31_t)0x8043fbf6,
+  (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x6ac406f, (q31_t)0x802c8ead,
+  (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x51a8e5c, (q31_t)0x801a0ef8,
+  (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x388a9ea, (q31_t)0x800c7d8c,
+  (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x1f6a297, (q31_t)0x8003daf1,
+  (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0xc90f88, (q31_t)0x80009dea, (q31_t)0x6487e3, (q31_t)0x8000277a
+};
+
+static const q31_t WeightsQ31_2048[4096] = {
+  (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7fffe9cb, (q31_t)0xffb49a12,
+  (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff8719, (q31_t)0xff501258,
+  (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a,
+  (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffdd4d7, (q31_t)0xfe870467,
+  (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffc8549, (q31_t)0xfe227eac,
+  (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18,
+  (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff8f954, (q31_t)0xfd5976e9,
+  (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c,
+  (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4319d, (q31_t)0xfc9075af,
+  (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1575d, (q31_t)0xfc2bf821,
+  (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7feeffe1, (q31_t)0xfbe09b80, (q31_t)0x7fee2e30, (q31_t)0xfbc77cf0,
+  (q31_t)0x7fed5791, (q31_t)0xfbae5e89, (q31_t)0x7fec7c02, (q31_t)0xfb95404d, (q31_t)0x7feb9b85, (q31_t)0xfb7c223d, (q31_t)0x7feab61a, (q31_t)0xfb630459,
+  (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe8dc78, (q31_t)0xfb30c91b, (q31_t)0x7fe7e841, (q31_t)0xfb17abc2, (q31_t)0x7fe6ef1c, (q31_t)0xfafe8e9b,
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+  (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd74964, (q31_t)0xf99f0c68, (q31_t)0x7fd6064c, (q31_t)0xf985f28a, (q31_t)0x7fd4be46, (q31_t)0xf96cd8ed,
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+  (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fba6357, (q31_t)0xf7a93ae0, (q31_t)0x7fb8bdb8, (q31_t)0xf79026b9, (q31_t)0x7fb7132b, (q31_t)0xf77712e5,
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+  (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, (q31_t)0x7f698461, (q31_t)0xf3bf37cb, (q31_t)0x7f671a05, (q31_t)0xf3a63398, (q31_t)0x7f64aabf, (q31_t)0xf38d2fe0,
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+  (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7dac3b15, (q31_t)0xe7b3eb9f, (q31_t)0x7da77359, (q31_t)0xe79b3f16, (q31_t)0x7da2a6c6, (q31_t)0xe782937e,
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+  (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7cc80a0f, (q31_t)0xe379eeed, (q31_t)0x7cc26de5, (q31_t)0xe3616f48, (q31_t)0x7cbcccec, (q31_t)0xe348f0bd,
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+  (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c837ad8, (q31_t)0xe2543ccc, (q31_t)0x7c7da505, (q31_t)0xe23bcaa2, (q31_t)0x7c77ca65, (q31_t)0xe223599e,
+  (q31_t)0x7c71eaf9, (q31_t)0xe20ae9c1, (q31_t)0x7c6c06c0, (q31_t)0xe1f27b0b, (q31_t)0x7c661dbc, (q31_t)0xe1da0d7e, (q31_t)0x7c602fec, (q31_t)0xe1c1a11b,
+  (q31_t)0x7c5a3d50, (q31_t)0xe1a935e2, (q31_t)0x7c5445e9, (q31_t)0xe190cbd4, (q31_t)0x7c4e49b7, (q31_t)0xe17862f3, (q31_t)0x7c4848ba, (q31_t)0xe15ffb3f,
+  (q31_t)0x7c4242f2, (q31_t)0xe14794ba, (q31_t)0x7c3c3860, (q31_t)0xe12f2f63, (q31_t)0x7c362904, (q31_t)0xe116cb3d, (q31_t)0x7c3014de, (q31_t)0xe0fe6848,
+  (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7c23de35, (q31_t)0xe0cda5f5, (q31_t)0x7c1dbbb3, (q31_t)0xe0b54698, (q31_t)0x7c179467, (q31_t)0xe09ce871,
+  (q31_t)0x7c116853, (q31_t)0xe0848b7f, (q31_t)0x7c0b3777, (q31_t)0xe06c2fc4, (q31_t)0x7c0501d2, (q31_t)0xe053d541, (q31_t)0x7bfec765, (q31_t)0xe03b7bf6,
+  (q31_t)0x7bf88830, (q31_t)0xe02323e5, (q31_t)0x7bf24434, (q31_t)0xe00acd0e, (q31_t)0x7bebfb70, (q31_t)0xdff27773, (q31_t)0x7be5ade6, (q31_t)0xdfda2314,
+  (q31_t)0x7bdf5b94, (q31_t)0xdfc1cff3, (q31_t)0x7bd9047c, (q31_t)0xdfa97e0f, (q31_t)0x7bd2a89e, (q31_t)0xdf912d6b, (q31_t)0x7bcc47fa, (q31_t)0xdf78de07,
+  (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7bbf7860, (q31_t)0xdf484302, (q31_t)0x7bb9096b, (q31_t)0xdf2ff764, (q31_t)0x7bb295b0, (q31_t)0xdf17ad0a,
+  (q31_t)0x7bac1d31, (q31_t)0xdeff63f4, (q31_t)0x7ba59fee, (q31_t)0xdee71c24, (q31_t)0x7b9f1de6, (q31_t)0xdeced59b, (q31_t)0x7b989719, (q31_t)0xdeb69059,
+  (q31_t)0x7b920b89, (q31_t)0xde9e4c60, (q31_t)0x7b8b7b36, (q31_t)0xde8609b1, (q31_t)0x7b84e61f, (q31_t)0xde6dc84b, (q31_t)0x7b7e4c45, (q31_t)0xde558831,
+  (q31_t)0x7b77ada8, (q31_t)0xde3d4964, (q31_t)0x7b710a49, (q31_t)0xde250be3, (q31_t)0x7b6a6227, (q31_t)0xde0ccfb1, (q31_t)0x7b63b543, (q31_t)0xddf494ce,
+  (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7b564d36, (q31_t)0xddc422f8, (q31_t)0x7b4f920e, (q31_t)0xddabec08, (q31_t)0x7b48d225, (q31_t)0xdd93b66a,
+  (q31_t)0x7b420d7a, (q31_t)0xdd7b8220, (q31_t)0x7b3b4410, (q31_t)0xdd634f2b, (q31_t)0x7b3475e5, (q31_t)0xdd4b1d8c, (q31_t)0x7b2da2fa, (q31_t)0xdd32ed43,
+  (q31_t)0x7b26cb4f, (q31_t)0xdd1abe51, (q31_t)0x7b1feee5, (q31_t)0xdd0290b8, (q31_t)0x7b190dbc, (q31_t)0xdcea6478, (q31_t)0x7b1227d3, (q31_t)0xdcd23993,
+  (q31_t)0x7b0b3d2c, (q31_t)0xdcba1008, (q31_t)0x7b044dc7, (q31_t)0xdca1e7da, (q31_t)0x7afd59a4, (q31_t)0xdc89c109, (q31_t)0x7af660c2, (q31_t)0xdc719b96,
+  (q31_t)0x7aef6323, (q31_t)0xdc597781, (q31_t)0x7ae860c7, (q31_t)0xdc4154cd, (q31_t)0x7ae159ae, (q31_t)0xdc293379, (q31_t)0x7ada4dd8, (q31_t)0xdc111388,
+  (q31_t)0x7ad33d45, (q31_t)0xdbf8f4f8, (q31_t)0x7acc27f7, (q31_t)0xdbe0d7cd, (q31_t)0x7ac50dec, (q31_t)0xdbc8bc06, (q31_t)0x7abdef25, (q31_t)0xdbb0a1a4,
+  (q31_t)0x7ab6cba4, (q31_t)0xdb9888a8, (q31_t)0x7aafa367, (q31_t)0xdb807114, (q31_t)0x7aa8766f, (q31_t)0xdb685ae9, (q31_t)0x7aa144bc, (q31_t)0xdb504626,
+  (q31_t)0x7a9a0e50, (q31_t)0xdb3832cd, (q31_t)0x7a92d329, (q31_t)0xdb2020e0, (q31_t)0x7a8b9348, (q31_t)0xdb08105e, (q31_t)0x7a844eae, (q31_t)0xdaf00149,
+  (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a75b74f, (q31_t)0xdabfe76a, (q31_t)0x7a6e648a, (q31_t)0xdaa7dca1, (q31_t)0x7a670d0d, (q31_t)0xda8fd349,
+  (q31_t)0x7a5fb0d8, (q31_t)0xda77cb63, (q31_t)0x7a584feb, (q31_t)0xda5fc4ef, (q31_t)0x7a50ea47, (q31_t)0xda47bfee, (q31_t)0x7a497feb, (q31_t)0xda2fbc61,
+  (q31_t)0x7a4210d8, (q31_t)0xda17ba4a, (q31_t)0x7a3a9d0f, (q31_t)0xd9ffb9a9, (q31_t)0x7a332490, (q31_t)0xd9e7ba7f, (q31_t)0x7a2ba75a, (q31_t)0xd9cfbccd,
+  (q31_t)0x7a24256f, (q31_t)0xd9b7c094, (q31_t)0x7a1c9ece, (q31_t)0xd99fc5d4, (q31_t)0x7a151378, (q31_t)0xd987cc90, (q31_t)0x7a0d836d, (q31_t)0xd96fd4c7,
+  (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x79fe5539, (q31_t)0xd93fe9ab, (q31_t)0x79f6b711, (q31_t)0xd927f65b, (q31_t)0x79ef1436, (q31_t)0xd910048a,
+  (q31_t)0x79e76ca7, (q31_t)0xd8f81439, (q31_t)0x79dfc064, (q31_t)0xd8e0256a, (q31_t)0x79d80f6f, (q31_t)0xd8c8381d, (q31_t)0x79d059c8, (q31_t)0xd8b04c52,
+  (q31_t)0x79c89f6e, (q31_t)0xd898620c, (q31_t)0x79c0e062, (q31_t)0xd880794b, (q31_t)0x79b91ca4, (q31_t)0xd868920f, (q31_t)0x79b15435, (q31_t)0xd850ac5a,
+  (q31_t)0x79a98715, (q31_t)0xd838c82d, (q31_t)0x79a1b545, (q31_t)0xd820e589, (q31_t)0x7999dec4, (q31_t)0xd809046e, (q31_t)0x79920392, (q31_t)0xd7f124dd,
+  (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x79823f20, (q31_t)0xd7c16a5f, (q31_t)0x797a55e0, (q31_t)0xd7a98f73, (q31_t)0x797267f2, (q31_t)0xd791b616,
+  (q31_t)0x796a7554, (q31_t)0xd779de47, (q31_t)0x79627e08, (q31_t)0xd7620808, (q31_t)0x795a820e, (q31_t)0xd74a335b, (q31_t)0x79528167, (q31_t)0xd732603f,
+  (q31_t)0x794a7c12, (q31_t)0xd71a8eb5, (q31_t)0x79427210, (q31_t)0xd702bec0, (q31_t)0x793a6361, (q31_t)0xd6eaf05f, (q31_t)0x79325006, (q31_t)0xd6d32393,
+  (q31_t)0x792a37fe, (q31_t)0xd6bb585e, (q31_t)0x79221b4b, (q31_t)0xd6a38ec0, (q31_t)0x7919f9ec, (q31_t)0xd68bc6ba, (q31_t)0x7911d3e2, (q31_t)0xd674004e,
+  (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, (q31_t)0x790179cd, (q31_t)0xd6447844, (q31_t)0x78f945c3, (q31_t)0xd62cb6a8, (q31_t)0x78f10d0f, (q31_t)0xd614f6a9,
+  (q31_t)0x78e8cfb2, (q31_t)0xd5fd3848, (q31_t)0x78e08dab, (q31_t)0xd5e57b85, (q31_t)0x78d846fb, (q31_t)0xd5cdc062, (q31_t)0x78cffba3, (q31_t)0xd5b606e0,
+  (q31_t)0x78c7aba2, (q31_t)0xd59e4eff, (q31_t)0x78bf56f9, (q31_t)0xd58698c0, (q31_t)0x78b6fda8, (q31_t)0xd56ee424, (q31_t)0x78ae9fb0, (q31_t)0xd557312d,
+  (q31_t)0x78a63d11, (q31_t)0xd53f7fda, (q31_t)0x789dd5cb, (q31_t)0xd527d02e, (q31_t)0x789569df, (q31_t)0xd5102228, (q31_t)0x788cf94c, (q31_t)0xd4f875ca,
+  (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x787c0a36, (q31_t)0xd4c92209, (q31_t)0x78738bb3, (q31_t)0xd4b17aa8, (q31_t)0x786b088c, (q31_t)0xd499d4f2,
+  (q31_t)0x786280bf, (q31_t)0xd48230e9, (q31_t)0x7859f44f, (q31_t)0xd46a8e8d, (q31_t)0x7851633b, (q31_t)0xd452eddf, (q31_t)0x7848cd83, (q31_t)0xd43b4ee0,
+  (q31_t)0x78403329, (q31_t)0xd423b191, (q31_t)0x7837942b, (q31_t)0xd40c15f3, (q31_t)0x782ef08b, (q31_t)0xd3f47c06, (q31_t)0x78264849, (q31_t)0xd3dce3cd,
+  (q31_t)0x781d9b65, (q31_t)0xd3c54d47, (q31_t)0x7814e9df, (q31_t)0xd3adb876, (q31_t)0x780c33b8, (q31_t)0xd396255a, (q31_t)0x780378f1, (q31_t)0xd37e93f4,
+  (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x77f1f581, (q31_t)0xd34f764f, (q31_t)0x77e92cd9, (q31_t)0xd337ea12, (q31_t)0x77e05f91, (q31_t)0xd3205f8f,
+  (q31_t)0x77d78daa, (q31_t)0xd308d6c7, (q31_t)0x77ceb725, (q31_t)0xd2f14fba, (q31_t)0x77c5dc01, (q31_t)0xd2d9ca6a, (q31_t)0x77bcfc3f, (q31_t)0xd2c246d8,
+  (q31_t)0x77b417df, (q31_t)0xd2aac504, (q31_t)0x77ab2ee2, (q31_t)0xd29344f0, (q31_t)0x77a24148, (q31_t)0xd27bc69c, (q31_t)0x77994f11, (q31_t)0xd2644a0a,
+  (q31_t)0x7790583e, (q31_t)0xd24ccf39, (q31_t)0x77875cce, (q31_t)0xd235562b, (q31_t)0x777e5cc3, (q31_t)0xd21ddee2, (q31_t)0x7775581d, (q31_t)0xd206695d,
+  (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x776340ff, (q31_t)0xd1d783a6, (q31_t)0x775a2e89, (q31_t)0xd1c01375, (q31_t)0x77511778, (q31_t)0xd1a8a50d,
+  (q31_t)0x7747fbce, (q31_t)0xd191386e, (q31_t)0x773edb8b, (q31_t)0xd179cd99, (q31_t)0x7735b6af, (q31_t)0xd1626490, (q31_t)0x772c8d3a, (q31_t)0xd14afd52,
+  (q31_t)0x77235f2d, (q31_t)0xd13397e2, (q31_t)0x771a2c88, (q31_t)0xd11c343f, (q31_t)0x7710f54c, (q31_t)0xd104d26b, (q31_t)0x7707b979, (q31_t)0xd0ed7267,
+  (q31_t)0x76fe790e, (q31_t)0xd0d61434, (q31_t)0x76f5340e, (q31_t)0xd0beb7d2, (q31_t)0x76ebea77, (q31_t)0xd0a75d42, (q31_t)0x76e29c4b, (q31_t)0xd0900486,
+  (q31_t)0x76d94989, (q31_t)0xd078ad9e, (q31_t)0x76cff232, (q31_t)0xd061588b, (q31_t)0x76c69647, (q31_t)0xd04a054e, (q31_t)0x76bd35c7, (q31_t)0xd032b3e7,
+  (q31_t)0x76b3d0b4, (q31_t)0xd01b6459, (q31_t)0x76aa670d, (q31_t)0xd00416a3, (q31_t)0x76a0f8d2, (q31_t)0xcfeccac7, (q31_t)0x76978605, (q31_t)0xcfd580c6,
+  (q31_t)0x768e0ea6, (q31_t)0xcfbe389f, (q31_t)0x768492b4, (q31_t)0xcfa6f255, (q31_t)0x767b1231, (q31_t)0xcf8fade9, (q31_t)0x76718d1c, (q31_t)0xcf786b5a,
+  (q31_t)0x76680376, (q31_t)0xcf612aaa, (q31_t)0x765e7540, (q31_t)0xcf49ebda, (q31_t)0x7654e279, (q31_t)0xcf32aeeb, (q31_t)0x764b4b23, (q31_t)0xcf1b73de,
+  (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x76380ec8, (q31_t)0xceed036b, (q31_t)0x762e69c4, (q31_t)0xced5ce08, (q31_t)0x7624c031, (q31_t)0xcebe9a8a,
+  (q31_t)0x761b1211, (q31_t)0xcea768f2, (q31_t)0x76115f63, (q31_t)0xce903942, (q31_t)0x7607a828, (q31_t)0xce790b79, (q31_t)0x75fdec60, (q31_t)0xce61df99,
+  (q31_t)0x75f42c0b, (q31_t)0xce4ab5a2, (q31_t)0x75ea672a, (q31_t)0xce338d97, (q31_t)0x75e09dbd, (q31_t)0xce1c6777, (q31_t)0x75d6cfc5, (q31_t)0xce054343,
+  (q31_t)0x75ccfd42, (q31_t)0xcdee20fc, (q31_t)0x75c32634, (q31_t)0xcdd700a4, (q31_t)0x75b94a9c, (q31_t)0xcdbfe23a, (q31_t)0x75af6a7b, (q31_t)0xcda8c5c1,
+  (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x759b9c9b, (q31_t)0xcd7a92a2, (q31_t)0x7591aedd, (q31_t)0xcd637bfe, (q31_t)0x7587bc98, (q31_t)0xcd4c674d,
+  (q31_t)0x757dc5ca, (q31_t)0xcd355491, (q31_t)0x7573ca75, (q31_t)0xcd1e43ca, (q31_t)0x7569ca99, (q31_t)0xcd0734f9, (q31_t)0x755fc635, (q31_t)0xccf0281f,
+  (q31_t)0x7555bd4c, (q31_t)0xccd91d3d, (q31_t)0x754bafdc, (q31_t)0xccc21455, (q31_t)0x75419de7, (q31_t)0xccab0d65, (q31_t)0x7537876c, (q31_t)0xcc940871,
+  (q31_t)0x752d6c6c, (q31_t)0xcc7d0578, (q31_t)0x75234ce8, (q31_t)0xcc66047b, (q31_t)0x751928e0, (q31_t)0xcc4f057c, (q31_t)0x750f0054, (q31_t)0xcc38087b,
+  (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x74faa1b3, (q31_t)0xcc0a1477, (q31_t)0x74f06b9e, (q31_t)0xcbf31d75, (q31_t)0x74e63108, (q31_t)0xcbdc2876,
+  (q31_t)0x74dbf1ef, (q31_t)0xcbc53579, (q31_t)0x74d1ae55, (q31_t)0xcbae447f, (q31_t)0x74c7663a, (q31_t)0xcb97558a, (q31_t)0x74bd199f, (q31_t)0xcb80689a,
+  (q31_t)0x74b2c884, (q31_t)0xcb697db0, (q31_t)0x74a872e8, (q31_t)0xcb5294ce, (q31_t)0x749e18cd, (q31_t)0xcb3badf3, (q31_t)0x7493ba34, (q31_t)0xcb24c921,
+  (q31_t)0x7489571c, (q31_t)0xcb0de658, (q31_t)0x747eef85, (q31_t)0xcaf7059a, (q31_t)0x74748371, (q31_t)0xcae026e8, (q31_t)0x746a12df, (q31_t)0xcac94a42,
+  (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, (q31_t)0x74552446, (q31_t)0xca9b971e, (q31_t)0x744aa63f, (q31_t)0xca84c0a3, (q31_t)0x744023bc, (q31_t)0xca6dec37,
+  (q31_t)0x74359cbd, (q31_t)0xca5719db, (q31_t)0x742b1144, (q31_t)0xca404992, (q31_t)0x74208150, (q31_t)0xca297b5a, (q31_t)0x7415ece2, (q31_t)0xca12af37,
+  (q31_t)0x740b53fb, (q31_t)0xc9fbe527, (q31_t)0x7400b69a, (q31_t)0xc9e51d2d, (q31_t)0x73f614c0, (q31_t)0xc9ce5748, (q31_t)0x73eb6e6e, (q31_t)0xc9b7937a,
+  (q31_t)0x73e0c3a3, (q31_t)0xc9a0d1c5, (q31_t)0x73d61461, (q31_t)0xc98a1227, (q31_t)0x73cb60a8, (q31_t)0xc97354a4, (q31_t)0x73c0a878, (q31_t)0xc95c993a,
+  (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x73ab2ab4, (q31_t)0xc92f28ba, (q31_t)0x73a06522, (q31_t)0xc91873a5, (q31_t)0x73959b1b, (q31_t)0xc901c0ae,
+  (q31_t)0x738acc9e, (q31_t)0xc8eb0fd6, (q31_t)0x737ff9ae, (q31_t)0xc8d4611d, (q31_t)0x73752249, (q31_t)0xc8bdb485, (q31_t)0x736a4671, (q31_t)0xc8a70a0e,
+  (q31_t)0x735f6626, (q31_t)0xc89061ba, (q31_t)0x73548168, (q31_t)0xc879bb89, (q31_t)0x73499838, (q31_t)0xc863177b, (q31_t)0x733eaa96, (q31_t)0xc84c7593,
+  (q31_t)0x7333b883, (q31_t)0xc835d5d0, (q31_t)0x7328c1ff, (q31_t)0xc81f3834, (q31_t)0x731dc70a, (q31_t)0xc8089cbf, (q31_t)0x7312c7a5, (q31_t)0xc7f20373,
+  (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72fcbb8c, (q31_t)0xc7c4d757, (q31_t)0x72f1aed9, (q31_t)0xc7ae4489, (q31_t)0x72e69db7, (q31_t)0xc797b3e7,
+  (q31_t)0x72db8828, (q31_t)0xc7812572, (q31_t)0x72d06e2b, (q31_t)0xc76a992a, (q31_t)0x72c54fc1, (q31_t)0xc7540f11, (q31_t)0x72ba2cea, (q31_t)0xc73d8727,
+  (q31_t)0x72af05a7, (q31_t)0xc727016d, (q31_t)0x72a3d9f7, (q31_t)0xc7107de4, (q31_t)0x7298a9dd, (q31_t)0xc6f9fc8d, (q31_t)0x728d7557, (q31_t)0xc6e37d69,
+  (q31_t)0x72823c67, (q31_t)0xc6cd0079, (q31_t)0x7276ff0d, (q31_t)0xc6b685bd, (q31_t)0x726bbd48, (q31_t)0xc6a00d37, (q31_t)0x7260771b, (q31_t)0xc68996e7,
+  (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x7249dd86, (q31_t)0xc65cb0ed, (q31_t)0x723e8a20, (q31_t)0xc6464144, (q31_t)0x72333251, (q31_t)0xc62fd3d6,
+  (q31_t)0x7227d61c, (q31_t)0xc61968a2, (q31_t)0x721c7580, (q31_t)0xc602ffaa, (q31_t)0x7211107e, (q31_t)0xc5ec98ee, (q31_t)0x7205a716, (q31_t)0xc5d6346f,
+  (q31_t)0x71fa3949, (q31_t)0xc5bfd22e, (q31_t)0x71eec716, (q31_t)0xc5a9722c, (q31_t)0x71e35080, (q31_t)0xc593146a, (q31_t)0x71d7d585, (q31_t)0xc57cb8e9,
+  (q31_t)0x71cc5626, (q31_t)0xc5665fa9, (q31_t)0x71c0d265, (q31_t)0xc55008ab, (q31_t)0x71b54a41, (q31_t)0xc539b3f1, (q31_t)0x71a9bdba, (q31_t)0xc523617a,
+  (q31_t)0x719e2cd2, (q31_t)0xc50d1149, (q31_t)0x71929789, (q31_t)0xc4f6c35d, (q31_t)0x7186fdde, (q31_t)0xc4e077b8, (q31_t)0x717b5fd3, (q31_t)0xc4ca2e5b,
+  (q31_t)0x716fbd68, (q31_t)0xc4b3e746, (q31_t)0x7164169d, (q31_t)0xc49da27a, (q31_t)0x71586b74, (q31_t)0xc4875ff9, (q31_t)0x714cbbeb, (q31_t)0xc4711fc2,
+  (q31_t)0x71410805, (q31_t)0xc45ae1d7, (q31_t)0x71354fc0, (q31_t)0xc444a639, (q31_t)0x7129931f, (q31_t)0xc42e6ce8, (q31_t)0x711dd220, (q31_t)0xc41835e6,
+  (q31_t)0x71120cc5, (q31_t)0xc4020133, (q31_t)0x7106430e, (q31_t)0xc3ebced0, (q31_t)0x70fa74fc, (q31_t)0xc3d59ebe, (q31_t)0x70eea28e, (q31_t)0xc3bf70fd,
+  (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x70d6f0a4, (q31_t)0xc3931c76, (q31_t)0x70cb1128, (q31_t)0xc37cf5b0, (q31_t)0x70bf2d53, (q31_t)0xc366d140,
+  (q31_t)0x70b34525, (q31_t)0xc350af26, (q31_t)0x70a7589f, (q31_t)0xc33a8f62, (q31_t)0x709b67c0, (q31_t)0xc32471f7, (q31_t)0x708f728b, (q31_t)0xc30e56e4,
+  (q31_t)0x708378ff, (q31_t)0xc2f83e2a, (q31_t)0x70777b1c, (q31_t)0xc2e227cb, (q31_t)0x706b78e3, (q31_t)0xc2cc13c7, (q31_t)0x705f7255, (q31_t)0xc2b6021f,
+  (q31_t)0x70536771, (q31_t)0xc29ff2d4, (q31_t)0x70475839, (q31_t)0xc289e5e7, (q31_t)0x703b44ad, (q31_t)0xc273db58, (q31_t)0x702f2ccd, (q31_t)0xc25dd329,
+  (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x7016f014, (q31_t)0xc231c9ec, (q31_t)0x700acb3c, (q31_t)0xc21bc8e1, (q31_t)0x6ffea212, (q31_t)0xc205ca38,
+  (q31_t)0x6ff27497, (q31_t)0xc1efcdf3, (q31_t)0x6fe642ca, (q31_t)0xc1d9d412, (q31_t)0x6fda0cae, (q31_t)0xc1c3dc97, (q31_t)0x6fcdd241, (q31_t)0xc1ade781,
+  (q31_t)0x6fc19385, (q31_t)0xc197f4d4, (q31_t)0x6fb5507a, (q31_t)0xc182048d, (q31_t)0x6fa90921, (q31_t)0xc16c16b0, (q31_t)0x6f9cbd79, (q31_t)0xc1562b3d,
+  (q31_t)0x6f906d84, (q31_t)0xc1404233, (q31_t)0x6f841942, (q31_t)0xc12a5b95, (q31_t)0x6f77c0b3, (q31_t)0xc1147764, (q31_t)0x6f6b63d8, (q31_t)0xc0fe959f,
+  (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6f529d40, (q31_t)0xc0d2d960, (q31_t)0x6f463383, (q31_t)0xc0bcfee7, (q31_t)0x6f39c57d, (q31_t)0xc0a726df,
+  (q31_t)0x6f2d532c, (q31_t)0xc0915148, (q31_t)0x6f20dc92, (q31_t)0xc07b7e23, (q31_t)0x6f1461b0, (q31_t)0xc065ad70, (q31_t)0x6f07e285, (q31_t)0xc04fdf32,
+  (q31_t)0x6efb5f12, (q31_t)0xc03a1368, (q31_t)0x6eeed758, (q31_t)0xc0244a14, (q31_t)0x6ee24b57, (q31_t)0xc00e8336, (q31_t)0x6ed5bb10, (q31_t)0xbff8bece,
+  (q31_t)0x6ec92683, (q31_t)0xbfe2fcdf, (q31_t)0x6ebc8db0, (q31_t)0xbfcd3d69, (q31_t)0x6eaff099, (q31_t)0xbfb7806c, (q31_t)0x6ea34f3d, (q31_t)0xbfa1c5ea,
+  (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, (q31_t)0x6e89ffb9, (q31_t)0xbf765858, (q31_t)0x6e7d5193, (q31_t)0xbf60a54a, (q31_t)0x6e709f2a, (q31_t)0xbf4af4ba,
+  (q31_t)0x6e63e87f, (q31_t)0xbf3546a8, (q31_t)0x6e572d93, (q31_t)0xbf1f9b16, (q31_t)0x6e4a6e66, (q31_t)0xbf09f205, (q31_t)0x6e3daaf8, (q31_t)0xbef44b74,
+  (q31_t)0x6e30e34a, (q31_t)0xbedea765, (q31_t)0x6e24175c, (q31_t)0xbec905d9, (q31_t)0x6e174730, (q31_t)0xbeb366d1, (q31_t)0x6e0a72c5, (q31_t)0xbe9dca4e,
+  (q31_t)0x6dfd9a1c, (q31_t)0xbe88304f, (q31_t)0x6df0bd35, (q31_t)0xbe7298d7, (q31_t)0x6de3dc11, (q31_t)0xbe5d03e6, (q31_t)0x6dd6f6b1, (q31_t)0xbe47717c,
+  (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6dbd1f3c, (q31_t)0xbe1c5444, (q31_t)0x6db02d29, (q31_t)0xbe06c977, (q31_t)0x6da336dc, (q31_t)0xbdf14135,
+  (q31_t)0x6d963c54, (q31_t)0xbddbbb7f, (q31_t)0x6d893d93, (q31_t)0xbdc63856, (q31_t)0x6d7c3a98, (q31_t)0xbdb0b7bb, (q31_t)0x6d6f3365, (q31_t)0xbd9b39ad,
+  (q31_t)0x6d6227fa, (q31_t)0xbd85be30, (q31_t)0x6d551858, (q31_t)0xbd704542, (q31_t)0x6d48047e, (q31_t)0xbd5acee5, (q31_t)0x6d3aec6e, (q31_t)0xbd455b1a,
+  (q31_t)0x6d2dd027, (q31_t)0xbd2fe9e2, (q31_t)0x6d20afac, (q31_t)0xbd1a7b3d, (q31_t)0x6d138afb, (q31_t)0xbd050f2c, (q31_t)0x6d066215, (q31_t)0xbcefa5b0,
+  (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6cec03af, (q31_t)0xbcc4da7b, (q31_t)0x6cdece2f, (q31_t)0xbcaf78c4, (q31_t)0x6cd1947c, (q31_t)0xbc9a19a5,
+  (q31_t)0x6cc45698, (q31_t)0xbc84bd1f, (q31_t)0x6cb71482, (q31_t)0xbc6f6333, (q31_t)0x6ca9ce3b, (q31_t)0xbc5a0be2, (q31_t)0x6c9c83c3, (q31_t)0xbc44b72c,
+  (q31_t)0x6c8f351c, (q31_t)0xbc2f6513, (q31_t)0x6c81e245, (q31_t)0xbc1a1598, (q31_t)0x6c748b3f, (q31_t)0xbc04c8ba, (q31_t)0x6c67300b, (q31_t)0xbbef7e7c,
+  (q31_t)0x6c59d0a9, (q31_t)0xbbda36dd, (q31_t)0x6c4c6d1a, (q31_t)0xbbc4f1df, (q31_t)0x6c3f055d, (q31_t)0xbbafaf82, (q31_t)0x6c319975, (q31_t)0xbb9a6fc7,
+  (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6c16b521, (q31_t)0xbb6ff83c, (q31_t)0x6c093cb6, (q31_t)0xbb5ac06d, (q31_t)0x6bfbc021, (q31_t)0xbb458b43,
+  (q31_t)0x6bee3f62, (q31_t)0xbb3058c0, (q31_t)0x6be0ba7b, (q31_t)0xbb1b28e4, (q31_t)0x6bd3316a, (q31_t)0xbb05fbb0, (q31_t)0x6bc5a431, (q31_t)0xbaf0d125,
+  (q31_t)0x6bb812d1, (q31_t)0xbadba943, (q31_t)0x6baa7d49, (q31_t)0xbac6840c, (q31_t)0x6b9ce39b, (q31_t)0xbab16180, (q31_t)0x6b8f45c7, (q31_t)0xba9c41a0,
+  (q31_t)0x6b81a3cd, (q31_t)0xba87246d, (q31_t)0x6b73fdae, (q31_t)0xba7209e7, (q31_t)0x6b66536b, (q31_t)0xba5cf210, (q31_t)0x6b58a503, (q31_t)0xba47dce8,
+  (q31_t)0x6b4af279, (q31_t)0xba32ca71, (q31_t)0x6b3d3bcb, (q31_t)0xba1dbaaa, (q31_t)0x6b2f80fb, (q31_t)0xba08ad95, (q31_t)0x6b21c208, (q31_t)0xb9f3a332,
+  (q31_t)0x6b13fef5, (q31_t)0xb9de9b83, (q31_t)0x6b0637c1, (q31_t)0xb9c99688, (q31_t)0x6af86c6c, (q31_t)0xb9b49442, (q31_t)0x6aea9cf8, (q31_t)0xb99f94b2,
+  (q31_t)0x6adcc964, (q31_t)0xb98a97d8, (q31_t)0x6acef1b2, (q31_t)0xb9759db6, (q31_t)0x6ac115e2, (q31_t)0xb960a64c, (q31_t)0x6ab335f4, (q31_t)0xb94bb19b,
+  (q31_t)0x6aa551e9, (q31_t)0xb936bfa4, (q31_t)0x6a9769c1, (q31_t)0xb921d067, (q31_t)0x6a897d7d, (q31_t)0xb90ce3e6, (q31_t)0x6a7b8d1e, (q31_t)0xb8f7fa21,
+  (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x6a5fa010, (q31_t)0xb8ce2ecf, (q31_t)0x6a51a361, (q31_t)0xb8b94d44, (q31_t)0x6a43a29a, (q31_t)0xb8a46e78,
+  (q31_t)0x6a359db9, (q31_t)0xb88f926d, (q31_t)0x6a2794c1, (q31_t)0xb87ab922, (q31_t)0x6a1987b0, (q31_t)0xb865e299, (q31_t)0x6a0b7689, (q31_t)0xb8510ed4,
+  (q31_t)0x69fd614a, (q31_t)0xb83c3dd1, (q31_t)0x69ef47f6, (q31_t)0xb8276f93, (q31_t)0x69e12a8c, (q31_t)0xb812a41a, (q31_t)0x69d3090e, (q31_t)0xb7fddb67,
+  (q31_t)0x69c4e37a, (q31_t)0xb7e9157a, (q31_t)0x69b6b9d3, (q31_t)0xb7d45255, (q31_t)0x69a88c19, (q31_t)0xb7bf91f8, (q31_t)0x699a5a4c, (q31_t)0xb7aad465,
+  (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x697dea7b, (q31_t)0xb781619c, (q31_t)0x696fac78, (q31_t)0xb76cac69, (q31_t)0x69616a65, (q31_t)0xb757fa01,
+  (q31_t)0x69532442, (q31_t)0xb7434a67, (q31_t)0x6944da10, (q31_t)0xb72e9d9b, (q31_t)0x69368bce, (q31_t)0xb719f39e, (q31_t)0x6928397e, (q31_t)0xb7054c6f,
+  (q31_t)0x6919e320, (q31_t)0xb6f0a812, (q31_t)0x690b88b5, (q31_t)0xb6dc0685, (q31_t)0x68fd2a3d, (q31_t)0xb6c767ca, (q31_t)0x68eec7b9, (q31_t)0xb6b2cbe2,
+  (q31_t)0x68e06129, (q31_t)0xb69e32cd, (q31_t)0x68d1f68f, (q31_t)0xb6899c8d, (q31_t)0x68c387e9, (q31_t)0xb6750921, (q31_t)0x68b5153a, (q31_t)0xb660788c,
+  (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x689823bf, (q31_t)0xb6375fe5, (q31_t)0x6889a4f6, (q31_t)0xb622d7d6, (q31_t)0x687b2224, (q31_t)0xb60e529f,
+  (q31_t)0x686c9b4b, (q31_t)0xb5f9d043, (q31_t)0x685e106c, (q31_t)0xb5e550c1, (q31_t)0x684f8186, (q31_t)0xb5d0d41a, (q31_t)0x6840ee9b, (q31_t)0xb5bc5a50,
+  (q31_t)0x683257ab, (q31_t)0xb5a7e362, (q31_t)0x6823bcb7, (q31_t)0xb5936f53, (q31_t)0x68151dbe, (q31_t)0xb57efe22, (q31_t)0x68067ac3, (q31_t)0xb56a8fd0,
+  (q31_t)0x67f7d3c5, (q31_t)0xb556245e, (q31_t)0x67e928c5, (q31_t)0xb541bbcd, (q31_t)0x67da79c3, (q31_t)0xb52d561e, (q31_t)0x67cbc6c0, (q31_t)0xb518f351,
+  (q31_t)0x67bd0fbd, (q31_t)0xb5049368, (q31_t)0x67ae54ba, (q31_t)0xb4f03663, (q31_t)0x679f95b7, (q31_t)0xb4dbdc42, (q31_t)0x6790d2b6, (q31_t)0xb4c78507,
+  (q31_t)0x67820bb7, (q31_t)0xb4b330b3, (q31_t)0x677340ba, (q31_t)0xb49edf45, (q31_t)0x676471c0, (q31_t)0xb48a90c0, (q31_t)0x67559eca, (q31_t)0xb4764523,
+  (q31_t)0x6746c7d8, (q31_t)0xb461fc70, (q31_t)0x6737ecea, (q31_t)0xb44db6a8, (q31_t)0x67290e02, (q31_t)0xb43973ca, (q31_t)0x671a2b20, (q31_t)0xb42533d8,
+  (q31_t)0x670b4444, (q31_t)0xb410f6d3, (q31_t)0x66fc596f, (q31_t)0xb3fcbcbb, (q31_t)0x66ed6aa1, (q31_t)0xb3e88592, (q31_t)0x66de77dc, (q31_t)0xb3d45157,
+  (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x66c0866d, (q31_t)0xb3abf1b2, (q31_t)0x66b187c3, (q31_t)0xb397c649, (q31_t)0x66a28524, (q31_t)0xb3839dd3,
+  (q31_t)0x66937e91, (q31_t)0xb36f784f, (q31_t)0x66847408, (q31_t)0xb35b55bf, (q31_t)0x6675658c, (q31_t)0xb3473623, (q31_t)0x6666531d, (q31_t)0xb333197c,
+  (q31_t)0x66573cbb, (q31_t)0xb31effcc, (q31_t)0x66482267, (q31_t)0xb30ae912, (q31_t)0x66390422, (q31_t)0xb2f6d550, (q31_t)0x6629e1ec, (q31_t)0xb2e2c486,
+  (q31_t)0x661abbc5, (q31_t)0xb2ceb6b5, (q31_t)0x660b91af, (q31_t)0xb2baabde, (q31_t)0x65fc63a9, (q31_t)0xb2a6a402, (q31_t)0x65ed31b5, (q31_t)0xb2929f21,
+  (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x65cec204, (q31_t)0xb26a9e54, (q31_t)0x65bf8447, (q31_t)0xb256a26a, (q31_t)0x65b0429f, (q31_t)0xb242a97e,
+  (q31_t)0x65a0fd0b, (q31_t)0xb22eb392, (q31_t)0x6591b38c, (q31_t)0xb21ac0a6, (q31_t)0x65826622, (q31_t)0xb206d0ba, (q31_t)0x657314cf, (q31_t)0xb1f2e3d0,
+  (q31_t)0x6563bf92, (q31_t)0xb1def9e9, (q31_t)0x6554666d, (q31_t)0xb1cb1304, (q31_t)0x6545095f, (q31_t)0xb1b72f23, (q31_t)0x6535a86b, (q31_t)0xb1a34e47,
+  (q31_t)0x6526438f, (q31_t)0xb18f7071, (q31_t)0x6516dacd, (q31_t)0xb17b95a0, (q31_t)0x65076e25, (q31_t)0xb167bdd7, (q31_t)0x64f7fd98, (q31_t)0xb153e915,
+  (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x64d910d1, (q31_t)0xb12c48ab, (q31_t)0x64c99498, (q31_t)0xb1187d05, (q31_t)0x64ba147d, (q31_t)0xb104b46a,
+  (q31_t)0x64aa907f, (q31_t)0xb0f0eeda, (q31_t)0x649b08a0, (q31_t)0xb0dd2c56, (q31_t)0x648b7ce0, (q31_t)0xb0c96ce0, (q31_t)0x647bed3f, (q31_t)0xb0b5b077,
+  (q31_t)0x646c59bf, (q31_t)0xb0a1f71d, (q31_t)0x645cc260, (q31_t)0xb08e40d2, (q31_t)0x644d2722, (q31_t)0xb07a8d97, (q31_t)0x643d8806, (q31_t)0xb066dd6d,
+  (q31_t)0x642de50d, (q31_t)0xb0533055, (q31_t)0x641e3e38, (q31_t)0xb03f864f, (q31_t)0x640e9386, (q31_t)0xb02bdf5c, (q31_t)0x63fee4f8, (q31_t)0xb0183b7d,
+  (q31_t)0x63ef3290, (q31_t)0xb0049ab3, (q31_t)0x63df7c4d, (q31_t)0xaff0fcfe, (q31_t)0x63cfc231, (q31_t)0xafdd625f, (q31_t)0x63c0043b, (q31_t)0xafc9cad7,
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+  (q31_t)0x637114cc, (q31_t)0xaf6803a2, (q31_t)0x63613fcd, (q31_t)0xaf547eb3, (q31_t)0x635166f9, (q31_t)0xaf40fce1, (q31_t)0x63418a50, (q31_t)0xaf2d7e2b,
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+  (q31_t)0x5f5e0db3, (q31_t)0xaa9fbf1e, (q31_t)0x5f4d4865, (q31_t)0xaa8d0713, (q31_t)0x5f3c7f6b, (q31_t)0xaa7a5253, (q31_t)0x5f2bb2c5, (q31_t)0xaa67a0e0,
+  (q31_t)0x5f1ae274, (q31_t)0xaa54f2ba, (q31_t)0x5f0a0e77, (q31_t)0xaa4247e1, (q31_t)0x5ef936d1, (q31_t)0xaa2fa056, (q31_t)0x5ee85b82, (q31_t)0xaa1cfc1a,
+  (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5ec699e9, (q31_t)0xa9f7bd92, (q31_t)0x5eb5b3a2, (q31_t)0xa9e52347, (q31_t)0x5ea4c9b3, (q31_t)0xa9d28c4e,
+  (q31_t)0x5e93dc1f, (q31_t)0xa9bff8a8, (q31_t)0x5e82eae5, (q31_t)0xa9ad6855, (q31_t)0x5e71f606, (q31_t)0xa99adb56, (q31_t)0x5e60fd84, (q31_t)0xa98851ac,
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+  (q31_t)0x5e0bec6e, (q31_t)0xa92bd367, (q31_t)0x5dfade20, (q31_t)0xa9195dc7, (q31_t)0x5de9cc33, (q31_t)0xa906eb82, (q31_t)0x5dd8b6a7, (q31_t)0xa8f47c97,
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+  (q31_t)0x5cf95638, (q31_t)0xa8060d08, (q31_t)0x5ce80e41, (q31_t)0xa7f3cd59, (q31_t)0x5cd6c2b5, (q31_t)0xa7e1910f, (q31_t)0x5cc57394, (q31_t)0xa7cf582a,
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+  (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x5208c36a, (q31_t)0x9dbe4701, (q31_t)0x51f576ea, (q31_t)0x9dae2d68, (q31_t)0x51e22740, (q31_t)0x9d9e179a,
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+  (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x50d281d5, (q31_t)0x9cbe75b0, (q31_t)0x50bf031f, (q31_t)0x9cae9907, (q31_t)0x50ab814d, (q31_t)0x9c9ec033,
+  (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x50847454, (q31_t)0x9c7f1a0a, (q31_t)0x5070e92f, (q31_t)0x9c6f4cb6, (q31_t)0x505d5af1, (q31_t)0x9c5f8339,
+  (q31_t)0x5049c999, (q31_t)0x9c4fbd93, (q31_t)0x50363529, (q31_t)0x9c3ffbc5, (q31_t)0x50229da1, (q31_t)0x9c303dcf, (q31_t)0x500f0302, (q31_t)0x9c2083b3,
+  (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4fe7c483, (q31_t)0x9c011b08, (q31_t)0x4fd420a4, (q31_t)0x9bf16c7a, (q31_t)0x4fc079b1, (q31_t)0x9be1c1c8,
+  (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4f992293, (q31_t)0x9bc277fa, (q31_t)0x4f857269, (q31_t)0x9bb2d8de, (q31_t)0x4f71bf2e, (q31_t)0x9ba33da0,
+  (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f4a4f89, (q31_t)0x9b8412c1, (q31_t)0x4f369320, (q31_t)0x9b748320, (q31_t)0x4f22d3aa, (q31_t)0x9b64f760,
+  (q31_t)0x4f0f1126, (q31_t)0x9b556f81, (q31_t)0x4efb4b96, (q31_t)0x9b45eb83, (q31_t)0x4ee782fb, (q31_t)0x9b366b68, (q31_t)0x4ed3b755, (q31_t)0x9b26ef2f,
+  (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4eac16eb, (q31_t)0x9b080268, (q31_t)0x4e984229, (q31_t)0x9af891db, (q31_t)0x4e846a60, (q31_t)0x9ae92533,
+  (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e5cb1b9, (q31_t)0x9aca5795, (q31_t)0x4e48d0dd, (q31_t)0x9abaf6a1, (q31_t)0x4e34ecfc, (q31_t)0x9aab9993,
+  (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4e0d1c30, (q31_t)0x9a8ceb31, (q31_t)0x4df92f46, (q31_t)0x9a7d99de, (q31_t)0x4de53f5a, (q31_t)0x9a6e4c74,
+  (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5, (q31_t)0x4dbd5682, (q31_t)0x9a4fbd61, (q31_t)0x4da95d96, (q31_t)0x9a407bb9, (q31_t)0x4d9561ac, (q31_t)0x9a313dfc,
+  (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d6d60df, (q31_t)0x9a12ce4b, (q31_t)0x4d595bfe, (q31_t)0x9a039c57, (q31_t)0x4d455422, (q31_t)0x99f46e51,
+  (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4d1d3b7a, (q31_t)0x99d61e14, (q31_t)0x4d092ab0, (q31_t)0x99c6fbde, (q31_t)0x4cf516ee, (q31_t)0x99b7dd99,
+  (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4ccce684, (q31_t)0x9999ace3, (q31_t)0x4cb8c9dd, (q31_t)0x998a9a74, (q31_t)0x4ca4aa41, (q31_t)0x997b8bf8,
+  (q31_t)0x4c9087b1, (q31_t)0x996c816f, (q31_t)0x4c7c622d, (q31_t)0x995d7adc, (q31_t)0x4c6839b7, (q31_t)0x994e783d, (q31_t)0x4c540e4e, (q31_t)0x993f7993,
+  (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4c2baea9, (q31_t)0x99218824, (q31_t)0x4c177a6e, (q31_t)0x9912955f, (q31_t)0x4c034345, (q31_t)0x9903a691,
+  (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4bdacc28, (q31_t)0x98e5d4e0, (q31_t)0x4bc68c36, (q31_t)0x98d6f1fe, (q31_t)0x4bb24958, (q31_t)0x98c81316,
+  (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b89badd, (q31_t)0x98aa6136, (q31_t)0x4b756f40, (q31_t)0x989b8e40, (q31_t)0x4b6120bb, (q31_t)0x988cbf46,
+  (q31_t)0x4b4ccf4d, (q31_t)0x987df449, (q31_t)0x4b387af9, (q31_t)0x986f2d4a, (q31_t)0x4b2423be, (q31_t)0x98606a49, (q31_t)0x4b0fc99d, (q31_t)0x9851ab46,
+  (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4ae70caf, (q31_t)0x98343940, (q31_t)0x4ad2a9e2, (q31_t)0x9825863d, (q31_t)0x4abe4433, (q31_t)0x9816d73b,
+  (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4a957030, (q31_t)0x97f9853d, (q31_t)0x4a8101de, (q31_t)0x97eae242, (q31_t)0x4a6c90ad, (q31_t)0x97dc4349,
+  (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a43a5b0, (q31_t)0x97bf1165, (q31_t)0x4a2f2be6, (q31_t)0x97b07e7a, (q31_t)0x4a1aaf3f, (q31_t)0x97a1ef94,
+  (q31_t)0x4a062fbd, (q31_t)0x979364b5, (q31_t)0x49f1ad61, (q31_t)0x9784dddc, (q31_t)0x49dd282a, (q31_t)0x97765b0a, (q31_t)0x49c8a01b, (q31_t)0x9767dc41,
+  (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x499f8774, (q31_t)0x974aeac6, (q31_t)0x498af6df, (q31_t)0x973c7817, (q31_t)0x49766373, (q31_t)0x972e0971,
+  (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x494d341e, (q31_t)0x97113847, (q31_t)0x49389836, (q31_t)0x9702d5c3, (q31_t)0x4923f97b, (q31_t)0x96f4774b,
+  (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x48fab391, (q31_t)0x96d7c682, (q31_t)0x48e60c62, (q31_t)0x96c97432, (q31_t)0x48d16265, (q31_t)0x96bb25f0,
+  (q31_t)0x48bcb599, (q31_t)0x96acdbbe, (q31_t)0x48a805ff, (q31_t)0x969e959b, (q31_t)0x48935397, (q31_t)0x96905388, (q31_t)0x487e9e64, (q31_t)0x96821585,
+  (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x48552b9b, (q31_t)0x9665a5b4, (q31_t)0x48406e08, (q31_t)0x965773e7, (q31_t)0x482badab, (q31_t)0x9649462d,
+  (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x48022499, (q31_t)0x962cf6f2, (q31_t)0x47ed5be6, (q31_t)0x961ed574, (q31_t)0x47d8906d, (q31_t)0x9610b80a,
+  (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47aef12c, (q31_t)0x95f48977, (q31_t)0x479a1d67, (q31_t)0x95e67850, (q31_t)0x478546de, (q31_t)0x95d86b3f,
+  (q31_t)0x47706d93, (q31_t)0x95ca6247, (q31_t)0x475b9188, (q31_t)0x95bc5d66, (q31_t)0x4746b2bc, (q31_t)0x95ae5c9f, (q31_t)0x4731d131, (q31_t)0x95a05ff0,
+  (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x470805df, (q31_t)0x958472e2, (q31_t)0x46f31c1a, (q31_t)0x95768283, (q31_t)0x46de2f99, (q31_t)0x9568963f,
+  (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46b44e65, (q31_t)0x954cca0c, (q31_t)0x469f59b4, (q31_t)0x953eea1e, (q31_t)0x468a624a, (q31_t)0x95310e4e,
+  (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x46606b4e, (q31_t)0x95156308, (q31_t)0x464b6bbe, (q31_t)0x95079394, (q31_t)0x46366978, (q31_t)0x94f9c83f,
+  (q31_t)0x4621647d, (q31_t)0x94ec010b, (q31_t)0x460c5cce, (q31_t)0x94de3df8, (q31_t)0x45f7526b, (q31_t)0x94d07f05, (q31_t)0x45e24556, (q31_t)0x94c2c435,
+  (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x45b82318, (q31_t)0x94a75afd, (q31_t)0x45a30df0, (q31_t)0x9499ac95, (q31_t)0x458df619, (q31_t)0x948c0252,
+  (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x4563be60, (q31_t)0x9470ba39, (q31_t)0x454e9e80, (q31_t)0x94631c65, (q31_t)0x45397bf4, (q31_t)0x945582b7,
+  (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x450f2edb, (q31_t)0x943a5bcf, (q31_t)0x44fa0450, (q31_t)0x942cce96, (q31_t)0x44e4d71c, (q31_t)0x941f4585,
+  (q31_t)0x44cfa740, (q31_t)0x9411c09e, (q31_t)0x44ba74bd, (q31_t)0x94043fdf, (q31_t)0x44a53f93, (q31_t)0x93f6c34a, (q31_t)0x449007c4, (q31_t)0x93e94adf,
+  (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x44659039, (q31_t)0x93ce668b, (q31_t)0x4450507e, (q31_t)0x93c0faa3, (q31_t)0x443b0e21, (q31_t)0x93b392e6,
+  (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x44108184, (q31_t)0x9398cff5, (q31_t)0x43fb3746, (q31_t)0x938b74c1, (q31_t)0x43e5ea68, (q31_t)0x937e1dbb,
+  (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x43bb48d4, (q31_t)0x93637c3d, (q31_t)0x43a5f41e, (q31_t)0x935631c5, (q31_t)0x43909ccd, (q31_t)0x9348eb7e,
+  (q31_t)0x437b42e1, (q31_t)0x933ba968, (q31_t)0x4365e65b, (q31_t)0x932e6b84, (q31_t)0x4350873c, (q31_t)0x932131d1, (q31_t)0x433b2585, (q31_t)0x9313fc51,
+  (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x43105a50, (q31_t)0x92f99deb, (q31_t)0x42faf0d4, (q31_t)0x92ec7505, (q31_t)0x42e584c3, (q31_t)0x92df5054,
+  (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x42baa4e6, (q31_t)0x92c51392, (q31_t)0x42a5311b, (q31_t)0x92b7fb82, (q31_t)0x428fbabe, (q31_t)0x92aae7a8,
+  (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x4264c653, (q31_t)0x9290cc9b, (q31_t)0x424f4845, (q31_t)0x9283c568, (q31_t)0x4239c7aa, (q31_t)0x9276c26d,
+  (q31_t)0x42244481, (q31_t)0x9269c3ac, (q31_t)0x420ebecb, (q31_t)0x925cc924, (q31_t)0x41f93689, (q31_t)0x924fd2d7, (q31_t)0x41e3abbc, (q31_t)0x9242e0c4,
+  (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x41b88e84, (q31_t)0x9229094f, (q31_t)0x41a2fc1a, (q31_t)0x921c23ef, (q31_t)0x418d6729, (q31_t)0x920f42cb,
+  (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x416235b2, (q31_t)0x91f58d3b, (q31_t)0x414c992f, (q31_t)0x91e8b8d0, (q31_t)0x4136fa27, (q31_t)0x91dbe8a4,
+  (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x410bb48c, (q31_t)0x91c25508, (q31_t)0x40f60dfb, (q31_t)0x91b5919a, (q31_t)0x40e064ea, (q31_t)0x91a8d26d,
+  (q31_t)0x40cab958, (q31_t)0x919c1781, (q31_t)0x40b50b46, (q31_t)0x918f60d6, (q31_t)0x409f5ab6, (q31_t)0x9182ae6d, (q31_t)0x4089a7a8, (q31_t)0x91760047,
+  (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x405e3a16, (q31_t)0x915cb0c3, (q31_t)0x40487f94, (q31_t)0x91500f67, (q31_t)0x4032c297, (q31_t)0x91437250,
+  (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x40074132, (q31_t)0x912a44f0, (q31_t)0x3ff17cca, (q31_t)0x911db4a9, (q31_t)0x3fdbb5ec, (q31_t)0x911128a8,
+  (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3fb020ce, (q31_t)0x90f81d7b, (q31_t)0x3f9a5290, (q31_t)0x90eb9e50, (q31_t)0x3f8481dd, (q31_t)0x90df236e,
+  (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4, (q31_t)0x3f58d921, (q31_t)0x90c63a83, (q31_t)0x3f430119, (q31_t)0x90b9cc7d, (q31_t)0x3f2d26a0, (q31_t)0x90ad62c0,
+  (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3f016a61, (q31_t)0x90949c28, (q31_t)0x3eeb889c, (q31_t)0x90883f4d, (q31_t)0x3ed5a46b, (q31_t)0x907be6be,
+  (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3ea9d4c3, (q31_t)0x90634287, (q31_t)0x3e93e950, (q31_t)0x9056f6df, (q31_t)0x3e7dfb73, (q31_t)0x904aaf86,
+  (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e52187f, (q31_t)0x90322dbf, (q31_t)0x3e3c2369, (q31_t)0x9025f352, (q31_t)0x3e262bee, (q31_t)0x9019bd36,
+  (q31_t)0x3e10320d, (q31_t)0x900d8b69, (q31_t)0x3dfa35c8, (q31_t)0x90015dee, (q31_t)0x3de4371f, (q31_t)0x8ff534c4, (q31_t)0x3dce3614, (q31_t)0x8fe90fec,
+  (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3da22cd7, (q31_t)0x8fd0d333, (q31_t)0x3d8c24a8, (q31_t)0x8fc4bb53, (q31_t)0x3d761a19, (q31_t)0x8fb8a7c7,
+  (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d49fde1, (q31_t)0x8fa08dab, (q31_t)0x3d33ec39, (q31_t)0x8f94871d, (q31_t)0x3d1dd835, (q31_t)0x8f8884e4,
+  (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3cf1a91c, (q31_t)0x8f708d75, (q31_t)0x3cdb8e09, (q31_t)0x8f649840, (q31_t)0x3cc5709e, (q31_t)0x8f58a761,
+  (q31_t)0x3caf50da, (q31_t)0x8f4cbadb, (q31_t)0x3c992ec0, (q31_t)0x8f40d2ad, (q31_t)0x3c830a50, (q31_t)0x8f34eed8, (q31_t)0x3c6ce38a, (q31_t)0x8f290f5c,
+  (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3c408f03, (q31_t)0x8f115d72, (q31_t)0x3c2a6142, (q31_t)0x8f058b04, (q31_t)0x3c143130, (q31_t)0x8ef9bcf2,
+  (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3be7ca1a, (q31_t)0x8ee22de0, (q31_t)0x3bd19318, (q31_t)0x8ed66ce1, (q31_t)0x3bbb59c7, (q31_t)0x8ecab040,
+  (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b8ee03e, (q31_t)0x8eb34415, (q31_t)0x3b78a007, (q31_t)0x8ea7948c, (q31_t)0x3b625d86, (q31_t)0x8e9be963,
+  (q31_t)0x3b4c18ba, (q31_t)0x8e904298, (q31_t)0x3b35d1a5, (q31_t)0x8e84a02d, (q31_t)0x3b1f8848, (q31_t)0x8e790222, (q31_t)0x3b093ca3, (q31_t)0x8e6d6877,
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+  (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x25d0439f, (q31_t)0x85b68015, (q31_t)0x25b84012, (q31_t)0x85af15b9, (q31_t)0x25a03b11, (q31_t)0x85a7b015,
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+  (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x250ffeb7, (q31_t)0x857bb152, (q31_t)0x24f7efa2, (q31_t)0x85746cb8, (q31_t)0x24dfdf20, (q31_t)0x856d2cd7,
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+  (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x244f5e5c, (q31_t)0x854210db, (q31_t)0x243743fa, (q31_t)0x853af214, (q31_t)0x241f2833, (q31_t)0x8533d809,
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+  (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22cd12bd, (q31_t)0x84d25d06, (q31_t)0x22b4e274, (q31_t)0x84cb8a1b, (q31_t)0x229cb0d5, (q31_t)0x84c4bbf0,
+  (q31_t)0x22847de0, (q31_t)0x84bdf286, (q31_t)0x226c4996, (q31_t)0x84b72ddb, (q31_t)0x225413f8, (q31_t)0x84b06df2, (q31_t)0x223bdd08, (q31_t)0x84a9b2ca,
+  (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x220b6b32, (q31_t)0x849c4abd, (q31_t)0x21f3304f, (q31_t)0x84959dd9, (q31_t)0x21daf41d, (q31_t)0x848ef5b7,
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+  (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x21496fa7, (q31_t)0x846768e7, (q31_t)0x21312a65, (q31_t)0x8460e21a, (q31_t)0x2118e3dc, (q31_t)0x845a6012,
+  (q31_t)0x21009c0c, (q31_t)0x8453e2cf, (q31_t)0x20e852f6, (q31_t)0x844d6a50, (q31_t)0x20d0089c, (q31_t)0x8446f695, (q31_t)0x20b7bcfe, (q31_t)0x844087a0,
+  (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x208721f9, (q31_t)0x8433b806, (q31_t)0x206ed295, (q31_t)0x842d5762, (q31_t)0x205681f1, (q31_t)0x8426fb84,
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+  (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1fc4840a, (q31_t)0x8401389b, (q31_t)0x1fac2abf, (q31_t)0x83fafe2e, (q31_t)0x1f93d03c, (q31_t)0x83f4c889,
+  (q31_t)0x1f7b7481, (q31_t)0x83ee97ad, (q31_t)0x1f63178f, (q31_t)0x83e86b99, (q31_t)0x1f4ab968, (q31_t)0x83e2444d, (q31_t)0x1f325a0b, (q31_t)0x83dc21cb,
+  (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1f0197b8, (q31_t)0x83cfeb22, (q31_t)0x1ee934c3, (q31_t)0x83c9d6fc, (q31_t)0x1ed0d09d, (q31_t)0x83c3c7a0,
+  (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1ea004c1, (q31_t)0x83b7b746, (q31_t)0x1e879d0d, (q31_t)0x83b1b649, (q31_t)0x1e6f342c, (q31_t)0x83abba17,
+  (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1e3e5ee5, (q31_t)0x839fd014, (q31_t)0x1e25f282, (q31_t)0x8399e244, (q31_t)0x1e0d84f5, (q31_t)0x8393f940,
+  (q31_t)0x1df5163f, (q31_t)0x838e1507, (q31_t)0x1ddca662, (q31_t)0x8388359b, (q31_t)0x1dc4355e, (q31_t)0x83825afb, (q31_t)0x1dabc334, (q31_t)0x837c8528,
+  (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d7adb73, (q31_t)0x8370e7e9, (q31_t)0x1d6265dd, (q31_t)0x836b207d, (q31_t)0x1d49ef26, (q31_t)0x83655ddf,
+  (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1d18fe54, (q31_t)0x8359e70d, (q31_t)0x1d00843d, (q31_t)0x835432d8, (q31_t)0x1ce80906, (q31_t)0x834e8373,
+  (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1cb70f43, (q31_t)0x83433314, (q31_t)0x1c9e90b8, (q31_t)0x833d921b, (q31_t)0x1c861113, (q31_t)0x8337f5f1,
+  (q31_t)0x1c6d9053, (q31_t)0x83325e97, (q31_t)0x1c550e7c, (q31_t)0x832ccc0d, (q31_t)0x1c3c8b8c, (q31_t)0x83273e52, (q31_t)0x1c240786, (q31_t)0x8321b568,
+  (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1bf2fc3a, (q31_t)0x8316b205, (q31_t)0x1bda74f6, (q31_t)0x8311378d, (q31_t)0x1bc1ec9e, (q31_t)0x830bc1e6,
+  (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1b90d8bb, (q31_t)0x8300e50b, (q31_t)0x1b784d30, (q31_t)0x82fb7dd8, (q31_t)0x1b5fc097, (q31_t)0x82f61b77,
+  (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1b2ea43a, (q31_t)0x82eb652b, (q31_t)0x1b161479, (q31_t)0x82e61141, (q31_t)0x1afd83ad, (q31_t)0x82e0c22a,
+  (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5, (q31_t)0x1acc5ef6, (q31_t)0x82d63274, (q31_t)0x1ab3cb0d, (q31_t)0x82d0f1d5, (q31_t)0x1a9b361d, (q31_t)0x82cbb60b,
+  (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a6a0929, (q31_t)0x82c14cf1, (q31_t)0x1a517128, (q31_t)0x82bc1fa2, (q31_t)0x1a38d823, (q31_t)0x82b6f727,
+  (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x1a07a311, (q31_t)0x82acb4b0, (q31_t)0x19ef0707, (q31_t)0x82a79ab3, (q31_t)0x19d669fc, (q31_t)0x82a2858c,
+  (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x19a52ceb, (q31_t)0x829869be, (q31_t)0x198c8ce7, (q31_t)0x82936317, (q31_t)0x1973ebe6, (q31_t)0x828e6146,
+  (q31_t)0x195b49ea, (q31_t)0x8289644b, (q31_t)0x1942a6f3, (q31_t)0x82846c26, (q31_t)0x192a0304, (q31_t)0x827f78d8, (q31_t)0x19115e1c, (q31_t)0x827a8a61,
+  (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18e01167, (q31_t)0x8270bbf7, (q31_t)0x18c7699b, (q31_t)0x826bdc04, (q31_t)0x18aec0db, (q31_t)0x826700e9,
+  (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x187d6c82, (q31_t)0x825d593a, (q31_t)0x1864c0ea, (q31_t)0x82588ca7, (q31_t)0x184c1461, (q31_t)0x8253c4eb,
+  (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x181ab881, (q31_t)0x824a43fe, (q31_t)0x1802092c, (q31_t)0x82458acc, (q31_t)0x17e958ea, (q31_t)0x8240d673,
+  (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, (q31_t)0x17b7f5a3, (q31_t)0x82377c4c, (q31_t)0x179f429f, (q31_t)0x8232d67f, (q31_t)0x17868eb3, (q31_t)0x822e358b,
+  (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x17552422, (q31_t)0x82250232, (q31_t)0x173c6d80, (q31_t)0x82206fcc, (q31_t)0x1723b5f9, (q31_t)0x821be240,
+  (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16f2443e, (q31_t)0x8212d5b9, (q31_t)0x16d98a0c, (q31_t)0x820e56be, (q31_t)0x16c0cef9, (q31_t)0x8209dc9e,
+  (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x168f5632, (q31_t)0x8200f6ef, (q31_t)0x1676987f, (q31_t)0x81fc8b60, (q31_t)0x165dd9f0, (q31_t)0x81f824ae,
+  (q31_t)0x16451a83, (q31_t)0x81f3c2d7, (q31_t)0x162c5a3b, (q31_t)0x81ef65dc, (q31_t)0x16139918, (q31_t)0x81eb0dbe, (q31_t)0x15fad71b, (q31_t)0x81e6ba7c,
+  (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x15c95097, (q31_t)0x81de228d, (q31_t)0x15b08c12, (q31_t)0x81d9dde1, (q31_t)0x1597c6b7, (q31_t)0x81d59e13,
+  (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x15663982, (q31_t)0x81cd2d0c, (q31_t)0x154d71aa, (q31_t)0x81c8fbd6, (q31_t)0x1534a901, (q31_t)0x81c4cf7d,
+  (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x1503153a, (q31_t)0x81bc8564, (q31_t)0x14ea4a1f, (q31_t)0x81b867a5, (q31_t)0x14d17e36, (q31_t)0x81b44ec4,
+  (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, (q31_t)0x149fe3fc, (q31_t)0x81ac2b9e, (q31_t)0x148715ae, (q31_t)0x81a82159, (q31_t)0x146e4694, (q31_t)0x81a41bf4,
+  (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x143ca605, (q31_t)0x819c1fc5, (q31_t)0x1423d492, (q31_t)0x819828fd, (q31_t)0x140b0258, (q31_t)0x81943715,
+  (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x13d95b93, (q31_t)0x818c61e3, (q31_t)0x13c0870a, (q31_t)0x81887e9a, (q31_t)0x13a7b1bf, (q31_t)0x8184a032,
+  (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x137604e2, (q31_t)0x817cf201, (q31_t)0x135d2d53, (q31_t)0x8179223a, (q31_t)0x13445505, (q31_t)0x81755754,
+  (q31_t)0x132b7bf9, (q31_t)0x8171914e, (q31_t)0x1312a230, (q31_t)0x816dd02a, (q31_t)0x12f9c7aa, (q31_t)0x816a13e6, (q31_t)0x12e0ec6a, (q31_t)0x81665c84,
+  (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x12af33ba, (q31_t)0x815efc65, (q31_t)0x1296564d, (q31_t)0x815b53a8, (q31_t)0x127d7829, (q31_t)0x8157afcd,
+  (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x124bb9be, (q31_t)0x815076bd, (q31_t)0x1232d979, (q31_t)0x814ce188, (q31_t)0x1219f880, (q31_t)0x81495136,
+  (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x11e83478, (q31_t)0x81423f3a, (q31_t)0x11cf516a, (q31_t)0x813ebd90, (q31_t)0x11b66dad, (q31_t)0x813b40ca,
+  (q31_t)0x119d8941, (q31_t)0x8137c8e6, (q31_t)0x1184a427, (q31_t)0x813455e6, (q31_t)0x116bbe60, (q31_t)0x8130e7c9, (q31_t)0x1152d7ed, (q31_t)0x812d7e8f,
+  (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x11210907, (q31_t)0x8126bac8, (q31_t)0x11082096, (q31_t)0x8123603a, (q31_t)0x10ef377d, (q31_t)0x81200a90,
+  (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x10bd6356, (q31_t)0x81196de9, (q31_t)0x10a4784b, (q31_t)0x811626ec, (q31_t)0x108b8c9b, (q31_t)0x8112e4d4,
+  (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x1059b352, (q31_t)0x810c6f52, (q31_t)0x1040c5bb, (q31_t)0x81093be8, (q31_t)0x1027d784, (q31_t)0x81060d63,
+  (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, (q31_t)0xff5f938, (q31_t)0x80ffbf0a, (q31_t)0xfdd0926, (q31_t)0x80fc9f35, (q31_t)0xfc41876, (q31_t)0x80f98446,
+  (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xf923546, (q31_t)0x80f35d19, (q31_t)0xf7942c7, (q31_t)0x80f050db, (q31_t)0xf604faf, (q31_t)0x80ed4984,
+  (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xf2e67b8, (q31_t)0x80e74987, (q31_t)0xf1572dc, (q31_t)0x80e450e2, (q31_t)0xefc7d6b, (q31_t)0x80e15d24,
+  (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xeca90ce, (q31_t)0x80db845b, (q31_t)0xeb199a4, (q31_t)0x80d89f51, (q31_t)0xe98a1e9, (q31_t)0x80d5bf2e,
+  (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2, (q31_t)0xe66b0c3, (q31_t)0x80d00d9d, (q31_t)0xe4db75b, (q31_t)0x80cd3c2f, (q31_t)0xe34bd66, (q31_t)0x80ca6fa9,
+  (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xe02c7d7, (q31_t)0x80c4e553, (q31_t)0xde9cc40, (q31_t)0x80c22784, (q31_t)0xdd0d01f, (q31_t)0x80bf6e9c,
+  (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xd9ed646, (q31_t)0x80ba0b85, (q31_t)0xd85d88f, (q31_t)0x80b76156, (q31_t)0xd6cda53, (q31_t)0x80b4bc0e,
+  (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xd3adc4e, (q31_t)0x80af8039, (q31_t)0xd21dc87, (q31_t)0x80ace9ab, (q31_t)0xd08dc3f, (q31_t)0x80aa5806,
+  (q31_t)0xcefdb76, (q31_t)0x80a7cb49, (q31_t)0xcd6da2d, (q31_t)0x80a54376, (q31_t)0xcbdd865, (q31_t)0x80a2c08b, (q31_t)0xca4d620, (q31_t)0x80a04289,
+  (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc72d020, (q31_t)0x809b5541, (q31_t)0xc59cc68, (q31_t)0x8098e5fb, (q31_t)0xc40c835, (q31_t)0x80967b9f,
+  (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xc0ebe66, (q31_t)0x8091b5a2, (q31_t)0xbf5b8cb, (q31_t)0x808f5a02, (q31_t)0xbdcb2bb, (q31_t)0x808d034c,
+  (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xbaaa53b, (q31_t)0x8088649e, (q31_t)0xb919dcf, (q31_t)0x80861ca6, (q31_t)0xb7895f0, (q31_t)0x8083d998,
+  (q31_t)0xb5f8d9f, (q31_t)0x80819b74, (q31_t)0xb4684df, (q31_t)0x807f623b, (q31_t)0xb2d7baf, (q31_t)0x807d2dec, (q31_t)0xb147211, (q31_t)0x807afe87,
+  (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xae25d8d, (q31_t)0x8076ae7e, (q31_t)0xac952aa, (q31_t)0x80748dd9, (q31_t)0xab0475c, (q31_t)0x8072721f,
+  (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa7e2f85, (q31_t)0x806e496c, (q31_t)0xa6522fe, (q31_t)0x806c3c74, (q31_t)0xa4c1610, (q31_t)0x806a3466,
+  (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0xa19fb04, (q31_t)0x8066330c, (q31_t)0xa00ece8, (q31_t)0x806439c0, (q31_t)0x9e7de6a, (q31_t)0x80624560,
+  (q31_t)0x9cecf89, (q31_t)0x806055eb, (q31_t)0x9b5c048, (q31_t)0x805e6b62, (q31_t)0x99cb0a7, (q31_t)0x805c85c4, (q31_t)0x983a0a7, (q31_t)0x805aa512,
+  (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9517f8f, (q31_t)0x8056f272, (q31_t)0x9386e78, (q31_t)0x80552084, (q31_t)0x91f5d06, (q31_t)0x80535381,
+  (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x8ed3916, (q31_t)0x804fc841, (q31_t)0x8d42699, (q31_t)0x804e0a04, (q31_t)0x8bb13c5, (q31_t)0x804c50b2,
+  (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x888ed1b, (q31_t)0x8048ecd5, (q31_t)0x86fd947, (q31_t)0x80474248, (q31_t)0x856c520, (q31_t)0x80459ca9,
+  (q31_t)0x83db0a7, (q31_t)0x8043fbf6, (q31_t)0x8249bdd, (q31_t)0x80426030, (q31_t)0x80b86c2, (q31_t)0x8040c956, (q31_t)0x7f27157, (q31_t)0x803f376a,
+  (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x7c04598, (q31_t)0x803c2257, (q31_t)0x7a72f45, (q31_t)0x803a9f31, (q31_t)0x78e18a7, (q31_t)0x803920f8,
+  (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x75bea8c, (q31_t)0x8036334e, (q31_t)0x742d311, (q31_t)0x8034c3dd, (q31_t)0x729bb4e, (q31_t)0x80335959,
+  (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x6f78af6, (q31_t)0x80309318, (q31_t)0x6de7262, (q31_t)0x802f375d, (q31_t)0x6c5598a, (q31_t)0x802de08e,
+  (q31_t)0x6ac406f, (q31_t)0x802c8ead, (q31_t)0x6932713, (q31_t)0x802b41ba, (q31_t)0x67a0d76, (q31_t)0x8029f9b4, (q31_t)0x660f398, (q31_t)0x8028b69c,
+  (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x62ebf22, (q31_t)0x80263f36, (q31_t)0x615a48b, (q31_t)0x80250ae7, (q31_t)0x5fc89b8, (q31_t)0x8023db86,
+  (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x5ca5361, (q31_t)0x80218b8f, (q31_t)0x5b137df, (q31_t)0x80206af8, (q31_t)0x5981c26, (q31_t)0x801f4f4f,
+  (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x565e40d, (q31_t)0x801d26c8, (q31_t)0x54cc7b1, (q31_t)0x801c19ea, (q31_t)0x533ab20, (q31_t)0x801b11fa,
+  (q31_t)0x51a8e5c, (q31_t)0x801a0ef8, (q31_t)0x5017165, (q31_t)0x801910e4, (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4cf36e5, (q31_t)0x80172388,
+  (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x46abfb3, (q31_t)0x801383fe,
+  (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x40645c7, (q31_t)0x8010335c,
+  (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3a1c960, (q31_t)0x800d31a5,
+  (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x33d4abb, (q31_t)0x800a7edb,
+  (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2d8ca16, (q31_t)0x80081b00,
+  (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x27447b0, (q31_t)0x80060614,
+  (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x20fc3c6, (q31_t)0x8004401a,
+  (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1ab3e97, (q31_t)0x8002c912,
+  (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x146b860, (q31_t)0x8001a0fd,
+  (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0xfb5330, (q31_t)0x8000f6bd, (q31_t)0xe23160, (q31_t)0x8000c7dc,
+  (q31_t)0xc90f88, (q31_t)0x80009dea, (q31_t)0xafeda8, (q31_t)0x800078e7, (q31_t)0x96cbc1, (q31_t)0x800058d4, (q31_t)0x7da9d4, (q31_t)0x80003daf,
+  (q31_t)0x6487e3, (q31_t)0x8000277a, (q31_t)0x4b65ee, (q31_t)0x80001635, (q31_t)0x3243f5, (q31_t)0x800009df, (q31_t)0x1921fb, (q31_t)0x80000278
+};
+
+static const q31_t WeightsQ31_8192[16384] = {
+  (q31_t)0x7fffffff, (q31_t)0x0, (q31_t)0x7fffffd9, (q31_t)0xfff9b781, (q31_t)0x7fffff62, (q31_t)0xfff36f02, (q31_t)0x7ffffe9d,
+    (q31_t)0xffed2684,
+  (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffffc25, (q31_t)0xffe09586, (q31_t)0x7ffffa73, (q31_t)0xffda4d08,
+    (q31_t)0x7ffff872, (q31_t)0xffd40489,
+  (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7ffff382, (q31_t)0xffc7738c, (q31_t)0x7ffff094, (q31_t)0xffc12b0e,
+    (q31_t)0x7fffed57, (q31_t)0xffbae290,
+  (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, (q31_t)0x7fffe5f0, (q31_t)0xffae5195, (q31_t)0x7fffe1c6, (q31_t)0xffa80917,
+    (q31_t)0x7fffdd4d, (q31_t)0xffa1c09a,
+  (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffd36f, (q31_t)0xff952fa0, (q31_t)0x7fffce09, (q31_t)0xff8ee724,
+    (q31_t)0x7fffc854, (q31_t)0xff889ea7,
+  (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffbbfe, (q31_t)0xff7c0db0, (q31_t)0x7fffb55c, (q31_t)0xff75c535,
+    (q31_t)0x7fffae6c, (q31_t)0xff6f7cba,
+  (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff9f9e, (q31_t)0xff62ebc5, (q31_t)0x7fff97c1, (q31_t)0xff5ca34b,
+    (q31_t)0x7fff8f94, (q31_t)0xff565ad1,
+  (q31_t)0x7fff8719, (q31_t)0xff501258, (q31_t)0x7fff7e4f, (q31_t)0xff49c9df, (q31_t)0x7fff7536, (q31_t)0xff438167,
+    (q31_t)0x7fff6bcd, (q31_t)0xff3d38ef,
+  (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff5810, (q31_t)0xff30a801, (q31_t)0x7fff4dbb, (q31_t)0xff2a5f8b,
+    (q31_t)0x7fff4317, (q31_t)0xff241715,
+  (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff2ce2, (q31_t)0xff17862b, (q31_t)0x7fff2151, (q31_t)0xff113db7,
+    (q31_t)0x7fff1572, (q31_t)0xff0af543,
+  (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffefcc5, (q31_t)0xfefe645e, (q31_t)0x7ffeeff8, (q31_t)0xfef81bec,
+    (q31_t)0x7ffee2dd, (q31_t)0xfef1d37b,
+  (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, (q31_t)0x7ffec7b9, (q31_t)0xfee5429a, (q31_t)0x7ffeb9b0, (q31_t)0xfedefa2b,
+    (q31_t)0x7ffeab59, (q31_t)0xfed8b1bd,
+  (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe8dbd, (q31_t)0xfecc20e2, (q31_t)0x7ffe7e79, (q31_t)0xfec5d876,
+    (q31_t)0x7ffe6ee5, (q31_t)0xfebf900a,
+  (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe4ed2, (q31_t)0xfeb2ff36, (q31_t)0x7ffe3e52, (q31_t)0xfeacb6cc,
+    (q31_t)0x7ffe2d83, (q31_t)0xfea66e64,
+  (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffe0af8, (q31_t)0xfe99dd96, (q31_t)0x7ffdf93c, (q31_t)0xfe939530,
+    (q31_t)0x7ffde731, (q31_t)0xfe8d4ccb,
+  (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, (q31_t)0x7ffdc22e, (q31_t)0xfe80bc04, (q31_t)0x7ffdaf37, (q31_t)0xfe7a73a2,
+    (q31_t)0x7ffd9bf0, (q31_t)0xfe742b41,
+  (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd7476, (q31_t)0xfe679a81, (q31_t)0x7ffd6042, (q31_t)0xfe615223,
+    (q31_t)0x7ffd4bc0, (q31_t)0xfe5b09c5,
+  (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffd21ce, (q31_t)0xfe4e790d, (q31_t)0x7ffd0c5f, (q31_t)0xfe4830b3,
+    (q31_t)0x7ffcf6a0, (q31_t)0xfe41e85a,
+  (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffcca37, (q31_t)0xfe3557ab, (q31_t)0x7ffcb38c, (q31_t)0xfe2f0f55,
+    (q31_t)0x7ffc9c92, (q31_t)0xfe28c700,
+  (q31_t)0x7ffc8549, (q31_t)0xfe227eac, (q31_t)0x7ffc6db1, (q31_t)0xfe1c365a, (q31_t)0x7ffc55ca, (q31_t)0xfe15ee09,
+    (q31_t)0x7ffc3d94, (q31_t)0xfe0fa5b8,
+  (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffc0c3b, (q31_t)0xfe03151c, (q31_t)0x7ffbf319, (q31_t)0xfdfccccf,
+    (q31_t)0x7ffbd9a7, (q31_t)0xfdf68484,
+  (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffba5d7, (q31_t)0xfde9f3f1, (q31_t)0x7ffb8b78, (q31_t)0xfde3aba9,
+    (q31_t)0x7ffb70cb, (q31_t)0xfddd6363,
+  (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffb3a83, (q31_t)0xfdd0d2db, (q31_t)0x7ffb1ee9, (q31_t)0xfdca8a99,
+    (q31_t)0x7ffb0300, (q31_t)0xfdc44258,
+  (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18, (q31_t)0x7ffaca40, (q31_t)0xfdb7b1da, (q31_t)0x7ffaad6a, (q31_t)0xfdb1699e,
+    (q31_t)0x7ffa9045, (q31_t)0xfdab2162,
+  (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ffa550e, (q31_t)0xfd9e90f0, (q31_t)0x7ffa36fc, (q31_t)0xfd9848b9,
+    (q31_t)0x7ffa189c, (q31_t)0xfd920084,
+  (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff9daed, (q31_t)0xfd85701e, (q31_t)0x7ff9bba0, (q31_t)0xfd7f27ed,
+    (q31_t)0x7ff99c03, (q31_t)0xfd78dfbd,
+  (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff95bdd, (q31_t)0xfd6c4f64, (q31_t)0x7ff93b54, (q31_t)0xfd660739,
+    (q31_t)0x7ff91a7b, (q31_t)0xfd5fbf10,
+  (q31_t)0x7ff8f954, (q31_t)0xfd5976e9, (q31_t)0x7ff8d7de, (q31_t)0xfd532ec3, (q31_t)0x7ff8b619, (q31_t)0xfd4ce69f,
+    (q31_t)0x7ff89405, (q31_t)0xfd469e7c,
+  (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff84ef0, (q31_t)0xfd3a0e3d, (q31_t)0x7ff82bef, (q31_t)0xfd33c61f,
+    (q31_t)0x7ff8089f, (q31_t)0xfd2d7e04,
+  (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff7c113, (q31_t)0xfd20edd2, (q31_t)0x7ff79cd6, (q31_t)0xfd1aa5bc,
+    (q31_t)0x7ff7784a, (q31_t)0xfd145da7,
+  (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff72e46, (q31_t)0xfd07cd83, (q31_t)0x7ff708ce, (q31_t)0xfd018574,
+    (q31_t)0x7ff6e307, (q31_t)0xfcfb3d67,
+  (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c, (q31_t)0x7ff6968b, (q31_t)0xfceead52, (q31_t)0x7ff66fd7, (q31_t)0xfce8654b,
+    (q31_t)0x7ff648d4, (q31_t)0xfce21d45,
+  (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff5f9e1, (q31_t)0xfcd58d3f, (q31_t)0x7ff5d1f1, (q31_t)0xfccf453f,
+    (q31_t)0x7ff5a9b2, (q31_t)0xfcc8fd41,
+  (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff55848, (q31_t)0xfcbc6d4c, (q31_t)0x7ff52f1d, (q31_t)0xfcb62554,
+    (q31_t)0x7ff505a2, (q31_t)0xfcafdd5e,
+  (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4b1c0, (q31_t)0xfca34d78, (q31_t)0x7ff48759, (q31_t)0xfc9d0588,
+    (q31_t)0x7ff45ca3, (q31_t)0xfc96bd9b,
+  (q31_t)0x7ff4319d, (q31_t)0xfc9075af, (q31_t)0x7ff40649, (q31_t)0xfc8a2dc6, (q31_t)0x7ff3daa6, (q31_t)0xfc83e5de,
+    (q31_t)0x7ff3aeb4, (q31_t)0xfc7d9df9,
+  (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff355e4, (q31_t)0xfc710e36, (q31_t)0x7ff32905, (q31_t)0xfc6ac657,
+    (q31_t)0x7ff2fbd7, (q31_t)0xfc647e7b,
+  (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff2a08f, (q31_t)0xfc57eec9, (q31_t)0x7ff27275, (q31_t)0xfc51a6f3,
+    (q31_t)0x7ff2440b, (q31_t)0xfc4b5f20,
+  (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1e64c, (q31_t)0xfc3ecf80, (q31_t)0x7ff1b6f6, (q31_t)0xfc3887b3,
+    (q31_t)0x7ff18751, (q31_t)0xfc323fe9,
+  (q31_t)0x7ff1575d, (q31_t)0xfc2bf821, (q31_t)0x7ff1271a, (q31_t)0xfc25b05c, (q31_t)0x7ff0f688, (q31_t)0xfc1f6899,
+    (q31_t)0x7ff0c5a7, (q31_t)0xfc1920d8,
+  (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7ff062f9, (q31_t)0xfc0c915e, (q31_t)0x7ff0312c, (q31_t)0xfc0649a5,
+    (q31_t)0x7fefff0f, (q31_t)0xfc0001ee,
+  (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7fef99ea, (q31_t)0xfbf37287, (q31_t)0x7fef66e1, (q31_t)0xfbed2ad8,
+    (q31_t)0x7fef3388, (q31_t)0xfbe6e32b,
+  (q31_t)0x7feeffe1, (q31_t)0xfbe09b80, (q31_t)0x7feecbec, (q31_t)0xfbda53d8, (q31_t)0x7fee97a7, (q31_t)0xfbd40c33,
+    (q31_t)0x7fee6313, (q31_t)0xfbcdc490,
+  (q31_t)0x7fee2e30, (q31_t)0xfbc77cf0, (q31_t)0x7fedf8ff, (q31_t)0xfbc13552, (q31_t)0x7fedc37e, (q31_t)0xfbbaedb7,
+    (q31_t)0x7fed8daf, (q31_t)0xfbb4a61f,
+  (q31_t)0x7fed5791, (q31_t)0xfbae5e89, (q31_t)0x7fed2123, (q31_t)0xfba816f6, (q31_t)0x7fecea67, (q31_t)0xfba1cf66,
+    (q31_t)0x7fecb35c, (q31_t)0xfb9b87d8,
+  (q31_t)0x7fec7c02, (q31_t)0xfb95404d, (q31_t)0x7fec4459, (q31_t)0xfb8ef8c5, (q31_t)0x7fec0c62, (q31_t)0xfb88b13f,
+    (q31_t)0x7febd41b, (q31_t)0xfb8269bd,
+  (q31_t)0x7feb9b85, (q31_t)0xfb7c223d, (q31_t)0x7feb62a1, (q31_t)0xfb75dac0, (q31_t)0x7feb296d, (q31_t)0xfb6f9345,
+    (q31_t)0x7feaefeb, (q31_t)0xfb694bce,
+  (q31_t)0x7feab61a, (q31_t)0xfb630459, (q31_t)0x7fea7bfa, (q31_t)0xfb5cbce7, (q31_t)0x7fea418b, (q31_t)0xfb567578,
+    (q31_t)0x7fea06cd, (q31_t)0xfb502e0c,
+  (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe99064, (q31_t)0xfb439f3c, (q31_t)0x7fe954ba, (q31_t)0xfb3d57d9,
+    (q31_t)0x7fe918c0, (q31_t)0xfb371078,
+  (q31_t)0x7fe8dc78, (q31_t)0xfb30c91b, (q31_t)0x7fe89fe0, (q31_t)0xfb2a81c0, (q31_t)0x7fe862fa, (q31_t)0xfb243a69,
+    (q31_t)0x7fe825c5, (q31_t)0xfb1df314,
+  (q31_t)0x7fe7e841, (q31_t)0xfb17abc2, (q31_t)0x7fe7aa6e, (q31_t)0xfb116474, (q31_t)0x7fe76c4c, (q31_t)0xfb0b1d28,
+    (q31_t)0x7fe72ddb, (q31_t)0xfb04d5e0,
+  (q31_t)0x7fe6ef1c, (q31_t)0xfafe8e9b, (q31_t)0x7fe6b00d, (q31_t)0xfaf84758, (q31_t)0x7fe670b0, (q31_t)0xfaf20019,
+    (q31_t)0x7fe63103, (q31_t)0xfaebb8dd,
+  (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe5b0be, (q31_t)0xfadf2a6e, (q31_t)0x7fe57025, (q31_t)0xfad8e33c,
+    (q31_t)0x7fe52f3d, (q31_t)0xfad29c0c,
+  (q31_t)0x7fe4ee06, (q31_t)0xfacc54e0, (q31_t)0x7fe4ac81, (q31_t)0xfac60db7, (q31_t)0x7fe46aac, (q31_t)0xfabfc691,
+    (q31_t)0x7fe42889, (q31_t)0xfab97f6e,
+  (q31_t)0x7fe3e616, (q31_t)0xfab3384f, (q31_t)0x7fe3a355, (q31_t)0xfaacf133, (q31_t)0x7fe36045, (q31_t)0xfaa6aa1a,
+    (q31_t)0x7fe31ce6, (q31_t)0xfaa06305,
+  (q31_t)0x7fe2d938, (q31_t)0xfa9a1bf3, (q31_t)0x7fe2953b, (q31_t)0xfa93d4e4, (q31_t)0x7fe250ef, (q31_t)0xfa8d8dd8,
+    (q31_t)0x7fe20c55, (q31_t)0xfa8746d0,
+  (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fe18233, (q31_t)0xfa7ab8ca, (q31_t)0x7fe13cac, (q31_t)0xfa7471cc,
+    (q31_t)0x7fe0f6d6, (q31_t)0xfa6e2ad1,
+  (q31_t)0x7fe0b0b1, (q31_t)0xfa67e3da, (q31_t)0x7fe06a3d, (q31_t)0xfa619ce7, (q31_t)0x7fe0237a, (q31_t)0xfa5b55f7,
+    (q31_t)0x7fdfdc69, (q31_t)0xfa550f0a,
+  (q31_t)0x7fdf9508, (q31_t)0xfa4ec821, (q31_t)0x7fdf4d59, (q31_t)0xfa48813b, (q31_t)0x7fdf055a, (q31_t)0xfa423a59,
+    (q31_t)0x7fdebd0d, (q31_t)0xfa3bf37a,
+  (q31_t)0x7fde7471, (q31_t)0xfa35ac9f, (q31_t)0x7fde2b86, (q31_t)0xfa2f65c8, (q31_t)0x7fdde24d, (q31_t)0xfa291ef4,
+    (q31_t)0x7fdd98c4, (q31_t)0xfa22d823,
+  (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, (q31_t)0x7fdd04c6, (q31_t)0xfa164a8e, (q31_t)0x7fdcba51, (q31_t)0xfa1003c8,
+    (q31_t)0x7fdc6f8d, (q31_t)0xfa09bd06,
+  (q31_t)0x7fdc247a, (q31_t)0xfa037648, (q31_t)0x7fdbd918, (q31_t)0xf9fd2f8e, (q31_t)0x7fdb8d67, (q31_t)0xf9f6e8d7,
+    (q31_t)0x7fdb4167, (q31_t)0xf9f0a224,
+  (q31_t)0x7fdaf519, (q31_t)0xf9ea5b75, (q31_t)0x7fdaa87c, (q31_t)0xf9e414ca, (q31_t)0x7fda5b8f, (q31_t)0xf9ddce22,
+    (q31_t)0x7fda0e54, (q31_t)0xf9d7877e,
+  (q31_t)0x7fd9c0ca, (q31_t)0xf9d140de, (q31_t)0x7fd972f2, (q31_t)0xf9cafa42, (q31_t)0x7fd924ca, (q31_t)0xf9c4b3a9,
+    (q31_t)0x7fd8d653, (q31_t)0xf9be6d15,
+  (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd8387a, (q31_t)0xf9b1dff7, (q31_t)0x7fd7e917, (q31_t)0xf9ab996e,
+    (q31_t)0x7fd79965, (q31_t)0xf9a552e9,
+  (q31_t)0x7fd74964, (q31_t)0xf99f0c68, (q31_t)0x7fd6f914, (q31_t)0xf998c5ea, (q31_t)0x7fd6a875, (q31_t)0xf9927f71,
+    (q31_t)0x7fd65788, (q31_t)0xf98c38fc,
+  (q31_t)0x7fd6064c, (q31_t)0xf985f28a, (q31_t)0x7fd5b4c1, (q31_t)0xf97fac1d, (q31_t)0x7fd562e7, (q31_t)0xf97965b4,
+    (q31_t)0x7fd510be, (q31_t)0xf9731f4e,
+  (q31_t)0x7fd4be46, (q31_t)0xf96cd8ed, (q31_t)0x7fd46b80, (q31_t)0xf9669290, (q31_t)0x7fd4186a, (q31_t)0xf9604c37,
+    (q31_t)0x7fd3c506, (q31_t)0xf95a05e2,
+  (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fd31d51, (q31_t)0xf94d7944, (q31_t)0x7fd2c900, (q31_t)0xf94732fb,
+    (q31_t)0x7fd27460, (q31_t)0xf940ecb7,
+  (q31_t)0x7fd21f72, (q31_t)0xf93aa676, (q31_t)0x7fd1ca35, (q31_t)0xf934603a, (q31_t)0x7fd174a8, (q31_t)0xf92e1a02,
+    (q31_t)0x7fd11ecd, (q31_t)0xf927d3ce,
+  (q31_t)0x7fd0c8a3, (q31_t)0xf9218d9e, (q31_t)0x7fd0722b, (q31_t)0xf91b4773, (q31_t)0x7fd01b63, (q31_t)0xf915014c,
+    (q31_t)0x7fcfc44d, (q31_t)0xf90ebb29,
+  (q31_t)0x7fcf6ce8, (q31_t)0xf908750a, (q31_t)0x7fcf1533, (q31_t)0xf9022ef0, (q31_t)0x7fcebd31, (q31_t)0xf8fbe8da,
+    (q31_t)0x7fce64df, (q31_t)0xf8f5a2c9,
+  (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fcdb34f, (q31_t)0xf8e916b2, (q31_t)0x7fcd5a11, (q31_t)0xf8e2d0ae,
+    (q31_t)0x7fcd0083, (q31_t)0xf8dc8aae,
+  (q31_t)0x7fcca6a7, (q31_t)0xf8d644b2, (q31_t)0x7fcc4c7d, (q31_t)0xf8cffebb, (q31_t)0x7fcbf203, (q31_t)0xf8c9b8c8,
+    (q31_t)0x7fcb973b, (q31_t)0xf8c372d9,
+  (q31_t)0x7fcb3c23, (q31_t)0xf8bd2cef, (q31_t)0x7fcae0bd, (q31_t)0xf8b6e70a, (q31_t)0x7fca8508, (q31_t)0xf8b0a129,
+    (q31_t)0x7fca2905, (q31_t)0xf8aa5b4c,
+  (q31_t)0x7fc9ccb2, (q31_t)0xf8a41574, (q31_t)0x7fc97011, (q31_t)0xf89dcfa1, (q31_t)0x7fc91320, (q31_t)0xf89789d2,
+    (q31_t)0x7fc8b5e1, (q31_t)0xf8914407,
+  (q31_t)0x7fc85854, (q31_t)0xf88afe42, (q31_t)0x7fc7fa77, (q31_t)0xf884b880, (q31_t)0x7fc79c4b, (q31_t)0xf87e72c4,
+    (q31_t)0x7fc73dd1, (q31_t)0xf8782d0c,
+  (q31_t)0x7fc6df08, (q31_t)0xf871e759, (q31_t)0x7fc67ff0, (q31_t)0xf86ba1aa, (q31_t)0x7fc62089, (q31_t)0xf8655c00,
+    (q31_t)0x7fc5c0d3, (q31_t)0xf85f165b,
+  (q31_t)0x7fc560cf, (q31_t)0xf858d0bb, (q31_t)0x7fc5007c, (q31_t)0xf8528b1f, (q31_t)0x7fc49fda, (q31_t)0xf84c4588,
+    (q31_t)0x7fc43ee9, (q31_t)0xf845fff5,
+  (q31_t)0x7fc3dda9, (q31_t)0xf83fba68, (q31_t)0x7fc37c1b, (q31_t)0xf83974df, (q31_t)0x7fc31a3d, (q31_t)0xf8332f5b,
+    (q31_t)0x7fc2b811, (q31_t)0xf82ce9dc,
+  (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fc1f2cc, (q31_t)0xf8205eec, (q31_t)0x7fc18fb4, (q31_t)0xf81a197b,
+    (q31_t)0x7fc12c4d, (q31_t)0xf813d410,
+  (q31_t)0x7fc0c896, (q31_t)0xf80d8ea9, (q31_t)0x7fc06491, (q31_t)0xf8074947, (q31_t)0x7fc0003e, (q31_t)0xf80103ea,
+    (q31_t)0x7fbf9b9b, (q31_t)0xf7fabe92,
+  (q31_t)0x7fbf36aa, (q31_t)0xf7f4793e, (q31_t)0x7fbed16a, (q31_t)0xf7ee33f0, (q31_t)0x7fbe6bdb, (q31_t)0xf7e7eea7,
+    (q31_t)0x7fbe05fd, (q31_t)0xf7e1a963,
+  (q31_t)0x7fbd9fd0, (q31_t)0xf7db6423, (q31_t)0x7fbd3955, (q31_t)0xf7d51ee9, (q31_t)0x7fbcd28b, (q31_t)0xf7ced9b4,
+    (q31_t)0x7fbc6b72, (q31_t)0xf7c89484,
+  (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fbb9c53, (q31_t)0xf7bc0a33, (q31_t)0x7fbb344e, (q31_t)0xf7b5c512,
+    (q31_t)0x7fbacbfa, (q31_t)0xf7af7ff6,
+  (q31_t)0x7fba6357, (q31_t)0xf7a93ae0, (q31_t)0x7fb9fa65, (q31_t)0xf7a2f5ce, (q31_t)0x7fb99125, (q31_t)0xf79cb0c2,
+    (q31_t)0x7fb92796, (q31_t)0xf7966bbb,
+  (q31_t)0x7fb8bdb8, (q31_t)0xf79026b9, (q31_t)0x7fb8538b, (q31_t)0xf789e1bc, (q31_t)0x7fb7e90f, (q31_t)0xf7839cc4,
+    (q31_t)0x7fb77e45, (q31_t)0xf77d57d2,
+  (q31_t)0x7fb7132b, (q31_t)0xf77712e5, (q31_t)0x7fb6a7c3, (q31_t)0xf770cdfd, (q31_t)0x7fb63c0d, (q31_t)0xf76a891b,
+    (q31_t)0x7fb5d007, (q31_t)0xf764443d,
+  (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fb4f710, (q31_t)0xf757ba93, (q31_t)0x7fb48a1e, (q31_t)0xf75175c6,
+    (q31_t)0x7fb41cdd, (q31_t)0xf74b30fe,
+  (q31_t)0x7fb3af4e, (q31_t)0xf744ec3b, (q31_t)0x7fb34170, (q31_t)0xf73ea77e, (q31_t)0x7fb2d343, (q31_t)0xf73862c6,
+    (q31_t)0x7fb264c7, (q31_t)0xf7321e14,
+  (q31_t)0x7fb1f5fc, (q31_t)0xf72bd967, (q31_t)0x7fb186e3, (q31_t)0xf72594c0, (q31_t)0x7fb1177b, (q31_t)0xf71f501e,
+    (q31_t)0x7fb0a7c4, (q31_t)0xf7190b81,
+  (q31_t)0x7fb037bf, (q31_t)0xf712c6ea, (q31_t)0x7fafc76a, (q31_t)0xf70c8259, (q31_t)0x7faf56c7, (q31_t)0xf7063dcd,
+    (q31_t)0x7faee5d5, (q31_t)0xf6fff946,
+  (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, (q31_t)0x7fae0305, (q31_t)0xf6f3704a, (q31_t)0x7fad9127, (q31_t)0xf6ed2bd4,
+    (q31_t)0x7fad1efa, (q31_t)0xf6e6e764,
+  (q31_t)0x7facac7f, (q31_t)0xf6e0a2fa, (q31_t)0x7fac39b4, (q31_t)0xf6da5e95, (q31_t)0x7fabc69b, (q31_t)0xf6d41a36,
+    (q31_t)0x7fab5333, (q31_t)0xf6cdd5dc,
+  (q31_t)0x7faadf7c, (q31_t)0xf6c79188, (q31_t)0x7faa6b77, (q31_t)0xf6c14d3a, (q31_t)0x7fa9f723, (q31_t)0xf6bb08f1,
+    (q31_t)0x7fa98280, (q31_t)0xf6b4c4ae,
+  (q31_t)0x7fa90d8e, (q31_t)0xf6ae8071, (q31_t)0x7fa8984e, (q31_t)0xf6a83c3a, (q31_t)0x7fa822bf, (q31_t)0xf6a1f808,
+    (q31_t)0x7fa7ace1, (q31_t)0xf69bb3dd,
+  (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7fa6c039, (q31_t)0xf68f2b96, (q31_t)0x7fa6496e, (q31_t)0xf688e77c,
+    (q31_t)0x7fa5d256, (q31_t)0xf682a367,
+  (q31_t)0x7fa55aee, (q31_t)0xf67c5f59, (q31_t)0x7fa4e338, (q31_t)0xf6761b50, (q31_t)0x7fa46b32, (q31_t)0xf66fd74d,
+    (q31_t)0x7fa3f2df, (q31_t)0xf6699350,
+  (q31_t)0x7fa37a3c, (q31_t)0xf6634f59, (q31_t)0x7fa3014b, (q31_t)0xf65d0b68, (q31_t)0x7fa2880b, (q31_t)0xf656c77c,
+    (q31_t)0x7fa20e7c, (q31_t)0xf6508397,
+  (q31_t)0x7fa1949e, (q31_t)0xf64a3fb8, (q31_t)0x7fa11a72, (q31_t)0xf643fbdf, (q31_t)0x7fa09ff7, (q31_t)0xf63db80b,
+    (q31_t)0x7fa0252e, (q31_t)0xf637743e,
+  (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f9f2eae, (q31_t)0xf62aecb5, (q31_t)0x7f9eb2f8, (q31_t)0xf624a8fa,
+    (q31_t)0x7f9e36f4, (q31_t)0xf61e6545,
+  (q31_t)0x7f9dbaa0, (q31_t)0xf6182196, (q31_t)0x7f9d3dfe, (q31_t)0xf611dded, (q31_t)0x7f9cc10d, (q31_t)0xf60b9a4b,
+    (q31_t)0x7f9c43ce, (q31_t)0xf60556ae,
+  (q31_t)0x7f9bc640, (q31_t)0xf5ff1318, (q31_t)0x7f9b4863, (q31_t)0xf5f8cf87, (q31_t)0x7f9aca37, (q31_t)0xf5f28bfd,
+    (q31_t)0x7f9a4bbd, (q31_t)0xf5ec4879,
+  (q31_t)0x7f99ccf4, (q31_t)0xf5e604fc, (q31_t)0x7f994ddc, (q31_t)0xf5dfc184, (q31_t)0x7f98ce76, (q31_t)0xf5d97e13,
+    (q31_t)0x7f984ec1, (q31_t)0xf5d33aa8,
+  (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f974e6a, (q31_t)0xf5c6b3e5, (q31_t)0x7f96cdc9, (q31_t)0xf5c0708d,
+    (q31_t)0x7f964cd9, (q31_t)0xf5ba2d3b,
+  (q31_t)0x7f95cb9a, (q31_t)0xf5b3e9f0, (q31_t)0x7f954a0d, (q31_t)0xf5ada6ab, (q31_t)0x7f94c831, (q31_t)0xf5a7636c,
+    (q31_t)0x7f944606, (q31_t)0xf5a12034,
+  (q31_t)0x7f93c38c, (q31_t)0xf59add02, (q31_t)0x7f9340c4, (q31_t)0xf59499d6, (q31_t)0x7f92bdad, (q31_t)0xf58e56b1,
+    (q31_t)0x7f923a48, (q31_t)0xf5881393,
+  (q31_t)0x7f91b694, (q31_t)0xf581d07b, (q31_t)0x7f913291, (q31_t)0xf57b8d69, (q31_t)0x7f90ae3f, (q31_t)0xf5754a5e,
+    (q31_t)0x7f90299f, (q31_t)0xf56f0759,
+  (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, (q31_t)0x7f8f1f72, (q31_t)0xf5628163, (q31_t)0x7f8e99e6, (q31_t)0xf55c3e72,
+    (q31_t)0x7f8e140a, (q31_t)0xf555fb88,
+  (q31_t)0x7f8d8de1, (q31_t)0xf54fb8a4, (q31_t)0x7f8d0768, (q31_t)0xf54975c6, (q31_t)0x7f8c80a1, (q31_t)0xf54332ef,
+    (q31_t)0x7f8bf98b, (q31_t)0xf53cf01f,
+  (q31_t)0x7f8b7227, (q31_t)0xf536ad56, (q31_t)0x7f8aea74, (q31_t)0xf5306a93, (q31_t)0x7f8a6272, (q31_t)0xf52a27d7,
+    (q31_t)0x7f89da21, (q31_t)0xf523e521,
+  (q31_t)0x7f895182, (q31_t)0xf51da273, (q31_t)0x7f88c894, (q31_t)0xf5175fca, (q31_t)0x7f883f58, (q31_t)0xf5111d29,
+    (q31_t)0x7f87b5cd, (q31_t)0xf50ada8f,
+  (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f86a1ca, (q31_t)0xf4fe556e, (q31_t)0x7f861753, (q31_t)0xf4f812e7,
+    (q31_t)0x7f858c8d, (q31_t)0xf4f1d068,
+  (q31_t)0x7f850179, (q31_t)0xf4eb8def, (q31_t)0x7f847616, (q31_t)0xf4e54b7d, (q31_t)0x7f83ea64, (q31_t)0xf4df0912,
+    (q31_t)0x7f835e64, (q31_t)0xf4d8c6ae,
+  (q31_t)0x7f82d214, (q31_t)0xf4d28451, (q31_t)0x7f824577, (q31_t)0xf4cc41fb, (q31_t)0x7f81b88a, (q31_t)0xf4c5ffab,
+    (q31_t)0x7f812b4f, (q31_t)0xf4bfbd63,
+  (q31_t)0x7f809dc5, (q31_t)0xf4b97b21, (q31_t)0x7f800fed, (q31_t)0xf4b338e7, (q31_t)0x7f7f81c6, (q31_t)0xf4acf6b3,
+    (q31_t)0x7f7ef350, (q31_t)0xf4a6b486,
+  (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f7dd579, (q31_t)0xf49a3042, (q31_t)0x7f7d4617, (q31_t)0xf493ee2b,
+    (q31_t)0x7f7cb667, (q31_t)0xf48dac1a,
+  (q31_t)0x7f7c2668, (q31_t)0xf4876a10, (q31_t)0x7f7b961b, (q31_t)0xf481280e, (q31_t)0x7f7b057e, (q31_t)0xf47ae613,
+    (q31_t)0x7f7a7494, (q31_t)0xf474a41f,
+  (q31_t)0x7f79e35a, (q31_t)0xf46e6231, (q31_t)0x7f7951d2, (q31_t)0xf468204b, (q31_t)0x7f78bffb, (q31_t)0xf461de6d,
+    (q31_t)0x7f782dd6, (q31_t)0xf45b9c95,
+  (q31_t)0x7f779b62, (q31_t)0xf4555ac5, (q31_t)0x7f77089f, (q31_t)0xf44f18fb, (q31_t)0x7f76758e, (q31_t)0xf448d739,
+    (q31_t)0x7f75e22e, (q31_t)0xf442957e,
+  (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f74ba83, (q31_t)0xf436121e, (q31_t)0x7f742637, (q31_t)0xf42fd079,
+    (q31_t)0x7f73919d, (q31_t)0xf4298edc,
+  (q31_t)0x7f72fcb4, (q31_t)0xf4234d45, (q31_t)0x7f72677c, (q31_t)0xf41d0bb6, (q31_t)0x7f71d1f6, (q31_t)0xf416ca2e,
+    (q31_t)0x7f713c21, (q31_t)0xf41088ae,
+  (q31_t)0x7f70a5fe, (q31_t)0xf40a4735, (q31_t)0x7f700f8c, (q31_t)0xf40405c3, (q31_t)0x7f6f78cb, (q31_t)0xf3fdc459,
+    (q31_t)0x7f6ee1bc, (q31_t)0xf3f782f6,
+  (q31_t)0x7f6e4a5e, (q31_t)0xf3f1419a, (q31_t)0x7f6db2b1, (q31_t)0xf3eb0046, (q31_t)0x7f6d1ab6, (q31_t)0xf3e4bef9,
+    (q31_t)0x7f6c826d, (q31_t)0xf3de7db4,
+  (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, (q31_t)0x7f6b50ed, (q31_t)0xf3d1fb40, (q31_t)0x7f6ab7b8, (q31_t)0xf3cbba12,
+    (q31_t)0x7f6a1e34, (q31_t)0xf3c578eb,
+  (q31_t)0x7f698461, (q31_t)0xf3bf37cb, (q31_t)0x7f68ea40, (q31_t)0xf3b8f6b3, (q31_t)0x7f684fd0, (q31_t)0xf3b2b5a3,
+    (q31_t)0x7f67b512, (q31_t)0xf3ac749a,
+  (q31_t)0x7f671a05, (q31_t)0xf3a63398, (q31_t)0x7f667ea9, (q31_t)0xf39ff29f, (q31_t)0x7f65e2ff, (q31_t)0xf399b1ad,
+    (q31_t)0x7f654706, (q31_t)0xf39370c2,
+  (q31_t)0x7f64aabf, (q31_t)0xf38d2fe0, (q31_t)0x7f640e29, (q31_t)0xf386ef05, (q31_t)0x7f637144, (q31_t)0xf380ae31,
+    (q31_t)0x7f62d411, (q31_t)0xf37a6d66,
+  (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f6198bf, (q31_t)0xf36debe6, (q31_t)0x7f60faa0, (q31_t)0xf367ab31,
+    (q31_t)0x7f605c33, (q31_t)0xf3616a85,
+  (q31_t)0x7f5fbd77, (q31_t)0xf35b29e0, (q31_t)0x7f5f1e6c, (q31_t)0xf354e943, (q31_t)0x7f5e7f13, (q31_t)0xf34ea8ae,
+    (q31_t)0x7f5ddf6b, (q31_t)0xf3486820,
+  (q31_t)0x7f5d3f75, (q31_t)0xf342279b, (q31_t)0x7f5c9f30, (q31_t)0xf33be71d, (q31_t)0x7f5bfe9d, (q31_t)0xf335a6a7,
+    (q31_t)0x7f5b5dbb, (q31_t)0xf32f6639,
+  (q31_t)0x7f5abc8a, (q31_t)0xf32925d3, (q31_t)0x7f5a1b0b, (q31_t)0xf322e575, (q31_t)0x7f59793e, (q31_t)0xf31ca51f,
+    (q31_t)0x7f58d721, (q31_t)0xf31664d1,
+  (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f5791fd, (q31_t)0xf309e44c, (q31_t)0x7f56eef5, (q31_t)0xf303a416,
+    (q31_t)0x7f564b9f, (q31_t)0xf2fd63e8,
+  (q31_t)0x7f55a7fa, (q31_t)0xf2f723c1, (q31_t)0x7f550407, (q31_t)0xf2f0e3a3, (q31_t)0x7f545fc5, (q31_t)0xf2eaa38d,
+    (q31_t)0x7f53bb34, (q31_t)0xf2e4637f,
+  (q31_t)0x7f531655, (q31_t)0xf2de2379, (q31_t)0x7f527127, (q31_t)0xf2d7e37b, (q31_t)0x7f51cbab, (q31_t)0xf2d1a385,
+    (q31_t)0x7f5125e0, (q31_t)0xf2cb6398,
+  (q31_t)0x7f507fc7, (q31_t)0xf2c523b2, (q31_t)0x7f4fd95f, (q31_t)0xf2bee3d5, (q31_t)0x7f4f32a9, (q31_t)0xf2b8a400,
+    (q31_t)0x7f4e8ba4, (q31_t)0xf2b26433,
+  (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f4d3caf, (q31_t)0xf2a5e4b1, (q31_t)0x7f4c94be, (q31_t)0xf29fa4fd,
+    (q31_t)0x7f4bec7f, (q31_t)0xf2996551,
+  (q31_t)0x7f4b43f2, (q31_t)0xf29325ad, (q31_t)0x7f4a9b16, (q31_t)0xf28ce612, (q31_t)0x7f49f1eb, (q31_t)0xf286a67e,
+    (q31_t)0x7f494872, (q31_t)0xf28066f4,
+  (q31_t)0x7f489eaa, (q31_t)0xf27a2771, (q31_t)0x7f47f494, (q31_t)0xf273e7f7, (q31_t)0x7f474a30, (q31_t)0xf26da885,
+    (q31_t)0x7f469f7d, (q31_t)0xf267691b,
+  (q31_t)0x7f45f47b, (q31_t)0xf26129ba, (q31_t)0x7f45492b, (q31_t)0xf25aea61, (q31_t)0x7f449d8c, (q31_t)0xf254ab11,
+    (q31_t)0x7f43f19f, (q31_t)0xf24e6bc9,
+  (q31_t)0x7f434563, (q31_t)0xf2482c8a, (q31_t)0x7f4298d9, (q31_t)0xf241ed53, (q31_t)0x7f41ec01, (q31_t)0xf23bae24,
+    (q31_t)0x7f413ed9, (q31_t)0xf2356efe,
+  (q31_t)0x7f409164, (q31_t)0xf22f2fe1, (q31_t)0x7f3fe3a0, (q31_t)0xf228f0cc, (q31_t)0x7f3f358d, (q31_t)0xf222b1c0,
+    (q31_t)0x7f3e872c, (q31_t)0xf21c72bc,
+  (q31_t)0x7f3dd87c, (q31_t)0xf21633c0, (q31_t)0x7f3d297e, (q31_t)0xf20ff4ce, (q31_t)0x7f3c7a31, (q31_t)0xf209b5e4,
+    (q31_t)0x7f3bca96, (q31_t)0xf2037702,
+  (q31_t)0x7f3b1aad, (q31_t)0xf1fd3829, (q31_t)0x7f3a6a75, (q31_t)0xf1f6f959, (q31_t)0x7f39b9ee, (q31_t)0xf1f0ba91,
+    (q31_t)0x7f390919, (q31_t)0xf1ea7bd2,
+  (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f37a684, (q31_t)0xf1ddfe6f, (q31_t)0x7f36f4c3, (q31_t)0xf1d7bfca,
+    (q31_t)0x7f3642b4, (q31_t)0xf1d1812e,
+  (q31_t)0x7f359057, (q31_t)0xf1cb429a, (q31_t)0x7f34ddab, (q31_t)0xf1c50410, (q31_t)0x7f342ab1, (q31_t)0xf1bec58e,
+    (q31_t)0x7f337768, (q31_t)0xf1b88715,
+  (q31_t)0x7f32c3d1, (q31_t)0xf1b248a5, (q31_t)0x7f320feb, (q31_t)0xf1ac0a3e, (q31_t)0x7f315bb7, (q31_t)0xf1a5cbdf,
+    (q31_t)0x7f30a734, (q31_t)0xf19f8d89,
+  (q31_t)0x7f2ff263, (q31_t)0xf1994f3d, (q31_t)0x7f2f3d44, (q31_t)0xf19310f9, (q31_t)0x7f2e87d6, (q31_t)0xf18cd2be,
+    (q31_t)0x7f2dd219, (q31_t)0xf186948c,
+  (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2c65b5, (q31_t)0xf17a1842, (q31_t)0x7f2baf0d, (q31_t)0xf173da2b,
+    (q31_t)0x7f2af817, (q31_t)0xf16d9c1d,
+  (q31_t)0x7f2a40d2, (q31_t)0xf1675e17, (q31_t)0x7f29893f, (q31_t)0xf161201b, (q31_t)0x7f28d15d, (q31_t)0xf15ae228,
+    (q31_t)0x7f28192d, (q31_t)0xf154a43d,
+  (q31_t)0x7f2760af, (q31_t)0xf14e665c, (q31_t)0x7f26a7e2, (q31_t)0xf1482884, (q31_t)0x7f25eec7, (q31_t)0xf141eab5,
+    (q31_t)0x7f25355d, (q31_t)0xf13bacef,
+  (q31_t)0x7f247ba5, (q31_t)0xf1356f32, (q31_t)0x7f23c19e, (q31_t)0xf12f317e, (q31_t)0x7f230749, (q31_t)0xf128f3d4,
+    (q31_t)0x7f224ca6, (q31_t)0xf122b632,
+  (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f20d674, (q31_t)0xf1163b0b, (q31_t)0x7f201ae5, (q31_t)0xf10ffd85,
+    (q31_t)0x7f1f5f08, (q31_t)0xf109c009,
+  (q31_t)0x7f1ea2dc, (q31_t)0xf1038295, (q31_t)0x7f1de662, (q31_t)0xf0fd452b, (q31_t)0x7f1d299a, (q31_t)0xf0f707ca,
+    (q31_t)0x7f1c6c83, (q31_t)0xf0f0ca72,
+  (q31_t)0x7f1baf1e, (q31_t)0xf0ea8d24, (q31_t)0x7f1af16a, (q31_t)0xf0e44fdf, (q31_t)0x7f1a3368, (q31_t)0xf0de12a3,
+    (q31_t)0x7f197518, (q31_t)0xf0d7d571,
+  (q31_t)0x7f18b679, (q31_t)0xf0d19848, (q31_t)0x7f17f78c, (q31_t)0xf0cb5b28, (q31_t)0x7f173850, (q31_t)0xf0c51e12,
+    (q31_t)0x7f1678c6, (q31_t)0xf0bee105,
+  (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, (q31_t)0x7f14f8c7, (q31_t)0xf0b26707, (q31_t)0x7f143852, (q31_t)0xf0ac2a16,
+    (q31_t)0x7f13778e, (q31_t)0xf0a5ed2f,
+  (q31_t)0x7f12b67c, (q31_t)0xf09fb051, (q31_t)0x7f11f51c, (q31_t)0xf099737d, (q31_t)0x7f11336d, (q31_t)0xf09336b2,
+    (q31_t)0x7f107170, (q31_t)0xf08cf9f1,
+  (q31_t)0x7f0faf25, (q31_t)0xf086bd39, (q31_t)0x7f0eec8b, (q31_t)0xf080808b, (q31_t)0x7f0e29a3, (q31_t)0xf07a43e7,
+    (q31_t)0x7f0d666c, (q31_t)0xf074074c,
+  (q31_t)0x7f0ca2e7, (q31_t)0xf06dcaba, (q31_t)0x7f0bdf14, (q31_t)0xf0678e32, (q31_t)0x7f0b1af2, (q31_t)0xf06151b4,
+    (q31_t)0x7f0a5682, (q31_t)0xf05b1540,
+  (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7f08ccb7, (q31_t)0xf04e9c73, (q31_t)0x7f08075c, (q31_t)0xf048601c,
+    (q31_t)0x7f0741b2, (q31_t)0xf04223ce,
+  (q31_t)0x7f067bba, (q31_t)0xf03be78a, (q31_t)0x7f05b574, (q31_t)0xf035ab4f, (q31_t)0x7f04eedf, (q31_t)0xf02f6f1f,
+    (q31_t)0x7f0427fc, (q31_t)0xf02932f8,
+  (q31_t)0x7f0360cb, (q31_t)0xf022f6da, (q31_t)0x7f02994b, (q31_t)0xf01cbac7, (q31_t)0x7f01d17d, (q31_t)0xf0167ebd,
+    (q31_t)0x7f010961, (q31_t)0xf01042be,
+  (q31_t)0x7f0040f6, (q31_t)0xf00a06c8, (q31_t)0x7eff783d, (q31_t)0xf003cadc, (q31_t)0x7efeaf36, (q31_t)0xeffd8ef9,
+    (q31_t)0x7efde5e0, (q31_t)0xeff75321,
+  (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7efc524a, (q31_t)0xefeadb8e, (q31_t)0x7efb8809, (q31_t)0xefe49fd3,
+    (q31_t)0x7efabd7a, (q31_t)0xefde6423,
+  (q31_t)0x7ef9f29d, (q31_t)0xefd8287c, (q31_t)0x7ef92771, (q31_t)0xefd1ecdf, (q31_t)0x7ef85bf7, (q31_t)0xefcbb14c,
+    (q31_t)0x7ef7902f, (q31_t)0xefc575c3,
+  (q31_t)0x7ef6c418, (q31_t)0xefbf3a45, (q31_t)0x7ef5f7b3, (q31_t)0xefb8fed0, (q31_t)0x7ef52b00, (q31_t)0xefb2c365,
+    (q31_t)0x7ef45dfe, (q31_t)0xefac8804,
+  (q31_t)0x7ef390ae, (q31_t)0xefa64cae, (q31_t)0x7ef2c310, (q31_t)0xefa01161, (q31_t)0x7ef1f524, (q31_t)0xef99d61f,
+    (q31_t)0x7ef126e9, (q31_t)0xef939ae6,
+  (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7eef8988, (q31_t)0xef872494, (q31_t)0x7eeeba62, (q31_t)0xef80e97a,
+    (q31_t)0x7eedeaee, (q31_t)0xef7aae6b,
+  (q31_t)0x7eed1b2c, (q31_t)0xef747365, (q31_t)0x7eec4b1b, (q31_t)0xef6e386a, (q31_t)0x7eeb7abc, (q31_t)0xef67fd79,
+    (q31_t)0x7eeaaa0f, (q31_t)0xef61c292,
+  (q31_t)0x7ee9d914, (q31_t)0xef5b87b5, (q31_t)0x7ee907ca, (q31_t)0xef554ce3, (q31_t)0x7ee83632, (q31_t)0xef4f121b,
+    (q31_t)0x7ee7644c, (q31_t)0xef48d75d,
+  (q31_t)0x7ee69217, (q31_t)0xef429caa, (q31_t)0x7ee5bf94, (q31_t)0xef3c6201, (q31_t)0x7ee4ecc3, (q31_t)0xef362762,
+    (q31_t)0x7ee419a3, (q31_t)0xef2feccd,
+  (q31_t)0x7ee34636, (q31_t)0xef29b243, (q31_t)0x7ee2727a, (q31_t)0xef2377c4, (q31_t)0x7ee19e6f, (q31_t)0xef1d3d4e,
+    (q31_t)0x7ee0ca17, (q31_t)0xef1702e4,
+  (q31_t)0x7edff570, (q31_t)0xef10c883, (q31_t)0x7edf207b, (q31_t)0xef0a8e2d, (q31_t)0x7ede4b38, (q31_t)0xef0453e2,
+    (q31_t)0x7edd75a6, (q31_t)0xeefe19a1,
+  (q31_t)0x7edc9fc6, (q31_t)0xeef7df6a, (q31_t)0x7edbc998, (q31_t)0xeef1a53e, (q31_t)0x7edaf31c, (q31_t)0xeeeb6b1c,
+    (q31_t)0x7eda1c51, (q31_t)0xeee53105,
+  (q31_t)0x7ed94538, (q31_t)0xeedef6f9, (q31_t)0x7ed86dd1, (q31_t)0xeed8bcf7, (q31_t)0x7ed7961c, (q31_t)0xeed28300,
+    (q31_t)0x7ed6be18, (q31_t)0xeecc4913,
+  (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ed50d26, (q31_t)0xeebfd55a, (q31_t)0x7ed43438, (q31_t)0xeeb99b8d,
+    (q31_t)0x7ed35afb, (q31_t)0xeeb361cb,
+  (q31_t)0x7ed28171, (q31_t)0xeead2813, (q31_t)0x7ed1a798, (q31_t)0xeea6ee66, (q31_t)0x7ed0cd70, (q31_t)0xeea0b4c4,
+    (q31_t)0x7ecff2fb, (q31_t)0xee9a7b2d,
+  (q31_t)0x7ecf1837, (q31_t)0xee9441a0, (q31_t)0x7ece3d25, (q31_t)0xee8e081e, (q31_t)0x7ecd61c5, (q31_t)0xee87cea7,
+    (q31_t)0x7ecc8617, (q31_t)0xee81953b,
+  (q31_t)0x7ecbaa1a, (q31_t)0xee7b5bd9, (q31_t)0x7ecacdd0, (q31_t)0xee752283, (q31_t)0x7ec9f137, (q31_t)0xee6ee937,
+    (q31_t)0x7ec9144f, (q31_t)0xee68aff6,
+  (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7ec75996, (q31_t)0xee5c3d94, (q31_t)0x7ec67bc5, (q31_t)0xee560473,
+    (q31_t)0x7ec59da5, (q31_t)0xee4fcb5e,
+  (q31_t)0x7ec4bf36, (q31_t)0xee499253, (q31_t)0x7ec3e07a, (q31_t)0xee435953, (q31_t)0x7ec3016f, (q31_t)0xee3d205e,
+    (q31_t)0x7ec22217, (q31_t)0xee36e775,
+  (q31_t)0x7ec14270, (q31_t)0xee30ae96, (q31_t)0x7ec0627a, (q31_t)0xee2a75c2, (q31_t)0x7ebf8237, (q31_t)0xee243cf9,
+    (q31_t)0x7ebea1a6, (q31_t)0xee1e043b,
+  (q31_t)0x7ebdc0c6, (q31_t)0xee17cb88, (q31_t)0x7ebcdf98, (q31_t)0xee1192e0, (q31_t)0x7ebbfe1c, (q31_t)0xee0b5a43,
+    (q31_t)0x7ebb1c52, (q31_t)0xee0521b2,
+  (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eb957d2, (q31_t)0xedf8b0b0, (q31_t)0x7eb8751e, (q31_t)0xedf2783f,
+    (q31_t)0x7eb7921b, (q31_t)0xedec3fda,
+  (q31_t)0x7eb6aeca, (q31_t)0xede60780, (q31_t)0x7eb5cb2a, (q31_t)0xeddfcf31, (q31_t)0x7eb4e73d, (q31_t)0xedd996ed,
+    (q31_t)0x7eb40301, (q31_t)0xedd35eb5,
+  (q31_t)0x7eb31e78, (q31_t)0xedcd2687, (q31_t)0x7eb239a0, (q31_t)0xedc6ee65, (q31_t)0x7eb1547a, (q31_t)0xedc0b64e,
+    (q31_t)0x7eb06f05, (q31_t)0xedba7e43,
+  (q31_t)0x7eaf8943, (q31_t)0xedb44642, (q31_t)0x7eaea333, (q31_t)0xedae0e4d, (q31_t)0x7eadbcd4, (q31_t)0xeda7d664,
+    (q31_t)0x7eacd627, (q31_t)0xeda19e85,
+  (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, (q31_t)0x7eab07e3, (q31_t)0xed952eea, (q31_t)0x7eaa204c, (q31_t)0xed8ef72e,
+    (q31_t)0x7ea93867, (q31_t)0xed88bf7d,
+  (q31_t)0x7ea85033, (q31_t)0xed8287d7, (q31_t)0x7ea767b2, (q31_t)0xed7c503d, (q31_t)0x7ea67ee2, (q31_t)0xed7618ae,
+    (q31_t)0x7ea595c4, (q31_t)0xed6fe12b,
+  (q31_t)0x7ea4ac58, (q31_t)0xed69a9b3, (q31_t)0x7ea3c29e, (q31_t)0xed637246, (q31_t)0x7ea2d896, (q31_t)0xed5d3ae5,
+    (q31_t)0x7ea1ee3f, (q31_t)0xed570390,
+  (q31_t)0x7ea1039b, (q31_t)0xed50cc46, (q31_t)0x7ea018a8, (q31_t)0xed4a9507, (q31_t)0x7e9f2d68, (q31_t)0xed445dd5,
+    (q31_t)0x7e9e41d9, (q31_t)0xed3e26ad,
+  (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e9c69d1, (q31_t)0xed31b881, (q31_t)0x7e9b7d58, (q31_t)0xed2b817d,
+    (q31_t)0x7e9a9091, (q31_t)0xed254a84,
+  (q31_t)0x7e99a37c, (q31_t)0xed1f1396, (q31_t)0x7e98b618, (q31_t)0xed18dcb5, (q31_t)0x7e97c867, (q31_t)0xed12a5df,
+    (q31_t)0x7e96da67, (q31_t)0xed0c6f14,
+  (q31_t)0x7e95ec1a, (q31_t)0xed063856, (q31_t)0x7e94fd7e, (q31_t)0xed0001a3, (q31_t)0x7e940e94, (q31_t)0xecf9cafb,
+    (q31_t)0x7e931f5c, (q31_t)0xecf39460,
+  (q31_t)0x7e922fd6, (q31_t)0xeced5dd0, (q31_t)0x7e914002, (q31_t)0xece7274c, (q31_t)0x7e904fe0, (q31_t)0xece0f0d4,
+    (q31_t)0x7e8f5f70, (q31_t)0xecdaba67,
+  (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e8d7da6, (q31_t)0xecce4db2, (q31_t)0x7e8c8c4b, (q31_t)0xecc81769,
+    (q31_t)0x7e8b9aa3, (q31_t)0xecc1e12c,
+  (q31_t)0x7e8aa8ac, (q31_t)0xecbbaafb, (q31_t)0x7e89b668, (q31_t)0xecb574d5, (q31_t)0x7e88c3d5, (q31_t)0xecaf3ebc,
+    (q31_t)0x7e87d0f5, (q31_t)0xeca908ae,
+  (q31_t)0x7e86ddc6, (q31_t)0xeca2d2ad, (q31_t)0x7e85ea49, (q31_t)0xec9c9cb7, (q31_t)0x7e84f67e, (q31_t)0xec9666cd,
+    (q31_t)0x7e840265, (q31_t)0xec9030f0,
+  (q31_t)0x7e830dff, (q31_t)0xec89fb1e, (q31_t)0x7e82194a, (q31_t)0xec83c558, (q31_t)0x7e812447, (q31_t)0xec7d8f9e,
+    (q31_t)0x7e802ef6, (q31_t)0xec7759f1,
+  (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e7e436a, (q31_t)0xec6aeeba, (q31_t)0x7e7d4d2f, (q31_t)0xec64b930,
+    (q31_t)0x7e7c56a5, (q31_t)0xec5e83b3,
+  (q31_t)0x7e7b5fce, (q31_t)0xec584e41, (q31_t)0x7e7a68a9, (q31_t)0xec5218dc, (q31_t)0x7e797136, (q31_t)0xec4be383,
+    (q31_t)0x7e787975, (q31_t)0xec45ae36,
+  (q31_t)0x7e778166, (q31_t)0xec3f78f6, (q31_t)0x7e768908, (q31_t)0xec3943c1, (q31_t)0x7e75905d, (q31_t)0xec330e99,
+    (q31_t)0x7e749764, (q31_t)0xec2cd97d,
+  (q31_t)0x7e739e1d, (q31_t)0xec26a46d, (q31_t)0x7e72a488, (q31_t)0xec206f69, (q31_t)0x7e71aaa4, (q31_t)0xec1a3a72,
+    (q31_t)0x7e70b073, (q31_t)0xec140587,
+  (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, (q31_t)0x7e6ebb27, (q31_t)0xec079bd6, (q31_t)0x7e6dc00c, (q31_t)0xec01670f,
+    (q31_t)0x7e6cc4a2, (q31_t)0xebfb3256,
+  (q31_t)0x7e6bc8eb, (q31_t)0xebf4fda8, (q31_t)0x7e6acce6, (q31_t)0xebeec907, (q31_t)0x7e69d093, (q31_t)0xebe89472,
+    (q31_t)0x7e68d3f2, (q31_t)0xebe25fea,
+  (q31_t)0x7e67d703, (q31_t)0xebdc2b6e, (q31_t)0x7e66d9c6, (q31_t)0xebd5f6fe, (q31_t)0x7e65dc3b, (q31_t)0xebcfc29b,
+    (q31_t)0x7e64de62, (q31_t)0xebc98e45,
+  (q31_t)0x7e63e03b, (q31_t)0xebc359fb, (q31_t)0x7e62e1c6, (q31_t)0xebbd25bd, (q31_t)0x7e61e303, (q31_t)0xebb6f18c,
+    (q31_t)0x7e60e3f2, (q31_t)0xebb0bd67,
+  (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e5ee4e6, (q31_t)0xeba45543, (q31_t)0x7e5de4ec, (q31_t)0xeb9e2144,
+    (q31_t)0x7e5ce4a3, (q31_t)0xeb97ed52,
+  (q31_t)0x7e5be40c, (q31_t)0xeb91b96c, (q31_t)0x7e5ae328, (q31_t)0xeb8b8593, (q31_t)0x7e59e1f5, (q31_t)0xeb8551c6,
+    (q31_t)0x7e58e075, (q31_t)0xeb7f1e06,
+  (q31_t)0x7e57dea7, (q31_t)0xeb78ea52, (q31_t)0x7e56dc8a, (q31_t)0xeb72b6ac, (q31_t)0x7e55da20, (q31_t)0xeb6c8312,
+    (q31_t)0x7e54d768, (q31_t)0xeb664f84,
+  (q31_t)0x7e53d462, (q31_t)0xeb601c04, (q31_t)0x7e52d10e, (q31_t)0xeb59e890, (q31_t)0x7e51cd6c, (q31_t)0xeb53b529,
+    (q31_t)0x7e50c97c, (q31_t)0xeb4d81ce,
+  (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e4ec0b2, (q31_t)0xeb411b40, (q31_t)0x7e4dbbd9, (q31_t)0xeb3ae80c,
+    (q31_t)0x7e4cb6b1, (q31_t)0xeb34b4e4,
+  (q31_t)0x7e4bb13c, (q31_t)0xeb2e81ca, (q31_t)0x7e4aab78, (q31_t)0xeb284ebc, (q31_t)0x7e49a567, (q31_t)0xeb221bbb,
+    (q31_t)0x7e489f08, (q31_t)0xeb1be8c8,
+  (q31_t)0x7e47985b, (q31_t)0xeb15b5e1, (q31_t)0x7e469160, (q31_t)0xeb0f8307, (q31_t)0x7e458a17, (q31_t)0xeb095039,
+    (q31_t)0x7e448281, (q31_t)0xeb031d79,
+  (q31_t)0x7e437a9c, (q31_t)0xeafceac6, (q31_t)0x7e427269, (q31_t)0xeaf6b81f, (q31_t)0x7e4169e9, (q31_t)0xeaf08586,
+    (q31_t)0x7e40611b, (q31_t)0xeaea52fa,
+  (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e3e4e95, (q31_t)0xeaddee08, (q31_t)0x7e3d44dd, (q31_t)0xead7bba3,
+    (q31_t)0x7e3c3ad7, (q31_t)0xead1894b,
+  (q31_t)0x7e3b3083, (q31_t)0xeacb56ff, (q31_t)0x7e3a25e2, (q31_t)0xeac524c1, (q31_t)0x7e391af3, (q31_t)0xeabef290,
+    (q31_t)0x7e380fb5, (q31_t)0xeab8c06c,
+  (q31_t)0x7e37042a, (q31_t)0xeab28e56, (q31_t)0x7e35f851, (q31_t)0xeaac5c4c, (q31_t)0x7e34ec2b, (q31_t)0xeaa62a4f,
+    (q31_t)0x7e33dfb6, (q31_t)0xea9ff860,
+  (q31_t)0x7e32d2f4, (q31_t)0xea99c67e, (q31_t)0x7e31c5e3, (q31_t)0xea9394a9, (q31_t)0x7e30b885, (q31_t)0xea8d62e1,
+    (q31_t)0x7e2faad9, (q31_t)0xea873127,
+  (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, (q31_t)0x7e2d8e97, (q31_t)0xea7acdda, (q31_t)0x7e2c8002, (q31_t)0xea749c47,
+    (q31_t)0x7e2b711f, (q31_t)0xea6e6ac2,
+  (q31_t)0x7e2a61ed, (q31_t)0xea683949, (q31_t)0x7e29526e, (q31_t)0xea6207df, (q31_t)0x7e2842a2, (q31_t)0xea5bd681,
+    (q31_t)0x7e273287, (q31_t)0xea55a531,
+  (q31_t)0x7e26221f, (q31_t)0xea4f73ee, (q31_t)0x7e251168, (q31_t)0xea4942b9, (q31_t)0x7e240064, (q31_t)0xea431191,
+    (q31_t)0x7e22ef12, (q31_t)0xea3ce077,
+  (q31_t)0x7e21dd73, (q31_t)0xea36af69, (q31_t)0x7e20cb85, (q31_t)0xea307e6a, (q31_t)0x7e1fb94a, (q31_t)0xea2a4d78,
+    (q31_t)0x7e1ea6c1, (q31_t)0xea241c93,
+  (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e1c80c5, (q31_t)0xea17baf2, (q31_t)0x7e1b6d53, (q31_t)0xea118a35,
+    (q31_t)0x7e1a5992, (q31_t)0xea0b5987,
+  (q31_t)0x7e194584, (q31_t)0xea0528e5, (q31_t)0x7e183128, (q31_t)0xe9fef852, (q31_t)0x7e171c7f, (q31_t)0xe9f8c7cc,
+    (q31_t)0x7e160787, (q31_t)0xe9f29753,
+  (q31_t)0x7e14f242, (q31_t)0xe9ec66e8, (q31_t)0x7e13dcaf, (q31_t)0xe9e6368b, (q31_t)0x7e12c6ce, (q31_t)0xe9e0063c,
+    (q31_t)0x7e11b0a0, (q31_t)0xe9d9d5fa,
+  (q31_t)0x7e109a24, (q31_t)0xe9d3a5c5, (q31_t)0x7e0f835a, (q31_t)0xe9cd759f, (q31_t)0x7e0e6c42, (q31_t)0xe9c74586,
+    (q31_t)0x7e0d54dc, (q31_t)0xe9c1157a,
+  (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7e0b2528, (q31_t)0xe9b4b58d, (q31_t)0x7e0a0cd9, (q31_t)0xe9ae85ab,
+    (q31_t)0x7e08f43d, (q31_t)0xe9a855d7,
+  (q31_t)0x7e07db52, (q31_t)0xe9a22610, (q31_t)0x7e06c21a, (q31_t)0xe99bf658, (q31_t)0x7e05a894, (q31_t)0xe995c6ad,
+    (q31_t)0x7e048ec1, (q31_t)0xe98f9710,
+  (q31_t)0x7e0374a0, (q31_t)0xe9896781, (q31_t)0x7e025a31, (q31_t)0xe98337ff, (q31_t)0x7e013f74, (q31_t)0xe97d088c,
+    (q31_t)0x7e00246a, (q31_t)0xe976d926,
+  (q31_t)0x7dff0911, (q31_t)0xe970a9ce, (q31_t)0x7dfded6c, (q31_t)0xe96a7a85, (q31_t)0x7dfcd178, (q31_t)0xe9644b49,
+    (q31_t)0x7dfbb537, (q31_t)0xe95e1c1b,
+  (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7df97bcb, (q31_t)0xe951bde9, (q31_t)0x7df85ea0, (q31_t)0xe94b8ee5,
+    (q31_t)0x7df74128, (q31_t)0xe9455fef,
+  (q31_t)0x7df62362, (q31_t)0xe93f3107, (q31_t)0x7df5054f, (q31_t)0xe939022d, (q31_t)0x7df3e6ee, (q31_t)0xe932d361,
+    (q31_t)0x7df2c83f, (q31_t)0xe92ca4a4,
+  (q31_t)0x7df1a942, (q31_t)0xe92675f4, (q31_t)0x7df089f8, (q31_t)0xe9204752, (q31_t)0x7def6a60, (q31_t)0xe91a18bf,
+    (q31_t)0x7dee4a7a, (q31_t)0xe913ea39,
+  (q31_t)0x7ded2a47, (q31_t)0xe90dbbc2, (q31_t)0x7dec09c6, (q31_t)0xe9078d59, (q31_t)0x7deae8f7, (q31_t)0xe9015efe,
+    (q31_t)0x7de9c7da, (q31_t)0xe8fb30b1,
+  (q31_t)0x7de8a670, (q31_t)0xe8f50273, (q31_t)0x7de784b9, (q31_t)0xe8eed443, (q31_t)0x7de662b3, (q31_t)0xe8e8a621,
+    (q31_t)0x7de54060, (q31_t)0xe8e2780d,
+  (q31_t)0x7de41dc0, (q31_t)0xe8dc4a07, (q31_t)0x7de2fad1, (q31_t)0xe8d61c10, (q31_t)0x7de1d795, (q31_t)0xe8cfee27,
+    (q31_t)0x7de0b40b, (q31_t)0xe8c9c04c,
+  (q31_t)0x7ddf9034, (q31_t)0xe8c39280, (q31_t)0x7dde6c0f, (q31_t)0xe8bd64c2, (q31_t)0x7ddd479d, (q31_t)0xe8b73712,
+    (q31_t)0x7ddc22dc, (q31_t)0xe8b10971,
+  (q31_t)0x7ddafdce, (q31_t)0xe8aadbde, (q31_t)0x7dd9d873, (q31_t)0xe8a4ae59, (q31_t)0x7dd8b2ca, (q31_t)0xe89e80e3,
+    (q31_t)0x7dd78cd3, (q31_t)0xe898537b,
+  (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dd53ffc, (q31_t)0xe88bf8d7, (q31_t)0x7dd4191d, (q31_t)0xe885cb9a,
+    (q31_t)0x7dd2f1f0, (q31_t)0xe87f9e6c,
+  (q31_t)0x7dd1ca75, (q31_t)0xe879714d, (q31_t)0x7dd0a2ac, (q31_t)0xe873443c, (q31_t)0x7dcf7a96, (q31_t)0xe86d173a,
+    (q31_t)0x7dce5232, (q31_t)0xe866ea46,
+  (q31_t)0x7dcd2981, (q31_t)0xe860bd61, (q31_t)0x7dcc0082, (q31_t)0xe85a908a, (q31_t)0x7dcad736, (q31_t)0xe85463c2,
+    (q31_t)0x7dc9ad9c, (q31_t)0xe84e3708,
+  (q31_t)0x7dc883b4, (q31_t)0xe8480a5d, (q31_t)0x7dc7597f, (q31_t)0xe841ddc1, (q31_t)0x7dc62efc, (q31_t)0xe83bb133,
+    (q31_t)0x7dc5042b, (q31_t)0xe83584b4,
+  (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7dc2ada2, (q31_t)0xe8292be3, (q31_t)0x7dc181e8, (q31_t)0xe822ff90,
+    (q31_t)0x7dc055e2, (q31_t)0xe81cd34b,
+  (q31_t)0x7dbf298d, (q31_t)0xe816a716, (q31_t)0x7dbdfceb, (q31_t)0xe8107aef, (q31_t)0x7dbccffc, (q31_t)0xe80a4ed7,
+    (q31_t)0x7dbba2bf, (q31_t)0xe80422ce,
+  (q31_t)0x7dba7534, (q31_t)0xe7fdf6d4, (q31_t)0x7db9475c, (q31_t)0xe7f7cae8, (q31_t)0x7db81936, (q31_t)0xe7f19f0c,
+    (q31_t)0x7db6eac3, (q31_t)0xe7eb733e,
+  (q31_t)0x7db5bc02, (q31_t)0xe7e5477f, (q31_t)0x7db48cf4, (q31_t)0xe7df1bcf, (q31_t)0x7db35d98, (q31_t)0xe7d8f02d,
+    (q31_t)0x7db22def, (q31_t)0xe7d2c49b,
+  (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7dafcdb3, (q31_t)0xe7c66da3, (q31_t)0x7dae9d21, (q31_t)0xe7c0423d,
+    (q31_t)0x7dad6c42, (q31_t)0xe7ba16e7,
+  (q31_t)0x7dac3b15, (q31_t)0xe7b3eb9f, (q31_t)0x7dab099a, (q31_t)0xe7adc066, (q31_t)0x7da9d7d2, (q31_t)0xe7a7953d,
+    (q31_t)0x7da8a5bc, (q31_t)0xe7a16a22,
+  (q31_t)0x7da77359, (q31_t)0xe79b3f16, (q31_t)0x7da640a9, (q31_t)0xe795141a, (q31_t)0x7da50dab, (q31_t)0xe78ee92c,
+    (q31_t)0x7da3da5f, (q31_t)0xe788be4e,
+  (q31_t)0x7da2a6c6, (q31_t)0xe782937e, (q31_t)0x7da172df, (q31_t)0xe77c68be, (q31_t)0x7da03eab, (q31_t)0xe7763e0d,
+    (q31_t)0x7d9f0a29, (q31_t)0xe770136b,
+  (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8, (q31_t)0x7d9ca03e, (q31_t)0xe763be55, (q31_t)0x7d9b6ad3, (q31_t)0xe75d93e0,
+    (q31_t)0x7d9a351c, (q31_t)0xe757697b,
+  (q31_t)0x7d98ff17, (q31_t)0xe7513f25, (q31_t)0x7d97c8c4, (q31_t)0xe74b14de, (q31_t)0x7d969224, (q31_t)0xe744eaa6,
+    (q31_t)0x7d955b37, (q31_t)0xe73ec07e,
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+    (q31_t)0x7d86b07c, (q31_t)0xe6f4cb45,
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+    (q31_t)0x7d7cd121, (q31_t)0xe6c381f1,
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+    (q31_t)0x7d77da32, (q31_t)0xe6aadebc,
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+    (q31_t)0x7d72de6d, (q31_t)0xe6923c82,
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+    (q31_t)0x7d6dddd2, (q31_t)0xe6799b42,
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+    (q31_t)0x7c96509d, (q31_t)0xe2a3b7b5,
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+    (q31_t)0x7c908a65, (q31_t)0xe28b41d7,
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+    (q31_t)0x7c84ef8c, (q31_t)0xe25a5984,
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+    (q31_t)0x7c736347, (q31_t)0xe211059d,
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+    (q31_t)0x7c6d8041, (q31_t)0xe1f8969d,
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+    (q31_t)0x7c679870, (q31_t)0xe1e028c6,
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+    (q31_t)0x7c61abd3, (q31_t)0xe1c7bc18,
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+    (q31_t)0x7c5bba6a, (q31_t)0xe1af5094,
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+    (q31_t)0x7c55c436, (q31_t)0xe196e63c,
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+    (q31_t)0x7c4fc936, (q31_t)0xe17e7d0f,
+  (q31_t)0x7c4e49b7, (q31_t)0xe17862f3, (q31_t)0x7c4cc9ea, (q31_t)0xe17248ea, (q31_t)0x7c4b49d2, (q31_t)0xe16c2ef4,
+    (q31_t)0x7c49c96c, (q31_t)0xe1661510,
+  (q31_t)0x7c4848ba, (q31_t)0xe15ffb3f, (q31_t)0x7c46c7bb, (q31_t)0xe159e182, (q31_t)0x7c45466f, (q31_t)0xe153c7d7,
+    (q31_t)0x7c43c4d7, (q31_t)0xe14dae3f,
+  (q31_t)0x7c4242f2, (q31_t)0xe14794ba, (q31_t)0x7c40c0c1, (q31_t)0xe1417b48, (q31_t)0x7c3f3e42, (q31_t)0xe13b61e9,
+    (q31_t)0x7c3dbb78, (q31_t)0xe135489d,
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+    (q31_t)0x7c37ad4e, (q31_t)0xe11ce42a,
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+    (q31_t)0x7c319a5a, (q31_t)0xe10480e9,
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+    (q31_t)0x7c2b829d, (q31_t)0xe0ec1ed9,
+  (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7c2874f3, (q31_t)0xe0dfee44, (q31_t)0x7c26edab, (q31_t)0xe0d9d616,
+    (q31_t)0x7c256616, (q31_t)0xe0d3bdfc,
+  (q31_t)0x7c23de35, (q31_t)0xe0cda5f5, (q31_t)0x7c225607, (q31_t)0xe0c78e01, (q31_t)0x7c20cd8d, (q31_t)0xe0c17620,
+    (q31_t)0x7c1f44c6, (q31_t)0xe0bb5e53,
+  (q31_t)0x7c1dbbb3, (q31_t)0xe0b54698, (q31_t)0x7c1c3253, (q31_t)0xe0af2ef2, (q31_t)0x7c1aa8a6, (q31_t)0xe0a9175e,
+    (q31_t)0x7c191ead, (q31_t)0xe0a2ffde,
+  (q31_t)0x7c179467, (q31_t)0xe09ce871, (q31_t)0x7c1609d5, (q31_t)0xe096d117, (q31_t)0x7c147ef6, (q31_t)0xe090b9d1,
+    (q31_t)0x7c12f3cb, (q31_t)0xe08aa29f,
+  (q31_t)0x7c116853, (q31_t)0xe0848b7f, (q31_t)0x7c0fdc8f, (q31_t)0xe07e7473, (q31_t)0x7c0e507e, (q31_t)0xe0785d7b,
+    (q31_t)0x7c0cc421, (q31_t)0xe0724696,
+  (q31_t)0x7c0b3777, (q31_t)0xe06c2fc4, (q31_t)0x7c09aa80, (q31_t)0xe0661906, (q31_t)0x7c081d3d, (q31_t)0xe060025c,
+    (q31_t)0x7c068fae, (q31_t)0xe059ebc5,
+  (q31_t)0x7c0501d2, (q31_t)0xe053d541, (q31_t)0x7c0373a9, (q31_t)0xe04dbed1, (q31_t)0x7c01e534, (q31_t)0xe047a875,
+    (q31_t)0x7c005673, (q31_t)0xe041922c,
+  (q31_t)0x7bfec765, (q31_t)0xe03b7bf6, (q31_t)0x7bfd380a, (q31_t)0xe03565d5, (q31_t)0x7bfba863, (q31_t)0xe02f4fc6,
+    (q31_t)0x7bfa1870, (q31_t)0xe02939cc,
+  (q31_t)0x7bf88830, (q31_t)0xe02323e5, (q31_t)0x7bf6f7a4, (q31_t)0xe01d0e12, (q31_t)0x7bf566cb, (q31_t)0xe016f852,
+    (q31_t)0x7bf3d5a6, (q31_t)0xe010e2a7,
+  (q31_t)0x7bf24434, (q31_t)0xe00acd0e, (q31_t)0x7bf0b276, (q31_t)0xe004b78a, (q31_t)0x7bef206b, (q31_t)0xdffea219,
+    (q31_t)0x7bed8e14, (q31_t)0xdff88cbc,
+  (q31_t)0x7bebfb70, (q31_t)0xdff27773, (q31_t)0x7bea6880, (q31_t)0xdfec623e, (q31_t)0x7be8d544, (q31_t)0xdfe64d1c,
+    (q31_t)0x7be741bb, (q31_t)0xdfe0380e,
+  (q31_t)0x7be5ade6, (q31_t)0xdfda2314, (q31_t)0x7be419c4, (q31_t)0xdfd40e2e, (q31_t)0x7be28556, (q31_t)0xdfcdf95c,
+    (q31_t)0x7be0f09b, (q31_t)0xdfc7e49d,
+  (q31_t)0x7bdf5b94, (q31_t)0xdfc1cff3, (q31_t)0x7bddc641, (q31_t)0xdfbbbb5c, (q31_t)0x7bdc30a1, (q31_t)0xdfb5a6d9,
+    (q31_t)0x7bda9ab5, (q31_t)0xdfaf926a,
+  (q31_t)0x7bd9047c, (q31_t)0xdfa97e0f, (q31_t)0x7bd76df7, (q31_t)0xdfa369c8, (q31_t)0x7bd5d726, (q31_t)0xdf9d5595,
+    (q31_t)0x7bd44008, (q31_t)0xdf974176,
+  (q31_t)0x7bd2a89e, (q31_t)0xdf912d6b, (q31_t)0x7bd110e8, (q31_t)0xdf8b1974, (q31_t)0x7bcf78e5, (q31_t)0xdf850591,
+    (q31_t)0x7bcde095, (q31_t)0xdf7ef1c2,
+  (q31_t)0x7bcc47fa, (q31_t)0xdf78de07, (q31_t)0x7bcaaf12, (q31_t)0xdf72ca60, (q31_t)0x7bc915dd, (q31_t)0xdf6cb6cd,
+    (q31_t)0x7bc77c5d, (q31_t)0xdf66a34e,
+  (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7bc44876, (q31_t)0xdf5a7c8d, (q31_t)0x7bc2ae10, (q31_t)0xdf54694b,
+    (q31_t)0x7bc1135e, (q31_t)0xdf4e561c,
+  (q31_t)0x7bbf7860, (q31_t)0xdf484302, (q31_t)0x7bbddd15, (q31_t)0xdf422ffd, (q31_t)0x7bbc417e, (q31_t)0xdf3c1d0b,
+    (q31_t)0x7bbaa59a, (q31_t)0xdf360a2d,
+  (q31_t)0x7bb9096b, (q31_t)0xdf2ff764, (q31_t)0x7bb76cef, (q31_t)0xdf29e4af, (q31_t)0x7bb5d026, (q31_t)0xdf23d20e,
+    (q31_t)0x7bb43311, (q31_t)0xdf1dbf82,
+  (q31_t)0x7bb295b0, (q31_t)0xdf17ad0a, (q31_t)0x7bb0f803, (q31_t)0xdf119aa6, (q31_t)0x7baf5a09, (q31_t)0xdf0b8856,
+    (q31_t)0x7badbbc3, (q31_t)0xdf05761b,
+  (q31_t)0x7bac1d31, (q31_t)0xdeff63f4, (q31_t)0x7baa7e53, (q31_t)0xdef951e2, (q31_t)0x7ba8df28, (q31_t)0xdef33fe3,
+    (q31_t)0x7ba73fb1, (q31_t)0xdeed2dfa,
+  (q31_t)0x7ba59fee, (q31_t)0xdee71c24, (q31_t)0x7ba3ffde, (q31_t)0xdee10a63, (q31_t)0x7ba25f82, (q31_t)0xdedaf8b7,
+    (q31_t)0x7ba0beda, (q31_t)0xded4e71f,
+  (q31_t)0x7b9f1de6, (q31_t)0xdeced59b, (q31_t)0x7b9d7ca5, (q31_t)0xdec8c42c, (q31_t)0x7b9bdb18, (q31_t)0xdec2b2d1,
+    (q31_t)0x7b9a393f, (q31_t)0xdebca18b,
+  (q31_t)0x7b989719, (q31_t)0xdeb69059, (q31_t)0x7b96f4a8, (q31_t)0xdeb07f3c, (q31_t)0x7b9551ea, (q31_t)0xdeaa6e34,
+    (q31_t)0x7b93aee0, (q31_t)0xdea45d40,
+  (q31_t)0x7b920b89, (q31_t)0xde9e4c60, (q31_t)0x7b9067e7, (q31_t)0xde983b95, (q31_t)0x7b8ec3f8, (q31_t)0xde922adf,
+    (q31_t)0x7b8d1fbd, (q31_t)0xde8c1a3e,
+  (q31_t)0x7b8b7b36, (q31_t)0xde8609b1, (q31_t)0x7b89d662, (q31_t)0xde7ff938, (q31_t)0x7b883143, (q31_t)0xde79e8d5,
+    (q31_t)0x7b868bd7, (q31_t)0xde73d886,
+  (q31_t)0x7b84e61f, (q31_t)0xde6dc84b, (q31_t)0x7b83401b, (q31_t)0xde67b826, (q31_t)0x7b8199ca, (q31_t)0xde61a815,
+    (q31_t)0x7b7ff32e, (q31_t)0xde5b9819,
+  (q31_t)0x7b7e4c45, (q31_t)0xde558831, (q31_t)0x7b7ca510, (q31_t)0xde4f785f, (q31_t)0x7b7afd8f, (q31_t)0xde4968a1,
+    (q31_t)0x7b7955c2, (q31_t)0xde4358f8,
+  (q31_t)0x7b77ada8, (q31_t)0xde3d4964, (q31_t)0x7b760542, (q31_t)0xde3739e4, (q31_t)0x7b745c91, (q31_t)0xde312a7a,
+    (q31_t)0x7b72b393, (q31_t)0xde2b1b24,
+  (q31_t)0x7b710a49, (q31_t)0xde250be3, (q31_t)0x7b6f60b2, (q31_t)0xde1efcb7, (q31_t)0x7b6db6d0, (q31_t)0xde18eda0,
+    (q31_t)0x7b6c0ca2, (q31_t)0xde12de9e,
+  (q31_t)0x7b6a6227, (q31_t)0xde0ccfb1, (q31_t)0x7b68b760, (q31_t)0xde06c0d9, (q31_t)0x7b670c4d, (q31_t)0xde00b216,
+    (q31_t)0x7b6560ee, (q31_t)0xddfaa367,
+  (q31_t)0x7b63b543, (q31_t)0xddf494ce, (q31_t)0x7b62094c, (q31_t)0xddee8649, (q31_t)0x7b605d09, (q31_t)0xdde877da,
+    (q31_t)0x7b5eb079, (q31_t)0xdde26980,
+  (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7b5b5676, (q31_t)0xddd64d0a, (q31_t)0x7b59a902, (q31_t)0xddd03eef,
+    (q31_t)0x7b57fb42, (q31_t)0xddca30e9,
+  (q31_t)0x7b564d36, (q31_t)0xddc422f8, (q31_t)0x7b549ede, (q31_t)0xddbe151d, (q31_t)0x7b52f03a, (q31_t)0xddb80756,
+    (q31_t)0x7b51414a, (q31_t)0xddb1f9a4,
+  (q31_t)0x7b4f920e, (q31_t)0xddabec08, (q31_t)0x7b4de286, (q31_t)0xdda5de81, (q31_t)0x7b4c32b1, (q31_t)0xdd9fd10f,
+    (q31_t)0x7b4a8291, (q31_t)0xdd99c3b2,
+  (q31_t)0x7b48d225, (q31_t)0xdd93b66a, (q31_t)0x7b47216c, (q31_t)0xdd8da938, (q31_t)0x7b457068, (q31_t)0xdd879c1b,
+    (q31_t)0x7b43bf17, (q31_t)0xdd818f13,
+  (q31_t)0x7b420d7a, (q31_t)0xdd7b8220, (q31_t)0x7b405b92, (q31_t)0xdd757543, (q31_t)0x7b3ea95d, (q31_t)0xdd6f687b,
+    (q31_t)0x7b3cf6dc, (q31_t)0xdd695bc9,
+  (q31_t)0x7b3b4410, (q31_t)0xdd634f2b, (q31_t)0x7b3990f7, (q31_t)0xdd5d42a3, (q31_t)0x7b37dd92, (q31_t)0xdd573631,
+    (q31_t)0x7b3629e1, (q31_t)0xdd5129d4,
+  (q31_t)0x7b3475e5, (q31_t)0xdd4b1d8c, (q31_t)0x7b32c19c, (q31_t)0xdd451159, (q31_t)0x7b310d07, (q31_t)0xdd3f053c,
+    (q31_t)0x7b2f5826, (q31_t)0xdd38f935,
+  (q31_t)0x7b2da2fa, (q31_t)0xdd32ed43, (q31_t)0x7b2bed81, (q31_t)0xdd2ce166, (q31_t)0x7b2a37bc, (q31_t)0xdd26d59f,
+    (q31_t)0x7b2881ac, (q31_t)0xdd20c9ed,
+  (q31_t)0x7b26cb4f, (q31_t)0xdd1abe51, (q31_t)0x7b2514a6, (q31_t)0xdd14b2ca, (q31_t)0x7b235db2, (q31_t)0xdd0ea759,
+    (q31_t)0x7b21a671, (q31_t)0xdd089bfe,
+  (q31_t)0x7b1feee5, (q31_t)0xdd0290b8, (q31_t)0x7b1e370d, (q31_t)0xdcfc8588, (q31_t)0x7b1c7ee8, (q31_t)0xdcf67a6d,
+    (q31_t)0x7b1ac678, (q31_t)0xdcf06f68,
+  (q31_t)0x7b190dbc, (q31_t)0xdcea6478, (q31_t)0x7b1754b3, (q31_t)0xdce4599e, (q31_t)0x7b159b5f, (q31_t)0xdcde4eda,
+    (q31_t)0x7b13e1bf, (q31_t)0xdcd8442b,
+  (q31_t)0x7b1227d3, (q31_t)0xdcd23993, (q31_t)0x7b106d9b, (q31_t)0xdccc2f0f, (q31_t)0x7b0eb318, (q31_t)0xdcc624a2,
+    (q31_t)0x7b0cf848, (q31_t)0xdcc01a4a,
+  (q31_t)0x7b0b3d2c, (q31_t)0xdcba1008, (q31_t)0x7b0981c5, (q31_t)0xdcb405dc, (q31_t)0x7b07c612, (q31_t)0xdcadfbc5,
+    (q31_t)0x7b060a12, (q31_t)0xdca7f1c5,
+  (q31_t)0x7b044dc7, (q31_t)0xdca1e7da, (q31_t)0x7b029130, (q31_t)0xdc9bde05, (q31_t)0x7b00d44d, (q31_t)0xdc95d446,
+    (q31_t)0x7aff171e, (q31_t)0xdc8fca9c,
+  (q31_t)0x7afd59a4, (q31_t)0xdc89c109, (q31_t)0x7afb9bdd, (q31_t)0xdc83b78b, (q31_t)0x7af9ddcb, (q31_t)0xdc7dae23,
+    (q31_t)0x7af81f6c, (q31_t)0xdc77a4d2,
+  (q31_t)0x7af660c2, (q31_t)0xdc719b96, (q31_t)0x7af4a1cc, (q31_t)0xdc6b9270, (q31_t)0x7af2e28b, (q31_t)0xdc658960,
+    (q31_t)0x7af122fd, (q31_t)0xdc5f8066,
+  (q31_t)0x7aef6323, (q31_t)0xdc597781, (q31_t)0x7aeda2fe, (q31_t)0xdc536eb3, (q31_t)0x7aebe28d, (q31_t)0xdc4d65fb,
+    (q31_t)0x7aea21d0, (q31_t)0xdc475d59,
+  (q31_t)0x7ae860c7, (q31_t)0xdc4154cd, (q31_t)0x7ae69f73, (q31_t)0xdc3b4c57, (q31_t)0x7ae4ddd2, (q31_t)0xdc3543f7,
+    (q31_t)0x7ae31be6, (q31_t)0xdc2f3bad,
+  (q31_t)0x7ae159ae, (q31_t)0xdc293379, (q31_t)0x7adf972a, (q31_t)0xdc232b5c, (q31_t)0x7addd45b, (q31_t)0xdc1d2354,
+    (q31_t)0x7adc113f, (q31_t)0xdc171b63,
+  (q31_t)0x7ada4dd8, (q31_t)0xdc111388, (q31_t)0x7ad88a25, (q31_t)0xdc0b0bc2, (q31_t)0x7ad6c626, (q31_t)0xdc050414,
+    (q31_t)0x7ad501dc, (q31_t)0xdbfefc7b,
+  (q31_t)0x7ad33d45, (q31_t)0xdbf8f4f8, (q31_t)0x7ad17863, (q31_t)0xdbf2ed8c, (q31_t)0x7acfb336, (q31_t)0xdbece636,
+    (q31_t)0x7acdedbc, (q31_t)0xdbe6def6,
+  (q31_t)0x7acc27f7, (q31_t)0xdbe0d7cd, (q31_t)0x7aca61e6, (q31_t)0xdbdad0b9, (q31_t)0x7ac89b89, (q31_t)0xdbd4c9bc,
+    (q31_t)0x7ac6d4e0, (q31_t)0xdbcec2d6,
+  (q31_t)0x7ac50dec, (q31_t)0xdbc8bc06, (q31_t)0x7ac346ac, (q31_t)0xdbc2b54c, (q31_t)0x7ac17f20, (q31_t)0xdbbcaea8,
+    (q31_t)0x7abfb749, (q31_t)0xdbb6a81b,
+  (q31_t)0x7abdef25, (q31_t)0xdbb0a1a4, (q31_t)0x7abc26b7, (q31_t)0xdbaa9b43, (q31_t)0x7aba5dfc, (q31_t)0xdba494f9,
+    (q31_t)0x7ab894f6, (q31_t)0xdb9e8ec6,
+  (q31_t)0x7ab6cba4, (q31_t)0xdb9888a8, (q31_t)0x7ab50206, (q31_t)0xdb9282a2, (q31_t)0x7ab3381d, (q31_t)0xdb8c7cb1,
+    (q31_t)0x7ab16de7, (q31_t)0xdb8676d8,
+  (q31_t)0x7aafa367, (q31_t)0xdb807114, (q31_t)0x7aadd89a, (q31_t)0xdb7a6b68, (q31_t)0x7aac0d82, (q31_t)0xdb7465d1,
+    (q31_t)0x7aaa421e, (q31_t)0xdb6e6052,
+  (q31_t)0x7aa8766f, (q31_t)0xdb685ae9, (q31_t)0x7aa6aa74, (q31_t)0xdb625596, (q31_t)0x7aa4de2d, (q31_t)0xdb5c505a,
+    (q31_t)0x7aa3119a, (q31_t)0xdb564b35,
+  (q31_t)0x7aa144bc, (q31_t)0xdb504626, (q31_t)0x7a9f7793, (q31_t)0xdb4a412e, (q31_t)0x7a9daa1d, (q31_t)0xdb443c4c,
+    (q31_t)0x7a9bdc5c, (q31_t)0xdb3e3781,
+  (q31_t)0x7a9a0e50, (q31_t)0xdb3832cd, (q31_t)0x7a983ff7, (q31_t)0xdb322e30, (q31_t)0x7a967153, (q31_t)0xdb2c29a9,
+    (q31_t)0x7a94a264, (q31_t)0xdb262539,
+  (q31_t)0x7a92d329, (q31_t)0xdb2020e0, (q31_t)0x7a9103a2, (q31_t)0xdb1a1c9d, (q31_t)0x7a8f33d0, (q31_t)0xdb141871,
+    (q31_t)0x7a8d63b2, (q31_t)0xdb0e145c,
+  (q31_t)0x7a8b9348, (q31_t)0xdb08105e, (q31_t)0x7a89c293, (q31_t)0xdb020c77, (q31_t)0x7a87f192, (q31_t)0xdafc08a6,
+    (q31_t)0x7a862046, (q31_t)0xdaf604ec,
+  (q31_t)0x7a844eae, (q31_t)0xdaf00149, (q31_t)0x7a827ccb, (q31_t)0xdae9fdbd, (q31_t)0x7a80aa9c, (q31_t)0xdae3fa48,
+    (q31_t)0x7a7ed821, (q31_t)0xdaddf6ea,
+  (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a7b3249, (q31_t)0xdad1f072, (q31_t)0x7a795eec, (q31_t)0xdacbed58,
+    (q31_t)0x7a778b43, (q31_t)0xdac5ea56,
+  (q31_t)0x7a75b74f, (q31_t)0xdabfe76a, (q31_t)0x7a73e30f, (q31_t)0xdab9e495, (q31_t)0x7a720e84, (q31_t)0xdab3e1d8,
+    (q31_t)0x7a7039ad, (q31_t)0xdaaddf31,
+  (q31_t)0x7a6e648a, (q31_t)0xdaa7dca1, (q31_t)0x7a6c8f1c, (q31_t)0xdaa1da29, (q31_t)0x7a6ab963, (q31_t)0xda9bd7c7,
+    (q31_t)0x7a68e35e, (q31_t)0xda95d57d,
+  (q31_t)0x7a670d0d, (q31_t)0xda8fd349, (q31_t)0x7a653671, (q31_t)0xda89d12d, (q31_t)0x7a635f8a, (q31_t)0xda83cf28,
+    (q31_t)0x7a618857, (q31_t)0xda7dcd3a,
+  (q31_t)0x7a5fb0d8, (q31_t)0xda77cb63, (q31_t)0x7a5dd90e, (q31_t)0xda71c9a3, (q31_t)0x7a5c00f9, (q31_t)0xda6bc7fa,
+    (q31_t)0x7a5a2898, (q31_t)0xda65c669,
+  (q31_t)0x7a584feb, (q31_t)0xda5fc4ef, (q31_t)0x7a5676f3, (q31_t)0xda59c38c, (q31_t)0x7a549db0, (q31_t)0xda53c240,
+    (q31_t)0x7a52c421, (q31_t)0xda4dc10b,
+  (q31_t)0x7a50ea47, (q31_t)0xda47bfee, (q31_t)0x7a4f1021, (q31_t)0xda41bee8, (q31_t)0x7a4d35b0, (q31_t)0xda3bbdf9,
+    (q31_t)0x7a4b5af3, (q31_t)0xda35bd22,
+  (q31_t)0x7a497feb, (q31_t)0xda2fbc61, (q31_t)0x7a47a498, (q31_t)0xda29bbb9, (q31_t)0x7a45c8f9, (q31_t)0xda23bb27,
+    (q31_t)0x7a43ed0e, (q31_t)0xda1dbaad,
+  (q31_t)0x7a4210d8, (q31_t)0xda17ba4a, (q31_t)0x7a403457, (q31_t)0xda11b9ff, (q31_t)0x7a3e578b, (q31_t)0xda0bb9cb,
+    (q31_t)0x7a3c7a73, (q31_t)0xda05b9ae,
+  (q31_t)0x7a3a9d0f, (q31_t)0xd9ffb9a9, (q31_t)0x7a38bf60, (q31_t)0xd9f9b9bb, (q31_t)0x7a36e166, (q31_t)0xd9f3b9e5,
+    (q31_t)0x7a350321, (q31_t)0xd9edba26,
+  (q31_t)0x7a332490, (q31_t)0xd9e7ba7f, (q31_t)0x7a3145b3, (q31_t)0xd9e1baef, (q31_t)0x7a2f668c, (q31_t)0xd9dbbb77,
+    (q31_t)0x7a2d8719, (q31_t)0xd9d5bc16,
+  (q31_t)0x7a2ba75a, (q31_t)0xd9cfbccd, (q31_t)0x7a29c750, (q31_t)0xd9c9bd9b, (q31_t)0x7a27e6fb, (q31_t)0xd9c3be81,
+    (q31_t)0x7a26065b, (q31_t)0xd9bdbf7e,
+  (q31_t)0x7a24256f, (q31_t)0xd9b7c094, (q31_t)0x7a224437, (q31_t)0xd9b1c1c0, (q31_t)0x7a2062b5, (q31_t)0xd9abc305,
+    (q31_t)0x7a1e80e7, (q31_t)0xd9a5c461,
+  (q31_t)0x7a1c9ece, (q31_t)0xd99fc5d4, (q31_t)0x7a1abc69, (q31_t)0xd999c75f, (q31_t)0x7a18d9b9, (q31_t)0xd993c902,
+    (q31_t)0x7a16f6be, (q31_t)0xd98dcabd,
+  (q31_t)0x7a151378, (q31_t)0xd987cc90, (q31_t)0x7a132fe6, (q31_t)0xd981ce7a, (q31_t)0x7a114c09, (q31_t)0xd97bd07c,
+    (q31_t)0x7a0f67e0, (q31_t)0xd975d295,
+  (q31_t)0x7a0d836d, (q31_t)0xd96fd4c7, (q31_t)0x7a0b9eae, (q31_t)0xd969d710, (q31_t)0x7a09b9a4, (q31_t)0xd963d971,
+    (q31_t)0x7a07d44e, (q31_t)0xd95ddbea,
+  (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x7a0408c1, (q31_t)0xd951e123, (q31_t)0x7a02228a, (q31_t)0xd94be3e3,
+    (q31_t)0x7a003c07, (q31_t)0xd945e6bb,
+  (q31_t)0x79fe5539, (q31_t)0xd93fe9ab, (q31_t)0x79fc6e20, (q31_t)0xd939ecb3, (q31_t)0x79fa86bc, (q31_t)0xd933efd3,
+    (q31_t)0x79f89f0c, (q31_t)0xd92df30b,
+  (q31_t)0x79f6b711, (q31_t)0xd927f65b, (q31_t)0x79f4cecb, (q31_t)0xd921f9c3, (q31_t)0x79f2e63a, (q31_t)0xd91bfd43,
+    (q31_t)0x79f0fd5d, (q31_t)0xd91600da,
+  (q31_t)0x79ef1436, (q31_t)0xd910048a, (q31_t)0x79ed2ac3, (q31_t)0xd90a0852, (q31_t)0x79eb4105, (q31_t)0xd9040c32,
+    (q31_t)0x79e956fb, (q31_t)0xd8fe1029,
+  (q31_t)0x79e76ca7, (q31_t)0xd8f81439, (q31_t)0x79e58207, (q31_t)0xd8f21861, (q31_t)0x79e3971c, (q31_t)0xd8ec1ca1,
+    (q31_t)0x79e1abe6, (q31_t)0xd8e620fa,
+  (q31_t)0x79dfc064, (q31_t)0xd8e0256a, (q31_t)0x79ddd498, (q31_t)0xd8da29f2, (q31_t)0x79dbe880, (q31_t)0xd8d42e93,
+    (q31_t)0x79d9fc1d, (q31_t)0xd8ce334c,
+  (q31_t)0x79d80f6f, (q31_t)0xd8c8381d, (q31_t)0x79d62276, (q31_t)0xd8c23d06, (q31_t)0x79d43532, (q31_t)0xd8bc4207,
+    (q31_t)0x79d247a2, (q31_t)0xd8b64720,
+  (q31_t)0x79d059c8, (q31_t)0xd8b04c52, (q31_t)0x79ce6ba2, (q31_t)0xd8aa519c, (q31_t)0x79cc7d31, (q31_t)0xd8a456ff,
+    (q31_t)0x79ca8e75, (q31_t)0xd89e5c79,
+  (q31_t)0x79c89f6e, (q31_t)0xd898620c, (q31_t)0x79c6b01b, (q31_t)0xd89267b7, (q31_t)0x79c4c07e, (q31_t)0xd88c6d7b,
+    (q31_t)0x79c2d095, (q31_t)0xd8867356,
+  (q31_t)0x79c0e062, (q31_t)0xd880794b, (q31_t)0x79beefe3, (q31_t)0xd87a7f57, (q31_t)0x79bcff19, (q31_t)0xd874857c,
+    (q31_t)0x79bb0e04, (q31_t)0xd86e8bb9,
+  (q31_t)0x79b91ca4, (q31_t)0xd868920f, (q31_t)0x79b72af9, (q31_t)0xd862987d, (q31_t)0x79b53903, (q31_t)0xd85c9f04,
+    (q31_t)0x79b346c2, (q31_t)0xd856a5a3,
+  (q31_t)0x79b15435, (q31_t)0xd850ac5a, (q31_t)0x79af615e, (q31_t)0xd84ab32a, (q31_t)0x79ad6e3c, (q31_t)0xd844ba13,
+    (q31_t)0x79ab7ace, (q31_t)0xd83ec114,
+  (q31_t)0x79a98715, (q31_t)0xd838c82d, (q31_t)0x79a79312, (q31_t)0xd832cf5f, (q31_t)0x79a59ec3, (q31_t)0xd82cd6aa,
+    (q31_t)0x79a3aa29, (q31_t)0xd826de0d,
+  (q31_t)0x79a1b545, (q31_t)0xd820e589, (q31_t)0x799fc015, (q31_t)0xd81aed1d, (q31_t)0x799dca9a, (q31_t)0xd814f4ca,
+    (q31_t)0x799bd4d4, (q31_t)0xd80efc8f,
+  (q31_t)0x7999dec4, (q31_t)0xd809046e, (q31_t)0x7997e868, (q31_t)0xd8030c64, (q31_t)0x7995f1c1, (q31_t)0xd7fd1474,
+    (q31_t)0x7993facf, (q31_t)0xd7f71c9c,
+  (q31_t)0x79920392, (q31_t)0xd7f124dd, (q31_t)0x79900c0a, (q31_t)0xd7eb2d37, (q31_t)0x798e1438, (q31_t)0xd7e535a9,
+    (q31_t)0x798c1c1a, (q31_t)0xd7df3e34,
+  (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x79882afd, (q31_t)0xd7d34f94, (q31_t)0x798631ff, (q31_t)0xd7cd586a,
+    (q31_t)0x798438b5, (q31_t)0xd7c76158,
+  (q31_t)0x79823f20, (q31_t)0xd7c16a5f, (q31_t)0x79804541, (q31_t)0xd7bb737f, (q31_t)0x797e4b16, (q31_t)0xd7b57cb7,
+    (q31_t)0x797c50a1, (q31_t)0xd7af8609,
+  (q31_t)0x797a55e0, (q31_t)0xd7a98f73, (q31_t)0x79785ad5, (q31_t)0xd7a398f6, (q31_t)0x79765f7f, (q31_t)0xd79da293,
+    (q31_t)0x797463de, (q31_t)0xd797ac48,
+  (q31_t)0x797267f2, (q31_t)0xd791b616, (q31_t)0x79706bbb, (q31_t)0xd78bbffc, (q31_t)0x796e6f39, (q31_t)0xd785c9fc,
+    (q31_t)0x796c726c, (q31_t)0xd77fd415,
+  (q31_t)0x796a7554, (q31_t)0xd779de47, (q31_t)0x796877f1, (q31_t)0xd773e892, (q31_t)0x79667a44, (q31_t)0xd76df2f6,
+    (q31_t)0x79647c4c, (q31_t)0xd767fd72,
+  (q31_t)0x79627e08, (q31_t)0xd7620808, (q31_t)0x79607f7a, (q31_t)0xd75c12b7, (q31_t)0x795e80a1, (q31_t)0xd7561d7f,
+    (q31_t)0x795c817d, (q31_t)0xd7502860,
+  (q31_t)0x795a820e, (q31_t)0xd74a335b, (q31_t)0x79588255, (q31_t)0xd7443e6e, (q31_t)0x79568250, (q31_t)0xd73e499a,
+    (q31_t)0x79548201, (q31_t)0xd73854e0,
+  (q31_t)0x79528167, (q31_t)0xd732603f, (q31_t)0x79508082, (q31_t)0xd72c6bb6, (q31_t)0x794e7f52, (q31_t)0xd7267748,
+    (q31_t)0x794c7dd7, (q31_t)0xd72082f2,
+  (q31_t)0x794a7c12, (q31_t)0xd71a8eb5, (q31_t)0x79487a01, (q31_t)0xd7149a92, (q31_t)0x794677a6, (q31_t)0xd70ea688,
+    (q31_t)0x79447500, (q31_t)0xd708b297,
+  (q31_t)0x79427210, (q31_t)0xd702bec0, (q31_t)0x79406ed4, (q31_t)0xd6fccb01, (q31_t)0x793e6b4e, (q31_t)0xd6f6d75d,
+    (q31_t)0x793c677d, (q31_t)0xd6f0e3d1,
+  (q31_t)0x793a6361, (q31_t)0xd6eaf05f, (q31_t)0x79385efa, (q31_t)0xd6e4fd06, (q31_t)0x79365a49, (q31_t)0xd6df09c6,
+    (q31_t)0x7934554d, (q31_t)0xd6d916a0,
+  (q31_t)0x79325006, (q31_t)0xd6d32393, (q31_t)0x79304a74, (q31_t)0xd6cd30a0, (q31_t)0x792e4497, (q31_t)0xd6c73dc6,
+    (q31_t)0x792c3e70, (q31_t)0xd6c14b05,
+  (q31_t)0x792a37fe, (q31_t)0xd6bb585e, (q31_t)0x79283141, (q31_t)0xd6b565d0, (q31_t)0x79262a3a, (q31_t)0xd6af735c,
+    (q31_t)0x792422e8, (q31_t)0xd6a98101,
+  (q31_t)0x79221b4b, (q31_t)0xd6a38ec0, (q31_t)0x79201363, (q31_t)0xd69d9c98, (q31_t)0x791e0b31, (q31_t)0xd697aa8a,
+    (q31_t)0x791c02b4, (q31_t)0xd691b895,
+  (q31_t)0x7919f9ec, (q31_t)0xd68bc6ba, (q31_t)0x7917f0d9, (q31_t)0xd685d4f9, (q31_t)0x7915e77c, (q31_t)0xd67fe351,
+    (q31_t)0x7913ddd4, (q31_t)0xd679f1c2,
+  (q31_t)0x7911d3e2, (q31_t)0xd674004e, (q31_t)0x790fc9a4, (q31_t)0xd66e0ef2, (q31_t)0x790dbf1d, (q31_t)0xd6681db1,
+    (q31_t)0x790bb44a, (q31_t)0xd6622c89,
+  (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, (q31_t)0x79079dc5, (q31_t)0xd6564a87, (q31_t)0x79059212, (q31_t)0xd65059ac,
+    (q31_t)0x79038615, (q31_t)0xd64a68eb,
+  (q31_t)0x790179cd, (q31_t)0xd6447844, (q31_t)0x78ff6d3b, (q31_t)0xd63e87b6, (q31_t)0x78fd605d, (q31_t)0xd6389742,
+    (q31_t)0x78fb5336, (q31_t)0xd632a6e8,
+  (q31_t)0x78f945c3, (q31_t)0xd62cb6a8, (q31_t)0x78f73806, (q31_t)0xd626c681, (q31_t)0x78f529fe, (q31_t)0xd620d675,
+    (q31_t)0x78f31bac, (q31_t)0xd61ae682,
+  (q31_t)0x78f10d0f, (q31_t)0xd614f6a9, (q31_t)0x78eefe28, (q31_t)0xd60f06ea, (q31_t)0x78eceef6, (q31_t)0xd6091745,
+    (q31_t)0x78eadf79, (q31_t)0xd60327b9,
+  (q31_t)0x78e8cfb2, (q31_t)0xd5fd3848, (q31_t)0x78e6bfa0, (q31_t)0xd5f748f0, (q31_t)0x78e4af44, (q31_t)0xd5f159b3,
+    (q31_t)0x78e29e9d, (q31_t)0xd5eb6a8f,
+  (q31_t)0x78e08dab, (q31_t)0xd5e57b85, (q31_t)0x78de7c6f, (q31_t)0xd5df8c96, (q31_t)0x78dc6ae8, (q31_t)0xd5d99dc0,
+    (q31_t)0x78da5917, (q31_t)0xd5d3af04,
+  (q31_t)0x78d846fb, (q31_t)0xd5cdc062, (q31_t)0x78d63495, (q31_t)0xd5c7d1db, (q31_t)0x78d421e4, (q31_t)0xd5c1e36d,
+    (q31_t)0x78d20ee9, (q31_t)0xd5bbf519,
+  (q31_t)0x78cffba3, (q31_t)0xd5b606e0, (q31_t)0x78cde812, (q31_t)0xd5b018c0, (q31_t)0x78cbd437, (q31_t)0xd5aa2abb,
+    (q31_t)0x78c9c012, (q31_t)0xd5a43cd0,
+  (q31_t)0x78c7aba2, (q31_t)0xd59e4eff, (q31_t)0x78c596e7, (q31_t)0xd5986148, (q31_t)0x78c381e2, (q31_t)0xd59273ab,
+    (q31_t)0x78c16c93, (q31_t)0xd58c8628,
+  (q31_t)0x78bf56f9, (q31_t)0xd58698c0, (q31_t)0x78bd4114, (q31_t)0xd580ab72, (q31_t)0x78bb2ae5, (q31_t)0xd57abe3d,
+    (q31_t)0x78b9146c, (q31_t)0xd574d124,
+  (q31_t)0x78b6fda8, (q31_t)0xd56ee424, (q31_t)0x78b4e69a, (q31_t)0xd568f73f, (q31_t)0x78b2cf41, (q31_t)0xd5630a74,
+    (q31_t)0x78b0b79e, (q31_t)0xd55d1dc3,
+  (q31_t)0x78ae9fb0, (q31_t)0xd557312d, (q31_t)0x78ac8778, (q31_t)0xd55144b0, (q31_t)0x78aa6ef5, (q31_t)0xd54b584f,
+    (q31_t)0x78a85628, (q31_t)0xd5456c07,
+  (q31_t)0x78a63d11, (q31_t)0xd53f7fda, (q31_t)0x78a423af, (q31_t)0xd53993c7, (q31_t)0x78a20a03, (q31_t)0xd533a7cf,
+    (q31_t)0x789ff00c, (q31_t)0xd52dbbf1,
+  (q31_t)0x789dd5cb, (q31_t)0xd527d02e, (q31_t)0x789bbb3f, (q31_t)0xd521e484, (q31_t)0x7899a06a, (q31_t)0xd51bf8f6,
+    (q31_t)0x78978549, (q31_t)0xd5160d82,
+  (q31_t)0x789569df, (q31_t)0xd5102228, (q31_t)0x78934e2a, (q31_t)0xd50a36e9, (q31_t)0x7891322a, (q31_t)0xd5044bc4,
+    (q31_t)0x788f15e0, (q31_t)0xd4fe60ba,
+  (q31_t)0x788cf94c, (q31_t)0xd4f875ca, (q31_t)0x788adc6e, (q31_t)0xd4f28af5, (q31_t)0x7888bf45, (q31_t)0xd4eca03a,
+    (q31_t)0x7886a1d1, (q31_t)0xd4e6b59a,
+  (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x7882660c, (q31_t)0xd4dae0aa, (q31_t)0x788047ba, (q31_t)0xd4d4f65a,
+    (q31_t)0x787e291d, (q31_t)0xd4cf0c24,
+  (q31_t)0x787c0a36, (q31_t)0xd4c92209, (q31_t)0x7879eb05, (q31_t)0xd4c33809, (q31_t)0x7877cb89, (q31_t)0xd4bd4e23,
+    (q31_t)0x7875abc3, (q31_t)0xd4b76458,
+  (q31_t)0x78738bb3, (q31_t)0xd4b17aa8, (q31_t)0x78716b59, (q31_t)0xd4ab9112, (q31_t)0x786f4ab4, (q31_t)0xd4a5a798,
+    (q31_t)0x786d29c5, (q31_t)0xd49fbe37,
+  (q31_t)0x786b088c, (q31_t)0xd499d4f2, (q31_t)0x7868e708, (q31_t)0xd493ebc8, (q31_t)0x7866c53a, (q31_t)0xd48e02b8,
+    (q31_t)0x7864a322, (q31_t)0xd48819c3,
+  (q31_t)0x786280bf, (q31_t)0xd48230e9, (q31_t)0x78605e13, (q31_t)0xd47c4829, (q31_t)0x785e3b1c, (q31_t)0xd4765f85,
+    (q31_t)0x785c17db, (q31_t)0xd47076fb,
+  (q31_t)0x7859f44f, (q31_t)0xd46a8e8d, (q31_t)0x7857d079, (q31_t)0xd464a639, (q31_t)0x7855ac5a, (q31_t)0xd45ebe00,
+    (q31_t)0x785387ef, (q31_t)0xd458d5e2,
+  (q31_t)0x7851633b, (q31_t)0xd452eddf, (q31_t)0x784f3e3c, (q31_t)0xd44d05f6, (q31_t)0x784d18f4, (q31_t)0xd4471e29,
+    (q31_t)0x784af361, (q31_t)0xd4413677,
+  (q31_t)0x7848cd83, (q31_t)0xd43b4ee0, (q31_t)0x7846a75c, (q31_t)0xd4356763, (q31_t)0x784480ea, (q31_t)0xd42f8002,
+    (q31_t)0x78425a2f, (q31_t)0xd42998bc,
+  (q31_t)0x78403329, (q31_t)0xd423b191, (q31_t)0x783e0bd9, (q31_t)0xd41dca81, (q31_t)0x783be43e, (q31_t)0xd417e38c,
+    (q31_t)0x7839bc5a, (q31_t)0xd411fcb2,
+  (q31_t)0x7837942b, (q31_t)0xd40c15f3, (q31_t)0x78356bb2, (q31_t)0xd4062f4f, (q31_t)0x783342ef, (q31_t)0xd40048c6,
+    (q31_t)0x783119e2, (q31_t)0xd3fa6259,
+  (q31_t)0x782ef08b, (q31_t)0xd3f47c06, (q31_t)0x782cc6ea, (q31_t)0xd3ee95cf, (q31_t)0x782a9cfe, (q31_t)0xd3e8afb3,
+    (q31_t)0x782872c8, (q31_t)0xd3e2c9b2,
+  (q31_t)0x78264849, (q31_t)0xd3dce3cd, (q31_t)0x78241d7f, (q31_t)0xd3d6fe03, (q31_t)0x7821f26b, (q31_t)0xd3d11853,
+    (q31_t)0x781fc70d, (q31_t)0xd3cb32c0,
+  (q31_t)0x781d9b65, (q31_t)0xd3c54d47, (q31_t)0x781b6f72, (q31_t)0xd3bf67ea, (q31_t)0x78194336, (q31_t)0xd3b982a8,
+    (q31_t)0x781716b0, (q31_t)0xd3b39d81,
+  (q31_t)0x7814e9df, (q31_t)0xd3adb876, (q31_t)0x7812bcc4, (q31_t)0xd3a7d385, (q31_t)0x78108f60, (q31_t)0xd3a1eeb1,
+    (q31_t)0x780e61b1, (q31_t)0xd39c09f7,
+  (q31_t)0x780c33b8, (q31_t)0xd396255a, (q31_t)0x780a0575, (q31_t)0xd39040d7, (q31_t)0x7807d6e9, (q31_t)0xd38a5c70,
+    (q31_t)0x7805a812, (q31_t)0xd3847824,
+  (q31_t)0x780378f1, (q31_t)0xd37e93f4, (q31_t)0x78014986, (q31_t)0xd378afdf, (q31_t)0x77ff19d1, (q31_t)0xd372cbe6,
+    (q31_t)0x77fce9d2, (q31_t)0xd36ce808,
+  (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x77f888f6, (q31_t)0xd361209f, (q31_t)0x77f65819, (q31_t)0xd35b3d13,
+    (q31_t)0x77f426f2, (q31_t)0xd35559a4,
+  (q31_t)0x77f1f581, (q31_t)0xd34f764f, (q31_t)0x77efc3c5, (q31_t)0xd3499317, (q31_t)0x77ed91c0, (q31_t)0xd343affa,
+    (q31_t)0x77eb5f71, (q31_t)0xd33dccf8,
+  (q31_t)0x77e92cd9, (q31_t)0xd337ea12, (q31_t)0x77e6f9f6, (q31_t)0xd3320748, (q31_t)0x77e4c6c9, (q31_t)0xd32c2499,
+    (q31_t)0x77e29352, (q31_t)0xd3264206,
+  (q31_t)0x77e05f91, (q31_t)0xd3205f8f, (q31_t)0x77de2b86, (q31_t)0xd31a7d33, (q31_t)0x77dbf732, (q31_t)0xd3149af3,
+    (q31_t)0x77d9c293, (q31_t)0xd30eb8cf,
+  (q31_t)0x77d78daa, (q31_t)0xd308d6c7, (q31_t)0x77d55878, (q31_t)0xd302f4da, (q31_t)0x77d322fc, (q31_t)0xd2fd1309,
+    (q31_t)0x77d0ed35, (q31_t)0xd2f73154,
+  (q31_t)0x77ceb725, (q31_t)0xd2f14fba, (q31_t)0x77cc80cb, (q31_t)0xd2eb6e3c, (q31_t)0x77ca4a27, (q31_t)0xd2e58cdb,
+    (q31_t)0x77c81339, (q31_t)0xd2dfab95,
+  (q31_t)0x77c5dc01, (q31_t)0xd2d9ca6a, (q31_t)0x77c3a47f, (q31_t)0xd2d3e95c, (q31_t)0x77c16cb4, (q31_t)0xd2ce0869,
+    (q31_t)0x77bf349f, (q31_t)0xd2c82793,
+  (q31_t)0x77bcfc3f, (q31_t)0xd2c246d8, (q31_t)0x77bac396, (q31_t)0xd2bc6639, (q31_t)0x77b88aa3, (q31_t)0xd2b685b6,
+    (q31_t)0x77b65166, (q31_t)0xd2b0a54f,
+  (q31_t)0x77b417df, (q31_t)0xd2aac504, (q31_t)0x77b1de0f, (q31_t)0xd2a4e4d5, (q31_t)0x77afa3f5, (q31_t)0xd29f04c2,
+    (q31_t)0x77ad6990, (q31_t)0xd29924cb,
+  (q31_t)0x77ab2ee2, (q31_t)0xd29344f0, (q31_t)0x77a8f3ea, (q31_t)0xd28d6531, (q31_t)0x77a6b8a9, (q31_t)0xd287858e,
+    (q31_t)0x77a47d1d, (q31_t)0xd281a607,
+  (q31_t)0x77a24148, (q31_t)0xd27bc69c, (q31_t)0x77a00529, (q31_t)0xd275e74d, (q31_t)0x779dc8c0, (q31_t)0xd270081b,
+    (q31_t)0x779b8c0e, (q31_t)0xd26a2904,
+  (q31_t)0x77994f11, (q31_t)0xd2644a0a, (q31_t)0x779711cb, (q31_t)0xd25e6b2b, (q31_t)0x7794d43b, (q31_t)0xd2588c69,
+    (q31_t)0x77929661, (q31_t)0xd252adc3,
+  (q31_t)0x7790583e, (q31_t)0xd24ccf39, (q31_t)0x778e19d0, (q31_t)0xd246f0cb, (q31_t)0x778bdb19, (q31_t)0xd241127a,
+    (q31_t)0x77899c19, (q31_t)0xd23b3444,
+  (q31_t)0x77875cce, (q31_t)0xd235562b, (q31_t)0x77851d3a, (q31_t)0xd22f782f, (q31_t)0x7782dd5c, (q31_t)0xd2299a4e,
+    (q31_t)0x77809d35, (q31_t)0xd223bc8a,
+  (q31_t)0x777e5cc3, (q31_t)0xd21ddee2, (q31_t)0x777c1c08, (q31_t)0xd2180156, (q31_t)0x7779db03, (q31_t)0xd21223e7,
+    (q31_t)0x777799b5, (q31_t)0xd20c4694,
+  (q31_t)0x7775581d, (q31_t)0xd206695d, (q31_t)0x7773163b, (q31_t)0xd2008c43, (q31_t)0x7770d40f, (q31_t)0xd1faaf45,
+    (q31_t)0x776e919a, (q31_t)0xd1f4d263,
+  (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x776a0bd3, (q31_t)0xd1e918f5, (q31_t)0x7767c880, (q31_t)0xd1e33c69,
+    (q31_t)0x776584e5, (q31_t)0xd1dd5ff9,
+  (q31_t)0x776340ff, (q31_t)0xd1d783a6, (q31_t)0x7760fcd0, (q31_t)0xd1d1a76f, (q31_t)0x775eb857, (q31_t)0xd1cbcb54,
+    (q31_t)0x775c7395, (q31_t)0xd1c5ef56,
+  (q31_t)0x775a2e89, (q31_t)0xd1c01375, (q31_t)0x7757e933, (q31_t)0xd1ba37b0, (q31_t)0x7755a394, (q31_t)0xd1b45c08,
+    (q31_t)0x77535dab, (q31_t)0xd1ae807c,
+  (q31_t)0x77511778, (q31_t)0xd1a8a50d, (q31_t)0x774ed0fc, (q31_t)0xd1a2c9ba, (q31_t)0x774c8a36, (q31_t)0xd19cee84,
+    (q31_t)0x774a4327, (q31_t)0xd197136b,
+  (q31_t)0x7747fbce, (q31_t)0xd191386e, (q31_t)0x7745b42c, (q31_t)0xd18b5d8e, (q31_t)0x77436c40, (q31_t)0xd18582ca,
+    (q31_t)0x7741240a, (q31_t)0xd17fa823,
+  (q31_t)0x773edb8b, (q31_t)0xd179cd99, (q31_t)0x773c92c2, (q31_t)0xd173f32c, (q31_t)0x773a49b0, (q31_t)0xd16e18db,
+    (q31_t)0x77380054, (q31_t)0xd1683ea7,
+  (q31_t)0x7735b6af, (q31_t)0xd1626490, (q31_t)0x77336cc0, (q31_t)0xd15c8a95, (q31_t)0x77312287, (q31_t)0xd156b0b7,
+    (q31_t)0x772ed805, (q31_t)0xd150d6f6,
+  (q31_t)0x772c8d3a, (q31_t)0xd14afd52, (q31_t)0x772a4225, (q31_t)0xd14523cb, (q31_t)0x7727f6c6, (q31_t)0xd13f4a60,
+    (q31_t)0x7725ab1f, (q31_t)0xd1397113,
+  (q31_t)0x77235f2d, (q31_t)0xd13397e2, (q31_t)0x772112f2, (q31_t)0xd12dbece, (q31_t)0x771ec66e, (q31_t)0xd127e5d7,
+    (q31_t)0x771c79a0, (q31_t)0xd1220cfc,
+  (q31_t)0x771a2c88, (q31_t)0xd11c343f, (q31_t)0x7717df27, (q31_t)0xd1165b9f, (q31_t)0x7715917d, (q31_t)0xd110831b,
+    (q31_t)0x77134389, (q31_t)0xd10aaab5,
+  (q31_t)0x7710f54c, (q31_t)0xd104d26b, (q31_t)0x770ea6c5, (q31_t)0xd0fefa3f, (q31_t)0x770c57f5, (q31_t)0xd0f9222f,
+    (q31_t)0x770a08dc, (q31_t)0xd0f34a3d,
+  (q31_t)0x7707b979, (q31_t)0xd0ed7267, (q31_t)0x770569cc, (q31_t)0xd0e79aaf, (q31_t)0x770319d6, (q31_t)0xd0e1c313,
+    (q31_t)0x7700c997, (q31_t)0xd0dbeb95,
+  (q31_t)0x76fe790e, (q31_t)0xd0d61434, (q31_t)0x76fc283c, (q31_t)0xd0d03cf0, (q31_t)0x76f9d721, (q31_t)0xd0ca65c9,
+    (q31_t)0x76f785bc, (q31_t)0xd0c48ebf,
+  (q31_t)0x76f5340e, (q31_t)0xd0beb7d2, (q31_t)0x76f2e216, (q31_t)0xd0b8e102, (q31_t)0x76f08fd5, (q31_t)0xd0b30a50,
+    (q31_t)0x76ee3d4b, (q31_t)0xd0ad33ba,
+  (q31_t)0x76ebea77, (q31_t)0xd0a75d42, (q31_t)0x76e9975a, (q31_t)0xd0a186e7, (q31_t)0x76e743f4, (q31_t)0xd09bb0aa,
+    (q31_t)0x76e4f044, (q31_t)0xd095da89,
+  (q31_t)0x76e29c4b, (q31_t)0xd0900486, (q31_t)0x76e04808, (q31_t)0xd08a2ea0, (q31_t)0x76ddf37c, (q31_t)0xd08458d7,
+    (q31_t)0x76db9ea7, (q31_t)0xd07e832c,
+  (q31_t)0x76d94989, (q31_t)0xd078ad9e, (q31_t)0x76d6f421, (q31_t)0xd072d82d, (q31_t)0x76d49e70, (q31_t)0xd06d02da,
+    (q31_t)0x76d24876, (q31_t)0xd0672da3,
+  (q31_t)0x76cff232, (q31_t)0xd061588b, (q31_t)0x76cd9ba5, (q31_t)0xd05b838f, (q31_t)0x76cb44cf, (q31_t)0xd055aeb1,
+    (q31_t)0x76c8edb0, (q31_t)0xd04fd9f1,
+  (q31_t)0x76c69647, (q31_t)0xd04a054e, (q31_t)0x76c43e95, (q31_t)0xd04430c8, (q31_t)0x76c1e699, (q31_t)0xd03e5c60,
+    (q31_t)0x76bf8e55, (q31_t)0xd0388815,
+  (q31_t)0x76bd35c7, (q31_t)0xd032b3e7, (q31_t)0x76badcf0, (q31_t)0xd02cdfd8, (q31_t)0x76b883d0, (q31_t)0xd0270be5,
+    (q31_t)0x76b62a66, (q31_t)0xd0213810,
+  (q31_t)0x76b3d0b4, (q31_t)0xd01b6459, (q31_t)0x76b176b8, (q31_t)0xd01590bf, (q31_t)0x76af1c72, (q31_t)0xd00fbd43,
+    (q31_t)0x76acc1e4, (q31_t)0xd009e9e4,
+  (q31_t)0x76aa670d, (q31_t)0xd00416a3, (q31_t)0x76a80bec, (q31_t)0xcffe4380, (q31_t)0x76a5b082, (q31_t)0xcff8707a,
+    (q31_t)0x76a354cf, (q31_t)0xcff29d92,
+  (q31_t)0x76a0f8d2, (q31_t)0xcfeccac7, (q31_t)0x769e9c8d, (q31_t)0xcfe6f81a, (q31_t)0x769c3ffe, (q31_t)0xcfe1258b,
+    (q31_t)0x7699e326, (q31_t)0xcfdb531a,
+  (q31_t)0x76978605, (q31_t)0xcfd580c6, (q31_t)0x7695289b, (q31_t)0xcfcfae8f, (q31_t)0x7692cae8, (q31_t)0xcfc9dc77,
+    (q31_t)0x76906ceb, (q31_t)0xcfc40a7c,
+  (q31_t)0x768e0ea6, (q31_t)0xcfbe389f, (q31_t)0x768bb017, (q31_t)0xcfb866e0, (q31_t)0x7689513f, (q31_t)0xcfb2953f,
+    (q31_t)0x7686f21e, (q31_t)0xcfacc3bb,
+  (q31_t)0x768492b4, (q31_t)0xcfa6f255, (q31_t)0x76823301, (q31_t)0xcfa1210d, (q31_t)0x767fd304, (q31_t)0xcf9b4fe3,
+    (q31_t)0x767d72bf, (q31_t)0xcf957ed7,
+  (q31_t)0x767b1231, (q31_t)0xcf8fade9, (q31_t)0x7678b159, (q31_t)0xcf89dd18, (q31_t)0x76765038, (q31_t)0xcf840c65,
+    (q31_t)0x7673eecf, (q31_t)0xcf7e3bd1,
+  (q31_t)0x76718d1c, (q31_t)0xcf786b5a, (q31_t)0x766f2b20, (q31_t)0xcf729b01, (q31_t)0x766cc8db, (q31_t)0xcf6ccac6,
+    (q31_t)0x766a664d, (q31_t)0xcf66faa9,
+  (q31_t)0x76680376, (q31_t)0xcf612aaa, (q31_t)0x7665a056, (q31_t)0xcf5b5ac9, (q31_t)0x76633ced, (q31_t)0xcf558b06,
+    (q31_t)0x7660d93b, (q31_t)0xcf4fbb61,
+  (q31_t)0x765e7540, (q31_t)0xcf49ebda, (q31_t)0x765c10fc, (q31_t)0xcf441c71, (q31_t)0x7659ac6f, (q31_t)0xcf3e4d26,
+    (q31_t)0x76574798, (q31_t)0xcf387dfa,
+  (q31_t)0x7654e279, (q31_t)0xcf32aeeb, (q31_t)0x76527d11, (q31_t)0xcf2cdffa, (q31_t)0x76501760, (q31_t)0xcf271128,
+    (q31_t)0x764db166, (q31_t)0xcf214274,
+  (q31_t)0x764b4b23, (q31_t)0xcf1b73de, (q31_t)0x7648e497, (q31_t)0xcf15a566, (q31_t)0x76467dc2, (q31_t)0xcf0fd70c,
+    (q31_t)0x764416a4, (q31_t)0xcf0a08d0,
+  (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x763f478d, (q31_t)0xcefe6cb3, (q31_t)0x763cdf94, (q31_t)0xcef89ed2,
+    (q31_t)0x763a7752, (q31_t)0xcef2d110,
+  (q31_t)0x76380ec8, (q31_t)0xceed036b, (q31_t)0x7635a5f4, (q31_t)0xcee735e5, (q31_t)0x76333cd8, (q31_t)0xcee1687d,
+    (q31_t)0x7630d372, (q31_t)0xcedb9b33,
+  (q31_t)0x762e69c4, (q31_t)0xced5ce08, (q31_t)0x762bffcd, (q31_t)0xced000fb, (q31_t)0x7629958c, (q31_t)0xceca340c,
+    (q31_t)0x76272b03, (q31_t)0xcec4673c,
+  (q31_t)0x7624c031, (q31_t)0xcebe9a8a, (q31_t)0x76225517, (q31_t)0xceb8cdf7, (q31_t)0x761fe9b3, (q31_t)0xceb30181,
+    (q31_t)0x761d7e06, (q31_t)0xcead352b,
+  (q31_t)0x761b1211, (q31_t)0xcea768f2, (q31_t)0x7618a5d3, (q31_t)0xcea19cd8, (q31_t)0x7616394c, (q31_t)0xce9bd0dd,
+    (q31_t)0x7613cc7c, (q31_t)0xce960500,
+  (q31_t)0x76115f63, (q31_t)0xce903942, (q31_t)0x760ef201, (q31_t)0xce8a6da2, (q31_t)0x760c8457, (q31_t)0xce84a220,
+    (q31_t)0x760a1664, (q31_t)0xce7ed6bd,
+  (q31_t)0x7607a828, (q31_t)0xce790b79, (q31_t)0x760539a3, (q31_t)0xce734053, (q31_t)0x7602cad5, (q31_t)0xce6d754c,
+    (q31_t)0x76005bbf, (q31_t)0xce67aa63,
+  (q31_t)0x75fdec60, (q31_t)0xce61df99, (q31_t)0x75fb7cb8, (q31_t)0xce5c14ed, (q31_t)0x75f90cc7, (q31_t)0xce564a60,
+    (q31_t)0x75f69c8d, (q31_t)0xce507ff2,
+  (q31_t)0x75f42c0b, (q31_t)0xce4ab5a2, (q31_t)0x75f1bb40, (q31_t)0xce44eb71, (q31_t)0x75ef4a2c, (q31_t)0xce3f215f,
+    (q31_t)0x75ecd8cf, (q31_t)0xce39576c,
+  (q31_t)0x75ea672a, (q31_t)0xce338d97, (q31_t)0x75e7f53c, (q31_t)0xce2dc3e1, (q31_t)0x75e58305, (q31_t)0xce27fa49,
+    (q31_t)0x75e31086, (q31_t)0xce2230d0,
+  (q31_t)0x75e09dbd, (q31_t)0xce1c6777, (q31_t)0x75de2aac, (q31_t)0xce169e3b, (q31_t)0x75dbb753, (q31_t)0xce10d51f,
+    (q31_t)0x75d943b0, (q31_t)0xce0b0c21,
+  (q31_t)0x75d6cfc5, (q31_t)0xce054343, (q31_t)0x75d45b92, (q31_t)0xcdff7a83, (q31_t)0x75d1e715, (q31_t)0xcdf9b1e2,
+    (q31_t)0x75cf7250, (q31_t)0xcdf3e95f,
+  (q31_t)0x75ccfd42, (q31_t)0xcdee20fc, (q31_t)0x75ca87ec, (q31_t)0xcde858b8, (q31_t)0x75c8124d, (q31_t)0xcde29092,
+    (q31_t)0x75c59c65, (q31_t)0xcddcc88b,
+  (q31_t)0x75c32634, (q31_t)0xcdd700a4, (q31_t)0x75c0afbb, (q31_t)0xcdd138db, (q31_t)0x75be38fa, (q31_t)0xcdcb7131,
+    (q31_t)0x75bbc1ef, (q31_t)0xcdc5a9a6,
+  (q31_t)0x75b94a9c, (q31_t)0xcdbfe23a, (q31_t)0x75b6d301, (q31_t)0xcdba1aee, (q31_t)0x75b45b1d, (q31_t)0xcdb453c0,
+    (q31_t)0x75b1e2f0, (q31_t)0xcdae8cb1,
+  (q31_t)0x75af6a7b, (q31_t)0xcda8c5c1, (q31_t)0x75acf1bd, (q31_t)0xcda2fef0, (q31_t)0x75aa78b6, (q31_t)0xcd9d383f,
+    (q31_t)0x75a7ff67, (q31_t)0xcd9771ac,
+  (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x75a30bef, (q31_t)0xcd8be4e4, (q31_t)0x75a091c6, (q31_t)0xcd861eaf,
+    (q31_t)0x759e1755, (q31_t)0xcd805899,
+  (q31_t)0x759b9c9b, (q31_t)0xcd7a92a2, (q31_t)0x75992198, (q31_t)0xcd74ccca, (q31_t)0x7596a64d, (q31_t)0xcd6f0711,
+    (q31_t)0x75942ab9, (q31_t)0xcd694178,
+  (q31_t)0x7591aedd, (q31_t)0xcd637bfe, (q31_t)0x758f32b9, (q31_t)0xcd5db6a3, (q31_t)0x758cb64c, (q31_t)0xcd57f167,
+    (q31_t)0x758a3996, (q31_t)0xcd522c4a,
+  (q31_t)0x7587bc98, (q31_t)0xcd4c674d, (q31_t)0x75853f51, (q31_t)0xcd46a26f, (q31_t)0x7582c1c2, (q31_t)0xcd40ddb0,
+    (q31_t)0x758043ea, (q31_t)0xcd3b1911,
+  (q31_t)0x757dc5ca, (q31_t)0xcd355491, (q31_t)0x757b4762, (q31_t)0xcd2f9030, (q31_t)0x7578c8b0, (q31_t)0xcd29cbee,
+    (q31_t)0x757649b7, (q31_t)0xcd2407cc,
+  (q31_t)0x7573ca75, (q31_t)0xcd1e43ca, (q31_t)0x75714aea, (q31_t)0xcd187fe6, (q31_t)0x756ecb18, (q31_t)0xcd12bc22,
+    (q31_t)0x756c4afc, (q31_t)0xcd0cf87e,
+  (q31_t)0x7569ca99, (q31_t)0xcd0734f9, (q31_t)0x756749ec, (q31_t)0xcd017193, (q31_t)0x7564c8f8, (q31_t)0xccfbae4d,
+    (q31_t)0x756247bb, (q31_t)0xccf5eb26,
+  (q31_t)0x755fc635, (q31_t)0xccf0281f, (q31_t)0x755d4467, (q31_t)0xccea6538, (q31_t)0x755ac251, (q31_t)0xcce4a26f,
+    (q31_t)0x75583ff3, (q31_t)0xccdedfc7,
+  (q31_t)0x7555bd4c, (q31_t)0xccd91d3d, (q31_t)0x75533a5c, (q31_t)0xccd35ad4, (q31_t)0x7550b725, (q31_t)0xcccd988a,
+    (q31_t)0x754e33a4, (q31_t)0xccc7d65f,
+  (q31_t)0x754bafdc, (q31_t)0xccc21455, (q31_t)0x75492bcb, (q31_t)0xccbc5269, (q31_t)0x7546a772, (q31_t)0xccb6909e,
+    (q31_t)0x754422d0, (q31_t)0xccb0cef2,
+  (q31_t)0x75419de7, (q31_t)0xccab0d65, (q31_t)0x753f18b4, (q31_t)0xcca54bf9, (q31_t)0x753c933a, (q31_t)0xcc9f8aac,
+    (q31_t)0x753a0d77, (q31_t)0xcc99c97e,
+  (q31_t)0x7537876c, (q31_t)0xcc940871, (q31_t)0x75350118, (q31_t)0xcc8e4783, (q31_t)0x75327a7d, (q31_t)0xcc8886b5,
+    (q31_t)0x752ff399, (q31_t)0xcc82c607,
+  (q31_t)0x752d6c6c, (q31_t)0xcc7d0578, (q31_t)0x752ae4f8, (q31_t)0xcc774509, (q31_t)0x75285d3b, (q31_t)0xcc7184ba,
+    (q31_t)0x7525d536, (q31_t)0xcc6bc48b,
+  (q31_t)0x75234ce8, (q31_t)0xcc66047b, (q31_t)0x7520c453, (q31_t)0xcc60448c, (q31_t)0x751e3b75, (q31_t)0xcc5a84bc,
+    (q31_t)0x751bb24f, (q31_t)0xcc54c50c,
+  (q31_t)0x751928e0, (q31_t)0xcc4f057c, (q31_t)0x75169f2a, (q31_t)0xcc49460c, (q31_t)0x7514152b, (q31_t)0xcc4386bc,
+    (q31_t)0x75118ae4, (q31_t)0xcc3dc78b,
+  (q31_t)0x750f0054, (q31_t)0xcc38087b, (q31_t)0x750c757d, (q31_t)0xcc32498a, (q31_t)0x7509ea5d, (q31_t)0xcc2c8aba,
+    (q31_t)0x75075ef5, (q31_t)0xcc26cc09,
+  (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x7502474d, (q31_t)0xcc1b4f08, (q31_t)0x74ffbb0d, (q31_t)0xcc1590b8,
+    (q31_t)0x74fd2e84, (q31_t)0xcc0fd287,
+  (q31_t)0x74faa1b3, (q31_t)0xcc0a1477, (q31_t)0x74f8149a, (q31_t)0xcc045686, (q31_t)0x74f58739, (q31_t)0xcbfe98b6,
+    (q31_t)0x74f2f990, (q31_t)0xcbf8db05,
+  (q31_t)0x74f06b9e, (q31_t)0xcbf31d75, (q31_t)0x74eddd65, (q31_t)0xcbed6005, (q31_t)0x74eb4ee3, (q31_t)0xcbe7a2b5,
+    (q31_t)0x74e8c01a, (q31_t)0xcbe1e585,
+  (q31_t)0x74e63108, (q31_t)0xcbdc2876, (q31_t)0x74e3a1ae, (q31_t)0xcbd66b86, (q31_t)0x74e1120c, (q31_t)0xcbd0aeb7,
+    (q31_t)0x74de8221, (q31_t)0xcbcaf208,
+  (q31_t)0x74dbf1ef, (q31_t)0xcbc53579, (q31_t)0x74d96175, (q31_t)0xcbbf790a, (q31_t)0x74d6d0b2, (q31_t)0xcbb9bcbb,
+    (q31_t)0x74d43fa8, (q31_t)0xcbb4008d,
+  (q31_t)0x74d1ae55, (q31_t)0xcbae447f, (q31_t)0x74cf1cbb, (q31_t)0xcba88891, (q31_t)0x74cc8ad8, (q31_t)0xcba2ccc4,
+    (q31_t)0x74c9f8ad, (q31_t)0xcb9d1117,
+  (q31_t)0x74c7663a, (q31_t)0xcb97558a, (q31_t)0x74c4d380, (q31_t)0xcb919a1d, (q31_t)0x74c2407d, (q31_t)0xcb8bded1,
+    (q31_t)0x74bfad32, (q31_t)0xcb8623a5,
+  (q31_t)0x74bd199f, (q31_t)0xcb80689a, (q31_t)0x74ba85c4, (q31_t)0xcb7aadaf, (q31_t)0x74b7f1a1, (q31_t)0xcb74f2e4,
+    (q31_t)0x74b55d36, (q31_t)0xcb6f383a,
+  (q31_t)0x74b2c884, (q31_t)0xcb697db0, (q31_t)0x74b03389, (q31_t)0xcb63c347, (q31_t)0x74ad9e46, (q31_t)0xcb5e08fe,
+    (q31_t)0x74ab08bb, (q31_t)0xcb584ed6,
+  (q31_t)0x74a872e8, (q31_t)0xcb5294ce, (q31_t)0x74a5dccd, (q31_t)0xcb4cdae6, (q31_t)0x74a3466b, (q31_t)0xcb47211f,
+    (q31_t)0x74a0afc0, (q31_t)0xcb416779,
+  (q31_t)0x749e18cd, (q31_t)0xcb3badf3, (q31_t)0x749b8193, (q31_t)0xcb35f48d, (q31_t)0x7498ea11, (q31_t)0xcb303b49,
+    (q31_t)0x74965246, (q31_t)0xcb2a8224,
+  (q31_t)0x7493ba34, (q31_t)0xcb24c921, (q31_t)0x749121da, (q31_t)0xcb1f103e, (q31_t)0x748e8938, (q31_t)0xcb19577b,
+    (q31_t)0x748bf04d, (q31_t)0xcb139ed9,
+  (q31_t)0x7489571c, (q31_t)0xcb0de658, (q31_t)0x7486bda2, (q31_t)0xcb082df8, (q31_t)0x748423e0, (q31_t)0xcb0275b8,
+    (q31_t)0x748189d7, (q31_t)0xcafcbd99,
+  (q31_t)0x747eef85, (q31_t)0xcaf7059a, (q31_t)0x747c54ec, (q31_t)0xcaf14dbd, (q31_t)0x7479ba0b, (q31_t)0xcaeb9600,
+    (q31_t)0x74771ee2, (q31_t)0xcae5de64,
+  (q31_t)0x74748371, (q31_t)0xcae026e8, (q31_t)0x7471e7b8, (q31_t)0xcada6f8d, (q31_t)0x746f4bb8, (q31_t)0xcad4b853,
+    (q31_t)0x746caf70, (q31_t)0xcacf013a,
+  (q31_t)0x746a12df, (q31_t)0xcac94a42, (q31_t)0x74677608, (q31_t)0xcac3936b, (q31_t)0x7464d8e8, (q31_t)0xcabddcb4,
+    (q31_t)0x74623b80, (q31_t)0xcab8261e,
+  (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, (q31_t)0x745cffda, (q31_t)0xcaacb955, (q31_t)0x745a619b, (q31_t)0xcaa70322,
+    (q31_t)0x7457c314, (q31_t)0xcaa14d10,
+  (q31_t)0x74552446, (q31_t)0xca9b971e, (q31_t)0x74528530, (q31_t)0xca95e14e, (q31_t)0x744fe5d2, (q31_t)0xca902b9f,
+    (q31_t)0x744d462c, (q31_t)0xca8a7610,
+  (q31_t)0x744aa63f, (q31_t)0xca84c0a3, (q31_t)0x7448060a, (q31_t)0xca7f0b56, (q31_t)0x7445658d, (q31_t)0xca79562b,
+    (q31_t)0x7442c4c8, (q31_t)0xca73a120,
+  (q31_t)0x744023bc, (q31_t)0xca6dec37, (q31_t)0x743d8268, (q31_t)0xca68376e, (q31_t)0x743ae0cc, (q31_t)0xca6282c7,
+    (q31_t)0x74383ee9, (q31_t)0xca5cce40,
+  (q31_t)0x74359cbd, (q31_t)0xca5719db, (q31_t)0x7432fa4b, (q31_t)0xca516597, (q31_t)0x74305790, (q31_t)0xca4bb174,
+    (q31_t)0x742db48e, (q31_t)0xca45fd72,
+  (q31_t)0x742b1144, (q31_t)0xca404992, (q31_t)0x74286db3, (q31_t)0xca3a95d2, (q31_t)0x7425c9da, (q31_t)0xca34e234,
+    (q31_t)0x742325b9, (q31_t)0xca2f2eb6,
+  (q31_t)0x74208150, (q31_t)0xca297b5a, (q31_t)0x741ddca0, (q31_t)0xca23c820, (q31_t)0x741b37a9, (q31_t)0xca1e1506,
+    (q31_t)0x74189269, (q31_t)0xca18620e,
+  (q31_t)0x7415ece2, (q31_t)0xca12af37, (q31_t)0x74134714, (q31_t)0xca0cfc81, (q31_t)0x7410a0fe, (q31_t)0xca0749ec,
+    (q31_t)0x740dfaa0, (q31_t)0xca019779,
+  (q31_t)0x740b53fb, (q31_t)0xc9fbe527, (q31_t)0x7408ad0e, (q31_t)0xc9f632f6, (q31_t)0x740605d9, (q31_t)0xc9f080e7,
+    (q31_t)0x74035e5d, (q31_t)0xc9eacef9,
+  (q31_t)0x7400b69a, (q31_t)0xc9e51d2d, (q31_t)0x73fe0e8f, (q31_t)0xc9df6b81, (q31_t)0x73fb663c, (q31_t)0xc9d9b9f7,
+    (q31_t)0x73f8bda2, (q31_t)0xc9d4088f,
+  (q31_t)0x73f614c0, (q31_t)0xc9ce5748, (q31_t)0x73f36b97, (q31_t)0xc9c8a622, (q31_t)0x73f0c226, (q31_t)0xc9c2f51e,
+    (q31_t)0x73ee186e, (q31_t)0xc9bd443c,
+  (q31_t)0x73eb6e6e, (q31_t)0xc9b7937a, (q31_t)0x73e8c426, (q31_t)0xc9b1e2db, (q31_t)0x73e61997, (q31_t)0xc9ac325d,
+    (q31_t)0x73e36ec1, (q31_t)0xc9a68200,
+  (q31_t)0x73e0c3a3, (q31_t)0xc9a0d1c5, (q31_t)0x73de183e, (q31_t)0xc99b21ab, (q31_t)0x73db6c91, (q31_t)0xc99571b3,
+    (q31_t)0x73d8c09d, (q31_t)0xc98fc1dc,
+  (q31_t)0x73d61461, (q31_t)0xc98a1227, (q31_t)0x73d367de, (q31_t)0xc9846294, (q31_t)0x73d0bb13, (q31_t)0xc97eb322,
+    (q31_t)0x73ce0e01, (q31_t)0xc97903d2,
+  (q31_t)0x73cb60a8, (q31_t)0xc97354a4, (q31_t)0x73c8b307, (q31_t)0xc96da597, (q31_t)0x73c6051f, (q31_t)0xc967f6ac,
+    (q31_t)0x73c356ef, (q31_t)0xc96247e2,
+  (q31_t)0x73c0a878, (q31_t)0xc95c993a, (q31_t)0x73bdf9b9, (q31_t)0xc956eab4, (q31_t)0x73bb4ab3, (q31_t)0xc9513c50,
+    (q31_t)0x73b89b66, (q31_t)0xc94b8e0d,
+  (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x73b33bf5, (q31_t)0xc94031ed, (q31_t)0x73b08bd1, (q31_t)0xc93a8410,
+    (q31_t)0x73addb67, (q31_t)0xc934d654,
+  (q31_t)0x73ab2ab4, (q31_t)0xc92f28ba, (q31_t)0x73a879bb, (q31_t)0xc9297b42, (q31_t)0x73a5c87a, (q31_t)0xc923cdec,
+    (q31_t)0x73a316f2, (q31_t)0xc91e20b8,
+  (q31_t)0x73a06522, (q31_t)0xc91873a5, (q31_t)0x739db30b, (q31_t)0xc912c6b5, (q31_t)0x739b00ad, (q31_t)0xc90d19e6,
+    (q31_t)0x73984e07, (q31_t)0xc9076d39,
+  (q31_t)0x73959b1b, (q31_t)0xc901c0ae, (q31_t)0x7392e7e6, (q31_t)0xc8fc1445, (q31_t)0x7390346b, (q31_t)0xc8f667fe,
+    (q31_t)0x738d80a8, (q31_t)0xc8f0bbd9,
+  (q31_t)0x738acc9e, (q31_t)0xc8eb0fd6, (q31_t)0x7388184d, (q31_t)0xc8e563f5, (q31_t)0x738563b5, (q31_t)0xc8dfb836,
+    (q31_t)0x7382aed5, (q31_t)0xc8da0c99,
+  (q31_t)0x737ff9ae, (q31_t)0xc8d4611d, (q31_t)0x737d4440, (q31_t)0xc8ceb5c4, (q31_t)0x737a8e8a, (q31_t)0xc8c90a8d,
+    (q31_t)0x7377d88d, (q31_t)0xc8c35f78,
+  (q31_t)0x73752249, (q31_t)0xc8bdb485, (q31_t)0x73726bbe, (q31_t)0xc8b809b4, (q31_t)0x736fb4ec, (q31_t)0xc8b25f06,
+    (q31_t)0x736cfdd2, (q31_t)0xc8acb479,
+  (q31_t)0x736a4671, (q31_t)0xc8a70a0e, (q31_t)0x73678ec9, (q31_t)0xc8a15fc6, (q31_t)0x7364d6da, (q31_t)0xc89bb5a0,
+    (q31_t)0x73621ea4, (q31_t)0xc8960b9c,
+  (q31_t)0x735f6626, (q31_t)0xc89061ba, (q31_t)0x735cad61, (q31_t)0xc88ab7fa, (q31_t)0x7359f456, (q31_t)0xc8850e5d,
+    (q31_t)0x73573b03, (q31_t)0xc87f64e2,
+  (q31_t)0x73548168, (q31_t)0xc879bb89, (q31_t)0x7351c787, (q31_t)0xc8741252, (q31_t)0x734f0d5f, (q31_t)0xc86e693d,
+    (q31_t)0x734c52ef, (q31_t)0xc868c04b,
+  (q31_t)0x73499838, (q31_t)0xc863177b, (q31_t)0x7346dd3a, (q31_t)0xc85d6ece, (q31_t)0x734421f6, (q31_t)0xc857c642,
+    (q31_t)0x7341666a, (q31_t)0xc8521dd9,
+  (q31_t)0x733eaa96, (q31_t)0xc84c7593, (q31_t)0x733bee7c, (q31_t)0xc846cd6e, (q31_t)0x7339321b, (q31_t)0xc841256d,
+    (q31_t)0x73367572, (q31_t)0xc83b7d8d,
+  (q31_t)0x7333b883, (q31_t)0xc835d5d0, (q31_t)0x7330fb4d, (q31_t)0xc8302e35, (q31_t)0x732e3dcf, (q31_t)0xc82a86bd,
+    (q31_t)0x732b800a, (q31_t)0xc824df67,
+  (q31_t)0x7328c1ff, (q31_t)0xc81f3834, (q31_t)0x732603ac, (q31_t)0xc8199123, (q31_t)0x73234512, (q31_t)0xc813ea35,
+    (q31_t)0x73208632, (q31_t)0xc80e4369,
+  (q31_t)0x731dc70a, (q31_t)0xc8089cbf, (q31_t)0x731b079b, (q31_t)0xc802f638, (q31_t)0x731847e5, (q31_t)0xc7fd4fd4,
+    (q31_t)0x731587e8, (q31_t)0xc7f7a992,
+  (q31_t)0x7312c7a5, (q31_t)0xc7f20373, (q31_t)0x7310071a, (q31_t)0xc7ec5d76, (q31_t)0x730d4648, (q31_t)0xc7e6b79c,
+    (q31_t)0x730a8530, (q31_t)0xc7e111e5,
+  (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x73050229, (q31_t)0xc7d5c6de, (q31_t)0x7302403c, (q31_t)0xc7d0218e,
+    (q31_t)0x72ff7e07, (q31_t)0xc7ca7c61,
+  (q31_t)0x72fcbb8c, (q31_t)0xc7c4d757, (q31_t)0x72f9f8c9, (q31_t)0xc7bf3270, (q31_t)0x72f735c0, (q31_t)0xc7b98dab,
+    (q31_t)0x72f47270, (q31_t)0xc7b3e909,
+  (q31_t)0x72f1aed9, (q31_t)0xc7ae4489, (q31_t)0x72eeeafb, (q31_t)0xc7a8a02c, (q31_t)0x72ec26d6, (q31_t)0xc7a2fbf3,
+    (q31_t)0x72e9626a, (q31_t)0xc79d57db,
+  (q31_t)0x72e69db7, (q31_t)0xc797b3e7, (q31_t)0x72e3d8be, (q31_t)0xc7921015, (q31_t)0x72e1137d, (q31_t)0xc78c6c67,
+    (q31_t)0x72de4df6, (q31_t)0xc786c8db,
+  (q31_t)0x72db8828, (q31_t)0xc7812572, (q31_t)0x72d8c213, (q31_t)0xc77b822b, (q31_t)0x72d5fbb7, (q31_t)0xc775df08,
+    (q31_t)0x72d33514, (q31_t)0xc7703c08,
+  (q31_t)0x72d06e2b, (q31_t)0xc76a992a, (q31_t)0x72cda6fb, (q31_t)0xc764f66f, (q31_t)0x72cadf83, (q31_t)0xc75f53d7,
+    (q31_t)0x72c817c6, (q31_t)0xc759b163,
+  (q31_t)0x72c54fc1, (q31_t)0xc7540f11, (q31_t)0x72c28775, (q31_t)0xc74e6ce2, (q31_t)0x72bfbee3, (q31_t)0xc748cad6,
+    (q31_t)0x72bcf60a, (q31_t)0xc74328ed,
+  (q31_t)0x72ba2cea, (q31_t)0xc73d8727, (q31_t)0x72b76383, (q31_t)0xc737e584, (q31_t)0x72b499d6, (q31_t)0xc7324404,
+    (q31_t)0x72b1cfe1, (q31_t)0xc72ca2a7,
+  (q31_t)0x72af05a7, (q31_t)0xc727016d, (q31_t)0x72ac3b25, (q31_t)0xc7216056, (q31_t)0x72a9705c, (q31_t)0xc71bbf62,
+    (q31_t)0x72a6a54d, (q31_t)0xc7161e92,
+  (q31_t)0x72a3d9f7, (q31_t)0xc7107de4, (q31_t)0x72a10e5b, (q31_t)0xc70add5a, (q31_t)0x729e4277, (q31_t)0xc7053cf2,
+    (q31_t)0x729b764d, (q31_t)0xc6ff9cae,
+  (q31_t)0x7298a9dd, (q31_t)0xc6f9fc8d, (q31_t)0x7295dd25, (q31_t)0xc6f45c8f, (q31_t)0x72931027, (q31_t)0xc6eebcb5,
+    (q31_t)0x729042e3, (q31_t)0xc6e91cfd,
+  (q31_t)0x728d7557, (q31_t)0xc6e37d69, (q31_t)0x728aa785, (q31_t)0xc6ddddf8, (q31_t)0x7287d96c, (q31_t)0xc6d83eab,
+    (q31_t)0x72850b0d, (q31_t)0xc6d29f80,
+  (q31_t)0x72823c67, (q31_t)0xc6cd0079, (q31_t)0x727f6d7a, (q31_t)0xc6c76195, (q31_t)0x727c9e47, (q31_t)0xc6c1c2d4,
+    (q31_t)0x7279cecd, (q31_t)0xc6bc2437,
+  (q31_t)0x7276ff0d, (q31_t)0xc6b685bd, (q31_t)0x72742f05, (q31_t)0xc6b0e767, (q31_t)0x72715eb8, (q31_t)0xc6ab4933,
+    (q31_t)0x726e8e23, (q31_t)0xc6a5ab23,
+  (q31_t)0x726bbd48, (q31_t)0xc6a00d37, (q31_t)0x7268ec27, (q31_t)0xc69a6f6e, (q31_t)0x72661abf, (q31_t)0xc694d1c8,
+    (q31_t)0x72634910, (q31_t)0xc68f3446,
+  (q31_t)0x7260771b, (q31_t)0xc68996e7, (q31_t)0x725da4df, (q31_t)0xc683f9ab, (q31_t)0x725ad25d, (q31_t)0xc67e5c93,
+    (q31_t)0x7257ff94, (q31_t)0xc678bf9f,
+  (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x7252592f, (q31_t)0xc66d8620, (q31_t)0x724f8593, (q31_t)0xc667e996,
+    (q31_t)0x724cb1b0, (q31_t)0xc6624d30,
+  (q31_t)0x7249dd86, (q31_t)0xc65cb0ed, (q31_t)0x72470916, (q31_t)0xc65714cd, (q31_t)0x72443460, (q31_t)0xc65178d1,
+    (q31_t)0x72415f63, (q31_t)0xc64bdcf9,
+  (q31_t)0x723e8a20, (q31_t)0xc6464144, (q31_t)0x723bb496, (q31_t)0xc640a5b3, (q31_t)0x7238dec5, (q31_t)0xc63b0a46,
+    (q31_t)0x723608af, (q31_t)0xc6356efc,
+  (q31_t)0x72333251, (q31_t)0xc62fd3d6, (q31_t)0x72305bae, (q31_t)0xc62a38d4, (q31_t)0x722d84c4, (q31_t)0xc6249df5,
+    (q31_t)0x722aad93, (q31_t)0xc61f033a,
+  (q31_t)0x7227d61c, (q31_t)0xc61968a2, (q31_t)0x7224fe5f, (q31_t)0xc613ce2f, (q31_t)0x7222265b, (q31_t)0xc60e33df,
+    (q31_t)0x721f4e11, (q31_t)0xc60899b2,
+  (q31_t)0x721c7580, (q31_t)0xc602ffaa, (q31_t)0x72199ca9, (q31_t)0xc5fd65c5, (q31_t)0x7216c38c, (q31_t)0xc5f7cc04,
+    (q31_t)0x7213ea28, (q31_t)0xc5f23267,
+  (q31_t)0x7211107e, (q31_t)0xc5ec98ee, (q31_t)0x720e368d, (q31_t)0xc5e6ff98, (q31_t)0x720b5c57, (q31_t)0xc5e16667,
+    (q31_t)0x720881d9, (q31_t)0xc5dbcd59,
+  (q31_t)0x7205a716, (q31_t)0xc5d6346f, (q31_t)0x7202cc0c, (q31_t)0xc5d09ba9, (q31_t)0x71fff0bc, (q31_t)0xc5cb0307,
+    (q31_t)0x71fd1525, (q31_t)0xc5c56a89,
+  (q31_t)0x71fa3949, (q31_t)0xc5bfd22e, (q31_t)0x71f75d25, (q31_t)0xc5ba39f8, (q31_t)0x71f480bc, (q31_t)0xc5b4a1e5,
+    (q31_t)0x71f1a40c, (q31_t)0xc5af09f7,
+  (q31_t)0x71eec716, (q31_t)0xc5a9722c, (q31_t)0x71ebe9da, (q31_t)0xc5a3da86, (q31_t)0x71e90c57, (q31_t)0xc59e4303,
+    (q31_t)0x71e62e8f, (q31_t)0xc598aba5,
+  (q31_t)0x71e35080, (q31_t)0xc593146a, (q31_t)0x71e0722a, (q31_t)0xc58d7d54, (q31_t)0x71dd938f, (q31_t)0xc587e661,
+    (q31_t)0x71dab4ad, (q31_t)0xc5824f93,
+  (q31_t)0x71d7d585, (q31_t)0xc57cb8e9, (q31_t)0x71d4f617, (q31_t)0xc5772263, (q31_t)0x71d21662, (q31_t)0xc5718c00,
+    (q31_t)0x71cf3667, (q31_t)0xc56bf5c2,
+  (q31_t)0x71cc5626, (q31_t)0xc5665fa9, (q31_t)0x71c9759f, (q31_t)0xc560c9b3, (q31_t)0x71c694d2, (q31_t)0xc55b33e2,
+    (q31_t)0x71c3b3bf, (q31_t)0xc5559e34,
+  (q31_t)0x71c0d265, (q31_t)0xc55008ab, (q31_t)0x71bdf0c5, (q31_t)0xc54a7346, (q31_t)0x71bb0edf, (q31_t)0xc544de05,
+    (q31_t)0x71b82cb3, (q31_t)0xc53f48e9,
+  (q31_t)0x71b54a41, (q31_t)0xc539b3f1, (q31_t)0x71b26788, (q31_t)0xc5341f1d, (q31_t)0x71af848a, (q31_t)0xc52e8a6d,
+    (q31_t)0x71aca145, (q31_t)0xc528f5e1,
+  (q31_t)0x71a9bdba, (q31_t)0xc523617a, (q31_t)0x71a6d9e9, (q31_t)0xc51dcd37, (q31_t)0x71a3f5d2, (q31_t)0xc5183919,
+    (q31_t)0x71a11175, (q31_t)0xc512a51f,
+  (q31_t)0x719e2cd2, (q31_t)0xc50d1149, (q31_t)0x719b47e9, (q31_t)0xc5077d97, (q31_t)0x719862b9, (q31_t)0xc501ea0a,
+    (q31_t)0x71957d44, (q31_t)0xc4fc56a2,
+  (q31_t)0x71929789, (q31_t)0xc4f6c35d, (q31_t)0x718fb187, (q31_t)0xc4f1303d, (q31_t)0x718ccb3f, (q31_t)0xc4eb9d42,
+    (q31_t)0x7189e4b2, (q31_t)0xc4e60a6b,
+  (q31_t)0x7186fdde, (q31_t)0xc4e077b8, (q31_t)0x718416c4, (q31_t)0xc4dae52a, (q31_t)0x71812f65, (q31_t)0xc4d552c1,
+    (q31_t)0x717e47bf, (q31_t)0xc4cfc07c,
+  (q31_t)0x717b5fd3, (q31_t)0xc4ca2e5b, (q31_t)0x717877a1, (q31_t)0xc4c49c5f, (q31_t)0x71758f29, (q31_t)0xc4bf0a87,
+    (q31_t)0x7172a66c, (q31_t)0xc4b978d4,
+  (q31_t)0x716fbd68, (q31_t)0xc4b3e746, (q31_t)0x716cd41e, (q31_t)0xc4ae55dc, (q31_t)0x7169ea8f, (q31_t)0xc4a8c497,
+    (q31_t)0x716700b9, (q31_t)0xc4a33376,
+  (q31_t)0x7164169d, (q31_t)0xc49da27a, (q31_t)0x71612c3c, (q31_t)0xc49811a3, (q31_t)0x715e4194, (q31_t)0xc49280f0,
+    (q31_t)0x715b56a7, (q31_t)0xc48cf062,
+  (q31_t)0x71586b74, (q31_t)0xc4875ff9, (q31_t)0x71557ffa, (q31_t)0xc481cfb4, (q31_t)0x7152943b, (q31_t)0xc47c3f94,
+    (q31_t)0x714fa836, (q31_t)0xc476af98,
+  (q31_t)0x714cbbeb, (q31_t)0xc4711fc2, (q31_t)0x7149cf5a, (q31_t)0xc46b9010, (q31_t)0x7146e284, (q31_t)0xc4660083,
+    (q31_t)0x7143f567, (q31_t)0xc460711b,
+  (q31_t)0x71410805, (q31_t)0xc45ae1d7, (q31_t)0x713e1a5c, (q31_t)0xc45552b8, (q31_t)0x713b2c6e, (q31_t)0xc44fc3be,
+    (q31_t)0x71383e3a, (q31_t)0xc44a34e9,
+  (q31_t)0x71354fc0, (q31_t)0xc444a639, (q31_t)0x71326101, (q31_t)0xc43f17ad, (q31_t)0x712f71fb, (q31_t)0xc4398947,
+    (q31_t)0x712c82b0, (q31_t)0xc433fb05,
+  (q31_t)0x7129931f, (q31_t)0xc42e6ce8, (q31_t)0x7126a348, (q31_t)0xc428def0, (q31_t)0x7123b32b, (q31_t)0xc423511d,
+    (q31_t)0x7120c2c8, (q31_t)0xc41dc36f,
+  (q31_t)0x711dd220, (q31_t)0xc41835e6, (q31_t)0x711ae132, (q31_t)0xc412a882, (q31_t)0x7117effe, (q31_t)0xc40d1b42,
+    (q31_t)0x7114fe84, (q31_t)0xc4078e28,
+  (q31_t)0x71120cc5, (q31_t)0xc4020133, (q31_t)0x710f1ac0, (q31_t)0xc3fc7462, (q31_t)0x710c2875, (q31_t)0xc3f6e7b7,
+    (q31_t)0x710935e4, (q31_t)0xc3f15b31,
+  (q31_t)0x7106430e, (q31_t)0xc3ebced0, (q31_t)0x71034ff2, (q31_t)0xc3e64294, (q31_t)0x71005c90, (q31_t)0xc3e0b67d,
+    (q31_t)0x70fd68e9, (q31_t)0xc3db2a8b,
+  (q31_t)0x70fa74fc, (q31_t)0xc3d59ebe, (q31_t)0x70f780c9, (q31_t)0xc3d01316, (q31_t)0x70f48c50, (q31_t)0xc3ca8793,
+    (q31_t)0x70f19792, (q31_t)0xc3c4fc36,
+  (q31_t)0x70eea28e, (q31_t)0xc3bf70fd, (q31_t)0x70ebad45, (q31_t)0xc3b9e5ea, (q31_t)0x70e8b7b5, (q31_t)0xc3b45afc,
+    (q31_t)0x70e5c1e1, (q31_t)0xc3aed034,
+  (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x70dfd566, (q31_t)0xc3a3bb12, (q31_t)0x70dcdec0, (q31_t)0xc39e30b8,
+    (q31_t)0x70d9e7d5, (q31_t)0xc398a685,
+  (q31_t)0x70d6f0a4, (q31_t)0xc3931c76, (q31_t)0x70d3f92d, (q31_t)0xc38d928d, (q31_t)0x70d10171, (q31_t)0xc38808c9,
+    (q31_t)0x70ce096f, (q31_t)0xc3827f2a,
+  (q31_t)0x70cb1128, (q31_t)0xc37cf5b0, (q31_t)0x70c8189b, (q31_t)0xc3776c5c, (q31_t)0x70c51fc8, (q31_t)0xc371e32d,
+    (q31_t)0x70c226b0, (q31_t)0xc36c5a24,
+  (q31_t)0x70bf2d53, (q31_t)0xc366d140, (q31_t)0x70bc33b0, (q31_t)0xc3614881, (q31_t)0x70b939c7, (q31_t)0xc35bbfe8,
+    (q31_t)0x70b63f99, (q31_t)0xc3563774,
+  (q31_t)0x70b34525, (q31_t)0xc350af26, (q31_t)0x70b04a6b, (q31_t)0xc34b26fc, (q31_t)0x70ad4f6d, (q31_t)0xc3459ef9,
+    (q31_t)0x70aa5428, (q31_t)0xc340171b,
+  (q31_t)0x70a7589f, (q31_t)0xc33a8f62, (q31_t)0x70a45ccf, (q31_t)0xc33507cf, (q31_t)0x70a160ba, (q31_t)0xc32f8061,
+    (q31_t)0x709e6460, (q31_t)0xc329f919,
+  (q31_t)0x709b67c0, (q31_t)0xc32471f7, (q31_t)0x70986adb, (q31_t)0xc31eeaf9, (q31_t)0x70956db1, (q31_t)0xc3196422,
+    (q31_t)0x70927041, (q31_t)0xc313dd70,
+  (q31_t)0x708f728b, (q31_t)0xc30e56e4, (q31_t)0x708c7490, (q31_t)0xc308d07d, (q31_t)0x70897650, (q31_t)0xc3034a3c,
+    (q31_t)0x708677ca, (q31_t)0xc2fdc420,
+  (q31_t)0x708378ff, (q31_t)0xc2f83e2a, (q31_t)0x708079ee, (q31_t)0xc2f2b85a, (q31_t)0x707d7a98, (q31_t)0xc2ed32af,
+    (q31_t)0x707a7afd, (q31_t)0xc2e7ad2a,
+  (q31_t)0x70777b1c, (q31_t)0xc2e227cb, (q31_t)0x70747af6, (q31_t)0xc2dca291, (q31_t)0x70717a8a, (q31_t)0xc2d71d7e,
+    (q31_t)0x706e79d9, (q31_t)0xc2d1988f,
+  (q31_t)0x706b78e3, (q31_t)0xc2cc13c7, (q31_t)0x706877a7, (q31_t)0xc2c68f24, (q31_t)0x70657626, (q31_t)0xc2c10aa7,
+    (q31_t)0x70627460, (q31_t)0xc2bb8650,
+  (q31_t)0x705f7255, (q31_t)0xc2b6021f, (q31_t)0x705c7004, (q31_t)0xc2b07e14, (q31_t)0x70596d6d, (q31_t)0xc2aafa2e,
+    (q31_t)0x70566a92, (q31_t)0xc2a5766e,
+  (q31_t)0x70536771, (q31_t)0xc29ff2d4, (q31_t)0x7050640b, (q31_t)0xc29a6f60, (q31_t)0x704d6060, (q31_t)0xc294ec12,
+    (q31_t)0x704a5c6f, (q31_t)0xc28f68e9,
+  (q31_t)0x70475839, (q31_t)0xc289e5e7, (q31_t)0x704453be, (q31_t)0xc284630a, (q31_t)0x70414efd, (q31_t)0xc27ee054,
+    (q31_t)0x703e49f8, (q31_t)0xc2795dc3,
+  (q31_t)0x703b44ad, (q31_t)0xc273db58, (q31_t)0x70383f1d, (q31_t)0xc26e5913, (q31_t)0x70353947, (q31_t)0xc268d6f5,
+    (q31_t)0x7032332d, (q31_t)0xc26354fc,
+  (q31_t)0x702f2ccd, (q31_t)0xc25dd329, (q31_t)0x702c2628, (q31_t)0xc258517c, (q31_t)0x70291f3e, (q31_t)0xc252cff5,
+    (q31_t)0x7026180e, (q31_t)0xc24d4e95,
+  (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x702008e0, (q31_t)0xc2424c46, (q31_t)0x701d00e1, (q31_t)0xc23ccb57,
+    (q31_t)0x7019f89d, (q31_t)0xc2374a8f,
+  (q31_t)0x7016f014, (q31_t)0xc231c9ec, (q31_t)0x7013e746, (q31_t)0xc22c4970, (q31_t)0x7010de32, (q31_t)0xc226c91a,
+    (q31_t)0x700dd4da, (q31_t)0xc22148ea,
+  (q31_t)0x700acb3c, (q31_t)0xc21bc8e1, (q31_t)0x7007c159, (q31_t)0xc21648fd, (q31_t)0x7004b731, (q31_t)0xc210c940,
+    (q31_t)0x7001acc4, (q31_t)0xc20b49a9,
+  (q31_t)0x6ffea212, (q31_t)0xc205ca38, (q31_t)0x6ffb971b, (q31_t)0xc2004aed, (q31_t)0x6ff88bde, (q31_t)0xc1facbc9,
+    (q31_t)0x6ff5805d, (q31_t)0xc1f54cca,
+  (q31_t)0x6ff27497, (q31_t)0xc1efcdf3, (q31_t)0x6fef688b, (q31_t)0xc1ea4f41, (q31_t)0x6fec5c3b, (q31_t)0xc1e4d0b6,
+    (q31_t)0x6fe94fa5, (q31_t)0xc1df5251,
+  (q31_t)0x6fe642ca, (q31_t)0xc1d9d412, (q31_t)0x6fe335ab, (q31_t)0xc1d455f9, (q31_t)0x6fe02846, (q31_t)0xc1ced807,
+    (q31_t)0x6fdd1a9c, (q31_t)0xc1c95a3c,
+  (q31_t)0x6fda0cae, (q31_t)0xc1c3dc97, (q31_t)0x6fd6fe7a, (q31_t)0xc1be5f18, (q31_t)0x6fd3f001, (q31_t)0xc1b8e1bf,
+    (q31_t)0x6fd0e144, (q31_t)0xc1b3648d,
+  (q31_t)0x6fcdd241, (q31_t)0xc1ade781, (q31_t)0x6fcac2fa, (q31_t)0xc1a86a9c, (q31_t)0x6fc7b36d, (q31_t)0xc1a2edde,
+    (q31_t)0x6fc4a39c, (q31_t)0xc19d7145,
+  (q31_t)0x6fc19385, (q31_t)0xc197f4d4, (q31_t)0x6fbe832a, (q31_t)0xc1927888, (q31_t)0x6fbb728a, (q31_t)0xc18cfc63,
+    (q31_t)0x6fb861a4, (q31_t)0xc1878065,
+  (q31_t)0x6fb5507a, (q31_t)0xc182048d, (q31_t)0x6fb23f0b, (q31_t)0xc17c88dc, (q31_t)0x6faf2d57, (q31_t)0xc1770d52,
+    (q31_t)0x6fac1b5f, (q31_t)0xc17191ee,
+  (q31_t)0x6fa90921, (q31_t)0xc16c16b0, (q31_t)0x6fa5f69e, (q31_t)0xc1669b99, (q31_t)0x6fa2e3d7, (q31_t)0xc16120a9,
+    (q31_t)0x6f9fd0cb, (q31_t)0xc15ba5df,
+  (q31_t)0x6f9cbd79, (q31_t)0xc1562b3d, (q31_t)0x6f99a9e3, (q31_t)0xc150b0c0, (q31_t)0x6f969608, (q31_t)0xc14b366b,
+    (q31_t)0x6f9381e9, (q31_t)0xc145bc3c,
+  (q31_t)0x6f906d84, (q31_t)0xc1404233, (q31_t)0x6f8d58db, (q31_t)0xc13ac852, (q31_t)0x6f8a43ed, (q31_t)0xc1354e97,
+    (q31_t)0x6f872eba, (q31_t)0xc12fd503,
+  (q31_t)0x6f841942, (q31_t)0xc12a5b95, (q31_t)0x6f810386, (q31_t)0xc124e24f, (q31_t)0x6f7ded84, (q31_t)0xc11f692f,
+    (q31_t)0x6f7ad73e, (q31_t)0xc119f036,
+  (q31_t)0x6f77c0b3, (q31_t)0xc1147764, (q31_t)0x6f74a9e4, (q31_t)0xc10efeb8, (q31_t)0x6f7192cf, (q31_t)0xc1098634,
+    (q31_t)0x6f6e7b76, (q31_t)0xc1040dd6,
+  (q31_t)0x6f6b63d8, (q31_t)0xc0fe959f, (q31_t)0x6f684bf6, (q31_t)0xc0f91d8f, (q31_t)0x6f6533ce, (q31_t)0xc0f3a5a6,
+    (q31_t)0x6f621b62, (q31_t)0xc0ee2de3,
+  (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6f5be9bc, (q31_t)0xc0e33ed4, (q31_t)0x6f58d082, (q31_t)0xc0ddc786,
+    (q31_t)0x6f55b703, (q31_t)0xc0d8505f,
+  (q31_t)0x6f529d40, (q31_t)0xc0d2d960, (q31_t)0x6f4f8338, (q31_t)0xc0cd6287, (q31_t)0x6f4c68eb, (q31_t)0xc0c7ebd6,
+    (q31_t)0x6f494e5a, (q31_t)0xc0c2754b,
+  (q31_t)0x6f463383, (q31_t)0xc0bcfee7, (q31_t)0x6f431869, (q31_t)0xc0b788ab, (q31_t)0x6f3ffd09, (q31_t)0xc0b21295,
+    (q31_t)0x6f3ce165, (q31_t)0xc0ac9ca6,
+  (q31_t)0x6f39c57d, (q31_t)0xc0a726df, (q31_t)0x6f36a94f, (q31_t)0xc0a1b13e, (q31_t)0x6f338cde, (q31_t)0xc09c3bc5,
+    (q31_t)0x6f307027, (q31_t)0xc096c673,
+  (q31_t)0x6f2d532c, (q31_t)0xc0915148, (q31_t)0x6f2a35ed, (q31_t)0xc08bdc44, (q31_t)0x6f271868, (q31_t)0xc0866767,
+    (q31_t)0x6f23faa0, (q31_t)0xc080f2b1,
+  (q31_t)0x6f20dc92, (q31_t)0xc07b7e23, (q31_t)0x6f1dbe41, (q31_t)0xc07609bb, (q31_t)0x6f1a9faa, (q31_t)0xc070957b,
+    (q31_t)0x6f1780cf, (q31_t)0xc06b2162,
+  (q31_t)0x6f1461b0, (q31_t)0xc065ad70, (q31_t)0x6f11424c, (q31_t)0xc06039a6, (q31_t)0x6f0e22a3, (q31_t)0xc05ac603,
+    (q31_t)0x6f0b02b6, (q31_t)0xc0555287,
+  (q31_t)0x6f07e285, (q31_t)0xc04fdf32, (q31_t)0x6f04c20f, (q31_t)0xc04a6c05, (q31_t)0x6f01a155, (q31_t)0xc044f8fe,
+    (q31_t)0x6efe8056, (q31_t)0xc03f8620,
+  (q31_t)0x6efb5f12, (q31_t)0xc03a1368, (q31_t)0x6ef83d8a, (q31_t)0xc034a0d8, (q31_t)0x6ef51bbe, (q31_t)0xc02f2e6f,
+    (q31_t)0x6ef1f9ad, (q31_t)0xc029bc2e,
+  (q31_t)0x6eeed758, (q31_t)0xc0244a14, (q31_t)0x6eebb4bf, (q31_t)0xc01ed821, (q31_t)0x6ee891e1, (q31_t)0xc0196656,
+    (q31_t)0x6ee56ebe, (q31_t)0xc013f4b2,
+  (q31_t)0x6ee24b57, (q31_t)0xc00e8336, (q31_t)0x6edf27ac, (q31_t)0xc00911e1, (q31_t)0x6edc03bc, (q31_t)0xc003a0b3,
+    (q31_t)0x6ed8df88, (q31_t)0xbffe2fad,
+  (q31_t)0x6ed5bb10, (q31_t)0xbff8bece, (q31_t)0x6ed29653, (q31_t)0xbff34e17, (q31_t)0x6ecf7152, (q31_t)0xbfeddd88,
+    (q31_t)0x6ecc4c0d, (q31_t)0xbfe86d20,
+  (q31_t)0x6ec92683, (q31_t)0xbfe2fcdf, (q31_t)0x6ec600b5, (q31_t)0xbfdd8cc6, (q31_t)0x6ec2daa2, (q31_t)0xbfd81cd5,
+    (q31_t)0x6ebfb44b, (q31_t)0xbfd2ad0b,
+  (q31_t)0x6ebc8db0, (q31_t)0xbfcd3d69, (q31_t)0x6eb966d1, (q31_t)0xbfc7cdee, (q31_t)0x6eb63fad, (q31_t)0xbfc25e9b,
+    (q31_t)0x6eb31845, (q31_t)0xbfbcef70,
+  (q31_t)0x6eaff099, (q31_t)0xbfb7806c, (q31_t)0x6eacc8a8, (q31_t)0xbfb21190, (q31_t)0x6ea9a073, (q31_t)0xbfaca2dc,
+    (q31_t)0x6ea677fa, (q31_t)0xbfa7344f,
+  (q31_t)0x6ea34f3d, (q31_t)0xbfa1c5ea, (q31_t)0x6ea0263b, (q31_t)0xbf9c57ac, (q31_t)0x6e9cfcf5, (q31_t)0xbf96e997,
+    (q31_t)0x6e99d36b, (q31_t)0xbf917ba9,
+  (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, (q31_t)0x6e937f8a, (q31_t)0xbf86a044, (q31_t)0x6e905534, (q31_t)0xbf8132ce,
+    (q31_t)0x6e8d2a99, (q31_t)0xbf7bc57f,
+  (q31_t)0x6e89ffb9, (q31_t)0xbf765858, (q31_t)0x6e86d496, (q31_t)0xbf70eb59, (q31_t)0x6e83a92f, (q31_t)0xbf6b7e81,
+    (q31_t)0x6e807d83, (q31_t)0xbf6611d2,
+  (q31_t)0x6e7d5193, (q31_t)0xbf60a54a, (q31_t)0x6e7a255f, (q31_t)0xbf5b38ea, (q31_t)0x6e76f8e7, (q31_t)0xbf55ccb2,
+    (q31_t)0x6e73cc2b, (q31_t)0xbf5060a2,
+  (q31_t)0x6e709f2a, (q31_t)0xbf4af4ba, (q31_t)0x6e6d71e6, (q31_t)0xbf4588fa, (q31_t)0x6e6a445d, (q31_t)0xbf401d61,
+    (q31_t)0x6e671690, (q31_t)0xbf3ab1f1,
+  (q31_t)0x6e63e87f, (q31_t)0xbf3546a8, (q31_t)0x6e60ba2a, (q31_t)0xbf2fdb88, (q31_t)0x6e5d8b91, (q31_t)0xbf2a708f,
+    (q31_t)0x6e5a5cb4, (q31_t)0xbf2505bf,
+  (q31_t)0x6e572d93, (q31_t)0xbf1f9b16, (q31_t)0x6e53fe2e, (q31_t)0xbf1a3096, (q31_t)0x6e50ce84, (q31_t)0xbf14c63d,
+    (q31_t)0x6e4d9e97, (q31_t)0xbf0f5c0d,
+  (q31_t)0x6e4a6e66, (q31_t)0xbf09f205, (q31_t)0x6e473df0, (q31_t)0xbf048824, (q31_t)0x6e440d37, (q31_t)0xbeff1e6c,
+    (q31_t)0x6e40dc39, (q31_t)0xbef9b4dc,
+  (q31_t)0x6e3daaf8, (q31_t)0xbef44b74, (q31_t)0x6e3a7972, (q31_t)0xbeeee234, (q31_t)0x6e3747a9, (q31_t)0xbee9791c,
+    (q31_t)0x6e34159b, (q31_t)0xbee4102d,
+  (q31_t)0x6e30e34a, (q31_t)0xbedea765, (q31_t)0x6e2db0b4, (q31_t)0xbed93ec6, (q31_t)0x6e2a7ddb, (q31_t)0xbed3d64f,
+    (q31_t)0x6e274abe, (q31_t)0xbece6e00,
+  (q31_t)0x6e24175c, (q31_t)0xbec905d9, (q31_t)0x6e20e3b7, (q31_t)0xbec39ddb, (q31_t)0x6e1dafce, (q31_t)0xbebe3605,
+    (q31_t)0x6e1a7ba1, (q31_t)0xbeb8ce57,
+  (q31_t)0x6e174730, (q31_t)0xbeb366d1, (q31_t)0x6e14127b, (q31_t)0xbeadff74, (q31_t)0x6e10dd82, (q31_t)0xbea8983f,
+    (q31_t)0x6e0da845, (q31_t)0xbea33132,
+  (q31_t)0x6e0a72c5, (q31_t)0xbe9dca4e, (q31_t)0x6e073d00, (q31_t)0xbe986391, (q31_t)0x6e0406f8, (q31_t)0xbe92fcfe,
+    (q31_t)0x6e00d0ac, (q31_t)0xbe8d9692,
+  (q31_t)0x6dfd9a1c, (q31_t)0xbe88304f, (q31_t)0x6dfa6348, (q31_t)0xbe82ca35, (q31_t)0x6df72c30, (q31_t)0xbe7d6442,
+    (q31_t)0x6df3f4d4, (q31_t)0xbe77fe78,
+  (q31_t)0x6df0bd35, (q31_t)0xbe7298d7, (q31_t)0x6ded8552, (q31_t)0xbe6d335e, (q31_t)0x6dea4d2b, (q31_t)0xbe67ce0d,
+    (q31_t)0x6de714c0, (q31_t)0xbe6268e5,
+  (q31_t)0x6de3dc11, (q31_t)0xbe5d03e6, (q31_t)0x6de0a31f, (q31_t)0xbe579f0f, (q31_t)0x6ddd69e9, (q31_t)0xbe523a60,
+    (q31_t)0x6dda306f, (q31_t)0xbe4cd5da,
+  (q31_t)0x6dd6f6b1, (q31_t)0xbe47717c, (q31_t)0x6dd3bcaf, (q31_t)0xbe420d47, (q31_t)0x6dd0826a, (q31_t)0xbe3ca93b,
+    (q31_t)0x6dcd47e1, (q31_t)0xbe374557,
+  (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6dc6d204, (q31_t)0xbe2c7e09, (q31_t)0x6dc396b0, (q31_t)0xbe271a9f,
+    (q31_t)0x6dc05b18, (q31_t)0xbe21b75d,
+  (q31_t)0x6dbd1f3c, (q31_t)0xbe1c5444, (q31_t)0x6db9e31d, (q31_t)0xbe16f154, (q31_t)0x6db6a6ba, (q31_t)0xbe118e8c,
+    (q31_t)0x6db36a14, (q31_t)0xbe0c2bed,
+  (q31_t)0x6db02d29, (q31_t)0xbe06c977, (q31_t)0x6daceffb, (q31_t)0xbe01672a, (q31_t)0x6da9b28a, (q31_t)0xbdfc0505,
+    (q31_t)0x6da674d5, (q31_t)0xbdf6a309,
+  (q31_t)0x6da336dc, (q31_t)0xbdf14135, (q31_t)0x6d9ff89f, (q31_t)0xbdebdf8b, (q31_t)0x6d9cba1f, (q31_t)0xbde67e09,
+    (q31_t)0x6d997b5b, (q31_t)0xbde11cb0,
+  (q31_t)0x6d963c54, (q31_t)0xbddbbb7f, (q31_t)0x6d92fd09, (q31_t)0xbdd65a78, (q31_t)0x6d8fbd7a, (q31_t)0xbdd0f999,
+    (q31_t)0x6d8c7da8, (q31_t)0xbdcb98e3,
+  (q31_t)0x6d893d93, (q31_t)0xbdc63856, (q31_t)0x6d85fd39, (q31_t)0xbdc0d7f2, (q31_t)0x6d82bc9d, (q31_t)0xbdbb77b7,
+    (q31_t)0x6d7f7bbc, (q31_t)0xbdb617a4,
+  (q31_t)0x6d7c3a98, (q31_t)0xbdb0b7bb, (q31_t)0x6d78f931, (q31_t)0xbdab57fa, (q31_t)0x6d75b786, (q31_t)0xbda5f862,
+    (q31_t)0x6d727597, (q31_t)0xbda098f3,
+  (q31_t)0x6d6f3365, (q31_t)0xbd9b39ad, (q31_t)0x6d6bf0f0, (q31_t)0xbd95da91, (q31_t)0x6d68ae37, (q31_t)0xbd907b9d,
+    (q31_t)0x6d656b3a, (q31_t)0xbd8b1cd2,
+  (q31_t)0x6d6227fa, (q31_t)0xbd85be30, (q31_t)0x6d5ee477, (q31_t)0xbd805fb7, (q31_t)0x6d5ba0b0, (q31_t)0xbd7b0167,
+    (q31_t)0x6d585ca6, (q31_t)0xbd75a340,
+  (q31_t)0x6d551858, (q31_t)0xbd704542, (q31_t)0x6d51d3c6, (q31_t)0xbd6ae76d, (q31_t)0x6d4e8ef2, (q31_t)0xbd6589c1,
+    (q31_t)0x6d4b49da, (q31_t)0xbd602c3f,
+  (q31_t)0x6d48047e, (q31_t)0xbd5acee5, (q31_t)0x6d44bedf, (q31_t)0xbd5571b5, (q31_t)0x6d4178fd, (q31_t)0xbd5014ad,
+    (q31_t)0x6d3e32d7, (q31_t)0xbd4ab7cf,
+  (q31_t)0x6d3aec6e, (q31_t)0xbd455b1a, (q31_t)0x6d37a5c1, (q31_t)0xbd3ffe8e, (q31_t)0x6d345ed1, (q31_t)0xbd3aa22c,
+    (q31_t)0x6d31179e, (q31_t)0xbd3545f2,
+  (q31_t)0x6d2dd027, (q31_t)0xbd2fe9e2, (q31_t)0x6d2a886e, (q31_t)0xbd2a8dfb, (q31_t)0x6d274070, (q31_t)0xbd25323d,
+    (q31_t)0x6d23f830, (q31_t)0xbd1fd6a8,
+  (q31_t)0x6d20afac, (q31_t)0xbd1a7b3d, (q31_t)0x6d1d66e4, (q31_t)0xbd151ffb, (q31_t)0x6d1a1dda, (q31_t)0xbd0fc4e2,
+    (q31_t)0x6d16d48c, (q31_t)0xbd0a69f2,
+  (q31_t)0x6d138afb, (q31_t)0xbd050f2c, (q31_t)0x6d104126, (q31_t)0xbcffb48f, (q31_t)0x6d0cf70f, (q31_t)0xbcfa5a1b,
+    (q31_t)0x6d09acb4, (q31_t)0xbcf4ffd1,
+  (q31_t)0x6d066215, (q31_t)0xbcefa5b0, (q31_t)0x6d031734, (q31_t)0xbcea4bb9, (q31_t)0x6cffcc0f, (q31_t)0xbce4f1eb,
+    (q31_t)0x6cfc80a7, (q31_t)0xbcdf9846,
+  (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6cf5e90d, (q31_t)0xbcd4e579, (q31_t)0x6cf29cdc, (q31_t)0xbccf8c50,
+    (q31_t)0x6cef5067, (q31_t)0xbcca3351,
+  (q31_t)0x6cec03af, (q31_t)0xbcc4da7b, (q31_t)0x6ce8b6b4, (q31_t)0xbcbf81cf, (q31_t)0x6ce56975, (q31_t)0xbcba294d,
+    (q31_t)0x6ce21bf4, (q31_t)0xbcb4d0f4,
+  (q31_t)0x6cdece2f, (q31_t)0xbcaf78c4, (q31_t)0x6cdb8027, (q31_t)0xbcaa20be, (q31_t)0x6cd831dc, (q31_t)0xbca4c8e1,
+    (q31_t)0x6cd4e34e, (q31_t)0xbc9f712e,
+  (q31_t)0x6cd1947c, (q31_t)0xbc9a19a5, (q31_t)0x6cce4568, (q31_t)0xbc94c245, (q31_t)0x6ccaf610, (q31_t)0xbc8f6b0f,
+    (q31_t)0x6cc7a676, (q31_t)0xbc8a1402,
+  (q31_t)0x6cc45698, (q31_t)0xbc84bd1f, (q31_t)0x6cc10677, (q31_t)0xbc7f6665, (q31_t)0x6cbdb613, (q31_t)0xbc7a0fd6,
+    (q31_t)0x6cba656c, (q31_t)0xbc74b96f,
+  (q31_t)0x6cb71482, (q31_t)0xbc6f6333, (q31_t)0x6cb3c355, (q31_t)0xbc6a0d20, (q31_t)0x6cb071e4, (q31_t)0xbc64b737,
+    (q31_t)0x6cad2031, (q31_t)0xbc5f6177,
+  (q31_t)0x6ca9ce3b, (q31_t)0xbc5a0be2, (q31_t)0x6ca67c01, (q31_t)0xbc54b676, (q31_t)0x6ca32985, (q31_t)0xbc4f6134,
+    (q31_t)0x6c9fd6c6, (q31_t)0xbc4a0c1b,
+  (q31_t)0x6c9c83c3, (q31_t)0xbc44b72c, (q31_t)0x6c99307e, (q31_t)0xbc3f6267, (q31_t)0x6c95dcf6, (q31_t)0xbc3a0dcc,
+    (q31_t)0x6c92892a, (q31_t)0xbc34b95b,
+  (q31_t)0x6c8f351c, (q31_t)0xbc2f6513, (q31_t)0x6c8be0cb, (q31_t)0xbc2a10f6, (q31_t)0x6c888c36, (q31_t)0xbc24bd02,
+    (q31_t)0x6c85375f, (q31_t)0xbc1f6938,
+  (q31_t)0x6c81e245, (q31_t)0xbc1a1598, (q31_t)0x6c7e8ce8, (q31_t)0xbc14c221, (q31_t)0x6c7b3748, (q31_t)0xbc0f6ed5,
+    (q31_t)0x6c77e165, (q31_t)0xbc0a1bb3,
+  (q31_t)0x6c748b3f, (q31_t)0xbc04c8ba, (q31_t)0x6c7134d7, (q31_t)0xbbff75ec, (q31_t)0x6c6dde2b, (q31_t)0xbbfa2347,
+    (q31_t)0x6c6a873d, (q31_t)0xbbf4d0cc,
+  (q31_t)0x6c67300b, (q31_t)0xbbef7e7c, (q31_t)0x6c63d897, (q31_t)0xbbea2c55, (q31_t)0x6c6080e0, (q31_t)0xbbe4da58,
+    (q31_t)0x6c5d28e6, (q31_t)0xbbdf8885,
+  (q31_t)0x6c59d0a9, (q31_t)0xbbda36dd, (q31_t)0x6c56782a, (q31_t)0xbbd4e55e, (q31_t)0x6c531f67, (q31_t)0xbbcf940a,
+    (q31_t)0x6c4fc662, (q31_t)0xbbca42df,
+  (q31_t)0x6c4c6d1a, (q31_t)0xbbc4f1df, (q31_t)0x6c49138f, (q31_t)0xbbbfa108, (q31_t)0x6c45b9c1, (q31_t)0xbbba505c,
+    (q31_t)0x6c425fb1, (q31_t)0xbbb4ffda,
+  (q31_t)0x6c3f055d, (q31_t)0xbbafaf82, (q31_t)0x6c3baac7, (q31_t)0xbbaa5f54, (q31_t)0x6c384fef, (q31_t)0xbba50f50,
+    (q31_t)0x6c34f4d3, (q31_t)0xbb9fbf77,
+  (q31_t)0x6c319975, (q31_t)0xbb9a6fc7, (q31_t)0x6c2e3dd4, (q31_t)0xbb952042, (q31_t)0x6c2ae1f0, (q31_t)0xbb8fd0e7,
+    (q31_t)0x6c2785ca, (q31_t)0xbb8a81b6,
+  (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6c20ccb4, (q31_t)0xbb7fe3d3, (q31_t)0x6c1d6fc6, (q31_t)0xbb7a9521,
+    (q31_t)0x6c1a1295, (q31_t)0xbb754699,
+  (q31_t)0x6c16b521, (q31_t)0xbb6ff83c, (q31_t)0x6c13576a, (q31_t)0xbb6aaa09, (q31_t)0x6c0ff971, (q31_t)0xbb655c00,
+    (q31_t)0x6c0c9b35, (q31_t)0xbb600e21,
+  (q31_t)0x6c093cb6, (q31_t)0xbb5ac06d, (q31_t)0x6c05ddf5, (q31_t)0xbb5572e3, (q31_t)0x6c027ef1, (q31_t)0xbb502583,
+    (q31_t)0x6bff1faa, (q31_t)0xbb4ad84e,
+  (q31_t)0x6bfbc021, (q31_t)0xbb458b43, (q31_t)0x6bf86055, (q31_t)0xbb403e63, (q31_t)0x6bf50047, (q31_t)0xbb3af1ad,
+    (q31_t)0x6bf19ff6, (q31_t)0xbb35a521,
+  (q31_t)0x6bee3f62, (q31_t)0xbb3058c0, (q31_t)0x6beade8c, (q31_t)0xbb2b0c8a, (q31_t)0x6be77d74, (q31_t)0xbb25c07d,
+    (q31_t)0x6be41c18, (q31_t)0xbb20749c,
+  (q31_t)0x6be0ba7b, (q31_t)0xbb1b28e4, (q31_t)0x6bdd589a, (q31_t)0xbb15dd57, (q31_t)0x6bd9f677, (q31_t)0xbb1091f5,
+    (q31_t)0x6bd69412, (q31_t)0xbb0b46bd,
+  (q31_t)0x6bd3316a, (q31_t)0xbb05fbb0, (q31_t)0x6bcfce80, (q31_t)0xbb00b0ce, (q31_t)0x6bcc6b53, (q31_t)0xbafb6615,
+    (q31_t)0x6bc907e3, (q31_t)0xbaf61b88,
+  (q31_t)0x6bc5a431, (q31_t)0xbaf0d125, (q31_t)0x6bc2403d, (q31_t)0xbaeb86ed, (q31_t)0x6bbedc06, (q31_t)0xbae63cdf,
+    (q31_t)0x6bbb778d, (q31_t)0xbae0f2fc,
+  (q31_t)0x6bb812d1, (q31_t)0xbadba943, (q31_t)0x6bb4add3, (q31_t)0xbad65fb5, (q31_t)0x6bb14892, (q31_t)0xbad11652,
+    (q31_t)0x6bade30f, (q31_t)0xbacbcd1a,
+  (q31_t)0x6baa7d49, (q31_t)0xbac6840c, (q31_t)0x6ba71741, (q31_t)0xbac13b29, (q31_t)0x6ba3b0f7, (q31_t)0xbabbf270,
+    (q31_t)0x6ba04a6a, (q31_t)0xbab6a9e3,
+  (q31_t)0x6b9ce39b, (q31_t)0xbab16180, (q31_t)0x6b997c8a, (q31_t)0xbaac1948, (q31_t)0x6b961536, (q31_t)0xbaa6d13a,
+    (q31_t)0x6b92ada0, (q31_t)0xbaa18958,
+  (q31_t)0x6b8f45c7, (q31_t)0xba9c41a0, (q31_t)0x6b8bddac, (q31_t)0xba96fa13, (q31_t)0x6b88754f, (q31_t)0xba91b2b1,
+    (q31_t)0x6b850caf, (q31_t)0xba8c6b79,
+  (q31_t)0x6b81a3cd, (q31_t)0xba87246d, (q31_t)0x6b7e3aa9, (q31_t)0xba81dd8b, (q31_t)0x6b7ad142, (q31_t)0xba7c96d4,
+    (q31_t)0x6b776799, (q31_t)0xba775048,
+  (q31_t)0x6b73fdae, (q31_t)0xba7209e7, (q31_t)0x6b709381, (q31_t)0xba6cc3b1, (q31_t)0x6b6d2911, (q31_t)0xba677da6,
+    (q31_t)0x6b69be5f, (q31_t)0xba6237c5,
+  (q31_t)0x6b66536b, (q31_t)0xba5cf210, (q31_t)0x6b62e834, (q31_t)0xba57ac86, (q31_t)0x6b5f7cbc, (q31_t)0xba526726,
+    (q31_t)0x6b5c1101, (q31_t)0xba4d21f2,
+  (q31_t)0x6b58a503, (q31_t)0xba47dce8, (q31_t)0x6b5538c4, (q31_t)0xba42980a, (q31_t)0x6b51cc42, (q31_t)0xba3d5356,
+    (q31_t)0x6b4e5f7f, (q31_t)0xba380ece,
+  (q31_t)0x6b4af279, (q31_t)0xba32ca71, (q31_t)0x6b478530, (q31_t)0xba2d863e, (q31_t)0x6b4417a6, (q31_t)0xba284237,
+    (q31_t)0x6b40a9d9, (q31_t)0xba22fe5b,
+  (q31_t)0x6b3d3bcb, (q31_t)0xba1dbaaa, (q31_t)0x6b39cd7a, (q31_t)0xba187724, (q31_t)0x6b365ee7, (q31_t)0xba1333c9,
+    (q31_t)0x6b32f012, (q31_t)0xba0df099,
+  (q31_t)0x6b2f80fb, (q31_t)0xba08ad95, (q31_t)0x6b2c11a1, (q31_t)0xba036abb, (q31_t)0x6b28a206, (q31_t)0xb9fe280d,
+    (q31_t)0x6b253228, (q31_t)0xb9f8e58a,
+  (q31_t)0x6b21c208, (q31_t)0xb9f3a332, (q31_t)0x6b1e51a7, (q31_t)0xb9ee6106, (q31_t)0x6b1ae103, (q31_t)0xb9e91f04,
+    (q31_t)0x6b17701d, (q31_t)0xb9e3dd2e,
+  (q31_t)0x6b13fef5, (q31_t)0xb9de9b83, (q31_t)0x6b108d8b, (q31_t)0xb9d95a03, (q31_t)0x6b0d1bdf, (q31_t)0xb9d418af,
+    (q31_t)0x6b09a9f1, (q31_t)0xb9ced786,
+  (q31_t)0x6b0637c1, (q31_t)0xb9c99688, (q31_t)0x6b02c54f, (q31_t)0xb9c455b6, (q31_t)0x6aff529a, (q31_t)0xb9bf150e,
+    (q31_t)0x6afbdfa4, (q31_t)0xb9b9d493,
+  (q31_t)0x6af86c6c, (q31_t)0xb9b49442, (q31_t)0x6af4f8f2, (q31_t)0xb9af541d, (q31_t)0x6af18536, (q31_t)0xb9aa1423,
+    (q31_t)0x6aee1138, (q31_t)0xb9a4d455,
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+    (q31_t)0x6ae03eac, (q31_t)0xb98fd6cd,
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+    (q31_t)0x6ad26802, (q31_t)0xb97adbfd,
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+    (q31_t)0x6ac48d39, (q31_t)0xb965e3e5,
+  (q31_t)0x6ac115e2, (q31_t)0xb960a64c, (q31_t)0x6abd9e49, (q31_t)0xb95b68de, (q31_t)0x6aba266e, (q31_t)0xb9562b9c,
+    (q31_t)0x6ab6ae52, (q31_t)0xb950ee86,
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+    (q31_t)0x6aa8cb4e, (q31_t)0xb93bfbe0,
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+    (q31_t)0x6a9ae42e, (q31_t)0xb9270bf5,
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+    (q31_t)0x6a8cf8f1, (q31_t)0xb9121ec5,
+  (q31_t)0x6a897d7d, (q31_t)0xb90ce3e6, (q31_t)0x6a8601c8, (q31_t)0xb907a933, (q31_t)0x6a8285d1, (q31_t)0xb9026eac,
+    (q31_t)0x6a7f0999, (q31_t)0xb8fd3451,
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+    (q31_t)0x6a711625, (q31_t)0xb8e84c99,
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+    (q31_t)0x6a631e97, (q31_t)0xb8d367a0,
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+    (q31_t)0x6a5522ef, (q31_t)0xb8be8565,
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+    (q31_t)0x6a47232e, (q31_t)0xb8a9a5e9,
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+    (q31_t)0x6a391f54, (q31_t)0xb894c92d,
+  (q31_t)0x6a359db9, (q31_t)0xb88f926d, (q31_t)0x6a321bdd, (q31_t)0xb88a5bd8, (q31_t)0x6a2e99c0, (q31_t)0xb885256f,
+    (q31_t)0x6a2b1761, (q31_t)0xb87fef33,
+  (q31_t)0x6a2794c1, (q31_t)0xb87ab922, (q31_t)0x6a2411df, (q31_t)0xb875833e, (q31_t)0x6a208ebb, (q31_t)0xb8704d85,
+    (q31_t)0x6a1d0b57, (q31_t)0xb86b17f9,
+  (q31_t)0x6a1987b0, (q31_t)0xb865e299, (q31_t)0x6a1603c8, (q31_t)0xb860ad66, (q31_t)0x6a127f9f, (q31_t)0xb85b785e,
+    (q31_t)0x6a0efb35, (q31_t)0xb8564383,
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+    (q31_t)0x6a00e6fc, (q31_t)0xb84171cf,
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+    (q31_t)0x69f2cead, (q31_t)0xb82ca2e0,
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+    (q31_t)0x69e4b249, (q31_t)0xb817d6b6,
+  (q31_t)0x69e12a8c, (q31_t)0xb812a41a, (q31_t)0x69dda28f, (q31_t)0xb80d71aa, (q31_t)0x69da1a50, (q31_t)0xb8083f67,
+    (q31_t)0x69d691cf, (q31_t)0xb8030d51,
+  (q31_t)0x69d3090e, (q31_t)0xb7fddb67, (q31_t)0x69cf800b, (q31_t)0xb7f8a9a9, (q31_t)0x69cbf6c7, (q31_t)0xb7f37818,
+    (q31_t)0x69c86d41, (q31_t)0xb7ee46b3,
+  (q31_t)0x69c4e37a, (q31_t)0xb7e9157a, (q31_t)0x69c15973, (q31_t)0xb7e3e46e, (q31_t)0x69bdcf29, (q31_t)0xb7deb38f,
+    (q31_t)0x69ba449f, (q31_t)0xb7d982dc,
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+    (q31_t)0x69ac17e9, (q31_t)0xb7c4c1cd,
+  (q31_t)0x69a88c19, (q31_t)0xb7bf91f8, (q31_t)0x69a50007, (q31_t)0xb7ba6251, (q31_t)0x69a173b5, (q31_t)0xb7b532d6,
+    (q31_t)0x699de721, (q31_t)0xb7b00387,
+  (q31_t)0x699a5a4c, (q31_t)0xb7aad465, (q31_t)0x6996cd35, (q31_t)0xb7a5a570, (q31_t)0x69933fde, (q31_t)0xb7a076a7,
+    (q31_t)0x698fb246, (q31_t)0xb79b480b,
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+    (q31_t)0x69817959, (q31_t)0xb7868f59,
+  (q31_t)0x697dea7b, (q31_t)0xb781619c, (q31_t)0x697a5b5c, (q31_t)0xb77c340c, (q31_t)0x6976cbfc, (q31_t)0xb77706a9,
+    (q31_t)0x69733c5b, (q31_t)0xb771d972,
+  (q31_t)0x696fac78, (q31_t)0xb76cac69, (q31_t)0x696c1c55, (q31_t)0xb7677f8c, (q31_t)0x69688bf1, (q31_t)0xb76252db,
+    (q31_t)0x6964fb4c, (q31_t)0xb75d2658,
+  (q31_t)0x69616a65, (q31_t)0xb757fa01, (q31_t)0x695dd93e, (q31_t)0xb752cdd8, (q31_t)0x695a47d6, (q31_t)0xb74da1db,
+    (q31_t)0x6956b62d, (q31_t)0xb748760b,
+  (q31_t)0x69532442, (q31_t)0xb7434a67, (q31_t)0x694f9217, (q31_t)0xb73e1ef1, (q31_t)0x694bffab, (q31_t)0xb738f3a7,
+    (q31_t)0x69486cfe, (q31_t)0xb733c88b,
+  (q31_t)0x6944da10, (q31_t)0xb72e9d9b, (q31_t)0x694146e1, (q31_t)0xb72972d8, (q31_t)0x693db371, (q31_t)0xb7244842,
+    (q31_t)0x693a1fc0, (q31_t)0xb71f1dd9,
+  (q31_t)0x69368bce, (q31_t)0xb719f39e, (q31_t)0x6932f79b, (q31_t)0xb714c98e, (q31_t)0x692f6328, (q31_t)0xb70f9fac,
+    (q31_t)0x692bce73, (q31_t)0xb70a75f7,
+  (q31_t)0x6928397e, (q31_t)0xb7054c6f, (q31_t)0x6924a448, (q31_t)0xb7002314, (q31_t)0x69210ed1, (q31_t)0xb6faf9e6,
+    (q31_t)0x691d7919, (q31_t)0xb6f5d0e5,
+  (q31_t)0x6919e320, (q31_t)0xb6f0a812, (q31_t)0x69164ce7, (q31_t)0xb6eb7f6b, (q31_t)0x6912b66c, (q31_t)0xb6e656f1,
+    (q31_t)0x690f1fb1, (q31_t)0xb6e12ea4,
+  (q31_t)0x690b88b5, (q31_t)0xb6dc0685, (q31_t)0x6907f178, (q31_t)0xb6d6de92, (q31_t)0x690459fb, (q31_t)0xb6d1b6cd,
+    (q31_t)0x6900c23c, (q31_t)0xb6cc8f35,
+  (q31_t)0x68fd2a3d, (q31_t)0xb6c767ca, (q31_t)0x68f991fd, (q31_t)0xb6c2408c, (q31_t)0x68f5f97d, (q31_t)0xb6bd197c,
+    (q31_t)0x68f260bb, (q31_t)0xb6b7f298,
+  (q31_t)0x68eec7b9, (q31_t)0xb6b2cbe2, (q31_t)0x68eb2e76, (q31_t)0xb6ada559, (q31_t)0x68e794f3, (q31_t)0xb6a87efd,
+    (q31_t)0x68e3fb2e, (q31_t)0xb6a358ce,
+  (q31_t)0x68e06129, (q31_t)0xb69e32cd, (q31_t)0x68dcc6e4, (q31_t)0xb6990cf9, (q31_t)0x68d92c5d, (q31_t)0xb693e752,
+    (q31_t)0x68d59196, (q31_t)0xb68ec1d9,
+  (q31_t)0x68d1f68f, (q31_t)0xb6899c8d, (q31_t)0x68ce5b46, (q31_t)0xb684776e, (q31_t)0x68cabfbd, (q31_t)0xb67f527c,
+    (q31_t)0x68c723f3, (q31_t)0xb67a2db8,
+  (q31_t)0x68c387e9, (q31_t)0xb6750921, (q31_t)0x68bfeb9e, (q31_t)0xb66fe4b8, (q31_t)0x68bc4f13, (q31_t)0xb66ac07c,
+    (q31_t)0x68b8b247, (q31_t)0xb6659c6d,
+  (q31_t)0x68b5153a, (q31_t)0xb660788c, (q31_t)0x68b177ed, (q31_t)0xb65b54d8, (q31_t)0x68adda5f, (q31_t)0xb6563151,
+    (q31_t)0x68aa3c90, (q31_t)0xb6510df8,
+  (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x68a30031, (q31_t)0xb646c7ce, (q31_t)0x689f61a1, (q31_t)0xb641a4fe,
+    (q31_t)0x689bc2d1, (q31_t)0xb63c825b,
+  (q31_t)0x689823bf, (q31_t)0xb6375fe5, (q31_t)0x6894846e, (q31_t)0xb6323d9d, (q31_t)0x6890e4dc, (q31_t)0xb62d1b82,
+    (q31_t)0x688d4509, (q31_t)0xb627f995,
+  (q31_t)0x6889a4f6, (q31_t)0xb622d7d6, (q31_t)0x688604a2, (q31_t)0xb61db644, (q31_t)0x6882640e, (q31_t)0xb61894df,
+    (q31_t)0x687ec339, (q31_t)0xb61373a9,
+  (q31_t)0x687b2224, (q31_t)0xb60e529f, (q31_t)0x687780ce, (q31_t)0xb60931c4, (q31_t)0x6873df38, (q31_t)0xb6041116,
+    (q31_t)0x68703d62, (q31_t)0xb5fef095,
+  (q31_t)0x686c9b4b, (q31_t)0xb5f9d043, (q31_t)0x6868f8f4, (q31_t)0xb5f4b01e, (q31_t)0x6865565c, (q31_t)0xb5ef9026,
+    (q31_t)0x6861b384, (q31_t)0xb5ea705d,
+  (q31_t)0x685e106c, (q31_t)0xb5e550c1, (q31_t)0x685a6d13, (q31_t)0xb5e03153, (q31_t)0x6856c979, (q31_t)0xb5db1212,
+    (q31_t)0x685325a0, (q31_t)0xb5d5f2ff,
+  (q31_t)0x684f8186, (q31_t)0xb5d0d41a, (q31_t)0x684bdd2c, (q31_t)0xb5cbb563, (q31_t)0x68483891, (q31_t)0xb5c696da,
+    (q31_t)0x684493b6, (q31_t)0xb5c1787e,
+  (q31_t)0x6840ee9b, (q31_t)0xb5bc5a50, (q31_t)0x683d493f, (q31_t)0xb5b73c50, (q31_t)0x6839a3a4, (q31_t)0xb5b21e7e,
+    (q31_t)0x6835fdc7, (q31_t)0xb5ad00d9,
+  (q31_t)0x683257ab, (q31_t)0xb5a7e362, (q31_t)0x682eb14e, (q31_t)0xb5a2c61a, (q31_t)0x682b0ab1, (q31_t)0xb59da8ff,
+    (q31_t)0x682763d4, (q31_t)0xb5988c12,
+  (q31_t)0x6823bcb7, (q31_t)0xb5936f53, (q31_t)0x68201559, (q31_t)0xb58e52c2, (q31_t)0x681c6dbb, (q31_t)0xb589365e,
+    (q31_t)0x6818c5dd, (q31_t)0xb5841a29,
+  (q31_t)0x68151dbe, (q31_t)0xb57efe22, (q31_t)0x68117560, (q31_t)0xb579e248, (q31_t)0x680dccc1, (q31_t)0xb574c69d,
+    (q31_t)0x680a23e2, (q31_t)0xb56fab1f,
+  (q31_t)0x68067ac3, (q31_t)0xb56a8fd0, (q31_t)0x6802d164, (q31_t)0xb56574ae, (q31_t)0x67ff27c4, (q31_t)0xb56059bb,
+    (q31_t)0x67fb7de5, (q31_t)0xb55b3ef5,
+  (q31_t)0x67f7d3c5, (q31_t)0xb556245e, (q31_t)0x67f42965, (q31_t)0xb55109f5, (q31_t)0x67f07ec5, (q31_t)0xb54befba,
+    (q31_t)0x67ecd3e5, (q31_t)0xb546d5ac,
+  (q31_t)0x67e928c5, (q31_t)0xb541bbcd, (q31_t)0x67e57d64, (q31_t)0xb53ca21c, (q31_t)0x67e1d1c4, (q31_t)0xb5378899,
+    (q31_t)0x67de25e3, (q31_t)0xb5326f45,
+  (q31_t)0x67da79c3, (q31_t)0xb52d561e, (q31_t)0x67d6cd62, (q31_t)0xb5283d26, (q31_t)0x67d320c1, (q31_t)0xb523245b,
+    (q31_t)0x67cf73e1, (q31_t)0xb51e0bbf,
+  (q31_t)0x67cbc6c0, (q31_t)0xb518f351, (q31_t)0x67c8195f, (q31_t)0xb513db12, (q31_t)0x67c46bbe, (q31_t)0xb50ec300,
+    (q31_t)0x67c0bddd, (q31_t)0xb509ab1d,
+  (q31_t)0x67bd0fbd, (q31_t)0xb5049368, (q31_t)0x67b9615c, (q31_t)0xb4ff7be1, (q31_t)0x67b5b2bb, (q31_t)0xb4fa6489,
+    (q31_t)0x67b203da, (q31_t)0xb4f54d5f,
+  (q31_t)0x67ae54ba, (q31_t)0xb4f03663, (q31_t)0x67aaa559, (q31_t)0xb4eb1f95, (q31_t)0x67a6f5b8, (q31_t)0xb4e608f6,
+    (q31_t)0x67a345d8, (q31_t)0xb4e0f285,
+  (q31_t)0x679f95b7, (q31_t)0xb4dbdc42, (q31_t)0x679be557, (q31_t)0xb4d6c62e, (q31_t)0x679834b6, (q31_t)0xb4d1b048,
+    (q31_t)0x679483d6, (q31_t)0xb4cc9a90,
+  (q31_t)0x6790d2b6, (q31_t)0xb4c78507, (q31_t)0x678d2156, (q31_t)0xb4c26fad, (q31_t)0x67896fb6, (q31_t)0xb4bd5a80,
+    (q31_t)0x6785bdd6, (q31_t)0xb4b84582,
+  (q31_t)0x67820bb7, (q31_t)0xb4b330b3, (q31_t)0x677e5957, (q31_t)0xb4ae1c12, (q31_t)0x677aa6b8, (q31_t)0xb4a9079f,
+    (q31_t)0x6776f3d9, (q31_t)0xb4a3f35b,
+  (q31_t)0x677340ba, (q31_t)0xb49edf45, (q31_t)0x676f8d5b, (q31_t)0xb499cb5e, (q31_t)0x676bd9bd, (q31_t)0xb494b7a6,
+    (q31_t)0x676825de, (q31_t)0xb48fa41c,
+  (q31_t)0x676471c0, (q31_t)0xb48a90c0, (q31_t)0x6760bd62, (q31_t)0xb4857d93, (q31_t)0x675d08c4, (q31_t)0xb4806a95,
+    (q31_t)0x675953e7, (q31_t)0xb47b57c5,
+  (q31_t)0x67559eca, (q31_t)0xb4764523, (q31_t)0x6751e96d, (q31_t)0xb47132b1, (q31_t)0x674e33d0, (q31_t)0xb46c206d,
+    (q31_t)0x674a7df4, (q31_t)0xb4670e57,
+  (q31_t)0x6746c7d8, (q31_t)0xb461fc70, (q31_t)0x6743117c, (q31_t)0xb45ceab8, (q31_t)0x673f5ae0, (q31_t)0xb457d92f,
+    (q31_t)0x673ba405, (q31_t)0xb452c7d4,
+  (q31_t)0x6737ecea, (q31_t)0xb44db6a8, (q31_t)0x67343590, (q31_t)0xb448a5aa, (q31_t)0x67307df5, (q31_t)0xb44394db,
+    (q31_t)0x672cc61c, (q31_t)0xb43e843b,
+  (q31_t)0x67290e02, (q31_t)0xb43973ca, (q31_t)0x672555a9, (q31_t)0xb4346387, (q31_t)0x67219d10, (q31_t)0xb42f5373,
+    (q31_t)0x671de438, (q31_t)0xb42a438e,
+  (q31_t)0x671a2b20, (q31_t)0xb42533d8, (q31_t)0x671671c8, (q31_t)0xb4202451, (q31_t)0x6712b831, (q31_t)0xb41b14f8,
+    (q31_t)0x670efe5a, (q31_t)0xb41605ce,
+  (q31_t)0x670b4444, (q31_t)0xb410f6d3, (q31_t)0x670789ee, (q31_t)0xb40be807, (q31_t)0x6703cf58, (q31_t)0xb406d969,
+    (q31_t)0x67001483, (q31_t)0xb401cafb,
+  (q31_t)0x66fc596f, (q31_t)0xb3fcbcbb, (q31_t)0x66f89e1b, (q31_t)0xb3f7aeaa, (q31_t)0x66f4e287, (q31_t)0xb3f2a0c9,
+    (q31_t)0x66f126b4, (q31_t)0xb3ed9316,
+  (q31_t)0x66ed6aa1, (q31_t)0xb3e88592, (q31_t)0x66e9ae4f, (q31_t)0xb3e3783d, (q31_t)0x66e5f1be, (q31_t)0xb3de6b17,
+    (q31_t)0x66e234ed, (q31_t)0xb3d95e1f,
+  (q31_t)0x66de77dc, (q31_t)0xb3d45157, (q31_t)0x66daba8c, (q31_t)0xb3cf44be, (q31_t)0x66d6fcfd, (q31_t)0xb3ca3854,
+    (q31_t)0x66d33f2e, (q31_t)0xb3c52c19,
+  (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x66cbc2d2, (q31_t)0xb3bb142f, (q31_t)0x66c80445, (q31_t)0xb3b60881,
+    (q31_t)0x66c44579, (q31_t)0xb3b0fd02,
+  (q31_t)0x66c0866d, (q31_t)0xb3abf1b2, (q31_t)0x66bcc721, (q31_t)0xb3a6e691, (q31_t)0x66b90797, (q31_t)0xb3a1dba0,
+    (q31_t)0x66b547cd, (q31_t)0xb39cd0dd,
+  (q31_t)0x66b187c3, (q31_t)0xb397c649, (q31_t)0x66adc77b, (q31_t)0xb392bbe5, (q31_t)0x66aa06f3, (q31_t)0xb38db1b0,
+    (q31_t)0x66a6462b, (q31_t)0xb388a7aa,
+  (q31_t)0x66a28524, (q31_t)0xb3839dd3, (q31_t)0x669ec3de, (q31_t)0xb37e942b, (q31_t)0x669b0259, (q31_t)0xb3798ab2,
+    (q31_t)0x66974095, (q31_t)0xb3748169,
+  (q31_t)0x66937e91, (q31_t)0xb36f784f, (q31_t)0x668fbc4e, (q31_t)0xb36a6f64, (q31_t)0x668bf9cb, (q31_t)0xb36566a8,
+    (q31_t)0x66883709, (q31_t)0xb3605e1c,
+  (q31_t)0x66847408, (q31_t)0xb35b55bf, (q31_t)0x6680b0c8, (q31_t)0xb3564d91, (q31_t)0x667ced49, (q31_t)0xb3514592,
+    (q31_t)0x6679298a, (q31_t)0xb34c3dc3,
+  (q31_t)0x6675658c, (q31_t)0xb3473623, (q31_t)0x6671a14f, (q31_t)0xb3422eb2, (q31_t)0x666ddcd3, (q31_t)0xb33d2771,
+    (q31_t)0x666a1818, (q31_t)0xb338205f,
+  (q31_t)0x6666531d, (q31_t)0xb333197c, (q31_t)0x66628de4, (q31_t)0xb32e12c9, (q31_t)0x665ec86b, (q31_t)0xb3290c45,
+    (q31_t)0x665b02b3, (q31_t)0xb32405f1,
+  (q31_t)0x66573cbb, (q31_t)0xb31effcc, (q31_t)0x66537685, (q31_t)0xb319f9d6, (q31_t)0x664fb010, (q31_t)0xb314f410,
+    (q31_t)0x664be95b, (q31_t)0xb30fee79,
+  (q31_t)0x66482267, (q31_t)0xb30ae912, (q31_t)0x66445b35, (q31_t)0xb305e3da, (q31_t)0x664093c3, (q31_t)0xb300ded2,
+    (q31_t)0x663ccc12, (q31_t)0xb2fbd9f9,
+  (q31_t)0x66390422, (q31_t)0xb2f6d550, (q31_t)0x66353bf3, (q31_t)0xb2f1d0d6, (q31_t)0x66317385, (q31_t)0xb2eccc8c,
+    (q31_t)0x662daad8, (q31_t)0xb2e7c871,
+  (q31_t)0x6629e1ec, (q31_t)0xb2e2c486, (q31_t)0x662618c1, (q31_t)0xb2ddc0ca, (q31_t)0x66224f56, (q31_t)0xb2d8bd3e,
+    (q31_t)0x661e85ad, (q31_t)0xb2d3b9e2,
+  (q31_t)0x661abbc5, (q31_t)0xb2ceb6b5, (q31_t)0x6616f19e, (q31_t)0xb2c9b3b8, (q31_t)0x66132738, (q31_t)0xb2c4b0ea,
+    (q31_t)0x660f5c93, (q31_t)0xb2bfae4c,
+  (q31_t)0x660b91af, (q31_t)0xb2baabde, (q31_t)0x6607c68c, (q31_t)0xb2b5a99f, (q31_t)0x6603fb2a, (q31_t)0xb2b0a790,
+    (q31_t)0x66002f89, (q31_t)0xb2aba5b1,
+  (q31_t)0x65fc63a9, (q31_t)0xb2a6a402, (q31_t)0x65f8978b, (q31_t)0xb2a1a282, (q31_t)0x65f4cb2d, (q31_t)0xb29ca132,
+    (q31_t)0x65f0fe91, (q31_t)0xb297a011,
+  (q31_t)0x65ed31b5, (q31_t)0xb2929f21, (q31_t)0x65e9649b, (q31_t)0xb28d9e60, (q31_t)0x65e59742, (q31_t)0xb2889dcf,
+    (q31_t)0x65e1c9aa, (q31_t)0xb2839d6d,
+  (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x65da2dbd, (q31_t)0xb2799d3a, (q31_t)0x65d65f69, (q31_t)0xb2749d68,
+    (q31_t)0x65d290d6, (q31_t)0xb26f9dc6,
+  (q31_t)0x65cec204, (q31_t)0xb26a9e54, (q31_t)0x65caf2f3, (q31_t)0xb2659f12, (q31_t)0x65c723a3, (q31_t)0xb2609fff,
+    (q31_t)0x65c35415, (q31_t)0xb25ba11d,
+  (q31_t)0x65bf8447, (q31_t)0xb256a26a, (q31_t)0x65bbb43b, (q31_t)0xb251a3e7, (q31_t)0x65b7e3f1, (q31_t)0xb24ca594,
+    (q31_t)0x65b41367, (q31_t)0xb247a771,
+  (q31_t)0x65b0429f, (q31_t)0xb242a97e, (q31_t)0x65ac7198, (q31_t)0xb23dabbb, (q31_t)0x65a8a052, (q31_t)0xb238ae28,
+    (q31_t)0x65a4cece, (q31_t)0xb233b0c5,
+  (q31_t)0x65a0fd0b, (q31_t)0xb22eb392, (q31_t)0x659d2b09, (q31_t)0xb229b68f, (q31_t)0x659958c9, (q31_t)0xb224b9bc,
+    (q31_t)0x6595864a, (q31_t)0xb21fbd19,
+  (q31_t)0x6591b38c, (q31_t)0xb21ac0a6, (q31_t)0x658de08f, (q31_t)0xb215c463, (q31_t)0x658a0d54, (q31_t)0xb210c850,
+    (q31_t)0x658639db, (q31_t)0xb20bcc6d,
+  (q31_t)0x65826622, (q31_t)0xb206d0ba, (q31_t)0x657e922b, (q31_t)0xb201d537, (q31_t)0x657abdf6, (q31_t)0xb1fcd9e5,
+    (q31_t)0x6576e982, (q31_t)0xb1f7dec2,
+  (q31_t)0x657314cf, (q31_t)0xb1f2e3d0, (q31_t)0x656f3fde, (q31_t)0xb1ede90e, (q31_t)0x656b6aae, (q31_t)0xb1e8ee7c,
+    (q31_t)0x6567953f, (q31_t)0xb1e3f41a,
+  (q31_t)0x6563bf92, (q31_t)0xb1def9e9, (q31_t)0x655fe9a7, (q31_t)0xb1d9ffe7, (q31_t)0x655c137d, (q31_t)0xb1d50616,
+    (q31_t)0x65583d14, (q31_t)0xb1d00c75,
+  (q31_t)0x6554666d, (q31_t)0xb1cb1304, (q31_t)0x65508f87, (q31_t)0xb1c619c3, (q31_t)0x654cb863, (q31_t)0xb1c120b3,
+    (q31_t)0x6548e101, (q31_t)0xb1bc27d3,
+  (q31_t)0x6545095f, (q31_t)0xb1b72f23, (q31_t)0x65413180, (q31_t)0xb1b236a4, (q31_t)0x653d5962, (q31_t)0xb1ad3e55,
+    (q31_t)0x65398105, (q31_t)0xb1a84636,
+  (q31_t)0x6535a86b, (q31_t)0xb1a34e47, (q31_t)0x6531cf91, (q31_t)0xb19e5689, (q31_t)0x652df679, (q31_t)0xb1995efb,
+    (q31_t)0x652a1d23, (q31_t)0xb194679e,
+  (q31_t)0x6526438f, (q31_t)0xb18f7071, (q31_t)0x652269bc, (q31_t)0xb18a7974, (q31_t)0x651e8faa, (q31_t)0xb18582a8,
+    (q31_t)0x651ab55b, (q31_t)0xb1808c0c,
+  (q31_t)0x6516dacd, (q31_t)0xb17b95a0, (q31_t)0x65130000, (q31_t)0xb1769f65, (q31_t)0x650f24f5, (q31_t)0xb171a95b,
+    (q31_t)0x650b49ac, (q31_t)0xb16cb380,
+  (q31_t)0x65076e25, (q31_t)0xb167bdd7, (q31_t)0x6503925f, (q31_t)0xb162c85d, (q31_t)0x64ffb65b, (q31_t)0xb15dd315,
+    (q31_t)0x64fbda18, (q31_t)0xb158ddfd,
+  (q31_t)0x64f7fd98, (q31_t)0xb153e915, (q31_t)0x64f420d9, (q31_t)0xb14ef45e, (q31_t)0x64f043dc, (q31_t)0xb149ffd7,
+    (q31_t)0x64ec66a0, (q31_t)0xb1450b81,
+  (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x64e4ab6e, (q31_t)0xb13b2367, (q31_t)0x64e0cd78, (q31_t)0xb1362fa2,
+    (q31_t)0x64dcef44, (q31_t)0xb1313c0e,
+  (q31_t)0x64d910d1, (q31_t)0xb12c48ab, (q31_t)0x64d53220, (q31_t)0xb1275579, (q31_t)0x64d15331, (q31_t)0xb1226277,
+    (q31_t)0x64cd7404, (q31_t)0xb11d6fa6,
+  (q31_t)0x64c99498, (q31_t)0xb1187d05, (q31_t)0x64c5b4ef, (q31_t)0xb1138a95, (q31_t)0x64c1d507, (q31_t)0xb10e9856,
+    (q31_t)0x64bdf4e1, (q31_t)0xb109a648,
+  (q31_t)0x64ba147d, (q31_t)0xb104b46a, (q31_t)0x64b633da, (q31_t)0xb0ffc2bd, (q31_t)0x64b252fa, (q31_t)0xb0fad140,
+    (q31_t)0x64ae71dc, (q31_t)0xb0f5dff5,
+  (q31_t)0x64aa907f, (q31_t)0xb0f0eeda, (q31_t)0x64a6aee4, (q31_t)0xb0ebfdf0, (q31_t)0x64a2cd0c, (q31_t)0xb0e70d37,
+    (q31_t)0x649eeaf5, (q31_t)0xb0e21cae,
+  (q31_t)0x649b08a0, (q31_t)0xb0dd2c56, (q31_t)0x6497260d, (q31_t)0xb0d83c2f, (q31_t)0x6493433c, (q31_t)0xb0d34c39,
+    (q31_t)0x648f602d, (q31_t)0xb0ce5c74,
+  (q31_t)0x648b7ce0, (q31_t)0xb0c96ce0, (q31_t)0x64879955, (q31_t)0xb0c47d7c, (q31_t)0x6483b58c, (q31_t)0xb0bf8e4a,
+    (q31_t)0x647fd185, (q31_t)0xb0ba9f48,
+  (q31_t)0x647bed3f, (q31_t)0xb0b5b077, (q31_t)0x647808bc, (q31_t)0xb0b0c1d7, (q31_t)0x647423fb, (q31_t)0xb0abd368,
+    (q31_t)0x64703efc, (q31_t)0xb0a6e52a,
+  (q31_t)0x646c59bf, (q31_t)0xb0a1f71d, (q31_t)0x64687444, (q31_t)0xb09d0941, (q31_t)0x64648e8c, (q31_t)0xb0981b96,
+    (q31_t)0x6460a895, (q31_t)0xb0932e1b,
+  (q31_t)0x645cc260, (q31_t)0xb08e40d2, (q31_t)0x6458dbed, (q31_t)0xb08953ba, (q31_t)0x6454f53d, (q31_t)0xb08466d3,
+    (q31_t)0x64510e4e, (q31_t)0xb07f7a1c,
+  (q31_t)0x644d2722, (q31_t)0xb07a8d97, (q31_t)0x64493fb8, (q31_t)0xb075a143, (q31_t)0x64455810, (q31_t)0xb070b520,
+    (q31_t)0x6441702a, (q31_t)0xb06bc92e,
+  (q31_t)0x643d8806, (q31_t)0xb066dd6d, (q31_t)0x64399fa5, (q31_t)0xb061f1de, (q31_t)0x6435b706, (q31_t)0xb05d067f,
+    (q31_t)0x6431ce28, (q31_t)0xb0581b51,
+  (q31_t)0x642de50d, (q31_t)0xb0533055, (q31_t)0x6429fbb5, (q31_t)0xb04e458a, (q31_t)0x6426121e, (q31_t)0xb0495af0,
+    (q31_t)0x6422284a, (q31_t)0xb0447087,
+  (q31_t)0x641e3e38, (q31_t)0xb03f864f, (q31_t)0x641a53e8, (q31_t)0xb03a9c49, (q31_t)0x6416695a, (q31_t)0xb035b273,
+    (q31_t)0x64127e8f, (q31_t)0xb030c8cf,
+  (q31_t)0x640e9386, (q31_t)0xb02bdf5c, (q31_t)0x640aa83f, (q31_t)0xb026f61b, (q31_t)0x6406bcba, (q31_t)0xb0220d0a,
+    (q31_t)0x6402d0f8, (q31_t)0xb01d242b,
+  (q31_t)0x63fee4f8, (q31_t)0xb0183b7d, (q31_t)0x63faf8bb, (q31_t)0xb0135301, (q31_t)0x63f70c3f, (q31_t)0xb00e6ab5,
+    (q31_t)0x63f31f86, (q31_t)0xb009829c,
+  (q31_t)0x63ef3290, (q31_t)0xb0049ab3, (q31_t)0x63eb455c, (q31_t)0xafffb2fc, (q31_t)0x63e757ea, (q31_t)0xaffacb76,
+    (q31_t)0x63e36a3a, (q31_t)0xaff5e421,
+  (q31_t)0x63df7c4d, (q31_t)0xaff0fcfe, (q31_t)0x63db8e22, (q31_t)0xafec160c, (q31_t)0x63d79fba, (q31_t)0xafe72f4c,
+    (q31_t)0x63d3b114, (q31_t)0xafe248bd,
+  (q31_t)0x63cfc231, (q31_t)0xafdd625f, (q31_t)0x63cbd310, (q31_t)0xafd87c33, (q31_t)0x63c7e3b1, (q31_t)0xafd39638,
+    (q31_t)0x63c3f415, (q31_t)0xafceb06f,
+  (q31_t)0x63c0043b, (q31_t)0xafc9cad7, (q31_t)0x63bc1424, (q31_t)0xafc4e571, (q31_t)0x63b823cf, (q31_t)0xafc0003c,
+    (q31_t)0x63b4333d, (q31_t)0xafbb1b39,
+  (q31_t)0x63b0426d, (q31_t)0xafb63667, (q31_t)0x63ac5160, (q31_t)0xafb151c7, (q31_t)0x63a86015, (q31_t)0xafac6d58,
+    (q31_t)0x63a46e8d, (q31_t)0xafa7891b,
+  (q31_t)0x63a07cc7, (q31_t)0xafa2a50f, (q31_t)0x639c8ac4, (q31_t)0xaf9dc135, (q31_t)0x63989884, (q31_t)0xaf98dd8d,
+    (q31_t)0x6394a606, (q31_t)0xaf93fa16,
+  (q31_t)0x6390b34a, (q31_t)0xaf8f16d1, (q31_t)0x638cc051, (q31_t)0xaf8a33bd, (q31_t)0x6388cd1b, (q31_t)0xaf8550db,
+    (q31_t)0x6384d9a7, (q31_t)0xaf806e2b,
+  (q31_t)0x6380e5f6, (q31_t)0xaf7b8bac, (q31_t)0x637cf208, (q31_t)0xaf76a95f, (q31_t)0x6378fddc, (q31_t)0xaf71c743,
+    (q31_t)0x63750973, (q31_t)0xaf6ce55a,
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+    (q31_t)0x63653569, (q31_t)0xaf595fa4,
+  (q31_t)0x63613fcd, (q31_t)0xaf547eb3, (q31_t)0x635d49f4, (q31_t)0xaf4f9df4, (q31_t)0x635953dd, (q31_t)0xaf4abd66,
+    (q31_t)0x63555d8a, (q31_t)0xaf45dd0b,
+  (q31_t)0x635166f9, (q31_t)0xaf40fce1, (q31_t)0x634d702b, (q31_t)0xaf3c1ce9, (q31_t)0x6349791f, (q31_t)0xaf373d22,
+    (q31_t)0x634581d6, (q31_t)0xaf325d8e,
+  (q31_t)0x63418a50, (q31_t)0xaf2d7e2b, (q31_t)0x633d928d, (q31_t)0xaf289efa, (q31_t)0x63399a8d, (q31_t)0xaf23bffb,
+    (q31_t)0x6335a24f, (q31_t)0xaf1ee12e,
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+    (q31_t)0x6325bef5, (q31_t)0xaf0b67ed,
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+  (q31_t)0x6311dd64, (q31_t)0xaef314c0, (q31_t)0x630de2c3, (q31_t)0xaeee37e6, (q31_t)0x6309e7e4, (q31_t)0xaee95b3f,
+    (q31_t)0x6305ecc9, (q31_t)0xaee47ec9,
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+    (q31_t)0x6296150f, (q31_t)0xae5cb171,
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+    (q31_t)0x6205374c, (q31_t)0xadaef9e4,
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+    (q31_t)0x61e4dc62, (q31_t)0xad888229,
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+    (q31_t)0x61c47260, (q31_t)0xad621725,
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+    (q31_t)0x61b437b7, (q31_t)0xad4ee66a,
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+    (q31_t)0x61a3f94a, (q31_t)0xad3bb8df,
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+    (q31_t)0x6193b719, (q31_t)0xad288e85,
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+    (q31_t)0x61732770, (q31_t)0xad024366,
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+    (q31_t)0x6162d9f8, (q31_t)0xacef22a3,
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+    (q31_t)0x615288be, (q31_t)0xacdc0514,
+  (q31_t)0x614e73da, (q31_t)0xacd73e30, (q31_t)0x614a5eba, (q31_t)0xacd27780, (q31_t)0x6146495d, (q31_t)0xaccdb103,
+    (q31_t)0x614233c5, (q31_t)0xacc8eab9,
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+    (q31_t)0x6131db0b, (q31_t)0xacb5d394,
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+    (q31_t)0x61217e92, (q31_t)0xaca2bfa4,
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+    (q31_t)0x61111e5b, (q31_t)0xac8faeec,
+  (q31_t)0x610d05b7, (q31_t)0xac8aeb3e, (q31_t)0x6108ecd8, (q31_t)0xac8627c4, (q31_t)0x6104d3bc, (q31_t)0xac81647e,
+    (q31_t)0x6100ba65, (q31_t)0xac7ca16b,
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+    (q31_t)0x60f052b2, (q31_t)0xac699722,
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+    (q31_t)0x60dfe743, (q31_t)0xac569012,
+  (q31_t)0x60dbcbd1, (q31_t)0xac51cecf, (q31_t)0x60d7b024, (q31_t)0xac4d0dc0, (q31_t)0x60d3943b, (q31_t)0xac484ce4,
+    (q31_t)0x60cf7817, (q31_t)0xac438c3c,
+  (q31_t)0x60cb5bb7, (q31_t)0xac3ecbc7, (q31_t)0x60c73f1b, (q31_t)0xac3a0b87, (q31_t)0x60c32243, (q31_t)0xac354b7a,
+    (q31_t)0x60bf0530, (q31_t)0xac308ba0,
+  (q31_t)0x60bae7e1, (q31_t)0xac2bcbfa, (q31_t)0x60b6ca56, (q31_t)0xac270c88, (q31_t)0x60b2ac8f, (q31_t)0xac224d4a,
+    (q31_t)0x60ae8e8d, (q31_t)0xac1d8e40,
+  (q31_t)0x60aa7050, (q31_t)0xac18cf69, (q31_t)0x60a651d7, (q31_t)0xac1410c6, (q31_t)0x60a23322, (q31_t)0xac0f5256,
+    (q31_t)0x609e1431, (q31_t)0xac0a941b,
+  (q31_t)0x6099f505, (q31_t)0xac05d613, (q31_t)0x6095d59d, (q31_t)0xac01183f, (q31_t)0x6091b5fa, (q31_t)0xabfc5a9f,
+    (q31_t)0x608d961b, (q31_t)0xabf79d33,
+  (q31_t)0x60897601, (q31_t)0xabf2dffb, (q31_t)0x608555ab, (q31_t)0xabee22f6, (q31_t)0x60813519, (q31_t)0xabe96625,
+    (q31_t)0x607d144c, (q31_t)0xabe4a988,
+  (q31_t)0x6078f344, (q31_t)0xabdfed1f, (q31_t)0x6074d200, (q31_t)0xabdb30ea, (q31_t)0x6070b080, (q31_t)0xabd674e9,
+    (q31_t)0x606c8ec5, (q31_t)0xabd1b91c,
+  (q31_t)0x60686ccf, (q31_t)0xabccfd83, (q31_t)0x60644a9d, (q31_t)0xabc8421d, (q31_t)0x6060282f, (q31_t)0xabc386ec,
+    (q31_t)0x605c0587, (q31_t)0xabbecbee,
+  (q31_t)0x6057e2a2, (q31_t)0xabba1125, (q31_t)0x6053bf82, (q31_t)0xabb5568f, (q31_t)0x604f9c27, (q31_t)0xabb09c2e,
+    (q31_t)0x604b7891, (q31_t)0xababe200,
+  (q31_t)0x604754bf, (q31_t)0xaba72807, (q31_t)0x604330b1, (q31_t)0xaba26e41, (q31_t)0x603f0c69, (q31_t)0xab9db4b0,
+    (q31_t)0x603ae7e5, (q31_t)0xab98fb52,
+  (q31_t)0x6036c325, (q31_t)0xab944229, (q31_t)0x60329e2a, (q31_t)0xab8f8934, (q31_t)0x602e78f4, (q31_t)0xab8ad073,
+    (q31_t)0x602a5383, (q31_t)0xab8617e6,
+  (q31_t)0x60262dd6, (q31_t)0xab815f8d, (q31_t)0x602207ee, (q31_t)0xab7ca768, (q31_t)0x601de1ca, (q31_t)0xab77ef77,
+    (q31_t)0x6019bb6b, (q31_t)0xab7337bb,
+  (q31_t)0x601594d1, (q31_t)0xab6e8032, (q31_t)0x60116dfc, (q31_t)0xab69c8de, (q31_t)0x600d46ec, (q31_t)0xab6511be,
+    (q31_t)0x60091fa0, (q31_t)0xab605ad2,
+  (q31_t)0x6004f819, (q31_t)0xab5ba41a, (q31_t)0x6000d057, (q31_t)0xab56ed97, (q31_t)0x5ffca859, (q31_t)0xab523748,
+    (q31_t)0x5ff88021, (q31_t)0xab4d812d,
+  (q31_t)0x5ff457ad, (q31_t)0xab48cb46, (q31_t)0x5ff02efe, (q31_t)0xab441593, (q31_t)0x5fec0613, (q31_t)0xab3f6015,
+    (q31_t)0x5fe7dcee, (q31_t)0xab3aaacb,
+  (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, (q31_t)0x5fdf89f2, (q31_t)0xab3140d4, (q31_t)0x5fdb601b, (q31_t)0xab2c8c27,
+    (q31_t)0x5fd73609, (q31_t)0xab27d7ae,
+  (q31_t)0x5fd30bbc, (q31_t)0xab23236a, (q31_t)0x5fcee133, (q31_t)0xab1e6f5a, (q31_t)0x5fcab670, (q31_t)0xab19bb7e,
+    (q31_t)0x5fc68b72, (q31_t)0xab1507d7,
+  (q31_t)0x5fc26038, (q31_t)0xab105464, (q31_t)0x5fbe34c4, (q31_t)0xab0ba125, (q31_t)0x5fba0914, (q31_t)0xab06ee1b,
+    (q31_t)0x5fb5dd29, (q31_t)0xab023b46,
+  (q31_t)0x5fb1b104, (q31_t)0xaafd88a4, (q31_t)0x5fad84a3, (q31_t)0xaaf8d637, (q31_t)0x5fa95807, (q31_t)0xaaf423ff,
+    (q31_t)0x5fa52b31, (q31_t)0xaaef71fb,
+  (q31_t)0x5fa0fe1f, (q31_t)0xaaeac02c, (q31_t)0x5f9cd0d2, (q31_t)0xaae60e91, (q31_t)0x5f98a34a, (q31_t)0xaae15d2a,
+    (q31_t)0x5f947588, (q31_t)0xaadcabf8,
+  (q31_t)0x5f90478a, (q31_t)0xaad7fafb, (q31_t)0x5f8c1951, (q31_t)0xaad34a32, (q31_t)0x5f87eade, (q31_t)0xaace999d,
+    (q31_t)0x5f83bc2f, (q31_t)0xaac9e93e,
+  (q31_t)0x5f7f8d46, (q31_t)0xaac53912, (q31_t)0x5f7b5e22, (q31_t)0xaac0891c, (q31_t)0x5f772ec2, (q31_t)0xaabbd959,
+    (q31_t)0x5f72ff28, (q31_t)0xaab729cc,
+  (q31_t)0x5f6ecf53, (q31_t)0xaab27a73, (q31_t)0x5f6a9f44, (q31_t)0xaaadcb4f, (q31_t)0x5f666ef9, (q31_t)0xaaa91c5f,
+    (q31_t)0x5f623e73, (q31_t)0xaaa46da4,
+  (q31_t)0x5f5e0db3, (q31_t)0xaa9fbf1e, (q31_t)0x5f59dcb8, (q31_t)0xaa9b10cc, (q31_t)0x5f55ab82, (q31_t)0xaa9662af,
+    (q31_t)0x5f517a11, (q31_t)0xaa91b4c7,
+  (q31_t)0x5f4d4865, (q31_t)0xaa8d0713, (q31_t)0x5f49167f, (q31_t)0xaa885994, (q31_t)0x5f44e45e, (q31_t)0xaa83ac4a,
+    (q31_t)0x5f40b202, (q31_t)0xaa7eff34,
+  (q31_t)0x5f3c7f6b, (q31_t)0xaa7a5253, (q31_t)0x5f384c9a, (q31_t)0xaa75a5a8, (q31_t)0x5f34198e, (q31_t)0xaa70f930,
+    (q31_t)0x5f2fe647, (q31_t)0xaa6c4cee,
+  (q31_t)0x5f2bb2c5, (q31_t)0xaa67a0e0, (q31_t)0x5f277f09, (q31_t)0xaa62f507, (q31_t)0x5f234b12, (q31_t)0xaa5e4963,
+    (q31_t)0x5f1f16e0, (q31_t)0xaa599df4,
+  (q31_t)0x5f1ae274, (q31_t)0xaa54f2ba, (q31_t)0x5f16adcc, (q31_t)0xaa5047b4, (q31_t)0x5f1278eb, (q31_t)0xaa4b9ce3,
+    (q31_t)0x5f0e43ce, (q31_t)0xaa46f248,
+  (q31_t)0x5f0a0e77, (q31_t)0xaa4247e1, (q31_t)0x5f05d8e6, (q31_t)0xaa3d9daf, (q31_t)0x5f01a31a, (q31_t)0xaa38f3b1,
+    (q31_t)0x5efd6d13, (q31_t)0xaa3449e9,
+  (q31_t)0x5ef936d1, (q31_t)0xaa2fa056, (q31_t)0x5ef50055, (q31_t)0xaa2af6f7, (q31_t)0x5ef0c99f, (q31_t)0xaa264dce,
+    (q31_t)0x5eec92ae, (q31_t)0xaa21a4d9,
+  (q31_t)0x5ee85b82, (q31_t)0xaa1cfc1a, (q31_t)0x5ee4241c, (q31_t)0xaa18538f, (q31_t)0x5edfec7b, (q31_t)0xaa13ab3a,
+    (q31_t)0x5edbb49f, (q31_t)0xaa0f0319,
+  (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5ed34439, (q31_t)0xaa05b377, (q31_t)0x5ecf0baf, (q31_t)0xaa010bf6,
+    (q31_t)0x5ecad2e9, (q31_t)0xa9fc64a9,
+  (q31_t)0x5ec699e9, (q31_t)0xa9f7bd92, (q31_t)0x5ec260af, (q31_t)0xa9f316b0, (q31_t)0x5ebe273b, (q31_t)0xa9ee7002,
+    (q31_t)0x5eb9ed8b, (q31_t)0xa9e9c98a,
+  (q31_t)0x5eb5b3a2, (q31_t)0xa9e52347, (q31_t)0x5eb1797e, (q31_t)0xa9e07d39, (q31_t)0x5ead3f1f, (q31_t)0xa9dbd761,
+    (q31_t)0x5ea90487, (q31_t)0xa9d731bd,
+  (q31_t)0x5ea4c9b3, (q31_t)0xa9d28c4e, (q31_t)0x5ea08ea6, (q31_t)0xa9cde715, (q31_t)0x5e9c535e, (q31_t)0xa9c94211,
+    (q31_t)0x5e9817dc, (q31_t)0xa9c49d42,
+  (q31_t)0x5e93dc1f, (q31_t)0xa9bff8a8, (q31_t)0x5e8fa028, (q31_t)0xa9bb5444, (q31_t)0x5e8b63f7, (q31_t)0xa9b6b014,
+    (q31_t)0x5e87278b, (q31_t)0xa9b20c1a,
+  (q31_t)0x5e82eae5, (q31_t)0xa9ad6855, (q31_t)0x5e7eae05, (q31_t)0xa9a8c4c5, (q31_t)0x5e7a70ea, (q31_t)0xa9a4216b,
+    (q31_t)0x5e763395, (q31_t)0xa99f7e46,
+  (q31_t)0x5e71f606, (q31_t)0xa99adb56, (q31_t)0x5e6db83d, (q31_t)0xa996389b, (q31_t)0x5e697a39, (q31_t)0xa9919616,
+    (q31_t)0x5e653bfc, (q31_t)0xa98cf3c6,
+  (q31_t)0x5e60fd84, (q31_t)0xa98851ac, (q31_t)0x5e5cbed1, (q31_t)0xa983afc6, (q31_t)0x5e587fe5, (q31_t)0xa97f0e16,
+    (q31_t)0x5e5440be, (q31_t)0xa97a6c9c,
+  (q31_t)0x5e50015d, (q31_t)0xa975cb57, (q31_t)0x5e4bc1c2, (q31_t)0xa9712a47, (q31_t)0x5e4781ed, (q31_t)0xa96c896c,
+    (q31_t)0x5e4341de, (q31_t)0xa967e8c7,
+  (q31_t)0x5e3f0194, (q31_t)0xa9634858, (q31_t)0x5e3ac110, (q31_t)0xa95ea81d, (q31_t)0x5e368053, (q31_t)0xa95a0819,
+    (q31_t)0x5e323f5b, (q31_t)0xa9556849,
+  (q31_t)0x5e2dfe29, (q31_t)0xa950c8b0, (q31_t)0x5e29bcbd, (q31_t)0xa94c294b, (q31_t)0x5e257b17, (q31_t)0xa9478a1c,
+    (q31_t)0x5e213936, (q31_t)0xa942eb23,
+  (q31_t)0x5e1cf71c, (q31_t)0xa93e4c5f, (q31_t)0x5e18b4c8, (q31_t)0xa939add1, (q31_t)0x5e147239, (q31_t)0xa9350f78,
+    (q31_t)0x5e102f71, (q31_t)0xa9307155,
+  (q31_t)0x5e0bec6e, (q31_t)0xa92bd367, (q31_t)0x5e07a932, (q31_t)0xa92735af, (q31_t)0x5e0365bb, (q31_t)0xa922982c,
+    (q31_t)0x5dff220b, (q31_t)0xa91dfadf,
+  (q31_t)0x5dfade20, (q31_t)0xa9195dc7, (q31_t)0x5df699fc, (q31_t)0xa914c0e6, (q31_t)0x5df2559e, (q31_t)0xa9102439,
+    (q31_t)0x5dee1105, (q31_t)0xa90b87c3,
+  (q31_t)0x5de9cc33, (q31_t)0xa906eb82, (q31_t)0x5de58727, (q31_t)0xa9024f76, (q31_t)0x5de141e1, (q31_t)0xa8fdb3a1,
+    (q31_t)0x5ddcfc61, (q31_t)0xa8f91801,
+  (q31_t)0x5dd8b6a7, (q31_t)0xa8f47c97, (q31_t)0x5dd470b3, (q31_t)0xa8efe162, (q31_t)0x5dd02a85, (q31_t)0xa8eb4663,
+    (q31_t)0x5dcbe41d, (q31_t)0xa8e6ab9a,
+  (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5dc356a1, (q31_t)0xa8dd76a9, (q31_t)0x5dbf0f8c, (q31_t)0xa8d8dc81,
+    (q31_t)0x5dbac83d, (q31_t)0xa8d4428f,
+  (q31_t)0x5db680b4, (q31_t)0xa8cfa8d2, (q31_t)0x5db238f1, (q31_t)0xa8cb0f4b, (q31_t)0x5dadf0f5, (q31_t)0xa8c675fb,
+    (q31_t)0x5da9a8bf, (q31_t)0xa8c1dce0,
+  (q31_t)0x5da5604f, (q31_t)0xa8bd43fa, (q31_t)0x5da117a5, (q31_t)0xa8b8ab4b, (q31_t)0x5d9ccec2, (q31_t)0xa8b412d1,
+    (q31_t)0x5d9885a5, (q31_t)0xa8af7a8e,
+  (q31_t)0x5d943c4e, (q31_t)0xa8aae280, (q31_t)0x5d8ff2bd, (q31_t)0xa8a64aa8, (q31_t)0x5d8ba8f3, (q31_t)0xa8a1b306,
+    (q31_t)0x5d875eef, (q31_t)0xa89d1b99,
+  (q31_t)0x5d8314b1, (q31_t)0xa8988463, (q31_t)0x5d7eca39, (q31_t)0xa893ed63, (q31_t)0x5d7a7f88, (q31_t)0xa88f5698,
+    (q31_t)0x5d76349d, (q31_t)0xa88ac004,
+  (q31_t)0x5d71e979, (q31_t)0xa88629a5, (q31_t)0x5d6d9e1b, (q31_t)0xa881937c, (q31_t)0x5d695283, (q31_t)0xa87cfd8a,
+    (q31_t)0x5d6506b2, (q31_t)0xa87867cd,
+  (q31_t)0x5d60baa7, (q31_t)0xa873d246, (q31_t)0x5d5c6e62, (q31_t)0xa86f3cf6, (q31_t)0x5d5821e4, (q31_t)0xa86aa7db,
+    (q31_t)0x5d53d52d, (q31_t)0xa86612f6,
+  (q31_t)0x5d4f883b, (q31_t)0xa8617e48, (q31_t)0x5d4b3b10, (q31_t)0xa85ce9cf, (q31_t)0x5d46edac, (q31_t)0xa858558d,
+    (q31_t)0x5d42a00e, (q31_t)0xa853c180,
+  (q31_t)0x5d3e5237, (q31_t)0xa84f2daa, (q31_t)0x5d3a0426, (q31_t)0xa84a9a0a, (q31_t)0x5d35b5db, (q31_t)0xa84606a0,
+    (q31_t)0x5d316757, (q31_t)0xa841736c,
+  (q31_t)0x5d2d189a, (q31_t)0xa83ce06e, (q31_t)0x5d28c9a3, (q31_t)0xa8384da6, (q31_t)0x5d247a72, (q31_t)0xa833bb14,
+    (q31_t)0x5d202b09, (q31_t)0xa82f28b9,
+  (q31_t)0x5d1bdb65, (q31_t)0xa82a9693, (q31_t)0x5d178b89, (q31_t)0xa82604a4, (q31_t)0x5d133b72, (q31_t)0xa82172eb,
+    (q31_t)0x5d0eeb23, (q31_t)0xa81ce169,
+  (q31_t)0x5d0a9a9a, (q31_t)0xa818501c, (q31_t)0x5d0649d7, (q31_t)0xa813bf06, (q31_t)0x5d01f8dc, (q31_t)0xa80f2e26,
+    (q31_t)0x5cfda7a7, (q31_t)0xa80a9d7c,
+  (q31_t)0x5cf95638, (q31_t)0xa8060d08, (q31_t)0x5cf50490, (q31_t)0xa8017ccb, (q31_t)0x5cf0b2af, (q31_t)0xa7fcecc4,
+    (q31_t)0x5cec6095, (q31_t)0xa7f85cf3,
+  (q31_t)0x5ce80e41, (q31_t)0xa7f3cd59, (q31_t)0x5ce3bbb4, (q31_t)0xa7ef3df5, (q31_t)0x5cdf68ed, (q31_t)0xa7eaaec7,
+    (q31_t)0x5cdb15ed, (q31_t)0xa7e61fd0,
+  (q31_t)0x5cd6c2b5, (q31_t)0xa7e1910f, (q31_t)0x5cd26f42, (q31_t)0xa7dd0284, (q31_t)0x5cce1b97, (q31_t)0xa7d8742f,
+    (q31_t)0x5cc9c7b2, (q31_t)0xa7d3e611,
+  (q31_t)0x5cc57394, (q31_t)0xa7cf582a, (q31_t)0x5cc11f3d, (q31_t)0xa7caca79, (q31_t)0x5cbccaac, (q31_t)0xa7c63cfe,
+    (q31_t)0x5cb875e3, (q31_t)0xa7c1afb9,
+  (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5cafcba4, (q31_t)0xa7b895d4, (q31_t)0x5cab762f, (q31_t)0xa7b40933,
+    (q31_t)0x5ca72080, (q31_t)0xa7af7cc8,
+  (q31_t)0x5ca2ca99, (q31_t)0xa7aaf094, (q31_t)0x5c9e7478, (q31_t)0xa7a66497, (q31_t)0x5c9a1e1e, (q31_t)0xa7a1d8d0,
+    (q31_t)0x5c95c78b, (q31_t)0xa79d4d3f,
+  (q31_t)0x5c9170bf, (q31_t)0xa798c1e5, (q31_t)0x5c8d19ba, (q31_t)0xa79436c1, (q31_t)0x5c88c27c, (q31_t)0xa78fabd4,
+    (q31_t)0x5c846b05, (q31_t)0xa78b211e,
+  (q31_t)0x5c801354, (q31_t)0xa786969e, (q31_t)0x5c7bbb6b, (q31_t)0xa7820c55, (q31_t)0x5c776348, (q31_t)0xa77d8242,
+    (q31_t)0x5c730aed, (q31_t)0xa778f866,
+  (q31_t)0x5c6eb258, (q31_t)0xa7746ec0, (q31_t)0x5c6a598b, (q31_t)0xa76fe551, (q31_t)0x5c660084, (q31_t)0xa76b5c19,
+    (q31_t)0x5c61a745, (q31_t)0xa766d317,
+  (q31_t)0x5c5d4dcc, (q31_t)0xa7624a4d, (q31_t)0x5c58f41a, (q31_t)0xa75dc1b8, (q31_t)0x5c549a30, (q31_t)0xa759395b,
+    (q31_t)0x5c50400d, (q31_t)0xa754b134,
+  (q31_t)0x5c4be5b0, (q31_t)0xa7502943, (q31_t)0x5c478b1b, (q31_t)0xa74ba18a, (q31_t)0x5c43304d, (q31_t)0xa7471a07,
+    (q31_t)0x5c3ed545, (q31_t)0xa74292bb,
+  (q31_t)0x5c3a7a05, (q31_t)0xa73e0ba5, (q31_t)0x5c361e8c, (q31_t)0xa73984c7, (q31_t)0x5c31c2db, (q31_t)0xa734fe1f,
+    (q31_t)0x5c2d66f0, (q31_t)0xa73077ae,
+  (q31_t)0x5c290acc, (q31_t)0xa72bf174, (q31_t)0x5c24ae70, (q31_t)0xa7276b70, (q31_t)0x5c2051db, (q31_t)0xa722e5a3,
+    (q31_t)0x5c1bf50d, (q31_t)0xa71e600d,
+  (q31_t)0x5c179806, (q31_t)0xa719daae, (q31_t)0x5c133ac6, (q31_t)0xa7155586, (q31_t)0x5c0edd4e, (q31_t)0xa710d095,
+    (q31_t)0x5c0a7f9c, (q31_t)0xa70c4bda,
+  (q31_t)0x5c0621b2, (q31_t)0xa707c757, (q31_t)0x5c01c38f, (q31_t)0xa703430a, (q31_t)0x5bfd6534, (q31_t)0xa6febef4,
+    (q31_t)0x5bf906a0, (q31_t)0xa6fa3b15,
+  (q31_t)0x5bf4a7d2, (q31_t)0xa6f5b76d, (q31_t)0x5bf048cd, (q31_t)0xa6f133fc, (q31_t)0x5bebe98e, (q31_t)0xa6ecb0c2,
+    (q31_t)0x5be78a17, (q31_t)0xa6e82dbe,
+  (q31_t)0x5be32a67, (q31_t)0xa6e3aaf2, (q31_t)0x5bdeca7f, (q31_t)0xa6df285d, (q31_t)0x5bda6a5d, (q31_t)0xa6daa5fe,
+    (q31_t)0x5bd60a03, (q31_t)0xa6d623d7,
+  (q31_t)0x5bd1a971, (q31_t)0xa6d1a1e7, (q31_t)0x5bcd48a6, (q31_t)0xa6cd202d, (q31_t)0x5bc8e7a2, (q31_t)0xa6c89eab,
+    (q31_t)0x5bc48666, (q31_t)0xa6c41d60,
+  (q31_t)0x5bc024f0, (q31_t)0xa6bf9c4b, (q31_t)0x5bbbc343, (q31_t)0xa6bb1b6e, (q31_t)0x5bb7615d, (q31_t)0xa6b69ac8,
+    (q31_t)0x5bb2ff3e, (q31_t)0xa6b21a59,
+  (q31_t)0x5bae9ce7, (q31_t)0xa6ad9a21, (q31_t)0x5baa3a57, (q31_t)0xa6a91a20, (q31_t)0x5ba5d78e, (q31_t)0xa6a49a56,
+    (q31_t)0x5ba1748d, (q31_t)0xa6a01ac4,
+  (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, (q31_t)0x5b98ade2, (q31_t)0xa6971c44, (q31_t)0x5b944a37, (q31_t)0xa6929d57,
+    (q31_t)0x5b8fe654, (q31_t)0xa68e1ea1,
+  (q31_t)0x5b8b8239, (q31_t)0xa689a022, (q31_t)0x5b871de5, (q31_t)0xa68521da, (q31_t)0x5b82b958, (q31_t)0xa680a3ca,
+    (q31_t)0x5b7e5493, (q31_t)0xa67c25f0,
+  (q31_t)0x5b79ef96, (q31_t)0xa677a84e, (q31_t)0x5b758a60, (q31_t)0xa6732ae3, (q31_t)0x5b7124f2, (q31_t)0xa66eadb0,
+    (q31_t)0x5b6cbf4c, (q31_t)0xa66a30b3,
+  (q31_t)0x5b68596d, (q31_t)0xa665b3ee, (q31_t)0x5b63f355, (q31_t)0xa6613760, (q31_t)0x5b5f8d06, (q31_t)0xa65cbb0a,
+    (q31_t)0x5b5b267e, (q31_t)0xa6583eeb,
+  (q31_t)0x5b56bfbd, (q31_t)0xa653c303, (q31_t)0x5b5258c4, (q31_t)0xa64f4752, (q31_t)0x5b4df193, (q31_t)0xa64acbd9,
+    (q31_t)0x5b498a2a, (q31_t)0xa6465097,
+  (q31_t)0x5b452288, (q31_t)0xa641d58c, (q31_t)0x5b40baae, (q31_t)0xa63d5ab9, (q31_t)0x5b3c529c, (q31_t)0xa638e01d,
+    (q31_t)0x5b37ea51, (q31_t)0xa63465b9,
+  (q31_t)0x5b3381ce, (q31_t)0xa62feb8b, (q31_t)0x5b2f1913, (q31_t)0xa62b7196, (q31_t)0x5b2ab020, (q31_t)0xa626f7d7,
+    (q31_t)0x5b2646f4, (q31_t)0xa6227e50,
+  (q31_t)0x5b21dd90, (q31_t)0xa61e0501, (q31_t)0x5b1d73f4, (q31_t)0xa6198be9, (q31_t)0x5b190a20, (q31_t)0xa6151308,
+    (q31_t)0x5b14a014, (q31_t)0xa6109a5f,
+  (q31_t)0x5b1035cf, (q31_t)0xa60c21ee, (q31_t)0x5b0bcb52, (q31_t)0xa607a9b4, (q31_t)0x5b07609d, (q31_t)0xa60331b1,
+    (q31_t)0x5b02f5b0, (q31_t)0xa5feb9e6,
+  (q31_t)0x5afe8a8b, (q31_t)0xa5fa4252, (q31_t)0x5afa1f2e, (q31_t)0xa5f5caf6, (q31_t)0x5af5b398, (q31_t)0xa5f153d2,
+    (q31_t)0x5af147ca, (q31_t)0xa5ecdce5,
+  (q31_t)0x5aecdbc5, (q31_t)0xa5e8662f, (q31_t)0x5ae86f87, (q31_t)0xa5e3efb1, (q31_t)0x5ae40311, (q31_t)0xa5df796b,
+    (q31_t)0x5adf9663, (q31_t)0xa5db035c,
+  (q31_t)0x5adb297d, (q31_t)0xa5d68d85, (q31_t)0x5ad6bc5f, (q31_t)0xa5d217e6, (q31_t)0x5ad24f09, (q31_t)0xa5cda27e,
+    (q31_t)0x5acde17b, (q31_t)0xa5c92d4e,
+  (q31_t)0x5ac973b5, (q31_t)0xa5c4b855, (q31_t)0x5ac505b7, (q31_t)0xa5c04395, (q31_t)0x5ac09781, (q31_t)0xa5bbcf0b,
+    (q31_t)0x5abc2912, (q31_t)0xa5b75aba,
+  (q31_t)0x5ab7ba6c, (q31_t)0xa5b2e6a0, (q31_t)0x5ab34b8e, (q31_t)0xa5ae72be, (q31_t)0x5aaedc78, (q31_t)0xa5a9ff14,
+    (q31_t)0x5aaa6d2b, (q31_t)0xa5a58ba1,
+  (q31_t)0x5aa5fda5, (q31_t)0xa5a11866, (q31_t)0x5aa18de7, (q31_t)0xa59ca563, (q31_t)0x5a9d1df1, (q31_t)0xa5983297,
+    (q31_t)0x5a98adc4, (q31_t)0xa593c004,
+  (q31_t)0x5a943d5e, (q31_t)0xa58f4da8, (q31_t)0x5a8fccc1, (q31_t)0xa58adb84, (q31_t)0x5a8b5bec, (q31_t)0xa5866997,
+    (q31_t)0x5a86eadf, (q31_t)0xa581f7e3,
+  (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x5a7e081d, (q31_t)0xa5791521, (q31_t)0x5a799669, (q31_t)0xa574a414,
+    (q31_t)0x5a75247c, (q31_t)0xa570333f,
+  (q31_t)0x5a70b258, (q31_t)0xa56bc2a2, (q31_t)0x5a6c3ffc, (q31_t)0xa567523c, (q31_t)0x5a67cd69, (q31_t)0xa562e20f,
+    (q31_t)0x5a635a9d, (q31_t)0xa55e7219,
+  (q31_t)0x5a5ee79a, (q31_t)0xa55a025b, (q31_t)0x5a5a745f, (q31_t)0xa55592d5, (q31_t)0x5a5600ec, (q31_t)0xa5512388,
+    (q31_t)0x5a518d42, (q31_t)0xa54cb472,
+  (q31_t)0x5a4d1960, (q31_t)0xa5484594, (q31_t)0x5a48a546, (q31_t)0xa543d6ee, (q31_t)0x5a4430f5, (q31_t)0xa53f687f,
+    (q31_t)0x5a3fbc6b, (q31_t)0xa53afa49,
+  (q31_t)0x5a3b47ab, (q31_t)0xa5368c4b, (q31_t)0x5a36d2b2, (q31_t)0xa5321e85, (q31_t)0x5a325d82, (q31_t)0xa52db0f7,
+    (q31_t)0x5a2de81a, (q31_t)0xa52943a1,
+  (q31_t)0x5a29727b, (q31_t)0xa524d683, (q31_t)0x5a24fca4, (q31_t)0xa520699d, (q31_t)0x5a208695, (q31_t)0xa51bfcef,
+    (q31_t)0x5a1c104f, (q31_t)0xa5179079,
+  (q31_t)0x5a1799d1, (q31_t)0xa513243b, (q31_t)0x5a13231b, (q31_t)0xa50eb836, (q31_t)0x5a0eac2e, (q31_t)0xa50a4c68,
+    (q31_t)0x5a0a350a, (q31_t)0xa505e0d2,
+  (q31_t)0x5a05bdae, (q31_t)0xa5017575, (q31_t)0x5a01461a, (q31_t)0xa4fd0a50, (q31_t)0x59fcce4f, (q31_t)0xa4f89f63,
+    (q31_t)0x59f8564c, (q31_t)0xa4f434ae,
+  (q31_t)0x59f3de12, (q31_t)0xa4efca31, (q31_t)0x59ef65a1, (q31_t)0xa4eb5fec, (q31_t)0x59eaecf8, (q31_t)0xa4e6f5e0,
+    (q31_t)0x59e67417, (q31_t)0xa4e28c0c,
+  (q31_t)0x59e1faff, (q31_t)0xa4de2270, (q31_t)0x59dd81b0, (q31_t)0xa4d9b90c, (q31_t)0x59d90829, (q31_t)0xa4d54fe0,
+    (q31_t)0x59d48e6a, (q31_t)0xa4d0e6ed,
+  (q31_t)0x59d01475, (q31_t)0xa4cc7e32, (q31_t)0x59cb9a47, (q31_t)0xa4c815af, (q31_t)0x59c71fe3, (q31_t)0xa4c3ad64,
+    (q31_t)0x59c2a547, (q31_t)0xa4bf4552,
+  (q31_t)0x59be2a74, (q31_t)0xa4badd78, (q31_t)0x59b9af69, (q31_t)0xa4b675d6, (q31_t)0x59b53427, (q31_t)0xa4b20e6d,
+    (q31_t)0x59b0b8ae, (q31_t)0xa4ada73c,
+  (q31_t)0x59ac3cfd, (q31_t)0xa4a94043, (q31_t)0x59a7c115, (q31_t)0xa4a4d982, (q31_t)0x59a344f6, (q31_t)0xa4a072fa,
+    (q31_t)0x599ec8a0, (q31_t)0xa49c0cab,
+  (q31_t)0x599a4c12, (q31_t)0xa497a693, (q31_t)0x5995cf4d, (q31_t)0xa49340b4, (q31_t)0x59915250, (q31_t)0xa48edb0e,
+    (q31_t)0x598cd51d, (q31_t)0xa48a75a0,
+  (q31_t)0x598857b2, (q31_t)0xa486106a, (q31_t)0x5983da10, (q31_t)0xa481ab6d, (q31_t)0x597f5c36, (q31_t)0xa47d46a8,
+    (q31_t)0x597ade26, (q31_t)0xa478e21b,
+  (q31_t)0x59765fde, (q31_t)0xa4747dc7, (q31_t)0x5971e15f, (q31_t)0xa47019ac, (q31_t)0x596d62a9, (q31_t)0xa46bb5c9,
+    (q31_t)0x5968e3bc, (q31_t)0xa467521e,
+  (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x595fe53c, (q31_t)0xa45e8b73, (q31_t)0x595b65aa, (q31_t)0xa45a2872,
+    (q31_t)0x5956e5e0, (q31_t)0xa455c5a9,
+  (q31_t)0x595265df, (q31_t)0xa4516319, (q31_t)0x594de5a7, (q31_t)0xa44d00c2, (q31_t)0x59496538, (q31_t)0xa4489ea3,
+    (q31_t)0x5944e492, (q31_t)0xa4443cbd,
+  (q31_t)0x594063b5, (q31_t)0xa43fdb10, (q31_t)0x593be2a0, (q31_t)0xa43b799a, (q31_t)0x59376155, (q31_t)0xa437185e,
+    (q31_t)0x5932dfd3, (q31_t)0xa432b75a,
+  (q31_t)0x592e5e19, (q31_t)0xa42e568f, (q31_t)0x5929dc29, (q31_t)0xa429f5fd, (q31_t)0x59255a02, (q31_t)0xa42595a3,
+    (q31_t)0x5920d7a3, (q31_t)0xa4213581,
+  (q31_t)0x591c550e, (q31_t)0xa41cd599, (q31_t)0x5917d242, (q31_t)0xa41875e9, (q31_t)0x59134f3e, (q31_t)0xa4141672,
+    (q31_t)0x590ecc04, (q31_t)0xa40fb733,
+  (q31_t)0x590a4893, (q31_t)0xa40b582e, (q31_t)0x5905c4eb, (q31_t)0xa406f960, (q31_t)0x5901410c, (q31_t)0xa4029acc,
+    (q31_t)0x58fcbcf6, (q31_t)0xa3fe3c71,
+  (q31_t)0x58f838a9, (q31_t)0xa3f9de4e, (q31_t)0x58f3b426, (q31_t)0xa3f58064, (q31_t)0x58ef2f6b, (q31_t)0xa3f122b2,
+    (q31_t)0x58eaaa7a, (q31_t)0xa3ecc53a,
+  (q31_t)0x58e62552, (q31_t)0xa3e867fa, (q31_t)0x58e19ff3, (q31_t)0xa3e40af3, (q31_t)0x58dd1a5d, (q31_t)0xa3dfae25,
+    (q31_t)0x58d89490, (q31_t)0xa3db5190,
+  (q31_t)0x58d40e8c, (q31_t)0xa3d6f534, (q31_t)0x58cf8852, (q31_t)0xa3d29910, (q31_t)0x58cb01e1, (q31_t)0xa3ce3d25,
+    (q31_t)0x58c67b39, (q31_t)0xa3c9e174,
+  (q31_t)0x58c1f45b, (q31_t)0xa3c585fb, (q31_t)0x58bd6d45, (q31_t)0xa3c12abb, (q31_t)0x58b8e5f9, (q31_t)0xa3bccfb3,
+    (q31_t)0x58b45e76, (q31_t)0xa3b874e5,
+  (q31_t)0x58afd6bd, (q31_t)0xa3b41a50, (q31_t)0x58ab4ecc, (q31_t)0xa3afbff3, (q31_t)0x58a6c6a5, (q31_t)0xa3ab65d0,
+    (q31_t)0x58a23e48, (q31_t)0xa3a70be6,
+  (q31_t)0x589db5b3, (q31_t)0xa3a2b234, (q31_t)0x58992ce9, (q31_t)0xa39e58bb, (q31_t)0x5894a3e7, (q31_t)0xa399ff7c,
+    (q31_t)0x58901aaf, (q31_t)0xa395a675,
+  (q31_t)0x588b9140, (q31_t)0xa3914da8, (q31_t)0x5887079a, (q31_t)0xa38cf513, (q31_t)0x58827dbe, (q31_t)0xa3889cb8,
+    (q31_t)0x587df3ab, (q31_t)0xa3844495,
+  (q31_t)0x58796962, (q31_t)0xa37fecac, (q31_t)0x5874dee2, (q31_t)0xa37b94fb, (q31_t)0x5870542c, (q31_t)0xa3773d84,
+    (q31_t)0x586bc93f, (q31_t)0xa372e646,
+  (q31_t)0x58673e1b, (q31_t)0xa36e8f41, (q31_t)0x5862b2c1, (q31_t)0xa36a3875, (q31_t)0x585e2730, (q31_t)0xa365e1e2,
+    (q31_t)0x58599b69, (q31_t)0xa3618b88,
+  (q31_t)0x58550f6c, (q31_t)0xa35d3567, (q31_t)0x58508338, (q31_t)0xa358df80, (q31_t)0x584bf6cd, (q31_t)0xa35489d1,
+    (q31_t)0x58476a2c, (q31_t)0xa350345c,
+  (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x583e5047, (q31_t)0xa3478a1d, (q31_t)0x5839c302, (q31_t)0xa3433554,
+    (q31_t)0x58353587, (q31_t)0xa33ee0c3,
+  (q31_t)0x5830a7d6, (q31_t)0xa33a8c6c, (q31_t)0x582c19ef, (q31_t)0xa336384e, (q31_t)0x58278bd1, (q31_t)0xa331e469,
+    (q31_t)0x5822fd7c, (q31_t)0xa32d90be,
+  (q31_t)0x581e6ef1, (q31_t)0xa3293d4b, (q31_t)0x5819e030, (q31_t)0xa324ea13, (q31_t)0x58155139, (q31_t)0xa3209713,
+    (q31_t)0x5810c20b, (q31_t)0xa31c444c,
+  (q31_t)0x580c32a7, (q31_t)0xa317f1bf, (q31_t)0x5807a30d, (q31_t)0xa3139f6b, (q31_t)0x5803133c, (q31_t)0xa30f4d51,
+    (q31_t)0x57fe8335, (q31_t)0xa30afb70,
+  (q31_t)0x57f9f2f8, (q31_t)0xa306a9c8, (q31_t)0x57f56284, (q31_t)0xa3025859, (q31_t)0x57f0d1da, (q31_t)0xa2fe0724,
+    (q31_t)0x57ec40fa, (q31_t)0xa2f9b629,
+  (q31_t)0x57e7afe4, (q31_t)0xa2f56566, (q31_t)0x57e31e97, (q31_t)0xa2f114dd, (q31_t)0x57de8d15, (q31_t)0xa2ecc48e,
+    (q31_t)0x57d9fb5c, (q31_t)0xa2e87477,
+  (q31_t)0x57d5696d, (q31_t)0xa2e4249b, (q31_t)0x57d0d747, (q31_t)0xa2dfd4f7, (q31_t)0x57cc44ec, (q31_t)0xa2db858e,
+    (q31_t)0x57c7b25a, (q31_t)0xa2d7365d,
+  (q31_t)0x57c31f92, (q31_t)0xa2d2e766, (q31_t)0x57be8c94, (q31_t)0xa2ce98a9, (q31_t)0x57b9f960, (q31_t)0xa2ca4a25,
+    (q31_t)0x57b565f6, (q31_t)0xa2c5fbda,
+  (q31_t)0x57b0d256, (q31_t)0xa2c1adc9, (q31_t)0x57ac3e80, (q31_t)0xa2bd5ff2, (q31_t)0x57a7aa73, (q31_t)0xa2b91254,
+    (q31_t)0x57a31631, (q31_t)0xa2b4c4f0,
+  (q31_t)0x579e81b8, (q31_t)0xa2b077c5, (q31_t)0x5799ed0a, (q31_t)0xa2ac2ad3, (q31_t)0x57955825, (q31_t)0xa2a7de1c,
+    (q31_t)0x5790c30a, (q31_t)0xa2a3919e,
+  (q31_t)0x578c2dba, (q31_t)0xa29f4559, (q31_t)0x57879833, (q31_t)0xa29af94e, (q31_t)0x57830276, (q31_t)0xa296ad7d,
+    (q31_t)0x577e6c84, (q31_t)0xa29261e5,
+  (q31_t)0x5779d65b, (q31_t)0xa28e1687, (q31_t)0x57753ffc, (q31_t)0xa289cb63, (q31_t)0x5770a968, (q31_t)0xa2858078,
+    (q31_t)0x576c129d, (q31_t)0xa28135c7,
+  (q31_t)0x57677b9d, (q31_t)0xa27ceb4f, (q31_t)0x5762e467, (q31_t)0xa278a111, (q31_t)0x575e4cfa, (q31_t)0xa274570d,
+    (q31_t)0x5759b558, (q31_t)0xa2700d43,
+  (q31_t)0x57551d80, (q31_t)0xa26bc3b2, (q31_t)0x57508572, (q31_t)0xa2677a5b, (q31_t)0x574bed2f, (q31_t)0xa263313e,
+    (q31_t)0x574754b5, (q31_t)0xa25ee85b,
+  (q31_t)0x5742bc06, (q31_t)0xa25a9fb1, (q31_t)0x573e2320, (q31_t)0xa2565741, (q31_t)0x57398a05, (q31_t)0xa2520f0b,
+    (q31_t)0x5734f0b5, (q31_t)0xa24dc70f,
+  (q31_t)0x5730572e, (q31_t)0xa2497f4c, (q31_t)0x572bbd71, (q31_t)0xa24537c3, (q31_t)0x5727237f, (q31_t)0xa240f074,
+    (q31_t)0x57228957, (q31_t)0xa23ca95f,
+  (q31_t)0x571deefa, (q31_t)0xa2386284, (q31_t)0x57195466, (q31_t)0xa2341be3, (q31_t)0x5714b99d, (q31_t)0xa22fd57b,
+    (q31_t)0x57101e9e, (q31_t)0xa22b8f4d,
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+    (q31_t)0x56eb3f1a, (q31_t)0xa2096604,
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+    (q31_t)0x56d8ca51, (q31_t)0xa1f856ce,
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+    (q31_t)0x56c6522f, (q31_t)0xa1e74b38,
+  (q31_t)0x56c1b3a1, (q31_t)0xa1e308e4, (q31_t)0x56bd14dd, (q31_t)0xa1dec6ca, (q31_t)0x56b875e4, (q31_t)0xa1da84e9,
+    (q31_t)0x56b3d6b5, (q31_t)0xa1d64343,
+  (q31_t)0x56af3750, (q31_t)0xa1d201d7, (q31_t)0x56aa97b7, (q31_t)0xa1cdc0a5, (q31_t)0x56a5f7e7, (q31_t)0xa1c97fad,
+    (q31_t)0x56a157e3, (q31_t)0xa1c53ef0,
+  (q31_t)0x569cb7a8, (q31_t)0xa1c0fe6c, (q31_t)0x56981739, (q31_t)0xa1bcbe22, (q31_t)0x56937694, (q31_t)0xa1b87e13,
+    (q31_t)0x568ed5b9, (q31_t)0xa1b43e3e,
+  (q31_t)0x568a34a9, (q31_t)0xa1affea3, (q31_t)0x56859364, (q31_t)0xa1abbf42, (q31_t)0x5680f1ea, (q31_t)0xa1a7801b,
+    (q31_t)0x567c503a, (q31_t)0xa1a3412f,
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+    (q31_t)0x56573b3b, (q31_t)0xa18151fb,
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+    (q31_t)0x5644abbc, (q31_t)0xa1705fd8,
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+    (q31_t)0x526de11a, (q31_t)0x9e130b79,
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+    (q31_t)0x52476631, (q31_t)0x9df2b456,
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+  (q31_t)0x522f52ee, (q31_t)0x9dde858e, (q31_t)0x522a81af, (q31_t)0x9dda7ce9, (q31_t)0x5225b03d, (q31_t)0x9dd6747f,
+    (q31_t)0x5220de99, (q31_t)0x9dd26c53,
+  (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x52173ab8, (q31_t)0x9dca5caf, (q31_t)0x5212687b, (q31_t)0x9dc65539,
+    (q31_t)0x520d960c, (q31_t)0x9dc24dfe,
+  (q31_t)0x5208c36a, (q31_t)0x9dbe4701, (q31_t)0x5203f096, (q31_t)0x9dba4040, (q31_t)0x51ff1d8f, (q31_t)0x9db639bb,
+    (q31_t)0x51fa4a56, (q31_t)0x9db23373,
+  (q31_t)0x51f576ea, (q31_t)0x9dae2d68, (q31_t)0x51f0a34b, (q31_t)0x9daa279a, (q31_t)0x51ebcf7a, (q31_t)0x9da62208,
+    (q31_t)0x51e6fb76, (q31_t)0x9da21cb2,
+  (q31_t)0x51e22740, (q31_t)0x9d9e179a, (q31_t)0x51dd52d7, (q31_t)0x9d9a12be, (q31_t)0x51d87e3c, (q31_t)0x9d960e1f,
+    (q31_t)0x51d3a96f, (q31_t)0x9d9209bd,
+  (q31_t)0x51ced46e, (q31_t)0x9d8e0597, (q31_t)0x51c9ff3c, (q31_t)0x9d8a01ae, (q31_t)0x51c529d7, (q31_t)0x9d85fe02,
+    (q31_t)0x51c0543f, (q31_t)0x9d81fa92,
+  (q31_t)0x51bb7e75, (q31_t)0x9d7df75f, (q31_t)0x51b6a879, (q31_t)0x9d79f469, (q31_t)0x51b1d24a, (q31_t)0x9d75f1b0,
+    (q31_t)0x51acfbe9, (q31_t)0x9d71ef34,
+  (q31_t)0x51a82555, (q31_t)0x9d6decf4, (q31_t)0x51a34e8f, (q31_t)0x9d69eaf1, (q31_t)0x519e7797, (q31_t)0x9d65e92b,
+    (q31_t)0x5199a06d, (q31_t)0x9d61e7a2,
+  (q31_t)0x5194c910, (q31_t)0x9d5de656, (q31_t)0x518ff180, (q31_t)0x9d59e546, (q31_t)0x518b19bf, (q31_t)0x9d55e473,
+    (q31_t)0x518641cb, (q31_t)0x9d51e3dd,
+  (q31_t)0x518169a5, (q31_t)0x9d4de385, (q31_t)0x517c914c, (q31_t)0x9d49e368, (q31_t)0x5177b8c2, (q31_t)0x9d45e389,
+    (q31_t)0x5172e005, (q31_t)0x9d41e3e7,
+  (q31_t)0x516e0715, (q31_t)0x9d3de482, (q31_t)0x51692df4, (q31_t)0x9d39e559, (q31_t)0x516454a0, (q31_t)0x9d35e66e,
+    (q31_t)0x515f7b1a, (q31_t)0x9d31e7bf,
+  (q31_t)0x515aa162, (q31_t)0x9d2de94d, (q31_t)0x5155c778, (q31_t)0x9d29eb19, (q31_t)0x5150ed5c, (q31_t)0x9d25ed21,
+    (q31_t)0x514c130d, (q31_t)0x9d21ef66,
+  (q31_t)0x5147388c, (q31_t)0x9d1df1e9, (q31_t)0x51425dd9, (q31_t)0x9d19f4a8, (q31_t)0x513d82f4, (q31_t)0x9d15f7a4,
+    (q31_t)0x5138a7dd, (q31_t)0x9d11fadd,
+  (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x512ef119, (q31_t)0x9d0a0207, (q31_t)0x512a156b, (q31_t)0x9d0605f7,
+    (q31_t)0x5125398c, (q31_t)0x9d020a25,
+  (q31_t)0x51205d7b, (q31_t)0x9cfe0e8f, (q31_t)0x511b8137, (q31_t)0x9cfa1337, (q31_t)0x5116a4c1, (q31_t)0x9cf6181c,
+    (q31_t)0x5111c81a, (q31_t)0x9cf21d3d,
+  (q31_t)0x510ceb40, (q31_t)0x9cee229c, (q31_t)0x51080e35, (q31_t)0x9cea2838, (q31_t)0x510330f7, (q31_t)0x9ce62e11,
+    (q31_t)0x50fe5388, (q31_t)0x9ce23427,
+  (q31_t)0x50f975e6, (q31_t)0x9cde3a7b, (q31_t)0x50f49813, (q31_t)0x9cda410b, (q31_t)0x50efba0d, (q31_t)0x9cd647d9,
+    (q31_t)0x50eadbd6, (q31_t)0x9cd24ee4,
+  (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x50e11ed2, (q31_t)0x9cca5db1, (q31_t)0x50dc4005, (q31_t)0x9cc66573,
+    (q31_t)0x50d76106, (q31_t)0x9cc26d73,
+  (q31_t)0x50d281d5, (q31_t)0x9cbe75b0, (q31_t)0x50cda272, (q31_t)0x9cba7e2a, (q31_t)0x50c8c2de, (q31_t)0x9cb686e1,
+    (q31_t)0x50c3e317, (q31_t)0x9cb28fd5,
+  (q31_t)0x50bf031f, (q31_t)0x9cae9907, (q31_t)0x50ba22f5, (q31_t)0x9caaa276, (q31_t)0x50b5429a, (q31_t)0x9ca6ac23,
+    (q31_t)0x50b0620c, (q31_t)0x9ca2b60c,
+  (q31_t)0x50ab814d, (q31_t)0x9c9ec033, (q31_t)0x50a6a05c, (q31_t)0x9c9aca97, (q31_t)0x50a1bf39, (q31_t)0x9c96d539,
+    (q31_t)0x509cdde4, (q31_t)0x9c92e017,
+  (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x50931aa6, (q31_t)0x9c8af68d, (q31_t)0x508e38bd, (q31_t)0x9c870224,
+    (q31_t)0x508956a1, (q31_t)0x9c830df8,
+  (q31_t)0x50847454, (q31_t)0x9c7f1a0a, (q31_t)0x507f91d5, (q31_t)0x9c7b2659, (q31_t)0x507aaf25, (q31_t)0x9c7732e5,
+    (q31_t)0x5075cc43, (q31_t)0x9c733faf,
+  (q31_t)0x5070e92f, (q31_t)0x9c6f4cb6, (q31_t)0x506c05ea, (q31_t)0x9c6b59fa, (q31_t)0x50672273, (q31_t)0x9c67677c,
+    (q31_t)0x50623ecb, (q31_t)0x9c63753c,
+  (q31_t)0x505d5af1, (q31_t)0x9c5f8339, (q31_t)0x505876e5, (q31_t)0x9c5b9173, (q31_t)0x505392a8, (q31_t)0x9c579feb,
+    (q31_t)0x504eae39, (q31_t)0x9c53aea0,
+  (q31_t)0x5049c999, (q31_t)0x9c4fbd93, (q31_t)0x5044e4c7, (q31_t)0x9c4bccc3, (q31_t)0x503fffc4, (q31_t)0x9c47dc31,
+    (q31_t)0x503b1a8f, (q31_t)0x9c43ebdc,
+  (q31_t)0x50363529, (q31_t)0x9c3ffbc5, (q31_t)0x50314f91, (q31_t)0x9c3c0beb, (q31_t)0x502c69c8, (q31_t)0x9c381c4f,
+    (q31_t)0x502783cd, (q31_t)0x9c342cf0,
+  (q31_t)0x50229da1, (q31_t)0x9c303dcf, (q31_t)0x501db743, (q31_t)0x9c2c4eec, (q31_t)0x5018d0b4, (q31_t)0x9c286046,
+    (q31_t)0x5013e9f4, (q31_t)0x9c2471de,
+  (q31_t)0x500f0302, (q31_t)0x9c2083b3, (q31_t)0x500a1bdf, (q31_t)0x9c1c95c6, (q31_t)0x5005348a, (q31_t)0x9c18a816,
+    (q31_t)0x50004d04, (q31_t)0x9c14baa4,
+  (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4ff67d64, (q31_t)0x9c0ce07a, (q31_t)0x4ff1954b, (q31_t)0x9c08f3c1,
+    (q31_t)0x4fecacff, (q31_t)0x9c050745,
+  (q31_t)0x4fe7c483, (q31_t)0x9c011b08, (q31_t)0x4fe2dbd5, (q31_t)0x9bfd2f08, (q31_t)0x4fddf2f6, (q31_t)0x9bf94346,
+    (q31_t)0x4fd909e5, (q31_t)0x9bf557c1,
+  (q31_t)0x4fd420a4, (q31_t)0x9bf16c7a, (q31_t)0x4fcf3731, (q31_t)0x9bed8171, (q31_t)0x4fca4d8d, (q31_t)0x9be996a6,
+    (q31_t)0x4fc563b7, (q31_t)0x9be5ac18,
+  (q31_t)0x4fc079b1, (q31_t)0x9be1c1c8, (q31_t)0x4fbb8f79, (q31_t)0x9bddd7b6, (q31_t)0x4fb6a510, (q31_t)0x9bd9ede2,
+    (q31_t)0x4fb1ba76, (q31_t)0x9bd6044b,
+  (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4fa7e4af, (q31_t)0x9bce31d8, (q31_t)0x4fa2f981, (q31_t)0x9bca48fa,
+    (q31_t)0x4f9e0e22, (q31_t)0x9bc6605b,
+  (q31_t)0x4f992293, (q31_t)0x9bc277fa, (q31_t)0x4f9436d2, (q31_t)0x9bbe8fd6, (q31_t)0x4f8f4ae0, (q31_t)0x9bbaa7f0,
+    (q31_t)0x4f8a5ebd, (q31_t)0x9bb6c048,
+  (q31_t)0x4f857269, (q31_t)0x9bb2d8de, (q31_t)0x4f8085e4, (q31_t)0x9baef1b2, (q31_t)0x4f7b992d, (q31_t)0x9bab0ac3,
+    (q31_t)0x4f76ac46, (q31_t)0x9ba72413,
+  (q31_t)0x4f71bf2e, (q31_t)0x9ba33da0, (q31_t)0x4f6cd1e5, (q31_t)0x9b9f576b, (q31_t)0x4f67e46a, (q31_t)0x9b9b7174,
+    (q31_t)0x4f62f6bf, (q31_t)0x9b978bbc,
+  (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f591ad6, (q31_t)0x9b8fc104, (q31_t)0x4f542c98, (q31_t)0x9b8bdc05,
+    (q31_t)0x4f4f3e29, (q31_t)0x9b87f744,
+  (q31_t)0x4f4a4f89, (q31_t)0x9b8412c1, (q31_t)0x4f4560b8, (q31_t)0x9b802e7b, (q31_t)0x4f4071b6, (q31_t)0x9b7c4a74,
+    (q31_t)0x4f3b8284, (q31_t)0x9b7866ab,
+  (q31_t)0x4f369320, (q31_t)0x9b748320, (q31_t)0x4f31a38c, (q31_t)0x9b709fd3, (q31_t)0x4f2cb3c7, (q31_t)0x9b6cbcc4,
+    (q31_t)0x4f27c3d1, (q31_t)0x9b68d9f3,
+  (q31_t)0x4f22d3aa, (q31_t)0x9b64f760, (q31_t)0x4f1de352, (q31_t)0x9b61150b, (q31_t)0x4f18f2c9, (q31_t)0x9b5d32f4,
+    (q31_t)0x4f140210, (q31_t)0x9b59511c,
+  (q31_t)0x4f0f1126, (q31_t)0x9b556f81, (q31_t)0x4f0a200b, (q31_t)0x9b518e24, (q31_t)0x4f052ec0, (q31_t)0x9b4dad06,
+    (q31_t)0x4f003d43, (q31_t)0x9b49cc26,
+  (q31_t)0x4efb4b96, (q31_t)0x9b45eb83, (q31_t)0x4ef659b8, (q31_t)0x9b420b1f, (q31_t)0x4ef167aa, (q31_t)0x9b3e2af9,
+    (q31_t)0x4eec756b, (q31_t)0x9b3a4b11,
+  (q31_t)0x4ee782fb, (q31_t)0x9b366b68, (q31_t)0x4ee2905a, (q31_t)0x9b328bfc, (q31_t)0x4edd9d89, (q31_t)0x9b2eaccf,
+    (q31_t)0x4ed8aa87, (q31_t)0x9b2acde0,
+  (q31_t)0x4ed3b755, (q31_t)0x9b26ef2f, (q31_t)0x4ecec3f2, (q31_t)0x9b2310bc, (q31_t)0x4ec9d05e, (q31_t)0x9b1f3288,
+    (q31_t)0x4ec4dc99, (q31_t)0x9b1b5492,
+  (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4ebaf47f, (q31_t)0x9b139960, (q31_t)0x4eb60029, (q31_t)0x9b0fbc24,
+    (q31_t)0x4eb10ba2, (q31_t)0x9b0bdf27,
+  (q31_t)0x4eac16eb, (q31_t)0x9b080268, (q31_t)0x4ea72203, (q31_t)0x9b0425e8, (q31_t)0x4ea22ceb, (q31_t)0x9b0049a5,
+    (q31_t)0x4e9d37a3, (q31_t)0x9afc6da1,
+  (q31_t)0x4e984229, (q31_t)0x9af891db, (q31_t)0x4e934c80, (q31_t)0x9af4b654, (q31_t)0x4e8e56a5, (q31_t)0x9af0db0b,
+    (q31_t)0x4e89609b, (q31_t)0x9aed0000,
+  (q31_t)0x4e846a60, (q31_t)0x9ae92533, (q31_t)0x4e7f73f4, (q31_t)0x9ae54aa5, (q31_t)0x4e7a7d58, (q31_t)0x9ae17056,
+    (q31_t)0x4e75868c, (q31_t)0x9add9644,
+  (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e6b9862, (q31_t)0x9ad5e2dd, (q31_t)0x4e66a105, (q31_t)0x9ad20987,
+    (q31_t)0x4e61a977, (q31_t)0x9ace306f,
+  (q31_t)0x4e5cb1b9, (q31_t)0x9aca5795, (q31_t)0x4e57b9ca, (q31_t)0x9ac67efb, (q31_t)0x4e52c1ab, (q31_t)0x9ac2a69e,
+    (q31_t)0x4e4dc95c, (q31_t)0x9abece80,
+  (q31_t)0x4e48d0dd, (q31_t)0x9abaf6a1, (q31_t)0x4e43d82d, (q31_t)0x9ab71eff, (q31_t)0x4e3edf4d, (q31_t)0x9ab3479d,
+    (q31_t)0x4e39e63d, (q31_t)0x9aaf7079,
+  (q31_t)0x4e34ecfc, (q31_t)0x9aab9993, (q31_t)0x4e2ff38b, (q31_t)0x9aa7c2ec, (q31_t)0x4e2af9ea, (q31_t)0x9aa3ec83,
+    (q31_t)0x4e260019, (q31_t)0x9aa01659,
+  (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4e1c0be6, (q31_t)0x9a986ac1, (q31_t)0x4e171184, (q31_t)0x9a949552,
+    (q31_t)0x4e1216f2, (q31_t)0x9a90c022,
+  (q31_t)0x4e0d1c30, (q31_t)0x9a8ceb31, (q31_t)0x4e08213e, (q31_t)0x9a89167e, (q31_t)0x4e03261b, (q31_t)0x9a85420a,
+    (q31_t)0x4dfe2ac9, (q31_t)0x9a816dd5,
+  (q31_t)0x4df92f46, (q31_t)0x9a7d99de, (q31_t)0x4df43393, (q31_t)0x9a79c625, (q31_t)0x4def37b0, (q31_t)0x9a75f2ac,
+    (q31_t)0x4dea3b9d, (q31_t)0x9a721f71,
+  (q31_t)0x4de53f5a, (q31_t)0x9a6e4c74, (q31_t)0x4de042e7, (q31_t)0x9a6a79b6, (q31_t)0x4ddb4644, (q31_t)0x9a66a737,
+    (q31_t)0x4dd64971, (q31_t)0x9a62d4f7,
+  (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5, (q31_t)0x4dcc4f3b, (q31_t)0x9a5b3132, (q31_t)0x4dc751d8, (q31_t)0x9a575fae,
+    (q31_t)0x4dc25445, (q31_t)0x9a538e68,
+  (q31_t)0x4dbd5682, (q31_t)0x9a4fbd61, (q31_t)0x4db8588f, (q31_t)0x9a4bec99, (q31_t)0x4db35a6c, (q31_t)0x9a481c0f,
+    (q31_t)0x4dae5c19, (q31_t)0x9a444bc5,
+  (q31_t)0x4da95d96, (q31_t)0x9a407bb9, (q31_t)0x4da45ee3, (q31_t)0x9a3cabeb, (q31_t)0x4d9f6001, (q31_t)0x9a38dc5d,
+    (q31_t)0x4d9a60ee, (q31_t)0x9a350d0d,
+  (q31_t)0x4d9561ac, (q31_t)0x9a313dfc, (q31_t)0x4d90623a, (q31_t)0x9a2d6f2a, (q31_t)0x4d8b6298, (q31_t)0x9a29a097,
+    (q31_t)0x4d8662c6, (q31_t)0x9a25d243,
+  (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d7c6293, (q31_t)0x9a1e3656, (q31_t)0x4d776231, (q31_t)0x9a1a68be,
+    (q31_t)0x4d7261a0, (q31_t)0x9a169b65,
+  (q31_t)0x4d6d60df, (q31_t)0x9a12ce4b, (q31_t)0x4d685fef, (q31_t)0x9a0f016f, (q31_t)0x4d635ece, (q31_t)0x9a0b34d3,
+    (q31_t)0x4d5e5d7e, (q31_t)0x9a076875,
+  (q31_t)0x4d595bfe, (q31_t)0x9a039c57, (q31_t)0x4d545a4f, (q31_t)0x99ffd077, (q31_t)0x4d4f5870, (q31_t)0x99fc04d6,
+    (q31_t)0x4d4a5661, (q31_t)0x99f83974,
+  (q31_t)0x4d455422, (q31_t)0x99f46e51, (q31_t)0x4d4051b4, (q31_t)0x99f0a36d, (q31_t)0x4d3b4f16, (q31_t)0x99ecd8c8,
+    (q31_t)0x4d364c48, (q31_t)0x99e90e62,
+  (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4d2c461e, (q31_t)0x99e17a53, (q31_t)0x4d2742c2, (q31_t)0x99ddb0aa,
+    (q31_t)0x4d223f36, (q31_t)0x99d9e73f,
+  (q31_t)0x4d1d3b7a, (q31_t)0x99d61e14, (q31_t)0x4d18378f, (q31_t)0x99d25528, (q31_t)0x4d133374, (q31_t)0x99ce8c7b,
+    (q31_t)0x4d0e2f2a, (q31_t)0x99cac40d,
+  (q31_t)0x4d092ab0, (q31_t)0x99c6fbde, (q31_t)0x4d042607, (q31_t)0x99c333ee, (q31_t)0x4cff212e, (q31_t)0x99bf6c3d,
+    (q31_t)0x4cfa1c26, (q31_t)0x99bba4cb,
+  (q31_t)0x4cf516ee, (q31_t)0x99b7dd99, (q31_t)0x4cf01187, (q31_t)0x99b416a5, (q31_t)0x4ceb0bf0, (q31_t)0x99b04ff0,
+    (q31_t)0x4ce6062a, (q31_t)0x99ac897b,
+  (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4cdbfa0f, (q31_t)0x99a4fd4d, (q31_t)0x4cd6f3bb, (q31_t)0x99a13795,
+    (q31_t)0x4cd1ed37, (q31_t)0x999d721c,
+  (q31_t)0x4ccce684, (q31_t)0x9999ace3, (q31_t)0x4cc7dfa1, (q31_t)0x9995e7e8, (q31_t)0x4cc2d88f, (q31_t)0x9992232d,
+    (q31_t)0x4cbdd14e, (q31_t)0x998e5eb1,
+  (q31_t)0x4cb8c9dd, (q31_t)0x998a9a74, (q31_t)0x4cb3c23d, (q31_t)0x9986d676, (q31_t)0x4caeba6e, (q31_t)0x998312b7,
+    (q31_t)0x4ca9b26f, (q31_t)0x997f4f38,
+  (q31_t)0x4ca4aa41, (q31_t)0x997b8bf8, (q31_t)0x4c9fa1e4, (q31_t)0x9977c8f7, (q31_t)0x4c9a9958, (q31_t)0x99740635,
+    (q31_t)0x4c95909c, (q31_t)0x997043b2,
+  (q31_t)0x4c9087b1, (q31_t)0x996c816f, (q31_t)0x4c8b7e97, (q31_t)0x9968bf6b, (q31_t)0x4c86754e, (q31_t)0x9964fda7,
+    (q31_t)0x4c816bd5, (q31_t)0x99613c22,
+  (q31_t)0x4c7c622d, (q31_t)0x995d7adc, (q31_t)0x4c775856, (q31_t)0x9959b9d5, (q31_t)0x4c724e50, (q31_t)0x9955f90d,
+    (q31_t)0x4c6d441b, (q31_t)0x99523885,
+  (q31_t)0x4c6839b7, (q31_t)0x994e783d, (q31_t)0x4c632f23, (q31_t)0x994ab833, (q31_t)0x4c5e2460, (q31_t)0x9946f869,
+    (q31_t)0x4c59196f, (q31_t)0x994338df,
+  (q31_t)0x4c540e4e, (q31_t)0x993f7993, (q31_t)0x4c4f02fe, (q31_t)0x993bba87, (q31_t)0x4c49f77f, (q31_t)0x9937fbbb,
+    (q31_t)0x4c44ebd1, (q31_t)0x99343d2e,
+  (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4c3ad3e7, (q31_t)0x992cc0d2, (q31_t)0x4c35c7ac, (q31_t)0x99290303,
+    (q31_t)0x4c30bb42, (q31_t)0x99254574,
+  (q31_t)0x4c2baea9, (q31_t)0x99218824, (q31_t)0x4c26a1e1, (q31_t)0x991dcb13, (q31_t)0x4c2194e9, (q31_t)0x991a0e42,
+    (q31_t)0x4c1c87c3, (q31_t)0x991651b1,
+  (q31_t)0x4c177a6e, (q31_t)0x9912955f, (q31_t)0x4c126cea, (q31_t)0x990ed94c, (q31_t)0x4c0d5f37, (q31_t)0x990b1d79,
+    (q31_t)0x4c085156, (q31_t)0x990761e5,
+  (q31_t)0x4c034345, (q31_t)0x9903a691, (q31_t)0x4bfe3505, (q31_t)0x98ffeb7d, (q31_t)0x4bf92697, (q31_t)0x98fc30a8,
+    (q31_t)0x4bf417f9, (q31_t)0x98f87612,
+  (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4be9fa32, (q31_t)0x98f101a6, (q31_t)0x4be4eb08, (q31_t)0x98ed47cf,
+    (q31_t)0x4bdfdbaf, (q31_t)0x98e98e38,
+  (q31_t)0x4bdacc28, (q31_t)0x98e5d4e0, (q31_t)0x4bd5bc72, (q31_t)0x98e21bc8, (q31_t)0x4bd0ac8d, (q31_t)0x98de62f0,
+    (q31_t)0x4bcb9c79, (q31_t)0x98daaa57,
+  (q31_t)0x4bc68c36, (q31_t)0x98d6f1fe, (q31_t)0x4bc17bc5, (q31_t)0x98d339e4, (q31_t)0x4bbc6b25, (q31_t)0x98cf820b,
+    (q31_t)0x4bb75a56, (q31_t)0x98cbca70,
+  (q31_t)0x4bb24958, (q31_t)0x98c81316, (q31_t)0x4bad382c, (q31_t)0x98c45bfb, (q31_t)0x4ba826d1, (q31_t)0x98c0a520,
+    (q31_t)0x4ba31548, (q31_t)0x98bcee84,
+  (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b98f1a9, (q31_t)0x98b5820c, (q31_t)0x4b93df93, (q31_t)0x98b1cc30,
+    (q31_t)0x4b8ecd4f, (q31_t)0x98ae1693,
+  (q31_t)0x4b89badd, (q31_t)0x98aa6136, (q31_t)0x4b84a83b, (q31_t)0x98a6ac19, (q31_t)0x4b7f956b, (q31_t)0x98a2f73c,
+    (q31_t)0x4b7a826d, (q31_t)0x989f429e,
+  (q31_t)0x4b756f40, (q31_t)0x989b8e40, (q31_t)0x4b705be4, (q31_t)0x9897da22, (q31_t)0x4b6b485a, (q31_t)0x98942643,
+    (q31_t)0x4b6634a2, (q31_t)0x989072a5,
+  (q31_t)0x4b6120bb, (q31_t)0x988cbf46, (q31_t)0x4b5c0ca5, (q31_t)0x98890c27, (q31_t)0x4b56f861, (q31_t)0x98855948,
+    (q31_t)0x4b51e3ee, (q31_t)0x9881a6a9,
+  (q31_t)0x4b4ccf4d, (q31_t)0x987df449, (q31_t)0x4b47ba7e, (q31_t)0x987a422a, (q31_t)0x4b42a580, (q31_t)0x9876904a,
+    (q31_t)0x4b3d9053, (q31_t)0x9872deaa,
+  (q31_t)0x4b387af9, (q31_t)0x986f2d4a, (q31_t)0x4b336570, (q31_t)0x986b7c2a, (q31_t)0x4b2e4fb8, (q31_t)0x9867cb4a,
+    (q31_t)0x4b2939d2, (q31_t)0x98641aa9,
+  (q31_t)0x4b2423be, (q31_t)0x98606a49, (q31_t)0x4b1f0d7b, (q31_t)0x985cba28, (q31_t)0x4b19f70a, (q31_t)0x98590a48,
+    (q31_t)0x4b14e06b, (q31_t)0x98555aa7,
+  (q31_t)0x4b0fc99d, (q31_t)0x9851ab46, (q31_t)0x4b0ab2a1, (q31_t)0x984dfc26, (q31_t)0x4b059b77, (q31_t)0x984a4d45,
+    (q31_t)0x4b00841f, (q31_t)0x98469ea4,
+  (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4af654e3, (q31_t)0x983f4223, (q31_t)0x4af13d00, (q31_t)0x983b9442,
+    (q31_t)0x4aec24ee, (q31_t)0x9837e6a1,
+  (q31_t)0x4ae70caf, (q31_t)0x98343940, (q31_t)0x4ae1f441, (q31_t)0x98308c1f, (q31_t)0x4adcdba5, (q31_t)0x982cdf3f,
+    (q31_t)0x4ad7c2da, (q31_t)0x9829329e,
+  (q31_t)0x4ad2a9e2, (q31_t)0x9825863d, (q31_t)0x4acd90bb, (q31_t)0x9821da1d, (q31_t)0x4ac87767, (q31_t)0x981e2e3c,
+    (q31_t)0x4ac35de4, (q31_t)0x981a829c,
+  (q31_t)0x4abe4433, (q31_t)0x9816d73b, (q31_t)0x4ab92a54, (q31_t)0x98132c1b, (q31_t)0x4ab41046, (q31_t)0x980f813b,
+    (q31_t)0x4aaef60b, (q31_t)0x980bd69b,
+  (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4aa4c10b, (q31_t)0x9804821b, (q31_t)0x4a9fa645, (q31_t)0x9800d83c,
+    (q31_t)0x4a9a8b52, (q31_t)0x97fd2e9c,
+  (q31_t)0x4a957030, (q31_t)0x97f9853d, (q31_t)0x4a9054e1, (q31_t)0x97f5dc1e, (q31_t)0x4a8b3963, (q31_t)0x97f2333f,
+    (q31_t)0x4a861db8, (q31_t)0x97ee8aa0,
+  (q31_t)0x4a8101de, (q31_t)0x97eae242, (q31_t)0x4a7be5d7, (q31_t)0x97e73a23, (q31_t)0x4a76c9a2, (q31_t)0x97e39245,
+    (q31_t)0x4a71ad3e, (q31_t)0x97dfeaa7,
+  (q31_t)0x4a6c90ad, (q31_t)0x97dc4349, (q31_t)0x4a6773ee, (q31_t)0x97d89c2c, (q31_t)0x4a625701, (q31_t)0x97d4f54f,
+    (q31_t)0x4a5d39e6, (q31_t)0x97d14eb2,
+  (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a52ff27, (q31_t)0x97ca0239, (q31_t)0x4a4de182, (q31_t)0x97c65c5c,
+    (q31_t)0x4a48c3b0, (q31_t)0x97c2b6c1,
+  (q31_t)0x4a43a5b0, (q31_t)0x97bf1165, (q31_t)0x4a3e8782, (q31_t)0x97bb6c4a, (q31_t)0x4a396926, (q31_t)0x97b7c76f,
+    (q31_t)0x4a344a9d, (q31_t)0x97b422d4,
+  (q31_t)0x4a2f2be6, (q31_t)0x97b07e7a, (q31_t)0x4a2a0d01, (q31_t)0x97acda60, (q31_t)0x4a24edee, (q31_t)0x97a93687,
+    (q31_t)0x4a1fcead, (q31_t)0x97a592ed,
+  (q31_t)0x4a1aaf3f, (q31_t)0x97a1ef94, (q31_t)0x4a158fa3, (q31_t)0x979e4c7c, (q31_t)0x4a106fda, (q31_t)0x979aa9a4,
+    (q31_t)0x4a0b4fe2, (q31_t)0x9797070c,
+  (q31_t)0x4a062fbd, (q31_t)0x979364b5, (q31_t)0x4a010f6b, (q31_t)0x978fc29e, (q31_t)0x49fbeeea, (q31_t)0x978c20c8,
+    (q31_t)0x49f6ce3c, (q31_t)0x97887f32,
+  (q31_t)0x49f1ad61, (q31_t)0x9784dddc, (q31_t)0x49ec8c57, (q31_t)0x97813cc7, (q31_t)0x49e76b21, (q31_t)0x977d9bf2,
+    (q31_t)0x49e249bc, (q31_t)0x9779fb5e,
+  (q31_t)0x49dd282a, (q31_t)0x97765b0a, (q31_t)0x49d8066b, (q31_t)0x9772baf7, (q31_t)0x49d2e47e, (q31_t)0x976f1b24,
+    (q31_t)0x49cdc263, (q31_t)0x976b7b92,
+  (q31_t)0x49c8a01b, (q31_t)0x9767dc41, (q31_t)0x49c37da5, (q31_t)0x97643d2f, (q31_t)0x49be5b02, (q31_t)0x97609e5f,
+    (q31_t)0x49b93832, (q31_t)0x975cffcf,
+  (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x49aef208, (q31_t)0x9755c370, (q31_t)0x49a9ceaf, (q31_t)0x975225a1,
+    (q31_t)0x49a4ab28, (q31_t)0x974e8813,
+  (q31_t)0x499f8774, (q31_t)0x974aeac6, (q31_t)0x499a6393, (q31_t)0x97474db9, (q31_t)0x49953f84, (q31_t)0x9743b0ed,
+    (q31_t)0x49901b48, (q31_t)0x97401462,
+  (q31_t)0x498af6df, (q31_t)0x973c7817, (q31_t)0x4985d248, (q31_t)0x9738dc0d, (q31_t)0x4980ad84, (q31_t)0x97354043,
+    (q31_t)0x497b8892, (q31_t)0x9731a4ba,
+  (q31_t)0x49766373, (q31_t)0x972e0971, (q31_t)0x49713e27, (q31_t)0x972a6e6a, (q31_t)0x496c18ae, (q31_t)0x9726d3a3,
+    (q31_t)0x4966f307, (q31_t)0x9723391c,
+  (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x495ca732, (q31_t)0x971c04d2, (q31_t)0x49578103, (q31_t)0x97186b0d,
+    (q31_t)0x49525aa7, (q31_t)0x9714d18a,
+  (q31_t)0x494d341e, (q31_t)0x97113847, (q31_t)0x49480d68, (q31_t)0x970d9f45, (q31_t)0x4942e684, (q31_t)0x970a0683,
+    (q31_t)0x493dbf74, (q31_t)0x97066e03,
+  (q31_t)0x49389836, (q31_t)0x9702d5c3, (q31_t)0x493370cb, (q31_t)0x96ff3dc4, (q31_t)0x492e4933, (q31_t)0x96fba605,
+    (q31_t)0x4929216e, (q31_t)0x96f80e88,
+  (q31_t)0x4923f97b, (q31_t)0x96f4774b, (q31_t)0x491ed15c, (q31_t)0x96f0e04f, (q31_t)0x4919a90f, (q31_t)0x96ed4994,
+    (q31_t)0x49148095, (q31_t)0x96e9b319,
+  (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x490a2f1b, (q31_t)0x96e286e7, (q31_t)0x4905061a, (q31_t)0x96def12f,
+    (q31_t)0x48ffdcec, (q31_t)0x96db5bb8,
+  (q31_t)0x48fab391, (q31_t)0x96d7c682, (q31_t)0x48f58a09, (q31_t)0x96d4318d, (q31_t)0x48f06054, (q31_t)0x96d09cd8,
+    (q31_t)0x48eb3672, (q31_t)0x96cd0865,
+  (q31_t)0x48e60c62, (q31_t)0x96c97432, (q31_t)0x48e0e227, (q31_t)0x96c5e040, (q31_t)0x48dbb7be, (q31_t)0x96c24c8f,
+    (q31_t)0x48d68d28, (q31_t)0x96beb91f,
+  (q31_t)0x48d16265, (q31_t)0x96bb25f0, (q31_t)0x48cc3775, (q31_t)0x96b79302, (q31_t)0x48c70c59, (q31_t)0x96b40055,
+    (q31_t)0x48c1e10f, (q31_t)0x96b06de9,
+  (q31_t)0x48bcb599, (q31_t)0x96acdbbe, (q31_t)0x48b789f5, (q31_t)0x96a949d3, (q31_t)0x48b25e25, (q31_t)0x96a5b82a,
+    (q31_t)0x48ad3228, (q31_t)0x96a226c2,
+  (q31_t)0x48a805ff, (q31_t)0x969e959b, (q31_t)0x48a2d9a8, (q31_t)0x969b04b4, (q31_t)0x489dad25, (q31_t)0x9697740f,
+    (q31_t)0x48988074, (q31_t)0x9693e3ab,
+  (q31_t)0x48935397, (q31_t)0x96905388, (q31_t)0x488e268e, (q31_t)0x968cc3a5, (q31_t)0x4888f957, (q31_t)0x96893404,
+    (q31_t)0x4883cbf4, (q31_t)0x9685a4a4,
+  (q31_t)0x487e9e64, (q31_t)0x96821585, (q31_t)0x487970a7, (q31_t)0x967e86a7, (q31_t)0x487442be, (q31_t)0x967af80a,
+    (q31_t)0x486f14a8, (q31_t)0x967769af,
+  (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x4864b7f5, (q31_t)0x96704dba, (q31_t)0x485f8959, (q31_t)0x966cc022,
+    (q31_t)0x485a5a90, (q31_t)0x966932cb,
+  (q31_t)0x48552b9b, (q31_t)0x9665a5b4, (q31_t)0x484ffc79, (q31_t)0x966218df, (q31_t)0x484acd2a, (q31_t)0x965e8c4b,
+    (q31_t)0x48459daf, (q31_t)0x965afff9,
+  (q31_t)0x48406e08, (q31_t)0x965773e7, (q31_t)0x483b3e33, (q31_t)0x9653e817, (q31_t)0x48360e32, (q31_t)0x96505c88,
+    (q31_t)0x4830de05, (q31_t)0x964cd139,
+  (q31_t)0x482badab, (q31_t)0x9649462d, (q31_t)0x48267d24, (q31_t)0x9645bb61, (q31_t)0x48214c71, (q31_t)0x964230d7,
+    (q31_t)0x481c1b92, (q31_t)0x963ea68d,
+  (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x4811b94d, (q31_t)0x963792bf, (q31_t)0x480c87e8, (q31_t)0x96340939,
+    (q31_t)0x48075657, (q31_t)0x96307ff5,
+  (q31_t)0x48022499, (q31_t)0x962cf6f2, (q31_t)0x47fcf2af, (q31_t)0x96296e31, (q31_t)0x47f7c099, (q31_t)0x9625e5b0,
+    (q31_t)0x47f28e56, (q31_t)0x96225d71,
+  (q31_t)0x47ed5be6, (q31_t)0x961ed574, (q31_t)0x47e8294a, (q31_t)0x961b4db7, (q31_t)0x47e2f682, (q31_t)0x9617c63c,
+    (q31_t)0x47ddc38e, (q31_t)0x96143f02,
+  (q31_t)0x47d8906d, (q31_t)0x9610b80a, (q31_t)0x47d35d20, (q31_t)0x960d3153, (q31_t)0x47ce29a7, (q31_t)0x9609aadd,
+    (q31_t)0x47c8f601, (q31_t)0x960624a9,
+  (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47be8e31, (q31_t)0x95ff1904, (q31_t)0x47b95a06, (q31_t)0x95fb9394,
+    (q31_t)0x47b425af, (q31_t)0x95f80e65,
+  (q31_t)0x47aef12c, (q31_t)0x95f48977, (q31_t)0x47a9bc7d, (q31_t)0x95f104cb, (q31_t)0x47a487a2, (q31_t)0x95ed8061,
+    (q31_t)0x479f529a, (q31_t)0x95e9fc38,
+  (q31_t)0x479a1d67, (q31_t)0x95e67850, (q31_t)0x4794e807, (q31_t)0x95e2f4a9, (q31_t)0x478fb27b, (q31_t)0x95df7145,
+    (q31_t)0x478a7cc2, (q31_t)0x95dbee21,
+  (q31_t)0x478546de, (q31_t)0x95d86b3f, (q31_t)0x478010cd, (q31_t)0x95d4e89f, (q31_t)0x477ada91, (q31_t)0x95d16640,
+    (q31_t)0x4775a428, (q31_t)0x95cde423,
+  (q31_t)0x47706d93, (q31_t)0x95ca6247, (q31_t)0x476b36d3, (q31_t)0x95c6e0ac, (q31_t)0x4765ffe6, (q31_t)0x95c35f53,
+    (q31_t)0x4760c8cd, (q31_t)0x95bfde3c,
+  (q31_t)0x475b9188, (q31_t)0x95bc5d66, (q31_t)0x47565a17, (q31_t)0x95b8dcd2, (q31_t)0x4751227a, (q31_t)0x95b55c7f,
+    (q31_t)0x474beab1, (q31_t)0x95b1dc6e,
+  (q31_t)0x4746b2bc, (q31_t)0x95ae5c9f, (q31_t)0x47417a9b, (q31_t)0x95aadd11, (q31_t)0x473c424e, (q31_t)0x95a75dc4,
+    (q31_t)0x473709d5, (q31_t)0x95a3deb9,
+  (q31_t)0x4731d131, (q31_t)0x95a05ff0, (q31_t)0x472c9860, (q31_t)0x959ce169, (q31_t)0x47275f63, (q31_t)0x95996323,
+    (q31_t)0x4722263b, (q31_t)0x9595e51e,
+  (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x4717b367, (q31_t)0x958ee9db, (q31_t)0x471279ba, (q31_t)0x958b6c9b,
+    (q31_t)0x470d3fe3, (q31_t)0x9587ef9e,
+  (q31_t)0x470805df, (q31_t)0x958472e2, (q31_t)0x4702cbaf, (q31_t)0x9580f667, (q31_t)0x46fd9154, (q31_t)0x957d7a2f,
+    (q31_t)0x46f856cd, (q31_t)0x9579fe38,
+  (q31_t)0x46f31c1a, (q31_t)0x95768283, (q31_t)0x46ede13b, (q31_t)0x9573070f, (q31_t)0x46e8a631, (q31_t)0x956f8bdd,
+    (q31_t)0x46e36afb, (q31_t)0x956c10ed,
+  (q31_t)0x46de2f99, (q31_t)0x9568963f, (q31_t)0x46d8f40b, (q31_t)0x95651bd2, (q31_t)0x46d3b852, (q31_t)0x9561a1a8,
+    (q31_t)0x46ce7c6d, (q31_t)0x955e27bf,
+  (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46c40420, (q31_t)0x955734b2, (q31_t)0x46bec7b8, (q31_t)0x9553bb8e,
+    (q31_t)0x46b98b24, (q31_t)0x955042ac,
+  (q31_t)0x46b44e65, (q31_t)0x954cca0c, (q31_t)0x46af117a, (q31_t)0x954951ae, (q31_t)0x46a9d464, (q31_t)0x9545d992,
+    (q31_t)0x46a49722, (q31_t)0x954261b7,
+  (q31_t)0x469f59b4, (q31_t)0x953eea1e, (q31_t)0x469a1c1b, (q31_t)0x953b72c7, (q31_t)0x4694de56, (q31_t)0x9537fbb2,
+    (q31_t)0x468fa066, (q31_t)0x953484df,
+  (q31_t)0x468a624a, (q31_t)0x95310e4e, (q31_t)0x46852403, (q31_t)0x952d97fe, (q31_t)0x467fe590, (q31_t)0x952a21f1,
+    (q31_t)0x467aa6f2, (q31_t)0x9526ac25,
+  (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x46702933, (q31_t)0x951fc154, (q31_t)0x466aea12, (q31_t)0x951c4c4e,
+    (q31_t)0x4665aac6, (q31_t)0x9518d78a,
+  (q31_t)0x46606b4e, (q31_t)0x95156308, (q31_t)0x465b2bab, (q31_t)0x9511eec8, (q31_t)0x4655ebdd, (q31_t)0x950e7aca,
+    (q31_t)0x4650abe3, (q31_t)0x950b070e,
+  (q31_t)0x464b6bbe, (q31_t)0x95079394, (q31_t)0x46462b6d, (q31_t)0x9504205c, (q31_t)0x4640eaf2, (q31_t)0x9500ad66,
+    (q31_t)0x463baa4a, (q31_t)0x94fd3ab1,
+  (q31_t)0x46366978, (q31_t)0x94f9c83f, (q31_t)0x4631287a, (q31_t)0x94f6560f, (q31_t)0x462be751, (q31_t)0x94f2e421,
+    (q31_t)0x4626a5fd, (q31_t)0x94ef7275,
+  (q31_t)0x4621647d, (q31_t)0x94ec010b, (q31_t)0x461c22d2, (q31_t)0x94e88fe3, (q31_t)0x4616e0fc, (q31_t)0x94e51efd,
+    (q31_t)0x46119efa, (q31_t)0x94e1ae59,
+  (q31_t)0x460c5cce, (q31_t)0x94de3df8, (q31_t)0x46071a76, (q31_t)0x94dacdd8, (q31_t)0x4601d7f3, (q31_t)0x94d75dfa,
+    (q31_t)0x45fc9545, (q31_t)0x94d3ee5f,
+  (q31_t)0x45f7526b, (q31_t)0x94d07f05, (q31_t)0x45f20f67, (q31_t)0x94cd0fee, (q31_t)0x45eccc37, (q31_t)0x94c9a119,
+    (q31_t)0x45e788dc, (q31_t)0x94c63286,
+  (q31_t)0x45e24556, (q31_t)0x94c2c435, (q31_t)0x45dd01a5, (q31_t)0x94bf5627, (q31_t)0x45d7bdc9, (q31_t)0x94bbe85a,
+    (q31_t)0x45d279c2, (q31_t)0x94b87ad0,
+  (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x45c7f132, (q31_t)0x94b1a081, (q31_t)0x45c2acaa, (q31_t)0x94ae33be,
+    (q31_t)0x45bd67f6, (q31_t)0x94aac73c,
+  (q31_t)0x45b82318, (q31_t)0x94a75afd, (q31_t)0x45b2de0e, (q31_t)0x94a3eeff, (q31_t)0x45ad98da, (q31_t)0x94a08344,
+    (q31_t)0x45a8537a, (q31_t)0x949d17cc,
+  (q31_t)0x45a30df0, (q31_t)0x9499ac95, (q31_t)0x459dc83b, (q31_t)0x949641a1, (q31_t)0x4598825a, (q31_t)0x9492d6ef,
+    (q31_t)0x45933c4f, (q31_t)0x948f6c7f,
+  (q31_t)0x458df619, (q31_t)0x948c0252, (q31_t)0x4588afb8, (q31_t)0x94889867, (q31_t)0x4583692c, (q31_t)0x94852ebe,
+    (q31_t)0x457e2275, (q31_t)0x9481c557,
+  (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x45739487, (q31_t)0x947af351, (q31_t)0x456e4d4f, (q31_t)0x94778ab1,
+    (q31_t)0x456905ed, (q31_t)0x94742254,
+  (q31_t)0x4563be60, (q31_t)0x9470ba39, (q31_t)0x455e76a8, (q31_t)0x946d5260, (q31_t)0x45592ec6, (q31_t)0x9469eaca,
+    (q31_t)0x4553e6b8, (q31_t)0x94668376,
+  (q31_t)0x454e9e80, (q31_t)0x94631c65, (q31_t)0x4549561d, (q31_t)0x945fb596, (q31_t)0x45440d90, (q31_t)0x945c4f09,
+    (q31_t)0x453ec4d7, (q31_t)0x9458e8bf,
+  (q31_t)0x45397bf4, (q31_t)0x945582b7, (q31_t)0x453432e6, (q31_t)0x94521cf1, (q31_t)0x452ee9ae, (q31_t)0x944eb76e,
+    (q31_t)0x4529a04b, (q31_t)0x944b522d,
+  (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x451f0d04, (q31_t)0x94448873, (q31_t)0x4519c321, (q31_t)0x944123fa,
+    (q31_t)0x45147913, (q31_t)0x943dbfc3,
+  (q31_t)0x450f2edb, (q31_t)0x943a5bcf, (q31_t)0x4509e478, (q31_t)0x9436f81d, (q31_t)0x450499eb, (q31_t)0x943394ad,
+    (q31_t)0x44ff4f32, (q31_t)0x94303180,
+  (q31_t)0x44fa0450, (q31_t)0x942cce96, (q31_t)0x44f4b943, (q31_t)0x94296bee, (q31_t)0x44ef6e0b, (q31_t)0x94260989,
+    (q31_t)0x44ea22a9, (q31_t)0x9422a766,
+  (q31_t)0x44e4d71c, (q31_t)0x941f4585, (q31_t)0x44df8b64, (q31_t)0x941be3e8, (q31_t)0x44da3f83, (q31_t)0x9418828c,
+    (q31_t)0x44d4f376, (q31_t)0x94152174,
+  (q31_t)0x44cfa740, (q31_t)0x9411c09e, (q31_t)0x44ca5adf, (q31_t)0x940e600a, (q31_t)0x44c50e53, (q31_t)0x940affb9,
+    (q31_t)0x44bfc19d, (q31_t)0x94079fab,
+  (q31_t)0x44ba74bd, (q31_t)0x94043fdf, (q31_t)0x44b527b2, (q31_t)0x9400e056, (q31_t)0x44afda7d, (q31_t)0x93fd810f,
+    (q31_t)0x44aa8d1d, (q31_t)0x93fa220b,
+  (q31_t)0x44a53f93, (q31_t)0x93f6c34a, (q31_t)0x449ff1df, (q31_t)0x93f364cb, (q31_t)0x449aa400, (q31_t)0x93f0068f,
+    (q31_t)0x449555f7, (q31_t)0x93eca896,
+  (q31_t)0x449007c4, (q31_t)0x93e94adf, (q31_t)0x448ab967, (q31_t)0x93e5ed6b, (q31_t)0x44856adf, (q31_t)0x93e2903a,
+    (q31_t)0x44801c2d, (q31_t)0x93df334c,
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+    (q31_t)0x446adfbe, (q31_t)0x93d1c22c,
+  (q31_t)0x44659039, (q31_t)0x93ce668b, (q31_t)0x44604089, (q31_t)0x93cb0b2d, (q31_t)0x445af0b0, (q31_t)0x93c7b011,
+    (q31_t)0x4455a0ac, (q31_t)0x93c45539,
+  (q31_t)0x4450507e, (q31_t)0x93c0faa3, (q31_t)0x444b0026, (q31_t)0x93bda04f, (q31_t)0x4445afa4, (q31_t)0x93ba463f,
+    (q31_t)0x44405ef8, (q31_t)0x93b6ec71,
+  (q31_t)0x443b0e21, (q31_t)0x93b392e6, (q31_t)0x4435bd21, (q31_t)0x93b0399e, (q31_t)0x44306bf6, (q31_t)0x93ace099,
+    (q31_t)0x442b1aa2, (q31_t)0x93a987d6,
+  (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x4420777b, (q31_t)0x93a2d71a, (q31_t)0x441b25a8, (q31_t)0x939f7f20,
+    (q31_t)0x4415d3ab, (q31_t)0x939c2769,
+  (q31_t)0x44108184, (q31_t)0x9398cff5, (q31_t)0x440b2f34, (q31_t)0x939578c3, (q31_t)0x4405dcb9, (q31_t)0x939221d5,
+    (q31_t)0x44008a14, (q31_t)0x938ecb29,
+  (q31_t)0x43fb3746, (q31_t)0x938b74c1, (q31_t)0x43f5e44d, (q31_t)0x93881e9b, (q31_t)0x43f0912b, (q31_t)0x9384c8b8,
+    (q31_t)0x43eb3ddf, (q31_t)0x93817318,
+  (q31_t)0x43e5ea68, (q31_t)0x937e1dbb, (q31_t)0x43e096c8, (q31_t)0x937ac8a1, (q31_t)0x43db42fe, (q31_t)0x937773ca,
+    (q31_t)0x43d5ef0a, (q31_t)0x93741f35,
+  (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x43cb46a5, (q31_t)0x936d76d6, (q31_t)0x43c5f234, (q31_t)0x936a230a,
+    (q31_t)0x43c09d99, (q31_t)0x9366cf82,
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+    (q31_t)0x43ab498a, (q31_t)0x935983ff,
+  (q31_t)0x43a5f41e, (q31_t)0x935631c5, (q31_t)0x43a09e89, (q31_t)0x9352dfcf, (q31_t)0x439b48c9, (q31_t)0x934f8e1c,
+    (q31_t)0x4395f2e0, (q31_t)0x934c3cab,
+  (q31_t)0x43909ccd, (q31_t)0x9348eb7e, (q31_t)0x438b4691, (q31_t)0x93459a94, (q31_t)0x4385f02a, (q31_t)0x934249ed,
+    (q31_t)0x4380999b, (q31_t)0x933ef989,
+  (q31_t)0x437b42e1, (q31_t)0x933ba968, (q31_t)0x4375ebfe, (q31_t)0x9338598a, (q31_t)0x437094f1, (q31_t)0x933509f0,
+    (q31_t)0x436b3dbb, (q31_t)0x9331ba98,
+  (q31_t)0x4365e65b, (q31_t)0x932e6b84, (q31_t)0x43608ed2, (q31_t)0x932b1cb2, (q31_t)0x435b371f, (q31_t)0x9327ce24,
+    (q31_t)0x4355df42, (q31_t)0x93247fd9,
+  (q31_t)0x4350873c, (q31_t)0x932131d1, (q31_t)0x434b2f0c, (q31_t)0x931de40c, (q31_t)0x4345d6b3, (q31_t)0x931a968b,
+    (q31_t)0x43407e31, (q31_t)0x9317494c,
+  (q31_t)0x433b2585, (q31_t)0x9313fc51, (q31_t)0x4335ccaf, (q31_t)0x9310af99, (q31_t)0x433073b0, (q31_t)0x930d6324,
+    (q31_t)0x432b1a87, (q31_t)0x930a16f3,
+  (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x432067ba, (q31_t)0x93037f59, (q31_t)0x431b0e15, (q31_t)0x930033f1,
+    (q31_t)0x4315b447, (q31_t)0x92fce8cc,
+  (q31_t)0x43105a50, (q31_t)0x92f99deb, (q31_t)0x430b002f, (q31_t)0x92f6534c, (q31_t)0x4305a5e5, (q31_t)0x92f308f1,
+    (q31_t)0x43004b71, (q31_t)0x92efbeda,
+  (q31_t)0x42faf0d4, (q31_t)0x92ec7505, (q31_t)0x42f5960e, (q31_t)0x92e92b74, (q31_t)0x42f03b1e, (q31_t)0x92e5e226,
+    (q31_t)0x42eae005, (q31_t)0x92e2991c,
+  (q31_t)0x42e584c3, (q31_t)0x92df5054, (q31_t)0x42e02958, (q31_t)0x92dc07d0, (q31_t)0x42dacdc3, (q31_t)0x92d8bf90,
+    (q31_t)0x42d57205, (q31_t)0x92d57792,
+  (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x42caba0e, (q31_t)0x92cee862, (q31_t)0x42c55dd4, (q31_t)0x92cba12f,
+    (q31_t)0x42c00172, (q31_t)0x92c85a3f,
+  (q31_t)0x42baa4e6, (q31_t)0x92c51392, (q31_t)0x42b54831, (q31_t)0x92c1cd29, (q31_t)0x42afeb53, (q31_t)0x92be8703,
+    (q31_t)0x42aa8e4b, (q31_t)0x92bb4121,
+  (q31_t)0x42a5311b, (q31_t)0x92b7fb82, (q31_t)0x429fd3c1, (q31_t)0x92b4b626, (q31_t)0x429a763f, (q31_t)0x92b1710e,
+    (q31_t)0x42951893, (q31_t)0x92ae2c3a,
+  (q31_t)0x428fbabe, (q31_t)0x92aae7a8, (q31_t)0x428a5cc0, (q31_t)0x92a7a35a, (q31_t)0x4284fe99, (q31_t)0x92a45f50,
+    (q31_t)0x427fa049, (q31_t)0x92a11b89,
+  (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x4274e32e, (q31_t)0x929a94c6, (q31_t)0x426f8463, (q31_t)0x929751c9,
+    (q31_t)0x426a256f, (q31_t)0x92940f10,
+  (q31_t)0x4264c653, (q31_t)0x9290cc9b, (q31_t)0x425f670d, (q31_t)0x928d8a69, (q31_t)0x425a079e, (q31_t)0x928a487a,
+    (q31_t)0x4254a806, (q31_t)0x928706cf,
+  (q31_t)0x424f4845, (q31_t)0x9283c568, (q31_t)0x4249e85c, (q31_t)0x92808444, (q31_t)0x42448849, (q31_t)0x927d4363,
+    (q31_t)0x423f280e, (q31_t)0x927a02c7,
+  (q31_t)0x4239c7aa, (q31_t)0x9276c26d, (q31_t)0x4234671d, (q31_t)0x92738258, (q31_t)0x422f0667, (q31_t)0x92704286,
+    (q31_t)0x4229a588, (q31_t)0x926d02f7,
+  (q31_t)0x42244481, (q31_t)0x9269c3ac, (q31_t)0x421ee350, (q31_t)0x926684a5, (q31_t)0x421981f7, (q31_t)0x926345e1,
+    (q31_t)0x42142075, (q31_t)0x92600761,
+  (q31_t)0x420ebecb, (q31_t)0x925cc924, (q31_t)0x42095cf7, (q31_t)0x92598b2b, (q31_t)0x4203fafb, (q31_t)0x92564d76,
+    (q31_t)0x41fe98d6, (q31_t)0x92531005,
+  (q31_t)0x41f93689, (q31_t)0x924fd2d7, (q31_t)0x41f3d413, (q31_t)0x924c95ec, (q31_t)0x41ee7174, (q31_t)0x92495946,
+    (q31_t)0x41e90eac, (q31_t)0x92461ce3,
+  (q31_t)0x41e3abbc, (q31_t)0x9242e0c4, (q31_t)0x41de48a3, (q31_t)0x923fa4e8, (q31_t)0x41d8e561, (q31_t)0x923c6950,
+    (q31_t)0x41d381f7, (q31_t)0x92392dfc,
+  (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x41c8baa9, (q31_t)0x9232b81f, (q31_t)0x41c356c5, (q31_t)0x922f7d96,
+    (q31_t)0x41bdf2b9, (q31_t)0x922c4351,
+  (q31_t)0x41b88e84, (q31_t)0x9229094f, (q31_t)0x41b32a26, (q31_t)0x9225cf91, (q31_t)0x41adc5a0, (q31_t)0x92229617,
+    (q31_t)0x41a860f1, (q31_t)0x921f5ce1,
+  (q31_t)0x41a2fc1a, (q31_t)0x921c23ef, (q31_t)0x419d971b, (q31_t)0x9218eb40, (q31_t)0x419831f3, (q31_t)0x9215b2d5,
+    (q31_t)0x4192cca2, (q31_t)0x92127aae,
+  (q31_t)0x418d6729, (q31_t)0x920f42cb, (q31_t)0x41880188, (q31_t)0x920c0b2c, (q31_t)0x41829bbe, (q31_t)0x9208d3d0,
+    (q31_t)0x417d35cb, (q31_t)0x92059cb8,
+  (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x4172696e, (q31_t)0x91ff2f54, (q31_t)0x416d0302, (q31_t)0x91fbf908,
+    (q31_t)0x41679c6f, (q31_t)0x91f8c300,
+  (q31_t)0x416235b2, (q31_t)0x91f58d3b, (q31_t)0x415ccece, (q31_t)0x91f257bb, (q31_t)0x415767c1, (q31_t)0x91ef227e,
+    (q31_t)0x4152008c, (q31_t)0x91ebed85,
+  (q31_t)0x414c992f, (q31_t)0x91e8b8d0, (q31_t)0x414731a9, (q31_t)0x91e5845f, (q31_t)0x4141c9fb, (q31_t)0x91e25032,
+    (q31_t)0x413c6225, (q31_t)0x91df1c49,
+  (q31_t)0x4136fa27, (q31_t)0x91dbe8a4, (q31_t)0x41319200, (q31_t)0x91d8b542, (q31_t)0x412c29b1, (q31_t)0x91d58225,
+    (q31_t)0x4126c13a, (q31_t)0x91d24f4c,
+  (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x411befd3, (q31_t)0x91cbea65, (q31_t)0x411686e4, (q31_t)0x91c8b857,
+    (q31_t)0x41111dcc, (q31_t)0x91c5868e,
+  (q31_t)0x410bb48c, (q31_t)0x91c25508, (q31_t)0x41064b24, (q31_t)0x91bf23c7, (q31_t)0x4100e194, (q31_t)0x91bbf2c9,
+    (q31_t)0x40fb77dc, (q31_t)0x91b8c210,
+  (q31_t)0x40f60dfb, (q31_t)0x91b5919a, (q31_t)0x40f0a3f3, (q31_t)0x91b26169, (q31_t)0x40eb39c3, (q31_t)0x91af317c,
+    (q31_t)0x40e5cf6a, (q31_t)0x91ac01d2,
+  (q31_t)0x40e064ea, (q31_t)0x91a8d26d, (q31_t)0x40dafa41, (q31_t)0x91a5a34c, (q31_t)0x40d58f71, (q31_t)0x91a2746f,
+    (q31_t)0x40d02478, (q31_t)0x919f45d6,
+  (q31_t)0x40cab958, (q31_t)0x919c1781, (q31_t)0x40c54e0f, (q31_t)0x9198e970, (q31_t)0x40bfe29f, (q31_t)0x9195bba3,
+    (q31_t)0x40ba7706, (q31_t)0x91928e1a,
+  (q31_t)0x40b50b46, (q31_t)0x918f60d6, (q31_t)0x40af9f5e, (q31_t)0x918c33d5, (q31_t)0x40aa334e, (q31_t)0x91890719,
+    (q31_t)0x40a4c716, (q31_t)0x9185daa1,
+  (q31_t)0x409f5ab6, (q31_t)0x9182ae6d, (q31_t)0x4099ee2e, (q31_t)0x917f827d, (q31_t)0x4094817f, (q31_t)0x917c56d1,
+    (q31_t)0x408f14a7, (q31_t)0x91792b6a,
+  (q31_t)0x4089a7a8, (q31_t)0x91760047, (q31_t)0x40843a81, (q31_t)0x9172d567, (q31_t)0x407ecd32, (q31_t)0x916faacc,
+    (q31_t)0x40795fbc, (q31_t)0x916c8076,
+  (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x406e8457, (q31_t)0x91662c95, (q31_t)0x40691669, (q31_t)0x9163030b,
+    (q31_t)0x4063a854, (q31_t)0x915fd9c5,
+  (q31_t)0x405e3a16, (q31_t)0x915cb0c3, (q31_t)0x4058cbb1, (q31_t)0x91598806, (q31_t)0x40535d24, (q31_t)0x91565f8d,
+    (q31_t)0x404dee70, (q31_t)0x91533758,
+  (q31_t)0x40487f94, (q31_t)0x91500f67, (q31_t)0x40431090, (q31_t)0x914ce7bb, (q31_t)0x403da165, (q31_t)0x9149c053,
+    (q31_t)0x40383212, (q31_t)0x9146992f,
+  (q31_t)0x4032c297, (q31_t)0x91437250, (q31_t)0x402d52f5, (q31_t)0x91404bb5, (q31_t)0x4027e32b, (q31_t)0x913d255e,
+    (q31_t)0x4022733a, (q31_t)0x9139ff4b,
+  (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x401792e0, (q31_t)0x9133b3f3, (q31_t)0x40122278, (q31_t)0x91308eae,
+    (q31_t)0x400cb1e9, (q31_t)0x912d69ad,
+  (q31_t)0x40074132, (q31_t)0x912a44f0, (q31_t)0x4001d053, (q31_t)0x91272078, (q31_t)0x3ffc5f4d, (q31_t)0x9123fc44,
+    (q31_t)0x3ff6ee1f, (q31_t)0x9120d854,
+  (q31_t)0x3ff17cca, (q31_t)0x911db4a9, (q31_t)0x3fec0b4e, (q31_t)0x911a9142, (q31_t)0x3fe699aa, (q31_t)0x91176e1f,
+    (q31_t)0x3fe127df, (q31_t)0x91144b41,
+  (q31_t)0x3fdbb5ec, (q31_t)0x911128a8, (q31_t)0x3fd643d2, (q31_t)0x910e0653, (q31_t)0x3fd0d191, (q31_t)0x910ae442,
+    (q31_t)0x3fcb5f28, (q31_t)0x9107c276,
+  (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3fc079e0, (q31_t)0x91017faa, (q31_t)0x3fbb0702, (q31_t)0x90fe5eab,
+    (q31_t)0x3fb593fb, (q31_t)0x90fb3df1,
+  (q31_t)0x3fb020ce, (q31_t)0x90f81d7b, (q31_t)0x3faaad79, (q31_t)0x90f4fd4a, (q31_t)0x3fa539fd, (q31_t)0x90f1dd5d,
+    (q31_t)0x3f9fc65a, (q31_t)0x90eebdb4,
+  (q31_t)0x3f9a5290, (q31_t)0x90eb9e50, (q31_t)0x3f94de9e, (q31_t)0x90e87f31, (q31_t)0x3f8f6a85, (q31_t)0x90e56056,
+    (q31_t)0x3f89f645, (q31_t)0x90e241bf,
+  (q31_t)0x3f8481dd, (q31_t)0x90df236e, (q31_t)0x3f7f0d4f, (q31_t)0x90dc0560, (q31_t)0x3f799899, (q31_t)0x90d8e798,
+    (q31_t)0x3f7423bc, (q31_t)0x90d5ca13,
+  (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4, (q31_t)0x3f69398d, (q31_t)0x90cf8fd9, (q31_t)0x3f63c43b, (q31_t)0x90cc7322,
+    (q31_t)0x3f5e4ec2, (q31_t)0x90c956b1,
+  (q31_t)0x3f58d921, (q31_t)0x90c63a83, (q31_t)0x3f53635a, (q31_t)0x90c31e9b, (q31_t)0x3f4ded6b, (q31_t)0x90c002f7,
+    (q31_t)0x3f487755, (q31_t)0x90bce797,
+  (q31_t)0x3f430119, (q31_t)0x90b9cc7d, (q31_t)0x3f3d8ab5, (q31_t)0x90b6b1a6, (q31_t)0x3f38142a, (q31_t)0x90b39715,
+    (q31_t)0x3f329d79, (q31_t)0x90b07cc8,
+  (q31_t)0x3f2d26a0, (q31_t)0x90ad62c0, (q31_t)0x3f27afa1, (q31_t)0x90aa48fd, (q31_t)0x3f22387a, (q31_t)0x90a72f7e,
+    (q31_t)0x3f1cc12c, (q31_t)0x90a41644,
+  (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3f11d21d, (q31_t)0x909de49e, (q31_t)0x3f0c5a5a, (q31_t)0x909acc32,
+    (q31_t)0x3f06e271, (q31_t)0x9097b40a,
+  (q31_t)0x3f016a61, (q31_t)0x90949c28, (q31_t)0x3efbf22a, (q31_t)0x9091848a, (q31_t)0x3ef679cc, (q31_t)0x908e6d31,
+    (q31_t)0x3ef10148, (q31_t)0x908b561c,
+  (q31_t)0x3eeb889c, (q31_t)0x90883f4d, (q31_t)0x3ee60fca, (q31_t)0x908528c2, (q31_t)0x3ee096d1, (q31_t)0x9082127c,
+    (q31_t)0x3edb1db1, (q31_t)0x907efc7a,
+  (q31_t)0x3ed5a46b, (q31_t)0x907be6be, (q31_t)0x3ed02afd, (q31_t)0x9078d146, (q31_t)0x3ecab169, (q31_t)0x9075bc13,
+    (q31_t)0x3ec537ae, (q31_t)0x9072a725,
+  (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3eba43c4, (q31_t)0x906c7e17, (q31_t)0x3eb4c995, (q31_t)0x906969f8,
+    (q31_t)0x3eaf4f40, (q31_t)0x9066561d,
+  (q31_t)0x3ea9d4c3, (q31_t)0x90634287, (q31_t)0x3ea45a21, (q31_t)0x90602f35, (q31_t)0x3e9edf57, (q31_t)0x905d1c29,
+    (q31_t)0x3e996467, (q31_t)0x905a0962,
+  (q31_t)0x3e93e950, (q31_t)0x9056f6df, (q31_t)0x3e8e6e12, (q31_t)0x9053e4a1, (q31_t)0x3e88f2ae, (q31_t)0x9050d2a9,
+    (q31_t)0x3e837724, (q31_t)0x904dc0f5,
+  (q31_t)0x3e7dfb73, (q31_t)0x904aaf86, (q31_t)0x3e787f9b, (q31_t)0x90479e5c, (q31_t)0x3e73039d, (q31_t)0x90448d76,
+    (q31_t)0x3e6d8778, (q31_t)0x90417cd6,
+  (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e628ebb, (q31_t)0x903b5c64, (q31_t)0x3e5d1222, (q31_t)0x90384c93,
+    (q31_t)0x3e579564, (q31_t)0x90353d06,
+  (q31_t)0x3e52187f, (q31_t)0x90322dbf, (q31_t)0x3e4c9b73, (q31_t)0x902f1ebc, (q31_t)0x3e471e41, (q31_t)0x902c0fff,
+    (q31_t)0x3e41a0e8, (q31_t)0x90290186,
+  (q31_t)0x3e3c2369, (q31_t)0x9025f352, (q31_t)0x3e36a5c4, (q31_t)0x9022e564, (q31_t)0x3e3127f9, (q31_t)0x901fd7ba,
+    (q31_t)0x3e2baa07, (q31_t)0x901cca55,
+  (q31_t)0x3e262bee, (q31_t)0x9019bd36, (q31_t)0x3e20adaf, (q31_t)0x9016b05b, (q31_t)0x3e1b2f4a, (q31_t)0x9013a3c5,
+    (q31_t)0x3e15b0bf, (q31_t)0x90109775,
+  (q31_t)0x3e10320d, (q31_t)0x900d8b69, (q31_t)0x3e0ab336, (q31_t)0x900a7fa3, (q31_t)0x3e053437, (q31_t)0x90077422,
+    (q31_t)0x3dffb513, (q31_t)0x900468e5,
+  (q31_t)0x3dfa35c8, (q31_t)0x90015dee, (q31_t)0x3df4b657, (q31_t)0x8ffe533c, (q31_t)0x3def36c0, (q31_t)0x8ffb48cf,
+    (q31_t)0x3de9b703, (q31_t)0x8ff83ea7,
+  (q31_t)0x3de4371f, (q31_t)0x8ff534c4, (q31_t)0x3ddeb716, (q31_t)0x8ff22b26, (q31_t)0x3dd936e6, (q31_t)0x8fef21ce,
+    (q31_t)0x3dd3b690, (q31_t)0x8fec18ba,
+  (q31_t)0x3dce3614, (q31_t)0x8fe90fec, (q31_t)0x3dc8b571, (q31_t)0x8fe60763, (q31_t)0x3dc334a9, (q31_t)0x8fe2ff1f,
+    (q31_t)0x3dbdb3ba, (q31_t)0x8fdff720,
+  (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3db2b16b, (q31_t)0x8fd9e7f2, (q31_t)0x3dad300b, (q31_t)0x8fd6e0c2,
+    (q31_t)0x3da7ae84, (q31_t)0x8fd3d9d8,
+  (q31_t)0x3da22cd7, (q31_t)0x8fd0d333, (q31_t)0x3d9cab04, (q31_t)0x8fcdccd3, (q31_t)0x3d97290b, (q31_t)0x8fcac6b9,
+    (q31_t)0x3d91a6ed, (q31_t)0x8fc7c0e3,
+  (q31_t)0x3d8c24a8, (q31_t)0x8fc4bb53, (q31_t)0x3d86a23d, (q31_t)0x8fc1b608, (q31_t)0x3d811fac, (q31_t)0x8fbeb103,
+    (q31_t)0x3d7b9cf6, (q31_t)0x8fbbac42,
+  (q31_t)0x3d761a19, (q31_t)0x8fb8a7c7, (q31_t)0x3d709717, (q31_t)0x8fb5a391, (q31_t)0x3d6b13ee, (q31_t)0x8fb29fa0,
+    (q31_t)0x3d6590a0, (q31_t)0x8faf9bf5,
+  (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d5a8992, (q31_t)0x8fa9956e, (q31_t)0x3d5505d2, (q31_t)0x8fa69293,
+    (q31_t)0x3d4f81ec, (q31_t)0x8fa38ffc,
+  (q31_t)0x3d49fde1, (q31_t)0x8fa08dab, (q31_t)0x3d4479b0, (q31_t)0x8f9d8ba0, (q31_t)0x3d3ef559, (q31_t)0x8f9a89da,
+    (q31_t)0x3d3970dc, (q31_t)0x8f978859,
+  (q31_t)0x3d33ec39, (q31_t)0x8f94871d, (q31_t)0x3d2e6771, (q31_t)0x8f918627, (q31_t)0x3d28e282, (q31_t)0x8f8e8576,
+    (q31_t)0x3d235d6f, (q31_t)0x8f8b850a,
+  (q31_t)0x3d1dd835, (q31_t)0x8f8884e4, (q31_t)0x3d1852d6, (q31_t)0x8f858503, (q31_t)0x3d12cd51, (q31_t)0x8f828568,
+    (q31_t)0x3d0d47a6, (q31_t)0x8f7f8612,
+  (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3d023be0, (q31_t)0x8f798836, (q31_t)0x3cfcb5c4, (q31_t)0x8f7689b0,
+    (q31_t)0x3cf72f83, (q31_t)0x8f738b70,
+  (q31_t)0x3cf1a91c, (q31_t)0x8f708d75, (q31_t)0x3cec2290, (q31_t)0x8f6d8fbf, (q31_t)0x3ce69bde, (q31_t)0x8f6a924f,
+    (q31_t)0x3ce11507, (q31_t)0x8f679525,
+  (q31_t)0x3cdb8e09, (q31_t)0x8f649840, (q31_t)0x3cd606e7, (q31_t)0x8f619ba0, (q31_t)0x3cd07f9f, (q31_t)0x8f5e9f46,
+    (q31_t)0x3ccaf831, (q31_t)0x8f5ba331,
+  (q31_t)0x3cc5709e, (q31_t)0x8f58a761, (q31_t)0x3cbfe8e5, (q31_t)0x8f55abd8, (q31_t)0x3cba6107, (q31_t)0x8f52b093,
+    (q31_t)0x3cb4d904, (q31_t)0x8f4fb595,
+  (q31_t)0x3caf50da, (q31_t)0x8f4cbadb, (q31_t)0x3ca9c88c, (q31_t)0x8f49c067, (q31_t)0x3ca44018, (q31_t)0x8f46c639,
+    (q31_t)0x3c9eb77f, (q31_t)0x8f43cc50,
+  (q31_t)0x3c992ec0, (q31_t)0x8f40d2ad, (q31_t)0x3c93a5dc, (q31_t)0x8f3dd950, (q31_t)0x3c8e1cd3, (q31_t)0x8f3ae038,
+    (q31_t)0x3c8893a4, (q31_t)0x8f37e765,
+  (q31_t)0x3c830a50, (q31_t)0x8f34eed8, (q31_t)0x3c7d80d6, (q31_t)0x8f31f691, (q31_t)0x3c77f737, (q31_t)0x8f2efe8f,
+    (q31_t)0x3c726d73, (q31_t)0x8f2c06d3,
+  (q31_t)0x3c6ce38a, (q31_t)0x8f290f5c, (q31_t)0x3c67597b, (q31_t)0x8f26182b, (q31_t)0x3c61cf48, (q31_t)0x8f232140,
+    (q31_t)0x3c5c44ee, (q31_t)0x8f202a9a,
+  (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3c512fcc, (q31_t)0x8f1a3e1f, (q31_t)0x3c4ba504, (q31_t)0x8f17484b,
+    (q31_t)0x3c461a16, (q31_t)0x8f1452bb,
+  (q31_t)0x3c408f03, (q31_t)0x8f115d72, (q31_t)0x3c3b03ca, (q31_t)0x8f0e686e, (q31_t)0x3c35786d, (q31_t)0x8f0b73b0,
+    (q31_t)0x3c2fecea, (q31_t)0x8f087f37,
+  (q31_t)0x3c2a6142, (q31_t)0x8f058b04, (q31_t)0x3c24d575, (q31_t)0x8f029717, (q31_t)0x3c1f4983, (q31_t)0x8effa370,
+    (q31_t)0x3c19bd6c, (q31_t)0x8efcb00e,
+  (q31_t)0x3c143130, (q31_t)0x8ef9bcf2, (q31_t)0x3c0ea4cf, (q31_t)0x8ef6ca1c, (q31_t)0x3c091849, (q31_t)0x8ef3d78b,
+    (q31_t)0x3c038b9e, (q31_t)0x8ef0e540,
+  (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3bf871d8, (q31_t)0x8eeb017c, (q31_t)0x3bf2e4be, (q31_t)0x8ee81002,
+    (q31_t)0x3bed577e, (q31_t)0x8ee51ece,
+  (q31_t)0x3be7ca1a, (q31_t)0x8ee22de0, (q31_t)0x3be23c91, (q31_t)0x8edf3d38, (q31_t)0x3bdcaee3, (q31_t)0x8edc4cd5,
+    (q31_t)0x3bd72110, (q31_t)0x8ed95cb8,
+  (q31_t)0x3bd19318, (q31_t)0x8ed66ce1, (q31_t)0x3bcc04fb, (q31_t)0x8ed37d50, (q31_t)0x3bc676b9, (q31_t)0x8ed08e05,
+    (q31_t)0x3bc0e853, (q31_t)0x8ecd9eff,
+  (q31_t)0x3bbb59c7, (q31_t)0x8ecab040, (q31_t)0x3bb5cb17, (q31_t)0x8ec7c1c6, (q31_t)0x3bb03c42, (q31_t)0x8ec4d392,
+    (q31_t)0x3baaad48, (q31_t)0x8ec1e5a4,
+  (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b9f8ee5, (q31_t)0x8ebc0a99, (q31_t)0x3b99ff7d, (q31_t)0x8eb91d7c,
+    (q31_t)0x3b946ff0, (q31_t)0x8eb630a6,
+  (q31_t)0x3b8ee03e, (q31_t)0x8eb34415, (q31_t)0x3b895068, (q31_t)0x8eb057ca, (q31_t)0x3b83c06c, (q31_t)0x8ead6bc5,
+    (q31_t)0x3b7e304c, (q31_t)0x8eaa8006,
+  (q31_t)0x3b78a007, (q31_t)0x8ea7948c, (q31_t)0x3b730f9e, (q31_t)0x8ea4a959, (q31_t)0x3b6d7f10, (q31_t)0x8ea1be6c,
+    (q31_t)0x3b67ee5d, (q31_t)0x8e9ed3c4,
+  (q31_t)0x3b625d86, (q31_t)0x8e9be963, (q31_t)0x3b5ccc8a, (q31_t)0x8e98ff47, (q31_t)0x3b573b69, (q31_t)0x8e961571,
+    (q31_t)0x3b51aa24, (q31_t)0x8e932be2,
+  (q31_t)0x3b4c18ba, (q31_t)0x8e904298, (q31_t)0x3b46872c, (q31_t)0x8e8d5994, (q31_t)0x3b40f579, (q31_t)0x8e8a70d7,
+    (q31_t)0x3b3b63a1, (q31_t)0x8e87885f,
+  (q31_t)0x3b35d1a5, (q31_t)0x8e84a02d, (q31_t)0x3b303f84, (q31_t)0x8e81b841, (q31_t)0x3b2aad3f, (q31_t)0x8e7ed09b,
+    (q31_t)0x3b251ad6, (q31_t)0x8e7be93c,
+  (q31_t)0x3b1f8848, (q31_t)0x8e790222, (q31_t)0x3b19f595, (q31_t)0x8e761b4e, (q31_t)0x3b1462be, (q31_t)0x8e7334c1,
+    (q31_t)0x3b0ecfc3, (q31_t)0x8e704e79,
+  (q31_t)0x3b093ca3, (q31_t)0x8e6d6877, (q31_t)0x3b03a95e, (q31_t)0x8e6a82bc, (q31_t)0x3afe15f6, (q31_t)0x8e679d47,
+    (q31_t)0x3af88269, (q31_t)0x8e64b817,
+  (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x3aed5ae1, (q31_t)0x8e5eee8b, (q31_t)0x3ae7c6e7, (q31_t)0x8e5c0a2e,
+    (q31_t)0x3ae232c9, (q31_t)0x8e592617,
+  (q31_t)0x3adc9e86, (q31_t)0x8e564246, (q31_t)0x3ad70a1f, (q31_t)0x8e535ebb, (q31_t)0x3ad17593, (q31_t)0x8e507b76,
+    (q31_t)0x3acbe0e3, (q31_t)0x8e4d9878,
+  (q31_t)0x3ac64c0f, (q31_t)0x8e4ab5bf, (q31_t)0x3ac0b717, (q31_t)0x8e47d34d, (q31_t)0x3abb21fb, (q31_t)0x8e44f121,
+    (q31_t)0x3ab58cba, (q31_t)0x8e420f3b,
+  (q31_t)0x3aaff755, (q31_t)0x8e3f2d9b, (q31_t)0x3aaa61cc, (q31_t)0x8e3c4c41, (q31_t)0x3aa4cc1e, (q31_t)0x8e396b2e,
+    (q31_t)0x3a9f364d, (q31_t)0x8e368a61,
+  (q31_t)0x3a99a057, (q31_t)0x8e33a9da, (q31_t)0x3a940a3e, (q31_t)0x8e30c999, (q31_t)0x3a8e7400, (q31_t)0x8e2de99e,
+    (q31_t)0x3a88dd9d, (q31_t)0x8e2b09e9,
+  (q31_t)0x3a834717, (q31_t)0x8e282a7b, (q31_t)0x3a7db06d, (q31_t)0x8e254b53, (q31_t)0x3a78199f, (q31_t)0x8e226c71,
+    (q31_t)0x3a7282ac, (q31_t)0x8e1f8dd6,
+  (q31_t)0x3a6ceb96, (q31_t)0x8e1caf80, (q31_t)0x3a67545b, (q31_t)0x8e19d171, (q31_t)0x3a61bcfd, (q31_t)0x8e16f3a9,
+    (q31_t)0x3a5c257a, (q31_t)0x8e141626,
+  (q31_t)0x3a568dd4, (q31_t)0x8e1138ea, (q31_t)0x3a50f609, (q31_t)0x8e0e5bf4, (q31_t)0x3a4b5e1b, (q31_t)0x8e0b7f44,
+    (q31_t)0x3a45c608, (q31_t)0x8e08a2db,
+  (q31_t)0x3a402dd2, (q31_t)0x8e05c6b7, (q31_t)0x3a3a9577, (q31_t)0x8e02eadb, (q31_t)0x3a34fcf9, (q31_t)0x8e000f44,
+    (q31_t)0x3a2f6457, (q31_t)0x8dfd33f4,
+  (q31_t)0x3a29cb91, (q31_t)0x8dfa58ea, (q31_t)0x3a2432a7, (q31_t)0x8df77e27, (q31_t)0x3a1e9999, (q31_t)0x8df4a3a9,
+    (q31_t)0x3a190068, (q31_t)0x8df1c973,
+  (q31_t)0x3a136712, (q31_t)0x8deeef82, (q31_t)0x3a0dcd99, (q31_t)0x8dec15d8, (q31_t)0x3a0833fc, (q31_t)0x8de93c74,
+    (q31_t)0x3a029a3b, (q31_t)0x8de66357,
+  (q31_t)0x39fd0056, (q31_t)0x8de38a80, (q31_t)0x39f7664e, (q31_t)0x8de0b1ef, (q31_t)0x39f1cc21, (q31_t)0x8dddd9a5,
+    (q31_t)0x39ec31d1, (q31_t)0x8ddb01a1,
+  (q31_t)0x39e6975e, (q31_t)0x8dd829e4, (q31_t)0x39e0fcc6, (q31_t)0x8dd5526d, (q31_t)0x39db620b, (q31_t)0x8dd27b3c,
+    (q31_t)0x39d5c72c, (q31_t)0x8dcfa452,
+  (q31_t)0x39d02c2a, (q31_t)0x8dcccdaf, (q31_t)0x39ca9104, (q31_t)0x8dc9f751, (q31_t)0x39c4f5ba, (q31_t)0x8dc7213b,
+    (q31_t)0x39bf5a4d, (q31_t)0x8dc44b6a,
+  (q31_t)0x39b9bebc, (q31_t)0x8dc175e0, (q31_t)0x39b42307, (q31_t)0x8dbea09d, (q31_t)0x39ae872f, (q31_t)0x8dbbcba0,
+    (q31_t)0x39a8eb33, (q31_t)0x8db8f6ea,
+  (q31_t)0x39a34f13, (q31_t)0x8db6227a, (q31_t)0x399db2d0, (q31_t)0x8db34e50, (q31_t)0x3998166a, (q31_t)0x8db07a6d,
+    (q31_t)0x399279e0, (q31_t)0x8dada6d1,
+  (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x39874061, (q31_t)0x8da8006c, (q31_t)0x3981a36d, (q31_t)0x8da52da3,
+    (q31_t)0x397c0655, (q31_t)0x8da25b21,
+  (q31_t)0x39766919, (q31_t)0x8d9f88e5, (q31_t)0x3970cbba, (q31_t)0x8d9cb6f0, (q31_t)0x396b2e38, (q31_t)0x8d99e541,
+    (q31_t)0x39659092, (q31_t)0x8d9713d9,
+  (q31_t)0x395ff2c9, (q31_t)0x8d9442b8, (q31_t)0x395a54dd, (q31_t)0x8d9171dd, (q31_t)0x3954b6cd, (q31_t)0x8d8ea148,
+    (q31_t)0x394f1899, (q31_t)0x8d8bd0fb,
+  (q31_t)0x39497a43, (q31_t)0x8d8900f3, (q31_t)0x3943dbc9, (q31_t)0x8d863133, (q31_t)0x393e3d2c, (q31_t)0x8d8361b9,
+    (q31_t)0x39389e6b, (q31_t)0x8d809286,
+  (q31_t)0x3932ff87, (q31_t)0x8d7dc399, (q31_t)0x392d6080, (q31_t)0x8d7af4f3, (q31_t)0x3927c155, (q31_t)0x8d782694,
+    (q31_t)0x39222208, (q31_t)0x8d75587b,
+  (q31_t)0x391c8297, (q31_t)0x8d728aa9, (q31_t)0x3916e303, (q31_t)0x8d6fbd1d, (q31_t)0x3911434b, (q31_t)0x8d6cefd9,
+    (q31_t)0x390ba371, (q31_t)0x8d6a22db,
+  (q31_t)0x39060373, (q31_t)0x8d675623, (q31_t)0x39006352, (q31_t)0x8d6489b3, (q31_t)0x38fac30e, (q31_t)0x8d61bd89,
+    (q31_t)0x38f522a6, (q31_t)0x8d5ef1a5,
+  (q31_t)0x38ef821c, (q31_t)0x8d5c2609, (q31_t)0x38e9e16e, (q31_t)0x8d595ab3, (q31_t)0x38e4409e, (q31_t)0x8d568fa4,
+    (q31_t)0x38de9faa, (q31_t)0x8d53c4db,
+  (q31_t)0x38d8fe93, (q31_t)0x8d50fa59, (q31_t)0x38d35d59, (q31_t)0x8d4e301f, (q31_t)0x38cdbbfc, (q31_t)0x8d4b662a,
+    (q31_t)0x38c81a7c, (q31_t)0x8d489c7d,
+  (q31_t)0x38c278d9, (q31_t)0x8d45d316, (q31_t)0x38bcd713, (q31_t)0x8d4309f6, (q31_t)0x38b7352a, (q31_t)0x8d40411d,
+    (q31_t)0x38b1931e, (q31_t)0x8d3d788b,
+  (q31_t)0x38abf0ef, (q31_t)0x8d3ab03f, (q31_t)0x38a64e9d, (q31_t)0x8d37e83a, (q31_t)0x38a0ac29, (q31_t)0x8d35207d,
+    (q31_t)0x389b0991, (q31_t)0x8d325905,
+  (q31_t)0x389566d6, (q31_t)0x8d2f91d5, (q31_t)0x388fc3f8, (q31_t)0x8d2ccaec, (q31_t)0x388a20f8, (q31_t)0x8d2a0449,
+    (q31_t)0x38847dd5, (q31_t)0x8d273ded,
+  (q31_t)0x387eda8e, (q31_t)0x8d2477d8, (q31_t)0x38793725, (q31_t)0x8d21b20a, (q31_t)0x38739399, (q31_t)0x8d1eec83,
+    (q31_t)0x386defeb, (q31_t)0x8d1c2742,
+  (q31_t)0x38684c19, (q31_t)0x8d196249, (q31_t)0x3862a825, (q31_t)0x8d169d96, (q31_t)0x385d040d, (q31_t)0x8d13d92a,
+    (q31_t)0x38575fd4, (q31_t)0x8d111505,
+  (q31_t)0x3851bb77, (q31_t)0x8d0e5127, (q31_t)0x384c16f7, (q31_t)0x8d0b8d90, (q31_t)0x38467255, (q31_t)0x8d08ca40,
+    (q31_t)0x3840cd90, (q31_t)0x8d060737,
+  (q31_t)0x383b28a9, (q31_t)0x8d034474, (q31_t)0x3835839f, (q31_t)0x8d0081f9, (q31_t)0x382fde72, (q31_t)0x8cfdbfc4,
+    (q31_t)0x382a3922, (q31_t)0x8cfafdd7,
+  (q31_t)0x382493b0, (q31_t)0x8cf83c30, (q31_t)0x381eee1b, (q31_t)0x8cf57ad0, (q31_t)0x38194864, (q31_t)0x8cf2b9b8,
+    (q31_t)0x3813a28a, (q31_t)0x8ceff8e6,
+  (q31_t)0x380dfc8d, (q31_t)0x8ced385b, (q31_t)0x3808566e, (q31_t)0x8cea7818, (q31_t)0x3802b02c, (q31_t)0x8ce7b81b,
+    (q31_t)0x37fd09c8, (q31_t)0x8ce4f865,
+  (q31_t)0x37f76341, (q31_t)0x8ce238f6, (q31_t)0x37f1bc97, (q31_t)0x8cdf79ce, (q31_t)0x37ec15cb, (q31_t)0x8cdcbaee,
+    (q31_t)0x37e66edd, (q31_t)0x8cd9fc54,
+  (q31_t)0x37e0c7cc, (q31_t)0x8cd73e01, (q31_t)0x37db2099, (q31_t)0x8cd47ff6, (q31_t)0x37d57943, (q31_t)0x8cd1c231,
+    (q31_t)0x37cfd1cb, (q31_t)0x8ccf04b3,
+  (q31_t)0x37ca2a30, (q31_t)0x8ccc477d, (q31_t)0x37c48273, (q31_t)0x8cc98a8e, (q31_t)0x37beda93, (q31_t)0x8cc6cde5,
+    (q31_t)0x37b93292, (q31_t)0x8cc41184,
+  (q31_t)0x37b38a6d, (q31_t)0x8cc1556a, (q31_t)0x37ade227, (q31_t)0x8cbe9996, (q31_t)0x37a839be, (q31_t)0x8cbbde0a,
+    (q31_t)0x37a29132, (q31_t)0x8cb922c6,
+  (q31_t)0x379ce885, (q31_t)0x8cb667c8, (q31_t)0x37973fb5, (q31_t)0x8cb3ad11, (q31_t)0x379196c3, (q31_t)0x8cb0f2a1,
+    (q31_t)0x378bedae, (q31_t)0x8cae3879,
+  (q31_t)0x37864477, (q31_t)0x8cab7e98, (q31_t)0x37809b1e, (q31_t)0x8ca8c4fd, (q31_t)0x377af1a3, (q31_t)0x8ca60baa,
+    (q31_t)0x37754806, (q31_t)0x8ca3529f,
+  (q31_t)0x376f9e46, (q31_t)0x8ca099da, (q31_t)0x3769f464, (q31_t)0x8c9de15c, (q31_t)0x37644a60, (q31_t)0x8c9b2926,
+    (q31_t)0x375ea03a, (q31_t)0x8c987137,
+  (q31_t)0x3758f5f2, (q31_t)0x8c95b98f, (q31_t)0x37534b87, (q31_t)0x8c93022e, (q31_t)0x374da0fa, (q31_t)0x8c904b14,
+    (q31_t)0x3747f64c, (q31_t)0x8c8d9442,
+  (q31_t)0x37424b7b, (q31_t)0x8c8addb7, (q31_t)0x373ca088, (q31_t)0x8c882773, (q31_t)0x3736f573, (q31_t)0x8c857176,
+    (q31_t)0x37314a3c, (q31_t)0x8c82bbc0,
+  (q31_t)0x372b9ee3, (q31_t)0x8c800652, (q31_t)0x3725f367, (q31_t)0x8c7d512b, (q31_t)0x372047ca, (q31_t)0x8c7a9c4b,
+    (q31_t)0x371a9c0b, (q31_t)0x8c77e7b3,
+  (q31_t)0x3714f02a, (q31_t)0x8c753362, (q31_t)0x370f4427, (q31_t)0x8c727f58, (q31_t)0x37099802, (q31_t)0x8c6fcb95,
+    (q31_t)0x3703ebbb, (q31_t)0x8c6d181a,
+  (q31_t)0x36fe3f52, (q31_t)0x8c6a64e5, (q31_t)0x36f892c7, (q31_t)0x8c67b1f9, (q31_t)0x36f2e61a, (q31_t)0x8c64ff53,
+    (q31_t)0x36ed394b, (q31_t)0x8c624cf5,
+  (q31_t)0x36e78c5b, (q31_t)0x8c5f9ade, (q31_t)0x36e1df48, (q31_t)0x8c5ce90e, (q31_t)0x36dc3214, (q31_t)0x8c5a3786,
+    (q31_t)0x36d684be, (q31_t)0x8c578645,
+  (q31_t)0x36d0d746, (q31_t)0x8c54d54c, (q31_t)0x36cb29ac, (q31_t)0x8c522499, (q31_t)0x36c57bf0, (q31_t)0x8c4f742f,
+    (q31_t)0x36bfce13, (q31_t)0x8c4cc40b,
+  (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x36b471f3, (q31_t)0x8c47649a, (q31_t)0x36aec3b0, (q31_t)0x8c44b54d,
+    (q31_t)0x36a9154c, (q31_t)0x8c420647,
+  (q31_t)0x36a366c6, (q31_t)0x8c3f5788, (q31_t)0x369db81e, (q31_t)0x8c3ca911, (q31_t)0x36980954, (q31_t)0x8c39fae1,
+    (q31_t)0x36925a69, (q31_t)0x8c374cf9,
+  (q31_t)0x368cab5c, (q31_t)0x8c349f58, (q31_t)0x3686fc2e, (q31_t)0x8c31f1ff, (q31_t)0x36814cde, (q31_t)0x8c2f44ed,
+    (q31_t)0x367b9d6c, (q31_t)0x8c2c9822,
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+    (q31_t)0x3664de55, (q31_t)0x8c21e7c2,
+  (q31_t)0x365f2e3b, (q31_t)0x8c1f3c5d, (q31_t)0x36597e00, (q31_t)0x8c1c913f, (q31_t)0x3653cda3, (q31_t)0x8c19e669,
+    (q31_t)0x364e1d25, (q31_t)0x8c173bda,
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+    (q31_t)0x363759de, (q31_t)0x8c0c9469,
+  (q31_t)0x3631a8b8, (q31_t)0x8c09eb40, (q31_t)0x362bf771, (q31_t)0x8c07425e, (q31_t)0x36264609, (q31_t)0x8c0499c4,
+    (q31_t)0x3620947f, (q31_t)0x8c01f171,
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+    (q31_t)0x3609cd0a, (q31_t)0x8bf752f2,
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+    (q31_t)0x35f3037f, (q31_t)0x8becb8ec,
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+    (q31_t)0x35c56a2e, (q31_t)0x8bd7924d,
+  (q31_t)0x35bfb66e, (q31_t)0x8bd4eebc, (q31_t)0x35ba028e, (q31_t)0x8bd24b72, (q31_t)0x35b44e8c, (q31_t)0x8bcfa870,
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+    (q31_t)0x3580f4aa, (q31_t)0x8bb7f9f6,
+  (q31_t)0x357b3f5d, (q31_t)0x8bb559c1, (q31_t)0x357589f0, (q31_t)0x8bb2b9d4, (q31_t)0x356fd461, (q31_t)0x8bb01a2e,
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+    (q31_t)0x34b3251a, (q31_t)0x8b5a2333,
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+    (q31_t)0x34855251, (q31_t)0x8b457a3c,
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+    (q31_t)0x322ec725, (q31_t)0x8a3f5045,
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+    (q31_t)0x3217a748, (q31_t)0x8a357814,
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+    (q31_t)0x31e961c5, (q31_t)0x8a21d554,
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+    (q31_t)0x31d23c1f, (q31_t)0x8a180ac4,
+  (q31_t)0x31cc7269, (q31_t)0x8a1598d6, (q31_t)0x31c6a894, (q31_t)0x8a132731, (q31_t)0x31c0dea1, (q31_t)0x8a10b5d4,
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+    (q31_t)0x31a3eb13, (q31_t)0x8a048348,
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+    (q31_t)0x318cbfad, (q31_t)0x89fac65d,
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+    (q31_t)0x3175925e, (q31_t)0x89f10dff,
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+    (q31_t)0x315e6328, (q31_t)0x89e75a2d,
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+    (q31_t)0x31473209, (q31_t)0x89ddaae9,
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+    (q31_t)0x312fff05, (q31_t)0x89d40033,
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+    (q31_t)0x3118ca1b, (q31_t)0x89ca5a0c,
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+    (q31_t)0x3101934d, (q31_t)0x89c0b873,
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+    (q31_t)0x30ea5a9a, (q31_t)0x89b71b69,
+  (q31_t)0x30e48c22, (q31_t)0x89b4b4dd, (q31_t)0x30debd8c, (q31_t)0x89b24e9a, (q31_t)0x30d8eed8, (q31_t)0x89afe8a0,
+    (q31_t)0x30d32006, (q31_t)0x89ad82ef,
+  (q31_t)0x30cd5115, (q31_t)0x89ab1d87, (q31_t)0x30c78206, (q31_t)0x89a8b868, (q31_t)0x30c1b2da, (q31_t)0x89a65391,
+    (q31_t)0x30bbe38f, (q31_t)0x89a3ef04,
+  (q31_t)0x30b61426, (q31_t)0x89a18ac0, (q31_t)0x30b0449f, (q31_t)0x899f26c5, (q31_t)0x30aa74fa, (q31_t)0x899cc313,
+    (q31_t)0x30a4a537, (q31_t)0x899a5faa,
+  (q31_t)0x309ed556, (q31_t)0x8997fc8a, (q31_t)0x30990557, (q31_t)0x899599b3, (q31_t)0x3093353a, (q31_t)0x89933725,
+    (q31_t)0x308d64ff, (q31_t)0x8990d4e0,
+  (q31_t)0x308794a6, (q31_t)0x898e72e4, (q31_t)0x3081c42f, (q31_t)0x898c1131, (q31_t)0x307bf39b, (q31_t)0x8989afc8,
+    (q31_t)0x307622e8, (q31_t)0x89874ea7,
+  (q31_t)0x30705217, (q31_t)0x8984edcf, (q31_t)0x306a8129, (q31_t)0x89828d41, (q31_t)0x3064b01d, (q31_t)0x89802cfc,
+    (q31_t)0x305edef3, (q31_t)0x897dccff,
+  (q31_t)0x30590dab, (q31_t)0x897b6d4c, (q31_t)0x30533c45, (q31_t)0x89790de2, (q31_t)0x304d6ac1, (q31_t)0x8976aec1,
+    (q31_t)0x30479920, (q31_t)0x89744fe9,
+  (q31_t)0x3041c761, (q31_t)0x8971f15a, (q31_t)0x303bf584, (q31_t)0x896f9315, (q31_t)0x30362389, (q31_t)0x896d3518,
+    (q31_t)0x30305171, (q31_t)0x896ad765,
+  (q31_t)0x302a7f3a, (q31_t)0x896879fb, (q31_t)0x3024ace6, (q31_t)0x89661cda, (q31_t)0x301eda75, (q31_t)0x8963c002,
+    (q31_t)0x301907e6, (q31_t)0x89616373,
+  (q31_t)0x30133539, (q31_t)0x895f072e, (q31_t)0x300d626e, (q31_t)0x895cab31, (q31_t)0x30078f86, (q31_t)0x895a4f7e,
+    (q31_t)0x3001bc80, (q31_t)0x8957f414,
+  (q31_t)0x2ffbe95d, (q31_t)0x895598f3, (q31_t)0x2ff6161c, (q31_t)0x89533e1c, (q31_t)0x2ff042bd, (q31_t)0x8950e38e,
+    (q31_t)0x2fea6f41, (q31_t)0x894e8948,
+  (q31_t)0x2fe49ba7, (q31_t)0x894c2f4c, (q31_t)0x2fdec7f0, (q31_t)0x8949d59a, (q31_t)0x2fd8f41b, (q31_t)0x89477c30,
+    (q31_t)0x2fd32028, (q31_t)0x89452310,
+  (q31_t)0x2fcd4c19, (q31_t)0x8942ca39, (q31_t)0x2fc777eb, (q31_t)0x894071ab, (q31_t)0x2fc1a3a0, (q31_t)0x893e1967,
+    (q31_t)0x2fbbcf38, (q31_t)0x893bc16b,
+  (q31_t)0x2fb5fab2, (q31_t)0x893969b9, (q31_t)0x2fb0260f, (q31_t)0x89371250, (q31_t)0x2faa514f, (q31_t)0x8934bb31,
+    (q31_t)0x2fa47c71, (q31_t)0x8932645b,
+  (q31_t)0x2f9ea775, (q31_t)0x89300dce, (q31_t)0x2f98d25d, (q31_t)0x892db78a, (q31_t)0x2f92fd26, (q31_t)0x892b6190,
+    (q31_t)0x2f8d27d3, (q31_t)0x89290bdf,
+  (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2f817cd4, (q31_t)0x89246159, (q31_t)0x2f7ba729, (q31_t)0x89220c84,
+    (q31_t)0x2f75d160, (q31_t)0x891fb7f8,
+  (q31_t)0x2f6ffb7a, (q31_t)0x891d63b5, (q31_t)0x2f6a2577, (q31_t)0x891b0fbc, (q31_t)0x2f644f56, (q31_t)0x8918bc0c,
+    (q31_t)0x2f5e7919, (q31_t)0x891668a6,
+  (q31_t)0x2f58a2be, (q31_t)0x89141589, (q31_t)0x2f52cc46, (q31_t)0x8911c2b5, (q31_t)0x2f4cf5b0, (q31_t)0x890f702b,
+    (q31_t)0x2f471efe, (q31_t)0x890d1dea,
+  (q31_t)0x2f41482e, (q31_t)0x890acbf2, (q31_t)0x2f3b7141, (q31_t)0x89087a44, (q31_t)0x2f359a37, (q31_t)0x890628df,
+    (q31_t)0x2f2fc310, (q31_t)0x8903d7c4,
+  (q31_t)0x2f29ebcc, (q31_t)0x890186f2, (q31_t)0x2f24146b, (q31_t)0x88ff3669, (q31_t)0x2f1e3ced, (q31_t)0x88fce62a,
+    (q31_t)0x2f186551, (q31_t)0x88fa9634,
+  (q31_t)0x2f128d99, (q31_t)0x88f84687, (q31_t)0x2f0cb5c3, (q31_t)0x88f5f724, (q31_t)0x2f06ddd1, (q31_t)0x88f3a80b,
+    (q31_t)0x2f0105c1, (q31_t)0x88f1593b,
+  (q31_t)0x2efb2d95, (q31_t)0x88ef0ab4, (q31_t)0x2ef5554b, (q31_t)0x88ecbc77, (q31_t)0x2eef7ce5, (q31_t)0x88ea6e83,
+    (q31_t)0x2ee9a461, (q31_t)0x88e820d9,
+  (q31_t)0x2ee3cbc1, (q31_t)0x88e5d378, (q31_t)0x2eddf304, (q31_t)0x88e38660, (q31_t)0x2ed81a29, (q31_t)0x88e13992,
+    (q31_t)0x2ed24132, (q31_t)0x88deed0e,
+  (q31_t)0x2ecc681e, (q31_t)0x88dca0d3, (q31_t)0x2ec68eed, (q31_t)0x88da54e1, (q31_t)0x2ec0b5a0, (q31_t)0x88d8093a,
+    (q31_t)0x2ebadc35, (q31_t)0x88d5bddb,
+  (q31_t)0x2eb502ae, (q31_t)0x88d372c6, (q31_t)0x2eaf290a, (q31_t)0x88d127fb, (q31_t)0x2ea94f49, (q31_t)0x88cedd79,
+    (q31_t)0x2ea3756b, (q31_t)0x88cc9340,
+  (q31_t)0x2e9d9b70, (q31_t)0x88ca4951, (q31_t)0x2e97c159, (q31_t)0x88c7ffac, (q31_t)0x2e91e725, (q31_t)0x88c5b650,
+    (q31_t)0x2e8c0cd4, (q31_t)0x88c36d3e,
+  (q31_t)0x2e863267, (q31_t)0x88c12475, (q31_t)0x2e8057dd, (q31_t)0x88bedbf6, (q31_t)0x2e7a7d36, (q31_t)0x88bc93c0,
+    (q31_t)0x2e74a272, (q31_t)0x88ba4bd4,
+  (q31_t)0x2e6ec792, (q31_t)0x88b80432, (q31_t)0x2e68ec95, (q31_t)0x88b5bcd9, (q31_t)0x2e63117c, (q31_t)0x88b375ca,
+    (q31_t)0x2e5d3646, (q31_t)0x88b12f04,
+  (q31_t)0x2e575af3, (q31_t)0x88aee888, (q31_t)0x2e517f84, (q31_t)0x88aca255, (q31_t)0x2e4ba3f8, (q31_t)0x88aa5c6c,
+    (q31_t)0x2e45c850, (q31_t)0x88a816cd,
+  (q31_t)0x2e3fec8b, (q31_t)0x88a5d177, (q31_t)0x2e3a10aa, (q31_t)0x88a38c6b, (q31_t)0x2e3434ac, (q31_t)0x88a147a9,
+    (q31_t)0x2e2e5891, (q31_t)0x889f0330,
+  (q31_t)0x2e287c5a, (q31_t)0x889cbf01, (q31_t)0x2e22a007, (q31_t)0x889a7b1b, (q31_t)0x2e1cc397, (q31_t)0x88983780,
+    (q31_t)0x2e16e70b, (q31_t)0x8895f42d,
+  (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2e0b2d9d, (q31_t)0x88916e66, (q31_t)0x2e0550bb, (q31_t)0x888f2bf1,
+    (q31_t)0x2dff73bd, (q31_t)0x888ce9c5,
+  (q31_t)0x2df996a3, (q31_t)0x888aa7e3, (q31_t)0x2df3b96c, (q31_t)0x8888664b, (q31_t)0x2deddc19, (q31_t)0x888624fd,
+    (q31_t)0x2de7feaa, (q31_t)0x8883e3f8,
+  (q31_t)0x2de2211e, (q31_t)0x8881a33d, (q31_t)0x2ddc4376, (q31_t)0x887f62cb, (q31_t)0x2dd665b2, (q31_t)0x887d22a4,
+    (q31_t)0x2dd087d1, (q31_t)0x887ae2c6,
+  (q31_t)0x2dcaa9d5, (q31_t)0x8878a332, (q31_t)0x2dc4cbbc, (q31_t)0x887663e7, (q31_t)0x2dbeed86, (q31_t)0x887424e7,
+    (q31_t)0x2db90f35, (q31_t)0x8871e630,
+  (q31_t)0x2db330c7, (q31_t)0x886fa7c2, (q31_t)0x2dad523d, (q31_t)0x886d699f, (q31_t)0x2da77397, (q31_t)0x886b2bc5,
+    (q31_t)0x2da194d5, (q31_t)0x8868ee35,
+  (q31_t)0x2d9bb5f6, (q31_t)0x8866b0ef, (q31_t)0x2d95d6fc, (q31_t)0x886473f2, (q31_t)0x2d8ff7e5, (q31_t)0x88623740,
+    (q31_t)0x2d8a18b3, (q31_t)0x885ffad7,
+  (q31_t)0x2d843964, (q31_t)0x885dbeb8, (q31_t)0x2d7e59f9, (q31_t)0x885b82e3, (q31_t)0x2d787a72, (q31_t)0x88594757,
+    (q31_t)0x2d729acf, (q31_t)0x88570c16,
+  (q31_t)0x2d6cbb10, (q31_t)0x8854d11e, (q31_t)0x2d66db35, (q31_t)0x88529670, (q31_t)0x2d60fb3e, (q31_t)0x88505c0b,
+    (q31_t)0x2d5b1b2b, (q31_t)0x884e21f1,
+  (q31_t)0x2d553afc, (q31_t)0x884be821, (q31_t)0x2d4f5ab1, (q31_t)0x8849ae9a, (q31_t)0x2d497a4a, (q31_t)0x8847755d,
+    (q31_t)0x2d4399c7, (q31_t)0x88453c6a,
+  (q31_t)0x2d3db928, (q31_t)0x884303c1, (q31_t)0x2d37d86d, (q31_t)0x8840cb61, (q31_t)0x2d31f797, (q31_t)0x883e934c,
+    (q31_t)0x2d2c16a4, (q31_t)0x883c5b81,
+  (q31_t)0x2d263596, (q31_t)0x883a23ff, (q31_t)0x2d20546b, (q31_t)0x8837ecc7, (q31_t)0x2d1a7325, (q31_t)0x8835b5d9,
+    (q31_t)0x2d1491c4, (q31_t)0x88337f35,
+  (q31_t)0x2d0eb046, (q31_t)0x883148db, (q31_t)0x2d08ceac, (q31_t)0x882f12cb, (q31_t)0x2d02ecf7, (q31_t)0x882cdd04,
+    (q31_t)0x2cfd0b26, (q31_t)0x882aa788,
+  (q31_t)0x2cf72939, (q31_t)0x88287256, (q31_t)0x2cf14731, (q31_t)0x88263d6d, (q31_t)0x2ceb650d, (q31_t)0x882408ce,
+    (q31_t)0x2ce582cd, (q31_t)0x8821d47a,
+  (q31_t)0x2cdfa071, (q31_t)0x881fa06f, (q31_t)0x2cd9bdfa, (q31_t)0x881d6cae, (q31_t)0x2cd3db67, (q31_t)0x881b3937,
+    (q31_t)0x2ccdf8b8, (q31_t)0x8819060a,
+  (q31_t)0x2cc815ee, (q31_t)0x8816d327, (q31_t)0x2cc23308, (q31_t)0x8814a08f, (q31_t)0x2cbc5006, (q31_t)0x88126e40,
+    (q31_t)0x2cb66ce9, (q31_t)0x88103c3b,
+  (q31_t)0x2cb089b1, (q31_t)0x880e0a7f, (q31_t)0x2caaa65c, (q31_t)0x880bd90e, (q31_t)0x2ca4c2ed, (q31_t)0x8809a7e7,
+    (q31_t)0x2c9edf61, (q31_t)0x8807770a,
+  (q31_t)0x2c98fbba, (q31_t)0x88054677, (q31_t)0x2c9317f8, (q31_t)0x8803162e, (q31_t)0x2c8d341a, (q31_t)0x8800e62f,
+    (q31_t)0x2c875021, (q31_t)0x87feb67a,
+  (q31_t)0x2c816c0c, (q31_t)0x87fc870f, (q31_t)0x2c7b87dc, (q31_t)0x87fa57ee, (q31_t)0x2c75a390, (q31_t)0x87f82917,
+    (q31_t)0x2c6fbf29, (q31_t)0x87f5fa8b,
+  (q31_t)0x2c69daa6, (q31_t)0x87f3cc48, (q31_t)0x2c63f609, (q31_t)0x87f19e4f, (q31_t)0x2c5e114f, (q31_t)0x87ef70a0,
+    (q31_t)0x2c582c7b, (q31_t)0x87ed433c,
+  (q31_t)0x2c52478a, (q31_t)0x87eb1621, (q31_t)0x2c4c627f, (q31_t)0x87e8e950, (q31_t)0x2c467d58, (q31_t)0x87e6bcca,
+    (q31_t)0x2c409816, (q31_t)0x87e4908e,
+  (q31_t)0x2c3ab2b9, (q31_t)0x87e2649b, (q31_t)0x2c34cd40, (q31_t)0x87e038f3, (q31_t)0x2c2ee7ad, (q31_t)0x87de0d95,
+    (q31_t)0x2c2901fd, (q31_t)0x87dbe281,
+  (q31_t)0x2c231c33, (q31_t)0x87d9b7b7, (q31_t)0x2c1d364e, (q31_t)0x87d78d38, (q31_t)0x2c17504d, (q31_t)0x87d56302,
+    (q31_t)0x2c116a31, (q31_t)0x87d33916,
+  (q31_t)0x2c0b83fa, (q31_t)0x87d10f75, (q31_t)0x2c059da7, (q31_t)0x87cee61e, (q31_t)0x2bffb73a, (q31_t)0x87ccbd11,
+    (q31_t)0x2bf9d0b1, (q31_t)0x87ca944e,
+  (q31_t)0x2bf3ea0d, (q31_t)0x87c86bd5, (q31_t)0x2bee034e, (q31_t)0x87c643a6, (q31_t)0x2be81c74, (q31_t)0x87c41bc2,
+    (q31_t)0x2be2357f, (q31_t)0x87c1f427,
+  (q31_t)0x2bdc4e6f, (q31_t)0x87bfccd7, (q31_t)0x2bd66744, (q31_t)0x87bda5d1, (q31_t)0x2bd07ffe, (q31_t)0x87bb7f16,
+    (q31_t)0x2bca989d, (q31_t)0x87b958a4,
+  (q31_t)0x2bc4b120, (q31_t)0x87b7327d, (q31_t)0x2bbec989, (q31_t)0x87b50c9f, (q31_t)0x2bb8e1d7, (q31_t)0x87b2e70c,
+    (q31_t)0x2bb2fa0a, (q31_t)0x87b0c1c4,
+  (q31_t)0x2bad1221, (q31_t)0x87ae9cc5, (q31_t)0x2ba72a1e, (q31_t)0x87ac7811, (q31_t)0x2ba14200, (q31_t)0x87aa53a6,
+    (q31_t)0x2b9b59c7, (q31_t)0x87a82f87,
+  (q31_t)0x2b957173, (q31_t)0x87a60bb1, (q31_t)0x2b8f8905, (q31_t)0x87a3e825, (q31_t)0x2b89a07b, (q31_t)0x87a1c4e4,
+    (q31_t)0x2b83b7d7, (q31_t)0x879fa1ed,
+  (q31_t)0x2b7dcf17, (q31_t)0x879d7f41, (q31_t)0x2b77e63d, (q31_t)0x879b5cde, (q31_t)0x2b71fd48, (q31_t)0x87993ac6,
+    (q31_t)0x2b6c1438, (q31_t)0x879718f8,
+  (q31_t)0x2b662b0e, (q31_t)0x8794f774, (q31_t)0x2b6041c9, (q31_t)0x8792d63b, (q31_t)0x2b5a5868, (q31_t)0x8790b54c,
+    (q31_t)0x2b546eee, (q31_t)0x878e94a7,
+  (q31_t)0x2b4e8558, (q31_t)0x878c744d, (q31_t)0x2b489ba8, (q31_t)0x878a543d, (q31_t)0x2b42b1dd, (q31_t)0x87883477,
+    (q31_t)0x2b3cc7f7, (q31_t)0x878614fb,
+  (q31_t)0x2b36ddf7, (q31_t)0x8783f5ca, (q31_t)0x2b30f3dc, (q31_t)0x8781d6e3, (q31_t)0x2b2b09a6, (q31_t)0x877fb846,
+    (q31_t)0x2b251f56, (q31_t)0x877d99f4,
+  (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2b194a66, (q31_t)0x87795e2f, (q31_t)0x2b135fc6, (q31_t)0x877740bb,
+    (q31_t)0x2b0d750b, (q31_t)0x87752392,
+  (q31_t)0x2b078a36, (q31_t)0x877306b4, (q31_t)0x2b019f46, (q31_t)0x8770ea20, (q31_t)0x2afbb43c, (q31_t)0x876ecdd6,
+    (q31_t)0x2af5c917, (q31_t)0x876cb1d6,
+  (q31_t)0x2aefddd8, (q31_t)0x876a9621, (q31_t)0x2ae9f27e, (q31_t)0x87687ab7, (q31_t)0x2ae4070a, (q31_t)0x87665f96,
+    (q31_t)0x2ade1b7c, (q31_t)0x876444c1,
+  (q31_t)0x2ad82fd2, (q31_t)0x87622a35, (q31_t)0x2ad2440f, (q31_t)0x87600ff4, (q31_t)0x2acc5831, (q31_t)0x875df5fd,
+    (q31_t)0x2ac66c39, (q31_t)0x875bdc51,
+  (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2aba93f9, (q31_t)0x8757a9d8, (q31_t)0x2ab4a7b1, (q31_t)0x8755910b,
+    (q31_t)0x2aaebb50, (q31_t)0x87537888,
+  (q31_t)0x2aa8ced3, (q31_t)0x87516050, (q31_t)0x2aa2e23d, (q31_t)0x874f4862, (q31_t)0x2a9cf58c, (q31_t)0x874d30bf,
+    (q31_t)0x2a9708c1, (q31_t)0x874b1966,
+  (q31_t)0x2a911bdc, (q31_t)0x87490258, (q31_t)0x2a8b2edc, (q31_t)0x8746eb94, (q31_t)0x2a8541c3, (q31_t)0x8744d51b,
+    (q31_t)0x2a7f548e, (q31_t)0x8742beec,
+  (q31_t)0x2a796740, (q31_t)0x8740a907, (q31_t)0x2a7379d8, (q31_t)0x873e936d, (q31_t)0x2a6d8c55, (q31_t)0x873c7e1e,
+    (q31_t)0x2a679eb8, (q31_t)0x873a6919,
+  (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a5bc330, (q31_t)0x87363fee, (q31_t)0x2a55d545, (q31_t)0x87342bc9,
+    (q31_t)0x2a4fe740, (q31_t)0x873217ee,
+  (q31_t)0x2a49f920, (q31_t)0x8730045d, (q31_t)0x2a440ae7, (q31_t)0x872df117, (q31_t)0x2a3e1c93, (q31_t)0x872bde1c,
+    (q31_t)0x2a382e25, (q31_t)0x8729cb6b,
+  (q31_t)0x2a323f9e, (q31_t)0x8727b905, (q31_t)0x2a2c50fc, (q31_t)0x8725a6e9, (q31_t)0x2a266240, (q31_t)0x87239518,
+    (q31_t)0x2a20736a, (q31_t)0x87218391,
+  (q31_t)0x2a1a847b, (q31_t)0x871f7255, (q31_t)0x2a149571, (q31_t)0x871d6163, (q31_t)0x2a0ea64d, (q31_t)0x871b50bc,
+    (q31_t)0x2a08b710, (q31_t)0x87194060,
+  (q31_t)0x2a02c7b8, (q31_t)0x8717304e, (q31_t)0x29fcd847, (q31_t)0x87152087, (q31_t)0x29f6e8bb, (q31_t)0x8713110a,
+    (q31_t)0x29f0f916, (q31_t)0x871101d8,
+  (q31_t)0x29eb0957, (q31_t)0x870ef2f1, (q31_t)0x29e5197e, (q31_t)0x870ce454, (q31_t)0x29df298b, (q31_t)0x870ad602,
+    (q31_t)0x29d9397f, (q31_t)0x8708c7fa,
+  (q31_t)0x29d34958, (q31_t)0x8706ba3d, (q31_t)0x29cd5918, (q31_t)0x8704acca, (q31_t)0x29c768be, (q31_t)0x87029fa3,
+    (q31_t)0x29c1784a, (q31_t)0x870092c5,
+  (q31_t)0x29bb87bc, (q31_t)0x86fe8633, (q31_t)0x29b59715, (q31_t)0x86fc79eb, (q31_t)0x29afa654, (q31_t)0x86fa6dee,
+    (q31_t)0x29a9b579, (q31_t)0x86f8623b,
+  (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x299dd377, (q31_t)0x86f44bb6, (q31_t)0x2997e24f, (q31_t)0x86f240e3,
+    (q31_t)0x2991f10e, (q31_t)0x86f0365c,
+  (q31_t)0x298bffb2, (q31_t)0x86ee2c1e, (q31_t)0x29860e3e, (q31_t)0x86ec222c, (q31_t)0x29801caf, (q31_t)0x86ea1884,
+    (q31_t)0x297a2b07, (q31_t)0x86e80f27,
+  (q31_t)0x29743946, (q31_t)0x86e60614, (q31_t)0x296e476b, (q31_t)0x86e3fd4c, (q31_t)0x29685576, (q31_t)0x86e1f4cf,
+    (q31_t)0x29626368, (q31_t)0x86dfec9d,
+  (q31_t)0x295c7140, (q31_t)0x86dde4b5, (q31_t)0x29567eff, (q31_t)0x86dbdd18, (q31_t)0x29508ca4, (q31_t)0x86d9d5c6,
+    (q31_t)0x294a9a30, (q31_t)0x86d7cebf,
+  (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x293eb4fb, (q31_t)0x86d3c190, (q31_t)0x2938c23a, (q31_t)0x86d1bb69,
+    (q31_t)0x2932cf60, (q31_t)0x86cfb58c,
+  (q31_t)0x292cdc6d, (q31_t)0x86cdaffa, (q31_t)0x2926e960, (q31_t)0x86cbaab3, (q31_t)0x2920f63a, (q31_t)0x86c9a5b7,
+    (q31_t)0x291b02fa, (q31_t)0x86c7a106,
+  (q31_t)0x29150fa1, (q31_t)0x86c59c9f, (q31_t)0x290f1c2f, (q31_t)0x86c39883, (q31_t)0x290928a3, (q31_t)0x86c194b2,
+    (q31_t)0x290334ff, (q31_t)0x86bf912c,
+  (q31_t)0x28fd4140, (q31_t)0x86bd8df0, (q31_t)0x28f74d69, (q31_t)0x86bb8b00, (q31_t)0x28f15978, (q31_t)0x86b9885a,
+    (q31_t)0x28eb656e, (q31_t)0x86b785ff,
+  (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x28df7d0e, (q31_t)0x86b38229, (q31_t)0x28d988b8, (q31_t)0x86b180ae,
+    (q31_t)0x28d3944a, (q31_t)0x86af7f7e,
+  (q31_t)0x28cd9fc1, (q31_t)0x86ad7e99, (q31_t)0x28c7ab20, (q31_t)0x86ab7dff, (q31_t)0x28c1b666, (q31_t)0x86a97db0,
+    (q31_t)0x28bbc192, (q31_t)0x86a77dab,
+  (q31_t)0x28b5cca5, (q31_t)0x86a57df2, (q31_t)0x28afd7a0, (q31_t)0x86a37e83, (q31_t)0x28a9e281, (q31_t)0x86a17f5f,
+    (q31_t)0x28a3ed49, (q31_t)0x869f8086,
+  (q31_t)0x289df7f8, (q31_t)0x869d81f8, (q31_t)0x2898028e, (q31_t)0x869b83b4, (q31_t)0x28920d0a, (q31_t)0x869985bc,
+    (q31_t)0x288c176e, (q31_t)0x8697880f,
+  (q31_t)0x288621b9, (q31_t)0x86958aac, (q31_t)0x28802beb, (q31_t)0x86938d94, (q31_t)0x287a3604, (q31_t)0x869190c7,
+    (q31_t)0x28744004, (q31_t)0x868f9445,
+  (q31_t)0x286e49ea, (q31_t)0x868d980e, (q31_t)0x286853b8, (q31_t)0x868b9c22, (q31_t)0x28625d6d, (q31_t)0x8689a081,
+    (q31_t)0x285c670a, (q31_t)0x8687a52b,
+  (q31_t)0x2856708d, (q31_t)0x8685aa20, (q31_t)0x285079f7, (q31_t)0x8683af5f, (q31_t)0x284a8349, (q31_t)0x8681b4ea,
+    (q31_t)0x28448c81, (q31_t)0x867fbabf,
+  (q31_t)0x283e95a1, (q31_t)0x867dc0e0, (q31_t)0x28389ea8, (q31_t)0x867bc74b, (q31_t)0x2832a796, (q31_t)0x8679ce01,
+    (q31_t)0x282cb06c, (q31_t)0x8677d503,
+  (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x2820c1cc, (q31_t)0x8673e3e6, (q31_t)0x281aca57, (q31_t)0x8671ebc8,
+    (q31_t)0x2814d2c9, (q31_t)0x866ff3f6,
+  (q31_t)0x280edb23, (q31_t)0x866dfc6e, (q31_t)0x2808e364, (q31_t)0x866c0531, (q31_t)0x2802eb8c, (q31_t)0x866a0e3f,
+    (q31_t)0x27fcf39c, (q31_t)0x86681798,
+  (q31_t)0x27f6fb92, (q31_t)0x8666213c, (q31_t)0x27f10371, (q31_t)0x86642b2c, (q31_t)0x27eb0b36, (q31_t)0x86623566,
+    (q31_t)0x27e512e3, (q31_t)0x86603feb,
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+    (q31_t)0x27cd30a1, (q31_t)0x86586cee,
+  (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27c13eec, (q31_t)0x86548532, (q31_t)0x27bb45ed, (q31_t)0x865291c4,
+    (q31_t)0x27b54cd6, (q31_t)0x86509ea2,
+  (q31_t)0x27af53a6, (q31_t)0x864eabcb, (q31_t)0x27a95a5d, (q31_t)0x864cb93e, (q31_t)0x27a360fc, (q31_t)0x864ac6fd,
+    (q31_t)0x279d6783, (q31_t)0x8648d507,
+  (q31_t)0x27976df1, (q31_t)0x8646e35c, (q31_t)0x27917447, (q31_t)0x8644f1fc, (q31_t)0x278b7a84, (q31_t)0x864300e7,
+    (q31_t)0x278580a9, (q31_t)0x8641101d,
+  (q31_t)0x277f86b5, (q31_t)0x863f1f9e, (q31_t)0x27798caa, (q31_t)0x863d2f6b, (q31_t)0x27739285, (q31_t)0x863b3f82,
+    (q31_t)0x276d9849, (q31_t)0x86394fe5,
+  (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x2761a387, (q31_t)0x8635718b, (q31_t)0x275ba901, (q31_t)0x863382cf,
+    (q31_t)0x2755ae64, (q31_t)0x8631945e,
+  (q31_t)0x274fb3ae, (q31_t)0x862fa638, (q31_t)0x2749b8e0, (q31_t)0x862db85e, (q31_t)0x2743bdf9, (q31_t)0x862bcace,
+    (q31_t)0x273dc2fa, (q31_t)0x8629dd8a,
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+    (q31_t)0x2725d60e, (q31_t)0x86222b68,
+  (q31_t)0x271fda96, (q31_t)0x86203f9c, (q31_t)0x2719df06, (q31_t)0x861e541a, (q31_t)0x2713e35f, (q31_t)0x861c68e4,
+    (q31_t)0x270de79f, (q31_t)0x861a7df9,
+  (q31_t)0x2707ebc7, (q31_t)0x86189359, (q31_t)0x2701efd7, (q31_t)0x8616a905, (q31_t)0x26fbf3ce, (q31_t)0x8614befb,
+    (q31_t)0x26f5f7ae, (q31_t)0x8612d53d,
+  (q31_t)0x26effb76, (q31_t)0x8610ebca, (q31_t)0x26e9ff26, (q31_t)0x860f02a3, (q31_t)0x26e402bd, (q31_t)0x860d19c6,
+    (q31_t)0x26de063d, (q31_t)0x860b3135,
+  (q31_t)0x26d809a5, (q31_t)0x860948ef, (q31_t)0x26d20cf5, (q31_t)0x860760f4, (q31_t)0x26cc102d, (q31_t)0x86057944,
+    (q31_t)0x26c6134d, (q31_t)0x860391e0,
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+    (q31_t)0x26ae1edd, (q31_t)0x85fbf73f,
+  (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26a22416, (q31_t)0x85f82bb2, (q31_t)0x269c268f, (q31_t)0x85f6465c,
+    (q31_t)0x269628f0, (q31_t)0x85f46152,
+  (q31_t)0x26902b39, (q31_t)0x85f27c93, (q31_t)0x268a2d6b, (q31_t)0x85f09820, (q31_t)0x26842f84, (q31_t)0x85eeb3f7,
+    (q31_t)0x267e3186, (q31_t)0x85ecd01a,
+  (q31_t)0x26783370, (q31_t)0x85eaec88, (q31_t)0x26723543, (q31_t)0x85e90942, (q31_t)0x266c36fe, (q31_t)0x85e72647,
+    (q31_t)0x266638a1, (q31_t)0x85e54397,
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+    (q31_t)0x264e3e40, (q31_t)0x85ddbbc9,
+  (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x26424082, (q31_t)0x85d9f9a5, (q31_t)0x263c417f, (q31_t)0x85d81905,
+    (q31_t)0x26364265, (q31_t)0x85d638b0,
+  (q31_t)0x26304333, (q31_t)0x85d458a6, (q31_t)0x262a43ea, (q31_t)0x85d278e7, (q31_t)0x26244489, (q31_t)0x85d09974,
+    (q31_t)0x261e4511, (q31_t)0x85ceba4d,
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+    (q31_t)0x26064645, (q31_t)0x85c740a0,
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+    (q31_t)0x25ee4601, (q31_t)0x85bfcba9,
+  (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x25e24553, (q31_t)0x85bc12f2, (q31_t)0x25dc44d9, (q31_t)0x85ba3707,
+    (q31_t)0x25d64447, (q31_t)0x85b85b68,
+  (q31_t)0x25d0439f, (q31_t)0x85b68015, (q31_t)0x25ca42de, (q31_t)0x85b4a50d, (q31_t)0x25c44207, (q31_t)0x85b2ca50,
+    (q31_t)0x25be4118, (q31_t)0x85b0efdf,
+  (q31_t)0x25b84012, (q31_t)0x85af15b9, (q31_t)0x25b23ef5, (q31_t)0x85ad3bdf, (q31_t)0x25ac3dc0, (q31_t)0x85ab6250,
+    (q31_t)0x25a63c74, (q31_t)0x85a9890d,
+  (q31_t)0x25a03b11, (q31_t)0x85a7b015, (q31_t)0x259a3997, (q31_t)0x85a5d768, (q31_t)0x25943806, (q31_t)0x85a3ff07,
+    (q31_t)0x258e365d, (q31_t)0x85a226f2,
+  (q31_t)0x2588349d, (q31_t)0x85a04f28, (q31_t)0x258232c6, (q31_t)0x859e77a9, (q31_t)0x257c30d8, (q31_t)0x859ca076,
+    (q31_t)0x25762ed3, (q31_t)0x859ac98f,
+  (q31_t)0x25702cb7, (q31_t)0x8598f2f3, (q31_t)0x256a2a83, (q31_t)0x85971ca2, (q31_t)0x25642839, (q31_t)0x8595469d,
+    (q31_t)0x255e25d7, (q31_t)0x859370e4,
+  (q31_t)0x2558235f, (q31_t)0x85919b76, (q31_t)0x255220cf, (q31_t)0x858fc653, (q31_t)0x254c1e28, (q31_t)0x858df17c,
+    (q31_t)0x25461b6b, (q31_t)0x858c1cf1,
+  (q31_t)0x25401896, (q31_t)0x858a48b1, (q31_t)0x253a15aa, (q31_t)0x858874bd, (q31_t)0x253412a8, (q31_t)0x8586a114,
+    (q31_t)0x252e0f8e, (q31_t)0x8584cdb7,
+  (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x25220916, (q31_t)0x858127df, (q31_t)0x251c05b8, (q31_t)0x857f5564,
+    (q31_t)0x25160243, (q31_t)0x857d8335,
+  (q31_t)0x250ffeb7, (q31_t)0x857bb152, (q31_t)0x2509fb14, (q31_t)0x8579dfba, (q31_t)0x2503f75a, (q31_t)0x85780e6e,
+    (q31_t)0x24fdf389, (q31_t)0x85763d6d,
+  (q31_t)0x24f7efa2, (q31_t)0x85746cb8, (q31_t)0x24f1eba4, (q31_t)0x85729c4e, (q31_t)0x24ebe78f, (q31_t)0x8570cc30,
+    (q31_t)0x24e5e363, (q31_t)0x856efc5e,
+  (q31_t)0x24dfdf20, (q31_t)0x856d2cd7, (q31_t)0x24d9dac7, (q31_t)0x856b5d9c, (q31_t)0x24d3d657, (q31_t)0x85698ead,
+    (q31_t)0x24cdd1d0, (q31_t)0x8567c009,
+  (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24c1c87f, (q31_t)0x856423a4, (q31_t)0x24bbc3b4, (q31_t)0x856255e3,
+    (q31_t)0x24b5bed2, (q31_t)0x8560886d,
+  (q31_t)0x24afb9da, (q31_t)0x855ebb44, (q31_t)0x24a9b4cb, (q31_t)0x855cee66, (q31_t)0x24a3afa6, (q31_t)0x855b21d3,
+    (q31_t)0x249daa6a, (q31_t)0x8559558c,
+  (q31_t)0x2497a517, (q31_t)0x85578991, (q31_t)0x24919fae, (q31_t)0x8555bde2, (q31_t)0x248b9a2f, (q31_t)0x8553f27e,
+    (q31_t)0x24859498, (q31_t)0x85522766,
+  (q31_t)0x247f8eec, (q31_t)0x85505c99, (q31_t)0x24798928, (q31_t)0x854e9219, (q31_t)0x2473834f, (q31_t)0x854cc7e3,
+    (q31_t)0x246d7d5e, (q31_t)0x854afdfa,
+  (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x2461713a, (q31_t)0x85476b0a, (q31_t)0x245b6b07, (q31_t)0x8545a204,
+    (q31_t)0x245564bd, (q31_t)0x8543d949,
+  (q31_t)0x244f5e5c, (q31_t)0x854210db, (q31_t)0x244957e5, (q31_t)0x854048b7, (q31_t)0x24435158, (q31_t)0x853e80e0,
+    (q31_t)0x243d4ab4, (q31_t)0x853cb954,
+  (q31_t)0x243743fa, (q31_t)0x853af214, (q31_t)0x24313d2a, (q31_t)0x85392b20, (q31_t)0x242b3644, (q31_t)0x85376477,
+    (q31_t)0x24252f47, (q31_t)0x85359e1a,
+  (q31_t)0x241f2833, (q31_t)0x8533d809, (q31_t)0x2419210a, (q31_t)0x85321244, (q31_t)0x241319ca, (q31_t)0x85304cca,
+    (q31_t)0x240d1274, (q31_t)0x852e879d,
+  (q31_t)0x24070b08, (q31_t)0x852cc2bb, (q31_t)0x24010385, (q31_t)0x852afe24, (q31_t)0x23fafbec, (q31_t)0x852939da,
+    (q31_t)0x23f4f43e, (q31_t)0x852775db,
+  (q31_t)0x23eeec78, (q31_t)0x8525b228, (q31_t)0x23e8e49d, (q31_t)0x8523eec1, (q31_t)0x23e2dcac, (q31_t)0x85222ba5,
+    (q31_t)0x23dcd4a4, (q31_t)0x852068d6,
+  (q31_t)0x23d6cc87, (q31_t)0x851ea652, (q31_t)0x23d0c453, (q31_t)0x851ce41a, (q31_t)0x23cabc09, (q31_t)0x851b222e,
+    (q31_t)0x23c4b3a9, (q31_t)0x8519608d,
+  (q31_t)0x23beab33, (q31_t)0x85179f39, (q31_t)0x23b8a2a7, (q31_t)0x8515de30, (q31_t)0x23b29a05, (q31_t)0x85141d73,
+    (q31_t)0x23ac914d, (q31_t)0x85125d02,
+  (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x23a07f9a, (q31_t)0x850edd03, (q31_t)0x239a76a0, (q31_t)0x850d1d75,
+    (q31_t)0x23946d90, (q31_t)0x850b5e34,
+  (q31_t)0x238e646a, (q31_t)0x85099f3e, (q31_t)0x23885b2e, (q31_t)0x8507e094, (q31_t)0x238251dd, (q31_t)0x85062235,
+    (q31_t)0x237c4875, (q31_t)0x85046423,
+  (q31_t)0x23763ef7, (q31_t)0x8502a65c, (q31_t)0x23703564, (q31_t)0x8500e8e2, (q31_t)0x236a2bba, (q31_t)0x84ff2bb3,
+    (q31_t)0x236421fb, (q31_t)0x84fd6ed0,
+  (q31_t)0x235e1826, (q31_t)0x84fbb239, (q31_t)0x23580e3b, (q31_t)0x84f9f5ee, (q31_t)0x2352043b, (q31_t)0x84f839ee,
+    (q31_t)0x234bfa24, (q31_t)0x84f67e3b,
+  (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x233fe5b6, (q31_t)0x84f307b8, (q31_t)0x2339db5e, (q31_t)0x84f14ce8,
+    (q31_t)0x2333d0f1, (q31_t)0x84ef9265,
+  (q31_t)0x232dc66d, (q31_t)0x84edd82d, (q31_t)0x2327bbd5, (q31_t)0x84ec1e41, (q31_t)0x2321b126, (q31_t)0x84ea64a1,
+    (q31_t)0x231ba662, (q31_t)0x84e8ab4d,
+  (q31_t)0x23159b88, (q31_t)0x84e6f244, (q31_t)0x230f9098, (q31_t)0x84e53988, (q31_t)0x23098593, (q31_t)0x84e38118,
+    (q31_t)0x23037a78, (q31_t)0x84e1c8f3,
+  (q31_t)0x22fd6f48, (q31_t)0x84e0111b, (q31_t)0x22f76402, (q31_t)0x84de598f, (q31_t)0x22f158a7, (q31_t)0x84dca24e,
+    (q31_t)0x22eb4d36, (q31_t)0x84daeb5a,
+  (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22df3613, (q31_t)0x84d77e54, (q31_t)0x22d92a61, (q31_t)0x84d5c844,
+    (q31_t)0x22d31e9a, (q31_t)0x84d4127f,
+  (q31_t)0x22cd12bd, (q31_t)0x84d25d06, (q31_t)0x22c706cb, (q31_t)0x84d0a7da, (q31_t)0x22c0fac4, (q31_t)0x84cef2f9,
+    (q31_t)0x22baeea7, (q31_t)0x84cd3e64,
+  (q31_t)0x22b4e274, (q31_t)0x84cb8a1b, (q31_t)0x22aed62c, (q31_t)0x84c9d61f, (q31_t)0x22a8c9cf, (q31_t)0x84c8226e,
+    (q31_t)0x22a2bd5d, (q31_t)0x84c66f09,
+  (q31_t)0x229cb0d5, (q31_t)0x84c4bbf0, (q31_t)0x2296a437, (q31_t)0x84c30924, (q31_t)0x22909785, (q31_t)0x84c156a3,
+    (q31_t)0x228a8abd, (q31_t)0x84bfa46e,
+  (q31_t)0x22847de0, (q31_t)0x84bdf286, (q31_t)0x227e70ed, (q31_t)0x84bc40e9, (q31_t)0x227863e5, (q31_t)0x84ba8f98,
+    (q31_t)0x227256c8, (q31_t)0x84b8de94,
+  (q31_t)0x226c4996, (q31_t)0x84b72ddb, (q31_t)0x22663c4e, (q31_t)0x84b57d6f, (q31_t)0x22602ef1, (q31_t)0x84b3cd4f,
+    (q31_t)0x225a217f, (q31_t)0x84b21d7a,
+  (q31_t)0x225413f8, (q31_t)0x84b06df2, (q31_t)0x224e065c, (q31_t)0x84aebeb6, (q31_t)0x2247f8aa, (q31_t)0x84ad0fc6,
+    (q31_t)0x2241eae3, (q31_t)0x84ab6122,
+  (q31_t)0x223bdd08, (q31_t)0x84a9b2ca, (q31_t)0x2235cf17, (q31_t)0x84a804be, (q31_t)0x222fc111, (q31_t)0x84a656fe,
+    (q31_t)0x2229b2f6, (q31_t)0x84a4a98a,
+  (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x221d9680, (q31_t)0x84a14f87, (q31_t)0x22178826, (q31_t)0x849fa2f7,
+    (q31_t)0x221179b7, (q31_t)0x849df6b4,
+  (q31_t)0x220b6b32, (q31_t)0x849c4abd, (q31_t)0x22055c99, (q31_t)0x849a9f12, (q31_t)0x21ff4dea, (q31_t)0x8498f3b3,
+    (q31_t)0x21f93f27, (q31_t)0x849748a0,
+  (q31_t)0x21f3304f, (q31_t)0x84959dd9, (q31_t)0x21ed2162, (q31_t)0x8493f35e, (q31_t)0x21e71260, (q31_t)0x84924930,
+    (q31_t)0x21e10349, (q31_t)0x84909f4e,
+  (q31_t)0x21daf41d, (q31_t)0x848ef5b7, (q31_t)0x21d4e4dc, (q31_t)0x848d4c6d, (q31_t)0x21ced586, (q31_t)0x848ba36f,
+    (q31_t)0x21c8c61c, (q31_t)0x8489fabe,
+  (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x21bca708, (q31_t)0x8486aa3e, (q31_t)0x21b6975f, (q31_t)0x84850271,
+    (q31_t)0x21b087a1, (q31_t)0x84835af0,
+  (q31_t)0x21aa77cf, (q31_t)0x8481b3bb, (q31_t)0x21a467e7, (q31_t)0x84800cd2, (q31_t)0x219e57eb, (q31_t)0x847e6636,
+    (q31_t)0x219847da, (q31_t)0x847cbfe5,
+  (q31_t)0x219237b5, (q31_t)0x847b19e1, (q31_t)0x218c277a, (q31_t)0x84797429, (q31_t)0x2186172b, (q31_t)0x8477cebd,
+    (q31_t)0x218006c8, (q31_t)0x8476299e,
+  (q31_t)0x2179f64f, (q31_t)0x847484ca, (q31_t)0x2173e5c2, (q31_t)0x8472e043, (q31_t)0x216dd521, (q31_t)0x84713c08,
+    (q31_t)0x2167c46b, (q31_t)0x846f9819,
+  (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x215ba2c0, (q31_t)0x846c5120, (q31_t)0x215591cc, (q31_t)0x846aae16,
+    (q31_t)0x214f80c4, (q31_t)0x84690b58,
+  (q31_t)0x21496fa7, (q31_t)0x846768e7, (q31_t)0x21435e75, (q31_t)0x8465c6c1, (q31_t)0x213d4d2f, (q31_t)0x846424e8,
+    (q31_t)0x21373bd4, (q31_t)0x8462835b,
+  (q31_t)0x21312a65, (q31_t)0x8460e21a, (q31_t)0x212b18e1, (q31_t)0x845f4126, (q31_t)0x21250749, (q31_t)0x845da07e,
+    (q31_t)0x211ef59d, (q31_t)0x845c0022,
+  (q31_t)0x2118e3dc, (q31_t)0x845a6012, (q31_t)0x2112d206, (q31_t)0x8458c04f, (q31_t)0x210cc01d, (q31_t)0x845720d8,
+    (q31_t)0x2106ae1e, (q31_t)0x845581ad,
+  (q31_t)0x21009c0c, (q31_t)0x8453e2cf, (q31_t)0x20fa89e5, (q31_t)0x8452443d, (q31_t)0x20f477aa, (q31_t)0x8450a5f7,
+    (q31_t)0x20ee655a, (q31_t)0x844f07fd,
+  (q31_t)0x20e852f6, (q31_t)0x844d6a50, (q31_t)0x20e2407e, (q31_t)0x844bccef, (q31_t)0x20dc2df2, (q31_t)0x844a2fda,
+    (q31_t)0x20d61b51, (q31_t)0x84489311,
+  (q31_t)0x20d0089c, (q31_t)0x8446f695, (q31_t)0x20c9f5d3, (q31_t)0x84455a66, (q31_t)0x20c3e2f5, (q31_t)0x8443be82,
+    (q31_t)0x20bdd003, (q31_t)0x844222eb,
+  (q31_t)0x20b7bcfe, (q31_t)0x844087a0, (q31_t)0x20b1a9e4, (q31_t)0x843eeca2, (q31_t)0x20ab96b5, (q31_t)0x843d51f0,
+    (q31_t)0x20a58373, (q31_t)0x843bb78a,
+  (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x20995cb2, (q31_t)0x843883a3, (q31_t)0x20934933, (q31_t)0x8436ea23,
+    (q31_t)0x208d35a0, (q31_t)0x843550ee,
+  (q31_t)0x208721f9, (q31_t)0x8433b806, (q31_t)0x20810e3e, (q31_t)0x84321f6b, (q31_t)0x207afa6f, (q31_t)0x8430871b,
+    (q31_t)0x2074e68c, (q31_t)0x842eef18,
+  (q31_t)0x206ed295, (q31_t)0x842d5762, (q31_t)0x2068be8a, (q31_t)0x842bbff8, (q31_t)0x2062aa6b, (q31_t)0x842a28da,
+    (q31_t)0x205c9638, (q31_t)0x84289209,
+  (q31_t)0x205681f1, (q31_t)0x8426fb84, (q31_t)0x20506d96, (q31_t)0x8425654b, (q31_t)0x204a5927, (q31_t)0x8423cf5f,
+    (q31_t)0x204444a4, (q31_t)0x842239bf,
+  (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x20381b63, (q31_t)0x841f0f65, (q31_t)0x203206a4, (q31_t)0x841d7aaa,
+    (q31_t)0x202bf1d2, (q31_t)0x841be63c,
+  (q31_t)0x2025dcec, (q31_t)0x841a521a, (q31_t)0x201fc7f2, (q31_t)0x8418be45, (q31_t)0x2019b2e4, (q31_t)0x84172abc,
+    (q31_t)0x20139dc2, (q31_t)0x84159780,
+  (q31_t)0x200d888d, (q31_t)0x84140490, (q31_t)0x20077344, (q31_t)0x841271ec, (q31_t)0x20015de7, (q31_t)0x8410df95,
+    (q31_t)0x1ffb4876, (q31_t)0x840f4d8a,
+  (q31_t)0x1ff532f2, (q31_t)0x840dbbcc, (q31_t)0x1fef1d59, (q31_t)0x840c2a5a, (q31_t)0x1fe907ae, (q31_t)0x840a9935,
+    (q31_t)0x1fe2f1ee, (q31_t)0x8409085c,
+  (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1fd6c634, (q31_t)0x8405e790, (q31_t)0x1fd0b03a, (q31_t)0x8404579d,
+    (q31_t)0x1fca9a2b, (q31_t)0x8402c7f6,
+  (q31_t)0x1fc4840a, (q31_t)0x8401389b, (q31_t)0x1fbe6dd4, (q31_t)0x83ffa98d, (q31_t)0x1fb8578b, (q31_t)0x83fe1acc,
+    (q31_t)0x1fb2412f, (q31_t)0x83fc8c57,
+  (q31_t)0x1fac2abf, (q31_t)0x83fafe2e, (q31_t)0x1fa6143b, (q31_t)0x83f97052, (q31_t)0x1f9ffda4, (q31_t)0x83f7e2c3,
+    (q31_t)0x1f99e6fa, (q31_t)0x83f65580,
+  (q31_t)0x1f93d03c, (q31_t)0x83f4c889, (q31_t)0x1f8db96a, (q31_t)0x83f33bdf, (q31_t)0x1f87a285, (q31_t)0x83f1af82,
+    (q31_t)0x1f818b8d, (q31_t)0x83f02371,
+  (q31_t)0x1f7b7481, (q31_t)0x83ee97ad, (q31_t)0x1f755d61, (q31_t)0x83ed0c35, (q31_t)0x1f6f462f, (q31_t)0x83eb810a,
+    (q31_t)0x1f692ee9, (q31_t)0x83e9f62b,
+  (q31_t)0x1f63178f, (q31_t)0x83e86b99, (q31_t)0x1f5d0022, (q31_t)0x83e6e153, (q31_t)0x1f56e8a2, (q31_t)0x83e5575a,
+    (q31_t)0x1f50d10e, (q31_t)0x83e3cdad,
+  (q31_t)0x1f4ab968, (q31_t)0x83e2444d, (q31_t)0x1f44a1ad, (q31_t)0x83e0bb3a, (q31_t)0x1f3e89e0, (q31_t)0x83df3273,
+    (q31_t)0x1f3871ff, (q31_t)0x83dda9f9,
+  (q31_t)0x1f325a0b, (q31_t)0x83dc21cb, (q31_t)0x1f2c4204, (q31_t)0x83da99ea, (q31_t)0x1f2629ea, (q31_t)0x83d91255,
+    (q31_t)0x1f2011bc, (q31_t)0x83d78b0d,
+  (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1f13e127, (q31_t)0x83d47d63, (q31_t)0x1f0dc8c0, (q31_t)0x83d2f701,
+    (q31_t)0x1f07b045, (q31_t)0x83d170eb,
+  (q31_t)0x1f0197b8, (q31_t)0x83cfeb22, (q31_t)0x1efb7f17, (q31_t)0x83ce65a6, (q31_t)0x1ef56664, (q31_t)0x83cce076,
+    (q31_t)0x1eef4d9d, (q31_t)0x83cb5b93,
+  (q31_t)0x1ee934c3, (q31_t)0x83c9d6fc, (q31_t)0x1ee31bd6, (q31_t)0x83c852b2, (q31_t)0x1edd02d6, (q31_t)0x83c6ceb5,
+    (q31_t)0x1ed6e9c3, (q31_t)0x83c54b04,
+  (q31_t)0x1ed0d09d, (q31_t)0x83c3c7a0, (q31_t)0x1ecab763, (q31_t)0x83c24488, (q31_t)0x1ec49e17, (q31_t)0x83c0c1be,
+    (q31_t)0x1ebe84b8, (q31_t)0x83bf3f3f,
+  (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1eb251c1, (q31_t)0x83bc3b29, (q31_t)0x1eac3829, (q31_t)0x83bab991,
+    (q31_t)0x1ea61e7e, (q31_t)0x83b93845,
+  (q31_t)0x1ea004c1, (q31_t)0x83b7b746, (q31_t)0x1e99eaf0, (q31_t)0x83b63694, (q31_t)0x1e93d10c, (q31_t)0x83b4b62e,
+    (q31_t)0x1e8db716, (q31_t)0x83b33616,
+  (q31_t)0x1e879d0d, (q31_t)0x83b1b649, (q31_t)0x1e8182f1, (q31_t)0x83b036ca, (q31_t)0x1e7b68c2, (q31_t)0x83aeb797,
+    (q31_t)0x1e754e80, (q31_t)0x83ad38b1,
+  (q31_t)0x1e6f342c, (q31_t)0x83abba17, (q31_t)0x1e6919c4, (q31_t)0x83aa3bca, (q31_t)0x1e62ff4a, (q31_t)0x83a8bdca,
+    (q31_t)0x1e5ce4be, (q31_t)0x83a74017,
+  (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1e50af6c, (q31_t)0x83a44596, (q31_t)0x1e4a94a7, (q31_t)0x83a2c8c9,
+    (q31_t)0x1e4479cf, (q31_t)0x83a14c48,
+  (q31_t)0x1e3e5ee5, (q31_t)0x839fd014, (q31_t)0x1e3843e8, (q31_t)0x839e542d, (q31_t)0x1e3228d9, (q31_t)0x839cd893,
+    (q31_t)0x1e2c0db6, (q31_t)0x839b5d45,
+  (q31_t)0x1e25f282, (q31_t)0x8399e244, (q31_t)0x1e1fd73a, (q31_t)0x83986790, (q31_t)0x1e19bbe0, (q31_t)0x8396ed29,
+    (q31_t)0x1e13a074, (q31_t)0x8395730e,
+  (q31_t)0x1e0d84f5, (q31_t)0x8393f940, (q31_t)0x1e076963, (q31_t)0x83927fbf, (q31_t)0x1e014dbf, (q31_t)0x8391068a,
+    (q31_t)0x1dfb3208, (q31_t)0x838f8da2,
+  (q31_t)0x1df5163f, (q31_t)0x838e1507, (q31_t)0x1deefa63, (q31_t)0x838c9cb9, (q31_t)0x1de8de75, (q31_t)0x838b24b8,
+    (q31_t)0x1de2c275, (q31_t)0x8389ad03,
+  (q31_t)0x1ddca662, (q31_t)0x8388359b, (q31_t)0x1dd68a3c, (q31_t)0x8386be80, (q31_t)0x1dd06e04, (q31_t)0x838547b2,
+    (q31_t)0x1dca51ba, (q31_t)0x8383d130,
+  (q31_t)0x1dc4355e, (q31_t)0x83825afb, (q31_t)0x1dbe18ef, (q31_t)0x8380e513, (q31_t)0x1db7fc6d, (q31_t)0x837f6f78,
+    (q31_t)0x1db1dfda, (q31_t)0x837dfa2a,
+  (q31_t)0x1dabc334, (q31_t)0x837c8528, (q31_t)0x1da5a67c, (q31_t)0x837b1074, (q31_t)0x1d9f89b1, (q31_t)0x83799c0c,
+    (q31_t)0x1d996cd4, (q31_t)0x837827f0,
+  (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d8d32e4, (q31_t)0x837540a1, (q31_t)0x1d8715d0, (q31_t)0x8373cd6c,
+    (q31_t)0x1d80f8ab, (q31_t)0x83725a84,
+  (q31_t)0x1d7adb73, (q31_t)0x8370e7e9, (q31_t)0x1d74be29, (q31_t)0x836f759b, (q31_t)0x1d6ea0cc, (q31_t)0x836e039a,
+    (q31_t)0x1d68835e, (q31_t)0x836c91e5,
+  (q31_t)0x1d6265dd, (q31_t)0x836b207d, (q31_t)0x1d5c484b, (q31_t)0x8369af63, (q31_t)0x1d562aa6, (q31_t)0x83683e95,
+    (q31_t)0x1d500cef, (q31_t)0x8366ce14,
+  (q31_t)0x1d49ef26, (q31_t)0x83655ddf, (q31_t)0x1d43d14b, (q31_t)0x8363edf8, (q31_t)0x1d3db35e, (q31_t)0x83627e5d,
+    (q31_t)0x1d37955e, (q31_t)0x83610f10,
+  (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1d2b592a, (q31_t)0x835e315b, (q31_t)0x1d253af5, (q31_t)0x835cc2f4,
+    (q31_t)0x1d1f1cae, (q31_t)0x835b54da,
+  (q31_t)0x1d18fe54, (q31_t)0x8359e70d, (q31_t)0x1d12dfe9, (q31_t)0x8358798c, (q31_t)0x1d0cc16c, (q31_t)0x83570c59,
+    (q31_t)0x1d06a2dd, (q31_t)0x83559f72,
+  (q31_t)0x1d00843d, (q31_t)0x835432d8, (q31_t)0x1cfa658a, (q31_t)0x8352c68c, (q31_t)0x1cf446c5, (q31_t)0x83515a8c,
+    (q31_t)0x1cee27ef, (q31_t)0x834feed9,
+  (q31_t)0x1ce80906, (q31_t)0x834e8373, (q31_t)0x1ce1ea0c, (q31_t)0x834d185a, (q31_t)0x1cdbcb00, (q31_t)0x834bad8e,
+    (q31_t)0x1cd5abe3, (q31_t)0x834a430e,
+  (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1cc96d72, (q31_t)0x83476ef6, (q31_t)0x1cc34e1f, (q31_t)0x8346055e,
+    (q31_t)0x1cbd2eba, (q31_t)0x83449c12,
+  (q31_t)0x1cb70f43, (q31_t)0x83433314, (q31_t)0x1cb0efbb, (q31_t)0x8341ca62, (q31_t)0x1caad021, (q31_t)0x834061fd,
+    (q31_t)0x1ca4b075, (q31_t)0x833ef9e6,
+  (q31_t)0x1c9e90b8, (q31_t)0x833d921b, (q31_t)0x1c9870e9, (q31_t)0x833c2a9d, (q31_t)0x1c925109, (q31_t)0x833ac36c,
+    (q31_t)0x1c8c3116, (q31_t)0x83395c88,
+  (q31_t)0x1c861113, (q31_t)0x8337f5f1, (q31_t)0x1c7ff0fd, (q31_t)0x83368fa7, (q31_t)0x1c79d0d6, (q31_t)0x833529aa,
+    (q31_t)0x1c73b09d, (q31_t)0x8333c3fa,
+  (q31_t)0x1c6d9053, (q31_t)0x83325e97, (q31_t)0x1c676ff8, (q31_t)0x8330f981, (q31_t)0x1c614f8b, (q31_t)0x832f94b8,
+    (q31_t)0x1c5b2f0c, (q31_t)0x832e303c,
+  (q31_t)0x1c550e7c, (q31_t)0x832ccc0d, (q31_t)0x1c4eedda, (q31_t)0x832b682b, (q31_t)0x1c48cd27, (q31_t)0x832a0496,
+    (q31_t)0x1c42ac62, (q31_t)0x8328a14d,
+  (q31_t)0x1c3c8b8c, (q31_t)0x83273e52, (q31_t)0x1c366aa5, (q31_t)0x8325dba4, (q31_t)0x1c3049ac, (q31_t)0x83247943,
+    (q31_t)0x1c2a28a2, (q31_t)0x8323172f,
+  (q31_t)0x1c240786, (q31_t)0x8321b568, (q31_t)0x1c1de659, (q31_t)0x832053ee, (q31_t)0x1c17c51b, (q31_t)0x831ef2c1,
+    (q31_t)0x1c11a3cb, (q31_t)0x831d91e1,
+  (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1c0560f8, (q31_t)0x831ad109, (q31_t)0x1bff3f75, (q31_t)0x83197110,
+    (q31_t)0x1bf91de0, (q31_t)0x83181164,
+  (q31_t)0x1bf2fc3a, (q31_t)0x8316b205, (q31_t)0x1becda83, (q31_t)0x831552f4, (q31_t)0x1be6b8ba, (q31_t)0x8313f42f,
+    (q31_t)0x1be096e0, (q31_t)0x831295b7,
+  (q31_t)0x1bda74f6, (q31_t)0x8311378d, (q31_t)0x1bd452f9, (q31_t)0x830fd9af, (q31_t)0x1bce30ec, (q31_t)0x830e7c1f,
+    (q31_t)0x1bc80ece, (q31_t)0x830d1edc,
+  (q31_t)0x1bc1ec9e, (q31_t)0x830bc1e6, (q31_t)0x1bbbca5e, (q31_t)0x830a653c, (q31_t)0x1bb5a80c, (q31_t)0x830908e0,
+    (q31_t)0x1baf85a9, (q31_t)0x8307acd1,
+  (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1ba340b0, (q31_t)0x8304f59b, (q31_t)0x1b9d1e1a, (q31_t)0x83039a73,
+    (q31_t)0x1b96fb73, (q31_t)0x83023f98,
+  (q31_t)0x1b90d8bb, (q31_t)0x8300e50b, (q31_t)0x1b8ab5f2, (q31_t)0x82ff8acb, (q31_t)0x1b849317, (q31_t)0x82fe30d7,
+    (q31_t)0x1b7e702c, (q31_t)0x82fcd731,
+  (q31_t)0x1b784d30, (q31_t)0x82fb7dd8, (q31_t)0x1b722a23, (q31_t)0x82fa24cc, (q31_t)0x1b6c0705, (q31_t)0x82f8cc0d,
+    (q31_t)0x1b65e3d7, (q31_t)0x82f7739c,
+  (q31_t)0x1b5fc097, (q31_t)0x82f61b77, (q31_t)0x1b599d46, (q31_t)0x82f4c3a0, (q31_t)0x1b5379e5, (q31_t)0x82f36c15,
+    (q31_t)0x1b4d5672, (q31_t)0x82f214d8,
+  (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1b410f5b, (q31_t)0x82ef6745, (q31_t)0x1b3aebb6, (q31_t)0x82ee10ef,
+    (q31_t)0x1b34c801, (q31_t)0x82ecbae7,
+  (q31_t)0x1b2ea43a, (q31_t)0x82eb652b, (q31_t)0x1b288063, (q31_t)0x82ea0fbd, (q31_t)0x1b225c7b, (q31_t)0x82e8ba9c,
+    (q31_t)0x1b1c3883, (q31_t)0x82e765c8,
+  (q31_t)0x1b161479, (q31_t)0x82e61141, (q31_t)0x1b0ff05f, (q31_t)0x82e4bd07, (q31_t)0x1b09cc34, (q31_t)0x82e3691b,
+    (q31_t)0x1b03a7f9, (q31_t)0x82e2157c,
+  (q31_t)0x1afd83ad, (q31_t)0x82e0c22a, (q31_t)0x1af75f50, (q31_t)0x82df6f25, (q31_t)0x1af13ae3, (q31_t)0x82de1c6d,
+    (q31_t)0x1aeb1665, (q31_t)0x82dcca02,
+  (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5, (q31_t)0x1adecd37, (q31_t)0x82da2615, (q31_t)0x1ad8a887, (q31_t)0x82d8d492,
+    (q31_t)0x1ad283c7, (q31_t)0x82d7835c,
+  (q31_t)0x1acc5ef6, (q31_t)0x82d63274, (q31_t)0x1ac63a14, (q31_t)0x82d4e1d8, (q31_t)0x1ac01522, (q31_t)0x82d3918a,
+    (q31_t)0x1ab9f020, (q31_t)0x82d24189,
+  (q31_t)0x1ab3cb0d, (q31_t)0x82d0f1d5, (q31_t)0x1aada5e9, (q31_t)0x82cfa26f, (q31_t)0x1aa780b6, (q31_t)0x82ce5356,
+    (q31_t)0x1aa15b71, (q31_t)0x82cd048a,
+  (q31_t)0x1a9b361d, (q31_t)0x82cbb60b, (q31_t)0x1a9510b7, (q31_t)0x82ca67d9, (q31_t)0x1a8eeb42, (q31_t)0x82c919f5,
+    (q31_t)0x1a88c5bc, (q31_t)0x82c7cc5e,
+  (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a7c7a7f, (q31_t)0x82c53217, (q31_t)0x1a7654c8, (q31_t)0x82c3e568,
+    (q31_t)0x1a702f01, (q31_t)0x82c29906,
+  (q31_t)0x1a6a0929, (q31_t)0x82c14cf1, (q31_t)0x1a63e341, (q31_t)0x82c00129, (q31_t)0x1a5dbd49, (q31_t)0x82beb5af,
+    (q31_t)0x1a579741, (q31_t)0x82bd6a82,
+  (q31_t)0x1a517128, (q31_t)0x82bc1fa2, (q31_t)0x1a4b4aff, (q31_t)0x82bad50f, (q31_t)0x1a4524c6, (q31_t)0x82b98aca,
+    (q31_t)0x1a3efe7c, (q31_t)0x82b840d2,
+  (q31_t)0x1a38d823, (q31_t)0x82b6f727, (q31_t)0x1a32b1b9, (q31_t)0x82b5adca, (q31_t)0x1a2c8b3f, (q31_t)0x82b464ba,
+    (q31_t)0x1a2664b5, (q31_t)0x82b31bf7,
+  (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x1a1a1771, (q31_t)0x82b08b59, (q31_t)0x1a13f0b6, (q31_t)0x82af437e,
+    (q31_t)0x1a0dc9ec, (q31_t)0x82adfbf0,
+  (q31_t)0x1a07a311, (q31_t)0x82acb4b0, (q31_t)0x1a017c27, (q31_t)0x82ab6dbd, (q31_t)0x19fb552c, (q31_t)0x82aa2717,
+    (q31_t)0x19f52e22, (q31_t)0x82a8e0bf,
+  (q31_t)0x19ef0707, (q31_t)0x82a79ab3, (q31_t)0x19e8dfdc, (q31_t)0x82a654f6, (q31_t)0x19e2b8a2, (q31_t)0x82a50f85,
+    (q31_t)0x19dc9157, (q31_t)0x82a3ca62,
+  (q31_t)0x19d669fc, (q31_t)0x82a2858c, (q31_t)0x19d04292, (q31_t)0x82a14104, (q31_t)0x19ca1b17, (q31_t)0x829ffcc8,
+    (q31_t)0x19c3f38d, (q31_t)0x829eb8db,
+  (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x19b7a449, (q31_t)0x829c31e7, (q31_t)0x19b17c8f, (q31_t)0x829aeee1,
+    (q31_t)0x19ab54c5, (q31_t)0x8299ac29,
+  (q31_t)0x19a52ceb, (q31_t)0x829869be, (q31_t)0x199f0502, (q31_t)0x829727a0, (q31_t)0x1998dd09, (q31_t)0x8295e5cf,
+    (q31_t)0x1992b4ff, (q31_t)0x8294a44c,
+  (q31_t)0x198c8ce7, (q31_t)0x82936317, (q31_t)0x198664be, (q31_t)0x8292222e, (q31_t)0x19803c86, (q31_t)0x8290e194,
+    (q31_t)0x197a143e, (q31_t)0x828fa146,
+  (q31_t)0x1973ebe6, (q31_t)0x828e6146, (q31_t)0x196dc37e, (q31_t)0x828d2193, (q31_t)0x19679b07, (q31_t)0x828be22e,
+    (q31_t)0x19617280, (q31_t)0x828aa316,
+  (q31_t)0x195b49ea, (q31_t)0x8289644b, (q31_t)0x19552144, (q31_t)0x828825ce, (q31_t)0x194ef88e, (q31_t)0x8286e79e,
+    (q31_t)0x1948cfc8, (q31_t)0x8285a9bb,
+  (q31_t)0x1942a6f3, (q31_t)0x82846c26, (q31_t)0x193c7e0f, (q31_t)0x82832edf, (q31_t)0x1936551b, (q31_t)0x8281f1e4,
+    (q31_t)0x19302c17, (q31_t)0x8280b538,
+  (q31_t)0x192a0304, (q31_t)0x827f78d8, (q31_t)0x1923d9e1, (q31_t)0x827e3cc6, (q31_t)0x191db0af, (q31_t)0x827d0102,
+    (q31_t)0x1917876d, (q31_t)0x827bc58a,
+  (q31_t)0x19115e1c, (q31_t)0x827a8a61, (q31_t)0x190b34bb, (q31_t)0x82794f84, (q31_t)0x19050b4b, (q31_t)0x827814f6,
+    (q31_t)0x18fee1cb, (q31_t)0x8276dab4,
+  (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18f28e9e, (q31_t)0x8274671a, (q31_t)0x18ec64f0, (q31_t)0x82732dc0,
+    (q31_t)0x18e63b33, (q31_t)0x8271f4b5,
+  (q31_t)0x18e01167, (q31_t)0x8270bbf7, (q31_t)0x18d9e78b, (q31_t)0x826f8386, (q31_t)0x18d3bda0, (q31_t)0x826e4b62,
+    (q31_t)0x18cd93a5, (q31_t)0x826d138d,
+  (q31_t)0x18c7699b, (q31_t)0x826bdc04, (q31_t)0x18c13f82, (q31_t)0x826aa4c9, (q31_t)0x18bb155a, (q31_t)0x82696ddc,
+    (q31_t)0x18b4eb22, (q31_t)0x8268373c,
+  (q31_t)0x18aec0db, (q31_t)0x826700e9, (q31_t)0x18a89685, (q31_t)0x8265cae4, (q31_t)0x18a26c20, (q31_t)0x8264952d,
+    (q31_t)0x189c41ab, (q31_t)0x82635fc2,
+  (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x188fec95, (q31_t)0x8260f5d7, (q31_t)0x1889c1f3, (q31_t)0x825fc155,
+    (q31_t)0x18839742, (q31_t)0x825e8d21,
+  (q31_t)0x187d6c82, (q31_t)0x825d593a, (q31_t)0x187741b2, (q31_t)0x825c25a1, (q31_t)0x187116d4, (q31_t)0x825af255,
+    (q31_t)0x186aebe6, (q31_t)0x8259bf57,
+  (q31_t)0x1864c0ea, (q31_t)0x82588ca7, (q31_t)0x185e95de, (q31_t)0x82575a44, (q31_t)0x18586ac3, (q31_t)0x8256282e,
+    (q31_t)0x18523f9a, (q31_t)0x8254f666,
+  (q31_t)0x184c1461, (q31_t)0x8253c4eb, (q31_t)0x1845e919, (q31_t)0x825293be, (q31_t)0x183fbdc3, (q31_t)0x825162df,
+    (q31_t)0x1839925d, (q31_t)0x8250324d,
+  (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x182d3b65, (q31_t)0x824dd211, (q31_t)0x18270fd3, (q31_t)0x824ca268,
+    (q31_t)0x1820e431, (q31_t)0x824b730c,
+  (q31_t)0x181ab881, (q31_t)0x824a43fe, (q31_t)0x18148cc2, (q31_t)0x8249153d, (q31_t)0x180e60f4, (q31_t)0x8247e6ca,
+    (q31_t)0x18083518, (q31_t)0x8246b8a4,
+  (q31_t)0x1802092c, (q31_t)0x82458acc, (q31_t)0x17fbdd32, (q31_t)0x82445d41, (q31_t)0x17f5b129, (q31_t)0x82433004,
+    (q31_t)0x17ef8511, (q31_t)0x82420315,
+  (q31_t)0x17e958ea, (q31_t)0x8240d673, (q31_t)0x17e32cb5, (q31_t)0x823faa1e, (q31_t)0x17dd0070, (q31_t)0x823e7e18,
+    (q31_t)0x17d6d41d, (q31_t)0x823d525e,
+  (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, (q31_t)0x17ca7b4c, (q31_t)0x823afbd5, (q31_t)0x17c44ecd, (q31_t)0x8239d104,
+    (q31_t)0x17be223f, (q31_t)0x8238a681,
+  (q31_t)0x17b7f5a3, (q31_t)0x82377c4c, (q31_t)0x17b1c8f8, (q31_t)0x82365264, (q31_t)0x17ab9c3e, (q31_t)0x823528ca,
+    (q31_t)0x17a56f76, (q31_t)0x8233ff7e,
+  (q31_t)0x179f429f, (q31_t)0x8232d67f, (q31_t)0x179915ba, (q31_t)0x8231adce, (q31_t)0x1792e8c6, (q31_t)0x8230856a,
+    (q31_t)0x178cbbc4, (q31_t)0x822f5d54,
+  (q31_t)0x17868eb3, (q31_t)0x822e358b, (q31_t)0x17806194, (q31_t)0x822d0e10, (q31_t)0x177a3466, (q31_t)0x822be6e3,
+    (q31_t)0x17740729, (q31_t)0x822ac004,
+  (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x1767ac85, (q31_t)0x8228732d, (q31_t)0x17617f1d, (q31_t)0x82274d36,
+    (q31_t)0x175b51a7, (q31_t)0x8226278d,
+  (q31_t)0x17552422, (q31_t)0x82250232, (q31_t)0x174ef68f, (q31_t)0x8223dd24, (q31_t)0x1748c8ee, (q31_t)0x8222b863,
+    (q31_t)0x17429b3e, (q31_t)0x822193f1,
+  (q31_t)0x173c6d80, (q31_t)0x82206fcc, (q31_t)0x17363fb4, (q31_t)0x821f4bf5, (q31_t)0x173011d9, (q31_t)0x821e286b,
+    (q31_t)0x1729e3f0, (q31_t)0x821d052f,
+  (q31_t)0x1723b5f9, (q31_t)0x821be240, (q31_t)0x171d87f3, (q31_t)0x821abfa0, (q31_t)0x171759df, (q31_t)0x82199d4d,
+    (q31_t)0x17112bbd, (q31_t)0x82187b47,
+  (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x1704cf4f, (q31_t)0x82163826, (q31_t)0x16fea102, (q31_t)0x82151709,
+    (q31_t)0x16f872a7, (q31_t)0x8213f63a,
+  (q31_t)0x16f2443e, (q31_t)0x8212d5b9, (q31_t)0x16ec15c7, (q31_t)0x8211b586, (q31_t)0x16e5e741, (q31_t)0x821095a0,
+    (q31_t)0x16dfb8ae, (q31_t)0x820f7608,
+  (q31_t)0x16d98a0c, (q31_t)0x820e56be, (q31_t)0x16d35b5c, (q31_t)0x820d37c1, (q31_t)0x16cd2c9f, (q31_t)0x820c1912,
+    (q31_t)0x16c6fdd3, (q31_t)0x820afab1,
+  (q31_t)0x16c0cef9, (q31_t)0x8209dc9e, (q31_t)0x16baa011, (q31_t)0x8208bed8, (q31_t)0x16b4711b, (q31_t)0x8207a160,
+    (q31_t)0x16ae4217, (q31_t)0x82068435,
+  (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x16a1e3e5, (q31_t)0x82044ac9, (q31_t)0x169bb4b7, (q31_t)0x82032e88,
+    (q31_t)0x1695857b, (q31_t)0x82021294,
+  (q31_t)0x168f5632, (q31_t)0x8200f6ef, (q31_t)0x168926da, (q31_t)0x81ffdb96, (q31_t)0x1682f774, (q31_t)0x81fec08c,
+    (q31_t)0x167cc801, (q31_t)0x81fda5cf,
+  (q31_t)0x1676987f, (q31_t)0x81fc8b60, (q31_t)0x167068f0, (q31_t)0x81fb713f, (q31_t)0x166a3953, (q31_t)0x81fa576c,
+    (q31_t)0x166409a8, (q31_t)0x81f93de6,
+  (q31_t)0x165dd9f0, (q31_t)0x81f824ae, (q31_t)0x1657aa29, (q31_t)0x81f70bc3, (q31_t)0x16517a55, (q31_t)0x81f5f327,
+    (q31_t)0x164b4a73, (q31_t)0x81f4dad8,
+  (q31_t)0x16451a83, (q31_t)0x81f3c2d7, (q31_t)0x163eea86, (q31_t)0x81f2ab24, (q31_t)0x1638ba7a, (q31_t)0x81f193be,
+    (q31_t)0x16328a61, (q31_t)0x81f07ca6,
+  (q31_t)0x162c5a3b, (q31_t)0x81ef65dc, (q31_t)0x16262a06, (q31_t)0x81ee4f60, (q31_t)0x161ff9c4, (q31_t)0x81ed3932,
+    (q31_t)0x1619c975, (q31_t)0x81ec2351,
+  (q31_t)0x16139918, (q31_t)0x81eb0dbe, (q31_t)0x160d68ad, (q31_t)0x81e9f879, (q31_t)0x16073834, (q31_t)0x81e8e381,
+    (q31_t)0x160107ae, (q31_t)0x81e7ced8,
+  (q31_t)0x15fad71b, (q31_t)0x81e6ba7c, (q31_t)0x15f4a679, (q31_t)0x81e5a66e, (q31_t)0x15ee75cb, (q31_t)0x81e492ad,
+    (q31_t)0x15e8450e, (q31_t)0x81e37f3b,
+  (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x15dbe36d, (q31_t)0x81e1593f, (q31_t)0x15d5b288, (q31_t)0x81e046b6,
+    (q31_t)0x15cf8196, (q31_t)0x81df347b,
+  (q31_t)0x15c95097, (q31_t)0x81de228d, (q31_t)0x15c31f89, (q31_t)0x81dd10ee, (q31_t)0x15bcee6f, (q31_t)0x81dbff9c,
+    (q31_t)0x15b6bd47, (q31_t)0x81daee98,
+  (q31_t)0x15b08c12, (q31_t)0x81d9dde1, (q31_t)0x15aa5acf, (q31_t)0x81d8cd79, (q31_t)0x15a4297f, (q31_t)0x81d7bd5e,
+    (q31_t)0x159df821, (q31_t)0x81d6ad92,
+  (q31_t)0x1597c6b7, (q31_t)0x81d59e13, (q31_t)0x1591953e, (q31_t)0x81d48ee1, (q31_t)0x158b63b9, (q31_t)0x81d37ffe,
+    (q31_t)0x15853226, (q31_t)0x81d27169,
+  (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x1578ced9, (q31_t)0x81d05527, (q31_t)0x15729d1f, (q31_t)0x81cf477b,
+    (q31_t)0x156c6b57, (q31_t)0x81ce3a1d,
+  (q31_t)0x15663982, (q31_t)0x81cd2d0c, (q31_t)0x156007a0, (q31_t)0x81cc204a, (q31_t)0x1559d5b1, (q31_t)0x81cb13d5,
+    (q31_t)0x1553a3b4, (q31_t)0x81ca07af,
+  (q31_t)0x154d71aa, (q31_t)0x81c8fbd6, (q31_t)0x15473f94, (q31_t)0x81c7f04b, (q31_t)0x15410d70, (q31_t)0x81c6e50d,
+    (q31_t)0x153adb3f, (q31_t)0x81c5da1e,
+  (q31_t)0x1534a901, (q31_t)0x81c4cf7d, (q31_t)0x152e76b5, (q31_t)0x81c3c529, (q31_t)0x1528445d, (q31_t)0x81c2bb23,
+    (q31_t)0x152211f8, (q31_t)0x81c1b16b,
+  (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x1515ad06, (q31_t)0x81bf9ee5, (q31_t)0x150f7a7a, (q31_t)0x81be9617,
+    (q31_t)0x150947e1, (q31_t)0x81bd8d97,
+  (q31_t)0x1503153a, (q31_t)0x81bc8564, (q31_t)0x14fce287, (q31_t)0x81bb7d7f, (q31_t)0x14f6afc7, (q31_t)0x81ba75e9,
+    (q31_t)0x14f07cf9, (q31_t)0x81b96ea0,
+  (q31_t)0x14ea4a1f, (q31_t)0x81b867a5, (q31_t)0x14e41738, (q31_t)0x81b760f8, (q31_t)0x14dde445, (q31_t)0x81b65a99,
+    (q31_t)0x14d7b144, (q31_t)0x81b55488,
+  (q31_t)0x14d17e36, (q31_t)0x81b44ec4, (q31_t)0x14cb4b1c, (q31_t)0x81b3494f, (q31_t)0x14c517f4, (q31_t)0x81b24427,
+    (q31_t)0x14bee4c0, (q31_t)0x81b13f4e,
+  (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, (q31_t)0x14b27e32, (q31_t)0x81af3684, (q31_t)0x14ac4ad7, (q31_t)0x81ae3294,
+    (q31_t)0x14a61770, (q31_t)0x81ad2ef2,
+  (q31_t)0x149fe3fc, (q31_t)0x81ac2b9e, (q31_t)0x1499b07c, (q31_t)0x81ab2898, (q31_t)0x14937cee, (q31_t)0x81aa25e0,
+    (q31_t)0x148d4954, (q31_t)0x81a92376,
+  (q31_t)0x148715ae, (q31_t)0x81a82159, (q31_t)0x1480e1fa, (q31_t)0x81a71f8b, (q31_t)0x147aae3a, (q31_t)0x81a61e0b,
+    (q31_t)0x14747a6d, (q31_t)0x81a51cd8,
+  (q31_t)0x146e4694, (q31_t)0x81a41bf4, (q31_t)0x146812ae, (q31_t)0x81a31b5d, (q31_t)0x1461debc, (q31_t)0x81a21b14,
+    (q31_t)0x145baabd, (q31_t)0x81a11b1a,
+  (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x144f4299, (q31_t)0x819f1c0e, (q31_t)0x14490e74, (q31_t)0x819e1cfd,
+    (q31_t)0x1442da43, (q31_t)0x819d1e3a,
+  (q31_t)0x143ca605, (q31_t)0x819c1fc5, (q31_t)0x143671bb, (q31_t)0x819b219e, (q31_t)0x14303d65, (q31_t)0x819a23c5,
+    (q31_t)0x142a0902, (q31_t)0x8199263a,
+  (q31_t)0x1423d492, (q31_t)0x819828fd, (q31_t)0x141da016, (q31_t)0x81972c0e, (q31_t)0x14176b8e, (q31_t)0x81962f6d,
+    (q31_t)0x141136f9, (q31_t)0x8195331a,
+  (q31_t)0x140b0258, (q31_t)0x81943715, (q31_t)0x1404cdaa, (q31_t)0x81933b5e, (q31_t)0x13fe98f1, (q31_t)0x81923ff4,
+    (q31_t)0x13f8642a, (q31_t)0x819144d9,
+  (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x13ebfa79, (q31_t)0x818f4f8d, (q31_t)0x13e5c58e, (q31_t)0x818e555c,
+    (q31_t)0x13df9097, (q31_t)0x818d5b78,
+  (q31_t)0x13d95b93, (q31_t)0x818c61e3, (q31_t)0x13d32683, (q31_t)0x818b689c, (q31_t)0x13ccf167, (q31_t)0x818a6fa3,
+    (q31_t)0x13c6bc3f, (q31_t)0x818976f8,
+  (q31_t)0x13c0870a, (q31_t)0x81887e9a, (q31_t)0x13ba51ca, (q31_t)0x8187868b, (q31_t)0x13b41c7d, (q31_t)0x81868eca,
+    (q31_t)0x13ade724, (q31_t)0x81859757,
+  (q31_t)0x13a7b1bf, (q31_t)0x8184a032, (q31_t)0x13a17c4d, (q31_t)0x8183a95b, (q31_t)0x139b46d0, (q31_t)0x8182b2d1,
+    (q31_t)0x13951146, (q31_t)0x8181bc96,
+  (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x1388a60f, (q31_t)0x817fd10a, (q31_t)0x13827062, (q31_t)0x817edbb9,
+    (q31_t)0x137c3aa8, (q31_t)0x817de6b6,
+  (q31_t)0x137604e2, (q31_t)0x817cf201, (q31_t)0x136fcf10, (q31_t)0x817bfd9b, (q31_t)0x13699933, (q31_t)0x817b0982,
+    (q31_t)0x13636349, (q31_t)0x817a15b7,
+  (q31_t)0x135d2d53, (q31_t)0x8179223a, (q31_t)0x1356f752, (q31_t)0x81782f0b, (q31_t)0x1350c144, (q31_t)0x81773c2b,
+    (q31_t)0x134a8b2b, (q31_t)0x81764998,
+  (q31_t)0x13445505, (q31_t)0x81755754, (q31_t)0x133e1ed4, (q31_t)0x8174655d, (q31_t)0x1337e897, (q31_t)0x817373b5,
+    (q31_t)0x1331b24e, (q31_t)0x8172825a,
+  (q31_t)0x132b7bf9, (q31_t)0x8171914e, (q31_t)0x13254599, (q31_t)0x8170a090, (q31_t)0x131f0f2c, (q31_t)0x816fb020,
+    (q31_t)0x1318d8b4, (q31_t)0x816ebffe,
+  (q31_t)0x1312a230, (q31_t)0x816dd02a, (q31_t)0x130c6ba0, (q31_t)0x816ce0a4, (q31_t)0x13063505, (q31_t)0x816bf16c,
+    (q31_t)0x12fffe5d, (q31_t)0x816b0282,
+  (q31_t)0x12f9c7aa, (q31_t)0x816a13e6, (q31_t)0x12f390ec, (q31_t)0x81692599, (q31_t)0x12ed5a21, (q31_t)0x81683799,
+    (q31_t)0x12e7234b, (q31_t)0x816749e8,
+  (q31_t)0x12e0ec6a, (q31_t)0x81665c84, (q31_t)0x12dab57c, (q31_t)0x81656f6f, (q31_t)0x12d47e83, (q31_t)0x816482a8,
+    (q31_t)0x12ce477f, (q31_t)0x8163962f,
+  (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x12c1d953, (q31_t)0x8161be27, (q31_t)0x12bba22b, (q31_t)0x8160d298,
+    (q31_t)0x12b56af9, (q31_t)0x815fe758,
+  (q31_t)0x12af33ba, (q31_t)0x815efc65, (q31_t)0x12a8fc70, (q31_t)0x815e11c1, (q31_t)0x12a2c51b, (q31_t)0x815d276a,
+    (q31_t)0x129c8dba, (q31_t)0x815c3d62,
+  (q31_t)0x1296564d, (q31_t)0x815b53a8, (q31_t)0x12901ed5, (q31_t)0x815a6a3c, (q31_t)0x1289e752, (q31_t)0x8159811e,
+    (q31_t)0x1283afc3, (q31_t)0x8158984e,
+  (q31_t)0x127d7829, (q31_t)0x8157afcd, (q31_t)0x12774083, (q31_t)0x8156c799, (q31_t)0x127108d2, (q31_t)0x8155dfb4,
+    (q31_t)0x126ad116, (q31_t)0x8154f81d,
+  (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x125e617b, (q31_t)0x815329d9, (q31_t)0x1258299c, (q31_t)0x8152432c,
+    (q31_t)0x1251f1b3, (q31_t)0x81515ccd,
+  (q31_t)0x124bb9be, (q31_t)0x815076bd, (q31_t)0x124581bd, (q31_t)0x814f90fb, (q31_t)0x123f49b2, (q31_t)0x814eab86,
+    (q31_t)0x1239119b, (q31_t)0x814dc660,
+  (q31_t)0x1232d979, (q31_t)0x814ce188, (q31_t)0x122ca14b, (q31_t)0x814bfcff, (q31_t)0x12266913, (q31_t)0x814b18c3,
+    (q31_t)0x122030cf, (q31_t)0x814a34d6,
+  (q31_t)0x1219f880, (q31_t)0x81495136, (q31_t)0x1213c026, (q31_t)0x81486de5, (q31_t)0x120d87c1, (q31_t)0x81478ae2,
+    (q31_t)0x12074f50, (q31_t)0x8146a82e,
+  (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x11fade4e, (q31_t)0x8144e3ae, (q31_t)0x11f4a5bd, (q31_t)0x814401e4,
+    (q31_t)0x11ee6d20, (q31_t)0x81432068,
+  (q31_t)0x11e83478, (q31_t)0x81423f3a, (q31_t)0x11e1fbc5, (q31_t)0x81415e5a, (q31_t)0x11dbc307, (q31_t)0x81407dc9,
+    (q31_t)0x11d58a3e, (q31_t)0x813f9d86,
+  (q31_t)0x11cf516a, (q31_t)0x813ebd90, (q31_t)0x11c9188b, (q31_t)0x813ddde9, (q31_t)0x11c2dfa2, (q31_t)0x813cfe91,
+    (q31_t)0x11bca6ad, (q31_t)0x813c1f86,
+  (q31_t)0x11b66dad, (q31_t)0x813b40ca, (q31_t)0x11b034a2, (q31_t)0x813a625b, (q31_t)0x11a9fb8d, (q31_t)0x8139843b,
+    (q31_t)0x11a3c26c, (q31_t)0x8138a66a,
+  (q31_t)0x119d8941, (q31_t)0x8137c8e6, (q31_t)0x1197500a, (q31_t)0x8136ebb1, (q31_t)0x119116c9, (q31_t)0x81360ec9,
+    (q31_t)0x118add7d, (q31_t)0x81353230,
+  (q31_t)0x1184a427, (q31_t)0x813455e6, (q31_t)0x117e6ac5, (q31_t)0x813379e9, (q31_t)0x11783159, (q31_t)0x81329e3b,
+    (q31_t)0x1171f7e2, (q31_t)0x8131c2db,
+  (q31_t)0x116bbe60, (q31_t)0x8130e7c9, (q31_t)0x116584d3, (q31_t)0x81300d05, (q31_t)0x115f4b3c, (q31_t)0x812f3290,
+    (q31_t)0x1159119a, (q31_t)0x812e5868,
+  (q31_t)0x1152d7ed, (q31_t)0x812d7e8f, (q31_t)0x114c9e35, (q31_t)0x812ca505, (q31_t)0x11466473, (q31_t)0x812bcbc8,
+    (q31_t)0x11402aa6, (q31_t)0x812af2da,
+  (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x1133b6ed, (q31_t)0x812941e8, (q31_t)0x112d7d00, (q31_t)0x812869e4,
+    (q31_t)0x11274309, (q31_t)0x8127922f,
+  (q31_t)0x11210907, (q31_t)0x8126bac8, (q31_t)0x111acefb, (q31_t)0x8125e3af, (q31_t)0x111494e4, (q31_t)0x81250ce4,
+    (q31_t)0x110e5ac2, (q31_t)0x81243668,
+  (q31_t)0x11082096, (q31_t)0x8123603a, (q31_t)0x1101e65f, (q31_t)0x81228a5a, (q31_t)0x10fbac1e, (q31_t)0x8121b4c8,
+    (q31_t)0x10f571d3, (q31_t)0x8120df85,
+  (q31_t)0x10ef377d, (q31_t)0x81200a90, (q31_t)0x10e8fd1c, (q31_t)0x811f35e9, (q31_t)0x10e2c2b2, (q31_t)0x811e6191,
+    (q31_t)0x10dc883c, (q31_t)0x811d8d86,
+  (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x10d01333, (q31_t)0x811be65d, (q31_t)0x10c9d89e, (q31_t)0x811b133d,
+    (q31_t)0x10c39dff, (q31_t)0x811a406c,
+  (q31_t)0x10bd6356, (q31_t)0x81196de9, (q31_t)0x10b728a3, (q31_t)0x81189bb4, (q31_t)0x10b0ede5, (q31_t)0x8117c9ce,
+    (q31_t)0x10aab31d, (q31_t)0x8116f836,
+  (q31_t)0x10a4784b, (q31_t)0x811626ec, (q31_t)0x109e3d6e, (q31_t)0x811555f1, (q31_t)0x10980287, (q31_t)0x81148544,
+    (q31_t)0x1091c796, (q31_t)0x8113b4e5,
+  (q31_t)0x108b8c9b, (q31_t)0x8112e4d4, (q31_t)0x10855195, (q31_t)0x81121512, (q31_t)0x107f1686, (q31_t)0x8111459e,
+    (q31_t)0x1078db6c, (q31_t)0x81107678,
+  (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x106c651a, (q31_t)0x810ed917, (q31_t)0x106629e1, (q31_t)0x810e0adc,
+    (q31_t)0x105fee9f, (q31_t)0x810d3cf0,
+  (q31_t)0x1059b352, (q31_t)0x810c6f52, (q31_t)0x105377fc, (q31_t)0x810ba202, (q31_t)0x104d3c9b, (q31_t)0x810ad500,
+    (q31_t)0x10470130, (q31_t)0x810a084d,
+  (q31_t)0x1040c5bb, (q31_t)0x81093be8, (q31_t)0x103a8a3d, (q31_t)0x81086fd1, (q31_t)0x10344eb4, (q31_t)0x8107a409,
+    (q31_t)0x102e1321, (q31_t)0x8106d88f,
+  (q31_t)0x1027d784, (q31_t)0x81060d63, (q31_t)0x10219bdd, (q31_t)0x81054286, (q31_t)0x101b602d, (q31_t)0x810477f7,
+    (q31_t)0x10152472, (q31_t)0x8103adb6,
+  (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, (q31_t)0x1008acdf, (q31_t)0x81021a20, (q31_t)0x10027107, (q31_t)0x810150ca,
+    (q31_t)0xffc3524, (q31_t)0x810087c3,
+  (q31_t)0xff5f938, (q31_t)0x80ffbf0a, (q31_t)0xfefbd42, (q31_t)0x80fef69f, (q31_t)0xfe98143, (q31_t)0x80fe2e83,
+    (q31_t)0xfe34539, (q31_t)0x80fd66b5,
+  (q31_t)0xfdd0926, (q31_t)0x80fc9f35, (q31_t)0xfd6cd08, (q31_t)0x80fbd804, (q31_t)0xfd090e1, (q31_t)0x80fb1121,
+    (q31_t)0xfca54b1, (q31_t)0x80fa4a8c,
+  (q31_t)0xfc41876, (q31_t)0x80f98446, (q31_t)0xfbddc32, (q31_t)0x80f8be4e, (q31_t)0xfb79fe4, (q31_t)0x80f7f8a4,
+    (q31_t)0xfb1638d, (q31_t)0x80f73349,
+  (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xfa4eac0, (q31_t)0x80f5a97e, (q31_t)0xf9eae4c, (q31_t)0x80f4e50e,
+    (q31_t)0xf9871ce, (q31_t)0x80f420ec,
+  (q31_t)0xf923546, (q31_t)0x80f35d19, (q31_t)0xf8bf8b4, (q31_t)0x80f29994, (q31_t)0xf85bc19, (q31_t)0x80f1d65d,
+    (q31_t)0xf7f7f75, (q31_t)0x80f11375,
+  (q31_t)0xf7942c7, (q31_t)0x80f050db, (q31_t)0xf73060f, (q31_t)0x80ef8e90, (q31_t)0xf6cc94e, (q31_t)0x80eecc93,
+    (q31_t)0xf668c83, (q31_t)0x80ee0ae4,
+  (q31_t)0xf604faf, (q31_t)0x80ed4984, (q31_t)0xf5a12d1, (q31_t)0x80ec8872, (q31_t)0xf53d5ea, (q31_t)0x80ebc7ae,
+    (q31_t)0xf4d98f9, (q31_t)0x80eb0739,
+  (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xf411efb, (q31_t)0x80e9873a, (q31_t)0xf3ae1ee, (q31_t)0x80e8c7b0,
+    (q31_t)0xf34a4d8, (q31_t)0x80e80874,
+  (q31_t)0xf2e67b8, (q31_t)0x80e74987, (q31_t)0xf282a8f, (q31_t)0x80e68ae8, (q31_t)0xf21ed5d, (q31_t)0x80e5cc98,
+    (q31_t)0xf1bb021, (q31_t)0x80e50e96,
+  (q31_t)0xf1572dc, (q31_t)0x80e450e2, (q31_t)0xf0f358e, (q31_t)0x80e3937d, (q31_t)0xf08f836, (q31_t)0x80e2d666,
+    (q31_t)0xf02bad5, (q31_t)0x80e2199e,
+  (q31_t)0xefc7d6b, (q31_t)0x80e15d24, (q31_t)0xef63ff7, (q31_t)0x80e0a0f8, (q31_t)0xef0027b, (q31_t)0x80dfe51b,
+    (q31_t)0xee9c4f5, (q31_t)0x80df298c,
+  (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xedd49ce, (q31_t)0x80ddb35a, (q31_t)0xed70c2c, (q31_t)0x80dcf8b7,
+    (q31_t)0xed0ce82, (q31_t)0x80dc3e62,
+  (q31_t)0xeca90ce, (q31_t)0x80db845b, (q31_t)0xec45311, (q31_t)0x80dacaa3, (q31_t)0xebe154b, (q31_t)0x80da1139,
+    (q31_t)0xeb7d77c, (q31_t)0x80d9581e,
+  (q31_t)0xeb199a4, (q31_t)0x80d89f51, (q31_t)0xeab5bc3, (q31_t)0x80d7e6d3, (q31_t)0xea51dd8, (q31_t)0x80d72ea3,
+    (q31_t)0xe9edfe5, (q31_t)0x80d676c1,
+  (q31_t)0xe98a1e9, (q31_t)0x80d5bf2e, (q31_t)0xe9263e3, (q31_t)0x80d507e9, (q31_t)0xe8c25d5, (q31_t)0x80d450f3,
+    (q31_t)0xe85e7be, (q31_t)0x80d39a4b,
+  (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2, (q31_t)0xe796b74, (q31_t)0x80d22de7, (q31_t)0xe732d42, (q31_t)0x80d1782a,
+    (q31_t)0xe6cef07, (q31_t)0x80d0c2bc,
+  (q31_t)0xe66b0c3, (q31_t)0x80d00d9d, (q31_t)0xe607277, (q31_t)0x80cf58cc, (q31_t)0xe5a3421, (q31_t)0x80cea449,
+    (q31_t)0xe53f5c2, (q31_t)0x80cdf015,
+  (q31_t)0xe4db75b, (q31_t)0x80cd3c2f, (q31_t)0xe4778eb, (q31_t)0x80cc8898, (q31_t)0xe413a72, (q31_t)0x80cbd54f,
+    (q31_t)0xe3afbf0, (q31_t)0x80cb2255,
+  (q31_t)0xe34bd66, (q31_t)0x80ca6fa9, (q31_t)0xe2e7ed2, (q31_t)0x80c9bd4c, (q31_t)0xe284036, (q31_t)0x80c90b3d,
+    (q31_t)0xe220191, (q31_t)0x80c8597c,
+  (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xe15842e, (q31_t)0x80c6f6e7, (q31_t)0xe0f456f, (q31_t)0x80c64612,
+    (q31_t)0xe0906a7, (q31_t)0x80c5958b,
+  (q31_t)0xe02c7d7, (q31_t)0x80c4e553, (q31_t)0xdfc88fe, (q31_t)0x80c4356a, (q31_t)0xdf64a1c, (q31_t)0x80c385cf,
+    (q31_t)0xdf00b32, (q31_t)0x80c2d682,
+  (q31_t)0xde9cc40, (q31_t)0x80c22784, (q31_t)0xde38d44, (q31_t)0x80c178d4, (q31_t)0xddd4e40, (q31_t)0x80c0ca73,
+    (q31_t)0xdd70f34, (q31_t)0x80c01c60,
+  (q31_t)0xdd0d01f, (q31_t)0x80bf6e9c, (q31_t)0xdca9102, (q31_t)0x80bec127, (q31_t)0xdc451dc, (q31_t)0x80be13ff,
+    (q31_t)0xdbe12ad, (q31_t)0x80bd6727,
+  (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xdb19437, (q31_t)0x80bc0e61, (q31_t)0xdab54ef, (q31_t)0x80bb6274,
+    (q31_t)0xda5159f, (q31_t)0x80bab6d5,
+  (q31_t)0xd9ed646, (q31_t)0x80ba0b85, (q31_t)0xd9896e5, (q31_t)0x80b96083, (q31_t)0xd92577b, (q31_t)0x80b8b5d0,
+    (q31_t)0xd8c1809, (q31_t)0x80b80b6c,
+  (q31_t)0xd85d88f, (q31_t)0x80b76156, (q31_t)0xd7f990c, (q31_t)0x80b6b78e, (q31_t)0xd795982, (q31_t)0x80b60e15,
+    (q31_t)0xd7319ee, (q31_t)0x80b564ea,
+  (q31_t)0xd6cda53, (q31_t)0x80b4bc0e, (q31_t)0xd669aaf, (q31_t)0x80b41381, (q31_t)0xd605b03, (q31_t)0x80b36b42,
+    (q31_t)0xd5a1b4f, (q31_t)0x80b2c351,
+  (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xd4d9bcd, (q31_t)0x80b1745c, (q31_t)0xd475c00, (q31_t)0x80b0cd57,
+    (q31_t)0xd411c2b, (q31_t)0x80b026a1,
+  (q31_t)0xd3adc4e, (q31_t)0x80af8039, (q31_t)0xd349c68, (q31_t)0x80aeda20, (q31_t)0xd2e5c7b, (q31_t)0x80ae3455,
+    (q31_t)0xd281c85, (q31_t)0x80ad8ed9,
+  (q31_t)0xd21dc87, (q31_t)0x80ace9ab, (q31_t)0xd1b9c81, (q31_t)0x80ac44cc, (q31_t)0xd155c73, (q31_t)0x80aba03b,
+    (q31_t)0xd0f1c5d, (q31_t)0x80aafbf9,
+  (q31_t)0xd08dc3f, (q31_t)0x80aa5806, (q31_t)0xd029c18, (q31_t)0x80a9b461, (q31_t)0xcfc5bea, (q31_t)0x80a9110b,
+    (q31_t)0xcf61bb4, (q31_t)0x80a86e03,
+  (q31_t)0xcefdb76, (q31_t)0x80a7cb49, (q31_t)0xce99b2f, (q31_t)0x80a728df, (q31_t)0xce35ae1, (q31_t)0x80a686c2,
+    (q31_t)0xcdd1a8b, (q31_t)0x80a5e4f5,
+  (q31_t)0xcd6da2d, (q31_t)0x80a54376, (q31_t)0xcd099c7, (q31_t)0x80a4a245, (q31_t)0xcca5959, (q31_t)0x80a40163,
+    (q31_t)0xcc418e3, (q31_t)0x80a360d0,
+  (q31_t)0xcbdd865, (q31_t)0x80a2c08b, (q31_t)0xcb797e0, (q31_t)0x80a22095, (q31_t)0xcb15752, (q31_t)0x80a180ed,
+    (q31_t)0xcab16bd, (q31_t)0x80a0e194,
+  (q31_t)0xca4d620, (q31_t)0x80a04289, (q31_t)0xc9e957b, (q31_t)0x809fa3cd, (q31_t)0xc9854cf, (q31_t)0x809f0560,
+    (q31_t)0xc92141a, (q31_t)0x809e6741,
+  (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc85929a, (q31_t)0x809d2bef, (q31_t)0xc7f51cf, (q31_t)0x809c8ebc,
+    (q31_t)0xc7910fb, (q31_t)0x809bf1d7,
+  (q31_t)0xc72d020, (q31_t)0x809b5541, (q31_t)0xc6c8f3e, (q31_t)0x809ab8fa, (q31_t)0xc664e53, (q31_t)0x809a1d01,
+    (q31_t)0xc600d61, (q31_t)0x80998157,
+  (q31_t)0xc59cc68, (q31_t)0x8098e5fb, (q31_t)0xc538b66, (q31_t)0x80984aee, (q31_t)0xc4d4a5d, (q31_t)0x8097b030,
+    (q31_t)0xc47094d, (q31_t)0x809715c0,
+  (q31_t)0xc40c835, (q31_t)0x80967b9f, (q31_t)0xc3a8715, (q31_t)0x8095e1cc, (q31_t)0xc3445ee, (q31_t)0x80954848,
+    (q31_t)0xc2e04c0, (q31_t)0x8094af13,
+  (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xc21824c, (q31_t)0x80937d93, (q31_t)0xc1b4107, (q31_t)0x8092e54a,
+    (q31_t)0xc14ffba, (q31_t)0x80924d4f,
+  (q31_t)0xc0ebe66, (q31_t)0x8091b5a2, (q31_t)0xc087d0a, (q31_t)0x80911e44, (q31_t)0xc023ba7, (q31_t)0x80908735,
+    (q31_t)0xbfbfa3d, (q31_t)0x808ff074,
+  (q31_t)0xbf5b8cb, (q31_t)0x808f5a02, (q31_t)0xbef7752, (q31_t)0x808ec3df, (q31_t)0xbe935d2, (q31_t)0x808e2e0a,
+    (q31_t)0xbe2f44a, (q31_t)0x808d9884,
+  (q31_t)0xbdcb2bb, (q31_t)0x808d034c, (q31_t)0xbd67124, (q31_t)0x808c6e63, (q31_t)0xbd02f87, (q31_t)0x808bd9c9,
+    (q31_t)0xbc9ede2, (q31_t)0x808b457d,
+  (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xbbd6a82, (q31_t)0x808a1dd2, (q31_t)0xbb728c7, (q31_t)0x80898a72,
+    (q31_t)0xbb0e705, (q31_t)0x8088f761,
+  (q31_t)0xbaaa53b, (q31_t)0x8088649e, (q31_t)0xba4636b, (q31_t)0x8087d22a, (q31_t)0xb9e2193, (q31_t)0x80874005,
+    (q31_t)0xb97dfb5, (q31_t)0x8086ae2e,
+  (q31_t)0xb919dcf, (q31_t)0x80861ca6, (q31_t)0xb8b5be1, (q31_t)0x80858b6c, (q31_t)0xb8519ed, (q31_t)0x8084fa82,
+    (q31_t)0xb7ed7f2, (q31_t)0x808469e5,
+  (q31_t)0xb7895f0, (q31_t)0x8083d998, (q31_t)0xb7253e6, (q31_t)0x80834999, (q31_t)0xb6c11d5, (q31_t)0x8082b9e9,
+    (q31_t)0xb65cfbe, (q31_t)0x80822a87,
+  (q31_t)0xb5f8d9f, (q31_t)0x80819b74, (q31_t)0xb594b7a, (q31_t)0x80810cb0, (q31_t)0xb53094d, (q31_t)0x80807e3a,
+    (q31_t)0xb4cc719, (q31_t)0x807ff013,
+  (q31_t)0xb4684df, (q31_t)0x807f623b, (q31_t)0xb40429d, (q31_t)0x807ed4b1, (q31_t)0xb3a0055, (q31_t)0x807e4776,
+    (q31_t)0xb33be05, (q31_t)0x807dba89,
+  (q31_t)0xb2d7baf, (q31_t)0x807d2dec, (q31_t)0xb273952, (q31_t)0x807ca19c, (q31_t)0xb20f6ee, (q31_t)0x807c159c,
+    (q31_t)0xb1ab483, (q31_t)0x807b89ea,
+  (q31_t)0xb147211, (q31_t)0x807afe87, (q31_t)0xb0e2f98, (q31_t)0x807a7373, (q31_t)0xb07ed19, (q31_t)0x8079e8ad,
+    (q31_t)0xb01aa92, (q31_t)0x80795e36,
+  (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xaf52571, (q31_t)0x80784a33, (q31_t)0xaeee2d7, (q31_t)0x8077c0a8,
+    (q31_t)0xae8a036, (q31_t)0x8077376c,
+  (q31_t)0xae25d8d, (q31_t)0x8076ae7e, (q31_t)0xadc1adf, (q31_t)0x807625df, (q31_t)0xad5d829, (q31_t)0x80759d8e,
+    (q31_t)0xacf956d, (q31_t)0x8075158c,
+  (q31_t)0xac952aa, (q31_t)0x80748dd9, (q31_t)0xac30fe1, (q31_t)0x80740675, (q31_t)0xabccd11, (q31_t)0x80737f5f,
+    (q31_t)0xab68a3a, (q31_t)0x8072f898,
+  (q31_t)0xab0475c, (q31_t)0x8072721f, (q31_t)0xaaa0478, (q31_t)0x8071ebf6, (q31_t)0xaa3c18e, (q31_t)0x8071661a,
+    (q31_t)0xa9d7e9d, (q31_t)0x8070e08e,
+  (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa90f8a7, (q31_t)0x806fd661, (q31_t)0xa8ab5a2, (q31_t)0x806f51c1,
+    (q31_t)0xa847297, (q31_t)0x806ecd6f,
+  (q31_t)0xa7e2f85, (q31_t)0x806e496c, (q31_t)0xa77ec6d, (q31_t)0x806dc5b8, (q31_t)0xa71a94f, (q31_t)0x806d4253,
+    (q31_t)0xa6b662a, (q31_t)0x806cbf3c,
+  (q31_t)0xa6522fe, (q31_t)0x806c3c74, (q31_t)0xa5edfcc, (q31_t)0x806bb9fa, (q31_t)0xa589c94, (q31_t)0x806b37cf,
+    (q31_t)0xa525955, (q31_t)0x806ab5f3,
+  (q31_t)0xa4c1610, (q31_t)0x806a3466, (q31_t)0xa45d2c5, (q31_t)0x8069b327, (q31_t)0xa3f8f73, (q31_t)0x80693237,
+    (q31_t)0xa394c1b, (q31_t)0x8068b196,
+  (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0xa2cc558, (q31_t)0x8067b13f, (q31_t)0xa2681ed, (q31_t)0x8067318a,
+    (q31_t)0xa203e7c, (q31_t)0x8066b224,
+  (q31_t)0xa19fb04, (q31_t)0x8066330c, (q31_t)0xa13b787, (q31_t)0x8065b443, (q31_t)0xa0d7403, (q31_t)0x806535c9,
+    (q31_t)0xa073079, (q31_t)0x8064b79d,
+  (q31_t)0xa00ece8, (q31_t)0x806439c0, (q31_t)0x9faa952, (q31_t)0x8063bc32, (q31_t)0x9f465b5, (q31_t)0x80633ef3,
+    (q31_t)0x9ee2213, (q31_t)0x8062c202,
+  (q31_t)0x9e7de6a, (q31_t)0x80624560, (q31_t)0x9e19abb, (q31_t)0x8061c90c, (q31_t)0x9db5706, (q31_t)0x80614d08,
+    (q31_t)0x9d5134b, (q31_t)0x8060d152,
+  (q31_t)0x9cecf89, (q31_t)0x806055eb, (q31_t)0x9c88bc2, (q31_t)0x805fdad2, (q31_t)0x9c247f5, (q31_t)0x805f6009,
+    (q31_t)0x9bc0421, (q31_t)0x805ee58e,
+  (q31_t)0x9b5c048, (q31_t)0x805e6b62, (q31_t)0x9af7c69, (q31_t)0x805df184, (q31_t)0x9a93884, (q31_t)0x805d77f5,
+    (q31_t)0x9a2f498, (q31_t)0x805cfeb5,
+  (q31_t)0x99cb0a7, (q31_t)0x805c85c4, (q31_t)0x9966cb0, (q31_t)0x805c0d21, (q31_t)0x99028b3, (q31_t)0x805b94ce,
+    (q31_t)0x989e4b0, (q31_t)0x805b1cc8,
+  (q31_t)0x983a0a7, (q31_t)0x805aa512, (q31_t)0x97d5c99, (q31_t)0x805a2daa, (q31_t)0x9771884, (q31_t)0x8059b692,
+    (q31_t)0x970d46a, (q31_t)0x80593fc7,
+  (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9644c23, (q31_t)0x8058531f, (q31_t)0x95e07f8, (q31_t)0x8057dd41,
+    (q31_t)0x957c3c6, (q31_t)0x805767b2,
+  (q31_t)0x9517f8f, (q31_t)0x8056f272, (q31_t)0x94b3b52, (q31_t)0x80567d80, (q31_t)0x944f70f, (q31_t)0x805608dd,
+    (q31_t)0x93eb2c6, (q31_t)0x80559489,
+  (q31_t)0x9386e78, (q31_t)0x80552084, (q31_t)0x9322a24, (q31_t)0x8054accd, (q31_t)0x92be5ca, (q31_t)0x80543965,
+    (q31_t)0x925a16b, (q31_t)0x8053c64c,
+  (q31_t)0x91f5d06, (q31_t)0x80535381, (q31_t)0x919189c, (q31_t)0x8052e106, (q31_t)0x912d42c, (q31_t)0x80526ed9,
+    (q31_t)0x90c8fb6, (q31_t)0x8051fcfb,
+  (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x90006ba, (q31_t)0x80511a2b, (q31_t)0x8f9c233, (q31_t)0x8050a939,
+    (q31_t)0x8f37da7, (q31_t)0x80503896,
+  (q31_t)0x8ed3916, (q31_t)0x804fc841, (q31_t)0x8e6f47f, (q31_t)0x804f583c, (q31_t)0x8e0afe2, (q31_t)0x804ee885,
+    (q31_t)0x8da6b40, (q31_t)0x804e791d,
+  (q31_t)0x8d42699, (q31_t)0x804e0a04, (q31_t)0x8cde1ec, (q31_t)0x804d9b39, (q31_t)0x8c79d3a, (q31_t)0x804d2cbd,
+    (q31_t)0x8c15882, (q31_t)0x804cbe90,
+  (q31_t)0x8bb13c5, (q31_t)0x804c50b2, (q31_t)0x8b4cf02, (q31_t)0x804be323, (q31_t)0x8ae8a3a, (q31_t)0x804b75e2,
+    (q31_t)0x8a8456d, (q31_t)0x804b08f0,
+  (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x89bbbc3, (q31_t)0x804a2ff9, (q31_t)0x89576e5, (q31_t)0x8049c3f3,
+    (q31_t)0x88f3203, (q31_t)0x8049583d,
+  (q31_t)0x888ed1b, (q31_t)0x8048ecd5, (q31_t)0x882a82e, (q31_t)0x804881bb, (q31_t)0x87c633c, (q31_t)0x804816f1,
+    (q31_t)0x8761e44, (q31_t)0x8047ac75,
+  (q31_t)0x86fd947, (q31_t)0x80474248, (q31_t)0x8699445, (q31_t)0x8046d86a, (q31_t)0x8634f3e, (q31_t)0x80466edb,
+    (q31_t)0x85d0a32, (q31_t)0x8046059b,
+  (q31_t)0x856c520, (q31_t)0x80459ca9, (q31_t)0x850800a, (q31_t)0x80453406, (q31_t)0x84a3aee, (q31_t)0x8044cbb2,
+    (q31_t)0x843f5cd, (q31_t)0x804463ad,
+  (q31_t)0x83db0a7, (q31_t)0x8043fbf6, (q31_t)0x8376b7c, (q31_t)0x8043948e, (q31_t)0x831264c, (q31_t)0x80432d75,
+    (q31_t)0x82ae117, (q31_t)0x8042c6ab,
+  (q31_t)0x8249bdd, (q31_t)0x80426030, (q31_t)0x81e569d, (q31_t)0x8041fa03, (q31_t)0x8181159, (q31_t)0x80419425,
+    (q31_t)0x811cc10, (q31_t)0x80412e96,
+  (q31_t)0x80b86c2, (q31_t)0x8040c956, (q31_t)0x805416e, (q31_t)0x80406465, (q31_t)0x7fefc16, (q31_t)0x803fffc2,
+    (q31_t)0x7f8b6b9, (q31_t)0x803f9b6f,
+  (q31_t)0x7f27157, (q31_t)0x803f376a, (q31_t)0x7ec2bf0, (q31_t)0x803ed3b3, (q31_t)0x7e5e685, (q31_t)0x803e704c,
+    (q31_t)0x7dfa114, (q31_t)0x803e0d34,
+  (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x7d31624, (q31_t)0x803d47ef, (q31_t)0x7ccd0a5, (q31_t)0x803ce5c3,
+    (q31_t)0x7c68b21, (q31_t)0x803c83e5,
+  (q31_t)0x7c04598, (q31_t)0x803c2257, (q31_t)0x7ba000b, (q31_t)0x803bc117, (q31_t)0x7b3ba78, (q31_t)0x803b6026,
+    (q31_t)0x7ad74e1, (q31_t)0x803aff84,
+  (q31_t)0x7a72f45, (q31_t)0x803a9f31, (q31_t)0x7a0e9a5, (q31_t)0x803a3f2d, (q31_t)0x79aa400, (q31_t)0x8039df77,
+    (q31_t)0x7945e56, (q31_t)0x80398010,
+  (q31_t)0x78e18a7, (q31_t)0x803920f8, (q31_t)0x787d2f4, (q31_t)0x8038c22f, (q31_t)0x7818d3c, (q31_t)0x803863b5,
+    (q31_t)0x77b4780, (q31_t)0x80380589,
+  (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x76ebbf9, (q31_t)0x80374a1f, (q31_t)0x768762e, (q31_t)0x8036ece0,
+    (q31_t)0x762305f, (q31_t)0x80368fef,
+  (q31_t)0x75bea8c, (q31_t)0x8036334e, (q31_t)0x755a4b4, (q31_t)0x8035d6fb, (q31_t)0x74f5ed7, (q31_t)0x80357af8,
+    (q31_t)0x74918f6, (q31_t)0x80351f43,
+  (q31_t)0x742d311, (q31_t)0x8034c3dd, (q31_t)0x73c8d27, (q31_t)0x803468c5, (q31_t)0x7364738, (q31_t)0x80340dfd,
+    (q31_t)0x7300145, (q31_t)0x8033b383,
+  (q31_t)0x729bb4e, (q31_t)0x80335959, (q31_t)0x7237552, (q31_t)0x8032ff7d, (q31_t)0x71d2f52, (q31_t)0x8032a5ef,
+    (q31_t)0x716e94e, (q31_t)0x80324cb1,
+  (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x70a5d37, (q31_t)0x80319b21, (q31_t)0x7041726, (q31_t)0x803142cf,
+    (q31_t)0x6fdd110, (q31_t)0x8030eacd,
+  (q31_t)0x6f78af6, (q31_t)0x80309318, (q31_t)0x6f144d7, (q31_t)0x80303bb3, (q31_t)0x6eafeb4, (q31_t)0x802fe49d,
+    (q31_t)0x6e4b88d, (q31_t)0x802f8dd5,
+  (q31_t)0x6de7262, (q31_t)0x802f375d, (q31_t)0x6d82c32, (q31_t)0x802ee133, (q31_t)0x6d1e5fe, (q31_t)0x802e8b58,
+    (q31_t)0x6cb9fc6, (q31_t)0x802e35cb,
+  (q31_t)0x6c5598a, (q31_t)0x802de08e, (q31_t)0x6bf1349, (q31_t)0x802d8ba0, (q31_t)0x6b8cd05, (q31_t)0x802d3700,
+    (q31_t)0x6b286bc, (q31_t)0x802ce2af,
+  (q31_t)0x6ac406f, (q31_t)0x802c8ead, (q31_t)0x6a5fa1e, (q31_t)0x802c3afa, (q31_t)0x69fb3c9, (q31_t)0x802be796,
+    (q31_t)0x6996d70, (q31_t)0x802b9480,
+  (q31_t)0x6932713, (q31_t)0x802b41ba, (q31_t)0x68ce0b2, (q31_t)0x802aef42, (q31_t)0x6869a4c, (q31_t)0x802a9d19,
+    (q31_t)0x68053e3, (q31_t)0x802a4b3f,
+  (q31_t)0x67a0d76, (q31_t)0x8029f9b4, (q31_t)0x673c704, (q31_t)0x8029a878, (q31_t)0x66d808f, (q31_t)0x8029578b,
+    (q31_t)0x6673a16, (q31_t)0x802906ec,
+  (q31_t)0x660f398, (q31_t)0x8028b69c, (q31_t)0x65aad17, (q31_t)0x8028669b, (q31_t)0x6546692, (q31_t)0x802816e9,
+    (q31_t)0x64e2009, (q31_t)0x8027c786,
+  (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x64192eb, (q31_t)0x802729ad, (q31_t)0x63b4c57, (q31_t)0x8026db36,
+    (q31_t)0x63505be, (q31_t)0x80268d0e,
+  (q31_t)0x62ebf22, (q31_t)0x80263f36, (q31_t)0x6287882, (q31_t)0x8025f1ac, (q31_t)0x62231de, (q31_t)0x8025a471,
+    (q31_t)0x61beb36, (q31_t)0x80255784,
+  (q31_t)0x615a48b, (q31_t)0x80250ae7, (q31_t)0x60f5ddc, (q31_t)0x8024be99, (q31_t)0x6091729, (q31_t)0x80247299,
+    (q31_t)0x602d072, (q31_t)0x802426e8,
+  (q31_t)0x5fc89b8, (q31_t)0x8023db86, (q31_t)0x5f642fa, (q31_t)0x80239073, (q31_t)0x5effc38, (q31_t)0x802345af,
+    (q31_t)0x5e9b572, (q31_t)0x8022fb3a,
+  (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x5dd27dd, (q31_t)0x8022673c, (q31_t)0x5d6e10c, (q31_t)0x80221db3,
+    (q31_t)0x5d09a38, (q31_t)0x8021d47a,
+  (q31_t)0x5ca5361, (q31_t)0x80218b8f, (q31_t)0x5c40c86, (q31_t)0x802142f3, (q31_t)0x5bdc5a7, (q31_t)0x8020faa6,
+    (q31_t)0x5b77ec5, (q31_t)0x8020b2a7,
+  (q31_t)0x5b137df, (q31_t)0x80206af8, (q31_t)0x5aaf0f6, (q31_t)0x80202397, (q31_t)0x5a4aa09, (q31_t)0x801fdc86,
+    (q31_t)0x59e6319, (q31_t)0x801f95c3,
+  (q31_t)0x5981c26, (q31_t)0x801f4f4f, (q31_t)0x591d52f, (q31_t)0x801f092a, (q31_t)0x58b8e34, (q31_t)0x801ec354,
+    (q31_t)0x5854736, (q31_t)0x801e7dcd,
+  (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x578b930, (q31_t)0x801df3ab, (q31_t)0x5727228, (q31_t)0x801daf11,
+    (q31_t)0x56c2b1c, (q31_t)0x801d6ac5,
+  (q31_t)0x565e40d, (q31_t)0x801d26c8, (q31_t)0x55f9cfb, (q31_t)0x801ce31a, (q31_t)0x55955e6, (q31_t)0x801c9fbb,
+    (q31_t)0x5530ecd, (q31_t)0x801c5cab,
+  (q31_t)0x54cc7b1, (q31_t)0x801c19ea, (q31_t)0x5468092, (q31_t)0x801bd777, (q31_t)0x540396f, (q31_t)0x801b9554,
+    (q31_t)0x539f249, (q31_t)0x801b537f,
+  (q31_t)0x533ab20, (q31_t)0x801b11fa, (q31_t)0x52d63f4, (q31_t)0x801ad0c3, (q31_t)0x5271cc4, (q31_t)0x801a8fdb,
+    (q31_t)0x520d592, (q31_t)0x801a4f42,
+  (q31_t)0x51a8e5c, (q31_t)0x801a0ef8, (q31_t)0x5144723, (q31_t)0x8019cefd, (q31_t)0x50dffe7, (q31_t)0x80198f50,
+    (q31_t)0x507b8a8, (q31_t)0x80194ff3,
+  (q31_t)0x5017165, (q31_t)0x801910e4, (q31_t)0x4fb2a20, (q31_t)0x8018d225, (q31_t)0x4f4e2d8, (q31_t)0x801893b4,
+    (q31_t)0x4ee9b8c, (q31_t)0x80185592,
+  (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4e20cec, (q31_t)0x8017da3b, (q31_t)0x4dbc597, (q31_t)0x80179d06,
+    (q31_t)0x4d57e40, (q31_t)0x80176020,
+  (q31_t)0x4cf36e5, (q31_t)0x80172388, (q31_t)0x4c8ef88, (q31_t)0x8016e740, (q31_t)0x4c2a827, (q31_t)0x8016ab46,
+    (q31_t)0x4bc60c4, (q31_t)0x80166f9c,
+  (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x4afd1f4, (q31_t)0x8015f933, (q31_t)0x4a98a88, (q31_t)0x8015be75,
+    (q31_t)0x4a34319, (q31_t)0x80158406,
+  (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x496b432, (q31_t)0x80151015, (q31_t)0x4906cbb, (q31_t)0x8014d693,
+    (q31_t)0x48a2540, (q31_t)0x80149d5f,
+  (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x47d9643, (q31_t)0x80142be5, (q31_t)0x4774ec1, (q31_t)0x8013f39e,
+    (q31_t)0x471073b, (q31_t)0x8013bba7,
+  (q31_t)0x46abfb3, (q31_t)0x801383fe, (q31_t)0x4647828, (q31_t)0x80134ca4, (q31_t)0x45e309a, (q31_t)0x80131599,
+    (q31_t)0x457e90a, (q31_t)0x8012dedd,
+  (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x44b59e1, (q31_t)0x80127251, (q31_t)0x4451249, (q31_t)0x80123c82,
+    (q31_t)0x43ecaae, (q31_t)0x80120701,
+  (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x4323b70, (q31_t)0x80119ced, (q31_t)0x42bf3cd, (q31_t)0x80116859,
+    (q31_t)0x425ac28, (q31_t)0x80113414,
+  (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x4191cd5, (q31_t)0x8010cc78, (q31_t)0x412d528, (q31_t)0x8010991f,
+    (q31_t)0x40c8d79, (q31_t)0x80106616,
+  (q31_t)0x40645c7, (q31_t)0x8010335c, (q31_t)0x3fffe12, (q31_t)0x801000f1, (q31_t)0x3f9b65b, (q31_t)0x800fced4,
+    (q31_t)0x3f36ea2, (q31_t)0x800f9d07,
+  (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3e6df28, (q31_t)0x800f3a59, (q31_t)0x3e09767, (q31_t)0x800f0978,
+    (q31_t)0x3da4fa4, (q31_t)0x800ed8e6,
+  (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3cdc017, (q31_t)0x800e78af, (q31_t)0x3c7784d, (q31_t)0x800e490a,
+    (q31_t)0x3c13080, (q31_t)0x800e19b4,
+  (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3b4a0e0, (q31_t)0x800dbbf5, (q31_t)0x3ae590d, (q31_t)0x800d8d8b,
+    (q31_t)0x3a81137, (q31_t)0x800d5f71,
+  (q31_t)0x3a1c960, (q31_t)0x800d31a5, (q31_t)0x39b8185, (q31_t)0x800d0429, (q31_t)0x39539a9, (q31_t)0x800cd6fb,
+    (q31_t)0x38ef1ca, (q31_t)0x800caa1c,
+  (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x3826207, (q31_t)0x800c514c, (q31_t)0x37c1a22, (q31_t)0x800c255a,
+    (q31_t)0x375d23a, (q31_t)0x800bf9b7,
+  (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3694265, (q31_t)0x800ba35d, (q31_t)0x362fa78, (q31_t)0x800b78a7,
+    (q31_t)0x35cb288, (q31_t)0x800b4e40,
+  (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x35022a2, (q31_t)0x800afa5e, (q31_t)0x349daac, (q31_t)0x800ad0e3,
+    (q31_t)0x34392b4, (q31_t)0x800aa7b8,
+  (q31_t)0x33d4abb, (q31_t)0x800a7edb, (q31_t)0x33702bf, (q31_t)0x800a564e, (q31_t)0x330bac1, (q31_t)0x800a2e0f,
+    (q31_t)0x32a72c1, (q31_t)0x800a061f,
+  (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x31de2bb, (q31_t)0x8009b72c, (q31_t)0x3179ab5, (q31_t)0x80099029,
+    (q31_t)0x31152ae, (q31_t)0x80096975,
+  (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x304c299, (q31_t)0x80091cf9, (q31_t)0x2fe7a8c, (q31_t)0x8008f732,
+    (q31_t)0x2f8327d, (q31_t)0x8008d1ba,
+  (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2eba259, (q31_t)0x800887b6, (q31_t)0x2e55a44, (q31_t)0x8008632a,
+    (q31_t)0x2df122e, (q31_t)0x80083eed,
+  (q31_t)0x2d8ca16, (q31_t)0x80081b00, (q31_t)0x2d281fc, (q31_t)0x8007f761, (q31_t)0x2cc39e1, (q31_t)0x8007d411,
+    (q31_t)0x2c5f1c3, (q31_t)0x8007b110,
+  (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2b96184, (q31_t)0x80076bfb, (q31_t)0x2b31961, (q31_t)0x800749e7,
+    (q31_t)0x2acd13d, (q31_t)0x80072822,
+  (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x2a040f0, (q31_t)0x8006e585, (q31_t)0x299f8c7, (q31_t)0x8006c4ac,
+    (q31_t)0x293b09c, (q31_t)0x8006a423,
+  (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x2872043, (q31_t)0x800663fd, (q31_t)0x280d813, (q31_t)0x80064460,
+    (q31_t)0x27a8fe2, (q31_t)0x80062513,
+  (q31_t)0x27447b0, (q31_t)0x80060614, (q31_t)0x26dff7c, (q31_t)0x8005e764, (q31_t)0x267b747, (q31_t)0x8005c904,
+    (q31_t)0x2616f10, (q31_t)0x8005aaf2,
+  (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x254de9e, (q31_t)0x80056fbb, (q31_t)0x24e9662, (q31_t)0x80055296,
+    (q31_t)0x2484e26, (q31_t)0x800535c0,
+  (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x23bbda8, (q31_t)0x8004fd00, (q31_t)0x2357567, (q31_t)0x8004e117,
+    (q31_t)0x22f2d25, (q31_t)0x8004c57d,
+  (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x2229c9d, (q31_t)0x80048f35, (q31_t)0x21c5457, (q31_t)0x80047488,
+    (q31_t)0x2160c0f, (q31_t)0x80045a29,
+  (q31_t)0x20fc3c6, (q31_t)0x8004401a, (q31_t)0x2097b7c, (q31_t)0x80042659, (q31_t)0x2033331, (q31_t)0x80040ce7,
+    (q31_t)0x1fceae4, (q31_t)0x8003f3c5,
+  (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1f05a48, (q31_t)0x8003c26c, (q31_t)0x1ea11f7, (q31_t)0x8003aa36,
+    (q31_t)0x1e3c9a6, (q31_t)0x8003924f,
+  (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1d73900, (q31_t)0x8003636e, (q31_t)0x1d0f0ab, (q31_t)0x80034c74,
+    (q31_t)0x1caa855, (q31_t)0x800335c9,
+  (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1be17a6, (q31_t)0x80030960, (q31_t)0x1b7cf4d, (q31_t)0x8002f3a1,
+    (q31_t)0x1b186f3, (q31_t)0x8002de32,
+  (q31_t)0x1ab3e97, (q31_t)0x8002c912, (q31_t)0x1a4f63b, (q31_t)0x8002b440, (q31_t)0x19eaddd, (q31_t)0x80029fbe,
+    (q31_t)0x198657f, (q31_t)0x80028b8a,
+  (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x18bd4bf, (q31_t)0x80026410, (q31_t)0x1858c5e, (q31_t)0x800250c9,
+    (q31_t)0x17f43fc, (q31_t)0x80023dd2,
+  (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x172b335, (q31_t)0x800218cf, (q31_t)0x16c6ad0, (q31_t)0x800206c4,
+    (q31_t)0x166226a, (q31_t)0x8001f508,
+  (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x159919c, (q31_t)0x8001d27d, (q31_t)0x1534934, (q31_t)0x8001c1ae,
+    (q31_t)0x14d00ca, (q31_t)0x8001b12e,
+  (q31_t)0x146b860, (q31_t)0x8001a0fd, (q31_t)0x1406ff6, (q31_t)0x8001911b, (q31_t)0x13a278a, (q31_t)0x80018187,
+    (q31_t)0x133df1e, (q31_t)0x80017243,
+  (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x1274e43, (q31_t)0x800154a7, (q31_t)0x12105d5, (q31_t)0x80014650,
+    (q31_t)0x11abd66, (q31_t)0x80013847,
+  (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x10e2c85, (q31_t)0x80011d23, (q31_t)0x107e414, (q31_t)0x80011008,
+    (q31_t)0x1019ba2, (q31_t)0x8001033b,
+  (q31_t)0xfb5330, (q31_t)0x8000f6bd, (q31_t)0xf50abd, (q31_t)0x8000ea8e, (q31_t)0xeec249, (q31_t)0x8000deaf, (q31_t)0xe879d5,
+    (q31_t)0x8000d31e,
+  (q31_t)0xe23160, (q31_t)0x8000c7dc, (q31_t)0xdbe8eb, (q31_t)0x8000bce9, (q31_t)0xd5a075, (q31_t)0x8000b245, (q31_t)0xcf57ff,
+    (q31_t)0x8000a7f0,
+  (q31_t)0xc90f88, (q31_t)0x80009dea, (q31_t)0xc2c711, (q31_t)0x80009433, (q31_t)0xbc7e99, (q31_t)0x80008aca, (q31_t)0xb63621,
+    (q31_t)0x800081b1,
+  (q31_t)0xafeda8, (q31_t)0x800078e7, (q31_t)0xa9a52f, (q31_t)0x8000706c, (q31_t)0xa35cb5, (q31_t)0x8000683f, (q31_t)0x9d143b,
+    (q31_t)0x80006062,
+  (q31_t)0x96cbc1, (q31_t)0x800058d4, (q31_t)0x908346, (q31_t)0x80005194, (q31_t)0x8a3acb, (q31_t)0x80004aa4, (q31_t)0x83f250,
+    (q31_t)0x80004402,
+  (q31_t)0x7da9d4, (q31_t)0x80003daf, (q31_t)0x776159, (q31_t)0x800037ac, (q31_t)0x7118dc, (q31_t)0x800031f7, (q31_t)0x6ad060,
+    (q31_t)0x80002c91,
+  (q31_t)0x6487e3, (q31_t)0x8000277a, (q31_t)0x5e3f66, (q31_t)0x800022b3, (q31_t)0x57f6e9, (q31_t)0x80001e3a, (q31_t)0x51ae6b,
+    (q31_t)0x80001a10,
+  (q31_t)0x4b65ee, (q31_t)0x80001635, (q31_t)0x451d70, (q31_t)0x800012a9, (q31_t)0x3ed4f2, (q31_t)0x80000f6c, (q31_t)0x388c74,
+    (q31_t)0x80000c7e,
+  (q31_t)0x3243f5, (q31_t)0x800009df, (q31_t)0x2bfb77, (q31_t)0x8000078e, (q31_t)0x25b2f8, (q31_t)0x8000058d, (q31_t)0x1f6a7a,
+    (q31_t)0x800003db,
+  (q31_t)0x1921fb, (q31_t)0x80000278, (q31_t)0x12d97c, (q31_t)0x80000163, (q31_t)0xc90fe, (q31_t)0x8000009e, (q31_t)0x6487f,
+    (q31_t)0x80000027
+
+};
+
+/**
+* \par
+* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))

+* \par
+* C command to generate the table
+* 
+* for(i = 0; i< N; i++)
+* {
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* } 

+* \par
+* where N is the number of factors to generate and c is pi/(2*N)
+* \par
+* Then converted to q31 format by multiplying with 2^31 and saturated if required.
+*/
+
+
+static const q31_t cos_factorsQ31_128[128] = {
+  (q31_t)0x7fff6216, (q31_t)0x7ffa72d1, (q31_t)0x7ff09478, (q31_t)0x7fe1c76b, (q31_t)0x7fce0c3e, (q31_t)0x7fb563b3,
+  (q31_t)0x7f97cebd, (q31_t)0x7f754e80,
+  (q31_t)0x7f4de451, (q31_t)0x7f2191b4, (q31_t)0x7ef05860, (q31_t)0x7eba3a39, (q31_t)0x7e7f3957, (q31_t)0x7e3f57ff,
+  (q31_t)0x7dfa98a8, (q31_t)0x7db0fdf8,
+  (q31_t)0x7d628ac6, (q31_t)0x7d0f4218, (q31_t)0x7cb72724, (q31_t)0x7c5a3d50, (q31_t)0x7bf88830, (q31_t)0x7b920b89,
+  (q31_t)0x7b26cb4f, (q31_t)0x7ab6cba4,
+  (q31_t)0x7a4210d8, (q31_t)0x79c89f6e, (q31_t)0x794a7c12, (q31_t)0x78c7aba2, (q31_t)0x78403329, (q31_t)0x77b417df,
+  (q31_t)0x77235f2d, (q31_t)0x768e0ea6,
+  (q31_t)0x75f42c0b, (q31_t)0x7555bd4c, (q31_t)0x74b2c884, (q31_t)0x740b53fb, (q31_t)0x735f6626, (q31_t)0x72af05a7,
+  (q31_t)0x71fa3949, (q31_t)0x71410805,
+  (q31_t)0x708378ff, (q31_t)0x6fc19385, (q31_t)0x6efb5f12, (q31_t)0x6e30e34a, (q31_t)0x6d6227fa, (q31_t)0x6c8f351c,
+  (q31_t)0x6bb812d1, (q31_t)0x6adcc964,
+  (q31_t)0x69fd614a, (q31_t)0x6919e320, (q31_t)0x683257ab, (q31_t)0x6746c7d8, (q31_t)0x66573cbb, (q31_t)0x6563bf92,
+  (q31_t)0x646c59bf, (q31_t)0x637114cc,
+  (q31_t)0x6271fa69, (q31_t)0x616f146c, (q31_t)0x60686ccf, (q31_t)0x5f5e0db3, (q31_t)0x5e50015d, (q31_t)0x5d3e5237,
+  (q31_t)0x5c290acc, (q31_t)0x5b1035cf,
+  (q31_t)0x59f3de12, (q31_t)0x58d40e8c, (q31_t)0x57b0d256, (q31_t)0x568a34a9, (q31_t)0x556040e2, (q31_t)0x5433027d,
+  (q31_t)0x53028518, (q31_t)0x51ced46e,
+  (q31_t)0x5097fc5e, (q31_t)0x4f5e08e3, (q31_t)0x4e210617, (q31_t)0x4ce10034, (q31_t)0x4b9e0390, (q31_t)0x4a581c9e,
+  (q31_t)0x490f57ee, (q31_t)0x47c3c22f,
+  (q31_t)0x46756828, (q31_t)0x452456bd, (q31_t)0x43d09aed, (q31_t)0x427a41d0, (q31_t)0x4121589b, (q31_t)0x3fc5ec98,
+  (q31_t)0x3e680b2c, (q31_t)0x3d07c1d6,
+  (q31_t)0x3ba51e29, (q31_t)0x3a402dd2, (q31_t)0x38d8fe93, (q31_t)0x376f9e46, (q31_t)0x36041ad9, (q31_t)0x34968250,
+  (q31_t)0x3326e2c3, (q31_t)0x31b54a5e,
+  (q31_t)0x3041c761, (q31_t)0x2ecc681e, (q31_t)0x2d553afc, (q31_t)0x2bdc4e6f, (q31_t)0x2a61b101, (q31_t)0x28e5714b,
+  (q31_t)0x27679df4, (q31_t)0x25e845b6,
+  (q31_t)0x24677758, (q31_t)0x22e541af, (q31_t)0x2161b3a0, (q31_t)0x1fdcdc1b, (q31_t)0x1e56ca1e, (q31_t)0x1ccf8cb3,
+  (q31_t)0x1b4732ef, (q31_t)0x19bdcbf3,
+  (q31_t)0x183366e9, (q31_t)0x16a81305, (q31_t)0x151bdf86, (q31_t)0x138edbb1, (q31_t)0x120116d5, (q31_t)0x1072a048,
+  (q31_t)0xee38766, (q31_t)0xd53db92,
+  (q31_t)0xbc3ac35, (q31_t)0xa3308bd, (q31_t)0x8a2009a, (q31_t)0x710a345, (q31_t)0x57f0035, (q31_t)0x3ed26e6, (q31_t)0x25b26d7,
+  (q31_t)0xc90f88
+};
+
+static const q31_t cos_factorsQ31_512[512] = {
+  (q31_t)0x7ffff621, (q31_t)0x7fffa72c, (q31_t)0x7fff0943, (q31_t)0x7ffe1c65, (q31_t)0x7ffce093, (q31_t)0x7ffb55ce,
+  (q31_t)0x7ff97c18, (q31_t)0x7ff75370,
+  (q31_t)0x7ff4dbd9, (q31_t)0x7ff21553, (q31_t)0x7feeffe1, (q31_t)0x7feb9b85, (q31_t)0x7fe7e841, (q31_t)0x7fe3e616,
+  (q31_t)0x7fdf9508, (q31_t)0x7fdaf519,
+  (q31_t)0x7fd6064c, (q31_t)0x7fd0c8a3, (q31_t)0x7fcb3c23, (q31_t)0x7fc560cf, (q31_t)0x7fbf36aa, (q31_t)0x7fb8bdb8,
+  (q31_t)0x7fb1f5fc, (q31_t)0x7faadf7c,
+  (q31_t)0x7fa37a3c, (q31_t)0x7f9bc640, (q31_t)0x7f93c38c, (q31_t)0x7f8b7227, (q31_t)0x7f82d214, (q31_t)0x7f79e35a,
+  (q31_t)0x7f70a5fe, (q31_t)0x7f671a05,
+  (q31_t)0x7f5d3f75, (q31_t)0x7f531655, (q31_t)0x7f489eaa, (q31_t)0x7f3dd87c, (q31_t)0x7f32c3d1, (q31_t)0x7f2760af,
+  (q31_t)0x7f1baf1e, (q31_t)0x7f0faf25,
+  (q31_t)0x7f0360cb, (q31_t)0x7ef6c418, (q31_t)0x7ee9d914, (q31_t)0x7edc9fc6, (q31_t)0x7ecf1837, (q31_t)0x7ec14270,
+  (q31_t)0x7eb31e78, (q31_t)0x7ea4ac58,
+  (q31_t)0x7e95ec1a, (q31_t)0x7e86ddc6, (q31_t)0x7e778166, (q31_t)0x7e67d703, (q31_t)0x7e57dea7, (q31_t)0x7e47985b,
+  (q31_t)0x7e37042a, (q31_t)0x7e26221f,
+  (q31_t)0x7e14f242, (q31_t)0x7e0374a0, (q31_t)0x7df1a942, (q31_t)0x7ddf9034, (q31_t)0x7dcd2981, (q31_t)0x7dba7534,
+  (q31_t)0x7da77359, (q31_t)0x7d9423fc,
+  (q31_t)0x7d808728, (q31_t)0x7d6c9ce9, (q31_t)0x7d58654d, (q31_t)0x7d43e05e, (q31_t)0x7d2f0e2b, (q31_t)0x7d19eebf,
+  (q31_t)0x7d048228, (q31_t)0x7ceec873,
+  (q31_t)0x7cd8c1ae, (q31_t)0x7cc26de5, (q31_t)0x7cabcd28, (q31_t)0x7c94df83, (q31_t)0x7c7da505, (q31_t)0x7c661dbc,
+  (q31_t)0x7c4e49b7, (q31_t)0x7c362904,
+  (q31_t)0x7c1dbbb3, (q31_t)0x7c0501d2, (q31_t)0x7bebfb70, (q31_t)0x7bd2a89e, (q31_t)0x7bb9096b, (q31_t)0x7b9f1de6,
+  (q31_t)0x7b84e61f, (q31_t)0x7b6a6227,
+  (q31_t)0x7b4f920e, (q31_t)0x7b3475e5, (q31_t)0x7b190dbc, (q31_t)0x7afd59a4, (q31_t)0x7ae159ae, (q31_t)0x7ac50dec,
+  (q31_t)0x7aa8766f, (q31_t)0x7a8b9348,
+  (q31_t)0x7a6e648a, (q31_t)0x7a50ea47, (q31_t)0x7a332490, (q31_t)0x7a151378, (q31_t)0x79f6b711, (q31_t)0x79d80f6f,
+  (q31_t)0x79b91ca4, (q31_t)0x7999dec4,
+  (q31_t)0x797a55e0, (q31_t)0x795a820e, (q31_t)0x793a6361, (q31_t)0x7919f9ec, (q31_t)0x78f945c3, (q31_t)0x78d846fb,
+  (q31_t)0x78b6fda8, (q31_t)0x789569df,
+  (q31_t)0x78738bb3, (q31_t)0x7851633b, (q31_t)0x782ef08b, (q31_t)0x780c33b8, (q31_t)0x77e92cd9, (q31_t)0x77c5dc01,
+  (q31_t)0x77a24148, (q31_t)0x777e5cc3,
+  (q31_t)0x775a2e89, (q31_t)0x7735b6af, (q31_t)0x7710f54c, (q31_t)0x76ebea77, (q31_t)0x76c69647, (q31_t)0x76a0f8d2,
+  (q31_t)0x767b1231, (q31_t)0x7654e279,
+  (q31_t)0x762e69c4, (q31_t)0x7607a828, (q31_t)0x75e09dbd, (q31_t)0x75b94a9c, (q31_t)0x7591aedd, (q31_t)0x7569ca99,
+  (q31_t)0x75419de7, (q31_t)0x751928e0,
+  (q31_t)0x74f06b9e, (q31_t)0x74c7663a, (q31_t)0x749e18cd, (q31_t)0x74748371, (q31_t)0x744aa63f, (q31_t)0x74208150,
+  (q31_t)0x73f614c0, (q31_t)0x73cb60a8,
+  (q31_t)0x73a06522, (q31_t)0x73752249, (q31_t)0x73499838, (q31_t)0x731dc70a, (q31_t)0x72f1aed9, (q31_t)0x72c54fc1,
+  (q31_t)0x7298a9dd, (q31_t)0x726bbd48,
+  (q31_t)0x723e8a20, (q31_t)0x7211107e, (q31_t)0x71e35080, (q31_t)0x71b54a41, (q31_t)0x7186fdde, (q31_t)0x71586b74,
+  (q31_t)0x7129931f, (q31_t)0x70fa74fc,
+  (q31_t)0x70cb1128, (q31_t)0x709b67c0, (q31_t)0x706b78e3, (q31_t)0x703b44ad, (q31_t)0x700acb3c, (q31_t)0x6fda0cae,
+  (q31_t)0x6fa90921, (q31_t)0x6f77c0b3,
+  (q31_t)0x6f463383, (q31_t)0x6f1461b0, (q31_t)0x6ee24b57, (q31_t)0x6eaff099, (q31_t)0x6e7d5193, (q31_t)0x6e4a6e66,
+  (q31_t)0x6e174730, (q31_t)0x6de3dc11,
+  (q31_t)0x6db02d29, (q31_t)0x6d7c3a98, (q31_t)0x6d48047e, (q31_t)0x6d138afb, (q31_t)0x6cdece2f, (q31_t)0x6ca9ce3b,
+  (q31_t)0x6c748b3f, (q31_t)0x6c3f055d,
+  (q31_t)0x6c093cb6, (q31_t)0x6bd3316a, (q31_t)0x6b9ce39b, (q31_t)0x6b66536b, (q31_t)0x6b2f80fb, (q31_t)0x6af86c6c,
+  (q31_t)0x6ac115e2, (q31_t)0x6a897d7d,
+  (q31_t)0x6a51a361, (q31_t)0x6a1987b0, (q31_t)0x69e12a8c, (q31_t)0x69a88c19, (q31_t)0x696fac78, (q31_t)0x69368bce,
+  (q31_t)0x68fd2a3d, (q31_t)0x68c387e9,
+  (q31_t)0x6889a4f6, (q31_t)0x684f8186, (q31_t)0x68151dbe, (q31_t)0x67da79c3, (q31_t)0x679f95b7, (q31_t)0x676471c0,
+  (q31_t)0x67290e02, (q31_t)0x66ed6aa1,
+  (q31_t)0x66b187c3, (q31_t)0x6675658c, (q31_t)0x66390422, (q31_t)0x65fc63a9, (q31_t)0x65bf8447, (q31_t)0x65826622,
+  (q31_t)0x6545095f, (q31_t)0x65076e25,
+  (q31_t)0x64c99498, (q31_t)0x648b7ce0, (q31_t)0x644d2722, (q31_t)0x640e9386, (q31_t)0x63cfc231, (q31_t)0x6390b34a,
+  (q31_t)0x635166f9, (q31_t)0x6311dd64,
+  (q31_t)0x62d216b3, (q31_t)0x6292130c, (q31_t)0x6251d298, (q31_t)0x6211557e, (q31_t)0x61d09be5, (q31_t)0x618fa5f7,
+  (q31_t)0x614e73da, (q31_t)0x610d05b7,
+  (q31_t)0x60cb5bb7, (q31_t)0x60897601, (q31_t)0x604754bf, (q31_t)0x6004f819, (q31_t)0x5fc26038, (q31_t)0x5f7f8d46,
+  (q31_t)0x5f3c7f6b, (q31_t)0x5ef936d1,
+  (q31_t)0x5eb5b3a2, (q31_t)0x5e71f606, (q31_t)0x5e2dfe29, (q31_t)0x5de9cc33, (q31_t)0x5da5604f, (q31_t)0x5d60baa7,
+  (q31_t)0x5d1bdb65, (q31_t)0x5cd6c2b5,
+  (q31_t)0x5c9170bf, (q31_t)0x5c4be5b0, (q31_t)0x5c0621b2, (q31_t)0x5bc024f0, (q31_t)0x5b79ef96, (q31_t)0x5b3381ce,
+  (q31_t)0x5aecdbc5, (q31_t)0x5aa5fda5,
+  (q31_t)0x5a5ee79a, (q31_t)0x5a1799d1, (q31_t)0x59d01475, (q31_t)0x598857b2, (q31_t)0x594063b5, (q31_t)0x58f838a9,
+  (q31_t)0x58afd6bd, (q31_t)0x58673e1b,
+  (q31_t)0x581e6ef1, (q31_t)0x57d5696d, (q31_t)0x578c2dba, (q31_t)0x5742bc06, (q31_t)0x56f9147e, (q31_t)0x56af3750,
+  (q31_t)0x566524aa, (q31_t)0x561adcb9,
+  (q31_t)0x55d05faa, (q31_t)0x5585adad, (q31_t)0x553ac6ee, (q31_t)0x54efab9c, (q31_t)0x54a45be6, (q31_t)0x5458d7f9,
+  (q31_t)0x540d2005, (q31_t)0x53c13439,
+  (q31_t)0x537514c2, (q31_t)0x5328c1d0, (q31_t)0x52dc3b92, (q31_t)0x528f8238, (q31_t)0x524295f0, (q31_t)0x51f576ea,
+  (q31_t)0x51a82555, (q31_t)0x515aa162,
+  (q31_t)0x510ceb40, (q31_t)0x50bf031f, (q31_t)0x5070e92f, (q31_t)0x50229da1, (q31_t)0x4fd420a4, (q31_t)0x4f857269,
+  (q31_t)0x4f369320, (q31_t)0x4ee782fb,
+  (q31_t)0x4e984229, (q31_t)0x4e48d0dd, (q31_t)0x4df92f46, (q31_t)0x4da95d96, (q31_t)0x4d595bfe, (q31_t)0x4d092ab0,
+  (q31_t)0x4cb8c9dd, (q31_t)0x4c6839b7,
+  (q31_t)0x4c177a6e, (q31_t)0x4bc68c36, (q31_t)0x4b756f40, (q31_t)0x4b2423be, (q31_t)0x4ad2a9e2, (q31_t)0x4a8101de,
+  (q31_t)0x4a2f2be6, (q31_t)0x49dd282a,
+  (q31_t)0x498af6df, (q31_t)0x49389836, (q31_t)0x48e60c62, (q31_t)0x48935397, (q31_t)0x48406e08, (q31_t)0x47ed5be6,
+  (q31_t)0x479a1d67, (q31_t)0x4746b2bc,
+  (q31_t)0x46f31c1a, (q31_t)0x469f59b4, (q31_t)0x464b6bbe, (q31_t)0x45f7526b, (q31_t)0x45a30df0, (q31_t)0x454e9e80,
+  (q31_t)0x44fa0450, (q31_t)0x44a53f93,
+  (q31_t)0x4450507e, (q31_t)0x43fb3746, (q31_t)0x43a5f41e, (q31_t)0x4350873c, (q31_t)0x42faf0d4, (q31_t)0x42a5311b,
+  (q31_t)0x424f4845, (q31_t)0x41f93689,
+  (q31_t)0x41a2fc1a, (q31_t)0x414c992f, (q31_t)0x40f60dfb, (q31_t)0x409f5ab6, (q31_t)0x40487f94, (q31_t)0x3ff17cca,
+  (q31_t)0x3f9a5290, (q31_t)0x3f430119,
+  (q31_t)0x3eeb889c, (q31_t)0x3e93e950, (q31_t)0x3e3c2369, (q31_t)0x3de4371f, (q31_t)0x3d8c24a8, (q31_t)0x3d33ec39,
+  (q31_t)0x3cdb8e09, (q31_t)0x3c830a50,
+  (q31_t)0x3c2a6142, (q31_t)0x3bd19318, (q31_t)0x3b78a007, (q31_t)0x3b1f8848, (q31_t)0x3ac64c0f, (q31_t)0x3a6ceb96,
+  (q31_t)0x3a136712, (q31_t)0x39b9bebc,
+  (q31_t)0x395ff2c9, (q31_t)0x39060373, (q31_t)0x38abf0ef, (q31_t)0x3851bb77, (q31_t)0x37f76341, (q31_t)0x379ce885,
+  (q31_t)0x37424b7b, (q31_t)0x36e78c5b,
+  (q31_t)0x368cab5c, (q31_t)0x3631a8b8, (q31_t)0x35d684a6, (q31_t)0x357b3f5d, (q31_t)0x351fd918, (q31_t)0x34c4520d,
+  (q31_t)0x3468aa76, (q31_t)0x340ce28b,
+  (q31_t)0x33b0fa84, (q31_t)0x3354f29b, (q31_t)0x32f8cb07, (q31_t)0x329c8402, (q31_t)0x32401dc6, (q31_t)0x31e39889,
+  (q31_t)0x3186f487, (q31_t)0x312a31f8,
+  (q31_t)0x30cd5115, (q31_t)0x30705217, (q31_t)0x30133539, (q31_t)0x2fb5fab2, (q31_t)0x2f58a2be, (q31_t)0x2efb2d95,
+  (q31_t)0x2e9d9b70, (q31_t)0x2e3fec8b,
+  (q31_t)0x2de2211e, (q31_t)0x2d843964, (q31_t)0x2d263596, (q31_t)0x2cc815ee, (q31_t)0x2c69daa6, (q31_t)0x2c0b83fa,
+  (q31_t)0x2bad1221, (q31_t)0x2b4e8558,
+  (q31_t)0x2aefddd8, (q31_t)0x2a911bdc, (q31_t)0x2a323f9e, (q31_t)0x29d34958, (q31_t)0x29743946, (q31_t)0x29150fa1,
+  (q31_t)0x28b5cca5, (q31_t)0x2856708d,
+  (q31_t)0x27f6fb92, (q31_t)0x27976df1, (q31_t)0x2737c7e3, (q31_t)0x26d809a5, (q31_t)0x26783370, (q31_t)0x26184581,
+  (q31_t)0x25b84012, (q31_t)0x2558235f,
+  (q31_t)0x24f7efa2, (q31_t)0x2497a517, (q31_t)0x243743fa, (q31_t)0x23d6cc87, (q31_t)0x23763ef7, (q31_t)0x23159b88,
+  (q31_t)0x22b4e274, (q31_t)0x225413f8,
+  (q31_t)0x21f3304f, (q31_t)0x219237b5, (q31_t)0x21312a65, (q31_t)0x20d0089c, (q31_t)0x206ed295, (q31_t)0x200d888d,
+  (q31_t)0x1fac2abf, (q31_t)0x1f4ab968,
+  (q31_t)0x1ee934c3, (q31_t)0x1e879d0d, (q31_t)0x1e25f282, (q31_t)0x1dc4355e, (q31_t)0x1d6265dd, (q31_t)0x1d00843d,
+  (q31_t)0x1c9e90b8, (q31_t)0x1c3c8b8c,
+  (q31_t)0x1bda74f6, (q31_t)0x1b784d30, (q31_t)0x1b161479, (q31_t)0x1ab3cb0d, (q31_t)0x1a517128, (q31_t)0x19ef0707,
+  (q31_t)0x198c8ce7, (q31_t)0x192a0304,
+  (q31_t)0x18c7699b, (q31_t)0x1864c0ea, (q31_t)0x1802092c, (q31_t)0x179f429f, (q31_t)0x173c6d80, (q31_t)0x16d98a0c,
+  (q31_t)0x1676987f, (q31_t)0x16139918,
+  (q31_t)0x15b08c12, (q31_t)0x154d71aa, (q31_t)0x14ea4a1f, (q31_t)0x148715ae, (q31_t)0x1423d492, (q31_t)0x13c0870a,
+  (q31_t)0x135d2d53, (q31_t)0x12f9c7aa,
+  (q31_t)0x1296564d, (q31_t)0x1232d979, (q31_t)0x11cf516a, (q31_t)0x116bbe60, (q31_t)0x11082096, (q31_t)0x10a4784b,
+  (q31_t)0x1040c5bb, (q31_t)0xfdd0926,
+  (q31_t)0xf7942c7, (q31_t)0xf1572dc, (q31_t)0xeb199a4, (q31_t)0xe4db75b, (q31_t)0xde9cc40, (q31_t)0xd85d88f, (q31_t)0xd21dc87,
+  (q31_t)0xcbdd865,
+  (q31_t)0xc59cc68, (q31_t)0xbf5b8cb, (q31_t)0xb919dcf, (q31_t)0xb2d7baf, (q31_t)0xac952aa, (q31_t)0xa6522fe, (q31_t)0xa00ece8,
+  (q31_t)0x99cb0a7,
+  (q31_t)0x9386e78, (q31_t)0x8d42699, (q31_t)0x86fd947, (q31_t)0x80b86c2, (q31_t)0x7a72f45, (q31_t)0x742d311, (q31_t)0x6de7262,
+  (q31_t)0x67a0d76,
+  (q31_t)0x615a48b, (q31_t)0x5b137df, (q31_t)0x54cc7b1, (q31_t)0x4e8543e, (q31_t)0x483ddc3, (q31_t)0x41f6480, (q31_t)0x3bae8b2,
+  (q31_t)0x3566a96,
+  (q31_t)0x2f1ea6c, (q31_t)0x28d6870, (q31_t)0x228e4e2, (q31_t)0x1c45ffe, (q31_t)0x15fda03, (q31_t)0xfb5330, (q31_t)0x96cbc1,
+  (q31_t)0x3243f5
+};
+
+static const q31_t cos_factorsQ31_2048[2048] = {
+  (q31_t)0x7fffff62, (q31_t)0x7ffffa73, (q31_t)0x7ffff094, (q31_t)0x7fffe1c6, (q31_t)0x7fffce09, (q31_t)0x7fffb55c,
+  (q31_t)0x7fff97c1, (q31_t)0x7fff7536,
+  (q31_t)0x7fff4dbb, (q31_t)0x7fff2151, (q31_t)0x7ffeeff8, (q31_t)0x7ffeb9b0, (q31_t)0x7ffe7e79, (q31_t)0x7ffe3e52,
+  (q31_t)0x7ffdf93c, (q31_t)0x7ffdaf37,
+  (q31_t)0x7ffd6042, (q31_t)0x7ffd0c5f, (q31_t)0x7ffcb38c, (q31_t)0x7ffc55ca, (q31_t)0x7ffbf319, (q31_t)0x7ffb8b78,
+  (q31_t)0x7ffb1ee9, (q31_t)0x7ffaad6a,
+  (q31_t)0x7ffa36fc, (q31_t)0x7ff9bba0, (q31_t)0x7ff93b54, (q31_t)0x7ff8b619, (q31_t)0x7ff82bef, (q31_t)0x7ff79cd6,
+  (q31_t)0x7ff708ce, (q31_t)0x7ff66fd7,
+  (q31_t)0x7ff5d1f1, (q31_t)0x7ff52f1d, (q31_t)0x7ff48759, (q31_t)0x7ff3daa6, (q31_t)0x7ff32905, (q31_t)0x7ff27275,
+  (q31_t)0x7ff1b6f6, (q31_t)0x7ff0f688,
+  (q31_t)0x7ff0312c, (q31_t)0x7fef66e1, (q31_t)0x7fee97a7, (q31_t)0x7fedc37e, (q31_t)0x7fecea67, (q31_t)0x7fec0c62,
+  (q31_t)0x7feb296d, (q31_t)0x7fea418b,
+  (q31_t)0x7fe954ba, (q31_t)0x7fe862fa, (q31_t)0x7fe76c4c, (q31_t)0x7fe670b0, (q31_t)0x7fe57025, (q31_t)0x7fe46aac,
+  (q31_t)0x7fe36045, (q31_t)0x7fe250ef,
+  (q31_t)0x7fe13cac, (q31_t)0x7fe0237a, (q31_t)0x7fdf055a, (q31_t)0x7fdde24d, (q31_t)0x7fdcba51, (q31_t)0x7fdb8d67,
+  (q31_t)0x7fda5b8f, (q31_t)0x7fd924ca,
+  (q31_t)0x7fd7e917, (q31_t)0x7fd6a875, (q31_t)0x7fd562e7, (q31_t)0x7fd4186a, (q31_t)0x7fd2c900, (q31_t)0x7fd174a8,
+  (q31_t)0x7fd01b63, (q31_t)0x7fcebd31,
+  (q31_t)0x7fcd5a11, (q31_t)0x7fcbf203, (q31_t)0x7fca8508, (q31_t)0x7fc91320, (q31_t)0x7fc79c4b, (q31_t)0x7fc62089,
+  (q31_t)0x7fc49fda, (q31_t)0x7fc31a3d,
+  (q31_t)0x7fc18fb4, (q31_t)0x7fc0003e, (q31_t)0x7fbe6bdb, (q31_t)0x7fbcd28b, (q31_t)0x7fbb344e, (q31_t)0x7fb99125,
+  (q31_t)0x7fb7e90f, (q31_t)0x7fb63c0d,
+  (q31_t)0x7fb48a1e, (q31_t)0x7fb2d343, (q31_t)0x7fb1177b, (q31_t)0x7faf56c7, (q31_t)0x7fad9127, (q31_t)0x7fabc69b,
+  (q31_t)0x7fa9f723, (q31_t)0x7fa822bf,
+  (q31_t)0x7fa6496e, (q31_t)0x7fa46b32, (q31_t)0x7fa2880b, (q31_t)0x7fa09ff7, (q31_t)0x7f9eb2f8, (q31_t)0x7f9cc10d,
+  (q31_t)0x7f9aca37, (q31_t)0x7f98ce76,
+  (q31_t)0x7f96cdc9, (q31_t)0x7f94c831, (q31_t)0x7f92bdad, (q31_t)0x7f90ae3f, (q31_t)0x7f8e99e6, (q31_t)0x7f8c80a1,
+  (q31_t)0x7f8a6272, (q31_t)0x7f883f58,
+  (q31_t)0x7f861753, (q31_t)0x7f83ea64, (q31_t)0x7f81b88a, (q31_t)0x7f7f81c6, (q31_t)0x7f7d4617, (q31_t)0x7f7b057e,
+  (q31_t)0x7f78bffb, (q31_t)0x7f76758e,
+  (q31_t)0x7f742637, (q31_t)0x7f71d1f6, (q31_t)0x7f6f78cb, (q31_t)0x7f6d1ab6, (q31_t)0x7f6ab7b8, (q31_t)0x7f684fd0,
+  (q31_t)0x7f65e2ff, (q31_t)0x7f637144,
+  (q31_t)0x7f60faa0, (q31_t)0x7f5e7f13, (q31_t)0x7f5bfe9d, (q31_t)0x7f59793e, (q31_t)0x7f56eef5, (q31_t)0x7f545fc5,
+  (q31_t)0x7f51cbab, (q31_t)0x7f4f32a9,
+  (q31_t)0x7f4c94be, (q31_t)0x7f49f1eb, (q31_t)0x7f474a30, (q31_t)0x7f449d8c, (q31_t)0x7f41ec01, (q31_t)0x7f3f358d,
+  (q31_t)0x7f3c7a31, (q31_t)0x7f39b9ee,
+  (q31_t)0x7f36f4c3, (q31_t)0x7f342ab1, (q31_t)0x7f315bb7, (q31_t)0x7f2e87d6, (q31_t)0x7f2baf0d, (q31_t)0x7f28d15d,
+  (q31_t)0x7f25eec7, (q31_t)0x7f230749,
+  (q31_t)0x7f201ae5, (q31_t)0x7f1d299a, (q31_t)0x7f1a3368, (q31_t)0x7f173850, (q31_t)0x7f143852, (q31_t)0x7f11336d,
+  (q31_t)0x7f0e29a3, (q31_t)0x7f0b1af2,
+  (q31_t)0x7f08075c, (q31_t)0x7f04eedf, (q31_t)0x7f01d17d, (q31_t)0x7efeaf36, (q31_t)0x7efb8809, (q31_t)0x7ef85bf7,
+  (q31_t)0x7ef52b00, (q31_t)0x7ef1f524,
+  (q31_t)0x7eeeba62, (q31_t)0x7eeb7abc, (q31_t)0x7ee83632, (q31_t)0x7ee4ecc3, (q31_t)0x7ee19e6f, (q31_t)0x7ede4b38,
+  (q31_t)0x7edaf31c, (q31_t)0x7ed7961c,
+  (q31_t)0x7ed43438, (q31_t)0x7ed0cd70, (q31_t)0x7ecd61c5, (q31_t)0x7ec9f137, (q31_t)0x7ec67bc5, (q31_t)0x7ec3016f,
+  (q31_t)0x7ebf8237, (q31_t)0x7ebbfe1c,
+  (q31_t)0x7eb8751e, (q31_t)0x7eb4e73d, (q31_t)0x7eb1547a, (q31_t)0x7eadbcd4, (q31_t)0x7eaa204c, (q31_t)0x7ea67ee2,
+  (q31_t)0x7ea2d896, (q31_t)0x7e9f2d68,
+  (q31_t)0x7e9b7d58, (q31_t)0x7e97c867, (q31_t)0x7e940e94, (q31_t)0x7e904fe0, (q31_t)0x7e8c8c4b, (q31_t)0x7e88c3d5,
+  (q31_t)0x7e84f67e, (q31_t)0x7e812447,
+  (q31_t)0x7e7d4d2f, (q31_t)0x7e797136, (q31_t)0x7e75905d, (q31_t)0x7e71aaa4, (q31_t)0x7e6dc00c, (q31_t)0x7e69d093,
+  (q31_t)0x7e65dc3b, (q31_t)0x7e61e303,
+  (q31_t)0x7e5de4ec, (q31_t)0x7e59e1f5, (q31_t)0x7e55da20, (q31_t)0x7e51cd6c, (q31_t)0x7e4dbbd9, (q31_t)0x7e49a567,
+  (q31_t)0x7e458a17, (q31_t)0x7e4169e9,
+  (q31_t)0x7e3d44dd, (q31_t)0x7e391af3, (q31_t)0x7e34ec2b, (q31_t)0x7e30b885, (q31_t)0x7e2c8002, (q31_t)0x7e2842a2,
+  (q31_t)0x7e240064, (q31_t)0x7e1fb94a,
+  (q31_t)0x7e1b6d53, (q31_t)0x7e171c7f, (q31_t)0x7e12c6ce, (q31_t)0x7e0e6c42, (q31_t)0x7e0a0cd9, (q31_t)0x7e05a894,
+  (q31_t)0x7e013f74, (q31_t)0x7dfcd178,
+  (q31_t)0x7df85ea0, (q31_t)0x7df3e6ee, (q31_t)0x7def6a60, (q31_t)0x7deae8f7, (q31_t)0x7de662b3, (q31_t)0x7de1d795,
+  (q31_t)0x7ddd479d, (q31_t)0x7dd8b2ca,
+  (q31_t)0x7dd4191d, (q31_t)0x7dcf7a96, (q31_t)0x7dcad736, (q31_t)0x7dc62efc, (q31_t)0x7dc181e8, (q31_t)0x7dbccffc,
+  (q31_t)0x7db81936, (q31_t)0x7db35d98,
+  (q31_t)0x7dae9d21, (q31_t)0x7da9d7d2, (q31_t)0x7da50dab, (q31_t)0x7da03eab, (q31_t)0x7d9b6ad3, (q31_t)0x7d969224,
+  (q31_t)0x7d91b49e, (q31_t)0x7d8cd240,
+  (q31_t)0x7d87eb0a, (q31_t)0x7d82fefe, (q31_t)0x7d7e0e1c, (q31_t)0x7d791862, (q31_t)0x7d741dd2, (q31_t)0x7d6f1e6c,
+  (q31_t)0x7d6a1a31, (q31_t)0x7d65111f,
+  (q31_t)0x7d600338, (q31_t)0x7d5af07b, (q31_t)0x7d55d8e9, (q31_t)0x7d50bc82, (q31_t)0x7d4b9b46, (q31_t)0x7d467536,
+  (q31_t)0x7d414a51, (q31_t)0x7d3c1a98,
+  (q31_t)0x7d36e60b, (q31_t)0x7d31acaa, (q31_t)0x7d2c6e76, (q31_t)0x7d272b6e, (q31_t)0x7d21e393, (q31_t)0x7d1c96e5,
+  (q31_t)0x7d174564, (q31_t)0x7d11ef11,
+  (q31_t)0x7d0c93eb, (q31_t)0x7d0733f3, (q31_t)0x7d01cf29, (q31_t)0x7cfc658d, (q31_t)0x7cf6f720, (q31_t)0x7cf183e1,
+  (q31_t)0x7cec0bd1, (q31_t)0x7ce68ef0,
+  (q31_t)0x7ce10d3f, (q31_t)0x7cdb86bd, (q31_t)0x7cd5fb6a, (q31_t)0x7cd06b48, (q31_t)0x7ccad656, (q31_t)0x7cc53c94,
+  (q31_t)0x7cbf9e03, (q31_t)0x7cb9faa2,
+  (q31_t)0x7cb45272, (q31_t)0x7caea574, (q31_t)0x7ca8f3a7, (q31_t)0x7ca33d0c, (q31_t)0x7c9d81a3, (q31_t)0x7c97c16b,
+  (q31_t)0x7c91fc66, (q31_t)0x7c8c3294,
+  (q31_t)0x7c8663f4, (q31_t)0x7c809088, (q31_t)0x7c7ab84e, (q31_t)0x7c74db48, (q31_t)0x7c6ef976, (q31_t)0x7c6912d7,
+  (q31_t)0x7c63276d, (q31_t)0x7c5d3737,
+  (q31_t)0x7c574236, (q31_t)0x7c514869, (q31_t)0x7c4b49d2, (q31_t)0x7c45466f, (q31_t)0x7c3f3e42, (q31_t)0x7c39314b,
+  (q31_t)0x7c331f8a, (q31_t)0x7c2d08ff,
+  (q31_t)0x7c26edab, (q31_t)0x7c20cd8d, (q31_t)0x7c1aa8a6, (q31_t)0x7c147ef6, (q31_t)0x7c0e507e, (q31_t)0x7c081d3d,
+  (q31_t)0x7c01e534, (q31_t)0x7bfba863,
+  (q31_t)0x7bf566cb, (q31_t)0x7bef206b, (q31_t)0x7be8d544, (q31_t)0x7be28556, (q31_t)0x7bdc30a1, (q31_t)0x7bd5d726,
+  (q31_t)0x7bcf78e5, (q31_t)0x7bc915dd,
+  (q31_t)0x7bc2ae10, (q31_t)0x7bbc417e, (q31_t)0x7bb5d026, (q31_t)0x7baf5a09, (q31_t)0x7ba8df28, (q31_t)0x7ba25f82,
+  (q31_t)0x7b9bdb18, (q31_t)0x7b9551ea,
+  (q31_t)0x7b8ec3f8, (q31_t)0x7b883143, (q31_t)0x7b8199ca, (q31_t)0x7b7afd8f, (q31_t)0x7b745c91, (q31_t)0x7b6db6d0,
+  (q31_t)0x7b670c4d, (q31_t)0x7b605d09,
+  (q31_t)0x7b59a902, (q31_t)0x7b52f03a, (q31_t)0x7b4c32b1, (q31_t)0x7b457068, (q31_t)0x7b3ea95d, (q31_t)0x7b37dd92,
+  (q31_t)0x7b310d07, (q31_t)0x7b2a37bc,
+  (q31_t)0x7b235db2, (q31_t)0x7b1c7ee8, (q31_t)0x7b159b5f, (q31_t)0x7b0eb318, (q31_t)0x7b07c612, (q31_t)0x7b00d44d,
+  (q31_t)0x7af9ddcb, (q31_t)0x7af2e28b,
+  (q31_t)0x7aebe28d, (q31_t)0x7ae4ddd2, (q31_t)0x7addd45b, (q31_t)0x7ad6c626, (q31_t)0x7acfb336, (q31_t)0x7ac89b89,
+  (q31_t)0x7ac17f20, (q31_t)0x7aba5dfc,
+  (q31_t)0x7ab3381d, (q31_t)0x7aac0d82, (q31_t)0x7aa4de2d, (q31_t)0x7a9daa1d, (q31_t)0x7a967153, (q31_t)0x7a8f33d0,
+  (q31_t)0x7a87f192, (q31_t)0x7a80aa9c,
+  (q31_t)0x7a795eec, (q31_t)0x7a720e84, (q31_t)0x7a6ab963, (q31_t)0x7a635f8a, (q31_t)0x7a5c00f9, (q31_t)0x7a549db0,
+  (q31_t)0x7a4d35b0, (q31_t)0x7a45c8f9,
+  (q31_t)0x7a3e578b, (q31_t)0x7a36e166, (q31_t)0x7a2f668c, (q31_t)0x7a27e6fb, (q31_t)0x7a2062b5, (q31_t)0x7a18d9b9,
+  (q31_t)0x7a114c09, (q31_t)0x7a09b9a4,
+  (q31_t)0x7a02228a, (q31_t)0x79fa86bc, (q31_t)0x79f2e63a, (q31_t)0x79eb4105, (q31_t)0x79e3971c, (q31_t)0x79dbe880,
+  (q31_t)0x79d43532, (q31_t)0x79cc7d31,
+  (q31_t)0x79c4c07e, (q31_t)0x79bcff19, (q31_t)0x79b53903, (q31_t)0x79ad6e3c, (q31_t)0x79a59ec3, (q31_t)0x799dca9a,
+  (q31_t)0x7995f1c1, (q31_t)0x798e1438,
+  (q31_t)0x798631ff, (q31_t)0x797e4b16, (q31_t)0x79765f7f, (q31_t)0x796e6f39, (q31_t)0x79667a44, (q31_t)0x795e80a1,
+  (q31_t)0x79568250, (q31_t)0x794e7f52,
+  (q31_t)0x794677a6, (q31_t)0x793e6b4e, (q31_t)0x79365a49, (q31_t)0x792e4497, (q31_t)0x79262a3a, (q31_t)0x791e0b31,
+  (q31_t)0x7915e77c, (q31_t)0x790dbf1d,
+  (q31_t)0x79059212, (q31_t)0x78fd605d, (q31_t)0x78f529fe, (q31_t)0x78eceef6, (q31_t)0x78e4af44, (q31_t)0x78dc6ae8,
+  (q31_t)0x78d421e4, (q31_t)0x78cbd437,
+  (q31_t)0x78c381e2, (q31_t)0x78bb2ae5, (q31_t)0x78b2cf41, (q31_t)0x78aa6ef5, (q31_t)0x78a20a03, (q31_t)0x7899a06a,
+  (q31_t)0x7891322a, (q31_t)0x7888bf45,
+  (q31_t)0x788047ba, (q31_t)0x7877cb89, (q31_t)0x786f4ab4, (q31_t)0x7866c53a, (q31_t)0x785e3b1c, (q31_t)0x7855ac5a,
+  (q31_t)0x784d18f4, (q31_t)0x784480ea,
+  (q31_t)0x783be43e, (q31_t)0x783342ef, (q31_t)0x782a9cfe, (q31_t)0x7821f26b, (q31_t)0x78194336, (q31_t)0x78108f60,
+  (q31_t)0x7807d6e9, (q31_t)0x77ff19d1,
+  (q31_t)0x77f65819, (q31_t)0x77ed91c0, (q31_t)0x77e4c6c9, (q31_t)0x77dbf732, (q31_t)0x77d322fc, (q31_t)0x77ca4a27,
+  (q31_t)0x77c16cb4, (q31_t)0x77b88aa3,
+  (q31_t)0x77afa3f5, (q31_t)0x77a6b8a9, (q31_t)0x779dc8c0, (q31_t)0x7794d43b, (q31_t)0x778bdb19, (q31_t)0x7782dd5c,
+  (q31_t)0x7779db03, (q31_t)0x7770d40f,
+  (q31_t)0x7767c880, (q31_t)0x775eb857, (q31_t)0x7755a394, (q31_t)0x774c8a36, (q31_t)0x77436c40, (q31_t)0x773a49b0,
+  (q31_t)0x77312287, (q31_t)0x7727f6c6,
+  (q31_t)0x771ec66e, (q31_t)0x7715917d, (q31_t)0x770c57f5, (q31_t)0x770319d6, (q31_t)0x76f9d721, (q31_t)0x76f08fd5,
+  (q31_t)0x76e743f4, (q31_t)0x76ddf37c,
+  (q31_t)0x76d49e70, (q31_t)0x76cb44cf, (q31_t)0x76c1e699, (q31_t)0x76b883d0, (q31_t)0x76af1c72, (q31_t)0x76a5b082,
+  (q31_t)0x769c3ffe, (q31_t)0x7692cae8,
+  (q31_t)0x7689513f, (q31_t)0x767fd304, (q31_t)0x76765038, (q31_t)0x766cc8db, (q31_t)0x76633ced, (q31_t)0x7659ac6f,
+  (q31_t)0x76501760, (q31_t)0x76467dc2,
+  (q31_t)0x763cdf94, (q31_t)0x76333cd8, (q31_t)0x7629958c, (q31_t)0x761fe9b3, (q31_t)0x7616394c, (q31_t)0x760c8457,
+  (q31_t)0x7602cad5, (q31_t)0x75f90cc7,
+  (q31_t)0x75ef4a2c, (q31_t)0x75e58305, (q31_t)0x75dbb753, (q31_t)0x75d1e715, (q31_t)0x75c8124d, (q31_t)0x75be38fa,
+  (q31_t)0x75b45b1d, (q31_t)0x75aa78b6,
+  (q31_t)0x75a091c6, (q31_t)0x7596a64d, (q31_t)0x758cb64c, (q31_t)0x7582c1c2, (q31_t)0x7578c8b0, (q31_t)0x756ecb18,
+  (q31_t)0x7564c8f8, (q31_t)0x755ac251,
+  (q31_t)0x7550b725, (q31_t)0x7546a772, (q31_t)0x753c933a, (q31_t)0x75327a7d, (q31_t)0x75285d3b, (q31_t)0x751e3b75,
+  (q31_t)0x7514152b, (q31_t)0x7509ea5d,
+  (q31_t)0x74ffbb0d, (q31_t)0x74f58739, (q31_t)0x74eb4ee3, (q31_t)0x74e1120c, (q31_t)0x74d6d0b2, (q31_t)0x74cc8ad8,
+  (q31_t)0x74c2407d, (q31_t)0x74b7f1a1,
+  (q31_t)0x74ad9e46, (q31_t)0x74a3466b, (q31_t)0x7498ea11, (q31_t)0x748e8938, (q31_t)0x748423e0, (q31_t)0x7479ba0b,
+  (q31_t)0x746f4bb8, (q31_t)0x7464d8e8,
+  (q31_t)0x745a619b, (q31_t)0x744fe5d2, (q31_t)0x7445658d, (q31_t)0x743ae0cc, (q31_t)0x74305790, (q31_t)0x7425c9da,
+  (q31_t)0x741b37a9, (q31_t)0x7410a0fe,
+  (q31_t)0x740605d9, (q31_t)0x73fb663c, (q31_t)0x73f0c226, (q31_t)0x73e61997, (q31_t)0x73db6c91, (q31_t)0x73d0bb13,
+  (q31_t)0x73c6051f, (q31_t)0x73bb4ab3,
+  (q31_t)0x73b08bd1, (q31_t)0x73a5c87a, (q31_t)0x739b00ad, (q31_t)0x7390346b, (q31_t)0x738563b5, (q31_t)0x737a8e8a,
+  (q31_t)0x736fb4ec, (q31_t)0x7364d6da,
+  (q31_t)0x7359f456, (q31_t)0x734f0d5f, (q31_t)0x734421f6, (q31_t)0x7339321b, (q31_t)0x732e3dcf, (q31_t)0x73234512,
+  (q31_t)0x731847e5, (q31_t)0x730d4648,
+  (q31_t)0x7302403c, (q31_t)0x72f735c0, (q31_t)0x72ec26d6, (q31_t)0x72e1137d, (q31_t)0x72d5fbb7, (q31_t)0x72cadf83,
+  (q31_t)0x72bfbee3, (q31_t)0x72b499d6,
+  (q31_t)0x72a9705c, (q31_t)0x729e4277, (q31_t)0x72931027, (q31_t)0x7287d96c, (q31_t)0x727c9e47, (q31_t)0x72715eb8,
+  (q31_t)0x72661abf, (q31_t)0x725ad25d,
+  (q31_t)0x724f8593, (q31_t)0x72443460, (q31_t)0x7238dec5, (q31_t)0x722d84c4, (q31_t)0x7222265b, (q31_t)0x7216c38c,
+  (q31_t)0x720b5c57, (q31_t)0x71fff0bc,
+  (q31_t)0x71f480bc, (q31_t)0x71e90c57, (q31_t)0x71dd938f, (q31_t)0x71d21662, (q31_t)0x71c694d2, (q31_t)0x71bb0edf,
+  (q31_t)0x71af848a, (q31_t)0x71a3f5d2,
+  (q31_t)0x719862b9, (q31_t)0x718ccb3f, (q31_t)0x71812f65, (q31_t)0x71758f29, (q31_t)0x7169ea8f, (q31_t)0x715e4194,
+  (q31_t)0x7152943b, (q31_t)0x7146e284,
+  (q31_t)0x713b2c6e, (q31_t)0x712f71fb, (q31_t)0x7123b32b, (q31_t)0x7117effe, (q31_t)0x710c2875, (q31_t)0x71005c90,
+  (q31_t)0x70f48c50, (q31_t)0x70e8b7b5,
+  (q31_t)0x70dcdec0, (q31_t)0x70d10171, (q31_t)0x70c51fc8, (q31_t)0x70b939c7, (q31_t)0x70ad4f6d, (q31_t)0x70a160ba,
+  (q31_t)0x70956db1, (q31_t)0x70897650,
+  (q31_t)0x707d7a98, (q31_t)0x70717a8a, (q31_t)0x70657626, (q31_t)0x70596d6d, (q31_t)0x704d6060, (q31_t)0x70414efd,
+  (q31_t)0x70353947, (q31_t)0x70291f3e,
+  (q31_t)0x701d00e1, (q31_t)0x7010de32, (q31_t)0x7004b731, (q31_t)0x6ff88bde, (q31_t)0x6fec5c3b, (q31_t)0x6fe02846,
+  (q31_t)0x6fd3f001, (q31_t)0x6fc7b36d,
+  (q31_t)0x6fbb728a, (q31_t)0x6faf2d57, (q31_t)0x6fa2e3d7, (q31_t)0x6f969608, (q31_t)0x6f8a43ed, (q31_t)0x6f7ded84,
+  (q31_t)0x6f7192cf, (q31_t)0x6f6533ce,
+  (q31_t)0x6f58d082, (q31_t)0x6f4c68eb, (q31_t)0x6f3ffd09, (q31_t)0x6f338cde, (q31_t)0x6f271868, (q31_t)0x6f1a9faa,
+  (q31_t)0x6f0e22a3, (q31_t)0x6f01a155,
+  (q31_t)0x6ef51bbe, (q31_t)0x6ee891e1, (q31_t)0x6edc03bc, (q31_t)0x6ecf7152, (q31_t)0x6ec2daa2, (q31_t)0x6eb63fad,
+  (q31_t)0x6ea9a073, (q31_t)0x6e9cfcf5,
+  (q31_t)0x6e905534, (q31_t)0x6e83a92f, (q31_t)0x6e76f8e7, (q31_t)0x6e6a445d, (q31_t)0x6e5d8b91, (q31_t)0x6e50ce84,
+  (q31_t)0x6e440d37, (q31_t)0x6e3747a9,
+  (q31_t)0x6e2a7ddb, (q31_t)0x6e1dafce, (q31_t)0x6e10dd82, (q31_t)0x6e0406f8, (q31_t)0x6df72c30, (q31_t)0x6dea4d2b,
+  (q31_t)0x6ddd69e9, (q31_t)0x6dd0826a,
+  (q31_t)0x6dc396b0, (q31_t)0x6db6a6ba, (q31_t)0x6da9b28a, (q31_t)0x6d9cba1f, (q31_t)0x6d8fbd7a, (q31_t)0x6d82bc9d,
+  (q31_t)0x6d75b786, (q31_t)0x6d68ae37,
+  (q31_t)0x6d5ba0b0, (q31_t)0x6d4e8ef2, (q31_t)0x6d4178fd, (q31_t)0x6d345ed1, (q31_t)0x6d274070, (q31_t)0x6d1a1dda,
+  (q31_t)0x6d0cf70f, (q31_t)0x6cffcc0f,
+  (q31_t)0x6cf29cdc, (q31_t)0x6ce56975, (q31_t)0x6cd831dc, (q31_t)0x6ccaf610, (q31_t)0x6cbdb613, (q31_t)0x6cb071e4,
+  (q31_t)0x6ca32985, (q31_t)0x6c95dcf6,
+  (q31_t)0x6c888c36, (q31_t)0x6c7b3748, (q31_t)0x6c6dde2b, (q31_t)0x6c6080e0, (q31_t)0x6c531f67, (q31_t)0x6c45b9c1,
+  (q31_t)0x6c384fef, (q31_t)0x6c2ae1f0,
+  (q31_t)0x6c1d6fc6, (q31_t)0x6c0ff971, (q31_t)0x6c027ef1, (q31_t)0x6bf50047, (q31_t)0x6be77d74, (q31_t)0x6bd9f677,
+  (q31_t)0x6bcc6b53, (q31_t)0x6bbedc06,
+  (q31_t)0x6bb14892, (q31_t)0x6ba3b0f7, (q31_t)0x6b961536, (q31_t)0x6b88754f, (q31_t)0x6b7ad142, (q31_t)0x6b6d2911,
+  (q31_t)0x6b5f7cbc, (q31_t)0x6b51cc42,
+  (q31_t)0x6b4417a6, (q31_t)0x6b365ee7, (q31_t)0x6b28a206, (q31_t)0x6b1ae103, (q31_t)0x6b0d1bdf, (q31_t)0x6aff529a,
+  (q31_t)0x6af18536, (q31_t)0x6ae3b3b2,
+  (q31_t)0x6ad5de0f, (q31_t)0x6ac8044e, (q31_t)0x6aba266e, (q31_t)0x6aac4472, (q31_t)0x6a9e5e58, (q31_t)0x6a907423,
+  (q31_t)0x6a8285d1, (q31_t)0x6a749365,
+  (q31_t)0x6a669cdd, (q31_t)0x6a58a23c, (q31_t)0x6a4aa381, (q31_t)0x6a3ca0ad, (q31_t)0x6a2e99c0, (q31_t)0x6a208ebb,
+  (q31_t)0x6a127f9f, (q31_t)0x6a046c6c,
+  (q31_t)0x69f65523, (q31_t)0x69e839c4, (q31_t)0x69da1a50, (q31_t)0x69cbf6c7, (q31_t)0x69bdcf29, (q31_t)0x69afa378,
+  (q31_t)0x69a173b5, (q31_t)0x69933fde,
+  (q31_t)0x698507f6, (q31_t)0x6976cbfc, (q31_t)0x69688bf1, (q31_t)0x695a47d6, (q31_t)0x694bffab, (q31_t)0x693db371,
+  (q31_t)0x692f6328, (q31_t)0x69210ed1,
+  (q31_t)0x6912b66c, (q31_t)0x690459fb, (q31_t)0x68f5f97d, (q31_t)0x68e794f3, (q31_t)0x68d92c5d, (q31_t)0x68cabfbd,
+  (q31_t)0x68bc4f13, (q31_t)0x68adda5f,
+  (q31_t)0x689f61a1, (q31_t)0x6890e4dc, (q31_t)0x6882640e, (q31_t)0x6873df38, (q31_t)0x6865565c, (q31_t)0x6856c979,
+  (q31_t)0x68483891, (q31_t)0x6839a3a4,
+  (q31_t)0x682b0ab1, (q31_t)0x681c6dbb, (q31_t)0x680dccc1, (q31_t)0x67ff27c4, (q31_t)0x67f07ec5, (q31_t)0x67e1d1c4,
+  (q31_t)0x67d320c1, (q31_t)0x67c46bbe,
+  (q31_t)0x67b5b2bb, (q31_t)0x67a6f5b8, (q31_t)0x679834b6, (q31_t)0x67896fb6, (q31_t)0x677aa6b8, (q31_t)0x676bd9bd,
+  (q31_t)0x675d08c4, (q31_t)0x674e33d0,
+  (q31_t)0x673f5ae0, (q31_t)0x67307df5, (q31_t)0x67219d10, (q31_t)0x6712b831, (q31_t)0x6703cf58, (q31_t)0x66f4e287,
+  (q31_t)0x66e5f1be, (q31_t)0x66d6fcfd,
+  (q31_t)0x66c80445, (q31_t)0x66b90797, (q31_t)0x66aa06f3, (q31_t)0x669b0259, (q31_t)0x668bf9cb, (q31_t)0x667ced49,
+  (q31_t)0x666ddcd3, (q31_t)0x665ec86b,
+  (q31_t)0x664fb010, (q31_t)0x664093c3, (q31_t)0x66317385, (q31_t)0x66224f56, (q31_t)0x66132738, (q31_t)0x6603fb2a,
+  (q31_t)0x65f4cb2d, (q31_t)0x65e59742,
+  (q31_t)0x65d65f69, (q31_t)0x65c723a3, (q31_t)0x65b7e3f1, (q31_t)0x65a8a052, (q31_t)0x659958c9, (q31_t)0x658a0d54,
+  (q31_t)0x657abdf6, (q31_t)0x656b6aae,
+  (q31_t)0x655c137d, (q31_t)0x654cb863, (q31_t)0x653d5962, (q31_t)0x652df679, (q31_t)0x651e8faa, (q31_t)0x650f24f5,
+  (q31_t)0x64ffb65b, (q31_t)0x64f043dc,
+  (q31_t)0x64e0cd78, (q31_t)0x64d15331, (q31_t)0x64c1d507, (q31_t)0x64b252fa, (q31_t)0x64a2cd0c, (q31_t)0x6493433c,
+  (q31_t)0x6483b58c, (q31_t)0x647423fb,
+  (q31_t)0x64648e8c, (q31_t)0x6454f53d, (q31_t)0x64455810, (q31_t)0x6435b706, (q31_t)0x6426121e, (q31_t)0x6416695a,
+  (q31_t)0x6406bcba, (q31_t)0x63f70c3f,
+  (q31_t)0x63e757ea, (q31_t)0x63d79fba, (q31_t)0x63c7e3b1, (q31_t)0x63b823cf, (q31_t)0x63a86015, (q31_t)0x63989884,
+  (q31_t)0x6388cd1b, (q31_t)0x6378fddc,
+  (q31_t)0x63692ac7, (q31_t)0x635953dd, (q31_t)0x6349791f, (q31_t)0x63399a8d, (q31_t)0x6329b827, (q31_t)0x6319d1ef,
+  (q31_t)0x6309e7e4, (q31_t)0x62f9fa09,
+  (q31_t)0x62ea085c, (q31_t)0x62da12df, (q31_t)0x62ca1992, (q31_t)0x62ba1c77, (q31_t)0x62aa1b8d, (q31_t)0x629a16d5,
+  (q31_t)0x628a0e50, (q31_t)0x627a01fe,
+  (q31_t)0x6269f1e1, (q31_t)0x6259ddf8, (q31_t)0x6249c645, (q31_t)0x6239aac7, (q31_t)0x62298b81, (q31_t)0x62196871,
+  (q31_t)0x62094199, (q31_t)0x61f916f9,
+  (q31_t)0x61e8e893, (q31_t)0x61d8b666, (q31_t)0x61c88074, (q31_t)0x61b846bc, (q31_t)0x61a80940, (q31_t)0x6197c800,
+  (q31_t)0x618782fd, (q31_t)0x61773a37,
+  (q31_t)0x6166edb0, (q31_t)0x61569d67, (q31_t)0x6146495d, (q31_t)0x6135f193, (q31_t)0x6125960a, (q31_t)0x611536c2,
+  (q31_t)0x6104d3bc, (q31_t)0x60f46cf9,
+  (q31_t)0x60e40278, (q31_t)0x60d3943b, (q31_t)0x60c32243, (q31_t)0x60b2ac8f, (q31_t)0x60a23322, (q31_t)0x6091b5fa,
+  (q31_t)0x60813519, (q31_t)0x6070b080,
+  (q31_t)0x6060282f, (q31_t)0x604f9c27, (q31_t)0x603f0c69, (q31_t)0x602e78f4, (q31_t)0x601de1ca, (q31_t)0x600d46ec,
+  (q31_t)0x5ffca859, (q31_t)0x5fec0613,
+  (q31_t)0x5fdb601b, (q31_t)0x5fcab670, (q31_t)0x5fba0914, (q31_t)0x5fa95807, (q31_t)0x5f98a34a, (q31_t)0x5f87eade,
+  (q31_t)0x5f772ec2, (q31_t)0x5f666ef9,
+  (q31_t)0x5f55ab82, (q31_t)0x5f44e45e, (q31_t)0x5f34198e, (q31_t)0x5f234b12, (q31_t)0x5f1278eb, (q31_t)0x5f01a31a,
+  (q31_t)0x5ef0c99f, (q31_t)0x5edfec7b,
+  (q31_t)0x5ecf0baf, (q31_t)0x5ebe273b, (q31_t)0x5ead3f1f, (q31_t)0x5e9c535e, (q31_t)0x5e8b63f7, (q31_t)0x5e7a70ea,
+  (q31_t)0x5e697a39, (q31_t)0x5e587fe5,
+  (q31_t)0x5e4781ed, (q31_t)0x5e368053, (q31_t)0x5e257b17, (q31_t)0x5e147239, (q31_t)0x5e0365bb, (q31_t)0x5df2559e,
+  (q31_t)0x5de141e1, (q31_t)0x5dd02a85,
+  (q31_t)0x5dbf0f8c, (q31_t)0x5dadf0f5, (q31_t)0x5d9ccec2, (q31_t)0x5d8ba8f3, (q31_t)0x5d7a7f88, (q31_t)0x5d695283,
+  (q31_t)0x5d5821e4, (q31_t)0x5d46edac,
+  (q31_t)0x5d35b5db, (q31_t)0x5d247a72, (q31_t)0x5d133b72, (q31_t)0x5d01f8dc, (q31_t)0x5cf0b2af, (q31_t)0x5cdf68ed,
+  (q31_t)0x5cce1b97, (q31_t)0x5cbccaac,
+  (q31_t)0x5cab762f, (q31_t)0x5c9a1e1e, (q31_t)0x5c88c27c, (q31_t)0x5c776348, (q31_t)0x5c660084, (q31_t)0x5c549a30,
+  (q31_t)0x5c43304d, (q31_t)0x5c31c2db,
+  (q31_t)0x5c2051db, (q31_t)0x5c0edd4e, (q31_t)0x5bfd6534, (q31_t)0x5bebe98e, (q31_t)0x5bda6a5d, (q31_t)0x5bc8e7a2,
+  (q31_t)0x5bb7615d, (q31_t)0x5ba5d78e,
+  (q31_t)0x5b944a37, (q31_t)0x5b82b958, (q31_t)0x5b7124f2, (q31_t)0x5b5f8d06, (q31_t)0x5b4df193, (q31_t)0x5b3c529c,
+  (q31_t)0x5b2ab020, (q31_t)0x5b190a20,
+  (q31_t)0x5b07609d, (q31_t)0x5af5b398, (q31_t)0x5ae40311, (q31_t)0x5ad24f09, (q31_t)0x5ac09781, (q31_t)0x5aaedc78,
+  (q31_t)0x5a9d1df1, (q31_t)0x5a8b5bec,
+  (q31_t)0x5a799669, (q31_t)0x5a67cd69, (q31_t)0x5a5600ec, (q31_t)0x5a4430f5, (q31_t)0x5a325d82, (q31_t)0x5a208695,
+  (q31_t)0x5a0eac2e, (q31_t)0x59fcce4f,
+  (q31_t)0x59eaecf8, (q31_t)0x59d90829, (q31_t)0x59c71fe3, (q31_t)0x59b53427, (q31_t)0x59a344f6, (q31_t)0x59915250,
+  (q31_t)0x597f5c36, (q31_t)0x596d62a9,
+  (q31_t)0x595b65aa, (q31_t)0x59496538, (q31_t)0x59376155, (q31_t)0x59255a02, (q31_t)0x59134f3e, (q31_t)0x5901410c,
+  (q31_t)0x58ef2f6b, (q31_t)0x58dd1a5d,
+  (q31_t)0x58cb01e1, (q31_t)0x58b8e5f9, (q31_t)0x58a6c6a5, (q31_t)0x5894a3e7, (q31_t)0x58827dbe, (q31_t)0x5870542c,
+  (q31_t)0x585e2730, (q31_t)0x584bf6cd,
+  (q31_t)0x5839c302, (q31_t)0x58278bd1, (q31_t)0x58155139, (q31_t)0x5803133c, (q31_t)0x57f0d1da, (q31_t)0x57de8d15,
+  (q31_t)0x57cc44ec, (q31_t)0x57b9f960,
+  (q31_t)0x57a7aa73, (q31_t)0x57955825, (q31_t)0x57830276, (q31_t)0x5770a968, (q31_t)0x575e4cfa, (q31_t)0x574bed2f,
+  (q31_t)0x57398a05, (q31_t)0x5727237f,
+  (q31_t)0x5714b99d, (q31_t)0x57024c5f, (q31_t)0x56efdbc7, (q31_t)0x56dd67d4, (q31_t)0x56caf088, (q31_t)0x56b875e4,
+  (q31_t)0x56a5f7e7, (q31_t)0x56937694,
+  (q31_t)0x5680f1ea, (q31_t)0x566e69ea, (q31_t)0x565bde95, (q31_t)0x56494fec, (q31_t)0x5636bdef, (q31_t)0x5624289f,
+  (q31_t)0x56118ffe, (q31_t)0x55fef40a,
+  (q31_t)0x55ec54c6, (q31_t)0x55d9b232, (q31_t)0x55c70c4f, (q31_t)0x55b4631d, (q31_t)0x55a1b69d, (q31_t)0x558f06d0,
+  (q31_t)0x557c53b6, (q31_t)0x55699d51,
+  (q31_t)0x5556e3a1, (q31_t)0x554426a7, (q31_t)0x55316663, (q31_t)0x551ea2d6, (q31_t)0x550bdc01, (q31_t)0x54f911e5,
+  (q31_t)0x54e64482, (q31_t)0x54d373d9,
+  (q31_t)0x54c09feb, (q31_t)0x54adc8b8, (q31_t)0x549aee42, (q31_t)0x54881089, (q31_t)0x54752f8d, (q31_t)0x54624b50,
+  (q31_t)0x544f63d2, (q31_t)0x543c7914,
+  (q31_t)0x54298b17, (q31_t)0x541699db, (q31_t)0x5403a561, (q31_t)0x53f0adaa, (q31_t)0x53ddb2b6, (q31_t)0x53cab486,
+  (q31_t)0x53b7b31c, (q31_t)0x53a4ae77,
+  (q31_t)0x5391a699, (q31_t)0x537e9b82, (q31_t)0x536b8d33, (q31_t)0x53587bad, (q31_t)0x534566f0, (q31_t)0x53324efd,
+  (q31_t)0x531f33d5, (q31_t)0x530c1579,
+  (q31_t)0x52f8f3e9, (q31_t)0x52e5cf27, (q31_t)0x52d2a732, (q31_t)0x52bf7c0b, (q31_t)0x52ac4db4, (q31_t)0x52991c2d,
+  (q31_t)0x5285e777, (q31_t)0x5272af92,
+  (q31_t)0x525f7480, (q31_t)0x524c3640, (q31_t)0x5238f4d4, (q31_t)0x5225b03d, (q31_t)0x5212687b, (q31_t)0x51ff1d8f,
+  (q31_t)0x51ebcf7a, (q31_t)0x51d87e3c,
+  (q31_t)0x51c529d7, (q31_t)0x51b1d24a, (q31_t)0x519e7797, (q31_t)0x518b19bf, (q31_t)0x5177b8c2, (q31_t)0x516454a0,
+  (q31_t)0x5150ed5c, (q31_t)0x513d82f4,
+  (q31_t)0x512a156b, (q31_t)0x5116a4c1, (q31_t)0x510330f7, (q31_t)0x50efba0d, (q31_t)0x50dc4005, (q31_t)0x50c8c2de,
+  (q31_t)0x50b5429a, (q31_t)0x50a1bf39,
+  (q31_t)0x508e38bd, (q31_t)0x507aaf25, (q31_t)0x50672273, (q31_t)0x505392a8, (q31_t)0x503fffc4, (q31_t)0x502c69c8,
+  (q31_t)0x5018d0b4, (q31_t)0x5005348a,
+  (q31_t)0x4ff1954b, (q31_t)0x4fddf2f6, (q31_t)0x4fca4d8d, (q31_t)0x4fb6a510, (q31_t)0x4fa2f981, (q31_t)0x4f8f4ae0,
+  (q31_t)0x4f7b992d, (q31_t)0x4f67e46a,
+  (q31_t)0x4f542c98, (q31_t)0x4f4071b6, (q31_t)0x4f2cb3c7, (q31_t)0x4f18f2c9, (q31_t)0x4f052ec0, (q31_t)0x4ef167aa,
+  (q31_t)0x4edd9d89, (q31_t)0x4ec9d05e,
+  (q31_t)0x4eb60029, (q31_t)0x4ea22ceb, (q31_t)0x4e8e56a5, (q31_t)0x4e7a7d58, (q31_t)0x4e66a105, (q31_t)0x4e52c1ab,
+  (q31_t)0x4e3edf4d, (q31_t)0x4e2af9ea,
+  (q31_t)0x4e171184, (q31_t)0x4e03261b, (q31_t)0x4def37b0, (q31_t)0x4ddb4644, (q31_t)0x4dc751d8, (q31_t)0x4db35a6c,
+  (q31_t)0x4d9f6001, (q31_t)0x4d8b6298,
+  (q31_t)0x4d776231, (q31_t)0x4d635ece, (q31_t)0x4d4f5870, (q31_t)0x4d3b4f16, (q31_t)0x4d2742c2, (q31_t)0x4d133374,
+  (q31_t)0x4cff212e, (q31_t)0x4ceb0bf0,
+  (q31_t)0x4cd6f3bb, (q31_t)0x4cc2d88f, (q31_t)0x4caeba6e, (q31_t)0x4c9a9958, (q31_t)0x4c86754e, (q31_t)0x4c724e50,
+  (q31_t)0x4c5e2460, (q31_t)0x4c49f77f,
+  (q31_t)0x4c35c7ac, (q31_t)0x4c2194e9, (q31_t)0x4c0d5f37, (q31_t)0x4bf92697, (q31_t)0x4be4eb08, (q31_t)0x4bd0ac8d,
+  (q31_t)0x4bbc6b25, (q31_t)0x4ba826d1,
+  (q31_t)0x4b93df93, (q31_t)0x4b7f956b, (q31_t)0x4b6b485a, (q31_t)0x4b56f861, (q31_t)0x4b42a580, (q31_t)0x4b2e4fb8,
+  (q31_t)0x4b19f70a, (q31_t)0x4b059b77,
+  (q31_t)0x4af13d00, (q31_t)0x4adcdba5, (q31_t)0x4ac87767, (q31_t)0x4ab41046, (q31_t)0x4a9fa645, (q31_t)0x4a8b3963,
+  (q31_t)0x4a76c9a2, (q31_t)0x4a625701,
+  (q31_t)0x4a4de182, (q31_t)0x4a396926, (q31_t)0x4a24edee, (q31_t)0x4a106fda, (q31_t)0x49fbeeea, (q31_t)0x49e76b21,
+  (q31_t)0x49d2e47e, (q31_t)0x49be5b02,
+  (q31_t)0x49a9ceaf, (q31_t)0x49953f84, (q31_t)0x4980ad84, (q31_t)0x496c18ae, (q31_t)0x49578103, (q31_t)0x4942e684,
+  (q31_t)0x492e4933, (q31_t)0x4919a90f,
+  (q31_t)0x4905061a, (q31_t)0x48f06054, (q31_t)0x48dbb7be, (q31_t)0x48c70c59, (q31_t)0x48b25e25, (q31_t)0x489dad25,
+  (q31_t)0x4888f957, (q31_t)0x487442be,
+  (q31_t)0x485f8959, (q31_t)0x484acd2a, (q31_t)0x48360e32, (q31_t)0x48214c71, (q31_t)0x480c87e8, (q31_t)0x47f7c099,
+  (q31_t)0x47e2f682, (q31_t)0x47ce29a7,
+  (q31_t)0x47b95a06, (q31_t)0x47a487a2, (q31_t)0x478fb27b, (q31_t)0x477ada91, (q31_t)0x4765ffe6, (q31_t)0x4751227a,
+  (q31_t)0x473c424e, (q31_t)0x47275f63,
+  (q31_t)0x471279ba, (q31_t)0x46fd9154, (q31_t)0x46e8a631, (q31_t)0x46d3b852, (q31_t)0x46bec7b8, (q31_t)0x46a9d464,
+  (q31_t)0x4694de56, (q31_t)0x467fe590,
+  (q31_t)0x466aea12, (q31_t)0x4655ebdd, (q31_t)0x4640eaf2, (q31_t)0x462be751, (q31_t)0x4616e0fc, (q31_t)0x4601d7f3,
+  (q31_t)0x45eccc37, (q31_t)0x45d7bdc9,
+  (q31_t)0x45c2acaa, (q31_t)0x45ad98da, (q31_t)0x4598825a, (q31_t)0x4583692c, (q31_t)0x456e4d4f, (q31_t)0x45592ec6,
+  (q31_t)0x45440d90, (q31_t)0x452ee9ae,
+  (q31_t)0x4519c321, (q31_t)0x450499eb, (q31_t)0x44ef6e0b, (q31_t)0x44da3f83, (q31_t)0x44c50e53, (q31_t)0x44afda7d,
+  (q31_t)0x449aa400, (q31_t)0x44856adf,
+  (q31_t)0x44702f19, (q31_t)0x445af0b0, (q31_t)0x4445afa4, (q31_t)0x44306bf6, (q31_t)0x441b25a8, (q31_t)0x4405dcb9,
+  (q31_t)0x43f0912b, (q31_t)0x43db42fe,
+  (q31_t)0x43c5f234, (q31_t)0x43b09ecc, (q31_t)0x439b48c9, (q31_t)0x4385f02a, (q31_t)0x437094f1, (q31_t)0x435b371f,
+  (q31_t)0x4345d6b3, (q31_t)0x433073b0,
+  (q31_t)0x431b0e15, (q31_t)0x4305a5e5, (q31_t)0x42f03b1e, (q31_t)0x42dacdc3, (q31_t)0x42c55dd4, (q31_t)0x42afeb53,
+  (q31_t)0x429a763f, (q31_t)0x4284fe99,
+  (q31_t)0x426f8463, (q31_t)0x425a079e, (q31_t)0x42448849, (q31_t)0x422f0667, (q31_t)0x421981f7, (q31_t)0x4203fafb,
+  (q31_t)0x41ee7174, (q31_t)0x41d8e561,
+  (q31_t)0x41c356c5, (q31_t)0x41adc5a0, (q31_t)0x419831f3, (q31_t)0x41829bbe, (q31_t)0x416d0302, (q31_t)0x415767c1,
+  (q31_t)0x4141c9fb, (q31_t)0x412c29b1,
+  (q31_t)0x411686e4, (q31_t)0x4100e194, (q31_t)0x40eb39c3, (q31_t)0x40d58f71, (q31_t)0x40bfe29f, (q31_t)0x40aa334e,
+  (q31_t)0x4094817f, (q31_t)0x407ecd32,
+  (q31_t)0x40691669, (q31_t)0x40535d24, (q31_t)0x403da165, (q31_t)0x4027e32b, (q31_t)0x40122278, (q31_t)0x3ffc5f4d,
+  (q31_t)0x3fe699aa, (q31_t)0x3fd0d191,
+  (q31_t)0x3fbb0702, (q31_t)0x3fa539fd, (q31_t)0x3f8f6a85, (q31_t)0x3f799899, (q31_t)0x3f63c43b, (q31_t)0x3f4ded6b,
+  (q31_t)0x3f38142a, (q31_t)0x3f22387a,
+  (q31_t)0x3f0c5a5a, (q31_t)0x3ef679cc, (q31_t)0x3ee096d1, (q31_t)0x3ecab169, (q31_t)0x3eb4c995, (q31_t)0x3e9edf57,
+  (q31_t)0x3e88f2ae, (q31_t)0x3e73039d,
+  (q31_t)0x3e5d1222, (q31_t)0x3e471e41, (q31_t)0x3e3127f9, (q31_t)0x3e1b2f4a, (q31_t)0x3e053437, (q31_t)0x3def36c0,
+  (q31_t)0x3dd936e6, (q31_t)0x3dc334a9,
+  (q31_t)0x3dad300b, (q31_t)0x3d97290b, (q31_t)0x3d811fac, (q31_t)0x3d6b13ee, (q31_t)0x3d5505d2, (q31_t)0x3d3ef559,
+  (q31_t)0x3d28e282, (q31_t)0x3d12cd51,
+  (q31_t)0x3cfcb5c4, (q31_t)0x3ce69bde, (q31_t)0x3cd07f9f, (q31_t)0x3cba6107, (q31_t)0x3ca44018, (q31_t)0x3c8e1cd3,
+  (q31_t)0x3c77f737, (q31_t)0x3c61cf48,
+  (q31_t)0x3c4ba504, (q31_t)0x3c35786d, (q31_t)0x3c1f4983, (q31_t)0x3c091849, (q31_t)0x3bf2e4be, (q31_t)0x3bdcaee3,
+  (q31_t)0x3bc676b9, (q31_t)0x3bb03c42,
+  (q31_t)0x3b99ff7d, (q31_t)0x3b83c06c, (q31_t)0x3b6d7f10, (q31_t)0x3b573b69, (q31_t)0x3b40f579, (q31_t)0x3b2aad3f,
+  (q31_t)0x3b1462be, (q31_t)0x3afe15f6,
+  (q31_t)0x3ae7c6e7, (q31_t)0x3ad17593, (q31_t)0x3abb21fb, (q31_t)0x3aa4cc1e, (q31_t)0x3a8e7400, (q31_t)0x3a78199f,
+  (q31_t)0x3a61bcfd, (q31_t)0x3a4b5e1b,
+  (q31_t)0x3a34fcf9, (q31_t)0x3a1e9999, (q31_t)0x3a0833fc, (q31_t)0x39f1cc21, (q31_t)0x39db620b, (q31_t)0x39c4f5ba,
+  (q31_t)0x39ae872f, (q31_t)0x3998166a,
+  (q31_t)0x3981a36d, (q31_t)0x396b2e38, (q31_t)0x3954b6cd, (q31_t)0x393e3d2c, (q31_t)0x3927c155, (q31_t)0x3911434b,
+  (q31_t)0x38fac30e, (q31_t)0x38e4409e,
+  (q31_t)0x38cdbbfc, (q31_t)0x38b7352a, (q31_t)0x38a0ac29, (q31_t)0x388a20f8, (q31_t)0x38739399, (q31_t)0x385d040d,
+  (q31_t)0x38467255, (q31_t)0x382fde72,
+  (q31_t)0x38194864, (q31_t)0x3802b02c, (q31_t)0x37ec15cb, (q31_t)0x37d57943, (q31_t)0x37beda93, (q31_t)0x37a839be,
+  (q31_t)0x379196c3, (q31_t)0x377af1a3,
+  (q31_t)0x37644a60, (q31_t)0x374da0fa, (q31_t)0x3736f573, (q31_t)0x372047ca, (q31_t)0x37099802, (q31_t)0x36f2e61a,
+  (q31_t)0x36dc3214, (q31_t)0x36c57bf0,
+  (q31_t)0x36aec3b0, (q31_t)0x36980954, (q31_t)0x36814cde, (q31_t)0x366a8e4d, (q31_t)0x3653cda3, (q31_t)0x363d0ae2,
+  (q31_t)0x36264609, (q31_t)0x360f7f19,
+  (q31_t)0x35f8b614, (q31_t)0x35e1eafa, (q31_t)0x35cb1dcc, (q31_t)0x35b44e8c, (q31_t)0x359d7d39, (q31_t)0x3586a9d5,
+  (q31_t)0x356fd461, (q31_t)0x3558fcde,
+  (q31_t)0x3542234c, (q31_t)0x352b47ad, (q31_t)0x35146a00, (q31_t)0x34fd8a48, (q31_t)0x34e6a885, (q31_t)0x34cfc4b7,
+  (q31_t)0x34b8dee1, (q31_t)0x34a1f702,
+  (q31_t)0x348b0d1c, (q31_t)0x3474212f, (q31_t)0x345d333c, (q31_t)0x34464345, (q31_t)0x342f5149, (q31_t)0x34185d4b,
+  (q31_t)0x3401674a, (q31_t)0x33ea6f48,
+  (q31_t)0x33d37546, (q31_t)0x33bc7944, (q31_t)0x33a57b44, (q31_t)0x338e7b46, (q31_t)0x3377794b, (q31_t)0x33607554,
+  (q31_t)0x33496f62, (q31_t)0x33326776,
+  (q31_t)0x331b5d91, (q31_t)0x330451b3, (q31_t)0x32ed43de, (q31_t)0x32d63412, (q31_t)0x32bf2250, (q31_t)0x32a80e99,
+  (q31_t)0x3290f8ef, (q31_t)0x3279e151,
+  (q31_t)0x3262c7c1, (q31_t)0x324bac40, (q31_t)0x32348ecf, (q31_t)0x321d6f6e, (q31_t)0x32064e1e, (q31_t)0x31ef2ae1,
+  (q31_t)0x31d805b7, (q31_t)0x31c0dea1,
+  (q31_t)0x31a9b5a0, (q31_t)0x31928ab4, (q31_t)0x317b5de0, (q31_t)0x31642f23, (q31_t)0x314cfe7f, (q31_t)0x3135cbf4,
+  (q31_t)0x311e9783, (q31_t)0x3107612e,
+  (q31_t)0x30f028f4, (q31_t)0x30d8eed8, (q31_t)0x30c1b2da, (q31_t)0x30aa74fa, (q31_t)0x3093353a, (q31_t)0x307bf39b,
+  (q31_t)0x3064b01d, (q31_t)0x304d6ac1,
+  (q31_t)0x30362389, (q31_t)0x301eda75, (q31_t)0x30078f86, (q31_t)0x2ff042bd, (q31_t)0x2fd8f41b, (q31_t)0x2fc1a3a0,
+  (q31_t)0x2faa514f, (q31_t)0x2f92fd26,
+  (q31_t)0x2f7ba729, (q31_t)0x2f644f56, (q31_t)0x2f4cf5b0, (q31_t)0x2f359a37, (q31_t)0x2f1e3ced, (q31_t)0x2f06ddd1,
+  (q31_t)0x2eef7ce5, (q31_t)0x2ed81a29,
+  (q31_t)0x2ec0b5a0, (q31_t)0x2ea94f49, (q31_t)0x2e91e725, (q31_t)0x2e7a7d36, (q31_t)0x2e63117c, (q31_t)0x2e4ba3f8,
+  (q31_t)0x2e3434ac, (q31_t)0x2e1cc397,
+  (q31_t)0x2e0550bb, (q31_t)0x2deddc19, (q31_t)0x2dd665b2, (q31_t)0x2dbeed86, (q31_t)0x2da77397, (q31_t)0x2d8ff7e5,
+  (q31_t)0x2d787a72, (q31_t)0x2d60fb3e,
+  (q31_t)0x2d497a4a, (q31_t)0x2d31f797, (q31_t)0x2d1a7325, (q31_t)0x2d02ecf7, (q31_t)0x2ceb650d, (q31_t)0x2cd3db67,
+  (q31_t)0x2cbc5006, (q31_t)0x2ca4c2ed,
+  (q31_t)0x2c8d341a, (q31_t)0x2c75a390, (q31_t)0x2c5e114f, (q31_t)0x2c467d58, (q31_t)0x2c2ee7ad, (q31_t)0x2c17504d,
+  (q31_t)0x2bffb73a, (q31_t)0x2be81c74,
+  (q31_t)0x2bd07ffe, (q31_t)0x2bb8e1d7, (q31_t)0x2ba14200, (q31_t)0x2b89a07b, (q31_t)0x2b71fd48, (q31_t)0x2b5a5868,
+  (q31_t)0x2b42b1dd, (q31_t)0x2b2b09a6,
+  (q31_t)0x2b135fc6, (q31_t)0x2afbb43c, (q31_t)0x2ae4070a, (q31_t)0x2acc5831, (q31_t)0x2ab4a7b1, (q31_t)0x2a9cf58c,
+  (q31_t)0x2a8541c3, (q31_t)0x2a6d8c55,
+  (q31_t)0x2a55d545, (q31_t)0x2a3e1c93, (q31_t)0x2a266240, (q31_t)0x2a0ea64d, (q31_t)0x29f6e8bb, (q31_t)0x29df298b,
+  (q31_t)0x29c768be, (q31_t)0x29afa654,
+  (q31_t)0x2997e24f, (q31_t)0x29801caf, (q31_t)0x29685576, (q31_t)0x29508ca4, (q31_t)0x2938c23a, (q31_t)0x2920f63a,
+  (q31_t)0x290928a3, (q31_t)0x28f15978,
+  (q31_t)0x28d988b8, (q31_t)0x28c1b666, (q31_t)0x28a9e281, (q31_t)0x28920d0a, (q31_t)0x287a3604, (q31_t)0x28625d6d,
+  (q31_t)0x284a8349, (q31_t)0x2832a796,
+  (q31_t)0x281aca57, (q31_t)0x2802eb8c, (q31_t)0x27eb0b36, (q31_t)0x27d32956, (q31_t)0x27bb45ed, (q31_t)0x27a360fc,
+  (q31_t)0x278b7a84, (q31_t)0x27739285,
+  (q31_t)0x275ba901, (q31_t)0x2743bdf9, (q31_t)0x272bd16d, (q31_t)0x2713e35f, (q31_t)0x26fbf3ce, (q31_t)0x26e402bd,
+  (q31_t)0x26cc102d, (q31_t)0x26b41c1d,
+  (q31_t)0x269c268f, (q31_t)0x26842f84, (q31_t)0x266c36fe, (q31_t)0x26543cfb, (q31_t)0x263c417f, (q31_t)0x26244489,
+  (q31_t)0x260c461b, (q31_t)0x25f44635,
+  (q31_t)0x25dc44d9, (q31_t)0x25c44207, (q31_t)0x25ac3dc0, (q31_t)0x25943806, (q31_t)0x257c30d8, (q31_t)0x25642839,
+  (q31_t)0x254c1e28, (q31_t)0x253412a8,
+  (q31_t)0x251c05b8, (q31_t)0x2503f75a, (q31_t)0x24ebe78f, (q31_t)0x24d3d657, (q31_t)0x24bbc3b4, (q31_t)0x24a3afa6,
+  (q31_t)0x248b9a2f, (q31_t)0x2473834f,
+  (q31_t)0x245b6b07, (q31_t)0x24435158, (q31_t)0x242b3644, (q31_t)0x241319ca, (q31_t)0x23fafbec, (q31_t)0x23e2dcac,
+  (q31_t)0x23cabc09, (q31_t)0x23b29a05,
+  (q31_t)0x239a76a0, (q31_t)0x238251dd, (q31_t)0x236a2bba, (q31_t)0x2352043b, (q31_t)0x2339db5e, (q31_t)0x2321b126,
+  (q31_t)0x23098593, (q31_t)0x22f158a7,
+  (q31_t)0x22d92a61, (q31_t)0x22c0fac4, (q31_t)0x22a8c9cf, (q31_t)0x22909785, (q31_t)0x227863e5, (q31_t)0x22602ef1,
+  (q31_t)0x2247f8aa, (q31_t)0x222fc111,
+  (q31_t)0x22178826, (q31_t)0x21ff4dea, (q31_t)0x21e71260, (q31_t)0x21ced586, (q31_t)0x21b6975f, (q31_t)0x219e57eb,
+  (q31_t)0x2186172b, (q31_t)0x216dd521,
+  (q31_t)0x215591cc, (q31_t)0x213d4d2f, (q31_t)0x21250749, (q31_t)0x210cc01d, (q31_t)0x20f477aa, (q31_t)0x20dc2df2,
+  (q31_t)0x20c3e2f5, (q31_t)0x20ab96b5,
+  (q31_t)0x20934933, (q31_t)0x207afa6f, (q31_t)0x2062aa6b, (q31_t)0x204a5927, (q31_t)0x203206a4, (q31_t)0x2019b2e4,
+  (q31_t)0x20015de7, (q31_t)0x1fe907ae,
+  (q31_t)0x1fd0b03a, (q31_t)0x1fb8578b, (q31_t)0x1f9ffda4, (q31_t)0x1f87a285, (q31_t)0x1f6f462f, (q31_t)0x1f56e8a2,
+  (q31_t)0x1f3e89e0, (q31_t)0x1f2629ea,
+  (q31_t)0x1f0dc8c0, (q31_t)0x1ef56664, (q31_t)0x1edd02d6, (q31_t)0x1ec49e17, (q31_t)0x1eac3829, (q31_t)0x1e93d10c,
+  (q31_t)0x1e7b68c2, (q31_t)0x1e62ff4a,
+  (q31_t)0x1e4a94a7, (q31_t)0x1e3228d9, (q31_t)0x1e19bbe0, (q31_t)0x1e014dbf, (q31_t)0x1de8de75, (q31_t)0x1dd06e04,
+  (q31_t)0x1db7fc6d, (q31_t)0x1d9f89b1,
+  (q31_t)0x1d8715d0, (q31_t)0x1d6ea0cc, (q31_t)0x1d562aa6, (q31_t)0x1d3db35e, (q31_t)0x1d253af5, (q31_t)0x1d0cc16c,
+  (q31_t)0x1cf446c5, (q31_t)0x1cdbcb00,
+  (q31_t)0x1cc34e1f, (q31_t)0x1caad021, (q31_t)0x1c925109, (q31_t)0x1c79d0d6, (q31_t)0x1c614f8b, (q31_t)0x1c48cd27,
+  (q31_t)0x1c3049ac, (q31_t)0x1c17c51b,
+  (q31_t)0x1bff3f75, (q31_t)0x1be6b8ba, (q31_t)0x1bce30ec, (q31_t)0x1bb5a80c, (q31_t)0x1b9d1e1a, (q31_t)0x1b849317,
+  (q31_t)0x1b6c0705, (q31_t)0x1b5379e5,
+  (q31_t)0x1b3aebb6, (q31_t)0x1b225c7b, (q31_t)0x1b09cc34, (q31_t)0x1af13ae3, (q31_t)0x1ad8a887, (q31_t)0x1ac01522,
+  (q31_t)0x1aa780b6, (q31_t)0x1a8eeb42,
+  (q31_t)0x1a7654c8, (q31_t)0x1a5dbd49, (q31_t)0x1a4524c6, (q31_t)0x1a2c8b3f, (q31_t)0x1a13f0b6, (q31_t)0x19fb552c,
+  (q31_t)0x19e2b8a2, (q31_t)0x19ca1b17,
+  (q31_t)0x19b17c8f, (q31_t)0x1998dd09, (q31_t)0x19803c86, (q31_t)0x19679b07, (q31_t)0x194ef88e, (q31_t)0x1936551b,
+  (q31_t)0x191db0af, (q31_t)0x19050b4b,
+  (q31_t)0x18ec64f0, (q31_t)0x18d3bda0, (q31_t)0x18bb155a, (q31_t)0x18a26c20, (q31_t)0x1889c1f3, (q31_t)0x187116d4,
+  (q31_t)0x18586ac3, (q31_t)0x183fbdc3,
+  (q31_t)0x18270fd3, (q31_t)0x180e60f4, (q31_t)0x17f5b129, (q31_t)0x17dd0070, (q31_t)0x17c44ecd, (q31_t)0x17ab9c3e,
+  (q31_t)0x1792e8c6, (q31_t)0x177a3466,
+  (q31_t)0x17617f1d, (q31_t)0x1748c8ee, (q31_t)0x173011d9, (q31_t)0x171759df, (q31_t)0x16fea102, (q31_t)0x16e5e741,
+  (q31_t)0x16cd2c9f, (q31_t)0x16b4711b,
+  (q31_t)0x169bb4b7, (q31_t)0x1682f774, (q31_t)0x166a3953, (q31_t)0x16517a55, (q31_t)0x1638ba7a, (q31_t)0x161ff9c4,
+  (q31_t)0x16073834, (q31_t)0x15ee75cb,
+  (q31_t)0x15d5b288, (q31_t)0x15bcee6f, (q31_t)0x15a4297f, (q31_t)0x158b63b9, (q31_t)0x15729d1f, (q31_t)0x1559d5b1,
+  (q31_t)0x15410d70, (q31_t)0x1528445d,
+  (q31_t)0x150f7a7a, (q31_t)0x14f6afc7, (q31_t)0x14dde445, (q31_t)0x14c517f4, (q31_t)0x14ac4ad7, (q31_t)0x14937cee,
+  (q31_t)0x147aae3a, (q31_t)0x1461debc,
+  (q31_t)0x14490e74, (q31_t)0x14303d65, (q31_t)0x14176b8e, (q31_t)0x13fe98f1, (q31_t)0x13e5c58e, (q31_t)0x13ccf167,
+  (q31_t)0x13b41c7d, (q31_t)0x139b46d0,
+  (q31_t)0x13827062, (q31_t)0x13699933, (q31_t)0x1350c144, (q31_t)0x1337e897, (q31_t)0x131f0f2c, (q31_t)0x13063505,
+  (q31_t)0x12ed5a21, (q31_t)0x12d47e83,
+  (q31_t)0x12bba22b, (q31_t)0x12a2c51b, (q31_t)0x1289e752, (q31_t)0x127108d2, (q31_t)0x1258299c, (q31_t)0x123f49b2,
+  (q31_t)0x12266913, (q31_t)0x120d87c1,
+  (q31_t)0x11f4a5bd, (q31_t)0x11dbc307, (q31_t)0x11c2dfa2, (q31_t)0x11a9fb8d, (q31_t)0x119116c9, (q31_t)0x11783159,
+  (q31_t)0x115f4b3c, (q31_t)0x11466473,
+  (q31_t)0x112d7d00, (q31_t)0x111494e4, (q31_t)0x10fbac1e, (q31_t)0x10e2c2b2, (q31_t)0x10c9d89e, (q31_t)0x10b0ede5,
+  (q31_t)0x10980287, (q31_t)0x107f1686,
+  (q31_t)0x106629e1, (q31_t)0x104d3c9b, (q31_t)0x10344eb4, (q31_t)0x101b602d, (q31_t)0x10027107, (q31_t)0xfe98143,
+  (q31_t)0xfd090e1, (q31_t)0xfb79fe4,
+  (q31_t)0xf9eae4c, (q31_t)0xf85bc19, (q31_t)0xf6cc94e, (q31_t)0xf53d5ea, (q31_t)0xf3ae1ee, (q31_t)0xf21ed5d, (q31_t)0xf08f836,
+  (q31_t)0xef0027b,
+  (q31_t)0xed70c2c, (q31_t)0xebe154b, (q31_t)0xea51dd8, (q31_t)0xe8c25d5, (q31_t)0xe732d42, (q31_t)0xe5a3421, (q31_t)0xe413a72,
+  (q31_t)0xe284036,
+  (q31_t)0xe0f456f, (q31_t)0xdf64a1c, (q31_t)0xddd4e40, (q31_t)0xdc451dc, (q31_t)0xdab54ef, (q31_t)0xd92577b, (q31_t)0xd795982,
+  (q31_t)0xd605b03,
+  (q31_t)0xd475c00, (q31_t)0xd2e5c7b, (q31_t)0xd155c73, (q31_t)0xcfc5bea, (q31_t)0xce35ae1, (q31_t)0xcca5959, (q31_t)0xcb15752,
+  (q31_t)0xc9854cf,
+  (q31_t)0xc7f51cf, (q31_t)0xc664e53, (q31_t)0xc4d4a5d, (q31_t)0xc3445ee, (q31_t)0xc1b4107, (q31_t)0xc023ba7, (q31_t)0xbe935d2,
+  (q31_t)0xbd02f87,
+  (q31_t)0xbb728c7, (q31_t)0xb9e2193, (q31_t)0xb8519ed, (q31_t)0xb6c11d5, (q31_t)0xb53094d, (q31_t)0xb3a0055, (q31_t)0xb20f6ee,
+  (q31_t)0xb07ed19,
+  (q31_t)0xaeee2d7, (q31_t)0xad5d829, (q31_t)0xabccd11, (q31_t)0xaa3c18e, (q31_t)0xa8ab5a2, (q31_t)0xa71a94f, (q31_t)0xa589c94,
+  (q31_t)0xa3f8f73,
+  (q31_t)0xa2681ed, (q31_t)0xa0d7403, (q31_t)0x9f465b5, (q31_t)0x9db5706, (q31_t)0x9c247f5, (q31_t)0x9a93884, (q31_t)0x99028b3,
+  (q31_t)0x9771884,
+  (q31_t)0x95e07f8, (q31_t)0x944f70f, (q31_t)0x92be5ca, (q31_t)0x912d42c, (q31_t)0x8f9c233, (q31_t)0x8e0afe2, (q31_t)0x8c79d3a,
+  (q31_t)0x8ae8a3a,
+  (q31_t)0x89576e5, (q31_t)0x87c633c, (q31_t)0x8634f3e, (q31_t)0x84a3aee, (q31_t)0x831264c, (q31_t)0x8181159, (q31_t)0x7fefc16,
+  (q31_t)0x7e5e685,
+  (q31_t)0x7ccd0a5, (q31_t)0x7b3ba78, (q31_t)0x79aa400, (q31_t)0x7818d3c, (q31_t)0x768762e, (q31_t)0x74f5ed7, (q31_t)0x7364738,
+  (q31_t)0x71d2f52,
+  (q31_t)0x7041726, (q31_t)0x6eafeb4, (q31_t)0x6d1e5fe, (q31_t)0x6b8cd05, (q31_t)0x69fb3c9, (q31_t)0x6869a4c, (q31_t)0x66d808f,
+  (q31_t)0x6546692,
+  (q31_t)0x63b4c57, (q31_t)0x62231de, (q31_t)0x6091729, (q31_t)0x5effc38, (q31_t)0x5d6e10c, (q31_t)0x5bdc5a7, (q31_t)0x5a4aa09,
+  (q31_t)0x58b8e34,
+  (q31_t)0x5727228, (q31_t)0x55955e6, (q31_t)0x540396f, (q31_t)0x5271cc4, (q31_t)0x50dffe7, (q31_t)0x4f4e2d8, (q31_t)0x4dbc597,
+  (q31_t)0x4c2a827,
+  (q31_t)0x4a98a88, (q31_t)0x4906cbb, (q31_t)0x4774ec1, (q31_t)0x45e309a, (q31_t)0x4451249, (q31_t)0x42bf3cd, (q31_t)0x412d528,
+  (q31_t)0x3f9b65b,
+  (q31_t)0x3e09767, (q31_t)0x3c7784d, (q31_t)0x3ae590d, (q31_t)0x39539a9, (q31_t)0x37c1a22, (q31_t)0x362fa78, (q31_t)0x349daac,
+  (q31_t)0x330bac1,
+  (q31_t)0x3179ab5, (q31_t)0x2fe7a8c, (q31_t)0x2e55a44, (q31_t)0x2cc39e1, (q31_t)0x2b31961, (q31_t)0x299f8c7, (q31_t)0x280d813,
+  (q31_t)0x267b747,
+  (q31_t)0x24e9662, (q31_t)0x2357567, (q31_t)0x21c5457, (q31_t)0x2033331, (q31_t)0x1ea11f7, (q31_t)0x1d0f0ab, (q31_t)0x1b7cf4d,
+  (q31_t)0x19eaddd,
+  (q31_t)0x1858c5e, (q31_t)0x16c6ad0, (q31_t)0x1534934, (q31_t)0x13a278a, (q31_t)0x12105d5, (q31_t)0x107e414, (q31_t)0xeec249,
+  (q31_t)0xd5a075,
+  (q31_t)0xbc7e99, (q31_t)0xa35cb5, (q31_t)0x8a3acb, (q31_t)0x7118dc, (q31_t)0x57f6e9, (q31_t)0x3ed4f2, (q31_t)0x25b2f8,
+  (q31_t)0xc90fe
+};
+
+static const q31_t cos_factorsQ31_8192[8192] = {
+  (q31_t)0x7ffffff6, (q31_t)0x7fffffa7, (q31_t)0x7fffff09, (q31_t)0x7ffffe1c, (q31_t)0x7ffffce1, (q31_t)0x7ffffb56,
+    (q31_t)0x7ffff97c, (q31_t)0x7ffff753,
+  (q31_t)0x7ffff4dc, (q31_t)0x7ffff215, (q31_t)0x7fffef00, (q31_t)0x7fffeb9b, (q31_t)0x7fffe7e8, (q31_t)0x7fffe3e5,
+    (q31_t)0x7fffdf94, (q31_t)0x7fffdaf3,
+  (q31_t)0x7fffd604, (q31_t)0x7fffd0c6, (q31_t)0x7fffcb39, (q31_t)0x7fffc55c, (q31_t)0x7fffbf31, (q31_t)0x7fffb8b7,
+    (q31_t)0x7fffb1ee, (q31_t)0x7fffaad6,
+  (q31_t)0x7fffa36f, (q31_t)0x7fff9bb9, (q31_t)0x7fff93b4, (q31_t)0x7fff8b61, (q31_t)0x7fff82be, (q31_t)0x7fff79cc,
+    (q31_t)0x7fff708b, (q31_t)0x7fff66fc,
+  (q31_t)0x7fff5d1d, (q31_t)0x7fff52ef, (q31_t)0x7fff4873, (q31_t)0x7fff3da8, (q31_t)0x7fff328d, (q31_t)0x7fff2724,
+    (q31_t)0x7fff1b6b, (q31_t)0x7fff0f64,
+  (q31_t)0x7fff030e, (q31_t)0x7ffef669, (q31_t)0x7ffee975, (q31_t)0x7ffedc31, (q31_t)0x7ffece9f, (q31_t)0x7ffec0be,
+    (q31_t)0x7ffeb28e, (q31_t)0x7ffea40f,
+  (q31_t)0x7ffe9542, (q31_t)0x7ffe8625, (q31_t)0x7ffe76b9, (q31_t)0x7ffe66fe, (q31_t)0x7ffe56f5, (q31_t)0x7ffe469c,
+    (q31_t)0x7ffe35f4, (q31_t)0x7ffe24fe,
+  (q31_t)0x7ffe13b8, (q31_t)0x7ffe0224, (q31_t)0x7ffdf040, (q31_t)0x7ffdde0e, (q31_t)0x7ffdcb8d, (q31_t)0x7ffdb8bc,
+    (q31_t)0x7ffda59d, (q31_t)0x7ffd922f,
+  (q31_t)0x7ffd7e72, (q31_t)0x7ffd6a66, (q31_t)0x7ffd560b, (q31_t)0x7ffd4161, (q31_t)0x7ffd2c68, (q31_t)0x7ffd1720,
+    (q31_t)0x7ffd0189, (q31_t)0x7ffceba4,
+  (q31_t)0x7ffcd56f, (q31_t)0x7ffcbeeb, (q31_t)0x7ffca819, (q31_t)0x7ffc90f7, (q31_t)0x7ffc7987, (q31_t)0x7ffc61c7,
+    (q31_t)0x7ffc49b9, (q31_t)0x7ffc315b,
+  (q31_t)0x7ffc18af, (q31_t)0x7ffbffb4, (q31_t)0x7ffbe66a, (q31_t)0x7ffbccd0, (q31_t)0x7ffbb2e8, (q31_t)0x7ffb98b1,
+    (q31_t)0x7ffb7e2b, (q31_t)0x7ffb6356,
+  (q31_t)0x7ffb4833, (q31_t)0x7ffb2cc0, (q31_t)0x7ffb10fe, (q31_t)0x7ffaf4ed, (q31_t)0x7ffad88e, (q31_t)0x7ffabbdf,
+    (q31_t)0x7ffa9ee2, (q31_t)0x7ffa8195,
+  (q31_t)0x7ffa63fa, (q31_t)0x7ffa460f, (q31_t)0x7ffa27d6, (q31_t)0x7ffa094e, (q31_t)0x7ff9ea76, (q31_t)0x7ff9cb50,
+    (q31_t)0x7ff9abdb, (q31_t)0x7ff98c17,
+  (q31_t)0x7ff96c04, (q31_t)0x7ff94ba2, (q31_t)0x7ff92af1, (q31_t)0x7ff909f2, (q31_t)0x7ff8e8a3, (q31_t)0x7ff8c705,
+    (q31_t)0x7ff8a519, (q31_t)0x7ff882dd,
+  (q31_t)0x7ff86053, (q31_t)0x7ff83d79, (q31_t)0x7ff81a51, (q31_t)0x7ff7f6da, (q31_t)0x7ff7d313, (q31_t)0x7ff7aefe,
+    (q31_t)0x7ff78a9a, (q31_t)0x7ff765e7,
+  (q31_t)0x7ff740e5, (q31_t)0x7ff71b94, (q31_t)0x7ff6f5f4, (q31_t)0x7ff6d005, (q31_t)0x7ff6a9c8, (q31_t)0x7ff6833b,
+    (q31_t)0x7ff65c5f, (q31_t)0x7ff63535,
+  (q31_t)0x7ff60dbb, (q31_t)0x7ff5e5f3, (q31_t)0x7ff5bddc, (q31_t)0x7ff59576, (q31_t)0x7ff56cc0, (q31_t)0x7ff543bc,
+    (q31_t)0x7ff51a69, (q31_t)0x7ff4f0c7,
+  (q31_t)0x7ff4c6d6, (q31_t)0x7ff49c96, (q31_t)0x7ff47208, (q31_t)0x7ff4472a, (q31_t)0x7ff41bfd, (q31_t)0x7ff3f082,
+    (q31_t)0x7ff3c4b7, (q31_t)0x7ff3989e,
+  (q31_t)0x7ff36c36, (q31_t)0x7ff33f7e, (q31_t)0x7ff31278, (q31_t)0x7ff2e523, (q31_t)0x7ff2b77f, (q31_t)0x7ff2898c,
+    (q31_t)0x7ff25b4a, (q31_t)0x7ff22cb9,
+  (q31_t)0x7ff1fdd9, (q31_t)0x7ff1ceab, (q31_t)0x7ff19f2d, (q31_t)0x7ff16f61, (q31_t)0x7ff13f45, (q31_t)0x7ff10edb,
+    (q31_t)0x7ff0de22, (q31_t)0x7ff0ad19,
+  (q31_t)0x7ff07bc2, (q31_t)0x7ff04a1c, (q31_t)0x7ff01827, (q31_t)0x7fefe5e4, (q31_t)0x7fefb351, (q31_t)0x7fef806f,
+    (q31_t)0x7fef4d3e, (q31_t)0x7fef19bf,
+  (q31_t)0x7feee5f0, (q31_t)0x7feeb1d3, (q31_t)0x7fee7d67, (q31_t)0x7fee48ac, (q31_t)0x7fee13a1, (q31_t)0x7fedde48,
+    (q31_t)0x7feda8a0, (q31_t)0x7fed72aa,
+  (q31_t)0x7fed3c64, (q31_t)0x7fed05cf, (q31_t)0x7fecceec, (q31_t)0x7fec97b9, (q31_t)0x7fec6038, (q31_t)0x7fec2867,
+    (q31_t)0x7febf048, (q31_t)0x7febb7da,
+  (q31_t)0x7feb7f1d, (q31_t)0x7feb4611, (q31_t)0x7feb0cb6, (q31_t)0x7fead30c, (q31_t)0x7fea9914, (q31_t)0x7fea5ecc,
+    (q31_t)0x7fea2436, (q31_t)0x7fe9e950,
+  (q31_t)0x7fe9ae1c, (q31_t)0x7fe97299, (q31_t)0x7fe936c7, (q31_t)0x7fe8faa6, (q31_t)0x7fe8be36, (q31_t)0x7fe88177,
+    (q31_t)0x7fe84469, (q31_t)0x7fe8070d,
+  (q31_t)0x7fe7c961, (q31_t)0x7fe78b67, (q31_t)0x7fe74d1e, (q31_t)0x7fe70e85, (q31_t)0x7fe6cf9e, (q31_t)0x7fe69068,
+    (q31_t)0x7fe650e3, (q31_t)0x7fe61110,
+  (q31_t)0x7fe5d0ed, (q31_t)0x7fe5907b, (q31_t)0x7fe54fbb, (q31_t)0x7fe50eac, (q31_t)0x7fe4cd4d, (q31_t)0x7fe48ba0,
+    (q31_t)0x7fe449a4, (q31_t)0x7fe40759,
+  (q31_t)0x7fe3c4bf, (q31_t)0x7fe381d7, (q31_t)0x7fe33e9f, (q31_t)0x7fe2fb19, (q31_t)0x7fe2b743, (q31_t)0x7fe2731f,
+    (q31_t)0x7fe22eac, (q31_t)0x7fe1e9ea,
+  (q31_t)0x7fe1a4d9, (q31_t)0x7fe15f79, (q31_t)0x7fe119cb, (q31_t)0x7fe0d3cd, (q31_t)0x7fe08d81, (q31_t)0x7fe046e5,
+    (q31_t)0x7fdffffb, (q31_t)0x7fdfb8c2,
+  (q31_t)0x7fdf713a, (q31_t)0x7fdf2963, (q31_t)0x7fdee13e, (q31_t)0x7fde98c9, (q31_t)0x7fde5006, (q31_t)0x7fde06f3,
+    (q31_t)0x7fddbd92, (q31_t)0x7fdd73e2,
+  (q31_t)0x7fdd29e3, (q31_t)0x7fdcdf95, (q31_t)0x7fdc94f9, (q31_t)0x7fdc4a0d, (q31_t)0x7fdbfed3, (q31_t)0x7fdbb349,
+    (q31_t)0x7fdb6771, (q31_t)0x7fdb1b4a,
+  (q31_t)0x7fdaced4, (q31_t)0x7fda820f, (q31_t)0x7fda34fc, (q31_t)0x7fd9e799, (q31_t)0x7fd999e8, (q31_t)0x7fd94be8,
+    (q31_t)0x7fd8fd98, (q31_t)0x7fd8aefa,
+  (q31_t)0x7fd8600e, (q31_t)0x7fd810d2, (q31_t)0x7fd7c147, (q31_t)0x7fd7716e, (q31_t)0x7fd72146, (q31_t)0x7fd6d0cf,
+    (q31_t)0x7fd68009, (q31_t)0x7fd62ef4,
+  (q31_t)0x7fd5dd90, (q31_t)0x7fd58bdd, (q31_t)0x7fd539dc, (q31_t)0x7fd4e78c, (q31_t)0x7fd494ed, (q31_t)0x7fd441ff,
+    (q31_t)0x7fd3eec2, (q31_t)0x7fd39b36,
+  (q31_t)0x7fd3475c, (q31_t)0x7fd2f332, (q31_t)0x7fd29eba, (q31_t)0x7fd249f3, (q31_t)0x7fd1f4dd, (q31_t)0x7fd19f78,
+    (q31_t)0x7fd149c5, (q31_t)0x7fd0f3c2,
+  (q31_t)0x7fd09d71, (q31_t)0x7fd046d1, (q31_t)0x7fcfefe2, (q31_t)0x7fcf98a4, (q31_t)0x7fcf4117, (q31_t)0x7fcee93c,
+    (q31_t)0x7fce9112, (q31_t)0x7fce3898,
+  (q31_t)0x7fcddfd0, (q31_t)0x7fcd86b9, (q31_t)0x7fcd2d54, (q31_t)0x7fccd39f, (q31_t)0x7fcc799c, (q31_t)0x7fcc1f4a,
+    (q31_t)0x7fcbc4a9, (q31_t)0x7fcb69b9,
+  (q31_t)0x7fcb0e7a, (q31_t)0x7fcab2ed, (q31_t)0x7fca5710, (q31_t)0x7fc9fae5, (q31_t)0x7fc99e6b, (q31_t)0x7fc941a2,
+    (q31_t)0x7fc8e48b, (q31_t)0x7fc88724,
+  (q31_t)0x7fc8296f, (q31_t)0x7fc7cb6b, (q31_t)0x7fc76d18, (q31_t)0x7fc70e76, (q31_t)0x7fc6af86, (q31_t)0x7fc65046,
+    (q31_t)0x7fc5f0b8, (q31_t)0x7fc590db,
+  (q31_t)0x7fc530af, (q31_t)0x7fc4d035, (q31_t)0x7fc46f6b, (q31_t)0x7fc40e53, (q31_t)0x7fc3acec, (q31_t)0x7fc34b36,
+    (q31_t)0x7fc2e931, (q31_t)0x7fc286de,
+  (q31_t)0x7fc2243b, (q31_t)0x7fc1c14a, (q31_t)0x7fc15e0a, (q31_t)0x7fc0fa7b, (q31_t)0x7fc0969e, (q31_t)0x7fc03271,
+    (q31_t)0x7fbfcdf6, (q31_t)0x7fbf692c,
+  (q31_t)0x7fbf0414, (q31_t)0x7fbe9eac, (q31_t)0x7fbe38f6, (q31_t)0x7fbdd2f0, (q31_t)0x7fbd6c9c, (q31_t)0x7fbd05fa,
+    (q31_t)0x7fbc9f08, (q31_t)0x7fbc37c8,
+  (q31_t)0x7fbbd039, (q31_t)0x7fbb685b, (q31_t)0x7fbb002e, (q31_t)0x7fba97b2, (q31_t)0x7fba2ee8, (q31_t)0x7fb9c5cf,
+    (q31_t)0x7fb95c67, (q31_t)0x7fb8f2b0,
+  (q31_t)0x7fb888ab, (q31_t)0x7fb81e57, (q31_t)0x7fb7b3b4, (q31_t)0x7fb748c2, (q31_t)0x7fb6dd81, (q31_t)0x7fb671f2,
+    (q31_t)0x7fb60614, (q31_t)0x7fb599e7,
+  (q31_t)0x7fb52d6b, (q31_t)0x7fb4c0a1, (q31_t)0x7fb45387, (q31_t)0x7fb3e61f, (q31_t)0x7fb37869, (q31_t)0x7fb30a63,
+    (q31_t)0x7fb29c0f, (q31_t)0x7fb22d6c,
+  (q31_t)0x7fb1be7a, (q31_t)0x7fb14f39, (q31_t)0x7fb0dfaa, (q31_t)0x7fb06fcb, (q31_t)0x7fafff9e, (q31_t)0x7faf8f23,
+    (q31_t)0x7faf1e58, (q31_t)0x7faead3f,
+  (q31_t)0x7fae3bd7, (q31_t)0x7fadca20, (q31_t)0x7fad581b, (q31_t)0x7face5c6, (q31_t)0x7fac7323, (q31_t)0x7fac0031,
+    (q31_t)0x7fab8cf1, (q31_t)0x7fab1962,
+  (q31_t)0x7faaa584, (q31_t)0x7faa3157, (q31_t)0x7fa9bcdb, (q31_t)0x7fa94811, (q31_t)0x7fa8d2f8, (q31_t)0x7fa85d90,
+    (q31_t)0x7fa7e7d9, (q31_t)0x7fa771d4,
+  (q31_t)0x7fa6fb80, (q31_t)0x7fa684dd, (q31_t)0x7fa60dec, (q31_t)0x7fa596ac, (q31_t)0x7fa51f1d, (q31_t)0x7fa4a73f,
+    (q31_t)0x7fa42f12, (q31_t)0x7fa3b697,
+  (q31_t)0x7fa33dcd, (q31_t)0x7fa2c4b5, (q31_t)0x7fa24b4d, (q31_t)0x7fa1d197, (q31_t)0x7fa15792, (q31_t)0x7fa0dd3f,
+    (q31_t)0x7fa0629c, (q31_t)0x7f9fe7ab,
+  (q31_t)0x7f9f6c6b, (q31_t)0x7f9ef0dd, (q31_t)0x7f9e7500, (q31_t)0x7f9df8d4, (q31_t)0x7f9d7c59, (q31_t)0x7f9cff90,
+    (q31_t)0x7f9c8278, (q31_t)0x7f9c0511,
+  (q31_t)0x7f9b875b, (q31_t)0x7f9b0957, (q31_t)0x7f9a8b04, (q31_t)0x7f9a0c62, (q31_t)0x7f998d72, (q31_t)0x7f990e33,
+    (q31_t)0x7f988ea5, (q31_t)0x7f980ec8,
+  (q31_t)0x7f978e9d, (q31_t)0x7f970e23, (q31_t)0x7f968d5b, (q31_t)0x7f960c43, (q31_t)0x7f958add, (q31_t)0x7f950929,
+    (q31_t)0x7f948725, (q31_t)0x7f9404d3,
+  (q31_t)0x7f938232, (q31_t)0x7f92ff43, (q31_t)0x7f927c04, (q31_t)0x7f91f878, (q31_t)0x7f91749c, (q31_t)0x7f90f072,
+    (q31_t)0x7f906bf9, (q31_t)0x7f8fe731,
+  (q31_t)0x7f8f621b, (q31_t)0x7f8edcb6, (q31_t)0x7f8e5702, (q31_t)0x7f8dd0ff, (q31_t)0x7f8d4aae, (q31_t)0x7f8cc40f,
+    (q31_t)0x7f8c3d20, (q31_t)0x7f8bb5e3,
+  (q31_t)0x7f8b2e57, (q31_t)0x7f8aa67d, (q31_t)0x7f8a1e54, (q31_t)0x7f8995dc, (q31_t)0x7f890d15, (q31_t)0x7f888400,
+    (q31_t)0x7f87fa9c, (q31_t)0x7f8770ea,
+  (q31_t)0x7f86e6e9, (q31_t)0x7f865c99, (q31_t)0x7f85d1fa, (q31_t)0x7f85470d, (q31_t)0x7f84bbd1, (q31_t)0x7f843047,
+    (q31_t)0x7f83a46e, (q31_t)0x7f831846,
+  (q31_t)0x7f828bcf, (q31_t)0x7f81ff0a, (q31_t)0x7f8171f6, (q31_t)0x7f80e494, (q31_t)0x7f8056e3, (q31_t)0x7f7fc8e3,
+    (q31_t)0x7f7f3a95, (q31_t)0x7f7eabf8,
+  (q31_t)0x7f7e1d0c, (q31_t)0x7f7d8dd2, (q31_t)0x7f7cfe49, (q31_t)0x7f7c6e71, (q31_t)0x7f7bde4b, (q31_t)0x7f7b4dd6,
+    (q31_t)0x7f7abd13, (q31_t)0x7f7a2c01,
+  (q31_t)0x7f799aa0, (q31_t)0x7f7908f0, (q31_t)0x7f7876f2, (q31_t)0x7f77e4a6, (q31_t)0x7f77520a, (q31_t)0x7f76bf21,
+    (q31_t)0x7f762be8, (q31_t)0x7f759861,
+  (q31_t)0x7f75048b, (q31_t)0x7f747067, (q31_t)0x7f73dbf4, (q31_t)0x7f734732, (q31_t)0x7f72b222, (q31_t)0x7f721cc3,
+    (q31_t)0x7f718715, (q31_t)0x7f70f119,
+  (q31_t)0x7f705ace, (q31_t)0x7f6fc435, (q31_t)0x7f6f2d4d, (q31_t)0x7f6e9617, (q31_t)0x7f6dfe91, (q31_t)0x7f6d66be,
+    (q31_t)0x7f6cce9b, (q31_t)0x7f6c362a,
+  (q31_t)0x7f6b9d6b, (q31_t)0x7f6b045d, (q31_t)0x7f6a6b00, (q31_t)0x7f69d154, (q31_t)0x7f69375a, (q31_t)0x7f689d12,
+    (q31_t)0x7f68027b, (q31_t)0x7f676795,
+  (q31_t)0x7f66cc61, (q31_t)0x7f6630de, (q31_t)0x7f65950c, (q31_t)0x7f64f8ec, (q31_t)0x7f645c7d, (q31_t)0x7f63bfc0,
+    (q31_t)0x7f6322b4, (q31_t)0x7f62855a,
+  (q31_t)0x7f61e7b1, (q31_t)0x7f6149b9, (q31_t)0x7f60ab73, (q31_t)0x7f600cdf, (q31_t)0x7f5f6dfb, (q31_t)0x7f5ecec9,
+    (q31_t)0x7f5e2f49, (q31_t)0x7f5d8f7a,
+  (q31_t)0x7f5cef5c, (q31_t)0x7f5c4ef0, (q31_t)0x7f5bae36, (q31_t)0x7f5b0d2c, (q31_t)0x7f5a6bd5, (q31_t)0x7f59ca2e,
+    (q31_t)0x7f592839, (q31_t)0x7f5885f6,
+  (q31_t)0x7f57e364, (q31_t)0x7f574083, (q31_t)0x7f569d54, (q31_t)0x7f55f9d6, (q31_t)0x7f55560a, (q31_t)0x7f54b1ef,
+    (q31_t)0x7f540d86, (q31_t)0x7f5368ce,
+  (q31_t)0x7f52c3c8, (q31_t)0x7f521e73, (q31_t)0x7f5178cf, (q31_t)0x7f50d2dd, (q31_t)0x7f502c9d, (q31_t)0x7f4f860e,
+    (q31_t)0x7f4edf30, (q31_t)0x7f4e3804,
+  (q31_t)0x7f4d9089, (q31_t)0x7f4ce8c0, (q31_t)0x7f4c40a8, (q31_t)0x7f4b9842, (q31_t)0x7f4aef8d, (q31_t)0x7f4a468a,
+    (q31_t)0x7f499d38, (q31_t)0x7f48f398,
+  (q31_t)0x7f4849a9, (q31_t)0x7f479f6c, (q31_t)0x7f46f4e0, (q31_t)0x7f464a06, (q31_t)0x7f459edd, (q31_t)0x7f44f365,
+    (q31_t)0x7f44479f, (q31_t)0x7f439b8b,
+  (q31_t)0x7f42ef28, (q31_t)0x7f424277, (q31_t)0x7f419577, (q31_t)0x7f40e828, (q31_t)0x7f403a8b, (q31_t)0x7f3f8ca0,
+    (q31_t)0x7f3ede66, (q31_t)0x7f3e2fde,
+  (q31_t)0x7f3d8107, (q31_t)0x7f3cd1e2, (q31_t)0x7f3c226e, (q31_t)0x7f3b72ab, (q31_t)0x7f3ac29b, (q31_t)0x7f3a123b,
+    (q31_t)0x7f39618e, (q31_t)0x7f38b091,
+  (q31_t)0x7f37ff47, (q31_t)0x7f374dad, (q31_t)0x7f369bc6, (q31_t)0x7f35e990, (q31_t)0x7f35370b, (q31_t)0x7f348438,
+    (q31_t)0x7f33d116, (q31_t)0x7f331da6,
+  (q31_t)0x7f3269e8, (q31_t)0x7f31b5db, (q31_t)0x7f31017f, (q31_t)0x7f304cd6, (q31_t)0x7f2f97dd, (q31_t)0x7f2ee296,
+    (q31_t)0x7f2e2d01, (q31_t)0x7f2d771e,
+  (q31_t)0x7f2cc0eb, (q31_t)0x7f2c0a6b, (q31_t)0x7f2b539c, (q31_t)0x7f2a9c7e, (q31_t)0x7f29e512, (q31_t)0x7f292d58,
+    (q31_t)0x7f28754f, (q31_t)0x7f27bcf8,
+  (q31_t)0x7f270452, (q31_t)0x7f264b5e, (q31_t)0x7f25921c, (q31_t)0x7f24d88b, (q31_t)0x7f241eab, (q31_t)0x7f23647e,
+    (q31_t)0x7f22aa01, (q31_t)0x7f21ef37,
+  (q31_t)0x7f21341e, (q31_t)0x7f2078b6, (q31_t)0x7f1fbd00, (q31_t)0x7f1f00fc, (q31_t)0x7f1e44a9, (q31_t)0x7f1d8808,
+    (q31_t)0x7f1ccb18, (q31_t)0x7f1c0dda,
+  (q31_t)0x7f1b504e, (q31_t)0x7f1a9273, (q31_t)0x7f19d44a, (q31_t)0x7f1915d2, (q31_t)0x7f18570c, (q31_t)0x7f1797f8,
+    (q31_t)0x7f16d895, (q31_t)0x7f1618e4,
+  (q31_t)0x7f1558e4, (q31_t)0x7f149896, (q31_t)0x7f13d7fa, (q31_t)0x7f13170f, (q31_t)0x7f1255d6, (q31_t)0x7f11944f,
+    (q31_t)0x7f10d279, (q31_t)0x7f101054,
+  (q31_t)0x7f0f4de2, (q31_t)0x7f0e8b21, (q31_t)0x7f0dc811, (q31_t)0x7f0d04b3, (q31_t)0x7f0c4107, (q31_t)0x7f0b7d0d,
+    (q31_t)0x7f0ab8c4, (q31_t)0x7f09f42d,
+  (q31_t)0x7f092f47, (q31_t)0x7f086a13, (q31_t)0x7f07a491, (q31_t)0x7f06dec0, (q31_t)0x7f0618a1, (q31_t)0x7f055233,
+    (q31_t)0x7f048b78, (q31_t)0x7f03c46d,
+  (q31_t)0x7f02fd15, (q31_t)0x7f02356e, (q31_t)0x7f016d79, (q31_t)0x7f00a535, (q31_t)0x7effdca4, (q31_t)0x7eff13c3,
+    (q31_t)0x7efe4a95, (q31_t)0x7efd8118,
+  (q31_t)0x7efcb74d, (q31_t)0x7efbed33, (q31_t)0x7efb22cb, (q31_t)0x7efa5815, (q31_t)0x7ef98d11, (q31_t)0x7ef8c1be,
+    (q31_t)0x7ef7f61d, (q31_t)0x7ef72a2d,
+  (q31_t)0x7ef65def, (q31_t)0x7ef59163, (q31_t)0x7ef4c489, (q31_t)0x7ef3f760, (q31_t)0x7ef329e9, (q31_t)0x7ef25c24,
+    (q31_t)0x7ef18e10, (q31_t)0x7ef0bfae,
+  (q31_t)0x7eeff0fe, (q31_t)0x7eef21ff, (q31_t)0x7eee52b2, (q31_t)0x7eed8317, (q31_t)0x7eecb32d, (q31_t)0x7eebe2f6,
+    (q31_t)0x7eeb1270, (q31_t)0x7eea419b,
+  (q31_t)0x7ee97079, (q31_t)0x7ee89f08, (q31_t)0x7ee7cd49, (q31_t)0x7ee6fb3b, (q31_t)0x7ee628df, (q31_t)0x7ee55635,
+    (q31_t)0x7ee4833d, (q31_t)0x7ee3aff6,
+  (q31_t)0x7ee2dc61, (q31_t)0x7ee2087e, (q31_t)0x7ee1344d, (q31_t)0x7ee05fcd, (q31_t)0x7edf8aff, (q31_t)0x7edeb5e3,
+    (q31_t)0x7edde079, (q31_t)0x7edd0ac0,
+  (q31_t)0x7edc34b9, (q31_t)0x7edb5e64, (q31_t)0x7eda87c0, (q31_t)0x7ed9b0ce, (q31_t)0x7ed8d98e, (q31_t)0x7ed80200,
+    (q31_t)0x7ed72a24, (q31_t)0x7ed651f9,
+  (q31_t)0x7ed57980, (q31_t)0x7ed4a0b9, (q31_t)0x7ed3c7a3, (q31_t)0x7ed2ee40, (q31_t)0x7ed2148e, (q31_t)0x7ed13a8e,
+    (q31_t)0x7ed0603f, (q31_t)0x7ecf85a3,
+  (q31_t)0x7eceaab8, (q31_t)0x7ecdcf7f, (q31_t)0x7eccf3f8, (q31_t)0x7ecc1822, (q31_t)0x7ecb3bff, (q31_t)0x7eca5f8d,
+    (q31_t)0x7ec982cd, (q31_t)0x7ec8a5bf,
+  (q31_t)0x7ec7c862, (q31_t)0x7ec6eab7, (q31_t)0x7ec60cbe, (q31_t)0x7ec52e77, (q31_t)0x7ec44fe2, (q31_t)0x7ec370fe,
+    (q31_t)0x7ec291cd, (q31_t)0x7ec1b24d,
+  (q31_t)0x7ec0d27f, (q31_t)0x7ebff263, (q31_t)0x7ebf11f8, (q31_t)0x7ebe313f, (q31_t)0x7ebd5039, (q31_t)0x7ebc6ee4,
+    (q31_t)0x7ebb8d40, (q31_t)0x7ebaab4f,
+  (q31_t)0x7eb9c910, (q31_t)0x7eb8e682, (q31_t)0x7eb803a6, (q31_t)0x7eb7207c, (q31_t)0x7eb63d04, (q31_t)0x7eb5593d,
+    (q31_t)0x7eb47529, (q31_t)0x7eb390c6,
+  (q31_t)0x7eb2ac15, (q31_t)0x7eb1c716, (q31_t)0x7eb0e1c9, (q31_t)0x7eaffc2e, (q31_t)0x7eaf1645, (q31_t)0x7eae300d,
+    (q31_t)0x7ead4987, (q31_t)0x7eac62b3,
+  (q31_t)0x7eab7b91, (q31_t)0x7eaa9421, (q31_t)0x7ea9ac63, (q31_t)0x7ea8c457, (q31_t)0x7ea7dbfc, (q31_t)0x7ea6f353,
+    (q31_t)0x7ea60a5d, (q31_t)0x7ea52118,
+  (q31_t)0x7ea43785, (q31_t)0x7ea34da4, (q31_t)0x7ea26374, (q31_t)0x7ea178f7, (q31_t)0x7ea08e2b, (q31_t)0x7e9fa312,
+    (q31_t)0x7e9eb7aa, (q31_t)0x7e9dcbf4,
+  (q31_t)0x7e9cdff0, (q31_t)0x7e9bf39e, (q31_t)0x7e9b06fe, (q31_t)0x7e9a1a10, (q31_t)0x7e992cd4, (q31_t)0x7e983f49,
+    (q31_t)0x7e975171, (q31_t)0x7e96634a,
+  (q31_t)0x7e9574d6, (q31_t)0x7e948613, (q31_t)0x7e939702, (q31_t)0x7e92a7a3, (q31_t)0x7e91b7f6, (q31_t)0x7e90c7fb,
+    (q31_t)0x7e8fd7b2, (q31_t)0x7e8ee71b,
+  (q31_t)0x7e8df636, (q31_t)0x7e8d0502, (q31_t)0x7e8c1381, (q31_t)0x7e8b21b1, (q31_t)0x7e8a2f94, (q31_t)0x7e893d28,
+    (q31_t)0x7e884a6f, (q31_t)0x7e875767,
+  (q31_t)0x7e866411, (q31_t)0x7e85706d, (q31_t)0x7e847c7c, (q31_t)0x7e83883c, (q31_t)0x7e8293ae, (q31_t)0x7e819ed2,
+    (q31_t)0x7e80a9a8, (q31_t)0x7e7fb430,
+  (q31_t)0x7e7ebe6a, (q31_t)0x7e7dc856, (q31_t)0x7e7cd1f4, (q31_t)0x7e7bdb44, (q31_t)0x7e7ae446, (q31_t)0x7e79ecf9,
+    (q31_t)0x7e78f55f, (q31_t)0x7e77fd77,
+  (q31_t)0x7e770541, (q31_t)0x7e760cbd, (q31_t)0x7e7513ea, (q31_t)0x7e741aca, (q31_t)0x7e73215c, (q31_t)0x7e7227a0,
+    (q31_t)0x7e712d96, (q31_t)0x7e70333d,
+  (q31_t)0x7e6f3897, (q31_t)0x7e6e3da3, (q31_t)0x7e6d4261, (q31_t)0x7e6c46d1, (q31_t)0x7e6b4af2, (q31_t)0x7e6a4ec6,
+    (q31_t)0x7e69524c, (q31_t)0x7e685584,
+  (q31_t)0x7e67586e, (q31_t)0x7e665b0a, (q31_t)0x7e655d58, (q31_t)0x7e645f58, (q31_t)0x7e63610a, (q31_t)0x7e62626e,
+    (q31_t)0x7e616384, (q31_t)0x7e60644c,
+  (q31_t)0x7e5f64c7, (q31_t)0x7e5e64f3, (q31_t)0x7e5d64d1, (q31_t)0x7e5c6461, (q31_t)0x7e5b63a4, (q31_t)0x7e5a6298,
+    (q31_t)0x7e59613f, (q31_t)0x7e585f97,
+  (q31_t)0x7e575da2, (q31_t)0x7e565b5f, (q31_t)0x7e5558ce, (q31_t)0x7e5455ef, (q31_t)0x7e5352c1, (q31_t)0x7e524f46,
+    (q31_t)0x7e514b7e, (q31_t)0x7e504767,
+  (q31_t)0x7e4f4302, (q31_t)0x7e4e3e4f, (q31_t)0x7e4d394f, (q31_t)0x7e4c3400, (q31_t)0x7e4b2e64, (q31_t)0x7e4a287a,
+    (q31_t)0x7e492241, (q31_t)0x7e481bbb,
+  (q31_t)0x7e4714e7, (q31_t)0x7e460dc5, (q31_t)0x7e450656, (q31_t)0x7e43fe98, (q31_t)0x7e42f68c, (q31_t)0x7e41ee33,
+    (q31_t)0x7e40e58c, (q31_t)0x7e3fdc97,
+  (q31_t)0x7e3ed353, (q31_t)0x7e3dc9c3, (q31_t)0x7e3cbfe4, (q31_t)0x7e3bb5b7, (q31_t)0x7e3aab3c, (q31_t)0x7e39a074,
+    (q31_t)0x7e38955e, (q31_t)0x7e3789fa,
+  (q31_t)0x7e367e48, (q31_t)0x7e357248, (q31_t)0x7e3465fa, (q31_t)0x7e33595e, (q31_t)0x7e324c75, (q31_t)0x7e313f3e,
+    (q31_t)0x7e3031b9, (q31_t)0x7e2f23e6,
+  (q31_t)0x7e2e15c5, (q31_t)0x7e2d0756, (q31_t)0x7e2bf89a, (q31_t)0x7e2ae990, (q31_t)0x7e29da38, (q31_t)0x7e28ca92,
+    (q31_t)0x7e27ba9e, (q31_t)0x7e26aa5d,
+  (q31_t)0x7e2599cd, (q31_t)0x7e2488f0, (q31_t)0x7e2377c5, (q31_t)0x7e22664c, (q31_t)0x7e215486, (q31_t)0x7e204271,
+    (q31_t)0x7e1f300f, (q31_t)0x7e1e1d5f,
+  (q31_t)0x7e1d0a61, (q31_t)0x7e1bf716, (q31_t)0x7e1ae37c, (q31_t)0x7e19cf95, (q31_t)0x7e18bb60, (q31_t)0x7e17a6dd,
+    (q31_t)0x7e16920d, (q31_t)0x7e157cee,
+  (q31_t)0x7e146782, (q31_t)0x7e1351c9, (q31_t)0x7e123bc1, (q31_t)0x7e11256c, (q31_t)0x7e100ec8, (q31_t)0x7e0ef7d7,
+    (q31_t)0x7e0de099, (q31_t)0x7e0cc90c,
+  (q31_t)0x7e0bb132, (q31_t)0x7e0a990a, (q31_t)0x7e098095, (q31_t)0x7e0867d1, (q31_t)0x7e074ec0, (q31_t)0x7e063561,
+    (q31_t)0x7e051bb4, (q31_t)0x7e0401ba,
+  (q31_t)0x7e02e772, (q31_t)0x7e01ccdc, (q31_t)0x7e00b1f9, (q31_t)0x7dff96c7, (q31_t)0x7dfe7b48, (q31_t)0x7dfd5f7b,
+    (q31_t)0x7dfc4361, (q31_t)0x7dfb26f9,
+  (q31_t)0x7dfa0a43, (q31_t)0x7df8ed3f, (q31_t)0x7df7cfee, (q31_t)0x7df6b24f, (q31_t)0x7df59462, (q31_t)0x7df47628,
+    (q31_t)0x7df357a0, (q31_t)0x7df238ca,
+  (q31_t)0x7df119a7, (q31_t)0x7deffa35, (q31_t)0x7deeda77, (q31_t)0x7dedba6a, (q31_t)0x7dec9a10, (q31_t)0x7deb7968,
+    (q31_t)0x7dea5872, (q31_t)0x7de9372f,
+  (q31_t)0x7de8159e, (q31_t)0x7de6f3c0, (q31_t)0x7de5d193, (q31_t)0x7de4af1a, (q31_t)0x7de38c52, (q31_t)0x7de2693d,
+    (q31_t)0x7de145da, (q31_t)0x7de02229,
+  (q31_t)0x7ddefe2b, (q31_t)0x7dddd9e0, (q31_t)0x7ddcb546, (q31_t)0x7ddb905f, (q31_t)0x7dda6b2a, (q31_t)0x7dd945a8,
+    (q31_t)0x7dd81fd8, (q31_t)0x7dd6f9ba,
+  (q31_t)0x7dd5d34f, (q31_t)0x7dd4ac96, (q31_t)0x7dd38590, (q31_t)0x7dd25e3c, (q31_t)0x7dd1369a, (q31_t)0x7dd00eab,
+    (q31_t)0x7dcee66e, (q31_t)0x7dcdbde3,
+  (q31_t)0x7dcc950b, (q31_t)0x7dcb6be6, (q31_t)0x7dca4272, (q31_t)0x7dc918b1, (q31_t)0x7dc7eea3, (q31_t)0x7dc6c447,
+    (q31_t)0x7dc5999d, (q31_t)0x7dc46ea6,
+  (q31_t)0x7dc34361, (q31_t)0x7dc217cf, (q31_t)0x7dc0ebef, (q31_t)0x7dbfbfc1, (q31_t)0x7dbe9346, (q31_t)0x7dbd667d,
+    (q31_t)0x7dbc3967, (q31_t)0x7dbb0c03,
+  (q31_t)0x7db9de52, (q31_t)0x7db8b053, (q31_t)0x7db78207, (q31_t)0x7db6536d, (q31_t)0x7db52485, (q31_t)0x7db3f550,
+    (q31_t)0x7db2c5cd, (q31_t)0x7db195fd,
+  (q31_t)0x7db065df, (q31_t)0x7daf3574, (q31_t)0x7dae04bb, (q31_t)0x7dacd3b5, (q31_t)0x7daba261, (q31_t)0x7daa70c0,
+    (q31_t)0x7da93ed1, (q31_t)0x7da80c95,
+  (q31_t)0x7da6da0b, (q31_t)0x7da5a733, (q31_t)0x7da4740e, (q31_t)0x7da3409c, (q31_t)0x7da20cdc, (q31_t)0x7da0d8cf,
+    (q31_t)0x7d9fa474, (q31_t)0x7d9e6fcb,
+  (q31_t)0x7d9d3ad6, (q31_t)0x7d9c0592, (q31_t)0x7d9ad001, (q31_t)0x7d999a23, (q31_t)0x7d9863f7, (q31_t)0x7d972d7e,
+    (q31_t)0x7d95f6b7, (q31_t)0x7d94bfa3,
+  (q31_t)0x7d938841, (q31_t)0x7d925092, (q31_t)0x7d911896, (q31_t)0x7d8fe04c, (q31_t)0x7d8ea7b4, (q31_t)0x7d8d6ecf,
+    (q31_t)0x7d8c359d, (q31_t)0x7d8afc1d,
+  (q31_t)0x7d89c250, (q31_t)0x7d888835, (q31_t)0x7d874dcd, (q31_t)0x7d861317, (q31_t)0x7d84d814, (q31_t)0x7d839cc4,
+    (q31_t)0x7d826126, (q31_t)0x7d81253a,
+  (q31_t)0x7d7fe902, (q31_t)0x7d7eac7c, (q31_t)0x7d7d6fa8, (q31_t)0x7d7c3287, (q31_t)0x7d7af519, (q31_t)0x7d79b75d,
+    (q31_t)0x7d787954, (q31_t)0x7d773afd,
+  (q31_t)0x7d75fc59, (q31_t)0x7d74bd68, (q31_t)0x7d737e29, (q31_t)0x7d723e9d, (q31_t)0x7d70fec4, (q31_t)0x7d6fbe9d,
+    (q31_t)0x7d6e7e29, (q31_t)0x7d6d3d67,
+  (q31_t)0x7d6bfc58, (q31_t)0x7d6abafc, (q31_t)0x7d697952, (q31_t)0x7d68375b, (q31_t)0x7d66f517, (q31_t)0x7d65b285,
+    (q31_t)0x7d646fa6, (q31_t)0x7d632c79,
+  (q31_t)0x7d61e8ff, (q31_t)0x7d60a538, (q31_t)0x7d5f6124, (q31_t)0x7d5e1cc2, (q31_t)0x7d5cd813, (q31_t)0x7d5b9316,
+    (q31_t)0x7d5a4dcc, (q31_t)0x7d590835,
+  (q31_t)0x7d57c251, (q31_t)0x7d567c1f, (q31_t)0x7d5535a0, (q31_t)0x7d53eed3, (q31_t)0x7d52a7ba, (q31_t)0x7d516053,
+    (q31_t)0x7d50189e, (q31_t)0x7d4ed09d,
+  (q31_t)0x7d4d884e, (q31_t)0x7d4c3fb1, (q31_t)0x7d4af6c8, (q31_t)0x7d49ad91, (q31_t)0x7d48640d, (q31_t)0x7d471a3c,
+    (q31_t)0x7d45d01d, (q31_t)0x7d4485b1,
+  (q31_t)0x7d433af8, (q31_t)0x7d41eff1, (q31_t)0x7d40a49e, (q31_t)0x7d3f58fd, (q31_t)0x7d3e0d0e, (q31_t)0x7d3cc0d3,
+    (q31_t)0x7d3b744a, (q31_t)0x7d3a2774,
+  (q31_t)0x7d38da51, (q31_t)0x7d378ce0, (q31_t)0x7d363f23, (q31_t)0x7d34f118, (q31_t)0x7d33a2bf, (q31_t)0x7d32541a,
+    (q31_t)0x7d310527, (q31_t)0x7d2fb5e7,
+  (q31_t)0x7d2e665a, (q31_t)0x7d2d1680, (q31_t)0x7d2bc659, (q31_t)0x7d2a75e4, (q31_t)0x7d292522, (q31_t)0x7d27d413,
+    (q31_t)0x7d2682b6, (q31_t)0x7d25310d,
+  (q31_t)0x7d23df16, (q31_t)0x7d228cd2, (q31_t)0x7d213a41, (q31_t)0x7d1fe762, (q31_t)0x7d1e9437, (q31_t)0x7d1d40be,
+    (q31_t)0x7d1becf8, (q31_t)0x7d1a98e5,
+  (q31_t)0x7d194485, (q31_t)0x7d17efd8, (q31_t)0x7d169add, (q31_t)0x7d154595, (q31_t)0x7d13f001, (q31_t)0x7d129a1f,
+    (q31_t)0x7d1143ef, (q31_t)0x7d0fed73,
+  (q31_t)0x7d0e96aa, (q31_t)0x7d0d3f93, (q31_t)0x7d0be82f, (q31_t)0x7d0a907e, (q31_t)0x7d093880, (q31_t)0x7d07e035,
+    (q31_t)0x7d06879d, (q31_t)0x7d052eb8,
+  (q31_t)0x7d03d585, (q31_t)0x7d027c05, (q31_t)0x7d012239, (q31_t)0x7cffc81f, (q31_t)0x7cfe6db8, (q31_t)0x7cfd1304,
+    (q31_t)0x7cfbb803, (q31_t)0x7cfa5cb4,
+  (q31_t)0x7cf90119, (q31_t)0x7cf7a531, (q31_t)0x7cf648fb, (q31_t)0x7cf4ec79, (q31_t)0x7cf38fa9, (q31_t)0x7cf2328c,
+    (q31_t)0x7cf0d522, (q31_t)0x7cef776b,
+  (q31_t)0x7cee1967, (q31_t)0x7cecbb16, (q31_t)0x7ceb5c78, (q31_t)0x7ce9fd8d, (q31_t)0x7ce89e55, (q31_t)0x7ce73ed0,
+    (q31_t)0x7ce5defd, (q31_t)0x7ce47ede,
+  (q31_t)0x7ce31e72, (q31_t)0x7ce1bdb8, (q31_t)0x7ce05cb2, (q31_t)0x7cdefb5e, (q31_t)0x7cdd99be, (q31_t)0x7cdc37d0,
+    (q31_t)0x7cdad596, (q31_t)0x7cd9730e,
+  (q31_t)0x7cd8103a, (q31_t)0x7cd6ad18, (q31_t)0x7cd549aa, (q31_t)0x7cd3e5ee, (q31_t)0x7cd281e5, (q31_t)0x7cd11d90,
+    (q31_t)0x7ccfb8ed, (q31_t)0x7cce53fe,
+  (q31_t)0x7ccceec1, (q31_t)0x7ccb8937, (q31_t)0x7cca2361, (q31_t)0x7cc8bd3d, (q31_t)0x7cc756cd, (q31_t)0x7cc5f010,
+    (q31_t)0x7cc48905, (q31_t)0x7cc321ae,
+  (q31_t)0x7cc1ba09, (q31_t)0x7cc05218, (q31_t)0x7cbee9da, (q31_t)0x7cbd814f, (q31_t)0x7cbc1877, (q31_t)0x7cbaaf51,
+    (q31_t)0x7cb945df, (q31_t)0x7cb7dc20,
+  (q31_t)0x7cb67215, (q31_t)0x7cb507bc, (q31_t)0x7cb39d16, (q31_t)0x7cb23223, (q31_t)0x7cb0c6e4, (q31_t)0x7caf5b57,
+    (q31_t)0x7cadef7e, (q31_t)0x7cac8358,
+  (q31_t)0x7cab16e4, (q31_t)0x7ca9aa24, (q31_t)0x7ca83d17, (q31_t)0x7ca6cfbd, (q31_t)0x7ca56216, (q31_t)0x7ca3f423,
+    (q31_t)0x7ca285e2, (q31_t)0x7ca11755,
+  (q31_t)0x7c9fa87a, (q31_t)0x7c9e3953, (q31_t)0x7c9cc9df, (q31_t)0x7c9b5a1e, (q31_t)0x7c99ea10, (q31_t)0x7c9879b6,
+    (q31_t)0x7c97090e, (q31_t)0x7c95981a,
+  (q31_t)0x7c9426d8, (q31_t)0x7c92b54a, (q31_t)0x7c91436f, (q31_t)0x7c8fd148, (q31_t)0x7c8e5ed3, (q31_t)0x7c8cec12,
+    (q31_t)0x7c8b7903, (q31_t)0x7c8a05a8,
+  (q31_t)0x7c889200, (q31_t)0x7c871e0c, (q31_t)0x7c85a9ca, (q31_t)0x7c84353c, (q31_t)0x7c82c060, (q31_t)0x7c814b39,
+    (q31_t)0x7c7fd5c4, (q31_t)0x7c7e6002,
+  (q31_t)0x7c7ce9f4, (q31_t)0x7c7b7399, (q31_t)0x7c79fcf1, (q31_t)0x7c7885fc, (q31_t)0x7c770eba, (q31_t)0x7c75972c,
+    (q31_t)0x7c741f51, (q31_t)0x7c72a729,
+  (q31_t)0x7c712eb5, (q31_t)0x7c6fb5f3, (q31_t)0x7c6e3ce5, (q31_t)0x7c6cc38a, (q31_t)0x7c6b49e3, (q31_t)0x7c69cfee,
+    (q31_t)0x7c6855ad, (q31_t)0x7c66db1f,
+  (q31_t)0x7c656045, (q31_t)0x7c63e51e, (q31_t)0x7c6269aa, (q31_t)0x7c60ede9, (q31_t)0x7c5f71db, (q31_t)0x7c5df581,
+    (q31_t)0x7c5c78da, (q31_t)0x7c5afbe6,
+  (q31_t)0x7c597ea6, (q31_t)0x7c580119, (q31_t)0x7c56833f, (q31_t)0x7c550519, (q31_t)0x7c5386a6, (q31_t)0x7c5207e6,
+    (q31_t)0x7c5088d9, (q31_t)0x7c4f0980,
+  (q31_t)0x7c4d89da, (q31_t)0x7c4c09e8, (q31_t)0x7c4a89a8, (q31_t)0x7c49091c, (q31_t)0x7c478844, (q31_t)0x7c46071f,
+    (q31_t)0x7c4485ad, (q31_t)0x7c4303ee,
+  (q31_t)0x7c4181e3, (q31_t)0x7c3fff8b, (q31_t)0x7c3e7ce7, (q31_t)0x7c3cf9f5, (q31_t)0x7c3b76b8, (q31_t)0x7c39f32d,
+    (q31_t)0x7c386f56, (q31_t)0x7c36eb33,
+  (q31_t)0x7c3566c2, (q31_t)0x7c33e205, (q31_t)0x7c325cfc, (q31_t)0x7c30d7a6, (q31_t)0x7c2f5203, (q31_t)0x7c2dcc14,
+    (q31_t)0x7c2c45d8, (q31_t)0x7c2abf4f,
+  (q31_t)0x7c29387a, (q31_t)0x7c27b158, (q31_t)0x7c2629ea, (q31_t)0x7c24a22f, (q31_t)0x7c231a28, (q31_t)0x7c2191d4,
+    (q31_t)0x7c200933, (q31_t)0x7c1e8046,
+  (q31_t)0x7c1cf70c, (q31_t)0x7c1b6d86, (q31_t)0x7c19e3b3, (q31_t)0x7c185994, (q31_t)0x7c16cf28, (q31_t)0x7c15446f,
+    (q31_t)0x7c13b96a, (q31_t)0x7c122e19,
+  (q31_t)0x7c10a27b, (q31_t)0x7c0f1690, (q31_t)0x7c0d8a59, (q31_t)0x7c0bfdd5, (q31_t)0x7c0a7105, (q31_t)0x7c08e3e8,
+    (q31_t)0x7c07567f, (q31_t)0x7c05c8c9,
+  (q31_t)0x7c043ac7, (q31_t)0x7c02ac78, (q31_t)0x7c011ddd, (q31_t)0x7bff8ef5, (q31_t)0x7bfdffc1, (q31_t)0x7bfc7041,
+    (q31_t)0x7bfae073, (q31_t)0x7bf9505a,
+  (q31_t)0x7bf7bff4, (q31_t)0x7bf62f41, (q31_t)0x7bf49e42, (q31_t)0x7bf30cf6, (q31_t)0x7bf17b5e, (q31_t)0x7befe97a,
+    (q31_t)0x7bee5749, (q31_t)0x7becc4cc,
+  (q31_t)0x7beb3202, (q31_t)0x7be99eec, (q31_t)0x7be80b89, (q31_t)0x7be677da, (q31_t)0x7be4e3df, (q31_t)0x7be34f97,
+    (q31_t)0x7be1bb02, (q31_t)0x7be02621,
+  (q31_t)0x7bde90f4, (q31_t)0x7bdcfb7b, (q31_t)0x7bdb65b5, (q31_t)0x7bd9cfa2, (q31_t)0x7bd83944, (q31_t)0x7bd6a298,
+    (q31_t)0x7bd50ba1, (q31_t)0x7bd3745d,
+  (q31_t)0x7bd1dccc, (q31_t)0x7bd044f0, (q31_t)0x7bceacc7, (q31_t)0x7bcd1451, (q31_t)0x7bcb7b8f, (q31_t)0x7bc9e281,
+    (q31_t)0x7bc84927, (q31_t)0x7bc6af80,
+  (q31_t)0x7bc5158c, (q31_t)0x7bc37b4d, (q31_t)0x7bc1e0c1, (q31_t)0x7bc045e9, (q31_t)0x7bbeaac4, (q31_t)0x7bbd0f53,
+    (q31_t)0x7bbb7396, (q31_t)0x7bb9d78c,
+  (q31_t)0x7bb83b36, (q31_t)0x7bb69e94, (q31_t)0x7bb501a5, (q31_t)0x7bb3646a, (q31_t)0x7bb1c6e3, (q31_t)0x7bb02910,
+    (q31_t)0x7bae8af0, (q31_t)0x7bacec84,
+  (q31_t)0x7bab4dcc, (q31_t)0x7ba9aec7, (q31_t)0x7ba80f76, (q31_t)0x7ba66fd9, (q31_t)0x7ba4cfef, (q31_t)0x7ba32fba,
+    (q31_t)0x7ba18f38, (q31_t)0x7b9fee69,
+  (q31_t)0x7b9e4d4f, (q31_t)0x7b9cabe8, (q31_t)0x7b9b0a35, (q31_t)0x7b996836, (q31_t)0x7b97c5ea, (q31_t)0x7b962352,
+    (q31_t)0x7b94806e, (q31_t)0x7b92dd3e,
+  (q31_t)0x7b9139c2, (q31_t)0x7b8f95f9, (q31_t)0x7b8df1e4, (q31_t)0x7b8c4d83, (q31_t)0x7b8aa8d6, (q31_t)0x7b8903dc,
+    (q31_t)0x7b875e96, (q31_t)0x7b85b904,
+  (q31_t)0x7b841326, (q31_t)0x7b826cfc, (q31_t)0x7b80c686, (q31_t)0x7b7f1fc3, (q31_t)0x7b7d78b4, (q31_t)0x7b7bd159,
+    (q31_t)0x7b7a29b2, (q31_t)0x7b7881be,
+  (q31_t)0x7b76d97f, (q31_t)0x7b7530f3, (q31_t)0x7b73881b, (q31_t)0x7b71def7, (q31_t)0x7b703587, (q31_t)0x7b6e8bcb,
+    (q31_t)0x7b6ce1c2, (q31_t)0x7b6b376e,
+  (q31_t)0x7b698ccd, (q31_t)0x7b67e1e0, (q31_t)0x7b6636a7, (q31_t)0x7b648b22, (q31_t)0x7b62df51, (q31_t)0x7b613334,
+    (q31_t)0x7b5f86ca, (q31_t)0x7b5dda15,
+  (q31_t)0x7b5c2d13, (q31_t)0x7b5a7fc6, (q31_t)0x7b58d22c, (q31_t)0x7b572446, (q31_t)0x7b557614, (q31_t)0x7b53c796,
+    (q31_t)0x7b5218cc, (q31_t)0x7b5069b6,
+  (q31_t)0x7b4eba53, (q31_t)0x7b4d0aa5, (q31_t)0x7b4b5aab, (q31_t)0x7b49aa64, (q31_t)0x7b47f9d2, (q31_t)0x7b4648f3,
+    (q31_t)0x7b4497c9, (q31_t)0x7b42e652,
+  (q31_t)0x7b413490, (q31_t)0x7b3f8281, (q31_t)0x7b3dd026, (q31_t)0x7b3c1d80, (q31_t)0x7b3a6a8d, (q31_t)0x7b38b74e,
+    (q31_t)0x7b3703c3, (q31_t)0x7b354fed,
+  (q31_t)0x7b339bca, (q31_t)0x7b31e75b, (q31_t)0x7b3032a0, (q31_t)0x7b2e7d9a, (q31_t)0x7b2cc847, (q31_t)0x7b2b12a8,
+    (q31_t)0x7b295cbe, (q31_t)0x7b27a687,
+  (q31_t)0x7b25f004, (q31_t)0x7b243936, (q31_t)0x7b22821b, (q31_t)0x7b20cab5, (q31_t)0x7b1f1302, (q31_t)0x7b1d5b04,
+    (q31_t)0x7b1ba2b9, (q31_t)0x7b19ea23,
+  (q31_t)0x7b183141, (q31_t)0x7b167813, (q31_t)0x7b14be99, (q31_t)0x7b1304d3, (q31_t)0x7b114ac1, (q31_t)0x7b0f9063,
+    (q31_t)0x7b0dd5b9, (q31_t)0x7b0c1ac4,
+  (q31_t)0x7b0a5f82, (q31_t)0x7b08a3f5, (q31_t)0x7b06e81b, (q31_t)0x7b052bf6, (q31_t)0x7b036f85, (q31_t)0x7b01b2c8,
+    (q31_t)0x7afff5bf, (q31_t)0x7afe386a,
+  (q31_t)0x7afc7aca, (q31_t)0x7afabcdd, (q31_t)0x7af8fea5, (q31_t)0x7af74021, (q31_t)0x7af58151, (q31_t)0x7af3c235,
+    (q31_t)0x7af202cd, (q31_t)0x7af0431a,
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+    (q31_t)0x7ae3fce6, (q31_t)0x7ae23ad4,
+  (q31_t)0x7ae07876, (q31_t)0x7adeb5cc, (q31_t)0x7adcf2d6, (q31_t)0x7adb2f95, (q31_t)0x7ad96c08, (q31_t)0x7ad7a82f,
+    (q31_t)0x7ad5e40a, (q31_t)0x7ad41f9a,
+  (q31_t)0x7ad25ade, (q31_t)0x7ad095d6, (q31_t)0x7aced082, (q31_t)0x7acd0ae3, (q31_t)0x7acb44f8, (q31_t)0x7ac97ec1,
+    (q31_t)0x7ac7b83e, (q31_t)0x7ac5f170,
+  (q31_t)0x7ac42a55, (q31_t)0x7ac262ef, (q31_t)0x7ac09b3e, (q31_t)0x7abed341, (q31_t)0x7abd0af7, (q31_t)0x7abb4263,
+    (q31_t)0x7ab97982, (q31_t)0x7ab7b056,
+  (q31_t)0x7ab5e6de, (q31_t)0x7ab41d1b, (q31_t)0x7ab2530b, (q31_t)0x7ab088b0, (q31_t)0x7aaebe0a, (q31_t)0x7aacf318,
+    (q31_t)0x7aab27da, (q31_t)0x7aa95c50,
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+    (q31_t)0x7a9cc346, (q31_t)0x7a9af55f,
+  (q31_t)0x7a99272d, (q31_t)0x7a9758af, (q31_t)0x7a9589e5, (q31_t)0x7a93bad0, (q31_t)0x7a91eb6f, (q31_t)0x7a901bc2,
+    (q31_t)0x7a8e4bca, (q31_t)0x7a8c7b87,
+  (q31_t)0x7a8aaaf7, (q31_t)0x7a88da1c, (q31_t)0x7a8708f6, (q31_t)0x7a853784, (q31_t)0x7a8365c6, (q31_t)0x7a8193bd,
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+  (q31_t)0x7a6d79dd, (q31_t)0x7a6ba449, (q31_t)0x7a69ce6a, (q31_t)0x7a67f83f, (q31_t)0x7a6621c9, (q31_t)0x7a644b07,
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+  (q31_t)0x7a4ffd3d, (q31_t)0x7a4e22f2, (q31_t)0x7a4c485b, (q31_t)0x7a4a6d78, (q31_t)0x7a48924b, (q31_t)0x7a46b6d1,
+    (q31_t)0x7a44db0d, (q31_t)0x7a42fefd,
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+    (q31_t)0x7a17e845, (q31_t)0x7a160524,
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+    (q31_t)0x7a08c702, (q31_t)0x7a06e187,
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+    (q31_t)0x798d1832, (q31_t)0x798b1fef,
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+    (q31_t)0x797d4de5, (q31_t)0x797b534a,
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+  (q31_t)0x79497b13, (q31_t)0x794778dd, (q31_t)0x7945765d, (q31_t)0x79437391, (q31_t)0x7941707b, (q31_t)0x793f6d1a,
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+    (q31_t)0x792d418d, (q31_t)0x792b3b40,
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+    (q31_t)0x790cb9bd, (q31_t)0x790aaec5,
+  (q31_t)0x7908a382, (q31_t)0x790697f5, (q31_t)0x79048c1d, (q31_t)0x79027ffa, (q31_t)0x7900738d, (q31_t)0x78fe66d5,
+    (q31_t)0x78fc59d3, (q31_t)0x78fa4c86,
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+    (q31_t)0x78ebe741, (q31_t)0x78e9d79f,
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+    (q31_t)0x78db6209, (q31_t)0x78d95012,
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+    (q31_t)0x78caca2e, (q31_t)0x78c8b5e3,
+  (q31_t)0x78c6a14e, (q31_t)0x78c48c6e, (q31_t)0x78c27744, (q31_t)0x78c061cf, (q31_t)0x78be4c10, (q31_t)0x78bc3606,
+    (q31_t)0x78ba1fb2, (q31_t)0x78b80913,
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+    (q31_t)0x78a96298, (q31_t)0x78a749a6,
+  (q31_t)0x78a53069, (q31_t)0x78a316e2, (q31_t)0x78a0fd11, (q31_t)0x789ee2f5, (q31_t)0x789cc88f, (q31_t)0x789aadde,
+    (q31_t)0x789892e3, (q31_t)0x7896779d,
+  (q31_t)0x78945c0d, (q31_t)0x78924033, (q31_t)0x7890240e, (q31_t)0x788e07a0, (q31_t)0x788beae6, (q31_t)0x7889cde2,
+    (q31_t)0x7887b094, (q31_t)0x788592fc,
+  (q31_t)0x78837519, (q31_t)0x788156ec, (q31_t)0x787f3875, (q31_t)0x787d19b3, (q31_t)0x787afaa7, (q31_t)0x7878db50,
+    (q31_t)0x7876bbb0, (q31_t)0x78749bc5,
+  (q31_t)0x78727b8f, (q31_t)0x78705b10, (q31_t)0x786e3a46, (q31_t)0x786c1932, (q31_t)0x7869f7d3, (q31_t)0x7867d62a,
+    (q31_t)0x7865b437, (q31_t)0x786391fa,
+  (q31_t)0x78616f72, (q31_t)0x785f4ca1, (q31_t)0x785d2984, (q31_t)0x785b061e, (q31_t)0x7858e26e, (q31_t)0x7856be73,
+    (q31_t)0x78549a2e, (q31_t)0x7852759e,
+  (q31_t)0x785050c5, (q31_t)0x784e2ba1, (q31_t)0x784c0633, (q31_t)0x7849e07b, (q31_t)0x7847ba79, (q31_t)0x7845942c,
+    (q31_t)0x78436d96, (q31_t)0x784146b5,
+  (q31_t)0x783f1f8a, (q31_t)0x783cf815, (q31_t)0x783ad055, (q31_t)0x7838a84c, (q31_t)0x78367ff8, (q31_t)0x7834575a,
+    (q31_t)0x78322e72, (q31_t)0x78300540,
+  (q31_t)0x782ddbc4, (q31_t)0x782bb1fd, (q31_t)0x782987ed, (q31_t)0x78275d92, (q31_t)0x782532ed, (q31_t)0x782307fe,
+    (q31_t)0x7820dcc5, (q31_t)0x781eb142,
+  (q31_t)0x781c8575, (q31_t)0x781a595d, (q31_t)0x78182cfc, (q31_t)0x78160051, (q31_t)0x7813d35b, (q31_t)0x7811a61b,
+    (q31_t)0x780f7892, (q31_t)0x780d4abe,
+  (q31_t)0x780b1ca0, (q31_t)0x7808ee38, (q31_t)0x7806bf86, (q31_t)0x7804908a, (q31_t)0x78026145, (q31_t)0x780031b5,
+    (q31_t)0x77fe01db, (q31_t)0x77fbd1b6,
+  (q31_t)0x77f9a148, (q31_t)0x77f77090, (q31_t)0x77f53f8e, (q31_t)0x77f30e42, (q31_t)0x77f0dcac, (q31_t)0x77eeaacc,
+    (q31_t)0x77ec78a2, (q31_t)0x77ea462e,
+  (q31_t)0x77e81370, (q31_t)0x77e5e068, (q31_t)0x77e3ad17, (q31_t)0x77e1797b, (q31_t)0x77df4595, (q31_t)0x77dd1165,
+    (q31_t)0x77dadcec, (q31_t)0x77d8a828,
+  (q31_t)0x77d6731a, (q31_t)0x77d43dc3, (q31_t)0x77d20822, (q31_t)0x77cfd236, (q31_t)0x77cd9c01, (q31_t)0x77cb6582,
+    (q31_t)0x77c92eb9, (q31_t)0x77c6f7a6,
+  (q31_t)0x77c4c04a, (q31_t)0x77c288a3, (q31_t)0x77c050b2, (q31_t)0x77be1878, (q31_t)0x77bbdff4, (q31_t)0x77b9a726,
+    (q31_t)0x77b76e0e, (q31_t)0x77b534ac,
+  (q31_t)0x77b2fb00, (q31_t)0x77b0c10b, (q31_t)0x77ae86cc, (q31_t)0x77ac4c43, (q31_t)0x77aa1170, (q31_t)0x77a7d653,
+    (q31_t)0x77a59aec, (q31_t)0x77a35f3c,
+  (q31_t)0x77a12342, (q31_t)0x779ee6fe, (q31_t)0x779caa70, (q31_t)0x779a6d99, (q31_t)0x77983077, (q31_t)0x7795f30c,
+    (q31_t)0x7793b557, (q31_t)0x77917759,
+  (q31_t)0x778f3910, (q31_t)0x778cfa7e, (q31_t)0x778abba2, (q31_t)0x77887c7d, (q31_t)0x77863d0d, (q31_t)0x7783fd54,
+    (q31_t)0x7781bd52, (q31_t)0x777f7d05,
+  (q31_t)0x777d3c6f, (q31_t)0x777afb8f, (q31_t)0x7778ba65, (q31_t)0x777678f2, (q31_t)0x77743735, (q31_t)0x7771f52e,
+    (q31_t)0x776fb2de, (q31_t)0x776d7044,
+  (q31_t)0x776b2d60, (q31_t)0x7768ea33, (q31_t)0x7766a6bc, (q31_t)0x776462fb, (q31_t)0x77621ef1, (q31_t)0x775fda9d,
+    (q31_t)0x775d95ff, (q31_t)0x775b5118,
+  (q31_t)0x77590be7, (q31_t)0x7756c66c, (q31_t)0x775480a8, (q31_t)0x77523a9b, (q31_t)0x774ff443, (q31_t)0x774dada2,
+    (q31_t)0x774b66b8, (q31_t)0x77491f84,
+  (q31_t)0x7746d806, (q31_t)0x7744903f, (q31_t)0x7742482e, (q31_t)0x773fffd4, (q31_t)0x773db730, (q31_t)0x773b6e42,
+    (q31_t)0x7739250b, (q31_t)0x7736db8b,
+  (q31_t)0x773491c0, (q31_t)0x773247ad, (q31_t)0x772ffd50, (q31_t)0x772db2a9, (q31_t)0x772b67b9, (q31_t)0x77291c7f,
+    (q31_t)0x7726d0fc, (q31_t)0x7724852f,
+  (q31_t)0x77223919, (q31_t)0x771fecb9, (q31_t)0x771da010, (q31_t)0x771b531d, (q31_t)0x771905e1, (q31_t)0x7716b85b,
+    (q31_t)0x77146a8c, (q31_t)0x77121c74,
+  (q31_t)0x770fce12, (q31_t)0x770d7f66, (q31_t)0x770b3072, (q31_t)0x7708e133, (q31_t)0x770691ab, (q31_t)0x770441da,
+    (q31_t)0x7701f1c0, (q31_t)0x76ffa15c,
+  (q31_t)0x76fd50ae, (q31_t)0x76faffb8, (q31_t)0x76f8ae78, (q31_t)0x76f65cee, (q31_t)0x76f40b1b, (q31_t)0x76f1b8ff,
+    (q31_t)0x76ef6699, (q31_t)0x76ed13ea,
+  (q31_t)0x76eac0f2, (q31_t)0x76e86db0, (q31_t)0x76e61a25, (q31_t)0x76e3c650, (q31_t)0x76e17233, (q31_t)0x76df1dcb,
+    (q31_t)0x76dcc91b, (q31_t)0x76da7421,
+  (q31_t)0x76d81ede, (q31_t)0x76d5c952, (q31_t)0x76d3737c, (q31_t)0x76d11d5d, (q31_t)0x76cec6f5, (q31_t)0x76cc7043,
+    (q31_t)0x76ca1948, (q31_t)0x76c7c204,
+  (q31_t)0x76c56a77, (q31_t)0x76c312a0, (q31_t)0x76c0ba80, (q31_t)0x76be6217, (q31_t)0x76bc0965, (q31_t)0x76b9b069,
+    (q31_t)0x76b75724, (q31_t)0x76b4fd96,
+  (q31_t)0x76b2a3bf, (q31_t)0x76b0499e, (q31_t)0x76adef34, (q31_t)0x76ab9481, (q31_t)0x76a93985, (q31_t)0x76a6de40,
+    (q31_t)0x76a482b1, (q31_t)0x76a226da,
+  (q31_t)0x769fcab9, (q31_t)0x769d6e4f, (q31_t)0x769b119b, (q31_t)0x7698b49f, (q31_t)0x76965759, (q31_t)0x7693f9ca,
+    (q31_t)0x76919bf3, (q31_t)0x768f3dd2,
+  (q31_t)0x768cdf67, (q31_t)0x768a80b4, (q31_t)0x768821b8, (q31_t)0x7685c272, (q31_t)0x768362e4, (q31_t)0x7681030c,
+    (q31_t)0x767ea2eb, (q31_t)0x767c4281,
+  (q31_t)0x7679e1ce, (q31_t)0x767780d2, (q31_t)0x76751f8d, (q31_t)0x7672bdfe, (q31_t)0x76705c27, (q31_t)0x766dfa07,
+    (q31_t)0x766b979d, (q31_t)0x766934eb,
+  (q31_t)0x7666d1ef, (q31_t)0x76646eab, (q31_t)0x76620b1d, (q31_t)0x765fa747, (q31_t)0x765d4327, (q31_t)0x765adebe,
+    (q31_t)0x76587a0d, (q31_t)0x76561512,
+  (q31_t)0x7653afce, (q31_t)0x76514a42, (q31_t)0x764ee46c, (q31_t)0x764c7e4d, (q31_t)0x764a17e6, (q31_t)0x7647b135,
+    (q31_t)0x76454a3c, (q31_t)0x7642e2f9,
+  (q31_t)0x76407b6e, (q31_t)0x763e139a, (q31_t)0x763bab7c, (q31_t)0x76394316, (q31_t)0x7636da67, (q31_t)0x7634716f,
+    (q31_t)0x7632082e, (q31_t)0x762f9ea4,
+  (q31_t)0x762d34d1, (q31_t)0x762acab6, (q31_t)0x76286051, (q31_t)0x7625f5a3, (q31_t)0x76238aad, (q31_t)0x76211f6e,
+    (q31_t)0x761eb3e6, (q31_t)0x761c4815,
+  (q31_t)0x7619dbfb, (q31_t)0x76176f98, (q31_t)0x761502ed, (q31_t)0x761295f9, (q31_t)0x761028bb, (q31_t)0x760dbb35,
+    (q31_t)0x760b4d67, (q31_t)0x7608df4f,
+  (q31_t)0x760670ee, (q31_t)0x76040245, (q31_t)0x76019353, (q31_t)0x75ff2418, (q31_t)0x75fcb495, (q31_t)0x75fa44c8,
+    (q31_t)0x75f7d4b3, (q31_t)0x75f56455,
+  (q31_t)0x75f2f3ae, (q31_t)0x75f082bf, (q31_t)0x75ee1187, (q31_t)0x75eba006, (q31_t)0x75e92e3c, (q31_t)0x75e6bc2a,
+    (q31_t)0x75e449ce, (q31_t)0x75e1d72b,
+  (q31_t)0x75df643e, (q31_t)0x75dcf109, (q31_t)0x75da7d8b, (q31_t)0x75d809c4, (q31_t)0x75d595b4, (q31_t)0x75d3215c,
+    (q31_t)0x75d0acbc, (q31_t)0x75ce37d2,
+  (q31_t)0x75cbc2a0, (q31_t)0x75c94d25, (q31_t)0x75c6d762, (q31_t)0x75c46156, (q31_t)0x75c1eb01, (q31_t)0x75bf7464,
+    (q31_t)0x75bcfd7e, (q31_t)0x75ba864f,
+  (q31_t)0x75b80ed8, (q31_t)0x75b59718, (q31_t)0x75b31f0f, (q31_t)0x75b0a6be, (q31_t)0x75ae2e25, (q31_t)0x75abb542,
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+  (q31_t)0x75a448e8, (q31_t)0x75a1cee4, (q31_t)0x759f5496, (q31_t)0x759cda01, (q31_t)0x759a5f22, (q31_t)0x7597e3fc,
+    (q31_t)0x7595688c, (q31_t)0x7592ecd4,
+  (q31_t)0x759070d4, (q31_t)0x758df48b, (q31_t)0x758b77fa, (q31_t)0x7588fb20, (q31_t)0x75867dfd, (q31_t)0x75840093,
+    (q31_t)0x758182df, (q31_t)0x757f04e3,
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+    (q31_t)0x756d8b13, (q31_t)0x756b0ad3,
+  (q31_t)0x75688a4b, (q31_t)0x7566097b, (q31_t)0x75638862, (q31_t)0x75610701, (q31_t)0x755e8557, (q31_t)0x755c0365,
+    (q31_t)0x7559812b, (q31_t)0x7556fea8,
+  (q31_t)0x75547bdd, (q31_t)0x7551f8c9, (q31_t)0x754f756e, (q31_t)0x754cf1c9, (q31_t)0x754a6ddd, (q31_t)0x7547e9a8,
+    (q31_t)0x7545652a, (q31_t)0x7542e065,
+  (q31_t)0x75405b57, (q31_t)0x753dd600, (q31_t)0x753b5061, (q31_t)0x7538ca7b, (q31_t)0x7536444b, (q31_t)0x7533bdd4,
+    (q31_t)0x75313714, (q31_t)0x752eb00c,
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+    (q31_t)0x751cf6eb, (q31_t)0x751a6da0,
+  (q31_t)0x7517e40e, (q31_t)0x75155a33, (q31_t)0x7512d010, (q31_t)0x751045a5, (q31_t)0x750dbaf2, (q31_t)0x750b2ff6,
+    (q31_t)0x7508a4b2, (q31_t)0x75061926,
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+  (q31_t)0x74ef248b, (q31_t)0x74ec962d, (q31_t)0x74ea0787, (q31_t)0x74e7789a, (q31_t)0x74e4e964, (q31_t)0x74e259e6,
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+    (q31_t)0x74cb41cc, (q31_t)0x74c8af7d,
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+    (q31_t)0x74786c7f, (q31_t)0x7475d132,
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+    (q31_t)0x74638a3d, (q31_t)0x7460ecb2,
+  (q31_t)0x745e4ede, (q31_t)0x745bb0c3, (q31_t)0x74591261, (q31_t)0x745673b6, (q31_t)0x7453d4c4, (q31_t)0x7451358a,
+    (q31_t)0x744e9608, (q31_t)0x744bf63e,
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+    (q31_t)0x74398fe3, (q31_t)0x7436eddc,
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+    (q31_t)0x742477d2, (q31_t)0x7421d38e,
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+    (q31_t)0x740f4dd8, (q31_t)0x740ca756,
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+    (q31_t)0x73fa11f8, (q31_t)0x73f7693a,
+  (q31_t)0x73f4c034, (q31_t)0x73f216e7, (q31_t)0x73ef6d53, (q31_t)0x73ecc377, (q31_t)0x73ea1953, (q31_t)0x73e76ee8,
+    (q31_t)0x73e4c435, (q31_t)0x73e2193b,
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+    (q31_t)0x73cf6493, (q31_t)0x73ccb75d,
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+    (q31_t)0x73b9f315, (q31_t)0x73b743a4,
+  (q31_t)0x73b493ec, (q31_t)0x73b1e3ec, (q31_t)0x73af33a5, (q31_t)0x73ac8316, (q31_t)0x73a9d240, (q31_t)0x73a72123,
+    (q31_t)0x73a46fbf, (q31_t)0x73a1be13,
+  (q31_t)0x739f0c20, (q31_t)0x739c59e5, (q31_t)0x7399a763, (q31_t)0x7396f49a, (q31_t)0x73944189, (q31_t)0x73918e32,
+    (q31_t)0x738eda93, (q31_t)0x738c26ac,
+  (q31_t)0x7389727f, (q31_t)0x7386be0a, (q31_t)0x7384094e, (q31_t)0x7381544a, (q31_t)0x737e9f00, (q31_t)0x737be96e,
+    (q31_t)0x73793395, (q31_t)0x73767d74,
+  (q31_t)0x7373c70d, (q31_t)0x7371105e, (q31_t)0x736e5968, (q31_t)0x736ba22b, (q31_t)0x7368eaa6, (q31_t)0x736632db,
+    (q31_t)0x73637ac8, (q31_t)0x7360c26e,
+  (q31_t)0x735e09cd, (q31_t)0x735b50e4, (q31_t)0x735897b5, (q31_t)0x7355de3e, (q31_t)0x73532481, (q31_t)0x73506a7c,
+    (q31_t)0x734db030, (q31_t)0x734af59d,
+  (q31_t)0x73483ac2, (q31_t)0x73457fa1, (q31_t)0x7342c438, (q31_t)0x73400889, (q31_t)0x733d4c92, (q31_t)0x733a9054,
+    (q31_t)0x7337d3d0, (q31_t)0x73351704,
+  (q31_t)0x733259f1, (q31_t)0x732f9c97, (q31_t)0x732cdef6, (q31_t)0x732a210d, (q31_t)0x732762de, (q31_t)0x7324a468,
+    (q31_t)0x7321e5ab, (q31_t)0x731f26a7,
+  (q31_t)0x731c675b, (q31_t)0x7319a7c9, (q31_t)0x7316e7f0, (q31_t)0x731427cf, (q31_t)0x73116768, (q31_t)0x730ea6ba,
+    (q31_t)0x730be5c5, (q31_t)0x73092489,
+  (q31_t)0x73066306, (q31_t)0x7303a13b, (q31_t)0x7300df2a, (q31_t)0x72fe1cd2, (q31_t)0x72fb5a34, (q31_t)0x72f8974e,
+    (q31_t)0x72f5d421, (q31_t)0x72f310ad,
+  (q31_t)0x72f04cf3, (q31_t)0x72ed88f1, (q31_t)0x72eac4a9, (q31_t)0x72e8001a, (q31_t)0x72e53b44, (q31_t)0x72e27627,
+    (q31_t)0x72dfb0c3, (q31_t)0x72dceb18,
+  (q31_t)0x72da2526, (q31_t)0x72d75eee, (q31_t)0x72d4986f, (q31_t)0x72d1d1a9, (q31_t)0x72cf0a9c, (q31_t)0x72cc4348,
+    (q31_t)0x72c97bad, (q31_t)0x72c6b3cc,
+  (q31_t)0x72c3eba4, (q31_t)0x72c12335, (q31_t)0x72be5a7f, (q31_t)0x72bb9183, (q31_t)0x72b8c83f, (q31_t)0x72b5feb5,
+    (q31_t)0x72b334e4, (q31_t)0x72b06acd,
+  (q31_t)0x72ada06f, (q31_t)0x72aad5c9, (q31_t)0x72a80ade, (q31_t)0x72a53fab, (q31_t)0x72a27432, (q31_t)0x729fa872,
+    (q31_t)0x729cdc6b, (q31_t)0x729a101e,
+  (q31_t)0x7297438a, (q31_t)0x729476af, (q31_t)0x7291a98e, (q31_t)0x728edc26, (q31_t)0x728c0e77, (q31_t)0x72894082,
+    (q31_t)0x72867245, (q31_t)0x7283a3c3,
+  (q31_t)0x7280d4f9, (q31_t)0x727e05e9, (q31_t)0x727b3693, (q31_t)0x727866f6, (q31_t)0x72759712, (q31_t)0x7272c6e7,
+    (q31_t)0x726ff676, (q31_t)0x726d25bf,
+  (q31_t)0x726a54c1, (q31_t)0x7267837c, (q31_t)0x7264b1f0, (q31_t)0x7261e01e, (q31_t)0x725f0e06, (q31_t)0x725c3ba7,
+    (q31_t)0x72596901, (q31_t)0x72569615,
+  (q31_t)0x7253c2e3, (q31_t)0x7250ef6a, (q31_t)0x724e1baa, (q31_t)0x724b47a4, (q31_t)0x72487357, (q31_t)0x72459ec4,
+    (q31_t)0x7242c9ea, (q31_t)0x723ff4ca,
+  (q31_t)0x723d1f63, (q31_t)0x723a49b6, (q31_t)0x723773c3, (q31_t)0x72349d89, (q31_t)0x7231c708, (q31_t)0x722ef041,
+    (q31_t)0x722c1934, (q31_t)0x722941e0,
+  (q31_t)0x72266a46, (q31_t)0x72239266, (q31_t)0x7220ba3f, (q31_t)0x721de1d1, (q31_t)0x721b091d, (q31_t)0x72183023,
+    (q31_t)0x721556e3, (q31_t)0x72127d5c,
+  (q31_t)0x720fa38e, (q31_t)0x720cc97b, (q31_t)0x7209ef21, (q31_t)0x72071480, (q31_t)0x7204399a, (q31_t)0x72015e6d,
+    (q31_t)0x71fe82f9, (q31_t)0x71fba740,
+  (q31_t)0x71f8cb40, (q31_t)0x71f5eefa, (q31_t)0x71f3126d, (q31_t)0x71f0359a, (q31_t)0x71ed5881, (q31_t)0x71ea7b22,
+    (q31_t)0x71e79d7c, (q31_t)0x71e4bf90,
+  (q31_t)0x71e1e15e, (q31_t)0x71df02e5, (q31_t)0x71dc2427, (q31_t)0x71d94522, (q31_t)0x71d665d6, (q31_t)0x71d38645,
+    (q31_t)0x71d0a66d, (q31_t)0x71cdc650,
+  (q31_t)0x71cae5ec, (q31_t)0x71c80542, (q31_t)0x71c52451, (q31_t)0x71c2431b, (q31_t)0x71bf619e, (q31_t)0x71bc7fdb,
+    (q31_t)0x71b99dd2, (q31_t)0x71b6bb83,
+  (q31_t)0x71b3d8ed, (q31_t)0x71b0f612, (q31_t)0x71ae12f0, (q31_t)0x71ab2f89, (q31_t)0x71a84bdb, (q31_t)0x71a567e7,
+    (q31_t)0x71a283ad, (q31_t)0x719f9f2c,
+  (q31_t)0x719cba66, (q31_t)0x7199d55a, (q31_t)0x7196f008, (q31_t)0x71940a6f, (q31_t)0x71912490, (q31_t)0x718e3e6c,
+    (q31_t)0x718b5801, (q31_t)0x71887151,
+  (q31_t)0x71858a5a, (q31_t)0x7182a31d, (q31_t)0x717fbb9a, (q31_t)0x717cd3d2, (q31_t)0x7179ebc3, (q31_t)0x7177036e,
+    (q31_t)0x71741ad3, (q31_t)0x717131f3,
+  (q31_t)0x716e48cc, (q31_t)0x716b5f5f, (q31_t)0x716875ad, (q31_t)0x71658bb4, (q31_t)0x7162a175, (q31_t)0x715fb6f1,
+    (q31_t)0x715ccc26, (q31_t)0x7159e116,
+  (q31_t)0x7156f5c0, (q31_t)0x71540a24, (q31_t)0x71511e42, (q31_t)0x714e321a, (q31_t)0x714b45ac, (q31_t)0x714858f8,
+    (q31_t)0x71456bfe, (q31_t)0x71427ebf,
+  (q31_t)0x713f9139, (q31_t)0x713ca36e, (q31_t)0x7139b55d, (q31_t)0x7136c706, (q31_t)0x7133d869, (q31_t)0x7130e987,
+    (q31_t)0x712dfa5e, (q31_t)0x712b0af0,
+  (q31_t)0x71281b3c, (q31_t)0x71252b42, (q31_t)0x71223b02, (q31_t)0x711f4a7d, (q31_t)0x711c59b2, (q31_t)0x711968a1,
+    (q31_t)0x7116774a, (q31_t)0x711385ad,
+  (q31_t)0x711093cb, (q31_t)0x710da1a3, (q31_t)0x710aaf35, (q31_t)0x7107bc82, (q31_t)0x7104c989, (q31_t)0x7101d64a,
+    (q31_t)0x70fee2c5, (q31_t)0x70fbeefb,
+  (q31_t)0x70f8faeb, (q31_t)0x70f60695, (q31_t)0x70f311fa, (q31_t)0x70f01d19, (q31_t)0x70ed27f2, (q31_t)0x70ea3286,
+    (q31_t)0x70e73cd4, (q31_t)0x70e446dc,
+  (q31_t)0x70e1509f, (q31_t)0x70de5a1c, (q31_t)0x70db6353, (q31_t)0x70d86c45, (q31_t)0x70d574f1, (q31_t)0x70d27d58,
+    (q31_t)0x70cf8579, (q31_t)0x70cc8d54,
+  (q31_t)0x70c994ea, (q31_t)0x70c69c3a, (q31_t)0x70c3a345, (q31_t)0x70c0aa0a, (q31_t)0x70bdb08a, (q31_t)0x70bab6c4,
+    (q31_t)0x70b7bcb8, (q31_t)0x70b4c267,
+  (q31_t)0x70b1c7d1, (q31_t)0x70aeccf5, (q31_t)0x70abd1d3, (q31_t)0x70a8d66c, (q31_t)0x70a5dac0, (q31_t)0x70a2dece,
+    (q31_t)0x709fe296, (q31_t)0x709ce619,
+  (q31_t)0x7099e957, (q31_t)0x7096ec4f, (q31_t)0x7093ef01, (q31_t)0x7090f16e, (q31_t)0x708df396, (q31_t)0x708af579,
+    (q31_t)0x7087f715, (q31_t)0x7084f86d,
+  (q31_t)0x7081f97f, (q31_t)0x707efa4c, (q31_t)0x707bfad3, (q31_t)0x7078fb15, (q31_t)0x7075fb11, (q31_t)0x7072fac9,
+    (q31_t)0x706ffa3a, (q31_t)0x706cf967,
+  (q31_t)0x7069f84e, (q31_t)0x7066f6f0, (q31_t)0x7063f54c, (q31_t)0x7060f363, (q31_t)0x705df135, (q31_t)0x705aeec1,
+    (q31_t)0x7057ec08, (q31_t)0x7054e90a,
+  (q31_t)0x7051e5c7, (q31_t)0x704ee23e, (q31_t)0x704bde70, (q31_t)0x7048da5d, (q31_t)0x7045d604, (q31_t)0x7042d166,
+    (q31_t)0x703fcc83, (q31_t)0x703cc75b,
+  (q31_t)0x7039c1ed, (q31_t)0x7036bc3b, (q31_t)0x7033b643, (q31_t)0x7030b005, (q31_t)0x702da983, (q31_t)0x702aa2bb,
+    (q31_t)0x70279baf, (q31_t)0x7024945d,
+  (q31_t)0x70218cc6, (q31_t)0x701e84e9, (q31_t)0x701b7cc8, (q31_t)0x70187461, (q31_t)0x70156bb5, (q31_t)0x701262c4,
+    (q31_t)0x700f598e, (q31_t)0x700c5013,
+  (q31_t)0x70094653, (q31_t)0x70063c4e, (q31_t)0x70033203, (q31_t)0x70002774, (q31_t)0x6ffd1c9f, (q31_t)0x6ffa1185,
+    (q31_t)0x6ff70626, (q31_t)0x6ff3fa82,
+  (q31_t)0x6ff0ee99, (q31_t)0x6fede26b, (q31_t)0x6fead5f8, (q31_t)0x6fe7c940, (q31_t)0x6fe4bc43, (q31_t)0x6fe1af01,
+    (q31_t)0x6fdea17a, (q31_t)0x6fdb93ae,
+  (q31_t)0x6fd8859d, (q31_t)0x6fd57746, (q31_t)0x6fd268ab, (q31_t)0x6fcf59cb, (q31_t)0x6fcc4aa6, (q31_t)0x6fc93b3c,
+    (q31_t)0x6fc62b8d, (q31_t)0x6fc31b99,
+  (q31_t)0x6fc00b60, (q31_t)0x6fbcfae2, (q31_t)0x6fb9ea20, (q31_t)0x6fb6d918, (q31_t)0x6fb3c7cb, (q31_t)0x6fb0b63a,
+    (q31_t)0x6fada464, (q31_t)0x6faa9248,
+  (q31_t)0x6fa77fe8, (q31_t)0x6fa46d43, (q31_t)0x6fa15a59, (q31_t)0x6f9e472b, (q31_t)0x6f9b33b7, (q31_t)0x6f981fff,
+    (q31_t)0x6f950c01, (q31_t)0x6f91f7bf,
+  (q31_t)0x6f8ee338, (q31_t)0x6f8bce6c, (q31_t)0x6f88b95c, (q31_t)0x6f85a407, (q31_t)0x6f828e6c, (q31_t)0x6f7f788d,
+    (q31_t)0x6f7c626a, (q31_t)0x6f794c01,
+  (q31_t)0x6f763554, (q31_t)0x6f731e62, (q31_t)0x6f70072b, (q31_t)0x6f6cefb0, (q31_t)0x6f69d7f0, (q31_t)0x6f66bfeb,
+    (q31_t)0x6f63a7a1, (q31_t)0x6f608f13,
+  (q31_t)0x6f5d7640, (q31_t)0x6f5a5d28, (q31_t)0x6f5743cb, (q31_t)0x6f542a2a, (q31_t)0x6f511044, (q31_t)0x6f4df61a,
+    (q31_t)0x6f4adbab, (q31_t)0x6f47c0f7,
+  (q31_t)0x6f44a5ff, (q31_t)0x6f418ac2, (q31_t)0x6f3e6f40, (q31_t)0x6f3b537a, (q31_t)0x6f38376f, (q31_t)0x6f351b1f,
+    (q31_t)0x6f31fe8b, (q31_t)0x6f2ee1b2,
+  (q31_t)0x6f2bc495, (q31_t)0x6f28a733, (q31_t)0x6f25898d, (q31_t)0x6f226ba2, (q31_t)0x6f1f4d72, (q31_t)0x6f1c2efe,
+    (q31_t)0x6f191045, (q31_t)0x6f15f148,
+  (q31_t)0x6f12d206, (q31_t)0x6f0fb280, (q31_t)0x6f0c92b6, (q31_t)0x6f0972a6, (q31_t)0x6f065253, (q31_t)0x6f0331ba,
+    (q31_t)0x6f0010de, (q31_t)0x6efcefbd,
+  (q31_t)0x6ef9ce57, (q31_t)0x6ef6acad, (q31_t)0x6ef38abe, (q31_t)0x6ef0688b, (q31_t)0x6eed4614, (q31_t)0x6eea2358,
+    (q31_t)0x6ee70058, (q31_t)0x6ee3dd13,
+  (q31_t)0x6ee0b98a, (q31_t)0x6edd95bd, (q31_t)0x6eda71ab, (q31_t)0x6ed74d55, (q31_t)0x6ed428ba, (q31_t)0x6ed103db,
+    (q31_t)0x6ecddeb8, (q31_t)0x6ecab950,
+  (q31_t)0x6ec793a4, (q31_t)0x6ec46db4, (q31_t)0x6ec1477f, (q31_t)0x6ebe2106, (q31_t)0x6ebafa49, (q31_t)0x6eb7d347,
+    (q31_t)0x6eb4ac02, (q31_t)0x6eb18477,
+  (q31_t)0x6eae5ca9, (q31_t)0x6eab3496, (q31_t)0x6ea80c3f, (q31_t)0x6ea4e3a4, (q31_t)0x6ea1bac4, (q31_t)0x6e9e91a1,
+    (q31_t)0x6e9b6839, (q31_t)0x6e983e8d,
+  (q31_t)0x6e95149c, (q31_t)0x6e91ea67, (q31_t)0x6e8ebfef, (q31_t)0x6e8b9532, (q31_t)0x6e886a30, (q31_t)0x6e853eeb,
+    (q31_t)0x6e821361, (q31_t)0x6e7ee794,
+  (q31_t)0x6e7bbb82, (q31_t)0x6e788f2c, (q31_t)0x6e756291, (q31_t)0x6e7235b3, (q31_t)0x6e6f0890, (q31_t)0x6e6bdb2a,
+    (q31_t)0x6e68ad7f, (q31_t)0x6e657f90,
+  (q31_t)0x6e62515d, (q31_t)0x6e5f22e6, (q31_t)0x6e5bf42b, (q31_t)0x6e58c52c, (q31_t)0x6e5595e9, (q31_t)0x6e526662,
+    (q31_t)0x6e4f3696, (q31_t)0x6e4c0687,
+  (q31_t)0x6e48d633, (q31_t)0x6e45a59c, (q31_t)0x6e4274c1, (q31_t)0x6e3f43a1, (q31_t)0x6e3c123e, (q31_t)0x6e38e096,
+    (q31_t)0x6e35aeab, (q31_t)0x6e327c7b,
+  (q31_t)0x6e2f4a08, (q31_t)0x6e2c1750, (q31_t)0x6e28e455, (q31_t)0x6e25b115, (q31_t)0x6e227d92, (q31_t)0x6e1f49cb,
+    (q31_t)0x6e1c15c0, (q31_t)0x6e18e171,
+  (q31_t)0x6e15acde, (q31_t)0x6e127807, (q31_t)0x6e0f42ec, (q31_t)0x6e0c0d8e, (q31_t)0x6e08d7eb, (q31_t)0x6e05a205,
+    (q31_t)0x6e026bda, (q31_t)0x6dff356c,
+  (q31_t)0x6dfbfeba, (q31_t)0x6df8c7c4, (q31_t)0x6df5908b, (q31_t)0x6df2590d, (q31_t)0x6def214c, (q31_t)0x6debe947,
+    (q31_t)0x6de8b0fe, (q31_t)0x6de57871,
+  (q31_t)0x6de23fa0, (q31_t)0x6ddf068c, (q31_t)0x6ddbcd34, (q31_t)0x6dd89398, (q31_t)0x6dd559b9, (q31_t)0x6dd21f95,
+    (q31_t)0x6dcee52e, (q31_t)0x6dcbaa83,
+  (q31_t)0x6dc86f95, (q31_t)0x6dc53462, (q31_t)0x6dc1f8ec, (q31_t)0x6dbebd33, (q31_t)0x6dbb8135, (q31_t)0x6db844f4,
+    (q31_t)0x6db5086f, (q31_t)0x6db1cba7,
+  (q31_t)0x6dae8e9b, (q31_t)0x6dab514b, (q31_t)0x6da813b8, (q31_t)0x6da4d5e1, (q31_t)0x6da197c6, (q31_t)0x6d9e5968,
+    (q31_t)0x6d9b1ac6, (q31_t)0x6d97dbe0,
+  (q31_t)0x6d949cb7, (q31_t)0x6d915d4a, (q31_t)0x6d8e1d9a, (q31_t)0x6d8adda6, (q31_t)0x6d879d6e, (q31_t)0x6d845cf3,
+    (q31_t)0x6d811c35, (q31_t)0x6d7ddb33,
+  (q31_t)0x6d7a99ed, (q31_t)0x6d775864, (q31_t)0x6d741697, (q31_t)0x6d70d487, (q31_t)0x6d6d9233, (q31_t)0x6d6a4f9c,
+    (q31_t)0x6d670cc1, (q31_t)0x6d63c9a3,
+  (q31_t)0x6d608641, (q31_t)0x6d5d429c, (q31_t)0x6d59feb3, (q31_t)0x6d56ba87, (q31_t)0x6d537617, (q31_t)0x6d503164,
+    (q31_t)0x6d4cec6e, (q31_t)0x6d49a734,
+  (q31_t)0x6d4661b7, (q31_t)0x6d431bf6, (q31_t)0x6d3fd5f2, (q31_t)0x6d3c8fab, (q31_t)0x6d394920, (q31_t)0x6d360252,
+    (q31_t)0x6d32bb40, (q31_t)0x6d2f73eb,
+  (q31_t)0x6d2c2c53, (q31_t)0x6d28e477, (q31_t)0x6d259c58, (q31_t)0x6d2253f6, (q31_t)0x6d1f0b50, (q31_t)0x6d1bc267,
+    (q31_t)0x6d18793b, (q31_t)0x6d152fcc,
+  (q31_t)0x6d11e619, (q31_t)0x6d0e9c23, (q31_t)0x6d0b51e9, (q31_t)0x6d08076d, (q31_t)0x6d04bcad, (q31_t)0x6d0171aa,
+    (q31_t)0x6cfe2663, (q31_t)0x6cfadada,
+  (q31_t)0x6cf78f0d, (q31_t)0x6cf442fd, (q31_t)0x6cf0f6aa, (q31_t)0x6cedaa13, (q31_t)0x6cea5d3a, (q31_t)0x6ce7101d,
+    (q31_t)0x6ce3c2bd, (q31_t)0x6ce0751a,
+  (q31_t)0x6cdd2733, (q31_t)0x6cd9d90a, (q31_t)0x6cd68a9d, (q31_t)0x6cd33bed, (q31_t)0x6ccfecfa, (q31_t)0x6ccc9dc4,
+    (q31_t)0x6cc94e4b, (q31_t)0x6cc5fe8f,
+  (q31_t)0x6cc2ae90, (q31_t)0x6cbf5e4d, (q31_t)0x6cbc0dc8, (q31_t)0x6cb8bcff, (q31_t)0x6cb56bf4, (q31_t)0x6cb21aa5,
+    (q31_t)0x6caec913, (q31_t)0x6cab773e,
+  (q31_t)0x6ca82527, (q31_t)0x6ca4d2cc, (q31_t)0x6ca1802e, (q31_t)0x6c9e2d4d, (q31_t)0x6c9ada29, (q31_t)0x6c9786c2,
+    (q31_t)0x6c943318, (q31_t)0x6c90df2c,
+  (q31_t)0x6c8d8afc, (q31_t)0x6c8a3689, (q31_t)0x6c86e1d3, (q31_t)0x6c838cdb, (q31_t)0x6c80379f, (q31_t)0x6c7ce220,
+    (q31_t)0x6c798c5f, (q31_t)0x6c76365b,
+  (q31_t)0x6c72e013, (q31_t)0x6c6f8989, (q31_t)0x6c6c32bc, (q31_t)0x6c68dbac, (q31_t)0x6c658459, (q31_t)0x6c622cc4,
+    (q31_t)0x6c5ed4eb, (q31_t)0x6c5b7cd0,
+  (q31_t)0x6c582472, (q31_t)0x6c54cbd1, (q31_t)0x6c5172ed, (q31_t)0x6c4e19c6, (q31_t)0x6c4ac05d, (q31_t)0x6c4766b0,
+    (q31_t)0x6c440cc1, (q31_t)0x6c40b28f,
+  (q31_t)0x6c3d581b, (q31_t)0x6c39fd63, (q31_t)0x6c36a269, (q31_t)0x6c33472c, (q31_t)0x6c2febad, (q31_t)0x6c2c8fea,
+    (q31_t)0x6c2933e5, (q31_t)0x6c25d79d,
+  (q31_t)0x6c227b13, (q31_t)0x6c1f1e45, (q31_t)0x6c1bc136, (q31_t)0x6c1863e3, (q31_t)0x6c15064e, (q31_t)0x6c11a876,
+    (q31_t)0x6c0e4a5b, (q31_t)0x6c0aebfe,
+  (q31_t)0x6c078d5e, (q31_t)0x6c042e7b, (q31_t)0x6c00cf56, (q31_t)0x6bfd6fee, (q31_t)0x6bfa1044, (q31_t)0x6bf6b056,
+    (q31_t)0x6bf35027, (q31_t)0x6befefb5,
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+  (q31_t)0x644b3375, (q31_t)0x64474bec, (q31_t)0x64436425, (q31_t)0x643f7c20, (q31_t)0x643b93dd, (q31_t)0x6437ab5d,
+    (q31_t)0x6433c29f, (q31_t)0x642fd9a3,
+  (q31_t)0x642bf069, (q31_t)0x642806f1, (q31_t)0x64241d3c, (q31_t)0x64203348, (q31_t)0x641c4917, (q31_t)0x64185ea9,
+    (q31_t)0x641473fc, (q31_t)0x64108912,
+  (q31_t)0x640c9dea, (q31_t)0x6408b284, (q31_t)0x6404c6e1, (q31_t)0x6400db00, (q31_t)0x63fceee1, (q31_t)0x63f90285,
+    (q31_t)0x63f515eb, (q31_t)0x63f12913,
+  (q31_t)0x63ed3bfd, (q31_t)0x63e94eaa, (q31_t)0x63e5611a, (q31_t)0x63e1734b, (q31_t)0x63dd853f, (q31_t)0x63d996f6,
+    (q31_t)0x63d5a86f, (q31_t)0x63d1b9aa,
+  (q31_t)0x63cdcaa8, (q31_t)0x63c9db68, (q31_t)0x63c5ebeb, (q31_t)0x63c1fc30, (q31_t)0x63be0c37, (q31_t)0x63ba1c01,
+    (q31_t)0x63b62b8e, (q31_t)0x63b23add,
+  (q31_t)0x63ae49ee, (q31_t)0x63aa58c2, (q31_t)0x63a66759, (q31_t)0x63a275b2, (q31_t)0x639e83cd, (q31_t)0x639a91ac,
+    (q31_t)0x63969f4c, (q31_t)0x6392acaf,
+  (q31_t)0x638eb9d5, (q31_t)0x638ac6be, (q31_t)0x6386d369, (q31_t)0x6382dfd6, (q31_t)0x637eec07, (q31_t)0x637af7fa,
+    (q31_t)0x637703af, (q31_t)0x63730f27,
+  (q31_t)0x636f1a62, (q31_t)0x636b2560, (q31_t)0x63673020, (q31_t)0x63633aa3, (q31_t)0x635f44e8, (q31_t)0x635b4ef0,
+    (q31_t)0x635758bb, (q31_t)0x63536249,
+  (q31_t)0x634f6b99, (q31_t)0x634b74ad, (q31_t)0x63477d82, (q31_t)0x6343861b, (q31_t)0x633f8e76, (q31_t)0x633b9695,
+    (q31_t)0x63379e76, (q31_t)0x6333a619,
+  (q31_t)0x632fad80, (q31_t)0x632bb4a9, (q31_t)0x6327bb96, (q31_t)0x6323c245, (q31_t)0x631fc8b7, (q31_t)0x631bceeb,
+    (q31_t)0x6317d4e3, (q31_t)0x6313da9e,
+  (q31_t)0x630fe01b, (q31_t)0x630be55b, (q31_t)0x6307ea5e, (q31_t)0x6303ef25, (q31_t)0x62fff3ae, (q31_t)0x62fbf7fa,
+    (q31_t)0x62f7fc08, (q31_t)0x62f3ffda,
+  (q31_t)0x62f0036f, (q31_t)0x62ec06c7, (q31_t)0x62e809e2, (q31_t)0x62e40cbf, (q31_t)0x62e00f60, (q31_t)0x62dc11c4,
+    (q31_t)0x62d813eb, (q31_t)0x62d415d4,
+  (q31_t)0x62d01781, (q31_t)0x62cc18f1, (q31_t)0x62c81a24, (q31_t)0x62c41b1a, (q31_t)0x62c01bd3, (q31_t)0x62bc1c4f,
+    (q31_t)0x62b81c8f, (q31_t)0x62b41c91,
+  (q31_t)0x62b01c57, (q31_t)0x62ac1bdf, (q31_t)0x62a81b2b, (q31_t)0x62a41a3a, (q31_t)0x62a0190c, (q31_t)0x629c17a1,
+    (q31_t)0x629815fa, (q31_t)0x62941415,
+  (q31_t)0x629011f4, (q31_t)0x628c0f96, (q31_t)0x62880cfb, (q31_t)0x62840a23, (q31_t)0x6280070f, (q31_t)0x627c03be,
+    (q31_t)0x62780030, (q31_t)0x6273fc65,
+  (q31_t)0x626ff85e, (q31_t)0x626bf41a, (q31_t)0x6267ef99, (q31_t)0x6263eadc, (q31_t)0x625fe5e1, (q31_t)0x625be0ab,
+    (q31_t)0x6257db37, (q31_t)0x6253d587,
+  (q31_t)0x624fcf9a, (q31_t)0x624bc970, (q31_t)0x6247c30a, (q31_t)0x6243bc68, (q31_t)0x623fb588, (q31_t)0x623bae6c,
+    (q31_t)0x6237a714, (q31_t)0x62339f7e,
+  (q31_t)0x622f97ad, (q31_t)0x622b8f9e, (q31_t)0x62278754, (q31_t)0x62237ecc, (q31_t)0x621f7608, (q31_t)0x621b6d08,
+    (q31_t)0x621763cb, (q31_t)0x62135a51,
+  (q31_t)0x620f509b, (q31_t)0x620b46a9, (q31_t)0x62073c7a, (q31_t)0x6203320e, (q31_t)0x61ff2766, (q31_t)0x61fb1c82,
+    (q31_t)0x61f71161, (q31_t)0x61f30604,
+  (q31_t)0x61eefa6b, (q31_t)0x61eaee95, (q31_t)0x61e6e282, (q31_t)0x61e2d633, (q31_t)0x61dec9a8, (q31_t)0x61dabce0,
+    (q31_t)0x61d6afdd, (q31_t)0x61d2a29c,
+  (q31_t)0x61ce9520, (q31_t)0x61ca8767, (q31_t)0x61c67971, (q31_t)0x61c26b40, (q31_t)0x61be5cd2, (q31_t)0x61ba4e28,
+    (q31_t)0x61b63f41, (q31_t)0x61b2301e,
+  (q31_t)0x61ae20bf, (q31_t)0x61aa1124, (q31_t)0x61a6014d, (q31_t)0x61a1f139, (q31_t)0x619de0e9, (q31_t)0x6199d05d,
+    (q31_t)0x6195bf94, (q31_t)0x6191ae90,
+  (q31_t)0x618d9d4f, (q31_t)0x61898bd2, (q31_t)0x61857a19, (q31_t)0x61816824, (q31_t)0x617d55f2, (q31_t)0x61794385,
+    (q31_t)0x617530db, (q31_t)0x61711df5,
+  (q31_t)0x616d0ad3, (q31_t)0x6168f775, (q31_t)0x6164e3db, (q31_t)0x6160d005, (q31_t)0x615cbbf3, (q31_t)0x6158a7a4,
+    (q31_t)0x6154931a, (q31_t)0x61507e54,
+  (q31_t)0x614c6951, (q31_t)0x61485413, (q31_t)0x61443e98, (q31_t)0x614028e2, (q31_t)0x613c12f0, (q31_t)0x6137fcc1,
+    (q31_t)0x6133e657, (q31_t)0x612fcfb0,
+  (q31_t)0x612bb8ce, (q31_t)0x6127a1b0, (q31_t)0x61238a56, (q31_t)0x611f72c0, (q31_t)0x611b5aee, (q31_t)0x611742e0,
+    (q31_t)0x61132a96, (q31_t)0x610f1210,
+  (q31_t)0x610af94f, (q31_t)0x6106e051, (q31_t)0x6102c718, (q31_t)0x60feada3, (q31_t)0x60fa93f2, (q31_t)0x60f67a05,
+    (q31_t)0x60f25fdd, (q31_t)0x60ee4579,
+  (q31_t)0x60ea2ad8, (q31_t)0x60e60ffd, (q31_t)0x60e1f4e5, (q31_t)0x60ddd991, (q31_t)0x60d9be02, (q31_t)0x60d5a237,
+    (q31_t)0x60d18631, (q31_t)0x60cd69ee,
+  (q31_t)0x60c94d70, (q31_t)0x60c530b6, (q31_t)0x60c113c1, (q31_t)0x60bcf690, (q31_t)0x60b8d923, (q31_t)0x60b4bb7a,
+    (q31_t)0x60b09d96, (q31_t)0x60ac7f76,
+  (q31_t)0x60a8611b, (q31_t)0x60a44284, (q31_t)0x60a023b1, (q31_t)0x609c04a3, (q31_t)0x6097e559, (q31_t)0x6093c5d3,
+    (q31_t)0x608fa612, (q31_t)0x608b8616,
+  (q31_t)0x608765dd, (q31_t)0x6083456a, (q31_t)0x607f24ba, (q31_t)0x607b03d0, (q31_t)0x6076e2a9, (q31_t)0x6072c148,
+    (q31_t)0x606e9faa, (q31_t)0x606a7dd2,
+  (q31_t)0x60665bbd, (q31_t)0x6062396e, (q31_t)0x605e16e2, (q31_t)0x6059f41c, (q31_t)0x6055d11a, (q31_t)0x6051addc,
+    (q31_t)0x604d8a63, (q31_t)0x604966af,
+  (q31_t)0x604542bf, (q31_t)0x60411e94, (q31_t)0x603cfa2e, (q31_t)0x6038d58c, (q31_t)0x6034b0af, (q31_t)0x60308b97,
+    (q31_t)0x602c6643, (q31_t)0x602840b4,
+  (q31_t)0x60241ae9, (q31_t)0x601ff4e3, (q31_t)0x601bcea2, (q31_t)0x6017a826, (q31_t)0x6013816e, (q31_t)0x600f5a7b,
+    (q31_t)0x600b334d, (q31_t)0x60070be4,
+  (q31_t)0x6002e43f, (q31_t)0x5ffebc5f, (q31_t)0x5ffa9444, (q31_t)0x5ff66bee, (q31_t)0x5ff2435d, (q31_t)0x5fee1a90,
+    (q31_t)0x5fe9f188, (q31_t)0x5fe5c845,
+  (q31_t)0x5fe19ec7, (q31_t)0x5fdd750e, (q31_t)0x5fd94b19, (q31_t)0x5fd520ea, (q31_t)0x5fd0f67f, (q31_t)0x5fcccbd9,
+    (q31_t)0x5fc8a0f8, (q31_t)0x5fc475dc,
+  (q31_t)0x5fc04a85, (q31_t)0x5fbc1ef3, (q31_t)0x5fb7f326, (q31_t)0x5fb3c71e, (q31_t)0x5faf9adb, (q31_t)0x5fab6e5d,
+    (q31_t)0x5fa741a3, (q31_t)0x5fa314af,
+  (q31_t)0x5f9ee780, (q31_t)0x5f9aba16, (q31_t)0x5f968c70, (q31_t)0x5f925e90, (q31_t)0x5f8e3075, (q31_t)0x5f8a021f,
+    (q31_t)0x5f85d38e, (q31_t)0x5f81a4c2,
+  (q31_t)0x5f7d75bb, (q31_t)0x5f794679, (q31_t)0x5f7516fd, (q31_t)0x5f70e745, (q31_t)0x5f6cb753, (q31_t)0x5f688726,
+    (q31_t)0x5f6456be, (q31_t)0x5f60261b,
+  (q31_t)0x5f5bf53d, (q31_t)0x5f57c424, (q31_t)0x5f5392d1, (q31_t)0x5f4f6143, (q31_t)0x5f4b2f7a, (q31_t)0x5f46fd76,
+    (q31_t)0x5f42cb37, (q31_t)0x5f3e98be,
+  (q31_t)0x5f3a660a, (q31_t)0x5f36331b, (q31_t)0x5f31fff1, (q31_t)0x5f2dcc8d, (q31_t)0x5f2998ee, (q31_t)0x5f256515,
+    (q31_t)0x5f213100, (q31_t)0x5f1cfcb1,
+  (q31_t)0x5f18c827, (q31_t)0x5f149363, (q31_t)0x5f105e64, (q31_t)0x5f0c292a, (q31_t)0x5f07f3b6, (q31_t)0x5f03be07,
+    (q31_t)0x5eff881d, (q31_t)0x5efb51f9,
+  (q31_t)0x5ef71b9b, (q31_t)0x5ef2e501, (q31_t)0x5eeeae2d, (q31_t)0x5eea771f, (q31_t)0x5ee63fd6, (q31_t)0x5ee20853,
+    (q31_t)0x5eddd094, (q31_t)0x5ed9989c,
+  (q31_t)0x5ed56069, (q31_t)0x5ed127fb, (q31_t)0x5eccef53, (q31_t)0x5ec8b671, (q31_t)0x5ec47d54, (q31_t)0x5ec043fc,
+    (q31_t)0x5ebc0a6a, (q31_t)0x5eb7d09e,
+  (q31_t)0x5eb39697, (q31_t)0x5eaf5c56, (q31_t)0x5eab21da, (q31_t)0x5ea6e724, (q31_t)0x5ea2ac34, (q31_t)0x5e9e7109,
+    (q31_t)0x5e9a35a4, (q31_t)0x5e95fa05,
+  (q31_t)0x5e91be2b, (q31_t)0x5e8d8217, (q31_t)0x5e8945c8, (q31_t)0x5e85093f, (q31_t)0x5e80cc7c, (q31_t)0x5e7c8f7f,
+    (q31_t)0x5e785247, (q31_t)0x5e7414d5,
+  (q31_t)0x5e6fd729, (q31_t)0x5e6b9943, (q31_t)0x5e675b22, (q31_t)0x5e631cc7, (q31_t)0x5e5ede32, (q31_t)0x5e5a9f62,
+    (q31_t)0x5e566059, (q31_t)0x5e522115,
+  (q31_t)0x5e4de197, (q31_t)0x5e49a1df, (q31_t)0x5e4561ed, (q31_t)0x5e4121c0, (q31_t)0x5e3ce15a, (q31_t)0x5e38a0b9,
+    (q31_t)0x5e345fde, (q31_t)0x5e301ec9,
+  (q31_t)0x5e2bdd7a, (q31_t)0x5e279bf1, (q31_t)0x5e235a2e, (q31_t)0x5e1f1830, (q31_t)0x5e1ad5f9, (q31_t)0x5e169388,
+    (q31_t)0x5e1250dc, (q31_t)0x5e0e0df7,
+  (q31_t)0x5e09cad7, (q31_t)0x5e05877e, (q31_t)0x5e0143ea, (q31_t)0x5dfd001d, (q31_t)0x5df8bc15, (q31_t)0x5df477d4,
+    (q31_t)0x5df03359, (q31_t)0x5debeea3,
+  (q31_t)0x5de7a9b4, (q31_t)0x5de3648b, (q31_t)0x5ddf1f28, (q31_t)0x5ddad98b, (q31_t)0x5dd693b4, (q31_t)0x5dd24da3,
+    (q31_t)0x5dce0759, (q31_t)0x5dc9c0d4,
+  (q31_t)0x5dc57a16, (q31_t)0x5dc1331d, (q31_t)0x5dbcebeb, (q31_t)0x5db8a480, (q31_t)0x5db45cda, (q31_t)0x5db014fa,
+    (q31_t)0x5dabcce1, (q31_t)0x5da7848e,
+  (q31_t)0x5da33c01, (q31_t)0x5d9ef33b, (q31_t)0x5d9aaa3a, (q31_t)0x5d966100, (q31_t)0x5d92178d, (q31_t)0x5d8dcddf,
+    (q31_t)0x5d8983f8, (q31_t)0x5d8539d7,
+  (q31_t)0x5d80ef7c, (q31_t)0x5d7ca4e8, (q31_t)0x5d785a1a, (q31_t)0x5d740f12, (q31_t)0x5d6fc3d1, (q31_t)0x5d6b7856,
+    (q31_t)0x5d672ca2, (q31_t)0x5d62e0b4,
+  (q31_t)0x5d5e948c, (q31_t)0x5d5a482a, (q31_t)0x5d55fb90, (q31_t)0x5d51aebb, (q31_t)0x5d4d61ad, (q31_t)0x5d491465,
+    (q31_t)0x5d44c6e4, (q31_t)0x5d40792a,
+  (q31_t)0x5d3c2b35, (q31_t)0x5d37dd08, (q31_t)0x5d338ea0, (q31_t)0x5d2f4000, (q31_t)0x5d2af125, (q31_t)0x5d26a212,
+    (q31_t)0x5d2252c5, (q31_t)0x5d1e033e,
+  (q31_t)0x5d19b37e, (q31_t)0x5d156385, (q31_t)0x5d111352, (q31_t)0x5d0cc2e5, (q31_t)0x5d087240, (q31_t)0x5d042161,
+    (q31_t)0x5cffd048, (q31_t)0x5cfb7ef7,
+  (q31_t)0x5cf72d6b, (q31_t)0x5cf2dba7, (q31_t)0x5cee89a9, (q31_t)0x5cea3772, (q31_t)0x5ce5e501, (q31_t)0x5ce19258,
+    (q31_t)0x5cdd3f75, (q31_t)0x5cd8ec58,
+  (q31_t)0x5cd49903, (q31_t)0x5cd04574, (q31_t)0x5ccbf1ab, (q31_t)0x5cc79daa, (q31_t)0x5cc3496f, (q31_t)0x5cbef4fc,
+    (q31_t)0x5cbaa04f, (q31_t)0x5cb64b68,
+  (q31_t)0x5cb1f649, (q31_t)0x5cada0f0, (q31_t)0x5ca94b5e, (q31_t)0x5ca4f594, (q31_t)0x5ca09f8f, (q31_t)0x5c9c4952,
+    (q31_t)0x5c97f2dc, (q31_t)0x5c939c2c,
+  (q31_t)0x5c8f4544, (q31_t)0x5c8aee22, (q31_t)0x5c8696c7, (q31_t)0x5c823f34, (q31_t)0x5c7de767, (q31_t)0x5c798f61,
+    (q31_t)0x5c753722, (q31_t)0x5c70deaa,
+  (q31_t)0x5c6c85f9, (q31_t)0x5c682d0f, (q31_t)0x5c63d3eb, (q31_t)0x5c5f7a8f, (q31_t)0x5c5b20fa, (q31_t)0x5c56c72c,
+    (q31_t)0x5c526d25, (q31_t)0x5c4e12e5,
+  (q31_t)0x5c49b86d, (q31_t)0x5c455dbb, (q31_t)0x5c4102d0, (q31_t)0x5c3ca7ad, (q31_t)0x5c384c50, (q31_t)0x5c33f0bb,
+    (q31_t)0x5c2f94ec, (q31_t)0x5c2b38e5,
+  (q31_t)0x5c26dca5, (q31_t)0x5c22802c, (q31_t)0x5c1e237b, (q31_t)0x5c19c690, (q31_t)0x5c15696d, (q31_t)0x5c110c11,
+    (q31_t)0x5c0cae7c, (q31_t)0x5c0850ae,
+  (q31_t)0x5c03f2a8, (q31_t)0x5bff9469, (q31_t)0x5bfb35f1, (q31_t)0x5bf6d740, (q31_t)0x5bf27857, (q31_t)0x5bee1935,
+    (q31_t)0x5be9b9da, (q31_t)0x5be55a46,
+  (q31_t)0x5be0fa7a, (q31_t)0x5bdc9a75, (q31_t)0x5bd83a37, (q31_t)0x5bd3d9c1, (q31_t)0x5bcf7912, (q31_t)0x5bcb182b,
+    (q31_t)0x5bc6b70b, (q31_t)0x5bc255b2,
+  (q31_t)0x5bbdf421, (q31_t)0x5bb99257, (q31_t)0x5bb53054, (q31_t)0x5bb0ce19, (q31_t)0x5bac6ba6, (q31_t)0x5ba808f9,
+    (q31_t)0x5ba3a615, (q31_t)0x5b9f42f7,
+  (q31_t)0x5b9adfa2, (q31_t)0x5b967c13, (q31_t)0x5b92184d, (q31_t)0x5b8db44d, (q31_t)0x5b895016, (q31_t)0x5b84eba6,
+    (q31_t)0x5b8086fd, (q31_t)0x5b7c221c,
+  (q31_t)0x5b77bd02, (q31_t)0x5b7357b0, (q31_t)0x5b6ef226, (q31_t)0x5b6a8c63, (q31_t)0x5b662668, (q31_t)0x5b61c035,
+    (q31_t)0x5b5d59c9, (q31_t)0x5b58f324,
+  (q31_t)0x5b548c48, (q31_t)0x5b502533, (q31_t)0x5b4bbde6, (q31_t)0x5b475660, (q31_t)0x5b42eea2, (q31_t)0x5b3e86ac,
+    (q31_t)0x5b3a1e7e, (q31_t)0x5b35b617,
+  (q31_t)0x5b314d78, (q31_t)0x5b2ce4a1, (q31_t)0x5b287b91, (q31_t)0x5b241249, (q31_t)0x5b1fa8c9, (q31_t)0x5b1b3f11,
+    (q31_t)0x5b16d521, (q31_t)0x5b126af8,
+  (q31_t)0x5b0e0098, (q31_t)0x5b0995ff, (q31_t)0x5b052b2e, (q31_t)0x5b00c025, (q31_t)0x5afc54e3, (q31_t)0x5af7e96a,
+    (q31_t)0x5af37db8, (q31_t)0x5aef11cf,
+  (q31_t)0x5aeaa5ad, (q31_t)0x5ae63953, (q31_t)0x5ae1ccc1, (q31_t)0x5add5ff7, (q31_t)0x5ad8f2f5, (q31_t)0x5ad485bb,
+    (q31_t)0x5ad01849, (q31_t)0x5acbaa9f,
+  (q31_t)0x5ac73cbd, (q31_t)0x5ac2cea3, (q31_t)0x5abe6050, (q31_t)0x5ab9f1c6, (q31_t)0x5ab58304, (q31_t)0x5ab1140a,
+    (q31_t)0x5aaca4d8, (q31_t)0x5aa8356f,
+  (q31_t)0x5aa3c5cd, (q31_t)0x5a9f55f3, (q31_t)0x5a9ae5e2, (q31_t)0x5a967598, (q31_t)0x5a920517, (q31_t)0x5a8d945d,
+    (q31_t)0x5a89236c, (q31_t)0x5a84b243,
+  (q31_t)0x5a8040e3, (q31_t)0x5a7bcf4a, (q31_t)0x5a775d7a, (q31_t)0x5a72eb71, (q31_t)0x5a6e7931, (q31_t)0x5a6a06ba,
+    (q31_t)0x5a65940a, (q31_t)0x5a612123,
+  (q31_t)0x5a5cae04, (q31_t)0x5a583aad, (q31_t)0x5a53c71e, (q31_t)0x5a4f5358, (q31_t)0x5a4adf5a, (q31_t)0x5a466b24,
+    (q31_t)0x5a41f6b7, (q31_t)0x5a3d8212,
+  (q31_t)0x5a390d35, (q31_t)0x5a349821, (q31_t)0x5a3022d5, (q31_t)0x5a2bad51, (q31_t)0x5a273796, (q31_t)0x5a22c1a3,
+    (q31_t)0x5a1e4b79, (q31_t)0x5a19d517,
+  (q31_t)0x5a155e7d, (q31_t)0x5a10e7ac, (q31_t)0x5a0c70a3, (q31_t)0x5a07f963, (q31_t)0x5a0381eb, (q31_t)0x59ff0a3c,
+    (q31_t)0x59fa9255, (q31_t)0x59f61a36,
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+    (q31_t)0x59d6cb50, (q31_t)0x59d25176,
+  (q31_t)0x59cdd765, (q31_t)0x59c95d1c, (q31_t)0x59c4e29c, (q31_t)0x59c067e4, (q31_t)0x59bbecf5, (q31_t)0x59b771cf,
+    (q31_t)0x59b2f671, (q31_t)0x59ae7add,
+  (q31_t)0x59a9ff10, (q31_t)0x59a5830d, (q31_t)0x59a106d2, (q31_t)0x599c8a60, (q31_t)0x59980db6, (q31_t)0x599390d5,
+    (q31_t)0x598f13bd, (q31_t)0x598a966e,
+  (q31_t)0x598618e8, (q31_t)0x59819b2a, (q31_t)0x597d1d35, (q31_t)0x59789f09, (q31_t)0x597420a6, (q31_t)0x596fa20b,
+    (q31_t)0x596b233a, (q31_t)0x5966a431,
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+    (q31_t)0x594724ec, (q31_t)0x5942a42a,
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+    (q31_t)0x592318d9, (q31_t)0x591e9660,
+  (q31_t)0x591a13af, (q31_t)0x591590c7, (q31_t)0x59110da8, (q31_t)0x590c8a53, (q31_t)0x590806c6, (q31_t)0x59038302,
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+    (q31_t)0x58dad77d, (q31_t)0x58d65195,
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+    (q31_t)0x58b6a23e, (q31_t)0x58b21aa0,
+  (q31_t)0x58ad92cb, (q31_t)0x58a90ac0, (q31_t)0x58a4827d, (q31_t)0x589ffa04, (q31_t)0x589b7155, (q31_t)0x5896e86f,
+    (q31_t)0x58925f52, (q31_t)0x588dd5fe,
+  (q31_t)0x58894c74, (q31_t)0x5884c2b3, (q31_t)0x588038bb, (q31_t)0x587bae8d, (q31_t)0x58772429, (q31_t)0x5872998e,
+    (q31_t)0x586e0ebc, (q31_t)0x586983b4,
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+    (q31_t)0x582544ad, (q31_t)0x5820b63e,
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+  (q31_t)0x57f7aac5, (q31_t)0x57f31a36, (q31_t)0x57ee8971, (q31_t)0x57e9f876, (q31_t)0x57e56744, (q31_t)0x57e0d5dd,
+    (q31_t)0x57dc443f, (q31_t)0x57d7b26b,
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+    (q31_t)0x57b7afb2, (q31_t)0x57b31c2d,
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+    (q31_t)0x5724d672, (q31_t)0x57203c2f,
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+    (q31_t)0x5691262d, (q31_t)0x568c8538,
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+    (q31_t)0x5646fddb, (q31_t)0x56425991,
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+    (q31_t)0x55d75da4, (q31_t)0x55d2b460,
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+    (q31_t)0x5541cecc, (q31_t)0x553d1ef0,
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+    (q31_t)0x551c4a29, (q31_t)0x551798a8,
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+    (q31_t)0x54d11989, (q31_t)0x54cc64c2,
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+    (q31_t)0x54ab6d97, (q31_t)0x54a6b72e,
+  (q31_t)0x54a20090, (q31_t)0x549d49bf, (q31_t)0x549892b9, (q31_t)0x5493db7f, (q31_t)0x548f2410, (q31_t)0x548a6c6e,
+    (q31_t)0x5485b497, (q31_t)0x5480fc8c,
+  (q31_t)0x547c444d, (q31_t)0x54778bda, (q31_t)0x5472d333, (q31_t)0x546e1a58, (q31_t)0x54696149, (q31_t)0x5464a805,
+    (q31_t)0x545fee8e, (q31_t)0x545b34e3,
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+    (q31_t)0x543a1b82, (q31_t)0x54356037,
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+    (q31_t)0x54143b79, (q31_t)0x540f7e8e,
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+    (q31_t)0x53ee4e78, (q31_t)0x53e98fef,
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+    (q31_t)0x53c85486, (q31_t)0x53c3945f,
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+    (q31_t)0x53a24da9, (q31_t)0x539d8be5,
+  (q31_t)0x5398c9ed, (q31_t)0x539407c2, (q31_t)0x538f4564, (q31_t)0x538a82d1, (q31_t)0x5385c00c, (q31_t)0x5380fd12,
+    (q31_t)0x537c39e6, (q31_t)0x53777685,
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+    (q31_t)0x53561942, (q31_t)0x53515447,
+  (q31_t)0x534c8f17, (q31_t)0x5347c9b5, (q31_t)0x5343041f, (q31_t)0x533e3e55, (q31_t)0x53397859, (q31_t)0x5334b229,
+    (q31_t)0x532febc5, (q31_t)0x532b252f,
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+    (q31_t)0x5309b174, (q31_t)0x5304e943,
+  (q31_t)0x530020df, (q31_t)0x52fb5848, (q31_t)0x52f68f7e, (q31_t)0x52f1c680, (q31_t)0x52ecfd4f, (q31_t)0x52e833ec,
+    (q31_t)0x52e36a55, (q31_t)0x52dea08a,
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+    (q31_t)0x52bd166d, (q31_t)0x52b84b0a,
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+    (q31_t)0x5296b5c3, (q31_t)0x5291e8c8,
+  (q31_t)0x528d1b9b, (q31_t)0x52884e3a, (q31_t)0x528380a7, (q31_t)0x527eb2e0, (q31_t)0x5279e4e7, (q31_t)0x527516bb,
+    (q31_t)0x5270485c, (q31_t)0x526b79ca,
+  (q31_t)0x5266ab06, (q31_t)0x5261dc0e, (q31_t)0x525d0ce4, (q31_t)0x52583d87, (q31_t)0x52536df7, (q31_t)0x524e9e34,
+    (q31_t)0x5249ce3f, (q31_t)0x5244fe17,
+  (q31_t)0x52402dbc, (q31_t)0x523b5d2e, (q31_t)0x52368c6e, (q31_t)0x5231bb7b, (q31_t)0x522cea55, (q31_t)0x522818fc,
+    (q31_t)0x52234771, (q31_t)0x521e75b3,
+  (q31_t)0x5219a3c3, (q31_t)0x5214d1a0, (q31_t)0x520fff4a, (q31_t)0x520b2cc2, (q31_t)0x52065a07, (q31_t)0x52018719,
+    (q31_t)0x51fcb3f9, (q31_t)0x51f7e0a6,
+  (q31_t)0x51f30d21, (q31_t)0x51ee3969, (q31_t)0x51e9657e, (q31_t)0x51e49162, (q31_t)0x51dfbd12, (q31_t)0x51dae890,
+    (q31_t)0x51d613dc, (q31_t)0x51d13ef5,
+  (q31_t)0x51cc69db, (q31_t)0x51c79490, (q31_t)0x51c2bf11, (q31_t)0x51bde960, (q31_t)0x51b9137d, (q31_t)0x51b43d68,
+    (q31_t)0x51af6720, (q31_t)0x51aa90a5,
+  (q31_t)0x51a5b9f9, (q31_t)0x51a0e31a, (q31_t)0x519c0c08, (q31_t)0x519734c4, (q31_t)0x51925d4e, (q31_t)0x518d85a6,
+    (q31_t)0x5188adcb, (q31_t)0x5183d5be,
+  (q31_t)0x517efd7f, (q31_t)0x517a250d, (q31_t)0x51754c69, (q31_t)0x51707393, (q31_t)0x516b9a8b, (q31_t)0x5166c150,
+    (q31_t)0x5161e7e4, (q31_t)0x515d0e45,
+  (q31_t)0x51583473, (q31_t)0x51535a70, (q31_t)0x514e803b, (q31_t)0x5149a5d3, (q31_t)0x5144cb39, (q31_t)0x513ff06d,
+    (q31_t)0x513b156f, (q31_t)0x51363a3f,
+  (q31_t)0x51315edd, (q31_t)0x512c8348, (q31_t)0x5127a782, (q31_t)0x5122cb8a, (q31_t)0x511def5f, (q31_t)0x51191302,
+    (q31_t)0x51143674, (q31_t)0x510f59b3,
+  (q31_t)0x510a7cc1, (q31_t)0x51059f9c, (q31_t)0x5100c246, (q31_t)0x50fbe4bd, (q31_t)0x50f70703, (q31_t)0x50f22916,
+    (q31_t)0x50ed4af8, (q31_t)0x50e86ca8,
+  (q31_t)0x50e38e25, (q31_t)0x50deaf71, (q31_t)0x50d9d08b, (q31_t)0x50d4f173, (q31_t)0x50d0122a, (q31_t)0x50cb32ae,
+    (q31_t)0x50c65301, (q31_t)0x50c17322,
+  (q31_t)0x50bc9311, (q31_t)0x50b7b2ce, (q31_t)0x50b2d259, (q31_t)0x50adf1b3, (q31_t)0x50a910db, (q31_t)0x50a42fd1,
+    (q31_t)0x509f4e95, (q31_t)0x509a6d28,
+  (q31_t)0x50958b88, (q31_t)0x5090a9b8, (q31_t)0x508bc7b5, (q31_t)0x5086e581, (q31_t)0x5082031b, (q31_t)0x507d2083,
+    (q31_t)0x50783dba, (q31_t)0x50735abf,
+  (q31_t)0x506e7793, (q31_t)0x50699435, (q31_t)0x5064b0a5, (q31_t)0x505fcce4, (q31_t)0x505ae8f1, (q31_t)0x505604cd,
+    (q31_t)0x50512077, (q31_t)0x504c3bef,
+  (q31_t)0x50475736, (q31_t)0x5042724c, (q31_t)0x503d8d30, (q31_t)0x5038a7e2, (q31_t)0x5033c263, (q31_t)0x502edcb2,
+    (q31_t)0x5029f6d1, (q31_t)0x502510bd,
+  (q31_t)0x50202a78, (q31_t)0x501b4402, (q31_t)0x50165d5a, (q31_t)0x50117681, (q31_t)0x500c8f77, (q31_t)0x5007a83b,
+    (q31_t)0x5002c0cd, (q31_t)0x4ffdd92f,
+  (q31_t)0x4ff8f15f, (q31_t)0x4ff4095e, (q31_t)0x4fef212b, (q31_t)0x4fea38c7, (q31_t)0x4fe55032, (q31_t)0x4fe0676c,
+    (q31_t)0x4fdb7e74, (q31_t)0x4fd6954b,
+  (q31_t)0x4fd1abf0, (q31_t)0x4fccc265, (q31_t)0x4fc7d8a8, (q31_t)0x4fc2eeba, (q31_t)0x4fbe049b, (q31_t)0x4fb91a4b,
+    (q31_t)0x4fb42fc9, (q31_t)0x4faf4517,
+  (q31_t)0x4faa5a33, (q31_t)0x4fa56f1e, (q31_t)0x4fa083d8, (q31_t)0x4f9b9861, (q31_t)0x4f96acb8, (q31_t)0x4f91c0df,
+    (q31_t)0x4f8cd4d4, (q31_t)0x4f87e899,
+  (q31_t)0x4f82fc2c, (q31_t)0x4f7e0f8f, (q31_t)0x4f7922c0, (q31_t)0x4f7435c0, (q31_t)0x4f6f488f, (q31_t)0x4f6a5b2e,
+    (q31_t)0x4f656d9b, (q31_t)0x4f607fd7,
+  (q31_t)0x4f5b91e3, (q31_t)0x4f56a3bd, (q31_t)0x4f51b566, (q31_t)0x4f4cc6df, (q31_t)0x4f47d827, (q31_t)0x4f42e93d,
+    (q31_t)0x4f3dfa23, (q31_t)0x4f390ad8,
+  (q31_t)0x4f341b5c, (q31_t)0x4f2f2baf, (q31_t)0x4f2a3bd2, (q31_t)0x4f254bc3, (q31_t)0x4f205b84, (q31_t)0x4f1b6b14,
+    (q31_t)0x4f167a73, (q31_t)0x4f1189a1,
+  (q31_t)0x4f0c989f, (q31_t)0x4f07a76b, (q31_t)0x4f02b608, (q31_t)0x4efdc473, (q31_t)0x4ef8d2ad, (q31_t)0x4ef3e0b7,
+    (q31_t)0x4eeeee90, (q31_t)0x4ee9fc39,
+  (q31_t)0x4ee509b1, (q31_t)0x4ee016f8, (q31_t)0x4edb240e, (q31_t)0x4ed630f4, (q31_t)0x4ed13da9, (q31_t)0x4ecc4a2e,
+    (q31_t)0x4ec75682, (q31_t)0x4ec262a5,
+  (q31_t)0x4ebd6e98, (q31_t)0x4eb87a5a, (q31_t)0x4eb385ec, (q31_t)0x4eae914d, (q31_t)0x4ea99c7d, (q31_t)0x4ea4a77d,
+    (q31_t)0x4e9fb24d, (q31_t)0x4e9abcec,
+  (q31_t)0x4e95c75b, (q31_t)0x4e90d199, (q31_t)0x4e8bdba6, (q31_t)0x4e86e583, (q31_t)0x4e81ef30, (q31_t)0x4e7cf8ac,
+    (q31_t)0x4e7801f8, (q31_t)0x4e730b14,
+  (q31_t)0x4e6e13ff, (q31_t)0x4e691cba, (q31_t)0x4e642544, (q31_t)0x4e5f2d9e, (q31_t)0x4e5a35c7, (q31_t)0x4e553dc1,
+    (q31_t)0x4e50458a, (q31_t)0x4e4b4d22,
+  (q31_t)0x4e46548b, (q31_t)0x4e415bc3, (q31_t)0x4e3c62cb, (q31_t)0x4e3769a2, (q31_t)0x4e32704a, (q31_t)0x4e2d76c1,
+    (q31_t)0x4e287d08, (q31_t)0x4e23831e,
+  (q31_t)0x4e1e8905, (q31_t)0x4e198ebb, (q31_t)0x4e149441, (q31_t)0x4e0f9997, (q31_t)0x4e0a9ebd, (q31_t)0x4e05a3b2,
+    (q31_t)0x4e00a878, (q31_t)0x4dfbad0d,
+  (q31_t)0x4df6b173, (q31_t)0x4df1b5a8, (q31_t)0x4decb9ad, (q31_t)0x4de7bd82, (q31_t)0x4de2c127, (q31_t)0x4dddc49c,
+    (q31_t)0x4dd8c7e1, (q31_t)0x4dd3caf6,
+  (q31_t)0x4dcecdda, (q31_t)0x4dc9d08f, (q31_t)0x4dc4d314, (q31_t)0x4dbfd569, (q31_t)0x4dbad78e, (q31_t)0x4db5d983,
+    (q31_t)0x4db0db48, (q31_t)0x4dabdcdd,
+  (q31_t)0x4da6de43, (q31_t)0x4da1df78, (q31_t)0x4d9ce07d, (q31_t)0x4d97e153, (q31_t)0x4d92e1f9, (q31_t)0x4d8de26f,
+    (q31_t)0x4d88e2b5, (q31_t)0x4d83e2cb,
+  (q31_t)0x4d7ee2b1, (q31_t)0x4d79e268, (q31_t)0x4d74e1ef, (q31_t)0x4d6fe146, (q31_t)0x4d6ae06d, (q31_t)0x4d65df64,
+    (q31_t)0x4d60de2c, (q31_t)0x4d5bdcc4,
+  (q31_t)0x4d56db2d, (q31_t)0x4d51d965, (q31_t)0x4d4cd76e, (q31_t)0x4d47d547, (q31_t)0x4d42d2f1, (q31_t)0x4d3dd06b,
+    (q31_t)0x4d38cdb5, (q31_t)0x4d33cad0,
+  (q31_t)0x4d2ec7bb, (q31_t)0x4d29c476, (q31_t)0x4d24c102, (q31_t)0x4d1fbd5e, (q31_t)0x4d1ab98b, (q31_t)0x4d15b588,
+    (q31_t)0x4d10b155, (q31_t)0x4d0bacf3,
+  (q31_t)0x4d06a862, (q31_t)0x4d01a3a0, (q31_t)0x4cfc9eb0, (q31_t)0x4cf79990, (q31_t)0x4cf29440, (q31_t)0x4ced8ec1,
+    (q31_t)0x4ce88913, (q31_t)0x4ce38335,
+  (q31_t)0x4cde7d28, (q31_t)0x4cd976eb, (q31_t)0x4cd4707f, (q31_t)0x4ccf69e3, (q31_t)0x4cca6318, (q31_t)0x4cc55c1e,
+    (q31_t)0x4cc054f4, (q31_t)0x4cbb4d9b,
+  (q31_t)0x4cb64613, (q31_t)0x4cb13e5b, (q31_t)0x4cac3674, (q31_t)0x4ca72e5e, (q31_t)0x4ca22619, (q31_t)0x4c9d1da4,
+    (q31_t)0x4c981500, (q31_t)0x4c930c2d,
+  (q31_t)0x4c8e032a, (q31_t)0x4c88f9f8, (q31_t)0x4c83f097, (q31_t)0x4c7ee707, (q31_t)0x4c79dd48, (q31_t)0x4c74d359,
+    (q31_t)0x4c6fc93b, (q31_t)0x4c6abeef,
+  (q31_t)0x4c65b473, (q31_t)0x4c60a9c8, (q31_t)0x4c5b9eed, (q31_t)0x4c5693e4, (q31_t)0x4c5188ac, (q31_t)0x4c4c7d44,
+    (q31_t)0x4c4771ae, (q31_t)0x4c4265e8,
+  (q31_t)0x4c3d59f3, (q31_t)0x4c384dd0, (q31_t)0x4c33417d, (q31_t)0x4c2e34fb, (q31_t)0x4c29284b, (q31_t)0x4c241b6b,
+    (q31_t)0x4c1f0e5c, (q31_t)0x4c1a011f,
+  (q31_t)0x4c14f3b2, (q31_t)0x4c0fe617, (q31_t)0x4c0ad84c, (q31_t)0x4c05ca53, (q31_t)0x4c00bc2b, (q31_t)0x4bfbadd4,
+    (q31_t)0x4bf69f4e, (q31_t)0x4bf19099,
+  (q31_t)0x4bec81b5, (q31_t)0x4be772a3, (q31_t)0x4be26362, (q31_t)0x4bdd53f2, (q31_t)0x4bd84453, (q31_t)0x4bd33485,
+    (q31_t)0x4bce2488, (q31_t)0x4bc9145d,
+  (q31_t)0x4bc40403, (q31_t)0x4bbef37b, (q31_t)0x4bb9e2c3, (q31_t)0x4bb4d1dd, (q31_t)0x4bafc0c8, (q31_t)0x4baaaf85,
+    (q31_t)0x4ba59e12, (q31_t)0x4ba08c72,
+  (q31_t)0x4b9b7aa2, (q31_t)0x4b9668a4, (q31_t)0x4b915677, (q31_t)0x4b8c441c, (q31_t)0x4b873192, (q31_t)0x4b821ed9,
+    (q31_t)0x4b7d0bf2, (q31_t)0x4b77f8dc,
+  (q31_t)0x4b72e598, (q31_t)0x4b6dd225, (q31_t)0x4b68be84, (q31_t)0x4b63aab4, (q31_t)0x4b5e96b6, (q31_t)0x4b598289,
+    (q31_t)0x4b546e2d, (q31_t)0x4b4f59a4,
+  (q31_t)0x4b4a44eb, (q31_t)0x4b453005, (q31_t)0x4b401aef, (q31_t)0x4b3b05ac, (q31_t)0x4b35f03a, (q31_t)0x4b30da9a,
+    (q31_t)0x4b2bc4cb, (q31_t)0x4b26aece,
+  (q31_t)0x4b2198a2, (q31_t)0x4b1c8248, (q31_t)0x4b176bc0, (q31_t)0x4b12550a, (q31_t)0x4b0d3e25, (q31_t)0x4b082712,
+    (q31_t)0x4b030fd1, (q31_t)0x4afdf861,
+  (q31_t)0x4af8e0c3, (q31_t)0x4af3c8f7, (q31_t)0x4aeeb0fd, (q31_t)0x4ae998d4, (q31_t)0x4ae4807d, (q31_t)0x4adf67f8,
+    (q31_t)0x4ada4f45, (q31_t)0x4ad53664,
+  (q31_t)0x4ad01d54, (q31_t)0x4acb0417, (q31_t)0x4ac5eaab, (q31_t)0x4ac0d111, (q31_t)0x4abbb749, (q31_t)0x4ab69d53,
+    (q31_t)0x4ab1832f, (q31_t)0x4aac68dc,
+  (q31_t)0x4aa74e5c, (q31_t)0x4aa233ae, (q31_t)0x4a9d18d1, (q31_t)0x4a97fdc7, (q31_t)0x4a92e28e, (q31_t)0x4a8dc728,
+    (q31_t)0x4a88ab93, (q31_t)0x4a838fd1,
+  (q31_t)0x4a7e73e0, (q31_t)0x4a7957c2, (q31_t)0x4a743b76, (q31_t)0x4a6f1efc, (q31_t)0x4a6a0253, (q31_t)0x4a64e57d,
+    (q31_t)0x4a5fc879, (q31_t)0x4a5aab48,
+  (q31_t)0x4a558de8, (q31_t)0x4a50705a, (q31_t)0x4a4b529f, (q31_t)0x4a4634b6, (q31_t)0x4a41169f, (q31_t)0x4a3bf85a,
+    (q31_t)0x4a36d9e7, (q31_t)0x4a31bb47,
+  (q31_t)0x4a2c9c79, (q31_t)0x4a277d7d, (q31_t)0x4a225e53, (q31_t)0x4a1d3efc, (q31_t)0x4a181f77, (q31_t)0x4a12ffc4,
+    (q31_t)0x4a0ddfe4, (q31_t)0x4a08bfd5,
+  (q31_t)0x4a039f9a, (q31_t)0x49fe7f30, (q31_t)0x49f95e99, (q31_t)0x49f43dd4, (q31_t)0x49ef1ce2, (q31_t)0x49e9fbc2,
+    (q31_t)0x49e4da74, (q31_t)0x49dfb8f9,
+  (q31_t)0x49da9750, (q31_t)0x49d5757a, (q31_t)0x49d05376, (q31_t)0x49cb3145, (q31_t)0x49c60ee6, (q31_t)0x49c0ec59,
+    (q31_t)0x49bbc9a0, (q31_t)0x49b6a6b8,
+  (q31_t)0x49b183a3, (q31_t)0x49ac6061, (q31_t)0x49a73cf1, (q31_t)0x49a21954, (q31_t)0x499cf589, (q31_t)0x4997d191,
+    (q31_t)0x4992ad6c, (q31_t)0x498d8919,
+  (q31_t)0x49886499, (q31_t)0x49833fec, (q31_t)0x497e1b11, (q31_t)0x4978f609, (q31_t)0x4973d0d3, (q31_t)0x496eab70,
+    (q31_t)0x496985e0, (q31_t)0x49646023,
+  (q31_t)0x495f3a38, (q31_t)0x495a1420, (q31_t)0x4954eddb, (q31_t)0x494fc768, (q31_t)0x494aa0c9, (q31_t)0x494579fc,
+    (q31_t)0x49405302, (q31_t)0x493b2bdb,
+  (q31_t)0x49360486, (q31_t)0x4930dd05, (q31_t)0x492bb556, (q31_t)0x49268d7a, (q31_t)0x49216571, (q31_t)0x491c3d3b,
+    (q31_t)0x491714d8, (q31_t)0x4911ec47,
+  (q31_t)0x490cc38a, (q31_t)0x49079aa0, (q31_t)0x49027188, (q31_t)0x48fd4844, (q31_t)0x48f81ed2, (q31_t)0x48f2f534,
+    (q31_t)0x48edcb68, (q31_t)0x48e8a170,
+  (q31_t)0x48e3774a, (q31_t)0x48de4cf8, (q31_t)0x48d92278, (q31_t)0x48d3f7cc, (q31_t)0x48ceccf3, (q31_t)0x48c9a1ed,
+    (q31_t)0x48c476b9, (q31_t)0x48bf4b59,
+  (q31_t)0x48ba1fcd, (q31_t)0x48b4f413, (q31_t)0x48afc82c, (q31_t)0x48aa9c19, (q31_t)0x48a56fd9, (q31_t)0x48a0436c,
+    (q31_t)0x489b16d2, (q31_t)0x4895ea0b,
+  (q31_t)0x4890bd18, (q31_t)0x488b8ff8, (q31_t)0x488662ab, (q31_t)0x48813531, (q31_t)0x487c078b, (q31_t)0x4876d9b8,
+    (q31_t)0x4871abb8, (q31_t)0x486c7d8c,
+  (q31_t)0x48674f33, (q31_t)0x486220ad, (q31_t)0x485cf1fa, (q31_t)0x4857c31b, (q31_t)0x48529410, (q31_t)0x484d64d7,
+    (q31_t)0x48483572, (q31_t)0x484305e1,
+  (q31_t)0x483dd623, (q31_t)0x4838a638, (q31_t)0x48337621, (q31_t)0x482e45dd, (q31_t)0x4829156d, (q31_t)0x4823e4d0,
+    (q31_t)0x481eb407, (q31_t)0x48198311,
+  (q31_t)0x481451ef, (q31_t)0x480f20a0, (q31_t)0x4809ef25, (q31_t)0x4804bd7e, (q31_t)0x47ff8baa, (q31_t)0x47fa59a9,
+    (q31_t)0x47f5277d, (q31_t)0x47eff523,
+  (q31_t)0x47eac29e, (q31_t)0x47e58fec, (q31_t)0x47e05d0e, (q31_t)0x47db2a03, (q31_t)0x47d5f6cc, (q31_t)0x47d0c369,
+    (q31_t)0x47cb8fd9, (q31_t)0x47c65c1d,
+  (q31_t)0x47c12835, (q31_t)0x47bbf421, (q31_t)0x47b6bfe0, (q31_t)0x47b18b74, (q31_t)0x47ac56da, (q31_t)0x47a72215,
+    (q31_t)0x47a1ed24, (q31_t)0x479cb806,
+  (q31_t)0x479782bc, (q31_t)0x47924d46, (q31_t)0x478d17a4, (q31_t)0x4787e1d6, (q31_t)0x4782abdb, (q31_t)0x477d75b5,
+    (q31_t)0x47783f62, (q31_t)0x477308e3,
+  (q31_t)0x476dd239, (q31_t)0x47689b62, (q31_t)0x4763645f, (q31_t)0x475e2d30, (q31_t)0x4758f5d5, (q31_t)0x4753be4e,
+    (q31_t)0x474e869b, (q31_t)0x47494ebc,
+  (q31_t)0x474416b1, (q31_t)0x473ede7a, (q31_t)0x4739a617, (q31_t)0x47346d89, (q31_t)0x472f34ce, (q31_t)0x4729fbe7,
+    (q31_t)0x4724c2d5, (q31_t)0x471f8996,
+  (q31_t)0x471a502c, (q31_t)0x47151696, (q31_t)0x470fdcd4, (q31_t)0x470aa2e6, (q31_t)0x470568cd, (q31_t)0x47002e87,
+    (q31_t)0x46faf416, (q31_t)0x46f5b979,
+  (q31_t)0x46f07eb0, (q31_t)0x46eb43bc, (q31_t)0x46e6089b, (q31_t)0x46e0cd4f, (q31_t)0x46db91d8, (q31_t)0x46d65634,
+    (q31_t)0x46d11a65, (q31_t)0x46cbde6a,
+  (q31_t)0x46c6a244, (q31_t)0x46c165f1, (q31_t)0x46bc2974, (q31_t)0x46b6ecca, (q31_t)0x46b1aff5, (q31_t)0x46ac72f4,
+    (q31_t)0x46a735c8, (q31_t)0x46a1f870,
+  (q31_t)0x469cbaed, (q31_t)0x46977d3e, (q31_t)0x46923f63, (q31_t)0x468d015d, (q31_t)0x4687c32c, (q31_t)0x468284cf,
+    (q31_t)0x467d4646, (q31_t)0x46780792,
+  (q31_t)0x4672c8b3, (q31_t)0x466d89a8, (q31_t)0x46684a71, (q31_t)0x46630b0f, (q31_t)0x465dcb82, (q31_t)0x46588bc9,
+    (q31_t)0x46534be5, (q31_t)0x464e0bd6,
+  (q31_t)0x4648cb9b, (q31_t)0x46438b35, (q31_t)0x463e4aa3, (q31_t)0x463909e7, (q31_t)0x4633c8fe, (q31_t)0x462e87eb,
+    (q31_t)0x462946ac, (q31_t)0x46240542,
+  (q31_t)0x461ec3ad, (q31_t)0x461981ec, (q31_t)0x46144001, (q31_t)0x460efde9, (q31_t)0x4609bba7, (q31_t)0x4604793a,
+    (q31_t)0x45ff36a1, (q31_t)0x45f9f3dd,
+  (q31_t)0x45f4b0ee, (q31_t)0x45ef6dd4, (q31_t)0x45ea2a8f, (q31_t)0x45e4e71f, (q31_t)0x45dfa383, (q31_t)0x45da5fbc,
+    (q31_t)0x45d51bcb, (q31_t)0x45cfd7ae,
+  (q31_t)0x45ca9366, (q31_t)0x45c54ef3, (q31_t)0x45c00a55, (q31_t)0x45bac58c, (q31_t)0x45b58098, (q31_t)0x45b03b79,
+    (q31_t)0x45aaf630, (q31_t)0x45a5b0bb,
+  (q31_t)0x45a06b1b, (q31_t)0x459b2550, (q31_t)0x4595df5a, (q31_t)0x45909939, (q31_t)0x458b52ee, (q31_t)0x45860c77,
+    (q31_t)0x4580c5d6, (q31_t)0x457b7f0a,
+  (q31_t)0x45763813, (q31_t)0x4570f0f1, (q31_t)0x456ba9a4, (q31_t)0x4566622c, (q31_t)0x45611a8a, (q31_t)0x455bd2bc,
+    (q31_t)0x45568ac4, (q31_t)0x455142a2,
+  (q31_t)0x454bfa54, (q31_t)0x4546b1dc, (q31_t)0x45416939, (q31_t)0x453c206b, (q31_t)0x4536d773, (q31_t)0x45318e4f,
+    (q31_t)0x452c4502, (q31_t)0x4526fb89,
+  (q31_t)0x4521b1e6, (q31_t)0x451c6818, (q31_t)0x45171e20, (q31_t)0x4511d3fd, (q31_t)0x450c89af, (q31_t)0x45073f37,
+    (q31_t)0x4501f494, (q31_t)0x44fca9c6,
+  (q31_t)0x44f75ecf, (q31_t)0x44f213ac, (q31_t)0x44ecc85f, (q31_t)0x44e77ce7, (q31_t)0x44e23145, (q31_t)0x44dce579,
+    (q31_t)0x44d79982, (q31_t)0x44d24d60,
+  (q31_t)0x44cd0114, (q31_t)0x44c7b49e, (q31_t)0x44c267fd, (q31_t)0x44bd1b32, (q31_t)0x44b7ce3c, (q31_t)0x44b2811c,
+    (q31_t)0x44ad33d2, (q31_t)0x44a7e65d,
+  (q31_t)0x44a298be, (q31_t)0x449d4af5, (q31_t)0x4497fd01, (q31_t)0x4492aee3, (q31_t)0x448d609b, (q31_t)0x44881228,
+    (q31_t)0x4482c38b, (q31_t)0x447d74c4,
+  (q31_t)0x447825d2, (q31_t)0x4472d6b7, (q31_t)0x446d8771, (q31_t)0x44683801, (q31_t)0x4462e866, (q31_t)0x445d98a2,
+    (q31_t)0x445848b3, (q31_t)0x4452f89b,
+  (q31_t)0x444da858, (q31_t)0x444857ea, (q31_t)0x44430753, (q31_t)0x443db692, (q31_t)0x443865a7, (q31_t)0x44331491,
+    (q31_t)0x442dc351, (q31_t)0x442871e8,
+  (q31_t)0x44232054, (q31_t)0x441dce96, (q31_t)0x44187caf, (q31_t)0x44132a9d, (q31_t)0x440dd861, (q31_t)0x440885fc,
+    (q31_t)0x4403336c, (q31_t)0x43fde0b2,
+  (q31_t)0x43f88dcf, (q31_t)0x43f33ac1, (q31_t)0x43ede78a, (q31_t)0x43e89429, (q31_t)0x43e3409d, (q31_t)0x43ddece8,
+    (q31_t)0x43d8990a, (q31_t)0x43d34501,
+  (q31_t)0x43cdf0ce, (q31_t)0x43c89c72, (q31_t)0x43c347eb, (q31_t)0x43bdf33b, (q31_t)0x43b89e62, (q31_t)0x43b3495e,
+    (q31_t)0x43adf431, (q31_t)0x43a89ed9,
+  (q31_t)0x43a34959, (q31_t)0x439df3ae, (q31_t)0x43989dda, (q31_t)0x439347dc, (q31_t)0x438df1b4, (q31_t)0x43889b63,
+    (q31_t)0x438344e8, (q31_t)0x437dee43,
+  (q31_t)0x43789775, (q31_t)0x4373407d, (q31_t)0x436de95b, (q31_t)0x43689210, (q31_t)0x43633a9c, (q31_t)0x435de2fd,
+    (q31_t)0x43588b36, (q31_t)0x43533344,
+  (q31_t)0x434ddb29, (q31_t)0x434882e5, (q31_t)0x43432a77, (q31_t)0x433dd1e0, (q31_t)0x4338791f, (q31_t)0x43332035,
+    (q31_t)0x432dc721, (q31_t)0x43286de4,
+  (q31_t)0x4323147d, (q31_t)0x431dbaed, (q31_t)0x43186133, (q31_t)0x43130751, (q31_t)0x430dad44, (q31_t)0x4308530f,
+    (q31_t)0x4302f8b0, (q31_t)0x42fd9e28,
+  (q31_t)0x42f84376, (q31_t)0x42f2e89b, (q31_t)0x42ed8d97, (q31_t)0x42e83269, (q31_t)0x42e2d713, (q31_t)0x42dd7b93,
+    (q31_t)0x42d81fe9, (q31_t)0x42d2c417,
+  (q31_t)0x42cd681b, (q31_t)0x42c80bf6, (q31_t)0x42c2afa8, (q31_t)0x42bd5331, (q31_t)0x42b7f690, (q31_t)0x42b299c7,
+    (q31_t)0x42ad3cd4, (q31_t)0x42a7dfb8,
+  (q31_t)0x42a28273, (q31_t)0x429d2505, (q31_t)0x4297c76e, (q31_t)0x429269ae, (q31_t)0x428d0bc4, (q31_t)0x4287adb2,
+    (q31_t)0x42824f76, (q31_t)0x427cf112,
+  (q31_t)0x42779285, (q31_t)0x427233ce, (q31_t)0x426cd4ef, (q31_t)0x426775e6, (q31_t)0x426216b5, (q31_t)0x425cb75a,
+    (q31_t)0x425757d7, (q31_t)0x4251f82b,
+  (q31_t)0x424c9856, (q31_t)0x42473858, (q31_t)0x4241d831, (q31_t)0x423c77e1, (q31_t)0x42371769, (q31_t)0x4231b6c7,
+    (q31_t)0x422c55fd, (q31_t)0x4226f50a,
+  (q31_t)0x422193ee, (q31_t)0x421c32a9, (q31_t)0x4216d13c, (q31_t)0x42116fa5, (q31_t)0x420c0de6, (q31_t)0x4206abfe,
+    (q31_t)0x420149ee, (q31_t)0x41fbe7b5,
+  (q31_t)0x41f68553, (q31_t)0x41f122c8, (q31_t)0x41ebc015, (q31_t)0x41e65d39, (q31_t)0x41e0fa35, (q31_t)0x41db9707,
+    (q31_t)0x41d633b1, (q31_t)0x41d0d033,
+  (q31_t)0x41cb6c8c, (q31_t)0x41c608bc, (q31_t)0x41c0a4c4, (q31_t)0x41bb40a3, (q31_t)0x41b5dc5a, (q31_t)0x41b077e8,
+    (q31_t)0x41ab134e, (q31_t)0x41a5ae8b,
+  (q31_t)0x41a049a0, (q31_t)0x419ae48c, (q31_t)0x41957f4f, (q31_t)0x419019eb, (q31_t)0x418ab45d, (q31_t)0x41854ea8,
+    (q31_t)0x417fe8ca, (q31_t)0x417a82c3,
+  (q31_t)0x41751c94, (q31_t)0x416fb63d, (q31_t)0x416a4fbd, (q31_t)0x4164e916, (q31_t)0x415f8245, (q31_t)0x415a1b4d,
+    (q31_t)0x4154b42c, (q31_t)0x414f4ce2,
+  (q31_t)0x4149e571, (q31_t)0x41447dd7, (q31_t)0x413f1615, (q31_t)0x4139ae2b, (q31_t)0x41344618, (q31_t)0x412edddd,
+    (q31_t)0x4129757b, (q31_t)0x41240cef,
+  (q31_t)0x411ea43c, (q31_t)0x41193b61, (q31_t)0x4113d25d, (q31_t)0x410e6931, (q31_t)0x4108ffdd, (q31_t)0x41039661,
+    (q31_t)0x40fe2cbd, (q31_t)0x40f8c2f1,
+  (q31_t)0x40f358fc, (q31_t)0x40edeee0, (q31_t)0x40e8849b, (q31_t)0x40e31a2f, (q31_t)0x40ddaf9b, (q31_t)0x40d844de,
+    (q31_t)0x40d2d9f9, (q31_t)0x40cd6eed,
+  (q31_t)0x40c803b8, (q31_t)0x40c2985c, (q31_t)0x40bd2cd8, (q31_t)0x40b7c12b, (q31_t)0x40b25557, (q31_t)0x40ace95b,
+    (q31_t)0x40a77d37, (q31_t)0x40a210eb,
+  (q31_t)0x409ca477, (q31_t)0x409737dc, (q31_t)0x4091cb18, (q31_t)0x408c5e2d, (q31_t)0x4086f11a, (q31_t)0x408183df,
+    (q31_t)0x407c167c, (q31_t)0x4076a8f1,
+  (q31_t)0x40713b3f, (q31_t)0x406bcd65, (q31_t)0x40665f63, (q31_t)0x4060f13a, (q31_t)0x405b82e9, (q31_t)0x40561470,
+    (q31_t)0x4050a5cf, (q31_t)0x404b3707,
+  (q31_t)0x4045c817, (q31_t)0x404058ff, (q31_t)0x403ae9c0, (q31_t)0x40357a59, (q31_t)0x40300acb, (q31_t)0x402a9b15,
+    (q31_t)0x40252b37, (q31_t)0x401fbb32,
+  (q31_t)0x401a4b05, (q31_t)0x4014dab1, (q31_t)0x400f6a35, (q31_t)0x4009f992, (q31_t)0x400488c7, (q31_t)0x3fff17d5,
+    (q31_t)0x3ff9a6bb, (q31_t)0x3ff4357a,
+  (q31_t)0x3feec411, (q31_t)0x3fe95281, (q31_t)0x3fe3e0c9, (q31_t)0x3fde6eeb, (q31_t)0x3fd8fce4, (q31_t)0x3fd38ab6,
+    (q31_t)0x3fce1861, (q31_t)0x3fc8a5e5,
+  (q31_t)0x3fc33341, (q31_t)0x3fbdc076, (q31_t)0x3fb84d83, (q31_t)0x3fb2da6a, (q31_t)0x3fad6729, (q31_t)0x3fa7f3c0,
+    (q31_t)0x3fa28031, (q31_t)0x3f9d0c7a,
+  (q31_t)0x3f97989c, (q31_t)0x3f922496, (q31_t)0x3f8cb06a, (q31_t)0x3f873c16, (q31_t)0x3f81c79b, (q31_t)0x3f7c52f9,
+    (q31_t)0x3f76de30, (q31_t)0x3f71693f,
+  (q31_t)0x3f6bf428, (q31_t)0x3f667ee9, (q31_t)0x3f610983, (q31_t)0x3f5b93f6, (q31_t)0x3f561e42, (q31_t)0x3f50a867,
+    (q31_t)0x3f4b3265, (q31_t)0x3f45bc3c,
+  (q31_t)0x3f4045ec, (q31_t)0x3f3acf75, (q31_t)0x3f3558d7, (q31_t)0x3f2fe211, (q31_t)0x3f2a6b25, (q31_t)0x3f24f412,
+    (q31_t)0x3f1f7cd8, (q31_t)0x3f1a0577,
+  (q31_t)0x3f148def, (q31_t)0x3f0f1640, (q31_t)0x3f099e6b, (q31_t)0x3f04266e, (q31_t)0x3efeae4a, (q31_t)0x3ef93600,
+    (q31_t)0x3ef3bd8f, (q31_t)0x3eee44f7,
+  (q31_t)0x3ee8cc38, (q31_t)0x3ee35352, (q31_t)0x3eddda46, (q31_t)0x3ed86113, (q31_t)0x3ed2e7b9, (q31_t)0x3ecd6e38,
+    (q31_t)0x3ec7f491, (q31_t)0x3ec27ac2,
+  (q31_t)0x3ebd00cd, (q31_t)0x3eb786b2, (q31_t)0x3eb20c6f, (q31_t)0x3eac9206, (q31_t)0x3ea71777, (q31_t)0x3ea19cc1,
+    (q31_t)0x3e9c21e4, (q31_t)0x3e96a6e0,
+  (q31_t)0x3e912bb6, (q31_t)0x3e8bb065, (q31_t)0x3e8634ee, (q31_t)0x3e80b950, (q31_t)0x3e7b3d8c, (q31_t)0x3e75c1a1,
+    (q31_t)0x3e70458f, (q31_t)0x3e6ac957,
+  (q31_t)0x3e654cf8, (q31_t)0x3e5fd073, (q31_t)0x3e5a53c8, (q31_t)0x3e54d6f6, (q31_t)0x3e4f59fe, (q31_t)0x3e49dcdf,
+    (q31_t)0x3e445f99, (q31_t)0x3e3ee22e,
+  (q31_t)0x3e39649c, (q31_t)0x3e33e6e3, (q31_t)0x3e2e6904, (q31_t)0x3e28eaff, (q31_t)0x3e236cd4, (q31_t)0x3e1dee82,
+    (q31_t)0x3e18700a, (q31_t)0x3e12f16b,
+  (q31_t)0x3e0d72a6, (q31_t)0x3e07f3bb, (q31_t)0x3e0274aa, (q31_t)0x3dfcf572, (q31_t)0x3df77615, (q31_t)0x3df1f691,
+    (q31_t)0x3dec76e6, (q31_t)0x3de6f716,
+  (q31_t)0x3de1771f, (q31_t)0x3ddbf703, (q31_t)0x3dd676c0, (q31_t)0x3dd0f656, (q31_t)0x3dcb75c7, (q31_t)0x3dc5f512,
+    (q31_t)0x3dc07436, (q31_t)0x3dbaf335,
+  (q31_t)0x3db5720d, (q31_t)0x3daff0c0, (q31_t)0x3daa6f4c, (q31_t)0x3da4edb2, (q31_t)0x3d9f6bf2, (q31_t)0x3d99ea0d,
+    (q31_t)0x3d946801, (q31_t)0x3d8ee5cf,
+  (q31_t)0x3d896377, (q31_t)0x3d83e0f9, (q31_t)0x3d7e5e56, (q31_t)0x3d78db8c, (q31_t)0x3d73589d, (q31_t)0x3d6dd587,
+    (q31_t)0x3d68524c, (q31_t)0x3d62ceeb,
+  (q31_t)0x3d5d4b64, (q31_t)0x3d57c7b7, (q31_t)0x3d5243e4, (q31_t)0x3d4cbfeb, (q31_t)0x3d473bcd, (q31_t)0x3d41b789,
+    (q31_t)0x3d3c331f, (q31_t)0x3d36ae8f,
+  (q31_t)0x3d3129da, (q31_t)0x3d2ba4fe, (q31_t)0x3d261ffd, (q31_t)0x3d209ad7, (q31_t)0x3d1b158a, (q31_t)0x3d159018,
+    (q31_t)0x3d100a80, (q31_t)0x3d0a84c3,
+  (q31_t)0x3d04fee0, (q31_t)0x3cff78d7, (q31_t)0x3cf9f2a9, (q31_t)0x3cf46c55, (q31_t)0x3ceee5db, (q31_t)0x3ce95f3c,
+    (q31_t)0x3ce3d877, (q31_t)0x3cde518d,
+  (q31_t)0x3cd8ca7d, (q31_t)0x3cd34347, (q31_t)0x3ccdbbed, (q31_t)0x3cc8346c, (q31_t)0x3cc2acc6, (q31_t)0x3cbd24fb,
+    (q31_t)0x3cb79d0a, (q31_t)0x3cb214f4,
+  (q31_t)0x3cac8cb8, (q31_t)0x3ca70457, (q31_t)0x3ca17bd0, (q31_t)0x3c9bf324, (q31_t)0x3c966a53, (q31_t)0x3c90e15c,
+    (q31_t)0x3c8b5840, (q31_t)0x3c85cefe,
+  (q31_t)0x3c804598, (q31_t)0x3c7abc0c, (q31_t)0x3c75325a, (q31_t)0x3c6fa883, (q31_t)0x3c6a1e87, (q31_t)0x3c649466,
+    (q31_t)0x3c5f0a20, (q31_t)0x3c597fb4,
+  (q31_t)0x3c53f523, (q31_t)0x3c4e6a6d, (q31_t)0x3c48df91, (q31_t)0x3c435491, (q31_t)0x3c3dc96b, (q31_t)0x3c383e20,
+    (q31_t)0x3c32b2b0, (q31_t)0x3c2d271b,
+  (q31_t)0x3c279b61, (q31_t)0x3c220f81, (q31_t)0x3c1c837d, (q31_t)0x3c16f753, (q31_t)0x3c116b04, (q31_t)0x3c0bde91,
+    (q31_t)0x3c0651f8, (q31_t)0x3c00c53a,
+  (q31_t)0x3bfb3857, (q31_t)0x3bf5ab50, (q31_t)0x3bf01e23, (q31_t)0x3bea90d1, (q31_t)0x3be5035a, (q31_t)0x3bdf75bf,
+    (q31_t)0x3bd9e7fe, (q31_t)0x3bd45a19,
+  (q31_t)0x3bcecc0e, (q31_t)0x3bc93ddf, (q31_t)0x3bc3af8b, (q31_t)0x3bbe2112, (q31_t)0x3bb89274, (q31_t)0x3bb303b1,
+    (q31_t)0x3bad74c9, (q31_t)0x3ba7e5bd,
+  (q31_t)0x3ba2568c, (q31_t)0x3b9cc736, (q31_t)0x3b9737bb, (q31_t)0x3b91a81c, (q31_t)0x3b8c1857, (q31_t)0x3b86886e,
+    (q31_t)0x3b80f861, (q31_t)0x3b7b682e,
+  (q31_t)0x3b75d7d7, (q31_t)0x3b70475c, (q31_t)0x3b6ab6bb, (q31_t)0x3b6525f6, (q31_t)0x3b5f950c, (q31_t)0x3b5a03fe,
+    (q31_t)0x3b5472cb, (q31_t)0x3b4ee173,
+  (q31_t)0x3b494ff7, (q31_t)0x3b43be57, (q31_t)0x3b3e2c91, (q31_t)0x3b389aa8, (q31_t)0x3b330899, (q31_t)0x3b2d7666,
+    (q31_t)0x3b27e40f, (q31_t)0x3b225193,
+  (q31_t)0x3b1cbef3, (q31_t)0x3b172c2e, (q31_t)0x3b119945, (q31_t)0x3b0c0637, (q31_t)0x3b067305, (q31_t)0x3b00dfaf,
+    (q31_t)0x3afb4c34, (q31_t)0x3af5b894,
+  (q31_t)0x3af024d1, (q31_t)0x3aea90e9, (q31_t)0x3ae4fcdc, (q31_t)0x3adf68ac, (q31_t)0x3ad9d457, (q31_t)0x3ad43fdd,
+    (q31_t)0x3aceab40, (q31_t)0x3ac9167e,
+  (q31_t)0x3ac38198, (q31_t)0x3abdec8d, (q31_t)0x3ab8575f, (q31_t)0x3ab2c20c, (q31_t)0x3aad2c95, (q31_t)0x3aa796fa,
+    (q31_t)0x3aa2013a, (q31_t)0x3a9c6b57,
+  (q31_t)0x3a96d54f, (q31_t)0x3a913f23, (q31_t)0x3a8ba8d3, (q31_t)0x3a86125f, (q31_t)0x3a807bc7, (q31_t)0x3a7ae50a,
+    (q31_t)0x3a754e2a, (q31_t)0x3a6fb726,
+  (q31_t)0x3a6a1ffd, (q31_t)0x3a6488b1, (q31_t)0x3a5ef140, (q31_t)0x3a5959ab, (q31_t)0x3a53c1f3, (q31_t)0x3a4e2a16,
+    (q31_t)0x3a489216, (q31_t)0x3a42f9f2,
+  (q31_t)0x3a3d61a9, (q31_t)0x3a37c93d, (q31_t)0x3a3230ad, (q31_t)0x3a2c97f9, (q31_t)0x3a26ff21, (q31_t)0x3a216625,
+    (q31_t)0x3a1bcd05, (q31_t)0x3a1633c1,
+  (q31_t)0x3a109a5a, (q31_t)0x3a0b00cf, (q31_t)0x3a056720, (q31_t)0x39ffcd4d, (q31_t)0x39fa3356, (q31_t)0x39f4993c,
+    (q31_t)0x39eefefe, (q31_t)0x39e9649c,
+  (q31_t)0x39e3ca17, (q31_t)0x39de2f6d, (q31_t)0x39d894a0, (q31_t)0x39d2f9b0, (q31_t)0x39cd5e9b, (q31_t)0x39c7c363,
+    (q31_t)0x39c22808, (q31_t)0x39bc8c89,
+  (q31_t)0x39b6f0e6, (q31_t)0x39b1551f, (q31_t)0x39abb935, (q31_t)0x39a61d28, (q31_t)0x39a080f6, (q31_t)0x399ae4a2,
+    (q31_t)0x39954829, (q31_t)0x398fab8e,
+  (q31_t)0x398a0ece, (q31_t)0x398471ec, (q31_t)0x397ed4e5, (q31_t)0x397937bc, (q31_t)0x39739a6e, (q31_t)0x396dfcfe,
+    (q31_t)0x39685f6a, (q31_t)0x3962c1b2,
+  (q31_t)0x395d23d7, (q31_t)0x395785d9, (q31_t)0x3951e7b8, (q31_t)0x394c4973, (q31_t)0x3946ab0a, (q31_t)0x39410c7f,
+    (q31_t)0x393b6dd0, (q31_t)0x3935cefd,
+  (q31_t)0x39303008, (q31_t)0x392a90ef, (q31_t)0x3924f1b3, (q31_t)0x391f5254, (q31_t)0x3919b2d1, (q31_t)0x3914132b,
+    (q31_t)0x390e7362, (q31_t)0x3908d376,
+  (q31_t)0x39033367, (q31_t)0x38fd9334, (q31_t)0x38f7f2de, (q31_t)0x38f25266, (q31_t)0x38ecb1ca, (q31_t)0x38e7110a,
+    (q31_t)0x38e17028, (q31_t)0x38dbcf23,
+  (q31_t)0x38d62dfb, (q31_t)0x38d08caf, (q31_t)0x38caeb41, (q31_t)0x38c549af, (q31_t)0x38bfa7fb, (q31_t)0x38ba0623,
+    (q31_t)0x38b46429, (q31_t)0x38aec20b,
+  (q31_t)0x38a91fcb, (q31_t)0x38a37d67, (q31_t)0x389ddae1, (q31_t)0x38983838, (q31_t)0x3892956c, (q31_t)0x388cf27d,
+    (q31_t)0x38874f6b, (q31_t)0x3881ac36,
+  (q31_t)0x387c08de, (q31_t)0x38766564, (q31_t)0x3870c1c6, (q31_t)0x386b1e06, (q31_t)0x38657a23, (q31_t)0x385fd61d,
+    (q31_t)0x385a31f5, (q31_t)0x38548daa,
+  (q31_t)0x384ee93b, (q31_t)0x384944ab, (q31_t)0x38439ff7, (q31_t)0x383dfb21, (q31_t)0x38385628, (q31_t)0x3832b10d,
+    (q31_t)0x382d0bce, (q31_t)0x3827666d,
+  (q31_t)0x3821c0ea, (q31_t)0x381c1b44, (q31_t)0x3816757b, (q31_t)0x3810cf90, (q31_t)0x380b2982, (q31_t)0x38058351,
+    (q31_t)0x37ffdcfe, (q31_t)0x37fa3688,
+  (q31_t)0x37f48ff0, (q31_t)0x37eee936, (q31_t)0x37e94259, (q31_t)0x37e39b59, (q31_t)0x37ddf437, (q31_t)0x37d84cf2,
+    (q31_t)0x37d2a58b, (q31_t)0x37ccfe02,
+  (q31_t)0x37c75656, (q31_t)0x37c1ae87, (q31_t)0x37bc0697, (q31_t)0x37b65e84, (q31_t)0x37b0b64e, (q31_t)0x37ab0df6,
+    (q31_t)0x37a5657c, (q31_t)0x379fbce0,
+  (q31_t)0x379a1421, (q31_t)0x37946b40, (q31_t)0x378ec23d, (q31_t)0x37891917, (q31_t)0x37836fcf, (q31_t)0x377dc665,
+    (q31_t)0x37781cd9, (q31_t)0x3772732a,
+  (q31_t)0x376cc959, (q31_t)0x37671f66, (q31_t)0x37617551, (q31_t)0x375bcb1a, (q31_t)0x375620c1, (q31_t)0x37507645,
+    (q31_t)0x374acba7, (q31_t)0x374520e7,
+  (q31_t)0x373f7606, (q31_t)0x3739cb02, (q31_t)0x37341fdc, (q31_t)0x372e7493, (q31_t)0x3728c929, (q31_t)0x37231d9d,
+    (q31_t)0x371d71ef, (q31_t)0x3717c61f,
+  (q31_t)0x37121a2d, (q31_t)0x370c6e19, (q31_t)0x3706c1e2, (q31_t)0x3701158a, (q31_t)0x36fb6910, (q31_t)0x36f5bc75,
+    (q31_t)0x36f00fb7, (q31_t)0x36ea62d7,
+  (q31_t)0x36e4b5d6, (q31_t)0x36df08b2, (q31_t)0x36d95b6d, (q31_t)0x36d3ae06, (q31_t)0x36ce007d, (q31_t)0x36c852d2,
+    (q31_t)0x36c2a506, (q31_t)0x36bcf718,
+  (q31_t)0x36b74908, (q31_t)0x36b19ad6, (q31_t)0x36abec82, (q31_t)0x36a63e0d, (q31_t)0x36a08f76, (q31_t)0x369ae0bd,
+    (q31_t)0x369531e3, (q31_t)0x368f82e7,
+  (q31_t)0x3689d3c9, (q31_t)0x3684248a, (q31_t)0x367e7529, (q31_t)0x3678c5a7, (q31_t)0x36731602, (q31_t)0x366d663d,
+    (q31_t)0x3667b655, (q31_t)0x3662064c,
+  (q31_t)0x365c5622, (q31_t)0x3656a5d6, (q31_t)0x3650f569, (q31_t)0x364b44da, (q31_t)0x36459429, (q31_t)0x363fe357,
+    (q31_t)0x363a3264, (q31_t)0x3634814f,
+  (q31_t)0x362ed019, (q31_t)0x36291ec1, (q31_t)0x36236d48, (q31_t)0x361dbbad, (q31_t)0x361809f1, (q31_t)0x36125814,
+    (q31_t)0x360ca615, (q31_t)0x3606f3f5,
+  (q31_t)0x360141b4, (q31_t)0x35fb8f52, (q31_t)0x35f5dcce, (q31_t)0x35f02a28, (q31_t)0x35ea7762, (q31_t)0x35e4c47a,
+    (q31_t)0x35df1171, (q31_t)0x35d95e47,
+  (q31_t)0x35d3aafc, (q31_t)0x35cdf78f, (q31_t)0x35c84401, (q31_t)0x35c29052, (q31_t)0x35bcdc82, (q31_t)0x35b72891,
+    (q31_t)0x35b1747e, (q31_t)0x35abc04b,
+  (q31_t)0x35a60bf6, (q31_t)0x35a05781, (q31_t)0x359aa2ea, (q31_t)0x3594ee32, (q31_t)0x358f3959, (q31_t)0x3589845f,
+    (q31_t)0x3583cf44, (q31_t)0x357e1a08,
+  (q31_t)0x357864ab, (q31_t)0x3572af2d, (q31_t)0x356cf98e, (q31_t)0x356743ce, (q31_t)0x35618ded, (q31_t)0x355bd7eb,
+    (q31_t)0x355621c9, (q31_t)0x35506b85,
+  (q31_t)0x354ab520, (q31_t)0x3544fe9b, (q31_t)0x353f47f5, (q31_t)0x3539912e, (q31_t)0x3533da46, (q31_t)0x352e233d,
+    (q31_t)0x35286c14, (q31_t)0x3522b4c9,
+  (q31_t)0x351cfd5e, (q31_t)0x351745d2, (q31_t)0x35118e26, (q31_t)0x350bd658, (q31_t)0x35061e6a, (q31_t)0x3500665c,
+    (q31_t)0x34faae2c, (q31_t)0x34f4f5dc,
+  (q31_t)0x34ef3d6b, (q31_t)0x34e984da, (q31_t)0x34e3cc28, (q31_t)0x34de1355, (q31_t)0x34d85a62, (q31_t)0x34d2a14e,
+    (q31_t)0x34cce819, (q31_t)0x34c72ec4,
+  (q31_t)0x34c1754e, (q31_t)0x34bbbbb8, (q31_t)0x34b60202, (q31_t)0x34b0482a, (q31_t)0x34aa8e33, (q31_t)0x34a4d41a,
+    (q31_t)0x349f19e2, (q31_t)0x34995f88,
+  (q31_t)0x3493a50f, (q31_t)0x348dea75, (q31_t)0x34882fba, (q31_t)0x348274e0, (q31_t)0x347cb9e4, (q31_t)0x3476fec9,
+    (q31_t)0x3471438d, (q31_t)0x346b8830,
+  (q31_t)0x3465ccb4, (q31_t)0x34601117, (q31_t)0x345a5559, (q31_t)0x3454997c, (q31_t)0x344edd7e, (q31_t)0x34492160,
+    (q31_t)0x34436521, (q31_t)0x343da8c3,
+  (q31_t)0x3437ec44, (q31_t)0x34322fa5, (q31_t)0x342c72e6, (q31_t)0x3426b606, (q31_t)0x3420f907, (q31_t)0x341b3be7,
+    (q31_t)0x34157ea7, (q31_t)0x340fc147,
+  (q31_t)0x340a03c7, (q31_t)0x34044626, (q31_t)0x33fe8866, (q31_t)0x33f8ca86, (q31_t)0x33f30c85, (q31_t)0x33ed4e65,
+    (q31_t)0x33e79024, (q31_t)0x33e1d1c4,
+  (q31_t)0x33dc1343, (q31_t)0x33d654a2, (q31_t)0x33d095e2, (q31_t)0x33cad701, (q31_t)0x33c51801, (q31_t)0x33bf58e1,
+    (q31_t)0x33b999a0, (q31_t)0x33b3da40,
+  (q31_t)0x33ae1ac0, (q31_t)0x33a85b20, (q31_t)0x33a29b60, (q31_t)0x339cdb81, (q31_t)0x33971b81, (q31_t)0x33915b62,
+    (q31_t)0x338b9b22, (q31_t)0x3385dac4,
+  (q31_t)0x33801a45, (q31_t)0x337a59a6, (q31_t)0x337498e8, (q31_t)0x336ed80a, (q31_t)0x3369170c, (q31_t)0x336355ef,
+    (q31_t)0x335d94b2, (q31_t)0x3357d355,
+  (q31_t)0x335211d8, (q31_t)0x334c503c, (q31_t)0x33468e80, (q31_t)0x3340cca5, (q31_t)0x333b0aaa, (q31_t)0x3335488f,
+    (q31_t)0x332f8655, (q31_t)0x3329c3fb,
+  (q31_t)0x33240182, (q31_t)0x331e3ee9, (q31_t)0x33187c31, (q31_t)0x3312b959, (q31_t)0x330cf661, (q31_t)0x3307334a,
+    (q31_t)0x33017014, (q31_t)0x32fbacbe,
+  (q31_t)0x32f5e948, (q31_t)0x32f025b4, (q31_t)0x32ea61ff, (q31_t)0x32e49e2c, (q31_t)0x32deda39, (q31_t)0x32d91626,
+    (q31_t)0x32d351f5, (q31_t)0x32cd8da4,
+  (q31_t)0x32c7c933, (q31_t)0x32c204a3, (q31_t)0x32bc3ff4, (q31_t)0x32b67b26, (q31_t)0x32b0b638, (q31_t)0x32aaf12b,
+    (q31_t)0x32a52bff, (q31_t)0x329f66b4,
+  (q31_t)0x3299a149, (q31_t)0x3293dbbf, (q31_t)0x328e1616, (q31_t)0x3288504e, (q31_t)0x32828a67, (q31_t)0x327cc460,
+    (q31_t)0x3276fe3a, (q31_t)0x327137f6,
+  (q31_t)0x326b7192, (q31_t)0x3265ab0f, (q31_t)0x325fe46c, (q31_t)0x325a1dab, (q31_t)0x325456cb, (q31_t)0x324e8fcc,
+    (q31_t)0x3248c8ad, (q31_t)0x32430170,
+  (q31_t)0x323d3a14, (q31_t)0x32377298, (q31_t)0x3231aafe, (q31_t)0x322be345, (q31_t)0x32261b6c, (q31_t)0x32205375,
+    (q31_t)0x321a8b5f, (q31_t)0x3214c32a,
+  (q31_t)0x320efad6, (q31_t)0x32093263, (q31_t)0x320369d2, (q31_t)0x31fda121, (q31_t)0x31f7d852, (q31_t)0x31f20f64,
+    (q31_t)0x31ec4657, (q31_t)0x31e67d2b,
+  (q31_t)0x31e0b3e0, (q31_t)0x31daea77, (q31_t)0x31d520ef, (q31_t)0x31cf5748, (q31_t)0x31c98d83, (q31_t)0x31c3c39e,
+    (q31_t)0x31bdf99b, (q31_t)0x31b82f7a,
+  (q31_t)0x31b2653a, (q31_t)0x31ac9adb, (q31_t)0x31a6d05d, (q31_t)0x31a105c1, (q31_t)0x319b3b06, (q31_t)0x3195702d,
+    (q31_t)0x318fa535, (q31_t)0x3189da1e,
+  (q31_t)0x31840ee9, (q31_t)0x317e4395, (q31_t)0x31787823, (q31_t)0x3172ac92, (q31_t)0x316ce0e3, (q31_t)0x31671515,
+    (q31_t)0x31614929, (q31_t)0x315b7d1e,
+  (q31_t)0x3155b0f5, (q31_t)0x314fe4ae, (q31_t)0x314a1848, (q31_t)0x31444bc3, (q31_t)0x313e7f21, (q31_t)0x3138b260,
+    (q31_t)0x3132e580, (q31_t)0x312d1882,
+  (q31_t)0x31274b66, (q31_t)0x31217e2c, (q31_t)0x311bb0d3, (q31_t)0x3115e35c, (q31_t)0x311015c6, (q31_t)0x310a4813,
+    (q31_t)0x31047a41, (q31_t)0x30feac51,
+  (q31_t)0x30f8de42, (q31_t)0x30f31016, (q31_t)0x30ed41cb, (q31_t)0x30e77362, (q31_t)0x30e1a4db, (q31_t)0x30dbd636,
+    (q31_t)0x30d60772, (q31_t)0x30d03891,
+  (q31_t)0x30ca6991, (q31_t)0x30c49a74, (q31_t)0x30becb38, (q31_t)0x30b8fbde, (q31_t)0x30b32c66, (q31_t)0x30ad5cd0,
+    (q31_t)0x30a78d1c, (q31_t)0x30a1bd4a,
+  (q31_t)0x309bed5a, (q31_t)0x30961d4c, (q31_t)0x30904d20, (q31_t)0x308a7cd6, (q31_t)0x3084ac6e, (q31_t)0x307edbe9,
+    (q31_t)0x30790b45, (q31_t)0x30733a83,
+  (q31_t)0x306d69a4, (q31_t)0x306798a7, (q31_t)0x3061c78b, (q31_t)0x305bf652, (q31_t)0x305624fb, (q31_t)0x30505387,
+    (q31_t)0x304a81f4, (q31_t)0x3044b044,
+  (q31_t)0x303ede76, (q31_t)0x30390c8a, (q31_t)0x30333a80, (q31_t)0x302d6859, (q31_t)0x30279614, (q31_t)0x3021c3b1,
+    (q31_t)0x301bf131, (q31_t)0x30161e93,
+  (q31_t)0x30104bd7, (q31_t)0x300a78fe, (q31_t)0x3004a607, (q31_t)0x2ffed2f2, (q31_t)0x2ff8ffc0, (q31_t)0x2ff32c70,
+    (q31_t)0x2fed5902, (q31_t)0x2fe78577,
+  (q31_t)0x2fe1b1cf, (q31_t)0x2fdbde09, (q31_t)0x2fd60a25, (q31_t)0x2fd03624, (q31_t)0x2fca6206, (q31_t)0x2fc48dc9,
+    (q31_t)0x2fbeb970, (q31_t)0x2fb8e4f9,
+  (q31_t)0x2fb31064, (q31_t)0x2fad3bb3, (q31_t)0x2fa766e3, (q31_t)0x2fa191f7, (q31_t)0x2f9bbced, (q31_t)0x2f95e7c5,
+    (q31_t)0x2f901280, (q31_t)0x2f8a3d1e,
+  (q31_t)0x2f84679f, (q31_t)0x2f7e9202, (q31_t)0x2f78bc48, (q31_t)0x2f72e671, (q31_t)0x2f6d107c, (q31_t)0x2f673a6a,
+    (q31_t)0x2f61643b, (q31_t)0x2f5b8def,
+  (q31_t)0x2f55b785, (q31_t)0x2f4fe0ff, (q31_t)0x2f4a0a5b, (q31_t)0x2f44339a, (q31_t)0x2f3e5cbb, (q31_t)0x2f3885c0,
+    (q31_t)0x2f32aea8, (q31_t)0x2f2cd772,
+  (q31_t)0x2f27001f, (q31_t)0x2f2128af, (q31_t)0x2f1b5122, (q31_t)0x2f157979, (q31_t)0x2f0fa1b2, (q31_t)0x2f09c9ce,
+    (q31_t)0x2f03f1cd, (q31_t)0x2efe19ae,
+  (q31_t)0x2ef84173, (q31_t)0x2ef2691b, (q31_t)0x2eec90a7, (q31_t)0x2ee6b815, (q31_t)0x2ee0df66, (q31_t)0x2edb069a,
+    (q31_t)0x2ed52db1, (q31_t)0x2ecf54ac,
+  (q31_t)0x2ec97b89, (q31_t)0x2ec3a24a, (q31_t)0x2ebdc8ee, (q31_t)0x2eb7ef75, (q31_t)0x2eb215df, (q31_t)0x2eac3c2d,
+    (q31_t)0x2ea6625d, (q31_t)0x2ea08871,
+  (q31_t)0x2e9aae68, (q31_t)0x2e94d443, (q31_t)0x2e8efa00, (q31_t)0x2e891fa1, (q31_t)0x2e834525, (q31_t)0x2e7d6a8d,
+    (q31_t)0x2e778fd8, (q31_t)0x2e71b506,
+  (q31_t)0x2e6bda17, (q31_t)0x2e65ff0c, (q31_t)0x2e6023e5, (q31_t)0x2e5a48a0, (q31_t)0x2e546d3f, (q31_t)0x2e4e91c2,
+    (q31_t)0x2e48b628, (q31_t)0x2e42da71,
+  (q31_t)0x2e3cfe9e, (q31_t)0x2e3722ae, (q31_t)0x2e3146a2, (q31_t)0x2e2b6a79, (q31_t)0x2e258e34, (q31_t)0x2e1fb1d3,
+    (q31_t)0x2e19d554, (q31_t)0x2e13f8ba,
+  (q31_t)0x2e0e1c03, (q31_t)0x2e083f30, (q31_t)0x2e026240, (q31_t)0x2dfc8534, (q31_t)0x2df6a80b, (q31_t)0x2df0cac6,
+    (q31_t)0x2deaed65, (q31_t)0x2de50fe8,
+  (q31_t)0x2ddf324e, (q31_t)0x2dd95498, (q31_t)0x2dd376c5, (q31_t)0x2dcd98d7, (q31_t)0x2dc7bacc, (q31_t)0x2dc1dca4,
+    (q31_t)0x2dbbfe61, (q31_t)0x2db62001,
+  (q31_t)0x2db04186, (q31_t)0x2daa62ee, (q31_t)0x2da4843a, (q31_t)0x2d9ea569, (q31_t)0x2d98c67d, (q31_t)0x2d92e774,
+    (q31_t)0x2d8d084f, (q31_t)0x2d87290f,
+  (q31_t)0x2d8149b2, (q31_t)0x2d7b6a39, (q31_t)0x2d758aa4, (q31_t)0x2d6faaf3, (q31_t)0x2d69cb26, (q31_t)0x2d63eb3d,
+    (q31_t)0x2d5e0b38, (q31_t)0x2d582b17,
+  (q31_t)0x2d524ada, (q31_t)0x2d4c6a81, (q31_t)0x2d468a0c, (q31_t)0x2d40a97b, (q31_t)0x2d3ac8ce, (q31_t)0x2d34e805,
+    (q31_t)0x2d2f0721, (q31_t)0x2d292620,
+  (q31_t)0x2d234504, (q31_t)0x2d1d63cc, (q31_t)0x2d178278, (q31_t)0x2d11a108, (q31_t)0x2d0bbf7d, (q31_t)0x2d05ddd5,
+    (q31_t)0x2cfffc12, (q31_t)0x2cfa1a33,
+  (q31_t)0x2cf43839, (q31_t)0x2cee5622, (q31_t)0x2ce873f0, (q31_t)0x2ce291a2, (q31_t)0x2cdcaf39, (q31_t)0x2cd6ccb4,
+    (q31_t)0x2cd0ea13, (q31_t)0x2ccb0756,
+  (q31_t)0x2cc5247e, (q31_t)0x2cbf418b, (q31_t)0x2cb95e7b, (q31_t)0x2cb37b51, (q31_t)0x2cad980a, (q31_t)0x2ca7b4a8,
+    (q31_t)0x2ca1d12a, (q31_t)0x2c9bed91,
+  (q31_t)0x2c9609dd, (q31_t)0x2c90260d, (q31_t)0x2c8a4221, (q31_t)0x2c845e1a, (q31_t)0x2c7e79f7, (q31_t)0x2c7895b9,
+    (q31_t)0x2c72b160, (q31_t)0x2c6ccceb,
+  (q31_t)0x2c66e85b, (q31_t)0x2c6103af, (q31_t)0x2c5b1ee8, (q31_t)0x2c553a06, (q31_t)0x2c4f5508, (q31_t)0x2c496fef,
+    (q31_t)0x2c438abb, (q31_t)0x2c3da56b,
+  (q31_t)0x2c37c000, (q31_t)0x2c31da7a, (q31_t)0x2c2bf4d8, (q31_t)0x2c260f1c, (q31_t)0x2c202944, (q31_t)0x2c1a4351,
+    (q31_t)0x2c145d42, (q31_t)0x2c0e7719,
+  (q31_t)0x2c0890d4, (q31_t)0x2c02aa74, (q31_t)0x2bfcc3f9, (q31_t)0x2bf6dd63, (q31_t)0x2bf0f6b1, (q31_t)0x2beb0fe5,
+    (q31_t)0x2be528fd, (q31_t)0x2bdf41fb,
+  (q31_t)0x2bd95add, (q31_t)0x2bd373a4, (q31_t)0x2bcd8c51, (q31_t)0x2bc7a4e2, (q31_t)0x2bc1bd58, (q31_t)0x2bbbd5b3,
+    (q31_t)0x2bb5edf4, (q31_t)0x2bb00619,
+  (q31_t)0x2baa1e23, (q31_t)0x2ba43613, (q31_t)0x2b9e4de7, (q31_t)0x2b9865a1, (q31_t)0x2b927d3f, (q31_t)0x2b8c94c3,
+    (q31_t)0x2b86ac2c, (q31_t)0x2b80c37a,
+  (q31_t)0x2b7adaae, (q31_t)0x2b74f1c6, (q31_t)0x2b6f08c4, (q31_t)0x2b691fa6, (q31_t)0x2b63366f, (q31_t)0x2b5d4d1c,
+    (q31_t)0x2b5763ae, (q31_t)0x2b517a26,
+  (q31_t)0x2b4b9083, (q31_t)0x2b45a6c6, (q31_t)0x2b3fbced, (q31_t)0x2b39d2fa, (q31_t)0x2b33e8ed, (q31_t)0x2b2dfec5,
+    (q31_t)0x2b281482, (q31_t)0x2b222a24,
+  (q31_t)0x2b1c3fac, (q31_t)0x2b165519, (q31_t)0x2b106a6c, (q31_t)0x2b0a7fa4, (q31_t)0x2b0494c2, (q31_t)0x2afea9c5,
+    (q31_t)0x2af8bead, (q31_t)0x2af2d37b,
+  (q31_t)0x2aece82f, (q31_t)0x2ae6fcc8, (q31_t)0x2ae11146, (q31_t)0x2adb25aa, (q31_t)0x2ad539f4, (q31_t)0x2acf4e23,
+    (q31_t)0x2ac96238, (q31_t)0x2ac37633,
+  (q31_t)0x2abd8a13, (q31_t)0x2ab79dd8, (q31_t)0x2ab1b184, (q31_t)0x2aabc515, (q31_t)0x2aa5d88b, (q31_t)0x2a9febe8,
+    (q31_t)0x2a99ff2a, (q31_t)0x2a941252,
+  (q31_t)0x2a8e255f, (q31_t)0x2a883853, (q31_t)0x2a824b2c, (q31_t)0x2a7c5deb, (q31_t)0x2a76708f, (q31_t)0x2a70831a,
+    (q31_t)0x2a6a958a, (q31_t)0x2a64a7e0,
+  (q31_t)0x2a5eba1c, (q31_t)0x2a58cc3e, (q31_t)0x2a52de46, (q31_t)0x2a4cf033, (q31_t)0x2a470207, (q31_t)0x2a4113c0,
+    (q31_t)0x2a3b2560, (q31_t)0x2a3536e5,
+  (q31_t)0x2a2f4850, (q31_t)0x2a2959a1, (q31_t)0x2a236ad9, (q31_t)0x2a1d7bf6, (q31_t)0x2a178cf9, (q31_t)0x2a119de2,
+    (q31_t)0x2a0baeb2, (q31_t)0x2a05bf67,
+  (q31_t)0x29ffd003, (q31_t)0x29f9e084, (q31_t)0x29f3f0ec, (q31_t)0x29ee013a, (q31_t)0x29e8116e, (q31_t)0x29e22188,
+    (q31_t)0x29dc3188, (q31_t)0x29d6416f,
+  (q31_t)0x29d0513b, (q31_t)0x29ca60ee, (q31_t)0x29c47087, (q31_t)0x29be8007, (q31_t)0x29b88f6c, (q31_t)0x29b29eb8,
+    (q31_t)0x29acadea, (q31_t)0x29a6bd02,
+  (q31_t)0x29a0cc01, (q31_t)0x299adae6, (q31_t)0x2994e9b1, (q31_t)0x298ef863, (q31_t)0x298906fb, (q31_t)0x2983157a,
+    (q31_t)0x297d23df, (q31_t)0x2977322a,
+  (q31_t)0x2971405b, (q31_t)0x296b4e74, (q31_t)0x29655c72, (q31_t)0x295f6a57, (q31_t)0x29597823, (q31_t)0x295385d5,
+    (q31_t)0x294d936d, (q31_t)0x2947a0ec,
+  (q31_t)0x2941ae52, (q31_t)0x293bbb9e, (q31_t)0x2935c8d1, (q31_t)0x292fd5ea, (q31_t)0x2929e2ea, (q31_t)0x2923efd0,
+    (q31_t)0x291dfc9d, (q31_t)0x29180951,
+  (q31_t)0x291215eb, (q31_t)0x290c226c, (q31_t)0x29062ed4, (q31_t)0x29003b23, (q31_t)0x28fa4758, (q31_t)0x28f45374,
+    (q31_t)0x28ee5f76, (q31_t)0x28e86b5f,
+  (q31_t)0x28e27730, (q31_t)0x28dc82e6, (q31_t)0x28d68e84, (q31_t)0x28d09a09, (q31_t)0x28caa574, (q31_t)0x28c4b0c6,
+    (q31_t)0x28bebbff, (q31_t)0x28b8c71f,
+  (q31_t)0x28b2d226, (q31_t)0x28acdd13, (q31_t)0x28a6e7e8, (q31_t)0x28a0f2a3, (q31_t)0x289afd46, (q31_t)0x289507cf,
+    (q31_t)0x288f123f, (q31_t)0x28891c97,
+  (q31_t)0x288326d5, (q31_t)0x287d30fa, (q31_t)0x28773b07, (q31_t)0x287144fa, (q31_t)0x286b4ed5, (q31_t)0x28655896,
+    (q31_t)0x285f623f, (q31_t)0x28596bce,
+  (q31_t)0x28537545, (q31_t)0x284d7ea3, (q31_t)0x284787e8, (q31_t)0x28419114, (q31_t)0x283b9a28, (q31_t)0x2835a322,
+    (q31_t)0x282fac04, (q31_t)0x2829b4cd,
+  (q31_t)0x2823bd7d, (q31_t)0x281dc615, (q31_t)0x2817ce93, (q31_t)0x2811d6f9, (q31_t)0x280bdf46, (q31_t)0x2805e77b,
+    (q31_t)0x27ffef97, (q31_t)0x27f9f79a,
+  (q31_t)0x27f3ff85, (q31_t)0x27ee0756, (q31_t)0x27e80f10, (q31_t)0x27e216b0, (q31_t)0x27dc1e38, (q31_t)0x27d625a8,
+    (q31_t)0x27d02cff, (q31_t)0x27ca343d,
+  (q31_t)0x27c43b63, (q31_t)0x27be4270, (q31_t)0x27b84965, (q31_t)0x27b25041, (q31_t)0x27ac5705, (q31_t)0x27a65db0,
+    (q31_t)0x27a06443, (q31_t)0x279a6abd,
+  (q31_t)0x2794711f, (q31_t)0x278e7768, (q31_t)0x27887d99, (q31_t)0x278283b2, (q31_t)0x277c89b3, (q31_t)0x27768f9b,
+    (q31_t)0x2770956a, (q31_t)0x276a9b21,
+  (q31_t)0x2764a0c0, (q31_t)0x275ea647, (q31_t)0x2758abb6, (q31_t)0x2752b10c, (q31_t)0x274cb64a, (q31_t)0x2746bb6f,
+    (q31_t)0x2740c07d, (q31_t)0x273ac572,
+  (q31_t)0x2734ca4f, (q31_t)0x272ecf14, (q31_t)0x2728d3c0, (q31_t)0x2722d855, (q31_t)0x271cdcd1, (q31_t)0x2716e136,
+    (q31_t)0x2710e582, (q31_t)0x270ae9b6,
+  (q31_t)0x2704edd2, (q31_t)0x26fef1d5, (q31_t)0x26f8f5c1, (q31_t)0x26f2f995, (q31_t)0x26ecfd51, (q31_t)0x26e700f5,
+    (q31_t)0x26e10480, (q31_t)0x26db07f4,
+  (q31_t)0x26d50b50, (q31_t)0x26cf0e94, (q31_t)0x26c911c0, (q31_t)0x26c314d4, (q31_t)0x26bd17d0, (q31_t)0x26b71ab4,
+    (q31_t)0x26b11d80, (q31_t)0x26ab2034,
+  (q31_t)0x26a522d1, (q31_t)0x269f2556, (q31_t)0x269927c3, (q31_t)0x26932a18, (q31_t)0x268d2c55, (q31_t)0x26872e7b,
+    (q31_t)0x26813088, (q31_t)0x267b327e,
+  (q31_t)0x2675345d, (q31_t)0x266f3623, (q31_t)0x266937d2, (q31_t)0x26633969, (q31_t)0x265d3ae9, (q31_t)0x26573c50,
+    (q31_t)0x26513da1, (q31_t)0x264b3ed9,
+  (q31_t)0x26453ffa, (q31_t)0x263f4103, (q31_t)0x263941f5, (q31_t)0x263342cf, (q31_t)0x262d4392, (q31_t)0x2627443d,
+    (q31_t)0x262144d0, (q31_t)0x261b454c,
+  (q31_t)0x261545b0, (q31_t)0x260f45fd, (q31_t)0x26094633, (q31_t)0x26034651, (q31_t)0x25fd4657, (q31_t)0x25f74646,
+    (q31_t)0x25f1461e, (q31_t)0x25eb45de,
+  (q31_t)0x25e54587, (q31_t)0x25df4519, (q31_t)0x25d94493, (q31_t)0x25d343f6, (q31_t)0x25cd4341, (q31_t)0x25c74276,
+    (q31_t)0x25c14192, (q31_t)0x25bb4098,
+  (q31_t)0x25b53f86, (q31_t)0x25af3e5d, (q31_t)0x25a93d1d, (q31_t)0x25a33bc6, (q31_t)0x259d3a57, (q31_t)0x259738d1,
+    (q31_t)0x25913734, (q31_t)0x258b3580,
+  (q31_t)0x258533b5, (q31_t)0x257f31d2, (q31_t)0x25792fd8, (q31_t)0x25732dc8, (q31_t)0x256d2ba0, (q31_t)0x25672961,
+    (q31_t)0x2561270b, (q31_t)0x255b249e,
+  (q31_t)0x2555221a, (q31_t)0x254f1f7e, (q31_t)0x25491ccc, (q31_t)0x25431a03, (q31_t)0x253d1723, (q31_t)0x2537142c,
+    (q31_t)0x2531111e, (q31_t)0x252b0df9,
+  (q31_t)0x25250abd, (q31_t)0x251f076a, (q31_t)0x25190400, (q31_t)0x25130080, (q31_t)0x250cfce8, (q31_t)0x2506f93a,
+    (q31_t)0x2500f574, (q31_t)0x24faf198,
+  (q31_t)0x24f4eda6, (q31_t)0x24eee99c, (q31_t)0x24e8e57c, (q31_t)0x24e2e144, (q31_t)0x24dcdcf6, (q31_t)0x24d6d892,
+    (q31_t)0x24d0d416, (q31_t)0x24cacf84,
+  (q31_t)0x24c4cadb, (q31_t)0x24bec61c, (q31_t)0x24b8c146, (q31_t)0x24b2bc59, (q31_t)0x24acb756, (q31_t)0x24a6b23b,
+    (q31_t)0x24a0ad0b, (q31_t)0x249aa7c4,
+  (q31_t)0x2494a266, (q31_t)0x248e9cf1, (q31_t)0x24889766, (q31_t)0x248291c5, (q31_t)0x247c8c0d, (q31_t)0x2476863e,
+    (q31_t)0x24708059, (q31_t)0x246a7a5e,
+  (q31_t)0x2464744c, (q31_t)0x245e6e23, (q31_t)0x245867e4, (q31_t)0x2452618f, (q31_t)0x244c5b24, (q31_t)0x244654a1,
+    (q31_t)0x24404e09, (q31_t)0x243a475a,
+  (q31_t)0x24344095, (q31_t)0x242e39ba, (q31_t)0x242832c8, (q31_t)0x24222bc0, (q31_t)0x241c24a1, (q31_t)0x24161d6d,
+    (q31_t)0x24101622, (q31_t)0x240a0ec1,
+  (q31_t)0x24040749, (q31_t)0x23fdffbc, (q31_t)0x23f7f818, (q31_t)0x23f1f05e, (q31_t)0x23ebe88e, (q31_t)0x23e5e0a7,
+    (q31_t)0x23dfd8ab, (q31_t)0x23d9d098,
+  (q31_t)0x23d3c86f, (q31_t)0x23cdc031, (q31_t)0x23c7b7dc, (q31_t)0x23c1af71, (q31_t)0x23bba6f0, (q31_t)0x23b59e59,
+    (q31_t)0x23af95ac, (q31_t)0x23a98ce8,
+  (q31_t)0x23a3840f, (q31_t)0x239d7b20, (q31_t)0x2397721b, (q31_t)0x23916900, (q31_t)0x238b5fcf, (q31_t)0x23855688,
+    (q31_t)0x237f4d2b, (q31_t)0x237943b9,
+  (q31_t)0x23733a30, (q31_t)0x236d3092, (q31_t)0x236726dd, (q31_t)0x23611d13, (q31_t)0x235b1333, (q31_t)0x2355093e,
+    (q31_t)0x234eff32, (q31_t)0x2348f511,
+  (q31_t)0x2342eada, (q31_t)0x233ce08d, (q31_t)0x2336d62a, (q31_t)0x2330cbb2, (q31_t)0x232ac124, (q31_t)0x2324b680,
+    (q31_t)0x231eabc7, (q31_t)0x2318a0f8,
+  (q31_t)0x23129613, (q31_t)0x230c8b19, (q31_t)0x23068009, (q31_t)0x230074e3, (q31_t)0x22fa69a8, (q31_t)0x22f45e57,
+    (q31_t)0x22ee52f1, (q31_t)0x22e84775,
+  (q31_t)0x22e23be4, (q31_t)0x22dc303d, (q31_t)0x22d62480, (q31_t)0x22d018ae, (q31_t)0x22ca0cc7, (q31_t)0x22c400ca,
+    (q31_t)0x22bdf4b8, (q31_t)0x22b7e890,
+  (q31_t)0x22b1dc53, (q31_t)0x22abd001, (q31_t)0x22a5c399, (q31_t)0x229fb71b, (q31_t)0x2299aa89, (q31_t)0x22939de1,
+    (q31_t)0x228d9123, (q31_t)0x22878451,
+  (q31_t)0x22817769, (q31_t)0x227b6a6c, (q31_t)0x22755d59, (q31_t)0x226f5032, (q31_t)0x226942f5, (q31_t)0x226335a2,
+    (q31_t)0x225d283b, (q31_t)0x22571abe,
+  (q31_t)0x22510d2d, (q31_t)0x224aff86, (q31_t)0x2244f1c9, (q31_t)0x223ee3f8, (q31_t)0x2238d612, (q31_t)0x2232c816,
+    (q31_t)0x222cba06, (q31_t)0x2226abe0,
+  (q31_t)0x22209da5, (q31_t)0x221a8f56, (q31_t)0x221480f1, (q31_t)0x220e7277, (q31_t)0x220863e8, (q31_t)0x22025544,
+    (q31_t)0x21fc468b, (q31_t)0x21f637be,
+  (q31_t)0x21f028db, (q31_t)0x21ea19e3, (q31_t)0x21e40ad7, (q31_t)0x21ddfbb5, (q31_t)0x21d7ec7f, (q31_t)0x21d1dd34,
+    (q31_t)0x21cbcdd3, (q31_t)0x21c5be5e,
+  (q31_t)0x21bfaed5, (q31_t)0x21b99f36, (q31_t)0x21b38f83, (q31_t)0x21ad7fba, (q31_t)0x21a76fdd, (q31_t)0x21a15fec,
+    (q31_t)0x219b4fe5, (q31_t)0x21953fca,
+  (q31_t)0x218f2f9a, (q31_t)0x21891f55, (q31_t)0x21830efc, (q31_t)0x217cfe8e, (q31_t)0x2176ee0b, (q31_t)0x2170dd74,
+    (q31_t)0x216accc8, (q31_t)0x2164bc08,
+  (q31_t)0x215eab33, (q31_t)0x21589a49, (q31_t)0x2152894b, (q31_t)0x214c7838, (q31_t)0x21466710, (q31_t)0x214055d4,
+    (q31_t)0x213a4484, (q31_t)0x2134331f,
+  (q31_t)0x212e21a6, (q31_t)0x21281018, (q31_t)0x2121fe76, (q31_t)0x211becbf, (q31_t)0x2115daf4, (q31_t)0x210fc914,
+    (q31_t)0x2109b720, (q31_t)0x2103a518,
+  (q31_t)0x20fd92fb, (q31_t)0x20f780ca, (q31_t)0x20f16e84, (q31_t)0x20eb5c2b, (q31_t)0x20e549bd, (q31_t)0x20df373a,
+    (q31_t)0x20d924a4, (q31_t)0x20d311f9,
+  (q31_t)0x20ccff3a, (q31_t)0x20c6ec66, (q31_t)0x20c0d97f, (q31_t)0x20bac683, (q31_t)0x20b4b373, (q31_t)0x20aea04f,
+    (q31_t)0x20a88d17, (q31_t)0x20a279ca,
+  (q31_t)0x209c666a, (q31_t)0x209652f5, (q31_t)0x20903f6c, (q31_t)0x208a2bcf, (q31_t)0x2084181e, (q31_t)0x207e0459,
+    (q31_t)0x2077f080, (q31_t)0x2071dc93,
+  (q31_t)0x206bc892, (q31_t)0x2065b47d, (q31_t)0x205fa054, (q31_t)0x20598c17, (q31_t)0x205377c6, (q31_t)0x204d6361,
+    (q31_t)0x20474ee8, (q31_t)0x20413a5b,
+  (q31_t)0x203b25bb, (q31_t)0x20351106, (q31_t)0x202efc3e, (q31_t)0x2028e761, (q31_t)0x2022d271, (q31_t)0x201cbd6d,
+    (q31_t)0x2016a856, (q31_t)0x2010932a,
+  (q31_t)0x200a7deb, (q31_t)0x20046898, (q31_t)0x1ffe5331, (q31_t)0x1ff83db6, (q31_t)0x1ff22828, (q31_t)0x1fec1286,
+    (q31_t)0x1fe5fcd0, (q31_t)0x1fdfe707,
+  (q31_t)0x1fd9d12a, (q31_t)0x1fd3bb39, (q31_t)0x1fcda535, (q31_t)0x1fc78f1d, (q31_t)0x1fc178f1, (q31_t)0x1fbb62b2,
+    (q31_t)0x1fb54c60, (q31_t)0x1faf35f9,
+  (q31_t)0x1fa91f80, (q31_t)0x1fa308f2, (q31_t)0x1f9cf252, (q31_t)0x1f96db9d, (q31_t)0x1f90c4d5, (q31_t)0x1f8aadfa,
+    (q31_t)0x1f84970b, (q31_t)0x1f7e8009,
+  (q31_t)0x1f7868f4, (q31_t)0x1f7251ca, (q31_t)0x1f6c3a8e, (q31_t)0x1f66233e, (q31_t)0x1f600bdb, (q31_t)0x1f59f465,
+    (q31_t)0x1f53dcdb, (q31_t)0x1f4dc53d,
+  (q31_t)0x1f47ad8d, (q31_t)0x1f4195c9, (q31_t)0x1f3b7df2, (q31_t)0x1f356608, (q31_t)0x1f2f4e0a, (q31_t)0x1f2935f9,
+    (q31_t)0x1f231dd5, (q31_t)0x1f1d059e,
+  (q31_t)0x1f16ed54, (q31_t)0x1f10d4f6, (q31_t)0x1f0abc85, (q31_t)0x1f04a401, (q31_t)0x1efe8b6a, (q31_t)0x1ef872c0,
+    (q31_t)0x1ef25a03, (q31_t)0x1eec4132,
+  (q31_t)0x1ee6284f, (q31_t)0x1ee00f58, (q31_t)0x1ed9f64f, (q31_t)0x1ed3dd32, (q31_t)0x1ecdc402, (q31_t)0x1ec7aac0,
+    (q31_t)0x1ec1916a, (q31_t)0x1ebb7802,
+  (q31_t)0x1eb55e86, (q31_t)0x1eaf44f8, (q31_t)0x1ea92b56, (q31_t)0x1ea311a2, (q31_t)0x1e9cf7db, (q31_t)0x1e96de01,
+    (q31_t)0x1e90c414, (q31_t)0x1e8aaa14,
+  (q31_t)0x1e849001, (q31_t)0x1e7e75dc, (q31_t)0x1e785ba3, (q31_t)0x1e724158, (q31_t)0x1e6c26fa, (q31_t)0x1e660c8a,
+    (q31_t)0x1e5ff206, (q31_t)0x1e59d770,
+  (q31_t)0x1e53bcc7, (q31_t)0x1e4da20c, (q31_t)0x1e47873d, (q31_t)0x1e416c5d, (q31_t)0x1e3b5169, (q31_t)0x1e353663,
+    (q31_t)0x1e2f1b4a, (q31_t)0x1e29001e,
+  (q31_t)0x1e22e4e0, (q31_t)0x1e1cc990, (q31_t)0x1e16ae2c, (q31_t)0x1e1092b6, (q31_t)0x1e0a772e, (q31_t)0x1e045b93,
+    (q31_t)0x1dfe3fe6, (q31_t)0x1df82426,
+  (q31_t)0x1df20853, (q31_t)0x1debec6f, (q31_t)0x1de5d077, (q31_t)0x1ddfb46e, (q31_t)0x1dd99851, (q31_t)0x1dd37c23,
+    (q31_t)0x1dcd5fe2, (q31_t)0x1dc7438e,
+  (q31_t)0x1dc12729, (q31_t)0x1dbb0ab0, (q31_t)0x1db4ee26, (q31_t)0x1daed189, (q31_t)0x1da8b4da, (q31_t)0x1da29819,
+    (q31_t)0x1d9c7b45, (q31_t)0x1d965e5f,
+  (q31_t)0x1d904167, (q31_t)0x1d8a245c, (q31_t)0x1d840740, (q31_t)0x1d7dea11, (q31_t)0x1d77ccd0, (q31_t)0x1d71af7d,
+    (q31_t)0x1d6b9217, (q31_t)0x1d6574a0,
+  (q31_t)0x1d5f5716, (q31_t)0x1d59397a, (q31_t)0x1d531bcc, (q31_t)0x1d4cfe0d, (q31_t)0x1d46e03a, (q31_t)0x1d40c256,
+    (q31_t)0x1d3aa460, (q31_t)0x1d348658,
+  (q31_t)0x1d2e683e, (q31_t)0x1d284a12, (q31_t)0x1d222bd3, (q31_t)0x1d1c0d83, (q31_t)0x1d15ef21, (q31_t)0x1d0fd0ad,
+    (q31_t)0x1d09b227, (q31_t)0x1d03938f,
+  (q31_t)0x1cfd74e5, (q31_t)0x1cf7562a, (q31_t)0x1cf1375c, (q31_t)0x1ceb187d, (q31_t)0x1ce4f98c, (q31_t)0x1cdeda89,
+    (q31_t)0x1cd8bb74, (q31_t)0x1cd29c4d,
+  (q31_t)0x1ccc7d15, (q31_t)0x1cc65dca, (q31_t)0x1cc03e6e, (q31_t)0x1cba1f01, (q31_t)0x1cb3ff81, (q31_t)0x1caddff0,
+    (q31_t)0x1ca7c04d, (q31_t)0x1ca1a099,
+  (q31_t)0x1c9b80d3, (q31_t)0x1c9560fb, (q31_t)0x1c8f4112, (q31_t)0x1c892117, (q31_t)0x1c83010a, (q31_t)0x1c7ce0ec,
+    (q31_t)0x1c76c0bc, (q31_t)0x1c70a07b,
+  (q31_t)0x1c6a8028, (q31_t)0x1c645fc3, (q31_t)0x1c5e3f4d, (q31_t)0x1c581ec6, (q31_t)0x1c51fe2d, (q31_t)0x1c4bdd83,
+    (q31_t)0x1c45bcc7, (q31_t)0x1c3f9bf9,
+  (q31_t)0x1c397b1b, (q31_t)0x1c335a2b, (q31_t)0x1c2d3929, (q31_t)0x1c271816, (q31_t)0x1c20f6f2, (q31_t)0x1c1ad5bc,
+    (q31_t)0x1c14b475, (q31_t)0x1c0e931d,
+  (q31_t)0x1c0871b4, (q31_t)0x1c025039, (q31_t)0x1bfc2ead, (q31_t)0x1bf60d0f, (q31_t)0x1befeb60, (q31_t)0x1be9c9a1,
+    (q31_t)0x1be3a7cf, (q31_t)0x1bdd85ed,
+  (q31_t)0x1bd763fa, (q31_t)0x1bd141f5, (q31_t)0x1bcb1fdf, (q31_t)0x1bc4fdb8, (q31_t)0x1bbedb80, (q31_t)0x1bb8b937,
+    (q31_t)0x1bb296dc, (q31_t)0x1bac7471,
+  (q31_t)0x1ba651f5, (q31_t)0x1ba02f67, (q31_t)0x1b9a0cc8, (q31_t)0x1b93ea19, (q31_t)0x1b8dc758, (q31_t)0x1b87a487,
+    (q31_t)0x1b8181a4, (q31_t)0x1b7b5eb0,
+  (q31_t)0x1b753bac, (q31_t)0x1b6f1897, (q31_t)0x1b68f570, (q31_t)0x1b62d239, (q31_t)0x1b5caef1, (q31_t)0x1b568b98,
+    (q31_t)0x1b50682e, (q31_t)0x1b4a44b3,
+  (q31_t)0x1b442127, (q31_t)0x1b3dfd8b, (q31_t)0x1b37d9de, (q31_t)0x1b31b620, (q31_t)0x1b2b9251, (q31_t)0x1b256e71,
+    (q31_t)0x1b1f4a81, (q31_t)0x1b192680,
+  (q31_t)0x1b13026e, (q31_t)0x1b0cde4c, (q31_t)0x1b06ba19, (q31_t)0x1b0095d5, (q31_t)0x1afa7180, (q31_t)0x1af44d1b,
+    (q31_t)0x1aee28a6, (q31_t)0x1ae8041f,
+  (q31_t)0x1ae1df88, (q31_t)0x1adbbae1, (q31_t)0x1ad59629, (q31_t)0x1acf7160, (q31_t)0x1ac94c87, (q31_t)0x1ac3279d,
+    (q31_t)0x1abd02a3, (q31_t)0x1ab6dd98,
+  (q31_t)0x1ab0b87d, (q31_t)0x1aaa9352, (q31_t)0x1aa46e16, (q31_t)0x1a9e48c9, (q31_t)0x1a98236c, (q31_t)0x1a91fdff,
+    (q31_t)0x1a8bd881, (q31_t)0x1a85b2f3,
+  (q31_t)0x1a7f8d54, (q31_t)0x1a7967a6, (q31_t)0x1a7341e6, (q31_t)0x1a6d1c17, (q31_t)0x1a66f637, (q31_t)0x1a60d047,
+    (q31_t)0x1a5aaa47, (q31_t)0x1a548436,
+  (q31_t)0x1a4e5e15, (q31_t)0x1a4837e4, (q31_t)0x1a4211a3, (q31_t)0x1a3beb52, (q31_t)0x1a35c4f0, (q31_t)0x1a2f9e7e,
+    (q31_t)0x1a2977fc, (q31_t)0x1a23516a,
+  (q31_t)0x1a1d2ac8, (q31_t)0x1a170416, (q31_t)0x1a10dd53, (q31_t)0x1a0ab681, (q31_t)0x1a048f9e, (q31_t)0x19fe68ac,
+    (q31_t)0x19f841a9, (q31_t)0x19f21a96,
+  (q31_t)0x19ebf374, (q31_t)0x19e5cc41, (q31_t)0x19dfa4fe, (q31_t)0x19d97dac, (q31_t)0x19d35649, (q31_t)0x19cd2ed7,
+    (q31_t)0x19c70754, (q31_t)0x19c0dfc2,
+  (q31_t)0x19bab820, (q31_t)0x19b4906e, (q31_t)0x19ae68ac, (q31_t)0x19a840da, (q31_t)0x19a218f9, (q31_t)0x199bf107,
+    (q31_t)0x1995c906, (q31_t)0x198fa0f5,
+  (q31_t)0x198978d4, (q31_t)0x198350a4, (q31_t)0x197d2864, (q31_t)0x19770014, (q31_t)0x1970d7b4, (q31_t)0x196aaf45,
+    (q31_t)0x196486c6, (q31_t)0x195e5e37,
+  (q31_t)0x19583599, (q31_t)0x19520ceb, (q31_t)0x194be42d, (q31_t)0x1945bb60, (q31_t)0x193f9283, (q31_t)0x19396997,
+    (q31_t)0x1933409b, (q31_t)0x192d178f,
+  (q31_t)0x1926ee74, (q31_t)0x1920c54a, (q31_t)0x191a9c10, (q31_t)0x191472c6, (q31_t)0x190e496d, (q31_t)0x19082005,
+    (q31_t)0x1901f68d, (q31_t)0x18fbcd06,
+  (q31_t)0x18f5a36f, (q31_t)0x18ef79c9, (q31_t)0x18e95014, (q31_t)0x18e3264f, (q31_t)0x18dcfc7b, (q31_t)0x18d6d297,
+    (q31_t)0x18d0a8a4, (q31_t)0x18ca7ea2,
+  (q31_t)0x18c45491, (q31_t)0x18be2a70, (q31_t)0x18b80040, (q31_t)0x18b1d601, (q31_t)0x18ababb2, (q31_t)0x18a58154,
+    (q31_t)0x189f56e8, (q31_t)0x18992c6b,
+  (q31_t)0x189301e0, (q31_t)0x188cd746, (q31_t)0x1886ac9c, (q31_t)0x188081e4, (q31_t)0x187a571c, (q31_t)0x18742c45,
+    (q31_t)0x186e015f, (q31_t)0x1867d66a,
+  (q31_t)0x1861ab66, (q31_t)0x185b8053, (q31_t)0x18555530, (q31_t)0x184f29ff, (q31_t)0x1848febf, (q31_t)0x1842d370,
+    (q31_t)0x183ca812, (q31_t)0x18367ca5,
+  (q31_t)0x18305129, (q31_t)0x182a259e, (q31_t)0x1823fa04, (q31_t)0x181dce5b, (q31_t)0x1817a2a4, (q31_t)0x181176dd,
+    (q31_t)0x180b4b08, (q31_t)0x18051f24,
+  (q31_t)0x17fef331, (q31_t)0x17f8c72f, (q31_t)0x17f29b1e, (q31_t)0x17ec6eff, (q31_t)0x17e642d1, (q31_t)0x17e01694,
+    (q31_t)0x17d9ea49, (q31_t)0x17d3bdee,
+  (q31_t)0x17cd9186, (q31_t)0x17c7650e, (q31_t)0x17c13888, (q31_t)0x17bb0bf3, (q31_t)0x17b4df4f, (q31_t)0x17aeb29d,
+    (q31_t)0x17a885dc, (q31_t)0x17a2590d,
+  (q31_t)0x179c2c2f, (q31_t)0x1795ff42, (q31_t)0x178fd247, (q31_t)0x1789a53d, (q31_t)0x17837825, (q31_t)0x177d4afe,
+    (q31_t)0x17771dc9, (q31_t)0x1770f086,
+  (q31_t)0x176ac333, (q31_t)0x176495d3, (q31_t)0x175e6864, (q31_t)0x17583ae7, (q31_t)0x17520d5b, (q31_t)0x174bdfc1,
+    (q31_t)0x1745b218, (q31_t)0x173f8461,
+  (q31_t)0x1739569c, (q31_t)0x173328c8, (q31_t)0x172cfae6, (q31_t)0x1726ccf6, (q31_t)0x17209ef8, (q31_t)0x171a70eb,
+    (q31_t)0x171442d0, (q31_t)0x170e14a7,
+  (q31_t)0x1707e670, (q31_t)0x1701b82a, (q31_t)0x16fb89d6, (q31_t)0x16f55b74, (q31_t)0x16ef2d04, (q31_t)0x16e8fe86,
+    (q31_t)0x16e2cff9, (q31_t)0x16dca15f,
+  (q31_t)0x16d672b6, (q31_t)0x16d043ff, (q31_t)0x16ca153a, (q31_t)0x16c3e667, (q31_t)0x16bdb787, (q31_t)0x16b78898,
+    (q31_t)0x16b1599b, (q31_t)0x16ab2a90,
+  (q31_t)0x16a4fb77, (q31_t)0x169ecc50, (q31_t)0x16989d1b, (q31_t)0x16926dd8, (q31_t)0x168c3e87, (q31_t)0x16860f29,
+    (q31_t)0x167fdfbc, (q31_t)0x1679b042,
+  (q31_t)0x167380ba, (q31_t)0x166d5123, (q31_t)0x1667217f, (q31_t)0x1660f1ce, (q31_t)0x165ac20e, (q31_t)0x16549241,
+    (q31_t)0x164e6266, (q31_t)0x1648327d,
+  (q31_t)0x16420286, (q31_t)0x163bd282, (q31_t)0x1635a270, (q31_t)0x162f7250, (q31_t)0x16294222, (q31_t)0x162311e7,
+    (q31_t)0x161ce19e, (q31_t)0x1616b148,
+  (q31_t)0x161080e4, (q31_t)0x160a5072, (q31_t)0x16041ff3, (q31_t)0x15fdef66, (q31_t)0x15f7becc, (q31_t)0x15f18e24,
+    (q31_t)0x15eb5d6e, (q31_t)0x15e52cab,
+  (q31_t)0x15defbdb, (q31_t)0x15d8cafd, (q31_t)0x15d29a11, (q31_t)0x15cc6918, (q31_t)0x15c63812, (q31_t)0x15c006fe,
+    (q31_t)0x15b9d5dd, (q31_t)0x15b3a4ae,
+  (q31_t)0x15ad7372, (q31_t)0x15a74228, (q31_t)0x15a110d2, (q31_t)0x159adf6e, (q31_t)0x1594adfc, (q31_t)0x158e7c7d,
+    (q31_t)0x15884af1, (q31_t)0x15821958,
+  (q31_t)0x157be7b1, (q31_t)0x1575b5fe, (q31_t)0x156f843c, (q31_t)0x1569526e, (q31_t)0x15632093, (q31_t)0x155ceeaa,
+    (q31_t)0x1556bcb4, (q31_t)0x15508ab1,
+  (q31_t)0x154a58a1, (q31_t)0x15442683, (q31_t)0x153df459, (q31_t)0x1537c221, (q31_t)0x15318fdd, (q31_t)0x152b5d8b,
+    (q31_t)0x15252b2c, (q31_t)0x151ef8c0,
+  (q31_t)0x1518c648, (q31_t)0x151293c2, (q31_t)0x150c612f, (q31_t)0x15062e8f, (q31_t)0x14fffbe2, (q31_t)0x14f9c928,
+    (q31_t)0x14f39662, (q31_t)0x14ed638e,
+  (q31_t)0x14e730ae, (q31_t)0x14e0fdc0, (q31_t)0x14dacac6, (q31_t)0x14d497bf, (q31_t)0x14ce64ab, (q31_t)0x14c8318a,
+    (q31_t)0x14c1fe5c, (q31_t)0x14bbcb22,
+  (q31_t)0x14b597da, (q31_t)0x14af6486, (q31_t)0x14a93125, (q31_t)0x14a2fdb8, (q31_t)0x149cca3e, (q31_t)0x149696b7,
+    (q31_t)0x14906323, (q31_t)0x148a2f82,
+  (q31_t)0x1483fbd5, (q31_t)0x147dc81c, (q31_t)0x14779455, (q31_t)0x14716082, (q31_t)0x146b2ca3, (q31_t)0x1464f8b7,
+    (q31_t)0x145ec4be, (q31_t)0x145890b9,
+  (q31_t)0x14525ca7, (q31_t)0x144c2888, (q31_t)0x1445f45d, (q31_t)0x143fc026, (q31_t)0x14398be2, (q31_t)0x14335792,
+    (q31_t)0x142d2335, (q31_t)0x1426eecb,
+  (q31_t)0x1420ba56, (q31_t)0x141a85d3, (q31_t)0x14145145, (q31_t)0x140e1caa, (q31_t)0x1407e803, (q31_t)0x1401b34f,
+    (q31_t)0x13fb7e8f, (q31_t)0x13f549c3,
+  (q31_t)0x13ef14ea, (q31_t)0x13e8e005, (q31_t)0x13e2ab14, (q31_t)0x13dc7616, (q31_t)0x13d6410d, (q31_t)0x13d00bf7,
+    (q31_t)0x13c9d6d4, (q31_t)0x13c3a1a6,
+  (q31_t)0x13bd6c6b, (q31_t)0x13b73725, (q31_t)0x13b101d2, (q31_t)0x13aacc73, (q31_t)0x13a49707, (q31_t)0x139e6190,
+    (q31_t)0x13982c0d, (q31_t)0x1391f67d,
+  (q31_t)0x138bc0e1, (q31_t)0x13858b3a, (q31_t)0x137f5586, (q31_t)0x13791fc6, (q31_t)0x1372e9fb, (q31_t)0x136cb423,
+    (q31_t)0x13667e3f, (q31_t)0x13604850,
+  (q31_t)0x135a1254, (q31_t)0x1353dc4c, (q31_t)0x134da639, (q31_t)0x1347701a, (q31_t)0x134139ee, (q31_t)0x133b03b7,
+    (q31_t)0x1334cd74, (q31_t)0x132e9725,
+  (q31_t)0x132860ca, (q31_t)0x13222a64, (q31_t)0x131bf3f2, (q31_t)0x1315bd73, (q31_t)0x130f86ea, (q31_t)0x13095054,
+    (q31_t)0x130319b3, (q31_t)0x12fce305,
+  (q31_t)0x12f6ac4d, (q31_t)0x12f07588, (q31_t)0x12ea3eb8, (q31_t)0x12e407dc, (q31_t)0x12ddd0f4, (q31_t)0x12d79a01,
+    (q31_t)0x12d16303, (q31_t)0x12cb2bf8,
+  (q31_t)0x12c4f4e2, (q31_t)0x12bebdc1, (q31_t)0x12b88693, (q31_t)0x12b24f5b, (q31_t)0x12ac1817, (q31_t)0x12a5e0c7,
+    (q31_t)0x129fa96c, (q31_t)0x12997205,
+  (q31_t)0x12933a93, (q31_t)0x128d0315, (q31_t)0x1286cb8c, (q31_t)0x128093f7, (q31_t)0x127a5c57, (q31_t)0x127424ac,
+    (q31_t)0x126decf5, (q31_t)0x1267b533,
+  (q31_t)0x12617d66, (q31_t)0x125b458d, (q31_t)0x12550da9, (q31_t)0x124ed5ba, (q31_t)0x12489dbf, (q31_t)0x124265b9,
+    (q31_t)0x123c2da8, (q31_t)0x1235f58b,
+  (q31_t)0x122fbd63, (q31_t)0x12298530, (q31_t)0x12234cf2, (q31_t)0x121d14a9, (q31_t)0x1216dc54, (q31_t)0x1210a3f5,
+    (q31_t)0x120a6b8a, (q31_t)0x12043314,
+  (q31_t)0x11fdfa93, (q31_t)0x11f7c207, (q31_t)0x11f18970, (q31_t)0x11eb50cd, (q31_t)0x11e51820, (q31_t)0x11dedf68,
+    (q31_t)0x11d8a6a4, (q31_t)0x11d26dd6,
+  (q31_t)0x11cc34fc, (q31_t)0x11c5fc18, (q31_t)0x11bfc329, (q31_t)0x11b98a2e, (q31_t)0x11b35129, (q31_t)0x11ad1819,
+    (q31_t)0x11a6defe, (q31_t)0x11a0a5d8,
+  (q31_t)0x119a6ca7, (q31_t)0x1194336b, (q31_t)0x118dfa25, (q31_t)0x1187c0d3, (q31_t)0x11818777, (q31_t)0x117b4e10,
+    (q31_t)0x1175149e, (q31_t)0x116edb22,
+  (q31_t)0x1168a19b, (q31_t)0x11626809, (q31_t)0x115c2e6c, (q31_t)0x1155f4c4, (q31_t)0x114fbb12, (q31_t)0x11498156,
+    (q31_t)0x1143478e, (q31_t)0x113d0dbc,
+  (q31_t)0x1136d3df, (q31_t)0x113099f8, (q31_t)0x112a6006, (q31_t)0x11242609, (q31_t)0x111dec02, (q31_t)0x1117b1f0,
+    (q31_t)0x111177d4, (q31_t)0x110b3dad,
+  (q31_t)0x1105037c, (q31_t)0x10fec940, (q31_t)0x10f88efa, (q31_t)0x10f254a9, (q31_t)0x10ec1a4e, (q31_t)0x10e5dfe8,
+    (q31_t)0x10dfa578, (q31_t)0x10d96afe,
+  (q31_t)0x10d33079, (q31_t)0x10ccf5ea, (q31_t)0x10c6bb50, (q31_t)0x10c080ac, (q31_t)0x10ba45fe, (q31_t)0x10b40b45,
+    (q31_t)0x10add082, (q31_t)0x10a795b5,
+  (q31_t)0x10a15ade, (q31_t)0x109b1ffc, (q31_t)0x1094e510, (q31_t)0x108eaa1a, (q31_t)0x10886f19, (q31_t)0x1082340f,
+    (q31_t)0x107bf8fa, (q31_t)0x1075bddb,
+  (q31_t)0x106f82b2, (q31_t)0x1069477f, (q31_t)0x10630c41, (q31_t)0x105cd0fa, (q31_t)0x105695a8, (q31_t)0x10505a4d,
+    (q31_t)0x104a1ee7, (q31_t)0x1043e377,
+  (q31_t)0x103da7fd, (q31_t)0x10376c79, (q31_t)0x103130ec, (q31_t)0x102af554, (q31_t)0x1024b9b2, (q31_t)0x101e7e06,
+    (q31_t)0x10184251, (q31_t)0x10120691,
+  (q31_t)0x100bcac7, (q31_t)0x10058ef4, (q31_t)0xfff5317, (q31_t)0xff91730, (q31_t)0xff2db3e, (q31_t)0xfec9f44,
+    (q31_t)0xfe6633f, (q31_t)0xfe02730,
+  (q31_t)0xfd9eb18, (q31_t)0xfd3aef6, (q31_t)0xfcd72ca, (q31_t)0xfc73695, (q31_t)0xfc0fa55, (q31_t)0xfbabe0c, (q31_t)0xfb481ba,
+    (q31_t)0xfae455d,
+  (q31_t)0xfa808f7, (q31_t)0xfa1cc87, (q31_t)0xf9b900e, (q31_t)0xf95538b, (q31_t)0xf8f16fe, (q31_t)0xf88da68, (q31_t)0xf829dc8,
+    (q31_t)0xf7c611f,
+  (q31_t)0xf76246c, (q31_t)0xf6fe7af, (q31_t)0xf69aae9, (q31_t)0xf636e1a, (q31_t)0xf5d3141, (q31_t)0xf56f45e, (q31_t)0xf50b773,
+    (q31_t)0xf4a7a7d,
+  (q31_t)0xf443d7e, (q31_t)0xf3e0076, (q31_t)0xf37c365, (q31_t)0xf318649, (q31_t)0xf2b4925, (q31_t)0xf250bf7, (q31_t)0xf1ecec0,
+    (q31_t)0xf189180,
+  (q31_t)0xf125436, (q31_t)0xf0c16e3, (q31_t)0xf05d987, (q31_t)0xeff9c21, (q31_t)0xef95eb2, (q31_t)0xef3213a, (q31_t)0xeece3b9,
+    (q31_t)0xee6a62f,
+  (q31_t)0xee0689b, (q31_t)0xeda2afe, (q31_t)0xed3ed58, (q31_t)0xecdafa9, (q31_t)0xec771f1, (q31_t)0xec1342f, (q31_t)0xebaf665,
+    (q31_t)0xeb4b891,
+  (q31_t)0xeae7ab4, (q31_t)0xea83ccf, (q31_t)0xea1fee0, (q31_t)0xe9bc0e8, (q31_t)0xe9582e7, (q31_t)0xe8f44dd, (q31_t)0xe8906cb,
+    (q31_t)0xe82c8af,
+  (q31_t)0xe7c8a8a, (q31_t)0xe764c5c, (q31_t)0xe700e26, (q31_t)0xe69cfe6, (q31_t)0xe63919e, (q31_t)0xe5d534d, (q31_t)0xe5714f3,
+    (q31_t)0xe50d690,
+  (q31_t)0xe4a9824, (q31_t)0xe4459af, (q31_t)0xe3e1b32, (q31_t)0xe37dcac, (q31_t)0xe319e1d, (q31_t)0xe2b5f85, (q31_t)0xe2520e5,
+    (q31_t)0xe1ee23c,
+  (q31_t)0xe18a38a, (q31_t)0xe1264cf, (q31_t)0xe0c260c, (q31_t)0xe05e740, (q31_t)0xdffa86b, (q31_t)0xdf9698e, (q31_t)0xdf32aa8,
+    (q31_t)0xdecebba,
+  (q31_t)0xde6acc3, (q31_t)0xde06dc3, (q31_t)0xdda2ebb, (q31_t)0xdd3efab, (q31_t)0xdcdb091, (q31_t)0xdc77170, (q31_t)0xdc13245,
+    (q31_t)0xdbaf313,
+  (q31_t)0xdb4b3d7, (q31_t)0xdae7494, (q31_t)0xda83548, (q31_t)0xda1f5f3, (q31_t)0xd9bb696, (q31_t)0xd957731, (q31_t)0xd8f37c3,
+    (q31_t)0xd88f84d,
+  (q31_t)0xd82b8cf, (q31_t)0xd7c7948, (q31_t)0xd7639b9, (q31_t)0xd6ffa22, (q31_t)0xd69ba82, (q31_t)0xd637ada, (q31_t)0xd5d3b2a,
+    (q31_t)0xd56fb71,
+  (q31_t)0xd50bbb1, (q31_t)0xd4a7be8, (q31_t)0xd443c17, (q31_t)0xd3dfc3e, (q31_t)0xd37bc5c, (q31_t)0xd317c73, (q31_t)0xd2b3c81,
+    (q31_t)0xd24fc87,
+  (q31_t)0xd1ebc85, (q31_t)0xd187c7b, (q31_t)0xd123c69, (q31_t)0xd0bfc4f, (q31_t)0xd05bc2d, (q31_t)0xcff7c02, (q31_t)0xcf93bd0,
+    (q31_t)0xcf2fb96,
+  (q31_t)0xcecbb53, (q31_t)0xce67b09, (q31_t)0xce03ab7, (q31_t)0xcd9fa5d, (q31_t)0xcd3b9fb, (q31_t)0xccd7991, (q31_t)0xcc7391f,
+    (q31_t)0xcc0f8a5,
+  (q31_t)0xcbab824, (q31_t)0xcb4779a, (q31_t)0xcae3709, (q31_t)0xca7f670, (q31_t)0xca1b5cf, (q31_t)0xc9b7526, (q31_t)0xc953475,
+    (q31_t)0xc8ef3bd,
+  (q31_t)0xc88b2fd, (q31_t)0xc827235, (q31_t)0xc7c3166, (q31_t)0xc75f08f, (q31_t)0xc6fafb0, (q31_t)0xc696ec9, (q31_t)0xc632ddb,
+    (q31_t)0xc5cece5,
+  (q31_t)0xc56abe8, (q31_t)0xc506ae3, (q31_t)0xc4a29d6, (q31_t)0xc43e8c2, (q31_t)0xc3da7a6, (q31_t)0xc376683, (q31_t)0xc312558,
+    (q31_t)0xc2ae425,
+  (q31_t)0xc24a2eb, (q31_t)0xc1e61aa, (q31_t)0xc182061, (q31_t)0xc11df11, (q31_t)0xc0b9db9, (q31_t)0xc055c5a, (q31_t)0xbff1af3,
+    (q31_t)0xbf8d985,
+  (q31_t)0xbf29810, (q31_t)0xbec5693, (q31_t)0xbe6150f, (q31_t)0xbdfd383, (q31_t)0xbd991f0, (q31_t)0xbd35056, (q31_t)0xbcd0eb5,
+    (q31_t)0xbc6cd0c,
+  (q31_t)0xbc08b5c, (q31_t)0xbba49a5, (q31_t)0xbb407e7, (q31_t)0xbadc621, (q31_t)0xba78454, (q31_t)0xba14280, (q31_t)0xb9b00a5,
+    (q31_t)0xb94bec2,
+  (q31_t)0xb8e7cd9, (q31_t)0xb883ae8, (q31_t)0xb81f8f0, (q31_t)0xb7bb6f2, (q31_t)0xb7574ec, (q31_t)0xb6f32df, (q31_t)0xb68f0cb,
+    (q31_t)0xb62aeaf,
+  (q31_t)0xb5c6c8d, (q31_t)0xb562a64, (q31_t)0xb4fe834, (q31_t)0xb49a5fd, (q31_t)0xb4363bf, (q31_t)0xb3d217a, (q31_t)0xb36df2e,
+    (q31_t)0xb309cdb,
+  (q31_t)0xb2a5a81, (q31_t)0xb241820, (q31_t)0xb1dd5b9, (q31_t)0xb17934b, (q31_t)0xb1150d5, (q31_t)0xb0b0e59, (q31_t)0xb04cbd6,
+    (q31_t)0xafe894d,
+  (q31_t)0xaf846bc, (q31_t)0xaf20425, (q31_t)0xaebc187, (q31_t)0xae57ee2, (q31_t)0xadf3c37, (q31_t)0xad8f985, (q31_t)0xad2b6cc,
+    (q31_t)0xacc740c,
+  (q31_t)0xac63146, (q31_t)0xabfee79, (q31_t)0xab9aba6, (q31_t)0xab368cc, (q31_t)0xaad25eb, (q31_t)0xaa6e304, (q31_t)0xaa0a016,
+    (q31_t)0xa9a5d22,
+  (q31_t)0xa941a27, (q31_t)0xa8dd725, (q31_t)0xa87941d, (q31_t)0xa81510f, (q31_t)0xa7b0dfa, (q31_t)0xa74cadf, (q31_t)0xa6e87bd,
+    (q31_t)0xa684495,
+  (q31_t)0xa620166, (q31_t)0xa5bbe31, (q31_t)0xa557af5, (q31_t)0xa4f37b3, (q31_t)0xa48f46b, (q31_t)0xa42b11d, (q31_t)0xa3c6dc8,
+    (q31_t)0xa362a6d,
+  (q31_t)0xa2fe70b, (q31_t)0xa29a3a3, (q31_t)0xa236035, (q31_t)0xa1d1cc1, (q31_t)0xa16d946, (q31_t)0xa1095c6, (q31_t)0xa0a523f,
+    (q31_t)0xa040eb1,
+  (q31_t)0x9fdcb1e, (q31_t)0x9f78784, (q31_t)0x9f143e5, (q31_t)0x9eb003f, (q31_t)0x9e4bc93, (q31_t)0x9de78e1, (q31_t)0x9d83529,
+    (q31_t)0x9d1f16b,
+  (q31_t)0x9cbada7, (q31_t)0x9c569dc, (q31_t)0x9bf260c, (q31_t)0x9b8e236, (q31_t)0x9b29e59, (q31_t)0x9ac5a77, (q31_t)0x9a6168f,
+    (q31_t)0x99fd2a0,
+  (q31_t)0x9998eac, (q31_t)0x9934ab2, (q31_t)0x98d06b2, (q31_t)0x986c2ac, (q31_t)0x9807ea1, (q31_t)0x97a3a8f, (q31_t)0x973f678,
+    (q31_t)0x96db25a,
+  (q31_t)0x9676e37, (q31_t)0x9612a0e, (q31_t)0x95ae5e0, (q31_t)0x954a1ab, (q31_t)0x94e5d71, (q31_t)0x9481931, (q31_t)0x941d4eb,
+    (q31_t)0x93b90a0,
+  (q31_t)0x9354c4f, (q31_t)0x92f07f8, (q31_t)0x928c39b, (q31_t)0x9227f39, (q31_t)0x91c3ad2, (q31_t)0x915f664, (q31_t)0x90fb1f1,
+    (q31_t)0x9096d79,
+  (q31_t)0x90328fb, (q31_t)0x8fce477, (q31_t)0x8f69fee, (q31_t)0x8f05b5f, (q31_t)0x8ea16cb, (q31_t)0x8e3d231, (q31_t)0x8dd8d92,
+    (q31_t)0x8d748ed,
+  (q31_t)0x8d10443, (q31_t)0x8cabf93, (q31_t)0x8c47ade, (q31_t)0x8be3624, (q31_t)0x8b7f164, (q31_t)0x8b1ac9f, (q31_t)0x8ab67d4,
+    (q31_t)0x8a52304,
+  (q31_t)0x89ede2f, (q31_t)0x8989955, (q31_t)0x8925475, (q31_t)0x88c0f90, (q31_t)0x885caa5, (q31_t)0x87f85b5, (q31_t)0x87940c1,
+    (q31_t)0x872fbc6,
+  (q31_t)0x86cb6c7, (q31_t)0x86671c2, (q31_t)0x8602cb9, (q31_t)0x859e7aa, (q31_t)0x853a296, (q31_t)0x84d5d7d, (q31_t)0x847185e,
+    (q31_t)0x840d33b,
+  (q31_t)0x83a8e12, (q31_t)0x83448e5, (q31_t)0x82e03b2, (q31_t)0x827be7a, (q31_t)0x821793e, (q31_t)0x81b33fc, (q31_t)0x814eeb5,
+    (q31_t)0x80ea969,
+  (q31_t)0x8086419, (q31_t)0x8021ec3, (q31_t)0x7fbd968, (q31_t)0x7f59409, (q31_t)0x7ef4ea4, (q31_t)0x7e9093b, (q31_t)0x7e2c3cd,
+    (q31_t)0x7dc7e5a,
+  (q31_t)0x7d638e2, (q31_t)0x7cff365, (q31_t)0x7c9ade4, (q31_t)0x7c3685d, (q31_t)0x7bd22d2, (q31_t)0x7b6dd42, (q31_t)0x7b097ad,
+    (q31_t)0x7aa5214,
+  (q31_t)0x7a40c76, (q31_t)0x79dc6d3, (q31_t)0x797812b, (q31_t)0x7913b7f, (q31_t)0x78af5ce, (q31_t)0x784b019, (q31_t)0x77e6a5e,
+    (q31_t)0x77824a0,
+  (q31_t)0x771dedc, (q31_t)0x76b9914, (q31_t)0x7655347, (q31_t)0x75f0d76, (q31_t)0x758c7a1, (q31_t)0x75281c6, (q31_t)0x74c3be7,
+    (q31_t)0x745f604,
+  (q31_t)0x73fb01c, (q31_t)0x7396a30, (q31_t)0x733243f, (q31_t)0x72cde4a, (q31_t)0x7269851, (q31_t)0x7205253, (q31_t)0x71a0c50,
+    (q31_t)0x713c64a,
+  (q31_t)0x70d803f, (q31_t)0x7073a2f, (q31_t)0x700f41b, (q31_t)0x6faae03, (q31_t)0x6f467e7, (q31_t)0x6ee21c6, (q31_t)0x6e7dba1,
+    (q31_t)0x6e19578,
+  (q31_t)0x6db4f4a, (q31_t)0x6d50919, (q31_t)0x6cec2e3, (q31_t)0x6c87ca9, (q31_t)0x6c2366a, (q31_t)0x6bbf028, (q31_t)0x6b5a9e1,
+    (q31_t)0x6af6396,
+  (q31_t)0x6a91d47, (q31_t)0x6a2d6f4, (q31_t)0x69c909d, (q31_t)0x6964a42, (q31_t)0x69003e3, (q31_t)0x689bd80, (q31_t)0x6837718,
+    (q31_t)0x67d30ad,
+  (q31_t)0x676ea3d, (q31_t)0x670a3ca, (q31_t)0x66a5d53, (q31_t)0x66416d8, (q31_t)0x65dd058, (q31_t)0x65789d5, (q31_t)0x651434e,
+    (q31_t)0x64afcc3,
+  (q31_t)0x644b634, (q31_t)0x63e6fa2, (q31_t)0x638290b, (q31_t)0x631e271, (q31_t)0x62b9bd3, (q31_t)0x6255531, (q31_t)0x61f0e8b,
+    (q31_t)0x618c7e1,
+  (q31_t)0x6128134, (q31_t)0x60c3a83, (q31_t)0x605f3ce, (q31_t)0x5ffad15, (q31_t)0x5f96659, (q31_t)0x5f31f99, (q31_t)0x5ecd8d6,
+    (q31_t)0x5e6920e,
+  (q31_t)0x5e04b43, (q31_t)0x5da0475, (q31_t)0x5d3bda3, (q31_t)0x5cd76cd, (q31_t)0x5c72ff4, (q31_t)0x5c0e917, (q31_t)0x5baa237,
+    (q31_t)0x5b45b53,
+  (q31_t)0x5ae146b, (q31_t)0x5a7cd80, (q31_t)0x5a18692, (q31_t)0x59b3fa0, (q31_t)0x594f8aa, (q31_t)0x58eb1b2, (q31_t)0x5886ab5,
+    (q31_t)0x58223b6,
+  (q31_t)0x57bdcb3, (q31_t)0x57595ac, (q31_t)0x56f4ea2, (q31_t)0x5690795, (q31_t)0x562c085, (q31_t)0x55c7971, (q31_t)0x556325a,
+    (q31_t)0x54feb3f,
+  (q31_t)0x549a422, (q31_t)0x5435d01, (q31_t)0x53d15dd, (q31_t)0x536ceb5, (q31_t)0x530878a, (q31_t)0x52a405d, (q31_t)0x523f92c,
+    (q31_t)0x51db1f7,
+  (q31_t)0x5176ac0, (q31_t)0x5112385, (q31_t)0x50adc48, (q31_t)0x5049507, (q31_t)0x4fe4dc3, (q31_t)0x4f8067c, (q31_t)0x4f1bf32,
+    (q31_t)0x4eb77e5,
+  (q31_t)0x4e53095, (q31_t)0x4dee942, (q31_t)0x4d8a1ec, (q31_t)0x4d25a93, (q31_t)0x4cc1337, (q31_t)0x4c5cbd8, (q31_t)0x4bf8476,
+    (q31_t)0x4b93d11,
+  (q31_t)0x4b2f5a9, (q31_t)0x4acae3e, (q31_t)0x4a666d1, (q31_t)0x4a01f60, (q31_t)0x499d7ed, (q31_t)0x4939077, (q31_t)0x48d48fe,
+    (q31_t)0x4870182,
+  (q31_t)0x480ba04, (q31_t)0x47a7282, (q31_t)0x4742afe, (q31_t)0x46de377, (q31_t)0x4679bee, (q31_t)0x4615461, (q31_t)0x45b0cd2,
+    (q31_t)0x454c541,
+  (q31_t)0x44e7dac, (q31_t)0x4483615, (q31_t)0x441ee7c, (q31_t)0x43ba6df, (q31_t)0x4355f40, (q31_t)0x42f179f, (q31_t)0x428cffb,
+    (q31_t)0x4228854,
+  (q31_t)0x41c40ab, (q31_t)0x415f8ff, (q31_t)0x40fb151, (q31_t)0x40969a0, (q31_t)0x40321ed, (q31_t)0x3fcda37, (q31_t)0x3f6927f,
+    (q31_t)0x3f04ac4,
+  (q31_t)0x3ea0307, (q31_t)0x3e3bb48, (q31_t)0x3dd7386, (q31_t)0x3d72bc2, (q31_t)0x3d0e3fb, (q31_t)0x3ca9c32, (q31_t)0x3c45467,
+    (q31_t)0x3be0c99,
+  (q31_t)0x3b7c4c9, (q31_t)0x3b17cf7, (q31_t)0x3ab3523, (q31_t)0x3a4ed4c, (q31_t)0x39ea573, (q31_t)0x3985d97, (q31_t)0x39215ba,
+    (q31_t)0x38bcdda,
+  (q31_t)0x38585f8, (q31_t)0x37f3e14, (q31_t)0x378f62e, (q31_t)0x372ae46, (q31_t)0x36c665b, (q31_t)0x3661e6f, (q31_t)0x35fd680,
+    (q31_t)0x3598e8f,
+  (q31_t)0x353469c, (q31_t)0x34cfea8, (q31_t)0x346b6b1, (q31_t)0x3406eb8, (q31_t)0x33a26bd, (q31_t)0x333dec0, (q31_t)0x32d96c1,
+    (q31_t)0x3274ec0,
+  (q31_t)0x32106bd, (q31_t)0x31abeb9, (q31_t)0x31476b2, (q31_t)0x30e2ea9, (q31_t)0x307e69f, (q31_t)0x3019e93, (q31_t)0x2fb5684,
+    (q31_t)0x2f50e74,
+  (q31_t)0x2eec663, (q31_t)0x2e87e4f, (q31_t)0x2e2363a, (q31_t)0x2dbee22, (q31_t)0x2d5a609, (q31_t)0x2cf5def, (q31_t)0x2c915d2,
+    (q31_t)0x2c2cdb4,
+  (q31_t)0x2bc8594, (q31_t)0x2b63d73, (q31_t)0x2aff54f, (q31_t)0x2a9ad2a, (q31_t)0x2a36504, (q31_t)0x29d1cdc, (q31_t)0x296d4b2,
+    (q31_t)0x2908c87,
+  (q31_t)0x28a445a, (q31_t)0x283fc2b, (q31_t)0x27db3fb, (q31_t)0x2776bc9, (q31_t)0x2712396, (q31_t)0x26adb62, (q31_t)0x264932b,
+    (q31_t)0x25e4af4,
+  (q31_t)0x25802bb, (q31_t)0x251ba80, (q31_t)0x24b7244, (q31_t)0x2452a07, (q31_t)0x23ee1c8, (q31_t)0x2389988, (q31_t)0x2325147,
+    (q31_t)0x22c0904,
+  (q31_t)0x225c0bf, (q31_t)0x21f787a, (q31_t)0x2193033, (q31_t)0x212e7eb, (q31_t)0x20c9fa1, (q31_t)0x2065757, (q31_t)0x2000f0b,
+    (q31_t)0x1f9c6be,
+  (q31_t)0x1f37e6f, (q31_t)0x1ed3620, (q31_t)0x1e6edcf, (q31_t)0x1e0a57d, (q31_t)0x1da5d2a, (q31_t)0x1d414d6, (q31_t)0x1cdcc80,
+    (q31_t)0x1c7842a,
+  (q31_t)0x1c13bd2, (q31_t)0x1baf37a, (q31_t)0x1b4ab20, (q31_t)0x1ae62c5, (q31_t)0x1a81a69, (q31_t)0x1a1d20c, (q31_t)0x19b89ae,
+    (q31_t)0x1954150,
+  (q31_t)0x18ef8f0, (q31_t)0x188b08f, (q31_t)0x182682d, (q31_t)0x17c1fcb, (q31_t)0x175d767, (q31_t)0x16f8f03, (q31_t)0x169469d,
+    (q31_t)0x162fe37,
+  (q31_t)0x15cb5d0, (q31_t)0x1566d68, (q31_t)0x15024ff, (q31_t)0x149dc96, (q31_t)0x143942b, (q31_t)0x13d4bc0, (q31_t)0x1370354,
+    (q31_t)0x130bae7,
+  (q31_t)0x12a727a, (q31_t)0x1242a0c, (q31_t)0x11de19d, (q31_t)0x117992e, (q31_t)0x11150be, (q31_t)0x10b084d, (q31_t)0x104bfdb,
+    (q31_t)0xfe7769,
+  (q31_t)0xf82ef6, (q31_t)0xf1e683, (q31_t)0xeb9e0f, (q31_t)0xe5559b, (q31_t)0xdf0d26, (q31_t)0xd8c4b0, (q31_t)0xd27c3a,
+    (q31_t)0xcc33c3,
+  (q31_t)0xc5eb4c, (q31_t)0xbfa2d5, (q31_t)0xb95a5d, (q31_t)0xb311e4, (q31_t)0xacc96b, (q31_t)0xa680f2, (q31_t)0xa03878,
+    (q31_t)0x99effe,
+  (q31_t)0x93a784, (q31_t)0x8d5f09, (q31_t)0x87168e, (q31_t)0x80ce12, (q31_t)0x7a8597, (q31_t)0x743d1a, (q31_t)0x6df49e,
+    (q31_t)0x67ac21,
+  (q31_t)0x6163a5, (q31_t)0x5b1b27, (q31_t)0x54d2aa, (q31_t)0x4e8a2c, (q31_t)0x4841af, (q31_t)0x41f931, (q31_t)0x3bb0b3,
+    (q31_t)0x356835,
+  (q31_t)0x2f1fb6, (q31_t)0x28d738, (q31_t)0x228eb9, (q31_t)0x1c463b, (q31_t)0x15fdbc, (q31_t)0xfb53d, (q31_t)0x96cbe, (q31_t)0x3243f
+};
+
+/**
+ * @} end of DCT4_IDCT4_Table group
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief  Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return		  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.
+ * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingQ31Table.gif
+ */
+
+arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q31_t *twiddlePtr[4] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
+    (q31_t *) WeightsQ31_2048, (q31_t *) WeightsQ31_8192
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q31_t *pCosFactor[4] =
+    { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
+    (q31_t *) cos_factorsQ31_2048, (q31_t *) cos_factorsQ31_8192
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 8192U:
+    S->pTwiddle = twiddlePtr[3];
+    S->pCosFactor = pCosFactor[3];
+    break;
+  case 2048U:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512U:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128U:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT Function */
+  arm_rfft_init_q31(S->pRfft,  S->N, 0, 1);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c
new file mode 100644
index 0000000..4fd7f6e
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c
@@ -0,0 +1,382 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_dct4_q15.c
+ * Description:  Processing function of DCT4 & IDCT4 Q15
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+ * @param[in]       *pState        points to state buffer.
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ *
+ * \par Input an output formats:
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.
+ * Number of bits downscaled, depends on the size of the transform.
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
+ *
+ * \image html dct4FormatsQ15Table.gif
+ */
+
+void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  q15_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q15_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q15_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q15_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+   * along with some pre-processing and post-processing.
+   * Computational procedure is explained as follows:
+   * (a) Pre-processing involves multiplying input with cos factor,
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+   *              where,
+   *                 r(n) -- output of preprocessing
+   *                 u(n) -- input to preprocessing(actual Source buffer)
+   * (b) Calculation of DCT2 using FFT is divided into three steps:
+   *                  Step1: Re-ordering of even and odd elements of input.
+   *                  Step2: Calculating FFT of the re-ordered input.
+   *                  Step3: Taking the real part of the product of FFT output and weights.
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+   *                        where,
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------
+   * Step1: Re-ordering of even and odd elements as
+   *             pState[i] =  pInlineBuffer[2*i] and
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1U);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2U;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+
+  /* ---------------------------------------------------------
+   *     Step2: Calculate RFFT for N-point input
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+  *  Step3: Multiply the FFT output with the weights.
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1U) >> 2U;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1U;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1U) % 0x4U;
+
+  while (i > 0U)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2U;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+
+  /* ---------------------------------------------------------
+   *     Step2: Calculate RFFT for N-point input
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+  *  Step3: Multiply the FFT output with the weights.
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1U);
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1U;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+   * @} end of DCT4_IDCT4 group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c
new file mode 100644
index 0000000..7191208
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c
@@ -0,0 +1,383 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_dct4_q31.c
+ * Description:  Processing function of DCT4 & IDCT4 Q31
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+ * @param[in]       *pState        points to state buffer.
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ * \par Input an output formats:
+ * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,
+ * as the conversion from DCT2 to DCT4 involves one subtraction.
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.
+ * Number of bits downscaled, depends on the size of the transform.
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
+ *
+ * \image html dct4FormatsQ31Table.gif
+ */
+
+void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer)
+{
+  uint16_t i;                                    /* Loop counter */
+  q31_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q31_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q31_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q31_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+   * along with some pre-processing and post-processing.
+   * Computational procedure is explained as follows:
+   * (a) Pre-processing involves multiplying input with cos factor,
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+   *              where,
+   *                 r(n) -- output of preprocessing
+   *                 u(n) -- input to preprocessing(actual Source buffer)
+   * (b) Calculation of DCT2 using FFT is divided into three steps:
+   *                  Step1: Re-ordering of even and odd elements of input.
+   *                  Step2: Calculating FFT of the re-ordered input.
+   *                  Step3: Taking the real part of the product of FFT output and weights.
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+   *                        where,
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------
+   * Step1: Re-ordering of even and odd elements as
+   *             pState[i] =  pInlineBuffer[2*i] and
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1U);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#if defined (ARM_MATH_DSP)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = S->Nby2 >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2U;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+
+  /* ---------------------------------------------------------
+   *     Step2: Calculate RFFT for N-point input
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------
+   *  Step3: Multiply the FFT output with the weights.
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = (S->N - 1U) >> 2U;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1U;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  i = (S->N - 1U) % 0x4U;
+
+  while (i > 0U)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2U;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+
+  /* ---------------------------------------------------------
+   *     Step2: Calculate RFFT for N-point input
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------
+   *  Step3: Multiply the FFT output with the weights.
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1U;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = (S->N - 1U);
+
+  while (i > 0U)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while (i > 0U);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+   * @} end of DCT4_IDCT4 group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c
new file mode 100644
index 0000000..16c75eb
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c
@@ -0,0 +1,318 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_rfft_f32.c
+ * Description:  RFFT & RIFFT Floating point process function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+ * Internal functions prototypes
+ * -------------------------------------------------------------------- */
+
+extern void arm_radix4_butterfly_f32(
+    float32_t * pSrc,
+    uint16_t fftLen,
+    float32_t * pCoef,
+    uint16_t twidCoefModifier);
+
+extern void arm_radix4_butterfly_inverse_f32(
+    float32_t * pSrc,
+    uint16_t fftLen,
+    float32_t * pCoef,
+    uint16_t twidCoefModifier,
+    float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+    float32_t * pSrc,
+    uint16_t fftSize,
+    uint16_t bitRevFactor,
+    uint16_t * pBitRevTab);
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point RFFT/RIFFT.
+ * @deprecated Do not use this function.  It has been superceded by \ref arm_rfft_fast_f32 and will be removed
+ * in the future.
+ * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in]  *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst)
+{
+  const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
+
+
+  /* Calculation of Real IFFT of input */
+  if (S->ifftFlagR == 1U)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+
+    /* Complex radix-4 IFFT process */
+    arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier,
+                                     S_CFFT->onebyfftLen);
+
+    /* Bit reversal process */
+    if (S->bitReverseFlagR == 1U)
+    {
+      arm_bitreversal_f32(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+
+    /* Calculation of RFFT of input */
+
+    /* Complex radix-4 FFT process */
+    arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if (S->bitReverseFlagR == 1U)
+    {
+      arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+
+    /*  Real FFT core process */
+    arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+/**
+   * @} end of RealFFT group
+   */
+
+/**
+ * @brief  Core Real FFT process
+ * @param[in]   *pSrc 				points to the input buffer.
+ * @param[in]   fftLen  			length of FFT.
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.
+ * @param[out]  *pDst 				points to the output buffer.
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4U * fftLen) - 1U];      /* temp pointers for output buffer */
+  float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2U * fftLen) - 1U];      /* temp pointers for input buffer */
+
+  /* Init coefficient pointers */
+  pCoefA = &pATable[modifier * 2U];
+  pCoefB = &pBTable[modifier * 2U];
+
+  i = fftLen - 1U;
+
+  while (i > 0U)
+  {
+    /*
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+    /* read pATable[2 * i] */
+    CoefA1 = *pCoefA++;
+    /* pATable[2 * i + 1] */
+    CoefA2 = *pCoefA;
+
+    /* pSrc[2 * i] * pATable[2 * i] */
+    outR = *pSrc1 * CoefA1;
+    /* pSrc[2 * i] * CoefA2 */
+    outI = *pSrc1++ * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR -= (*pSrc1 + *pSrc2) * CoefA2;
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += *pSrc1++ * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI -= *pSrc2 * CoefA2;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2-- * CoefB1;
+
+    /* write output */
+    *pDst1++ = outR;
+    *pDst1++ = outI;
+
+    /* write complex conjugate output */
+    *pDst2-- = -outI;
+    *pDst2-- = outR;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2U);
+    pCoefA = pCoefA + ((modifier * 2U) - 1U);
+
+    i--;
+
+  }
+
+  pDst[2U * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2U * fftLen) + 1U] = 0.0f;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0.0f;
+
+}
+
+
+/**
+ * @brief  Core Real IFFT process
+ * @param[in]   *pSrc 				points to the input buffer.
+ * @param[in]   fftLen  			length of FFT.
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.
+ * @param[out]  *pDst 				points to the output buffer.
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2U * fftLen) + 1U];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  while (fftLen > 0U)
+  {
+    /*
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+
+     */
+
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pSrc[2 * i] * CoefA1 */
+    outR = *pSrc1 * CoefA1;
+
+    /* - pSrc[2 * i] * CoefA2 */
+    outI = -(*pSrc1++) * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR += (*pSrc1 + *pSrc2) * CoefA2;
+
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += (*pSrc1++) * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2 * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI += *pSrc2-- * CoefA2;
+
+    /* write output */
+    *pDst++ = outR;
+    *pDst++ = outI;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2U);
+    pCoefA = pCoefA + ((modifier * 2U) - 1U);
+
+    /* Decrement loop count */
+    fftLen--;
+  }
+
+}
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c
new file mode 100644
index 0000000..08e06e0
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c
@@ -0,0 +1,317 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_rfft_f32.c
+ * Description:  RFFT & RIFFT Floating point process function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+void stage_rfft_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut)
+{
+   uint32_t  k;								   /* Loop Counter                     */
+   float32_t twR, twI;						   /* RFFT Twiddle coefficients        */
+   float32_t * pCoeff = S->pTwiddleRFFT;  /* Points to RFFT Twiddle factors   */
+   float32_t *pA = p;						   /* increasing pointer               */
+   float32_t *pB = p;						   /* decreasing pointer               */
+   float32_t xAR, xAI, xBR, xBI;				/* temporary variables              */
+   float32_t t1a, t1b;				         /* temporary variables              */
+   float32_t p0, p1, p2, p3;				   /* temporary variables              */
+
+
+   k = (S->Sint).fftLen - 1;
+
+   /* Pack first and last sample of the frequency domain together */
+
+   xBR = pB[0];
+   xBI = pB[1];
+   xAR = pA[0];
+   xAI = pA[1];
+
+   twR = *pCoeff++ ;
+   twI = *pCoeff++ ;
+
+   // U1 = XA(1) + XB(1); % It is real
+   t1a = xBR + xAR  ;
+
+   // U2 = XB(1) - XA(1); % It is imaginary
+   t1b = xBI + xAI  ;
+
+   // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+   // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+   *pOut++ = 0.5f * ( t1a + t1b );
+   *pOut++ = 0.5f * ( t1a - t1b );
+
+   // XA(1) = 1/2*( U1 - imag(U2) +  i*( U1 +imag(U2) ));
+   pB  = p + 2*k;
+   pA += 2;
+
+   do
+   {
+      /*
+         function X = my_split_rfft(X, ifftFlag)
+         % X is a series of real numbers
+         L  = length(X);
+         XC = X(1:2:end) +i*X(2:2:end);
+         XA = fft(XC);
+         XB = conj(XA([1 end:-1:2]));
+         TW = i*exp(-2*pi*i*[0:L/2-1]/L).';
+         for l = 2:L/2
+            XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l)));
+         end
+         XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1))));
+         X = XA;
+      */
+
+      xBI = pB[1];
+      xBR = pB[0];
+      xAR = pA[0];
+      xAI = pA[1];
+
+      twR = *pCoeff++;
+      twI = *pCoeff++;
+
+      t1a = xBR - xAR ;
+      t1b = xBI + xAI ;
+
+      // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+      // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+      p0 = twR * t1a;
+      p1 = twI * t1a;
+      p2 = twR * t1b;
+      p3 = twI * t1b;
+
+      *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR
+      *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI
+
+      pA += 2;
+      pB -= 2;
+      k--;
+   } while (k > 0U);
+}
+
+/* Prepares data for inverse cfft */
+void merge_rfft_f32(
+arm_rfft_fast_instance_f32 * S,
+float32_t * p, float32_t * pOut)
+{
+   uint32_t  k;								/* Loop Counter                     */
+   float32_t twR, twI;						/* RFFT Twiddle coefficients        */
+   float32_t *pCoeff = S->pTwiddleRFFT;		/* Points to RFFT Twiddle factors   */
+   float32_t *pA = p;						/* increasing pointer               */
+   float32_t *pB = p;						/* decreasing pointer               */
+   float32_t xAR, xAI, xBR, xBI;			/* temporary variables              */
+   float32_t t1a, t1b, r, s, t, u;			/* temporary variables              */
+
+   k = (S->Sint).fftLen - 1;
+
+   xAR = pA[0];
+   xAI = pA[1];
+
+   pCoeff += 2 ;
+
+   *pOut++ = 0.5f * ( xAR + xAI );
+   *pOut++ = 0.5f * ( xAR - xAI );
+
+   pB  =  p + 2*k ;
+   pA +=  2	   ;
+
+   while (k > 0U)
+   {
+      /* G is half of the frequency complex spectrum */
+      //for k = 2:N
+      //    Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2))));
+      xBI =   pB[1]    ;
+      xBR =   pB[0]    ;
+      xAR =  pA[0];
+      xAI =  pA[1];
+
+      twR = *pCoeff++;
+      twI = *pCoeff++;
+
+      t1a = xAR - xBR ;
+      t1b = xAI + xBI ;
+
+      r = twR * t1a;
+      s = twI * t1b;
+      t = twI * t1a;
+      u = twR * t1b;
+
+      // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI);
+      // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI);
+      *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR
+      *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI
+
+      pA += 2;
+      pB -= 2;
+      k--;
+   }
+
+}
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+ * @defgroup RealFFT Real FFT Functions
+ *
+ * \par
+ * The CMSIS DSP library includes specialized algorithms for computing the
+ * FFT of real data sequences.  The FFT is defined over complex data but
+ * in many applications the input is real.  Real FFT algorithms take advantage
+ * of the symmetry properties of the FFT and have a speed advantage over complex
+ * algorithms of the same length.
+ * \par
+ * The Fast RFFT algorith relays on the mixed radix CFFT that save processor usage.
+ * \par
+ * The real length N forward FFT of a sequence is computed using the steps shown below.
+ * \par
+ * \image html RFFT.gif "Real Fast Fourier Transform"
+ * \par
+ * The real sequence is initially treated as if it were complex to perform a CFFT.
+ * Later, a processing stage reshapes the data to obtain half of the frequency spectrum
+ * in complex format. Except the first complex number that contains the two real numbers
+ * X[0] and X[N/2] all the data is complex. In other words, the first complex sample
+ * contains two real values packed.
+ * \par
+ * The input for the inverse RFFT should keep the same format as the output of the
+ * forward RFFT. A first processing stage pre-process the data to later perform an
+ * inverse CFFT.
+ * \par
+ * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"
+ * \par
+ * The algorithms for floating-point, Q15, and Q31 data are slightly different
+ * and we describe each algorithm in turn.
+ * \par Floating-point
+ * The main functions are arm_rfft_fast_f32() and arm_rfft_fast_init_f32().
+ * The older functions arm_rfft_f32() and arm_rfft_init_f32() have been
+ * deprecated but are still documented.
+ * \par
+ * The FFT of a real N-point sequence has even symmetry in the frequency
+ * domain. The second half of the data equals the conjugate of the first
+ * half flipped in frequency. Looking at the data, we see that we can
+ * uniquely represent the FFT using only N/2 complex numbers. These are
+ * packed into the output array in alternating real and imaginary
+ * components:
+ * \par
+ * X = { real[0], imag[0], real[1], imag[1], real[2], imag[2] ...
+ * real[(N/2)-1], imag[(N/2)-1 }
+ * \par
+ * It happens that the first complex number (real[0], imag[0]) is actually
+ * all real. real[0] represents the DC offset, and imag[0] should be 0.
+ * (real[1], imag[1]) is the fundamental frequency, (real[2], imag[2]) is
+ * the first harmonic and so on.
+ * \par
+ * The real FFT functions pack the frequency domain data in this fashion.
+ * The forward transform outputs the data in this form and the inverse
+ * transform expects input data in this form. The function always performs
+ * the needed bitreversal so that the input and output data is always in
+ * normal order. The functions support lengths of [32, 64, 128, ..., 4096]
+ * samples.
+ * \par Q15 and Q31
+ * The real algorithms are defined in a similar manner and utilize N/2 complex
+ * transforms behind the scenes.
+ * \par
+ * The complex transforms used internally include scaling to prevent fixed-point
+ * overflows.  The overall scaling equals 1/(fftLen/2).
+ * \par
+ * A separate instance structure must be defined for each transform used but
+ * twiddle factor and bit reversal tables can be reused.
+ * \par
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Initializes twiddle factor table and bit reversal table pointers.
+ * - Initializes the internal complex FFT data structure.
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure
+ * cannot be placed into a const data section. To place an instance structure
+ * into a const data section, the instance structure should be manually
+ * initialized as follows:
+ * 
+ *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+ *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+ * 

+ * where fftLenReal is the length of the real transform;
+ * fftLenBy2 length of  the internal complex transform.
+ * ifftFlagR Selects forward (=0) or inverse (=1) transform.
+ * bitReverseFlagR Selects bit reversed output (=0) or normal order
+ * output (=1).
+ * twidCoefRModifier stride modifier for the twiddle factor table.
+ * The value is based on the FFT length;
+ * pTwiddleARealpoints to the A array of twiddle coefficients;
+ * pTwiddleBRealpoints to the B array of twiddle coefficients;
+ * pCfft points to the CFFT Instance structure. The CFFT structure
+ * must also be initialized.  Refer to arm_cfft_radix4_f32() for details regarding
+ * static initialization of the complex FFT instance structure.
+ */
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point real FFT.
+* @param[in]  *S              points to an arm_rfft_fast_instance_f32 structure.
+* @param[in]  *p              points to the input buffer.
+* @param[in]  *pOut           points to the output buffer.
+* @param[in]  ifftFlag        RFFT if flag is 0, RIFFT if flag is 1
+* @return none.
+*/
+
+void arm_rfft_fast_f32(
+arm_rfft_fast_instance_f32 * S,
+float32_t * p, float32_t * pOut,
+uint8_t ifftFlag)
+{
+   arm_cfft_instance_f32 * Sint = &(S->Sint);
+   Sint->fftLen = S->fftLenRFFT / 2;
+
+   /* Calculation of Real FFT */
+   if (ifftFlag)
+   {
+      /*  Real FFT compression */
+      merge_rfft_f32(S, p, pOut);
+
+      /* Complex radix-4 IFFT process */
+      arm_cfft_f32( Sint, pOut, ifftFlag, 1);
+   }
+   else
+   {
+      /* Calculation of RFFT of input */
+      arm_cfft_f32( Sint, p, ifftFlag, 1);
+
+      /*  Real FFT extraction */
+      stage_rfft_f32(S, p, pOut);
+   }
+}
+
+/**
+* @} end of RealFFT group
+*/
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c
new file mode 100644
index 0000000..6f6c2f9
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_cfft_init_f32.c
+ * Description:  Split Radix Decimation in Frequency CFFT Floating point processing function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+* @brief  Initialization function for the floating-point real FFT.
+* @param[in,out] *S             points to an arm_rfft_fast_instance_f32 structure.
+* @param[in]     fftLen         length of the Real Sequence.
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter fftLen	Specifies length of RFFT/CIFFT process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+arm_status arm_rfft_fast_init_f32(
+  arm_rfft_fast_instance_f32 * S,
+  uint16_t fftLen)
+{
+  arm_cfft_instance_f32 * Sint;
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  Sint = &(S->Sint);
+  Sint->fftLen = fftLen/2;
+  S->fftLenRFFT = fftLen;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (Sint->fftLen)
+  {
+  case 2048U:
+    /*  Initializations of structure parameters for 2048 point FFT */
+    /*  Initialise the bit reversal table length */
+    Sint->bitRevLength = ARMBITREVINDEXTABLE_2048_TABLE_LENGTH;
+    /*  Initialise the bit reversal table pointer */
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable2048;
+    /*  Initialise the Twiddle coefficient pointers */
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_2048;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_4096;
+    break;
+  case 1024U:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE_1024_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable1024;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_1024;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_2048;
+    break;
+  case 512U:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE_512_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable512;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_512;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_1024;
+    break;
+  case 256U:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE_256_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable256;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_256;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_512;
+    break;
+  case 128U:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE_128_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable128;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_128;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_256;
+    break;
+  case 64U:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE_64_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable64;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_64;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_128;
+    break;
+  case 32U:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE_32_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable32;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_32;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_64;
+    break;
+  case 16U:
+    Sint->bitRevLength = ARMBITREVINDEXTABLE_16_TABLE_LENGTH;
+    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable16;
+		Sint->pTwiddle     = (float32_t *) twiddleCoef_16;
+		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_32;
+    break;
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**
+ * @} end of RealFFT group
+ */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c
new file mode 100644
index 0000000..fd02e41
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c
@@ -0,0 +1,4273 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_rfft_init_f32.c
+ * Description:  RFFT & RIFFT Floating point initialisation function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup RealFFT
+ */
+
+/**
+ * @addtogroup RealFFT_Table Real FFT Tables
+ * @{
+ */
+
+/**
+* \par
+* Generation of realCoefA array:
+* \par
+* 	n = 4096
+* 
for (i = 0; i < n; i++)
+*  {
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+*  } 

+*/
+static const float32_t realCoefA[8192] = {
+  0.500000000000000f, -0.500000000000000f, 0.499616503715515f, -0.499999850988388f,
+  0.499233007431030f, -0.499999403953552f, 0.498849511146545f, -0.499998688697815f,
+  0.498466014862061f, -0.499997645616531f, 0.498082518577576f, -0.499996334314346f,
+  0.497699022293091f, -0.499994695186615f, 0.497315555810928f, -0.499992787837982f,
+  0.496932059526443f, -0.499990582466125f, 0.496548563241959f, -0.499988079071045f,
+  0.496165096759796f, -0.499985307455063f, 0.495781600475311f, -0.499982208013535f,
+  0.495398133993149f, -0.499978810548782f, 0.495014637708664f, -0.499975144863129f,
+  0.494631171226501f, -0.499971181154251f, 0.494247704744339f, -0.499966919422150f,
+  0.493864238262177f, -0.499962359666824f, 0.493480771780014f, -0.499957501888275f,
+  0.493097305297852f, -0.499952346086502f, 0.492713838815689f, -0.499946922063828f,
+  0.492330402135849f, -0.499941170215607f, 0.491946935653687f, -0.499935150146484f,
+  0.491563498973846f, -0.499928832054138f, 0.491180062294006f, -0.499922215938568f,
+  0.490796625614166f, -0.499915301799774f, 0.490413218736649f, -0.499908089637756f,
+  0.490029782056808f, -0.499900579452515f, 0.489646375179291f, -0.499892801046371f,
+  0.489262968301773f, -0.499884694814682f, 0.488879561424255f, -0.499876320362091f,
+  0.488496154546738f, -0.499867647886276f, 0.488112777471542f, -0.499858677387238f,
+  0.487729400396347f, -0.499849408864975f, 0.487346023321152f, -0.499839842319489f,
+  0.486962646245956f, -0.499830007553101f, 0.486579269170761f, -0.499819844961166f,
+  0.486195921897888f, -0.499809414148331f, 0.485812574625015f, -0.499798685312271f,
+  0.485429257154465f, -0.499787658452988f, 0.485045909881592f, -0.499776333570480f,
+  0.484662592411041f, -0.499764710664749f, 0.484279274940491f, -0.499752789735794f,
+  0.483895987272263f, -0.499740600585938f, 0.483512699604034f, -0.499728083610535f,
+  0.483129411935806f, -0.499715298414230f, 0.482746154069901f, -0.499702215194702f,
+  0.482362866401672f, -0.499688833951950f, 0.481979638338089f, -0.499675154685974f,
+  0.481596380472183f, -0.499661177396774f, 0.481213152408600f, -0.499646931886673f,
+  0.480829954147339f, -0.499632388353348f, 0.480446726083755f, -0.499617516994476f,
+  0.480063527822495f, -0.499602377414703f, 0.479680359363556f, -0.499586939811707f,
+  0.479297190904617f, -0.499571204185486f, 0.478914022445679f, -0.499555170536041f,
+  0.478530883789063f, -0.499538868665695f, 0.478147745132446f, -0.499522238969803f,
+  0.477764606475830f, -0.499505341053009f, 0.477381497621536f, -0.499488145112991f,
+  0.476998418569565f, -0.499470651149750f, 0.476615339517593f, -0.499452859163284f,
+  0.476232260465622f, -0.499434769153595f, 0.475849211215973f, -0.499416410923004f,
+  0.475466161966324f, -0.499397724866867f, 0.475083142518997f, -0.499378770589828f,
+  0.474700123071671f, -0.499359518289566f, 0.474317133426666f, -0.499339967966080f,
+  0.473934143781662f, -0.499320119619370f, 0.473551183938980f, -0.499299973249435f,
+  0.473168224096298f, -0.499279528856277f, 0.472785294055939f, -0.499258816242218f,
+  0.472402364015579f, -0.499237775802612f, 0.472019463777542f, -0.499216467142105f,
+  0.471636593341827f, -0.499194860458374f, 0.471253722906113f, -0.499172955751419f,
+  0.470870882272720f, -0.499150782823563f, 0.470488041639328f, -0.499128282070160f,
+  0.470105201005936f, -0.499105513095856f, 0.469722419977188f, -0.499082416296005f,
+  0.469339638948441f, -0.499059051275253f, 0.468956857919693f, -0.499035388231277f,
+  0.468574106693268f, -0.499011427164078f, 0.468191385269165f, -0.498987197875977f,
+  0.467808693647385f, -0.498962640762329f, 0.467426002025604f, -0.498937815427780f,
+  0.467043310403824f, -0.498912662267685f, 0.466660678386688f, -0.498887240886688f,
+  0.466278046369553f, -0.498861521482468f, 0.465895414352417f, -0.498835533857346f,
+  0.465512841939926f, -0.498809218406677f, 0.465130269527435f, -0.498782604932785f,
+  0.464747726917267f, -0.498755723237991f, 0.464365184307098f, -0.498728543519974f,
+  0.463982671499252f, -0.498701065778732f, 0.463600188493729f, -0.498673290014267f,
+  0.463217705488205f, -0.498645216226578f, 0.462835282087326f, -0.498616874217987f,
+  0.462452858686447f, -0.498588204383850f, 0.462070435285568f, -0.498559266328812f,
+  0.461688071489334f, -0.498530030250549f, 0.461305707693100f, -0.498500496149063f,
+  0.460923373699188f, -0.498470664024353f, 0.460541069507599f, -0.498440563678741f,
+  0.460158795118332f, -0.498410135507584f, 0.459776520729065f, -0.498379439115524f,
+  0.459394276142120f, -0.498348444700241f, 0.459012061357498f, -0.498317152261734f,
+  0.458629876375198f, -0.498285561800003f, 0.458247691392899f, -0.498253703117371f,
+  0.457865566015244f, -0.498221516609192f, 0.457483440637589f, -0.498189061880112f,
+  0.457101345062256f, -0.498156309127808f, 0.456719279289246f, -0.498123258352280f,
+  0.456337243318558f, -0.498089909553528f, 0.455955207347870f, -0.498056292533875f,
+  0.455573230981827f, -0.498022347688675f, 0.455191254615784f, -0.497988134622574f,
+  0.454809308052063f, -0.497953623533249f, 0.454427421092987f, -0.497918814420700f,
+  0.454045534133911f, -0.497883707284927f, 0.453663676977158f, -0.497848302125931f,
+  0.453281819820404f, -0.497812628746033f, 0.452900022268295f, -0.497776657342911f,
+  0.452518254518509f, -0.497740387916565f, 0.452136516571045f, -0.497703820466995f,
+  0.451754778623581f, -0.497666954994202f, 0.451373100280762f, -0.497629791498184f,
+  0.450991421937943f, -0.497592359781265f, 0.450609803199768f, -0.497554630041122f,
+  0.450228184461594f, -0.497516602277756f, 0.449846625328064f, -0.497478276491165f,
+  0.449465066194534f, -0.497439652681351f, 0.449083566665649f, -0.497400760650635f,
+  0.448702067136765f, -0.497361570596695f, 0.448320597410202f, -0.497322082519531f,
+  0.447939187288284f, -0.497282296419144f, 0.447557777166367f, -0.497242212295532f,
+  0.447176426649094f, -0.497201830148697f, 0.446795076131821f, -0.497161179780960f,
+  0.446413785219193f, -0.497120231389999f, 0.446032524108887f, -0.497078984975815f,
+  0.445651292800903f, -0.497037440538406f, 0.445270061492920f, -0.496995598077774f,
+  0.444888889789581f, -0.496953487396240f, 0.444507747888565f, -0.496911078691483f,
+  0.444126635789871f, -0.496868371963501f, 0.443745553493500f, -0.496825367212296f,
+  0.443364530801773f, -0.496782064437866f, 0.442983508110046f, -0.496738493442535f,
+  0.442602545022964f, -0.496694594621658f, 0.442221581935883f, -0.496650427579880f,
+  0.441840678453445f, -0.496605962514877f, 0.441459804773331f, -0.496561229228973f,
+  0.441078960895538f, -0.496516168117523f, 0.440698176622391f, -0.496470838785172f,
+  0.440317392349243f, -0.496425211429596f, 0.439936667680740f, -0.496379286050797f,
+  0.439555943012238f, -0.496333062648773f, 0.439175277948380f, -0.496286571025848f,
+  0.438794672489166f, -0.496239781379700f, 0.438414067029953f, -0.496192663908005f,
+  0.438033521175385f, -0.496145308017731f, 0.437653005123138f, -0.496097624301910f,
+  0.437272518873215f, -0.496049642562866f, 0.436892062425613f, -0.496001392602921f,
+  0.436511665582657f, -0.495952844619751f, 0.436131268739700f, -0.495903998613358f,
+  0.435750931501389f, -0.495854884386063f, 0.435370653867722f, -0.495805442333221f,
+  0.434990376234055f, -0.495755732059479f, 0.434610158205032f, -0.495705723762512f,
+  0.434229999780655f, -0.495655417442322f, 0.433849841356277f, -0.495604842901230f,
+  0.433469742536545f, -0.495553970336914f, 0.433089673519135f, -0.495502769947052f,
+  0.432709634304047f, -0.495451331138611f, 0.432329654693604f, -0.495399564504623f,
+  0.431949704885483f, -0.495347499847412f, 0.431569814682007f, -0.495295166969299f,
+  0.431189924478531f, -0.495242536067963f, 0.430810123682022f, -0.495189607143402f,
+  0.430430322885513f, -0.495136409997940f, 0.430050581693649f, -0.495082914829254f,
+  0.429670870304108f, -0.495029091835022f, 0.429291218519211f, -0.494975030422211f,
+  0.428911596536636f, -0.494920641183853f, 0.428532034158707f, -0.494865983724594f,
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+  0.472402364015579f, 0.499237775802612f, 0.472785294055939f, 0.499258816242218f,
+  0.473168224096298f, 0.499279528856277f, 0.473551183938980f, 0.499299973249435f,
+  0.473934143781662f, 0.499320119619370f, 0.474317133426666f, 0.499339967966080f,
+  0.474700123071671f, 0.499359518289566f, 0.475083142518997f, 0.499378770589828f,
+  0.475466161966324f, 0.499397724866867f, 0.475849211215973f, 0.499416410923004f,
+  0.476232260465622f, 0.499434769153595f, 0.476615339517593f, 0.499452859163284f,
+  0.476998418569565f, 0.499470651149750f, 0.477381497621536f, 0.499488145112991f,
+  0.477764606475830f, 0.499505341053009f, 0.478147745132446f, 0.499522238969803f,
+  0.478530883789063f, 0.499538868665695f, 0.478914022445679f, 0.499555170536041f,
+  0.479297190904617f, 0.499571204185486f, 0.479680359363556f, 0.499586939811707f,
+  0.480063527822495f, 0.499602377414703f, 0.480446726083755f, 0.499617516994476f,
+  0.480829954147339f, 0.499632388353348f, 0.481213152408600f, 0.499646931886673f,
+  0.481596380472183f, 0.499661177396774f, 0.481979638338089f, 0.499675154685974f,
+  0.482362866401672f, 0.499688833951950f, 0.482746154069901f, 0.499702215194702f,
+  0.483129411935806f, 0.499715298414230f, 0.483512699604034f, 0.499728083610535f,
+  0.483895987272263f, 0.499740600585938f, 0.484279274940491f, 0.499752789735794f,
+  0.484662592411041f, 0.499764710664749f, 0.485045909881592f, 0.499776333570480f,
+  0.485429257154465f, 0.499787658452988f, 0.485812574625015f, 0.499798685312271f,
+  0.486195921897888f, 0.499809414148331f, 0.486579269170761f, 0.499819844961166f,
+  0.486962646245956f, 0.499830007553101f, 0.487346023321152f, 0.499839842319489f,
+  0.487729400396347f, 0.499849408864975f, 0.488112777471542f, 0.499858677387238f,
+  0.488496154546738f, 0.499867647886276f, 0.488879561424255f, 0.499876320362091f,
+  0.489262968301773f, 0.499884694814682f, 0.489646375179291f, 0.499892801046371f,
+  0.490029782056808f, 0.499900579452515f, 0.490413218736649f, 0.499908089637756f,
+  0.490796625614166f, 0.499915301799774f, 0.491180062294006f, 0.499922215938568f,
+  0.491563498973846f, 0.499928832054138f, 0.491946935653687f, 0.499935150146484f,
+  0.492330402135849f, 0.499941170215607f, 0.492713838815689f, 0.499946922063828f,
+  0.493097305297852f, 0.499952346086502f, 0.493480771780014f, 0.499957501888275f,
+  0.493864238262177f, 0.499962359666824f, 0.494247704744339f, 0.499966919422150f,
+  0.494631171226501f, 0.499971181154251f, 0.495014637708664f, 0.499975144863129f,
+  0.495398133993149f, 0.499978810548782f, 0.495781600475311f, 0.499982208013535f,
+  0.496165096759796f, 0.499985307455063f, 0.496548563241959f, 0.499988079071045f,
+  0.496932059526443f, 0.499990582466125f, 0.497315555810928f, 0.499992787837982f,
+  0.497699022293091f, 0.499994695186615f, 0.498082518577576f, 0.499996334314346f,
+  0.498466014862061f, 0.499997645616531f, 0.498849511146545f, 0.499998688697815f,
+  0.499233007431030f, 0.499999403953552f, 0.499616503715515f, 0.499999850988388f,
+};
+
+
+/**
+* \par
+* Generation of realCoefB array:
+* \par
+* n = 4096
+* 
for (i = 0; i < n; i++)
+* {
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+*  } 

+*
+*/
+static const float32_t realCoefB[8192] = {
+  0.500000000000000f, 0.500000000000000f, 0.500383496284485f, 0.499999850988388f,
+  0.500766992568970f, 0.499999403953552f, 0.501150488853455f, 0.499998688697815f,
+  0.501533985137939f, 0.499997645616531f, 0.501917481422424f, 0.499996334314346f,
+  0.502300977706909f, 0.499994695186615f, 0.502684473991394f, 0.499992787837982f,
+  0.503067970275879f, 0.499990582466125f, 0.503451406955719f, 0.499988079071045f,
+  0.503834903240204f, 0.499985307455063f, 0.504218399524689f, 0.499982208013535f,
+  0.504601895809174f, 0.499978810548782f, 0.504985332489014f, 0.499975144863129f,
+  0.505368828773499f, 0.499971181154251f, 0.505752325057983f, 0.499966919422150f,
+  0.506135761737823f, 0.499962359666824f, 0.506519258022308f, 0.499957501888275f,
+  0.506902694702148f, 0.499952346086502f, 0.507286131381989f, 0.499946922063828f,
+  0.507669627666473f, 0.499941170215607f, 0.508053064346313f, 0.499935150146484f,
+  0.508436501026154f, 0.499928832054138f, 0.508819937705994f, 0.499922215938568f,
+  0.509203374385834f, 0.499915301799774f, 0.509586811065674f, 0.499908089637756f,
+  0.509970188140869f, 0.499900579452515f, 0.510353624820709f, 0.499892801046371f,
+  0.510737061500549f, 0.499884694814682f, 0.511120438575745f, 0.499876320362091f,
+  0.511503815650940f, 0.499867647886276f, 0.511887252330780f, 0.499858677387238f,
+  0.512270629405975f, 0.499849408864975f, 0.512654006481171f, 0.499839842319489f,
+  0.513037383556366f, 0.499830007553101f, 0.513420701026917f, 0.499819844961166f,
+  0.513804078102112f, 0.499809414148331f, 0.514187395572662f, 0.499798685312271f,
+  0.514570772647858f, 0.499787658452988f, 0.514954090118408f, 0.499776333570480f,
+  0.515337407588959f, 0.499764710664749f, 0.515720725059509f, 0.499752789735794f,
+  0.516103982925415f, 0.499740600585938f, 0.516487300395966f, 0.499728083610535f,
+  0.516870558261871f, 0.499715298414230f, 0.517253875732422f, 0.499702215194702f,
+  0.517637133598328f, 0.499688833951950f, 0.518020391464233f, 0.499675154685974f,
+  0.518403589725494f, 0.499661177396774f, 0.518786847591400f, 0.499646931886673f,
+  0.519170045852661f, 0.499632388353348f, 0.519553244113922f, 0.499617516994476f,
+  0.519936442375183f, 0.499602377414703f, 0.520319640636444f, 0.499586939811707f,
+  0.520702838897705f, 0.499571204185486f, 0.521085977554321f, 0.499555170536041f,
+  0.521469116210938f, 0.499538868665695f, 0.521852254867554f, 0.499522238969803f,
+  0.522235393524170f, 0.499505341053009f, 0.522618472576141f, 0.499488145112991f,
+  0.523001611232758f, 0.499470651149750f, 0.523384690284729f, 0.499452859163284f,
+  0.523767769336700f, 0.499434769153595f, 0.524150788784027f, 0.499416410923004f,
+  0.524533808231354f, 0.499397724866867f, 0.524916887283325f, 0.499378770589828f,
+  0.525299847126007f, 0.499359518289566f, 0.525682866573334f, 0.499339967966080f,
+  0.526065826416016f, 0.499320119619370f, 0.526448845863342f, 0.499299973249435f,
+  0.526831746101379f, 0.499279528856277f, 0.527214705944061f, 0.499258816242218f,
+  0.527597606182098f, 0.499237775802612f, 0.527980506420136f, 0.499216467142105f,
+  0.528363406658173f, 0.499194860458374f, 0.528746306896210f, 0.499172955751419f,
+  0.529129147529602f, 0.499150782823563f, 0.529511988162994f, 0.499128282070160f,
+  0.529894769191742f, 0.499105513095856f, 0.530277609825134f, 0.499082416296005f,
+  0.530660390853882f, 0.499059051275253f, 0.531043112277985f, 0.499035388231277f,
+  0.531425893306732f, 0.499011427164078f, 0.531808614730835f, 0.498987197875977f,
+  0.532191336154938f, 0.498962640762329f, 0.532573997974396f, 0.498937815427780f,
+  0.532956659793854f, 0.498912662267685f, 0.533339321613312f, 0.498887240886688f,
+  0.533721983432770f, 0.498861521482468f, 0.534104585647583f, 0.498835533857346f,
+  0.534487187862396f, 0.498809218406677f, 0.534869730472565f, 0.498782604932785f,
+  0.535252273082733f, 0.498755723237991f, 0.535634815692902f, 0.498728543519974f,
+  0.536017298698425f, 0.498701065778732f, 0.536399841308594f, 0.498673290014267f,
+  0.536782264709473f, 0.498645216226578f, 0.537164747714996f, 0.498616874217987f,
+  0.537547171115875f, 0.498588204383850f, 0.537929534912109f, 0.498559266328812f,
+  0.538311958312988f, 0.498530030250549f, 0.538694262504578f, 0.498500496149063f,
+  0.539076626300812f, 0.498470664024353f, 0.539458930492401f, 0.498440563678741f,
+  0.539841234683990f, 0.498410135507584f, 0.540223479270935f, 0.498379439115524f,
+  0.540605723857880f, 0.498348444700241f, 0.540987968444824f, 0.498317152261734f,
+  0.541370153427124f, 0.498285561800003f, 0.541752278804779f, 0.498253703117371f,
+  0.542134463787079f, 0.498221516609192f, 0.542516589164734f, 0.498189061880112f,
+  0.542898654937744f, 0.498156309127808f, 0.543280720710754f, 0.498123258352280f,
+  0.543662786483765f, 0.498089909553528f, 0.544044792652130f, 0.498056292533875f,
+  0.544426798820496f, 0.498022347688675f, 0.544808745384216f, 0.497988134622574f,
+  0.545190691947937f, 0.497953623533249f, 0.545572578907013f, 0.497918814420700f,
+  0.545954465866089f, 0.497883707284927f, 0.546336352825165f, 0.497848302125931f,
+  0.546718180179596f, 0.497812628746033f, 0.547099947929382f, 0.497776657342911f,
+  0.547481775283813f, 0.497740387916565f, 0.547863483428955f, 0.497703820466995f,
+  0.548245191574097f, 0.497666954994202f, 0.548626899719238f, 0.497629791498184f,
+  0.549008548259735f, 0.497592359781265f, 0.549390196800232f, 0.497554630041122f,
+  0.549771785736084f, 0.497516602277756f, 0.550153374671936f, 0.497478276491165f,
+  0.550534904003143f, 0.497439652681351f, 0.550916433334351f, 0.497400760650635f,
+  0.551297962665558f, 0.497361570596695f, 0.551679372787476f, 0.497322082519531f,
+  0.552060842514038f, 0.497282296419144f, 0.552442193031311f, 0.497242212295532f,
+  0.552823603153229f, 0.497201830148697f, 0.553204894065857f, 0.497161179780960f,
+  0.553586184978485f, 0.497120231389999f, 0.553967475891113f, 0.497078984975815f,
+  0.554348707199097f, 0.497037440538406f, 0.554729938507080f, 0.496995598077774f,
+  0.555111110210419f, 0.496953487396240f, 0.555492222309113f, 0.496911078691483f,
+  0.555873334407806f, 0.496868371963501f, 0.556254446506500f, 0.496825367212296f,
+  0.556635499000549f, 0.496782064437866f, 0.557016491889954f, 0.496738493442535f,
+  0.557397484779358f, 0.496694594621658f, 0.557778418064117f, 0.496650427579880f,
+  0.558159291744232f, 0.496605962514877f, 0.558540165424347f, 0.496561229228973f,
+  0.558921039104462f, 0.496516168117523f, 0.559301853179932f, 0.496470838785172f,
+  0.559682607650757f, 0.496425211429596f, 0.560063362121582f, 0.496379286050797f,
+  0.560444056987762f, 0.496333062648773f, 0.560824692249298f, 0.496286571025848f,
+  0.561205327510834f, 0.496239781379700f, 0.561585903167725f, 0.496192663908005f,
+  0.561966478824615f, 0.496145308017731f, 0.562346994876862f, 0.496097624301910f,
+  0.562727510929108f, 0.496049642562866f, 0.563107967376709f, 0.496001392602921f,
+  0.563488364219666f, 0.495952844619751f, 0.563868701457977f, 0.495903998613358f,
+  0.564249038696289f, 0.495854884386063f, 0.564629375934601f, 0.495805442333221f,
+  0.565009593963623f, 0.495755732059479f, 0.565389811992645f, 0.495705723762512f,
+  0.565770030021667f, 0.495655417442322f, 0.566150128841400f, 0.495604842901230f,
+  0.566530287265778f, 0.495553970336914f, 0.566910326480865f, 0.495502769947052f,
+  0.567290365695953f, 0.495451331138611f, 0.567670345306396f, 0.495399564504623f,
+  0.568050265312195f, 0.495347499847412f, 0.568430185317993f, 0.495295166969299f,
+  0.568810045719147f, 0.495242536067963f, 0.569189906120300f, 0.495189607143402f,
+  0.569569647312164f, 0.495136409997940f, 0.569949388504028f, 0.495082914829254f,
+  0.570329129695892f, 0.495029091835022f, 0.570708811283112f, 0.494975030422211f,
+  0.571088373661041f, 0.494920641183853f, 0.571467995643616f, 0.494865983724594f,
+  0.571847498416901f, 0.494810998439789f, 0.572227001190186f, 0.494755744934082f,
+  0.572606444358826f, 0.494700223207474f, 0.572985887527466f, 0.494644373655319f,
+  0.573365211486816f, 0.494588255882263f, 0.573744535446167f, 0.494531840085983f,
+  0.574123859405518f, 0.494475126266479f, 0.574503064155579f, 0.494418144226074f,
+  0.574882268905640f, 0.494360834360123f, 0.575261414051056f, 0.494303256273270f,
+  0.575640499591827f, 0.494245409965515f, 0.576019585132599f, 0.494187235832214f,
+  0.576398611068726f, 0.494128793478012f, 0.576777577400208f, 0.494070053100586f,
+  0.577156484127045f, 0.494011014699936f, 0.577535390853882f, 0.493951678276062f,
+  0.577914178371429f, 0.493892073631287f, 0.578292965888977f, 0.493832170963287f,
+  0.578671753406525f, 0.493771970272064f, 0.579050421714783f, 0.493711471557617f,
+  0.579429090023041f, 0.493650704622269f, 0.579807698726654f, 0.493589639663696f,
+  0.580186247825623f, 0.493528276681900f, 0.580564737319946f, 0.493466645479202f,
+  0.580943167209625f, 0.493404686450958f, 0.581321597099304f, 0.493342459201813f,
+  0.581699967384338f, 0.493279963731766f, 0.582078278064728f, 0.493217140436172f,
+  0.582456588745117f, 0.493154048919678f, 0.582834780216217f, 0.493090659379959f,
+  0.583212971687317f, 0.493026971817017f, 0.583591103553772f, 0.492963016033173f,
+  0.583969175815582f, 0.492898762226105f, 0.584347188472748f, 0.492834210395813f,
+  0.584725141525269f, 0.492769360542297f, 0.585103094577789f, 0.492704242467880f,
+  0.585480928421021f, 0.492638826370239f, 0.585858762264252f, 0.492573112249374f,
+  0.586236536502838f, 0.492507129907608f, 0.586614251136780f, 0.492440819740295f,
+  0.586991965770721f, 0.492374241352081f, 0.587369561195374f, 0.492307394742966f,
+  0.587747097015381f, 0.492240220308304f, 0.588124632835388f, 0.492172777652740f,
+  0.588502109050751f, 0.492105036973953f, 0.588879525661469f, 0.492037028074265f,
+  0.589256882667542f, 0.491968721151352f, 0.589634180068970f, 0.491900116205215f,
+  0.590011477470398f, 0.491831213235855f, 0.590388655662537f, 0.491762012243271f,
+  0.590765833854675f, 0.491692543029785f, 0.591142892837524f, 0.491622805595398f,
+  0.591519951820374f, 0.491552740335464f, 0.591896951198578f, 0.491482406854630f,
+  0.592273890972137f, 0.491411775350571f, 0.592650771141052f, 0.491340845823288f,
+  0.593027591705322f, 0.491269648075104f, 0.593404352664948f, 0.491198152303696f,
+  0.593781054019928f, 0.491126358509064f, 0.594157755374908f, 0.491054296493530f,
+  0.594534337520599f, 0.490981936454773f, 0.594910860061646f, 0.490909278392792f,
+  0.595287382602692f, 0.490836352109909f, 0.595663845539093f, 0.490763127803802f,
+  0.596040189266205f, 0.490689605474472f, 0.596416532993317f, 0.490615785121918f,
+  0.596792817115784f, 0.490541696548462f, 0.597168982028961f, 0.490467309951782f,
+  0.597545146942139f, 0.490392625331879f, 0.597921252250671f, 0.490317672491074f,
+  0.598297297954559f, 0.490242421627045f, 0.598673284053802f, 0.490166902542114f,
+  0.599049210548401f, 0.490091055631638f, 0.599425077438354f, 0.490014940500259f,
+  0.599800884723663f, 0.489938557147980f, 0.600176632404327f, 0.489861875772476f,
+  0.600552320480347f, 0.489784896373749f, 0.600927948951721f, 0.489707618951797f,
+  0.601303517818451f, 0.489630073308945f, 0.601679027080536f, 0.489552229642868f,
+  0.602054476737976f, 0.489474087953568f, 0.602429866790771f, 0.489395678043365f,
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+  0.512270629405975f, -0.499849408864975f, 0.511887252330780f, -0.499858677387238f,
+  0.511503815650940f, -0.499867647886276f, 0.511120438575745f, -0.499876320362091f,
+  0.510737061500549f, -0.499884694814682f, 0.510353624820709f, -0.499892801046371f,
+  0.509970188140869f, -0.499900579452515f, 0.509586811065674f, -0.499908089637756f,
+  0.509203374385834f, -0.499915301799774f, 0.508819937705994f, -0.499922215938568f,
+  0.508436501026154f, -0.499928832054138f, 0.508053064346313f, -0.499935150146484f,
+  0.507669627666473f, -0.499941170215607f, 0.507286131381989f, -0.499946922063828f,
+  0.506902694702148f, -0.499952346086502f, 0.506519258022308f, -0.499957501888275f,
+  0.506135761737823f, -0.499962359666824f, 0.505752325057983f, -0.499966919422150f,
+  0.505368828773499f, -0.499971181154251f, 0.504985332489014f, -0.499975144863129f,
+  0.504601895809174f, -0.499978810548782f, 0.504218399524689f, -0.499982208013535f,
+  0.503834903240204f, -0.499985307455063f, 0.503451406955719f, -0.499988079071045f,
+  0.503067970275879f, -0.499990582466125f, 0.502684473991394f, -0.499992787837982f,
+  0.502300977706909f, -0.499994695186615f, 0.501917481422424f, -0.499996334314346f,
+  0.501533985137939f, -0.499997645616531f, 0.501150488853455f, -0.499998688697815f,
+  0.500766992568970f, -0.499999403953552f, 0.500383496284485f, -0.499999850988388f,
+};
+
+
+
+/**
+* @brief  Initialization function for the floating-point RFFT/RIFFT.
+* @deprecated Do not use this function.  It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed
+* in the future.
+* @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.
+* @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in]     fftLenReal     length of the FFT.
+* @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.
+* \par
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* This function also initializes Twiddle factor table.
+*/
+
+/**
+* @} end of RealFFT_Table group
+*/
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2U;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (float32_t *) realCoefA;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (float32_t *) realCoefB;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+    /* Init table modifier value */
+  case 8192U:
+    S->twidCoefRModifier = 1U;
+    break;
+  case 2048U:
+    S->twidCoefRModifier = 4U;
+    break;
+  case 512U:
+    S->twidCoefRModifier = 16U;
+    break;
+  case 128U:
+    S->twidCoefRModifier = 64U;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if (S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1U, 0U);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0U, 0U);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**
+   * @} end of RealFFT group
+   */
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c
new file mode 100644
index 0000000..3d1f229
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c
@@ -0,0 +1,2229 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_rfft_init_q15.c
+ * Description:  RFFT & RIFFT Q15 initialisation function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include "arm_const_structs.h"
+
+/**
+* @ingroup RealFFT
+*/
+
+/**
+ * @addtogroup RealFFT_Table Real FFT Tables
+* @{
+*/
+
+/**
+* \par
+* Generation fixed-point realCoefAQ15 array in Q15 format:
+* \par
+* n = 4096
+* 
for (i = 0; i < n; i++)
+*  {
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+*  } 

+* \par
+* Convert to fixed point Q15 format
+*       round(pATable[i] * pow(2, 15))
+*/
+const q15_t ALIGN4 realCoefAQ15[8192] = {
+    (q15_t)0x4000, (q15_t)0xc000, (q15_t)0x3ff3, (q15_t)0xc000, (q15_t)0x3fe7, (q15_t)0xc000, (q15_t)0x3fda, (q15_t)0xc000,
+    (q15_t)0x3fce, (q15_t)0xc000, (q15_t)0x3fc1, (q15_t)0xc000, (q15_t)0x3fb5, (q15_t)0xc000, (q15_t)0x3fa8, (q15_t)0xc000,
+    (q15_t)0x3f9b, (q15_t)0xc000, (q15_t)0x3f8f, (q15_t)0xc000, (q15_t)0x3f82, (q15_t)0xc000, (q15_t)0x3f76, (q15_t)0xc001,
+    (q15_t)0x3f69, (q15_t)0xc001, (q15_t)0x3f5d, (q15_t)0xc001, (q15_t)0x3f50, (q15_t)0xc001, (q15_t)0x3f44, (q15_t)0xc001,
+    (q15_t)0x3f37, (q15_t)0xc001, (q15_t)0x3f2a, (q15_t)0xc001, (q15_t)0x3f1e, (q15_t)0xc002, (q15_t)0x3f11, (q15_t)0xc002,
+    (q15_t)0x3f05, (q15_t)0xc002, (q15_t)0x3ef8, (q15_t)0xc002, (q15_t)0x3eec, (q15_t)0xc002, (q15_t)0x3edf, (q15_t)0xc003,
+    (q15_t)0x3ed2, (q15_t)0xc003, (q15_t)0x3ec6, (q15_t)0xc003, (q15_t)0x3eb9, (q15_t)0xc003, (q15_t)0x3ead, (q15_t)0xc004,
+    (q15_t)0x3ea0, (q15_t)0xc004, (q15_t)0x3e94, (q15_t)0xc004, (q15_t)0x3e87, (q15_t)0xc004, (q15_t)0x3e7a, (q15_t)0xc005,
+    (q15_t)0x3e6e, (q15_t)0xc005, (q15_t)0x3e61, (q15_t)0xc005, (q15_t)0x3e55, (q15_t)0xc006, (q15_t)0x3e48, (q15_t)0xc006,
+    (q15_t)0x3e3c, (q15_t)0xc006, (q15_t)0x3e2f, (q15_t)0xc007, (q15_t)0x3e23, (q15_t)0xc007, (q15_t)0x3e16, (q15_t)0xc007,
+    (q15_t)0x3e09, (q15_t)0xc008, (q15_t)0x3dfd, (q15_t)0xc008, (q15_t)0x3df0, (q15_t)0xc009, (q15_t)0x3de4, (q15_t)0xc009,
+    (q15_t)0x3dd7, (q15_t)0xc009, (q15_t)0x3dcb, (q15_t)0xc00a, (q15_t)0x3dbe, (q15_t)0xc00a, (q15_t)0x3db2, (q15_t)0xc00b,
+    (q15_t)0x3da5, (q15_t)0xc00b, (q15_t)0x3d98, (q15_t)0xc00c, (q15_t)0x3d8c, (q15_t)0xc00c, (q15_t)0x3d7f, (q15_t)0xc00d,
+    (q15_t)0x3d73, (q15_t)0xc00d, (q15_t)0x3d66, (q15_t)0xc00e, (q15_t)0x3d5a, (q15_t)0xc00e, (q15_t)0x3d4d, (q15_t)0xc00f,
+    (q15_t)0x3d40, (q15_t)0xc00f, (q15_t)0x3d34, (q15_t)0xc010, (q15_t)0x3d27, (q15_t)0xc010, (q15_t)0x3d1b, (q15_t)0xc011,
+    (q15_t)0x3d0e, (q15_t)0xc011, (q15_t)0x3d02, (q15_t)0xc012, (q15_t)0x3cf5, (q15_t)0xc013, (q15_t)0x3ce9, (q15_t)0xc013,
+    (q15_t)0x3cdc, (q15_t)0xc014, (q15_t)0x3cd0, (q15_t)0xc014, (q15_t)0x3cc3, (q15_t)0xc015, (q15_t)0x3cb6, (q15_t)0xc016,
+    (q15_t)0x3caa, (q15_t)0xc016, (q15_t)0x3c9d, (q15_t)0xc017, (q15_t)0x3c91, (q15_t)0xc018, (q15_t)0x3c84, (q15_t)0xc018,
+    (q15_t)0x3c78, (q15_t)0xc019, (q15_t)0x3c6b, (q15_t)0xc01a, (q15_t)0x3c5f, (q15_t)0xc01a, (q15_t)0x3c52, (q15_t)0xc01b,
+    (q15_t)0x3c45, (q15_t)0xc01c, (q15_t)0x3c39, (q15_t)0xc01d, (q15_t)0x3c2c, (q15_t)0xc01d, (q15_t)0x3c20, (q15_t)0xc01e,
+    (q15_t)0x3c13, (q15_t)0xc01f, (q15_t)0x3c07, (q15_t)0xc020, (q15_t)0x3bfa, (q15_t)0xc020, (q15_t)0x3bee, (q15_t)0xc021,
+    (q15_t)0x3be1, (q15_t)0xc022, (q15_t)0x3bd5, (q15_t)0xc023, (q15_t)0x3bc8, (q15_t)0xc024, (q15_t)0x3bbc, (q15_t)0xc024,
+    (q15_t)0x3baf, (q15_t)0xc025, (q15_t)0x3ba2, (q15_t)0xc026, (q15_t)0x3b96, (q15_t)0xc027, (q15_t)0x3b89, (q15_t)0xc028,
+    (q15_t)0x3b7d, (q15_t)0xc029, (q15_t)0x3b70, (q15_t)0xc02a, (q15_t)0x3b64, (q15_t)0xc02b, (q15_t)0x3b57, (q15_t)0xc02b,
+    (q15_t)0x3b4b, (q15_t)0xc02c, (q15_t)0x3b3e, (q15_t)0xc02d, (q15_t)0x3b32, (q15_t)0xc02e, (q15_t)0x3b25, (q15_t)0xc02f,
+    (q15_t)0x3b19, (q15_t)0xc030, (q15_t)0x3b0c, (q15_t)0xc031, (q15_t)0x3b00, (q15_t)0xc032, (q15_t)0x3af3, (q15_t)0xc033,
+    (q15_t)0x3ae6, (q15_t)0xc034, (q15_t)0x3ada, (q15_t)0xc035, (q15_t)0x3acd, (q15_t)0xc036, (q15_t)0x3ac1, (q15_t)0xc037,
+    (q15_t)0x3ab4, (q15_t)0xc038, (q15_t)0x3aa8, (q15_t)0xc039, (q15_t)0x3a9b, (q15_t)0xc03a, (q15_t)0x3a8f, (q15_t)0xc03b,
+    (q15_t)0x3a82, (q15_t)0xc03c, (q15_t)0x3a76, (q15_t)0xc03d, (q15_t)0x3a69, (q15_t)0xc03f, (q15_t)0x3a5d, (q15_t)0xc040,
+    (q15_t)0x3a50, (q15_t)0xc041, (q15_t)0x3a44, (q15_t)0xc042, (q15_t)0x3a37, (q15_t)0xc043, (q15_t)0x3a2b, (q15_t)0xc044,
+    (q15_t)0x3a1e, (q15_t)0xc045, (q15_t)0x3a12, (q15_t)0xc047, (q15_t)0x3a05, (q15_t)0xc048, (q15_t)0x39f9, (q15_t)0xc049,
+    (q15_t)0x39ec, (q15_t)0xc04a, (q15_t)0x39e0, (q15_t)0xc04b, (q15_t)0x39d3, (q15_t)0xc04c, (q15_t)0x39c7, (q15_t)0xc04e,
+    (q15_t)0x39ba, (q15_t)0xc04f, (q15_t)0x39ae, (q15_t)0xc050, (q15_t)0x39a1, (q15_t)0xc051, (q15_t)0x3995, (q15_t)0xc053,
+    (q15_t)0x3988, (q15_t)0xc054, (q15_t)0x397c, (q15_t)0xc055, (q15_t)0x396f, (q15_t)0xc056, (q15_t)0x3963, (q15_t)0xc058,
+    (q15_t)0x3956, (q15_t)0xc059, (q15_t)0x394a, (q15_t)0xc05a, (q15_t)0x393d, (q15_t)0xc05c, (q15_t)0x3931, (q15_t)0xc05d,
+    (q15_t)0x3924, (q15_t)0xc05e, (q15_t)0x3918, (q15_t)0xc060, (q15_t)0x390b, (q15_t)0xc061, (q15_t)0x38ff, (q15_t)0xc062,
+    (q15_t)0x38f2, (q15_t)0xc064, (q15_t)0x38e6, (q15_t)0xc065, (q15_t)0x38d9, (q15_t)0xc067, (q15_t)0x38cd, (q15_t)0xc068,
+    (q15_t)0x38c0, (q15_t)0xc069, (q15_t)0x38b4, (q15_t)0xc06b, (q15_t)0x38a7, (q15_t)0xc06c, (q15_t)0x389b, (q15_t)0xc06e,
+    (q15_t)0x388e, (q15_t)0xc06f, (q15_t)0x3882, (q15_t)0xc071, (q15_t)0x3875, (q15_t)0xc072, (q15_t)0x3869, (q15_t)0xc074,
+    (q15_t)0x385c, (q15_t)0xc075, (q15_t)0x3850, (q15_t)0xc077, (q15_t)0x3843, (q15_t)0xc078, (q15_t)0x3837, (q15_t)0xc07a,
+    (q15_t)0x382a, (q15_t)0xc07b, (q15_t)0x381e, (q15_t)0xc07d, (q15_t)0x3811, (q15_t)0xc07e, (q15_t)0x3805, (q15_t)0xc080,
+    (q15_t)0x37f9, (q15_t)0xc081, (q15_t)0x37ec, (q15_t)0xc083, (q15_t)0x37e0, (q15_t)0xc085, (q15_t)0x37d3, (q15_t)0xc086,
+    (q15_t)0x37c7, (q15_t)0xc088, (q15_t)0x37ba, (q15_t)0xc089, (q15_t)0x37ae, (q15_t)0xc08b, (q15_t)0x37a1, (q15_t)0xc08d,
+    (q15_t)0x3795, (q15_t)0xc08e, (q15_t)0x3788, (q15_t)0xc090, (q15_t)0x377c, (q15_t)0xc092, (q15_t)0x376f, (q15_t)0xc093,
+    (q15_t)0x3763, (q15_t)0xc095, (q15_t)0x3757, (q15_t)0xc097, (q15_t)0x374a, (q15_t)0xc098, (q15_t)0x373e, (q15_t)0xc09a,
+    (q15_t)0x3731, (q15_t)0xc09c, (q15_t)0x3725, (q15_t)0xc09e, (q15_t)0x3718, (q15_t)0xc09f, (q15_t)0x370c, (q15_t)0xc0a1,
+    (q15_t)0x36ff, (q15_t)0xc0a3, (q15_t)0x36f3, (q15_t)0xc0a5, (q15_t)0x36e7, (q15_t)0xc0a6, (q15_t)0x36da, (q15_t)0xc0a8,
+    (q15_t)0x36ce, (q15_t)0xc0aa, (q15_t)0x36c1, (q15_t)0xc0ac, (q15_t)0x36b5, (q15_t)0xc0ae, (q15_t)0x36a8, (q15_t)0xc0af,
+    (q15_t)0x369c, (q15_t)0xc0b1, (q15_t)0x3690, (q15_t)0xc0b3, (q15_t)0x3683, (q15_t)0xc0b5, (q15_t)0x3677, (q15_t)0xc0b7,
+    (q15_t)0x366a, (q15_t)0xc0b9, (q15_t)0x365e, (q15_t)0xc0bb, (q15_t)0x3651, (q15_t)0xc0bd, (q15_t)0x3645, (q15_t)0xc0be,
+    (q15_t)0x3639, (q15_t)0xc0c0, (q15_t)0x362c, (q15_t)0xc0c2, (q15_t)0x3620, (q15_t)0xc0c4, (q15_t)0x3613, (q15_t)0xc0c6,
+    (q15_t)0x3607, (q15_t)0xc0c8, (q15_t)0x35fa, (q15_t)0xc0ca, (q15_t)0x35ee, (q15_t)0xc0cc, (q15_t)0x35e2, (q15_t)0xc0ce,
+    (q15_t)0x35d5, (q15_t)0xc0d0, (q15_t)0x35c9, (q15_t)0xc0d2, (q15_t)0x35bc, (q15_t)0xc0d4, (q15_t)0x35b0, (q15_t)0xc0d6,
+    (q15_t)0x35a4, (q15_t)0xc0d8, (q15_t)0x3597, (q15_t)0xc0da, (q15_t)0x358b, (q15_t)0xc0dc, (q15_t)0x357e, (q15_t)0xc0de,
+    (q15_t)0x3572, (q15_t)0xc0e0, (q15_t)0x3566, (q15_t)0xc0e2, (q15_t)0x3559, (q15_t)0xc0e4, (q15_t)0x354d, (q15_t)0xc0e7,
+    (q15_t)0x3540, (q15_t)0xc0e9, (q15_t)0x3534, (q15_t)0xc0eb, (q15_t)0x3528, (q15_t)0xc0ed, (q15_t)0x351b, (q15_t)0xc0ef,
+    (q15_t)0x350f, (q15_t)0xc0f1, (q15_t)0x3503, (q15_t)0xc0f3, (q15_t)0x34f6, (q15_t)0xc0f6, (q15_t)0x34ea, (q15_t)0xc0f8,
+    (q15_t)0x34dd, (q15_t)0xc0fa, (q15_t)0x34d1, (q15_t)0xc0fc, (q15_t)0x34c5, (q15_t)0xc0fe, (q15_t)0x34b8, (q15_t)0xc100,
+    (q15_t)0x34ac, (q15_t)0xc103, (q15_t)0x34a0, (q15_t)0xc105, (q15_t)0x3493, (q15_t)0xc107, (q15_t)0x3487, (q15_t)0xc109,
+    (q15_t)0x347b, (q15_t)0xc10c, (q15_t)0x346e, (q15_t)0xc10e, (q15_t)0x3462, (q15_t)0xc110, (q15_t)0x3455, (q15_t)0xc113,
+    (q15_t)0x3449, (q15_t)0xc115, (q15_t)0x343d, (q15_t)0xc117, (q15_t)0x3430, (q15_t)0xc119, (q15_t)0x3424, (q15_t)0xc11c,
+    (q15_t)0x3418, (q15_t)0xc11e, (q15_t)0x340b, (q15_t)0xc120, (q15_t)0x33ff, (q15_t)0xc123, (q15_t)0x33f3, (q15_t)0xc125,
+    (q15_t)0x33e6, (q15_t)0xc128, (q15_t)0x33da, (q15_t)0xc12a, (q15_t)0x33ce, (q15_t)0xc12c, (q15_t)0x33c1, (q15_t)0xc12f,
+    (q15_t)0x33b5, (q15_t)0xc131, (q15_t)0x33a9, (q15_t)0xc134, (q15_t)0x339c, (q15_t)0xc136, (q15_t)0x3390, (q15_t)0xc138,
+    (q15_t)0x3384, (q15_t)0xc13b, (q15_t)0x3377, (q15_t)0xc13d, (q15_t)0x336b, (q15_t)0xc140, (q15_t)0x335f, (q15_t)0xc142,
+    (q15_t)0x3352, (q15_t)0xc145, (q15_t)0x3346, (q15_t)0xc147, (q15_t)0x333a, (q15_t)0xc14a, (q15_t)0x332d, (q15_t)0xc14c,
+    (q15_t)0x3321, (q15_t)0xc14f, (q15_t)0x3315, (q15_t)0xc151, (q15_t)0x3308, (q15_t)0xc154, (q15_t)0x32fc, (q15_t)0xc156,
+    (q15_t)0x32f0, (q15_t)0xc159, (q15_t)0x32e4, (q15_t)0xc15b, (q15_t)0x32d7, (q15_t)0xc15e, (q15_t)0x32cb, (q15_t)0xc161,
+    (q15_t)0x32bf, (q15_t)0xc163, (q15_t)0x32b2, (q15_t)0xc166, (q15_t)0x32a6, (q15_t)0xc168, (q15_t)0x329a, (q15_t)0xc16b,
+    (q15_t)0x328e, (q15_t)0xc16e, (q15_t)0x3281, (q15_t)0xc170, (q15_t)0x3275, (q15_t)0xc173, (q15_t)0x3269, (q15_t)0xc176,
+    (q15_t)0x325c, (q15_t)0xc178, (q15_t)0x3250, (q15_t)0xc17b, (q15_t)0x3244, (q15_t)0xc17e, (q15_t)0x3238, (q15_t)0xc180,
+    (q15_t)0x322b, (q15_t)0xc183, (q15_t)0x321f, (q15_t)0xc186, (q15_t)0x3213, (q15_t)0xc189, (q15_t)0x3207, (q15_t)0xc18b,
+    (q15_t)0x31fa, (q15_t)0xc18e, (q15_t)0x31ee, (q15_t)0xc191, (q15_t)0x31e2, (q15_t)0xc194, (q15_t)0x31d5, (q15_t)0xc196,
+    (q15_t)0x31c9, (q15_t)0xc199, (q15_t)0x31bd, (q15_t)0xc19c, (q15_t)0x31b1, (q15_t)0xc19f, (q15_t)0x31a4, (q15_t)0xc1a2,
+    (q15_t)0x3198, (q15_t)0xc1a4, (q15_t)0x318c, (q15_t)0xc1a7, (q15_t)0x3180, (q15_t)0xc1aa, (q15_t)0x3174, (q15_t)0xc1ad,
+    (q15_t)0x3167, (q15_t)0xc1b0, (q15_t)0x315b, (q15_t)0xc1b3, (q15_t)0x314f, (q15_t)0xc1b6, (q15_t)0x3143, (q15_t)0xc1b8,
+    (q15_t)0x3136, (q15_t)0xc1bb, (q15_t)0x312a, (q15_t)0xc1be, (q15_t)0x311e, (q15_t)0xc1c1, (q15_t)0x3112, (q15_t)0xc1c4,
+    (q15_t)0x3105, (q15_t)0xc1c7, (q15_t)0x30f9, (q15_t)0xc1ca, (q15_t)0x30ed, (q15_t)0xc1cd, (q15_t)0x30e1, (q15_t)0xc1d0,
+    (q15_t)0x30d5, (q15_t)0xc1d3, (q15_t)0x30c8, (q15_t)0xc1d6, (q15_t)0x30bc, (q15_t)0xc1d9, (q15_t)0x30b0, (q15_t)0xc1dc,
+    (q15_t)0x30a4, (q15_t)0xc1df, (q15_t)0x3098, (q15_t)0xc1e2, (q15_t)0x308b, (q15_t)0xc1e5, (q15_t)0x307f, (q15_t)0xc1e8,
+    (q15_t)0x3073, (q15_t)0xc1eb, (q15_t)0x3067, (q15_t)0xc1ee, (q15_t)0x305b, (q15_t)0xc1f1, (q15_t)0x304e, (q15_t)0xc1f4,
+    (q15_t)0x3042, (q15_t)0xc1f7, (q15_t)0x3036, (q15_t)0xc1fa, (q15_t)0x302a, (q15_t)0xc1fd, (q15_t)0x301e, (q15_t)0xc201,
+    (q15_t)0x3012, (q15_t)0xc204, (q15_t)0x3005, (q15_t)0xc207, (q15_t)0x2ff9, (q15_t)0xc20a, (q15_t)0x2fed, (q15_t)0xc20d,
+    (q15_t)0x2fe1, (q15_t)0xc210, (q15_t)0x2fd5, (q15_t)0xc213, (q15_t)0x2fc9, (q15_t)0xc217, (q15_t)0x2fbc, (q15_t)0xc21a,
+    (q15_t)0x2fb0, (q15_t)0xc21d, (q15_t)0x2fa4, (q15_t)0xc220, (q15_t)0x2f98, (q15_t)0xc223, (q15_t)0x2f8c, (q15_t)0xc227,
+    (q15_t)0x2f80, (q15_t)0xc22a, (q15_t)0x2f74, (q15_t)0xc22d, (q15_t)0x2f67, (q15_t)0xc230, (q15_t)0x2f5b, (q15_t)0xc234,
+    (q15_t)0x2f4f, (q15_t)0xc237, (q15_t)0x2f43, (q15_t)0xc23a, (q15_t)0x2f37, (q15_t)0xc23e, (q15_t)0x2f2b, (q15_t)0xc241,
+    (q15_t)0x2f1f, (q15_t)0xc244, (q15_t)0x2f13, (q15_t)0xc247, (q15_t)0x2f06, (q15_t)0xc24b, (q15_t)0x2efa, (q15_t)0xc24e,
+    (q15_t)0x2eee, (q15_t)0xc251, (q15_t)0x2ee2, (q15_t)0xc255, (q15_t)0x2ed6, (q15_t)0xc258, (q15_t)0x2eca, (q15_t)0xc25c,
+    (q15_t)0x2ebe, (q15_t)0xc25f, (q15_t)0x2eb2, (q15_t)0xc262, (q15_t)0x2ea6, (q15_t)0xc266, (q15_t)0x2e99, (q15_t)0xc269,
+    (q15_t)0x2e8d, (q15_t)0xc26d, (q15_t)0x2e81, (q15_t)0xc270, (q15_t)0x2e75, (q15_t)0xc273, (q15_t)0x2e69, (q15_t)0xc277,
+    (q15_t)0x2e5d, (q15_t)0xc27a, (q15_t)0x2e51, (q15_t)0xc27e, (q15_t)0x2e45, (q15_t)0xc281, (q15_t)0x2e39, (q15_t)0xc285,
+    (q15_t)0x2e2d, (q15_t)0xc288, (q15_t)0x2e21, (q15_t)0xc28c, (q15_t)0x2e15, (q15_t)0xc28f, (q15_t)0x2e09, (q15_t)0xc293,
+    (q15_t)0x2dfc, (q15_t)0xc296, (q15_t)0x2df0, (q15_t)0xc29a, (q15_t)0x2de4, (q15_t)0xc29d, (q15_t)0x2dd8, (q15_t)0xc2a1,
+    (q15_t)0x2dcc, (q15_t)0xc2a5, (q15_t)0x2dc0, (q15_t)0xc2a8, (q15_t)0x2db4, (q15_t)0xc2ac, (q15_t)0x2da8, (q15_t)0xc2af,
+    (q15_t)0x2d9c, (q15_t)0xc2b3, (q15_t)0x2d90, (q15_t)0xc2b7, (q15_t)0x2d84, (q15_t)0xc2ba, (q15_t)0x2d78, (q15_t)0xc2be,
+    (q15_t)0x2d6c, (q15_t)0xc2c1, (q15_t)0x2d60, (q15_t)0xc2c5, (q15_t)0x2d54, (q15_t)0xc2c9, (q15_t)0x2d48, (q15_t)0xc2cc,
+    (q15_t)0x2d3c, (q15_t)0xc2d0, (q15_t)0x2d30, (q15_t)0xc2d4, (q15_t)0x2d24, (q15_t)0xc2d8, (q15_t)0x2d18, (q15_t)0xc2db,
+    (q15_t)0x2d0c, (q15_t)0xc2df, (q15_t)0x2d00, (q15_t)0xc2e3, (q15_t)0x2cf4, (q15_t)0xc2e6, (q15_t)0x2ce8, (q15_t)0xc2ea,
+    (q15_t)0x2cdc, (q15_t)0xc2ee, (q15_t)0x2cd0, (q15_t)0xc2f2, (q15_t)0x2cc4, (q15_t)0xc2f5, (q15_t)0x2cb8, (q15_t)0xc2f9,
+    (q15_t)0x2cac, (q15_t)0xc2fd, (q15_t)0x2ca0, (q15_t)0xc301, (q15_t)0x2c94, (q15_t)0xc305, (q15_t)0x2c88, (q15_t)0xc308,
+    (q15_t)0x2c7c, (q15_t)0xc30c, (q15_t)0x2c70, (q15_t)0xc310, (q15_t)0x2c64, (q15_t)0xc314, (q15_t)0x2c58, (q15_t)0xc318,
+    (q15_t)0x2c4c, (q15_t)0xc31c, (q15_t)0x2c40, (q15_t)0xc320, (q15_t)0x2c34, (q15_t)0xc323, (q15_t)0x2c28, (q15_t)0xc327,
+    (q15_t)0x2c1c, (q15_t)0xc32b, (q15_t)0x2c10, (q15_t)0xc32f, (q15_t)0x2c05, (q15_t)0xc333, (q15_t)0x2bf9, (q15_t)0xc337,
+    (q15_t)0x2bed, (q15_t)0xc33b, (q15_t)0x2be1, (q15_t)0xc33f, (q15_t)0x2bd5, (q15_t)0xc343, (q15_t)0x2bc9, (q15_t)0xc347,
+    (q15_t)0x2bbd, (q15_t)0xc34b, (q15_t)0x2bb1, (q15_t)0xc34f, (q15_t)0x2ba5, (q15_t)0xc353, (q15_t)0x2b99, (q15_t)0xc357,
+    (q15_t)0x2b8d, (q15_t)0xc35b, (q15_t)0x2b81, (q15_t)0xc35f, (q15_t)0x2b75, (q15_t)0xc363, (q15_t)0x2b6a, (q15_t)0xc367,
+    (q15_t)0x2b5e, (q15_t)0xc36b, (q15_t)0x2b52, (q15_t)0xc36f, (q15_t)0x2b46, (q15_t)0xc373, (q15_t)0x2b3a, (q15_t)0xc377,
+    (q15_t)0x2b2e, (q15_t)0xc37b, (q15_t)0x2b22, (q15_t)0xc37f, (q15_t)0x2b16, (q15_t)0xc383, (q15_t)0x2b0a, (q15_t)0xc387,
+    (q15_t)0x2aff, (q15_t)0xc38c, (q15_t)0x2af3, (q15_t)0xc390, (q15_t)0x2ae7, (q15_t)0xc394, (q15_t)0x2adb, (q15_t)0xc398,
+    (q15_t)0x2acf, (q15_t)0xc39c, (q15_t)0x2ac3, (q15_t)0xc3a0, (q15_t)0x2ab7, (q15_t)0xc3a5, (q15_t)0x2aac, (q15_t)0xc3a9,
+    (q15_t)0x2aa0, (q15_t)0xc3ad, (q15_t)0x2a94, (q15_t)0xc3b1, (q15_t)0x2a88, (q15_t)0xc3b5, (q15_t)0x2a7c, (q15_t)0xc3ba,
+    (q15_t)0x2a70, (q15_t)0xc3be, (q15_t)0x2a65, (q15_t)0xc3c2, (q15_t)0x2a59, (q15_t)0xc3c6, (q15_t)0x2a4d, (q15_t)0xc3ca,
+    (q15_t)0x2a41, (q15_t)0xc3cf, (q15_t)0x2a35, (q15_t)0xc3d3, (q15_t)0x2a29, (q15_t)0xc3d7, (q15_t)0x2a1e, (q15_t)0xc3dc,
+    (q15_t)0x2a12, (q15_t)0xc3e0, (q15_t)0x2a06, (q15_t)0xc3e4, (q15_t)0x29fa, (q15_t)0xc3e9, (q15_t)0x29ee, (q15_t)0xc3ed,
+    (q15_t)0x29e3, (q15_t)0xc3f1, (q15_t)0x29d7, (q15_t)0xc3f6, (q15_t)0x29cb, (q15_t)0xc3fa, (q15_t)0x29bf, (q15_t)0xc3fe,
+    (q15_t)0x29b4, (q15_t)0xc403, (q15_t)0x29a8, (q15_t)0xc407, (q15_t)0x299c, (q15_t)0xc40b, (q15_t)0x2990, (q15_t)0xc410,
+    (q15_t)0x2984, (q15_t)0xc414, (q15_t)0x2979, (q15_t)0xc419, (q15_t)0x296d, (q15_t)0xc41d, (q15_t)0x2961, (q15_t)0xc422,
+    (q15_t)0x2955, (q15_t)0xc426, (q15_t)0x294a, (q15_t)0xc42a, (q15_t)0x293e, (q15_t)0xc42f, (q15_t)0x2932, (q15_t)0xc433,
+    (q15_t)0x2926, (q15_t)0xc438, (q15_t)0x291b, (q15_t)0xc43c, (q15_t)0x290f, (q15_t)0xc441, (q15_t)0x2903, (q15_t)0xc445,
+    (q15_t)0x28f7, (q15_t)0xc44a, (q15_t)0x28ec, (q15_t)0xc44e, (q15_t)0x28e0, (q15_t)0xc453, (q15_t)0x28d4, (q15_t)0xc457,
+    (q15_t)0x28c9, (q15_t)0xc45c, (q15_t)0x28bd, (q15_t)0xc461, (q15_t)0x28b1, (q15_t)0xc465, (q15_t)0x28a5, (q15_t)0xc46a,
+    (q15_t)0x289a, (q15_t)0xc46e, (q15_t)0x288e, (q15_t)0xc473, (q15_t)0x2882, (q15_t)0xc478, (q15_t)0x2877, (q15_t)0xc47c,
+    (q15_t)0x286b, (q15_t)0xc481, (q15_t)0x285f, (q15_t)0xc485, (q15_t)0x2854, (q15_t)0xc48a, (q15_t)0x2848, (q15_t)0xc48f,
+    (q15_t)0x283c, (q15_t)0xc493, (q15_t)0x2831, (q15_t)0xc498, (q15_t)0x2825, (q15_t)0xc49d, (q15_t)0x2819, (q15_t)0xc4a1,
+    (q15_t)0x280e, (q15_t)0xc4a6, (q15_t)0x2802, (q15_t)0xc4ab, (q15_t)0x27f6, (q15_t)0xc4b0, (q15_t)0x27eb, (q15_t)0xc4b4,
+    (q15_t)0x27df, (q15_t)0xc4b9, (q15_t)0x27d3, (q15_t)0xc4be, (q15_t)0x27c8, (q15_t)0xc4c2, (q15_t)0x27bc, (q15_t)0xc4c7,
+    (q15_t)0x27b1, (q15_t)0xc4cc, (q15_t)0x27a5, (q15_t)0xc4d1, (q15_t)0x2799, (q15_t)0xc4d6, (q15_t)0x278e, (q15_t)0xc4da,
+    (q15_t)0x2782, (q15_t)0xc4df, (q15_t)0x2777, (q15_t)0xc4e4, (q15_t)0x276b, (q15_t)0xc4e9, (q15_t)0x275f, (q15_t)0xc4ee,
+    (q15_t)0x2754, (q15_t)0xc4f2, (q15_t)0x2748, (q15_t)0xc4f7, (q15_t)0x273d, (q15_t)0xc4fc, (q15_t)0x2731, (q15_t)0xc501,
+    (q15_t)0x2725, (q15_t)0xc506, (q15_t)0x271a, (q15_t)0xc50b, (q15_t)0x270e, (q15_t)0xc510, (q15_t)0x2703, (q15_t)0xc515,
+    (q15_t)0x26f7, (q15_t)0xc51a, (q15_t)0x26ec, (q15_t)0xc51e, (q15_t)0x26e0, (q15_t)0xc523, (q15_t)0x26d4, (q15_t)0xc528,
+    (q15_t)0x26c9, (q15_t)0xc52d, (q15_t)0x26bd, (q15_t)0xc532, (q15_t)0x26b2, (q15_t)0xc537, (q15_t)0x26a6, (q15_t)0xc53c,
+    (q15_t)0x269b, (q15_t)0xc541, (q15_t)0x268f, (q15_t)0xc546, (q15_t)0x2684, (q15_t)0xc54b, (q15_t)0x2678, (q15_t)0xc550,
+    (q15_t)0x266d, (q15_t)0xc555, (q15_t)0x2661, (q15_t)0xc55a, (q15_t)0x2656, (q15_t)0xc55f, (q15_t)0x264a, (q15_t)0xc564,
+    (q15_t)0x263f, (q15_t)0xc569, (q15_t)0x2633, (q15_t)0xc56e, (q15_t)0x2628, (q15_t)0xc573, (q15_t)0x261c, (q15_t)0xc578,
+    (q15_t)0x2611, (q15_t)0xc57e, (q15_t)0x2605, (q15_t)0xc583, (q15_t)0x25fa, (q15_t)0xc588, (q15_t)0x25ee, (q15_t)0xc58d,
+    (q15_t)0x25e3, (q15_t)0xc592, (q15_t)0x25d7, (q15_t)0xc597, (q15_t)0x25cc, (q15_t)0xc59c, (q15_t)0x25c0, (q15_t)0xc5a1,
+    (q15_t)0x25b5, (q15_t)0xc5a7, (q15_t)0x25a9, (q15_t)0xc5ac, (q15_t)0x259e, (q15_t)0xc5b1, (q15_t)0x2592, (q15_t)0xc5b6,
+    (q15_t)0x2587, (q15_t)0xc5bb, (q15_t)0x257c, (q15_t)0xc5c1, (q15_t)0x2570, (q15_t)0xc5c6, (q15_t)0x2565, (q15_t)0xc5cb,
+    (q15_t)0x2559, (q15_t)0xc5d0, (q15_t)0x254e, (q15_t)0xc5d5, (q15_t)0x2542, (q15_t)0xc5db, (q15_t)0x2537, (q15_t)0xc5e0,
+    (q15_t)0x252c, (q15_t)0xc5e5, (q15_t)0x2520, (q15_t)0xc5ea, (q15_t)0x2515, (q15_t)0xc5f0, (q15_t)0x2509, (q15_t)0xc5f5,
+    (q15_t)0x24fe, (q15_t)0xc5fa, (q15_t)0x24f3, (q15_t)0xc600, (q15_t)0x24e7, (q15_t)0xc605, (q15_t)0x24dc, (q15_t)0xc60a,
+    (q15_t)0x24d0, (q15_t)0xc610, (q15_t)0x24c5, (q15_t)0xc615, (q15_t)0x24ba, (q15_t)0xc61a, (q15_t)0x24ae, (q15_t)0xc620,
+    (q15_t)0x24a3, (q15_t)0xc625, (q15_t)0x2498, (q15_t)0xc62a, (q15_t)0x248c, (q15_t)0xc630, (q15_t)0x2481, (q15_t)0xc635,
+    (q15_t)0x2476, (q15_t)0xc63b, (q15_t)0x246a, (q15_t)0xc640, (q15_t)0x245f, (q15_t)0xc645, (q15_t)0x2454, (q15_t)0xc64b,
+    (q15_t)0x2448, (q15_t)0xc650, (q15_t)0x243d, (q15_t)0xc656, (q15_t)0x2432, (q15_t)0xc65b, (q15_t)0x2426, (q15_t)0xc661,
+    (q15_t)0x241b, (q15_t)0xc666, (q15_t)0x2410, (q15_t)0xc66c, (q15_t)0x2404, (q15_t)0xc671, (q15_t)0x23f9, (q15_t)0xc677,
+    (q15_t)0x23ee, (q15_t)0xc67c, (q15_t)0x23e2, (q15_t)0xc682, (q15_t)0x23d7, (q15_t)0xc687, (q15_t)0x23cc, (q15_t)0xc68d,
+    (q15_t)0x23c1, (q15_t)0xc692, (q15_t)0x23b5, (q15_t)0xc698, (q15_t)0x23aa, (q15_t)0xc69d, (q15_t)0x239f, (q15_t)0xc6a3,
+    (q15_t)0x2394, (q15_t)0xc6a8, (q15_t)0x2388, (q15_t)0xc6ae, (q15_t)0x237d, (q15_t)0xc6b4, (q15_t)0x2372, (q15_t)0xc6b9,
+    (q15_t)0x2367, (q15_t)0xc6bf, (q15_t)0x235b, (q15_t)0xc6c5, (q15_t)0x2350, (q15_t)0xc6ca, (q15_t)0x2345, (q15_t)0xc6d0,
+    (q15_t)0x233a, (q15_t)0xc6d5, (q15_t)0x232e, (q15_t)0xc6db, (q15_t)0x2323, (q15_t)0xc6e1, (q15_t)0x2318, (q15_t)0xc6e6,
+    (q15_t)0x230d, (q15_t)0xc6ec, (q15_t)0x2301, (q15_t)0xc6f2, (q15_t)0x22f6, (q15_t)0xc6f7, (q15_t)0x22eb, (q15_t)0xc6fd,
+    (q15_t)0x22e0, (q15_t)0xc703, (q15_t)0x22d5, (q15_t)0xc709, (q15_t)0x22ca, (q15_t)0xc70e, (q15_t)0x22be, (q15_t)0xc714,
+    (q15_t)0x22b3, (q15_t)0xc71a, (q15_t)0x22a8, (q15_t)0xc720, (q15_t)0x229d, (q15_t)0xc725, (q15_t)0x2292, (q15_t)0xc72b,
+    (q15_t)0x2287, (q15_t)0xc731, (q15_t)0x227b, (q15_t)0xc737, (q15_t)0x2270, (q15_t)0xc73d, (q15_t)0x2265, (q15_t)0xc742,
+    (q15_t)0x225a, (q15_t)0xc748, (q15_t)0x224f, (q15_t)0xc74e, (q15_t)0x2244, (q15_t)0xc754, (q15_t)0x2239, (q15_t)0xc75a,
+    (q15_t)0x222d, (q15_t)0xc75f, (q15_t)0x2222, (q15_t)0xc765, (q15_t)0x2217, (q15_t)0xc76b, (q15_t)0x220c, (q15_t)0xc771,
+    (q15_t)0x2201, (q15_t)0xc777, (q15_t)0x21f6, (q15_t)0xc77d, (q15_t)0x21eb, (q15_t)0xc783, (q15_t)0x21e0, (q15_t)0xc789,
+    (q15_t)0x21d5, (q15_t)0xc78f, (q15_t)0x21ca, (q15_t)0xc795, (q15_t)0x21be, (q15_t)0xc79a, (q15_t)0x21b3, (q15_t)0xc7a0,
+    (q15_t)0x21a8, (q15_t)0xc7a6, (q15_t)0x219d, (q15_t)0xc7ac, (q15_t)0x2192, (q15_t)0xc7b2, (q15_t)0x2187, (q15_t)0xc7b8,
+    (q15_t)0x217c, (q15_t)0xc7be, (q15_t)0x2171, (q15_t)0xc7c4, (q15_t)0x2166, (q15_t)0xc7ca, (q15_t)0x215b, (q15_t)0xc7d0,
+    (q15_t)0x2150, (q15_t)0xc7d6, (q15_t)0x2145, (q15_t)0xc7dc, (q15_t)0x213a, (q15_t)0xc7e2, (q15_t)0x212f, (q15_t)0xc7e8,
+    (q15_t)0x2124, (q15_t)0xc7ee, (q15_t)0x2119, (q15_t)0xc7f5, (q15_t)0x210e, (q15_t)0xc7fb, (q15_t)0x2103, (q15_t)0xc801,
+    (q15_t)0x20f8, (q15_t)0xc807, (q15_t)0x20ed, (q15_t)0xc80d, (q15_t)0x20e2, (q15_t)0xc813, (q15_t)0x20d7, (q15_t)0xc819,
+    (q15_t)0x20cc, (q15_t)0xc81f, (q15_t)0x20c1, (q15_t)0xc825, (q15_t)0x20b6, (q15_t)0xc82b, (q15_t)0x20ab, (q15_t)0xc832,
+    (q15_t)0x20a0, (q15_t)0xc838, (q15_t)0x2095, (q15_t)0xc83e, (q15_t)0x208a, (q15_t)0xc844, (q15_t)0x207f, (q15_t)0xc84a,
+    (q15_t)0x2074, (q15_t)0xc850, (q15_t)0x2069, (q15_t)0xc857, (q15_t)0x205e, (q15_t)0xc85d, (q15_t)0x2054, (q15_t)0xc863,
+    (q15_t)0x2049, (q15_t)0xc869, (q15_t)0x203e, (q15_t)0xc870, (q15_t)0x2033, (q15_t)0xc876, (q15_t)0x2028, (q15_t)0xc87c,
+    (q15_t)0x201d, (q15_t)0xc882, (q15_t)0x2012, (q15_t)0xc889, (q15_t)0x2007, (q15_t)0xc88f, (q15_t)0x1ffc, (q15_t)0xc895,
+    (q15_t)0x1ff1, (q15_t)0xc89b, (q15_t)0x1fe7, (q15_t)0xc8a2, (q15_t)0x1fdc, (q15_t)0xc8a8, (q15_t)0x1fd1, (q15_t)0xc8ae,
+    (q15_t)0x1fc6, (q15_t)0xc8b5, (q15_t)0x1fbb, (q15_t)0xc8bb, (q15_t)0x1fb0, (q15_t)0xc8c1, (q15_t)0x1fa5, (q15_t)0xc8c8,
+    (q15_t)0x1f9b, (q15_t)0xc8ce, (q15_t)0x1f90, (q15_t)0xc8d4, (q15_t)0x1f85, (q15_t)0xc8db, (q15_t)0x1f7a, (q15_t)0xc8e1,
+    (q15_t)0x1f6f, (q15_t)0xc8e8, (q15_t)0x1f65, (q15_t)0xc8ee, (q15_t)0x1f5a, (q15_t)0xc8f4, (q15_t)0x1f4f, (q15_t)0xc8fb,
+    (q15_t)0x1f44, (q15_t)0xc901, (q15_t)0x1f39, (q15_t)0xc908, (q15_t)0x1f2f, (q15_t)0xc90e, (q15_t)0x1f24, (q15_t)0xc915,
+    (q15_t)0x1f19, (q15_t)0xc91b, (q15_t)0x1f0e, (q15_t)0xc921, (q15_t)0x1f03, (q15_t)0xc928, (q15_t)0x1ef9, (q15_t)0xc92e,
+    (q15_t)0x1eee, (q15_t)0xc935, (q15_t)0x1ee3, (q15_t)0xc93b, (q15_t)0x1ed8, (q15_t)0xc942, (q15_t)0x1ece, (q15_t)0xc948,
+    (q15_t)0x1ec3, (q15_t)0xc94f, (q15_t)0x1eb8, (q15_t)0xc955, (q15_t)0x1ead, (q15_t)0xc95c, (q15_t)0x1ea3, (q15_t)0xc963,
+    (q15_t)0x1e98, (q15_t)0xc969, (q15_t)0x1e8d, (q15_t)0xc970, (q15_t)0x1e83, (q15_t)0xc976, (q15_t)0x1e78, (q15_t)0xc97d,
+    (q15_t)0x1e6d, (q15_t)0xc983, (q15_t)0x1e62, (q15_t)0xc98a, (q15_t)0x1e58, (q15_t)0xc991, (q15_t)0x1e4d, (q15_t)0xc997,
+    (q15_t)0x1e42, (q15_t)0xc99e, (q15_t)0x1e38, (q15_t)0xc9a4, (q15_t)0x1e2d, (q15_t)0xc9ab, (q15_t)0x1e22, (q15_t)0xc9b2,
+    (q15_t)0x1e18, (q15_t)0xc9b8, (q15_t)0x1e0d, (q15_t)0xc9bf, (q15_t)0x1e02, (q15_t)0xc9c6, (q15_t)0x1df8, (q15_t)0xc9cc,
+    (q15_t)0x1ded, (q15_t)0xc9d3, (q15_t)0x1de2, (q15_t)0xc9da, (q15_t)0x1dd8, (q15_t)0xc9e0, (q15_t)0x1dcd, (q15_t)0xc9e7,
+    (q15_t)0x1dc3, (q15_t)0xc9ee, (q15_t)0x1db8, (q15_t)0xc9f5, (q15_t)0x1dad, (q15_t)0xc9fb, (q15_t)0x1da3, (q15_t)0xca02,
+    (q15_t)0x1d98, (q15_t)0xca09, (q15_t)0x1d8e, (q15_t)0xca10, (q15_t)0x1d83, (q15_t)0xca16, (q15_t)0x1d78, (q15_t)0xca1d,
+    (q15_t)0x1d6e, (q15_t)0xca24, (q15_t)0x1d63, (q15_t)0xca2b, (q15_t)0x1d59, (q15_t)0xca32, (q15_t)0x1d4e, (q15_t)0xca38,
+    (q15_t)0x1d44, (q15_t)0xca3f, (q15_t)0x1d39, (q15_t)0xca46, (q15_t)0x1d2e, (q15_t)0xca4d, (q15_t)0x1d24, (q15_t)0xca54,
+    (q15_t)0x1d19, (q15_t)0xca5b, (q15_t)0x1d0f, (q15_t)0xca61, (q15_t)0x1d04, (q15_t)0xca68, (q15_t)0x1cfa, (q15_t)0xca6f,
+    (q15_t)0x1cef, (q15_t)0xca76, (q15_t)0x1ce5, (q15_t)0xca7d, (q15_t)0x1cda, (q15_t)0xca84, (q15_t)0x1cd0, (q15_t)0xca8b,
+    (q15_t)0x1cc5, (q15_t)0xca92, (q15_t)0x1cbb, (q15_t)0xca99, (q15_t)0x1cb0, (q15_t)0xca9f, (q15_t)0x1ca6, (q15_t)0xcaa6,
+    (q15_t)0x1c9b, (q15_t)0xcaad, (q15_t)0x1c91, (q15_t)0xcab4, (q15_t)0x1c86, (q15_t)0xcabb, (q15_t)0x1c7c, (q15_t)0xcac2,
+    (q15_t)0x1c72, (q15_t)0xcac9, (q15_t)0x1c67, (q15_t)0xcad0, (q15_t)0x1c5d, (q15_t)0xcad7, (q15_t)0x1c52, (q15_t)0xcade,
+    (q15_t)0x1c48, (q15_t)0xcae5, (q15_t)0x1c3d, (q15_t)0xcaec, (q15_t)0x1c33, (q15_t)0xcaf3, (q15_t)0x1c29, (q15_t)0xcafa,
+    (q15_t)0x1c1e, (q15_t)0xcb01, (q15_t)0x1c14, (q15_t)0xcb08, (q15_t)0x1c09, (q15_t)0xcb0f, (q15_t)0x1bff, (q15_t)0xcb16,
+    (q15_t)0x1bf5, (q15_t)0xcb1e, (q15_t)0x1bea, (q15_t)0xcb25, (q15_t)0x1be0, (q15_t)0xcb2c, (q15_t)0x1bd5, (q15_t)0xcb33,
+    (q15_t)0x1bcb, (q15_t)0xcb3a, (q15_t)0x1bc1, (q15_t)0xcb41, (q15_t)0x1bb6, (q15_t)0xcb48, (q15_t)0x1bac, (q15_t)0xcb4f,
+    (q15_t)0x1ba2, (q15_t)0xcb56, (q15_t)0x1b97, (q15_t)0xcb5e, (q15_t)0x1b8d, (q15_t)0xcb65, (q15_t)0x1b83, (q15_t)0xcb6c,
+    (q15_t)0x1b78, (q15_t)0xcb73, (q15_t)0x1b6e, (q15_t)0xcb7a, (q15_t)0x1b64, (q15_t)0xcb81, (q15_t)0x1b59, (q15_t)0xcb89,
+    (q15_t)0x1b4f, (q15_t)0xcb90, (q15_t)0x1b45, (q15_t)0xcb97, (q15_t)0x1b3b, (q15_t)0xcb9e, (q15_t)0x1b30, (q15_t)0xcba5,
+    (q15_t)0x1b26, (q15_t)0xcbad, (q15_t)0x1b1c, (q15_t)0xcbb4, (q15_t)0x1b11, (q15_t)0xcbbb, (q15_t)0x1b07, (q15_t)0xcbc2,
+    (q15_t)0x1afd, (q15_t)0xcbca, (q15_t)0x1af3, (q15_t)0xcbd1, (q15_t)0x1ae8, (q15_t)0xcbd8, (q15_t)0x1ade, (q15_t)0xcbe0,
+    (q15_t)0x1ad4, (q15_t)0xcbe7, (q15_t)0x1aca, (q15_t)0xcbee, (q15_t)0x1abf, (q15_t)0xcbf5, (q15_t)0x1ab5, (q15_t)0xcbfd,
+    (q15_t)0x1aab, (q15_t)0xcc04, (q15_t)0x1aa1, (q15_t)0xcc0b, (q15_t)0x1a97, (q15_t)0xcc13, (q15_t)0x1a8c, (q15_t)0xcc1a,
+    (q15_t)0x1a82, (q15_t)0xcc21, (q15_t)0x1a78, (q15_t)0xcc29, (q15_t)0x1a6e, (q15_t)0xcc30, (q15_t)0x1a64, (q15_t)0xcc38,
+    (q15_t)0x1a5a, (q15_t)0xcc3f, (q15_t)0x1a4f, (q15_t)0xcc46, (q15_t)0x1a45, (q15_t)0xcc4e, (q15_t)0x1a3b, (q15_t)0xcc55,
+    (q15_t)0x1a31, (q15_t)0xcc5d, (q15_t)0x1a27, (q15_t)0xcc64, (q15_t)0x1a1d, (q15_t)0xcc6b, (q15_t)0x1a13, (q15_t)0xcc73,
+    (q15_t)0x1a08, (q15_t)0xcc7a, (q15_t)0x19fe, (q15_t)0xcc82, (q15_t)0x19f4, (q15_t)0xcc89, (q15_t)0x19ea, (q15_t)0xcc91,
+    (q15_t)0x19e0, (q15_t)0xcc98, (q15_t)0x19d6, (q15_t)0xcca0, (q15_t)0x19cc, (q15_t)0xcca7, (q15_t)0x19c2, (q15_t)0xccaf,
+    (q15_t)0x19b8, (q15_t)0xccb6, (q15_t)0x19ae, (q15_t)0xccbe, (q15_t)0x19a4, (q15_t)0xccc5, (q15_t)0x199a, (q15_t)0xcccd,
+    (q15_t)0x198f, (q15_t)0xccd4, (q15_t)0x1985, (q15_t)0xccdc, (q15_t)0x197b, (q15_t)0xcce3, (q15_t)0x1971, (q15_t)0xcceb,
+    (q15_t)0x1967, (q15_t)0xccf3, (q15_t)0x195d, (q15_t)0xccfa, (q15_t)0x1953, (q15_t)0xcd02, (q15_t)0x1949, (q15_t)0xcd09,
+    (q15_t)0x193f, (q15_t)0xcd11, (q15_t)0x1935, (q15_t)0xcd19, (q15_t)0x192b, (q15_t)0xcd20, (q15_t)0x1921, (q15_t)0xcd28,
+    (q15_t)0x1917, (q15_t)0xcd30, (q15_t)0x190d, (q15_t)0xcd37, (q15_t)0x1903, (q15_t)0xcd3f, (q15_t)0x18f9, (q15_t)0xcd46,
+    (q15_t)0x18ef, (q15_t)0xcd4e, (q15_t)0x18e6, (q15_t)0xcd56, (q15_t)0x18dc, (q15_t)0xcd5d, (q15_t)0x18d2, (q15_t)0xcd65,
+    (q15_t)0x18c8, (q15_t)0xcd6d, (q15_t)0x18be, (q15_t)0xcd75, (q15_t)0x18b4, (q15_t)0xcd7c, (q15_t)0x18aa, (q15_t)0xcd84,
+    (q15_t)0x18a0, (q15_t)0xcd8c, (q15_t)0x1896, (q15_t)0xcd93, (q15_t)0x188c, (q15_t)0xcd9b, (q15_t)0x1882, (q15_t)0xcda3,
+    (q15_t)0x1878, (q15_t)0xcdab, (q15_t)0x186f, (q15_t)0xcdb2, (q15_t)0x1865, (q15_t)0xcdba, (q15_t)0x185b, (q15_t)0xcdc2,
+    (q15_t)0x1851, (q15_t)0xcdca, (q15_t)0x1847, (q15_t)0xcdd2, (q15_t)0x183d, (q15_t)0xcdd9, (q15_t)0x1833, (q15_t)0xcde1,
+    (q15_t)0x182a, (q15_t)0xcde9, (q15_t)0x1820, (q15_t)0xcdf1, (q15_t)0x1816, (q15_t)0xcdf9, (q15_t)0x180c, (q15_t)0xce01,
+    (q15_t)0x1802, (q15_t)0xce08, (q15_t)0x17f8, (q15_t)0xce10, (q15_t)0x17ef, (q15_t)0xce18, (q15_t)0x17e5, (q15_t)0xce20,
+    (q15_t)0x17db, (q15_t)0xce28, (q15_t)0x17d1, (q15_t)0xce30, (q15_t)0x17c8, (q15_t)0xce38, (q15_t)0x17be, (q15_t)0xce40,
+    (q15_t)0x17b4, (q15_t)0xce47, (q15_t)0x17aa, (q15_t)0xce4f, (q15_t)0x17a0, (q15_t)0xce57, (q15_t)0x1797, (q15_t)0xce5f,
+    (q15_t)0x178d, (q15_t)0xce67, (q15_t)0x1783, (q15_t)0xce6f, (q15_t)0x177a, (q15_t)0xce77, (q15_t)0x1770, (q15_t)0xce7f,
+    (q15_t)0x1766, (q15_t)0xce87, (q15_t)0x175c, (q15_t)0xce8f, (q15_t)0x1753, (q15_t)0xce97, (q15_t)0x1749, (q15_t)0xce9f,
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+    (q15_t)0xbca, (q15_t)0xdafd, (q15_t)0xbc2, (q15_t)0xdb07, (q15_t)0xbbb, (q15_t)0xdb11, (q15_t)0xbb4, (q15_t)0xdb1c,
+    (q15_t)0xbad, (q15_t)0xdb26, (q15_t)0xba5, (q15_t)0xdb30, (q15_t)0xb9e, (q15_t)0xdb3b, (q15_t)0xb97, (q15_t)0xdb45,
+    (q15_t)0xb90, (q15_t)0xdb4f, (q15_t)0xb89, (q15_t)0xdb59, (q15_t)0xb81, (q15_t)0xdb64, (q15_t)0xb7a, (q15_t)0xdb6e,
+    (q15_t)0xb73, (q15_t)0xdb78, (q15_t)0xb6c, (q15_t)0xdb83, (q15_t)0xb65, (q15_t)0xdb8d, (q15_t)0xb5e, (q15_t)0xdb97,
+    (q15_t)0xb56, (q15_t)0xdba2, (q15_t)0xb4f, (q15_t)0xdbac, (q15_t)0xb48, (q15_t)0xdbb6, (q15_t)0xb41, (q15_t)0xdbc1,
+    (q15_t)0xb3a, (q15_t)0xdbcb, (q15_t)0xb33, (q15_t)0xdbd5, (q15_t)0xb2c, (q15_t)0xdbe0, (q15_t)0xb25, (q15_t)0xdbea,
+    (q15_t)0xb1e, (q15_t)0xdbf5, (q15_t)0xb16, (q15_t)0xdbff, (q15_t)0xb0f, (q15_t)0xdc09, (q15_t)0xb08, (q15_t)0xdc14,
+    (q15_t)0xb01, (q15_t)0xdc1e, (q15_t)0xafa, (q15_t)0xdc29, (q15_t)0xaf3, (q15_t)0xdc33, (q15_t)0xaec, (q15_t)0xdc3d,
+    (q15_t)0xae5, (q15_t)0xdc48, (q15_t)0xade, (q15_t)0xdc52, (q15_t)0xad7, (q15_t)0xdc5d, (q15_t)0xad0, (q15_t)0xdc67,
+    (q15_t)0xac9, (q15_t)0xdc72, (q15_t)0xac2, (q15_t)0xdc7c, (q15_t)0xabb, (q15_t)0xdc86, (q15_t)0xab4, (q15_t)0xdc91,
+    (q15_t)0xaad, (q15_t)0xdc9b, (q15_t)0xaa6, (q15_t)0xdca6, (q15_t)0xa9f, (q15_t)0xdcb0, (q15_t)0xa99, (q15_t)0xdcbb,
+    (q15_t)0xa92, (q15_t)0xdcc5, (q15_t)0xa8b, (q15_t)0xdcd0, (q15_t)0xa84, (q15_t)0xdcda, (q15_t)0xa7d, (q15_t)0xdce5,
+    (q15_t)0xa76, (q15_t)0xdcef, (q15_t)0xa6f, (q15_t)0xdcfa, (q15_t)0xa68, (q15_t)0xdd04, (q15_t)0xa61, (q15_t)0xdd0f,
+    (q15_t)0xa5b, (q15_t)0xdd19, (q15_t)0xa54, (q15_t)0xdd24, (q15_t)0xa4d, (q15_t)0xdd2e, (q15_t)0xa46, (q15_t)0xdd39,
+    (q15_t)0xa3f, (q15_t)0xdd44, (q15_t)0xa38, (q15_t)0xdd4e, (q15_t)0xa32, (q15_t)0xdd59, (q15_t)0xa2b, (q15_t)0xdd63,
+    (q15_t)0xa24, (q15_t)0xdd6e, (q15_t)0xa1d, (q15_t)0xdd78, (q15_t)0xa16, (q15_t)0xdd83, (q15_t)0xa10, (q15_t)0xdd8e,
+    (q15_t)0xa09, (q15_t)0xdd98, (q15_t)0xa02, (q15_t)0xdda3, (q15_t)0x9fb, (q15_t)0xddad, (q15_t)0x9f5, (q15_t)0xddb8,
+    (q15_t)0x9ee, (q15_t)0xddc3, (q15_t)0x9e7, (q15_t)0xddcd, (q15_t)0x9e0, (q15_t)0xddd8, (q15_t)0x9da, (q15_t)0xdde2,
+    (q15_t)0x9d3, (q15_t)0xdded, (q15_t)0x9cc, (q15_t)0xddf8, (q15_t)0x9c6, (q15_t)0xde02, (q15_t)0x9bf, (q15_t)0xde0d,
+    (q15_t)0x9b8, (q15_t)0xde18, (q15_t)0x9b2, (q15_t)0xde22, (q15_t)0x9ab, (q15_t)0xde2d, (q15_t)0x9a4, (q15_t)0xde38,
+    (q15_t)0x99e, (q15_t)0xde42, (q15_t)0x997, (q15_t)0xde4d, (q15_t)0x991, (q15_t)0xde58, (q15_t)0x98a, (q15_t)0xde62,
+    (q15_t)0x983, (q15_t)0xde6d, (q15_t)0x97d, (q15_t)0xde78, (q15_t)0x976, (q15_t)0xde83, (q15_t)0x970, (q15_t)0xde8d,
+    (q15_t)0x969, (q15_t)0xde98, (q15_t)0x963, (q15_t)0xdea3, (q15_t)0x95c, (q15_t)0xdead, (q15_t)0x955, (q15_t)0xdeb8,
+    (q15_t)0x94f, (q15_t)0xdec3, (q15_t)0x948, (q15_t)0xdece, (q15_t)0x942, (q15_t)0xded8, (q15_t)0x93b, (q15_t)0xdee3,
+    (q15_t)0x935, (q15_t)0xdeee, (q15_t)0x92e, (q15_t)0xdef9, (q15_t)0x928, (q15_t)0xdf03, (q15_t)0x921, (q15_t)0xdf0e,
+    (q15_t)0x91b, (q15_t)0xdf19, (q15_t)0x915, (q15_t)0xdf24, (q15_t)0x90e, (q15_t)0xdf2f, (q15_t)0x908, (q15_t)0xdf39,
+    (q15_t)0x901, (q15_t)0xdf44, (q15_t)0x8fb, (q15_t)0xdf4f, (q15_t)0x8f4, (q15_t)0xdf5a, (q15_t)0x8ee, (q15_t)0xdf65,
+    (q15_t)0x8e8, (q15_t)0xdf6f, (q15_t)0x8e1, (q15_t)0xdf7a, (q15_t)0x8db, (q15_t)0xdf85, (q15_t)0x8d4, (q15_t)0xdf90,
+    (q15_t)0x8ce, (q15_t)0xdf9b, (q15_t)0x8c8, (q15_t)0xdfa5, (q15_t)0x8c1, (q15_t)0xdfb0, (q15_t)0x8bb, (q15_t)0xdfbb,
+    (q15_t)0x8b5, (q15_t)0xdfc6, (q15_t)0x8ae, (q15_t)0xdfd1, (q15_t)0x8a8, (q15_t)0xdfdc, (q15_t)0x8a2, (q15_t)0xdfe7,
+    (q15_t)0x89b, (q15_t)0xdff1, (q15_t)0x895, (q15_t)0xdffc, (q15_t)0x88f, (q15_t)0xe007, (q15_t)0x889, (q15_t)0xe012,
+    (q15_t)0x882, (q15_t)0xe01d, (q15_t)0x87c, (q15_t)0xe028, (q15_t)0x876, (q15_t)0xe033, (q15_t)0x870, (q15_t)0xe03e,
+    (q15_t)0x869, (q15_t)0xe049, (q15_t)0x863, (q15_t)0xe054, (q15_t)0x85d, (q15_t)0xe05e, (q15_t)0x857, (q15_t)0xe069,
+    (q15_t)0x850, (q15_t)0xe074, (q15_t)0x84a, (q15_t)0xe07f, (q15_t)0x844, (q15_t)0xe08a, (q15_t)0x83e, (q15_t)0xe095,
+    (q15_t)0x838, (q15_t)0xe0a0, (q15_t)0x832, (q15_t)0xe0ab, (q15_t)0x82b, (q15_t)0xe0b6, (q15_t)0x825, (q15_t)0xe0c1,
+    (q15_t)0x81f, (q15_t)0xe0cc, (q15_t)0x819, (q15_t)0xe0d7, (q15_t)0x813, (q15_t)0xe0e2, (q15_t)0x80d, (q15_t)0xe0ed,
+    (q15_t)0x807, (q15_t)0xe0f8, (q15_t)0x801, (q15_t)0xe103, (q15_t)0x7fb, (q15_t)0xe10e, (q15_t)0x7f5, (q15_t)0xe119,
+    (q15_t)0x7ee, (q15_t)0xe124, (q15_t)0x7e8, (q15_t)0xe12f, (q15_t)0x7e2, (q15_t)0xe13a, (q15_t)0x7dc, (q15_t)0xe145,
+    (q15_t)0x7d6, (q15_t)0xe150, (q15_t)0x7d0, (q15_t)0xe15b, (q15_t)0x7ca, (q15_t)0xe166, (q15_t)0x7c4, (q15_t)0xe171,
+    (q15_t)0x7be, (q15_t)0xe17c, (q15_t)0x7b8, (q15_t)0xe187, (q15_t)0x7b2, (q15_t)0xe192, (q15_t)0x7ac, (q15_t)0xe19d,
+    (q15_t)0x7a6, (q15_t)0xe1a8, (q15_t)0x7a0, (q15_t)0xe1b3, (q15_t)0x79a, (q15_t)0xe1be, (q15_t)0x795, (q15_t)0xe1ca,
+    (q15_t)0x78f, (q15_t)0xe1d5, (q15_t)0x789, (q15_t)0xe1e0, (q15_t)0x783, (q15_t)0xe1eb, (q15_t)0x77d, (q15_t)0xe1f6,
+    (q15_t)0x777, (q15_t)0xe201, (q15_t)0x771, (q15_t)0xe20c, (q15_t)0x76b, (q15_t)0xe217, (q15_t)0x765, (q15_t)0xe222,
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+    (q15_t)0x748, (q15_t)0xe25a, (q15_t)0x742, (q15_t)0xe265, (q15_t)0x73d, (q15_t)0xe270, (q15_t)0x737, (q15_t)0xe27b,
+    (q15_t)0x731, (q15_t)0xe287, (q15_t)0x72b, (q15_t)0xe292, (q15_t)0x725, (q15_t)0xe29d, (q15_t)0x720, (q15_t)0xe2a8,
+    (q15_t)0x71a, (q15_t)0xe2b3, (q15_t)0x714, (q15_t)0xe2be, (q15_t)0x70e, (q15_t)0xe2ca, (q15_t)0x709, (q15_t)0xe2d5,
+    (q15_t)0x703, (q15_t)0xe2e0, (q15_t)0x6fd, (q15_t)0xe2eb, (q15_t)0x6f7, (q15_t)0xe2f6, (q15_t)0x6f2, (q15_t)0xe301,
+    (q15_t)0x6ec, (q15_t)0xe30d, (q15_t)0x6e6, (q15_t)0xe318, (q15_t)0x6e1, (q15_t)0xe323, (q15_t)0x6db, (q15_t)0xe32e,
+    (q15_t)0x6d5, (q15_t)0xe33a, (q15_t)0x6d0, (q15_t)0xe345, (q15_t)0x6ca, (q15_t)0xe350, (q15_t)0x6c5, (q15_t)0xe35b,
+    (q15_t)0x6bf, (q15_t)0xe367, (q15_t)0x6b9, (q15_t)0xe372, (q15_t)0x6b4, (q15_t)0xe37d, (q15_t)0x6ae, (q15_t)0xe388,
+    (q15_t)0x6a8, (q15_t)0xe394, (q15_t)0x6a3, (q15_t)0xe39f, (q15_t)0x69d, (q15_t)0xe3aa, (q15_t)0x698, (q15_t)0xe3b5,
+    (q15_t)0x692, (q15_t)0xe3c1, (q15_t)0x68d, (q15_t)0xe3cc, (q15_t)0x687, (q15_t)0xe3d7, (q15_t)0x682, (q15_t)0xe3e2,
+    (q15_t)0x67c, (q15_t)0xe3ee, (q15_t)0x677, (q15_t)0xe3f9, (q15_t)0x671, (q15_t)0xe404, (q15_t)0x66c, (q15_t)0xe410,
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+    (q15_t)0x650, (q15_t)0xe448, (q15_t)0x64b, (q15_t)0xe454, (q15_t)0x645, (q15_t)0xe45f, (q15_t)0x640, (q15_t)0xe46a,
+    (q15_t)0x63b, (q15_t)0xe476, (q15_t)0x635, (q15_t)0xe481, (q15_t)0x630, (q15_t)0xe48c, (q15_t)0x62a, (q15_t)0xe498,
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+    (q15_t)0x610, (q15_t)0xe4d0, (q15_t)0x60a, (q15_t)0xe4dc, (q15_t)0x605, (q15_t)0xe4e7, (q15_t)0x600, (q15_t)0xe4f3,
+    (q15_t)0x5fa, (q15_t)0xe4fe, (q15_t)0x5f5, (q15_t)0xe509, (q15_t)0x5f0, (q15_t)0xe515, (q15_t)0x5ea, (q15_t)0xe520,
+    (q15_t)0x5e5, (q15_t)0xe52c, (q15_t)0x5e0, (q15_t)0xe537, (q15_t)0x5db, (q15_t)0xe542, (q15_t)0x5d5, (q15_t)0xe54e,
+    (q15_t)0x5d0, (q15_t)0xe559, (q15_t)0x5cb, (q15_t)0xe565, (q15_t)0x5c6, (q15_t)0xe570, (q15_t)0x5c1, (q15_t)0xe57c,
+    (q15_t)0x5bb, (q15_t)0xe587, (q15_t)0x5b6, (q15_t)0xe592, (q15_t)0x5b1, (q15_t)0xe59e, (q15_t)0x5ac, (q15_t)0xe5a9,
+    (q15_t)0x5a7, (q15_t)0xe5b5, (q15_t)0x5a1, (q15_t)0xe5c0, (q15_t)0x59c, (q15_t)0xe5cc, (q15_t)0x597, (q15_t)0xe5d7,
+    (q15_t)0x592, (q15_t)0xe5e3, (q15_t)0x58d, (q15_t)0xe5ee, (q15_t)0x588, (q15_t)0xe5fa, (q15_t)0x583, (q15_t)0xe605,
+    (q15_t)0x57e, (q15_t)0xe611, (q15_t)0x578, (q15_t)0xe61c, (q15_t)0x573, (q15_t)0xe628, (q15_t)0x56e, (q15_t)0xe633,
+    (q15_t)0x569, (q15_t)0xe63f, (q15_t)0x564, (q15_t)0xe64a, (q15_t)0x55f, (q15_t)0xe656, (q15_t)0x55a, (q15_t)0xe661,
+    (q15_t)0x555, (q15_t)0xe66d, (q15_t)0x550, (q15_t)0xe678, (q15_t)0x54b, (q15_t)0xe684, (q15_t)0x546, (q15_t)0xe68f,
+    (q15_t)0x541, (q15_t)0xe69b, (q15_t)0x53c, (q15_t)0xe6a6, (q15_t)0x537, (q15_t)0xe6b2, (q15_t)0x532, (q15_t)0xe6bd,
+    (q15_t)0x52d, (q15_t)0xe6c9, (q15_t)0x528, (q15_t)0xe6d4, (q15_t)0x523, (q15_t)0xe6e0, (q15_t)0x51e, (q15_t)0xe6ec,
+    (q15_t)0x51a, (q15_t)0xe6f7, (q15_t)0x515, (q15_t)0xe703, (q15_t)0x510, (q15_t)0xe70e, (q15_t)0x50b, (q15_t)0xe71a,
+    (q15_t)0x506, (q15_t)0xe725, (q15_t)0x501, (q15_t)0xe731, (q15_t)0x4fc, (q15_t)0xe73d, (q15_t)0x4f7, (q15_t)0xe748,
+    (q15_t)0x4f2, (q15_t)0xe754, (q15_t)0x4ee, (q15_t)0xe75f, (q15_t)0x4e9, (q15_t)0xe76b, (q15_t)0x4e4, (q15_t)0xe777,
+    (q15_t)0x4df, (q15_t)0xe782, (q15_t)0x4da, (q15_t)0xe78e, (q15_t)0x4d6, (q15_t)0xe799, (q15_t)0x4d1, (q15_t)0xe7a5,
+    (q15_t)0x4cc, (q15_t)0xe7b1, (q15_t)0x4c7, (q15_t)0xe7bc, (q15_t)0x4c2, (q15_t)0xe7c8, (q15_t)0x4be, (q15_t)0xe7d3,
+    (q15_t)0x4b9, (q15_t)0xe7df, (q15_t)0x4b4, (q15_t)0xe7eb, (q15_t)0x4b0, (q15_t)0xe7f6, (q15_t)0x4ab, (q15_t)0xe802,
+    (q15_t)0x4a6, (q15_t)0xe80e, (q15_t)0x4a1, (q15_t)0xe819, (q15_t)0x49d, (q15_t)0xe825, (q15_t)0x498, (q15_t)0xe831,
+    (q15_t)0x493, (q15_t)0xe83c, (q15_t)0x48f, (q15_t)0xe848, (q15_t)0x48a, (q15_t)0xe854, (q15_t)0x485, (q15_t)0xe85f,
+    (q15_t)0x481, (q15_t)0xe86b, (q15_t)0x47c, (q15_t)0xe877, (q15_t)0x478, (q15_t)0xe882, (q15_t)0x473, (q15_t)0xe88e,
+    (q15_t)0x46e, (q15_t)0xe89a, (q15_t)0x46a, (q15_t)0xe8a5, (q15_t)0x465, (q15_t)0xe8b1, (q15_t)0x461, (q15_t)0xe8bd,
+    (q15_t)0x45c, (q15_t)0xe8c9, (q15_t)0x457, (q15_t)0xe8d4, (q15_t)0x453, (q15_t)0xe8e0, (q15_t)0x44e, (q15_t)0xe8ec,
+    (q15_t)0x44a, (q15_t)0xe8f7, (q15_t)0x445, (q15_t)0xe903, (q15_t)0x441, (q15_t)0xe90f, (q15_t)0x43c, (q15_t)0xe91b,
+    (q15_t)0x438, (q15_t)0xe926, (q15_t)0x433, (q15_t)0xe932, (q15_t)0x42f, (q15_t)0xe93e, (q15_t)0x42a, (q15_t)0xe94a,
+    (q15_t)0x426, (q15_t)0xe955, (q15_t)0x422, (q15_t)0xe961, (q15_t)0x41d, (q15_t)0xe96d, (q15_t)0x419, (q15_t)0xe979,
+    (q15_t)0x414, (q15_t)0xe984, (q15_t)0x410, (q15_t)0xe990, (q15_t)0x40b, (q15_t)0xe99c, (q15_t)0x407, (q15_t)0xe9a8,
+    (q15_t)0x403, (q15_t)0xe9b4, (q15_t)0x3fe, (q15_t)0xe9bf, (q15_t)0x3fa, (q15_t)0xe9cb, (q15_t)0x3f6, (q15_t)0xe9d7,
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+    (q15_t)0x38, (q15_t)0xfab4, (q15_t)0x37, (q15_t)0xfac1, (q15_t)0x36, (q15_t)0xfacd, (q15_t)0x35, (q15_t)0xfada,
+    (q15_t)0x34, (q15_t)0xfae6, (q15_t)0x33, (q15_t)0xfaf3, (q15_t)0x32, (q15_t)0xfb00, (q15_t)0x31, (q15_t)0xfb0c,
+    (q15_t)0x30, (q15_t)0xfb19, (q15_t)0x2f, (q15_t)0xfb25, (q15_t)0x2e, (q15_t)0xfb32, (q15_t)0x2d, (q15_t)0xfb3e,
+    (q15_t)0x2c, (q15_t)0xfb4b, (q15_t)0x2b, (q15_t)0xfb57, (q15_t)0x2b, (q15_t)0xfb64, (q15_t)0x2a, (q15_t)0xfb70,
+    (q15_t)0x29, (q15_t)0xfb7d, (q15_t)0x28, (q15_t)0xfb89, (q15_t)0x27, (q15_t)0xfb96, (q15_t)0x26, (q15_t)0xfba2,
+    (q15_t)0x25, (q15_t)0xfbaf, (q15_t)0x24, (q15_t)0xfbbc, (q15_t)0x24, (q15_t)0xfbc8, (q15_t)0x23, (q15_t)0xfbd5,
+    (q15_t)0x22, (q15_t)0xfbe1, (q15_t)0x21, (q15_t)0xfbee, (q15_t)0x20, (q15_t)0xfbfa, (q15_t)0x20, (q15_t)0xfc07,
+    (q15_t)0x1f, (q15_t)0xfc13, (q15_t)0x1e, (q15_t)0xfc20, (q15_t)0x1d, (q15_t)0xfc2c, (q15_t)0x1d, (q15_t)0xfc39,
+    (q15_t)0x1c, (q15_t)0xfc45, (q15_t)0x1b, (q15_t)0xfc52, (q15_t)0x1a, (q15_t)0xfc5f, (q15_t)0x1a, (q15_t)0xfc6b,
+    (q15_t)0x19, (q15_t)0xfc78, (q15_t)0x18, (q15_t)0xfc84, (q15_t)0x18, (q15_t)0xfc91, (q15_t)0x17, (q15_t)0xfc9d,
+    (q15_t)0x16, (q15_t)0xfcaa, (q15_t)0x16, (q15_t)0xfcb6, (q15_t)0x15, (q15_t)0xfcc3, (q15_t)0x14, (q15_t)0xfcd0,
+    (q15_t)0x14, (q15_t)0xfcdc, (q15_t)0x13, (q15_t)0xfce9, (q15_t)0x13, (q15_t)0xfcf5, (q15_t)0x12, (q15_t)0xfd02,
+    (q15_t)0x11, (q15_t)0xfd0e, (q15_t)0x11, (q15_t)0xfd1b, (q15_t)0x10, (q15_t)0xfd27, (q15_t)0x10, (q15_t)0xfd34,
+    (q15_t)0xf, (q15_t)0xfd40, (q15_t)0xf, (q15_t)0xfd4d, (q15_t)0xe, (q15_t)0xfd5a, (q15_t)0xe, (q15_t)0xfd66,
+    (q15_t)0xd, (q15_t)0xfd73, (q15_t)0xd, (q15_t)0xfd7f, (q15_t)0xc, (q15_t)0xfd8c, (q15_t)0xc, (q15_t)0xfd98,
+    (q15_t)0xb, (q15_t)0xfda5, (q15_t)0xb, (q15_t)0xfdb2, (q15_t)0xa, (q15_t)0xfdbe, (q15_t)0xa, (q15_t)0xfdcb,
+    (q15_t)0x9, (q15_t)0xfdd7, (q15_t)0x9, (q15_t)0xfde4, (q15_t)0x9, (q15_t)0xfdf0, (q15_t)0x8, (q15_t)0xfdfd,
+    (q15_t)0x8, (q15_t)0xfe09, (q15_t)0x7, (q15_t)0xfe16, (q15_t)0x7, (q15_t)0xfe23, (q15_t)0x7, (q15_t)0xfe2f,
+    (q15_t)0x6, (q15_t)0xfe3c, (q15_t)0x6, (q15_t)0xfe48, (q15_t)0x6, (q15_t)0xfe55, (q15_t)0x5, (q15_t)0xfe61,
+    (q15_t)0x5, (q15_t)0xfe6e, (q15_t)0x5, (q15_t)0xfe7a, (q15_t)0x4, (q15_t)0xfe87, (q15_t)0x4, (q15_t)0xfe94,
+    (q15_t)0x4, (q15_t)0xfea0, (q15_t)0x4, (q15_t)0xfead, (q15_t)0x3, (q15_t)0xfeb9, (q15_t)0x3, (q15_t)0xfec6,
+    (q15_t)0x3, (q15_t)0xfed2, (q15_t)0x3, (q15_t)0xfedf, (q15_t)0x2, (q15_t)0xfeec, (q15_t)0x2, (q15_t)0xfef8,
+    (q15_t)0x2, (q15_t)0xff05, (q15_t)0x2, (q15_t)0xff11, (q15_t)0x2, (q15_t)0xff1e, (q15_t)0x1, (q15_t)0xff2a,
+    (q15_t)0x1, (q15_t)0xff37, (q15_t)0x1, (q15_t)0xff44, (q15_t)0x1, (q15_t)0xff50, (q15_t)0x1, (q15_t)0xff5d,
+    (q15_t)0x1, (q15_t)0xff69, (q15_t)0x1, (q15_t)0xff76, (q15_t)0x0, (q15_t)0xff82, (q15_t)0x0, (q15_t)0xff8f,
+    (q15_t)0x0, (q15_t)0xff9b, (q15_t)0x0, (q15_t)0xffa8, (q15_t)0x0, (q15_t)0xffb5, (q15_t)0x0, (q15_t)0xffc1,
+    (q15_t)0x0, (q15_t)0xffce, (q15_t)0x0, (q15_t)0xffda, (q15_t)0x0, (q15_t)0xffe7, (q15_t)0x0, (q15_t)0xfff3,
+    (q15_t)0x0, (q15_t)0x0, (q15_t)0x0, (q15_t)0xd, (q15_t)0x0, (q15_t)0x19, (q15_t)0x0, (q15_t)0x26,
+    (q15_t)0x0, (q15_t)0x32, (q15_t)0x0, (q15_t)0x3f, (q15_t)0x0, (q15_t)0x4b, (q15_t)0x0, (q15_t)0x58,
+    (q15_t)0x0, (q15_t)0x65, (q15_t)0x0, (q15_t)0x71, (q15_t)0x0, (q15_t)0x7e, (q15_t)0x1, (q15_t)0x8a,
+    (q15_t)0x1, (q15_t)0x97, (q15_t)0x1, (q15_t)0xa3, (q15_t)0x1, (q15_t)0xb0, (q15_t)0x1, (q15_t)0xbc,
+    (q15_t)0x1, (q15_t)0xc9, (q15_t)0x1, (q15_t)0xd6, (q15_t)0x2, (q15_t)0xe2, (q15_t)0x2, (q15_t)0xef,
+    (q15_t)0x2, (q15_t)0xfb, (q15_t)0x2, (q15_t)0x108, (q15_t)0x2, (q15_t)0x114, (q15_t)0x3, (q15_t)0x121,
+    (q15_t)0x3, (q15_t)0x12e, (q15_t)0x3, (q15_t)0x13a, (q15_t)0x3, (q15_t)0x147, (q15_t)0x4, (q15_t)0x153,
+    (q15_t)0x4, (q15_t)0x160, (q15_t)0x4, (q15_t)0x16c, (q15_t)0x4, (q15_t)0x179, (q15_t)0x5, (q15_t)0x186,
+    (q15_t)0x5, (q15_t)0x192, (q15_t)0x5, (q15_t)0x19f, (q15_t)0x6, (q15_t)0x1ab, (q15_t)0x6, (q15_t)0x1b8,
+    (q15_t)0x6, (q15_t)0x1c4, (q15_t)0x7, (q15_t)0x1d1, (q15_t)0x7, (q15_t)0x1dd, (q15_t)0x7, (q15_t)0x1ea,
+    (q15_t)0x8, (q15_t)0x1f7, (q15_t)0x8, (q15_t)0x203, (q15_t)0x9, (q15_t)0x210, (q15_t)0x9, (q15_t)0x21c,
+    (q15_t)0x9, (q15_t)0x229, (q15_t)0xa, (q15_t)0x235, (q15_t)0xa, (q15_t)0x242, (q15_t)0xb, (q15_t)0x24e,
+    (q15_t)0xb, (q15_t)0x25b, (q15_t)0xc, (q15_t)0x268, (q15_t)0xc, (q15_t)0x274, (q15_t)0xd, (q15_t)0x281,
+    (q15_t)0xd, (q15_t)0x28d, (q15_t)0xe, (q15_t)0x29a, (q15_t)0xe, (q15_t)0x2a6, (q15_t)0xf, (q15_t)0x2b3,
+    (q15_t)0xf, (q15_t)0x2c0, (q15_t)0x10, (q15_t)0x2cc, (q15_t)0x10, (q15_t)0x2d9, (q15_t)0x11, (q15_t)0x2e5,
+    (q15_t)0x11, (q15_t)0x2f2, (q15_t)0x12, (q15_t)0x2fe, (q15_t)0x13, (q15_t)0x30b, (q15_t)0x13, (q15_t)0x317,
+    (q15_t)0x14, (q15_t)0x324, (q15_t)0x14, (q15_t)0x330, (q15_t)0x15, (q15_t)0x33d, (q15_t)0x16, (q15_t)0x34a,
+    (q15_t)0x16, (q15_t)0x356, (q15_t)0x17, (q15_t)0x363, (q15_t)0x18, (q15_t)0x36f, (q15_t)0x18, (q15_t)0x37c,
+    (q15_t)0x19, (q15_t)0x388, (q15_t)0x1a, (q15_t)0x395, (q15_t)0x1a, (q15_t)0x3a1, (q15_t)0x1b, (q15_t)0x3ae,
+    (q15_t)0x1c, (q15_t)0x3bb, (q15_t)0x1d, (q15_t)0x3c7, (q15_t)0x1d, (q15_t)0x3d4, (q15_t)0x1e, (q15_t)0x3e0,
+    (q15_t)0x1f, (q15_t)0x3ed, (q15_t)0x20, (q15_t)0x3f9, (q15_t)0x20, (q15_t)0x406, (q15_t)0x21, (q15_t)0x412,
+    (q15_t)0x22, (q15_t)0x41f, (q15_t)0x23, (q15_t)0x42b, (q15_t)0x24, (q15_t)0x438, (q15_t)0x24, (q15_t)0x444,
+    (q15_t)0x25, (q15_t)0x451, (q15_t)0x26, (q15_t)0x45e, (q15_t)0x27, (q15_t)0x46a, (q15_t)0x28, (q15_t)0x477,
+    (q15_t)0x29, (q15_t)0x483, (q15_t)0x2a, (q15_t)0x490, (q15_t)0x2b, (q15_t)0x49c, (q15_t)0x2b, (q15_t)0x4a9,
+    (q15_t)0x2c, (q15_t)0x4b5, (q15_t)0x2d, (q15_t)0x4c2, (q15_t)0x2e, (q15_t)0x4ce, (q15_t)0x2f, (q15_t)0x4db,
+    (q15_t)0x30, (q15_t)0x4e7, (q15_t)0x31, (q15_t)0x4f4, (q15_t)0x32, (q15_t)0x500, (q15_t)0x33, (q15_t)0x50d,
+    (q15_t)0x34, (q15_t)0x51a, (q15_t)0x35, (q15_t)0x526, (q15_t)0x36, (q15_t)0x533, (q15_t)0x37, (q15_t)0x53f,
+    (q15_t)0x38, (q15_t)0x54c, (q15_t)0x39, (q15_t)0x558, (q15_t)0x3a, (q15_t)0x565, (q15_t)0x3b, (q15_t)0x571,
+    (q15_t)0x3c, (q15_t)0x57e, (q15_t)0x3d, (q15_t)0x58a, (q15_t)0x3f, (q15_t)0x597, (q15_t)0x40, (q15_t)0x5a3,
+    (q15_t)0x41, (q15_t)0x5b0, (q15_t)0x42, (q15_t)0x5bc, (q15_t)0x43, (q15_t)0x5c9, (q15_t)0x44, (q15_t)0x5d5,
+    (q15_t)0x45, (q15_t)0x5e2, (q15_t)0x47, (q15_t)0x5ee, (q15_t)0x48, (q15_t)0x5fb, (q15_t)0x49, (q15_t)0x607,
+    (q15_t)0x4a, (q15_t)0x614, (q15_t)0x4b, (q15_t)0x620, (q15_t)0x4c, (q15_t)0x62d, (q15_t)0x4e, (q15_t)0x639,
+    (q15_t)0x4f, (q15_t)0x646, (q15_t)0x50, (q15_t)0x652, (q15_t)0x51, (q15_t)0x65f, (q15_t)0x53, (q15_t)0x66b,
+    (q15_t)0x54, (q15_t)0x678, (q15_t)0x55, (q15_t)0x684, (q15_t)0x56, (q15_t)0x691, (q15_t)0x58, (q15_t)0x69d,
+    (q15_t)0x59, (q15_t)0x6aa, (q15_t)0x5a, (q15_t)0x6b6, (q15_t)0x5c, (q15_t)0x6c3, (q15_t)0x5d, (q15_t)0x6cf,
+    (q15_t)0x5e, (q15_t)0x6dc, (q15_t)0x60, (q15_t)0x6e8, (q15_t)0x61, (q15_t)0x6f5, (q15_t)0x62, (q15_t)0x701,
+    (q15_t)0x64, (q15_t)0x70e, (q15_t)0x65, (q15_t)0x71a, (q15_t)0x67, (q15_t)0x727, (q15_t)0x68, (q15_t)0x733,
+    (q15_t)0x69, (q15_t)0x740, (q15_t)0x6b, (q15_t)0x74c, (q15_t)0x6c, (q15_t)0x759, (q15_t)0x6e, (q15_t)0x765,
+    (q15_t)0x6f, (q15_t)0x772, (q15_t)0x71, (q15_t)0x77e, (q15_t)0x72, (q15_t)0x78b, (q15_t)0x74, (q15_t)0x797,
+    (q15_t)0x75, (q15_t)0x7a4, (q15_t)0x77, (q15_t)0x7b0, (q15_t)0x78, (q15_t)0x7bd, (q15_t)0x7a, (q15_t)0x7c9,
+    (q15_t)0x7b, (q15_t)0x7d6, (q15_t)0x7d, (q15_t)0x7e2, (q15_t)0x7e, (q15_t)0x7ef, (q15_t)0x80, (q15_t)0x7fb,
+    (q15_t)0x81, (q15_t)0x807, (q15_t)0x83, (q15_t)0x814, (q15_t)0x85, (q15_t)0x820, (q15_t)0x86, (q15_t)0x82d,
+    (q15_t)0x88, (q15_t)0x839, (q15_t)0x89, (q15_t)0x846, (q15_t)0x8b, (q15_t)0x852, (q15_t)0x8d, (q15_t)0x85f,
+    (q15_t)0x8e, (q15_t)0x86b, (q15_t)0x90, (q15_t)0x878, (q15_t)0x92, (q15_t)0x884, (q15_t)0x93, (q15_t)0x891,
+    (q15_t)0x95, (q15_t)0x89d, (q15_t)0x97, (q15_t)0x8a9, (q15_t)0x98, (q15_t)0x8b6, (q15_t)0x9a, (q15_t)0x8c2,
+    (q15_t)0x9c, (q15_t)0x8cf, (q15_t)0x9e, (q15_t)0x8db, (q15_t)0x9f, (q15_t)0x8e8, (q15_t)0xa1, (q15_t)0x8f4,
+    (q15_t)0xa3, (q15_t)0x901, (q15_t)0xa5, (q15_t)0x90d, (q15_t)0xa6, (q15_t)0x919, (q15_t)0xa8, (q15_t)0x926,
+    (q15_t)0xaa, (q15_t)0x932, (q15_t)0xac, (q15_t)0x93f, (q15_t)0xae, (q15_t)0x94b, (q15_t)0xaf, (q15_t)0x958,
+    (q15_t)0xb1, (q15_t)0x964, (q15_t)0xb3, (q15_t)0x970, (q15_t)0xb5, (q15_t)0x97d, (q15_t)0xb7, (q15_t)0x989,
+    (q15_t)0xb9, (q15_t)0x996, (q15_t)0xbb, (q15_t)0x9a2, (q15_t)0xbd, (q15_t)0x9af, (q15_t)0xbe, (q15_t)0x9bb,
+    (q15_t)0xc0, (q15_t)0x9c7, (q15_t)0xc2, (q15_t)0x9d4, (q15_t)0xc4, (q15_t)0x9e0, (q15_t)0xc6, (q15_t)0x9ed,
+    (q15_t)0xc8, (q15_t)0x9f9, (q15_t)0xca, (q15_t)0xa06, (q15_t)0xcc, (q15_t)0xa12, (q15_t)0xce, (q15_t)0xa1e,
+    (q15_t)0xd0, (q15_t)0xa2b, (q15_t)0xd2, (q15_t)0xa37, (q15_t)0xd4, (q15_t)0xa44, (q15_t)0xd6, (q15_t)0xa50,
+    (q15_t)0xd8, (q15_t)0xa5c, (q15_t)0xda, (q15_t)0xa69, (q15_t)0xdc, (q15_t)0xa75, (q15_t)0xde, (q15_t)0xa82,
+    (q15_t)0xe0, (q15_t)0xa8e, (q15_t)0xe2, (q15_t)0xa9a, (q15_t)0xe4, (q15_t)0xaa7, (q15_t)0xe7, (q15_t)0xab3,
+    (q15_t)0xe9, (q15_t)0xac0, (q15_t)0xeb, (q15_t)0xacc, (q15_t)0xed, (q15_t)0xad8, (q15_t)0xef, (q15_t)0xae5,
+    (q15_t)0xf1, (q15_t)0xaf1, (q15_t)0xf3, (q15_t)0xafd, (q15_t)0xf6, (q15_t)0xb0a, (q15_t)0xf8, (q15_t)0xb16,
+    (q15_t)0xfa, (q15_t)0xb23, (q15_t)0xfc, (q15_t)0xb2f, (q15_t)0xfe, (q15_t)0xb3b, (q15_t)0x100, (q15_t)0xb48,
+    (q15_t)0x103, (q15_t)0xb54, (q15_t)0x105, (q15_t)0xb60, (q15_t)0x107, (q15_t)0xb6d, (q15_t)0x109, (q15_t)0xb79,
+    (q15_t)0x10c, (q15_t)0xb85, (q15_t)0x10e, (q15_t)0xb92, (q15_t)0x110, (q15_t)0xb9e, (q15_t)0x113, (q15_t)0xbab,
+    (q15_t)0x115, (q15_t)0xbb7, (q15_t)0x117, (q15_t)0xbc3, (q15_t)0x119, (q15_t)0xbd0, (q15_t)0x11c, (q15_t)0xbdc,
+    (q15_t)0x11e, (q15_t)0xbe8, (q15_t)0x120, (q15_t)0xbf5, (q15_t)0x123, (q15_t)0xc01, (q15_t)0x125, (q15_t)0xc0d,
+    (q15_t)0x128, (q15_t)0xc1a, (q15_t)0x12a, (q15_t)0xc26, (q15_t)0x12c, (q15_t)0xc32, (q15_t)0x12f, (q15_t)0xc3f,
+    (q15_t)0x131, (q15_t)0xc4b, (q15_t)0x134, (q15_t)0xc57, (q15_t)0x136, (q15_t)0xc64, (q15_t)0x138, (q15_t)0xc70,
+    (q15_t)0x13b, (q15_t)0xc7c, (q15_t)0x13d, (q15_t)0xc89, (q15_t)0x140, (q15_t)0xc95, (q15_t)0x142, (q15_t)0xca1,
+    (q15_t)0x145, (q15_t)0xcae, (q15_t)0x147, (q15_t)0xcba, (q15_t)0x14a, (q15_t)0xcc6, (q15_t)0x14c, (q15_t)0xcd3,
+    (q15_t)0x14f, (q15_t)0xcdf, (q15_t)0x151, (q15_t)0xceb, (q15_t)0x154, (q15_t)0xcf8, (q15_t)0x156, (q15_t)0xd04,
+    (q15_t)0x159, (q15_t)0xd10, (q15_t)0x15b, (q15_t)0xd1c, (q15_t)0x15e, (q15_t)0xd29, (q15_t)0x161, (q15_t)0xd35,
+    (q15_t)0x163, (q15_t)0xd41, (q15_t)0x166, (q15_t)0xd4e, (q15_t)0x168, (q15_t)0xd5a, (q15_t)0x16b, (q15_t)0xd66,
+    (q15_t)0x16e, (q15_t)0xd72, (q15_t)0x170, (q15_t)0xd7f, (q15_t)0x173, (q15_t)0xd8b, (q15_t)0x176, (q15_t)0xd97,
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+    (q15_t)0x183, (q15_t)0xdd5, (q15_t)0x186, (q15_t)0xde1, (q15_t)0x189, (q15_t)0xded, (q15_t)0x18b, (q15_t)0xdf9,
+    (q15_t)0x18e, (q15_t)0xe06, (q15_t)0x191, (q15_t)0xe12, (q15_t)0x194, (q15_t)0xe1e, (q15_t)0x196, (q15_t)0xe2b,
+    (q15_t)0x199, (q15_t)0xe37, (q15_t)0x19c, (q15_t)0xe43, (q15_t)0x19f, (q15_t)0xe4f, (q15_t)0x1a2, (q15_t)0xe5c,
+    (q15_t)0x1a4, (q15_t)0xe68, (q15_t)0x1a7, (q15_t)0xe74, (q15_t)0x1aa, (q15_t)0xe80, (q15_t)0x1ad, (q15_t)0xe8c,
+    (q15_t)0x1b0, (q15_t)0xe99, (q15_t)0x1b3, (q15_t)0xea5, (q15_t)0x1b6, (q15_t)0xeb1, (q15_t)0x1b8, (q15_t)0xebd,
+    (q15_t)0x1bb, (q15_t)0xeca, (q15_t)0x1be, (q15_t)0xed6, (q15_t)0x1c1, (q15_t)0xee2, (q15_t)0x1c4, (q15_t)0xeee,
+    (q15_t)0x1c7, (q15_t)0xefb, (q15_t)0x1ca, (q15_t)0xf07, (q15_t)0x1cd, (q15_t)0xf13, (q15_t)0x1d0, (q15_t)0xf1f,
+    (q15_t)0x1d3, (q15_t)0xf2b, (q15_t)0x1d6, (q15_t)0xf38, (q15_t)0x1d9, (q15_t)0xf44, (q15_t)0x1dc, (q15_t)0xf50,
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+    (q15_t)0x1eb, (q15_t)0xf8d, (q15_t)0x1ee, (q15_t)0xf99, (q15_t)0x1f1, (q15_t)0xfa5, (q15_t)0x1f4, (q15_t)0xfb2,
+    (q15_t)0x1f7, (q15_t)0xfbe, (q15_t)0x1fa, (q15_t)0xfca, (q15_t)0x1fd, (q15_t)0xfd6, (q15_t)0x201, (q15_t)0xfe2,
+    (q15_t)0x204, (q15_t)0xfee, (q15_t)0x207, (q15_t)0xffb, (q15_t)0x20a, (q15_t)0x1007, (q15_t)0x20d, (q15_t)0x1013,
+    (q15_t)0x210, (q15_t)0x101f, (q15_t)0x213, (q15_t)0x102b, (q15_t)0x217, (q15_t)0x1037, (q15_t)0x21a, (q15_t)0x1044,
+    (q15_t)0x21d, (q15_t)0x1050, (q15_t)0x220, (q15_t)0x105c, (q15_t)0x223, (q15_t)0x1068, (q15_t)0x227, (q15_t)0x1074,
+    (q15_t)0x22a, (q15_t)0x1080, (q15_t)0x22d, (q15_t)0x108c, (q15_t)0x230, (q15_t)0x1099, (q15_t)0x234, (q15_t)0x10a5,
+    (q15_t)0x237, (q15_t)0x10b1, (q15_t)0x23a, (q15_t)0x10bd, (q15_t)0x23e, (q15_t)0x10c9, (q15_t)0x241, (q15_t)0x10d5,
+    (q15_t)0x244, (q15_t)0x10e1, (q15_t)0x247, (q15_t)0x10ed, (q15_t)0x24b, (q15_t)0x10fa, (q15_t)0x24e, (q15_t)0x1106,
+    (q15_t)0x251, (q15_t)0x1112, (q15_t)0x255, (q15_t)0x111e, (q15_t)0x258, (q15_t)0x112a, (q15_t)0x25c, (q15_t)0x1136,
+    (q15_t)0x25f, (q15_t)0x1142, (q15_t)0x262, (q15_t)0x114e, (q15_t)0x266, (q15_t)0x115a, (q15_t)0x269, (q15_t)0x1167,
+    (q15_t)0x26d, (q15_t)0x1173, (q15_t)0x270, (q15_t)0x117f, (q15_t)0x273, (q15_t)0x118b, (q15_t)0x277, (q15_t)0x1197,
+    (q15_t)0x27a, (q15_t)0x11a3, (q15_t)0x27e, (q15_t)0x11af, (q15_t)0x281, (q15_t)0x11bb, (q15_t)0x285, (q15_t)0x11c7,
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+    (q15_t)0x296, (q15_t)0x1204, (q15_t)0x29a, (q15_t)0x1210, (q15_t)0x29d, (q15_t)0x121c, (q15_t)0x2a1, (q15_t)0x1228,
+    (q15_t)0x2a5, (q15_t)0x1234, (q15_t)0x2a8, (q15_t)0x1240, (q15_t)0x2ac, (q15_t)0x124c, (q15_t)0x2af, (q15_t)0x1258,
+    (q15_t)0x2b3, (q15_t)0x1264, (q15_t)0x2b7, (q15_t)0x1270, (q15_t)0x2ba, (q15_t)0x127c, (q15_t)0x2be, (q15_t)0x1288,
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+    (q15_t)0x2fd, (q15_t)0x1354, (q15_t)0x301, (q15_t)0x1360, (q15_t)0x305, (q15_t)0x136c, (q15_t)0x308, (q15_t)0x1378,
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+    (q15_t)0x31c, (q15_t)0x13b4, (q15_t)0x320, (q15_t)0x13c0, (q15_t)0x323, (q15_t)0x13cc, (q15_t)0x327, (q15_t)0x13d8,
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+    (q15_t)0x493, (q15_t)0x17c4, (q15_t)0x498, (q15_t)0x17cf, (q15_t)0x49d, (q15_t)0x17db, (q15_t)0x4a1, (q15_t)0x17e7,
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+    (q15_t)0x4b9, (q15_t)0x1821, (q15_t)0x4be, (q15_t)0x182d, (q15_t)0x4c2, (q15_t)0x1838, (q15_t)0x4c7, (q15_t)0x1844,
+    (q15_t)0x4cc, (q15_t)0x184f, (q15_t)0x4d1, (q15_t)0x185b, (q15_t)0x4d6, (q15_t)0x1867, (q15_t)0x4da, (q15_t)0x1872,
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+    (q15_t)0x5bb, (q15_t)0x1a79, (q15_t)0x5c1, (q15_t)0x1a84, (q15_t)0x5c6, (q15_t)0x1a90, (q15_t)0x5cb, (q15_t)0x1a9b,
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+    (q15_t)0x610, (q15_t)0x1b30, (q15_t)0x615, (q15_t)0x1b3b, (q15_t)0x61a, (q15_t)0x1b46, (q15_t)0x620, (q15_t)0x1b52,
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+    (q15_t)0x6bf, (q15_t)0x1c99, (q15_t)0x6c5, (q15_t)0x1ca5, (q15_t)0x6ca, (q15_t)0x1cb0, (q15_t)0x6d0, (q15_t)0x1cbb,
+    (q15_t)0x6d5, (q15_t)0x1cc6, (q15_t)0x6db, (q15_t)0x1cd2, (q15_t)0x6e1, (q15_t)0x1cdd, (q15_t)0x6e6, (q15_t)0x1ce8,
+    (q15_t)0x6ec, (q15_t)0x1cf3, (q15_t)0x6f2, (q15_t)0x1cff, (q15_t)0x6f7, (q15_t)0x1d0a, (q15_t)0x6fd, (q15_t)0x1d15,
+    (q15_t)0x703, (q15_t)0x1d20, (q15_t)0x709, (q15_t)0x1d2b, (q15_t)0x70e, (q15_t)0x1d36, (q15_t)0x714, (q15_t)0x1d42,
+    (q15_t)0x71a, (q15_t)0x1d4d, (q15_t)0x720, (q15_t)0x1d58, (q15_t)0x725, (q15_t)0x1d63, (q15_t)0x72b, (q15_t)0x1d6e,
+    (q15_t)0x731, (q15_t)0x1d79, (q15_t)0x737, (q15_t)0x1d85, (q15_t)0x73d, (q15_t)0x1d90, (q15_t)0x742, (q15_t)0x1d9b,
+    (q15_t)0x748, (q15_t)0x1da6, (q15_t)0x74e, (q15_t)0x1db1, (q15_t)0x754, (q15_t)0x1dbc, (q15_t)0x75a, (q15_t)0x1dc7,
+    (q15_t)0x75f, (q15_t)0x1dd3, (q15_t)0x765, (q15_t)0x1dde, (q15_t)0x76b, (q15_t)0x1de9, (q15_t)0x771, (q15_t)0x1df4,
+    (q15_t)0x777, (q15_t)0x1dff, (q15_t)0x77d, (q15_t)0x1e0a, (q15_t)0x783, (q15_t)0x1e15, (q15_t)0x789, (q15_t)0x1e20,
+    (q15_t)0x78f, (q15_t)0x1e2b, (q15_t)0x795, (q15_t)0x1e36, (q15_t)0x79a, (q15_t)0x1e42, (q15_t)0x7a0, (q15_t)0x1e4d,
+    (q15_t)0x7a6, (q15_t)0x1e58, (q15_t)0x7ac, (q15_t)0x1e63, (q15_t)0x7b2, (q15_t)0x1e6e, (q15_t)0x7b8, (q15_t)0x1e79,
+    (q15_t)0x7be, (q15_t)0x1e84, (q15_t)0x7c4, (q15_t)0x1e8f, (q15_t)0x7ca, (q15_t)0x1e9a, (q15_t)0x7d0, (q15_t)0x1ea5,
+    (q15_t)0x7d6, (q15_t)0x1eb0, (q15_t)0x7dc, (q15_t)0x1ebb, (q15_t)0x7e2, (q15_t)0x1ec6, (q15_t)0x7e8, (q15_t)0x1ed1,
+    (q15_t)0x7ee, (q15_t)0x1edc, (q15_t)0x7f5, (q15_t)0x1ee7, (q15_t)0x7fb, (q15_t)0x1ef2, (q15_t)0x801, (q15_t)0x1efd,
+    (q15_t)0x807, (q15_t)0x1f08, (q15_t)0x80d, (q15_t)0x1f13, (q15_t)0x813, (q15_t)0x1f1e, (q15_t)0x819, (q15_t)0x1f29,
+    (q15_t)0x81f, (q15_t)0x1f34, (q15_t)0x825, (q15_t)0x1f3f, (q15_t)0x82b, (q15_t)0x1f4a, (q15_t)0x832, (q15_t)0x1f55,
+    (q15_t)0x838, (q15_t)0x1f60, (q15_t)0x83e, (q15_t)0x1f6b, (q15_t)0x844, (q15_t)0x1f76, (q15_t)0x84a, (q15_t)0x1f81,
+    (q15_t)0x850, (q15_t)0x1f8c, (q15_t)0x857, (q15_t)0x1f97, (q15_t)0x85d, (q15_t)0x1fa2, (q15_t)0x863, (q15_t)0x1fac,
+    (q15_t)0x869, (q15_t)0x1fb7, (q15_t)0x870, (q15_t)0x1fc2, (q15_t)0x876, (q15_t)0x1fcd, (q15_t)0x87c, (q15_t)0x1fd8,
+    (q15_t)0x882, (q15_t)0x1fe3, (q15_t)0x889, (q15_t)0x1fee, (q15_t)0x88f, (q15_t)0x1ff9, (q15_t)0x895, (q15_t)0x2004,
+    (q15_t)0x89b, (q15_t)0x200f, (q15_t)0x8a2, (q15_t)0x2019, (q15_t)0x8a8, (q15_t)0x2024, (q15_t)0x8ae, (q15_t)0x202f,
+    (q15_t)0x8b5, (q15_t)0x203a, (q15_t)0x8bb, (q15_t)0x2045, (q15_t)0x8c1, (q15_t)0x2050, (q15_t)0x8c8, (q15_t)0x205b,
+    (q15_t)0x8ce, (q15_t)0x2065, (q15_t)0x8d4, (q15_t)0x2070, (q15_t)0x8db, (q15_t)0x207b, (q15_t)0x8e1, (q15_t)0x2086,
+    (q15_t)0x8e8, (q15_t)0x2091, (q15_t)0x8ee, (q15_t)0x209b, (q15_t)0x8f4, (q15_t)0x20a6, (q15_t)0x8fb, (q15_t)0x20b1,
+    (q15_t)0x901, (q15_t)0x20bc, (q15_t)0x908, (q15_t)0x20c7, (q15_t)0x90e, (q15_t)0x20d1, (q15_t)0x915, (q15_t)0x20dc,
+    (q15_t)0x91b, (q15_t)0x20e7, (q15_t)0x921, (q15_t)0x20f2, (q15_t)0x928, (q15_t)0x20fd, (q15_t)0x92e, (q15_t)0x2107,
+    (q15_t)0x935, (q15_t)0x2112, (q15_t)0x93b, (q15_t)0x211d, (q15_t)0x942, (q15_t)0x2128, (q15_t)0x948, (q15_t)0x2132,
+    (q15_t)0x94f, (q15_t)0x213d, (q15_t)0x955, (q15_t)0x2148, (q15_t)0x95c, (q15_t)0x2153, (q15_t)0x963, (q15_t)0x215d,
+    (q15_t)0x969, (q15_t)0x2168, (q15_t)0x970, (q15_t)0x2173, (q15_t)0x976, (q15_t)0x217d, (q15_t)0x97d, (q15_t)0x2188,
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+    (q15_t)0x99e, (q15_t)0x21be, (q15_t)0x9a4, (q15_t)0x21c8, (q15_t)0x9ab, (q15_t)0x21d3, (q15_t)0x9b2, (q15_t)0x21de,
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+    (q15_t)0xdab, (q15_t)0x2788, (q15_t)0xdb2, (q15_t)0x2791, (q15_t)0xdba, (q15_t)0x279b, (q15_t)0xdc2, (q15_t)0x27a5,
+    (q15_t)0xdca, (q15_t)0x27af, (q15_t)0xdd2, (q15_t)0x27b9, (q15_t)0xdd9, (q15_t)0x27c3, (q15_t)0xde1, (q15_t)0x27cd,
+    (q15_t)0xde9, (q15_t)0x27d6, (q15_t)0xdf1, (q15_t)0x27e0, (q15_t)0xdf9, (q15_t)0x27ea, (q15_t)0xe01, (q15_t)0x27f4,
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+    (q15_t)0xe28, (q15_t)0x2825, (q15_t)0xe30, (q15_t)0x282f, (q15_t)0xe38, (q15_t)0x2838, (q15_t)0xe40, (q15_t)0x2842,
+    (q15_t)0xe47, (q15_t)0x284c, (q15_t)0xe4f, (q15_t)0x2856, (q15_t)0xe57, (q15_t)0x2860, (q15_t)0xe5f, (q15_t)0x2869,
+    (q15_t)0xe67, (q15_t)0x2873, (q15_t)0xe6f, (q15_t)0x287d, (q15_t)0xe77, (q15_t)0x2886, (q15_t)0xe7f, (q15_t)0x2890,
+    (q15_t)0xe87, (q15_t)0x289a, (q15_t)0xe8f, (q15_t)0x28a4, (q15_t)0xe97, (q15_t)0x28ad, (q15_t)0xe9f, (q15_t)0x28b7,
+    (q15_t)0xea7, (q15_t)0x28c1, (q15_t)0xeaf, (q15_t)0x28ca, (q15_t)0xeb7, (q15_t)0x28d4, (q15_t)0xebf, (q15_t)0x28de,
+    (q15_t)0xec7, (q15_t)0x28e7, (q15_t)0xecf, (q15_t)0x28f1, (q15_t)0xed7, (q15_t)0x28fb, (q15_t)0xedf, (q15_t)0x2904,
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+    (q15_t)0xfab, (q15_t)0x29f4, (q15_t)0xfb3, (q15_t)0x29fd, (q15_t)0xfbb, (q15_t)0x2a07, (q15_t)0xfc4, (q15_t)0x2a10,
+    (q15_t)0xfcc, (q15_t)0x2a1a, (q15_t)0xfd4, (q15_t)0x2a23, (q15_t)0xfdc, (q15_t)0x2a2c, (q15_t)0xfe5, (q15_t)0x2a36,
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+    (q15_t)0x100e, (q15_t)0x2a65, (q15_t)0x1016, (q15_t)0x2a6e, (q15_t)0x101f, (q15_t)0x2a78, (q15_t)0x1027, (q15_t)0x2a81,
+    (q15_t)0x1030, (q15_t)0x2a8b, (q15_t)0x1038, (q15_t)0x2a94, (q15_t)0x1040, (q15_t)0x2a9d, (q15_t)0x1049, (q15_t)0x2aa7,
+    (q15_t)0x1051, (q15_t)0x2ab0, (q15_t)0x1059, (q15_t)0x2ab9, (q15_t)0x1062, (q15_t)0x2ac3, (q15_t)0x106a, (q15_t)0x2acc,
+    (q15_t)0x1073, (q15_t)0x2ad6, (q15_t)0x107b, (q15_t)0x2adf, (q15_t)0x1083, (q15_t)0x2ae8, (q15_t)0x108c, (q15_t)0x2af2,
+    (q15_t)0x1094, (q15_t)0x2afb, (q15_t)0x109d, (q15_t)0x2b04, (q15_t)0x10a5, (q15_t)0x2b0d, (q15_t)0x10ae, (q15_t)0x2b17,
+    (q15_t)0x10b6, (q15_t)0x2b20, (q15_t)0x10bf, (q15_t)0x2b29, (q15_t)0x10c7, (q15_t)0x2b33, (q15_t)0x10d0, (q15_t)0x2b3c,
+    (q15_t)0x10d8, (q15_t)0x2b45, (q15_t)0x10e0, (q15_t)0x2b4e, (q15_t)0x10e9, (q15_t)0x2b58, (q15_t)0x10f2, (q15_t)0x2b61,
+    (q15_t)0x10fa, (q15_t)0x2b6a, (q15_t)0x1103, (q15_t)0x2b73, (q15_t)0x110b, (q15_t)0x2b7d, (q15_t)0x1114, (q15_t)0x2b86,
+    (q15_t)0x111c, (q15_t)0x2b8f, (q15_t)0x1125, (q15_t)0x2b98, (q15_t)0x112d, (q15_t)0x2ba1, (q15_t)0x1136, (q15_t)0x2bab,
+    (q15_t)0x113e, (q15_t)0x2bb4, (q15_t)0x1147, (q15_t)0x2bbd, (q15_t)0x1150, (q15_t)0x2bc6, (q15_t)0x1158, (q15_t)0x2bcf,
+    (q15_t)0x1161, (q15_t)0x2bd8, (q15_t)0x1169, (q15_t)0x2be2, (q15_t)0x1172, (q15_t)0x2beb, (q15_t)0x117b, (q15_t)0x2bf4,
+    (q15_t)0x1183, (q15_t)0x2bfd, (q15_t)0x118c, (q15_t)0x2c06, (q15_t)0x1195, (q15_t)0x2c0f, (q15_t)0x119d, (q15_t)0x2c18,
+    (q15_t)0x11a6, (q15_t)0x2c21, (q15_t)0x11af, (q15_t)0x2c2b, (q15_t)0x11b7, (q15_t)0x2c34, (q15_t)0x11c0, (q15_t)0x2c3d,
+    (q15_t)0x11c9, (q15_t)0x2c46, (q15_t)0x11d1, (q15_t)0x2c4f, (q15_t)0x11da, (q15_t)0x2c58, (q15_t)0x11e3, (q15_t)0x2c61,
+    (q15_t)0x11eb, (q15_t)0x2c6a, (q15_t)0x11f4, (q15_t)0x2c73, (q15_t)0x11fd, (q15_t)0x2c7c, (q15_t)0x1206, (q15_t)0x2c85,
+    (q15_t)0x120e, (q15_t)0x2c8e, (q15_t)0x1217, (q15_t)0x2c97, (q15_t)0x1220, (q15_t)0x2ca0, (q15_t)0x1229, (q15_t)0x2ca9,
+    (q15_t)0x1231, (q15_t)0x2cb2, (q15_t)0x123a, (q15_t)0x2cbb, (q15_t)0x1243, (q15_t)0x2cc4, (q15_t)0x124c, (q15_t)0x2ccd,
+    (q15_t)0x1255, (q15_t)0x2cd6, (q15_t)0x125d, (q15_t)0x2cdf, (q15_t)0x1266, (q15_t)0x2ce8, (q15_t)0x126f, (q15_t)0x2cf1,
+    (q15_t)0x1278, (q15_t)0x2cfa, (q15_t)0x1281, (q15_t)0x2d03, (q15_t)0x128a, (q15_t)0x2d0c, (q15_t)0x1292, (q15_t)0x2d15,
+    (q15_t)0x129b, (q15_t)0x2d1e, (q15_t)0x12a4, (q15_t)0x2d27, (q15_t)0x12ad, (q15_t)0x2d2f, (q15_t)0x12b6, (q15_t)0x2d38,
+    (q15_t)0x12bf, (q15_t)0x2d41, (q15_t)0x12c8, (q15_t)0x2d4a, (q15_t)0x12d1, (q15_t)0x2d53, (q15_t)0x12d9, (q15_t)0x2d5c,
+    (q15_t)0x12e2, (q15_t)0x2d65, (q15_t)0x12eb, (q15_t)0x2d6e, (q15_t)0x12f4, (q15_t)0x2d76, (q15_t)0x12fd, (q15_t)0x2d7f,
+    (q15_t)0x1306, (q15_t)0x2d88, (q15_t)0x130f, (q15_t)0x2d91, (q15_t)0x1318, (q15_t)0x2d9a, (q15_t)0x1321, (q15_t)0x2da3,
+    (q15_t)0x132a, (q15_t)0x2dab, (q15_t)0x1333, (q15_t)0x2db4, (q15_t)0x133c, (q15_t)0x2dbd, (q15_t)0x1345, (q15_t)0x2dc6,
+    (q15_t)0x134e, (q15_t)0x2dcf, (q15_t)0x1357, (q15_t)0x2dd7, (q15_t)0x1360, (q15_t)0x2de0, (q15_t)0x1369, (q15_t)0x2de9,
+    (q15_t)0x1372, (q15_t)0x2df2, (q15_t)0x137b, (q15_t)0x2dfa, (q15_t)0x1384, (q15_t)0x2e03, (q15_t)0x138d, (q15_t)0x2e0c,
+    (q15_t)0x1396, (q15_t)0x2e15, (q15_t)0x139f, (q15_t)0x2e1d, (q15_t)0x13a8, (q15_t)0x2e26, (q15_t)0x13b1, (q15_t)0x2e2f,
+    (q15_t)0x13ba, (q15_t)0x2e37, (q15_t)0x13c3, (q15_t)0x2e40, (q15_t)0x13cc, (q15_t)0x2e49, (q15_t)0x13d5, (q15_t)0x2e51,
+    (q15_t)0x13df, (q15_t)0x2e5a, (q15_t)0x13e8, (q15_t)0x2e63, (q15_t)0x13f1, (q15_t)0x2e6b, (q15_t)0x13fa, (q15_t)0x2e74,
+    (q15_t)0x1403, (q15_t)0x2e7d, (q15_t)0x140c, (q15_t)0x2e85, (q15_t)0x1415, (q15_t)0x2e8e, (q15_t)0x141e, (q15_t)0x2e97,
+    (q15_t)0x1428, (q15_t)0x2e9f, (q15_t)0x1431, (q15_t)0x2ea8, (q15_t)0x143a, (q15_t)0x2eb0, (q15_t)0x1443, (q15_t)0x2eb9,
+    (q15_t)0x144c, (q15_t)0x2ec2, (q15_t)0x1455, (q15_t)0x2eca, (q15_t)0x145f, (q15_t)0x2ed3, (q15_t)0x1468, (q15_t)0x2edb,
+    (q15_t)0x1471, (q15_t)0x2ee4, (q15_t)0x147a, (q15_t)0x2eec, (q15_t)0x1483, (q15_t)0x2ef5, (q15_t)0x148d, (q15_t)0x2efd,
+    (q15_t)0x1496, (q15_t)0x2f06, (q15_t)0x149f, (q15_t)0x2f0e, (q15_t)0x14a8, (q15_t)0x2f17, (q15_t)0x14b2, (q15_t)0x2f20,
+    (q15_t)0x14bb, (q15_t)0x2f28, (q15_t)0x14c4, (q15_t)0x2f30, (q15_t)0x14cd, (q15_t)0x2f39, (q15_t)0x14d7, (q15_t)0x2f41,
+    (q15_t)0x14e0, (q15_t)0x2f4a, (q15_t)0x14e9, (q15_t)0x2f52, (q15_t)0x14f3, (q15_t)0x2f5b, (q15_t)0x14fc, (q15_t)0x2f63,
+    (q15_t)0x1505, (q15_t)0x2f6c, (q15_t)0x150e, (q15_t)0x2f74, (q15_t)0x1518, (q15_t)0x2f7d, (q15_t)0x1521, (q15_t)0x2f85,
+    (q15_t)0x152a, (q15_t)0x2f8d, (q15_t)0x1534, (q15_t)0x2f96, (q15_t)0x153d, (q15_t)0x2f9e, (q15_t)0x1547, (q15_t)0x2fa7,
+    (q15_t)0x1550, (q15_t)0x2faf, (q15_t)0x1559, (q15_t)0x2fb7, (q15_t)0x1563, (q15_t)0x2fc0, (q15_t)0x156c, (q15_t)0x2fc8,
+    (q15_t)0x1575, (q15_t)0x2fd0, (q15_t)0x157f, (q15_t)0x2fd9, (q15_t)0x1588, (q15_t)0x2fe1, (q15_t)0x1592, (q15_t)0x2fea,
+    (q15_t)0x159b, (q15_t)0x2ff2, (q15_t)0x15a4, (q15_t)0x2ffa, (q15_t)0x15ae, (q15_t)0x3002, (q15_t)0x15b7, (q15_t)0x300b,
+    (q15_t)0x15c1, (q15_t)0x3013, (q15_t)0x15ca, (q15_t)0x301b, (q15_t)0x15d4, (q15_t)0x3024, (q15_t)0x15dd, (q15_t)0x302c,
+    (q15_t)0x15e6, (q15_t)0x3034, (q15_t)0x15f0, (q15_t)0x303c, (q15_t)0x15f9, (q15_t)0x3045, (q15_t)0x1603, (q15_t)0x304d,
+    (q15_t)0x160c, (q15_t)0x3055, (q15_t)0x1616, (q15_t)0x305d, (q15_t)0x161f, (q15_t)0x3066, (q15_t)0x1629, (q15_t)0x306e,
+    (q15_t)0x1632, (q15_t)0x3076, (q15_t)0x163c, (q15_t)0x307e, (q15_t)0x1645, (q15_t)0x3087, (q15_t)0x164f, (q15_t)0x308f,
+    (q15_t)0x1659, (q15_t)0x3097, (q15_t)0x1662, (q15_t)0x309f, (q15_t)0x166c, (q15_t)0x30a7, (q15_t)0x1675, (q15_t)0x30af,
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+    (q15_t)0x16a5, (q15_t)0x30d8, (q15_t)0x16af, (q15_t)0x30e0, (q15_t)0x16b8, (q15_t)0x30e8, (q15_t)0x16c2, (q15_t)0x30f0,
+    (q15_t)0x16cb, (q15_t)0x30f9, (q15_t)0x16d5, (q15_t)0x3101, (q15_t)0x16df, (q15_t)0x3109, (q15_t)0x16e8, (q15_t)0x3111,
+    (q15_t)0x16f2, (q15_t)0x3119, (q15_t)0x16fc, (q15_t)0x3121, (q15_t)0x1705, (q15_t)0x3129, (q15_t)0x170f, (q15_t)0x3131,
+    (q15_t)0x1719, (q15_t)0x3139, (q15_t)0x1722, (q15_t)0x3141, (q15_t)0x172c, (q15_t)0x3149, (q15_t)0x1736, (q15_t)0x3151,
+    (q15_t)0x173f, (q15_t)0x3159, (q15_t)0x1749, (q15_t)0x3161, (q15_t)0x1753, (q15_t)0x3169, (q15_t)0x175c, (q15_t)0x3171,
+    (q15_t)0x1766, (q15_t)0x3179, (q15_t)0x1770, (q15_t)0x3181, (q15_t)0x177a, (q15_t)0x3189, (q15_t)0x1783, (q15_t)0x3191,
+    (q15_t)0x178d, (q15_t)0x3199, (q15_t)0x1797, (q15_t)0x31a1, (q15_t)0x17a0, (q15_t)0x31a9, (q15_t)0x17aa, (q15_t)0x31b1,
+    (q15_t)0x17b4, (q15_t)0x31b9, (q15_t)0x17be, (q15_t)0x31c0, (q15_t)0x17c8, (q15_t)0x31c8, (q15_t)0x17d1, (q15_t)0x31d0,
+    (q15_t)0x17db, (q15_t)0x31d8, (q15_t)0x17e5, (q15_t)0x31e0, (q15_t)0x17ef, (q15_t)0x31e8, (q15_t)0x17f8, (q15_t)0x31f0,
+    (q15_t)0x1802, (q15_t)0x31f8, (q15_t)0x180c, (q15_t)0x31ff, (q15_t)0x1816, (q15_t)0x3207, (q15_t)0x1820, (q15_t)0x320f,
+    (q15_t)0x182a, (q15_t)0x3217, (q15_t)0x1833, (q15_t)0x321f, (q15_t)0x183d, (q15_t)0x3227, (q15_t)0x1847, (q15_t)0x322e,
+    (q15_t)0x1851, (q15_t)0x3236, (q15_t)0x185b, (q15_t)0x323e, (q15_t)0x1865, (q15_t)0x3246, (q15_t)0x186f, (q15_t)0x324e,
+    (q15_t)0x1878, (q15_t)0x3255, (q15_t)0x1882, (q15_t)0x325d, (q15_t)0x188c, (q15_t)0x3265, (q15_t)0x1896, (q15_t)0x326d,
+    (q15_t)0x18a0, (q15_t)0x3274, (q15_t)0x18aa, (q15_t)0x327c, (q15_t)0x18b4, (q15_t)0x3284, (q15_t)0x18be, (q15_t)0x328b,
+    (q15_t)0x18c8, (q15_t)0x3293, (q15_t)0x18d2, (q15_t)0x329b, (q15_t)0x18dc, (q15_t)0x32a3, (q15_t)0x18e6, (q15_t)0x32aa,
+    (q15_t)0x18ef, (q15_t)0x32b2, (q15_t)0x18f9, (q15_t)0x32ba, (q15_t)0x1903, (q15_t)0x32c1, (q15_t)0x190d, (q15_t)0x32c9,
+    (q15_t)0x1917, (q15_t)0x32d0, (q15_t)0x1921, (q15_t)0x32d8, (q15_t)0x192b, (q15_t)0x32e0, (q15_t)0x1935, (q15_t)0x32e7,
+    (q15_t)0x193f, (q15_t)0x32ef, (q15_t)0x1949, (q15_t)0x32f7, (q15_t)0x1953, (q15_t)0x32fe, (q15_t)0x195d, (q15_t)0x3306,
+    (q15_t)0x1967, (q15_t)0x330d, (q15_t)0x1971, (q15_t)0x3315, (q15_t)0x197b, (q15_t)0x331d, (q15_t)0x1985, (q15_t)0x3324,
+    (q15_t)0x198f, (q15_t)0x332c, (q15_t)0x199a, (q15_t)0x3333, (q15_t)0x19a4, (q15_t)0x333b, (q15_t)0x19ae, (q15_t)0x3342,
+    (q15_t)0x19b8, (q15_t)0x334a, (q15_t)0x19c2, (q15_t)0x3351, (q15_t)0x19cc, (q15_t)0x3359, (q15_t)0x19d6, (q15_t)0x3360,
+    (q15_t)0x19e0, (q15_t)0x3368, (q15_t)0x19ea, (q15_t)0x336f, (q15_t)0x19f4, (q15_t)0x3377, (q15_t)0x19fe, (q15_t)0x337e,
+    (q15_t)0x1a08, (q15_t)0x3386, (q15_t)0x1a13, (q15_t)0x338d, (q15_t)0x1a1d, (q15_t)0x3395, (q15_t)0x1a27, (q15_t)0x339c,
+    (q15_t)0x1a31, (q15_t)0x33a3, (q15_t)0x1a3b, (q15_t)0x33ab, (q15_t)0x1a45, (q15_t)0x33b2, (q15_t)0x1a4f, (q15_t)0x33ba,
+    (q15_t)0x1a5a, (q15_t)0x33c1, (q15_t)0x1a64, (q15_t)0x33c8, (q15_t)0x1a6e, (q15_t)0x33d0, (q15_t)0x1a78, (q15_t)0x33d7,
+    (q15_t)0x1a82, (q15_t)0x33df, (q15_t)0x1a8c, (q15_t)0x33e6, (q15_t)0x1a97, (q15_t)0x33ed, (q15_t)0x1aa1, (q15_t)0x33f5,
+    (q15_t)0x1aab, (q15_t)0x33fc, (q15_t)0x1ab5, (q15_t)0x3403, (q15_t)0x1abf, (q15_t)0x340b, (q15_t)0x1aca, (q15_t)0x3412,
+    (q15_t)0x1ad4, (q15_t)0x3419, (q15_t)0x1ade, (q15_t)0x3420, (q15_t)0x1ae8, (q15_t)0x3428, (q15_t)0x1af3, (q15_t)0x342f,
+    (q15_t)0x1afd, (q15_t)0x3436, (q15_t)0x1b07, (q15_t)0x343e, (q15_t)0x1b11, (q15_t)0x3445, (q15_t)0x1b1c, (q15_t)0x344c,
+    (q15_t)0x1b26, (q15_t)0x3453, (q15_t)0x1b30, (q15_t)0x345b, (q15_t)0x1b3b, (q15_t)0x3462, (q15_t)0x1b45, (q15_t)0x3469,
+    (q15_t)0x1b4f, (q15_t)0x3470, (q15_t)0x1b59, (q15_t)0x3477, (q15_t)0x1b64, (q15_t)0x347f, (q15_t)0x1b6e, (q15_t)0x3486,
+    (q15_t)0x1b78, (q15_t)0x348d, (q15_t)0x1b83, (q15_t)0x3494, (q15_t)0x1b8d, (q15_t)0x349b, (q15_t)0x1b97, (q15_t)0x34a2,
+    (q15_t)0x1ba2, (q15_t)0x34aa, (q15_t)0x1bac, (q15_t)0x34b1, (q15_t)0x1bb6, (q15_t)0x34b8, (q15_t)0x1bc1, (q15_t)0x34bf,
+    (q15_t)0x1bcb, (q15_t)0x34c6, (q15_t)0x1bd5, (q15_t)0x34cd, (q15_t)0x1be0, (q15_t)0x34d4, (q15_t)0x1bea, (q15_t)0x34db,
+    (q15_t)0x1bf5, (q15_t)0x34e2, (q15_t)0x1bff, (q15_t)0x34ea, (q15_t)0x1c09, (q15_t)0x34f1, (q15_t)0x1c14, (q15_t)0x34f8,
+    (q15_t)0x1c1e, (q15_t)0x34ff, (q15_t)0x1c29, (q15_t)0x3506, (q15_t)0x1c33, (q15_t)0x350d, (q15_t)0x1c3d, (q15_t)0x3514,
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+    (q15_t)0x1d44, (q15_t)0x35c1, (q15_t)0x1d4e, (q15_t)0x35c8, (q15_t)0x1d59, (q15_t)0x35ce, (q15_t)0x1d63, (q15_t)0x35d5,
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+    (q15_t)0x1ded, (q15_t)0x362d, (q15_t)0x1df8, (q15_t)0x3634, (q15_t)0x1e02, (q15_t)0x363a, (q15_t)0x1e0d, (q15_t)0x3641,
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+    (q15_t)0x2aa0, (q15_t)0x3c53, (q15_t)0x2aac, (q15_t)0x3c57, (q15_t)0x2ab7, (q15_t)0x3c5b, (q15_t)0x2ac3, (q15_t)0x3c60,
+    (q15_t)0x2acf, (q15_t)0x3c64, (q15_t)0x2adb, (q15_t)0x3c68, (q15_t)0x2ae7, (q15_t)0x3c6c, (q15_t)0x2af3, (q15_t)0x3c70,
+    (q15_t)0x2aff, (q15_t)0x3c74, (q15_t)0x2b0a, (q15_t)0x3c79, (q15_t)0x2b16, (q15_t)0x3c7d, (q15_t)0x2b22, (q15_t)0x3c81,
+    (q15_t)0x2b2e, (q15_t)0x3c85, (q15_t)0x2b3a, (q15_t)0x3c89, (q15_t)0x2b46, (q15_t)0x3c8d, (q15_t)0x2b52, (q15_t)0x3c91,
+    (q15_t)0x2b5e, (q15_t)0x3c95, (q15_t)0x2b6a, (q15_t)0x3c99, (q15_t)0x2b75, (q15_t)0x3c9d, (q15_t)0x2b81, (q15_t)0x3ca1,
+    (q15_t)0x2b8d, (q15_t)0x3ca5, (q15_t)0x2b99, (q15_t)0x3ca9, (q15_t)0x2ba5, (q15_t)0x3cad, (q15_t)0x2bb1, (q15_t)0x3cb1,
+    (q15_t)0x2bbd, (q15_t)0x3cb5, (q15_t)0x2bc9, (q15_t)0x3cb9, (q15_t)0x2bd5, (q15_t)0x3cbd, (q15_t)0x2be1, (q15_t)0x3cc1,
+    (q15_t)0x2bed, (q15_t)0x3cc5, (q15_t)0x2bf9, (q15_t)0x3cc9, (q15_t)0x2c05, (q15_t)0x3ccd, (q15_t)0x2c10, (q15_t)0x3cd1,
+    (q15_t)0x2c1c, (q15_t)0x3cd5, (q15_t)0x2c28, (q15_t)0x3cd9, (q15_t)0x2c34, (q15_t)0x3cdd, (q15_t)0x2c40, (q15_t)0x3ce0,
+    (q15_t)0x2c4c, (q15_t)0x3ce4, (q15_t)0x2c58, (q15_t)0x3ce8, (q15_t)0x2c64, (q15_t)0x3cec, (q15_t)0x2c70, (q15_t)0x3cf0,
+    (q15_t)0x2c7c, (q15_t)0x3cf4, (q15_t)0x2c88, (q15_t)0x3cf8, (q15_t)0x2c94, (q15_t)0x3cfb, (q15_t)0x2ca0, (q15_t)0x3cff,
+    (q15_t)0x2cac, (q15_t)0x3d03, (q15_t)0x2cb8, (q15_t)0x3d07, (q15_t)0x2cc4, (q15_t)0x3d0b, (q15_t)0x2cd0, (q15_t)0x3d0e,
+    (q15_t)0x2cdc, (q15_t)0x3d12, (q15_t)0x2ce8, (q15_t)0x3d16, (q15_t)0x2cf4, (q15_t)0x3d1a, (q15_t)0x2d00, (q15_t)0x3d1d,
+    (q15_t)0x2d0c, (q15_t)0x3d21, (q15_t)0x2d18, (q15_t)0x3d25, (q15_t)0x2d24, (q15_t)0x3d28, (q15_t)0x2d30, (q15_t)0x3d2c,
+    (q15_t)0x2d3c, (q15_t)0x3d30, (q15_t)0x2d48, (q15_t)0x3d34, (q15_t)0x2d54, (q15_t)0x3d37, (q15_t)0x2d60, (q15_t)0x3d3b,
+    (q15_t)0x2d6c, (q15_t)0x3d3f, (q15_t)0x2d78, (q15_t)0x3d42, (q15_t)0x2d84, (q15_t)0x3d46, (q15_t)0x2d90, (q15_t)0x3d49,
+    (q15_t)0x2d9c, (q15_t)0x3d4d, (q15_t)0x2da8, (q15_t)0x3d51, (q15_t)0x2db4, (q15_t)0x3d54, (q15_t)0x2dc0, (q15_t)0x3d58,
+    (q15_t)0x2dcc, (q15_t)0x3d5b, (q15_t)0x2dd8, (q15_t)0x3d5f, (q15_t)0x2de4, (q15_t)0x3d63, (q15_t)0x2df0, (q15_t)0x3d66,
+    (q15_t)0x2dfc, (q15_t)0x3d6a, (q15_t)0x2e09, (q15_t)0x3d6d, (q15_t)0x2e15, (q15_t)0x3d71, (q15_t)0x2e21, (q15_t)0x3d74,
+    (q15_t)0x2e2d, (q15_t)0x3d78, (q15_t)0x2e39, (q15_t)0x3d7b, (q15_t)0x2e45, (q15_t)0x3d7f, (q15_t)0x2e51, (q15_t)0x3d82,
+    (q15_t)0x2e5d, (q15_t)0x3d86, (q15_t)0x2e69, (q15_t)0x3d89, (q15_t)0x2e75, (q15_t)0x3d8d, (q15_t)0x2e81, (q15_t)0x3d90,
+    (q15_t)0x2e8d, (q15_t)0x3d93, (q15_t)0x2e99, (q15_t)0x3d97, (q15_t)0x2ea6, (q15_t)0x3d9a, (q15_t)0x2eb2, (q15_t)0x3d9e,
+    (q15_t)0x2ebe, (q15_t)0x3da1, (q15_t)0x2eca, (q15_t)0x3da4, (q15_t)0x2ed6, (q15_t)0x3da8, (q15_t)0x2ee2, (q15_t)0x3dab,
+    (q15_t)0x2eee, (q15_t)0x3daf, (q15_t)0x2efa, (q15_t)0x3db2, (q15_t)0x2f06, (q15_t)0x3db5, (q15_t)0x2f13, (q15_t)0x3db9,
+    (q15_t)0x2f1f, (q15_t)0x3dbc, (q15_t)0x2f2b, (q15_t)0x3dbf, (q15_t)0x2f37, (q15_t)0x3dc2, (q15_t)0x2f43, (q15_t)0x3dc6,
+    (q15_t)0x2f4f, (q15_t)0x3dc9, (q15_t)0x2f5b, (q15_t)0x3dcc, (q15_t)0x2f67, (q15_t)0x3dd0, (q15_t)0x2f74, (q15_t)0x3dd3,
+    (q15_t)0x2f80, (q15_t)0x3dd6, (q15_t)0x2f8c, (q15_t)0x3dd9, (q15_t)0x2f98, (q15_t)0x3ddd, (q15_t)0x2fa4, (q15_t)0x3de0,
+    (q15_t)0x2fb0, (q15_t)0x3de3, (q15_t)0x2fbc, (q15_t)0x3de6, (q15_t)0x2fc9, (q15_t)0x3de9, (q15_t)0x2fd5, (q15_t)0x3ded,
+    (q15_t)0x2fe1, (q15_t)0x3df0, (q15_t)0x2fed, (q15_t)0x3df3, (q15_t)0x2ff9, (q15_t)0x3df6, (q15_t)0x3005, (q15_t)0x3df9,
+    (q15_t)0x3012, (q15_t)0x3dfc, (q15_t)0x301e, (q15_t)0x3dff, (q15_t)0x302a, (q15_t)0x3e03, (q15_t)0x3036, (q15_t)0x3e06,
+    (q15_t)0x3042, (q15_t)0x3e09, (q15_t)0x304e, (q15_t)0x3e0c, (q15_t)0x305b, (q15_t)0x3e0f, (q15_t)0x3067, (q15_t)0x3e12,
+    (q15_t)0x3073, (q15_t)0x3e15, (q15_t)0x307f, (q15_t)0x3e18, (q15_t)0x308b, (q15_t)0x3e1b, (q15_t)0x3098, (q15_t)0x3e1e,
+    (q15_t)0x30a4, (q15_t)0x3e21, (q15_t)0x30b0, (q15_t)0x3e24, (q15_t)0x30bc, (q15_t)0x3e27, (q15_t)0x30c8, (q15_t)0x3e2a,
+    (q15_t)0x30d5, (q15_t)0x3e2d, (q15_t)0x30e1, (q15_t)0x3e30, (q15_t)0x30ed, (q15_t)0x3e33, (q15_t)0x30f9, (q15_t)0x3e36,
+    (q15_t)0x3105, (q15_t)0x3e39, (q15_t)0x3112, (q15_t)0x3e3c, (q15_t)0x311e, (q15_t)0x3e3f, (q15_t)0x312a, (q15_t)0x3e42,
+    (q15_t)0x3136, (q15_t)0x3e45, (q15_t)0x3143, (q15_t)0x3e48, (q15_t)0x314f, (q15_t)0x3e4a, (q15_t)0x315b, (q15_t)0x3e4d,
+    (q15_t)0x3167, (q15_t)0x3e50, (q15_t)0x3174, (q15_t)0x3e53, (q15_t)0x3180, (q15_t)0x3e56, (q15_t)0x318c, (q15_t)0x3e59,
+    (q15_t)0x3198, (q15_t)0x3e5c, (q15_t)0x31a4, (q15_t)0x3e5e, (q15_t)0x31b1, (q15_t)0x3e61, (q15_t)0x31bd, (q15_t)0x3e64,
+    (q15_t)0x31c9, (q15_t)0x3e67, (q15_t)0x31d5, (q15_t)0x3e6a, (q15_t)0x31e2, (q15_t)0x3e6c, (q15_t)0x31ee, (q15_t)0x3e6f,
+    (q15_t)0x31fa, (q15_t)0x3e72, (q15_t)0x3207, (q15_t)0x3e75, (q15_t)0x3213, (q15_t)0x3e77, (q15_t)0x321f, (q15_t)0x3e7a,
+    (q15_t)0x322b, (q15_t)0x3e7d, (q15_t)0x3238, (q15_t)0x3e80, (q15_t)0x3244, (q15_t)0x3e82, (q15_t)0x3250, (q15_t)0x3e85,
+    (q15_t)0x325c, (q15_t)0x3e88, (q15_t)0x3269, (q15_t)0x3e8a, (q15_t)0x3275, (q15_t)0x3e8d, (q15_t)0x3281, (q15_t)0x3e90,
+    (q15_t)0x328e, (q15_t)0x3e92, (q15_t)0x329a, (q15_t)0x3e95, (q15_t)0x32a6, (q15_t)0x3e98, (q15_t)0x32b2, (q15_t)0x3e9a,
+    (q15_t)0x32bf, (q15_t)0x3e9d, (q15_t)0x32cb, (q15_t)0x3e9f, (q15_t)0x32d7, (q15_t)0x3ea2, (q15_t)0x32e4, (q15_t)0x3ea5,
+    (q15_t)0x32f0, (q15_t)0x3ea7, (q15_t)0x32fc, (q15_t)0x3eaa, (q15_t)0x3308, (q15_t)0x3eac, (q15_t)0x3315, (q15_t)0x3eaf,
+    (q15_t)0x3321, (q15_t)0x3eb1, (q15_t)0x332d, (q15_t)0x3eb4, (q15_t)0x333a, (q15_t)0x3eb6, (q15_t)0x3346, (q15_t)0x3eb9,
+    (q15_t)0x3352, (q15_t)0x3ebb, (q15_t)0x335f, (q15_t)0x3ebe, (q15_t)0x336b, (q15_t)0x3ec0, (q15_t)0x3377, (q15_t)0x3ec3,
+    (q15_t)0x3384, (q15_t)0x3ec5, (q15_t)0x3390, (q15_t)0x3ec8, (q15_t)0x339c, (q15_t)0x3eca, (q15_t)0x33a9, (q15_t)0x3ecc,
+    (q15_t)0x33b5, (q15_t)0x3ecf, (q15_t)0x33c1, (q15_t)0x3ed1, (q15_t)0x33ce, (q15_t)0x3ed4, (q15_t)0x33da, (q15_t)0x3ed6,
+    (q15_t)0x33e6, (q15_t)0x3ed8, (q15_t)0x33f3, (q15_t)0x3edb, (q15_t)0x33ff, (q15_t)0x3edd, (q15_t)0x340b, (q15_t)0x3ee0,
+    (q15_t)0x3418, (q15_t)0x3ee2, (q15_t)0x3424, (q15_t)0x3ee4, (q15_t)0x3430, (q15_t)0x3ee7, (q15_t)0x343d, (q15_t)0x3ee9,
+    (q15_t)0x3449, (q15_t)0x3eeb, (q15_t)0x3455, (q15_t)0x3eed, (q15_t)0x3462, (q15_t)0x3ef0, (q15_t)0x346e, (q15_t)0x3ef2,
+    (q15_t)0x347b, (q15_t)0x3ef4, (q15_t)0x3487, (q15_t)0x3ef7, (q15_t)0x3493, (q15_t)0x3ef9, (q15_t)0x34a0, (q15_t)0x3efb,
+    (q15_t)0x34ac, (q15_t)0x3efd, (q15_t)0x34b8, (q15_t)0x3f00, (q15_t)0x34c5, (q15_t)0x3f02, (q15_t)0x34d1, (q15_t)0x3f04,
+    (q15_t)0x34dd, (q15_t)0x3f06, (q15_t)0x34ea, (q15_t)0x3f08, (q15_t)0x34f6, (q15_t)0x3f0a, (q15_t)0x3503, (q15_t)0x3f0d,
+    (q15_t)0x350f, (q15_t)0x3f0f, (q15_t)0x351b, (q15_t)0x3f11, (q15_t)0x3528, (q15_t)0x3f13, (q15_t)0x3534, (q15_t)0x3f15,
+    (q15_t)0x3540, (q15_t)0x3f17, (q15_t)0x354d, (q15_t)0x3f19, (q15_t)0x3559, (q15_t)0x3f1c, (q15_t)0x3566, (q15_t)0x3f1e,
+    (q15_t)0x3572, (q15_t)0x3f20, (q15_t)0x357e, (q15_t)0x3f22, (q15_t)0x358b, (q15_t)0x3f24, (q15_t)0x3597, (q15_t)0x3f26,
+    (q15_t)0x35a4, (q15_t)0x3f28, (q15_t)0x35b0, (q15_t)0x3f2a, (q15_t)0x35bc, (q15_t)0x3f2c, (q15_t)0x35c9, (q15_t)0x3f2e,
+    (q15_t)0x35d5, (q15_t)0x3f30, (q15_t)0x35e2, (q15_t)0x3f32, (q15_t)0x35ee, (q15_t)0x3f34, (q15_t)0x35fa, (q15_t)0x3f36,
+    (q15_t)0x3607, (q15_t)0x3f38, (q15_t)0x3613, (q15_t)0x3f3a, (q15_t)0x3620, (q15_t)0x3f3c, (q15_t)0x362c, (q15_t)0x3f3e,
+    (q15_t)0x3639, (q15_t)0x3f40, (q15_t)0x3645, (q15_t)0x3f42, (q15_t)0x3651, (q15_t)0x3f43, (q15_t)0x365e, (q15_t)0x3f45,
+    (q15_t)0x366a, (q15_t)0x3f47, (q15_t)0x3677, (q15_t)0x3f49, (q15_t)0x3683, (q15_t)0x3f4b, (q15_t)0x3690, (q15_t)0x3f4d,
+    (q15_t)0x369c, (q15_t)0x3f4f, (q15_t)0x36a8, (q15_t)0x3f51, (q15_t)0x36b5, (q15_t)0x3f52, (q15_t)0x36c1, (q15_t)0x3f54,
+    (q15_t)0x36ce, (q15_t)0x3f56, (q15_t)0x36da, (q15_t)0x3f58, (q15_t)0x36e7, (q15_t)0x3f5a, (q15_t)0x36f3, (q15_t)0x3f5b,
+    (q15_t)0x36ff, (q15_t)0x3f5d, (q15_t)0x370c, (q15_t)0x3f5f, (q15_t)0x3718, (q15_t)0x3f61, (q15_t)0x3725, (q15_t)0x3f62,
+    (q15_t)0x3731, (q15_t)0x3f64, (q15_t)0x373e, (q15_t)0x3f66, (q15_t)0x374a, (q15_t)0x3f68, (q15_t)0x3757, (q15_t)0x3f69,
+    (q15_t)0x3763, (q15_t)0x3f6b, (q15_t)0x376f, (q15_t)0x3f6d, (q15_t)0x377c, (q15_t)0x3f6e, (q15_t)0x3788, (q15_t)0x3f70,
+    (q15_t)0x3795, (q15_t)0x3f72, (q15_t)0x37a1, (q15_t)0x3f73, (q15_t)0x37ae, (q15_t)0x3f75, (q15_t)0x37ba, (q15_t)0x3f77,
+    (q15_t)0x37c7, (q15_t)0x3f78, (q15_t)0x37d3, (q15_t)0x3f7a, (q15_t)0x37e0, (q15_t)0x3f7b, (q15_t)0x37ec, (q15_t)0x3f7d,
+    (q15_t)0x37f9, (q15_t)0x3f7f, (q15_t)0x3805, (q15_t)0x3f80, (q15_t)0x3811, (q15_t)0x3f82, (q15_t)0x381e, (q15_t)0x3f83,
+    (q15_t)0x382a, (q15_t)0x3f85, (q15_t)0x3837, (q15_t)0x3f86, (q15_t)0x3843, (q15_t)0x3f88, (q15_t)0x3850, (q15_t)0x3f89,
+    (q15_t)0x385c, (q15_t)0x3f8b, (q15_t)0x3869, (q15_t)0x3f8c, (q15_t)0x3875, (q15_t)0x3f8e, (q15_t)0x3882, (q15_t)0x3f8f,
+    (q15_t)0x388e, (q15_t)0x3f91, (q15_t)0x389b, (q15_t)0x3f92, (q15_t)0x38a7, (q15_t)0x3f94, (q15_t)0x38b4, (q15_t)0x3f95,
+    (q15_t)0x38c0, (q15_t)0x3f97, (q15_t)0x38cd, (q15_t)0x3f98, (q15_t)0x38d9, (q15_t)0x3f99, (q15_t)0x38e6, (q15_t)0x3f9b,
+    (q15_t)0x38f2, (q15_t)0x3f9c, (q15_t)0x38ff, (q15_t)0x3f9e, (q15_t)0x390b, (q15_t)0x3f9f, (q15_t)0x3918, (q15_t)0x3fa0,
+    (q15_t)0x3924, (q15_t)0x3fa2, (q15_t)0x3931, (q15_t)0x3fa3, (q15_t)0x393d, (q15_t)0x3fa4, (q15_t)0x394a, (q15_t)0x3fa6,
+    (q15_t)0x3956, (q15_t)0x3fa7, (q15_t)0x3963, (q15_t)0x3fa8, (q15_t)0x396f, (q15_t)0x3faa, (q15_t)0x397c, (q15_t)0x3fab,
+    (q15_t)0x3988, (q15_t)0x3fac, (q15_t)0x3995, (q15_t)0x3fad, (q15_t)0x39a1, (q15_t)0x3faf, (q15_t)0x39ae, (q15_t)0x3fb0,
+    (q15_t)0x39ba, (q15_t)0x3fb1, (q15_t)0x39c7, (q15_t)0x3fb2, (q15_t)0x39d3, (q15_t)0x3fb4, (q15_t)0x39e0, (q15_t)0x3fb5,
+    (q15_t)0x39ec, (q15_t)0x3fb6, (q15_t)0x39f9, (q15_t)0x3fb7, (q15_t)0x3a05, (q15_t)0x3fb8, (q15_t)0x3a12, (q15_t)0x3fb9,
+    (q15_t)0x3a1e, (q15_t)0x3fbb, (q15_t)0x3a2b, (q15_t)0x3fbc, (q15_t)0x3a37, (q15_t)0x3fbd, (q15_t)0x3a44, (q15_t)0x3fbe,
+    (q15_t)0x3a50, (q15_t)0x3fbf, (q15_t)0x3a5d, (q15_t)0x3fc0, (q15_t)0x3a69, (q15_t)0x3fc1, (q15_t)0x3a76, (q15_t)0x3fc3,
+    (q15_t)0x3a82, (q15_t)0x3fc4, (q15_t)0x3a8f, (q15_t)0x3fc5, (q15_t)0x3a9b, (q15_t)0x3fc6, (q15_t)0x3aa8, (q15_t)0x3fc7,
+    (q15_t)0x3ab4, (q15_t)0x3fc8, (q15_t)0x3ac1, (q15_t)0x3fc9, (q15_t)0x3acd, (q15_t)0x3fca, (q15_t)0x3ada, (q15_t)0x3fcb,
+    (q15_t)0x3ae6, (q15_t)0x3fcc, (q15_t)0x3af3, (q15_t)0x3fcd, (q15_t)0x3b00, (q15_t)0x3fce, (q15_t)0x3b0c, (q15_t)0x3fcf,
+    (q15_t)0x3b19, (q15_t)0x3fd0, (q15_t)0x3b25, (q15_t)0x3fd1, (q15_t)0x3b32, (q15_t)0x3fd2, (q15_t)0x3b3e, (q15_t)0x3fd3,
+    (q15_t)0x3b4b, (q15_t)0x3fd4, (q15_t)0x3b57, (q15_t)0x3fd5, (q15_t)0x3b64, (q15_t)0x3fd5, (q15_t)0x3b70, (q15_t)0x3fd6,
+    (q15_t)0x3b7d, (q15_t)0x3fd7, (q15_t)0x3b89, (q15_t)0x3fd8, (q15_t)0x3b96, (q15_t)0x3fd9, (q15_t)0x3ba2, (q15_t)0x3fda,
+    (q15_t)0x3baf, (q15_t)0x3fdb, (q15_t)0x3bbc, (q15_t)0x3fdc, (q15_t)0x3bc8, (q15_t)0x3fdc, (q15_t)0x3bd5, (q15_t)0x3fdd,
+    (q15_t)0x3be1, (q15_t)0x3fde, (q15_t)0x3bee, (q15_t)0x3fdf, (q15_t)0x3bfa, (q15_t)0x3fe0, (q15_t)0x3c07, (q15_t)0x3fe0,
+    (q15_t)0x3c13, (q15_t)0x3fe1, (q15_t)0x3c20, (q15_t)0x3fe2, (q15_t)0x3c2c, (q15_t)0x3fe3, (q15_t)0x3c39, (q15_t)0x3fe3,
+    (q15_t)0x3c45, (q15_t)0x3fe4, (q15_t)0x3c52, (q15_t)0x3fe5, (q15_t)0x3c5f, (q15_t)0x3fe6, (q15_t)0x3c6b, (q15_t)0x3fe6,
+    (q15_t)0x3c78, (q15_t)0x3fe7, (q15_t)0x3c84, (q15_t)0x3fe8, (q15_t)0x3c91, (q15_t)0x3fe8, (q15_t)0x3c9d, (q15_t)0x3fe9,
+    (q15_t)0x3caa, (q15_t)0x3fea, (q15_t)0x3cb6, (q15_t)0x3fea, (q15_t)0x3cc3, (q15_t)0x3feb, (q15_t)0x3cd0, (q15_t)0x3fec,
+    (q15_t)0x3cdc, (q15_t)0x3fec, (q15_t)0x3ce9, (q15_t)0x3fed, (q15_t)0x3cf5, (q15_t)0x3fed, (q15_t)0x3d02, (q15_t)0x3fee,
+    (q15_t)0x3d0e, (q15_t)0x3fef, (q15_t)0x3d1b, (q15_t)0x3fef, (q15_t)0x3d27, (q15_t)0x3ff0, (q15_t)0x3d34, (q15_t)0x3ff0,
+    (q15_t)0x3d40, (q15_t)0x3ff1, (q15_t)0x3d4d, (q15_t)0x3ff1, (q15_t)0x3d5a, (q15_t)0x3ff2, (q15_t)0x3d66, (q15_t)0x3ff2,
+    (q15_t)0x3d73, (q15_t)0x3ff3, (q15_t)0x3d7f, (q15_t)0x3ff3, (q15_t)0x3d8c, (q15_t)0x3ff4, (q15_t)0x3d98, (q15_t)0x3ff4,
+    (q15_t)0x3da5, (q15_t)0x3ff5, (q15_t)0x3db2, (q15_t)0x3ff5, (q15_t)0x3dbe, (q15_t)0x3ff6, (q15_t)0x3dcb, (q15_t)0x3ff6,
+    (q15_t)0x3dd7, (q15_t)0x3ff7, (q15_t)0x3de4, (q15_t)0x3ff7, (q15_t)0x3df0, (q15_t)0x3ff7, (q15_t)0x3dfd, (q15_t)0x3ff8,
+    (q15_t)0x3e09, (q15_t)0x3ff8, (q15_t)0x3e16, (q15_t)0x3ff9, (q15_t)0x3e23, (q15_t)0x3ff9, (q15_t)0x3e2f, (q15_t)0x3ff9,
+    (q15_t)0x3e3c, (q15_t)0x3ffa, (q15_t)0x3e48, (q15_t)0x3ffa, (q15_t)0x3e55, (q15_t)0x3ffa, (q15_t)0x3e61, (q15_t)0x3ffb,
+    (q15_t)0x3e6e, (q15_t)0x3ffb, (q15_t)0x3e7a, (q15_t)0x3ffb, (q15_t)0x3e87, (q15_t)0x3ffc, (q15_t)0x3e94, (q15_t)0x3ffc,
+    (q15_t)0x3ea0, (q15_t)0x3ffc, (q15_t)0x3ead, (q15_t)0x3ffc, (q15_t)0x3eb9, (q15_t)0x3ffd, (q15_t)0x3ec6, (q15_t)0x3ffd,
+    (q15_t)0x3ed2, (q15_t)0x3ffd, (q15_t)0x3edf, (q15_t)0x3ffd, (q15_t)0x3eec, (q15_t)0x3ffe, (q15_t)0x3ef8, (q15_t)0x3ffe,
+    (q15_t)0x3f05, (q15_t)0x3ffe, (q15_t)0x3f11, (q15_t)0x3ffe, (q15_t)0x3f1e, (q15_t)0x3ffe, (q15_t)0x3f2a, (q15_t)0x3fff,
+    (q15_t)0x3f37, (q15_t)0x3fff, (q15_t)0x3f44, (q15_t)0x3fff, (q15_t)0x3f50, (q15_t)0x3fff, (q15_t)0x3f5d, (q15_t)0x3fff,
+    (q15_t)0x3f69, (q15_t)0x3fff, (q15_t)0x3f76, (q15_t)0x3fff, (q15_t)0x3f82, (q15_t)0x4000, (q15_t)0x3f8f, (q15_t)0x4000,
+    (q15_t)0x3f9b, (q15_t)0x4000, (q15_t)0x3fa8, (q15_t)0x4000, (q15_t)0x3fb5, (q15_t)0x4000, (q15_t)0x3fc1, (q15_t)0x4000,
+    (q15_t)0x3fce, (q15_t)0x4000, (q15_t)0x3fda, (q15_t)0x4000, (q15_t)0x3fe7, (q15_t)0x4000, (q15_t)0x3ff3, (q15_t)0x4000,
+};
+
+/**
+* \par
+* Generation of real_CoefB array:
+* \par
+* n = 4096
+* 
for (i = 0; i < n; i++)
+*  {
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+*  } 

+* \par
+* Convert to fixed point Q15 format
+*       round(pBTable[i] * pow(2, 15))
+*
+*/
+const q15_t ALIGN4 realCoefBQ15[8192] = {
+    (q15_t)0x4000, (q15_t)0x4000, (q15_t)0x400d, (q15_t)0x4000, (q15_t)0x4019, (q15_t)0x4000, (q15_t)0x4026, (q15_t)0x4000,
+    (q15_t)0x4032, (q15_t)0x4000, (q15_t)0x403f, (q15_t)0x4000, (q15_t)0x404b, (q15_t)0x4000, (q15_t)0x4058, (q15_t)0x4000,
+    (q15_t)0x4065, (q15_t)0x4000, (q15_t)0x4071, (q15_t)0x4000, (q15_t)0x407e, (q15_t)0x4000, (q15_t)0x408a, (q15_t)0x3fff,
+    (q15_t)0x4097, (q15_t)0x3fff, (q15_t)0x40a3, (q15_t)0x3fff, (q15_t)0x40b0, (q15_t)0x3fff, (q15_t)0x40bc, (q15_t)0x3fff,
+    (q15_t)0x40c9, (q15_t)0x3fff, (q15_t)0x40d6, (q15_t)0x3fff, (q15_t)0x40e2, (q15_t)0x3ffe, (q15_t)0x40ef, (q15_t)0x3ffe,
+    (q15_t)0x40fb, (q15_t)0x3ffe, (q15_t)0x4108, (q15_t)0x3ffe, (q15_t)0x4114, (q15_t)0x3ffe, (q15_t)0x4121, (q15_t)0x3ffd,
+    (q15_t)0x412e, (q15_t)0x3ffd, (q15_t)0x413a, (q15_t)0x3ffd, (q15_t)0x4147, (q15_t)0x3ffd, (q15_t)0x4153, (q15_t)0x3ffc,
+    (q15_t)0x4160, (q15_t)0x3ffc, (q15_t)0x416c, (q15_t)0x3ffc, (q15_t)0x4179, (q15_t)0x3ffc, (q15_t)0x4186, (q15_t)0x3ffb,
+    (q15_t)0x4192, (q15_t)0x3ffb, (q15_t)0x419f, (q15_t)0x3ffb, (q15_t)0x41ab, (q15_t)0x3ffa, (q15_t)0x41b8, (q15_t)0x3ffa,
+    (q15_t)0x41c4, (q15_t)0x3ffa, (q15_t)0x41d1, (q15_t)0x3ff9, (q15_t)0x41dd, (q15_t)0x3ff9, (q15_t)0x41ea, (q15_t)0x3ff9,
+    (q15_t)0x41f7, (q15_t)0x3ff8, (q15_t)0x4203, (q15_t)0x3ff8, (q15_t)0x4210, (q15_t)0x3ff7, (q15_t)0x421c, (q15_t)0x3ff7,
+    (q15_t)0x4229, (q15_t)0x3ff7, (q15_t)0x4235, (q15_t)0x3ff6, (q15_t)0x4242, (q15_t)0x3ff6, (q15_t)0x424e, (q15_t)0x3ff5,
+    (q15_t)0x425b, (q15_t)0x3ff5, (q15_t)0x4268, (q15_t)0x3ff4, (q15_t)0x4274, (q15_t)0x3ff4, (q15_t)0x4281, (q15_t)0x3ff3,
+    (q15_t)0x428d, (q15_t)0x3ff3, (q15_t)0x429a, (q15_t)0x3ff2, (q15_t)0x42a6, (q15_t)0x3ff2, (q15_t)0x42b3, (q15_t)0x3ff1,
+    (q15_t)0x42c0, (q15_t)0x3ff1, (q15_t)0x42cc, (q15_t)0x3ff0, (q15_t)0x42d9, (q15_t)0x3ff0, (q15_t)0x42e5, (q15_t)0x3fef,
+    (q15_t)0x42f2, (q15_t)0x3fef, (q15_t)0x42fe, (q15_t)0x3fee, (q15_t)0x430b, (q15_t)0x3fed, (q15_t)0x4317, (q15_t)0x3fed,
+    (q15_t)0x4324, (q15_t)0x3fec, (q15_t)0x4330, (q15_t)0x3fec, (q15_t)0x433d, (q15_t)0x3feb, (q15_t)0x434a, (q15_t)0x3fea,
+    (q15_t)0x4356, (q15_t)0x3fea, (q15_t)0x4363, (q15_t)0x3fe9, (q15_t)0x436f, (q15_t)0x3fe8, (q15_t)0x437c, (q15_t)0x3fe8,
+    (q15_t)0x4388, (q15_t)0x3fe7, (q15_t)0x4395, (q15_t)0x3fe6, (q15_t)0x43a1, (q15_t)0x3fe6, (q15_t)0x43ae, (q15_t)0x3fe5,
+    (q15_t)0x43bb, (q15_t)0x3fe4, (q15_t)0x43c7, (q15_t)0x3fe3, (q15_t)0x43d4, (q15_t)0x3fe3, (q15_t)0x43e0, (q15_t)0x3fe2,
+    (q15_t)0x43ed, (q15_t)0x3fe1, (q15_t)0x43f9, (q15_t)0x3fe0, (q15_t)0x4406, (q15_t)0x3fe0, (q15_t)0x4412, (q15_t)0x3fdf,
+    (q15_t)0x441f, (q15_t)0x3fde, (q15_t)0x442b, (q15_t)0x3fdd, (q15_t)0x4438, (q15_t)0x3fdc, (q15_t)0x4444, (q15_t)0x3fdc,
+    (q15_t)0x4451, (q15_t)0x3fdb, (q15_t)0x445e, (q15_t)0x3fda, (q15_t)0x446a, (q15_t)0x3fd9, (q15_t)0x4477, (q15_t)0x3fd8,
+    (q15_t)0x4483, (q15_t)0x3fd7, (q15_t)0x4490, (q15_t)0x3fd6, (q15_t)0x449c, (q15_t)0x3fd5, (q15_t)0x44a9, (q15_t)0x3fd5,
+    (q15_t)0x44b5, (q15_t)0x3fd4, (q15_t)0x44c2, (q15_t)0x3fd3, (q15_t)0x44ce, (q15_t)0x3fd2, (q15_t)0x44db, (q15_t)0x3fd1,
+    (q15_t)0x44e7, (q15_t)0x3fd0, (q15_t)0x44f4, (q15_t)0x3fcf, (q15_t)0x4500, (q15_t)0x3fce, (q15_t)0x450d, (q15_t)0x3fcd,
+    (q15_t)0x451a, (q15_t)0x3fcc, (q15_t)0x4526, (q15_t)0x3fcb, (q15_t)0x4533, (q15_t)0x3fca, (q15_t)0x453f, (q15_t)0x3fc9,
+    (q15_t)0x454c, (q15_t)0x3fc8, (q15_t)0x4558, (q15_t)0x3fc7, (q15_t)0x4565, (q15_t)0x3fc6, (q15_t)0x4571, (q15_t)0x3fc5,
+    (q15_t)0x457e, (q15_t)0x3fc4, (q15_t)0x458a, (q15_t)0x3fc3, (q15_t)0x4597, (q15_t)0x3fc1, (q15_t)0x45a3, (q15_t)0x3fc0,
+    (q15_t)0x45b0, (q15_t)0x3fbf, (q15_t)0x45bc, (q15_t)0x3fbe, (q15_t)0x45c9, (q15_t)0x3fbd, (q15_t)0x45d5, (q15_t)0x3fbc,
+    (q15_t)0x45e2, (q15_t)0x3fbb, (q15_t)0x45ee, (q15_t)0x3fb9, (q15_t)0x45fb, (q15_t)0x3fb8, (q15_t)0x4607, (q15_t)0x3fb7,
+    (q15_t)0x4614, (q15_t)0x3fb6, (q15_t)0x4620, (q15_t)0x3fb5, (q15_t)0x462d, (q15_t)0x3fb4, (q15_t)0x4639, (q15_t)0x3fb2,
+    (q15_t)0x4646, (q15_t)0x3fb1, (q15_t)0x4652, (q15_t)0x3fb0, (q15_t)0x465f, (q15_t)0x3faf, (q15_t)0x466b, (q15_t)0x3fad,
+    (q15_t)0x4678, (q15_t)0x3fac, (q15_t)0x4684, (q15_t)0x3fab, (q15_t)0x4691, (q15_t)0x3faa, (q15_t)0x469d, (q15_t)0x3fa8,
+    (q15_t)0x46aa, (q15_t)0x3fa7, (q15_t)0x46b6, (q15_t)0x3fa6, (q15_t)0x46c3, (q15_t)0x3fa4, (q15_t)0x46cf, (q15_t)0x3fa3,
+    (q15_t)0x46dc, (q15_t)0x3fa2, (q15_t)0x46e8, (q15_t)0x3fa0, (q15_t)0x46f5, (q15_t)0x3f9f, (q15_t)0x4701, (q15_t)0x3f9e,
+    (q15_t)0x470e, (q15_t)0x3f9c, (q15_t)0x471a, (q15_t)0x3f9b, (q15_t)0x4727, (q15_t)0x3f99, (q15_t)0x4733, (q15_t)0x3f98,
+    (q15_t)0x4740, (q15_t)0x3f97, (q15_t)0x474c, (q15_t)0x3f95, (q15_t)0x4759, (q15_t)0x3f94, (q15_t)0x4765, (q15_t)0x3f92,
+    (q15_t)0x4772, (q15_t)0x3f91, (q15_t)0x477e, (q15_t)0x3f8f, (q15_t)0x478b, (q15_t)0x3f8e, (q15_t)0x4797, (q15_t)0x3f8c,
+    (q15_t)0x47a4, (q15_t)0x3f8b, (q15_t)0x47b0, (q15_t)0x3f89, (q15_t)0x47bd, (q15_t)0x3f88, (q15_t)0x47c9, (q15_t)0x3f86,
+    (q15_t)0x47d6, (q15_t)0x3f85, (q15_t)0x47e2, (q15_t)0x3f83, (q15_t)0x47ef, (q15_t)0x3f82, (q15_t)0x47fb, (q15_t)0x3f80,
+    (q15_t)0x4807, (q15_t)0x3f7f, (q15_t)0x4814, (q15_t)0x3f7d, (q15_t)0x4820, (q15_t)0x3f7b, (q15_t)0x482d, (q15_t)0x3f7a,
+    (q15_t)0x4839, (q15_t)0x3f78, (q15_t)0x4846, (q15_t)0x3f77, (q15_t)0x4852, (q15_t)0x3f75, (q15_t)0x485f, (q15_t)0x3f73,
+    (q15_t)0x486b, (q15_t)0x3f72, (q15_t)0x4878, (q15_t)0x3f70, (q15_t)0x4884, (q15_t)0x3f6e, (q15_t)0x4891, (q15_t)0x3f6d,
+    (q15_t)0x489d, (q15_t)0x3f6b, (q15_t)0x48a9, (q15_t)0x3f69, (q15_t)0x48b6, (q15_t)0x3f68, (q15_t)0x48c2, (q15_t)0x3f66,
+    (q15_t)0x48cf, (q15_t)0x3f64, (q15_t)0x48db, (q15_t)0x3f62, (q15_t)0x48e8, (q15_t)0x3f61, (q15_t)0x48f4, (q15_t)0x3f5f,
+    (q15_t)0x4901, (q15_t)0x3f5d, (q15_t)0x490d, (q15_t)0x3f5b, (q15_t)0x4919, (q15_t)0x3f5a, (q15_t)0x4926, (q15_t)0x3f58,
+    (q15_t)0x4932, (q15_t)0x3f56, (q15_t)0x493f, (q15_t)0x3f54, (q15_t)0x494b, (q15_t)0x3f52, (q15_t)0x4958, (q15_t)0x3f51,
+    (q15_t)0x4964, (q15_t)0x3f4f, (q15_t)0x4970, (q15_t)0x3f4d, (q15_t)0x497d, (q15_t)0x3f4b, (q15_t)0x4989, (q15_t)0x3f49,
+    (q15_t)0x4996, (q15_t)0x3f47, (q15_t)0x49a2, (q15_t)0x3f45, (q15_t)0x49af, (q15_t)0x3f43, (q15_t)0x49bb, (q15_t)0x3f42,
+    (q15_t)0x49c7, (q15_t)0x3f40, (q15_t)0x49d4, (q15_t)0x3f3e, (q15_t)0x49e0, (q15_t)0x3f3c, (q15_t)0x49ed, (q15_t)0x3f3a,
+    (q15_t)0x49f9, (q15_t)0x3f38, (q15_t)0x4a06, (q15_t)0x3f36, (q15_t)0x4a12, (q15_t)0x3f34, (q15_t)0x4a1e, (q15_t)0x3f32,
+    (q15_t)0x4a2b, (q15_t)0x3f30, (q15_t)0x4a37, (q15_t)0x3f2e, (q15_t)0x4a44, (q15_t)0x3f2c, (q15_t)0x4a50, (q15_t)0x3f2a,
+    (q15_t)0x4a5c, (q15_t)0x3f28, (q15_t)0x4a69, (q15_t)0x3f26, (q15_t)0x4a75, (q15_t)0x3f24, (q15_t)0x4a82, (q15_t)0x3f22,
+    (q15_t)0x4a8e, (q15_t)0x3f20, (q15_t)0x4a9a, (q15_t)0x3f1e, (q15_t)0x4aa7, (q15_t)0x3f1c, (q15_t)0x4ab3, (q15_t)0x3f19,
+    (q15_t)0x4ac0, (q15_t)0x3f17, (q15_t)0x4acc, (q15_t)0x3f15, (q15_t)0x4ad8, (q15_t)0x3f13, (q15_t)0x4ae5, (q15_t)0x3f11,
+    (q15_t)0x4af1, (q15_t)0x3f0f, (q15_t)0x4afd, (q15_t)0x3f0d, (q15_t)0x4b0a, (q15_t)0x3f0a, (q15_t)0x4b16, (q15_t)0x3f08,
+    (q15_t)0x4b23, (q15_t)0x3f06, (q15_t)0x4b2f, (q15_t)0x3f04, (q15_t)0x4b3b, (q15_t)0x3f02, (q15_t)0x4b48, (q15_t)0x3f00,
+    (q15_t)0x4b54, (q15_t)0x3efd, (q15_t)0x4b60, (q15_t)0x3efb, (q15_t)0x4b6d, (q15_t)0x3ef9, (q15_t)0x4b79, (q15_t)0x3ef7,
+    (q15_t)0x4b85, (q15_t)0x3ef4, (q15_t)0x4b92, (q15_t)0x3ef2, (q15_t)0x4b9e, (q15_t)0x3ef0, (q15_t)0x4bab, (q15_t)0x3eed,
+    (q15_t)0x4bb7, (q15_t)0x3eeb, (q15_t)0x4bc3, (q15_t)0x3ee9, (q15_t)0x4bd0, (q15_t)0x3ee7, (q15_t)0x4bdc, (q15_t)0x3ee4,
+    (q15_t)0x4be8, (q15_t)0x3ee2, (q15_t)0x4bf5, (q15_t)0x3ee0, (q15_t)0x4c01, (q15_t)0x3edd, (q15_t)0x4c0d, (q15_t)0x3edb,
+    (q15_t)0x4c1a, (q15_t)0x3ed8, (q15_t)0x4c26, (q15_t)0x3ed6, (q15_t)0x4c32, (q15_t)0x3ed4, (q15_t)0x4c3f, (q15_t)0x3ed1,
+    (q15_t)0x4c4b, (q15_t)0x3ecf, (q15_t)0x4c57, (q15_t)0x3ecc, (q15_t)0x4c64, (q15_t)0x3eca, (q15_t)0x4c70, (q15_t)0x3ec8,
+    (q15_t)0x4c7c, (q15_t)0x3ec5, (q15_t)0x4c89, (q15_t)0x3ec3, (q15_t)0x4c95, (q15_t)0x3ec0, (q15_t)0x4ca1, (q15_t)0x3ebe,
+    (q15_t)0x4cae, (q15_t)0x3ebb, (q15_t)0x4cba, (q15_t)0x3eb9, (q15_t)0x4cc6, (q15_t)0x3eb6, (q15_t)0x4cd3, (q15_t)0x3eb4,
+    (q15_t)0x4cdf, (q15_t)0x3eb1, (q15_t)0x4ceb, (q15_t)0x3eaf, (q15_t)0x4cf8, (q15_t)0x3eac, (q15_t)0x4d04, (q15_t)0x3eaa,
+    (q15_t)0x4d10, (q15_t)0x3ea7, (q15_t)0x4d1c, (q15_t)0x3ea5, (q15_t)0x4d29, (q15_t)0x3ea2, (q15_t)0x4d35, (q15_t)0x3e9f,
+    (q15_t)0x4d41, (q15_t)0x3e9d, (q15_t)0x4d4e, (q15_t)0x3e9a, (q15_t)0x4d5a, (q15_t)0x3e98, (q15_t)0x4d66, (q15_t)0x3e95,
+    (q15_t)0x4d72, (q15_t)0x3e92, (q15_t)0x4d7f, (q15_t)0x3e90, (q15_t)0x4d8b, (q15_t)0x3e8d, (q15_t)0x4d97, (q15_t)0x3e8a,
+    (q15_t)0x4da4, (q15_t)0x3e88, (q15_t)0x4db0, (q15_t)0x3e85, (q15_t)0x4dbc, (q15_t)0x3e82, (q15_t)0x4dc8, (q15_t)0x3e80,
+    (q15_t)0x4dd5, (q15_t)0x3e7d, (q15_t)0x4de1, (q15_t)0x3e7a, (q15_t)0x4ded, (q15_t)0x3e77, (q15_t)0x4df9, (q15_t)0x3e75,
+    (q15_t)0x4e06, (q15_t)0x3e72, (q15_t)0x4e12, (q15_t)0x3e6f, (q15_t)0x4e1e, (q15_t)0x3e6c, (q15_t)0x4e2b, (q15_t)0x3e6a,
+    (q15_t)0x4e37, (q15_t)0x3e67, (q15_t)0x4e43, (q15_t)0x3e64, (q15_t)0x4e4f, (q15_t)0x3e61, (q15_t)0x4e5c, (q15_t)0x3e5e,
+    (q15_t)0x4e68, (q15_t)0x3e5c, (q15_t)0x4e74, (q15_t)0x3e59, (q15_t)0x4e80, (q15_t)0x3e56, (q15_t)0x4e8c, (q15_t)0x3e53,
+    (q15_t)0x4e99, (q15_t)0x3e50, (q15_t)0x4ea5, (q15_t)0x3e4d, (q15_t)0x4eb1, (q15_t)0x3e4a, (q15_t)0x4ebd, (q15_t)0x3e48,
+    (q15_t)0x4eca, (q15_t)0x3e45, (q15_t)0x4ed6, (q15_t)0x3e42, (q15_t)0x4ee2, (q15_t)0x3e3f, (q15_t)0x4eee, (q15_t)0x3e3c,
+    (q15_t)0x4efb, (q15_t)0x3e39, (q15_t)0x4f07, (q15_t)0x3e36, (q15_t)0x4f13, (q15_t)0x3e33, (q15_t)0x4f1f, (q15_t)0x3e30,
+    (q15_t)0x4f2b, (q15_t)0x3e2d, (q15_t)0x4f38, (q15_t)0x3e2a, (q15_t)0x4f44, (q15_t)0x3e27, (q15_t)0x4f50, (q15_t)0x3e24,
+    (q15_t)0x4f5c, (q15_t)0x3e21, (q15_t)0x4f68, (q15_t)0x3e1e, (q15_t)0x4f75, (q15_t)0x3e1b, (q15_t)0x4f81, (q15_t)0x3e18,
+    (q15_t)0x4f8d, (q15_t)0x3e15, (q15_t)0x4f99, (q15_t)0x3e12, (q15_t)0x4fa5, (q15_t)0x3e0f, (q15_t)0x4fb2, (q15_t)0x3e0c,
+    (q15_t)0x4fbe, (q15_t)0x3e09, (q15_t)0x4fca, (q15_t)0x3e06, (q15_t)0x4fd6, (q15_t)0x3e03, (q15_t)0x4fe2, (q15_t)0x3dff,
+    (q15_t)0x4fee, (q15_t)0x3dfc, (q15_t)0x4ffb, (q15_t)0x3df9, (q15_t)0x5007, (q15_t)0x3df6, (q15_t)0x5013, (q15_t)0x3df3,
+    (q15_t)0x501f, (q15_t)0x3df0, (q15_t)0x502b, (q15_t)0x3ded, (q15_t)0x5037, (q15_t)0x3de9, (q15_t)0x5044, (q15_t)0x3de6,
+    (q15_t)0x5050, (q15_t)0x3de3, (q15_t)0x505c, (q15_t)0x3de0, (q15_t)0x5068, (q15_t)0x3ddd, (q15_t)0x5074, (q15_t)0x3dd9,
+    (q15_t)0x5080, (q15_t)0x3dd6, (q15_t)0x508c, (q15_t)0x3dd3, (q15_t)0x5099, (q15_t)0x3dd0, (q15_t)0x50a5, (q15_t)0x3dcc,
+    (q15_t)0x50b1, (q15_t)0x3dc9, (q15_t)0x50bd, (q15_t)0x3dc6, (q15_t)0x50c9, (q15_t)0x3dc2, (q15_t)0x50d5, (q15_t)0x3dbf,
+    (q15_t)0x50e1, (q15_t)0x3dbc, (q15_t)0x50ed, (q15_t)0x3db9, (q15_t)0x50fa, (q15_t)0x3db5, (q15_t)0x5106, (q15_t)0x3db2,
+    (q15_t)0x5112, (q15_t)0x3daf, (q15_t)0x511e, (q15_t)0x3dab, (q15_t)0x512a, (q15_t)0x3da8, (q15_t)0x5136, (q15_t)0x3da4,
+    (q15_t)0x5142, (q15_t)0x3da1, (q15_t)0x514e, (q15_t)0x3d9e, (q15_t)0x515a, (q15_t)0x3d9a, (q15_t)0x5167, (q15_t)0x3d97,
+    (q15_t)0x5173, (q15_t)0x3d93, (q15_t)0x517f, (q15_t)0x3d90, (q15_t)0x518b, (q15_t)0x3d8d, (q15_t)0x5197, (q15_t)0x3d89,
+    (q15_t)0x51a3, (q15_t)0x3d86, (q15_t)0x51af, (q15_t)0x3d82, (q15_t)0x51bb, (q15_t)0x3d7f, (q15_t)0x51c7, (q15_t)0x3d7b,
+    (q15_t)0x51d3, (q15_t)0x3d78, (q15_t)0x51df, (q15_t)0x3d74, (q15_t)0x51eb, (q15_t)0x3d71, (q15_t)0x51f7, (q15_t)0x3d6d,
+    (q15_t)0x5204, (q15_t)0x3d6a, (q15_t)0x5210, (q15_t)0x3d66, (q15_t)0x521c, (q15_t)0x3d63, (q15_t)0x5228, (q15_t)0x3d5f,
+    (q15_t)0x5234, (q15_t)0x3d5b, (q15_t)0x5240, (q15_t)0x3d58, (q15_t)0x524c, (q15_t)0x3d54, (q15_t)0x5258, (q15_t)0x3d51,
+    (q15_t)0x5264, (q15_t)0x3d4d, (q15_t)0x5270, (q15_t)0x3d49, (q15_t)0x527c, (q15_t)0x3d46, (q15_t)0x5288, (q15_t)0x3d42,
+    (q15_t)0x5294, (q15_t)0x3d3f, (q15_t)0x52a0, (q15_t)0x3d3b, (q15_t)0x52ac, (q15_t)0x3d37, (q15_t)0x52b8, (q15_t)0x3d34,
+    (q15_t)0x52c4, (q15_t)0x3d30, (q15_t)0x52d0, (q15_t)0x3d2c, (q15_t)0x52dc, (q15_t)0x3d28, (q15_t)0x52e8, (q15_t)0x3d25,
+    (q15_t)0x52f4, (q15_t)0x3d21, (q15_t)0x5300, (q15_t)0x3d1d, (q15_t)0x530c, (q15_t)0x3d1a, (q15_t)0x5318, (q15_t)0x3d16,
+    (q15_t)0x5324, (q15_t)0x3d12, (q15_t)0x5330, (q15_t)0x3d0e, (q15_t)0x533c, (q15_t)0x3d0b, (q15_t)0x5348, (q15_t)0x3d07,
+    (q15_t)0x5354, (q15_t)0x3d03, (q15_t)0x5360, (q15_t)0x3cff, (q15_t)0x536c, (q15_t)0x3cfb, (q15_t)0x5378, (q15_t)0x3cf8,
+    (q15_t)0x5384, (q15_t)0x3cf4, (q15_t)0x5390, (q15_t)0x3cf0, (q15_t)0x539c, (q15_t)0x3cec, (q15_t)0x53a8, (q15_t)0x3ce8,
+    (q15_t)0x53b4, (q15_t)0x3ce4, (q15_t)0x53c0, (q15_t)0x3ce0, (q15_t)0x53cc, (q15_t)0x3cdd, (q15_t)0x53d8, (q15_t)0x3cd9,
+    (q15_t)0x53e4, (q15_t)0x3cd5, (q15_t)0x53f0, (q15_t)0x3cd1, (q15_t)0x53fb, (q15_t)0x3ccd, (q15_t)0x5407, (q15_t)0x3cc9,
+    (q15_t)0x5413, (q15_t)0x3cc5, (q15_t)0x541f, (q15_t)0x3cc1, (q15_t)0x542b, (q15_t)0x3cbd, (q15_t)0x5437, (q15_t)0x3cb9,
+    (q15_t)0x5443, (q15_t)0x3cb5, (q15_t)0x544f, (q15_t)0x3cb1, (q15_t)0x545b, (q15_t)0x3cad, (q15_t)0x5467, (q15_t)0x3ca9,
+    (q15_t)0x5473, (q15_t)0x3ca5, (q15_t)0x547f, (q15_t)0x3ca1, (q15_t)0x548b, (q15_t)0x3c9d, (q15_t)0x5496, (q15_t)0x3c99,
+    (q15_t)0x54a2, (q15_t)0x3c95, (q15_t)0x54ae, (q15_t)0x3c91, (q15_t)0x54ba, (q15_t)0x3c8d, (q15_t)0x54c6, (q15_t)0x3c89,
+    (q15_t)0x54d2, (q15_t)0x3c85, (q15_t)0x54de, (q15_t)0x3c81, (q15_t)0x54ea, (q15_t)0x3c7d, (q15_t)0x54f6, (q15_t)0x3c79,
+    (q15_t)0x5501, (q15_t)0x3c74, (q15_t)0x550d, (q15_t)0x3c70, (q15_t)0x5519, (q15_t)0x3c6c, (q15_t)0x5525, (q15_t)0x3c68,
+    (q15_t)0x5531, (q15_t)0x3c64, (q15_t)0x553d, (q15_t)0x3c60, (q15_t)0x5549, (q15_t)0x3c5b, (q15_t)0x5554, (q15_t)0x3c57,
+    (q15_t)0x5560, (q15_t)0x3c53, (q15_t)0x556c, (q15_t)0x3c4f, (q15_t)0x5578, (q15_t)0x3c4b, (q15_t)0x5584, (q15_t)0x3c46,
+    (q15_t)0x5590, (q15_t)0x3c42, (q15_t)0x559b, (q15_t)0x3c3e, (q15_t)0x55a7, (q15_t)0x3c3a, (q15_t)0x55b3, (q15_t)0x3c36,
+    (q15_t)0x55bf, (q15_t)0x3c31, (q15_t)0x55cb, (q15_t)0x3c2d, (q15_t)0x55d7, (q15_t)0x3c29, (q15_t)0x55e2, (q15_t)0x3c24,
+    (q15_t)0x55ee, (q15_t)0x3c20, (q15_t)0x55fa, (q15_t)0x3c1c, (q15_t)0x5606, (q15_t)0x3c17, (q15_t)0x5612, (q15_t)0x3c13,
+    (q15_t)0x561d, (q15_t)0x3c0f, (q15_t)0x5629, (q15_t)0x3c0a, (q15_t)0x5635, (q15_t)0x3c06, (q15_t)0x5641, (q15_t)0x3c02,
+    (q15_t)0x564c, (q15_t)0x3bfd, (q15_t)0x5658, (q15_t)0x3bf9, (q15_t)0x5664, (q15_t)0x3bf5, (q15_t)0x5670, (q15_t)0x3bf0,
+    (q15_t)0x567c, (q15_t)0x3bec, (q15_t)0x5687, (q15_t)0x3be7, (q15_t)0x5693, (q15_t)0x3be3, (q15_t)0x569f, (q15_t)0x3bde,
+    (q15_t)0x56ab, (q15_t)0x3bda, (q15_t)0x56b6, (q15_t)0x3bd6, (q15_t)0x56c2, (q15_t)0x3bd1, (q15_t)0x56ce, (q15_t)0x3bcd,
+    (q15_t)0x56da, (q15_t)0x3bc8, (q15_t)0x56e5, (q15_t)0x3bc4, (q15_t)0x56f1, (q15_t)0x3bbf, (q15_t)0x56fd, (q15_t)0x3bbb,
+    (q15_t)0x5709, (q15_t)0x3bb6, (q15_t)0x5714, (q15_t)0x3bb2, (q15_t)0x5720, (q15_t)0x3bad, (q15_t)0x572c, (q15_t)0x3ba9,
+    (q15_t)0x5737, (q15_t)0x3ba4, (q15_t)0x5743, (q15_t)0x3b9f, (q15_t)0x574f, (q15_t)0x3b9b, (q15_t)0x575b, (q15_t)0x3b96,
+    (q15_t)0x5766, (q15_t)0x3b92, (q15_t)0x5772, (q15_t)0x3b8d, (q15_t)0x577e, (q15_t)0x3b88, (q15_t)0x5789, (q15_t)0x3b84,
+    (q15_t)0x5795, (q15_t)0x3b7f, (q15_t)0x57a1, (q15_t)0x3b7b, (q15_t)0x57ac, (q15_t)0x3b76, (q15_t)0x57b8, (q15_t)0x3b71,
+    (q15_t)0x57c4, (q15_t)0x3b6d, (q15_t)0x57cf, (q15_t)0x3b68, (q15_t)0x57db, (q15_t)0x3b63, (q15_t)0x57e7, (q15_t)0x3b5f,
+    (q15_t)0x57f2, (q15_t)0x3b5a, (q15_t)0x57fe, (q15_t)0x3b55, (q15_t)0x580a, (q15_t)0x3b50, (q15_t)0x5815, (q15_t)0x3b4c,
+    (q15_t)0x5821, (q15_t)0x3b47, (q15_t)0x582d, (q15_t)0x3b42, (q15_t)0x5838, (q15_t)0x3b3e, (q15_t)0x5844, (q15_t)0x3b39,
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+    (q15_t)0x587e, (q15_t)0x3b21, (q15_t)0x5889, (q15_t)0x3b1c, (q15_t)0x5895, (q15_t)0x3b17, (q15_t)0x58a1, (q15_t)0x3b12,
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+    (q15_t)0x6699, (q15_t)0x330d, (q15_t)0x66a3, (q15_t)0x3306, (q15_t)0x66ad, (q15_t)0x32fe, (q15_t)0x66b7, (q15_t)0x32f7,
+    (q15_t)0x66c1, (q15_t)0x32ef, (q15_t)0x66cb, (q15_t)0x32e7, (q15_t)0x66d5, (q15_t)0x32e0, (q15_t)0x66df, (q15_t)0x32d8,
+    (q15_t)0x66e9, (q15_t)0x32d0, (q15_t)0x66f3, (q15_t)0x32c9, (q15_t)0x66fd, (q15_t)0x32c1, (q15_t)0x6707, (q15_t)0x32ba,
+    (q15_t)0x6711, (q15_t)0x32b2, (q15_t)0x671a, (q15_t)0x32aa, (q15_t)0x6724, (q15_t)0x32a3, (q15_t)0x672e, (q15_t)0x329b,
+    (q15_t)0x6738, (q15_t)0x3293, (q15_t)0x6742, (q15_t)0x328b, (q15_t)0x674c, (q15_t)0x3284, (q15_t)0x6756, (q15_t)0x327c,
+    (q15_t)0x6760, (q15_t)0x3274, (q15_t)0x676a, (q15_t)0x326d, (q15_t)0x6774, (q15_t)0x3265, (q15_t)0x677e, (q15_t)0x325d,
+    (q15_t)0x6788, (q15_t)0x3255, (q15_t)0x6791, (q15_t)0x324e, (q15_t)0x679b, (q15_t)0x3246, (q15_t)0x67a5, (q15_t)0x323e,
+    (q15_t)0x67af, (q15_t)0x3236, (q15_t)0x67b9, (q15_t)0x322e, (q15_t)0x67c3, (q15_t)0x3227, (q15_t)0x67cd, (q15_t)0x321f,
+    (q15_t)0x67d6, (q15_t)0x3217, (q15_t)0x67e0, (q15_t)0x320f, (q15_t)0x67ea, (q15_t)0x3207, (q15_t)0x67f4, (q15_t)0x31ff,
+    (q15_t)0x67fe, (q15_t)0x31f8, (q15_t)0x6808, (q15_t)0x31f0, (q15_t)0x6811, (q15_t)0x31e8, (q15_t)0x681b, (q15_t)0x31e0,
+    (q15_t)0x6825, (q15_t)0x31d8, (q15_t)0x682f, (q15_t)0x31d0, (q15_t)0x6838, (q15_t)0x31c8, (q15_t)0x6842, (q15_t)0x31c0,
+    (q15_t)0x684c, (q15_t)0x31b9, (q15_t)0x6856, (q15_t)0x31b1, (q15_t)0x6860, (q15_t)0x31a9, (q15_t)0x6869, (q15_t)0x31a1,
+    (q15_t)0x6873, (q15_t)0x3199, (q15_t)0x687d, (q15_t)0x3191, (q15_t)0x6886, (q15_t)0x3189, (q15_t)0x6890, (q15_t)0x3181,
+    (q15_t)0x689a, (q15_t)0x3179, (q15_t)0x68a4, (q15_t)0x3171, (q15_t)0x68ad, (q15_t)0x3169, (q15_t)0x68b7, (q15_t)0x3161,
+    (q15_t)0x68c1, (q15_t)0x3159, (q15_t)0x68ca, (q15_t)0x3151, (q15_t)0x68d4, (q15_t)0x3149, (q15_t)0x68de, (q15_t)0x3141,
+    (q15_t)0x68e7, (q15_t)0x3139, (q15_t)0x68f1, (q15_t)0x3131, (q15_t)0x68fb, (q15_t)0x3129, (q15_t)0x6904, (q15_t)0x3121,
+    (q15_t)0x690e, (q15_t)0x3119, (q15_t)0x6918, (q15_t)0x3111, (q15_t)0x6921, (q15_t)0x3109, (q15_t)0x692b, (q15_t)0x3101,
+    (q15_t)0x6935, (q15_t)0x30f9, (q15_t)0x693e, (q15_t)0x30f0, (q15_t)0x6948, (q15_t)0x30e8, (q15_t)0x6951, (q15_t)0x30e0,
+    (q15_t)0x695b, (q15_t)0x30d8, (q15_t)0x6965, (q15_t)0x30d0, (q15_t)0x696e, (q15_t)0x30c8, (q15_t)0x6978, (q15_t)0x30c0,
+    (q15_t)0x6981, (q15_t)0x30b8, (q15_t)0x698b, (q15_t)0x30af, (q15_t)0x6994, (q15_t)0x30a7, (q15_t)0x699e, (q15_t)0x309f,
+    (q15_t)0x69a7, (q15_t)0x3097, (q15_t)0x69b1, (q15_t)0x308f, (q15_t)0x69bb, (q15_t)0x3087, (q15_t)0x69c4, (q15_t)0x307e,
+    (q15_t)0x69ce, (q15_t)0x3076, (q15_t)0x69d7, (q15_t)0x306e, (q15_t)0x69e1, (q15_t)0x3066, (q15_t)0x69ea, (q15_t)0x305d,
+    (q15_t)0x69f4, (q15_t)0x3055, (q15_t)0x69fd, (q15_t)0x304d, (q15_t)0x6a07, (q15_t)0x3045, (q15_t)0x6a10, (q15_t)0x303c,
+    (q15_t)0x6a1a, (q15_t)0x3034, (q15_t)0x6a23, (q15_t)0x302c, (q15_t)0x6a2c, (q15_t)0x3024, (q15_t)0x6a36, (q15_t)0x301b,
+    (q15_t)0x6a3f, (q15_t)0x3013, (q15_t)0x6a49, (q15_t)0x300b, (q15_t)0x6a52, (q15_t)0x3002, (q15_t)0x6a5c, (q15_t)0x2ffa,
+    (q15_t)0x6a65, (q15_t)0x2ff2, (q15_t)0x6a6e, (q15_t)0x2fea, (q15_t)0x6a78, (q15_t)0x2fe1, (q15_t)0x6a81, (q15_t)0x2fd9,
+    (q15_t)0x6a8b, (q15_t)0x2fd0, (q15_t)0x6a94, (q15_t)0x2fc8, (q15_t)0x6a9d, (q15_t)0x2fc0, (q15_t)0x6aa7, (q15_t)0x2fb7,
+    (q15_t)0x6ab0, (q15_t)0x2faf, (q15_t)0x6ab9, (q15_t)0x2fa7, (q15_t)0x6ac3, (q15_t)0x2f9e, (q15_t)0x6acc, (q15_t)0x2f96,
+    (q15_t)0x6ad6, (q15_t)0x2f8d, (q15_t)0x6adf, (q15_t)0x2f85, (q15_t)0x6ae8, (q15_t)0x2f7d, (q15_t)0x6af2, (q15_t)0x2f74,
+    (q15_t)0x6afb, (q15_t)0x2f6c, (q15_t)0x6b04, (q15_t)0x2f63, (q15_t)0x6b0d, (q15_t)0x2f5b, (q15_t)0x6b17, (q15_t)0x2f52,
+    (q15_t)0x6b20, (q15_t)0x2f4a, (q15_t)0x6b29, (q15_t)0x2f41, (q15_t)0x6b33, (q15_t)0x2f39, (q15_t)0x6b3c, (q15_t)0x2f30,
+    (q15_t)0x6b45, (q15_t)0x2f28, (q15_t)0x6b4e, (q15_t)0x2f20, (q15_t)0x6b58, (q15_t)0x2f17, (q15_t)0x6b61, (q15_t)0x2f0e,
+    (q15_t)0x6b6a, (q15_t)0x2f06, (q15_t)0x6b73, (q15_t)0x2efd, (q15_t)0x6b7d, (q15_t)0x2ef5, (q15_t)0x6b86, (q15_t)0x2eec,
+    (q15_t)0x6b8f, (q15_t)0x2ee4, (q15_t)0x6b98, (q15_t)0x2edb, (q15_t)0x6ba1, (q15_t)0x2ed3, (q15_t)0x6bab, (q15_t)0x2eca,
+    (q15_t)0x6bb4, (q15_t)0x2ec2, (q15_t)0x6bbd, (q15_t)0x2eb9, (q15_t)0x6bc6, (q15_t)0x2eb0, (q15_t)0x6bcf, (q15_t)0x2ea8,
+    (q15_t)0x6bd8, (q15_t)0x2e9f, (q15_t)0x6be2, (q15_t)0x2e97, (q15_t)0x6beb, (q15_t)0x2e8e, (q15_t)0x6bf4, (q15_t)0x2e85,
+    (q15_t)0x6bfd, (q15_t)0x2e7d, (q15_t)0x6c06, (q15_t)0x2e74, (q15_t)0x6c0f, (q15_t)0x2e6b, (q15_t)0x6c18, (q15_t)0x2e63,
+    (q15_t)0x6c21, (q15_t)0x2e5a, (q15_t)0x6c2b, (q15_t)0x2e51, (q15_t)0x6c34, (q15_t)0x2e49, (q15_t)0x6c3d, (q15_t)0x2e40,
+    (q15_t)0x6c46, (q15_t)0x2e37, (q15_t)0x6c4f, (q15_t)0x2e2f, (q15_t)0x6c58, (q15_t)0x2e26, (q15_t)0x6c61, (q15_t)0x2e1d,
+    (q15_t)0x6c6a, (q15_t)0x2e15, (q15_t)0x6c73, (q15_t)0x2e0c, (q15_t)0x6c7c, (q15_t)0x2e03, (q15_t)0x6c85, (q15_t)0x2dfa,
+    (q15_t)0x6c8e, (q15_t)0x2df2, (q15_t)0x6c97, (q15_t)0x2de9, (q15_t)0x6ca0, (q15_t)0x2de0, (q15_t)0x6ca9, (q15_t)0x2dd7,
+    (q15_t)0x6cb2, (q15_t)0x2dcf, (q15_t)0x6cbb, (q15_t)0x2dc6, (q15_t)0x6cc4, (q15_t)0x2dbd, (q15_t)0x6ccd, (q15_t)0x2db4,
+    (q15_t)0x6cd6, (q15_t)0x2dab, (q15_t)0x6cdf, (q15_t)0x2da3, (q15_t)0x6ce8, (q15_t)0x2d9a, (q15_t)0x6cf1, (q15_t)0x2d91,
+    (q15_t)0x6cfa, (q15_t)0x2d88, (q15_t)0x6d03, (q15_t)0x2d7f, (q15_t)0x6d0c, (q15_t)0x2d76, (q15_t)0x6d15, (q15_t)0x2d6e,
+    (q15_t)0x6d1e, (q15_t)0x2d65, (q15_t)0x6d27, (q15_t)0x2d5c, (q15_t)0x6d2f, (q15_t)0x2d53, (q15_t)0x6d38, (q15_t)0x2d4a,
+    (q15_t)0x6d41, (q15_t)0x2d41, (q15_t)0x6d4a, (q15_t)0x2d38, (q15_t)0x6d53, (q15_t)0x2d2f, (q15_t)0x6d5c, (q15_t)0x2d27,
+    (q15_t)0x6d65, (q15_t)0x2d1e, (q15_t)0x6d6e, (q15_t)0x2d15, (q15_t)0x6d76, (q15_t)0x2d0c, (q15_t)0x6d7f, (q15_t)0x2d03,
+    (q15_t)0x6d88, (q15_t)0x2cfa, (q15_t)0x6d91, (q15_t)0x2cf1, (q15_t)0x6d9a, (q15_t)0x2ce8, (q15_t)0x6da3, (q15_t)0x2cdf,
+    (q15_t)0x6dab, (q15_t)0x2cd6, (q15_t)0x6db4, (q15_t)0x2ccd, (q15_t)0x6dbd, (q15_t)0x2cc4, (q15_t)0x6dc6, (q15_t)0x2cbb,
+    (q15_t)0x6dcf, (q15_t)0x2cb2, (q15_t)0x6dd7, (q15_t)0x2ca9, (q15_t)0x6de0, (q15_t)0x2ca0, (q15_t)0x6de9, (q15_t)0x2c97,
+    (q15_t)0x6df2, (q15_t)0x2c8e, (q15_t)0x6dfa, (q15_t)0x2c85, (q15_t)0x6e03, (q15_t)0x2c7c, (q15_t)0x6e0c, (q15_t)0x2c73,
+    (q15_t)0x6e15, (q15_t)0x2c6a, (q15_t)0x6e1d, (q15_t)0x2c61, (q15_t)0x6e26, (q15_t)0x2c58, (q15_t)0x6e2f, (q15_t)0x2c4f,
+    (q15_t)0x6e37, (q15_t)0x2c46, (q15_t)0x6e40, (q15_t)0x2c3d, (q15_t)0x6e49, (q15_t)0x2c34, (q15_t)0x6e51, (q15_t)0x2c2b,
+    (q15_t)0x6e5a, (q15_t)0x2c21, (q15_t)0x6e63, (q15_t)0x2c18, (q15_t)0x6e6b, (q15_t)0x2c0f, (q15_t)0x6e74, (q15_t)0x2c06,
+    (q15_t)0x6e7d, (q15_t)0x2bfd, (q15_t)0x6e85, (q15_t)0x2bf4, (q15_t)0x6e8e, (q15_t)0x2beb, (q15_t)0x6e97, (q15_t)0x2be2,
+    (q15_t)0x6e9f, (q15_t)0x2bd8, (q15_t)0x6ea8, (q15_t)0x2bcf, (q15_t)0x6eb0, (q15_t)0x2bc6, (q15_t)0x6eb9, (q15_t)0x2bbd,
+    (q15_t)0x6ec2, (q15_t)0x2bb4, (q15_t)0x6eca, (q15_t)0x2bab, (q15_t)0x6ed3, (q15_t)0x2ba1, (q15_t)0x6edb, (q15_t)0x2b98,
+    (q15_t)0x6ee4, (q15_t)0x2b8f, (q15_t)0x6eec, (q15_t)0x2b86, (q15_t)0x6ef5, (q15_t)0x2b7d, (q15_t)0x6efd, (q15_t)0x2b73,
+    (q15_t)0x6f06, (q15_t)0x2b6a, (q15_t)0x6f0e, (q15_t)0x2b61, (q15_t)0x6f17, (q15_t)0x2b58, (q15_t)0x6f20, (q15_t)0x2b4e,
+    (q15_t)0x6f28, (q15_t)0x2b45, (q15_t)0x6f30, (q15_t)0x2b3c, (q15_t)0x6f39, (q15_t)0x2b33, (q15_t)0x6f41, (q15_t)0x2b29,
+    (q15_t)0x6f4a, (q15_t)0x2b20, (q15_t)0x6f52, (q15_t)0x2b17, (q15_t)0x6f5b, (q15_t)0x2b0d, (q15_t)0x6f63, (q15_t)0x2b04,
+    (q15_t)0x6f6c, (q15_t)0x2afb, (q15_t)0x6f74, (q15_t)0x2af2, (q15_t)0x6f7d, (q15_t)0x2ae8, (q15_t)0x6f85, (q15_t)0x2adf,
+    (q15_t)0x6f8d, (q15_t)0x2ad6, (q15_t)0x6f96, (q15_t)0x2acc, (q15_t)0x6f9e, (q15_t)0x2ac3, (q15_t)0x6fa7, (q15_t)0x2ab9,
+    (q15_t)0x6faf, (q15_t)0x2ab0, (q15_t)0x6fb7, (q15_t)0x2aa7, (q15_t)0x6fc0, (q15_t)0x2a9d, (q15_t)0x6fc8, (q15_t)0x2a94,
+    (q15_t)0x6fd0, (q15_t)0x2a8b, (q15_t)0x6fd9, (q15_t)0x2a81, (q15_t)0x6fe1, (q15_t)0x2a78, (q15_t)0x6fea, (q15_t)0x2a6e,
+    (q15_t)0x6ff2, (q15_t)0x2a65, (q15_t)0x6ffa, (q15_t)0x2a5c, (q15_t)0x7002, (q15_t)0x2a52, (q15_t)0x700b, (q15_t)0x2a49,
+    (q15_t)0x7013, (q15_t)0x2a3f, (q15_t)0x701b, (q15_t)0x2a36, (q15_t)0x7024, (q15_t)0x2a2c, (q15_t)0x702c, (q15_t)0x2a23,
+    (q15_t)0x7034, (q15_t)0x2a1a, (q15_t)0x703c, (q15_t)0x2a10, (q15_t)0x7045, (q15_t)0x2a07, (q15_t)0x704d, (q15_t)0x29fd,
+    (q15_t)0x7055, (q15_t)0x29f4, (q15_t)0x705d, (q15_t)0x29ea, (q15_t)0x7066, (q15_t)0x29e1, (q15_t)0x706e, (q15_t)0x29d7,
+    (q15_t)0x7076, (q15_t)0x29ce, (q15_t)0x707e, (q15_t)0x29c4, (q15_t)0x7087, (q15_t)0x29bb, (q15_t)0x708f, (q15_t)0x29b1,
+    (q15_t)0x7097, (q15_t)0x29a7, (q15_t)0x709f, (q15_t)0x299e, (q15_t)0x70a7, (q15_t)0x2994, (q15_t)0x70af, (q15_t)0x298b,
+    (q15_t)0x70b8, (q15_t)0x2981, (q15_t)0x70c0, (q15_t)0x2978, (q15_t)0x70c8, (q15_t)0x296e, (q15_t)0x70d0, (q15_t)0x2965,
+    (q15_t)0x70d8, (q15_t)0x295b, (q15_t)0x70e0, (q15_t)0x2951, (q15_t)0x70e8, (q15_t)0x2948, (q15_t)0x70f0, (q15_t)0x293e,
+    (q15_t)0x70f9, (q15_t)0x2935, (q15_t)0x7101, (q15_t)0x292b, (q15_t)0x7109, (q15_t)0x2921, (q15_t)0x7111, (q15_t)0x2918,
+    (q15_t)0x7119, (q15_t)0x290e, (q15_t)0x7121, (q15_t)0x2904, (q15_t)0x7129, (q15_t)0x28fb, (q15_t)0x7131, (q15_t)0x28f1,
+    (q15_t)0x7139, (q15_t)0x28e7, (q15_t)0x7141, (q15_t)0x28de, (q15_t)0x7149, (q15_t)0x28d4, (q15_t)0x7151, (q15_t)0x28ca,
+    (q15_t)0x7159, (q15_t)0x28c1, (q15_t)0x7161, (q15_t)0x28b7, (q15_t)0x7169, (q15_t)0x28ad, (q15_t)0x7171, (q15_t)0x28a4,
+    (q15_t)0x7179, (q15_t)0x289a, (q15_t)0x7181, (q15_t)0x2890, (q15_t)0x7189, (q15_t)0x2886, (q15_t)0x7191, (q15_t)0x287d,
+    (q15_t)0x7199, (q15_t)0x2873, (q15_t)0x71a1, (q15_t)0x2869, (q15_t)0x71a9, (q15_t)0x2860, (q15_t)0x71b1, (q15_t)0x2856,
+    (q15_t)0x71b9, (q15_t)0x284c, (q15_t)0x71c0, (q15_t)0x2842, (q15_t)0x71c8, (q15_t)0x2838, (q15_t)0x71d0, (q15_t)0x282f,
+    (q15_t)0x71d8, (q15_t)0x2825, (q15_t)0x71e0, (q15_t)0x281b, (q15_t)0x71e8, (q15_t)0x2811, (q15_t)0x71f0, (q15_t)0x2808,
+    (q15_t)0x71f8, (q15_t)0x27fe, (q15_t)0x71ff, (q15_t)0x27f4, (q15_t)0x7207, (q15_t)0x27ea, (q15_t)0x720f, (q15_t)0x27e0,
+    (q15_t)0x7217, (q15_t)0x27d6, (q15_t)0x721f, (q15_t)0x27cd, (q15_t)0x7227, (q15_t)0x27c3, (q15_t)0x722e, (q15_t)0x27b9,
+    (q15_t)0x7236, (q15_t)0x27af, (q15_t)0x723e, (q15_t)0x27a5, (q15_t)0x7246, (q15_t)0x279b, (q15_t)0x724e, (q15_t)0x2791,
+    (q15_t)0x7255, (q15_t)0x2788, (q15_t)0x725d, (q15_t)0x277e, (q15_t)0x7265, (q15_t)0x2774, (q15_t)0x726d, (q15_t)0x276a,
+    (q15_t)0x7274, (q15_t)0x2760, (q15_t)0x727c, (q15_t)0x2756, (q15_t)0x7284, (q15_t)0x274c, (q15_t)0x728b, (q15_t)0x2742,
+    (q15_t)0x7293, (q15_t)0x2738, (q15_t)0x729b, (q15_t)0x272e, (q15_t)0x72a3, (q15_t)0x2724, (q15_t)0x72aa, (q15_t)0x271a,
+    (q15_t)0x72b2, (q15_t)0x2711, (q15_t)0x72ba, (q15_t)0x2707, (q15_t)0x72c1, (q15_t)0x26fd, (q15_t)0x72c9, (q15_t)0x26f3,
+    (q15_t)0x72d0, (q15_t)0x26e9, (q15_t)0x72d8, (q15_t)0x26df, (q15_t)0x72e0, (q15_t)0x26d5, (q15_t)0x72e7, (q15_t)0x26cb,
+    (q15_t)0x72ef, (q15_t)0x26c1, (q15_t)0x72f7, (q15_t)0x26b7, (q15_t)0x72fe, (q15_t)0x26ad, (q15_t)0x7306, (q15_t)0x26a3,
+    (q15_t)0x730d, (q15_t)0x2699, (q15_t)0x7315, (q15_t)0x268f, (q15_t)0x731d, (q15_t)0x2685, (q15_t)0x7324, (q15_t)0x267b,
+    (q15_t)0x732c, (q15_t)0x2671, (q15_t)0x7333, (q15_t)0x2666, (q15_t)0x733b, (q15_t)0x265c, (q15_t)0x7342, (q15_t)0x2652,
+    (q15_t)0x734a, (q15_t)0x2648, (q15_t)0x7351, (q15_t)0x263e, (q15_t)0x7359, (q15_t)0x2634, (q15_t)0x7360, (q15_t)0x262a,
+    (q15_t)0x7368, (q15_t)0x2620, (q15_t)0x736f, (q15_t)0x2616, (q15_t)0x7377, (q15_t)0x260c, (q15_t)0x737e, (q15_t)0x2602,
+    (q15_t)0x7386, (q15_t)0x25f8, (q15_t)0x738d, (q15_t)0x25ed, (q15_t)0x7395, (q15_t)0x25e3, (q15_t)0x739c, (q15_t)0x25d9,
+    (q15_t)0x73a3, (q15_t)0x25cf, (q15_t)0x73ab, (q15_t)0x25c5, (q15_t)0x73b2, (q15_t)0x25bb, (q15_t)0x73ba, (q15_t)0x25b1,
+    (q15_t)0x73c1, (q15_t)0x25a6, (q15_t)0x73c8, (q15_t)0x259c, (q15_t)0x73d0, (q15_t)0x2592, (q15_t)0x73d7, (q15_t)0x2588,
+    (q15_t)0x73df, (q15_t)0x257e, (q15_t)0x73e6, (q15_t)0x2574, (q15_t)0x73ed, (q15_t)0x2569, (q15_t)0x73f5, (q15_t)0x255f,
+    (q15_t)0x73fc, (q15_t)0x2555, (q15_t)0x7403, (q15_t)0x254b, (q15_t)0x740b, (q15_t)0x2541, (q15_t)0x7412, (q15_t)0x2536,
+    (q15_t)0x7419, (q15_t)0x252c, (q15_t)0x7420, (q15_t)0x2522, (q15_t)0x7428, (q15_t)0x2518, (q15_t)0x742f, (q15_t)0x250d,
+    (q15_t)0x7436, (q15_t)0x2503, (q15_t)0x743e, (q15_t)0x24f9, (q15_t)0x7445, (q15_t)0x24ef, (q15_t)0x744c, (q15_t)0x24e4,
+    (q15_t)0x7453, (q15_t)0x24da, (q15_t)0x745b, (q15_t)0x24d0, (q15_t)0x7462, (q15_t)0x24c5, (q15_t)0x7469, (q15_t)0x24bb,
+    (q15_t)0x7470, (q15_t)0x24b1, (q15_t)0x7477, (q15_t)0x24a7, (q15_t)0x747f, (q15_t)0x249c, (q15_t)0x7486, (q15_t)0x2492,
+    (q15_t)0x748d, (q15_t)0x2488, (q15_t)0x7494, (q15_t)0x247d, (q15_t)0x749b, (q15_t)0x2473, (q15_t)0x74a2, (q15_t)0x2469,
+    (q15_t)0x74aa, (q15_t)0x245e, (q15_t)0x74b1, (q15_t)0x2454, (q15_t)0x74b8, (q15_t)0x244a, (q15_t)0x74bf, (q15_t)0x243f,
+    (q15_t)0x74c6, (q15_t)0x2435, (q15_t)0x74cd, (q15_t)0x242b, (q15_t)0x74d4, (q15_t)0x2420, (q15_t)0x74db, (q15_t)0x2416,
+    (q15_t)0x74e2, (q15_t)0x240b, (q15_t)0x74ea, (q15_t)0x2401, (q15_t)0x74f1, (q15_t)0x23f7, (q15_t)0x74f8, (q15_t)0x23ec,
+    (q15_t)0x74ff, (q15_t)0x23e2, (q15_t)0x7506, (q15_t)0x23d7, (q15_t)0x750d, (q15_t)0x23cd, (q15_t)0x7514, (q15_t)0x23c3,
+    (q15_t)0x751b, (q15_t)0x23b8, (q15_t)0x7522, (q15_t)0x23ae, (q15_t)0x7529, (q15_t)0x23a3, (q15_t)0x7530, (q15_t)0x2399,
+    (q15_t)0x7537, (q15_t)0x238e, (q15_t)0x753e, (q15_t)0x2384, (q15_t)0x7545, (q15_t)0x237a, (q15_t)0x754c, (q15_t)0x236f,
+    (q15_t)0x7553, (q15_t)0x2365, (q15_t)0x755a, (q15_t)0x235a, (q15_t)0x7561, (q15_t)0x2350, (q15_t)0x7567, (q15_t)0x2345,
+    (q15_t)0x756e, (q15_t)0x233b, (q15_t)0x7575, (q15_t)0x2330, (q15_t)0x757c, (q15_t)0x2326, (q15_t)0x7583, (q15_t)0x231b,
+    (q15_t)0x758a, (q15_t)0x2311, (q15_t)0x7591, (q15_t)0x2306, (q15_t)0x7598, (q15_t)0x22fc, (q15_t)0x759f, (q15_t)0x22f1,
+    (q15_t)0x75a5, (q15_t)0x22e7, (q15_t)0x75ac, (q15_t)0x22dc, (q15_t)0x75b3, (q15_t)0x22d2, (q15_t)0x75ba, (q15_t)0x22c7,
+    (q15_t)0x75c1, (q15_t)0x22bc, (q15_t)0x75c8, (q15_t)0x22b2, (q15_t)0x75ce, (q15_t)0x22a7, (q15_t)0x75d5, (q15_t)0x229d,
+    (q15_t)0x75dc, (q15_t)0x2292, (q15_t)0x75e3, (q15_t)0x2288, (q15_t)0x75ea, (q15_t)0x227d, (q15_t)0x75f0, (q15_t)0x2272,
+    (q15_t)0x75f7, (q15_t)0x2268, (q15_t)0x75fe, (q15_t)0x225d, (q15_t)0x7605, (q15_t)0x2253, (q15_t)0x760b, (q15_t)0x2248,
+    (q15_t)0x7612, (q15_t)0x223d, (q15_t)0x7619, (q15_t)0x2233, (q15_t)0x7620, (q15_t)0x2228, (q15_t)0x7626, (q15_t)0x221e,
+    (q15_t)0x762d, (q15_t)0x2213, (q15_t)0x7634, (q15_t)0x2208, (q15_t)0x763a, (q15_t)0x21fe, (q15_t)0x7641, (q15_t)0x21f3,
+    (q15_t)0x7648, (q15_t)0x21e8, (q15_t)0x764e, (q15_t)0x21de, (q15_t)0x7655, (q15_t)0x21d3, (q15_t)0x765c, (q15_t)0x21c8,
+    (q15_t)0x7662, (q15_t)0x21be, (q15_t)0x7669, (q15_t)0x21b3, (q15_t)0x766f, (q15_t)0x21a8, (q15_t)0x7676, (q15_t)0x219e,
+    (q15_t)0x767d, (q15_t)0x2193, (q15_t)0x7683, (q15_t)0x2188, (q15_t)0x768a, (q15_t)0x217d, (q15_t)0x7690, (q15_t)0x2173,
+    (q15_t)0x7697, (q15_t)0x2168, (q15_t)0x769d, (q15_t)0x215d, (q15_t)0x76a4, (q15_t)0x2153, (q15_t)0x76ab, (q15_t)0x2148,
+    (q15_t)0x76b1, (q15_t)0x213d, (q15_t)0x76b8, (q15_t)0x2132, (q15_t)0x76be, (q15_t)0x2128, (q15_t)0x76c5, (q15_t)0x211d,
+    (q15_t)0x76cb, (q15_t)0x2112, (q15_t)0x76d2, (q15_t)0x2107, (q15_t)0x76d8, (q15_t)0x20fd, (q15_t)0x76df, (q15_t)0x20f2,
+    (q15_t)0x76e5, (q15_t)0x20e7, (q15_t)0x76eb, (q15_t)0x20dc, (q15_t)0x76f2, (q15_t)0x20d1, (q15_t)0x76f8, (q15_t)0x20c7,
+    (q15_t)0x76ff, (q15_t)0x20bc, (q15_t)0x7705, (q15_t)0x20b1, (q15_t)0x770c, (q15_t)0x20a6, (q15_t)0x7712, (q15_t)0x209b,
+    (q15_t)0x7718, (q15_t)0x2091, (q15_t)0x771f, (q15_t)0x2086, (q15_t)0x7725, (q15_t)0x207b, (q15_t)0x772c, (q15_t)0x2070,
+    (q15_t)0x7732, (q15_t)0x2065, (q15_t)0x7738, (q15_t)0x205b, (q15_t)0x773f, (q15_t)0x2050, (q15_t)0x7745, (q15_t)0x2045,
+    (q15_t)0x774b, (q15_t)0x203a, (q15_t)0x7752, (q15_t)0x202f, (q15_t)0x7758, (q15_t)0x2024, (q15_t)0x775e, (q15_t)0x2019,
+    (q15_t)0x7765, (q15_t)0x200f, (q15_t)0x776b, (q15_t)0x2004, (q15_t)0x7771, (q15_t)0x1ff9, (q15_t)0x7777, (q15_t)0x1fee,
+    (q15_t)0x777e, (q15_t)0x1fe3, (q15_t)0x7784, (q15_t)0x1fd8, (q15_t)0x778a, (q15_t)0x1fcd, (q15_t)0x7790, (q15_t)0x1fc2,
+    (q15_t)0x7797, (q15_t)0x1fb7, (q15_t)0x779d, (q15_t)0x1fac, (q15_t)0x77a3, (q15_t)0x1fa2, (q15_t)0x77a9, (q15_t)0x1f97,
+    (q15_t)0x77b0, (q15_t)0x1f8c, (q15_t)0x77b6, (q15_t)0x1f81, (q15_t)0x77bc, (q15_t)0x1f76, (q15_t)0x77c2, (q15_t)0x1f6b,
+    (q15_t)0x77c8, (q15_t)0x1f60, (q15_t)0x77ce, (q15_t)0x1f55, (q15_t)0x77d5, (q15_t)0x1f4a, (q15_t)0x77db, (q15_t)0x1f3f,
+    (q15_t)0x77e1, (q15_t)0x1f34, (q15_t)0x77e7, (q15_t)0x1f29, (q15_t)0x77ed, (q15_t)0x1f1e, (q15_t)0x77f3, (q15_t)0x1f13,
+    (q15_t)0x77f9, (q15_t)0x1f08, (q15_t)0x77ff, (q15_t)0x1efd, (q15_t)0x7805, (q15_t)0x1ef2, (q15_t)0x780b, (q15_t)0x1ee7,
+    (q15_t)0x7812, (q15_t)0x1edc, (q15_t)0x7818, (q15_t)0x1ed1, (q15_t)0x781e, (q15_t)0x1ec6, (q15_t)0x7824, (q15_t)0x1ebb,
+    (q15_t)0x782a, (q15_t)0x1eb0, (q15_t)0x7830, (q15_t)0x1ea5, (q15_t)0x7836, (q15_t)0x1e9a, (q15_t)0x783c, (q15_t)0x1e8f,
+    (q15_t)0x7842, (q15_t)0x1e84, (q15_t)0x7848, (q15_t)0x1e79, (q15_t)0x784e, (q15_t)0x1e6e, (q15_t)0x7854, (q15_t)0x1e63,
+    (q15_t)0x785a, (q15_t)0x1e58, (q15_t)0x7860, (q15_t)0x1e4d, (q15_t)0x7866, (q15_t)0x1e42, (q15_t)0x786b, (q15_t)0x1e36,
+    (q15_t)0x7871, (q15_t)0x1e2b, (q15_t)0x7877, (q15_t)0x1e20, (q15_t)0x787d, (q15_t)0x1e15, (q15_t)0x7883, (q15_t)0x1e0a,
+    (q15_t)0x7889, (q15_t)0x1dff, (q15_t)0x788f, (q15_t)0x1df4, (q15_t)0x7895, (q15_t)0x1de9, (q15_t)0x789b, (q15_t)0x1dde,
+    (q15_t)0x78a1, (q15_t)0x1dd3, (q15_t)0x78a6, (q15_t)0x1dc7, (q15_t)0x78ac, (q15_t)0x1dbc, (q15_t)0x78b2, (q15_t)0x1db1,
+    (q15_t)0x78b8, (q15_t)0x1da6, (q15_t)0x78be, (q15_t)0x1d9b, (q15_t)0x78c3, (q15_t)0x1d90, (q15_t)0x78c9, (q15_t)0x1d85,
+    (q15_t)0x78cf, (q15_t)0x1d79, (q15_t)0x78d5, (q15_t)0x1d6e, (q15_t)0x78db, (q15_t)0x1d63, (q15_t)0x78e0, (q15_t)0x1d58,
+    (q15_t)0x78e6, (q15_t)0x1d4d, (q15_t)0x78ec, (q15_t)0x1d42, (q15_t)0x78f2, (q15_t)0x1d36, (q15_t)0x78f7, (q15_t)0x1d2b,
+    (q15_t)0x78fd, (q15_t)0x1d20, (q15_t)0x7903, (q15_t)0x1d15, (q15_t)0x7909, (q15_t)0x1d0a, (q15_t)0x790e, (q15_t)0x1cff,
+    (q15_t)0x7914, (q15_t)0x1cf3, (q15_t)0x791a, (q15_t)0x1ce8, (q15_t)0x791f, (q15_t)0x1cdd, (q15_t)0x7925, (q15_t)0x1cd2,
+    (q15_t)0x792b, (q15_t)0x1cc6, (q15_t)0x7930, (q15_t)0x1cbb, (q15_t)0x7936, (q15_t)0x1cb0, (q15_t)0x793b, (q15_t)0x1ca5,
+    (q15_t)0x7941, (q15_t)0x1c99, (q15_t)0x7947, (q15_t)0x1c8e, (q15_t)0x794c, (q15_t)0x1c83, (q15_t)0x7952, (q15_t)0x1c78,
+    (q15_t)0x7958, (q15_t)0x1c6c, (q15_t)0x795d, (q15_t)0x1c61, (q15_t)0x7963, (q15_t)0x1c56, (q15_t)0x7968, (q15_t)0x1c4b,
+    (q15_t)0x796e, (q15_t)0x1c3f, (q15_t)0x7973, (q15_t)0x1c34, (q15_t)0x7979, (q15_t)0x1c29, (q15_t)0x797e, (q15_t)0x1c1e,
+    (q15_t)0x7984, (q15_t)0x1c12, (q15_t)0x7989, (q15_t)0x1c07, (q15_t)0x798f, (q15_t)0x1bfc, (q15_t)0x7994, (q15_t)0x1bf0,
+    (q15_t)0x799a, (q15_t)0x1be5, (q15_t)0x799f, (q15_t)0x1bda, (q15_t)0x79a5, (q15_t)0x1bce, (q15_t)0x79aa, (q15_t)0x1bc3,
+    (q15_t)0x79b0, (q15_t)0x1bb8, (q15_t)0x79b5, (q15_t)0x1bac, (q15_t)0x79bb, (q15_t)0x1ba1, (q15_t)0x79c0, (q15_t)0x1b96,
+    (q15_t)0x79c5, (q15_t)0x1b8a, (q15_t)0x79cb, (q15_t)0x1b7f, (q15_t)0x79d0, (q15_t)0x1b74, (q15_t)0x79d6, (q15_t)0x1b68,
+    (q15_t)0x79db, (q15_t)0x1b5d, (q15_t)0x79e0, (q15_t)0x1b52, (q15_t)0x79e6, (q15_t)0x1b46, (q15_t)0x79eb, (q15_t)0x1b3b,
+    (q15_t)0x79f0, (q15_t)0x1b30, (q15_t)0x79f6, (q15_t)0x1b24, (q15_t)0x79fb, (q15_t)0x1b19, (q15_t)0x7a00, (q15_t)0x1b0d,
+    (q15_t)0x7a06, (q15_t)0x1b02, (q15_t)0x7a0b, (q15_t)0x1af7, (q15_t)0x7a10, (q15_t)0x1aeb, (q15_t)0x7a16, (q15_t)0x1ae0,
+    (q15_t)0x7a1b, (q15_t)0x1ad4, (q15_t)0x7a20, (q15_t)0x1ac9, (q15_t)0x7a25, (q15_t)0x1abe, (q15_t)0x7a2b, (q15_t)0x1ab2,
+    (q15_t)0x7a30, (q15_t)0x1aa7, (q15_t)0x7a35, (q15_t)0x1a9b, (q15_t)0x7a3a, (q15_t)0x1a90, (q15_t)0x7a3f, (q15_t)0x1a84,
+    (q15_t)0x7a45, (q15_t)0x1a79, (q15_t)0x7a4a, (q15_t)0x1a6e, (q15_t)0x7a4f, (q15_t)0x1a62, (q15_t)0x7a54, (q15_t)0x1a57,
+    (q15_t)0x7a59, (q15_t)0x1a4b, (q15_t)0x7a5f, (q15_t)0x1a40, (q15_t)0x7a64, (q15_t)0x1a34, (q15_t)0x7a69, (q15_t)0x1a29,
+    (q15_t)0x7a6e, (q15_t)0x1a1d, (q15_t)0x7a73, (q15_t)0x1a12, (q15_t)0x7a78, (q15_t)0x1a06, (q15_t)0x7a7d, (q15_t)0x19fb,
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+    (q15_t)0x7ad3, (q15_t)0x1937, (q15_t)0x7ad8, (q15_t)0x192c, (q15_t)0x7add, (q15_t)0x1920, (q15_t)0x7ae2, (q15_t)0x1914,
+    (q15_t)0x7ae6, (q15_t)0x1909, (q15_t)0x7aeb, (q15_t)0x18fd, (q15_t)0x7af0, (q15_t)0x18f2, (q15_t)0x7af5, (q15_t)0x18e6,
+    (q15_t)0x7afa, (q15_t)0x18db, (q15_t)0x7aff, (q15_t)0x18cf, (q15_t)0x7b04, (q15_t)0x18c3, (q15_t)0x7b09, (q15_t)0x18b8,
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+    (q15_t)0x7b34, (q15_t)0x184f, (q15_t)0x7b39, (q15_t)0x1844, (q15_t)0x7b3e, (q15_t)0x1838, (q15_t)0x7b42, (q15_t)0x182d,
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+    (q15_t)0x7f0f, (q15_t)0xaf1, (q15_t)0x7f11, (q15_t)0xae5, (q15_t)0x7f13, (q15_t)0xad8, (q15_t)0x7f15, (q15_t)0xacc,
+    (q15_t)0x7f17, (q15_t)0xac0, (q15_t)0x7f19, (q15_t)0xab3, (q15_t)0x7f1c, (q15_t)0xaa7, (q15_t)0x7f1e, (q15_t)0xa9a,
+    (q15_t)0x7f20, (q15_t)0xa8e, (q15_t)0x7f22, (q15_t)0xa82, (q15_t)0x7f24, (q15_t)0xa75, (q15_t)0x7f26, (q15_t)0xa69,
+    (q15_t)0x7f28, (q15_t)0xa5c, (q15_t)0x7f2a, (q15_t)0xa50, (q15_t)0x7f2c, (q15_t)0xa44, (q15_t)0x7f2e, (q15_t)0xa37,
+    (q15_t)0x7f30, (q15_t)0xa2b, (q15_t)0x7f32, (q15_t)0xa1e, (q15_t)0x7f34, (q15_t)0xa12, (q15_t)0x7f36, (q15_t)0xa06,
+    (q15_t)0x7f38, (q15_t)0x9f9, (q15_t)0x7f3a, (q15_t)0x9ed, (q15_t)0x7f3c, (q15_t)0x9e0, (q15_t)0x7f3e, (q15_t)0x9d4,
+    (q15_t)0x7f40, (q15_t)0x9c7, (q15_t)0x7f42, (q15_t)0x9bb, (q15_t)0x7f43, (q15_t)0x9af, (q15_t)0x7f45, (q15_t)0x9a2,
+    (q15_t)0x7f47, (q15_t)0x996, (q15_t)0x7f49, (q15_t)0x989, (q15_t)0x7f4b, (q15_t)0x97d, (q15_t)0x7f4d, (q15_t)0x970,
+    (q15_t)0x7f4f, (q15_t)0x964, (q15_t)0x7f51, (q15_t)0x958, (q15_t)0x7f52, (q15_t)0x94b, (q15_t)0x7f54, (q15_t)0x93f,
+    (q15_t)0x7f56, (q15_t)0x932, (q15_t)0x7f58, (q15_t)0x926, (q15_t)0x7f5a, (q15_t)0x919, (q15_t)0x7f5b, (q15_t)0x90d,
+    (q15_t)0x7f5d, (q15_t)0x901, (q15_t)0x7f5f, (q15_t)0x8f4, (q15_t)0x7f61, (q15_t)0x8e8, (q15_t)0x7f62, (q15_t)0x8db,
+    (q15_t)0x7f64, (q15_t)0x8cf, (q15_t)0x7f66, (q15_t)0x8c2, (q15_t)0x7f68, (q15_t)0x8b6, (q15_t)0x7f69, (q15_t)0x8a9,
+    (q15_t)0x7f6b, (q15_t)0x89d, (q15_t)0x7f6d, (q15_t)0x891, (q15_t)0x7f6e, (q15_t)0x884, (q15_t)0x7f70, (q15_t)0x878,
+    (q15_t)0x7f72, (q15_t)0x86b, (q15_t)0x7f73, (q15_t)0x85f, (q15_t)0x7f75, (q15_t)0x852, (q15_t)0x7f77, (q15_t)0x846,
+    (q15_t)0x7f78, (q15_t)0x839, (q15_t)0x7f7a, (q15_t)0x82d, (q15_t)0x7f7b, (q15_t)0x820, (q15_t)0x7f7d, (q15_t)0x814,
+    (q15_t)0x7f7f, (q15_t)0x807, (q15_t)0x7f80, (q15_t)0x7fb, (q15_t)0x7f82, (q15_t)0x7ef, (q15_t)0x7f83, (q15_t)0x7e2,
+    (q15_t)0x7f85, (q15_t)0x7d6, (q15_t)0x7f86, (q15_t)0x7c9, (q15_t)0x7f88, (q15_t)0x7bd, (q15_t)0x7f89, (q15_t)0x7b0,
+    (q15_t)0x7f8b, (q15_t)0x7a4, (q15_t)0x7f8c, (q15_t)0x797, (q15_t)0x7f8e, (q15_t)0x78b, (q15_t)0x7f8f, (q15_t)0x77e,
+    (q15_t)0x7f91, (q15_t)0x772, (q15_t)0x7f92, (q15_t)0x765, (q15_t)0x7f94, (q15_t)0x759, (q15_t)0x7f95, (q15_t)0x74c,
+    (q15_t)0x7f97, (q15_t)0x740, (q15_t)0x7f98, (q15_t)0x733, (q15_t)0x7f99, (q15_t)0x727, (q15_t)0x7f9b, (q15_t)0x71a,
+    (q15_t)0x7f9c, (q15_t)0x70e, (q15_t)0x7f9e, (q15_t)0x701, (q15_t)0x7f9f, (q15_t)0x6f5, (q15_t)0x7fa0, (q15_t)0x6e8,
+    (q15_t)0x7fa2, (q15_t)0x6dc, (q15_t)0x7fa3, (q15_t)0x6cf, (q15_t)0x7fa4, (q15_t)0x6c3, (q15_t)0x7fa6, (q15_t)0x6b6,
+    (q15_t)0x7fa7, (q15_t)0x6aa, (q15_t)0x7fa8, (q15_t)0x69d, (q15_t)0x7faa, (q15_t)0x691, (q15_t)0x7fab, (q15_t)0x684,
+    (q15_t)0x7fac, (q15_t)0x678, (q15_t)0x7fad, (q15_t)0x66b, (q15_t)0x7faf, (q15_t)0x65f, (q15_t)0x7fb0, (q15_t)0x652,
+    (q15_t)0x7fb1, (q15_t)0x646, (q15_t)0x7fb2, (q15_t)0x639, (q15_t)0x7fb4, (q15_t)0x62d, (q15_t)0x7fb5, (q15_t)0x620,
+    (q15_t)0x7fb6, (q15_t)0x614, (q15_t)0x7fb7, (q15_t)0x607, (q15_t)0x7fb8, (q15_t)0x5fb, (q15_t)0x7fb9, (q15_t)0x5ee,
+    (q15_t)0x7fbb, (q15_t)0x5e2, (q15_t)0x7fbc, (q15_t)0x5d5, (q15_t)0x7fbd, (q15_t)0x5c9, (q15_t)0x7fbe, (q15_t)0x5bc,
+    (q15_t)0x7fbf, (q15_t)0x5b0, (q15_t)0x7fc0, (q15_t)0x5a3, (q15_t)0x7fc1, (q15_t)0x597, (q15_t)0x7fc3, (q15_t)0x58a,
+    (q15_t)0x7fc4, (q15_t)0x57e, (q15_t)0x7fc5, (q15_t)0x571, (q15_t)0x7fc6, (q15_t)0x565, (q15_t)0x7fc7, (q15_t)0x558,
+    (q15_t)0x7fc8, (q15_t)0x54c, (q15_t)0x7fc9, (q15_t)0x53f, (q15_t)0x7fca, (q15_t)0x533, (q15_t)0x7fcb, (q15_t)0x526,
+    (q15_t)0x7fcc, (q15_t)0x51a, (q15_t)0x7fcd, (q15_t)0x50d, (q15_t)0x7fce, (q15_t)0x500, (q15_t)0x7fcf, (q15_t)0x4f4,
+    (q15_t)0x7fd0, (q15_t)0x4e7, (q15_t)0x7fd1, (q15_t)0x4db, (q15_t)0x7fd2, (q15_t)0x4ce, (q15_t)0x7fd3, (q15_t)0x4c2,
+    (q15_t)0x7fd4, (q15_t)0x4b5, (q15_t)0x7fd5, (q15_t)0x4a9, (q15_t)0x7fd5, (q15_t)0x49c, (q15_t)0x7fd6, (q15_t)0x490,
+    (q15_t)0x7fd7, (q15_t)0x483, (q15_t)0x7fd8, (q15_t)0x477, (q15_t)0x7fd9, (q15_t)0x46a, (q15_t)0x7fda, (q15_t)0x45e,
+    (q15_t)0x7fdb, (q15_t)0x451, (q15_t)0x7fdc, (q15_t)0x444, (q15_t)0x7fdc, (q15_t)0x438, (q15_t)0x7fdd, (q15_t)0x42b,
+    (q15_t)0x7fde, (q15_t)0x41f, (q15_t)0x7fdf, (q15_t)0x412, (q15_t)0x7fe0, (q15_t)0x406, (q15_t)0x7fe0, (q15_t)0x3f9,
+    (q15_t)0x7fe1, (q15_t)0x3ed, (q15_t)0x7fe2, (q15_t)0x3e0, (q15_t)0x7fe3, (q15_t)0x3d4, (q15_t)0x7fe3, (q15_t)0x3c7,
+    (q15_t)0x7fe4, (q15_t)0x3bb, (q15_t)0x7fe5, (q15_t)0x3ae, (q15_t)0x7fe6, (q15_t)0x3a1, (q15_t)0x7fe6, (q15_t)0x395,
+    (q15_t)0x7fe7, (q15_t)0x388, (q15_t)0x7fe8, (q15_t)0x37c, (q15_t)0x7fe8, (q15_t)0x36f, (q15_t)0x7fe9, (q15_t)0x363,
+    (q15_t)0x7fea, (q15_t)0x356, (q15_t)0x7fea, (q15_t)0x34a, (q15_t)0x7feb, (q15_t)0x33d, (q15_t)0x7fec, (q15_t)0x330,
+    (q15_t)0x7fec, (q15_t)0x324, (q15_t)0x7fed, (q15_t)0x317, (q15_t)0x7fed, (q15_t)0x30b, (q15_t)0x7fee, (q15_t)0x2fe,
+    (q15_t)0x7fef, (q15_t)0x2f2, (q15_t)0x7fef, (q15_t)0x2e5, (q15_t)0x7ff0, (q15_t)0x2d9, (q15_t)0x7ff0, (q15_t)0x2cc,
+    (q15_t)0x7ff1, (q15_t)0x2c0, (q15_t)0x7ff1, (q15_t)0x2b3, (q15_t)0x7ff2, (q15_t)0x2a6, (q15_t)0x7ff2, (q15_t)0x29a,
+    (q15_t)0x7ff3, (q15_t)0x28d, (q15_t)0x7ff3, (q15_t)0x281, (q15_t)0x7ff4, (q15_t)0x274, (q15_t)0x7ff4, (q15_t)0x268,
+    (q15_t)0x7ff5, (q15_t)0x25b, (q15_t)0x7ff5, (q15_t)0x24e, (q15_t)0x7ff6, (q15_t)0x242, (q15_t)0x7ff6, (q15_t)0x235,
+    (q15_t)0x7ff7, (q15_t)0x229, (q15_t)0x7ff7, (q15_t)0x21c, (q15_t)0x7ff7, (q15_t)0x210, (q15_t)0x7ff8, (q15_t)0x203,
+    (q15_t)0x7ff8, (q15_t)0x1f7, (q15_t)0x7ff9, (q15_t)0x1ea, (q15_t)0x7ff9, (q15_t)0x1dd, (q15_t)0x7ff9, (q15_t)0x1d1,
+    (q15_t)0x7ffa, (q15_t)0x1c4, (q15_t)0x7ffa, (q15_t)0x1b8, (q15_t)0x7ffa, (q15_t)0x1ab, (q15_t)0x7ffb, (q15_t)0x19f,
+    (q15_t)0x7ffb, (q15_t)0x192, (q15_t)0x7ffb, (q15_t)0x186, (q15_t)0x7ffc, (q15_t)0x179, (q15_t)0x7ffc, (q15_t)0x16c,
+    (q15_t)0x7ffc, (q15_t)0x160, (q15_t)0x7ffc, (q15_t)0x153, (q15_t)0x7ffd, (q15_t)0x147, (q15_t)0x7ffd, (q15_t)0x13a,
+    (q15_t)0x7ffd, (q15_t)0x12e, (q15_t)0x7ffd, (q15_t)0x121, (q15_t)0x7ffe, (q15_t)0x114, (q15_t)0x7ffe, (q15_t)0x108,
+    (q15_t)0x7ffe, (q15_t)0xfb, (q15_t)0x7ffe, (q15_t)0xef, (q15_t)0x7ffe, (q15_t)0xe2, (q15_t)0x7fff, (q15_t)0xd6,
+    (q15_t)0x7fff, (q15_t)0xc9, (q15_t)0x7fff, (q15_t)0xbc, (q15_t)0x7fff, (q15_t)0xb0, (q15_t)0x7fff, (q15_t)0xa3,
+    (q15_t)0x7fff, (q15_t)0x97, (q15_t)0x7fff, (q15_t)0x8a, (q15_t)0x7fff, (q15_t)0x7e, (q15_t)0x7fff, (q15_t)0x71,
+    (q15_t)0x7fff, (q15_t)0x65, (q15_t)0x7fff, (q15_t)0x58, (q15_t)0x7fff, (q15_t)0x4b, (q15_t)0x7fff, (q15_t)0x3f,
+    (q15_t)0x7fff, (q15_t)0x32, (q15_t)0x7fff, (q15_t)0x26, (q15_t)0x7fff, (q15_t)0x19, (q15_t)0x7fff, (q15_t)0xd,
+    (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xfff3, (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffda,
+    (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffc1, (q15_t)0x7fff, (q15_t)0xffb5, (q15_t)0x7fff, (q15_t)0xffa8,
+    (q15_t)0x7fff, (q15_t)0xff9b, (q15_t)0x7fff, (q15_t)0xff8f, (q15_t)0x7fff, (q15_t)0xff82, (q15_t)0x7fff, (q15_t)0xff76,
+    (q15_t)0x7fff, (q15_t)0xff69, (q15_t)0x7fff, (q15_t)0xff5d, (q15_t)0x7fff, (q15_t)0xff50, (q15_t)0x7fff, (q15_t)0xff44,
+    (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff2a, (q15_t)0x7ffe, (q15_t)0xff1e, (q15_t)0x7ffe, (q15_t)0xff11,
+    (q15_t)0x7ffe, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfef8, (q15_t)0x7ffe, (q15_t)0xfeec, (q15_t)0x7ffd, (q15_t)0xfedf,
+    (q15_t)0x7ffd, (q15_t)0xfed2, (q15_t)0x7ffd, (q15_t)0xfec6, (q15_t)0x7ffd, (q15_t)0xfeb9, (q15_t)0x7ffc, (q15_t)0xfead,
+    (q15_t)0x7ffc, (q15_t)0xfea0, (q15_t)0x7ffc, (q15_t)0xfe94, (q15_t)0x7ffc, (q15_t)0xfe87, (q15_t)0x7ffb, (q15_t)0xfe7a,
+    (q15_t)0x7ffb, (q15_t)0xfe6e, (q15_t)0x7ffb, (q15_t)0xfe61, (q15_t)0x7ffa, (q15_t)0xfe55, (q15_t)0x7ffa, (q15_t)0xfe48,
+    (q15_t)0x7ffa, (q15_t)0xfe3c, (q15_t)0x7ff9, (q15_t)0xfe2f, (q15_t)0x7ff9, (q15_t)0xfe23, (q15_t)0x7ff9, (q15_t)0xfe16,
+    (q15_t)0x7ff8, (q15_t)0xfe09, (q15_t)0x7ff8, (q15_t)0xfdfd, (q15_t)0x7ff7, (q15_t)0xfdf0, (q15_t)0x7ff7, (q15_t)0xfde4,
+    (q15_t)0x7ff7, (q15_t)0xfdd7, (q15_t)0x7ff6, (q15_t)0xfdcb, (q15_t)0x7ff6, (q15_t)0xfdbe, (q15_t)0x7ff5, (q15_t)0xfdb2,
+    (q15_t)0x7ff5, (q15_t)0xfda5, (q15_t)0x7ff4, (q15_t)0xfd98, (q15_t)0x7ff4, (q15_t)0xfd8c, (q15_t)0x7ff3, (q15_t)0xfd7f,
+    (q15_t)0x7ff3, (q15_t)0xfd73, (q15_t)0x7ff2, (q15_t)0xfd66, (q15_t)0x7ff2, (q15_t)0xfd5a, (q15_t)0x7ff1, (q15_t)0xfd4d,
+    (q15_t)0x7ff1, (q15_t)0xfd40, (q15_t)0x7ff0, (q15_t)0xfd34, (q15_t)0x7ff0, (q15_t)0xfd27, (q15_t)0x7fef, (q15_t)0xfd1b,
+    (q15_t)0x7fef, (q15_t)0xfd0e, (q15_t)0x7fee, (q15_t)0xfd02, (q15_t)0x7fed, (q15_t)0xfcf5, (q15_t)0x7fed, (q15_t)0xfce9,
+    (q15_t)0x7fec, (q15_t)0xfcdc, (q15_t)0x7fec, (q15_t)0xfcd0, (q15_t)0x7feb, (q15_t)0xfcc3, (q15_t)0x7fea, (q15_t)0xfcb6,
+    (q15_t)0x7fea, (q15_t)0xfcaa, (q15_t)0x7fe9, (q15_t)0xfc9d, (q15_t)0x7fe8, (q15_t)0xfc91, (q15_t)0x7fe8, (q15_t)0xfc84,
+    (q15_t)0x7fe7, (q15_t)0xfc78, (q15_t)0x7fe6, (q15_t)0xfc6b, (q15_t)0x7fe6, (q15_t)0xfc5f, (q15_t)0x7fe5, (q15_t)0xfc52,
+    (q15_t)0x7fe4, (q15_t)0xfc45, (q15_t)0x7fe3, (q15_t)0xfc39, (q15_t)0x7fe3, (q15_t)0xfc2c, (q15_t)0x7fe2, (q15_t)0xfc20,
+    (q15_t)0x7fe1, (q15_t)0xfc13, (q15_t)0x7fe0, (q15_t)0xfc07, (q15_t)0x7fe0, (q15_t)0xfbfa, (q15_t)0x7fdf, (q15_t)0xfbee,
+    (q15_t)0x7fde, (q15_t)0xfbe1, (q15_t)0x7fdd, (q15_t)0xfbd5, (q15_t)0x7fdc, (q15_t)0xfbc8, (q15_t)0x7fdc, (q15_t)0xfbbc,
+    (q15_t)0x7fdb, (q15_t)0xfbaf, (q15_t)0x7fda, (q15_t)0xfba2, (q15_t)0x7fd9, (q15_t)0xfb96, (q15_t)0x7fd8, (q15_t)0xfb89,
+    (q15_t)0x7fd7, (q15_t)0xfb7d, (q15_t)0x7fd6, (q15_t)0xfb70, (q15_t)0x7fd5, (q15_t)0xfb64, (q15_t)0x7fd5, (q15_t)0xfb57,
+    (q15_t)0x7fd4, (q15_t)0xfb4b, (q15_t)0x7fd3, (q15_t)0xfb3e, (q15_t)0x7fd2, (q15_t)0xfb32, (q15_t)0x7fd1, (q15_t)0xfb25,
+    (q15_t)0x7fd0, (q15_t)0xfb19, (q15_t)0x7fcf, (q15_t)0xfb0c, (q15_t)0x7fce, (q15_t)0xfb00, (q15_t)0x7fcd, (q15_t)0xfaf3,
+    (q15_t)0x7fcc, (q15_t)0xfae6, (q15_t)0x7fcb, (q15_t)0xfada, (q15_t)0x7fca, (q15_t)0xfacd, (q15_t)0x7fc9, (q15_t)0xfac1,
+    (q15_t)0x7fc8, (q15_t)0xfab4, (q15_t)0x7fc7, (q15_t)0xfaa8, (q15_t)0x7fc6, (q15_t)0xfa9b, (q15_t)0x7fc5, (q15_t)0xfa8f,
+    (q15_t)0x7fc4, (q15_t)0xfa82, (q15_t)0x7fc3, (q15_t)0xfa76, (q15_t)0x7fc1, (q15_t)0xfa69, (q15_t)0x7fc0, (q15_t)0xfa5d,
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+    (q15_t)0x74e2, (q15_t)0xdbf5, (q15_t)0x74db, (q15_t)0xdbea, (q15_t)0x74d4, (q15_t)0xdbe0, (q15_t)0x74cd, (q15_t)0xdbd5,
+    (q15_t)0x74c6, (q15_t)0xdbcb, (q15_t)0x74bf, (q15_t)0xdbc1, (q15_t)0x74b8, (q15_t)0xdbb6, (q15_t)0x74b1, (q15_t)0xdbac,
+    (q15_t)0x74aa, (q15_t)0xdba2, (q15_t)0x74a2, (q15_t)0xdb97, (q15_t)0x749b, (q15_t)0xdb8d, (q15_t)0x7494, (q15_t)0xdb83,
+    (q15_t)0x748d, (q15_t)0xdb78, (q15_t)0x7486, (q15_t)0xdb6e, (q15_t)0x747f, (q15_t)0xdb64, (q15_t)0x7477, (q15_t)0xdb59,
+    (q15_t)0x7470, (q15_t)0xdb4f, (q15_t)0x7469, (q15_t)0xdb45, (q15_t)0x7462, (q15_t)0xdb3b, (q15_t)0x745b, (q15_t)0xdb30,
+    (q15_t)0x7453, (q15_t)0xdb26, (q15_t)0x744c, (q15_t)0xdb1c, (q15_t)0x7445, (q15_t)0xdb11, (q15_t)0x743e, (q15_t)0xdb07,
+    (q15_t)0x7436, (q15_t)0xdafd, (q15_t)0x742f, (q15_t)0xdaf3, (q15_t)0x7428, (q15_t)0xdae8, (q15_t)0x7420, (q15_t)0xdade,
+    (q15_t)0x7419, (q15_t)0xdad4, (q15_t)0x7412, (q15_t)0xdaca, (q15_t)0x740b, (q15_t)0xdabf, (q15_t)0x7403, (q15_t)0xdab5,
+    (q15_t)0x73fc, (q15_t)0xdaab, (q15_t)0x73f5, (q15_t)0xdaa1, (q15_t)0x73ed, (q15_t)0xda97, (q15_t)0x73e6, (q15_t)0xda8c,
+    (q15_t)0x73df, (q15_t)0xda82, (q15_t)0x73d7, (q15_t)0xda78, (q15_t)0x73d0, (q15_t)0xda6e, (q15_t)0x73c8, (q15_t)0xda64,
+    (q15_t)0x73c1, (q15_t)0xda5a, (q15_t)0x73ba, (q15_t)0xda4f, (q15_t)0x73b2, (q15_t)0xda45, (q15_t)0x73ab, (q15_t)0xda3b,
+    (q15_t)0x73a3, (q15_t)0xda31, (q15_t)0x739c, (q15_t)0xda27, (q15_t)0x7395, (q15_t)0xda1d, (q15_t)0x738d, (q15_t)0xda13,
+    (q15_t)0x7386, (q15_t)0xda08, (q15_t)0x737e, (q15_t)0xd9fe, (q15_t)0x7377, (q15_t)0xd9f4, (q15_t)0x736f, (q15_t)0xd9ea,
+    (q15_t)0x7368, (q15_t)0xd9e0, (q15_t)0x7360, (q15_t)0xd9d6, (q15_t)0x7359, (q15_t)0xd9cc, (q15_t)0x7351, (q15_t)0xd9c2,
+    (q15_t)0x734a, (q15_t)0xd9b8, (q15_t)0x7342, (q15_t)0xd9ae, (q15_t)0x733b, (q15_t)0xd9a4, (q15_t)0x7333, (q15_t)0xd99a,
+    (q15_t)0x732c, (q15_t)0xd98f, (q15_t)0x7324, (q15_t)0xd985, (q15_t)0x731d, (q15_t)0xd97b, (q15_t)0x7315, (q15_t)0xd971,
+    (q15_t)0x730d, (q15_t)0xd967, (q15_t)0x7306, (q15_t)0xd95d, (q15_t)0x72fe, (q15_t)0xd953, (q15_t)0x72f7, (q15_t)0xd949,
+    (q15_t)0x72ef, (q15_t)0xd93f, (q15_t)0x72e7, (q15_t)0xd935, (q15_t)0x72e0, (q15_t)0xd92b, (q15_t)0x72d8, (q15_t)0xd921,
+    (q15_t)0x72d0, (q15_t)0xd917, (q15_t)0x72c9, (q15_t)0xd90d, (q15_t)0x72c1, (q15_t)0xd903, (q15_t)0x72ba, (q15_t)0xd8f9,
+    (q15_t)0x72b2, (q15_t)0xd8ef, (q15_t)0x72aa, (q15_t)0xd8e6, (q15_t)0x72a3, (q15_t)0xd8dc, (q15_t)0x729b, (q15_t)0xd8d2,
+    (q15_t)0x7293, (q15_t)0xd8c8, (q15_t)0x728b, (q15_t)0xd8be, (q15_t)0x7284, (q15_t)0xd8b4, (q15_t)0x727c, (q15_t)0xd8aa,
+    (q15_t)0x7274, (q15_t)0xd8a0, (q15_t)0x726d, (q15_t)0xd896, (q15_t)0x7265, (q15_t)0xd88c, (q15_t)0x725d, (q15_t)0xd882,
+    (q15_t)0x7255, (q15_t)0xd878, (q15_t)0x724e, (q15_t)0xd86f, (q15_t)0x7246, (q15_t)0xd865, (q15_t)0x723e, (q15_t)0xd85b,
+    (q15_t)0x7236, (q15_t)0xd851, (q15_t)0x722e, (q15_t)0xd847, (q15_t)0x7227, (q15_t)0xd83d, (q15_t)0x721f, (q15_t)0xd833,
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+    (q15_t)0x71f8, (q15_t)0xd802, (q15_t)0x71f0, (q15_t)0xd7f8, (q15_t)0x71e8, (q15_t)0xd7ef, (q15_t)0x71e0, (q15_t)0xd7e5,
+    (q15_t)0x71d8, (q15_t)0xd7db, (q15_t)0x71d0, (q15_t)0xd7d1, (q15_t)0x71c8, (q15_t)0xd7c8, (q15_t)0x71c0, (q15_t)0xd7be,
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+    (q15_t)0x7119, (q15_t)0xd6f2, (q15_t)0x7111, (q15_t)0xd6e8, (q15_t)0x7109, (q15_t)0xd6df, (q15_t)0x7101, (q15_t)0xd6d5,
+    (q15_t)0x70f9, (q15_t)0xd6cb, (q15_t)0x70f0, (q15_t)0xd6c2, (q15_t)0x70e8, (q15_t)0xd6b8, (q15_t)0x70e0, (q15_t)0xd6af,
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+    (q15_t)0x6dab, (q15_t)0xd32a, (q15_t)0x6da3, (q15_t)0xd321, (q15_t)0x6d9a, (q15_t)0xd318, (q15_t)0x6d91, (q15_t)0xd30f,
+    (q15_t)0x6d88, (q15_t)0xd306, (q15_t)0x6d7f, (q15_t)0xd2fd, (q15_t)0x6d76, (q15_t)0xd2f4, (q15_t)0x6d6e, (q15_t)0xd2eb,
+    (q15_t)0x6d65, (q15_t)0xd2e2, (q15_t)0x6d5c, (q15_t)0xd2d9, (q15_t)0x6d53, (q15_t)0xd2d1, (q15_t)0x6d4a, (q15_t)0xd2c8,
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+    (q15_t)0x6cd6, (q15_t)0xd255, (q15_t)0x6ccd, (q15_t)0xd24c, (q15_t)0x6cc4, (q15_t)0xd243, (q15_t)0x6cbb, (q15_t)0xd23a,
+    (q15_t)0x6cb2, (q15_t)0xd231, (q15_t)0x6ca9, (q15_t)0xd229, (q15_t)0x6ca0, (q15_t)0xd220, (q15_t)0x6c97, (q15_t)0xd217,
+    (q15_t)0x6c8e, (q15_t)0xd20e, (q15_t)0x6c85, (q15_t)0xd206, (q15_t)0x6c7c, (q15_t)0xd1fd, (q15_t)0x6c73, (q15_t)0xd1f4,
+    (q15_t)0x6c6a, (q15_t)0xd1eb, (q15_t)0x6c61, (q15_t)0xd1e3, (q15_t)0x6c58, (q15_t)0xd1da, (q15_t)0x6c4f, (q15_t)0xd1d1,
+    (q15_t)0x6c46, (q15_t)0xd1c9, (q15_t)0x6c3d, (q15_t)0xd1c0, (q15_t)0x6c34, (q15_t)0xd1b7, (q15_t)0x6c2b, (q15_t)0xd1af,
+    (q15_t)0x6c21, (q15_t)0xd1a6, (q15_t)0x6c18, (q15_t)0xd19d, (q15_t)0x6c0f, (q15_t)0xd195, (q15_t)0x6c06, (q15_t)0xd18c,
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+    (q15_t)0x6bd8, (q15_t)0xd161, (q15_t)0x6bcf, (q15_t)0xd158, (q15_t)0x6bc6, (q15_t)0xd150, (q15_t)0x6bbd, (q15_t)0xd147,
+    (q15_t)0x6bb4, (q15_t)0xd13e, (q15_t)0x6bab, (q15_t)0xd136, (q15_t)0x6ba1, (q15_t)0xd12d, (q15_t)0x6b98, (q15_t)0xd125,
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+    (q15_t)0x6b6a, (q15_t)0xd0fa, (q15_t)0x6b61, (q15_t)0xd0f2, (q15_t)0x6b58, (q15_t)0xd0e9, (q15_t)0x6b4e, (q15_t)0xd0e0,
+    (q15_t)0x6b45, (q15_t)0xd0d8, (q15_t)0x6b3c, (q15_t)0xd0d0, (q15_t)0x6b33, (q15_t)0xd0c7, (q15_t)0x6b29, (q15_t)0xd0bf,
+    (q15_t)0x6b20, (q15_t)0xd0b6, (q15_t)0x6b17, (q15_t)0xd0ae, (q15_t)0x6b0d, (q15_t)0xd0a5, (q15_t)0x6b04, (q15_t)0xd09d,
+    (q15_t)0x6afb, (q15_t)0xd094, (q15_t)0x6af2, (q15_t)0xd08c, (q15_t)0x6ae8, (q15_t)0xd083, (q15_t)0x6adf, (q15_t)0xd07b,
+    (q15_t)0x6ad6, (q15_t)0xd073, (q15_t)0x6acc, (q15_t)0xd06a, (q15_t)0x6ac3, (q15_t)0xd062, (q15_t)0x6ab9, (q15_t)0xd059,
+    (q15_t)0x6ab0, (q15_t)0xd051, (q15_t)0x6aa7, (q15_t)0xd049, (q15_t)0x6a9d, (q15_t)0xd040, (q15_t)0x6a94, (q15_t)0xd038,
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+    (q15_t)0x6a1a, (q15_t)0xcfcc, (q15_t)0x6a10, (q15_t)0xcfc4, (q15_t)0x6a07, (q15_t)0xcfbb, (q15_t)0x69fd, (q15_t)0xcfb3,
+    (q15_t)0x69f4, (q15_t)0xcfab, (q15_t)0x69ea, (q15_t)0xcfa3, (q15_t)0x69e1, (q15_t)0xcf9a, (q15_t)0x69d7, (q15_t)0xcf92,
+    (q15_t)0x69ce, (q15_t)0xcf8a, (q15_t)0x69c4, (q15_t)0xcf82, (q15_t)0x69bb, (q15_t)0xcf79, (q15_t)0x69b1, (q15_t)0xcf71,
+    (q15_t)0x69a7, (q15_t)0xcf69, (q15_t)0x699e, (q15_t)0xcf61, (q15_t)0x6994, (q15_t)0xcf59, (q15_t)0x698b, (q15_t)0xcf51,
+    (q15_t)0x6981, (q15_t)0xcf48, (q15_t)0x6978, (q15_t)0xcf40, (q15_t)0x696e, (q15_t)0xcf38, (q15_t)0x6965, (q15_t)0xcf30,
+    (q15_t)0x695b, (q15_t)0xcf28, (q15_t)0x6951, (q15_t)0xcf20, (q15_t)0x6948, (q15_t)0xcf18, (q15_t)0x693e, (q15_t)0xcf10,
+    (q15_t)0x6935, (q15_t)0xcf07, (q15_t)0x692b, (q15_t)0xceff, (q15_t)0x6921, (q15_t)0xcef7, (q15_t)0x6918, (q15_t)0xceef,
+    (q15_t)0x690e, (q15_t)0xcee7, (q15_t)0x6904, (q15_t)0xcedf, (q15_t)0x68fb, (q15_t)0xced7, (q15_t)0x68f1, (q15_t)0xcecf,
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+    (q15_t)0x68c1, (q15_t)0xcea7, (q15_t)0x68b7, (q15_t)0xce9f, (q15_t)0x68ad, (q15_t)0xce97, (q15_t)0x68a4, (q15_t)0xce8f,
+    (q15_t)0x689a, (q15_t)0xce87, (q15_t)0x6890, (q15_t)0xce7f, (q15_t)0x6886, (q15_t)0xce77, (q15_t)0x687d, (q15_t)0xce6f,
+    (q15_t)0x6873, (q15_t)0xce67, (q15_t)0x6869, (q15_t)0xce5f, (q15_t)0x6860, (q15_t)0xce57, (q15_t)0x6856, (q15_t)0xce4f,
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+    (q15_t)0x67d6, (q15_t)0xcde9, (q15_t)0x67cd, (q15_t)0xcde1, (q15_t)0x67c3, (q15_t)0xcdd9, (q15_t)0x67b9, (q15_t)0xcdd2,
+    (q15_t)0x67af, (q15_t)0xcdca, (q15_t)0x67a5, (q15_t)0xcdc2, (q15_t)0x679b, (q15_t)0xcdba, (q15_t)0x6791, (q15_t)0xcdb2,
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+    (q15_t)0x6760, (q15_t)0xcd8c, (q15_t)0x6756, (q15_t)0xcd84, (q15_t)0x674c, (q15_t)0xcd7c, (q15_t)0x6742, (q15_t)0xcd75,
+    (q15_t)0x6738, (q15_t)0xcd6d, (q15_t)0x672e, (q15_t)0xcd65, (q15_t)0x6724, (q15_t)0xcd5d, (q15_t)0x671a, (q15_t)0xcd56,
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+    (q15_t)0x66c1, (q15_t)0xcd11, (q15_t)0x66b7, (q15_t)0xcd09, (q15_t)0x66ad, (q15_t)0xcd02, (q15_t)0x66a3, (q15_t)0xccfa,
+    (q15_t)0x6699, (q15_t)0xccf3, (q15_t)0x668f, (q15_t)0xcceb, (q15_t)0x6685, (q15_t)0xcce3, (q15_t)0x667b, (q15_t)0xccdc,
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+    (q15_t)0x6648, (q15_t)0xccb6, (q15_t)0x663e, (q15_t)0xccaf, (q15_t)0x6634, (q15_t)0xcca7, (q15_t)0x662a, (q15_t)0xcca0,
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+    (q15_t)0x65cf, (q15_t)0xcc5d, (q15_t)0x65c5, (q15_t)0xcc55, (q15_t)0x65bb, (q15_t)0xcc4e, (q15_t)0x65b1, (q15_t)0xcc46,
+    (q15_t)0x65a6, (q15_t)0xcc3f, (q15_t)0x659c, (q15_t)0xcc38, (q15_t)0x6592, (q15_t)0xcc30, (q15_t)0x6588, (q15_t)0xcc29,
+    (q15_t)0x657e, (q15_t)0xcc21, (q15_t)0x6574, (q15_t)0xcc1a, (q15_t)0x6569, (q15_t)0xcc13, (q15_t)0x655f, (q15_t)0xcc0b,
+    (q15_t)0x6555, (q15_t)0xcc04, (q15_t)0x654b, (q15_t)0xcbfd, (q15_t)0x6541, (q15_t)0xcbf5, (q15_t)0x6536, (q15_t)0xcbee,
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+    (q15_t)0x6503, (q15_t)0xcbca, (q15_t)0x64f9, (q15_t)0xcbc2, (q15_t)0x64ef, (q15_t)0xcbbb, (q15_t)0x64e4, (q15_t)0xcbb4,
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+    (q15_t)0x645e, (q15_t)0xcb56, (q15_t)0x6454, (q15_t)0xcb4f, (q15_t)0x644a, (q15_t)0xcb48, (q15_t)0x643f, (q15_t)0xcb41,
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+    (q15_t)0x60e7, (q15_t)0xc91b, (q15_t)0x60dc, (q15_t)0xc915, (q15_t)0x60d1, (q15_t)0xc90e, (q15_t)0x60c7, (q15_t)0xc908,
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+    (q15_t)0x5f60, (q15_t)0xc838, (q15_t)0x5f55, (q15_t)0xc832, (q15_t)0x5f4a, (q15_t)0xc82b, (q15_t)0x5f3f, (q15_t)0xc825,
+    (q15_t)0x5f34, (q15_t)0xc81f, (q15_t)0x5f29, (q15_t)0xc819, (q15_t)0x5f1e, (q15_t)0xc813, (q15_t)0x5f13, (q15_t)0xc80d,
+    (q15_t)0x5f08, (q15_t)0xc807, (q15_t)0x5efd, (q15_t)0xc801, (q15_t)0x5ef2, (q15_t)0xc7fb, (q15_t)0x5ee7, (q15_t)0xc7f5,
+    (q15_t)0x5edc, (q15_t)0xc7ee, (q15_t)0x5ed1, (q15_t)0xc7e8, (q15_t)0x5ec6, (q15_t)0xc7e2, (q15_t)0x5ebb, (q15_t)0xc7dc,
+    (q15_t)0x5eb0, (q15_t)0xc7d6, (q15_t)0x5ea5, (q15_t)0xc7d0, (q15_t)0x5e9a, (q15_t)0xc7ca, (q15_t)0x5e8f, (q15_t)0xc7c4,
+    (q15_t)0x5e84, (q15_t)0xc7be, (q15_t)0x5e79, (q15_t)0xc7b8, (q15_t)0x5e6e, (q15_t)0xc7b2, (q15_t)0x5e63, (q15_t)0xc7ac,
+    (q15_t)0x5e58, (q15_t)0xc7a6, (q15_t)0x5e4d, (q15_t)0xc7a0, (q15_t)0x5e42, (q15_t)0xc79a, (q15_t)0x5e36, (q15_t)0xc795,
+    (q15_t)0x5e2b, (q15_t)0xc78f, (q15_t)0x5e20, (q15_t)0xc789, (q15_t)0x5e15, (q15_t)0xc783, (q15_t)0x5e0a, (q15_t)0xc77d,
+    (q15_t)0x5dff, (q15_t)0xc777, (q15_t)0x5df4, (q15_t)0xc771, (q15_t)0x5de9, (q15_t)0xc76b, (q15_t)0x5dde, (q15_t)0xc765,
+    (q15_t)0x5dd3, (q15_t)0xc75f, (q15_t)0x5dc7, (q15_t)0xc75a, (q15_t)0x5dbc, (q15_t)0xc754, (q15_t)0x5db1, (q15_t)0xc74e,
+    (q15_t)0x5da6, (q15_t)0xc748, (q15_t)0x5d9b, (q15_t)0xc742, (q15_t)0x5d90, (q15_t)0xc73d, (q15_t)0x5d85, (q15_t)0xc737,
+    (q15_t)0x5d79, (q15_t)0xc731, (q15_t)0x5d6e, (q15_t)0xc72b, (q15_t)0x5d63, (q15_t)0xc725, (q15_t)0x5d58, (q15_t)0xc720,
+    (q15_t)0x5d4d, (q15_t)0xc71a, (q15_t)0x5d42, (q15_t)0xc714, (q15_t)0x5d36, (q15_t)0xc70e, (q15_t)0x5d2b, (q15_t)0xc709,
+    (q15_t)0x5d20, (q15_t)0xc703, (q15_t)0x5d15, (q15_t)0xc6fd, (q15_t)0x5d0a, (q15_t)0xc6f7, (q15_t)0x5cff, (q15_t)0xc6f2,
+    (q15_t)0x5cf3, (q15_t)0xc6ec, (q15_t)0x5ce8, (q15_t)0xc6e6, (q15_t)0x5cdd, (q15_t)0xc6e1, (q15_t)0x5cd2, (q15_t)0xc6db,
+    (q15_t)0x5cc6, (q15_t)0xc6d5, (q15_t)0x5cbb, (q15_t)0xc6d0, (q15_t)0x5cb0, (q15_t)0xc6ca, (q15_t)0x5ca5, (q15_t)0xc6c5,
+    (q15_t)0x5c99, (q15_t)0xc6bf, (q15_t)0x5c8e, (q15_t)0xc6b9, (q15_t)0x5c83, (q15_t)0xc6b4, (q15_t)0x5c78, (q15_t)0xc6ae,
+    (q15_t)0x5c6c, (q15_t)0xc6a8, (q15_t)0x5c61, (q15_t)0xc6a3, (q15_t)0x5c56, (q15_t)0xc69d, (q15_t)0x5c4b, (q15_t)0xc698,
+    (q15_t)0x5c3f, (q15_t)0xc692, (q15_t)0x5c34, (q15_t)0xc68d, (q15_t)0x5c29, (q15_t)0xc687, (q15_t)0x5c1e, (q15_t)0xc682,
+    (q15_t)0x5c12, (q15_t)0xc67c, (q15_t)0x5c07, (q15_t)0xc677, (q15_t)0x5bfc, (q15_t)0xc671, (q15_t)0x5bf0, (q15_t)0xc66c,
+    (q15_t)0x5be5, (q15_t)0xc666, (q15_t)0x5bda, (q15_t)0xc661, (q15_t)0x5bce, (q15_t)0xc65b, (q15_t)0x5bc3, (q15_t)0xc656,
+    (q15_t)0x5bb8, (q15_t)0xc650, (q15_t)0x5bac, (q15_t)0xc64b, (q15_t)0x5ba1, (q15_t)0xc645, (q15_t)0x5b96, (q15_t)0xc640,
+    (q15_t)0x5b8a, (q15_t)0xc63b, (q15_t)0x5b7f, (q15_t)0xc635, (q15_t)0x5b74, (q15_t)0xc630, (q15_t)0x5b68, (q15_t)0xc62a,
+    (q15_t)0x5b5d, (q15_t)0xc625, (q15_t)0x5b52, (q15_t)0xc620, (q15_t)0x5b46, (q15_t)0xc61a, (q15_t)0x5b3b, (q15_t)0xc615,
+    (q15_t)0x5b30, (q15_t)0xc610, (q15_t)0x5b24, (q15_t)0xc60a, (q15_t)0x5b19, (q15_t)0xc605, (q15_t)0x5b0d, (q15_t)0xc600,
+    (q15_t)0x5b02, (q15_t)0xc5fa, (q15_t)0x5af7, (q15_t)0xc5f5, (q15_t)0x5aeb, (q15_t)0xc5f0, (q15_t)0x5ae0, (q15_t)0xc5ea,
+    (q15_t)0x5ad4, (q15_t)0xc5e5, (q15_t)0x5ac9, (q15_t)0xc5e0, (q15_t)0x5abe, (q15_t)0xc5db, (q15_t)0x5ab2, (q15_t)0xc5d5,
+    (q15_t)0x5aa7, (q15_t)0xc5d0, (q15_t)0x5a9b, (q15_t)0xc5cb, (q15_t)0x5a90, (q15_t)0xc5c6, (q15_t)0x5a84, (q15_t)0xc5c1,
+    (q15_t)0x5a79, (q15_t)0xc5bb, (q15_t)0x5a6e, (q15_t)0xc5b6, (q15_t)0x5a62, (q15_t)0xc5b1, (q15_t)0x5a57, (q15_t)0xc5ac,
+    (q15_t)0x5a4b, (q15_t)0xc5a7, (q15_t)0x5a40, (q15_t)0xc5a1, (q15_t)0x5a34, (q15_t)0xc59c, (q15_t)0x5a29, (q15_t)0xc597,
+    (q15_t)0x5a1d, (q15_t)0xc592, (q15_t)0x5a12, (q15_t)0xc58d, (q15_t)0x5a06, (q15_t)0xc588, (q15_t)0x59fb, (q15_t)0xc583,
+    (q15_t)0x59ef, (q15_t)0xc57e, (q15_t)0x59e4, (q15_t)0xc578, (q15_t)0x59d8, (q15_t)0xc573, (q15_t)0x59cd, (q15_t)0xc56e,
+    (q15_t)0x59c1, (q15_t)0xc569, (q15_t)0x59b6, (q15_t)0xc564, (q15_t)0x59aa, (q15_t)0xc55f, (q15_t)0x599f, (q15_t)0xc55a,
+    (q15_t)0x5993, (q15_t)0xc555, (q15_t)0x5988, (q15_t)0xc550, (q15_t)0x597c, (q15_t)0xc54b, (q15_t)0x5971, (q15_t)0xc546,
+    (q15_t)0x5965, (q15_t)0xc541, (q15_t)0x595a, (q15_t)0xc53c, (q15_t)0x594e, (q15_t)0xc537, (q15_t)0x5943, (q15_t)0xc532,
+    (q15_t)0x5937, (q15_t)0xc52d, (q15_t)0x592c, (q15_t)0xc528, (q15_t)0x5920, (q15_t)0xc523, (q15_t)0x5914, (q15_t)0xc51e,
+    (q15_t)0x5909, (q15_t)0xc51a, (q15_t)0x58fd, (q15_t)0xc515, (q15_t)0x58f2, (q15_t)0xc510, (q15_t)0x58e6, (q15_t)0xc50b,
+    (q15_t)0x58db, (q15_t)0xc506, (q15_t)0x58cf, (q15_t)0xc501, (q15_t)0x58c3, (q15_t)0xc4fc, (q15_t)0x58b8, (q15_t)0xc4f7,
+    (q15_t)0x58ac, (q15_t)0xc4f2, (q15_t)0x58a1, (q15_t)0xc4ee, (q15_t)0x5895, (q15_t)0xc4e9, (q15_t)0x5889, (q15_t)0xc4e4,
+    (q15_t)0x587e, (q15_t)0xc4df, (q15_t)0x5872, (q15_t)0xc4da, (q15_t)0x5867, (q15_t)0xc4d6, (q15_t)0x585b, (q15_t)0xc4d1,
+    (q15_t)0x584f, (q15_t)0xc4cc, (q15_t)0x5844, (q15_t)0xc4c7, (q15_t)0x5838, (q15_t)0xc4c2, (q15_t)0x582d, (q15_t)0xc4be,
+    (q15_t)0x5821, (q15_t)0xc4b9, (q15_t)0x5815, (q15_t)0xc4b4, (q15_t)0x580a, (q15_t)0xc4b0, (q15_t)0x57fe, (q15_t)0xc4ab,
+    (q15_t)0x57f2, (q15_t)0xc4a6, (q15_t)0x57e7, (q15_t)0xc4a1, (q15_t)0x57db, (q15_t)0xc49d, (q15_t)0x57cf, (q15_t)0xc498,
+    (q15_t)0x57c4, (q15_t)0xc493, (q15_t)0x57b8, (q15_t)0xc48f, (q15_t)0x57ac, (q15_t)0xc48a, (q15_t)0x57a1, (q15_t)0xc485,
+    (q15_t)0x5795, (q15_t)0xc481, (q15_t)0x5789, (q15_t)0xc47c, (q15_t)0x577e, (q15_t)0xc478, (q15_t)0x5772, (q15_t)0xc473,
+    (q15_t)0x5766, (q15_t)0xc46e, (q15_t)0x575b, (q15_t)0xc46a, (q15_t)0x574f, (q15_t)0xc465, (q15_t)0x5743, (q15_t)0xc461,
+    (q15_t)0x5737, (q15_t)0xc45c, (q15_t)0x572c, (q15_t)0xc457, (q15_t)0x5720, (q15_t)0xc453, (q15_t)0x5714, (q15_t)0xc44e,
+    (q15_t)0x5709, (q15_t)0xc44a, (q15_t)0x56fd, (q15_t)0xc445, (q15_t)0x56f1, (q15_t)0xc441, (q15_t)0x56e5, (q15_t)0xc43c,
+    (q15_t)0x56da, (q15_t)0xc438, (q15_t)0x56ce, (q15_t)0xc433, (q15_t)0x56c2, (q15_t)0xc42f, (q15_t)0x56b6, (q15_t)0xc42a,
+    (q15_t)0x56ab, (q15_t)0xc426, (q15_t)0x569f, (q15_t)0xc422, (q15_t)0x5693, (q15_t)0xc41d, (q15_t)0x5687, (q15_t)0xc419,
+    (q15_t)0x567c, (q15_t)0xc414, (q15_t)0x5670, (q15_t)0xc410, (q15_t)0x5664, (q15_t)0xc40b, (q15_t)0x5658, (q15_t)0xc407,
+    (q15_t)0x564c, (q15_t)0xc403, (q15_t)0x5641, (q15_t)0xc3fe, (q15_t)0x5635, (q15_t)0xc3fa, (q15_t)0x5629, (q15_t)0xc3f6,
+    (q15_t)0x561d, (q15_t)0xc3f1, (q15_t)0x5612, (q15_t)0xc3ed, (q15_t)0x5606, (q15_t)0xc3e9, (q15_t)0x55fa, (q15_t)0xc3e4,
+    (q15_t)0x55ee, (q15_t)0xc3e0, (q15_t)0x55e2, (q15_t)0xc3dc, (q15_t)0x55d7, (q15_t)0xc3d7, (q15_t)0x55cb, (q15_t)0xc3d3,
+    (q15_t)0x55bf, (q15_t)0xc3cf, (q15_t)0x55b3, (q15_t)0xc3ca, (q15_t)0x55a7, (q15_t)0xc3c6, (q15_t)0x559b, (q15_t)0xc3c2,
+    (q15_t)0x5590, (q15_t)0xc3be, (q15_t)0x5584, (q15_t)0xc3ba, (q15_t)0x5578, (q15_t)0xc3b5, (q15_t)0x556c, (q15_t)0xc3b1,
+    (q15_t)0x5560, (q15_t)0xc3ad, (q15_t)0x5554, (q15_t)0xc3a9, (q15_t)0x5549, (q15_t)0xc3a5, (q15_t)0x553d, (q15_t)0xc3a0,
+    (q15_t)0x5531, (q15_t)0xc39c, (q15_t)0x5525, (q15_t)0xc398, (q15_t)0x5519, (q15_t)0xc394, (q15_t)0x550d, (q15_t)0xc390,
+    (q15_t)0x5501, (q15_t)0xc38c, (q15_t)0x54f6, (q15_t)0xc387, (q15_t)0x54ea, (q15_t)0xc383, (q15_t)0x54de, (q15_t)0xc37f,
+    (q15_t)0x54d2, (q15_t)0xc37b, (q15_t)0x54c6, (q15_t)0xc377, (q15_t)0x54ba, (q15_t)0xc373, (q15_t)0x54ae, (q15_t)0xc36f,
+    (q15_t)0x54a2, (q15_t)0xc36b, (q15_t)0x5496, (q15_t)0xc367, (q15_t)0x548b, (q15_t)0xc363, (q15_t)0x547f, (q15_t)0xc35f,
+    (q15_t)0x5473, (q15_t)0xc35b, (q15_t)0x5467, (q15_t)0xc357, (q15_t)0x545b, (q15_t)0xc353, (q15_t)0x544f, (q15_t)0xc34f,
+    (q15_t)0x5443, (q15_t)0xc34b, (q15_t)0x5437, (q15_t)0xc347, (q15_t)0x542b, (q15_t)0xc343, (q15_t)0x541f, (q15_t)0xc33f,
+    (q15_t)0x5413, (q15_t)0xc33b, (q15_t)0x5407, (q15_t)0xc337, (q15_t)0x53fb, (q15_t)0xc333, (q15_t)0x53f0, (q15_t)0xc32f,
+    (q15_t)0x53e4, (q15_t)0xc32b, (q15_t)0x53d8, (q15_t)0xc327, (q15_t)0x53cc, (q15_t)0xc323, (q15_t)0x53c0, (q15_t)0xc320,
+    (q15_t)0x53b4, (q15_t)0xc31c, (q15_t)0x53a8, (q15_t)0xc318, (q15_t)0x539c, (q15_t)0xc314, (q15_t)0x5390, (q15_t)0xc310,
+    (q15_t)0x5384, (q15_t)0xc30c, (q15_t)0x5378, (q15_t)0xc308, (q15_t)0x536c, (q15_t)0xc305, (q15_t)0x5360, (q15_t)0xc301,
+    (q15_t)0x5354, (q15_t)0xc2fd, (q15_t)0x5348, (q15_t)0xc2f9, (q15_t)0x533c, (q15_t)0xc2f5, (q15_t)0x5330, (q15_t)0xc2f2,
+    (q15_t)0x5324, (q15_t)0xc2ee, (q15_t)0x5318, (q15_t)0xc2ea, (q15_t)0x530c, (q15_t)0xc2e6, (q15_t)0x5300, (q15_t)0xc2e3,
+    (q15_t)0x52f4, (q15_t)0xc2df, (q15_t)0x52e8, (q15_t)0xc2db, (q15_t)0x52dc, (q15_t)0xc2d8, (q15_t)0x52d0, (q15_t)0xc2d4,
+    (q15_t)0x52c4, (q15_t)0xc2d0, (q15_t)0x52b8, (q15_t)0xc2cc, (q15_t)0x52ac, (q15_t)0xc2c9, (q15_t)0x52a0, (q15_t)0xc2c5,
+    (q15_t)0x5294, (q15_t)0xc2c1, (q15_t)0x5288, (q15_t)0xc2be, (q15_t)0x527c, (q15_t)0xc2ba, (q15_t)0x5270, (q15_t)0xc2b7,
+    (q15_t)0x5264, (q15_t)0xc2b3, (q15_t)0x5258, (q15_t)0xc2af, (q15_t)0x524c, (q15_t)0xc2ac, (q15_t)0x5240, (q15_t)0xc2a8,
+    (q15_t)0x5234, (q15_t)0xc2a5, (q15_t)0x5228, (q15_t)0xc2a1, (q15_t)0x521c, (q15_t)0xc29d, (q15_t)0x5210, (q15_t)0xc29a,
+    (q15_t)0x5204, (q15_t)0xc296, (q15_t)0x51f7, (q15_t)0xc293, (q15_t)0x51eb, (q15_t)0xc28f, (q15_t)0x51df, (q15_t)0xc28c,
+    (q15_t)0x51d3, (q15_t)0xc288, (q15_t)0x51c7, (q15_t)0xc285, (q15_t)0x51bb, (q15_t)0xc281, (q15_t)0x51af, (q15_t)0xc27e,
+    (q15_t)0x51a3, (q15_t)0xc27a, (q15_t)0x5197, (q15_t)0xc277, (q15_t)0x518b, (q15_t)0xc273, (q15_t)0x517f, (q15_t)0xc270,
+    (q15_t)0x5173, (q15_t)0xc26d, (q15_t)0x5167, (q15_t)0xc269, (q15_t)0x515a, (q15_t)0xc266, (q15_t)0x514e, (q15_t)0xc262,
+    (q15_t)0x5142, (q15_t)0xc25f, (q15_t)0x5136, (q15_t)0xc25c, (q15_t)0x512a, (q15_t)0xc258, (q15_t)0x511e, (q15_t)0xc255,
+    (q15_t)0x5112, (q15_t)0xc251, (q15_t)0x5106, (q15_t)0xc24e, (q15_t)0x50fa, (q15_t)0xc24b, (q15_t)0x50ed, (q15_t)0xc247,
+    (q15_t)0x50e1, (q15_t)0xc244, (q15_t)0x50d5, (q15_t)0xc241, (q15_t)0x50c9, (q15_t)0xc23e, (q15_t)0x50bd, (q15_t)0xc23a,
+    (q15_t)0x50b1, (q15_t)0xc237, (q15_t)0x50a5, (q15_t)0xc234, (q15_t)0x5099, (q15_t)0xc230, (q15_t)0x508c, (q15_t)0xc22d,
+    (q15_t)0x5080, (q15_t)0xc22a, (q15_t)0x5074, (q15_t)0xc227, (q15_t)0x5068, (q15_t)0xc223, (q15_t)0x505c, (q15_t)0xc220,
+    (q15_t)0x5050, (q15_t)0xc21d, (q15_t)0x5044, (q15_t)0xc21a, (q15_t)0x5037, (q15_t)0xc217, (q15_t)0x502b, (q15_t)0xc213,
+    (q15_t)0x501f, (q15_t)0xc210, (q15_t)0x5013, (q15_t)0xc20d, (q15_t)0x5007, (q15_t)0xc20a, (q15_t)0x4ffb, (q15_t)0xc207,
+    (q15_t)0x4fee, (q15_t)0xc204, (q15_t)0x4fe2, (q15_t)0xc201, (q15_t)0x4fd6, (q15_t)0xc1fd, (q15_t)0x4fca, (q15_t)0xc1fa,
+    (q15_t)0x4fbe, (q15_t)0xc1f7, (q15_t)0x4fb2, (q15_t)0xc1f4, (q15_t)0x4fa5, (q15_t)0xc1f1, (q15_t)0x4f99, (q15_t)0xc1ee,
+    (q15_t)0x4f8d, (q15_t)0xc1eb, (q15_t)0x4f81, (q15_t)0xc1e8, (q15_t)0x4f75, (q15_t)0xc1e5, (q15_t)0x4f68, (q15_t)0xc1e2,
+    (q15_t)0x4f5c, (q15_t)0xc1df, (q15_t)0x4f50, (q15_t)0xc1dc, (q15_t)0x4f44, (q15_t)0xc1d9, (q15_t)0x4f38, (q15_t)0xc1d6,
+    (q15_t)0x4f2b, (q15_t)0xc1d3, (q15_t)0x4f1f, (q15_t)0xc1d0, (q15_t)0x4f13, (q15_t)0xc1cd, (q15_t)0x4f07, (q15_t)0xc1ca,
+    (q15_t)0x4efb, (q15_t)0xc1c7, (q15_t)0x4eee, (q15_t)0xc1c4, (q15_t)0x4ee2, (q15_t)0xc1c1, (q15_t)0x4ed6, (q15_t)0xc1be,
+    (q15_t)0x4eca, (q15_t)0xc1bb, (q15_t)0x4ebd, (q15_t)0xc1b8, (q15_t)0x4eb1, (q15_t)0xc1b6, (q15_t)0x4ea5, (q15_t)0xc1b3,
+    (q15_t)0x4e99, (q15_t)0xc1b0, (q15_t)0x4e8c, (q15_t)0xc1ad, (q15_t)0x4e80, (q15_t)0xc1aa, (q15_t)0x4e74, (q15_t)0xc1a7,
+    (q15_t)0x4e68, (q15_t)0xc1a4, (q15_t)0x4e5c, (q15_t)0xc1a2, (q15_t)0x4e4f, (q15_t)0xc19f, (q15_t)0x4e43, (q15_t)0xc19c,
+    (q15_t)0x4e37, (q15_t)0xc199, (q15_t)0x4e2b, (q15_t)0xc196, (q15_t)0x4e1e, (q15_t)0xc194, (q15_t)0x4e12, (q15_t)0xc191,
+    (q15_t)0x4e06, (q15_t)0xc18e, (q15_t)0x4df9, (q15_t)0xc18b, (q15_t)0x4ded, (q15_t)0xc189, (q15_t)0x4de1, (q15_t)0xc186,
+    (q15_t)0x4dd5, (q15_t)0xc183, (q15_t)0x4dc8, (q15_t)0xc180, (q15_t)0x4dbc, (q15_t)0xc17e, (q15_t)0x4db0, (q15_t)0xc17b,
+    (q15_t)0x4da4, (q15_t)0xc178, (q15_t)0x4d97, (q15_t)0xc176, (q15_t)0x4d8b, (q15_t)0xc173, (q15_t)0x4d7f, (q15_t)0xc170,
+    (q15_t)0x4d72, (q15_t)0xc16e, (q15_t)0x4d66, (q15_t)0xc16b, (q15_t)0x4d5a, (q15_t)0xc168, (q15_t)0x4d4e, (q15_t)0xc166,
+    (q15_t)0x4d41, (q15_t)0xc163, (q15_t)0x4d35, (q15_t)0xc161, (q15_t)0x4d29, (q15_t)0xc15e, (q15_t)0x4d1c, (q15_t)0xc15b,
+    (q15_t)0x4d10, (q15_t)0xc159, (q15_t)0x4d04, (q15_t)0xc156, (q15_t)0x4cf8, (q15_t)0xc154, (q15_t)0x4ceb, (q15_t)0xc151,
+    (q15_t)0x4cdf, (q15_t)0xc14f, (q15_t)0x4cd3, (q15_t)0xc14c, (q15_t)0x4cc6, (q15_t)0xc14a, (q15_t)0x4cba, (q15_t)0xc147,
+    (q15_t)0x4cae, (q15_t)0xc145, (q15_t)0x4ca1, (q15_t)0xc142, (q15_t)0x4c95, (q15_t)0xc140, (q15_t)0x4c89, (q15_t)0xc13d,
+    (q15_t)0x4c7c, (q15_t)0xc13b, (q15_t)0x4c70, (q15_t)0xc138, (q15_t)0x4c64, (q15_t)0xc136, (q15_t)0x4c57, (q15_t)0xc134,
+    (q15_t)0x4c4b, (q15_t)0xc131, (q15_t)0x4c3f, (q15_t)0xc12f, (q15_t)0x4c32, (q15_t)0xc12c, (q15_t)0x4c26, (q15_t)0xc12a,
+    (q15_t)0x4c1a, (q15_t)0xc128, (q15_t)0x4c0d, (q15_t)0xc125, (q15_t)0x4c01, (q15_t)0xc123, (q15_t)0x4bf5, (q15_t)0xc120,
+    (q15_t)0x4be8, (q15_t)0xc11e, (q15_t)0x4bdc, (q15_t)0xc11c, (q15_t)0x4bd0, (q15_t)0xc119, (q15_t)0x4bc3, (q15_t)0xc117,
+    (q15_t)0x4bb7, (q15_t)0xc115, (q15_t)0x4bab, (q15_t)0xc113, (q15_t)0x4b9e, (q15_t)0xc110, (q15_t)0x4b92, (q15_t)0xc10e,
+    (q15_t)0x4b85, (q15_t)0xc10c, (q15_t)0x4b79, (q15_t)0xc109, (q15_t)0x4b6d, (q15_t)0xc107, (q15_t)0x4b60, (q15_t)0xc105,
+    (q15_t)0x4b54, (q15_t)0xc103, (q15_t)0x4b48, (q15_t)0xc100, (q15_t)0x4b3b, (q15_t)0xc0fe, (q15_t)0x4b2f, (q15_t)0xc0fc,
+    (q15_t)0x4b23, (q15_t)0xc0fa, (q15_t)0x4b16, (q15_t)0xc0f8, (q15_t)0x4b0a, (q15_t)0xc0f6, (q15_t)0x4afd, (q15_t)0xc0f3,
+    (q15_t)0x4af1, (q15_t)0xc0f1, (q15_t)0x4ae5, (q15_t)0xc0ef, (q15_t)0x4ad8, (q15_t)0xc0ed, (q15_t)0x4acc, (q15_t)0xc0eb,
+    (q15_t)0x4ac0, (q15_t)0xc0e9, (q15_t)0x4ab3, (q15_t)0xc0e7, (q15_t)0x4aa7, (q15_t)0xc0e4, (q15_t)0x4a9a, (q15_t)0xc0e2,
+    (q15_t)0x4a8e, (q15_t)0xc0e0, (q15_t)0x4a82, (q15_t)0xc0de, (q15_t)0x4a75, (q15_t)0xc0dc, (q15_t)0x4a69, (q15_t)0xc0da,
+    (q15_t)0x4a5c, (q15_t)0xc0d8, (q15_t)0x4a50, (q15_t)0xc0d6, (q15_t)0x4a44, (q15_t)0xc0d4, (q15_t)0x4a37, (q15_t)0xc0d2,
+    (q15_t)0x4a2b, (q15_t)0xc0d0, (q15_t)0x4a1e, (q15_t)0xc0ce, (q15_t)0x4a12, (q15_t)0xc0cc, (q15_t)0x4a06, (q15_t)0xc0ca,
+    (q15_t)0x49f9, (q15_t)0xc0c8, (q15_t)0x49ed, (q15_t)0xc0c6, (q15_t)0x49e0, (q15_t)0xc0c4, (q15_t)0x49d4, (q15_t)0xc0c2,
+    (q15_t)0x49c7, (q15_t)0xc0c0, (q15_t)0x49bb, (q15_t)0xc0be, (q15_t)0x49af, (q15_t)0xc0bd, (q15_t)0x49a2, (q15_t)0xc0bb,
+    (q15_t)0x4996, (q15_t)0xc0b9, (q15_t)0x4989, (q15_t)0xc0b7, (q15_t)0x497d, (q15_t)0xc0b5, (q15_t)0x4970, (q15_t)0xc0b3,
+    (q15_t)0x4964, (q15_t)0xc0b1, (q15_t)0x4958, (q15_t)0xc0af, (q15_t)0x494b, (q15_t)0xc0ae, (q15_t)0x493f, (q15_t)0xc0ac,
+    (q15_t)0x4932, (q15_t)0xc0aa, (q15_t)0x4926, (q15_t)0xc0a8, (q15_t)0x4919, (q15_t)0xc0a6, (q15_t)0x490d, (q15_t)0xc0a5,
+    (q15_t)0x4901, (q15_t)0xc0a3, (q15_t)0x48f4, (q15_t)0xc0a1, (q15_t)0x48e8, (q15_t)0xc09f, (q15_t)0x48db, (q15_t)0xc09e,
+    (q15_t)0x48cf, (q15_t)0xc09c, (q15_t)0x48c2, (q15_t)0xc09a, (q15_t)0x48b6, (q15_t)0xc098, (q15_t)0x48a9, (q15_t)0xc097,
+    (q15_t)0x489d, (q15_t)0xc095, (q15_t)0x4891, (q15_t)0xc093, (q15_t)0x4884, (q15_t)0xc092, (q15_t)0x4878, (q15_t)0xc090,
+    (q15_t)0x486b, (q15_t)0xc08e, (q15_t)0x485f, (q15_t)0xc08d, (q15_t)0x4852, (q15_t)0xc08b, (q15_t)0x4846, (q15_t)0xc089,
+    (q15_t)0x4839, (q15_t)0xc088, (q15_t)0x482d, (q15_t)0xc086, (q15_t)0x4820, (q15_t)0xc085, (q15_t)0x4814, (q15_t)0xc083,
+    (q15_t)0x4807, (q15_t)0xc081, (q15_t)0x47fb, (q15_t)0xc080, (q15_t)0x47ef, (q15_t)0xc07e, (q15_t)0x47e2, (q15_t)0xc07d,
+    (q15_t)0x47d6, (q15_t)0xc07b, (q15_t)0x47c9, (q15_t)0xc07a, (q15_t)0x47bd, (q15_t)0xc078, (q15_t)0x47b0, (q15_t)0xc077,
+    (q15_t)0x47a4, (q15_t)0xc075, (q15_t)0x4797, (q15_t)0xc074, (q15_t)0x478b, (q15_t)0xc072, (q15_t)0x477e, (q15_t)0xc071,
+    (q15_t)0x4772, (q15_t)0xc06f, (q15_t)0x4765, (q15_t)0xc06e, (q15_t)0x4759, (q15_t)0xc06c, (q15_t)0x474c, (q15_t)0xc06b,
+    (q15_t)0x4740, (q15_t)0xc069, (q15_t)0x4733, (q15_t)0xc068, (q15_t)0x4727, (q15_t)0xc067, (q15_t)0x471a, (q15_t)0xc065,
+    (q15_t)0x470e, (q15_t)0xc064, (q15_t)0x4701, (q15_t)0xc062, (q15_t)0x46f5, (q15_t)0xc061, (q15_t)0x46e8, (q15_t)0xc060,
+    (q15_t)0x46dc, (q15_t)0xc05e, (q15_t)0x46cf, (q15_t)0xc05d, (q15_t)0x46c3, (q15_t)0xc05c, (q15_t)0x46b6, (q15_t)0xc05a,
+    (q15_t)0x46aa, (q15_t)0xc059, (q15_t)0x469d, (q15_t)0xc058, (q15_t)0x4691, (q15_t)0xc056, (q15_t)0x4684, (q15_t)0xc055,
+    (q15_t)0x4678, (q15_t)0xc054, (q15_t)0x466b, (q15_t)0xc053, (q15_t)0x465f, (q15_t)0xc051, (q15_t)0x4652, (q15_t)0xc050,
+    (q15_t)0x4646, (q15_t)0xc04f, (q15_t)0x4639, (q15_t)0xc04e, (q15_t)0x462d, (q15_t)0xc04c, (q15_t)0x4620, (q15_t)0xc04b,
+    (q15_t)0x4614, (q15_t)0xc04a, (q15_t)0x4607, (q15_t)0xc049, (q15_t)0x45fb, (q15_t)0xc048, (q15_t)0x45ee, (q15_t)0xc047,
+    (q15_t)0x45e2, (q15_t)0xc045, (q15_t)0x45d5, (q15_t)0xc044, (q15_t)0x45c9, (q15_t)0xc043, (q15_t)0x45bc, (q15_t)0xc042,
+    (q15_t)0x45b0, (q15_t)0xc041, (q15_t)0x45a3, (q15_t)0xc040, (q15_t)0x4597, (q15_t)0xc03f, (q15_t)0x458a, (q15_t)0xc03d,
+    (q15_t)0x457e, (q15_t)0xc03c, (q15_t)0x4571, (q15_t)0xc03b, (q15_t)0x4565, (q15_t)0xc03a, (q15_t)0x4558, (q15_t)0xc039,
+    (q15_t)0x454c, (q15_t)0xc038, (q15_t)0x453f, (q15_t)0xc037, (q15_t)0x4533, (q15_t)0xc036, (q15_t)0x4526, (q15_t)0xc035,
+    (q15_t)0x451a, (q15_t)0xc034, (q15_t)0x450d, (q15_t)0xc033, (q15_t)0x4500, (q15_t)0xc032, (q15_t)0x44f4, (q15_t)0xc031,
+    (q15_t)0x44e7, (q15_t)0xc030, (q15_t)0x44db, (q15_t)0xc02f, (q15_t)0x44ce, (q15_t)0xc02e, (q15_t)0x44c2, (q15_t)0xc02d,
+    (q15_t)0x44b5, (q15_t)0xc02c, (q15_t)0x44a9, (q15_t)0xc02b, (q15_t)0x449c, (q15_t)0xc02b, (q15_t)0x4490, (q15_t)0xc02a,
+    (q15_t)0x4483, (q15_t)0xc029, (q15_t)0x4477, (q15_t)0xc028, (q15_t)0x446a, (q15_t)0xc027, (q15_t)0x445e, (q15_t)0xc026,
+    (q15_t)0x4451, (q15_t)0xc025, (q15_t)0x4444, (q15_t)0xc024, (q15_t)0x4438, (q15_t)0xc024, (q15_t)0x442b, (q15_t)0xc023,
+    (q15_t)0x441f, (q15_t)0xc022, (q15_t)0x4412, (q15_t)0xc021, (q15_t)0x4406, (q15_t)0xc020, (q15_t)0x43f9, (q15_t)0xc020,
+    (q15_t)0x43ed, (q15_t)0xc01f, (q15_t)0x43e0, (q15_t)0xc01e, (q15_t)0x43d4, (q15_t)0xc01d, (q15_t)0x43c7, (q15_t)0xc01d,
+    (q15_t)0x43bb, (q15_t)0xc01c, (q15_t)0x43ae, (q15_t)0xc01b, (q15_t)0x43a1, (q15_t)0xc01a, (q15_t)0x4395, (q15_t)0xc01a,
+    (q15_t)0x4388, (q15_t)0xc019, (q15_t)0x437c, (q15_t)0xc018, (q15_t)0x436f, (q15_t)0xc018, (q15_t)0x4363, (q15_t)0xc017,
+    (q15_t)0x4356, (q15_t)0xc016, (q15_t)0x434a, (q15_t)0xc016, (q15_t)0x433d, (q15_t)0xc015, (q15_t)0x4330, (q15_t)0xc014,
+    (q15_t)0x4324, (q15_t)0xc014, (q15_t)0x4317, (q15_t)0xc013, (q15_t)0x430b, (q15_t)0xc013, (q15_t)0x42fe, (q15_t)0xc012,
+    (q15_t)0x42f2, (q15_t)0xc011, (q15_t)0x42e5, (q15_t)0xc011, (q15_t)0x42d9, (q15_t)0xc010, (q15_t)0x42cc, (q15_t)0xc010,
+    (q15_t)0x42c0, (q15_t)0xc00f, (q15_t)0x42b3, (q15_t)0xc00f, (q15_t)0x42a6, (q15_t)0xc00e, (q15_t)0x429a, (q15_t)0xc00e,
+    (q15_t)0x428d, (q15_t)0xc00d, (q15_t)0x4281, (q15_t)0xc00d, (q15_t)0x4274, (q15_t)0xc00c, (q15_t)0x4268, (q15_t)0xc00c,
+    (q15_t)0x425b, (q15_t)0xc00b, (q15_t)0x424e, (q15_t)0xc00b, (q15_t)0x4242, (q15_t)0xc00a, (q15_t)0x4235, (q15_t)0xc00a,
+    (q15_t)0x4229, (q15_t)0xc009, (q15_t)0x421c, (q15_t)0xc009, (q15_t)0x4210, (q15_t)0xc009, (q15_t)0x4203, (q15_t)0xc008,
+    (q15_t)0x41f7, (q15_t)0xc008, (q15_t)0x41ea, (q15_t)0xc007, (q15_t)0x41dd, (q15_t)0xc007, (q15_t)0x41d1, (q15_t)0xc007,
+    (q15_t)0x41c4, (q15_t)0xc006, (q15_t)0x41b8, (q15_t)0xc006, (q15_t)0x41ab, (q15_t)0xc006, (q15_t)0x419f, (q15_t)0xc005,
+    (q15_t)0x4192, (q15_t)0xc005, (q15_t)0x4186, (q15_t)0xc005, (q15_t)0x4179, (q15_t)0xc004, (q15_t)0x416c, (q15_t)0xc004,
+    (q15_t)0x4160, (q15_t)0xc004, (q15_t)0x4153, (q15_t)0xc004, (q15_t)0x4147, (q15_t)0xc003, (q15_t)0x413a, (q15_t)0xc003,
+    (q15_t)0x412e, (q15_t)0xc003, (q15_t)0x4121, (q15_t)0xc003, (q15_t)0x4114, (q15_t)0xc002, (q15_t)0x4108, (q15_t)0xc002,
+    (q15_t)0x40fb, (q15_t)0xc002, (q15_t)0x40ef, (q15_t)0xc002, (q15_t)0x40e2, (q15_t)0xc002, (q15_t)0x40d6, (q15_t)0xc001,
+    (q15_t)0x40c9, (q15_t)0xc001, (q15_t)0x40bc, (q15_t)0xc001, (q15_t)0x40b0, (q15_t)0xc001, (q15_t)0x40a3, (q15_t)0xc001,
+    (q15_t)0x4097, (q15_t)0xc001, (q15_t)0x408a, (q15_t)0xc001, (q15_t)0x407e, (q15_t)0xc000, (q15_t)0x4071, (q15_t)0xc000,
+    (q15_t)0x4065, (q15_t)0xc000, (q15_t)0x4058, (q15_t)0xc000, (q15_t)0x404b, (q15_t)0xc000, (q15_t)0x403f, (q15_t)0xc000,
+    (q15_t)0x4032, (q15_t)0xc000, (q15_t)0x4026, (q15_t)0xc000, (q15_t)0x4019, (q15_t)0xc000, (q15_t)0x400d, (q15_t)0xc000,
+};
+
+/**
+* @} end of RealFFT_Table group
+*/
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* @brief  Initialization function for the Q15 RFFT/RIFFT.
+* @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.
+* @param[in]      fftLenReal     length of the FFT.
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return         The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192.
+* \par
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* This function also initializes Twiddle factor table.
+*/
+arm_status arm_rfft_init_q15(
+    arm_rfft_instance_q15 * S,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag)
+{
+    /*  Initialise the default arm status */
+    arm_status status = ARM_MATH_SUCCESS;
+
+    /*  Initialize the Real FFT length */
+    S->fftLenReal = (uint16_t) fftLenReal;
+
+    /*  Initialize the Twiddle coefficientA pointer */
+    S->pTwiddleAReal = (q15_t *) realCoefAQ15;
+
+    /*  Initialize the Twiddle coefficientB pointer */
+    S->pTwiddleBReal = (q15_t *) realCoefBQ15;
+
+    /*  Initialize the Flag for selection of RFFT or RIFFT */
+    S->ifftFlagR = (uint8_t) ifftFlagR;
+
+    /*  Initialize the Flag for calculation Bit reversal or not */
+    S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+    /*  Initialization of coef modifier depending on the FFT length */
+    switch (S->fftLenReal)
+    {
+    case 8192U:
+        S->twidCoefRModifier = 1U;
+        S->pCfft = &arm_cfft_sR_q15_len4096;
+        break;
+    case 4096U:
+        S->twidCoefRModifier = 2U;
+        S->pCfft = &arm_cfft_sR_q15_len2048;
+        break;
+    case 2048U:
+        S->twidCoefRModifier = 4U;
+        S->pCfft = &arm_cfft_sR_q15_len1024;
+        break;
+    case 1024U:
+        S->twidCoefRModifier = 8U;
+        S->pCfft = &arm_cfft_sR_q15_len512;
+        break;
+    case 512U:
+        S->twidCoefRModifier = 16U;
+        S->pCfft = &arm_cfft_sR_q15_len256;
+        break;
+    case 256U:
+        S->twidCoefRModifier = 32U;
+        S->pCfft = &arm_cfft_sR_q15_len128;
+        break;
+    case 128U:
+        S->twidCoefRModifier = 64U;
+        S->pCfft = &arm_cfft_sR_q15_len64;
+        break;
+    case 64U:
+        S->twidCoefRModifier = 128U;
+        S->pCfft = &arm_cfft_sR_q15_len32;
+        break;
+    case 32U:
+        S->twidCoefRModifier = 256U;
+        S->pCfft = &arm_cfft_sR_q15_len16;
+        break;
+    default:
+        /*  Reporting argument error if rfftSize is not valid value */
+        status = ARM_MATH_ARGUMENT_ERROR;
+        break;
+    }
+
+    /* return the status of RFFT Init function */
+    return (status);
+}
+
+/**
+* @} end of RealFFT group
+*/
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c
new file mode 100644
index 0000000..04369ed
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c
@@ -0,0 +1,4280 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_rfft_init_q31.c
+ * Description:  RFFT & RIFFT Q31 initialisation function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include "arm_const_structs.h"
+
+/**
+* @ingroup RealFFT
+*/
+
+/**
+ * @addtogroup RealFFT_Table Real FFT Tables
+* @{
+*/
+
+/**
+* \par
+* Generation fixed-point realCoefAQ31 array in Q31 format:
+* \par
+* n = 4096
+* 
for (i = 0; i < n; i++)
+* {
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* }

+* \par
+* Convert to fixed point Q31 format
+*     round(pATable[i] * pow(2, 31))
+*/
+const q31_t realCoefAQ31[8192] = {
+    (q31_t)0x40000000, (q31_t)0xc0000000, (q31_t)0x3ff36f02, (q31_t)0xc000013c,
+    (q31_t)0x3fe6de05, (q31_t)0xc00004ef, (q31_t)0x3fda4d09, (q31_t)0xc0000b1a,
+    (q31_t)0x3fcdbc0f, (q31_t)0xc00013bd, (q31_t)0x3fc12b16, (q31_t)0xc0001ed8,
+    (q31_t)0x3fb49a1f, (q31_t)0xc0002c6a, (q31_t)0x3fa8092c, (q31_t)0xc0003c74,
+    (q31_t)0x3f9b783c, (q31_t)0xc0004ef5, (q31_t)0x3f8ee750, (q31_t)0xc00063ee,
+    (q31_t)0x3f825668, (q31_t)0xc0007b5f, (q31_t)0x3f75c585, (q31_t)0xc0009547,
+    (q31_t)0x3f6934a8, (q31_t)0xc000b1a7, (q31_t)0x3f5ca3d0, (q31_t)0xc000d07e,
+    (q31_t)0x3f5012fe, (q31_t)0xc000f1ce, (q31_t)0x3f438234, (q31_t)0xc0011594,
+    (q31_t)0x3f36f170, (q31_t)0xc0013bd3, (q31_t)0x3f2a60b4, (q31_t)0xc0016489,
+    (q31_t)0x3f1dd001, (q31_t)0xc0018fb6, (q31_t)0x3f113f56, (q31_t)0xc001bd5c,
+    (q31_t)0x3f04aeb5, (q31_t)0xc001ed78, (q31_t)0x3ef81e1d, (q31_t)0xc002200d,
+    (q31_t)0x3eeb8d8f, (q31_t)0xc0025519, (q31_t)0x3edefd0c, (q31_t)0xc0028c9c,
+    (q31_t)0x3ed26c94, (q31_t)0xc002c697, (q31_t)0x3ec5dc28, (q31_t)0xc003030a,
+    (q31_t)0x3eb94bc8, (q31_t)0xc00341f4, (q31_t)0x3eacbb74, (q31_t)0xc0038356,
+    (q31_t)0x3ea02b2e, (q31_t)0xc003c72f, (q31_t)0x3e939af5, (q31_t)0xc0040d80,
+    (q31_t)0x3e870aca, (q31_t)0xc0045648, (q31_t)0x3e7a7aae, (q31_t)0xc004a188,
+    (q31_t)0x3e6deaa1, (q31_t)0xc004ef3f, (q31_t)0x3e615aa3, (q31_t)0xc0053f6e,
+    (q31_t)0x3e54cab5, (q31_t)0xc0059214, (q31_t)0x3e483ad8, (q31_t)0xc005e731,
+    (q31_t)0x3e3bab0b, (q31_t)0xc0063ec6, (q31_t)0x3e2f1b50, (q31_t)0xc00698d3,
+    (q31_t)0x3e228ba7, (q31_t)0xc006f556, (q31_t)0x3e15fc11, (q31_t)0xc0075452,
+    (q31_t)0x3e096c8d, (q31_t)0xc007b5c4, (q31_t)0x3dfcdd1d, (q31_t)0xc00819ae,
+    (q31_t)0x3df04dc0, (q31_t)0xc008800f, (q31_t)0x3de3be78, (q31_t)0xc008e8e8,
+    (q31_t)0x3dd72f45, (q31_t)0xc0095438, (q31_t)0x3dcaa027, (q31_t)0xc009c1ff,
+    (q31_t)0x3dbe111e, (q31_t)0xc00a323d, (q31_t)0x3db1822c, (q31_t)0xc00aa4f3,
+    (q31_t)0x3da4f351, (q31_t)0xc00b1a20, (q31_t)0x3d98648d, (q31_t)0xc00b91c4,
+    (q31_t)0x3d8bd5e1, (q31_t)0xc00c0be0, (q31_t)0x3d7f474d, (q31_t)0xc00c8872,
+    (q31_t)0x3d72b8d2, (q31_t)0xc00d077c, (q31_t)0x3d662a70, (q31_t)0xc00d88fd,
+    (q31_t)0x3d599c28, (q31_t)0xc00e0cf5, (q31_t)0x3d4d0df9, (q31_t)0xc00e9364,
+    (q31_t)0x3d407fe6, (q31_t)0xc00f1c4a, (q31_t)0x3d33f1ed, (q31_t)0xc00fa7a8,
+    (q31_t)0x3d276410, (q31_t)0xc010357c, (q31_t)0x3d1ad650, (q31_t)0xc010c5c7,
+    (q31_t)0x3d0e48ab, (q31_t)0xc011588a, (q31_t)0x3d01bb24, (q31_t)0xc011edc3,
+    (q31_t)0x3cf52dbb, (q31_t)0xc0128574, (q31_t)0x3ce8a06f, (q31_t)0xc0131f9b,
+    (q31_t)0x3cdc1342, (q31_t)0xc013bc39, (q31_t)0x3ccf8634, (q31_t)0xc0145b4e,
+    (q31_t)0x3cc2f945, (q31_t)0xc014fcda, (q31_t)0x3cb66c77, (q31_t)0xc015a0dd,
+    (q31_t)0x3ca9dfc8, (q31_t)0xc0164757, (q31_t)0x3c9d533b, (q31_t)0xc016f047,
+    (q31_t)0x3c90c6cf, (q31_t)0xc0179bae, (q31_t)0x3c843a85, (q31_t)0xc018498c,
+    (q31_t)0x3c77ae5e, (q31_t)0xc018f9e1, (q31_t)0x3c6b2259, (q31_t)0xc019acac,
+    (q31_t)0x3c5e9678, (q31_t)0xc01a61ee, (q31_t)0x3c520aba, (q31_t)0xc01b19a7,
+    (q31_t)0x3c457f21, (q31_t)0xc01bd3d6, (q31_t)0x3c38f3ac, (q31_t)0xc01c907c,
+    (q31_t)0x3c2c685d, (q31_t)0xc01d4f99, (q31_t)0x3c1fdd34, (q31_t)0xc01e112b,
+    (q31_t)0x3c135231, (q31_t)0xc01ed535, (q31_t)0x3c06c754, (q31_t)0xc01f9bb5,
+    (q31_t)0x3bfa3c9f, (q31_t)0xc02064ab, (q31_t)0x3bedb212, (q31_t)0xc0213018,
+    (q31_t)0x3be127ac, (q31_t)0xc021fdfb, (q31_t)0x3bd49d70, (q31_t)0xc022ce54,
+    (q31_t)0x3bc8135c, (q31_t)0xc023a124, (q31_t)0x3bbb8973, (q31_t)0xc024766a,
+    (q31_t)0x3baeffb3, (q31_t)0xc0254e27, (q31_t)0x3ba2761e, (q31_t)0xc0262859,
+    (q31_t)0x3b95ecb4, (q31_t)0xc0270502, (q31_t)0x3b896375, (q31_t)0xc027e421,
+    (q31_t)0x3b7cda63, (q31_t)0xc028c5b6, (q31_t)0x3b70517d, (q31_t)0xc029a9c1,
+    (q31_t)0x3b63c8c4, (q31_t)0xc02a9042, (q31_t)0x3b574039, (q31_t)0xc02b7939,
+    (q31_t)0x3b4ab7db, (q31_t)0xc02c64a6, (q31_t)0x3b3e2fac, (q31_t)0xc02d5289,
+    (q31_t)0x3b31a7ac, (q31_t)0xc02e42e2, (q31_t)0x3b251fdc, (q31_t)0xc02f35b1,
+    (q31_t)0x3b18983b, (q31_t)0xc0302af5, (q31_t)0x3b0c10cb, (q31_t)0xc03122b0,
+    (q31_t)0x3aff898c, (q31_t)0xc0321ce0, (q31_t)0x3af3027e, (q31_t)0xc0331986,
+    (q31_t)0x3ae67ba2, (q31_t)0xc03418a2, (q31_t)0x3ad9f4f8, (q31_t)0xc0351a33,
+    (q31_t)0x3acd6e81, (q31_t)0xc0361e3a, (q31_t)0x3ac0e83d, (q31_t)0xc03724b6,
+    (q31_t)0x3ab4622d, (q31_t)0xc0382da8, (q31_t)0x3aa7dc52, (q31_t)0xc0393910,
+    (q31_t)0x3a9b56ab, (q31_t)0xc03a46ed, (q31_t)0x3a8ed139, (q31_t)0xc03b573f,
+    (q31_t)0x3a824bfd, (q31_t)0xc03c6a07, (q31_t)0x3a75c6f8, (q31_t)0xc03d7f44,
+    (q31_t)0x3a694229, (q31_t)0xc03e96f6, (q31_t)0x3a5cbd91, (q31_t)0xc03fb11d,
+    (q31_t)0x3a503930, (q31_t)0xc040cdba, (q31_t)0x3a43b508, (q31_t)0xc041eccc,
+    (q31_t)0x3a373119, (q31_t)0xc0430e53, (q31_t)0x3a2aad62, (q31_t)0xc044324f,
+    (q31_t)0x3a1e29e5, (q31_t)0xc04558c0, (q31_t)0x3a11a6a3, (q31_t)0xc04681a6,
+    (q31_t)0x3a05239a, (q31_t)0xc047ad01, (q31_t)0x39f8a0cd, (q31_t)0xc048dad1,
+    (q31_t)0x39ec1e3b, (q31_t)0xc04a0b16, (q31_t)0x39df9be6, (q31_t)0xc04b3dcf,
+    (q31_t)0x39d319cc, (q31_t)0xc04c72fe, (q31_t)0x39c697f0, (q31_t)0xc04daaa1,
+    (q31_t)0x39ba1651, (q31_t)0xc04ee4b8, (q31_t)0x39ad94f0, (q31_t)0xc0502145,
+    (q31_t)0x39a113cd, (q31_t)0xc0516045, (q31_t)0x399492ea, (q31_t)0xc052a1bb,
+    (q31_t)0x39881245, (q31_t)0xc053e5a5, (q31_t)0x397b91e1, (q31_t)0xc0552c03,
+    (q31_t)0x396f11bc, (q31_t)0xc05674d6, (q31_t)0x396291d9, (q31_t)0xc057c01d,
+    (q31_t)0x39561237, (q31_t)0xc0590dd8, (q31_t)0x394992d7, (q31_t)0xc05a5e07,
+    (q31_t)0x393d13b8, (q31_t)0xc05bb0ab, (q31_t)0x393094dd, (q31_t)0xc05d05c3,
+    (q31_t)0x39241645, (q31_t)0xc05e5d4e, (q31_t)0x391797f0, (q31_t)0xc05fb74e,
+    (q31_t)0x390b19e0, (q31_t)0xc06113c2, (q31_t)0x38fe9c15, (q31_t)0xc06272aa,
+    (q31_t)0x38f21e8e, (q31_t)0xc063d405, (q31_t)0x38e5a14d, (q31_t)0xc06537d4,
+    (q31_t)0x38d92452, (q31_t)0xc0669e18, (q31_t)0x38cca79e, (q31_t)0xc06806ce,
+    (q31_t)0x38c02b31, (q31_t)0xc06971f9, (q31_t)0x38b3af0c, (q31_t)0xc06adf97,
+    (q31_t)0x38a7332e, (q31_t)0xc06c4fa8, (q31_t)0x389ab799, (q31_t)0xc06dc22e,
+    (q31_t)0x388e3c4d, (q31_t)0xc06f3726, (q31_t)0x3881c14b, (q31_t)0xc070ae92,
+    (q31_t)0x38754692, (q31_t)0xc0722871, (q31_t)0x3868cc24, (q31_t)0xc073a4c3,
+    (q31_t)0x385c5201, (q31_t)0xc0752389, (q31_t)0x384fd829, (q31_t)0xc076a4c2,
+    (q31_t)0x38435e9d, (q31_t)0xc078286e, (q31_t)0x3836e55d, (q31_t)0xc079ae8c,
+    (q31_t)0x382a6c6a, (q31_t)0xc07b371e, (q31_t)0x381df3c5, (q31_t)0xc07cc223,
+    (q31_t)0x38117b6d, (q31_t)0xc07e4f9b, (q31_t)0x38050364, (q31_t)0xc07fdf85,
+    (q31_t)0x37f88ba9, (q31_t)0xc08171e2, (q31_t)0x37ec143e, (q31_t)0xc08306b2,
+    (q31_t)0x37df9d22, (q31_t)0xc0849df4, (q31_t)0x37d32657, (q31_t)0xc08637a9,
+    (q31_t)0x37c6afdc, (q31_t)0xc087d3d0, (q31_t)0x37ba39b3, (q31_t)0xc089726a,
+    (q31_t)0x37adc3db, (q31_t)0xc08b1376, (q31_t)0x37a14e55, (q31_t)0xc08cb6f5,
+    (q31_t)0x3794d922, (q31_t)0xc08e5ce5, (q31_t)0x37886442, (q31_t)0xc0900548,
+    (q31_t)0x377befb5, (q31_t)0xc091b01d, (q31_t)0x376f7b7d, (q31_t)0xc0935d64,
+    (q31_t)0x37630799, (q31_t)0xc0950d1d, (q31_t)0x3756940a, (q31_t)0xc096bf48,
+    (q31_t)0x374a20d0, (q31_t)0xc09873e4, (q31_t)0x373daded, (q31_t)0xc09a2af3,
+    (q31_t)0x37313b60, (q31_t)0xc09be473, (q31_t)0x3724c92a, (q31_t)0xc09da065,
+    (q31_t)0x3718574b, (q31_t)0xc09f5ec8, (q31_t)0x370be5c4, (q31_t)0xc0a11f9d,
+    (q31_t)0x36ff7496, (q31_t)0xc0a2e2e3, (q31_t)0x36f303c0, (q31_t)0xc0a4a89b,
+    (q31_t)0x36e69344, (q31_t)0xc0a670c4, (q31_t)0x36da2321, (q31_t)0xc0a83b5e,
+    (q31_t)0x36cdb359, (q31_t)0xc0aa086a, (q31_t)0x36c143ec, (q31_t)0xc0abd7e6,
+    (q31_t)0x36b4d4d9, (q31_t)0xc0ada9d4, (q31_t)0x36a86623, (q31_t)0xc0af7e33,
+    (q31_t)0x369bf7c9, (q31_t)0xc0b15502, (q31_t)0x368f89cb, (q31_t)0xc0b32e42,
+    (q31_t)0x36831c2b, (q31_t)0xc0b509f3, (q31_t)0x3676aee8, (q31_t)0xc0b6e815,
+    (q31_t)0x366a4203, (q31_t)0xc0b8c8a7, (q31_t)0x365dd57d, (q31_t)0xc0baabaa,
+    (q31_t)0x36516956, (q31_t)0xc0bc911d, (q31_t)0x3644fd8f, (q31_t)0xc0be7901,
+    (q31_t)0x36389228, (q31_t)0xc0c06355, (q31_t)0x362c2721, (q31_t)0xc0c25019,
+    (q31_t)0x361fbc7b, (q31_t)0xc0c43f4d, (q31_t)0x36135237, (q31_t)0xc0c630f2,
+    (q31_t)0x3606e854, (q31_t)0xc0c82506, (q31_t)0x35fa7ed4, (q31_t)0xc0ca1b8a,
+    (q31_t)0x35ee15b7, (q31_t)0xc0cc147f, (q31_t)0x35e1acfd, (q31_t)0xc0ce0fe3,
+    (q31_t)0x35d544a7, (q31_t)0xc0d00db6, (q31_t)0x35c8dcb6, (q31_t)0xc0d20dfa,
+    (q31_t)0x35bc7529, (q31_t)0xc0d410ad, (q31_t)0x35b00e02, (q31_t)0xc0d615cf,
+    (q31_t)0x35a3a740, (q31_t)0xc0d81d61, (q31_t)0x359740e5, (q31_t)0xc0da2762,
+    (q31_t)0x358adaf0, (q31_t)0xc0dc33d2, (q31_t)0x357e7563, (q31_t)0xc0de42b2,
+    (q31_t)0x3572103d, (q31_t)0xc0e05401, (q31_t)0x3565ab80, (q31_t)0xc0e267be,
+    (q31_t)0x3559472b, (q31_t)0xc0e47deb, (q31_t)0x354ce33f, (q31_t)0xc0e69686,
+    (q31_t)0x35407fbd, (q31_t)0xc0e8b190, (q31_t)0x35341ca5, (q31_t)0xc0eacf09,
+    (q31_t)0x3527b9f7, (q31_t)0xc0eceef1, (q31_t)0x351b57b5, (q31_t)0xc0ef1147,
+    (q31_t)0x350ef5de, (q31_t)0xc0f1360b, (q31_t)0x35029473, (q31_t)0xc0f35d3e,
+    (q31_t)0x34f63374, (q31_t)0xc0f586df, (q31_t)0x34e9d2e3, (q31_t)0xc0f7b2ee,
+    (q31_t)0x34dd72be, (q31_t)0xc0f9e16b, (q31_t)0x34d11308, (q31_t)0xc0fc1257,
+    (q31_t)0x34c4b3c0, (q31_t)0xc0fe45b0, (q31_t)0x34b854e7, (q31_t)0xc1007b77,
+    (q31_t)0x34abf67e, (q31_t)0xc102b3ac, (q31_t)0x349f9884, (q31_t)0xc104ee4f,
+    (q31_t)0x34933afa, (q31_t)0xc1072b5f, (q31_t)0x3486dde1, (q31_t)0xc1096add,
+    (q31_t)0x347a8139, (q31_t)0xc10bacc8, (q31_t)0x346e2504, (q31_t)0xc10df120,
+    (q31_t)0x3461c940, (q31_t)0xc11037e6, (q31_t)0x34556def, (q31_t)0xc1128119,
+    (q31_t)0x34491311, (q31_t)0xc114ccb9, (q31_t)0x343cb8a7, (q31_t)0xc1171ac6,
+    (q31_t)0x34305eb0, (q31_t)0xc1196b3f, (q31_t)0x3424052f, (q31_t)0xc11bbe26,
+    (q31_t)0x3417ac22, (q31_t)0xc11e1379, (q31_t)0x340b538b, (q31_t)0xc1206b39,
+    (q31_t)0x33fefb6a, (q31_t)0xc122c566, (q31_t)0x33f2a3bf, (q31_t)0xc12521ff,
+    (q31_t)0x33e64c8c, (q31_t)0xc1278104, (q31_t)0x33d9f5cf, (q31_t)0xc129e276,
+    (q31_t)0x33cd9f8b, (q31_t)0xc12c4653, (q31_t)0x33c149bf, (q31_t)0xc12eac9d,
+    (q31_t)0x33b4f46c, (q31_t)0xc1311553, (q31_t)0x33a89f92, (q31_t)0xc1338075,
+    (q31_t)0x339c4b32, (q31_t)0xc135ee02, (q31_t)0x338ff74d, (q31_t)0xc1385dfb,
+    (q31_t)0x3383a3e2, (q31_t)0xc13ad060, (q31_t)0x337750f2, (q31_t)0xc13d4530,
+    (q31_t)0x336afe7e, (q31_t)0xc13fbc6c, (q31_t)0x335eac86, (q31_t)0xc1423613,
+    (q31_t)0x33525b0b, (q31_t)0xc144b225, (q31_t)0x33460a0d, (q31_t)0xc14730a3,
+    (q31_t)0x3339b98d, (q31_t)0xc149b18b, (q31_t)0x332d698a, (q31_t)0xc14c34df,
+    (q31_t)0x33211a07, (q31_t)0xc14eba9d, (q31_t)0x3314cb02, (q31_t)0xc15142c6,
+    (q31_t)0x33087c7d, (q31_t)0xc153cd5a, (q31_t)0x32fc2e77, (q31_t)0xc1565a58,
+    (q31_t)0x32efe0f2, (q31_t)0xc158e9c1, (q31_t)0x32e393ef, (q31_t)0xc15b7b94,
+    (q31_t)0x32d7476c, (q31_t)0xc15e0fd1, (q31_t)0x32cafb6b, (q31_t)0xc160a678,
+    (q31_t)0x32beafed, (q31_t)0xc1633f8a, (q31_t)0x32b264f2, (q31_t)0xc165db05,
+    (q31_t)0x32a61a7a, (q31_t)0xc16878eb, (q31_t)0x3299d085, (q31_t)0xc16b193a,
+    (q31_t)0x328d8715, (q31_t)0xc16dbbf3, (q31_t)0x32813e2a, (q31_t)0xc1706115,
+    (q31_t)0x3274f5c3, (q31_t)0xc17308a1, (q31_t)0x3268ade3, (q31_t)0xc175b296,
+    (q31_t)0x325c6688, (q31_t)0xc1785ef4, (q31_t)0x32501fb5, (q31_t)0xc17b0dbb,
+    (q31_t)0x3243d968, (q31_t)0xc17dbeec, (q31_t)0x323793a3, (q31_t)0xc1807285,
+    (q31_t)0x322b4e66, (q31_t)0xc1832888, (q31_t)0x321f09b1, (q31_t)0xc185e0f3,
+    (q31_t)0x3212c585, (q31_t)0xc1889bc6, (q31_t)0x320681e3, (q31_t)0xc18b5903,
+    (q31_t)0x31fa3ecb, (q31_t)0xc18e18a7, (q31_t)0x31edfc3d, (q31_t)0xc190dab4,
+    (q31_t)0x31e1ba3a, (q31_t)0xc1939f29, (q31_t)0x31d578c2, (q31_t)0xc1966606,
+    (q31_t)0x31c937d6, (q31_t)0xc1992f4c, (q31_t)0x31bcf777, (q31_t)0xc19bfaf9,
+    (q31_t)0x31b0b7a4, (q31_t)0xc19ec90d, (q31_t)0x31a4785e, (q31_t)0xc1a1998a,
+    (q31_t)0x319839a6, (q31_t)0xc1a46c6e, (q31_t)0x318bfb7d, (q31_t)0xc1a741b9,
+    (q31_t)0x317fbde2, (q31_t)0xc1aa196c, (q31_t)0x317380d6, (q31_t)0xc1acf386,
+    (q31_t)0x31674459, (q31_t)0xc1afd007, (q31_t)0x315b086d, (q31_t)0xc1b2aef0,
+    (q31_t)0x314ecd11, (q31_t)0xc1b5903f, (q31_t)0x31429247, (q31_t)0xc1b873f5,
+    (q31_t)0x3136580d, (q31_t)0xc1bb5a11, (q31_t)0x312a1e66, (q31_t)0xc1be4294,
+    (q31_t)0x311de551, (q31_t)0xc1c12d7e, (q31_t)0x3111accf, (q31_t)0xc1c41ace,
+    (q31_t)0x310574e0, (q31_t)0xc1c70a84, (q31_t)0x30f93d86, (q31_t)0xc1c9fca0,
+    (q31_t)0x30ed06bf, (q31_t)0xc1ccf122, (q31_t)0x30e0d08d, (q31_t)0xc1cfe80a,
+    (q31_t)0x30d49af1, (q31_t)0xc1d2e158, (q31_t)0x30c865ea, (q31_t)0xc1d5dd0c,
+    (q31_t)0x30bc317a, (q31_t)0xc1d8db25, (q31_t)0x30affda0, (q31_t)0xc1dbdba3,
+    (q31_t)0x30a3ca5d, (q31_t)0xc1dede87, (q31_t)0x309797b2, (q31_t)0xc1e1e3d0,
+    (q31_t)0x308b659f, (q31_t)0xc1e4eb7e, (q31_t)0x307f3424, (q31_t)0xc1e7f591,
+    (q31_t)0x30730342, (q31_t)0xc1eb0209, (q31_t)0x3066d2fa, (q31_t)0xc1ee10e5,
+    (q31_t)0x305aa34c, (q31_t)0xc1f12227, (q31_t)0x304e7438, (q31_t)0xc1f435cc,
+    (q31_t)0x304245c0, (q31_t)0xc1f74bd6, (q31_t)0x303617e2, (q31_t)0xc1fa6445,
+    (q31_t)0x3029eaa1, (q31_t)0xc1fd7f17, (q31_t)0x301dbdfb, (q31_t)0xc2009c4e,
+    (q31_t)0x301191f3, (q31_t)0xc203bbe8, (q31_t)0x30056687, (q31_t)0xc206dde6,
+    (q31_t)0x2ff93bba, (q31_t)0xc20a0248, (q31_t)0x2fed118a, (q31_t)0xc20d290d,
+    (q31_t)0x2fe0e7f9, (q31_t)0xc2105236, (q31_t)0x2fd4bf08, (q31_t)0xc2137dc2,
+    (q31_t)0x2fc896b5, (q31_t)0xc216abb1, (q31_t)0x2fbc6f03, (q31_t)0xc219dc03,
+    (q31_t)0x2fb047f2, (q31_t)0xc21d0eb8, (q31_t)0x2fa42181, (q31_t)0xc22043d0,
+    (q31_t)0x2f97fbb2, (q31_t)0xc2237b4b, (q31_t)0x2f8bd685, (q31_t)0xc226b528,
+    (q31_t)0x2f7fb1fa, (q31_t)0xc229f167, (q31_t)0x2f738e12, (q31_t)0xc22d3009,
+    (q31_t)0x2f676ace, (q31_t)0xc230710d, (q31_t)0x2f5b482d, (q31_t)0xc233b473,
+    (q31_t)0x2f4f2630, (q31_t)0xc236fa3b, (q31_t)0x2f4304d8, (q31_t)0xc23a4265,
+    (q31_t)0x2f36e426, (q31_t)0xc23d8cf1, (q31_t)0x2f2ac419, (q31_t)0xc240d9de,
+    (q31_t)0x2f1ea4b2, (q31_t)0xc244292c, (q31_t)0x2f1285f2, (q31_t)0xc2477adc,
+    (q31_t)0x2f0667d9, (q31_t)0xc24aceed, (q31_t)0x2efa4a67, (q31_t)0xc24e255e,
+    (q31_t)0x2eee2d9d, (q31_t)0xc2517e31, (q31_t)0x2ee2117c, (q31_t)0xc254d965,
+    (q31_t)0x2ed5f604, (q31_t)0xc25836f9, (q31_t)0x2ec9db35, (q31_t)0xc25b96ee,
+    (q31_t)0x2ebdc110, (q31_t)0xc25ef943, (q31_t)0x2eb1a796, (q31_t)0xc2625df8,
+    (q31_t)0x2ea58ec6, (q31_t)0xc265c50e, (q31_t)0x2e9976a1, (q31_t)0xc2692e83,
+    (q31_t)0x2e8d5f29, (q31_t)0xc26c9a58, (q31_t)0x2e81485c, (q31_t)0xc270088e,
+    (q31_t)0x2e75323c, (q31_t)0xc2737922, (q31_t)0x2e691cc9, (q31_t)0xc276ec16,
+    (q31_t)0x2e5d0804, (q31_t)0xc27a616a, (q31_t)0x2e50f3ed, (q31_t)0xc27dd91c,
+    (q31_t)0x2e44e084, (q31_t)0xc281532e, (q31_t)0x2e38cdcb, (q31_t)0xc284cf9f,
+    (q31_t)0x2e2cbbc1, (q31_t)0xc2884e6e, (q31_t)0x2e20aa67, (q31_t)0xc28bcf9c,
+    (q31_t)0x2e1499bd, (q31_t)0xc28f5329, (q31_t)0x2e0889c4, (q31_t)0xc292d914,
+    (q31_t)0x2dfc7a7c, (q31_t)0xc296615d, (q31_t)0x2df06be6, (q31_t)0xc299ec05,
+    (q31_t)0x2de45e03, (q31_t)0xc29d790a, (q31_t)0x2dd850d2, (q31_t)0xc2a1086d,
+    (q31_t)0x2dcc4454, (q31_t)0xc2a49a2e, (q31_t)0x2dc0388a, (q31_t)0xc2a82e4d,
+    (q31_t)0x2db42d74, (q31_t)0xc2abc4c9, (q31_t)0x2da82313, (q31_t)0xc2af5da2,
+    (q31_t)0x2d9c1967, (q31_t)0xc2b2f8d8, (q31_t)0x2d901070, (q31_t)0xc2b6966c,
+    (q31_t)0x2d84082f, (q31_t)0xc2ba365c, (q31_t)0x2d7800a5, (q31_t)0xc2bdd8a9,
+    (q31_t)0x2d6bf9d1, (q31_t)0xc2c17d52, (q31_t)0x2d5ff3b5, (q31_t)0xc2c52459,
+    (q31_t)0x2d53ee51, (q31_t)0xc2c8cdbb, (q31_t)0x2d47e9a5, (q31_t)0xc2cc7979,
+    (q31_t)0x2d3be5b1, (q31_t)0xc2d02794, (q31_t)0x2d2fe277, (q31_t)0xc2d3d80a,
+    (q31_t)0x2d23dff7, (q31_t)0xc2d78add, (q31_t)0x2d17de31, (q31_t)0xc2db400a,
+    (q31_t)0x2d0bdd25, (q31_t)0xc2def794, (q31_t)0x2cffdcd4, (q31_t)0xc2e2b178,
+    (q31_t)0x2cf3dd3f, (q31_t)0xc2e66db8, (q31_t)0x2ce7de66, (q31_t)0xc2ea2c53,
+    (q31_t)0x2cdbe04a, (q31_t)0xc2eded49, (q31_t)0x2ccfe2ea, (q31_t)0xc2f1b099,
+    (q31_t)0x2cc3e648, (q31_t)0xc2f57644, (q31_t)0x2cb7ea63, (q31_t)0xc2f93e4a,
+    (q31_t)0x2cabef3d, (q31_t)0xc2fd08a9, (q31_t)0x2c9ff4d6, (q31_t)0xc300d563,
+    (q31_t)0x2c93fb2e, (q31_t)0xc304a477, (q31_t)0x2c880245, (q31_t)0xc30875e5,
+    (q31_t)0x2c7c0a1d, (q31_t)0xc30c49ad, (q31_t)0x2c7012b5, (q31_t)0xc3101fce,
+    (q31_t)0x2c641c0e, (q31_t)0xc313f848, (q31_t)0x2c582629, (q31_t)0xc317d31c,
+    (q31_t)0x2c4c3106, (q31_t)0xc31bb049, (q31_t)0x2c403ca5, (q31_t)0xc31f8fcf,
+    (q31_t)0x2c344908, (q31_t)0xc32371ae, (q31_t)0x2c28562d, (q31_t)0xc32755e5,
+    (q31_t)0x2c1c6417, (q31_t)0xc32b3c75, (q31_t)0x2c1072c4, (q31_t)0xc32f255e,
+    (q31_t)0x2c048237, (q31_t)0xc333109e, (q31_t)0x2bf8926f, (q31_t)0xc336fe37,
+    (q31_t)0x2beca36c, (q31_t)0xc33aee27, (q31_t)0x2be0b52f, (q31_t)0xc33ee070,
+    (q31_t)0x2bd4c7ba, (q31_t)0xc342d510, (q31_t)0x2bc8db0b, (q31_t)0xc346cc07,
+    (q31_t)0x2bbcef23, (q31_t)0xc34ac556, (q31_t)0x2bb10404, (q31_t)0xc34ec0fc,
+    (q31_t)0x2ba519ad, (q31_t)0xc352bef9, (q31_t)0x2b99301f, (q31_t)0xc356bf4d,
+    (q31_t)0x2b8d475b, (q31_t)0xc35ac1f7, (q31_t)0x2b815f60, (q31_t)0xc35ec6f8,
+    (q31_t)0x2b75782f, (q31_t)0xc362ce50, (q31_t)0x2b6991ca, (q31_t)0xc366d7fd,
+    (q31_t)0x2b5dac2f, (q31_t)0xc36ae401, (q31_t)0x2b51c760, (q31_t)0xc36ef25b,
+    (q31_t)0x2b45e35d, (q31_t)0xc373030a, (q31_t)0x2b3a0027, (q31_t)0xc377160f,
+    (q31_t)0x2b2e1dbe, (q31_t)0xc37b2b6a, (q31_t)0x2b223c22, (q31_t)0xc37f4319,
+    (q31_t)0x2b165b54, (q31_t)0xc3835d1e, (q31_t)0x2b0a7b54, (q31_t)0xc3877978,
+    (q31_t)0x2afe9c24, (q31_t)0xc38b9827, (q31_t)0x2af2bdc3, (q31_t)0xc38fb92a,
+    (q31_t)0x2ae6e031, (q31_t)0xc393dc82, (q31_t)0x2adb0370, (q31_t)0xc398022f,
+    (q31_t)0x2acf277f, (q31_t)0xc39c2a2f, (q31_t)0x2ac34c60, (q31_t)0xc3a05484,
+    (q31_t)0x2ab77212, (q31_t)0xc3a4812c, (q31_t)0x2aab9896, (q31_t)0xc3a8b028,
+    (q31_t)0x2a9fbfed, (q31_t)0xc3ace178, (q31_t)0x2a93e817, (q31_t)0xc3b1151b,
+    (q31_t)0x2a881114, (q31_t)0xc3b54b11, (q31_t)0x2a7c3ae5, (q31_t)0xc3b9835a,
+    (q31_t)0x2a70658a, (q31_t)0xc3bdbdf6, (q31_t)0x2a649105, (q31_t)0xc3c1fae5,
+    (q31_t)0x2a58bd54, (q31_t)0xc3c63a26, (q31_t)0x2a4cea79, (q31_t)0xc3ca7bba,
+    (q31_t)0x2a411874, (q31_t)0xc3cebfa0, (q31_t)0x2a354746, (q31_t)0xc3d305d8,
+    (q31_t)0x2a2976ef, (q31_t)0xc3d74e62, (q31_t)0x2a1da770, (q31_t)0xc3db993e,
+    (q31_t)0x2a11d8c8, (q31_t)0xc3dfe66c, (q31_t)0x2a060af9, (q31_t)0xc3e435ea,
+    (q31_t)0x29fa3e03, (q31_t)0xc3e887bb, (q31_t)0x29ee71e6, (q31_t)0xc3ecdbdc,
+    (q31_t)0x29e2a6a3, (q31_t)0xc3f1324e, (q31_t)0x29d6dc3b, (q31_t)0xc3f58b10,
+    (q31_t)0x29cb12ad, (q31_t)0xc3f9e624, (q31_t)0x29bf49fa, (q31_t)0xc3fe4388,
+    (q31_t)0x29b38223, (q31_t)0xc402a33c, (q31_t)0x29a7bb28, (q31_t)0xc4070540,
+    (q31_t)0x299bf509, (q31_t)0xc40b6994, (q31_t)0x29902fc7, (q31_t)0xc40fd037,
+    (q31_t)0x29846b63, (q31_t)0xc414392b, (q31_t)0x2978a7dd, (q31_t)0xc418a46d,
+    (q31_t)0x296ce535, (q31_t)0xc41d11ff, (q31_t)0x2961236c, (q31_t)0xc42181e0,
+    (q31_t)0x29556282, (q31_t)0xc425f410, (q31_t)0x2949a278, (q31_t)0xc42a688f,
+    (q31_t)0x293de34e, (q31_t)0xc42edf5c, (q31_t)0x29322505, (q31_t)0xc4335877,
+    (q31_t)0x2926679c, (q31_t)0xc437d3e1, (q31_t)0x291aab16, (q31_t)0xc43c5199,
+    (q31_t)0x290eef71, (q31_t)0xc440d19e, (q31_t)0x290334af, (q31_t)0xc44553f2,
+    (q31_t)0x28f77acf, (q31_t)0xc449d892, (q31_t)0x28ebc1d3, (q31_t)0xc44e5f80,
+    (q31_t)0x28e009ba, (q31_t)0xc452e8bc, (q31_t)0x28d45286, (q31_t)0xc4577444,
+    (q31_t)0x28c89c37, (q31_t)0xc45c0219, (q31_t)0x28bce6cd, (q31_t)0xc460923b,
+    (q31_t)0x28b13248, (q31_t)0xc46524a9, (q31_t)0x28a57ea9, (q31_t)0xc469b963,
+    (q31_t)0x2899cbf1, (q31_t)0xc46e5069, (q31_t)0x288e1a20, (q31_t)0xc472e9bc,
+    (q31_t)0x28826936, (q31_t)0xc477855a, (q31_t)0x2876b934, (q31_t)0xc47c2344,
+    (q31_t)0x286b0a1a, (q31_t)0xc480c379, (q31_t)0x285f5be9, (q31_t)0xc48565f9,
+    (q31_t)0x2853aea1, (q31_t)0xc48a0ac4, (q31_t)0x28480243, (q31_t)0xc48eb1db,
+    (q31_t)0x283c56cf, (q31_t)0xc4935b3c, (q31_t)0x2830ac45, (q31_t)0xc49806e7,
+    (q31_t)0x282502a7, (q31_t)0xc49cb4dd, (q31_t)0x281959f4, (q31_t)0xc4a1651c,
+    (q31_t)0x280db22d, (q31_t)0xc4a617a6, (q31_t)0x28020b52, (q31_t)0xc4aacc7a,
+    (q31_t)0x27f66564, (q31_t)0xc4af8397, (q31_t)0x27eac063, (q31_t)0xc4b43cfd,
+    (q31_t)0x27df1c50, (q31_t)0xc4b8f8ad, (q31_t)0x27d3792b, (q31_t)0xc4bdb6a6,
+    (q31_t)0x27c7d6f4, (q31_t)0xc4c276e8, (q31_t)0x27bc35ad, (q31_t)0xc4c73972,
+    (q31_t)0x27b09555, (q31_t)0xc4cbfe45, (q31_t)0x27a4f5ed, (q31_t)0xc4d0c560,
+    (q31_t)0x27995776, (q31_t)0xc4d58ec3, (q31_t)0x278db9ef, (q31_t)0xc4da5a6f,
+    (q31_t)0x27821d59, (q31_t)0xc4df2862, (q31_t)0x277681b6, (q31_t)0xc4e3f89c,
+    (q31_t)0x276ae704, (q31_t)0xc4e8cb1e, (q31_t)0x275f4d45, (q31_t)0xc4ed9fe7,
+    (q31_t)0x2753b479, (q31_t)0xc4f276f7, (q31_t)0x27481ca1, (q31_t)0xc4f7504e,
+    (q31_t)0x273c85bc, (q31_t)0xc4fc2bec, (q31_t)0x2730efcc, (q31_t)0xc50109d0,
+    (q31_t)0x27255ad1, (q31_t)0xc505e9fb, (q31_t)0x2719c6cb, (q31_t)0xc50acc6b,
+    (q31_t)0x270e33bb, (q31_t)0xc50fb121, (q31_t)0x2702a1a1, (q31_t)0xc514981d,
+    (q31_t)0x26f7107e, (q31_t)0xc519815f, (q31_t)0x26eb8052, (q31_t)0xc51e6ce6,
+    (q31_t)0x26dff11d, (q31_t)0xc5235ab2, (q31_t)0x26d462e1, (q31_t)0xc5284ac3,
+    (q31_t)0x26c8d59c, (q31_t)0xc52d3d18, (q31_t)0x26bd4951, (q31_t)0xc53231b3,
+    (q31_t)0x26b1bdff, (q31_t)0xc5372891, (q31_t)0x26a633a6, (q31_t)0xc53c21b4,
+    (q31_t)0x269aaa48, (q31_t)0xc5411d1b, (q31_t)0x268f21e5, (q31_t)0xc5461ac6,
+    (q31_t)0x26839a7c, (q31_t)0xc54b1ab4, (q31_t)0x26781410, (q31_t)0xc5501ce5,
+    (q31_t)0x266c8e9f, (q31_t)0xc555215a, (q31_t)0x26610a2a, (q31_t)0xc55a2812,
+    (q31_t)0x265586b3, (q31_t)0xc55f310d, (q31_t)0x264a0438, (q31_t)0xc5643c4a,
+    (q31_t)0x263e82bc, (q31_t)0xc56949ca, (q31_t)0x2633023e, (q31_t)0xc56e598c,
+    (q31_t)0x262782be, (q31_t)0xc5736b90, (q31_t)0x261c043d, (q31_t)0xc5787fd6,
+    (q31_t)0x261086bc, (q31_t)0xc57d965d, (q31_t)0x26050a3b, (q31_t)0xc582af26,
+    (q31_t)0x25f98ebb, (q31_t)0xc587ca31, (q31_t)0x25ee143b, (q31_t)0xc58ce77c,
+    (q31_t)0x25e29abc, (q31_t)0xc5920708, (q31_t)0x25d72240, (q31_t)0xc59728d5,
+    (q31_t)0x25cbaac5, (q31_t)0xc59c4ce3, (q31_t)0x25c0344d, (q31_t)0xc5a17330,
+    (q31_t)0x25b4bed8, (q31_t)0xc5a69bbe, (q31_t)0x25a94a67, (q31_t)0xc5abc68c,
+    (q31_t)0x259dd6f9, (q31_t)0xc5b0f399, (q31_t)0x25926490, (q31_t)0xc5b622e6,
+    (q31_t)0x2586f32c, (q31_t)0xc5bb5472, (q31_t)0x257b82cd, (q31_t)0xc5c0883d,
+    (q31_t)0x25701374, (q31_t)0xc5c5be47, (q31_t)0x2564a521, (q31_t)0xc5caf690,
+    (q31_t)0x255937d5, (q31_t)0xc5d03118, (q31_t)0x254dcb8f, (q31_t)0xc5d56ddd,
+    (q31_t)0x25426051, (q31_t)0xc5daace1, (q31_t)0x2536f61b, (q31_t)0xc5dfee22,
+    (q31_t)0x252b8cee, (q31_t)0xc5e531a1, (q31_t)0x252024c9, (q31_t)0xc5ea775e,
+    (q31_t)0x2514bdad, (q31_t)0xc5efbf58, (q31_t)0x2509579b, (q31_t)0xc5f5098f,
+    (q31_t)0x24fdf294, (q31_t)0xc5fa5603, (q31_t)0x24f28e96, (q31_t)0xc5ffa4b3,
+    (q31_t)0x24e72ba4, (q31_t)0xc604f5a0, (q31_t)0x24dbc9bd, (q31_t)0xc60a48c9,
+    (q31_t)0x24d068e2, (q31_t)0xc60f9e2e, (q31_t)0x24c50914, (q31_t)0xc614f5cf,
+    (q31_t)0x24b9aa52, (q31_t)0xc61a4fac, (q31_t)0x24ae4c9d, (q31_t)0xc61fabc4,
+    (q31_t)0x24a2eff6, (q31_t)0xc6250a18, (q31_t)0x2497945d, (q31_t)0xc62a6aa6,
+    (q31_t)0x248c39d3, (q31_t)0xc62fcd6f, (q31_t)0x2480e057, (q31_t)0xc6353273,
+    (q31_t)0x247587eb, (q31_t)0xc63a99b1, (q31_t)0x246a308f, (q31_t)0xc6400329,
+    (q31_t)0x245eda43, (q31_t)0xc6456edb, (q31_t)0x24538507, (q31_t)0xc64adcc7,
+    (q31_t)0x244830dd, (q31_t)0xc6504ced, (q31_t)0x243cddc4, (q31_t)0xc655bf4c,
+    (q31_t)0x24318bbe, (q31_t)0xc65b33e4, (q31_t)0x24263ac9, (q31_t)0xc660aab5,
+    (q31_t)0x241aeae8, (q31_t)0xc66623be, (q31_t)0x240f9c1a, (q31_t)0xc66b9f01,
+    (q31_t)0x24044e60, (q31_t)0xc6711c7b, (q31_t)0x23f901ba, (q31_t)0xc6769c2e,
+    (q31_t)0x23edb628, (q31_t)0xc67c1e18, (q31_t)0x23e26bac, (q31_t)0xc681a23a,
+    (q31_t)0x23d72245, (q31_t)0xc6872894, (q31_t)0x23cbd9f4, (q31_t)0xc68cb124,
+    (q31_t)0x23c092b9, (q31_t)0xc6923bec, (q31_t)0x23b54c95, (q31_t)0xc697c8eb,
+    (q31_t)0x23aa0788, (q31_t)0xc69d5820, (q31_t)0x239ec393, (q31_t)0xc6a2e98b,
+    (q31_t)0x239380b6, (q31_t)0xc6a87d2d, (q31_t)0x23883ef2, (q31_t)0xc6ae1304,
+    (q31_t)0x237cfe47, (q31_t)0xc6b3ab12, (q31_t)0x2371beb5, (q31_t)0xc6b94554,
+    (q31_t)0x2366803c, (q31_t)0xc6bee1cd, (q31_t)0x235b42df, (q31_t)0xc6c4807a,
+    (q31_t)0x2350069b, (q31_t)0xc6ca215c, (q31_t)0x2344cb73, (q31_t)0xc6cfc472,
+    (q31_t)0x23399167, (q31_t)0xc6d569be, (q31_t)0x232e5876, (q31_t)0xc6db113d,
+    (q31_t)0x232320a2, (q31_t)0xc6e0baf0, (q31_t)0x2317e9eb, (q31_t)0xc6e666d7,
+    (q31_t)0x230cb451, (q31_t)0xc6ec14f2, (q31_t)0x23017fd5, (q31_t)0xc6f1c540,
+    (q31_t)0x22f64c77, (q31_t)0xc6f777c1, (q31_t)0x22eb1a37, (q31_t)0xc6fd2c75,
+    (q31_t)0x22dfe917, (q31_t)0xc702e35c, (q31_t)0x22d4b916, (q31_t)0xc7089c75,
+    (q31_t)0x22c98a35, (q31_t)0xc70e57c0, (q31_t)0x22be5c74, (q31_t)0xc714153e,
+    (q31_t)0x22b32fd4, (q31_t)0xc719d4ed, (q31_t)0x22a80456, (q31_t)0xc71f96ce,
+    (q31_t)0x229cd9f8, (q31_t)0xc7255ae0, (q31_t)0x2291b0bd, (q31_t)0xc72b2123,
+    (q31_t)0x228688a4, (q31_t)0xc730e997, (q31_t)0x227b61af, (q31_t)0xc736b43c,
+    (q31_t)0x22703bdc, (q31_t)0xc73c8111, (q31_t)0x2265172e, (q31_t)0xc7425016,
+    (q31_t)0x2259f3a3, (q31_t)0xc748214c, (q31_t)0x224ed13d, (q31_t)0xc74df4b1,
+    (q31_t)0x2243affc, (q31_t)0xc753ca46, (q31_t)0x22388fe1, (q31_t)0xc759a20a,
+    (q31_t)0x222d70eb, (q31_t)0xc75f7bfe, (q31_t)0x2222531c, (q31_t)0xc7655820,
+    (q31_t)0x22173674, (q31_t)0xc76b3671, (q31_t)0x220c1af3, (q31_t)0xc77116f0,
+    (q31_t)0x22010099, (q31_t)0xc776f99d, (q31_t)0x21f5e768, (q31_t)0xc77cde79,
+    (q31_t)0x21eacf5f, (q31_t)0xc782c582, (q31_t)0x21dfb87f, (q31_t)0xc788aeb9,
+    (q31_t)0x21d4a2c8, (q31_t)0xc78e9a1d, (q31_t)0x21c98e3b, (q31_t)0xc79487ae,
+    (q31_t)0x21be7ad8, (q31_t)0xc79a776c, (q31_t)0x21b368a0, (q31_t)0xc7a06957,
+    (q31_t)0x21a85793, (q31_t)0xc7a65d6e, (q31_t)0x219d47b1, (q31_t)0xc7ac53b1,
+    (q31_t)0x219238fb, (q31_t)0xc7b24c20, (q31_t)0x21872b72, (q31_t)0xc7b846ba,
+    (q31_t)0x217c1f15, (q31_t)0xc7be4381, (q31_t)0x217113e5, (q31_t)0xc7c44272,
+    (q31_t)0x216609e3, (q31_t)0xc7ca438f, (q31_t)0x215b0110, (q31_t)0xc7d046d6,
+    (q31_t)0x214ff96a, (q31_t)0xc7d64c47, (q31_t)0x2144f2f3, (q31_t)0xc7dc53e3,
+    (q31_t)0x2139edac, (q31_t)0xc7e25daa, (q31_t)0x212ee995, (q31_t)0xc7e8699a,
+    (q31_t)0x2123e6ad, (q31_t)0xc7ee77b3, (q31_t)0x2118e4f6, (q31_t)0xc7f487f6,
+    (q31_t)0x210de470, (q31_t)0xc7fa9a62, (q31_t)0x2102e51c, (q31_t)0xc800aef7,
+    (q31_t)0x20f7e6f9, (q31_t)0xc806c5b5, (q31_t)0x20ecea09, (q31_t)0xc80cde9b,
+    (q31_t)0x20e1ee4b, (q31_t)0xc812f9a9, (q31_t)0x20d6f3c1, (q31_t)0xc81916df,
+    (q31_t)0x20cbfa6a, (q31_t)0xc81f363d, (q31_t)0x20c10247, (q31_t)0xc82557c3,
+    (q31_t)0x20b60b58, (q31_t)0xc82b7b70, (q31_t)0x20ab159e, (q31_t)0xc831a143,
+    (q31_t)0x20a0211a, (q31_t)0xc837c93e, (q31_t)0x20952dcb, (q31_t)0xc83df35f,
+    (q31_t)0x208a3bb2, (q31_t)0xc8441fa6, (q31_t)0x207f4acf, (q31_t)0xc84a4e14,
+    (q31_t)0x20745b24, (q31_t)0xc8507ea7, (q31_t)0x20696cb0, (q31_t)0xc856b160,
+    (q31_t)0x205e7f74, (q31_t)0xc85ce63e, (q31_t)0x2053936f, (q31_t)0xc8631d42,
+    (q31_t)0x2048a8a4, (q31_t)0xc869566a, (q31_t)0x203dbf11, (q31_t)0xc86f91b7,
+    (q31_t)0x2032d6b8, (q31_t)0xc875cf28, (q31_t)0x2027ef99, (q31_t)0xc87c0ebd,
+    (q31_t)0x201d09b4, (q31_t)0xc8825077, (q31_t)0x2012250a, (q31_t)0xc8889454,
+    (q31_t)0x2007419b, (q31_t)0xc88eda54, (q31_t)0x1ffc5f67, (q31_t)0xc8952278,
+    (q31_t)0x1ff17e70, (q31_t)0xc89b6cbf, (q31_t)0x1fe69eb4, (q31_t)0xc8a1b928,
+    (q31_t)0x1fdbc036, (q31_t)0xc8a807b4, (q31_t)0x1fd0e2f5, (q31_t)0xc8ae5862,
+    (q31_t)0x1fc606f1, (q31_t)0xc8b4ab32, (q31_t)0x1fbb2c2c, (q31_t)0xc8bb0023,
+    (q31_t)0x1fb052a5, (q31_t)0xc8c15736, (q31_t)0x1fa57a5d, (q31_t)0xc8c7b06b,
+    (q31_t)0x1f9aa354, (q31_t)0xc8ce0bc0, (q31_t)0x1f8fcd8b, (q31_t)0xc8d46936,
+    (q31_t)0x1f84f902, (q31_t)0xc8dac8cd, (q31_t)0x1f7a25ba, (q31_t)0xc8e12a84,
+    (q31_t)0x1f6f53b3, (q31_t)0xc8e78e5b, (q31_t)0x1f6482ed, (q31_t)0xc8edf452,
+    (q31_t)0x1f59b369, (q31_t)0xc8f45c68, (q31_t)0x1f4ee527, (q31_t)0xc8fac69e,
+    (q31_t)0x1f441828, (q31_t)0xc90132f2, (q31_t)0x1f394c6b, (q31_t)0xc907a166,
+    (q31_t)0x1f2e81f3, (q31_t)0xc90e11f7, (q31_t)0x1f23b8be, (q31_t)0xc91484a8,
+    (q31_t)0x1f18f0ce, (q31_t)0xc91af976, (q31_t)0x1f0e2a22, (q31_t)0xc9217062,
+    (q31_t)0x1f0364bc, (q31_t)0xc927e96b, (q31_t)0x1ef8a09b, (q31_t)0xc92e6492,
+    (q31_t)0x1eedddc0, (q31_t)0xc934e1d6, (q31_t)0x1ee31c2b, (q31_t)0xc93b6137,
+    (q31_t)0x1ed85bdd, (q31_t)0xc941e2b4, (q31_t)0x1ecd9cd7, (q31_t)0xc948664d,
+    (q31_t)0x1ec2df18, (q31_t)0xc94eec03, (q31_t)0x1eb822a1, (q31_t)0xc95573d4,
+    (q31_t)0x1ead6773, (q31_t)0xc95bfdc1, (q31_t)0x1ea2ad8d, (q31_t)0xc96289c9,
+    (q31_t)0x1e97f4f1, (q31_t)0xc96917ec, (q31_t)0x1e8d3d9e, (q31_t)0xc96fa82a,
+    (q31_t)0x1e828796, (q31_t)0xc9763a83, (q31_t)0x1e77d2d8, (q31_t)0xc97ccef5,
+    (q31_t)0x1e6d1f65, (q31_t)0xc9836582, (q31_t)0x1e626d3e, (q31_t)0xc989fe29,
+    (q31_t)0x1e57bc62, (q31_t)0xc99098e9, (q31_t)0x1e4d0cd2, (q31_t)0xc99735c2,
+    (q31_t)0x1e425e8f, (q31_t)0xc99dd4b4, (q31_t)0x1e37b199, (q31_t)0xc9a475bf,
+    (q31_t)0x1e2d05f1, (q31_t)0xc9ab18e3, (q31_t)0x1e225b96, (q31_t)0xc9b1be1e,
+    (q31_t)0x1e17b28a, (q31_t)0xc9b86572, (q31_t)0x1e0d0acc, (q31_t)0xc9bf0edd,
+    (q31_t)0x1e02645d, (q31_t)0xc9c5ba60, (q31_t)0x1df7bf3e, (q31_t)0xc9cc67fa,
+    (q31_t)0x1ded1b6e, (q31_t)0xc9d317ab, (q31_t)0x1de278ef, (q31_t)0xc9d9c973,
+    (q31_t)0x1dd7d7c1, (q31_t)0xc9e07d51, (q31_t)0x1dcd37e4, (q31_t)0xc9e73346,
+    (q31_t)0x1dc29958, (q31_t)0xc9edeb50, (q31_t)0x1db7fc1e, (q31_t)0xc9f4a570,
+    (q31_t)0x1dad6036, (q31_t)0xc9fb61a5, (q31_t)0x1da2c5a2, (q31_t)0xca021fef,
+    (q31_t)0x1d982c60, (q31_t)0xca08e04f, (q31_t)0x1d8d9472, (q31_t)0xca0fa2c3,
+    (q31_t)0x1d82fdd8, (q31_t)0xca16674b, (q31_t)0x1d786892, (q31_t)0xca1d2de7,
+    (q31_t)0x1d6dd4a2, (q31_t)0xca23f698, (q31_t)0x1d634206, (q31_t)0xca2ac15b,
+    (q31_t)0x1d58b0c0, (q31_t)0xca318e32, (q31_t)0x1d4e20d0, (q31_t)0xca385d1d,
+    (q31_t)0x1d439236, (q31_t)0xca3f2e19, (q31_t)0x1d3904f4, (q31_t)0xca460129,
+    (q31_t)0x1d2e7908, (q31_t)0xca4cd64b, (q31_t)0x1d23ee74, (q31_t)0xca53ad7e,
+    (q31_t)0x1d196538, (q31_t)0xca5a86c4, (q31_t)0x1d0edd55, (q31_t)0xca61621b,
+    (q31_t)0x1d0456ca, (q31_t)0xca683f83, (q31_t)0x1cf9d199, (q31_t)0xca6f1efc,
+    (q31_t)0x1cef4dc2, (q31_t)0xca760086, (q31_t)0x1ce4cb44, (q31_t)0xca7ce420,
+    (q31_t)0x1cda4a21, (q31_t)0xca83c9ca, (q31_t)0x1ccfca59, (q31_t)0xca8ab184,
+    (q31_t)0x1cc54bec, (q31_t)0xca919b4e, (q31_t)0x1cbacedb, (q31_t)0xca988727,
+    (q31_t)0x1cb05326, (q31_t)0xca9f750f, (q31_t)0x1ca5d8cd, (q31_t)0xcaa66506,
+    (q31_t)0x1c9b5fd2, (q31_t)0xcaad570c, (q31_t)0x1c90e834, (q31_t)0xcab44b1f,
+    (q31_t)0x1c8671f3, (q31_t)0xcabb4141, (q31_t)0x1c7bfd11, (q31_t)0xcac23971,
+    (q31_t)0x1c71898d, (q31_t)0xcac933ae, (q31_t)0x1c671768, (q31_t)0xcad02ff8,
+    (q31_t)0x1c5ca6a2, (q31_t)0xcad72e4f, (q31_t)0x1c52373c, (q31_t)0xcade2eb3,
+    (q31_t)0x1c47c936, (q31_t)0xcae53123, (q31_t)0x1c3d5c91, (q31_t)0xcaec35a0,
+    (q31_t)0x1c32f14d, (q31_t)0xcaf33c28, (q31_t)0x1c28876a, (q31_t)0xcafa44bc,
+    (q31_t)0x1c1e1ee9, (q31_t)0xcb014f5b, (q31_t)0x1c13b7c9, (q31_t)0xcb085c05,
+    (q31_t)0x1c09520d, (q31_t)0xcb0f6aba, (q31_t)0x1bfeedb3, (q31_t)0xcb167b79,
+    (q31_t)0x1bf48abd, (q31_t)0xcb1d8e43, (q31_t)0x1bea292b, (q31_t)0xcb24a316,
+    (q31_t)0x1bdfc8fc, (q31_t)0xcb2bb9f4, (q31_t)0x1bd56a32, (q31_t)0xcb32d2da,
+    (q31_t)0x1bcb0cce, (q31_t)0xcb39edca, (q31_t)0x1bc0b0ce, (q31_t)0xcb410ac3,
+    (q31_t)0x1bb65634, (q31_t)0xcb4829c4, (q31_t)0x1babfd01, (q31_t)0xcb4f4acd,
+    (q31_t)0x1ba1a534, (q31_t)0xcb566ddf, (q31_t)0x1b974ece, (q31_t)0xcb5d92f8,
+    (q31_t)0x1b8cf9cf, (q31_t)0xcb64ba19, (q31_t)0x1b82a638, (q31_t)0xcb6be341,
+    (q31_t)0x1b785409, (q31_t)0xcb730e70, (q31_t)0x1b6e0342, (q31_t)0xcb7a3ba5,
+    (q31_t)0x1b63b3e5, (q31_t)0xcb816ae1, (q31_t)0x1b5965f1, (q31_t)0xcb889c23,
+    (q31_t)0x1b4f1967, (q31_t)0xcb8fcf6b, (q31_t)0x1b44ce46, (q31_t)0xcb9704b9,
+    (q31_t)0x1b3a8491, (q31_t)0xcb9e3c0b, (q31_t)0x1b303c46, (q31_t)0xcba57563,
+    (q31_t)0x1b25f566, (q31_t)0xcbacb0bf, (q31_t)0x1b1baff2, (q31_t)0xcbb3ee20,
+    (q31_t)0x1b116beb, (q31_t)0xcbbb2d85, (q31_t)0x1b072950, (q31_t)0xcbc26eee,
+    (q31_t)0x1afce821, (q31_t)0xcbc9b25a, (q31_t)0x1af2a860, (q31_t)0xcbd0f7ca,
+    (q31_t)0x1ae86a0d, (q31_t)0xcbd83f3d, (q31_t)0x1ade2d28, (q31_t)0xcbdf88b3,
+    (q31_t)0x1ad3f1b1, (q31_t)0xcbe6d42b, (q31_t)0x1ac9b7a9, (q31_t)0xcbee21a5,
+    (q31_t)0x1abf7f11, (q31_t)0xcbf57121, (q31_t)0x1ab547e8, (q31_t)0xcbfcc29f,
+    (q31_t)0x1aab122f, (q31_t)0xcc04161e, (q31_t)0x1aa0dde7, (q31_t)0xcc0b6b9e,
+    (q31_t)0x1a96ab0f, (q31_t)0xcc12c31f, (q31_t)0x1a8c79a9, (q31_t)0xcc1a1ca0,
+    (q31_t)0x1a8249b4, (q31_t)0xcc217822, (q31_t)0x1a781b31, (q31_t)0xcc28d5a3,
+    (q31_t)0x1a6dee21, (q31_t)0xcc303524, (q31_t)0x1a63c284, (q31_t)0xcc3796a5,
+    (q31_t)0x1a599859, (q31_t)0xcc3efa25, (q31_t)0x1a4f6fa3, (q31_t)0xcc465fa3,
+    (q31_t)0x1a454860, (q31_t)0xcc4dc720, (q31_t)0x1a3b2292, (q31_t)0xcc55309b,
+    (q31_t)0x1a30fe38, (q31_t)0xcc5c9c14, (q31_t)0x1a26db54, (q31_t)0xcc64098b,
+    (q31_t)0x1a1cb9e5, (q31_t)0xcc6b78ff, (q31_t)0x1a1299ec, (q31_t)0xcc72ea70,
+    (q31_t)0x1a087b69, (q31_t)0xcc7a5dde, (q31_t)0x19fe5e5e, (q31_t)0xcc81d349,
+    (q31_t)0x19f442c9, (q31_t)0xcc894aaf, (q31_t)0x19ea28ac, (q31_t)0xcc90c412,
+    (q31_t)0x19e01006, (q31_t)0xcc983f70, (q31_t)0x19d5f8d9, (q31_t)0xcc9fbcca,
+    (q31_t)0x19cbe325, (q31_t)0xcca73c1e, (q31_t)0x19c1cee9, (q31_t)0xccaebd6e,
+    (q31_t)0x19b7bc27, (q31_t)0xccb640b8, (q31_t)0x19adaadf, (q31_t)0xccbdc5fc,
+    (q31_t)0x19a39b11, (q31_t)0xccc54d3a, (q31_t)0x19998cbe, (q31_t)0xccccd671,
+    (q31_t)0x198f7fe6, (q31_t)0xccd461a2, (q31_t)0x19857489, (q31_t)0xccdbeecc,
+    (q31_t)0x197b6aa8, (q31_t)0xcce37def, (q31_t)0x19716243, (q31_t)0xcceb0f0a,
+    (q31_t)0x19675b5a, (q31_t)0xccf2a21d, (q31_t)0x195d55ef, (q31_t)0xccfa3729,
+    (q31_t)0x19535201, (q31_t)0xcd01ce2b, (q31_t)0x19494f90, (q31_t)0xcd096725,
+    (q31_t)0x193f4e9e, (q31_t)0xcd110216, (q31_t)0x19354f2a, (q31_t)0xcd189efe,
+    (q31_t)0x192b5135, (q31_t)0xcd203ddc, (q31_t)0x192154bf, (q31_t)0xcd27deb0,
+    (q31_t)0x191759c9, (q31_t)0xcd2f817b, (q31_t)0x190d6053, (q31_t)0xcd37263a,
+    (q31_t)0x1903685d, (q31_t)0xcd3eccef, (q31_t)0x18f971e8, (q31_t)0xcd467599,
+    (q31_t)0x18ef7cf4, (q31_t)0xcd4e2037, (q31_t)0x18e58982, (q31_t)0xcd55ccca,
+    (q31_t)0x18db9792, (q31_t)0xcd5d7b50, (q31_t)0x18d1a724, (q31_t)0xcd652bcb,
+    (q31_t)0x18c7b838, (q31_t)0xcd6cde39, (q31_t)0x18bdcad0, (q31_t)0xcd74929a,
+    (q31_t)0x18b3deeb, (q31_t)0xcd7c48ee, (q31_t)0x18a9f48a, (q31_t)0xcd840134,
+    (q31_t)0x18a00bae, (q31_t)0xcd8bbb6d, (q31_t)0x18962456, (q31_t)0xcd937798,
+    (q31_t)0x188c3e83, (q31_t)0xcd9b35b4, (q31_t)0x18825a35, (q31_t)0xcda2f5c2,
+    (q31_t)0x1878776d, (q31_t)0xcdaab7c0, (q31_t)0x186e962b, (q31_t)0xcdb27bb0,
+    (q31_t)0x1864b670, (q31_t)0xcdba4190, (q31_t)0x185ad83c, (q31_t)0xcdc20960,
+    (q31_t)0x1850fb8e, (q31_t)0xcdc9d320, (q31_t)0x18472069, (q31_t)0xcdd19ed0,
+    (q31_t)0x183d46cc, (q31_t)0xcdd96c6f, (q31_t)0x18336eb7, (q31_t)0xcde13bfd,
+    (q31_t)0x1829982b, (q31_t)0xcde90d79, (q31_t)0x181fc328, (q31_t)0xcdf0e0e4,
+    (q31_t)0x1815efae, (q31_t)0xcdf8b63d, (q31_t)0x180c1dbf, (q31_t)0xce008d84,
+    (q31_t)0x18024d59, (q31_t)0xce0866b8, (q31_t)0x17f87e7f, (q31_t)0xce1041d9,
+    (q31_t)0x17eeb130, (q31_t)0xce181ee8, (q31_t)0x17e4e56c, (q31_t)0xce1ffde2,
+    (q31_t)0x17db1b34, (q31_t)0xce27dec9, (q31_t)0x17d15288, (q31_t)0xce2fc19c,
+    (q31_t)0x17c78b68, (q31_t)0xce37a65b, (q31_t)0x17bdc5d6, (q31_t)0xce3f8d05,
+    (q31_t)0x17b401d1, (q31_t)0xce47759a, (q31_t)0x17aa3f5a, (q31_t)0xce4f6019,
+    (q31_t)0x17a07e70, (q31_t)0xce574c84, (q31_t)0x1796bf16, (q31_t)0xce5f3ad8,
+    (q31_t)0x178d014a, (q31_t)0xce672b16, (q31_t)0x1783450d, (q31_t)0xce6f1d3d,
+    (q31_t)0x17798a60, (q31_t)0xce77114e, (q31_t)0x176fd143, (q31_t)0xce7f0748,
+    (q31_t)0x176619b6, (q31_t)0xce86ff2a, (q31_t)0x175c63ba, (q31_t)0xce8ef8f4,
+    (q31_t)0x1752af4f, (q31_t)0xce96f4a7, (q31_t)0x1748fc75, (q31_t)0xce9ef241,
+    (q31_t)0x173f4b2e, (q31_t)0xcea6f1c2, (q31_t)0x17359b78, (q31_t)0xceaef32b,
+    (q31_t)0x172bed55, (q31_t)0xceb6f67a, (q31_t)0x172240c5, (q31_t)0xcebefbb0,
+    (q31_t)0x171895c9, (q31_t)0xcec702cb, (q31_t)0x170eec60, (q31_t)0xcecf0bcd,
+    (q31_t)0x1705448b, (q31_t)0xced716b4, (q31_t)0x16fb9e4b, (q31_t)0xcedf2380,
+    (q31_t)0x16f1f99f, (q31_t)0xcee73231, (q31_t)0x16e85689, (q31_t)0xceef42c7,
+    (q31_t)0x16deb508, (q31_t)0xcef75541, (q31_t)0x16d5151d, (q31_t)0xceff699f,
+    (q31_t)0x16cb76c9, (q31_t)0xcf077fe1, (q31_t)0x16c1da0b, (q31_t)0xcf0f9805,
+    (q31_t)0x16b83ee4, (q31_t)0xcf17b20d, (q31_t)0x16aea555, (q31_t)0xcf1fcdf8,
+    (q31_t)0x16a50d5d, (q31_t)0xcf27ebc5, (q31_t)0x169b76fe, (q31_t)0xcf300b74,
+    (q31_t)0x1691e237, (q31_t)0xcf382d05, (q31_t)0x16884f09, (q31_t)0xcf405077,
+    (q31_t)0x167ebd74, (q31_t)0xcf4875ca, (q31_t)0x16752d79, (q31_t)0xcf509cfe,
+    (q31_t)0x166b9f18, (q31_t)0xcf58c613, (q31_t)0x16621251, (q31_t)0xcf60f108,
+    (q31_t)0x16588725, (q31_t)0xcf691ddd, (q31_t)0x164efd94, (q31_t)0xcf714c91,
+    (q31_t)0x1645759f, (q31_t)0xcf797d24, (q31_t)0x163bef46, (q31_t)0xcf81af97,
+    (q31_t)0x16326a88, (q31_t)0xcf89e3e8, (q31_t)0x1628e767, (q31_t)0xcf921a17,
+    (q31_t)0x161f65e4, (q31_t)0xcf9a5225, (q31_t)0x1615e5fd, (q31_t)0xcfa28c10,
+    (q31_t)0x160c67b4, (q31_t)0xcfaac7d8, (q31_t)0x1602eb0a, (q31_t)0xcfb3057d,
+    (q31_t)0x15f96ffd, (q31_t)0xcfbb4500, (q31_t)0x15eff690, (q31_t)0xcfc3865e,
+    (q31_t)0x15e67ec1, (q31_t)0xcfcbc999, (q31_t)0x15dd0892, (q31_t)0xcfd40eaf,
+    (q31_t)0x15d39403, (q31_t)0xcfdc55a1, (q31_t)0x15ca2115, (q31_t)0xcfe49e6d,
+    (q31_t)0x15c0afc6, (q31_t)0xcfece915, (q31_t)0x15b74019, (q31_t)0xcff53597,
+    (q31_t)0x15add20d, (q31_t)0xcffd83f4, (q31_t)0x15a465a3, (q31_t)0xd005d42a,
+    (q31_t)0x159afadb, (q31_t)0xd00e2639, (q31_t)0x159191b5, (q31_t)0xd0167a22,
+    (q31_t)0x15882a32, (q31_t)0xd01ecfe4, (q31_t)0x157ec452, (q31_t)0xd027277e,
+    (q31_t)0x15756016, (q31_t)0xd02f80f1, (q31_t)0x156bfd7d, (q31_t)0xd037dc3b,
+    (q31_t)0x15629c89, (q31_t)0xd040395d, (q31_t)0x15593d3a, (q31_t)0xd0489856,
+    (q31_t)0x154fdf8f, (q31_t)0xd050f926, (q31_t)0x15468389, (q31_t)0xd0595bcd,
+    (q31_t)0x153d292a, (q31_t)0xd061c04a, (q31_t)0x1533d070, (q31_t)0xd06a269d,
+    (q31_t)0x152a795d, (q31_t)0xd0728ec6, (q31_t)0x152123f0, (q31_t)0xd07af8c4,
+    (q31_t)0x1517d02b, (q31_t)0xd0836497, (q31_t)0x150e7e0d, (q31_t)0xd08bd23f,
+    (q31_t)0x15052d97, (q31_t)0xd09441bb, (q31_t)0x14fbdec9, (q31_t)0xd09cb30b,
+    (q31_t)0x14f291a4, (q31_t)0xd0a5262f, (q31_t)0x14e94627, (q31_t)0xd0ad9b26,
+    (q31_t)0x14dffc54, (q31_t)0xd0b611f1, (q31_t)0x14d6b42b, (q31_t)0xd0be8a8d,
+    (q31_t)0x14cd6dab, (q31_t)0xd0c704fd, (q31_t)0x14c428d6, (q31_t)0xd0cf813e,
+    (q31_t)0x14bae5ab, (q31_t)0xd0d7ff51, (q31_t)0x14b1a42c, (q31_t)0xd0e07f36,
+    (q31_t)0x14a86458, (q31_t)0xd0e900ec, (q31_t)0x149f2630, (q31_t)0xd0f18472,
+    (q31_t)0x1495e9b3, (q31_t)0xd0fa09c9, (q31_t)0x148caee4, (q31_t)0xd10290f0,
+    (q31_t)0x148375c1, (q31_t)0xd10b19e7, (q31_t)0x147a3e4b, (q31_t)0xd113a4ad,
+    (q31_t)0x14710883, (q31_t)0xd11c3142, (q31_t)0x1467d469, (q31_t)0xd124bfa6,
+    (q31_t)0x145ea1fd, (q31_t)0xd12d4fd9, (q31_t)0x14557140, (q31_t)0xd135e1d9,
+    (q31_t)0x144c4232, (q31_t)0xd13e75a8, (q31_t)0x144314d3, (q31_t)0xd1470b44,
+    (q31_t)0x1439e923, (q31_t)0xd14fa2ad, (q31_t)0x1430bf24, (q31_t)0xd1583be2,
+    (q31_t)0x142796d5, (q31_t)0xd160d6e5, (q31_t)0x141e7037, (q31_t)0xd16973b3,
+    (q31_t)0x14154b4a, (q31_t)0xd172124d, (q31_t)0x140c280e, (q31_t)0xd17ab2b3,
+    (q31_t)0x14030684, (q31_t)0xd18354e4, (q31_t)0x13f9e6ad, (q31_t)0xd18bf8e0,
+    (q31_t)0x13f0c887, (q31_t)0xd1949ea6, (q31_t)0x13e7ac15, (q31_t)0xd19d4636,
+    (q31_t)0x13de9156, (q31_t)0xd1a5ef90, (q31_t)0x13d5784a, (q31_t)0xd1ae9ab4,
+    (q31_t)0x13cc60f2, (q31_t)0xd1b747a0, (q31_t)0x13c34b4f, (q31_t)0xd1bff656,
+    (q31_t)0x13ba3760, (q31_t)0xd1c8a6d4, (q31_t)0x13b12526, (q31_t)0xd1d1591a,
+    (q31_t)0x13a814a2, (q31_t)0xd1da0d28, (q31_t)0x139f05d3, (q31_t)0xd1e2c2fd,
+    (q31_t)0x1395f8ba, (q31_t)0xd1eb7a9a, (q31_t)0x138ced57, (q31_t)0xd1f433fd,
+    (q31_t)0x1383e3ab, (q31_t)0xd1fcef27, (q31_t)0x137adbb6, (q31_t)0xd205ac17,
+    (q31_t)0x1371d579, (q31_t)0xd20e6acc, (q31_t)0x1368d0f3, (q31_t)0xd2172b48,
+    (q31_t)0x135fce26, (q31_t)0xd21fed88, (q31_t)0x1356cd11, (q31_t)0xd228b18d,
+    (q31_t)0x134dcdb4, (q31_t)0xd2317756, (q31_t)0x1344d011, (q31_t)0xd23a3ee4,
+    (q31_t)0x133bd427, (q31_t)0xd2430835, (q31_t)0x1332d9f7, (q31_t)0xd24bd34a,
+    (q31_t)0x1329e181, (q31_t)0xd254a021, (q31_t)0x1320eac6, (q31_t)0xd25d6ebc,
+    (q31_t)0x1317f5c6, (q31_t)0xd2663f19, (q31_t)0x130f0280, (q31_t)0xd26f1138,
+    (q31_t)0x130610f7, (q31_t)0xd277e518, (q31_t)0x12fd2129, (q31_t)0xd280babb,
+    (q31_t)0x12f43318, (q31_t)0xd289921e, (q31_t)0x12eb46c3, (q31_t)0xd2926b41,
+    (q31_t)0x12e25c2b, (q31_t)0xd29b4626, (q31_t)0x12d97350, (q31_t)0xd2a422ca,
+    (q31_t)0x12d08c33, (q31_t)0xd2ad012e, (q31_t)0x12c7a6d4, (q31_t)0xd2b5e151,
+    (q31_t)0x12bec333, (q31_t)0xd2bec333, (q31_t)0x12b5e151, (q31_t)0xd2c7a6d4,
+    (q31_t)0x12ad012e, (q31_t)0xd2d08c33, (q31_t)0x12a422ca, (q31_t)0xd2d97350,
+    (q31_t)0x129b4626, (q31_t)0xd2e25c2b, (q31_t)0x12926b41, (q31_t)0xd2eb46c3,
+    (q31_t)0x1289921e, (q31_t)0xd2f43318, (q31_t)0x1280babb, (q31_t)0xd2fd2129,
+    (q31_t)0x1277e518, (q31_t)0xd30610f7, (q31_t)0x126f1138, (q31_t)0xd30f0280,
+    (q31_t)0x12663f19, (q31_t)0xd317f5c6, (q31_t)0x125d6ebc, (q31_t)0xd320eac6,
+    (q31_t)0x1254a021, (q31_t)0xd329e181, (q31_t)0x124bd34a, (q31_t)0xd332d9f7,
+    (q31_t)0x12430835, (q31_t)0xd33bd427, (q31_t)0x123a3ee4, (q31_t)0xd344d011,
+    (q31_t)0x12317756, (q31_t)0xd34dcdb4, (q31_t)0x1228b18d, (q31_t)0xd356cd11,
+    (q31_t)0x121fed88, (q31_t)0xd35fce26, (q31_t)0x12172b48, (q31_t)0xd368d0f3,
+    (q31_t)0x120e6acc, (q31_t)0xd371d579, (q31_t)0x1205ac17, (q31_t)0xd37adbb6,
+    (q31_t)0x11fcef27, (q31_t)0xd383e3ab, (q31_t)0x11f433fd, (q31_t)0xd38ced57,
+    (q31_t)0x11eb7a9a, (q31_t)0xd395f8ba, (q31_t)0x11e2c2fd, (q31_t)0xd39f05d3,
+    (q31_t)0x11da0d28, (q31_t)0xd3a814a2, (q31_t)0x11d1591a, (q31_t)0xd3b12526,
+    (q31_t)0x11c8a6d4, (q31_t)0xd3ba3760, (q31_t)0x11bff656, (q31_t)0xd3c34b4f,
+    (q31_t)0x11b747a0, (q31_t)0xd3cc60f2, (q31_t)0x11ae9ab4, (q31_t)0xd3d5784a,
+    (q31_t)0x11a5ef90, (q31_t)0xd3de9156, (q31_t)0x119d4636, (q31_t)0xd3e7ac15,
+    (q31_t)0x11949ea6, (q31_t)0xd3f0c887, (q31_t)0x118bf8e0, (q31_t)0xd3f9e6ad,
+    (q31_t)0x118354e4, (q31_t)0xd4030684, (q31_t)0x117ab2b3, (q31_t)0xd40c280e,
+    (q31_t)0x1172124d, (q31_t)0xd4154b4a, (q31_t)0x116973b3, (q31_t)0xd41e7037,
+    (q31_t)0x1160d6e5, (q31_t)0xd42796d5, (q31_t)0x11583be2, (q31_t)0xd430bf24,
+    (q31_t)0x114fa2ad, (q31_t)0xd439e923, (q31_t)0x11470b44, (q31_t)0xd44314d3,
+    (q31_t)0x113e75a8, (q31_t)0xd44c4232, (q31_t)0x1135e1d9, (q31_t)0xd4557140,
+    (q31_t)0x112d4fd9, (q31_t)0xd45ea1fd, (q31_t)0x1124bfa6, (q31_t)0xd467d469,
+    (q31_t)0x111c3142, (q31_t)0xd4710883, (q31_t)0x1113a4ad, (q31_t)0xd47a3e4b,
+    (q31_t)0x110b19e7, (q31_t)0xd48375c1, (q31_t)0x110290f0, (q31_t)0xd48caee4,
+    (q31_t)0x10fa09c9, (q31_t)0xd495e9b3, (q31_t)0x10f18472, (q31_t)0xd49f2630,
+    (q31_t)0x10e900ec, (q31_t)0xd4a86458, (q31_t)0x10e07f36, (q31_t)0xd4b1a42c,
+    (q31_t)0x10d7ff51, (q31_t)0xd4bae5ab, (q31_t)0x10cf813e, (q31_t)0xd4c428d6,
+    (q31_t)0x10c704fd, (q31_t)0xd4cd6dab, (q31_t)0x10be8a8d, (q31_t)0xd4d6b42b,
+    (q31_t)0x10b611f1, (q31_t)0xd4dffc54, (q31_t)0x10ad9b26, (q31_t)0xd4e94627,
+    (q31_t)0x10a5262f, (q31_t)0xd4f291a4, (q31_t)0x109cb30b, (q31_t)0xd4fbdec9,
+    (q31_t)0x109441bb, (q31_t)0xd5052d97, (q31_t)0x108bd23f, (q31_t)0xd50e7e0d,
+    (q31_t)0x10836497, (q31_t)0xd517d02b, (q31_t)0x107af8c4, (q31_t)0xd52123f0,
+    (q31_t)0x10728ec6, (q31_t)0xd52a795d, (q31_t)0x106a269d, (q31_t)0xd533d070,
+    (q31_t)0x1061c04a, (q31_t)0xd53d292a, (q31_t)0x10595bcd, (q31_t)0xd5468389,
+    (q31_t)0x1050f926, (q31_t)0xd54fdf8f, (q31_t)0x10489856, (q31_t)0xd5593d3a,
+    (q31_t)0x1040395d, (q31_t)0xd5629c89, (q31_t)0x1037dc3b, (q31_t)0xd56bfd7d,
+    (q31_t)0x102f80f1, (q31_t)0xd5756016, (q31_t)0x1027277e, (q31_t)0xd57ec452,
+    (q31_t)0x101ecfe4, (q31_t)0xd5882a32, (q31_t)0x10167a22, (q31_t)0xd59191b5,
+    (q31_t)0x100e2639, (q31_t)0xd59afadb, (q31_t)0x1005d42a, (q31_t)0xd5a465a3,
+    (q31_t)0xffd83f4, (q31_t)0xd5add20d, (q31_t)0xff53597, (q31_t)0xd5b74019,
+    (q31_t)0xfece915, (q31_t)0xd5c0afc6, (q31_t)0xfe49e6d, (q31_t)0xd5ca2115,
+    (q31_t)0xfdc55a1, (q31_t)0xd5d39403, (q31_t)0xfd40eaf, (q31_t)0xd5dd0892,
+    (q31_t)0xfcbc999, (q31_t)0xd5e67ec1, (q31_t)0xfc3865e, (q31_t)0xd5eff690,
+    (q31_t)0xfbb4500, (q31_t)0xd5f96ffd, (q31_t)0xfb3057d, (q31_t)0xd602eb0a,
+    (q31_t)0xfaac7d8, (q31_t)0xd60c67b4, (q31_t)0xfa28c10, (q31_t)0xd615e5fd,
+    (q31_t)0xf9a5225, (q31_t)0xd61f65e4, (q31_t)0xf921a17, (q31_t)0xd628e767,
+    (q31_t)0xf89e3e8, (q31_t)0xd6326a88, (q31_t)0xf81af97, (q31_t)0xd63bef46,
+    (q31_t)0xf797d24, (q31_t)0xd645759f, (q31_t)0xf714c91, (q31_t)0xd64efd94,
+    (q31_t)0xf691ddd, (q31_t)0xd6588725, (q31_t)0xf60f108, (q31_t)0xd6621251,
+    (q31_t)0xf58c613, (q31_t)0xd66b9f18, (q31_t)0xf509cfe, (q31_t)0xd6752d79,
+    (q31_t)0xf4875ca, (q31_t)0xd67ebd74, (q31_t)0xf405077, (q31_t)0xd6884f09,
+    (q31_t)0xf382d05, (q31_t)0xd691e237, (q31_t)0xf300b74, (q31_t)0xd69b76fe,
+    (q31_t)0xf27ebc5, (q31_t)0xd6a50d5d, (q31_t)0xf1fcdf8, (q31_t)0xd6aea555,
+    (q31_t)0xf17b20d, (q31_t)0xd6b83ee4, (q31_t)0xf0f9805, (q31_t)0xd6c1da0b,
+    (q31_t)0xf077fe1, (q31_t)0xd6cb76c9, (q31_t)0xeff699f, (q31_t)0xd6d5151d,
+    (q31_t)0xef75541, (q31_t)0xd6deb508, (q31_t)0xeef42c7, (q31_t)0xd6e85689,
+    (q31_t)0xee73231, (q31_t)0xd6f1f99f, (q31_t)0xedf2380, (q31_t)0xd6fb9e4b,
+    (q31_t)0xed716b4, (q31_t)0xd705448b, (q31_t)0xecf0bcd, (q31_t)0xd70eec60,
+    (q31_t)0xec702cb, (q31_t)0xd71895c9, (q31_t)0xebefbb0, (q31_t)0xd72240c5,
+    (q31_t)0xeb6f67a, (q31_t)0xd72bed55, (q31_t)0xeaef32b, (q31_t)0xd7359b78,
+    (q31_t)0xea6f1c2, (q31_t)0xd73f4b2e, (q31_t)0xe9ef241, (q31_t)0xd748fc75,
+    (q31_t)0xe96f4a7, (q31_t)0xd752af4f, (q31_t)0xe8ef8f4, (q31_t)0xd75c63ba,
+    (q31_t)0xe86ff2a, (q31_t)0xd76619b6, (q31_t)0xe7f0748, (q31_t)0xd76fd143,
+    (q31_t)0xe77114e, (q31_t)0xd7798a60, (q31_t)0xe6f1d3d, (q31_t)0xd783450d,
+    (q31_t)0xe672b16, (q31_t)0xd78d014a, (q31_t)0xe5f3ad8, (q31_t)0xd796bf16,
+    (q31_t)0xe574c84, (q31_t)0xd7a07e70, (q31_t)0xe4f6019, (q31_t)0xd7aa3f5a,
+    (q31_t)0xe47759a, (q31_t)0xd7b401d1, (q31_t)0xe3f8d05, (q31_t)0xd7bdc5d6,
+    (q31_t)0xe37a65b, (q31_t)0xd7c78b68, (q31_t)0xe2fc19c, (q31_t)0xd7d15288,
+    (q31_t)0xe27dec9, (q31_t)0xd7db1b34, (q31_t)0xe1ffde2, (q31_t)0xd7e4e56c,
+    (q31_t)0xe181ee8, (q31_t)0xd7eeb130, (q31_t)0xe1041d9, (q31_t)0xd7f87e7f,
+    (q31_t)0xe0866b8, (q31_t)0xd8024d59, (q31_t)0xe008d84, (q31_t)0xd80c1dbf,
+    (q31_t)0xdf8b63d, (q31_t)0xd815efae, (q31_t)0xdf0e0e4, (q31_t)0xd81fc328,
+    (q31_t)0xde90d79, (q31_t)0xd829982b, (q31_t)0xde13bfd, (q31_t)0xd8336eb7,
+    (q31_t)0xdd96c6f, (q31_t)0xd83d46cc, (q31_t)0xdd19ed0, (q31_t)0xd8472069,
+    (q31_t)0xdc9d320, (q31_t)0xd850fb8e, (q31_t)0xdc20960, (q31_t)0xd85ad83c,
+    (q31_t)0xdba4190, (q31_t)0xd864b670, (q31_t)0xdb27bb0, (q31_t)0xd86e962b,
+    (q31_t)0xdaab7c0, (q31_t)0xd878776d, (q31_t)0xda2f5c2, (q31_t)0xd8825a35,
+    (q31_t)0xd9b35b4, (q31_t)0xd88c3e83, (q31_t)0xd937798, (q31_t)0xd8962456,
+    (q31_t)0xd8bbb6d, (q31_t)0xd8a00bae, (q31_t)0xd840134, (q31_t)0xd8a9f48a,
+    (q31_t)0xd7c48ee, (q31_t)0xd8b3deeb, (q31_t)0xd74929a, (q31_t)0xd8bdcad0,
+    (q31_t)0xd6cde39, (q31_t)0xd8c7b838, (q31_t)0xd652bcb, (q31_t)0xd8d1a724,
+    (q31_t)0xd5d7b50, (q31_t)0xd8db9792, (q31_t)0xd55ccca, (q31_t)0xd8e58982,
+    (q31_t)0xd4e2037, (q31_t)0xd8ef7cf4, (q31_t)0xd467599, (q31_t)0xd8f971e8,
+    (q31_t)0xd3eccef, (q31_t)0xd903685d, (q31_t)0xd37263a, (q31_t)0xd90d6053,
+    (q31_t)0xd2f817b, (q31_t)0xd91759c9, (q31_t)0xd27deb0, (q31_t)0xd92154bf,
+    (q31_t)0xd203ddc, (q31_t)0xd92b5135, (q31_t)0xd189efe, (q31_t)0xd9354f2a,
+    (q31_t)0xd110216, (q31_t)0xd93f4e9e, (q31_t)0xd096725, (q31_t)0xd9494f90,
+    (q31_t)0xd01ce2b, (q31_t)0xd9535201, (q31_t)0xcfa3729, (q31_t)0xd95d55ef,
+    (q31_t)0xcf2a21d, (q31_t)0xd9675b5a, (q31_t)0xceb0f0a, (q31_t)0xd9716243,
+    (q31_t)0xce37def, (q31_t)0xd97b6aa8, (q31_t)0xcdbeecc, (q31_t)0xd9857489,
+    (q31_t)0xcd461a2, (q31_t)0xd98f7fe6, (q31_t)0xcccd671, (q31_t)0xd9998cbe,
+    (q31_t)0xcc54d3a, (q31_t)0xd9a39b11, (q31_t)0xcbdc5fc, (q31_t)0xd9adaadf,
+    (q31_t)0xcb640b8, (q31_t)0xd9b7bc27, (q31_t)0xcaebd6e, (q31_t)0xd9c1cee9,
+    (q31_t)0xca73c1e, (q31_t)0xd9cbe325, (q31_t)0xc9fbcca, (q31_t)0xd9d5f8d9,
+    (q31_t)0xc983f70, (q31_t)0xd9e01006, (q31_t)0xc90c412, (q31_t)0xd9ea28ac,
+    (q31_t)0xc894aaf, (q31_t)0xd9f442c9, (q31_t)0xc81d349, (q31_t)0xd9fe5e5e,
+    (q31_t)0xc7a5dde, (q31_t)0xda087b69, (q31_t)0xc72ea70, (q31_t)0xda1299ec,
+    (q31_t)0xc6b78ff, (q31_t)0xda1cb9e5, (q31_t)0xc64098b, (q31_t)0xda26db54,
+    (q31_t)0xc5c9c14, (q31_t)0xda30fe38, (q31_t)0xc55309b, (q31_t)0xda3b2292,
+    (q31_t)0xc4dc720, (q31_t)0xda454860, (q31_t)0xc465fa3, (q31_t)0xda4f6fa3,
+    (q31_t)0xc3efa25, (q31_t)0xda599859, (q31_t)0xc3796a5, (q31_t)0xda63c284,
+    (q31_t)0xc303524, (q31_t)0xda6dee21, (q31_t)0xc28d5a3, (q31_t)0xda781b31,
+    (q31_t)0xc217822, (q31_t)0xda8249b4, (q31_t)0xc1a1ca0, (q31_t)0xda8c79a9,
+    (q31_t)0xc12c31f, (q31_t)0xda96ab0f, (q31_t)0xc0b6b9e, (q31_t)0xdaa0dde7,
+    (q31_t)0xc04161e, (q31_t)0xdaab122f, (q31_t)0xbfcc29f, (q31_t)0xdab547e8,
+    (q31_t)0xbf57121, (q31_t)0xdabf7f11, (q31_t)0xbee21a5, (q31_t)0xdac9b7a9,
+    (q31_t)0xbe6d42b, (q31_t)0xdad3f1b1, (q31_t)0xbdf88b3, (q31_t)0xdade2d28,
+    (q31_t)0xbd83f3d, (q31_t)0xdae86a0d, (q31_t)0xbd0f7ca, (q31_t)0xdaf2a860,
+    (q31_t)0xbc9b25a, (q31_t)0xdafce821, (q31_t)0xbc26eee, (q31_t)0xdb072950,
+    (q31_t)0xbbb2d85, (q31_t)0xdb116beb, (q31_t)0xbb3ee20, (q31_t)0xdb1baff2,
+    (q31_t)0xbacb0bf, (q31_t)0xdb25f566, (q31_t)0xba57563, (q31_t)0xdb303c46,
+    (q31_t)0xb9e3c0b, (q31_t)0xdb3a8491, (q31_t)0xb9704b9, (q31_t)0xdb44ce46,
+    (q31_t)0xb8fcf6b, (q31_t)0xdb4f1967, (q31_t)0xb889c23, (q31_t)0xdb5965f1,
+    (q31_t)0xb816ae1, (q31_t)0xdb63b3e5, (q31_t)0xb7a3ba5, (q31_t)0xdb6e0342,
+    (q31_t)0xb730e70, (q31_t)0xdb785409, (q31_t)0xb6be341, (q31_t)0xdb82a638,
+    (q31_t)0xb64ba19, (q31_t)0xdb8cf9cf, (q31_t)0xb5d92f8, (q31_t)0xdb974ece,
+    (q31_t)0xb566ddf, (q31_t)0xdba1a534, (q31_t)0xb4f4acd, (q31_t)0xdbabfd01,
+    (q31_t)0xb4829c4, (q31_t)0xdbb65634, (q31_t)0xb410ac3, (q31_t)0xdbc0b0ce,
+    (q31_t)0xb39edca, (q31_t)0xdbcb0cce, (q31_t)0xb32d2da, (q31_t)0xdbd56a32,
+    (q31_t)0xb2bb9f4, (q31_t)0xdbdfc8fc, (q31_t)0xb24a316, (q31_t)0xdbea292b,
+    (q31_t)0xb1d8e43, (q31_t)0xdbf48abd, (q31_t)0xb167b79, (q31_t)0xdbfeedb3,
+    (q31_t)0xb0f6aba, (q31_t)0xdc09520d, (q31_t)0xb085c05, (q31_t)0xdc13b7c9,
+    (q31_t)0xb014f5b, (q31_t)0xdc1e1ee9, (q31_t)0xafa44bc, (q31_t)0xdc28876a,
+    (q31_t)0xaf33c28, (q31_t)0xdc32f14d, (q31_t)0xaec35a0, (q31_t)0xdc3d5c91,
+    (q31_t)0xae53123, (q31_t)0xdc47c936, (q31_t)0xade2eb3, (q31_t)0xdc52373c,
+    (q31_t)0xad72e4f, (q31_t)0xdc5ca6a2, (q31_t)0xad02ff8, (q31_t)0xdc671768,
+    (q31_t)0xac933ae, (q31_t)0xdc71898d, (q31_t)0xac23971, (q31_t)0xdc7bfd11,
+    (q31_t)0xabb4141, (q31_t)0xdc8671f3, (q31_t)0xab44b1f, (q31_t)0xdc90e834,
+    (q31_t)0xaad570c, (q31_t)0xdc9b5fd2, (q31_t)0xaa66506, (q31_t)0xdca5d8cd,
+    (q31_t)0xa9f750f, (q31_t)0xdcb05326, (q31_t)0xa988727, (q31_t)0xdcbacedb,
+    (q31_t)0xa919b4e, (q31_t)0xdcc54bec, (q31_t)0xa8ab184, (q31_t)0xdccfca59,
+    (q31_t)0xa83c9ca, (q31_t)0xdcda4a21, (q31_t)0xa7ce420, (q31_t)0xdce4cb44,
+    (q31_t)0xa760086, (q31_t)0xdcef4dc2, (q31_t)0xa6f1efc, (q31_t)0xdcf9d199,
+    (q31_t)0xa683f83, (q31_t)0xdd0456ca, (q31_t)0xa61621b, (q31_t)0xdd0edd55,
+    (q31_t)0xa5a86c4, (q31_t)0xdd196538, (q31_t)0xa53ad7e, (q31_t)0xdd23ee74,
+    (q31_t)0xa4cd64b, (q31_t)0xdd2e7908, (q31_t)0xa460129, (q31_t)0xdd3904f4,
+    (q31_t)0xa3f2e19, (q31_t)0xdd439236, (q31_t)0xa385d1d, (q31_t)0xdd4e20d0,
+    (q31_t)0xa318e32, (q31_t)0xdd58b0c0, (q31_t)0xa2ac15b, (q31_t)0xdd634206,
+    (q31_t)0xa23f698, (q31_t)0xdd6dd4a2, (q31_t)0xa1d2de7, (q31_t)0xdd786892,
+    (q31_t)0xa16674b, (q31_t)0xdd82fdd8, (q31_t)0xa0fa2c3, (q31_t)0xdd8d9472,
+    (q31_t)0xa08e04f, (q31_t)0xdd982c60, (q31_t)0xa021fef, (q31_t)0xdda2c5a2,
+    (q31_t)0x9fb61a5, (q31_t)0xddad6036, (q31_t)0x9f4a570, (q31_t)0xddb7fc1e,
+    (q31_t)0x9edeb50, (q31_t)0xddc29958, (q31_t)0x9e73346, (q31_t)0xddcd37e4,
+    (q31_t)0x9e07d51, (q31_t)0xddd7d7c1, (q31_t)0x9d9c973, (q31_t)0xdde278ef,
+    (q31_t)0x9d317ab, (q31_t)0xdded1b6e, (q31_t)0x9cc67fa, (q31_t)0xddf7bf3e,
+    (q31_t)0x9c5ba60, (q31_t)0xde02645d, (q31_t)0x9bf0edd, (q31_t)0xde0d0acc,
+    (q31_t)0x9b86572, (q31_t)0xde17b28a, (q31_t)0x9b1be1e, (q31_t)0xde225b96,
+    (q31_t)0x9ab18e3, (q31_t)0xde2d05f1, (q31_t)0x9a475bf, (q31_t)0xde37b199,
+    (q31_t)0x99dd4b4, (q31_t)0xde425e8f, (q31_t)0x99735c2, (q31_t)0xde4d0cd2,
+    (q31_t)0x99098e9, (q31_t)0xde57bc62, (q31_t)0x989fe29, (q31_t)0xde626d3e,
+    (q31_t)0x9836582, (q31_t)0xde6d1f65, (q31_t)0x97ccef5, (q31_t)0xde77d2d8,
+    (q31_t)0x9763a83, (q31_t)0xde828796, (q31_t)0x96fa82a, (q31_t)0xde8d3d9e,
+    (q31_t)0x96917ec, (q31_t)0xde97f4f1, (q31_t)0x96289c9, (q31_t)0xdea2ad8d,
+    (q31_t)0x95bfdc1, (q31_t)0xdead6773, (q31_t)0x95573d4, (q31_t)0xdeb822a1,
+    (q31_t)0x94eec03, (q31_t)0xdec2df18, (q31_t)0x948664d, (q31_t)0xdecd9cd7,
+    (q31_t)0x941e2b4, (q31_t)0xded85bdd, (q31_t)0x93b6137, (q31_t)0xdee31c2b,
+    (q31_t)0x934e1d6, (q31_t)0xdeedddc0, (q31_t)0x92e6492, (q31_t)0xdef8a09b,
+    (q31_t)0x927e96b, (q31_t)0xdf0364bc, (q31_t)0x9217062, (q31_t)0xdf0e2a22,
+    (q31_t)0x91af976, (q31_t)0xdf18f0ce, (q31_t)0x91484a8, (q31_t)0xdf23b8be,
+    (q31_t)0x90e11f7, (q31_t)0xdf2e81f3, (q31_t)0x907a166, (q31_t)0xdf394c6b,
+    (q31_t)0x90132f2, (q31_t)0xdf441828, (q31_t)0x8fac69e, (q31_t)0xdf4ee527,
+    (q31_t)0x8f45c68, (q31_t)0xdf59b369, (q31_t)0x8edf452, (q31_t)0xdf6482ed,
+    (q31_t)0x8e78e5b, (q31_t)0xdf6f53b3, (q31_t)0x8e12a84, (q31_t)0xdf7a25ba,
+    (q31_t)0x8dac8cd, (q31_t)0xdf84f902, (q31_t)0x8d46936, (q31_t)0xdf8fcd8b,
+    (q31_t)0x8ce0bc0, (q31_t)0xdf9aa354, (q31_t)0x8c7b06b, (q31_t)0xdfa57a5d,
+    (q31_t)0x8c15736, (q31_t)0xdfb052a5, (q31_t)0x8bb0023, (q31_t)0xdfbb2c2c,
+    (q31_t)0x8b4ab32, (q31_t)0xdfc606f1, (q31_t)0x8ae5862, (q31_t)0xdfd0e2f5,
+    (q31_t)0x8a807b4, (q31_t)0xdfdbc036, (q31_t)0x8a1b928, (q31_t)0xdfe69eb4,
+    (q31_t)0x89b6cbf, (q31_t)0xdff17e70, (q31_t)0x8952278, (q31_t)0xdffc5f67,
+    (q31_t)0x88eda54, (q31_t)0xe007419b, (q31_t)0x8889454, (q31_t)0xe012250a,
+    (q31_t)0x8825077, (q31_t)0xe01d09b4, (q31_t)0x87c0ebd, (q31_t)0xe027ef99,
+    (q31_t)0x875cf28, (q31_t)0xe032d6b8, (q31_t)0x86f91b7, (q31_t)0xe03dbf11,
+    (q31_t)0x869566a, (q31_t)0xe048a8a4, (q31_t)0x8631d42, (q31_t)0xe053936f,
+    (q31_t)0x85ce63e, (q31_t)0xe05e7f74, (q31_t)0x856b160, (q31_t)0xe0696cb0,
+    (q31_t)0x8507ea7, (q31_t)0xe0745b24, (q31_t)0x84a4e14, (q31_t)0xe07f4acf,
+    (q31_t)0x8441fa6, (q31_t)0xe08a3bb2, (q31_t)0x83df35f, (q31_t)0xe0952dcb,
+    (q31_t)0x837c93e, (q31_t)0xe0a0211a, (q31_t)0x831a143, (q31_t)0xe0ab159e,
+    (q31_t)0x82b7b70, (q31_t)0xe0b60b58, (q31_t)0x82557c3, (q31_t)0xe0c10247,
+    (q31_t)0x81f363d, (q31_t)0xe0cbfa6a, (q31_t)0x81916df, (q31_t)0xe0d6f3c1,
+    (q31_t)0x812f9a9, (q31_t)0xe0e1ee4b, (q31_t)0x80cde9b, (q31_t)0xe0ecea09,
+    (q31_t)0x806c5b5, (q31_t)0xe0f7e6f9, (q31_t)0x800aef7, (q31_t)0xe102e51c,
+    (q31_t)0x7fa9a62, (q31_t)0xe10de470, (q31_t)0x7f487f6, (q31_t)0xe118e4f6,
+    (q31_t)0x7ee77b3, (q31_t)0xe123e6ad, (q31_t)0x7e8699a, (q31_t)0xe12ee995,
+    (q31_t)0x7e25daa, (q31_t)0xe139edac, (q31_t)0x7dc53e3, (q31_t)0xe144f2f3,
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+    (q31_t)0x7be4381, (q31_t)0xe17c1f15, (q31_t)0x7b846ba, (q31_t)0xe1872b72,
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+    (q31_t)0x7a65d6e, (q31_t)0xe1a85793, (q31_t)0x7a06957, (q31_t)0xe1b368a0,
+    (q31_t)0x79a776c, (q31_t)0xe1be7ad8, (q31_t)0x79487ae, (q31_t)0xe1c98e3b,
+    (q31_t)0x78e9a1d, (q31_t)0xe1d4a2c8, (q31_t)0x788aeb9, (q31_t)0xe1dfb87f,
+    (q31_t)0x782c582, (q31_t)0xe1eacf5f, (q31_t)0x77cde79, (q31_t)0xe1f5e768,
+    (q31_t)0x776f99d, (q31_t)0xe2010099, (q31_t)0x77116f0, (q31_t)0xe20c1af3,
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+    (q31_t)0x3b54b11, (q31_t)0xea881114, (q31_t)0x3b1151b, (q31_t)0xea93e817,
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+    (q31_t)0x352bef9, (q31_t)0xeba519ad, (q31_t)0x34ec0fc, (q31_t)0xebb10404,
+    (q31_t)0x34ac556, (q31_t)0xebbcef23, (q31_t)0x346cc07, (q31_t)0xebc8db0b,
+    (q31_t)0x342d510, (q31_t)0xebd4c7ba, (q31_t)0x33ee070, (q31_t)0xebe0b52f,
+    (q31_t)0x33aee27, (q31_t)0xebeca36c, (q31_t)0x336fe37, (q31_t)0xebf8926f,
+    (q31_t)0x333109e, (q31_t)0xec048237, (q31_t)0x32f255e, (q31_t)0xec1072c4,
+    (q31_t)0x32b3c75, (q31_t)0xec1c6417, (q31_t)0x32755e5, (q31_t)0xec28562d,
+    (q31_t)0x32371ae, (q31_t)0xec344908, (q31_t)0x31f8fcf, (q31_t)0xec403ca5,
+    (q31_t)0x31bb049, (q31_t)0xec4c3106, (q31_t)0x317d31c, (q31_t)0xec582629,
+    (q31_t)0x313f848, (q31_t)0xec641c0e, (q31_t)0x3101fce, (q31_t)0xec7012b5,
+    (q31_t)0x30c49ad, (q31_t)0xec7c0a1d, (q31_t)0x30875e5, (q31_t)0xec880245,
+    (q31_t)0x304a477, (q31_t)0xec93fb2e, (q31_t)0x300d563, (q31_t)0xec9ff4d6,
+    (q31_t)0x2fd08a9, (q31_t)0xecabef3d, (q31_t)0x2f93e4a, (q31_t)0xecb7ea63,
+    (q31_t)0x2f57644, (q31_t)0xecc3e648, (q31_t)0x2f1b099, (q31_t)0xeccfe2ea,
+    (q31_t)0x2eded49, (q31_t)0xecdbe04a, (q31_t)0x2ea2c53, (q31_t)0xece7de66,
+    (q31_t)0x2e66db8, (q31_t)0xecf3dd3f, (q31_t)0x2e2b178, (q31_t)0xecffdcd4,
+    (q31_t)0x2def794, (q31_t)0xed0bdd25, (q31_t)0x2db400a, (q31_t)0xed17de31,
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+    (q31_t)0x2d02794, (q31_t)0xed3be5b1, (q31_t)0x2cc7979, (q31_t)0xed47e9a5,
+    (q31_t)0x2c8cdbb, (q31_t)0xed53ee51, (q31_t)0x2c52459, (q31_t)0xed5ff3b5,
+    (q31_t)0x2c17d52, (q31_t)0xed6bf9d1, (q31_t)0x2bdd8a9, (q31_t)0xed7800a5,
+    (q31_t)0x2ba365c, (q31_t)0xed84082f, (q31_t)0x2b6966c, (q31_t)0xed901070,
+    (q31_t)0x2b2f8d8, (q31_t)0xed9c1967, (q31_t)0x2af5da2, (q31_t)0xeda82313,
+    (q31_t)0x2abc4c9, (q31_t)0xedb42d74, (q31_t)0x2a82e4d, (q31_t)0xedc0388a,
+    (q31_t)0x2a49a2e, (q31_t)0xedcc4454, (q31_t)0x2a1086d, (q31_t)0xedd850d2,
+    (q31_t)0x29d790a, (q31_t)0xede45e03, (q31_t)0x299ec05, (q31_t)0xedf06be6,
+    (q31_t)0x296615d, (q31_t)0xedfc7a7c, (q31_t)0x292d914, (q31_t)0xee0889c4,
+    (q31_t)0x28f5329, (q31_t)0xee1499bd, (q31_t)0x28bcf9c, (q31_t)0xee20aa67,
+    (q31_t)0x2884e6e, (q31_t)0xee2cbbc1, (q31_t)0x284cf9f, (q31_t)0xee38cdcb,
+    (q31_t)0x281532e, (q31_t)0xee44e084, (q31_t)0x27dd91c, (q31_t)0xee50f3ed,
+    (q31_t)0x27a616a, (q31_t)0xee5d0804, (q31_t)0x276ec16, (q31_t)0xee691cc9,
+    (q31_t)0x2737922, (q31_t)0xee75323c, (q31_t)0x270088e, (q31_t)0xee81485c,
+    (q31_t)0x26c9a58, (q31_t)0xee8d5f29, (q31_t)0x2692e83, (q31_t)0xee9976a1,
+    (q31_t)0x265c50e, (q31_t)0xeea58ec6, (q31_t)0x2625df8, (q31_t)0xeeb1a796,
+    (q31_t)0x25ef943, (q31_t)0xeebdc110, (q31_t)0x25b96ee, (q31_t)0xeec9db35,
+    (q31_t)0x25836f9, (q31_t)0xeed5f604, (q31_t)0x254d965, (q31_t)0xeee2117c,
+    (q31_t)0x2517e31, (q31_t)0xeeee2d9d, (q31_t)0x24e255e, (q31_t)0xeefa4a67,
+    (q31_t)0x24aceed, (q31_t)0xef0667d9, (q31_t)0x2477adc, (q31_t)0xef1285f2,
+    (q31_t)0x244292c, (q31_t)0xef1ea4b2, (q31_t)0x240d9de, (q31_t)0xef2ac419,
+    (q31_t)0x23d8cf1, (q31_t)0xef36e426, (q31_t)0x23a4265, (q31_t)0xef4304d8,
+    (q31_t)0x236fa3b, (q31_t)0xef4f2630, (q31_t)0x233b473, (q31_t)0xef5b482d,
+    (q31_t)0x230710d, (q31_t)0xef676ace, (q31_t)0x22d3009, (q31_t)0xef738e12,
+    (q31_t)0x229f167, (q31_t)0xef7fb1fa, (q31_t)0x226b528, (q31_t)0xef8bd685,
+    (q31_t)0x2237b4b, (q31_t)0xef97fbb2, (q31_t)0x22043d0, (q31_t)0xefa42181,
+    (q31_t)0x21d0eb8, (q31_t)0xefb047f2, (q31_t)0x219dc03, (q31_t)0xefbc6f03,
+    (q31_t)0x216abb1, (q31_t)0xefc896b5, (q31_t)0x2137dc2, (q31_t)0xefd4bf08,
+    (q31_t)0x2105236, (q31_t)0xefe0e7f9, (q31_t)0x20d290d, (q31_t)0xefed118a,
+    (q31_t)0x20a0248, (q31_t)0xeff93bba, (q31_t)0x206dde6, (q31_t)0xf0056687,
+    (q31_t)0x203bbe8, (q31_t)0xf01191f3, (q31_t)0x2009c4e, (q31_t)0xf01dbdfb,
+    (q31_t)0x1fd7f17, (q31_t)0xf029eaa1, (q31_t)0x1fa6445, (q31_t)0xf03617e2,
+    (q31_t)0x1f74bd6, (q31_t)0xf04245c0, (q31_t)0x1f435cc, (q31_t)0xf04e7438,
+    (q31_t)0x1f12227, (q31_t)0xf05aa34c, (q31_t)0x1ee10e5, (q31_t)0xf066d2fa,
+    (q31_t)0x1eb0209, (q31_t)0xf0730342, (q31_t)0x1e7f591, (q31_t)0xf07f3424,
+    (q31_t)0x1e4eb7e, (q31_t)0xf08b659f, (q31_t)0x1e1e3d0, (q31_t)0xf09797b2,
+    (q31_t)0x1dede87, (q31_t)0xf0a3ca5d, (q31_t)0x1dbdba3, (q31_t)0xf0affda0,
+    (q31_t)0x1d8db25, (q31_t)0xf0bc317a, (q31_t)0x1d5dd0c, (q31_t)0xf0c865ea,
+    (q31_t)0x1d2e158, (q31_t)0xf0d49af1, (q31_t)0x1cfe80a, (q31_t)0xf0e0d08d,
+    (q31_t)0x1ccf122, (q31_t)0xf0ed06bf, (q31_t)0x1c9fca0, (q31_t)0xf0f93d86,
+    (q31_t)0x1c70a84, (q31_t)0xf10574e0, (q31_t)0x1c41ace, (q31_t)0xf111accf,
+    (q31_t)0x1c12d7e, (q31_t)0xf11de551, (q31_t)0x1be4294, (q31_t)0xf12a1e66,
+    (q31_t)0x1bb5a11, (q31_t)0xf136580d, (q31_t)0x1b873f5, (q31_t)0xf1429247,
+    (q31_t)0x1b5903f, (q31_t)0xf14ecd11, (q31_t)0x1b2aef0, (q31_t)0xf15b086d,
+    (q31_t)0x1afd007, (q31_t)0xf1674459, (q31_t)0x1acf386, (q31_t)0xf17380d6,
+    (q31_t)0x1aa196c, (q31_t)0xf17fbde2, (q31_t)0x1a741b9, (q31_t)0xf18bfb7d,
+    (q31_t)0x1a46c6e, (q31_t)0xf19839a6, (q31_t)0x1a1998a, (q31_t)0xf1a4785e,
+    (q31_t)0x19ec90d, (q31_t)0xf1b0b7a4, (q31_t)0x19bfaf9, (q31_t)0xf1bcf777,
+    (q31_t)0x1992f4c, (q31_t)0xf1c937d6, (q31_t)0x1966606, (q31_t)0xf1d578c2,
+    (q31_t)0x1939f29, (q31_t)0xf1e1ba3a, (q31_t)0x190dab4, (q31_t)0xf1edfc3d,
+    (q31_t)0x18e18a7, (q31_t)0xf1fa3ecb, (q31_t)0x18b5903, (q31_t)0xf20681e3,
+    (q31_t)0x1889bc6, (q31_t)0xf212c585, (q31_t)0x185e0f3, (q31_t)0xf21f09b1,
+    (q31_t)0x1832888, (q31_t)0xf22b4e66, (q31_t)0x1807285, (q31_t)0xf23793a3,
+    (q31_t)0x17dbeec, (q31_t)0xf243d968, (q31_t)0x17b0dbb, (q31_t)0xf2501fb5,
+    (q31_t)0x1785ef4, (q31_t)0xf25c6688, (q31_t)0x175b296, (q31_t)0xf268ade3,
+    (q31_t)0x17308a1, (q31_t)0xf274f5c3, (q31_t)0x1706115, (q31_t)0xf2813e2a,
+    (q31_t)0x16dbbf3, (q31_t)0xf28d8715, (q31_t)0x16b193a, (q31_t)0xf299d085,
+    (q31_t)0x16878eb, (q31_t)0xf2a61a7a, (q31_t)0x165db05, (q31_t)0xf2b264f2,
+    (q31_t)0x1633f8a, (q31_t)0xf2beafed, (q31_t)0x160a678, (q31_t)0xf2cafb6b,
+    (q31_t)0x15e0fd1, (q31_t)0xf2d7476c, (q31_t)0x15b7b94, (q31_t)0xf2e393ef,
+    (q31_t)0x158e9c1, (q31_t)0xf2efe0f2, (q31_t)0x1565a58, (q31_t)0xf2fc2e77,
+    (q31_t)0x153cd5a, (q31_t)0xf3087c7d, (q31_t)0x15142c6, (q31_t)0xf314cb02,
+    (q31_t)0x14eba9d, (q31_t)0xf3211a07, (q31_t)0x14c34df, (q31_t)0xf32d698a,
+    (q31_t)0x149b18b, (q31_t)0xf339b98d, (q31_t)0x14730a3, (q31_t)0xf3460a0d,
+    (q31_t)0x144b225, (q31_t)0xf3525b0b, (q31_t)0x1423613, (q31_t)0xf35eac86,
+    (q31_t)0x13fbc6c, (q31_t)0xf36afe7e, (q31_t)0x13d4530, (q31_t)0xf37750f2,
+    (q31_t)0x13ad060, (q31_t)0xf383a3e2, (q31_t)0x1385dfb, (q31_t)0xf38ff74d,
+    (q31_t)0x135ee02, (q31_t)0xf39c4b32, (q31_t)0x1338075, (q31_t)0xf3a89f92,
+    (q31_t)0x1311553, (q31_t)0xf3b4f46c, (q31_t)0x12eac9d, (q31_t)0xf3c149bf,
+    (q31_t)0x12c4653, (q31_t)0xf3cd9f8b, (q31_t)0x129e276, (q31_t)0xf3d9f5cf,
+    (q31_t)0x1278104, (q31_t)0xf3e64c8c, (q31_t)0x12521ff, (q31_t)0xf3f2a3bf,
+    (q31_t)0x122c566, (q31_t)0xf3fefb6a, (q31_t)0x1206b39, (q31_t)0xf40b538b,
+    (q31_t)0x11e1379, (q31_t)0xf417ac22, (q31_t)0x11bbe26, (q31_t)0xf424052f,
+    (q31_t)0x1196b3f, (q31_t)0xf4305eb0, (q31_t)0x1171ac6, (q31_t)0xf43cb8a7,
+    (q31_t)0x114ccb9, (q31_t)0xf4491311, (q31_t)0x1128119, (q31_t)0xf4556def,
+    (q31_t)0x11037e6, (q31_t)0xf461c940, (q31_t)0x10df120, (q31_t)0xf46e2504,
+    (q31_t)0x10bacc8, (q31_t)0xf47a8139, (q31_t)0x1096add, (q31_t)0xf486dde1,
+    (q31_t)0x1072b5f, (q31_t)0xf4933afa, (q31_t)0x104ee4f, (q31_t)0xf49f9884,
+    (q31_t)0x102b3ac, (q31_t)0xf4abf67e, (q31_t)0x1007b77, (q31_t)0xf4b854e7,
+    (q31_t)0xfe45b0, (q31_t)0xf4c4b3c0, (q31_t)0xfc1257, (q31_t)0xf4d11308,
+    (q31_t)0xf9e16b, (q31_t)0xf4dd72be, (q31_t)0xf7b2ee, (q31_t)0xf4e9d2e3,
+    (q31_t)0xf586df, (q31_t)0xf4f63374, (q31_t)0xf35d3e, (q31_t)0xf5029473,
+    (q31_t)0xf1360b, (q31_t)0xf50ef5de, (q31_t)0xef1147, (q31_t)0xf51b57b5,
+    (q31_t)0xeceef1, (q31_t)0xf527b9f7, (q31_t)0xeacf09, (q31_t)0xf5341ca5,
+    (q31_t)0xe8b190, (q31_t)0xf5407fbd, (q31_t)0xe69686, (q31_t)0xf54ce33f,
+    (q31_t)0xe47deb, (q31_t)0xf559472b, (q31_t)0xe267be, (q31_t)0xf565ab80,
+    (q31_t)0xe05401, (q31_t)0xf572103d, (q31_t)0xde42b2, (q31_t)0xf57e7563,
+    (q31_t)0xdc33d2, (q31_t)0xf58adaf0, (q31_t)0xda2762, (q31_t)0xf59740e5,
+    (q31_t)0xd81d61, (q31_t)0xf5a3a740, (q31_t)0xd615cf, (q31_t)0xf5b00e02,
+    (q31_t)0xd410ad, (q31_t)0xf5bc7529, (q31_t)0xd20dfa, (q31_t)0xf5c8dcb6,
+    (q31_t)0xd00db6, (q31_t)0xf5d544a7, (q31_t)0xce0fe3, (q31_t)0xf5e1acfd,
+    (q31_t)0xcc147f, (q31_t)0xf5ee15b7, (q31_t)0xca1b8a, (q31_t)0xf5fa7ed4,
+    (q31_t)0xc82506, (q31_t)0xf606e854, (q31_t)0xc630f2, (q31_t)0xf6135237,
+    (q31_t)0xc43f4d, (q31_t)0xf61fbc7b, (q31_t)0xc25019, (q31_t)0xf62c2721,
+    (q31_t)0xc06355, (q31_t)0xf6389228, (q31_t)0xbe7901, (q31_t)0xf644fd8f,
+    (q31_t)0xbc911d, (q31_t)0xf6516956, (q31_t)0xbaabaa, (q31_t)0xf65dd57d,
+    (q31_t)0xb8c8a7, (q31_t)0xf66a4203, (q31_t)0xb6e815, (q31_t)0xf676aee8,
+    (q31_t)0xb509f3, (q31_t)0xf6831c2b, (q31_t)0xb32e42, (q31_t)0xf68f89cb,
+    (q31_t)0xb15502, (q31_t)0xf69bf7c9, (q31_t)0xaf7e33, (q31_t)0xf6a86623,
+    (q31_t)0xada9d4, (q31_t)0xf6b4d4d9, (q31_t)0xabd7e6, (q31_t)0xf6c143ec,
+    (q31_t)0xaa086a, (q31_t)0xf6cdb359, (q31_t)0xa83b5e, (q31_t)0xf6da2321,
+    (q31_t)0xa670c4, (q31_t)0xf6e69344, (q31_t)0xa4a89b, (q31_t)0xf6f303c0,
+    (q31_t)0xa2e2e3, (q31_t)0xf6ff7496, (q31_t)0xa11f9d, (q31_t)0xf70be5c4,
+    (q31_t)0x9f5ec8, (q31_t)0xf718574b, (q31_t)0x9da065, (q31_t)0xf724c92a,
+    (q31_t)0x9be473, (q31_t)0xf7313b60, (q31_t)0x9a2af3, (q31_t)0xf73daded,
+    (q31_t)0x9873e4, (q31_t)0xf74a20d0, (q31_t)0x96bf48, (q31_t)0xf756940a,
+    (q31_t)0x950d1d, (q31_t)0xf7630799, (q31_t)0x935d64, (q31_t)0xf76f7b7d,
+    (q31_t)0x91b01d, (q31_t)0xf77befb5, (q31_t)0x900548, (q31_t)0xf7886442,
+    (q31_t)0x8e5ce5, (q31_t)0xf794d922, (q31_t)0x8cb6f5, (q31_t)0xf7a14e55,
+    (q31_t)0x8b1376, (q31_t)0xf7adc3db, (q31_t)0x89726a, (q31_t)0xf7ba39b3,
+    (q31_t)0x87d3d0, (q31_t)0xf7c6afdc, (q31_t)0x8637a9, (q31_t)0xf7d32657,
+    (q31_t)0x849df4, (q31_t)0xf7df9d22, (q31_t)0x8306b2, (q31_t)0xf7ec143e,
+    (q31_t)0x8171e2, (q31_t)0xf7f88ba9, (q31_t)0x7fdf85, (q31_t)0xf8050364,
+    (q31_t)0x7e4f9b, (q31_t)0xf8117b6d, (q31_t)0x7cc223, (q31_t)0xf81df3c5,
+    (q31_t)0x7b371e, (q31_t)0xf82a6c6a, (q31_t)0x79ae8c, (q31_t)0xf836e55d,
+    (q31_t)0x78286e, (q31_t)0xf8435e9d, (q31_t)0x76a4c2, (q31_t)0xf84fd829,
+    (q31_t)0x752389, (q31_t)0xf85c5201, (q31_t)0x73a4c3, (q31_t)0xf868cc24,
+    (q31_t)0x722871, (q31_t)0xf8754692, (q31_t)0x70ae92, (q31_t)0xf881c14b,
+    (q31_t)0x6f3726, (q31_t)0xf88e3c4d, (q31_t)0x6dc22e, (q31_t)0xf89ab799,
+    (q31_t)0x6c4fa8, (q31_t)0xf8a7332e, (q31_t)0x6adf97, (q31_t)0xf8b3af0c,
+    (q31_t)0x6971f9, (q31_t)0xf8c02b31, (q31_t)0x6806ce, (q31_t)0xf8cca79e,
+    (q31_t)0x669e18, (q31_t)0xf8d92452, (q31_t)0x6537d4, (q31_t)0xf8e5a14d,
+    (q31_t)0x63d405, (q31_t)0xf8f21e8e, (q31_t)0x6272aa, (q31_t)0xf8fe9c15,
+    (q31_t)0x6113c2, (q31_t)0xf90b19e0, (q31_t)0x5fb74e, (q31_t)0xf91797f0,
+    (q31_t)0x5e5d4e, (q31_t)0xf9241645, (q31_t)0x5d05c3, (q31_t)0xf93094dd,
+    (q31_t)0x5bb0ab, (q31_t)0xf93d13b8, (q31_t)0x5a5e07, (q31_t)0xf94992d7,
+    (q31_t)0x590dd8, (q31_t)0xf9561237, (q31_t)0x57c01d, (q31_t)0xf96291d9,
+    (q31_t)0x5674d6, (q31_t)0xf96f11bc, (q31_t)0x552c03, (q31_t)0xf97b91e1,
+    (q31_t)0x53e5a5, (q31_t)0xf9881245, (q31_t)0x52a1bb, (q31_t)0xf99492ea,
+    (q31_t)0x516045, (q31_t)0xf9a113cd, (q31_t)0x502145, (q31_t)0xf9ad94f0,
+    (q31_t)0x4ee4b8, (q31_t)0xf9ba1651, (q31_t)0x4daaa1, (q31_t)0xf9c697f0,
+    (q31_t)0x4c72fe, (q31_t)0xf9d319cc, (q31_t)0x4b3dcf, (q31_t)0xf9df9be6,
+    (q31_t)0x4a0b16, (q31_t)0xf9ec1e3b, (q31_t)0x48dad1, (q31_t)0xf9f8a0cd,
+    (q31_t)0x47ad01, (q31_t)0xfa05239a, (q31_t)0x4681a6, (q31_t)0xfa11a6a3,
+    (q31_t)0x4558c0, (q31_t)0xfa1e29e5, (q31_t)0x44324f, (q31_t)0xfa2aad62,
+    (q31_t)0x430e53, (q31_t)0xfa373119, (q31_t)0x41eccc, (q31_t)0xfa43b508,
+    (q31_t)0x40cdba, (q31_t)0xfa503930, (q31_t)0x3fb11d, (q31_t)0xfa5cbd91,
+    (q31_t)0x3e96f6, (q31_t)0xfa694229, (q31_t)0x3d7f44, (q31_t)0xfa75c6f8,
+    (q31_t)0x3c6a07, (q31_t)0xfa824bfd, (q31_t)0x3b573f, (q31_t)0xfa8ed139,
+    (q31_t)0x3a46ed, (q31_t)0xfa9b56ab, (q31_t)0x393910, (q31_t)0xfaa7dc52,
+    (q31_t)0x382da8, (q31_t)0xfab4622d, (q31_t)0x3724b6, (q31_t)0xfac0e83d,
+    (q31_t)0x361e3a, (q31_t)0xfacd6e81, (q31_t)0x351a33, (q31_t)0xfad9f4f8,
+    (q31_t)0x3418a2, (q31_t)0xfae67ba2, (q31_t)0x331986, (q31_t)0xfaf3027e,
+    (q31_t)0x321ce0, (q31_t)0xfaff898c, (q31_t)0x3122b0, (q31_t)0xfb0c10cb,
+    (q31_t)0x302af5, (q31_t)0xfb18983b, (q31_t)0x2f35b1, (q31_t)0xfb251fdc,
+    (q31_t)0x2e42e2, (q31_t)0xfb31a7ac, (q31_t)0x2d5289, (q31_t)0xfb3e2fac,
+    (q31_t)0x2c64a6, (q31_t)0xfb4ab7db, (q31_t)0x2b7939, (q31_t)0xfb574039,
+    (q31_t)0x2a9042, (q31_t)0xfb63c8c4, (q31_t)0x29a9c1, (q31_t)0xfb70517d,
+    (q31_t)0x28c5b6, (q31_t)0xfb7cda63, (q31_t)0x27e421, (q31_t)0xfb896375,
+    (q31_t)0x270502, (q31_t)0xfb95ecb4, (q31_t)0x262859, (q31_t)0xfba2761e,
+    (q31_t)0x254e27, (q31_t)0xfbaeffb3, (q31_t)0x24766a, (q31_t)0xfbbb8973,
+    (q31_t)0x23a124, (q31_t)0xfbc8135c, (q31_t)0x22ce54, (q31_t)0xfbd49d70,
+    (q31_t)0x21fdfb, (q31_t)0xfbe127ac, (q31_t)0x213018, (q31_t)0xfbedb212,
+    (q31_t)0x2064ab, (q31_t)0xfbfa3c9f, (q31_t)0x1f9bb5, (q31_t)0xfc06c754,
+    (q31_t)0x1ed535, (q31_t)0xfc135231, (q31_t)0x1e112b, (q31_t)0xfc1fdd34,
+    (q31_t)0x1d4f99, (q31_t)0xfc2c685d, (q31_t)0x1c907c, (q31_t)0xfc38f3ac,
+    (q31_t)0x1bd3d6, (q31_t)0xfc457f21, (q31_t)0x1b19a7, (q31_t)0xfc520aba,
+    (q31_t)0x1a61ee, (q31_t)0xfc5e9678, (q31_t)0x19acac, (q31_t)0xfc6b2259,
+    (q31_t)0x18f9e1, (q31_t)0xfc77ae5e, (q31_t)0x18498c, (q31_t)0xfc843a85,
+    (q31_t)0x179bae, (q31_t)0xfc90c6cf, (q31_t)0x16f047, (q31_t)0xfc9d533b,
+    (q31_t)0x164757, (q31_t)0xfca9dfc8, (q31_t)0x15a0dd, (q31_t)0xfcb66c77,
+    (q31_t)0x14fcda, (q31_t)0xfcc2f945, (q31_t)0x145b4e, (q31_t)0xfccf8634,
+    (q31_t)0x13bc39, (q31_t)0xfcdc1342, (q31_t)0x131f9b, (q31_t)0xfce8a06f,
+    (q31_t)0x128574, (q31_t)0xfcf52dbb, (q31_t)0x11edc3, (q31_t)0xfd01bb24,
+    (q31_t)0x11588a, (q31_t)0xfd0e48ab, (q31_t)0x10c5c7, (q31_t)0xfd1ad650,
+    (q31_t)0x10357c, (q31_t)0xfd276410, (q31_t)0xfa7a8, (q31_t)0xfd33f1ed,
+    (q31_t)0xf1c4a, (q31_t)0xfd407fe6, (q31_t)0xe9364, (q31_t)0xfd4d0df9,
+    (q31_t)0xe0cf5, (q31_t)0xfd599c28, (q31_t)0xd88fd, (q31_t)0xfd662a70,
+    (q31_t)0xd077c, (q31_t)0xfd72b8d2, (q31_t)0xc8872, (q31_t)0xfd7f474d,
+    (q31_t)0xc0be0, (q31_t)0xfd8bd5e1, (q31_t)0xb91c4, (q31_t)0xfd98648d,
+    (q31_t)0xb1a20, (q31_t)0xfda4f351, (q31_t)0xaa4f3, (q31_t)0xfdb1822c,
+    (q31_t)0xa323d, (q31_t)0xfdbe111e, (q31_t)0x9c1ff, (q31_t)0xfdcaa027,
+    (q31_t)0x95438, (q31_t)0xfdd72f45, (q31_t)0x8e8e8, (q31_t)0xfde3be78,
+    (q31_t)0x8800f, (q31_t)0xfdf04dc0, (q31_t)0x819ae, (q31_t)0xfdfcdd1d,
+    (q31_t)0x7b5c4, (q31_t)0xfe096c8d, (q31_t)0x75452, (q31_t)0xfe15fc11,
+    (q31_t)0x6f556, (q31_t)0xfe228ba7, (q31_t)0x698d3, (q31_t)0xfe2f1b50,
+    (q31_t)0x63ec6, (q31_t)0xfe3bab0b, (q31_t)0x5e731, (q31_t)0xfe483ad8,
+    (q31_t)0x59214, (q31_t)0xfe54cab5, (q31_t)0x53f6e, (q31_t)0xfe615aa3,
+    (q31_t)0x4ef3f, (q31_t)0xfe6deaa1, (q31_t)0x4a188, (q31_t)0xfe7a7aae,
+    (q31_t)0x45648, (q31_t)0xfe870aca, (q31_t)0x40d80, (q31_t)0xfe939af5,
+    (q31_t)0x3c72f, (q31_t)0xfea02b2e, (q31_t)0x38356, (q31_t)0xfeacbb74,
+    (q31_t)0x341f4, (q31_t)0xfeb94bc8, (q31_t)0x3030a, (q31_t)0xfec5dc28,
+    (q31_t)0x2c697, (q31_t)0xfed26c94, (q31_t)0x28c9c, (q31_t)0xfedefd0c,
+    (q31_t)0x25519, (q31_t)0xfeeb8d8f, (q31_t)0x2200d, (q31_t)0xfef81e1d,
+    (q31_t)0x1ed78, (q31_t)0xff04aeb5, (q31_t)0x1bd5c, (q31_t)0xff113f56,
+    (q31_t)0x18fb6, (q31_t)0xff1dd001, (q31_t)0x16489, (q31_t)0xff2a60b4,
+    (q31_t)0x13bd3, (q31_t)0xff36f170, (q31_t)0x11594, (q31_t)0xff438234,
+    (q31_t)0xf1ce, (q31_t)0xff5012fe, (q31_t)0xd07e, (q31_t)0xff5ca3d0,
+    (q31_t)0xb1a7, (q31_t)0xff6934a8, (q31_t)0x9547, (q31_t)0xff75c585,
+    (q31_t)0x7b5f, (q31_t)0xff825668, (q31_t)0x63ee, (q31_t)0xff8ee750,
+    (q31_t)0x4ef5, (q31_t)0xff9b783c, (q31_t)0x3c74, (q31_t)0xffa8092c,
+    (q31_t)0x2c6a, (q31_t)0xffb49a1f, (q31_t)0x1ed8, (q31_t)0xffc12b16,
+    (q31_t)0x13bd, (q31_t)0xffcdbc0f, (q31_t)0xb1a, (q31_t)0xffda4d09,
+    (q31_t)0x4ef, (q31_t)0xffe6de05, (q31_t)0x13c, (q31_t)0xfff36f02,
+    (q31_t)0x0, (q31_t)0x0, (q31_t)0x13c, (q31_t)0xc90fe,
+    (q31_t)0x4ef, (q31_t)0x1921fb, (q31_t)0xb1a, (q31_t)0x25b2f7,
+    (q31_t)0x13bd, (q31_t)0x3243f1, (q31_t)0x1ed8, (q31_t)0x3ed4ea,
+    (q31_t)0x2c6a, (q31_t)0x4b65e1, (q31_t)0x3c74, (q31_t)0x57f6d4,
+    (q31_t)0x4ef5, (q31_t)0x6487c4, (q31_t)0x63ee, (q31_t)0x7118b0,
+    (q31_t)0x7b5f, (q31_t)0x7da998, (q31_t)0x9547, (q31_t)0x8a3a7b,
+    (q31_t)0xb1a7, (q31_t)0x96cb58, (q31_t)0xd07e, (q31_t)0xa35c30,
+    (q31_t)0xf1ce, (q31_t)0xafed02, (q31_t)0x11594, (q31_t)0xbc7dcc,
+    (q31_t)0x13bd3, (q31_t)0xc90e90, (q31_t)0x16489, (q31_t)0xd59f4c,
+    (q31_t)0x18fb6, (q31_t)0xe22fff, (q31_t)0x1bd5c, (q31_t)0xeec0aa,
+    (q31_t)0x1ed78, (q31_t)0xfb514b, (q31_t)0x2200d, (q31_t)0x107e1e3,
+    (q31_t)0x25519, (q31_t)0x1147271, (q31_t)0x28c9c, (q31_t)0x12102f4,
+    (q31_t)0x2c697, (q31_t)0x12d936c, (q31_t)0x3030a, (q31_t)0x13a23d8,
+    (q31_t)0x341f4, (q31_t)0x146b438, (q31_t)0x38356, (q31_t)0x153448c,
+    (q31_t)0x3c72f, (q31_t)0x15fd4d2, (q31_t)0x40d80, (q31_t)0x16c650b,
+    (q31_t)0x45648, (q31_t)0x178f536, (q31_t)0x4a188, (q31_t)0x1858552,
+    (q31_t)0x4ef3f, (q31_t)0x192155f, (q31_t)0x53f6e, (q31_t)0x19ea55d,
+    (q31_t)0x59214, (q31_t)0x1ab354b, (q31_t)0x5e731, (q31_t)0x1b7c528,
+    (q31_t)0x63ec6, (q31_t)0x1c454f5, (q31_t)0x698d3, (q31_t)0x1d0e4b0,
+    (q31_t)0x6f556, (q31_t)0x1dd7459, (q31_t)0x75452, (q31_t)0x1ea03ef,
+    (q31_t)0x7b5c4, (q31_t)0x1f69373, (q31_t)0x819ae, (q31_t)0x20322e3,
+    (q31_t)0x8800f, (q31_t)0x20fb240, (q31_t)0x8e8e8, (q31_t)0x21c4188,
+    (q31_t)0x95438, (q31_t)0x228d0bb, (q31_t)0x9c1ff, (q31_t)0x2355fd9,
+    (q31_t)0xa323d, (q31_t)0x241eee2, (q31_t)0xaa4f3, (q31_t)0x24e7dd4,
+    (q31_t)0xb1a20, (q31_t)0x25b0caf, (q31_t)0xb91c4, (q31_t)0x2679b73,
+    (q31_t)0xc0be0, (q31_t)0x2742a1f, (q31_t)0xc8872, (q31_t)0x280b8b3,
+    (q31_t)0xd077c, (q31_t)0x28d472e, (q31_t)0xd88fd, (q31_t)0x299d590,
+    (q31_t)0xe0cf5, (q31_t)0x2a663d8, (q31_t)0xe9364, (q31_t)0x2b2f207,
+    (q31_t)0xf1c4a, (q31_t)0x2bf801a, (q31_t)0xfa7a8, (q31_t)0x2cc0e13,
+    (q31_t)0x10357c, (q31_t)0x2d89bf0, (q31_t)0x10c5c7, (q31_t)0x2e529b0,
+    (q31_t)0x11588a, (q31_t)0x2f1b755, (q31_t)0x11edc3, (q31_t)0x2fe44dc,
+    (q31_t)0x128574, (q31_t)0x30ad245, (q31_t)0x131f9b, (q31_t)0x3175f91,
+    (q31_t)0x13bc39, (q31_t)0x323ecbe, (q31_t)0x145b4e, (q31_t)0x33079cc,
+    (q31_t)0x14fcda, (q31_t)0x33d06bb, (q31_t)0x15a0dd, (q31_t)0x3499389,
+    (q31_t)0x164757, (q31_t)0x3562038, (q31_t)0x16f047, (q31_t)0x362acc5,
+    (q31_t)0x179bae, (q31_t)0x36f3931, (q31_t)0x18498c, (q31_t)0x37bc57b,
+    (q31_t)0x18f9e1, (q31_t)0x38851a2, (q31_t)0x19acac, (q31_t)0x394dda7,
+    (q31_t)0x1a61ee, (q31_t)0x3a16988, (q31_t)0x1b19a7, (q31_t)0x3adf546,
+    (q31_t)0x1bd3d6, (q31_t)0x3ba80df, (q31_t)0x1c907c, (q31_t)0x3c70c54,
+    (q31_t)0x1d4f99, (q31_t)0x3d397a3, (q31_t)0x1e112b, (q31_t)0x3e022cc,
+    (q31_t)0x1ed535, (q31_t)0x3ecadcf, (q31_t)0x1f9bb5, (q31_t)0x3f938ac,
+    (q31_t)0x2064ab, (q31_t)0x405c361, (q31_t)0x213018, (q31_t)0x4124dee,
+    (q31_t)0x21fdfb, (q31_t)0x41ed854, (q31_t)0x22ce54, (q31_t)0x42b6290,
+    (q31_t)0x23a124, (q31_t)0x437eca4, (q31_t)0x24766a, (q31_t)0x444768d,
+    (q31_t)0x254e27, (q31_t)0x451004d, (q31_t)0x262859, (q31_t)0x45d89e2,
+    (q31_t)0x270502, (q31_t)0x46a134c, (q31_t)0x27e421, (q31_t)0x4769c8b,
+    (q31_t)0x28c5b6, (q31_t)0x483259d, (q31_t)0x29a9c1, (q31_t)0x48fae83,
+    (q31_t)0x2a9042, (q31_t)0x49c373c, (q31_t)0x2b7939, (q31_t)0x4a8bfc7,
+    (q31_t)0x2c64a6, (q31_t)0x4b54825, (q31_t)0x2d5289, (q31_t)0x4c1d054,
+    (q31_t)0x2e42e2, (q31_t)0x4ce5854, (q31_t)0x2f35b1, (q31_t)0x4dae024,
+    (q31_t)0x302af5, (q31_t)0x4e767c5, (q31_t)0x3122b0, (q31_t)0x4f3ef35,
+    (q31_t)0x321ce0, (q31_t)0x5007674, (q31_t)0x331986, (q31_t)0x50cfd82,
+    (q31_t)0x3418a2, (q31_t)0x519845e, (q31_t)0x351a33, (q31_t)0x5260b08,
+    (q31_t)0x361e3a, (q31_t)0x532917f, (q31_t)0x3724b6, (q31_t)0x53f17c3,
+    (q31_t)0x382da8, (q31_t)0x54b9dd3, (q31_t)0x393910, (q31_t)0x55823ae,
+    (q31_t)0x3a46ed, (q31_t)0x564a955, (q31_t)0x3b573f, (q31_t)0x5712ec7,
+    (q31_t)0x3c6a07, (q31_t)0x57db403, (q31_t)0x3d7f44, (q31_t)0x58a3908,
+    (q31_t)0x3e96f6, (q31_t)0x596bdd7, (q31_t)0x3fb11d, (q31_t)0x5a3426f,
+    (q31_t)0x40cdba, (q31_t)0x5afc6d0, (q31_t)0x41eccc, (q31_t)0x5bc4af8,
+    (q31_t)0x430e53, (q31_t)0x5c8cee7, (q31_t)0x44324f, (q31_t)0x5d5529e,
+    (q31_t)0x4558c0, (q31_t)0x5e1d61b, (q31_t)0x4681a6, (q31_t)0x5ee595d,
+    (q31_t)0x47ad01, (q31_t)0x5fadc66, (q31_t)0x48dad1, (q31_t)0x6075f33,
+    (q31_t)0x4a0b16, (q31_t)0x613e1c5, (q31_t)0x4b3dcf, (q31_t)0x620641a,
+    (q31_t)0x4c72fe, (q31_t)0x62ce634, (q31_t)0x4daaa1, (q31_t)0x6396810,
+    (q31_t)0x4ee4b8, (q31_t)0x645e9af, (q31_t)0x502145, (q31_t)0x6526b10,
+    (q31_t)0x516045, (q31_t)0x65eec33, (q31_t)0x52a1bb, (q31_t)0x66b6d16,
+    (q31_t)0x53e5a5, (q31_t)0x677edbb, (q31_t)0x552c03, (q31_t)0x6846e1f,
+    (q31_t)0x5674d6, (q31_t)0x690ee44, (q31_t)0x57c01d, (q31_t)0x69d6e27,
+    (q31_t)0x590dd8, (q31_t)0x6a9edc9, (q31_t)0x5a5e07, (q31_t)0x6b66d29,
+    (q31_t)0x5bb0ab, (q31_t)0x6c2ec48, (q31_t)0x5d05c3, (q31_t)0x6cf6b23,
+    (q31_t)0x5e5d4e, (q31_t)0x6dbe9bb, (q31_t)0x5fb74e, (q31_t)0x6e86810,
+    (q31_t)0x6113c2, (q31_t)0x6f4e620, (q31_t)0x6272aa, (q31_t)0x70163eb,
+    (q31_t)0x63d405, (q31_t)0x70de172, (q31_t)0x6537d4, (q31_t)0x71a5eb3,
+    (q31_t)0x669e18, (q31_t)0x726dbae, (q31_t)0x6806ce, (q31_t)0x7335862,
+    (q31_t)0x6971f9, (q31_t)0x73fd4cf, (q31_t)0x6adf97, (q31_t)0x74c50f4,
+    (q31_t)0x6c4fa8, (q31_t)0x758ccd2, (q31_t)0x6dc22e, (q31_t)0x7654867,
+    (q31_t)0x6f3726, (q31_t)0x771c3b3, (q31_t)0x70ae92, (q31_t)0x77e3eb5,
+    (q31_t)0x722871, (q31_t)0x78ab96e, (q31_t)0x73a4c3, (q31_t)0x79733dc,
+    (q31_t)0x752389, (q31_t)0x7a3adff, (q31_t)0x76a4c2, (q31_t)0x7b027d7,
+    (q31_t)0x78286e, (q31_t)0x7bca163, (q31_t)0x79ae8c, (q31_t)0x7c91aa3,
+    (q31_t)0x7b371e, (q31_t)0x7d59396, (q31_t)0x7cc223, (q31_t)0x7e20c3b,
+    (q31_t)0x7e4f9b, (q31_t)0x7ee8493, (q31_t)0x7fdf85, (q31_t)0x7fafc9c,
+    (q31_t)0x8171e2, (q31_t)0x8077457, (q31_t)0x8306b2, (q31_t)0x813ebc2,
+    (q31_t)0x849df4, (q31_t)0x82062de, (q31_t)0x8637a9, (q31_t)0x82cd9a9,
+    (q31_t)0x87d3d0, (q31_t)0x8395024, (q31_t)0x89726a, (q31_t)0x845c64d,
+    (q31_t)0x8b1376, (q31_t)0x8523c25, (q31_t)0x8cb6f5, (q31_t)0x85eb1ab,
+    (q31_t)0x8e5ce5, (q31_t)0x86b26de, (q31_t)0x900548, (q31_t)0x8779bbe,
+    (q31_t)0x91b01d, (q31_t)0x884104b, (q31_t)0x935d64, (q31_t)0x8908483,
+    (q31_t)0x950d1d, (q31_t)0x89cf867, (q31_t)0x96bf48, (q31_t)0x8a96bf6,
+    (q31_t)0x9873e4, (q31_t)0x8b5df30, (q31_t)0x9a2af3, (q31_t)0x8c25213,
+    (q31_t)0x9be473, (q31_t)0x8cec4a0, (q31_t)0x9da065, (q31_t)0x8db36d6,
+    (q31_t)0x9f5ec8, (q31_t)0x8e7a8b5, (q31_t)0xa11f9d, (q31_t)0x8f41a3c,
+    (q31_t)0xa2e2e3, (q31_t)0x9008b6a, (q31_t)0xa4a89b, (q31_t)0x90cfc40,
+    (q31_t)0xa670c4, (q31_t)0x9196cbc, (q31_t)0xa83b5e, (q31_t)0x925dcdf,
+    (q31_t)0xaa086a, (q31_t)0x9324ca7, (q31_t)0xabd7e6, (q31_t)0x93ebc14,
+    (q31_t)0xada9d4, (q31_t)0x94b2b27, (q31_t)0xaf7e33, (q31_t)0x95799dd,
+    (q31_t)0xb15502, (q31_t)0x9640837, (q31_t)0xb32e42, (q31_t)0x9707635,
+    (q31_t)0xb509f3, (q31_t)0x97ce3d5, (q31_t)0xb6e815, (q31_t)0x9895118,
+    (q31_t)0xb8c8a7, (q31_t)0x995bdfd, (q31_t)0xbaabaa, (q31_t)0x9a22a83,
+    (q31_t)0xbc911d, (q31_t)0x9ae96aa, (q31_t)0xbe7901, (q31_t)0x9bb0271,
+    (q31_t)0xc06355, (q31_t)0x9c76dd8, (q31_t)0xc25019, (q31_t)0x9d3d8df,
+    (q31_t)0xc43f4d, (q31_t)0x9e04385, (q31_t)0xc630f2, (q31_t)0x9ecadc9,
+    (q31_t)0xc82506, (q31_t)0x9f917ac, (q31_t)0xca1b8a, (q31_t)0xa05812c,
+    (q31_t)0xcc147f, (q31_t)0xa11ea49, (q31_t)0xce0fe3, (q31_t)0xa1e5303,
+    (q31_t)0xd00db6, (q31_t)0xa2abb59, (q31_t)0xd20dfa, (q31_t)0xa37234a,
+    (q31_t)0xd410ad, (q31_t)0xa438ad7, (q31_t)0xd615cf, (q31_t)0xa4ff1fe,
+    (q31_t)0xd81d61, (q31_t)0xa5c58c0, (q31_t)0xda2762, (q31_t)0xa68bf1b,
+    (q31_t)0xdc33d2, (q31_t)0xa752510, (q31_t)0xde42b2, (q31_t)0xa818a9d,
+    (q31_t)0xe05401, (q31_t)0xa8defc3, (q31_t)0xe267be, (q31_t)0xa9a5480,
+    (q31_t)0xe47deb, (q31_t)0xaa6b8d5, (q31_t)0xe69686, (q31_t)0xab31cc1,
+    (q31_t)0xe8b190, (q31_t)0xabf8043, (q31_t)0xeacf09, (q31_t)0xacbe35b,
+    (q31_t)0xeceef1, (q31_t)0xad84609, (q31_t)0xef1147, (q31_t)0xae4a84b,
+    (q31_t)0xf1360b, (q31_t)0xaf10a22, (q31_t)0xf35d3e, (q31_t)0xafd6b8d,
+    (q31_t)0xf586df, (q31_t)0xb09cc8c, (q31_t)0xf7b2ee, (q31_t)0xb162d1d,
+    (q31_t)0xf9e16b, (q31_t)0xb228d42, (q31_t)0xfc1257, (q31_t)0xb2eecf8,
+    (q31_t)0xfe45b0, (q31_t)0xb3b4c40, (q31_t)0x1007b77, (q31_t)0xb47ab19,
+    (q31_t)0x102b3ac, (q31_t)0xb540982, (q31_t)0x104ee4f, (q31_t)0xb60677c,
+    (q31_t)0x1072b5f, (q31_t)0xb6cc506, (q31_t)0x1096add, (q31_t)0xb79221f,
+    (q31_t)0x10bacc8, (q31_t)0xb857ec7, (q31_t)0x10df120, (q31_t)0xb91dafc,
+    (q31_t)0x11037e6, (q31_t)0xb9e36c0, (q31_t)0x1128119, (q31_t)0xbaa9211,
+    (q31_t)0x114ccb9, (q31_t)0xbb6ecef, (q31_t)0x1171ac6, (q31_t)0xbc34759,
+    (q31_t)0x1196b3f, (q31_t)0xbcfa150, (q31_t)0x11bbe26, (q31_t)0xbdbfad1,
+    (q31_t)0x11e1379, (q31_t)0xbe853de, (q31_t)0x1206b39, (q31_t)0xbf4ac75,
+    (q31_t)0x122c566, (q31_t)0xc010496, (q31_t)0x12521ff, (q31_t)0xc0d5c41,
+    (q31_t)0x1278104, (q31_t)0xc19b374, (q31_t)0x129e276, (q31_t)0xc260a31,
+    (q31_t)0x12c4653, (q31_t)0xc326075, (q31_t)0x12eac9d, (q31_t)0xc3eb641,
+    (q31_t)0x1311553, (q31_t)0xc4b0b94, (q31_t)0x1338075, (q31_t)0xc57606e,
+    (q31_t)0x135ee02, (q31_t)0xc63b4ce, (q31_t)0x1385dfb, (q31_t)0xc7008b3,
+    (q31_t)0x13ad060, (q31_t)0xc7c5c1e, (q31_t)0x13d4530, (q31_t)0xc88af0e,
+    (q31_t)0x13fbc6c, (q31_t)0xc950182, (q31_t)0x1423613, (q31_t)0xca1537a,
+    (q31_t)0x144b225, (q31_t)0xcada4f5, (q31_t)0x14730a3, (q31_t)0xcb9f5f3,
+    (q31_t)0x149b18b, (q31_t)0xcc64673, (q31_t)0x14c34df, (q31_t)0xcd29676,
+    (q31_t)0x14eba9d, (q31_t)0xcdee5f9, (q31_t)0x15142c6, (q31_t)0xceb34fe,
+    (q31_t)0x153cd5a, (q31_t)0xcf78383, (q31_t)0x1565a58, (q31_t)0xd03d189,
+    (q31_t)0x158e9c1, (q31_t)0xd101f0e, (q31_t)0x15b7b94, (q31_t)0xd1c6c11,
+    (q31_t)0x15e0fd1, (q31_t)0xd28b894, (q31_t)0x160a678, (q31_t)0xd350495,
+    (q31_t)0x1633f8a, (q31_t)0xd415013, (q31_t)0x165db05, (q31_t)0xd4d9b0e,
+    (q31_t)0x16878eb, (q31_t)0xd59e586, (q31_t)0x16b193a, (q31_t)0xd662f7b,
+    (q31_t)0x16dbbf3, (q31_t)0xd7278eb, (q31_t)0x1706115, (q31_t)0xd7ec1d6,
+    (q31_t)0x17308a1, (q31_t)0xd8b0a3d, (q31_t)0x175b296, (q31_t)0xd97521d,
+    (q31_t)0x1785ef4, (q31_t)0xda39978, (q31_t)0x17b0dbb, (q31_t)0xdafe04b,
+    (q31_t)0x17dbeec, (q31_t)0xdbc2698, (q31_t)0x1807285, (q31_t)0xdc86c5d,
+    (q31_t)0x1832888, (q31_t)0xdd4b19a, (q31_t)0x185e0f3, (q31_t)0xde0f64f,
+    (q31_t)0x1889bc6, (q31_t)0xded3a7b, (q31_t)0x18b5903, (q31_t)0xdf97e1d,
+    (q31_t)0x18e18a7, (q31_t)0xe05c135, (q31_t)0x190dab4, (q31_t)0xe1203c3,
+    (q31_t)0x1939f29, (q31_t)0xe1e45c6, (q31_t)0x1966606, (q31_t)0xe2a873e,
+    (q31_t)0x1992f4c, (q31_t)0xe36c82a, (q31_t)0x19bfaf9, (q31_t)0xe430889,
+    (q31_t)0x19ec90d, (q31_t)0xe4f485c, (q31_t)0x1a1998a, (q31_t)0xe5b87a2,
+    (q31_t)0x1a46c6e, (q31_t)0xe67c65a, (q31_t)0x1a741b9, (q31_t)0xe740483,
+    (q31_t)0x1aa196c, (q31_t)0xe80421e, (q31_t)0x1acf386, (q31_t)0xe8c7f2a,
+    (q31_t)0x1afd007, (q31_t)0xe98bba7, (q31_t)0x1b2aef0, (q31_t)0xea4f793,
+    (q31_t)0x1b5903f, (q31_t)0xeb132ef, (q31_t)0x1b873f5, (q31_t)0xebd6db9,
+    (q31_t)0x1bb5a11, (q31_t)0xec9a7f3, (q31_t)0x1be4294, (q31_t)0xed5e19a,
+    (q31_t)0x1c12d7e, (q31_t)0xee21aaf, (q31_t)0x1c41ace, (q31_t)0xeee5331,
+    (q31_t)0x1c70a84, (q31_t)0xefa8b20, (q31_t)0x1c9fca0, (q31_t)0xf06c27a,
+    (q31_t)0x1ccf122, (q31_t)0xf12f941, (q31_t)0x1cfe80a, (q31_t)0xf1f2f73,
+    (q31_t)0x1d2e158, (q31_t)0xf2b650f, (q31_t)0x1d5dd0c, (q31_t)0xf379a16,
+    (q31_t)0x1d8db25, (q31_t)0xf43ce86, (q31_t)0x1dbdba3, (q31_t)0xf500260,
+    (q31_t)0x1dede87, (q31_t)0xf5c35a3, (q31_t)0x1e1e3d0, (q31_t)0xf68684e,
+    (q31_t)0x1e4eb7e, (q31_t)0xf749a61, (q31_t)0x1e7f591, (q31_t)0xf80cbdc,
+    (q31_t)0x1eb0209, (q31_t)0xf8cfcbe, (q31_t)0x1ee10e5, (q31_t)0xf992d06,
+    (q31_t)0x1f12227, (q31_t)0xfa55cb4, (q31_t)0x1f435cc, (q31_t)0xfb18bc8,
+    (q31_t)0x1f74bd6, (q31_t)0xfbdba40, (q31_t)0x1fa6445, (q31_t)0xfc9e81e,
+    (q31_t)0x1fd7f17, (q31_t)0xfd6155f, (q31_t)0x2009c4e, (q31_t)0xfe24205,
+    (q31_t)0x203bbe8, (q31_t)0xfee6e0d, (q31_t)0x206dde6, (q31_t)0xffa9979,
+    (q31_t)0x20a0248, (q31_t)0x1006c446, (q31_t)0x20d290d, (q31_t)0x1012ee76,
+    (q31_t)0x2105236, (q31_t)0x101f1807, (q31_t)0x2137dc2, (q31_t)0x102b40f8,
+    (q31_t)0x216abb1, (q31_t)0x1037694b, (q31_t)0x219dc03, (q31_t)0x104390fd,
+    (q31_t)0x21d0eb8, (q31_t)0x104fb80e, (q31_t)0x22043d0, (q31_t)0x105bde7f,
+    (q31_t)0x2237b4b, (q31_t)0x1068044e, (q31_t)0x226b528, (q31_t)0x1074297b,
+    (q31_t)0x229f167, (q31_t)0x10804e06, (q31_t)0x22d3009, (q31_t)0x108c71ee,
+    (q31_t)0x230710d, (q31_t)0x10989532, (q31_t)0x233b473, (q31_t)0x10a4b7d3,
+    (q31_t)0x236fa3b, (q31_t)0x10b0d9d0, (q31_t)0x23a4265, (q31_t)0x10bcfb28,
+    (q31_t)0x23d8cf1, (q31_t)0x10c91bda, (q31_t)0x240d9de, (q31_t)0x10d53be7,
+    (q31_t)0x244292c, (q31_t)0x10e15b4e, (q31_t)0x2477adc, (q31_t)0x10ed7a0e,
+    (q31_t)0x24aceed, (q31_t)0x10f99827, (q31_t)0x24e255e, (q31_t)0x1105b599,
+    (q31_t)0x2517e31, (q31_t)0x1111d263, (q31_t)0x254d965, (q31_t)0x111dee84,
+    (q31_t)0x25836f9, (q31_t)0x112a09fc, (q31_t)0x25b96ee, (q31_t)0x113624cb,
+    (q31_t)0x25ef943, (q31_t)0x11423ef0, (q31_t)0x2625df8, (q31_t)0x114e586a,
+    (q31_t)0x265c50e, (q31_t)0x115a713a, (q31_t)0x2692e83, (q31_t)0x1166895f,
+    (q31_t)0x26c9a58, (q31_t)0x1172a0d7, (q31_t)0x270088e, (q31_t)0x117eb7a4,
+    (q31_t)0x2737922, (q31_t)0x118acdc4, (q31_t)0x276ec16, (q31_t)0x1196e337,
+    (q31_t)0x27a616a, (q31_t)0x11a2f7fc, (q31_t)0x27dd91c, (q31_t)0x11af0c13,
+    (q31_t)0x281532e, (q31_t)0x11bb1f7c, (q31_t)0x284cf9f, (q31_t)0x11c73235,
+    (q31_t)0x2884e6e, (q31_t)0x11d3443f, (q31_t)0x28bcf9c, (q31_t)0x11df5599,
+    (q31_t)0x28f5329, (q31_t)0x11eb6643, (q31_t)0x292d914, (q31_t)0x11f7763c,
+    (q31_t)0x296615d, (q31_t)0x12038584, (q31_t)0x299ec05, (q31_t)0x120f941a,
+    (q31_t)0x29d790a, (q31_t)0x121ba1fd, (q31_t)0x2a1086d, (q31_t)0x1227af2e,
+    (q31_t)0x2a49a2e, (q31_t)0x1233bbac, (q31_t)0x2a82e4d, (q31_t)0x123fc776,
+    (q31_t)0x2abc4c9, (q31_t)0x124bd28c, (q31_t)0x2af5da2, (q31_t)0x1257dced,
+    (q31_t)0x2b2f8d8, (q31_t)0x1263e699, (q31_t)0x2b6966c, (q31_t)0x126fef90,
+    (q31_t)0x2ba365c, (q31_t)0x127bf7d1, (q31_t)0x2bdd8a9, (q31_t)0x1287ff5b,
+    (q31_t)0x2c17d52, (q31_t)0x1294062f, (q31_t)0x2c52459, (q31_t)0x12a00c4b,
+    (q31_t)0x2c8cdbb, (q31_t)0x12ac11af, (q31_t)0x2cc7979, (q31_t)0x12b8165b,
+    (q31_t)0x2d02794, (q31_t)0x12c41a4f, (q31_t)0x2d3d80a, (q31_t)0x12d01d89,
+    (q31_t)0x2d78add, (q31_t)0x12dc2009, (q31_t)0x2db400a, (q31_t)0x12e821cf,
+    (q31_t)0x2def794, (q31_t)0x12f422db, (q31_t)0x2e2b178, (q31_t)0x1300232c,
+    (q31_t)0x2e66db8, (q31_t)0x130c22c1, (q31_t)0x2ea2c53, (q31_t)0x1318219a,
+    (q31_t)0x2eded49, (q31_t)0x13241fb6, (q31_t)0x2f1b099, (q31_t)0x13301d16,
+    (q31_t)0x2f57644, (q31_t)0x133c19b8, (q31_t)0x2f93e4a, (q31_t)0x1348159d,
+    (q31_t)0x2fd08a9, (q31_t)0x135410c3, (q31_t)0x300d563, (q31_t)0x13600b2a,
+    (q31_t)0x304a477, (q31_t)0x136c04d2, (q31_t)0x30875e5, (q31_t)0x1377fdbb,
+    (q31_t)0x30c49ad, (q31_t)0x1383f5e3, (q31_t)0x3101fce, (q31_t)0x138fed4b,
+    (q31_t)0x313f848, (q31_t)0x139be3f2, (q31_t)0x317d31c, (q31_t)0x13a7d9d7,
+    (q31_t)0x31bb049, (q31_t)0x13b3cefa, (q31_t)0x31f8fcf, (q31_t)0x13bfc35b,
+    (q31_t)0x32371ae, (q31_t)0x13cbb6f8, (q31_t)0x32755e5, (q31_t)0x13d7a9d3,
+    (q31_t)0x32b3c75, (q31_t)0x13e39be9, (q31_t)0x32f255e, (q31_t)0x13ef8d3c,
+    (q31_t)0x333109e, (q31_t)0x13fb7dc9, (q31_t)0x336fe37, (q31_t)0x14076d91,
+    (q31_t)0x33aee27, (q31_t)0x14135c94, (q31_t)0x33ee070, (q31_t)0x141f4ad1,
+    (q31_t)0x342d510, (q31_t)0x142b3846, (q31_t)0x346cc07, (q31_t)0x143724f5,
+    (q31_t)0x34ac556, (q31_t)0x144310dd, (q31_t)0x34ec0fc, (q31_t)0x144efbfc,
+    (q31_t)0x352bef9, (q31_t)0x145ae653, (q31_t)0x356bf4d, (q31_t)0x1466cfe1,
+    (q31_t)0x35ac1f7, (q31_t)0x1472b8a5, (q31_t)0x35ec6f8, (q31_t)0x147ea0a0,
+    (q31_t)0x362ce50, (q31_t)0x148a87d1, (q31_t)0x366d7fd, (q31_t)0x14966e36,
+    (q31_t)0x36ae401, (q31_t)0x14a253d1, (q31_t)0x36ef25b, (q31_t)0x14ae38a0,
+    (q31_t)0x373030a, (q31_t)0x14ba1ca3, (q31_t)0x377160f, (q31_t)0x14c5ffd9,
+    (q31_t)0x37b2b6a, (q31_t)0x14d1e242, (q31_t)0x37f4319, (q31_t)0x14ddc3de,
+    (q31_t)0x3835d1e, (q31_t)0x14e9a4ac, (q31_t)0x3877978, (q31_t)0x14f584ac,
+    (q31_t)0x38b9827, (q31_t)0x150163dc, (q31_t)0x38fb92a, (q31_t)0x150d423d,
+    (q31_t)0x393dc82, (q31_t)0x15191fcf, (q31_t)0x398022f, (q31_t)0x1524fc90,
+    (q31_t)0x39c2a2f, (q31_t)0x1530d881, (q31_t)0x3a05484, (q31_t)0x153cb3a0,
+    (q31_t)0x3a4812c, (q31_t)0x15488dee, (q31_t)0x3a8b028, (q31_t)0x1554676a,
+    (q31_t)0x3ace178, (q31_t)0x15604013, (q31_t)0x3b1151b, (q31_t)0x156c17e9,
+    (q31_t)0x3b54b11, (q31_t)0x1577eeec, (q31_t)0x3b9835a, (q31_t)0x1583c51b,
+    (q31_t)0x3bdbdf6, (q31_t)0x158f9a76, (q31_t)0x3c1fae5, (q31_t)0x159b6efb,
+    (q31_t)0x3c63a26, (q31_t)0x15a742ac, (q31_t)0x3ca7bba, (q31_t)0x15b31587,
+    (q31_t)0x3cebfa0, (q31_t)0x15bee78c, (q31_t)0x3d305d8, (q31_t)0x15cab8ba,
+    (q31_t)0x3d74e62, (q31_t)0x15d68911, (q31_t)0x3db993e, (q31_t)0x15e25890,
+    (q31_t)0x3dfe66c, (q31_t)0x15ee2738, (q31_t)0x3e435ea, (q31_t)0x15f9f507,
+    (q31_t)0x3e887bb, (q31_t)0x1605c1fd, (q31_t)0x3ecdbdc, (q31_t)0x16118e1a,
+    (q31_t)0x3f1324e, (q31_t)0x161d595d, (q31_t)0x3f58b10, (q31_t)0x162923c5,
+    (q31_t)0x3f9e624, (q31_t)0x1634ed53, (q31_t)0x3fe4388, (q31_t)0x1640b606,
+    (q31_t)0x402a33c, (q31_t)0x164c7ddd, (q31_t)0x4070540, (q31_t)0x165844d8,
+    (q31_t)0x40b6994, (q31_t)0x16640af7, (q31_t)0x40fd037, (q31_t)0x166fd039,
+    (q31_t)0x414392b, (q31_t)0x167b949d, (q31_t)0x418a46d, (q31_t)0x16875823,
+    (q31_t)0x41d11ff, (q31_t)0x16931acb, (q31_t)0x42181e0, (q31_t)0x169edc94,
+    (q31_t)0x425f410, (q31_t)0x16aa9d7e, (q31_t)0x42a688f, (q31_t)0x16b65d88,
+    (q31_t)0x42edf5c, (q31_t)0x16c21cb2, (q31_t)0x4335877, (q31_t)0x16cddafb,
+    (q31_t)0x437d3e1, (q31_t)0x16d99864, (q31_t)0x43c5199, (q31_t)0x16e554ea,
+    (q31_t)0x440d19e, (q31_t)0x16f1108f, (q31_t)0x44553f2, (q31_t)0x16fccb51,
+    (q31_t)0x449d892, (q31_t)0x17088531, (q31_t)0x44e5f80, (q31_t)0x17143e2d,
+    (q31_t)0x452e8bc, (q31_t)0x171ff646, (q31_t)0x4577444, (q31_t)0x172bad7a,
+    (q31_t)0x45c0219, (q31_t)0x173763c9, (q31_t)0x460923b, (q31_t)0x17431933,
+    (q31_t)0x46524a9, (q31_t)0x174ecdb8, (q31_t)0x469b963, (q31_t)0x175a8157,
+    (q31_t)0x46e5069, (q31_t)0x1766340f, (q31_t)0x472e9bc, (q31_t)0x1771e5e0,
+    (q31_t)0x477855a, (q31_t)0x177d96ca, (q31_t)0x47c2344, (q31_t)0x178946cc,
+    (q31_t)0x480c379, (q31_t)0x1794f5e6, (q31_t)0x48565f9, (q31_t)0x17a0a417,
+    (q31_t)0x48a0ac4, (q31_t)0x17ac515f, (q31_t)0x48eb1db, (q31_t)0x17b7fdbd,
+    (q31_t)0x4935b3c, (q31_t)0x17c3a931, (q31_t)0x49806e7, (q31_t)0x17cf53bb,
+    (q31_t)0x49cb4dd, (q31_t)0x17dafd59, (q31_t)0x4a1651c, (q31_t)0x17e6a60c,
+    (q31_t)0x4a617a6, (q31_t)0x17f24dd3, (q31_t)0x4aacc7a, (q31_t)0x17fdf4ae,
+    (q31_t)0x4af8397, (q31_t)0x18099a9c, (q31_t)0x4b43cfd, (q31_t)0x18153f9d,
+    (q31_t)0x4b8f8ad, (q31_t)0x1820e3b0, (q31_t)0x4bdb6a6, (q31_t)0x182c86d5,
+    (q31_t)0x4c276e8, (q31_t)0x1838290c, (q31_t)0x4c73972, (q31_t)0x1843ca53,
+    (q31_t)0x4cbfe45, (q31_t)0x184f6aab, (q31_t)0x4d0c560, (q31_t)0x185b0a13,
+    (q31_t)0x4d58ec3, (q31_t)0x1866a88a, (q31_t)0x4da5a6f, (q31_t)0x18724611,
+    (q31_t)0x4df2862, (q31_t)0x187de2a7, (q31_t)0x4e3f89c, (q31_t)0x18897e4a,
+    (q31_t)0x4e8cb1e, (q31_t)0x189518fc, (q31_t)0x4ed9fe7, (q31_t)0x18a0b2bb,
+    (q31_t)0x4f276f7, (q31_t)0x18ac4b87, (q31_t)0x4f7504e, (q31_t)0x18b7e35f,
+    (q31_t)0x4fc2bec, (q31_t)0x18c37a44, (q31_t)0x50109d0, (q31_t)0x18cf1034,
+    (q31_t)0x505e9fb, (q31_t)0x18daa52f, (q31_t)0x50acc6b, (q31_t)0x18e63935,
+    (q31_t)0x50fb121, (q31_t)0x18f1cc45, (q31_t)0x514981d, (q31_t)0x18fd5e5f,
+    (q31_t)0x519815f, (q31_t)0x1908ef82, (q31_t)0x51e6ce6, (q31_t)0x19147fae,
+    (q31_t)0x5235ab2, (q31_t)0x19200ee3, (q31_t)0x5284ac3, (q31_t)0x192b9d1f,
+    (q31_t)0x52d3d18, (q31_t)0x19372a64, (q31_t)0x53231b3, (q31_t)0x1942b6af,
+    (q31_t)0x5372891, (q31_t)0x194e4201, (q31_t)0x53c21b4, (q31_t)0x1959cc5a,
+    (q31_t)0x5411d1b, (q31_t)0x196555b8, (q31_t)0x5461ac6, (q31_t)0x1970de1b,
+    (q31_t)0x54b1ab4, (q31_t)0x197c6584, (q31_t)0x5501ce5, (q31_t)0x1987ebf0,
+    (q31_t)0x555215a, (q31_t)0x19937161, (q31_t)0x55a2812, (q31_t)0x199ef5d6,
+    (q31_t)0x55f310d, (q31_t)0x19aa794d, (q31_t)0x5643c4a, (q31_t)0x19b5fbc8,
+    (q31_t)0x56949ca, (q31_t)0x19c17d44, (q31_t)0x56e598c, (q31_t)0x19ccfdc2,
+    (q31_t)0x5736b90, (q31_t)0x19d87d42, (q31_t)0x5787fd6, (q31_t)0x19e3fbc3,
+    (q31_t)0x57d965d, (q31_t)0x19ef7944, (q31_t)0x582af26, (q31_t)0x19faf5c5,
+    (q31_t)0x587ca31, (q31_t)0x1a067145, (q31_t)0x58ce77c, (q31_t)0x1a11ebc5,
+    (q31_t)0x5920708, (q31_t)0x1a1d6544, (q31_t)0x59728d5, (q31_t)0x1a28ddc0,
+    (q31_t)0x59c4ce3, (q31_t)0x1a34553b, (q31_t)0x5a17330, (q31_t)0x1a3fcbb3,
+    (q31_t)0x5a69bbe, (q31_t)0x1a4b4128, (q31_t)0x5abc68c, (q31_t)0x1a56b599,
+    (q31_t)0x5b0f399, (q31_t)0x1a622907, (q31_t)0x5b622e6, (q31_t)0x1a6d9b70,
+    (q31_t)0x5bb5472, (q31_t)0x1a790cd4, (q31_t)0x5c0883d, (q31_t)0x1a847d33,
+    (q31_t)0x5c5be47, (q31_t)0x1a8fec8c, (q31_t)0x5caf690, (q31_t)0x1a9b5adf,
+    (q31_t)0x5d03118, (q31_t)0x1aa6c82b, (q31_t)0x5d56ddd, (q31_t)0x1ab23471,
+    (q31_t)0x5daace1, (q31_t)0x1abd9faf, (q31_t)0x5dfee22, (q31_t)0x1ac909e5,
+    (q31_t)0x5e531a1, (q31_t)0x1ad47312, (q31_t)0x5ea775e, (q31_t)0x1adfdb37,
+    (q31_t)0x5efbf58, (q31_t)0x1aeb4253, (q31_t)0x5f5098f, (q31_t)0x1af6a865,
+    (q31_t)0x5fa5603, (q31_t)0x1b020d6c, (q31_t)0x5ffa4b3, (q31_t)0x1b0d716a,
+    (q31_t)0x604f5a0, (q31_t)0x1b18d45c, (q31_t)0x60a48c9, (q31_t)0x1b243643,
+    (q31_t)0x60f9e2e, (q31_t)0x1b2f971e, (q31_t)0x614f5cf, (q31_t)0x1b3af6ec,
+    (q31_t)0x61a4fac, (q31_t)0x1b4655ae, (q31_t)0x61fabc4, (q31_t)0x1b51b363,
+    (q31_t)0x6250a18, (q31_t)0x1b5d100a, (q31_t)0x62a6aa6, (q31_t)0x1b686ba3,
+    (q31_t)0x62fcd6f, (q31_t)0x1b73c62d, (q31_t)0x6353273, (q31_t)0x1b7f1fa9,
+    (q31_t)0x63a99b1, (q31_t)0x1b8a7815, (q31_t)0x6400329, (q31_t)0x1b95cf71,
+    (q31_t)0x6456edb, (q31_t)0x1ba125bd, (q31_t)0x64adcc7, (q31_t)0x1bac7af9,
+    (q31_t)0x6504ced, (q31_t)0x1bb7cf23, (q31_t)0x655bf4c, (q31_t)0x1bc3223c,
+    (q31_t)0x65b33e4, (q31_t)0x1bce7442, (q31_t)0x660aab5, (q31_t)0x1bd9c537,
+    (q31_t)0x66623be, (q31_t)0x1be51518, (q31_t)0x66b9f01, (q31_t)0x1bf063e6,
+    (q31_t)0x6711c7b, (q31_t)0x1bfbb1a0, (q31_t)0x6769c2e, (q31_t)0x1c06fe46,
+    (q31_t)0x67c1e18, (q31_t)0x1c1249d8, (q31_t)0x681a23a, (q31_t)0x1c1d9454,
+    (q31_t)0x6872894, (q31_t)0x1c28ddbb, (q31_t)0x68cb124, (q31_t)0x1c34260c,
+    (q31_t)0x6923bec, (q31_t)0x1c3f6d47, (q31_t)0x697c8eb, (q31_t)0x1c4ab36b,
+    (q31_t)0x69d5820, (q31_t)0x1c55f878, (q31_t)0x6a2e98b, (q31_t)0x1c613c6d,
+    (q31_t)0x6a87d2d, (q31_t)0x1c6c7f4a, (q31_t)0x6ae1304, (q31_t)0x1c77c10e,
+    (q31_t)0x6b3ab12, (q31_t)0x1c8301b9, (q31_t)0x6b94554, (q31_t)0x1c8e414b,
+    (q31_t)0x6bee1cd, (q31_t)0x1c997fc4, (q31_t)0x6c4807a, (q31_t)0x1ca4bd21,
+    (q31_t)0x6ca215c, (q31_t)0x1caff965, (q31_t)0x6cfc472, (q31_t)0x1cbb348d,
+    (q31_t)0x6d569be, (q31_t)0x1cc66e99, (q31_t)0x6db113d, (q31_t)0x1cd1a78a,
+    (q31_t)0x6e0baf0, (q31_t)0x1cdcdf5e, (q31_t)0x6e666d7, (q31_t)0x1ce81615,
+    (q31_t)0x6ec14f2, (q31_t)0x1cf34baf, (q31_t)0x6f1c540, (q31_t)0x1cfe802b,
+    (q31_t)0x6f777c1, (q31_t)0x1d09b389, (q31_t)0x6fd2c75, (q31_t)0x1d14e5c9,
+    (q31_t)0x702e35c, (q31_t)0x1d2016e9, (q31_t)0x7089c75, (q31_t)0x1d2b46ea,
+    (q31_t)0x70e57c0, (q31_t)0x1d3675cb, (q31_t)0x714153e, (q31_t)0x1d41a38c,
+    (q31_t)0x719d4ed, (q31_t)0x1d4cd02c, (q31_t)0x71f96ce, (q31_t)0x1d57fbaa,
+    (q31_t)0x7255ae0, (q31_t)0x1d632608, (q31_t)0x72b2123, (q31_t)0x1d6e4f43,
+    (q31_t)0x730e997, (q31_t)0x1d79775c, (q31_t)0x736b43c, (q31_t)0x1d849e51,
+    (q31_t)0x73c8111, (q31_t)0x1d8fc424, (q31_t)0x7425016, (q31_t)0x1d9ae8d2,
+    (q31_t)0x748214c, (q31_t)0x1da60c5d, (q31_t)0x74df4b1, (q31_t)0x1db12ec3,
+    (q31_t)0x753ca46, (q31_t)0x1dbc5004, (q31_t)0x759a20a, (q31_t)0x1dc7701f,
+    (q31_t)0x75f7bfe, (q31_t)0x1dd28f15, (q31_t)0x7655820, (q31_t)0x1dddace4,
+    (q31_t)0x76b3671, (q31_t)0x1de8c98c, (q31_t)0x77116f0, (q31_t)0x1df3e50d,
+    (q31_t)0x776f99d, (q31_t)0x1dfeff67, (q31_t)0x77cde79, (q31_t)0x1e0a1898,
+    (q31_t)0x782c582, (q31_t)0x1e1530a1, (q31_t)0x788aeb9, (q31_t)0x1e204781,
+    (q31_t)0x78e9a1d, (q31_t)0x1e2b5d38, (q31_t)0x79487ae, (q31_t)0x1e3671c5,
+    (q31_t)0x79a776c, (q31_t)0x1e418528, (q31_t)0x7a06957, (q31_t)0x1e4c9760,
+    (q31_t)0x7a65d6e, (q31_t)0x1e57a86d, (q31_t)0x7ac53b1, (q31_t)0x1e62b84f,
+    (q31_t)0x7b24c20, (q31_t)0x1e6dc705, (q31_t)0x7b846ba, (q31_t)0x1e78d48e,
+    (q31_t)0x7be4381, (q31_t)0x1e83e0eb, (q31_t)0x7c44272, (q31_t)0x1e8eec1b,
+    (q31_t)0x7ca438f, (q31_t)0x1e99f61d, (q31_t)0x7d046d6, (q31_t)0x1ea4fef0,
+    (q31_t)0x7d64c47, (q31_t)0x1eb00696, (q31_t)0x7dc53e3, (q31_t)0x1ebb0d0d,
+    (q31_t)0x7e25daa, (q31_t)0x1ec61254, (q31_t)0x7e8699a, (q31_t)0x1ed1166b,
+    (q31_t)0x7ee77b3, (q31_t)0x1edc1953, (q31_t)0x7f487f6, (q31_t)0x1ee71b0a,
+    (q31_t)0x7fa9a62, (q31_t)0x1ef21b90, (q31_t)0x800aef7, (q31_t)0x1efd1ae4,
+    (q31_t)0x806c5b5, (q31_t)0x1f081907, (q31_t)0x80cde9b, (q31_t)0x1f1315f7,
+    (q31_t)0x812f9a9, (q31_t)0x1f1e11b5, (q31_t)0x81916df, (q31_t)0x1f290c3f,
+    (q31_t)0x81f363d, (q31_t)0x1f340596, (q31_t)0x82557c3, (q31_t)0x1f3efdb9,
+    (q31_t)0x82b7b70, (q31_t)0x1f49f4a8, (q31_t)0x831a143, (q31_t)0x1f54ea62,
+    (q31_t)0x837c93e, (q31_t)0x1f5fdee6, (q31_t)0x83df35f, (q31_t)0x1f6ad235,
+    (q31_t)0x8441fa6, (q31_t)0x1f75c44e, (q31_t)0x84a4e14, (q31_t)0x1f80b531,
+    (q31_t)0x8507ea7, (q31_t)0x1f8ba4dc, (q31_t)0x856b160, (q31_t)0x1f969350,
+    (q31_t)0x85ce63e, (q31_t)0x1fa1808c, (q31_t)0x8631d42, (q31_t)0x1fac6c91,
+    (q31_t)0x869566a, (q31_t)0x1fb7575c, (q31_t)0x86f91b7, (q31_t)0x1fc240ef,
+    (q31_t)0x875cf28, (q31_t)0x1fcd2948, (q31_t)0x87c0ebd, (q31_t)0x1fd81067,
+    (q31_t)0x8825077, (q31_t)0x1fe2f64c, (q31_t)0x8889454, (q31_t)0x1feddaf6,
+    (q31_t)0x88eda54, (q31_t)0x1ff8be65, (q31_t)0x8952278, (q31_t)0x2003a099,
+    (q31_t)0x89b6cbf, (q31_t)0x200e8190, (q31_t)0x8a1b928, (q31_t)0x2019614c,
+    (q31_t)0x8a807b4, (q31_t)0x20243fca, (q31_t)0x8ae5862, (q31_t)0x202f1d0b,
+    (q31_t)0x8b4ab32, (q31_t)0x2039f90f, (q31_t)0x8bb0023, (q31_t)0x2044d3d4,
+    (q31_t)0x8c15736, (q31_t)0x204fad5b, (q31_t)0x8c7b06b, (q31_t)0x205a85a3,
+    (q31_t)0x8ce0bc0, (q31_t)0x20655cac, (q31_t)0x8d46936, (q31_t)0x20703275,
+    (q31_t)0x8dac8cd, (q31_t)0x207b06fe, (q31_t)0x8e12a84, (q31_t)0x2085da46,
+    (q31_t)0x8e78e5b, (q31_t)0x2090ac4d, (q31_t)0x8edf452, (q31_t)0x209b7d13,
+    (q31_t)0x8f45c68, (q31_t)0x20a64c97, (q31_t)0x8fac69e, (q31_t)0x20b11ad9,
+    (q31_t)0x90132f2, (q31_t)0x20bbe7d8, (q31_t)0x907a166, (q31_t)0x20c6b395,
+    (q31_t)0x90e11f7, (q31_t)0x20d17e0d, (q31_t)0x91484a8, (q31_t)0x20dc4742,
+    (q31_t)0x91af976, (q31_t)0x20e70f32, (q31_t)0x9217062, (q31_t)0x20f1d5de,
+    (q31_t)0x927e96b, (q31_t)0x20fc9b44, (q31_t)0x92e6492, (q31_t)0x21075f65,
+    (q31_t)0x934e1d6, (q31_t)0x21122240, (q31_t)0x93b6137, (q31_t)0x211ce3d5,
+    (q31_t)0x941e2b4, (q31_t)0x2127a423, (q31_t)0x948664d, (q31_t)0x21326329,
+    (q31_t)0x94eec03, (q31_t)0x213d20e8, (q31_t)0x95573d4, (q31_t)0x2147dd5f,
+    (q31_t)0x95bfdc1, (q31_t)0x2152988d, (q31_t)0x96289c9, (q31_t)0x215d5273,
+    (q31_t)0x96917ec, (q31_t)0x21680b0f, (q31_t)0x96fa82a, (q31_t)0x2172c262,
+    (q31_t)0x9763a83, (q31_t)0x217d786a, (q31_t)0x97ccef5, (q31_t)0x21882d28,
+    (q31_t)0x9836582, (q31_t)0x2192e09b, (q31_t)0x989fe29, (q31_t)0x219d92c2,
+    (q31_t)0x99098e9, (q31_t)0x21a8439e, (q31_t)0x99735c2, (q31_t)0x21b2f32e,
+    (q31_t)0x99dd4b4, (q31_t)0x21bda171, (q31_t)0x9a475bf, (q31_t)0x21c84e67,
+    (q31_t)0x9ab18e3, (q31_t)0x21d2fa0f, (q31_t)0x9b1be1e, (q31_t)0x21dda46a,
+    (q31_t)0x9b86572, (q31_t)0x21e84d76, (q31_t)0x9bf0edd, (q31_t)0x21f2f534,
+    (q31_t)0x9c5ba60, (q31_t)0x21fd9ba3, (q31_t)0x9cc67fa, (q31_t)0x220840c2,
+    (q31_t)0x9d317ab, (q31_t)0x2212e492, (q31_t)0x9d9c973, (q31_t)0x221d8711,
+    (q31_t)0x9e07d51, (q31_t)0x2228283f, (q31_t)0x9e73346, (q31_t)0x2232c81c,
+    (q31_t)0x9edeb50, (q31_t)0x223d66a8, (q31_t)0x9f4a570, (q31_t)0x224803e2,
+    (q31_t)0x9fb61a5, (q31_t)0x22529fca, (q31_t)0xa021fef, (q31_t)0x225d3a5e,
+    (q31_t)0xa08e04f, (q31_t)0x2267d3a0, (q31_t)0xa0fa2c3, (q31_t)0x22726b8e,
+    (q31_t)0xa16674b, (q31_t)0x227d0228, (q31_t)0xa1d2de7, (q31_t)0x2287976e,
+    (q31_t)0xa23f698, (q31_t)0x22922b5e, (q31_t)0xa2ac15b, (q31_t)0x229cbdfa,
+    (q31_t)0xa318e32, (q31_t)0x22a74f40, (q31_t)0xa385d1d, (q31_t)0x22b1df30,
+    (q31_t)0xa3f2e19, (q31_t)0x22bc6dca, (q31_t)0xa460129, (q31_t)0x22c6fb0c,
+    (q31_t)0xa4cd64b, (q31_t)0x22d186f8, (q31_t)0xa53ad7e, (q31_t)0x22dc118c,
+    (q31_t)0xa5a86c4, (q31_t)0x22e69ac8, (q31_t)0xa61621b, (q31_t)0x22f122ab,
+    (q31_t)0xa683f83, (q31_t)0x22fba936, (q31_t)0xa6f1efc, (q31_t)0x23062e67,
+    (q31_t)0xa760086, (q31_t)0x2310b23e, (q31_t)0xa7ce420, (q31_t)0x231b34bc,
+    (q31_t)0xa83c9ca, (q31_t)0x2325b5df, (q31_t)0xa8ab184, (q31_t)0x233035a7,
+    (q31_t)0xa919b4e, (q31_t)0x233ab414, (q31_t)0xa988727, (q31_t)0x23453125,
+    (q31_t)0xa9f750f, (q31_t)0x234facda, (q31_t)0xaa66506, (q31_t)0x235a2733,
+    (q31_t)0xaad570c, (q31_t)0x2364a02e, (q31_t)0xab44b1f, (q31_t)0x236f17cc,
+    (q31_t)0xabb4141, (q31_t)0x23798e0d, (q31_t)0xac23971, (q31_t)0x238402ef,
+    (q31_t)0xac933ae, (q31_t)0x238e7673, (q31_t)0xad02ff8, (q31_t)0x2398e898,
+    (q31_t)0xad72e4f, (q31_t)0x23a3595e, (q31_t)0xade2eb3, (q31_t)0x23adc8c4,
+    (q31_t)0xae53123, (q31_t)0x23b836ca, (q31_t)0xaec35a0, (q31_t)0x23c2a36f,
+    (q31_t)0xaf33c28, (q31_t)0x23cd0eb3, (q31_t)0xafa44bc, (q31_t)0x23d77896,
+    (q31_t)0xb014f5b, (q31_t)0x23e1e117, (q31_t)0xb085c05, (q31_t)0x23ec4837,
+    (q31_t)0xb0f6aba, (q31_t)0x23f6adf3, (q31_t)0xb167b79, (q31_t)0x2401124d,
+    (q31_t)0xb1d8e43, (q31_t)0x240b7543, (q31_t)0xb24a316, (q31_t)0x2415d6d5,
+    (q31_t)0xb2bb9f4, (q31_t)0x24203704, (q31_t)0xb32d2da, (q31_t)0x242a95ce,
+    (q31_t)0xb39edca, (q31_t)0x2434f332, (q31_t)0xb410ac3, (q31_t)0x243f4f32,
+    (q31_t)0xb4829c4, (q31_t)0x2449a9cc, (q31_t)0xb4f4acd, (q31_t)0x245402ff,
+    (q31_t)0xb566ddf, (q31_t)0x245e5acc, (q31_t)0xb5d92f8, (q31_t)0x2468b132,
+    (q31_t)0xb64ba19, (q31_t)0x24730631, (q31_t)0xb6be341, (q31_t)0x247d59c8,
+    (q31_t)0xb730e70, (q31_t)0x2487abf7, (q31_t)0xb7a3ba5, (q31_t)0x2491fcbe,
+    (q31_t)0xb816ae1, (q31_t)0x249c4c1b, (q31_t)0xb889c23, (q31_t)0x24a69a0f,
+    (q31_t)0xb8fcf6b, (q31_t)0x24b0e699, (q31_t)0xb9704b9, (q31_t)0x24bb31ba,
+    (q31_t)0xb9e3c0b, (q31_t)0x24c57b6f, (q31_t)0xba57563, (q31_t)0x24cfc3ba,
+    (q31_t)0xbacb0bf, (q31_t)0x24da0a9a, (q31_t)0xbb3ee20, (q31_t)0x24e4500e,
+    (q31_t)0xbbb2d85, (q31_t)0x24ee9415, (q31_t)0xbc26eee, (q31_t)0x24f8d6b0,
+    (q31_t)0xbc9b25a, (q31_t)0x250317df, (q31_t)0xbd0f7ca, (q31_t)0x250d57a0,
+    (q31_t)0xbd83f3d, (q31_t)0x251795f3, (q31_t)0xbdf88b3, (q31_t)0x2521d2d8,
+    (q31_t)0xbe6d42b, (q31_t)0x252c0e4f, (q31_t)0xbee21a5, (q31_t)0x25364857,
+    (q31_t)0xbf57121, (q31_t)0x254080ef, (q31_t)0xbfcc29f, (q31_t)0x254ab818,
+    (q31_t)0xc04161e, (q31_t)0x2554edd1, (q31_t)0xc0b6b9e, (q31_t)0x255f2219,
+    (q31_t)0xc12c31f, (q31_t)0x256954f1, (q31_t)0xc1a1ca0, (q31_t)0x25738657,
+    (q31_t)0xc217822, (q31_t)0x257db64c, (q31_t)0xc28d5a3, (q31_t)0x2587e4cf,
+    (q31_t)0xc303524, (q31_t)0x259211df, (q31_t)0xc3796a5, (q31_t)0x259c3d7c,
+    (q31_t)0xc3efa25, (q31_t)0x25a667a7, (q31_t)0xc465fa3, (q31_t)0x25b0905d,
+    (q31_t)0xc4dc720, (q31_t)0x25bab7a0, (q31_t)0xc55309b, (q31_t)0x25c4dd6e,
+    (q31_t)0xc5c9c14, (q31_t)0x25cf01c8, (q31_t)0xc64098b, (q31_t)0x25d924ac,
+    (q31_t)0xc6b78ff, (q31_t)0x25e3461b, (q31_t)0xc72ea70, (q31_t)0x25ed6614,
+    (q31_t)0xc7a5dde, (q31_t)0x25f78497, (q31_t)0xc81d349, (q31_t)0x2601a1a2,
+    (q31_t)0xc894aaf, (q31_t)0x260bbd37, (q31_t)0xc90c412, (q31_t)0x2615d754,
+    (q31_t)0xc983f70, (q31_t)0x261feffa, (q31_t)0xc9fbcca, (q31_t)0x262a0727,
+    (q31_t)0xca73c1e, (q31_t)0x26341cdb, (q31_t)0xcaebd6e, (q31_t)0x263e3117,
+    (q31_t)0xcb640b8, (q31_t)0x264843d9, (q31_t)0xcbdc5fc, (q31_t)0x26525521,
+    (q31_t)0xcc54d3a, (q31_t)0x265c64ef, (q31_t)0xcccd671, (q31_t)0x26667342,
+    (q31_t)0xcd461a2, (q31_t)0x2670801a, (q31_t)0xcdbeecc, (q31_t)0x267a8b77,
+    (q31_t)0xce37def, (q31_t)0x26849558, (q31_t)0xceb0f0a, (q31_t)0x268e9dbd,
+    (q31_t)0xcf2a21d, (q31_t)0x2698a4a6, (q31_t)0xcfa3729, (q31_t)0x26a2aa11,
+    (q31_t)0xd01ce2b, (q31_t)0x26acadff, (q31_t)0xd096725, (q31_t)0x26b6b070,
+    (q31_t)0xd110216, (q31_t)0x26c0b162, (q31_t)0xd189efe, (q31_t)0x26cab0d6,
+    (q31_t)0xd203ddc, (q31_t)0x26d4aecb, (q31_t)0xd27deb0, (q31_t)0x26deab41,
+    (q31_t)0xd2f817b, (q31_t)0x26e8a637, (q31_t)0xd37263a, (q31_t)0x26f29fad,
+    (q31_t)0xd3eccef, (q31_t)0x26fc97a3, (q31_t)0xd467599, (q31_t)0x27068e18,
+    (q31_t)0xd4e2037, (q31_t)0x2710830c, (q31_t)0xd55ccca, (q31_t)0x271a767e,
+    (q31_t)0xd5d7b50, (q31_t)0x2724686e, (q31_t)0xd652bcb, (q31_t)0x272e58dc,
+    (q31_t)0xd6cde39, (q31_t)0x273847c8, (q31_t)0xd74929a, (q31_t)0x27423530,
+    (q31_t)0xd7c48ee, (q31_t)0x274c2115, (q31_t)0xd840134, (q31_t)0x27560b76,
+    (q31_t)0xd8bbb6d, (q31_t)0x275ff452, (q31_t)0xd937798, (q31_t)0x2769dbaa,
+    (q31_t)0xd9b35b4, (q31_t)0x2773c17d, (q31_t)0xda2f5c2, (q31_t)0x277da5cb,
+    (q31_t)0xdaab7c0, (q31_t)0x27878893, (q31_t)0xdb27bb0, (q31_t)0x279169d5,
+    (q31_t)0xdba4190, (q31_t)0x279b4990, (q31_t)0xdc20960, (q31_t)0x27a527c4,
+    (q31_t)0xdc9d320, (q31_t)0x27af0472, (q31_t)0xdd19ed0, (q31_t)0x27b8df97,
+    (q31_t)0xdd96c6f, (q31_t)0x27c2b934, (q31_t)0xde13bfd, (q31_t)0x27cc9149,
+    (q31_t)0xde90d79, (q31_t)0x27d667d5, (q31_t)0xdf0e0e4, (q31_t)0x27e03cd8,
+    (q31_t)0xdf8b63d, (q31_t)0x27ea1052, (q31_t)0xe008d84, (q31_t)0x27f3e241,
+    (q31_t)0xe0866b8, (q31_t)0x27fdb2a7, (q31_t)0xe1041d9, (q31_t)0x28078181,
+    (q31_t)0xe181ee8, (q31_t)0x28114ed0, (q31_t)0xe1ffde2, (q31_t)0x281b1a94,
+    (q31_t)0xe27dec9, (q31_t)0x2824e4cc, (q31_t)0xe2fc19c, (q31_t)0x282ead78,
+    (q31_t)0xe37a65b, (q31_t)0x28387498, (q31_t)0xe3f8d05, (q31_t)0x28423a2a,
+    (q31_t)0xe47759a, (q31_t)0x284bfe2f, (q31_t)0xe4f6019, (q31_t)0x2855c0a6,
+    (q31_t)0xe574c84, (q31_t)0x285f8190, (q31_t)0xe5f3ad8, (q31_t)0x286940ea,
+    (q31_t)0xe672b16, (q31_t)0x2872feb6, (q31_t)0xe6f1d3d, (q31_t)0x287cbaf3,
+    (q31_t)0xe77114e, (q31_t)0x288675a0, (q31_t)0xe7f0748, (q31_t)0x28902ebd,
+    (q31_t)0xe86ff2a, (q31_t)0x2899e64a, (q31_t)0xe8ef8f4, (q31_t)0x28a39c46,
+    (q31_t)0xe96f4a7, (q31_t)0x28ad50b1, (q31_t)0xe9ef241, (q31_t)0x28b7038b,
+    (q31_t)0xea6f1c2, (q31_t)0x28c0b4d2, (q31_t)0xeaef32b, (q31_t)0x28ca6488,
+    (q31_t)0xeb6f67a, (q31_t)0x28d412ab, (q31_t)0xebefbb0, (q31_t)0x28ddbf3b,
+    (q31_t)0xec702cb, (q31_t)0x28e76a37, (q31_t)0xecf0bcd, (q31_t)0x28f113a0,
+    (q31_t)0xed716b4, (q31_t)0x28fabb75, (q31_t)0xedf2380, (q31_t)0x290461b5,
+    (q31_t)0xee73231, (q31_t)0x290e0661, (q31_t)0xeef42c7, (q31_t)0x2917a977,
+    (q31_t)0xef75541, (q31_t)0x29214af8, (q31_t)0xeff699f, (q31_t)0x292aeae3,
+    (q31_t)0xf077fe1, (q31_t)0x29348937, (q31_t)0xf0f9805, (q31_t)0x293e25f5,
+    (q31_t)0xf17b20d, (q31_t)0x2947c11c, (q31_t)0xf1fcdf8, (q31_t)0x29515aab,
+    (q31_t)0xf27ebc5, (q31_t)0x295af2a3, (q31_t)0xf300b74, (q31_t)0x29648902,
+    (q31_t)0xf382d05, (q31_t)0x296e1dc9, (q31_t)0xf405077, (q31_t)0x2977b0f7,
+    (q31_t)0xf4875ca, (q31_t)0x2981428c, (q31_t)0xf509cfe, (q31_t)0x298ad287,
+    (q31_t)0xf58c613, (q31_t)0x299460e8, (q31_t)0xf60f108, (q31_t)0x299dedaf,
+    (q31_t)0xf691ddd, (q31_t)0x29a778db, (q31_t)0xf714c91, (q31_t)0x29b1026c,
+    (q31_t)0xf797d24, (q31_t)0x29ba8a61, (q31_t)0xf81af97, (q31_t)0x29c410ba,
+    (q31_t)0xf89e3e8, (q31_t)0x29cd9578, (q31_t)0xf921a17, (q31_t)0x29d71899,
+    (q31_t)0xf9a5225, (q31_t)0x29e09a1c, (q31_t)0xfa28c10, (q31_t)0x29ea1a03,
+    (q31_t)0xfaac7d8, (q31_t)0x29f3984c, (q31_t)0xfb3057d, (q31_t)0x29fd14f6,
+    (q31_t)0xfbb4500, (q31_t)0x2a069003, (q31_t)0xfc3865e, (q31_t)0x2a100970,
+    (q31_t)0xfcbc999, (q31_t)0x2a19813f, (q31_t)0xfd40eaf, (q31_t)0x2a22f76e,
+    (q31_t)0xfdc55a1, (q31_t)0x2a2c6bfd, (q31_t)0xfe49e6d, (q31_t)0x2a35deeb,
+    (q31_t)0xfece915, (q31_t)0x2a3f503a, (q31_t)0xff53597, (q31_t)0x2a48bfe7,
+    (q31_t)0xffd83f4, (q31_t)0x2a522df3, (q31_t)0x1005d42a, (q31_t)0x2a5b9a5d,
+    (q31_t)0x100e2639, (q31_t)0x2a650525, (q31_t)0x10167a22, (q31_t)0x2a6e6e4b,
+    (q31_t)0x101ecfe4, (q31_t)0x2a77d5ce, (q31_t)0x1027277e, (q31_t)0x2a813bae,
+    (q31_t)0x102f80f1, (q31_t)0x2a8a9fea, (q31_t)0x1037dc3b, (q31_t)0x2a940283,
+    (q31_t)0x1040395d, (q31_t)0x2a9d6377, (q31_t)0x10489856, (q31_t)0x2aa6c2c6,
+    (q31_t)0x1050f926, (q31_t)0x2ab02071, (q31_t)0x10595bcd, (q31_t)0x2ab97c77,
+    (q31_t)0x1061c04a, (q31_t)0x2ac2d6d6, (q31_t)0x106a269d, (q31_t)0x2acc2f90,
+    (q31_t)0x10728ec6, (q31_t)0x2ad586a3, (q31_t)0x107af8c4, (q31_t)0x2adedc10,
+    (q31_t)0x10836497, (q31_t)0x2ae82fd5, (q31_t)0x108bd23f, (q31_t)0x2af181f3,
+    (q31_t)0x109441bb, (q31_t)0x2afad269, (q31_t)0x109cb30b, (q31_t)0x2b042137,
+    (q31_t)0x10a5262f, (q31_t)0x2b0d6e5c, (q31_t)0x10ad9b26, (q31_t)0x2b16b9d9,
+    (q31_t)0x10b611f1, (q31_t)0x2b2003ac, (q31_t)0x10be8a8d, (q31_t)0x2b294bd5,
+    (q31_t)0x10c704fd, (q31_t)0x2b329255, (q31_t)0x10cf813e, (q31_t)0x2b3bd72a,
+    (q31_t)0x10d7ff51, (q31_t)0x2b451a55, (q31_t)0x10e07f36, (q31_t)0x2b4e5bd4,
+    (q31_t)0x10e900ec, (q31_t)0x2b579ba8, (q31_t)0x10f18472, (q31_t)0x2b60d9d0,
+    (q31_t)0x10fa09c9, (q31_t)0x2b6a164d, (q31_t)0x110290f0, (q31_t)0x2b73511c,
+    (q31_t)0x110b19e7, (q31_t)0x2b7c8a3f, (q31_t)0x1113a4ad, (q31_t)0x2b85c1b5,
+    (q31_t)0x111c3142, (q31_t)0x2b8ef77d, (q31_t)0x1124bfa6, (q31_t)0x2b982b97,
+    (q31_t)0x112d4fd9, (q31_t)0x2ba15e03, (q31_t)0x1135e1d9, (q31_t)0x2baa8ec0,
+    (q31_t)0x113e75a8, (q31_t)0x2bb3bdce, (q31_t)0x11470b44, (q31_t)0x2bbceb2d,
+    (q31_t)0x114fa2ad, (q31_t)0x2bc616dd, (q31_t)0x11583be2, (q31_t)0x2bcf40dc,
+    (q31_t)0x1160d6e5, (q31_t)0x2bd8692b, (q31_t)0x116973b3, (q31_t)0x2be18fc9,
+    (q31_t)0x1172124d, (q31_t)0x2beab4b6, (q31_t)0x117ab2b3, (q31_t)0x2bf3d7f2,
+    (q31_t)0x118354e4, (q31_t)0x2bfcf97c, (q31_t)0x118bf8e0, (q31_t)0x2c061953,
+    (q31_t)0x11949ea6, (q31_t)0x2c0f3779, (q31_t)0x119d4636, (q31_t)0x2c1853eb,
+    (q31_t)0x11a5ef90, (q31_t)0x2c216eaa, (q31_t)0x11ae9ab4, (q31_t)0x2c2a87b6,
+    (q31_t)0x11b747a0, (q31_t)0x2c339f0e, (q31_t)0x11bff656, (q31_t)0x2c3cb4b1,
+    (q31_t)0x11c8a6d4, (q31_t)0x2c45c8a0, (q31_t)0x11d1591a, (q31_t)0x2c4edada,
+    (q31_t)0x11da0d28, (q31_t)0x2c57eb5e, (q31_t)0x11e2c2fd, (q31_t)0x2c60fa2d,
+    (q31_t)0x11eb7a9a, (q31_t)0x2c6a0746, (q31_t)0x11f433fd, (q31_t)0x2c7312a9,
+    (q31_t)0x11fcef27, (q31_t)0x2c7c1c55, (q31_t)0x1205ac17, (q31_t)0x2c85244a,
+    (q31_t)0x120e6acc, (q31_t)0x2c8e2a87, (q31_t)0x12172b48, (q31_t)0x2c972f0d,
+    (q31_t)0x121fed88, (q31_t)0x2ca031da, (q31_t)0x1228b18d, (q31_t)0x2ca932ef,
+    (q31_t)0x12317756, (q31_t)0x2cb2324c, (q31_t)0x123a3ee4, (q31_t)0x2cbb2fef,
+    (q31_t)0x12430835, (q31_t)0x2cc42bd9, (q31_t)0x124bd34a, (q31_t)0x2ccd2609,
+    (q31_t)0x1254a021, (q31_t)0x2cd61e7f, (q31_t)0x125d6ebc, (q31_t)0x2cdf153a,
+    (q31_t)0x12663f19, (q31_t)0x2ce80a3a, (q31_t)0x126f1138, (q31_t)0x2cf0fd80,
+    (q31_t)0x1277e518, (q31_t)0x2cf9ef09, (q31_t)0x1280babb, (q31_t)0x2d02ded7,
+    (q31_t)0x1289921e, (q31_t)0x2d0bcce8, (q31_t)0x12926b41, (q31_t)0x2d14b93d,
+    (q31_t)0x129b4626, (q31_t)0x2d1da3d5, (q31_t)0x12a422ca, (q31_t)0x2d268cb0,
+    (q31_t)0x12ad012e, (q31_t)0x2d2f73cd, (q31_t)0x12b5e151, (q31_t)0x2d38592c,
+    (q31_t)0x12bec333, (q31_t)0x2d413ccd, (q31_t)0x12c7a6d4, (q31_t)0x2d4a1eaf,
+    (q31_t)0x12d08c33, (q31_t)0x2d52fed2, (q31_t)0x12d97350, (q31_t)0x2d5bdd36,
+    (q31_t)0x12e25c2b, (q31_t)0x2d64b9da, (q31_t)0x12eb46c3, (q31_t)0x2d6d94bf,
+    (q31_t)0x12f43318, (q31_t)0x2d766de2, (q31_t)0x12fd2129, (q31_t)0x2d7f4545,
+    (q31_t)0x130610f7, (q31_t)0x2d881ae8, (q31_t)0x130f0280, (q31_t)0x2d90eec8,
+    (q31_t)0x1317f5c6, (q31_t)0x2d99c0e7, (q31_t)0x1320eac6, (q31_t)0x2da29144,
+    (q31_t)0x1329e181, (q31_t)0x2dab5fdf, (q31_t)0x1332d9f7, (q31_t)0x2db42cb6,
+    (q31_t)0x133bd427, (q31_t)0x2dbcf7cb, (q31_t)0x1344d011, (q31_t)0x2dc5c11c,
+    (q31_t)0x134dcdb4, (q31_t)0x2dce88aa, (q31_t)0x1356cd11, (q31_t)0x2dd74e73,
+    (q31_t)0x135fce26, (q31_t)0x2de01278, (q31_t)0x1368d0f3, (q31_t)0x2de8d4b8,
+    (q31_t)0x1371d579, (q31_t)0x2df19534, (q31_t)0x137adbb6, (q31_t)0x2dfa53e9,
+    (q31_t)0x1383e3ab, (q31_t)0x2e0310d9, (q31_t)0x138ced57, (q31_t)0x2e0bcc03,
+    (q31_t)0x1395f8ba, (q31_t)0x2e148566, (q31_t)0x139f05d3, (q31_t)0x2e1d3d03,
+    (q31_t)0x13a814a2, (q31_t)0x2e25f2d8, (q31_t)0x13b12526, (q31_t)0x2e2ea6e6,
+    (q31_t)0x13ba3760, (q31_t)0x2e37592c, (q31_t)0x13c34b4f, (q31_t)0x2e4009aa,
+    (q31_t)0x13cc60f2, (q31_t)0x2e48b860, (q31_t)0x13d5784a, (q31_t)0x2e51654c,
+    (q31_t)0x13de9156, (q31_t)0x2e5a1070, (q31_t)0x13e7ac15, (q31_t)0x2e62b9ca,
+    (q31_t)0x13f0c887, (q31_t)0x2e6b615a, (q31_t)0x13f9e6ad, (q31_t)0x2e740720,
+    (q31_t)0x14030684, (q31_t)0x2e7cab1c, (q31_t)0x140c280e, (q31_t)0x2e854d4d,
+    (q31_t)0x14154b4a, (q31_t)0x2e8dedb3, (q31_t)0x141e7037, (q31_t)0x2e968c4d,
+    (q31_t)0x142796d5, (q31_t)0x2e9f291b, (q31_t)0x1430bf24, (q31_t)0x2ea7c41e,
+    (q31_t)0x1439e923, (q31_t)0x2eb05d53, (q31_t)0x144314d3, (q31_t)0x2eb8f4bc,
+    (q31_t)0x144c4232, (q31_t)0x2ec18a58, (q31_t)0x14557140, (q31_t)0x2eca1e27,
+    (q31_t)0x145ea1fd, (q31_t)0x2ed2b027, (q31_t)0x1467d469, (q31_t)0x2edb405a,
+    (q31_t)0x14710883, (q31_t)0x2ee3cebe, (q31_t)0x147a3e4b, (q31_t)0x2eec5b53,
+    (q31_t)0x148375c1, (q31_t)0x2ef4e619, (q31_t)0x148caee4, (q31_t)0x2efd6f10,
+    (q31_t)0x1495e9b3, (q31_t)0x2f05f637, (q31_t)0x149f2630, (q31_t)0x2f0e7b8e,
+    (q31_t)0x14a86458, (q31_t)0x2f16ff14, (q31_t)0x14b1a42c, (q31_t)0x2f1f80ca,
+    (q31_t)0x14bae5ab, (q31_t)0x2f2800af, (q31_t)0x14c428d6, (q31_t)0x2f307ec2,
+    (q31_t)0x14cd6dab, (q31_t)0x2f38fb03, (q31_t)0x14d6b42b, (q31_t)0x2f417573,
+    (q31_t)0x14dffc54, (q31_t)0x2f49ee0f, (q31_t)0x14e94627, (q31_t)0x2f5264da,
+    (q31_t)0x14f291a4, (q31_t)0x2f5ad9d1, (q31_t)0x14fbdec9, (q31_t)0x2f634cf5,
+    (q31_t)0x15052d97, (q31_t)0x2f6bbe45, (q31_t)0x150e7e0d, (q31_t)0x2f742dc1,
+    (q31_t)0x1517d02b, (q31_t)0x2f7c9b69, (q31_t)0x152123f0, (q31_t)0x2f85073c,
+    (q31_t)0x152a795d, (q31_t)0x2f8d713a, (q31_t)0x1533d070, (q31_t)0x2f95d963,
+    (q31_t)0x153d292a, (q31_t)0x2f9e3fb6, (q31_t)0x15468389, (q31_t)0x2fa6a433,
+    (q31_t)0x154fdf8f, (q31_t)0x2faf06da, (q31_t)0x15593d3a, (q31_t)0x2fb767aa,
+    (q31_t)0x15629c89, (q31_t)0x2fbfc6a3, (q31_t)0x156bfd7d, (q31_t)0x2fc823c5,
+    (q31_t)0x15756016, (q31_t)0x2fd07f0f, (q31_t)0x157ec452, (q31_t)0x2fd8d882,
+    (q31_t)0x15882a32, (q31_t)0x2fe1301c, (q31_t)0x159191b5, (q31_t)0x2fe985de,
+    (q31_t)0x159afadb, (q31_t)0x2ff1d9c7, (q31_t)0x15a465a3, (q31_t)0x2ffa2bd6,
+    (q31_t)0x15add20d, (q31_t)0x30027c0c, (q31_t)0x15b74019, (q31_t)0x300aca69,
+    (q31_t)0x15c0afc6, (q31_t)0x301316eb, (q31_t)0x15ca2115, (q31_t)0x301b6193,
+    (q31_t)0x15d39403, (q31_t)0x3023aa5f, (q31_t)0x15dd0892, (q31_t)0x302bf151,
+    (q31_t)0x15e67ec1, (q31_t)0x30343667, (q31_t)0x15eff690, (q31_t)0x303c79a2,
+    (q31_t)0x15f96ffd, (q31_t)0x3044bb00, (q31_t)0x1602eb0a, (q31_t)0x304cfa83,
+    (q31_t)0x160c67b4, (q31_t)0x30553828, (q31_t)0x1615e5fd, (q31_t)0x305d73f0,
+    (q31_t)0x161f65e4, (q31_t)0x3065addb, (q31_t)0x1628e767, (q31_t)0x306de5e9,
+    (q31_t)0x16326a88, (q31_t)0x30761c18, (q31_t)0x163bef46, (q31_t)0x307e5069,
+    (q31_t)0x1645759f, (q31_t)0x308682dc, (q31_t)0x164efd94, (q31_t)0x308eb36f,
+    (q31_t)0x16588725, (q31_t)0x3096e223, (q31_t)0x16621251, (q31_t)0x309f0ef8,
+    (q31_t)0x166b9f18, (q31_t)0x30a739ed, (q31_t)0x16752d79, (q31_t)0x30af6302,
+    (q31_t)0x167ebd74, (q31_t)0x30b78a36, (q31_t)0x16884f09, (q31_t)0x30bfaf89,
+    (q31_t)0x1691e237, (q31_t)0x30c7d2fb, (q31_t)0x169b76fe, (q31_t)0x30cff48c,
+    (q31_t)0x16a50d5d, (q31_t)0x30d8143b, (q31_t)0x16aea555, (q31_t)0x30e03208,
+    (q31_t)0x16b83ee4, (q31_t)0x30e84df3, (q31_t)0x16c1da0b, (q31_t)0x30f067fb,
+    (q31_t)0x16cb76c9, (q31_t)0x30f8801f, (q31_t)0x16d5151d, (q31_t)0x31009661,
+    (q31_t)0x16deb508, (q31_t)0x3108aabf, (q31_t)0x16e85689, (q31_t)0x3110bd39,
+    (q31_t)0x16f1f99f, (q31_t)0x3118cdcf, (q31_t)0x16fb9e4b, (q31_t)0x3120dc80,
+    (q31_t)0x1705448b, (q31_t)0x3128e94c, (q31_t)0x170eec60, (q31_t)0x3130f433,
+    (q31_t)0x171895c9, (q31_t)0x3138fd35, (q31_t)0x172240c5, (q31_t)0x31410450,
+    (q31_t)0x172bed55, (q31_t)0x31490986, (q31_t)0x17359b78, (q31_t)0x31510cd5,
+    (q31_t)0x173f4b2e, (q31_t)0x31590e3e, (q31_t)0x1748fc75, (q31_t)0x31610dbf,
+    (q31_t)0x1752af4f, (q31_t)0x31690b59, (q31_t)0x175c63ba, (q31_t)0x3171070c,
+    (q31_t)0x176619b6, (q31_t)0x317900d6, (q31_t)0x176fd143, (q31_t)0x3180f8b8,
+    (q31_t)0x17798a60, (q31_t)0x3188eeb2, (q31_t)0x1783450d, (q31_t)0x3190e2c3,
+    (q31_t)0x178d014a, (q31_t)0x3198d4ea, (q31_t)0x1796bf16, (q31_t)0x31a0c528,
+    (q31_t)0x17a07e70, (q31_t)0x31a8b37c, (q31_t)0x17aa3f5a, (q31_t)0x31b09fe7,
+    (q31_t)0x17b401d1, (q31_t)0x31b88a66, (q31_t)0x17bdc5d6, (q31_t)0x31c072fb,
+    (q31_t)0x17c78b68, (q31_t)0x31c859a5, (q31_t)0x17d15288, (q31_t)0x31d03e64,
+    (q31_t)0x17db1b34, (q31_t)0x31d82137, (q31_t)0x17e4e56c, (q31_t)0x31e0021e,
+    (q31_t)0x17eeb130, (q31_t)0x31e7e118, (q31_t)0x17f87e7f, (q31_t)0x31efbe27,
+    (q31_t)0x18024d59, (q31_t)0x31f79948, (q31_t)0x180c1dbf, (q31_t)0x31ff727c,
+    (q31_t)0x1815efae, (q31_t)0x320749c3, (q31_t)0x181fc328, (q31_t)0x320f1f1c,
+    (q31_t)0x1829982b, (q31_t)0x3216f287, (q31_t)0x18336eb7, (q31_t)0x321ec403,
+    (q31_t)0x183d46cc, (q31_t)0x32269391, (q31_t)0x18472069, (q31_t)0x322e6130,
+    (q31_t)0x1850fb8e, (q31_t)0x32362ce0, (q31_t)0x185ad83c, (q31_t)0x323df6a0,
+    (q31_t)0x1864b670, (q31_t)0x3245be70, (q31_t)0x186e962b, (q31_t)0x324d8450,
+    (q31_t)0x1878776d, (q31_t)0x32554840, (q31_t)0x18825a35, (q31_t)0x325d0a3e,
+    (q31_t)0x188c3e83, (q31_t)0x3264ca4c, (q31_t)0x18962456, (q31_t)0x326c8868,
+    (q31_t)0x18a00bae, (q31_t)0x32744493, (q31_t)0x18a9f48a, (q31_t)0x327bfecc,
+    (q31_t)0x18b3deeb, (q31_t)0x3283b712, (q31_t)0x18bdcad0, (q31_t)0x328b6d66,
+    (q31_t)0x18c7b838, (q31_t)0x329321c7, (q31_t)0x18d1a724, (q31_t)0x329ad435,
+    (q31_t)0x18db9792, (q31_t)0x32a284b0, (q31_t)0x18e58982, (q31_t)0x32aa3336,
+    (q31_t)0x18ef7cf4, (q31_t)0x32b1dfc9, (q31_t)0x18f971e8, (q31_t)0x32b98a67,
+    (q31_t)0x1903685d, (q31_t)0x32c13311, (q31_t)0x190d6053, (q31_t)0x32c8d9c6,
+    (q31_t)0x191759c9, (q31_t)0x32d07e85, (q31_t)0x192154bf, (q31_t)0x32d82150,
+    (q31_t)0x192b5135, (q31_t)0x32dfc224, (q31_t)0x19354f2a, (q31_t)0x32e76102,
+    (q31_t)0x193f4e9e, (q31_t)0x32eefdea, (q31_t)0x19494f90, (q31_t)0x32f698db,
+    (q31_t)0x19535201, (q31_t)0x32fe31d5, (q31_t)0x195d55ef, (q31_t)0x3305c8d7,
+    (q31_t)0x19675b5a, (q31_t)0x330d5de3, (q31_t)0x19716243, (q31_t)0x3314f0f6,
+    (q31_t)0x197b6aa8, (q31_t)0x331c8211, (q31_t)0x19857489, (q31_t)0x33241134,
+    (q31_t)0x198f7fe6, (q31_t)0x332b9e5e, (q31_t)0x19998cbe, (q31_t)0x3333298f,
+    (q31_t)0x19a39b11, (q31_t)0x333ab2c6, (q31_t)0x19adaadf, (q31_t)0x33423a04,
+    (q31_t)0x19b7bc27, (q31_t)0x3349bf48, (q31_t)0x19c1cee9, (q31_t)0x33514292,
+    (q31_t)0x19cbe325, (q31_t)0x3358c3e2, (q31_t)0x19d5f8d9, (q31_t)0x33604336,
+    (q31_t)0x19e01006, (q31_t)0x3367c090, (q31_t)0x19ea28ac, (q31_t)0x336f3bee,
+    (q31_t)0x19f442c9, (q31_t)0x3376b551, (q31_t)0x19fe5e5e, (q31_t)0x337e2cb7,
+    (q31_t)0x1a087b69, (q31_t)0x3385a222, (q31_t)0x1a1299ec, (q31_t)0x338d1590,
+    (q31_t)0x1a1cb9e5, (q31_t)0x33948701, (q31_t)0x1a26db54, (q31_t)0x339bf675,
+    (q31_t)0x1a30fe38, (q31_t)0x33a363ec, (q31_t)0x1a3b2292, (q31_t)0x33aacf65,
+    (q31_t)0x1a454860, (q31_t)0x33b238e0, (q31_t)0x1a4f6fa3, (q31_t)0x33b9a05d,
+    (q31_t)0x1a599859, (q31_t)0x33c105db, (q31_t)0x1a63c284, (q31_t)0x33c8695b,
+    (q31_t)0x1a6dee21, (q31_t)0x33cfcadc, (q31_t)0x1a781b31, (q31_t)0x33d72a5d,
+    (q31_t)0x1a8249b4, (q31_t)0x33de87de, (q31_t)0x1a8c79a9, (q31_t)0x33e5e360,
+    (q31_t)0x1a96ab0f, (q31_t)0x33ed3ce1, (q31_t)0x1aa0dde7, (q31_t)0x33f49462,
+    (q31_t)0x1aab122f, (q31_t)0x33fbe9e2, (q31_t)0x1ab547e8, (q31_t)0x34033d61,
+    (q31_t)0x1abf7f11, (q31_t)0x340a8edf, (q31_t)0x1ac9b7a9, (q31_t)0x3411de5b,
+    (q31_t)0x1ad3f1b1, (q31_t)0x34192bd5, (q31_t)0x1ade2d28, (q31_t)0x3420774d,
+    (q31_t)0x1ae86a0d, (q31_t)0x3427c0c3, (q31_t)0x1af2a860, (q31_t)0x342f0836,
+    (q31_t)0x1afce821, (q31_t)0x34364da6, (q31_t)0x1b072950, (q31_t)0x343d9112,
+    (q31_t)0x1b116beb, (q31_t)0x3444d27b, (q31_t)0x1b1baff2, (q31_t)0x344c11e0,
+    (q31_t)0x1b25f566, (q31_t)0x34534f41, (q31_t)0x1b303c46, (q31_t)0x345a8a9d,
+    (q31_t)0x1b3a8491, (q31_t)0x3461c3f5, (q31_t)0x1b44ce46, (q31_t)0x3468fb47,
+    (q31_t)0x1b4f1967, (q31_t)0x34703095, (q31_t)0x1b5965f1, (q31_t)0x347763dd,
+    (q31_t)0x1b63b3e5, (q31_t)0x347e951f, (q31_t)0x1b6e0342, (q31_t)0x3485c45b,
+    (q31_t)0x1b785409, (q31_t)0x348cf190, (q31_t)0x1b82a638, (q31_t)0x34941cbf,
+    (q31_t)0x1b8cf9cf, (q31_t)0x349b45e7, (q31_t)0x1b974ece, (q31_t)0x34a26d08,
+    (q31_t)0x1ba1a534, (q31_t)0x34a99221, (q31_t)0x1babfd01, (q31_t)0x34b0b533,
+    (q31_t)0x1bb65634, (q31_t)0x34b7d63c, (q31_t)0x1bc0b0ce, (q31_t)0x34bef53d,
+    (q31_t)0x1bcb0cce, (q31_t)0x34c61236, (q31_t)0x1bd56a32, (q31_t)0x34cd2d26,
+    (q31_t)0x1bdfc8fc, (q31_t)0x34d4460c, (q31_t)0x1bea292b, (q31_t)0x34db5cea,
+    (q31_t)0x1bf48abd, (q31_t)0x34e271bd, (q31_t)0x1bfeedb3, (q31_t)0x34e98487,
+    (q31_t)0x1c09520d, (q31_t)0x34f09546, (q31_t)0x1c13b7c9, (q31_t)0x34f7a3fb,
+    (q31_t)0x1c1e1ee9, (q31_t)0x34feb0a5, (q31_t)0x1c28876a, (q31_t)0x3505bb44,
+    (q31_t)0x1c32f14d, (q31_t)0x350cc3d8, (q31_t)0x1c3d5c91, (q31_t)0x3513ca60,
+    (q31_t)0x1c47c936, (q31_t)0x351acedd, (q31_t)0x1c52373c, (q31_t)0x3521d14d,
+    (q31_t)0x1c5ca6a2, (q31_t)0x3528d1b1, (q31_t)0x1c671768, (q31_t)0x352fd008,
+    (q31_t)0x1c71898d, (q31_t)0x3536cc52, (q31_t)0x1c7bfd11, (q31_t)0x353dc68f,
+    (q31_t)0x1c8671f3, (q31_t)0x3544bebf, (q31_t)0x1c90e834, (q31_t)0x354bb4e1,
+    (q31_t)0x1c9b5fd2, (q31_t)0x3552a8f4, (q31_t)0x1ca5d8cd, (q31_t)0x35599afa,
+    (q31_t)0x1cb05326, (q31_t)0x35608af1, (q31_t)0x1cbacedb, (q31_t)0x356778d9,
+    (q31_t)0x1cc54bec, (q31_t)0x356e64b2, (q31_t)0x1ccfca59, (q31_t)0x35754e7c,
+    (q31_t)0x1cda4a21, (q31_t)0x357c3636, (q31_t)0x1ce4cb44, (q31_t)0x35831be0,
+    (q31_t)0x1cef4dc2, (q31_t)0x3589ff7a, (q31_t)0x1cf9d199, (q31_t)0x3590e104,
+    (q31_t)0x1d0456ca, (q31_t)0x3597c07d, (q31_t)0x1d0edd55, (q31_t)0x359e9de5,
+    (q31_t)0x1d196538, (q31_t)0x35a5793c, (q31_t)0x1d23ee74, (q31_t)0x35ac5282,
+    (q31_t)0x1d2e7908, (q31_t)0x35b329b5, (q31_t)0x1d3904f4, (q31_t)0x35b9fed7,
+    (q31_t)0x1d439236, (q31_t)0x35c0d1e7, (q31_t)0x1d4e20d0, (q31_t)0x35c7a2e3,
+    (q31_t)0x1d58b0c0, (q31_t)0x35ce71ce, (q31_t)0x1d634206, (q31_t)0x35d53ea5,
+    (q31_t)0x1d6dd4a2, (q31_t)0x35dc0968, (q31_t)0x1d786892, (q31_t)0x35e2d219,
+    (q31_t)0x1d82fdd8, (q31_t)0x35e998b5, (q31_t)0x1d8d9472, (q31_t)0x35f05d3d,
+    (q31_t)0x1d982c60, (q31_t)0x35f71fb1, (q31_t)0x1da2c5a2, (q31_t)0x35fde011,
+    (q31_t)0x1dad6036, (q31_t)0x36049e5b, (q31_t)0x1db7fc1e, (q31_t)0x360b5a90,
+    (q31_t)0x1dc29958, (q31_t)0x361214b0, (q31_t)0x1dcd37e4, (q31_t)0x3618ccba,
+    (q31_t)0x1dd7d7c1, (q31_t)0x361f82af, (q31_t)0x1de278ef, (q31_t)0x3626368d,
+    (q31_t)0x1ded1b6e, (q31_t)0x362ce855, (q31_t)0x1df7bf3e, (q31_t)0x36339806,
+    (q31_t)0x1e02645d, (q31_t)0x363a45a0, (q31_t)0x1e0d0acc, (q31_t)0x3640f123,
+    (q31_t)0x1e17b28a, (q31_t)0x36479a8e, (q31_t)0x1e225b96, (q31_t)0x364e41e2,
+    (q31_t)0x1e2d05f1, (q31_t)0x3654e71d, (q31_t)0x1e37b199, (q31_t)0x365b8a41,
+    (q31_t)0x1e425e8f, (q31_t)0x36622b4c, (q31_t)0x1e4d0cd2, (q31_t)0x3668ca3e,
+    (q31_t)0x1e57bc62, (q31_t)0x366f6717, (q31_t)0x1e626d3e, (q31_t)0x367601d7,
+    (q31_t)0x1e6d1f65, (q31_t)0x367c9a7e, (q31_t)0x1e77d2d8, (q31_t)0x3683310b,
+    (q31_t)0x1e828796, (q31_t)0x3689c57d, (q31_t)0x1e8d3d9e, (q31_t)0x369057d6,
+    (q31_t)0x1e97f4f1, (q31_t)0x3696e814, (q31_t)0x1ea2ad8d, (q31_t)0x369d7637,
+    (q31_t)0x1ead6773, (q31_t)0x36a4023f, (q31_t)0x1eb822a1, (q31_t)0x36aa8c2c,
+    (q31_t)0x1ec2df18, (q31_t)0x36b113fd, (q31_t)0x1ecd9cd7, (q31_t)0x36b799b3,
+    (q31_t)0x1ed85bdd, (q31_t)0x36be1d4c, (q31_t)0x1ee31c2b, (q31_t)0x36c49ec9,
+    (q31_t)0x1eedddc0, (q31_t)0x36cb1e2a, (q31_t)0x1ef8a09b, (q31_t)0x36d19b6e,
+    (q31_t)0x1f0364bc, (q31_t)0x36d81695, (q31_t)0x1f0e2a22, (q31_t)0x36de8f9e,
+    (q31_t)0x1f18f0ce, (q31_t)0x36e5068a, (q31_t)0x1f23b8be, (q31_t)0x36eb7b58,
+    (q31_t)0x1f2e81f3, (q31_t)0x36f1ee09, (q31_t)0x1f394c6b, (q31_t)0x36f85e9a,
+    (q31_t)0x1f441828, (q31_t)0x36fecd0e, (q31_t)0x1f4ee527, (q31_t)0x37053962,
+    (q31_t)0x1f59b369, (q31_t)0x370ba398, (q31_t)0x1f6482ed, (q31_t)0x37120bae,
+    (q31_t)0x1f6f53b3, (q31_t)0x371871a5, (q31_t)0x1f7a25ba, (q31_t)0x371ed57c,
+    (q31_t)0x1f84f902, (q31_t)0x37253733, (q31_t)0x1f8fcd8b, (q31_t)0x372b96ca,
+    (q31_t)0x1f9aa354, (q31_t)0x3731f440, (q31_t)0x1fa57a5d, (q31_t)0x37384f95,
+    (q31_t)0x1fb052a5, (q31_t)0x373ea8ca, (q31_t)0x1fbb2c2c, (q31_t)0x3744ffdd,
+    (q31_t)0x1fc606f1, (q31_t)0x374b54ce, (q31_t)0x1fd0e2f5, (q31_t)0x3751a79e,
+    (q31_t)0x1fdbc036, (q31_t)0x3757f84c, (q31_t)0x1fe69eb4, (q31_t)0x375e46d8,
+    (q31_t)0x1ff17e70, (q31_t)0x37649341, (q31_t)0x1ffc5f67, (q31_t)0x376add88,
+    (q31_t)0x2007419b, (q31_t)0x377125ac, (q31_t)0x2012250a, (q31_t)0x37776bac,
+    (q31_t)0x201d09b4, (q31_t)0x377daf89, (q31_t)0x2027ef99, (q31_t)0x3783f143,
+    (q31_t)0x2032d6b8, (q31_t)0x378a30d8, (q31_t)0x203dbf11, (q31_t)0x37906e49,
+    (q31_t)0x2048a8a4, (q31_t)0x3796a996, (q31_t)0x2053936f, (q31_t)0x379ce2be,
+    (q31_t)0x205e7f74, (q31_t)0x37a319c2, (q31_t)0x20696cb0, (q31_t)0x37a94ea0,
+    (q31_t)0x20745b24, (q31_t)0x37af8159, (q31_t)0x207f4acf, (q31_t)0x37b5b1ec,
+    (q31_t)0x208a3bb2, (q31_t)0x37bbe05a, (q31_t)0x20952dcb, (q31_t)0x37c20ca1,
+    (q31_t)0x20a0211a, (q31_t)0x37c836c2, (q31_t)0x20ab159e, (q31_t)0x37ce5ebd,
+    (q31_t)0x20b60b58, (q31_t)0x37d48490, (q31_t)0x20c10247, (q31_t)0x37daa83d,
+    (q31_t)0x20cbfa6a, (q31_t)0x37e0c9c3, (q31_t)0x20d6f3c1, (q31_t)0x37e6e921,
+    (q31_t)0x20e1ee4b, (q31_t)0x37ed0657, (q31_t)0x20ecea09, (q31_t)0x37f32165,
+    (q31_t)0x20f7e6f9, (q31_t)0x37f93a4b, (q31_t)0x2102e51c, (q31_t)0x37ff5109,
+    (q31_t)0x210de470, (q31_t)0x3805659e, (q31_t)0x2118e4f6, (q31_t)0x380b780a,
+    (q31_t)0x2123e6ad, (q31_t)0x3811884d, (q31_t)0x212ee995, (q31_t)0x38179666,
+    (q31_t)0x2139edac, (q31_t)0x381da256, (q31_t)0x2144f2f3, (q31_t)0x3823ac1d,
+    (q31_t)0x214ff96a, (q31_t)0x3829b3b9, (q31_t)0x215b0110, (q31_t)0x382fb92a,
+    (q31_t)0x216609e3, (q31_t)0x3835bc71, (q31_t)0x217113e5, (q31_t)0x383bbd8e,
+    (q31_t)0x217c1f15, (q31_t)0x3841bc7f, (q31_t)0x21872b72, (q31_t)0x3847b946,
+    (q31_t)0x219238fb, (q31_t)0x384db3e0, (q31_t)0x219d47b1, (q31_t)0x3853ac4f,
+    (q31_t)0x21a85793, (q31_t)0x3859a292, (q31_t)0x21b368a0, (q31_t)0x385f96a9,
+    (q31_t)0x21be7ad8, (q31_t)0x38658894, (q31_t)0x21c98e3b, (q31_t)0x386b7852,
+    (q31_t)0x21d4a2c8, (q31_t)0x387165e3, (q31_t)0x21dfb87f, (q31_t)0x38775147,
+    (q31_t)0x21eacf5f, (q31_t)0x387d3a7e, (q31_t)0x21f5e768, (q31_t)0x38832187,
+    (q31_t)0x22010099, (q31_t)0x38890663, (q31_t)0x220c1af3, (q31_t)0x388ee910,
+    (q31_t)0x22173674, (q31_t)0x3894c98f, (q31_t)0x2222531c, (q31_t)0x389aa7e0,
+    (q31_t)0x222d70eb, (q31_t)0x38a08402, (q31_t)0x22388fe1, (q31_t)0x38a65df6,
+    (q31_t)0x2243affc, (q31_t)0x38ac35ba, (q31_t)0x224ed13d, (q31_t)0x38b20b4f,
+    (q31_t)0x2259f3a3, (q31_t)0x38b7deb4, (q31_t)0x2265172e, (q31_t)0x38bdafea,
+    (q31_t)0x22703bdc, (q31_t)0x38c37eef, (q31_t)0x227b61af, (q31_t)0x38c94bc4,
+    (q31_t)0x228688a4, (q31_t)0x38cf1669, (q31_t)0x2291b0bd, (q31_t)0x38d4dedd,
+    (q31_t)0x229cd9f8, (q31_t)0x38daa520, (q31_t)0x22a80456, (q31_t)0x38e06932,
+    (q31_t)0x22b32fd4, (q31_t)0x38e62b13, (q31_t)0x22be5c74, (q31_t)0x38ebeac2,
+    (q31_t)0x22c98a35, (q31_t)0x38f1a840, (q31_t)0x22d4b916, (q31_t)0x38f7638b,
+    (q31_t)0x22dfe917, (q31_t)0x38fd1ca4, (q31_t)0x22eb1a37, (q31_t)0x3902d38b,
+    (q31_t)0x22f64c77, (q31_t)0x3908883f, (q31_t)0x23017fd5, (q31_t)0x390e3ac0,
+    (q31_t)0x230cb451, (q31_t)0x3913eb0e, (q31_t)0x2317e9eb, (q31_t)0x39199929,
+    (q31_t)0x232320a2, (q31_t)0x391f4510, (q31_t)0x232e5876, (q31_t)0x3924eec3,
+    (q31_t)0x23399167, (q31_t)0x392a9642, (q31_t)0x2344cb73, (q31_t)0x39303b8e,
+    (q31_t)0x2350069b, (q31_t)0x3935dea4, (q31_t)0x235b42df, (q31_t)0x393b7f86,
+    (q31_t)0x2366803c, (q31_t)0x39411e33, (q31_t)0x2371beb5, (q31_t)0x3946baac,
+    (q31_t)0x237cfe47, (q31_t)0x394c54ee, (q31_t)0x23883ef2, (q31_t)0x3951ecfc,
+    (q31_t)0x239380b6, (q31_t)0x395782d3, (q31_t)0x239ec393, (q31_t)0x395d1675,
+    (q31_t)0x23aa0788, (q31_t)0x3962a7e0, (q31_t)0x23b54c95, (q31_t)0x39683715,
+    (q31_t)0x23c092b9, (q31_t)0x396dc414, (q31_t)0x23cbd9f4, (q31_t)0x39734edc,
+    (q31_t)0x23d72245, (q31_t)0x3978d76c, (q31_t)0x23e26bac, (q31_t)0x397e5dc6,
+    (q31_t)0x23edb628, (q31_t)0x3983e1e8, (q31_t)0x23f901ba, (q31_t)0x398963d2,
+    (q31_t)0x24044e60, (q31_t)0x398ee385, (q31_t)0x240f9c1a, (q31_t)0x399460ff,
+    (q31_t)0x241aeae8, (q31_t)0x3999dc42, (q31_t)0x24263ac9, (q31_t)0x399f554b,
+    (q31_t)0x24318bbe, (q31_t)0x39a4cc1c, (q31_t)0x243cddc4, (q31_t)0x39aa40b4,
+    (q31_t)0x244830dd, (q31_t)0x39afb313, (q31_t)0x24538507, (q31_t)0x39b52339,
+    (q31_t)0x245eda43, (q31_t)0x39ba9125, (q31_t)0x246a308f, (q31_t)0x39bffcd7,
+    (q31_t)0x247587eb, (q31_t)0x39c5664f, (q31_t)0x2480e057, (q31_t)0x39cacd8d,
+    (q31_t)0x248c39d3, (q31_t)0x39d03291, (q31_t)0x2497945d, (q31_t)0x39d5955a,
+    (q31_t)0x24a2eff6, (q31_t)0x39daf5e8, (q31_t)0x24ae4c9d, (q31_t)0x39e0543c,
+    (q31_t)0x24b9aa52, (q31_t)0x39e5b054, (q31_t)0x24c50914, (q31_t)0x39eb0a31,
+    (q31_t)0x24d068e2, (q31_t)0x39f061d2, (q31_t)0x24dbc9bd, (q31_t)0x39f5b737,
+    (q31_t)0x24e72ba4, (q31_t)0x39fb0a60, (q31_t)0x24f28e96, (q31_t)0x3a005b4d,
+    (q31_t)0x24fdf294, (q31_t)0x3a05a9fd, (q31_t)0x2509579b, (q31_t)0x3a0af671,
+    (q31_t)0x2514bdad, (q31_t)0x3a1040a8, (q31_t)0x252024c9, (q31_t)0x3a1588a2,
+    (q31_t)0x252b8cee, (q31_t)0x3a1ace5f, (q31_t)0x2536f61b, (q31_t)0x3a2011de,
+    (q31_t)0x25426051, (q31_t)0x3a25531f, (q31_t)0x254dcb8f, (q31_t)0x3a2a9223,
+    (q31_t)0x255937d5, (q31_t)0x3a2fcee8, (q31_t)0x2564a521, (q31_t)0x3a350970,
+    (q31_t)0x25701374, (q31_t)0x3a3a41b9, (q31_t)0x257b82cd, (q31_t)0x3a3f77c3,
+    (q31_t)0x2586f32c, (q31_t)0x3a44ab8e, (q31_t)0x25926490, (q31_t)0x3a49dd1a,
+    (q31_t)0x259dd6f9, (q31_t)0x3a4f0c67, (q31_t)0x25a94a67, (q31_t)0x3a543974,
+    (q31_t)0x25b4bed8, (q31_t)0x3a596442, (q31_t)0x25c0344d, (q31_t)0x3a5e8cd0,
+    (q31_t)0x25cbaac5, (q31_t)0x3a63b31d, (q31_t)0x25d72240, (q31_t)0x3a68d72b,
+    (q31_t)0x25e29abc, (q31_t)0x3a6df8f8, (q31_t)0x25ee143b, (q31_t)0x3a731884,
+    (q31_t)0x25f98ebb, (q31_t)0x3a7835cf, (q31_t)0x26050a3b, (q31_t)0x3a7d50da,
+    (q31_t)0x261086bc, (q31_t)0x3a8269a3, (q31_t)0x261c043d, (q31_t)0x3a87802a,
+    (q31_t)0x262782be, (q31_t)0x3a8c9470, (q31_t)0x2633023e, (q31_t)0x3a91a674,
+    (q31_t)0x263e82bc, (q31_t)0x3a96b636, (q31_t)0x264a0438, (q31_t)0x3a9bc3b6,
+    (q31_t)0x265586b3, (q31_t)0x3aa0cef3, (q31_t)0x26610a2a, (q31_t)0x3aa5d7ee,
+    (q31_t)0x266c8e9f, (q31_t)0x3aaadea6, (q31_t)0x26781410, (q31_t)0x3aafe31b,
+    (q31_t)0x26839a7c, (q31_t)0x3ab4e54c, (q31_t)0x268f21e5, (q31_t)0x3ab9e53a,
+    (q31_t)0x269aaa48, (q31_t)0x3abee2e5, (q31_t)0x26a633a6, (q31_t)0x3ac3de4c,
+    (q31_t)0x26b1bdff, (q31_t)0x3ac8d76f, (q31_t)0x26bd4951, (q31_t)0x3acdce4d,
+    (q31_t)0x26c8d59c, (q31_t)0x3ad2c2e8, (q31_t)0x26d462e1, (q31_t)0x3ad7b53d,
+    (q31_t)0x26dff11d, (q31_t)0x3adca54e, (q31_t)0x26eb8052, (q31_t)0x3ae1931a,
+    (q31_t)0x26f7107e, (q31_t)0x3ae67ea1, (q31_t)0x2702a1a1, (q31_t)0x3aeb67e3,
+    (q31_t)0x270e33bb, (q31_t)0x3af04edf, (q31_t)0x2719c6cb, (q31_t)0x3af53395,
+    (q31_t)0x27255ad1, (q31_t)0x3afa1605, (q31_t)0x2730efcc, (q31_t)0x3afef630,
+    (q31_t)0x273c85bc, (q31_t)0x3b03d414, (q31_t)0x27481ca1, (q31_t)0x3b08afb2,
+    (q31_t)0x2753b479, (q31_t)0x3b0d8909, (q31_t)0x275f4d45, (q31_t)0x3b126019,
+    (q31_t)0x276ae704, (q31_t)0x3b1734e2, (q31_t)0x277681b6, (q31_t)0x3b1c0764,
+    (q31_t)0x27821d59, (q31_t)0x3b20d79e, (q31_t)0x278db9ef, (q31_t)0x3b25a591,
+    (q31_t)0x27995776, (q31_t)0x3b2a713d, (q31_t)0x27a4f5ed, (q31_t)0x3b2f3aa0,
+    (q31_t)0x27b09555, (q31_t)0x3b3401bb, (q31_t)0x27bc35ad, (q31_t)0x3b38c68e,
+    (q31_t)0x27c7d6f4, (q31_t)0x3b3d8918, (q31_t)0x27d3792b, (q31_t)0x3b42495a,
+    (q31_t)0x27df1c50, (q31_t)0x3b470753, (q31_t)0x27eac063, (q31_t)0x3b4bc303,
+    (q31_t)0x27f66564, (q31_t)0x3b507c69, (q31_t)0x28020b52, (q31_t)0x3b553386,
+    (q31_t)0x280db22d, (q31_t)0x3b59e85a, (q31_t)0x281959f4, (q31_t)0x3b5e9ae4,
+    (q31_t)0x282502a7, (q31_t)0x3b634b23, (q31_t)0x2830ac45, (q31_t)0x3b67f919,
+    (q31_t)0x283c56cf, (q31_t)0x3b6ca4c4, (q31_t)0x28480243, (q31_t)0x3b714e25,
+    (q31_t)0x2853aea1, (q31_t)0x3b75f53c, (q31_t)0x285f5be9, (q31_t)0x3b7a9a07,
+    (q31_t)0x286b0a1a, (q31_t)0x3b7f3c87, (q31_t)0x2876b934, (q31_t)0x3b83dcbc,
+    (q31_t)0x28826936, (q31_t)0x3b887aa6, (q31_t)0x288e1a20, (q31_t)0x3b8d1644,
+    (q31_t)0x2899cbf1, (q31_t)0x3b91af97, (q31_t)0x28a57ea9, (q31_t)0x3b96469d,
+    (q31_t)0x28b13248, (q31_t)0x3b9adb57, (q31_t)0x28bce6cd, (q31_t)0x3b9f6dc5,
+    (q31_t)0x28c89c37, (q31_t)0x3ba3fde7, (q31_t)0x28d45286, (q31_t)0x3ba88bbc,
+    (q31_t)0x28e009ba, (q31_t)0x3bad1744, (q31_t)0x28ebc1d3, (q31_t)0x3bb1a080,
+    (q31_t)0x28f77acf, (q31_t)0x3bb6276e, (q31_t)0x290334af, (q31_t)0x3bbaac0e,
+    (q31_t)0x290eef71, (q31_t)0x3bbf2e62, (q31_t)0x291aab16, (q31_t)0x3bc3ae67,
+    (q31_t)0x2926679c, (q31_t)0x3bc82c1f, (q31_t)0x29322505, (q31_t)0x3bcca789,
+    (q31_t)0x293de34e, (q31_t)0x3bd120a4, (q31_t)0x2949a278, (q31_t)0x3bd59771,
+    (q31_t)0x29556282, (q31_t)0x3bda0bf0, (q31_t)0x2961236c, (q31_t)0x3bde7e20,
+    (q31_t)0x296ce535, (q31_t)0x3be2ee01, (q31_t)0x2978a7dd, (q31_t)0x3be75b93,
+    (q31_t)0x29846b63, (q31_t)0x3bebc6d5, (q31_t)0x29902fc7, (q31_t)0x3bf02fc9,
+    (q31_t)0x299bf509, (q31_t)0x3bf4966c, (q31_t)0x29a7bb28, (q31_t)0x3bf8fac0,
+    (q31_t)0x29b38223, (q31_t)0x3bfd5cc4, (q31_t)0x29bf49fa, (q31_t)0x3c01bc78,
+    (q31_t)0x29cb12ad, (q31_t)0x3c0619dc, (q31_t)0x29d6dc3b, (q31_t)0x3c0a74f0,
+    (q31_t)0x29e2a6a3, (q31_t)0x3c0ecdb2, (q31_t)0x29ee71e6, (q31_t)0x3c132424,
+    (q31_t)0x29fa3e03, (q31_t)0x3c177845, (q31_t)0x2a060af9, (q31_t)0x3c1bca16,
+    (q31_t)0x2a11d8c8, (q31_t)0x3c201994, (q31_t)0x2a1da770, (q31_t)0x3c2466c2,
+    (q31_t)0x2a2976ef, (q31_t)0x3c28b19e, (q31_t)0x2a354746, (q31_t)0x3c2cfa28,
+    (q31_t)0x2a411874, (q31_t)0x3c314060, (q31_t)0x2a4cea79, (q31_t)0x3c358446,
+    (q31_t)0x2a58bd54, (q31_t)0x3c39c5da, (q31_t)0x2a649105, (q31_t)0x3c3e051b,
+    (q31_t)0x2a70658a, (q31_t)0x3c42420a, (q31_t)0x2a7c3ae5, (q31_t)0x3c467ca6,
+    (q31_t)0x2a881114, (q31_t)0x3c4ab4ef, (q31_t)0x2a93e817, (q31_t)0x3c4eeae5,
+    (q31_t)0x2a9fbfed, (q31_t)0x3c531e88, (q31_t)0x2aab9896, (q31_t)0x3c574fd8,
+    (q31_t)0x2ab77212, (q31_t)0x3c5b7ed4, (q31_t)0x2ac34c60, (q31_t)0x3c5fab7c,
+    (q31_t)0x2acf277f, (q31_t)0x3c63d5d1, (q31_t)0x2adb0370, (q31_t)0x3c67fdd1,
+    (q31_t)0x2ae6e031, (q31_t)0x3c6c237e, (q31_t)0x2af2bdc3, (q31_t)0x3c7046d6,
+    (q31_t)0x2afe9c24, (q31_t)0x3c7467d9, (q31_t)0x2b0a7b54, (q31_t)0x3c788688,
+    (q31_t)0x2b165b54, (q31_t)0x3c7ca2e2, (q31_t)0x2b223c22, (q31_t)0x3c80bce7,
+    (q31_t)0x2b2e1dbe, (q31_t)0x3c84d496, (q31_t)0x2b3a0027, (q31_t)0x3c88e9f1,
+    (q31_t)0x2b45e35d, (q31_t)0x3c8cfcf6, (q31_t)0x2b51c760, (q31_t)0x3c910da5,
+    (q31_t)0x2b5dac2f, (q31_t)0x3c951bff, (q31_t)0x2b6991ca, (q31_t)0x3c992803,
+    (q31_t)0x2b75782f, (q31_t)0x3c9d31b0, (q31_t)0x2b815f60, (q31_t)0x3ca13908,
+    (q31_t)0x2b8d475b, (q31_t)0x3ca53e09, (q31_t)0x2b99301f, (q31_t)0x3ca940b3,
+    (q31_t)0x2ba519ad, (q31_t)0x3cad4107, (q31_t)0x2bb10404, (q31_t)0x3cb13f04,
+    (q31_t)0x2bbcef23, (q31_t)0x3cb53aaa, (q31_t)0x2bc8db0b, (q31_t)0x3cb933f9,
+    (q31_t)0x2bd4c7ba, (q31_t)0x3cbd2af0, (q31_t)0x2be0b52f, (q31_t)0x3cc11f90,
+    (q31_t)0x2beca36c, (q31_t)0x3cc511d9, (q31_t)0x2bf8926f, (q31_t)0x3cc901c9,
+    (q31_t)0x2c048237, (q31_t)0x3cccef62, (q31_t)0x2c1072c4, (q31_t)0x3cd0daa2,
+    (q31_t)0x2c1c6417, (q31_t)0x3cd4c38b, (q31_t)0x2c28562d, (q31_t)0x3cd8aa1b,
+    (q31_t)0x2c344908, (q31_t)0x3cdc8e52, (q31_t)0x2c403ca5, (q31_t)0x3ce07031,
+    (q31_t)0x2c4c3106, (q31_t)0x3ce44fb7, (q31_t)0x2c582629, (q31_t)0x3ce82ce4,
+    (q31_t)0x2c641c0e, (q31_t)0x3cec07b8, (q31_t)0x2c7012b5, (q31_t)0x3cefe032,
+    (q31_t)0x2c7c0a1d, (q31_t)0x3cf3b653, (q31_t)0x2c880245, (q31_t)0x3cf78a1b,
+    (q31_t)0x2c93fb2e, (q31_t)0x3cfb5b89, (q31_t)0x2c9ff4d6, (q31_t)0x3cff2a9d,
+    (q31_t)0x2cabef3d, (q31_t)0x3d02f757, (q31_t)0x2cb7ea63, (q31_t)0x3d06c1b6,
+    (q31_t)0x2cc3e648, (q31_t)0x3d0a89bc, (q31_t)0x2ccfe2ea, (q31_t)0x3d0e4f67,
+    (q31_t)0x2cdbe04a, (q31_t)0x3d1212b7, (q31_t)0x2ce7de66, (q31_t)0x3d15d3ad,
+    (q31_t)0x2cf3dd3f, (q31_t)0x3d199248, (q31_t)0x2cffdcd4, (q31_t)0x3d1d4e88,
+    (q31_t)0x2d0bdd25, (q31_t)0x3d21086c, (q31_t)0x2d17de31, (q31_t)0x3d24bff6,
+    (q31_t)0x2d23dff7, (q31_t)0x3d287523, (q31_t)0x2d2fe277, (q31_t)0x3d2c27f6,
+    (q31_t)0x2d3be5b1, (q31_t)0x3d2fd86c, (q31_t)0x2d47e9a5, (q31_t)0x3d338687,
+    (q31_t)0x2d53ee51, (q31_t)0x3d373245, (q31_t)0x2d5ff3b5, (q31_t)0x3d3adba7,
+    (q31_t)0x2d6bf9d1, (q31_t)0x3d3e82ae, (q31_t)0x2d7800a5, (q31_t)0x3d422757,
+    (q31_t)0x2d84082f, (q31_t)0x3d45c9a4, (q31_t)0x2d901070, (q31_t)0x3d496994,
+    (q31_t)0x2d9c1967, (q31_t)0x3d4d0728, (q31_t)0x2da82313, (q31_t)0x3d50a25e,
+    (q31_t)0x2db42d74, (q31_t)0x3d543b37, (q31_t)0x2dc0388a, (q31_t)0x3d57d1b3,
+    (q31_t)0x2dcc4454, (q31_t)0x3d5b65d2, (q31_t)0x2dd850d2, (q31_t)0x3d5ef793,
+    (q31_t)0x2de45e03, (q31_t)0x3d6286f6, (q31_t)0x2df06be6, (q31_t)0x3d6613fb,
+    (q31_t)0x2dfc7a7c, (q31_t)0x3d699ea3, (q31_t)0x2e0889c4, (q31_t)0x3d6d26ec,
+    (q31_t)0x2e1499bd, (q31_t)0x3d70acd7, (q31_t)0x2e20aa67, (q31_t)0x3d743064,
+    (q31_t)0x2e2cbbc1, (q31_t)0x3d77b192, (q31_t)0x2e38cdcb, (q31_t)0x3d7b3061,
+    (q31_t)0x2e44e084, (q31_t)0x3d7eacd2, (q31_t)0x2e50f3ed, (q31_t)0x3d8226e4,
+    (q31_t)0x2e5d0804, (q31_t)0x3d859e96, (q31_t)0x2e691cc9, (q31_t)0x3d8913ea,
+    (q31_t)0x2e75323c, (q31_t)0x3d8c86de, (q31_t)0x2e81485c, (q31_t)0x3d8ff772,
+    (q31_t)0x2e8d5f29, (q31_t)0x3d9365a8, (q31_t)0x2e9976a1, (q31_t)0x3d96d17d,
+    (q31_t)0x2ea58ec6, (q31_t)0x3d9a3af2, (q31_t)0x2eb1a796, (q31_t)0x3d9da208,
+    (q31_t)0x2ebdc110, (q31_t)0x3da106bd, (q31_t)0x2ec9db35, (q31_t)0x3da46912,
+    (q31_t)0x2ed5f604, (q31_t)0x3da7c907, (q31_t)0x2ee2117c, (q31_t)0x3dab269b,
+    (q31_t)0x2eee2d9d, (q31_t)0x3dae81cf, (q31_t)0x2efa4a67, (q31_t)0x3db1daa2,
+    (q31_t)0x2f0667d9, (q31_t)0x3db53113, (q31_t)0x2f1285f2, (q31_t)0x3db88524,
+    (q31_t)0x2f1ea4b2, (q31_t)0x3dbbd6d4, (q31_t)0x2f2ac419, (q31_t)0x3dbf2622,
+    (q31_t)0x2f36e426, (q31_t)0x3dc2730f, (q31_t)0x2f4304d8, (q31_t)0x3dc5bd9b,
+    (q31_t)0x2f4f2630, (q31_t)0x3dc905c5, (q31_t)0x2f5b482d, (q31_t)0x3dcc4b8d,
+    (q31_t)0x2f676ace, (q31_t)0x3dcf8ef3, (q31_t)0x2f738e12, (q31_t)0x3dd2cff7,
+    (q31_t)0x2f7fb1fa, (q31_t)0x3dd60e99, (q31_t)0x2f8bd685, (q31_t)0x3dd94ad8,
+    (q31_t)0x2f97fbb2, (q31_t)0x3ddc84b5, (q31_t)0x2fa42181, (q31_t)0x3ddfbc30,
+    (q31_t)0x2fb047f2, (q31_t)0x3de2f148, (q31_t)0x2fbc6f03, (q31_t)0x3de623fd,
+    (q31_t)0x2fc896b5, (q31_t)0x3de9544f, (q31_t)0x2fd4bf08, (q31_t)0x3dec823e,
+    (q31_t)0x2fe0e7f9, (q31_t)0x3defadca, (q31_t)0x2fed118a, (q31_t)0x3df2d6f3,
+    (q31_t)0x2ff93bba, (q31_t)0x3df5fdb8, (q31_t)0x30056687, (q31_t)0x3df9221a,
+    (q31_t)0x301191f3, (q31_t)0x3dfc4418, (q31_t)0x301dbdfb, (q31_t)0x3dff63b2,
+    (q31_t)0x3029eaa1, (q31_t)0x3e0280e9, (q31_t)0x303617e2, (q31_t)0x3e059bbb,
+    (q31_t)0x304245c0, (q31_t)0x3e08b42a, (q31_t)0x304e7438, (q31_t)0x3e0bca34,
+    (q31_t)0x305aa34c, (q31_t)0x3e0eddd9, (q31_t)0x3066d2fa, (q31_t)0x3e11ef1b,
+    (q31_t)0x30730342, (q31_t)0x3e14fdf7, (q31_t)0x307f3424, (q31_t)0x3e180a6f,
+    (q31_t)0x308b659f, (q31_t)0x3e1b1482, (q31_t)0x309797b2, (q31_t)0x3e1e1c30,
+    (q31_t)0x30a3ca5d, (q31_t)0x3e212179, (q31_t)0x30affda0, (q31_t)0x3e24245d,
+    (q31_t)0x30bc317a, (q31_t)0x3e2724db, (q31_t)0x30c865ea, (q31_t)0x3e2a22f4,
+    (q31_t)0x30d49af1, (q31_t)0x3e2d1ea8, (q31_t)0x30e0d08d, (q31_t)0x3e3017f6,
+    (q31_t)0x30ed06bf, (q31_t)0x3e330ede, (q31_t)0x30f93d86, (q31_t)0x3e360360,
+    (q31_t)0x310574e0, (q31_t)0x3e38f57c, (q31_t)0x3111accf, (q31_t)0x3e3be532,
+    (q31_t)0x311de551, (q31_t)0x3e3ed282, (q31_t)0x312a1e66, (q31_t)0x3e41bd6c,
+    (q31_t)0x3136580d, (q31_t)0x3e44a5ef, (q31_t)0x31429247, (q31_t)0x3e478c0b,
+    (q31_t)0x314ecd11, (q31_t)0x3e4a6fc1, (q31_t)0x315b086d, (q31_t)0x3e4d5110,
+    (q31_t)0x31674459, (q31_t)0x3e502ff9, (q31_t)0x317380d6, (q31_t)0x3e530c7a,
+    (q31_t)0x317fbde2, (q31_t)0x3e55e694, (q31_t)0x318bfb7d, (q31_t)0x3e58be47,
+    (q31_t)0x319839a6, (q31_t)0x3e5b9392, (q31_t)0x31a4785e, (q31_t)0x3e5e6676,
+    (q31_t)0x31b0b7a4, (q31_t)0x3e6136f3, (q31_t)0x31bcf777, (q31_t)0x3e640507,
+    (q31_t)0x31c937d6, (q31_t)0x3e66d0b4, (q31_t)0x31d578c2, (q31_t)0x3e6999fa,
+    (q31_t)0x31e1ba3a, (q31_t)0x3e6c60d7, (q31_t)0x31edfc3d, (q31_t)0x3e6f254c,
+    (q31_t)0x31fa3ecb, (q31_t)0x3e71e759, (q31_t)0x320681e3, (q31_t)0x3e74a6fd,
+    (q31_t)0x3212c585, (q31_t)0x3e77643a, (q31_t)0x321f09b1, (q31_t)0x3e7a1f0d,
+    (q31_t)0x322b4e66, (q31_t)0x3e7cd778, (q31_t)0x323793a3, (q31_t)0x3e7f8d7b,
+    (q31_t)0x3243d968, (q31_t)0x3e824114, (q31_t)0x32501fb5, (q31_t)0x3e84f245,
+    (q31_t)0x325c6688, (q31_t)0x3e87a10c, (q31_t)0x3268ade3, (q31_t)0x3e8a4d6a,
+    (q31_t)0x3274f5c3, (q31_t)0x3e8cf75f, (q31_t)0x32813e2a, (q31_t)0x3e8f9eeb,
+    (q31_t)0x328d8715, (q31_t)0x3e92440d, (q31_t)0x3299d085, (q31_t)0x3e94e6c6,
+    (q31_t)0x32a61a7a, (q31_t)0x3e978715, (q31_t)0x32b264f2, (q31_t)0x3e9a24fb,
+    (q31_t)0x32beafed, (q31_t)0x3e9cc076, (q31_t)0x32cafb6b, (q31_t)0x3e9f5988,
+    (q31_t)0x32d7476c, (q31_t)0x3ea1f02f, (q31_t)0x32e393ef, (q31_t)0x3ea4846c,
+    (q31_t)0x32efe0f2, (q31_t)0x3ea7163f, (q31_t)0x32fc2e77, (q31_t)0x3ea9a5a8,
+    (q31_t)0x33087c7d, (q31_t)0x3eac32a6, (q31_t)0x3314cb02, (q31_t)0x3eaebd3a,
+    (q31_t)0x33211a07, (q31_t)0x3eb14563, (q31_t)0x332d698a, (q31_t)0x3eb3cb21,
+    (q31_t)0x3339b98d, (q31_t)0x3eb64e75, (q31_t)0x33460a0d, (q31_t)0x3eb8cf5d,
+    (q31_t)0x33525b0b, (q31_t)0x3ebb4ddb, (q31_t)0x335eac86, (q31_t)0x3ebdc9ed,
+    (q31_t)0x336afe7e, (q31_t)0x3ec04394, (q31_t)0x337750f2, (q31_t)0x3ec2bad0,
+    (q31_t)0x3383a3e2, (q31_t)0x3ec52fa0, (q31_t)0x338ff74d, (q31_t)0x3ec7a205,
+    (q31_t)0x339c4b32, (q31_t)0x3eca11fe, (q31_t)0x33a89f92, (q31_t)0x3ecc7f8b,
+    (q31_t)0x33b4f46c, (q31_t)0x3eceeaad, (q31_t)0x33c149bf, (q31_t)0x3ed15363,
+    (q31_t)0x33cd9f8b, (q31_t)0x3ed3b9ad, (q31_t)0x33d9f5cf, (q31_t)0x3ed61d8a,
+    (q31_t)0x33e64c8c, (q31_t)0x3ed87efc, (q31_t)0x33f2a3bf, (q31_t)0x3edade01,
+    (q31_t)0x33fefb6a, (q31_t)0x3edd3a9a, (q31_t)0x340b538b, (q31_t)0x3edf94c7,
+    (q31_t)0x3417ac22, (q31_t)0x3ee1ec87, (q31_t)0x3424052f, (q31_t)0x3ee441da,
+    (q31_t)0x34305eb0, (q31_t)0x3ee694c1, (q31_t)0x343cb8a7, (q31_t)0x3ee8e53a,
+    (q31_t)0x34491311, (q31_t)0x3eeb3347, (q31_t)0x34556def, (q31_t)0x3eed7ee7,
+    (q31_t)0x3461c940, (q31_t)0x3eefc81a, (q31_t)0x346e2504, (q31_t)0x3ef20ee0,
+    (q31_t)0x347a8139, (q31_t)0x3ef45338, (q31_t)0x3486dde1, (q31_t)0x3ef69523,
+    (q31_t)0x34933afa, (q31_t)0x3ef8d4a1, (q31_t)0x349f9884, (q31_t)0x3efb11b1,
+    (q31_t)0x34abf67e, (q31_t)0x3efd4c54, (q31_t)0x34b854e7, (q31_t)0x3eff8489,
+    (q31_t)0x34c4b3c0, (q31_t)0x3f01ba50, (q31_t)0x34d11308, (q31_t)0x3f03eda9,
+    (q31_t)0x34dd72be, (q31_t)0x3f061e95, (q31_t)0x34e9d2e3, (q31_t)0x3f084d12,
+    (q31_t)0x34f63374, (q31_t)0x3f0a7921, (q31_t)0x35029473, (q31_t)0x3f0ca2c2,
+    (q31_t)0x350ef5de, (q31_t)0x3f0ec9f5, (q31_t)0x351b57b5, (q31_t)0x3f10eeb9,
+    (q31_t)0x3527b9f7, (q31_t)0x3f13110f, (q31_t)0x35341ca5, (q31_t)0x3f1530f7,
+    (q31_t)0x35407fbd, (q31_t)0x3f174e70, (q31_t)0x354ce33f, (q31_t)0x3f19697a,
+    (q31_t)0x3559472b, (q31_t)0x3f1b8215, (q31_t)0x3565ab80, (q31_t)0x3f1d9842,
+    (q31_t)0x3572103d, (q31_t)0x3f1fabff, (q31_t)0x357e7563, (q31_t)0x3f21bd4e,
+    (q31_t)0x358adaf0, (q31_t)0x3f23cc2e, (q31_t)0x359740e5, (q31_t)0x3f25d89e,
+    (q31_t)0x35a3a740, (q31_t)0x3f27e29f, (q31_t)0x35b00e02, (q31_t)0x3f29ea31,
+    (q31_t)0x35bc7529, (q31_t)0x3f2bef53, (q31_t)0x35c8dcb6, (q31_t)0x3f2df206,
+    (q31_t)0x35d544a7, (q31_t)0x3f2ff24a, (q31_t)0x35e1acfd, (q31_t)0x3f31f01d,
+    (q31_t)0x35ee15b7, (q31_t)0x3f33eb81, (q31_t)0x35fa7ed4, (q31_t)0x3f35e476,
+    (q31_t)0x3606e854, (q31_t)0x3f37dafa, (q31_t)0x36135237, (q31_t)0x3f39cf0e,
+    (q31_t)0x361fbc7b, (q31_t)0x3f3bc0b3, (q31_t)0x362c2721, (q31_t)0x3f3dafe7,
+    (q31_t)0x36389228, (q31_t)0x3f3f9cab, (q31_t)0x3644fd8f, (q31_t)0x3f4186ff,
+    (q31_t)0x36516956, (q31_t)0x3f436ee3, (q31_t)0x365dd57d, (q31_t)0x3f455456,
+    (q31_t)0x366a4203, (q31_t)0x3f473759, (q31_t)0x3676aee8, (q31_t)0x3f4917eb,
+    (q31_t)0x36831c2b, (q31_t)0x3f4af60d, (q31_t)0x368f89cb, (q31_t)0x3f4cd1be,
+    (q31_t)0x369bf7c9, (q31_t)0x3f4eaafe, (q31_t)0x36a86623, (q31_t)0x3f5081cd,
+    (q31_t)0x36b4d4d9, (q31_t)0x3f52562c, (q31_t)0x36c143ec, (q31_t)0x3f54281a,
+    (q31_t)0x36cdb359, (q31_t)0x3f55f796, (q31_t)0x36da2321, (q31_t)0x3f57c4a2,
+    (q31_t)0x36e69344, (q31_t)0x3f598f3c, (q31_t)0x36f303c0, (q31_t)0x3f5b5765,
+    (q31_t)0x36ff7496, (q31_t)0x3f5d1d1d, (q31_t)0x370be5c4, (q31_t)0x3f5ee063,
+    (q31_t)0x3718574b, (q31_t)0x3f60a138, (q31_t)0x3724c92a, (q31_t)0x3f625f9b,
+    (q31_t)0x37313b60, (q31_t)0x3f641b8d, (q31_t)0x373daded, (q31_t)0x3f65d50d,
+    (q31_t)0x374a20d0, (q31_t)0x3f678c1c, (q31_t)0x3756940a, (q31_t)0x3f6940b8,
+    (q31_t)0x37630799, (q31_t)0x3f6af2e3, (q31_t)0x376f7b7d, (q31_t)0x3f6ca29c,
+    (q31_t)0x377befb5, (q31_t)0x3f6e4fe3, (q31_t)0x37886442, (q31_t)0x3f6ffab8,
+    (q31_t)0x3794d922, (q31_t)0x3f71a31b, (q31_t)0x37a14e55, (q31_t)0x3f73490b,
+    (q31_t)0x37adc3db, (q31_t)0x3f74ec8a, (q31_t)0x37ba39b3, (q31_t)0x3f768d96,
+    (q31_t)0x37c6afdc, (q31_t)0x3f782c30, (q31_t)0x37d32657, (q31_t)0x3f79c857,
+    (q31_t)0x37df9d22, (q31_t)0x3f7b620c, (q31_t)0x37ec143e, (q31_t)0x3f7cf94e,
+    (q31_t)0x37f88ba9, (q31_t)0x3f7e8e1e, (q31_t)0x38050364, (q31_t)0x3f80207b,
+    (q31_t)0x38117b6d, (q31_t)0x3f81b065, (q31_t)0x381df3c5, (q31_t)0x3f833ddd,
+    (q31_t)0x382a6c6a, (q31_t)0x3f84c8e2, (q31_t)0x3836e55d, (q31_t)0x3f865174,
+    (q31_t)0x38435e9d, (q31_t)0x3f87d792, (q31_t)0x384fd829, (q31_t)0x3f895b3e,
+    (q31_t)0x385c5201, (q31_t)0x3f8adc77, (q31_t)0x3868cc24, (q31_t)0x3f8c5b3d,
+    (q31_t)0x38754692, (q31_t)0x3f8dd78f, (q31_t)0x3881c14b, (q31_t)0x3f8f516e,
+    (q31_t)0x388e3c4d, (q31_t)0x3f90c8da, (q31_t)0x389ab799, (q31_t)0x3f923dd2,
+    (q31_t)0x38a7332e, (q31_t)0x3f93b058, (q31_t)0x38b3af0c, (q31_t)0x3f952069,
+    (q31_t)0x38c02b31, (q31_t)0x3f968e07, (q31_t)0x38cca79e, (q31_t)0x3f97f932,
+    (q31_t)0x38d92452, (q31_t)0x3f9961e8, (q31_t)0x38e5a14d, (q31_t)0x3f9ac82c,
+    (q31_t)0x38f21e8e, (q31_t)0x3f9c2bfb, (q31_t)0x38fe9c15, (q31_t)0x3f9d8d56,
+    (q31_t)0x390b19e0, (q31_t)0x3f9eec3e, (q31_t)0x391797f0, (q31_t)0x3fa048b2,
+    (q31_t)0x39241645, (q31_t)0x3fa1a2b2, (q31_t)0x393094dd, (q31_t)0x3fa2fa3d,
+    (q31_t)0x393d13b8, (q31_t)0x3fa44f55, (q31_t)0x394992d7, (q31_t)0x3fa5a1f9,
+    (q31_t)0x39561237, (q31_t)0x3fa6f228, (q31_t)0x396291d9, (q31_t)0x3fa83fe3,
+    (q31_t)0x396f11bc, (q31_t)0x3fa98b2a, (q31_t)0x397b91e1, (q31_t)0x3faad3fd,
+    (q31_t)0x39881245, (q31_t)0x3fac1a5b, (q31_t)0x399492ea, (q31_t)0x3fad5e45,
+    (q31_t)0x39a113cd, (q31_t)0x3fae9fbb, (q31_t)0x39ad94f0, (q31_t)0x3fafdebb,
+    (q31_t)0x39ba1651, (q31_t)0x3fb11b48, (q31_t)0x39c697f0, (q31_t)0x3fb2555f,
+    (q31_t)0x39d319cc, (q31_t)0x3fb38d02, (q31_t)0x39df9be6, (q31_t)0x3fb4c231,
+    (q31_t)0x39ec1e3b, (q31_t)0x3fb5f4ea, (q31_t)0x39f8a0cd, (q31_t)0x3fb7252f,
+    (q31_t)0x3a05239a, (q31_t)0x3fb852ff, (q31_t)0x3a11a6a3, (q31_t)0x3fb97e5a,
+    (q31_t)0x3a1e29e5, (q31_t)0x3fbaa740, (q31_t)0x3a2aad62, (q31_t)0x3fbbcdb1,
+    (q31_t)0x3a373119, (q31_t)0x3fbcf1ad, (q31_t)0x3a43b508, (q31_t)0x3fbe1334,
+    (q31_t)0x3a503930, (q31_t)0x3fbf3246, (q31_t)0x3a5cbd91, (q31_t)0x3fc04ee3,
+    (q31_t)0x3a694229, (q31_t)0x3fc1690a, (q31_t)0x3a75c6f8, (q31_t)0x3fc280bc,
+    (q31_t)0x3a824bfd, (q31_t)0x3fc395f9, (q31_t)0x3a8ed139, (q31_t)0x3fc4a8c1,
+    (q31_t)0x3a9b56ab, (q31_t)0x3fc5b913, (q31_t)0x3aa7dc52, (q31_t)0x3fc6c6f0,
+    (q31_t)0x3ab4622d, (q31_t)0x3fc7d258, (q31_t)0x3ac0e83d, (q31_t)0x3fc8db4a,
+    (q31_t)0x3acd6e81, (q31_t)0x3fc9e1c6, (q31_t)0x3ad9f4f8, (q31_t)0x3fcae5cd,
+    (q31_t)0x3ae67ba2, (q31_t)0x3fcbe75e, (q31_t)0x3af3027e, (q31_t)0x3fcce67a,
+    (q31_t)0x3aff898c, (q31_t)0x3fcde320, (q31_t)0x3b0c10cb, (q31_t)0x3fcedd50,
+    (q31_t)0x3b18983b, (q31_t)0x3fcfd50b, (q31_t)0x3b251fdc, (q31_t)0x3fd0ca4f,
+    (q31_t)0x3b31a7ac, (q31_t)0x3fd1bd1e, (q31_t)0x3b3e2fac, (q31_t)0x3fd2ad77,
+    (q31_t)0x3b4ab7db, (q31_t)0x3fd39b5a, (q31_t)0x3b574039, (q31_t)0x3fd486c7,
+    (q31_t)0x3b63c8c4, (q31_t)0x3fd56fbe, (q31_t)0x3b70517d, (q31_t)0x3fd6563f,
+    (q31_t)0x3b7cda63, (q31_t)0x3fd73a4a, (q31_t)0x3b896375, (q31_t)0x3fd81bdf,
+    (q31_t)0x3b95ecb4, (q31_t)0x3fd8fafe, (q31_t)0x3ba2761e, (q31_t)0x3fd9d7a7,
+    (q31_t)0x3baeffb3, (q31_t)0x3fdab1d9, (q31_t)0x3bbb8973, (q31_t)0x3fdb8996,
+    (q31_t)0x3bc8135c, (q31_t)0x3fdc5edc, (q31_t)0x3bd49d70, (q31_t)0x3fdd31ac,
+    (q31_t)0x3be127ac, (q31_t)0x3fde0205, (q31_t)0x3bedb212, (q31_t)0x3fdecfe8,
+    (q31_t)0x3bfa3c9f, (q31_t)0x3fdf9b55, (q31_t)0x3c06c754, (q31_t)0x3fe0644b,
+    (q31_t)0x3c135231, (q31_t)0x3fe12acb, (q31_t)0x3c1fdd34, (q31_t)0x3fe1eed5,
+    (q31_t)0x3c2c685d, (q31_t)0x3fe2b067, (q31_t)0x3c38f3ac, (q31_t)0x3fe36f84,
+    (q31_t)0x3c457f21, (q31_t)0x3fe42c2a, (q31_t)0x3c520aba, (q31_t)0x3fe4e659,
+    (q31_t)0x3c5e9678, (q31_t)0x3fe59e12, (q31_t)0x3c6b2259, (q31_t)0x3fe65354,
+    (q31_t)0x3c77ae5e, (q31_t)0x3fe7061f, (q31_t)0x3c843a85, (q31_t)0x3fe7b674,
+    (q31_t)0x3c90c6cf, (q31_t)0x3fe86452, (q31_t)0x3c9d533b, (q31_t)0x3fe90fb9,
+    (q31_t)0x3ca9dfc8, (q31_t)0x3fe9b8a9, (q31_t)0x3cb66c77, (q31_t)0x3fea5f23,
+    (q31_t)0x3cc2f945, (q31_t)0x3feb0326, (q31_t)0x3ccf8634, (q31_t)0x3feba4b2,
+    (q31_t)0x3cdc1342, (q31_t)0x3fec43c7, (q31_t)0x3ce8a06f, (q31_t)0x3fece065,
+    (q31_t)0x3cf52dbb, (q31_t)0x3fed7a8c, (q31_t)0x3d01bb24, (q31_t)0x3fee123d,
+    (q31_t)0x3d0e48ab, (q31_t)0x3feea776, (q31_t)0x3d1ad650, (q31_t)0x3fef3a39,
+    (q31_t)0x3d276410, (q31_t)0x3fefca84, (q31_t)0x3d33f1ed, (q31_t)0x3ff05858,
+    (q31_t)0x3d407fe6, (q31_t)0x3ff0e3b6, (q31_t)0x3d4d0df9, (q31_t)0x3ff16c9c,
+    (q31_t)0x3d599c28, (q31_t)0x3ff1f30b, (q31_t)0x3d662a70, (q31_t)0x3ff27703,
+    (q31_t)0x3d72b8d2, (q31_t)0x3ff2f884, (q31_t)0x3d7f474d, (q31_t)0x3ff3778e,
+    (q31_t)0x3d8bd5e1, (q31_t)0x3ff3f420, (q31_t)0x3d98648d, (q31_t)0x3ff46e3c,
+    (q31_t)0x3da4f351, (q31_t)0x3ff4e5e0, (q31_t)0x3db1822c, (q31_t)0x3ff55b0d,
+    (q31_t)0x3dbe111e, (q31_t)0x3ff5cdc3, (q31_t)0x3dcaa027, (q31_t)0x3ff63e01,
+    (q31_t)0x3dd72f45, (q31_t)0x3ff6abc8, (q31_t)0x3de3be78, (q31_t)0x3ff71718,
+    (q31_t)0x3df04dc0, (q31_t)0x3ff77ff1, (q31_t)0x3dfcdd1d, (q31_t)0x3ff7e652,
+    (q31_t)0x3e096c8d, (q31_t)0x3ff84a3c, (q31_t)0x3e15fc11, (q31_t)0x3ff8abae,
+    (q31_t)0x3e228ba7, (q31_t)0x3ff90aaa, (q31_t)0x3e2f1b50, (q31_t)0x3ff9672d,
+    (q31_t)0x3e3bab0b, (q31_t)0x3ff9c13a, (q31_t)0x3e483ad8, (q31_t)0x3ffa18cf,
+    (q31_t)0x3e54cab5, (q31_t)0x3ffa6dec, (q31_t)0x3e615aa3, (q31_t)0x3ffac092,
+    (q31_t)0x3e6deaa1, (q31_t)0x3ffb10c1, (q31_t)0x3e7a7aae, (q31_t)0x3ffb5e78,
+    (q31_t)0x3e870aca, (q31_t)0x3ffba9b8, (q31_t)0x3e939af5, (q31_t)0x3ffbf280,
+    (q31_t)0x3ea02b2e, (q31_t)0x3ffc38d1, (q31_t)0x3eacbb74, (q31_t)0x3ffc7caa,
+    (q31_t)0x3eb94bc8, (q31_t)0x3ffcbe0c, (q31_t)0x3ec5dc28, (q31_t)0x3ffcfcf6,
+    (q31_t)0x3ed26c94, (q31_t)0x3ffd3969, (q31_t)0x3edefd0c, (q31_t)0x3ffd7364,
+    (q31_t)0x3eeb8d8f, (q31_t)0x3ffdaae7, (q31_t)0x3ef81e1d, (q31_t)0x3ffddff3,
+    (q31_t)0x3f04aeb5, (q31_t)0x3ffe1288, (q31_t)0x3f113f56, (q31_t)0x3ffe42a4,
+    (q31_t)0x3f1dd001, (q31_t)0x3ffe704a, (q31_t)0x3f2a60b4, (q31_t)0x3ffe9b77,
+    (q31_t)0x3f36f170, (q31_t)0x3ffec42d, (q31_t)0x3f438234, (q31_t)0x3ffeea6c,
+    (q31_t)0x3f5012fe, (q31_t)0x3fff0e32, (q31_t)0x3f5ca3d0, (q31_t)0x3fff2f82,
+    (q31_t)0x3f6934a8, (q31_t)0x3fff4e59, (q31_t)0x3f75c585, (q31_t)0x3fff6ab9,
+    (q31_t)0x3f825668, (q31_t)0x3fff84a1, (q31_t)0x3f8ee750, (q31_t)0x3fff9c12,
+    (q31_t)0x3f9b783c, (q31_t)0x3fffb10b, (q31_t)0x3fa8092c, (q31_t)0x3fffc38c,
+    (q31_t)0x3fb49a1f, (q31_t)0x3fffd396, (q31_t)0x3fc12b16, (q31_t)0x3fffe128,
+    (q31_t)0x3fcdbc0f, (q31_t)0x3fffec43, (q31_t)0x3fda4d09, (q31_t)0x3ffff4e6,
+    (q31_t)0x3fe6de05, (q31_t)0x3ffffb11, (q31_t)0x3ff36f02, (q31_t)0x3ffffec4,
+};
+
+
+/**
+* \par
+* Generation of realCoefBQ31 array:
+* \par
+*  n = 4096
+* 
for (i = 0; i < n; i++)
+* {
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* } 

+* \par
+* Convert to fixed point Q31 format
+*     round(pBTable[i] * pow(2, 31))
+*
+*/
+
+const q31_t realCoefBQ31[8192] = {
+    (q31_t)0x40000000, (q31_t)0x40000000, (q31_t)0x400c90fe, (q31_t)0x3ffffec4,
+    (q31_t)0x401921fb, (q31_t)0x3ffffb11, (q31_t)0x4025b2f7, (q31_t)0x3ffff4e6,
+    (q31_t)0x403243f1, (q31_t)0x3fffec43, (q31_t)0x403ed4ea, (q31_t)0x3fffe128,
+    (q31_t)0x404b65e1, (q31_t)0x3fffd396, (q31_t)0x4057f6d4, (q31_t)0x3fffc38c,
+    (q31_t)0x406487c4, (q31_t)0x3fffb10b, (q31_t)0x407118b0, (q31_t)0x3fff9c12,
+    (q31_t)0x407da998, (q31_t)0x3fff84a1, (q31_t)0x408a3a7b, (q31_t)0x3fff6ab9,
+    (q31_t)0x4096cb58, (q31_t)0x3fff4e59, (q31_t)0x40a35c30, (q31_t)0x3fff2f82,
+    (q31_t)0x40afed02, (q31_t)0x3fff0e32, (q31_t)0x40bc7dcc, (q31_t)0x3ffeea6c,
+    (q31_t)0x40c90e90, (q31_t)0x3ffec42d, (q31_t)0x40d59f4c, (q31_t)0x3ffe9b77,
+    (q31_t)0x40e22fff, (q31_t)0x3ffe704a, (q31_t)0x40eec0aa, (q31_t)0x3ffe42a4,
+    (q31_t)0x40fb514b, (q31_t)0x3ffe1288, (q31_t)0x4107e1e3, (q31_t)0x3ffddff3,
+    (q31_t)0x41147271, (q31_t)0x3ffdaae7, (q31_t)0x412102f4, (q31_t)0x3ffd7364,
+    (q31_t)0x412d936c, (q31_t)0x3ffd3969, (q31_t)0x413a23d8, (q31_t)0x3ffcfcf6,
+    (q31_t)0x4146b438, (q31_t)0x3ffcbe0c, (q31_t)0x4153448c, (q31_t)0x3ffc7caa,
+    (q31_t)0x415fd4d2, (q31_t)0x3ffc38d1, (q31_t)0x416c650b, (q31_t)0x3ffbf280,
+    (q31_t)0x4178f536, (q31_t)0x3ffba9b8, (q31_t)0x41858552, (q31_t)0x3ffb5e78,
+    (q31_t)0x4192155f, (q31_t)0x3ffb10c1, (q31_t)0x419ea55d, (q31_t)0x3ffac092,
+    (q31_t)0x41ab354b, (q31_t)0x3ffa6dec, (q31_t)0x41b7c528, (q31_t)0x3ffa18cf,
+    (q31_t)0x41c454f5, (q31_t)0x3ff9c13a, (q31_t)0x41d0e4b0, (q31_t)0x3ff9672d,
+    (q31_t)0x41dd7459, (q31_t)0x3ff90aaa, (q31_t)0x41ea03ef, (q31_t)0x3ff8abae,
+    (q31_t)0x41f69373, (q31_t)0x3ff84a3c, (q31_t)0x420322e3, (q31_t)0x3ff7e652,
+    (q31_t)0x420fb240, (q31_t)0x3ff77ff1, (q31_t)0x421c4188, (q31_t)0x3ff71718,
+    (q31_t)0x4228d0bb, (q31_t)0x3ff6abc8, (q31_t)0x42355fd9, (q31_t)0x3ff63e01,
+    (q31_t)0x4241eee2, (q31_t)0x3ff5cdc3, (q31_t)0x424e7dd4, (q31_t)0x3ff55b0d,
+    (q31_t)0x425b0caf, (q31_t)0x3ff4e5e0, (q31_t)0x42679b73, (q31_t)0x3ff46e3c,
+    (q31_t)0x42742a1f, (q31_t)0x3ff3f420, (q31_t)0x4280b8b3, (q31_t)0x3ff3778e,
+    (q31_t)0x428d472e, (q31_t)0x3ff2f884, (q31_t)0x4299d590, (q31_t)0x3ff27703,
+    (q31_t)0x42a663d8, (q31_t)0x3ff1f30b, (q31_t)0x42b2f207, (q31_t)0x3ff16c9c,
+    (q31_t)0x42bf801a, (q31_t)0x3ff0e3b6, (q31_t)0x42cc0e13, (q31_t)0x3ff05858,
+    (q31_t)0x42d89bf0, (q31_t)0x3fefca84, (q31_t)0x42e529b0, (q31_t)0x3fef3a39,
+    (q31_t)0x42f1b755, (q31_t)0x3feea776, (q31_t)0x42fe44dc, (q31_t)0x3fee123d,
+    (q31_t)0x430ad245, (q31_t)0x3fed7a8c, (q31_t)0x43175f91, (q31_t)0x3fece065,
+    (q31_t)0x4323ecbe, (q31_t)0x3fec43c7, (q31_t)0x433079cc, (q31_t)0x3feba4b2,
+    (q31_t)0x433d06bb, (q31_t)0x3feb0326, (q31_t)0x43499389, (q31_t)0x3fea5f23,
+    (q31_t)0x43562038, (q31_t)0x3fe9b8a9, (q31_t)0x4362acc5, (q31_t)0x3fe90fb9,
+    (q31_t)0x436f3931, (q31_t)0x3fe86452, (q31_t)0x437bc57b, (q31_t)0x3fe7b674,
+    (q31_t)0x438851a2, (q31_t)0x3fe7061f, (q31_t)0x4394dda7, (q31_t)0x3fe65354,
+    (q31_t)0x43a16988, (q31_t)0x3fe59e12, (q31_t)0x43adf546, (q31_t)0x3fe4e659,
+    (q31_t)0x43ba80df, (q31_t)0x3fe42c2a, (q31_t)0x43c70c54, (q31_t)0x3fe36f84,
+    (q31_t)0x43d397a3, (q31_t)0x3fe2b067, (q31_t)0x43e022cc, (q31_t)0x3fe1eed5,
+    (q31_t)0x43ecadcf, (q31_t)0x3fe12acb, (q31_t)0x43f938ac, (q31_t)0x3fe0644b,
+    (q31_t)0x4405c361, (q31_t)0x3fdf9b55, (q31_t)0x44124dee, (q31_t)0x3fdecfe8,
+    (q31_t)0x441ed854, (q31_t)0x3fde0205, (q31_t)0x442b6290, (q31_t)0x3fdd31ac,
+    (q31_t)0x4437eca4, (q31_t)0x3fdc5edc, (q31_t)0x4444768d, (q31_t)0x3fdb8996,
+    (q31_t)0x4451004d, (q31_t)0x3fdab1d9, (q31_t)0x445d89e2, (q31_t)0x3fd9d7a7,
+    (q31_t)0x446a134c, (q31_t)0x3fd8fafe, (q31_t)0x44769c8b, (q31_t)0x3fd81bdf,
+    (q31_t)0x4483259d, (q31_t)0x3fd73a4a, (q31_t)0x448fae83, (q31_t)0x3fd6563f,
+    (q31_t)0x449c373c, (q31_t)0x3fd56fbe, (q31_t)0x44a8bfc7, (q31_t)0x3fd486c7,
+    (q31_t)0x44b54825, (q31_t)0x3fd39b5a, (q31_t)0x44c1d054, (q31_t)0x3fd2ad77,
+    (q31_t)0x44ce5854, (q31_t)0x3fd1bd1e, (q31_t)0x44dae024, (q31_t)0x3fd0ca4f,
+    (q31_t)0x44e767c5, (q31_t)0x3fcfd50b, (q31_t)0x44f3ef35, (q31_t)0x3fcedd50,
+    (q31_t)0x45007674, (q31_t)0x3fcde320, (q31_t)0x450cfd82, (q31_t)0x3fcce67a,
+    (q31_t)0x4519845e, (q31_t)0x3fcbe75e, (q31_t)0x45260b08, (q31_t)0x3fcae5cd,
+    (q31_t)0x4532917f, (q31_t)0x3fc9e1c6, (q31_t)0x453f17c3, (q31_t)0x3fc8db4a,
+    (q31_t)0x454b9dd3, (q31_t)0x3fc7d258, (q31_t)0x455823ae, (q31_t)0x3fc6c6f0,
+    (q31_t)0x4564a955, (q31_t)0x3fc5b913, (q31_t)0x45712ec7, (q31_t)0x3fc4a8c1,
+    (q31_t)0x457db403, (q31_t)0x3fc395f9, (q31_t)0x458a3908, (q31_t)0x3fc280bc,
+    (q31_t)0x4596bdd7, (q31_t)0x3fc1690a, (q31_t)0x45a3426f, (q31_t)0x3fc04ee3,
+    (q31_t)0x45afc6d0, (q31_t)0x3fbf3246, (q31_t)0x45bc4af8, (q31_t)0x3fbe1334,
+    (q31_t)0x45c8cee7, (q31_t)0x3fbcf1ad, (q31_t)0x45d5529e, (q31_t)0x3fbbcdb1,
+    (q31_t)0x45e1d61b, (q31_t)0x3fbaa740, (q31_t)0x45ee595d, (q31_t)0x3fb97e5a,
+    (q31_t)0x45fadc66, (q31_t)0x3fb852ff, (q31_t)0x46075f33, (q31_t)0x3fb7252f,
+    (q31_t)0x4613e1c5, (q31_t)0x3fb5f4ea, (q31_t)0x4620641a, (q31_t)0x3fb4c231,
+    (q31_t)0x462ce634, (q31_t)0x3fb38d02, (q31_t)0x46396810, (q31_t)0x3fb2555f,
+    (q31_t)0x4645e9af, (q31_t)0x3fb11b48, (q31_t)0x46526b10, (q31_t)0x3fafdebb,
+    (q31_t)0x465eec33, (q31_t)0x3fae9fbb, (q31_t)0x466b6d16, (q31_t)0x3fad5e45,
+    (q31_t)0x4677edbb, (q31_t)0x3fac1a5b, (q31_t)0x46846e1f, (q31_t)0x3faad3fd,
+    (q31_t)0x4690ee44, (q31_t)0x3fa98b2a, (q31_t)0x469d6e27, (q31_t)0x3fa83fe3,
+    (q31_t)0x46a9edc9, (q31_t)0x3fa6f228, (q31_t)0x46b66d29, (q31_t)0x3fa5a1f9,
+    (q31_t)0x46c2ec48, (q31_t)0x3fa44f55, (q31_t)0x46cf6b23, (q31_t)0x3fa2fa3d,
+    (q31_t)0x46dbe9bb, (q31_t)0x3fa1a2b2, (q31_t)0x46e86810, (q31_t)0x3fa048b2,
+    (q31_t)0x46f4e620, (q31_t)0x3f9eec3e, (q31_t)0x470163eb, (q31_t)0x3f9d8d56,
+    (q31_t)0x470de172, (q31_t)0x3f9c2bfb, (q31_t)0x471a5eb3, (q31_t)0x3f9ac82c,
+    (q31_t)0x4726dbae, (q31_t)0x3f9961e8, (q31_t)0x47335862, (q31_t)0x3f97f932,
+    (q31_t)0x473fd4cf, (q31_t)0x3f968e07, (q31_t)0x474c50f4, (q31_t)0x3f952069,
+    (q31_t)0x4758ccd2, (q31_t)0x3f93b058, (q31_t)0x47654867, (q31_t)0x3f923dd2,
+    (q31_t)0x4771c3b3, (q31_t)0x3f90c8da, (q31_t)0x477e3eb5, (q31_t)0x3f8f516e,
+    (q31_t)0x478ab96e, (q31_t)0x3f8dd78f, (q31_t)0x479733dc, (q31_t)0x3f8c5b3d,
+    (q31_t)0x47a3adff, (q31_t)0x3f8adc77, (q31_t)0x47b027d7, (q31_t)0x3f895b3e,
+    (q31_t)0x47bca163, (q31_t)0x3f87d792, (q31_t)0x47c91aa3, (q31_t)0x3f865174,
+    (q31_t)0x47d59396, (q31_t)0x3f84c8e2, (q31_t)0x47e20c3b, (q31_t)0x3f833ddd,
+    (q31_t)0x47ee8493, (q31_t)0x3f81b065, (q31_t)0x47fafc9c, (q31_t)0x3f80207b,
+    (q31_t)0x48077457, (q31_t)0x3f7e8e1e, (q31_t)0x4813ebc2, (q31_t)0x3f7cf94e,
+    (q31_t)0x482062de, (q31_t)0x3f7b620c, (q31_t)0x482cd9a9, (q31_t)0x3f79c857,
+    (q31_t)0x48395024, (q31_t)0x3f782c30, (q31_t)0x4845c64d, (q31_t)0x3f768d96,
+    (q31_t)0x48523c25, (q31_t)0x3f74ec8a, (q31_t)0x485eb1ab, (q31_t)0x3f73490b,
+    (q31_t)0x486b26de, (q31_t)0x3f71a31b, (q31_t)0x48779bbe, (q31_t)0x3f6ffab8,
+    (q31_t)0x4884104b, (q31_t)0x3f6e4fe3, (q31_t)0x48908483, (q31_t)0x3f6ca29c,
+    (q31_t)0x489cf867, (q31_t)0x3f6af2e3, (q31_t)0x48a96bf6, (q31_t)0x3f6940b8,
+    (q31_t)0x48b5df30, (q31_t)0x3f678c1c, (q31_t)0x48c25213, (q31_t)0x3f65d50d,
+    (q31_t)0x48cec4a0, (q31_t)0x3f641b8d, (q31_t)0x48db36d6, (q31_t)0x3f625f9b,
+    (q31_t)0x48e7a8b5, (q31_t)0x3f60a138, (q31_t)0x48f41a3c, (q31_t)0x3f5ee063,
+    (q31_t)0x49008b6a, (q31_t)0x3f5d1d1d, (q31_t)0x490cfc40, (q31_t)0x3f5b5765,
+    (q31_t)0x49196cbc, (q31_t)0x3f598f3c, (q31_t)0x4925dcdf, (q31_t)0x3f57c4a2,
+    (q31_t)0x49324ca7, (q31_t)0x3f55f796, (q31_t)0x493ebc14, (q31_t)0x3f54281a,
+    (q31_t)0x494b2b27, (q31_t)0x3f52562c, (q31_t)0x495799dd, (q31_t)0x3f5081cd,
+    (q31_t)0x49640837, (q31_t)0x3f4eaafe, (q31_t)0x49707635, (q31_t)0x3f4cd1be,
+    (q31_t)0x497ce3d5, (q31_t)0x3f4af60d, (q31_t)0x49895118, (q31_t)0x3f4917eb,
+    (q31_t)0x4995bdfd, (q31_t)0x3f473759, (q31_t)0x49a22a83, (q31_t)0x3f455456,
+    (q31_t)0x49ae96aa, (q31_t)0x3f436ee3, (q31_t)0x49bb0271, (q31_t)0x3f4186ff,
+    (q31_t)0x49c76dd8, (q31_t)0x3f3f9cab, (q31_t)0x49d3d8df, (q31_t)0x3f3dafe7,
+    (q31_t)0x49e04385, (q31_t)0x3f3bc0b3, (q31_t)0x49ecadc9, (q31_t)0x3f39cf0e,
+    (q31_t)0x49f917ac, (q31_t)0x3f37dafa, (q31_t)0x4a05812c, (q31_t)0x3f35e476,
+    (q31_t)0x4a11ea49, (q31_t)0x3f33eb81, (q31_t)0x4a1e5303, (q31_t)0x3f31f01d,
+    (q31_t)0x4a2abb59, (q31_t)0x3f2ff24a, (q31_t)0x4a37234a, (q31_t)0x3f2df206,
+    (q31_t)0x4a438ad7, (q31_t)0x3f2bef53, (q31_t)0x4a4ff1fe, (q31_t)0x3f29ea31,
+    (q31_t)0x4a5c58c0, (q31_t)0x3f27e29f, (q31_t)0x4a68bf1b, (q31_t)0x3f25d89e,
+    (q31_t)0x4a752510, (q31_t)0x3f23cc2e, (q31_t)0x4a818a9d, (q31_t)0x3f21bd4e,
+    (q31_t)0x4a8defc3, (q31_t)0x3f1fabff, (q31_t)0x4a9a5480, (q31_t)0x3f1d9842,
+    (q31_t)0x4aa6b8d5, (q31_t)0x3f1b8215, (q31_t)0x4ab31cc1, (q31_t)0x3f19697a,
+    (q31_t)0x4abf8043, (q31_t)0x3f174e70, (q31_t)0x4acbe35b, (q31_t)0x3f1530f7,
+    (q31_t)0x4ad84609, (q31_t)0x3f13110f, (q31_t)0x4ae4a84b, (q31_t)0x3f10eeb9,
+    (q31_t)0x4af10a22, (q31_t)0x3f0ec9f5, (q31_t)0x4afd6b8d, (q31_t)0x3f0ca2c2,
+    (q31_t)0x4b09cc8c, (q31_t)0x3f0a7921, (q31_t)0x4b162d1d, (q31_t)0x3f084d12,
+    (q31_t)0x4b228d42, (q31_t)0x3f061e95, (q31_t)0x4b2eecf8, (q31_t)0x3f03eda9,
+    (q31_t)0x4b3b4c40, (q31_t)0x3f01ba50, (q31_t)0x4b47ab19, (q31_t)0x3eff8489,
+    (q31_t)0x4b540982, (q31_t)0x3efd4c54, (q31_t)0x4b60677c, (q31_t)0x3efb11b1,
+    (q31_t)0x4b6cc506, (q31_t)0x3ef8d4a1, (q31_t)0x4b79221f, (q31_t)0x3ef69523,
+    (q31_t)0x4b857ec7, (q31_t)0x3ef45338, (q31_t)0x4b91dafc, (q31_t)0x3ef20ee0,
+    (q31_t)0x4b9e36c0, (q31_t)0x3eefc81a, (q31_t)0x4baa9211, (q31_t)0x3eed7ee7,
+    (q31_t)0x4bb6ecef, (q31_t)0x3eeb3347, (q31_t)0x4bc34759, (q31_t)0x3ee8e53a,
+    (q31_t)0x4bcfa150, (q31_t)0x3ee694c1, (q31_t)0x4bdbfad1, (q31_t)0x3ee441da,
+    (q31_t)0x4be853de, (q31_t)0x3ee1ec87, (q31_t)0x4bf4ac75, (q31_t)0x3edf94c7,
+    (q31_t)0x4c010496, (q31_t)0x3edd3a9a, (q31_t)0x4c0d5c41, (q31_t)0x3edade01,
+    (q31_t)0x4c19b374, (q31_t)0x3ed87efc, (q31_t)0x4c260a31, (q31_t)0x3ed61d8a,
+    (q31_t)0x4c326075, (q31_t)0x3ed3b9ad, (q31_t)0x4c3eb641, (q31_t)0x3ed15363,
+    (q31_t)0x4c4b0b94, (q31_t)0x3eceeaad, (q31_t)0x4c57606e, (q31_t)0x3ecc7f8b,
+    (q31_t)0x4c63b4ce, (q31_t)0x3eca11fe, (q31_t)0x4c7008b3, (q31_t)0x3ec7a205,
+    (q31_t)0x4c7c5c1e, (q31_t)0x3ec52fa0, (q31_t)0x4c88af0e, (q31_t)0x3ec2bad0,
+    (q31_t)0x4c950182, (q31_t)0x3ec04394, (q31_t)0x4ca1537a, (q31_t)0x3ebdc9ed,
+    (q31_t)0x4cada4f5, (q31_t)0x3ebb4ddb, (q31_t)0x4cb9f5f3, (q31_t)0x3eb8cf5d,
+    (q31_t)0x4cc64673, (q31_t)0x3eb64e75, (q31_t)0x4cd29676, (q31_t)0x3eb3cb21,
+    (q31_t)0x4cdee5f9, (q31_t)0x3eb14563, (q31_t)0x4ceb34fe, (q31_t)0x3eaebd3a,
+    (q31_t)0x4cf78383, (q31_t)0x3eac32a6, (q31_t)0x4d03d189, (q31_t)0x3ea9a5a8,
+    (q31_t)0x4d101f0e, (q31_t)0x3ea7163f, (q31_t)0x4d1c6c11, (q31_t)0x3ea4846c,
+    (q31_t)0x4d28b894, (q31_t)0x3ea1f02f, (q31_t)0x4d350495, (q31_t)0x3e9f5988,
+    (q31_t)0x4d415013, (q31_t)0x3e9cc076, (q31_t)0x4d4d9b0e, (q31_t)0x3e9a24fb,
+    (q31_t)0x4d59e586, (q31_t)0x3e978715, (q31_t)0x4d662f7b, (q31_t)0x3e94e6c6,
+    (q31_t)0x4d7278eb, (q31_t)0x3e92440d, (q31_t)0x4d7ec1d6, (q31_t)0x3e8f9eeb,
+    (q31_t)0x4d8b0a3d, (q31_t)0x3e8cf75f, (q31_t)0x4d97521d, (q31_t)0x3e8a4d6a,
+    (q31_t)0x4da39978, (q31_t)0x3e87a10c, (q31_t)0x4dafe04b, (q31_t)0x3e84f245,
+    (q31_t)0x4dbc2698, (q31_t)0x3e824114, (q31_t)0x4dc86c5d, (q31_t)0x3e7f8d7b,
+    (q31_t)0x4dd4b19a, (q31_t)0x3e7cd778, (q31_t)0x4de0f64f, (q31_t)0x3e7a1f0d,
+    (q31_t)0x4ded3a7b, (q31_t)0x3e77643a, (q31_t)0x4df97e1d, (q31_t)0x3e74a6fd,
+    (q31_t)0x4e05c135, (q31_t)0x3e71e759, (q31_t)0x4e1203c3, (q31_t)0x3e6f254c,
+    (q31_t)0x4e1e45c6, (q31_t)0x3e6c60d7, (q31_t)0x4e2a873e, (q31_t)0x3e6999fa,
+    (q31_t)0x4e36c82a, (q31_t)0x3e66d0b4, (q31_t)0x4e430889, (q31_t)0x3e640507,
+    (q31_t)0x4e4f485c, (q31_t)0x3e6136f3, (q31_t)0x4e5b87a2, (q31_t)0x3e5e6676,
+    (q31_t)0x4e67c65a, (q31_t)0x3e5b9392, (q31_t)0x4e740483, (q31_t)0x3e58be47,
+    (q31_t)0x4e80421e, (q31_t)0x3e55e694, (q31_t)0x4e8c7f2a, (q31_t)0x3e530c7a,
+    (q31_t)0x4e98bba7, (q31_t)0x3e502ff9, (q31_t)0x4ea4f793, (q31_t)0x3e4d5110,
+    (q31_t)0x4eb132ef, (q31_t)0x3e4a6fc1, (q31_t)0x4ebd6db9, (q31_t)0x3e478c0b,
+    (q31_t)0x4ec9a7f3, (q31_t)0x3e44a5ef, (q31_t)0x4ed5e19a, (q31_t)0x3e41bd6c,
+    (q31_t)0x4ee21aaf, (q31_t)0x3e3ed282, (q31_t)0x4eee5331, (q31_t)0x3e3be532,
+    (q31_t)0x4efa8b20, (q31_t)0x3e38f57c, (q31_t)0x4f06c27a, (q31_t)0x3e360360,
+    (q31_t)0x4f12f941, (q31_t)0x3e330ede, (q31_t)0x4f1f2f73, (q31_t)0x3e3017f6,
+    (q31_t)0x4f2b650f, (q31_t)0x3e2d1ea8, (q31_t)0x4f379a16, (q31_t)0x3e2a22f4,
+    (q31_t)0x4f43ce86, (q31_t)0x3e2724db, (q31_t)0x4f500260, (q31_t)0x3e24245d,
+    (q31_t)0x4f5c35a3, (q31_t)0x3e212179, (q31_t)0x4f68684e, (q31_t)0x3e1e1c30,
+    (q31_t)0x4f749a61, (q31_t)0x3e1b1482, (q31_t)0x4f80cbdc, (q31_t)0x3e180a6f,
+    (q31_t)0x4f8cfcbe, (q31_t)0x3e14fdf7, (q31_t)0x4f992d06, (q31_t)0x3e11ef1b,
+    (q31_t)0x4fa55cb4, (q31_t)0x3e0eddd9, (q31_t)0x4fb18bc8, (q31_t)0x3e0bca34,
+    (q31_t)0x4fbdba40, (q31_t)0x3e08b42a, (q31_t)0x4fc9e81e, (q31_t)0x3e059bbb,
+    (q31_t)0x4fd6155f, (q31_t)0x3e0280e9, (q31_t)0x4fe24205, (q31_t)0x3dff63b2,
+    (q31_t)0x4fee6e0d, (q31_t)0x3dfc4418, (q31_t)0x4ffa9979, (q31_t)0x3df9221a,
+    (q31_t)0x5006c446, (q31_t)0x3df5fdb8, (q31_t)0x5012ee76, (q31_t)0x3df2d6f3,
+    (q31_t)0x501f1807, (q31_t)0x3defadca, (q31_t)0x502b40f8, (q31_t)0x3dec823e,
+    (q31_t)0x5037694b, (q31_t)0x3de9544f, (q31_t)0x504390fd, (q31_t)0x3de623fd,
+    (q31_t)0x504fb80e, (q31_t)0x3de2f148, (q31_t)0x505bde7f, (q31_t)0x3ddfbc30,
+    (q31_t)0x5068044e, (q31_t)0x3ddc84b5, (q31_t)0x5074297b, (q31_t)0x3dd94ad8,
+    (q31_t)0x50804e06, (q31_t)0x3dd60e99, (q31_t)0x508c71ee, (q31_t)0x3dd2cff7,
+    (q31_t)0x50989532, (q31_t)0x3dcf8ef3, (q31_t)0x50a4b7d3, (q31_t)0x3dcc4b8d,
+    (q31_t)0x50b0d9d0, (q31_t)0x3dc905c5, (q31_t)0x50bcfb28, (q31_t)0x3dc5bd9b,
+    (q31_t)0x50c91bda, (q31_t)0x3dc2730f, (q31_t)0x50d53be7, (q31_t)0x3dbf2622,
+    (q31_t)0x50e15b4e, (q31_t)0x3dbbd6d4, (q31_t)0x50ed7a0e, (q31_t)0x3db88524,
+    (q31_t)0x50f99827, (q31_t)0x3db53113, (q31_t)0x5105b599, (q31_t)0x3db1daa2,
+    (q31_t)0x5111d263, (q31_t)0x3dae81cf, (q31_t)0x511dee84, (q31_t)0x3dab269b,
+    (q31_t)0x512a09fc, (q31_t)0x3da7c907, (q31_t)0x513624cb, (q31_t)0x3da46912,
+    (q31_t)0x51423ef0, (q31_t)0x3da106bd, (q31_t)0x514e586a, (q31_t)0x3d9da208,
+    (q31_t)0x515a713a, (q31_t)0x3d9a3af2, (q31_t)0x5166895f, (q31_t)0x3d96d17d,
+    (q31_t)0x5172a0d7, (q31_t)0x3d9365a8, (q31_t)0x517eb7a4, (q31_t)0x3d8ff772,
+    (q31_t)0x518acdc4, (q31_t)0x3d8c86de, (q31_t)0x5196e337, (q31_t)0x3d8913ea,
+    (q31_t)0x51a2f7fc, (q31_t)0x3d859e96, (q31_t)0x51af0c13, (q31_t)0x3d8226e4,
+    (q31_t)0x51bb1f7c, (q31_t)0x3d7eacd2, (q31_t)0x51c73235, (q31_t)0x3d7b3061,
+    (q31_t)0x51d3443f, (q31_t)0x3d77b192, (q31_t)0x51df5599, (q31_t)0x3d743064,
+    (q31_t)0x51eb6643, (q31_t)0x3d70acd7, (q31_t)0x51f7763c, (q31_t)0x3d6d26ec,
+    (q31_t)0x52038584, (q31_t)0x3d699ea3, (q31_t)0x520f941a, (q31_t)0x3d6613fb,
+    (q31_t)0x521ba1fd, (q31_t)0x3d6286f6, (q31_t)0x5227af2e, (q31_t)0x3d5ef793,
+    (q31_t)0x5233bbac, (q31_t)0x3d5b65d2, (q31_t)0x523fc776, (q31_t)0x3d57d1b3,
+    (q31_t)0x524bd28c, (q31_t)0x3d543b37, (q31_t)0x5257dced, (q31_t)0x3d50a25e,
+    (q31_t)0x5263e699, (q31_t)0x3d4d0728, (q31_t)0x526fef90, (q31_t)0x3d496994,
+    (q31_t)0x527bf7d1, (q31_t)0x3d45c9a4, (q31_t)0x5287ff5b, (q31_t)0x3d422757,
+    (q31_t)0x5294062f, (q31_t)0x3d3e82ae, (q31_t)0x52a00c4b, (q31_t)0x3d3adba7,
+    (q31_t)0x52ac11af, (q31_t)0x3d373245, (q31_t)0x52b8165b, (q31_t)0x3d338687,
+    (q31_t)0x52c41a4f, (q31_t)0x3d2fd86c, (q31_t)0x52d01d89, (q31_t)0x3d2c27f6,
+    (q31_t)0x52dc2009, (q31_t)0x3d287523, (q31_t)0x52e821cf, (q31_t)0x3d24bff6,
+    (q31_t)0x52f422db, (q31_t)0x3d21086c, (q31_t)0x5300232c, (q31_t)0x3d1d4e88,
+    (q31_t)0x530c22c1, (q31_t)0x3d199248, (q31_t)0x5318219a, (q31_t)0x3d15d3ad,
+    (q31_t)0x53241fb6, (q31_t)0x3d1212b7, (q31_t)0x53301d16, (q31_t)0x3d0e4f67,
+    (q31_t)0x533c19b8, (q31_t)0x3d0a89bc, (q31_t)0x5348159d, (q31_t)0x3d06c1b6,
+    (q31_t)0x535410c3, (q31_t)0x3d02f757, (q31_t)0x53600b2a, (q31_t)0x3cff2a9d,
+    (q31_t)0x536c04d2, (q31_t)0x3cfb5b89, (q31_t)0x5377fdbb, (q31_t)0x3cf78a1b,
+    (q31_t)0x5383f5e3, (q31_t)0x3cf3b653, (q31_t)0x538fed4b, (q31_t)0x3cefe032,
+    (q31_t)0x539be3f2, (q31_t)0x3cec07b8, (q31_t)0x53a7d9d7, (q31_t)0x3ce82ce4,
+    (q31_t)0x53b3cefa, (q31_t)0x3ce44fb7, (q31_t)0x53bfc35b, (q31_t)0x3ce07031,
+    (q31_t)0x53cbb6f8, (q31_t)0x3cdc8e52, (q31_t)0x53d7a9d3, (q31_t)0x3cd8aa1b,
+    (q31_t)0x53e39be9, (q31_t)0x3cd4c38b, (q31_t)0x53ef8d3c, (q31_t)0x3cd0daa2,
+    (q31_t)0x53fb7dc9, (q31_t)0x3cccef62, (q31_t)0x54076d91, (q31_t)0x3cc901c9,
+    (q31_t)0x54135c94, (q31_t)0x3cc511d9, (q31_t)0x541f4ad1, (q31_t)0x3cc11f90,
+    (q31_t)0x542b3846, (q31_t)0x3cbd2af0, (q31_t)0x543724f5, (q31_t)0x3cb933f9,
+    (q31_t)0x544310dd, (q31_t)0x3cb53aaa, (q31_t)0x544efbfc, (q31_t)0x3cb13f04,
+    (q31_t)0x545ae653, (q31_t)0x3cad4107, (q31_t)0x5466cfe1, (q31_t)0x3ca940b3,
+    (q31_t)0x5472b8a5, (q31_t)0x3ca53e09, (q31_t)0x547ea0a0, (q31_t)0x3ca13908,
+    (q31_t)0x548a87d1, (q31_t)0x3c9d31b0, (q31_t)0x54966e36, (q31_t)0x3c992803,
+    (q31_t)0x54a253d1, (q31_t)0x3c951bff, (q31_t)0x54ae38a0, (q31_t)0x3c910da5,
+    (q31_t)0x54ba1ca3, (q31_t)0x3c8cfcf6, (q31_t)0x54c5ffd9, (q31_t)0x3c88e9f1,
+    (q31_t)0x54d1e242, (q31_t)0x3c84d496, (q31_t)0x54ddc3de, (q31_t)0x3c80bce7,
+    (q31_t)0x54e9a4ac, (q31_t)0x3c7ca2e2, (q31_t)0x54f584ac, (q31_t)0x3c788688,
+    (q31_t)0x550163dc, (q31_t)0x3c7467d9, (q31_t)0x550d423d, (q31_t)0x3c7046d6,
+    (q31_t)0x55191fcf, (q31_t)0x3c6c237e, (q31_t)0x5524fc90, (q31_t)0x3c67fdd1,
+    (q31_t)0x5530d881, (q31_t)0x3c63d5d1, (q31_t)0x553cb3a0, (q31_t)0x3c5fab7c,
+    (q31_t)0x55488dee, (q31_t)0x3c5b7ed4, (q31_t)0x5554676a, (q31_t)0x3c574fd8,
+    (q31_t)0x55604013, (q31_t)0x3c531e88, (q31_t)0x556c17e9, (q31_t)0x3c4eeae5,
+    (q31_t)0x5577eeec, (q31_t)0x3c4ab4ef, (q31_t)0x5583c51b, (q31_t)0x3c467ca6,
+    (q31_t)0x558f9a76, (q31_t)0x3c42420a, (q31_t)0x559b6efb, (q31_t)0x3c3e051b,
+    (q31_t)0x55a742ac, (q31_t)0x3c39c5da, (q31_t)0x55b31587, (q31_t)0x3c358446,
+    (q31_t)0x55bee78c, (q31_t)0x3c314060, (q31_t)0x55cab8ba, (q31_t)0x3c2cfa28,
+    (q31_t)0x55d68911, (q31_t)0x3c28b19e, (q31_t)0x55e25890, (q31_t)0x3c2466c2,
+    (q31_t)0x55ee2738, (q31_t)0x3c201994, (q31_t)0x55f9f507, (q31_t)0x3c1bca16,
+    (q31_t)0x5605c1fd, (q31_t)0x3c177845, (q31_t)0x56118e1a, (q31_t)0x3c132424,
+    (q31_t)0x561d595d, (q31_t)0x3c0ecdb2, (q31_t)0x562923c5, (q31_t)0x3c0a74f0,
+    (q31_t)0x5634ed53, (q31_t)0x3c0619dc, (q31_t)0x5640b606, (q31_t)0x3c01bc78,
+    (q31_t)0x564c7ddd, (q31_t)0x3bfd5cc4, (q31_t)0x565844d8, (q31_t)0x3bf8fac0,
+    (q31_t)0x56640af7, (q31_t)0x3bf4966c, (q31_t)0x566fd039, (q31_t)0x3bf02fc9,
+    (q31_t)0x567b949d, (q31_t)0x3bebc6d5, (q31_t)0x56875823, (q31_t)0x3be75b93,
+    (q31_t)0x56931acb, (q31_t)0x3be2ee01, (q31_t)0x569edc94, (q31_t)0x3bde7e20,
+    (q31_t)0x56aa9d7e, (q31_t)0x3bda0bf0, (q31_t)0x56b65d88, (q31_t)0x3bd59771,
+    (q31_t)0x56c21cb2, (q31_t)0x3bd120a4, (q31_t)0x56cddafb, (q31_t)0x3bcca789,
+    (q31_t)0x56d99864, (q31_t)0x3bc82c1f, (q31_t)0x56e554ea, (q31_t)0x3bc3ae67,
+    (q31_t)0x56f1108f, (q31_t)0x3bbf2e62, (q31_t)0x56fccb51, (q31_t)0x3bbaac0e,
+    (q31_t)0x57088531, (q31_t)0x3bb6276e, (q31_t)0x57143e2d, (q31_t)0x3bb1a080,
+    (q31_t)0x571ff646, (q31_t)0x3bad1744, (q31_t)0x572bad7a, (q31_t)0x3ba88bbc,
+    (q31_t)0x573763c9, (q31_t)0x3ba3fde7, (q31_t)0x57431933, (q31_t)0x3b9f6dc5,
+    (q31_t)0x574ecdb8, (q31_t)0x3b9adb57, (q31_t)0x575a8157, (q31_t)0x3b96469d,
+    (q31_t)0x5766340f, (q31_t)0x3b91af97, (q31_t)0x5771e5e0, (q31_t)0x3b8d1644,
+    (q31_t)0x577d96ca, (q31_t)0x3b887aa6, (q31_t)0x578946cc, (q31_t)0x3b83dcbc,
+    (q31_t)0x5794f5e6, (q31_t)0x3b7f3c87, (q31_t)0x57a0a417, (q31_t)0x3b7a9a07,
+    (q31_t)0x57ac515f, (q31_t)0x3b75f53c, (q31_t)0x57b7fdbd, (q31_t)0x3b714e25,
+    (q31_t)0x57c3a931, (q31_t)0x3b6ca4c4, (q31_t)0x57cf53bb, (q31_t)0x3b67f919,
+    (q31_t)0x57dafd59, (q31_t)0x3b634b23, (q31_t)0x57e6a60c, (q31_t)0x3b5e9ae4,
+    (q31_t)0x57f24dd3, (q31_t)0x3b59e85a, (q31_t)0x57fdf4ae, (q31_t)0x3b553386,
+    (q31_t)0x58099a9c, (q31_t)0x3b507c69, (q31_t)0x58153f9d, (q31_t)0x3b4bc303,
+    (q31_t)0x5820e3b0, (q31_t)0x3b470753, (q31_t)0x582c86d5, (q31_t)0x3b42495a,
+    (q31_t)0x5838290c, (q31_t)0x3b3d8918, (q31_t)0x5843ca53, (q31_t)0x3b38c68e,
+    (q31_t)0x584f6aab, (q31_t)0x3b3401bb, (q31_t)0x585b0a13, (q31_t)0x3b2f3aa0,
+    (q31_t)0x5866a88a, (q31_t)0x3b2a713d, (q31_t)0x58724611, (q31_t)0x3b25a591,
+    (q31_t)0x587de2a7, (q31_t)0x3b20d79e, (q31_t)0x58897e4a, (q31_t)0x3b1c0764,
+    (q31_t)0x589518fc, (q31_t)0x3b1734e2, (q31_t)0x58a0b2bb, (q31_t)0x3b126019,
+    (q31_t)0x58ac4b87, (q31_t)0x3b0d8909, (q31_t)0x58b7e35f, (q31_t)0x3b08afb2,
+    (q31_t)0x58c37a44, (q31_t)0x3b03d414, (q31_t)0x58cf1034, (q31_t)0x3afef630,
+    (q31_t)0x58daa52f, (q31_t)0x3afa1605, (q31_t)0x58e63935, (q31_t)0x3af53395,
+    (q31_t)0x58f1cc45, (q31_t)0x3af04edf, (q31_t)0x58fd5e5f, (q31_t)0x3aeb67e3,
+    (q31_t)0x5908ef82, (q31_t)0x3ae67ea1, (q31_t)0x59147fae, (q31_t)0x3ae1931a,
+    (q31_t)0x59200ee3, (q31_t)0x3adca54e, (q31_t)0x592b9d1f, (q31_t)0x3ad7b53d,
+    (q31_t)0x59372a64, (q31_t)0x3ad2c2e8, (q31_t)0x5942b6af, (q31_t)0x3acdce4d,
+    (q31_t)0x594e4201, (q31_t)0x3ac8d76f, (q31_t)0x5959cc5a, (q31_t)0x3ac3de4c,
+    (q31_t)0x596555b8, (q31_t)0x3abee2e5, (q31_t)0x5970de1b, (q31_t)0x3ab9e53a,
+    (q31_t)0x597c6584, (q31_t)0x3ab4e54c, (q31_t)0x5987ebf0, (q31_t)0x3aafe31b,
+    (q31_t)0x59937161, (q31_t)0x3aaadea6, (q31_t)0x599ef5d6, (q31_t)0x3aa5d7ee,
+    (q31_t)0x59aa794d, (q31_t)0x3aa0cef3, (q31_t)0x59b5fbc8, (q31_t)0x3a9bc3b6,
+    (q31_t)0x59c17d44, (q31_t)0x3a96b636, (q31_t)0x59ccfdc2, (q31_t)0x3a91a674,
+    (q31_t)0x59d87d42, (q31_t)0x3a8c9470, (q31_t)0x59e3fbc3, (q31_t)0x3a87802a,
+    (q31_t)0x59ef7944, (q31_t)0x3a8269a3, (q31_t)0x59faf5c5, (q31_t)0x3a7d50da,
+    (q31_t)0x5a067145, (q31_t)0x3a7835cf, (q31_t)0x5a11ebc5, (q31_t)0x3a731884,
+    (q31_t)0x5a1d6544, (q31_t)0x3a6df8f8, (q31_t)0x5a28ddc0, (q31_t)0x3a68d72b,
+    (q31_t)0x5a34553b, (q31_t)0x3a63b31d, (q31_t)0x5a3fcbb3, (q31_t)0x3a5e8cd0,
+    (q31_t)0x5a4b4128, (q31_t)0x3a596442, (q31_t)0x5a56b599, (q31_t)0x3a543974,
+    (q31_t)0x5a622907, (q31_t)0x3a4f0c67, (q31_t)0x5a6d9b70, (q31_t)0x3a49dd1a,
+    (q31_t)0x5a790cd4, (q31_t)0x3a44ab8e, (q31_t)0x5a847d33, (q31_t)0x3a3f77c3,
+    (q31_t)0x5a8fec8c, (q31_t)0x3a3a41b9, (q31_t)0x5a9b5adf, (q31_t)0x3a350970,
+    (q31_t)0x5aa6c82b, (q31_t)0x3a2fcee8, (q31_t)0x5ab23471, (q31_t)0x3a2a9223,
+    (q31_t)0x5abd9faf, (q31_t)0x3a25531f, (q31_t)0x5ac909e5, (q31_t)0x3a2011de,
+    (q31_t)0x5ad47312, (q31_t)0x3a1ace5f, (q31_t)0x5adfdb37, (q31_t)0x3a1588a2,
+    (q31_t)0x5aeb4253, (q31_t)0x3a1040a8, (q31_t)0x5af6a865, (q31_t)0x3a0af671,
+    (q31_t)0x5b020d6c, (q31_t)0x3a05a9fd, (q31_t)0x5b0d716a, (q31_t)0x3a005b4d,
+    (q31_t)0x5b18d45c, (q31_t)0x39fb0a60, (q31_t)0x5b243643, (q31_t)0x39f5b737,
+    (q31_t)0x5b2f971e, (q31_t)0x39f061d2, (q31_t)0x5b3af6ec, (q31_t)0x39eb0a31,
+    (q31_t)0x5b4655ae, (q31_t)0x39e5b054, (q31_t)0x5b51b363, (q31_t)0x39e0543c,
+    (q31_t)0x5b5d100a, (q31_t)0x39daf5e8, (q31_t)0x5b686ba3, (q31_t)0x39d5955a,
+    (q31_t)0x5b73c62d, (q31_t)0x39d03291, (q31_t)0x5b7f1fa9, (q31_t)0x39cacd8d,
+    (q31_t)0x5b8a7815, (q31_t)0x39c5664f, (q31_t)0x5b95cf71, (q31_t)0x39bffcd7,
+    (q31_t)0x5ba125bd, (q31_t)0x39ba9125, (q31_t)0x5bac7af9, (q31_t)0x39b52339,
+    (q31_t)0x5bb7cf23, (q31_t)0x39afb313, (q31_t)0x5bc3223c, (q31_t)0x39aa40b4,
+    (q31_t)0x5bce7442, (q31_t)0x39a4cc1c, (q31_t)0x5bd9c537, (q31_t)0x399f554b,
+    (q31_t)0x5be51518, (q31_t)0x3999dc42, (q31_t)0x5bf063e6, (q31_t)0x399460ff,
+    (q31_t)0x5bfbb1a0, (q31_t)0x398ee385, (q31_t)0x5c06fe46, (q31_t)0x398963d2,
+    (q31_t)0x5c1249d8, (q31_t)0x3983e1e8, (q31_t)0x5c1d9454, (q31_t)0x397e5dc6,
+    (q31_t)0x5c28ddbb, (q31_t)0x3978d76c, (q31_t)0x5c34260c, (q31_t)0x39734edc,
+    (q31_t)0x5c3f6d47, (q31_t)0x396dc414, (q31_t)0x5c4ab36b, (q31_t)0x39683715,
+    (q31_t)0x5c55f878, (q31_t)0x3962a7e0, (q31_t)0x5c613c6d, (q31_t)0x395d1675,
+    (q31_t)0x5c6c7f4a, (q31_t)0x395782d3, (q31_t)0x5c77c10e, (q31_t)0x3951ecfc,
+    (q31_t)0x5c8301b9, (q31_t)0x394c54ee, (q31_t)0x5c8e414b, (q31_t)0x3946baac,
+    (q31_t)0x5c997fc4, (q31_t)0x39411e33, (q31_t)0x5ca4bd21, (q31_t)0x393b7f86,
+    (q31_t)0x5caff965, (q31_t)0x3935dea4, (q31_t)0x5cbb348d, (q31_t)0x39303b8e,
+    (q31_t)0x5cc66e99, (q31_t)0x392a9642, (q31_t)0x5cd1a78a, (q31_t)0x3924eec3,
+    (q31_t)0x5cdcdf5e, (q31_t)0x391f4510, (q31_t)0x5ce81615, (q31_t)0x39199929,
+    (q31_t)0x5cf34baf, (q31_t)0x3913eb0e, (q31_t)0x5cfe802b, (q31_t)0x390e3ac0,
+    (q31_t)0x5d09b389, (q31_t)0x3908883f, (q31_t)0x5d14e5c9, (q31_t)0x3902d38b,
+    (q31_t)0x5d2016e9, (q31_t)0x38fd1ca4, (q31_t)0x5d2b46ea, (q31_t)0x38f7638b,
+    (q31_t)0x5d3675cb, (q31_t)0x38f1a840, (q31_t)0x5d41a38c, (q31_t)0x38ebeac2,
+    (q31_t)0x5d4cd02c, (q31_t)0x38e62b13, (q31_t)0x5d57fbaa, (q31_t)0x38e06932,
+    (q31_t)0x5d632608, (q31_t)0x38daa520, (q31_t)0x5d6e4f43, (q31_t)0x38d4dedd,
+    (q31_t)0x5d79775c, (q31_t)0x38cf1669, (q31_t)0x5d849e51, (q31_t)0x38c94bc4,
+    (q31_t)0x5d8fc424, (q31_t)0x38c37eef, (q31_t)0x5d9ae8d2, (q31_t)0x38bdafea,
+    (q31_t)0x5da60c5d, (q31_t)0x38b7deb4, (q31_t)0x5db12ec3, (q31_t)0x38b20b4f,
+    (q31_t)0x5dbc5004, (q31_t)0x38ac35ba, (q31_t)0x5dc7701f, (q31_t)0x38a65df6,
+    (q31_t)0x5dd28f15, (q31_t)0x38a08402, (q31_t)0x5dddace4, (q31_t)0x389aa7e0,
+    (q31_t)0x5de8c98c, (q31_t)0x3894c98f, (q31_t)0x5df3e50d, (q31_t)0x388ee910,
+    (q31_t)0x5dfeff67, (q31_t)0x38890663, (q31_t)0x5e0a1898, (q31_t)0x38832187,
+    (q31_t)0x5e1530a1, (q31_t)0x387d3a7e, (q31_t)0x5e204781, (q31_t)0x38775147,
+    (q31_t)0x5e2b5d38, (q31_t)0x387165e3, (q31_t)0x5e3671c5, (q31_t)0x386b7852,
+    (q31_t)0x5e418528, (q31_t)0x38658894, (q31_t)0x5e4c9760, (q31_t)0x385f96a9,
+    (q31_t)0x5e57a86d, (q31_t)0x3859a292, (q31_t)0x5e62b84f, (q31_t)0x3853ac4f,
+    (q31_t)0x5e6dc705, (q31_t)0x384db3e0, (q31_t)0x5e78d48e, (q31_t)0x3847b946,
+    (q31_t)0x5e83e0eb, (q31_t)0x3841bc7f, (q31_t)0x5e8eec1b, (q31_t)0x383bbd8e,
+    (q31_t)0x5e99f61d, (q31_t)0x3835bc71, (q31_t)0x5ea4fef0, (q31_t)0x382fb92a,
+    (q31_t)0x5eb00696, (q31_t)0x3829b3b9, (q31_t)0x5ebb0d0d, (q31_t)0x3823ac1d,
+    (q31_t)0x5ec61254, (q31_t)0x381da256, (q31_t)0x5ed1166b, (q31_t)0x38179666,
+    (q31_t)0x5edc1953, (q31_t)0x3811884d, (q31_t)0x5ee71b0a, (q31_t)0x380b780a,
+    (q31_t)0x5ef21b90, (q31_t)0x3805659e, (q31_t)0x5efd1ae4, (q31_t)0x37ff5109,
+    (q31_t)0x5f081907, (q31_t)0x37f93a4b, (q31_t)0x5f1315f7, (q31_t)0x37f32165,
+    (q31_t)0x5f1e11b5, (q31_t)0x37ed0657, (q31_t)0x5f290c3f, (q31_t)0x37e6e921,
+    (q31_t)0x5f340596, (q31_t)0x37e0c9c3, (q31_t)0x5f3efdb9, (q31_t)0x37daa83d,
+    (q31_t)0x5f49f4a8, (q31_t)0x37d48490, (q31_t)0x5f54ea62, (q31_t)0x37ce5ebd,
+    (q31_t)0x5f5fdee6, (q31_t)0x37c836c2, (q31_t)0x5f6ad235, (q31_t)0x37c20ca1,
+    (q31_t)0x5f75c44e, (q31_t)0x37bbe05a, (q31_t)0x5f80b531, (q31_t)0x37b5b1ec,
+    (q31_t)0x5f8ba4dc, (q31_t)0x37af8159, (q31_t)0x5f969350, (q31_t)0x37a94ea0,
+    (q31_t)0x5fa1808c, (q31_t)0x37a319c2, (q31_t)0x5fac6c91, (q31_t)0x379ce2be,
+    (q31_t)0x5fb7575c, (q31_t)0x3796a996, (q31_t)0x5fc240ef, (q31_t)0x37906e49,
+    (q31_t)0x5fcd2948, (q31_t)0x378a30d8, (q31_t)0x5fd81067, (q31_t)0x3783f143,
+    (q31_t)0x5fe2f64c, (q31_t)0x377daf89, (q31_t)0x5feddaf6, (q31_t)0x37776bac,
+    (q31_t)0x5ff8be65, (q31_t)0x377125ac, (q31_t)0x6003a099, (q31_t)0x376add88,
+    (q31_t)0x600e8190, (q31_t)0x37649341, (q31_t)0x6019614c, (q31_t)0x375e46d8,
+    (q31_t)0x60243fca, (q31_t)0x3757f84c, (q31_t)0x602f1d0b, (q31_t)0x3751a79e,
+    (q31_t)0x6039f90f, (q31_t)0x374b54ce, (q31_t)0x6044d3d4, (q31_t)0x3744ffdd,
+    (q31_t)0x604fad5b, (q31_t)0x373ea8ca, (q31_t)0x605a85a3, (q31_t)0x37384f95,
+    (q31_t)0x60655cac, (q31_t)0x3731f440, (q31_t)0x60703275, (q31_t)0x372b96ca,
+    (q31_t)0x607b06fe, (q31_t)0x37253733, (q31_t)0x6085da46, (q31_t)0x371ed57c,
+    (q31_t)0x6090ac4d, (q31_t)0x371871a5, (q31_t)0x609b7d13, (q31_t)0x37120bae,
+    (q31_t)0x60a64c97, (q31_t)0x370ba398, (q31_t)0x60b11ad9, (q31_t)0x37053962,
+    (q31_t)0x60bbe7d8, (q31_t)0x36fecd0e, (q31_t)0x60c6b395, (q31_t)0x36f85e9a,
+    (q31_t)0x60d17e0d, (q31_t)0x36f1ee09, (q31_t)0x60dc4742, (q31_t)0x36eb7b58,
+    (q31_t)0x60e70f32, (q31_t)0x36e5068a, (q31_t)0x60f1d5de, (q31_t)0x36de8f9e,
+    (q31_t)0x60fc9b44, (q31_t)0x36d81695, (q31_t)0x61075f65, (q31_t)0x36d19b6e,
+    (q31_t)0x61122240, (q31_t)0x36cb1e2a, (q31_t)0x611ce3d5, (q31_t)0x36c49ec9,
+    (q31_t)0x6127a423, (q31_t)0x36be1d4c, (q31_t)0x61326329, (q31_t)0x36b799b3,
+    (q31_t)0x613d20e8, (q31_t)0x36b113fd, (q31_t)0x6147dd5f, (q31_t)0x36aa8c2c,
+    (q31_t)0x6152988d, (q31_t)0x36a4023f, (q31_t)0x615d5273, (q31_t)0x369d7637,
+    (q31_t)0x61680b0f, (q31_t)0x3696e814, (q31_t)0x6172c262, (q31_t)0x369057d6,
+    (q31_t)0x617d786a, (q31_t)0x3689c57d, (q31_t)0x61882d28, (q31_t)0x3683310b,
+    (q31_t)0x6192e09b, (q31_t)0x367c9a7e, (q31_t)0x619d92c2, (q31_t)0x367601d7,
+    (q31_t)0x61a8439e, (q31_t)0x366f6717, (q31_t)0x61b2f32e, (q31_t)0x3668ca3e,
+    (q31_t)0x61bda171, (q31_t)0x36622b4c, (q31_t)0x61c84e67, (q31_t)0x365b8a41,
+    (q31_t)0x61d2fa0f, (q31_t)0x3654e71d, (q31_t)0x61dda46a, (q31_t)0x364e41e2,
+    (q31_t)0x61e84d76, (q31_t)0x36479a8e, (q31_t)0x61f2f534, (q31_t)0x3640f123,
+    (q31_t)0x61fd9ba3, (q31_t)0x363a45a0, (q31_t)0x620840c2, (q31_t)0x36339806,
+    (q31_t)0x6212e492, (q31_t)0x362ce855, (q31_t)0x621d8711, (q31_t)0x3626368d,
+    (q31_t)0x6228283f, (q31_t)0x361f82af, (q31_t)0x6232c81c, (q31_t)0x3618ccba,
+    (q31_t)0x623d66a8, (q31_t)0x361214b0, (q31_t)0x624803e2, (q31_t)0x360b5a90,
+    (q31_t)0x62529fca, (q31_t)0x36049e5b, (q31_t)0x625d3a5e, (q31_t)0x35fde011,
+    (q31_t)0x6267d3a0, (q31_t)0x35f71fb1, (q31_t)0x62726b8e, (q31_t)0x35f05d3d,
+    (q31_t)0x627d0228, (q31_t)0x35e998b5, (q31_t)0x6287976e, (q31_t)0x35e2d219,
+    (q31_t)0x62922b5e, (q31_t)0x35dc0968, (q31_t)0x629cbdfa, (q31_t)0x35d53ea5,
+    (q31_t)0x62a74f40, (q31_t)0x35ce71ce, (q31_t)0x62b1df30, (q31_t)0x35c7a2e3,
+    (q31_t)0x62bc6dca, (q31_t)0x35c0d1e7, (q31_t)0x62c6fb0c, (q31_t)0x35b9fed7,
+    (q31_t)0x62d186f8, (q31_t)0x35b329b5, (q31_t)0x62dc118c, (q31_t)0x35ac5282,
+    (q31_t)0x62e69ac8, (q31_t)0x35a5793c, (q31_t)0x62f122ab, (q31_t)0x359e9de5,
+    (q31_t)0x62fba936, (q31_t)0x3597c07d, (q31_t)0x63062e67, (q31_t)0x3590e104,
+    (q31_t)0x6310b23e, (q31_t)0x3589ff7a, (q31_t)0x631b34bc, (q31_t)0x35831be0,
+    (q31_t)0x6325b5df, (q31_t)0x357c3636, (q31_t)0x633035a7, (q31_t)0x35754e7c,
+    (q31_t)0x633ab414, (q31_t)0x356e64b2, (q31_t)0x63453125, (q31_t)0x356778d9,
+    (q31_t)0x634facda, (q31_t)0x35608af1, (q31_t)0x635a2733, (q31_t)0x35599afa,
+    (q31_t)0x6364a02e, (q31_t)0x3552a8f4, (q31_t)0x636f17cc, (q31_t)0x354bb4e1,
+    (q31_t)0x63798e0d, (q31_t)0x3544bebf, (q31_t)0x638402ef, (q31_t)0x353dc68f,
+    (q31_t)0x638e7673, (q31_t)0x3536cc52, (q31_t)0x6398e898, (q31_t)0x352fd008,
+    (q31_t)0x63a3595e, (q31_t)0x3528d1b1, (q31_t)0x63adc8c4, (q31_t)0x3521d14d,
+    (q31_t)0x63b836ca, (q31_t)0x351acedd, (q31_t)0x63c2a36f, (q31_t)0x3513ca60,
+    (q31_t)0x63cd0eb3, (q31_t)0x350cc3d8, (q31_t)0x63d77896, (q31_t)0x3505bb44,
+    (q31_t)0x63e1e117, (q31_t)0x34feb0a5, (q31_t)0x63ec4837, (q31_t)0x34f7a3fb,
+    (q31_t)0x63f6adf3, (q31_t)0x34f09546, (q31_t)0x6401124d, (q31_t)0x34e98487,
+    (q31_t)0x640b7543, (q31_t)0x34e271bd, (q31_t)0x6415d6d5, (q31_t)0x34db5cea,
+    (q31_t)0x64203704, (q31_t)0x34d4460c, (q31_t)0x642a95ce, (q31_t)0x34cd2d26,
+    (q31_t)0x6434f332, (q31_t)0x34c61236, (q31_t)0x643f4f32, (q31_t)0x34bef53d,
+    (q31_t)0x6449a9cc, (q31_t)0x34b7d63c, (q31_t)0x645402ff, (q31_t)0x34b0b533,
+    (q31_t)0x645e5acc, (q31_t)0x34a99221, (q31_t)0x6468b132, (q31_t)0x34a26d08,
+    (q31_t)0x64730631, (q31_t)0x349b45e7, (q31_t)0x647d59c8, (q31_t)0x34941cbf,
+    (q31_t)0x6487abf7, (q31_t)0x348cf190, (q31_t)0x6491fcbe, (q31_t)0x3485c45b,
+    (q31_t)0x649c4c1b, (q31_t)0x347e951f, (q31_t)0x64a69a0f, (q31_t)0x347763dd,
+    (q31_t)0x64b0e699, (q31_t)0x34703095, (q31_t)0x64bb31ba, (q31_t)0x3468fb47,
+    (q31_t)0x64c57b6f, (q31_t)0x3461c3f5, (q31_t)0x64cfc3ba, (q31_t)0x345a8a9d,
+    (q31_t)0x64da0a9a, (q31_t)0x34534f41, (q31_t)0x64e4500e, (q31_t)0x344c11e0,
+    (q31_t)0x64ee9415, (q31_t)0x3444d27b, (q31_t)0x64f8d6b0, (q31_t)0x343d9112,
+    (q31_t)0x650317df, (q31_t)0x34364da6, (q31_t)0x650d57a0, (q31_t)0x342f0836,
+    (q31_t)0x651795f3, (q31_t)0x3427c0c3, (q31_t)0x6521d2d8, (q31_t)0x3420774d,
+    (q31_t)0x652c0e4f, (q31_t)0x34192bd5, (q31_t)0x65364857, (q31_t)0x3411de5b,
+    (q31_t)0x654080ef, (q31_t)0x340a8edf, (q31_t)0x654ab818, (q31_t)0x34033d61,
+    (q31_t)0x6554edd1, (q31_t)0x33fbe9e2, (q31_t)0x655f2219, (q31_t)0x33f49462,
+    (q31_t)0x656954f1, (q31_t)0x33ed3ce1, (q31_t)0x65738657, (q31_t)0x33e5e360,
+    (q31_t)0x657db64c, (q31_t)0x33de87de, (q31_t)0x6587e4cf, (q31_t)0x33d72a5d,
+    (q31_t)0x659211df, (q31_t)0x33cfcadc, (q31_t)0x659c3d7c, (q31_t)0x33c8695b,
+    (q31_t)0x65a667a7, (q31_t)0x33c105db, (q31_t)0x65b0905d, (q31_t)0x33b9a05d,
+    (q31_t)0x65bab7a0, (q31_t)0x33b238e0, (q31_t)0x65c4dd6e, (q31_t)0x33aacf65,
+    (q31_t)0x65cf01c8, (q31_t)0x33a363ec, (q31_t)0x65d924ac, (q31_t)0x339bf675,
+    (q31_t)0x65e3461b, (q31_t)0x33948701, (q31_t)0x65ed6614, (q31_t)0x338d1590,
+    (q31_t)0x65f78497, (q31_t)0x3385a222, (q31_t)0x6601a1a2, (q31_t)0x337e2cb7,
+    (q31_t)0x660bbd37, (q31_t)0x3376b551, (q31_t)0x6615d754, (q31_t)0x336f3bee,
+    (q31_t)0x661feffa, (q31_t)0x3367c090, (q31_t)0x662a0727, (q31_t)0x33604336,
+    (q31_t)0x66341cdb, (q31_t)0x3358c3e2, (q31_t)0x663e3117, (q31_t)0x33514292,
+    (q31_t)0x664843d9, (q31_t)0x3349bf48, (q31_t)0x66525521, (q31_t)0x33423a04,
+    (q31_t)0x665c64ef, (q31_t)0x333ab2c6, (q31_t)0x66667342, (q31_t)0x3333298f,
+    (q31_t)0x6670801a, (q31_t)0x332b9e5e, (q31_t)0x667a8b77, (q31_t)0x33241134,
+    (q31_t)0x66849558, (q31_t)0x331c8211, (q31_t)0x668e9dbd, (q31_t)0x3314f0f6,
+    (q31_t)0x6698a4a6, (q31_t)0x330d5de3, (q31_t)0x66a2aa11, (q31_t)0x3305c8d7,
+    (q31_t)0x66acadff, (q31_t)0x32fe31d5, (q31_t)0x66b6b070, (q31_t)0x32f698db,
+    (q31_t)0x66c0b162, (q31_t)0x32eefdea, (q31_t)0x66cab0d6, (q31_t)0x32e76102,
+    (q31_t)0x66d4aecb, (q31_t)0x32dfc224, (q31_t)0x66deab41, (q31_t)0x32d82150,
+    (q31_t)0x66e8a637, (q31_t)0x32d07e85, (q31_t)0x66f29fad, (q31_t)0x32c8d9c6,
+    (q31_t)0x66fc97a3, (q31_t)0x32c13311, (q31_t)0x67068e18, (q31_t)0x32b98a67,
+    (q31_t)0x6710830c, (q31_t)0x32b1dfc9, (q31_t)0x671a767e, (q31_t)0x32aa3336,
+    (q31_t)0x6724686e, (q31_t)0x32a284b0, (q31_t)0x672e58dc, (q31_t)0x329ad435,
+    (q31_t)0x673847c8, (q31_t)0x329321c7, (q31_t)0x67423530, (q31_t)0x328b6d66,
+    (q31_t)0x674c2115, (q31_t)0x3283b712, (q31_t)0x67560b76, (q31_t)0x327bfecc,
+    (q31_t)0x675ff452, (q31_t)0x32744493, (q31_t)0x6769dbaa, (q31_t)0x326c8868,
+    (q31_t)0x6773c17d, (q31_t)0x3264ca4c, (q31_t)0x677da5cb, (q31_t)0x325d0a3e,
+    (q31_t)0x67878893, (q31_t)0x32554840, (q31_t)0x679169d5, (q31_t)0x324d8450,
+    (q31_t)0x679b4990, (q31_t)0x3245be70, (q31_t)0x67a527c4, (q31_t)0x323df6a0,
+    (q31_t)0x67af0472, (q31_t)0x32362ce0, (q31_t)0x67b8df97, (q31_t)0x322e6130,
+    (q31_t)0x67c2b934, (q31_t)0x32269391, (q31_t)0x67cc9149, (q31_t)0x321ec403,
+    (q31_t)0x67d667d5, (q31_t)0x3216f287, (q31_t)0x67e03cd8, (q31_t)0x320f1f1c,
+    (q31_t)0x67ea1052, (q31_t)0x320749c3, (q31_t)0x67f3e241, (q31_t)0x31ff727c,
+    (q31_t)0x67fdb2a7, (q31_t)0x31f79948, (q31_t)0x68078181, (q31_t)0x31efbe27,
+    (q31_t)0x68114ed0, (q31_t)0x31e7e118, (q31_t)0x681b1a94, (q31_t)0x31e0021e,
+    (q31_t)0x6824e4cc, (q31_t)0x31d82137, (q31_t)0x682ead78, (q31_t)0x31d03e64,
+    (q31_t)0x68387498, (q31_t)0x31c859a5, (q31_t)0x68423a2a, (q31_t)0x31c072fb,
+    (q31_t)0x684bfe2f, (q31_t)0x31b88a66, (q31_t)0x6855c0a6, (q31_t)0x31b09fe7,
+    (q31_t)0x685f8190, (q31_t)0x31a8b37c, (q31_t)0x686940ea, (q31_t)0x31a0c528,
+    (q31_t)0x6872feb6, (q31_t)0x3198d4ea, (q31_t)0x687cbaf3, (q31_t)0x3190e2c3,
+    (q31_t)0x688675a0, (q31_t)0x3188eeb2, (q31_t)0x68902ebd, (q31_t)0x3180f8b8,
+    (q31_t)0x6899e64a, (q31_t)0x317900d6, (q31_t)0x68a39c46, (q31_t)0x3171070c,
+    (q31_t)0x68ad50b1, (q31_t)0x31690b59, (q31_t)0x68b7038b, (q31_t)0x31610dbf,
+    (q31_t)0x68c0b4d2, (q31_t)0x31590e3e, (q31_t)0x68ca6488, (q31_t)0x31510cd5,
+    (q31_t)0x68d412ab, (q31_t)0x31490986, (q31_t)0x68ddbf3b, (q31_t)0x31410450,
+    (q31_t)0x68e76a37, (q31_t)0x3138fd35, (q31_t)0x68f113a0, (q31_t)0x3130f433,
+    (q31_t)0x68fabb75, (q31_t)0x3128e94c, (q31_t)0x690461b5, (q31_t)0x3120dc80,
+    (q31_t)0x690e0661, (q31_t)0x3118cdcf, (q31_t)0x6917a977, (q31_t)0x3110bd39,
+    (q31_t)0x69214af8, (q31_t)0x3108aabf, (q31_t)0x692aeae3, (q31_t)0x31009661,
+    (q31_t)0x69348937, (q31_t)0x30f8801f, (q31_t)0x693e25f5, (q31_t)0x30f067fb,
+    (q31_t)0x6947c11c, (q31_t)0x30e84df3, (q31_t)0x69515aab, (q31_t)0x30e03208,
+    (q31_t)0x695af2a3, (q31_t)0x30d8143b, (q31_t)0x69648902, (q31_t)0x30cff48c,
+    (q31_t)0x696e1dc9, (q31_t)0x30c7d2fb, (q31_t)0x6977b0f7, (q31_t)0x30bfaf89,
+    (q31_t)0x6981428c, (q31_t)0x30b78a36, (q31_t)0x698ad287, (q31_t)0x30af6302,
+    (q31_t)0x699460e8, (q31_t)0x30a739ed, (q31_t)0x699dedaf, (q31_t)0x309f0ef8,
+    (q31_t)0x69a778db, (q31_t)0x3096e223, (q31_t)0x69b1026c, (q31_t)0x308eb36f,
+    (q31_t)0x69ba8a61, (q31_t)0x308682dc, (q31_t)0x69c410ba, (q31_t)0x307e5069,
+    (q31_t)0x69cd9578, (q31_t)0x30761c18, (q31_t)0x69d71899, (q31_t)0x306de5e9,
+    (q31_t)0x69e09a1c, (q31_t)0x3065addb, (q31_t)0x69ea1a03, (q31_t)0x305d73f0,
+    (q31_t)0x69f3984c, (q31_t)0x30553828, (q31_t)0x69fd14f6, (q31_t)0x304cfa83,
+    (q31_t)0x6a069003, (q31_t)0x3044bb00, (q31_t)0x6a100970, (q31_t)0x303c79a2,
+    (q31_t)0x6a19813f, (q31_t)0x30343667, (q31_t)0x6a22f76e, (q31_t)0x302bf151,
+    (q31_t)0x6a2c6bfd, (q31_t)0x3023aa5f, (q31_t)0x6a35deeb, (q31_t)0x301b6193,
+    (q31_t)0x6a3f503a, (q31_t)0x301316eb, (q31_t)0x6a48bfe7, (q31_t)0x300aca69,
+    (q31_t)0x6a522df3, (q31_t)0x30027c0c, (q31_t)0x6a5b9a5d, (q31_t)0x2ffa2bd6,
+    (q31_t)0x6a650525, (q31_t)0x2ff1d9c7, (q31_t)0x6a6e6e4b, (q31_t)0x2fe985de,
+    (q31_t)0x6a77d5ce, (q31_t)0x2fe1301c, (q31_t)0x6a813bae, (q31_t)0x2fd8d882,
+    (q31_t)0x6a8a9fea, (q31_t)0x2fd07f0f, (q31_t)0x6a940283, (q31_t)0x2fc823c5,
+    (q31_t)0x6a9d6377, (q31_t)0x2fbfc6a3, (q31_t)0x6aa6c2c6, (q31_t)0x2fb767aa,
+    (q31_t)0x6ab02071, (q31_t)0x2faf06da, (q31_t)0x6ab97c77, (q31_t)0x2fa6a433,
+    (q31_t)0x6ac2d6d6, (q31_t)0x2f9e3fb6, (q31_t)0x6acc2f90, (q31_t)0x2f95d963,
+    (q31_t)0x6ad586a3, (q31_t)0x2f8d713a, (q31_t)0x6adedc10, (q31_t)0x2f85073c,
+    (q31_t)0x6ae82fd5, (q31_t)0x2f7c9b69, (q31_t)0x6af181f3, (q31_t)0x2f742dc1,
+    (q31_t)0x6afad269, (q31_t)0x2f6bbe45, (q31_t)0x6b042137, (q31_t)0x2f634cf5,
+    (q31_t)0x6b0d6e5c, (q31_t)0x2f5ad9d1, (q31_t)0x6b16b9d9, (q31_t)0x2f5264da,
+    (q31_t)0x6b2003ac, (q31_t)0x2f49ee0f, (q31_t)0x6b294bd5, (q31_t)0x2f417573,
+    (q31_t)0x6b329255, (q31_t)0x2f38fb03, (q31_t)0x6b3bd72a, (q31_t)0x2f307ec2,
+    (q31_t)0x6b451a55, (q31_t)0x2f2800af, (q31_t)0x6b4e5bd4, (q31_t)0x2f1f80ca,
+    (q31_t)0x6b579ba8, (q31_t)0x2f16ff14, (q31_t)0x6b60d9d0, (q31_t)0x2f0e7b8e,
+    (q31_t)0x6b6a164d, (q31_t)0x2f05f637, (q31_t)0x6b73511c, (q31_t)0x2efd6f10,
+    (q31_t)0x6b7c8a3f, (q31_t)0x2ef4e619, (q31_t)0x6b85c1b5, (q31_t)0x2eec5b53,
+    (q31_t)0x6b8ef77d, (q31_t)0x2ee3cebe, (q31_t)0x6b982b97, (q31_t)0x2edb405a,
+    (q31_t)0x6ba15e03, (q31_t)0x2ed2b027, (q31_t)0x6baa8ec0, (q31_t)0x2eca1e27,
+    (q31_t)0x6bb3bdce, (q31_t)0x2ec18a58, (q31_t)0x6bbceb2d, (q31_t)0x2eb8f4bc,
+    (q31_t)0x6bc616dd, (q31_t)0x2eb05d53, (q31_t)0x6bcf40dc, (q31_t)0x2ea7c41e,
+    (q31_t)0x6bd8692b, (q31_t)0x2e9f291b, (q31_t)0x6be18fc9, (q31_t)0x2e968c4d,
+    (q31_t)0x6beab4b6, (q31_t)0x2e8dedb3, (q31_t)0x6bf3d7f2, (q31_t)0x2e854d4d,
+    (q31_t)0x6bfcf97c, (q31_t)0x2e7cab1c, (q31_t)0x6c061953, (q31_t)0x2e740720,
+    (q31_t)0x6c0f3779, (q31_t)0x2e6b615a, (q31_t)0x6c1853eb, (q31_t)0x2e62b9ca,
+    (q31_t)0x6c216eaa, (q31_t)0x2e5a1070, (q31_t)0x6c2a87b6, (q31_t)0x2e51654c,
+    (q31_t)0x6c339f0e, (q31_t)0x2e48b860, (q31_t)0x6c3cb4b1, (q31_t)0x2e4009aa,
+    (q31_t)0x6c45c8a0, (q31_t)0x2e37592c, (q31_t)0x6c4edada, (q31_t)0x2e2ea6e6,
+    (q31_t)0x6c57eb5e, (q31_t)0x2e25f2d8, (q31_t)0x6c60fa2d, (q31_t)0x2e1d3d03,
+    (q31_t)0x6c6a0746, (q31_t)0x2e148566, (q31_t)0x6c7312a9, (q31_t)0x2e0bcc03,
+    (q31_t)0x6c7c1c55, (q31_t)0x2e0310d9, (q31_t)0x6c85244a, (q31_t)0x2dfa53e9,
+    (q31_t)0x6c8e2a87, (q31_t)0x2df19534, (q31_t)0x6c972f0d, (q31_t)0x2de8d4b8,
+    (q31_t)0x6ca031da, (q31_t)0x2de01278, (q31_t)0x6ca932ef, (q31_t)0x2dd74e73,
+    (q31_t)0x6cb2324c, (q31_t)0x2dce88aa, (q31_t)0x6cbb2fef, (q31_t)0x2dc5c11c,
+    (q31_t)0x6cc42bd9, (q31_t)0x2dbcf7cb, (q31_t)0x6ccd2609, (q31_t)0x2db42cb6,
+    (q31_t)0x6cd61e7f, (q31_t)0x2dab5fdf, (q31_t)0x6cdf153a, (q31_t)0x2da29144,
+    (q31_t)0x6ce80a3a, (q31_t)0x2d99c0e7, (q31_t)0x6cf0fd80, (q31_t)0x2d90eec8,
+    (q31_t)0x6cf9ef09, (q31_t)0x2d881ae8, (q31_t)0x6d02ded7, (q31_t)0x2d7f4545,
+    (q31_t)0x6d0bcce8, (q31_t)0x2d766de2, (q31_t)0x6d14b93d, (q31_t)0x2d6d94bf,
+    (q31_t)0x6d1da3d5, (q31_t)0x2d64b9da, (q31_t)0x6d268cb0, (q31_t)0x2d5bdd36,
+    (q31_t)0x6d2f73cd, (q31_t)0x2d52fed2, (q31_t)0x6d38592c, (q31_t)0x2d4a1eaf,
+    (q31_t)0x6d413ccd, (q31_t)0x2d413ccd, (q31_t)0x6d4a1eaf, (q31_t)0x2d38592c,
+    (q31_t)0x6d52fed2, (q31_t)0x2d2f73cd, (q31_t)0x6d5bdd36, (q31_t)0x2d268cb0,
+    (q31_t)0x6d64b9da, (q31_t)0x2d1da3d5, (q31_t)0x6d6d94bf, (q31_t)0x2d14b93d,
+    (q31_t)0x6d766de2, (q31_t)0x2d0bcce8, (q31_t)0x6d7f4545, (q31_t)0x2d02ded7,
+    (q31_t)0x6d881ae8, (q31_t)0x2cf9ef09, (q31_t)0x6d90eec8, (q31_t)0x2cf0fd80,
+    (q31_t)0x6d99c0e7, (q31_t)0x2ce80a3a, (q31_t)0x6da29144, (q31_t)0x2cdf153a,
+    (q31_t)0x6dab5fdf, (q31_t)0x2cd61e7f, (q31_t)0x6db42cb6, (q31_t)0x2ccd2609,
+    (q31_t)0x6dbcf7cb, (q31_t)0x2cc42bd9, (q31_t)0x6dc5c11c, (q31_t)0x2cbb2fef,
+    (q31_t)0x6dce88aa, (q31_t)0x2cb2324c, (q31_t)0x6dd74e73, (q31_t)0x2ca932ef,
+    (q31_t)0x6de01278, (q31_t)0x2ca031da, (q31_t)0x6de8d4b8, (q31_t)0x2c972f0d,
+    (q31_t)0x6df19534, (q31_t)0x2c8e2a87, (q31_t)0x6dfa53e9, (q31_t)0x2c85244a,
+    (q31_t)0x6e0310d9, (q31_t)0x2c7c1c55, (q31_t)0x6e0bcc03, (q31_t)0x2c7312a9,
+    (q31_t)0x6e148566, (q31_t)0x2c6a0746, (q31_t)0x6e1d3d03, (q31_t)0x2c60fa2d,
+    (q31_t)0x6e25f2d8, (q31_t)0x2c57eb5e, (q31_t)0x6e2ea6e6, (q31_t)0x2c4edada,
+    (q31_t)0x6e37592c, (q31_t)0x2c45c8a0, (q31_t)0x6e4009aa, (q31_t)0x2c3cb4b1,
+    (q31_t)0x6e48b860, (q31_t)0x2c339f0e, (q31_t)0x6e51654c, (q31_t)0x2c2a87b6,
+    (q31_t)0x6e5a1070, (q31_t)0x2c216eaa, (q31_t)0x6e62b9ca, (q31_t)0x2c1853eb,
+    (q31_t)0x6e6b615a, (q31_t)0x2c0f3779, (q31_t)0x6e740720, (q31_t)0x2c061953,
+    (q31_t)0x6e7cab1c, (q31_t)0x2bfcf97c, (q31_t)0x6e854d4d, (q31_t)0x2bf3d7f2,
+    (q31_t)0x6e8dedb3, (q31_t)0x2beab4b6, (q31_t)0x6e968c4d, (q31_t)0x2be18fc9,
+    (q31_t)0x6e9f291b, (q31_t)0x2bd8692b, (q31_t)0x6ea7c41e, (q31_t)0x2bcf40dc,
+    (q31_t)0x6eb05d53, (q31_t)0x2bc616dd, (q31_t)0x6eb8f4bc, (q31_t)0x2bbceb2d,
+    (q31_t)0x6ec18a58, (q31_t)0x2bb3bdce, (q31_t)0x6eca1e27, (q31_t)0x2baa8ec0,
+    (q31_t)0x6ed2b027, (q31_t)0x2ba15e03, (q31_t)0x6edb405a, (q31_t)0x2b982b97,
+    (q31_t)0x6ee3cebe, (q31_t)0x2b8ef77d, (q31_t)0x6eec5b53, (q31_t)0x2b85c1b5,
+    (q31_t)0x6ef4e619, (q31_t)0x2b7c8a3f, (q31_t)0x6efd6f10, (q31_t)0x2b73511c,
+    (q31_t)0x6f05f637, (q31_t)0x2b6a164d, (q31_t)0x6f0e7b8e, (q31_t)0x2b60d9d0,
+    (q31_t)0x6f16ff14, (q31_t)0x2b579ba8, (q31_t)0x6f1f80ca, (q31_t)0x2b4e5bd4,
+    (q31_t)0x6f2800af, (q31_t)0x2b451a55, (q31_t)0x6f307ec2, (q31_t)0x2b3bd72a,
+    (q31_t)0x6f38fb03, (q31_t)0x2b329255, (q31_t)0x6f417573, (q31_t)0x2b294bd5,
+    (q31_t)0x6f49ee0f, (q31_t)0x2b2003ac, (q31_t)0x6f5264da, (q31_t)0x2b16b9d9,
+    (q31_t)0x6f5ad9d1, (q31_t)0x2b0d6e5c, (q31_t)0x6f634cf5, (q31_t)0x2b042137,
+    (q31_t)0x6f6bbe45, (q31_t)0x2afad269, (q31_t)0x6f742dc1, (q31_t)0x2af181f3,
+    (q31_t)0x6f7c9b69, (q31_t)0x2ae82fd5, (q31_t)0x6f85073c, (q31_t)0x2adedc10,
+    (q31_t)0x6f8d713a, (q31_t)0x2ad586a3, (q31_t)0x6f95d963, (q31_t)0x2acc2f90,
+    (q31_t)0x6f9e3fb6, (q31_t)0x2ac2d6d6, (q31_t)0x6fa6a433, (q31_t)0x2ab97c77,
+    (q31_t)0x6faf06da, (q31_t)0x2ab02071, (q31_t)0x6fb767aa, (q31_t)0x2aa6c2c6,
+    (q31_t)0x6fbfc6a3, (q31_t)0x2a9d6377, (q31_t)0x6fc823c5, (q31_t)0x2a940283,
+    (q31_t)0x6fd07f0f, (q31_t)0x2a8a9fea, (q31_t)0x6fd8d882, (q31_t)0x2a813bae,
+    (q31_t)0x6fe1301c, (q31_t)0x2a77d5ce, (q31_t)0x6fe985de, (q31_t)0x2a6e6e4b,
+    (q31_t)0x6ff1d9c7, (q31_t)0x2a650525, (q31_t)0x6ffa2bd6, (q31_t)0x2a5b9a5d,
+    (q31_t)0x70027c0c, (q31_t)0x2a522df3, (q31_t)0x700aca69, (q31_t)0x2a48bfe7,
+    (q31_t)0x701316eb, (q31_t)0x2a3f503a, (q31_t)0x701b6193, (q31_t)0x2a35deeb,
+    (q31_t)0x7023aa5f, (q31_t)0x2a2c6bfd, (q31_t)0x702bf151, (q31_t)0x2a22f76e,
+    (q31_t)0x70343667, (q31_t)0x2a19813f, (q31_t)0x703c79a2, (q31_t)0x2a100970,
+    (q31_t)0x7044bb00, (q31_t)0x2a069003, (q31_t)0x704cfa83, (q31_t)0x29fd14f6,
+    (q31_t)0x70553828, (q31_t)0x29f3984c, (q31_t)0x705d73f0, (q31_t)0x29ea1a03,
+    (q31_t)0x7065addb, (q31_t)0x29e09a1c, (q31_t)0x706de5e9, (q31_t)0x29d71899,
+    (q31_t)0x70761c18, (q31_t)0x29cd9578, (q31_t)0x707e5069, (q31_t)0x29c410ba,
+    (q31_t)0x708682dc, (q31_t)0x29ba8a61, (q31_t)0x708eb36f, (q31_t)0x29b1026c,
+    (q31_t)0x7096e223, (q31_t)0x29a778db, (q31_t)0x709f0ef8, (q31_t)0x299dedaf,
+    (q31_t)0x70a739ed, (q31_t)0x299460e8, (q31_t)0x70af6302, (q31_t)0x298ad287,
+    (q31_t)0x70b78a36, (q31_t)0x2981428c, (q31_t)0x70bfaf89, (q31_t)0x2977b0f7,
+    (q31_t)0x70c7d2fb, (q31_t)0x296e1dc9, (q31_t)0x70cff48c, (q31_t)0x29648902,
+    (q31_t)0x70d8143b, (q31_t)0x295af2a3, (q31_t)0x70e03208, (q31_t)0x29515aab,
+    (q31_t)0x70e84df3, (q31_t)0x2947c11c, (q31_t)0x70f067fb, (q31_t)0x293e25f5,
+    (q31_t)0x70f8801f, (q31_t)0x29348937, (q31_t)0x71009661, (q31_t)0x292aeae3,
+    (q31_t)0x7108aabf, (q31_t)0x29214af8, (q31_t)0x7110bd39, (q31_t)0x2917a977,
+    (q31_t)0x7118cdcf, (q31_t)0x290e0661, (q31_t)0x7120dc80, (q31_t)0x290461b5,
+    (q31_t)0x7128e94c, (q31_t)0x28fabb75, (q31_t)0x7130f433, (q31_t)0x28f113a0,
+    (q31_t)0x7138fd35, (q31_t)0x28e76a37, (q31_t)0x71410450, (q31_t)0x28ddbf3b,
+    (q31_t)0x71490986, (q31_t)0x28d412ab, (q31_t)0x71510cd5, (q31_t)0x28ca6488,
+    (q31_t)0x71590e3e, (q31_t)0x28c0b4d2, (q31_t)0x71610dbf, (q31_t)0x28b7038b,
+    (q31_t)0x71690b59, (q31_t)0x28ad50b1, (q31_t)0x7171070c, (q31_t)0x28a39c46,
+    (q31_t)0x717900d6, (q31_t)0x2899e64a, (q31_t)0x7180f8b8, (q31_t)0x28902ebd,
+    (q31_t)0x7188eeb2, (q31_t)0x288675a0, (q31_t)0x7190e2c3, (q31_t)0x287cbaf3,
+    (q31_t)0x7198d4ea, (q31_t)0x2872feb6, (q31_t)0x71a0c528, (q31_t)0x286940ea,
+    (q31_t)0x71a8b37c, (q31_t)0x285f8190, (q31_t)0x71b09fe7, (q31_t)0x2855c0a6,
+    (q31_t)0x71b88a66, (q31_t)0x284bfe2f, (q31_t)0x71c072fb, (q31_t)0x28423a2a,
+    (q31_t)0x71c859a5, (q31_t)0x28387498, (q31_t)0x71d03e64, (q31_t)0x282ead78,
+    (q31_t)0x71d82137, (q31_t)0x2824e4cc, (q31_t)0x71e0021e, (q31_t)0x281b1a94,
+    (q31_t)0x71e7e118, (q31_t)0x28114ed0, (q31_t)0x71efbe27, (q31_t)0x28078181,
+    (q31_t)0x71f79948, (q31_t)0x27fdb2a7, (q31_t)0x71ff727c, (q31_t)0x27f3e241,
+    (q31_t)0x720749c3, (q31_t)0x27ea1052, (q31_t)0x720f1f1c, (q31_t)0x27e03cd8,
+    (q31_t)0x7216f287, (q31_t)0x27d667d5, (q31_t)0x721ec403, (q31_t)0x27cc9149,
+    (q31_t)0x72269391, (q31_t)0x27c2b934, (q31_t)0x722e6130, (q31_t)0x27b8df97,
+    (q31_t)0x72362ce0, (q31_t)0x27af0472, (q31_t)0x723df6a0, (q31_t)0x27a527c4,
+    (q31_t)0x7245be70, (q31_t)0x279b4990, (q31_t)0x724d8450, (q31_t)0x279169d5,
+    (q31_t)0x72554840, (q31_t)0x27878893, (q31_t)0x725d0a3e, (q31_t)0x277da5cb,
+    (q31_t)0x7264ca4c, (q31_t)0x2773c17d, (q31_t)0x726c8868, (q31_t)0x2769dbaa,
+    (q31_t)0x72744493, (q31_t)0x275ff452, (q31_t)0x727bfecc, (q31_t)0x27560b76,
+    (q31_t)0x7283b712, (q31_t)0x274c2115, (q31_t)0x728b6d66, (q31_t)0x27423530,
+    (q31_t)0x729321c7, (q31_t)0x273847c8, (q31_t)0x729ad435, (q31_t)0x272e58dc,
+    (q31_t)0x72a284b0, (q31_t)0x2724686e, (q31_t)0x72aa3336, (q31_t)0x271a767e,
+    (q31_t)0x72b1dfc9, (q31_t)0x2710830c, (q31_t)0x72b98a67, (q31_t)0x27068e18,
+    (q31_t)0x72c13311, (q31_t)0x26fc97a3, (q31_t)0x72c8d9c6, (q31_t)0x26f29fad,
+    (q31_t)0x72d07e85, (q31_t)0x26e8a637, (q31_t)0x72d82150, (q31_t)0x26deab41,
+    (q31_t)0x72dfc224, (q31_t)0x26d4aecb, (q31_t)0x72e76102, (q31_t)0x26cab0d6,
+    (q31_t)0x72eefdea, (q31_t)0x26c0b162, (q31_t)0x72f698db, (q31_t)0x26b6b070,
+    (q31_t)0x72fe31d5, (q31_t)0x26acadff, (q31_t)0x7305c8d7, (q31_t)0x26a2aa11,
+    (q31_t)0x730d5de3, (q31_t)0x2698a4a6, (q31_t)0x7314f0f6, (q31_t)0x268e9dbd,
+    (q31_t)0x731c8211, (q31_t)0x26849558, (q31_t)0x73241134, (q31_t)0x267a8b77,
+    (q31_t)0x732b9e5e, (q31_t)0x2670801a, (q31_t)0x7333298f, (q31_t)0x26667342,
+    (q31_t)0x733ab2c6, (q31_t)0x265c64ef, (q31_t)0x73423a04, (q31_t)0x26525521,
+    (q31_t)0x7349bf48, (q31_t)0x264843d9, (q31_t)0x73514292, (q31_t)0x263e3117,
+    (q31_t)0x7358c3e2, (q31_t)0x26341cdb, (q31_t)0x73604336, (q31_t)0x262a0727,
+    (q31_t)0x7367c090, (q31_t)0x261feffa, (q31_t)0x736f3bee, (q31_t)0x2615d754,
+    (q31_t)0x7376b551, (q31_t)0x260bbd37, (q31_t)0x737e2cb7, (q31_t)0x2601a1a2,
+    (q31_t)0x7385a222, (q31_t)0x25f78497, (q31_t)0x738d1590, (q31_t)0x25ed6614,
+    (q31_t)0x73948701, (q31_t)0x25e3461b, (q31_t)0x739bf675, (q31_t)0x25d924ac,
+    (q31_t)0x73a363ec, (q31_t)0x25cf01c8, (q31_t)0x73aacf65, (q31_t)0x25c4dd6e,
+    (q31_t)0x73b238e0, (q31_t)0x25bab7a0, (q31_t)0x73b9a05d, (q31_t)0x25b0905d,
+    (q31_t)0x73c105db, (q31_t)0x25a667a7, (q31_t)0x73c8695b, (q31_t)0x259c3d7c,
+    (q31_t)0x73cfcadc, (q31_t)0x259211df, (q31_t)0x73d72a5d, (q31_t)0x2587e4cf,
+    (q31_t)0x73de87de, (q31_t)0x257db64c, (q31_t)0x73e5e360, (q31_t)0x25738657,
+    (q31_t)0x73ed3ce1, (q31_t)0x256954f1, (q31_t)0x73f49462, (q31_t)0x255f2219,
+    (q31_t)0x73fbe9e2, (q31_t)0x2554edd1, (q31_t)0x74033d61, (q31_t)0x254ab818,
+    (q31_t)0x740a8edf, (q31_t)0x254080ef, (q31_t)0x7411de5b, (q31_t)0x25364857,
+    (q31_t)0x74192bd5, (q31_t)0x252c0e4f, (q31_t)0x7420774d, (q31_t)0x2521d2d8,
+    (q31_t)0x7427c0c3, (q31_t)0x251795f3, (q31_t)0x742f0836, (q31_t)0x250d57a0,
+    (q31_t)0x74364da6, (q31_t)0x250317df, (q31_t)0x743d9112, (q31_t)0x24f8d6b0,
+    (q31_t)0x7444d27b, (q31_t)0x24ee9415, (q31_t)0x744c11e0, (q31_t)0x24e4500e,
+    (q31_t)0x74534f41, (q31_t)0x24da0a9a, (q31_t)0x745a8a9d, (q31_t)0x24cfc3ba,
+    (q31_t)0x7461c3f5, (q31_t)0x24c57b6f, (q31_t)0x7468fb47, (q31_t)0x24bb31ba,
+    (q31_t)0x74703095, (q31_t)0x24b0e699, (q31_t)0x747763dd, (q31_t)0x24a69a0f,
+    (q31_t)0x747e951f, (q31_t)0x249c4c1b, (q31_t)0x7485c45b, (q31_t)0x2491fcbe,
+    (q31_t)0x748cf190, (q31_t)0x2487abf7, (q31_t)0x74941cbf, (q31_t)0x247d59c8,
+    (q31_t)0x749b45e7, (q31_t)0x24730631, (q31_t)0x74a26d08, (q31_t)0x2468b132,
+    (q31_t)0x74a99221, (q31_t)0x245e5acc, (q31_t)0x74b0b533, (q31_t)0x245402ff,
+    (q31_t)0x74b7d63c, (q31_t)0x2449a9cc, (q31_t)0x74bef53d, (q31_t)0x243f4f32,
+    (q31_t)0x74c61236, (q31_t)0x2434f332, (q31_t)0x74cd2d26, (q31_t)0x242a95ce,
+    (q31_t)0x74d4460c, (q31_t)0x24203704, (q31_t)0x74db5cea, (q31_t)0x2415d6d5,
+    (q31_t)0x74e271bd, (q31_t)0x240b7543, (q31_t)0x74e98487, (q31_t)0x2401124d,
+    (q31_t)0x74f09546, (q31_t)0x23f6adf3, (q31_t)0x74f7a3fb, (q31_t)0x23ec4837,
+    (q31_t)0x74feb0a5, (q31_t)0x23e1e117, (q31_t)0x7505bb44, (q31_t)0x23d77896,
+    (q31_t)0x750cc3d8, (q31_t)0x23cd0eb3, (q31_t)0x7513ca60, (q31_t)0x23c2a36f,
+    (q31_t)0x751acedd, (q31_t)0x23b836ca, (q31_t)0x7521d14d, (q31_t)0x23adc8c4,
+    (q31_t)0x7528d1b1, (q31_t)0x23a3595e, (q31_t)0x752fd008, (q31_t)0x2398e898,
+    (q31_t)0x7536cc52, (q31_t)0x238e7673, (q31_t)0x753dc68f, (q31_t)0x238402ef,
+    (q31_t)0x7544bebf, (q31_t)0x23798e0d, (q31_t)0x754bb4e1, (q31_t)0x236f17cc,
+    (q31_t)0x7552a8f4, (q31_t)0x2364a02e, (q31_t)0x75599afa, (q31_t)0x235a2733,
+    (q31_t)0x75608af1, (q31_t)0x234facda, (q31_t)0x756778d9, (q31_t)0x23453125,
+    (q31_t)0x756e64b2, (q31_t)0x233ab414, (q31_t)0x75754e7c, (q31_t)0x233035a7,
+    (q31_t)0x757c3636, (q31_t)0x2325b5df, (q31_t)0x75831be0, (q31_t)0x231b34bc,
+    (q31_t)0x7589ff7a, (q31_t)0x2310b23e, (q31_t)0x7590e104, (q31_t)0x23062e67,
+    (q31_t)0x7597c07d, (q31_t)0x22fba936, (q31_t)0x759e9de5, (q31_t)0x22f122ab,
+    (q31_t)0x75a5793c, (q31_t)0x22e69ac8, (q31_t)0x75ac5282, (q31_t)0x22dc118c,
+    (q31_t)0x75b329b5, (q31_t)0x22d186f8, (q31_t)0x75b9fed7, (q31_t)0x22c6fb0c,
+    (q31_t)0x75c0d1e7, (q31_t)0x22bc6dca, (q31_t)0x75c7a2e3, (q31_t)0x22b1df30,
+    (q31_t)0x75ce71ce, (q31_t)0x22a74f40, (q31_t)0x75d53ea5, (q31_t)0x229cbdfa,
+    (q31_t)0x75dc0968, (q31_t)0x22922b5e, (q31_t)0x75e2d219, (q31_t)0x2287976e,
+    (q31_t)0x75e998b5, (q31_t)0x227d0228, (q31_t)0x75f05d3d, (q31_t)0x22726b8e,
+    (q31_t)0x75f71fb1, (q31_t)0x2267d3a0, (q31_t)0x75fde011, (q31_t)0x225d3a5e,
+    (q31_t)0x76049e5b, (q31_t)0x22529fca, (q31_t)0x760b5a90, (q31_t)0x224803e2,
+    (q31_t)0x761214b0, (q31_t)0x223d66a8, (q31_t)0x7618ccba, (q31_t)0x2232c81c,
+    (q31_t)0x761f82af, (q31_t)0x2228283f, (q31_t)0x7626368d, (q31_t)0x221d8711,
+    (q31_t)0x762ce855, (q31_t)0x2212e492, (q31_t)0x76339806, (q31_t)0x220840c2,
+    (q31_t)0x763a45a0, (q31_t)0x21fd9ba3, (q31_t)0x7640f123, (q31_t)0x21f2f534,
+    (q31_t)0x76479a8e, (q31_t)0x21e84d76, (q31_t)0x764e41e2, (q31_t)0x21dda46a,
+    (q31_t)0x7654e71d, (q31_t)0x21d2fa0f, (q31_t)0x765b8a41, (q31_t)0x21c84e67,
+    (q31_t)0x76622b4c, (q31_t)0x21bda171, (q31_t)0x7668ca3e, (q31_t)0x21b2f32e,
+    (q31_t)0x766f6717, (q31_t)0x21a8439e, (q31_t)0x767601d7, (q31_t)0x219d92c2,
+    (q31_t)0x767c9a7e, (q31_t)0x2192e09b, (q31_t)0x7683310b, (q31_t)0x21882d28,
+    (q31_t)0x7689c57d, (q31_t)0x217d786a, (q31_t)0x769057d6, (q31_t)0x2172c262,
+    (q31_t)0x7696e814, (q31_t)0x21680b0f, (q31_t)0x769d7637, (q31_t)0x215d5273,
+    (q31_t)0x76a4023f, (q31_t)0x2152988d, (q31_t)0x76aa8c2c, (q31_t)0x2147dd5f,
+    (q31_t)0x76b113fd, (q31_t)0x213d20e8, (q31_t)0x76b799b3, (q31_t)0x21326329,
+    (q31_t)0x76be1d4c, (q31_t)0x2127a423, (q31_t)0x76c49ec9, (q31_t)0x211ce3d5,
+    (q31_t)0x76cb1e2a, (q31_t)0x21122240, (q31_t)0x76d19b6e, (q31_t)0x21075f65,
+    (q31_t)0x76d81695, (q31_t)0x20fc9b44, (q31_t)0x76de8f9e, (q31_t)0x20f1d5de,
+    (q31_t)0x76e5068a, (q31_t)0x20e70f32, (q31_t)0x76eb7b58, (q31_t)0x20dc4742,
+    (q31_t)0x76f1ee09, (q31_t)0x20d17e0d, (q31_t)0x76f85e9a, (q31_t)0x20c6b395,
+    (q31_t)0x76fecd0e, (q31_t)0x20bbe7d8, (q31_t)0x77053962, (q31_t)0x20b11ad9,
+    (q31_t)0x770ba398, (q31_t)0x20a64c97, (q31_t)0x77120bae, (q31_t)0x209b7d13,
+    (q31_t)0x771871a5, (q31_t)0x2090ac4d, (q31_t)0x771ed57c, (q31_t)0x2085da46,
+    (q31_t)0x77253733, (q31_t)0x207b06fe, (q31_t)0x772b96ca, (q31_t)0x20703275,
+    (q31_t)0x7731f440, (q31_t)0x20655cac, (q31_t)0x77384f95, (q31_t)0x205a85a3,
+    (q31_t)0x773ea8ca, (q31_t)0x204fad5b, (q31_t)0x7744ffdd, (q31_t)0x2044d3d4,
+    (q31_t)0x774b54ce, (q31_t)0x2039f90f, (q31_t)0x7751a79e, (q31_t)0x202f1d0b,
+    (q31_t)0x7757f84c, (q31_t)0x20243fca, (q31_t)0x775e46d8, (q31_t)0x2019614c,
+    (q31_t)0x77649341, (q31_t)0x200e8190, (q31_t)0x776add88, (q31_t)0x2003a099,
+    (q31_t)0x777125ac, (q31_t)0x1ff8be65, (q31_t)0x77776bac, (q31_t)0x1feddaf6,
+    (q31_t)0x777daf89, (q31_t)0x1fe2f64c, (q31_t)0x7783f143, (q31_t)0x1fd81067,
+    (q31_t)0x778a30d8, (q31_t)0x1fcd2948, (q31_t)0x77906e49, (q31_t)0x1fc240ef,
+    (q31_t)0x7796a996, (q31_t)0x1fb7575c, (q31_t)0x779ce2be, (q31_t)0x1fac6c91,
+    (q31_t)0x77a319c2, (q31_t)0x1fa1808c, (q31_t)0x77a94ea0, (q31_t)0x1f969350,
+    (q31_t)0x77af8159, (q31_t)0x1f8ba4dc, (q31_t)0x77b5b1ec, (q31_t)0x1f80b531,
+    (q31_t)0x77bbe05a, (q31_t)0x1f75c44e, (q31_t)0x77c20ca1, (q31_t)0x1f6ad235,
+    (q31_t)0x77c836c2, (q31_t)0x1f5fdee6, (q31_t)0x77ce5ebd, (q31_t)0x1f54ea62,
+    (q31_t)0x77d48490, (q31_t)0x1f49f4a8, (q31_t)0x77daa83d, (q31_t)0x1f3efdb9,
+    (q31_t)0x77e0c9c3, (q31_t)0x1f340596, (q31_t)0x77e6e921, (q31_t)0x1f290c3f,
+    (q31_t)0x77ed0657, (q31_t)0x1f1e11b5, (q31_t)0x77f32165, (q31_t)0x1f1315f7,
+    (q31_t)0x77f93a4b, (q31_t)0x1f081907, (q31_t)0x77ff5109, (q31_t)0x1efd1ae4,
+    (q31_t)0x7805659e, (q31_t)0x1ef21b90, (q31_t)0x780b780a, (q31_t)0x1ee71b0a,
+    (q31_t)0x7811884d, (q31_t)0x1edc1953, (q31_t)0x78179666, (q31_t)0x1ed1166b,
+    (q31_t)0x781da256, (q31_t)0x1ec61254, (q31_t)0x7823ac1d, (q31_t)0x1ebb0d0d,
+    (q31_t)0x7829b3b9, (q31_t)0x1eb00696, (q31_t)0x782fb92a, (q31_t)0x1ea4fef0,
+    (q31_t)0x7835bc71, (q31_t)0x1e99f61d, (q31_t)0x783bbd8e, (q31_t)0x1e8eec1b,
+    (q31_t)0x7841bc7f, (q31_t)0x1e83e0eb, (q31_t)0x7847b946, (q31_t)0x1e78d48e,
+    (q31_t)0x784db3e0, (q31_t)0x1e6dc705, (q31_t)0x7853ac4f, (q31_t)0x1e62b84f,
+    (q31_t)0x7859a292, (q31_t)0x1e57a86d, (q31_t)0x785f96a9, (q31_t)0x1e4c9760,
+    (q31_t)0x78658894, (q31_t)0x1e418528, (q31_t)0x786b7852, (q31_t)0x1e3671c5,
+    (q31_t)0x787165e3, (q31_t)0x1e2b5d38, (q31_t)0x78775147, (q31_t)0x1e204781,
+    (q31_t)0x787d3a7e, (q31_t)0x1e1530a1, (q31_t)0x78832187, (q31_t)0x1e0a1898,
+    (q31_t)0x78890663, (q31_t)0x1dfeff67, (q31_t)0x788ee910, (q31_t)0x1df3e50d,
+    (q31_t)0x7894c98f, (q31_t)0x1de8c98c, (q31_t)0x789aa7e0, (q31_t)0x1dddace4,
+    (q31_t)0x78a08402, (q31_t)0x1dd28f15, (q31_t)0x78a65df6, (q31_t)0x1dc7701f,
+    (q31_t)0x78ac35ba, (q31_t)0x1dbc5004, (q31_t)0x78b20b4f, (q31_t)0x1db12ec3,
+    (q31_t)0x78b7deb4, (q31_t)0x1da60c5d, (q31_t)0x78bdafea, (q31_t)0x1d9ae8d2,
+    (q31_t)0x78c37eef, (q31_t)0x1d8fc424, (q31_t)0x78c94bc4, (q31_t)0x1d849e51,
+    (q31_t)0x78cf1669, (q31_t)0x1d79775c, (q31_t)0x78d4dedd, (q31_t)0x1d6e4f43,
+    (q31_t)0x78daa520, (q31_t)0x1d632608, (q31_t)0x78e06932, (q31_t)0x1d57fbaa,
+    (q31_t)0x78e62b13, (q31_t)0x1d4cd02c, (q31_t)0x78ebeac2, (q31_t)0x1d41a38c,
+    (q31_t)0x78f1a840, (q31_t)0x1d3675cb, (q31_t)0x78f7638b, (q31_t)0x1d2b46ea,
+    (q31_t)0x78fd1ca4, (q31_t)0x1d2016e9, (q31_t)0x7902d38b, (q31_t)0x1d14e5c9,
+    (q31_t)0x7908883f, (q31_t)0x1d09b389, (q31_t)0x790e3ac0, (q31_t)0x1cfe802b,
+    (q31_t)0x7913eb0e, (q31_t)0x1cf34baf, (q31_t)0x79199929, (q31_t)0x1ce81615,
+    (q31_t)0x791f4510, (q31_t)0x1cdcdf5e, (q31_t)0x7924eec3, (q31_t)0x1cd1a78a,
+    (q31_t)0x792a9642, (q31_t)0x1cc66e99, (q31_t)0x79303b8e, (q31_t)0x1cbb348d,
+    (q31_t)0x7935dea4, (q31_t)0x1caff965, (q31_t)0x793b7f86, (q31_t)0x1ca4bd21,
+    (q31_t)0x79411e33, (q31_t)0x1c997fc4, (q31_t)0x7946baac, (q31_t)0x1c8e414b,
+    (q31_t)0x794c54ee, (q31_t)0x1c8301b9, (q31_t)0x7951ecfc, (q31_t)0x1c77c10e,
+    (q31_t)0x795782d3, (q31_t)0x1c6c7f4a, (q31_t)0x795d1675, (q31_t)0x1c613c6d,
+    (q31_t)0x7962a7e0, (q31_t)0x1c55f878, (q31_t)0x79683715, (q31_t)0x1c4ab36b,
+    (q31_t)0x796dc414, (q31_t)0x1c3f6d47, (q31_t)0x79734edc, (q31_t)0x1c34260c,
+    (q31_t)0x7978d76c, (q31_t)0x1c28ddbb, (q31_t)0x797e5dc6, (q31_t)0x1c1d9454,
+    (q31_t)0x7983e1e8, (q31_t)0x1c1249d8, (q31_t)0x798963d2, (q31_t)0x1c06fe46,
+    (q31_t)0x798ee385, (q31_t)0x1bfbb1a0, (q31_t)0x799460ff, (q31_t)0x1bf063e6,
+    (q31_t)0x7999dc42, (q31_t)0x1be51518, (q31_t)0x799f554b, (q31_t)0x1bd9c537,
+    (q31_t)0x79a4cc1c, (q31_t)0x1bce7442, (q31_t)0x79aa40b4, (q31_t)0x1bc3223c,
+    (q31_t)0x79afb313, (q31_t)0x1bb7cf23, (q31_t)0x79b52339, (q31_t)0x1bac7af9,
+    (q31_t)0x79ba9125, (q31_t)0x1ba125bd, (q31_t)0x79bffcd7, (q31_t)0x1b95cf71,
+    (q31_t)0x79c5664f, (q31_t)0x1b8a7815, (q31_t)0x79cacd8d, (q31_t)0x1b7f1fa9,
+    (q31_t)0x79d03291, (q31_t)0x1b73c62d, (q31_t)0x79d5955a, (q31_t)0x1b686ba3,
+    (q31_t)0x79daf5e8, (q31_t)0x1b5d100a, (q31_t)0x79e0543c, (q31_t)0x1b51b363,
+    (q31_t)0x79e5b054, (q31_t)0x1b4655ae, (q31_t)0x79eb0a31, (q31_t)0x1b3af6ec,
+    (q31_t)0x79f061d2, (q31_t)0x1b2f971e, (q31_t)0x79f5b737, (q31_t)0x1b243643,
+    (q31_t)0x79fb0a60, (q31_t)0x1b18d45c, (q31_t)0x7a005b4d, (q31_t)0x1b0d716a,
+    (q31_t)0x7a05a9fd, (q31_t)0x1b020d6c, (q31_t)0x7a0af671, (q31_t)0x1af6a865,
+    (q31_t)0x7a1040a8, (q31_t)0x1aeb4253, (q31_t)0x7a1588a2, (q31_t)0x1adfdb37,
+    (q31_t)0x7a1ace5f, (q31_t)0x1ad47312, (q31_t)0x7a2011de, (q31_t)0x1ac909e5,
+    (q31_t)0x7a25531f, (q31_t)0x1abd9faf, (q31_t)0x7a2a9223, (q31_t)0x1ab23471,
+    (q31_t)0x7a2fcee8, (q31_t)0x1aa6c82b, (q31_t)0x7a350970, (q31_t)0x1a9b5adf,
+    (q31_t)0x7a3a41b9, (q31_t)0x1a8fec8c, (q31_t)0x7a3f77c3, (q31_t)0x1a847d33,
+    (q31_t)0x7a44ab8e, (q31_t)0x1a790cd4, (q31_t)0x7a49dd1a, (q31_t)0x1a6d9b70,
+    (q31_t)0x7a4f0c67, (q31_t)0x1a622907, (q31_t)0x7a543974, (q31_t)0x1a56b599,
+    (q31_t)0x7a596442, (q31_t)0x1a4b4128, (q31_t)0x7a5e8cd0, (q31_t)0x1a3fcbb3,
+    (q31_t)0x7a63b31d, (q31_t)0x1a34553b, (q31_t)0x7a68d72b, (q31_t)0x1a28ddc0,
+    (q31_t)0x7a6df8f8, (q31_t)0x1a1d6544, (q31_t)0x7a731884, (q31_t)0x1a11ebc5,
+    (q31_t)0x7a7835cf, (q31_t)0x1a067145, (q31_t)0x7a7d50da, (q31_t)0x19faf5c5,
+    (q31_t)0x7a8269a3, (q31_t)0x19ef7944, (q31_t)0x7a87802a, (q31_t)0x19e3fbc3,
+    (q31_t)0x7a8c9470, (q31_t)0x19d87d42, (q31_t)0x7a91a674, (q31_t)0x19ccfdc2,
+    (q31_t)0x7a96b636, (q31_t)0x19c17d44, (q31_t)0x7a9bc3b6, (q31_t)0x19b5fbc8,
+    (q31_t)0x7aa0cef3, (q31_t)0x19aa794d, (q31_t)0x7aa5d7ee, (q31_t)0x199ef5d6,
+    (q31_t)0x7aaadea6, (q31_t)0x19937161, (q31_t)0x7aafe31b, (q31_t)0x1987ebf0,
+    (q31_t)0x7ab4e54c, (q31_t)0x197c6584, (q31_t)0x7ab9e53a, (q31_t)0x1970de1b,
+    (q31_t)0x7abee2e5, (q31_t)0x196555b8, (q31_t)0x7ac3de4c, (q31_t)0x1959cc5a,
+    (q31_t)0x7ac8d76f, (q31_t)0x194e4201, (q31_t)0x7acdce4d, (q31_t)0x1942b6af,
+    (q31_t)0x7ad2c2e8, (q31_t)0x19372a64, (q31_t)0x7ad7b53d, (q31_t)0x192b9d1f,
+    (q31_t)0x7adca54e, (q31_t)0x19200ee3, (q31_t)0x7ae1931a, (q31_t)0x19147fae,
+    (q31_t)0x7ae67ea1, (q31_t)0x1908ef82, (q31_t)0x7aeb67e3, (q31_t)0x18fd5e5f,
+    (q31_t)0x7af04edf, (q31_t)0x18f1cc45, (q31_t)0x7af53395, (q31_t)0x18e63935,
+    (q31_t)0x7afa1605, (q31_t)0x18daa52f, (q31_t)0x7afef630, (q31_t)0x18cf1034,
+    (q31_t)0x7b03d414, (q31_t)0x18c37a44, (q31_t)0x7b08afb2, (q31_t)0x18b7e35f,
+    (q31_t)0x7b0d8909, (q31_t)0x18ac4b87, (q31_t)0x7b126019, (q31_t)0x18a0b2bb,
+    (q31_t)0x7b1734e2, (q31_t)0x189518fc, (q31_t)0x7b1c0764, (q31_t)0x18897e4a,
+    (q31_t)0x7b20d79e, (q31_t)0x187de2a7, (q31_t)0x7b25a591, (q31_t)0x18724611,
+    (q31_t)0x7b2a713d, (q31_t)0x1866a88a, (q31_t)0x7b2f3aa0, (q31_t)0x185b0a13,
+    (q31_t)0x7b3401bb, (q31_t)0x184f6aab, (q31_t)0x7b38c68e, (q31_t)0x1843ca53,
+    (q31_t)0x7b3d8918, (q31_t)0x1838290c, (q31_t)0x7b42495a, (q31_t)0x182c86d5,
+    (q31_t)0x7b470753, (q31_t)0x1820e3b0, (q31_t)0x7b4bc303, (q31_t)0x18153f9d,
+    (q31_t)0x7b507c69, (q31_t)0x18099a9c, (q31_t)0x7b553386, (q31_t)0x17fdf4ae,
+    (q31_t)0x7b59e85a, (q31_t)0x17f24dd3, (q31_t)0x7b5e9ae4, (q31_t)0x17e6a60c,
+    (q31_t)0x7b634b23, (q31_t)0x17dafd59, (q31_t)0x7b67f919, (q31_t)0x17cf53bb,
+    (q31_t)0x7b6ca4c4, (q31_t)0x17c3a931, (q31_t)0x7b714e25, (q31_t)0x17b7fdbd,
+    (q31_t)0x7b75f53c, (q31_t)0x17ac515f, (q31_t)0x7b7a9a07, (q31_t)0x17a0a417,
+    (q31_t)0x7b7f3c87, (q31_t)0x1794f5e6, (q31_t)0x7b83dcbc, (q31_t)0x178946cc,
+    (q31_t)0x7b887aa6, (q31_t)0x177d96ca, (q31_t)0x7b8d1644, (q31_t)0x1771e5e0,
+    (q31_t)0x7b91af97, (q31_t)0x1766340f, (q31_t)0x7b96469d, (q31_t)0x175a8157,
+    (q31_t)0x7b9adb57, (q31_t)0x174ecdb8, (q31_t)0x7b9f6dc5, (q31_t)0x17431933,
+    (q31_t)0x7ba3fde7, (q31_t)0x173763c9, (q31_t)0x7ba88bbc, (q31_t)0x172bad7a,
+    (q31_t)0x7bad1744, (q31_t)0x171ff646, (q31_t)0x7bb1a080, (q31_t)0x17143e2d,
+    (q31_t)0x7bb6276e, (q31_t)0x17088531, (q31_t)0x7bbaac0e, (q31_t)0x16fccb51,
+    (q31_t)0x7bbf2e62, (q31_t)0x16f1108f, (q31_t)0x7bc3ae67, (q31_t)0x16e554ea,
+    (q31_t)0x7bc82c1f, (q31_t)0x16d99864, (q31_t)0x7bcca789, (q31_t)0x16cddafb,
+    (q31_t)0x7bd120a4, (q31_t)0x16c21cb2, (q31_t)0x7bd59771, (q31_t)0x16b65d88,
+    (q31_t)0x7bda0bf0, (q31_t)0x16aa9d7e, (q31_t)0x7bde7e20, (q31_t)0x169edc94,
+    (q31_t)0x7be2ee01, (q31_t)0x16931acb, (q31_t)0x7be75b93, (q31_t)0x16875823,
+    (q31_t)0x7bebc6d5, (q31_t)0x167b949d, (q31_t)0x7bf02fc9, (q31_t)0x166fd039,
+    (q31_t)0x7bf4966c, (q31_t)0x16640af7, (q31_t)0x7bf8fac0, (q31_t)0x165844d8,
+    (q31_t)0x7bfd5cc4, (q31_t)0x164c7ddd, (q31_t)0x7c01bc78, (q31_t)0x1640b606,
+    (q31_t)0x7c0619dc, (q31_t)0x1634ed53, (q31_t)0x7c0a74f0, (q31_t)0x162923c5,
+    (q31_t)0x7c0ecdb2, (q31_t)0x161d595d, (q31_t)0x7c132424, (q31_t)0x16118e1a,
+    (q31_t)0x7c177845, (q31_t)0x1605c1fd, (q31_t)0x7c1bca16, (q31_t)0x15f9f507,
+    (q31_t)0x7c201994, (q31_t)0x15ee2738, (q31_t)0x7c2466c2, (q31_t)0x15e25890,
+    (q31_t)0x7c28b19e, (q31_t)0x15d68911, (q31_t)0x7c2cfa28, (q31_t)0x15cab8ba,
+    (q31_t)0x7c314060, (q31_t)0x15bee78c, (q31_t)0x7c358446, (q31_t)0x15b31587,
+    (q31_t)0x7c39c5da, (q31_t)0x15a742ac, (q31_t)0x7c3e051b, (q31_t)0x159b6efb,
+    (q31_t)0x7c42420a, (q31_t)0x158f9a76, (q31_t)0x7c467ca6, (q31_t)0x1583c51b,
+    (q31_t)0x7c4ab4ef, (q31_t)0x1577eeec, (q31_t)0x7c4eeae5, (q31_t)0x156c17e9,
+    (q31_t)0x7c531e88, (q31_t)0x15604013, (q31_t)0x7c574fd8, (q31_t)0x1554676a,
+    (q31_t)0x7c5b7ed4, (q31_t)0x15488dee, (q31_t)0x7c5fab7c, (q31_t)0x153cb3a0,
+    (q31_t)0x7c63d5d1, (q31_t)0x1530d881, (q31_t)0x7c67fdd1, (q31_t)0x1524fc90,
+    (q31_t)0x7c6c237e, (q31_t)0x15191fcf, (q31_t)0x7c7046d6, (q31_t)0x150d423d,
+    (q31_t)0x7c7467d9, (q31_t)0x150163dc, (q31_t)0x7c788688, (q31_t)0x14f584ac,
+    (q31_t)0x7c7ca2e2, (q31_t)0x14e9a4ac, (q31_t)0x7c80bce7, (q31_t)0x14ddc3de,
+    (q31_t)0x7c84d496, (q31_t)0x14d1e242, (q31_t)0x7c88e9f1, (q31_t)0x14c5ffd9,
+    (q31_t)0x7c8cfcf6, (q31_t)0x14ba1ca3, (q31_t)0x7c910da5, (q31_t)0x14ae38a0,
+    (q31_t)0x7c951bff, (q31_t)0x14a253d1, (q31_t)0x7c992803, (q31_t)0x14966e36,
+    (q31_t)0x7c9d31b0, (q31_t)0x148a87d1, (q31_t)0x7ca13908, (q31_t)0x147ea0a0,
+    (q31_t)0x7ca53e09, (q31_t)0x1472b8a5, (q31_t)0x7ca940b3, (q31_t)0x1466cfe1,
+    (q31_t)0x7cad4107, (q31_t)0x145ae653, (q31_t)0x7cb13f04, (q31_t)0x144efbfc,
+    (q31_t)0x7cb53aaa, (q31_t)0x144310dd, (q31_t)0x7cb933f9, (q31_t)0x143724f5,
+    (q31_t)0x7cbd2af0, (q31_t)0x142b3846, (q31_t)0x7cc11f90, (q31_t)0x141f4ad1,
+    (q31_t)0x7cc511d9, (q31_t)0x14135c94, (q31_t)0x7cc901c9, (q31_t)0x14076d91,
+    (q31_t)0x7cccef62, (q31_t)0x13fb7dc9, (q31_t)0x7cd0daa2, (q31_t)0x13ef8d3c,
+    (q31_t)0x7cd4c38b, (q31_t)0x13e39be9, (q31_t)0x7cd8aa1b, (q31_t)0x13d7a9d3,
+    (q31_t)0x7cdc8e52, (q31_t)0x13cbb6f8, (q31_t)0x7ce07031, (q31_t)0x13bfc35b,
+    (q31_t)0x7ce44fb7, (q31_t)0x13b3cefa, (q31_t)0x7ce82ce4, (q31_t)0x13a7d9d7,
+    (q31_t)0x7cec07b8, (q31_t)0x139be3f2, (q31_t)0x7cefe032, (q31_t)0x138fed4b,
+    (q31_t)0x7cf3b653, (q31_t)0x1383f5e3, (q31_t)0x7cf78a1b, (q31_t)0x1377fdbb,
+    (q31_t)0x7cfb5b89, (q31_t)0x136c04d2, (q31_t)0x7cff2a9d, (q31_t)0x13600b2a,
+    (q31_t)0x7d02f757, (q31_t)0x135410c3, (q31_t)0x7d06c1b6, (q31_t)0x1348159d,
+    (q31_t)0x7d0a89bc, (q31_t)0x133c19b8, (q31_t)0x7d0e4f67, (q31_t)0x13301d16,
+    (q31_t)0x7d1212b7, (q31_t)0x13241fb6, (q31_t)0x7d15d3ad, (q31_t)0x1318219a,
+    (q31_t)0x7d199248, (q31_t)0x130c22c1, (q31_t)0x7d1d4e88, (q31_t)0x1300232c,
+    (q31_t)0x7d21086c, (q31_t)0x12f422db, (q31_t)0x7d24bff6, (q31_t)0x12e821cf,
+    (q31_t)0x7d287523, (q31_t)0x12dc2009, (q31_t)0x7d2c27f6, (q31_t)0x12d01d89,
+    (q31_t)0x7d2fd86c, (q31_t)0x12c41a4f, (q31_t)0x7d338687, (q31_t)0x12b8165b,
+    (q31_t)0x7d373245, (q31_t)0x12ac11af, (q31_t)0x7d3adba7, (q31_t)0x12a00c4b,
+    (q31_t)0x7d3e82ae, (q31_t)0x1294062f, (q31_t)0x7d422757, (q31_t)0x1287ff5b,
+    (q31_t)0x7d45c9a4, (q31_t)0x127bf7d1, (q31_t)0x7d496994, (q31_t)0x126fef90,
+    (q31_t)0x7d4d0728, (q31_t)0x1263e699, (q31_t)0x7d50a25e, (q31_t)0x1257dced,
+    (q31_t)0x7d543b37, (q31_t)0x124bd28c, (q31_t)0x7d57d1b3, (q31_t)0x123fc776,
+    (q31_t)0x7d5b65d2, (q31_t)0x1233bbac, (q31_t)0x7d5ef793, (q31_t)0x1227af2e,
+    (q31_t)0x7d6286f6, (q31_t)0x121ba1fd, (q31_t)0x7d6613fb, (q31_t)0x120f941a,
+    (q31_t)0x7d699ea3, (q31_t)0x12038584, (q31_t)0x7d6d26ec, (q31_t)0x11f7763c,
+    (q31_t)0x7d70acd7, (q31_t)0x11eb6643, (q31_t)0x7d743064, (q31_t)0x11df5599,
+    (q31_t)0x7d77b192, (q31_t)0x11d3443f, (q31_t)0x7d7b3061, (q31_t)0x11c73235,
+    (q31_t)0x7d7eacd2, (q31_t)0x11bb1f7c, (q31_t)0x7d8226e4, (q31_t)0x11af0c13,
+    (q31_t)0x7d859e96, (q31_t)0x11a2f7fc, (q31_t)0x7d8913ea, (q31_t)0x1196e337,
+    (q31_t)0x7d8c86de, (q31_t)0x118acdc4, (q31_t)0x7d8ff772, (q31_t)0x117eb7a4,
+    (q31_t)0x7d9365a8, (q31_t)0x1172a0d7, (q31_t)0x7d96d17d, (q31_t)0x1166895f,
+    (q31_t)0x7d9a3af2, (q31_t)0x115a713a, (q31_t)0x7d9da208, (q31_t)0x114e586a,
+    (q31_t)0x7da106bd, (q31_t)0x11423ef0, (q31_t)0x7da46912, (q31_t)0x113624cb,
+    (q31_t)0x7da7c907, (q31_t)0x112a09fc, (q31_t)0x7dab269b, (q31_t)0x111dee84,
+    (q31_t)0x7dae81cf, (q31_t)0x1111d263, (q31_t)0x7db1daa2, (q31_t)0x1105b599,
+    (q31_t)0x7db53113, (q31_t)0x10f99827, (q31_t)0x7db88524, (q31_t)0x10ed7a0e,
+    (q31_t)0x7dbbd6d4, (q31_t)0x10e15b4e, (q31_t)0x7dbf2622, (q31_t)0x10d53be7,
+    (q31_t)0x7dc2730f, (q31_t)0x10c91bda, (q31_t)0x7dc5bd9b, (q31_t)0x10bcfb28,
+    (q31_t)0x7dc905c5, (q31_t)0x10b0d9d0, (q31_t)0x7dcc4b8d, (q31_t)0x10a4b7d3,
+    (q31_t)0x7dcf8ef3, (q31_t)0x10989532, (q31_t)0x7dd2cff7, (q31_t)0x108c71ee,
+    (q31_t)0x7dd60e99, (q31_t)0x10804e06, (q31_t)0x7dd94ad8, (q31_t)0x1074297b,
+    (q31_t)0x7ddc84b5, (q31_t)0x1068044e, (q31_t)0x7ddfbc30, (q31_t)0x105bde7f,
+    (q31_t)0x7de2f148, (q31_t)0x104fb80e, (q31_t)0x7de623fd, (q31_t)0x104390fd,
+    (q31_t)0x7de9544f, (q31_t)0x1037694b, (q31_t)0x7dec823e, (q31_t)0x102b40f8,
+    (q31_t)0x7defadca, (q31_t)0x101f1807, (q31_t)0x7df2d6f3, (q31_t)0x1012ee76,
+    (q31_t)0x7df5fdb8, (q31_t)0x1006c446, (q31_t)0x7df9221a, (q31_t)0xffa9979,
+    (q31_t)0x7dfc4418, (q31_t)0xfee6e0d, (q31_t)0x7dff63b2, (q31_t)0xfe24205,
+    (q31_t)0x7e0280e9, (q31_t)0xfd6155f, (q31_t)0x7e059bbb, (q31_t)0xfc9e81e,
+    (q31_t)0x7e08b42a, (q31_t)0xfbdba40, (q31_t)0x7e0bca34, (q31_t)0xfb18bc8,
+    (q31_t)0x7e0eddd9, (q31_t)0xfa55cb4, (q31_t)0x7e11ef1b, (q31_t)0xf992d06,
+    (q31_t)0x7e14fdf7, (q31_t)0xf8cfcbe, (q31_t)0x7e180a6f, (q31_t)0xf80cbdc,
+    (q31_t)0x7e1b1482, (q31_t)0xf749a61, (q31_t)0x7e1e1c30, (q31_t)0xf68684e,
+    (q31_t)0x7e212179, (q31_t)0xf5c35a3, (q31_t)0x7e24245d, (q31_t)0xf500260,
+    (q31_t)0x7e2724db, (q31_t)0xf43ce86, (q31_t)0x7e2a22f4, (q31_t)0xf379a16,
+    (q31_t)0x7e2d1ea8, (q31_t)0xf2b650f, (q31_t)0x7e3017f6, (q31_t)0xf1f2f73,
+    (q31_t)0x7e330ede, (q31_t)0xf12f941, (q31_t)0x7e360360, (q31_t)0xf06c27a,
+    (q31_t)0x7e38f57c, (q31_t)0xefa8b20, (q31_t)0x7e3be532, (q31_t)0xeee5331,
+    (q31_t)0x7e3ed282, (q31_t)0xee21aaf, (q31_t)0x7e41bd6c, (q31_t)0xed5e19a,
+    (q31_t)0x7e44a5ef, (q31_t)0xec9a7f3, (q31_t)0x7e478c0b, (q31_t)0xebd6db9,
+    (q31_t)0x7e4a6fc1, (q31_t)0xeb132ef, (q31_t)0x7e4d5110, (q31_t)0xea4f793,
+    (q31_t)0x7e502ff9, (q31_t)0xe98bba7, (q31_t)0x7e530c7a, (q31_t)0xe8c7f2a,
+    (q31_t)0x7e55e694, (q31_t)0xe80421e, (q31_t)0x7e58be47, (q31_t)0xe740483,
+    (q31_t)0x7e5b9392, (q31_t)0xe67c65a, (q31_t)0x7e5e6676, (q31_t)0xe5b87a2,
+    (q31_t)0x7e6136f3, (q31_t)0xe4f485c, (q31_t)0x7e640507, (q31_t)0xe430889,
+    (q31_t)0x7e66d0b4, (q31_t)0xe36c82a, (q31_t)0x7e6999fa, (q31_t)0xe2a873e,
+    (q31_t)0x7e6c60d7, (q31_t)0xe1e45c6, (q31_t)0x7e6f254c, (q31_t)0xe1203c3,
+    (q31_t)0x7e71e759, (q31_t)0xe05c135, (q31_t)0x7e74a6fd, (q31_t)0xdf97e1d,
+    (q31_t)0x7e77643a, (q31_t)0xded3a7b, (q31_t)0x7e7a1f0d, (q31_t)0xde0f64f,
+    (q31_t)0x7e7cd778, (q31_t)0xdd4b19a, (q31_t)0x7e7f8d7b, (q31_t)0xdc86c5d,
+    (q31_t)0x7e824114, (q31_t)0xdbc2698, (q31_t)0x7e84f245, (q31_t)0xdafe04b,
+    (q31_t)0x7e87a10c, (q31_t)0xda39978, (q31_t)0x7e8a4d6a, (q31_t)0xd97521d,
+    (q31_t)0x7e8cf75f, (q31_t)0xd8b0a3d, (q31_t)0x7e8f9eeb, (q31_t)0xd7ec1d6,
+    (q31_t)0x7e92440d, (q31_t)0xd7278eb, (q31_t)0x7e94e6c6, (q31_t)0xd662f7b,
+    (q31_t)0x7e978715, (q31_t)0xd59e586, (q31_t)0x7e9a24fb, (q31_t)0xd4d9b0e,
+    (q31_t)0x7e9cc076, (q31_t)0xd415013, (q31_t)0x7e9f5988, (q31_t)0xd350495,
+    (q31_t)0x7ea1f02f, (q31_t)0xd28b894, (q31_t)0x7ea4846c, (q31_t)0xd1c6c11,
+    (q31_t)0x7ea7163f, (q31_t)0xd101f0e, (q31_t)0x7ea9a5a8, (q31_t)0xd03d189,
+    (q31_t)0x7eac32a6, (q31_t)0xcf78383, (q31_t)0x7eaebd3a, (q31_t)0xceb34fe,
+    (q31_t)0x7eb14563, (q31_t)0xcdee5f9, (q31_t)0x7eb3cb21, (q31_t)0xcd29676,
+    (q31_t)0x7eb64e75, (q31_t)0xcc64673, (q31_t)0x7eb8cf5d, (q31_t)0xcb9f5f3,
+    (q31_t)0x7ebb4ddb, (q31_t)0xcada4f5, (q31_t)0x7ebdc9ed, (q31_t)0xca1537a,
+    (q31_t)0x7ec04394, (q31_t)0xc950182, (q31_t)0x7ec2bad0, (q31_t)0xc88af0e,
+    (q31_t)0x7ec52fa0, (q31_t)0xc7c5c1e, (q31_t)0x7ec7a205, (q31_t)0xc7008b3,
+    (q31_t)0x7eca11fe, (q31_t)0xc63b4ce, (q31_t)0x7ecc7f8b, (q31_t)0xc57606e,
+    (q31_t)0x7eceeaad, (q31_t)0xc4b0b94, (q31_t)0x7ed15363, (q31_t)0xc3eb641,
+    (q31_t)0x7ed3b9ad, (q31_t)0xc326075, (q31_t)0x7ed61d8a, (q31_t)0xc260a31,
+    (q31_t)0x7ed87efc, (q31_t)0xc19b374, (q31_t)0x7edade01, (q31_t)0xc0d5c41,
+    (q31_t)0x7edd3a9a, (q31_t)0xc010496, (q31_t)0x7edf94c7, (q31_t)0xbf4ac75,
+    (q31_t)0x7ee1ec87, (q31_t)0xbe853de, (q31_t)0x7ee441da, (q31_t)0xbdbfad1,
+    (q31_t)0x7ee694c1, (q31_t)0xbcfa150, (q31_t)0x7ee8e53a, (q31_t)0xbc34759,
+    (q31_t)0x7eeb3347, (q31_t)0xbb6ecef, (q31_t)0x7eed7ee7, (q31_t)0xbaa9211,
+    (q31_t)0x7eefc81a, (q31_t)0xb9e36c0, (q31_t)0x7ef20ee0, (q31_t)0xb91dafc,
+    (q31_t)0x7ef45338, (q31_t)0xb857ec7, (q31_t)0x7ef69523, (q31_t)0xb79221f,
+    (q31_t)0x7ef8d4a1, (q31_t)0xb6cc506, (q31_t)0x7efb11b1, (q31_t)0xb60677c,
+    (q31_t)0x7efd4c54, (q31_t)0xb540982, (q31_t)0x7eff8489, (q31_t)0xb47ab19,
+    (q31_t)0x7f01ba50, (q31_t)0xb3b4c40, (q31_t)0x7f03eda9, (q31_t)0xb2eecf8,
+    (q31_t)0x7f061e95, (q31_t)0xb228d42, (q31_t)0x7f084d12, (q31_t)0xb162d1d,
+    (q31_t)0x7f0a7921, (q31_t)0xb09cc8c, (q31_t)0x7f0ca2c2, (q31_t)0xafd6b8d,
+    (q31_t)0x7f0ec9f5, (q31_t)0xaf10a22, (q31_t)0x7f10eeb9, (q31_t)0xae4a84b,
+    (q31_t)0x7f13110f, (q31_t)0xad84609, (q31_t)0x7f1530f7, (q31_t)0xacbe35b,
+    (q31_t)0x7f174e70, (q31_t)0xabf8043, (q31_t)0x7f19697a, (q31_t)0xab31cc1,
+    (q31_t)0x7f1b8215, (q31_t)0xaa6b8d5, (q31_t)0x7f1d9842, (q31_t)0xa9a5480,
+    (q31_t)0x7f1fabff, (q31_t)0xa8defc3, (q31_t)0x7f21bd4e, (q31_t)0xa818a9d,
+    (q31_t)0x7f23cc2e, (q31_t)0xa752510, (q31_t)0x7f25d89e, (q31_t)0xa68bf1b,
+    (q31_t)0x7f27e29f, (q31_t)0xa5c58c0, (q31_t)0x7f29ea31, (q31_t)0xa4ff1fe,
+    (q31_t)0x7f2bef53, (q31_t)0xa438ad7, (q31_t)0x7f2df206, (q31_t)0xa37234a,
+    (q31_t)0x7f2ff24a, (q31_t)0xa2abb59, (q31_t)0x7f31f01d, (q31_t)0xa1e5303,
+    (q31_t)0x7f33eb81, (q31_t)0xa11ea49, (q31_t)0x7f35e476, (q31_t)0xa05812c,
+    (q31_t)0x7f37dafa, (q31_t)0x9f917ac, (q31_t)0x7f39cf0e, (q31_t)0x9ecadc9,
+    (q31_t)0x7f3bc0b3, (q31_t)0x9e04385, (q31_t)0x7f3dafe7, (q31_t)0x9d3d8df,
+    (q31_t)0x7f3f9cab, (q31_t)0x9c76dd8, (q31_t)0x7f4186ff, (q31_t)0x9bb0271,
+    (q31_t)0x7f436ee3, (q31_t)0x9ae96aa, (q31_t)0x7f455456, (q31_t)0x9a22a83,
+    (q31_t)0x7f473759, (q31_t)0x995bdfd, (q31_t)0x7f4917eb, (q31_t)0x9895118,
+    (q31_t)0x7f4af60d, (q31_t)0x97ce3d5, (q31_t)0x7f4cd1be, (q31_t)0x9707635,
+    (q31_t)0x7f4eaafe, (q31_t)0x9640837, (q31_t)0x7f5081cd, (q31_t)0x95799dd,
+    (q31_t)0x7f52562c, (q31_t)0x94b2b27, (q31_t)0x7f54281a, (q31_t)0x93ebc14,
+    (q31_t)0x7f55f796, (q31_t)0x9324ca7, (q31_t)0x7f57c4a2, (q31_t)0x925dcdf,
+    (q31_t)0x7f598f3c, (q31_t)0x9196cbc, (q31_t)0x7f5b5765, (q31_t)0x90cfc40,
+    (q31_t)0x7f5d1d1d, (q31_t)0x9008b6a, (q31_t)0x7f5ee063, (q31_t)0x8f41a3c,
+    (q31_t)0x7f60a138, (q31_t)0x8e7a8b5, (q31_t)0x7f625f9b, (q31_t)0x8db36d6,
+    (q31_t)0x7f641b8d, (q31_t)0x8cec4a0, (q31_t)0x7f65d50d, (q31_t)0x8c25213,
+    (q31_t)0x7f678c1c, (q31_t)0x8b5df30, (q31_t)0x7f6940b8, (q31_t)0x8a96bf6,
+    (q31_t)0x7f6af2e3, (q31_t)0x89cf867, (q31_t)0x7f6ca29c, (q31_t)0x8908483,
+    (q31_t)0x7f6e4fe3, (q31_t)0x884104b, (q31_t)0x7f6ffab8, (q31_t)0x8779bbe,
+    (q31_t)0x7f71a31b, (q31_t)0x86b26de, (q31_t)0x7f73490b, (q31_t)0x85eb1ab,
+    (q31_t)0x7f74ec8a, (q31_t)0x8523c25, (q31_t)0x7f768d96, (q31_t)0x845c64d,
+    (q31_t)0x7f782c30, (q31_t)0x8395024, (q31_t)0x7f79c857, (q31_t)0x82cd9a9,
+    (q31_t)0x7f7b620c, (q31_t)0x82062de, (q31_t)0x7f7cf94e, (q31_t)0x813ebc2,
+    (q31_t)0x7f7e8e1e, (q31_t)0x8077457, (q31_t)0x7f80207b, (q31_t)0x7fafc9c,
+    (q31_t)0x7f81b065, (q31_t)0x7ee8493, (q31_t)0x7f833ddd, (q31_t)0x7e20c3b,
+    (q31_t)0x7f84c8e2, (q31_t)0x7d59396, (q31_t)0x7f865174, (q31_t)0x7c91aa3,
+    (q31_t)0x7f87d792, (q31_t)0x7bca163, (q31_t)0x7f895b3e, (q31_t)0x7b027d7,
+    (q31_t)0x7f8adc77, (q31_t)0x7a3adff, (q31_t)0x7f8c5b3d, (q31_t)0x79733dc,
+    (q31_t)0x7f8dd78f, (q31_t)0x78ab96e, (q31_t)0x7f8f516e, (q31_t)0x77e3eb5,
+    (q31_t)0x7f90c8da, (q31_t)0x771c3b3, (q31_t)0x7f923dd2, (q31_t)0x7654867,
+    (q31_t)0x7f93b058, (q31_t)0x758ccd2, (q31_t)0x7f952069, (q31_t)0x74c50f4,
+    (q31_t)0x7f968e07, (q31_t)0x73fd4cf, (q31_t)0x7f97f932, (q31_t)0x7335862,
+    (q31_t)0x7f9961e8, (q31_t)0x726dbae, (q31_t)0x7f9ac82c, (q31_t)0x71a5eb3,
+    (q31_t)0x7f9c2bfb, (q31_t)0x70de172, (q31_t)0x7f9d8d56, (q31_t)0x70163eb,
+    (q31_t)0x7f9eec3e, (q31_t)0x6f4e620, (q31_t)0x7fa048b2, (q31_t)0x6e86810,
+    (q31_t)0x7fa1a2b2, (q31_t)0x6dbe9bb, (q31_t)0x7fa2fa3d, (q31_t)0x6cf6b23,
+    (q31_t)0x7fa44f55, (q31_t)0x6c2ec48, (q31_t)0x7fa5a1f9, (q31_t)0x6b66d29,
+    (q31_t)0x7fa6f228, (q31_t)0x6a9edc9, (q31_t)0x7fa83fe3, (q31_t)0x69d6e27,
+    (q31_t)0x7fa98b2a, (q31_t)0x690ee44, (q31_t)0x7faad3fd, (q31_t)0x6846e1f,
+    (q31_t)0x7fac1a5b, (q31_t)0x677edbb, (q31_t)0x7fad5e45, (q31_t)0x66b6d16,
+    (q31_t)0x7fae9fbb, (q31_t)0x65eec33, (q31_t)0x7fafdebb, (q31_t)0x6526b10,
+    (q31_t)0x7fb11b48, (q31_t)0x645e9af, (q31_t)0x7fb2555f, (q31_t)0x6396810,
+    (q31_t)0x7fb38d02, (q31_t)0x62ce634, (q31_t)0x7fb4c231, (q31_t)0x620641a,
+    (q31_t)0x7fb5f4ea, (q31_t)0x613e1c5, (q31_t)0x7fb7252f, (q31_t)0x6075f33,
+    (q31_t)0x7fb852ff, (q31_t)0x5fadc66, (q31_t)0x7fb97e5a, (q31_t)0x5ee595d,
+    (q31_t)0x7fbaa740, (q31_t)0x5e1d61b, (q31_t)0x7fbbcdb1, (q31_t)0x5d5529e,
+    (q31_t)0x7fbcf1ad, (q31_t)0x5c8cee7, (q31_t)0x7fbe1334, (q31_t)0x5bc4af8,
+    (q31_t)0x7fbf3246, (q31_t)0x5afc6d0, (q31_t)0x7fc04ee3, (q31_t)0x5a3426f,
+    (q31_t)0x7fc1690a, (q31_t)0x596bdd7, (q31_t)0x7fc280bc, (q31_t)0x58a3908,
+    (q31_t)0x7fc395f9, (q31_t)0x57db403, (q31_t)0x7fc4a8c1, (q31_t)0x5712ec7,
+    (q31_t)0x7fc5b913, (q31_t)0x564a955, (q31_t)0x7fc6c6f0, (q31_t)0x55823ae,
+    (q31_t)0x7fc7d258, (q31_t)0x54b9dd3, (q31_t)0x7fc8db4a, (q31_t)0x53f17c3,
+    (q31_t)0x7fc9e1c6, (q31_t)0x532917f, (q31_t)0x7fcae5cd, (q31_t)0x5260b08,
+    (q31_t)0x7fcbe75e, (q31_t)0x519845e, (q31_t)0x7fcce67a, (q31_t)0x50cfd82,
+    (q31_t)0x7fcde320, (q31_t)0x5007674, (q31_t)0x7fcedd50, (q31_t)0x4f3ef35,
+    (q31_t)0x7fcfd50b, (q31_t)0x4e767c5, (q31_t)0x7fd0ca4f, (q31_t)0x4dae024,
+    (q31_t)0x7fd1bd1e, (q31_t)0x4ce5854, (q31_t)0x7fd2ad77, (q31_t)0x4c1d054,
+    (q31_t)0x7fd39b5a, (q31_t)0x4b54825, (q31_t)0x7fd486c7, (q31_t)0x4a8bfc7,
+    (q31_t)0x7fd56fbe, (q31_t)0x49c373c, (q31_t)0x7fd6563f, (q31_t)0x48fae83,
+    (q31_t)0x7fd73a4a, (q31_t)0x483259d, (q31_t)0x7fd81bdf, (q31_t)0x4769c8b,
+    (q31_t)0x7fd8fafe, (q31_t)0x46a134c, (q31_t)0x7fd9d7a7, (q31_t)0x45d89e2,
+    (q31_t)0x7fdab1d9, (q31_t)0x451004d, (q31_t)0x7fdb8996, (q31_t)0x444768d,
+    (q31_t)0x7fdc5edc, (q31_t)0x437eca4, (q31_t)0x7fdd31ac, (q31_t)0x42b6290,
+    (q31_t)0x7fde0205, (q31_t)0x41ed854, (q31_t)0x7fdecfe8, (q31_t)0x4124dee,
+    (q31_t)0x7fdf9b55, (q31_t)0x405c361, (q31_t)0x7fe0644b, (q31_t)0x3f938ac,
+    (q31_t)0x7fe12acb, (q31_t)0x3ecadcf, (q31_t)0x7fe1eed5, (q31_t)0x3e022cc,
+    (q31_t)0x7fe2b067, (q31_t)0x3d397a3, (q31_t)0x7fe36f84, (q31_t)0x3c70c54,
+    (q31_t)0x7fe42c2a, (q31_t)0x3ba80df, (q31_t)0x7fe4e659, (q31_t)0x3adf546,
+    (q31_t)0x7fe59e12, (q31_t)0x3a16988, (q31_t)0x7fe65354, (q31_t)0x394dda7,
+    (q31_t)0x7fe7061f, (q31_t)0x38851a2, (q31_t)0x7fe7b674, (q31_t)0x37bc57b,
+    (q31_t)0x7fe86452, (q31_t)0x36f3931, (q31_t)0x7fe90fb9, (q31_t)0x362acc5,
+    (q31_t)0x7fe9b8a9, (q31_t)0x3562038, (q31_t)0x7fea5f23, (q31_t)0x3499389,
+    (q31_t)0x7feb0326, (q31_t)0x33d06bb, (q31_t)0x7feba4b2, (q31_t)0x33079cc,
+    (q31_t)0x7fec43c7, (q31_t)0x323ecbe, (q31_t)0x7fece065, (q31_t)0x3175f91,
+    (q31_t)0x7fed7a8c, (q31_t)0x30ad245, (q31_t)0x7fee123d, (q31_t)0x2fe44dc,
+    (q31_t)0x7feea776, (q31_t)0x2f1b755, (q31_t)0x7fef3a39, (q31_t)0x2e529b0,
+    (q31_t)0x7fefca84, (q31_t)0x2d89bf0, (q31_t)0x7ff05858, (q31_t)0x2cc0e13,
+    (q31_t)0x7ff0e3b6, (q31_t)0x2bf801a, (q31_t)0x7ff16c9c, (q31_t)0x2b2f207,
+    (q31_t)0x7ff1f30b, (q31_t)0x2a663d8, (q31_t)0x7ff27703, (q31_t)0x299d590,
+    (q31_t)0x7ff2f884, (q31_t)0x28d472e, (q31_t)0x7ff3778e, (q31_t)0x280b8b3,
+    (q31_t)0x7ff3f420, (q31_t)0x2742a1f, (q31_t)0x7ff46e3c, (q31_t)0x2679b73,
+    (q31_t)0x7ff4e5e0, (q31_t)0x25b0caf, (q31_t)0x7ff55b0d, (q31_t)0x24e7dd4,
+    (q31_t)0x7ff5cdc3, (q31_t)0x241eee2, (q31_t)0x7ff63e01, (q31_t)0x2355fd9,
+    (q31_t)0x7ff6abc8, (q31_t)0x228d0bb, (q31_t)0x7ff71718, (q31_t)0x21c4188,
+    (q31_t)0x7ff77ff1, (q31_t)0x20fb240, (q31_t)0x7ff7e652, (q31_t)0x20322e3,
+    (q31_t)0x7ff84a3c, (q31_t)0x1f69373, (q31_t)0x7ff8abae, (q31_t)0x1ea03ef,
+    (q31_t)0x7ff90aaa, (q31_t)0x1dd7459, (q31_t)0x7ff9672d, (q31_t)0x1d0e4b0,
+    (q31_t)0x7ff9c13a, (q31_t)0x1c454f5, (q31_t)0x7ffa18cf, (q31_t)0x1b7c528,
+    (q31_t)0x7ffa6dec, (q31_t)0x1ab354b, (q31_t)0x7ffac092, (q31_t)0x19ea55d,
+    (q31_t)0x7ffb10c1, (q31_t)0x192155f, (q31_t)0x7ffb5e78, (q31_t)0x1858552,
+    (q31_t)0x7ffba9b8, (q31_t)0x178f536, (q31_t)0x7ffbf280, (q31_t)0x16c650b,
+    (q31_t)0x7ffc38d1, (q31_t)0x15fd4d2, (q31_t)0x7ffc7caa, (q31_t)0x153448c,
+    (q31_t)0x7ffcbe0c, (q31_t)0x146b438, (q31_t)0x7ffcfcf6, (q31_t)0x13a23d8,
+    (q31_t)0x7ffd3969, (q31_t)0x12d936c, (q31_t)0x7ffd7364, (q31_t)0x12102f4,
+    (q31_t)0x7ffdaae7, (q31_t)0x1147271, (q31_t)0x7ffddff3, (q31_t)0x107e1e3,
+    (q31_t)0x7ffe1288, (q31_t)0xfb514b, (q31_t)0x7ffe42a4, (q31_t)0xeec0aa,
+    (q31_t)0x7ffe704a, (q31_t)0xe22fff, (q31_t)0x7ffe9b77, (q31_t)0xd59f4c,
+    (q31_t)0x7ffec42d, (q31_t)0xc90e90, (q31_t)0x7ffeea6c, (q31_t)0xbc7dcc,
+    (q31_t)0x7fff0e32, (q31_t)0xafed02, (q31_t)0x7fff2f82, (q31_t)0xa35c30,
+    (q31_t)0x7fff4e59, (q31_t)0x96cb58, (q31_t)0x7fff6ab9, (q31_t)0x8a3a7b,
+    (q31_t)0x7fff84a1, (q31_t)0x7da998, (q31_t)0x7fff9c12, (q31_t)0x7118b0,
+    (q31_t)0x7fffb10b, (q31_t)0x6487c4, (q31_t)0x7fffc38c, (q31_t)0x57f6d4,
+    (q31_t)0x7fffd396, (q31_t)0x4b65e1, (q31_t)0x7fffe128, (q31_t)0x3ed4ea,
+    (q31_t)0x7fffec43, (q31_t)0x3243f1, (q31_t)0x7ffff4e6, (q31_t)0x25b2f7,
+    (q31_t)0x7ffffb11, (q31_t)0x1921fb, (q31_t)0x7ffffec4, (q31_t)0xc90fe,
+    (q31_t)0x7fffffff, (q31_t)0x0, (q31_t)0x7ffffec4, (q31_t)0xfff36f02,
+    (q31_t)0x7ffffb11, (q31_t)0xffe6de05, (q31_t)0x7ffff4e6, (q31_t)0xffda4d09,
+    (q31_t)0x7fffec43, (q31_t)0xffcdbc0f, (q31_t)0x7fffe128, (q31_t)0xffc12b16,
+    (q31_t)0x7fffd396, (q31_t)0xffb49a1f, (q31_t)0x7fffc38c, (q31_t)0xffa8092c,
+    (q31_t)0x7fffb10b, (q31_t)0xff9b783c, (q31_t)0x7fff9c12, (q31_t)0xff8ee750,
+    (q31_t)0x7fff84a1, (q31_t)0xff825668, (q31_t)0x7fff6ab9, (q31_t)0xff75c585,
+    (q31_t)0x7fff4e59, (q31_t)0xff6934a8, (q31_t)0x7fff2f82, (q31_t)0xff5ca3d0,
+    (q31_t)0x7fff0e32, (q31_t)0xff5012fe, (q31_t)0x7ffeea6c, (q31_t)0xff438234,
+    (q31_t)0x7ffec42d, (q31_t)0xff36f170, (q31_t)0x7ffe9b77, (q31_t)0xff2a60b4,
+    (q31_t)0x7ffe704a, (q31_t)0xff1dd001, (q31_t)0x7ffe42a4, (q31_t)0xff113f56,
+    (q31_t)0x7ffe1288, (q31_t)0xff04aeb5, (q31_t)0x7ffddff3, (q31_t)0xfef81e1d,
+    (q31_t)0x7ffdaae7, (q31_t)0xfeeb8d8f, (q31_t)0x7ffd7364, (q31_t)0xfedefd0c,
+    (q31_t)0x7ffd3969, (q31_t)0xfed26c94, (q31_t)0x7ffcfcf6, (q31_t)0xfec5dc28,
+    (q31_t)0x7ffcbe0c, (q31_t)0xfeb94bc8, (q31_t)0x7ffc7caa, (q31_t)0xfeacbb74,
+    (q31_t)0x7ffc38d1, (q31_t)0xfea02b2e, (q31_t)0x7ffbf280, (q31_t)0xfe939af5,
+    (q31_t)0x7ffba9b8, (q31_t)0xfe870aca, (q31_t)0x7ffb5e78, (q31_t)0xfe7a7aae,
+    (q31_t)0x7ffb10c1, (q31_t)0xfe6deaa1, (q31_t)0x7ffac092, (q31_t)0xfe615aa3,
+    (q31_t)0x7ffa6dec, (q31_t)0xfe54cab5, (q31_t)0x7ffa18cf, (q31_t)0xfe483ad8,
+    (q31_t)0x7ff9c13a, (q31_t)0xfe3bab0b, (q31_t)0x7ff9672d, (q31_t)0xfe2f1b50,
+    (q31_t)0x7ff90aaa, (q31_t)0xfe228ba7, (q31_t)0x7ff8abae, (q31_t)0xfe15fc11,
+    (q31_t)0x7ff84a3c, (q31_t)0xfe096c8d, (q31_t)0x7ff7e652, (q31_t)0xfdfcdd1d,
+    (q31_t)0x7ff77ff1, (q31_t)0xfdf04dc0, (q31_t)0x7ff71718, (q31_t)0xfde3be78,
+    (q31_t)0x7ff6abc8, (q31_t)0xfdd72f45, (q31_t)0x7ff63e01, (q31_t)0xfdcaa027,
+    (q31_t)0x7ff5cdc3, (q31_t)0xfdbe111e, (q31_t)0x7ff55b0d, (q31_t)0xfdb1822c,
+    (q31_t)0x7ff4e5e0, (q31_t)0xfda4f351, (q31_t)0x7ff46e3c, (q31_t)0xfd98648d,
+    (q31_t)0x7ff3f420, (q31_t)0xfd8bd5e1, (q31_t)0x7ff3778e, (q31_t)0xfd7f474d,
+    (q31_t)0x7ff2f884, (q31_t)0xfd72b8d2, (q31_t)0x7ff27703, (q31_t)0xfd662a70,
+    (q31_t)0x7ff1f30b, (q31_t)0xfd599c28, (q31_t)0x7ff16c9c, (q31_t)0xfd4d0df9,
+    (q31_t)0x7ff0e3b6, (q31_t)0xfd407fe6, (q31_t)0x7ff05858, (q31_t)0xfd33f1ed,
+    (q31_t)0x7fefca84, (q31_t)0xfd276410, (q31_t)0x7fef3a39, (q31_t)0xfd1ad650,
+    (q31_t)0x7feea776, (q31_t)0xfd0e48ab, (q31_t)0x7fee123d, (q31_t)0xfd01bb24,
+    (q31_t)0x7fed7a8c, (q31_t)0xfcf52dbb, (q31_t)0x7fece065, (q31_t)0xfce8a06f,
+    (q31_t)0x7fec43c7, (q31_t)0xfcdc1342, (q31_t)0x7feba4b2, (q31_t)0xfccf8634,
+    (q31_t)0x7feb0326, (q31_t)0xfcc2f945, (q31_t)0x7fea5f23, (q31_t)0xfcb66c77,
+    (q31_t)0x7fe9b8a9, (q31_t)0xfca9dfc8, (q31_t)0x7fe90fb9, (q31_t)0xfc9d533b,
+    (q31_t)0x7fe86452, (q31_t)0xfc90c6cf, (q31_t)0x7fe7b674, (q31_t)0xfc843a85,
+    (q31_t)0x7fe7061f, (q31_t)0xfc77ae5e, (q31_t)0x7fe65354, (q31_t)0xfc6b2259,
+    (q31_t)0x7fe59e12, (q31_t)0xfc5e9678, (q31_t)0x7fe4e659, (q31_t)0xfc520aba,
+    (q31_t)0x7fe42c2a, (q31_t)0xfc457f21, (q31_t)0x7fe36f84, (q31_t)0xfc38f3ac,
+    (q31_t)0x7fe2b067, (q31_t)0xfc2c685d, (q31_t)0x7fe1eed5, (q31_t)0xfc1fdd34,
+    (q31_t)0x7fe12acb, (q31_t)0xfc135231, (q31_t)0x7fe0644b, (q31_t)0xfc06c754,
+    (q31_t)0x7fdf9b55, (q31_t)0xfbfa3c9f, (q31_t)0x7fdecfe8, (q31_t)0xfbedb212,
+    (q31_t)0x7fde0205, (q31_t)0xfbe127ac, (q31_t)0x7fdd31ac, (q31_t)0xfbd49d70,
+    (q31_t)0x7fdc5edc, (q31_t)0xfbc8135c, (q31_t)0x7fdb8996, (q31_t)0xfbbb8973,
+    (q31_t)0x7fdab1d9, (q31_t)0xfbaeffb3, (q31_t)0x7fd9d7a7, (q31_t)0xfba2761e,
+    (q31_t)0x7fd8fafe, (q31_t)0xfb95ecb4, (q31_t)0x7fd81bdf, (q31_t)0xfb896375,
+    (q31_t)0x7fd73a4a, (q31_t)0xfb7cda63, (q31_t)0x7fd6563f, (q31_t)0xfb70517d,
+    (q31_t)0x7fd56fbe, (q31_t)0xfb63c8c4, (q31_t)0x7fd486c7, (q31_t)0xfb574039,
+    (q31_t)0x7fd39b5a, (q31_t)0xfb4ab7db, (q31_t)0x7fd2ad77, (q31_t)0xfb3e2fac,
+    (q31_t)0x7fd1bd1e, (q31_t)0xfb31a7ac, (q31_t)0x7fd0ca4f, (q31_t)0xfb251fdc,
+    (q31_t)0x7fcfd50b, (q31_t)0xfb18983b, (q31_t)0x7fcedd50, (q31_t)0xfb0c10cb,
+    (q31_t)0x7fcde320, (q31_t)0xfaff898c, (q31_t)0x7fcce67a, (q31_t)0xfaf3027e,
+    (q31_t)0x7fcbe75e, (q31_t)0xfae67ba2, (q31_t)0x7fcae5cd, (q31_t)0xfad9f4f8,
+    (q31_t)0x7fc9e1c6, (q31_t)0xfacd6e81, (q31_t)0x7fc8db4a, (q31_t)0xfac0e83d,
+    (q31_t)0x7fc7d258, (q31_t)0xfab4622d, (q31_t)0x7fc6c6f0, (q31_t)0xfaa7dc52,
+    (q31_t)0x7fc5b913, (q31_t)0xfa9b56ab, (q31_t)0x7fc4a8c1, (q31_t)0xfa8ed139,
+    (q31_t)0x7fc395f9, (q31_t)0xfa824bfd, (q31_t)0x7fc280bc, (q31_t)0xfa75c6f8,
+    (q31_t)0x7fc1690a, (q31_t)0xfa694229, (q31_t)0x7fc04ee3, (q31_t)0xfa5cbd91,
+    (q31_t)0x7fbf3246, (q31_t)0xfa503930, (q31_t)0x7fbe1334, (q31_t)0xfa43b508,
+    (q31_t)0x7fbcf1ad, (q31_t)0xfa373119, (q31_t)0x7fbbcdb1, (q31_t)0xfa2aad62,
+    (q31_t)0x7fbaa740, (q31_t)0xfa1e29e5, (q31_t)0x7fb97e5a, (q31_t)0xfa11a6a3,
+    (q31_t)0x7fb852ff, (q31_t)0xfa05239a, (q31_t)0x7fb7252f, (q31_t)0xf9f8a0cd,
+    (q31_t)0x7fb5f4ea, (q31_t)0xf9ec1e3b, (q31_t)0x7fb4c231, (q31_t)0xf9df9be6,
+    (q31_t)0x7fb38d02, (q31_t)0xf9d319cc, (q31_t)0x7fb2555f, (q31_t)0xf9c697f0,
+    (q31_t)0x7fb11b48, (q31_t)0xf9ba1651, (q31_t)0x7fafdebb, (q31_t)0xf9ad94f0,
+    (q31_t)0x7fae9fbb, (q31_t)0xf9a113cd, (q31_t)0x7fad5e45, (q31_t)0xf99492ea,
+    (q31_t)0x7fac1a5b, (q31_t)0xf9881245, (q31_t)0x7faad3fd, (q31_t)0xf97b91e1,
+    (q31_t)0x7fa98b2a, (q31_t)0xf96f11bc, (q31_t)0x7fa83fe3, (q31_t)0xf96291d9,
+    (q31_t)0x7fa6f228, (q31_t)0xf9561237, (q31_t)0x7fa5a1f9, (q31_t)0xf94992d7,
+    (q31_t)0x7fa44f55, (q31_t)0xf93d13b8, (q31_t)0x7fa2fa3d, (q31_t)0xf93094dd,
+    (q31_t)0x7fa1a2b2, (q31_t)0xf9241645, (q31_t)0x7fa048b2, (q31_t)0xf91797f0,
+    (q31_t)0x7f9eec3e, (q31_t)0xf90b19e0, (q31_t)0x7f9d8d56, (q31_t)0xf8fe9c15,
+    (q31_t)0x7f9c2bfb, (q31_t)0xf8f21e8e, (q31_t)0x7f9ac82c, (q31_t)0xf8e5a14d,
+    (q31_t)0x7f9961e8, (q31_t)0xf8d92452, (q31_t)0x7f97f932, (q31_t)0xf8cca79e,
+    (q31_t)0x7f968e07, (q31_t)0xf8c02b31, (q31_t)0x7f952069, (q31_t)0xf8b3af0c,
+    (q31_t)0x7f93b058, (q31_t)0xf8a7332e, (q31_t)0x7f923dd2, (q31_t)0xf89ab799,
+    (q31_t)0x7f90c8da, (q31_t)0xf88e3c4d, (q31_t)0x7f8f516e, (q31_t)0xf881c14b,
+    (q31_t)0x7f8dd78f, (q31_t)0xf8754692, (q31_t)0x7f8c5b3d, (q31_t)0xf868cc24,
+    (q31_t)0x7f8adc77, (q31_t)0xf85c5201, (q31_t)0x7f895b3e, (q31_t)0xf84fd829,
+    (q31_t)0x7f87d792, (q31_t)0xf8435e9d, (q31_t)0x7f865174, (q31_t)0xf836e55d,
+    (q31_t)0x7f84c8e2, (q31_t)0xf82a6c6a, (q31_t)0x7f833ddd, (q31_t)0xf81df3c5,
+    (q31_t)0x7f81b065, (q31_t)0xf8117b6d, (q31_t)0x7f80207b, (q31_t)0xf8050364,
+    (q31_t)0x7f7e8e1e, (q31_t)0xf7f88ba9, (q31_t)0x7f7cf94e, (q31_t)0xf7ec143e,
+    (q31_t)0x7f7b620c, (q31_t)0xf7df9d22, (q31_t)0x7f79c857, (q31_t)0xf7d32657,
+    (q31_t)0x7f782c30, (q31_t)0xf7c6afdc, (q31_t)0x7f768d96, (q31_t)0xf7ba39b3,
+    (q31_t)0x7f74ec8a, (q31_t)0xf7adc3db, (q31_t)0x7f73490b, (q31_t)0xf7a14e55,
+    (q31_t)0x7f71a31b, (q31_t)0xf794d922, (q31_t)0x7f6ffab8, (q31_t)0xf7886442,
+    (q31_t)0x7f6e4fe3, (q31_t)0xf77befb5, (q31_t)0x7f6ca29c, (q31_t)0xf76f7b7d,
+    (q31_t)0x7f6af2e3, (q31_t)0xf7630799, (q31_t)0x7f6940b8, (q31_t)0xf756940a,
+    (q31_t)0x7f678c1c, (q31_t)0xf74a20d0, (q31_t)0x7f65d50d, (q31_t)0xf73daded,
+    (q31_t)0x7f641b8d, (q31_t)0xf7313b60, (q31_t)0x7f625f9b, (q31_t)0xf724c92a,
+    (q31_t)0x7f60a138, (q31_t)0xf718574b, (q31_t)0x7f5ee063, (q31_t)0xf70be5c4,
+    (q31_t)0x7f5d1d1d, (q31_t)0xf6ff7496, (q31_t)0x7f5b5765, (q31_t)0xf6f303c0,
+    (q31_t)0x7f598f3c, (q31_t)0xf6e69344, (q31_t)0x7f57c4a2, (q31_t)0xf6da2321,
+    (q31_t)0x7f55f796, (q31_t)0xf6cdb359, (q31_t)0x7f54281a, (q31_t)0xf6c143ec,
+    (q31_t)0x7f52562c, (q31_t)0xf6b4d4d9, (q31_t)0x7f5081cd, (q31_t)0xf6a86623,
+    (q31_t)0x7f4eaafe, (q31_t)0xf69bf7c9, (q31_t)0x7f4cd1be, (q31_t)0xf68f89cb,
+    (q31_t)0x7f4af60d, (q31_t)0xf6831c2b, (q31_t)0x7f4917eb, (q31_t)0xf676aee8,
+    (q31_t)0x7f473759, (q31_t)0xf66a4203, (q31_t)0x7f455456, (q31_t)0xf65dd57d,
+    (q31_t)0x7f436ee3, (q31_t)0xf6516956, (q31_t)0x7f4186ff, (q31_t)0xf644fd8f,
+    (q31_t)0x7f3f9cab, (q31_t)0xf6389228, (q31_t)0x7f3dafe7, (q31_t)0xf62c2721,
+    (q31_t)0x7f3bc0b3, (q31_t)0xf61fbc7b, (q31_t)0x7f39cf0e, (q31_t)0xf6135237,
+    (q31_t)0x7f37dafa, (q31_t)0xf606e854, (q31_t)0x7f35e476, (q31_t)0xf5fa7ed4,
+    (q31_t)0x7f33eb81, (q31_t)0xf5ee15b7, (q31_t)0x7f31f01d, (q31_t)0xf5e1acfd,
+    (q31_t)0x7f2ff24a, (q31_t)0xf5d544a7, (q31_t)0x7f2df206, (q31_t)0xf5c8dcb6,
+    (q31_t)0x7f2bef53, (q31_t)0xf5bc7529, (q31_t)0x7f29ea31, (q31_t)0xf5b00e02,
+    (q31_t)0x7f27e29f, (q31_t)0xf5a3a740, (q31_t)0x7f25d89e, (q31_t)0xf59740e5,
+    (q31_t)0x7f23cc2e, (q31_t)0xf58adaf0, (q31_t)0x7f21bd4e, (q31_t)0xf57e7563,
+    (q31_t)0x7f1fabff, (q31_t)0xf572103d, (q31_t)0x7f1d9842, (q31_t)0xf565ab80,
+    (q31_t)0x7f1b8215, (q31_t)0xf559472b, (q31_t)0x7f19697a, (q31_t)0xf54ce33f,
+    (q31_t)0x7f174e70, (q31_t)0xf5407fbd, (q31_t)0x7f1530f7, (q31_t)0xf5341ca5,
+    (q31_t)0x7f13110f, (q31_t)0xf527b9f7, (q31_t)0x7f10eeb9, (q31_t)0xf51b57b5,
+    (q31_t)0x7f0ec9f5, (q31_t)0xf50ef5de, (q31_t)0x7f0ca2c2, (q31_t)0xf5029473,
+    (q31_t)0x7f0a7921, (q31_t)0xf4f63374, (q31_t)0x7f084d12, (q31_t)0xf4e9d2e3,
+    (q31_t)0x7f061e95, (q31_t)0xf4dd72be, (q31_t)0x7f03eda9, (q31_t)0xf4d11308,
+    (q31_t)0x7f01ba50, (q31_t)0xf4c4b3c0, (q31_t)0x7eff8489, (q31_t)0xf4b854e7,
+    (q31_t)0x7efd4c54, (q31_t)0xf4abf67e, (q31_t)0x7efb11b1, (q31_t)0xf49f9884,
+    (q31_t)0x7ef8d4a1, (q31_t)0xf4933afa, (q31_t)0x7ef69523, (q31_t)0xf486dde1,
+    (q31_t)0x7ef45338, (q31_t)0xf47a8139, (q31_t)0x7ef20ee0, (q31_t)0xf46e2504,
+    (q31_t)0x7eefc81a, (q31_t)0xf461c940, (q31_t)0x7eed7ee7, (q31_t)0xf4556def,
+    (q31_t)0x7eeb3347, (q31_t)0xf4491311, (q31_t)0x7ee8e53a, (q31_t)0xf43cb8a7,
+    (q31_t)0x7ee694c1, (q31_t)0xf4305eb0, (q31_t)0x7ee441da, (q31_t)0xf424052f,
+    (q31_t)0x7ee1ec87, (q31_t)0xf417ac22, (q31_t)0x7edf94c7, (q31_t)0xf40b538b,
+    (q31_t)0x7edd3a9a, (q31_t)0xf3fefb6a, (q31_t)0x7edade01, (q31_t)0xf3f2a3bf,
+    (q31_t)0x7ed87efc, (q31_t)0xf3e64c8c, (q31_t)0x7ed61d8a, (q31_t)0xf3d9f5cf,
+    (q31_t)0x7ed3b9ad, (q31_t)0xf3cd9f8b, (q31_t)0x7ed15363, (q31_t)0xf3c149bf,
+    (q31_t)0x7eceeaad, (q31_t)0xf3b4f46c, (q31_t)0x7ecc7f8b, (q31_t)0xf3a89f92,
+    (q31_t)0x7eca11fe, (q31_t)0xf39c4b32, (q31_t)0x7ec7a205, (q31_t)0xf38ff74d,
+    (q31_t)0x7ec52fa0, (q31_t)0xf383a3e2, (q31_t)0x7ec2bad0, (q31_t)0xf37750f2,
+    (q31_t)0x7ec04394, (q31_t)0xf36afe7e, (q31_t)0x7ebdc9ed, (q31_t)0xf35eac86,
+    (q31_t)0x7ebb4ddb, (q31_t)0xf3525b0b, (q31_t)0x7eb8cf5d, (q31_t)0xf3460a0d,
+    (q31_t)0x7eb64e75, (q31_t)0xf339b98d, (q31_t)0x7eb3cb21, (q31_t)0xf32d698a,
+    (q31_t)0x7eb14563, (q31_t)0xf3211a07, (q31_t)0x7eaebd3a, (q31_t)0xf314cb02,
+    (q31_t)0x7eac32a6, (q31_t)0xf3087c7d, (q31_t)0x7ea9a5a8, (q31_t)0xf2fc2e77,
+    (q31_t)0x7ea7163f, (q31_t)0xf2efe0f2, (q31_t)0x7ea4846c, (q31_t)0xf2e393ef,
+    (q31_t)0x7ea1f02f, (q31_t)0xf2d7476c, (q31_t)0x7e9f5988, (q31_t)0xf2cafb6b,
+    (q31_t)0x7e9cc076, (q31_t)0xf2beafed, (q31_t)0x7e9a24fb, (q31_t)0xf2b264f2,
+    (q31_t)0x7e978715, (q31_t)0xf2a61a7a, (q31_t)0x7e94e6c6, (q31_t)0xf299d085,
+    (q31_t)0x7e92440d, (q31_t)0xf28d8715, (q31_t)0x7e8f9eeb, (q31_t)0xf2813e2a,
+    (q31_t)0x7e8cf75f, (q31_t)0xf274f5c3, (q31_t)0x7e8a4d6a, (q31_t)0xf268ade3,
+    (q31_t)0x7e87a10c, (q31_t)0xf25c6688, (q31_t)0x7e84f245, (q31_t)0xf2501fb5,
+    (q31_t)0x7e824114, (q31_t)0xf243d968, (q31_t)0x7e7f8d7b, (q31_t)0xf23793a3,
+    (q31_t)0x7e7cd778, (q31_t)0xf22b4e66, (q31_t)0x7e7a1f0d, (q31_t)0xf21f09b1,
+    (q31_t)0x7e77643a, (q31_t)0xf212c585, (q31_t)0x7e74a6fd, (q31_t)0xf20681e3,
+    (q31_t)0x7e71e759, (q31_t)0xf1fa3ecb, (q31_t)0x7e6f254c, (q31_t)0xf1edfc3d,
+    (q31_t)0x7e6c60d7, (q31_t)0xf1e1ba3a, (q31_t)0x7e6999fa, (q31_t)0xf1d578c2,
+    (q31_t)0x7e66d0b4, (q31_t)0xf1c937d6, (q31_t)0x7e640507, (q31_t)0xf1bcf777,
+    (q31_t)0x7e6136f3, (q31_t)0xf1b0b7a4, (q31_t)0x7e5e6676, (q31_t)0xf1a4785e,
+    (q31_t)0x7e5b9392, (q31_t)0xf19839a6, (q31_t)0x7e58be47, (q31_t)0xf18bfb7d,
+    (q31_t)0x7e55e694, (q31_t)0xf17fbde2, (q31_t)0x7e530c7a, (q31_t)0xf17380d6,
+    (q31_t)0x7e502ff9, (q31_t)0xf1674459, (q31_t)0x7e4d5110, (q31_t)0xf15b086d,
+    (q31_t)0x7e4a6fc1, (q31_t)0xf14ecd11, (q31_t)0x7e478c0b, (q31_t)0xf1429247,
+    (q31_t)0x7e44a5ef, (q31_t)0xf136580d, (q31_t)0x7e41bd6c, (q31_t)0xf12a1e66,
+    (q31_t)0x7e3ed282, (q31_t)0xf11de551, (q31_t)0x7e3be532, (q31_t)0xf111accf,
+    (q31_t)0x7e38f57c, (q31_t)0xf10574e0, (q31_t)0x7e360360, (q31_t)0xf0f93d86,
+    (q31_t)0x7e330ede, (q31_t)0xf0ed06bf, (q31_t)0x7e3017f6, (q31_t)0xf0e0d08d,
+    (q31_t)0x7e2d1ea8, (q31_t)0xf0d49af1, (q31_t)0x7e2a22f4, (q31_t)0xf0c865ea,
+    (q31_t)0x7e2724db, (q31_t)0xf0bc317a, (q31_t)0x7e24245d, (q31_t)0xf0affda0,
+    (q31_t)0x7e212179, (q31_t)0xf0a3ca5d, (q31_t)0x7e1e1c30, (q31_t)0xf09797b2,
+    (q31_t)0x7e1b1482, (q31_t)0xf08b659f, (q31_t)0x7e180a6f, (q31_t)0xf07f3424,
+    (q31_t)0x7e14fdf7, (q31_t)0xf0730342, (q31_t)0x7e11ef1b, (q31_t)0xf066d2fa,
+    (q31_t)0x7e0eddd9, (q31_t)0xf05aa34c, (q31_t)0x7e0bca34, (q31_t)0xf04e7438,
+    (q31_t)0x7e08b42a, (q31_t)0xf04245c0, (q31_t)0x7e059bbb, (q31_t)0xf03617e2,
+    (q31_t)0x7e0280e9, (q31_t)0xf029eaa1, (q31_t)0x7dff63b2, (q31_t)0xf01dbdfb,
+    (q31_t)0x7dfc4418, (q31_t)0xf01191f3, (q31_t)0x7df9221a, (q31_t)0xf0056687,
+    (q31_t)0x7df5fdb8, (q31_t)0xeff93bba, (q31_t)0x7df2d6f3, (q31_t)0xefed118a,
+    (q31_t)0x7defadca, (q31_t)0xefe0e7f9, (q31_t)0x7dec823e, (q31_t)0xefd4bf08,
+    (q31_t)0x7de9544f, (q31_t)0xefc896b5, (q31_t)0x7de623fd, (q31_t)0xefbc6f03,
+    (q31_t)0x7de2f148, (q31_t)0xefb047f2, (q31_t)0x7ddfbc30, (q31_t)0xefa42181,
+    (q31_t)0x7ddc84b5, (q31_t)0xef97fbb2, (q31_t)0x7dd94ad8, (q31_t)0xef8bd685,
+    (q31_t)0x7dd60e99, (q31_t)0xef7fb1fa, (q31_t)0x7dd2cff7, (q31_t)0xef738e12,
+    (q31_t)0x7dcf8ef3, (q31_t)0xef676ace, (q31_t)0x7dcc4b8d, (q31_t)0xef5b482d,
+    (q31_t)0x7dc905c5, (q31_t)0xef4f2630, (q31_t)0x7dc5bd9b, (q31_t)0xef4304d8,
+    (q31_t)0x7dc2730f, (q31_t)0xef36e426, (q31_t)0x7dbf2622, (q31_t)0xef2ac419,
+    (q31_t)0x7dbbd6d4, (q31_t)0xef1ea4b2, (q31_t)0x7db88524, (q31_t)0xef1285f2,
+    (q31_t)0x7db53113, (q31_t)0xef0667d9, (q31_t)0x7db1daa2, (q31_t)0xeefa4a67,
+    (q31_t)0x7dae81cf, (q31_t)0xeeee2d9d, (q31_t)0x7dab269b, (q31_t)0xeee2117c,
+    (q31_t)0x7da7c907, (q31_t)0xeed5f604, (q31_t)0x7da46912, (q31_t)0xeec9db35,
+    (q31_t)0x7da106bd, (q31_t)0xeebdc110, (q31_t)0x7d9da208, (q31_t)0xeeb1a796,
+    (q31_t)0x7d9a3af2, (q31_t)0xeea58ec6, (q31_t)0x7d96d17d, (q31_t)0xee9976a1,
+    (q31_t)0x7d9365a8, (q31_t)0xee8d5f29, (q31_t)0x7d8ff772, (q31_t)0xee81485c,
+    (q31_t)0x7d8c86de, (q31_t)0xee75323c, (q31_t)0x7d8913ea, (q31_t)0xee691cc9,
+    (q31_t)0x7d859e96, (q31_t)0xee5d0804, (q31_t)0x7d8226e4, (q31_t)0xee50f3ed,
+    (q31_t)0x7d7eacd2, (q31_t)0xee44e084, (q31_t)0x7d7b3061, (q31_t)0xee38cdcb,
+    (q31_t)0x7d77b192, (q31_t)0xee2cbbc1, (q31_t)0x7d743064, (q31_t)0xee20aa67,
+    (q31_t)0x7d70acd7, (q31_t)0xee1499bd, (q31_t)0x7d6d26ec, (q31_t)0xee0889c4,
+    (q31_t)0x7d699ea3, (q31_t)0xedfc7a7c, (q31_t)0x7d6613fb, (q31_t)0xedf06be6,
+    (q31_t)0x7d6286f6, (q31_t)0xede45e03, (q31_t)0x7d5ef793, (q31_t)0xedd850d2,
+    (q31_t)0x7d5b65d2, (q31_t)0xedcc4454, (q31_t)0x7d57d1b3, (q31_t)0xedc0388a,
+    (q31_t)0x7d543b37, (q31_t)0xedb42d74, (q31_t)0x7d50a25e, (q31_t)0xeda82313,
+    (q31_t)0x7d4d0728, (q31_t)0xed9c1967, (q31_t)0x7d496994, (q31_t)0xed901070,
+    (q31_t)0x7d45c9a4, (q31_t)0xed84082f, (q31_t)0x7d422757, (q31_t)0xed7800a5,
+    (q31_t)0x7d3e82ae, (q31_t)0xed6bf9d1, (q31_t)0x7d3adba7, (q31_t)0xed5ff3b5,
+    (q31_t)0x7d373245, (q31_t)0xed53ee51, (q31_t)0x7d338687, (q31_t)0xed47e9a5,
+    (q31_t)0x7d2fd86c, (q31_t)0xed3be5b1, (q31_t)0x7d2c27f6, (q31_t)0xed2fe277,
+    (q31_t)0x7d287523, (q31_t)0xed23dff7, (q31_t)0x7d24bff6, (q31_t)0xed17de31,
+    (q31_t)0x7d21086c, (q31_t)0xed0bdd25, (q31_t)0x7d1d4e88, (q31_t)0xecffdcd4,
+    (q31_t)0x7d199248, (q31_t)0xecf3dd3f, (q31_t)0x7d15d3ad, (q31_t)0xece7de66,
+    (q31_t)0x7d1212b7, (q31_t)0xecdbe04a, (q31_t)0x7d0e4f67, (q31_t)0xeccfe2ea,
+    (q31_t)0x7d0a89bc, (q31_t)0xecc3e648, (q31_t)0x7d06c1b6, (q31_t)0xecb7ea63,
+    (q31_t)0x7d02f757, (q31_t)0xecabef3d, (q31_t)0x7cff2a9d, (q31_t)0xec9ff4d6,
+    (q31_t)0x7cfb5b89, (q31_t)0xec93fb2e, (q31_t)0x7cf78a1b, (q31_t)0xec880245,
+    (q31_t)0x7cf3b653, (q31_t)0xec7c0a1d, (q31_t)0x7cefe032, (q31_t)0xec7012b5,
+    (q31_t)0x7cec07b8, (q31_t)0xec641c0e, (q31_t)0x7ce82ce4, (q31_t)0xec582629,
+    (q31_t)0x7ce44fb7, (q31_t)0xec4c3106, (q31_t)0x7ce07031, (q31_t)0xec403ca5,
+    (q31_t)0x7cdc8e52, (q31_t)0xec344908, (q31_t)0x7cd8aa1b, (q31_t)0xec28562d,
+    (q31_t)0x7cd4c38b, (q31_t)0xec1c6417, (q31_t)0x7cd0daa2, (q31_t)0xec1072c4,
+    (q31_t)0x7cccef62, (q31_t)0xec048237, (q31_t)0x7cc901c9, (q31_t)0xebf8926f,
+    (q31_t)0x7cc511d9, (q31_t)0xebeca36c, (q31_t)0x7cc11f90, (q31_t)0xebe0b52f,
+    (q31_t)0x7cbd2af0, (q31_t)0xebd4c7ba, (q31_t)0x7cb933f9, (q31_t)0xebc8db0b,
+    (q31_t)0x7cb53aaa, (q31_t)0xebbcef23, (q31_t)0x7cb13f04, (q31_t)0xebb10404,
+    (q31_t)0x7cad4107, (q31_t)0xeba519ad, (q31_t)0x7ca940b3, (q31_t)0xeb99301f,
+    (q31_t)0x7ca53e09, (q31_t)0xeb8d475b, (q31_t)0x7ca13908, (q31_t)0xeb815f60,
+    (q31_t)0x7c9d31b0, (q31_t)0xeb75782f, (q31_t)0x7c992803, (q31_t)0xeb6991ca,
+    (q31_t)0x7c951bff, (q31_t)0xeb5dac2f, (q31_t)0x7c910da5, (q31_t)0xeb51c760,
+    (q31_t)0x7c8cfcf6, (q31_t)0xeb45e35d, (q31_t)0x7c88e9f1, (q31_t)0xeb3a0027,
+    (q31_t)0x7c84d496, (q31_t)0xeb2e1dbe, (q31_t)0x7c80bce7, (q31_t)0xeb223c22,
+    (q31_t)0x7c7ca2e2, (q31_t)0xeb165b54, (q31_t)0x7c788688, (q31_t)0xeb0a7b54,
+    (q31_t)0x7c7467d9, (q31_t)0xeafe9c24, (q31_t)0x7c7046d6, (q31_t)0xeaf2bdc3,
+    (q31_t)0x7c6c237e, (q31_t)0xeae6e031, (q31_t)0x7c67fdd1, (q31_t)0xeadb0370,
+    (q31_t)0x7c63d5d1, (q31_t)0xeacf277f, (q31_t)0x7c5fab7c, (q31_t)0xeac34c60,
+    (q31_t)0x7c5b7ed4, (q31_t)0xeab77212, (q31_t)0x7c574fd8, (q31_t)0xeaab9896,
+    (q31_t)0x7c531e88, (q31_t)0xea9fbfed, (q31_t)0x7c4eeae5, (q31_t)0xea93e817,
+    (q31_t)0x7c4ab4ef, (q31_t)0xea881114, (q31_t)0x7c467ca6, (q31_t)0xea7c3ae5,
+    (q31_t)0x7c42420a, (q31_t)0xea70658a, (q31_t)0x7c3e051b, (q31_t)0xea649105,
+    (q31_t)0x7c39c5da, (q31_t)0xea58bd54, (q31_t)0x7c358446, (q31_t)0xea4cea79,
+    (q31_t)0x7c314060, (q31_t)0xea411874, (q31_t)0x7c2cfa28, (q31_t)0xea354746,
+    (q31_t)0x7c28b19e, (q31_t)0xea2976ef, (q31_t)0x7c2466c2, (q31_t)0xea1da770,
+    (q31_t)0x7c201994, (q31_t)0xea11d8c8, (q31_t)0x7c1bca16, (q31_t)0xea060af9,
+    (q31_t)0x7c177845, (q31_t)0xe9fa3e03, (q31_t)0x7c132424, (q31_t)0xe9ee71e6,
+    (q31_t)0x7c0ecdb2, (q31_t)0xe9e2a6a3, (q31_t)0x7c0a74f0, (q31_t)0xe9d6dc3b,
+    (q31_t)0x7c0619dc, (q31_t)0xe9cb12ad, (q31_t)0x7c01bc78, (q31_t)0xe9bf49fa,
+    (q31_t)0x7bfd5cc4, (q31_t)0xe9b38223, (q31_t)0x7bf8fac0, (q31_t)0xe9a7bb28,
+    (q31_t)0x7bf4966c, (q31_t)0xe99bf509, (q31_t)0x7bf02fc9, (q31_t)0xe9902fc7,
+    (q31_t)0x7bebc6d5, (q31_t)0xe9846b63, (q31_t)0x7be75b93, (q31_t)0xe978a7dd,
+    (q31_t)0x7be2ee01, (q31_t)0xe96ce535, (q31_t)0x7bde7e20, (q31_t)0xe961236c,
+    (q31_t)0x7bda0bf0, (q31_t)0xe9556282, (q31_t)0x7bd59771, (q31_t)0xe949a278,
+    (q31_t)0x7bd120a4, (q31_t)0xe93de34e, (q31_t)0x7bcca789, (q31_t)0xe9322505,
+    (q31_t)0x7bc82c1f, (q31_t)0xe926679c, (q31_t)0x7bc3ae67, (q31_t)0xe91aab16,
+    (q31_t)0x7bbf2e62, (q31_t)0xe90eef71, (q31_t)0x7bbaac0e, (q31_t)0xe90334af,
+    (q31_t)0x7bb6276e, (q31_t)0xe8f77acf, (q31_t)0x7bb1a080, (q31_t)0xe8ebc1d3,
+    (q31_t)0x7bad1744, (q31_t)0xe8e009ba, (q31_t)0x7ba88bbc, (q31_t)0xe8d45286,
+    (q31_t)0x7ba3fde7, (q31_t)0xe8c89c37, (q31_t)0x7b9f6dc5, (q31_t)0xe8bce6cd,
+    (q31_t)0x7b9adb57, (q31_t)0xe8b13248, (q31_t)0x7b96469d, (q31_t)0xe8a57ea9,
+    (q31_t)0x7b91af97, (q31_t)0xe899cbf1, (q31_t)0x7b8d1644, (q31_t)0xe88e1a20,
+    (q31_t)0x7b887aa6, (q31_t)0xe8826936, (q31_t)0x7b83dcbc, (q31_t)0xe876b934,
+    (q31_t)0x7b7f3c87, (q31_t)0xe86b0a1a, (q31_t)0x7b7a9a07, (q31_t)0xe85f5be9,
+    (q31_t)0x7b75f53c, (q31_t)0xe853aea1, (q31_t)0x7b714e25, (q31_t)0xe8480243,
+    (q31_t)0x7b6ca4c4, (q31_t)0xe83c56cf, (q31_t)0x7b67f919, (q31_t)0xe830ac45,
+    (q31_t)0x7b634b23, (q31_t)0xe82502a7, (q31_t)0x7b5e9ae4, (q31_t)0xe81959f4,
+    (q31_t)0x7b59e85a, (q31_t)0xe80db22d, (q31_t)0x7b553386, (q31_t)0xe8020b52,
+    (q31_t)0x7b507c69, (q31_t)0xe7f66564, (q31_t)0x7b4bc303, (q31_t)0xe7eac063,
+    (q31_t)0x7b470753, (q31_t)0xe7df1c50, (q31_t)0x7b42495a, (q31_t)0xe7d3792b,
+    (q31_t)0x7b3d8918, (q31_t)0xe7c7d6f4, (q31_t)0x7b38c68e, (q31_t)0xe7bc35ad,
+    (q31_t)0x7b3401bb, (q31_t)0xe7b09555, (q31_t)0x7b2f3aa0, (q31_t)0xe7a4f5ed,
+    (q31_t)0x7b2a713d, (q31_t)0xe7995776, (q31_t)0x7b25a591, (q31_t)0xe78db9ef,
+    (q31_t)0x7b20d79e, (q31_t)0xe7821d59, (q31_t)0x7b1c0764, (q31_t)0xe77681b6,
+    (q31_t)0x7b1734e2, (q31_t)0xe76ae704, (q31_t)0x7b126019, (q31_t)0xe75f4d45,
+    (q31_t)0x7b0d8909, (q31_t)0xe753b479, (q31_t)0x7b08afb2, (q31_t)0xe7481ca1,
+    (q31_t)0x7b03d414, (q31_t)0xe73c85bc, (q31_t)0x7afef630, (q31_t)0xe730efcc,
+    (q31_t)0x7afa1605, (q31_t)0xe7255ad1, (q31_t)0x7af53395, (q31_t)0xe719c6cb,
+    (q31_t)0x7af04edf, (q31_t)0xe70e33bb, (q31_t)0x7aeb67e3, (q31_t)0xe702a1a1,
+    (q31_t)0x7ae67ea1, (q31_t)0xe6f7107e, (q31_t)0x7ae1931a, (q31_t)0xe6eb8052,
+    (q31_t)0x7adca54e, (q31_t)0xe6dff11d, (q31_t)0x7ad7b53d, (q31_t)0xe6d462e1,
+    (q31_t)0x7ad2c2e8, (q31_t)0xe6c8d59c, (q31_t)0x7acdce4d, (q31_t)0xe6bd4951,
+    (q31_t)0x7ac8d76f, (q31_t)0xe6b1bdff, (q31_t)0x7ac3de4c, (q31_t)0xe6a633a6,
+    (q31_t)0x7abee2e5, (q31_t)0xe69aaa48, (q31_t)0x7ab9e53a, (q31_t)0xe68f21e5,
+    (q31_t)0x7ab4e54c, (q31_t)0xe6839a7c, (q31_t)0x7aafe31b, (q31_t)0xe6781410,
+    (q31_t)0x7aaadea6, (q31_t)0xe66c8e9f, (q31_t)0x7aa5d7ee, (q31_t)0xe6610a2a,
+    (q31_t)0x7aa0cef3, (q31_t)0xe65586b3, (q31_t)0x7a9bc3b6, (q31_t)0xe64a0438,
+    (q31_t)0x7a96b636, (q31_t)0xe63e82bc, (q31_t)0x7a91a674, (q31_t)0xe633023e,
+    (q31_t)0x7a8c9470, (q31_t)0xe62782be, (q31_t)0x7a87802a, (q31_t)0xe61c043d,
+    (q31_t)0x7a8269a3, (q31_t)0xe61086bc, (q31_t)0x7a7d50da, (q31_t)0xe6050a3b,
+    (q31_t)0x7a7835cf, (q31_t)0xe5f98ebb, (q31_t)0x7a731884, (q31_t)0xe5ee143b,
+    (q31_t)0x7a6df8f8, (q31_t)0xe5e29abc, (q31_t)0x7a68d72b, (q31_t)0xe5d72240,
+    (q31_t)0x7a63b31d, (q31_t)0xe5cbaac5, (q31_t)0x7a5e8cd0, (q31_t)0xe5c0344d,
+    (q31_t)0x7a596442, (q31_t)0xe5b4bed8, (q31_t)0x7a543974, (q31_t)0xe5a94a67,
+    (q31_t)0x7a4f0c67, (q31_t)0xe59dd6f9, (q31_t)0x7a49dd1a, (q31_t)0xe5926490,
+    (q31_t)0x7a44ab8e, (q31_t)0xe586f32c, (q31_t)0x7a3f77c3, (q31_t)0xe57b82cd,
+    (q31_t)0x7a3a41b9, (q31_t)0xe5701374, (q31_t)0x7a350970, (q31_t)0xe564a521,
+    (q31_t)0x7a2fcee8, (q31_t)0xe55937d5, (q31_t)0x7a2a9223, (q31_t)0xe54dcb8f,
+    (q31_t)0x7a25531f, (q31_t)0xe5426051, (q31_t)0x7a2011de, (q31_t)0xe536f61b,
+    (q31_t)0x7a1ace5f, (q31_t)0xe52b8cee, (q31_t)0x7a1588a2, (q31_t)0xe52024c9,
+    (q31_t)0x7a1040a8, (q31_t)0xe514bdad, (q31_t)0x7a0af671, (q31_t)0xe509579b,
+    (q31_t)0x7a05a9fd, (q31_t)0xe4fdf294, (q31_t)0x7a005b4d, (q31_t)0xe4f28e96,
+    (q31_t)0x79fb0a60, (q31_t)0xe4e72ba4, (q31_t)0x79f5b737, (q31_t)0xe4dbc9bd,
+    (q31_t)0x79f061d2, (q31_t)0xe4d068e2, (q31_t)0x79eb0a31, (q31_t)0xe4c50914,
+    (q31_t)0x79e5b054, (q31_t)0xe4b9aa52, (q31_t)0x79e0543c, (q31_t)0xe4ae4c9d,
+    (q31_t)0x79daf5e8, (q31_t)0xe4a2eff6, (q31_t)0x79d5955a, (q31_t)0xe497945d,
+    (q31_t)0x79d03291, (q31_t)0xe48c39d3, (q31_t)0x79cacd8d, (q31_t)0xe480e057,
+    (q31_t)0x79c5664f, (q31_t)0xe47587eb, (q31_t)0x79bffcd7, (q31_t)0xe46a308f,
+    (q31_t)0x79ba9125, (q31_t)0xe45eda43, (q31_t)0x79b52339, (q31_t)0xe4538507,
+    (q31_t)0x79afb313, (q31_t)0xe44830dd, (q31_t)0x79aa40b4, (q31_t)0xe43cddc4,
+    (q31_t)0x79a4cc1c, (q31_t)0xe4318bbe, (q31_t)0x799f554b, (q31_t)0xe4263ac9,
+    (q31_t)0x7999dc42, (q31_t)0xe41aeae8, (q31_t)0x799460ff, (q31_t)0xe40f9c1a,
+    (q31_t)0x798ee385, (q31_t)0xe4044e60, (q31_t)0x798963d2, (q31_t)0xe3f901ba,
+    (q31_t)0x7983e1e8, (q31_t)0xe3edb628, (q31_t)0x797e5dc6, (q31_t)0xe3e26bac,
+    (q31_t)0x7978d76c, (q31_t)0xe3d72245, (q31_t)0x79734edc, (q31_t)0xe3cbd9f4,
+    (q31_t)0x796dc414, (q31_t)0xe3c092b9, (q31_t)0x79683715, (q31_t)0xe3b54c95,
+    (q31_t)0x7962a7e0, (q31_t)0xe3aa0788, (q31_t)0x795d1675, (q31_t)0xe39ec393,
+    (q31_t)0x795782d3, (q31_t)0xe39380b6, (q31_t)0x7951ecfc, (q31_t)0xe3883ef2,
+    (q31_t)0x794c54ee, (q31_t)0xe37cfe47, (q31_t)0x7946baac, (q31_t)0xe371beb5,
+    (q31_t)0x79411e33, (q31_t)0xe366803c, (q31_t)0x793b7f86, (q31_t)0xe35b42df,
+    (q31_t)0x7935dea4, (q31_t)0xe350069b, (q31_t)0x79303b8e, (q31_t)0xe344cb73,
+    (q31_t)0x792a9642, (q31_t)0xe3399167, (q31_t)0x7924eec3, (q31_t)0xe32e5876,
+    (q31_t)0x791f4510, (q31_t)0xe32320a2, (q31_t)0x79199929, (q31_t)0xe317e9eb,
+    (q31_t)0x7913eb0e, (q31_t)0xe30cb451, (q31_t)0x790e3ac0, (q31_t)0xe3017fd5,
+    (q31_t)0x7908883f, (q31_t)0xe2f64c77, (q31_t)0x7902d38b, (q31_t)0xe2eb1a37,
+    (q31_t)0x78fd1ca4, (q31_t)0xe2dfe917, (q31_t)0x78f7638b, (q31_t)0xe2d4b916,
+    (q31_t)0x78f1a840, (q31_t)0xe2c98a35, (q31_t)0x78ebeac2, (q31_t)0xe2be5c74,
+    (q31_t)0x78e62b13, (q31_t)0xe2b32fd4, (q31_t)0x78e06932, (q31_t)0xe2a80456,
+    (q31_t)0x78daa520, (q31_t)0xe29cd9f8, (q31_t)0x78d4dedd, (q31_t)0xe291b0bd,
+    (q31_t)0x78cf1669, (q31_t)0xe28688a4, (q31_t)0x78c94bc4, (q31_t)0xe27b61af,
+    (q31_t)0x78c37eef, (q31_t)0xe2703bdc, (q31_t)0x78bdafea, (q31_t)0xe265172e,
+    (q31_t)0x78b7deb4, (q31_t)0xe259f3a3, (q31_t)0x78b20b4f, (q31_t)0xe24ed13d,
+    (q31_t)0x78ac35ba, (q31_t)0xe243affc, (q31_t)0x78a65df6, (q31_t)0xe2388fe1,
+    (q31_t)0x78a08402, (q31_t)0xe22d70eb, (q31_t)0x789aa7e0, (q31_t)0xe222531c,
+    (q31_t)0x7894c98f, (q31_t)0xe2173674, (q31_t)0x788ee910, (q31_t)0xe20c1af3,
+    (q31_t)0x78890663, (q31_t)0xe2010099, (q31_t)0x78832187, (q31_t)0xe1f5e768,
+    (q31_t)0x787d3a7e, (q31_t)0xe1eacf5f, (q31_t)0x78775147, (q31_t)0xe1dfb87f,
+    (q31_t)0x787165e3, (q31_t)0xe1d4a2c8, (q31_t)0x786b7852, (q31_t)0xe1c98e3b,
+    (q31_t)0x78658894, (q31_t)0xe1be7ad8, (q31_t)0x785f96a9, (q31_t)0xe1b368a0,
+    (q31_t)0x7859a292, (q31_t)0xe1a85793, (q31_t)0x7853ac4f, (q31_t)0xe19d47b1,
+    (q31_t)0x784db3e0, (q31_t)0xe19238fb, (q31_t)0x7847b946, (q31_t)0xe1872b72,
+    (q31_t)0x7841bc7f, (q31_t)0xe17c1f15, (q31_t)0x783bbd8e, (q31_t)0xe17113e5,
+    (q31_t)0x7835bc71, (q31_t)0xe16609e3, (q31_t)0x782fb92a, (q31_t)0xe15b0110,
+    (q31_t)0x7829b3b9, (q31_t)0xe14ff96a, (q31_t)0x7823ac1d, (q31_t)0xe144f2f3,
+    (q31_t)0x781da256, (q31_t)0xe139edac, (q31_t)0x78179666, (q31_t)0xe12ee995,
+    (q31_t)0x7811884d, (q31_t)0xe123e6ad, (q31_t)0x780b780a, (q31_t)0xe118e4f6,
+    (q31_t)0x7805659e, (q31_t)0xe10de470, (q31_t)0x77ff5109, (q31_t)0xe102e51c,
+    (q31_t)0x77f93a4b, (q31_t)0xe0f7e6f9, (q31_t)0x77f32165, (q31_t)0xe0ecea09,
+    (q31_t)0x77ed0657, (q31_t)0xe0e1ee4b, (q31_t)0x77e6e921, (q31_t)0xe0d6f3c1,
+    (q31_t)0x77e0c9c3, (q31_t)0xe0cbfa6a, (q31_t)0x77daa83d, (q31_t)0xe0c10247,
+    (q31_t)0x77d48490, (q31_t)0xe0b60b58, (q31_t)0x77ce5ebd, (q31_t)0xe0ab159e,
+    (q31_t)0x77c836c2, (q31_t)0xe0a0211a, (q31_t)0x77c20ca1, (q31_t)0xe0952dcb,
+    (q31_t)0x77bbe05a, (q31_t)0xe08a3bb2, (q31_t)0x77b5b1ec, (q31_t)0xe07f4acf,
+    (q31_t)0x77af8159, (q31_t)0xe0745b24, (q31_t)0x77a94ea0, (q31_t)0xe0696cb0,
+    (q31_t)0x77a319c2, (q31_t)0xe05e7f74, (q31_t)0x779ce2be, (q31_t)0xe053936f,
+    (q31_t)0x7796a996, (q31_t)0xe048a8a4, (q31_t)0x77906e49, (q31_t)0xe03dbf11,
+    (q31_t)0x778a30d8, (q31_t)0xe032d6b8, (q31_t)0x7783f143, (q31_t)0xe027ef99,
+    (q31_t)0x777daf89, (q31_t)0xe01d09b4, (q31_t)0x77776bac, (q31_t)0xe012250a,
+    (q31_t)0x777125ac, (q31_t)0xe007419b, (q31_t)0x776add88, (q31_t)0xdffc5f67,
+    (q31_t)0x77649341, (q31_t)0xdff17e70, (q31_t)0x775e46d8, (q31_t)0xdfe69eb4,
+    (q31_t)0x7757f84c, (q31_t)0xdfdbc036, (q31_t)0x7751a79e, (q31_t)0xdfd0e2f5,
+    (q31_t)0x774b54ce, (q31_t)0xdfc606f1, (q31_t)0x7744ffdd, (q31_t)0xdfbb2c2c,
+    (q31_t)0x773ea8ca, (q31_t)0xdfb052a5, (q31_t)0x77384f95, (q31_t)0xdfa57a5d,
+    (q31_t)0x7731f440, (q31_t)0xdf9aa354, (q31_t)0x772b96ca, (q31_t)0xdf8fcd8b,
+    (q31_t)0x77253733, (q31_t)0xdf84f902, (q31_t)0x771ed57c, (q31_t)0xdf7a25ba,
+    (q31_t)0x771871a5, (q31_t)0xdf6f53b3, (q31_t)0x77120bae, (q31_t)0xdf6482ed,
+    (q31_t)0x770ba398, (q31_t)0xdf59b369, (q31_t)0x77053962, (q31_t)0xdf4ee527,
+    (q31_t)0x76fecd0e, (q31_t)0xdf441828, (q31_t)0x76f85e9a, (q31_t)0xdf394c6b,
+    (q31_t)0x76f1ee09, (q31_t)0xdf2e81f3, (q31_t)0x76eb7b58, (q31_t)0xdf23b8be,
+    (q31_t)0x76e5068a, (q31_t)0xdf18f0ce, (q31_t)0x76de8f9e, (q31_t)0xdf0e2a22,
+    (q31_t)0x76d81695, (q31_t)0xdf0364bc, (q31_t)0x76d19b6e, (q31_t)0xdef8a09b,
+    (q31_t)0x76cb1e2a, (q31_t)0xdeedddc0, (q31_t)0x76c49ec9, (q31_t)0xdee31c2b,
+    (q31_t)0x76be1d4c, (q31_t)0xded85bdd, (q31_t)0x76b799b3, (q31_t)0xdecd9cd7,
+    (q31_t)0x76b113fd, (q31_t)0xdec2df18, (q31_t)0x76aa8c2c, (q31_t)0xdeb822a1,
+    (q31_t)0x76a4023f, (q31_t)0xdead6773, (q31_t)0x769d7637, (q31_t)0xdea2ad8d,
+    (q31_t)0x7696e814, (q31_t)0xde97f4f1, (q31_t)0x769057d6, (q31_t)0xde8d3d9e,
+    (q31_t)0x7689c57d, (q31_t)0xde828796, (q31_t)0x7683310b, (q31_t)0xde77d2d8,
+    (q31_t)0x767c9a7e, (q31_t)0xde6d1f65, (q31_t)0x767601d7, (q31_t)0xde626d3e,
+    (q31_t)0x766f6717, (q31_t)0xde57bc62, (q31_t)0x7668ca3e, (q31_t)0xde4d0cd2,
+    (q31_t)0x76622b4c, (q31_t)0xde425e8f, (q31_t)0x765b8a41, (q31_t)0xde37b199,
+    (q31_t)0x7654e71d, (q31_t)0xde2d05f1, (q31_t)0x764e41e2, (q31_t)0xde225b96,
+    (q31_t)0x76479a8e, (q31_t)0xde17b28a, (q31_t)0x7640f123, (q31_t)0xde0d0acc,
+    (q31_t)0x763a45a0, (q31_t)0xde02645d, (q31_t)0x76339806, (q31_t)0xddf7bf3e,
+    (q31_t)0x762ce855, (q31_t)0xdded1b6e, (q31_t)0x7626368d, (q31_t)0xdde278ef,
+    (q31_t)0x761f82af, (q31_t)0xddd7d7c1, (q31_t)0x7618ccba, (q31_t)0xddcd37e4,
+    (q31_t)0x761214b0, (q31_t)0xddc29958, (q31_t)0x760b5a90, (q31_t)0xddb7fc1e,
+    (q31_t)0x76049e5b, (q31_t)0xddad6036, (q31_t)0x75fde011, (q31_t)0xdda2c5a2,
+    (q31_t)0x75f71fb1, (q31_t)0xdd982c60, (q31_t)0x75f05d3d, (q31_t)0xdd8d9472,
+    (q31_t)0x75e998b5, (q31_t)0xdd82fdd8, (q31_t)0x75e2d219, (q31_t)0xdd786892,
+    (q31_t)0x75dc0968, (q31_t)0xdd6dd4a2, (q31_t)0x75d53ea5, (q31_t)0xdd634206,
+    (q31_t)0x75ce71ce, (q31_t)0xdd58b0c0, (q31_t)0x75c7a2e3, (q31_t)0xdd4e20d0,
+    (q31_t)0x75c0d1e7, (q31_t)0xdd439236, (q31_t)0x75b9fed7, (q31_t)0xdd3904f4,
+    (q31_t)0x75b329b5, (q31_t)0xdd2e7908, (q31_t)0x75ac5282, (q31_t)0xdd23ee74,
+    (q31_t)0x75a5793c, (q31_t)0xdd196538, (q31_t)0x759e9de5, (q31_t)0xdd0edd55,
+    (q31_t)0x7597c07d, (q31_t)0xdd0456ca, (q31_t)0x7590e104, (q31_t)0xdcf9d199,
+    (q31_t)0x7589ff7a, (q31_t)0xdcef4dc2, (q31_t)0x75831be0, (q31_t)0xdce4cb44,
+    (q31_t)0x757c3636, (q31_t)0xdcda4a21, (q31_t)0x75754e7c, (q31_t)0xdccfca59,
+    (q31_t)0x756e64b2, (q31_t)0xdcc54bec, (q31_t)0x756778d9, (q31_t)0xdcbacedb,
+    (q31_t)0x75608af1, (q31_t)0xdcb05326, (q31_t)0x75599afa, (q31_t)0xdca5d8cd,
+    (q31_t)0x7552a8f4, (q31_t)0xdc9b5fd2, (q31_t)0x754bb4e1, (q31_t)0xdc90e834,
+    (q31_t)0x7544bebf, (q31_t)0xdc8671f3, (q31_t)0x753dc68f, (q31_t)0xdc7bfd11,
+    (q31_t)0x7536cc52, (q31_t)0xdc71898d, (q31_t)0x752fd008, (q31_t)0xdc671768,
+    (q31_t)0x7528d1b1, (q31_t)0xdc5ca6a2, (q31_t)0x7521d14d, (q31_t)0xdc52373c,
+    (q31_t)0x751acedd, (q31_t)0xdc47c936, (q31_t)0x7513ca60, (q31_t)0xdc3d5c91,
+    (q31_t)0x750cc3d8, (q31_t)0xdc32f14d, (q31_t)0x7505bb44, (q31_t)0xdc28876a,
+    (q31_t)0x74feb0a5, (q31_t)0xdc1e1ee9, (q31_t)0x74f7a3fb, (q31_t)0xdc13b7c9,
+    (q31_t)0x74f09546, (q31_t)0xdc09520d, (q31_t)0x74e98487, (q31_t)0xdbfeedb3,
+    (q31_t)0x74e271bd, (q31_t)0xdbf48abd, (q31_t)0x74db5cea, (q31_t)0xdbea292b,
+    (q31_t)0x74d4460c, (q31_t)0xdbdfc8fc, (q31_t)0x74cd2d26, (q31_t)0xdbd56a32,
+    (q31_t)0x74c61236, (q31_t)0xdbcb0cce, (q31_t)0x74bef53d, (q31_t)0xdbc0b0ce,
+    (q31_t)0x74b7d63c, (q31_t)0xdbb65634, (q31_t)0x74b0b533, (q31_t)0xdbabfd01,
+    (q31_t)0x74a99221, (q31_t)0xdba1a534, (q31_t)0x74a26d08, (q31_t)0xdb974ece,
+    (q31_t)0x749b45e7, (q31_t)0xdb8cf9cf, (q31_t)0x74941cbf, (q31_t)0xdb82a638,
+    (q31_t)0x748cf190, (q31_t)0xdb785409, (q31_t)0x7485c45b, (q31_t)0xdb6e0342,
+    (q31_t)0x747e951f, (q31_t)0xdb63b3e5, (q31_t)0x747763dd, (q31_t)0xdb5965f1,
+    (q31_t)0x74703095, (q31_t)0xdb4f1967, (q31_t)0x7468fb47, (q31_t)0xdb44ce46,
+    (q31_t)0x7461c3f5, (q31_t)0xdb3a8491, (q31_t)0x745a8a9d, (q31_t)0xdb303c46,
+    (q31_t)0x74534f41, (q31_t)0xdb25f566, (q31_t)0x744c11e0, (q31_t)0xdb1baff2,
+    (q31_t)0x7444d27b, (q31_t)0xdb116beb, (q31_t)0x743d9112, (q31_t)0xdb072950,
+    (q31_t)0x74364da6, (q31_t)0xdafce821, (q31_t)0x742f0836, (q31_t)0xdaf2a860,
+    (q31_t)0x7427c0c3, (q31_t)0xdae86a0d, (q31_t)0x7420774d, (q31_t)0xdade2d28,
+    (q31_t)0x74192bd5, (q31_t)0xdad3f1b1, (q31_t)0x7411de5b, (q31_t)0xdac9b7a9,
+    (q31_t)0x740a8edf, (q31_t)0xdabf7f11, (q31_t)0x74033d61, (q31_t)0xdab547e8,
+    (q31_t)0x73fbe9e2, (q31_t)0xdaab122f, (q31_t)0x73f49462, (q31_t)0xdaa0dde7,
+    (q31_t)0x73ed3ce1, (q31_t)0xda96ab0f, (q31_t)0x73e5e360, (q31_t)0xda8c79a9,
+    (q31_t)0x73de87de, (q31_t)0xda8249b4, (q31_t)0x73d72a5d, (q31_t)0xda781b31,
+    (q31_t)0x73cfcadc, (q31_t)0xda6dee21, (q31_t)0x73c8695b, (q31_t)0xda63c284,
+    (q31_t)0x73c105db, (q31_t)0xda599859, (q31_t)0x73b9a05d, (q31_t)0xda4f6fa3,
+    (q31_t)0x73b238e0, (q31_t)0xda454860, (q31_t)0x73aacf65, (q31_t)0xda3b2292,
+    (q31_t)0x73a363ec, (q31_t)0xda30fe38, (q31_t)0x739bf675, (q31_t)0xda26db54,
+    (q31_t)0x73948701, (q31_t)0xda1cb9e5, (q31_t)0x738d1590, (q31_t)0xda1299ec,
+    (q31_t)0x7385a222, (q31_t)0xda087b69, (q31_t)0x737e2cb7, (q31_t)0xd9fe5e5e,
+    (q31_t)0x7376b551, (q31_t)0xd9f442c9, (q31_t)0x736f3bee, (q31_t)0xd9ea28ac,
+    (q31_t)0x7367c090, (q31_t)0xd9e01006, (q31_t)0x73604336, (q31_t)0xd9d5f8d9,
+    (q31_t)0x7358c3e2, (q31_t)0xd9cbe325, (q31_t)0x73514292, (q31_t)0xd9c1cee9,
+    (q31_t)0x7349bf48, (q31_t)0xd9b7bc27, (q31_t)0x73423a04, (q31_t)0xd9adaadf,
+    (q31_t)0x733ab2c6, (q31_t)0xd9a39b11, (q31_t)0x7333298f, (q31_t)0xd9998cbe,
+    (q31_t)0x732b9e5e, (q31_t)0xd98f7fe6, (q31_t)0x73241134, (q31_t)0xd9857489,
+    (q31_t)0x731c8211, (q31_t)0xd97b6aa8, (q31_t)0x7314f0f6, (q31_t)0xd9716243,
+    (q31_t)0x730d5de3, (q31_t)0xd9675b5a, (q31_t)0x7305c8d7, (q31_t)0xd95d55ef,
+    (q31_t)0x72fe31d5, (q31_t)0xd9535201, (q31_t)0x72f698db, (q31_t)0xd9494f90,
+    (q31_t)0x72eefdea, (q31_t)0xd93f4e9e, (q31_t)0x72e76102, (q31_t)0xd9354f2a,
+    (q31_t)0x72dfc224, (q31_t)0xd92b5135, (q31_t)0x72d82150, (q31_t)0xd92154bf,
+    (q31_t)0x72d07e85, (q31_t)0xd91759c9, (q31_t)0x72c8d9c6, (q31_t)0xd90d6053,
+    (q31_t)0x72c13311, (q31_t)0xd903685d, (q31_t)0x72b98a67, (q31_t)0xd8f971e8,
+    (q31_t)0x72b1dfc9, (q31_t)0xd8ef7cf4, (q31_t)0x72aa3336, (q31_t)0xd8e58982,
+    (q31_t)0x72a284b0, (q31_t)0xd8db9792, (q31_t)0x729ad435, (q31_t)0xd8d1a724,
+    (q31_t)0x729321c7, (q31_t)0xd8c7b838, (q31_t)0x728b6d66, (q31_t)0xd8bdcad0,
+    (q31_t)0x7283b712, (q31_t)0xd8b3deeb, (q31_t)0x727bfecc, (q31_t)0xd8a9f48a,
+    (q31_t)0x72744493, (q31_t)0xd8a00bae, (q31_t)0x726c8868, (q31_t)0xd8962456,
+    (q31_t)0x7264ca4c, (q31_t)0xd88c3e83, (q31_t)0x725d0a3e, (q31_t)0xd8825a35,
+    (q31_t)0x72554840, (q31_t)0xd878776d, (q31_t)0x724d8450, (q31_t)0xd86e962b,
+    (q31_t)0x7245be70, (q31_t)0xd864b670, (q31_t)0x723df6a0, (q31_t)0xd85ad83c,
+    (q31_t)0x72362ce0, (q31_t)0xd850fb8e, (q31_t)0x722e6130, (q31_t)0xd8472069,
+    (q31_t)0x72269391, (q31_t)0xd83d46cc, (q31_t)0x721ec403, (q31_t)0xd8336eb7,
+    (q31_t)0x7216f287, (q31_t)0xd829982b, (q31_t)0x720f1f1c, (q31_t)0xd81fc328,
+    (q31_t)0x720749c3, (q31_t)0xd815efae, (q31_t)0x71ff727c, (q31_t)0xd80c1dbf,
+    (q31_t)0x71f79948, (q31_t)0xd8024d59, (q31_t)0x71efbe27, (q31_t)0xd7f87e7f,
+    (q31_t)0x71e7e118, (q31_t)0xd7eeb130, (q31_t)0x71e0021e, (q31_t)0xd7e4e56c,
+    (q31_t)0x71d82137, (q31_t)0xd7db1b34, (q31_t)0x71d03e64, (q31_t)0xd7d15288,
+    (q31_t)0x71c859a5, (q31_t)0xd7c78b68, (q31_t)0x71c072fb, (q31_t)0xd7bdc5d6,
+    (q31_t)0x71b88a66, (q31_t)0xd7b401d1, (q31_t)0x71b09fe7, (q31_t)0xd7aa3f5a,
+    (q31_t)0x71a8b37c, (q31_t)0xd7a07e70, (q31_t)0x71a0c528, (q31_t)0xd796bf16,
+    (q31_t)0x7198d4ea, (q31_t)0xd78d014a, (q31_t)0x7190e2c3, (q31_t)0xd783450d,
+    (q31_t)0x7188eeb2, (q31_t)0xd7798a60, (q31_t)0x7180f8b8, (q31_t)0xd76fd143,
+    (q31_t)0x717900d6, (q31_t)0xd76619b6, (q31_t)0x7171070c, (q31_t)0xd75c63ba,
+    (q31_t)0x71690b59, (q31_t)0xd752af4f, (q31_t)0x71610dbf, (q31_t)0xd748fc75,
+    (q31_t)0x71590e3e, (q31_t)0xd73f4b2e, (q31_t)0x71510cd5, (q31_t)0xd7359b78,
+    (q31_t)0x71490986, (q31_t)0xd72bed55, (q31_t)0x71410450, (q31_t)0xd72240c5,
+    (q31_t)0x7138fd35, (q31_t)0xd71895c9, (q31_t)0x7130f433, (q31_t)0xd70eec60,
+    (q31_t)0x7128e94c, (q31_t)0xd705448b, (q31_t)0x7120dc80, (q31_t)0xd6fb9e4b,
+    (q31_t)0x7118cdcf, (q31_t)0xd6f1f99f, (q31_t)0x7110bd39, (q31_t)0xd6e85689,
+    (q31_t)0x7108aabf, (q31_t)0xd6deb508, (q31_t)0x71009661, (q31_t)0xd6d5151d,
+    (q31_t)0x70f8801f, (q31_t)0xd6cb76c9, (q31_t)0x70f067fb, (q31_t)0xd6c1da0b,
+    (q31_t)0x70e84df3, (q31_t)0xd6b83ee4, (q31_t)0x70e03208, (q31_t)0xd6aea555,
+    (q31_t)0x70d8143b, (q31_t)0xd6a50d5d, (q31_t)0x70cff48c, (q31_t)0xd69b76fe,
+    (q31_t)0x70c7d2fb, (q31_t)0xd691e237, (q31_t)0x70bfaf89, (q31_t)0xd6884f09,
+    (q31_t)0x70b78a36, (q31_t)0xd67ebd74, (q31_t)0x70af6302, (q31_t)0xd6752d79,
+    (q31_t)0x70a739ed, (q31_t)0xd66b9f18, (q31_t)0x709f0ef8, (q31_t)0xd6621251,
+    (q31_t)0x7096e223, (q31_t)0xd6588725, (q31_t)0x708eb36f, (q31_t)0xd64efd94,
+    (q31_t)0x708682dc, (q31_t)0xd645759f, (q31_t)0x707e5069, (q31_t)0xd63bef46,
+    (q31_t)0x70761c18, (q31_t)0xd6326a88, (q31_t)0x706de5e9, (q31_t)0xd628e767,
+    (q31_t)0x7065addb, (q31_t)0xd61f65e4, (q31_t)0x705d73f0, (q31_t)0xd615e5fd,
+    (q31_t)0x70553828, (q31_t)0xd60c67b4, (q31_t)0x704cfa83, (q31_t)0xd602eb0a,
+    (q31_t)0x7044bb00, (q31_t)0xd5f96ffd, (q31_t)0x703c79a2, (q31_t)0xd5eff690,
+    (q31_t)0x70343667, (q31_t)0xd5e67ec1, (q31_t)0x702bf151, (q31_t)0xd5dd0892,
+    (q31_t)0x7023aa5f, (q31_t)0xd5d39403, (q31_t)0x701b6193, (q31_t)0xd5ca2115,
+    (q31_t)0x701316eb, (q31_t)0xd5c0afc6, (q31_t)0x700aca69, (q31_t)0xd5b74019,
+    (q31_t)0x70027c0c, (q31_t)0xd5add20d, (q31_t)0x6ffa2bd6, (q31_t)0xd5a465a3,
+    (q31_t)0x6ff1d9c7, (q31_t)0xd59afadb, (q31_t)0x6fe985de, (q31_t)0xd59191b5,
+    (q31_t)0x6fe1301c, (q31_t)0xd5882a32, (q31_t)0x6fd8d882, (q31_t)0xd57ec452,
+    (q31_t)0x6fd07f0f, (q31_t)0xd5756016, (q31_t)0x6fc823c5, (q31_t)0xd56bfd7d,
+    (q31_t)0x6fbfc6a3, (q31_t)0xd5629c89, (q31_t)0x6fb767aa, (q31_t)0xd5593d3a,
+    (q31_t)0x6faf06da, (q31_t)0xd54fdf8f, (q31_t)0x6fa6a433, (q31_t)0xd5468389,
+    (q31_t)0x6f9e3fb6, (q31_t)0xd53d292a, (q31_t)0x6f95d963, (q31_t)0xd533d070,
+    (q31_t)0x6f8d713a, (q31_t)0xd52a795d, (q31_t)0x6f85073c, (q31_t)0xd52123f0,
+    (q31_t)0x6f7c9b69, (q31_t)0xd517d02b, (q31_t)0x6f742dc1, (q31_t)0xd50e7e0d,
+    (q31_t)0x6f6bbe45, (q31_t)0xd5052d97, (q31_t)0x6f634cf5, (q31_t)0xd4fbdec9,
+    (q31_t)0x6f5ad9d1, (q31_t)0xd4f291a4, (q31_t)0x6f5264da, (q31_t)0xd4e94627,
+    (q31_t)0x6f49ee0f, (q31_t)0xd4dffc54, (q31_t)0x6f417573, (q31_t)0xd4d6b42b,
+    (q31_t)0x6f38fb03, (q31_t)0xd4cd6dab, (q31_t)0x6f307ec2, (q31_t)0xd4c428d6,
+    (q31_t)0x6f2800af, (q31_t)0xd4bae5ab, (q31_t)0x6f1f80ca, (q31_t)0xd4b1a42c,
+    (q31_t)0x6f16ff14, (q31_t)0xd4a86458, (q31_t)0x6f0e7b8e, (q31_t)0xd49f2630,
+    (q31_t)0x6f05f637, (q31_t)0xd495e9b3, (q31_t)0x6efd6f10, (q31_t)0xd48caee4,
+    (q31_t)0x6ef4e619, (q31_t)0xd48375c1, (q31_t)0x6eec5b53, (q31_t)0xd47a3e4b,
+    (q31_t)0x6ee3cebe, (q31_t)0xd4710883, (q31_t)0x6edb405a, (q31_t)0xd467d469,
+    (q31_t)0x6ed2b027, (q31_t)0xd45ea1fd, (q31_t)0x6eca1e27, (q31_t)0xd4557140,
+    (q31_t)0x6ec18a58, (q31_t)0xd44c4232, (q31_t)0x6eb8f4bc, (q31_t)0xd44314d3,
+    (q31_t)0x6eb05d53, (q31_t)0xd439e923, (q31_t)0x6ea7c41e, (q31_t)0xd430bf24,
+    (q31_t)0x6e9f291b, (q31_t)0xd42796d5, (q31_t)0x6e968c4d, (q31_t)0xd41e7037,
+    (q31_t)0x6e8dedb3, (q31_t)0xd4154b4a, (q31_t)0x6e854d4d, (q31_t)0xd40c280e,
+    (q31_t)0x6e7cab1c, (q31_t)0xd4030684, (q31_t)0x6e740720, (q31_t)0xd3f9e6ad,
+    (q31_t)0x6e6b615a, (q31_t)0xd3f0c887, (q31_t)0x6e62b9ca, (q31_t)0xd3e7ac15,
+    (q31_t)0x6e5a1070, (q31_t)0xd3de9156, (q31_t)0x6e51654c, (q31_t)0xd3d5784a,
+    (q31_t)0x6e48b860, (q31_t)0xd3cc60f2, (q31_t)0x6e4009aa, (q31_t)0xd3c34b4f,
+    (q31_t)0x6e37592c, (q31_t)0xd3ba3760, (q31_t)0x6e2ea6e6, (q31_t)0xd3b12526,
+    (q31_t)0x6e25f2d8, (q31_t)0xd3a814a2, (q31_t)0x6e1d3d03, (q31_t)0xd39f05d3,
+    (q31_t)0x6e148566, (q31_t)0xd395f8ba, (q31_t)0x6e0bcc03, (q31_t)0xd38ced57,
+    (q31_t)0x6e0310d9, (q31_t)0xd383e3ab, (q31_t)0x6dfa53e9, (q31_t)0xd37adbb6,
+    (q31_t)0x6df19534, (q31_t)0xd371d579, (q31_t)0x6de8d4b8, (q31_t)0xd368d0f3,
+    (q31_t)0x6de01278, (q31_t)0xd35fce26, (q31_t)0x6dd74e73, (q31_t)0xd356cd11,
+    (q31_t)0x6dce88aa, (q31_t)0xd34dcdb4, (q31_t)0x6dc5c11c, (q31_t)0xd344d011,
+    (q31_t)0x6dbcf7cb, (q31_t)0xd33bd427, (q31_t)0x6db42cb6, (q31_t)0xd332d9f7,
+    (q31_t)0x6dab5fdf, (q31_t)0xd329e181, (q31_t)0x6da29144, (q31_t)0xd320eac6,
+    (q31_t)0x6d99c0e7, (q31_t)0xd317f5c6, (q31_t)0x6d90eec8, (q31_t)0xd30f0280,
+    (q31_t)0x6d881ae8, (q31_t)0xd30610f7, (q31_t)0x6d7f4545, (q31_t)0xd2fd2129,
+    (q31_t)0x6d766de2, (q31_t)0xd2f43318, (q31_t)0x6d6d94bf, (q31_t)0xd2eb46c3,
+    (q31_t)0x6d64b9da, (q31_t)0xd2e25c2b, (q31_t)0x6d5bdd36, (q31_t)0xd2d97350,
+    (q31_t)0x6d52fed2, (q31_t)0xd2d08c33, (q31_t)0x6d4a1eaf, (q31_t)0xd2c7a6d4,
+    (q31_t)0x6d413ccd, (q31_t)0xd2bec333, (q31_t)0x6d38592c, (q31_t)0xd2b5e151,
+    (q31_t)0x6d2f73cd, (q31_t)0xd2ad012e, (q31_t)0x6d268cb0, (q31_t)0xd2a422ca,
+    (q31_t)0x6d1da3d5, (q31_t)0xd29b4626, (q31_t)0x6d14b93d, (q31_t)0xd2926b41,
+    (q31_t)0x6d0bcce8, (q31_t)0xd289921e, (q31_t)0x6d02ded7, (q31_t)0xd280babb,
+    (q31_t)0x6cf9ef09, (q31_t)0xd277e518, (q31_t)0x6cf0fd80, (q31_t)0xd26f1138,
+    (q31_t)0x6ce80a3a, (q31_t)0xd2663f19, (q31_t)0x6cdf153a, (q31_t)0xd25d6ebc,
+    (q31_t)0x6cd61e7f, (q31_t)0xd254a021, (q31_t)0x6ccd2609, (q31_t)0xd24bd34a,
+    (q31_t)0x6cc42bd9, (q31_t)0xd2430835, (q31_t)0x6cbb2fef, (q31_t)0xd23a3ee4,
+    (q31_t)0x6cb2324c, (q31_t)0xd2317756, (q31_t)0x6ca932ef, (q31_t)0xd228b18d,
+    (q31_t)0x6ca031da, (q31_t)0xd21fed88, (q31_t)0x6c972f0d, (q31_t)0xd2172b48,
+    (q31_t)0x6c8e2a87, (q31_t)0xd20e6acc, (q31_t)0x6c85244a, (q31_t)0xd205ac17,
+    (q31_t)0x6c7c1c55, (q31_t)0xd1fcef27, (q31_t)0x6c7312a9, (q31_t)0xd1f433fd,
+    (q31_t)0x6c6a0746, (q31_t)0xd1eb7a9a, (q31_t)0x6c60fa2d, (q31_t)0xd1e2c2fd,
+    (q31_t)0x6c57eb5e, (q31_t)0xd1da0d28, (q31_t)0x6c4edada, (q31_t)0xd1d1591a,
+    (q31_t)0x6c45c8a0, (q31_t)0xd1c8a6d4, (q31_t)0x6c3cb4b1, (q31_t)0xd1bff656,
+    (q31_t)0x6c339f0e, (q31_t)0xd1b747a0, (q31_t)0x6c2a87b6, (q31_t)0xd1ae9ab4,
+    (q31_t)0x6c216eaa, (q31_t)0xd1a5ef90, (q31_t)0x6c1853eb, (q31_t)0xd19d4636,
+    (q31_t)0x6c0f3779, (q31_t)0xd1949ea6, (q31_t)0x6c061953, (q31_t)0xd18bf8e0,
+    (q31_t)0x6bfcf97c, (q31_t)0xd18354e4, (q31_t)0x6bf3d7f2, (q31_t)0xd17ab2b3,
+    (q31_t)0x6beab4b6, (q31_t)0xd172124d, (q31_t)0x6be18fc9, (q31_t)0xd16973b3,
+    (q31_t)0x6bd8692b, (q31_t)0xd160d6e5, (q31_t)0x6bcf40dc, (q31_t)0xd1583be2,
+    (q31_t)0x6bc616dd, (q31_t)0xd14fa2ad, (q31_t)0x6bbceb2d, (q31_t)0xd1470b44,
+    (q31_t)0x6bb3bdce, (q31_t)0xd13e75a8, (q31_t)0x6baa8ec0, (q31_t)0xd135e1d9,
+    (q31_t)0x6ba15e03, (q31_t)0xd12d4fd9, (q31_t)0x6b982b97, (q31_t)0xd124bfa6,
+    (q31_t)0x6b8ef77d, (q31_t)0xd11c3142, (q31_t)0x6b85c1b5, (q31_t)0xd113a4ad,
+    (q31_t)0x6b7c8a3f, (q31_t)0xd10b19e7, (q31_t)0x6b73511c, (q31_t)0xd10290f0,
+    (q31_t)0x6b6a164d, (q31_t)0xd0fa09c9, (q31_t)0x6b60d9d0, (q31_t)0xd0f18472,
+    (q31_t)0x6b579ba8, (q31_t)0xd0e900ec, (q31_t)0x6b4e5bd4, (q31_t)0xd0e07f36,
+    (q31_t)0x6b451a55, (q31_t)0xd0d7ff51, (q31_t)0x6b3bd72a, (q31_t)0xd0cf813e,
+    (q31_t)0x6b329255, (q31_t)0xd0c704fd, (q31_t)0x6b294bd5, (q31_t)0xd0be8a8d,
+    (q31_t)0x6b2003ac, (q31_t)0xd0b611f1, (q31_t)0x6b16b9d9, (q31_t)0xd0ad9b26,
+    (q31_t)0x6b0d6e5c, (q31_t)0xd0a5262f, (q31_t)0x6b042137, (q31_t)0xd09cb30b,
+    (q31_t)0x6afad269, (q31_t)0xd09441bb, (q31_t)0x6af181f3, (q31_t)0xd08bd23f,
+    (q31_t)0x6ae82fd5, (q31_t)0xd0836497, (q31_t)0x6adedc10, (q31_t)0xd07af8c4,
+    (q31_t)0x6ad586a3, (q31_t)0xd0728ec6, (q31_t)0x6acc2f90, (q31_t)0xd06a269d,
+    (q31_t)0x6ac2d6d6, (q31_t)0xd061c04a, (q31_t)0x6ab97c77, (q31_t)0xd0595bcd,
+    (q31_t)0x6ab02071, (q31_t)0xd050f926, (q31_t)0x6aa6c2c6, (q31_t)0xd0489856,
+    (q31_t)0x6a9d6377, (q31_t)0xd040395d, (q31_t)0x6a940283, (q31_t)0xd037dc3b,
+    (q31_t)0x6a8a9fea, (q31_t)0xd02f80f1, (q31_t)0x6a813bae, (q31_t)0xd027277e,
+    (q31_t)0x6a77d5ce, (q31_t)0xd01ecfe4, (q31_t)0x6a6e6e4b, (q31_t)0xd0167a22,
+    (q31_t)0x6a650525, (q31_t)0xd00e2639, (q31_t)0x6a5b9a5d, (q31_t)0xd005d42a,
+    (q31_t)0x6a522df3, (q31_t)0xcffd83f4, (q31_t)0x6a48bfe7, (q31_t)0xcff53597,
+    (q31_t)0x6a3f503a, (q31_t)0xcfece915, (q31_t)0x6a35deeb, (q31_t)0xcfe49e6d,
+    (q31_t)0x6a2c6bfd, (q31_t)0xcfdc55a1, (q31_t)0x6a22f76e, (q31_t)0xcfd40eaf,
+    (q31_t)0x6a19813f, (q31_t)0xcfcbc999, (q31_t)0x6a100970, (q31_t)0xcfc3865e,
+    (q31_t)0x6a069003, (q31_t)0xcfbb4500, (q31_t)0x69fd14f6, (q31_t)0xcfb3057d,
+    (q31_t)0x69f3984c, (q31_t)0xcfaac7d8, (q31_t)0x69ea1a03, (q31_t)0xcfa28c10,
+    (q31_t)0x69e09a1c, (q31_t)0xcf9a5225, (q31_t)0x69d71899, (q31_t)0xcf921a17,
+    (q31_t)0x69cd9578, (q31_t)0xcf89e3e8, (q31_t)0x69c410ba, (q31_t)0xcf81af97,
+    (q31_t)0x69ba8a61, (q31_t)0xcf797d24, (q31_t)0x69b1026c, (q31_t)0xcf714c91,
+    (q31_t)0x69a778db, (q31_t)0xcf691ddd, (q31_t)0x699dedaf, (q31_t)0xcf60f108,
+    (q31_t)0x699460e8, (q31_t)0xcf58c613, (q31_t)0x698ad287, (q31_t)0xcf509cfe,
+    (q31_t)0x6981428c, (q31_t)0xcf4875ca, (q31_t)0x6977b0f7, (q31_t)0xcf405077,
+    (q31_t)0x696e1dc9, (q31_t)0xcf382d05, (q31_t)0x69648902, (q31_t)0xcf300b74,
+    (q31_t)0x695af2a3, (q31_t)0xcf27ebc5, (q31_t)0x69515aab, (q31_t)0xcf1fcdf8,
+    (q31_t)0x6947c11c, (q31_t)0xcf17b20d, (q31_t)0x693e25f5, (q31_t)0xcf0f9805,
+    (q31_t)0x69348937, (q31_t)0xcf077fe1, (q31_t)0x692aeae3, (q31_t)0xceff699f,
+    (q31_t)0x69214af8, (q31_t)0xcef75541, (q31_t)0x6917a977, (q31_t)0xceef42c7,
+    (q31_t)0x690e0661, (q31_t)0xcee73231, (q31_t)0x690461b5, (q31_t)0xcedf2380,
+    (q31_t)0x68fabb75, (q31_t)0xced716b4, (q31_t)0x68f113a0, (q31_t)0xcecf0bcd,
+    (q31_t)0x68e76a37, (q31_t)0xcec702cb, (q31_t)0x68ddbf3b, (q31_t)0xcebefbb0,
+    (q31_t)0x68d412ab, (q31_t)0xceb6f67a, (q31_t)0x68ca6488, (q31_t)0xceaef32b,
+    (q31_t)0x68c0b4d2, (q31_t)0xcea6f1c2, (q31_t)0x68b7038b, (q31_t)0xce9ef241,
+    (q31_t)0x68ad50b1, (q31_t)0xce96f4a7, (q31_t)0x68a39c46, (q31_t)0xce8ef8f4,
+    (q31_t)0x6899e64a, (q31_t)0xce86ff2a, (q31_t)0x68902ebd, (q31_t)0xce7f0748,
+    (q31_t)0x688675a0, (q31_t)0xce77114e, (q31_t)0x687cbaf3, (q31_t)0xce6f1d3d,
+    (q31_t)0x6872feb6, (q31_t)0xce672b16, (q31_t)0x686940ea, (q31_t)0xce5f3ad8,
+    (q31_t)0x685f8190, (q31_t)0xce574c84, (q31_t)0x6855c0a6, (q31_t)0xce4f6019,
+    (q31_t)0x684bfe2f, (q31_t)0xce47759a, (q31_t)0x68423a2a, (q31_t)0xce3f8d05,
+    (q31_t)0x68387498, (q31_t)0xce37a65b, (q31_t)0x682ead78, (q31_t)0xce2fc19c,
+    (q31_t)0x6824e4cc, (q31_t)0xce27dec9, (q31_t)0x681b1a94, (q31_t)0xce1ffde2,
+    (q31_t)0x68114ed0, (q31_t)0xce181ee8, (q31_t)0x68078181, (q31_t)0xce1041d9,
+    (q31_t)0x67fdb2a7, (q31_t)0xce0866b8, (q31_t)0x67f3e241, (q31_t)0xce008d84,
+    (q31_t)0x67ea1052, (q31_t)0xcdf8b63d, (q31_t)0x67e03cd8, (q31_t)0xcdf0e0e4,
+    (q31_t)0x67d667d5, (q31_t)0xcde90d79, (q31_t)0x67cc9149, (q31_t)0xcde13bfd,
+    (q31_t)0x67c2b934, (q31_t)0xcdd96c6f, (q31_t)0x67b8df97, (q31_t)0xcdd19ed0,
+    (q31_t)0x67af0472, (q31_t)0xcdc9d320, (q31_t)0x67a527c4, (q31_t)0xcdc20960,
+    (q31_t)0x679b4990, (q31_t)0xcdba4190, (q31_t)0x679169d5, (q31_t)0xcdb27bb0,
+    (q31_t)0x67878893, (q31_t)0xcdaab7c0, (q31_t)0x677da5cb, (q31_t)0xcda2f5c2,
+    (q31_t)0x6773c17d, (q31_t)0xcd9b35b4, (q31_t)0x6769dbaa, (q31_t)0xcd937798,
+    (q31_t)0x675ff452, (q31_t)0xcd8bbb6d, (q31_t)0x67560b76, (q31_t)0xcd840134,
+    (q31_t)0x674c2115, (q31_t)0xcd7c48ee, (q31_t)0x67423530, (q31_t)0xcd74929a,
+    (q31_t)0x673847c8, (q31_t)0xcd6cde39, (q31_t)0x672e58dc, (q31_t)0xcd652bcb,
+    (q31_t)0x6724686e, (q31_t)0xcd5d7b50, (q31_t)0x671a767e, (q31_t)0xcd55ccca,
+    (q31_t)0x6710830c, (q31_t)0xcd4e2037, (q31_t)0x67068e18, (q31_t)0xcd467599,
+    (q31_t)0x66fc97a3, (q31_t)0xcd3eccef, (q31_t)0x66f29fad, (q31_t)0xcd37263a,
+    (q31_t)0x66e8a637, (q31_t)0xcd2f817b, (q31_t)0x66deab41, (q31_t)0xcd27deb0,
+    (q31_t)0x66d4aecb, (q31_t)0xcd203ddc, (q31_t)0x66cab0d6, (q31_t)0xcd189efe,
+    (q31_t)0x66c0b162, (q31_t)0xcd110216, (q31_t)0x66b6b070, (q31_t)0xcd096725,
+    (q31_t)0x66acadff, (q31_t)0xcd01ce2b, (q31_t)0x66a2aa11, (q31_t)0xccfa3729,
+    (q31_t)0x6698a4a6, (q31_t)0xccf2a21d, (q31_t)0x668e9dbd, (q31_t)0xcceb0f0a,
+    (q31_t)0x66849558, (q31_t)0xcce37def, (q31_t)0x667a8b77, (q31_t)0xccdbeecc,
+    (q31_t)0x6670801a, (q31_t)0xccd461a2, (q31_t)0x66667342, (q31_t)0xccccd671,
+    (q31_t)0x665c64ef, (q31_t)0xccc54d3a, (q31_t)0x66525521, (q31_t)0xccbdc5fc,
+    (q31_t)0x664843d9, (q31_t)0xccb640b8, (q31_t)0x663e3117, (q31_t)0xccaebd6e,
+    (q31_t)0x66341cdb, (q31_t)0xcca73c1e, (q31_t)0x662a0727, (q31_t)0xcc9fbcca,
+    (q31_t)0x661feffa, (q31_t)0xcc983f70, (q31_t)0x6615d754, (q31_t)0xcc90c412,
+    (q31_t)0x660bbd37, (q31_t)0xcc894aaf, (q31_t)0x6601a1a2, (q31_t)0xcc81d349,
+    (q31_t)0x65f78497, (q31_t)0xcc7a5dde, (q31_t)0x65ed6614, (q31_t)0xcc72ea70,
+    (q31_t)0x65e3461b, (q31_t)0xcc6b78ff, (q31_t)0x65d924ac, (q31_t)0xcc64098b,
+    (q31_t)0x65cf01c8, (q31_t)0xcc5c9c14, (q31_t)0x65c4dd6e, (q31_t)0xcc55309b,
+    (q31_t)0x65bab7a0, (q31_t)0xcc4dc720, (q31_t)0x65b0905d, (q31_t)0xcc465fa3,
+    (q31_t)0x65a667a7, (q31_t)0xcc3efa25, (q31_t)0x659c3d7c, (q31_t)0xcc3796a5,
+    (q31_t)0x659211df, (q31_t)0xcc303524, (q31_t)0x6587e4cf, (q31_t)0xcc28d5a3,
+    (q31_t)0x657db64c, (q31_t)0xcc217822, (q31_t)0x65738657, (q31_t)0xcc1a1ca0,
+    (q31_t)0x656954f1, (q31_t)0xcc12c31f, (q31_t)0x655f2219, (q31_t)0xcc0b6b9e,
+    (q31_t)0x6554edd1, (q31_t)0xcc04161e, (q31_t)0x654ab818, (q31_t)0xcbfcc29f,
+    (q31_t)0x654080ef, (q31_t)0xcbf57121, (q31_t)0x65364857, (q31_t)0xcbee21a5,
+    (q31_t)0x652c0e4f, (q31_t)0xcbe6d42b, (q31_t)0x6521d2d8, (q31_t)0xcbdf88b3,
+    (q31_t)0x651795f3, (q31_t)0xcbd83f3d, (q31_t)0x650d57a0, (q31_t)0xcbd0f7ca,
+    (q31_t)0x650317df, (q31_t)0xcbc9b25a, (q31_t)0x64f8d6b0, (q31_t)0xcbc26eee,
+    (q31_t)0x64ee9415, (q31_t)0xcbbb2d85, (q31_t)0x64e4500e, (q31_t)0xcbb3ee20,
+    (q31_t)0x64da0a9a, (q31_t)0xcbacb0bf, (q31_t)0x64cfc3ba, (q31_t)0xcba57563,
+    (q31_t)0x64c57b6f, (q31_t)0xcb9e3c0b, (q31_t)0x64bb31ba, (q31_t)0xcb9704b9,
+    (q31_t)0x64b0e699, (q31_t)0xcb8fcf6b, (q31_t)0x64a69a0f, (q31_t)0xcb889c23,
+    (q31_t)0x649c4c1b, (q31_t)0xcb816ae1, (q31_t)0x6491fcbe, (q31_t)0xcb7a3ba5,
+    (q31_t)0x6487abf7, (q31_t)0xcb730e70, (q31_t)0x647d59c8, (q31_t)0xcb6be341,
+    (q31_t)0x64730631, (q31_t)0xcb64ba19, (q31_t)0x6468b132, (q31_t)0xcb5d92f8,
+    (q31_t)0x645e5acc, (q31_t)0xcb566ddf, (q31_t)0x645402ff, (q31_t)0xcb4f4acd,
+    (q31_t)0x6449a9cc, (q31_t)0xcb4829c4, (q31_t)0x643f4f32, (q31_t)0xcb410ac3,
+    (q31_t)0x6434f332, (q31_t)0xcb39edca, (q31_t)0x642a95ce, (q31_t)0xcb32d2da,
+    (q31_t)0x64203704, (q31_t)0xcb2bb9f4, (q31_t)0x6415d6d5, (q31_t)0xcb24a316,
+    (q31_t)0x640b7543, (q31_t)0xcb1d8e43, (q31_t)0x6401124d, (q31_t)0xcb167b79,
+    (q31_t)0x63f6adf3, (q31_t)0xcb0f6aba, (q31_t)0x63ec4837, (q31_t)0xcb085c05,
+    (q31_t)0x63e1e117, (q31_t)0xcb014f5b, (q31_t)0x63d77896, (q31_t)0xcafa44bc,
+    (q31_t)0x63cd0eb3, (q31_t)0xcaf33c28, (q31_t)0x63c2a36f, (q31_t)0xcaec35a0,
+    (q31_t)0x63b836ca, (q31_t)0xcae53123, (q31_t)0x63adc8c4, (q31_t)0xcade2eb3,
+    (q31_t)0x63a3595e, (q31_t)0xcad72e4f, (q31_t)0x6398e898, (q31_t)0xcad02ff8,
+    (q31_t)0x638e7673, (q31_t)0xcac933ae, (q31_t)0x638402ef, (q31_t)0xcac23971,
+    (q31_t)0x63798e0d, (q31_t)0xcabb4141, (q31_t)0x636f17cc, (q31_t)0xcab44b1f,
+    (q31_t)0x6364a02e, (q31_t)0xcaad570c, (q31_t)0x635a2733, (q31_t)0xcaa66506,
+    (q31_t)0x634facda, (q31_t)0xca9f750f, (q31_t)0x63453125, (q31_t)0xca988727,
+    (q31_t)0x633ab414, (q31_t)0xca919b4e, (q31_t)0x633035a7, (q31_t)0xca8ab184,
+    (q31_t)0x6325b5df, (q31_t)0xca83c9ca, (q31_t)0x631b34bc, (q31_t)0xca7ce420,
+    (q31_t)0x6310b23e, (q31_t)0xca760086, (q31_t)0x63062e67, (q31_t)0xca6f1efc,
+    (q31_t)0x62fba936, (q31_t)0xca683f83, (q31_t)0x62f122ab, (q31_t)0xca61621b,
+    (q31_t)0x62e69ac8, (q31_t)0xca5a86c4, (q31_t)0x62dc118c, (q31_t)0xca53ad7e,
+    (q31_t)0x62d186f8, (q31_t)0xca4cd64b, (q31_t)0x62c6fb0c, (q31_t)0xca460129,
+    (q31_t)0x62bc6dca, (q31_t)0xca3f2e19, (q31_t)0x62b1df30, (q31_t)0xca385d1d,
+    (q31_t)0x62a74f40, (q31_t)0xca318e32, (q31_t)0x629cbdfa, (q31_t)0xca2ac15b,
+    (q31_t)0x62922b5e, (q31_t)0xca23f698, (q31_t)0x6287976e, (q31_t)0xca1d2de7,
+    (q31_t)0x627d0228, (q31_t)0xca16674b, (q31_t)0x62726b8e, (q31_t)0xca0fa2c3,
+    (q31_t)0x6267d3a0, (q31_t)0xca08e04f, (q31_t)0x625d3a5e, (q31_t)0xca021fef,
+    (q31_t)0x62529fca, (q31_t)0xc9fb61a5, (q31_t)0x624803e2, (q31_t)0xc9f4a570,
+    (q31_t)0x623d66a8, (q31_t)0xc9edeb50, (q31_t)0x6232c81c, (q31_t)0xc9e73346,
+    (q31_t)0x6228283f, (q31_t)0xc9e07d51, (q31_t)0x621d8711, (q31_t)0xc9d9c973,
+    (q31_t)0x6212e492, (q31_t)0xc9d317ab, (q31_t)0x620840c2, (q31_t)0xc9cc67fa,
+    (q31_t)0x61fd9ba3, (q31_t)0xc9c5ba60, (q31_t)0x61f2f534, (q31_t)0xc9bf0edd,
+    (q31_t)0x61e84d76, (q31_t)0xc9b86572, (q31_t)0x61dda46a, (q31_t)0xc9b1be1e,
+    (q31_t)0x61d2fa0f, (q31_t)0xc9ab18e3, (q31_t)0x61c84e67, (q31_t)0xc9a475bf,
+    (q31_t)0x61bda171, (q31_t)0xc99dd4b4, (q31_t)0x61b2f32e, (q31_t)0xc99735c2,
+    (q31_t)0x61a8439e, (q31_t)0xc99098e9, (q31_t)0x619d92c2, (q31_t)0xc989fe29,
+    (q31_t)0x6192e09b, (q31_t)0xc9836582, (q31_t)0x61882d28, (q31_t)0xc97ccef5,
+    (q31_t)0x617d786a, (q31_t)0xc9763a83, (q31_t)0x6172c262, (q31_t)0xc96fa82a,
+    (q31_t)0x61680b0f, (q31_t)0xc96917ec, (q31_t)0x615d5273, (q31_t)0xc96289c9,
+    (q31_t)0x6152988d, (q31_t)0xc95bfdc1, (q31_t)0x6147dd5f, (q31_t)0xc95573d4,
+    (q31_t)0x613d20e8, (q31_t)0xc94eec03, (q31_t)0x61326329, (q31_t)0xc948664d,
+    (q31_t)0x6127a423, (q31_t)0xc941e2b4, (q31_t)0x611ce3d5, (q31_t)0xc93b6137,
+    (q31_t)0x61122240, (q31_t)0xc934e1d6, (q31_t)0x61075f65, (q31_t)0xc92e6492,
+    (q31_t)0x60fc9b44, (q31_t)0xc927e96b, (q31_t)0x60f1d5de, (q31_t)0xc9217062,
+    (q31_t)0x60e70f32, (q31_t)0xc91af976, (q31_t)0x60dc4742, (q31_t)0xc91484a8,
+    (q31_t)0x60d17e0d, (q31_t)0xc90e11f7, (q31_t)0x60c6b395, (q31_t)0xc907a166,
+    (q31_t)0x60bbe7d8, (q31_t)0xc90132f2, (q31_t)0x60b11ad9, (q31_t)0xc8fac69e,
+    (q31_t)0x60a64c97, (q31_t)0xc8f45c68, (q31_t)0x609b7d13, (q31_t)0xc8edf452,
+    (q31_t)0x6090ac4d, (q31_t)0xc8e78e5b, (q31_t)0x6085da46, (q31_t)0xc8e12a84,
+    (q31_t)0x607b06fe, (q31_t)0xc8dac8cd, (q31_t)0x60703275, (q31_t)0xc8d46936,
+    (q31_t)0x60655cac, (q31_t)0xc8ce0bc0, (q31_t)0x605a85a3, (q31_t)0xc8c7b06b,
+    (q31_t)0x604fad5b, (q31_t)0xc8c15736, (q31_t)0x6044d3d4, (q31_t)0xc8bb0023,
+    (q31_t)0x6039f90f, (q31_t)0xc8b4ab32, (q31_t)0x602f1d0b, (q31_t)0xc8ae5862,
+    (q31_t)0x60243fca, (q31_t)0xc8a807b4, (q31_t)0x6019614c, (q31_t)0xc8a1b928,
+    (q31_t)0x600e8190, (q31_t)0xc89b6cbf, (q31_t)0x6003a099, (q31_t)0xc8952278,
+    (q31_t)0x5ff8be65, (q31_t)0xc88eda54, (q31_t)0x5feddaf6, (q31_t)0xc8889454,
+    (q31_t)0x5fe2f64c, (q31_t)0xc8825077, (q31_t)0x5fd81067, (q31_t)0xc87c0ebd,
+    (q31_t)0x5fcd2948, (q31_t)0xc875cf28, (q31_t)0x5fc240ef, (q31_t)0xc86f91b7,
+    (q31_t)0x5fb7575c, (q31_t)0xc869566a, (q31_t)0x5fac6c91, (q31_t)0xc8631d42,
+    (q31_t)0x5fa1808c, (q31_t)0xc85ce63e, (q31_t)0x5f969350, (q31_t)0xc856b160,
+    (q31_t)0x5f8ba4dc, (q31_t)0xc8507ea7, (q31_t)0x5f80b531, (q31_t)0xc84a4e14,
+    (q31_t)0x5f75c44e, (q31_t)0xc8441fa6, (q31_t)0x5f6ad235, (q31_t)0xc83df35f,
+    (q31_t)0x5f5fdee6, (q31_t)0xc837c93e, (q31_t)0x5f54ea62, (q31_t)0xc831a143,
+    (q31_t)0x5f49f4a8, (q31_t)0xc82b7b70, (q31_t)0x5f3efdb9, (q31_t)0xc82557c3,
+    (q31_t)0x5f340596, (q31_t)0xc81f363d, (q31_t)0x5f290c3f, (q31_t)0xc81916df,
+    (q31_t)0x5f1e11b5, (q31_t)0xc812f9a9, (q31_t)0x5f1315f7, (q31_t)0xc80cde9b,
+    (q31_t)0x5f081907, (q31_t)0xc806c5b5, (q31_t)0x5efd1ae4, (q31_t)0xc800aef7,
+    (q31_t)0x5ef21b90, (q31_t)0xc7fa9a62, (q31_t)0x5ee71b0a, (q31_t)0xc7f487f6,
+    (q31_t)0x5edc1953, (q31_t)0xc7ee77b3, (q31_t)0x5ed1166b, (q31_t)0xc7e8699a,
+    (q31_t)0x5ec61254, (q31_t)0xc7e25daa, (q31_t)0x5ebb0d0d, (q31_t)0xc7dc53e3,
+    (q31_t)0x5eb00696, (q31_t)0xc7d64c47, (q31_t)0x5ea4fef0, (q31_t)0xc7d046d6,
+    (q31_t)0x5e99f61d, (q31_t)0xc7ca438f, (q31_t)0x5e8eec1b, (q31_t)0xc7c44272,
+    (q31_t)0x5e83e0eb, (q31_t)0xc7be4381, (q31_t)0x5e78d48e, (q31_t)0xc7b846ba,
+    (q31_t)0x5e6dc705, (q31_t)0xc7b24c20, (q31_t)0x5e62b84f, (q31_t)0xc7ac53b1,
+    (q31_t)0x5e57a86d, (q31_t)0xc7a65d6e, (q31_t)0x5e4c9760, (q31_t)0xc7a06957,
+    (q31_t)0x5e418528, (q31_t)0xc79a776c, (q31_t)0x5e3671c5, (q31_t)0xc79487ae,
+    (q31_t)0x5e2b5d38, (q31_t)0xc78e9a1d, (q31_t)0x5e204781, (q31_t)0xc788aeb9,
+    (q31_t)0x5e1530a1, (q31_t)0xc782c582, (q31_t)0x5e0a1898, (q31_t)0xc77cde79,
+    (q31_t)0x5dfeff67, (q31_t)0xc776f99d, (q31_t)0x5df3e50d, (q31_t)0xc77116f0,
+    (q31_t)0x5de8c98c, (q31_t)0xc76b3671, (q31_t)0x5dddace4, (q31_t)0xc7655820,
+    (q31_t)0x5dd28f15, (q31_t)0xc75f7bfe, (q31_t)0x5dc7701f, (q31_t)0xc759a20a,
+    (q31_t)0x5dbc5004, (q31_t)0xc753ca46, (q31_t)0x5db12ec3, (q31_t)0xc74df4b1,
+    (q31_t)0x5da60c5d, (q31_t)0xc748214c, (q31_t)0x5d9ae8d2, (q31_t)0xc7425016,
+    (q31_t)0x5d8fc424, (q31_t)0xc73c8111, (q31_t)0x5d849e51, (q31_t)0xc736b43c,
+    (q31_t)0x5d79775c, (q31_t)0xc730e997, (q31_t)0x5d6e4f43, (q31_t)0xc72b2123,
+    (q31_t)0x5d632608, (q31_t)0xc7255ae0, (q31_t)0x5d57fbaa, (q31_t)0xc71f96ce,
+    (q31_t)0x5d4cd02c, (q31_t)0xc719d4ed, (q31_t)0x5d41a38c, (q31_t)0xc714153e,
+    (q31_t)0x5d3675cb, (q31_t)0xc70e57c0, (q31_t)0x5d2b46ea, (q31_t)0xc7089c75,
+    (q31_t)0x5d2016e9, (q31_t)0xc702e35c, (q31_t)0x5d14e5c9, (q31_t)0xc6fd2c75,
+    (q31_t)0x5d09b389, (q31_t)0xc6f777c1, (q31_t)0x5cfe802b, (q31_t)0xc6f1c540,
+    (q31_t)0x5cf34baf, (q31_t)0xc6ec14f2, (q31_t)0x5ce81615, (q31_t)0xc6e666d7,
+    (q31_t)0x5cdcdf5e, (q31_t)0xc6e0baf0, (q31_t)0x5cd1a78a, (q31_t)0xc6db113d,
+    (q31_t)0x5cc66e99, (q31_t)0xc6d569be, (q31_t)0x5cbb348d, (q31_t)0xc6cfc472,
+    (q31_t)0x5caff965, (q31_t)0xc6ca215c, (q31_t)0x5ca4bd21, (q31_t)0xc6c4807a,
+    (q31_t)0x5c997fc4, (q31_t)0xc6bee1cd, (q31_t)0x5c8e414b, (q31_t)0xc6b94554,
+    (q31_t)0x5c8301b9, (q31_t)0xc6b3ab12, (q31_t)0x5c77c10e, (q31_t)0xc6ae1304,
+    (q31_t)0x5c6c7f4a, (q31_t)0xc6a87d2d, (q31_t)0x5c613c6d, (q31_t)0xc6a2e98b,
+    (q31_t)0x5c55f878, (q31_t)0xc69d5820, (q31_t)0x5c4ab36b, (q31_t)0xc697c8eb,
+    (q31_t)0x5c3f6d47, (q31_t)0xc6923bec, (q31_t)0x5c34260c, (q31_t)0xc68cb124,
+    (q31_t)0x5c28ddbb, (q31_t)0xc6872894, (q31_t)0x5c1d9454, (q31_t)0xc681a23a,
+    (q31_t)0x5c1249d8, (q31_t)0xc67c1e18, (q31_t)0x5c06fe46, (q31_t)0xc6769c2e,
+    (q31_t)0x5bfbb1a0, (q31_t)0xc6711c7b, (q31_t)0x5bf063e6, (q31_t)0xc66b9f01,
+    (q31_t)0x5be51518, (q31_t)0xc66623be, (q31_t)0x5bd9c537, (q31_t)0xc660aab5,
+    (q31_t)0x5bce7442, (q31_t)0xc65b33e4, (q31_t)0x5bc3223c, (q31_t)0xc655bf4c,
+    (q31_t)0x5bb7cf23, (q31_t)0xc6504ced, (q31_t)0x5bac7af9, (q31_t)0xc64adcc7,
+    (q31_t)0x5ba125bd, (q31_t)0xc6456edb, (q31_t)0x5b95cf71, (q31_t)0xc6400329,
+    (q31_t)0x5b8a7815, (q31_t)0xc63a99b1, (q31_t)0x5b7f1fa9, (q31_t)0xc6353273,
+    (q31_t)0x5b73c62d, (q31_t)0xc62fcd6f, (q31_t)0x5b686ba3, (q31_t)0xc62a6aa6,
+    (q31_t)0x5b5d100a, (q31_t)0xc6250a18, (q31_t)0x5b51b363, (q31_t)0xc61fabc4,
+    (q31_t)0x5b4655ae, (q31_t)0xc61a4fac, (q31_t)0x5b3af6ec, (q31_t)0xc614f5cf,
+    (q31_t)0x5b2f971e, (q31_t)0xc60f9e2e, (q31_t)0x5b243643, (q31_t)0xc60a48c9,
+    (q31_t)0x5b18d45c, (q31_t)0xc604f5a0, (q31_t)0x5b0d716a, (q31_t)0xc5ffa4b3,
+    (q31_t)0x5b020d6c, (q31_t)0xc5fa5603, (q31_t)0x5af6a865, (q31_t)0xc5f5098f,
+    (q31_t)0x5aeb4253, (q31_t)0xc5efbf58, (q31_t)0x5adfdb37, (q31_t)0xc5ea775e,
+    (q31_t)0x5ad47312, (q31_t)0xc5e531a1, (q31_t)0x5ac909e5, (q31_t)0xc5dfee22,
+    (q31_t)0x5abd9faf, (q31_t)0xc5daace1, (q31_t)0x5ab23471, (q31_t)0xc5d56ddd,
+    (q31_t)0x5aa6c82b, (q31_t)0xc5d03118, (q31_t)0x5a9b5adf, (q31_t)0xc5caf690,
+    (q31_t)0x5a8fec8c, (q31_t)0xc5c5be47, (q31_t)0x5a847d33, (q31_t)0xc5c0883d,
+    (q31_t)0x5a790cd4, (q31_t)0xc5bb5472, (q31_t)0x5a6d9b70, (q31_t)0xc5b622e6,
+    (q31_t)0x5a622907, (q31_t)0xc5b0f399, (q31_t)0x5a56b599, (q31_t)0xc5abc68c,
+    (q31_t)0x5a4b4128, (q31_t)0xc5a69bbe, (q31_t)0x5a3fcbb3, (q31_t)0xc5a17330,
+    (q31_t)0x5a34553b, (q31_t)0xc59c4ce3, (q31_t)0x5a28ddc0, (q31_t)0xc59728d5,
+    (q31_t)0x5a1d6544, (q31_t)0xc5920708, (q31_t)0x5a11ebc5, (q31_t)0xc58ce77c,
+    (q31_t)0x5a067145, (q31_t)0xc587ca31, (q31_t)0x59faf5c5, (q31_t)0xc582af26,
+    (q31_t)0x59ef7944, (q31_t)0xc57d965d, (q31_t)0x59e3fbc3, (q31_t)0xc5787fd6,
+    (q31_t)0x59d87d42, (q31_t)0xc5736b90, (q31_t)0x59ccfdc2, (q31_t)0xc56e598c,
+    (q31_t)0x59c17d44, (q31_t)0xc56949ca, (q31_t)0x59b5fbc8, (q31_t)0xc5643c4a,
+    (q31_t)0x59aa794d, (q31_t)0xc55f310d, (q31_t)0x599ef5d6, (q31_t)0xc55a2812,
+    (q31_t)0x59937161, (q31_t)0xc555215a, (q31_t)0x5987ebf0, (q31_t)0xc5501ce5,
+    (q31_t)0x597c6584, (q31_t)0xc54b1ab4, (q31_t)0x5970de1b, (q31_t)0xc5461ac6,
+    (q31_t)0x596555b8, (q31_t)0xc5411d1b, (q31_t)0x5959cc5a, (q31_t)0xc53c21b4,
+    (q31_t)0x594e4201, (q31_t)0xc5372891, (q31_t)0x5942b6af, (q31_t)0xc53231b3,
+    (q31_t)0x59372a64, (q31_t)0xc52d3d18, (q31_t)0x592b9d1f, (q31_t)0xc5284ac3,
+    (q31_t)0x59200ee3, (q31_t)0xc5235ab2, (q31_t)0x59147fae, (q31_t)0xc51e6ce6,
+    (q31_t)0x5908ef82, (q31_t)0xc519815f, (q31_t)0x58fd5e5f, (q31_t)0xc514981d,
+    (q31_t)0x58f1cc45, (q31_t)0xc50fb121, (q31_t)0x58e63935, (q31_t)0xc50acc6b,
+    (q31_t)0x58daa52f, (q31_t)0xc505e9fb, (q31_t)0x58cf1034, (q31_t)0xc50109d0,
+    (q31_t)0x58c37a44, (q31_t)0xc4fc2bec, (q31_t)0x58b7e35f, (q31_t)0xc4f7504e,
+    (q31_t)0x58ac4b87, (q31_t)0xc4f276f7, (q31_t)0x58a0b2bb, (q31_t)0xc4ed9fe7,
+    (q31_t)0x589518fc, (q31_t)0xc4e8cb1e, (q31_t)0x58897e4a, (q31_t)0xc4e3f89c,
+    (q31_t)0x587de2a7, (q31_t)0xc4df2862, (q31_t)0x58724611, (q31_t)0xc4da5a6f,
+    (q31_t)0x5866a88a, (q31_t)0xc4d58ec3, (q31_t)0x585b0a13, (q31_t)0xc4d0c560,
+    (q31_t)0x584f6aab, (q31_t)0xc4cbfe45, (q31_t)0x5843ca53, (q31_t)0xc4c73972,
+    (q31_t)0x5838290c, (q31_t)0xc4c276e8, (q31_t)0x582c86d5, (q31_t)0xc4bdb6a6,
+    (q31_t)0x5820e3b0, (q31_t)0xc4b8f8ad, (q31_t)0x58153f9d, (q31_t)0xc4b43cfd,
+    (q31_t)0x58099a9c, (q31_t)0xc4af8397, (q31_t)0x57fdf4ae, (q31_t)0xc4aacc7a,
+    (q31_t)0x57f24dd3, (q31_t)0xc4a617a6, (q31_t)0x57e6a60c, (q31_t)0xc4a1651c,
+    (q31_t)0x57dafd59, (q31_t)0xc49cb4dd, (q31_t)0x57cf53bb, (q31_t)0xc49806e7,
+    (q31_t)0x57c3a931, (q31_t)0xc4935b3c, (q31_t)0x57b7fdbd, (q31_t)0xc48eb1db,
+    (q31_t)0x57ac515f, (q31_t)0xc48a0ac4, (q31_t)0x57a0a417, (q31_t)0xc48565f9,
+    (q31_t)0x5794f5e6, (q31_t)0xc480c379, (q31_t)0x578946cc, (q31_t)0xc47c2344,
+    (q31_t)0x577d96ca, (q31_t)0xc477855a, (q31_t)0x5771e5e0, (q31_t)0xc472e9bc,
+    (q31_t)0x5766340f, (q31_t)0xc46e5069, (q31_t)0x575a8157, (q31_t)0xc469b963,
+    (q31_t)0x574ecdb8, (q31_t)0xc46524a9, (q31_t)0x57431933, (q31_t)0xc460923b,
+    (q31_t)0x573763c9, (q31_t)0xc45c0219, (q31_t)0x572bad7a, (q31_t)0xc4577444,
+    (q31_t)0x571ff646, (q31_t)0xc452e8bc, (q31_t)0x57143e2d, (q31_t)0xc44e5f80,
+    (q31_t)0x57088531, (q31_t)0xc449d892, (q31_t)0x56fccb51, (q31_t)0xc44553f2,
+    (q31_t)0x56f1108f, (q31_t)0xc440d19e, (q31_t)0x56e554ea, (q31_t)0xc43c5199,
+    (q31_t)0x56d99864, (q31_t)0xc437d3e1, (q31_t)0x56cddafb, (q31_t)0xc4335877,
+    (q31_t)0x56c21cb2, (q31_t)0xc42edf5c, (q31_t)0x56b65d88, (q31_t)0xc42a688f,
+    (q31_t)0x56aa9d7e, (q31_t)0xc425f410, (q31_t)0x569edc94, (q31_t)0xc42181e0,
+    (q31_t)0x56931acb, (q31_t)0xc41d11ff, (q31_t)0x56875823, (q31_t)0xc418a46d,
+    (q31_t)0x567b949d, (q31_t)0xc414392b, (q31_t)0x566fd039, (q31_t)0xc40fd037,
+    (q31_t)0x56640af7, (q31_t)0xc40b6994, (q31_t)0x565844d8, (q31_t)0xc4070540,
+    (q31_t)0x564c7ddd, (q31_t)0xc402a33c, (q31_t)0x5640b606, (q31_t)0xc3fe4388,
+    (q31_t)0x5634ed53, (q31_t)0xc3f9e624, (q31_t)0x562923c5, (q31_t)0xc3f58b10,
+    (q31_t)0x561d595d, (q31_t)0xc3f1324e, (q31_t)0x56118e1a, (q31_t)0xc3ecdbdc,
+    (q31_t)0x5605c1fd, (q31_t)0xc3e887bb, (q31_t)0x55f9f507, (q31_t)0xc3e435ea,
+    (q31_t)0x55ee2738, (q31_t)0xc3dfe66c, (q31_t)0x55e25890, (q31_t)0xc3db993e,
+    (q31_t)0x55d68911, (q31_t)0xc3d74e62, (q31_t)0x55cab8ba, (q31_t)0xc3d305d8,
+    (q31_t)0x55bee78c, (q31_t)0xc3cebfa0, (q31_t)0x55b31587, (q31_t)0xc3ca7bba,
+    (q31_t)0x55a742ac, (q31_t)0xc3c63a26, (q31_t)0x559b6efb, (q31_t)0xc3c1fae5,
+    (q31_t)0x558f9a76, (q31_t)0xc3bdbdf6, (q31_t)0x5583c51b, (q31_t)0xc3b9835a,
+    (q31_t)0x5577eeec, (q31_t)0xc3b54b11, (q31_t)0x556c17e9, (q31_t)0xc3b1151b,
+    (q31_t)0x55604013, (q31_t)0xc3ace178, (q31_t)0x5554676a, (q31_t)0xc3a8b028,
+    (q31_t)0x55488dee, (q31_t)0xc3a4812c, (q31_t)0x553cb3a0, (q31_t)0xc3a05484,
+    (q31_t)0x5530d881, (q31_t)0xc39c2a2f, (q31_t)0x5524fc90, (q31_t)0xc398022f,
+    (q31_t)0x55191fcf, (q31_t)0xc393dc82, (q31_t)0x550d423d, (q31_t)0xc38fb92a,
+    (q31_t)0x550163dc, (q31_t)0xc38b9827, (q31_t)0x54f584ac, (q31_t)0xc3877978,
+    (q31_t)0x54e9a4ac, (q31_t)0xc3835d1e, (q31_t)0x54ddc3de, (q31_t)0xc37f4319,
+    (q31_t)0x54d1e242, (q31_t)0xc37b2b6a, (q31_t)0x54c5ffd9, (q31_t)0xc377160f,
+    (q31_t)0x54ba1ca3, (q31_t)0xc373030a, (q31_t)0x54ae38a0, (q31_t)0xc36ef25b,
+    (q31_t)0x54a253d1, (q31_t)0xc36ae401, (q31_t)0x54966e36, (q31_t)0xc366d7fd,
+    (q31_t)0x548a87d1, (q31_t)0xc362ce50, (q31_t)0x547ea0a0, (q31_t)0xc35ec6f8,
+    (q31_t)0x5472b8a5, (q31_t)0xc35ac1f7, (q31_t)0x5466cfe1, (q31_t)0xc356bf4d,
+    (q31_t)0x545ae653, (q31_t)0xc352bef9, (q31_t)0x544efbfc, (q31_t)0xc34ec0fc,
+    (q31_t)0x544310dd, (q31_t)0xc34ac556, (q31_t)0x543724f5, (q31_t)0xc346cc07,
+    (q31_t)0x542b3846, (q31_t)0xc342d510, (q31_t)0x541f4ad1, (q31_t)0xc33ee070,
+    (q31_t)0x54135c94, (q31_t)0xc33aee27, (q31_t)0x54076d91, (q31_t)0xc336fe37,
+    (q31_t)0x53fb7dc9, (q31_t)0xc333109e, (q31_t)0x53ef8d3c, (q31_t)0xc32f255e,
+    (q31_t)0x53e39be9, (q31_t)0xc32b3c75, (q31_t)0x53d7a9d3, (q31_t)0xc32755e5,
+    (q31_t)0x53cbb6f8, (q31_t)0xc32371ae, (q31_t)0x53bfc35b, (q31_t)0xc31f8fcf,
+    (q31_t)0x53b3cefa, (q31_t)0xc31bb049, (q31_t)0x53a7d9d7, (q31_t)0xc317d31c,
+    (q31_t)0x539be3f2, (q31_t)0xc313f848, (q31_t)0x538fed4b, (q31_t)0xc3101fce,
+    (q31_t)0x5383f5e3, (q31_t)0xc30c49ad, (q31_t)0x5377fdbb, (q31_t)0xc30875e5,
+    (q31_t)0x536c04d2, (q31_t)0xc304a477, (q31_t)0x53600b2a, (q31_t)0xc300d563,
+    (q31_t)0x535410c3, (q31_t)0xc2fd08a9, (q31_t)0x5348159d, (q31_t)0xc2f93e4a,
+    (q31_t)0x533c19b8, (q31_t)0xc2f57644, (q31_t)0x53301d16, (q31_t)0xc2f1b099,
+    (q31_t)0x53241fb6, (q31_t)0xc2eded49, (q31_t)0x5318219a, (q31_t)0xc2ea2c53,
+    (q31_t)0x530c22c1, (q31_t)0xc2e66db8, (q31_t)0x5300232c, (q31_t)0xc2e2b178,
+    (q31_t)0x52f422db, (q31_t)0xc2def794, (q31_t)0x52e821cf, (q31_t)0xc2db400a,
+    (q31_t)0x52dc2009, (q31_t)0xc2d78add, (q31_t)0x52d01d89, (q31_t)0xc2d3d80a,
+    (q31_t)0x52c41a4f, (q31_t)0xc2d02794, (q31_t)0x52b8165b, (q31_t)0xc2cc7979,
+    (q31_t)0x52ac11af, (q31_t)0xc2c8cdbb, (q31_t)0x52a00c4b, (q31_t)0xc2c52459,
+    (q31_t)0x5294062f, (q31_t)0xc2c17d52, (q31_t)0x5287ff5b, (q31_t)0xc2bdd8a9,
+    (q31_t)0x527bf7d1, (q31_t)0xc2ba365c, (q31_t)0x526fef90, (q31_t)0xc2b6966c,
+    (q31_t)0x5263e699, (q31_t)0xc2b2f8d8, (q31_t)0x5257dced, (q31_t)0xc2af5da2,
+    (q31_t)0x524bd28c, (q31_t)0xc2abc4c9, (q31_t)0x523fc776, (q31_t)0xc2a82e4d,
+    (q31_t)0x5233bbac, (q31_t)0xc2a49a2e, (q31_t)0x5227af2e, (q31_t)0xc2a1086d,
+    (q31_t)0x521ba1fd, (q31_t)0xc29d790a, (q31_t)0x520f941a, (q31_t)0xc299ec05,
+    (q31_t)0x52038584, (q31_t)0xc296615d, (q31_t)0x51f7763c, (q31_t)0xc292d914,
+    (q31_t)0x51eb6643, (q31_t)0xc28f5329, (q31_t)0x51df5599, (q31_t)0xc28bcf9c,
+    (q31_t)0x51d3443f, (q31_t)0xc2884e6e, (q31_t)0x51c73235, (q31_t)0xc284cf9f,
+    (q31_t)0x51bb1f7c, (q31_t)0xc281532e, (q31_t)0x51af0c13, (q31_t)0xc27dd91c,
+    (q31_t)0x51a2f7fc, (q31_t)0xc27a616a, (q31_t)0x5196e337, (q31_t)0xc276ec16,
+    (q31_t)0x518acdc4, (q31_t)0xc2737922, (q31_t)0x517eb7a4, (q31_t)0xc270088e,
+    (q31_t)0x5172a0d7, (q31_t)0xc26c9a58, (q31_t)0x5166895f, (q31_t)0xc2692e83,
+    (q31_t)0x515a713a, (q31_t)0xc265c50e, (q31_t)0x514e586a, (q31_t)0xc2625df8,
+    (q31_t)0x51423ef0, (q31_t)0xc25ef943, (q31_t)0x513624cb, (q31_t)0xc25b96ee,
+    (q31_t)0x512a09fc, (q31_t)0xc25836f9, (q31_t)0x511dee84, (q31_t)0xc254d965,
+    (q31_t)0x5111d263, (q31_t)0xc2517e31, (q31_t)0x5105b599, (q31_t)0xc24e255e,
+    (q31_t)0x50f99827, (q31_t)0xc24aceed, (q31_t)0x50ed7a0e, (q31_t)0xc2477adc,
+    (q31_t)0x50e15b4e, (q31_t)0xc244292c, (q31_t)0x50d53be7, (q31_t)0xc240d9de,
+    (q31_t)0x50c91bda, (q31_t)0xc23d8cf1, (q31_t)0x50bcfb28, (q31_t)0xc23a4265,
+    (q31_t)0x50b0d9d0, (q31_t)0xc236fa3b, (q31_t)0x50a4b7d3, (q31_t)0xc233b473,
+    (q31_t)0x50989532, (q31_t)0xc230710d, (q31_t)0x508c71ee, (q31_t)0xc22d3009,
+    (q31_t)0x50804e06, (q31_t)0xc229f167, (q31_t)0x5074297b, (q31_t)0xc226b528,
+    (q31_t)0x5068044e, (q31_t)0xc2237b4b, (q31_t)0x505bde7f, (q31_t)0xc22043d0,
+    (q31_t)0x504fb80e, (q31_t)0xc21d0eb8, (q31_t)0x504390fd, (q31_t)0xc219dc03,
+    (q31_t)0x5037694b, (q31_t)0xc216abb1, (q31_t)0x502b40f8, (q31_t)0xc2137dc2,
+    (q31_t)0x501f1807, (q31_t)0xc2105236, (q31_t)0x5012ee76, (q31_t)0xc20d290d,
+    (q31_t)0x5006c446, (q31_t)0xc20a0248, (q31_t)0x4ffa9979, (q31_t)0xc206dde6,
+    (q31_t)0x4fee6e0d, (q31_t)0xc203bbe8, (q31_t)0x4fe24205, (q31_t)0xc2009c4e,
+    (q31_t)0x4fd6155f, (q31_t)0xc1fd7f17, (q31_t)0x4fc9e81e, (q31_t)0xc1fa6445,
+    (q31_t)0x4fbdba40, (q31_t)0xc1f74bd6, (q31_t)0x4fb18bc8, (q31_t)0xc1f435cc,
+    (q31_t)0x4fa55cb4, (q31_t)0xc1f12227, (q31_t)0x4f992d06, (q31_t)0xc1ee10e5,
+    (q31_t)0x4f8cfcbe, (q31_t)0xc1eb0209, (q31_t)0x4f80cbdc, (q31_t)0xc1e7f591,
+    (q31_t)0x4f749a61, (q31_t)0xc1e4eb7e, (q31_t)0x4f68684e, (q31_t)0xc1e1e3d0,
+    (q31_t)0x4f5c35a3, (q31_t)0xc1dede87, (q31_t)0x4f500260, (q31_t)0xc1dbdba3,
+    (q31_t)0x4f43ce86, (q31_t)0xc1d8db25, (q31_t)0x4f379a16, (q31_t)0xc1d5dd0c,
+    (q31_t)0x4f2b650f, (q31_t)0xc1d2e158, (q31_t)0x4f1f2f73, (q31_t)0xc1cfe80a,
+    (q31_t)0x4f12f941, (q31_t)0xc1ccf122, (q31_t)0x4f06c27a, (q31_t)0xc1c9fca0,
+    (q31_t)0x4efa8b20, (q31_t)0xc1c70a84, (q31_t)0x4eee5331, (q31_t)0xc1c41ace,
+    (q31_t)0x4ee21aaf, (q31_t)0xc1c12d7e, (q31_t)0x4ed5e19a, (q31_t)0xc1be4294,
+    (q31_t)0x4ec9a7f3, (q31_t)0xc1bb5a11, (q31_t)0x4ebd6db9, (q31_t)0xc1b873f5,
+    (q31_t)0x4eb132ef, (q31_t)0xc1b5903f, (q31_t)0x4ea4f793, (q31_t)0xc1b2aef0,
+    (q31_t)0x4e98bba7, (q31_t)0xc1afd007, (q31_t)0x4e8c7f2a, (q31_t)0xc1acf386,
+    (q31_t)0x4e80421e, (q31_t)0xc1aa196c, (q31_t)0x4e740483, (q31_t)0xc1a741b9,
+    (q31_t)0x4e67c65a, (q31_t)0xc1a46c6e, (q31_t)0x4e5b87a2, (q31_t)0xc1a1998a,
+    (q31_t)0x4e4f485c, (q31_t)0xc19ec90d, (q31_t)0x4e430889, (q31_t)0xc19bfaf9,
+    (q31_t)0x4e36c82a, (q31_t)0xc1992f4c, (q31_t)0x4e2a873e, (q31_t)0xc1966606,
+    (q31_t)0x4e1e45c6, (q31_t)0xc1939f29, (q31_t)0x4e1203c3, (q31_t)0xc190dab4,
+    (q31_t)0x4e05c135, (q31_t)0xc18e18a7, (q31_t)0x4df97e1d, (q31_t)0xc18b5903,
+    (q31_t)0x4ded3a7b, (q31_t)0xc1889bc6, (q31_t)0x4de0f64f, (q31_t)0xc185e0f3,
+    (q31_t)0x4dd4b19a, (q31_t)0xc1832888, (q31_t)0x4dc86c5d, (q31_t)0xc1807285,
+    (q31_t)0x4dbc2698, (q31_t)0xc17dbeec, (q31_t)0x4dafe04b, (q31_t)0xc17b0dbb,
+    (q31_t)0x4da39978, (q31_t)0xc1785ef4, (q31_t)0x4d97521d, (q31_t)0xc175b296,
+    (q31_t)0x4d8b0a3d, (q31_t)0xc17308a1, (q31_t)0x4d7ec1d6, (q31_t)0xc1706115,
+    (q31_t)0x4d7278eb, (q31_t)0xc16dbbf3, (q31_t)0x4d662f7b, (q31_t)0xc16b193a,
+    (q31_t)0x4d59e586, (q31_t)0xc16878eb, (q31_t)0x4d4d9b0e, (q31_t)0xc165db05,
+    (q31_t)0x4d415013, (q31_t)0xc1633f8a, (q31_t)0x4d350495, (q31_t)0xc160a678,
+    (q31_t)0x4d28b894, (q31_t)0xc15e0fd1, (q31_t)0x4d1c6c11, (q31_t)0xc15b7b94,
+    (q31_t)0x4d101f0e, (q31_t)0xc158e9c1, (q31_t)0x4d03d189, (q31_t)0xc1565a58,
+    (q31_t)0x4cf78383, (q31_t)0xc153cd5a, (q31_t)0x4ceb34fe, (q31_t)0xc15142c6,
+    (q31_t)0x4cdee5f9, (q31_t)0xc14eba9d, (q31_t)0x4cd29676, (q31_t)0xc14c34df,
+    (q31_t)0x4cc64673, (q31_t)0xc149b18b, (q31_t)0x4cb9f5f3, (q31_t)0xc14730a3,
+    (q31_t)0x4cada4f5, (q31_t)0xc144b225, (q31_t)0x4ca1537a, (q31_t)0xc1423613,
+    (q31_t)0x4c950182, (q31_t)0xc13fbc6c, (q31_t)0x4c88af0e, (q31_t)0xc13d4530,
+    (q31_t)0x4c7c5c1e, (q31_t)0xc13ad060, (q31_t)0x4c7008b3, (q31_t)0xc1385dfb,
+    (q31_t)0x4c63b4ce, (q31_t)0xc135ee02, (q31_t)0x4c57606e, (q31_t)0xc1338075,
+    (q31_t)0x4c4b0b94, (q31_t)0xc1311553, (q31_t)0x4c3eb641, (q31_t)0xc12eac9d,
+    (q31_t)0x4c326075, (q31_t)0xc12c4653, (q31_t)0x4c260a31, (q31_t)0xc129e276,
+    (q31_t)0x4c19b374, (q31_t)0xc1278104, (q31_t)0x4c0d5c41, (q31_t)0xc12521ff,
+    (q31_t)0x4c010496, (q31_t)0xc122c566, (q31_t)0x4bf4ac75, (q31_t)0xc1206b39,
+    (q31_t)0x4be853de, (q31_t)0xc11e1379, (q31_t)0x4bdbfad1, (q31_t)0xc11bbe26,
+    (q31_t)0x4bcfa150, (q31_t)0xc1196b3f, (q31_t)0x4bc34759, (q31_t)0xc1171ac6,
+    (q31_t)0x4bb6ecef, (q31_t)0xc114ccb9, (q31_t)0x4baa9211, (q31_t)0xc1128119,
+    (q31_t)0x4b9e36c0, (q31_t)0xc11037e6, (q31_t)0x4b91dafc, (q31_t)0xc10df120,
+    (q31_t)0x4b857ec7, (q31_t)0xc10bacc8, (q31_t)0x4b79221f, (q31_t)0xc1096add,
+    (q31_t)0x4b6cc506, (q31_t)0xc1072b5f, (q31_t)0x4b60677c, (q31_t)0xc104ee4f,
+    (q31_t)0x4b540982, (q31_t)0xc102b3ac, (q31_t)0x4b47ab19, (q31_t)0xc1007b77,
+    (q31_t)0x4b3b4c40, (q31_t)0xc0fe45b0, (q31_t)0x4b2eecf8, (q31_t)0xc0fc1257,
+    (q31_t)0x4b228d42, (q31_t)0xc0f9e16b, (q31_t)0x4b162d1d, (q31_t)0xc0f7b2ee,
+    (q31_t)0x4b09cc8c, (q31_t)0xc0f586df, (q31_t)0x4afd6b8d, (q31_t)0xc0f35d3e,
+    (q31_t)0x4af10a22, (q31_t)0xc0f1360b, (q31_t)0x4ae4a84b, (q31_t)0xc0ef1147,
+    (q31_t)0x4ad84609, (q31_t)0xc0eceef1, (q31_t)0x4acbe35b, (q31_t)0xc0eacf09,
+    (q31_t)0x4abf8043, (q31_t)0xc0e8b190, (q31_t)0x4ab31cc1, (q31_t)0xc0e69686,
+    (q31_t)0x4aa6b8d5, (q31_t)0xc0e47deb, (q31_t)0x4a9a5480, (q31_t)0xc0e267be,
+    (q31_t)0x4a8defc3, (q31_t)0xc0e05401, (q31_t)0x4a818a9d, (q31_t)0xc0de42b2,
+    (q31_t)0x4a752510, (q31_t)0xc0dc33d2, (q31_t)0x4a68bf1b, (q31_t)0xc0da2762,
+    (q31_t)0x4a5c58c0, (q31_t)0xc0d81d61, (q31_t)0x4a4ff1fe, (q31_t)0xc0d615cf,
+    (q31_t)0x4a438ad7, (q31_t)0xc0d410ad, (q31_t)0x4a37234a, (q31_t)0xc0d20dfa,
+    (q31_t)0x4a2abb59, (q31_t)0xc0d00db6, (q31_t)0x4a1e5303, (q31_t)0xc0ce0fe3,
+    (q31_t)0x4a11ea49, (q31_t)0xc0cc147f, (q31_t)0x4a05812c, (q31_t)0xc0ca1b8a,
+    (q31_t)0x49f917ac, (q31_t)0xc0c82506, (q31_t)0x49ecadc9, (q31_t)0xc0c630f2,
+    (q31_t)0x49e04385, (q31_t)0xc0c43f4d, (q31_t)0x49d3d8df, (q31_t)0xc0c25019,
+    (q31_t)0x49c76dd8, (q31_t)0xc0c06355, (q31_t)0x49bb0271, (q31_t)0xc0be7901,
+    (q31_t)0x49ae96aa, (q31_t)0xc0bc911d, (q31_t)0x49a22a83, (q31_t)0xc0baabaa,
+    (q31_t)0x4995bdfd, (q31_t)0xc0b8c8a7, (q31_t)0x49895118, (q31_t)0xc0b6e815,
+    (q31_t)0x497ce3d5, (q31_t)0xc0b509f3, (q31_t)0x49707635, (q31_t)0xc0b32e42,
+    (q31_t)0x49640837, (q31_t)0xc0b15502, (q31_t)0x495799dd, (q31_t)0xc0af7e33,
+    (q31_t)0x494b2b27, (q31_t)0xc0ada9d4, (q31_t)0x493ebc14, (q31_t)0xc0abd7e6,
+    (q31_t)0x49324ca7, (q31_t)0xc0aa086a, (q31_t)0x4925dcdf, (q31_t)0xc0a83b5e,
+    (q31_t)0x49196cbc, (q31_t)0xc0a670c4, (q31_t)0x490cfc40, (q31_t)0xc0a4a89b,
+    (q31_t)0x49008b6a, (q31_t)0xc0a2e2e3, (q31_t)0x48f41a3c, (q31_t)0xc0a11f9d,
+    (q31_t)0x48e7a8b5, (q31_t)0xc09f5ec8, (q31_t)0x48db36d6, (q31_t)0xc09da065,
+    (q31_t)0x48cec4a0, (q31_t)0xc09be473, (q31_t)0x48c25213, (q31_t)0xc09a2af3,
+    (q31_t)0x48b5df30, (q31_t)0xc09873e4, (q31_t)0x48a96bf6, (q31_t)0xc096bf48,
+    (q31_t)0x489cf867, (q31_t)0xc0950d1d, (q31_t)0x48908483, (q31_t)0xc0935d64,
+    (q31_t)0x4884104b, (q31_t)0xc091b01d, (q31_t)0x48779bbe, (q31_t)0xc0900548,
+    (q31_t)0x486b26de, (q31_t)0xc08e5ce5, (q31_t)0x485eb1ab, (q31_t)0xc08cb6f5,
+    (q31_t)0x48523c25, (q31_t)0xc08b1376, (q31_t)0x4845c64d, (q31_t)0xc089726a,
+    (q31_t)0x48395024, (q31_t)0xc087d3d0, (q31_t)0x482cd9a9, (q31_t)0xc08637a9,
+    (q31_t)0x482062de, (q31_t)0xc0849df4, (q31_t)0x4813ebc2, (q31_t)0xc08306b2,
+    (q31_t)0x48077457, (q31_t)0xc08171e2, (q31_t)0x47fafc9c, (q31_t)0xc07fdf85,
+    (q31_t)0x47ee8493, (q31_t)0xc07e4f9b, (q31_t)0x47e20c3b, (q31_t)0xc07cc223,
+    (q31_t)0x47d59396, (q31_t)0xc07b371e, (q31_t)0x47c91aa3, (q31_t)0xc079ae8c,
+    (q31_t)0x47bca163, (q31_t)0xc078286e, (q31_t)0x47b027d7, (q31_t)0xc076a4c2,
+    (q31_t)0x47a3adff, (q31_t)0xc0752389, (q31_t)0x479733dc, (q31_t)0xc073a4c3,
+    (q31_t)0x478ab96e, (q31_t)0xc0722871, (q31_t)0x477e3eb5, (q31_t)0xc070ae92,
+    (q31_t)0x4771c3b3, (q31_t)0xc06f3726, (q31_t)0x47654867, (q31_t)0xc06dc22e,
+    (q31_t)0x4758ccd2, (q31_t)0xc06c4fa8, (q31_t)0x474c50f4, (q31_t)0xc06adf97,
+    (q31_t)0x473fd4cf, (q31_t)0xc06971f9, (q31_t)0x47335862, (q31_t)0xc06806ce,
+    (q31_t)0x4726dbae, (q31_t)0xc0669e18, (q31_t)0x471a5eb3, (q31_t)0xc06537d4,
+    (q31_t)0x470de172, (q31_t)0xc063d405, (q31_t)0x470163eb, (q31_t)0xc06272aa,
+    (q31_t)0x46f4e620, (q31_t)0xc06113c2, (q31_t)0x46e86810, (q31_t)0xc05fb74e,
+    (q31_t)0x46dbe9bb, (q31_t)0xc05e5d4e, (q31_t)0x46cf6b23, (q31_t)0xc05d05c3,
+    (q31_t)0x46c2ec48, (q31_t)0xc05bb0ab, (q31_t)0x46b66d29, (q31_t)0xc05a5e07,
+    (q31_t)0x46a9edc9, (q31_t)0xc0590dd8, (q31_t)0x469d6e27, (q31_t)0xc057c01d,
+    (q31_t)0x4690ee44, (q31_t)0xc05674d6, (q31_t)0x46846e1f, (q31_t)0xc0552c03,
+    (q31_t)0x4677edbb, (q31_t)0xc053e5a5, (q31_t)0x466b6d16, (q31_t)0xc052a1bb,
+    (q31_t)0x465eec33, (q31_t)0xc0516045, (q31_t)0x46526b10, (q31_t)0xc0502145,
+    (q31_t)0x4645e9af, (q31_t)0xc04ee4b8, (q31_t)0x46396810, (q31_t)0xc04daaa1,
+    (q31_t)0x462ce634, (q31_t)0xc04c72fe, (q31_t)0x4620641a, (q31_t)0xc04b3dcf,
+    (q31_t)0x4613e1c5, (q31_t)0xc04a0b16, (q31_t)0x46075f33, (q31_t)0xc048dad1,
+    (q31_t)0x45fadc66, (q31_t)0xc047ad01, (q31_t)0x45ee595d, (q31_t)0xc04681a6,
+    (q31_t)0x45e1d61b, (q31_t)0xc04558c0, (q31_t)0x45d5529e, (q31_t)0xc044324f,
+    (q31_t)0x45c8cee7, (q31_t)0xc0430e53, (q31_t)0x45bc4af8, (q31_t)0xc041eccc,
+    (q31_t)0x45afc6d0, (q31_t)0xc040cdba, (q31_t)0x45a3426f, (q31_t)0xc03fb11d,
+    (q31_t)0x4596bdd7, (q31_t)0xc03e96f6, (q31_t)0x458a3908, (q31_t)0xc03d7f44,
+    (q31_t)0x457db403, (q31_t)0xc03c6a07, (q31_t)0x45712ec7, (q31_t)0xc03b573f,
+    (q31_t)0x4564a955, (q31_t)0xc03a46ed, (q31_t)0x455823ae, (q31_t)0xc0393910,
+    (q31_t)0x454b9dd3, (q31_t)0xc0382da8, (q31_t)0x453f17c3, (q31_t)0xc03724b6,
+    (q31_t)0x4532917f, (q31_t)0xc0361e3a, (q31_t)0x45260b08, (q31_t)0xc0351a33,
+    (q31_t)0x4519845e, (q31_t)0xc03418a2, (q31_t)0x450cfd82, (q31_t)0xc0331986,
+    (q31_t)0x45007674, (q31_t)0xc0321ce0, (q31_t)0x44f3ef35, (q31_t)0xc03122b0,
+    (q31_t)0x44e767c5, (q31_t)0xc0302af5, (q31_t)0x44dae024, (q31_t)0xc02f35b1,
+    (q31_t)0x44ce5854, (q31_t)0xc02e42e2, (q31_t)0x44c1d054, (q31_t)0xc02d5289,
+    (q31_t)0x44b54825, (q31_t)0xc02c64a6, (q31_t)0x44a8bfc7, (q31_t)0xc02b7939,
+    (q31_t)0x449c373c, (q31_t)0xc02a9042, (q31_t)0x448fae83, (q31_t)0xc029a9c1,
+    (q31_t)0x4483259d, (q31_t)0xc028c5b6, (q31_t)0x44769c8b, (q31_t)0xc027e421,
+    (q31_t)0x446a134c, (q31_t)0xc0270502, (q31_t)0x445d89e2, (q31_t)0xc0262859,
+    (q31_t)0x4451004d, (q31_t)0xc0254e27, (q31_t)0x4444768d, (q31_t)0xc024766a,
+    (q31_t)0x4437eca4, (q31_t)0xc023a124, (q31_t)0x442b6290, (q31_t)0xc022ce54,
+    (q31_t)0x441ed854, (q31_t)0xc021fdfb, (q31_t)0x44124dee, (q31_t)0xc0213018,
+    (q31_t)0x4405c361, (q31_t)0xc02064ab, (q31_t)0x43f938ac, (q31_t)0xc01f9bb5,
+    (q31_t)0x43ecadcf, (q31_t)0xc01ed535, (q31_t)0x43e022cc, (q31_t)0xc01e112b,
+    (q31_t)0x43d397a3, (q31_t)0xc01d4f99, (q31_t)0x43c70c54, (q31_t)0xc01c907c,
+    (q31_t)0x43ba80df, (q31_t)0xc01bd3d6, (q31_t)0x43adf546, (q31_t)0xc01b19a7,
+    (q31_t)0x43a16988, (q31_t)0xc01a61ee, (q31_t)0x4394dda7, (q31_t)0xc019acac,
+    (q31_t)0x438851a2, (q31_t)0xc018f9e1, (q31_t)0x437bc57b, (q31_t)0xc018498c,
+    (q31_t)0x436f3931, (q31_t)0xc0179bae, (q31_t)0x4362acc5, (q31_t)0xc016f047,
+    (q31_t)0x43562038, (q31_t)0xc0164757, (q31_t)0x43499389, (q31_t)0xc015a0dd,
+    (q31_t)0x433d06bb, (q31_t)0xc014fcda, (q31_t)0x433079cc, (q31_t)0xc0145b4e,
+    (q31_t)0x4323ecbe, (q31_t)0xc013bc39, (q31_t)0x43175f91, (q31_t)0xc0131f9b,
+    (q31_t)0x430ad245, (q31_t)0xc0128574, (q31_t)0x42fe44dc, (q31_t)0xc011edc3,
+    (q31_t)0x42f1b755, (q31_t)0xc011588a, (q31_t)0x42e529b0, (q31_t)0xc010c5c7,
+    (q31_t)0x42d89bf0, (q31_t)0xc010357c, (q31_t)0x42cc0e13, (q31_t)0xc00fa7a8,
+    (q31_t)0x42bf801a, (q31_t)0xc00f1c4a, (q31_t)0x42b2f207, (q31_t)0xc00e9364,
+    (q31_t)0x42a663d8, (q31_t)0xc00e0cf5, (q31_t)0x4299d590, (q31_t)0xc00d88fd,
+    (q31_t)0x428d472e, (q31_t)0xc00d077c, (q31_t)0x4280b8b3, (q31_t)0xc00c8872,
+    (q31_t)0x42742a1f, (q31_t)0xc00c0be0, (q31_t)0x42679b73, (q31_t)0xc00b91c4,
+    (q31_t)0x425b0caf, (q31_t)0xc00b1a20, (q31_t)0x424e7dd4, (q31_t)0xc00aa4f3,
+    (q31_t)0x4241eee2, (q31_t)0xc00a323d, (q31_t)0x42355fd9, (q31_t)0xc009c1ff,
+    (q31_t)0x4228d0bb, (q31_t)0xc0095438, (q31_t)0x421c4188, (q31_t)0xc008e8e8,
+    (q31_t)0x420fb240, (q31_t)0xc008800f, (q31_t)0x420322e3, (q31_t)0xc00819ae,
+    (q31_t)0x41f69373, (q31_t)0xc007b5c4, (q31_t)0x41ea03ef, (q31_t)0xc0075452,
+    (q31_t)0x41dd7459, (q31_t)0xc006f556, (q31_t)0x41d0e4b0, (q31_t)0xc00698d3,
+    (q31_t)0x41c454f5, (q31_t)0xc0063ec6, (q31_t)0x41b7c528, (q31_t)0xc005e731,
+    (q31_t)0x41ab354b, (q31_t)0xc0059214, (q31_t)0x419ea55d, (q31_t)0xc0053f6e,
+    (q31_t)0x4192155f, (q31_t)0xc004ef3f, (q31_t)0x41858552, (q31_t)0xc004a188,
+    (q31_t)0x4178f536, (q31_t)0xc0045648, (q31_t)0x416c650b, (q31_t)0xc0040d80,
+    (q31_t)0x415fd4d2, (q31_t)0xc003c72f, (q31_t)0x4153448c, (q31_t)0xc0038356,
+    (q31_t)0x4146b438, (q31_t)0xc00341f4, (q31_t)0x413a23d8, (q31_t)0xc003030a,
+    (q31_t)0x412d936c, (q31_t)0xc002c697, (q31_t)0x412102f4, (q31_t)0xc0028c9c,
+    (q31_t)0x41147271, (q31_t)0xc0025519, (q31_t)0x4107e1e3, (q31_t)0xc002200d,
+    (q31_t)0x40fb514b, (q31_t)0xc001ed78, (q31_t)0x40eec0aa, (q31_t)0xc001bd5c,
+    (q31_t)0x40e22fff, (q31_t)0xc0018fb6, (q31_t)0x40d59f4c, (q31_t)0xc0016489,
+    (q31_t)0x40c90e90, (q31_t)0xc0013bd3, (q31_t)0x40bc7dcc, (q31_t)0xc0011594,
+    (q31_t)0x40afed02, (q31_t)0xc000f1ce, (q31_t)0x40a35c30, (q31_t)0xc000d07e,
+    (q31_t)0x4096cb58, (q31_t)0xc000b1a7, (q31_t)0x408a3a7b, (q31_t)0xc0009547,
+    (q31_t)0x407da998, (q31_t)0xc0007b5f, (q31_t)0x407118b0, (q31_t)0xc00063ee,
+    (q31_t)0x406487c4, (q31_t)0xc0004ef5, (q31_t)0x4057f6d4, (q31_t)0xc0003c74,
+    (q31_t)0x404b65e1, (q31_t)0xc0002c6a, (q31_t)0x403ed4ea, (q31_t)0xc0001ed8,
+    (q31_t)0x403243f1, (q31_t)0xc00013bd, (q31_t)0x4025b2f7, (q31_t)0xc0000b1a,
+    (q31_t)0x401921fb, (q31_t)0xc00004ef, (q31_t)0x400c90fe, (q31_t)0xc000013c,
+};
+
+/**
+* @} end of RealFFT_Table group
+*/
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* @brief  Initialization function for the Q31 RFFT/RIFFT.
+* @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.
+* @param[in]      fftLenReal     length of the FFT.
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return         The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192.
+* \par
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par    7
+* This function also initializes Twiddle factor table.
+*/
+
+arm_status arm_rfft_init_q31(
+    arm_rfft_instance_q31 * S,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag)
+{
+    /*  Initialise the default arm status */
+    arm_status status = ARM_MATH_SUCCESS;
+
+    /*  Initialize the Real FFT length */
+    S->fftLenReal = (uint16_t) fftLenReal;
+
+    /*  Initialize the Twiddle coefficientA pointer */
+    S->pTwiddleAReal = (q31_t *) realCoefAQ31;
+
+    /*  Initialize the Twiddle coefficientB pointer */
+    S->pTwiddleBReal = (q31_t *) realCoefBQ31;
+
+    /*  Initialize the Flag for selection of RFFT or RIFFT */
+    S->ifftFlagR = (uint8_t) ifftFlagR;
+
+    /*  Initialize the Flag for calculation Bit reversal or not */
+    S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+    /*  Initialization of coef modifier depending on the FFT length */
+    switch (S->fftLenReal)
+    {
+    case 8192U:
+        S->twidCoefRModifier = 1U;
+        S->pCfft = &arm_cfft_sR_q31_len4096;
+        break;
+    case 4096U:
+        S->twidCoefRModifier = 2U;
+        S->pCfft = &arm_cfft_sR_q31_len2048;
+        break;
+    case 2048U:
+        S->twidCoefRModifier = 4U;
+        S->pCfft = &arm_cfft_sR_q31_len1024;
+        break;
+    case 1024U:
+        S->twidCoefRModifier = 8U;
+        S->pCfft = &arm_cfft_sR_q31_len512;
+        break;
+    case 512U:
+        S->twidCoefRModifier = 16U;
+        S->pCfft = &arm_cfft_sR_q31_len256;
+        break;
+    case 256U:
+        S->twidCoefRModifier = 32U;
+        S->pCfft = &arm_cfft_sR_q31_len128;
+        break;
+    case 128U:
+        S->twidCoefRModifier = 64U;
+        S->pCfft = &arm_cfft_sR_q31_len64;
+        break;
+    case 64U:
+        S->twidCoefRModifier = 128U;
+        S->pCfft = &arm_cfft_sR_q31_len32;
+        break;
+    case 32U:
+        S->twidCoefRModifier = 256U;
+        S->pCfft = &arm_cfft_sR_q31_len16;
+        break;
+    default:
+        /*  Reporting argument error if rfftSize is not valid value */
+        status = ARM_MATH_ARGUMENT_ERROR;
+        break;
+    }
+
+    /* return the status of RFFT Init function */
+    return (status);
+}
+
+/**
+* @} end of RealFFT group
+*/
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c
new file mode 100644
index 0000000..8a888f4
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c
@@ -0,0 +1,426 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_rfft_q15.c
+ * Description:  RFFT & RIFFT Q15 process function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+ * Internal functions prototypes
+ * -------------------------------------------------------------------- */
+
+void arm_split_rfft_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    q15_t * pATable,
+    q15_t * pBTable,
+    q15_t * pDst,
+    uint32_t modifier);
+
+void arm_split_rifft_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    q15_t * pATable,
+    q15_t * pBTable,
+    q15_t * pDst,
+    uint32_t modifier);
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* @brief Processing function for the Q15 RFFT/RIFFT.
+* @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.
+* @param[in]  *pSrc points to the input buffer.
+* @param[out] *pDst points to the output buffer.
+* @return none.
+*
+* \par Input an output formats:
+* \par
+* Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+* Hence the output format is different for different RFFT sizes.
+* The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
+* \par
+* \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"
+* \par
+* \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"
+*/
+
+void arm_rfft_q15(
+    const arm_rfft_instance_q15 * S,
+    q15_t * pSrc,
+    q15_t * pDst)
+{
+    const arm_cfft_instance_q15 *S_CFFT = S->pCfft;
+    uint32_t i;
+    uint32_t L2 = S->fftLenReal >> 1;
+
+    /* Calculation of RIFFT of input */
+    if (S->ifftFlagR == 1U)
+    {
+        /*  Real IFFT core process */
+        arm_split_rifft_q15(pSrc, L2, S->pTwiddleAReal,
+                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+        /* Complex IFFT process */
+        arm_cfft_q15(S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR);
+
+        for(i=0;ifftLenReal;i++)
+        {
+            pDst[i] = pDst[i] << 1;
+        }
+    }
+    else
+    {
+        /* Calculation of RFFT of input */
+
+        /* Complex FFT process */
+        arm_cfft_q15(S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR);
+
+        /*  Real FFT core process */
+        arm_split_rfft_q15(pSrc, L2, S->pTwiddleAReal,
+                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+    }
+}
+
+/**
+* @} end of RealFFT group
+*/
+
+/**
+* @brief  Core Real FFT process
+* @param  *pSrc 				points to the input buffer.
+* @param  fftLen  				length of FFT.
+* @param  *pATable 			points to the A twiddle Coef buffer.
+* @param  *pBTable 			points to the B twiddle Coef buffer.
+* @param  *pDst 				points to the output buffer.
+* @param  modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+* The function implements a Real FFT
+*/
+
+void arm_split_rfft_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    q15_t * pATable,
+    q15_t * pBTable,
+    q15_t * pDst,
+    uint32_t modifier)
+{
+    uint32_t i;                                    /* Loop Counter */
+    q31_t outR, outI;                              /* Temporary variables for output */
+    q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+    q15_t *pSrc1, *pSrc2;
+#if defined (ARM_MATH_DSP)
+    q15_t *pD1, *pD2;
+#endif
+
+    //  pSrc[2U * fftLen] = pSrc[0];
+    //  pSrc[(2U * fftLen) + 1U] = pSrc[1];
+
+    pCoefA = &pATable[modifier * 2U];
+    pCoefB = &pBTable[modifier * 2U];
+
+    pSrc1 = &pSrc[2];
+    pSrc2 = &pSrc[(2U * fftLen) - 2U];
+
+#if defined (ARM_MATH_DSP)
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    i = 1U;
+    pD1 = pDst + 2;
+    pD2 = pDst + (4U * fftLen) - 2;
+
+    for(i = fftLen - 1; i > 0; i--)
+    {
+        /*
+        outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+        + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+        */
+
+        /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+        outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
+
+#else
+
+        /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
+        outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+        outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 16U;
+
+        /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+#else
+
+        outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
+        outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
+
+        /* write output */
+        *pD1++ = (q15_t) outR;
+        *pD1++ = outI >> 16U;
+
+        /* write complex conjugate output */
+        pD2[0] = (q15_t) outR;
+        pD2[1] = -(outI >> 16U);
+        pD2 -= 2;
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (2U * modifier);
+        pCoefA = pCoefA + (2U * modifier);
+    }
+
+    pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
+    pDst[(2U * fftLen) + 1U] = 0;
+
+    pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
+    pDst[1] = 0;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+    i = 1U;
+
+    while (i < fftLen)
+    {
+        /*
+        outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+        + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+        */
+
+        outR = *pSrc1 * *pCoefA;
+        outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
+        outR = outR + (*pSrc2 * *pCoefB);
+        outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 16;
+
+
+        /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+        */
+
+        outI = *pSrc2 * *(pCoefB + 1);
+        outI = outI - (*(pSrc2 + 1) * *pCoefB);
+        outI = outI + (*(pSrc1 + 1) * *pCoefA);
+        outI = outI + (*pSrc1 * *(pCoefA + 1));
+
+        /* update input pointers */
+        pSrc1 += 2U;
+        pSrc2 -= 2U;
+
+        /* write output */
+        pDst[2U * i] = (q15_t) outR;
+        pDst[(2U * i) + 1U] = outI >> 16U;
+
+        /* write complex conjugate output */
+        pDst[(4U * fftLen) - (2U * i)] = (q15_t) outR;
+        pDst[((4U * fftLen) - (2U * i)) + 1U] = -(outI >> 16U);
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (2U * modifier);
+        pCoefA = pCoefA + (2U * modifier);
+
+        i++;
+    }
+
+    pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
+    pDst[(2U * fftLen) + 1U] = 0;
+
+    pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
+    pDst[1] = 0;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+}
+
+
+/**
+* @brief  Core Real IFFT process
+* @param[in]   *pSrc 				points to the input buffer.
+* @param[in]   fftLen  		    length of FFT.
+* @param[in]   *pATable 			points to the twiddle Coef A buffer.
+* @param[in]   *pBTable 			points to the twiddle Coef B buffer.
+* @param[out]  *pDst 				points to the output buffer.
+* @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+* The function implements a Real IFFT
+*/
+void arm_split_rifft_q15(
+    q15_t * pSrc,
+    uint32_t fftLen,
+    q15_t * pATable,
+    q15_t * pBTable,
+    q15_t * pDst,
+    uint32_t modifier)
+{
+    uint32_t i;                                    /* Loop Counter */
+    q31_t outR, outI;                              /* Temporary variables for output */
+    q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+    q15_t *pSrc1, *pSrc2;
+    q15_t *pDst1 = &pDst[0];
+
+    pCoefA = &pATable[0];
+    pCoefB = &pBTable[0];
+
+    pSrc1 = &pSrc[0];
+    pSrc2 = &pSrc[2U * fftLen];
+
+#if defined (ARM_MATH_DSP)
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    i = fftLen;
+
+    while (i > 0U)
+    {
+        /*
+        outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+        pIn[2 * n - 2 * i] * pBTable[2 * i] -
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+        outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+        */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* pIn[2 * n - 2 * i] * pBTable[2 * i] -
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+        outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
+
+#else
+
+        /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
+        outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+        pIn[2 * n - 2 * i] * pBTable[2 * i] */
+        outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 16U;
+
+        /*
+        -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+        outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+        /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
+
+#else
+
+        outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+        /* write output */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 16U), 16);
+
+#else
+
+        *__SIMD32(pDst1)++ = __PKHBT((outI >> 16U), outR, 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (2U * modifier);
+        pCoefA = pCoefA + (2U * modifier);
+
+        i--;
+    }
+#else
+    /* Run the below code for Cortex-M0 */
+    i = fftLen;
+
+    while (i > 0U)
+    {
+        /*
+        outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+        pIn[2 * n - 2 * i] * pBTable[2 * i] -
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+        */
+
+        outR = *pSrc2 * *pCoefB;
+        outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
+        outR = outR + (*pSrc1 * *pCoefA);
+        outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 16;
+
+        /*
+        outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+        */
+
+        outI = *(pSrc1 + 1) * *pCoefA;
+        outI = outI - (*pSrc1 * *(pCoefA + 1));
+        outI = outI - (*pSrc2 * *(pCoefB + 1));
+        outI = outI - (*(pSrc2 + 1) * *(pCoefB));
+
+        /* update input pointers */
+        pSrc1 += 2U;
+        pSrc2 -= 2U;
+
+        /* write output */
+        *pDst1++ = (q15_t) outR;
+        *pDst1++ = (q15_t) (outI >> 16);
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (2U * modifier);
+        pCoefA = pCoefA + (2U * modifier);
+
+        i--;
+    }
+#endif /* #if defined (ARM_MATH_DSP) */
+}
diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c
new file mode 100644
index 0000000..d21b964
--- /dev/null
+++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c
@@ -0,0 +1,283 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_rfft_q31.c
+ * Description:  FFT & RIFFT Q31 process function
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+ * Internal functions prototypes
+ * -------------------------------------------------------------------- */
+
+void arm_split_rfft_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pATable,
+    q31_t * pBTable,
+    q31_t * pDst,
+    uint32_t modifier);
+
+void arm_split_rifft_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pATable,
+    q31_t * pBTable,
+    q31_t * pDst,
+    uint32_t modifier);
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* @brief Processing function for the Q31 RFFT/RIFFT.
+* @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.
+* @param[in]  *pSrc points to the input buffer.
+* @param[out] *pDst points to the output buffer.
+* @return none.
+*
+* \par Input an output formats:
+* \par
+* Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+* Hence the output format is different for different RFFT sizes.
+* The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
+* \par
+* \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"
+*
+* \par
+* \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"
+*/
+void arm_rfft_q31(
+    const arm_rfft_instance_q31 * S,
+    q31_t * pSrc,
+    q31_t * pDst)
+{
+    const arm_cfft_instance_q31 *S_CFFT = S->pCfft;
+    uint32_t i;
+    uint32_t L2 = S->fftLenReal >> 1;
+
+    /* Calculation of RIFFT of input */
+    if (S->ifftFlagR == 1U)
+    {
+        /*  Real IFFT core process */
+        arm_split_rifft_q31(pSrc, L2, S->pTwiddleAReal,
+                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+        /* Complex IFFT process */
+        arm_cfft_q31(S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR);
+
+        for(i=0;ifftLenReal;i++)
+        {
+            pDst[i] = pDst[i] << 1;
+        }
+    }
+    else
+    {
+        /* Calculation of RFFT of input */
+
+        /* Complex FFT process */
+        arm_cfft_q31(S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR);
+
+        /*  Real FFT core process */
+        arm_split_rfft_q31(pSrc, L2, S->pTwiddleAReal,
+                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+    }
+}
+
+/**
+* @} end of RealFFT group
+*/
+
+/**
+* @brief  Core Real FFT process
+* @param[in]   *pSrc 				points to the input buffer.
+* @param[in]   fftLen  			    length of FFT.
+* @param[in]   *pATable 			points to the twiddle Coef A buffer.
+* @param[in]   *pBTable 			points to the twiddle Coef B buffer.
+* @param[out]  *pDst 				points to the output buffer.
+* @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+void arm_split_rfft_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pATable,
+    q31_t * pBTable,
+    q31_t * pDst,
+    uint32_t modifier)
+{
+    uint32_t i;                                    /* Loop Counter */
+    q31_t outR, outI;                              /* Temporary variables for output */
+    q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+    q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+    q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4U * fftLen) - 1U];
+    q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2U * fftLen) - 1U];
+
+    /* Init coefficient pointers */
+    pCoefA = &pATable[modifier * 2U];
+    pCoefB = &pBTable[modifier * 2U];
+
+    i = fftLen - 1U;
+
+    while (i > 0U)
+    {
+        /*
+        outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+        + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+        */
+
+        /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+        CoefA1 = *pCoefA++;
+        CoefA2 = *pCoefA;
+
+        /* outR = (pSrc[2 * i] * pATable[2 * i] */
+        mult_32x32_keep32_R(outR, *pIn1, CoefA1);
+
+        /* outI = pIn[2 * i] * pATable[2 * i + 1] */
+        mult_32x32_keep32_R(outI, *pIn1++, CoefA2);
+
+        /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+        multSub_32x32_keep32_R(outR, *pIn1, CoefA2);
+
+        /* (pIn[2 * i + 1] * pATable[2 * i] */
+        multAcc_32x32_keep32_R(outI, *pIn1++, CoefA1);
+
+        /* pSrc[2 * n - 2 * i] * pBTable[2 * i]  */
+        multSub_32x32_keep32_R(outR, *pIn2, CoefA2);
+        CoefB1 = *pCoefB;
+
+        /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+        multSub_32x32_keep32_R(outI, *pIn2--, CoefB1);
+
+        /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+        multAcc_32x32_keep32_R(outR, *pIn2, CoefB1);
+
+        /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+        multSub_32x32_keep32_R(outI, *pIn2--, CoefA2);
+
+        /* write output */
+        *pOut1++ = outR;
+        *pOut1++ = outI;
+
+        /* write complex conjugate output */
+        *pOut2-- = -outI;
+        *pOut2-- = outR;
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (modifier * 2U);
+        pCoefA = pCoefA + ((modifier * 2U) - 1U);
+
+        i--;
+    }
+    pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
+    pDst[(2U * fftLen) + 1U] = 0;
+
+    pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
+    pDst[1] = 0;
+}
+
+/**
+* @brief  Core Real IFFT process
+* @param[in]   *pSrc 				points to the input buffer.
+* @param[in]   fftLen  			    length of FFT.
+* @param[in]   *pATable 			points to the twiddle Coef A buffer.
+* @param[in]   *pBTable 			points to the twiddle Coef B buffer.
+* @param[out]  *pDst 				points to the output buffer.
+* @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+void arm_split_rifft_q31(
+    q31_t * pSrc,
+    uint32_t fftLen,
+    q31_t * pATable,
+    q31_t * pBTable,
+    q31_t * pDst,
+    uint32_t modifier)
+{
+    q31_t outR, outI;                              /* Temporary variables for output */
+    q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+    q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+    q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2U * fftLen) + 1U];
+
+    pCoefA = &pATable[0];
+    pCoefB = &pBTable[0];
+
+    while (fftLen > 0U)
+    {
+        /*
+        outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+        pIn[2 * n - 2 * i] * pBTable[2 * i] -
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+        outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+        */
+        CoefA1 = *pCoefA++;
+        CoefA2 = *pCoefA;
+
+        /* outR = (pIn[2 * i] * pATable[2 * i] */
+        mult_32x32_keep32_R(outR, *pIn1, CoefA1);
+
+        /* - pIn[2 * i] * pATable[2 * i + 1] */
+        mult_32x32_keep32_R(outI, *pIn1++, -CoefA2);
+
+        /* pIn[2 * i + 1] * pATable[2 * i + 1] */
+        multAcc_32x32_keep32_R(outR, *pIn1, CoefA2);
+
+        /* pIn[2 * i + 1] * pATable[2 * i] */
+        multAcc_32x32_keep32_R(outI, *pIn1++, CoefA1);
+
+        /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
+        multAcc_32x32_keep32_R(outR, *pIn2, CoefA2);
+        CoefB1 = *pCoefB;
+
+        /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+        multSub_32x32_keep32_R(outI, *pIn2--, CoefB1);
+
+        /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+        multAcc_32x32_keep32_R(outR, *pIn2, CoefB1);
+
+        /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+        multAcc_32x32_keep32_R(outI, *pIn2--, CoefA2);
+
+        /* write output */
+        *pDst++ = outR;
+        *pDst++ = outI;
+
+        /* update coefficient pointer */
+        pCoefB = pCoefB + (modifier * 2U);
+        pCoefA = pCoefA + ((modifier * 2U) - 1U);
+
+        /* Decrement loop count */
+        fftLen--;
+    }
+}
diff --git a/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h b/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h
new file mode 100644
index 0000000..6e08d2f
--- /dev/null
+++ b/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h
@@ -0,0 +1,18950 @@
+/**
+  ******************************************************************************
+  * @file    stm32f767xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32f767xx
+  * @{
+  */
+
+#ifndef __STM32F767xx_H
+#define __STM32F767xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief STM32F7xx Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
+  DFSDM1_FLT0_IRQn	          = 99,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
+  DFSDM1_FLT1_IRQn	          = 100,    /*!< DFSDM1 Filter 1 global Interrupt                                  */
+  DFSDM1_FLT2_IRQn	          = 101,    /*!< DFSDM1 Filter 2 global Interrupt                                  */
+  DFSDM1_FLT3_IRQn	          = 102,    /*!< DFSDM1 Filter 3 global Interrupt                                  */
+  SDMMC2_IRQn                 = 103,    /*!< SDMMC2 global Interrupt                                           */
+  CAN3_TX_IRQn                = 104,    /*!< CAN3 TX Interrupt                                                 */
+  CAN3_RX0_IRQn               = 105,    /*!< CAN3 RX0 Interrupt                                                */
+  CAN3_RX1_IRQn               = 106,    /*!< CAN3 RX1 Interrupt                                                */
+  CAN3_SCE_IRQn               = 107,    /*!< CAN3 SCE Interrupt                                                */
+  JPEG_IRQn                   = 108,    /*!< JPEG global Interrupt                                             */
+  MDIOS_IRQn                  = 109     /*!< MDIO Slave global Interrupt                                       */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+/**
+ * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
+ */
+#define __CM7_REV                 0x0100U  /*!< Cortex-M7 revision r1p0                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
+#include "core_cm7.h"                      /*!< Cortex-M7 processor and core peripherals      */
+
+
+#include "system_stm32f7xx.h"
+#include 
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief Controller Area Network TxMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FIFOMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FilterRegister
+  */
+
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+  * @brief Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/**
+  * @brief HDMI-CEC
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */
+  uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */
+  __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;         /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;         /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;         /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;         /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;       /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;         /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;      /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;      /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;       /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;       /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;        /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;       /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;       /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;       /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;     /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
+                                  short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+
+/**
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+  uint32_t      RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+  uint32_t      RESERVED1;
+  __IO uint32_t MACDBGR;
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+  uint32_t      RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+  uint32_t      RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+  uint32_t      RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+  uint32_t      RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+  uint32_t      RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+  uint32_t      RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+  __IO uint32_t RESERVED8;
+  __IO uint32_t PTPTSSR;
+  __IO uint32_t PTPPPSCR;
+  uint32_t      RESERVED9[564];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+  __IO uint32_t DMARSWTR;
+  uint32_t      RESERVED10[8];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */
+  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
+  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
+  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
+  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */
+  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank5_6
+  */
+
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef;
+
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */
+  __IO uint32_t CBR;          /*!< SYSCFG Class B register,                           Address offset: 0x1C      */
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+/**
+  * @brief LCD-TFT Display Controller
+  */
+
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+  * @brief LCD-TFT Display layer x Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */
+  __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */
+} PWR_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
+  __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */
+  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */
+
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t reserved;   /*!< Reserved  */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief SPDIF-RX Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
+} SPDIFRX_TypeDef;
+
+/**
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */
+  __IO uint32_t AF1;         /*!< TIM Alternate function option register 1, Address offset: 0x60 */
+  __IO uint32_t AF2;         /*!< TIM Alternate function option register 2, Address offset: 0x64 */
+
+} TIM_TypeDef;
+
+/**
+  * @brief LPTIMIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+} USART_TypeDef;
+
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  uint32_t  Reserved7;                /*!< Reserved                                     058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+  uint32_t  Reserved43[40];           /*!< Reserved                                 60h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO              104h-13Ch */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encoder, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encoder, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;               /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 00h       */
+  __IO uint32_t WRFR;             /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 04h       */
+  __IO uint32_t CWRFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 08h       */
+  __IO uint32_t RDFR;             /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 0Ch       */
+  __IO uint32_t CRDFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 10h       */
+  __IO uint32_t SR;               /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 14h       */
+  __IO uint32_t CLRFR;            /*!< MDIOS Configuration Register (MDIOS_CR),        Address offset: 18h       */
+  uint32_t RESERVED0[57];         /* Reserved                                          Address offset: 1Ch       */
+  __IO uint32_t DINR0;            /*!< MDIOS Input Data Register (MDIOS_DINR0),        Address offset: 100h      */
+  __IO uint32_t DINR1;            /*!< MDIOS Input Data Register (MDIOS_DINR1),        Address offset: 104h      */
+  __IO uint32_t DINR2;            /*!< MDIOS Input Data Register (MDIOS_DINR2),        Address offset: 108h      */
+  __IO uint32_t DINR3;            /*!< MDIOS Input Data Register (MDIOS_DINR3),        Address offset: 10Ch      */
+  __IO uint32_t DINR4;            /*!< MDIOS Input Data Register (MDIOS_DINR4),        Address offset: 110h      */
+  __IO uint32_t DINR5;            /*!< MDIOS Input Data Register (MDIOS_DINR5),        Address offset: 114h      */
+  __IO uint32_t DINR6;            /*!< MDIOS Input Data Register (MDIOS_DINR6),        Address offset: 118h      */
+  __IO uint32_t DINR7;            /*!< MDIOS Input Data Register (MDIOS_DINR7),        Address offset: 11Ch      */
+  __IO uint32_t DINR8;            /*!< MDIOS Input Data Register (MDIOS_DINR8),        Address offset: 120h      */
+  __IO uint32_t DINR9;            /*!< MDIOS Input Data Register (MDIOS_DINR9),        Address offset: 124h      */
+  __IO uint32_t DINR10;           /*!< MDIOS Input Data Register (MDIOS_DINR10),       Address offset: 128h      */
+  __IO uint32_t DINR11;           /*!< MDIOS Input Data Register (MDIOS_DINR11),       Address offset: 12Ch      */
+  __IO uint32_t DINR12;           /*!< MDIOS Input Data Register (MDIOS_DINR12),       Address offset: 130h      */
+  __IO uint32_t DINR13;           /*!< MDIOS Input Data Register (MDIOS_DINR13),       Address offset: 134h      */
+  __IO uint32_t DINR14;           /*!< MDIOS Input Data Register (MDIOS_DINR14),       Address offset: 138h      */
+  __IO uint32_t DINR15;           /*!< MDIOS Input Data Register (MDIOS_DINR15),       Address offset: 13Ch      */
+  __IO uint32_t DINR16;           /*!< MDIOS Input Data Register (MDIOS_DINR16),       Address offset: 140h      */
+  __IO uint32_t DINR17;           /*!< MDIOS Input Data Register (MDIOS_DINR17),       Address offset: 144h      */
+  __IO uint32_t DINR18;           /*!< MDIOS Input Data Register (MDIOS_DINR18),       Address offset: 148h      */
+  __IO uint32_t DINR19;           /*!< MDIOS Input Data Register (MDIOS_DINR19),       Address offset: 14Ch      */
+  __IO uint32_t DINR20;           /*!< MDIOS Input Data Register (MDIOS_DINR20),       Address offset: 150h      */
+  __IO uint32_t DINR21;           /*!< MDIOS Input Data Register (MDIOS_DINR21),       Address offset: 154h      */
+  __IO uint32_t DINR22;           /*!< MDIOS Input Data Register (MDIOS_DINR22),       Address offset: 158h      */
+  __IO uint32_t DINR23;           /*!< MDIOS Input Data Register (MDIOS_DINR23),       Address offset: 15Ch      */
+  __IO uint32_t DINR24;           /*!< MDIOS Input Data Register (MDIOS_DINR24),       Address offset: 160h      */
+  __IO uint32_t DINR25;           /*!< MDIOS Input Data Register (MDIOS_DINR25),       Address offset: 164h      */
+  __IO uint32_t DINR26;           /*!< MDIOS Input Data Register (MDIOS_DINR26),       Address offset: 168h      */
+  __IO uint32_t DINR27;           /*!< MDIOS Input Data Register (MDIOS_DINR27),       Address offset: 16Ch      */
+  __IO uint32_t DINR28;           /*!< MDIOS Input Data Register (MDIOS_DINR28),       Address offset: 170h      */
+  __IO uint32_t DINR29;           /*!< MDIOS Input Data Register (MDIOS_DINR29),       Address offset: 174h      */
+  __IO uint32_t DINR30;           /*!< MDIOS Input Data Register (MDIOS_DINR30),       Address offset: 178h      */
+  __IO uint32_t DINR31;           /*!< MDIOS Input Data Register (MDIOS_DINR31),       Address offset: 17Ch      */
+  __IO uint32_t DOUTR0;           /*!< MDIOS Output Data Register (MDIOS_DOUTR0),      Address offset: 180h      */
+  __IO uint32_t DOUTR1;           /*!< MDIOS Output Data Register (MDIOS_DOUTR1),      Address offset: 184h      */
+  __IO uint32_t DOUTR2;           /*!< MDIOS Output Data Register (MDIOS_DOUTR2),      Address offset: 188h      */
+  __IO uint32_t DOUTR3;           /*!< MDIOS Output Data Register (MDIOS_DOUTR3),      Address offset: 18Ch      */
+  __IO uint32_t DOUTR4;           /*!< MDIOS Output Data Register (MDIOS_DOUTR4),      Address offset: 190h      */
+  __IO uint32_t DOUTR5;           /*!< MDIOS Output Data Register (MDIOS_DOUTR5),      Address offset: 194h      */
+  __IO uint32_t DOUTR6;           /*!< MDIOS Output Data Register (MDIOS_DOUTR6),      Address offset: 198h      */
+  __IO uint32_t DOUTR7;           /*!< MDIOS Output Data Register (MDIOS_DOUTR7),      Address offset: 19Ch      */
+  __IO uint32_t DOUTR8;           /*!< MDIOS Output Data Register (MDIOS_DOUTR8),      Address offset: 1A0h      */
+  __IO uint32_t DOUTR9;           /*!< MDIOS Output Data Register (MDIOS_DOUTR9),      Address offset: 1A4h      */
+  __IO uint32_t DOUTR10;          /*!< MDIOS Output Data Register (MDIOS_DOUTR10),     Address offset: 1A8h      */
+  __IO uint32_t DOUTR11;          /*!< MDIOS Output Data Register (MDIOS_DOUTR11),     Address offset: 1ACh      */
+  __IO uint32_t DOUTR12;          /*!< MDIOS Output Data Register (MDIOS_DOUTR12),     Address offset: 1B0h      */
+  __IO uint32_t DOUTR13;          /*!< MDIOS Output Data Register (MDIOS_DOUTR13),     Address offset: 1B4h      */
+  __IO uint32_t DOUTR14;          /*!< MDIOS Output Data Register (MDIOS_DOUTR14),     Address offset: 1B8h      */
+  __IO uint32_t DOUTR15;          /*!< MDIOS Output Data Register (MDIOS_DOUTR15),     Address offset: 1BCh      */
+  __IO uint32_t DOUTR16;          /*!< MDIOS Output Data Register (MDIOS_DOUTR16),     Address offset: 1C0h      */
+  __IO uint32_t DOUTR17;          /*!< MDIOS Output Data Register (MDIOS_DOUTR17),     Address offset: 1C4h      */
+  __IO uint32_t DOUTR18;          /*!< MDIOS Output Data Register (MDIOS_DOUTR18),     Address offset: 1C8h      */
+  __IO uint32_t DOUTR19;          /*!< MDIOS Output Data Register (MDIOS_DOUTR19),     Address offset: 1CCh      */
+  __IO uint32_t DOUTR20;          /*!< MDIOS Output Data Register (MDIOS_DOUTR20),     Address offset: 1D0h      */
+  __IO uint32_t DOUTR21;          /*!< MDIOS Output Data Register (MDIOS_DOUTR21),     Address offset: 1D4h      */
+  __IO uint32_t DOUTR22;          /*!< MDIOS Output Data Register (MDIOS_DOUTR22),     Address offset: 1D8h      */
+  __IO uint32_t DOUTR23;          /*!< MDIOS Output Data Register (MDIOS_DOUTR23),     Address offset: 1DCh      */
+  __IO uint32_t DOUTR24;          /*!< MDIOS Output Data Register (MDIOS_DOUTR24),     Address offset: 1E0h      */
+  __IO uint32_t DOUTR25;          /*!< MDIOS Output Data Register (MDIOS_DOUTR25),     Address offset: 1E4h      */
+  __IO uint32_t DOUTR26;          /*!< MDIOS Output Data Register (MDIOS_DOUTR26),     Address offset: 1E8h      */
+  __IO uint32_t DOUTR27;          /*!< MDIOS Output Data Register (MDIOS_DOUTR27),     Address offset: 1ECh      */
+  __IO uint32_t DOUTR28;          /*!< MDIOS Output Data Register (MDIOS_DOUTR28),     Address offset: 1F0h      */
+  __IO uint32_t DOUTR29;          /*!< MDIOS Output Data Register (MDIOS_DOUTR29),     Address offset: 1F4h      */
+  __IO uint32_t DOUTR30;          /*!< MDIOS Output Data Register (MDIOS_DOUTR30),     Address offset: 1F8h      */
+  __IO uint32_t DOUTR31;          /*!< MDIOS Output Data Register (MDIOS_DOUTR31),     Address offset: 1FCh      */
+} MDIOS_TypeDef;
+
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define RAMITCM_BASE           0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM  */
+#define FLASHITCM_BASE         0x00200000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory  accessible over ITCM              */
+#define FLASHAXI_BASE          0x08000000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */
+#define RAMDTCM_BASE           0x20000000UL /*!< Base address of : 128KB system data RAM accessible over DTCM                            */
+#define PERIPH_BASE            0x40000000UL /*!< Base address of : AHB/ABP Peripherals                                                   */
+#define BKPSRAM_BASE           0x40024000UL /*!< Base address of : Backup SRAM(4 KB)                                                     */
+#define QSPI_BASE              0x90000000UL /*!< Base address of : QSPI memories  accessible over AXI                                    */
+#define FMC_R_BASE             0xA0000000UL /*!< Base address of : FMC Control registers                                                 */
+#define QSPI_R_BASE            0xA0001000UL /*!< Base address of : QSPI Control  registers                                               */
+#define SRAM1_BASE             0x20020000UL /*!< Base address of : 368KB RAM1 accessible over AXI/AHB                                    */
+#define SRAM2_BASE             0x2007C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
+#define FLASH_END              0x081FFFFFUL /*!< FLASH end address */
+#define FLASH_OTP_BASE         0x1FF0F000UL /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area                            */
+#define FLASH_OTP_END          0x1FF0F41FUL /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area                             */
+
+/* Legacy define */
+#define FLASH_BASE     FLASHAXI_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400UL)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
+#define CAN3_BASE             (APB1PERIPH_BASE + 0x3400UL)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
+#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000UL)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
+#define I2C4_BASE             (APB1PERIPH_BASE + 0x6000UL)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
+#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00UL)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
+#define UART7_BASE            (APB1PERIPH_BASE + 0x7800UL)
+#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00UL)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
+#define SDMMC2_BASE           (APB2PERIPH_BASE + 0x1C00UL)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300UL)
+#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
+#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)
+#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400UL)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800UL)
+#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00UL)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)
+#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800UL)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x0084UL)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x0104UL)
+#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x7400UL)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
+#define MDIOS_BASE            (APB2PERIPH_BASE + 0x7800UL)
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
+#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400UL)
+#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800UL)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
+#define UID_BASE              0x1FF0F420UL                   /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE        0x1FF0F442UL                   /*!< FLASH Size register base address */
+#define PACKAGE_BASE          0x1FF0F7E0UL                   /*!< Package size register base address */
+/* Legacy define */
+#define PACKAGESIZE_BASE      PACKAGE_BASE
+
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)
+#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000UL)
+/*!< AHB2 peripherals */
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
+#define JPEG_BASE           (AHB2PERIPH_BASE + 0x51000UL)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           0xE0042000UL
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE               0x40040000UL
+#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
+
+#define USB_OTG_GLOBAL_BASE                  0x0000UL
+#define USB_OTG_DEVICE_BASE                  0x0800UL
+#define USB_OTG_IN_ENDPOINT_BASE             0x0900UL
+#define USB_OTG_OUT_ENDPOINT_BASE            0x0B00UL
+#define USB_OTG_EP_REG_SIZE                  0x0020UL
+#define USB_OTG_HOST_BASE                    0x0400UL
+#define USB_OTG_HOST_PORT_BASE               0x0440UL
+#define USB_OTG_HOST_CHANNEL_BASE            0x0500UL
+#define USB_OTG_HOST_CHANNEL_SIZE            0x0020UL
+#define USB_OTG_PCGCCTL_BASE                 0x0E00UL
+#define USB_OTG_FIFO_BASE                    0x1000UL
+#define USB_OTG_FIFO_SIZE                    0x1000UL
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC_BASE)
+#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+#define CAN3                ((CAN_TypeDef *) CAN3_BASE)
+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+#define JPEG                ((JPEG_TypeDef *) JPEG_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+#define VREFINT_CAL_ADDR_CMSIS                   ((uint16_t*) (0x1FF0F44A))     /*!>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 0000000..d8031b0
--- /dev/null
+++ b/Drivers/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include     /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 0000000..79a2cac
--- /dev/null
+++ b/Drivers/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include 
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include 
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include 
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include 
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 0000000..1bd41a4
--- /dev/null
+++ b/Drivers/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Drivers/CMSIS/Include/cmsis_iccarm.h
new file mode 100644
index 0000000..3c90a2c
--- /dev/null
+++ b/Drivers/CMSIS/Include/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include 
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Drivers/CMSIS/Include/cmsis_version.h
new file mode 100644
index 0000000..ae3f2e3
--- /dev/null
+++ b/Drivers/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h
new file mode 100644
index 0000000..ec76ab2
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_armv8mbl.h
@@ -0,0 +1,1918 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h
new file mode 100644
index 0000000..2d0f106
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_armv8mml.h
@@ -0,0 +1,2927 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000..6f82227
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm0.h
@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000..b9377e8
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,1083 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h
new file mode 100644
index 0000000..fd1c407
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm1.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h
new file mode 100644
index 0000000..8202a8d
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm23.h
@@ -0,0 +1,1993 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+	
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000..b0dfbd3
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1941 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h
new file mode 100644
index 0000000..02f82e2
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm33.h
@@ -0,0 +1,3002 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.9
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_PCS_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..308b868
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h
new file mode 100644
index 0000000..ada6c2a
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2671 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000..9086c64
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_sc000.h
@@ -0,0 +1,1022 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000..665822d
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1915 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h
new file mode 100644
index 0000000..7d4b600
--- /dev/null
+++ b/Drivers/CMSIS/Include/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h
new file mode 100644
index 0000000..99ee9f9
--- /dev/null
+++ b/Drivers/CMSIS/Include/mpu_armv8.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h
new file mode 100644
index 0000000..d4c1474
--- /dev/null
+++ b/Drivers/CMSIS/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include 
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/Drivers/CMSIS/LICENSE.txt b/Drivers/CMSIS/LICENSE.txt
new file mode 100644
index 0000000..c0ee812
--- /dev/null
+++ b/Drivers/CMSIS/LICENSE.txt
@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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diff --git a/Drivers/CMSIS/Lib/ARM/arm_cortexM7b_math.lib b/Drivers/CMSIS/Lib/ARM/arm_cortexM7b_math.lib
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diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Compiler/EventRecorderConf.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Compiler/EventRecorderConf.h
new file mode 100644
index 0000000..5958233
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Compiler/EventRecorderConf.h
@@ -0,0 +1,44 @@
+/*------------------------------------------------------------------------------
+ * MDK - Component ::Event Recorder
+ * Copyright (c) 2016 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    EventRecorderConf.h
+ * Purpose: Event Recorder Configuration
+ * Rev.:    V1.0.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Event Recorder
+
+//   Number of Records
+//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
+//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
+//     <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288
+//     <1048576=>1048576
+//   Configure size of Event Record Buffer (each record is 16 bytes)
+//   Must be 2^n (min=8, max=1048576)
+#define EVENT_RECORD_COUNT      64U
+
+//   Time Stamp Source
+//      <0=> DWT Cycle Counter  <1=> SysTick
+//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)
+//   Selects source for 32-bit time stamp
+#define EVENT_TIMESTAMP_SOURCE  1
+
+//   SysTick Configuration
+//   Configure values when Time Stamp Source is set to SysTick
+
+//     SysTick Input Clock Frequency [Hz] <1-1000000000>
+//     Defines SysTick input clock (typical identical with processor clock)
+#define SYSTICK_CLOCK           100000000U
+
+//     SysTick Interrupt Period [us] <1-1000000000>
+//     Defines time period of the SysTick timer interrupt
+#define SYSTICK_PERIOD_US       1000U
+
+//   
+
+// 
+
+//------------- <<< end of configuration section >>> ---------------------------
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h
new file mode 100644
index 0000000..182fb76
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h
@@ -0,0 +1,24 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_cifar10' 
+ * Target:  'ARMCM0' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM0.h"
+
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h
new file mode 100644
index 0000000..2aa5627
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h
@@ -0,0 +1,22 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_cifar10' 
+ * Target:  'ARMCM3' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM3.h"
+
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h
new file mode 100644
index 0000000..bdf6fb9
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h
@@ -0,0 +1,22 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_cifar10' 
+ * Target:  'ARMCM4_FP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM4_FP.h"
+
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h
new file mode 100644
index 0000000..9d43970
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h
@@ -0,0 +1,22 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_cifar10' 
+ * Target:  'ARMCM7_SP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM7_SP.h"
+
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp
new file mode 100644
index 0000000..ee1083b
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp
@@ -0,0 +1,196 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2018 Arm Limited. All rights reserved.
+*
+*
+* Project:       CMSIS NN Library
+* Title:         arm_nnexamples_cifar10.cpp
+*
+* Description:   Convolutional Neural Network Example
+*
+* Target Processor: Cortex-M4/Cortex-M7
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of Arm LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup CNNExample Convolutional Neural Network Example
+ *
+ * \par Description:
+ * \par
+ * Demonstrates a convolutional neural network (CNN) example with the use of convolution,
+ * ReLU activation, pooling and fully-connected functions.
+ *
+ * \par Model definition:
+ * \par
+ * The CNN used in this example is based on CIFAR-10 example from Caffe [1]. 
+ * The neural network consists
+ * of 3 convolution layers interspersed by ReLU activation and max pooling layers, followed by a 
+ * fully-connected layer at the end. The input to the network is a 32x32 pixel color image, which will 
+ * be classified into one of the 10 output classes. 
+ * This example model implementation needs 32.3 KB to store weights, 40 KB for activations and 
+ * 3.1 KB for storing the \c im2col data.
+ *
+ * \image html CIFAR10_CNN.gif "Neural Network model definition"
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c conv1_wt, \c conv2_wt, \c conv3_wt are convolution layer weight matrices
+ * \li \c conv1_bias, \c conv2_bias, \c conv3_bias are convolution layer bias arrays
+ * \li \c ip1_wt, ip1_bias point to fully-connected layer weights and biases
+ * \li \c input_data points to the input image data
+ * \li \c output_data points to the classification output
+ * \li \c col_buffer is a buffer to store the \c im2col output
+ * \li \c scratch_buffer is used to store the activation data (intermediate layer outputs)
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_convolve_HWC_q7_RGB()
+ * - arm_convolve_HWC_q7_fast()
+ * - arm_relu_q7()
+ * - arm_maxpool_q7_HWC()
+ * - arm_avepool_q7_HWC()
+ * - arm_fully_connected_q7_opt()
+ * - arm_fully_connected_q7()
+ *
+ *  Refer  
+ * \link arm_nnexamples_cifar10.cpp \endlink
+ *
+ * \par [1] https://github.com/BVLC/caffe
+ */
+
+#include 
+#include 
+#include "arm_math.h"
+#include "arm_nnexamples_cifar10_parameter.h"
+#include "arm_nnexamples_cifar10_weights.h"
+
+#include "arm_nnfunctions.h"
+#include "arm_nnexamples_cifar10_inputs.h"
+
+#ifdef _RTE_
+#include "RTE_Components.h"
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+#endif
+
+// include the input and weights
+
+static q7_t conv1_wt[CONV1_IM_CH * CONV1_KER_DIM * CONV1_KER_DIM * CONV1_OUT_CH] = CONV1_WT;
+static q7_t conv1_bias[CONV1_OUT_CH] = CONV1_BIAS;
+
+static q7_t conv2_wt[CONV2_IM_CH * CONV2_KER_DIM * CONV2_KER_DIM * CONV2_OUT_CH] = CONV2_WT;
+static q7_t conv2_bias[CONV2_OUT_CH] = CONV2_BIAS;
+
+static q7_t conv3_wt[CONV3_IM_CH * CONV3_KER_DIM * CONV3_KER_DIM * CONV3_OUT_CH] = CONV3_WT;
+static q7_t conv3_bias[CONV3_OUT_CH] = CONV3_BIAS;
+
+static q7_t ip1_wt[IP1_DIM * IP1_OUT] = IP1_WT;
+static q7_t ip1_bias[IP1_OUT] = IP1_BIAS;
+
+/* Here the image_data should be the raw uint8 type RGB image in [RGB, RGB, RGB ... RGB] format */
+uint8_t   image_data[CONV1_IM_CH * CONV1_IM_DIM * CONV1_IM_DIM] = IMG_DATA;
+q7_t      output_data[IP1_OUT];
+
+//vector buffer: max(im2col buffer,average pool buffer, fully connected buffer)
+q7_t      col_buffer[2 * 5 * 5 * 32 * 2];
+
+q7_t      scratch_buffer[32 * 32 * 10 * 4];
+
+int main()
+{
+  #ifdef RTE_Compiler_EventRecorder
+  EventRecorderInitialize (EventRecordAll, 1);  // initialize and start Event Recorder
+  #endif
+
+  printf("start execution\n");
+  /* start the execution */
+
+  q7_t     *img_buffer1 = scratch_buffer;
+  q7_t     *img_buffer2 = img_buffer1 + 32 * 32 * 32;
+
+  /* input pre-processing */
+  int mean_data[3] = INPUT_MEAN_SHIFT;
+  unsigned int scale_data[3] = INPUT_RIGHT_SHIFT;
+  for (int i=0;i<32*32*3; i+=3) {
+    img_buffer2[i] =   (q7_t)__SSAT( ((((int)image_data[i]   - mean_data[0])<<7) + (0x1<<(scale_data[0]-1)))
+                             >> scale_data[0], 8);
+    img_buffer2[i+1] = (q7_t)__SSAT( ((((int)image_data[i+1] - mean_data[1])<<7) + (0x1<<(scale_data[1]-1)))
+                             >> scale_data[1], 8);
+    img_buffer2[i+2] = (q7_t)__SSAT( ((((int)image_data[i+2] - mean_data[2])<<7) + (0x1<<(scale_data[2]-1)))
+                             >> scale_data[2], 8);
+  }
+  
+  // conv1 img_buffer2 -> img_buffer1
+  arm_convolve_HWC_q7_RGB(img_buffer2, CONV1_IM_DIM, CONV1_IM_CH, conv1_wt, CONV1_OUT_CH, CONV1_KER_DIM, CONV1_PADDING,
+                          CONV1_STRIDE, conv1_bias, CONV1_BIAS_LSHIFT, CONV1_OUT_RSHIFT, img_buffer1, CONV1_OUT_DIM,
+                          (q15_t *) col_buffer, NULL);
+
+  arm_relu_q7(img_buffer1, CONV1_OUT_DIM * CONV1_OUT_DIM * CONV1_OUT_CH);
+
+  // pool1 img_buffer1 -> img_buffer2
+  arm_maxpool_q7_HWC(img_buffer1, CONV1_OUT_DIM, CONV1_OUT_CH, POOL1_KER_DIM,
+                     POOL1_PADDING, POOL1_STRIDE, POOL1_OUT_DIM, NULL, img_buffer2);
+
+  // conv2 img_buffer2 -> img_buffer1
+  arm_convolve_HWC_q7_fast(img_buffer2, CONV2_IM_DIM, CONV2_IM_CH, conv2_wt, CONV2_OUT_CH, CONV2_KER_DIM,
+                           CONV2_PADDING, CONV2_STRIDE, conv2_bias, CONV2_BIAS_LSHIFT, CONV2_OUT_RSHIFT, img_buffer1,
+                           CONV2_OUT_DIM, (q15_t *) col_buffer, NULL);
+
+  arm_relu_q7(img_buffer1, CONV2_OUT_DIM * CONV2_OUT_DIM * CONV2_OUT_CH);
+
+  // pool2 img_buffer1 -> img_buffer2
+  arm_maxpool_q7_HWC(img_buffer1, CONV2_OUT_DIM, CONV2_OUT_CH, POOL2_KER_DIM,
+                     POOL2_PADDING, POOL2_STRIDE, POOL2_OUT_DIM, col_buffer, img_buffer2);
+
+// conv3 img_buffer2 -> img_buffer1
+  arm_convolve_HWC_q7_fast(img_buffer2, CONV3_IM_DIM, CONV3_IM_CH, conv3_wt, CONV3_OUT_CH, CONV3_KER_DIM,
+                           CONV3_PADDING, CONV3_STRIDE, conv3_bias, CONV3_BIAS_LSHIFT, CONV3_OUT_RSHIFT, img_buffer1,
+                           CONV3_OUT_DIM, (q15_t *) col_buffer, NULL);
+
+  arm_relu_q7(img_buffer1, CONV3_OUT_DIM * CONV3_OUT_DIM * CONV3_OUT_CH);
+
+  // pool3 img_buffer-> img_buffer2
+  arm_maxpool_q7_HWC(img_buffer1, CONV3_OUT_DIM, CONV3_OUT_CH, POOL3_KER_DIM,
+                     POOL3_PADDING, POOL3_STRIDE, POOL3_OUT_DIM, col_buffer, img_buffer2);
+
+  arm_fully_connected_q7_opt(img_buffer2, ip1_wt, IP1_DIM, IP1_OUT, IP1_BIAS_LSHIFT, IP1_OUT_RSHIFT, ip1_bias,
+                             output_data, (q15_t *) img_buffer1);
+
+  arm_softmax_q7(output_data, 10, output_data);
+
+  for (int i = 0; i < 10; i++)
+  {
+      printf("%d: %d\n", i, output_data[i]);
+  }
+
+  return 0;
+}
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h
new file mode 100644
index 0000000..4ff8dc2
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h
@@ -0,0 +1,6 @@
+/* Here are two different test images */
+
+//#define IMG_DATA {158,112,49,159,111,47,165,116,51,166,118,53,160,112,46,156,109,41,162,115,47,159,113,45,158,111,44,159,113,41,161,116,41,160,111,52,161,111,49,166,117,41,169,117,45,170,119,44,167,117,40,162,113,38,160,111,39,160,112,43,156,109,44,149,107,45,150,107,45,148,106,43,149,107,44,143,101,39,140,98,43,141,97,41,143,97,38,137,95,36,126,91,36,116,85,33,152,112,51,151,110,40,159,114,45,166,116,56,162,112,49,160,113,43,164,117,47,162,114,45,163,116,46,156,110,38,155,111,41,159,110,54,163,113,52,170,119,41,171,117,40,171,115,33,169,115,30,160,111,33,154,112,41,151,115,50,145,110,53,139,104,55,140,102,52,141,100,48,149,105,50,147,102,46,145,102,45,142,97,38,143,98,34,136,95,31,125,91,32,119,88,34,151,110,47,151,109,33,158,111,36,167,111,48,160,106,42,163,115,44,165,117,45,165,117,45,163,115,43,162,115,43,158,114,48,157,109,57,161,111,51,166,115,38,167,114,37,169,113,35,170,116,39,159,114,47,145,111,54,121,96,49,110,90,52,98,78,50,101,77,47,114,85,50,120,86,48,134,96,55,143,103,51,140,99,39,142,99,35,139,98,34,130,95,34,120,89,33,155,107,40,155,110,32,160,109,31,174,112,44,167,110,43,167,117,46,169,120,48,169,119,48,165,115,44,165,117,45,167,123,57,191,146,95,177,130,75,157,111,41,162,115,47,164,114,54,158,112,58,149,111,67,104,80,47,103,87,65,98,90,76,92,90,84,80,75,66,74,63,50,86,70,52,83,62,39,113,85,45,132,98,46,140,102,43,140,101,39,136,99,39,127,94,36,155,107,41,156,114,48,161,115,49,170,114,47,169,114,43,163,113,40,169,120,47,166,116,44,164,113,41,164,116,42,173,128,59,246,214,164,195,156,107,151,114,56,146,111,60,142,108,71,111,80,50,78,53,31,85,69,56,113,103,98,112,110,111,106,114,118,97,102,105,93,94,93,74,72,67,84,78,70,85,73,47,105,83,45,128,96,48,138,101,46,133,94,36,129,93,36,148,109,54,133,104,64,130,100,57,147,112,53,161,115,44,165,113,39,167,116,41,167,115,41,163,111,37,165,116,39,163,118,42,180,138,85,157,122,78,128,102,58,97,75,43,66,50,31,69,58,43,66,56,45,89,83,76,118,113,110,122,121,120,119,122,122,114,116,116,94,96,96,99,100,97,91,91,86,58,58,47,67,58,37,108,84,49,140,105,58,138,98,44,134,95,40,127,100,57,109,95,80,47,37,17,88,74,28,153,117,48,170,118,43,168,115,40,170,118,43,169,117,42,166,116,37,164,120,39,147,107,52,129,98,59,127,108,75,100,87,70,68,67,57,78,83,72,72,75,64,83,84,74,132,130,121,146,142,132,124,118,108,105,99,90,107,102,94,115,111,103,85,83,77,63,71,69,46,47,39,79,61,36,132,98,58,141,99,48,134,93,39,131,115,90,99,96,92,42,43,38,70,64,41,143,111,56,167,117,42,165,114,36,168,116,39,171,119,49,161,113,51,140,109,51,120,94,49,130,110,77,144,131,107,116,106,93,88,87,79,91,95,88,85,88,82,77,77,69,124,118,107,163,153,140,136,124,112,102,93,81,106,98,88,100,93,84,85,81,74,54,60,58,49,53,49,57,47,32,107,83,50,138,103,51,136,97,39,170,161,144,103,105,105,54,58,59,124,121,113,153,124,82,161,113,43,163,117,41,166,122,50,165,121,66,174,135,95,113,89,59,125,105,78,157,141,121,156,143,128,121,111,101,86,80,74,82,81,77,84,85,82,80,78,73,81,71,61,138,125,112,146,135,123,113,103,93,87,79,70,83,77,69,86,82,76,71,73,67,56,57,53,40,35,27,74,59,35,133,106,59,137,103,45,180,176,163,134,139,143,94,100,105,154,154,149,174,149,112,158,116,51,156,116,47,153,118,60,207,180,146,237,214,198,207,180,166,156,131,119,174,153,145,148,131,125,125,110,107,93,85,79,86,84,79,74,74,71,59,57,53,76,68,58,137,125,112,143,133,122,133,124,114,106,98,89,86,81,74,87,85,78,84,85,78,75,76,71,50,49,43,40,30,15,95,75,44,132,103,57,183,183,175,108,116,122,142,151,158,165,169,168,177,156,122,155,112,50,159,118,51,122,89,47,213,197,179,237,224,226,220,191,188,164,135,131,183,159,155,156,137,132,125,108,104,120,111,104,78,76,69,80,80,77,45,44,40,91,85,77,175,165,154,157,147,137,155,147,138,107,100,92,87,83,77,103,102,96,88,88,79,78,79,73,59,59,59,41,36,33,59,46,31,104,81,46,188,191,189,100,108,116,135,144,153,170,175,178,187,167,136,166,120,59,173,123,55,134,93,44,117,95,80,194,182,188,199,171,164,170,142,133,185,161,151,189,171,159,134,119,106,117,107,95,102,98,89,84,84,79,38,38,34,125,121,113,210,201,192,160,152,142,146,139,130,93,89,82,83,80,75,94,93,88,104,104,94,85,87,81,73,75,78,55,53,55,62,55,48,76,56,26,189,194,194,90,96,105,127,134,144,175,180,185,174,156,133,166,123,68,178,123,53,159,109,47,97,68,44,168,154,152,168,144,126,137,114,94,186,166,148,216,202,183,160,149,129,123,113,98,120,114,105,115,114,109,50,50,47,150,147,140,194,187,178,155,149,140,123,118,111,91,88,83,84,83,79,84,84,80,95,95,85,86,87,81,84,87,89,73,73,73,79,74,64,73,55,24,189,192,193,93,95,103,152,154,163,185,188,192,119,110,98,136,106,66,173,124,58,167,116,50,103,72,39,147,132,120,145,125,103,167,149,127,189,174,155,226,216,200,180,172,157,141,131,117,126,117,107,117,114,109,71,71,68,154,152,147,186,181,174,149,144,136,114,110,104,87,85,80,80,80,76,72,73,70,80,80,72,99,100,94,100,101,99,90,88,81,97,89,69,94,73,34,194,196,196,108,107,112,168,167,172,186,186,188,105,109,109,99,89,67,156,119,62,167,122,55,100,74,34,115,106,88,138,123,103,198,185,169,190,180,169,172,165,159,145,140,140,154,143,134,146,136,125,103,100,95,71,71,70,152,152,149,179,175,170,137,133,127,130,128,122,110,109,105,85,86,83,91,93,91,95,96,90,109,110,104,115,116,111,100,96,80,97,85,53,117,95,47,197,197,197,132,129,136,172,167,174,184,178,181,130,137,142,78,83,77,140,120,88,155,125,77,115,94,52,130,120,93,143,131,116,230,221,211,242,236,230,145,138,137,135,130,130,131,121,112,121,112,101,108,104,95,95,88,75,144,134,118,168,159,146,152,147,138,112,108,101,87,85,80,71,72,68,87,88,87,105,104,99,112,109,99,120,110,93,103,86,54,121,96,48,136,104,48,203,203,204,146,146,160,168,164,178,191,182,188,168,170,172,78,86,90,126,125,126,138,126,113,138,121,82,96,80,37,154,143,133,173,163,155,162,152,141,140,132,117,113,106,88,113,106,90,101,101,92,105,101,87,112,90,58,171,143,104,156,138,109,148,141,126,135,130,118,109,105,97,78,76,72,79,79,77,94,93,94,101,91,82,107,83,55,125,88,45,151,108,55,144,104,46,214,215,215,163,166,180,164,167,184,183,184,194,176,182,186,94,102,105,96,96,102,156,149,145,148,137,111,106,93,61,129,116,105,118,105,95,114,102,89,116,105,89,102,91,73,115,110,98,86,91,88,101,103,95,144,128,102,118,96,64,68,56,32,128,120,105,133,126,115,75,69,61,60,56,51,58,56,53,71,70,65,102,93,78,116,94,64,143,112,68,150,116,64,140,110,54,212,211,205,178,184,192,167,175,189,173,181,193,176,184,188,124,131,133,86,88,96,141,139,143,153,148,141,135,128,111,104,90,80,77,64,55,134,121,108,124,111,96,129,117,100,147,143,133,85,92,93,92,96,93,150,139,120,132,117,93,117,109,92,107,99,86,75,68,58,64,59,52,44,41,39,65,62,60,86,69,40,133,105,59,155,119,62,160,120,54,154,115,45,151,111,46,199,192,180,187,189,187,171,176,181,174,179,185,177,182,184,144,149,152,86,90,99,119,121,132,122,124,130,137,136,135,144,134,126,70,59,51,129,118,108,108,97,86,145,134,123,184,176,168,116,118,118,73,75,73,131,119,103,137,124,105,134,129,118,89,86,78,51,49,44,52,51,50,47,49,52,90,90,93,121,91,60,163,118,68,171,121,64,164,113,52,158,111,50,149,107,46,165,156,146,195,193,187,179,178,175,177,173,172,181,181,180,152,157,160,99,103,111,131,135,146,171,175,185,103,105,111,93,90,87,80,77,73,93,90,86,122,118,116,178,173,173,191,182,177,150,148,148,100,100,101,89,78,66,87,77,63,60,61,57,46,52,54,38,46,51,24,33,41,46,57,69,60,71,83,108,100,75,144,125,82,144,123,76,128,109,61,127,113,69,120,105,63,117,120,124,195,200,200,177,178,176,178,169,168,181,179,179,138,144,147,83,87,91,150,153,159,245,247,250,219,222,225,133,140,144,134,141,147,149,156,164,176,182,192,190,196,208,194,192,197,168,172,181,125,133,143,110,109,109,61,62,62,35,49,58,34,54,68,49,70,87,58,81,102,61,85,110,58,84,111,69,99,122,72,101,119,78,104,120,69,96,112,59,92,112,55,90,115,79,105,133,175,197,213,174,183,192,176,172,177,177,177,182,140,146,150,109,112,113,211,211,209,253,252,247,252,253,252,208,224,232,124,143,157,114,132,149,124,141,162,116,133,156,122,133,152,104,124,148,68,93,119,68,87,104,60,82,101,52,84,111,50,84,110,51,85,115,56,93,125,56,94,131,51,91,130,43,96,135,51,104,141,59,108,142,48,97,132,43,97,137,42,95,132,41,89,135,96,137,168,144,168,188,168,174,188,178,182,192,165,170,174,165,166,164,246,245,237,253,251,241,227,231,228,110,136,153,60,88,111,53,80,105,49,76,105,49,75,107,48,72,101,45,79,115,42,81,120,46,81,113,42,82,116,38,86,125,46,90,125,46,89,126,43,87,128,42,89,132,46,93,139,46,94,137,50,96,137,55,96,135,53,94,134,51,95,139,45,90,133,29,91,141,29,87,130,59,102,134,131,153,176,166,179,191,132,136,137,194,189,181,254,250,242,241,245,245,141,159,175,61,94,127,50,84,118,50,84,119,51,85,121,49,83,120,50,84,116,47,86,117,42,84,117,39,82,115,34,79,113,35,83,120,39,86,125,38,85,125,42,89,130,45,92,134,56,103,145,62,103,142,59,101,142,56,102,146,50,99,144,46,94,140,51,103,149,48,111,162,30,94,140,34,85,124,73,106,136,128,148,167,128,136,143,215,213,209,255,253,249,187,198,205,66,93,118,54,91,128,50,88,125,52,90,127,52,90,127,46,83,121,45,82,115,43,82,113,41,81,112,36,80,113,39,83,117,40,86,123,40,89,131,43,92,134,46,95,138,59,108,150,62,110,152,64,109,147,59,108,149,54,108,154,50,105,152,70,123,167,83,137,182,52,114,165,35,99,147,31,86,130,41,83,122,66,95,126,128,145,164,224,229,234,240,245,247,124,143,153,58,92,114,49,87,123,56,94,131,54,92,129,44,82,119,44,82,119,47,83,119,46,84,119,43,83,119,43,86,123,44,88,127,44,90,131,45,97,141,54,106,150,58,110,154,54,105,150,46,97,141,43,95,140,36,91,138,51,108,158,73,130,178,85,138,182,76,125,169,50,110,162,35,98,149,29,89,138,35,86,133,44,83,126,78,106,138,202,219,233,211,228,234,97,126,140,65,104,126,54,94,129,48,87,124,58,97,133,48,87,123,40,80,116,45,82,119,47,84,122,48,87,126,47,89,130,46,89,132,51,97,140,39,92,138,39,93,139,48,102,148,47,101,147,39,93,139,28,85,133,40,101,153,67,129,182,67,126,176,46,98,142,51,96,139,50,108,161,35,97,147,32,92,143,33,88,141,41,88,138,46,84,125,104,133,159,170,197,211,64,100,119,54,97,121,52,94,128,53,95,130,61,103,139,58,100,135,54,96,131,45,83,120,42,79,118,41,80,120,46,88,130,49,92,135,46,92,136,42,95,139,40,93,138,39,92,136,37,90,135,40,93,138,44,102,151,63,125,178,47,110,164,31,90,140,15,60,103,51,93,136,68,124,177,42,100,148,31,88,137,38,91,146,37,87,139,43,89,132,42,79,113,71,107,133,49,89,114,31,77,105,27,71,105,38,82,117,49,93,128,56,100,135,58,102,137,53,92,128,56,94,131,60,99,137,57,99,139,53,97,138,50,95,137,45,94,136,39,88,131,33,83,125,42,91,133,62,112,154,79,132,179,73,131,181,56,116,168,38,97,146,13,64,108,40,85,127,61,116,168,49,102,148,35,85,132,43,91,143,39,90,139,42,92,134,44,88,125,40,81,112,42,85,115,27,72,104,23,67,102,30,74,109,27,71,106,29,73,108,36,80,115,47,86,120,56,95,128,62,101,135,66,109,144,75,119,156,69,113,152,49,95,134,43,88,127,43,88,127,60,105,144,85,130,170,109,156,197,93,145,190,60,115,164,26,82,130,29,82,126,20,64,107,54,107,160,56,105,149,45,89,132,43,86,134,40,89,134,40,92,132,40,87,123,38,81,115,36,79,114,26,69,105,22,66,101,29,73,108,25,69,104,29,73,108,19,63,98,18,58,89,32,70,100,47,87,118,61,104,137,74,119,152,66,111,145,53,96,131,52,95,130,45,87,123,67,109,145,89,131,167,105,146,182,89,135,175,48,99,145,24,77,124,34,84,129,21,67,110}
+
+
+#define IMG_DATA {235,235,235,231,231,231,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,232,233,233,231,233,232,231,233,231,233,233,230,233,232,232,232,234,232,231,234,232,232,232,233,233,230,232,233,231,233,233,233,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,232,232,232,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,237,234,233,236,234,233,236,236,234,234,236,234,234,235,237,234,234,238,235,236,237,236,236,235,236,236,234,236,236,236,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,235,235,235,237,237,237,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,234,234,236,233,231,236,234,231,235,235,234,234,235,236,227,230,233,231,235,238,231,233,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,234,233,233,230,232,232,231,228,230,232,223,226,231,186,192,197,209,216,219,207,210,213,228,228,230,236,235,235,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,237,237,237,234,234,234,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,236,238,236,233,237,237,219,225,230,203,210,219,163,172,179,195,205,208,214,218,221,230,229,232,237,235,237,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,239,239,238,236,235,235,236,235,235,236,235,235,236,235,235,236,235,235,235,236,235,235,235,235,234,234,234,235,235,235,237,236,236,237,236,236,234,235,236,232,233,234,235,237,237,229,231,232,208,216,218,194,205,210,185,198,207,174,188,200,165,179,189,184,196,202,207,215,220,226,228,232,236,235,237,236,236,235,236,236,235,236,236,235,236,236,236,237,237,237,237,237,237,237,237,237,228,229,229,228,227,228,232,230,231,231,228,230,234,232,233,237,236,236,237,237,235,236,237,235,237,235,236,237,235,236,239,236,237,239,237,238,225,229,230,224,228,229,233,237,238,221,226,228,183,197,204,161,180,190,159,180,191,154,176,190,144,163,177,143,159,171,156,169,177,198,206,211,233,238,239,236,237,234,235,236,233,235,235,235,235,236,236,236,238,237,237,237,237,239,237,238,212,220,222,224,230,233,230,234,238,227,232,234,229,234,234,234,237,236,237,238,235,238,237,236,239,237,238,239,237,238,239,236,237,240,238,239,201,204,203,219,222,221,233,236,235,214,218,218,193,204,210,185,201,210,184,201,211,173,191,203,165,182,196,159,174,187,162,176,185,186,199,204,229,239,240,234,239,238,233,238,237,233,238,238,234,239,238,236,239,238,237,239,238,238,238,238,216,234,241,221,236,243,225,238,246,225,239,243,227,240,240,231,238,237,236,237,235,238,236,235,238,236,237,238,236,237,237,237,237,239,239,239,197,198,196,220,221,218,233,234,231,230,231,229,209,213,217,209,216,222,219,228,235,208,218,227,209,221,234,210,224,235,217,233,240,218,235,241,225,240,243,228,238,240,228,239,240,230,240,240,230,240,239,235,240,239,237,240,239,238,238,238,118,140,149,119,138,148,124,142,153,136,155,161,172,188,191,225,234,233,235,236,233,237,234,232,236,233,234,235,235,235,235,237,236,233,237,235,214,216,214,226,228,226,232,234,232,236,237,236,228,230,232,227,230,235,231,236,241,225,232,239,225,237,247,217,233,243,201,219,226,185,204,211,172,189,195,167,179,186,167,180,185,186,199,201,223,235,235,235,241,239,236,240,239,238,240,239,109,130,141,103,121,133,108,125,137,111,127,137,146,159,165,222,229,231,227,228,225,229,226,224,236,232,233,234,234,234,231,236,234,230,237,235,229,234,235,231,235,236,232,237,238,230,235,236,231,236,238,231,237,240,229,237,241,223,232,238,191,206,213,164,184,191,146,165,172,137,156,163,134,149,159,128,140,153,121,133,143,149,162,166,216,228,229,234,241,239,235,240,238,237,240,239,195,212,224,188,202,215,199,211,224,200,211,223,209,217,227,223,227,231,213,213,211,211,209,206,216,213,214,220,222,222,219,226,225,210,221,219,209,219,223,211,221,225,216,225,230,220,229,233,225,234,237,226,236,239,225,237,241,218,231,237,183,204,208,175,198,203,181,200,207,178,194,202,186,197,211,170,178,196,142,151,164,185,195,202,219,230,233,231,240,238,234,241,239,236,240,239,193,207,222,191,202,217,202,211,224,214,217,234,223,225,241,214,219,227,203,208,208,171,174,174,177,180,183,207,213,214,174,184,188,98,112,121,93,114,126,101,121,132,111,129,139,122,138,147,137,152,161,153,167,174,202,216,220,223,236,237,218,232,235,220,233,238,223,234,240,217,226,233,221,228,237,212,219,229,196,203,212,222,230,237,219,227,234,221,230,233,232,239,242,235,241,242,113,130,152,111,125,147,113,125,141,125,131,151,138,145,165,170,182,193,191,201,205,190,199,204,208,219,226,216,230,234,158,172,183,54,71,92,45,70,91,49,73,91,53,73,90,66,84,98,102,114,129,159,168,179,221,227,233,234,239,241,233,237,241,227,231,237,223,228,233,207,211,217,202,208,212,211,218,220,212,219,223,199,206,214,179,186,196,188,197,205,211,221,227,221,231,234,61,81,108,69,86,114,63,79,100,68,85,102,123,141,155,139,155,164,151,157,164,195,200,207,214,228,234,206,223,228,163,180,190,103,121,138,95,112,131,101,117,135,138,151,168,181,192,207,207,212,223,221,222,232,219,219,227,205,203,212,183,186,195,158,166,174,147,154,163,131,138,147,125,133,140,130,139,144,136,146,152,133,142,151,128,137,147,138,153,160,182,197,203,197,212,216,40,53,77,58,70,94,85,98,116,127,144,153,132,151,156,96,107,110,119,115,118,163,158,161,173,180,182,184,194,197,182,194,198,181,193,200,183,194,202,198,209,217,218,228,236,200,210,217,174,181,186,159,165,172,145,150,159,132,136,149,116,125,138,98,111,123,94,106,118,99,111,123,105,118,128,107,121,130,122,135,145,138,151,161,150,164,174,157,174,184,188,206,213,185,203,208,13,15,35,26,29,47,134,140,151,206,216,220,138,150,150,118,123,123,141,133,134,172,162,162,181,181,180,207,209,211,220,224,225,228,234,233,224,234,232,230,241,240,226,238,238,176,189,190,144,159,163,138,154,162,142,158,170,145,163,177,154,171,187,149,165,182,149,165,182,154,171,187,157,174,189,160,177,191,173,190,204,187,204,217,190,207,218,178,196,208,165,183,193,157,175,183,5,5,24,58,62,79,200,207,217,225,232,239,197,205,212,199,207,211,212,212,218,226,224,229,229,230,237,233,236,246,232,238,245,230,238,239,209,221,220,223,238,239,221,238,241,210,228,234,198,217,228,180,200,214,193,216,230,188,213,229,189,212,231,194,214,234,192,212,232,184,204,224,172,193,212,171,191,209,161,181,197,144,165,179,136,156,169,131,146,161,128,143,158,138,154,165,39,45,71,145,155,179,190,204,222,186,196,216,184,197,217,192,211,229,194,211,230,194,208,227,194,206,227,191,203,228,192,207,228,190,207,221,177,193,207,180,198,215,154,176,193,147,169,188,145,161,184,156,171,195,146,163,186,113,133,156,114,137,161,132,157,180,126,150,173,111,135,158,92,115,138,91,112,135,93,114,133,94,116,131,105,125,140,121,133,151,129,141,158,129,142,156,122,135,161,162,179,207,143,160,194,137,154,189,131,152,187,128,152,190,127,150,192,130,150,193,131,150,192,128,147,190,127,147,189,129,149,189,129,149,188,124,145,186,104,126,163,100,122,154,102,120,154,118,134,170,112,128,163,94,109,145,94,112,148,94,117,153,87,112,144,83,103,136,80,97,130,83,103,134,93,111,139,101,117,141,108,121,144,115,125,146,121,133,148,130,144,156,73,87,109,76,90,113,77,90,122,80,93,127,84,98,134,87,102,142,87,102,147,90,105,150,94,111,152,102,119,160,107,124,165,113,131,172,115,137,181,118,136,186,118,132,180,120,133,175,115,136,172,110,133,168,106,127,163,100,119,155,95,109,148,85,101,139,79,97,132,80,92,127,80,94,129,77,100,133,80,100,129,82,98,122,92,104,126,113,119,138,125,135,146,136,149,156,13,25,41,3,11,25,9,16,35,18,26,48,18,26,52,21,25,56,20,25,58,22,30,61,26,36,62,34,43,70,42,51,77,48,59,87,52,69,106,60,75,121,66,77,126,70,79,126,71,87,127,72,88,126,67,81,120,60,72,112,55,67,106,53,68,104,53,69,103,57,69,102,57,71,105,57,78,110,72,89,115,87,100,119,104,113,128,120,124,136,130,136,141,137,146,149,36,46,55,11,16,20,8,13,19,32,44,53,36,45,58,22,25,41,8,11,30,3,8,24,1,4,17,0,2,15,0,2,15,0,4,20,6,13,42,5,18,56,1,19,60,3,23,62,13,29,71,24,38,81,21,33,77,21,31,76,21,38,78,22,44,79,30,50,83,39,58,90,57,70,101,85,90,118,113,115,138,123,123,138,116,115,125,122,123,128,134,139,137,153,160,158,35,41,45,26,27,26,13,19,18,27,41,41,71,81,84,70,70,76,49,50,57,27,31,37,15,15,21,5,5,11,2,2,7,0,0,7,17,17,35,57,64,91,31,50,78,10,36,62,4,30,60,4,30,62,7,30,63,14,35,69,25,43,74,41,55,83,62,71,99,86,97,123,122,124,146,144,131,149,132,120,135,114,105,114,117,111,116,132,134,133,146,152,146,172,179,175,16,15,17,13,10,9,4,10,8,3,12,11,45,44,46,65,52,57,54,43,47,36,33,35,18,18,20,4,4,7,2,2,4,0,1,3,7,8,15,118,117,134,161,158,179,131,128,148,112,112,131,105,105,125,105,103,124,109,105,127,118,107,126,138,115,133,154,126,144,151,126,141,127,106,116,105,86,91,106,94,97,120,116,116,129,130,129,142,147,144,164,172,165,184,194,190,40,40,35,12,10,7,0,3,3,0,4,4,12,6,7,30,12,17,32,12,17,21,10,12,7,6,7,2,1,3,2,1,2,3,2,3,0,0,2,68,58,64,182,128,146,205,130,148,196,127,144,194,123,141,195,119,137,187,113,129,172,110,122,150,96,106,123,75,83,103,66,69,95,71,70,104,93,88,122,118,113,129,132,126,132,141,135,152,162,158,171,182,176,185,197,194,69,77,64,26,29,21,1,1,1,1,1,2,4,1,0,12,2,5,18,3,9,12,2,5,4,1,2,2,0,0,2,0,0,4,0,1,1,1,1,32,12,11,153,45,59,203,47,68,195,46,67,191,48,69,179,50,67,155,49,59,119,42,49,91,38,42,81,48,46,94,77,71,117,110,102,125,126,116,125,128,120,129,135,128,144,153,147,162,176,171,173,187,183,184,198,196,83,94,82,47,52,43,1,1,1,2,1,2,2,0,0,5,1,2,7,1,5,4,0,2,1,0,0,1,0,0,1,0,0,3,0,0,1,2,0,27,3,2,142,25,38,205,32,54,198,25,46,169,25,43,121,25,36,85,29,34,74,41,39,85,66,56,102,92,82,121,113,105,128,124,115,122,126,115,121,127,118,132,139,131,147,157,150,165,179,174,176,191,187,186,201,199,92,102,93,54,60,50,6,7,3,3,2,1,2,2,0,1,3,1,1,3,3,1,2,2,1,1,1,1,0,0,1,0,0,1,1,1,0,3,2,15,1,0,102,19,28,157,31,47,117,17,23,74,13,12,56,27,22,74,58,55,99,90,81,115,115,99,122,126,111,124,124,112,123,123,113,125,130,119,128,135,126,136,145,137,148,159,151,162,176,171,177,192,188,188,202,201,87,99,89,43,51,37,19,23,11,11,12,4,8,10,2,5,11,4,2,10,4,2,7,2,3,4,1,3,4,1,3,4,1,2,3,2,0,6,6,4,5,2,42,13,13,71,21,24,53,27,25,57,50,41,80,77,62,113,98,82,132,113,101,134,126,113,123,126,112,116,125,111,120,128,115,131,138,126,139,148,137,143,154,145,156,168,161,169,184,179,182,197,193,188,202,201,82,96,82,46,57,36,36,44,22,31,35,17,27,30,15,22,28,15,17,26,13,16,23,12,18,21,12,19,21,13,20,22,14,19,23,15,19,27,20,23,31,21,37,40,27,64,55,45,87,70,67,104,88,81,116,102,85,128,112,88,139,121,105,131,122,110,117,122,107,115,127,112,123,133,119,131,139,127,139,149,138,148,160,151,159,172,164,174,189,183,185,200,196,187,202,200,85,101,83,62,75,48,58,67,38,55,61,37,51,56,35,47,53,33,46,53,34,48,55,38,49,55,40,51,56,41,53,58,44,55,62,46,59,67,45,68,71,48,81,84,59,104,96,74,116,103,83,127,109,92,133,116,97,127,121,97,127,127,107,118,124,106,114,125,108,122,131,117,129,136,123,136,145,133,141,152,141,149,162,153,158,171,163,168,183,178,180,195,191,186,200,199}
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h
new file mode 100644
index 0000000..423d069
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h
@@ -0,0 +1,43 @@
+#define CONV1_IM_DIM 32
+#define CONV1_IM_CH 3
+#define CONV1_KER_DIM 5
+#define CONV1_PADDING 2
+#define CONV1_STRIDE 1
+#define CONV1_OUT_CH 32
+#define CONV1_OUT_DIM 32
+
+#define POOL1_KER_DIM 3
+#define POOL1_STRIDE 2
+#define POOL1_PADDING 0
+#define POOL1_OUT_DIM 16
+
+#define CONV2_IM_DIM 16
+#define CONV2_IM_CH 32
+#define CONV2_KER_DIM 5
+#define CONV2_PADDING 2
+#define CONV2_STRIDE 1
+#define CONV2_OUT_CH 16
+#define CONV2_OUT_DIM 16
+
+#define POOL2_KER_DIM 3
+#define POOL2_STRIDE 2
+#define POOL2_PADDING 0
+#define POOL2_OUT_DIM 8
+
+#define CONV3_IM_DIM 8
+#define CONV3_IM_CH 16
+#define CONV3_KER_DIM 5
+#define CONV3_PADDING 2
+#define CONV3_STRIDE 1
+#define CONV3_OUT_CH 32
+#define CONV3_OUT_DIM 8
+
+#define POOL3_KER_DIM 3
+#define POOL3_STRIDE 2
+#define POOL3_PADDING 0
+#define POOL3_OUT_DIM 4
+
+#define IP1_DIM 4*4*32
+#define IP1_IM_DIM 4
+#define IP1_IM_CH 32
+#define IP1_OUT 10
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h
new file mode 100644
index 0000000..2c3cedd
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h
@@ -0,0 +1,26 @@
+#define CONV1_WT {-9,-1,2,6,-4,6,4,-11,8,-9,-11,10,-12,5,15,11,-1,-1,33,-25,-18,47,-35,-23,25,-27,-5,0,-4,9,2,-5,0,34,-25,-21,55,-40,-33,34,-32,-16,5,-7,2,-21,16,14,-4,5,3,14,-10,-7,3,-10,-2,-8,5,8,-29,23,12,-25,15,8,-15,4,7,-16,5,8,-13,17,12,2,-4,-1,-1,-10,9,6,-4,21,11,0,12,-10,-9,-4,13,10,12,19,11,27,0,-5,11,-21,-26,-28,-7,3,-15,16,14,26,-22,-25,-8,-29,-24,-23,0,6,-13,13,25,0,-21,-18,-3,-21,-19,-13,11,14,4,13,18,-4,6,16,-1,-10,-14,-7,12,9,5,13,8,-4,9,10,-9,-4,7,-3,7,7,-12,7,3,0,-1,-7,2,-8,-5,9,-3,6,-4,7,-10,-25,7,-7,-7,10,2,14,-4,2,17,-9,5,-3,7,-10,-25,4,-10,-8,0,0,16,-7,11,25,-14,13,4,7,-12,-23,5,-16,-17,8,0,11,2,13,21,-11,9,-3,2,-9,-9,-3,-14,-11,1,-1,6,-6,6,14,-1,16,11,7,3,-14,21,6,-6,17,13,4,1,7,-3,-6,2,2,27,13,-5,18,0,-7,-6,-4,2,-24,-11,0,-18,-8,6,24,8,-14,11,-6,-8,-8,0,12,-22,-2,13,-15,-3,7,29,6,-16,10,-6,-4,-12,-7,11,-26,-14,3,-10,-8,0,16,5,-8,-5,-5,3,-15,-2,23,-17,-5,17,1,1,12,10,3,-5,-7,-18,-7,-3,-4,2,3,6,4,4,2,-7,17,20,12,-23,-27,-15,-3,3,6,5,15,6,-2,2,-5,22,22,11,-26,-30,-19,-6,-5,3,10,12,6,2,1,-3,20,14,4,-15,-26,-18,0,-9,1,14,8,6,1,-7,-9,8,11,6,-10,-13,-11,-4,-4,8,2,5,17,-9,0,11,-9,-11,21,6,13,39,-7,1,30,2,12,36,-11,-1,28,-2,-25,-6,6,-16,-6,-9,-34,-24,3,-17,-15,2,-20,-11,0,-13,-11,25,13,6,0,-15,-20,16,7,-11,7,-3,-10,-5,-2,-6,14,22,12,-16,-5,-12,7,23,7,-10,5,-2,-10,-1,-9,7,21,8,-19,-2,-13,2,21,3,-15,9,-2,-4,-2,-2,-12,2,13,-19,1,6,0,16,-1,5,8,-28,11,-2,-4,-10,-1,21,-30,-4,22,-8,14,9,11,14,-21,20,-9,-23,0,-4,19,-28,-9,31,-30,-1,12,3,14,-11,30,3,-24,3,-8,6,-22,-9,31,-29,2,26,-5,11,8,24,2,-36,24,3,-9,-6,-17,4,-8,-8,12,1,-1,5,3,-12,15,-6,-2,-1,0,15,-11,-18,6,-18,-10,6,3,6,-3,3,-12,13,-14,-1,43,-23,-3,52,-16,-11,28,-8,4,-6,5,-11,16,-6,-20,32,-28,-24,38,-31,-22,20,-16,5,-13,7,-2,5,3,-6,17,-10,-8,22,-13,-5,13,0,11,-16,14,-3,-14,6,3,-4,4,4,-2,2,-3,-9,5,2,1,-2,-10,-6,-3,-17,-2,1,-19,2,1,-14,8,11,14,3,7,1,-13,-13,2,-1,-3,-9,0,-5,-18,4,0,18,3,9,15,-10,-8,10,-12,-18,5,-3,-16,-10,0,-14,5,4,14,14,-1,10,16,-6,-2,14,-1,-12,8,2,-18,-13,-1,17,-2,2,24,-4,-3,17,8,-1,12,9,-6,-3,-2,-9,3,-2,-13,-1,-5,-17,-5,-7,-16,-7,-8,-14,-9,3,-9,-1,0,-13,-7,4,-9,-7,3,-6,-8,-2,-4,-7,5,-7,-4,1,-8,-11,10,6,-3,14,12,-1,6,10,-2,0,-12,-16,-3,-9,-19,0,1,-12,9,12,-2,1,10,-1,10,4,-8,6,3,-11,11,14,1,12,19,8,3,16,9,-7,-1,4,-11,-1,3,1,12,8,7,15,13,-5,-2,4,-7,-5,1,-8,-3,2,1,10,9,-1,8,9,-11,-9,-2,0,-1,6,-14,-13,-6,1,3,10,3,4,11,-1,-5,5,7,4,10,-14,-17,-10,-12,-13,-6,-11,-14,-6,1,-6,1,2,-1,1,-5,-7,-3,-2,-4,1,-11,-13,-9,-12,-16,-12,-2,-1,-2,-9,-5,-4,-7,-3,3,-1,-3,8,9,-2,1,8,11,13,5,14,17,1,10,17,-1,3,18,0,-6,0,-1,0,3,4,13,16,-1,8,14,-4,2,14,-16,-20,-14,-3,-3,0,13,21,25,5,11,14,-5,-2,9,1,-5,2,-6,-9,-14,-7,-4,-8,-10,-9,-13,-10,-12,-12,7,-1,-2,-5,2,-14,-5,3,-6,1,9,3,-8,3,-1,-9,2,0,-12,-4,-21,6,17,8,17,28,22,-5,6,2,-15,-8,-7,8,21,-3,2,20,-5,-1,16,-8,7,17,3,0,6,1,11,26,0,-22,-4,-33,-36,-16,-40,-2,14,1,2,10,5,1,17,-10,-16,3,-22,-22,-1,-14,-9,10,6,-7,7,7,10,-8,5,-3,-4,-1,-7,-7,-7,1,0,-2,-7,11,9,5,-2,2,12,14,16,12,7,2,0,-9,-23,-14,-8,-23,-1,-11,-14,-7,-9,-7,14,11,7,44,35,19,34,38,12,1,3,9,-6,-4,8,-32,-28,-19,-41,-45,-37,-14,-17,-17,-7,4,-3,-5,8,8,3,16,21,8,14,24,-3,-5,6,-11,-15,-18,-8,-12,-12,-6,-14,-8,9,-6,1,16,3,11,3,3,-8,-5,0,-6,-13,-13,-13,-6,-15,-15,6,-5,-4,9,16,5,1,14,5,-4,7,-1,-12,-11,-18,0,-6,-12,5,14,0,-1,13,2,2,18,6,-9,-4,-16,0,-3,-17,4,12,0,-1,13,2,0,16,6,-6,1,-9,-5,-8,-19,18,-1,-4,16,-2,-6,18,-1,-4,9,-4,1,-12,-13,-4,9,-3,-9,6,-4,-14,15,5,-2,-5,-5,-1,-20,-9,-3,16,2,-5,12,3,-7,15,7,1,-12,-7,-2,-15,-2,2,18,7,-1,10,2,-5,-1,-8,-8,-18,-15,-7,-2,7,9,-15,-15,-17,-7,-6,-7,-12,-12,-6,-17,-12,-6,9,14,12,13,7,6,3,-3,2,-6,-7,1,-7,-4,3,-11,-12,-6,12,11,6,-4,-3,-2,-15,-12,-4,-7,-4,3,-9,-9,-4,15,17,12,-3,1,2,-18,-13,-6,4,5,10,6,1,5,9,14,8,-6,1,3,-21,-15,-7,-2,-1,5,4,-1,2,4,17,14,-4,4,9,-24,-20,-11,-7,-7,3,-2,-6,1,5,9,-10,6,9,-12,12,11,-7,4,1,-15,11,9,-6,25,15,5,21,13,5,23,14,7,13,2,-3,17,10,6,-1,-10,-2,-20,-21,-14,-11,-11,-2,-11,-12,-3,-16,-15,-3,-4,-14,6,-16,-19,-1,-3,-2,13,-1,-3,12,-6,-10,8,0,-5,10,-11,-10,4,-4,-1,8,-11,-5,3,-6,-1,8,-8,-15,0,-3,0,9,4,11,14,-3,3,4,-15,-9,-6,-12,-14,-1,-18,-8,-1,-26,-12,-8,-28,-12,-9,-30,-13,-8,10,-1,-6,15,17,5,11,22,8,15,24,8,17,25,12,10,-5,-9,4,4,-5,1,10,1,2,4,-8,6,7,-7,5,-10,-6,-1,-5,-3,3,8,10,1,4,-2,-1,0,-8,2,-8,3,0,-6,9,1,-2,-8,6,1,-3,1,-10,6,5,-6,7,-8,-12,0,11,17,-4,-7,-1,-12,1,-2,9,11,2,17,-35,-32,-21,38,52,20,-27,-17,-30,4,2,17,18,10,19,-44,-34,-34,43,59,28,-25,-17,-31,6,0,16,10,4,18,-31,-27,-22,27,31,16,-10,-9,-16,3,-6,6,-2,-11,15,10,0,14,-2,-8,-8,0,-7,-7,13,0,11,2,-7,3,10,4,3,0,-2,-14,-1,-1,-16,-1,3,-6,8,-4,3,12,4,2,4,1,-17,7,10,-8,0,10,-2,-3,-15,0,10,4,8,-10,-13,-24,-7,-2,-16,0,8,-3,-6,-6,7,7,11,13,2,9,-6,-4,11,-15,2,22,0,2,-4,-2,-10,-12,-5,24,15,25,-1,-4,-2,-11,-1,-3,7,11,5,-16,-17,-23,-29,-35,-30,53,45,54,-11,-9,-12,-3,5,4,44,39,36,-45,-51,-51,-19,-28,-16,25,24,28,-15,0,-12,7,1,2,44,42,40,-36,-41,-41,5,0,3,-1,18,5,-17,-15,-15,7,8,14,11,3,4,1,-11,-8,10,-1,-2,-5,-10,-3,6,6,10,5,9,9,-6,3,0,-14,-21,-16,-40,-39,-26,0,4,16,15,20,24,-14,-7,-5,3,-5,1,-13,-12,0,-16,-11,6,4,7,20,-11,-9,-1,11,-4,7,14,7,22,-14,-14,5,-7,-6,12,-4,-9,4,18,-6,5,14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+
+#define CONV1_BIAS {-49,-18,-7,-20,-12,-15,7,2,-10,-84,-72,-65,-53,-6,-87,-63,-64,-28,-28,-4,-3,-10,-52,-15,-5,-7,-31,-44,-102,-19,-5,-65}
+
+#define CONV2_WT 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+
+#define CONV2_BIAS {55,50,34,43,-37,35,-21,10,35,-53,-76,7,14,-1,92,20}
+
+#define CONV3_WT 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+
+#define CONV3_BIAS {18,36,-46,-45,64,8,13,-19,28,1,14,-57,23,20,-2,32,48,-11,85,73,-7,52,125,33,125,13,92,-72,89,-1,11,70}
+
+#define IP1_WT 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34,-1,-20}
+
+#define IP1_BIAS {30,-121,-51,77,40,20,46,-35,28,-33}
+
+#define CONV1_BIAS_LSHIFT 6
+#define CONV1_OUT_RSHIFT 9
+#define CONV2_BIAS_LSHIFT 4
+#define CONV2_OUT_RSHIFT 9
+#define CONV3_BIAS_LSHIFT 1
+#define CONV3_OUT_RSHIFT 7
+#define IP1_BIAS_LSHIFT 1
+#define IP1_OUT_RSHIFT 8
+#define INPUT_MEAN_SHIFT {125,123,114}
+#define INPUT_RIGHT_SHIFT {8,8,8}
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt
new file mode 100644
index 0000000..75b6e01
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt
@@ -0,0 +1,4 @@
+CMSIS NN Lib example arm_nnexample_cifar10 for
+  Cortex-M4 and Cortex-M7.
+
+The example is configured for uVision Simulator.
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h
new file mode 100644
index 0000000..5958233
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h
@@ -0,0 +1,44 @@
+/*------------------------------------------------------------------------------
+ * MDK - Component ::Event Recorder
+ * Copyright (c) 2016 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    EventRecorderConf.h
+ * Purpose: Event Recorder Configuration
+ * Rev.:    V1.0.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Event Recorder
+
+//   Number of Records
+//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
+//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
+//     <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288
+//     <1048576=>1048576
+//   Configure size of Event Record Buffer (each record is 16 bytes)
+//   Must be 2^n (min=8, max=1048576)
+#define EVENT_RECORD_COUNT      64U
+
+//   Time Stamp Source
+//      <0=> DWT Cycle Counter  <1=> SysTick
+//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)
+//   Selects source for 32-bit time stamp
+#define EVENT_TIMESTAMP_SOURCE  1
+
+//   SysTick Configuration
+//   Configure values when Time Stamp Source is set to SysTick
+
+//     SysTick Input Clock Frequency [Hz] <1-1000000000>
+//     Defines SysTick input clock (typical identical with processor clock)
+#define SYSTICK_CLOCK           100000000U
+
+//     SysTick Interrupt Period [us] <1-1000000000>
+//     Defines time period of the SysTick timer interrupt
+#define SYSTICK_PERIOD_US       1000U
+
+//   
+
+// 
+
+//------------- <<< end of configuration section >>> ---------------------------
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h
new file mode 100644
index 0000000..73f80ad
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h
@@ -0,0 +1,24 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_gru' 
+ * Target:  'ARMCM0' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM0.h"
+
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h
new file mode 100644
index 0000000..1f91822
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h
@@ -0,0 +1,22 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_gru' 
+ * Target:  'ARMCM3' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM3.h"
+
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h
new file mode 100644
index 0000000..3df85a0
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h
@@ -0,0 +1,22 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_gru' 
+ * Target:  'ARMCM4_FP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM4_FP.h"
+
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h
new file mode 100644
index 0000000..04bee02
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h
@@ -0,0 +1,22 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_gru' 
+ * Target:  'ARMCM7_SP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM7_SP.h"
+
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp
new file mode 100644
index 0000000..efb3257
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp
@@ -0,0 +1,221 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2018 Arm Limited. All rights reserved.
+*
+*
+* Project:       CMSIS NN Library
+* Title:         arm_nnexamples_gru.cpp
+*
+* Description:   Gated Recurrent Unit Example
+*
+* Target Processor: Cortex-M4/Cortex-M7
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of Arm LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup GRUExample Gated Recurrent Unit Example
+ *
+ * \par Description:
+ * \par
+ * Demonstrates a gated recurrent unit (GRU) example with the use of fully-connected,
+ * Tanh/Sigmoid activation functions.
+ *
+ * \par Model definition:
+ * \par
+ * GRU is a type of recurrent neural network (RNN). It contains two sigmoid gates and one hidden
+ * state. 
+ * \par
+ * The computation can be summarized as:
+ * 
z[t] = sigmoid( W_z ⋅ {h[t-1],x[t]} )
+ * r[t] = sigmoid( W_r ⋅ {h[t-1],x[t]} ) 
+ * n[t] = tanh( W_n ⋅ [r[t] × {h[t-1], x[t]} ) 
+ * h[t] = (1 - z[t]) × h[t-1] + z[t] × n[t] 

+ * \image html GRU.gif "Gate Recurrent Unit Diagram"
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c update_gate_weights, \c reset_gate_weights, \c hidden_state_weights are weights corresponding to update gate (W_z), reset gate (W_r), and hidden state (W_n).
+ * \li \c update_gate_bias, \c reset_gate_bias, \c hidden_state_bias are layer bias arrays
+ * \li \c test_input1, \c test_input2, \c test_history are the inputs and initial history
+ *
+ * \par
+ * The buffer is allocated as:
+ * \par
+ * | reset | input | history | update | hidden_state |
+ * \par
+ * In this way, the concatination is automatically done since (reset, input) and (input, history)
+ * are physically concatinated in memory.
+ * \par
+ *  The ordering of the weight matrix should be adjusted accordingly.
+ *
+  *
+ * 
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_fully_connected_mat_q7_vec_q15_opt()
+ * - arm_nn_activations_direct_q15()
+ * - arm_mult_q15()
+ * - arm_offset_q15()
+ * - arm_sub_q15()
+ * - arm_copy_q15()
+ *
+ *  Refer  
+ * \link arm_nnexamples_gru.cpp \endlink
+ *
+ */
+
+#include 
+#include 
+#include 
+#include "arm_nnexamples_gru_test_data.h"
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+#ifdef _RTE_
+#include "RTE_Components.h"
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+#endif
+
+#define DIM_HISTORY 32
+#define DIM_INPUT 32
+#define DIM_VEC 64
+
+#define USE_X4
+
+#ifndef USE_X4
+static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X2;
+static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X2;
+static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X2;
+#else
+static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X4;
+static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X4;
+static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X4;
+#endif
+
+static q7_t update_gate_bias[DIM_HISTORY] = UPDATE_GATE_BIAS;
+static q7_t reset_gate_bias[DIM_HISTORY] = RESET_GATE_BIAS;
+static q7_t hidden_state_bias[DIM_HISTORY] = HIDDEN_STATE_BIAS;
+
+static q15_t test_input1[DIM_INPUT] = INPUT_DATA1;
+static q15_t test_input2[DIM_INPUT] = INPUT_DATA2;
+static q15_t test_history[DIM_HISTORY] = HISTORY_DATA;
+
+q15_t     scratch_buffer[DIM_HISTORY * 4 + DIM_INPUT];
+
+void gru_example(q15_t * scratch_input, uint16_t input_size, uint16_t history_size,
+                 q7_t * weights_update, q7_t * weights_reset, q7_t * weights_hidden_state,
+                 q7_t * bias_update, q7_t * bias_reset, q7_t * bias_hidden_state)
+{
+  q15_t    *reset = scratch_input;
+  q15_t    *input = scratch_input + history_size;
+  q15_t    *history = scratch_input + history_size + input_size;
+  q15_t    *update = scratch_input + 2 * history_size + input_size;
+  q15_t    *hidden_state = scratch_input + 3 * history_size + input_size;
+
+  // reset gate calculation
+  // the range of the output can be adjusted with bias_shift and output_shift
+#ifndef USE_X4
+  arm_fully_connected_mat_q7_vec_q15(input, weights_reset, input_size + history_size, history_size, 0, 15, bias_reset,
+                                     reset, NULL);
+#else
+  arm_fully_connected_mat_q7_vec_q15_opt(input, weights_reset, input_size + history_size, history_size, 0, 15,
+                                         bias_reset, reset, NULL);
+#endif
+  // sigmoid function, the size of the integer bit-width should be consistent with out_shift
+  arm_nn_activations_direct_q15(reset, history_size, 0, ARM_SIGMOID);
+  arm_mult_q15(history, reset, reset, history_size);
+
+  // update gate calculation
+  // the range of the output can be adjusted with bias_shift and output_shift
+#ifndef USE_X4
+  arm_fully_connected_mat_q7_vec_q15(input, weights_update, input_size + history_size, history_size, 0, 15,
+                                     bias_update, update, NULL);
+#else
+  arm_fully_connected_mat_q7_vec_q15_opt(input, weights_update, input_size + history_size, history_size, 0, 15,
+                                         bias_update, update, NULL);
+#endif
+
+  // sigmoid function, the size of the integer bit-width should be consistent with out_shift
+  arm_nn_activations_direct_q15(update, history_size, 0, ARM_SIGMOID);
+
+  // hidden state calculation
+#ifndef USE_X4
+  arm_fully_connected_mat_q7_vec_q15(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15,
+                                     bias_hidden_state, hidden_state, NULL);
+#else
+  arm_fully_connected_mat_q7_vec_q15_opt(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15,
+                                         bias_hidden_state, hidden_state, NULL);
+#endif
+
+  // tanh function, the size of the integer bit-width should be consistent with out_shift
+  arm_nn_activations_direct_q15(hidden_state, history_size, 0, ARM_TANH);
+  arm_mult_q15(update, hidden_state, hidden_state, history_size);
+
+  // we calculate z - 1 here
+  // so final addition becomes substraction
+  arm_offset_q15(update, 0x8000, update, history_size);
+  // multiply history
+  arm_mult_q15(history, update, update, history_size);
+  // calculate history_out
+  arm_sub_q15(hidden_state, update, history, history_size);
+
+  return;
+}
+
+int main()
+{
+  #ifdef RTE_Compiler_EventRecorder
+  EventRecorderInitialize (EventRecordAll, 1);  // initialize and start Event Recorder
+  #endif
+
+  printf("Start GRU execution\n");
+  int       input_size = DIM_INPUT;
+  int       history_size = DIM_HISTORY;
+
+  // copy over the input data 
+  arm_copy_q15(test_input1, scratch_buffer + history_size, input_size);
+  arm_copy_q15(test_history, scratch_buffer + history_size + input_size, history_size);
+
+  gru_example(scratch_buffer, input_size, history_size,
+              update_gate_weights, reset_gate_weights, hidden_state_weights,
+              update_gate_bias, reset_gate_bias, hidden_state_bias);
+  printf("Complete first iteration on GRU\n");
+
+  arm_copy_q15(test_input2, scratch_buffer + history_size, input_size);
+  gru_example(scratch_buffer, input_size, history_size,
+              update_gate_weights, reset_gate_weights, hidden_state_weights,
+              update_gate_bias, reset_gate_bias, hidden_state_bias);
+  printf("Complete second iteration on GRU\n");
+
+  return 0;
+}
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h
new file mode 100644
index 0000000..e0ccbe1
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h
@@ -0,0 +1,23 @@
+#define UPDATE_GATE_WEIGHT_X2 {-62,83,-58,-89,-80,1,-93,31,101,95,121,-83,71,18,-98,-5,44,-100,-16,-73,25,62,34,-22,-16,42,9,-125,60,-78,15,-76,-76,-63,71,-25,78,-66,38,-118,-71,-120,-80,28,33,51,82,-105,26,-47,38,86,-114,44,90,-98,105,-123,24,95,-12,11,49,-35,78,104,104,17,-116,-40,-83,4,88,-110,-111,-98,18,-89,120,-84,66,-69,-8,-22,-91,-29,-41,110,55,-124,-67,103,-40,-100,1,-25,-68,-62,-89,-75,-20,-78,101,-92,-51,-97,-54,59,-78,41,34,-102,-9,-53,56,103,-55,13,81,-75,-20,-37,29,36,110,84,-80,-127,-68,-33,-70,-16,-42,-9,-104,107,-81,-16,42,-74,-63,-4,-128,-109,-105,55,-51,-68,-88,19,-39,116,-7,66,52,-29,63,-94,71,-2,-127,31,-103,120,124,41,-13,-23,127,59,-22,54,-2,32,-87,-109,85,-31,-5,-59,-122,-97,-14,-88,-19,43,-30,115,42,14,10,121,28,-63,83,-85,101,40,23,-39,74,-99,73,50,-20,123,-88,-13,-126,-25,70,-11,16,-28,121,-29,20,-69,104,117,-40,-1,-97,-12,31,32,15,-32,77,31,16,40,107,-52,-52,-89,-17,124,-95,54,48,-40,37,24,-46,42,119,5,-118,-45,-10,106,83,57,-74,-10,-56,85,37,-25,83,-31,-54,111,-78,-96,-114,-65,-100,28,-31,-111,33,66,74,-43,112,119,-80,-26,74,-81,-123,55,-126,32,-66,110,-86,-118,-21,15,16,26,13,-109,41,-16,88,81,-82,-55,-89,109,-52,118,-39,57,-16,86,-68,-10,-19,110,-50,-17,-84,103,-3,94,-8,50,15,-44,-87,6,18,8,61,66,-108,-67,-6,107,-68,25,25,25,-82,71,62,121,-31,-4,17,-6,-60,-17,116,-67,45,117,-90,12,-68,20,121,-65,-43,74,-104,-42,-69,35,4,-17,5,95,-82,18,65,43,-57,89,1,-8,37,-51,10,67,4,-50,-18,81,-120,44,98,16,-98,25,127,88,-111,-49,114,111,-17,-74,40,-18,35,19,31,48,-23,53,102,41,89,-27,87,-54,-121,-113,97,125,125,-108,58,-17,8,70,-67,-55,59,42,-85,78,27,16,66,67,54,-74,33,-19,72,77,126,-122,-7,-109,58,78,-88,15,2,16,37,-34,-114,-88,-53,88,115,19,7,-67,93,80,-48,-11,-61,31,38,29,-59,-70,0,25,106,-7,-44,53,62,19,-64,109,70,-103,-114,97,57,112,24,-66,-127,29,29,-31,-87,-125,54,-98,101,-39,56,-88,-63,-113,-73,-91,80,112,-27,-75,-42,-5,79,60,-55,23,-61,66,51,39,-91,96,-60,-64,-1,75,55,-108,73,38,75,-113,-9,-92,-92,-3,-30,93,-27,-100,-55,125,52,72,110,12,84,-83,65,-79,92,11,87,-106,35,-38,-24,-79,15,-11,-109,-22,95,82,-1,-2,-113,116,-64,93,-62,-11,101,35,-91,51,-6,21,29,25,-16,68,-103,-111,-23,-123,-80,24,-17,-7,53,23,114,-13,-105,-88,120,13,-25,-40,29,-38,-43,3,2,-121,-110,54,-43,30,66,28,60,-81,-6,-8,126,-80,64,-42,126,75,-69,-116,-41,81,94,31,-116,5,-46,5,-21,-105,78,-20,-34,54,46,-124,120,-83,44,-17,-52,-23,-110,34,-35,31,61,88,-108,-38,31,117,-26,38,-57,65,9,0,59,124,14,-39,-95,-91,107,-34,85,-83,-31,-68,-78,-86,21,-118,56,60,-3,-116,33,53,-94,85,77,91,-94,100,-89,97,88,111,36,74,-110,7,-74,91,-112,21,32,-59,98,36,10,-41,44,-114,-88,92,111,72,43,58,42,-125,-11,96,126,25,96,-105,-128,-70,85,-82,-17,103,23,-37,76,58,108,16,-116,-44,22,89,0,6,-108,27,-34,88,-125,22,-45,-116,28,-29,-70,-3,-81,-80,42,119,105,-40,-109,105,64,5,72,-32,-95,90,60,6,-29,40,-19,57,89,-50,34,-123,-32,-18,20,9,-19,-81,-45,-120,-120,20,2,18,70,75,100,64,126,-9,63,-82,114,-62,106,-11,104,-9,-13,88,-40,101,73,108,52,33,116,-54,-114,-47,85,2,-117,-80,100,-20,98,-75,-83,-24,-125,-91,-97,95,-46,15,-94,-21,53,-27,-18,65,87,112,38,-115,-27,37,-84,1,103,85,-50,36,-49,-119,68,20,119,-113,43,-67,105,44,4,-48,16,-42,83,-39,106,31,-34,-76,-51,68,82,-111,-116,-104,-118,109,-29,-6,-91,81,-102,-76,-82,64,121,27,-98,-24,-88,36,115,59,-84,-121,4,29,45,73,110,-56,-12,109,-88,85,-30,87,18,118,23,21,106,40,115,78,-72,-103,11,83,44,117,-63,98,30,115,123,-39,25,15,84,52,46,77,64,-104,125,-13,34,125,65,6,57,-128,-2,115,7,-65,-73,82,72,-109,99,43,-94,-106,-39,-4,-127,58,123,-128,29,-80,4,51,109,-50,-38,25,-13,-52,-106,87,76,44,78,101,16,-102,-20,104,23,107,-88,18,-85,119,-21,-53,-84,-7,-8,-114,23,-54,74,80,77,-40,19,-75,-41,60,77,82,-96,-121,-43,114,-124,-1,-75,32,34,-117,21,64,-87,-100,-29,-36,-45,-46,-111,4,-44,-94,-117,100,-25,-27,105,95,15,88,25,-38,-88,122,62,-62,-28,95,-86,125,-83,-9,-100,101,-124,22,21,-91,50,-100,-27,-92,115,86,85,33,-112,-43,61,114,62,-31,-84,-7,5,-26,-10,-21,-89,60,-96,48,-34,88,-80,-91,92,12,118,-2,-38,83,-50,-109,-111,-26,-109,-78,-7,84,60,-95,15,-71,112,126,71,36,39,-42,-85,-126,-68,105,-18,-127,48,-41,57,-93,13,-25,-71,66,-43,-23,122,4,-70,123,115,124,-61,-32,18,-18,49,123,-101,37,-50,-111,-73,124,-18,54,-64,93,-69,16,112,21,-56,56,127,113,-48,-57,-4,85,-84,53,44,28,-126,-59,-11,94,58,-64,112,82,127,58,50,5,-6,-102,90,-18,-86,104,17,108,-64,-22,73,-102,-17,-31,-11,-105,-40,-49,84,-82,104,57,30,112,-119,-92,78,-92,35,90,-45,-13,-75,-125,-19,-83,-75,29,15,-33,127,-14,29,-80,61,41,67,-14,-18,101,101,108,-24,-61,-90,-59,-48,-114,1,-14,106,52,109,-45,-100,74,-33,-68,-94,-68,-22,-99,31,-86,85,-27,-70,69,127,92,125,-95,117,-87,-8,-71,18,94,-90,103,-31,-1,-50,-60,-2,96,31,-1,-98,75,104,-6,-38,-24,127,94,-48,97,-96,4,-108,106,76,-31,-7,-41,58,-13,-72,-81,-116,-24,-45,46,-20,114,97,-14,125,11,22,26,27,-2,-88,-28,-76,119,50,52,66,65,120,-42,-43,-59,-56,-28,-42,-87,-18,-47,-85,74,119,97,-6,-127,-86,30,18,-43,48,-73,22,-5,34,122,9,115,-32,-63,-13,61,119,18,-113,-12,80,26,-39,-76,-101,-104,-6,48,38,-82,-52,-91,-38,112,110,115,76,69,100,-116,109,3,-35,16,94,24,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+
+#define UPDATE_GATE_WEIGHT_X4 {-62,78,83,104,-68,28,-33,-63,-58,104,-89,17,-70,83,-16,-85,-80,-116,1,-40,-42,101,-9,40,-93,-83,31,4,-104,23,107,-39,101,88,95,-110,-81,74,-16,-99,121,-111,-83,-98,42,73,-74,50,71,18,18,-89,-63,-20,-4,123,-98,120,-5,-84,-128,-88,-109,-13,44,66,-100,-69,-105,-126,55,-25,-16,-8,-73,-22,-51,70,-68,-11,25,-91,62,-29,-88,16,19,-28,34,-41,-22,110,-39,121,116,-29,-16,55,42,-124,-7,20,66,-69,9,-67,-125,103,52,104,-29,117,60,-40,-78,-100,63,-40,-94,-1,15,1,-76,-25,71,-97,-2,-12,-76,-68,-63,-62,-127,31,31,32,71,-89,-25,-75,-103,15,120,-32,78,-20,-66,-78,124,77,41,31,38,101,-118,-92,-13,16,-23,40,-71,-51,-120,-97,127,107,59,-52,-80,-54,28,59,-22,-52,54,-89,33,-78,51,41,-2,-17,32,124,82,34,-105,-102,-87,-95,-109,54,26,-9,-47,-53,85,48,-31,-40,38,56,86,103,-5,37,-59,24,-114,-55,44,13,-122,-46,-97,42,90,81,-98,-75,-14,119,-88,5,105,-20,-123,-37,-19,-118,43,-45,24,29,95,36,-30,-10,115,106,-12,110,11,84,42,83,14,57,49,-80,-35,-127,10,-74,121,-10,-56,-8,85,50,-120,37,44,-34,37,15,-25,-44,98,-114,16,-88,83,-87,-31,6,-98,-53,25,88,-54,18,111,8,127,115,88,19,-78,61,-96,66,-111,7,-49,-67,-114,-108,-65,-67,114,93,111,80,-100,-6,28,107,-17,-48,-74,-11,-31,-68,-111,25,40,-61,-18,31,33,25,66,25,35,38,19,29,74,-82,-43,71,31,-59,48,-70,112,62,119,121,-23,0,53,25,-80,-31,-26,-4,102,106,41,-7,74,17,-81,-6,89,-44,-27,53,-123,-60,55,-17,87,62,-54,19,-126,116,32,-67,-121,-64,-113,109,-66,45,110,117,97,70,125,-103,-86,-90,-118,12,125,-114,-108,97,-21,-68,15,20,58,57,-17,112,16,121,26,-65,8,24,70,-66,13,-43,-109,74,-67,-127,-55,29,41,-104,-16,-42,59,29,42,-31,88,-69,81,35,-85,-87,78,-125,-82,4,-55,-17,27,54,16,-98,-89,5,109,95,66,101,67,-39,-52,-82,118,18,54,56,-74,-88,-39,65,57,43,33,-63,-19,-113,-16,-57,86,89,72,-73,77,-91,-68,1,-10,-8,126,80,-122,112,-19,37,110,-51,-7,-27,-109,-75,-50,10,-17,67,58,-42,78,-5,-84,4,103,-50,-88,79,15,60,-3,-18,94,81,2,-55,16,23,-61,-16,66,68,-52,44,-23,-114,51,-103,39,-111,-110,-88,34,92,-91,-23,96,-123,-35,111,31,72,-60,-80,-64,24,61,43,88,58,-1,-17,75,-7,-108,42,-38,-125,55,53,-108,23,31,-11,117,96,73,114,38,-13,-26,126,38,25,75,-105,-113,-88,-57,96,65,-105,-9,120,-92,13,9,-128,0,-70,-92,-25,-3,-40,59,85,124,-82,-30,29,93,-38,14,-17,-39,103,-27,-43,-100,3,-95,23,-91,-37,-55,2,125,-121,107,76,-34,58,52,-110,72,54,85,108,-83,16,110,-43,12,30,-31,-116,-68,-44,84,66,-83,28,-78,22,-86,89,65,60,-79,-81,21,0,-118,6,92,-6,11,-8,56,-108,60,27,87,126,-106,-80,-3,-34,-116,88,35,64,-38,-42,33,-125,53,22,-24,126,-79,75,-94,-45,85,-116,15,-69,-11,-116,77,28,91,-29,-109,-41,-22,81,-94,-70,100,-3,95,94,82,31,-89,-81,97,-80,-1,-116,-2,5,88,42,111,119,-113,-46,116,5,36,105,74,-40,-64,-21,93,-105,-110,-109,7,105,-62,78,-11,-20,-74,64,91,5,101,-34,35,54,-112,72,21,-32,-91,46,51,-124,32,-95,-59,90,-6,120,21,-83,98,60,36,6,29,44,25,-17,10,-29,-41,40,-19,-18,57,65,110,4,-56,51,89,87,-50,112,-12,109,109,-50,34,38,-123,-115,-88,-38,85,25,-32,-27,-18,37,-30,-13,87,-52,20,-84,9,1,18,-106,118,87,-19,103,-81,85,23,76,21,44,-45,-50,-120,36,106,78,40,101,-120,-49,20,-119,115,16,78,-102,2,68,18,20,-72,-20,-103,104,70,119,75,-113,11,23,83,107,100,43,64,-67,44,-88,117,18,126,105,-9,44,-63,-85,98,119,63,4,-82,-48,30,-21,115,-53,114,16,-62,-42,123,-84,-39,-7,106,83,-11,-39,25,-8,15,-114,104,106,-9,31,84,23,52,-54,-13,-34,88,-76,46,74,77,80,-40,-51,101,68,64,77,-104,-40,73,82,108,-111,125,19,-13,-75,52,-116,33,-104,34,-41,125,60,116,-118,-54,109,65,77,6,82,-114,-29,-47,-6,57,-96,-128,-121,85,-91,2,81,-2,-43,115,114,-117,-102,-80,-76,7,-124,-65,-1,100,-82,-20,64,-73,-75,82,32,98,121,-75,27,72,34,-109,-117,-83,-98,-24,-24,99,21,43,64,-125,-88,-91,36,-94,-87,-106,-100,-97,115,95,59,-39,-29,-4,-36,-46,-84,15,-121,-127,-45,58,-46,-94,4,-21,29,123,-111,-128,4,53,45,-27,73,29,-44,-80,-94,-117,-109,100,-78,-84,-18,53,101,-25,-7,-27,84,44,101,28,108,105,60,95,-95,-126,-24,-59,-61,15,15,88,-71,-11,-90,94,-59,25,112,-38,126,58,-48,-64,-114,-88,71,122,36,112,1,82,-14,62,39,-62,-42,127,106,58,52,-28,-85,95,-126,50,109,5,-45,-86,-68,125,105,-6,-100,-102,74,-83,-18,-9,-127,90,-33,-18,-68,-100,48,101,-41,-86,-94,104,-68,-124,57,22,-93,17,-22,108,-99,21,13,-91,-25,-64,31,-22,-86,50,-71,-100,66,73,85,-102,-27,-27,-43,-92,-23,-17,-70,-31,69,115,122,86,4,-11,127,-105,92,85,-70,33,123,-40,125,-49,-95,-112,115,-43,124,84,117,-82,-87,61,-61,114,-32,104,-8,57,-71,62,18,-31,-18,30,18,112,94,-84,49,-7,123,-119,-90,-92,103,5,-101,-26,37,78,-31,-92,-1,-10,-50,-21,-111,35,-50,90,-60,-89,-73,60,124,-45,-2,-13,96,-96,-18,48,54,-75,31,-125,-1,-34,-64,88,93,-19,-98,-83,75,-80,-69,-91,16,-75,104,29,-6,92,112,12,21,15,-38,-33,-24,118,-56,-2,56,127,127,-14,94,-38,127,83,113,29,-48,-80,97,-50,-48,-109,-57,61,-96,41,4,-111,-4,-26,85,67,-108,-14,106,76,-113,-31,-12,-2,-30,-29,-76,-7,80,-41,26,63,94,-5,116,58,-39,-13,-76,95,44,-79,-109,-72,-101,-81,-104,26,-122,-42,38,-116,-6,-24,48,-91,112,-109,-103,-45,38,46,-82,-19,99,107,-119,-20,-52,114,-91,-102,49,62,35,97,-38,-14,112,111,107,-35,108,125,110,11,115,80,47,36,54,22,76,26,69,55,11,-65,-50,27,100,-2,-116,26,-73,76,37,-88,109,-2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+
+#define RESET_GATE_WEIGHT_X2 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+
+#define RESET_GATE_WEIGHT_X4 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+
+#define HIDDEN_STATE_WEIGHT_X2 {-3,-33,59,21,117,70,0,44,108,108,-47,-80,-118,34,88,-91,-123,-108,8,51,26,82,-80,107,-100,-69,97,-90,17,19,63,111,-40,-125,110,24,58,-69,26,-31,-65,-37,-47,-41,-109,106,-100,108,-99,108,116,104,86,-50,-45,10,-53,112,34,96,-10,-39,-32,-25,69,102,-2,-4,-25,121,-1,-28,-48,-100,0,-128,60,-73,42,-32,118,-88,-113,-112,-113,70,-98,118,95,77,-52,123,-99,72,26,-102,-32,120,113,22,6,-68,84,-33,103,66,111,60,-76,33,10,25,-43,93,41,-79,110,13,67,107,-113,90,58,64,-125,79,-85,-18,76,80,-59,11,-18,-74,15,-102,99,-19,117,99,65,-50,-108,-121,-9,-104,33,94,-95,110,-48,-97,76,36,1,-58,86,-115,45,-88,38,51,123,-23,-20,-43,-37,15,91,-85,-88,6,-96,58,78,13,23,1,-43,62,-70,-108,44,30,74,90,79,-80,-20,71,-21,0,60,19,-59,-52,44,-14,77,92,-69,121,-123,-27,119,-84,79,87,24,85,118,1,-51,-96,60,102,-6,15,96,120,-109,6,35,11,-119,-109,-18,16,-112,91,-126,71,-29,121,-21,-120,37,57,-117,-39,93,56,-73,-104,77,-107,-52,111,-61,-4,44,-119,67,72,-66,36,-127,-113,-124,123,21,98,84,86,76,23,78,7,-127,-4,1,-46,-107,59,-21,53,-65,-99,-15,-98,53,-31,7,64,7,105,51,-75,50,-52,48,101,-126,-120,5,34,3,81,-39,70,41,112,25,30,79,-6,107,-11,-97,92,-84,67,49,107,60,101,-37,27,-91,-61,-96,120,-113,87,-46,68,64,102,-86,-60,13,-71,56,-105,90,-9,-35,27,103,120,39,23,-39,-1,-85,-95,-6,119,-41,-2,-69,102,102,-119,-3,-11,-125,-111,40,-115,-41,-117,-44,-7,83,123,-21,23,99,-107,43,100,-99,-3,89,3,-113,103,47,-94,-69,-38,-28,-37,49,-117,-49,-126,17,-98,37,92,55,-116,-70,-50,77,120,47,124,78,114,67,-48,6,-42,-115,85,116,-114,-46,-50,-13,70,-101,110,-55,20,-51,125,-19,-9,-15,46,30,-27,-123,114,-50,-30,-72,76,-83,71,47,-45,74,102,44,108,-26,108,-113,-43,110,-91,37,-69,76,-33,106,-76,-96,20,-117,63,-33,-5,11,-121,-51,63,-56,59,-16,-33,114,74,124,73,99,-50,51,-71,118,106,30,-92,26,-40,119,-121,2,-45,9,0,-5,-2,-89,88,-11,-85,-60,19,81,-96,75,82,-40,124,89,-36,-117,-100,-2,-34,112,101,39,-101,-106,60,59,-126,-32,96,68,-53,87,20,54,-24,46,-95,65,-112,22,60,122,-22,-106,-124,97,-37,-86,95,-110,-8,44,58,-12,-120,-45,-86,-32,-86,-94,-14,15,29,-8,-114,71,70,-93,-69,100,-123,-18,-47,-12,127,104,-102,93,-11,-73,121,87,-79,-92,46,92,-108,-107,79,121,-71,-89,16,-11,-52,72,-114,-32,-60,-9,-57,-4,10,-81,-22,68,74,76,-68,-127,96,-84,69,-3,-26,-106,-3,-87,-65,105,109,122,-103,31,-108,-86,-5,-39,85,88,67,-82,0,-25,93,61,-62,5,-54,-114,-51,-9,-114,20,49,-26,38,19,39,-103,33,-120,37,-97,32,-89,119,111,-124,-99,78,-49,-128,76,-18,-12,-109,96,90,-73,-104,59,-59,-92,123,55,54,-120,-80,-48,-16,-95,96,36,118,-119,-58,93,45,-43,-75,64,38,-2,-72,-111,22,-89,-75,-120,-42,45,108,59,-105,40,27,32,-66,121,-22,-71,-9,118,124,60,-96,47,4,14,-27,64,70,47,-91,-70,1,-44,94,-46,53,4,23,-124,-92,-95,83,-49,-81,40,-80,48,0,39,1,-113,32,40,-21,-1,-110,102,1,-74,-51,40,108,-35,-36,89,84,123,-48,-115,-115,83,-61,114,-127,-61,114,100,-82,-45,60,87,60,19,86,97,-68,40,-66,75,86,-32,-128,88,-57,-27,77,3,-27,43,-39,-62,66,5,-82,45,-104,-78,34,57,96,89,-90,66,-10,37,-110,-30,82,-58,13,94,12,115,35,117,0,80,61,-7,107,-104,-21,21,-70,-93,-94,-51,-61,39,-62,64,-82,-109,76,84,58,-47,-100,52,46,-51,88,91,8,-47,108,-80,25,-58,111,-59,-83,-75,92,98,110,54,106,65,-47,-120,-5,90,-123,101,-61,-85,-93,109,88,0,8,59,86,56,126,17,-26,58,-101,-25,35,0,-123,-3,-56,112,-128,8,17,-52,88,31,-3,105,-56,68,-1,-94,96,-19,10,-22,-88,-10,119,-44,19,42,75,-86,18,-107,89,-82,-120,76,40,84,-122,29,33,-47,17,-50,-13,23,-66,-46,85,-29,-110,42,-68,8,99,-93,-29,101,16,52,-13,127,0,86,-117,-92,-70,-32,-27,127,-123,1,34,-13,92,114,-11,29,-103,-121,-54,20,73,16,74,108,16,-61,89,50,-30,-14,116,44,-31,16,96,24,-51,7,39,-87,-69,-61,-98,61,-46,113,85,-95,103,67,99,-66,-45,-42,-70,96,104,5,-111,69,-25,99,-118,23,109,11,4,-41,-94,73,100,96,6,90,-75,-25,79,-13,-43,-6,-12,51,12,40,124,-56,81,-8,59,-60,-26,-54,33,122,85,53,-99,125,19,-26,94,41,-5,46,-48,-70,-10,41,102,-1,-98,-9,15,29,46,-66,-118,-53,45,119,-127,94,53,-58,90,124,5,-110,-98,-80,-77,77,29,19,105,-121,92,9,-124,50,-119,59,40,67,104,-12,13,103,101,47,-51,34,-66,-101,-117,112,-5,118,-48,-60,-114,38,-71,2,51,114,80,115,-5,116,20,16,-47,-19,30,24,-68,7,-30,-3,-64,-7,-34,-12,44,34,-91,-97,116,112,-99,108,-75,17,26,-14,-61,80,22,-7,34,47,-93,45,106,121,78,43,-97,39,-99,-68,-72,-7,64,-49,-82,-127,78,-64,48,18,15,126,-125,-111,-69,-111,10,-46,111,-75,123,-44,-67,-31,-96,-67,-53,-53,-106,67,-101,23,62,30,9,-114,-12,-57,-38,-78,95,-10,-3,110,88,123,-26,78,-125,114,53,10,-57,26,38,-51,73,92,-124,79,15,75,-62,109,-113,-67,1,35,52,-36,55,7,111,-43,109,101,88,122,-21,-32,-87,59,16,-122,-109,-118,17,-22,-39,53,-105,77,90,-24,-65,43,-27,113,30,-117,-30,106,37,55,59,54,-70,99,99,-73,120,97,-39,-88,-54,101,51,-76,70,-121,-68,23,-73,-31,75,-8,-63,-123,-93,96,-81,99,-95,28,-36,55,-104,32,-64,41,-97,95,-89,126,-26,-25,126,2,-26,-54,110,-86,110,74,-3,-110,56,-60,-49,117,-82,-55,-103,-112,70,-85,85,-63,82,7,75,-61,90,32,35,-115,72,73,-121,63,-84,-52,-29,-59,-4,29,64,119,127,58,-117,48,126,120,-115,-15,-10,27,27,-81,117,-5,121,-72,113,31,-13,10,27,-106,-51,81,-96,-22,19,-78,6,71,-34,123,118,75,-23,-72,-97,111,-121,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+
+#define HIDDEN_STATE_WEIGHT_X4 {-3,69,-33,102,76,60,80,19,59,-2,21,-4,-59,-59,11,-52,117,-25,70,121,-18,44,-74,-14,0,-1,44,-28,15,77,-102,92,108,-48,108,-100,99,-69,-19,121,-47,0,-80,-128,117,-123,99,-27,-118,60,34,-73,65,119,-50,-84,88,42,-91,-32,-108,79,-121,87,-123,118,-108,-88,-9,24,-104,85,8,-113,51,-112,33,118,94,1,26,-113,82,70,-95,-51,110,-96,-80,-98,107,118,-48,60,-97,102,-100,95,-69,77,76,-6,36,15,97,-52,-90,123,1,96,-58,120,17,-99,19,72,86,-109,-115,6,63,26,111,-102,45,35,-88,11,-40,-32,-125,120,38,-119,51,-109,110,113,24,22,123,-18,-23,16,58,6,-69,-68,-20,-112,-43,91,26,84,-31,-33,-37,-126,15,71,-65,103,-37,66,91,-29,-85,121,-47,111,-41,60,-88,-21,6,-120,-109,-76,106,33,-96,37,58,57,-100,10,108,25,78,-117,13,-39,-99,-43,108,93,23,93,1,56,116,41,104,-79,-43,-73,62,-104,86,110,-50,13,-70,77,-108,-107,-45,67,10,107,44,-52,30,111,-53,-113,112,90,74,-61,90,-4,34,58,96,64,79,44,-80,-119,-10,-125,-39,79,-20,67,71,72,-32,-85,-25,-18,-21,-66,0,36,-127,-96,-113,120,49,76,-117,-33,-124,-113,123,87,-49,106,-126,-76,21,-46,98,68,17,-96,-98,20,84,64,86,102,37,-117,92,63,76,-86,23,-60,55,-33,-116,-5,78,13,7,-71,-70,11,-50,-121,-127,56,-4,-105,77,-51,120,63,1,90,-46,-9,47,-56,124,59,-107,-35,59,27,78,-16,114,-33,-21,103,53,120,67,114,-48,74,-65,39,-99,23,6,124,-42,73,-15,-39,-98,-1,-115,99,85,-50,53,-85,-31,-95,116,51,-114,-71,7,-6,64,119,-46,118,-50,106,7,-41,105,-2,-13,30,70,-92,51,-69,-75,102,-101,26,110,-40,50,102,-52,-119,-55,119,20,-121,48,-3,101,-11,-51,2,125,-45,-126,-125,-120,-111,-19,9,-9,0,5,40,34,-115,-15,-5,46,-2,3,-41,81,-117,30,-89,-27,88,-39,-44,70,-7,-123,-11,114,-85,41,83,112,123,-50,-60,-30,19,25,-21,30,23,-72,81,76,-96,79,99,-6,-107,-83,75,71,82,107,43,-11,100,47,-40,-45,124,-97,-99,92,-3,74,89,102,-36,-84,89,67,3,44,-117,108,-100,49,-113,107,103,-26,-2,108,-34,60,47,101,-94,-113,112,-43,101,-37,-69,27,-38,110,39,-91,-101,-91,-28,-61,-37,37,-106,-69,60,59,121,-126,-71,-97,47,32,4,-32,-89,96,16,-89,14,119,-27,68,-11,-53,-52,111,64,-124,70,87,72,20,-114,-99,47,78,-91,54,-32,-24,-60,-49,-70,-128,1,46,-9,-95,-57,76,-44,-18,94,65,-4,-112,10,-12,-46,-109,53,22,-81,60,-22,96,4,90,23,122,68,-22,74,-73,-124,-104,-92,-106,76,-124,-68,59,-95,-59,83,97,-127,-37,96,-92,-49,123,-81,-86,-84,95,69,55,40,54,-80,-110,-3,-8,-26,-120,48,-80,0,44,-106,58,-3,-48,39,-16,1,-12,-87,-120,-65,-95,-113,96,32,-45,105,-86,109,36,40,118,-21,-32,122,-86,-103,-119,-1,-58,-110,-94,31,-14,-108,93,102,45,1,15,-86,29,-5,-43,-74,-75,-51,-8,-39,-114,85,64,40,38,108,71,88,70,67,-2,-35,-72,-36,-93,-82,-69,0,-111,89,22,84,100,-25,-123,93,-89,123,-75,-48,-18,61,-47,-62,-120,-115,-42,-115,-12,5,127,-54,45,83,108,-61,104,-114,-102,-51,59,114,-105,-127,93,-9,-11,-114,40,-61,27,114,-73,20,121,49,32,100,-66,-82,87,-26,-79,38,121,-45,-22,60,-92,19,46,39,-71,87,-9,60,92,-103,-108,33,118,19,124,86,-107,-120,79,37,60,97,-96,-68,40,-51,-66,88,-10,-61,119,89,75,91,86,8,-44,50,19,-30,-32,-47,-128,108,42,-14,75,116,88,-80,-57,25,-86,44,18,-31,-27,-58,77,111,-107,16,89,96,3,-59,-27,-83,-82,24,-120,-51,43,-75,-39,92,76,7,40,39,-62,98,66,110,84,-87,-122,-69,5,54,-82,106,29,-61,33,-98,45,65,-104,-47,-47,61,17,-46,-78,-120,34,-5,-50,113,-13,85,57,90,96,-123,23,-95,-66,103,89,101,-90,-61,-46,67,85,99,66,-85,-10,-93,-29,-66,-110,-45,37,109,-110,88,42,-42,-68,-70,-30,0,82,8,8,96,99,104,-58,59,13,86,-93,5,-29,-111,94,56,12,126,101,69,16,-25,115,17,35,-26,52,99,-13,-118,117,58,0,-101,127,23,0,109,80,-25,61,35,86,11,-117,4,-7,0,107,-123,-92,-41,-70,-94,-104,-3,-21,-56,-32,73,-27,100,21,112,-70,-128,127,96,-123,6,-93,8,-94,17,1,90,34,-75,-51,-52,-61,88,-13,-25,92,79,39,31,-62,-3,114,-13,-11,-43,64,105,-82,-56,29,-6,-103,-12,-109,68,76,-1,-121,51,-54,12,84,-94,58,96,20,40,73,124,-47,-19,-100,10,16,-56,74,81,52,-22,46,-88,108,-8,16,59,-60,-101,-26,-117,-127,-36,78,55,-54,112,33,-5,-64,7,48,111,122,118,85,-48,18,-43,15,109,53,-60,-99,-114,126,101,-125,88,125,38,19,-71,-111,122,-69,-21,-26,2,94,51,-111,-32,10,-87,41,114,-5,80,-46,59,111,16,46,115,-48,-5,-75,-122,123,-109,-70,116,-10,20,-44,-118,-67,17,41,16,102,-47,-31,-22,-96,-39,-1,-19,-98,30,-67,53,-53,-105,-9,24,15,-68,-53,77,-106,90,29,7,46,-30,67,-24,-101,-65,-66,-3,-118,-64,23,43,62,-27,-53,-7,45,-34,30,113,9,30,119,-12,-127,44,-114,-117,-12,-30,94,34,53,-91,-57,106,-38,37,-58,-97,90,116,-78,55,95,59,124,112,5,-99,-10,54,-3,-70,-110,108,-98,-75,110,99,88,99,-80,17,-77,26,123,-73,-26,120,77,-14,29,-61,78,97,-125,-39,19,80,105,22,114,-88,53,-54,-121,-7,92,34,10,101,-57,51,9,47,-124,-93,26,-76,38,70,50,45,-119,106,-51,-121,73,-68,59,121,40,78,92,23,-124,-73,67,43,104,-97,79,-31,15,75,-12,39,13,-99,75,-8,-62,-63,103,-68,101,-72,109,-123,-113,-93,47,-7,-51,64,-67,96,1,-81,34,-49,-66,-82,35,99,52,-95,28,27,-36,27,-93,-15,52,-68,55,-81,-104,117,67,-3,53,102,32,-5,-64,121,-31,-10,19,-123,41,-72,-97,113,45,-10,-111,-71,95,31,-89,-13,36,-111,39,86,126,10,-26,27,-91,48,-77,-45,-25,-106,126,-51,104,101,71,81,2,81,-26,-96,7,-114,-44,-94,-54,-22,110,19,-76,77,3,-127,-86,-78,110,6,-62,-96,121,-100,74,71,-3,-34,43,86,37,109,-110,123,56,118,-7,-33,-96,15,-60,75,-49,-23,-6,-34,57,60,117,-72,-82,-97,-104,88,30,-86,-55,111,-103,-121,-126,-63,-94,-103,-112,0,70,80,118,-46,-44,101,-85,28,85,52,91,-127,29,-88,-63,95,82,59,124,90,-86,-37,7,-116,75,72,-13,82,55,-125,-61,80,90,-75,41,-28,-41,-6,32,-62,35,88,91,61,-112,-104,-115,23,72,-102,-25,77,103,0,73,13,-121,6,81,-52,-70,59,63,113,-84,-85,-112,-9,113,-82,-52,98,-29,45,-25,59,-73,-78,-59,-96,-4,-32,-82,79,16,80,29,94,64,-7,67,-77,-5,-125,119,12,127,-9,104,-95,56,16,58,86,-117,18,66,26,-115,-55,48,59,126,-15,-90,-16,-126,15,120,75,-115,13,106,-76,80,-9,-15,-70,-10,50,-78,56,-51,110,85,-29,-102,20,15,-56,-73,-64,-23,-66,-12,-80,-128,-6,-121,-103,-6,-122,-97,40,46,-36,30,-2,-34,-2,32,116,-93,-59,-109,34,-79,126,-95,-120,-15,-40,-86,-64,71,-48,126,124,-2,-39,75,-64,127,57,30,-107,1,-74,-32,-105,-112,104,-115,80,-27,50,-86,-86,75,-13,-8,81,-13,-66,-38,-14,125,118,103,33,48,-71,10,35,-118,88,65,119,-36,-116,-107,-20,-43,-110,107,33,-27,15,-48,-119,46,-35,96,-75,88,-12,-7,90,-41,-6,-87,89,-88,-117,98,-29,-64,-41,-18,99,-83,13,61,-8,126,46,82,127,-81,-75,20,57,10,-36,81,54,-123,67,18,124,45,-55,95,50,-41,-38,-127,66,61,24,9,51,-55,113,-66,-80,28,49,-113,-71,24,113,-107,105,-71,37,47,-117,73,45,30,-74,117,114,26,6,-42,-80,-74,108,-81,110,73,88,124,-24,-43,-3,49,84,-55,-30,-125,36,102,62,-126,-45,-33,-50,98,-8,6,109,62,113,-84,-12,32,-40,24,-101,-87,-57,-56,59,-123,106,32,12,-71,-18,97,49,113,-47,105,-113,49,99,-124,-124,-81,-118,117,-12,-76,46,-9,-48,-41,-3,-54,-86,97,88,119,-82,-113,-52,-126,-93,-23,-121,127,-97,-28,-24,31,-62,-119,52,-93,75,7,33,-101,-67,67,-45,39,74,-83,127,-115,-66,4,-6,-18,-29,29,-23,68,-123,-103,31,24,117,49,8,-70,41,1,20,71,99,-40,-21,-116,-30,93,66,95,27,63,117,-49,20,-113,-92,-7,127,115,-85,97,-39,34,-67,-10,-53,123,-87,119,2,-77,68,-74,-66,22,96,-13,-12,96,-26,86,35,47,-128,-4,83,52,114,-2,-84,-14,67,-94,-53,-45,-74,-71,-94,94,-101,-122,3,-48,-14,124,-43,56,-3,58,-22,-97,-106,1,-32,57,-16,-127,51,23,-67,-59,-27,-60,125,-46,-125,-117,28,-74,29,29,-76,94,25,58,-32,-31,-101,-105,42,49,101,-115,-60,114,-55,-72,101,94,35,-14,-6,-115,-101,20,-36,-8,103,77,-42,82,61,104,85,35,-71,100,111,67,107,-90,-24,19,6,117,-87,-16,-67,-26,26,24,105,-64,102,105,-36,-7,60,109,112,-19,119,59,-81,10,-91,-9,69,124,-54,124,52,80,13,-105,21,-116,-114,-33,5,0,10,126,-93,22,-26,-115,115,94,22,105,-111,30,-7,102,44,63,0,85,-38,91,-30,98,-21,43,4,-63,-34,-124,-67,38,33,-2,45,-32,-86,12,-92,-38,29,39,121,-119,-42,-23,-30,-106,3,-12,-54,-108,7}
+
+#define UPDATE_GATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103}
+
+#define RESET_GATE_BIAS {-77,67,-93,-3,98,59,-121,33,49,50,41,91,-115,-33,71,47,-70,45,89,-115,72,106,-22,100,97,-100,-95,108,-33,3,14,30}
+
+#define HIDDEN_STATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103}
+
+#define INPUT_DATA1 {-367,-338,0,-89,453,-413,-343,-16,42,418,201,274,-352,477,-290,-92,266,-49,342,453,-398,247,-153,328,217,342,85,69,-38,351,73,128}
+
+#define INPUT_DATA2 {280,41,-322,61,315,350,504,-227,-221,-483,352,252,455,-236,344,364,-378,229,-187,-498,295,357,-511,58,-349,-458,-420,-66,-400,-379,477,-60}
+
+#define HISTORY_DATA {-38,53,105,-79,-463,51,-343,-226,-435,-282,218,441,-299,-215,-109,335,340,-471,-109,273,33,-245,-469,170,-26,-59,192,-119,76,-6,236,-145}
diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt
new file mode 100644
index 0000000..99cf676
--- /dev/null
+++ b/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt
@@ -0,0 +1,4 @@
+CMSIS NN Lib example arm_nnexample_gru0 for
+  Cortex-M4 and Cortex-M7.
+
+The example is configured for uVision Simulator.
diff --git a/Drivers/CMSIS/NN/Include/arm_nn_tables.h b/Drivers/CMSIS/NN/Include/arm_nn_tables.h
new file mode 100644
index 0000000..9357424
--- /dev/null
+++ b/Drivers/CMSIS/NN/Include/arm_nn_tables.h
@@ -0,0 +1,59 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nn_tables.h
+ * Description:  Extern declaration for NN tables
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_NN_TABLES_H
+#define _ARM_NN_TABLES_H
+
+#include "arm_math.h"
+
+/**
+* @brief tables for various activation functions
+*
+*/
+
+extern const q15_t sigmoidTable_q15[256];
+extern const q7_t sigmoidTable_q7[256];
+
+extern const q7_t tanhTable_q7[256];
+extern const q15_t tanhTable_q15[256];
+
+  /**
+   * @brief 2-way tables for various activation functions
+   *
+   * 2-way table, H table for value larger than 1/4
+   * L table for value smaller than 1/4, H table for remaining
+   * We have this only for the q15_t version. It does not make
+   * sense to have it for q7_t type
+   */
+extern const q15_t sigmoidHTable_q15[192];
+extern const q15_t sigmoidLTable_q15[128];
+
+extern const q15_t sigmoidLTable_q15[128];
+extern const q15_t sigmoidHTable_q15[192];
+
+#endif                          /*  ARM_NN_TABLES_H */
diff --git a/Drivers/CMSIS/NN/Include/arm_nnfunctions.h b/Drivers/CMSIS/NN/Include/arm_nnfunctions.h
new file mode 100644
index 0000000..96c59c2
--- /dev/null
+++ b/Drivers/CMSIS/NN/Include/arm_nnfunctions.h
@@ -0,0 +1,1010 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nnfunctions.h
+ * Description:  Public header file for CMSIS NN Library
+ *
+ * $Date:        13. July 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS NN Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS NN software library,
+   * a collection of efficient neural network kernels developed to maximize the 
+   * performance and minimize the memory footprint of neural networks on Cortex-M processor cores.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Neural Network Convolution Functions
+   * - Neural Network Activation Functions
+   * - Fully-connected Layer Functions
+   * - Neural Network Pooling Functions
+   * - Softmax Functions
+   * - Neural Network Support Functions
+   *
+   * The library has separate functions for operating on different weight and activation data
+   * types including 8-bit integers (q7_t) and 16-bit integers (q15_t). The descrition of the
+   * kernels are included in the function description. The implementation details are also 
+   * described in this paper [1]. 
+   *
+   * Block Diagram
+   * --------
+   * \image html CMSIS-NN-OVERVIEW.PNG
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - ARM_MATH_DSP:
+   *
+   * Define macro ARM_MATH_DSP, If the silicon supports DSP instructions.
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_NN_TRUNCATE:
+   *
+   * Define macro ARM_NN_TRUNCATE to use floor instead of round-to-the-nearest-int for the computation.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2018 Arm Limited. All rights reserved.
+   *
+   * [1] CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs https://arxiv.org/abs/1801.06601
+   */
+
+/**
+ * @defgroup groupNN Neural Network Functions
+ * These functions perform basic operations for neural network layers. 
+ */
+
+#ifndef _ARM_NNFUNCTIONS_H
+#define _ARM_NNFUNCTIONS_H
+
+#include "arm_nnsupportfunctions.h"
+#include "arm_nn_tables.h"
+
+#define USE_INTRINSIC
+
+//#define ARM_NN_TRUNCATE /* This config the rounding model to floor or round to the nearest int */
+
+#ifdef __cplusplus
+extern    "C"
+{
+#endif
+
+/**
+ * @defgroup NNConv Neural Network Convolution Functions
+ *
+ * Perform convolution layer
+ *
+ * The convolution is implemented in 2 steps: im2col and GEMM
+ *
+ * im2col is a process of converting each patch of image data into 
+ * a column. After im2col, the convolution is computed as matrix-matrix
+ * multiplication.
+ * 
+ * To reduce the memory footprint, the im2col is performed partially.
+ * Each iteration, only a few column (i.e., patches) are generated and 
+ * computed with GEMM kernels similar to CMSIS-DSP arm_mat_mult functions.
+ *
+ */
+
+  /**
+   * @brief Basic Q7 convolution function
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       wt          pointer to kernel weights
+   * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       bias        pointer to bias
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input 
+   * @param[in,out]   bufferB     pointer to buffer space for output
+   * @return     The function returns ARM_MATH_SUCCESS 
+   *
+   */
+
+    arm_status arm_convolve_HWC_q7_basic(const q7_t * Im_in,
+                                         const uint16_t dim_im_in,
+                                         const uint16_t ch_im_in,
+                                         const q7_t * wt,
+                                         const uint16_t ch_im_out,
+                                         const uint16_t dim_kernel,
+                                         const uint16_t padding,
+                                         const uint16_t stride,
+                                         const q7_t * bias,
+                                         const uint16_t bias_shift,
+                                         const uint16_t out_shift,
+                                         q7_t * Im_out, 
+                                         const uint16_t dim_im_out, 
+                                         q15_t * bufferA, 
+                                         q7_t * bufferB);
+
+  /**
+   * @brief Basic Q7 convolution function (non-sqaure shape)
+   * @param[in]       Im_in        pointer to input tensor
+   * @param[in]       dim_im_in_x  input tensor dimention x
+   * @param[in]       dim_im_in_y  input tensor dimention y
+   * @param[in]       ch_im_in     number of input tensor channels
+   * @param[in]       wt           pointer to kernel weights
+   * @param[in]       ch_im_out    number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel_x filter kernel size x
+   * @param[in]       dim_kernel_y filter kernel size y
+   * @param[in]       padding_x    padding size x
+   * @param[in]       padding_y    padding size y
+   * @param[in]       stride_x     convolution stride x
+   * @param[in]       stride_y     convolution stride y
+   * @param[in]       bias         pointer to bias
+   * @param[in]       bias_shift   amount of left-shift for bias
+   * @param[in]       out_shift    amount of right-shift for output
+   * @param[in,out]   Im_out       pointer to output tensor
+   * @param[in]       dim_im_out_x output tensor dimension x
+   * @param[in]       dim_im_out_y output tensor dimension y
+   * @param[in,out]   bufferA      pointer to buffer space for input
+   * @param[in,out]   bufferB      pointer to buffer space for output
+   * @return     The function returns ARM_MATH_SUCCESS 
+   */
+
+    arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in,
+                                                  const uint16_t dim_im_in_x,
+                                                  const uint16_t dim_im_in_y,
+                                                  const uint16_t ch_im_in,
+                                                  const q7_t * wt,
+                                                  const uint16_t ch_im_out,
+                                                  const uint16_t dim_kernel_x,
+                                                  const uint16_t dim_kernel_y,
+                                                  const uint16_t padding_x,
+                                                  const uint16_t padding_y,
+                                                  const uint16_t stride_x,
+                                                  const uint16_t stride_y,
+                                                  const q7_t * bias,
+                                                  const uint16_t bias_shift,
+                                                  const uint16_t out_shift,
+                                                  q7_t * Im_out,
+                                                  const uint16_t dim_im_out_x,
+                                                  const uint16_t dim_im_out_y,
+                                                  q15_t * bufferA,
+                                                  q7_t * bufferB);
+
+  /**
+   * @brief Basic Q15 convolution function
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       wt          pointer to kernel weights
+   * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       bias        pointer to bias
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input 
+   * @param[in,out]   bufferB     pointer to buffer space for output
+   * @return     The function returns ARM_MATH_SUCCESS 
+   *
+   */
+
+    arm_status arm_convolve_HWC_q15_basic(const q15_t * Im_in,
+                                          const uint16_t dim_im_in,
+                                          const uint16_t ch_im_in,
+                                          const q15_t * wt,
+                                          const uint16_t ch_im_out,
+                                          const uint16_t dim_kernel,
+                                          const uint16_t padding,
+                                          const uint16_t stride,
+                                          const q15_t * bias,
+                                          const uint16_t bias_shift,
+                                          const uint16_t out_shift,
+                                          q15_t * Im_out, 
+                                          const uint16_t dim_im_out, 
+                                          q15_t * bufferA, 
+                                          q7_t * bufferB);
+
+  /**
+   * @brief Fast Q7 convolution function
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       wt          pointer to kernel weights
+   * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       bias        pointer to bias
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input 
+   * @param[in,out]   bufferB     pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * This function is the version with full list of optimization tricks, but with
+   * some contraints:
+   *   ch_im_in is multiple of 4
+   *   ch_im_out is multiple of 2
+   */
+
+    arm_status arm_convolve_HWC_q7_fast(const q7_t * Im_in,
+                                        const uint16_t dim_im_in,
+                                        const uint16_t ch_im_in,
+                                        const q7_t * wt,
+                                        const uint16_t ch_im_out,
+                                        const uint16_t dim_kernel,
+                                        const uint16_t padding,
+                                        const uint16_t stride,
+                                        const q7_t * bias,
+                                        const uint16_t bias_shift,
+                                        const uint16_t out_shift,
+                                        q7_t * Im_out, 
+                                        const uint16_t dim_im_out, 
+                                        q15_t * bufferA, 
+                                        q7_t * bufferB);
+
+  /**
+   * @brief Fast Q7 convolution function (non-sqaure shape)
+   * @param[in]       Im_in        pointer to input tensor
+   * @param[in]       dim_im_in_x  input tensor dimention x
+   * @param[in]       dim_im_in_y  input tensor dimention y
+   * @param[in]       ch_im_in     number of input tensor channels
+   * @param[in]       wt           pointer to kernel weights
+   * @param[in]       ch_im_out    number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel_x filter kernel size x
+   * @param[in]       dim_kernel_y filter kernel size y
+   * @param[in]       padding_x    padding size x
+   * @param[in]       padding_y    padding size y
+   * @param[in]       stride_x     convolution stride x
+   * @param[in]       stride_y     convolution stride y
+   * @param[in]       bias         pointer to bias
+   * @param[in]       bias_shift   amount of left-shift for bias
+   * @param[in]       out_shift    amount of right-shift for output
+   * @param[in,out]   Im_out       pointer to output tensor
+   * @param[in]       dim_im_out_x output tensor dimension x
+   * @param[in]       dim_im_out_y output tensor dimension y
+   * @param[in,out]   bufferA      pointer to buffer space for input 
+   * @param[in,out]   bufferB      pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * This function is the version with full list of optimization tricks, but with
+   * some contraints:
+   *   ch_im_in is multiple of 4
+   *   ch_im_out is multiple of 2
+   */
+
+    arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t * Im_in,
+                                                  const uint16_t dim_im_in_x,
+                                                  const uint16_t dim_im_in_y,
+                                                  const uint16_t ch_im_in,
+                                                  const q7_t * wt,
+                                                  const uint16_t ch_im_out,
+                                                  const uint16_t dim_kernel_x,
+                                                  const uint16_t dim_kernel_y,
+                                                  const uint16_t padding_x,
+                                                  const uint16_t padding_y,
+                                                  const uint16_t stride_x,
+                                                  const uint16_t stride_y,
+                                                  const q7_t * bias,
+                                                  const uint16_t bias_shift,
+                                                  const uint16_t out_shift,
+                                                  q7_t * Im_out,
+                                                  const uint16_t dim_im_out_x,
+                                                  const uint16_t dim_im_out_y,
+                                                  q15_t * bufferA,
+                                                  q7_t * bufferB);
+
+  /**
+   * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape)
+   * @param[in]       Im_in        pointer to input tensor
+   * @param[in]       dim_im_in_x  input tensor dimention x
+   * @param[in]       dim_im_in_y  input tensor dimention y
+   * @param[in]       ch_im_in     number of input tensor channels
+   * @param[in]       wt           pointer to kernel weights
+   * @param[in]       ch_im_out    number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel_x filter kernel size x
+   * @param[in]       dim_kernel_y filter kernel size y
+   * @param[in]       padding_x    padding size x
+   * @param[in]       padding_y    padding size y
+   * @param[in]       stride_x     convolution stride x
+   * @param[in]       stride_y     convolution stride y
+   * @param[in]       bias         pointer to bias
+   * @param[in]       bias_shift   amount of left-shift for bias
+   * @param[in]       out_shift    amount of right-shift for output
+   * @param[in,out]   Im_out       pointer to output tensor
+   * @param[in]       dim_im_out_x output tensor dimension x
+   * @param[in]       dim_im_out_y output tensor dimension y
+   * @param[in,out]   bufferA      pointer to buffer space for input 
+   * @param[in,out]   bufferB      pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * This function implement convolution with 1x1 kernel size (i.e., dim_kernel_x=1
+   * and dim_kernel_y=1). It can be used for
+   * second half of MobileNets after depthwise separable convolution.
+   *
+   * This function is the version with full list of optimization tricks, but with
+   * some contraints:
+   *   ch_im_in is multiple of 4
+   *   ch_im_out is multiple of 2
+   */
+    arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t * Im_in,
+                                                      const uint16_t dim_im_in_x,
+                                                      const uint16_t dim_im_in_y,
+                                                      const uint16_t ch_im_in,
+                                                      const q7_t * wt,
+                                                      const uint16_t ch_im_out,
+                                                      const uint16_t dim_kernel_x,
+                                                      const uint16_t dim_kernel_y,
+                                                      const uint16_t padding_x,
+                                                      const uint16_t padding_y,
+                                                      const uint16_t stride_x,
+                                                      const uint16_t stride_y,
+                                                      const q7_t * bias,
+                                                      const uint16_t bias_shift,
+                                                      const uint16_t out_shift,
+                                                      q7_t * Im_out,
+                                                      const uint16_t dim_im_out_x,
+                                                      const uint16_t dim_im_out_y,
+                                                      q15_t * bufferA,
+                                                      q7_t * bufferB);
+
+  /**
+   * @brief Q7 version of convolution for RGB image
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       wt          pointer to kernel weights
+   * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       bias        pointer to bias
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input 
+   * @param[in,out]   bufferB     pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * This kernel is written exclusively for convolution with ch_im_in
+   * equals 3. This applies on the first layer of CNNs which has input
+   * image with RGB format.
+   */
+
+    arm_status arm_convolve_HWC_q7_RGB(const q7_t * Im_in,
+                                       const uint16_t dim_im_in,
+                                       const uint16_t ch_im_in,
+                                       const q7_t * wt,
+                                       const uint16_t ch_im_out,
+                                       const uint16_t dim_kernel,
+                                       const uint16_t padding,
+                                       const uint16_t stride,
+                                       const q7_t * bias,
+                                       const uint16_t bias_shift,
+                                       const uint16_t out_shift,
+                                       q7_t * Im_out, 
+                                       const uint16_t dim_im_out, 
+                                       q15_t * bufferA, 
+                                       q7_t * bufferB);
+
+  /**
+   * @brief Fast Q15 convolution function
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       wt          pointer to kernel weights
+   * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       bias        pointer to bias
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input 
+   * @param[in,out]   bufferB     pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * This function is the version with full list of optimization tricks, but with
+   * some contraints:
+   *   ch_im_in is multiple of 2
+   *   ch_im_out is multiple of 2
+   */
+
+    arm_status arm_convolve_HWC_q15_fast(const q15_t * Im_in,
+                                         const uint16_t dim_im_in,
+                                         const uint16_t ch_im_in,
+                                         const q15_t * wt,
+                                         const uint16_t ch_im_out,
+                                         const uint16_t dim_kernel,
+                                         const uint16_t padding,
+                                         const uint16_t stride,
+                                         const q15_t * bias,
+                                         const uint16_t bias_shift,
+                                         const uint16_t out_shift,
+                                         q15_t * Im_out, 
+                                         const uint16_t dim_im_out, 
+                                         q15_t * bufferA, 
+                                         q7_t * bufferB);
+
+  /**
+   * @brief Fast Q15 convolution function (non-sqaure shape)
+   * @param[in]       Im_in        pointer to input tensor
+   * @param[in]       dim_im_in_x  input tensor dimention x
+   * @param[in]       dim_im_in_y  input tensor dimention y
+   * @param[in]       ch_im_in     number of input tensor channels
+   * @param[in]       wt           pointer to kernel weights
+   * @param[in]       ch_im_out    number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel_x filter kernel size x
+   * @param[in]       dim_kernel_y filter kernel size y
+   * @param[in]       padding_x    padding size x
+   * @param[in]       padding_y    padding size y
+   * @param[in]       stride_x     convolution stride x
+   * @param[in]       stride_y     convolution stride y
+   * @param[in]       bias         pointer to bias
+   * @param[in]       bias_shift   amount of left-shift for bias
+   * @param[in]       out_shift    amount of right-shift for output
+   * @param[in,out]   Im_out       pointer to output tensor
+   * @param[in]       dim_im_out_x output tensor dimension x
+   * @param[in]       dim_im_out_y output tensor dimension y
+   * @param[in,out]   bufferA      pointer to buffer space for input 
+   * @param[in,out]   bufferB      pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
+   *
+   * bufferB size: 0
+   *
+   * Input dimension constraints:
+   *
+   * ch_im_in is multiple of 2 
+   *
+   * ch_im_out is multipe of 2
+   *
+   */
+
+    arm_status
+    arm_convolve_HWC_q15_fast_nonsquare(const q15_t * Im_in,
+                              const uint16_t dim_im_in_x,
+                              const uint16_t dim_im_in_y,
+                              const uint16_t ch_im_in,
+                              const q15_t * wt,
+                              const uint16_t ch_im_out,
+                              const uint16_t dim_kernel_x,
+                              const uint16_t dim_kernel_y,
+                              const uint16_t padding_x,
+                              const uint16_t padding_y,
+                              const uint16_t stride_x,
+                              const uint16_t stride_y,
+                              const q15_t * bias,
+                              const uint16_t bias_shift,
+                              const uint16_t out_shift,
+                              q15_t * Im_out,
+                              const uint16_t dim_im_out_x,
+                              const uint16_t dim_im_out_y, 
+                              q15_t * bufferA, 
+                              q7_t * bufferB);
+										 
+  /**
+   * @brief Q7 depthwise separable convolution function
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       wt          pointer to kernel weights
+   * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       bias        pointer to bias
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input 
+   * @param[in,out]   bufferB     pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * This function is the version with full list of optimization tricks, but with
+   * some contraints:
+   *   ch_im_in is multiple of 2
+   *   ch_im_out is multiple of 2
+   */
+
+    arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t * Im_in,
+                                                   const uint16_t dim_im_in,
+                                                   const uint16_t ch_im_in,
+                                                   const q7_t * wt,
+                                                   const uint16_t ch_im_out,
+                                                   const uint16_t dim_kernel,
+                                                   const uint16_t padding,
+                                                   const uint16_t stride,
+                                                   const q7_t * bias,
+                                                   const uint16_t bias_shift,
+                                                   const uint16_t out_shift,
+                                                   q7_t * Im_out,
+                                                   const uint16_t dim_im_out, 
+                                                   q15_t * bufferA, 
+                                                   q7_t * bufferB);
+
+  /**
+   * @brief Q7 depthwise separable convolution function (non-square shape)
+   * @param[in]       Im_in         pointer to input tensor
+   * @param[in]       dim_im_in_x   input tensor dimention x
+   * @param[in]       dim_im_in_y   input tensor dimention y
+   * @param[in]       ch_im_in      number of input tensor channels
+   * @param[in]       wt            pointer to kernel weights
+   * @param[in]       ch_im_out     number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel_x  filter kernel size x
+   * @param[in]       dim_kernel_y  filter kernel size y
+   * @param[in]       padding_x     padding sizes x
+   * @param[in]       padding_y     padding sizes y
+   * @param[in]       stride_x      convolution stride x
+   * @param[in]       stride_y      convolution stride y
+   * @param[in]       bias          pointer to bias
+   * @param[in]       bias_shift    amount of left-shift for bias
+   * @param[in]       out_shift     amount of right-shift for output
+   * @param[in,out]   Im_out        pointer to output tensor
+   * @param[in]       dim_im_out_x  output tensor dimension x
+   * @param[in]       dim_im_out_y  output tensor dimension y
+   * @param[in,out]   bufferA       pointer to buffer space for input 
+   * @param[in,out]   bufferB       pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * This function is the version with full list of optimization tricks, but with
+   * some contraints:
+   *   ch_im_in is multiple of 2
+   *   ch_im_out is multiple of 2
+   */
+    arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t * Im_in,
+                                                             const uint16_t dim_im_in_x,
+                                                             const uint16_t dim_im_in_y,
+                                                             const uint16_t ch_im_in,
+                                                             const q7_t * wt,
+                                                             const uint16_t ch_im_out,
+                                                             const uint16_t dim_kernel_x,
+                                                             const uint16_t dim_kernel_y,
+                                                             const uint16_t padding_x,
+                                                             const uint16_t padding_y,
+                                                             const uint16_t stride_x,
+                                                             const uint16_t stride_y,
+                                                             const q7_t * bias,
+                                                             const uint16_t bias_shift,
+                                                             const uint16_t out_shift,
+                                                             q7_t * Im_out,
+                                                             const uint16_t dim_im_out_x,
+                                                             const uint16_t dim_im_out_y,
+                                                             q15_t * bufferA,
+                                                             q7_t * bufferB);
+
+
+/**
+ * @defgroup FC Fully-connected Layer Functions
+ *
+ * Perform fully-connected layer
+ *
+ * Fully-connected layer is basically a matrix-vector multiplication
+ * with bias. The matrix is the weights and the input/output vectors
+ * are the activation values. Supported {weight, activation} precisions
+ * include {8-bit, 8-bit}, {16-bit, 16-bit}, and {8-bit, 16-bit}.
+ *
+ * Here we have two types of kernel functions. The basic function
+ * implements the function using regular GEMV approach. The opt functions
+ * operates with weights in interleaved formats. 
+ *
+ */
+
+  /**
+   * @brief Q7 basic fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   */
+
+    arm_status arm_fully_connected_q7(const q7_t * pV,
+                                      const q7_t * pM,
+                                      const uint16_t dim_vec,
+                                      const uint16_t num_of_rows,
+                                      const uint16_t bias_shift,
+                                      const uint16_t out_shift, 
+                                      const q7_t * bias, 
+                                      q7_t * pOut, 
+                                      q15_t * vec_buffer);
+
+  /**
+   * @brief Q7 opt fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   */
+
+    arm_status arm_fully_connected_q7_opt(const q7_t * pV,
+                                          const q7_t * pM,
+                                          const uint16_t dim_vec,
+                                          const uint16_t num_of_rows,
+                                          const uint16_t bias_shift,
+                                          const uint16_t out_shift, 
+                                          const q7_t * bias, 
+                                          q7_t * pOut, 
+                                          q15_t * vec_buffer);
+
+  /**
+   * @brief Q15 basic fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   */
+
+    arm_status arm_fully_connected_q15(const q15_t * pV,
+                                       const q15_t * pM,
+                                       const uint16_t dim_vec,
+                                       const uint16_t num_of_rows,
+                                       const uint16_t bias_shift,
+                                       const uint16_t out_shift, 
+                                       const q15_t * bias, 
+                                       q15_t * pOut, 
+                                       q15_t * vec_buffer);
+
+  /**
+   * @brief Q15 opt fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   */
+
+    arm_status arm_fully_connected_q15_opt(const q15_t * pV,
+                                           const q15_t * pM,
+                                           const uint16_t dim_vec,
+                                           const uint16_t num_of_rows,
+                                           const uint16_t bias_shift,
+                                           const uint16_t out_shift,
+                                           const q15_t * bias, 
+                                           q15_t * pOut, 
+                                           q15_t * vec_buffer);
+
+  /**
+   * @brief Mixed Q15-Q7 fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   */
+
+    arm_status arm_fully_connected_mat_q7_vec_q15(const q15_t * pV,
+                                                  const q7_t * pM,
+                                                  const uint16_t dim_vec,
+                                                  const uint16_t num_of_rows,
+                                                  const uint16_t bias_shift,
+                                                  const uint16_t out_shift,
+                                                  const q7_t * bias, 
+                                                  q15_t * pOut, 
+                                                  q15_t * vec_buffer);
+
+  /**
+   * @brief Mixed Q15-Q7 opt fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   */
+
+    arm_status arm_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV,
+                                                      const q7_t * pM,
+                                                      const uint16_t dim_vec,
+                                                      const uint16_t num_of_rows,
+                                                      const uint16_t bias_shift,
+                                                      const uint16_t out_shift,
+                                                      const q7_t * bias, 
+                                                      q15_t * pOut, 
+                                                      q15_t * vec_buffer);
+
+/**
+ * @brief Matrix-Multiplication Kernels for Convolution
+ *
+ * These functions are used within convolution layer functions for 
+ * matrix multiplication.
+ * 
+ * The implementation is similar to CMSIS-DSP arm_mat_mult functions
+ * with one Q7 and one Q15 operands. The Q15 operand is the im2col
+ * output which is always with 2 columns.
+ *
+ */
+
+  /**
+   * @brief Matrix-multiplication function for convolution
+   * @param[in]       pA          pointer to operand A
+   * @param[in]       pInBuffer   pointer to operand B, always conssists of 2 vectors
+   * @param[in]       ch_im_out   numRow of A
+   * @param[in]       numCol_A    numCol of A
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        the bias
+   * @param[in,out]   pOut        pointer to output
+   * @return     The function returns the incremented output pointer
+   */
+
+    q7_t     *arm_nn_mat_mult_kernel_q7_q15(const q7_t * pA,
+                                            const q15_t * pInBuffer,
+                                            const uint16_t ch_im_out,
+                                            const uint16_t numCol_A,
+                                            const uint16_t bias_shift,
+                                            const uint16_t out_shift, 
+                                            const q7_t * bias, 
+                                            q7_t * pOut);
+
+  /**
+   * @brief Matrix-multiplication function for convolution with reordered columns
+   * @param[in]       pA          pointer to operand A
+   * @param[in]       pInBuffer   pointer to operand B, always conssists of 2 vectors
+   * @param[in]       ch_im_out   numRow of A
+   * @param[in]       numCol_A    numCol of A
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        the bias
+   * @param[in,out]   pOut        pointer to output
+   * @return     The function returns the incremented output pointer
+   */
+
+    q7_t     *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t * pA,
+                                                      const q15_t * pInBuffer,
+                                                      const uint16_t ch_im_out,
+                                                      const uint16_t numCol_A,
+                                                      const uint16_t bias_shift,
+                                                      const uint16_t out_shift, 
+                                                      const q7_t * bias, 
+                                                      q7_t * pOut);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*
+ *  Other functions
+ *  These layers are typically not timing critical
+ *  Basic implementation is supported here
+ */
+
+#ifdef __cplusplus
+extern    "C"
+{
+#endif
+
+/**
+ * @defgroup Acti Neural Network Activation Functions
+ *
+ * Perform activation layers, including ReLU (Rectified Linear Unit),
+ * sigmoid and tanh
+ *
+ */
+
+  /**
+   * @brief Q7 RELU function
+   * @param[in,out]   data        pointer to input
+   * @param[in]       size        number of elements
+   * @return none.
+   */
+
+    void      arm_relu_q7(q7_t * data, uint16_t size);
+
+  /**
+   * @brief Q15 RELU function
+   * @param[in,out]   data        pointer to input
+   * @param[in]       size        number of elements
+   * @return none.
+   */
+
+    void      arm_relu_q15(q15_t * data, uint16_t size);
+
+  /**
+   * @brief Q7 neural network activation function using direct table look-up
+   * @param[in,out]   data        pointer to input
+   * @param[in]       size        number of elements
+   * @param[in]       int_width   bit-width of the integer part, assume to be smaller than 3
+   * @param[in]       type        type of activation functions
+   * @return none.
+   */
+
+    void      arm_nn_activations_direct_q7(q7_t * data, uint16_t size, uint16_t int_width, 
+                                           arm_nn_activation_type type);
+
+  /**
+   * @brief Q15 neural network activation function using direct table look-up
+   * @param[in,out]   data        pointer to input
+   * @param[in]       size        number of elements
+   * @param[in]       int_width   bit-width of the integer part, assume to be smaller than 3
+   * @param[in]       type        type of activation functions
+   * @return none.
+   */
+
+    void      arm_nn_activations_direct_q15(q15_t * data, uint16_t size, uint16_t int_width,
+                                            arm_nn_activation_type type);
+
+/**
+ * @defgroup Pooling Neural Network Pooling Functions
+ *
+ * Perform pooling functions, including max pooling and average pooling
+ *
+ */
+
+  /**
+   * @brief Q7 max pooling function
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @return none.
+   *
+   */
+
+    void      arm_maxpool_q7_HWC(q7_t * Im_in,
+                                 const uint16_t dim_im_in,
+                                 const uint16_t ch_im_in,
+                                 const uint16_t dim_kernel,
+                                 const uint16_t padding,
+                                 const uint16_t stride, 
+                                 const uint16_t dim_im_out, 
+                                 q7_t * bufferA, 
+                                 q7_t * Im_out);
+
+  /**
+   * @brief Q7 average pooling function
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @return none.
+   *
+   */
+
+    void      arm_avepool_q7_HWC(q7_t * Im_in,
+                                 const uint16_t dim_im_in,
+                                 const uint16_t ch_im_in,
+                                 const uint16_t dim_kernel,
+                                 const uint16_t padding,
+                                 const uint16_t stride, 
+                                 const uint16_t dim_im_out, 
+                                 q7_t * bufferA, 
+                                 q7_t * Im_out);
+
+/**
+ * @defgroup Softmax Softmax Functions
+ *
+ * EXP(2) based softmax function
+ *
+ */
+
+  /**
+   * @brief Q7 softmax function
+   * @param[in]       vec_in      pointer to input vector
+   * @param[in]       dim_vec     input vector dimention
+   * @param[out]      p_out       pointer to output vector
+   * @return none.
+   *
+   */
+
+    void      arm_softmax_q7(const q7_t * vec_in, const uint16_t dim_vec, q7_t * p_out);
+
+  /**
+   * @brief Q15 softmax function
+   * @param[in]       vec_in      pointer to input vector
+   * @param[in]       dim_vec     input vector dimention
+   * @param[out]      p_out       pointer to output vector
+   * @return none.
+   *
+   */
+
+    void      arm_softmax_q15(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h b/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h
new file mode 100644
index 0000000..05a239d
--- /dev/null
+++ b/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nnsupportfunctions.h
+ * Description:  Public header file of support functions for CMSIS NN Library
+ *
+ * $Date:        13. July 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ * -------------------------------------------------------------------- */
+
+#ifndef _ARM_NNSUPPORTFUNCTIONS_H_
+#define _ARM_NNSUPPORTFUNCTIONS_H_
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+//#include 
+
+#ifdef __cplusplus
+extern    "C"
+{
+#endif
+
+/**
+ * @brief Union for SIMD access of Q31/Q15/Q7 types
+ */
+union arm_nnword
+{
+    q31_t     word;
+               /**< Q31 type */
+    q15_t     half_words[2];
+               /**< Q15 type */
+    q7_t      bytes[4];
+               /**< Q7 type */
+};
+
+/**
+ * @brief Struct for specifying activation function types
+ *
+ */
+typedef enum
+{
+    ARM_SIGMOID = 0,
+                /**< Sigmoid activation function */
+    ARM_TANH = 1,
+             /**< Tanh activation function */
+} arm_nn_activation_type;
+
+/**
+ * @defgroup nndata_convert Neural Network Data Conversion Functions
+ *
+ * Perform data type conversion in-between neural network operations
+ *
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift 
+ * @param[in]       *pSrc points to the Q7 input vector    
+ * @param[out]      *pDst points to the Q15 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *
+ */
+
+void      arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize);
+
+/**
+ * @brief  Converts the elements of the Q7 vector to reordered Q15 vector without left-shift
+ * @param[in]       *pSrc points to the Q7 input vector    
+ * @param[out]      *pDst points to the Q15 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *
+ */
+
+void      arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize);
+
+#if defined (ARM_MATH_DSP)
+
+/**
+ * @brief read and expand one Q7 word into two Q15 words
+ */
+
+__STATIC_FORCEINLINE void *read_and_pad(void *source, q31_t * out1, q31_t * out2)
+{
+        q31_t     inA = *__SIMD32(source)++;
+        q31_t     inAbuf1 = __SXTB16(__ROR(inA, 8));
+        q31_t     inAbuf2 = __SXTB16(inA);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        *out2 = __PKHTB(inAbuf1, inAbuf2, 16);
+        *out1 = __PKHBT(inAbuf2, inAbuf1, 16);
+#else
+        *out1 = __PKHTB(inAbuf1, inAbuf2, 16);
+        *out2 = __PKHBT(inAbuf2, inAbuf1, 16);
+#endif
+
+        return source;
+}
+
+/**
+ * @brief read and expand one Q7 word into two Q15 words with reordering
+ */
+
+__STATIC_FORCEINLINE void *read_and_pad_reordered(void *source, q31_t * out1, q31_t * out2)
+{
+        q31_t     inA = *__SIMD32(source)++;
+#ifndef ARM_MATH_BIG_ENDIAN
+        *out2 = __SXTB16(__ROR(inA, 8));
+        *out1 = __SXTB16(inA);
+#else
+        *out1 = __SXTB16(__ROR(inA, 8));
+        *out2 = __SXTB16(inA);
+#endif
+
+        return source;
+}
+#endif
+
+/**
+ * @defgroup NNBasicMath Basic Math Functions for Neural Network Computation
+ *
+ * Basic Math Functions for Neural Network Computation
+ *
+ */
+
+/**
+ * @brief           Q7 vector multiplication with variable output shifts
+ * @param[in]       *pSrcA        pointer to the first input vector
+ * @param[in]       *pSrcB        pointer to the second input vector
+ * @param[out]      *pDst         pointer to the output vector
+ * @param[in]       out_shift     amount of right-shift for output
+ * @param[in]       blockSize     number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_nn_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  const uint16_t out_shift,
+  uint32_t blockSize);
+  
+/**
+ * @brief           Q7 vector multiplication with variable output shifts
+ * @param[in]       *pSrcA        pointer to the first input vector
+ * @param[in]       *pSrcB        pointer to the second input vector
+ * @param[out]      *pDst         pointer to the output vector
+ * @param[in]       out_shift     amount of right-shift for output
+ * @param[in]       blockSize     number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_nn_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  const uint16_t out_shift,
+  uint32_t blockSize);
+ 
+/**
+ * @brief defition to adding rouding offset
+ */
+#ifndef ARM_NN_TRUNCATE
+    #define NN_ROUND(out_shift) ( 0x1 << (out_shift - 1) )
+#else
+    #define NN_ROUND(out_shift) 0
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h
new file mode 100644
index 0000000..bf1d6d1
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h
@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_cifar10' 
+ * Target:  'ARMCM0' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM0.h"
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h
new file mode 100644
index 0000000..6993e2a
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h
@@ -0,0 +1,26 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_nn_test' 
+ * Target:  'ARMCM3' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM3.h"
+
+#define RTE_Compiler_IO_STDERR          /* Compiler I/O: STDERR */
+          #define RTE_Compiler_IO_STDERR_ITM      /* Compiler I/O: STDERR ITM */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
+#define RTE_Compiler_IO_TTY             /* Compiler I/O: TTY */
+          #define RTE_Compiler_IO_TTY_ITM         /* Compiler I/O: TTY ITM */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h
new file mode 100644
index 0000000..374579e
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h
@@ -0,0 +1,26 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_nn_test' 
+ * Target:  'ARMCM4_FP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM4_FP.h"
+
+#define RTE_Compiler_IO_STDERR          /* Compiler I/O: STDERR */
+          #define RTE_Compiler_IO_STDERR_ITM      /* Compiler I/O: STDERR ITM */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
+#define RTE_Compiler_IO_TTY             /* Compiler I/O: TTY */
+          #define RTE_Compiler_IO_TTY_ITM         /* Compiler I/O: TTY ITM */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h
new file mode 100644
index 0000000..40dfc78
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h
@@ -0,0 +1,26 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'arm_nnexamples_nn_test' 
+ * Target:  'ARMCM7_SP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM7_SP.h"
+
+#define RTE_Compiler_IO_STDERR          /* Compiler I/O: STDERR */
+          #define RTE_Compiler_IO_STDERR_ITM      /* Compiler I/O: STDERR ITM */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
+#define RTE_Compiler_IO_TTY             /* Compiler I/O: TTY */
+          #define RTE_Compiler_IO_TTY_ITM         /* Compiler I/O: TTY ITM */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c
new file mode 100644
index 0000000..4aa6077
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_convolve_HWC_q15_ref(const q15_t * Im_in,  // input image
+                              const uint16_t dim_im_in, // input image dimention
+                              const uint16_t ch_im_in,  // number of input image channels
+                              const q15_t * wt, // kernel weights 
+                              const uint16_t ch_im_out, // number of filters, i.e., output image channels
+                              const uint16_t dim_kernel,    // filter kernel size
+                              const uint16_t padding,   // padding sizes
+                              const uint16_t stride,    // stride
+                              const q15_t * bias,   // bias
+                              const uint16_t bias_shift, const uint16_t out_shift, q15_t * Im_out,  // output image
+                              const uint16_t dim_im_out,    // output image dimension
+                              q15_t * bufferA,  //buffer space for input
+                              q7_t * bufferB    //buffer space for output
+    )
+{
+    int       i, j, k, l, m, n;
+    int       conv_out;
+    int       in_row, in_col;
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out; j++)
+        {
+            for (k = 0; k < dim_im_out; k++)
+            {
+#ifndef ARM_NN_TRUNCATE
+                conv_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1));
+#else
+                conv_out = bias[i] << bias_shift;
+#endif
+                for (m = 0; m < dim_kernel; m++)
+                {
+                    for (n = 0; n < dim_kernel; n++)
+                    {
+                        in_row = stride * j + m - padding;
+                        in_col = stride * k + n - padding;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] *
+                                    wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16);
+            }
+        }
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c
new file mode 100644
index 0000000..69efcb2
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void
+arm_convolve_HWC_q15_nonsquare_ref(const q15_t * Im_in,
+                          const uint16_t dim_im_in_x,
+                          const uint16_t dim_im_in_y,
+                          const uint16_t ch_im_in,
+                          const q15_t * wt,
+                          const uint16_t ch_im_out,
+                          const uint16_t dim_kernel_x,
+                          const uint16_t dim_kernel_y,
+                          const uint16_t padding_x,
+                          const uint16_t padding_y,
+                          const uint16_t stride_x,
+                          const uint16_t stride_y,
+                          const q15_t * bias,
+                          const uint16_t bias_shift,
+                          const uint16_t out_shift,
+                          q15_t * Im_out,
+                          const uint16_t dim_im_out_x,
+                          const uint16_t dim_im_out_y, 
+                          q15_t * bufferA, 
+                          q7_t * bufferB)
+
+{	
+    uint16_t  i, j, k, l, m, n;
+    int       conv_out;
+    signed char in_row, in_col;
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out_y; j++)
+        {
+            for (k = 0; k < dim_im_out_x; k++)
+            {
+#ifndef ARM_NN_TRUNCATE
+                conv_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1));
+#else
+                conv_out = bias[i] << bias_shift;
+#endif
+                for (m = 0; m < dim_kernel_y; m++)
+                {
+                    for (n = 0; n < dim_kernel_x; n++)
+                    {
+                        in_row = stride_y * j + m - padding_y;
+                        in_col = stride_x * k + n - padding_x;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out +=
+                                    Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in +
+                                          l] * wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x +
+                                                                                            n) * ch_im_in + l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16);
+            }
+        }
+    }
+}	
+
+	
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c
new file mode 100644
index 0000000..aaf25ba
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_convolve_HWC_q7_ref(const q7_t * Im_in,    // input image
+                             const uint16_t dim_im_in,  // input image dimention
+                             const uint16_t ch_im_in,   // number of input image channels
+                             const q7_t * wt,   // kernel weights 
+                             const uint16_t ch_im_out,  // number of filters, i.e., output image channels
+                             const uint16_t dim_kernel, // filter kernel size
+                             const uint16_t padding,    // padding sizes
+                             const uint16_t stride, // stride
+                             const q7_t * bias, // bias
+                             const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out,    // output image
+                             const uint16_t dim_im_out, // output image dimension
+                             q15_t * bufferA,   //buffer space for input
+                             q7_t * bufferB //buffer space for output
+    )
+{
+    int       i, j, k, l, m, n;
+    int       conv_out;
+    int       in_row, in_col;
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out; j++)
+        {
+            for (k = 0; k < dim_im_out; k++)
+            {
+#ifndef ARM_NN_TRUNCATE
+                conv_out = ((q31_t) (bias[i]) << bias_shift) + (0x1 << (out_shift - 1));
+#else
+                conv_out = bias[i] << bias_shift;
+#endif
+                for (m = 0; m < dim_kernel; m++)
+                {
+                    for (n = 0; n < dim_kernel; n++)
+                    {
+                        // if-for implementation
+                        in_row = stride * j + m - padding;
+                        in_col = stride * k + n - padding;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] *
+                                    wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c
new file mode 100644
index 0000000..e731d07
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_convolve_HWC_q7_ref_nonsquare(const q7_t * Im_in,  // input image
+                                       const uint16_t dim_im_in_x,  // input image dimention x
+                                       const uint16_t dim_im_in_y,  // input image dimention y
+                                       const uint16_t ch_im_in, // number of input image channels
+                                       const q7_t * wt, // kernel weights 
+                                       const uint16_t ch_im_out,    // number of filters, i.e., output image channels
+                                       const uint16_t dim_kernel_x, // filter kernel size x
+                                       const uint16_t dim_kernel_y, // filter kernel size y
+                                       const uint16_t padding_x,    // padding sizes x
+                                       const uint16_t padding_y,    // padding sizes y
+                                       const uint16_t stride_x, // stride x
+                                       const uint16_t stride_y, // stride y
+                                       const q7_t * bias,   // bias
+                                       const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out,  // output image
+                                       const uint16_t dim_im_out_x, // output image dimension x
+                                       const uint16_t dim_im_out_y, // output image dimension y
+                                       q15_t * bufferA, //buffer space for input
+                                       q7_t * bufferB   //buffer space for output
+    )
+{
+    int       i, j, k, l, m, n;
+    int       conv_out;
+    int       in_row, in_col;
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out_y; j++)
+        {
+            for (k = 0; k < dim_im_out_x; k++)
+            {
+#ifndef ARM_NN_TRUNCATE
+                conv_out = ((q31_t) (bias[i]) << bias_shift) + (0x1 << (out_shift - 1));
+#else
+                conv_out = bias[i] << bias_shift;
+#endif
+                for (m = 0; m < dim_kernel_y; m++)
+                {
+                    for (n = 0; n < dim_kernel_x; n++)
+                    {
+                        // if-for implementation
+                        in_row = stride_y * j + m - padding_y;
+                        in_col = stride_x * k + n - padding_x;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] *
+                                    wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in +
+                                       l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c
new file mode 100644
index 0000000..970effc
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_depthwise_separable_conv_HWC_q7_ref(const q7_t * Im_in,    // input image
+                                             const uint16_t dim_im_in,  // input image dimention
+                                             const uint16_t ch_im_in,   // number of input image channels
+                                             const q7_t * wt,   // kernel weights 
+                                             const uint16_t ch_im_out,  // number of filters, i.e., output image channels
+                                             const uint16_t dim_kernel, // filter kernel size
+                                             const uint16_t padding,    // padding sizes
+                                             const uint16_t stride, // stride
+                                             const q7_t * bias, // bias
+                                             const uint16_t bias_shift, // amount of left-shift for bias
+                                             const uint16_t out_shift,  // amount of right-shift for output
+                                             q7_t * Im_out, // output image
+                                             const uint16_t dim_im_out, // output image dimension
+                                             q15_t * bufferA,   //buffer space for input
+                                             q7_t * bufferB //buffer space for output
+    )
+{
+    int       i_out_y, i_out_x, i_ch_out;
+    int       i_ker_y, i_ker_x;
+    for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
+        {
+            for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++)
+            {
+                // for each output
+#ifndef ARM_NN_TRUNCATE
+                int       conv_out = (bias[i_ch_out] << bias_shift) + (0x1 << (out_shift - 1));
+#else
+                int       conv_out = bias[i_ch_out] << bias_shift;
+#endif
+                for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++)
+                {
+                    for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++)
+                    {
+                        int       in_row = stride * i_out_y + i_ker_y - padding;
+                        int       in_col = stride * i_out_x + i_ker_x - padding;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
+                        {
+                            conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + i_ch_out] *
+                                wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out];
+                        }
+                    }
+                }
+                Im_out[(i_out_y * dim_im_out + i_out_x) * ch_im_out + i_ch_out] =
+                    (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c
new file mode 100644
index 0000000..8fa4147
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(const q7_t * Im_in,  // input image
+                                                       const uint16_t dim_im_in_x,  // input image dimention x
+                                                       const uint16_t dim_im_in_y,  // input image dimention y
+                                                       const uint16_t ch_im_in, // number of input image channels
+                                                       const q7_t * wt, // kernel weights 
+                                                       const uint16_t ch_im_out,    // number of filters, i.e., output image channels
+                                                       const uint16_t dim_kernel_x, // filter kernel size x
+                                                       const uint16_t dim_kernel_y, // filter kernel size y
+                                                       const uint16_t padding_x,    // padding sizes x
+                                                       const uint16_t padding_y,    // padding sizes y
+                                                       const uint16_t stride_x, // stride x
+                                                       const uint16_t stride_y, // stride y
+                                                       const q7_t * bias,   // bias
+                                                       const uint16_t bias_shift,   // amount of left-shift for bias
+                                                       const uint16_t out_shift,    // amount of right-shift for output
+                                                       q7_t * Im_out,   // output image
+                                                       const uint16_t dim_im_out_x, // output image dimension x
+                                                       const uint16_t dim_im_out_y, // output image dimension y
+                                                       q15_t * bufferA, //buffer space for input
+                                                       q7_t * bufferB   //buffer space for output
+    )
+{
+    int       i_out_y, i_out_x, i_ch_out;
+    int       i_ker_y, i_ker_x;
+    for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
+        {
+            for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++)
+            {
+                // for each output
+#ifndef ARM_NN_TRUNCATE
+                int       conv_out = (bias[i_ch_out] << bias_shift) + (0x1 << (out_shift - 1));
+#else
+                int       conv_out = bias[i_ch_out] << bias_shift;
+#endif
+                for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++)
+                {
+                    for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++)
+                    {
+                        int       in_row = stride_y * i_out_y + i_ker_y - padding_y;
+                        int       in_col = stride_x * i_out_x + i_ker_x - padding_x;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
+                        {
+                            conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] *
+                                wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out];
+                        }
+                    }
+                }
+                Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] =
+                    (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c
new file mode 100644
index 0000000..6fe5e2b
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_fully_connected_mat_q7_vec_q15_opt_ref(const q15_t * pV,   // pointer to vector
+                                                const q7_t * pM,    // pointer to matrix
+                                                const uint16_t dim_vec, // length of the vector
+                                                const uint16_t num_of_rows, // numCol of A
+                                                const uint16_t bias_shift,  // amount of left-shift for bias
+                                                const uint16_t out_shift,   // amount of right-shift for output
+                                                const q7_t * bias, q15_t * pOut,    // output operand
+                                                q15_t * vec_buffer)
+{
+
+    uint16_t  rowCnt = num_of_rows >> 2;
+    const q7_t *pB = pM;
+    const q15_t *pA;
+    q15_t    *pO = pOut;
+    const q7_t *pBias = bias;
+
+    while (rowCnt)
+    {
+        pA = pV;
+#ifndef ARM_NN_TRUNCATE
+        q31_t     sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+        q31_t     sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+        q31_t     sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+        q31_t     sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+#else
+        q31_t     sum = *pBias++ << bias_shift;
+        q31_t     sum2 = *pBias++ << bias_shift;
+        q31_t     sum3 = *pBias++ << bias_shift;
+        q31_t     sum4 = *pBias++ << bias_shift;
+#endif
+
+        uint16_t  colCnt = dim_vec >> 1;
+
+        while (colCnt)
+        {
+            q15_t     inA1 = *pA++;
+            q15_t     inA2 = *pA++;
+
+            q7_t      inB1 = *pB++;
+            q7_t      inB3 = *pB++;
+            q7_t      inB2 = *pB++;
+            q7_t      inB4 = *pB++;
+
+            sum += inA1 * inB1 + inA2 * inB2;
+            sum2 += inA1 * inB3 + inA2 * inB4;
+
+            inB1 = *pB++;
+            inB3 = *pB++;
+            inB2 = *pB++;
+            inB4 = *pB++;
+
+            sum3 += inA1 * inB1 + inA2 * inB2;
+            sum4 += inA1 * inB3 + inA2 * inB4;
+
+            colCnt--;
+        }
+        colCnt = dim_vec & 0x1;
+        while (colCnt)
+        {
+            q15_t     inA = *pA++;
+            q7_t      inB = *pB++;
+            sum += inA * inB;
+            inB = *pB++;
+            sum2 += inA * inB;
+            inB = *pB++;
+            sum3 += inA * inB;
+            inB = *pB++;
+            sum4 += inA * inB;
+
+            colCnt--;
+        }
+        *pO++ = (q15_t) __SSAT((sum >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16);
+
+        rowCnt--;
+    }
+
+    rowCnt = num_of_rows & 0x3;
+
+    while (rowCnt)
+    {
+        pA = pV;
+#ifndef ARM_NN_TRUNCATE
+        int       ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+#else
+        int       ip_out = *pBias++ << bias_shift;
+#endif
+        for (int j = 0; j < dim_vec; j++)
+        {
+            q15_t     inA = *pA++;
+            q7_t      inB = *pB++;
+            ip_out += inA * inB;
+        }
+        *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16);
+
+        rowCnt--;
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c
new file mode 100644
index 0000000..6a4d385
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_fully_connected_mat_q7_vec_q15_ref(const q15_t * pV,   // pointer to vector
+                                            const q7_t * pM,    // pointer to matrix
+                                            const uint16_t dim_vec, // length of the vector
+                                            const uint16_t num_of_rows, // numCol of A
+                                            const uint16_t bias_shift,  // amount of left-shift for bias
+                                            const uint16_t out_shift,   // amount of right-shift for output
+                                            const q7_t * bias, q15_t * pOut,    // output operand
+                                            q15_t * vec_buffer)
+{
+    for (int i = 0; i < num_of_rows; i++)
+    {
+#ifndef ARM_NN_TRUNCATE
+        int       ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1));
+#else
+        int       ip_out = bias[i] << bias_shift;
+#endif
+        for (int j = 0; j < dim_vec; j++)
+        {
+            ip_out += pV[j] * pM[i * dim_vec + j];
+        }
+        pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16);
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c
new file mode 100644
index 0000000..475c757
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_fully_connected_q15_opt_ref(const q15_t * pV,  // pointer to vector
+                                     const q15_t * pM,  // pointer to matrix
+                                     const uint16_t dim_vec,    // length of the vector
+                                     const uint16_t num_of_rows,    // numCol of A
+                                     const uint16_t bias_shift, // amount of left-shift for bias
+                                     const uint16_t out_shift,  // amount of right-shift for output
+                                     const q15_t * bias, q15_t * pOut,  // output operand
+                                     q15_t * vec_buffer)
+{
+
+    uint16_t  rowCnt = num_of_rows >> 2;
+    const q15_t *pB = pM;
+    const q15_t *pA;
+    q15_t    *pO = pOut;
+    const q15_t *pBias = bias;
+
+    while (rowCnt)
+    {
+        pA = pV;
+#ifndef ARM_NN_TRUNCATE
+        q31_t     sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+        q31_t     sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+        q31_t     sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+        q31_t     sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+#else
+        q31_t     sum = *pBias++ << bias_shift;
+        q31_t     sum2 = *pBias++ << bias_shift;
+        q31_t     sum3 = *pBias++ << bias_shift;
+        q31_t     sum4 = *pBias++ << bias_shift;
+#endif
+
+        uint16_t  colCnt = dim_vec >> 1;
+
+        while (colCnt)
+        {
+            q15_t     inA1 = *pA++;
+            q15_t     inA2 = *pA++;
+
+            q15_t     inB1 = *pB++;
+            q15_t     inB2 = *pB++;
+            sum += inA1 * inB1 + inA2 * inB2;
+
+            inB1 = *pB++;
+            inB2 = *pB++;
+            sum2 += inA1 * inB1 + inA2 * inB2;
+
+            inB1 = *pB++;
+            inB2 = *pB++;
+            sum3 += inA1 * inB1 + inA2 * inB2;
+
+            inB1 = *pB++;
+            inB2 = *pB++;
+            sum4 += inA1 * inB1 + inA2 * inB2;
+
+            colCnt--;
+        }
+        colCnt = dim_vec & 0x1;
+        while (colCnt)
+        {
+            q15_t     inA = *pA++;
+            q15_t     inB = *pB++;
+            sum += inA * inB;
+            inB = *pB++;
+            sum2 += inA * inB;
+            inB = *pB++;
+            sum3 += inA * inB;
+            inB = *pB++;
+            sum4 += inA * inB;
+            colCnt--;
+        }
+        *pO++ = (q15_t) __SSAT((sum >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16);
+
+        rowCnt--;
+    }
+
+    rowCnt = num_of_rows & 0x3;
+
+    while (rowCnt)
+    {
+        pA = pV;
+#ifndef ARM_NN_TRUNCATE
+        int       ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+#else
+        int       ip_out = *pBias++ << bias_shift;
+#endif
+        for (int j = 0; j < dim_vec; j++)
+        {
+            q15_t     inA = *pA++;
+            q15_t     inB = *pB++;
+            ip_out += inA * inB;
+        }
+        *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16);
+
+        rowCnt--;
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c
new file mode 100644
index 0000000..3fd0bc0
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_fully_connected_q15_ref(const q15_t * pV,  // pointer to vector
+                                 const q15_t * pM,  // pointer to matrix
+                                 const uint16_t dim_vec,    // length of the vector
+                                 const uint16_t num_of_rows,    // numCol of A
+                                 const uint16_t bias_shift, // amount of left-shift for bias
+                                 const uint16_t out_shift,  // amount of right-shift for output
+                                 const q15_t * bias, q15_t * pOut,  // output operand
+                                 q15_t * vec_buffer)
+{
+    for (int i = 0; i < num_of_rows; i++)
+    {
+#ifndef ARM_NN_TRUNCATE
+        int       ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1));
+#else
+        int       ip_out = bias[i] << bias_shift;
+#endif
+        for (int j = 0; j < dim_vec; j++)
+        {
+            ip_out += pV[j] * pM[i * dim_vec + j];
+        }
+        pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16);
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c
new file mode 100644
index 0000000..cee8faa
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_fully_connected_q7_opt_ref(const q7_t * pV,    // pointer to vector
+                                    const q7_t * pM,    // pointer to matrix
+                                    const uint16_t dim_vec, // length of the vector
+                                    const uint16_t num_of_rows, // numCol of A
+                                    const uint16_t bias_shift,  // amount of left-shift for bias
+                                    const uint16_t out_shift,   // amount of right-shift for output
+                                    const q7_t * bias, q7_t * pOut, // output operand
+                                    q15_t * vec_buffer)
+{
+
+    uint16_t  rowCnt = num_of_rows >> 2;
+    const q7_t *pB = pM;
+    const q7_t *pA;
+    q7_t     *pO = pOut;
+    const q7_t *pBias = bias;
+
+    while (rowCnt)
+    {
+        pA = pV;
+#ifndef ARM_NN_TRUNCATE
+        q31_t     sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+        q31_t     sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+        q31_t     sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+        q31_t     sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+#else
+        q31_t     sum = *pBias++ << bias_shift;
+        q31_t     sum2 = *pBias++ << bias_shift;
+        q31_t     sum3 = *pBias++ << bias_shift;
+        q31_t     sum4 = *pBias++ << bias_shift;
+#endif
+
+        uint16_t  colCnt = dim_vec >> 2;
+
+        while (colCnt)
+        {
+            q7_t      inA1 = *pA++;
+            q7_t      inA3 = *pA++;
+            q7_t      inA2 = *pA++;
+            q7_t      inA4 = *pA++;
+
+            q7_t      inB1 = *pB++;
+            q7_t      inB3 = *pB++;
+            q7_t      inB2 = *pB++;
+            q7_t      inB4 = *pB++;
+
+            sum += inA1 * inB1 + inA2 * inB2;
+            sum2 += inA1 * inB3 + inA2 * inB4;
+
+            inB1 = *pB++;
+            inB3 = *pB++;
+            inB2 = *pB++;
+            inB4 = *pB++;
+
+            sum3 += inA1 * inB1 + inA2 * inB2;
+            sum4 += inA1 * inB3 + inA2 * inB4;
+
+            inB1 = *pB++;
+            inB3 = *pB++;
+            inB2 = *pB++;
+            inB4 = *pB++;
+
+            sum += inA3 * inB1 + inA4 * inB2;
+            sum2 += inA3 * inB3 + inA4 * inB4;
+
+            inB1 = *pB++;
+            inB3 = *pB++;
+            inB2 = *pB++;
+            inB4 = *pB++;
+
+            sum3 += inA3 * inB1 + inA4 * inB2;
+            sum4 += inA3 * inB3 + inA4 * inB4;
+
+            colCnt--;
+        }
+        colCnt = dim_vec & 0x3;
+        while (colCnt)
+        {
+            q7_t      inA = *pA++;
+            q7_t      inB = *pB++;
+            sum += inA * inB;
+            inB = *pB++;
+            sum2 += inA * inB;
+            inB = *pB++;
+            sum3 += inA * inB;
+            inB = *pB++;
+            sum4 += inA * inB;
+
+            colCnt--;
+        }
+        *pO++ = (q7_t) __SSAT((sum >> out_shift), 8);
+        *pO++ = (q7_t) __SSAT((sum2 >> out_shift), 8);
+        *pO++ = (q7_t) __SSAT((sum3 >> out_shift), 8);
+        *pO++ = (q7_t) __SSAT((sum4 >> out_shift), 8);
+
+        rowCnt--;
+    }
+
+    rowCnt = num_of_rows & 0x3;
+
+    while (rowCnt)
+    {
+        pA = pV;
+#ifndef ARM_NN_TRUNCATE
+        int       ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1));
+#else
+        int       ip_out = *pBias++ << bias_shift;
+#endif
+        for (int j = 0; j < dim_vec; j++)
+        {
+            q7_t      inA = *pA++;
+            q7_t      inB = *pB++;
+            ip_out += inA * inB;
+        }
+        *pO++ = (q7_t) __SSAT((ip_out >> out_shift), 8);
+
+        rowCnt--;
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c
new file mode 100644
index 0000000..78c891c
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_fully_connected_q7_ref(const q7_t * pV,    // pointer to vector
+                                const q7_t * pM,    // pointer to matrix
+                                const uint16_t dim_vec, // length of the vector
+                                const uint16_t num_of_rows, // numCol of A
+                                const uint16_t bias_shift,  // amount of left-shift for bias
+                                const uint16_t out_shift,   // amount of right-shift for output
+                                const q7_t * bias, q7_t * pOut, // output operand
+                                q15_t * vec_buffer)
+{
+    for (int i = 0; i < num_of_rows; i++)
+    {
+#ifndef ARM_NN_TRUNCATE
+        int       ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1));
+#else
+        int       ip_out = bias[i] << bias_shift;
+#endif
+        for (int j = 0; j < dim_vec; j++)
+        {
+            ip_out += pV[j] * pM[i * dim_vec + j];
+        }
+        pOut[i] = (q7_t) __SSAT((ip_out >> out_shift), 8);
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c
new file mode 100644
index 0000000..e78850f
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+void      arm_nn_mult_q7_ref(q7_t * pSrcA, 
+                             q7_t * pSrcB, 
+                             q7_t * pDst, 
+                             const uint16_t out_shift, 
+                             uint32_t blockSize) {
+    uint16_t  i;
+
+for (i = 0; i < blockSize; i++)
+    {
+		q31_t product = pSrcA[i] * pSrcB[i];
+#ifndef ARM_NN_TRUNCATE
+        pDst[i] = (q7_t)__SSAT((product + (0x1 << (out_shift - 1)))>>out_shift, 8);
+#else
+        pDst[i] = (q7_t)__SSAT(product >> out_shift, 8);
+#endif
+    }
+}
+
+void     arm_nn_mult_q15_ref(q15_t * pSrcA, 
+                             q15_t * pSrcB, 
+                             q15_t * pDst, 
+                             const uint16_t out_shift, 
+                             uint32_t blockSize) {
+    uint16_t  i;
+
+for (i = 0; i < blockSize; i++)
+    {
+		q31_t product = pSrcA[i] * pSrcB[i];
+#ifndef ARM_NN_TRUNCATE
+        pDst[i] = (q15_t)__SSAT((product + (0x1 << (out_shift - 1)))>>out_shift, 16);
+#else
+        pDst[i] = (q15_t)__SSAT(product >> out_shift, 16);
+#endif
+
+
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c
new file mode 100644
index 0000000..b75a0a2
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ref_functions.h"
+
+void arm_avepool_q7_HWC_ref(const q7_t * Im_in, // input image
+                            const uint16_t dim_im_in,   // input image dimension
+                            const uint16_t ch_im_in,    // number of input image channels
+                            const uint16_t dim_kernel,  // window kernel size
+                            const uint16_t padding, // padding sizes
+                            const uint16_t stride,  // stride
+                            const uint16_t dim_im_out,  // output image dimension
+                            q7_t * bufferA, // a buffer for local storage
+                            q7_t * Im_out)
+{
+    int16_t   i_ch_in, i_x, i_y;
+    int16_t   k_x, k_y;
+
+    for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++)
+    {
+        for (i_y = 0; i_y < dim_im_out; i_y++)
+        {
+            for (i_x = 0; i_x < dim_im_out; i_x++)
+            {
+                int       sum = 0;
+                int       count = 0;
+                for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++)
+                {
+                    for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++)
+                    {
+                        if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in)
+                        {
+                            sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)];
+                            count++;
+                        }
+                    }
+                }
+                Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count;
+            }
+        }
+    }
+}
+
+void arm_maxpool_q7_HWC_ref(const q7_t * Im_in, // input image
+                            const uint16_t dim_im_in,   // input image dimension
+                            const uint16_t ch_im_in,    // number of input image channels
+                            const uint16_t dim_kernel,  // window kernel size
+                            const uint16_t padding, // padding sizes
+                            const uint16_t stride,  // stride
+                            const uint16_t dim_im_out,  // output image dimension
+                            q7_t * bufferA, // a buffer for local storage
+                            q7_t * Im_out)
+{
+    int16_t   i_ch_in, i_x, i_y;
+    int16_t   k_x, k_y;
+
+    for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++)
+    {
+        for (i_y = 0; i_y < dim_im_out; i_y++)
+        {
+            for (i_x = 0; i_x < dim_im_out; i_x++)
+            {
+                int       max = -129;
+                for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++)
+                {
+                    for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++)
+                    {
+                        if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in)
+                        {
+                            if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max)
+                            {
+                                max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)];
+                            }
+                        }
+                    }
+                }
+                Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max;
+            }
+        }
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c
new file mode 100644
index 0000000..9397ef1
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+void arm_relu_q7_ref(q7_t * data, uint16_t size)
+{
+    uint16_t  i;
+
+    for (i = 0; i < size; i++)
+    {
+        if (data[i] < 0)
+            data[i] = 0;
+    }
+}
+
+void arm_relu_q15_ref(q15_t * data, uint16_t size)
+{
+    uint16_t  i;
+
+    for (i = 0; i < size; i++)
+    {
+        if (data[i] < 0)
+            data[i] = 0;
+    }
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h
new file mode 100644
index 0000000..31cdcb0
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h
@@ -0,0 +1,7 @@
+#define IP2_WEIGHT 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+
+#define IP4_WEIGHT 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+
+#define IP4_q7_q15_WEIGHT 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+
+#define IP4_WEIGHT_Q15 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diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h
new file mode 100644
index 0000000..5a25ffa
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _REF_FUNCTIONS_H_
+#define _REF_FUNCTIONS_H_
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+//#include "arm_nnsupportfunctions.h"
+#include "fully_connected_testing_weights.h"
+
+#ifdef __cplusplus
+extern    "C"
+{
+#endif
+
+/*
+ *
+ * Convolution reference implemenation
+ *
+ */
+
+    void      arm_convolve_HWC_q7_ref(const q7_t * Im_in,   // input image
+                                      const uint16_t dim_im_in, // input image dimention
+                                      const uint16_t ch_im_in,  // number of input image channels
+                                      const q7_t * wt,  // kernel weights 
+                                      const uint16_t ch_im_out, // number of filters, i.e., output image channels
+                                      const uint16_t dim_kernel,    // filter kernel size
+                                      const uint16_t padding,   // padding sizes
+                                      const uint16_t stride,    // stride
+                                      const q7_t * bias,    // bias
+                                      const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out,   // output image
+                                      const uint16_t dim_im_out,    // output image dimension
+                                      q15_t * bufferA,  //buffer space for input
+                                      q7_t * bufferB    //buffer space for output
+        );
+
+    void      arm_convolve_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image
+                                                const uint16_t dim_im_in_x, // input image dimention x
+                                                const uint16_t dim_im_in_y, // input image dimention y
+                                                const uint16_t ch_im_in,    // number of input image channels
+                                                const q7_t * wt,    // kernel weights 
+                                                const uint16_t ch_im_out,   // number of filters, i.e., output image channels
+                                                const uint16_t dim_kernel_x,    // filter kernel size x
+                                                const uint16_t dim_kernel_y,    // filter kernel size y
+                                                const uint16_t padding_x,   // padding sizes x
+                                                const uint16_t padding_y,   // padding sizes y
+                                                const uint16_t stride_x,    // stride x
+                                                const uint16_t stride_y,    // stride y
+                                                const q7_t * bias,  // bias
+                                                const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image
+                                                const uint16_t dim_im_out_x,    // output image dimension x
+                                                const uint16_t dim_im_out_y,    // output image dimension y
+                                                q15_t * bufferA,    //buffer space for input
+                                                q7_t * bufferB  //buffer space for output
+        );
+
+    void      arm_convolve_HWC_q15_ref(const q15_t * Im_in, // input image
+                                       const uint16_t dim_im_in,    // input image dimention
+                                       const uint16_t ch_im_in, // number of input image channels
+                                       const q15_t * wt,    // kernel weights 
+                                       const uint16_t ch_im_out,    // number of filters, i.e., output image channels
+                                       const uint16_t dim_kernel,   // filter kernel size
+                                       const uint16_t padding,  // padding sizes
+                                       const uint16_t stride,   // stride
+                                       const q15_t * bias,  // bias
+                                       const uint16_t bias_shift, const uint16_t out_shift, q15_t * Im_out, // output image
+                                       const uint16_t dim_im_out,   // output image dimension
+                                       q15_t * bufferA, //buffer space for input
+                                       q7_t * bufferB   //buffer space for output
+        );
+    void      arm_convolve_HWC_q15_nonsquare_ref(const q15_t * Im_in,
+                                                      const uint16_t dim_im_in_x,
+                                                      const uint16_t dim_im_in_y,
+                                                      const uint16_t ch_im_in,
+                                                      const q15_t * wt,
+                                                      const uint16_t ch_im_out,
+                                                      const uint16_t dim_kernel_x,
+                                                      const uint16_t dim_kernel_y,
+                                                      const uint16_t padding_x,
+                                                      const uint16_t padding_y,
+                                                      const uint16_t stride_x,
+                                                      const uint16_t stride_y,
+                                                      const q15_t * bias,
+                                                      const uint16_t bias_shift,
+                                                      const uint16_t out_shift,
+                                                      q15_t * Im_out,
+                                                      const uint16_t dim_im_out_x,
+                                                      const uint16_t dim_im_out_y, 
+                                                      q15_t * bufferA, 
+                                                      q7_t * bufferB);
+													  
+    void      arm_depthwise_separable_conv_HWC_q7_ref(const q7_t * Im_in,   // input image
+                                                      const uint16_t dim_im_in, // input image dimention
+                                                      const uint16_t ch_im_in,  // number of input image channels
+                                                      const q7_t * wt,  // kernel weights 
+                                                      const uint16_t ch_im_out, // number of filters, i.e., output image channels
+                                                      const uint16_t dim_kernel,    // filter kernel size
+                                                      const uint16_t padding,   // padding sizes
+                                                      const uint16_t stride,    // stride
+                                                      const q7_t * bias,    // bias
+                                                      const uint16_t bias_shift,    // amount of left-shift for bias
+                                                      const uint16_t out_shift, // amount of right-shift for output
+                                                      q7_t * Im_out,    // output image
+                                                      const uint16_t dim_im_out,    // output image dimension
+                                                      q15_t * bufferA,  //buffer space for input
+                                                      q7_t * bufferB    //buffer space for output
+        );
+    void      arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image
+                                                                const uint16_t dim_im_in_x, // input image dimention x
+                                                                const uint16_t dim_im_in_y, // input image dimention y
+                                                                const uint16_t ch_im_in,    // number of input image channels
+                                                                const q7_t * wt,    // kernel weights 
+                                                                const uint16_t ch_im_out,   // number of filters, i.e., output image channels
+                                                                const uint16_t dim_kernel_x,    // filter kernel size x
+                                                                const uint16_t dim_kernel_y,    // filter kernel size y
+                                                                const uint16_t padding_x,   // padding sizes x
+                                                                const uint16_t padding_y,   // padding sizes y
+                                                                const uint16_t stride_x,    // stride x
+                                                                const uint16_t stride_y,    // stride y
+                                                                const q7_t * bias,  // bias
+                                                                const uint16_t bias_shift,  // amount of left-shift for bias
+                                                                const uint16_t out_shift,   // amount of right-shift for output
+                                                                q7_t * Im_out,  // output image
+                                                                const uint16_t dim_im_out_x,    // output image dimension x
+                                                                const uint16_t dim_im_out_y,    // output image dimension y
+                                                                q15_t * bufferA,    //buffer space for input
+                                                                q7_t * bufferB  //buffer space for output
+        );
+
+/*
+ *
+ * Fully-connected reference implemenation
+ *
+ */
+
+    void      arm_fully_connected_q7_ref(const q7_t * pV,   // pointer to vector
+                                         const q7_t * pM,   // pointer to matrix
+                                         const uint16_t dim_vec,    // length of the vector
+                                         const uint16_t num_of_rows,    // numCol of A
+                                         const uint16_t bias_shift, // amount of left-shift for bias
+                                         const uint16_t out_shift,  // amount of right-shift for output
+                                         const q7_t * bias, q7_t * pOut,    // output operand
+                                         q15_t * vec_buffer);
+
+    void      arm_fully_connected_q15_ref(const q15_t * pV, // pointer to vector
+                                          const q15_t * pM, // pointer to matrix
+                                          const uint16_t dim_vec,   // length of the vector
+                                          const uint16_t num_of_rows,   // numCol of A
+                                          const uint16_t bias_shift,    // amount of left-shift for bias
+                                          const uint16_t out_shift, // amount of right-shift for output
+                                          const q15_t * bias, q15_t * pOut, // output operand
+                                          q15_t * vec_buffer);
+
+    void      arm_fully_connected_mat_q7_vec_q15_ref(const q15_t * pV,  // pointer to vector
+                                                     const q7_t * pM,   // pointer to matrix
+                                                     const uint16_t dim_vec,    // length of the vector
+                                                     const uint16_t num_of_rows,    // numCol of A
+                                                     const uint16_t bias_shift, // amount of left-shift for bias
+                                                     const uint16_t out_shift,  // amount of right-shift for output
+                                                     const q7_t * bias, q15_t * pOut,   // output operand
+                                                     q15_t * vec_buffer);
+
+    void      arm_fully_connected_q7_opt_ref(const q7_t * pV,   // pointer to vector
+                                             const q7_t * pM,   // pointer to matrix
+                                             const uint16_t dim_vec,    // length of the vector
+                                             const uint16_t num_of_rows,    // numCol of A
+                                             const uint16_t bias_shift, // amount of left-shift for bias
+                                             const uint16_t out_shift,  // amount of right-shift for output
+                                             const q7_t * bias, q7_t * pOut,    // output operand
+                                             q15_t * vec_buffer);
+
+    void      arm_fully_connected_q15_opt_ref(const q15_t * pV, // pointer to vector
+                                              const q15_t * pM, // pointer to matrix
+                                              const uint16_t dim_vec,   // length of the vector
+                                              const uint16_t num_of_rows,   // numCol of A
+                                              const uint16_t bias_shift,    // amount of left-shift for bias
+                                              const uint16_t out_shift, // amount of right-shift for output
+                                              const q15_t * bias, q15_t * pOut, // output operand
+                                              q15_t * vec_buffer);
+
+    void      arm_fully_connected_mat_q7_vec_q15_opt_ref(const q15_t * pV,  // pointer to vector
+                                                         const q7_t * pM,   // pointer to matrix
+                                                         const uint16_t dim_vec,    // length of the vector
+                                                         const uint16_t num_of_rows,    // numCol of A
+                                                         const uint16_t bias_shift, // amount of left-shift for bias
+                                                         const uint16_t out_shift,  // amount of right-shift for output
+                                                         const q7_t * bias, q15_t * pOut,   // output operand
+                                                         q15_t * vec_buffer);
+
+/*
+ *
+ * Pooling reference implemenation
+ *
+ */
+
+    void      arm_avepool_q7_HWC_ref(const q7_t * Im_in,    // input image
+                                     const uint16_t dim_im_in,  // input image dimension
+                                     const uint16_t ch_im_in,   // number of input image channels
+                                     const uint16_t dim_kernel, // window kernel size
+                                     const uint16_t padding,    // padding sizes
+                                     const uint16_t stride, // stride
+                                     const uint16_t dim_im_out, // output image dimension
+                                     q7_t * bufferA,    // a buffer for local storage
+                                     q7_t * Im_out);
+
+    void      arm_maxpool_q7_HWC_ref(const q7_t * Im_in,    // input image
+                                     const uint16_t dim_im_in,  // input image dimension
+                                     const uint16_t ch_im_in,   // number of input image channels
+                                     const uint16_t dim_kernel, // window kernel size
+                                     const uint16_t padding,    // padding sizes
+                                     const uint16_t stride, // stride
+                                     const uint16_t dim_im_out, // output image dimension
+                                     q7_t * bufferA,    // a buffer for local storage
+                                     q7_t * Im_out);
+
+/*
+ *
+ * Other reference implemenation
+ *
+ */
+
+    void      arm_relu_q7_ref(q7_t * data, uint16_t size);
+
+    void      arm_relu_q15_ref(q15_t * data, uint16_t size);
+
+    void      arm_nn_mult_q7_ref(q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, const uint16_t out_shift, uint32_t blockSize);
+
+    void      arm_nn_mult_q15_ref(q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, const uint16_t out_shift, uint32_t blockSize);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp
new file mode 100644
index 0000000..41088fe
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp
@@ -0,0 +1,801 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2018 Arm Limited. All rights reserved.
+*
+*
+* Project:       CMSIS NN Library
+* Title:         arm_nnexamples_nn_test.cpp
+*
+* Description:   Example code for NN kernel testing.
+*
+* Target Processor: Cortex-M cores
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_nnexamples_nn_test.h"
+
+//#define TEST_SIGMOID
+//#define TEST_TANH
+#define TEST_POOL
+#define TEST_RELU
+#define TEST_IP
+#define TEST_CONV
+#define TEST_NONSQUARE
+#define TEST_NNMULT
+
+int test_index = 0;
+q7_t test_flags[50];
+bool test_pass;
+
+int main()
+{
+    printf("start tests\n");
+
+    srand(1);
+
+    // common pointers for testing data
+    q7_t     *test1;
+    q15_t    *test2;
+    q7_t     *test3;
+    q15_t    *test4;
+
+    for (test_index = 0; test_index<50; test_index++) {
+        test_flags[test_index] = -1;
+    }
+    test_index = 0;
+
+#ifdef TEST_NNMULT
+#define NNMULT_DIM 128
+    test1 = new q7_t[NNMULT_DIM*2];
+    test2 = new q15_t[NNMULT_DIM*2];
+    test3 = new q7_t[NNMULT_DIM*2];
+    test4 = new q15_t[NNMULT_DIM*2];
+
+    q7_t * mult_out_q7 = test3;
+    q7_t * mult_ref_q7 = test3 + NNMULT_DIM;
+    q15_t * mult_out_q15 = test4;
+    q15_t * mult_ref_q15 = test4 + NNMULT_DIM;
+
+    for (int i=0;i= 2 || pool_out_opt[i] - pool_out_ref[i] >= 2)
+        {
+            printf("Output mismatch at %d, expected %d, actual %d\n", i, pool_out_ref[i], pool_out_opt[i]);
+            if_ave_pool_match = false;
+        }
+    }
+    if (if_ave_pool_match == true)
+    {
+        printf("Outputs match.\n");
+    }
+
+    delete[]test1;
+    delete[]test2;
+    delete[]test3;
+
+#endif
+
+#ifdef TEST_RELU
+
+#define RELU_DIM 127
+
+    test1 = new q7_t[RELU_DIM];
+    test2 = new q15_t[RELU_DIM];
+    test3 = new q7_t[RELU_DIM];
+    test4 = new q15_t[RELU_DIM];
+
+    for (int i = 0; i < RELU_DIM; i++)
+    {
+        test1[i] = (rand() % 256 - 128);
+        test2[i] = (rand() % 65536 - 32768);
+        test3[i] = test1[i];
+        test4[i] = test2[i];
+    }
+
+    q7_t     *relu_ref_data_q7 = test1;
+    q7_t     *relu_opt_data_q7 = test3;
+    q15_t    *relu_ref_data_q15 = test2;
+    q15_t    *relu_opt_data_q15 = test4;
+
+    printf("Start ref relu q7 implementation\n");
+
+    arm_relu_q7_ref(relu_ref_data_q7, RELU_DIM);
+
+    printf("Start opt relu q7 implementation\n");
+
+    arm_relu_q7(relu_opt_data_q7, RELU_DIM);
+
+    verify_results_q7(relu_ref_data_q7, relu_opt_data_q7, RELU_DIM);
+
+    printf("Start ref relu q15 implementation\n");
+
+    arm_relu_q15_ref(relu_ref_data_q15, RELU_DIM);
+
+    printf("Start opt relu q15 implementation\n");
+
+    arm_relu_q15(relu_opt_data_q15, RELU_DIM);
+
+    verify_results_q15(relu_ref_data_q15, relu_opt_data_q15, RELU_DIM);
+
+    delete[]test1;
+    delete[]test2;
+    delete[]test3;
+    delete[]test4;
+
+#endif
+
+#ifdef TEST_IP
+
+#define IP_ROW_DIM 127
+#define IP_COL_DIM 127
+
+    q7_t      ip_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT;
+    q7_t      ip_q7_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT;
+    q7_t      ip_q7_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_q7_q15_WEIGHT;
+    q15_t     ip_q15_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT;
+    q15_t     ip_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT_Q15;
+
+    test1 = new q7_t[IP_COL_DIM + IP_ROW_DIM];
+    test2 = new q15_t[IP_COL_DIM];
+    test3 = new q7_t[IP_ROW_DIM * 3];
+    test4 = new q15_t[IP_COL_DIM + IP_ROW_DIM * 2];
+
+    for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++)
+    {
+        test1[i] = rand() % 256 - 100;
+    }
+    for (int i = 0; i < IP_ROW_DIM * 3; i++)
+    {
+        test3[i] = 0;
+    }
+
+    q7_t     *ip_bias_q7 = test1 + IP_COL_DIM;
+
+    q7_t     *ip_out_q7_ref = test3;
+    q7_t     *ip_out_q7_opt = test3 + IP_ROW_DIM;
+    q7_t     *ip_out_q7_opt_fast = test3 + 2 * IP_ROW_DIM;
+    q15_t    *ip_out_q15_ref = test4 + IP_COL_DIM;
+    q15_t    *ip_out_q15_opt = test4 + IP_COL_DIM + IP_ROW_DIM;
+
+    initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM);
+    initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM);
+    initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM);
+
+    printf("Start ref q7 implementation\n");
+
+    arm_fully_connected_q7_ref(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_ref, test2);
+
+    printf("Start q7 implementation\n");
+
+    arm_fully_connected_q7(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt, test2);
+
+    verify_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM);
+
+    printf("Start q7 ref opt implementation\n");
+
+    arm_fully_connected_q7_opt_ref(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7,
+                                   ip_out_q7_opt_fast, test2);
+
+    verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM);
+
+    printf("Start q7 opt implementation\n");
+
+    arm_fully_connected_q7_opt(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt_fast,
+                               test2);
+
+    verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM);
+
+    for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++)
+    {
+        test4[i] = (rand() % 65536 - 32768);
+    }
+
+    initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM);
+
+    printf("Start ref q15 implementation\n");
+
+    arm_fully_connected_q15_ref(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_ref, NULL);
+
+    printf("Start q15 implementation\n");
+
+    arm_fully_connected_q15(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL);
+
+    verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM);
+
+    printf("Start ref opt q15 implementation\n");
+
+    arm_fully_connected_q15_opt_ref(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt,
+                                    NULL);
+
+    verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM);
+
+    printf("Start opt q15 implementation\n");
+
+    arm_fully_connected_q15_opt(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL);
+
+    verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM);
+
+    initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM);
+
+    printf("Start ref q7_q15 implementation\n");
+
+    arm_fully_connected_mat_q7_vec_q15_ref(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_ref,
+                                           test2);
+
+    printf("Start q7_q15 implementation\n");
+
+    arm_fully_connected_mat_q7_vec_q15(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_opt,
+                                       test2);
+
+    verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM);
+
+    printf("Start ref opt q7_q15 implementation\n");
+
+    arm_fully_connected_mat_q7_vec_q15_opt_ref(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7,
+                                               ip_out_q15_opt, test2);
+
+    verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM);
+
+    printf("Start opt q7_q15 implementation\n");
+
+    arm_fully_connected_mat_q7_vec_q15_opt(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7,
+                                           ip_out_q15_opt, test2);
+
+    verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM);
+
+    delete[]test1;
+    delete[]test2;
+    delete[]test3;
+    delete[]test4;
+
+#endif
+
+#ifdef TEST_NONSQUARE
+
+/* Use RCONV to differential with square CONV */
+
+#define RCONV_IM_DIM_X 10
+#define RCONV_IM_DIM_Y 8
+#define RCONV_IM_CH 4
+#define RCONV_KER_DIM_X 5
+#define RCONV_KER_DIM_Y 3
+#define RCONV_STRIDE_X 1
+#define RCONV_STRIDE_Y 1
+#define RCONV_PADDING_X 2
+#define RCONV_PADDING_Y 1
+#define RCONV_OUT_CH 4
+#define RCONV_OUT_DIM_X 10
+#define RCONV_OUT_DIM_Y 8
+
+    test1 = new q7_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH];
+    test2 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH];
+    test3 =
+        new q7_t[RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH];
+
+    for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++)
+    {
+        test1[i] = rand() % 256 - 100;
+    }
+
+    for (int i = 0;
+         i < RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; i++)
+    {
+        test3[i] = rand() % 256 - 100;
+    }
+
+    q7_t     *rconv_weight_q7 = test1;
+    q7_t     *rconv_bias_q7 = test1 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH;
+
+    q15_t    *rconv_buf = test2;
+
+    q7_t     *rconv_im_in_q7 = test3;
+    q7_t     *rconv_im_out_ref_q7 = test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH;
+    q7_t     *rconv_im_out_opt_q7 =
+        test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH;
+
+    initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH);
+
+    printf("start conv q7 nonsquare ref implementation\n");
+    arm_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7,
+                                      RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y,
+                                      RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7,
+                                      RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL);
+
+    printf("start conv q7 nonsquare opt implementation\n");
+    arm_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7,
+                                       RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y,
+                                       RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7,
+                                       RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL);
+
+    verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH);
+
+    initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH);
+
+    printf("start conv q7 nonsquare ref implementation\n");
+    arm_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7,
+                                      RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y,
+                                      RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7,
+                                      RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL);
+
+    printf("start conv q7 nonsquare basic implementation\n");
+    arm_convolve_HWC_q7_basic_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7,
+                                       RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y,
+                                       RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7,
+                                       RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL);
+
+    verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH);
+
+    initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH);
+
+    printf("start 1x1 conv q7 nonsquare fast implementation\n");
+    arm_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7,
+                                       RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X,
+                                       RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X,
+                                       RCONV_OUT_DIM_Y, rconv_buf, NULL);
+
+    printf("start 1x1 conv q7 nonsquare dedicated function implementation\n");
+    arm_convolve_1x1_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7,
+                                           RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X,
+                                           RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X,
+                                           RCONV_OUT_DIM_Y, rconv_buf, NULL);
+
+    verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH);
+
+    printf("start depthwise separable conv q7 nonsquare ref implementation\n");
+    arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH,
+                                                      rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y,
+                                                      RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y,
+                                                      rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X,
+                                                      RCONV_OUT_DIM_Y, rconv_buf, NULL);
+
+    printf("start depthwise separable conv q7 nonsquare opt implementation\n");
+    arm_depthwise_separable_conv_HWC_q7_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH,
+                                                  rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y,
+                                                  RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y,
+                                                  rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X,
+                                                  RCONV_OUT_DIM_Y, rconv_buf, NULL);
+
+    verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH);
+
+    delete[]test1;
+    delete[]test2;
+    delete[]test3;
+	
+	test2 = new q15_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH]; // weights + bias
+	test4 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH   //buffer
+	         + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH]; // i/o
+
+    for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++)
+    {
+        test2[i] = rand() % 256 - 100;
+    }
+
+    for (int i = 0;
+         i < 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH
+         + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH;
+        i++)
+    {
+        test4[i] = rand() % 256 - 100;
+    }
+
+    q15_t     *rconv_weight_q15 = test2;
+    q15_t     *rconv_bias_q15 = test2 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH;
+
+    rconv_buf = test4;
+
+    q15_t     *rconv_im_in_q15 = test4 + 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH;
+    q15_t     *rconv_im_out_ref_q15 = rconv_im_in_q15 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH;
+    q15_t     *rconv_im_out_opt_q15 = rconv_im_out_ref_q15 + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH;
+
+    initialize_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH);
+
+    printf("start conv q15 nonsquare ref implementation\n");
+    arm_convolve_HWC_q15_nonsquare_ref(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15,
+                                      RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y,
+                                      RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_ref_q15,
+                                      RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL);
+
+    printf("start conv q5 nonsquare opt implementation\n");
+    arm_convolve_HWC_q15_fast_nonsquare(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15,
+                                       RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y,
+                                       RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_opt_q15,
+                                       RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL);
+
+    verify_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH);
+	
+    delete [] test2;
+    delete [] test4;
+#endif
+
+#ifdef TEST_CONV
+
+#define CONV_IM_DIM 16
+#define CONV_IM_CH 16
+#define CONV_KER_DIM 5
+#define CONV_OUT_CH 16
+#define CONV_OUT_DIM 16
+
+    test1 = new q7_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH];
+    test2 =
+        new q15_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH +
+                  2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH];
+    test3 = new q7_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH];
+    test4 = new q15_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH];
+
+    for (int i = 0; i < CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; i++)
+    {
+        test1[i] = rand() % 256 - 100;
+    }
+
+    for (int i = 0;
+         i <
+         CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH +
+         2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; i++)
+    {
+        test2[i] = (rand() % 65536 - 32768);
+    }
+
+    for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++)
+    {
+        test3[i] = rand() % 256 - 100;
+    }
+
+    for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++)
+    {
+        test4[i] = (rand() % 65536 - 32768);
+    }
+
+    q7_t     *conv_weight_q7 = test1;
+    q7_t     *conv_bias_q7 = test1 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH;
+
+    q15_t    *conv_weight_q15 = test2;
+    q15_t    *conv_buf = test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH;
+    q15_t    *conv_bias_q15 =
+        test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH +
+        2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH;
+
+    q7_t     *conv_im_in_q7 = test3;
+    q7_t     *conv_im_out_ref_q7 = test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH;
+    q7_t     *conv_im_out_opt_q7 =
+        test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH;
+
+    q15_t    *conv_im_in_q15 = test4;
+    q15_t    *conv_im_out_ref_q15 = test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH;
+    q15_t    *conv_im_out_opt_q15 =
+        test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH;
+
+    initialize_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH);
+
+    printf("start q7 ref implementation\n");
+
+    arm_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7,
+                            CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7,
+                            CONV_OUT_DIM, conv_buf, NULL);
+
+    printf("start q7 basic implementation\n");
+
+    arm_convolve_HWC_q7_basic(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7,
+                              CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7,
+                              CONV_OUT_DIM, conv_buf, NULL);
+
+    verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH);
+
+    printf("start q7 fast implementation\n");
+
+    arm_convolve_HWC_q7_fast(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7,
+                             CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7,
+                             CONV_OUT_DIM, conv_buf, NULL);
+
+    verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH);
+
+    // testing with RGB
+    printf("start q7 ref implementation for RGB\n");
+
+    arm_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7,
+                            CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7,
+                            CONV_OUT_DIM, conv_buf, NULL);
+
+    printf("start q7 basic implementation for RGB\n");
+
+    arm_convolve_HWC_q7_basic(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7,
+                              CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7,
+                              CONV_OUT_DIM, conv_buf, NULL);
+
+    verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH);
+
+    printf("start q7 RGB implementation for RGB\n");
+
+    arm_convolve_HWC_q7_RGB(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7,
+                            CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7,
+                            CONV_OUT_DIM, conv_buf, NULL);
+
+    verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH);
+
+    // testing q15
+    initialize_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH);
+
+    printf("start q15 ref implementation\n");
+
+    arm_convolve_HWC_q15_ref(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15,
+                             CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_ref_q15,
+                             CONV_OUT_DIM, conv_buf, NULL);
+
+    printf("start q15 basic implementation\n");
+
+    arm_convolve_HWC_q15_basic(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15,
+                               CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_opt_q15,
+                               CONV_OUT_DIM, conv_buf, NULL);
+
+    verify_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH);
+
+    printf("start q15 fast implementation\n");
+
+    arm_convolve_HWC_q15_fast(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15,
+                              CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_opt_q15,
+                              CONV_OUT_DIM, conv_buf, NULL);
+
+    verify_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH);
+
+    // depthwise separable conv
+    initialize_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH);
+
+    printf("start q7 depthwise_separable_conv ref implementation\n");
+
+    arm_depthwise_separable_conv_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7,
+                                            CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7,
+                                            CONV_OUT_DIM, conv_buf, NULL);
+
+    printf("start q7 depthwise_separable_conv implementation\n");
+
+    arm_depthwise_separable_conv_HWC_q7(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7,
+                                        CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7,
+                                        CONV_OUT_DIM, conv_buf, NULL);
+
+    verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH);
+
+    delete[]test1;
+    delete[]test2;
+    delete[]test3;
+    delete[]test4;
+
+#endif
+
+    test_pass = true;
+    test_index = 0;
+    while (test_flags[test_index] != -1) {
+        if (test_flags[test_index]) {
+             test_pass = false;
+        }
+        test_index ++;
+    }
+    if (test_pass) {
+        printf("All tests passed\n");
+    } else {
+        printf("Test failed passed\n");
+    }
+
+    return 0;
+}
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h
new file mode 100644
index 0000000..2e33988
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h
@@ -0,0 +1,78 @@
+#ifndef _MAIN_H_
+#define _MAIN_H_
+
+#include 
+#include 
+#include 
+
+#include "arm_math.h"
+
+#include "arm_nnfunctions.h"
+#include "ref_functions.h"
+
+extern int test_index;
+extern q7_t test_flags[50];
+
+void initialize_results_q7(q7_t * ref, q7_t * opt, int length)
+{
+    arm_fill_q7(0, ref, length);
+    arm_fill_q7(37, opt, length);
+}
+
+void initialize_results_q15(q15_t * ref, q15_t * opt, int length)
+{
+    arm_fill_q15(0, ref, length);
+    arm_fill_q15(0x5F5, opt, length);
+}
+
+void verify_results_q7(q7_t * ref, q7_t * opt, int length)
+{
+
+    bool      if_match = true;
+
+    for (int i = 0; i < length; i++)
+    {
+        if (ref[i] != opt[i])
+        {
+            printf("Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]);
+
+            if_match = false;
+        }
+    }
+
+    if (if_match == true)
+    {
+        printf("Outputs match.\r\n\r\n");
+        test_flags[test_index++] = 0;
+    } else {
+        test_flags[test_index++] = 1;
+    }
+
+}
+
+void verify_results_q15(q15_t * ref, q15_t * opt, int length)
+{
+
+    bool      if_match = true;
+
+    for (int i = 0; i < length; i++)
+    {
+        if (ref[i] != opt[i])
+        {
+            printf("Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]);
+
+            if_match = false;
+        }
+    }
+
+    if (if_match == true)
+    {
+        printf("Outputs match.\r\n\r\n");
+        test_flags[test_index++] = 0;
+    } else {
+        test_flags[test_index++] = 1;
+    }
+
+}
+
+#endif
diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt
new file mode 100644
index 0000000..0ea82e7
--- /dev/null
+++ b/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt
@@ -0,0 +1,4 @@
+CMSIS DSP_Lib example arm_nnexample_nn_test for
+  Cortex-M3, Cortex-M4 and Cortex-M7.
+
+The example is configured for uVision Simulator.
diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c
new file mode 100644
index 0000000..fd447e5
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nn_activations_q15.c
+ * Description:  Q15 neural network activation function using direct table look-up
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Acti
+ * @{
+ */
+
+  /**
+   * @brief Q15 neural network activation function using direct table look-up
+   * @param[in,out]   data        pointer to input
+   * @param[in]       size        number of elements
+   * @param[in]       int_width   bit-width of the integer part, assume to be smaller than 3
+   * @param[in]       type        type of activation functions
+   * @return none.
+   *
+   * @details
+   * 
+   * This is the direct table look-up approach.
+   *
+   * Assume here the integer part of the fixed-point is <= 3.
+   * More than 3 just not making much sense, makes no difference with
+   * saturation followed by any of these activation functions. 
+   */
+
+void arm_nn_activations_direct_q15(q15_t * data, uint16_t size, uint16_t int_width, arm_nn_activation_type type)
+{
+    uint16_t  i = size;
+    q15_t    *pIn = data;
+    q15_t    *pOut = data;
+    uint16_t  shift_size = 8 + 3 - int_width;
+    uint32_t  bit_mask = 0x7FF >> int_width;
+    uint32_t  full_frac = bit_mask + 1;
+    const q15_t *lookup_table;
+
+    switch (type)
+    {
+    case ARM_SIGMOID:
+        lookup_table = sigmoidTable_q15;
+        break;
+    case ARM_TANH:
+    default:
+        lookup_table = tanhTable_q15;
+        break;
+    }
+
+    while (i)
+    {
+        q15_t     out;
+        q15_t     in = *pIn++;
+        q15_t     frac = (uint32_t) in & bit_mask;
+        q15_t     value = lookup_table[__USAT(in >> shift_size, 8)];
+        q15_t     value2 = lookup_table[__USAT(1 + (in >> shift_size), 8)];
+
+        /* doing the interpolation here for better accuracy */
+        out = ((q31_t) (full_frac - frac) * value + (q31_t) value2 * frac) >> shift_size;
+
+        *pOut++ = out;
+        i--;
+    }
+
+}
+
+/**
+ * @} end of Acti group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c
new file mode 100644
index 0000000..2953bd5
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nn_activations_q7.c
+ * Description:  Q7 neural network activation function using direct table look-up
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Acti
+ * @{
+ */
+
+  /**
+   * @brief Q7 neural network activation function using direct table look-up
+   * @param[in,out]   data        pointer to input
+   * @param[in]       size        number of elements
+   * @param[in]       int_width   bit-width of the integer part, assume to be smaller than 3
+   * @param[in]       type        type of activation functions
+   * @return none.
+   *
+   * @details
+   * 
+   * This is the direct table look-up approach.
+   *
+   * Assume here the integer part of the fixed-point is <= 3.
+   * More than 3 just not making much sense, makes no difference with
+   * saturation followed by any of these activation functions. 
+   */
+
+void arm_nn_activations_direct_q7(q7_t * data, uint16_t size, uint16_t int_width, arm_nn_activation_type type)
+{
+    uint16_t  i = size;
+    q7_t     *pIn = data;
+    q7_t     *pOut = data;
+    q7_t      in;
+    q7_t      out;
+    uint16_t  shift_size = 3 - int_width;
+    const q7_t *lookup_table;
+    switch (type)
+    {
+    case ARM_SIGMOID:
+        lookup_table = sigmoidTable_q7;
+        break;
+    case ARM_TANH:
+    default:
+        lookup_table = tanhTable_q7;
+        break;
+    }
+    while (i)
+    {
+        in = *pIn++;
+        out = lookup_table[(uint8_t) (in >> shift_size)];
+        *pOut++ = out;
+        i--;
+    }
+}
+
+/**
+ * @} end of Acti group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c
new file mode 100644
index 0000000..6a1b907
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_relu_q15.c
+ * Description:  Q15 version of ReLU
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Acti
+ * @{
+ */
+
+  /**
+   * @brief Q15 RELU function
+   * @param[in,out]   data        pointer to input
+   * @param[in]       size        number of elements
+   * @return none.
+   * 
+   * @details
+   *
+   * Optimized relu with QSUB instructions.
+   *
+   */
+
+void arm_relu_q15(q15_t * data, uint16_t size)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    uint16_t  i = size >> 1;
+    q15_t    *pIn = data;
+    q15_t    *pOut = data;
+    q31_t     in;
+    q31_t     buf;
+    q31_t     mask;
+
+    while (i)
+    {
+        in = *__SIMD32(pIn)++;
+
+        /* extract the first bit */
+        buf = __ROR(in & 0x80008000, 15);
+
+        /* if MSB=1, mask will be 0xFF, 0x0 otherwise */
+        mask = __QSUB16(0x00000000, buf);
+
+        *__SIMD32(pOut)++ = in & (~mask);
+        i--;
+    }
+
+    if (size & 0x1)
+    {
+        if (*pIn < 0)
+        {
+            *pIn = 0;
+        }
+        pIn++;
+    }
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    uint16_t  i;
+
+    for (i = 0; i < size; i++)
+    {
+        if (data[i] < 0)
+            data[i] = 0;
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+}
+
+/**
+ * @} end of Acti group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c
new file mode 100644
index 0000000..caa027b
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_relu_q7.c
+ * Description:  Q7 version of ReLU
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Acti
+ * @{
+ */
+
+  /**
+   * @brief Q7 RELU function
+   * @param[in,out]   data        pointer to input
+   * @param[in]       size        number of elements
+   * @return none.
+   * 
+   * @details
+   *
+   * Optimized relu with QSUB instructions.
+   *
+   */
+
+void arm_relu_q7(q7_t * data, uint16_t size)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    uint16_t  i = size >> 2;
+    q7_t     *pIn = data;
+    q7_t     *pOut = data;
+    q31_t     in;
+    q31_t     buf;
+    q31_t     mask;
+
+    while (i)
+    {
+        in = *__SIMD32(pIn)++;
+
+        /* extract the first bit */
+        buf = __ROR(in & 0x80808080, 7);
+
+        /* if MSB=1, mask will be 0xFF, 0x0 otherwise */
+        mask = __QSUB8(0x00000000, buf);
+
+        *__SIMD32(pOut)++ = in & (~mask);
+        i--;
+    }
+
+    i = size & 0x3;
+    while (i)
+    {
+        if (*pIn < 0)
+        {
+            *pIn = 0;
+        }
+        pIn++;
+        i--;
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+
+    uint16_t  i;
+
+    for (i = 0; i < size; i++)
+    {
+        if (data[i] < 0)
+            data[i] = 0;
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+}
+
+/**
+ * @} end of Acti group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c
new file mode 100644
index 0000000..4c69e7c
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_convolve_1x1_HWC_q7_fast_nonsquare.c
+ * Description:  Fast Q7 version of 1x1 convolution (non-square shape)
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup NNConv
+ * @{
+ */
+
+/**
+ * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape)
+ * @param[in]       Im_in        pointer to input tensor
+ * @param[in]       dim_im_in_x  input tensor dimention x
+ * @param[in]       dim_im_in_y  input tensor dimention y
+ * @param[in]       ch_im_in     number of input tensor channels
+ * @param[in]       wt           pointer to kernel weights
+ * @param[in]       ch_im_out    number of filters, i.e., output tensor channels
+ * @param[in]       dim_kernel_x filter kernel size x
+ * @param[in]       dim_kernel_y filter kernel size y
+ * @param[in]       padding_x    padding size x
+ * @param[in]       padding_y    padding size y
+ * @param[in]       stride_x     convolution stride x
+ * @param[in]       stride_y     convolution stride y
+ * @param[in]       bias         pointer to bias
+ * @param[in]       bias_shift   amount of left-shift for bias
+ * @param[in]       out_shift    amount of right-shift for output
+ * @param[in,out]   Im_out       pointer to output tensor
+ * @param[in]       dim_im_out_x output tensor dimension x
+ * @param[in]       dim_im_out_y output tensor dimension y
+ * @param[in,out]   bufferA      pointer to buffer space for input 
+ * @param[in,out]   bufferB      pointer to buffer space for output
+ * @return     The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * This function is optimized for convolution with 1x1 kernel size (i.e., dim_kernel_x=1
+ * and dim_kernel_y=1). It can be used for the second half of MobileNets [1] after depthwise 
+ * separable convolution.
+ *
+ * This function is the version with full list of optimization tricks, but with
+ * some contraints:
+ *   ch_im_in is multiple of 4
+ *   ch_im_out is multiple of 2
+ *
+ * [1] MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications
+ * https://arxiv.org/abs/1704.04861
+ */
+
+arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t * Im_in,
+                                                  const uint16_t dim_im_in_x,
+                                                  const uint16_t dim_im_in_y,
+                                                  const uint16_t ch_im_in,
+                                                  const q7_t * wt,
+                                                  const uint16_t ch_im_out,
+                                                  const uint16_t dim_kernel_x,
+                                                  const uint16_t dim_kernel_y,
+                                                  const uint16_t padding_x,
+                                                  const uint16_t padding_y,
+                                                  const uint16_t stride_x,
+                                                  const uint16_t stride_y,
+                                                  const q7_t * bias,
+                                                  const uint16_t bias_shift,
+                                                  const uint16_t out_shift,
+                                                  q7_t * Im_out,
+                                                  const uint16_t dim_im_out_x,
+                                                  const uint16_t dim_im_out_y, 
+                                                  q15_t * bufferA, 
+                                                  q7_t * bufferB)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    int16_t   i_out_y, i_out_x;
+    int16_t   i_ch_out;
+
+    /* -----------------------
+     *  Here we use bufferA as q15_t internally as computation are done with q15_t level
+     *  im2col are done to output in q15_t format from q7_t input
+     */
+
+    q15_t    *pBuffer = bufferA;
+    q7_t     *pOut = Im_out;
+
+    if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1
+        || padding_x != 0 || padding_y != 0 || stride_x != 1 || stride_y != 1)
+    {
+        /* check if the input dimension meets the constraints */
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
+        {
+            /* This part implements the im2col function */
+            arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_out_y * dim_im_in_x + i_out_x) * ch_im_in, pBuffer,
+                                             ch_im_in);
+            pBuffer += ch_im_in;
+
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in, bias_shift, out_shift, bias, pOut);
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+    }
+
+    /* check if there is left-over for compute */
+    if (pBuffer != bufferA)
+    {
+        const q7_t *pA = wt;
+        for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++)
+        {
+            q31_t     sum = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift);
+            q15_t    *pB = bufferA;
+            /* basically each time it process 4 entries */
+            uint16_t  colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2;
+
+            while (colCnt)
+            {
+
+                q31_t     inA1, inA2;
+                q31_t     inB1, inB2;
+
+                pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2);
+
+                inB1 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA1, inB1, sum);
+                inB2 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA2, inB2, sum);
+
+                colCnt--;
+            }
+            colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3;
+            while (colCnt)
+            {
+                q7_t      inA1 = *pA++;
+                q15_t     inB1 = *pB++;
+                sum += inA1 * inB1;
+                colCnt--;
+            }
+            *pOut = (q7_t) __SSAT((sum >> out_shift), 8);
+            pOut++;
+
+        }
+
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+		
+    int       i, j, k, l, m, n;
+    int       conv_out;
+    int       in_row, in_col;
+
+    if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1
+        || padding_x != 0 || padding_y != 0 || stride_x != 1 || stride_y != 1)
+    {
+        /* check if the input dimension meets the constraints */
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out_y; j++)
+        {
+            for (k = 0; k < dim_im_out_x; k++)
+            {
+                conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift);
+                for (m = 0; m < dim_kernel_y; m++)
+                {
+                    for (n = 0; n < dim_kernel_x; n++)
+                    {
+                        // if-for implementation
+                        in_row = stride_y * j + m - padding_y;
+                        in_col = stride_x * k + n - padding_x;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] *
+                                    wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_y + n) * ch_im_in + l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to application */
+    return ARM_MATH_SUCCESS;
+}
+
+/**
+ * @} end of NNConv group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c
new file mode 100644
index 0000000..ee08d74
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_convolve_HWC_q15_basic.c
+ * Description:  Q15 version of convolution
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup NNConv
+ * @{
+ */
+
+  /**
+   * @brief Basic Q15 convolution function
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       wt          pointer to kernel weights
+   * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       bias        pointer to bias
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input
+   * @param[in,out]   bufferB     pointer to buffer space for output
+   * @return     The function returns ARM_MATH_SUCCESS 
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * bufferA size: ch_im_in*dim_kernel*dim_kernel
+   *
+   * bufferB size: 0
+   *
+   * This basic version is designed to work for any input tensor and weight
+   * dimension. 
+   */
+
+arm_status
+arm_convolve_HWC_q15_basic(const q15_t * Im_in,
+                           const uint16_t dim_im_in,
+                           const uint16_t ch_im_in,
+                           const q15_t * wt,
+                           const uint16_t ch_im_out,
+                           const uint16_t dim_kernel,
+                           const uint16_t padding,
+                           const uint16_t stride,
+                           const q15_t * bias,
+                           const uint16_t bias_shift,
+                           const uint16_t out_shift,
+                           q15_t * Im_out, 
+                           const uint16_t dim_im_out, 
+                           q15_t * bufferA, 
+                           q7_t * bufferB)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    int16_t   i_out_y, i_out_x, i_ker_y, i_ker_x;
+
+    uint16_t  im2col_out_pixel_index = 0;
+    q15_t    *pBuffer = bufferA;
+    q15_t    *pOut = Im_out;
+    q15_t    *im_buffer = bufferA;
+    const q15_t *pA;
+    int       i;
+
+    /* This part implements the im2col function */
+    for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
+        {
+            for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
+                    {
+                        /* Filling 0 for out-of-bound paddings */
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */
+                        memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            pA = wt;
+            for (i = 0; i < ch_im_out; i++)
+            {
+                q31_t     sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+                q15_t    *pB = im_buffer;
+                uint16_t  colCnt = ch_im_in * dim_kernel * dim_kernel >> 2;
+                while (colCnt)
+                {
+                    q31_t     inA1 = *__SIMD32(pA)++;
+                    q31_t     inB1 = *__SIMD32(pB)++;
+                    q31_t     inA2 = *__SIMD32(pA)++;
+                    q31_t     inB2 = *__SIMD32(pB)++;
+
+                    sum = __SMLAD(inA1, inB1, sum);
+                    sum = __SMLAD(inA2, inB2, sum);
+
+                    colCnt--;
+                }
+                colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3;
+                while (colCnt)
+                {
+                    q15_t     inA1 = *pA++;
+                    q15_t     inB1 = *pB++;
+                    sum += inA1 * inB1;
+                    colCnt--;
+                }
+                *pOut = (q15_t) __SSAT((sum >> out_shift), 16);
+                pOut++;
+            }
+
+            /* counter reset */
+            pBuffer = im_buffer;
+            im2col_out_pixel_index++;
+        }
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    uint16_t  i, j, k, l, m, n;
+    int       conv_out;
+    signed char in_row, in_col;
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out; j++)
+        {
+            for (k = 0; k < dim_im_out; k++)
+            {
+                conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+                for (m = 0; m < dim_kernel; m++)
+                {
+                    for (n = 0; n < dim_kernel; n++)
+                    {
+                        in_row = stride * j + m - padding;
+                        in_col = stride * k + n - padding;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out +=
+                                    Im_in[(in_row * dim_im_in + in_col) * ch_im_in +
+                                          l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel +
+                                                                                            n) * ch_im_in + l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16);
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to application */
+    return ARM_MATH_SUCCESS;
+}
+
+/**
+ * @} end of NNConv group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c
new file mode 100644
index 0000000..a02aaa0
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_convolve_HWC_q15_fast.c
+ * Description:  Fast Q15 version of convolution
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup NNConv
+ * @{
+ */
+
+  /**
+   * @brief Fast Q15 convolution function
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       wt          pointer to kernel weights
+   * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       bias        pointer to bias
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input 
+   * @param[in,out]   bufferB     pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
+   *
+   * bufferB size: 0
+   *
+   * Input dimension constraints:
+   *
+   * ch_im_in is multiple of 2 
+   *
+   * ch_im_out is multipe of 2
+   *
+   */
+
+arm_status
+arm_convolve_HWC_q15_fast(const q15_t * Im_in,
+                          const uint16_t dim_im_in,
+                          const uint16_t ch_im_in,
+                          const q15_t * wt,
+                          const uint16_t ch_im_out,
+                          const uint16_t dim_kernel,
+                          const uint16_t padding,
+                          const uint16_t stride,
+                          const q15_t * bias,
+                          const uint16_t bias_shift,
+                          const uint16_t out_shift,
+                          q15_t * Im_out, 
+                          const uint16_t dim_im_out, 
+                          q15_t * bufferA, 
+                          q7_t * bufferB)
+{
+
+#if defined (ARM_MATH_DSP)
+    int16_t   i_out_y, i_out_x, i_ker_y, i_ker_x;
+
+    q15_t    *pBuffer = bufferA;
+    q15_t    *im_buffer = bufferA;
+    q15_t    *pOut = Im_out;
+
+    if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0)
+    {
+        /* check if the input dimension meets the constraints */
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    /* This part implements the im2col function */
+    for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
+        {
+            for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
+                    {
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */
+                        memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            if (i_out_x & 0x1)
+            {
+                int       i;
+                /* initialize the matrix pointers for A */
+                const q15_t *pA = wt;
+
+                /* set up the second output pointers */
+                q15_t    *pOut2 = pOut + ch_im_out;
+
+                /* this loop over rows in A */
+                for (i = 0; i < ch_im_out; i += 2)
+                {
+                    /* setup pointers for B */
+                    q15_t    *pB = im_buffer;
+                    const q15_t *pB2 = pB + ch_im_in * dim_kernel * dim_kernel;
+
+                    /* aling the second pointer for A */
+                    const q15_t *pA2 = pA + ch_im_in * dim_kernel * dim_kernel;
+
+                    /* init the sum with bias */
+                    q31_t     sum =  ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+                    q31_t     sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+                    q31_t     sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift);
+                    q31_t     sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift);
+
+                    uint16_t  colCnt = ch_im_in * dim_kernel * dim_kernel >> 1;
+                    /* accumulate over the vector */
+                    while (colCnt)
+                    {
+                        q31_t     inA1 = *__SIMD32(pA)++;
+                        q31_t     inB1 = *__SIMD32(pB)++;
+                        q31_t     inA2 = *__SIMD32(pA2)++;
+                        q31_t     inB2 = *__SIMD32(pB2)++;
+
+                        sum = __SMLAD(inA1, inB1, sum);
+                        sum2 = __SMLAD(inA1, inB2, sum2);
+                        sum3 = __SMLAD(inA2, inB1, sum3);
+                        sum4 = __SMLAD(inA2, inB2, sum4);
+
+                        colCnt--;
+                    }           /* while over colCnt */
+                    colCnt = ch_im_in * dim_kernel * dim_kernel & 0x1;
+                    while (colCnt)
+                    {
+                        q15_t     inA1 = *pA++;
+                        q15_t     inB1 = *pB++;
+                        q15_t     inA2 = *pA2++;
+                        q15_t     inB2 = *pB2++;
+
+                        sum += inA1 * inB1;
+                        sum2 += inA1 * inB2;
+                        sum3 += inA2 * inB1;
+                        sum4 += inA2 * inB2;
+                        colCnt--;
+                    }           /* while over colCnt */
+                    *pOut++ = (q15_t) __SSAT(sum >> out_shift, 16);
+                    *pOut++ = (q15_t) __SSAT(sum3 >> out_shift, 16);
+                    *pOut2++ = (q15_t) __SSAT(sum2 >> out_shift, 16);
+                    *pOut2++ = (q15_t) __SSAT(sum4 >> out_shift, 16);
+
+                    /* skip the row computed with A2 */
+                    pA += ch_im_in * dim_kernel * dim_kernel;
+                }               /* for over ch_im_out */
+
+                pOut += ch_im_out;
+                /* counter reset */
+                pBuffer = im_buffer;
+            }
+        }
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    uint16_t  i, j, k, l, m, n;
+    int       conv_out;
+    signed char in_row, in_col;
+
+    if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0)
+    {
+        /* check if the input dimension meets the constraints */
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out; j++)
+        {
+            for (k = 0; k < dim_im_out; k++)
+            {
+                conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+                for (m = 0; m < dim_kernel; m++)
+                {
+                    for (n = 0; n < dim_kernel; n++)
+                    {
+                        in_row = stride * j + m - padding;
+                        in_col = stride * k + n - padding;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out +=
+                                    Im_in[(in_row * dim_im_in + in_col) * ch_im_in +
+                                          l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel +
+                                                                                            n) * ch_im_in + l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16);
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to application */
+    return ARM_MATH_SUCCESS;
+}
+
+/**
+ * @} end of NNConv group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c
new file mode 100644
index 0000000..14d9130
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_convolve_HWC_q15_fast.c
+ * Description:  Fast Q15 version of convolution
+ *
+ * $Date:        24. May 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup NNConv
+ * @{
+ */
+
+  /**
+   * @brief Fast Q15 convolution function (non-sqaure shape)
+   * @param[in]       Im_in        pointer to input tensor
+   * @param[in]       dim_im_in_x  input tensor dimention x
+   * @param[in]       dim_im_in_y  input tensor dimention y
+   * @param[in]       ch_im_in     number of input tensor channels
+   * @param[in]       wt           pointer to kernel weights
+   * @param[in]       ch_im_out    number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel_x filter kernel size x
+   * @param[in]       dim_kernel_y filter kernel size y
+   * @param[in]       padding_x    padding size x
+   * @param[in]       padding_y    padding size y
+   * @param[in]       stride_x     convolution stride x
+   * @param[in]       stride_y     convolution stride y
+   * @param[in]       bias         pointer to bias
+   * @param[in]       bias_shift   amount of left-shift for bias
+   * @param[in]       out_shift    amount of right-shift for output
+   * @param[in,out]   Im_out       pointer to output tensor
+   * @param[in]       dim_im_out_x output tensor dimension x
+   * @param[in]       dim_im_out_y output tensor dimension y
+   * @param[in,out]   bufferA      pointer to buffer space for input 
+   * @param[in,out]   bufferB      pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
+   *
+   * bufferB size: 0
+   *
+   * Input dimension constraints:
+   *
+   * ch_im_in is multiple of 2 
+   *
+   * ch_im_out is multipe of 2
+   *
+   */
+
+arm_status
+arm_convolve_HWC_q15_fast_nonsquare(const q15_t * Im_in,
+                                    const uint16_t dim_im_in_x,
+                                    const uint16_t dim_im_in_y,
+                                    const uint16_t ch_im_in,
+                                    const q15_t * wt,
+                                    const uint16_t ch_im_out,
+                                    const uint16_t dim_kernel_x,
+                                    const uint16_t dim_kernel_y,
+                                    const uint16_t padding_x,
+                                    const uint16_t padding_y,
+                                    const uint16_t stride_x,
+                                    const uint16_t stride_y,
+                                    const q15_t * bias,
+                                    const uint16_t bias_shift,
+                                    const uint16_t out_shift,
+                                    q15_t * Im_out,
+                                    const uint16_t dim_im_out_x,
+                                    const uint16_t dim_im_out_y, 
+                                    q15_t * bufferA, 
+                                    q7_t * bufferB)
+{
+
+#if defined (ARM_MATH_DSP)
+    int16_t   i_out_y, i_out_x, i_ker_y, i_ker_x;
+
+    q15_t    *pBuffer = bufferA;
+    q15_t    *im_buffer = bufferA;
+    q15_t    *pOut = Im_out;
+
+    if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0)
+    {
+        /* check if the input dimension meets the constraints */
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    /* This part implements the im2col function */
+    for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
+        {
+            for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x)
+                    {
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */
+                        memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            if (i_out_x & 0x1)
+            {
+                int       i;
+                /* initialize the matrix pointers for A */
+                const q15_t *pA = wt;
+
+                /* set up the second output pointers */
+                q15_t    *pOut2 = pOut + ch_im_out;
+
+                /* this loop over rows in A */
+                for (i = 0; i < ch_im_out; i += 2)
+                {
+                    /* setup pointers for B */
+                    q15_t    *pB = im_buffer;
+                    const q15_t *pB2 = pB + ch_im_in * dim_kernel_y * dim_kernel_x;
+
+                    /* aling the second pointer for A */
+                    const q15_t *pA2 = pA + ch_im_in * dim_kernel_y * dim_kernel_x;
+
+                    /* init the sum with bias */
+                    q31_t     sum =  ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+                    q31_t     sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+                    q31_t     sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift);
+                    q31_t     sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift);
+
+                    uint16_t  colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 1;
+                    /* accumulate over the vector */
+                    while (colCnt)
+                    {
+                        q31_t     inA1 = *__SIMD32(pA)++;
+                        q31_t     inB1 = *__SIMD32(pB)++;
+                        q31_t     inA2 = *__SIMD32(pA2)++;
+                        q31_t     inB2 = *__SIMD32(pB2)++;
+
+                        sum = __SMLAD(inA1, inB1, sum);
+                        sum2 = __SMLAD(inA1, inB2, sum2);
+                        sum3 = __SMLAD(inA2, inB1, sum3);
+                        sum4 = __SMLAD(inA2, inB2, sum4);
+
+                        colCnt--;
+                    }           /* while over colCnt */
+                    colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x1;
+                    while (colCnt)
+                    {
+                        q15_t     inA1 = *pA++;
+                        q15_t     inB1 = *pB++;
+                        q15_t     inA2 = *pA2++;
+                        q15_t     inB2 = *pB2++;
+
+                        sum += inA1 * inB1;
+                        sum2 += inA1 * inB2;
+                        sum3 += inA2 * inB1;
+                        sum4 += inA2 * inB2;
+                        colCnt--;
+                    }           /* while over colCnt */
+                    *pOut++ = (q15_t) __SSAT(sum >> out_shift, 16);
+                    *pOut++ = (q15_t) __SSAT(sum3 >> out_shift, 16);
+                    *pOut2++ = (q15_t) __SSAT(sum2 >> out_shift, 16);
+                    *pOut2++ = (q15_t) __SSAT(sum4 >> out_shift, 16);
+
+                    /* skip the row computed with A2 */
+                    pA += ch_im_in * dim_kernel_y * dim_kernel_x;
+                }               /* for over ch_im_out */
+
+                pOut += ch_im_out;
+                /* counter reset */
+                pBuffer = im_buffer;
+            }
+        }
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    uint16_t  i, j, k, l, m, n;
+    int       conv_out;
+    signed char in_row, in_col;
+
+    if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0)
+    {
+        /* check if the input dimension meets the constraints */
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out_y; j++)
+        {
+            for (k = 0; k < dim_im_out_x; k++)
+            {
+                conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+                for (m = 0; m < dim_kernel_y; m++)
+                {
+                    for (n = 0; n < dim_kernel_x; n++)
+                    {
+                        in_row = stride_y * j + m - padding_y;
+                        in_col = stride_x * k + n - padding_x;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out +=
+                                    Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in +
+                                          l] * wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x +
+                                                                                            n) * ch_im_in + l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16);
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to application */
+    return ARM_MATH_SUCCESS;
+}
+
+/**
+ * @} end of NNConv group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c
new file mode 100644
index 0000000..e53c6f9
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_convolve_HWC_q7_RGB.c
+ * Description:  Q7 version of convolution for RGB image
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup NNConv
+ * @{
+ */
+
+  /**
+   * @brief Q7 convolution function for RGB image
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       wt          pointer to kernel weights
+   * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       bias        pointer to bias
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input
+   * @param[in,out]   bufferB     pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
+   *
+   * bufferB size: 0
+   *
+   * Input dimension constraints:
+   *
+   * ch_im_in equals 3
+   *
+   * This kernel is written exclusively for convolution with ch_im_in
+   * equals 3. This applies on the first layer of CNNs which has input
+   * image with RGB format.
+   */
+
+arm_status
+arm_convolve_HWC_q7_RGB(const q7_t * Im_in,
+                        const uint16_t dim_im_in,
+                        const uint16_t ch_im_in,
+                        const q7_t * wt,
+                        const uint16_t ch_im_out,
+                        const uint16_t dim_kernel,
+                        const uint16_t padding,
+                        const uint16_t stride,
+                        const q7_t * bias,
+                        const uint16_t bias_shift,
+                        const uint16_t out_shift,
+                        q7_t * Im_out, const uint16_t dim_im_out, q15_t * bufferA, q7_t * bufferB)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+    int16_t   i_out_y, i_out_x, i_ker_y, i_ker_x;
+
+    /*
+     *  Here we use bufferA as q15_t internally as computation are done with q15_t level
+     *  im2col are done to output in q15_t format from q7_t input
+     */
+    q15_t    *pBuffer = bufferA;
+    q7_t     *pOut = Im_out;
+
+    // check if number of input channels is 3
+    if (ch_im_in != 3)
+    {
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+    // This part implements the im2col function
+    for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
+        {
+            for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
+                    {
+                        /* Equivalent to arm_fill_q15(0, pBuffer, ch_im_in) with assumption: ch_im_in = 3 */
+                        *__SIMD32(pBuffer) = 0x0;
+                        *(pBuffer + 2) = 0;
+                        pBuffer += 3;
+                    } else
+                    {
+                        /* 
+                         * Equivalent to:
+                         *  arm_q7_to_q15_no_shift( (q7_t*)Im_in+(i_ker_y*dim_im_in+i_ker_x)*3, pBuffer, 3);
+                         */
+
+                        const q7_t *pPixel = Im_in + (i_ker_y * dim_im_in + i_ker_x) * 3;
+                        q31_t     buf = *__SIMD32(pPixel);
+
+                        union arm_nnword top;
+                        union arm_nnword bottom;
+
+                        top.word = __SXTB16(buf);
+                        bottom.word = __SXTB16(__ROR(buf, 8));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+                        /*
+                         *  little-endian, | omit | 3rd  | 2nd  | 1st  |
+                         *                MSB                         LSB
+                         *   top | 3rd | 1st |; bottom | omit | 2nd |
+                         *
+                         *  version 1, need to swap 2nd and 3rd weight
+                         * *__SIMD32(pBuffer) = top.word;
+                         * *(pBuffer+2) = bottom.half_words[0];
+                         *
+                         *  version 2, no weight shuffling required
+                         */
+                        *pBuffer++ = top.half_words[0];
+                        *__SIMD32(pBuffer) = __PKHBT(bottom.word, top.word, 0);
+#else
+                        /*
+                         *  big-endian,    | 1st  | 2nd  | 3rd  | omit | 
+                         *                MSB                         LSB
+                         *  top | 2nd | omit |; bottom | 1st | 3rd |
+                         * 
+                         *  version 1, need to swap 2nd and 3rd weight
+                         * *__SIMD32(pBuffer) = bottom.word;
+                         * *(pBuffer+2) = top.half_words[1];
+                         * 
+                         *  version 2, no weight shuffling required
+                         */
+                        *pBuffer++ = bottom.half_words[0];
+                        *__SIMD32(pBuffer) = __PKHTB(top.word, bottom.word, 0);
+#endif
+                        pBuffer += 2;
+                    }
+                }
+            }
+
+            if (pBuffer == bufferA + 2 * 3 * dim_kernel * dim_kernel)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15(wt, bufferA,
+                                                  ch_im_out,
+                                                  3 * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut);
+
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+    }
+
+    /* left-over because odd number of output pixels */
+    if (pBuffer != bufferA)
+    {
+        const q7_t *pA = wt;
+        int       i;
+
+        for (i = 0; i < ch_im_out; i++)
+        {
+            q31_t     sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+            q15_t    *pB = bufferA;
+            /* basically each time it process 4 entries */
+            uint16_t  colCnt = 3 * dim_kernel * dim_kernel >> 2;
+
+            while (colCnt)
+            {
+
+                q31_t     inA1, inA2;
+                q31_t     inB1, inB2;
+
+                pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2);
+
+                inB1 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA1, inB1, sum);
+                inB2 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA2, inB2, sum);
+
+                colCnt--;
+            }
+            colCnt = 3 * dim_kernel * dim_kernel & 0x3;
+            while (colCnt)
+            {
+                q7_t      inA1 = *pA++;
+                q15_t     inB1 = *pB++;
+                sum += inA1 * inB1;
+                colCnt--;
+            }
+            *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
+        }
+    }
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+
+    uint16_t  i, j, k, l, m, n;
+    int       conv_out;
+    signed char in_row, in_col;
+
+    // check if number of input channels is 3
+    if (ch_im_in != 3)
+    {
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out; j++)
+        {
+            for (k = 0; k < dim_im_out; k++)
+            {
+                conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift);
+                for (m = 0; m < dim_kernel; m++)
+                {
+                    for (n = 0; n < dim_kernel; n++)
+                    {
+                        /* if-for implementation */
+                        in_row = stride * j + m - padding;
+                        in_col = stride * k + n - padding;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out +=
+                                    Im_in[(in_row * dim_im_in + in_col) * ch_im_in +
+                                          l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel +
+                                                                                            n) * ch_im_in + l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to application */
+    return (ARM_MATH_SUCCESS);
+}
+
+/**
+ * @} end of NNConv group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c
new file mode 100644
index 0000000..7c9ec65
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_convolve_HWC_q7_basic.c
+ * Description:	 Q7 version of convolution
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup NNConv
+ * @{
+ */
+
+  /**
+   * @brief Basic Q7 convolution function
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       wt          pointer to kernel weights
+   * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       bias        pointer to bias
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input 
+   * @param[in,out]   bufferB     pointer to buffer space for output
+   * @return     The function returns ARM_MATH_SUCCESS 
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
+   *
+   * bufferB size: 0
+   *
+   * This basic version is designed to work for any input tensor and weight
+   * dimension. 
+   */
+
+arm_status
+arm_convolve_HWC_q7_basic(const q7_t * Im_in,
+                          const uint16_t dim_im_in,
+                          const uint16_t ch_im_in,
+                          const q7_t * wt,
+                          const uint16_t ch_im_out,
+                          const uint16_t dim_kernel,
+                          const uint16_t padding,
+                          const uint16_t stride,
+                          const q7_t * bias,
+                          const uint16_t bias_shift,
+                          const uint16_t out_shift,
+                          q7_t * Im_out, 
+                          const uint16_t dim_im_out, 
+                          q15_t * bufferA, 
+                          q7_t * bufferB)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    int16_t   i_out_y, i_out_x, i_ker_y, i_ker_x;
+
+    /* 
+     *  Here we use bufferA as q15_t internally as computation are done with q15_t level
+     *  im2col are done to output in q15_t format from q7_t input
+     */
+    q15_t    *pBuffer = bufferA;
+    q7_t     *pOut = Im_out;
+
+    /* This part implements the im2col function */
+    for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
+        {
+            for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
+                    {
+                        /* Filling 0 for out-of-bound paddings */
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        /* Copying the pixel data to column */
+                        arm_q7_to_q15_no_shift((q7_t *)
+                                               Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            /* Computation is filed for every 2 columns */
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15(wt, bufferA,
+                                                  ch_im_out,
+                                                  ch_im_in *
+                                                  dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut);
+
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+    }
+
+    /* left-over because odd number of output pixels */
+    if (pBuffer != bufferA)
+    {
+        const q7_t *pA = wt;
+        int       i;
+
+        for (i = 0; i < ch_im_out; i++)
+        {
+            /* Load the accumulator with bias first */
+            q31_t     sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+
+            /* Point to the beging of the im2col buffer */
+            q15_t    *pB = bufferA;
+
+            /* Each time it process 4 entries */
+            uint16_t  colCnt = ch_im_in * dim_kernel * dim_kernel >> 2;
+
+            while (colCnt)
+            {
+                q31_t     inA1, inA2;
+                q31_t     inB1, inB2;
+
+                pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2);
+
+                inB1 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA1, inB1, sum);
+                inB2 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA2, inB2, sum);
+
+                colCnt--;
+            }
+            colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3;
+            while (colCnt)
+            {
+                q7_t      inA1 = *pA++;
+                q15_t     inB1 = *pB++;
+                sum += inA1 * inB1;
+                colCnt--;
+            }
+            *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
+        }
+    }
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+
+    uint16_t  i, j, k, l, m, n;
+    int       conv_out;
+    signed char in_row, in_col;
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out; j++)
+        {
+            for (k = 0; k < dim_im_out; k++)
+            {
+                conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+                for (m = 0; m < dim_kernel; m++)
+                {
+                    for (n = 0; n < dim_kernel; n++)
+                    {
+                        // if-for implementation
+                        in_row = stride * j + m - padding;
+                        in_col = stride * k + n - padding;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out +=
+                                    Im_in[(in_row * dim_im_in + in_col) * ch_im_in +
+                                          l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel +
+                                                                                            n) * ch_im_in + l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to application */
+    return ARM_MATH_SUCCESS;
+}
+
+/**
+ * @} end of NNConv group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c
new file mode 100644
index 0000000..24356d9
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_convolve_HWC_q7_basic.c
+ * Description:	 Q7 version of convolution
+ *
+ * $Date:        13. July 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup NNConv
+ * @{
+ */
+
+  /**
+   * @brief Basic Q7 convolution function (non-sqaure shape)
+   * @param[in]       Im_in        pointer to input tensor
+   * @param[in]       dim_im_in_x  input tensor dimention x
+   * @param[in]       dim_im_in_y  input tensor dimention y
+   * @param[in]       ch_im_in     number of input tensor channels
+   * @param[in]       wt           pointer to kernel weights
+   * @param[in]       ch_im_out    number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel_x filter kernel size x
+   * @param[in]       dim_kernel_y filter kernel size y
+   * @param[in]       padding_x    padding size x
+   * @param[in]       padding_y    padding size y
+   * @param[in]       stride_x     convolution stride x
+   * @param[in]       stride_y     convolution stride y
+   * @param[in]       bias         pointer to bias
+   * @param[in]       bias_shift   amount of left-shift for bias
+   * @param[in]       out_shift    amount of right-shift for output
+   * @param[in,out]   Im_out       pointer to output tensor
+   * @param[in]       dim_im_out_x output tensor dimension x
+   * @param[in]       dim_im_out_y output tensor dimension y
+   * @param[in,out]   bufferA      pointer to buffer space for input
+   * @param[in,out]   bufferB      pointer to buffer space for output
+   * @return     The function returns ARM_MATH_SUCCESS
+   */
+
+arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in,
+                                               const uint16_t dim_im_in_x,
+                                               const uint16_t dim_im_in_y,
+                                               const uint16_t ch_im_in,
+                                               const q7_t * wt,
+                                               const uint16_t ch_im_out,
+                                               const uint16_t dim_kernel_x,
+                                               const uint16_t dim_kernel_y,
+                                               const uint16_t padding_x,
+                                               const uint16_t padding_y,
+                                               const uint16_t stride_x,
+                                               const uint16_t stride_y,
+                                               const q7_t * bias,
+                                               const uint16_t bias_shift,
+                                               const uint16_t out_shift,
+                                               q7_t * Im_out,
+                                               const uint16_t dim_im_out_x,
+                                               const uint16_t dim_im_out_y,
+                                               q15_t * bufferA,
+                                               q7_t * bufferB)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    int16_t   i_out_y, i_out_x, i_ker_y, i_ker_x;
+
+    /* 
+     *  Here we use bufferA as q15_t internally as computation are done with q15_t level
+     *  im2col are done to output in q15_t format from q7_t input
+     */
+    q15_t    *pBuffer = bufferA;
+    q7_t     *pOut = Im_out;
+
+    /* This part implements the im2col function */
+    for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
+        {
+            for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x)
+                    {
+                        /* Filling 0 for out-of-bound paddings */
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        /* Copying the pixel data to column */
+                        arm_q7_to_q15_no_shift((q7_t *)
+                                               Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            /* Computation is filed for every 2 columns */
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_y * dim_kernel_x)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15(wt, bufferA,
+                                                  ch_im_out,
+                                                  ch_im_in *
+                                                  dim_kernel_y * dim_kernel_x, bias_shift, out_shift, bias, pOut);
+
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+    }
+
+    /* left-over because odd number of output pixels */
+    if (pBuffer != bufferA)
+    {
+        const q7_t *pA = wt;
+        int       i;
+
+        for (i = 0; i < ch_im_out; i++)
+        {
+            /* Load the accumulator with bias first */
+            q31_t     sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+
+            /* Point to the beging of the im2col buffer */
+            q15_t    *pB = bufferA;
+
+            /* Each time it process 4 entries */
+            uint16_t  colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 2;
+
+            while (colCnt)
+            {
+                q31_t     inA1, inA2;
+                q31_t     inB1, inB2;
+
+                pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2);
+
+                inB1 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA1, inB1, sum);
+                inB2 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA2, inB2, sum);
+
+                colCnt--;
+            }
+            colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3;
+            while (colCnt)
+            {
+                q7_t      inA1 = *pA++;
+                q15_t     inB1 = *pB++;
+                sum += inA1 * inB1;
+                colCnt--;
+            }
+            *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
+        }
+    }
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+
+    uint16_t  i, j, k, l, m, n;
+    int       conv_out;
+    signed char in_row, in_col;
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out_y; j++)
+        {
+            for (k = 0; k < dim_im_out_x; k++)
+            {
+                conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+                for (m = 0; m < dim_kernel_y; m++)
+                {
+                    for (n = 0; n < dim_kernel_x; n++)
+                    {
+                        // if-for implementation
+                        in_row = stride_y * j + m - padding_y;
+                        in_col = stride_x * k + n - padding_x;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out +=
+                                    Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * 
+                                         wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + 
+                                         (m * dim_kernel_x + n) * ch_im_in + l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to application */
+    return ARM_MATH_SUCCESS;
+}
+
+/**
+ * @} end of NNConv group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c
new file mode 100644
index 0000000..e2d469f
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c
@@ -0,0 +1,408 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_convolve_HWC_q7_fast.c
+ * Description:  Fast Q7 version of convolution
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup NNConv
+ * @{
+ */
+
+  /**
+   * @brief Fast Q7 convolution function
+   * @param[in]       Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       wt          pointer to kernel weights
+   * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       bias        pointer to bias
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input 
+   * @param[in,out]   bufferB     pointer to buffer space for output
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
+   *
+   * bufferB size: 0
+   *
+   * Input dimension constraints:
+   *
+   * ch_im_in is multiple of 4    ( because of the SIMD32 read and swap )
+   *
+   * ch_im_out is multipe of 2    ( bacause 2x2 mat_mult kernel )
+   *
+   * The im2col converts the Q7 tensor input into Q15 column, which is stored in
+   * bufferA. There is reordering happenning during this im2col process with
+   * arm_q7_to_q15_reordered_no_shift. For every four elements, the second and
+   * third elements are swapped. 
+   *
+   * The computation kernel arm_nn_mat_mult_kernel_q7_q15_reordered does the
+   * GEMM computation with the reordered columns.
+   *
+   * To speed-up the determination of the padding condition, we split the
+   * computation into 3x3 parts, i.e., {top, mid, bottom} X {left, mid, right}.
+   * This reduces the total number of boundary condition checks and improves
+   * the data copying performance.
+   */
+
+arm_status
+arm_convolve_HWC_q7_fast(const q7_t * Im_in,
+                         const uint16_t dim_im_in,
+                         const uint16_t ch_im_in,
+                         const q7_t * wt,
+                         const uint16_t ch_im_out,
+                         const uint16_t dim_kernel,
+                         const uint16_t padding,
+                         const uint16_t stride,
+                         const q7_t * bias,
+                         const uint16_t bias_shift,
+                         const uint16_t out_shift,
+                         q7_t * Im_out, 
+                         const uint16_t dim_im_out, 
+                         q15_t * bufferA, 
+                         q7_t * bufferB)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    int16_t   i_out_y, i_out_x, i_ker_y, i_ker_x;
+
+    /*
+     *  Here we use bufferA as q15_t internally as computation are done with q15_t level
+     *  im2col are done to output in q15_t format from q7_t input
+     */
+
+    q15_t    *pBuffer = bufferA;
+    q7_t     *pOut = Im_out;
+
+    if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0)
+    {
+        /* check if the input dimension meets the constraints */
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    /*
+     *  Here we split the entire matrix into three regions depending on the padding situation
+     *    Top: i_out_y from 0 to padding - 1
+     * Middle: i_out_y from padding to dim_im_out-padding-1
+     * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1
+     */
+
+    /* top part */
+    for (i_out_y = 0; i_out_y < padding; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
+        {
+            /* This part implements the im2col function */
+            for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
+                    {
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        arm_q7_to_q15_reordered_no_shift
+                            ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15_reordered(wt,
+                                                            bufferA,
+                                                            ch_im_out,
+                                                            ch_im_in
+                                                            *
+                                                            dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut);
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+    }
+
+    /* middle part, here we also divide the x into left, mid and right */
+    for (; i_out_y < dim_im_out - padding; i_out_y++)
+    {
+
+        /* left part */
+        for (i_out_x = 0; i_out_x < padding; i_out_x++)
+        {
+            /* This part implements the im2col function */
+            for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
+                {
+                    if (i_ker_x < 0 || i_ker_x >= dim_im_in)
+                    {
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        arm_q7_to_q15_reordered_no_shift
+                            ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15_reordered(wt,
+                                                            bufferA,
+                                                            ch_im_out,
+                                                            ch_im_in
+                                                            *
+                                                            dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut);
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+
+        /* mid part */
+        for (; i_out_x < dim_im_out - padding; i_out_x++)
+        {
+            /* This part implements the im2col function */
+            for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
+            {
+                arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in
+                                                 +
+                                                 (i_ker_y *
+                                                  dim_im_in +
+                                                  i_out_x *
+                                                  stride - padding) * ch_im_in, pBuffer, ch_im_in * dim_kernel);
+                pBuffer += ch_im_in * dim_kernel;
+            }
+
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15_reordered(wt,
+                                                            bufferA,
+                                                            ch_im_out,
+                                                            ch_im_in
+                                                            *
+                                                            dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut);
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+
+        /* right part */
+        for (; i_out_x < dim_im_out; i_out_x++)
+        {
+            /* This part implements the im2col function */
+            for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
+                {
+                    if (i_ker_x < 0 || i_ker_x >= dim_im_in)
+                    {
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        arm_q7_to_q15_reordered_no_shift
+                            ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15_reordered(wt,
+                                                            bufferA,
+                                                            ch_im_out,
+                                                            ch_im_in
+                                                            *
+                                                            dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut);
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+    }
+
+    for (; i_out_y < dim_im_out; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
+        {
+            /* This part implements the im2col function */
+            for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
+                    {
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        arm_q7_to_q15_reordered_no_shift
+                            ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15_reordered(wt,
+                                                            bufferA,
+                                                            ch_im_out,
+                                                            ch_im_in
+                                                            *
+                                                            dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut);
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+    }
+
+    /* check if there is left-over for compute */
+    if (pBuffer != bufferA)
+    {
+        const q7_t *pA = wt;
+        int       i;
+
+        for (i = 0; i < ch_im_out; i++)
+        {
+            q31_t     sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
+            q15_t    *pB = bufferA;
+            /* each time it process 4 entries */
+            uint16_t  colCnt = ch_im_in * dim_kernel * dim_kernel >> 2;
+
+            while (colCnt)
+            {
+
+                q31_t     inA1, inA2;
+                q31_t     inB1, inB2;
+
+                pA = (q7_t *) read_and_pad_reordered((void *)pA, &inA1, &inA2);
+
+                inB1 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA1, inB1, sum);
+                inB2 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA2, inB2, sum);
+
+                colCnt--;
+            }
+            colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3;
+            while (colCnt)
+            {
+                q7_t      inA1 = *pA++;
+                q15_t     inB1 = *pB++;
+                sum += inA1 * inB1;
+                colCnt--;
+            }
+            *pOut = (q7_t) __SSAT((sum >> out_shift), 8);
+            pOut++;
+
+        }
+
+    }
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+
+    uint16_t  i, j, k, l, m, n;
+    int       conv_out;
+    signed char in_row, in_col;
+
+    if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0)
+    {
+        /* check if the input dimension meets the constraints */
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out; j++)
+        {
+            for (k = 0; k < dim_im_out; k++)
+            {
+                conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift);
+                for (m = 0; m < dim_kernel; m++)
+                {
+                    for (n = 0; n < dim_kernel; n++)
+                    {
+                        // if-for implementation
+                        in_row = stride * j + m - padding;
+                        in_col = stride * k + n - padding;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out +=
+                                    Im_in[(in_row * dim_im_in + in_col) * ch_im_in +
+                                          l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel +
+                                                                                            n) * ch_im_in + l];
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to application */
+    return ARM_MATH_SUCCESS;
+}
+
+/**
+ * @} end of NNConv group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c
new file mode 100644
index 0000000..6dc6f0b
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c
@@ -0,0 +1,379 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_convolve_HWC_q7_fast_nonsquare.c
+ * Description:  Fast Q7 version of convolution (non-sqaure shape)
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup NNConv
+ * @{
+ */
+
+/**
+ * @brief Fast Q7 convolution function (non-sqaure shape)
+ * @param[in]       Im_in        pointer to input tensor
+ * @param[in]       dim_im_in_x  input tensor dimention x
+ * @param[in]       dim_im_in_y  input tensor dimention y
+ * @param[in]       ch_im_in     number of input tensor channels
+ * @param[in]       wt           pointer to kernel weights
+ * @param[in]       ch_im_out    number of filters, i.e., output tensor channels
+ * @param[in]       dim_kernel_x filter kernel size x
+ * @param[in]       dim_kernel_y filter kernel size y
+ * @param[in]       padding_x    padding size x
+ * @param[in]       padding_y    padding size y
+ * @param[in]       stride_x     convolution stride x
+ * @param[in]       stride_y     convolution stride y
+ * @param[in]       bias         pointer to bias
+ * @param[in]       bias_shift   amount of left-shift for bias
+ * @param[in]       out_shift    amount of right-shift for output
+ * @param[in,out]   Im_out       pointer to output tensor
+ * @param[in]       dim_im_out_x output tensor dimension x
+ * @param[in]       dim_im_out_y output tensor dimension y
+ * @param[in,out]   bufferA      pointer to buffer space for input 
+ * @param[in,out]   bufferB      pointer to buffer space for output
+ * @return     The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * This function is the version with full list of optimization tricks, but with
+ * some contraints:
+ *   ch_im_in is multiple of 4
+ *   ch_im_out is multiple of 2
+ */
+
+arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t * Im_in,
+                                              const uint16_t dim_im_in_x,
+                                              const uint16_t dim_im_in_y,
+                                              const uint16_t ch_im_in,
+                                              const q7_t * wt,
+                                              const uint16_t ch_im_out,
+                                              const uint16_t dim_kernel_x,
+                                              const uint16_t dim_kernel_y,
+                                              const uint16_t padding_x,
+                                              const uint16_t padding_y,
+                                              const uint16_t stride_x,
+                                              const uint16_t stride_y,
+                                              const q7_t * bias,
+                                              const uint16_t bias_shift,
+                                              const uint16_t out_shift,
+                                              q7_t * Im_out,
+                                              const uint16_t dim_im_out_x,
+                                              const uint16_t dim_im_out_y, 
+                                              q15_t * bufferA, 
+                                              q7_t * bufferB)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    int16_t   i_out_y, i_out_x, i_ker_y, i_ker_x;
+
+    /* -----------------------
+     *  Here we use bufferA as q15_t internally as computation are done with q15_t level
+     *  im2col are done to output in q15_t format from q7_t input
+     */
+
+    q15_t    *pBuffer = bufferA;
+    q7_t     *pOut = Im_out;
+
+    if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0)
+    {
+        /* check if the input dimension meets the constraints */
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    /*
+     *  Here we split the entire matrix into three regions depending on the padding situation
+     *    Top: i_out_y from 0 to padding - 1
+     * Middle: i_out_y from padding to dim_im_out-padding-1
+     * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1
+     */
+
+    /* top part */
+    for (i_out_y = 0; i_out_y < padding_y; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
+        {
+            /* This part implements the im2col function */
+            for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y;
+                 i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x;
+                     i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x)
+                    {
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in,
+                                                         pBuffer, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y,
+                                                  bias_shift, out_shift, bias, pOut);
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+    }
+
+    /* middle part, here we also divide the x into left, mid and right */
+    for (; i_out_y < dim_im_out_y - padding_y; i_out_y++)
+    {
+
+        /* left part */
+        for (i_out_x = 0; i_out_x < padding_x; i_out_x++)
+        {
+            /* This part implements the im2col function */
+            for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y;
+                 i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x;
+                     i_ker_x++)
+                {
+                    if (i_ker_x < 0 || i_ker_x >= dim_im_in_x)
+                    {
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in,
+                                                         pBuffer, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y,
+                                                  bias_shift, out_shift, bias, pOut);
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+
+        /* mid part */
+        for (; i_out_x < dim_im_out_x - padding_x; i_out_x++)
+        {
+            /* This part implements the im2col function */
+            for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y;
+                 i_ker_y++)
+            {
+                arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in +
+                                                 (i_ker_y * dim_im_in_x + i_out_x * stride_x - padding_x) * ch_im_in,
+                                                 pBuffer, ch_im_in * dim_kernel_x);
+                pBuffer += ch_im_in * dim_kernel_x;
+            }
+
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y,
+                                                  bias_shift, out_shift, bias, pOut);
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+
+        /* right part */
+        for (; i_out_x < dim_im_out_x; i_out_x++)
+        {
+            /* This part implements the im2col function */
+            for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y;
+                 i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x;
+                     i_ker_x++)
+                {
+                    if (i_ker_x < 0 || i_ker_x >= dim_im_in_x)
+                    {
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in,
+                                                         pBuffer, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y,
+                                                  bias_shift, out_shift, bias, pOut);
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+    }
+
+    for (; i_out_y < dim_im_out_y; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
+        {
+            /* This part implements the im2col function */
+            for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y;
+                 i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x;
+                     i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x)
+                    {
+                        /* arm_fill_q15(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
+                    } else
+                    {
+                        arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in,
+                                                         pBuffer, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y)
+            {
+                pOut =
+                    arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y,
+                                                  bias_shift, out_shift, bias, pOut);
+                /* counter reset */
+                pBuffer = bufferA;
+            }
+        }
+    }
+
+    /* check if there is left-over for compute */
+    if (pBuffer != bufferA)
+    {
+        const q7_t *pA = wt;
+        int       i;
+        for (i = 0; i < ch_im_out; i++)
+        {
+            q31_t     sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift);
+            q15_t    *pB = bufferA;
+            /* basically each time it process 4 entries */
+            uint16_t  colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2;
+
+            while (colCnt)
+            {
+
+                q31_t     inA1, inA2;
+                q31_t     inB1, inB2;
+
+                pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2);
+
+                inB1 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA1, inB1, sum);
+                inB2 = *__SIMD32(pB)++;
+                sum = __SMLAD(inA2, inB2, sum);
+
+                colCnt--;
+            }
+            colCnt = (ch_im_in * dim_kernel_y * dim_kernel_x) & 0x3;
+            while (colCnt)
+            {
+                q7_t      inA1 = *pA++;
+                q15_t     inB1 = *pB++;
+                sum += inA1 * inB1;
+                colCnt--;
+            }
+            *pOut = (q7_t) __SSAT((sum >> out_shift), 8);
+            pOut++;
+
+        }
+
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    int       i, j, k, l, m, n;
+    int       conv_out;
+    int       in_row, in_col;
+
+    if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0)
+    {
+        /* check if the input dimension meets the constraints */
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    for (i = 0; i < ch_im_out; i++)
+    {
+        for (j = 0; j < dim_im_out_y; j++)
+        {
+            for (k = 0; k < dim_im_out_x; k++)
+            {
+                conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift);
+                for (m = 0; m < dim_kernel_y; m++)
+                {
+                    for (n = 0; n < dim_kernel_x; n++)
+                    {
+                        /* if-for implementation */
+                        in_row = stride_y * j + m - padding_y;
+                        in_col = stride_x * k + n - padding_x;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
+                        {
+                            for (l = 0; l < ch_im_in; l++)
+                            {
+                                conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] *
+                                    wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + l];      
+                            }
+                        }
+                    }
+                }
+                Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to application */
+    return ARM_MATH_SUCCESS;
+}
+
+/**
+ * @} end of NNConv group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c
new file mode 100644
index 0000000..705fa6a
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c
@@ -0,0 +1,418 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_depthwise_separable_conv_HWC_q7.c
+ * Description:  Q7 depthwise separable convolution function
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup NNConv
+ * @{
+ */
+
+/**
+ * @brief Q7 depthwise separable convolution function
+ * @param[in]       Im_in       pointer to input tensor
+ * @param[in]       dim_im_in   input tensor dimention
+ * @param[in]       ch_im_in    number of input tensor channels
+ * @param[in]       wt          pointer to kernel weights
+ * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
+ * @param[in]       dim_kernel  filter kernel size
+ * @param[in]       padding     padding sizes
+ * @param[in]       stride      convolution stride
+ * @param[in]       bias        pointer to bias
+ * @param[in]       bias_shift  amount of left-shift for bias
+ * @param[in]       out_shift   amount of right-shift for output
+ * @param[in,out]   Im_out      pointer to output tensor
+ * @param[in]       dim_im_out  output tensor dimension
+ * @param[in,out]   bufferA     pointer to buffer space for input
+ * @param[in,out]   bufferB     pointer to buffer space for output
+ * @return     The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ *
+ * Buffer size:
+ *
+ * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
+ *
+ * bufferB size: 0
+ *
+ * Input dimension constraints:
+ *
+ * ch_im_in equals ch_im_out
+ *
+ * Implementation:
+ * There are 3 nested loop here:
+ * Inner loop: calculate each output value with MAC instruction over an accumulator
+ * Mid   loop: loop over different output channel
+ * Outer loop: loop over different output (x, y)
+ */
+
+arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t * Im_in,
+                                               const uint16_t dim_im_in,
+                                               const uint16_t ch_im_in,
+                                               const q7_t * wt,
+                                               const uint16_t ch_im_out,
+                                               const uint16_t dim_kernel,
+                                               const uint16_t padding,
+                                               const uint16_t stride,
+                                               const q7_t * bias,
+                                               const uint16_t bias_shift,
+                                               const uint16_t out_shift,
+                                               q7_t * Im_out, 
+                                               const uint16_t dim_im_out, 
+                                               q15_t * bufferA, 
+                                               q7_t * bufferB)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    int16_t   i_out_y, i_out_x;
+    int16_t   i_ker_y, i_ker_x;
+    q7_t     *colBuffer = (q7_t *) bufferA;
+    q7_t     *pBuffer = colBuffer;
+    const q7_t *pBias = bias;
+    q7_t     *pOut = Im_out;
+    uint16_t  rowCnt;
+    uint16_t  row_shift;
+
+    /* do some checking here, basically ch_im_in == ch_im_out */
+    if (ch_im_in != ch_im_out)
+    {
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
+        {
+            /* we first do im2col here */
+            for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
+                    {
+                        /* arm_fill_q7(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, ch_im_in);
+                    } else
+                    {
+                        /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */
+                        memcpy(pBuffer, (q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            /* we will do the computation here for each channel */
+            rowCnt = ch_im_out >> 2;
+            row_shift = 0;
+            pBias = bias;
+
+            while (rowCnt)
+            {
+                q31_t     sum =  ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+                q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+                q31_t     sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+                q31_t     sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+                uint16_t  colCnt = (dim_kernel * dim_kernel) >> 1;
+                q7_t     *pB = colBuffer + row_shift;
+                const q7_t *pA = wt + row_shift;
+                row_shift += 4;
+
+#ifdef USE_INTRINSIC
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+                while (colCnt)
+                {
+                    q31_t     inA1, inA2, inB1, inB2, opA, opB;
+
+                    inB1 = *__SIMD32(pB);
+                    pB += ch_im_in;
+                    opB = *__SIMD32(pB);
+                    pB += ch_im_in;
+                    inB2 = __PKHTB(opB, inB1, 16);
+                    inB1 = __PKHBT(inB1, opB, 16);
+                    inA1 = *__SIMD32(pA);
+                    pA += ch_im_in;
+                    opB = *__SIMD32(pA);
+                    pA += ch_im_in;
+                    inA2 = __PKHTB(opB, inA1, 16);
+                    inA1 = __PKHBT(inA1, opB, 16);
+                    opA = __SXTB16(inA1);
+                    opB = __SXTB16(inB1);
+                    sum = __SMLAD(opA, opB, sum);
+                    opA = __SXTB16(__ROR(inA1, 8));
+                    opB = __SXTB16(__ROR(inB1, 8));
+                    sum2 = __SMLAD(opA, opB, sum2);
+                    opA = __SXTB16(inA2);
+                    opB = __SXTB16(inB2);
+                    sum3 = __SMLAD(opA, opB, sum3);
+                    opA = __SXTB16(__ROR(inA2, 8));
+                    opB = __SXTB16(__ROR(inB2, 8));
+                    sum4 = __SMLAD(opA, opB, sum4);
+                    colCnt--;
+                }
+#else
+
+                while (colCnt)
+                {
+                    q31_t     inA1, inA2, inB1, inB2, opA, opB;
+
+                    inB1 = *__SIMD32(pB);
+                    pB += ch_im_in;
+                    opB = *__SIMD32(pB);
+                    pB += ch_im_in;
+                    inB2 = __PKHBT(opB, inB1, 16);
+                    inB1 = __PKHTB(inB1, opB, 16);
+                    inA1 = *__SIMD32(pA);
+                    pA += ch_im_in;
+                    opB = *__SIMD32(pA);
+                    pA += ch_im_in;
+                    inA2 = __PKHBT(opB, inA1, 16);
+                    inA1 = __PKHTB(inA1, opB, 16);
+                    opA = __SXTB16(inA1);
+                    opB = __SXTB16(inB1);
+                    sum2 = __SMLAD(opA, opB, sum2);
+                    opA = __SXTB16(__ROR(inA1, 8));
+                    opB = __SXTB16(__ROR(inB1, 8));
+                    sum = __SMLAD(opA, opB, sum);
+                    opA = __SXTB16(inA2);
+                    opB = __SXTB16(inB2);
+                    sum4 = __SMLAD(opA, opB, sum4);
+                    opA = __SXTB16(__ROR(inA2, 8));
+                    opB = __SXTB16(__ROR(inB2, 8));
+                    sum3 = __SMLAD(opA, opB, sum3);
+                    colCnt--;
+                }
+
+#endif                          /* ARM_MATH_BIG_ENDIAN */
+
+#else
+
+#ifndef ARM_MATH_BIG_ENDIAN
+                /*
+                 *   r0    r1    r2    r3    r4   r5
+                 *  inA1, inA2, inB1, inB2, opA, opB
+                 */
+
+                asm volatile ("COL_LOOP_%=:\n"
+                              "ldr.w r2, [%[pB], #0]\n"
+                              "add.w %[pB], %[pB], %[ch_im_in]\n"
+                              "ldr.w r5, [%[pB], #0]\n"
+                              "add.w %[pB], %[pB], %[ch_im_in]\n"
+                              "pkhtb r3, r5, r2, ASR #16\n"
+                              "pkhbt r2, r2, r5, LSL #16\n"
+                              "ldr.w r0, [%[pA], #0]\n"
+                              "add.w %[pA], %[pA], %[ch_im_in]\n"
+                              "ldr.w r5, [%[pA], #0]\n"
+                              "add.w %[pA], %[pA], %[ch_im_in]\n"
+                              "pkhtb r1, r5, r0, ASR #16\n"
+                              "pkhbt r0, r0, r5, LSL #16\n"
+                              "sxtb16 r4, r0\n"
+                              "sxtb16 r5, r2\n"
+                              "smlad %[sum], r4, r5, %[sum]\n"
+                              "mov.w r4, r0, ror #8\n"
+                              "mov.w r5, r2, ror #8\n"
+                              "sxtb16 r4, r4\n"
+                              "sxtb16 r5, r5\n"
+                              "smlad %[sum2], r4, r5, %[sum2]\n"
+                              "sxtb16 r4, r1\n"
+                              "sxtb16 r5, r3\n"
+                              "smlad %[sum3], r4, r5, %[sum3]\n"
+                              "mov.w r4, r1, ror #8\n"
+                              "mov.w r5, r3, ror #8\n"
+                              "sxtb16 r4, r4\n"
+                              "sxtb16 r5, r5\n"
+                              "smlad %[sum4], r4, r5, %[sum4]\n"
+                              "subs %[colCnt], #1\n"
+                              "bne COL_LOOP_%=\n":[sum]
+                              "+r"(sum),[sum2] "+r"(sum2),
+                              [sum3] "+r"(sum3),
+                              [sum4] "+r"(sum4),[pB] "+r"(pB),
+                              [pA] "+r"(pA):[colCnt]
+                              "r"(colCnt),[ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5");
+#else
+                /*
+                 *  r0    r1    r2    r3    r4   r5
+                 * inA1, inA2, inB1, inB2, opA, opB
+                 */
+                asm volatile ("COL_LOOP_%=:\n"
+                              "ldr.w r2, [%[pB], #0]\n"
+                              "add.w %[pB], %[pB], %[ch_im_in]\n"
+                              "ldr.w r5, [%[pB], #0]\n"
+                              "add.w %[pB], %[pB], %[ch_im_in]\n"
+                              "pkhbt r3, r5, r2, LSL #16\n"
+                              "pkhtb r2, r2, r5, ASR #16\n"
+                              "ldr.w r0, [%[pA], #0]\n"
+                              "add.w %[pA], %[pA], %[ch_im_in]\n"
+                              "ldr.w r5, [%[pA], #0]\n"
+                              "add.w %[pA], %[pA], %[ch_im_in]\n"
+                              "pkhbt r1, r5, r0, LSL #16\n"
+                              "pkhtb r0, r0, r5, ASR #16\n"
+                              "sxtb16 r4, r0\n"
+                              "sxtb16 r5, r2\n"
+                              "smlad %[sum2], r4, r5, %[sum2]\n"
+                              "mov.w r4, r0, ror #8\n"
+                              "mov.w r5, r2, ror #8\n"
+                              "sxtb16 r4, r4\n"
+                              "sxtb16 r5, r5\n"
+                              "smlad %[sum], r4, r5, %[sum]\n"
+                              "sxtb16 r4, r1\n"
+                              "sxtb16 r5, r3\n"
+                              "smlad %[sum4], r4, r5, %[sum4]\n"
+                              "mov.w r4, r1, ror #8\n"
+                              "mov.w r5, r3, ror #8\n"
+                              "sxtb16 r4, r4\n"
+                              "sxtb16 r5, r5\n"
+                              "smlad %[sum3], r4, r5, %[sum3]\n"
+                              "subs %[colCnt], #1\n"
+                              "bne COL_LOOP_%=\n":[sum]
+                              "+r"(sum),[sum2] "+r"(sum2),
+                              [sum3] "+r"(sum3),
+                              [sum4] "+r"(sum4),[pB] "+r"(pB),
+                              [pA] "+r"(pA):[colCnt]
+                              "r"(colCnt),[ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5");
+
+#endif                          /* ARM_MATH_BIG_ENDIAN */
+
+#endif                          /* USE_INTRINSIC */
+
+                colCnt = (dim_kernel * dim_kernel) & 0x1;
+                while (colCnt)
+                {
+                    union arm_nnword inA, inB;
+                    inA.word = *__SIMD32(pA);
+                    pA += ch_im_in;
+                    inB.word = *__SIMD32(pB);
+                    pB += ch_im_in;
+                    sum += inA.bytes[0] * inB.bytes[0];
+                    sum2 += inA.bytes[1] * inB.bytes[1];
+                    sum3 += inA.bytes[2] * inB.bytes[2];
+                    sum4 += inA.bytes[3] * inB.bytes[3];
+                    colCnt--;
+                }
+
+                *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
+                *pOut++ = (q7_t) __SSAT((sum2 >> out_shift), 8);
+                *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8);
+                *pOut++ = (q7_t) __SSAT((sum4 >> out_shift), 8);
+
+                rowCnt--;
+            }
+
+            rowCnt = ch_im_out & 0x3;
+            while (rowCnt)
+            {
+                q7_t     *pB = colBuffer + row_shift;
+                const q7_t *pA = wt + row_shift;
+                q31_t     sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+                uint16_t  colCnt = (dim_kernel * dim_kernel);
+
+                row_shift += 1;
+
+                while (colCnt)
+                {
+                    q7_t      A1 = *pA;
+                    q7_t      B1 = *pB;
+                    pA += ch_im_in;
+                    pB += ch_im_in;
+                    sum += A1 * B1;
+
+                    colCnt--;
+                }
+                *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
+                rowCnt--;
+            }
+
+            /* clear counter and pointers */
+            pBuffer = colBuffer;
+        }
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    int       i_out_y, i_out_x, i_ch_out, i_ker_x, i_ker_y;
+    int       conv_out;
+
+    /* do some checking here, basically ch_im_in == ch_im_out */
+    if (ch_im_in != ch_im_out)
+    {
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
+        {
+            for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++)
+            {
+                // for each output
+                conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift);
+                for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++)
+                {
+                    for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++)
+                    {
+                        int       in_row = stride * i_out_y + i_ker_y - padding;
+                        int       in_col = stride * i_out_x + i_ker_x - padding;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
+                        {
+                            conv_out +=
+                                Im_in[(in_row *
+                                       dim_im_in +
+                                       in_col) *
+                                      ch_im_in +
+                                      i_ch_out] * wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out];
+                        }
+                    }
+                }
+                Im_out[(i_out_y * dim_im_out +
+                        i_out_x) * ch_im_out + i_ch_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to application */
+    return ARM_MATH_SUCCESS;
+
+}
+
+/**
+ * @} end of NNConv group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c
new file mode 100644
index 0000000..5989304
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_depthwise_separable_conv_HWC_q7_nonsquare.c
+ * Description:  Q7 depthwise separable convolution function (non-square shape)
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup NNConv
+ * @{
+ */
+
+/**
+ * @brief Q7 depthwise separable convolution function (non-square shape)
+ * @param[in]       Im_in         pointer to input tensor
+ * @param[in]       dim_im_in_x   input tensor dimention x
+ * @param[in]       dim_im_in_y   input tensor dimention y
+ * @param[in]       ch_im_in      number of input tensor channels
+ * @param[in]       wt            pointer to kernel weights
+ * @param[in]       ch_im_out     number of filters, i.e., output tensor channels
+ * @param[in]       dim_kernel_x  filter kernel size x
+ * @param[in]       dim_kernel_y  filter kernel size y
+ * @param[in]       padding_x     padding sizes x
+ * @param[in]       padding_y     padding sizes y
+ * @param[in]       stride_x      convolution stride x
+ * @param[in]       stride_y      convolution stride y
+ * @param[in]       bias          pointer to bias
+ * @param[in]       bias_shift    amount of left-shift for bias
+ * @param[in]       out_shift     amount of right-shift for output
+ * @param[in,out]   Im_out        pointer to output tensor
+ * @param[in]       dim_im_out_x  output tensor dimension x
+ * @param[in]       dim_im_out_y  output tensor dimension y
+ * @param[in,out]   bufferA       pointer to buffer space for input 
+ * @param[in,out]   bufferB       pointer to buffer space for output
+ * @return     The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * This function is the version with full list of optimization tricks, but with
+ * some contraints:
+ *   ch_im_in is multiple of 2
+ *   ch_im_out is multiple of 2
+ */
+
+arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t * Im_in,
+                                                         const uint16_t dim_im_in_x,
+                                                         const uint16_t dim_im_in_y,
+                                                         const uint16_t ch_im_in,
+                                                         const q7_t * wt,
+                                                         const uint16_t ch_im_out,
+                                                         const uint16_t dim_kernel_x,
+                                                         const uint16_t dim_kernel_y,
+                                                         const uint16_t padding_x,
+                                                         const uint16_t padding_y,
+                                                         const uint16_t stride_x,
+                                                         const uint16_t stride_y,
+                                                         const q7_t * bias,
+                                                         const uint16_t bias_shift,
+                                                         const uint16_t out_shift,
+                                                         q7_t * Im_out,
+                                                         const uint16_t dim_im_out_x,
+                                                         const uint16_t dim_im_out_y, 
+                                                         q15_t * bufferA, 
+                                                         q7_t * bufferB)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+/*
+ * Implementation:
+ * There are 3 nested loop here:
+ * Inner loop: calculate each output value with MAC instruction over an accumulator
+ * Mid   loop: loop over different output channel
+ * Outer loop: loop over different output (x, y)
+ *
+ */
+
+    int16_t   i_out_y, i_out_x;
+    int16_t   i_ker_y, i_ker_x;
+    q7_t     *colBuffer = (q7_t *) bufferA;
+    q7_t     *pBuffer = colBuffer;
+    const q7_t *pBias = bias;
+    q7_t     *pOut = Im_out;
+    uint16_t  rowCnt;
+    uint16_t  row_shift;
+
+    /* do some checking here, basically ch_im_in == ch_im_out */
+    if (ch_im_in != ch_im_out)
+    {
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
+        {
+            /* we first do im2col here */
+            for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y;
+                 i_ker_y++)
+            {
+                for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x;
+                     i_ker_x++)
+                {
+                    if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x)
+                    {
+                        /* arm_fill_q7(0, pBuffer, ch_im_in); */
+                        memset(pBuffer, 0, ch_im_in);
+                    } else
+                    {
+                        /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */
+                        memcpy(pBuffer, (q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, ch_im_in);
+                    }
+                    pBuffer += ch_im_in;
+                }
+            }
+
+            /* we will do the computation here for each channel */
+            rowCnt = ch_im_out >> 2;
+            row_shift = 0;
+            pBias = bias;
+
+            while (rowCnt)
+            {
+                q31_t     sum =  ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+                q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+                q31_t     sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+                q31_t     sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+                uint16_t  colCnt = (dim_kernel_x * dim_kernel_y) >> 1;
+                q7_t     *pB = colBuffer + row_shift;
+                const q7_t *pA = wt + row_shift;
+                row_shift += 4;
+
+#ifdef USE_INTRINSIC
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+                while (colCnt)
+                {
+                    q31_t     inA1, inA2, inB1, inB2, opA, opB;
+
+                    inB1 = *__SIMD32(pB);
+                    pB += ch_im_in;
+                    opB = *__SIMD32(pB);
+                    pB += ch_im_in;
+                    inB2 = __PKHTB(opB, inB1, 16);
+                    inB1 = __PKHBT(inB1, opB, 16);
+                    inA1 = *__SIMD32(pA);
+                    pA += ch_im_in;
+                    opB = *__SIMD32(pA);
+                    pA += ch_im_in;
+                    inA2 = __PKHTB(opB, inA1, 16);
+                    inA1 = __PKHBT(inA1, opB, 16);
+                    opA = __SXTB16(inA1);
+                    opB = __SXTB16(inB1);
+                    sum = __SMLAD(opA, opB, sum);
+                    opA = __SXTB16(__ROR(inA1, 8));
+                    opB = __SXTB16(__ROR(inB1, 8));
+                    sum2 = __SMLAD(opA, opB, sum2);
+                    opA = __SXTB16(inA2);
+                    opB = __SXTB16(inB2);
+                    sum3 = __SMLAD(opA, opB, sum3);
+                    opA = __SXTB16(__ROR(inA2, 8));
+                    opB = __SXTB16(__ROR(inB2, 8));
+                    sum4 = __SMLAD(opA, opB, sum4);
+                    colCnt--;
+                }
+#else
+
+                while (colCnt)
+                {
+                    q31_t     inA1, inA2, inB1, inB2, opA, opB;
+
+                    inB1 = *__SIMD32(pB);
+                    pB += ch_im_in;
+                    opB = *__SIMD32(pB);
+                    pB += ch_im_in;
+                    inB2 = __PKHBT(opB, inB1, 16);
+                    inB1 = __PKHTB(inB1, opB, 16);
+                    inA1 = *__SIMD32(pA);
+                    pA += ch_im_in;
+                    opB = *__SIMD32(pA);
+                    pA += ch_im_in;
+                    inA2 = __PKHBT(opB, inA1, 16);
+                    inA1 = __PKHTB(inA1, opB, 16);
+                    opA = __SXTB16(inA1);
+                    opB = __SXTB16(inB1);
+                    sum2 = __SMLAD(opA, opB, sum2);
+                    opA = __SXTB16(__ROR(inA1, 8));
+                    opB = __SXTB16(__ROR(inB1, 8));
+                    sum = __SMLAD(opA, opB, sum);
+                    opA = __SXTB16(inA2);
+                    opB = __SXTB16(inB2);
+                    sum4 = __SMLAD(opA, opB, sum4);
+                    opA = __SXTB16(__ROR(inA2, 8));
+                    opB = __SXTB16(__ROR(inB2, 8));
+                    sum3 = __SMLAD(opA, opB, sum3);
+                    colCnt--;
+                }
+
+#endif                          /* ARM_MATH_BIG_ENDIAN */
+
+#else
+
+#ifndef ARM_MATH_BIG_ENDIAN
+                //  r0    r1    r2    r3    r4   r5
+                // inA1, inA2, inB1, inB2, opA, opB
+                asm volatile ("COL_LOOP:\n"
+                              "ldr.w r2, [%[pB], #0]\n"
+                              "add.w %[pB], %[pB], %[ch_im_in]\n"
+                              "ldr.w r5, [%[pB], #0]\n"
+                              "add.w %[pB], %[pB], %[ch_im_in]\n"
+                              "pkhtb r3, r5, r2, ASR #16\n"
+                              "pkhbt r2, r2, r5, LSL #16\n"
+                              "ldr.w r0, [%[pA], #0]\n"
+                              "add.w %[pA], %[pA], %[ch_im_in]\n"
+                              "ldr.w r5, [%[pA], #0]\n"
+                              "add.w %[pA], %[pA], %[ch_im_in]\n"
+                              "pkhtb r1, r5, r0, ASR #16\n"
+                              "pkhbt r0, r0, r5, LSL #16\n"
+                              "sxtb16 r4, r0\n"
+                              "sxtb16 r5, r2\n"
+                              "smlad %[sum], r4, r5, %[sum]\n"
+                              "mov.w r4, r0, ror #8\n"
+                              "mov.w r5, r2, ror #8\n"
+                              "sxtb16 r4, r4\n"
+                              "sxtb16 r5, r5\n"
+                              "smlad %[sum2], r4, r5, %[sum2]\n"
+                              "sxtb16 r4, r1\n"
+                              "sxtb16 r5, r3\n"
+                              "smlad %[sum3], r4, r5, %[sum3]\n"
+                              "mov.w r4, r1, ror #8\n"
+                              "mov.w r5, r3, ror #8\n"
+                              "sxtb16 r4, r4\n"
+                              "sxtb16 r5, r5\n"
+                              "smlad %[sum4], r4, r5, %[sum4]\n"
+                              "subs %[colCnt], #1\n"
+                              "bne COL_LOOP\n":[sum] "+r"(sum),[sum2] "+r"(sum2),[sum3] "+r"(sum3),
+                              [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt),
+                              [ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5");
+#else
+                //  r0    r1    r2    r3    r4   r5
+                // inA1, inA2, inB1, inB2, opA, opB
+                asm volatile ("COL_LOOP:\n"
+                              "ldr.w r2, [%[pB], #0]\n"
+                              "add.w %[pB], %[pB], %[ch_im_in]\n"
+                              "ldr.w r5, [%[pB], #0]\n"
+                              "add.w %[pB], %[pB], %[ch_im_in]\n"
+                              "pkhbt r3, r5, r2, LSL #16\n"
+                              "pkhtb r2, r2, r5, ASR #16\n"
+                              "ldr.w r0, [%[pA], #0]\n"
+                              "add.w %[pA], %[pA], %[ch_im_in]\n"
+                              "ldr.w r5, [%[pA], #0]\n"
+                              "add.w %[pA], %[pA], %[ch_im_in]\n"
+                              "pkhbt r1, r5, r0, LSL #16\n"
+                              "pkhtb r0, r0, r5, ASR #16\n"
+                              "sxtb16 r4, r0\n"
+                              "sxtb16 r5, r2\n"
+                              "smlad %[sum2], r4, r5, %[sum2]\n"
+                              "mov.w r4, r0, ror #8\n"
+                              "mov.w r5, r2, ror #8\n"
+                              "sxtb16 r4, r4\n"
+                              "sxtb16 r5, r5\n"
+                              "smlad %[sum], r4, r5, %[sum]\n"
+                              "sxtb16 r4, r1\n"
+                              "sxtb16 r5, r3\n"
+                              "smlad %[sum4], r4, r5, %[sum4]\n"
+                              "mov.w r4, r1, ror #8\n"
+                              "mov.w r5, r3, ror #8\n"
+                              "sxtb16 r4, r4\n"
+                              "sxtb16 r5, r5\n"
+                              "smlad %[sum3], r4, r5, %[sum3]\n"
+                              "subs %[colCnt], #1\n"
+                              "bne COL_LOOP\n":[sum] "+r"(sum),[sum2] "+r"(sum2),[sum3] "+r"(sum3),
+                              [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt),
+                              [ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5");
+#endif                          /*ARM_MATH_BIG_ENDIAN */
+
+#endif                          /* USE_INTRINSIC */
+
+                colCnt = (dim_kernel_x * dim_kernel_y) & 0x1;
+                while (colCnt)
+                {
+                    union arm_nnword inA, inB;
+                    inA.word = *__SIMD32(pA);
+                    pA += ch_im_in;
+                    inB.word = *__SIMD32(pB);
+                    pB += ch_im_in;
+                    sum += inA.bytes[0] * inB.bytes[0];
+                    sum2 += inA.bytes[1] * inB.bytes[1];
+                    sum3 += inA.bytes[2] * inB.bytes[2];
+                    sum4 += inA.bytes[3] * inB.bytes[3];
+                    colCnt--;
+                }
+
+                *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
+                *pOut++ = (q7_t) __SSAT((sum2 >> out_shift), 8);
+                *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8);
+                *pOut++ = (q7_t) __SSAT((sum4 >> out_shift), 8);
+
+                rowCnt--;
+            }
+
+            rowCnt = ch_im_out & 0x3;
+            while (rowCnt)
+            {
+                q7_t     *pB = colBuffer + row_shift;
+                const q7_t *pA = wt + row_shift;
+                q31_t     sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+                uint16_t  colCnt = (dim_kernel_x * dim_kernel_y);
+
+                row_shift += 1;
+
+                while (colCnt)
+                {
+                    q7_t      A1 = *pA;
+                    q7_t      B1 = *pB;
+                    pA += ch_im_in;
+                    pB += ch_im_in;
+                    sum += A1 * B1;
+
+                    colCnt--;
+                }
+                *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
+                rowCnt--;
+            }
+
+            // clear counter and pointers
+            pBuffer = colBuffer;
+        }
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    int       i_out_y, i_out_x, i_ch_out;
+    int       i_ker_y, i_ker_x; 
+
+    /* do some checking here, basically ch_im_in == ch_im_out */
+    if (ch_im_in != ch_im_out)
+    {
+        return ARM_MATH_SIZE_MISMATCH;
+    }
+
+    for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++)
+    {
+        for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
+        {
+            for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++)
+            {
+                // for each output 
+                int       conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift);
+                for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++)
+                {
+                    for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++)
+                    {
+                        int       in_row = stride_y * i_out_y + i_ker_y - padding_y;
+                        int       in_col = stride_x * i_out_x + i_ker_x - padding_x;
+                        if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
+                        {
+                            conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] *                        
+                                wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out];
+                        }
+                    }
+                }
+                Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] =
+                    (q7_t) __SSAT((conv_out >> out_shift), 8);
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+
+    /* Return to application */
+    return ARM_MATH_SUCCESS;
+
+}
+
+/**
+ * @} end of NNConv group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c
new file mode 100644
index 0000000..24ab412
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nn_mat_mult_kernel_q7_q15.c
+ * Description:  Matrix-multiplication function for convolution
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+  /**
+   * @brief Matrix-multiplication function for convolution
+   * @param[in]       pA          pointer to operand A
+   * @param[in]       pInBuffer   pointer to operand B, always conssists of 2 vectors
+   * @param[in]       ch_im_out   numRow of A
+   * @param[in]       numCol_A    numCol of A
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        the bias
+   * @param[in,out]   pOut        pointer to output
+   * @return     The function returns the incremented output pointer
+   *
+   * @details
+   *
+   * This function does the matrix multiplication with weight matrix
+   * and 2 columns from im2col. 
+   */
+
+q7_t     *arm_nn_mat_mult_kernel_q7_q15(const q7_t * pA,
+                                        const q15_t * pInBuffer,
+                                        const uint16_t ch_im_out,
+                                        const uint16_t numCol_A,
+                                        const uint16_t bias_shift,
+                                        const uint16_t out_shift, 
+                                        const q7_t * bias, 
+                                        q7_t * pOut)
+{
+#if defined (ARM_MATH_DSP)
+    /* set up the second output pointers */
+    q7_t     *pOut2 = pOut + ch_im_out;
+    const q7_t *pBias = bias;
+
+    uint16_t  rowCnt = ch_im_out >> 1;
+    /* this loop over rows in A */
+    while (rowCnt)
+    {
+        /* setup pointers for B */
+        const q15_t *pB = pInBuffer;
+        const q15_t *pB2 = pB + numCol_A;
+
+        /* align the second pointer for A */
+        const q7_t *pA2 = pA + numCol_A;
+
+        /* init the sum with bias */
+        q31_t     sum =  ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum3 = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        uint16_t  colCnt = numCol_A >> 2;
+        /* accumulate over the vector */
+        while (colCnt)
+        {
+            q31_t     inA11, inA12, inA21, inA22;
+            q31_t     inB1 = *__SIMD32(pB)++;
+            q31_t     inB2 = *__SIMD32(pB2)++;
+
+            pA = (q7_t *) read_and_pad((void *)pA, &inA11, &inA12);
+            pA2 = (q7_t *) read_and_pad((void *)pA2, &inA21, &inA22);
+
+            sum = __SMLAD(inA11, inB1, sum);
+            sum2 = __SMLAD(inA11, inB2, sum2);
+            sum3 = __SMLAD(inA21, inB1, sum3);
+            sum4 = __SMLAD(inA21, inB2, sum4);
+
+            inB1 = *__SIMD32(pB)++;
+            inB2 = *__SIMD32(pB2)++;
+
+            sum = __SMLAD(inA12, inB1, sum);
+            sum2 = __SMLAD(inA12, inB2, sum2);
+            sum3 = __SMLAD(inA22, inB1, sum3);
+            sum4 = __SMLAD(inA22, inB2, sum4);
+
+            colCnt--;
+        }                       /* while over colCnt */
+        colCnt = numCol_A & 0x3;
+        while (colCnt)
+        {
+            q7_t      inA1 = *pA++;
+            q15_t     inB1 = *pB++;
+            q7_t      inA2 = *pA2++;
+            q15_t     inB2 = *pB2++;
+
+            sum += inA1 * inB1;
+            sum2 += inA1 * inB2;
+            sum3 += inA2 * inB1;
+            sum4 += inA2 * inB2;
+            colCnt--;
+        }                       /* while over colCnt */
+        *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
+        *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8);
+        *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8);
+        *pOut2++ = (q7_t) __SSAT((sum4 >> out_shift), 8);
+
+        /* skip the row computed with A2 */
+        pA += numCol_A;
+        rowCnt--;
+    }                           /* for over ch_im_out */
+
+    /* compute left-over row if any */
+    if (ch_im_out & 0x1)
+    {
+        /* setup pointers for B */
+        const q15_t *pB = pInBuffer;
+        const q15_t *pB2 = pB + numCol_A;
+
+        /* load the bias */
+        q31_t     sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        uint16_t  colCnt = numCol_A >> 2;
+        while (colCnt)
+        {
+            q31_t     inA11, inA12;
+            q31_t     inB1 = *__SIMD32(pB)++;
+            q31_t     inB2 = *__SIMD32(pB2)++;
+
+            pA = (q7_t *) read_and_pad((void *)pA, &inA11, &inA12);
+
+            sum = __SMLAD(inA11, inB1, sum);
+            sum2 = __SMLAD(inA11, inB2, sum2);
+
+            inB1 = *__SIMD32(pB)++;
+            inB2 = *__SIMD32(pB2)++;
+            sum = __SMLAD(inA12, inB1, sum);
+            sum2 = __SMLAD(inA12, inB2, sum2);
+
+            colCnt--;
+        }
+        colCnt = numCol_A & 0x3;
+        while (colCnt)
+        {
+            q7_t      inA1 = *pA++;
+            q15_t     inB1 = *pB++;
+            q15_t     inB2 = *pB2++;
+
+            sum += inA1 * inB1;
+            sum2 += inA1 * inB2;
+            colCnt--;
+        }
+
+        *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
+        *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8);
+    }
+
+    pOut += ch_im_out;
+
+    /* return the new output pointer with offset */
+    return pOut;
+#else
+    /* To be completed */
+    return NULL;
+#endif                          /* ARM_MATH_DSP */
+
+}
diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c
new file mode 100644
index 0000000..36af21a
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nn_mat_mult_kernel_q7_q15_reordered.c
+ * Description:  Matrix-multiplication function for convolution with reordered columns
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnfunctions.h"
+#include "arm_math.h"
+
+  /**
+   * @brief Matrix-multiplication function for convolution with reordered columns
+   * @param[in]       pA          pointer to operand A
+   * @param[in]       pInBuffer   pointer to operand B, always conssists of 2 vectors
+   * @param[in]       ch_im_out   numRow of A
+   * @param[in]       numCol_A    numCol of A
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        the bias
+   * @param[in,out]   pOut        pointer to output
+   * @return     The function returns the incremented output pointer
+   *
+   * @details
+   *
+   * This function assumes that data in pInBuffer are reordered
+   */
+
+q7_t     *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t * pA,
+                                                  const q15_t * pInBuffer,
+                                                  const uint16_t ch_im_out,
+                                                  const uint16_t numCol_A,
+                                                  const uint16_t bias_shift,
+                                                  const uint16_t out_shift, 
+                                                  const q7_t * bias, 
+                                                  q7_t * pOut)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* set up the second output pointers */
+    q7_t     *pOut2 = pOut + ch_im_out;
+    int       i;
+
+    /* this loop over rows in A */
+    for (i = 0; i < ch_im_out; i += 2)
+    {
+        /* setup pointers for B */
+        const q15_t *pB = pInBuffer;
+        const q15_t *pB2 = pB + numCol_A;
+
+        /* align the second pointer for A */
+        const q7_t *pA2 = pA + numCol_A;
+
+        /* init the sum with bias */
+        q31_t     sum =  ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum3 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum4 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift);
+
+        uint16_t  colCnt = numCol_A >> 2;
+        /* accumulate over the vector */
+        while (colCnt)
+        {
+            q31_t     inA11, inA12, inA21, inA22;
+            q31_t     inB1 = *__SIMD32(pB)++;
+            q31_t     inB2 = *__SIMD32(pB2)++;
+
+            pA = (q7_t *) read_and_pad_reordered((void *)pA, &inA11, &inA12);
+            pA2 = (q7_t *) read_and_pad_reordered((void *)pA2, &inA21, &inA22);
+
+            sum = __SMLAD(inA11, inB1, sum);
+            sum2 = __SMLAD(inA11, inB2, sum2);
+            sum3 = __SMLAD(inA21, inB1, sum3);
+            sum4 = __SMLAD(inA21, inB2, sum4);
+
+            inB1 = *__SIMD32(pB)++;
+            inB2 = *__SIMD32(pB2)++;
+
+            sum = __SMLAD(inA12, inB1, sum);
+            sum2 = __SMLAD(inA12, inB2, sum2);
+            sum3 = __SMLAD(inA22, inB1, sum3);
+            sum4 = __SMLAD(inA22, inB2, sum4);
+
+            colCnt--;
+        }                       /* while over colCnt */
+        colCnt = numCol_A & 0x3;
+        while (colCnt)
+        {
+            q7_t      inA1 = *pA++;
+            q15_t     inB1 = *pB++;
+            q7_t      inA2 = *pA2++;
+            q15_t     inB2 = *pB2++;
+
+            sum += inA1 * inB1;
+            sum2 += inA1 * inB2;
+            sum3 += inA2 * inB1;
+            sum4 += inA2 * inB2;
+            colCnt--;
+        }                       /* while over colCnt */
+        *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
+        *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8);
+        *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8);
+        *pOut2++ = (q7_t) __SSAT((sum4 >> out_shift), 8);
+
+        /* skip the row computed with A2 */
+        pA += numCol_A;
+    }                           /* for over ch_im_out */
+
+    pOut += ch_im_out;
+
+    /* return the new output pointer with offset */
+    return pOut;
+#else
+    /* To be completed */
+    return NULL;
+#endif                          /* ARM_MATH_DSP */
+}
diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c
new file mode 100644
index 0000000..bb9a091
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_fully_connected_mat_q7_vec_q15.c
+ * Description:  Mixed Q15-Q7 fully-connected layer function
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup FC
+ * @{
+ */
+
+  /**
+   * @brief Mixed Q15-Q7 fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * vec_buffer size: 0
+   *
+   *  Q7_Q15 version of the fully connected layer
+   *
+   *  Weights are in q7_t and Activations are in q15_t
+   *
+   */
+
+arm_status
+arm_fully_connected_mat_q7_vec_q15(const q15_t * pV,
+                                   const q7_t * pM,
+                                   const uint16_t dim_vec,
+                                   const uint16_t num_of_rows,
+                                   const uint16_t bias_shift,
+                                   const uint16_t out_shift, 
+                                   const q7_t * bias, 
+                                   q15_t * pOut, 
+                                   q15_t * vec_buffer)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    const q7_t *pB = pM;
+    const q7_t *pB2;
+    q15_t    *pO = pOut;
+    const q7_t *pBias = bias;
+    const q15_t *pA = pV;
+
+    uint16_t  rowCnt = num_of_rows >> 1;
+
+    while (rowCnt)
+    {
+        q31_t     sum =  ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        uint16_t  colCnt = dim_vec >> 2;
+
+        pA = pV;
+        pB2 = pB + dim_vec;
+
+        while (colCnt)
+        {
+            q31_t     inV, inM11, inM12, inM21, inM22;
+            pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12);
+            pB2 = (q7_t *) read_and_pad((void *)pB2, &inM21, &inM22);
+
+            inV = *__SIMD32(pA)++;
+
+            sum = __SMLAD(inV, inM11, sum);
+            sum2 = __SMLAD(inV, inM21, sum2);
+
+            inV = *__SIMD32(pA)++;
+
+            sum = __SMLAD(inV, inM12, sum);
+            sum2 = __SMLAD(inV, inM22, sum2);
+
+            colCnt--;
+        }
+        colCnt = dim_vec & 0x3;
+        while (colCnt)
+        {
+            q15_t     inV = *pA++;
+            q7_t      inM = *pB++;
+            q7_t      inM2 = *pB2++;
+
+            sum += inV * inM;
+            sum2 += inV * inM2;
+            colCnt--;
+        }                       /* while over colCnt */
+        *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16));
+        *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16));
+
+        /*adjust the pointers and counters */
+        pB += dim_vec;
+        rowCnt--;
+    }
+
+    /* left-over part of the rows */
+    rowCnt = num_of_rows & 0x1;
+
+    while (rowCnt)
+    {
+        q31_t     sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        uint16_t  colCnt = dim_vec >> 2;
+
+        pA = pV;
+
+        while (colCnt)
+        {
+            q31_t     inV1, inV2, inM11, inM12;
+
+            pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12);
+
+            inV1 = *__SIMD32(pA)++;
+            sum = __SMLAD(inV1, inM11, sum);
+
+            inV2 = *__SIMD32(pA)++;
+            sum = __SMLAD(inV2, inM12, sum);
+
+            colCnt--;
+        }
+
+        /* left-over of the vector */
+        colCnt = dim_vec & 0x3;
+        while (colCnt)
+        {
+            q15_t     inV = *pA++;
+            q7_t      inM = *pB++;
+            sum += inV * inM;
+            colCnt--;
+        }
+
+        *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16));
+
+        rowCnt--;
+    }
+
+#else
+    int       i, j;
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    for (i = 0; i < num_of_rows; i++)
+    {
+        int       ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift);
+        for (j = 0; j < dim_vec; j++)
+        {
+            ip_out += pV[j] * pM[i * dim_vec + j];
+        }
+        pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16);
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to ARM_MATH_SUCCESS */
+    return (ARM_MATH_SUCCESS);
+
+}
+
+/**
+ * @} end of FC group
+ */
diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c
new file mode 100644
index 0000000..b0c308b
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_fully_connected_mat_q7_vec_q15_opt.c
+ * Description:  Mixed Q15-Q7 opt fully-connected layer function
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup FC
+ * @{
+ */
+
+  /**
+   * @brief Mixed Q15-Q7 opt fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * vec_buffer size: 0
+   *
+   *  Q7_Q15 version of the fully connected layer
+   *
+   *  Weights are in q7_t and Activations are in q15_t
+   *
+   *  Limitation: x4 version requires weight reordering to work
+   *
+   *  Here we use only one pointer to read 4 rows in the weight
+   *  matrix. So if the original q7_t matrix looks like this:
+   *
+   *  | a11 | a12 | a13 | a14 | a15 | a16 | a17 |
+   *
+   *  | a21 | a22 | a23 | a24 | a25 | a26 | a27 |
+   *
+   *  | a31 | a32 | a33 | a34 | a35 | a36 | a37 |
+   *
+   *  | a41 | a42 | a43 | a44 | a45 | a46 | a47 |
+   *
+   *  | a51 | a52 | a53 | a54 | a55 | a56 | a57 |
+   *
+   *  | a61 | a62 | a63 | a64 | a65 | a66 | a67 |
+   *
+   *  We operates on multiple-of-4 rows, so the first four rows becomes
+   *
+   *  | a11 | a21 | a12 | a22 | a31 | a41 | a32 | a42 |
+   *
+   *  | a13 | a23 | a14 | a24 | a33 | a43 | a34 | a44 |
+   *
+   *  | a15 | a25 | a16 | a26 | a35 | a45 | a36 | a46 |
+   *
+   *  The column left over will be in-order.
+   *  which is:
+   *  | a17 | a27 | a37 | a47 |
+   *
+   *  For the left-over rows, we do 1x1 computation, so the data remains
+   *  as its original order. 
+   *
+   *  So the stored weight matrix looks like this:
+   *
+   *  | a11 | a21 | a12 | a22 | a31 | a41 |
+   *
+   *  | a32 | a42 | a13 | a23 | a14 | a24 |
+   *
+   *  | a33 | a43 | a34 | a44 | a15 | a25 |
+   *
+   *  | a16 | a26 | a35 | a45 | a36 | a46 |
+   *
+   *  | a17 | a27 | a37 | a47 | a51 | a52 |
+   *
+   *  | a53 | a54 | a55 | a56 | a57 | a61 |
+   *
+   *  | a62 | a63 | a64 | a65 | a66 | a67 |
+   *
+   */
+
+arm_status
+arm_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV,
+                                       const q7_t * pM,
+                                       const uint16_t dim_vec,
+                                       const uint16_t num_of_rows,
+                                       const uint16_t bias_shift,
+                                       const uint16_t out_shift, const q7_t * bias, q15_t * pOut, q15_t * vec_buffer)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    const q7_t *pB = pM;
+    q15_t    *pO = pOut;
+    const q7_t *pBias = bias;
+    const q15_t *pA = pV;
+
+    uint16_t  rowCnt = num_of_rows >> 2;
+
+    while (rowCnt)
+    {
+        q31_t     sum =  ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        uint16_t  colCnt = dim_vec >> 1;
+
+        pA = pV;
+
+#ifdef USE_INTRINSIC
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        while (colCnt)
+        {
+            q31_t     inM11, inM12, inM13, inM14;
+            q31_t     inV;
+
+            inV = *__SIMD32(pA)++;
+            inM11 = *__SIMD32(pB)++;
+            inM12 = __SXTB16(__ROR(inM11, 8));
+            inM11 = __SXTB16(inM11);
+            sum = __SMLAD(inM11, inV, sum);
+            sum2 = __SMLAD(inM12, inV, sum2);
+            inM13 = *__SIMD32(pB)++;
+            inM14 = __SXTB16(__ROR(inM13, 8));
+            inM13 = __SXTB16(inM13);
+            sum3 = __SMLAD(inM13, inV, sum3);
+            sum4 = __SMLAD(inM14, inV, sum4);
+            colCnt--;
+        }
+
+#else
+
+        while (colCnt)
+        {
+            q31_t     inM11, inM12, inM13, inM14;
+            q31_t     inV;
+
+            inV = *__SIMD32(pA)++;
+            inM11 = *__SIMD32(pB)++;
+            inM12 = __SXTB16(__ROR(inM11, 8));
+            inM11 = __SXTB16(inM11);
+            sum = __SMLAD(inM12, inV, sum);
+            sum2 = __SMLAD(inM11, inV, sum2);
+            inM13 = *__SIMD32(pB)++;
+            inM14 = __SXTB16(__ROR(inM13, 8));
+            inM13 = __SXTB16(inM13);
+            sum3 = __SMLAD(inM14, inV, sum3);
+            sum4 = __SMLAD(inM13, inV, sum4);
+            colCnt--;
+        }
+
+#endif                          /* ARM_MATH_BIG_ENDIAN */
+
+#else
+
+        /*
+         * register needed:
+         * loop counter: colCnt
+         * accumulators: sum, sum2, sum3, sum4
+         * pointers: pB, pA
+         * weight data: inM11, inM12, inM13, inM14
+         * activation data: inV
+         */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        asm volatile ("COL_LOOP_%=:\n"
+                      "ldr.w r4, [%[pA]], #4\n"
+                      "ldr.w r1, [%[pB]], #8\n"
+                      "mov.w r0, r1, ror #8\n"
+                      "sxtb16 r0, r0\n"
+                      "sxtb16 r1, r1\n"
+                      "smlad %[sum], r4, r1, %[sum]\n"
+                      "smlad %[sum2], r4, r0, %[sum2]\n"
+                      "ldr.w r3, [%[pB], #-4]\n"
+                      "mov.w r2, r3, ror #8\n"
+                      "sxtb16 r2, r2\n"
+                      "sxtb16 r3, r3\n"
+                      "smlad %[sum3], r4, r3, %[sum3]\n"
+                      "smlad %[sum4], r4, r2, %[sum4]\n"
+                      "subs %[colCnt], #1\n"
+                      "bne COL_LOOP_%=\n":[sum] "+r"(sum),
+                      [sum2] "+r"(sum2),[sum3] "+r"(sum3),
+                      [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4");
+#else
+        asm volatile ("COL_LOOP_%=:\n"
+                      "ldr.w r4, [%[pA]], #4\n"
+                      "ldr.w r1, [%[pB]], #8\n"
+                      "mov.w r0, r1, ror #8\n"
+                      "sxtb16 r0, r0\n"
+                      "sxtb16 r1, r1\n"
+                      "smlad %[sum], r4, r0, %[sum]\n"
+                      "smlad %[sum2], r4, r1, %[sum2]\n"
+                      "ldr.w r3, [%[pB], #-4]\n"
+                      "mov.w r2, r3, ror #8\n"
+                      "sxtb16 r2, r2\n"
+                      "sxtb16 r3, r3\n"
+                      "smlad %[sum3], r4, r2, %[sum3]\n"
+                      "smlad %[sum4], r4, r3, %[sum4]\n"
+                      "subs %[colCnt], #1\n"
+                      "bne COL_LOOP_%=\n":[sum] "+r"(sum),
+                      [sum2] "+r"(sum2),[sum3] "+r"(sum3),
+                      [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4");
+#endif                          /* ARM_MATH_BIG_ENDIAN */
+
+#endif                          /* USE_INTRINSIC */
+
+        colCnt = dim_vec & 0x1;
+        while (colCnt)
+        {
+            q15_t     inV = *pA++;
+            q7_t      inM = *pB++;
+            q7_t      inM2 = *pB++;
+            q7_t      inM3 = *pB++;
+            q7_t      inM4 = *pB++;
+
+            sum += inV * inM;
+            sum2 += inV * inM2;
+            sum3 += inV * inM3;
+            sum4 += inV * inM4;
+            colCnt--;
+        }                       /* while over colCnt */
+        *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16));
+        *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16));
+        *pO++ = (q15_t) (__SSAT((sum3 >> out_shift), 16));
+        *pO++ = (q15_t) (__SSAT((sum4 >> out_shift), 16));
+
+        /* adjust the pointers and counters */
+        rowCnt--;
+    }
+
+    /* left-over part of the rows */
+    rowCnt = num_of_rows & 0x3;
+
+    while (rowCnt)
+    {
+        q31_t     sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        uint16_t  colCnt = dim_vec >> 2;
+
+        pA = pV;
+
+        while (colCnt)
+        {
+            q31_t     inV1, inV2, inM11, inM12;
+
+            pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12);
+
+            inV1 = *__SIMD32(pA)++;
+            sum = __SMLAD(inV1, inM11, sum);
+
+            inV2 = *__SIMD32(pA)++;
+            sum = __SMLAD(inV2, inM12, sum);
+
+            colCnt--;
+        }
+
+        /* left-over of the vector */
+        colCnt = dim_vec & 0x3;
+        while (colCnt)
+        {
+            q15_t     inV = *pA++;
+            q7_t      inM = *pB++;
+            sum += inV * inM;
+            colCnt--;
+        }
+
+        *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16));
+
+        rowCnt--;
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    uint16_t  rowCnt = num_of_rows >> 2;
+    const q7_t *pB = pM;
+    const q15_t *pA;
+    q15_t    *pO = pOut;
+    const q7_t *pBias = bias;
+
+    while (rowCnt)
+    {
+        q31_t     sum =  ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); 
+        q31_t     sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); 
+        uint16_t  colCnt = dim_vec >> 1;
+
+        pA = pV;
+
+        while (colCnt)
+        {
+            q15_t     inA1 = *pA++;
+            q15_t     inA2 = *pA++;
+
+            q7_t      inB1 = *pB++;
+            q7_t      inB3 = *pB++;
+            q7_t      inB2 = *pB++;
+            q7_t      inB4 = *pB++;
+
+            sum += inA1 * inB1 + inA2 * inB2;
+            sum2 += inA1 * inB3 + inA2 * inB4;
+
+            inB1 = *pB++;
+            inB3 = *pB++;
+            inB2 = *pB++;
+            inB4 = *pB++;
+
+            sum3 += inA1 * inB1 + inA2 * inB2;
+            sum4 += inA1 * inB3 + inA2 * inB4;
+
+            colCnt--;
+        }
+
+        colCnt = dim_vec & 0x1;
+        while (colCnt)
+        {
+            q15_t     inA = *pA++;
+            q7_t      inB = *pB++;
+            sum += inA * inB;
+            inB = *pB++;
+            sum2 += inA * inB;
+            inB = *pB++;
+            sum3 += inA * inB;
+            inB = *pB++;
+            sum4 += inA * inB;
+
+            colCnt--;
+        }
+        *pO++ = (q15_t) __SSAT((sum >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16);
+
+        rowCnt--;
+    }
+
+    rowCnt = num_of_rows & 0x3;
+
+    while (rowCnt)
+    {
+        int       ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        int       j;
+
+        pA = pV;
+        for (j = 0; j < dim_vec; j++)
+        {
+            q15_t     inA = *pA++;
+            q7_t      inB = *pB++;
+            ip_out += inA * inB;
+        }
+        *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16);
+
+        rowCnt--;
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to ARM_MATH_SUCCESS */
+    return (ARM_MATH_SUCCESS);
+
+}
+
+/**
+ * @} end of FC group
+ */
diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c
new file mode 100644
index 0000000..a4c6bba
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_fully_connected_q15.c
+ * Description:  Q15 basic fully-connected layer function
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup FC
+ * @{
+ */
+
+  /**
+   * @brief Q15 opt fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * vec_buffer size: 0
+   *
+   */
+
+arm_status
+arm_fully_connected_q15(const q15_t * pV,
+                        const q15_t * pM,
+                        const uint16_t dim_vec,
+                        const uint16_t num_of_rows,
+                        const uint16_t bias_shift,
+                        const uint16_t out_shift, 
+                        const q15_t * bias, 
+                        q15_t * pOut,
+                        q15_t * vec_buffer)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    const q15_t *pB = pM;
+    const q15_t *pB2 = pB + dim_vec;
+    q15_t    *pO = pOut;
+    const q15_t    *pA;
+    const q15_t    *pBias = bias;
+    uint16_t rowCnt = num_of_rows >> 1;
+
+    /* this loop loops over different output */
+    while (rowCnt) {
+        q31_t     sum =  ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        uint16_t  colCnt = dim_vec >> 2;
+
+        pA = pV;
+        pB2 = pB + dim_vec;
+
+        while (colCnt)
+        {
+            q31_t     inV1, inM1, inM2;
+            inV1 = *__SIMD32(pA)++;
+            inM1 = *__SIMD32(pB)++;
+            sum = __SMLAD(inV1, inM1, sum);
+            inM2 = *__SIMD32(pB2)++;
+            sum2 = __SMLAD(inV1, inM2, sum2);
+
+            inV1 = *__SIMD32(pA)++;
+            inM1 = *__SIMD32(pB)++;
+            sum = __SMLAD(inV1, inM1, sum);
+            inM2 = *__SIMD32(pB2)++;
+            sum2 = __SMLAD(inV1, inM2, sum2);
+
+            colCnt--;
+        }
+        colCnt = dim_vec & 0x3;
+        while (colCnt)
+        {
+            q15_t     inV = *pA++;
+            q15_t     inM = *pB++;
+            q15_t     inM2 = *pB2++;
+
+            sum += inV * inM;
+            sum2 += inV * inM2;
+            colCnt--;
+        }                       /* while over colCnt */
+        *pO++ =  (q15_t) (__SSAT((sum >> out_shift), 16));
+        *pO++ = (q15_t) (__SSAT((sum2>> out_shift), 16));
+		
+        /* adjust the pointers and counters */
+        pB = pB + dim_vec;
+        rowCnt --;
+    }
+
+    rowCnt = num_of_rows & 0x1;
+
+    while (rowCnt) {
+        q31_t     sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        uint16_t  colCnt = dim_vec >> 2;
+
+        pA = pV;
+      
+        while (colCnt) {
+            q31_t     inV1, inM1;
+            inV1 = *__SIMD32(pA)++;
+            inM1 = *__SIMD32(pB)++;
+            sum = __SMLAD(inV1, inM1, sum);
+            
+            inV1 = *__SIMD32(pA)++;
+            inM1 = *__SIMD32(pB)++;
+            sum = __SMLAD(inV1, inM1, sum);
+				
+            colCnt--;
+	}
+			
+	/* left-over of the vector */
+	colCnt = dim_vec & 0x3;
+	while(colCnt) {
+            q15_t     inV = *pA++;
+            q15_t     inM = *pB++;
+
+            sum += inV * inM;
+
+            colCnt--;
+	}
+
+        *pO++ =  (q15_t) (__SSAT((sum >> out_shift), 16));
+			
+        rowCnt --;
+    }
+
+#else
+    int       i, j;
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    for (i = 0; i < num_of_rows; i++)
+    {
+        int       ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift);
+        for (j = 0; j < dim_vec; j++)
+        {
+            ip_out += pV[j] * pM[i * dim_vec + j];
+        }
+        pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16);
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to application */
+    return (ARM_MATH_SUCCESS);
+
+}
+
+/**
+ * @} end of FC group
+ */
diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c
new file mode 100644
index 0000000..8f3bbea
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c
@@ -0,0 +1,332 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_fully_connected_q15_opt.c
+ * Description:  Q15 opt fully-connected layer function
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup FC
+ * @{
+ */
+
+  /**
+   * @brief Q15 opt fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * vec_buffer size: 0
+   *
+   *  Here we use only one pointer to read 4 rows in the weight
+   *  matrix. So if the original matrix looks like this:
+   *
+   *  | a11 | a12 | a13 |
+   *
+   *  | a21 | a22 | a23 |
+   *
+   *  | a31 | a32 | a33 |
+   *
+   *  | a41 | a42 | a43 |
+   *
+   *  | a51 | a52 | a53 |
+   *
+   *  | a61 | a62 | a63 |
+   *
+   *  We operates on multiple-of-4 rows, so the first four rows becomes
+   *
+   *  | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 |
+   *
+   *  | a13 | a23 | a33 | a43 |
+   *
+   *  Remaining rows are kept the same original order.
+   *
+   *  So the stored weight matrix looks like this:
+   *
+   *
+   *  | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 |
+   *
+   *  | a13 | a23 | a33 | a43 | a51 | a52 | a53 | a61 |
+   *
+   *  | a62 | a63 |
+   */
+
+arm_status
+arm_fully_connected_q15_opt(const q15_t * pV,
+                            const q15_t * pM,
+                            const uint16_t dim_vec,
+                            const uint16_t num_of_rows,
+                            const uint16_t bias_shift,
+                            const uint16_t out_shift, 
+                            const q15_t * bias, 
+                            q15_t * pOut, 
+                            q15_t * vec_buffer)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    const q15_t *pB = pM;
+    q15_t    *pO = pOut;
+    const q15_t *pBias = bias;
+    const q15_t *pA = pV;
+
+    uint16_t  rowCnt = num_of_rows >> 2;
+
+    while (rowCnt)
+    {
+        q31_t     sum =  ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); 
+        q31_t     sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); 
+        q31_t     sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); 
+
+        uint16_t  colCnt = dim_vec >> 1;
+
+        pA = pV;
+
+#ifdef USE_INTRINSIC
+
+        while (colCnt)
+        {
+            q31_t     inM11, inM12, inM13, inM14;
+            q31_t     inV;
+
+            inV = *__SIMD32(pA)++;
+            inM11 = *__SIMD32(pB)++;
+            sum = __SMLAD(inV, inM11, sum);
+            inM12 = *__SIMD32(pB)++;
+            sum2 = __SMLAD(inV, inM12, sum2);
+            inM13 = *__SIMD32(pB)++;
+            sum3 = __SMLAD(inV, inM13, sum3);
+            inM14 = *__SIMD32(pB)++;
+            sum4 = __SMLAD(inV, inM14, sum4);
+            colCnt--;
+        }
+
+#else
+
+        /*
+         * register needed:
+         * loop counter: colCnt
+         * accumulators: sum, sum2, sum3, sum4
+         * pointers: pB, pA
+         * weight data: inM11, inM12, inM13, inM14
+         * activation data: inV
+         */
+
+        asm volatile ("COL_LOOP_%=:\n"
+                      "ldr.w r4, [%[pA]], #4\n"
+                      "ldr.w r0, [%[pB]], #16\n"
+                      "smlad %[sum], r4, r0, %[sum]\n"
+                      "ldr.w r1, [%[pB] , #-12]\n"
+                      "smlad %[sum2], r4, r1, %[sum2]\n"
+                      "ldr.w r2, [%[pB] , #-8]\n"
+                      "smlad %[sum3], r4, r2, %[sum3]\n"
+                      "ldr.w r3, [%[pB] , #-4]\n"
+                      "smlad %[sum4], r4, r3, %[sum4]\n"
+                      "subs %[colCnt], #1\n"
+                      "bne COL_LOOP_%=\n":[sum] "+r"(sum),
+                      [sum2] "+r"(sum2),[sum3] "+r"(sum3),
+                      [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4");
+
+#endif                          /* USE_INTRINSIC */
+
+        colCnt = dim_vec & 0x1;
+        while (colCnt)
+        {
+
+            q15_t     inV = *pA++;
+            q15_t     inM = *pB++;
+            q15_t     inM2 = *pB++;
+            q15_t     inM3 = *pB++;
+            q15_t     inM4 = *pB++;
+
+            sum += inV * inM;
+            sum2 += inV * inM2;
+            sum3 += inV * inM3;
+            sum4 += inV * inM4;
+            colCnt--;
+        }                       /* while over colCnt */
+        *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16));
+        *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16));
+        *pO++ = (q15_t) (__SSAT((sum3 >> out_shift), 16));
+        *pO++ = (q15_t) (__SSAT((sum4 >> out_shift), 16));
+
+        /* adjust the pointers and counters */
+        rowCnt--;
+    }
+
+    /* left-over part of the rows */
+    rowCnt = num_of_rows & 0x3;
+
+    while (rowCnt)
+    {
+        q31_t     sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        uint16_t  colCnt = dim_vec >> 2;
+
+        pA = pV;
+
+        while (colCnt)
+        {
+            q31_t     inV1, inV2, inM1, inM2;
+
+            inM1 = *__SIMD32(pB)++;
+            inV1 = *__SIMD32(pA)++;
+            sum = __SMLAD(inV1, inM1, sum);
+
+            inM2 = *__SIMD32(pB)++;
+            inV2 = *__SIMD32(pA)++;
+            sum = __SMLAD(inV2, inM2, sum);
+
+            colCnt--;
+        }
+
+        /* left-over of the vector */
+        colCnt = dim_vec & 0x3;
+        while (colCnt)
+        {
+            q15_t     inV = *pA++;
+            q15_t     inM = *pB++;
+            sum += inV * inM;
+            colCnt--;
+        }
+
+        *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16));
+
+        rowCnt--;
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    uint16_t  rowCnt = num_of_rows >> 2;
+    const q15_t *pB = pM;
+    const q15_t *pA;
+    q15_t    *pO = pOut;
+    const q15_t *pBias = bias;
+
+    while (rowCnt)
+    {
+        q31_t     sum =  ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        uint16_t  colCnt = dim_vec >> 1;
+
+        pA = pV;
+        while (colCnt)
+        {
+            q15_t     inA1 = *pA++;
+            q15_t     inA2 = *pA++;
+
+            q15_t     inB1 = *pB++;
+            q15_t     inB2 = *pB++;
+            sum += inA1 * inB1 + inA2 * inB2;
+
+            inB1 = *pB++;
+            inB2 = *pB++;
+            sum2 += inA1 * inB1 + inA2 * inB2;
+
+            inB1 = *pB++;
+            inB2 = *pB++;
+            sum3 += inA1 * inB1 + inA2 * inB2;
+
+            inB1 = *pB++;
+            inB2 = *pB++;
+            sum4 += inA1 * inB1 + inA2 * inB2;
+
+            colCnt--;
+        }
+        colCnt = dim_vec & 0x1;
+        while (colCnt)
+        {
+            q15_t     inA = *pA++;
+            q15_t     inB = *pB++;
+            sum += inA * inB;
+            inB = *pB++;
+            sum2 += inA * inB;
+            inB = *pB++;
+            sum3 += inA * inB;
+            inB = *pB++;
+            sum4 += inA * inB;
+            colCnt--;
+        }
+        *pO++ = (q15_t) __SSAT((sum >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16);
+        *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16);
+
+        rowCnt--;
+    }
+    rowCnt = num_of_rows & 0x3;
+
+    while (rowCnt)
+    {
+        int       ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        int       j;
+
+        pA = pV;
+        for (j = 0; j < dim_vec; j++)
+        {
+            q15_t     inA = *pA++;
+            q15_t     inB = *pB++;
+            ip_out += inA * inB;
+        }
+        *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16);
+
+        rowCnt--;
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to ARM_MATH_SUCCESS */
+    return (ARM_MATH_SUCCESS);
+
+}
+
+/**
+ * @} end of FC group
+ */
diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c
new file mode 100644
index 0000000..75e924f
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_fully_connected_q7.c
+ * Description:  Q7 basic fully-connected layer function
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup FC
+ * @{
+ */
+
+  /**
+   * @brief Q7 basic fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * vec_buffer size: dim_vec
+   *
+   * This basic function is designed to work with regular weight
+   * matrix without interleaving.
+   *
+   */
+
+arm_status
+arm_fully_connected_q7(const q7_t * pV,
+                       const q7_t * pM,
+                       const uint16_t dim_vec,
+                       const uint16_t num_of_rows,
+                       const uint16_t bias_shift,
+                       const uint16_t out_shift, const q7_t * bias, q7_t * pOut, q15_t * vec_buffer)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    const q7_t *pB = pM;
+    const q7_t *pB2;
+    q7_t     *pO = pOut;
+    const q7_t *pBias = bias;
+    q15_t    *pA;
+    uint16_t  rowCnt = num_of_rows >> 1;
+
+    /* expand the vector into the buffer */
+    arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec);
+
+    while (rowCnt)
+    {
+        q31_t     sum =  ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        uint16_t  colCnt = dim_vec >> 2;
+
+        pA = vec_buffer;
+        pB2 = pB + dim_vec;
+
+        while (colCnt)
+        {
+            q31_t     inV, inM11, inM12, inM21, inM22;
+            pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12);
+            pB2 = (q7_t *) read_and_pad_reordered((void *)pB2, &inM21, &inM22);
+
+            inV = *__SIMD32(pA)++;
+
+            sum = __SMLAD(inV, inM11, sum);
+            sum2 = __SMLAD(inV, inM21, sum2);
+
+            inV = *__SIMD32(pA)++;
+
+            sum = __SMLAD(inV, inM12, sum);
+            sum2 = __SMLAD(inV, inM22, sum2);
+
+            colCnt--;
+        }
+        colCnt = dim_vec & 0x3;
+        while (colCnt)
+        {
+            q7_t      inV = *pA++;
+            q15_t     inM = *pB++;
+            q15_t     inM2 = *pB2++;
+
+            sum += inV * inM;
+            sum2 += inV * inM2;
+            colCnt--;
+        }                       /* while over colCnt */
+        *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8));
+        *pO++ = (q7_t) (__SSAT((sum2 >> out_shift), 8));
+
+        /* adjust the pointers and counters */
+        pB += dim_vec;
+        rowCnt--;
+    }
+
+    /* left-over part of the rows */
+    rowCnt = num_of_rows & 0x1;
+
+    while (rowCnt)
+    {
+        uint16_t  colCnt = dim_vec >> 2;
+        q31_t     sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        pA = vec_buffer;
+
+        while (colCnt)
+        {
+            q31_t     inV1, inV2, inM11, inM12;
+
+            pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12);
+
+            inV1 = *__SIMD32(pA)++;
+            sum = __SMLAD(inV1, inM11, sum);
+
+            inV2 = *__SIMD32(pA)++;
+            sum = __SMLAD(inV2, inM12, sum);
+
+            colCnt--;
+        }
+
+        /* left-over of the vector */
+        colCnt = dim_vec & 0x3;
+        while (colCnt)
+        {
+            q7_t      inV = *pA++;
+            q15_t     inM = *pB++;
+            sum += inV * inM;
+            colCnt--;
+        }
+
+        *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8));
+
+        rowCnt--;
+    }
+
+#else
+    int       i, j;
+
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    for (i = 0; i < num_of_rows; i++)
+    {
+        int       ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift);
+        for (j = 0; j < dim_vec; j++)
+        {
+            ip_out += pV[j] * pM[i * dim_vec + j];
+        }
+        pOut[i] = (q7_t) __SSAT((ip_out >> out_shift), 8);
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to ARM_MATH_SUCCESS */
+    return (ARM_MATH_SUCCESS);
+
+}
+
+/**
+ * @} end of FC group
+ */
diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c
new file mode 100644
index 0000000..d197adc
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c
@@ -0,0 +1,484 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_fully_connected_q7_opt.c
+ * Description:  Q7 basic fully-connected layer function
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup FC
+ * @{
+ */
+
+  /**
+   * @brief Q7 opt fully-connected layer function
+   * @param[in]       pV          pointer to input vector
+   * @param[in]       pM          pointer to matrix weights
+   * @param[in]       dim_vec     length of the vector
+   * @param[in]       num_of_rows number of rows in weight matrix
+   * @param[in]       bias_shift  amount of left-shift for bias
+   * @param[in]       out_shift   amount of right-shift for output
+   * @param[in]       bias        pointer to bias
+   * @param[in,out]   pOut        pointer to output vector
+   * @param[in,out]   vec_buffer  pointer to buffer space for input
+   * @return     The function returns ARM_MATH_SUCCESS
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * vec_buffer size: dim_vec
+   *
+   * This opt function is designed to work with interleaved weight
+   * matrix. The vector input is assumed in q7_t format, we call
+   *  arm_q7_to_q15_no_shift_shuffle function to expand into
+   *  q15_t format with certain weight re-ordering, refer to the function
+   *  comments for more details.
+   *  Here we use only one pointer to read 4 rows in the weight
+   *  matrix. So if the original q7_t matrix looks like this:
+   *
+   *  | a11 | a12 | a13 | a14 | a15 | a16 | a17 |
+   *
+   *  | a21 | a22 | a23 | a24 | a25 | a26 | a27 |
+   *
+   *  | a31 | a32 | a33 | a34 | a35 | a36 | a37 |
+   *
+   *  | a41 | a42 | a43 | a44 | a45 | a46 | a47 |
+   *
+   *  | a51 | a52 | a53 | a54 | a55 | a56 | a57 |
+   *
+   *  | a61 | a62 | a63 | a64 | a65 | a66 | a67 |
+   *
+   *
+   *  We operates on multiple-of-4 rows, so the first four rows becomes
+   *
+   *  | a11 | a21 | a13 | a23 | a31 | a41 | a33 | a43 |
+   *
+   *  | a12 | a22 | a14 | a24 | a32 | a42 | a34 | a44 |
+   *
+   *  | a15 | a25 | a35 | a45 | a16 | a26 | a36 | a46 |
+   *
+   *  So within the kernel, we first read the re-ordered vector in as:
+   *
+   *  | b1  | b3  | and | b2  | b4  |
+   *
+   *  the four q31_t weights will look like
+   *
+   *  | a11 | a13 |, | a21 | a23 |, | a31 | a33 |, | a41 | a43 |
+   *
+   *  | a12 | a14 |, | a22 | a24 |, | a32 | a34 |, | a42 | a44 |
+   *
+   *  The column left over will be in-order.
+   *  which is:
+   *
+   *  | a17 | a27 | a37 | a47 |
+   *
+   *  For the left-over rows, we do 1x1 computation, so the data remains
+   *  as its original order. 
+   *
+   *  So the stored weight matrix looks like this:
+   *
+   *  | a11 | a21 | a13 | a23 | a31 | a41 |
+   *
+   *  | a33 | a43 | a12 | a22 | a14 | a24 |
+   *
+   *  | a32 | a42 | a34 | a44 | a15 | a25 |
+   *
+   *  | a35 | a45 | a16 | a26 | a36 | a46 |
+   *
+   *  | a17 | a27 | a37 | a47 | a51 | a52 |
+   *
+   *  | a53 | a54 | a55 | a56 | a57 | a61 |
+   *
+   *  | a62 | a63 | a64 | a65 | a66 | a67 |
+   *
+   *
+   */
+
+arm_status
+arm_fully_connected_q7_opt(const q7_t * pV,
+                           const q7_t * pM,
+                           const uint16_t dim_vec,
+                           const uint16_t num_of_rows,
+                           const uint16_t bias_shift,
+                           const uint16_t out_shift, 
+                           const q7_t * bias, 
+                           q7_t * pOut, 
+                           q15_t * vec_buffer)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    const q7_t *pB = pM;
+    q7_t     *pO = pOut;
+    const q7_t *pBias = bias;
+    q15_t    *pA;
+    uint16_t  rowCnt = num_of_rows >> 2;
+
+    arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec);
+
+    while (rowCnt)
+    {
+
+        q31_t     sum =  ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        uint16_t  colCnt = dim_vec >> 2;
+
+        pA = vec_buffer;
+
+#ifdef USE_INTRINSIC
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        while (colCnt)
+        {
+            q31_t     inM11, inM12, inM13, inM14;
+            q31_t     inV;
+
+            inV = *__SIMD32(pA)++;
+            inM11 = *__SIMD32(pB)++;
+            inM12 = __SXTB16(__ROR(inM11, 8));
+            inM11 = __SXTB16(inM11);
+            sum = __SMLAD(inM11, inV, sum);
+            sum2 = __SMLAD(inM12, inV, sum2);
+            inM13 = *__SIMD32(pB)++;
+            inM14 = __SXTB16(__ROR(inM13, 8));
+            inM13 = __SXTB16(inM13);
+            sum3 = __SMLAD(inM13, inV, sum3);
+            sum4 = __SMLAD(inM14, inV, sum4);
+
+            inV = *__SIMD32(pA)++;
+            inM11 = *__SIMD32(pB)++;
+            inM12 = __SXTB16(__ROR(inM11, 8));
+            inM11 = __SXTB16(inM11);
+            sum = __SMLAD(inM11, inV, sum);
+            sum2 = __SMLAD(inM12, inV, sum2);
+            inM13 = *__SIMD32(pB)++;
+            inM14 = __SXTB16(__ROR(inM13, 8));
+            inM13 = __SXTB16(inM13);
+            sum3 = __SMLAD(inM13, inV, sum3);
+            sum4 = __SMLAD(inM14, inV, sum4);
+            colCnt--;
+        }
+#else
+        while (colCnt)
+        {
+            q31_t     inM11, inM12, inM13, inM14;
+            q31_t     inV;
+
+            inV = *__SIMD32(pA)++;
+            inM11 = *__SIMD32(pB)++;
+            inM12 = __SXTB16(__ROR(inM11, 8));
+            inM11 = __SXTB16(inM11);
+            sum = __SMLAD(inM12, inV, sum);
+            sum2 = __SMLAD(inM11, inV, sum2);
+            inM13 = *__SIMD32(pB)++;
+            inM14 = __SXTB16(__ROR(inM13, 8));
+            inM13 = __SXTB16(inM13);
+            sum3 = __SMLAD(inM14, inV, sum3);
+            sum4 = __SMLAD(inM13, inV, sum4);
+
+            inV = *__SIMD32(pA)++;
+            inM11 = *__SIMD32(pB)++;
+            inM12 = __SXTB16(__ROR(inM11, 8));
+            inM11 = __SXTB16(inM11);
+            sum = __SMLAD(inM12, inV, sum);
+            sum2 = __SMLAD(inM11, inV, sum2);
+            inM13 = *__SIMD32(pB)++;
+            inM14 = __SXTB16(__ROR(inM13, 8));
+            inM13 = __SXTB16(inM13);
+            sum3 = __SMLAD(inM14, inV, sum3);
+            sum4 = __SMLAD(inM13, inV, sum4);
+            colCnt--;
+        }
+#endif                          /* ARM_MATH_BIG_ENDIAN */
+
+#else
+
+        /*
+         * register needed:
+         * loop counter: colCnt
+         * accumulators: sum, sum2, sum3, sum4
+         * pointers: pB, pA
+         * weight data: inM11, inM12, inM13, inM14
+         * activation data: inV
+         */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        asm volatile ("COL_LOOP_%=:\n"
+                      "ldr.w r4, [%[pA]], #8\n"
+                      "ldr.w r1, [%[pB]], #16\n"
+                      "mov.w r0, r1, ror #8\n"
+                      "sxtb16 r0, r0\n"
+                      "sxtb16 r1, r1\n"
+                      "smlad %[sum], r4, r1, %[sum]\n"
+                      "smlad %[sum2], r4, r0, %[sum2]\n"
+                      "ldr.w r3, [%[pB], #-12]\n"
+                      "mov.w r2, r3, ror #8\n"
+                      "sxtb16 r2, r2\n"
+                      "sxtb16 r3, r3\n"
+                      "smlad %[sum3], r4, r3, %[sum3]\n"
+                      "smlad %[sum4], r4, r2, %[sum4]\n"
+                      "ldr.w r4, [%[pA], #-4]\n"
+                      "ldr.w r1, [%[pB], #-8]\n"
+                      "mov.w r0, r1, ror #8\n"
+                      "sxtb16 r0, r0\n"
+                      "sxtb16 r1, r1\n"
+                      "smlad %[sum], r4, r1, %[sum]\n"
+                      "smlad %[sum2], r4, r0, %[sum2]\n"
+                      "ldr.w r3, [%[pB], #-4]\n"
+                      "mov.w r2, r3, ror #8\n"
+                      "sxtb16 r2, r2\n"
+                      "sxtb16 r3, r3\n"
+                      "smlad %[sum3], r4, r3, %[sum3]\n"
+                      "smlad %[sum4], r4, r2, %[sum4]\n"
+                      "subs %[colCnt], #1\n"
+                      "bne COL_LOOP_%=\n":[sum] "+r"(sum),
+                      [sum2] "+r"(sum2),[sum3] "+r"(sum3),
+                      [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4");
+#else
+        asm volatile ("COL_LOOP_%=:\n"
+                      "ldr.w r4, [%[pA]], #8\n"
+                      "ldr.w r1, [%[pB]], #16\n"
+                      "mov.w r0, r1, ror #8\n"
+                      "sxtb16 r0, r0\n"
+                      "sxtb16 r1, r1\n"
+                      "smlad %[sum], r4, r0, %[sum]\n"
+                      "smlad %[sum2], r4, r1, %[sum2]\n"
+                      "ldr.w r3, [%[pB], #-12]\n"
+                      "mov.w r2, r3, ror #8\n"
+                      "sxtb16 r2, r2\n"
+                      "sxtb16 r3, r3\n"
+                      "smlad %[sum3], r4, r2, %[sum3]\n"
+                      "smlad %[sum4], r4, r3, %[sum4]\n"
+                      "ldr.w r4, [%[pA], #-4]\n"
+                      "ldr.w r1, [%[pB], #-8]\n"
+                      "mov.w r0, r1, ror #8\n"
+                      "sxtb16 r0, r0\n"
+                      "sxtb16 r1, r1\n"
+                      "smlad %[sum], r4, r0, %[sum]\n"
+                      "smlad %[sum2], r4, r1, %[sum2]\n"
+                      "ldr.w r3, [%[pB], #-4]\n"
+                      "mov.w r2, r3, ror #8\n"
+                      "sxtb16 r2, r2\n"
+                      "sxtb16 r3, r3\n"
+                      "smlad %[sum3], r4, r2, %[sum3]\n"
+                      "smlad %[sum4], r4, r3, %[sum4]\n"
+                      "subs %[colCnt], #1\n"
+                      "bne COL_LOOP_%=\n":[sum] "+r"(sum),
+                      [sum2] "+r"(sum2),[sum3] "+r"(sum3),
+                      [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4");
+#endif                          /* ARM_MATH_BIG_ENDIAN */
+
+#endif                          /* USE_INTRINSIC */
+
+        colCnt = dim_vec & 0x3;
+        while (colCnt)
+        {
+            q15_t     inV = *pA++;
+            q7_t      inM = *pB++;
+            q7_t      inM2 = *pB++;
+            q7_t      inM3 = *pB++;
+            q7_t      inM4 = *pB++;
+
+            sum += inV * inM;
+            sum2 += inV * inM2;
+            sum3 += inV * inM3;
+            sum4 += inV * inM4;
+            colCnt--;
+        }                       /* while over colCnt */
+        *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8));
+        *pO++ = (q7_t) (__SSAT((sum2 >> out_shift), 8));
+        *pO++ = (q7_t) (__SSAT((sum3 >> out_shift), 8));
+        *pO++ = (q7_t) (__SSAT((sum4 >> out_shift), 8));
+
+        /* adjust the pointers and counters */
+        rowCnt--;
+    }
+
+    /* left-over part of the rows */
+    rowCnt = num_of_rows & 0x3;
+
+    while (rowCnt)
+    {
+        q31_t     sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        uint16_t  colCnt = dim_vec >> 2;
+
+        pA = vec_buffer;
+
+        while (colCnt)
+        {
+            q31_t     inV1, inV2, inM11, inM12;
+
+            pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12);
+
+            inV1 = *__SIMD32(pA)++;
+            sum = __SMLAD(inV1, inM11, sum);
+
+            inV2 = *__SIMD32(pA)++;
+            sum = __SMLAD(inV2, inM12, sum);
+
+            colCnt--;
+        }
+
+        /* left-over of the vector */
+        colCnt = dim_vec & 0x3;
+        while (colCnt)
+        {
+            q15_t     inV = *pA++;
+            q7_t      inM = *pB++;
+            sum += inV * inM;
+            colCnt--;
+        }
+
+        *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8));
+
+        rowCnt--;
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+    uint16_t  rowCnt = num_of_rows >> 2;
+    const q7_t *pB = pM;
+    const q7_t *pA;
+    q7_t     *pO = pOut;
+    const q7_t *pBias = bias;
+
+    while (rowCnt)
+    {
+        q31_t     sum =  ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+        q31_t     sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        uint16_t  colCnt = dim_vec >> 2;
+
+        pA = pV;
+
+        while (colCnt)
+        {
+            q7_t      inA1 = *pA++;
+            q7_t      inA3 = *pA++;
+            q7_t      inA2 = *pA++;
+            q7_t      inA4 = *pA++;
+
+            q7_t      inB1 = *pB++;
+            q7_t      inB3 = *pB++;
+            q7_t      inB2 = *pB++;
+            q7_t      inB4 = *pB++;
+
+            sum += inA1 * inB1 + inA2 * inB2;
+            sum2 += inA1 * inB3 + inA2 * inB4;
+
+            inB1 = *pB++;
+            inB3 = *pB++;
+            inB2 = *pB++;
+            inB4 = *pB++;
+
+            sum3 += inA1 * inB1 + inA2 * inB2;
+            sum4 += inA1 * inB3 + inA2 * inB4;
+
+            inB1 = *pB++;
+            inB3 = *pB++;
+            inB2 = *pB++;
+            inB4 = *pB++;
+
+            sum += inA3 * inB1 + inA4 * inB2;
+            sum2 += inA3 * inB3 + inA4 * inB4;
+
+            inB1 = *pB++;
+            inB3 = *pB++;
+            inB2 = *pB++;
+            inB4 = *pB++;
+
+            sum3 += inA3 * inB1 + inA4 * inB2;
+            sum4 += inA3 * inB3 + inA4 * inB4;
+
+            colCnt--;
+        }
+        colCnt = dim_vec & 0x3;
+        while (colCnt)
+        {
+            q7_t      inA = *pA++;
+            q7_t      inB = *pB++;
+            sum += inA * inB;
+            inB = *pB++;
+            sum2 += inA * inB;
+            inB = *pB++;
+            sum3 += inA * inB;
+            inB = *pB++;
+            sum4 += inA * inB;
+
+            colCnt--;
+        }
+        *pO++ = (q7_t) __SSAT((sum >> out_shift), 8);
+        *pO++ = (q7_t) __SSAT((sum2 >> out_shift), 8);
+        *pO++ = (q7_t) __SSAT((sum3 >> out_shift), 8);
+        *pO++ = (q7_t) __SSAT((sum4 >> out_shift), 8);
+
+        rowCnt--;
+    }
+
+    rowCnt = num_of_rows & 0x3;
+
+    while (rowCnt)
+    {
+        int       ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift);
+
+        int       j;
+
+        pA = pV;
+        for (j = 0; j < dim_vec; j++)
+        {
+            q7_t      inA = *pA++;
+            q7_t      inB = *pB++;
+            ip_out += inA * inB;
+        }
+        *pO++ = (q7_t) __SSAT((ip_out >> out_shift), 8);
+
+        rowCnt--;
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+    /* Return to ARM_MATH_SUCCESS */
+    return (ARM_MATH_SUCCESS);
+
+}
+
+/**
+ * @} end of FC group
+ */
diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c
new file mode 100644
index 0000000..de7668b
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nn_mult_q15.c
+ * Description:  Q15 vector multiplication with variable output shifts
+ *
+ * $Date:        13. July 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnfunctions.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**
+ * @addtogroup NNBasicMath
+ * @{
+ */
+
+
+/**
+ * @brief           Q7 vector multiplication with variable output shifts
+ * @param[in]       *pSrcA        pointer to the first input vector
+ * @param[in]       *pSrcB        pointer to the second input vector
+ * @param[out]      *pDst         pointer to the output vector
+ * @param[in]       out_shift     amount of right-shift for output
+ * @param[in]       blockSize     number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_nn_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  const uint16_t out_shift,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counters */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t inA1, inA2, inB1, inB2;                  /* temporary input variables */
+  q15_t out1, out2, out3, out4;                  /* temporary output variables */
+  q31_t mul1, mul2, mul3, mul4;                  /* temporary variables */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* read two samples at a time from sourceA */
+    inA1 = *__SIMD32(pSrcA)++;
+    /* read two samples at a time from sourceB */
+    inB1 = *__SIMD32(pSrcB)++;
+    /* read two samples at a time from sourceA */
+    inA2 = *__SIMD32(pSrcA)++;
+    /* read two samples at a time from sourceB */
+    inB2 = *__SIMD32(pSrcB)++;
+
+    /* multiply mul = sourceA * sourceB */
+    mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+    mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1);
+    mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16));
+    mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2);
+
+    /* saturate result to 16 bit */
+    out1 = (q15_t) __SSAT((mul1 + NN_ROUND(out_shift)) >> out_shift, 16);
+    out2 = (q15_t) __SSAT((mul2 + NN_ROUND(out_shift)) >> out_shift, 16);
+    out3 = (q15_t) __SSAT((mul3 + NN_ROUND(out_shift)) >> out_shift, 16);
+    out4 = (q15_t) __SSAT((mul4 + NN_ROUND(out_shift)) >> out_shift, 16);
+
+    /* store the result */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+    *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+    *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+  while (blkCnt > 0U)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the result in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 16);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of NNBasicMath group
+ */
+
diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c
new file mode 100644
index 0000000..1b4e02c
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nn_mult_q7.c
+ * Description:  Q7 vector multiplication with variable output shifts
+ *
+ * $Date:        13. July 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnfunctions.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**
+ * @addtogroup NNBasicMath
+ * @{
+ */
+
+/**
+ * @brief           Q7 vector multiplication with variable output shifts
+ * @param[in]       *pSrcA        pointer to the first input vector
+ * @param[in]       *pSrcB        pointer to the second input vector
+ * @param[out]      *pDst         pointer to the output vector
+ * @param[in]       out_shift     amount of right-shift for output
+ * @param[in]       blockSize     number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_nn_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  const uint16_t out_shift,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counters */
+
+#if defined (ARM_MATH_DSP)
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q7_t out1, out2, out3, out4;                   /* Temporary variables to store the product */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2U;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while (blkCnt > 0U)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the results in temporary variables */
+    out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8);
+    out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8);
+    out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8);
+    out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8);
+
+    /* Store the results of 4 inputs in the destination buffer in single cycle by packing */
+    *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4U;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+
+  while (blkCnt > 0U)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the result in the destination buffer */
+    *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+}
+
+/**
+ * @} end of NNBasicMath group
+ */
diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c
new file mode 100644
index 0000000..cabd9b1
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nntables.c
+ * Description:  Converts the elements of the Q7 vector to Q15 vector without left-shift
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnsupportfunctions.h"
+
+/**
+ * @brief tables for various activation functions
+ *
+ * This file include the declaration of common tables.
+ * Most of them are used for activation functions 
+ *
+ * Assumption:
+ * Unified table: input is 3.x format, i.e, range of [-8, 8)
+ * sigmoid(8) = 0.9996646498695336
+ * tanh(8) = 0.9999997749296758
+ * The accuracy here should be good enough
+ *
+ * 2-stage HL table: 
+ *
+ * The entire input range is divided into two parts:
+ *
+ * Low range table: 0x000x xxxx or 0x111x xxxx 
+ * table entry will be the binary number excluding the first
+ * two digits, i.e., 0x0x xxxx or 0x1x xxxx
+ * 
+ *
+ *
+ * High range table 0x0010 0000 -- 0x0111 1111
+ *                  0x1000 0000 -- 0x1101 1111
+ * 
+ * For positive numbers, table entry will be
+ * 0x0010 0000 -- 0x0111 1111 minus 0x0010 0000
+ * i.e., 0x0000 0000 - 0x0101 11111
+ *
+ * same thing for the negative numbers, table entry will be
+ * 0x1000 0000 -- 0x1101 1111 minux 0x0010 0000
+ * i.e., 0x0110 0000 - 0x1011 1111
+ */
+
+const q7_t sigmoidTable_q7[256] = {
+    0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e,
+    0x50, 0x52, 0x53, 0x55, 0x57, 0x59, 0x5a, 0x5c,
+    0x5e, 0x5f, 0x61, 0x62, 0x63, 0x65, 0x66, 0x67,
+    0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
+    0x71, 0x72, 0x72, 0x73, 0x74, 0x74, 0x75, 0x76,
+    0x76, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7a,
+    0x7a, 0x7a, 0x7b, 0x7b, 0x7b, 0x7c, 0x7c, 0x7c,
+    0x7c, 0x7c, 0x7d, 0x7d, 0x7d, 0x7d, 0x7d, 0x7e,
+    0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+    0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+    0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04,
+    0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x06,
+    0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09,
+    0x0a, 0x0a, 0x0b, 0x0c, 0x0c, 0x0d, 0x0e, 0x0e,
+    0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16,
+    0x17, 0x19, 0x1a, 0x1b, 0x1d, 0x1e, 0x1f, 0x21,
+    0x22, 0x24, 0x26, 0x27, 0x29, 0x2b, 0x2d, 0x2e,
+    0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e,
+};
+
+const q15_t sigmoidTable_q15[256] = {
+    0x4000, 0x4200, 0x43ff, 0x45fc, 0x47f5, 0x49eb, 0x4bdc, 0x4dc8,
+    0x4fad, 0x518a, 0x5360, 0x552c, 0x56ef, 0x58a8, 0x5a57, 0x5bfb,
+    0x5d93, 0x5f20, 0x60a1, 0x6216, 0x637f, 0x64db, 0x662b, 0x676f,
+    0x68a6, 0x69d2, 0x6af1, 0x6c05, 0x6d0d, 0x6e09, 0x6efb, 0x6fe2,
+    0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7,
+    0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f,
+    0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03,
+    0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d,
+    0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81,
+    0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17,
+    0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72,
+    0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa,
+    0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc,
+    0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0,
+    0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed,
+    0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4,
+    0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011,
+    0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c,
+    0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e,
+    0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c,
+    0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d,
+    0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce,
+    0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152,
+    0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a,
+    0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388,
+    0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8,
+    0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a,
+    0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70,
+    0x0f42, 0x101e, 0x1105, 0x11f7, 0x12f3, 0x13fb, 0x150f, 0x162e,
+    0x175a, 0x1891, 0x19d5, 0x1b25, 0x1c81, 0x1dea, 0x1f5f, 0x20e0,
+    0x226d, 0x2405, 0x25a9, 0x2758, 0x2911, 0x2ad4, 0x2ca0, 0x2e76,
+    0x3053, 0x3238, 0x3424, 0x3615, 0x380b, 0x3a04, 0x3c01, 0x3e00,
+};
+
+const q15_t sigmoidLTable_q15[128] = {
+    0x4000, 0x4100, 0x4200, 0x42ff, 0x43ff, 0x44fd, 0x45fc, 0x46f9,
+    0x47f5, 0x48f1, 0x49eb, 0x4ae5, 0x4bdc, 0x4cd3, 0x4dc8, 0x4ebb,
+    0x4fad, 0x509c, 0x518a, 0x5276, 0x5360, 0x5447, 0x552c, 0x560f,
+    0x56ef, 0x57cd, 0x58a8, 0x5981, 0x5a57, 0x5b2a, 0x5bfb, 0x5cc9,
+    0x5d93, 0x5e5b, 0x5f20, 0x5fe2, 0x60a1, 0x615d, 0x6216, 0x62cc,
+    0x637f, 0x642e, 0x64db, 0x6584, 0x662b, 0x66ce, 0x676f, 0x680c,
+    0x68a6, 0x693d, 0x69d2, 0x6a63, 0x6af1, 0x6b7c, 0x6c05, 0x6c8a,
+    0x6d0d, 0x6d8d, 0x6e09, 0x6e84, 0x6efb, 0x6f70, 0x6fe2, 0x7051,
+    0x0f42, 0x0faf, 0x101e, 0x1090, 0x1105, 0x117c, 0x11f7, 0x1273,
+    0x12f3, 0x1376, 0x13fb, 0x1484, 0x150f, 0x159d, 0x162e, 0x16c3,
+    0x175a, 0x17f4, 0x1891, 0x1932, 0x19d5, 0x1a7c, 0x1b25, 0x1bd2,
+    0x1c81, 0x1d34, 0x1dea, 0x1ea3, 0x1f5f, 0x201e, 0x20e0, 0x21a5,
+    0x226d, 0x2337, 0x2405, 0x24d6, 0x25a9, 0x267f, 0x2758, 0x2833,
+    0x2911, 0x29f1, 0x2ad4, 0x2bb9, 0x2ca0, 0x2d8a, 0x2e76, 0x2f64,
+    0x3053, 0x3145, 0x3238, 0x332d, 0x3424, 0x351b, 0x3615, 0x370f,
+    0x380b, 0x3907, 0x3a04, 0x3b03, 0x3c01, 0x3d01, 0x3e00, 0x3f00,
+};
+
+const q15_t sigmoidHTable_q15[192] = {
+    0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7,
+    0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f,
+    0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03,
+    0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d,
+    0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81,
+    0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17,
+    0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72,
+    0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa,
+    0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc,
+    0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0,
+    0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed,
+    0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4,
+    0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011,
+    0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c,
+    0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e,
+    0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c,
+    0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d,
+    0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce,
+    0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152,
+    0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a,
+    0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388,
+    0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8,
+    0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a,
+    0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70,
+};
+
+const q7_t tanhTable_q7[256] = {
+    0x00, 0x08, 0x10, 0x18, 0x1f, 0x27, 0x2e, 0x35,
+    0x3b, 0x41, 0x47, 0x4c, 0x51, 0x56, 0x5a, 0x5e,
+    0x61, 0x65, 0x68, 0x6a, 0x6d, 0x6f, 0x71, 0x72,
+    0x74, 0x75, 0x76, 0x78, 0x78, 0x79, 0x7a, 0x7b,
+    0x7b, 0x7c, 0x7c, 0x7d, 0x7d, 0x7e, 0x7e, 0x7e,
+    0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81,
+    0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x82,
+    0x82, 0x82, 0x82, 0x82, 0x83, 0x83, 0x84, 0x84,
+    0x85, 0x85, 0x86, 0x87, 0x88, 0x88, 0x8a, 0x8b,
+    0x8c, 0x8e, 0x8f, 0x91, 0x93, 0x96, 0x98, 0x9b,
+    0x9f, 0xa2, 0xa6, 0xaa, 0xaf, 0xb4, 0xb9, 0xbf,
+    0xc5, 0xcb, 0xd2, 0xd9, 0xe1, 0xe8, 0xf0, 0xf8,
+};
+
+const q15_t tanhTable_q15[256] = {
+    0x0000, 0x07fd, 0x0feb, 0x17b9, 0x1f59, 0x26bf, 0x2ddf, 0x34ae,
+    0x3b27, 0x4142, 0x46fd, 0x4c56, 0x514d, 0x55e2, 0x5a1a, 0x5df6,
+    0x617c, 0x64b0, 0x6797, 0x6a37, 0x6c95, 0x6eb5, 0x709e, 0x7254,
+    0x73dc, 0x753a, 0x7672, 0x7788, 0x787f, 0x795b, 0x7a1e, 0x7acb,
+    0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f,
+    0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48,
+    0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc,
+    0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7,
+    0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7,
+    0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd,
+    0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff,
+    0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+    0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+    0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+    0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+    0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001,
+    0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003,
+    0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007,
+    0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013,
+    0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035,
+    0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f,
+    0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183,
+    0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412,
+    0x849b, 0x8535, 0x85e2, 0x86a5, 0x8781, 0x8878, 0x898e, 0x8ac6,
+    0x8c24, 0x8dac, 0x8f62, 0x914b, 0x936b, 0x95c9, 0x9869, 0x9b50,
+    0x9e84, 0xa20a, 0xa5e6, 0xaa1e, 0xaeb3, 0xb3aa, 0xb903, 0xbebe,
+    0xc4d9, 0xcb52, 0xd221, 0xd941, 0xe0a7, 0xe847, 0xf015, 0xf803,
+};
+
+const q15_t tanhLTable_q15[128] = {
+    0x0000, 0x0400, 0x07fd, 0x0bf7, 0x0feb, 0x13d7, 0x17b9, 0x1b90,
+    0x1f59, 0x2314, 0x26bf, 0x2a58, 0x2ddf, 0x3151, 0x34ae, 0x37f6,
+    0x3b27, 0x3e40, 0x4142, 0x442c, 0x46fd, 0x49b6, 0x4c56, 0x4edd,
+    0x514d, 0x53a3, 0x55e2, 0x580a, 0x5a1a, 0x5c13, 0x5df6, 0x5fc4,
+    0x617c, 0x6320, 0x64b0, 0x662d, 0x6797, 0x68f0, 0x6a37, 0x6b6e,
+    0x6c95, 0x6dac, 0x6eb5, 0x6fb0, 0x709e, 0x717f, 0x7254, 0x731e,
+    0x73dc, 0x7490, 0x753a, 0x75da, 0x7672, 0x7701, 0x7788, 0x7807,
+    0x787f, 0x78f0, 0x795b, 0x79bf, 0x7a1e, 0x7a77, 0x7acb, 0x7b1b,
+    0x849b, 0x84e5, 0x8535, 0x8589, 0x85e2, 0x8641, 0x86a5, 0x8710,
+    0x8781, 0x87f9, 0x8878, 0x88ff, 0x898e, 0x8a26, 0x8ac6, 0x8b70,
+    0x8c24, 0x8ce2, 0x8dac, 0x8e81, 0x8f62, 0x9050, 0x914b, 0x9254,
+    0x936b, 0x9492, 0x95c9, 0x9710, 0x9869, 0x99d3, 0x9b50, 0x9ce0,
+    0x9e84, 0xa03c, 0xa20a, 0xa3ed, 0xa5e6, 0xa7f6, 0xaa1e, 0xac5d,
+    0xaeb3, 0xb123, 0xb3aa, 0xb64a, 0xb903, 0xbbd4, 0xbebe, 0xc1c0,
+    0xc4d9, 0xc80a, 0xcb52, 0xceaf, 0xd221, 0xd5a8, 0xd941, 0xdcec,
+    0xe0a7, 0xe470, 0xe847, 0xec29, 0xf015, 0xf409, 0xf803, 0xfc00,
+};
+
+const q15_t tanhHTable_q15[192] = {
+    0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f,
+    0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48,
+    0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc,
+    0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7,
+    0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7,
+    0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd,
+    0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff,
+    0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+    0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+    0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+    0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+    0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001,
+    0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003,
+    0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007,
+    0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013,
+    0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035,
+    0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f,
+    0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183,
+    0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412,
+};
diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c
new file mode 100644
index 0000000..e043b38
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_q7_to_q15_no_shift.c
+ * Description:  Converts the elements of the Q7 vector to Q15 vector without left-shift
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnsupportfunctions.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup nndata_convert    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift 
+ * @param[in]       *pSrc points to the Q7 input vector    
+ * @param[out]      *pDst points to the Q15 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * 
    
+ * 	pDst[n] = (q15_t) pSrc[n];   0 <= n < blockSize.    
+ * 
    
+ *   
+ */
+
+void arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize)
+{
+    const q7_t *pIn = pSrc;     /* Src pointer */
+    uint32_t  blkCnt;           /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+    q31_t     in;
+    q31_t     in1, in2;
+    q31_t     out1, out2;
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /*loop Unrolling */
+    blkCnt = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (blkCnt > 0u)
+    {
+        /* C = (q15_t) A << 8 */
+        /* convert from q7 to q15 and then store the results in the destination buffer */
+        in = *__SIMD32(pIn)++;
+
+        /* rotatate in by 8 and extend two q7_t values to q15_t values */
+        in1 = __SXTB16(__ROR(in, 8));
+
+        /* extend remainig two q7_t values to q15_t values */
+        in2 = __SXTB16(in);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out2 = __PKHTB(in1, in2, 16);
+        out1 = __PKHBT(in2, in1, 16);
+
+#else
+
+        out1 = __PKHTB(in1, in2, 16);
+        out2 = __PKHBT(in2, in1, 16);
+
+#endif
+
+        *__SIMD32(pDst)++ = out1;
+        *__SIMD32(pDst)++ = out2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Loop over blockSize number of values */
+    blkCnt = blockSize;
+
+#endif                          /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    while (blkCnt > 0u)
+    {
+        /* C = (q15_t) A << 8 */
+        /* convert from q7 to q15 and then store the results in the destination buffer */
+        *pDst++ = (q15_t) * pIn++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+    }
+
+}
+
+/**    
+ * @} end of nndata_convert group   
+ */
diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c
new file mode 100644
index 0000000..52f5f8e
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_q7_to_q15_reordered_no_shift.c
+ * Description:  Converts the elements of the Q7 vector to reordered Q15 vector without left-shift
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnsupportfunctions.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup nndata_convert    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift
+ * @param[in]       *pSrc points to the Q7 input vector    
+ * @param[out]      *pDst points to the Q15 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * @details
+ *
+ * This function does the q7 to q15 expansion with re-ordering 
+ *
+ * 
+ *                          |   A1   |   A2   |   A3   |   A4   |
+ *
+ *                           0      7 8     15 16    23 24    31
+ * 

+ *
+ * is converted into:
+ *
+ * 
+ *  |       A1       |       A3       |   and  |       A2       |       A4       |
+ *
+ *   0             15 16            31          0             15 16            31
+ * 

+ *
+ *
+ * This looks strange but is natural considering how sign-extension is done at
+ * assembly level. 
+ *
+ * The expansion of other other oprand will follow the same rule so that the end 
+ * results are the same.
+ *
+ * The tail (i.e., last (N % 4) elements) will still be in original order.
+ *   
+ */
+
+void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize)
+{
+    const q7_t *pIn = pSrc;     /* Src pointer */
+    uint32_t  blkCnt;           /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+    q31_t     in;
+    q31_t     in1, in2;
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /*loop Unrolling */
+    blkCnt = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while (blkCnt > 0u)
+    {
+        /* C = (q15_t) A << 8 */
+        /* convert from q7 to q15 and then store the results in the destination buffer */
+        in = *__SIMD32(pIn)++;
+
+        /* rotatate in by 8 and extend two q7_t values to q15_t values */
+        in1 = __SXTB16(__ROR(in, 8));
+
+        /* extend remainig two q7_t values to q15_t values */
+        in2 = __SXTB16(in);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        *__SIMD32(pDst)++ = in2;
+        *__SIMD32(pDst)++ = in1;
+#else
+        *__SIMD32(pDst)++ = in1;
+        *__SIMD32(pDst)++ = in2;
+#endif
+
+        /* Decrement the loop counter */
+        blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Loop over blockSize number of values */
+    blkCnt = blockSize;
+
+#endif                          /* #ifndef ARM_MATH_CM0_FAMILY */
+
+    while (blkCnt > 0u)
+    {
+        /* C = (q15_t) A << 8 */
+        /* convert from q7 to q15 and then store the results in the destination buffer */
+        *pDst++ = (q15_t) * pIn++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+    }
+
+}
+
+/**    
+ * @} end of q7_to_x group    
+ */
diff --git a/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c
new file mode 100644
index 0000000..2759731
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c
@@ -0,0 +1,448 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_pool_q7_HWC.c
+ * Description:  Pooling function implementations
+ *
+ * $Date:        17. January 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+#if defined (ARM_MATH_DSP)
+
+/**
+ * @brief A few utility functions used by pooling functions
+ *
+ * 
+ */
+
+static void buffer_scale_back_q15_to_q7(q15_t * buffer, q7_t * target, uint16_t length, uint16_t scale)
+{
+    int       i;
+
+    for (i = 0; i < length; i++)
+    {
+        target[i] = (q7_t) (buffer[i] / scale);
+    }
+}
+
+static void compare_and_replace_if_larger_q7(q7_t * base,   // base data
+                                             q7_t * target, // compare target
+                                             const uint16_t length  // data length
+    )
+{
+    q7_t     *pIn = base;
+    q7_t     *pCom = target;
+    union arm_nnword in;
+    union arm_nnword com;
+    uint16_t  cnt = length >> 2;
+
+    while (cnt > 0u)
+    {
+        in.word = *__SIMD32(pIn);
+        com.word = *__SIMD32(pCom)++;
+
+        // if version
+        if (com.bytes[0] > in.bytes[0])
+            in.bytes[0] = com.bytes[0];
+        if (com.bytes[1] > in.bytes[1])
+            in.bytes[1] = com.bytes[1];
+        if (com.bytes[2] > in.bytes[2])
+            in.bytes[2] = com.bytes[2];
+        if (com.bytes[3] > in.bytes[3])
+            in.bytes[3] = com.bytes[3];
+
+        *__SIMD32(pIn)++ = in.word;
+
+        cnt--;
+    }
+}
+
+static void accumulate_q7_to_q15(q15_t * base, q7_t * target, const uint16_t length)
+{
+    q15_t    *pCnt = base;
+    q7_t     *pV = target;
+    q31_t     v1, v2, vo1, vo2;
+    uint16_t  cnt = length >> 2;
+    q31_t     in;
+
+    while (cnt > 0u)
+    {
+        q31_t     value = *__SIMD32(pV)++;
+        v1 = __SXTB16(__ROR(value, 8));
+        v2 = __SXTB16(value);
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        vo2 = __PKHTB(v1, v2, 16);
+        vo1 = __PKHBT(v2, v1, 16);
+
+#else
+
+        vo1 = __PKHTB(v1, v2, 16);
+        vo2 = __PKHBT(v2, v1, 16);
+
+#endif
+
+        in = *__SIMD32(pCnt);
+        *__SIMD32(pCnt)++ = __QADD16(vo1, in);
+
+        in = *__SIMD32(pCnt);
+        *__SIMD32(pCnt)++ = __QADD16(vo2, in);
+
+        cnt--;
+    }
+    cnt = length & 0x3;
+    while (cnt > 0u)
+    {
+        *pCnt++ += *pV++;
+        cnt--;
+    }
+}
+
+#endif                          // ARM_MATH_DSP
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Pooling
+ * @{
+ */
+
+  /**
+   * @brief Q7 max pooling function
+   * @param[in, out]  Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @return none.
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * bufferA size:  0
+   *
+   * The pooling function is implemented as split x-pooling then
+   * y-pooling.
+   *
+   * This pooling function is input-destructive. Input data is undefined
+   * after calling this function.
+   *
+   */
+
+void
+arm_maxpool_q7_HWC(q7_t * Im_in,
+                   const uint16_t dim_im_in,
+                   const uint16_t ch_im_in,
+                   const uint16_t dim_kernel,
+                   const uint16_t padding,
+                   const uint16_t stride, const uint16_t dim_im_out, q7_t * bufferA, q7_t * Im_out)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    int16_t   i_x, i_y;
+
+    /* first does the pooling along x axis */
+    for (i_y = 0; i_y < dim_im_in; i_y++)
+    {
+
+        for (i_x = 0; i_x < dim_im_out; i_x++)
+        {
+            /* for each output pixel */
+            q7_t     *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in;
+            q7_t     *win_start;
+            q7_t     *win_stop;
+            if (i_x * stride - padding < 0)
+            {
+                win_start = target;
+            } else
+            {
+                win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in;
+            }
+
+            if (i_x * stride - padding + dim_kernel >= dim_im_in)
+            {
+                win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in;
+            } else
+            {
+                win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in;
+            }
+
+            /* first step is to copy over initial data */
+            /* arm_copy_q7(win_start, target, ch_im_in); */
+            memmove(target, win_start, ch_im_in);
+
+            /* start the max operation from the second part */
+            win_start += ch_im_in;
+            for (; win_start < win_stop; win_start += ch_im_in)
+            {
+                compare_and_replace_if_larger_q7(target, win_start, ch_im_in);
+            }
+        }
+    }
+
+    /* then does the pooling along y axis */
+    for (i_y = 0; i_y < dim_im_out; i_y++)
+    {
+
+        /* for each output row */
+        q7_t     *target = Im_out + i_y * dim_im_out * ch_im_in;
+        q7_t     *row_start;
+        q7_t     *row_end;
+        /* setting the starting row */
+        if (i_y * stride - padding < 0)
+        {
+            row_start = Im_in;
+        } else
+        {
+            row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in;
+        }
+        /* setting the stopping row */
+        if (i_y * stride - padding + dim_kernel >= dim_im_in)
+        {
+            row_end = Im_in + dim_im_in * dim_im_in * ch_im_in;
+        } else
+        {
+            row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in;
+        }
+
+        /* copy over the first row */
+        /* arm_copy_q7(row_start, target, dim_im_out * ch_im_in); */
+        memmove(target, row_start, dim_im_out * ch_im_in);
+
+        /* move over to next row */
+        row_start += ch_im_in * dim_im_in;
+
+        for (; row_start < row_end; row_start += dim_im_in * ch_im_in)
+        {
+            compare_and_replace_if_larger_q7(target, row_start, dim_im_out * ch_im_in);
+        }
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+
+    int16_t   i_ch_in, i_x, i_y;
+    int16_t   k_x, k_y;
+
+    for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++)
+    {
+        for (i_y = 0; i_y < dim_im_out; i_y++)
+        {
+            for (i_x = 0; i_x < dim_im_out; i_x++)
+            {
+                int       max = -129;
+                for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++)
+                {
+                    for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++)
+                    {
+                        if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in)
+                        {
+                            if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max)
+                            {
+                                max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)];
+                            }
+                        }
+                    }
+                }
+                Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max;
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+}
+
+  /**
+   * @brief Q7 average pooling function
+   * @param[in,out]   Im_in       pointer to input tensor
+   * @param[in]       dim_im_in   input tensor dimention
+   * @param[in]       ch_im_in    number of input tensor channels
+   * @param[in]       dim_kernel  filter kernel size
+   * @param[in]       padding     padding sizes
+   * @param[in]       stride      convolution stride
+   * @param[in]       dim_im_out  output tensor dimension
+   * @param[in,out]   bufferA     pointer to buffer space for input
+   * @param[in,out]   Im_out      pointer to output tensor
+   * @return none.
+   *
+   * @details
+   *
+   * Buffer size:
+   *
+   * bufferA size:  2*dim_im_out*ch_im_in
+   *
+   * The pooling function is implemented as split x-pooling then
+   * y-pooling.
+   *
+   * This pooling function is input-destructive. Input data is undefined
+   * after calling this function.
+   *
+   */
+
+void
+arm_avepool_q7_HWC(q7_t * Im_in,
+                   const uint16_t dim_im_in,
+                   const uint16_t ch_im_in,
+                   const uint16_t dim_kernel,
+                   const uint16_t padding,
+                   const uint16_t stride, const uint16_t dim_im_out, q7_t * bufferA, q7_t * Im_out)
+{
+
+#if defined (ARM_MATH_DSP)
+    /* Run the following code for Cortex-M4 and Cortex-M7 */
+
+    q15_t    *buffer = (q15_t *) bufferA;
+    int16_t   i_x, i_y;
+    int16_t   count = 0;
+
+    /* first does the pooling along x axis */
+    for (i_y = 0; i_y < dim_im_in; i_y++)
+    {
+
+        for (i_x = 0; i_x < dim_im_out; i_x++)
+        {
+            /* for each output pixel */
+            q7_t     *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in;
+            q7_t     *win_start;
+            q7_t     *win_stop;
+            if (i_x * stride - padding < 0)
+            {
+                win_start = target;
+            } else
+            {
+                win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in;
+            }
+
+            if (i_x * stride - padding + dim_kernel >= dim_im_in)
+            {
+                win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in;
+            } else
+            {
+                win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in;
+            }
+
+            /* first step is to copy over initial data */
+            arm_q7_to_q15_no_shift(win_start, buffer, ch_im_in);
+            count = 1;
+
+            /* start the max operation from the second part */
+            win_start += ch_im_in;
+            for (; win_start < win_stop; win_start += ch_im_in)
+            {
+                accumulate_q7_to_q15(buffer, win_start, ch_im_in);
+                count++;
+            }
+            buffer_scale_back_q15_to_q7(buffer, target, ch_im_in, count);
+        }
+    }
+
+    /* then does the pooling along y axis */
+    for (i_y = 0; i_y < dim_im_out; i_y++)
+    {
+        /* for each output row */
+        q7_t     *target = Im_out + i_y * dim_im_out * ch_im_in;
+        q7_t     *row_start;
+        q7_t     *row_end;
+        /* setting the starting row */
+        if (i_y * stride - padding < 0)
+        {
+            row_start = Im_in;
+        } else
+        {
+            row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in;
+        }
+        /* setting the stopping row */
+        if (i_y * stride - padding + dim_kernel >= dim_im_in)
+        {
+            row_end = Im_in + dim_im_in * dim_im_in * ch_im_in;
+        } else
+        {
+            row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in;
+        }
+
+        /* copy over the first row */
+        arm_q7_to_q15_no_shift(row_start, buffer, dim_im_out * ch_im_in);
+        count = 1;
+
+        /* move over to next row */
+        row_start += ch_im_in * dim_im_in;
+
+        for (; row_start < row_end; row_start += dim_im_in * ch_im_in)
+        {
+            accumulate_q7_to_q15(buffer, row_start, dim_im_out * ch_im_in);
+            count++;
+        }
+        buffer_scale_back_q15_to_q7(buffer, target, dim_im_out * ch_im_in, count);
+    }
+
+#else
+    /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
+
+    int16_t   i_ch_in, i_x, i_y;
+    int16_t   k_x, k_y;
+
+    for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++)
+    {
+        for (i_y = 0; i_y < dim_im_out; i_y++)
+        {
+            for (i_x = 0; i_x < dim_im_out; i_x++)
+            {
+                int       sum = 0;
+                int       count = 0;
+                for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++)
+                {
+                    for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++)
+                    {
+                        if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in)
+                        {
+                            sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)];
+                            count++;
+                        }
+                    }
+                }
+                Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count;
+            }
+        }
+    }
+
+#endif                          /* ARM_MATH_DSP */
+
+}
+
+/**
+ * @} end of Pooling group
+ */
diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c
new file mode 100644
index 0000000..22fa62b
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_softmax_q15.c
+ * Description:  Q15 softmax function
+ *
+ * $Date:        20. February 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Softmax
+ * @{
+ */
+
+  /**
+   * @brief Q15 softmax function
+   * @param[in]       vec_in      pointer to input vector
+   * @param[in]       dim_vec     input vector dimention
+   * @param[out]      p_out       pointer to output vector
+   * @return none.
+   *
+   * @details
+   *
+   *  Here, instead of typical e based softmax, we use
+   *  2-based softmax, i.e.,:
+   *
+   *  y_i = 2^(x_i) / sum(2^x_j)
+   *
+   *  The relative output will be different here.
+   *  But mathematically, the gradient will be the same
+   *  with a log(2) scaling factor.
+   *
+   */
+
+void arm_softmax_q15(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out)
+{
+    q31_t     sum;
+    int16_t   i;
+    uint8_t   shift;
+    q31_t     base;
+    base = -1 * 0x100000;
+    for (i = 0; i < dim_vec; i++)
+    {
+        if (vec_in[i] > base)
+        {
+            base = vec_in[i];
+        }
+    }
+
+    /* we ignore really small values  
+     * anyway, they will be 0 after shrinking
+     * to q15_t
+     */
+    base = base - 16;
+
+    sum = 0;
+
+    for (i = 0; i < dim_vec; i++)
+    {
+        if (vec_in[i] > base)
+        {
+            shift = (uint8_t)__USAT(vec_in[i] - base, 5);
+            sum += 0x1 << shift;
+        }
+    }
+
+    /* This is effectively (0x1 << 32) / sum */
+    int64_t div_base = 0x100000000LL;
+    int output_base = (int32_t)(div_base / sum);
+
+    /* Final confidence will be output_base >> ( 17 - (vec_in[i] - base) )
+     * so 32768 (0x1<<15) -> 100% confidence when sum = 0x1 << 16, output_base = 0x1 << 16
+     * and vec_in[i]-base = 16
+     */
+    for (i = 0; i < dim_vec; i++)
+    {
+        if (vec_in[i] > base) 
+        {
+            /* Here minimum value of 17+base-vec[i] will be 1 */
+            shift = (uint8_t)__USAT(17+base-vec_in[i], 5);
+            p_out[i] = (q15_t) __SSAT((output_base >> shift), 16);
+        } else
+        {
+            p_out[i] = 0;
+        }
+    }
+
+}
+
+/**
+ * @} end of Softmax group
+ */
diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c
new file mode 100644
index 0000000..06a69e1
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_softmax_q7.c
+ * Description:  Q7 softmax function
+ *
+ * $Date:        20. February 2018
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Softmax
+ * @{
+ */
+
+  /**
+   * @brief Q7 softmax function
+   * @param[in]       vec_in      pointer to input vector
+   * @param[in]       dim_vec     input vector dimention
+   * @param[out]      p_out       pointer to output vector
+   * @return none.
+   *
+   * @details
+   *
+   *  Here, instead of typical natural logarithm e based softmax, we use
+   *  2-based softmax here, i.e.,:
+   * 
+   *  y_i = 2^(x_i) / sum(2^x_j)
+   *
+   *  The relative output will be different here.
+   *  But mathematically, the gradient will be the same
+   *  with a log(2) scaling factor.
+   *
+   */
+
+void arm_softmax_q7(const q7_t * vec_in, const uint16_t dim_vec, q7_t * p_out)
+{
+    q31_t     sum;
+    int16_t   i;
+    uint8_t   shift;
+    q15_t     base;
+    base = -257;
+
+    /* We first search for the maximum */
+    for (i = 0; i < dim_vec; i++)
+    {
+        if (vec_in[i] > base)
+        {
+            base = vec_in[i];
+        }
+    }
+
+    /* 
+     * So the base is set to max-8, meaning 
+     * that we ignore really small values. 
+     * anyway, they will be 0 after shrinking to q7_t.
+     */
+    base = base - 8;
+
+    sum = 0;
+
+    for (i = 0; i < dim_vec; i++)
+    {
+        if (vec_in[i] > base) 
+        {
+            shift = (uint8_t)__USAT(vec_in[i] - base, 5);
+            sum += 0x1 << shift;
+        }
+    }
+
+    /* This is effectively (0x1 << 20) / sum */
+    int output_base = 0x100000 / sum;
+
+    /* 
+     * Final confidence will be output_base >> ( 13 - (vec_in[i] - base) )
+     * so 128 (0x1<<7) -> 100% confidence when sum = 0x1 << 8, output_base = 0x1 << 12 
+     * and vec_in[i]-base = 8
+     */
+    for (i = 0; i < dim_vec; i++) 
+    {
+        if (vec_in[i] > base) 
+        {
+            /* Here minimum value of 13+base-vec_in[i] will be 5 */
+            shift = (uint8_t)__USAT(13+base-vec_in[i], 5);
+            p_out[i] = (q7_t) __SSAT((output_base >> shift), 8);
+        } else {
+            p_out[i] = 0;
+        }
+    }
+}
+
+/**
+ * @} end of Softmax group
+ */
diff --git a/Drivers/CMSIS/RTOS/Template/cmsis_os.h b/Drivers/CMSIS/RTOS/Template/cmsis_os.h
new file mode 100644
index 0000000..85e24a4
--- /dev/null
+++ b/Drivers/CMSIS/RTOS/Template/cmsis_os.h
@@ -0,0 +1,698 @@
+/* ----------------------------------------------------------------------
+ * $Date:        5. February 2013
+ * $Revision:    V1.02
+ *
+ * Project:      CMSIS-RTOS API
+ * Title:        cmsis_os.h template header file
+ *
+ * Version 0.02
+ *    Initial Proposal Phase
+ * Version 0.03
+ *    osKernelStart added, optional feature: main started as thread
+ *    osSemaphores have standard behavior
+ *    osTimerCreate does not start the timer, added osTimerStart
+ *    osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ *    Support for C++ interface
+ *     - const attribute removed from the osXxxxDef_t typedef's
+ *     - const attribute added to the osXxxxDef macros
+ *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ *    Added: osKernelInitialize
+ * Version 1.02
+ *    Control functions for short timeouts in microsecond resolution:
+ *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
+ *    Removed: osSignalGet 
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2013-2017 ARM LIMITED
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *---------------------------------------------------------------------------*/
+ 
+ 
+#ifndef _CMSIS_OS_H
+#define _CMSIS_OS_H
+ 
+/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
+#define osCMSIS           0x10002      ///< API version (main [31:16] .sub [15:0])
+ 
+/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
+#define osCMSIS_KERNEL    0x10000	   ///< RTOS identification and version (main [31:16] .sub [15:0])
+ 
+/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
+#define osKernelSystemId "KERNEL V1.00"   ///< RTOS identification string
+ 
+/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
+#define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available
+#define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available
+#define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available
+#define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available
+#define osFeature_Signals      8       ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore    30      ///< maximum count for \ref osSemaphoreCreate function
+#define osFeature_Wait         1       ///< osWait function: 1=available, 0=not available
+#define osFeature_SysTick      1       ///< osKernelSysTick functions: 1=available, 0=not available
+ 
+#include 
+#include 
+ 
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+ 
+ 
+// ==== Enumeration, structures, defines ====
+ 
+/// Priority used for thread control.
+/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osPriorityIdle          = -3,          ///< priority: idle (lowest)
+  osPriorityLow           = -2,          ///< priority: low
+  osPriorityBelowNormal   = -1,          ///< priority: below normal
+  osPriorityNormal        =  0,          ///< priority: normal (default)
+  osPriorityAboveNormal   = +1,          ///< priority: above normal
+  osPriorityHigh          = +2,          ///< priority: high
+  osPriorityRealtime      = +3,          ///< priority: realtime (highest)
+  osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority
+} osPriority;
+ 
+/// Timeout value.
+/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
+#define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value
+ 
+/// Status code values returned by CMSIS-RTOS functions.
+/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osOK                    =     0,       ///< function completed; no error or event occurred.
+  osEventSignal           =  0x08,       ///< function completed; signal event occurred.
+  osEventMessage          =  0x10,       ///< function completed; message event occurred.
+  osEventMail             =  0x20,       ///< function completed; mail event occurred.
+  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.
+  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
+  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.
+  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.
+  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.
+  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.
+  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorValue            =  0x86,       ///< value of a parameter is out of range.
+  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.
+  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.
+} osStatus;
+ 
+ 
+/// Timer type value for the timer definition.
+/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osTimerOnce             =     0,       ///< one-shot timer
+  osTimerPeriodic         =     1        ///< repeating timer
+} os_timer_type;
+ 
+/// Entry point of a thread.
+/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
+typedef void (*os_pthread) (void const *argument);
+ 
+/// Entry point of a timer call back function.
+/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
+typedef void (*os_ptimer) (void const *argument);
+ 
+// >>> the following data type definitions may shall adapted towards a specific RTOS
+ 
+/// Thread ID identifies the thread (pointer to a thread control block).
+/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_cb *osThreadId;
+ 
+/// Timer ID identifies the timer (pointer to a timer control block).
+/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_cb *osTimerId;
+ 
+/// Mutex ID identifies the mutex (pointer to a mutex control block).
+/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_cb *osMutexId;
+ 
+/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
+/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_cb *osSemaphoreId;
+ 
+/// Pool ID identifies the memory pool (pointer to a memory pool control block).
+/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_cb *osPoolId;
+ 
+/// Message ID identifies the message queue (pointer to a message queue control block).
+/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_cb *osMessageQId;
+ 
+/// Mail ID identifies the mail queue (pointer to a mail queue control block).
+/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_cb *osMailQId;
+ 
+ 
+/// Thread Definition structure contains startup information of a thread.
+/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_def  {
+  os_pthread               pthread;    ///< start address of thread function
+  osPriority             tpriority;    ///< initial thread priority
+  uint32_t               instances;    ///< maximum number of instances of that thread function
+  uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size
+} osThreadDef_t;
+ 
+/// Timer Definition structure contains timer parameters.
+/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_def  {
+  os_ptimer                 ptimer;    ///< start address of a timer function
+} osTimerDef_t;
+ 
+/// Mutex Definition structure contains setup information for a mutex.
+/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_def  {
+  uint32_t                   dummy;    ///< dummy value.
+} osMutexDef_t;
+ 
+/// Semaphore Definition structure contains setup information for a semaphore.
+/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_def  {
+  uint32_t                   dummy;    ///< dummy value.
+} osSemaphoreDef_t;
+ 
+/// Definition structure for memory block allocation.
+/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_def  {
+  uint32_t                 pool_sz;    ///< number of items (elements) in the pool
+  uint32_t                 item_sz;    ///< size of an item
+  void                       *pool;    ///< pointer to memory for pool
+} osPoolDef_t;
+ 
+/// Definition structure for message queue.
+/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  uint32_t                 item_sz;    ///< size of an item
+  void                       *pool;    ///< memory array for messages
+} osMessageQDef_t;
+ 
+/// Definition structure for mail queue.
+/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  uint32_t                 item_sz;    ///< size of an item
+  void                       *pool;    ///< memory array for mail
+} osMailQDef_t;
+ 
+/// Event structure contains detailed information about an event.
+/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
+///       However the struct may be extended at the end.
+typedef struct  {
+  osStatus                 status;     ///< status code: event or error information
+  union  {
+    uint32_t                    v;     ///< message as 32-bit value
+    void                       *p;     ///< message or mail as void pointer
+    int32_t               signals;     ///< signal flags
+  } value;                             ///< event value
+  union  {
+    osMailQId             mail_id;     ///< mail id obtained by \ref osMailCreate
+    osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate
+  } def;                               ///< event definition
+} osEvent;
+ 
+ 
+//  ==== Kernel Control Functions ====
+ 
+/// Initialize the RTOS Kernel for creating objects.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
+osStatus osKernelInitialize (void);
+ 
+/// Start the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
+osStatus osKernelStart (void);
+ 
+/// Check if the RTOS kernel is already started.
+/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+int32_t osKernelRunning(void);
+ 
+#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available
+ 
+/// Get the RTOS kernel system timer counter 
+/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
+/// \return RTOS kernel system timer as 32-bit value 
+uint32_t osKernelSysTick (void);
+ 
+/// The RTOS kernel system timer frequency in Hz
+/// \note Reflects the system timer setting and is typically defined in a configuration file.
+#define osKernelSysTickFrequency 100000000
+ 
+/// Convert a microseconds value to a RTOS kernel system timer value.
+/// \param         microsec     time value in microseconds.
+/// \return time value normalized to the \ref osKernelSysTickFrequency
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
+ 
+#endif    // System Timer available
+ 
+//  ==== Thread Management ====
+ 
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param         name         name of the thread function.
+/// \param         priority     initial priority of the thread function.
+/// \param         instances    number of possible thread instances.
+/// \param         stacksz      stack size (in bytes) requirements for the thread function.
+/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osThreadDef(name, priority, instances, stacksz)  \
+extern const osThreadDef_t os_thread_def_##name
+#else                            // define the object
+#define osThreadDef(name, priority, instances, stacksz)  \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), (priority), (instances), (stacksz)  }
+#endif
+ 
+/// Access a Thread definition.
+/// \param         name          name of the thread definition object.
+/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osThread(name)  \
+&os_thread_def_##name
+ 
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in]     thread_def    thread definition referenced with \ref osThread.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
+ 
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadGetId (void);
+ 
+/// Terminate execution of a thread and remove it from Active Threads.
+/// \param[in]     thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
+osStatus osThreadTerminate (osThreadId thread_id);
+ 
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
+osStatus osThreadYield (void);
+ 
+/// Change priority of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+ 
+/// Get current priority of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the thread function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
+osPriority osThreadGetPriority (osThreadId thread_id);
+ 
+ 
+//  ==== Generic Wait Functions ====
+ 
+/// Wait for Timeout (Time Delay).
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value
+/// \return status code that indicates the execution status of the function.
+osStatus osDelay (uint32_t millisec);
+ 
+#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available
+ 
+/// Wait for Signal, Message, Mail, or Timeout.
+/// \param[in] millisec          \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
+osEvent osWait (uint32_t millisec);
+ 
+#endif  // Generic Wait available
+ 
+ 
+//  ==== Timer Management Functions ====
+/// Define a Timer object.
+/// \param         name          name of the timer object.
+/// \param         function      name of the timer call back function.
+/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osTimerDef(name, function)  \
+extern const osTimerDef_t os_timer_def_##name
+#else                            // define the object
+#define osTimerDef(name, function)  \
+const osTimerDef_t os_timer_def_##name = \
+{ (function) }
+#endif
+ 
+/// Access a Timer definition.
+/// \param         name          name of the timer object.
+/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osTimer(name) \
+&os_timer_def_##name
+ 
+/// Create a timer.
+/// \param[in]     timer_def     timer object referenced with \ref osTimer.
+/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
+ 
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+ 
+/// Stop the timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStop (osTimerId timer_id);
+ 
+/// Delete a timer that was created by \ref osTimerCreate.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
+osStatus osTimerDelete (osTimerId timer_id);
+ 
+ 
+//  ==== Signal Management ====
+ 
+/// Set the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
+int32_t osSignalSet (osThreadId thread_id, int32_t signals);
+ 
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
+/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
+int32_t osSignalClear (osThreadId thread_id, int32_t signals);
+ 
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flag information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
+osEvent osSignalWait (int32_t signals, uint32_t millisec);
+ 
+ 
+//  ==== Mutex Management ====
+ 
+/// Define a Mutex.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMutexDef(name)  \
+extern const osMutexDef_t os_mutex_def_##name
+#else                            // define the object
+#define osMutexDef(name)  \
+const osMutexDef_t os_mutex_def_##name = { 0 }
+#endif
+ 
+/// Access a Mutex definition.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMutex(name)  \
+&os_mutex_def_##name
+ 
+/// Create and Initialize a Mutex object.
+/// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
+ 
+/// Wait until a Mutex becomes available.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+ 
+/// Release a Mutex that was obtained by \ref osMutexWait.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
+osStatus osMutexRelease (osMutexId mutex_id);
+ 
+/// Delete a Mutex that was created by \ref osMutexCreate.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
+osStatus osMutexDelete (osMutexId mutex_id);
+ 
+ 
+//  ==== Semaphore Management Functions ====
+ 
+#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available
+ 
+/// Define a Semaphore object.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osSemaphoreDef(name)  \
+extern const osSemaphoreDef_t os_semaphore_def_##name
+#else                            // define the object
+#define osSemaphoreDef(name)  \
+const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
+#endif
+ 
+/// Access a Semaphore definition.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osSemaphore(name)  \
+&os_semaphore_def_##name
+ 
+/// Create and Initialize a Semaphore object used for managing resources.
+/// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in]     count         number of available resources.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
+ 
+/// Wait until a Semaphore token becomes available.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+ 
+/// Release a Semaphore token.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+ 
+/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
+ 
+#endif     // Semaphore available
+ 
+ 
+//  ==== Memory Pool Management Functions ====
+ 
+#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available
+ 
+/// \brief Define a Memory Pool.
+/// \param         name          name of the memory pool.
+/// \param         no            maximum number of blocks (objects) in the memory pool.
+/// \param         type          data type of a single block (object).
+/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osPoolDef(name, no, type)   \
+extern const osPoolDef_t os_pool_def_##name
+#else                            // define the object
+#define osPoolDef(name, no, type)   \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), NULL }
+#endif
+ 
+/// \brief Access a Memory Pool definition.
+/// \param         name          name of the memory pool
+/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osPool(name) \
+&os_pool_def_##name
+ 
+/// Create and Initialize a memory pool.
+/// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
+osPoolId osPoolCreate (const osPoolDef_t *pool_def);
+ 
+/// Allocate a memory block from a memory pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolAlloc (osPoolId pool_id);
+ 
+/// Allocate a memory block from a memory pool and set memory block to zero.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolCAlloc (osPoolId pool_id);
+ 
+/// Return an allocated memory block back to a specific memory pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in]     block         address of the allocated memory block that is returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+ 
+#endif   // Memory Pool Management available
+ 
+ 
+//  ==== Message Queue Management Functions ====
+ 
+#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available
+ 
+/// \brief Create a Message Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of messages in the queue.
+/// \param         type          data type of a single message element (for debugger).
+/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMessageQDef(name, queue_sz, type)   \
+extern const osMessageQDef_t os_messageQ_def_##name
+#else                            // define the object
+#define osMessageQDef(name, queue_sz, type)   \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), sizeof (type)  }
+#endif
+ 
+/// \brief Access a Message Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+ 
+/// Create and Initialize a Message Queue.
+/// \param[in]     queue_def     queue definition referenced with \ref osMessageQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+ 
+/// Put a Message to a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     info          message information.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+ 
+/// Get a Message or Wait for a Message from a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event information that includes status code.
+/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
+osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+ 
+#endif     // Message Queues available
+ 
+ 
+//  ==== Mail Queue Management Functions ====
+ 
+#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available
+ 
+/// \brief Create a Mail Queue Definition.
+/// \param         name          name of the queue
+/// \param         queue_sz      maximum number of messages in queue
+/// \param         type          data type of a single message element
+/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern const osMailQDef_t os_mailQ_def_##name
+#else                            // define the object
+#define osMailQDef(name, queue_sz, type) \
+const osMailQDef_t os_mailQ_def_##name =  \
+{ (queue_sz), sizeof (type) }
+#endif
+ 
+/// \brief Access a Mail Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMailQ(name)  \
+&os_mailQ_def_##name
+ 
+/// Create and Initialize mail queue.
+/// \param[in]     queue_def     reference to the mail queue definition obtain with \ref osMailQ
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
+ 
+/// Allocate a memory block from a mail.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+ 
+/// Allocate a memory block from a mail and set memory block to zero.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+ 
+/// Put a mail to a queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
+osStatus osMailPut (osMailQId queue_id, void *mail);
+ 
+/// Get a mail from a queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return event that contains mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
+osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+ 
+/// Free a memory block from a mail.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to the memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+ 
+#endif  // Mail Queues available
+ 
+ 
+#ifdef  __cplusplus
+}
+#endif
+ 
+#endif  // _CMSIS_OS_H
diff --git a/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h b/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h
new file mode 100644
index 0000000..c86740d
--- /dev/null
+++ b/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h
@@ -0,0 +1,756 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        18. June 2018
+ * $Revision:    V2.1.3
+ *
+ * Project:      CMSIS-RTOS2 API
+ * Title:        cmsis_os2.h header file
+ *
+ * Version 2.1.3
+ *    Additional functions allowed to be called from Interrupt Service Routines:
+ *    - osThreadGetId
+ * Version 2.1.2
+ *    Additional functions allowed to be called from Interrupt Service Routines:
+ *    - osKernelGetInfo, osKernelGetState
+ * Version 2.1.1
+ *    Additional functions allowed to be called from Interrupt Service Routines:
+ *    - osKernelGetTickCount, osKernelGetTickFreq
+ *    Changed Kernel Tick type to uint32_t:
+ *    - updated: osKernelGetTickCount, osDelayUntil
+ * Version 2.1.0
+ *    Support for critical and uncritical sections (nesting safe):
+ *    - updated: osKernelLock, osKernelUnlock
+ *    - added: osKernelRestoreLock
+ *    Updated Thread and Event Flags:
+ *    - changed flags parameter and return type from int32_t to uint32_t
+ * Version 2.0.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+ 
+#ifndef CMSIS_OS2_H_
+#define CMSIS_OS2_H_
+ 
+#ifndef __NO_RETURN
+#if   defined(__CC_ARM)
+#define __NO_RETURN __declspec(noreturn)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__GNUC__)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__ICCARM__)
+#define __NO_RETURN __noreturn
+#else
+#define __NO_RETURN
+#endif
+#endif
+ 
+#include 
+#include 
+ 
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+ 
+ 
+//  ==== Enumerations, structures, defines ====
+ 
+/// Version information.
+typedef struct {
+  uint32_t                       api;   ///< API version (major.minor.rev: mmnnnrrrr dec).
+  uint32_t                    kernel;   ///< Kernel version (major.minor.rev: mmnnnrrrr dec).
+} osVersion_t;
+ 
+/// Kernel state.
+typedef enum {
+  osKernelInactive        =  0,         ///< Inactive.
+  osKernelReady           =  1,         ///< Ready.
+  osKernelRunning         =  2,         ///< Running.
+  osKernelLocked          =  3,         ///< Locked.
+  osKernelSuspended       =  4,         ///< Suspended.
+  osKernelError           = -1,         ///< Error.
+  osKernelReserved        = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization.
+} osKernelState_t;
+ 
+/// Thread state.
+typedef enum {
+  osThreadInactive        =  0,         ///< Inactive.
+  osThreadReady           =  1,         ///< Ready.
+  osThreadRunning         =  2,         ///< Running.
+  osThreadBlocked         =  3,         ///< Blocked.
+  osThreadTerminated      =  4,         ///< Terminated.
+  osThreadError           = -1,         ///< Error.
+  osThreadReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osThreadState_t;
+ 
+/// Priority values.
+typedef enum {
+  osPriorityNone          =  0,         ///< No priority (not initialized).
+  osPriorityIdle          =  1,         ///< Reserved for Idle thread.
+  osPriorityLow           =  8,         ///< Priority: low
+  osPriorityLow1          =  8+1,       ///< Priority: low + 1
+  osPriorityLow2          =  8+2,       ///< Priority: low + 2
+  osPriorityLow3          =  8+3,       ///< Priority: low + 3
+  osPriorityLow4          =  8+4,       ///< Priority: low + 4
+  osPriorityLow5          =  8+5,       ///< Priority: low + 5
+  osPriorityLow6          =  8+6,       ///< Priority: low + 6
+  osPriorityLow7          =  8+7,       ///< Priority: low + 7
+  osPriorityBelowNormal   = 16,         ///< Priority: below normal
+  osPriorityBelowNormal1  = 16+1,       ///< Priority: below normal + 1
+  osPriorityBelowNormal2  = 16+2,       ///< Priority: below normal + 2
+  osPriorityBelowNormal3  = 16+3,       ///< Priority: below normal + 3
+  osPriorityBelowNormal4  = 16+4,       ///< Priority: below normal + 4
+  osPriorityBelowNormal5  = 16+5,       ///< Priority: below normal + 5
+  osPriorityBelowNormal6  = 16+6,       ///< Priority: below normal + 6
+  osPriorityBelowNormal7  = 16+7,       ///< Priority: below normal + 7
+  osPriorityNormal        = 24,         ///< Priority: normal
+  osPriorityNormal1       = 24+1,       ///< Priority: normal + 1
+  osPriorityNormal2       = 24+2,       ///< Priority: normal + 2
+  osPriorityNormal3       = 24+3,       ///< Priority: normal + 3
+  osPriorityNormal4       = 24+4,       ///< Priority: normal + 4
+  osPriorityNormal5       = 24+5,       ///< Priority: normal + 5
+  osPriorityNormal6       = 24+6,       ///< Priority: normal + 6
+  osPriorityNormal7       = 24+7,       ///< Priority: normal + 7
+  osPriorityAboveNormal   = 32,         ///< Priority: above normal
+  osPriorityAboveNormal1  = 32+1,       ///< Priority: above normal + 1
+  osPriorityAboveNormal2  = 32+2,       ///< Priority: above normal + 2
+  osPriorityAboveNormal3  = 32+3,       ///< Priority: above normal + 3
+  osPriorityAboveNormal4  = 32+4,       ///< Priority: above normal + 4
+  osPriorityAboveNormal5  = 32+5,       ///< Priority: above normal + 5
+  osPriorityAboveNormal6  = 32+6,       ///< Priority: above normal + 6
+  osPriorityAboveNormal7  = 32+7,       ///< Priority: above normal + 7
+  osPriorityHigh          = 40,         ///< Priority: high
+  osPriorityHigh1         = 40+1,       ///< Priority: high + 1
+  osPriorityHigh2         = 40+2,       ///< Priority: high + 2
+  osPriorityHigh3         = 40+3,       ///< Priority: high + 3
+  osPriorityHigh4         = 40+4,       ///< Priority: high + 4
+  osPriorityHigh5         = 40+5,       ///< Priority: high + 5
+  osPriorityHigh6         = 40+6,       ///< Priority: high + 6
+  osPriorityHigh7         = 40+7,       ///< Priority: high + 7
+  osPriorityRealtime      = 48,         ///< Priority: realtime
+  osPriorityRealtime1     = 48+1,       ///< Priority: realtime + 1
+  osPriorityRealtime2     = 48+2,       ///< Priority: realtime + 2
+  osPriorityRealtime3     = 48+3,       ///< Priority: realtime + 3
+  osPriorityRealtime4     = 48+4,       ///< Priority: realtime + 4
+  osPriorityRealtime5     = 48+5,       ///< Priority: realtime + 5
+  osPriorityRealtime6     = 48+6,       ///< Priority: realtime + 6
+  osPriorityRealtime7     = 48+7,       ///< Priority: realtime + 7
+  osPriorityISR           = 56,         ///< Reserved for ISR deferred thread.
+  osPriorityError         = -1,         ///< System cannot determine priority or illegal priority.
+  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osPriority_t;
+ 
+/// Entry point of a thread.
+typedef void (*osThreadFunc_t) (void *argument);
+ 
+/// Timer callback function.
+typedef void (*osTimerFunc_t) (void *argument);
+ 
+/// Timer type.
+typedef enum {
+  osTimerOnce               = 0,          ///< One-shot timer.
+  osTimerPeriodic           = 1           ///< Repeating timer.
+} osTimerType_t;
+ 
+// Timeout value.
+#define osWaitForever         0xFFFFFFFFU ///< Wait forever timeout value.
+ 
+// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait).
+#define osFlagsWaitAny        0x00000000U ///< Wait for any flag (default).
+#define osFlagsWaitAll        0x00000001U ///< Wait for all flags.
+#define osFlagsNoClear        0x00000002U ///< Do not clear flags which have been specified to wait for.
+ 
+// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).
+#define osFlagsError          0x80000000U ///< Error indicator.
+#define osFlagsErrorUnknown   0xFFFFFFFFU ///< osError (-1).
+#define osFlagsErrorTimeout   0xFFFFFFFEU ///< osErrorTimeout (-2).
+#define osFlagsErrorResource  0xFFFFFFFDU ///< osErrorResource (-3).
+#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).
+#define osFlagsErrorISR       0xFFFFFFFAU ///< osErrorISR (-6).
+ 
+// Thread attributes (attr_bits in \ref osThreadAttr_t).
+#define osThreadDetached      0x00000000U ///< Thread created in detached mode (default)
+#define osThreadJoinable      0x00000001U ///< Thread created in joinable mode
+ 
+// Mutex attributes (attr_bits in \ref osMutexAttr_t).
+#define osMutexRecursive      0x00000001U ///< Recursive mutex.
+#define osMutexPrioInherit    0x00000002U ///< Priority inherit protocol.
+#define osMutexRobust         0x00000008U ///< Robust mutex.
+ 
+/// Status code values returned by CMSIS-RTOS functions.
+typedef enum {
+  osOK                      =  0,         ///< Operation completed successfully.
+  osError                   = -1,         ///< Unspecified RTOS error: run-time error but no other error message fits.
+  osErrorTimeout            = -2,         ///< Operation not completed within the timeout period.
+  osErrorResource           = -3,         ///< Resource not available.
+  osErrorParameter          = -4,         ///< Parameter error.
+  osErrorNoMemory           = -5,         ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorISR                = -6,         ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osStatusReserved          = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osStatus_t;
+ 
+ 
+/// \details Thread ID identifies the thread.
+typedef void *osThreadId_t;
+ 
+/// \details Timer ID identifies the timer.
+typedef void *osTimerId_t;
+ 
+/// \details Event Flags ID identifies the event flags.
+typedef void *osEventFlagsId_t;
+ 
+/// \details Mutex ID identifies the mutex.
+typedef void *osMutexId_t;
+ 
+/// \details Semaphore ID identifies the semaphore.
+typedef void *osSemaphoreId_t;
+ 
+/// \details Memory Pool ID identifies the memory pool.
+typedef void *osMemoryPoolId_t;
+ 
+/// \details Message Queue ID identifies the message queue.
+typedef void *osMessageQueueId_t;
+ 
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+ 
+/// Attributes structure for thread.
+typedef struct {
+  const char                   *name;   ///< name of the thread
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                   *stack_mem;    ///< memory for stack
+  uint32_t                stack_size;   ///< size of stack
+  osPriority_t              priority;   ///< initial thread priority (default: osPriorityNormal)
+  TZ_ModuleId_t            tz_module;   ///< TrustZone module identifier
+  uint32_t                  reserved;   ///< reserved (must be 0)
+} osThreadAttr_t;
+ 
+/// Attributes structure for timer.
+typedef struct {
+  const char                   *name;   ///< name of the timer
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osTimerAttr_t;
+ 
+/// Attributes structure for event flags.
+typedef struct {
+  const char                   *name;   ///< name of the event flags
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osEventFlagsAttr_t;
+ 
+/// Attributes structure for mutex.
+typedef struct {
+  const char                   *name;   ///< name of the mutex
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osMutexAttr_t;
+ 
+/// Attributes structure for semaphore.
+typedef struct {
+  const char                   *name;   ///< name of the semaphore
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osSemaphoreAttr_t;
+ 
+/// Attributes structure for memory pool.
+typedef struct {
+  const char                   *name;   ///< name of the memory pool
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                      *mp_mem;    ///< memory for data storage
+  uint32_t                   mp_size;   ///< size of provided memory for data storage 
+} osMemoryPoolAttr_t;
+ 
+/// Attributes structure for message queue.
+typedef struct {
+  const char                   *name;   ///< name of the message queue
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                      *mq_mem;    ///< memory for data storage
+  uint32_t                   mq_size;   ///< size of provided memory for data storage 
+} osMessageQueueAttr_t;
+ 
+ 
+//  ==== Kernel Management Functions ====
+ 
+/// Initialize the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelInitialize (void);
+ 
+///  Get RTOS Kernel Information.
+/// \param[out]    version       pointer to buffer for retrieving version information.
+/// \param[out]    id_buf        pointer to buffer for retrieving kernel identification string.
+/// \param[in]     id_size       size of buffer for kernel identification string.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
+ 
+/// Get the current RTOS Kernel state.
+/// \return current RTOS Kernel state.
+osKernelState_t osKernelGetState (void);
+ 
+/// Start the RTOS Kernel scheduler.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelStart (void);
+ 
+/// Lock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelLock (void);
+ 
+/// Unlock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelUnlock (void);
+ 
+/// Restore the RTOS Kernel scheduler lock state.
+/// \param[in]     lock          lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
+/// \return new lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelRestoreLock (int32_t lock);
+ 
+/// Suspend the RTOS Kernel scheduler.
+/// \return time in ticks, for how long the system can sleep or power-down.
+uint32_t osKernelSuspend (void);
+ 
+/// Resume the RTOS Kernel scheduler.
+/// \param[in]     sleep_ticks   time in ticks for how long the system was in sleep or power-down mode.
+void osKernelResume (uint32_t sleep_ticks);
+ 
+/// Get the RTOS kernel tick count.
+/// \return RTOS kernel current tick count.
+uint32_t osKernelGetTickCount (void);
+ 
+/// Get the RTOS kernel tick frequency.
+/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second.
+uint32_t osKernelGetTickFreq (void);
+ 
+/// Get the RTOS kernel system timer count.
+/// \return RTOS kernel current system timer count as 32-bit value.
+uint32_t osKernelGetSysTimerCount (void);
+ 
+/// Get the RTOS kernel system timer frequency.
+/// \return frequency of the system timer in hertz, i.e. timer ticks per second.
+uint32_t osKernelGetSysTimerFreq (void);
+ 
+ 
+//  ==== Thread Management Functions ====
+ 
+/// Create a thread and add it to Active Threads.
+/// \param[in]     func          thread function.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \param[in]     attr          thread attributes; NULL: default values.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
+ 
+/// Get name of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return name as null-terminated string.
+const char *osThreadGetName (osThreadId_t thread_id);
+ 
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadGetId (void);
+ 
+/// Get current thread state of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current thread state of the specified thread.
+osThreadState_t osThreadGetState (osThreadId_t thread_id);
+ 
+/// Get stack size of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return stack size in bytes.
+uint32_t osThreadGetStackSize (osThreadId_t thread_id);
+ 
+/// Get available stack space of a thread based on stack watermark recording during execution.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return remaining stack space in bytes.
+uint32_t osThreadGetStackSpace (osThreadId_t thread_id);
+ 
+/// Change priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
+ 
+/// Get current priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current priority value of the specified thread.
+osPriority_t osThreadGetPriority (osThreadId_t thread_id);
+ 
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadYield (void);
+ 
+/// Suspend execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSuspend (osThreadId_t thread_id);
+ 
+/// Resume execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadResume (osThreadId_t thread_id);
+ 
+/// Detach a thread (thread storage can be reclaimed when thread terminates).
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadDetach (osThreadId_t thread_id);
+ 
+/// Wait for specified thread to terminate.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadJoin (osThreadId_t thread_id);
+ 
+/// Terminate execution of current running thread.
+__NO_RETURN void osThreadExit (void);
+ 
+/// Terminate execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadTerminate (osThreadId_t thread_id);
+ 
+/// Get number of active threads.
+/// \return number of active threads.
+uint32_t osThreadGetCount (void);
+ 
+/// Enumerate active threads.
+/// \param[out]    thread_array  pointer to array for retrieving thread IDs.
+/// \param[in]     array_items   maximum number of items in array for retrieving thread IDs.
+/// \return number of enumerated threads.
+uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);
+ 
+ 
+//  ==== Thread Flags Functions ====
+ 
+/// Set the specified Thread Flags of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in]     flags         specifies the flags of the thread that shall be set.
+/// \return thread flags after setting or error code if highest bit set.
+uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
+ 
+/// Clear the specified Thread Flags of current running thread.
+/// \param[in]     flags         specifies the flags of the thread that shall be cleared.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsClear (uint32_t flags);
+ 
+/// Get the current Thread Flags of current running thread.
+/// \return current thread flags.
+uint32_t osThreadFlagsGet (void);
+ 
+/// Wait for one or more Thread Flags of the current running thread to become signaled.
+/// \param[in]     flags         specifies the flags to wait for.
+/// \param[in]     options       specifies flags options (osFlagsXxxx).
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
+ 
+ 
+//  ==== Generic Wait Functions ====
+ 
+/// Wait for Timeout (Time Delay).
+/// \param[in]     ticks         \ref CMSIS_RTOS_TimeOutValue "time ticks" value
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelay (uint32_t ticks);
+ 
+/// Wait until specified time.
+/// \param[in]     ticks         absolute time in ticks
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelayUntil (uint32_t ticks);
+ 
+ 
+//  ==== Timer Management Functions ====
+ 
+/// Create and Initialize a timer.
+/// \param[in]     func          function pointer to callback function.
+/// \param[in]     type          \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer callback function.
+/// \param[in]     attr          timer attributes; NULL: default values.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
+ 
+/// Get name of a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return name as null-terminated string.
+const char *osTimerGetName (osTimerId_t timer_id);
+ 
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \param[in]     ticks         \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);
+ 
+/// Stop a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStop (osTimerId_t timer_id);
+ 
+/// Check if a timer is running.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return 0 not running, 1 running.
+uint32_t osTimerIsRunning (osTimerId_t timer_id);
+ 
+/// Delete a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerDelete (osTimerId_t timer_id);
+ 
+ 
+//  ==== Event Flags Management Functions ====
+ 
+/// Create and Initialize an Event Flags object.
+/// \param[in]     attr          event flags attributes; NULL: default values.
+/// \return event flags ID for reference by other functions or NULL in case of error.
+osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);
+ 
+/// Get name of an Event Flags object.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return name as null-terminated string.
+const char *osEventFlagsGetName (osEventFlagsId_t ef_id);
+ 
+/// Set the specified Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags that shall be set.
+/// \return event flags after setting or error code if highest bit set.
+uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
+ 
+/// Clear the specified Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags that shall be cleared.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
+ 
+/// Get the current Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return current event flags.
+uint32_t osEventFlagsGet (osEventFlagsId_t ef_id);
+ 
+/// Wait for one or more Event Flags to become signaled.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags to wait for.
+/// \param[in]     options       specifies flags options (osFlagsXxxx).
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
+ 
+/// Delete an Event Flags object.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);
+ 
+ 
+//  ==== Mutex Management Functions ====
+ 
+/// Create and Initialize a Mutex object.
+/// \param[in]     attr          mutex attributes; NULL: default values.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId_t osMutexNew (const osMutexAttr_t *attr);
+ 
+/// Get name of a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return name as null-terminated string.
+const char *osMutexGetName (osMutexId_t mutex_id);
+ 
+/// Acquire a Mutex or timeout if it is locked.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
+ 
+/// Release a Mutex that was acquired by \ref osMutexAcquire.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexRelease (osMutexId_t mutex_id);
+ 
+/// Get Thread which owns a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return thread ID of owner thread or NULL when mutex was not acquired.
+osThreadId_t osMutexGetOwner (osMutexId_t mutex_id);
+ 
+/// Delete a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexDelete (osMutexId_t mutex_id);
+ 
+ 
+//  ==== Semaphore Management Functions ====
+ 
+/// Create and Initialize a Semaphore object.
+/// \param[in]     max_count     maximum number of available tokens.
+/// \param[in]     initial_count initial number of available tokens.
+/// \param[in]     attr          semaphore attributes; NULL: default values.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
+ 
+/// Get name of a Semaphore object.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return name as null-terminated string.
+const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);
+ 
+/// Acquire a Semaphore token or timeout if no tokens are available.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
+ 
+/// Release a Semaphore token up to the initial maximum count.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);
+ 
+/// Get current Semaphore token count.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return number of tokens available.
+uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);
+ 
+/// Delete a Semaphore object.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);
+ 
+ 
+//  ==== Memory Pool Management Functions ====
+ 
+/// Create and Initialize a Memory Pool object.
+/// \param[in]     block_count   maximum number of memory blocks in memory pool.
+/// \param[in]     block_size    memory block size in bytes.
+/// \param[in]     attr          memory pool attributes; NULL: default values.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
+ 
+/// Get name of a Memory Pool object.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return name as null-terminated string.
+const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);
+ 
+/// Allocate a memory block from a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return address of the allocated memory block or NULL in case of no memory is available.
+void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
+ 
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in]     block         address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
+ 
+/// Get maximum number of memory blocks in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return maximum number of memory blocks.
+uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);
+ 
+/// Get memory block size in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return memory block size in bytes.
+uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);
+ 
+/// Get number of memory blocks used in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks used.
+uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);
+ 
+/// Get number of memory blocks available in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks available.
+uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);
+ 
+/// Delete a Memory Pool object.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);
+ 
+ 
+//  ==== Message Queue Management Functions ====
+ 
+/// Create and Initialize a Message Queue object.
+/// \param[in]     msg_count     maximum number of messages in queue.
+/// \param[in]     msg_size      maximum message size in bytes.
+/// \param[in]     attr          message queue attributes; NULL: default values.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
+ 
+/// Get name of a Message Queue object.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return name as null-terminated string.
+const char *osMessageQueueGetName (osMessageQueueId_t mq_id);
+ 
+/// Put a Message into a Queue or timeout if Queue is full.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \param[in]     msg_ptr       pointer to buffer with message to put into a queue.
+/// \param[in]     msg_prio      message priority.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
+ 
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \param[out]    msg_ptr       pointer to buffer for message to get from a queue.
+/// \param[out]    msg_prio      pointer to buffer for message priority or NULL.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
+ 
+/// Get maximum number of messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum number of messages.
+uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);
+ 
+/// Get maximum message size in a Memory Pool.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum message size in bytes.
+uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);
+ 
+/// Get number of queued messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of queued messages.
+uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);
+ 
+/// Get number of available slots for messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of available slots for messages.
+uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);
+ 
+/// Reset a Message Queue to initial empty state.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);
+ 
+/// Delete a Message Queue object.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
+ 
+ 
+#ifdef  __cplusplus
+}
+#endif
+ 
+#endif  // CMSIS_OS2_H_
diff --git a/Drivers/CMSIS/RTOS2/Include/os_tick.h b/Drivers/CMSIS/RTOS2/Include/os_tick.h
new file mode 100644
index 0000000..dfeb953
--- /dev/null
+++ b/Drivers/CMSIS/RTOS2/Include/os_tick.h
@@ -0,0 +1,71 @@
+/**************************************************************************//**
+ * @file     os_tick.h
+ * @brief    CMSIS OS Tick header file
+ * @version  V1.0.1
+ * @date     24. November 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef OS_TICK_H
+#define OS_TICK_H
+
+#include 
+
+/// IRQ Handler.
+#ifndef IRQHANDLER_T
+#define IRQHANDLER_T
+typedef void (*IRQHandler_t) (void);
+#endif
+
+/// Setup OS Tick timer to generate periodic RTOS Kernel Ticks
+/// \param[in]     freq         tick frequency in Hz
+/// \param[in]     handler      tick IRQ handler
+/// \return 0 on success, -1 on error.
+int32_t  OS_Tick_Setup (uint32_t freq, IRQHandler_t handler);
+
+/// Enable OS Tick timer interrupt
+void     OS_Tick_Enable (void);
+
+/// Disable OS Tick timer interrupt
+void     OS_Tick_Disable (void);
+
+/// Acknowledge execution of OS Tick timer interrupt
+void     OS_Tick_AcknowledgeIRQ (void);
+
+/// Get OS Tick timer IRQ number
+/// \return OS Tick IRQ number
+int32_t  OS_Tick_GetIRQn (void);
+
+/// Get OS Tick timer clock frequency
+/// \return OS Tick timer clock frequency in Hz
+uint32_t OS_Tick_GetClock (void);
+
+/// Get OS Tick timer interval reload value
+/// \return OS Tick timer interval reload value
+uint32_t OS_Tick_GetInterval (void);
+
+/// Get OS Tick timer counter value
+/// \return OS Tick timer counter value
+uint32_t OS_Tick_GetCount (void);
+
+/// Get OS Tick timer overflow status
+/// \return OS Tick overflow status (1 - overflow, 0 - no overflow).
+uint32_t OS_Tick_GetOverflow (void);
+
+#endif  /* OS_TICK_H */
diff --git a/Drivers/CMSIS/RTOS2/Source/os_systick.c b/Drivers/CMSIS/RTOS2/Source/os_systick.c
new file mode 100644
index 0000000..f114caa
--- /dev/null
+++ b/Drivers/CMSIS/RTOS2/Source/os_systick.c
@@ -0,0 +1,132 @@
+/**************************************************************************//**
+ * @file     os_systick.c
+ * @brief    CMSIS OS Tick SysTick implementation
+ * @version  V1.0.1
+ * @date     24. November 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "os_tick.h"
+
+//lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer"
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifdef  SysTick
+
+#ifndef SYSTICK_IRQ_PRIORITY
+#define SYSTICK_IRQ_PRIORITY    0xFFU
+#endif
+
+static uint8_t PendST;
+
+// Setup OS Tick.
+__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {
+  uint32_t load;
+  (void)handler;
+
+  if (freq == 0U) {
+    //lint -e{904} "Return statement before end of function"
+    return (-1);
+  }
+
+  load = (SystemCoreClock / freq) - 1U;
+  if (load > 0x00FFFFFFU) {
+    //lint -e{904} "Return statement before end of function"
+    return (-1);
+  }
+
+  // Set SysTick Interrupt Priority
+#if   ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
+       (defined(__CORTEX_M)           && (__CORTEX_M           == 7U)))
+  SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY;
+#elif  (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
+  SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);
+#elif ((defined(__ARM_ARCH_7M__)      && (__ARM_ARCH_7M__      != 0)) || \
+       (defined(__ARM_ARCH_7EM__)     && (__ARM_ARCH_7EM__     != 0)))
+  SCB->SHP[11]  = SYSTICK_IRQ_PRIORITY;
+#elif  (defined(__ARM_ARCH_6M__)      && (__ARM_ARCH_6M__      != 0))
+  SCB->SHP[1]  |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);
+#else
+#error "Unknown ARM Core!"
+#endif
+
+  SysTick->CTRL =  SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk;
+  SysTick->LOAD =  load;
+  SysTick->VAL  =  0U;
+
+  PendST = 0U;
+
+  return (0);
+}
+
+/// Enable OS Tick.
+__WEAK void OS_Tick_Enable (void) {
+
+  if (PendST != 0U) {
+    PendST = 0U;
+    SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
+  }
+
+  SysTick->CTRL |=  SysTick_CTRL_ENABLE_Msk;
+}
+
+/// Disable OS Tick.
+__WEAK void OS_Tick_Disable (void) {
+
+  SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+
+  if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) {
+    SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
+    PendST = 1U;
+  }
+}
+
+// Acknowledge OS Tick IRQ.
+__WEAK void OS_Tick_AcknowledgeIRQ (void) {
+  (void)SysTick->CTRL;
+}
+
+// Get OS Tick IRQ number.
+__WEAK int32_t  OS_Tick_GetIRQn (void) {
+  return ((int32_t)SysTick_IRQn);
+}
+
+// Get OS Tick clock.
+__WEAK uint32_t OS_Tick_GetClock (void) {
+  return (SystemCoreClock);
+}
+
+// Get OS Tick interval.
+__WEAK uint32_t OS_Tick_GetInterval (void) {
+  return (SysTick->LOAD + 1U);
+}
+
+// Get OS Tick count value.
+__WEAK uint32_t OS_Tick_GetCount (void) {
+  uint32_t load = SysTick->LOAD;
+  return  (load - SysTick->VAL);
+}
+
+// Get OS Tick overflow status.
+__WEAK uint32_t OS_Tick_GetOverflow (void) {
+  return ((SysTick->CTRL >> 16) & 1U);
+}
+
+#endif  // SysTick
diff --git a/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c b/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c
new file mode 100644
index 0000000..1778ab7
--- /dev/null
+++ b/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c
@@ -0,0 +1,187 @@
+/**************************************************************************//**
+ * @file     os_tick_gtim.c
+ * @brief    CMSIS OS Tick implementation for Generic Timer
+ * @version  V1.0.1
+ * @date     24. November 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "os_tick.h"
+#include "irq_ctrl.h"
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#ifndef GTIM_IRQ_PRIORITY
+#define GTIM_IRQ_PRIORITY           0xFFU
+#endif
+
+#ifndef GTIM_IRQ_NUM
+#define GTIM_IRQ_NUM                SecurePhyTimer_IRQn
+#endif
+
+// Timer interrupt pending flag
+static uint8_t GTIM_PendIRQ;
+
+// Timer tick frequency
+static uint32_t GTIM_Clock;
+
+// Timer load value
+static uint32_t GTIM_Load;
+
+// Setup OS Tick.
+int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {
+  uint32_t prio, bits;
+
+  if (freq == 0U) {
+    return (-1);
+  }
+
+  GTIM_PendIRQ = 0U;
+
+  // Get timer clock
+#ifdef SCTR_BASE
+  GTIM_Clock = *(uint32_t*)(SCTR_BASE+0x20);
+#else
+  // FVP REFCLK CNTControl 100MHz
+  GTIM_Clock = 100000000UL;
+#endif
+
+  PL1_SetCounterFrequency(GTIM_Clock);
+
+  // Calculate load value
+  GTIM_Load = (GTIM_Clock / freq) - 1U;
+
+  // Disable Generic Timer and set load value
+  PL1_SetControl(0U);
+  PL1_SetLoadValue(GTIM_Load);
+
+  // Disable corresponding IRQ
+  IRQ_Disable(GTIM_IRQ_NUM);
+  IRQ_ClearPending(GTIM_IRQ_NUM);
+
+  // Determine number of implemented priority bits
+  IRQ_SetPriority(GTIM_IRQ_NUM, 0xFFU);
+
+  prio = IRQ_GetPriority(GTIM_IRQ_NUM);
+
+  // At least bits [7:4] must be implemented
+  if ((prio & 0xF0U) == 0U) {
+    return (-1);
+  }
+
+  for (bits = 0; bits < 4; bits++) {
+    if ((prio & 0x01) != 0) {
+      break;
+    }
+    prio >>= 1;
+  }
+  
+  // Adjust configured priority to the number of implemented priority bits
+  prio = (GTIM_IRQ_PRIORITY << bits) & 0xFFUL;
+
+  // Set Private Timer interrupt priority
+  IRQ_SetPriority(GTIM_IRQ_NUM, prio-1U);
+
+  // Set edge-triggered IRQ
+  IRQ_SetMode(GTIM_IRQ_NUM, IRQ_MODE_TRIG_EDGE);
+
+  // Register tick interrupt handler function
+  IRQ_SetHandler(GTIM_IRQ_NUM, handler);
+
+  // Enable corresponding interrupt
+  IRQ_Enable(GTIM_IRQ_NUM);
+
+  // Enable system counter and timer control
+#ifdef SCTR_BASE
+  *(uint32_t*)SCTR_BASE |= 3U;
+#endif
+
+  // Enable timer control
+  PL1_SetControl(1U);
+
+  return (0);
+}
+
+/// Enable OS Tick.
+void OS_Tick_Enable (void) {
+  uint32_t ctrl;
+
+  // Set pending interrupt if flag set
+  if (GTIM_PendIRQ != 0U) {
+    GTIM_PendIRQ = 0U;
+    IRQ_SetPending (GTIM_IRQ_NUM);
+  }
+
+  // Start the Private Timer
+  ctrl = PL1_GetControl();
+  // Set bit: Timer enable
+  ctrl |= 1U;
+  PL1_SetControl(ctrl);
+}
+
+/// Disable OS Tick.
+void OS_Tick_Disable (void) {
+  uint32_t ctrl;
+
+  // Stop the Private Timer
+  ctrl = PL1_GetControl();
+  // Clear bit: Timer enable
+  ctrl &= ~1U;
+  PL1_SetControl(ctrl);
+
+  // Remember pending interrupt flag
+  if (IRQ_GetPending(GTIM_IRQ_NUM) != 0) {
+    IRQ_ClearPending(GTIM_IRQ_NUM);
+    GTIM_PendIRQ = 1U;
+  }
+}
+
+// Acknowledge OS Tick IRQ.
+void OS_Tick_AcknowledgeIRQ (void) {
+  IRQ_ClearPending (GTIM_IRQ_NUM);
+  PL1_SetLoadValue(GTIM_Load);
+}
+
+// Get OS Tick IRQ number.
+int32_t  OS_Tick_GetIRQn (void) {
+  return (GTIM_IRQ_NUM);
+}
+
+// Get OS Tick clock.
+uint32_t OS_Tick_GetClock (void) {
+  return (GTIM_Clock);
+}
+
+// Get OS Tick interval.
+uint32_t OS_Tick_GetInterval (void) {
+  return (GTIM_Load + 1U);
+}
+
+// Get OS Tick count value.
+uint32_t OS_Tick_GetCount (void) {
+  return (GTIM_Load - PL1_GetCurrentValue());
+}
+
+// Get OS Tick overflow status.
+uint32_t OS_Tick_GetOverflow (void) {
+  CNTP_CTL_Type cntp_ctl;
+  cntp_ctl.w = PL1_GetControl();
+  return (cntp_ctl.b.ISTATUS);
+}
diff --git a/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c b/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c
new file mode 100644
index 0000000..ccd9cb6
--- /dev/null
+++ b/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c
@@ -0,0 +1,165 @@
+/**************************************************************************//**
+ * @file     os_tick_ptim.c
+ * @brief    CMSIS OS Tick implementation for Private Timer
+ * @version  V1.0.2
+ * @date     02. March 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#if defined(PTIM)
+
+#include "os_tick.h"
+#include "irq_ctrl.h"
+
+#ifndef PTIM_IRQ_PRIORITY
+#define PTIM_IRQ_PRIORITY           0xFFU
+#endif
+
+static uint8_t PTIM_PendIRQ;        // Timer interrupt pending flag
+
+// Setup OS Tick.
+int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {
+  uint32_t load;
+  uint32_t prio;
+  uint32_t bits;
+
+  if (freq == 0U) {
+    return (-1);
+  }
+
+  PTIM_PendIRQ = 0U;
+
+  // Private Timer runs with the system frequency
+  load = (SystemCoreClock / freq) - 1U;
+
+  // Disable Private Timer and set load value
+  PTIM_SetControl   (0U);
+  PTIM_SetLoadValue (load);
+
+  // Disable corresponding IRQ
+  IRQ_Disable     (PrivTimer_IRQn);
+  IRQ_ClearPending(PrivTimer_IRQn);
+
+  // Determine number of implemented priority bits
+  IRQ_SetPriority (PrivTimer_IRQn, 0xFFU);
+
+  prio = IRQ_GetPriority (PrivTimer_IRQn);
+
+  // At least bits [7:4] must be implemented
+  if ((prio & 0xF0U) == 0U) {
+    return (-1);
+  }
+
+  for (bits = 0; bits < 4; bits++) {
+    if ((prio & 0x01) != 0) {
+      break;
+    }
+    prio >>= 1;
+  }
+
+  // Adjust configured priority to the number of implemented priority bits
+  prio = (PTIM_IRQ_PRIORITY << bits) & 0xFFUL;
+
+  // Set Private Timer interrupt priority
+  IRQ_SetPriority(PrivTimer_IRQn, prio-1U);
+
+  // Set edge-triggered IRQ
+  IRQ_SetMode(PrivTimer_IRQn, IRQ_MODE_TRIG_EDGE);
+
+  // Register tick interrupt handler function
+  IRQ_SetHandler(PrivTimer_IRQn, handler);
+
+  // Enable corresponding interrupt
+  IRQ_Enable (PrivTimer_IRQn);
+
+  // Set bits: IRQ enable and Auto reload
+  PTIM_SetControl (0x06U);
+
+  return (0);
+}
+
+/// Enable OS Tick.
+void OS_Tick_Enable (void) {
+  uint32_t ctrl;
+
+  // Set pending interrupt if flag set
+  if (PTIM_PendIRQ != 0U) {
+    PTIM_PendIRQ = 0U;
+    IRQ_SetPending (PrivTimer_IRQn);
+  }
+
+  // Start the Private Timer
+  ctrl  = PTIM_GetControl();
+  // Set bit: Timer enable
+  ctrl |= 1U;
+  PTIM_SetControl (ctrl);
+}
+
+/// Disable OS Tick.
+void OS_Tick_Disable (void) {
+  uint32_t ctrl;
+
+  // Stop the Private Timer
+  ctrl  = PTIM_GetControl();
+  // Clear bit: Timer enable
+  ctrl &= ~1U;
+  PTIM_SetControl (ctrl);
+
+  // Remember pending interrupt flag
+  if (IRQ_GetPending(PrivTimer_IRQn) != 0) {
+    IRQ_ClearPending (PrivTimer_IRQn);
+    PTIM_PendIRQ = 1U;
+  }
+}
+
+// Acknowledge OS Tick IRQ.
+void OS_Tick_AcknowledgeIRQ (void) {
+  PTIM_ClearEventFlag();
+}
+
+// Get OS Tick IRQ number.
+int32_t  OS_Tick_GetIRQn (void) {
+  return (PrivTimer_IRQn);
+}
+
+// Get OS Tick clock.
+uint32_t OS_Tick_GetClock (void) {
+  return (SystemCoreClock);
+}
+
+// Get OS Tick interval.
+uint32_t OS_Tick_GetInterval (void) {
+  return (PTIM_GetLoadValue() + 1U);
+}
+
+// Get OS Tick count value.
+uint32_t OS_Tick_GetCount (void) {
+  uint32_t load = PTIM_GetLoadValue();
+  return  (load - PTIM_GetCurrentValue());
+}
+
+// Get OS Tick overflow status.
+uint32_t OS_Tick_GetOverflow (void) {
+  return (PTIM->ISR & 1);
+}
+
+#endif  // PTIM
diff --git a/Drivers/CMSIS/RTOS2/Template/cmsis_os.h b/Drivers/CMSIS/RTOS2/Template/cmsis_os.h
new file mode 100644
index 0000000..5447842
--- /dev/null
+++ b/Drivers/CMSIS/RTOS2/Template/cmsis_os.h
@@ -0,0 +1,922 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        18. June 2018
+ * $Revision:    V2.1.3
+ *
+ * Project:      CMSIS-RTOS API
+ * Title:        cmsis_os.h template header file
+ *
+ * Version 0.02
+ *    Initial Proposal Phase
+ * Version 0.03
+ *    osKernelStart added, optional feature: main started as thread
+ *    osSemaphores have standard behavior
+ *    osTimerCreate does not start the timer, added osTimerStart
+ *    osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ *    Support for C++ interface
+ *     - const attribute removed from the osXxxxDef_t typedefs
+ *     - const attribute added to the osXxxxDef macros
+ *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ *    Added: osKernelInitialize
+ * Version 1.02
+ *    Control functions for short timeouts in microsecond resolution:
+ *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
+ *    Removed: osSignalGet 
+ * Version 2.0.0
+ *    OS objects creation without macros (dynamic creation and resource allocation):
+ *     - added: osXxxxNew functions which replace osXxxxCreate
+ *     - added: osXxxxAttr_t structures
+ *     - deprecated: osXxxxCreate functions, osXxxxDef_t structures
+ *     - deprecated: osXxxxDef and osXxxx macros
+ *    osStatus codes simplified and renamed to osStatus_t
+ *    osEvent return structure deprecated
+ *    Kernel:
+ *     - added: osKernelInfo_t and osKernelGetInfo
+ *     - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)
+ *     - added: osKernelLock, osKernelUnlock
+ *     - added: osKernelSuspend, osKernelResume
+ *     - added: osKernelGetTickCount, osKernelGetTickFreq
+ *     - renamed osKernelSysTick to osKernelGetSysTimerCount
+ *     - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq
+ *     - deprecated osKernelSysTickMicroSec
+ *    Thread:
+ *     - extended number of thread priorities
+ *     - renamed osPrioriry to osPrioriry_t
+ *     - replaced osThreadCreate with osThreadNew
+ *     - added: osThreadGetName
+ *     - added: osThreadState_t and osThreadGetState
+ *     - added: osThreadGetStackSize, osThreadGetStackSpace
+ *     - added: osThreadSuspend, osThreadResume
+ *     - added: osThreadJoin, osThreadDetach, osThreadExit
+ *     - added: osThreadGetCount, osThreadEnumerate
+ *     - added: Thread Flags (moved from Signals) 
+ *    Signals:
+ *     - renamed osSignals to osThreadFlags (moved to Thread Flags)
+ *     - changed return value of Set/Clear/Wait functions
+ *     - Clear function limited to current running thread
+ *     - extended Wait function (options)
+ *     - added: osThreadFlagsGet
+ *    Event Flags:
+ *     - added new independent object for handling Event Flags
+ *    Delay and Wait functions:
+ *     - added: osDelayUntil
+ *     - deprecated: osWait
+ *    Timer:
+ *     - replaced osTimerCreate with osTimerNew
+ *     - added: osTimerGetName, osTimerIsRunning
+ *    Mutex:
+ *     - extended: attributes (Recursive, Priority Inherit, Robust)
+ *     - replaced osMutexCreate with osMutexNew
+ *     - renamed osMutexWait to osMutexAcquire
+ *     - added: osMutexGetName, osMutexGetOwner
+ *    Semaphore:
+ *     - extended: maximum and initial token count
+ *     - replaced osSemaphoreCreate with osSemaphoreNew
+ *     - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)
+ *     - added: osSemaphoreGetName, osSemaphoreGetCount
+ *    Memory Pool:
+ *     - using osMemoryPool prefix instead of osPool
+ *     - replaced osPoolCreate with osMemoryPoolNew
+ *     - extended osMemoryPoolAlloc (timeout)
+ *     - added: osMemoryPoolGetName
+ *     - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize
+ *     - added: osMemoryPoolGetCount, osMemoryPoolGetSpace
+ *     - added: osMemoryPoolDelete
+ *     - deprecated: osPoolCAlloc
+ *    Message Queue:
+ *     - extended: fixed size message instead of a single 32-bit value
+ *     - using osMessageQueue prefix instead of osMessage
+ *     - replaced osMessageCreate with osMessageQueueNew
+ *     - updated: osMessageQueuePut, osMessageQueueGet
+ *     - added: osMessageQueueGetName
+ *     - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize
+ *     - added: osMessageQueueGetCount, osMessageQueueGetSpace
+ *     - added: osMessageQueueReset, osMessageQueueDelete
+ *    Mail Queue: 
+ *     - deprecated (superseded by extended Message Queue functionality)
+ * Version 2.1.0
+ *    Support for critical and uncritical sections (nesting safe):
+ *    - updated: osKernelLock, osKernelUnlock
+ *    - added: osKernelRestoreLock
+ *    Updated Thread and Event Flags:
+ *    - changed flags parameter and return type from int32_t to uint32_t
+ * Version 2.1.1
+ *    Additional functions allowed to be called from Interrupt Service Routines:
+ *    - osKernelGetTickCount, osKernelGetTickFreq
+ *    Changed Kernel Tick type to uint32_t:
+ *    - updated: osKernelGetTickCount, osDelayUntil
+ * Version 2.1.2
+ *    Additional functions allowed to be called from Interrupt Service Routines:
+ *    - osKernelGetInfo, osKernelGetState
+ * Version 2.1.3
+ *    Additional functions allowed to be called from Interrupt Service Routines:
+ *    - osThreadGetId
+ *---------------------------------------------------------------------------*/
+ 
+#ifndef CMSIS_OS_H_
+#define CMSIS_OS_H_
+ 
+/// \b osCMSIS identifies the CMSIS-RTOS API version.
+#define osCMSIS             0x20001U    ///< API version (main[31:16].sub[15:0])
+ 
+/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
+#define osCMSIS_KERNEL      0x10000U    ///< RTOS identification and version (main[31:16].sub[15:0])
+ 
+/// \note CAN BE CHANGED: \b osKernelSystemId identifies the underlying RTOS kernel.
+#define osKernelSystemId "KERNEL V1.0"  ///< RTOS identification string
+ 
+/// \note CAN BE CHANGED: \b osFeature_xxx identifies RTOS features.
+#define osFeature_MainThread  0         ///< main thread      1=main can be thread, 0=not available
+#define osFeature_Signals     16U       ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore   65535U    ///< maximum count for \ref osSemaphoreCreate function
+#define osFeature_Wait        0         ///< osWait function: 1=available, 0=not available
+#define osFeature_SysTick     1         ///< osKernelSysTick functions: 1=available, 0=not available
+#define osFeature_Pool        1         ///< Memory Pools:    1=available, 0=not available
+#define osFeature_MessageQ    1         ///< Message Queues:  1=available, 0=not available
+#define osFeature_MailQ       1         ///< Mail Queues:     1=available, 0=not available
+ 
+#if (osCMSIS >= 0x20000U)
+#include "cmsis_os2.h"
+#else
+#include 
+#include 
+#endif
+ 
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+ 
+ 
+// ==== Enumerations, structures, defines ====
+ 
+/// Priority values.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+  osPriorityIdle          = -3,         ///< Priority: idle (lowest)
+  osPriorityLow           = -2,         ///< Priority: low
+  osPriorityBelowNormal   = -1,         ///< Priority: below normal
+  osPriorityNormal        =  0,         ///< Priority: normal (default)
+  osPriorityAboveNormal   = +1,         ///< Priority: above normal
+  osPriorityHigh          = +2,         ///< Priority: high
+  osPriorityRealtime      = +3,         ///< Priority: realtime (highest)
+  osPriorityError         = 0x84,       ///< System cannot determine priority or illegal priority.
+  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osPriority;
+#else
+#define osPriority osPriority_t
+#endif
+
+/// Entry point of a thread.
+typedef void (*os_pthread) (void const *argument);
+ 
+/// Entry point of a timer call back function.
+typedef void (*os_ptimer) (void const *argument);
+ 
+/// Timer type.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+  osTimerOnce             = 0,          ///< One-shot timer.
+  osTimerPeriodic         = 1           ///< Repeating timer.
+} os_timer_type;
+#else
+#define os_timer_type osTimerType_t
+#endif
+ 
+/// Timeout value.
+#define osWaitForever       0xFFFFFFFFU ///< Wait forever timeout value.
+ 
+/// Status code values returned by CMSIS-RTOS functions.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+  osOK                    =    0,       ///< Function completed; no error or event occurred.
+  osEventSignal           = 0x08,       ///< Function completed; signal event occurred.
+  osEventMessage          = 0x10,       ///< Function completed; message event occurred.
+  osEventMail             = 0x20,       ///< Function completed; mail event occurred.
+  osEventTimeout          = 0x40,       ///< Function completed; timeout occurred.
+  osErrorParameter        = 0x80,       ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.
+  osErrorResource         = 0x81,       ///< Resource not available: a specified resource was not available.
+  osErrorTimeoutResource  = 0xC1,       ///< Resource not available within given time: a specified resource was not available within the timeout period.
+  osErrorISR              = 0x82,       ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osErrorISRRecursive     = 0x83,       ///< Function called multiple times from ISR with same object.
+  osErrorPriority         = 0x84,       ///< System cannot determine priority or thread has illegal priority.
+  osErrorNoMemory         = 0x85,       ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorValue            = 0x86,       ///< Value of a parameter is out of range.
+  osErrorOS               = 0xFF,       ///< Unspecified RTOS error: run-time error but no other error message fits.
+  osStatusReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osStatus;
+#else
+typedef int32_t                  osStatus;
+#define osEventSignal           (0x08)
+#define osEventMessage          (0x10)
+#define osEventMail             (0x20)
+#define osEventTimeout          (0x40)
+#define osErrorOS               osError
+#define osErrorTimeoutResource  osErrorTimeout
+#define osErrorISRRecursive     (-126)
+#define osErrorValue            (-127)
+#define osErrorPriority         (-128)
+#endif
+ 
+ 
+// >>> the following data type definitions may be adapted towards a specific RTOS
+ 
+/// Thread ID identifies the thread.
+/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
+#if (osCMSIS < 0x20000U)
+typedef void *osThreadId;
+#else
+#define osThreadId osThreadId_t
+#endif
+ 
+/// Timer ID identifies the timer.
+/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
+#if (osCMSIS < 0x20000U)
+typedef void *osTimerId;
+#else
+#define osTimerId osTimerId_t
+#endif
+ 
+/// Mutex ID identifies the mutex.
+/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
+#if (osCMSIS < 0x20000U)
+typedef void *osMutexId;
+#else
+#define osMutexId osMutexId_t
+#endif
+ 
+/// Semaphore ID identifies the semaphore.
+/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
+#if (osCMSIS < 0x20000U)
+typedef void *osSemaphoreId;
+#else
+#define osSemaphoreId osSemaphoreId_t
+#endif
+ 
+/// Pool ID identifies the memory pool.
+/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
+typedef void *osPoolId;
+ 
+/// Message ID identifies the message queue.
+/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
+typedef void *osMessageQId;
+ 
+/// Mail ID identifies the mail queue.
+/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
+typedef void *osMailQId;
+ 
+ 
+/// Thread Definition structure contains startup information of a thread.
+/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
+#if (osCMSIS < 0x20000U)
+typedef struct os_thread_def {
+  os_pthread                 pthread;   ///< start address of thread function
+  osPriority               tpriority;   ///< initial thread priority
+  uint32_t                 instances;   ///< maximum number of instances of that thread function
+  uint32_t                 stacksize;   ///< stack size requirements in bytes; 0 is default stack size
+} osThreadDef_t;
+#else
+typedef struct os_thread_def {
+  os_pthread                 pthread;   ///< start address of thread function
+  osThreadAttr_t                attr;   ///< thread attributes
+} osThreadDef_t;
+#endif
+ 
+/// Timer Definition structure contains timer parameters.
+/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
+#if (osCMSIS < 0x20000U)
+typedef struct os_timer_def {
+  os_ptimer                   ptimer;   ///< start address of a timer function
+} osTimerDef_t;
+#else
+typedef struct os_timer_def {
+  os_ptimer                   ptimer;   ///< start address of a timer function
+  osTimerAttr_t                 attr;   ///< timer attributes
+} osTimerDef_t;
+#endif
+ 
+/// Mutex Definition structure contains setup information for a mutex.
+/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
+#if (osCMSIS < 0x20000U)
+typedef struct os_mutex_def {
+  uint32_t                     dummy;   ///< dummy value
+} osMutexDef_t;
+#else
+#define osMutexDef_t osMutexAttr_t
+#endif
+ 
+/// Semaphore Definition structure contains setup information for a semaphore.
+/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
+#if (osCMSIS < 0x20000U)
+typedef struct os_semaphore_def {
+  uint32_t                     dummy;   ///< dummy value
+} osSemaphoreDef_t;
+#else
+#define osSemaphoreDef_t osSemaphoreAttr_t
+#endif
+ 
+/// Definition structure for memory block allocation.
+/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
+#if (osCMSIS < 0x20000U)
+typedef struct os_pool_def {
+  uint32_t                   pool_sz;   ///< number of items (elements) in the pool
+  uint32_t                   item_sz;   ///< size of an item
+  void                         *pool;   ///< pointer to memory for pool
+} osPoolDef_t;
+#else
+typedef struct os_pool_def {
+  uint32_t                   pool_sz;   ///< number of items (elements) in the pool
+  uint32_t                   item_sz;   ///< size of an item
+  osMemoryPoolAttr_t            attr;   ///< memory pool attributes
+} osPoolDef_t;
+#endif
+ 
+/// Definition structure for message queue.
+/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
+#if (osCMSIS < 0x20000U)
+typedef struct os_messageQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  void                         *pool;   ///< memory array for messages
+} osMessageQDef_t;
+#else
+typedef struct os_messageQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  osMessageQueueAttr_t          attr;   ///< message queue attributes
+} osMessageQDef_t;
+#endif
+ 
+/// Definition structure for mail queue.
+/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
+#if (osCMSIS < 0x20000U)
+typedef struct os_mailQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  uint32_t                   item_sz;   ///< size of an item
+  void                         *pool;   ///< memory array for mail
+} osMailQDef_t;
+#else
+typedef struct os_mailQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  uint32_t                   item_sz;   ///< size of an item
+  void                         *mail;   ///< pointer to mail
+  osMemoryPoolAttr_t         mp_attr;   ///< memory pool attributes
+  osMessageQueueAttr_t       mq_attr;   ///< message queue attributes
+} osMailQDef_t;
+#endif
+ 
+ 
+/// Event structure contains detailed information about an event.
+typedef struct {
+  osStatus                    status;   ///< status code: event or error information
+  union {
+    uint32_t                       v;   ///< message as 32-bit value
+    void                          *p;   ///< message or mail as void pointer
+    int32_t                  signals;   ///< signal flags
+  } value;                              ///< event value
+  union {
+    osMailQId                mail_id;   ///< mail id obtained by \ref osMailCreate
+    osMessageQId          message_id;   ///< message id obtained by \ref osMessageCreate
+  } def;                                ///< event definition
+} osEvent;
+ 
+ 
+//  ==== Kernel Management Functions ====
+ 
+/// Initialize the RTOS Kernel for creating objects.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osKernelInitialize (void);
+#endif
+ 
+/// Start the RTOS Kernel scheduler.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osKernelStart (void);
+#endif
+ 
+/// Check if the RTOS kernel is already started.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+#if (osCMSIS < 0x20000U)
+int32_t osKernelRunning(void);
+#endif
+ 
+#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0))  // System Timer available
+ 
+/// Get the RTOS kernel system timer counter.
+/// \return RTOS kernel system timer as 32-bit value 
+#if (osCMSIS < 0x20000U)
+uint32_t osKernelSysTick (void);
+#else
+#define  osKernelSysTick osKernelGetSysTimerCount
+#endif
+ 
+/// The RTOS kernel system timer frequency in Hz.
+/// \note Reflects the system timer setting and is typically defined in a configuration file.
+#if (osCMSIS < 0x20000U)
+#define osKernelSysTickFrequency 100000000
+#endif
+ 
+/// Convert a microseconds value to a RTOS kernel system timer value.
+/// \param         microsec     time value in microseconds.
+/// \return time value normalized to the \ref osKernelSysTickFrequency
+#if (osCMSIS < 0x20000U)
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
+#else
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec *  osKernelGetSysTimerFreq()) / 1000000)
+#endif
+ 
+#endif  // System Timer available
+ 
+ 
+//  ==== Thread Management Functions ====
+ 
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param         name          name of the thread function.
+/// \param         priority      initial priority of the thread function.
+/// \param         instances     number of possible thread instances.
+/// \param         stacksz       stack size (in bytes) requirements for the thread function.
+/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osThreadDef(name, priority, instances, stacksz) \
+extern const osThreadDef_t os_thread_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osThreadDef(name, priority, instances, stacksz) \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), (priority), (instances), (stacksz) }
+#else
+#define osThreadDef(name, priority, instances, stacksz) \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), \
+  { NULL, osThreadDetached, NULL, 0U, NULL, 8*((stacksz+7)/8), (priority), 0U, 0U } }
+#endif
+#endif
+ 
+/// Access a Thread definition.
+/// \param         name          name of the thread definition object.
+/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osThread(name) \
+&os_thread_def_##name
+ 
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in]     thread_def    thread definition referenced with \ref osThread.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
+ 
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+#if (osCMSIS < 0x20000U)
+osThreadId osThreadGetId (void);
+#endif
+ 
+/// Change priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+#endif
+ 
+/// Get current priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the specified thread.
+#if (osCMSIS < 0x20000U)
+osPriority osThreadGetPriority (osThreadId thread_id);
+#endif
+ 
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadYield (void);
+#endif
+ 
+/// Terminate execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadTerminate (osThreadId thread_id);
+#endif
+ 
+ 
+//  ==== Signal Management ====
+ 
+/// Set the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+int32_t osSignalSet (osThreadId thread_id, int32_t signals);
+ 
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
+int32_t osSignalClear (osThreadId thread_id, int32_t signals);
+ 
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flag information or error code.
+osEvent osSignalWait (int32_t signals, uint32_t millisec);
+ 
+ 
+//  ==== Generic Wait Functions ====
+ 
+/// Wait for Timeout (Time Delay).
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osDelay (uint32_t millisec);
+#endif
+ 
+#if (defined (osFeature_Wait) && (osFeature_Wait != 0))  // Generic Wait available
+ 
+/// Wait for Signal, Message, Mail, or Timeout.
+/// \param[in] millisec          \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+osEvent osWait (uint32_t millisec);
+ 
+#endif  // Generic Wait available
+ 
+ 
+//  ==== Timer Management Functions ====
+ 
+/// Define a Timer object.
+/// \param         name          name of the timer object.
+/// \param         function      name of the timer call back function.
+/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osTimerDef(name, function) \
+extern const osTimerDef_t os_timer_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osTimerDef(name, function) \
+const osTimerDef_t os_timer_def_##name = { (function) }
+#else
+#define osTimerDef(name, function) \
+const osTimerDef_t os_timer_def_##name = \
+{ (function), { NULL, 0U, NULL, 0U } }
+#endif
+#endif
+ 
+/// Access a Timer definition.
+/// \param         name          name of the timer object.
+/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osTimer(name) \
+&os_timer_def_##name
+ 
+/// Create and Initialize a timer.
+/// \param[in]     timer_def     timer object referenced with \ref osTimer.
+/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
+ 
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+#endif
+ 
+/// Stop a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerStop (osTimerId timer_id);
+#endif
+ 
+/// Delete a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerDelete (osTimerId timer_id);
+#endif
+ 
+ 
+//  ==== Mutex Management Functions ====
+ 
+/// Define a Mutex.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMutexDef(name) \
+extern const osMutexDef_t os_mutex_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osMutexDef(name) \
+const osMutexDef_t os_mutex_def_##name = { 0 }
+#else
+#define osMutexDef(name) \
+const osMutexDef_t os_mutex_def_##name = \
+{ NULL, osMutexRecursive | osMutexPrioInherit | osMutexRobust, NULL, 0U }
+#endif
+#endif
+ 
+/// Access a Mutex definition.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMutex(name) \
+&os_mutex_def_##name
+ 
+/// Create and Initialize a Mutex object.
+/// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
+ 
+/// Wait until a Mutex becomes available.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+#else
+#define  osMutexWait osMutexAcquire
+#endif
+ 
+/// Release a Mutex that was obtained by \ref osMutexWait.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexRelease (osMutexId mutex_id);
+#endif
+ 
+/// Delete a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexDelete (osMutexId mutex_id);
+#endif
+ 
+ 
+//  ==== Semaphore Management Functions ====
+ 
+#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U))  // Semaphore available
+ 
+/// Define a Semaphore object.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osSemaphoreDef(name) \
+extern const osSemaphoreDef_t os_semaphore_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osSemaphoreDef(name) \
+const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
+#else
+#define osSemaphoreDef(name) \
+const osSemaphoreDef_t os_semaphore_def_##name = \
+{ NULL, 0U, NULL, 0U }
+#endif
+#endif
+ 
+/// Access a Semaphore definition.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osSemaphore(name) \
+&os_semaphore_def_##name
+ 
+/// Create and Initialize a Semaphore object.
+/// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in]     count         maximum and initial number of available tokens.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
+ 
+/// Wait until a Semaphore token becomes available.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+ 
+/// Release a Semaphore token.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+#endif
+ 
+/// Delete a Semaphore object.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
+#endif
+ 
+#endif  // Semaphore available
+ 
+ 
+//  ==== Memory Pool Management Functions ====
+ 
+#if (defined(osFeature_Pool) && (osFeature_Pool != 0))  // Memory Pool available
+ 
+/// \brief Define a Memory Pool.
+/// \param         name          name of the memory pool.
+/// \param         no            maximum number of blocks (objects) in the memory pool.
+/// \param         type          data type of a single block (object).
+/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osPoolDef(name, no, type) \
+extern const osPoolDef_t os_pool_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osPoolDef(name, no, type) \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), NULL }
+#else
+#define osPoolDef(name, no, type) \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), { NULL, 0U, NULL, 0U, NULL, 0U } }
+#endif
+#endif
+ 
+/// \brief Access a Memory Pool definition.
+/// \param         name          name of the memory pool
+/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osPool(name) \
+&os_pool_def_##name
+ 
+/// Create and Initialize a Memory Pool object.
+/// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osPoolId osPoolCreate (const osPoolDef_t *pool_def);
+ 
+/// Allocate a memory block from a Memory Pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+void *osPoolAlloc (osPoolId pool_id);
+ 
+/// Allocate a memory block from a Memory Pool and set memory block to zero.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+void *osPoolCAlloc (osPoolId pool_id);
+ 
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in]     block         address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+ 
+#endif  // Memory Pool available
+ 
+ 
+//  ==== Message Queue Management Functions ====
+ 
+#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0))  // Message Queue available
+  
+/// \brief Create a Message Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of messages in the queue.
+/// \param         type          data type of a single message element (for debugger).
+/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMessageQDef(name, queue_sz, type) \
+extern const osMessageQDef_t os_messageQ_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osMessageQDef(name, queue_sz, type) \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), NULL }
+#else
+#define osMessageQDef(name, queue_sz, type) \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), { NULL, 0U, NULL, 0U, NULL, 0U } }
+#endif
+#endif
+ 
+/// \brief Access a Message Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+ 
+/// Create and Initialize a Message Queue object.
+/// \param[in]     queue_def     message queue definition referenced with \ref osMessageQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+ 
+/// Put a Message to a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     info          message information.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+ 
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event information that includes status code.
+osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+ 
+#endif  // Message Queue available
+ 
+ 
+//  ==== Mail Queue Management Functions ====
+ 
+#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0))  // Mail Queue available
+ 
+/// \brief Create a Mail Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of mails in the queue.
+/// \param         type          data type of a single mail element.
+/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern const osMailQDef_t os_mailQ_def_##name
+#else                            // define the object
+#if (osCMSIS < 0x20000U)
+#define osMailQDef(name, queue_sz, type) \
+const osMailQDef_t os_mailQ_def_##name = \
+{ (queue_sz), sizeof(type), NULL }
+#else
+#define osMailQDef(name, queue_sz, type) \
+static void *os_mail_p_##name[2]; \
+const osMailQDef_t os_mailQ_def_##name = \
+{ (queue_sz), sizeof(type), (&os_mail_p_##name), \
+  { NULL, 0U, NULL, 0U, NULL, 0U }, \
+  { NULL, 0U, NULL, 0U, NULL, 0U } }
+#endif
+#endif
+ 
+/// \brief Access a Mail Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMailQ(name) \
+&os_mailQ_def_##name
+ 
+/// Create and Initialize a Mail Queue object.
+/// \param[in]     queue_def     mail queue definition referenced with \ref osMailQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
+ 
+/// Allocate a memory block for mail from a mail memory pool.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+ 
+/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+ 
+/// Put a Mail into a Queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to memory with mail to put into a queue.
+/// \return status code that indicates the execution status of the function.
+osStatus osMailPut (osMailQId queue_id, const void *mail);
+ 
+/// Get a Mail from a Queue or timeout if Queue is empty.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event information that includes status code.
+osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+ 
+/// Free a memory block by returning it to a mail memory pool.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+ 
+#endif  // Mail Queue available
+ 
+ 
+#ifdef  __cplusplus
+}
+#endif
+ 
+#endif  // CMSIS_OS_H_
diff --git a/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c b/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c
new file mode 100644
index 0000000..effe4a1
--- /dev/null
+++ b/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        10. January 2017
+ * $Revision:    V1.2
+ *
+ * Project:      CMSIS-RTOS API V1
+ * Title:        cmsis_os_v1.c V1 module file
+ *---------------------------------------------------------------------------*/
+
+#include 
+#include "cmsis_os.h"
+
+#if (osCMSIS >= 0x20000U)
+
+
+// Thread
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) {
+
+  if (thread_def == NULL) {
+    return (osThreadId)NULL;
+  }
+  return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr);
+}
+
+
+// Signals
+
+#define SignalMask ((1U< 0U) && (flags < 0x80000000U)) {
+    event.status = osEventSignal;
+    event.value.signals = (int32_t)flags;
+  } else {
+    switch ((int32_t)flags) {
+      case osErrorResource:
+        event.status = osOK;
+        break;
+      case osErrorTimeout:
+        event.status = osEventTimeout;
+        break;
+      case osErrorParameter:
+        event.status = osErrorValue;
+        break;
+      default:
+        event.status = (osStatus)flags;
+        break;
+    }
+  }
+  return event;
+}
+
+
+// Timer
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
+
+  if (timer_def == NULL) {
+    return (osTimerId)NULL;
+  }
+  return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr);
+}
+
+
+// Mutex
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def) {
+
+  if (mutex_def == NULL) {
+    return (osMutexId)NULL;
+  }
+  return osMutexNew(mutex_def);
+}
+
+
+// Semaphore
+
+#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U))
+
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
+
+  if (semaphore_def == NULL) {
+    return (osSemaphoreId)NULL;
+  }
+  return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def);
+}
+
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
+  osStatus_t status;
+  uint32_t   count;
+
+  status = osSemaphoreAcquire(semaphore_id, millisec);
+  switch (status) {
+    case osOK:
+      count = osSemaphoreGetCount(semaphore_id);
+      return ((int32_t)count + 1);
+    case osErrorResource:
+    case osErrorTimeout:
+      return 0;
+    default:
+      break;
+  }
+  return -1;
+}
+
+#endif  // Semaphore
+
+
+// Memory Pool
+
+#if (defined(osFeature_Pool) && (osFeature_Pool != 0))
+
+osPoolId osPoolCreate (const osPoolDef_t *pool_def) {
+
+  if (pool_def == NULL) {
+    return (osPoolId)NULL;
+  }
+  return ((osPoolId)(osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr)));
+}
+
+void *osPoolAlloc (osPoolId pool_id) {
+  return osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U);
+}
+
+void *osPoolCAlloc (osPoolId pool_id) {
+  void    *block;
+  uint32_t block_size;
+
+  block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id);
+  if (block_size == 0U) {
+    return NULL;
+  }
+  block = osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U);
+  if (block != NULL) {
+    memset(block, 0, block_size);
+  }
+  return block;
+}
+
+osStatus osPoolFree (osPoolId pool_id, void *block) {
+  return osMemoryPoolFree((osMemoryPoolId_t)pool_id, block);
+}
+
+#endif  // Memory Pool
+
+
+// Message Queue
+
+#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0))
+
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
+  (void)thread_id;
+
+  if (queue_def == NULL) {
+    return (osMessageQId)NULL;
+  }
+  return ((osMessageQId)(osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr)));
+}
+
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
+  return osMessageQueuePut((osMessageQueueId_t)queue_id, &info, 0U, millisec);
+}
+
+osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {
+  osStatus_t status;
+  osEvent    event;
+  uint32_t   message;
+
+  status = osMessageQueueGet((osMessageQueueId_t)queue_id, &message, NULL, millisec);
+  switch (status) {
+    case osOK:
+      event.status = osEventMessage;
+      event.value.v = message;
+      break;
+    case osErrorResource:
+      event.status = osOK;
+      break;
+    case osErrorTimeout:
+      event.status = osEventTimeout;
+      break;
+    default:
+      event.status = status;
+      break;
+  }
+  return event;
+}
+
+#endif  // Message Queue
+
+
+// Mail Queue
+
+#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0))
+
+typedef struct os_mail_queue_s {
+  osMemoryPoolId_t   mp_id;
+  osMessageQueueId_t mq_id;
+} os_mail_queue_t;
+
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
+  os_mail_queue_t *ptr;
+  (void)thread_id;
+
+  if (queue_def == NULL) {
+    return (osMailQId)NULL;
+  }
+
+  ptr = queue_def->mail;
+  if (ptr == NULL) {
+    return (osMailQId)NULL;
+  }
+
+  ptr->mp_id = osMemoryPoolNew  (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr);
+  ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr);
+  if ((ptr->mp_id == (osMemoryPoolId_t)NULL) || (ptr->mq_id == (osMessageQueueId_t)NULL)) {
+    if (ptr->mp_id != (osMemoryPoolId_t)NULL) {
+      osMemoryPoolDelete(ptr->mp_id);
+    }
+    if (ptr->mq_id != (osMessageQueueId_t)NULL) {
+      osMessageQueueDelete(ptr->mq_id);
+    }
+    return (osMailQId)NULL;
+  }
+
+  return (osMailQId)ptr;
+}
+
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec) {
+  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
+
+  if (ptr == NULL) {
+    return NULL;
+  }
+  return osMemoryPoolAlloc(ptr->mp_id, millisec);
+}
+
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {
+  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
+  void            *block;
+  uint32_t         block_size;
+
+  if (ptr == NULL) {
+    return NULL;
+  }
+  block_size = osMemoryPoolGetBlockSize(ptr->mp_id);
+  if (block_size == 0U) {
+    return NULL;
+  }
+  block = osMemoryPoolAlloc(ptr->mp_id, millisec);
+  if (block != NULL) {
+    memset(block, 0, block_size);
+  }
+
+  return block;
+
+}
+
+osStatus osMailPut (osMailQId queue_id, const void *mail) {
+  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
+
+  if (ptr == NULL) {
+    return osErrorParameter;
+  }
+  if (mail == NULL) {
+    return osErrorValue;
+  }
+  return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U);
+}
+
+osEvent osMailGet (osMailQId queue_id, uint32_t millisec) {
+  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
+  osStatus_t       status;
+  osEvent          event;
+  void            *mail;
+
+  if (ptr == NULL) {
+    event.status = osErrorParameter;
+    return event;
+  }
+
+  status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec);
+  switch (status) {
+    case osOK:
+      event.status = osEventMail;
+      event.value.p = mail;
+      break;
+    case osErrorResource:
+      event.status = osOK;
+      break;
+    case osErrorTimeout:
+      event.status = osEventTimeout;
+      break;
+    default:
+      event.status = status;
+      break;
+  }
+  return event;
+}
+
+osStatus osMailFree (osMailQId queue_id, void *mail) {
+  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
+
+  if (ptr == NULL) {
+    return osErrorParameter;
+  }
+  if (mail == NULL) {
+    return osErrorValue;
+  }
+  return osMemoryPoolFree(ptr->mp_id, mail);
+}
+
+#endif  // Mail Queue
+
+
+#endif  // osCMSIS
diff --git a/Drivers/CMSIS/docs/General/html/LICENSE.txt b/Drivers/CMSIS/docs/General/html/LICENSE.txt
new file mode 100644
index 0000000..c0ee812
--- /dev/null
+++ b/Drivers/CMSIS/docs/General/html/LICENSE.txt
@@ -0,0 +1,201 @@
+                                 Apache License
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+                        http://www.apache.org/licenses/
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+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
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+      the terms of any separate license agreement you may have executed
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+   6. Trademarks. This License does not grant permission to use the trade
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+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 0000000..ea1539b
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,4353 @@
+/**
+  ******************************************************************************
+  * @file    stm32_hal_legacy.h
+  * @author  MCD Application Team
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants
+  *          macros and functions maintained for legacy purpose.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
+#if defined(STM32H7) || defined(STM32MP1)
+#define CRYP_DATATYPE_32B               CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP
+#endif /* STM32H7 || STM32MP1 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP                   ADC_REGULAR_GROUP
+#define INJECTED_GROUP                  ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT                       ADC_AWD_EVENT
+#define AWD1_EVENT                      ADC_AWD1_EVENT
+#define AWD2_EVENT                      ADC_AWD2_EVENT
+#define AWD3_EVENT                      ADC_AWD3_EVENT
+#define OVR_EVENT                       ADC_OVR_EVENT
+#define JQOVF_EVENT                     ADC_JQOVF_EVENT
+#define ALL_CHANNELS                    ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE           ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5      ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5     ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define ADC_CHANNEL_VCORE               ADC_CHANNEL_VDDCORE
+#endif /* STM32H5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM 
+                                                                       input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
+/* to the second dedicated IO (only for COMP2).                               */
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+
+#if defined(STM32U5)
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define  MPU_DEVICE_nGnRnE          MPU_DEVICE_NGNRNE
+#define  MPU_DEVICE_nGnRE           MPU_DEVICE_NGNRE
+#define  MPU_DEVICE_nGRE            MPU_DEVICE_NGRE
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Aliases CRC API aliases
+  * @{
+  */
+#if defined(STM32H5) || defined(STM32C0)
+#else
+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for 
+                                                                          inter STM32 series compatibility  */
+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for 
+                                                                          inter STM32 series compatibility */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT  DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT  DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT       DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT       DAC_TRIGGER_LPTIM2_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
+    defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
+    defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI                        GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP                    OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE                      FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW                     OB_IWDG_SW
+#define OB_WDG_HW                     OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+#if defined(STM32G0) || defined(STM32C0)
+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0              OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0                OB_USER_NBOOT0
+#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
+#define OB_nBOOT0_SET                 OB_NBOOT0_SET
+#define OB_USER_SRAM134_RST           OB_USER_SRAM_RST
+#define OB_SRAM134_RST_ERASE          OB_SRAM_RST_ERASE
+#define OB_SRAM134_RST_NOT_ERASE      OB_SRAM_RST_NOT_ERASE
+#endif /* STM32U5 */
+#if defined(STM32U0)
+#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
+#define OB_USER_nBOOT_SEL             OB_USER_NBOOT_SEL
+#define OB_USER_nBOOT0                OB_USER_NBOOT0
+#define OB_USER_nBOOT1                OB_USER_NBOOT1
+#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
+#define OB_nBOOT0_SET                 OB_NBOOT0_SET
+#endif /* STM32U0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC         SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC         SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC         SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC         SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC         SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC         SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC    SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD          SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC     SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP       SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE   VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE    VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6   SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7   SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8   SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9   SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII   SBS_ETH_MII
+#define SYSCFG_ETH_RMII  SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG  IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE   SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR    SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG      IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC   SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC  SBS_VTOR_NSEC
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU              SBS_SAU
+#define SYSCFG_MPU_SEC          SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC   SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL         SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL         SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK      SBS_CLK
+#define SYSCFG_CLASSB   SBS_CLASSB
+#define SYSCFG_FPU      SBS_FPU
+#define SYSCFG_ALL      SBS_ALL
+
+#define SYSCFG_SEC      SBS_SEC
+#define SYSCFG_NSEC     SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE   __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE  __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK        __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK     __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK        __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK   __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE   __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE  __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS    __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS  __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT    IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG     IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE     IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE    IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING  IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS      IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES  IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES        IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS        IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig   HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig    HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig         HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF                  HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF                 HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect             HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock     HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock  HAL_SBS_GetLock
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes     HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes  HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+  * @{
+  */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
+#define GET_GPIO_INDEX                            GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
+         STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
+    defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
+
+#if defined(STM32L1)
+#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
+
+#if defined(STM32U5) || defined(STM32H5)
+#define GPIO_AF0_RTC_50Hz                         GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 || STM32H5 */
+#if defined(STM32U5)
+#define GPIO_AF0_S2DSTOP                          GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO                          GPIO_AF11_LPGPIO1
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI                      GTZC_PERIPH_DCMI_PSSI
+#define GTZC_PERIPH_LTDC                      GTZC_PERIPH_LTDCUSB
+#endif /* STM32U5 */
+#if defined(STM32H5)
+#define GTZC_PERIPH_DAC12                     GTZC_PERIPH_DAC1
+#define GTZC_PERIPH_ADC12                     GTZC_PERIPH_ADC
+#define GTZC_PERIPH_USBFS                     GTZC_PERIPH_USB
+#endif /* STM32H5 */
+#if defined(STM32H5) || defined(STM32U5)
+#define GTZC_MCPBB_NB_VCTR_REG_MAX            GTZC_MPCBB_NB_VCTR_REG_MAX
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX        GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED        GTZC_MPCBB_SUPERBLOCK_UNLOCKED
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED          GTZC_MPCBB_SUPERBLOCK_LOCKED
+#define GTZC_MCPBB_BLOCK_NSEC                 GTZC_MPCBB_BLOCK_NSEC
+#define GTZC_MCPBB_BLOCK_SEC                  GTZC_MPCBB_BLOCK_SEC
+#define GTZC_MCPBB_BLOCK_NPRIV                GTZC_MPCBB_BLOCK_NPRIV
+#define GTZC_MCPBB_BLOCK_PRIV                 GTZC_MPCBB_BLOCK_PRIV
+#define GTZC_MCPBB_LOCK_OFF                   GTZC_MPCBB_LOCK_OFF
+#define GTZC_MCPBB_LOCK_ON                    GTZC_MPCBB_LOCK_ON
+#endif /* STM32H5 || STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+  */
+#define HRTIM_EVENTSRC_1              (0x00000000U)
+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+  */
+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
+    defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_LPTIM_ReadCompare      HAL_LPTIM_ReadCapturedValue
+/**
+  * @}
+  */
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1        LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2        LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL    0x00000000U
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef             NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE                    NOR_WRITE
+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+#define I2S_IT_TXE               I2S_IT_TXP
+#define I2S_IT_RXNE              I2S_IT_RXP
+
+#define I2S_FLAG_TXE             I2S_FLAG_TXP
+#define I2S_FLAG_RXNE            I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+#define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA                       ATA_DATA
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD                  ATA_CARD_HEAD
+#define CF_STATUS_CMD                 ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FORMAT_BIN                  RTC_FORMAT_BIN
+#define FORMAT_BCD                  RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0   RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8   RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
+
+#if defined(STM32H5) || defined(STM32H7RS)
+#define TAMP_SECRETDEVICE_ERASE_NONE        TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM    TAMP_DEVICESECRETS_ERASE_BKPSRAM
+#endif /* STM32H5 || STM32H7RS */
+
+#if defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_NONE            TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_SRAM2           TAMP_DEVICESECRETS_ERASE_SRAM2
+#define TAMP_SECRETDEVICE_ERASE_RHUK            TAMP_DEVICESECRETS_ERASE_RHUK
+#define TAMP_SECRETDEVICE_ERASE_ICACHE          TAMP_DEVICESECRETS_ERASE_ICACHE
+#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH   TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
+#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM        TAMP_DEVICESECRETS_ERASE_PKA_SRAM
+#define TAMP_SECRETDEVICE_ERASE_ALL             TAMP_DEVICESECRETS_ERASE_ALL
+#endif /* STM32WBA */
+
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#define TAMP_SECRETDEVICE_ERASE_DISABLE     TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_ENABLE      TAMP_SECRETDEVICE_ERASE_ALL
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
+
+#if defined(STM32F7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 */
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
+
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 || STM32L0 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+#define SPI_FLAG_TXE                    SPI_FLAG_TXP
+#define SPI_FLAG_RXNE                   SPI_FLAG_RXP
+
+#define SPI_IT_TXE                      SPI_IT_TXP
+#define SPI_IT_RXNE                     SPI_IT_RXP
+
+#define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
+#define TIM_DMABase_SR                   TIM_DMABASE_SR
+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
+#define TIM_DMABase_OR                   TIM_DMABASE_OR
+
+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+#if defined(STM32U5)
+#define OCREF_CLEAR_SELECT_Pos       OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk       OCREF_CLEAR_SELECT_MSK
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
+
+#define __DIV_LPUART                    UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED               USART_NACK_ENABLE
+#define USARTNACK_DISABLED              USART_NACK_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CFR_BASE                    WWDG_CFR_BASE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0                CAN_IT_TME
+#define CAN_IT_RQCP1                CAN_IT_TME
+#define CAN_IT_RQCP2                CAN_IT_TME
+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define VLAN_TAG                ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL                           0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                       0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                   0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                           0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                           0x00100000U  /* Tx FIFO read status: Read (transferring data to 
+                                                                      the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                        0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from 
+                                                                      MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                        0x00300000U  /* Tx FIFO read status: Writing the received TxStatus
+                                                                      or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                    0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE          0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING       0x00020000U  /* MAC transmit frame controller: Waiting for Status 
+                                                                   of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U  /* MAC transmit frame controller: Generating and 
+                                                             transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING  0x00060000U  /* MAC transmit frame controller: Transferring input 
+                                                                      frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control 
+                                                              de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control 
+                                                              activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status 
+                                                             (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and 
+                                                              status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
+
+#define ETH_TxPacketConfig        ETH_TxPacketConfigTypeDef   /* Transmit Packet Configuration structure definition */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
+
+/**
+  * @}
+  */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888
+#define CM_RGB565               DMA2D_INPUT_RGB565
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8
+#define CM_AL44                 DMA2D_INPUT_AL44
+#define CM_AL88                 DMA2D_INPUT_AL88
+#define CM_L4                   DMA2D_INPUT_L4
+#define CM_A8                   DMA2D_INPUT_A8
+#define CM_A4                   DMA2D_INPUT_A4
+/**
+  * @}
+  */
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7) || defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+  * @{
+  */
+#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+                                                                        for compatibility with legacy code */
+/**
+  * @}
+  */
+
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 || STM32U5 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr     HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT  HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+  * @}
+  */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+  * @{
+  */
+#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< Redirection for compatibility with legacy code */
+/**
+  *
+  * @}
+  */
+#endif /* STM32F2 */
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
+                                             HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : \
+                                             HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
+    defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
+
+/**
+  * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
+                                                                HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
+                                                                HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
+    defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
+    defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
+          STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
+    defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+/**
+  * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
+#define CR_PMODE_BB                                   CR_VOS_BB
+
+#define DBP_BitNumber                                 DBP_BIT_NUMBER
+#define PVDE_BitNumber                                PVDE_BIT_NUMBER
+#define PMODE_BitNumber                               PMODE_BIT_NUMBER
+#define EWUP_BitNumber                                EWUP_BIT_NUMBER
+#define FPDS_BitNumber                                FPDS_BIT_NUMBER
+#define ODEN_BitNumber                                ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
+#define BRE_BitNumber                                 BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
+
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION                PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION                PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION                PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION                PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION                PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION                PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION                PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION                PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION                PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION               PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION               PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION               PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION                 PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION                PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION                PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION                 PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION                PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION                PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION                PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION                PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION                PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION                PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION                PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION                PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION                PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION               PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION               PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION               PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION               PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION                 PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION                 PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION                PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION                PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION                PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION                PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION                PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION                PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION                PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION                PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION                PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION               PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION               PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION               PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION               PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION                 PWR_SRAM5_FULL_STOP
+
+#define PWR_SRAM6_PAGE1_STOP_RETENTION                PWR_SRAM6_PAGE1_STOP
+#define PWR_SRAM6_PAGE2_STOP_RETENTION                PWR_SRAM6_PAGE2_STOP
+#define PWR_SRAM6_PAGE3_STOP_RETENTION                PWR_SRAM6_PAGE3_STOP
+#define PWR_SRAM6_PAGE4_STOP_RETENTION                PWR_SRAM6_PAGE4_STOP
+#define PWR_SRAM6_PAGE5_STOP_RETENTION                PWR_SRAM6_PAGE5_STOP
+#define PWR_SRAM6_PAGE6_STOP_RETENTION                PWR_SRAM6_PAGE6_STOP
+#define PWR_SRAM6_PAGE7_STOP_RETENTION                PWR_SRAM6_PAGE7_STOP
+#define PWR_SRAM6_PAGE8_STOP_RETENTION                PWR_SRAM6_PAGE8_STOP
+#define PWR_SRAM6_FULL_STOP_RETENTION                 PWR_SRAM6_FULL_STOP
+
+
+#define PWR_ICACHE_FULL_STOP_RETENTION                PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION               PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION               PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION              PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION             PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION              PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION           PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION                PWR_DSIRAM_FULL_STOP
+#define PWR_JPEGRAM_FULL_STOP_RETENTION               PWR_JPEGRAM_FULL_STOP
+
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION             PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION             PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION              PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION                  PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION                  PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION                  PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION                  PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION                  PWR_SRAM5_FULL_RUN
+#define PWR_SRAM6_FULL_RUN_RETENTION                  PWR_SRAM6_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK                PWR_ALL_RAM_RUN_MASK
+#endif
+
+/**
+  * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#define HAL_RTCEx_SetBoothardwareKey            HAL_RTCEx_LockBootHardwareKey
+#define HAL_RTCEx_BKUPBlock_Enable              HAL_RTCEx_BKUPBlock
+#define HAL_RTCEx_BKUPBlock_Disable             HAL_RTCEx_BKUPUnblock
+#define HAL_RTCEx_Erase_SecretDev_Conf          HAL_RTCEx_ConfigEraseDeviceSecrets
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError                                TIM_DMAError
+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
+    defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define AES_IT_CC                      CRYP_IT_CC
+#define AES_IT_ERR                     CRYP_IT_ERR
+#define AES_FLAG_CCF                   CRYP_FLAG_CCF
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1                                   ADC_SQR1
+#define __HAL_ADC_SMPR1                                  ADC_SMPR1
+#define __HAL_ADC_SMPR2                                  ADC_SMPR2
+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR                                   ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32F3)
+#define COMP_START                                       __HAL_COMP_ENABLE
+#define COMP_STOP                                        __HAL_COMP_DISABLE
+#define COMP_LOCK                                        __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
+    defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+  * @}
+  */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is 
+                                                  done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is 
+                                                  done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+                           ((WAVE) == DAC_WAVE_NOISE)|| \
+                           ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_WRPAREA          IS_OB_WRPAREA
+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE        IS_FLASH_TYPEERASE
+#define IS_NBSECTORS        IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
+#define __HAL_I2C_SPEED                 I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+#define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+                                                                      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+                                                                    } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
+                                                                      HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
+                                                                    } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
+                                                                      HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
+                                                                    } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+  * @{
+  */
+
+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
+                                        HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#define  RCC_SPI4CLKSOURCE_D2PCLK1       RCC_SPI4CLKSOURCE_D2PCLK2
+#define  RCC_SPI5CLKSOURCE_D2PCLK1       RCC_SPI5CLKSOURCE_D2PCLK2
+#define  RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_D2PCLK2
+#define  RCC_SPI45CLKSOURCE_CDPCLK1      RCC_SPI45CLKSOURCE_CDPCLK2
+#define  RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_PCLK2
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection               SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection                 Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV               RCC_MCODIV_1
+#define RCC_MCO_DIV1                RCC_MCODIV_1
+#define RCC_MCO_DIV2                RCC_MCODIV_2
+#define RCC_MCO_DIV4                RCC_MCODIV_4
+#define RCC_MCO_DIV8                RCC_MCODIV_8
+#define RCC_MCO_DIV16               RCC_MCODIV_16
+#define RCC_MCO_DIV32               RCC_MCODIV_32
+#define RCC_MCO_DIV64               RCC_MCODIV_64
+#define RCC_MCO_DIV128              RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32U0)
+#define RCC_SYSCLKSOURCE_STATUS_PLLR   RCC_SYSCLKSOURCE_STATUS_PLLCLK
+#endif
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
+    defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB            RCC_CR_HSION_BB
+#define CR_CSSON_BB            RCC_CR_CSSON_BB
+#define CR_PLLON_BB            RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB            RCC_CR_MSION_BB
+#define CSR_LSION_BB           RCC_CSR_LSION_BB
+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB            RCC_CR_HSEON_BB
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#if !defined(STM32U0)
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+#endif
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL                        RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL                        RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE           __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE           __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear      __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear     __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear     __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear      __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear      __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear      __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear      __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection            IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48                   RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48              RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2               RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1               RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK               RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE             __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE            __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED         __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED        __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET            __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET          __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE       __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE      __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE            __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE             __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE            __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG             __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE                 IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define __HAL_RCC_PLLFRACN_ENABLE       __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE      __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG       __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE           IS_RCC_PLL_FRACN_VALUE
+
+#define RCC_PLLSOURCE_NONE              RCC_PLL1_SOURCE_NONE
+#define RCC_PLLSOURCE_HSI               RCC_PLL1_SOURCE_HSI
+#define RCC_PLLSOURCE_CSI               RCC_PLL1_SOURCE_CSI
+#define RCC_PLLSOURCE_HSE               RCC_PLL1_SOURCE_HSE
+#define RCC_PLLVCIRANGE_0               RCC_PLL1_VCIRANGE_0
+#define RCC_PLLVCIRANGE_1               RCC_PLL1_VCIRANGE_1
+#define RCC_PLLVCIRANGE_2               RCC_PLL1_VCIRANGE_2
+#define RCC_PLLVCIRANGE_3               RCC_PLL1_VCIRANGE_3
+#define RCC_PLL1VCOWIDE                 RCC_PLL1_VCORANGE_WIDE
+#define RCC_PLL1VCOMEDIUM               RCC_PLL1_VCORANGE_MEDIUM
+
+#define IS_RCC_PLLSOURCE                IS_RCC_PLL1_SOURCE
+#define IS_RCC_PLLRGE_VALUE             IS_RCC_PLL1_VCIRGE_VALUE
+#define IS_RCC_PLLVCORGE_VALUE          IS_RCC_PLL1_VCORGE_VALUE
+#define IS_RCC_PLLCLOCKOUT_VALUE        IS_RCC_PLL1_CLOCKOUT_VALUE
+#define IS_RCC_PLL_FRACN_VALUE          IS_RCC_PLL1_FRACN_VALUE
+#define IS_RCC_PLLM_VALUE               IS_RCC_PLL1_DIVM_VALUE
+#define IS_RCC_PLLN_VALUE               IS_RCC_PLL1_MULN_VALUE
+#define IS_RCC_PLLP_VALUE               IS_RCC_PLL1_DIVP_VALUE
+#define IS_RCC_PLLQ_VALUE               IS_RCC_PLL1_DIVQ_VALUE
+#define IS_RCC_PLLR_VALUE               IS_RCC_PLL1_DIVR_VALUE
+
+#define __HAL_RCC_PLL_ENABLE            __HAL_RCC_PLL1_ENABLE
+#define __HAL_RCC_PLL_DISABLE           __HAL_RCC_PLL1_DISABLE
+#define __HAL_RCC_PLL_FRACN_ENABLE      __HAL_RCC_PLL1_FRACN_ENABLE
+#define __HAL_RCC_PLL_FRACN_DISABLE     __HAL_RCC_PLL1_FRACN_DISABLE
+#define __HAL_RCC_PLL_CONFIG            __HAL_RCC_PLL1_CONFIG
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG  __HAL_RCC_PLL1_PLLSOURCE_CONFIG
+#define __HAL_RCC_PLL_DIVM_CONFIG       __HAL_RCC_PLL1_DIVM_CONFIG
+#define __HAL_RCC_PLL_FRACN_CONFIG      __HAL_RCC_PLL1_FRACN_CONFIG
+#define __HAL_RCC_PLL_VCIRANGE          __HAL_RCC_PLL1_VCIRANGE
+#define __HAL_RCC_PLL_VCORANGE          __HAL_RCC_PLL1_VCORANGE
+#define __HAL_RCC_GET_PLL_OSCSOURCE     __HAL_RCC_GET_PLL1_OSCSOURCE
+#define __HAL_RCC_PLLCLKOUT_ENABLE      __HAL_RCC_PLL1_CLKOUT_ENABLE
+#define __HAL_RCC_PLLCLKOUT_DISABLE     __HAL_RCC_PLL1_CLKOUT_DISABLE
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG  __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL2FRACN_ENABLE      __HAL_RCC_PLL2_FRACN_ENABLE
+#define __HAL_RCC_PLL2FRACN_DISABLE     __HAL_RCC_PLL2_FRACN_DISABLE
+#define __HAL_RCC_PLL2CLKOUT_ENABLE     __HAL_RCC_PLL2_CLKOUT_ENABLE
+#define __HAL_RCC_PLL2CLKOUT_DISABLE    __HAL_RCC_PLL2_CLKOUT_DISABLE
+#define __HAL_RCC_PLL2FRACN_CONFIG      __HAL_RCC_PLL2_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL3FRACN_ENABLE      __HAL_RCC_PLL3_FRACN_ENABLE
+#define __HAL_RCC_PLL3FRACN_DISABLE     __HAL_RCC_PLL3_FRACN_DISABLE
+#define __HAL_RCC_PLL3CLKOUT_ENABLE     __HAL_RCC_PLL3_CLKOUT_ENABLE
+#define __HAL_RCC_PLL3CLKOUT_DISABLE    __HAL_RCC_PLL3_CLKOUT_DISABLE
+#define __HAL_RCC_PLL3FRACN_CONFIG      __HAL_RCC_PLL3_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
+
+#define RCC_PLL2VCIRANGE_0              RCC_PLL2_VCIRANGE_0
+#define RCC_PLL2VCIRANGE_1              RCC_PLL2_VCIRANGE_1
+#define RCC_PLL2VCIRANGE_2              RCC_PLL2_VCIRANGE_2
+#define RCC_PLL2VCIRANGE_3              RCC_PLL2_VCIRANGE_3
+
+#define RCC_PLL2VCOWIDE                 RCC_PLL2_VCORANGE_WIDE
+#define RCC_PLL2VCOMEDIUM               RCC_PLL2_VCORANGE_MEDIUM
+
+#define RCC_PLL2SOURCE_NONE             RCC_PLL2_SOURCE_NONE
+#define RCC_PLL2SOURCE_HSI              RCC_PLL2_SOURCE_HSI
+#define RCC_PLL2SOURCE_CSI              RCC_PLL2_SOURCE_CSI
+#define RCC_PLL2SOURCE_HSE              RCC_PLL2_SOURCE_HSE
+
+#define RCC_PLL3VCIRANGE_0              RCC_PLL3_VCIRANGE_0
+#define RCC_PLL3VCIRANGE_1              RCC_PLL3_VCIRANGE_1
+#define RCC_PLL3VCIRANGE_2              RCC_PLL3_VCIRANGE_2
+#define RCC_PLL3VCIRANGE_3              RCC_PLL3_VCIRANGE_3
+
+#define RCC_PLL3VCOWIDE                 RCC_PLL3_VCORANGE_WIDE
+#define RCC_PLL3VCOMEDIUM               RCC_PLL3_VCORANGE_MEDIUM
+
+#define RCC_PLL3SOURCE_NONE             RCC_PLL3_SOURCE_NONE
+#define RCC_PLL3SOURCE_HSI              RCC_PLL3_SOURCE_HSI
+#define RCC_PLL3SOURCE_CSI              RCC_PLL3_SOURCE_CSI
+#define RCC_PLL3SOURCE_HSE              RCC_PLL3_SOURCE_HSE
+
+
+#endif /* STM32H5 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
+    defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+    defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) ||  defined (STM32U0)
+#else
+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
+                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif   /* STM32F1 */
+
+#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
+    defined (STM32H7) || \
+    defined (STM32L0) || defined (STM32L1) || \
+    defined (STM32WB)
+#define __HAL_RTC_TAMPER_GET_IT                   __HAL_RTC_TAMPER_GET_FLAG
+#endif
+
+#define IS_ALARM                                  IS_RTC_ALARM
+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
+#define IS_TAMPER                                 IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
+
+#if defined (STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE   __HAL_RCC_RTC_CLK_ENABLE
+#define __HAL_RCC_RTCAPB_CLK_DISABLE  __HAL_RCC_RTC_CLK_DISABLE
+#endif   /* STM32H5 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
+
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
+#define eMMC_HIGH_VOLTAGE_RANGE     EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE     EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE      EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV        SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV        SDMMC_HSPEED_CLK_DIV
+#endif
+
+#if defined(STM32F4) || defined(STM32F2)
+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define  SDMMC1_IRQn                SDIO_IRQn
+#define  SDMMC1_IRQHandler          SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
+#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
+#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
+#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define  SDIO_IRQn                  SDMMC1_IRQn
+#define  SDIO_IRQHandler            SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
+#define __USART_ENABLE                  __HAL_USART_ENABLE
+#define __USART_DISABLE                 __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16               0x00000000U
+#define USART_OVERSAMPLING_8                USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
+
+#define TIM_OCMODE_ASSYMETRIC_PWM1      TIM_OCMODE_ASYMMETRIC_PWM1
+#define TIM_OCMODE_ASSYMETRIC_PWM2      TIM_OCMODE_ASYMMETRIC_PWM2
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE                     SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32F7)
+#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
+#endif /* STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h
new file mode 100644
index 0000000..9beac83
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h
@@ -0,0 +1,275 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL 
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_H
+#define __STM32F7xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_conf.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_BootMode Boot Mode
+  * @{
+  */
+#define SYSCFG_MEM_BOOT_ADD0          ((uint32_t)0x00000000U)
+#define SYSCFG_MEM_BOOT_ADD1          SYSCFG_MEMRMP_MEM_BOOT
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+   
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+  * @{
+  */
+  
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode 
+  */
+#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
+#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+#define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+
+/** @brief  FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC()          (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))
+                                       
+
+/** @brief  FMC/SDRAM  mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\
+                                          SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\
+                                         }while(0);
+/**
+  * @brief  Return the memory boot mapping as configured by user.
+  * @retval The boot mode as configured by user. The returned value can be one
+  *         of the following values:
+  *           @arg @ref SYSCFG_MEM_BOOT_ADD0
+  *           @arg @ref SYSCFG_MEM_BOOT_ADD1
+  */
+#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+/** @brief  SYSCFG Break Cortex-M7 Lockup lock.
+  *         Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL)
+
+/** @brief  SYSCFG Break PVD lock.
+  *         Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL)
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Functions
+  * @{
+  */
+/** @addtogroup HAL_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and Configuration functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+/**
+  * @}
+  */
+ 
+ /* Exported variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+  * @}
+  */
+ 
+/** @addtogroup HAL_Exported_Functions_Group2
+  * @{
+  */ 
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+void HAL_EnableFMCMemorySwapping(void);
+void HAL_DisableFMCMemorySwapping(void);
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+void HAL_EnableMemorySwappingBank(void);
+void HAL_DisableMemorySwappingBank(void);
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Constants HAL Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_H */
+
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h
new file mode 100644
index 0000000..d227917
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h
@@ -0,0 +1,957 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_ADC_H
+#define STM32F7xx_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  Structure definition of ADC and regular group initialization 
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
+  *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
+  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled
+  *          - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
+  *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t ClockPrescaler;               /*!< Select ADC clock prescaler. The clock is common for 
+                                              all the ADCs.
+                                              This parameter can be a value of @ref ADC_ClockPrescaler */
+  uint32_t Resolution;                   /*!< Configures the ADC resolution.
+                                              This parameter can be a value of @ref ADC_Resolution */
+  uint32_t DataAlign;                    /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
+                                              or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
+                                              This parameter can be a value of @ref ADC_Data_Align */
+  uint32_t ScanConvMode;                 /*!< Configures the sequencer of regular and injected groups.
+                                              This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+                                              If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+                                                           Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+                                              If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+                                                           Scan direction is upward: from rank1 to rank 'n'.
+                                              This parameter can be a value of @ref ADC_Scan_mode.
+                                              This parameter can be set to ENABLE or DISABLE */
+  uint32_t EOCSelection;                 /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
+                                              This parameter can be a value of @ref ADC_EOCSelection.
+                                              Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
+                                                    Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
+                                                    or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
+                                              Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
+                                              If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
+  uint32_t ContinuousConvMode;           /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+                                              after the selected trigger occurred (software start or external trigger).
+                                              This parameter can be set to ENABLE or DISABLE. */
+  uint32_t NbrOfConversion;              /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+                                              To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+                                              This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+  FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+                                              Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                              Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+                                              This parameter can be set to ENABLE or DISABLE. */
+  uint32_t NbrOfDiscConversion;          /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+                                              If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+                                              This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+  uint32_t ExternalTrigConv;             /*!< Selects the external event used to trigger the conversion start of regular group.
+                                              If set to ADC_SOFTWARE_START, external triggers are disabled.
+                                              If set to external trigger source, triggering is on event rising edge by default.
+                                              This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
+  uint32_t ExternalTrigConvEdge;         /*!< Selects the external trigger edge of regular group.
+                                              If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+                                              This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
+  FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
+                                              or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
+                                              Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+                                              Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
+                                              This parameter can be set to ENABLE or DISABLE. */
+}ADC_InitTypeDef;
+
+
+
+/** 
+  * @brief  Structure definition of ADC channel for regular group   
+  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+  *         ADC can be either disabled or enabled without conversion on going on regular group.
+  */ 
+typedef struct 
+{
+  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
+                                        This parameter can be a value of @ref ADC_channels */
+  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
+                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16 
+                                        This parameter can be a value of @ref ADC_regular_rank */
+  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
+                                        Unit: ADC clock cycles
+                                        Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
+                                        This parameter can be a value of @ref ADC_sampling_times
+                                        Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+                                                 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
+  uint32_t Offset;                 /*!< Reserved for future use, can be set to 0 */
+}ADC_ChannelConfTypeDef;
+
+/** 
+  * @brief ADC Configuration multi-mode structure definition  
+  */ 
+typedef struct
+{
+  uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.
+                                   This parameter can be a value of @ref ADC_analog_watchdog_selection */
+  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
+                                   This parameter must be a 12-bit value. */     
+  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
+                                   This parameter must be a 12-bit value. */
+  uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog. 
+                                   This parameter has an effect only if watchdog mode is configured on single channel 
+                                   This parameter can be a value of @ref ADC_channels */      
+  FunctionalState ITMode;     /*!< Specifies whether the analog watchdog is configured
+                                   is interrupt mode or in polling mode.
+                                   This parameter can be set to ENABLE or DISABLE */
+  uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
+}ADC_AnalogWDGConfTypeDef;
+
+/** 
+  * @brief  HAL ADC state machine: ADC states definition (bitfields)
+  */ 
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000U)    /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001U)    /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002U)    /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004U)    /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010U)    /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020U)    /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040U)    /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100U)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200U)    /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400U)    /*!< Overrun occurrence */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000U)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000U)    /*!< Conversion data available on group injected */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000U)    /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000U)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000U)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000U)    /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */
+
+
+/** 
+  * @brief  ADC handle Structure definition
+  */ 
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
+typedef struct
+#endif
+{
+  ADC_TypeDef                   *Instance;                   /*!< Register base address */
+
+  ADC_InitTypeDef               Init;                        /*!< ADC required parameters */
+
+  __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */
+
+  DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */
+
+  HAL_LockTypeDef               Lock;                        /*!< ADC locking object */
+
+  __IO uint32_t                 State;                       /*!< ADC communication state */
+
+  __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
+  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
+  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
+  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
+  void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete callback */
+  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
+  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}ADC_HandleTypeDef;
+
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL ADC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
+  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
+  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
+  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
+  HAL_ADC_MSPINIT_CB_ID                 = 0x05U,  /*!< ADC Msp Init callback ID          */
+  HAL_ADC_MSPDEINIT_CB_ID               = 0x06U   /*!< ADC Msp DeInit callback ID        */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL ADC Callback pointer definition
+  */
+typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+  * @{
+  */
+#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00U)   /*!< No error                                              */
+#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01U)   /*!< ADC IP internal error: if problem of clocking, 
+                                                          enable/disable, erroneous state                       */
+#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02U)   /*!< Overrun error                                         */
+#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04U)   /*!< DMA transfer error                                    */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler
+  * @{
+  */ 
+#define ADC_CLOCK_SYNC_PCLK_DIV2    ((uint32_t)0x00000000U)
+#define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)
+#define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)
+#define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
+  * @{
+  */ 
+#define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000U)
+#define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)
+#define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)
+#define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)
+#define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)
+#define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
+#define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Resolution ADC Resolution
+  * @{
+  */ 
+#define ADC_RESOLUTION_12B  ((uint32_t)0x00000000U)
+#define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)
+#define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)
+#define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
+  * @{
+  */ 
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000U)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
+  * @{
+  */
+/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */
+/*       compatibility with other STM32 devices.                              */
+
+
+#define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000U)
+#define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
+#define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
+#define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T5_TRGO   ((uint32_t)ADC_CR2_EXTSEL_2)
+#define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T3_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T8_TRGO2  ((uint32_t)ADC_CR2_EXTSEL_3)
+#define ADC_EXTERNALTRIGCONV_T1_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2  ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T4_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
+#define ADC_EXTERNALTRIGCONV_T6_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+
+#define ADC_EXTERNALTRIGCONV_EXT_IT11  ((uint32_t)ADC_CR2_EXTSEL)
+#define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Data_Align ADC Data Align
+  * @{
+  */ 
+#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000U)
+#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+  * @{
+  */
+#define ADC_SCAN_DISABLE         ((uint32_t)0x00000000)        /*!< Scan mode disabled */
+#define ADC_SCAN_ENABLE          ((uint32_t)0x00000001)        /*!< Scan mode enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_rank ADC group regular sequencer rank
+  * @{
+  */
+#define ADC_REGULAR_RANK_1    ((uint32_t)0x00000001)       /*!< ADC regular conversion rank 1  */
+#define ADC_REGULAR_RANK_2    ((uint32_t)0x00000002)       /*!< ADC regular conversion rank 2  */
+#define ADC_REGULAR_RANK_3    ((uint32_t)0x00000003)       /*!< ADC regular conversion rank 3  */
+#define ADC_REGULAR_RANK_4    ((uint32_t)0x00000004)       /*!< ADC regular conversion rank 4  */
+#define ADC_REGULAR_RANK_5    ((uint32_t)0x00000005)       /*!< ADC regular conversion rank 5  */
+#define ADC_REGULAR_RANK_6    ((uint32_t)0x00000006)       /*!< ADC regular conversion rank 6  */
+#define ADC_REGULAR_RANK_7    ((uint32_t)0x00000007)       /*!< ADC regular conversion rank 7  */
+#define ADC_REGULAR_RANK_8    ((uint32_t)0x00000008)       /*!< ADC regular conversion rank 8  */
+#define ADC_REGULAR_RANK_9    ((uint32_t)0x00000009)       /*!< ADC regular conversion rank 9  */
+#define ADC_REGULAR_RANK_10   ((uint32_t)0x0000000A)       /*!< ADC regular conversion rank 10 */
+#define ADC_REGULAR_RANK_11   ((uint32_t)0x0000000B)       /*!< ADC regular conversion rank 11 */
+#define ADC_REGULAR_RANK_12   ((uint32_t)0x0000000C)       /*!< ADC regular conversion rank 12 */
+#define ADC_REGULAR_RANK_13   ((uint32_t)0x0000000D)       /*!< ADC regular conversion rank 13 */
+#define ADC_REGULAR_RANK_14   ((uint32_t)0x0000000E)       /*!< ADC regular conversion rank 14 */
+#define ADC_REGULAR_RANK_15   ((uint32_t)0x0000000F)       /*!< ADC regular conversion rank 15 */
+#define ADC_REGULAR_RANK_16   ((uint32_t)0x00000010)       /*!< ADC regular conversion rank 16 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels ADC Common Channels
+  * @{
+  */ 
+#define ADC_CHANNEL_0           ((uint32_t)0x00000000U)
+#define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)
+#define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)
+#define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)
+#define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
+#define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)
+#define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
+
+#define ADC_INTERNAL_NONE                  0x80000000U
+#define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)
+#define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)
+#define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)(ADC_CHANNEL_18 | 0x10000000U))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_sampling_times ADC Sampling Times
+  * @{
+  */ 
+#define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000U)
+#define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)
+#define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)
+#define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
+#define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)
+#define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
+#define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
+#define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)
+/**
+  * @}
+  */ 
+
+  /** @defgroup ADC_EOCSelection ADC EOC Selection
+  * @{
+  */ 
+#define ADC_EOC_SEQ_CONV              ((uint32_t)0x00000000U)
+#define ADC_EOC_SINGLE_CONV           ((uint32_t)0x00000001U)
+#define ADC_EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002U)  /*!< reserved for future use */
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Event_type ADC Event Type
+  * @{
+  */ 
+#define ADC_AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)
+#define ADC_OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
+  * @{
+  */ 
+#define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000U)
+/**
+  * @}
+  */ 
+    
+/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
+  * @{
+  */ 
+#define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)  
+#define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE) 
+#define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)
+#define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE) 
+/**
+  * @}
+  */ 
+    
+/** @defgroup ADC_flags_definition ADC Flags Definition
+  * @{
+  */ 
+#define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)
+#define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)
+#define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)
+#define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)
+#define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)
+#define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_channels_type ADC Channels Type
+  * @{
+  */ 
+#define ADC_ALL_CHANNELS      ((uint32_t)0x00000001U)
+#define ADC_REGULAR_CHANNELS  ((uint32_t)0x00000002U) /*!< reserved for future use */
+#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+  * @{
+  */
+
+/** @brief Reset ADC handle state
+  * @param  __HANDLE__ ADC handle
+  * @retval None
+  */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  do{                                                                          \
+     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                               \
+     (__HANDLE__)->MspInitCallback = NULL;                                     \
+     (__HANDLE__)->MspDeInitCallback = NULL;                                   \
+    } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif
+
+/**
+  * @brief  Enable the ADC peripheral.
+  * @param  __HANDLE__ ADC handle
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)
+
+/**
+  * @brief  Disable the ADC peripheral.
+  * @param  __HANDLE__ ADC handle
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)
+
+/**
+  * @brief  Enable the ADC end of conversion interrupt.
+  * @param  __HANDLE__ specifies the ADC Handle.
+  * @param  __INTERRUPT__ ADC Interrupt.
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the ADC end of conversion interrupt.
+  * @param  __HANDLE__ specifies the ADC Handle.
+  * @param  __INTERRUPT__ ADC interrupt.
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
+
+/** @brief  Check if the specified ADC interrupt source is enabled or disabled.
+  * @param  __HANDLE__ specifies the ADC Handle.
+  * @param  __INTERRUPT__ specifies the ADC interrupt source to check.
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Clear the ADC's pending flags.
+  * @param  __HANDLE__ specifies the ADC Handle.
+  * @param  __FLAG__ ADC flag.
+  * @retval None
+  */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
+
+/**
+  * @brief  Get the selected ADC's flag status.
+  * @param  __HANDLE__ specifies the ADC Handle.
+  * @param  __FLAG__ ADC flag.
+  * @retval None
+  */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Include ADC HAL Extension module */
+#include "stm32f7xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void       HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void       HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+  * @{
+  */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+void              HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+uint32_t          HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+void       HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void       HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void       HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void       HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral State functions ***************************************************/
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+/* Delay for ADC stabilization time.                                        */
+/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
+/* Unit: us                                                                 */
+#define ADC_STAB_DELAY_US               ((uint32_t) 3U)
+/* Delay for temperature sensor stabilization time.                         */
+/* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
+/* Unit: us                                                                 */
+#define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10U)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_Private_Macros ADC Private Macros
+  * @{
+  */
+/* Macro reserved for internal HAL driver usage, not intended to be used in
+   code of final user */
+
+/**
+  * @brief Verification of ADC state: enabled or disabled
+  * @param __HANDLE__ ADC handle
+  * @retval SET (ADC enabled) or RESET (ADC disabled)
+  */
+#define ADC_IS_ENABLE(__HANDLE__)                                              \
+  ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
+  ) ? SET : RESET)
+
+/**
+  * @brief Test if conversion trigger of regular group is software start
+  *        or external trigger.
+  * @param __HANDLE__ ADC handle
+  * @retval SET (software start) or RESET (external trigger)
+  */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
+  (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+
+/**
+  * @brief Test if conversion trigger of injected group is software start
+  *        or external trigger.
+  * @param __HANDLE__ ADC handle
+  * @retval SET (software start) or RESET (external trigger)
+  */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
+  (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
+
+/**
+  * @brief Simultaneously clears and sets specific bits of the handle State
+  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+  *        the first parameter is the ADC handle State, the second parameter is the
+  *        bit field to clear, the third and last parameter is the bit field to set.
+  * @retval None
+  */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+  * @brief Clear ADC error code (set it to error code: "no error")
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
+  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
+                                 ((CHANNEL) == ADC_INTERNAL_NONE))
+#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)     (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
+                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
+                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))
+#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B))			
+#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
+                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
+                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO)  || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO)  || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
+                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+																			((__REGTRIG__) == ADC_SOFTWARE_START))
+#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
+                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT))
+		
+                                      									
+#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_15CYCLES)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_28CYCLES)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_56CYCLES)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_84CYCLES)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \
+                                      ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \
+                                      ((__TIME__) == ADC_SAMPLETIME_480CYCLES))	
+#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV)   || \
+                                               ((__EOCSelection__) == ADC_EOC_SEQ_CONV)  || \
+                                               ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))	
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \
+                                      ((__EVENT__) == ADC_OVR_EVENT))		
+#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
+                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
+                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
+                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
+                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
+                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
+                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))
+#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
+                                            ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
+                                            ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
+
+#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_2 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_3 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_4 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_5 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_6 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_7 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_8 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_9 ) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_10) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_11) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_12) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_13) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_14) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_15) || \
+                                       ((__RANK__) == ADC_REGULAR_RANK_16))
+
+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
+                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE))
+
+#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
+#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)                                     \
+   ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
+    (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
+    (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
+    (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))
+
+/**
+  * @brief  Set ADC Regular channel sequence length.
+  * @param  _NbrOfConversion_ Regular channel sequence length. 
+  * @retval None
+  */
+#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
+
+/**
+  * @brief  Set the ADC's sample time for channel numbers between 10 and 18.
+  * @param  _SAMPLETIME_ Sample time parameter.
+  * @param  _CHANNELNB_ Channel number.  
+  * @retval None
+  */
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
+
+/**
+  * @brief  Set the ADC's sample time for channel numbers between 0 and 9.
+  * @param  _SAMPLETIME_ Sample time parameter.
+  * @param  _CHANNELNB_ Channel number.  
+  * @retval None
+  */
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
+
+/**
+  * @brief  Set the selected regular channel rank for rank between 1 and 6.
+  * @param  _CHANNELNB_ Channel number.
+  * @param  _RANKNB_ Rank number.    
+  * @retval None
+  */
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
+
+/**
+  * @brief  Set the selected regular channel rank for rank between 7 and 12.
+  * @param  _CHANNELNB_ Channel number.
+  * @param  _RANKNB_ Rank number.    
+  * @retval None
+  */
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
+
+/**
+  * @brief  Set the selected regular channel rank for rank between 13 and 16.
+  * @param  _CHANNELNB_ Channel number.
+  * @param  _RANKNB_ Rank number.    
+  * @retval None
+  */
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
+
+/**
+  * @brief  Enable ADC continuous conversion mode.
+  * @param  _CONTINUOUS_MODE_ Continuous mode.
+  * @retval None
+  */
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
+
+/**
+  * @brief  Configures the number of discontinuous conversions for the regular group channels.
+  * @param  _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.
+  * @retval None
+  */
+#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << ADC_CR1_DISCNUM_Pos)
+
+/**
+  * @brief  Enable ADC scan mode.
+  * @param  _SCANCONV_MODE_ Scan conversion mode.
+  * @retval None
+  */
+#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
+
+/**
+  * @brief  Enable the ADC end of conversion selection.
+  * @param  _EOCSelection_MODE_ End of conversion selection mode.
+  * @retval None
+  */
+#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
+
+/**
+  * @brief  Enable the ADC DMA continuous request.
+  * @param  _DMAContReq_MODE_ DMA continuous request mode.
+  * @retval None
+  */
+#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
+
+/**
+  * @brief Return resolution bits in CR1 register.
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
+																
+/**
+  * @}
+  */
+	
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+	
+/**
+  * @}
+  */
+	
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F7xx_ADC_H */
+
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h
new file mode 100644
index 0000000..6ac4023
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h
@@ -0,0 +1,354 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_ADC_EX_H
+#define STM32F7xx_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADCEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Exported Types
+  * @{
+  */
+   
+/** 
+  * @brief  ADC Configuration injected Channel structure definition
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
+  *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+  *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
+  * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled
+  *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
+  *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
+  */
+typedef struct 
+{
+  uint32_t InjectedChannel;                      /*!< Selection of ADC channel to configure
+                                                      This parameter can be a value of @ref ADC_channels
+                                                      Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+  uint32_t InjectedRank;                         /*!< Rank in the injected group sequencer
+                                                      This parameter must be a value of @ref ADCEx_injected_rank
+                                                      Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+  uint32_t InjectedSamplingTime;                 /*!< Sampling time value to be set for the selected channel.
+                                                      Unit: ADC clock cycles
+                                                      Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
+                                                      This parameter can be a value of @ref ADC_sampling_times
+                                                      Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+                                                               If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+                                                      Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+                                                            sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                                            Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
+  uint32_t InjectedOffset;                       /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
+                                                      Offset value must be a positive number.
+                                                      Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+                                                      this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+  uint32_t InjectedNbrOfConversion;              /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+                                                      To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+                                                      This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                               configure a channel on injected group can impact the configuration of other channels previously set. */
+  FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+                                                      Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                                      Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+                                                      This parameter can be set to ENABLE or DISABLE.
+                                                      Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                               configure a channel on injected group can impact the configuration of other channels previously set. */
+  FunctionalState AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+                                                      This parameter can be set to ENABLE or DISABLE.      
+                                                      Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+                                                      Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+                                                      Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+                                                            To maintain JAUTO always enabled, DMA must be configured in circular mode.
+                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                               configure a channel on injected group can impact the configuration of other channels previously set. */
+  uint32_t ExternalTrigInjecConv;                /*!< Selects the external event used to trigger the conversion start of injected group.
+                                                      If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+                                                      If set to external trigger source, triggering is on event rising edge.
+                                                      This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
+                                                      Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+                                                            If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
+                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                               configure a channel on injected group can impact the configuration of other channels previously set. */
+  uint32_t ExternalTrigInjecConvEdge;            /*!< Selects the external trigger edge of injected group.
+                                                      This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
+                                                      If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
+                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                               configure a channel on injected group can impact the configuration of other channels previously set. */
+}ADC_InjectionConfTypeDef; 
+
+/** 
+  * @brief ADC Configuration multi-mode structure definition  
+  */ 
+typedef struct
+{
+  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode. 
+                                   This parameter can be a value of @ref ADCEx_Common_mode */
+  uint32_t DMAAccessMode;     /*!< Configures the Direct memory access mode for multi ADC mode.
+                                   This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
+  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
+                                   This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
+}ADC_MultiModeTypeDef;
+
+/**
+  * @}
+  */ 
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADCEx_Common_mode ADC Common Mode
+  * @{
+  */
+#define ADC_MODE_INDEPENDENT                  ((uint32_t)0x00000000U)      
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)ADC_CCR_MULTI_0)
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)ADC_CCR_MULTI_1)
+#define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
+#define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
+#define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
+#define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT  ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig    ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
+#define ADC_TRIPLEMODE_INJECSIMULT            ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
+#define ADC_TRIPLEMODE_INTERL                 ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_ALTERTRIG              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
+  * @{
+  */ 
+#define ADC_DMAACCESSMODE_DISABLED  ((uint32_t)0x00000000U)     /*!< DMA mode disabled */
+#define ADC_DMAACCESSMODE_1         ((uint32_t)ADC_CCR_DMA_0)  /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
+#define ADC_DMAACCESSMODE_2         ((uint32_t)ADC_CCR_DMA_1)  /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
+#define ADC_DMAACCESSMODE_3         ((uint32_t)ADC_CCR_DMA)    /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
+/**
+  * @}
+  */ 
+
+/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
+  * @{
+  */
+#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           ((uint32_t)0x00000000U)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
+  * @{
+  */
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO         ((uint32_t)0x00000000U)
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4          ((uint32_t)ADC_CR2_JEXTSEL_0)
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO         ((uint32_t)ADC_CR2_JEXTSEL_1)
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4          ((uint32_t)ADC_CR2_JEXTSEL_2)
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4          ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2        ((uint32_t)ADC_CR2_JEXTSEL_3)
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2        ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC3          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADCEx_injected_rank ADC Injected Channel Rank
+  * @{
+  */ 
+#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001U)
+#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002U)
+#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003U)
+#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004U)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADCEx_channels  ADC Specific Channels
+  * @{
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Macros ADC Private Macros
+  * @{
+  */
+                                     
+#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)                 || \
+                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)   || \
+                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)     || \
+                               ((__MODE__) == ADC_DUALMODE_INJECSIMULT)             || \
+                               ((__MODE__) == ADC_DUALMODE_REGSIMULT)               || \
+                               ((__MODE__) == ADC_DUALMODE_INTERL)                  || \
+                               ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               || \
+                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
+                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig)   || \
+                               ((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT)           || \
+                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT)             || \
+                               ((__MODE__) == ADC_TRIPLEMODE_INTERL)                || \
+                               ((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG))
+#define IS_ADC_DMA_ACCESS_MODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
+                                          ((__MODE__) == ADC_DMAACCESSMODE_1)        || \
+                                          ((__MODE__) == ADC_DMAACCESSMODE_2)        || \
+                                          ((__MODE__) == ADC_DMAACCESSMODE_3))
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE)    || \
+                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING)  || \
+                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
+                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
+#define IS_ADC_EXT_INJEC_TRIG(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO)  || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)   || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)  || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \
+                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \
+                                            ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
+#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) == ADC_INJECTED_RANK_1) || \
+                                       ((__RANK__) == ADC_INJECTED_RANK_2) || \
+                                       ((__RANK__) == ADC_INJECTED_RANK_3) || \
+                                       ((__RANK__) == ADC_INJECTED_RANK_4))
+#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
+
+/**
+  * @brief  Set the selected injected Channel rank.
+  * @param  _CHANNELNB_ Channel number.
+  * @param  _RANKNB_ Rank number. 
+  * @param  _JSQR_JL_ Sequence length.     
+  * @retval None
+  */
+#define   ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Functions ADC Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F7xx_ADC_EX_H */
+
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h
new file mode 100644
index 0000000..61907ec
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h
@@ -0,0 +1,406 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_CORTEX_H
+#define __STM32F7xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @brief  MPU Region initialization structure 
+  * @{
+  */
+typedef struct
+{
+  uint8_t                Enable;                /*!< Specifies the status of the region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
+                                                                 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
+                                                                 0 bits for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source 
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000U)
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004U)
+
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000U)  
+#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002U)
+#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004U)
+#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE     ((uint8_t)0x01U)
+#define  MPU_REGION_DISABLE    ((uint8_t)0x00U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00U)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01U)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01U)
+#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01U)
+#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0    ((uint8_t)0x00U)
+#define  MPU_TEX_LEVEL1    ((uint8_t)0x01U)
+#define  MPU_TEX_LEVEL2    ((uint8_t)0x02U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
+#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06U) 
+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07U) 
+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08U) 
+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)  
+#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) 
+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) 
+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) 
+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) 
+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) 
+#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
+#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
+#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) 
+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) 
+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) 
+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) 
+#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
+#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
+#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
+#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
+#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
+#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) 
+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) 
+#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
+/**                                
+  * @}
+  */
+   
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00U)  
+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01U) 
+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02U)  
+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03U)  
+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05U) 
+#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00U)  
+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01U) 
+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02U)  
+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03U)  
+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04U) 
+#define  MPU_REGION_NUMBER5    ((uint8_t)0x05U)
+#define  MPU_REGION_NUMBER6    ((uint8_t)0x06U)
+#define  MPU_REGION_NUMBER7    ((uint8_t)0x07U)
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+  
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_EnableRegion(uint32_t RegionNumber);
+void HAL_MPU_DisableRegion(uint32_t RegionNumber);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/ 
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FFU)
+#endif /* __MPU_PRESENT */
+
+/**                                                                          
+  * @}
+  */                                                                            
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_CORTEX_H */
+ 
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h
new file mode 100644
index 0000000..d0c34b6
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h
@@ -0,0 +1,220 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and 
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_DEF
+#define __STM32F7xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+#include "Legacy/stm32_hal_legacy.h"
+#include 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  HAL Status structures definition  
+  */  
+typedef enum 
+{
+  HAL_OK       = 0x00U,
+  HAL_ERROR    = 0x01U,
+  HAL_BUSY     = 0x02U,
+  HAL_TIMEOUT  = 0x03U
+} HAL_StatusTypeDef;
+
+/** 
+  * @brief  HAL Lock structures definition  
+  */
+typedef enum 
+{
+  HAL_UNLOCKED = 0x00U,
+  HAL_LOCKED   = 0x01U  
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+
+#if !defined(UNUSED)
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
+#endif /* UNUSED */
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
+                        do{                                                      \
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0)
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__ specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose: 
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function 
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+
+#if (USE_RTOS == 1U)
+  /* Reserved for future use */
+  #error "USE_RTOS should be 0 in the current HAL release"
+#else
+  #define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0U)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0U)
+#endif /* USE_RTOS */
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __weak
+    #define __weak  __attribute__((weak))
+  #endif
+  #ifndef __packed
+    #define __packed  __attribute__((packed))
+  #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif
+  #ifndef __ALIGN_END
+    #define __ALIGN_END      __attribute__ ((aligned (4)))
+  #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN  
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN      
+    #if defined   (__CC_ARM)      /* ARM Compiler V5*/
+      #define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN 
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
+#if defined   (__GNUC__)      /* GNU Compiler */
+  #define ALIGN_32BYTES(buf)  buf __attribute__ ((aligned (32)))
+#elif defined (__ICCARM__)    /* IAR Compiler */
+  #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf
+#elif defined (__CC_ARM)      /* ARM Compiler */
+  #define ALIGN_32BYTES(buf) __align(32) buf
+#endif
+
+/**
+  * @brief  __RAM_FUNC definition
+  */ 
+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+   --------------------------
+   RAM functions are defined using the toolchain options. 
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog. 
+*/
+#define __RAM_FUNC 
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute 
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+/** 
+  * @brief  __NOINLINE definition
+  */ 
+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )
+/* ARM V4/V5 and V6 & GNU Compiler
+   -------------------------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F7xx_HAL_DEF */
+
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h
new file mode 100644
index 0000000..cca4509
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h
@@ -0,0 +1,747 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_DMA_H
+#define __STM32F7xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @brief    DMA Exported Types 
+  * @{
+  */
+   
+/** 
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Channel;              /*!< Specifies the channel used for the specified stream. 
+                                      This parameter can be a value of @ref DMAEx_Channel_selection                  */
+
+  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral, 
+                                      from memory to memory or from peripheral to memory.
+                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */
+
+  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
+
+  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */
+
+  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
+                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */
+
+  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_Memory_data_size                     */
+
+  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_mode
+                                      @note The circular buffer mode cannot be used if the memory-to-memory
+                                            data transfer is configured on the selected Stream                        */
+
+  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_Priority_level                       */
+
+  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                      This parameter can be a value of @ref DMA_FIFO_direct_mode
+                                      @note The Direct mode (FIFO mode disabled) cannot be used if the 
+                                            memory-to-memory data transfer is configured on the selected stream       */
+
+  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
+                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
+
+  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers. 
+                                      It specifies the amount of data to be transferred in a single non interruptible 
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Memory_burst 
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+
+  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
+                                      It specifies the amount of data to be transferred in a single non interruptible 
+                                      transaction. 
+                                      This parameter can be a value of @ref DMA_Peripheral_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+}DMA_InitTypeDef;
+
+/** 
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
+  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
+  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
+}HAL_DMA_StateTypeDef;
+
+/** 
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/** 
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
+  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
+  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
+}HAL_DMA_CallbackIDTypeDef;
+
+/** 
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */
+
+  DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */ 
+
+  HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */  
+
+  __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
+
+  void                       *Parent;                                                      /*!< Parent object state                    */ 
+
+  void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
+
+  void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
+
+  void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
+  
+  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
+  
+  void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
+  
+  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer Abort callback            */  
+
+ __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                          */
+  
+ uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
+
+ uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */
+ 
+}DMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @brief    DMA Exported constants 
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @brief    DMA Error Code 
+  * @{
+  */ 
+#define HAL_DMA_ERROR_NONE                       0x00000000U    /*!< No error                               */
+#define HAL_DMA_ERROR_TE                         0x00000001U    /*!< Transfer error                         */
+#define HAL_DMA_ERROR_FE                         0x00000002U    /*!< FIFO error                             */
+#define HAL_DMA_ERROR_DME                        0x00000004U    /*!< Direct Mode error                      */
+#define HAL_DMA_ERROR_TIMEOUT                    0x00000020U    /*!< Timeout error                          */
+#define HAL_DMA_ERROR_PARAM                      0x00000040U    /*!< Parameter error                        */
+#define HAL_DMA_ERROR_NO_XFER                    0x00000080U    /*!< Abort requested with no Xfer ongoing   */
+#define HAL_DMA_ERROR_NOT_SUPPORTED              0x00000100U    /*!< Not supported mode                     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @brief    DMA data transfer direction 
+  * @{
+  */ 
+#define DMA_PERIPH_TO_MEMORY                     0x00000000U      /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH                     DMA_SxCR_DIR_0   /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY                     DMA_SxCR_DIR_1   /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+        
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @brief    DMA peripheral incremented mode 
+  * @{
+  */ 
+#define DMA_PINC_ENABLE                          DMA_SxCR_PINC    /*!< Peripheral increment mode enable  */
+#define DMA_PINC_DISABLE                         0x00000000U      /*!< Peripheral increment mode disable */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @brief    DMA memory incremented mode 
+  * @{
+  */ 
+#define DMA_MINC_ENABLE                          DMA_SxCR_MINC    /*!< Memory increment mode enable  */
+#define DMA_MINC_DISABLE                         0x00000000U      /*!< Memory increment mode disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @brief    DMA peripheral data size 
+  * @{
+  */ 
+#define DMA_PDATAALIGN_BYTE                      0x00000000U        /*!< Peripheral data alignment: Byte     */
+#define DMA_PDATAALIGN_HALFWORD                  DMA_SxCR_PSIZE_0   /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD                      DMA_SxCR_PSIZE_1   /*!< Peripheral data alignment: Word     */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @brief    DMA memory data size 
+  * @{ 
+  */
+#define DMA_MDATAALIGN_BYTE                      0x00000000U        /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD                  DMA_SxCR_MSIZE_0   /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD                      DMA_SxCR_MSIZE_1   /*!< Memory data alignment: Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @brief    DMA mode 
+  * @{
+  */ 
+#define DMA_NORMAL                               0x00000000U       /*!< Normal mode                  */
+#define DMA_CIRCULAR                             DMA_SxCR_CIRC     /*!< Circular mode                */
+#define DMA_PFCTRL                               DMA_SxCR_PFCTRL   /*!< Peripheral flow control mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @brief    DMA priority levels 
+  * @{
+  */
+#define DMA_PRIORITY_LOW                         0x00000000U    /*!< Priority level: Low       */
+#define DMA_PRIORITY_MEDIUM                      DMA_SxCR_PL_0  /*!< Priority level: Medium    */
+#define DMA_PRIORITY_HIGH                        DMA_SxCR_PL_1  /*!< Priority level: High      */
+#define DMA_PRIORITY_VERY_HIGH                   DMA_SxCR_PL    /*!< Priority level: Very High */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
+  * @brief    DMA FIFO direct mode
+  * @{
+  */
+#define DMA_FIFOMODE_DISABLE                     0x00000000U       /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE                      DMA_SxFCR_DMDIS   /*!< FIFO mode enable  */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
+  * @brief    DMA FIFO level 
+  * @{
+  */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL          0x00000000U       /*!< FIFO threshold 1 quart full configuration  */
+#define DMA_FIFO_THRESHOLD_HALFFULL              DMA_SxFCR_FTH_0   /*!< FIFO threshold half full configuration     */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL         DMA_SxFCR_FTH_1   /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL                  DMA_SxFCR_FTH     /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Memory_burst DMA Memory burst
+  * @brief    DMA memory burst 
+  * @{
+  */ 
+#define DMA_MBURST_SINGLE                        0x00000000U
+#define DMA_MBURST_INC4                          DMA_SxCR_MBURST_0
+#define DMA_MBURST_INC8                          DMA_SxCR_MBURST_1
+#define DMA_MBURST_INC16                         DMA_SxCR_MBURST
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
+  * @brief    DMA peripheral burst 
+  * @{
+  */ 
+#define DMA_PBURST_SINGLE                        0x00000000U
+#define DMA_PBURST_INC4                          DMA_SxCR_PBURST_0
+#define DMA_PBURST_INC8                          DMA_SxCR_PBURST_1
+#define DMA_PBURST_INC16                         DMA_SxCR_PBURST
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @brief    DMA interrupts definition 
+  * @{
+  */
+#define DMA_IT_TC                                DMA_SxCR_TCIE
+#define DMA_IT_HT                                DMA_SxCR_HTIE
+#define DMA_IT_TE                                DMA_SxCR_TEIE
+#define DMA_IT_DME                               DMA_SxCR_DMEIE
+#define DMA_IT_FE                                0x00000080U
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @brief    DMA flag definitions 
+  * @{
+  */ 
+#define DMA_FLAG_FEIF0_4                         0x00000001U
+#define DMA_FLAG_DMEIF0_4                        0x00000004U
+#define DMA_FLAG_TEIF0_4                         0x00000008U
+#define DMA_FLAG_HTIF0_4                         0x00000010U
+#define DMA_FLAG_TCIF0_4                         0x00000020U
+#define DMA_FLAG_FEIF1_5                         0x00000040U
+#define DMA_FLAG_DMEIF1_5                        0x00000100U
+#define DMA_FLAG_TEIF1_5                         0x00000200U
+#define DMA_FLAG_HTIF1_5                         0x00000400U
+#define DMA_FLAG_TCIF1_5                         0x00000800U
+#define DMA_FLAG_FEIF2_6                         0x00010000U
+#define DMA_FLAG_DMEIF2_6                        0x00040000U
+#define DMA_FLAG_TEIF2_6                         0x00080000U
+#define DMA_FLAG_HTIF2_6                         0x00100000U
+#define DMA_FLAG_TCIF2_6                         0x00200000U
+#define DMA_FLAG_FEIF3_7                         0x00400000U
+#define DMA_FLAG_DMEIF3_7                        0x01000000U
+#define DMA_FLAG_TEIF3_7                         0x02000000U
+#define DMA_FLAG_HTIF3_7                         0x04000000U
+#define DMA_FLAG_TCIF3_7                         0x08000000U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+ 
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA handle state
+  * @param  __HANDLE__ specifies the DMA handle.
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Return the current DMA Stream FIFO filled level.
+  * @param  __HANDLE__ DMA handle
+  * @retval The FIFO filling state.
+  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
+  *                                              and not empty.
+  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+  *           - DMA_FIFOStatus_Empty: when FIFO is empty
+  *           - DMA_FIFOStatus_Full: when FIFO is full
+  */
+#define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
+
+/**
+  * @brief  Enable the specified DMA Stream.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
+
+/**
+  * @brief  Disable the specified DMA Stream.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Stream transfer complete flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+   DMA_FLAG_TCIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream half transfer complete flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified half transfer complete flag index.
+  */      
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+   DMA_FLAG_HTIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream transfer error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+   DMA_FLAG_TEIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream FIFO error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified FIFO error flag index.
+  */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+   DMA_FLAG_FEIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream direct mode error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified direct mode error flag index.
+  */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+   DMA_FLAG_DMEIF3_7)
+
+/**
+  * @brief  Get the DMA Stream pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+
+/**
+  * @brief  Clear the DMA Stream pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
+  * @retval None
+  */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+
+/**
+  * @brief  Enable the specified DMA Stream interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
+  *        This parameter can be one of the following values:
+  *           @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *           @arg DMA_IT_TE: Transfer error interrupt mask.
+  *           @arg DMA_IT_FE: FIFO error interrupt mask.
+  *           @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
+
+/**
+  * @brief  Disable the specified DMA Stream interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
+
+/**
+  * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval The state of DMA_IT.
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
+                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Writes the number of data units to be transferred on the DMA Stream.
+  * @param  __HANDLE__ DMA handle
+  * @param  __COUNTER__ Number of data units to be transferred (from 0 to 65535) 
+  *          Number of data items depends only on the Peripheral data format.
+  *            
+  * @note   If Peripheral data format is Bytes: number of data units is equal 
+  *         to total number of bytes to be transferred.
+  *           
+  * @note   If Peripheral data format is Half-Word: number of data units is  
+  *         equal to total number of bytes to be transferred / 2.
+  *           
+  * @note   If Peripheral data format is Word: number of data units is equal 
+  *         to total  number of bytes to be transferred / 4.
+  *      
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
+  */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
+
+/**
+  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
+  * @param  __HANDLE__ DMA handle
+  *   
+  * @retval The number of remaining data units in the current DMA Stream transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
+
+
+/* Include DMA HAL Extension module */
+#include "stm32f7xx_hal_dma_ex.h"   
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+  * @brief    DMA Exported functions 
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief   Initialization and de-initialization functions 
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
+  * @brief   I/O operation functions  
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+  * @brief    Peripheral State functions 
+  * @{
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */ 
+/**
+  * @}
+  */ 
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+  * @brief    DMA private defines and constants 
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @brief    DMA private macros 
+  * @{
+  */
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR) || \
+                           ((MODE) == DMA_PFCTRL)) 
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+                                       ((STATE) == DMA_FIFOMODE_ENABLE))
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+                                    ((BURST) == DMA_MBURST_INC4)   || \
+                                    ((BURST) == DMA_MBURST_INC8)   || \
+                                    ((BURST) == DMA_MBURST_INC16))
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+                                        ((BURST) == DMA_PBURST_INC4)   || \
+                                        ((BURST) == DMA_PBURST_INC8)   || \
+                                        ((BURST) == DMA_PBURST_INC16))
+/**
+  * @}
+  */ 
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @brief    DMA private  functions 
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_DMA_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h
new file mode 100644
index 0000000..286fb30
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h
@@ -0,0 +1,183 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_DMA_EX_H
+#define __STM32F7xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+  * @brief DMAEx Exported types
+  * @{
+  */
+   
+/** 
+  * @brief  HAL DMA Memory definition  
+  */ 
+typedef enum
+{
+  MEMORY0      = 0x00U,    /*!< Memory 0     */
+  MEMORY1      = 0x01U,    /*!< Memory 1     */
+
+}HAL_DMA_MemoryTypeDef;
+
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @brief    DMA Exported constants 
+  * @{
+  */
+
+/** @defgroup DMAEx_Channel_selection DMA Channel selection
+  * @brief    DMAEx channel selection 
+  * @{
+  */ 
+#define DMA_CHANNEL_0                     0x00000000U  /*!< DMA Channel 0 */
+#define DMA_CHANNEL_1                     0x02000000U  /*!< DMA Channel 1 */
+#define DMA_CHANNEL_2                     0x04000000U  /*!< DMA Channel 2 */
+#define DMA_CHANNEL_3                     0x06000000U  /*!< DMA Channel 3 */
+#define DMA_CHANNEL_4                     0x08000000U  /*!< DMA Channel 4 */
+#define DMA_CHANNEL_5                     0x0A000000U  /*!< DMA Channel 5 */
+#define DMA_CHANNEL_6                     0x0C000000U  /*!< DMA Channel 6 */
+#define DMA_CHANNEL_7                     0x0E000000U  /*!< DMA Channel 7 */
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
+    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
+    defined (STM32F779xx) || defined (STM32F730xx)
+#define DMA_CHANNEL_8                     0x10000000U  /*!< DMA Channel 8 */
+#define DMA_CHANNEL_9                     0x12000000U  /*!< DMA Channel 9 */
+#define DMA_CHANNEL_10                    0x14000000U  /*!< DMA Channel 10*/
+#define DMA_CHANNEL_11                    0x16000000U  /*!< DMA Channel 11*/
+#define DMA_CHANNEL_12                    0x18000000U  /*!< DMA Channel 12*/
+#define DMA_CHANNEL_13                    0x1A000000U  /*!< DMA Channel 13*/
+#define DMA_CHANNEL_14                    0x1C000000U  /*!< DMA Channel 14*/
+#define DMA_CHANNEL_15                    0x1E000000U  /*!< DMA Channel 15*/
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
+          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+  * @brief   DMAEx Exported functions
+  * @{
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
+  * @brief   Extended features functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+  
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMA Private Macros
+  * @brief    DMAEx private macros 
+  * @{
+  */
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
+    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
+    defined (STM32F779xx) || defined (STM32F730xx)
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0)  || \
+                                 ((CHANNEL) == DMA_CHANNEL_1)  || \
+                                 ((CHANNEL) == DMA_CHANNEL_2)  || \
+                                 ((CHANNEL) == DMA_CHANNEL_3)  || \
+                                 ((CHANNEL) == DMA_CHANNEL_4)  || \
+                                 ((CHANNEL) == DMA_CHANNEL_5)  || \
+                                 ((CHANNEL) == DMA_CHANNEL_6)  || \
+                                 ((CHANNEL) == DMA_CHANNEL_7)  || \
+                                 ((CHANNEL) == DMA_CHANNEL_8)  || \
+                                 ((CHANNEL) == DMA_CHANNEL_9)  || \
+                                 ((CHANNEL) == DMA_CHANNEL_10) || \
+                                 ((CHANNEL) == DMA_CHANNEL_11) || \
+                                 ((CHANNEL) == DMA_CHANNEL_12) || \
+                                 ((CHANNEL) == DMA_CHANNEL_13) || \
+                                 ((CHANNEL) == DMA_CHANNEL_14) || \
+                                 ((CHANNEL) == DMA_CHANNEL_15)) 
+#else
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+                                 ((CHANNEL) == DMA_CHANNEL_1) || \
+                                 ((CHANNEL) == DMA_CHANNEL_2) || \
+                                 ((CHANNEL) == DMA_CHANNEL_3) || \
+                                 ((CHANNEL) == DMA_CHANNEL_4) || \
+                                 ((CHANNEL) == DMA_CHANNEL_5) || \
+                                 ((CHANNEL) == DMA_CHANNEL_6) || \
+                                 ((CHANNEL) == DMA_CHANNEL_7))
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
+          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx*/
+/**
+  * @}
+  */  
+         
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+  * @brief DMAEx Private functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_DMA_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h
new file mode 100644
index 0000000..992d22e
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h
@@ -0,0 +1,317 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_HAL_EXTI_H
+#define STM32F7xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup EXTI EXTI
+  * @brief EXTI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+  * @{
+  */
+typedef enum
+{
+  HAL_EXTI_COMMON_CB_ID          = 0x00U
+} EXTI_CallbackIDTypeDef;
+
+/**
+  * @brief  EXTI Handle structure definition
+  */
+typedef struct
+{
+  uint32_t Line;                    /*!<  Exti line number */
+  void (* PendingCallback)(void);   /*!<  Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Line;      /*!< The Exti line to be configured. This parameter
+                           can be a value of @ref EXTI_Line */
+  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
+                           This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
+                           can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
+                           This parameter is only possible for line 0 to 15. It
+                           can be a value of @ref EXTI_GPIOSel */
+} EXTI_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                          (EXTI_GPIO       | 0x00u)    /*!< External interrupt line 0 */
+#define EXTI_LINE_1                          (EXTI_GPIO       | 0x01u)    /*!< External interrupt line 1 */
+#define EXTI_LINE_2                          (EXTI_GPIO       | 0x02u)    /*!< External interrupt line 2 */
+#define EXTI_LINE_3                          (EXTI_GPIO       | 0x03u)    /*!< External interrupt line 3 */
+#define EXTI_LINE_4                          (EXTI_GPIO       | 0x04u)    /*!< External interrupt line 4 */
+#define EXTI_LINE_5                          (EXTI_GPIO       | 0x05u)    /*!< External interrupt line 5 */
+#define EXTI_LINE_6                          (EXTI_GPIO       | 0x06u)    /*!< External interrupt line 6 */
+#define EXTI_LINE_7                          (EXTI_GPIO       | 0x07u)    /*!< External interrupt line 7 */
+#define EXTI_LINE_8                          (EXTI_GPIO       | 0x08u)    /*!< External interrupt line 8 */
+#define EXTI_LINE_9                          (EXTI_GPIO       | 0x09u)    /*!< External interrupt line 9 */
+#define EXTI_LINE_10                         (EXTI_GPIO       | 0x0Au)    /*!< External interrupt line 10 */
+#define EXTI_LINE_11                         (EXTI_GPIO       | 0x0Bu)    /*!< External interrupt line 11 */
+#define EXTI_LINE_12                         (EXTI_GPIO       | 0x0Cu)    /*!< External interrupt line 12 */
+#define EXTI_LINE_13                         (EXTI_GPIO       | 0x0Du)    /*!< External interrupt line 13 */
+#define EXTI_LINE_14                         (EXTI_GPIO       | 0x0Eu)    /*!< External interrupt line 14 */
+#define EXTI_LINE_15                         (EXTI_GPIO       | 0x0Fu)    /*!< External interrupt line 15 */
+#define EXTI_LINE_16                         (EXTI_CONFIG     | 0x10u)    /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE_17                         (EXTI_CONFIG     | 0x11u)    /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_LINE_18                         (EXTI_CONFIG     | 0x12u)    /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
+#if defined(ETH)
+#define EXTI_LINE_19                         (EXTI_CONFIG     | 0x13u)    /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#else
+#define EXTI_LINE_19                         (EXTI_RESERVED   | 0x13u)    /*!< No interrupt supported in this line */
+#endif /* ETH */
+#define EXTI_LINE_20                         (EXTI_CONFIG     | 0x14u)    /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event  */
+#define EXTI_LINE_21                         (EXTI_CONFIG     | 0x15u)    /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define EXTI_LINE_22                         (EXTI_CONFIG     | 0x16u)    /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#define EXTI_LINE_23                         (EXTI_CONFIG     | 0x17u)    /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
+#if defined(EXTI_IMR_IM24)
+#define EXTI_LINE_24                         (EXTI_CONFIG     | 0x18u)    /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */
+#endif /* EXTI_IMR_IM24 */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_NONE                      0x00000000u
+#define EXTI_MODE_INTERRUPT                 0x00000001u
+#define EXTI_MODE_EVENT                     0x00000002u
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+
+#define EXTI_TRIGGER_NONE                   0x00000000u
+#define EXTI_TRIGGER_RISING                 0x00000001u
+#define EXTI_TRIGGER_FALLING                0x00000002u
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000u
+#define EXTI_GPIOB                          0x00000001u
+#define EXTI_GPIOC                          0x00000002u
+#define EXTI_GPIOD                          0x00000003u
+#define EXTI_GPIOE                          0x00000004u
+#define EXTI_GPIOF                          0x00000005u
+#define EXTI_GPIOG                          0x00000006u
+#define EXTI_GPIOH                          0x00000007u
+#define EXTI_GPIOI                          0x00000008u
+#define EXTI_GPIOJ                          0x00000009u
+#if defined (GPIOK)
+#define EXTI_GPIOK                          0x0000000Au
+#endif /* GPIOK */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+/**
+  * @brief  EXTI Line property definition
+  */
+#define EXTI_PROPERTY_SHIFT                  24u
+#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK                  (EXTI_CONFIG | EXTI_GPIO)
+
+/**
+  * @brief  EXTI bit usage
+  */
+#define EXTI_PIN_MASK                       0x0000001Fu
+
+/**
+  * @brief  EXTI Mask for interrupt & event mode
+  */
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+  * @brief  EXTI Mask for trigger possibilities
+  */
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+  * @brief  EXTI Line number
+  */
+#if defined(EXTI_IMR_IM24)
+#define EXTI_LINE_NB                        25u
+#else
+#define EXTI_LINE_NB                        24u
+#endif /* EXTI_IMR_IM24 */
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_LINE(__EXTI_LINE__)          ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+                                             ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
+                                              (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
+                                              (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
+
+#define IS_EXTI_MODE(__EXTI_LINE__)          ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
+                                              (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+
+#define IS_EXTI_TRIGGER(__EXTI_LINE__)       (((__EXTI_LINE__)  & ~EXTI_TRIGGER_MASK) == 0x00u)
+
+#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__)  (((__EXTI_LINE__) == EXTI_TRIGGER_FALLING) || \
+                                              ((__EXTI_LINE__) == EXTI_TRIGGER_RISING)  || \
+                                              ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
+
+#if defined (GPIOK)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH) || \
+                                         ((__PORT__) == EXTI_GPIOI) || \
+                                         ((__PORT__) == EXTI_GPIOJ) || \
+                                         ((__PORT__) == EXTI_GPIOK))
+#else
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH) || \
+                                         ((__PORT__) == EXTI_GPIOI) || \
+                                         ((__PORT__) == EXTI_GPIOJ))
+#endif /* GPIOK */
+
+#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16U)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+  * @brief    EXTI Exported Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+  * @brief    Configuration functions
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F7xx_HAL_EXTI_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h
new file mode 100644
index 0000000..39e859e
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h
@@ -0,0 +1,415 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_flash.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_FLASH_H
+#define __STM32F7xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum
+{
+  FLASH_PROC_NONE = 0U,
+  FLASH_PROC_SECTERASE,
+  FLASH_PROC_MASSERASE,
+  FLASH_PROC_PROGRAM
+} FLASH_ProcedureTypeDef;
+
+
+/**
+  * @brief  FLASH handle Structure definition
+  */
+typedef struct
+{
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /* Internal variable to indicate which procedure is ongoing or not in IT context */
+
+  __IO uint32_t               NbSectorsToErase;   /* Internal variable to save the remaining sectors to erase in IT context        */
+
+  __IO uint8_t                VoltageForErase;    /* Internal variable to provide voltage range selected by user in IT context     */
+
+  __IO uint32_t               Sector;             /* Internal variable to define the current sector which is erasing               */
+
+  __IO uint32_t               Address;            /* Internal variable to save address selected for program                        */
+
+  HAL_LockTypeDef             Lock;               /* FLASH locking object                                                          */
+
+  __IO uint32_t               ErrorCode;          /* FLASH error code                                                              */
+
+}FLASH_ProcessTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASH_Error_Code FLASH Error Code
+  * @brief    FLASH Error Code
+  * @{
+  */
+#define HAL_FLASH_ERROR_NONE         ((uint32_t)0x00000000U)    /*!< No error                      */
+#define HAL_FLASH_ERROR_ERS          ((uint32_t)0x00000002U)    /*!< Programming Sequence error    */
+#define HAL_FLASH_ERROR_PGP          ((uint32_t)0x00000004U)    /*!< Programming Parallelism error */
+#define HAL_FLASH_ERROR_PGA          ((uint32_t)0x00000008U)    /*!< Programming Alignment error   */
+#define HAL_FLASH_ERROR_WRP          ((uint32_t)0x00000010U)    /*!< Write protection error        */
+#define HAL_FLASH_ERROR_OPERATION    ((uint32_t)0x00000020U)    /*!< Operation Error               */
+#define HAL_FLASH_ERROR_RD           ((uint32_t)0x00000040U)    /*!< Read Protection Error         */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+  * @{
+  */
+#define FLASH_TYPEPROGRAM_BYTE        ((uint32_t)0x00U)  /*!< Program byte (8-bit) at a specified address           */
+#define FLASH_TYPEPROGRAM_HALFWORD    ((uint32_t)0x01U)  /*!< Program a half-word (16-bit) at a specified address   */
+#define FLASH_TYPEPROGRAM_WORD        ((uint32_t)0x02U)  /*!< Program a word (32-bit) at a specified address        */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD  ((uint32_t)0x03U)  /*!< Program a double word (64-bit) at a specified address */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+  * @brief Flag definition
+  * @{
+  */
+#define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */
+#define FLASH_FLAG_OPERR               FLASH_SR_OPERR          /*!< FLASH operation Error flag                */
+#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */
+#define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */
+#define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */
+#define FLASH_FLAG_ERSERR              FLASH_SR_ERSERR         /*!< FLASH Erasing Sequence error flag         */
+#define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */
+
+#if defined (FLASH_OPTCR2_PCROP)
+#define FLASH_FLAG_RDERR               FLASH_SR_RDERR          /*!< FLASH Read protection error flag          */
+#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+                                   FLASH_FLAG_PGPERR  | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR)
+#else
+#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+                                   FLASH_FLAG_PGPERR  | FLASH_FLAG_ERSERR)
+#endif /* FLASH_OPTCR2_PCROP */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */
+#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR                   ((uint32_t)0x02000000U)  /*!< Error Interrupt source                  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
+  * @{
+  */
+#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000U)
+#define FLASH_PSIZE_HALF_WORD      ((uint32_t)FLASH_CR_PSIZE_0)
+#define FLASH_PSIZE_WORD           ((uint32_t)FLASH_CR_PSIZE_1)
+#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)FLASH_CR_PSIZE)
+#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFFU)
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Keys FLASH Keys
+  * @{
+  */
+#define FLASH_KEY1               ((uint32_t)0x45670123U)
+#define FLASH_KEY2               ((uint32_t)0xCDEF89ABU)
+#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3BU)
+#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7FU)
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Sectors FLASH Sectors
+  * @{
+  */
+#if (FLASH_SECTOR_TOTAL == 2)
+#define FLASH_SECTOR_0           ((uint32_t)0U) /*!< Sector Number 0   */
+#define FLASH_SECTOR_1           ((uint32_t)1U) /*!< Sector Number 1   */
+#elif (FLASH_SECTOR_TOTAL == 4)
+#define FLASH_SECTOR_0           ((uint32_t)0U) /*!< Sector Number 0   */
+#define FLASH_SECTOR_1           ((uint32_t)1U) /*!< Sector Number 1   */
+#define FLASH_SECTOR_2           ((uint32_t)2U) /*!< Sector Number 2   */
+#define FLASH_SECTOR_3           ((uint32_t)3U) /*!< Sector Number 3   */
+#else
+#define FLASH_SECTOR_0           ((uint32_t)0U) /*!< Sector Number 0   */
+#define FLASH_SECTOR_1           ((uint32_t)1U) /*!< Sector Number 1   */
+#define FLASH_SECTOR_2           ((uint32_t)2U) /*!< Sector Number 2   */
+#define FLASH_SECTOR_3           ((uint32_t)3U) /*!< Sector Number 3   */
+#define FLASH_SECTOR_4           ((uint32_t)4U) /*!< Sector Number 4   */
+#define FLASH_SECTOR_5           ((uint32_t)5U) /*!< Sector Number 5   */
+#define FLASH_SECTOR_6           ((uint32_t)6U) /*!< Sector Number 6   */
+#define FLASH_SECTOR_7           ((uint32_t)7U) /*!< Sector Number 7   */
+#endif /* FLASH_SECTOR_TOTAL */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__ FLASH Latency
+  *         The value of this parameter depend on device used within the same series
+  * @retval none
+  */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
+                  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
+
+/**
+  * @brief  Get the FLASH Latency.
+  * @retval FLASH Latency
+  *          The value of this parameter depend on device used within the same series
+  */
+#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+  * @brief  Enable the FLASH prefetch buffer.
+  * @retval none
+  */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)
+
+/**
+  * @brief  Disable the FLASH prefetch buffer.
+  * @retval none
+  */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
+
+/**
+  * @brief  Enable the FLASH Adaptive Real-Time memory accelerator.
+  * @note   The ART accelerator is available only for flash access on ITCM interface.
+  * @retval none
+  */
+#define __HAL_FLASH_ART_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
+
+/**
+  * @brief  Disable the FLASH Adaptive Real-Time memory accelerator.
+  * @retval none
+  */
+#define __HAL_FLASH_ART_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
+
+/**
+  * @brief  Resets the FLASH Adaptive Real-Time memory accelerator.
+  * @note   This function must be used only when the Adaptive Real-Time memory accelerator
+  *         is disabled.
+  * @retval None
+  */
+#define __HAL_FLASH_ART_RESET()  (FLASH->ACR |= FLASH_ACR_ARTRST)
+
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__  FLASH interrupt
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_ERR: Error Interrupt
+  * @retval none
+  */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__  FLASH interrupt
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_ERR: Error Interrupt
+  * @retval none
+  */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
+
+/**
+  * @brief  Get the specified FLASH flag status.
+  * @param  __FLAG__ specifies the FLASH flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag
+  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+  *            @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
+  *            @arg FLASH_FLAG_BSY   : FLASH Busy flag
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))
+
+/**
+  * @brief  Clear the specified FLASH flag.
+  * @param  __FLAG__ specifies the FLASH flags to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag
+  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+  *            @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
+  * @retval none
+  */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))
+/**
+  * @}
+  */
+
+/* Include FLASH HAL Extension module */
+#include "stm32f7xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+  * @{
+  */
+/** @addtogroup FLASH_Exported_Functions_Group1
+  * @{
+  */
+/* Program operation functions  ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+uint32_t HAL_FLASH_GetError(void);
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+  * @{
+  */
+
+/**
+  * @brief   OPTCR register byte 1 (Bits[15:8]) base address
+  */
+#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+  * @{
+  */
+
+/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
+  * @{
+  */
+#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
+                                    ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+                                    ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
+                                    ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_FLASH_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h
new file mode 100644
index 0000000..6ec226a
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h
@@ -0,0 +1,697 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_FLASH_EX_H
+#define __STM32F7xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeErase;   /*!< Mass erase or sector Erase.
+                             This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+#if defined (FLASH_OPTCR_nDBANK)
+  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
+                             This parameter must be a value of @ref FLASHEx_Banks */
+#endif /* FLASH_OPTCR_nDBANK */
+
+  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
+                             This parameter must be a value of @ref FLASHEx_Sectors */
+
+  uint32_t NbSectors;   /*!< Number of sectors to be erased.
+                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
+                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
+
+} FLASH_EraseInitTypeDef;
+
+/**
+  * @brief  FLASH Option Bytes Program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;   /*!< Option byte to be configured.
+                              This parameter can be a value of @ref FLASHEx_Option_Type */
+
+  uint32_t WRPState;     /*!< Write protection activation or deactivation.
+                              This parameter can be a value of @ref FLASHEx_WRP_State */
+
+  uint32_t WRPSector;    /*!< Specifies the sector(s) to be write protected.
+                              The value of this parameter depend on device used within the same series */
+
+  uint32_t RDPLevel;     /*!< Set the read protection level.
+                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+
+  uint32_t BORLevel;     /*!< Set the BOR Level.
+                              This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+
+  uint32_t USERConfig;   /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /
+                              IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT.
+                              nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */
+
+  uint32_t BootAddr0;    /*!< Boot base address when Boot pin = 0.
+                              This parameter can be a value of @ref FLASHEx_Boot_Address */
+
+  uint32_t BootAddr1;    /*!< Boot base address when Boot pin = 1.
+                              This parameter can be a value of @ref FLASHEx_Boot_Address */
+
+#if defined (FLASH_OPTCR2_PCROP)
+  uint32_t PCROPSector;  /*!< Set the PCROP sector.
+                              This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */
+
+  uint32_t PCROPRdp;    /*!< Set the PCROP_RDP option.
+                              This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */
+#endif /* FLASH_OPTCR2_PCROP */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+  * @{
+  */
+#define FLASH_TYPEERASE_SECTORS         ((uint32_t)0x00U)  /*!< Sectors erase only          */
+#define FLASH_TYPEERASE_MASSERASE       ((uint32_t)0x01U)  /*!< Flash Mass erase activation */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+  * @{
+  */
+#define FLASH_VOLTAGE_RANGE_1        ((uint32_t)0x00U)  /*!< Device operating range: 1.8V to 2.1V                */
+#define FLASH_VOLTAGE_RANGE_2        ((uint32_t)0x01U)  /*!< Device operating range: 2.1V to 2.7V                */
+#define FLASH_VOLTAGE_RANGE_3        ((uint32_t)0x02U)  /*!< Device operating range: 2.7V to 3.6V                */
+#define FLASH_VOLTAGE_RANGE_4        ((uint32_t)0x03U)  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
+  * @{
+  */
+#define OB_WRPSTATE_DISABLE       ((uint32_t)0x00U)  /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE        ((uint32_t)0x01U)  /*!< Enable the write protection of the desired bank 1 sectors  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
+  * @{
+  */
+#define OPTIONBYTE_WRP         ((uint32_t)0x01U)  /*!< WRP option byte configuration  */
+#define OPTIONBYTE_RDP         ((uint32_t)0x02U)  /*!< RDP option byte configuration  */
+#define OPTIONBYTE_USER        ((uint32_t)0x04U)  /*!< USER option byte configuration */
+#define OPTIONBYTE_BOR         ((uint32_t)0x08U)  /*!< BOR option byte configuration  */
+#define OPTIONBYTE_BOOTADDR_0  ((uint32_t)0x10U)  /*!< Boot 0 Address configuration   */
+#define OPTIONBYTE_BOOTADDR_1  ((uint32_t)0x20U)  /*!< Boot 1 Address configuration   */
+#if defined (FLASH_OPTCR2_PCROP)
+#define OPTIONBYTE_PCROP       ((uint32_t)0x40U)  /*!< PCROP configuration            */
+#define OPTIONBYTE_PCROP_RDP   ((uint32_t)0x80U)  /*!< PCROP_RDP configuration        */
+#endif /* FLASH_OPTCR2_PCROP */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0       ((uint8_t)0xAAU)
+#define OB_RDP_LEVEL_1       ((uint8_t)0x55U)
+#define OB_RDP_LEVEL_2       ((uint8_t)0xCCU)   /*!< Warning: When enabling read protection level 2
+                                                  it s no more possible to go back to level 1 or 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
+  * @{
+  */
+#define OB_WWDG_SW           ((uint32_t)0x10U)  /*!< Software WWDG selected */
+#define OB_WWDG_HW           ((uint32_t)0x00U)  /*!< Hardware WWDG selected */
+/**
+  * @}
+  */
+
+
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+  * @{
+  */
+#define OB_IWDG_SW           ((uint32_t)0x20U)  /*!< Software IWDG selected */
+#define OB_IWDG_HW           ((uint32_t)0x00U)  /*!< Hardware IWDG selected */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+  * @{
+  */
+#define OB_STOP_NO_RST       ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST          ((uint32_t)0x00U) /*!< Reset generated when entering in STOP    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+  * @{
+  */
+#define OB_STDBY_NO_RST      ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST         ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
+  * @{
+  */
+#define OB_IWDG_STOP_FREEZE      ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */
+#define OB_IWDG_STOP_ACTIVE      ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
+  * @{
+  */
+#define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */
+#define OB_IWDG_STDBY_ACTIVE      ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+  * @{
+  */
+#define OB_BOR_LEVEL3          ((uint32_t)0x00U)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
+#define OB_BOR_LEVEL2          ((uint32_t)0x04U)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
+#define OB_BOR_LEVEL1          ((uint32_t)0x08U)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
+#define OB_BOR_OFF             ((uint32_t)0x0CU)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
+/**
+  * @}
+  */
+
+#if defined (FLASH_OPTCR_nDBOOT)
+/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT
+  * @{
+  */
+#define OB_DUAL_BOOT_DISABLE      ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */
+#define OB_DUAL_BOOT_ENABLE       ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash
+                                                              (Dual bank Boot mode), or RAM if Boot address option in RAM    */
+/**
+  * @}
+  */
+#endif /* FLASH_OPTCR_nDBOOT */
+
+#if defined (FLASH_OPTCR_nDBANK)
+/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank
+  * @{
+  */
+#define OB_NDBANK_SINGLE_BANK      ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */
+#define OB_NDBANK_DUAL_BANK        ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */
+/**
+  * @}
+  */
+#endif /* FLASH_OPTCR_nDBANK */
+
+/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
+  * @{
+  */
+#define OB_BOOTADDR_ITCM_RAM         ((uint32_t)0x0000U)  /*!< Boot from ITCM RAM (0x00000000)                 */
+#define OB_BOOTADDR_SYSTEM           ((uint32_t)0x0040U)  /*!< Boot from System memory bootloader (0x00100000) */
+#define OB_BOOTADDR_ITCM_FLASH       ((uint32_t)0x0080U)  /*!< Boot from Flash on ITCM interface (0x00200000)  */
+#define OB_BOOTADDR_AXIM_FLASH       ((uint32_t)0x2000U)  /*!< Boot from Flash on AXIM interface (0x08000000)  */
+#define OB_BOOTADDR_DTCM_RAM         ((uint32_t)0x8000U)  /*!< Boot from DTCM RAM (0x20000000)                 */
+#define OB_BOOTADDR_SRAM1            ((uint32_t)0x8004U)  /*!< Boot from SRAM1 (0x20010000)                    */
+#if (SRAM2_BASE == 0x2003C000U)
+#define OB_BOOTADDR_SRAM2            ((uint32_t)0x800FU)  /*!< Boot from SRAM2 (0x2003C000)                    */
+#else
+#define OB_BOOTADDR_SRAM2            ((uint32_t)0x8013U)  /*!< Boot from SRAM2 (0x2004C000)                    */
+#endif /* SRAM2_BASE == 0x2003C000U */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */
+#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
+#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
+#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
+#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
+#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
+#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
+#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
+#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+#define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */
+#define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */
+#define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
+#define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
+#define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
+#define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
+#define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
+#define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
+/**
+  * @}
+  */
+
+#if defined (FLASH_OPTCR_nDBANK)
+/** @defgroup FLASHEx_Banks FLASH Banks
+  * @{
+  */
+#define FLASH_BANK_1                       ((uint32_t)0x01U)                          /*!< Bank 1   */
+#define FLASH_BANK_2                       ((uint32_t)0x02U)                          /*!< Bank 2   */
+#define FLASH_BANK_BOTH                    ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */
+/**
+  * @}
+  */
+#endif /* FLASH_OPTCR_nDBANK */
+
+/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
+  * @{
+  */
+#if defined (FLASH_OPTCR_nDBANK)
+#define FLASH_MER_BIT     (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */
+#else
+#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER bit */
+#endif /* FLASH_OPTCR_nDBANK */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Sectors FLASH Sectors
+  * @{
+  */
+#if (FLASH_SECTOR_TOTAL == 24)
+#define FLASH_SECTOR_8     ((uint32_t)8U)  /*!< Sector Number 8   */
+#define FLASH_SECTOR_9     ((uint32_t)9U)  /*!< Sector Number 9   */
+#define FLASH_SECTOR_10    ((uint32_t)10U) /*!< Sector Number 10  */
+#define FLASH_SECTOR_11    ((uint32_t)11U) /*!< Sector Number 11  */
+#define FLASH_SECTOR_12    ((uint32_t)12U) /*!< Sector Number 12  */
+#define FLASH_SECTOR_13    ((uint32_t)13U) /*!< Sector Number 13  */
+#define FLASH_SECTOR_14    ((uint32_t)14U) /*!< Sector Number 14  */
+#define FLASH_SECTOR_15    ((uint32_t)15U) /*!< Sector Number 15  */
+#define FLASH_SECTOR_16    ((uint32_t)16U) /*!< Sector Number 16  */
+#define FLASH_SECTOR_17    ((uint32_t)17U) /*!< Sector Number 17  */
+#define FLASH_SECTOR_18    ((uint32_t)18U) /*!< Sector Number 18  */
+#define FLASH_SECTOR_19    ((uint32_t)19U) /*!< Sector Number 19  */
+#define FLASH_SECTOR_20    ((uint32_t)20U) /*!< Sector Number 20  */
+#define FLASH_SECTOR_21    ((uint32_t)21U) /*!< Sector Number 21  */
+#define FLASH_SECTOR_22    ((uint32_t)22U) /*!< Sector Number 22  */
+#define FLASH_SECTOR_23    ((uint32_t)23U) /*!< Sector Number 23  */
+#endif /* FLASH_SECTOR_TOTAL == 24 */
+/**
+  * @}
+  */
+
+#if (FLASH_SECTOR_TOTAL == 24)
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+  * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register,
+  *       nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11.
+  *       For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register,
+  *       nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and
+  *       a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1).
+  *       This behavior is applicable only for STM32F76xxx / STM32F77xxx devices.
+  * @{
+  */
+/* Single Bank Sectors */
+#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0   */
+#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1   */
+#define OB_WRP_SECTOR_2       ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2   */
+#define OB_WRP_SECTOR_3       ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3   */
+#define OB_WRP_SECTOR_4       ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4   */
+#define OB_WRP_SECTOR_5       ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5   */
+#define OB_WRP_SECTOR_6       ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6   */
+#define OB_WRP_SECTOR_7       ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7   */
+#define OB_WRP_SECTOR_8       ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8   */
+#define OB_WRP_SECTOR_9       ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9   */
+#define OB_WRP_SECTOR_10      ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10  */
+#define OB_WRP_SECTOR_11      ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11  */
+#define OB_WRP_SECTOR_All     ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */
+
+/* Dual Bank Sectors */
+#define OB_WRP_DB_SECTOR_0    ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0     */
+#define OB_WRP_DB_SECTOR_1    ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1     */
+#define OB_WRP_DB_SECTOR_2    ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2     */
+#define OB_WRP_DB_SECTOR_3    ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3     */
+#define OB_WRP_DB_SECTOR_4    ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4     */
+#define OB_WRP_DB_SECTOR_5    ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5     */
+#define OB_WRP_DB_SECTOR_6    ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6     */
+#define OB_WRP_DB_SECTOR_7    ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7     */
+#define OB_WRP_DB_SECTOR_8    ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8     */
+#define OB_WRP_DB_SECTOR_9    ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9     */
+#define OB_WRP_DB_SECTOR_10   ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10    */
+#define OB_WRP_DB_SECTOR_11   ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11    */
+#define OB_WRP_DB_SECTOR_12   ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12    */
+#define OB_WRP_DB_SECTOR_13   ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13    */
+#define OB_WRP_DB_SECTOR_14   ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14    */
+#define OB_WRP_DB_SECTOR_15   ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15    */
+#define OB_WRP_DB_SECTOR_16   ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16    */
+#define OB_WRP_DB_SECTOR_17   ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17    */
+#define OB_WRP_DB_SECTOR_18   ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18    */
+#define OB_WRP_DB_SECTOR_19   ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19    */
+#define OB_WRP_DB_SECTOR_20   ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20    */
+#define OB_WRP_DB_SECTOR_21   ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21    */
+#define OB_WRP_DB_SECTOR_22   ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22    */
+#define OB_WRP_DB_SECTOR_23   ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23    */
+#define OB_WRP_DB_SECTOR_All  ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */
+/**
+  * @}
+  */
+#endif /* FLASH_SECTOR_TOTAL == 24 */
+
+#if (FLASH_SECTOR_TOTAL == 8)
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+  * @{
+  */
+#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       ((uint32_t)0x00040000U) /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       ((uint32_t)0x00080000U) /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       ((uint32_t)0x00100000U) /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       ((uint32_t)0x00200000U) /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       ((uint32_t)0x00400000U) /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       ((uint32_t)0x00800000U) /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_All     ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */
+/**
+  * @}
+  */
+#endif /* FLASH_SECTOR_TOTAL == 8 */
+
+#if (FLASH_SECTOR_TOTAL == 4)
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+  * @{
+  */
+#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       ((uint32_t)0x00040000U) /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       ((uint32_t)0x00080000U) /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_All     ((uint32_t)0x000F0000U) /*!< Write protection of all Sectors */
+/**
+  * @}
+  */
+#endif /* FLASH_SECTOR_TOTAL == 4 */
+
+#if (FLASH_SECTOR_TOTAL == 2)
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+  * @{
+  */
+#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_All     ((uint32_t)0x00030000U) /*!< Write protection of all Sectors */
+/**
+  * @}
+  */
+#endif /* FLASH_SECTOR_TOTAL == 2 */
+
+#if defined (FLASH_OPTCR2_PCROP)
+#if (FLASH_SECTOR_TOTAL == 8)
+/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors
+  * @{
+  */
+#define OB_PCROP_SECTOR_0     ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0      */
+#define OB_PCROP_SECTOR_1     ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1      */
+#define OB_PCROP_SECTOR_2     ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2      */
+#define OB_PCROP_SECTOR_3     ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3      */
+#define OB_PCROP_SECTOR_4     ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4      */
+#define OB_PCROP_SECTOR_5     ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5      */
+#define OB_PCROP_SECTOR_6     ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6      */
+#define OB_PCROP_SECTOR_7     ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7      */
+#define OB_PCROP_SECTOR_All   ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors  */
+/**
+  * @}
+  */
+#endif /* FLASH_SECTOR_TOTAL == 8 */
+
+#if (FLASH_SECTOR_TOTAL == 4)
+/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors
+  * @{
+  */
+#define OB_PCROP_SECTOR_0     ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0      */
+#define OB_PCROP_SECTOR_1     ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1      */
+#define OB_PCROP_SECTOR_2     ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2      */
+#define OB_PCROP_SECTOR_3     ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3      */
+#define OB_PCROP_SECTOR_All   ((uint32_t)0x0000000FU) /*!< PC Readout protection of all Sectors  */
+/**
+  * @}
+  */
+#endif /* FLASH_SECTOR_TOTAL == 4 */
+
+/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit
+  * @{
+  */
+#define OB_PCROP_RDP_ENABLE   ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable      */
+#define OB_PCROP_RDP_DISABLE  ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable     */
+/**
+  * @}
+  */
+#endif /* FLASH_OPTCR2_PCROP */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1)
+  * @note   Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
+  * @param  __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
+  * @retval The FLASH Boot Base Address
+  */
+#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
+ /**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+/* Extension Program operation functions  *************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
+  * @{
+  */
+
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
+  * @{
+  */
+
+#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
+                                  ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
+                               ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
+                               ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
+                               ((RANGE) == FLASH_VOLTAGE_RANGE_4))
+
+#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
+                           ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#if defined (FLASH_OPTCR2_PCROP)
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP        | OPTIONBYTE_USER |\
+                                          OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\
+                                          OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP)))
+#else
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP        | OPTIONBYTE_USER |\
+                                          OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))
+#endif /* FLASH_OPTCR2_PCROP */
+
+#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0)   ||\
+                                ((LEVEL) == OB_RDP_LEVEL_1)   ||\
+                                ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
+
+#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
+
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
+                                   ((LATENCY) == FLASH_LATENCY_1)  || \
+                                   ((LATENCY) == FLASH_LATENCY_2)  || \
+                                   ((LATENCY) == FLASH_LATENCY_3)  || \
+                                   ((LATENCY) == FLASH_LATENCY_4)  || \
+                                   ((LATENCY) == FLASH_LATENCY_5)  || \
+                                   ((LATENCY) == FLASH_LATENCY_6)  || \
+                                   ((LATENCY) == FLASH_LATENCY_7)  || \
+                                   ((LATENCY) == FLASH_LATENCY_8)  || \
+                                   ((LATENCY) == FLASH_LATENCY_9)  || \
+                                   ((LATENCY) == FLASH_LATENCY_10) || \
+                                   ((LATENCY) == FLASH_LATENCY_11) || \
+                                   ((LATENCY) == FLASH_LATENCY_12) || \
+                                   ((LATENCY) == FLASH_LATENCY_13) || \
+                                   ((LATENCY) == FLASH_LATENCY_14) || \
+                                   ((LATENCY) == FLASH_LATENCY_15))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
+                                   (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+
+#if (FLASH_SECTOR_TOTAL == 8)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
+
+#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* FLASH_SECTOR_TOTAL == 8 */
+
+#if (FLASH_SECTOR_TOTAL == 24)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\
+                                 ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\
+                                 ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15)  ||\
+                                 ((SECTOR) == FLASH_SECTOR_16)  || ((SECTOR) == FLASH_SECTOR_17)  ||\
+                                 ((SECTOR) == FLASH_SECTOR_18)  || ((SECTOR) == FLASH_SECTOR_19)  ||\
+                                 ((SECTOR) == FLASH_SECTOR_20)  || ((SECTOR) == FLASH_SECTOR_21)  ||\
+                                 ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))
+
+#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* FLASH_SECTOR_TOTAL == 24 */
+
+#if (FLASH_SECTOR_TOTAL == 4)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3))
+
+#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & 0xFFF0FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* FLASH_SECTOR_TOTAL == 4 */
+
+#if (FLASH_SECTOR_TOTAL == 2)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1))
+
+#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & 0xFFFCFFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* FLASH_SECTOR_TOTAL == 2 */
+
+#if defined (FLASH_OPTCR_nDBANK)
+#define IS_OB_NDBANK(VALUE)        (((VALUE) == OB_NDBANK_SINGLE_BANK) || \
+                                    ((VALUE) == OB_NDBANK_DUAL_BANK))
+
+#define IS_FLASH_BANK(BANK)        (((BANK) == FLASH_BANK_1)  || \
+                                    ((BANK) == FLASH_BANK_2)  || \
+                                    ((BANK) == FLASH_BANK_BOTH))
+#endif /* FLASH_OPTCR_nDBANK */
+
+#if defined (FLASH_OPTCR_nDBOOT)
+#define IS_OB_NDBOOT(VALUE)        (((VALUE) == OB_DUAL_BOOT_DISABLE) || \
+                                    ((VALUE) == OB_DUAL_BOOT_ENABLE))
+#endif /* FLASH_OPTCR_nDBOOT */
+
+#if defined (FLASH_OPTCR2_PCROP)
+#define IS_OB_PCROP_SECTOR(SECTOR)   (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U)
+#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \
+                                      ((VALUE) == OB_PCROP_RDP_ENABLE))
+#endif /* FLASH_OPTCR2_PCROP */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
+  * @{
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_FLASH_EX_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h
new file mode 100644
index 0000000..9fc8540
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h
@@ -0,0 +1,323 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_GPIO_H
+#define __STM32F7xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+
+/**
+  * @brief GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins_define */
+
+  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode_define */
+
+  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull_define */
+
+  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed_define */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins.
+                            This parameter can be a value of @ref GPIO_Alternate_function_selection */
+} GPIO_InitTypeDef;
+
+/**
+  * @brief  GPIO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0,
+  GPIO_PIN_SET
+} GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define GPIO pins define
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001U)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002U)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004U)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008U)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010U)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020U)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040U)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080U)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100U)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200U)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400U)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800U)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000U)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000U)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000U)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000U)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFFU)  /* All pins selected */
+
+#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode_define GPIO mode define
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0x00WX00YZ
+  *           - W  : EXTI trigger detection on 3 bits
+  *           - X  : EXTI mode (IT or Event) on 2 bits
+  *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
+  *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
+  * @{
+  */
+#define  GPIO_MODE_INPUT                        MODE_INPUT                                                  /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode    */
+
+#define  GPIO_MODE_ANALOG                       MODE_ANALOG                                                 /*!< Analog Mode  */
+
+#define  GPIO_MODE_IT_RISING                    (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+
+#define  GPIO_MODE_EVT_RISING                   (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                     /*!< External Event Mode with Rising edge trigger detection             */
+#define  GPIO_MODE_EVT_FALLING                  (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                    /*!< External Event Mode with Falling edge trigger detection            */
+#define  GPIO_MODE_EVT_RISING_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Event Mode with Rising/Falling edge trigger detection     */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed_define  GPIO speed define
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW         ((uint32_t)0x00000000U)  /*!< Low speed     */
+#define  GPIO_SPEED_FREQ_MEDIUM      ((uint32_t)0x00000001U)  /*!< Medium speed  */
+#define  GPIO_SPEED_FREQ_HIGH        ((uint32_t)0x00000002U)  /*!< Fast speed    */
+#define  GPIO_SPEED_FREQ_VERY_HIGH   ((uint32_t)0x00000003U)  /*!< High speed    */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_pull_define GPIO pull define
+  * @brief GPIO Pull-Up or Pull-Down Activation
+  * @{
+  */
+#define  GPIO_NOPULL        ((uint32_t)0x00000000U)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        ((uint32_t)0x00000001U)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      ((uint32_t)0x00000002U)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extension module */
+#include "stm32f7xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+#define GPIO_MODE_Pos                           0U
+#define GPIO_MODE                               (0x3UL << GPIO_MODE_Pos)
+#define MODE_INPUT                              (0x0UL << GPIO_MODE_Pos)
+#define MODE_OUTPUT                             (0x1UL << GPIO_MODE_Pos)
+#define MODE_AF                                 (0x2UL << GPIO_MODE_Pos)
+#define MODE_ANALOG                             (0x3UL << GPIO_MODE_Pos)
+#define OUTPUT_TYPE_Pos                         4U
+#define OUTPUT_TYPE                             (0x1UL << OUTPUT_TYPE_Pos)
+#define OUTPUT_PP                               (0x0UL << OUTPUT_TYPE_Pos)
+#define OUTPUT_OD                               (0x1UL << OUTPUT_TYPE_Pos)
+#define EXTI_MODE_Pos                           16U
+#define EXTI_MODE                               (0x3UL << EXTI_MODE_Pos)
+#define EXTI_IT                                 (0x1UL << EXTI_MODE_Pos)
+#define EXTI_EVT                                (0x2UL << EXTI_MODE_Pos)
+#define TRIGGER_MODE_Pos                         20U
+#define TRIGGER_MODE                            (0x7UL << TRIGGER_MODE_Pos)
+#define TRIGGER_RISING                          (0x1UL << TRIGGER_MODE_Pos)
+#define TRIGGER_FALLING                         (0x2UL << TRIGGER_MODE_Pos)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U))
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
+                            ((MODE) == GPIO_MODE_AF_PP)              ||\
+                            ((MODE) == GPIO_MODE_AF_OD)              ||\
+                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
+                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
+                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
+                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                            ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW)  || ((SPEED) == GPIO_SPEED_MEDIUM) || \
+                              ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+                            ((PULL) == GPIO_PULLDOWN))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_GPIO_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h
new file mode 100644
index 0000000..0e2cb48
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h
@@ -0,0 +1,656 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_GPIO_EX_H
+#define __STM32F7xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIOEx GPIOEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
+  * @{
+  */
+/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\
+    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+#define GPIO_AF1_UART5         ((uint8_t)0x01U)  /* UART5 Alternate Function mapping */
+#define GPIO_AF1_I2C4          ((uint8_t)0x01U)  /* I2C4 Alternate Function mapping  */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
+#define GPIO_AF3_LPTIM1        ((uint8_t)0x03U)  /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF3_CEC           ((uint8_t)0x03U)  /* CEC Alternate Function mapping */
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+#define GPIO_AF3_DFSDM1         ((uint8_t)0x03U)  /* DFSDM1 Alternate Function mapping */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
+#define GPIO_AF4_I2C4          ((uint8_t)0x04U)  /* I2C4 Alternate Function mapping */
+#define GPIO_AF4_CEC           ((uint8_t)0x04U)  /* CEC Alternate Function mapping */
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+#define GPIO_AF6_UART4         ((uint8_t)0x06U)   /* UART4 Alternate Function mapping     */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06U)  /* DFSDM1 Alternate Function mapping     */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_UART5         ((uint8_t)0x07U)  /* UART5 Alternate Function mapping      */
+#define GPIO_AF7_SPDIFRX       ((uint8_t)0x07U)  /* SPDIF-RX Alternate Function mapping   */
+#define GPIO_AF7_SPI2          ((uint8_t)0x07U)  /* SPI2 Alternate Function mapping       */
+#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3 Alternate Function mapping       */
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+#define GPIO_AF7_SPI6          ((uint8_t)0x07U)  /* SPI6 Alternate Function mapping       */
+#define GPIO_AF7_DFSDM1         ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping      */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_SPDIFRX       ((uint8_t)0x08U)  /* SPIDIF-RX Alternate Function mapping */
+#define GPIO_AF8_SAI2          ((uint8_t)0x08U)  /* SAI2 Alternate Function mapping   */
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+#define GPIO_AF8_SPI6          ((uint8_t)0x08U)  /* SPI6 Alternate Function mapping   */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping    */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_QUADSPI       ((uint8_t)0x09U)  /* QUADSPI Alternate Function mapping */
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)
+#define GPIO_AF9_LTDC          ((uint8_t)0x09U)  /* LCD-TFT Alternate Function mapping */
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)
+#define GPIO_AF9_FMC           ((uint8_t)0x09U)   /* FMC Alternate Function mapping     */
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+/**
+  * @brief   AF 10 selection
+  */
+#define GPIO_AF10_OTG_FS        ((uint8_t)0xAU)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0xAU)  /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_QUADSPI       ((uint8_t)0xAU)  /* QUADSPI Alternate Function mapping */
+#define GPIO_AF10_SAI2          ((uint8_t)0xAU)  /* SAI2 Alternate Function mapping */
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+#define GPIO_AF10_DFSDM1         ((uint8_t)0x0AU)  /* DFSDM1 Alternate Function mapping  */
+#define GPIO_AF10_SDMMC2         ((uint8_t)0x0AU)  /* SDMMC2 Alternate Function mapping */
+#define GPIO_AF10_LTDC           ((uint8_t)0x0AU)  /* LCD-TFT Alternate Function mapping */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
+#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define GPIO_AF11_CAN3          ((uint8_t)0x0BU)  /* CAN3 Alternate Function mapping     */
+#define GPIO_AF11_SDMMC2        ((uint8_t)0x0BU)  /* SDMMC2 Alternate Function mapping   */
+#define GPIO_AF11_I2C4          ((uint8_t)0x0BU)  /* I2C4 Alternate Function mapping     */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_FMC           ((uint8_t)0xCU)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xCU)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDMMC1        ((uint8_t)0xCU)  /* SDMMC1 Alternate Function mapping                   */
+#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define GPIO_AF12_MDIOS        ((uint8_t)0xCU)  /* SDMMC1 Alternate Function mapping                    */
+#define GPIO_AF12_UART7        ((uint8_t)0xCU)  /* UART7 Alternate Function mapping                     */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
+#if defined (STM32F769xx) || defined (STM32F779xx)
+#define GPIO_AF13_DSI           ((uint8_t)0x0DU)  /* DSI Alternate Function mapping  */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)
+#define GPIO_AF13_LTDC          ((uint8_t)0x0DU)  /* LTDC Alternate Function mapping */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_LTDC          ((uint8_t)0x0EU)  /* LCD-TFT Alternate Function mapping */
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/
+#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F730xx)
+/**
+ * @brief   AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
+#define GPIO_AF3_LPTIM1        ((uint8_t)0x03U)  /* LPTIM1 Alternate Function mapping */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_UART5         ((uint8_t)0x07U)  /* UART5 Alternate Function mapping      */
+#define GPIO_AF7_SPI2          ((uint8_t)0x07U)  /* SPI2 Alternate Function mapping       */
+#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3 Alternate Function mapping       */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_SAI2          ((uint8_t)0x08U)  /* SAI2 Alternate Function mapping   */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_QUADSPI       ((uint8_t)0x09U)  /* QUADSPI Alternate Function mapping */
+
+/**
+  * @brief   AF 10 selection
+  */
+#define GPIO_AF10_OTG_FS        ((uint8_t)0xAU)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0xAU)  /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_QUADSPI       ((uint8_t)0xAU)  /* QUADSPI Alternate Function mapping */
+#define GPIO_AF10_SAI2          ((uint8_t)0xAU)  /* SAI2 Alternate Function mapping */
+#define GPIO_AF10_SDMMC2        ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */
+
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_SDMMC2        ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping   */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_FMC           ((uint8_t)0xCU)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xCU)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDMMC1        ((uint8_t)0xCU)  /* SDMMC1 Alternate Function mapping                   */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_RNG           ((uint8_t)0x0DU)  /* RNG Alternate Function mapping */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+/**
+  * @brief   GPIO pin available on the platform
+  */
+/* Defines the available pins per GPIOs */
+#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOD_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOE_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOF_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOG_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOI_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOH_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
+                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
+  * @{
+  */
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
+  * @{
+  */
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define GPIO_GET_INDEX(__GPIOx__)   (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                              ((__GPIOx__) == (GPIOB))? 1U :\
+                                              ((__GPIOx__) == (GPIOC))? 2U :\
+                                              ((__GPIOx__) == (GPIOD))? 3U :\
+                                              ((__GPIOx__) == (GPIOE))? 4U :\
+                                              ((__GPIOx__) == (GPIOF))? 5U :\
+                                              ((__GPIOx__) == (GPIOG))? 6U :\
+                                              ((__GPIOx__) == (GPIOH))? 7U :\
+                                              ((__GPIOx__) == (GPIOI))? 8U :\
+                                              ((__GPIOx__) == (GPIOJ))? 9U : 10U)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define GPIO_GET_INDEX(__GPIOx__)   (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                              ((__GPIOx__) == (GPIOB))? 1U :\
+                                              ((__GPIOx__) == (GPIOC))? 2U :\
+                                              ((__GPIOx__) == (GPIOD))? 3U :\
+                                              ((__GPIOx__) == (GPIOE))? 4U :\
+                                              ((__GPIOx__) == (GPIOF))? 5U :\
+                                              ((__GPIOx__) == (GPIOG))? 6U :\
+                                              ((__GPIOx__) == (GPIOH))? 7U : 8U)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
+/**
+  * @}
+  */
+
+#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__)  \
+           ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
+            (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
+            (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
+            (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
+            (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
+            (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \
+			(((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \
+			(((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \
+			(((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \
+			(((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \
+			(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
+  * @{
+  */
+#if defined(STM32F756xx) || defined(STM32F746xx)  || defined(STM32F750xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)       || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
+                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
+                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
+                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
+                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
+                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \
+                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \
+                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
+                          ((AF) == GPIO_AF9_LTDC)       || ((AF) == GPIO_AF10_OTG_FS)    || \
+                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
+                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
+                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)    || \
+                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT)  || \
+                          ((AF) == GPIO_AF13_DCMI)      || ((AF) == GPIO_AF14_LTDC))
+#elif defined(STM32F745xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)       || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)        || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
+                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
+                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
+                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
+                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
+                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \
+                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \
+                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
+                          ((AF) == GPIO_AF13_DCMI)      || ((AF) == GPIO_AF10_OTG_FS)    || \
+                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
+                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
+                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)    || \
+                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT))
+#elif defined(STM32F767xx) || defined(STM32F777xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)       || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
+                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
+                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
+                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
+                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
+                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \
+                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \
+                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF9_LTDC)       || \
+                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
+                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
+                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \
+                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF14_LTDC))
+#elif defined(STM32F769xx) || defined(STM32F779xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)       || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
+                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
+                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
+                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
+                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
+                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \
+                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \
+                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
+                          ((AF) == GPIO_AF9_LTDC)       || ((AF) == GPIO_AF10_OTG_FS)    || \
+                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
+                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
+                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \
+                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF14_LTDC)      || ((AF) == GPIO_AF13_DSI))
+#elif defined(STM32F765xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)       || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
+                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
+                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \
+                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
+                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
+                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \
+                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \
+                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \
+                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \
+                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \
+                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \
+                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF10_OTG_FS))
+#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)       || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \
+                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF5_SPI3)       || \
+                          ((AF) == GPIO_AF5_SPI4)       || ((AF) == GPIO_AF5_SPI5)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \
+                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \
+                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF9_TIM13)      || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF9_QUADSPI)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF10_SAI2)      || ((AF) == GPIO_AF10_QUADSPI)   || \
+                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \
+                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)    || \
+                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT)  || \
+                          ((AF) == GPIO_AF10_OTG_FS))
+#endif /* STM32F756xx || STM32F746xx || STM32F750xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_GPIO_EX_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h
new file mode 100644
index 0000000..6239a9f
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h
@@ -0,0 +1,838 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_HAL_I2C_H
+#define STM32F7xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                     This parameter calculated by referring to I2C initialization section
+                                     in Reference manual */
+
+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
+                                     This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                     This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+
+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
+                                     This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+
+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
+                                     This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing
+                                     mode is selected.
+                                     This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+
+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
+                                     This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+
+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
+                                     This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+
+} I2C_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :\n
+  *          b7-b6  Error information\n
+  *             00 : No Error\n
+  *             01 : Abort (Abort user request on going)\n
+  *             10 : Timeout\n
+  *             11 : Error\n
+  *          b5     Peripheral initialization status\n
+  *             0  : Reset (peripheral not initialized)\n
+  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
+  *          b4     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b3\n
+  *             0  : Ready or Busy (No Listen mode ongoing)\n
+  *             1  : Listen (peripheral in Address Listen Mode)\n
+  *          b2     Intrinsic process state\n
+  *             0  : Ready\n
+  *             1  : Busy (peripheral busy with some configuration or internal operations)\n
+  *          b1     Rx state\n
+  *             0  : Ready (no Rx operation ongoing)\n
+  *             1  : Busy (Rx operation ongoing)\n
+  *          b0     Tx state\n
+  *             0  : Ready (no Tx operation ongoing)\n
+  *             1  : Busy (Tx operation ongoing)
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition
+  * @{
+  */
+typedef struct __I2C_HandleTypeDef
+{
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                         */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
+
+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
+                                                  be a value of @ref I2C_XFEROPTIONS */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
+
+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+  /*!< I2C transfer IRQ handler function pointer */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
+
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
+
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
+
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
+
+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
+
+  __IO uint32_t              Devaddress;     /*!< I2C Target device address                 */
+
+  __IO uint32_t              Memaddress;     /*!< I2C Target memory address                 */
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Abort callback                        */
+
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+  /*!< I2C Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Msp DeInit callback                   */
+
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL I2C Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
+
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2C Callback pointer definition
+  */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
+/*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
+                                          uint16_t AddrMatchCode);
+/*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
+  * @{
+  */
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  I2C_OTHER_FRAME                (0x000000AAU)
+#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
+  * @{
+  */
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
+  * @{
+  */
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
+  * @{
+  */
+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
+#define  I2C_SOFTEND_MODE               (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
+  * @{
+  */
+#define  I2C_NO_STARTSTOP               (0x00000000U)
+#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */
+#define I2C_FLAG_TXE                    I2C_ISR_TXE
+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
+#define I2C_FLAG_AF                     I2C_ISR_NACKF
+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
+#define I2C_FLAG_TC                     I2C_ISR_TC
+#define I2C_FLAG_TCR                    I2C_ISR_TCR
+#define I2C_FLAG_BERR                   I2C_ISR_BERR
+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
+#define I2C_FLAG_OVR                    I2C_ISR_OVR
+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
+#define I2C_FLAG_DIR                    I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                             \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;  \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;       \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                                  } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/** @brief  Enable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified I2C interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & \
+                                                                   (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *            @arg @ref I2C_FLAG_BUSY    Bus busy
+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define I2C_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
+                                                    (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
+                                                    ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
+                                                    ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                         (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                        (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+/**
+  * @}
+  */
+
+/* Include I2C HAL Extended module */
+#include "stm32f7xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+                                           pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                          uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                         uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                         uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                        uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                   uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+                                        uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                            uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                      uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                               uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                              uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                  uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                 uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+  * @{
+  */
+
+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
+                                         ((MASK) == I2C_OA2_MASK01) || \
+                                         ((MASK) == I2C_OA2_MASK02) || \
+                                         ((MASK) == I2C_OA2_MASK03) || \
+                                         ((MASK) == I2C_OA2_MASK04) || \
+                                         ((MASK) == I2C_OA2_MASK05) || \
+                                         ((MASK) == I2C_OA2_MASK06) || \
+                                         ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                         ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
+                                         ((MODE) == I2C_AUTOEND_MODE) || \
+                                         ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+                                         ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
+                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
+                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= \
+                                                   (uint32_t)~((uint32_t)(I2C_CR2_SADD   | I2C_CR2_HEAD10R | \
+                                                                          I2C_CR2_NBYTES | I2C_CR2_RELOAD  | \
+                                                                          I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
+                                                              >> 16U))
+#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
+                                                             >> 16U))
+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
+                                                                         (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
+                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+                                                                 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+                                                                (~I2C_CR2_RD_WRN)) : \
+                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+                                                                 (I2C_CR2_ADD10) | (I2C_CR2_START) | \
+                                                                 (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
+                                                    ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32f7xx_hal_i2c.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32F7xx_HAL_I2C_H */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h
new file mode 100644
index 0000000..27bdcf0
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h
@@ -0,0 +1,212 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_HAL_I2C_EX_H
+#define STM32F7xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+  * @{
+  */
+#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
+#if defined(SYSCFG_PMC_I2C_PB6_FMP)
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_PMC_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_PMC_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
+#else
+#define I2C_FASTMODEPLUS_PB6            (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported   */
+#define I2C_FASTMODEPLUS_PB7            (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported   */
+#endif /* SYSCFG_PMC_I2C_PB6_FMP */
+#if defined(SYSCFG_PMC_I2C_PB8_FMP)
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_PMC_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_PMC_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
+#else
+#define I2C_FASTMODEPLUS_PB8            (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported   */
+#define I2C_FASTMODEPLUS_PB9            (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported   */
+#endif /* SYSCFG_PMC_I2C_PB8_FMP */
+#if defined(SYSCFG_PMC_I2C1_FMP)
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_PMC_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C1           (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported  */
+#endif /* SYSCFG_PMC_I2C1_FMP */
+#if defined(SYSCFG_PMC_I2C2_FMP)
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_PMC_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C2           (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported  */
+#endif /* SYSCFG_PMC_I2C2_FMP */
+#if defined(SYSCFG_PMC_I2C3_FMP)
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_PMC_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C3           (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported  */
+#endif /* SYSCFG_PMC_I2C3_FMP */
+#if defined(SYSCFG_PMC_I2C4_FMP)
+#define I2C_FASTMODEPLUS_I2C4           SYSCFG_PMC_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C4           (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported  */
+#endif /* SYSCFG_PMC_I2C4_FMP */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+/**
+  * @}
+  */
+#if  (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP)
+
+/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @{
+  */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+  * @}
+  */
+#endif /* Fast Mode Plus Availability */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                         ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+
+#if defined(SYSCFG_PMC_I2C4_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
+#elif defined(SYSCFG_PMC_I2C3_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
+#elif defined(SYSCFG_PMC_I2C2_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
+#elif defined(SYSCFG_PMC_I2C1_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
+#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F7xx_HAL_I2C_EX_H */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h
new file mode 100644
index 0000000..736ff6f
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h
@@ -0,0 +1,402 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_PWR_H
+#define __STM32F7xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+   
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
+                            This parameter can be a value of @ref PWR_PVD_detection_level */
+
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWR_PVD_Mode */
+}PWR_PVDTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+  * @{
+  */ 
+#define PWR_PVDLEVEL_0                  PWR_CR1_PLS_LEV0
+#define PWR_PVDLEVEL_1                  PWR_CR1_PLS_LEV1
+#define PWR_PVDLEVEL_2                  PWR_CR1_PLS_LEV2
+#define PWR_PVDLEVEL_3                  PWR_CR1_PLS_LEV3
+#define PWR_PVDLEVEL_4                  PWR_CR1_PLS_LEV4
+#define PWR_PVDLEVEL_5                  PWR_CR1_PLS_LEV5
+#define PWR_PVDLEVEL_6                  PWR_CR1_PLS_LEV6
+#define PWR_PVDLEVEL_7                  PWR_CR1_PLS_LEV7/* External input analog voltage 
+                                                          (Compare internally to VREFINT) */
+
+/**
+  * @}
+  */   
+ 
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000U)   /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001U)   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002U)   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000U)
+#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR1_LPDS
+/**
+  * @}
+  */
+    
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01U)
+#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI               ((uint8_t)0x01U)
+#define PWR_STOPENTRY_WFE               ((uint8_t)0x02U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
+  * @{
+  */
+#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR1_VOS
+#define PWR_REGULATOR_VOLTAGE_SCALE2         PWR_CR1_VOS_1
+#define PWR_REGULATOR_VOLTAGE_SCALE3         PWR_CR1_VOS_0
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag PWR Flag
+  * @{
+  */
+#define PWR_FLAG_WU                     PWR_CSR1_WUIF
+#define PWR_FLAG_SB                     PWR_CSR1_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR1_PVDO
+#define PWR_FLAG_BRR                    PWR_CSR1_BRR
+#define PWR_FLAG_VOSRDY                 PWR_CSR1_VOSRDY
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+  * @{
+  */
+
+/** @brief  macros configure the main internal regulator output voltage.
+  * @param  __REGULATOR__ specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption when the device does
+  *         not operate at the maximum frequency (refer to the datasheets for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+  * @retval None
+  */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
+                                                            __IO uint32_t tmpreg;                               \
+                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
+                                                            /* Delay after an RCC peripheral clock enabling */  \
+                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
+                                                            UNUSED(tmpreg);                                     \
+				                                                	} while(0)
+
+/** @brief  Check PWR flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
+  *                  was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B),
+  *                  RTC Tamper event, RTC TimeStamp event or RTC Wakeup)).
+  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+  *                  resumed from StandBy mode.    
+  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
+  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 
+  *                  For this reason, this bit is equal to 0 after Standby or reset
+  *                  until the PVDE bit is set.
+  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 
+  *                  when the device wakes up from Standby mode or by a system reset 
+  *                  or power reset.  
+  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage 
+  *                 scaling output selection is ready.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the PWR's pending flags.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_SB: StandBy flag
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |=  (__FLAG__) << 2)
+
+/**
+  * @brief Enable the PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Disable the PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Enable event on PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Disable event on PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Enable the PVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief Disable the PVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+  * @brief checks whether the specified PVD Exti interrupt flag is set or not.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR & (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Clear the PVD Exti flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief  Generates a Software interrupt on PVD EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
+
+/**
+  * @}
+  */
+
+/* Include PWR HAL Extension module */
+#include "stm32f7xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+  
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+/* PVD configuration */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes entry */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+/* Power PVD IRQ Handler */
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+
+/* Cortex System Control functions  *******************************************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD  ((uint32_t)EXTI_IMR_IM16)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+  * @{
+  */
+
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
+  * @{
+  */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
+                              ((MODE) == PWR_PVD_MODE_NORMAL))
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F7xx_HAL_PWR_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h
new file mode 100644
index 0000000..e4a5995
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h
@@ -0,0 +1,260 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_PWR_EX_H
+#define __STM32F7xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+  * @{
+  */
+/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins
+  * @{
+  */
+#define PWR_WAKEUP_PIN1                PWR_CSR2_EWUP1
+#define PWR_WAKEUP_PIN2                PWR_CSR2_EWUP2
+#define PWR_WAKEUP_PIN3                PWR_CSR2_EWUP3
+#define PWR_WAKEUP_PIN4                PWR_CSR2_EWUP4
+#define PWR_WAKEUP_PIN5                PWR_CSR2_EWUP5
+#define PWR_WAKEUP_PIN6                PWR_CSR2_EWUP6
+#define PWR_WAKEUP_PIN1_HIGH           PWR_CSR2_EWUP1
+#define PWR_WAKEUP_PIN2_HIGH           PWR_CSR2_EWUP2
+#define PWR_WAKEUP_PIN3_HIGH           PWR_CSR2_EWUP3
+#define PWR_WAKEUP_PIN4_HIGH           PWR_CSR2_EWUP4
+#define PWR_WAKEUP_PIN5_HIGH           PWR_CSR2_EWUP5
+#define PWR_WAKEUP_PIN6_HIGH           PWR_CSR2_EWUP6
+#define PWR_WAKEUP_PIN1_LOW            (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)
+#define PWR_WAKEUP_PIN2_LOW            (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)
+#define PWR_WAKEUP_PIN3_LOW            (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)
+#define PWR_WAKEUP_PIN4_LOW            (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)
+#define PWR_WAKEUP_PIN5_LOW            (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)
+#define PWR_WAKEUP_PIN6_LOW            (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)
+
+/**
+  * @}
+  */
+	
+/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_UNDERDRIVE_ON                       PWR_CR1_MRUDS
+#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON                   ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
+  * @{
+  */
+#define PWR_FLAG_ODRDY                  PWR_CSR1_ODRDY
+#define PWR_FLAG_ODSWRDY                PWR_CSR1_ODSWRDY
+#define PWR_FLAG_UDRDY                  PWR_CSR1_UDRDY
+/**
+  * @}
+  */
+	
+/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags
+  * @{
+  */
+#define PWR_WAKEUP_PIN_FLAG1            PWR_CSR2_WUPF1
+#define PWR_WAKEUP_PIN_FLAG2            PWR_CSR2_WUPF2
+#define PWR_WAKEUP_PIN_FLAG3            PWR_CSR2_WUPF3
+#define PWR_WAKEUP_PIN_FLAG4            PWR_CSR2_WUPF4
+#define PWR_WAKEUP_PIN_FLAG5            PWR_CSR2_WUPF5
+#define PWR_WAKEUP_PIN_FLAG6            PWR_CSR2_WUPF6
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
+  *  @{
+  */
+/** @brief Macros to enable or disable the Over drive mode.
+  */
+#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)
+#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))
+
+/** @brief Macros to enable or disable the Over drive switching.
+  */
+#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)
+#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))
+
+/** @brief Macros to enable or disable the Under drive mode.
+  * @note  This mode is enabled only with STOP low power mode.
+  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+  *        mode is only available when the main regulator or the low power regulator 
+  *        is in low voltage mode.      
+  * @note  If the Under-drive mode was enabled, it is automatically disabled after 
+  *        exiting Stop mode. 
+  *        When the voltage regulator operates in Under-drive mode, an additional  
+  *        startup delay is induced when waking up from Stop mode.
+  */
+#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)
+#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))
+
+/** @brief  Check PWR flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
+  *                                 is ready 
+  *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
+  *                                   switching is ready  
+  *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
+  *                                 is enabled in Stop mode
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the Under-Drive Ready flag.
+  */
+#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= (PWR_FLAG_UDRDY | PWR_CSR1_EIWUP))
+
+/** @brief  Check Wake Up flag is set or not.
+  * @param  __WUFLAG__ specifies the Wake Up flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
+  *            @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
+  *            @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
+  *            @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
+  *            @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
+  *            @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11          
+  */
+#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))
+
+/** @brief  Clear the WakeUp pins flags.
+  * @param  __WUFLAG__ specifies the Wake Up pin flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
+  *            @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
+  *            @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
+  *            @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
+  *            @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
+  *            @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11          
+  */
+#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |=  (__WUFLAG__))
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+  *  @{
+  */
+ 
+/** @addtogroup PWREx_Exported_Functions_Group1
+  * @{
+  */
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void); 
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); 
+
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
+
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+  * @{
+  */
+
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+  * @{
+  */
+#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
+                                                ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
+#define IS_PWR_WAKEUP_PIN(__PIN__)         (((__PIN__) == PWR_WAKEUP_PIN1)       || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN2)       || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN3)       || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN4)       || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN5)       || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN6)  		 || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN1_HIGH)  || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN2_HIGH)  || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN3_HIGH)  || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN4_HIGH)  || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN5_HIGH)  || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN6_HIGH)  || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN1_LOW)   || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN2_LOW)   || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN3_LOW)   || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN4_LOW)   || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN5_LOW)	 || \
+                                            ((__PIN__) == PWR_WAKEUP_PIN6_LOW))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F7xx_HAL_PWR_EX_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h
new file mode 100644
index 0000000..f3309a3
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h
@@ -0,0 +1,1307 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_RCC_H
+#define __STM32F7xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+   
+/* Include RCC HAL Extended module */
+/* (include on top of file since RCC structures are defined in extended file) */
+#include "stm32f7xx_hal_rcc_ex.h"   
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition  
+  */
+typedef struct
+{
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
+
+  uint32_t HSEState;             /*!< The new state of the HSE.
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */
+
+  uint32_t LSEState;             /*!< The new state of the LSE.
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */
+                                          
+  uint32_t HSIState;             /*!< The new state of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */
+
+  uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+                               
+  uint32_t LSIState;             /*!< The new state of the LSI.
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */
+
+  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */      
+
+}RCC_OscInitTypeDef;
+
+/**
+  * @brief  RCC System, AHB and APB buses clock configuration structure definition  
+  */
+typedef struct
+{
+  uint32_t ClockType;             /*!< The clock to be configured.
+                                       This parameter can be a value of @ref RCC_System_Clock_Type */
+  
+  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
+                                       This parameter can be a value of @ref RCC_System_Clock_Source    */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+}RCC_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+  * @{
+  */
+#define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000U)
+#define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001U)
+#define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002U)
+#define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004U)
+#define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Config RCC HSE Config
+  * @{
+  */
+#define RCC_HSE_OFF                      ((uint32_t)0x00000000U)
+#define RCC_HSE_ON                       RCC_CR_HSEON
+#define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Config RCC LSE Config
+  * @{
+  */
+#define RCC_LSE_OFF                    ((uint32_t)0x00000000U)
+#define RCC_LSE_ON                     RCC_BDCR_LSEON
+#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Config RCC HSI Config
+  * @{
+  */
+#define RCC_HSI_OFF                    ((uint32_t)0x00000000U)
+#define RCC_HSI_ON                     RCC_CR_HSION
+
+#define RCC_HSICALIBRATION_DEFAULT     ((uint32_t)0x10U)         /* Default HSI calibration trimming value */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Config RCC LSI Config
+  * @{
+  */
+#define RCC_LSI_OFF                    ((uint32_t)0x00000000U)
+#define RCC_LSI_ON                     RCC_CSR_LSION
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Config RCC PLL Config
+  * @{
+  */
+#define RCC_PLL_NONE                   ((uint32_t)0x00000000U)
+#define RCC_PLL_OFF                    ((uint32_t)0x00000001U)
+#define RCC_PLL_ON                     ((uint32_t)0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
+  * @{
+  */
+#define RCC_PLLP_DIV2                  ((uint32_t)0x00000002U)
+#define RCC_PLLP_DIV4                  ((uint32_t)0x00000004U)
+#define RCC_PLLP_DIV6                  ((uint32_t)0x00000006U)
+#define RCC_PLLP_DIV8                  ((uint32_t)0x00000008U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
+  * @{
+  */
+#define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI
+#define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Type RCC System Clock Type
+  * @{
+  */
+#define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001U)
+#define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002U)
+#define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004U)
+#define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008U)
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_System_Clock_Source RCC System Clock Source
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
+  * @{
+  */
+#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
+  * @{
+  */
+#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1
+#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2
+#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4
+#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8
+#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
+  * @{
+  */
+#define RCC_RTCCLKSOURCE_NO_CLK          ((uint32_t)0x00000000U)
+#define RCC_RTCCLKSOURCE_LSE             ((uint32_t)0x00000100U)
+#define RCC_RTCCLKSOURCE_LSI             ((uint32_t)0x00000200U)
+#define RCC_RTCCLKSOURCE_HSE_DIVX        ((uint32_t)0x00000300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV2        ((uint32_t)0x00020300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV3        ((uint32_t)0x00030300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)0x00040300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV5        ((uint32_t)0x00050300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV6        ((uint32_t)0x00060300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV7        ((uint32_t)0x00070300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)0x00080300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV9        ((uint32_t)0x00090300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV10       ((uint32_t)0x000A0300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV11       ((uint32_t)0x000B0300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV12       ((uint32_t)0x000C0300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV13       ((uint32_t)0x000D0300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV14       ((uint32_t)0x000E0300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV15       ((uint32_t)0x000F0300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)0x00100300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV17       ((uint32_t)0x00110300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV18       ((uint32_t)0x00120300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV19       ((uint32_t)0x00130300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV20       ((uint32_t)0x00140300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV21       ((uint32_t)0x00150300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV22       ((uint32_t)0x00160300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV23       ((uint32_t)0x00170300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV24       ((uint32_t)0x00180300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV25       ((uint32_t)0x00190300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV26       ((uint32_t)0x001A0300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV27       ((uint32_t)0x001B0300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV28       ((uint32_t)0x001C0300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV29       ((uint32_t)0x001D0300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV30       ((uint32_t)0x001E0300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV31       ((uint32_t)0x001F0300U)
+/**
+  * @}
+  */
+
+
+
+/** @defgroup RCC_MCO_Index RCC MCO Index
+  * @{
+  */
+#define RCC_MCO1                         ((uint32_t)0x00000000U)
+#define RCC_MCO2                         ((uint32_t)0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
+  * @{
+  */
+#define RCC_MCO1SOURCE_HSI               ((uint32_t)0x00000000U)
+#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
+#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
+#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
+  * @{
+  */
+#define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000U)
+#define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
+  * @{
+  */
+#define RCC_MCODIV_1                    ((uint32_t)0x00000000U)
+#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2
+#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt RCC Interrupt 
+  * @{
+  */
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01U)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02U)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04U)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08U)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10U)
+#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20U)
+#define RCC_IT_PLLSAIRDY                 ((uint8_t)0x40U)
+#define RCC_IT_CSS                       ((uint8_t)0x80U)
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_Flag RCC Flags
+  *        Elements values convention: 0XXYYYYYb
+  *           - YYYYY  : Flag position in the register
+  *           - 0XX  : Register index
+  *                 - 01: CR register
+  *                 - 10: BDCR register
+  *                 - 11: CSR register
+  * @{
+  */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21U)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31U)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39U)
+#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3BU)
+#define RCC_FLAG_PLLSAIRDY               ((uint8_t)0x3CU)
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41U)
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61U)
+#define RCC_FLAG_BORRST                  ((uint8_t)0x79U)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7AU)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7BU)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7CU)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7DU)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7EU)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7FU)
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
+  * @{
+  */
+#define RCC_LSEDRIVE_LOW                 ((uint32_t)0x00000000U)
+#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_1
+#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_0
+#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+   
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.   
+  * @{
+  */
+#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+									  
+#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+									  
+#define __HAL_RCC_PWR_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)									  
+
+#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable                                      
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+									  
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)  
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
+
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable  Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
+
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+/**
+  * @}
+  */  
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  EGet the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
+/**
+  * @}
+  */  
+  
+/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
+  * @brief  Force or release AHB peripheral reset.
+  * @{
+  */  
+#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+
+#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
+#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)  
+#define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U) 
+#define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)  
+#define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
+
+/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
+
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
+
+/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
+
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
+
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
+
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
+/**
+  * @}
+  */  
+
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+  * @{   
+  */ 
+                                      
+/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after startup
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).             
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.  
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.  
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.  
+  */
+#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
+#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
+
+/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value.
+  *         (default is RCC_HSICALIBRATION_DEFAULT).
+  */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
+        RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Configuration LSI Configuration
+  * @{   
+  */ 
+
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on 
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles. 
+  */
+#define __HAL_RCC_LSI_ENABLE()  (RCC->CSR |= (RCC_CSR_LSION))
+#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Configuration HSE Configuration
+  * @{   
+  */ 
+/**
+  * @brief  Macro to configure the External High Speed oscillator (HSE).
+  * @note   Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this macro. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  __STATE__ specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
+  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+  */
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \
+                    do {                                        \
+                      if ((__STATE__) == RCC_HSE_ON)            \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_OFF)      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_BYPASS)   \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else                                      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                    } while(0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+  * @{   
+  */
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE).
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 
+  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.  
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using 
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).  
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @param  __STATE__ specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
+  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
+  */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+                    do {                                       \
+                      if((__STATE__) == RCC_LSE_ON)            \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_OFF)      \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_BYPASS)   \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else                                     \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                    } while(0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
+  * @{   
+  */
+
+/** @brief  Macros to enable or disable the RTC clock.
+  * @note   These macros must be used only after the RTC clock source was selected.
+  */
+#define __HAL_RCC_RTC_ENABLE()  (RCC->BDCR |= (RCC_BDCR_RTCEN))
+#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
+
+/** @brief  Macros to configure the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using the Power Backup Access macro before to configure
+  *         the RTC clock source (to be done once after reset).    
+  * @note   Once the RTC clock is configured it can't be changed unless the  
+  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+  *         a Power On Reset (POR).
+  * @param  __RTCCLKSource__ specifies the RTC clock source.
+  *         This parameter can be one of the following values:
+               @arg @ref RCC_RTCCLKSOURCE_NO_CLK:  No clock selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
+  *                                                 as RTC clock, where x:[2,31]
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.    
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
+                                                     MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+                                                   
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
+                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF);  \
+                                                  } while (0)
+
+/** @brief Macro to get the RTC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
+  */
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/**
+  * @brief   Get the RTC and HSE clock divider (RTCPRE).
+  * @retval Returned value can be one of the following values:
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
+  *                                                 as RTC clock, where x:[2,31]
+  */
+#define  __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
+
+/** @brief  Macros to force or release the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_CSR register.
+  * @note   The BKPSRAM is not affected by this reset.   
+  */
+#define __HAL_RCC_BACKUPRESET_FORCE()   (RCC->BDCR |= (RCC_BDCR_BDRST))
+#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+  * @{   
+  */
+
+/** @brief  Macros to enable or disable the main PLL.
+  * @note   After enabling the main PLL, the application software should wait on 
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The main PLL can not be disabled if it is used as system clock source
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
+#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
+                            
+/** @brief  Macro to configure the PLL clock source.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  *      
+  */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
+
+/** @brief  Macro to configure the PLL multiplication factor.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLL jitter.
+  *      
+  */
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
+  * @{   
+  */
+
+/** @brief  Macro to configure the I2S clock source (I2SCLK).
+  * @note   This function must be called before enabling the I2S APB clock.
+  * @param  __SOURCE__ specifies the I2S clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+  *                                       used as I2S clock source.
+  */
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
+                                             RCC->CFGR |= (__SOURCE__);       \
+                                            }while(0)
+
+/** @brief Macros to enable or disable the PLLI2S. 
+  * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
+#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Get_Clock_source Get Clock source
+  * @{   
+  */
+/**
+  * @brief Macro to configure the system clock source.
+  * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
+  * This parameter can be one of the following values:
+  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+  */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
+/** @brief  Macro to get the clock source used as system clock.
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following:
+  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
+  */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
+
+/**
+  * @brief  Macro to configures the External Low Speed oscillator (LSE) drive capability.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @param  __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
+  *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
+  *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
+  *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
+  * @retval None
+  */
+#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
+                  (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
+
+/** @brief  Macro to get the oscillator used as PLL clock source.
+  * @retval The oscillator used as PLL clock source. The returned value can be one
+  *         of the following:
+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+  * @{   
+  */ 
+  
+/** @brief  Macro to configure the MCO1 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  */
+
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+        MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+                
+/** @brief  Macro to configure the MCO2 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source 
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  */
+
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+        MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+
+/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
+  *         the selected interrupts).
+  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 
+  *        the selected interrupts).
+  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
+
+/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
+  *         bits to clear the selected interrupt pending bits.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.  
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
+  */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+
+/** @brief  Check the RCC's interrupt has occurred or not.
+  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, 
+  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+  */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
+  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
+  *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
+  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
+  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
+  *            @arg RCC_FLAG_PINRST: Pin reset.
+  *            @arg RCC_FLAG_PORRST: POR/PDR reset.
+  *            @arg RCC_FLAG_SFTRST: Software reset.
+  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
+  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
+  *            @arg RCC_FLAG_LPWRRST: Low Power reset.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
+
+/**
+  * @}
+  */
+     
+/**
+  * @}
+  */
+
+/* Include RCC HAL Extension module */
+#include "stm32f7xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+ /** @addtogroup RCC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+  * @{
+  */                             
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void     HAL_RCC_EnableCSS(void);
+void     HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+
+/* User Callbacks in non blocking mode (IT mode) */ 
+void HAL_RCC_CSSCallback(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+  * @{
+  */
+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE          ((uint32_t)2)    /* 2 ms */
+#define LSI_TIMEOUT_VALUE          ((uint32_t)2)    /* 2 ms */
+#define PLL_TIMEOUT_VALUE          ((uint32_t)2)    /* 2 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s */
+#define PLLI2S_TIMEOUT_VALUE       100U             /* Timeout value fixed to 100 ms */
+#define PLLSAI_TIMEOUT_VALUE       100U             /* Timeout value fixed to 100 ms */
+
+/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
+  * @brief RCC registers bit address alias
+  * @{
+  */
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x01))
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x02))
+
+#define RCC_DBP_TIMEOUT_VALUE      ((uint32_t)100)
+#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+    
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */  
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS))
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS))
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
+
+#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
+
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
+                                  ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
+                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
+                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \
+                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
+                           ((HCLK) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
+
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
+                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
+                           ((PCLK) == RCC_HCLK_DIV16))
+
+#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
+
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
+                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
+                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
+                             ((DIV) == RCC_MCODIV_5)) 
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
+
+
+#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW)        || \
+                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW)  || \
+                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
+                                 ((DRIVE) == RCC_LSEDRIVE_HIGH))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_RCC_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h
new file mode 100644
index 0000000..558a743
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h
@@ -0,0 +1,3555 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_rcc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_RCC_EX_H
+#define __STM32F7xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC PLL configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PLLState;   /*!< The new state of the PLL.
+                            This parameter can be a value of @ref RCC_PLL_Config                      */
+
+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
+
+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 63    */
+
+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432  */
+
+  uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).
+                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
+
+  uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15    */
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+  uint32_t PLLR;       /*!< PLLR: Division factor for DSI clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7    */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+}RCC_PLLInitTypeDef;
+
+/**
+  * @brief  PLLI2S Clock structure definition
+  */
+typedef struct
+{
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
+    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+  uint32_t PLLI2SP;    /*!< Specifies the division factor for SPDIF-RX clock.
+                            This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
+                            This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+}RCC_PLLI2SInitTypeDef;
+
+/**
+  * @brief  PLLSAI Clock structure definition
+  */
+typedef struct
+{
+  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+
+  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
+    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+  uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+                            This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+  uint32_t PLLSAIP;    /*!< Specifies the division factor for 48MHz clock.
+                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
+                            This parameter will be used only when PLLSAI is disabled */
+}RCC_PLLSAIInitTypeDef;
+
+/**
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters.
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+  uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.
+                                      This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock source Selection.
+                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+  uint32_t I2sClockSelection;      /*!< Specifies I2S Clock source Selection.
+                                        This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+  uint32_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection.
+                                       This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
+
+  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 Clock Prescalers Selection
+                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
+
+  uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 Clock Prescalers Selection
+                                        This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
+
+  uint32_t Usart1ClockSelection; /*!< USART1 clock source
+                                      This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+  uint32_t Usart2ClockSelection; /*!< USART2 clock source
+                                      This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
+
+  uint32_t Usart3ClockSelection; /*!< USART3 clock source
+                                      This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
+
+  uint32_t Uart4ClockSelection;  /*!< UART4 clock source
+                                      This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+  uint32_t Uart5ClockSelection;  /*!< UART5 clock source
+                                      This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+  uint32_t Usart6ClockSelection;  /*!< USART6 clock source
+                                      This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
+
+  uint32_t Uart7ClockSelection;  /*!< UART7 clock source
+                                      This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
+
+  uint32_t Uart8ClockSelection;  /*!< UART8 clock source
+                                      This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
+
+  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
+                                      This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
+
+  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
+                                      This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
+                                      This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+  uint32_t I2c4ClockSelection;   /*!< I2C4 clock source
+                                      This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
+
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source
+                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
+
+  uint32_t CecClockSelection;      /*!< CEC clock source
+                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+  uint32_t Clk48ClockSelection;    /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
+                                        This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+
+  uint32_t Sdmmc1ClockSelection;     /*!< SDMMC1 clock source
+                                        This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+  uint32_t Sdmmc2ClockSelection;     /*!< SDMMC2 clock source
+                                        This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+  uint32_t Dfsdm1ClockSelection;     /*!< DFSDM1 clock source
+                                        This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
+
+  uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source
+                                        This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+}RCC_PeriphCLKInitTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
+  * @{
+  */
+#define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008U)
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010U)
+#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)
+#define RCC_PERIPHCLK_USART1          ((uint32_t)0x00000040U)
+#define RCC_PERIPHCLK_USART2          ((uint32_t)0x00000080U)
+#define RCC_PERIPHCLK_USART3          ((uint32_t)0x00000100U)
+#define RCC_PERIPHCLK_UART4           ((uint32_t)0x00000200U)
+#define RCC_PERIPHCLK_UART5           ((uint32_t)0x00000400U)
+#define RCC_PERIPHCLK_USART6          ((uint32_t)0x00000800U)
+#define RCC_PERIPHCLK_UART7           ((uint32_t)0x00001000U)
+#define RCC_PERIPHCLK_UART8           ((uint32_t)0x00002000U)
+#define RCC_PERIPHCLK_I2C1            ((uint32_t)0x00004000U)
+#define RCC_PERIPHCLK_I2C2            ((uint32_t)0x00008000U)
+#define RCC_PERIPHCLK_I2C3            ((uint32_t)0x00010000U)
+#define RCC_PERIPHCLK_I2C4            ((uint32_t)0x00020000U)
+#define RCC_PERIPHCLK_LPTIM1          ((uint32_t)0x00040000U)
+#define RCC_PERIPHCLK_SAI1            ((uint32_t)0x00080000U)
+#define RCC_PERIPHCLK_SAI2            ((uint32_t)0x00100000U)
+#define RCC_PERIPHCLK_CLK48           ((uint32_t)0x00200000U)
+#define RCC_PERIPHCLK_CEC             ((uint32_t)0x00400000U)
+#define RCC_PERIPHCLK_SDMMC1          ((uint32_t)0x00800000U)
+#define RCC_PERIPHCLK_SPDIFRX         ((uint32_t)0x01000000U)
+#define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x02000000U)
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+#define RCC_PERIPHCLK_SDMMC2          ((uint32_t)0x04000000U)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define RCC_PERIPHCLK_DFSDM1           ((uint32_t)0x08000000U)
+#define RCC_PERIPHCLK_DFSDM1_AUDIO     ((uint32_t)0x10000000U)
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/**
+  * @}
+  */
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
+    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
+  * @{
+  */
+#define RCC_PLLI2SP_DIV2                  ((uint32_t)0x00000000U)
+#define RCC_PLLI2SP_DIV4                  ((uint32_t)0x00000001U)
+#define RCC_PLLI2SP_DIV6                  ((uint32_t)0x00000002U)
+#define RCC_PLLI2SP_DIV8                  ((uint32_t)0x00000003U)
+/**
+  * @}
+  */
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
+  * @{
+  */
+#define RCC_PLLSAIP_DIV2                  ((uint32_t)0x00000000U)
+#define RCC_PLLSAIP_DIV4                  ((uint32_t)0x00000001U)
+#define RCC_PLLSAIP_DIV6                  ((uint32_t)0x00000002U)
+#define RCC_PLLSAIP_DIV8                  ((uint32_t)0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
+  * @{
+  */
+#define RCC_PLLSAIDIVR_2                ((uint32_t)0x00000000U)
+#define RCC_PLLSAIDIVR_4                RCC_DCKCFGR1_PLLSAIDIVR_0
+#define RCC_PLLSAIDIVR_8                RCC_DCKCFGR1_PLLSAIDIVR_1
+#define RCC_PLLSAIDIVR_16               RCC_DCKCFGR1_PLLSAIDIVR
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
+  * @{
+  */
+#define RCC_I2SCLKSOURCE_PLLI2S             ((uint32_t)0x00000000U)
+#define RCC_I2SCLKSOURCE_EXT                RCC_CFGR_I2SSRC
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
+  * @{
+  */
+#define RCC_SAI1CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
+#define RCC_SAI1CLKSOURCE_PLLI2S             RCC_DCKCFGR1_SAI1SEL_0
+#define RCC_SAI1CLKSOURCE_PIN                RCC_DCKCFGR1_SAI1SEL_1
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define RCC_SAI1CLKSOURCE_PLLSRC             RCC_DCKCFGR1_SAI1SEL
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
+  * @{
+  */
+#define RCC_SAI2CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
+#define RCC_SAI2CLKSOURCE_PLLI2S             RCC_DCKCFGR1_SAI2SEL_0
+#define RCC_SAI2CLKSOURCE_PIN                RCC_DCKCFGR1_SAI2SEL_1
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define RCC_SAI2CLKSOURCE_PLLSRC             RCC_DCKCFGR1_SAI2SEL
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
+  * @{
+  */
+#define RCC_CECCLKSOURCE_LSE             ((uint32_t)0x00000000U)
+#define RCC_CECCLKSOURCE_HSI             RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
+  * @{
+  */
+#define RCC_USART1CLKSOURCE_PCLK2      ((uint32_t)0x00000000U)
+#define RCC_USART1CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART1SEL_0
+#define RCC_USART1CLKSOURCE_HSI        RCC_DCKCFGR2_USART1SEL_1
+#define RCC_USART1CLKSOURCE_LSE        RCC_DCKCFGR2_USART1SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
+  * @{
+  */
+#define RCC_USART2CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
+#define RCC_USART2CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART2SEL_0
+#define RCC_USART2CLKSOURCE_HSI        RCC_DCKCFGR2_USART2SEL_1
+#define RCC_USART2CLKSOURCE_LSE        RCC_DCKCFGR2_USART2SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
+  * @{
+  */
+#define RCC_USART3CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
+#define RCC_USART3CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART3SEL_0
+#define RCC_USART3CLKSOURCE_HSI        RCC_DCKCFGR2_USART3SEL_1
+#define RCC_USART3CLKSOURCE_LSE        RCC_DCKCFGR2_USART3SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
+  * @{
+  */
+#define RCC_UART4CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
+#define RCC_UART4CLKSOURCE_SYSCLK       RCC_DCKCFGR2_UART4SEL_0
+#define RCC_UART4CLKSOURCE_HSI          RCC_DCKCFGR2_UART4SEL_1
+#define RCC_UART4CLKSOURCE_LSE          RCC_DCKCFGR2_UART4SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
+  * @{
+  */
+#define RCC_UART5CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
+#define RCC_UART5CLKSOURCE_SYSCLK       RCC_DCKCFGR2_UART5SEL_0
+#define RCC_UART5CLKSOURCE_HSI          RCC_DCKCFGR2_UART5SEL_1
+#define RCC_UART5CLKSOURCE_LSE          RCC_DCKCFGR2_UART5SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
+  * @{
+  */
+#define RCC_USART6CLKSOURCE_PCLK2       ((uint32_t)0x00000000U)
+#define RCC_USART6CLKSOURCE_SYSCLK      RCC_DCKCFGR2_USART6SEL_0
+#define RCC_USART6CLKSOURCE_HSI         RCC_DCKCFGR2_USART6SEL_1
+#define RCC_USART6CLKSOURCE_LSE         RCC_DCKCFGR2_USART6SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
+  * @{
+  */
+#define RCC_UART7CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
+#define RCC_UART7CLKSOURCE_SYSCLK      RCC_DCKCFGR2_UART7SEL_0
+#define RCC_UART7CLKSOURCE_HSI         RCC_DCKCFGR2_UART7SEL_1
+#define RCC_UART7CLKSOURCE_LSE         RCC_DCKCFGR2_UART7SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
+  * @{
+  */
+#define RCC_UART8CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
+#define RCC_UART8CLKSOURCE_SYSCLK      RCC_DCKCFGR2_UART8SEL_0
+#define RCC_UART8CLKSOURCE_HSI         RCC_DCKCFGR2_UART8SEL_1
+#define RCC_UART8CLKSOURCE_LSE         RCC_DCKCFGR2_UART8SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
+  * @{
+  */
+#define RCC_I2C1CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
+#define RCC_I2C1CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C1SEL_0
+#define RCC_I2C1CLKSOURCE_HSI          RCC_DCKCFGR2_I2C1SEL_1
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
+  * @{
+  */
+#define RCC_I2C2CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
+#define RCC_I2C2CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C2SEL_0
+#define RCC_I2C2CLKSOURCE_HSI          RCC_DCKCFGR2_I2C2SEL_1
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
+  * @{
+  */
+#define RCC_I2C3CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
+#define RCC_I2C3CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C3SEL_0
+#define RCC_I2C3CLKSOURCE_HSI          RCC_DCKCFGR2_I2C3SEL_1
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
+  * @{
+  */
+#define RCC_I2C4CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
+#define RCC_I2C4CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI          RCC_DCKCFGR2_I2C4SEL_1
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
+  * @{
+  */
+#define RCC_LPTIM1CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
+#define RCC_LPTIM1CLKSOURCE_LSI        RCC_DCKCFGR2_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_HSI        RCC_DCKCFGR2_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE        RCC_DCKCFGR2_LPTIM1SEL
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
+  * @{
+  */
+#define RCC_CLK48SOURCE_PLL         ((uint32_t)0x00000000U)
+#define RCC_CLK48SOURCE_PLLSAIP     RCC_DCKCFGR2_CK48MSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
+  * @{
+  */
+#define RCC_TIMPRES_DESACTIVATED        ((uint32_t)0x00000000U)
+#define RCC_TIMPRES_ACTIVATED           RCC_DCKCFGR1_TIMPRE
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
+  * @{
+  */
+#define RCC_SDMMC1CLKSOURCE_CLK48              ((uint32_t)0x00000000U)
+#define RCC_SDMMC1CLKSOURCE_SYSCLK             RCC_DCKCFGR2_SDMMC1SEL
+/**
+  * @}
+  */
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source
+  * @{
+  */
+#define RCC_SDMMC2CLKSOURCE_CLK48              ((uint32_t)0x00000000U)
+#define RCC_SDMMC2CLKSOURCE_SYSCLK             RCC_DCKCFGR2_SDMMC2SEL
+/**
+  * @}
+  */
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source  RCCEx DFSDM1 Kernel Clock Source
+  * @{
+  */
+#define RCC_DFSDM1CLKSOURCE_PCLK2             ((uint32_t)0x00000000U)
+#define RCC_DFSDM1CLKSOURCE_SYSCLK           RCC_DCKCFGR1_DFSDM1SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source
+  * @{
+  */
+#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1        ((uint32_t)0x00000000U)
+#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2        RCC_DCKCFGR1_ADFSDM1SEL
+/**
+  * @}
+  */
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+#if defined (STM32F769xx) || defined (STM32F779xx)
+/** @defgroup RCCEx_DSI_Clock_Source  RCC DSI Clock Source
+  * @{
+  */
+#define RCC_DSICLKSOURCE_DSIPHY             ((uint32_t)0x00000000U)
+#define RCC_DSICLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR2_DSISEL)
+/**
+  * @}
+  */
+#endif /* STM32F769xx || STM32F779xx */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+  * @{
+  */
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
+  * @brief  Enables or disables the AHB/APB peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+/** @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
+#define __HAL_RCC_DMA2_CLK_DISABLE()            (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
+#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
+#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
+#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+/**
+  * @brief  Enable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_ETH_CLK_ENABLE()       do {                            \
+                                     __HAL_RCC_ETHMAC_CLK_ENABLE();      \
+                                     __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
+                                     __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
+                                    } while(0)
+/**
+  * @brief  Disable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
+#define __HAL_RCC_ETH_CLK_DISABLE()       do {                             \
+                                      __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
+                                      __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
+                                      __HAL_RCC_ETHMAC_CLK_DISABLE();      \
+                                     } while(0)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_JPEG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_JPEG_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+#define __HAL_RCC_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
+                                        UNUSED(tmpreg); \
+                                        __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                      } while(0)
+
+#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+#endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define __HAL_RCC_AES_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_AES_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
+#endif /* STM32F732xx || STM32F733xx || STM32F730xx */
+
+/** @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_FMC_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_QSPI_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+
+/** @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
+    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
+    defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
+          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_CAN3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
+    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
+    defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_RTC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
+          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_CAN3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
+#define __HAL_RCC_UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
+#define __HAL_RCC_I2C4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_CEC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */
+
+/** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */
+
+#define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM9_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM10_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_TIM11_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined (STM32F769xx) || defined (STM32F779xx)
+#define __HAL_RCC_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#endif /* STM32F769xx || STM32F779xx */
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+
+#define __HAL_RCC_MDIO_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define __HAL_RCC_OTGPHYC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */
+
+#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+#define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_LTDC_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#if defined (STM32F769xx) || defined (STM32F779xx)
+#define __HAL_RCC_DSI_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
+#endif /* STM32F769xx || STM32F779xx */
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
+#define __HAL_RCC_MDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN))
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB/APB peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+/** @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
+#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
+#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+/**
+  * @brief  Enable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
+#define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
+                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
+                                               __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
+
+/**
+  * @brief  Disable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
+#define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
+                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
+                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+/** @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
+#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define __HAL_RCC_AES_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
+#define __HAL_RCC_AES_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
+#endif /* STM32F732xx || STM32F733xx || STM32F730xx */
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_JPEG_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)
+#define __HAL_RCC_JPEG_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/** @brief  Get the enable or disable status of the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
+
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+
+/** @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_CAN3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+#define __HAL_RCC_UART7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
+#define __HAL_RCC_UART8_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_CAN3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
+#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
+
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
+    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
+    defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_RTC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)
+#define __HAL_RCC_RTC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
+          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+
+/** @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
+#define __HAL_RCC_USART6_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#if defined (STM32F769xx) || defined (STM32F779xx)
+#define __HAL_RCC_DSI_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
+#endif /* STM32F769xx || STM32F779xx */
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
+#define __HAL_RCC_MDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET)
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#if defined (STM32F769xx) || defined (STM32F779xx)
+#define __HAL_RCC_DSI_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
+#endif /* STM32F769xx || STM32F779xx */
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
+#define __HAL_RCC_MDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET)
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
+  * @brief  Forces or releases AHB/APB peripheral reset.
+  * @{
+  */
+
+/** @brief  Force or release AHB1 peripheral reset.
+  */
+#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_GPIOI_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+
+#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
+#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_GPIOJ_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
+#define __HAL_RCC_GPIOK_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
+
+#define __HAL_RCC_DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
+#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+/** @brief  Force or release AHB2 peripheral reset.
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_JPEG_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST))
+#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define __HAL_RCC_AES_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))
+#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
+#endif /* STM32F732xx || STM32F733xx || STM32F730xx */
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+/** @brief  Force or release AHB3 peripheral reset
+  */
+#define __HAL_RCC_AHB3_FORCE_RESET()   (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
+#define __HAL_RCC_FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+
+/** @brief  Force or release APB1 peripheral reset.
+  */
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_CAN3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_CAN3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPDIFRX_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_I2C4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
+#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_I2C4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+/** @brief  Force or release APB2 peripheral reset.
+  */
+#define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SDMMC1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
+#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPI6_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_LTDC_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define __HAL_RCC_OTGPHYC_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST))
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */
+
+#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPI6_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_LTDC_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST))
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */
+
+#if defined (STM32F769xx) || defined (STM32F779xx)
+#define __HAL_RCC_DSI_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
+#define __HAL_RCC_DSI_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
+#endif /* STM32F769xx || STM32F779xx */
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_SDMMC2_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))
+#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_DFSDM1_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
+#define __HAL_RCC_MDIO_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST))
+#define __HAL_RCC_DFSDM1_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
+#define __HAL_RCC_MDIO_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
+  * @brief  Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+/** @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  */
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE()       (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()       (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
+
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+/** @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
+#endif /* STM32F732xx || STM32F733xx || STM32F730xx */
+
+/** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+
+/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
+    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
+    defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))
+#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
+          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
+
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx)
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx  */
+#if defined (STM32F769xx) || defined (STM32F779xx)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
+#endif /* STM32F769xx || STM32F779xx */
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
+#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN))
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
+#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+
+/** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
+#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
+#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
+
+#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
+#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
+#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
+#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
+
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
+#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+/** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)
+#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
+
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
+
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
+
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET)
+#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET)
+#endif /* STM32F732xx || STM32F733xx || STM32F730xx */
+
+/** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
+
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
+
+/** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
+    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
+    defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
+          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
+    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
+    defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
+          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
+
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+/** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
+#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
+#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
+#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
+#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#if defined (STM32F769xx) || defined (STM32F779xx)
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)
+#endif /* STM32F769xx || STM32F779xx */
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)
+#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
+#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
+#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
+#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
+#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#if defined (STM32F769xx) || defined (STM32F779xx)
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)
+#endif /* STM32F769xx || STM32F779xx */
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)
+#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+/**
+  * @}
+  */
+
+/*------------------------------- PLL Configuration --------------------------*/
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLL jitter.
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 100 and 432 MHz.
+  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  * @note   You have to set the PLLP parameter correctly to not exceed 216 MHz on
+  *         the System clock frequency.
+  * @param  __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  * @note   If the USB OTG FS is used in your application, you have to set the
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+  *         the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
+  *         correctly.
+  * @param  __PLLR__ specifies the division factor for DSI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__)  \
+                            (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \
+                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                      | \
+                            ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos)          | \
+                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)                      | \
+                            ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
+#else
+/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLL jitter.
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 100 and 432 MHz.
+  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  * @note   You have to set the PLLP parameter correctly to not exceed 216 MHz on
+  *         the System clock frequency.
+  * @param  __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  * @note   If the USB OTG FS is used in your application, you have to set the
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+  *         the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
+  *         correctly.
+  */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)     \
+                            (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
+                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                          | \
+                            ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos)              | \
+                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+/*---------------------------------------------------------------------------------------------*/
+
+/** @brief  Macro to configure the Timers clocks prescalers
+  * @param  __PRESC__  specifies the Timers clocks prescalers selection
+  *         This parameter can be one of the following values:
+  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
+  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2,
+  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
+  *                 division by 4 or more.
+  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
+  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
+  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
+  *                 to division by 8 or more.
+  */
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
+                                                 RCC->DCKCFGR1 |= (__PRESC__);           \
+                                                }while(0)
+
+/** @brief Macros to Enable or Disable the PLLISAI.
+  * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
+#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
+  * @note   This function must be used only when the PLLSAI is disabled.
+  * @note   PLLSAI clock source is common with the main PLL (configured in
+  *         RCC_PLLConfig function )
+  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  * @param  __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks
+  *         This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
+  * @param  __PLLSAIQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__)                        \
+                               (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\
+                               ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos)                    |\
+                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))
+
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors.
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in
+  *         HAL_RCC_ClockConfig() API)
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  * @param  __PLLI2SQ__ specifies the division factor for SAI clock.
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__)                        \
+                               (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)                    |\
+                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))
+#else
+/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
+  * @note   This function must be used only when the PLLSAI is disabled.
+  * @note   PLLSAI clock source is common with the main PLL (configured in
+  *         RCC_PLLConfig function )
+  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  * @param  __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks
+  *         This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
+  * @param  __PLLSAIQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  * @param  __PLLSAIR__ specifies the division factor for LTDC clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)              \
+                               (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\
+                               ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos)                    |\
+                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)                    |\
+                               ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))
+
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors.
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in
+  *         HAL_RCC_ClockConfig() API)
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  * @param  __PLLI2SP__ specifies the division factor for SPDDIF-RX clock.
+  *         This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
+  * @param  __PLLI2SQ__ specifies the division factor for SAI clock.
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)              \
+                               (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+                               ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos)                    |\
+                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)                    |\
+                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
+
+/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
+  * @note   This function must be called before enabling the PLLI2S.
+  * @param  __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock .
+  *          This parameter must be a number between 1 and 32.
+  *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
+  */
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
+
+/** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.
+  * @note   This function must be called before enabling the PLLSAI.
+  * @param  __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.
+  *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
+  */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
+    defined (STM32F750xx)
+/** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.
+  * @note   This function must be called before enabling the PLLSAI.
+  * @param  __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
+  *          This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
+  *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
+  */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
+                            MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+/** @brief  Macro to configure SAI1 clock source selection.
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+  *                                           as SAI1 clock.
+  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+  *                                           as SAI1 clock.
+  *            @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
+  *                                        used as SAI1 clock.
+  *            @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
+  *                                           used as SAI1 clock.
+  * @note      The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
+  */
+#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
+                             MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
+
+/** @brief  Macro to get the SAI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+  *                                           as SAI1 clock.
+  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+  *                                           as SAI1 clock.
+  *            @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
+  *                                        used as SAI1 clock.
+  *            @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
+  *                                           used as SAI1 clock.
+  * @note      The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
+  */
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
+
+/** @brief  Macro to configure SAI2 clock source selection.
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI2 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+  *                                           as SAI2 clock.
+  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+  *                                           as SAI2 clock.
+  *            @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
+  *                                        used as SAI2 clock.
+  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
+  *                                           used as SAI2 clock.
+  * @note      The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
+  */
+#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
+                            MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
+
+
+/** @brief  Macro to get the SAI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+  *                                           as SAI2 clock.
+  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+  *                                           as SAI2 clock.
+  *            @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
+  *                                        used as SAI2 clock.
+  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
+  *                                           used as SAI2 clock.
+  * @note      The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
+  */
+#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
+
+
+/** @brief Enable PLLSAI_RDY interrupt.
+  */
+#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Disable PLLSAI_RDY interrupt.
+  */
+#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Clear the PLLSAI RDY interrupt pending bits.
+  */
+#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
+
+/** @brief Check the PLLSAI RDY interrupt has occurred or not.
+  * @retval The new state (TRUE or FALSE).
+  */
+#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief  Check PLLSAI RDY flag is set or not.
+  * @retval The new state (TRUE or FALSE).
+  */
+#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
+
+/** @brief  Macro to Get I2S clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
+  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
+  */
+#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
+
+/** @brief  Macro to configure the I2C1 clock (I2C1CLK).
+  *
+  * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
+  */
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
+  */
+#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
+
+/** @brief  Macro to configure the I2C2 clock (I2C2CLK).
+  *
+  * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
+  */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
+  */
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
+
+/** @brief  Macro to configure the I2C3 clock (I2C3CLK).
+  *
+  * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
+  */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
+
+/** @brief  macro to get the I2C3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
+  */
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
+
+/** @brief  Macro to configure the I2C4 clock (I2C4CLK).
+  *
+  * @param  __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
+  */
+#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
+
+/** @brief  macro to get the I2C4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
+  */
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
+
+/** @brief  Macro to configure the USART1 clock (USART1CLK).
+  *
+  * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+  */
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
+
+/** @brief  macro to get the USART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+  */
+#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
+
+/** @brief  Macro to configure the USART2 clock (USART2CLK).
+  *
+  * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+  */
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
+
+/** @brief  macro to get the USART2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+  */
+#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
+
+/** @brief  Macro to configure the USART3 clock (USART3CLK).
+  *
+  * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+  */
+#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
+
+/** @brief  macro to get the USART3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+  */
+#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
+
+ /** @brief  Macro to configure the UART4 clock (UART4CLK).
+  *
+  * @param  __UART4_CLKSOURCE__ specifies the UART4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
+  */
+#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
+
+/** @brief  macro to get the UART4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
+  */
+#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
+
+ /** @brief  Macro to configure the UART5 clock (UART5CLK).
+  *
+  * @param  __UART5_CLKSOURCE__ specifies the UART5 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
+  */
+#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
+
+/** @brief  macro to get the UART5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
+  */
+#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
+
+ /** @brief  Macro to configure the USART6 clock (USART6CLK).
+  *
+  * @param  __USART6_CLKSOURCE__ specifies the USART6 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
+  */
+#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
+
+/** @brief  macro to get the USART6 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
+  */
+#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
+
+ /** @brief  Macro to configure the UART7 clock (UART7CLK).
+  *
+  * @param  __UART7_CLKSOURCE__ specifies the UART7 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
+  */
+#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
+
+/** @brief  macro to get the UART7 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
+  */
+#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
+
+/** @brief  Macro to configure the UART8 clock (UART8CLK).
+  *
+  * @param  __UART8_CLKSOURCE__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
+  */
+#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
+
+/** @brief  macro to get the UART8 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
+  */
+#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
+
+/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
+  *
+  * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  */
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
+
+/** @brief  macro to get the LPTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
+
+/** @brief  Macro to configure the CEC clock (CECCLK).
+  *
+  * @param  __CEC_CLKSOURCE__ specifies the CEC clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
+  */
+#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
+
+/** @brief  macro to get the CEC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
+  */
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
+
+/** @brief  Macro to configure the CLK48 source (CLK48CLK).
+  *
+  * @param  __CLK48_SOURCE__ specifies the CLK48 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
+  *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
+  */
+#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
+
+/** @brief  macro to get the CLK48 source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
+  *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
+  */
+#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
+
+/** @brief  Macro to configure the SDMMC1 clock (SDMMC1CLK).
+  *
+  * @param  __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
+  *            @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
+  */
+#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
+
+/** @brief  macro to get the SDMMC1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
+  *            @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
+  */
+#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+/** @brief  Macro to configure the SDMMC2 clock (SDMMC2CLK).
+  * @param  __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
+  *            @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
+  */
+#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))
+
+/** @brief  macro to get the SDMMC2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
+  *            @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
+  */
+#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx  || STM32F730xx */
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+/** @brief  Macro to configure the DFSDM1 clock
+  * @param  __DFSDM1_CLKSOURCE__ specifies the DFSDM1  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock
+  *            @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock
+  */
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
+
+/** @brief  Macro to get the DFSDM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2:  PCLK2 Clock selected as DFSDM1 clock
+  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK:   System Clock selected as DFSDM1 clock
+  */
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))
+
+/** @brief  Macro to configure the DFSDM1 Audio clock
+  * @param  __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1:  SAI1 Clock selected as DFSDM1 Audio clock
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2:  SAI2 Clock selected as DFSDM1 Audio clock
+  */
+#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
+                  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))
+
+/** @brief  Macro to get the DFSDM1 Audio clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1:  SAI1 Clock selected as DFSDM1 Audio clock
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2:  SAI2 Clock selected as DFSDM1 Audio clock
+  */
+#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+#if defined (STM32F769xx) || defined (STM32F779xx)
+/** @brief  Macro to configure the DSI clock.
+  * @param  __DSI_CLKSOURCE__ specifies the DSI clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
+  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
+  */
+#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))
+
+/** @brief  Macro to Get the DSI clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
+  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
+  */
+#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))
+#endif /* STM32F769xx || STM32F779xx */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
+  * @{
+  */
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION)  \
+               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
+                (((SELECTION) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \
+                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
+                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
+                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
+                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
+                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
+                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
+                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
+                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
+                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
+                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
+                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
+                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
+                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
+                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
+#elif defined(STM32F745xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION)  \
+               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
+                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
+                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
+                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
+                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
+                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
+                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
+                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
+                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
+                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
+                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
+                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
+                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
+                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
+                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
+#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION)  \
+               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
+                (((SELECTION) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \
+                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
+                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
+                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
+                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
+                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
+                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
+                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
+                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
+                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
+                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
+                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
+                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
+                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SDMMC2)      == RCC_PERIPHCLK_SDMMC2)  || \
+                (((SELECTION) & RCC_PERIPHCLK_DFSDM1)       == RCC_PERIPHCLK_DFSDM1)   || \
+                (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
+                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
+                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
+#elif defined (STM32F765xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION)  \
+               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
+                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
+                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
+                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
+                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
+                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
+                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
+                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
+                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \
+                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
+                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
+                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
+                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \
+                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SDMMC2)      == RCC_PERIPHCLK_SDMMC2)  || \
+                (((SELECTION) & RCC_PERIPHCLK_DFSDM1)       == RCC_PERIPHCLK_DFSDM1)   || \
+                (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
+                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \
+                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
+#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION)  \
+               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \
+                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \
+                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \
+                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \
+                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \
+                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \
+                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \
+                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \
+                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \
+                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \
+                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \
+                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \
+                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \
+                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \
+                (((SELECTION) & RCC_PERIPHCLK_SDMMC2)      == RCC_PERIPHCLK_SDMMC2)  || \
+                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))
+#endif /* STM32F746xx || STM32F756xx || STM32F750xx */
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
+    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
+                                     ((VALUE) == RCC_PLLI2SP_DIV4) ||\
+                                     ((VALUE) == RCC_PLLI2SP_DIV6) ||\
+                                     ((VALUE) == RCC_PLLI2SP_DIV8))
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
+                                     ((VALUE) == RCC_PLLSAIP_DIV4) ||\
+                                     ((VALUE) == RCC_PLLSAIP_DIV6) ||\
+                                     ((VALUE) == RCC_PLLSAIP_DIV8))
+#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_4) ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_8) ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_16))
+#define IS_RCC_I2SCLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
+                                      ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
+
+#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
+                                        ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
+
+#define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
+                                      ((SOURCE) == RCC_CECCLKSOURCE_LSE))
+#define IS_RCC_USART1CLKSOURCE(SOURCE)  \
+               (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2)  || \
+                ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+                ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
+                ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+
+#define IS_RCC_USART2CLKSOURCE(SOURCE)  \
+               (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1)  || \
+                ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
+                ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
+                ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
+#define IS_RCC_USART3CLKSOURCE(SOURCE)  \
+               (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1)  || \
+                ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
+                ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
+                ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
+
+#define IS_RCC_UART4CLKSOURCE(SOURCE)  \
+               (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1)  || \
+                ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
+                ((SOURCE) == RCC_UART4CLKSOURCE_LSE)    || \
+                ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
+
+#define IS_RCC_UART5CLKSOURCE(SOURCE)  \
+               (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1)  || \
+                ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
+                ((SOURCE) == RCC_UART5CLKSOURCE_LSE)    || \
+                ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
+
+#define IS_RCC_USART6CLKSOURCE(SOURCE)  \
+               (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2)  || \
+                ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
+                ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
+                ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
+
+#define IS_RCC_UART7CLKSOURCE(SOURCE)  \
+               (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1)  || \
+                ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
+                ((SOURCE) == RCC_UART7CLKSOURCE_LSE)    || \
+                ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
+
+#define IS_RCC_UART8CLKSOURCE(SOURCE)  \
+               (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1)  || \
+                ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
+                ((SOURCE) == RCC_UART8CLKSOURCE_LSE)    || \
+                ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
+#define IS_RCC_I2C1CLKSOURCE(SOURCE)   \
+               (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
+                ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
+                ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
+#define IS_RCC_I2C2CLKSOURCE(SOURCE)   \
+               (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
+                ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
+                ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
+
+#define IS_RCC_I2C3CLKSOURCE(SOURCE)   \
+               (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
+                ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
+                ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
+#define IS_RCC_I2C4CLKSOURCE(SOURCE)   \
+               (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
+                ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
+                ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
+#define IS_RCC_LPTIM1CLK(SOURCE)  \
+               (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
+                ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)  || \
+                ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI)  || \
+                ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
+#define IS_RCC_CLK48SOURCE(SOURCE)  \
+               (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
+                ((SOURCE) == RCC_CLK48SOURCE_PLL))
+#define IS_RCC_TIMPRES(VALUE)  \
+               (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
+                ((VALUE) == RCC_TIMPRES_ACTIVATED))
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\
+    defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx)
+#define IS_RCC_SAI1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
+                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
+                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
+#define IS_RCC_SAI2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
+                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
+                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define IS_RCC_PLLR_VALUE(VALUE)            ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+#define IS_RCC_SAI1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
+                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
+                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)    || \
+                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))
+
+#define IS_RCC_SAI2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
+                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
+                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)    || \
+                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
+                                        ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \
+                                             ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)
+#define IS_RCC_SDMMC2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \
+                                         ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
+
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR)  ||\
+                                             ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_RCC_EX_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h
new file mode 100644
index 0000000..8604832
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h
@@ -0,0 +1,758 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_sd.h
+  * @author  MCD Application Team
+  * @brief   Header file of SD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_HAL_SD_H
+#define STM32F7xx_HAL_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(SDMMC1)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_sdmmc.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SD SD
+  * @brief SD HAL module driver
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup SD_Exported_Types SD Exported Types
+  * @{
+  */
+
+/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
+  * @{
+  */   
+typedef enum
+{
+  HAL_SD_STATE_RESET                  = 0x00000000U,  /*!< SD not yet initialized or disabled  */
+  HAL_SD_STATE_READY                  = 0x00000001U,  /*!< SD initialized and ready for use    */
+  HAL_SD_STATE_TIMEOUT                = 0x00000002U,  /*!< SD Timeout state                    */
+  HAL_SD_STATE_BUSY                   = 0x00000003U,  /*!< SD process ongoing                  */
+  HAL_SD_STATE_PROGRAMMING            = 0x00000004U,  /*!< SD Programming State                */
+  HAL_SD_STATE_RECEIVING              = 0x00000005U,  /*!< SD Receiving State                  */
+  HAL_SD_STATE_TRANSFER               = 0x00000006U,  /*!< SD Transfer State                  */
+  HAL_SD_STATE_ERROR                  = 0x0000000FU   /*!< SD is in error state                */
+}HAL_SD_StateTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
+  * @{
+  */   
+typedef uint32_t HAL_SD_CardStateTypeDef;
+
+#define HAL_SD_CARD_READY          0x00000001U  /*!< Card state is ready                     */
+#define HAL_SD_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */
+#define HAL_SD_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */
+#define HAL_SD_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */
+#define HAL_SD_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */
+#define HAL_SD_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */
+#define HAL_SD_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */
+#define HAL_SD_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */
+#define HAL_SD_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition   
+  * @{
+  */
+#define SD_InitTypeDef      SDMMC_InitTypeDef 
+#define SD_TypeDef          SDMMC_TypeDef
+
+/** 
+  * @brief  SD Card Information Structure definition
+  */ 
+typedef struct
+{
+  uint32_t CardType;                     /*!< Specifies the card Type                         */
+  
+  uint32_t CardVersion;                  /*!< Specifies the card version                      */
+
+  uint32_t Class;                        /*!< Specifies the class of the card class           */
+
+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
+  
+  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
+
+  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
+  
+  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
+
+  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
+
+}HAL_SD_CardInfoTypeDef;
+
+/** 
+  * @brief  SD handle Structure definition
+  */ 
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+typedef struct __SD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+{
+  SD_TypeDef                   *Instance;        /*!< SD registers base address           */
+  
+  SD_InitTypeDef               Init;             /*!< SD required parameters              */
+  
+  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
+  
+  uint8_t                      *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
+
+  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
+
+  uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */
+
+  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */
+  
+  __IO uint32_t                Context;          /*!< SD transfer context                 */
+ 
+  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */
+  
+  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */  
+ 
+  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters         */
+
+  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters         */
+  
+  HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
+  
+  uint32_t                     CSD[4];           /*!< SD card specific data table         */
+  
+  uint32_t                     CID[4];           /*!< SD card identification number table */
+  
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+  void (* TxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
+  void (* RxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
+  void (* ErrorCallback)                  (struct __SD_HandleTypeDef *hsd);
+  void (* AbortCpltCallback)              (struct __SD_HandleTypeDef *hsd);
+
+  void (* MspInitCallback)                (struct __SD_HandleTypeDef *hsd);
+  void (* MspDeInitCallback)              (struct __SD_HandleTypeDef *hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+}SD_HandleTypeDef;
+
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register 
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
+  __IO uint8_t  Reserved1;            /*!< Reserved                              */
+  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
+  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
+  __IO uint8_t  Reserved2;            /*!< Reserved                              */
+  __IO uint32_t DeviceSize;           /*!< Device Size                           */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
+  __IO uint8_t  Reserved3;            /*!< Reserved                              */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
+  __IO uint8_t  FileFormatGroup;      /*!< File format group                     */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
+  __IO uint8_t  FileFormat;           /*!< File format                           */
+  __IO uint8_t  ECC;                  /*!< ECC code                              */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
+  __IO uint8_t  Reserved4;            /*!< Always 1                              */
+}HAL_SD_CardCSDTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
+  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
+  __IO uint32_t ProdName1;       /*!< Product Name part1    */
+  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
+  __IO uint8_t  ProdRev;         /*!< Product Revision      */
+  __IO uint32_t ProdSN;          /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;       /*!< Reserved1             */
+  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
+  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
+  __IO uint8_t  Reserved2;       /*!< Always 1              */
+
+}HAL_SD_CardCIDTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */
+  __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */
+  __IO uint16_t CardType;               /*!< Carries information about card type                        */
+  __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */
+  __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */
+  __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */
+  __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */
+  __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */
+  __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */
+  __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */
+
+}HAL_SD_CardStatusTypeDef;
+/** 
+  * @}
+  */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition 
+  * @{
+  */
+typedef enum
+{
+  HAL_SD_TX_CPLT_CB_ID                 = 0x00U,  /*!< SD Tx Complete Callback ID                     */
+  HAL_SD_RX_CPLT_CB_ID                 = 0x01U,  /*!< SD Rx Complete Callback ID                     */
+  HAL_SD_ERROR_CB_ID                   = 0x02U,  /*!< SD Error Callback ID                           */
+  HAL_SD_ABORT_CB_ID                   = 0x03U,  /*!< SD Abort Callback ID                           */
+
+  HAL_SD_MSP_INIT_CB_ID                = 0x10U,  /*!< SD MspInit Callback ID                         */
+  HAL_SD_MSP_DEINIT_CB_ID              = 0x11U   /*!< SD MspDeInit Callback ID                       */
+}HAL_SD_CallbackIDTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition 
+  * @{
+  */
+typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
+/** 
+  * @}
+  */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+/** 
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants Exported Constants
+  * @{
+  */
+
+#define BLOCKSIZE   512U /*!< Block size is 512 bytes */
+
+/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition 
+  * @{
+  */  
+#define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */
+#define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */
+#define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */
+#define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */
+#define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */
+#define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */
+#define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
+#define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
+#define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the 
+                                                                                       number of transferred bytes does not match the block length   */
+#define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
+#define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
+#define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock 
+                                                                                       command or if there was an attempt to access a locked card    */
+#define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
+#define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
+#define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
+#define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */
+#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */
+#define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */
+#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */
+#define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */
+#define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
+#define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
+#define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out 
+                                                                                       of erase sequence command was received                        */
+#define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
+#define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */        
+#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */        
+#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */  
+#define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */  
+#define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */
+#define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */ 
+#define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */
+#define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */
+                                                
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define HAL_SD_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+/** 
+  * @}
+  */
+ 
+/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
+  * @{
+  */ 
+#define SD_CONTEXT_NONE                            0x00000000U   /*!< None                             */
+#define SD_CONTEXT_READ_SINGLE_BLOCK               0x00000001U   /*!< Read single block operation      */
+#define SD_CONTEXT_READ_MULTIPLE_BLOCK             0x00000002U   /*!< Read multiple blocks operation   */
+#define SD_CONTEXT_WRITE_SINGLE_BLOCK              0x00000010U   /*!< Write single block operation     */
+#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK            0x00000020U   /*!< Write multiple blocks operation  */
+#define SD_CONTEXT_IT                              0x00000008U   /*!< Process in Interrupt mode        */
+#define SD_CONTEXT_DMA                             0x00000080U   /*!< Process in DMA mode              */
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
+  * @{
+  */
+#define CARD_SDSC                  0x00000000U  /*!< SD Standard Capacity <2Go                          */
+#define CARD_SDHC_SDXC             0x00000001U  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */
+#define CARD_SECURED               0x00000003U
+    
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
+  * @{
+  */
+#define CARD_V1_X                  0x00000000U
+#define CARD_V2_X                  0x00000001U
+/**
+  * @}
+  */
+      
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SD_Exported_macros SD Exported Macros
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+/** @brief Reset SD handle state.
+  * @param  __HANDLE__ : SD handle.
+  * @retval None
+  */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
+                                                               (__HANDLE__)->State = HAL_SD_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_SD_STATE_RESET)
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 
+/**
+  * @brief  Enable the SD device.
+  * @retval None
+  */ 
+#define __HAL_SD_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Disable the SD device.
+  * @retval None
+  */
+#define __HAL_SD_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Enable the SDMMC DMA transfer.
+  * @retval None
+  */ 
+#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Disable the SDMMC DMA transfer.
+  * @retval None
+  */
+#define __HAL_SD_DMA_DISABLE(__HANDLE__)  __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
+ 
+/**
+  * @brief  Enable the SD device interrupt.
+  * @param  __HANDLE__: SD Handle  
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SDIO interrupt received interrupt
+  * @retval None
+  */
+#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SD device interrupt.
+  * @param  __HANDLE__: SD Handle   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SDIO interrupt received interrupt   
+  * @retval None
+  */
+#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified SD flag is set or not. 
+  * @param  __HANDLE__: SD Handle   
+  * @param  __FLAG__: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
+  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
+  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
+  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
+  *            @arg SDMMC_FLAG_SDIOIT:   SDIO interrupt received
+  * @retval The new state of SD FLAG (SET or RESET).
+  */
+#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Clear the SD's pending flags.
+  * @param  __HANDLE__: SD Handle  
+  * @param  __FLAG__: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_SDIOIT:   SDIO interrupt received
+  * @retval None
+  */
+#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Check whether the specified SD interrupt has occurred or not.
+  * @param  __HANDLE__: SD Handle   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SDIO interrupt received interrupt
+  * @retval The new state of SD IT (SET or RESET).
+  */
+#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Clear the SD's interrupt pending bits.
+  * @param  __HANDLE__: SD Handle
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SDIO interrupt received interrupt
+  * @retval None
+  */
+#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @}
+  */
+  
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SD_Exported_Functions SD Exported Functions
+  * @{
+  */
+  
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
+void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+  
+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/* SD callback registering/unregistering */
+HAL_StatusTypeDef HAL_SD_RegisterCallback  (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+  
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group4 SD card related functions
+  * @{
+  */
+HAL_StatusTypeDef       HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
+HAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
+  * @{
+  */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+    
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SD_Private_Types SD Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SD_Private_Defines SD Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+          
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SD_Private_Variables SD Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SD_Private_Constants SD Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SD_Private_Macros SD Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* SDMMC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32F7xx_HAL_SD_H */ 
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h
new file mode 100644
index 0000000..a088bc1
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h
@@ -0,0 +1,2419 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_HAL_TIM_H
+#define STM32F7xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                    reaches zero, an update event is generated and counting restarts
+                                    from the RCR value (N).
+                                    This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                     Max_Data = 0xFF.
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                     Max_Data = 0xFFFF. */
+
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+  * @brief  TIM Encoder Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;     /*!< TIM clock filter
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+  * @brief  TIM Clear Input Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source,
+                                      ETR prescaler must be off */
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  * @note   Advanced timers provide TRGO2 internal line which is redirected
+  *         to the ADC
+  */
+typedef struct
+{
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  SlaveMode;         /*!< Slave mode selection
+                                    This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
+  *        filter and polarity.
+  */
+typedef struct
+{
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint32_t LockLevel;            /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
+
+  uint32_t DeadTime;             /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+  uint32_t BreakState;           /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
+
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Break2State;          /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+
+  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
+
+  uint32_t Break2Filter;         /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
+} HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  TIM Channel States definition
+  */
+typedef enum
+{
+  HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
+  HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
+  HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+  * @brief  DMA Burst States definition
+  */
+typedef enum
+{
+  HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
+  HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
+  HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
+  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+  TIM_TypeDef                        *Instance;         /*!< Register base address                             */
+  TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
+  HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
+  DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
+                                                             This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
+  __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
+  __IO HAL_TIM_ChannelStateTypeDef   ChannelState[6];   /*!< TIM channel operation state                       */
+  __IO HAL_TIM_ChannelStateTypeDef   ChannelNState[4];  /*!< TIM complementary channel operation state         */
+  __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
+  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL TIM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                               */
+  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                             */
+  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                 */
+  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                               */
+  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                 */
+  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                               */
+  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                                */
+  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                              */
+  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                          */
+  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                        */
+  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                            */
+  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                          */
+  , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
+  , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
+  , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
+  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
+  , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
+  , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
+  , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
+  , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
+  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
+  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID                         */
+  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
+  , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
+  , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */
+  , HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U   /*!< TIM Commutation half complete Callback ID                  */
+  , HAL_TIM_BREAK_CB_ID                   = 0x1AU   /*!< TIM Break Callback ID                                      */
+  , HAL_TIM_BREAK2_CB_ID                  = 0x1BU   /*!< TIM Break2 Callback ID                                     */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+  * @{
+  */
+#define TIM_DMABASE_CR1                    0x00000000U
+#define TIM_DMABASE_CR2                    0x00000001U
+#define TIM_DMABASE_SMCR                   0x00000002U
+#define TIM_DMABASE_DIER                   0x00000003U
+#define TIM_DMABASE_SR                     0x00000004U
+#define TIM_DMABASE_EGR                    0x00000005U
+#define TIM_DMABASE_CCMR1                  0x00000006U
+#define TIM_DMABASE_CCMR2                  0x00000007U
+#define TIM_DMABASE_CCER                   0x00000008U
+#define TIM_DMABASE_CNT                    0x00000009U
+#define TIM_DMABASE_PSC                    0x0000000AU
+#define TIM_DMABASE_ARR                    0x0000000BU
+#define TIM_DMABASE_RCR                    0x0000000CU
+#define TIM_DMABASE_CCR1                   0x0000000DU
+#define TIM_DMABASE_CCR2                   0x0000000EU
+#define TIM_DMABASE_CCR3                   0x0000000FU
+#define TIM_DMABASE_CCR4                   0x00000010U
+#define TIM_DMABASE_BDTR                   0x00000011U
+#define TIM_DMABASE_DCR                    0x00000012U
+#define TIM_DMABASE_DMAR                   0x00000013U
+#define TIM_DMABASE_OR                     0x00000014U
+#define TIM_DMABASE_CCMR3                  0x00000015U
+#define TIM_DMABASE_CCR5                   0x00000016U
+#define TIM_DMABASE_CCR6                   0x00000017U
+#if   defined(TIM_BREAK_INPUT_SUPPORT)
+#define TIM_DMABASE_AF1                    0x00000018U
+#define TIM_DMABASE_AF2                    0x00000019U
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+  * @{
+  */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+  * @{
+  */
+#define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+  * @{
+  */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+  * @{
+  */
+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+  * @{
+  */
+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+  * @{
+  */
+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+  * @{
+  */
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source
+  * @{
+  */
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
+  * @{
+  */
+#define TIM_CCDMAREQUEST_CC                 0x00000000U                         /*!< CCx DMA request sent when capture or compare match event occurs */
+#define TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS                        /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
+#define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
+#define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
+#define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel TIM Channel
+  * @{
+  */
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
+#define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
+#define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+  * @{
+  */
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+  * @{
+  */
+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+  * @{
+  */
+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+/** @defgroup TIM_Lock_level  TIM Lock level
+  * @{
+  */
+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+  * @{
+  */
+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+  * @{
+  */
+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
+  * @{
+  */
+#define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
+#define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
+  * @{
+  */
+#define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
+#define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+  * @{
+  */
+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
+  * @{
+  */
+#define TIM_GROUPCH5_NONE                  0x00000000U                          /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /*!< OC1REFC is the logical AND of OC1REFC and OC5REF    */
+#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /*!< OC2REFC is the logical AND of OC2REFC and OC5REF    */
+#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /*!< OC3REFC is the logical AND of OC3REFC and OC5REF    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+  * @{
+  */
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
+  * @{
+  */
+#define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
+#define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
+#define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
+#define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+  * @{
+  */
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
+#define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
+#define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
+#define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
+#define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
+#define TIM_OCMODE_ASYMMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
+#define TIM_OCMODE_ASYMMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+  * @{
+  */
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+  * @{
+  */
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+  * @{
+  */
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_System TIM Break System
+  * @{
+  */
+#define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \
+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \
+                                                     } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                     } while(0)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Enable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
+  *       disabled
+  */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+                                                             == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+  *       in an atomic way.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Get update interrupt flag (UIF) copy status.
+  * @param  __COUNTER__ Counter value.
+  * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+  */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__ TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
+  *       or Encoder mode.
+  */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the Prescaler new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+  * @brief  Set the TIM Counter Register value on runtime.
+  * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
+  *      case of 32 bits counter TIM instance.
+  *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+  */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+  do{                                                    \
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  * @retval None
+  */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+  do{                                                   \
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
+  *         function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  do{                                                    \
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
+  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+   ((__HANDLE__)->Instance->CCR6))
+
+/**
+  * @brief  Set the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Reset the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
+  *        overflow/underflow generates an update interrupt or DMA request (if
+  *        enabled)
+  * @retval None
+  */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
+  *        enabled):
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
+  * @retval None
+  */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __POLARITY__ Polarity for TIx source
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+  * @retval None
+  */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+  do{                                                                     \
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+  }while(0)
+
+/** @brief  Select the Capture/compare DMA request source.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __CCDMA__ specifies Capture/compare DMA request source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
+  *            @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
+  * @retval None
+  */
+#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__)    \
+  MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)    || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)    || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)   || \
+                                   ((__BASE__) == TIM_DMABASE_SR)     || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)    || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)   || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)    || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)    || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)    || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)    || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)   || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR)   || \
+                                   ((__BASE__) == TIM_DMABASE_OR)     || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR5)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR6)   || \
+                                   ((__BASE__) == TIM_DMABASE_AF1)    || \
+                                   ((__BASE__) == TIM_DMABASE_AF2))
+#else
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
+                                   ((__BASE__) == TIM_DMABASE_OR)    || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
+                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR6))
+#endif /* TIM_AF1_BKINE && TIM_AF1_BKINE */
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+                                            ((__MODE__) == TIM_UIFREMAP_ENABLE))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
+                                                       ((__CHANNEL__) != (TIM_CHANNEL_5)) && \
+                                                       ((__CHANNEL__) != (TIM_CHANNEL_6)))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
+                                               (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) :        \
+                                               ((__PERIOD__) > 0U))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
+                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
+                                   ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1)    || \
+                                   ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR1)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR2)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR3)    || \
+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1)  || \
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2)  || \
+                                                 ((__SELECTION__) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
+                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
+   (__HANDLE__)->ChannelState[5])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
+   ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
+                                                                       (__HANDLE__)->ChannelState[0]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[1]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[2]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[3]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[4]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[5]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                     } while(0)
+
+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
+   (__HANDLE__)->ChannelNState[3])
+
+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
+   ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
+                                                                         (__HANDLE__)->ChannelNState[0] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[1] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[2] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[3] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                       } while(0)
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32f7xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief   Time Base functions
+  * @{
+  */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief   TIM Output Compare functions
+  * @{
+  */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                       uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief   TIM PWM functions
+  * @{
+  */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                        uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief   TIM Input Capture functions
+  * @{
+  */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief   TIM One Pulse functions
+  * @{
+  */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief   TIM Encoder functions
+  * @{
+  */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief   IRQ handler management
+  * @{
+  */
+/* Interrupt Handler functions  ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief   Peripheral Control functions
+  * @{
+  */
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           const TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, const uint32_t  *BurstBuffer,
+                                              uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                                   uint32_t BurstLength,  uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief   TIM Callbacks functions
+  * @{
+  */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief  Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions  ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F7xx_HAL_TIM_H */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
new file mode 100644
index 0000000..11b372f
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
@@ -0,0 +1,360 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_HAL_TIM_EX_H
+#define STM32F7xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/**
+  * @brief  TIM Break/Break2 input configuration
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
+                                Not relevant when analog watchdog output of the DFSDM1 used as break input source */
+} TIMEx_BreakInputConfigTypeDef;
+
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+  * @{
+  */
+#define TIM_TIM2_TIM8_TRGO                     (0x00000000U)
+#define TIM_TIM2_ETH_PTP                       (0x00000400U)
+#define TIM_TIM2_USBFS_SOF                     (0x00000800U)
+#define TIM_TIM2_USBHS_SOF                     (0x00000C00U)
+#define TIM_TIM5_GPIO                          (0x00000000U)
+#define TIM_TIM5_LSI                           (0x00000040U)
+#define TIM_TIM5_LSE                           (0x00000080U)
+#define TIM_TIM5_RTC                           (0x000000C0U)
+#define TIM_TIM11_GPIO                         (0x00000000U)
+#define TIM_TIM11_SPDIFRX                      (0x00000001U)
+#define TIM_TIM11_HSE                          (0x00000002U)
+#define TIM_TIM11_MCO1                         (0x00000003U)
+/**
+  * @}
+  */
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
+  * @{
+  */
+#define TIM_BREAKINPUT_BRK     0x00000001U                                      /*!< Timer break input  */
+#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /*!< Timer break2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_BKIN     (0x00000001U)                  /*!< An external source (GPIO) is connected to the BKIN pin  */
+#define TIM_BREAKINPUTSOURCE_DFSDM1   (0x00000008U)                  /*!< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /*!< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /*!< Break input source is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /*!< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /*!< Break input source is active_high */
+/**
+  * @}
+  */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#define IS_TIM_REMAP(__TIM_REMAP__)  (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\
+                                      ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)  ||\
+                                      ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\
+                                      ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\
+                                      ((__TIM_REMAP__) == TIM_TIM5_GPIO)     ||\
+                                      ((__TIM_REMAP__) == TIM_TIM5_LSI)      ||\
+                                      ((__TIM_REMAP__) == TIM_TIM5_LSE)      ||\
+                                      ((__TIM_REMAP__) == TIM_TIM5_RTC)      ||\
+                                      ((__TIM_REMAP__) == TIM_TIM11_GPIO)    ||\
+                                      ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX) ||\
+                                      ((__TIM_REMAP__) == TIM_TIM11_HSE)     ||\
+                                      ((__TIM_REMAP__) == TIM_TIM11_MCO1))
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))
+
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  *  @brief    Timer Hall Sensor functions
+  * @{
+  */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  * @{
+  */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                          uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  *  @brief    Timer Complementary PWM functions
+  * @{
+  */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                           uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  *  @brief    Timer Complementary One Pulse functions
+  * @{
+  */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+                                             const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
+  * @{
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32F7xx_HAL_TIM_EX_H */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h
new file mode 100644
index 0000000..55a34ae
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h
@@ -0,0 +1,4730 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_LL_ADC_H
+#define __STM32F7xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3)
+
+/** @defgroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Internal mask for ADC group regular sequencer:                             */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
+/* - sequencer register offset                                                */
+/* - sequencer rank bits position into the selected register                  */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET                 0x00000000U
+#define ADC_SQR2_REGOFFSET                 0x00000100U
+#define ADC_SQR3_REGOFFSET                 0x00000200U
+#define ADC_SQR4_REGOFFSET                 0x00000300U
+
+#define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted  */
+/* into ADC group regular sequencer ranks literals definition.                */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
+
+/* Internal mask for ADC group injected sequencer:                            */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
+/* - data register offset                                                     */
+/* - offset register offset                                                   */
+/* - sequencer rank bits position into the selected register                  */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET                 0x00000000U
+#define ADC_JDR2_REGOFFSET                 0x00000100U
+#define ADC_JDR3_REGOFFSET                 0x00000200U
+#define ADC_JDR4_REGOFFSET                 0x00000300U
+
+/* Internal register offset for ADC group injected offset configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JOFR1_REGOFFSET                0x00000000U
+#define ADC_JOFR2_REGOFFSET                0x00001000U
+#define ADC_JOFR3_REGOFFSET                0x00002000U
+#define ADC_JOFR4_REGOFFSET                0x00003000U
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_JOFRX_REGOFFSET_MASK       (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Internal mask for ADC group regular trigger:                               */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
+/* - regular trigger source                                                   */
+/* - regular trigger edge                                                     */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
+                                             ((ADC_CR2_EXTSEL)                            >> (4U * 1U)) | \
+                                             ((ADC_CR2_EXTSEL)                            >> (4U * 2U)) | \
+                                             ((ADC_CR2_EXTSEL)                            >> (4U * 3U)))
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 1U)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 2U)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 3U)))
+
+/* Definition of ADC group regular trigger bits information.                  */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
+
+
+
+/* Internal mask for ADC group injected trigger:                              */
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
+/* - injected trigger source                                                  */
+/* - injected trigger edge                                                    */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
+                                             ((ADC_CR2_JEXTSEL)                            >> (4U * 1U)) | \
+                                             ((ADC_CR2_JEXTSEL)                            >> (4U * 2U)) | \
+                                             ((ADC_CR2_JEXTSEL)                            >> (4U * 3U)))
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 1U)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 2U)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 3U)))
+
+/* Definition of ADC group injected trigger bits information.                 */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
+
+/* Internal mask for ADC channel:                                             */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
+/* - channel identifier defined by number                                     */
+/* - channel differentiation between external channels (connected to          */
+/*   GPIO pins) and internal channels (connected to internal paths)           */
+/* - channel sampling time defined by SMPRx register offset                   */
+/*   and SMPx bits positions into SMPRx register                              */
+#define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CR1_AWDCH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH         0x80000000U   /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2       0x40000000U   /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
+#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U  /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET                0x00000000U
+#define ADC_SMPR2_REGOFFSET                0x02000000U
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK    0x01F00000U
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
+
+/* Definition of channels ID number information to be inserted into           */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_NUMBER               0x00000000U
+#define ADC_CHANNEL_1_NUMBER               (                                                                        ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_2_NUMBER               (                                                      ADC_CR1_AWDCH_1                  )
+#define ADC_CHANNEL_3_NUMBER               (                                                      ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_4_NUMBER               (                                    ADC_CR1_AWDCH_2                                    )
+#define ADC_CHANNEL_5_NUMBER               (                                    ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_6_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
+#define ADC_CHANNEL_7_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_8_NUMBER               (                  ADC_CR1_AWDCH_3                                                      )
+#define ADC_CHANNEL_9_NUMBER               (                  ADC_CR1_AWDCH_3                                     | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_10_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1                  )
+#define ADC_CHANNEL_11_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_12_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                                    )
+#define ADC_CHANNEL_13_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_14_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
+#define ADC_CHANNEL_15_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_16_NUMBER              (ADC_CR1_AWDCH_4                                                                        )
+#define ADC_CHANNEL_17_NUMBER              (ADC_CR1_AWDCH_4                                                       | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_18_NUMBER              (ADC_CR1_AWDCH_4                                     | ADC_CR1_AWDCH_1                  )
+
+/* Definition of channels sampling time information to be inserted into       */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_SMP                  (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
+#define ADC_CHANNEL_1_SMP                  (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
+#define ADC_CHANNEL_2_SMP                  (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
+#define ADC_CHANNEL_3_SMP                  (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
+#define ADC_CHANNEL_4_SMP                  (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
+#define ADC_CHANNEL_5_SMP                  (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
+#define ADC_CHANNEL_6_SMP                  (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
+#define ADC_CHANNEL_7_SMP                  (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
+#define ADC_CHANNEL_8_SMP                  (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
+#define ADC_CHANNEL_9_SMP                  (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
+#define ADC_CHANNEL_10_SMP                 (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
+#define ADC_CHANNEL_11_SMP                 (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
+#define ADC_CHANNEL_12_SMP                 (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
+#define ADC_CHANNEL_13_SMP                 (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
+#define ADC_CHANNEL_14_SMP                 (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
+#define ADC_CHANNEL_15_SMP                 (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
+#define ADC_CHANNEL_16_SMP                 (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
+#define ADC_CHANNEL_17_SMP                 (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
+#define ADC_CHANNEL_18_SMP                 (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
+
+/* Internal mask for ADC analog watchdog:                                     */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
+/* (concatenation of multiple bits used in different analog watchdogs,        */
+/* (feature of several watchdogs not available on all STM32 families)).       */
+/* - analog watchdog 1: monitored channel defined by number,                  */
+/*   selection of ADC group (ADC groups regular and-or injected).             */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET              0x00000000U
+
+#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK)
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_HIGH_REGOFFSET         0x00000000U
+#define ADC_AWD_TR1_LOW_REGOFFSET          0x00000001U
+#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
+
+/* ADC registers bits positions */
+#define ADC_CR1_RES_BITOFFSET_POS          (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
+#define ADC_TR_HT_BITOFFSET_POS            (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR                   VREFINT_CAL_ADDR_CMSIS      /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF                   ( 3300U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR               TEMPSENSOR_CAL1_ADDR_CMSIS  /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR               TEMPSENSOR_CAL2_ADDR_CMSIS  /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG          ( 3300U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Driver macro reserved for internal use: isolate bits with the
+  *         selected mask and shift them to the register LSB
+  *         (shift mask on register position bit 0).
+  * @param  __BITS__ Bits in register 32 bits
+  * @param  __MASK__ Mask in register 32 bits
+  * @retval Bits in register 32 bits
+  */
+#define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \
+  (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+  * @brief  Driver macro reserved for internal use: set a pointer to
+  *         a register from a register basis from which an offset
+  *         is applied.
+  * @param  __REG__ Register basis from which the offset is applied.
+  * @param  __REG_OFFFSET__ Offset to be applied (unit number of registers).
+  * @retval Pointer to register address
+  */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of ADC common parameters
+  *         and multimode
+  *         (all ADC instances belonging to the same ADC common instance).
+  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
+  *         is conditioned to ADC instances state (all ADC instances
+  *         sharing the same ADC common instance):
+  *         All ADC instances sharing the same ADC common instance must be
+  *         disabled.
+  */
+typedef struct
+{
+  uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
+                                             This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
+
+  uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
+
+  uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
+
+  uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Affects both group regular and group injected (availability
+  *         of ADC group injected depends on STM32 families).
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t Resolution;                  /*!< Set ADC resolution.
+                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
+
+  uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
+                                             This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+
+  uint32_t SequencersScanMode;          /*!< Set ADC scan selection.
+                                             This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+                                             @note On this STM32 series, setting of external trigger edge is performed
+                                                   using function @ref LL_ADC_REG_StartConversionExtTrig().
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+
+  uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+                                             @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group regular sequencer is enabled
+                                                   (scan length of 2 ranks or more).
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+                                             Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
+
+  uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group injected.
+  * @note   These parameters have an impact on ADC scope: ADC group injected.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "INJ").
+  * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+                                             @note On this STM32 series, setting of external trigger edge is performed
+                                                   using function @ref LL_ADC_INJ_StartConversionExtTrig().
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
+
+  uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+                                             @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group injected sequencer is enabled
+                                                   (scan length of 2 ranks or more).
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+  uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+                                             Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. 
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+  * @brief    Flags defines which can be used with LL_ADC_ReadReg function
+  * @{
+  */
+#define LL_ADC_FLAG_STRT                   ADC_SR_STRT        /*!< ADC flag ADC group regular conversion start */
+#define LL_ADC_FLAG_EOCS                   ADC_SR_EOC         /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
+#define LL_ADC_FLAG_OVR                    ADC_SR_OVR         /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_JSTRT                  ADC_SR_JSTRT       /*!< ADC flag ADC group injected conversion start */
+#define LL_ADC_FLAG_JEOS                   ADC_SR_JEOC        /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_AWD1                   ADC_SR_AWD         /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_EOCS_MST               ADC_CSR_EOC1       /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
+#define LL_ADC_FLAG_EOCS_SLV1              ADC_CSR_EOC2       /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
+#define LL_ADC_FLAG_EOCS_SLV2              ADC_CSR_EOC3       /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
+#define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR1    /*!< ADC flag ADC multimode master group regular overrun */ 
+#define LL_ADC_FLAG_OVR_SLV1               ADC_CSR_OVR2   /*!< ADC flag ADC multimode slave 1 group regular overrun */
+#define LL_ADC_FLAG_OVR_SLV2               ADC_CSR_OVR3   /*!< ADC flag ADC multimode slave 2 group regular overrun */
+#define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOC1     /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_JEOS_SLV1              ADC_CSR_JEOC2  /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_JEOS_SLV2              ADC_CSR_JEOC3  /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1       /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV1              ADC_CSR_AWD2       /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
+#define LL_ADC_FLAG_AWD1_SLV2              ADC_CSR_AWD3       /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
+  * @{
+  */
+#define LL_ADC_IT_EOCS                     ADC_CR1_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
+#define LL_ADC_IT_OVR                      ADC_CR1_OVRIE      /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_JEOS                     ADC_CR1_JEOCIE     /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_IT_AWD1                     ADC_CR1_AWDIE      /*!< ADC interruption ADC analog watchdog 1 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
+  * @{
+  */
+/* List of ADC registers intended to be used (most commonly) with             */
+/* DMA transfer.                                                              */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
+#define LL_ADC_DMA_REG_REGULAR_DATA          0x00000000U   /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    0x00000001U   /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
+  * @{
+  */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2        0x00000000U                                           /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (                   ADC_CCR_ADCPRE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV6        (ADC_CCR_ADCPRE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV8        (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
+  * @{
+  */
+/* Note: Other measurement paths to internal channels may be available        */
+/*       (connections to other peripherals).                                  */
+/*       If they are not listed below, they do not require any specific       */
+/*       path enable. In this case, Access to measurement path is done        */
+/*       only by selecting the corresponding ADC internal channel.            */
+#define LL_ADC_PATH_INTERNAL_NONE          0x00000000U            /*!< ADC measurement paths all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATE)        /*!< ADC measurement path to internal channel Vbat */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
+  * @{
+  */
+#define LL_ADC_RESOLUTION_12B              0x00000000U                         /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B              (                ADC_CR1_RES_0)     /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B               (ADC_CR1_RES_1                )     /*!< ADC resolution  8 bits */
+#define LL_ADC_RESOLUTION_6B               (ADC_CR1_RES_1 | ADC_CR1_RES_0)     /*!< ADC resolution  6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
+  * @{
+  */
+#define LL_ADC_DATA_ALIGN_RIGHT            0x00000000U            /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT             (ADC_CR2_ALIGN)        /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
+  * @{
+  */
+#define LL_ADC_SEQ_SCAN_DISABLE            0x00000000U    /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
+#define LL_ADC_SEQ_SCAN_ENABLE             (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
+  * @{
+  */
+#define LL_ADC_GROUP_REGULAR               0x00000001U   /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED              0x00000002U   /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED      0x00000003U   /*!< ADC both groups regular and injected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
+  * @{
+  */
+#define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
+#define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
+#define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
+#define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
+#define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
+#define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
+#define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
+#define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
+#define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
+#define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
+#define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F7, ADC channel available only on ADC instance: ADC1. */
+#define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F7, ADC channel available only on ADC instance: ADC1. */
+#define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F7, ADC channel available only on ADC instance: ADC1. */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
+  * @{
+  */
+#define LL_ADC_REG_TRIG_SOFTWARE           0x00000000U                                                                                                 /*!< ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1       ((uint32_t)ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM5_TRGO      (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                    /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                    /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CR2_EXTSEL_3 |ADC_CR2_EXTSEL_2| ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
+  * @{
+  */
+#define LL_ADC_REG_TRIG_EXT_RISING         (                  ADC_CR2_EXTEN_0)     /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CR2_EXTEN_1                  )     /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0)     /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
+* @{
+*/
+#define LL_ADC_REG_CONV_SINGLE             0x00000000U             /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CR2_CONT)          /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
+  * @{
+  */
+#define LL_ADC_REG_DMA_TRANSFER_NONE       0x00000000U              /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (              ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CR2_DDS | ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
+  * @{
+  */
+#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV       0x00000000U    /*!< ADC flag EOC (end of unitary conversion) selected */
+#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV        (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
+  * @{
+  */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE        0x00000000U                                                 /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE     0x00000000U                                                                  /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                            ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                        ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                    ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                    ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CR1_DISCNUM_2                                         | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CR1_DISCNUM_2                     | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+  * @{
+  */
+#define LL_ADC_REG_RANK_1                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_SOFTWARE           0x00000000U                                                                                                     /*!< ADC group injected conversion trigger internal: SW start. */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_EXT_RISING         (                   ADC_CR2_JEXTEN_0)   /*!< ADC group injected conversion trigger polarity set to rising edge */
+#define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_CR2_JEXTEN_1                   )   /*!< ADC group injected conversion trigger polarity set to falling edge */
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0)   /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
+* @{
+*/
+#define LL_ADC_INJ_TRIG_INDEPENDENT        0x00000000U            /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CR1_JAUTO)        /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
+  * @{
+  */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE        0x00000000U                     /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE     0x00000000U            /*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CR1_JDISCEN)      /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
+  * @{
+  */
+#define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+  * @{
+  */
+#define LL_ADC_SAMPLINGTIME_3CYCLES        0x00000000U                                              /*!< Sampling time 3 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_15CYCLES       (ADC_SMPR1_SMP10_0)                                      /*!< Sampling time 15 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_28CYCLES       (ADC_SMPR1_SMP10_1)                                      /*!< Sampling time 28 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_56CYCLES       (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)                  /*!< Sampling time 56 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_84CYCLES       (ADC_SMPR1_SMP10_2)                                      /*!< Sampling time 84 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_112CYCLES      (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)                  /*!< Sampling time 112 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_144CYCLES      (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)                  /*!< Sampling time 144 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_480CYCLES      (ADC_SMPR1_SMP10)                                        /*!< Sampling time 480 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+  * @{
+  */
+#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
+  * @{
+  */
+#define LL_ADC_AWD_DISABLE                 0x00000000U                                                                                   /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                             ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ        (                                            ADC_CR1_JAWDEN                                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (                                            ADC_CR1_JAWDEN | ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
+#define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
+  * @{
+  */
+#define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW           (ADC_AWD_TR1_LOW_REGOFFSET)  /*!< ADC analog watchdog threshold low */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
+  * @{
+  */
+#define LL_ADC_MULTI_INDEPENDENT           0x00000000U                                                             /*!< ADC dual mode disabled (ADC independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT       (                  ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1                  ) /*!< ADC dual mode enabled: group regular simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL       (                  ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                  ADC_CCR_MULTI_2                   | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_MULTI_3                                     | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                      ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                    ADC_CCR_MULTI_1                  ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                    ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
+#if defined(ADC3)
+#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM  (ADC_CCR_MULTI_4                                                       | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT  (ADC_CCR_MULTI_4                                     | ADC_CCR_MULTI_1                  ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_TRIPLE_INJ_SIMULT       (ADC_CCR_MULTI_4                   | ADC_CCR_MULTI_2                   | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */
+#define LL_ADC_MULTI_TRIPLE_REG_SIMULT       (ADC_CCR_MULTI_4                   | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1                  ) /*!< ADC triple mode enabled: group regular simultaneous */
+#define LL_ADC_MULTI_TRIPLE_REG_INTERL       (ADC_CCR_MULTI_4                   | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */
+#define LL_ADC_MULTI_TRIPLE_INJ_ALTERN       (ADC_CCR_MULTI_4                                                       | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer
+  * @{
+  */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC        0x00000000U                                   /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_1         (                              ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_2         (              ADC_CCR_DMA_1                ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_3         (              ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_1         (ADC_CCR_DDS |                 ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_2         (ADC_CCR_DDS | ADC_CCR_DMA_1                ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_3         (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
+  * @{
+  */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  0x00000000U                                                             /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3                                     | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
+  * @{
+  */
+#define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
+#define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
+  * @note   Only ADC IP HW delays are defined in ADC LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+  
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
+/*       not timeout values.                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Indications for estimation of ADC timeout delays, for this           */
+/*       STM32 series:                                                         */
+/*       - ADC enable time: maximum delay is 2us                              */
+/*         (refer to device datasheet, parameter "tSTAB")                     */
+/*       - ADC conversion time: duration depending on ADC clock and ADC       */
+/*         configuration.                                                     */
+/*         (refer to device reference manual, section "Timing")               */
+
+/* Delay for internal voltage reference stabilization time.                   */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_VREFINT_STAB_US       (  10U)  /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay for temperature sensor stabilization time.                           */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    (  10U)  /*!< Delay for internal voltage reference stabilization time */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+  * @{
+  */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get ADC channel number in decimal format
+  *         from literals LL_ADC_CHANNEL_x.
+  * @note   Example:
+  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+  *           will return decimal number "4".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned, either defined with number
+  *         or with bitfield (only one bit must be set).
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+  * @retval Value between Min_Data=0 and Max_Data=18
+  */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
+  (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+
+/**
+  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+  *         from number in decimal format.
+  * @note   Example:
+  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+  *           will return a data equivalent to "LL_ADC_CHANNEL_4".
+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
+  *         (1) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                          \
+  (((__DECIMAL_NB__) <= 9U)                                                                                     \
+    ? (                                                                                                         \
+       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \
+       (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \
+      )                                                                                                         \
+      :                                                                                                         \
+      (                                                                                                         \
+       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \
+       (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+      )                                                                                                         \
+  )
+
+/**
+  * @brief  Helper macro to determine whether the selected channel
+  *         corresponds to literal definitions of driver.
+  * @note   The different literal definitions of ADC channels are:
+  *         - ADC internal channel:
+  *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+  *         - ADC external channel (channel connected to a GPIO pin):
+  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+  * @note   The channel parameter must be a value defined from literal
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+  *         must not be a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+  */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
+  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
+
+/**
+  * @brief  Helper macro to convert a channel defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         to its equivalent parameter definition of a ADC external channel
+  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+  * @note   The channel parameter can be, additionally to a value
+  *         defined from parameter definition of a ADC internal channel
+  *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is returned
+  *         from ADC registers.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
+  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+  * @brief  Helper macro to determine whether the internal channel
+  *         selected is available on the ADC instance selected.
+  * @note   The channel parameter must be a value defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         must not be a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.
+  *         (2) On devices STM32F7x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+  *         Value "1" if the internal channel selected is available on the ADC instance selected.
+  */
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  (                                                                            \
+   ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                             \
+   ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                      \
+  )
+/**
+  * @brief  Helper macro to define ADC analog watchdog parameter:
+  *         define a single channel to monitor with analog watchdog
+  *         from sequencer channel and groups definition.
+  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+  *         Example:
+  *           LL_ADC_SetAnalogWDMonitChannels(
+  *             ADC1, LL_ADC_AWD1,
+  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
+  *         (1) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  * @param  __GROUP__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_GROUP_REGULAR
+  *         @arg @ref LL_ADC_GROUP_INJECTED
+  *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (1)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (1)(2)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (1)(2)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (1)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (1)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (1)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+  */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
+  (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
+    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)                            \
+      :                                                                                                   \
+      ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
+       ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)                        \
+         :                                                                                                \
+         (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)        \
+  )
+
+/**
+  * @brief  Helper macro to set the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to set the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           LL_ADC_SetAnalogWDThresholds
+  *            (< ADCx param >,
+  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, )
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is 
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to get the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+  *            (LL_ADC_RESOLUTION_8B,
+  *             LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the ADC multimode conversion data of ADC master
+  *         or ADC slave from raw value with both ADC conversion data concatenated.
+  * @note   This macro is intended to be used when multimode transfer by DMA
+  *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+  *         In this case the transferred data need to processed with this macro
+  *         to separate the conversion data of ADC master and ADC slave.
+  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
+  (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
+
+/**
+  * @brief  Helper macro to select the ADC common instance
+  *         to which is belonging the selected ADC instance.
+  * @note   ADC common register instance can be used for:
+  *         - Set parameters common to several ADC instances
+  *         - Multimode (for devices with several ADC instances)
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @param  __ADCx__ ADC instance
+  * @retval ADC common register instance
+  */
+#if defined(ADC1) && defined(ADC2) && defined(ADC3)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+  (ADC123_COMMON)
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+  (ADC12_COMMON)
+#else
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+  (ADC1_COMMON)
+#endif
+
+/**
+  * @brief  Helper macro to check if all ADC instances sharing the same
+  *         ADC common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @note   On devices with only 1 ADC common instance, parameter of this macro
+  *         is useless and can be ignored (parameter kept for compatibility
+  *         with devices featuring several ADC common instances).
+  * @param  __ADCXY_COMMON__ ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value "0" if all ADC instances sharing the same ADC common instance
+  *         are disabled.
+  *         Value "1" if at least one ADC instance sharing the same ADC common instance
+  *         is enabled.
+  */
+#if defined(ADC1) && defined(ADC2) && defined(ADC3)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (LL_ADC_IsEnabled(ADC1) |                                                    \
+   LL_ADC_IsEnabled(ADC2) |                                                    \
+   LL_ADC_IsEnabled(ADC3)  )
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (LL_ADC_IsEnabled(ADC1) |                                                    \
+   LL_ADC_IsEnabled(ADC2)  )
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (LL_ADC_IsEnabled(ADC1))
+#endif
+
+/**
+  * @brief  Helper macro to define the ADC conversion data full-scale digital
+  *         value corresponding to the selected ADC resolution.
+  * @note   ADC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+  (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
+
+/**
+  * @brief  Helper macro to convert the ADC conversion data from
+  *         a resolution to another resolution.
+  * @param  __DATA__ ADC conversion data to be converted 
+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data to the requested resolution
+  */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
+  (((__DATA__)                                                                 \
+    << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))     \
+   >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))        \
+  )
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                      __ADC_DATA__,\
+                                      __ADC_RESOLUTION__)                      \
+  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
+   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
+  )
+
+/**
+  * @brief  Helper macro to calculate analog reference voltage (Vref+)
+  *         (unit: mVolt) from ADC conversion data of internal voltage
+  *         reference VrefInt.
+  * @note   Computation is using VrefInt calibration value
+  *         stored in system memory for each device during production.
+  * @note   This voltage depends on user board environment: voltage level
+  *         connected to pin Vref+.
+  *         On devices with small package, the pin Vref+ is not present
+  *         and internally bonded to pin Vdda.
+  * @note   On this STM32 series, calibration data of internal voltage reference
+  *         VrefInt corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         internal voltage reference VrefInt.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *         of internal voltage reference VrefInt (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Analog reference voltage (unit: mV)
+  */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+                                         __ADC_RESOLUTION__)                   \
+  (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
+    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \
+                                       (__ADC_RESOLUTION__),                   \
+                                       LL_ADC_RESOLUTION_12B)                  \
+  )
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor calibration values
+  *         stored in system memory for each device during production.
+  * @note   Calculation formula:
+  *           Temperature = ((TS_ADC_DATA - TS_CAL1)
+  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
+  *                Avg_Slope = (TS_CAL2 - TS_CAL1)
+  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL1 (calibrated in factory)
+  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL2 (calibrated in factory)
+  *         Caution: Calculation relevancy under reserve that calibration
+  *                  parameters are correct (address and data).
+  *                  To calculate temperature using temperature sensor
+  *                  datasheet typical values (generic values less, therefore
+  *                  less accurate than calibrated values),
+  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   On this STM32 series, calibration data of temperature sensor
+  *         corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         temperature sensor.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit mV)
+  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+  *                                 temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
+  *                                 sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+                                  __TEMPSENSOR_ADC_DATA__,\
+                                  __ADC_RESOLUTION__)                              \
+  (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
+                                                    (__ADC_RESOLUTION__),          \
+                                                    LL_ADC_RESOLUTION_12B)         \
+                   * (__VREFANALOG_VOLTAGE__))                                     \
+                  / TEMPSENSOR_CAL_VREFANALOG)                                     \
+        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
+     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
+    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+   ) + TEMPSENSOR_CAL1_TEMP                                                        \
+  )
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor typical values
+  *         (refer to device datasheet).
+  * @note   Calculation formula:
+  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+  *                         / Avg_Slope + CALx_TEMP
+  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
+  *                                   (unit: digital value)
+  *                Avg_Slope        = temperature sensor slope
+  *                                   (unit: uV/Degree Celsius)
+  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
+  *                                   temperature CALx_TEMP (unit: mV)
+  *         Caution: Calculation relevancy under reserve the temperature sensor
+  *                  of the current device has characteristics in line with
+  *                  datasheet typical values.
+  *                  If temperature sensor calibration values are available on
+  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+  *                  temperature calculation will be more accurate using
+  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   ADC measurement data must correspond to a resolution of 12bits
+  *         (full scale digital value 4095). If not the case, the data must be
+  *         preliminarily rescaled to an equivalent resolution of 12 bits.
+  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius).
+  *                                       On STM32F7, refer to device datasheet parameter "Avg_Slope".
+  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV).
+  *                                       On STM32F4, refer to device datasheet parameter "V25".
+  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV)
+  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit mV)
+  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit digital value).
+  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+                                             __TEMPSENSOR_TYP_CALX_V__,\
+                                             __TEMPSENSOR_CALX_TEMP__,\
+                                             __VREFANALOG_VOLTAGE__,\
+                                             __TEMPSENSOR_ADC_DATA__,\
+                                             __ADC_RESOLUTION__)               \
+  ((( (                                                                        \
+       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
+                 * 1000)                                                       \
+       -                                                                       \
+       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
+                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
+                 * 1000)                                                       \
+      )                                                                        \
+    ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
+   ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
+  )
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+  * @{
+  */
+/* Note: LL ADC functions to set DMA transfer are located into sections of    */
+/*       configuration of ADC instance, groups and multimode (if available):  */
+/*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
+
+/**
+  * @brief  Function to help to configure DMA transfer from ADC: retrieve the
+  *         ADC register address from ADC instance and a list of ADC registers
+  *         intended to be used (most commonly) with DMA transfer.
+  * @note   These ADC registers are data registers:
+  *         when ADC conversion data is available in ADC data registers,
+  *         ADC generates a DMA transfer request.
+  * @note   This macro is intended to be used with LL DMA driver, refer to
+  *         function "LL_DMA_ConfigAddresses()".
+  *         Example:
+  *           LL_DMA_ConfigAddresses(DMA1,
+  *                                  LL_DMA_CHANNEL_1,
+  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+  *                                  (uint32_t)&< array or variable >,
+  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+  * @note   For devices with several ADC: in multimode, some devices
+  *         use a different data register outside of ADC instance scope
+  *         (common data register). This macro manages this register difference,
+  *         only ADC instance has to be set as parameter.
+  * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
+  *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
+  *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
+  * @param  ADCx ADC instance
+  * @param  Register This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+  *         
+  *         (1) Available on devices with several ADC instances.
+  * @retval ADC register address
+  */
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+  uint32_t data_reg_addr = 0U;
+  
+  if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+  {
+    /* Retrieve address of register DR */
+    data_reg_addr = (uint32_t)&(ADCx->DR);
+  }
+  else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+  {
+    /* Retrieve address of register CDR */
+    data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+  }
+  
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+  * @{
+  */
+
+/**
+  * @brief  Set parameter common to several ADC: Clock source and prescaler.
+  * @rmtoll CCR      ADCPRE         LL_ADC_SetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  CommonClock This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: Clock source and prescaler.
+  * @rmtoll CCR      ADCPRE         LL_ADC_GetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to internal
+  *         channels (VrefInt, temperature sensor, ...).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @rmtoll CCR      TSVREFE        LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      VBATE          LL_ADC_SetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: measurement path to internal
+  *         channels (VrefInt, temperature sensor, ...).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @rmtoll CCR      TSVREFE        LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      VBATE          LL_ADC_GetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Set ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CR1      RES            LL_ADC_SetResolution
+  * @param  ADCx ADC instance
+  * @param  Resolution This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+  MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
+}
+
+/**
+  * @brief  Get ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CR1      RES            LL_ADC_GetResolution
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
+}
+
+/**
+  * @brief  Set ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment
+  * @param  ADCx ADC instance
+  * @param  DataAlignment This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+  MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
+}
+
+/**
+  * @brief  Get ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
+}
+
+/**
+  * @brief  Set ADC sequencers scan mode, for all ADC groups
+  *         (group regular, group injected).
+  * @note  According to sequencers scan mode :
+  *         - If disabled: ADC conversion is performed in unitary conversion
+  *           mode (one channel converted, that defined in rank 1).
+  *           Configuration of sequencers of all ADC groups
+  *           (sequencer scan length, ...) is discarded: equivalent to
+  *           scan length of 1 rank.
+  *         - If enabled: ADC conversions are performed in sequence conversions
+  *           mode, according to configuration of sequencers of
+  *           each ADC group (sequencer scan length, ...).
+  *           Refer to function @ref LL_ADC_REG_SetSequencerLength()
+  *           and to function @ref LL_ADC_INJ_SetSequencerLength().
+  * @rmtoll CR1      SCAN           LL_ADC_SetSequencersScanMode
+  * @param  ADCx ADC instance
+  * @param  ScanMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
+{
+  MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
+}
+
+/**
+  * @brief  Get ADC sequencers scan mode, for all ADC groups
+  *         (group regular, group injected).
+  * @note  According to sequencers scan mode :
+  *         - If disabled: ADC conversion is performed in unitary conversion
+  *           mode (one channel converted, that defined in rank 1).
+  *           Configuration of sequencers of all ADC groups
+  *           (sequencer scan length, ...) is discarded: equivalent to
+  *           scan length of 1 rank.
+  *         - If enabled: ADC conversions are performed in sequence conversions
+  *           mode, according to configuration of sequencers of
+  *           each ADC group (sequencer scan length, ...).
+  *           Refer to function @ref LL_ADC_REG_SetSequencerLength()
+  *           and to function @ref LL_ADC_INJ_SetSequencerLength().
+  * @rmtoll CR1      SCAN           LL_ADC_GetSequencersScanMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group regular conversion trigger source:
+  *         internal (SW start) or from external IP (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 series, setting of external trigger edge is performed
+  *         using function @ref LL_ADC_REG_StartConversionExtTrig().
+  * @note   Availability of parameters of trigger sources from timer 
+  *         depends on timers availability on the selected device.
+  * @rmtoll CR2      EXTSEL         LL_ADC_REG_SetTriggerSource\n
+  *         CR2      EXTEN          LL_ADC_REG_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+/* Note: On this STM32 series, ADC group regular external trigger edge        */
+/*       is used to perform a ADC conversion start.                           */
+/*       This function does not set external trigger edge.                    */
+/*       This feature is set using function                                   */
+/*       @ref LL_ADC_REG_StartConversionExtTrig().                            */
+  MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source:
+  *         internal (SW start) or from external IP (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group regular trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to 
+  *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer 
+  *         depends on timers availability on the selected device.
+  * @rmtoll CR2      EXTSEL         LL_ADC_REG_GetTriggerSource\n
+  *         CR2      EXTEN          LL_ADC_REG_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+  uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
+  
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}.                             */
+  uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
+  
+  /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL           */
+  /* to match with triggers literals definition.                              */
+  return ((TriggerSource
+           & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
+          | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source internal (SW start)
+            or external.
+  * @note   In case of group regular trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_REG_GetTriggerSource().
+  * @rmtoll CR2      EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @note   On this STM32 series, setting of external trigger edge is performed
+  *         using function @ref LL_ADC_REG_StartConversionExtTrig().
+  * @rmtoll CR2      EXTEN          LL_ADC_REG_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
+}
+
+
+/**
+  * @brief  Set ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  * @note   On this STM32 series, group regular sequencer configuration
+  *         is conditioned to ADC instance sequencer mode.
+  *         If ADC instance sequencer mode is disabled, sequencers of
+  *         all groups (group regular, group injected) can be configured
+  *         but their execution is disabled (limited to rank 1).
+  *         Refer to function @ref LL_ADC_SetSequencersScanMode().
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+  MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  * @note   On this STM32 series, group regular sequencer configuration
+  *         is conditioned to ADC instance sequencer mode.
+  *         If ADC instance sequencer mode is disabled, sequencers of
+  *         all groups (group regular, group injected) can be configured
+  *         but their execution is disabled (limited to rank 1).
+  *         Refer to function @ref LL_ADC_SetSequencersScanMode().
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+  * @brief  Set ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group regular 
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   It is not possible to enable both ADC auto-injected mode
+  *         and ADC group regular sequencer discontinuous mode.
+  * @rmtoll CR1      DISCEN         LL_ADC_REG_SetSequencerDiscont\n
+  *         CR1      DISCNUM        LL_ADC_REG_SetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont\n
+  *         CR1      DISCNUM        LL_ADC_REG_GetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
+}
+
+/**
+  * @brief  Set ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   This function performs configuration of:
+  *         - Channels ordering into each rank of scan sequence:
+  *           whatever channel can be placed into whatever rank.
+  * @note   On this STM32 series, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @rmtoll SQR3     SQ1            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ2            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ3            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ4            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ5            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ6            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ10           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ11           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ12           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ13           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ14           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ15           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ16           LL_ADC_REG_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  *         @arg @ref LL_ADC_REG_RANK_9
+  *         @arg @ref LL_ADC_REG_RANK_10
+  *         @arg @ref LL_ADC_REG_RANK_11
+  *         @arg @ref LL_ADC_REG_RANK_12
+  *         @arg @ref LL_ADC_REG_RANK_13
+  *         @arg @ref LL_ADC_REG_RANK_14
+  *         @arg @ref LL_ADC_REG_RANK_15
+  *         @arg @ref LL_ADC_REG_RANK_16
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register and register position depending on parameter "Rank".         */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+  
+  MODIFY_REG(*preg,
+             ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+             (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+
+/**
+  * @brief  Get ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   On this STM32 series, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll SQR3     SQ1            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ2            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ3            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ4            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ5            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ6            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ10           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ11           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ12           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ13           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ14           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ15           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ16           LL_ADC_REG_GetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  *         @arg @ref LL_ADC_REG_RANK_9
+  *         @arg @ref LL_ADC_REG_RANK_10
+  *         @arg @ref LL_ADC_REG_RANK_11
+  *         @arg @ref LL_ADC_REG_RANK_12
+  *         @arg @ref LL_ADC_REG_RANK_13
+  *         @arg @ref LL_ADC_REG_RANK_14
+  *         @arg @ref LL_ADC_REG_RANK_15
+  *         @arg @ref LL_ADC_REG_RANK_16
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
+  *         (1) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+  
+  return (uint32_t) (READ_BIT(*preg,
+                              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+                     >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
+                    );
+}
+
+/**
+  * @brief  Set ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @note   It is not possible to enable both ADC group regular 
+  *         continuous mode and sequencer discontinuous mode.
+  * @rmtoll CR2      CONT           LL_ADC_REG_SetContinuousMode
+  * @param  ADCx ADC instance
+  * @param  Continuous This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+  MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
+}
+
+/**
+  * @brief  Get ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @rmtoll CR2      CONT           LL_ADC_REG_GetContinuousMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
+}
+
+/**
+  * @brief  Set ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *        (overrun flag and interruption if enabled).
+  * @note   For devices with several ADC instances: ADC multimode DMA
+  *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @rmtoll CR2      DMA            LL_ADC_REG_SetDMATransfer\n
+  *         CR2      DDS            LL_ADC_REG_SetDMATransfer
+  * @param  ADCx ADC instance
+  * @param  DMATransfer This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+  MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   For devices with several ADC instances: ADC multimode DMA
+  *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @rmtoll CR2      DMA            LL_ADC_REG_GetDMATransfer\n
+  *         CR2      DDS            LL_ADC_REG_GetDMATransfer
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
+}
+
+/**
+  * @brief  Specify which ADC flag between EOC (end of unitary conversion)
+  *         or EOS (end of sequence conversions) is used to indicate
+  *         the end of conversion.
+  * @note   This feature is aimed to be set when using ADC with
+  *         programming model by polling or interruption
+  *         (programming model by DMA usually uses DMA interruptions
+  *         to indicate end of conversion and data transfer).
+  * @note   For ADC group injected, end of conversion (flag&IT) is raised
+  *         only at the end of the sequence.
+  * @rmtoll CR2      EOCS           LL_ADC_REG_SetFlagEndOfConversion
+  * @param  ADCx ADC instance
+  * @param  EocSelection This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
+  *         @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
+{
+  MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
+}
+
+/**
+  * @brief  Get which ADC flag between EOC (end of unitary conversion)
+  *         or EOS (end of sequence conversions) is used to indicate
+  *         the end of conversion.
+  * @rmtoll CR2      EOCS           LL_ADC_REG_GetFlagEndOfConversion
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
+  *         @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group injected conversion trigger source:
+  *         internal (SW start) or from external IP (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 series, setting of external trigger edge is performed
+  *         using function @ref LL_ADC_INJ_StartConversionExtTrig().
+  * @note   Availability of parameters of trigger sources from timer 
+  *         depends on timers availability on the selected device.
+  * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
+  *         CR2      JEXTEN         LL_ADC_INJ_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+/* Note: On this STM32 series, ADC group injected external trigger edge       */
+/*       is used to perform a ADC conversion start.                           */
+/*       This function does not set external trigger edge.                    */
+/*       This feature is set using function                                   */
+/*       @ref LL_ADC_INJ_StartConversionExtTrig().                            */
+  MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger source:
+  *         internal (SW start) or from external IP (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group injected trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to 
+  *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer 
+  *         depends on timers availability on the selected device.
+  * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
+  *         CR2      JEXTEN         LL_ADC_INJ_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+  uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
+  
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}.                            */
+  uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
+  
+  /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL         */
+  /* to match with triggers literals definition.                              */
+  return ((TriggerSource
+           & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
+          | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger source internal (SW start)
+            or external
+  * @note   In case of group injected trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_INJ_GetTriggerSource.
+  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger polarity.
+  *         Applicable only for trigger source set to external trigger.
+  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
+}
+
+/**
+  * @brief  Set ADC group injected sequencer length and scan direction.
+  * @note   This function performs configuration of:
+  *         - Sequence length: Number of ranks in the scan sequence.
+  *         - Sequence direction: Unless specified in parameters, sequencer
+  *           scan direction is forward (from rank 1 to rank n).
+  * @note   On this STM32 series, group injected sequencer configuration
+  *         is conditioned to ADC instance sequencer mode.
+  *         If ADC instance sequencer mode is disabled, sequencers of
+  *         all groups (group regular, group injected) can be configured
+  *         but their execution is disabled (limited to rank 1).
+  *         Refer to function @ref LL_ADC_SetSequencersScanMode().
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+  * @brief  Get ADC group injected sequencer length and scan direction.
+  * @note   This function retrieves:
+  *         - Sequence length: Number of ranks in the scan sequence.
+  *         - Sequence direction: Unless specified in parameters, sequencer
+  *           scan direction is forward (from rank 1 to rank n).
+  * @note   On this STM32 series, group injected sequencer configuration
+  *         is conditioned to ADC instance sequencer mode.
+  *         If ADC instance sequencer mode is disabled, sequencers of
+  *         all groups (group regular, group injected) can be configured
+  *         but their execution is disabled (limited to rank 1).
+  *         Refer to function @ref LL_ADC_SetSequencersScanMode().
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+  * @brief  Set ADC group injected sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group injected
+  *         auto-injected mode and sequencer discontinuous mode.
+  * @rmtoll CR1      DISCEN         LL_ADC_INJ_SetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group injected sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
+}
+
+/**
+  * @brief  Set ADC group injected sequence: channel on the selected
+  *         sequence rank.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register depending on parameter "Rank".                               */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
+  
+  MODIFY_REG(ADCx->JSQR,
+             ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
+             (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
+}
+
+/**
+  * @brief  Get ADC group injected sequence: channel on the selected
+  *         sequence rank.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
+  *         (1) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos)  + 1U;
+  
+  return (uint32_t)(READ_BIT(ADCx->JSQR,
+                             ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
+                    >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
+                   );
+}
+
+/**
+  * @brief  Set ADC group injected conversion trigger:
+  *         independent or from ADC group regular.
+  * @note   This mode can be used to extend number of data registers
+  *         updated after one ADC conversion trigger and with data 
+  *         permanently kept (not erased by successive conversions of scan of
+  *         ADC sequencer ranks), up to 5 data registers:
+  *         1 data register on ADC group regular, 4 data registers
+  *         on ADC group injected.            
+  * @note   If ADC group injected injected trigger source is set to an
+  *         external trigger, this feature must be must be set to
+  *         independent trigger.
+  *         ADC group injected automatic trigger is compliant only with 
+  *         group injected trigger source set to SW start, without any 
+  *         further action on  ADC group injected conversion start or stop: 
+  *         in this case, ADC group injected is controlled only 
+  *         from ADC group regular.
+  * @note   It is not possible to enable both ADC group injected
+  *         auto-injected mode and sequencer discontinuous mode.
+  * @rmtoll CR1      JAUTO          LL_ADC_INJ_SetTrigAuto
+  * @param  ADCx ADC instance
+  * @param  TrigAuto This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+  MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger:
+  *         independent or from ADC group regular.
+  * @rmtoll CR1      JAUTO          LL_ADC_INJ_GetTrigAuto
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
+}
+
+/**
+  * @brief  Set ADC group injected offset.
+  * @note   It sets:
+  *         - ADC group injected rank to which the offset programmed
+  *           will be applied
+  *         - Offset level (offset to be subtracted from the raw
+  *           converted data).
+  *         Caution: Offset format is dependent to ADC resolution:
+  *         offset has to be left-aligned on bit 11, the LSB (right bits)
+  *         are set to 0.
+  * @note   Offset cannot be enabled or disabled.
+  *         To emulate offset disabled, set an offset value equal to 0.
+  * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_SetOffset\n
+  *         JOFR2    JOFFSET2       LL_ADC_INJ_SetOffset\n
+  *         JOFR3    JOFFSET3       LL_ADC_INJ_SetOffset\n
+  *         JOFR4    JOFFSET4       LL_ADC_INJ_SetOffset
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+  
+  MODIFY_REG(*preg,
+             ADC_JOFR1_JOFFSET1,
+             OffsetLevel);
+}
+
+/**
+  * @brief  Get ADC group injected offset.
+  * @note   It gives offset level (offset to be subtracted from the raw converted data).
+  *         Caution: Offset format is dependent to ADC resolution:
+  *         offset has to be left-aligned on bit 11, the LSB (right bits)
+  *         are set to 0.
+  * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_GetOffset\n
+  *         JOFR2    JOFFSET2       LL_ADC_INJ_GetOffset\n
+  *         JOFR3    JOFFSET3       LL_ADC_INJ_GetOffset\n
+  *         JOFR4    JOFFSET4       LL_ADC_INJ_GetOffset
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+  
+  return (uint32_t)(READ_BIT(*preg,
+                             ADC_JOFR1_JOFFSET1)
+                   );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+  * @{
+  */
+
+/**
+  * @brief  Set sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
+  *         converted:
+  *         sampling time constraints must be respected (sampling time can be
+  *         adjusted in function of ADC clock frequency and sampling time
+  *         setting).
+  *         Refer to device datasheet for timings values (parameters TS_vrefint,
+  *         TS_temp, ...).
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         Refer to reference manual for ADC processing time of
+  *         this STM32 series.
+  * @note   In case of ADC conversion of internal channel (VrefInt,
+  *         temperature sensor, ...), a sampling time minimum value
+  *         is required.
+  *         Refer to device datasheet.
+  * @rmtoll SMPR1    SMP18          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP17          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP16          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP15          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP14          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP13          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP12          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP11          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP10          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP9           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP8           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP7           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP6           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP5           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP4           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP3           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP2           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP1           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP0           LL_ADC_SetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+  * @param  SamplingTime This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+  /* Set bits with content of parameter "SamplingTime" with bits position     */
+  /* in register and register position depending on parameter "Channel".      */
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+  
+  MODIFY_REG(*preg,
+             ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
+             SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         Refer to reference manual for ADC processing time of
+  *         this STM32 series.
+  * @rmtoll SMPR1    SMP18          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP17          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP16          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP15          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP14          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP13          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP12          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP11          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP10          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP9           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP8           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP7           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP6           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP5           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP4           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP3           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP2           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP1           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP0           LL_ADC_GetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
+  *         @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+  
+  return (uint32_t)(READ_BIT(*preg,
+                             ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
+                    >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+  * @{
+  */
+
+/**
+  * @brief  Set ADC analog watchdog monitored channels:
+  *         a single channel or all channels,
+  *         on ADC groups regular and-or injected.
+  * @note   Once monitored channels are selected, analog watchdog
+  *         is enabled.
+  * @note   In case of need to define a single channel to monitor
+  *         with analog watchdog from sequencer channel definition,
+  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+  * @note   On this STM32 series, there is only 1 kind of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  * @rmtoll CR1      AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
+  *         CR1      AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
+  *         CR1      AWD1EN         LL_ADC_SetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDChannelGroup This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (1)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (1)(2)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (1)(2)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (1)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (1)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (1)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ         (1)
+  *         
+  *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
+  *         (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
+{
+  MODIFY_REG(ADCx->CR1,
+             (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
+             AWDChannelGroup);
+}
+
+/**
+  * @brief  Get ADC analog watchdog monitored channel.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Applicable only when the analog watchdog is set to monitor
+  *           one channel.
+  * @note   On this STM32 series, there is only 1 kind of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  * @rmtoll CR1      AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
+  *         CR1      AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
+  *         CR1      AWD1EN         LL_ADC_GetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
+}
+
+/**
+  * @brief  Set ADC analog watchdog threshold value of threshold
+  *         high or low.
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 series, there is only 1 kind of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  * @rmtoll HTR      HT             LL_ADC_SetAnalogWDThresholds\n
+  *         LTR      LT             LL_ADC_SetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+  
+  MODIFY_REG(*preg,
+             ADC_HTR_HT,
+             AWDThresholdValue);
+}
+
+/**
+  * @brief  Get ADC analog watchdog threshold value of threshold high or
+  *         threshold low.
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+  * @rmtoll HTR      HT             LL_ADC_GetAnalogWDThresholds\n
+  *         LTR      LT             LL_ADC_GetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+  
+  return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
+  * @{
+  */
+
+/**
+  * @brief  Set ADC multimode configuration to operate in independent mode
+  *         or multimode (for devices with several ADC instances).
+  * @note   If multimode configuration: the selected ADC instance is
+  *         either master or slave depending on hardware.
+  *         Refer to reference manual.
+  * @rmtoll CCR      MULTI          LL_ADC_SetMultimode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  Multimode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
+}
+
+/**
+  * @brief  Get ADC multimode configuration to operate in independent mode
+  *         or multimode (for devices with several ADC instances).
+  * @note   If multimode configuration: the selected ADC instance is
+  *         either master or slave depending on hardware.
+  *         Refer to reference manual.
+  * @rmtoll CCR      MULTI          LL_ADC_GetMultimode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
+}
+
+/**
+  * @brief  Set ADC multimode conversion data transfer: no transfer
+  *         or transfer by DMA.
+  * @note   If ADC multimode transfer by DMA is not selected:
+  *         each ADC uses its own DMA channel, with its individual
+  *         DMA transfer settings.
+  *         If ADC multimode transfer by DMA is selected:
+  *         One DMA channel is used for both ADC (DMA of ADC master)
+  *         Specifies the DMA requests mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   How to retrieve multimode conversion data:
+  *         Whatever multimode transfer by DMA setting: using function
+  *         @ref LL_ADC_REG_ReadMultiConversionData32().
+  *         If ADC multimode transfer by DMA is selected: conversion data
+  *         is a raw data with ADC master and slave concatenated.
+  *         A macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\n
+  *         CCR      DDS            LL_ADC_SetMultiDMATransfer
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  MultiDMATransfer This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);
+}
+
+/**
+  * @brief  Get ADC multimode conversion data transfer: no transfer
+  *         or transfer by DMA.
+  * @note   If ADC multimode transfer by DMA is not selected:
+  *         each ADC uses its own DMA channel, with its individual
+  *         DMA transfer settings.
+  *         If ADC multimode transfer by DMA is selected:
+  *         One DMA channel is used for both ADC (DMA of ADC master)
+  *         Specifies the DMA requests mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   How to retrieve multimode conversion data:
+  *         Whatever multimode transfer by DMA setting: using function
+  *         @ref LL_ADC_REG_ReadMultiConversionData32().
+  *         If ADC multimode transfer by DMA is selected: conversion data
+  *         is a raw data with ADC master and slave concatenated.
+  *         A macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\n
+  *         CCR      DDS            LL_ADC_GetMultiDMATransfer
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));
+}
+
+/**
+  * @brief  Set ADC multimode delay between 2 sampling phases.
+  * @note   The sampling delay range depends on ADC resolution:
+  *         - ADC resolution 12 bits can have maximum delay of 12 cycles.
+  *         - ADC resolution 10 bits can have maximum delay of 10 cycles.
+  *         - ADC resolution  8 bits can have maximum delay of  8 cycles.
+  *         - ADC resolution  6 bits can have maximum delay of  6 cycles.
+  * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  MultiTwoSamplingDelay This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+}
+
+/**
+  * @brief  Get ADC multimode delay between 2 sampling phases.
+  * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+}
+
+/**
+  * @}
+  */
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Enable the selected ADC instance.
+  * @note   On this STM32 series, after ADC enable, a delay for 
+  *         ADC internal analog stabilization is required before performing a
+  *         ADC conversion start.
+  *         Refer to device datasheet, parameter tSTAB.
+  * @rmtoll CR2      ADON           LL_ADC_Enable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->CR2, ADC_CR2_ADON);
+}
+
+/**
+  * @brief  Disable the selected ADC instance.
+  * @rmtoll CR2      ADON           LL_ADC_Disable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
+}
+
+/**
+  * @brief  Get the selected ADC instance enable state.
+  * @rmtoll CR2      ADON           LL_ADC_IsEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: ADC is disabled, 1: ADC is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group regular conversion.
+  * @note   On this STM32 series, this function is relevant only for
+  *         internal trigger (SW start), not for external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           start must be performed using function 
+  *           @ref LL_ADC_REG_StartConversionExtTrig().
+  *           (if external trigger edge would have been set during ADC other 
+  *           settings, ADC conversion would start at trigger event
+  *           as soon as ADC is enabled).
+  * @rmtoll CR2      SWSTART        LL_ADC_REG_StartConversionSWStart
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
+}
+
+/**
+  * @brief  Start ADC group regular conversion from external trigger.
+  * @note   ADC conversion will start at next trigger event (on the selected
+  *         trigger edge) following the ADC start conversion command.
+  * @note   On this STM32 series, this function is relevant for 
+  *         ADC conversion start from external trigger.
+  *         If internal trigger (SW start) is needed, perform ADC conversion
+  *         start using function @ref LL_ADC_REG_StartConversionSWStart().
+  * @rmtoll CR2      EXTEN          LL_ADC_REG_StartConversionExtTrig
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  SET_BIT(ADCx->CR2, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Stop ADC group regular conversion from external trigger.
+  * @note   No more ADC conversion will start at next trigger event
+  *         following the ADC stop conversion command.
+  *         If a conversion is on-going, it will be completed.
+  * @note   On this STM32 series, there is no specific command
+  *         to stop a conversion on-going or to stop ADC converting
+  *         in continuous mode. These actions can be performed
+  *         using function @ref LL_ADC_Disable().
+  * @rmtoll CR2      EXTEN          LL_ADC_REG_StopConversionExtTrig
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL);
+}
+
+/**
+  * @brief  Get ADC multimode conversion data of ADC master, ADC slave
+  *         or raw data with ADC master and slave concatenated.
+  * @note   If raw data with ADC master and slave concatenated is retrieved,
+  *         a macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  *         (however this macro is mainly intended for multimode
+  *         transfer by DMA, because this function can do the same
+  *         by getting multimode conversion data of ADC master or ADC slave
+  *         separately).
+  * @rmtoll CDR      DATA1          LL_ADC_REG_ReadMultiConversionData32\n
+  *         CDR      DATA2          LL_ADC_REG_ReadMultiConversionData32
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  ConversionData This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
+                             ADC_DR_ADC2DATA)
+                    >> POSITION_VAL(ConversionData)
+                   );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group injected conversion.
+  * @note   On this STM32 series, this function is relevant only for
+  *         internal trigger (SW start), not for external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           start must be performed using function 
+  *           @ref LL_ADC_INJ_StartConversionExtTrig().
+  *           (if external trigger edge would have been set during ADC other 
+  *           settings, ADC conversion would start at trigger event
+  *           as soon as ADC is enabled).
+  * @rmtoll CR2      JSWSTART       LL_ADC_INJ_StartConversionSWStart
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
+}
+
+/**
+  * @brief  Start ADC group injected conversion from external trigger.
+  * @note   ADC conversion will start at next trigger event (on the selected
+  *         trigger edge) following the ADC start conversion command.
+  * @note   On this STM32 series, this function is relevant for 
+  *         ADC conversion start from external trigger.
+  *         If internal trigger (SW start) is needed, perform ADC conversion
+  *         start using function @ref LL_ADC_INJ_StartConversionSWStart().
+  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_StartConversionExtTrig
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  SET_BIT(ADCx->CR2, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Stop ADC group injected conversion from external trigger.
+  * @note   No more ADC conversion will start at next trigger event
+  *         following the ADC stop conversion command.
+  *         If a conversion is on-going, it will be completed.
+  * @note   On this STM32 series, there is no specific command
+  *         to stop a conversion on-going or to stop ADC converting
+  *         in continuous mode. These actions can be performed
+  *         using function @ref LL_ADC_Disable().
+  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_StopConversionExtTrig
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+  
+  return (uint32_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+  
+  return (uint16_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+  
+  return (uint16_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+  
+  return (uint8_t)(READ_BIT(*preg,
+                            ADC_JDR1_JDATA) & 0x000000FFUL
+                  );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+  
+  return (uint8_t)(READ_BIT(*preg,
+                            ADC_JDR1_JDATA) & 0x000000FFUL
+                  );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+  * @{
+  */
+
+/**
+  * @brief  Get flag ADC group regular end of unitary conversion
+  *         or end of sequence conversions, depending on
+  *         ADC configuration.
+  * @note   To configure flag of end of conversion,
+  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+  * @rmtoll SR       EOC            LL_ADC_IsActiveFlag_EOCS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
+}
+
+/**
+  * @brief  Get flag ADC group regular overrun.
+  * @rmtoll SR       OVR            LL_ADC_IsActiveFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
+}
+
+
+/**
+  * @brief  Get flag ADC group injected end of sequence conversions.
+  * @rmtoll SR       JEOC           LL_ADC_IsActiveFlag_JEOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+{
+  /* Note: on this STM32 series, there is no flag ADC group injected          */
+  /*       end of unitary conversion.                                         */
+  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
+  /*       in other STM32 families).                                          */
+  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 1 flag
+  * @rmtoll SR       AWD            LL_ADC_IsActiveFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of unitary conversion
+  *         or end of sequence conversions, depending on
+  *         ADC configuration.
+  * @note   To configure flag of end of conversion,
+  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+  * @rmtoll SR       EOC            LL_ADC_ClearFlag_EOCS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
+}
+
+/**
+  * @brief  Clear flag ADC group regular overrun.
+  * @rmtoll SR       OVR            LL_ADC_ClearFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
+}
+
+
+/**
+  * @brief  Clear flag ADC group injected end of sequence conversions.
+  * @rmtoll SR       JEOC           LL_ADC_ClearFlag_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+  /* Note: on this STM32 series, there is no flag ADC group injected          */
+  /*       end of unitary conversion.                                         */
+  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
+  /*       in other STM32 families).                                          */
+  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 1.
+  * @rmtoll SR       AWD            LL_ADC_ClearFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of unitary conversion
+  *         or end of sequence conversions, depending on
+  *         ADC configuration, of the ADC master.
+  * @note   To configure flag of end of conversion,
+  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+  * @rmtoll CSR      EOC1           LL_ADC_IsActiveFlag_MST_EOCS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of unitary conversion
+  *         or end of sequence conversions, depending on
+  *         ADC configuration, of the ADC slave 1.
+  * @note   To configure flag of end of conversion,
+  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+  * @rmtoll CSR      EOC2           LL_ADC_IsActiveFlag_SLV1_EOCS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of unitary conversion
+  *         or end of sequence conversions, depending on
+  *         ADC configuration, of the ADC slave 2.
+  * @note   To configure flag of end of conversion,
+  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+  * @rmtoll CSR      EOC3           LL_ADC_IsActiveFlag_SLV2_EOCS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
+}
+/**
+  * @brief  Get flag multimode ADC group regular overrun of the ADC master.
+  * @rmtoll CSR      OVR1           LL_ADC_IsActiveFlag_MST_OVR
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular overrun of the ADC slave 1.
+  * @rmtoll CSR      OVR2           LL_ADC_IsActiveFlag_SLV1_OVR
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular overrun of the ADC slave 2.
+  * @rmtoll CSR      OVR3           LL_ADC_IsActiveFlag_SLV2_OVR
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
+}
+
+
+/**
+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
+  * @rmtoll CSR      JEOC           LL_ADC_IsActiveFlag_MST_EOCS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  /* Note: on this STM32 series, there is no flag ADC group injected          */
+  /*       end of unitary conversion.                                         */
+  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
+  /*       in other STM32 families).                                          */
+  return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
+  * @rmtoll CSR      JEOC2          LL_ADC_IsActiveFlag_SLV1_JEOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  /* Note: on this STM32 series, there is no flag ADC group injected          */
+  /*       end of unitary conversion.                                         */
+  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
+  /*       in other STM32 families).                                          */
+  return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
+  * @rmtoll CSR      JEOC3          LL_ADC_IsActiveFlag_SLV2_JEOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  /* Note: on this STM32 series, there is no flag ADC group injected          */
+  /*       end of unitary conversion.                                         */
+  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
+  /*       in other STM32 families).                                          */
+  return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
+  * @rmtoll CSR      AWD1           LL_ADC_IsActiveFlag_MST_AWD1
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
+}
+
+/**
+  * @brief  Get flag multimode analog watchdog 1 of the ADC slave 1.
+  * @rmtoll CSR      AWD2           LL_ADC_IsActiveFlag_SLV1_AWD1
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
+}
+
+/**
+  * @brief  Get flag multimode analog watchdog 1 of the ADC slave 2.
+  * @rmtoll CSR      AWD3           LL_ADC_IsActiveFlag_SLV2_AWD1
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+    return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+  * @{
+  */
+
+/**
+  * @brief  Enable interruption ADC group regular end of unitary conversion
+  *         or end of sequence conversions, depending on
+  *         ADC configuration.
+  * @note   To configure flag of end of conversion,
+  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+  * @rmtoll CR1      EOCIE          LL_ADC_EnableIT_EOCS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
+}
+
+/**
+  * @brief  Enable ADC group regular interruption overrun.
+  * @rmtoll CR1      OVRIE          LL_ADC_EnableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
+}
+
+
+/**
+  * @brief  Enable interruption ADC group injected end of sequence conversions.
+  * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+  /* Note: on this STM32 series, there is no flag ADC group injected          */
+  /*       end of unitary conversion.                                         */
+  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
+  /*       in other STM32 families).                                          */
+  SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 1.
+  * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of unitary conversion
+  *         or end of sequence conversions, depending on
+  *         ADC configuration.
+  * @note   To configure flag of end of conversion,
+  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+  * @rmtoll CR1      EOCIE          LL_ADC_DisableIT_EOCS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular overrun.
+  * @rmtoll CR1      OVRIE          LL_ADC_DisableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
+}
+
+
+/**
+  * @brief  Disable interruption ADC group injected end of sequence conversions.
+  * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+  /* Note: on this STM32 series, there is no flag ADC group injected          */
+  /*       end of unitary conversion.                                         */
+  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
+  /*       in other STM32 families).                                          */
+  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 1.
+  * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of unitary conversion
+  *         or end of sequence conversions, depending on
+  *         ADC configuration.
+  * @note   To configure flag of end of conversion,
+  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
+  *         (0: interrupt disabled, 1: interrupt enabled)
+  * @rmtoll CR1      EOCIE          LL_ADC_IsEnabledIT_EOCS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular overrun
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll CR1      OVRIE          LL_ADC_IsEnabledIT_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
+}
+
+
+/**
+  * @brief  Get state of interruption ADC group injected end of sequence conversions
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+{
+  /* Note: on this STM32 series, there is no flag ADC group injected          */
+  /*       end of unitary conversion.                                         */
+  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
+  /*       in other STM32 families).                                          */
+  return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
+}
+
+/**
+  * @brief  Get state of interruption ADC analog watchdog 1
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 families) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 || ADC2 || ADC3 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_LL_ADC_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h
new file mode 100644
index 0000000..a7af3f4
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h
@@ -0,0 +1,1973 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_bus.h
+  * @author  MCD Application Team
+  * @brief   Header file of BUS LL module.
+
+  @verbatim
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]  
+      A delay between an RCC peripheral clock enable and the effective peripheral 
+      enabling should be taken into account in order to manage the peripheral read/write 
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+        (++) AHB & APB peripherals, 1 dummy read is necessary
+
+    [..]  
+      Workarounds:
+      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_LL_BUS_H
+#define __STM32F7xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  * @{
+  */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN
+#define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN
+#define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN
+#define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN
+#define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN
+#define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN
+#define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN
+#define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN
+#define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN
+#if defined(GPIOJ)
+#define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN
+#endif /* GPIOJ */
+#if defined(GPIOK)
+#define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN
+#endif /* GPIOK */
+#define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN
+#define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN
+#define LL_AHB1_GRP1_PERIPH_DTCMRAM         RCC_AHB1ENR_DTCMRAMEN
+#define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN
+#define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN
+#if defined(DMA2D)
+#define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN
+#endif /* DMA2D */
+#if defined(ETH)
+#define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN
+#endif /* ETH */
+#define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN
+#define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN
+#define LL_AHB1_GRP1_PERIPH_AXI             RCC_AHB1LPENR_AXILPEN
+#define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN
+#define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN
+#define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#if defined(DCMI)
+#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+#endif /* DCMI */
+#if defined(JPEG)
+#define LL_AHB2_GRP1_PERIPH_JPEG           RCC_AHB2ENR_JPEGEN
+#endif /* JPEG */
+#if defined(CRYP) 
+#define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+#endif /* CRYP */
+#if defined(AES)
+#define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
+#endif /* AES */
+#if defined(HASH)
+#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+#endif /* HASH */
+#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+#define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
+#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
+#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
+#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
+#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
+#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
+#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
+#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
+#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
+#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN
+#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
+#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
+#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
+#if defined(SPDIFRX)
+#define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN
+#endif /* SPDIFRX */
+#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
+#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
+#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
+#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
+#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
+#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
+#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN
+#if defined(I2C4)
+#define LL_APB1_GRP1_PERIPH_I2C4           RCC_APB1ENR_I2C4EN
+#endif /* I2C4 */
+#define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN
+#if defined(CAN2)
+#define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN
+#endif /* CAN2 */
+#if defined(CAN3)
+#define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN
+#endif /* CAN3 */
+#if defined(CEC)
+#define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
+#endif /* CEC */
+#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
+#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
+#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN
+#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN
+#if defined(RCC_APB1ENR_RTCEN)
+#define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCEN
+#endif /* RCC_APB1ENR_RTCEN */
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN
+#define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN
+#define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN
+#define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN
+#define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN
+#define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN
+#define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN
+#define LL_APB2_GRP1_PERIPH_SDMMC1       RCC_APB2ENR_SDMMC1EN
+#if defined(SDMMC2)
+#define LL_APB2_GRP1_PERIPH_SDMMC2       RCC_APB2ENR_SDMMC2EN
+#endif /* SDMMC2 */
+#define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN
+#define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN
+#define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN
+#define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN
+#define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN
+#define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN
+#define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN
+#if defined(SPI6)
+#define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN
+#endif /* SPI6 */
+#define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN
+#define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN
+#if defined(LTDC)
+#define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN
+#endif /* LTDC */
+#if defined(DSI)
+#define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN
+#endif /* DSI */
+#if defined(DFSDM1_Channel0)
+#define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN
+#endif /* DFSDM1_Channel0 */
+#if defined(MDIOS)
+#define LL_APB2_GRP1_PERIPH_MDIO         RCC_APB2ENR_MDIOEN
+#endif /* MDIOS */
+#if defined(USB_HS_PHYC)
+#define LL_APB2_GRP1_PERIPH_OTGPHYC      RCC_APB2ENR_OTGPHYCEN
+#endif /* USB_HS_PHYC */
+#define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+  * @{
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB1 peripheral clocks in low-power mode
+  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    AXILPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    DTCMRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_AXI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB1 peripheral clocks in low-power mode
+  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    AXILPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    DTCMRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_AXI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      AESEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      AESEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      AESEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     JPEGRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     JPEGRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB2 peripheral clocks in low-power mode
+  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    JPEGLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB2 peripheral clocks in low-power mode
+  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    JPEGLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB3 peripheral clocks in low-power mode
+  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockLowPower\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB3 peripheral clocks in low-power mode
+  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockLowPower\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     USART3EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART4EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART5EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C4EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CAN1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CAN2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CAN3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CECEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART7EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART8EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     RTCEN         LL_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C4EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CAN1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CAN2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CAN3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART8EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     RTCEN         LL_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     USART3EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART4EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART5EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C4EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CAN1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CAN2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CAN3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CECEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART7EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART8EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     RTCEN         LL_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C4RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CECRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C4RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CECRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripheral clocks in low-power mode
+  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     I2C4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     RTCLPEN         LL_APB1_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripheral clocks in low-power mode
+  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     I2C4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     RTCLPEN         LL_APB1_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable APB2 peripherals clock.
+  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM8EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     USART1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     USART6EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     ADC1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     ADC2EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     ADC3EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI4EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM9EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM10EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM11EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI5EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI6EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SAI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SAI2EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     LTDCEN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     DSIEN         LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     MDIOEN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     USART6EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     ADC1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     ADC2EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     ADC3EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM9EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM10EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM11EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI6EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     LTDCEN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     DSIEN         LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     MDIOEN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock.
+  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM8EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     USART1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     USART6EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     ADC1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     ADC2EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     ADC3EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI4EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM9EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM10EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM11EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI5EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI6EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SAI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SAI2EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     LTDCEN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     DSIEN         LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     MDIOEN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SDMMC1RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SDMMC2RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     MDIORST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     OTGPHYCRST     LL_APB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SDMMC1RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SDMMC2RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     MDIORST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     OTGPHYCRST     LL_APB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB2 peripheral clocks in low-power mode
+  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SDMMC1LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SDMMC2LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     MDIOLPEN        LL_APB2_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB2 peripheral clocks in low-power mode
+  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SDMMC1LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SDMMC2LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     MDIOLPEN        LL_APB2_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_LL_BUS_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h
new file mode 100644
index 0000000..ad98cc2
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h
@@ -0,0 +1,639 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL CORTEX driver contains a set of generic APIs that can be
+    used by user:
+      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
+          functions
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
+      (+) MPU API to configure and enable regions
+      (+) API to access to MCU info (CPUID register)
+      (+) API to enable fault handler (SHCSR accesses)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_LL_CORTEX_H
+#define __STM32F7xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX_LL CORTEX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+  * @{
+  */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+  * @{
+  */
+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+  * @{
+  */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+  * @{
+  */
+#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+  * @{
+  */
+#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+  * @{
+  */
+#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+  * @{
+  */
+#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+
+/* Legacy Define */
+#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+  * @{
+  */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+  * @{
+  */
+
+/**
+  * @brief  This function checks if the Systick counter flag is active or not.
+  * @note   It can be used in timeout function on application side.
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+  * @brief  Configures the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+  {
+    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+  else
+  {
+    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+}
+
+/**
+  * @brief  Get the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+  * @brief  Enable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Disable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+  * @{
+  */
+
+/**
+  * @brief  Processor uses sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Processor uses deep sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+  *         empty main application.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Do not sleep when returning to Thread mode.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
+  *         processor.
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+  /* Set SEVEONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+  *         excluded
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+  * @{
+  */
+
+/**
+  * @brief  Enable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+  /* Enable the system handler fault */
+  SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @brief  Disable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+  /* Disable the system handler fault */
+  CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+  * @{
+  */
+
+/**
+  * @brief  Get Implementer code
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
+  * @retval Value should be equal to 0x41 for ARM
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
+  * @retval Value between 0 and 255 (0x0: revision 0)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+  * @brief  Get Constant number
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
+  * @retval Value should be equal to 0xF for Cortex-M7 devices
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+  * @brief  Get Part number
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
+  * @retval Value should be equal to 0xC27 for Cortex-M7
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
+  * @retval Value between 0 and 255 (0x1: patch 1)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+  * @{
+  */
+
+/**
+  * @brief  Enable MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  Options This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+  /* Enable the MPU*/
+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+  /* Ensure MPU settings take effects */
+  __DSB();
+  /* Sequence instruction fetches using update settings */
+  __ISB();
+}
+
+/**
+  * @brief  Disable MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+  /* Disable MPU*/
+  WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+  * @brief  Check if MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+  * @brief  Enable a MPU region
+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Enable the MPU region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Configure and enable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @param  Address Value of region base address
+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Set base address */
+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+  /* Configure MPU */
+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
+}
+
+/**
+  * @brief  Disable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @}
+  */
+
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_LL_CORTEX_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h
new file mode 100644
index 0000000..07933e4
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h
@@ -0,0 +1,2891 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_LL_DMA_H
+#define __STM32F7xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  * @{
+  */
+/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
+static const uint8_t STREAM_OFFSET_TAB[] =
+{
+  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
+};
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Constants DMA Private Constants
+  * @{
+  */
+#if defined(DMA_SxCR_CHSEL_3)
+#define DMA_CHANNEL_SELECTION_8_15
+#endif /* DMA_SxCR_CHSEL_3 */
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+                                        or as Source base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+                                        or as Destination base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+                                        This parameter can be a value of @ref DMA_LL_EC_MODE
+                                        @note The circular buffer mode cannot be used if the memory to memory
+                                              data transfer direction is configured on the selected Stream
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+                                        The data unit is equal to the source buffer configuration set in PeripheralSize
+                                        or MemorySize parameters depending in the transfer direction.
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+  uint32_t Channel;                /*!< Specifies the peripheral channel.
+                                        This parameter can be a value of @ref DMA_LL_EC_CHANNEL
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
+
+  uint32_t Priority;               /*!< Specifies the channel priority level.
+                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
+                                        
+  uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                        This parameter can be a value of @ref DMA_LL_FIFOMODE
+                                        @note The Direct mode (FIFO mode disabled) cannot be used if the 
+                                        memory-to-memory data transfer is configured on the selected stream
+
+                                        This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
+
+  uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
+                                        This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
+
+  uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptible
+                                        transaction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MBURST 
+                                        @note The burst mode is possible only if the address Increment mode is enabled. 
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
+
+  uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptible 
+                                        transaction. 
+                                        This parameter can be a value of @ref DMA_LL_EC_PBURST
+                                        @note The burst mode is possible only if the address Increment mode is enabled. 
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
+
+} LL_DMA_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_LL_EC_STREAM STREAM
+  * @{
+  */
+#define LL_DMA_STREAM_0                   0x00000000U
+#define LL_DMA_STREAM_1                   0x00000001U
+#define LL_DMA_STREAM_2                   0x00000002U
+#define LL_DMA_STREAM_3                   0x00000003U
+#define LL_DMA_STREAM_4                   0x00000004U
+#define LL_DMA_STREAM_5                   0x00000005U
+#define LL_DMA_STREAM_6                   0x00000006U
+#define LL_DMA_STREAM_7                   0x00000007U
+#define LL_DMA_STREAM_ALL                 0xFFFF0000U
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
+  * @{
+  */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MODE MODE
+  * @{
+  */
+#define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode                  */
+#define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode                */
+#define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
+  * @{
+  */
+#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering mode */
+#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mode  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PERIPH PERIPH
+  * @{
+  */
+#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode Disable */
+#define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MEMORY MEMORY
+  * @{
+  */
+#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disable */
+#define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
+  * @{
+  */
+#define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment : Byte     */
+#define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
+  * @{
+  */
+#define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : Byte     */
+#define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
+  * @{
+  */
+#define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offset size is linked to the PSIZE */
+#define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
+  * @{
+  */
+#define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */
+#define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium    */
+#define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High      */
+#define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+  * @{
+  */
+#define LL_DMA_CHANNEL_0                  0x00000000U                                                /* Select Channel0 of DMA Instance */
+#define LL_DMA_CHANNEL_1                  DMA_SxCR_CHSEL_0                                           /* Select Channel1 of DMA Instance */
+#define LL_DMA_CHANNEL_2                  DMA_SxCR_CHSEL_1                                           /* Select Channel2 of DMA Instance */
+#define LL_DMA_CHANNEL_3                  (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1)                      /* Select Channel3 of DMA Instance */
+#define LL_DMA_CHANNEL_4                  DMA_SxCR_CHSEL_2                                           /* Select Channel4 of DMA Instance */
+#define LL_DMA_CHANNEL_5                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)                      /* Select Channel5 of DMA Instance */
+#define LL_DMA_CHANNEL_6                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)                      /* Select Channel6 of DMA Instance */
+#define LL_DMA_CHANNEL_7                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)   /* Select Channel7 of DMA Instance */
+#if defined(DMA_CHANNEL_SELECTION_8_15)
+#define LL_DMA_CHANNEL_8                  DMA_SxCR_CHSEL_3                                           /* Select Channel8 of DMA Instance */
+#define LL_DMA_CHANNEL_9                  (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0)                      /* Select Channel9 of DMA Instance */
+#define LL_DMA_CHANNEL_10                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1)                      /* Select Channel10 of DMA Instance */
+#define LL_DMA_CHANNEL_11                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)   /* Select Channel11 of DMA Instance */
+#define LL_DMA_CHANNEL_12                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2)                      /* Select Channel12 of DMA Instance */
+#define LL_DMA_CHANNEL_13                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)   /* Select Channel13 of DMA Instance */
+#define LL_DMA_CHANNEL_14                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)   /* Select Channel14 of DMA Instance */
+#define LL_DMA_CHANNEL_15                 DMA_SxCR_CHSEL                                             /* Select Channel15 of DMA Instance */
+#endif /* DMA_CHANNEL_SELECTION_8_15 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MBURST MBURST
+  * @{
+  */
+#define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst single transfer configuration */
+#define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst of 4 beats transfer configuration */
+#define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst of 8 beats transfer configuration */
+#define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PBURST PBURST
+  * @{
+  */
+#define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral burst single transfer configuration */
+#define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral burst of 4 beats transfer configuration */
+#define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral burst of 8 beats transfer configuration */
+#define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
+  * @{
+  */
+#define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode disable (direct mode is enabled) */
+#define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode enable  */
+/**
+  * @}
+  */  
+
+/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
+  * @{
+  */
+#define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_level < 1/4    */
+#define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_level < 1/2  */
+#define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_level < 3/4  */
+#define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_level < full */
+#define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empty           */
+#define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full            */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
+  * @{
+  */
+#define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO threshold 1 quart full configuration  */
+#define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO threshold half full configuration     */
+#define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO threshold 3 quarts full configuration */
+#define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */
+    
+/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+  * @{
+  */
+#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */
+#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
+  * @{
+  */
+/**
+  * @brief  Convert DMAx_Streamy into DMAx
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval DMAx
+  */
+#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
+
+/**
+  * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval LL_DMA_CHANNEL_y
+  */
+#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
+ LL_DMA_STREAM_7)
+
+/**
+  * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
+  * @param  __DMA_INSTANCE__ DMAx
+  * @param  __STREAM__ LL_DMA_STREAM_y
+  * @retval DMAx_Streamy
+  */
+#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
+ DMA2_Stream7)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+ /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief Enable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_EnableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Disable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_DisableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Check if DMA stream is enabled or disabled.
+  * @rmtoll CR          EN            LL_DMA_IsEnabledStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
+}
+
+/**
+  * @brief  Configure all parameters linked to DMA transfer.
+  * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
+  *         CR          CIRC          LL_DMA_ConfigTransfer\n
+  *         CR          PINC          LL_DMA_ConfigTransfer\n
+  *         CR          MINC          LL_DMA_ConfigTransfer\n
+  *         CR          PSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          MSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          PL            LL_DMA_ConfigTransfer\n
+  *         CR          PFCTRL        LL_DMA_ConfigTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+  *@retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
+             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
+             Configuration);
+}
+
+/**
+  * @brief Set Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
+}
+
+/**
+  * @brief Get Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
+}
+
+/**
+  * @brief Set DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_SetMode\n
+  *         CR          PFCTRL         LL_DMA_SetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
+}
+
+/**
+  * @brief Get DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_GetMode\n
+  *         CR          PFCTRL         LL_DMA_GetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
+}
+
+/**
+  * @brief Set Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
+}
+
+/**
+  * @brief Get Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
+}
+
+/**
+  * @brief Set Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
+}
+
+/**
+  * @brief Get Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
+}
+
+/**
+  * @brief Set Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
+}
+
+/**
+  * @brief Get Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
+}
+
+/**
+  * @brief Set Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
+}
+
+/**
+  * @brief Get Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
+}
+
+/**
+  * @brief Set Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  OffsetSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
+}
+
+/**
+  * @brief Get Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
+}
+
+/**
+  * @brief Set Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Priority This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
+}
+
+/**
+  * @brief Get Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
+}
+
+/**
+  * @brief Set Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
+  * @note   This action has no effect if
+  *         stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  NbData Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
+}
+
+/**
+  * @brief Get Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
+  * @note   Once the stream is enabled, the return value indicate the
+  *         remaining bytes to be transmitted.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
+}
+
+/**
+  * @brief Select Channel number associated to the Stream.
+  * @rmtoll CR          CHSEL           LL_DMA_SetChannelSelection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         @arg @ref LL_DMA_CHANNEL_9 (*)
+  *         @arg @ref LL_DMA_CHANNEL_10 (*)
+  *         @arg @ref LL_DMA_CHANNEL_11 (*)
+  *         @arg @ref LL_DMA_CHANNEL_12 (*)
+  *         @arg @ref LL_DMA_CHANNEL_13 (*)
+  *         @arg @ref LL_DMA_CHANNEL_14 (*)
+  *         @arg @ref LL_DMA_CHANNEL_15 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
+}
+
+/**
+  * @brief Get the Channel number associated to the Stream.
+  * @rmtoll CR          CHSEL           LL_DMA_GetChannelSelection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8 (*)
+  *         @arg @ref LL_DMA_CHANNEL_9 (*)
+  *         @arg @ref LL_DMA_CHANNEL_10 (*)
+  *         @arg @ref LL_DMA_CHANNEL_11 (*)
+  *         @arg @ref LL_DMA_CHANNEL_12 (*)
+  *         @arg @ref LL_DMA_CHANNEL_13 (*)
+  *         @arg @ref LL_DMA_CHANNEL_14 (*)
+  *         @arg @ref LL_DMA_CHANNEL_15 (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
+}
+
+/**
+  * @brief Set Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
+}
+
+/**
+  * @brief Get Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
+}
+
+/**
+  * @brief Set  Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Pburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
+}
+
+/**
+  * @brief Get Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param CurrentMemory This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
+{
+   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
+}
+
+/**
+  * @brief Enable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Disable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Get FIFO status.
+  * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOSTATUS_0_25
+  *         @arg @ref LL_DMA_FIFOSTATUS_25_50
+  *         @arg @ref LL_DMA_FIFOSTATUS_50_75
+  *         @arg @ref LL_DMA_FIFOSTATUS_75_100
+  *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
+  *         @arg @ref LL_DMA_FIFOSTATUS_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
+}
+
+/**
+  * @brief Disable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Enable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Select FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
+}
+
+/**
+  * @brief Get FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
+}
+
+/**
+  * @brief Configure the FIFO .
+  * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
+  *         FCR         DMDIS        LL_DMA_ConfigFifo
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  FifoMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOMODE_ENABLE
+  *         @arg @ref LL_DMA_FIFOMODE_DISABLE
+  * @param  FifoThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
+}
+
+/**
+  * @brief Configure the Source and Destination addresses.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n 
+  *         PAR         PA          LL_DMA_ConfigAddresses
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  SrcAddress Between 0 to 0xFFFFFFFF
+  * @param  DstAddress Between 0 to 0xFFFFFFFF
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
+{
+  /* Direction Memory to Periph */
+  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+  {
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
+  }
+  /* Direction Periph to Memory and Memory to Memory */
+  else
+  {
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
+  }
+}
+
+/**
+  * @brief  Set the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  PeriphAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
+{
+  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
+}
+
+/**
+  * @brief  Get the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+  return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
+}
+
+/**
+  * @brief  Get the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+  return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
+}
+
+/**
+  * @brief  Set the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+  {
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
+  }
+
+/**
+  * @brief  Get the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+  {
+   return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
+  }
+
+/**
+  * @brief  Get the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+ return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
+}
+
+/**
+  * @brief Set Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Address Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
+}
+
+/**
+  * @brief Get Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief Get Stream 0 half transfer flag.
+  * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
+}
+
+/**
+  * @brief Get Stream 1 half transfer flag.
+  * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
+}
+
+/**
+  * @brief Get Stream 2 half transfer flag.
+  * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
+}
+
+/**
+  * @brief Get Stream 3 half transfer flag.
+  * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
+}
+
+/**
+  * @brief Get Stream 4 half transfer flag.
+  * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
+}
+
+/**
+  * @brief Get Stream 5 half transfer flag.
+  * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
+}
+
+/**
+  * @brief Get Stream 6 half transfer flag.
+  * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
+}
+
+/**
+  * @brief Get Stream 7 half transfer flag.
+  * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
+} 
+
+/**
+  * @brief Get Stream 0 transfer complete flag.
+  * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
+}
+
+/**
+  * @brief Get Stream 1 transfer complete flag.
+  * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
+}
+
+/**
+  * @brief Get Stream 2 transfer complete flag.
+  * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
+}
+
+/**
+  * @brief Get Stream 3 transfer complete flag.
+  * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
+}
+
+/**
+  * @brief Get Stream 4 transfer complete flag.
+  * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
+}
+
+/**
+  * @brief Get Stream 5 transfer complete flag.
+  * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
+}
+
+/**
+  * @brief Get Stream 6 transfer complete flag.
+  * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
+}
+
+/**
+  * @brief Get Stream 7 transfer complete flag.
+  * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
+} 
+
+/**
+  * @brief Get Stream 0 transfer error flag.
+  * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
+}
+
+/**
+  * @brief Get Stream 1 transfer error flag.
+  * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
+}
+
+/**
+  * @brief Get Stream 2 transfer error flag.
+  * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
+}
+
+/**
+  * @brief Get Stream 3 transfer error flag.
+  * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
+}
+
+/**
+  * @brief Get Stream 4 transfer error flag.
+  * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
+}
+
+/**
+  * @brief Get Stream 5 transfer error flag.
+  * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
+}
+
+/**
+  * @brief Get Stream 6 transfer error flag.
+  * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
+}
+
+/**
+  * @brief Get Stream 7 transfer error flag.
+  * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
+} 
+
+/**
+  * @brief Get Stream 0 direct mode error flag.
+  * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
+}
+
+/**
+  * @brief Get Stream 1 direct mode error flag.
+  * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
+}
+
+/**
+  * @brief Get Stream 2 direct mode error flag.
+  * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
+}
+
+/**
+  * @brief Get Stream 3 direct mode error flag.
+  * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
+}
+
+/**
+  * @brief Get Stream 4 direct mode error flag.
+  * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
+}
+
+/**
+  * @brief Get Stream 5 direct mode error flag.
+  * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
+}
+
+/**
+  * @brief Get Stream 6 direct mode error flag.
+  * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
+}
+
+/**
+  * @brief Get Stream 7 direct mode error flag.
+  * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
+}
+
+/**
+  * @brief Get Stream 0 FIFO error flag.
+  * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
+}
+
+/**
+  * @brief Get Stream 1 FIFO error flag.
+  * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
+}
+
+/**
+  * @brief Get Stream 2 FIFO error flag.
+  * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
+}
+
+/**
+  * @brief Get Stream 3 FIFO error flag.
+  * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
+}
+
+/**
+  * @brief Get Stream 4 FIFO error flag.
+  * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
+}
+
+/**
+  * @brief Get Stream 5 FIFO error flag.
+  * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
+}
+
+/**
+  * @brief Get Stream 6 FIFO error flag.
+  * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
+}
+
+/**
+  * @brief Get Stream 7 FIFO error flag.
+  * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
+}
+
+/**
+  * @brief Clear Stream 0 half transfer flag.
+  * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
+}
+
+/**
+  * @brief Clear Stream 1 half transfer flag.
+  * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
+}
+
+/**
+  * @brief Clear Stream 2 half transfer flag.
+  * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
+}
+
+/**
+  * @brief Clear Stream 3 half transfer flag.
+  * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
+}
+
+/**
+  * @brief Clear Stream 4 half transfer flag.
+  * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
+}
+
+/**
+  * @brief Clear Stream 5 half transfer flag.
+  * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
+}
+
+/**
+  * @brief Clear Stream 6 half transfer flag.
+  * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
+}
+
+/**
+  * @brief Clear Stream 7 half transfer flag.
+  * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer error flag.
+  * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer error flag.
+  * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer error flag.
+  * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer error flag.
+  * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer error flag.
+  * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer error flag.
+  * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer error flag.
+  * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer error flag.
+  * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief Enable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Enable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Enable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Enable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_EnableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Enable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_EnableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Disable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_DisableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Disable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_DisableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Disable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_DisableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Disable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_DisableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Disable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_DisableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Check if Half transfer interrup is enabled.
+  * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Check if Transfer error nterrup is enabled.
+  * @rmtoll CR        TEIE         LL_DMA_IsEnabledIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Check if Transfer complete interrup is enabled.
+  * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Check if Direct mode error interrupt is enabled.
+  * @rmtoll CR        DMEIE         LL_DMA_IsEnabledIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Check if FIFO error interrup is enabled.
+  * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_LL_DMA_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h
new file mode 100644
index 0000000..b240d5d
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h
@@ -0,0 +1,948 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_LL_EXTI_H
+#define __STM32F7xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+
+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+  * @{
+  */
+#define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */
+#define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */
+#define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */
+#define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */
+#define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */
+#define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */
+#define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */
+#define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */
+#define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */
+#define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */
+#define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */
+#define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */
+#define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */
+#define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */
+#define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */
+#define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */
+#if defined(EXTI_IMR_IM16)
+#define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
+#endif
+#define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
+#if defined(EXTI_IMR_IM18)
+#define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
+#endif
+#define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
+#if defined(EXTI_IMR_IM20)
+#define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
+#endif
+#if defined(EXTI_IMR_IM21)
+#define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */
+#endif
+#if defined(EXTI_IMR_IM22)
+#define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */
+#endif
+#define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */
+#if defined(EXTI_IMR_IM24)
+#define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */
+#endif
+#if defined(EXTI_IMR_IM25)
+#define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */
+#endif
+#if defined(EXTI_IMR_IM26)
+#define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */
+#endif
+#if defined(EXTI_IMR_IM27)
+#define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */
+#endif
+#if defined(EXTI_IMR_IM28)
+#define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */
+#endif
+#if defined(EXTI_IMR_IM29)
+#define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */
+#endif
+#if defined(EXTI_IMR_IM30)
+#define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */
+#endif
+#if defined(EXTI_IMR_IM31)
+#define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */
+#endif
+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+  * @{
+  */
+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+  * @}
+  */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in EXTI register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in EXTI register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
+
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll FTSR        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
+  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER       SWIx          LL_EXTI_GenerateSWI_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER, ExtiLine);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
+}
+
+
+/**
+  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR, ExtiLine);
+}
+
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* EXTI */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_LL_EXTI_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h
new file mode 100644
index 0000000..14c67ca
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h
@@ -0,0 +1,981 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_LL_GPIO_H
+#define __STM32F7xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
+
+/** @defgroup GPIO_LL GPIO
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL GPIO Init Structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+  * @{
+  */
+#define LL_GPIO_PIN_0                      GPIO_BSRR_BS_0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1                      GPIO_BSRR_BS_1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2                      GPIO_BSRR_BS_2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3                      GPIO_BSRR_BS_3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4                      GPIO_BSRR_BS_4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5                      GPIO_BSRR_BS_5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6                      GPIO_BSRR_BS_6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7                      GPIO_BSRR_BS_7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8                      GPIO_BSRR_BS_8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9                      GPIO_BSRR_BS_9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10                     GPIO_BSRR_BS_10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11                     GPIO_BSRR_BS_11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12                     GPIO_BSRR_BS_12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13                     GPIO_BSRR_BS_13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14                     GPIO_BSRR_BS_14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15                     GPIO_BSRR_BS_15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \
+                                           GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \
+                                           GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \
+                                           GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
+                                           GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
+                                           GPIO_BSRR_BS_15) /*!< Select all pins */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODER0_0  /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODER0_1  /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODER0    /*!< Select analog mode */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+  * @{
+  */
+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+  * @{
+  */
+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed   */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDER_OSPEEDR0   /*!< Select I/O high output speed   */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+  * @{
+  */
+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+  * @{
+  */
+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->MODER,
+                             (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @param  OutputType This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+  * @brief  Return gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Speed This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
+{
+  MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
+             (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
+                             (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Pull This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+  MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+                             (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)),
+             (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+                             (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)),
+             (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+                             (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
+}
+
+
+/**
+  * @brief  Lock configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the
+  *         value of this port bit can no longer be modified until the
+  *         next reset.
+  * @note   Each lock bit freezes a specific configuration register
+  *         (control and alternate function registers).
+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  __IO uint32_t temp;
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  WRITE_REG(GPIOx->LCKR, PinMask);
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  temp = READ_REG(GPIOx->LCKR);
+  (void) temp;
+}
+
+/**
+  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
+  * @param  GPIOx GPIO Port
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+  return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+  * @{
+  */
+
+/**
+  * @brief  Return full input data register value for a dedicated port.
+  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
+  * @param  GPIOx GPIO Port
+  * @retval Input data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Write output data register for the port.
+  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
+  * @param  GPIOx GPIO Port
+  * @param  PortValue Level value for each pin of the port
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+  WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+  * @brief  Return full output data register value for a dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
+  * @param  GPIOx GPIO Port
+  * @retval Output data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Set several pins to high level on dedicated gpio port.
+  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+  * @brief  Set several pins to low level on dedicated gpio port.
+  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, (PinMask << 16));
+}
+
+/**
+  * @brief  Toggle data value for several pin of dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  uint32_t odr = READ_REG(GPIOx->ODR);
+  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_LL_GPIO_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h
new file mode 100644
index 0000000..88e3f70
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h
@@ -0,0 +1,1016 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_LL_PWR_H
+#define __STM32F7xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+#define LL_PWR_CR1_CSBF                    PWR_CR1_CSBF            /*!< Clear standby flag */
+
+#define LL_PWR_CR2_CWUF6                   PWR_CR2_CWUF6           /*!< Clear WKUP pin 6 */
+#define LL_PWR_CR2_CWUF5                   PWR_CR2_CWUF5           /*!< Clear WKUP pin 5 */
+#define LL_PWR_CR2_CWUF4                   PWR_CR2_CWUF4           /*!< Clear WKUP pin 4 */
+#define LL_PWR_CR2_CWUF3                   PWR_CR2_CWUF3           /*!< Clear WKUP pin 3 */
+#define LL_PWR_CR2_CWUF2                   PWR_CR2_CWUF2           /*!< Clear WKUP pin 2 */
+#define LL_PWR_CR2_CWUF1                   PWR_CR2_CWUF1           /*!< Clear WKUP pin 1 */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
+  * @{
+  */
+#define LL_PWR_CSR1_WUIF                   PWR_CSR1_WUIF           /*!< Wakeup flag */
+#define LL_PWR_CSR1_SBF                    PWR_CSR1_SBF            /*!< Standby flag */
+#define LL_PWR_CSR1_PVDO                   PWR_CSR1_PVDO           /*!< Power voltage detector output flag */
+#define LL_PWR_CSR1_BRR                    PWR_CSR1_BRR            /*!< Backup Regulator ready flag */
+#define LL_PWR_CSR1_VOSRDY                 PWR_CSR1_VOSRDY         /*!< Voltage scaling select flag */
+#define LL_PWR_CSR1_ODRDY                  PWR_CSR1_ODRDY          /*!< Over-drive mode ready */
+#define LL_PWR_CSR1_ODSWRDY                PWR_CSR1_ODSWRDY        /*!< Over-drive mode switching ready */
+#define LL_PWR_CSR1_UDRDY                  PWR_CSR1_UDRDY          /*!< Under-drive ready flag */
+
+#define LL_PWR_CSR2_EWUP1                  PWR_CSR2_EWUP1          /*!< Enable WKUP pin 1 */
+#define LL_PWR_CSR2_EWUP2                  PWR_CSR2_EWUP2          /*!< Enable WKUP pin 2 */
+#define LL_PWR_CSR2_EWUP3                  PWR_CSR2_EWUP3          /*!< Enable WKUP pin 3 */
+#define LL_PWR_CSR2_EWUP4                  PWR_CSR2_EWUP4          /*!< Enable WKUP pin 4 */
+#define LL_PWR_CSR2_EWUP5                  PWR_CSR2_EWUP5          /*!< Enable WKUP pin 5 */
+#define LL_PWR_CSR2_EWUP6                  PWR_CSR2_EWUP6          /*!< Enable WKUP pin 6 */
+/**
+  * @}
+  */
+  
+/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
+  * @{
+  */
+#define LL_PWR_MODE_STOP_MAINREGU                     0x00000000U                                    /*!< Enter Stop mode (with main Regulator ON) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE          (PWR_CR1_MRUDS | PWR_CR1_FPDS)                 /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU                       PWR_CR1_LPDS                                   /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE            (PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS)  /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STANDBY                           PWR_CR1_PDDS                                   /*!< Enter Standby mode when the CPU enters deepsleep */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
+  * @{
+  */
+#define LL_PWR_REGU_VOLTAGE_SCALE3         PWR_CR1_VOS_0
+#define LL_PWR_REGU_VOLTAGE_SCALE2         PWR_CR1_VOS_1
+#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR1_VOS_0 | PWR_CR1_VOS_1)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
+  * @{
+  */
+#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U                    /*!< Voltage Regulator in main mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_LOW_POWER   PWR_CR1_LPDS                   /*!< Voltage Regulator in low-power mode during deepsleep mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
+  * @{
+  */
+#define LL_PWR_PVDLEVEL_0                  PWR_CR1_PLS_LEV0      /*!< Voltage threshold detected by PVD 2.0 V */
+#define LL_PWR_PVDLEVEL_1                  PWR_CR1_PLS_LEV1      /*!< Voltage threshold detected by PVD 2.1 V */
+#define LL_PWR_PVDLEVEL_2                  PWR_CR1_PLS_LEV2      /*!< Voltage threshold detected by PVD 2.3 V */
+#define LL_PWR_PVDLEVEL_3                  PWR_CR1_PLS_LEV3      /*!< Voltage threshold detected by PVD 2.5 V */
+#define LL_PWR_PVDLEVEL_4                  PWR_CR1_PLS_LEV4      /*!< Voltage threshold detected by PVD 2.6 V */
+#define LL_PWR_PVDLEVEL_5                  PWR_CR1_PLS_LEV5      /*!< Voltage threshold detected by PVD 2.7 V */
+#define LL_PWR_PVDLEVEL_6                  PWR_CR1_PLS_LEV6      /*!< Voltage threshold detected by PVD 2.8 V */
+#define LL_PWR_PVDLEVEL_7                  PWR_CR1_PLS_LEV7      /*!< Voltage threshold detected by PVD 2.9 V */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN1                 PWR_CSR2_EWUP1        /*!< WKUP pin 1 : PA0  */
+#define LL_PWR_WAKEUP_PIN2                 PWR_CSR2_EWUP2        /*!< WKUP pin 2 : PA2  */
+#define LL_PWR_WAKEUP_PIN3                 PWR_CSR2_EWUP3        /*!< WKUP pin 3 : PC1  */
+#define LL_PWR_WAKEUP_PIN4                 PWR_CSR2_EWUP4        /*!< WKUP pin 4 : PC13 */
+#define LL_PWR_WAKEUP_PIN5                 PWR_CSR2_EWUP5        /*!< WKUP pin 5 : PI8  */
+#define LL_PWR_WAKEUP_PIN6                 PWR_CSR2_EWUP6        /*!< WKUP pin 6 : PI11 */
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+  * @{
+  */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in PWR register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in PWR register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable Under Drive Mode
+  * @rmtoll CR1    UDEN       LL_PWR_EnableUnderDriveMode
+  * @note  This mode is enabled only with STOP low power mode.
+  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+  *        mode is only available when the main Regulator or the low power Regulator 
+  *        is in low voltage mode.      
+  * @note  If the Under-drive mode was enabled, it is automatically disabled after 
+  *        exiting Stop mode. 
+  *        When the voltage Regulator operates in Under-drive mode, an additional  
+  *        startup delay is induced when waking up from Stop mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_UDEN);
+}
+
+/**
+  * @brief  Disable Under Drive Mode
+  * @rmtoll CR1    UDEN       LL_PWR_DisableUnderDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_UDEN);
+}
+
+/**
+  * @brief  Check if Under Drive Mode is enabled
+  * @rmtoll CR1    UDEN       LL_PWR_IsEnabledUnderDriveMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
+{
+  return (READ_BIT(PWR->CR1, PWR_CR1_UDEN) == (PWR_CR1_UDEN));
+}
+
+/**
+  * @brief  Enable Over drive switching
+  * @rmtoll CR1    ODSWEN       LL_PWR_EnableOverDriveSwitching
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_ODSWEN);
+}
+
+/**
+  * @brief  Disable Over drive switching
+  * @rmtoll CR1    ODSWEN       LL_PWR_DisableOverDriveSwitching
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_ODSWEN);
+}
+
+/**
+  * @brief  Check if Over drive switching is enabled
+  * @rmtoll CR1    ODSWEN       LL_PWR_IsEnabledOverDriveSwitching
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
+{
+  return (READ_BIT(PWR->CR1, PWR_CR1_ODSWEN) == (PWR_CR1_ODSWEN));
+}
+
+/**
+  * @brief  Enable Over drive Mode
+  * @rmtoll CR1    ODEN       LL_PWR_EnableOverDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_ODEN);
+}
+
+/**
+  * @brief  Disable Over drive Mode
+  * @rmtoll CR1    ODEN       LL_PWR_DisableOverDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_ODEN);
+}
+
+/**
+  * @brief  Check if Over drive switching is enabled
+  * @rmtoll CR1    ODEN       LL_PWR_IsEnabledOverDriveMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
+{
+  return (READ_BIT(PWR->CR1, PWR_CR1_ODEN) == (PWR_CR1_ODEN));
+}
+
+/**
+  * @brief  Set the main internal Regulator output voltage
+  * @rmtoll CR1    VOS       LL_PWR_SetRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
+}
+
+/**
+  * @brief  Get the main internal Regulator output voltage
+  * @rmtoll CR1    VOS       LL_PWR_GetRegulVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
+}
+
+/**
+  * @brief  Enable Main Regulator in deepsleep under-drive Mode
+  * @rmtoll CR1    MRUDS       LL_PWR_EnableMainRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_MRUDS);
+}
+
+/**
+  * @brief  Disable Main Regulator in deepsleep under-drive Mode
+  * @rmtoll CR1    MRUDS       LL_PWR_DisableMainRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_MRUDS);
+}
+
+/**
+  * @brief  Check if Main Regulator in deepsleep under-drive Mode is enabled
+  * @rmtoll CR1    MRUDS       LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
+{
+  return (READ_BIT(PWR->CR1, PWR_CR1_MRUDS) == (PWR_CR1_MRUDS));
+}
+
+/**
+  * @brief  Enable Low Power Regulator in deepsleep under-drive Mode
+  * @rmtoll CR1    LPUDS       LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_LPUDS);
+}
+
+/**
+  * @brief  Disable Low Power Regulator in deepsleep under-drive Mode
+  * @rmtoll CR1    LPUDS       LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_LPUDS);
+}
+
+/**
+  * @brief  Check if Low Power Regulator in deepsleep under-drive Mode is enabled
+  * @rmtoll CR1    LPUDS       LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
+{
+  return (READ_BIT(PWR->CR1, PWR_CR1_LPUDS) == (PWR_CR1_LPUDS));
+}
+
+/**
+  * @brief  Enable the Flash Power Down in Stop Mode
+  * @rmtoll CR1    FPDS       LL_PWR_EnableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_FPDS);
+}
+
+/**
+  * @brief  Disable the Flash Power Down in Stop Mode
+  * @rmtoll CR1    FPDS       LL_PWR_DisableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_FPDS);
+}
+
+/**
+  * @brief  Check if the Flash Power Down in Stop Mode is enabled
+  * @rmtoll CR1    FPDS       LL_PWR_IsEnabledFlashPowerDown
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
+{
+  return (READ_BIT(PWR->CR1, PWR_CR1_FPDS) == (PWR_CR1_FPDS));
+}
+
+/**
+  * @brief  Enable access to the backup domain
+  * @rmtoll CR1    DBP       LL_PWR_EnableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain
+  * @rmtoll CR1    DBP       LL_PWR_DisableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Check if the backup domain is enabled
+  * @rmtoll CR1    DBP       LL_PWR_IsEnabledBkUpAccess
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+  return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP));
+}
+
+/**
+  * @brief  Enable Backup Regulator
+  * @rmtoll CSR1    BRE       LL_PWR_EnableBkUpRegulator
+  * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
+  *       VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
+  *       SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
+  *       the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
+  *       the data written into the RAM will be maintained in the Standby and VBAT modes.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
+{
+  SET_BIT(PWR->CSR1, PWR_CSR1_BRE);
+}
+
+/**
+  * @brief  Disable Backup Regulator
+  * @rmtoll CSR1    BRE       LL_PWR_DisableBkUpRegulator
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
+{
+  CLEAR_BIT(PWR->CSR1, PWR_CSR1_BRE);
+}
+
+/**
+  * @brief  Check if the backup Regulator is enabled
+  * @rmtoll CSR1    BRE      LL_PWR_IsEnabledBkUpRegulator
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
+{
+  return (READ_BIT(PWR->CSR1, PWR_CSR1_BRE) == (PWR_CSR1_BRE));
+}
+
+/**
+  * @brief  Set voltage Regulator mode during deep sleep mode
+  * @rmtoll CR1    LPDS         LL_PWR_SetRegulModeDS
+  * @param  RegulMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
+}
+
+/**
+  * @brief  Get voltage Regulator mode during deep sleep mode
+  * @rmtoll CR1    LPDS         LL_PWR_GetRegulModeDS
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
+}
+
+/**
+  * @brief  Set Power Down mode when CPU enters deepsleep
+  * @rmtoll CR1    PDDS         LL_PWR_SetPowerMode\n
+  *         CR1    LPDS         LL_PWR_SetPowerMode\n
+  *         CR1    FPDS         LL_PWR_SetPowerMode\n
+  *         CR1    LPUDS        LL_PWR_SetPowerMode\n  
+  *         CR1    MRUDS        LL_PWR_SetPowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS), PDMode);
+}
+
+/**
+  * @brief  Get Power Down mode when CPU enters deepsleep
+  * @rmtoll CR1    PDDS         LL_PWR_GetPowerMode\n
+  *         CR1    LPDS         LL_PWR_GetPowerMode\n
+  *         CR1    FPDS         LL_PWR_GetPowerMode\n
+  *         CR1    LPUDS        LL_PWR_GetPowerMode\n  
+  *         CR1    MRUDS        LL_PWR_GetPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS)));
+}
+
+/**
+  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
+  * @rmtoll CR1    PLS       LL_PWR_SetPVDLevel
+  * @param  PVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
+}
+
+/**
+  * @brief  Get the voltage threshold detection
+  * @rmtoll CR1    PLS       LL_PWR_GetPVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
+}
+
+/**
+  * @brief  Enable Power Voltage Detector
+  * @rmtoll CR1    PVDE       LL_PWR_EnablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_PVDE);
+}
+
+/**
+  * @brief  Disable Power Voltage Detector
+  * @rmtoll CR1    PVDE       LL_PWR_DisablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
+}
+
+/**
+  * @brief  Check if Power Voltage Detector is enabled
+  * @rmtoll CR1    PVDE       LL_PWR_IsEnabledPVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+  return (READ_BIT(PWR->CR1, PWR_CR1_PVDE) == (PWR_CR1_PVDE));
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality
+  * @rmtoll CSR2   EWUP1       LL_PWR_EnableWakeUpPin\n
+  *         CSR2   EWUP2       LL_PWR_EnableWakeUpPin\n
+  *         CSR2   EWUP3       LL_PWR_EnableWakeUpPin\n
+  *         CSR2   EWUP4       LL_PWR_EnableWakeUpPin\n
+  *         CSR2   EWUP5       LL_PWR_EnableWakeUpPin\n
+  *         CSR2   EWUP6       LL_PWR_EnableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->CSR2, WakeUpPin);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality
+  * @rmtoll CSR2   EWUP1       LL_PWR_DisableWakeUpPin\n
+  *         CSR2   EWUP2       LL_PWR_DisableWakeUpPin\n
+  *         CSR2   EWUP3       LL_PWR_DisableWakeUpPin\n
+  *         CSR2   EWUP4       LL_PWR_DisableWakeUpPin\n
+  *         CSR2   EWUP5       LL_PWR_DisableWakeUpPin\n
+  *         CSR2   EWUP6       LL_PWR_DisableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->CSR2, WakeUpPin);
+}
+
+/**
+  * @brief  Check if the WakeUp PINx functionality is enabled
+  * @rmtoll CSR2   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
+  *         CSR2   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
+  *         CSR2   EWUP3       LL_PWR_IsEnabledWakeUpPin\n
+  *         CSR2   EWUP4       LL_PWR_IsEnabledWakeUpPin\n
+  *         CSR2   EWUP5       LL_PWR_IsEnabledWakeUpPin\n
+  *         CSR2   EWUP6       LL_PWR_IsEnabledWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+  return (READ_BIT(PWR->CSR2, WakeUpPin) == (WakeUpPin));
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity low for the event detection
+  * @rmtoll CR2   WUPP1       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR2   WUPP2       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR2   WUPP3       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR2   WUPP4       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR2   WUPP5       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         CR2   WUPP6       LL_PWR_SetWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->CR2, WakeUpPin);
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity high for the event detection
+  * @rmtoll CR2   WUPP1       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR2   WUPP2       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR2   WUPP3       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR2   WUPP4       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR2   WUPP5       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         CR2   WUPP6       LL_PWR_SetWakeUpPinPolarityHigh
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->CR2, WakeUpPin);
+}
+
+/**
+  * @brief  Get the Wake-Up pin polarity for the event detection
+  * @rmtoll CR2   WUPP1       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR2   WUPP2       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR2   WUPP3       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR2   WUPP4       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR2   WUPP5       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         CR2   WUPP6       LL_PWR_IsWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  return (READ_BIT(PWR->CR2, WakeUpPin) == (WakeUpPin));
+}
+
+/**
+  * @brief  Enable Internal WakeUp
+  * @rmtoll CSR1    EIWUP       LL_PWR_EnableInternalWakeUp
+  * @note This API must be used when RTC events (Alarm A or Alarm B, RTC Tamper, RTC TimeStamp
+  *  or RTC Wakeup time) are used to wake up the system from Standby mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableInternalWakeUp(void)
+{
+  SET_BIT(PWR->CSR1, PWR_CSR1_EIWUP);
+}
+
+/**
+  * @brief  Disable Internal WakeUp
+  * @rmtoll CSR1    EIWUP       LL_PWR_DisableInternalWakeUp
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableInternalWakeUp(void)
+{
+  CLEAR_BIT(PWR->CSR1, PWR_CSR1_EIWUP);
+}
+
+/**
+  * @brief  Check if the Internal WakeUp functionality is enabled
+  * @rmtoll CSR1   EIWUP       LL_PWR_IsEnabledInternalWakeUp
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternalWakeUp(void)
+{
+  return (READ_BIT(PWR->CSR1, PWR_CSR1_EIWUP) == (PWR_CSR1_EIWUP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Wake-up Flag 6
+  * @rmtoll CSR2          WUPF6          LL_PWR_IsActiveFlag_WU6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
+{
+  return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF6) == (PWR_CSR2_WUPF6));
+}
+
+/**
+  * @brief  Get Wake-up Flag 5
+  * @rmtoll CSR2          WUPF5          LL_PWR_IsActiveFlag_WU5
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
+{
+  return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF5) == (PWR_CSR2_WUPF5));
+}
+
+/**
+  * @brief  Get Wake-up Flag 4
+  * @rmtoll CSR2          WUPF4          LL_PWR_IsActiveFlag_WU4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
+{
+  return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF4) == (PWR_CSR2_WUPF4));
+}
+
+/**
+  * @brief  Get Wake-up Flag 3
+  * @rmtoll CSR2          WUPF3          LL_PWR_IsActiveFlag_WU3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
+{
+  return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF3) == (PWR_CSR2_WUPF3));
+}
+
+/**
+  * @brief  Get Wake-up Flag 2
+  * @rmtoll CSR2          WUPF2          LL_PWR_IsActiveFlag_WU2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
+{
+  return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF2) == (PWR_CSR2_WUPF2));
+}
+
+/**
+  * @brief  Get Wake-up Flag 1
+  * @rmtoll CSR2          WUPF1          LL_PWR_IsActiveFlag_WU1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
+{
+  return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF1) == (PWR_CSR2_WUPF1));
+}
+
+/**
+  * @brief  Get Standby Flag
+  * @rmtoll CSR1   SBF       LL_PWR_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+  return (READ_BIT(PWR->CSR1, PWR_CSR1_SBF) == (PWR_CSR1_SBF));
+}
+
+/**
+  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
+  * @rmtoll CSR1   PVDO       LL_PWR_IsActiveFlag_PVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+  return (READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO));
+}
+
+/**
+  * @brief  Get Backup Regulator ready Flag
+  * @rmtoll CSR1   BRR       LL_PWR_IsActiveFlag_BRR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
+{
+  return (READ_BIT(PWR->CSR1, PWR_CSR1_BRR) == (PWR_CSR1_BRR));
+}
+
+/**
+  * @brief  Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
+  * @rmtoll CSR1   VOSRDY       LL_PWR_IsActiveFlag_VOS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
+{
+  return (READ_BIT(PWR->CSR1, PWR_CSR1_VOSRDY) == (PWR_CSR1_VOSRDY));
+}
+
+/**
+  * @brief  Indicate whether the Over-Drive mode is ready or not
+  * @rmtoll CSR1   ODRDY       LL_PWR_IsActiveFlag_OD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
+{
+  return (READ_BIT(PWR->CSR1, PWR_CSR1_ODRDY) == (PWR_CSR1_ODRDY));
+}
+
+/**
+  * @brief  Indicate whether the Over-Drive mode switching is ready or not
+  * @rmtoll CSR1   ODSWRDY       LL_PWR_IsActiveFlag_ODSW
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
+{
+  return (READ_BIT(PWR->CSR1, PWR_CSR1_ODSWRDY) == (PWR_CSR1_ODSWRDY));
+}
+
+/**
+  * @brief  Indicate whether the Under-Drive mode is ready or not
+  * @rmtoll CSR1   UDRDY       LL_PWR_IsActiveFlag_UD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
+{
+  return (READ_BIT(PWR->CSR1, PWR_CSR1_UDRDY) == (PWR_CSR1_UDRDY));
+}
+
+/**
+  * @brief  Clear Standby Flag
+  * @rmtoll CR1   CSBF       LL_PWR_ClearFlag_SB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_CSBF);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 6
+  * @rmtoll CR2          CWUF6         LL_PWR_ClearFlag_WU6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
+{
+  WRITE_REG(PWR->CR2, PWR_CR2_CWUPF6);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 5
+  * @rmtoll CR2          CWUF5         LL_PWR_ClearFlag_WU5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
+{
+  WRITE_REG(PWR->CR2, PWR_CR2_CWUPF5);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 4
+  * @rmtoll CR2          CWUF4         LL_PWR_ClearFlag_WU4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
+{
+  WRITE_REG(PWR->CR2, PWR_CR2_CWUPF4);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 3
+  * @rmtoll CR2          CWUF3         LL_PWR_ClearFlag_WU3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
+{
+  WRITE_REG(PWR->CR2, PWR_CR2_CWUPF3);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 2
+  * @rmtoll CR2          CWUF2         LL_PWR_ClearFlag_WU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
+{
+  WRITE_REG(PWR->CR2, PWR_CR2_CWUPF2);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 1
+  * @rmtoll CR2          CWUF1         LL_PWR_ClearFlag_WU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
+{
+  WRITE_REG(PWR->CR2, PWR_CR2_CWUPF1);
+}
+
+/**
+  * @brief  Clear Under-Drive ready Flag
+  * @rmtoll CSR1          UDRDY         LL_PWR_ClearFlag_UD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
+{
+  WRITE_REG(PWR->CSR1, PWR_CSR1_UDRDY);
+}
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(PWR) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_LL_PWR_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h
new file mode 100644
index 0000000..360cc30
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h
@@ -0,0 +1,5170 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_LL_RCC_H
+#define __STM32F7xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  * @{
+  */
+
+#if defined(RCC_DCKCFGR1_PLLSAIDIVR)
+static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
+#endif /* RCC_DCKCFGR1_PLLSAIDIVR */
+
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  * @{
+  */
+
+/**
+  * @brief  RCC Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
+  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
+  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
+  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  * @brief    Defines used to adapt values of different oscillators
+  * @note     These values could be modified in the user environment according to 
+  *           HW set-up.
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+#define EXTERNAL_SAI1_CLOCK_VALUE    48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
+#define EXTERNAL_SAI2_CLOCK_VALUE    48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */
+#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
+  * @{
+  */
+#define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
+#define LL_RCC_CIR_PLLI2SRDYC             RCC_CIR_PLLI2SRDYC  /*!< PLLI2S Ready Interrupt Clear */
+#define LL_RCC_CIR_PLLSAIRDYC             RCC_CIR_PLLSAIRDYC  /*!< PLLSAI Ready Interrupt Clear */
+#define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt Clear */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
+  * @{
+  */
+#define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */
+#define LL_RCC_CIR_PLLI2SRDYF             RCC_CIR_PLLI2SRDYF  /*!< PLLI2S Ready Interrupt flag */
+#define LL_RCC_CIR_PLLSAIRDYF             RCC_CIR_PLLSAIRDYF  /*!< PLLSAI Ready Interrupt flag */
+#define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF        /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
+#define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
+#define LL_RCC_CSR_PORRSTF                 RCC_CSR_PORRSTF    /*!< POR/PDR reset flag */
+#define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
+#define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
+  * @{
+  */
+#define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
+#define LL_RCC_CIR_PLLI2SRDYIE            RCC_CIR_PLLI2SRDYIE   /*!< PLLI2S Ready Interrupt Enable */
+#define LL_RCC_CIR_PLLSAIRDYIE            RCC_CIR_PLLSAIRDYIE   /*!< PLLSAI Ready Interrupt Enable */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
+  * @{
+  */
+#define LL_RCC_LSEDRIVE_LOW                0x00000000U             /*!< Xtal mode lower driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium high driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium low driving capability */
+#define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving capability */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
+  * @{
+  */
+#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
+  * @{
+  */
+#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
+  * @{
+  */
+#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
+  * @{
+  */
+#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)(RCC_CFGR_MCO1|0x00000000U)                    /*!< HSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U))       /*!< LSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U))       /*!< HSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U))       /*!< PLLCLK selection as MCO1 source */
+#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)(RCC_CFGR_MCO2|0x00000000U)                    /*!< SYSCLK selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_PLLI2S           (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U))       /*!< PLLI2S selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U))       /*!< HSE selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U))       /*!< PLLCLK selection as MCO2 source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
+  * @{
+  */
+#define LL_RCC_MCO1_DIV_1                  (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U)                       /*!< MCO1 not divided */
+#define LL_RCC_MCO1_DIV_2                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U))       /*!< MCO1 divided by 2 */
+#define LL_RCC_MCO1_DIV_3                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U))       /*!< MCO1 divided by 3 */
+#define LL_RCC_MCO1_DIV_4                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U))       /*!< MCO1 divided by 4 */
+#define LL_RCC_MCO1_DIV_5                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U))         /*!< MCO1 divided by 5 */
+#define LL_RCC_MCO2_DIV_1                  (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U)                       /*!< MCO2 not divided */
+#define LL_RCC_MCO2_DIV_2                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U))       /*!< MCO2 divided by 2 */
+#define LL_RCC_MCO2_DIV_3                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U))       /*!< MCO2 divided by 3 */
+#define LL_RCC_MCO2_DIV_4                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U))       /*!< MCO2 divided by 4 */
+#define LL_RCC_MCO2_DIV_5                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U))         /*!< MCO2 divided by 5 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
+  * @{
+  */
+#define LL_RCC_RTC_NOCLOCK                  0x00000000U             /*!< HSE not divided */
+#define LL_RCC_RTC_HSE_DIV_2                RCC_CFGR_RTCPRE_1       /*!< HSE clock divided by 2 */
+#define LL_RCC_RTC_HSE_DIV_3                (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 3 */
+#define LL_RCC_RTC_HSE_DIV_4                RCC_CFGR_RTCPRE_2       /*!< HSE clock divided by 4 */
+#define LL_RCC_RTC_HSE_DIV_5                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 5 */
+#define LL_RCC_RTC_HSE_DIV_6                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 6 */
+#define LL_RCC_RTC_HSE_DIV_7                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 7 */
+#define LL_RCC_RTC_HSE_DIV_8                RCC_CFGR_RTCPRE_3       /*!< HSE clock divided by 8 */
+#define LL_RCC_RTC_HSE_DIV_9                (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 9 */
+#define LL_RCC_RTC_HSE_DIV_10               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 10 */
+#define LL_RCC_RTC_HSE_DIV_11               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 11 */
+#define LL_RCC_RTC_HSE_DIV_12               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 12 */
+#define LL_RCC_RTC_HSE_DIV_13               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 13 */
+#define LL_RCC_RTC_HSE_DIV_14               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 14 */
+#define LL_RCC_RTC_HSE_DIV_15               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 15 */
+#define LL_RCC_RTC_HSE_DIV_16               RCC_CFGR_RTCPRE_4       /*!< HSE clock divided by 16 */
+#define LL_RCC_RTC_HSE_DIV_17               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 17 */
+#define LL_RCC_RTC_HSE_DIV_18               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 18 */
+#define LL_RCC_RTC_HSE_DIV_19               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 19 */
+#define LL_RCC_RTC_HSE_DIV_20               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 20 */
+#define LL_RCC_RTC_HSE_DIV_21               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 21 */
+#define LL_RCC_RTC_HSE_DIV_22               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 22 */
+#define LL_RCC_RTC_HSE_DIV_23               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 23 */
+#define LL_RCC_RTC_HSE_DIV_24               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)       /*!< HSE clock divided by 24 */
+#define LL_RCC_RTC_HSE_DIV_25               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 25 */
+#define LL_RCC_RTC_HSE_DIV_26               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 26 */
+#define LL_RCC_RTC_HSE_DIV_27               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 27 */
+#define LL_RCC_RTC_HSE_DIV_28               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 28 */
+#define LL_RCC_RTC_HSE_DIV_29               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 29 */
+#define LL_RCC_RTC_HSE_DIV_30               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 30 */
+#define LL_RCC_RTC_HSE_DIV_31               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 31 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+  * @{
+  */
+#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
+  * @{
+  */
+#define LL_RCC_USART1_CLKSOURCE_PCLK2      (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | 0x00000000U)   /*!< PCLK2 clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL)   /*!< LSE clock used as USART1 clock source */
+#define LL_RCC_USART2_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | 0x00000000U)   /*!< PCLK1 clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL)   /*!< LSE clock used as USART2 clock source */
+#define LL_RCC_USART3_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | 0x00000000U)   /*!< PCLK1 clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL)   /*!< LSE clock used as USART3 clock source */
+#define LL_RCC_USART6_CLKSOURCE_PCLK2      (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | 0x00000000U)   /*!< PCLK2 clock used as USART6 clock source */
+#define LL_RCC_USART6_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_0) /*!< SYSCLK clock used as USART6 clock source */
+#define LL_RCC_USART6_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_1) /*!< HSI clock used as USART6 clock source */
+#define LL_RCC_USART6_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL)   /*!< LSE clock used as USART6 clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_UARTx_CLKSOURCE  Peripheral UART clock source selection
+  * @{
+  */
+#define LL_RCC_UART4_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | 0x00000000U)   /*!< PCLK1 clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL)   /*!< LSE clock used as UART4 clock source */
+#define LL_RCC_UART5_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | 0x00000000U)   /*!< PCLK1 clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL)   /*!< LSE clock used as UART5 clock source */
+#define LL_RCC_UART7_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | 0x00000000U)   /*!< PCLK1 clock used as UART7 clock source */
+#define LL_RCC_UART7_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_0) /*!< SYSCLK clock used as UART7 clock source */
+#define LL_RCC_UART7_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_1) /*!< HSI clock used as UART7 clock source */
+#define LL_RCC_UART7_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL)   /*!< LSE clock used as UART7 clock source */
+#define LL_RCC_UART8_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | 0x00000000U)   /*!< PCLK1 clock used as UART8 clock source */
+#define LL_RCC_UART8_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_0) /*!< SYSCLK clock used as UART8 clock source */
+#define LL_RCC_UART8_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_1) /*!< HSI clock used as UART8 clock source */
+#define LL_RCC_UART8_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL)   /*!< LSE clock used as UART8 clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
+  * @{
+  */
+#define LL_RCC_I2C1_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C1SEL|0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_1 >> 16U)) /*!< HSI clock used as I2C1 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C2SEL|0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_1 >> 16U)) /*!< HSI clock used as I2C2 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C3SEL|0x00000000U) /*!< PCLK1 clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_1 >> 16U)) /*!< HSI clock used as I2C3 clock source */
+#if defined(I2C4)
+#define LL_RCC_I2C4_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C4SEL|0x00000000U) /*!< PCLK1 clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_1 >> 16U)) /*!< HSI clock used as I2C4 clock source */
+#endif /* I2C4 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1       0x00000000U                 /*!< PCLK1 clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI         RCC_DCKCFGR2_LPTIM1SEL_0    /*!< LSI oscillator clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_HSI         RCC_DCKCFGR2_LPTIM1SEL_1    /*!< HSI oscillator clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE         (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0)      /*!< LSE oscillator clock used as LPTIM1 clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
+  * @{
+  */
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR1_SAI1SEL | 0x00000000U)                      /*!< PLLSAI clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_0 >> 16U))  /*!< PLLI2S clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PIN          (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_1 >> 16U))  /*!< External pin clock used as SAI1 clock source */
+#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
+#define LL_RCC_SAI1_CLKSOURCE_PLLSRC       (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL >> 16U))    /*!< Main source clock used as SAI1 clock source */
+#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR1_SAI2SEL | 0x00000000U)                      /*!< PLLSAI clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_0 >> 16U))  /*!< PLLI2S clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PIN          (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_1 >> 16U))  /*!< External pin clock used as SAI2 clock source */
+#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
+#define LL_RCC_SAI2_CLKSOURCE_PLLSRC       (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL >> 16U))    /*!< Main source clock used as SAI2 clock source */
+#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE  Peripheral SDMMC clock source selection
+  * @{
+  */
+#define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK       (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | 0x00000000U)                        /*!< PLL 48M domain clock used as SDMMC1 clock */
+#define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK         (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | (RCC_DCKCFGR2_SDMMC1SEL >> 16U))    /*!< System clock clock used as SDMMC1 clock */
+#if defined(SDMMC2)
+#define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK       (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | 0x00000000U)                        /*!< PLL 48M domain clock used as SDMMC2 clock */
+#define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK         (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | (RCC_DCKCFGR2_SDMMC2SEL >> 16U))    /*!< System clock clock used as SDMMC2 clock */
+#endif /* SDMMC2 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
+  * @{
+  */
+#define LL_RCC_RNG_CLKSOURCE_PLL          0x00000000U            /*!< PLL clock used as RNG clock source */
+#define LL_RCC_RNG_CLKSOURCE_PLLSAI       RCC_DCKCFGR2_CK48MSEL  /*!< PLLSAI clock used as RNG clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
+  * @{
+  */
+#define LL_RCC_USB_CLKSOURCE_PLL          0x00000000U            /*!< PLL clock used as USB clock source */
+#define LL_RCC_USB_CLKSOURCE_PLLSAI       RCC_DCKCFGR2_CK48MSEL  /*!< PLLSAI1 clock used as USB clock source */
+/**
+  * @}
+  */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE_PHY          0x00000000U           /*!< DSI-PHY clock used as DSI byte lane clock source */
+#define LL_RCC_DSI_CLKSOURCE_PLL          RCC_DCKCFGR2_DSISEL   /*!< PLL clock used as DSI byte lane clock source */
+/**
+  * @}
+  */
+#endif /* DSI */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
+  * @{
+  */
+#define LL_RCC_CEC_CLKSOURCE_LSE               0x00000000U                /*!< LSE oscillator clock used as CEC clock */
+#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488        RCC_DCKCFGR2_CECSEL        /*!< HSI oscillator clock divided by 488 used as CEC clock */
+/**
+  * @}
+  */
+#endif /* CEC */
+
+/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE  Peripheral I2S clock source selection
+  * @{
+  */
+#define LL_RCC_I2S1_CLKSOURCE_PLLI2S           0x00000000U                /*!< I2S oscillator clock used as I2S1 clock */
+#define LL_RCC_I2S1_CLKSOURCE_PIN              RCC_CFGR_I2SSRC            /*!< External pin clock used as I2S1 clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE  Peripheral 48Mhz domain clock source selection
+  * @{
+  */
+#define LL_RCC_CK48M_CLKSOURCE_PLL             0x00000000U                /*!< PLL oscillator clock used as 48Mhz domain clock */
+#define LL_RCC_CK48M_CLKSOURCE_PLLSAI          RCC_DCKCFGR2_CK48MSEL      /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
+/**
+  * @}
+  */
+
+#if defined(DFSDM1_Channel0)
+/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE  Peripheral DFSDM Audio clock source selection
+  * @{
+  */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1     0x00000000U                /*!< SAI1 clock used as DFSDM1 Audio clock */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2     RCC_DCKCFGR1_ADFSDM1SEL    /*!< SAI2 clock used as DFSDM1 Audio clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE  Peripheral DFSDM clock source selection
+  * @{
+  */
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as DFSDM1 clock */
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         RCC_DCKCFGR1_DFSDM1SEL     /*!< System clock used as DFSDM1 clock */
+/**
+  * @}
+  */
+#endif /* DFSDM1_Channel0 */
+
+/** @defgroup RCC_LL_EC_USARTx  Peripheral USART get clock source
+  * @{
+  */
+#define LL_RCC_USART1_CLKSOURCE            RCC_DCKCFGR2_USART1SEL /*!< USART1 Clock source selection */
+#define LL_RCC_USART2_CLKSOURCE            RCC_DCKCFGR2_USART2SEL /*!< USART2 Clock source selection */
+#define LL_RCC_USART3_CLKSOURCE            RCC_DCKCFGR2_USART3SEL /*!< USART3 Clock source selection */
+#define LL_RCC_USART6_CLKSOURCE            RCC_DCKCFGR2_USART6SEL /*!< USART6 Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_UARTx  Peripheral UART get clock source
+  * @{
+  */
+#define LL_RCC_UART4_CLKSOURCE             RCC_DCKCFGR2_UART4SEL /*!< UART4 Clock source selection */
+#define LL_RCC_UART5_CLKSOURCE             RCC_DCKCFGR2_UART5SEL /*!< UART5 Clock source selection */
+#define LL_RCC_UART7_CLKSOURCE             RCC_DCKCFGR2_UART7SEL /*!< UART7 Clock source selection */
+#define LL_RCC_UART8_CLKSOURCE             RCC_DCKCFGR2_UART8SEL /*!< UART8 Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2Cx  Peripheral I2C get clock source
+  * @{
+  */
+#define LL_RCC_I2C1_CLKSOURCE              RCC_DCKCFGR2_I2C1SEL  /*!< I2C1 Clock source selection */
+#define LL_RCC_I2C2_CLKSOURCE              RCC_DCKCFGR2_I2C2SEL  /*!< I2C2 Clock source selection */
+#define LL_RCC_I2C3_CLKSOURCE              RCC_DCKCFGR2_I2C3SEL  /*!< I2C3 Clock source selection */
+#if defined(I2C4)
+#define LL_RCC_I2C4_CLKSOURCE              RCC_DCKCFGR2_I2C4SEL  /*!< I2C4 Clock source selection */
+#endif /* I2C4 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIM1  Peripheral LPTIM get clock source
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE            RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source
+  * @{
+  */
+#define LL_RCC_SAI1_CLKSOURCE              RCC_DCKCFGR1_SAI1SEL /*!< SAI1 Clock source selection */
+#define LL_RCC_SAI2_CLKSOURCE              RCC_DCKCFGR1_SAI2SEL /*!< SAI2 Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMCx  Peripheral SDMMC get clock source
+  * @{
+  */
+#define LL_RCC_SDMMC1_CLKSOURCE            RCC_DCKCFGR2_SDMMC1SEL /*!< SDMMC1 Clock source selection */
+#if defined(SDMMC2)
+#define LL_RCC_SDMMC2_CLKSOURCE            RCC_DCKCFGR2_SDMMC2SEL /*!< SDMMC2 Clock source selection */
+#endif /* SDMMC2 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CK48M  Peripheral CK48M get clock source
+  * @{
+  */
+#define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
+  * @{
+  */
+#define LL_RCC_RNG_CLKSOURCE               RCC_DCKCFGR2_CK48MSEL /*!< RNG Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
+  * @{
+  */
+#define LL_RCC_USB_CLKSOURCE               RCC_DCKCFGR2_CK48MSEL /*!< USB Clock source selection */
+/**
+  * @}
+  */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC  Peripheral CEC get clock source
+  * @{
+  */
+#define LL_RCC_CEC_CLKSOURCE               RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
+/**
+  * @}
+  */
+#endif /* CEC */
+
+/** @defgroup RCC_LL_EC_I2S1  Peripheral I2S get clock source
+  * @{
+  */
+#define LL_RCC_I2S1_CLKSOURCE              RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
+/**
+  * @}
+  */
+#if defined(DFSDM1_Channel0)
+/** @defgroup RCC_LL_EC_DFSDM_AUDIO  Peripheral DFSDM Audio get clock source
+  * @{
+  */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE      RCC_DCKCFGR1_ADFSDM1SEL /*!< DFSDM Audio Clock source selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
+  * @{
+  */
+#define LL_RCC_DFSDM1_CLKSOURCE            RCC_DCKCFGR1_DFSDM1SEL /*!< DFSDM Clock source selection */
+/**
+  * @}
+  */
+#endif /* DFSDM1_Channel0 */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE               RCC_DCKCFGR2_DSISEL /*!< DSI Clock source selection */
+/**
+  * @}
+  */
+#endif /* DSI */
+
+#if defined(LTDC)
+/** @defgroup RCC_LL_EC_LTDC  Peripheral LTDC get clock source
+  * @{
+  */
+#define LL_RCC_LTDC_CLKSOURCE              RCC_DCKCFGR1_PLLSAIDIVR /*!< LTDC Clock source selection */
+/**
+  * @}
+  */
+#endif /* LTDC */
+
+#if defined(SPDIFRX)
+/** @defgroup RCC_LL_EC_SPDIFRX  Peripheral SPDIFRX get clock source
+  * @{
+  */
+#define LL_RCC_SPDIFRX1_CLKSOURCE           RCC_PLLI2SCFGR_PLLI2SP /*!< SPDIFRX Clock source selection */
+/**
+  * @}
+  */
+#endif /* SPDIFRX */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+  * @{
+  */
+#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U             /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE           RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
+  * @{
+  */
+#define LL_RCC_TIM_PRESCALER_TWICE          0x00000000U                  /*!< Timers clock to twice PCLK */
+#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     RCC_DCKCFGR1_TIMPRE          /*!< Timers clock to four time PCLK */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLI2S and PLLSAI entry clock source
+  * @{
+  */
+#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLM_DIV  PLL, PLLI2S and PLLSAI division factor
+  * @{
+  */
+#define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
+#define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
+#define LL_RCC_PLLM_DIV_4                  (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
+#define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
+#define LL_RCC_PLLM_DIV_6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
+#define LL_RCC_PLLM_DIV_7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
+#define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
+#define LL_RCC_PLLM_DIV_9                  (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
+#define LL_RCC_PLLM_DIV_10                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
+#define LL_RCC_PLLM_DIV_11                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
+#define LL_RCC_PLLM_DIV_12                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
+#define LL_RCC_PLLM_DIV_13                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
+#define LL_RCC_PLLM_DIV_14                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
+#define LL_RCC_PLLM_DIV_15                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
+#define LL_RCC_PLLM_DIV_16                 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
+#define LL_RCC_PLLM_DIV_17                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
+#define LL_RCC_PLLM_DIV_18                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
+#define LL_RCC_PLLM_DIV_19                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
+#define LL_RCC_PLLM_DIV_20                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
+#define LL_RCC_PLLM_DIV_21                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
+#define LL_RCC_PLLM_DIV_22                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
+#define LL_RCC_PLLM_DIV_23                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
+#define LL_RCC_PLLM_DIV_24                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
+#define LL_RCC_PLLM_DIV_25                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
+#define LL_RCC_PLLM_DIV_26                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
+#define LL_RCC_PLLM_DIV_27                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
+#define LL_RCC_PLLM_DIV_28                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
+#define LL_RCC_PLLM_DIV_29                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
+#define LL_RCC_PLLM_DIV_30                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
+#define LL_RCC_PLLM_DIV_31                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
+#define LL_RCC_PLLM_DIV_32                 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
+#define LL_RCC_PLLM_DIV_33                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
+#define LL_RCC_PLLM_DIV_34                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
+#define LL_RCC_PLLM_DIV_35                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
+#define LL_RCC_PLLM_DIV_36                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
+#define LL_RCC_PLLM_DIV_37                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
+#define LL_RCC_PLLM_DIV_38                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
+#define LL_RCC_PLLM_DIV_39                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
+#define LL_RCC_PLLM_DIV_40                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
+#define LL_RCC_PLLM_DIV_41                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
+#define LL_RCC_PLLM_DIV_42                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
+#define LL_RCC_PLLM_DIV_43                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
+#define LL_RCC_PLLM_DIV_44                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
+#define LL_RCC_PLLM_DIV_45                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
+#define LL_RCC_PLLM_DIV_46                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
+#define LL_RCC_PLLM_DIV_47                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
+#define LL_RCC_PLLM_DIV_48                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
+#define LL_RCC_PLLM_DIV_49                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
+#define LL_RCC_PLLM_DIV_50                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
+#define LL_RCC_PLLM_DIV_51                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
+#define LL_RCC_PLLM_DIV_52                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
+#define LL_RCC_PLLM_DIV_53                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
+#define LL_RCC_PLLM_DIV_54                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
+#define LL_RCC_PLLM_DIV_55                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
+#define LL_RCC_PLLM_DIV_56                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
+#define LL_RCC_PLLM_DIV_57                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
+#define LL_RCC_PLLM_DIV_58                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
+#define LL_RCC_PLLM_DIV_59                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
+#define LL_RCC_PLLM_DIV_60                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
+#define LL_RCC_PLLM_DIV_61                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
+#define LL_RCC_PLLM_DIV_62                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
+#define LL_RCC_PLLM_DIV_63                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLCFGR_PLLR)
+/** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
+  * @{
+  */
+#define LL_RCC_PLLR_DIV_2                  (RCC_PLLCFGR_PLLR_1)                     /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
+#define LL_RCC_PLLR_DIV_3                  (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
+#define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_2)                     /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
+#define LL_RCC_PLLR_DIV_5                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
+#define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)  /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
+#define LL_RCC_PLLR_DIV_7                  (RCC_PLLCFGR_PLLR)                       /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLCFGR_PLLR */
+
+/** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
+  * @{
+  */
+#define LL_RCC_PLLP_DIV_2                  0x00000000U            /*!< Main PLL division factor for PLLP output by 2 */
+#define LL_RCC_PLLP_DIV_4                  RCC_PLLCFGR_PLLP_0     /*!< Main PLL division factor for PLLP output by 4 */
+#define LL_RCC_PLLP_DIV_6                  RCC_PLLCFGR_PLLP_1     /*!< Main PLL division factor for PLLP output by 6 */
+#define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)   /*!< Main PLL division factor for PLLP output by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
+  * @{
+  */
+#define LL_RCC_PLLQ_DIV_2                  RCC_PLLCFGR_PLLQ_1                      /*!< Main PLL division factor for PLLQ output by 2 */
+#define LL_RCC_PLLQ_DIV_3                  (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
+#define LL_RCC_PLLQ_DIV_4                  RCC_PLLCFGR_PLLQ_2                      /*!< Main PLL division factor for PLLQ output by 4 */
+#define LL_RCC_PLLQ_DIV_5                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
+#define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
+#define LL_RCC_PLLQ_DIV_7                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
+#define LL_RCC_PLLQ_DIV_8                  RCC_PLLCFGR_PLLQ_3                      /*!< Main PLL division factor for PLLQ output by 8 */
+#define LL_RCC_PLLQ_DIV_9                  (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
+#define LL_RCC_PLLQ_DIV_10                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
+#define LL_RCC_PLLQ_DIV_11                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
+#define LL_RCC_PLLQ_DIV_12                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
+#define LL_RCC_PLLQ_DIV_13                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
+#define LL_RCC_PLLQ_DIV_14                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
+#define LL_RCC_PLLQ_DIV_15                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLL_SPRE_SEL  PLL Spread Spectrum Selection
+  * @{
+  */
+#define LL_RCC_SPREAD_SELECT_CENTER        0x00000000U                   /*!< PLL center spread spectrum selection */
+#define LL_RCC_SPREAD_SELECT_DOWN          RCC_SSCGR_SPREADSEL           /*!< PLL down spread spectrum selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLI2SQ  PLLI2SQ division factor (PLLI2SQ)
+  * @{
+  */
+#define LL_RCC_PLLI2SQ_DIV_2              RCC_PLLI2SCFGR_PLLI2SQ_1        /*!< PLLI2S division factor for PLLI2SQ output by 2 */
+#define LL_RCC_PLLI2SQ_DIV_3              (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 3 */
+#define LL_RCC_PLLI2SQ_DIV_4              RCC_PLLI2SCFGR_PLLI2SQ_2        /*!< PLLI2S division factor for PLLI2SQ output by 4 */
+#define LL_RCC_PLLI2SQ_DIV_5              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 5 */
+#define LL_RCC_PLLI2SQ_DIV_6              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 6 */
+#define LL_RCC_PLLI2SQ_DIV_7              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 7 */
+#define LL_RCC_PLLI2SQ_DIV_8              RCC_PLLI2SCFGR_PLLI2SQ_3        /*!< PLLI2S division factor for PLLI2SQ output by 8 */
+#define LL_RCC_PLLI2SQ_DIV_9              (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 9 */
+#define LL_RCC_PLLI2SQ_DIV_10             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 10 */
+#define LL_RCC_PLLI2SQ_DIV_11             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 11 */
+#define LL_RCC_PLLI2SQ_DIV_12             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2)        /*!< PLLI2S division factor for PLLI2SQ output by 12 */
+#define LL_RCC_PLLI2SQ_DIV_13             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 13 */
+#define LL_RCC_PLLI2SQ_DIV_14             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 14 */
+#define LL_RCC_PLLI2SQ_DIV_15             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 15 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLI2SDIVQ  PLLI2SDIVQ division factor (PLLI2SDIVQ)
+  * @{
+  */
+#define LL_RCC_PLLI2SDIVQ_DIV_1           0x00000000U                        /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
+#define LL_RCC_PLLI2SDIVQ_DIV_2           RCC_DCKCFGR1_PLLI2SDIVQ_0          /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
+#define LL_RCC_PLLI2SDIVQ_DIV_3           RCC_DCKCFGR1_PLLI2SDIVQ_1          /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
+#define LL_RCC_PLLI2SDIVQ_DIV_4           (RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
+#define LL_RCC_PLLI2SDIVQ_DIV_5           RCC_DCKCFGR1_PLLI2SDIVQ_2          /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
+#define LL_RCC_PLLI2SDIVQ_DIV_6           (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
+#define LL_RCC_PLLI2SDIVQ_DIV_7           (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
+#define LL_RCC_PLLI2SDIVQ_DIV_8           (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
+#define LL_RCC_PLLI2SDIVQ_DIV_9           RCC_DCKCFGR1_PLLI2SDIVQ_3          /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
+#define LL_RCC_PLLI2SDIVQ_DIV_10          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
+#define LL_RCC_PLLI2SDIVQ_DIV_11          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
+#define LL_RCC_PLLI2SDIVQ_DIV_12          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
+#define LL_RCC_PLLI2SDIVQ_DIV_13          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
+#define LL_RCC_PLLI2SDIVQ_DIV_14          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
+#define LL_RCC_PLLI2SDIVQ_DIV_15          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
+#define LL_RCC_PLLI2SDIVQ_DIV_16          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
+#define LL_RCC_PLLI2SDIVQ_DIV_17          RCC_DCKCFGR1_PLLI2SDIVQ_4          /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
+#define LL_RCC_PLLI2SDIVQ_DIV_18          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
+#define LL_RCC_PLLI2SDIVQ_DIV_19          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
+#define LL_RCC_PLLI2SDIVQ_DIV_20          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
+#define LL_RCC_PLLI2SDIVQ_DIV_21          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
+#define LL_RCC_PLLI2SDIVQ_DIV_22          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
+#define LL_RCC_PLLI2SDIVQ_DIV_23          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
+#define LL_RCC_PLLI2SDIVQ_DIV_24          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
+#define LL_RCC_PLLI2SDIVQ_DIV_25          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
+#define LL_RCC_PLLI2SDIVQ_DIV_26          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
+#define LL_RCC_PLLI2SDIVQ_DIV_27          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
+#define LL_RCC_PLLI2SDIVQ_DIV_28          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
+#define LL_RCC_PLLI2SDIVQ_DIV_29          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
+#define LL_RCC_PLLI2SDIVQ_DIV_30          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
+#define LL_RCC_PLLI2SDIVQ_DIV_31          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
+#define LL_RCC_PLLI2SDIVQ_DIV_32          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLI2SR  PLLI2SR division factor (PLLI2SR)
+  * @{
+  */
+#define LL_RCC_PLLI2SR_DIV_2              RCC_PLLI2SCFGR_PLLI2SR_1                                     /*!< PLLI2S division factor for PLLI2SR output by 2 */
+#define LL_RCC_PLLI2SR_DIV_3              (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 3 */
+#define LL_RCC_PLLI2SR_DIV_4              RCC_PLLI2SCFGR_PLLI2SR_2                                     /*!< PLLI2S division factor for PLLI2SR output by 4 */
+#define LL_RCC_PLLI2SR_DIV_5              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 5 */
+#define LL_RCC_PLLI2SR_DIV_6              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1)        /*!< PLLI2S division factor for PLLI2SR output by 6 */
+#define LL_RCC_PLLI2SR_DIV_7              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 7 */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+/** @defgroup RCC_LL_EC_PLLI2SP  PLLI2SP division factor (PLLI2SP)
+  * @{
+  */
+#define LL_RCC_PLLI2SP_DIV_2              0x00000000U            /*!< PLLI2S division factor for PLLI2SP output by 2 */
+#define LL_RCC_PLLI2SP_DIV_4              RCC_PLLI2SCFGR_PLLI2SP_0        /*!< PLLI2S division factor for PLLI2SP output by 4 */
+#define LL_RCC_PLLI2SP_DIV_6              RCC_PLLI2SCFGR_PLLI2SP_1        /*!< PLLI2S division factor for PLLI2SP output by 6 */
+#define LL_RCC_PLLI2SP_DIV_8              (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0)        /*!< PLLI2S division factor for PLLI2SP output by 8 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+
+/** @defgroup RCC_LL_EC_PLLSAIQ  PLLSAIQ division factor (PLLSAIQ)
+  * @{
+  */
+#define LL_RCC_PLLSAIQ_DIV_2              RCC_PLLSAICFGR_PLLSAIQ_1        /*!< PLLSAI division factor for PLLSAIQ output by 2 */
+#define LL_RCC_PLLSAIQ_DIV_3              (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 3 */
+#define LL_RCC_PLLSAIQ_DIV_4              RCC_PLLSAICFGR_PLLSAIQ_2        /*!< PLLSAI division factor for PLLSAIQ output by 4 */
+#define LL_RCC_PLLSAIQ_DIV_5              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 5 */
+#define LL_RCC_PLLSAIQ_DIV_6              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 6 */
+#define LL_RCC_PLLSAIQ_DIV_7              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 7 */
+#define LL_RCC_PLLSAIQ_DIV_8              RCC_PLLSAICFGR_PLLSAIQ_3        /*!< PLLSAI division factor for PLLSAIQ output by 8 */
+#define LL_RCC_PLLSAIQ_DIV_9              (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 9 */
+#define LL_RCC_PLLSAIQ_DIV_10             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 10 */
+#define LL_RCC_PLLSAIQ_DIV_11             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 11 */
+#define LL_RCC_PLLSAIQ_DIV_12             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2)        /*!< PLLSAI division factor for PLLSAIQ output by 12 */
+#define LL_RCC_PLLSAIQ_DIV_13             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 13 */
+#define LL_RCC_PLLSAIQ_DIV_14             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 14 */
+#define LL_RCC_PLLSAIQ_DIV_15             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 15 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLSAIDIVQ  PLLSAIDIVQ division factor (PLLSAIDIVQ)
+  * @{
+  */
+#define LL_RCC_PLLSAIDIVQ_DIV_1           0x00000000U               /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
+#define LL_RCC_PLLSAIDIVQ_DIV_2           RCC_DCKCFGR1_PLLSAIDIVQ_0          /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
+#define LL_RCC_PLLSAIDIVQ_DIV_3           RCC_DCKCFGR1_PLLSAIDIVQ_1          /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
+#define LL_RCC_PLLSAIDIVQ_DIV_4           (RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
+#define LL_RCC_PLLSAIDIVQ_DIV_5           RCC_DCKCFGR1_PLLSAIDIVQ_2          /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
+#define LL_RCC_PLLSAIDIVQ_DIV_6           (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
+#define LL_RCC_PLLSAIDIVQ_DIV_7           (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
+#define LL_RCC_PLLSAIDIVQ_DIV_8           (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
+#define LL_RCC_PLLSAIDIVQ_DIV_9           RCC_DCKCFGR1_PLLSAIDIVQ_3          /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
+#define LL_RCC_PLLSAIDIVQ_DIV_10          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
+#define LL_RCC_PLLSAIDIVQ_DIV_11          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
+#define LL_RCC_PLLSAIDIVQ_DIV_12          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
+#define LL_RCC_PLLSAIDIVQ_DIV_13          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
+#define LL_RCC_PLLSAIDIVQ_DIV_14          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
+#define LL_RCC_PLLSAIDIVQ_DIV_15          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
+#define LL_RCC_PLLSAIDIVQ_DIV_16          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
+#define LL_RCC_PLLSAIDIVQ_DIV_17          RCC_DCKCFGR1_PLLSAIDIVQ_4         /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
+#define LL_RCC_PLLSAIDIVQ_DIV_18          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
+#define LL_RCC_PLLSAIDIVQ_DIV_19          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
+#define LL_RCC_PLLSAIDIVQ_DIV_20          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
+#define LL_RCC_PLLSAIDIVQ_DIV_21          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
+#define LL_RCC_PLLSAIDIVQ_DIV_22          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
+#define LL_RCC_PLLSAIDIVQ_DIV_23          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
+#define LL_RCC_PLLSAIDIVQ_DIV_24          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
+#define LL_RCC_PLLSAIDIVQ_DIV_25          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
+#define LL_RCC_PLLSAIDIVQ_DIV_26          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
+#define LL_RCC_PLLSAIDIVQ_DIV_27          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
+#define LL_RCC_PLLSAIDIVQ_DIV_28          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
+#define LL_RCC_PLLSAIDIVQ_DIV_29          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
+#define LL_RCC_PLLSAIDIVQ_DIV_30          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
+#define LL_RCC_PLLSAIDIVQ_DIV_31          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
+#define LL_RCC_PLLSAIDIVQ_DIV_32          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+/** @defgroup RCC_LL_EC_PLLSAIR  PLLSAIR division factor (PLLSAIR)
+  * @{
+  */
+#define LL_RCC_PLLSAIR_DIV_2              RCC_PLLSAICFGR_PLLSAIR_1                                     /*!< PLLSAI division factor for PLLSAIR output by 2 */
+#define LL_RCC_PLLSAIR_DIV_3              (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 3 */
+#define LL_RCC_PLLSAIR_DIV_4              RCC_PLLSAICFGR_PLLSAIR_2                                     /*!< PLLSAI division factor for PLLSAIR output by 4 */
+#define LL_RCC_PLLSAIR_DIV_5              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 5 */
+#define LL_RCC_PLLSAIR_DIV_6              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1)        /*!< PLLSAI division factor for PLLSAIR output by 6 */
+#define LL_RCC_PLLSAIR_DIV_7              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 7 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+#if defined(RCC_DCKCFGR1_PLLSAIDIVR)
+/** @defgroup RCC_LL_EC_PLLSAIDIVR  PLLSAIDIVR division factor (PLLSAIDIVR)
+  * @{
+  */
+#define LL_RCC_PLLSAIDIVR_DIV_2           0x00000000U             /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
+#define LL_RCC_PLLSAIDIVR_DIV_4           RCC_DCKCFGR1_PLLSAIDIVR_0        /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
+#define LL_RCC_PLLSAIDIVR_DIV_8           RCC_DCKCFGR1_PLLSAIDIVR_1        /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
+#define LL_RCC_PLLSAIDIVR_DIV_16          (RCC_DCKCFGR1_PLLSAIDIVR_1 | RCC_DCKCFGR1_PLLSAIDIVR_0)        /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR1_PLLSAIDIVR */
+
+/** @defgroup RCC_LL_EC_PLLSAIP  PLLSAIP division factor (PLLSAIP)
+  * @{
+  */
+#define LL_RCC_PLLSAIP_DIV_2              0x00000000U               /*!< PLLSAI division factor for PLLSAIP output by 2 */
+#define LL_RCC_PLLSAIP_DIV_4              RCC_PLLSAICFGR_PLLSAIP_0        /*!< PLLSAI division factor for PLLSAIP output by 4 */
+#define LL_RCC_PLLSAIP_DIV_6              RCC_PLLSAICFGR_PLLSAIP_1        /*!< PLLSAI division factor for PLLSAIP output by 6 */
+#define LL_RCC_PLLSAIP_DIV_8              (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0)        /*!< PLLSAI division factor for PLLSAIP output by 8 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RCC register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RCC register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency on system domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
+
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_3
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_5
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_7
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  *         @arg @ref LL_RCC_PLLQ_DIV_9
+  *         @arg @ref LL_RCC_PLLQ_DIV_10
+  *         @arg @ref LL_RCC_PLLQ_DIV_11
+  *         @arg @ref LL_RCC_PLLQ_DIV_12
+  *         @arg @ref LL_RCC_PLLQ_DIV_13
+  *         @arg @ref LL_RCC_PLLQ_DIV_14
+  *         @arg @ref LL_RCC_PLLQ_DIV_15
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
+
+#if defined(DSI)
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on DSI
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* DSI */
+
+/**
+  * @brief  Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLSAIN__ Between 50 and 432
+  * @param  __PLLSAIQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+  * @param  __PLLSAIDIVQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+                   (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos) + 1U)))
+
+/**
+  * @brief  Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLSAIN__ Between 50 and 432
+  * @param  __PLLSAIP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+                   ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U))
+
+#if defined(LTDC)
+/**
+  * @brief  Helper macro to calculate the PLLSAI frequency used for LTDC domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLSAIN__ Between 50 and 432
+  * @param  __PLLSAIR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+  * @param  __PLLSAIDIVR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+                   (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos])))
+#endif /* LTDC */
+
+/**
+  * @brief  Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains
+  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLI2SN__ Between 50 and 432
+  * @param  __PLLI2SQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+  * @param  __PLLI2SDIVQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   (((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos) + 1U)))
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
+  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLI2SN__ Between 50 and 432
+  * @param  __PLLI2SP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
+#endif /* SPDIFRX */
+
+/**
+  * @brief  Helper macro to calculate the PLLI2S frequency used for I2S domain
+  * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLI2SN__ Between 50 and 432
+  * @param  __PLLI2SR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
+
+/**
+  * @brief  Helper macro to calculate the HCLK frequency
+  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval HCLK clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
+
+/**
+  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
+
+/**
+  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System.
+  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+  * @brief  Enable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Disable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Enable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Disable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Check if HSE oscillator Ready
+  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Disable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Check if HSI clock is ready
+  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+}
+
+/**
+  * @brief  Get HSI Calibration value
+  * @note When HSITRIM is written, HSICAL is updated with the sum of
+  *       HSITRIM and the factory trim value
+  * @rmtoll CR        HSICAL        LL_RCC_HSI_GetCalibration
+  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
+}
+
+/**
+  * @brief  Set HSI Calibration trimming
+  * @note user-programmable trimming value that is added to the HSICAL
+  * @note Default value is 16, which, when added to the HSICAL value,
+  *       should trim the HSI to 16 MHz +/- 1 %
+  * @rmtoll CR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
+  * @param  Value Between Min_Data = 0 and Max_Data = 31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI Calibration trimming
+  * @rmtoll CR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
+  * @retval Between Min_Data = 0 and Max_Data = 31
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+  * @{
+  */
+
+/**
+  * @brief  Enable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Disable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Enable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Disable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Set LSE oscillator drive capability
+  * @note The oscillator is in Xtal mode when it is not in bypass mode.
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
+  * @param  LSEDrive This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+}
+
+/**
+  * @brief  Get LSE oscillator drive capability
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+}
+
+/**
+  * @brief  Check if LSE oscillator Ready
+  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Disable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Check if LSI is Ready
+  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_System System
+  * @{
+  */
+
+/**
+  * @brief  Configure the system clock source
+  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+  * @brief  Get the system clock source
+  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Set AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+  * @brief  Set APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+  * @brief  Set APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+  * @brief  Get AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+  * @brief  Get APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+  * @brief  Get APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+  * @{
+  */
+
+/**
+  * @brief  Configure MCOx
+  * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
+  * @param  MCOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
+  *         @arg @ref LL_RCC_MCO2SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
+  * @param  MCOxPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1_DIV_1
+  *         @arg @ref LL_RCC_MCO1_DIV_2
+  *         @arg @ref LL_RCC_MCO1_DIV_3
+  *         @arg @ref LL_RCC_MCO1_DIV_4
+  *         @arg @ref LL_RCC_MCO1_DIV_5
+  *         @arg @ref LL_RCC_MCO2_DIV_1
+  *         @arg @ref LL_RCC_MCO2_DIV_2
+  *         @arg @ref LL_RCC_MCO2_DIV_3
+  *         @arg @ref LL_RCC_MCO2_DIV_4
+  *         @arg @ref LL_RCC_MCO2_DIV_5
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+  MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U),  (MCOxSource << 16U) | (MCOxPrescaler << 16U));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+  * @{
+  */
+
+/**
+  * @brief  Configure USARTx clock source
+  * @rmtoll DCKCFGR2        USART1SEL     LL_RCC_SetUSARTClockSource\n
+  *         DCKCFGR2        USART2SEL     LL_RCC_SetUSARTClockSource\n
+  *         DCKCFGR2        USART3SEL     LL_RCC_SetUSARTClockSource\n
+  *         DCKCFGR2        USART6SEL     LL_RCC_SetUSARTClockSource
+  * @param  USARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
+}
+
+/**
+  * @brief  Configure UARTx clock source
+  * @rmtoll DCKCFGR2        UART4SEL      LL_RCC_SetUARTClockSource\n
+  *         DCKCFGR2        UART5SEL      LL_RCC_SetUARTClockSource\n
+  *         DCKCFGR2        UART7SEL      LL_RCC_SetUARTClockSource\n
+  *         DCKCFGR2        UART8SEL      LL_RCC_SetUARTClockSource
+  * @param  UARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
+}
+
+/**
+  * @brief  Configure I2Cx clock source
+  * @rmtoll DCKCFGR2        I2C1SEL       LL_RCC_SetI2CClockSource\n
+  *         DCKCFGR2        I2C2SEL       LL_RCC_SetI2CClockSource\n
+  *         DCKCFGR2        I2C3SEL       LL_RCC_SetI2CClockSource\n
+  *         DCKCFGR2        I2C4SEL       LL_RCC_SetI2CClockSource
+  * @param  I2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U),  (I2CxSource << 16U));
+}
+
+/**
+  * @brief  Configure LPTIMx clock source
+  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_SetLPTIMClockSource
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
+}
+
+/**
+  * @brief  Configure SAIx clock source
+  * @rmtoll DCKCFGR1        SAI1SEL       LL_RCC_SetSAIClockSource\n
+  *         DCKCFGR1        SAI2SEL       LL_RCC_SetSAIClockSource
+  * @param  SAIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
+}
+
+/**
+  * @brief  Configure SDMMC clock source
+  * @rmtoll DCKCFGR2        SDMMC1SEL      LL_RCC_SetSDMMCClockSource\n
+  *         DCKCFGR2        SDMMC2SEL      LL_RCC_SetSDMMCClockSource
+  * @param  SDMMCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U));
+}
+
+/**
+  * @brief  Configure 48Mhz domain clock source
+  * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_SetCK48MClockSource
+  * @param  CK48MxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
+}
+
+/**
+  * @brief  Configure RNG clock source
+  * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_SetRNGClockSource
+  * @param  RNGxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
+}
+
+/**
+  * @brief  Configure USB clock source
+  * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_SetUSBClockSource
+  * @param  USBxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
+}
+
+#if defined(CEC)
+/**
+  * @brief  Configure CEC clock source
+  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_SetCECClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
+}
+#endif /* CEC */
+
+/**
+  * @brief  Configure I2S clock source
+  * @rmtoll CFGR         I2SSRC        LL_RCC_SetI2SClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
+}
+
+#if defined(DSI)
+/**
+  * @brief  Configure DSI clock source
+  * @rmtoll DCKCFGR2         DSISEL        LL_RCC_SetDSIClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source);
+}
+#endif /* DSI */
+
+#if defined(DFSDM1_Channel0)
+/**
+  * @brief  Configure DFSDM Audio clock source
+  * @rmtoll DCKCFGR1         ADFSDM1SEL        LL_RCC_SetDFSDMAudioClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source);
+}
+
+/**
+  * @brief  Configure DFSDM Kernel clock source
+  * @rmtoll DCKCFGR1         DFSDM1SEL        LL_RCC_SetDFSDMClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source);
+}
+#endif /* DFSDM1_Channel0 */
+
+/**
+  * @brief  Get USARTx clock source
+  * @rmtoll DCKCFGR2        USART1SEL     LL_RCC_GetUSARTClockSource\n
+  *         DCKCFGR2        USART2SEL     LL_RCC_GetUSARTClockSource\n
+  *         DCKCFGR2        USART3SEL     LL_RCC_GetUSARTClockSource\n
+  *         DCKCFGR2        USART6SEL     LL_RCC_GetUSARTClockSource
+  * @param  USARTx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U));
+}
+
+/**
+  * @brief  Get UARTx clock source
+  * @rmtoll DCKCFGR2        UART4SEL      LL_RCC_GetUARTClockSource\n
+  *         DCKCFGR2        UART5SEL      LL_RCC_GetUARTClockSource\n
+  *         DCKCFGR2        UART7SEL      LL_RCC_GetUARTClockSource\n
+  *         DCKCFGR2        UART8SEL      LL_RCC_GetUARTClockSource
+  * @param  UARTx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U));
+}
+
+/**
+  * @brief  Get I2Cx clock source
+  * @rmtoll DCKCFGR2        I2C1SEL       LL_RCC_GetI2CClockSource\n
+  *         DCKCFGR2        I2C2SEL       LL_RCC_GetI2CClockSource\n
+  *         DCKCFGR2        I2C3SEL       LL_RCC_GetI2CClockSource\n
+  *         DCKCFGR2        I2C4SEL       LL_RCC_GetI2CClockSource
+  * @param  I2Cx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+  *
+  *         (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
+{
+  return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx);
+}
+
+/**
+  * @brief  Get LPTIMx clock source
+  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_GetLPTIMClockSource
+  * @param  LPTIMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
+}
+
+/**
+  * @brief  Get SAIx clock source
+  * @rmtoll DCKCFGR1        SAI1SEL       LL_RCC_GetSAIClockSource\n
+  *         DCKCFGR1        SAI2SEL       LL_RCC_GetSAIClockSource
+  * @param  SAIx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U | SAIx);
+}
+
+/**
+  * @brief  Get SDMMCx clock source
+  * @rmtoll DCKCFGR2        SDMMC1SEL      LL_RCC_GetSDMMCClockSource\n
+  *         DCKCFGR2        SDMMC2SEL      LL_RCC_GetSDMMCClockSource
+  * @param  SDMMCx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx);
+}
+
+/**
+  * @brief  Get 48Mhz domain clock source
+  * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_GetCK48MClockSource
+  * @param  CK48Mx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
+}
+
+/**
+  * @brief  Get RNGx clock source
+  * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_GetRNGClockSource
+  * @param  RNGx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
+}
+
+/**
+  * @brief  Get USBx clock source
+  * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_GetUSBClockSource
+  * @param  USBx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
+}
+
+#if defined(CEC)
+/**
+  * @brief  Get CEC Clock Source
+  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_GetCECClockSource
+  * @param  CECx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
+}
+#endif /* CEC */
+
+/**
+  * @brief  Get I2S Clock Source
+  * @rmtoll CFGR         I2SSRC        LL_RCC_GetI2SClockSource
+  * @param  I2Sx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
+}
+
+#if defined(DFSDM1_Channel0)
+/**
+  * @brief  Get DFSDM Audio Clock Source
+  * @rmtoll DCKCFGR1         ADFSDM1SEL        LL_RCC_GetDFSDMAudioClockSource
+  * @param  DFSDMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
+}
+
+/**
+  * @brief  Get DFSDM Audio Clock Source
+  * @rmtoll DCKCFGR1         DFSDM1SEL        LL_RCC_GetDFSDMClockSource
+  * @param  DFSDMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
+}
+#endif /* DFSDM1_Channel0 */
+
+#if defined(DSI)
+/**
+  * @brief  Get DSI Clock Source
+  * @rmtoll DCKCFGR2         DSISEL        LL_RCC_GetDSIClockSource
+  * @param  DSIx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx));
+}
+#endif /* DSI */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+  * @{
+  */
+
+/**
+  * @brief  Set RTC Clock Source
+  * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
+  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+  *       set). The BDRST bit can be used to reset them.
+  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+  * @brief  Get RTC Clock Source
+  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+  * @brief  Enable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Disable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Check if RTC has been enabled or not
+  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+  return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
+}
+
+/**
+  * @brief  Force the Backup domain reset
+  * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @brief  Release the Backup domain reset
+  * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @brief  Set HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
+}
+
+/**
+  * @brief  Get HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
+  * @{
+  */
+
+/**
+  * @brief  Set Timers Clock Prescalers
+  * @rmtoll DCKCFGR1         TIMPRE        LL_RCC_SetTIMPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler);
+}
+
+/**
+  * @brief  Get Timers Clock Prescalers
+  * @rmtoll DCKCFGR1         TIMPRE        LL_RCC_GetTIMPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+  * @{
+  */
+
+/**
+  * @brief  Enable PLL
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Disable PLL
+  * @note Cannot be disabled if the PLL clock is used as the system clock
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Check if PLL Ready
+  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+}
+
+/**
+  * @brief  Configure PLL used for SYSCLK Domain
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLP can be written only when PLL is disabled
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SYS
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+}
+
+/**
+  * @brief  Configure PLL used for 48Mhz domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLQ can be written only when PLL is disabled
+  * @note This  can be selected for USB, RNG, SDMMC1
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_3
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_5
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_7
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  *         @arg @ref LL_RCC_PLLQ_DIV_9
+  *         @arg @ref LL_RCC_PLLQ_DIV_10
+  *         @arg @ref LL_RCC_PLLQ_DIV_11
+  *         @arg @ref LL_RCC_PLLQ_DIV_12
+  *         @arg @ref LL_RCC_PLLQ_DIV_13
+  *         @arg @ref LL_RCC_PLLQ_DIV_14
+  *         @arg @ref LL_RCC_PLLQ_DIV_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
+}
+
+#if defined(DSI)
+/**
+  * @brief  Configure PLL used for DSI clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLR can be written only when PLL is disabled
+  * @note This  can be selected for DSI
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_DSI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_DSI\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_DSI\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_DSI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+}
+#endif /* DSI */
+
+/**
+  * @brief  Configure PLL clock source
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource
+  * @param PLLSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+}
+
+/**
+  * @brief  Get Main PLL multiplication factor for VCO
+  * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
+  * @retval Between 50 and 432
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
+}
+
+/**
+  * @brief  Get Main PLL division factor for PLLP 
+  * @rmtoll PLLCFGR      PLLP       LL_RCC_PLL_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
+}
+
+/**
+  * @brief  Get Main PLL division factor for PLLQ
+  * @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock)
+  * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_3
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_5
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_7
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  *         @arg @ref LL_RCC_PLLQ_DIV_9
+  *         @arg @ref LL_RCC_PLLQ_DIV_10
+  *         @arg @ref LL_RCC_PLLQ_DIV_11
+  *         @arg @ref LL_RCC_PLLQ_DIV_12
+  *         @arg @ref LL_RCC_PLLQ_DIV_13
+  *         @arg @ref LL_RCC_PLLQ_DIV_14
+  *         @arg @ref LL_RCC_PLLQ_DIV_15
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
+}
+
+#if defined(RCC_PLLCFGR_PLLR)
+/**
+  * @brief  Get Main PLL division factor for PLLR
+  * @note used for PLLCLK (system clock)
+  * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
+}
+#endif /* RCC_PLLCFGR_PLLR */
+
+/**
+  * @brief  Get Division factor for the main PLL and other PLL
+  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+}
+
+/**
+  * @brief  Configure Spread Spectrum used for PLL
+  * @note These bits must be written before enabling PLL
+  * @rmtoll SSCGR        MODPER        LL_RCC_PLL_ConfigSpreadSpectrum\n
+  *         SSCGR        INCSTEP       LL_RCC_PLL_ConfigSpreadSpectrum\n
+  *         SSCGR        SPREADSEL     LL_RCC_PLL_ConfigSpreadSpectrum
+  * @param  Mod Between Min_Data=0 and Max_Data=8191
+  * @param  Inc Between Min_Data=0 and Max_Data=32767
+  * @param  Sel This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
+{
+  MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
+}
+
+/**
+  * @brief  Get Spread Spectrum Modulation Period for PLL
+  * @rmtoll SSCGR         MODPER        LL_RCC_PLL_GetPeriodModulation
+  * @retval Between Min_Data=0 and Max_Data=8191
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
+{
+  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
+}
+
+/**
+  * @brief  Get Spread Spectrum Incrementation Step for PLL
+  * @note Must be written before enabling PLL
+  * @rmtoll SSCGR         INCSTEP        LL_RCC_PLL_GetStepIncrementation
+  * @retval Between Min_Data=0 and Max_Data=32767
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
+{
+  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
+}
+
+/**
+  * @brief  Get Spread Spectrum Selection for PLL
+  * @note Must be written before enabling PLL
+  * @rmtoll SSCGR         SPREADSEL        LL_RCC_PLL_GetSpreadSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
+{
+  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
+}
+
+/**
+  * @brief  Enable Spread Spectrum for PLL.
+  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
+{
+  SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+}
+
+/**
+  * @brief  Disable Spread Spectrum for PLL.
+  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
+{
+  CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
+  * @{
+  */
+
+/**
+  * @brief  Enable PLLI2S
+  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
+}
+
+/**
+  * @brief  Disable PLLI2S
+  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+}
+
+/**
+  * @brief  Check if PLLI2S Ready
+  * @rmtoll CR           PLLI2SRDY    LL_RCC_PLLI2S_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
+}
+
+/**
+  * @brief  Configure PLLI2S used for SAI1 and SAI2 domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLQ can be written only when PLLI2S is disabled
+  * @note This can be selected for SAI1 and SAI2
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         DCKCFGR1      PLLI2SDIVQ    LL_RCC_PLLI2S_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+  * @param  PLLDIVQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
+  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ);
+}
+
+#if defined(SPDIFRX)
+/**
+  * @brief Configure PLLI2S used for SPDIFRX domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLP can be written only when PLLI2S is disabled
+  * @note This  can be selected for SPDIFRX
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+  *         PLLI2SCFGR   PLLI2SP       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
+}
+#endif /* SPDIFRX */
+
+/**
+  * @brief  Configure PLLI2S used for I2S1 domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLR can be written only when PLLI2S is disabled
+  * @note This  can be selected for I2S
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_I2S
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
+}
+
+/**
+  * @brief  Get I2SPLL multiplication factor for VCO
+  * @rmtoll PLLI2SCFGR  PLLI2SN      LL_RCC_PLLI2S_GetN
+  * @retval Between 50 and 432
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+}
+
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SQ
+  * @rmtoll PLLI2SCFGR  PLLI2SQ      LL_RCC_PLLI2S_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
+}
+
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SR
+  * @note used for PLLI2SCLK (I2S clock)
+  * @rmtoll PLLI2SCFGR  PLLI2SR      LL_RCC_PLLI2S_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
+}
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SP
+  * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
+  * @rmtoll PLLI2SCFGR  PLLI2SP      LL_RCC_PLLI2S_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
+}
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SDIVQ
+  * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
+  * @rmtoll DCKCFGR1   PLLI2SDIVQ      LL_RCC_PLLI2S_GetDIVQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_PLLSAI PLLSAI
+  * @{
+  */
+
+/**
+  * @brief  Enable PLLSAI
+  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLSAION);
+}
+
+/**
+  * @brief  Disable PLLSAI
+  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+}
+
+/**
+  * @brief  Check if PLLSAI Ready
+  * @rmtoll CR           PLLSAIRDY    LL_RCC_PLLSAI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
+}
+
+/**
+  * @brief  Configure PLLSAI used for SAI1 and SAI2 domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLQ can be written only when PLLSAI is disabled
+  * @note This can be selected for SAI1 and SAI2
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         PLLSAICFGR   PLLSAIQ       LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         DCKCFGR1     PLLSAIDIVQ    LL_RCC_PLLSAI_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+  * @param  PLLDIVQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
+  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, PLLDIVQ);
+}
+
+/**
+  * @brief Configure PLLSAI used for 48Mhz domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLP can be written only when PLLSAI is disabled
+  * @note This  can be selected for USB, RNG, SDMMC1
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_48M\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_48M\n
+  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_48M\n
+  *         PLLSAICFGR   PLLSAIP       LL_RCC_PLLSAI_ConfigDomain_48M
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
+}
+
+#if defined(LTDC)
+/**
+  * @brief  Configure PLLSAI used for LTDC domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLR can be written only when PLLSAI is disabled
+  * @note This  can be selected for LTDC
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         PLLSAICFGR   PLLSAIR       LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         DCKCFGR1     PLLSAIDIVR    LL_RCC_PLLSAI_ConfigDomain_LTDC
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+  * @param  PLLDIVR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
+  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, PLLDIVR);
+}
+#endif /* LTDC */
+
+/**
+  * @brief  Get SAIPLL multiplication factor for VCO
+  * @rmtoll PLLSAICFGR  PLLSAIN      LL_RCC_PLLSAI_GetN
+  * @retval Between 50 and 432
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+}
+
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIQ
+  * @rmtoll PLLSAICFGR  PLLSAIQ      LL_RCC_PLLSAI_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
+}
+
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIR
+  * @note used for PLLSAICLK (SAI clock)
+  * @rmtoll PLLSAICFGR  PLLSAIR      LL_RCC_PLLSAI_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
+}
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIP
+  * @note used for PLL48MCLK (48M domain clock)
+  * @rmtoll PLLSAICFGR  PLLSAIP      LL_RCC_PLLSAI_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
+}
+
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIDIVQ
+  * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
+  * @rmtoll DCKCFGR1   PLLSAIDIVQ      LL_RCC_PLLSAI_GetDIVQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ));
+}
+
+#if defined(RCC_DCKCFGR1_PLLSAIDIVR)
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIDIVR
+  * @note used for LTDC domain clock
+  * @rmtoll DCKCFGR1  PLLSAIDIVR      LL_RCC_PLLSAI_GetDIVR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR));
+}
+#endif /* RCC_DCKCFGR1_PLLSAIDIVR */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear LSI ready interrupt flag
+  * @rmtoll CIR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
+}
+
+/**
+  * @brief  Clear LSE ready interrupt flag
+  * @rmtoll CIR         LSERDYC       LL_RCC_ClearFlag_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
+}
+
+/**
+  * @brief  Clear HSI ready interrupt flag
+  * @rmtoll CIR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
+}
+
+/**
+  * @brief  Clear HSE ready interrupt flag
+  * @rmtoll CIR         HSERDYC       LL_RCC_ClearFlag_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
+}
+
+/**
+  * @brief  Clear PLL ready interrupt flag
+  * @rmtoll CIR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
+}
+
+/**
+  * @brief  Clear PLLI2S ready interrupt flag
+  * @rmtoll CIR         PLLI2SRDYC   LL_RCC_ClearFlag_PLLI2SRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
+}
+
+/**
+  * @brief  Clear PLLSAI ready interrupt flag
+  * @rmtoll CIR         PLLSAIRDYC   LL_RCC_ClearFlag_PLLSAIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
+}
+
+/**
+  * @brief  Clear Clock security system interrupt flag
+  * @rmtoll CIR         CSSC          LL_RCC_ClearFlag_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_CSSC);
+}
+
+/**
+  * @brief  Check if LSI ready interrupt occurred or not
+  * @rmtoll CIR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
+}
+
+/**
+  * @brief  Check if LSE ready interrupt occurred or not
+  * @rmtoll CIR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
+}
+
+/**
+  * @brief  Check if HSI ready interrupt occurred or not
+  * @rmtoll CIR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
+}
+
+/**
+  * @brief  Check if HSE ready interrupt occurred or not
+  * @rmtoll CIR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
+}
+
+/**
+  * @brief  Check if PLL ready interrupt occurred or not
+  * @rmtoll CIR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
+}
+
+/**
+  * @brief  Check if PLLI2S ready interrupt occurred or not
+  * @rmtoll CIR         PLLI2SRDYF   LL_RCC_IsActiveFlag_PLLI2SRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
+}
+
+/**
+  * @brief  Check if PLLSAI ready interrupt occurred or not
+  * @rmtoll CIR         PLLSAIRDYF   LL_RCC_IsActiveFlag_PLLSAIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
+}
+
+/**
+  * @brief  Check if Clock security system interrupt occurred or not
+  * @rmtoll CIR         CSSF          LL_RCC_IsActiveFlag_HSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
+}
+
+/**
+  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
+  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Low Power reset is set or not.
+  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Pin reset is set or not.
+  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag POR/PDR reset is set or not.
+  * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Window Watchdog reset is set or not.
+  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag BOR reset is set or not.
+  * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
+}
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI ready interrupt
+  * @rmtoll CIR         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+  * @brief  Enable LSE ready interrupt
+  * @rmtoll CIR         LSERDYIE      LL_RCC_EnableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+  * @brief  Enable HSI ready interrupt
+  * @rmtoll CIR         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSE ready interrupt
+  * @rmtoll CIR         HSERDYIE      LL_RCC_EnableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+  * @brief  Enable PLL ready interrupt
+  * @rmtoll CIR         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+/**
+  * @brief  Enable PLLI2S ready interrupt
+  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_EnableIT_PLLI2SRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+}
+
+/**
+  * @brief  Enable PLLSAI ready interrupt
+  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_EnableIT_PLLSAIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+}
+
+/**
+  * @brief  Disable LSI ready interrupt
+  * @rmtoll CIR         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+  * @brief  Disable LSE ready interrupt
+  * @rmtoll CIR         LSERDYIE      LL_RCC_DisableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+  * @brief  Disable HSI ready interrupt
+  * @rmtoll CIR         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSE ready interrupt
+  * @rmtoll CIR         HSERDYIE      LL_RCC_DisableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+  * @brief  Disable PLL ready interrupt
+  * @rmtoll CIR         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+/**
+  * @brief  Disable PLLI2S ready interrupt
+  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_DisableIT_PLLI2SRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+}
+
+/**
+  * @brief  Disable PLLSAI ready interrupt
+  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_DisableIT_PLLSAIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+}
+
+/**
+  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
+}
+
+/**
+  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
+}
+
+/**
+  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
+}
+
+/**
+  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
+}
+
+/**
+  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
+}
+
+/**
+  * @brief  Checks if PLLI2S ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_IsEnabledIT_PLLI2SRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
+}
+
+/**
+  * @brief  Checks if PLLSAI ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_IsEnabledIT_PLLSAIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+  * @{
+  */
+void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+uint32_t    LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
+uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
+uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#if defined(DFSDM1_Channel0)
+uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
+uint32_t    LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
+#endif /* DFSDM1_Channel0 */
+uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
+#if defined(CEC)
+uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
+#endif /* CEC */
+#if defined(LTDC)
+uint32_t    LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
+#endif /* LTDC */
+#if defined(SPDIFRX)
+uint32_t    LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
+#endif /* SPDIFRX */
+#if defined(DSI)
+uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
+#endif /* DSI */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_LL_RCC_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h
new file mode 100644
index 0000000..4122a81
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h
@@ -0,0 +1,1036 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_sdmmc.h
+  * @author  MCD Application Team
+  * @brief   Header file of SDMMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_LL_SDMMC_H
+#define STM32F7xx_LL_SDMMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(SDMMC1)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_Driver
+  * @{
+  */
+
+/** @addtogroup SDMMC_LL
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
+  * @{
+  */
+  
+/** 
+  * @brief  SDMMC Configuration Structure definition  
+  */
+typedef struct
+{
+  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
+
+  uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is
+                                      enabled or disabled.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
+
+  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
+                                      disabled when the bus is idle.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
+
+  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
+                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
+
+  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
+                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
+
+  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
+  
+}SDMMC_InitTypeDef;
+  
+
+/** 
+  * @brief  SDMMC Command Control structure 
+  */
+typedef struct                                                                                            
+{
+  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
+                                     to a card as part of a command message. If a command
+                                     contains an argument, it must be loaded into this register
+                                     before writing the command to the command register.              */
+
+  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 
+                                     Max_Data = 64                                                    */
+
+  uint32_t Response;            /*!< Specifies the SDMMC response type.
+                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
+
+  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is 
+                                     enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
+
+  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
+}SDMMC_CmdInitTypeDef;
+
+
+/** 
+  * @brief  SDMMC Data Control structure 
+  */
+typedef struct
+{
+  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
+
+  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
+ 
+  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
+ 
+  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
+ 
+  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
+ 
+  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
+}SDMMC_DataInitTypeDef;
+
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
+  * @{
+  */
+#define SDMMC_ERROR_NONE                                0x00000000U    /*!< No error                                                      */
+#define SDMMC_ERROR_CMD_CRC_FAIL                        0x00000001U    /*!< Command response received (but CRC check failed)              */
+#define SDMMC_ERROR_DATA_CRC_FAIL                       0x00000002U    /*!< Data block sent/received (CRC check failed)                   */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT                     0x00000004U    /*!< Command response timeout                                      */
+#define SDMMC_ERROR_DATA_TIMEOUT                        0x00000008U    /*!< Data timeout                                                  */
+#define SDMMC_ERROR_TX_UNDERRUN                         0x00000010U    /*!< Transmit FIFO underrun                                        */
+#define SDMMC_ERROR_RX_OVERRUN                          0x00000020U    /*!< Receive FIFO overrun                                          */
+#define SDMMC_ERROR_ADDR_MISALIGNED                     0x00000040U    /*!< Misaligned address                                            */
+#define SDMMC_ERROR_BLOCK_LEN_ERR                       0x00000080U    /*!< Transferred block length is not allowed for the card or the
+                                                                            number of transferred bytes does not match the block length   */
+#define SDMMC_ERROR_ERASE_SEQ_ERR                       0x00000100U    /*!< An error in the sequence of erase command occurs              */
+#define SDMMC_ERROR_BAD_ERASE_PARAM                     0x00000200U    /*!< An invalid selection for erase groups                         */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION                0x00000400U    /*!< Attempt to program a write protect block                      */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED                  0x00000800U    /*!< Sequence or password error has been detected in unlock
+                                                                            command or if there was an attempt to access a locked card    */
+#define SDMMC_ERROR_COM_CRC_FAILED                      0x00001000U    /*!< CRC check of the previous command failed                      */
+#define SDMMC_ERROR_ILLEGAL_CMD                         0x00002000U    /*!< Command is not legal for the card state                       */
+#define SDMMC_ERROR_CARD_ECC_FAILED                     0x00004000U    /*!< Card internal ECC was applied but failed to correct the data  */
+#define SDMMC_ERROR_CC_ERR                              0x00008000U    /*!< Internal card controller error                                */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR                 0x00010000U    /*!< General or unknown error                                      */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN                0x00020000U    /*!< The card could not sustain data reading in stream rmode       */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN                0x00040000U    /*!< The card could not sustain data programming in stream mode    */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE                   0x00080000U    /*!< CID/CSD overwrite error                                       */
+#define SDMMC_ERROR_WP_ERASE_SKIP                       0x00100000U    /*!< Only partial address space was erased                         */
+#define SDMMC_ERROR_CARD_ECC_DISABLED                   0x00200000U    /*!< Command has been executed without using internal ECC          */
+#define SDMMC_ERROR_ERASE_RESET                         0x00400000U    /*!< Erase sequence was cleared before executing because an out
+                                                                            of erase sequence command was received                        */
+#define SDMMC_ERROR_AKE_SEQ_ERR                         0x00800000U    /*!< Error in sequence of authentication                           */
+#define SDMMC_ERROR_INVALID_VOLTRANGE                   0x01000000U    /*!< Error in case of invalid voltage range                        */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE                   0x02000000U    /*!< Error when addressed block is out of range                    */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE              0x04000000U    /*!< Error when command request is not applicable                  */
+#define SDMMC_ERROR_INVALID_PARAMETER                   0x08000000U    /*!< the used parameter is not valid                               */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE                 0x10000000U    /*!< Error when feature is not insupported                         */
+#define SDMMC_ERROR_BUSY                                0x20000000U    /*!< Error when transfer process is busy                           */
+#define SDMMC_ERROR_DMA                                 0x40000000U    /*!< Error while DMA transfer                                      */
+#define SDMMC_ERROR_TIMEOUT                             0x80000000U    /*!< Timeout error                                                 */
+
+/** 
+  * @brief SDMMC Commands Index 
+  */
+#define SDMMC_CMD_GO_IDLE_STATE                                 0U    /*!< Resets the SD memory card.                                                               */
+#define SDMMC_CMD_SEND_OP_COND                                  1U    /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID                                  2U    /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
+#define SDMMC_CMD_SET_REL_ADDR                                  3U    /*!< Asks the card to publish a new relative address (RCA).                                   */
+#define SDMMC_CMD_SET_DSR                                       4U    /*!< Programs the DSR of all cards.                                                           */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND                             5U    /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+                                                                           operating condition register (OCR) content in the response on the CMD line.              */
+#define SDMMC_CMD_HS_SWITCH                                     6U    /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
+#define SDMMC_CMD_SEL_DESEL_CARD                                7U    /*!< Selects the card by its own relative address and gets deselected by any other address    */
+#define SDMMC_CMD_HS_SEND_EXT_CSD                               8U    /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+                                                                           and asks the card whether card supports voltage.                                         */
+#define SDMMC_CMD_SEND_CSD                                      9U    /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
+#define SDMMC_CMD_SEND_CID                                      10U   /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
+#define SDMMC_CMD_READ_DAT_UNTIL_STOP                           11U   /*!< SD card doesn't support it.                                                              */
+#define SDMMC_CMD_STOP_TRANSMISSION                             12U   /*!< Forces the card to stop transmission.                                                    */
+#define SDMMC_CMD_SEND_STATUS                                   13U   /*!< Addressed card sends its status register.                                                */
+#define SDMMC_CMD_HS_BUSTEST_READ                               14U   /*!< Reserved                                                                                 */
+#define SDMMC_CMD_GO_INACTIVE_STATE                             15U   /*!< Sends an addressed card into the inactive state.                                         */
+#define SDMMC_CMD_SET_BLOCKLEN                                  16U   /*!< Sets the block length (in bytes for SDSC) for all following block commands
+                                                                           (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
+                                                                           for SDHS and SDXC.                                                                       */
+#define SDMMC_CMD_READ_SINGLE_BLOCK                             17U   /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SDMMC_CMD_READ_MULT_BLOCK                               18U   /*!< Continuously transfers data blocks from card to host until interrupted by
+                                                                           STOP_TRANSMISSION command.                                                               */
+#define SDMMC_CMD_HS_BUSTEST_WRITE                              19U   /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                          20U   /*!< Speed class control command.                                                             */
+#define SDMMC_CMD_SET_BLOCK_COUNT                               23U   /*!< Specify block count for CMD18 and CMD25.                                                 */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK                            24U   /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SDMMC_CMD_WRITE_MULT_BLOCK                              25U   /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
+#define SDMMC_CMD_PROG_CID                                      26U   /*!< Reserved for manufacturers.                                                              */
+#define SDMMC_CMD_PROG_CSD                                      27U   /*!< Programming of the programmable bits of the CSD.                                         */
+#define SDMMC_CMD_SET_WRITE_PROT                                28U   /*!< Sets the write protection bit of the addressed group.                                    */
+#define SDMMC_CMD_CLR_WRITE_PROT                                29U   /*!< Clears the write protection bit of the addressed group.                                  */
+#define SDMMC_CMD_SEND_WRITE_PROT                               30U   /*!< Asks the card to send the status of the write protection bits.                           */
+#define SDMMC_CMD_SD_ERASE_GRP_START                            32U   /*!< Sets the address of the first write block to be erased. (For SD card only).              */
+#define SDMMC_CMD_SD_ERASE_GRP_END                              33U   /*!< Sets the address of the last write block of the continuous range to be erased.           */
+#define SDMMC_CMD_ERASE_GRP_START                               35U   /*!< Sets the address of the first write block to be erased. Reserved for each command
+                                                                           system set by switch function command (CMD6).                                            */
+#define SDMMC_CMD_ERASE_GRP_END                                 36U   /*!< Sets the address of the last write block of the continuous range to be erased.
+                                                                           Reserved for each command system set by switch function command (CMD6).                  */
+#define SDMMC_CMD_ERASE                                         38U   /*!< Reserved for SD security applications.                                                   */
+#define SDMMC_CMD_FAST_IO                                       39U   /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_GO_IRQ_STATE                                  40U   /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_LOCK_UNLOCK                                   42U   /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+                                                                           the SET_BLOCK_LEN command.                                                               */
+#define SDMMC_CMD_APP_CMD                                       55U   /*!< Indicates to the card that the next command is an application specific command rather
+                                                                           than a standard command.                                                                 */
+#define SDMMC_CMD_GEN_CMD                                       56U   /*!< Used either to transfer a data block to the card or to get a data block from the card
+                                                                           for general purpose/application specific commands.                                       */
+#define SDMMC_CMD_NO_CMD                                        64U   /*!< No command                                                                               */
+
+/** 
+  * @brief Following commands are SD Card Specific commands.
+  *        SDMMC_APP_CMD should be sent before sending these commands. 
+  */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                           6U    /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+                                                                            widths are given in SCR register.                                                       */
+#define SDMMC_CMD_SD_APP_STATUS                                 13U   /*!< (ACMD13) Sends the SD status.                                                            */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS                  22U   /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+                                                                           32bit+CRC data block.                                                                    */
+#define SDMMC_CMD_SD_APP_OP_COND                                41U   /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+                                                                           send its operating condition register (OCR) content in the response on the CMD line.     */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT                    42U   /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
+#define SDMMC_CMD_SD_APP_SEND_SCR                               51U   /*!< Reads the SD Configuration Register (SCR).                                               */
+#define SDMMC_CMD_SDMMC_RW_DIRECT                               52U   /*!< For SD I/O card only, reserved for security specification.                               */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED                             53U   /*!< For SD I/O card only, reserved for security specification.                               */
+
+/** 
+  * @brief Following commands are SD Card Specific security commands.
+  *        SDMMC_CMD_APP_CMD should be sent before sending these commands. 
+  */
+#define SDMMC_CMD_SD_APP_GET_MKB                                43U
+#define SDMMC_CMD_SD_APP_GET_MID                                44U
+#define SDMMC_CMD_SD_APP_SET_CER_RN1                            45U
+#define SDMMC_CMD_SD_APP_GET_CER_RN2                            46U
+#define SDMMC_CMD_SD_APP_SET_CER_RES2                           47U
+#define SDMMC_CMD_SD_APP_GET_CER_RES1                           48U
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK             18U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK            25U
+#define SDMMC_CMD_SD_APP_SECURE_ERASE                           38U
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA                     49U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB                       48U
+
+/** 
+  * @brief  Masks for errors Card Status R1 (OCR Register) 
+  */
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE                   0x80000000U
+#define SDMMC_OCR_ADDR_MISALIGNED                     0x40000000U
+#define SDMMC_OCR_BLOCK_LEN_ERR                       0x20000000U
+#define SDMMC_OCR_ERASE_SEQ_ERR                       0x10000000U
+#define SDMMC_OCR_BAD_ERASE_PARAM                     0x08000000U
+#define SDMMC_OCR_WRITE_PROT_VIOLATION                0x04000000U
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED                  0x01000000U
+#define SDMMC_OCR_COM_CRC_FAILED                      0x00800000U
+#define SDMMC_OCR_ILLEGAL_CMD                         0x00400000U
+#define SDMMC_OCR_CARD_ECC_FAILED                     0x00200000U
+#define SDMMC_OCR_CC_ERROR                            0x00100000U
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR               0x00080000U
+#define SDMMC_OCR_STREAM_READ_UNDERRUN                0x00040000U
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN                0x00020000U
+#define SDMMC_OCR_CID_CSD_OVERWRITE                   0x00010000U
+#define SDMMC_OCR_WP_ERASE_SKIP                       0x00008000U
+#define SDMMC_OCR_CARD_ECC_DISABLED                   0x00004000U
+#define SDMMC_OCR_ERASE_RESET                         0x00002000U
+#define SDMMC_OCR_AKE_SEQ_ERROR                       0x00000008U
+#define SDMMC_OCR_ERRORBITS                           0xFDFFE008U
+
+/** 
+  * @brief  Masks for R6 Response 
+  */
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR                0x00002000U
+#define SDMMC_R6_ILLEGAL_CMD                          0x00004000U
+#define SDMMC_R6_COM_CRC_FAILED                       0x00008000U
+
+#define SDMMC_VOLTAGE_WINDOW_SD                       0x80100000U
+#define SDMMC_HIGH_CAPACITY                           0x40000000U
+#define SDMMC_STD_CAPACITY                            0x00000000U
+#define SDMMC_CHECK_PATTERN                           0x000001AAU
+#define SD_SWITCH_1_8V_CAPACITY                       0x01000000U
+
+#define SDMMC_MAX_VOLT_TRIAL                          0x0000FFFFU
+
+#define SDMMC_MAX_TRIAL                               0x0000FFFFU
+
+#define SDMMC_ALLZERO                                 0x00000000U
+
+#define SDMMC_WIDE_BUS_SUPPORT                        0x00040000U
+#define SDMMC_SINGLE_BUS_SUPPORT                      0x00010000U
+#define SDMMC_CARD_LOCKED                             0x02000000U
+
+#ifndef SDMMC_DATATIMEOUT
+#define SDMMC_DATATIMEOUT                             0xFFFFFFFFU
+#endif /* SDMMC_DATATIMEOUT */
+
+#define SDMMC_0TO7BITS                                0x000000FFU
+#define SDMMC_8TO15BITS                               0x0000FF00U
+#define SDMMC_16TO23BITS                              0x00FF0000U
+#define SDMMC_24TO31BITS                              0xFF000000U
+#define SDMMC_MAX_DATA_LENGTH                         0x01FFFFFFU
+
+#define SDMMC_HALFFIFO                                0x00000008U
+#define SDMMC_HALFFIFOBYTES                           0x00000020U
+
+/** 
+  * @brief  Command Class supported
+  */
+#define SDMMC_CCCC_ERASE                       0x00000020U
+
+#define SDMMC_CMDTIMEOUT                       5000U         /* Command send and response timeout */
+#define SDMMC_MAXERASETIMEOUT                  63000U        /* Max erase Timeout 63 s            */
+#define SDMMC_STOPTRANSFERTIMEOUT              100000000U    /* Timeout for STOP TRANSMISSION command */
+
+/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
+  * @{
+  */
+#define SDMMC_CLOCK_EDGE_RISING               0x00000000U
+#define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE
+
+#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
+                                          ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
+  * @{
+  */
+#define SDMMC_CLOCK_BYPASS_DISABLE             0x00000000U
+#define SDMMC_CLOCK_BYPASS_ENABLE              SDMMC_CLKCR_BYPASS   
+
+#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
+                                              ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
+  * @{
+  */
+#define SDMMC_CLOCK_POWER_SAVE_DISABLE         0x00000000U
+#define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV
+
+#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
+                                                ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Bus_Wide Bus Width
+  * @{
+  */
+#define SDMMC_BUS_WIDE_1B                      0x00000000U
+#define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0
+#define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1
+
+#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
+                                        ((WIDE) == SDMMC_BUS_WIDE_4B) || \
+                                        ((WIDE) == SDMMC_BUS_WIDE_8B))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
+  * @{
+  */
+#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    0x00000000U
+#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN
+
+#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
+                                                        ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup SDMMC_LL_Clock_Division Clock Division
+  * @{
+  */
+#define IS_SDMMC_CLKDIV(DIV)   ((DIV) <= 0xFFU)
+/**
+  * @}
+  */  
+    
+/** @defgroup SDMMC_LL_Command_Index Command Index
+  * @{
+  */
+#define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Response_Type Response Type
+  * @{
+  */
+#define SDMMC_RESPONSE_NO                    0x00000000U
+#define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0
+#define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP
+
+#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \
+                                            ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
+                                            ((RESPONSE) == SDMMC_RESPONSE_LONG))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
+  * @{
+  */
+#define SDMMC_WAIT_NO                        0x00000000U
+#define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT 
+#define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND
+
+#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
+                                    ((WAIT) == SDMMC_WAIT_IT) || \
+                                    ((WAIT) == SDMMC_WAIT_PEND))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_CPSM_State CPSM State
+  * @{
+  */
+#define SDMMC_CPSM_DISABLE                   0x00000000U
+#define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN
+
+#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
+                                    ((CPSM) == SDMMC_CPSM_ENABLE))
+/**
+  * @}
+  */  
+
+/** @defgroup SDMMC_LL_Response_Registers Response Register
+  * @{
+  */
+#define SDMMC_RESP1                          0x00000000U
+#define SDMMC_RESP2                          0x00000004U
+#define SDMMC_RESP3                          0x00000008U
+#define SDMMC_RESP4                          0x0000000CU
+
+#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
+                                    ((RESP) == SDMMC_RESP2) || \
+                                    ((RESP) == SDMMC_RESP3) || \
+                                    ((RESP) == SDMMC_RESP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Data_Length Data Length
+  * @{
+  */
+#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
+  * @{
+  */
+#define SDMMC_DATABLOCK_SIZE_1B               0x00000000U
+#define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0
+#define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1
+#define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
+#define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2
+#define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3
+#define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 
+#define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+
+#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
+                                          ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
+  * @{
+  */
+#define SDMMC_TRANSFER_DIR_TO_CARD            0x00000000U
+#define SDMMC_TRANSFER_DIR_TO_SDMMC    SDMMC_DCTRL_DTDIR
+
+#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
+                                           ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
+  * @{
+  */
+#define SDMMC_TRANSFER_MODE_BLOCK             0x00000000U
+#define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE
+
+#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
+                                             ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_DPSM_State DPSM State
+  * @{
+  */
+#define SDMMC_DPSM_DISABLE                    0x00000000U
+#define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN
+
+#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
+                                    ((DPSM) == SDMMC_DPSM_ENABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
+  * @{
+  */
+#define SDMMC_READ_WAIT_MODE_DATA2                0x00000000U
+#define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)
+
+#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
+                                             ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
+/**
+  * @}
+  */  
+
+/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
+  * @{
+  */
+#define SDMMC_IT_CCRCFAIL                    SDMMC_MASK_CCRCFAILIE
+#define SDMMC_IT_DCRCFAIL                    SDMMC_MASK_DCRCFAILIE
+#define SDMMC_IT_CTIMEOUT                    SDMMC_MASK_CTIMEOUTIE
+#define SDMMC_IT_DTIMEOUT                    SDMMC_MASK_DTIMEOUTIE
+#define SDMMC_IT_TXUNDERR                    SDMMC_MASK_TXUNDERRIE
+#define SDMMC_IT_RXOVERR                     SDMMC_MASK_RXOVERRIE
+#define SDMMC_IT_CMDREND                     SDMMC_MASK_CMDRENDIE
+#define SDMMC_IT_CMDSENT                     SDMMC_MASK_CMDSENTIE
+#define SDMMC_IT_DATAEND                     SDMMC_MASK_DATAENDIE
+#define SDMMC_IT_DBCKEND                     SDMMC_MASK_DBCKENDIE
+#define SDMMC_IT_CMDACT                      SDMMC_MASK_CMDACTIE
+#define SDMMC_IT_TXACT                       SDMMC_MASK_TXACTIE
+#define SDMMC_IT_RXACT                       SDMMC_MASK_RXACTIE
+#define SDMMC_IT_TXFIFOHE                    SDMMC_MASK_TXFIFOHEIE
+#define SDMMC_IT_RXFIFOHF                    SDMMC_MASK_RXFIFOHFIE
+#define SDMMC_IT_TXFIFOF                     SDMMC_MASK_TXFIFOFIE
+#define SDMMC_IT_RXFIFOF                     SDMMC_MASK_RXFIFOFIE
+#define SDMMC_IT_TXFIFOE                     SDMMC_MASK_TXFIFOEIE
+#define SDMMC_IT_RXFIFOE                     SDMMC_MASK_RXFIFOEIE
+#define SDMMC_IT_TXDAVL                      SDMMC_MASK_TXDAVLIE
+#define SDMMC_IT_RXDAVL                      SDMMC_MASK_RXDAVLIE
+#define SDMMC_IT_SDIOIT                      SDMMC_MASK_SDIOITIE
+/**
+  * @}
+  */ 
+
+/** @defgroup SDMMC_LL_Flags Flags
+  * @{
+  */
+#define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL
+#define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL
+#define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT
+#define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT
+#define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR
+#define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR
+#define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND
+#define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT
+#define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND
+#define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND
+#define SDMMC_FLAG_CMDACT                    SDMMC_STA_CMDACT
+#define SDMMC_FLAG_TXACT                     SDMMC_STA_TXACT
+#define SDMMC_FLAG_RXACT                     SDMMC_STA_RXACT
+#define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE
+#define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF
+#define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF
+#define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF
+#define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE
+#define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE
+#define SDMMC_FLAG_TXDAVL                    SDMMC_STA_TXDAVL
+#define SDMMC_FLAG_RXDAVL                    SDMMC_STA_RXDAVL
+#define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT
+#define SDMMC_STATIC_FLAGS                   ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
+                                                         SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\
+                                                         SDMMC_FLAG_CMDREND  | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\
+                                                         SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT))  
+
+#define SDMMC_STATIC_CMD_FLAGS               ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
+                                                         SDMMC_FLAG_CMDSENT))
+
+#define SDMMC_STATIC_DATA_FLAGS              ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
+                                                         SDMMC_FLAG_RXOVERR  | SDMMC_FLAG_DATAEND  | SDMMC_FLAG_DBCKEND))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
+  * @{
+  */
+
+/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
+  * @brief SDMMC_LL registers bit address in the alias region
+  * @{
+  */
+/* ---------------------- SDMMC registers bit mask --------------------------- */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */ 
+#define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\
+                                             SDMMC_CLKCR_BYPASS  | SDMMC_CLKCR_WIDBUS |\
+                                             SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
+
+/* --- DCTRL Register ---*/
+/* SDMMC DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\
+                                             SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
+                                             SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\
+                                             SDMMC_CMD_CPSMEN   | SDMMC_CMD_SDIOSUSPEND))
+
+/* SDMMC Initialization Frequency (400KHz max) */
+#define SDMMC_INIT_CLK_DIV     ((uint8_t)0x76)    /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
+
+/* SDMMC Data Transfer Frequency (25MHz max) */
+#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)     /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+ 
+/**
+  * @brief  Enable the SDMMC device.
+  * @param  __INSTANCE__: SDMMC Instance  
+  * @retval None
+  */
+#define __SDMMC_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
+
+/**
+  * @brief  Disable the SDMMC device.
+  * @param  __INSTANCE__: SDMMC Instance  
+  * @retval None
+  */
+#define __SDMMC_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
+
+/**
+  * @brief  Enable the SDMMC DMA transfer.
+  * @param  __INSTANCE__: SDMMC Instance  
+  * @retval None
+  */
+#define __SDMMC_DMA_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
+
+/**
+  * @brief  Disable the SDMMC DMA transfer.
+  * @param  __INSTANCE__: SDMMC Instance   
+  * @retval None
+  */
+#define __SDMMC_DMA_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
+ 
+/**
+  * @brief  Enable the SDMMC device interrupt.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base  
+  * @param  __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SDIO interrupt received interrupt 
+  * @retval None
+  */
+#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDMMC device interrupt.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base   
+  * @param  __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SDIO interrupt received interrupt   
+  * @retval None
+  */
+#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified SDMMC flag is set or not. 
+  * @param  __INSTANCE__ : Pointer to SDMMC register base   
+  * @param  __FLAG__: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
+  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
+  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
+  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
+  *            @arg SDMMC_FLAG_SDIOIT:   SDIO interrupt received
+  * @retval The new state of SDMMC_FLAG (SET or RESET).
+  */
+#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
+
+
+/**
+  * @brief  Clears the SDMMC pending flags.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base  
+  * @param  __FLAG__: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_SDIOIT:   SDIO interrupt received
+  * @retval None
+  */
+#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
+
+/**
+  * @brief  Checks whether the specified SDMMC interrupt has occurred or not.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SDIO interrupt received interrupt
+  * @retval The new state of SDMMC_IT (SET or RESET).
+  */
+#define __SDMMC_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Clears the SDMMC's interrupt pending bits.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base 
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SDIO interrupt received interrupt
+  * @retval None
+  */
+#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base  
+  * @retval None
+  */
+#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
+
+/**
+  * @brief  Disable Start the SD I/O Read Wait operations.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base   
+  * @retval None
+  */
+#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base   
+  * @retval None
+  */
+#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
+
+/**
+  * @brief  Disable Stop the SD I/O Read Wait operations.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base  
+  * @retval None
+  */
+#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
+
+/**
+  * @brief  Enable the SD I/O Mode Operation.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base   
+  * @retval None
+  */
+#define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
+
+/**
+  * @brief  Disable the SD I/O Mode Operation.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base 
+  * @retval None
+  */
+#define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 
+
+/**
+  * @brief  Enable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base  
+  * @retval None
+  */
+#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 
+
+/**
+  * @brief  Disable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__ : Pointer to SDMMC register base  
+  * @retval None
+  */
+#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDMMC_LL_Exported_Functions
+  * @{
+  */
+  
+/* Initialization/de-initialization functions  **********************************/
+/** @addtogroup HAL_SDMMC_LL_Group1
+  * @{
+  */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
+/**
+  * @}
+  */
+  
+/* I/O operation functions  *****************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group2
+  * @{
+  */
+uint32_t          SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
+/**
+  * @}
+  */
+  
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group3
+  * @{
+  */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
+
+/* Command path state machine (CPSM) management functions */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
+uint8_t           SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
+
+/* Data path state machine (DPSM) management functions */
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
+uint32_t          SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
+
+/* SDMMC Cards mode management functions */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
+/**
+  * @}
+  */
+
+/* SDMMC Commands management functions */
+/** @addtogroup HAL_SDMMC_LL_Group4
+  * @{
+  */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA);
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+/**
+  * @}
+  */
+
+/* SDMMC Responses management functions *****************************************/
+/** @addtogroup HAL_SDMMC_LL_Group5
+  * @{
+  */
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* SDMMC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F7xx_LL_SDMMC_H */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h
new file mode 100644
index 0000000..7eb04a5
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h
@@ -0,0 +1,2282 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_spi.h
+  * @author  MCD Application Team
+  * @brief   Header file of SPI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_LL_SPI_H
+#define STM32F7xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
+
+/** @defgroup SPI_LL SPI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  SPI Init structures definition
+  */
+typedef struct
+{
+  uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+
+  uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
+                                         This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+
+  uint32_t DataWidth;               /*!< Specifies the SPI data width.
+                                         This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+
+  uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+
+  uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+
+  uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+
+  uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+                                         @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+
+  uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+
+  uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
+                                         This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+                                         This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+  uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+  * @{
+  */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_SPI_ReadReg function
+  * @{
+  */
+#define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
+#define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
+#define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
+#define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
+#define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
+#define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
+#define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
+  * @{
+  */
+#define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
+#define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
+#define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_MODE Operation Mode
+  * @{
+  */
+#define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
+#define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
+  * @{
+  */
+#define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
+#define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+  * @{
+  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+  * @{
+  */
+#define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
+#define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+  * @{
+  */
+#define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
+#define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
+#define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+  * @{
+  */
+#define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
+#define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
+#define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  4 bits */
+#define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                              /*!< Data length for SPI transfer:  5 bits */
+#define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer:  6 bits */
+#define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  7 bits */
+#define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer:  8 bits */
+#define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                              /*!< Data length for SPI transfer:  9 bits */
+#define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer: 10 bits */
+#define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer: 11 bits */
+#define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 12 bits */
+#define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                               /*!< Data length for SPI transfer: 13 bits */
+#define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 14 bits */
+#define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)                /*!< Data length for SPI transfer: 15 bits */
+#define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+  * @{
+  */
+#define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
+  * @{
+  */
+#define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
+#define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
+  * @{
+  */
+#define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
+#define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit)  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
+  * @{
+  */
+#define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception empty */
+#define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/4   */
+#define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/2   */
+#define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
+  * @{
+  */
+#define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission empty */
+#define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission 1/4   */
+#define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission 1/2   */
+#define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
+  * @{
+  */
+#define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
+#define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+  * @{
+  */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in SPI register
+  * @param  __INSTANCE__ SPI Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in SPI register
+  * @param  __INSTANCE__ SPI Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+  * @{
+  */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable SPI peripheral
+  * @rmtoll CR1          SPE           LL_SPI_Enable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Disable SPI peripheral
+  * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
+  * @rmtoll CR1          SPE           LL_SPI_Disable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Check if SPI peripheral is enabled
+  * @rmtoll CR1          SPE           LL_SPI_IsEnabled
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set SPI operation mode to Master or Slave
+  * @note   This bit should not be changed when communication is ongoing.
+  * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
+  *         CR1          SSI           LL_SPI_SetMode
+  * @param  SPIx SPI Instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_MODE_MASTER
+  *         @arg @ref LL_SPI_MODE_SLAVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+}
+
+/**
+  * @brief  Get SPI operation mode (Master or Slave)
+  * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
+  *         CR1          SSI           LL_SPI_GetMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_MODE_MASTER
+  *         @arg @ref LL_SPI_MODE_SLAVE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+}
+
+/**
+  * @brief  Set serial protocol used
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR2          FRF           LL_SPI_SetStandard
+  * @param  SPIx SPI Instance
+  * @param  Standard This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+  *         @arg @ref LL_SPI_PROTOCOL_TI
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
+}
+
+/**
+  * @brief  Get serial protocol used
+  * @rmtoll CR2          FRF           LL_SPI_GetStandard
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+  *         @arg @ref LL_SPI_PROTOCOL_TI
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
+}
+
+/**
+  * @brief  Set clock phase
+  * @note   This bit should not be changed when communication is ongoing.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
+  * @param  SPIx SPI Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_PHASE_1EDGE
+  *         @arg @ref LL_SPI_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Get clock phase
+  * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_PHASE_1EDGE
+  *         @arg @ref LL_SPI_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+}
+
+/**
+  * @brief  Set clock polarity
+  * @note   This bit should not be changed when communication is ongoing.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
+  * @param  SPIx SPI Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_POLARITY_LOW
+  *         @arg @ref LL_SPI_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Get clock polarity
+  * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_POLARITY_LOW
+  *         @arg @ref LL_SPI_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+}
+
+/**
+  * @brief  Set baud rate prescaler
+  * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
+  * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
+  * @param  SPIx SPI Instance
+  * @param  BaudRate This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+}
+
+/**
+  * @brief  Get baud rate prescaler
+  * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+}
+
+/**
+  * @brief  Set transfer bit order
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_LSB_FIRST
+  *         @arg @ref LL_SPI_MSB_FIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Get transfer bit order
+  * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_LSB_FIRST
+  *         @arg @ref LL_SPI_MSB_FIRST
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+}
+
+/**
+  * @brief  Set transfer direction mode
+  * @note   For Half-Duplex mode, Rx Direction is set by default.
+  *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
+  * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
+  *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
+  *         CR1          BIDIOE        LL_SPI_SetTransferDirection
+  * @param  SPIx SPI Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_FULL_DUPLEX
+  *         @arg @ref LL_SPI_SIMPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+}
+
+/**
+  * @brief  Get transfer direction mode
+  * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
+  *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
+  *         CR1          BIDIOE        LL_SPI_GetTransferDirection
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_FULL_DUPLEX
+  *         @arg @ref LL_SPI_SIMPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+}
+
+/**
+  * @brief  Set frame data width
+  * @rmtoll CR2          DS            LL_SPI_SetDataWidth
+  * @param  SPIx SPI Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
+}
+
+/**
+  * @brief  Get frame data width
+  * @rmtoll CR2          DS            LL_SPI_GetDataWidth
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
+}
+
+/**
+  * @brief  Set threshold of RXFIFO that triggers an RXNE event
+  * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
+  * @param  SPIx SPI Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
+  *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
+}
+
+/**
+  * @brief  Get threshold of RXFIFO that triggers an RXNE event
+  * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
+  *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_CRC_Management CRC Management
+  * @{
+  */
+
+/**
+  * @brief  Enable CRC
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+  * @brief  Disable CRC
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+  * @brief  Check if CRC is enabled
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set CRC Length
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
+  * @param  SPIx SPI Instance
+  * @param  CRCLength This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_CRC_8BIT
+  *         @arg @ref LL_SPI_CRC_16BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
+}
+
+/**
+  * @brief  Get CRC Length
+  * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_CRC_8BIT
+  *         @arg @ref LL_SPI_CRC_16BIT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
+}
+
+/**
+  * @brief  Set CRCNext to transfer CRC on the line
+  * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
+  * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+}
+
+/**
+  * @brief  Set polynomial for CRC calculation
+  * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
+  * @param  SPIx SPI Instance
+  * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+  WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+}
+
+/**
+  * @brief  Get polynomial for CRC calculation
+  * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->CRCPR));
+}
+
+/**
+  * @brief  Get Rx CRC
+  * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->RXCRCR));
+}
+
+/**
+  * @brief  Get Tx CRC
+  * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->TXCRCR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+  * @{
+  */
+
+/**
+  * @brief  Set NSS mode
+  * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+  * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
+  * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
+  * @param  SPIx SPI Instance
+  * @param  NSS This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_SOFT
+  *         @arg @ref LL_SPI_NSS_HARD_INPUT
+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
+  MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+}
+
+/**
+  * @brief  Get NSS mode
+  * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
+  * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_SOFT
+  *         @arg @ref LL_SPI_NSS_HARD_INPUT
+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+{
+  uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+  uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
+  return (Ssm | Ssoe);
+}
+
+/**
+  * @brief  Enable NSS pulse management
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+  * @brief  Disable NSS pulse management
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+  * @brief  Check if NSS pulse is enabled
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Check if Rx buffer is not empty
+  * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx buffer is empty
+  * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get CRC error flag
+  * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get mode fault error flag
+  * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get overrun error flag
+  * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get busy flag
+  * @note   The BSY flag is cleared under any one of the following conditions:
+  * -When the SPI is correctly disabled
+  * -When a fault is detected in Master mode (MODF bit set to 1)
+  * -In Master mode, when it finishes a data transmission and no new data is ready to be
+  * sent
+  * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+  * each data transfer.
+  * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get frame format error flag
+  * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get FIFO reception Level
+  * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_RX_FIFO_EMPTY
+  *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
+  *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
+  *         @arg @ref LL_SPI_RX_FIFO_FULL
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
+}
+
+/**
+  * @brief  Get FIFO Transmission Level
+  * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_TX_FIFO_EMPTY
+  *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
+  *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
+  *         @arg @ref LL_SPI_TX_FIFO_FULL
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
+}
+
+/**
+  * @brief  Clear CRC error flag
+  * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+}
+
+/**
+  * @brief  Clear mode fault error flag
+  * @note   Clearing this flag is done by a read access to the SPIx_SR
+  *         register followed by a write access to the SPIx_CR1 register
+  * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg_sr;
+  tmpreg_sr = SPIx->SR;
+  (void) tmpreg_sr;
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Clear overrun error flag
+  * @note   Clearing this flag is done by a read access to the SPIx_DR
+  *         register followed by a read access to the SPIx_SR register
+  * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->DR;
+  (void) tmpreg;
+  tmpreg = SPIx->SR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear frame format error flag
+  * @note   Clearing this flag is done by reading SPIx_SR register
+  * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->SR;
+  (void) tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+  * @{
+  */
+
+/**
+  * @brief  Enable error interrupt
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+  * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+  * @brief  Enable Rx buffer not empty interrupt
+  * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+  * @brief  Enable Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+  * @brief  Disable error interrupt
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+  * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+  * @brief  Disable Rx buffer not empty interrupt
+  * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+  * @brief  Disable Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+  * @brief  Check if error interrupt is enabled
+  * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx buffer not empty interrupt is enabled
+  * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA Rx is enabled
+  * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA Tx is enabled
+  * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set parity of  Last DMA reception
+  * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
+  * @param  SPIx SPI Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
+}
+
+/**
+  * @brief  Get parity configuration for  Last DMA reception
+  * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
+}
+
+/**
+  * @brief  Set parity of  Last DMA transmission
+  * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
+  * @param  SPIx SPI Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
+}
+
+/**
+  * @brief  Get parity configuration for Last DMA transmission
+  * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_DMA_PARITY_ODD
+  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
+  * @param  SPIx SPI Instance
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+{
+  return (uint32_t) &(SPIx->DR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA Management
+  * @{
+  */
+
+/**
+  * @brief  Read 8-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_ReceiveData8
+  * @param  SPIx SPI Instance
+  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+{
+  return (*((__IO uint8_t *)&SPIx->DR));
+}
+
+/**
+  * @brief  Read 16-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_ReceiveData16
+  * @param  SPIx SPI Instance
+  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+{
+  return (uint16_t)(READ_REG(SPIx->DR));
+}
+
+/**
+  * @brief  Write 8-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_TransmitData8
+  * @param  SPIx SPI Instance
+  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+#if defined (__GNUC__)
+  __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+  *spidr = TxData;
+#else
+  *((__IO uint8_t *)&SPIx->DR) = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+  * @brief  Write 16-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_TransmitData16
+  * @param  SPIx SPI Instance
+  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+#if defined (__GNUC__)
+  __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+  *spidr = TxData;
+#else
+  SPIx->DR = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL I2S
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  I2S Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t Mode;                    /*!< Specifies the I2S operating mode.
+                                         This parameter can be a value of @ref I2S_LL_EC_MODE
+
+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
+
+  uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
+                                         This parameter can be a value of @ref I2S_LL_EC_STANDARD
+
+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
+
+
+  uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
+                                         This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
+
+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
+
+
+  uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                         This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
+
+                                         This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
+
+
+  uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
+                                         This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
+
+                                         Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
+                                         and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
+
+
+  uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
+                                         This parameter can be a value of @ref I2S_LL_EC_POLARITY
+
+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
+
+} LL_I2S_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+  * @{
+  */
+
+/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_I2S_ReadReg function
+  * @{
+  */
+#define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
+#define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
+#define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
+#define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
+#define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
+#define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
+  * @{
+  */
+#define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
+#define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
+#define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
+  * @{
+  */
+#define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel length 16bit */
+#define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel length 32bit */
+#define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel length 32bit */
+#define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel length 32bit */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
+#define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_STANDARD I2s Standard
+  * @{
+  */
+#define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
+#define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
+#define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
+#define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
+#define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_MODE Operation Mode
+  * @{
+  */
+#define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
+#define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
+#define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
+#define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
+  * @{
+  */
+#define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
+#define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+  * @{
+  */
+#define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+  * @{
+  */
+
+#define LL_I2S_AUDIOFREQ_192K              192000U       /*!< Audio Frequency configuration 192000 Hz       */
+#define LL_I2S_AUDIOFREQ_96K               96000U        /*!< Audio Frequency configuration  96000 Hz       */
+#define LL_I2S_AUDIOFREQ_48K               48000U        /*!< Audio Frequency configuration  48000 Hz       */
+#define LL_I2S_AUDIOFREQ_44K               44100U        /*!< Audio Frequency configuration  44100 Hz       */
+#define LL_I2S_AUDIOFREQ_32K               32000U        /*!< Audio Frequency configuration  32000 Hz       */
+#define LL_I2S_AUDIOFREQ_22K               22050U        /*!< Audio Frequency configuration  22050 Hz       */
+#define LL_I2S_AUDIOFREQ_16K               16000U        /*!< Audio Frequency configuration  16000 Hz       */
+#define LL_I2S_AUDIOFREQ_11K               11025U        /*!< Audio Frequency configuration  11025 Hz       */
+#define LL_I2S_AUDIOFREQ_8K                8000U         /*!< Audio Frequency configuration   8000 Hz       */
+#define LL_I2S_AUDIOFREQ_DEFAULT           2U            /*!< Audio Freq not specified. Register I2SDIV = 2 */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+  * @{
+  */
+
+/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in I2S register
+  * @param  __INSTANCE__ I2S Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in I2S register
+  * @param  __INSTANCE__ I2S Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+  * @{
+  */
+
+/** @defgroup I2S_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Select I2S mode and Enable I2S peripheral
+  * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
+  *         I2SCFGR      I2SE          LL_I2S_Enable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+  * @brief  Disable I2S peripheral
+  * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+  * @brief  Check if I2S peripheral is enabled
+  * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set I2S data frame length
+  * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
+  *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
+  * @param  SPIx SPI Instance
+  * @param  DataFormat This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_DATAFORMAT_16B
+  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+  *         @arg @ref LL_I2S_DATAFORMAT_24B
+  *         @arg @ref LL_I2S_DATAFORMAT_32B
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
+}
+
+/**
+  * @brief  Get I2S data frame length
+  * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
+  *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_DATAFORMAT_16B
+  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+  *         @arg @ref LL_I2S_DATAFORMAT_24B
+  *         @arg @ref LL_I2S_DATAFORMAT_32B
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
+}
+
+/**
+  * @brief  Set I2S clock polarity
+  * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
+  * @param  SPIx SPI Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_POLARITY_LOW
+  *         @arg @ref LL_I2S_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+  SET_BIT(SPIx->I2SCFGR, ClockPolarity);
+}
+
+/**
+  * @brief  Get I2S clock polarity
+  * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_POLARITY_LOW
+  *         @arg @ref LL_I2S_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
+}
+
+/**
+  * @brief  Set I2S standard protocol
+  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
+  *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
+  * @param  SPIx SPI Instance
+  * @param  Standard This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_STANDARD_PHILIPS
+  *         @arg @ref LL_I2S_STANDARD_MSB
+  *         @arg @ref LL_I2S_STANDARD_LSB
+  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
+  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
+}
+
+/**
+  * @brief  Get I2S standard protocol
+  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
+  *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_STANDARD_PHILIPS
+  *         @arg @ref LL_I2S_STANDARD_MSB
+  *         @arg @ref LL_I2S_STANDARD_LSB
+  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
+  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
+}
+
+/**
+  * @brief  Set I2S transfer mode
+  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
+  * @param  SPIx SPI Instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_MODE_SLAVE_TX
+  *         @arg @ref LL_I2S_MODE_SLAVE_RX
+  *         @arg @ref LL_I2S_MODE_MASTER_TX
+  *         @arg @ref LL_I2S_MODE_MASTER_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
+}
+
+/**
+  * @brief  Get I2S transfer mode
+  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_MODE_SLAVE_TX
+  *         @arg @ref LL_I2S_MODE_SLAVE_RX
+  *         @arg @ref LL_I2S_MODE_MASTER_TX
+  *         @arg @ref LL_I2S_MODE_MASTER_RX
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
+}
+
+/**
+  * @brief  Set I2S linear prescaler
+  * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
+  * @param  SPIx SPI Instance
+  * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
+{
+  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
+}
+
+/**
+  * @brief  Get I2S linear prescaler
+  * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
+  * @param  SPIx SPI Instance
+  * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
+}
+
+/**
+  * @brief  Set I2S parity prescaler
+  * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
+  * @param  SPIx SPI Instance
+  * @param  PrescalerParity This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
+{
+  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
+}
+
+/**
+  * @brief  Get I2S parity prescaler
+  * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
+}
+
+/**
+  * @brief  Enable the master clock output (Pin MCK)
+  * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+  * @brief  Disable the master clock output (Pin MCK)
+  * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+  * @brief  Check if the master clock output (Pin MCK) is enabled
+  * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
+}
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+/**
+  * @brief  Enable asynchronous start
+  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_EnableAsyncStart
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+}
+
+/**
+  * @brief  Disable  asynchronous start
+  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_DisableAsyncStart
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+}
+
+/**
+  * @brief  Check if asynchronous start is enabled
+  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_IsEnabledAsyncStart
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
+}
+#endif /* SPI_I2SCFGR_ASTRTEN */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EF_FLAG FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Check if Rx buffer is not empty
+  * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_RXNE(SPIx);
+}
+
+/**
+  * @brief  Check if Tx buffer is empty
+  * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_TXE(SPIx);
+}
+
+/**
+  * @brief  Get busy flag
+  * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_BSY(SPIx);
+}
+
+/**
+  * @brief  Get overrun error flag
+  * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_OVR(SPIx);
+}
+
+/**
+  * @brief  Get underrun error flag
+  * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get frame format error flag
+  * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_FRE(SPIx);
+}
+
+/**
+  * @brief  Get channel side flag.
+  * @note   0: Channel Left has to be transmitted or has been received\n
+  *         1: Channel Right has to be transmitted or has been received\n
+  *         It has no significance in PCM mode.
+  * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear overrun error flag
+  * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_ClearFlag_OVR(SPIx);
+}
+
+/**
+  * @brief  Clear underrun error flag
+  * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->SR;
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Clear frame format error flag
+  * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_ClearFlag_FRE(SPIx);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EF_IT Interrupt Management
+  * @{
+  */
+
+/**
+  * @brief  Enable error IT
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+  * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIT_ERR(SPIx);
+}
+
+/**
+  * @brief  Enable Rx buffer not empty IT
+  * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIT_RXNE(SPIx);
+}
+
+/**
+  * @brief  Enable Tx buffer empty IT
+  * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIT_TXE(SPIx);
+}
+
+/**
+  * @brief  Disable error IT
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+  * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIT_ERR(SPIx);
+}
+
+/**
+  * @brief  Disable Rx buffer not empty IT
+  * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIT_RXNE(SPIx);
+}
+
+/**
+  * @brief  Disable Tx buffer empty IT
+  * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIT_TXE(SPIx);
+}
+
+/**
+  * @brief  Check if ERR IT is enabled
+  * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIT_ERR(SPIx);
+}
+
+/**
+  * @brief  Check if RXNE IT is enabled
+  * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIT_RXNE(SPIx);
+}
+
+/**
+  * @brief  Check if TXE IT is enabled
+  * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIT_TXE(SPIx);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EF_DMA DMA Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableDMAReq_RX(SPIx);
+}
+
+/**
+  * @brief  Disable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableDMAReq_RX(SPIx);
+}
+
+/**
+  * @brief  Check if DMA Rx is enabled
+  * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledDMAReq_RX(SPIx);
+}
+
+/**
+  * @brief  Enable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableDMAReq_TX(SPIx);
+}
+
+/**
+  * @brief  Disable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableDMAReq_TX(SPIx);
+}
+
+/**
+  * @brief  Check if DMA Tx is enabled
+  * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledDMAReq_TX(SPIx);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EF_DATA DATA Management
+  * @{
+  */
+
+/**
+  * @brief  Read 16-Bits in data register
+  * @rmtoll DR           DR            LL_I2S_ReceiveData16
+  * @param  SPIx SPI Instance
+  * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_ReceiveData16(SPIx);
+}
+
+/**
+  * @brief  Write 16-Bits in data register
+  * @rmtoll DR           DR            LL_I2S_TransmitData16
+  * @param  SPIx SPI Instance
+  * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+  LL_SPI_TransmitData16(SPIx, TxData);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
+void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F7xx_LL_SPI_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h
new file mode 100644
index 0000000..d6aed25
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h
@@ -0,0 +1,1018 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_system.h
+  * @author  MCD Application Team
+  * @brief   Header file of SYSTEM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL SYSTEM driver contains a set of generic APIs that can be
+    used by user:
+      (+) Some of the FLASH features need to be handled in the SYSTEM file.
+      (+) Access to DBGCMU registers
+      (+) Access to SYSCFG registers
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_LL_SYSTEM_H
+#define __STM32F7xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
+* @{
+*/
+#define LL_SYSCFG_REMAP_BOOT0               0x00000000U                                         /*!< Boot information after Reset  */
+#define LL_SYSCFG_REMAP_BOOT1               SYSCFG_MEMRMP_MEM_BOOT                              /*!< Boot information after Reset  */
+/**
+  * @}
+  */
+
+
+#if defined(SYSCFG_MEMRMP_SWP_FB)
+/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
+  * @{
+  */
+#define LL_SYSCFG_BANKMODE_BANK1          0x00000000U              /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
+                                                                      and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
+
+#define LL_SYSCFG_BANKMODE_BANK2          SYSCFG_MEMRMP_SWP_FB     /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
+                                                                      and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
+/**
+  * @}
+  */
+#endif /* SYSCFG_MEMRMP_SWP_FB */
+
+#if defined(SYSCFG_PMC_MII_RMII_SEL)
+ /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
+* @{
+*/
+#define LL_SYSCFG_PMC_ETHMII               0x00000000U                                         /*!< ETH Media MII interface */
+#define LL_SYSCFG_PMC_ETHRMII              (uint32_t)SYSCFG_PMC_MII_RMII_SEL                   /*!< ETH Media RMII interface */
+
+/**
+  * @}
+  */
+#endif /* SYSCFG_PMC_MII_RMII_SEL */
+
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+  * @{
+  */
+#if defined(SYSCFG_PMC_I2C1_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1        SYSCFG_PMC_I2C1_FMP       /*!< Enable Fast Mode Plus for I2C1      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2        SYSCFG_PMC_I2C2_FMP       /*!< Enable Fast Mode Plus for I2C2      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3        SYSCFG_PMC_I2C3_FMP       /*!< Enable Fast Mode Plus for I2C3      */
+#endif /* SYSCFG_PMC_I2C1_FMP */
+#if defined(SYSCFG_PMC_I2C4_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4        SYSCFG_PMC_I2C4_FMP       /*!< Enable Fast Mode Plus for I2C4      */
+#endif /* SYSCFG_PMC_I2C4_FMP */
+#if defined(SYSCFG_PMC_I2C_PB6_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6         SYSCFG_PMC_I2C_PB6_FMP    /*!< Enable Fast Mode Plus on PB6        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7         SYSCFG_PMC_I2C_PB7_FMP    /*!< Enable Fast Mode Plus on PB7        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8         SYSCFG_PMC_I2C_PB8_FMP    /*!< Enable Fast Mode Plus on PB8        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9         SYSCFG_PMC_I2C_PB9_FMP    /*!< Enable Fast Mode Plus on PB9        */
+#endif /* SYSCFG_PMC_I2C_PB6_FMP */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+  * @{
+  */
+#define LL_SYSCFG_EXTI_PORTA               0U               /*!< EXTI PORT A                        */
+#define LL_SYSCFG_EXTI_PORTB               1U               /*!< EXTI PORT B                        */
+#define LL_SYSCFG_EXTI_PORTC               2U               /*!< EXTI PORT C                        */
+#define LL_SYSCFG_EXTI_PORTD               3U               /*!< EXTI PORT D                        */
+#define LL_SYSCFG_EXTI_PORTE               4U               /*!< EXTI PORT E                        */
+#if defined(GPIOF)
+#define LL_SYSCFG_EXTI_PORTF               5U               /*!< EXTI PORT F                        */
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define LL_SYSCFG_EXTI_PORTG               6U               /*!< EXTI PORT G                        */
+#endif /* GPIOG */
+#define LL_SYSCFG_EXTI_PORTH               7U               /*!< EXTI PORT H                        */
+#if defined(GPIOI)
+#define LL_SYSCFG_EXTI_PORTI               8U               /*!< EXTI PORT I                        */
+#endif /* GPIOI */
+#if defined(GPIOJ)
+#define LL_SYSCFG_EXTI_PORTJ               9U               /*!< EXTI PORT J                        */
+#endif /* GPIOJ */
+#if defined(GPIOK)
+#define LL_SYSCFG_EXTI_PORTK               10U              /*!< EXTI PORT k                        */
+#endif /* GPIOK */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+  * @{
+  */
+#define LL_SYSCFG_EXTI_LINE0               (0x000FU << 16U | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1               (0x00F0U << 16U | 0U)  /*!< EXTI_POSITION_4  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2               (0x0F00U << 16U | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3               (0xF000U << 16U | 0U)  /*!< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4               (0x000FU << 16U | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5               (0x00F0U << 16U | 1U)  /*!< EXTI_POSITION_4  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6               (0x0F00U << 16U | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7               (0xF000U << 16U | 1U)  /*!< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8               (0x000FU << 16U | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9               (0x00F0U << 16U | 2U)  /*!< EXTI_POSITION_4  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10              (0x0F00U << 16U | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11              (0xF000U << 16U | 2U)  /*!< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12              (0x000FU << 16U | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13              (0x00F0U << 16U | 3U)  /*!< EXTI_POSITION_4  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14              (0x0F00U << 16U | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15              (0xF000U << 16U | 3U)  /*!< EXTI_POSITION_12 | EXTICR[3] */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+  * @{
+  */
+#if defined(SYSCFG_CBR_CLL)
+#define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CBR_CLL     /*!< Enables and locks the Lockup output (raised during core
+                                                                   lockup state) of Cortex-M7 with Break Input of TIMER1, TIMER8 */
+#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CBR_PVDL    /*!< Enables and locks the PVD connection with TIMER1, TIMER8 Break input.
+                                                                   It also locks (write protect) the PVD_EN and PVDSEL[2:0] bits 
+                                                                   of the power controller */
+#endif /* SYSCFG_CBR_CLL */
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_EC_CMP_PD SYSCFG CMP PD
+  * @{
+  */
+#define LL_SYSCFG_DISABLE_CMP_PD          0x00000000U             /*!< I/O compensation cell power-down mode */
+#define LL_SYSCFG_ENABLE_CMP_PD           SYSCFG_CMPCR_CMP_PD     /*!< I/O compensation cell enabled */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+  * @{
+  */
+#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP          /*!< TIM2 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP          /*!< TIM3 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1_FZ_DBG_TIM4_STOP          /*!< TIM4 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1_FZ_DBG_TIM5_STOP          /*!< TIM5 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP          /*!< TIM6 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP          /*!< TIM7 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1_FZ_DBG_TIM12_STOP         /*!< TIM12 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1_FZ_DBG_TIM13_STOP         /*!< TIM13 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1_FZ_DBG_TIM14_STOP         /*!< TIM14 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1_FZ_DBG_LPTIM1_STOP        /*!< LPTIIM1 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP           /*!< RTC counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP          /*!< Debug Window Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP          /*!< Debug Independent Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C4_STOP      DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
+#define LL_DBGMCU_APB1_GRP1_CAN1_STOP       DBGMCU_APB1_FZ_DBG_CAN1_STOP         /*!< CAN1 debug stopped when Core is halted  */
+#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN2_STOP       DBGMCU_APB1_FZ_DBG_CAN2_STOP         /*!< CAN2 debug stopped when Core is halted  */
+#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN3_STOP       DBGMCU_APB1_FZ_DBG_CAN3_STOP         /*!< CAN3 debug stopped when Core is halted  */
+#endif /*DBGMCU_APB1_FZ_DBG_CAN3_STOP*/
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2_FZ_DBG_TIM1_STOP     /*!< TIM1 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2_FZ_DBG_TIM8_STOP     /*!< TIM8 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_APB2_FZ_DBG_TIM9_STOP     /*!< TIM9 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_APB2_FZ_DBG_TIM10_STOP    /*!< TIM10 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_APB2_FZ_DBG_TIM11_STOP    /*!< TIM11 counter stopped when core is halted */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+  * @{
+  */
+#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
+#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
+#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
+#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
+#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
+#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
+#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
+#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
+#define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */
+#define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */
+#define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS   /*!< FLASH ten wait states */
+#define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS   /*!< FLASH eleven wait states */
+#define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS   /*!< FLASH twelve wait states */
+#define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS   /*!< FLASH thirteen wait states */
+#define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS   /*!< FLASH fourteen wait states */
+#define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS   /*!< FLASH fifteen wait states */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+  * @{
+  */
+
+/**
+  * @brief  Enables the FMC Memory Mapping Swapping
+  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_EnableFMCMemorySwapping
+  * @note   SDRAM is accessible at 0x60000000 and NOR/RAM
+  *         is accessible at 0xC0000000
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
+{
+  SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
+}
+
+/**
+  * @brief  Disables the FMC Memory Mapping Swapping
+  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_DisableFMCMemorySwapping
+  * @note   SDRAM is accessible at 0xC0000000 (default mapping)
+  *         and NOR/RAM is accessible at 0x60000000 (default mapping)
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
+{
+  CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
+}
+
+/**
+  * @brief  Enables the Compensation Cell
+  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_EnableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
+{
+  SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
+}
+
+/**
+  * @brief  Disables the Compensation Cell
+  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_DisableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
+}
+
+/**
+  * @brief  Get Compensation Cell ready Flag
+  * @rmtoll SYSCFG_CMPCR READY  LL_SYSCFG_IsActiveFlag_CMPCR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
+{
+  return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
+}
+
+
+/**
+  * @brief  Get the memory boot mapping as configured by user
+  * @rmtoll SYSCFG_MEMRMP MEM_BOOT      LL_SYSCFG_GetRemapMemoryBoot
+  * @retval Returned value can be one of the following values:
+  *           @arg @ref LL_SYSCFG_REMAP_BOOT0
+  *           @arg @ref LL_SYSCFG_REMAP_BOOT1
+  *
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemoryBoot(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT));
+}
+
+#if defined(SYSCFG_PMC_MII_RMII_SEL)
+/**
+  * @brief  Select Ethernet PHY interface
+  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_SetPHYInterface
+  * @param  Interface This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_PMC_ETHMII
+  *         @arg @ref LL_SYSCFG_PMC_ETHRMII
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
+{
+  MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
+}
+
+/**
+  * @brief  Get Ethernet PHY interface
+  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_GetPHYInterface
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_PMC_ETHMII
+  *         @arg @ref LL_SYSCFG_PMC_ETHRMII
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
+}
+#endif /* SYSCFG_PMC_MII_RMII_SEL */
+
+
+#if defined(SYSCFG_MEMRMP_SWP_FB)
+/**
+  * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_SetFlashBankMode
+  * @param  Bank This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
+{
+  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB, Bank);
+}
+
+/**
+  * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_GetFlashBankMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB));
+}
+
+#endif /* SYSCFG_MEMRMP_SWP_FB */
+
+#if defined(SYSCFG_PMC_I2C1_FMP)
+/**
+  * @brief  Enable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_PMC I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
+  *         SYSCFG_PMC I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  SET_BIT(SYSCFG->PMC, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Disable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_PMC I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
+  *         SYSCFG_PMC I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  CLEAR_BIT(SYSCFG->PMC, ConfigFastModePlus);
+}
+#endif /* SYSCFG_PMC_I2C1_FMP */
+
+
+/**
+  * @brief  Configure source input for the EXTI external interrupt.
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
+  * @param  Port This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         @arg @ref LL_SYSCFG_EXTI_PORTI
+  *         @arg @ref LL_SYSCFG_EXTI_PORTJ
+  *         @arg @ref LL_SYSCFG_EXTI_PORTK
+  *
+  *         (*) value not defined in all devices
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+  MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
+}
+
+/**
+  * @brief  Get the configured defined for specific EXTI Line
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         @arg @ref LL_SYSCFG_EXTI_PORTI
+  *         @arg @ref LL_SYSCFG_EXTI_PORTJ
+  *         @arg @ref LL_SYSCFG_EXTI_PORTK
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
+}
+
+#if defined(SYSCFG_CBR_CLL)
+/**
+  * @brief  Set connections to TIM1/8/15/16/17 Break inputs
+  *         SYSCFG_CBR CLL             LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CBR PVDL            LL_SYSCFG_SetTIMBreakInputs
+  * @param  Break This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+  MODIFY_REG(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL, Break);
+}
+
+/**
+  * @brief  Get connections to TIM1/8/15/16/17 Break inputs
+  *         SYSCFG_CBR CLL             LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CBR PVDL            LL_SYSCFG_GetTIMBreakInputs
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL));
+}
+#endif /* SYSCFG_CBR_CLL */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+  * @{
+  */
+
+/**
+  * @brief  Return the device identifier
+  * @note For STM32F75xxx and STM32F74xxx devices, the device ID is 0x449
+  * @note For STM32F77xxx and STM32F76xxx devices, the device ID is 0x451
+  * @note For STM32F72xxx and STM32F73xxx devices, the device ID is 0x452
+  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+  * @brief  Return the device revision identifier
+  * @note This field indicates the revision of the device.
+          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
+  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Set Trace pin assignment control
+  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
+  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
+  * @param  PinAssignment This parameter can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRACE_NONE
+  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+  * @brief  Get Trace pin assignment control
+  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
+  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRACE_NONE
+  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+  * @brief  Freeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_LPTIM1_STOP         LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_LPTIM1_STOP         LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+  * @brief  Freeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+}
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+  * @{
+  */
+
+/**
+  * @brief  Set FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
+  * @param  Latency This parameter can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  *         @arg @ref LL_FLASH_LATENCY_8
+  *         @arg @ref LL_FLASH_LATENCY_9
+  *         @arg @ref LL_FLASH_LATENCY_10
+  *         @arg @ref LL_FLASH_LATENCY_11
+  *         @arg @ref LL_FLASH_LATENCY_12
+  *         @arg @ref LL_FLASH_LATENCY_13
+  *         @arg @ref LL_FLASH_LATENCY_14
+  *         @arg @ref LL_FLASH_LATENCY_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+  * @brief  Get FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  *         @arg @ref LL_FLASH_LATENCY_8
+  *         @arg @ref LL_FLASH_LATENCY_9
+  *         @arg @ref LL_FLASH_LATENCY_10
+  *         @arg @ref LL_FLASH_LATENCY_11
+  *         @arg @ref LL_FLASH_LATENCY_12
+  *         @arg @ref LL_FLASH_LATENCY_13
+  *         @arg @ref LL_FLASH_LATENCY_14
+  *         @arg @ref LL_FLASH_LATENCY_15
+  */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+  * @brief  Enable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Disable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Check if Prefetch buffer is enabled
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+  return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
+}
+
+
+
+/**
+  * @brief  Enable ART Accelerator
+  * @rmtoll FLASH_ACR    ARTEN      LL_FLASH_EnableART
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableART(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN);
+}
+
+/**
+  * @brief  Disable ART Accelerator
+  * @rmtoll FLASH_ACR    ARTEN      LL_FLASH_DisableART
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableART(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN);
+}
+
+/**
+  * @brief  Enable ART Reset
+  * @rmtoll FLASH_ACR    ARTRST      LL_FLASH_EnableARTReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableARTReset(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_ARTRST);
+}
+
+/**
+  * @brief  Disable ART Reset
+  * @rmtoll FLASH_ACR    ARTRST      LL_FLASH_DisableARTReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableARTReset(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTRST);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_LL_SYSTEM_H */
+
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h
new file mode 100644
index 0000000..6994e0b
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h
@@ -0,0 +1,4737 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_LL_TIM_H
+#define __STM32F7xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7)
+
+/** @defgroup TIM_LL TIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  * @{
+  */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+  0x00U,   /* 0: TIMx_CH1  */
+  0x00U,   /* 1: TIMx_CH1N */
+  0x00U,   /* 2: TIMx_CH2  */
+  0x00U,   /* 3: TIMx_CH2N */
+  0x04U,   /* 4: TIMx_CH3  */
+  0x04U,   /* 5: TIMx_CH3N */
+  0x04U,   /* 6: TIMx_CH4  */
+  0x3CU,   /* 7: TIMx_CH5  */
+  0x3CU    /* 8: TIMx_CH6  */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+  0U,            /* 0: OC1M, OC1FE, OC1PE */
+  0U,            /* 1: - NA */
+  8U,            /* 2: OC2M, OC2FE, OC2PE */
+  0U,            /* 3: - NA */
+  0U,            /* 4: OC3M, OC3FE, OC3PE */
+  0U,            /* 5: - NA */
+  8U,            /* 6: OC4M, OC4FE, OC4PE */
+  0U,            /* 7: OC5M, OC5FE, OC5PE */
+  8U             /* 8: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+  0U,            /* 0: CC1S, IC1PSC, IC1F */
+  0U,            /* 1: - NA */
+  8U,            /* 2: CC2S, IC2PSC, IC2F */
+  0U,            /* 3: - NA */
+  0U,            /* 4: CC3S, IC3PSC, IC3F */
+  0U,            /* 5: - NA */
+  8U,            /* 6: CC4S, IC4PSC, IC4F */
+  0U,            /* 7: - NA */
+  0U             /* 8: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+  0U,            /* 0: CC1P */
+  2U,            /* 1: CC1NP */
+  4U,            /* 2: CC2P */
+  6U,            /* 3: CC2NP */
+  8U,            /* 4: CC3P */
+  10U,           /* 5: CC3NP */
+  12U,           /* 6: CC4P */
+  16U,           /* 7: CC5P */
+  20U            /* 8: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+  0U,            /* 0: OIS1 */
+  1U,            /* 1: OIS1N */
+  2U,            /* 2: OIS2 */
+  3U,            /* 3: OIS2N */
+  4U,            /* 4: OIS3 */
+  5U,            /* 5: OIS3N */
+  6U,            /* 6: OIS4 */
+  8U,            /* 7: OIS5 */
+  10U            /* 8: OIS6 */
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+  * @{
+  */
+
+#if   defined(TIM_BREAK_INPUT_SUPPORT)
+/* Defines used for the bit position in the register and perform offsets */
+#define TIM_POSITION_BRK_SOURCE           (POSITION_VAL(Source) & 0x1FUL)
+
+/* Generic bit definitions for TIMx_AF1 register */
+#define TIMx_AF1_BKINP        TIM1_AF1_BKINP       /*!< BRK BKIN input polarity */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+
+/* Remap mask definitions */
+#define TIMx_OR_RMP_SHIFT  16U
+#define TIMx_OR_RMP_MASK   0x0000FFFFU
+#define TIM2_OR_RMP_MASK   (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
+#define TIM5_OR_RMP_MASK   (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
+#define TIM11_OR_RMP_MASK  (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+  * @{
+  */
+/** @brief  Convert channel id into channel index.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval none
+  */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
+
+/** @brief  Calculate the deadtime sampling period(in ps).
+  * @param  __TIMCLK__ timer input clock frequency (in Hz).
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval none
+  */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  TIM Time Base configuration structure definition.
+  */
+typedef struct
+{
+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetPrescaler().*/
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetCounterMode().*/
+
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must
+                                   be a number between 0x0000 and 0xFFFFFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetAutoReload().*/
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetClockDivision().*/
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                   reaches zero, an update event is generated and counting restarts
+                                   from the RCR value (N).
+                                   This means in PWM mode that (N+1) corresponds to:
+                                      - the number of PWM periods in edge-aligned mode
+                                      - the number of half PWM period in center-aligned mode
+                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                   Max_Data = 0xFF.
+                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                   Max_Data = 0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the output mode.
+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetMode().*/
+
+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                               This feature can be modified afterwards using unitary function
+                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture configuration structure definition.
+  */
+
+typedef struct
+{
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t ICActiveInput; /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+  * @brief  TIM Encoder interface configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_SetEncoderMode().*/
+
+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+  * @brief  TIM Hall sensor interface configuration structure definition.
+  */
+typedef struct
+{
+
+  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+                                    Prescaler must be set to get a maximum counter period longer than the
+                                    time interval between 2 consecutive changes on the Hall inputs.
+                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+                                    This parameter can be a value of
+                                    @ref TIM_LL_EC_IC_FILTER.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+                                    A positive pulse (TRGO event) is generated with a programmable delay every time
+                                    a change occurs on the Hall inputs.
+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+  * @brief  BDTR (Break and Dead Time) structure definition
+  */
+typedef struct
+{
+  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                       programmed. */
+
+  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                      programmed. */
+
+  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+                                      register has been written, their content is frozen until the next reset.*/
+
+  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_OC_SetDeadTime()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+                                       programmed. */
+
+  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+  * @{
+  */
+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
+#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
+#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+  * @{
+  */
+#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+  * @{
+  */
+#define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+  * @{
+  */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+  * @{
+  */
+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+  * @{
+  */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+  * @{
+  */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+  * @{
+  */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!< Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+  * @{
+  */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+  * @{
+  */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+  * @{
+  */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+  * @{
+  */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+  * @{
+  */
+#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
+#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
+#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+  * @{
+  */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
+/**
+@endcond
+  */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+  * @{
+  */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/
+#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
+  * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+  * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
+  *        to TIMx_CNT register bit 31)
+  * @param  __CNT__ Counter value
+  * @retval UIF status bit
+  */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
+  (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @param  __DT__ deadtime duration (in ns)
+  * @retval DTG[0:7]
+  */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
+    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
+    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
+                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
+    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+    0U)
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *         (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+  * @param  __ICPSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+  */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+  * @{
+  */
+/**
+  * @brief  Enable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Disable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Indicates whether the timer counter is enabled.
+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Disable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Indicates whether update event generation is enabled.
+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval Inverted state of bit (0 or 1).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set update event source
+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+  *       generate an update interrupt or DMA request if enabled:
+  *        - Counter overflow/underflow
+  *        - Setting the UG bit
+  *        - Update generation through the slave mode controller
+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+  *       overflow/underflow generates an update interrupt or DMA request if enabled.
+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+  * @param  TIMx Timer instance
+  * @param  UpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+  * @brief  Get actual event update source
+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+  * @brief  Set one pulse mode (one shot v.s. repetitive).
+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+  * @param  TIMx Timer instance
+  * @param  OnePulseMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+  * @brief  Get actual one pulse mode.
+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+  * @brief  Set the timer counter counting mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *       requires a timer reset to avoid unexpected direction
+  *       due to DIR bit readonly in center aligned mode.
+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+  *         CR1          CMS           LL_TIM_SetCounterMode
+  * @param  TIMx Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+  * @brief  Get actual counter mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+  *         CR1          CMS           LL_TIM_GetCounterMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
+{
+  uint32_t counter_mode;
+
+  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+  if (counter_mode == 0U)
+  {
+    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+  }
+
+  return counter_mode;
+}
+
+/**
+  * @brief  Enable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Disable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
+  *         (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+  * @param  TIMx Timer instance
+  * @param  ClockDivision This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
+  *         generators (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+  * @brief  Set the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_SetCounter
+  * @param  TIMx Timer instance
+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+  WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+  * @brief  Get the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_GetCounter
+  * @param  TIMx Timer instance
+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+  * @brief  Get the current direction of the counter
+  * @rmtoll CR1          DIR           LL_TIM_GetDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+  * @brief  Set the prescaler value.
+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+  * @note The prescaler can be changed on the fly as this control register is buffered. The new
+  *       prescaler ratio is taken into account at the next update event.
+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Prescaler between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+  WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the prescaler value.
+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+  * @param  TIMx Timer instance
+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+  * @brief  Set the auto-reload value.
+  * @note The counter is blocked while the auto-reload value is null.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+  * @param  TIMx Timer instance
+  * @param  AutoReload between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+  WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+  * @brief  Get the auto-reload value.
+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @param  TIMx Timer instance
+  * @retval Auto-reload value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+  * @brief  Set the repetition counter value.
+  * @note For advanced timer instances RepetitionCounter can be up to 65535.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+  WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+  * @brief  Get the repetition counter value.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @retval Repetition counter value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+  *       in an atomic way.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) copy is set.
+  * @param  Counter Counter value
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
+{
+  return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+  * @{
+  */
+/**
+  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+  *       they are updated only when a commutation event (COM) occurs.
+  * @note Only on channels that have a complementary output.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+  * @param  TIMx Timer instance
+  * @param  CCUpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+  * @brief  Set the trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @param  DMAReqTrigger This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+  * @brief  Get actual trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+  * @brief  Set the lock level to freeze the
+  *         configuration of several capture/compare parameters.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       the lock mechanism is supported by a timer instance.
+  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+  * @param  TIMx Timer instance
+  * @param  LockLevel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+  *         @arg @ref LL_TIM_LOCKLEVEL_1
+  *         @arg @ref LL_TIM_LOCKLEVEL_2
+  *         @arg @ref LL_TIM_LOCKLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+  * @brief  Enable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_EnableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Disable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_DisableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Indicate whether channel(s) is(are) enabled.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure an output channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS6          LL_TIM_OC_ConfigOutput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Define the behavior of the output reference signal OCxREF from which
+  *         OCx and OCxN (when relevant) are derived.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_SetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Get the output compare mode of an output channel.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_GetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the IDLE state of an output channel
+  * @note This function is significant only for the timer instances
+  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+  *       can be used to check whether or not a timer instance provides
+  *       a break input.
+  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_SetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  IdleState This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Get the IDLE state of an output channel
+  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_GetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Enable fast mode for the output channel.
+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Disable fast mode for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Indicates whether fast mode is enabled for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable clearing the output channel on an external event.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
+  * @note This function enables clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+  *         the Ocx and OCxN signals).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 5 (TIMx_CCR5).
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 6 (TIMx_CCR6).
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+/**
+  * @brief  Select on which reference signal the OC5REF is combined to.
+  * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the combined 3-phase PWM mode.
+  * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
+  * @param  TIMx Timer instance
+  * @param  GroupCH5 This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_GROUPCH5_NONE
+  *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+{
+  MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure input channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC1F          LL_TIM_IC_Config\n
+  *         CCMR1        CC2S          LL_TIM_IC_Config\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC2F          LL_TIM_IC_Config\n
+  *         CCMR2        CC3S          LL_TIM_IC_Config\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC3F          LL_TIM_IC_Config\n
+  *         CCMR2        CC4S          LL_TIM_IC_Config\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC4F          LL_TIM_IC_Config\n
+  *         CCER         CC1P          LL_TIM_IC_Config\n
+  *         CCER         CC1NP         LL_TIM_IC_Config\n
+  *         CCER         CC2P          LL_TIM_IC_Config\n
+  *         CCER         CC2NP         LL_TIM_IC_Config\n
+  *         CCER         CC3P          LL_TIM_IC_Config\n
+  *         CCER         CC3NP         LL_TIM_IC_Config\n
+  *         CCER         CC4P          LL_TIM_IC_Config\n
+  *         CCER         CC4NP         LL_TIM_IC_Config
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
+             << SHIFT_TAB_ICxx[iChannel]);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICActiveInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the prescaler of input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current prescaler value acting on an  input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the current input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+          SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get captured value for input channel 3.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get captured value for input channel 4.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+  * @{
+  */
+/**
+  * @brief  Enable external clock mode 2.
+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Disable external clock mode 2.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Indicate whether external clock mode 2 is enabled.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the clock source of the counter clock.
+  * @note when selected clock source is external clock mode 1, the timer input
+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+  *       function. This timer input must be configured by calling
+  *       the @ref LL_TIM_IC_Config() function.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode1.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+  *         SMCR         ECE           LL_TIM_SetClockSource
+  * @param  TIMx Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+  * @brief  Set the encoder interface mode.
+  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the encoder mode.
+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+  * @param  TIMx Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger output (TRGO) used for timer synchronization .
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can operate as a master timer.
+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+  * @param  TIMx Timer instance
+  * @param  TimerSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO_RESET
+  *         @arg @ref LL_TIM_TRGO_ENABLE
+  *         @arg @ref LL_TIM_TRGO_UPDATE
+  *         @arg @ref LL_TIM_TRGO_CC1IF
+  *         @arg @ref LL_TIM_TRGO_OC1REF
+  *         @arg @ref LL_TIM_TRGO_OC2REF
+  *         @arg @ref LL_TIM_TRGO_OC3REF
+  *         @arg @ref LL_TIM_TRGO_OC4REF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+  * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
+  * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can be used for ADC synchronization.
+  * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
+  * @param  TIMx Timer Instance
+  * @param  ADCSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO2_RESET
+  *         @arg @ref LL_TIM_TRGO2_ENABLE
+  *         @arg @ref LL_TIM_TRGO2_UPDATE
+  *         @arg @ref LL_TIM_TRGO2_CC1F
+  *         @arg @ref LL_TIM_TRGO2_OC1
+  *         @arg @ref LL_TIM_TRGO2_OC2
+  *         @arg @ref LL_TIM_TRGO2_OC3
+  *         @arg @ref LL_TIM_TRGO2_OC4
+  *         @arg @ref LL_TIM_TRGO2_OC5
+  *         @arg @ref LL_TIM_TRGO2_OC6
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+/**
+  * @brief  Set the synchronization mode of a slave timer.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+  * @param  TIMx Timer instance
+  * @param  SlaveMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+  *         @arg @ref LL_TIM_SLAVEMODE_RESET
+  *         @arg @ref LL_TIM_SLAVEMODE_GATED
+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+  * @brief  Set the selects the trigger input to be used to synchronize the counter.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+  * @param  TIMx Timer instance
+  * @param  TriggerInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TS_ITR0
+  *         @arg @ref LL_TIM_TS_ITR1
+  *         @arg @ref LL_TIM_TS_ITR2
+  *         @arg @ref LL_TIM_TS_ITR3
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+  * @brief  Enable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief  Disable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief Indicates whether the Master/Slave mode is enabled.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the external trigger (ETR) input.
+  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an external trigger input.
+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+  *         SMCR         ETPS          LL_TIM_ConfigETR\n
+  *         SMCR         ETF           LL_TIM_ConfigETR
+  * @param  TIMx Timer instance
+  * @param  ETRPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+  * @param  ETRPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+  * @param  ETRFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+                                      uint32_t ETRFilter)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+  * @{
+  */
+/**
+  * @brief  Enable the break function.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+  * @brief  Disable the break function.
+  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+  * @param  TIMx Timer instance
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+  * @brief  Configure the break input.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+  *         BDTR         BKF           LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @param  BreakFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
+                                      uint32_t BreakFilter)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
+}
+
+/**
+  * @brief  Enable the break 2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+  * @brief  Disable the break  2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+  * @brief  Configure the break 2 input.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2F          LL_TIM_ConfigBRK2
+  * @param  TIMx Timer instance
+  * @param  Break2Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+  * @param  Break2Filter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
+}
+
+/**
+  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+  *         BDTR         OSSR          LL_TIM_SetOffStates
+  * @param  TIMx Timer instance
+  * @param  OffStateIdle This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSI_DISABLE
+  *         @arg @ref LL_TIM_OSSI_ENABLE
+  * @param  OffStateRun This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSR_DISABLE
+  *         @arg @ref LL_TIM_OSSR_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Disable automatic output (MOE can be set only by software).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Indicate whether automatic output is enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Indicates whether outputs are enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+}
+
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+/**
+  * @brief  Enable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE          LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKDFBKE        LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2INE         LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2DFBKE       LL_TIM_EnableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  SET_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Disable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE          LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKDFBKE        LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2INE         LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2DFBKE       LL_TIM_DisableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  CLEAR_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Set the polarity of the break signal for the timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINP          LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKDFBKP        LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2INP         LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2DFBKP       LL_TIM_SetBreakInputSourcePolarity
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
+  *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
+                                                        uint32_t Polarity)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
+}
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+  * @{
+  */
+/**
+  * @brief  Configures the timer DMA burst feature.
+  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports the DMA burst mode.
+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+  *         DCR          DBA           LL_TIM_ConfigDMABurst
+  * @param  TIMx Timer instance
+  * @param  DMABurstBaseAddress This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1  (*)
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2  (*)
+  *         (*) value not defined in all devices
+  * @param  DMABurstLength This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+  * @{
+  */
+/**
+  * @brief  Remap TIM inputs (input channel, internal/external triggers).
+  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+  *       a some timer inputs can be remapped.
+  * @rmtoll TIM2_OR     ITR1_RMP          LL_TIM_SetRemap\n
+  *         TIM5_OR     TI4_RMP           LL_TIM_SetRemap\n
+  *         TIM11_OR    TI1_RMP           LL_TIM_SetRemap
+  * @param  TIMx Timer instance
+  * @param  Remap Remap param depends on the TIMx. Description available only
+  *         in CHM version of the User Manual (not in .pdf).
+  *         Otherwise see Reference Manual description of OR registers.
+  *
+  *         Below description summarizes "Timer Instance" and "Remap" param combinations:
+  *
+  *         TIM2: one of the following values
+  *
+  *            ITR1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
+  *            @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP
+  *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
+  *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
+  *
+  *         TIM5: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
+  *            @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
+  *            @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
+  *
+  *         TIM11: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_HSE
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+  MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+  * @{
+  */
+/**
+  * @brief  Clear the update interrupt flag (UIF).
+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
+  * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
+  * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
+  * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
+  * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the commutation interrupt flag (COMIF).
+  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the trigger interrupt flag (TIF).
+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break interrupt flag (BIF).
+  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break 2 interrupt flag (B2IF).
+  * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+  * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+  * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+  *         (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+  *         (Capture/Compare 2 over-capture interrupt is pending).
+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+  *         (Capture/Compare 3 over-capture interrupt is pending).
+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+  *         (Capture/Compare 4 over-capture interrupt is pending).
+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the system break interrupt flag (SBIF).
+  * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+}
+
+/**
+  * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
+  * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+  * @{
+  */
+/**
+  * @brief  Enable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Disable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Indicates whether the update interrupt (UIE) is enabled.
+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Disable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
+  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Disable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Indicates whether the break interrupt (BIE) is enabled.
+  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Disable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Disable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
+  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+  * @{
+  */
+/**
+  * @brief  Generate an update event.
+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+  * @brief  Generate Capture/Compare 1 event.
+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 2 event.
+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 3 event.
+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 4 event.
+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+  * @brief  Generate commutation event.
+  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+  * @brief  Generate trigger event.
+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+  * @brief  Generate break event.
+  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+  * @brief  Generate break 2 event.
+  * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM8 || TIM2 || TIM3 ||  TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_LL_TIM_H */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h
new file mode 100644
index 0000000..daa329e
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h
@@ -0,0 +1,3804 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_LL_USART_H
+#define STM32F7xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \
+ || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_WriteReg function
+  * @{
+  */
+#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error clear flag */
+#define LL_USART_ICR_NCF                        USART_ICR_NCF                 /*!< Noise error detected clear flag */
+#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected clear flag */
+#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete clear flag */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time clear flag */
+#endif /* USART_TCBGT_SUPPORT */
+#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block clear flag */
+#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match clear flag */
+#if defined(USART_CR1_UESM)
+#if defined(USART_CR3_WUFIE)
+#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
+#endif /* USART_CR3_WUFIE */
+#endif /* USART_CR1_UESM */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
+#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
+#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE                       USART_ISR_RXNE                /*!< Read data register not empty flag */
+#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE                        USART_ISR_TXE                 /*!< Transmit data register empty flag */
+#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
+#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
+#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
+#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#if defined(USART_CR1_UESM)
+#if defined(USART_CR3_WUFIE)
+#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#endif /* USART_CR3_WUFIE */
+#endif /* USART_CR1_UESM */
+#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#if defined(USART_ISR_REACK)
+#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+#endif /* USART_ISR_REACK */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
+#endif /* USART_TCBGT_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#if defined(USART_CR1_UESM)
+#if defined(USART_CR3_WUFIE)
+#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+#endif /* USART_CR3_WUFIE */
+#endif /* USART_CR1_UESM */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
+#endif /* USART_TCBGT_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+  * @{
+  */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+#if defined(USART_CR1_UESM)
+#if defined(USART_CR3_WUS)
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+#endif /* USART_CR3_WUS */
+#endif /* USART_CR1_UESM */
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\
+                                                                + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_ISR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_UESM)
+/**
+  * @brief  USART enabled in STOP Mode.
+  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+  *         USART clock selection is HSI or LSE in RCC.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  USART disabled in STOP Mode.
+  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR3_UCESM)
+/**
+  * @brief  USART Clock enabled in STOP Mode
+  * @note   When this function is called, USART Clock is enabled while in STOP mode
+  * @rmtoll CR3          UCESM         LL_USART_EnableClockInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM);
+}
+
+/**
+  * @brief  USART clock disabled in STOP Mode
+  * @note   When this function is called, USART Clock is disabled while in STOP mode
+  * @rmtoll CR3          UCESM         LL_USART_DisableClockInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM);
+}
+
+/**
+  * @brief  Indicate if USART clock is enabled in STOP Mode
+  * @rmtoll CR3          UCESM         LL_USART_IsClockEnabledInStopMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM));
+}
+
+#endif /* USART_CR3_UCESM */
+#endif /* USART_CR1_UESM*/
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+  *         CR1          M1            LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+  *         CR1          M1            LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M0            LL_USART_ConfigCharacter\n
+  *         CR1          M1            LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+  * @param  USARTx USART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Enable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Disable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Auto Baud-Rate mode bits
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @param  AutoBaudRateMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+  * @brief  Return Auto Baud-Rate mode
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+  * @brief  Enable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Disable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Indicate if Receiver Timeout feature is enabled
+  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+  * @param  USARTx USART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_UESM)
+#if defined(USART_CR3_WUS)
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+  * @param  USARTx USART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+#endif /* USART_CR3_WUS */
+#endif /* USART_CR1_UESM */
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  uint32_t usartdiv;
+  uint32_t brrtemp;
+
+  if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+    brrtemp = usartdiv & 0xFFF0U;
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+    USARTx->BRR = brrtemp;
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
+{
+  uint32_t usartdiv;
+  uint32_t brrresult = 0x0U;
+
+  usartdiv = USARTx->BRR;
+
+  if (usartdiv == 0U)
+  {
+    /* Do not perform a division by 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+    if (usartdiv != 0U)
+    {
+      brrresult = (PeriphClk * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = PeriphClk / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+  * @param  USARTx USART Instance
+  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+  * @brief  Set Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+  * @param  USARTx USART Instance
+  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @brief  Get Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+  *         In transmission mode, it specifies the number of automatic retransmission retries, before
+  *         generating a transmission error (FE bit set).
+  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
+  *         reception error (RXNE and PE bits set)
+  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
+  * @rmtoll ISR          RXNE          LL_USART_IsActiveFlag_RXNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
+  * @rmtoll ISR          TXE           LL_USART_IsActiveFlag_TXE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS interrupt Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Time Out Flag is set or not
+  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Flag is set or not
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_UESM)
+#if defined(USART_CR3_WUFIE)
+/**
+  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR3_WUFIE */
+#endif /* USART_CR1_UESM */
+/**
+  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+#if defined(USART_ISR_REACK)
+/**
+  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+#endif /* USART_ISR_REACK */
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+}
+
+#endif /* USART_TCBGT_SUPPORT */
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise Error detected Flag
+  * @rmtoll ICR          NCF           LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_NCF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+#endif /* USART_TCBGT_SUPPORT */
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Receiver Time Out Flag
+  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+  * @brief  Clear End Of Block Flag
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+#if defined(USART_CR1_UESM)
+#if defined(USART_CR3_WUFIE)
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+#endif /* USART_CR3_WUFIE */
+#endif /* USART_CR1_UESM */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Enable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Enable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Enable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+#if defined(USART_CR1_UESM)
+#if defined(USART_CR3_WUFIE)
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+#endif /* USART_CR3_WUFIE */
+#endif /* USART_CR1_UESM */
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+#endif /* USART_TCBGT_SUPPORT */
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Disable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Disable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+#if defined(USART_CR1_UESM)
+#if defined(USART_CR3_WUFIE)
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+#endif /* USART_CR3_WUFIE */
+#endif /* USART_CR1_UESM */
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+#endif /* USART_TCBGT_SUPPORT */
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_UESM)
+#if defined(USART_CR3_WUFIE)
+/**
+  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR3_WUFIE */
+#endif /* USART_CR1_UESM */
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+}
+#endif /* USART_TCBGT_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+  * @param  USARTx USART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(USARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(USARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request an Automatic Baud Rate measurement on next received data frame
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
+}
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put USART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data flush
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data flush
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F7xx_LL_USART_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h
new file mode 100644
index 0000000..87806ae
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h
@@ -0,0 +1,304 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_utils.h
+  * @author  MCD Application Team
+  * @brief   Header file of UTILS LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL UTILS driver contains a set of generic APIs that can be
+    used by user:
+      (+) Device electronic signature
+      (+) Timing functions
+      (+) PLL configuration functions
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_LL_UTILS_H
+#define __STM32F7xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx.h"
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup UTILS_LL UTILS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+  * @{
+  */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY                  0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS              UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+  * @{
+  */
+/**
+  * @brief  UTILS PLL structure definition
+  */
+typedef struct
+{
+  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
+                        This parameter must be a number between Min_Data = 50 and Max_Data = 432
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+  uint32_t PLLP;   /*!< Division for the main system clock.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAHBPrescaler(). */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB1Prescaler(). */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+  * @{
+  */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+  * @{
+  */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+  * @{
+  */
+#define LL_UTILS_PACKAGETYPE_LQFP100                    0x00000100U /*!< LQFP100 package type                         */
+#define LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143           0x00000200U /*!< LQFP144 or WLCSP143 package type             */
+#define LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176  0x00000300U /*!< WLCSP180, LQFP176 or UFBGA176 package type   */
+#define LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216   0x00000400U /*!< LQFP176, LQFP208 or TFBGA216 package type    */ 
+#define LL_UTILS_PACKAGETYPE_TFBGA216_LQFP176_LQFP208   0x00000500U /*!< LQFP176, LQFP208 or TFBGA216 package type    */ 
+#define LL_UTILS_PACKAGETYPE_LQFP176_TFBGA216_LQFP208   0x00000600U /*!< LQFP176, LQFP208 or TFBGA216 package type    */ 
+#define LL_UTILS_PACKAGETYPE_LQFP208_LQFP176_TFBGA216   0x00000700U /*!< LQFP176, LQFP208 or TFBGA216 package type    */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+  * @{
+  */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+  * @{
+  */
+
+/**
+  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[31:0]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[63:32]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[95:64]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+  * @brief  Get Flash memory size
+  * @note   This bitfield indicates the size of the device Flash memory expressed in
+  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+  * @retval FLASH_SIZE[15:0]: Flash memory size
+  */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
+}
+
+/**
+  * @brief  Get Package type
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source of the time base.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick 
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  Ticks Frequency of Ticks (Hz)
+  * @retval None
+  */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+  /* Configure the SysTick to have interrupt in 1ms time base */
+  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
+  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
+}
+
+void        LL_Init1msTick(uint32_t HCLKFrequency);
+void        LL_mDelay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+  * @{
+  */
+
+void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_LL_UTILS_H */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/LICENSE.txt b/Drivers/STM32F7xx_HAL_Driver/LICENSE.txt
new file mode 100644
index 0000000..b40364c
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/LICENSE.txt
@@ -0,0 +1,6 @@
+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the BSD-3-Clause license shall apply. 
+You may obtain a copy of the BSD-3-Clause at:
+https://opensource.org/licenses/BSD-3-Clause
diff --git a/Drivers/STM32F7xx_HAL_Driver/License.md b/Drivers/STM32F7xx_HAL_Driver/License.md
new file mode 100644
index 0000000..008472d
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/License.md
@@ -0,0 +1 @@
+License.md file kept for legacy purpose
\ No newline at end of file
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c
new file mode 100644
index 0000000..3ba2bc6
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c
@@ -0,0 +1,620 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal.c
+  * @author  MCD Application Team
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL. 
+    [..]
+    The HAL contains two APIs' categories: 
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL HAL
+  * @brief HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup HAL_Private_Constants
+  * @{
+  */
+/**
+ * @brief STM32F7xx HAL Driver version number V1.3.1
+   */
+#define __STM32F7xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F7xx_HAL_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32F7xx_HAL_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F7xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F7xx_HAL_VERSION         ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
+                                        |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
+                                        |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\
+                                        |(__STM32F7xx_HAL_VERSION_RC))
+                                        
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Exported variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions 
+ *  @brief    Initialization and de-initialization functions
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initializes the Flash interface the NVIC allocation and initial clock 
+          configuration. It initializes the systick also when timeout is needed 
+          and the backup domain when enabled.
+      (+) De-Initializes common part of the HAL.
+      (+) Configure the time base source to have 1ms time base with a dedicated 
+          Tick interrupt priority. 
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose 
+             timer for example or other time source), keeping in mind that Time base 
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically 
+             at the beginning of the program after reset by HAL_Init() or at any time 
+             when clock is configured, by HAL_RCC_ClockConfig(). 
+        (++) Source of time base is configured  to generate interrupts at regular 
+             time intervals. Care must be taken if HAL_Delay() is called from a 
+             peripheral ISR process, the Tick interrupt line must have higher priority 
+            (numerically lower) than the peripheral interrupt. Otherwise the caller 
+            ISR process will be blocked. 
+       (++) functions affecting time base configurations are declared as __weak  
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function is used to initialize the HAL Library; it must be the first 
+  *         instruction to be executed in the main program (before to call any other
+  *         HAL function), it performs the following:
+  *           Configure the Flash prefetch, and instruction cache through ART accelerator.
+  *           Configures the SysTick to generate an interrupt each 1 millisecond,
+  *           which is clocked by the HSI (at this stage, the clock is not yet
+  *           configured and thus the system is running from the internal HSI at 16 MHz).
+  *           Set NVIC Group Priority to 4.
+  *           Calls the HAL_MspInit() callback function defined in user file 
+  *           "stm32f7xx_hal_msp.c" to do the global low level hardware initialization 
+  *            
+  * @note   SysTick is used as time base for the HAL_Delay() function, the application
+  *         need to ensure that the SysTick time base is always set to 1 millisecond
+  *         to have correct HAL operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+  /* Configure Instruction cache through ART accelerator */ 
+#if (ART_ACCELERATOR_ENABLE != 0)
+  __HAL_FLASH_ART_ENABLE();
+#endif /* ART_ACCELERATOR_ENABLE */
+
+  /* Configure Flash prefetch */
+#if (PREFETCH_ENABLE != 0U)
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  HAL_InitTick(TICK_INT_PRIORITY);
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function de-Initializes common part of the HAL and stops the systick.
+  *         This function is optional.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_APB1_FORCE_RESET();
+  __HAL_RCC_APB1_RELEASE_RESET();
+
+  __HAL_RCC_APB2_FORCE_RESET();
+  __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB1_FORCE_RESET();
+  __HAL_RCC_AHB1_RELEASE_RESET();
+
+  __HAL_RCC_AHB2_FORCE_RESET();
+  __HAL_RCC_AHB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB3_FORCE_RESET();
+  __HAL_RCC_AHB3_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief This function configures the source of the time base.
+  *        The time source is configured  to have 1ms time base with a dedicated 
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base. 
+  *       It is used to generate interrupts at regular time intervals. 
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, 
+  *       The SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  /* Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+    uwTickPrio = TickPriority;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 
+ *  @brief    HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP mode
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment  a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in SysTick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other 
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick += uwTickFreq;
+}
+
+/**
+  * @brief Provides a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other 
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function returns a tick priority.
+  * @retval tick priority
+  */
+uint32_t HAL_GetTickPrio(void)
+{
+  return uwTickPrio;
+}
+
+/**
+  * @brief Set new tick Freq.
+  * @retval Status
+  */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  HAL_TickFreqTypeDef prevTickFreq;
+
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq)
+  {
+    /* Back up uwTickFreq frequency */
+    prevTickFreq = uwTickFreq;
+
+    /* Update uwTickFreq global variable used by HAL_InitTick() */
+    uwTickFreq = Freq;
+
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+
+    if (status != HAL_OK)
+    {
+      /* Restore previous tick frequency */
+      uwTickFreq = prevTickFreq;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Return tick frequency.
+  * @retval Tick frequency.
+  *         Value of @ref HAL_TickFreqTypeDef.
+  */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+  return uwTickFreq;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based
+  *        on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay  specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the SysTick interrupt will be disabled and so Tick increment 
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the SysTick interrupt will be enabled and so Tick increment 
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief  Returns the HAL revision
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+  return __STM32F7xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+   return((DBGMCU->IDCODE) >> 16U);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+  return(READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+  return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+  return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Enables the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @retval None
+  */
+void HAL_EnableCompensationCell(void)
+{
+  SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;
+}
+
+/**
+  * @brief  Power-down the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @retval None
+  */
+void HAL_DisableCompensationCell(void)
+{
+  SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);
+}
+
+/**
+  * @brief  Enables the FMC Memory Mapping Swapping.
+  *   
+  * @note   SDRAM is accessible at 0x60000000 
+  *         and NOR/RAM is accessible at 0xC0000000   
+  *
+  * @retval None
+  */
+void HAL_EnableFMCMemorySwapping(void)
+{
+  SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;
+}
+
+/**
+  * @brief  Disables the FMC Memory Mapping Swapping
+  *   
+  * @note   SDRAM is accessible at 0xC0000000 (default mapping)  
+  *         and NOR/RAM is accessible at 0x60000000 (default mapping)    
+  *           
+  * @retval None
+  */
+void HAL_DisableFMCMemorySwapping(void)
+{
+  SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);
+}
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+/**
+* @brief  Enable the Internal FLASH Bank Swapping.
+*   
+* @note   This function can be used only for STM32F77xx/STM32F76xx devices. 
+*
+* @note   Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) 
+*         and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM))   
+*
+* @retval None
+*/
+void HAL_EnableMemorySwappingBank(void)
+{
+  SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
+}
+
+/**
+* @brief  Disable the Internal FLASH Bank Swapping.
+*   
+* @note   This function can be used only for STM32F77xx/STM32F76xx devices. 
+*
+* @note   The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) 
+*         and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) 
+*           
+* @retval None
+*/
+void HAL_DisableMemorySwappingBank(void)
+{
+  CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
+}
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c
new file mode 100644
index 0000000..15fd1c7
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c
@@ -0,0 +1,2114 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_adc.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Converter (ADC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### ADC Peripheral features #####
+  ==============================================================================
+  [..] 
+  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+  (#) Interrupt generation at the end of conversion, end of injected conversion,  
+      and in case of analog watchdog or overrun events
+  (#) Single and continuous conversion modes.
+  (#) Scan mode for automatic conversion of channel 0 to channel x.
+  (#) Data alignment with in-built data coherency.
+  (#) Channel-wise programmable sampling time.
+  (#) External trigger option with configurable polarity for both regular and 
+      injected conversion.
+  (#) Dual/Triple mode (on devices with 2 ADCs or more).
+  (#) Configurable DMA data storage in Dual/Triple ADC mode. 
+  (#) Configurable delay between conversions in Dual/Triple interleaved mode.
+  (#) ADC conversion type (refer to the datasheets).
+  (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at 
+      slower speed.
+  (#) ADC input range: VREF(minus) = VIN = VREF(plus).
+  (#) DMA request generation during regular channel conversion.
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
+       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
+       (##) ADC pins configuration
+             (+++) Enable the clock for the ADC GPIOs using the following function:
+                   __HAL_RCC_GPIOx_CLK_ENABLE()  
+             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() 
+       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
+             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
+             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
+             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
+       (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
+             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
+             (+++) Configure and enable two DMA streams stream for managing data
+                 transfer from peripheral to memory (output stream)
+             (+++) Associate the initialized DMA handle to the CRYP DMA handle
+                 using  __HAL_LINKDMA()
+             (+++) Configure the priority and enable the NVIC for the transfer complete
+                 interrupt on the two DMA Streams. The output stream should have higher
+                 priority than the input stream.
+                       
+    *** Configuration of ADC, groups regular/injected, channels parameters ***
+  ==============================================================================
+  [..]
+  (#) Configure the ADC parameters (resolution, data alignment, ...)
+      and regular group parameters (conversion trigger, sequencer, ...)
+      using function HAL_ADC_Init().
+
+  (#) Configure the channels for regular group parameters (channel number, 
+      channel rank into sequencer, ..., into regular group)
+      using function HAL_ADC_ConfigChannel().
+
+  (#) Optionally, configure the injected group parameters (conversion trigger, 
+      sequencer, ..., of injected group)
+      and the channels for injected group parameters (channel number, 
+      channel rank into sequencer, ..., into injected group)
+      using function HAL_ADCEx_InjectedConfigChannel().
+
+  (#) Optionally, configure the analog watchdog parameters (channels
+      monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
+
+  (#) Optionally, for devices with several ADC instances: configure the 
+      multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
+
+                       *** Execution of ADC conversions ***
+  ==============================================================================
+  [..]  
+  (#) ADC driver can be used among three modes: polling, interruption,
+      transfer by DMA.    
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]    
+       (+) Start the ADC peripheral using HAL_ADC_Start() 
+       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
+           user can specify the value of timeout according to his end application      
+       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
+       (+) Stop the ADC peripheral using HAL_ADC_Stop()
+       
+     *** Interrupt mode IO operation ***    
+     ===================================
+     [..]    
+       (+) Start the ADC peripheral using HAL_ADC_Start_IT() 
+       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
+       (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can 
+           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback 
+       (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can 
+           add his own code by customization of function pointer HAL_ADC_ErrorCallback
+       (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()     
+
+     *** DMA mode IO operation ***    
+     ==============================
+     [..]    
+       (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length 
+           of data to be transferred at each end of conversion 
+       (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can 
+           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback 
+       (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can 
+           add his own code by customization of function pointer HAL_ADC_ErrorCallback
+       (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
+                    
+     *** ADC HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in ADC HAL driver.
+       
+      (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
+      (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
+      (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
+      (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
+      (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
+      (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
+      (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
+      (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register 
+      
+     *** Callback functions ***
+     ==============================
+     [..]
+      (@) Callback functions must be implemented in user program:
+      (+@) HAL_ADC_ErrorCallback()
+      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+      (+@) HAL_ADC_ConvCpltCallback()
+      (+@) HAL_ADC_ConvHalfCpltCallback
+
+       (@) You can refer to the ADC HAL driver header file for more useful macros 
+
+                      *** Deinitialization of ADC ***
+  ==============================================================================
+  [..]
+  (#) Disable the ADC interface
+     (++) ADC clock can be hard reset and disabled at RCC top level.
+     (++) Hard reset of ADC peripherals
+          using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
+     (++) ADC clock disable using the equivalent macro/functions as configuration step.
+               (+++) Example:
+                   Into HAL_ADC_MspDeInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
+               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
+               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+  (#) ADC pins configuration
+     (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+  (#) Optionally, in case of usage of ADC with interruptions:
+     (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
+
+  (#) Optionally, in case of usage of DMA:
+        (++) Deinitialize the DMA using function HAL_DMA_DeInit().
+        (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)   
+
+                      *** Callback registration ***
+  ==============================================================================
+    [..]
+
+     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_ADC_RegisterCallback()
+     to register an interrupt callback.
+    [..]
+
+     Function HAL_ADC_RegisterCallback() allows to register following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+
+     Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
+     weak function.
+    [..]
+
+     HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     [..]
+
+     By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
+     these callbacks are null (not registered beforehand).
+    [..]
+
+     If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+     [..]
+
+     Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    [..]
+
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
+     or HAL_ADC_Init() function.
+     [..]
+
+     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+    @endverbatim
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADC ADC
+  * @brief ADC driver modules
+  * @{
+  */ 
+
+#ifdef HAL_ADC_MODULE_ENABLED
+    
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions
+  * @{
+  */
+/* Private function prototypes -----------------------------------------------*/
+static void ADC_Init(ADC_HandleTypeDef* hadc);
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the ADC. 
+      (+) De-initialize the ADC. 
+         
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters 
+  *         in the ADC_InitStruct and initializes the ADC MSP.
+  *           
+  * @note   This function is used to configure the global features of the ADC ( 
+  *         ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
+  *         the rest of the configuration parameters are specific to the regular
+  *         channels group (scan mode activation, continuous mode activation,
+  *         External trigger source and edge, DMA continuous request after the  
+  *         last transfer and End of conversion selection).
+  *             
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check ADC handle */
+  if(hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
+  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+  {
+    assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  }
+
+  if(hadc->State == HAL_ADC_STATE_RESET)
+  {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    /* Init the ADC Callback settings */
+    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
+    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
+    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
+    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
+    hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */
+    if (hadc->MspInitCallback == NULL)
+    {
+      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hadc->MspInitCallback(hadc);
+#else
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Initialize ADC error code */
+    ADC_CLEAR_ERRORCODE(hadc);
+    
+    /* Allocate lock resource and initialize it */
+    hadc->Lock = HAL_UNLOCKED;
+  }
+  
+  /* Configuration of ADC parameters if previous preliminary actions are      */ 
+  /* correctly completed.                                                     */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+    
+    /* Set ADC parameters */
+    ADC_Init(hadc);
+    
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+    
+    /* Set the ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_BUSY_INTERNAL,
+                      HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Deinitializes the ADCx peripheral registers to their default reset values. 
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check ADC handle */
+  if(hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+  
+  /* Stop potential conversion on going, on regular and injected groups */
+  /* Disable ADC peripheral */
+  __HAL_ADC_DISABLE(hadc);
+  
+  /* Configuration of ADC parameters if previous preliminary actions are      */ 
+  /* correctly completed.                                                     */
+  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  if (hadc->MspDeInitCallback == NULL)
+  {
+    hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: RCC clock, NVIC */
+  hadc->MspDeInitCallback(hadc);
+#else
+  /* DeInit the low level hardware: RCC clock, NVIC */
+  HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+    
+    /* Set ADC state */
+    hadc->State = HAL_ADC_STATE_RESET;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Initializes the ADC MSP.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.  
+  * @retval None
+  */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitializes the ADC MSP.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.  
+  * @retval None
+  */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_MspDeInit could be implemented in the user file
+   */ 
+}
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User ADC Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = pCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = pCallback;
+        break;
+
+      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+        hadc->InjectedConvCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a ADC Callback
+  *         ADC callback is redirected to the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+        break;
+
+      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+        hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
+ *  @brief    IO operation functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### IO operation functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of regular channel.
+      (+) Stop conversion of regular channel.
+      (+) Start conversion of regular channel and enable interrupt.
+      (+) Stop conversion of regular channel and disable interrupt.
+      (+) Start conversion of regular channel and enable DMA transfer.
+      (+) Stop conversion of regular channel and disable DMA transfer.
+      (+) Handle ADC interrupt request. 
+               
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables ADC and starts conversion of the regular channels.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+  __IO uint32_t counter = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Enable the ADC peripheral */
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+  Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay for ADC stabilization time */
+    /* Compute number of CPU cycles to wait for */
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
+    {
+      counter--;
+    }
+  }
+  
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to regular group conversion results     */
+    /* - Set state bitfield related to regular group operation                */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+                      HAL_ADC_STATE_REG_BUSY);
+    
+    /* If conversions on group regular are also triggering group injected,    */
+    /* update ADC state.                                                      */
+    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+    {
+      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+    }
+    
+    /* State machine update: Check if an injected conversion is ongoing */
+    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+    {
+      /* Reset ADC error code fields related to conversions on group regular */
+      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+    }
+    else
+    {
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);
+    
+    /* Clear regular group conversion flag and overrun flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+    
+    /* Check if Multimode enabled */
+    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+    {
+      /* if no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+      {
+        /* Enable the selected ADC software conversion for regular group */
+        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
+    }
+    else
+    {
+      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+      {
+        /* Enable the selected ADC software conversion for regular group */
+          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
+
+      /* if dual mode is selected, ADC3 works independently. */
+      /* check if the mode selected is not triple */
+      if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
+      {
+        /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
+        if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+        {
+          /* Enable the selected ADC software conversion for regular group */
+          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    
+    /* Set ADC error code to ADC IP internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables ADC and stop conversion of regular channels.
+  * 
+  * @note   Caution: This function will stop also injected channels.  
+  *
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  *
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Stop potential conversion on going, on regular and injected groups */
+  /* Disable ADC peripheral */
+  __HAL_ADC_DISABLE(hadc);
+  
+  /* Check if ADC is effectively disabled */
+  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_READY);
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for regular conversion complete
+  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
+  *         conversion) are cleared by this function.
+  * @note   This function cannot be used in a particular setup: ADC configured 
+  *         in DMA mode and polling for end of each conversion (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+  *         In this case, DMA resets the flag EOC and polling cannot be
+  *         performed on each conversion. Nevertheless, polling can still 
+  *         be performed on the complete sequence.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  Timeout Timeout value in millisecond.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+  
+  /* Verification that ADC configuration is compliant with polling for      */
+  /* each conversion:                                                       */
+  /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
+  /* several ranks and polling for end of each conversion.                  */
+  /* For code simplicity sake, this particular case is generalized to       */
+  /* ADC configured in DMA mode and polling for end of each conversion.     */
+  if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
+      HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hadc);
+    
+    return HAL_ERROR;
+  }
+ 
+  /* Get tick */ 
+  tickstart = HAL_GetTick();
+
+  /* Check End of conversion flag */
+  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+          
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  
+  /* Clear regular group conversion flag */
+  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+  
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+  
+  /* Determine whether any further conversion upcoming on group regular       */
+  /* by external trigger, continuous mode or scan sequence on going.          */
+  /* Note: On STM32F7, there is no independent flag of end of sequence.       */
+  /*       The test of scan sequence on going is done either with scan        */
+  /*       sequence disabled or with end of conversion flag set to            */
+  /*       of end of sequence.                                                */
+  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+     (hadc->Init.ContinuousConvMode == DISABLE)            &&
+     (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+  {
+    /* Set ADC state */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
+    
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+    { 
+      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+    }
+  }
+  
+  /* Return ADC state */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for conversion event
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  EventType the ADC event type.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
+  *            @arg ADC_OVR_EVENT: ADC Overrun event.
+  * @param  Timeout Timeout value in millisecond.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check selected event flag */
+  while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+          
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  
+  /* Analog watchdog (level out of window) event */
+  if(EventType == ADC_AWD_EVENT)
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+      
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+  }
+  /* Overrun event */
+  else
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+    /* Set ADC error code to overrun */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+    
+    /* Clear ADC overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  }
+  
+  /* Return ADC state */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Enables the interrupt and starts ADC conversion of regular channels.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+  __IO uint32_t counter = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Enable the ADC peripheral */
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+     Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay for ADC stabilization time */
+    /* Compute number of CPU cycles to wait for */
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
+    {
+      counter--;
+    }
+  }
+  
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to regular group conversion results     */
+    /* - Set state bitfield related to regular group operation                */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+                      HAL_ADC_STATE_REG_BUSY);
+    
+    /* If conversions on group regular are also triggering group injected,    */
+    /* update ADC state.                                                      */
+    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+    {
+      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+    }
+    
+    /* State machine update: Check if an injected conversion is ongoing */
+    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+    {
+      /* Reset ADC error code fields related to conversions on group regular */
+      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+    }
+    else
+    {
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);
+    
+    /* Clear regular group conversion flag and overrun flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+    
+    /* Enable end of conversion interrupt for regular group */
+    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
+    
+    /* Check if Multimode enabled */
+    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+    {
+      /* if no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+      {
+        /* Enable the selected ADC software conversion for regular group */
+        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
+    }
+    else
+    {
+      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+      {
+        /* Enable the selected ADC software conversion for regular group */
+          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
+
+      /* if dual mode is selected, ADC3 works independently. */
+      /* check if the mode selected is not triple */
+      if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
+      {
+        /* if instance of handle correspond to ADC3 and  no external trigger present enable software conversion of regular channels */
+        if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+        {
+          /* Enable the selected ADC software conversion for regular group */
+          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+        }
+      } 
+    }
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    
+    /* Set ADC error code to ADC IP internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables the interrupt and stop ADC conversion of regular channels.
+  * 
+  * @note   Caution: This function will stop also injected channels.  
+  *
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Stop potential conversion on going, on regular and injected groups */
+  /* Disable ADC peripheral */
+  __HAL_ADC_DISABLE(hadc);
+  
+  /* Check if ADC is effectively disabled */
+  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+  	/* Disable ADC end of conversion interrupt for regular group */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
+
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_READY);
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles ADC interrupt request  
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+  uint32_t tmp1 = 0, tmp2 = 0;
+
+  uint32_t tmp_sr = hadc->Instance->SR;
+  uint32_t tmp_cr1 = hadc->Instance->CR1;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
+  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
+
+  tmp1 = tmp_sr & ADC_FLAG_EOC;
+  tmp2 = tmp_cr1 & ADC_IT_EOC;
+
+  /* Check End of conversion flag for regular channels */
+  if(tmp1 && tmp2)
+  {
+    /* Update state machine on conversion status if not in error state */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
+    }
+    
+    /* Determine whether any further conversion upcoming on group regular   */
+    /* by external trigger, continuous mode or scan sequence on going.      */
+    /* Note: On STM32F7, there is no independent flag of end of sequence.   */
+    /*       The test of scan sequence on going is done either with scan    */
+    /*       sequence disabled or with end of conversion flag set to        */
+    /*       of end of sequence.                                            */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+       (hadc->Init.ContinuousConvMode == DISABLE)            &&
+       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+    {
+      /* Disable ADC end of single conversion interrupt on group regular */
+      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
+      /* by overrun IRQ process below.                                      */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+      
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+      
+      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
+    }
+    
+    /* Conversion complete callback */ 
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    
+    /* Clear regular group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+  }
+  
+  tmp1 = tmp_sr & ADC_FLAG_JEOC;
+  tmp2 = tmp_cr1 & ADC_IT_JEOC;
+  /* Check End of conversion flag for injected channels */
+  if(tmp1 && tmp2)
+  {
+    /* Update state machine on conversion status if not in error state */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+    }
+
+    /* Determine whether any further conversion upcoming on group injected  */
+    /* by external trigger, scan sequence on going or by automatic injected */
+    /* conversion from group regular (same conditions as group regular      */
+    /* interruption disabling above).                                       */
+    if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
+       (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
+       (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+       (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+       (hadc->Init.ContinuousConvMode == DISABLE))))
+    {
+      /* Disable ADC end of single conversion interrupt on group injected */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+      
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
+
+      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+      { 
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
+    }
+
+    /* Conversion complete callback */ 
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->InjectedConvCpltCallback(hadc);
+#else
+      HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    
+    /* Clear injected group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
+  }
+  
+  tmp1 = tmp_sr & ADC_FLAG_AWD;
+  tmp2 = tmp_cr1 & ADC_IT_AWD;
+  /* Check Analog watchdog flag */
+  if(tmp1 && tmp2)
+  {
+    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+      
+      /* Level out of window callback */ 
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->LevelOutOfWindowCallback(hadc);
+#else
+      HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+      
+      /* Clear the ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+    }
+  }
+  
+  tmp1 = tmp_sr & ADC_FLAG_OVR;
+  tmp2 = tmp_cr1 & ADC_IT_OVR;
+  /* Check Overrun flag */
+  if(tmp1 && tmp2)
+  {
+    /* Note: On STM32F7, ADC overrun can be set through other parameters    */
+    /*       refer to description of parameter "EOCSelection" for more      */
+    /*       details.                                                       */
+    
+    /* Set ADC error code to overrun */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+    
+    /* Clear ADC overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+    
+    /* Error callback */ 
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    
+    /* Clear the Overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  }
+}
+
+/**
+  * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral  
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from ADC peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+  __IO uint32_t counter = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Enable the ADC peripheral */
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+     Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay for ADC stabilization time */
+    /* Compute number of CPU cycles to wait for */
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
+    {
+      counter--;
+    }
+  }
+  
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to regular group conversion results     */
+    /* - Set state bitfield related to regular group operation                */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+                      HAL_ADC_STATE_REG_BUSY);
+    
+    /* If conversions on group regular are also triggering group injected,    */
+    /* update ADC state.                                                      */
+    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+    {
+      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+    }
+    
+    /* State machine update: Check if an injected conversion is ongoing */
+    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+    {
+      /* Reset ADC error code fields related to conversions on group regular */
+      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+    }
+    else
+    {
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);   
+
+    /* Set the DMA transfer complete callback */
+    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+    /* Set the DMA half transfer complete callback */
+    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+    
+    /* Set the DMA error callback */
+    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+    
+    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
+    /* start (in case of SW start):                                           */
+    
+    /* Clear regular group conversion flag and overrun flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+
+    /* Enable ADC overrun interrupt */
+    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* Enable ADC DMA mode */
+    hadc->Instance->CR2 |= ADC_CR2_DMA;
+    
+    /* Start the DMA channel */
+    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+    
+    /* Check if Multimode enabled */
+    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+    {
+      /* if no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+      {
+        /* Enable the selected ADC software conversion for regular group */
+        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
+    }
+    else
+    {
+      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
+      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+      {
+        /* Enable the selected ADC software conversion for regular group */
+          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+      }
+      /* if dual mode is selected, ADC3 works independently. */
+      /* check if the mode selected is not triple */
+      if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
+      {
+        /* if instance of handle correspond to ADC3 and  no external trigger present enable software conversion of regular channels */
+        if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+        {
+          /* Enable the selected ADC software conversion for regular group */
+          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    
+    /* Set ADC error code to ADC IP internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral    
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Stop potential conversion on going, on regular and injected groups */
+  /* Disable ADC peripheral */
+  __HAL_ADC_DISABLE(hadc);
+  
+  /* Check if ADC is effectively disabled */
+  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Disable the selected ADC DMA mode */
+    hadc->Instance->CR2 &= ~ADC_CR2_DMA;
+    
+    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+    /* DMA transfer is on going)                                              */
+    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+    {
+      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+      
+      /* Check if DMA channel effectively disabled */
+      if (tmp_hal_status != HAL_OK)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+      }
+    }
+    
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_READY);
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Gets the converted value from data register of regular channel.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval Converted value
+  */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{       
+  /* Return the selected ADC converted value */ 
+  return hadc->Instance->DR;
+}
+
+/**
+  * @brief  Regular conversion complete callback in non blocking mode 
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_ConvCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Regular conversion half DMA transfer callback in non blocking mode 
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Analog watchdog callback in non blocking mode 
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error ADC callback.
+  * @note   In case of error due to overrun when using ADC with DMA transfer 
+  *         (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+  *         - If needed, restart a new ADC conversion using function
+  *           "HAL_ADC_Start_DMA()"
+  *           (this function is also clearing overrun flag)
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief   	Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure regular channels. 
+      (+) Configure injected channels.
+      (+) Configure multimode.
+      (+) Configure the analog watch dog.
+      
+@endverbatim
+  * @{
+  */
+
+  /**
+  * @brief  Configures for the selected ADC regular channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  sConfig ADC configuration structure. 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+  __IO uint32_t counter = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+  if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE))
+  {
+    /* Clear the old sample time */
+    hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
+
+    if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+    {
+      /* Set the new sample time */
+      hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
+    }
+    else
+    {
+      /* Set the new sample time */
+      hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
+    }
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Clear the old sample time */
+    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
+    
+    /* Set the new sample time */
+    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
+  }
+  
+  /* For Rank 1 to 6 */
+  if (sConfig->Rank < 7)
+  {
+    /* Clear the old SQx bits for the selected rank */
+    hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
+    
+    /* Set the SQx bits for the selected rank */
+    hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
+  }
+  /* For Rank 7 to 12 */
+  else if (sConfig->Rank < 13)
+  {
+    /* Clear the old SQx bits for the selected rank */
+    hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
+    
+    /* Set the SQx bits for the selected rank */
+    hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
+  }
+  /* For Rank 13 to 16 */
+  else
+  {
+    /* Clear the old SQx bits for the selected rank */
+    hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
+    
+    /* Set the SQx bits for the selected rank */
+    hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
+  }
+  
+  /* if no internal channel selected */
+  if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE))
+  {
+    /* Disable the VBAT & TSVREFE channel*/
+    ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
+  }
+
+  /* if ADC1 Channel_18 is selected enable VBAT Channel */
+  if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
+  {
+    /* Disable the TEMPSENSOR channel as it is multiplixed with the VBAT channel */
+    ADC->CCR &= ~ADC_CCR_TSVREFE;
+
+    /* Enable the VBAT channel*/
+    ADC->CCR |= ADC_CCR_VBATE;
+  }
+  
+  /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
+  if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
+  {
+    /* Disable the VBAT channel as it is multiplixed with TEMPSENSOR channel */
+    ADC->CCR &= ~ADC_CCR_VBATE;
+
+    /* Enable the TSVREFE channel*/
+    ADC->CCR |= ADC_CCR_TSVREFE;
+
+    if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+    {
+      /* Delay for temperature sensor stabilization time */
+      /* Compute number of CPU cycles to wait for */
+      counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+      while(counter != 0)
+      {
+        counter--;
+      }
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the analog watchdog.
+  * @note   Analog watchdog thresholds can be modified while ADC conversion
+  *         is on going.
+  *         In this case, some constraints must be taken into account:
+  *         the programmed threshold values are effective from the next
+  *         ADC EOC (end of unitary conversion).
+  *         Considering that registers write delay may happen due to
+  *         bus activity, this might cause an uncertainty on the
+  *         effective timing of the new programmed threshold values.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  AnalogWDGConfig  pointer to an ADC_AnalogWDGConfTypeDef structure 
+  *         that contains the configuration information of ADC analog watchdog.
+  * @retval HAL status	  
+  */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+#ifdef USE_FULL_ASSERT  
+  uint32_t tmp = 0;
+#endif /* USE_FULL_ASSERT  */  
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
+  assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+
+#ifdef USE_FULL_ASSERT  
+  tmp = ADC_GET_RESOLUTION(hadc);
+  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
+  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
+#endif /* USE_FULL_ASSERT  */
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  if(AnalogWDGConfig->ITMode == ENABLE)
+  {
+    /* Enable the ADC Analog watchdog interrupt */
+    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+  }
+  else
+  {
+    /* Disable the ADC Analog watchdog interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
+  }
+  
+  /* Clear AWDEN, JAWDEN and AWDSGL bits */
+  hadc->Instance->CR1 &=  ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
+  
+  /* Set the analog watchdog enable mode */
+  hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
+  
+  /* Set the high threshold */
+  hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
+  
+  /* Set the low threshold */
+  hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
+  
+  /* Clear the Analog watchdog channel select bits */
+  hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
+  
+  /* Set the Analog watchdog channel */
+  hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
+ *  @brief   ADC Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Peripheral State and errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the ADC state
+      (+) Check the ADC Error
+         
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  return the ADC state
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL state
+  */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+{
+  /* Return ADC state */
+  return hadc->State;
+}
+
+/**
+  * @brief  Return the ADC error code
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval ADC Error Code
+  */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+  return hadc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters 
+  *         in the ADC_InitStruct without initializing the ADC MSP.       
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.  
+  * @retval None
+  */
+static void ADC_Init(ADC_HandleTypeDef* hadc)
+{
+  /* Set ADC parameters */
+  /* Set the ADC clock prescaler */
+  ADC->CCR &= ~(ADC_CCR_ADCPRE);
+  ADC->CCR |=  hadc->Init.ClockPrescaler;
+  
+  /* Set ADC scan mode */
+  hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
+  hadc->Instance->CR1 |=  ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
+  
+  /* Set ADC resolution */
+  hadc->Instance->CR1 &= ~(ADC_CR1_RES);
+  hadc->Instance->CR1 |=  hadc->Init.Resolution;
+  
+  /* Set ADC data alignment */
+  hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
+  hadc->Instance->CR2 |= hadc->Init.DataAlign;
+  
+  /* Enable external trigger if trigger selection is different of software  */
+  /* start.                                                                 */
+  /* Note: This configuration keeps the hardware feature of parameter       */
+  /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+  /*       software start.                                                  */
+  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+  {
+    /* Select external trigger to start conversion */
+    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
+    
+    /* Select external trigger polarity */
+    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
+  }
+  else
+  {
+    /* Reset the external trigger */
+    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+  }
+  
+  /* Enable or disable ADC continuous conversion mode */
+  hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
+  hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
+  
+  if(hadc->Init.DiscontinuousConvMode != DISABLE)
+  {
+    assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
+  
+    /* Enable the selected ADC regular discontinuous mode */
+    hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
+    
+    /* Set the number of channels to be converted in discontinuous mode */
+    hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
+    hadc->Instance->CR1 |=  ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
+  }
+  else
+  {
+    /* Disable the selected ADC regular discontinuous mode */
+    hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
+  }
+  
+  /* Set ADC number of conversion */
+  hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
+  hadc->Instance->SQR1 |=  ADC_SQR1(hadc->Init.NbrOfConversion);
+  
+  /* Enable or disable ADC DMA continuous request */
+  hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
+  hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
+  
+  /* Enable or disable ADC end of conversion selection */
+  hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
+  hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
+}
+
+/**
+  * @brief  DMA transfer complete callback. 
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Update state machine on conversion status if not in error state */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+  {
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+    
+    /* Determine whether any further conversion upcoming on group regular   */
+    /* by external trigger, continuous mode or scan sequence on going.      */
+    /* Note: On STM32F7, there is no independent flag of end of sequence.   */
+    /*       The test of scan sequence on going is done either with scan    */
+    /*       sequence disabled or with end of conversion flag set to        */
+    /*       of end of sequence.                                            */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+       (hadc->Init.ContinuousConvMode == DISABLE)            &&
+       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+    {
+      /* Disable ADC end of single conversion interrupt on group regular */
+      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
+      /* by overrun IRQ process below.                                      */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+      
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
+      
+      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
+    }
+    
+    /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  }
+  else /* DMA and-or internal error occurred */
+  {
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+    {
+      /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Call DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback(hdma);
+    }
+  }
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+   /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ConvHalfCpltCallback(hadc);
+#else
+  HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA error callback 
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_DMAError(DMA_HandleTypeDef *hdma)   
+{
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hadc->State= HAL_ADC_STATE_ERROR_DMA;
+  /* Set ADC error code to DMA error */
+  hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+  /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ErrorCallback(hadc);
+#else
+  HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c
new file mode 100644
index 0000000..669ac29
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c
@@ -0,0 +1,1069 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_adc_ex.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the ADC extension peripheral:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
+       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
+       (##) ADC pins configuration
+             (+++) Enable the clock for the ADC GPIOs using the following function:
+                   __HAL_RCC_GPIOx_CLK_ENABLE()
+             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
+       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
+             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
+             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
+             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
+      (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
+             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
+             (+++) Configure and enable two DMA streams stream for managing data
+                 transfer from peripheral to memory (output stream)
+             (+++) Associate the initialized DMA handle to the ADC DMA handle
+                 using  __HAL_LINKDMA()
+             (+++) Configure the priority and enable the NVIC for the transfer complete
+                 interrupt on the two DMA Streams. The output stream should have higher
+                 priority than the input stream.
+     (#) Configure the ADC Prescaler, conversion resolution and data alignment
+         using the HAL_ADC_Init() function.
+
+     (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
+         and HAL_ADC_ConfigChannel() functions.
+
+     (#) Three operation modes are available within this driver :
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]
+       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
+       (+) Wait for end of conversion using HAL_ADCEx_InjectedPollForConversion(), at this stage
+           user can specify the value of timeout according to his end application
+       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
+       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
+       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
+       (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback 
+       (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
+       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
+
+     *** Multi mode ADCs Regular channels configuration ***
+     ======================================================
+     [..]
+       (+) Select the Multi mode ADC regular channels features (dual or triple mode)
+          and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
+       (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
+           of data to be transferred at each end of conversion
+       (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
+
+
+    @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADCEx ADCEx
+  * @brief ADC Extended driver modules
+  * @{
+  */ 
+
+#ifdef HAL_ADC_MODULE_ENABLED
+    
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/ 
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup ADCEx_Private_Functions
+  * @{
+  */
+/* Private function prototypes -----------------------------------------------*/
+static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
+static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); 
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group1  Extended features functions 
+  *  @brief    Extended features functions  
+  *
+@verbatim   
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of injected channel.
+      (+) Stop conversion of injected channel.
+      (+) Start multimode and enable DMA transfer.
+      (+) Stop multimode and disable DMA transfer.
+      (+) Get result of injected channel conversion.
+      (+) Get result of multimode conversion.
+      (+) Configure injected channels.
+      (+) Configure multimode.
+               
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables the selected ADC software start conversion of the injected channels.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
+{
+  __IO uint32_t counter = 0;
+  uint32_t tmp1 = 0, tmp2 = 0;
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Enable the ADC peripheral */
+  
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+     Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay for ADC stabilization time */
+    /* Compute number of CPU cycles to wait for */
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
+    {
+      counter--;
+    }
+  }
+  
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to injected group conversion results    */
+    /* - Set state bitfield related to injected operation                     */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+                      HAL_ADC_STATE_INJ_BUSY);
+    
+    /* Check if a regular conversion is ongoing */
+    /* Note: On this device, there is no ADC error code fields related to     */
+    /*       conversions on group injected only. In case of conversion on     */
+    /*       going on group regular, no error code is reset.                  */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+    {
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);
+    
+    /* Clear injected group conversion flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+    
+    /* Check if Multimode enabled */
+    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+    {
+      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+      if(tmp1 && tmp2)
+      {
+        /* Enable the selected ADC software conversion for injected group */
+        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+      }
+    }
+    else
+    {
+      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+      if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+      {
+        /* Enable the selected ADC software conversion for injected group */
+        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+      }
+    }
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    
+    /* Set ADC error code to ADC IP internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables the interrupt and starts ADC conversion of injected channels.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  *
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+{
+  __IO uint32_t counter = 0;
+  uint32_t tmp1 = 0, tmp2 = 0;
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Enable the ADC peripheral */
+  
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+     Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay for ADC stabilization time */
+    /* Compute number of CPU cycles to wait for */
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
+    {
+      counter--;
+    }
+  }
+  
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to injected group conversion results    */
+    /* - Set state bitfield related to injected operation                     */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+                      HAL_ADC_STATE_INJ_BUSY);
+    
+    /* Check if a regular conversion is ongoing */
+    /* Note: On this device, there is no ADC error code fields related to     */
+    /*       conversions on group injected only. In case of conversion on     */
+    /*       going on group regular, no error code is reset.                  */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+    {
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);
+    
+    /* Clear injected group conversion flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+    
+    /* Enable end of conversion interrupt for injected channels */
+    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+    
+    /* Check if Multimode enabled */
+    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+    {
+      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+      if(tmp1 && tmp2)
+      {
+        /* Enable the selected ADC software conversion for injected group */
+        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+      }
+    }
+    else
+    {
+      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+      if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+      {
+        /* Enable the selected ADC software conversion for injected group */
+        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+      }
+    }
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    
+    /* Set ADC error code to ADC IP internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop conversion of injected channels. Disable ADC peripheral if
+  *         no regular conversion is on going.
+  * @note   If ADC must be disabled and if conversion is on going on 
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
+  * @param  hadc ADC handle
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+    
+  /* Stop potential conversion and disable ADC peripheral                     */
+  /* Conditioned to:                                                          */
+  /* - No conversion on the other group (regular group) is intended to        */
+  /*   continue (injected and regular groups stop conversion and ADC disable  */
+  /*   are common)                                                            */
+  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
+  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
+     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+  {
+    /* Stop potential conversion on going, on regular and injected groups */
+    /* Disable ADC peripheral */
+    __HAL_ADC_DISABLE(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Poll for injected conversion complete
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  Timeout Timeout value in millisecond.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+
+  /* Get tick */ 
+  tickstart = HAL_GetTick();
+
+  /* Check End of conversion flag */
+  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
+        {
+          hadc->State= HAL_ADC_STATE_TIMEOUT;
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  
+  /* Clear injected group conversion flag */
+  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
+    
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+  
+  /* Determine whether any further conversion upcoming on group injected      */
+  /* by external trigger, continuous mode or scan sequence on going.          */
+  /* Note: On STM32F7, there is no independent flag of end of sequence.       */
+  /*       The test of scan sequence on going is done either with scan        */
+  /*       sequence disabled or with end of conversion flag set to            */
+  /*       of end of sequence.                                                */
+  if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
+     (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
+      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
+     (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+      (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
+      (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
+  {
+    /* Set ADC state */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+    { 
+      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+    }
+  }
+  
+  /* Return ADC state */
+  return HAL_OK;
+}      
+  
+/**
+  * @brief  Stop conversion of injected channels, disable interruption of 
+  *         end-of-conversion. Disable ADC peripheral if no regular conversion
+  *         is on going.
+  * @note   If ADC must be disabled and if conversion is on going on 
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @param  hadc ADC handle
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+    
+  /* Stop potential conversion and disable ADC peripheral                     */
+  /* Conditioned to:                                                          */
+  /* - No conversion on the other group (regular group) is intended to        */
+  /*   continue (injected and regular groups stop conversion and ADC disable  */
+  /*   are common)                                                            */
+  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */ 
+  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
+     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+  {
+    /* Stop potential conversion on going, on regular and injected groups */
+    /* Disable ADC peripheral */
+    __HAL_ADC_DISABLE(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+    {
+      /* Disable ADC end of conversion interrupt for injected channels */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+      
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Gets the converted value from data register of injected channel.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  InjectedRank the ADC injected rank.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
+  *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
+  *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
+  *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
+  * @retval None
+  */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+  
+  /* Clear injected group conversion flag to have similar behaviour as        */
+  /* regular group: reading data register also clears end of conversion flag. */
+  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+  
+  /* Return the selected ADC converted value */ 
+  switch(InjectedRank)
+  {  
+    case ADC_INJECTED_RANK_4:
+    {
+      tmp =  hadc->Instance->JDR4;
+    }  
+    break;
+    case ADC_INJECTED_RANK_3: 
+    {  
+      tmp =  hadc->Instance->JDR3;
+    }  
+    break;
+    case ADC_INJECTED_RANK_2: 
+    {  
+      tmp =  hadc->Instance->JDR2;
+    }
+    break;
+    case ADC_INJECTED_RANK_1:
+    {
+      tmp =  hadc->Instance->JDR1;
+    }
+    break;
+    default:
+    break;  
+  }
+  return tmp;
+}
+
+/**
+  * @brief  Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
+  * 
+  * @note   Caution: This function must be used only with the ADC master.  
+  *
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  pData   Pointer to buffer in which transferred from ADC peripheral to memory will be stored. 
+  * @param  Length  The length of data to be transferred from ADC peripheral to memory.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+  __IO uint32_t counter = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+     Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay for temperature sensor stabilization time */
+    /* Compute number of CPU cycles to wait for */
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
+    {
+      counter--;
+    }
+  }
+  
+  /* Start conversion if ADC is effectively enabled */
+  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Set ADC state                                                          */
+    /* - Clear state bitfield related to regular group conversion results     */
+    /* - Set state bitfield related to regular group operation                */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+                      HAL_ADC_STATE_REG_BUSY);
+    
+    /* If conversions on group regular are also triggering group injected,    */
+    /* update ADC state.                                                      */
+    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+    {
+      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+    }
+    
+    /* State machine update: Check if an injected conversion is ongoing */
+    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+    {
+      /* Reset ADC error code fields related to conversions on group regular */
+      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+    }
+    else
+    {
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+    }
+    
+    /* Process unlocked */
+    /* Unlock before starting ADC conversions: in case of potential           */
+    /* interruption, to let the process to ADC IRQ Handler.                   */
+    __HAL_UNLOCK(hadc);
+    
+    /* Set the DMA transfer complete callback */
+    hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
+    
+    /* Set the DMA half transfer complete callback */
+    hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
+    
+    /* Set the DMA error callback */
+    hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
+    
+    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
+    /* start (in case of SW start):                                           */
+    
+    /* Clear regular group conversion flag and overrun flag */
+    /* (To ensure of no unknown state from potential previous ADC operations) */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+    /* Enable ADC overrun interrupt */
+    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+    
+    if (hadc->Init.DMAContinuousRequests != DISABLE)
+    {
+      /* Enable the selected ADC DMA request after last transfer */
+      ADC->CCR |= ADC_CCR_DDS;
+    }
+    else
+    {
+      /* Disable the selected ADC EOC rising on each regular channel conversion */
+      ADC->CCR &= ~ADC_CCR_DDS;
+    }
+    
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
+    
+    /* if no external trigger present enable software conversion of regular channels */
+    if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+    {
+      /* Enable the selected ADC software conversion for regular group */
+      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+    }
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    
+    /* Set ADC error code to ADC IP internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral    
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Stop potential conversion on going, on regular and injected groups */
+  /* Disable ADC peripheral */
+  __HAL_ADC_DISABLE(hadc);
+  
+  /* Check if ADC is effectively disabled */
+  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+  {
+    /* Disable the selected ADC DMA mode for multimode */
+    ADC->CCR &= ~ADC_CCR_DDS;
+    
+    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+    /* DMA transfer is on going)                                              */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+    
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_READY);
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results 
+  *         data in the selected multi mode.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval The converted data value.
+  */
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* Return the multi mode conversion value */
+  return ADC->CDR;
+}
+
+/**
+  * @brief  Injected conversion complete callback in non blocking mode 
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Configures for the selected ADC injected channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  sConfigInjected ADC configuration structure for injected channel. 
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
+{
+  
+#ifdef USE_FULL_ASSERT  
+  uint32_t tmp = 0;
+#endif /* USE_FULL_ASSERT  */
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
+  assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+  assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
+  assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
+  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+
+#ifdef USE_FULL_ASSERT
+  tmp = ADC_GET_RESOLUTION(hadc);
+  assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
+#endif /* USE_FULL_ASSERT  */
+
+  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+  {
+    assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+  if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
+  {
+    /* Clear the old sample time */
+    hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
+    
+    /* Set the new sample time */
+    hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Clear the old sample time */
+    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
+    
+    /* Set the new sample time */
+    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
+  }
+  
+  /*---------------------------- ADCx JSQR Configuration -----------------*/
+  hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
+  hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
+  
+  /* Rank configuration */
+  
+  /* Clear the old SQx bits for the selected rank */
+  hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
+   
+  /* Set the SQx bits for the selected rank */
+  hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
+
+  /* Enable external trigger if trigger selection is different of software  */
+  /* start.                                                                 */
+  /* Note: This configuration keeps the hardware feature of parameter       */
+  /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+  /*       software start.                                                  */ 
+  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+  {  
+    /* Select external trigger to start conversion */
+    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+    hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
+    
+    /* Select external trigger polarity */
+    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+    hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+  }
+  else
+  {
+    /* Reset the external trigger */
+    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);  
+  }
+  
+  if (sConfigInjected->AutoInjectedConv != DISABLE)
+  {
+    /* Enable the selected ADC automatic injected group conversion */
+    hadc->Instance->CR1 |= ADC_CR1_JAUTO;
+  }
+  else
+  {
+    /* Disable the selected ADC automatic injected group conversion */
+    hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
+  }
+  
+  if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
+  {
+    /* Enable the selected ADC injected discontinuous mode */
+    hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
+  }
+  else
+  {
+    /* Disable the selected ADC injected discontinuous mode */
+    hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
+  }
+  
+  switch(sConfigInjected->InjectedRank)
+  {
+    case 1:
+      /* Set injected channel 1 offset */
+      hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
+      hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
+      break;
+    case 2:
+      /* Set injected channel 2 offset */
+      hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
+      hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
+      break;
+    case 3:
+      /* Set injected channel 3 offset */
+      hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
+      hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
+      break;
+    default:
+      /* Set injected channel 4 offset */
+      hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
+      hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
+      break;
+  }
+  
+  /* if ADC1 Channel_18 is selected enable VBAT Channel */
+  if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
+  {
+    /* Enable the VBAT channel*/
+    ADC->CCR |= ADC_CCR_VBATE;
+  }
+  
+  /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
+  if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
+  {
+    /* Enable the TSVREFE channel*/
+    ADC->CCR |= ADC_CCR_TSVREFE;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the ADC multi-mode 
+  * @param  hadc       pointer to a ADC_HandleTypeDef structure that contains
+  *                     the configuration information for the specified ADC.  
+  * @param  multimode  pointer to an ADC_MultiModeTypeDef structure that contains 
+  *                     the configuration information for  multimode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_MODE(multimode->Mode));
+  assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
+  assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Set ADC mode */
+  ADC->CCR &= ~(ADC_CCR_MULTI);
+  ADC->CCR |= multimode->Mode;
+  
+  /* Set the ADC DMA access mode */
+  ADC->CCR &= ~(ADC_CCR_DMA);
+  ADC->CCR |= multimode->DMAAccessMode;
+  
+  /* Set delay between two sampling phases */
+  ADC->CCR &= ~(ADC_CCR_DELAY);
+  ADC->CCR |= multimode->TwoSamplingDelay;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+  /**
+  * @brief  DMA transfer complete callback. 
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Update state machine on conversion status if not in error state */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+  {
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+    
+    /* Determine whether any further conversion upcoming on group regular   */
+    /* by external trigger, continuous mode or scan sequence on going.      */
+    /* Note: On STM32F7, there is no independent flag of end of sequence.   */
+    /*       The test of scan sequence on going is done either with scan    */
+    /*       sequence disabled or with end of conversion flag set to        */
+    /*       of end of sequence.                                            */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+       (hadc->Init.ContinuousConvMode == DISABLE)            &&
+       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+    {
+      /* Disable ADC end of single conversion interrupt on group regular */
+      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
+      /* by overrun IRQ process below.                                      */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+      
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
+      
+      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
+    }
+    
+    /* Conversion complete callback */
+    HAL_ADC_ConvCpltCallback(hadc);
+  }
+  else
+  {
+    /* Call DMA error callback */
+    hadc->DMA_Handle->XferErrorCallback(hdma);
+  }
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
+{
+    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    /* Conversion complete callback */
+    HAL_ADC_ConvHalfCpltCallback(hadc); 
+}
+
+/**
+  * @brief  DMA error callback 
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)   
+{
+    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    hadc->State= HAL_ADC_STATE_ERROR_DMA;
+    /* Set ADC error code to DMA error */
+    hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+    HAL_ADC_ErrorCallback(hadc); 
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c
new file mode 100644
index 0000000..d89d865
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c
@@ -0,0 +1,529 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the CORTEX:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions 
+  *
+  @verbatim  
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]  
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]     
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M4 exceptions are managed by CMSIS functions.
+   
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+        function according to the following table.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+    (#) please refer to programming manual for details in how to configure priority. 
+      
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 
+         The pending IRQ priority will be managed only by the sub priority.
+   
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest preemption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+ 
+    [..]  
+    *** How to configure Systick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+           
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+    
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+       inside the stm32f7xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+                            
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+   
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      Systick functionalities 
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Sets the priority grouping field (preemption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup The priority grouping bits length. 
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                    1 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                    0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
+  *         The pending IRQ priority will be managed only by the subpriority. 
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Sets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
+  * @param  PreemptPriority The preemption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority 
+  * @param  SubPriority the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.          
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{ 
+  uint32_t prioritygroup = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+  
+  prioritygroup = NVIC_GetPriorityGrouping();
+  
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before. 
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiates a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+   return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Cortex control functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================  
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities. 
+ 
+      
+@endverbatim
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/**
+  * @brief  Disables the MPU
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+  
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL = 0;
+}
+
+/**
+  * @brief  Enables the MPU
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault, 
+  *          NMI, FAULTMASK and privileged access to the default memory 
+  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+  
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+  
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+
+/**
+  * @brief  Enables the MPU Region.
+  * @retval None
+  */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+  /* Set the Region number */
+  MPU->RNR = RegionNumber;
+
+  /* Enable the Region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Disables the MPU Region.
+  * @retval None
+  */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+  /* Set the Region number */
+  MPU->RNR = RegionNumber;
+
+  /* Disable the Region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Initializes and configures the Region and the memory to be protected.
+  * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+  assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+  assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+  assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+  assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+  assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+  assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+  assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+  assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  /* Disable the Region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+
+  /* Apply configuration */
+  MPU->RBAR = MPU_Init->BaseAddress;
+  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+              ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+              ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+              ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+              ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+              ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+              ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+              ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+              ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+}
+#endif /* __MPU_PRESENT */
+
+/**
+  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Gets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
+  * @param   PriorityGroup the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                      1 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                      0 bits for subpriority
+  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Sets Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC 
+  *         and returns the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *          This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clears the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
+  *          This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  This function handles SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c
new file mode 100644
index 0000000..65d9596
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c
@@ -0,0 +1,1312 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  @verbatim     
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Stream
+       (except for internal SRAM/FLASH memories: no initialization is 
+       necessary) please refer to Reference manual for connection between peripherals
+       and DMA requests.
+
+   (#) For a given Stream, program the required configuration through the following parameters:
+       Transfer Direction, Source and Destination data formats, 
+       Circular, Normal or peripheral flow control mode, Stream Priority level, 
+       Source and Destination Increment mode, FIFO mode and its Threshold (if needed), 
+       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+
+   -@-   Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
+         __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 
+              address and destination address and the Length of data to be transferred.
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  
+              case a fixed Timeout can be configured by User depending from his application.
+          (+) Use HAL_DMA_Abort() function to abort the current transfer.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Select Callbacks functions using HAL_DMA_RegisterCallback()
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  
+              Source address and destination address and the Length of data to be transferred. In this 
+              case the DMA interrupt is configured 
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 
+              add his own function by customization of function pointer XferCpltCallback and 
+              XferErrorCallback (i.e a member of DMA handle structure).
+    [..]
+     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
+         detection.
+
+     (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
+
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+           Half-Word data size for the peripheral to access its data register and set Word data size
+           for the Memory to gain in access time. Each two half words will be packed and written in
+           a single access to a Word in the Memory).
+
+     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+           and Destination. In this case the Peripheral Data Size will be applied to both Source
+           and Destination.
+
+     *** DMA HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in DMA HAL driver.
+       
+      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
+      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. 
+
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA DMA
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< DMA interrupt status register */
+  __IO uint32_t Reserved0;
+  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Constants
+ * @{
+ */
+ #define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)5)  /* 5 ms */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */  
+
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to initialize the DMA Stream source
+    and destination addresses, incrementation and data sizes, transfer direction, 
+    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initialize the DMA according to the specified
+  *         parameters in the DMA_InitTypeDef and create the associated handle.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmp = 0U;
+  uint32_t tickstart = HAL_GetTick();
+  DMA_Base_Registers *regs;
+
+  /* Check the DMA peripheral state */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+  assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+  /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+     when FIFO mode is enabled */
+  if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
+  {
+    assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
+    assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+    assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+  }
+  
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+  
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hdma);
+
+  
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);
+  
+  /* Check if the DMA Stream is effectively disabled */
+  while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+    {
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+      
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_TIMEOUT;
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  /* Get the CR register value */
+  tmp = hdma->Instance->CR;
+
+  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+  tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+                      DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+                      DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
+                      DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
+
+  /* Prepare the DMA Stream configuration */
+  tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+          hdma->Init.Mode                | hdma->Init.Priority;
+
+  /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+  {
+    /* Get memory burst and peripheral burst */
+    tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+  }
+  
+  /* Write to DMA Stream CR register */
+  hdma->Instance->CR = tmp;  
+
+  /* Get the FCR register value */
+  tmp = hdma->Instance->FCR;
+
+  /* Clear Direct mode and FIFO threshold bits */
+  tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+
+  /* Prepare the DMA Stream FIFO configuration */
+  tmp |= hdma->Init.FIFOMode;
+
+  /* The FIFO threshold is not used when the FIFO mode is disabled */
+  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+  {
+    /* Get the FIFO threshold */
+    tmp |= hdma->Init.FIFOThreshold;
+    
+    /* Check compatibility between FIFO threshold level and size of the memory burst */
+    /* for INCR4, INCR8, INCR16 bursts */
+    if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+    {
+      if (DMA_CheckFifoParam(hdma) != HAL_OK)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_RESET;
+        
+        return HAL_ERROR; 
+      }
+    }
+  }
+  
+  /* Write to DMA Stream FCR */
+  hdma->Instance->FCR = tmp;
+
+  /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+     DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+  
+  /* Clear all interrupt flags */
+  regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+                                                                                     
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the DMA peripheral 
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+  DMA_Base_Registers *regs;
+
+  /* Check the DMA peripheral state */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the DMA peripheral state */
+  if(hdma->State == HAL_DMA_STATE_BUSY)
+  {
+    /* Return error status */
+    return HAL_BUSY;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+
+  /* Disable the selected DMA Streamx */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Reset DMA Streamx control register */
+  hdma->Instance->CR   = 0U;
+
+  /* Reset DMA Streamx number of data to transfer register */
+  hdma->Instance->NDTR = 0U;
+
+  /* Reset DMA Streamx peripheral address register */
+  hdma->Instance->PAR  = 0U;
+
+  /* Reset DMA Streamx memory 0 address register */
+  hdma->Instance->M0AR = 0U;
+  
+  /* Reset DMA Streamx memory 1 address register */
+  hdma->Instance->M1AR = 0U;
+  
+  /* Reset DMA Streamx FIFO control register */
+  hdma->Instance->FCR  = (uint32_t)0x00000021U;
+  
+  /* Get DMA steam Base Address */  
+  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+  
+  /* Clear all interrupt flags at correct offset within the register */
+  regs->IFCR = 0x3FU << hdma->StreamIndex;
+  
+  /* Clean all callbacks */
+  hdma->XferCpltCallback = NULL;
+  hdma->XferHalfCpltCallback = NULL;
+  hdma->XferM1CpltCallback = NULL;
+  hdma->XferM1HalfCpltCallback = NULL;
+  hdma->XferErrorCallback = NULL;
+  hdma->XferAbortCallback = NULL;  
+
+  /* Reset the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Reset the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  *
+@verbatim   
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and 
+          Start DMA transfer with interrupt
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the DMA Transfer.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  } 
+  return status; 
+}
+
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+ 
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+    
+    /* Clear all interrupt flags at correct offset within the register */
+    regs->IFCR = 0x3FU << hdma->StreamIndex;
+    
+    /* Enable Common interrupts*/
+    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+    hdma->Instance->FCR |= DMA_IT_FE;
+    
+    if(hdma->XferHalfCpltCallback != NULL)
+    {
+      hdma->Instance->CR  |= DMA_IT_HT;
+    }
+    
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);	  
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer.
+  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  *                   
+  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is 
+  *        effectively disabled is added. If a Stream is disabled 
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Stream will be effectively disabled only after the transfer of
+  *        this single data is finished.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  
+  uint32_t tickstart = HAL_GetTick();
+  
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+    hdma->Instance->FCR &= ~(DMA_IT_FE);
+    
+    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+    {
+      hdma->Instance->CR  &= ~(DMA_IT_HT);
+    }
+    
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+    
+    /* Check if the DMA Stream is effectively disabled */
+    while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Clear all interrupt flags at correct offset within the register */
+    regs->IFCR = 0x3FU << hdma->StreamIndex;
+    
+    /* Change the DMA state*/
+    hdma->State = HAL_DMA_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+    
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer in Interrupt mode.
+  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set Abort State  */
+    hdma->State = HAL_DMA_STATE_ABORT;
+    
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hdma          pointer to a DMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified DMA Stream.
+  * @param  CompleteLevel Specifies the DMA level complete.
+  * @note   The polling mode is kept in this version for legacy. it is recommended to use the IT model instead.
+  *         This model could be used for debug purpose.
+  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). 
+  * @param  Timeout       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK; 
+  uint32_t mask_cpltlevel;
+  uint32_t tickstart = HAL_GetTick(); 
+  uint32_t tmpisr;
+  
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs;
+
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* No transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    __HAL_UNLOCK(hdma);
+    return HAL_ERROR;
+  }
+
+  /* Polling mode not supported in circular mode and double buffering mode */
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+  
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Transfer Complete flag */
+    mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+  }
+  else
+  {
+    /* Half Transfer Complete flag */
+    mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+  }
+  
+  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  tmpisr = regs->ISR;
+  
+  while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
+  {
+    /* Check for the Timeout (Not applicable in circular mode)*/
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Get the ISR register value */
+    tmpisr = regs->ISR;
+
+    if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+      
+      /* Clear the transfer error flag */
+      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+    }
+    
+    if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+      
+      /* Clear the FIFO error flag */
+      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+    }
+    
+    if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+      
+      /* Clear the Direct Mode error flag */
+      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+    }
+  }
+  
+  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+  {
+    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+    {
+      HAL_DMA_Abort(hdma);
+    
+      /* Clear the half transfer and transfer complete flags */
+      regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+    
+      /* Change the DMA state */
+      hdma->State= HAL_DMA_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      return HAL_ERROR;
+   }
+  }
+  
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Clear the half transfer and transfer complete flags */
+    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+    
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+  }
+  else
+  {
+    /* Clear the half transfer flag */
+    regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Handles DMA interrupt request.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmpisr;
+  __IO uint32_t count = 0;
+  uint32_t timeout = SystemCoreClock / 9600;
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  tmpisr = regs->ISR;
+
+  /* Transfer Error Interrupt management ***************************************/
+  if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+    {
+      /* Disable the transfer error interrupt */
+      hdma->Instance->CR  &= ~(DMA_IT_TE);
+      
+      /* Clear the transfer error flag */
+      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+      
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+    }
+  }
+  /* FIFO Error Interrupt management ******************************************/
+  if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
+    {
+      /* Clear the FIFO error flag */
+      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+    }
+  }
+  /* Direct Mode Error Interrupt management ***********************************/
+  if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
+    {
+      /* Clear the direct mode error flag */
+      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+    }
+  }
+  /* Half Transfer Complete Interrupt management ******************************/
+  if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+    {
+      /* Clear the half transfer complete flag */
+      regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+      
+      /* Multi_Buffering mode enabled */
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
+        {
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferHalfCpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferM1HalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferM1HalfCpltCallback(hdma);
+          }
+        }
+      }
+      else
+      {
+        /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
+        {
+          /* Disable the half transfer interrupt */
+          hdma->Instance->CR  &= ~(DMA_IT_HT);
+        }
+        
+        if(hdma->XferHalfCpltCallback != NULL)
+        {
+          /* Half transfer callback */
+          hdma->XferHalfCpltCallback(hdma);
+        }
+      }
+    }
+  }
+  /* Transfer Complete Interrupt management ***********************************/
+  if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+    {
+      /* Clear the transfer complete flag */
+      regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+      
+      if(HAL_DMA_STATE_ABORT == hdma->State)
+      {
+        /* Disable all the transfer interrupts */
+        hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+        hdma->Instance->FCR &= ~(DMA_IT_FE);
+        
+        if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+        {
+          hdma->Instance->CR  &= ~(DMA_IT_HT);
+        }
+
+        /* Clear all interrupt flags at correct offset within the register */
+        regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        if(hdma->XferAbortCallback != NULL)
+        {
+          hdma->XferAbortCallback(hdma);
+        }
+        return;
+      }
+
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
+        {
+          if(hdma->XferM1CpltCallback != NULL)
+          {
+            /* Transfer complete Callback for memory1 */
+            hdma->XferM1CpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete Callback for memory0 */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+      else
+      {
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
+        {
+          /* Disable the transfer complete interrupt */
+          hdma->Instance->CR  &= ~(DMA_IT_TC);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+
+        }
+
+        if(hdma->XferCpltCallback != NULL)
+        {
+          /* Transfer complete callback */
+          hdma->XferCpltCallback(hdma);
+        }
+      }
+    }
+  }
+  
+  /* manage error case */
+  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+  {
+    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+    {
+      hdma->State = HAL_DMA_STATE_ABORT;
+
+      /* Disable the stream */
+      __HAL_DMA_DISABLE(hdma);
+
+      do
+      {
+        if (++count > timeout)
+        {
+          break;
+        }
+      }
+      while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+    }
+
+    if(hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID           User Callback identifier
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @param  pCallback            pointer to private callbacsk function which has pointer to 
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @retval HAL status
+  */                      
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID           User Callback identifier
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */              
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = NULL;
+      break; 
+      
+    case   HAL_DMA_XFER_ALL_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      hdma->XferHalfCpltCallback = NULL;
+      hdma->XferM1CpltCallback = NULL;
+      hdma->XferM1HalfCpltCallback = NULL;
+      hdma->XferErrorCallback = NULL;
+      hdma->XferAbortCallback = NULL;
+      break; 
+      
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the DMA state.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA error code
+  * @param  hdma  pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Stream.
+  * @retval DMA Error Code
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+  return hdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the DMA Transfer parameter.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Clear DBM bit */
+  hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
+  /* Configure DMA Stream data length */
+  hdma->Instance->NDTR = DataLength;
+
+  /* Memory to Peripheral */
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {
+    /* Configure DMA Stream destination address */
+    hdma->Instance->PAR = DstAddress;
+
+    /* Configure DMA Stream source address */
+    hdma->Instance->M0AR = SrcAddress;
+  }
+  /* Peripheral to Memory */
+  else
+  {
+    /* Configure DMA Stream source address */
+    hdma->Instance->PAR = SrcAddress;
+
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M0AR = DstAddress;
+  }
+}
+
+/**
+  * @brief  Returns the DMA Stream base address depending on stream number
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream. 
+  * @retval Stream base address
+  */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
+  
+  /* lookup table for necessary bitshift of flags within status registers */
+  static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+  hdma->StreamIndex = flagBitshiftOffset[stream_number];
+  
+  if (stream_number > 3U)
+  {
+    /* return pointer to HISR and HIFCR */
+    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
+  }
+  else
+  {
+    /* return pointer to LISR and LIFCR */
+    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
+  }
+  
+  return hdma->StreamBaseAddress;
+}
+
+/**
+  * @brief  Check compatibility between FIFO threshold level and size of the memory burst
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream. 
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmp = hdma->Init.FIFOThreshold;
+  
+  /* Memory Data size equal to Byte */
+  if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+      if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      break;
+    default:
+      break;
+    }
+  }
+  
+  /* Memory Data size equal to Half-Word */
+  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      status = HAL_ERROR;
+      break;
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+      {
+        status = HAL_ERROR;
+      }
+      break;   
+    default:
+      break;
+    }
+  }
+  
+  /* Memory Data size equal to Word */
+  else
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      status = HAL_ERROR;
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    default:
+      break;
+    }
+  } 
+  
+  return status; 
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c
new file mode 100644
index 0000000..8aadcc4
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c
@@ -0,0 +1,308 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_dma_ex.c
+  * @author  MCD Application Team
+  * @brief   DMA Extension HAL module driver
+  *         This file provides firmware functions to manage the following 
+  *         functionalities of the DMA Extension peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  The DMA Extension HAL driver can be used as follows:
+   (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
+
+     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
+     -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
+     -@-  In Multi (Double) buffer mode, it is possible to update the base address for 
+          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx DMAEx
+  * @brief DMA Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup DMAEx_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup DMAEx_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+                #####  Extended features functions  #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and 
+          Start MultiBuffer DMA transfer
+      (+) Configure the source, destination address and data length and 
+          Start MultiBuffer DMA transfer with interrupt
+      (+) Change on the fly the memory0 or memory1 address.
+      
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+    
+    if(HAL_DMA_STATE_READY == hdma->State)
+    {
+      /* Change DMA peripheral state */
+      hdma->State = HAL_DMA_STATE_BUSY; 
+      
+      /* Enable the double buffer mode */
+      hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+      
+      /* Configure DMA Stream destination address */
+      hdma->Instance->M1AR = SecondMemAddress;
+      
+      /* Configure the source, destination address and the data length */
+      DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+      
+      /* Enable the peripheral */
+      __HAL_DMA_ENABLE(hdma);
+    }
+    else
+    {
+      /* Return error status */
+      status = HAL_BUSY;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Enable the Double buffer mode */
+    hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+    
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M1AR = SecondMemAddress;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
+    
+    /* Clear all flags */
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+    
+    /* Enable Common interrupts*/
+    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+    hdma->Instance->FCR |= DMA_IT_FE;
+    
+    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+    {
+      hdma->Instance->CR  |= DMA_IT_HT;
+    }
+    
+    /* Enable the peripheral */
+    __HAL_DMA_ENABLE(hdma); 
+  }
+  else
+  {     
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);	  
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  }  
+  return status; 
+}
+
+/**
+  * @brief  Change the memory0 or memory1 address on the fly.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  Address    The new address
+  * @param  memory     the memory to be changed, This parameter can be one of 
+  *                     the following values:
+  *                      MEMORY0 /
+  *                      MEMORY1
+  * @note   The MEMORY0 address can be changed only when the current transfer use
+  *         MEMORY1 and the MEMORY1 address can be changed only when the current 
+  *         transfer use MEMORY0.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
+{
+  if(memory == MEMORY0)
+  {
+    /* change the memory0 address */
+    hdma->Instance->M0AR = Address;
+  }
+  else
+  {
+    /* change the memory1 address */
+    hdma->Instance->M1AR = Address;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the DMA Transfer parameter.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Configure DMA Stream data length */
+  hdma->Instance->NDTR = DataLength;
+  
+  /* Peripheral to Memory */
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {
+    /* Configure DMA Stream destination address */
+    hdma->Instance->PAR = DstAddress;
+    
+    /* Configure DMA Stream source address */
+    hdma->Instance->M0AR = SrcAddress;
+  }
+  /* Memory to Peripheral */
+  else
+  {
+    /* Configure DMA Stream source address */
+    hdma->Instance->PAR = SrcAddress;
+    
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M0AR = DstAddress;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c
new file mode 100644
index 0000000..3feffc6
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c
@@ -0,0 +1,547 @@
+/**
+  ******************************************************************************
+  * @file    stm32F7xx_hal_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### EXTI Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each Exti line can be configured within this driver.
+
+    (+) Exti line can be configured in 3 different modes
+        (++) Interrupt
+        (++) Event
+        (++) Both of them
+
+    (+) Configurable Exti lines can be configured with 3 different triggers
+        (++) Rising
+        (++) Falling
+        (++) Both of them
+
+    (+) When set in interrupt mode, configurable Exti lines have two different
+        interrupts pending registers which allow to distinguish which transition
+        occurs:
+        (++) Rising edge pending interrupt
+        (++) Falling
+
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+        be selected through multiplexer.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+        (++) Choose the interrupt line number by setting "Line" member from
+             EXTI_ConfigTypeDef structure.
+        (++) Configure the interrupt and/or event mode using "Mode" member from
+             EXTI_ConfigTypeDef structure.
+        (++) For configurable lines, configure rising and/or falling trigger
+             "Trigger" member from EXTI_ConfigTypeDef structure.
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+             member from GPIO_InitTypeDef structure.
+
+    (#) Get current Exti configuration of a dedicated line using
+        HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
+        (++) Provide exiting handle as parameter.
+
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+        (++) Provide exiting handle as first parameter.
+        (++) Provide which callback will be registered using one value from
+             EXTI_CallbackIDTypeDef.
+        (++) Provide callback function pointer.
+
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
+
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rule:
+  * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+  * of bounds [0,3] in following API :
+  * HAL_EXTI_SetConfigLine
+  * HAL_EXTI_GetConfigLine
+  * HAL_EXTI_ClearConfigLine
+  */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+  *  @brief    Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on EXTI configuration to be set.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+  /* Assign line number to handle */
+  hexti->Line = pExtiConfig->Line;
+
+  /* Compute line mask */
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* Configure triggers for configurable lines */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  {
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+    /* Configure rising trigger */
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
+    {
+      EXTI->RTSR |= maskline;
+    }
+    else
+    {
+      EXTI->RTSR &= ~maskline;
+    }
+
+    /* Configure falling trigger */
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
+    {
+      EXTI->FTSR |= maskline;
+    }
+    else
+    {
+      EXTI->FTSR &= ~maskline;
+    }
+
+
+    /* Configure gpio port selection in case of gpio exti line */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[linepos >> 2u];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      SYSCFG->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  /* Configure interrupt mode : read current mode */
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+  {
+    EXTI->IMR |= maskline;
+  }
+  else
+  {
+    EXTI->IMR &= ~maskline;
+  }
+
+  /* Configure event mode : read current mode */
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+  {
+    EXTI->EMR |= maskline;
+  }
+  else
+  {
+    EXTI->EMR &= ~maskline;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on structure to store Exti configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* Store handle line number to configuration structure */
+  pExtiConfig->Line = hexti->Line;
+
+  /* Compute line mask */
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* 1] Get core mode : interrupt */
+
+  /* Check if selected line is enable */
+  if ((EXTI->IMR & maskline) != 0x00u)
+  {
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+  }
+  else
+  {
+    pExtiConfig->Mode = EXTI_MODE_NONE;
+  }
+
+  /* Get event mode */
+  /* Check if selected line is enable */
+  if ((EXTI->EMR & maskline) != 0x00u)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;
+  }
+
+  /* Get default Trigger and GPIOSel configuration */
+  pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+  pExtiConfig->GPIOSel = 0x00u;
+
+  /* 2] Get trigger for configurable lines : rising */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  {
+    /* Check if configuration of selected line is enable */
+    if ((EXTI->RTSR & maskline) != 0x00u)
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+    }
+
+    /* Get falling configuration */
+    /* Check if configuration of selected line is enable */
+    if ((EXTI->FTSR & maskline) != 0x00u)
+    {
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+    }
+
+    /* Get Gpio port selection for gpio lines */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[linepos >> 2u];
+      pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clear whole configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* compute line mask */
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* 1] Clear interrupt mode */
+  EXTI->IMR = (EXTI->IMR & ~maskline);
+
+  /* 2] Clear event mode */
+  EXTI->EMR = (EXTI->EMR & ~maskline);
+
+  /* 3] Clear triggers in case of configurable lines */
+  if ((hexti->Line & EXTI_CONFIG) != 0x00u)
+  {
+    EXTI->RTSR = (EXTI->RTSR & ~maskline);
+    EXTI->FTSR = (EXTI->FTSR & ~maskline);
+
+    /* Get Gpio port selection for gpio lines */
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[linepos >> 2u];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      SYSCFG->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Register callback for a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  CallbackID User callback identifier.
+  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+  * @param  pPendingCbfn function pointer to be stored as callback.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  switch (CallbackID)
+  {
+    case  HAL_EXTI_COMMON_CB_ID:
+      hexti->PendingCallback = pPendingCbfn;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Store line number as handle private field.
+  * @param  hexti Exti handle.
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Store line number as handle private field */
+    hexti->Line = ExtiLine;
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+  *  @brief EXTI IO functions.
+  *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  hexti Exti handle.
+  * @retval none.
+  */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+  uint32_t regval;
+  uint32_t maskline;
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Get pending bit  */
+  regval = (EXTI->PR & maskline);
+  if (regval != 0x00u)
+  {
+    /* Clear pending bit */
+    EXTI->PR = maskline;
+
+    /* Call callback */
+    if (hexti->PendingCallback != NULL)
+    {
+      hexti->PendingCallback();
+    }
+  }
+}
+
+/**
+  * @brief  Get interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be checked.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval 1 if interrupt is pending else 0.
+  */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* Compute line mask */
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* return 1 if bit is set else 0 */
+  regval = ((EXTI->PR & maskline) >> linepos);
+  return regval;
+}
+
+/**
+  * @brief  Clear interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be clear.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval None.
+  */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  uint32_t maskline;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Clear Pending bit */
+  EXTI->PR =  maskline;
+}
+
+/**
+  * @brief  Generate a software interrupt for a dedicated line.
+  * @param  hexti Exti handle.
+  * @retval None.
+  */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+  uint32_t maskline;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Generate Software interrupt */
+  EXTI->SWIER = maskline;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c
new file mode 100644
index 0000000..d82d629
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c
@@ -0,0 +1,819 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_flash.c
+  * @author  MCD Application Team
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions 
+  *           + Peripheral Errors functions
+  *         
+  @verbatim
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+           
+  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
+       to the Flash memory. It implements the erase and program Flash memory operations 
+       and the read and write protection mechanisms.
+      
+  [..] The Flash memory interface accelerates code execution with a system of instruction
+       prefetch and cache lines. 
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Prefetch on I-Code
+      (+) 64 cache lines of 128 bits on I-Code
+      (+) 8 cache lines of 128 bits on D-Code
+      
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]                             
+      This driver provides functions and macros to configure and program the FLASH 
+      memory of all STM32F7xx devices.
+    
+      (#) FLASH Memory IO Programming functions: 
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+                HAL_FLASH_Lock() functions
+           (++) Program functions: byte, half word, word and double word
+           (++) There Two modes of programming :
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+    
+      (#) Interrupts and flags management functions : 
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Wait for last FLASH operation according to its status
+           (++) Get error flag status by calling HAL_SetErrorCode()          
+    [..] 
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the prefetch buffer
+       (+) Enable/Disable the Instruction cache and the Data cache
+       (+) Reset the Instruction cache and the Data cache
+       (+) Enable/Disable the FLASH interrupts
+       (+) Monitor the FLASH flags status
+    [..]	   
+	(@) For any Flash memory program operation (erase or program), the CPU clock frequency
+        (HCLK) must be at least 1MHz. 
+	(@) The contents of the Flash memory are not guaranteed if a device reset occurs during 
+	    a Flash memory operation.
+    (@) Any attempt to read the Flash memory while it is being written or erased, causes the 
+	    bus to stall. Read operations are processed correctly once the program operation has 
+		completed. This means that code or data fetches cannot be performed while a write/erase 
+		operation is ongoing.
+          
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Constants
+  * @{
+  */
+#define SECTOR_MASK               ((uint32_t)0xFFFFFF07U)
+#define FLASH_TIMEOUT_VALUE       ((uint32_t)50000U)/* 50 s */
+/**
+  * @}
+  */         
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Variables
+  * @{
+  */
+/* Variable used for Erase sectors under interruption */
+FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+/* Program operations */
+static void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void   FLASH_Program_Word(uint32_t Address, uint32_t Data);
+static void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+static void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);
+static void   FLASH_SetErrorCode(void);
+
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+  * @{
+  */
+  
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
+ *  @brief   Programming operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH 
+    program operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Program byte, halfword, word or double word at a specified address
+  * @param  TypeProgram  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address  specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed
+  * 
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  
+  if(status == HAL_OK)
+  {
+    switch(TypeProgram)
+    {
+      case FLASH_TYPEPROGRAM_BYTE :
+      {
+        /*Program byte (8-bit) at a specified address.*/
+        FLASH_Program_Byte(Address, (uint8_t) Data);
+        break;
+      }
+      
+      case FLASH_TYPEPROGRAM_HALFWORD :
+      {
+        /*Program halfword (16-bit) at a specified address.*/
+        FLASH_Program_HalfWord(Address, (uint16_t) Data);
+        break;
+      }
+      
+      case FLASH_TYPEPROGRAM_WORD :
+      {
+        /*Program word (32-bit) at a specified address.*/
+        FLASH_Program_Word(Address, (uint32_t) Data);
+        break;
+      }
+      
+      case FLASH_TYPEPROGRAM_DOUBLEWORD :
+      {
+        /*Program double word (64-bit) at a specified address.*/
+        FLASH_Program_DoubleWord(Address, Data);
+        break;
+      }
+      default :
+        break;
+    }
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+    
+    /* If the program operation is completed, disable the PG Bit */
+    FLASH->CR &= (~FLASH_CR_PG);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.
+  * @param  TypeProgram  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address  specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Enable End of FLASH Operation interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+  
+  /* Enable Error source interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+  
+  /* Clear pending flags (if any) */  
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
+                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);  
+
+  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+  pFlash.Address = Address;
+  
+  switch(TypeProgram)
+  {
+    case FLASH_TYPEPROGRAM_BYTE :
+    {
+      /*Program byte (8-bit) at a specified address.*/
+      FLASH_Program_Byte(Address, (uint8_t) Data);
+      break;
+    }
+    
+    case FLASH_TYPEPROGRAM_HALFWORD :
+    {
+      /*Program halfword (16-bit) at a specified address.*/
+      FLASH_Program_HalfWord(Address, (uint16_t) Data);
+      break;
+    }
+    
+    case FLASH_TYPEPROGRAM_WORD :
+    {
+      /*Program word (32-bit) at a specified address.*/
+      FLASH_Program_Word(Address, (uint32_t) Data);
+      break;
+    }
+    
+    case FLASH_TYPEPROGRAM_DOUBLEWORD :
+    {
+      /*Program double word (64-bit) at a specified address.*/
+      FLASH_Program_DoubleWord(Address, Data);
+      break;
+    }
+    default :
+      break;
+  }
+  return status;
+}
+
+/**
+  * @brief This function handles FLASH interrupt request.
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t temp = 0;
+  
+  /* If the program operation is completed, disable the PG Bit */
+  FLASH->CR &= (~FLASH_CR_PG);
+
+  /* If the erase operation is completed, disable the SER Bit */
+  FLASH->CR &= (~FLASH_CR_SER);
+  FLASH->CR &= SECTOR_MASK; 
+
+  /* if the erase operation is completed, disable the MER Bit */
+  FLASH->CR &= (~FLASH_MER_BIT);
+
+  /* Check FLASH End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+    
+    switch (pFlash.ProcedureOnGoing)
+    {
+      case FLASH_PROC_SECTERASE :
+      {
+        /* Nb of sector to erased can be decreased */
+        pFlash.NbSectorsToErase--;
+
+        /* Check if there are still sectors to erase */
+        if(pFlash.NbSectorsToErase != 0)
+        {
+          temp = pFlash.Sector;
+          /* Indicate user which sector has been erased */
+          HAL_FLASH_EndOfOperationCallback(temp);
+
+          /* Increment sector number */
+          temp = ++pFlash.Sector;
+          FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
+        }
+        else
+        {
+          /* No more sectors to Erase, user callback can be called.*/
+          /* Reset Sector and stop Erase sectors procedure */
+          pFlash.Sector = temp = 0xFFFFFFFFU;
+          /* FLASH EOP interrupt user callback */
+          HAL_FLASH_EndOfOperationCallback(temp);
+          /* Sector Erase procedure is completed */
+          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        }
+        break;
+      }
+    
+      case FLASH_PROC_MASSERASE :
+      {
+        /* MassErase ended. Return the selected bank : in this product we don't have Banks */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(0);
+        /* MAss Erase procedure is completed */
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        break;
+      }
+
+      case FLASH_PROC_PROGRAM :
+      {
+        /*Program ended. Return the selected address*/
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+        /* Programming procedure is completed */
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        break;
+      }
+      default :
+        break;
+    }
+  }
+  
+  /* Check FLASH operation error flags */
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
+  {
+    switch (pFlash.ProcedureOnGoing)
+    {
+      case FLASH_PROC_SECTERASE :
+      {
+        /* return the faulty sector */
+        temp = pFlash.Sector;
+        pFlash.Sector = 0xFFFFFFFFU;
+        break;
+      }
+      case FLASH_PROC_MASSERASE :
+      {
+        /* No return in case of Mass Erase */
+        temp = 0;
+        break;
+      }
+      case FLASH_PROC_PROGRAM :
+      {
+        /*return the faulty address*/
+        temp = pFlash.Address;
+        break;
+      }
+    default :
+      break;
+    }
+    /*Save the Error code*/
+    FLASH_SetErrorCode();
+
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(temp);
+
+    /*Stop the procedure ongoing */
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+  }
+  
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  {
+    /* Disable End of FLASH Operation interrupt */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
+
+    /* Disable Error source interrupt */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that 
+  *                                  all the selected sectors have been erased)
+  *                 - Program      : Address which was selected for data program
+  *                 - Mass Erase   : No return value expected
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+  */ 
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that 
+  *                                  all the selected sectors have been erased)
+  *                 - Program      : Address which was selected for data program
+  *                 - Mass Erase   : No return value expected
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH 
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control register access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+  {
+    /* Authorize the FLASH Registers access */
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+    /* Verify Flash is unlocked */
+    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Locks the FLASH control register access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  FLASH->CR |= FLASH_CR_LOCK;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Unlock the FLASH Option Control Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
+  {
+    /* Authorizes the Option Byte register programming */
+    FLASH->OPTKEYR = FLASH_OPT_KEY1;
+    FLASH->OPTKEYR = FLASH_OPT_KEY2;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }  
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Lock the FLASH Option Control Registers access.
+  * @retval HAL Status 
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  /* Set the OPTSTRT bit in OPTCR register */
+  FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
+
+  /* Wait for last operation to be completed */
+  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions 
+ *  @brief   Peripheral Errors functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @retval FLASH_ErrorCode: The returned value can be:
+  *            @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag 
+  *            @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  
+  *            @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+  *            @arg FLASH_ERROR_WRP: FLASH Write protected error flag
+  *            @arg FLASH_ERROR_OPERATION: FLASH operation Error flag 
+  */
+uint32_t HAL_FLASH_GetError(void)
+{ 
+   return pFlash.ErrorCode;
+}  
+  
+/**
+  * @}
+  */    
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout maximum flash operationtimeout
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{ 
+  uint32_t tickstart = 0;
+  
+  /* Clear Error Code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+  
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) 
+  { 
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        return HAL_TIMEOUT;
+      }
+    } 
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
+  {
+    /*Save the error code*/
+    FLASH_SetErrorCode();
+    return HAL_ERROR;
+  }
+  
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+  }
+
+  /* If there is an error flag set */
+  return HAL_OK;
+  
+}  
+
+/**
+  * @brief  Program a double word (64-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.7V to 3.6V and an External Vpp is present.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  /* Program first word */
+  *(__IO uint32_t*)Address = (uint32_t)Data;
+  /* Barrier to ensure programming is performed in 2 steps, in right order
+    (independently of compiler optimization behavior) */
+  __ISB();
+
+  /* Program second word */
+  *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
+
+  /* Data synchronous Barrier (DSB) Just after the write operation
+     This will force the CPU to respect the sequence of instruction (no optimization).*/
+  __DSB();
+}
+
+
+/**
+  * @brief  Program word (32-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.7V to 3.3V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= FLASH_PSIZE_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint32_t*)Address = Data;
+  
+  /* Data synchronous Barrier (DSB) Just after the write operation
+     This will force the CPU to respect the sequence of instruction (no optimization).*/
+  __DSB();
+}
+
+/**
+  * @brief  Program a half-word (16-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.1V to 3.6V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= FLASH_PSIZE_HALF_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint16_t*)Address = Data;
+
+  /* Data synchronous Barrier (DSB) Just after the write operation
+     This will force the CPU to respect the sequence of instruction (no optimization).*/
+  __DSB();
+  
+}
+
+/**
+  * @brief  Program byte (8-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         1.7V to 3.6V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= FLASH_PSIZE_BYTE;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint8_t*)Address = Data;
+
+  /* Data synchronous Barrier (DSB) Just after the write operation
+     This will force the CPU to respect the sequence of instruction (no optimization).*/
+  __DSB();
+}
+
+/**
+  * @brief  Set the specific FLASH error flag.
+  * @retval None
+  */
+static void FLASH_SetErrorCode(void)
+{
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
+  {
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
+  {
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET)
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;
+  }
+  
+#if defined (FLASH_OPTCR2_PCROP)
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
+  }  
+#endif /* FLASH_OPTCR2_PCROP */
+  
+  /* Clear error programming flags */
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c
new file mode 100644
index 0000000..b10c0d0
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c
@@ -0,0 +1,1119 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_flash_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the FLASH extension peripheral:
+  *           + Extended programming operations functions
+  *  
+  @verbatim
+  ==============================================================================
+                   ##### Flash Extension features #####
+  ==============================================================================
+           
+  [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx 
+       devices contains the following additional features 
+       
+       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+           capability (RWW)
+       (+) Dual bank memory organization       
+       (+) Dual boot mode
+   
+                      ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure and program the FLASH memory 
+       of all STM32F7xx devices. It includes
+      (#) FLASH Memory Erase functions: 
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+                HAL_FLASH_Lock() functions
+           (++) Erase function: Erase sector, erase all sectors
+           (++) There are two modes of erase :
+             (+++) Polling Mode using HAL_FLASHEx_Erase()
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+             
+      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
+           (++) Set/Reset the write protection
+           (++) Set the Read protection Level
+           (++) Set the BOR level
+           (++) Program the user Option Bytes
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASHEx FLASHEx
+  * @brief FLASH HAL Extension module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Constants
+  * @{
+  */    
+#define SECTOR_MASK               0xFFFFFF07U
+#define FLASH_TIMEOUT_VALUE       50000U/* 50 s */
+/**
+  * @}
+  */
+    
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Variables
+  * @{
+  */    
+extern FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Functions
+  * @{
+  */
+/* Option bytes control */
+static HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector);
+static HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector);
+static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);
+static HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);
+static HAL_StatusTypeDef  FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
+static uint32_t           FLASH_OB_GetUser(void);
+static uint32_t           FLASH_OB_GetWRP(void);
+static uint8_t            FLASH_OB_GetRDP(void);
+static uint32_t           FLASH_OB_GetBOR(void);
+static uint32_t           FLASH_OB_GetBootAddress(uint32_t BootOption);
+
+#if defined (FLASH_OPTCR_nDBANK)
+static void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
+static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
+                                              uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot);
+#else
+static void               FLASH_MassErase(uint8_t VoltageRange);
+static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
+#endif /* FLASH_OPTCR_nDBANK */
+
+#if defined (FLASH_OPTCR2_PCROP)
+static HAL_StatusTypeDef  FLASH_OB_PCROP_Config(uint32_t PCROPSector);
+static HAL_StatusTypeDef  FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp);
+static uint32_t           FLASH_OB_GetPCROP(void);
+static uint32_t           FLASH_OB_GetPCROPRDP(void);
+#endif /* FLASH_OPTCR2_PCROP */
+
+extern HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ *  @brief   Extended IO operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Extended programming operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the Extension FLASH 
+    programming operations Operations.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors 
+  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  * 
+  * @param[out]  SectorError pointer to variable  that
+  *         contains the configuration information on faulty sector in case of error 
+  *         (0xFFFFFFFF means that all the sectors have been correctly erased)
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t index = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  {
+    /*Initialization of SectorError variable*/
+    *SectorError = 0xFFFFFFFFU;
+    
+    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /*Mass erase to be done*/
+#if defined (FLASH_OPTCR_nDBANK)      
+      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+#else
+      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);      
+#endif /* FLASH_OPTCR_nDBANK */
+                      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+      
+      /* if the erase operation is completed, disable the MER Bit */
+      FLASH->CR &= (~FLASH_MER_BIT);
+    }
+    else
+    {
+      /* Check the parameters */
+      assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+
+      /* Erase by sector by sector to be done*/
+      for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
+      {
+        FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+        
+        /* If the erase operation is completed, disable the SER Bit and SNB Bits */
+        CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); 
+
+        if(status != HAL_OK) 
+        {
+          /* In case of error, stop erase procedure and return the faulty sector*/
+          *SectorError = index;
+          break;
+        }
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled
+  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  /* Enable End of FLASH Operation interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+  
+  /* Enable Error source interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+  
+  /* Clear pending flags (if any) */  
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
+                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);  
+  
+  if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+  {
+    /*Mass erase to be done*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+#if defined (FLASH_OPTCR_nDBANK)    
+    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+#else
+    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);      
+#endif /* FLASH_OPTCR_nDBANK */    
+  }
+  else
+  {
+    /* Erase by sector to be done*/
+
+    /* Check the parameters */
+    assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+
+    pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
+    pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+    pFlash.Sector = pEraseInit->Sector;
+    pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
+
+    /*Erase 1st sector and wait for IT*/
+    FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Program option bytes
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+  /* Write protection configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+  {
+    assert_param(IS_WRPSTATE(pOBInit->WRPState));
+    if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+    {
+      /*Enable of Write protection on the selected Sector*/
+      status = FLASH_OB_EnableWRP(pOBInit->WRPSector);
+    }
+    else
+    {
+      /*Disable of Write protection on the selected Sector*/
+      status = FLASH_OB_DisableWRP(pOBInit->WRPSector);
+    }
+  }
+
+  /* Read protection configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+  {
+    status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
+  }
+
+  /* USER  configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+  {
+#if defined (FLASH_OPTCR_nDBANK)
+    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, 
+                                 pOBInit->USERConfig & OB_IWDG_SW,
+                                 pOBInit->USERConfig & OB_STOP_NO_RST,
+                                 pOBInit->USERConfig & OB_STDBY_NO_RST, 
+                                 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
+                                 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,
+                                 pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,
+                                 pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);
+#else
+    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, 
+                                 pOBInit->USERConfig & OB_IWDG_SW,
+                                 pOBInit->USERConfig & OB_STOP_NO_RST,
+                                 pOBInit->USERConfig & OB_STDBY_NO_RST, 
+                                 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
+                                 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);    
+#endif /* FLASH_OPTCR_nDBANK */
+  }
+  
+  /* BOR Level  configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
+  {
+    status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
+  }
+  
+  /* Boot 0 Address configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)
+  {
+    status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);
+  }
+  
+  /* Boot 1 Address configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)
+  {
+    status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);
+  }
+  
+#if defined (FLASH_OPTCR2_PCROP)
+  /* PCROP configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
+  {
+    status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector);
+  }
+  
+  /* PCROP_RDP configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP)
+  {
+    status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp);
+  }
+#endif /* FLASH_OPTCR2_PCROP */
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Get the Option byte configuration
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  * 
+  * @retval None
+  */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
+	                OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
+
+  /*Get WRP*/
+  pOBInit->WRPSector = FLASH_OB_GetWRP();
+
+  /*Get RDP Level*/
+  pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+  /*Get USER*/
+  pOBInit->USERConfig = FLASH_OB_GetUser();
+
+  /*Get BOR Level*/
+  pOBInit->BORLevel = FLASH_OB_GetBOR();
+  
+  /*Get Boot Address when Boot pin = 0 */
+  pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
+  
+  /*Get Boot Address when Boot pin = 1 */
+  pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
+
+#if defined (FLASH_OPTCR2_PCROP)
+  /*Get PCROP Sectors */
+  pOBInit->PCROPSector = FLASH_OB_GetPCROP();
+  
+  /*Get PCROP_RDP Value */
+  pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP();
+#endif /* FLASH_OPTCR2_PCROP */
+}
+/**
+  * @}
+  */
+
+#if defined (FLASH_OPTCR_nDBANK)
+/**
+  * @brief  Full erase of FLASH memory sectors 
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
+  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  *
+  * @retval HAL Status
+  */
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* if the previous operation is completed, proceed to erase all sectors */
+  FLASH->CR &= CR_PSIZE_MASK;
+  if(Banks == FLASH_BANK_BOTH)
+  {
+    /* bank1 & bank2 will be erased*/
+    FLASH->CR |= FLASH_MER_BIT;
+  }
+  else if(Banks == FLASH_BANK_2)
+  {
+    /*Only bank2 will be erased*/
+    FLASH->CR |= FLASH_CR_MER2;
+  }
+  else
+  {
+    /*Only bank1 will be erased*/
+    FLASH->CR |= FLASH_CR_MER1;    
+  }
+  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
+  /* Data synchronous Barrier (DSB) Just after the write operation
+     This will force the CPU to respect the sequence of instruction (no optimization).*/
+  __DSB();
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector FLASH sector to erase
+  *         The value of this parameter depend on device used within the same series      
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
+  * 
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+{
+  uint32_t tmp_psize = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  
+  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
+  {
+     tmp_psize = FLASH_PSIZE_BYTE;
+  }
+  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
+  {
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
+  }
+  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
+  {
+    tmp_psize = FLASH_PSIZE_WORD;
+  }
+  else
+  {
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+  }
+  
+  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
+  if(Sector > FLASH_SECTOR_11) 
+  {
+    Sector += 4;
+  }  
+
+  /* If the previous operation is completed, proceed to erase the sector */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= tmp_psize;
+  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
+  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+  FLASH->CR |= FLASH_CR_STRT;
+  
+  /* Data synchronous Barrier (DSB) Just after the write operation
+     This will force the CPU to respect the sequence of instruction (no optimization).*/
+  __DSB();
+}
+
+/**
+  * @brief  Return the FLASH Write Protection Option Bytes value.
+  * @retval uint32_t FLASH Write Protection Option Bytes value
+  */
+static uint32_t FLASH_OB_GetWRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));
+}
+
+/**
+  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    
+  * @param  Wwdg Selects the IWDG mode
+  *          This parameter can be one of the following values:
+  *            @arg OB_WWDG_SW: Software WWDG selected
+  *            @arg OB_WWDG_HW: Hardware WWDG selected
+  * @param  Iwdg Selects the WWDG mode
+  *          This parameter can be one of the following values:
+  *            @arg OB_IWDG_SW: Software IWDG selected
+  *            @arg OB_IWDG_HW: Hardware IWDG selected
+  * @param  Stop Reset event when entering STOP mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
+  *            @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  Stdby Reset event when entering Standby mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
+  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @param  Iwdgstop Independent watchdog counter freeze in Stop mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
+  *            @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
+  * @param  Iwdgstdby Independent watchdog counter freeze in standby mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
+  *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
+  * @param  NDBank Flash Single Bank mode enabled.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)
+  *            @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode)  
+  * @param  NDBoot Flash Dual boot mode disable.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot
+  *            @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot
+
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
+                                             uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)
+{
+  uint32_t useroptionmask = 0x00;
+  uint32_t useroptionvalue = 0x00;
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WWDG_SOURCE(Wwdg));
+  assert_param(IS_OB_IWDG_SOURCE(Iwdg));
+  assert_param(IS_OB_STOP_SOURCE(Stop));
+  assert_param(IS_OB_STDBY_SOURCE(Stdby));
+  assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
+  assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
+  assert_param(IS_OB_NDBANK(NDBank));
+  assert_param(IS_OB_NDBOOT(NDBoot));
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  
+  if(status == HAL_OK)
+  {
+    useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
+                      FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \
+                      FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);
+                      
+    useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);
+        
+    /* Update User Option Byte */               
+    MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
+  }
+  
+  return status; 
+}
+
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), 
+  *         nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
+  */
+static uint32_t FLASH_OB_GetUser(void)
+{
+  /* Return the User Option Byte */
+  return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));
+}
+#else
+
+/**
+  * @brief  Full erase of FLASH memory sectors 
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
+  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
+  *
+  * @retval HAL Status
+  */
+static void FLASH_MassErase(uint8_t VoltageRange)
+{
+  /* Check the parameters */
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+
+  /* if the previous operation is completed, proceed to erase all sectors */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= FLASH_CR_MER;
+  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
+  /* Data synchronous Barrier (DSB) Just after the write operation
+     This will force the CPU to respect the sequence of instruction (no optimization).*/
+  __DSB();
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector FLASH sector to erase
+  *         The value of this parameter depend on device used within the same series      
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
+  * 
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+{
+  uint32_t tmp_psize = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  
+  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
+  {
+     tmp_psize = FLASH_PSIZE_BYTE;
+  }
+  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
+  {
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
+  }
+  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
+  {
+    tmp_psize = FLASH_PSIZE_WORD;
+  }
+  else
+  {
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+  }
+
+  /* If the previous operation is completed, proceed to erase the sector */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= tmp_psize;
+  FLASH->CR &= SECTOR_MASK;
+  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+  FLASH->CR |= FLASH_CR_STRT;
+  
+  /* Data synchronous Barrier (DSB) Just after the write operation
+     This will force the CPU to respect the sequence of instruction (no optimization).*/
+  __DSB();
+}
+
+/**
+  * @brief  Return the FLASH Write Protection Option Bytes value.
+  * @retval uint32_t FLASH Write Protection Option Bytes value
+  */
+static uint32_t FLASH_OB_GetWRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
+}
+
+/**
+  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    
+  * @param  Wwdg Selects the IWDG mode
+  *          This parameter can be one of the following values:
+  *            @arg OB_WWDG_SW: Software WWDG selected
+  *            @arg OB_WWDG_HW: Hardware WWDG selected
+  * @param  Iwdg Selects the WWDG mode
+  *          This parameter can be one of the following values:
+  *            @arg OB_IWDG_SW: Software IWDG selected
+  *            @arg OB_IWDG_HW: Hardware IWDG selected
+  * @param  Stop Reset event when entering STOP mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
+  *            @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  Stdby Reset event when entering Standby mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
+  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @param  Iwdgstop Independent watchdog counter freeze in Stop mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
+  *            @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
+  * @param  Iwdgstdby Independent watchdog counter freeze in standby mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
+  *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY           
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)
+{
+  uint32_t useroptionmask = 0x00;
+  uint32_t useroptionvalue = 0x00;
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WWDG_SOURCE(Wwdg));
+  assert_param(IS_OB_IWDG_SOURCE(Iwdg));
+  assert_param(IS_OB_STOP_SOURCE(Stop));
+  assert_param(IS_OB_STDBY_SOURCE(Stdby));
+  assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
+  assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  
+  if(status == HAL_OK)
+  {
+    useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
+                      FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);
+                      
+    useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);
+        
+    /* Update User Option Byte */               
+    MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
+  }
+  
+  return status; 
+
+}
+
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), 
+  *         nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
+  */
+static uint32_t FLASH_OB_GetUser(void)
+{
+  /* Return the User Option Byte */
+  return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U));
+}
+#endif /* FLASH_OPTCR_nDBANK */
+
+/**
+  * @brief  Enable the write protection of the desired bank1 or bank2 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1), 
+  *         it is not possible to program or erase the flash sector i if CortexM7  
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1    
+  * 
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
+  *              or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
+  *              or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
+  *            @arg OB_WRP_SECTOR_All
+  *
+  * @retval HAL FLASH State   
+  */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  {
+    /*Write protection enabled on sectors */
+    FLASH->OPTCR &= (~WRPSector);  
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1), 
+  *         it is not possible to program or erase the flash sector i if CortexM4  
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1  
+  * 
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
+  *              or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
+  *              or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)                      
+  *            @arg OB_WRP_Sector_All
+  *
+  *
+  * @retval HAL Status   
+  */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  {
+    /* Write protection disabled on sectors */
+    FLASH->OPTCR |= (WRPSector); 
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set the read protection level.
+  * @param  Level specifies the read protection level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  *   
+  * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+  *    
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_RDP_LEVEL(Level));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Set the BOR Level. 
+  * @param  Level specifies the Option Bytes BOR Reset Level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOR_LEVEL(Level));
+
+  /* Set the BOR Level */
+  MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);
+  
+  return HAL_OK;
+  
+}
+
+/**
+  * @brief  Configure Boot base address.
+  * 
+  * @param   BootOption  specifies Boot base address depending from Boot pin = 0 or pin = 1
+  *          This parameter can be one of the following values:
+  *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0                 
+  *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1  
+  * @param   Address specifies Boot base address
+  *          This parameter can be one of the following values:
+  *            @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)                 
+  *            @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) 
+  *            @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)  
+  *            @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)  
+  *            @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)                 
+  *            @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)                    
+  *            @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)              
+  *    
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT_ADDRESS(Address));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  
+  if(status == HAL_OK)
+  {
+    if(BootOption == OPTIONBYTE_BOOTADDR_0)
+    {			
+      MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
+    }
+    else
+    {
+      MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
+    }
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Returns the FLASH Read Protection level.
+  * @retval FlagStatus FLASH ReadOut Protection Status:
+  *         This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  */
+static uint8_t FLASH_OB_GetRDP(void)
+{
+  uint8_t readstatus = OB_RDP_LEVEL_0;
+  
+  if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)
+  {
+    readstatus = OB_RDP_LEVEL_0;
+  }
+  else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)
+  {
+    readstatus = OB_RDP_LEVEL_2;
+  }
+  else 
+  {
+    readstatus = OB_RDP_LEVEL_1;
+  }
+
+  return readstatus;
+}
+
+/**
+  * @brief  Returns the FLASH BOR level.
+  * @retval uint32_t The FLASH BOR level:
+  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V  
+  */
+static uint32_t FLASH_OB_GetBOR(void)
+{
+  /* Return the FLASH BOR level */
+  return ((uint32_t)(FLASH->OPTCR & 0x0C));
+}
+
+/**
+  * @brief  Configure Boot base address.
+  * 
+  * @param   BootOption  specifies Boot base address depending from Boot pin = 0 or pin = 1
+  *          This parameter can be one of the following values:
+  *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0                 
+  *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1       
+  *    
+  * @retval uint32_t Boot Base Address:
+  *            - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)                 
+  *            - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) 
+  *            - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)  
+  *            - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)  
+  *            - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)                 
+  *            - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)                    
+  *            - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) 
+  */
+static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)
+{  
+  uint32_t Address = 0;
+    
+	/* Return the Boot base Address */
+  if(BootOption == OPTIONBYTE_BOOTADDR_0)
+  {			
+    Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;
+	}
+  else
+	{
+		Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);
+	}
+
+  return Address;
+}
+
+#if defined (FLASH_OPTCR2_PCROP)
+/**
+  * @brief  Set the PCROP protection for sectors.
+  * @param  PCROPSector specifies the sector(s) to be PCROP protected.
+  *         This parameter can be one of the following values:
+  *            @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7
+  *            @arg OB_PCROP_SECTOR_ALL
+  *    
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_PCROP_SECTOR(PCROPSector));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP, PCROPSector);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Set the PCROP_RDP value
+  * @param  Pcrop_Rdp specifies the PCROP_RDP bit value.
+  *    
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_PCROP_RDP_VALUE(Pcrop_Rdp));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP_RDP, Pcrop_Rdp);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Return the FLASH PCROP Protection Option Bytes value.
+  * @retval uint32_t FLASH PCROP Protection Option Bytes value
+  */
+static uint32_t FLASH_OB_GetPCROP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP));
+}
+
+/**
+  * @brief  Return the FLASH PCROP_RDP option byte value.
+  * @retval uint32_t FLASH PCROP_RDP option byte value
+  */
+static uint32_t FLASH_OB_GetPCROPRDP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP_RDP));
+}
+#endif /* FLASH_OPTCR2_PCROP */
+
+/**
+  * @}
+  */
+  
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c
new file mode 100644
index 0000000..93738b9
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c
@@ -0,0 +1,528 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+  in several modes:
+  (+) Input mode
+  (+) Analog mode
+  (+) Output mode
+  (+) Alternate function mode
+  (+) External interrupt/event lines
+
+  [..]
+  During and just after reset, the alternate functions and external interrupt
+  lines are not active and the I/O ports are configured in input floating mode.
+
+  [..]
+  All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+  activated or not.
+
+  [..]
+  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+  type and the IO speed can be selected depending on the VDD value.
+
+  [..]
+  All ports have external interrupt/event capability. To use external interrupt
+  lines, the port must be configured in input mode. All available GPIO pins are
+  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+  [..]
+  The external interrupt/event controller consists of up to 23 edge detectors
+  (16 lines are connected to GPIO) for generating event/interrupt requests (each
+  input line can be independently configured to select the type (interrupt or event)
+  and the corresponding trigger event (rising or falling or both). Each line can
+  also be masked independently.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from
+             GPIO_InitTypeDef structure select the type (interrupt or event) and
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+    (#) To set/reset the level of a pin configured in output mode use
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+
+    (#) During and just after reset, the alternate functions are not
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+        priority over the GPIO function.
+
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+        The HSE has priority over the GPIO function.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+#define GPIO_NUMBER           ((uint32_t)16U)
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+  [..]
+    This section provides functions allowing to initialize and de-initialize the GPIOs
+    to be ready for use.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position = 0x00;
+  uint32_t ioposition = 0x00;
+  uint32_t iocurrent = 0x00;
+  uint32_t temp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+  /* Configure the port pins */
+  for (position = 0; position < GPIO_NUMBER; position++)
+  {
+    /* Get the IO position */
+    ioposition = ((uint32_t)0x01) << position;
+    /* Get the current IO position */
+    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+
+    if (iocurrent == ioposition)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+        temp |= (GPIO_Init->Speed << (position * 2));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+        GPIOx->OTYPER = temp;
+      }
+
+      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+      {
+        /* Check the Pull parameter */
+        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+        /* Activate the Pull-up or Pull down resistor for the current IO */
+        temp = GPIOx->PUPDR;
+        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+        temp |= ((GPIO_Init->Pull) << (position * 2));
+        GPIOx->PUPDR = temp;
+      }
+
+      /* In case of Alternate function mode selection */
+      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+      {
+        /* Check the Alternate function parameter */
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3];
+        temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+        GPIOx->AFR[position >> 3] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+      GPIOx->MODER = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+        temp = SYSCFG->EXTICR[position >> 2];
+        temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+        SYSCFG->EXTICR[position >> 2] = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR;
+        temp &= ~((uint32_t)iocurrent);
+        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR = temp;
+
+        temp = EXTI->FTSR;
+        temp &= ~((uint32_t)iocurrent);
+        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR = temp;
+
+        temp = EXTI->EMR;
+        temp &= ~((uint32_t)iocurrent);
+        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->EMR = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR;
+        temp &= ~((uint32_t)iocurrent);
+        if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->IMR = temp;
+      }
+    }
+  }
+}
+
+/**
+  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position;
+  uint32_t ioposition = 0x00;
+  uint32_t iocurrent = 0x00;
+  uint32_t tmp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+  /* Configure the port pins */
+  for (position = 0; position < GPIO_NUMBER; position++)
+  {
+    /* Get the IO position */
+    ioposition = ((uint32_t)0x01) << position;
+    /* Get the current IO position */
+    iocurrent = (GPIO_Pin) & ioposition;
+
+    if (iocurrent == ioposition)
+    {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      tmp = SYSCFG->EXTICR[position >> 2];
+      tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+      if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
+      {
+        /* Clear EXTI line configuration */
+        EXTI->IMR &= ~((uint32_t)iocurrent);
+        EXTI->EMR &= ~((uint32_t)iocurrent);
+
+        /* Clear Rising Falling edge configuration */
+        EXTI->FTSR &= ~((uint32_t)iocurrent);
+        EXTI->RTSR &= ~((uint32_t)iocurrent);
+
+        /* Configure the External Interrupt or event for the current IO */
+        tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+        SYSCFG->EXTICR[position >> 2] &= ~tmp;
+      }
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO Direction in Input Floating Mode */
+      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ *  @brief   GPIO Read and Write
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin specifies the port bit to read.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @param  PinState specifies the value to be written to the selected bit.
+  *          This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
+  }
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins.
+  * @param  GPIOx Where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin Specifies the pins to be toggled.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  uint32_t odr;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* get current Output Data Register value */
+  odr = GPIOx->ODR;
+
+  /* Set selected pins that were at low level, and reset ones that were high */
+  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family
+  * @param  GPIO_Pin specifies the port bit to be locked.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKR register. This read is mandatory to complete key lock sequence */
+  tmp = GPIOx->LCKR;
+
+  /* Read again in order to confirm lock is active */
+  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  This function handles EXTI interrupt request.
+  * @param  GPIO_Pin Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+  /* EXTI line interrupt detected */
+  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+}
+
+/**
+  * @brief  EXTI line detection callbacks.
+  * @param  GPIO_Pin Specifies the pins connected EXTI line
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c
new file mode 100644
index 0000000..4e4fbbf
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c
@@ -0,0 +1,7569 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_i2c.c
+  * @author  MCD Application Team
+  * @brief   I2C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The I2C HAL driver can be used as follows:
+
+    (#) Declare a I2C_HandleTypeDef handle structure, for example:
+        I2C_HandleTypeDef  hi2c;
+
+    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+        (##) Enable the I2Cx interface clock
+        (##) I2C pins configuration
+            (+++) Enable the clock for the I2C GPIOs
+            (+++) Configure I2C pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the I2Cx interrupt priority
+            (+++) Enable the NVIC I2C IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare a DMA_HandleTypeDef handle structure for
+                  the transmit or receive stream
+            (+++) Enable the DMAx interface clock using
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Tx or Rx stream
+            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA Tx or Rx stream
+
+    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+
+    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+    *** Polling mode IO MEM operation ***
+    =====================================
+    [..]
+      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+
+    *** Interrupt mode or DMA mode IO sequential operation ***
+    ==========================================================
+    [..]
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+          when a direction change during transfer
+    [..]
+      (+) A specific option field manage the different steps of a sequential transfer
+      (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
+           no sequential mode
+      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
+                            start condition, address and data to transfer without a final stop condition,
+                            an then permit a call the same master sequential interface several times
+                            (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
+                            or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
+      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to
+                            transfer
+                            if no direction change and without a final stop condition in both cases
+      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to
+                            transfer
+                            if no direction change and with a final stop condition in both cases
+      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
+                            after several call of the same master sequential interface several times
+                            (link with option I2C_FIRST_AND_NEXT_FRAME).
+                            Usage can, transfer several bytes one by one using
+                              HAL_I2C_Master_Seq_Transmit_IT
+                              or HAL_I2C_Master_Seq_Receive_IT
+                              or HAL_I2C_Master_Seq_Transmit_DMA
+                              or HAL_I2C_Master_Seq_Receive_DMA
+                              with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
+                             Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
+                              Receive sequence permit to call the opposite interface Receive or Transmit
+                              without stopping the communication and so generate a restart condition.
+      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
+                            each call of the same master sequential
+                            interface.
+                            Usage can, transfer several bytes one by one with a restart with slave address between
+                            each bytes using
+                              HAL_I2C_Master_Seq_Transmit_IT
+                              or HAL_I2C_Master_Seq_Receive_IT
+                              or HAL_I2C_Master_Seq_Transmit_DMA
+                              or HAL_I2C_Master_Seq_Receive_DMA
+                              with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
+                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
+                            generation of STOP condition.
+
+      (+) Different sequential I2C interfaces are listed below:
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
+            users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
+            HAL_I2C_DisableListen_IT()
+      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
+           add their own code to check the Address Match Code and the transmission direction request by master
+           (Write/Read).
+      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
+          add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
+            users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** Interrupt mode IO MEM operation ***
+    =======================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+          HAL_I2C_Mem_Write_IT()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+          HAL_I2C_Mem_Read_IT()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    ==============================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** DMA mode IO MEM operation ***
+    =================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+          HAL_I2C_Mem_Write_DMA()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+          HAL_I2C_Mem_Read_DMA()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+
+     *** I2C HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in I2C HAL driver.
+
+      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+     *** Callback registration ***
+     =============================================
+    [..]
+     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
+     to register an interrupt callback.
+    [..]
+     Function HAL_I2C_RegisterCallback() allows to register following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+     For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
+    [..]
+     Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
+     weak function.
+     HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+    [..]
+     For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
+    [..]
+     By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+    [..]
+     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
+     or HAL_I2C_Init() function.
+    [..]
+     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+     [..]
+       (@) You can refer to the I2C HAL driver header file for more useful macros
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2C I2C
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+  * @{
+  */
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
+#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE      255U
+#define SLAVE_ADDR_SHIFT     7U
+#define SLAVE_ADDR_MSK       0x06U
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
+                                                         (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
+                                              (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
+/*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))
+/*!< Default Value */
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /*!< Bit field can be combinated with
+                                                         @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /*!< Bit field can be combinated with
+                                                         @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
+                                                         and @ref I2C_XFER_RX_IT */
+
+#define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /*!< Bit definition to manage addition of global Error
+                                                         and NACK treatment */
+#define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /*!< Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /*!< Bit definition to manage only Reload of NBYTE */
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Macro
+  * @{
+  */
+/* Macro to get remaining data to transfer on DMA side */
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)     __HAL_DMA_GET_COUNTER(__HANDLE__)
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                                uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                               uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                               uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                        uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                          uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                            uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                         uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+                                                    uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                             uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Private function to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private function to handle  start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+                               uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the I2Cx peripheral:
+
+      (+) User must Implement HAL_I2C_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_I2C_Init() to configure the selected device with
+          the selected configuration:
+        (++) Clock Timing
+        (++) Own Address 1
+        (++) Addressing mode (Master, Slave)
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) Own Address 2 Mask
+        (++) General call mode
+        (++) Nostretch mode
+
+      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+          of the selected I2Cx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I2C according to the specified parameters
+  *         in the I2C_InitTypeDef and initialize the associated handle.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+  if (hi2c->State == HAL_I2C_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    /* Init the I2C Callback settings */
+    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
+    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
+    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
+    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
+    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
+    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
+
+    if (hi2c->MspInitCallback == NULL)
+    {
+      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    hi2c->MspInitCallback(hi2c);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+  /* Configure I2Cx: Frequency range */
+  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Disable Own Address1 before set the Own Address1 configuration */
+  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+  /* Configure I2Cx: Own Address1 and ack own address1 mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+  }
+  else /* I2C_ADDRESSINGMODE_10BIT */
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+  }
+
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+  /* Configure I2Cx: Addressing Master mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+  {
+    SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+  }
+  else
+  {
+    /* Clear the I2C ADD10 bit */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+  }
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+  /* Disable Own Address2 before set the Own Address2 configuration */
+  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
+  /* Configure I2Cx: Dual mode and Own Address2 */
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
+                          (hi2c->Init.OwnAddress2Masks << 8));
+
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+  /* Configure I2Cx: Generalcall and NoStretch mode */
+  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+  /* Enable the selected I2C peripheral */
+  __HAL_I2C_ENABLE(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the I2C peripheral.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the I2C Peripheral Clock */
+  __HAL_I2C_DISABLE(hi2c);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  if (hi2c->MspDeInitCallback == NULL)
+  {
+    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  hi2c->MspDeInitCallback(hi2c);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_RESET;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User I2C Callback
+  *         To be used instead of the weak predefined callback
+  * @note   The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+  *         to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+                                           pI2C_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = pCallback;
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an I2C Callback
+  *         I2C callback is redirected to the weak predefined callback
+  * @note   The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+  *         to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register the Slave Address Match I2C Callback
+  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pCallback pointer to the Address Match Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Slave Address Match I2C Callback
+  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2C data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2C_Master_Transmit()
+        (++) HAL_I2C_Master_Receive()
+        (++) HAL_I2C_Slave_Transmit()
+        (++) HAL_I2C_Slave_Receive()
+        (++) HAL_I2C_Mem_Write()
+        (++) HAL_I2C_Mem_Read()
+        (++) HAL_I2C_IsDeviceReady()
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2C_Master_Transmit_IT()
+        (++) HAL_I2C_Master_Receive_IT()
+        (++) HAL_I2C_Slave_Transmit_IT()
+        (++) HAL_I2C_Slave_Receive_IT()
+        (++) HAL_I2C_Mem_Write_IT()
+        (++) HAL_I2C_Mem_Read_IT()
+        (++) HAL_I2C_Master_Seq_Transmit_IT()
+        (++) HAL_I2C_Master_Seq_Receive_IT()
+        (++) HAL_I2C_Slave_Seq_Transmit_IT()
+        (++) HAL_I2C_Slave_Seq_Receive_IT()
+        (++) HAL_I2C_EnableListen_IT()
+        (++) HAL_I2C_DisableListen_IT()
+        (++) HAL_I2C_Master_Abort_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2C_Master_Transmit_DMA()
+        (++) HAL_I2C_Master_Receive_DMA()
+        (++) HAL_I2C_Slave_Transmit_DMA()
+        (++) HAL_I2C_Slave_Receive_DMA()
+        (++) HAL_I2C_Mem_Write_DMA()
+        (++) HAL_I2C_Mem_Read_DMA()
+        (++) HAL_I2C_Master_Seq_Transmit_DMA()
+        (++) HAL_I2C_Master_Seq_Receive_DMA()
+        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+        (++) HAL_I2C_Slave_Seq_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2C_MasterTxCpltCallback()
+        (++) HAL_I2C_MasterRxCpltCallback()
+        (++) HAL_I2C_SlaveTxCpltCallback()
+        (++) HAL_I2C_SlaveRxCpltCallback()
+        (++) HAL_I2C_MemTxCpltCallback()
+        (++) HAL_I2C_MemRxCpltCallback()
+        (++) HAL_I2C_AddrCallback()
+        (++) HAL_I2C_ListenCpltCallback()
+        (++) HAL_I2C_ErrorCallback()
+        (++) HAL_I2C_AbortCpltCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                          uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
+                         I2C_GENERATE_START_WRITE);
+    }
+    else
+    {
+      /* Send Slave Address */
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
+                         I2C_GENERATE_START_WRITE);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                         uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = 1U;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmits in slave mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                         uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint16_t tmpXferCount;
+  HAL_StatusTypeDef error;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Preload TX data if no stretch enable */
+    if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+      /* Flush TX register */
+      I2C_Flush_TXDR(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* If 10bit addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      /* Wait until ADDR flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Wait until DIR flag is set Transmitter mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+      /* Flush TX register */
+      I2C_Flush_TXDR(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until AF flag is set */
+    error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
+
+    if (error != HAL_OK)
+    {
+      /* Check that I2C transfer finished */
+      /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+      /* Mean XferCount == 0 */
+
+      tmpXferCount = hi2c->XferCount;
+      if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
+      {
+        /* Reset ErrorCode to NONE */
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+      }
+      else
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Flush TX register */
+      I2C_Flush_TXDR(hi2c);
+
+      /* Clear AF flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Wait until STOP flag is set */
+      if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        return HAL_ERROR;
+      }
+
+      /* Clear STOP flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+    }
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in blocking mode
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                        uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferSize = hi2c->XferCount;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Wait until DIR flag is reset Receiver mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        /* Store Last receive data if any */
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from RXDR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          hi2c->XferCount--;
+          hi2c->XferSize--;
+        }
+
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    if (hi2c->XferSize > 0U)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
+                         I2C_GENERATE_START_WRITE);
+    }
+    else
+    {
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
+                         I2C_GENERATE_START_WRITE);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                            uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = 1U;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Preload TX data if no stretch enable */
+    if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                              uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+  uint32_t sizetoxfer = 0U;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      sizetoxfer = hi2c->XferSize;
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+                                         (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
+                           xfermode, I2C_GENERATE_START_WRITE);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = 1U;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                         hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    /* Preload TX data if no stretch enable */
+    if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    if (hi2c->XferCount != 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
+                                         (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+                                         hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_LISTEN;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Enable Address Acknowledge */
+        hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR, STOP, NACK, ADDR interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_LISTEN;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                       hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Write an amount of data in blocking mode to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+    }
+
+    do
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+
+    } while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in blocking mode from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                   uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = 1U;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+
+    do
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = 1U;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+    } while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->XferSize    = 0U;
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Mem_ISR_IT;
+    hi2c->Devaddress  = DevAddress;
+
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+    {
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+    /* If Memory address size is 16Bit */
+    else
+    {
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+    }
+    /* Send Slave Address and Memory Address */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                      uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Mem_ISR_IT;
+    hi2c->Devaddress  = DevAddress;
+
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+    {
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+    /* If Memory address size is 16Bit */
+    else
+    {
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+    }
+    /* Send Slave Address and Memory Address */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Mem_ISR_DMA;
+    hi2c->Devaddress  = DevAddress;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+    {
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+    /* If Memory address size is 16Bit */
+    else
+    {
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+    }
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                       hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Send Slave Address and Memory Address */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Mem_ISR_DMA;
+    hi2c->Devaddress  = DevAddress;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+    {
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+    /* If Memory address size is 16Bit */
+    else
+    {
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+    }
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                       hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Send Slave Address and Memory Address */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+                                        uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  __IO uint32_t I2C_Trials = 0UL;
+
+  FlagStatus tmp1;
+  FlagStatus tmp2;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    do
+    {
+      /* Generate Start */
+      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+      /* Wait until STOPF flag is set or a NACK flag is set*/
+      tickstart = HAL_GetTick();
+
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+
+      while ((tmp1 == RESET) && (tmp2 == RESET))
+      {
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Update I2C state */
+            hi2c->State = HAL_I2C_STATE_READY;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+
+        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+      }
+
+      /* Check if the NACKF flag has not been set */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Device is ready */
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Clear STOP Flag, auto generated with autoend*/
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Increment Trials */
+      I2C_Trials++;
+    } while (I2C_Trials < Trials);
+
+    /* Update I2C state */
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Update I2C error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+  uint32_t sizetoxfer = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+                                  (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      sizetoxfer = hi2c->XferSize;
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to write */
+    if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+    {
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+    }
+    else
+    {
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                  uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+  HAL_StatusTypeDef dmaxferstatus;
+  uint32_t sizetoxfer = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+                                  (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      sizetoxfer = hi2c->XferSize;
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+                                         (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to write */
+        if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+        {
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+        }
+        else
+        {
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+        }
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+      {
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+      }
+      else
+      {
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to read */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                         hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to read */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      /* Abort DMA Xfer if any */
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                 uint32_t XferOptions)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+          will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+          will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                       hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* Enable ERR, STOP, NACK, ADDR interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                               uint32_t XferOptions)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
+                                       (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR = I2C_Slave_ISR_IT;
+
+    /* Enable the Address Match interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp;
+
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if (hi2c->State == HAL_I2C_STATE_LISTEN)
+  {
+    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+    hi2c->XferISR = NULL;
+
+    /* Disable the Address Match interrupt */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master or memory I2C IT or DMA process communication with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+  HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
+
+  if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts and Store Previous state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    }
+    else
+    {
+      /* Do nothing */
+    }
+
+    /* Set State at HAL_I2C_STATE_ABORT */
+    hi2c->State = HAL_I2C_STATE_ABORT;
+
+    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Wrong usage of abort function */
+    /* This function should be used only in case of abort monitored by master device */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Get current IT Flags and IT sources value */
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+  /* I2C events treatment -------------------------------------*/
+  if (hi2c->XferISR != NULL)
+  {
+    hi2c->XferISR(hi2c, itflags, itsources);
+  }
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmperror;
+
+  /* I2C Bus error interrupt occurred ------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+  }
+
+  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+  }
+
+  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+  }
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the Error Callback in case of Error detected */
+  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
+  {
+    I2C_ITError(hi2c, tmperror);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C error callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C abort callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  *  @brief   Peripheral State, Mode and Error functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2C handle state.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL state
+  */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
+{
+  /* Return I2C handle state */
+  return hi2c->State;
+}
+
+/**
+  * @brief  Returns the I2C Master, Slave, Memory or no mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL mode
+  */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->Mode;
+}
+
+/**
+  * @brief  Return the I2C error code.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *              the configuration information for the specified I2C.
+  * @retval I2C Error Code
+  */
+uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
+           ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
+  {
+    /* Write data to TXDR */
+    if (hi2c->XferCount != 0U)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+    {
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        /* Errata workaround 170323 */
+        if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+        {
+          hi2c->XferSize = 1U;
+        }
+        else
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+        }
+        I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+                             hi2c->XferOptions, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+                             I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, tmpITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                        uint32_t ITSources)
+{
+  uint32_t direction = I2C_GENERATE_START_WRITE;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    if (hi2c->Memaddress == 0xFFFFFFFFU)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+    else
+    {
+      /* Write LSB part of Memory Address */
+      hi2c->Instance->TXDR = hi2c->Memaddress;
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+    {
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        /* Errata workaround 170323 */
+        if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+        {
+          hi2c->XferSize = 1U;
+        }
+        else
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+        }
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TCR flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable Interrupt related to address step */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      direction = I2C_GENERATE_START_READ;
+    }
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      /* Errata workaround 170323 */
+      if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+      {
+        hi2c->XferSize = 1U;
+      }
+      else
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+      }
+
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_RELOAD_MODE, direction);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+
+      /* Set NBYTES to write and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_AUTOEND_MODE, direction);
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, tmpITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                          uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, tmpITFlags);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+        /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+           Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      }
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    if (hi2c->XferCount > 0U)
+    {
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+
+    if ((hi2c->XferCount == 0U) && \
+        (tmpoptions != I2C_NO_OPTION_FRAME))
+    {
+      /* Call I2C Slave Sequential complete process */
+      I2C_ITSlaveSeqCplt(hi2c);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, tmpITFlags);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Data have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if (hi2c->XferCount > 0U)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+    else
+    {
+      if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+      {
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                            uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t xfermode;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable TC interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Recover Slave address */
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      /* Prepare the new XferSize to transfer */
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        /* Errata workaround 170323 */
+        if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+        {
+          hi2c->XferSize = 1U;
+        }
+        else
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+        }
+        xfermode = I2C_RELOAD_MODE;
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          xfermode = hi2c->XferOptions;
+        }
+        else
+        {
+          xfermode = I2C_AUTOEND_MODE;
+        }
+      }
+
+      /* Set the new XferSize in Nbytes register */
+      I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Enable DMA Request */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                         uint32_t ITSources)
+{
+  uint32_t direction = I2C_GENERATE_START_WRITE;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write LSB part of Memory Address */
+    hi2c->Instance->TXDR = hi2c->Memaddress;
+
+    /* Reset Memaddress content */
+    hi2c->Memaddress = 0xFFFFFFFFU;
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable Interrupt related to address step */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Enable only Error interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Prepare the new XferSize to transfer */
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        /* Errata workaround 170323 */
+        if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+        {
+          hi2c->XferSize = 1U;
+        }
+        else
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+        }
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+      }
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Enable DMA Request */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TCR flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable Interrupt related to address step */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Enable only Error and NACK interrupt for data transfer */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      direction = I2C_GENERATE_START_READ;
+    }
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      /* Errata workaround 170323 */
+      if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+      {
+        hi2c->XferSize = 1U;
+      }
+      else
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+      }
+
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_RELOAD_MODE, direction);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+
+      /* Set NBYTES to write and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_AUTOEND_MODE, direction);
+    }
+
+    /* Update XferCount value */
+    hi2c->XferCount -= hi2c->XferSize;
+
+    /* Enable DMA Request */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t treatdmanack = 0U;
+  HAL_I2C_StateTypeDef tmpstate;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, ITFlags);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0 */
+    /* So clear Flag NACKF only */
+    if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+        (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+    {
+      /* Split check of hdmarx, for MISRA compliance */
+      if (hi2c->hdmarx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+        {
+          if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      /* Split check of hdmatx, for MISRA compliance  */
+      if (hi2c->hdmatx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+        {
+          if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      if (treatdmanack == 1U)
+      {
+        if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+          /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+             Warning[Pa134]: left and right operands are identical */
+        {
+          /* Call I2C Listen complete process */
+          I2C_ITListenCplt(hi2c, ITFlags);
+        }
+        else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+          /* Flush TX register */
+          I2C_Flush_TXDR(hi2c);
+
+          /* Last Byte is Transmitted */
+          /* Call I2C Slave Sequential complete process */
+          I2C_ITSlaveSeqCplt(hi2c);
+        }
+        else
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+        }
+      }
+      else
+      {
+        /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Set ErrorCode corresponding to a Non-Acknowledge */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+        /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+        tmpstate = hi2c->State;
+
+        if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+        {
+          if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+          }
+          else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+          }
+          else
+          {
+            /* Do nothing */
+          }
+
+          /* Call the corresponding callback to inform upper layer of End of Transfer */
+          I2C_ITError(hi2c, hi2c->ErrorCode);
+        }
+      }
+    }
+    else
+    {
+      /* Only Clear NACK Flag, no DMA treatment is pending */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for write request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                                uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TCR flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for read request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                               uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                               uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TC flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  I2C Address complete process callback.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint8_t transferdirection;
+  uint16_t slaveaddrcode;
+  uint16_t ownadd1code;
+  uint16_t ownadd2code;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ITFlags);
+
+  /* In case of Listen state, need to inform upper layer of address match code event */
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    transferdirection = I2C_GET_DIR(hi2c);
+    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+
+    /* If 10bits addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
+      {
+        slaveaddrcode = ownadd1code;
+        hi2c->AddrEventCount++;
+        if (hi2c->AddrEventCount == 2U)
+        {
+          /* Reset Address Event counter */
+          hi2c->AddrEventCount = 0U;
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        slaveaddrcode = ownadd2code;
+
+        /* Disable ADDR Interrupts */
+        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+    /* else 7 bits addressing mode is selected */
+    else
+    {
+      /* Disable ADDR Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* Else clear address flag only */
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Master sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* No Generate Stop, to permit restart mode */
+  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterTxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterRxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Slave sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Master complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmperror;
+  uint32_t tmpITFlags = ITFlags;
+  __IO uint32_t tmpreg;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+  }
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Reset handle parameters */
+  hi2c->XferISR       = NULL;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set acknowledge error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  /* Fetch Last receive data if any */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+  {
+    /* Read data from RXDR */
+    tmpreg = (uint8_t)hi2c->Instance->RXDR;
+    UNUSED(tmpreg);
+  }
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Slave complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmpITFlags = ITFlags;
+  uint32_t tmpoptions = hi2c->XferOptions;
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+  }
+  else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+  }
+  else if (tmpstate == HAL_I2C_STATE_LISTEN)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_NONE;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Disable Address Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
+    }
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
+    }
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+  }
+
+  /* All data are not transferred, so set error code accordingly */
+  if (hi2c->XferCount != 0U)
+  {
+    /* Set ErrorCode corresponding to a Non-Acknowledge */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+        /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+           Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      }
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+      }
+    }
+  }
+
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)
+    {
+      /* Call I2C Listen complete process */
+      I2C_ITListenCplt(hi2c, tmpITFlags);
+    }
+  }
+  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+  {
+    /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
+    I2C_ITSlaveSeqCplt(hi2c);
+
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ListenCpltCallback(hi2c);
+#else
+    HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Listen complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  /* Reset handle parameters */
+  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+
+  /* Disable all Interrupts*/
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+  /* Clear NACK Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  hi2c->ListenCpltCallback(hi2c);
+#else
+  HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  I2C interrupts error process.
+  * @param  hi2c I2C handle.
+  * @param  ErrorCode Error code to handle.
+  * @retval None
+  */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+  uint32_t tmppreviousstate;
+
+  /* Reset handle parameters */
+  hi2c->Mode          = HAL_I2C_MODE_NONE;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+  hi2c->XferCount     = 0U;
+
+  /* Set new error code */
+  hi2c->ErrorCode |= ErrorCode;
+
+  /* Disable Interrupts */
+  if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
+      (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+      (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    /* Disable all interrupts, except interrupts related to LISTEN state */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* keep HAL_I2C_STATE_LISTEN if set */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR       = I2C_Slave_ISR_IT;
+  }
+  else
+  {
+    /* Disable all interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
+    /* If state is an abort treatment on going, don't change state */
+    /* This change will be do later */
+    if (hi2c->State != HAL_I2C_STATE_ABORT)
+    {
+      /* Set HAL_I2C_STATE_READY */
+      hi2c->State         = HAL_I2C_STATE_READY;
+
+      /* Check if a STOPF is detected */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+      {
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+        {
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+          hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+    }
+    hi2c->XferISR       = NULL;
+  }
+
+  /* Abort DMA TX transfer if any */
+  tmppreviousstate = hi2c->PreviousState;
+
+  if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+                                 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+      {
+        /* Call Directly XferAbortCallback function in case of error */
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  /* Abort DMA RX transfer if any */
+  else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
+                                      (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  else
+  {
+    I2C_TreatErrorCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Error callback treatment.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Tx data register flush process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+  {
+    hi2c->Instance->TXDR = 0x00U;
+  }
+
+  /* Flush TX register if not empty */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  {
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+  }
+}
+
+/**
+  * @brief  DMA I2C master transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA stream */
+    if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+                         hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+
+/**
+  * @brief  DMA I2C slave transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    /* Last Byte is Transmitted */
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+
+/**
+  * @brief DMA I2C master receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      /* Errata workaround 170323 */
+      if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+      {
+        hi2c->XferSize = 1U;
+      }
+      else
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+      }
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA stream */
+    if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
+                         hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+
+/**
+  * @brief  DMA I2C slave receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
+      (tmpoptions != I2C_NO_OPTION_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+
+/**
+  * @brief  DMA I2C communication error callback.
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+  uint32_t treatdmaerror = 0U;
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  if (hi2c->hdmatx != NULL)
+  {
+    if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
+    {
+      treatdmaerror = 1U;
+    }
+  }
+
+  if (hi2c->hdmarx != NULL)
+  {
+    if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
+    {
+      treatdmaerror = 1U;
+    }
+  }
+
+  /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
+  if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
+  {
+    /* Disable Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+  }
+}
+
+
+/**
+  * @brief DMA I2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Reset AbortCpltCallback */
+  if (hi2c->hdmatx != NULL)
+  {
+    hi2c->hdmatx->XferAbortCallback = NULL;
+  }
+  if (hi2c->hdmarx != NULL)
+  {
+    hi2c->hdmarx->XferAbortCallback = NULL;
+  }
+
+  I2C_TreatErrorCallback(hi2c);
+}
+
+
+/**
+  * @brief  This function handles I2C Communication Timeout. It waits
+  *                until a flag is no longer in the specified status.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Flag Specifies the I2C flag to check.
+  * @param  Status The actual Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+                                                    uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
+        {
+          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+          hi2c->State = HAL_I2C_STATE_READY;
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
+        {
+          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+          hi2c->State = HAL_I2C_STATE_READY;
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+
+    /* Check if a STOPF is detected */
+    if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
+    {
+      /* Check if an RXNE is pending */
+      /* Store Last receive data if any */
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+      {
+        /* Return HAL_OK */
+        /* The Reading of data from RXDR will be done in caller function */
+        status = HAL_OK;
+      }
+
+      /* Check a no-acknowledge have been detected */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+      {
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+        hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Clear Configuration Register 2 */
+        I2C_RESET_CR2(hi2c);
+
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        status = HAL_ERROR;
+      }
+      else
+      {
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+      }
+    }
+
+    /* Check for the Timeout */
+    if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
+    {
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        status = HAL_ERROR;
+      }
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  This function handles errors detection during an I2C Communication.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t itflag   = hi2c->Instance->ISR;
+  uint32_t error_code = 0;
+  uint32_t tickstart = Tickstart;
+  uint32_t tmp1;
+  HAL_I2C_ModeTypeDef tmp2;
+
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
+  {
+    /* Clear NACKF Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Wait until STOP Flag is set or timeout occurred */
+    /* AutoEnd should be initiate after AF */
+    while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
+          tmp2 = hi2c->Mode;
+
+          /* In case of I2C still busy, try to regenerate a STOP manually */
+          if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
+              (tmp1 != I2C_CR2_STOP) && \
+              (tmp2 != HAL_I2C_MODE_SLAVE))
+          {
+            /* Generate Stop */
+            hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+            /* Update Tick with new reference */
+            tickstart = HAL_GetTick();
+          }
+
+          while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+          {
+            /* Check for the Timeout */
+            if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
+            {
+              error_code |= HAL_I2C_ERROR_TIMEOUT;
+
+              status = HAL_ERROR;
+
+              break;
+            }
+          }
+        }
+      }
+    }
+
+    /* In case STOP Flag is detected, clear it */
+    if (status == HAL_OK)
+    {
+      /* Clear STOP Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+    }
+
+    error_code |= HAL_I2C_ERROR_AF;
+
+    status = HAL_ERROR;
+  }
+
+  /* Refresh Content of Status register */
+  itflag = hi2c->Instance->ISR;
+
+  /* Then verify if an additional errors occurs */
+  /* Check if a Bus error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
+  {
+    error_code |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+
+    status = HAL_ERROR;
+  }
+
+  /* Check if an Over-Run/Under-Run error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
+  {
+    error_code |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+
+    status = HAL_ERROR;
+  }
+
+  /* Check if an Arbitration Loss error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
+  {
+    error_code |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+
+    status = HAL_ERROR;
+  }
+
+  if (status != HAL_OK)
+  {
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->ErrorCode |= error_code;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  hi2c I2C handle.
+  * @param  DevAddress Specifies the slave address to be programmed.
+  * @param  Size Specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  Mode New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+  * @param  Request New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+  * @retval None
+  */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+                               uint32_t Request)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_TRANSFER_MODE(Mode));
+  assert_param(IS_TRANSFER_REQUEST(Request));
+
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+                             (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+                             (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+
+  /* update CR2 register */
+  MODIFY_REG(hi2c->Instance->CR2, \
+             ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+               (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
+               I2C_CR2_START | I2C_CR2_STOP)), tmp);
+}
+
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
+      (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
+      (hi2c->XferISR != I2C_Mem_ISR_DMA))
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
+    if (InterruptRequest == I2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= I2C_IT_STOPI;
+    }
+  }
+
+  else
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
+    if (InterruptRequest == I2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+    }
+
+    if (InterruptRequest == I2C_XFER_RELOAD_IT)
+    {
+      /* Enable TC interrupts */
+      tmpisr |= I2C_IT_TCI;
+    }
+  }
+
+  /* Enable interrupts only at the end */
+  /* to avoid the risk of I2C interrupt handle execution before */
+  /* all interrupts requested done */
+  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+  {
+    /* Disable TC and TXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+  {
+    /* Disable TC and RXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+  {
+    /* Disable ADDR, NACK and STOP interrupts */
+    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+  }
+
+  if (InterruptRequest == I2C_XFER_ERROR_IT)
+  {
+    /* Enable ERR and NACK interrupts */
+    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+  }
+
+  if (InterruptRequest == I2C_XFER_CPLT_IT)
+  {
+    /* Enable STOP interrupts */
+    tmpisr |= I2C_IT_STOPI;
+  }
+
+  if (InterruptRequest == I2C_XFER_RELOAD_IT)
+  {
+    /* Enable TC interrupts */
+    tmpisr |= I2C_IT_TCI;
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+  /* if user set XferOptions to I2C_OTHER_FRAME            */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to I2C_FIRST_FRAME                    */
+  if (hi2c->XferOptions == I2C_OTHER_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+  /* it request implicitly to generate a restart condition    */
+  /* then generate a stop condition at the end of transfer    */
+  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
+  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c
new file mode 100644
index 0000000..035731f
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c
@@ -0,0 +1,270 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @brief   I2C Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of I2C Extended peripheral:
+  *           + Filter Mode Functions
+  *           + FastModePlus Functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the I2C interface for STM32F7xx
+       devices contains the following additional features
+
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+       (+) Disable or enable Fast Mode Plus
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to:
+    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_I2CEx_EnableFastModePlus()
+          (++) HAL_I2CEx_DisableFastModePlus()
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx I2CEx
+  * @brief I2C Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+  * @brief    Filter Mode Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Filter Mode Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure I2C Analog noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter New state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hi2c->Instance->CR1 |= AnalogFilter;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure I2C Digital noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->CR1;
+
+    /* Reset I2Cx DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << 8U;
+
+    /* Store the new register value */
+    hi2c->Instance->CR1 = tmpreg;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+#if  (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP)
+
+/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @brief    Fast Mode Plus Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Fast Mode Plus Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Enable fast mode plus driving capability for selected pin */
+  SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @brief Disable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Disable fast mode plus driving capability for selected pin */
+  CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
+}
+/**
+  * @}
+  */
+#endif /* Fast Mode Plus Availability */
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c
new file mode 100644
index 0000000..eb548e0
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c
@@ -0,0 +1,600 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions 
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWR_Private_Constants
+  * @{
+  */
+	
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  * @{
+  */     
+#define PVD_MODE_IT               ((uint32_t)0x00010000U)
+#define PVD_MODE_EVT              ((uint32_t)0x00020000U)
+#define PVD_RISING_EDGE           ((uint32_t)0x00000001U)
+#define PVD_FALLING_EDGE          ((uint32_t)0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
+  * @{
+  */  
+#define  PWR_EWUP_MASK                          ((uint32_t)0x00003F00)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  *  @brief    Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      After reset, the backup domain (RTC registers, RTC backup data 
+      registers and backup SRAM) is protected against possible unwanted 
+      write accesses. 
+      To enable access to the RTC Domain and RTC registers, proceed as follows:
+        (+) Enable the Power Controller (PWR) APB1 interface clock using the
+            __HAL_RCC_PWR_CLK_ENABLE() macro.
+        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
+  * @retval None
+  */
+void HAL_PWR_DeInit(void)
+{
+  __HAL_RCC_PWR_FORCE_RESET();
+  __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+  * @brief Enables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
+  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @retval None
+  */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+  /* Enable access to RTC and backup registers */
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief Disables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
+  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @retval None
+  */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+  /* Disable access to RTC and backup registers */
+	CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+  *  @brief Low Power modes configuration functions 
+  *
+@verbatim
+
+ ===============================================================================
+                 ##### Peripheral Control functions #####
+ ===============================================================================
+     
+    *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a 
+          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 
+          than the PVD threshold. This event is internally connected to the EXTI 
+          line16 and can generate an interrupt if enabled. This is done through
+          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
+      (+) The PVD is stopped in Standby mode.
+
+    *** Wake-up pin configuration ***
+    ================================
+    [..]
+      (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 
+          forced in input pull-down configuration and is active on rising edges.
+      (+) There are up to 6 Wake-up pin in the STM32F7 devices family
+
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+      The devices feature 3 low-power modes:
+      (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.
+      (+) Stop mode: all clocks are stopped, regulator running, regulator 
+          in low power mode
+      (+) Standby mode: 1.2V domain powered off.
+   
+   *** Sleep mode ***
+   ==================
+    [..]
+      (+) Entry:
+        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
+              functions with
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+      
+      -@@- The Regulator parameter is not used for the STM32F7 family 
+              and is kept as parameter just to maintain compatibility with the 
+              lower power families (STM32L).
+      (+) Exit:
+        Any peripheral interrupt acknowledged by the nested vectored interrupt 
+              controller (NVIC) can wake up the device from Sleep mode.
+
+   *** Stop mode ***
+   =================
+    [..]
+      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
+      and the HSE RC oscillators are disabled. Internal SRAM and register contents 
+      are preserved.
+      The voltage regulator can be configured either in normal or low-power mode.
+      To minimize the consumption In Stop mode, FLASH can be powered off before 
+      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
+      It can be switched on again by software after exiting the Stop mode using
+      the HAL_PWREx_DisableFlashPowerDown() function. 
+
+      (+) Entry:
+         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) 
+             function with:
+          (++) Main regulator ON.
+          (++) Low Power regulator ON.
+      (+) Exit:
+        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** Standby mode ***
+   ====================
+    [..]
+    (+)
+      The Standby mode allows to achieve the lowest power consumption. It is based 
+      on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. 
+      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
+      the HSE oscillator are also switched off. SRAM and register contents are lost 
+      except for the RTC registers, RTC backup registers, backup SRAM and Standby 
+      circuitry.
+   
+      The voltage regulator is OFF.
+      
+      (++) Entry:
+        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
+      (++) Exit:
+        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
+             wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+   =============================================
+    [..]
+    
+     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
+      Wakeup event, a tamper event or a time-stamp event, without depending on 
+      an external interrupt (Auto-wakeup mode).
+
+      (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
+       
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 
+              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+             is necessary to configure the RTC to detect the tamper or time stamp event using the
+                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
+                  
+        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
+              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
+  *        information for the PVD.
+  * @note Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each 
+  *         detection level.
+  * @retval None
+  */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+  
+  /* Set PLS[7:5] bits according to PVDLevel value */
+  MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
+  
+  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT();
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 
+
+  /* Configure interrupt mode */
+  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT();
+  }
+  
+  /* Configure event mode */
+  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+  }
+  
+  /* Configure the edge */
+  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+  }
+  
+  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+  }
+}
+
+/**
+  * @brief Enables the Power Voltage Detector(PVD).
+  * @retval None
+  */
+void HAL_PWR_EnablePVD(void)
+{
+  /* Enable the power voltage detector */
+	SET_BIT(PWR->CR1, PWR_CR1_PVDE);
+}
+
+/**
+  * @brief Disables the Power Voltage Detector(PVD).
+  * @retval None
+  */
+void HAL_PWR_DisablePVD(void)
+{
+  /* Disable the power voltage detector */
+	CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
+}
+
+/**
+  * @brief Enable the WakeUp PINx functionality.
+  * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
+  *         This parameter can be one of the following legacy values, which sets the default polarity: 
+  *         detection on high level (rising edge):
+  *           @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 
+  *         or one of the following value where the user can explicitly states the enabled pin and
+  *         the chosen polarity  
+  *           @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW 
+  *           @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW 
+  *           @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW 
+  *           @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
+  *           @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW 
+  *           @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW 
+  * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.               
+  * @retval None
+  */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
+{
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
+  
+  /* Enable wake-up pin */
+  SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));
+	
+  /* Specifies the Wake-Up pin polarity for the event detection
+    (rising or falling edge) */
+  MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));
+}
+
+/**
+  * @brief Disables the WakeUp PINx functionality.
+  * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
+  *         This parameter can be one of the following values:
+  *           @arg PWR_WAKEUP_PIN1
+  *           @arg PWR_WAKEUP_PIN2
+  *           @arg PWR_WAKEUP_PIN3
+  *           @arg PWR_WAKEUP_PIN4
+  *           @arg PWR_WAKEUP_PIN5
+  *           @arg PWR_WAKEUP_PIN6 
+  * @retval None
+  */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+  CLEAR_BIT(PWR->CSR2, WakeUpPinx);
+}
+  
+/**
+  * @brief Enters Sleep mode.
+  *   
+  * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+  * 
+  * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
+  *       systick interrupt when used as time base for Timeout 
+  *                
+  * @param Regulator Specifies the regulator state in SLEEP mode.
+  *            This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
+  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
+  * @note This parameter is not used for the STM32F7 family and is kept as parameter
+  *       just to maintain compatibility with the lower power families.
+  * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Regulator);
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Ensure that all instructions done before entering SLEEP mode */
+  __DSB();
+  __ISB();
+
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+}
+
+/**
+  * @brief Enters Stop mode. 
+  * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note When exiting Stop mode by issuing an interrupt or a wakeup event, 
+  *         the HSI RC oscillator is selected as system clock.
+  * @note When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.    
+  * @param Regulator Specifies the regulator state in Stop mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
+  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
+  * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
+  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+  /* Select the regulator state in Stop mode ---------------------------------*/
+  tmpreg = PWR->CR1;
+  /* Clear PDDS and LPDS bits */
+  tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);
+
+  /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
+  tmpreg |= Regulator;
+
+  /* Store the new value */
+  PWR->CR1 = tmpreg;
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+  /* Ensure that all instructions done before entering STOP mode */
+  __DSB();
+  __ISB();
+
+  /* Select Stop mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_STOPENTRY_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
+}
+
+/**
+  * @brief Enters Standby mode.
+  * @note In Standby mode, all I/O pins are high impedance except for:
+  *          - Reset pad (still available) 
+  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
+  *            Alarm out, or RTC clock calibration out.
+  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
+  *          - WKUP pins if enabled.       
+  * @retval None
+  */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+  /* Select Standby mode */
+  PWR->CR1 |= PWR_CR1_PDDS;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+  /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @brief This function handles the PWR PVD interrupt request.
+  * @note This API should be called under the PVD_IRQHandler().
+  * @retval None
+  */
+void HAL_PWR_PVD_IRQHandler(void)
+{
+  /* Check PWR Exti flag */
+  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
+  {
+    /* PWR PVD interrupt user callback */
+    HAL_PWR_PVDCallback();
+    
+    /* Clear PWR Exti pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+  }
+}
+
+/**
+  * @brief  PWR PVD interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWR_PVDCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PWR_PVDCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 
+  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+  *       re-enters SLEEP mode when an interruption handling is over.
+  *       Setting this bit is useful when the processor is expected to run only on
+  *       interruptions handling.         
+  * @retval None
+  */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
+  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+  *       re-enters SLEEP mode when an interruption handling is over.          
+  * @retval None
+  */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief Enables CORTEX M4 SEVONPEND bit. 
+  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 
+  *       WFE to wake up when an interrupt moves from inactive to pended.
+  * @retval None
+  */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+  /* Set SEVONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @brief Disables CORTEX M4 SEVONPEND bit. 
+  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
+  *       WFE to wake up when an interrupt moves from inactive to pended.         
+  * @retval None
+  */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c
new file mode 100644
index 0000000..f426aaa
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c
@@ -0,0 +1,552 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_pwr_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended PWR HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of PWR extension peripheral:           
+  *           + Peripheral Extended features functions
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx PWREx
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWREx_Private_Constants
+  * @{
+  */    
+#define PWR_OVERDRIVE_TIMEOUT_VALUE  1000
+#define PWR_UDERDRIVE_TIMEOUT_VALUE  1000
+#define PWR_BKPREG_TIMEOUT_VALUE     1000
+#define PWR_VOSRDY_TIMEOUT_VALUE     1000
+/**
+  * @}
+  */
+    
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+  *  @{
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions 
+  *  @brief Peripheral Extended features functions 
+  *
+@verbatim   
+
+ ===============================================================================
+                 ##### Peripheral extended features functions #####
+ ===============================================================================
+
+    *** Main and Backup Regulators configuration ***
+    ================================================
+    [..] 
+      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from 
+          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is 
+          retained even in Standby or VBAT mode when the low power backup regulator
+          is enabled. It can be considered as an internal EEPROM when VBAT is 
+          always present. You can use the HAL_PWREx_EnableBkUpReg() function to 
+          enable the low power backup regulator. 
+
+      (+) When the backup domain is supplied by VDD (analog switch connected to VDD) 
+          the backup SRAM is powered from VDD which replaces the VBAT power supply to 
+          save battery life.
+
+      (+) The backup SRAM is not mass erased by a tamper event. It is read 
+          protected to prevent confidential data, such as cryptographic private 
+          key, from being accessed. The backup SRAM can be erased only through 
+          the Flash interface when a protection level change from level 1 to 
+          level 0 is requested. 
+      -@- Refer to the description of Read protection (RDP) in the Flash 
+          programming manual.
+
+      (+) The main internal regulator can be configured to have a tradeoff between 
+          performance and power consumption when the device does not operate at 
+          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() 
+          macro which configure VOS bit in PWR_CR register
+          
+        Refer to the product datasheets for more details.
+
+    *** FLASH Power Down configuration ****
+    =======================================
+    [..] 
+      (+) By setting the FPDS bit in the PWR_CR register by using the 
+          HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power 
+          down mode when the device enters Stop mode. When the Flash memory 
+          is in power down mode, an additional startup delay is incurred when 
+          waking up from Stop mode.
+
+    *** Over-Drive and Under-Drive configuration ****
+    =================================================
+    [..]         
+       (+) In Run mode: the main regulator has 2 operating modes available:
+        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given 
+             voltage scaling (scale 1, scale 2 or scale 3)
+        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a 
+            higher frequency than the normal mode for a given voltage scaling (scale 1,  
+            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
+            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow 
+            the sequence described in Reference manual.
+             
+       (+) In Stop mode: the main regulator or low power regulator supplies a low power 
+           voltage to the 1.2V domain, thus preserving the content of registers 
+           and internal SRAM. 2 operating modes are available:
+         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only 
+              available when the main regulator or the low power regulator is used in Scale 3 or 
+              low voltage mode.
+         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
+              available when the main regulator or the low power regulator is in low voltage mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enables the Backup Regulator.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
+{
+  uint32_t tickstart = 0;
+
+  /* Enable Backup regulator */
+  PWR->CSR1 |= PWR_CSR1_BRE;
+    
+  /* Workaround for the following hardware bug: */
+  /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
+  PWR->CSR1 |= PWR_CSR1_EIWUP;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till Backup regulator ready flag is set */  
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    } 
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Disables the Backup Regulator.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
+{
+  uint32_t tickstart = 0;
+  
+  /* Disable Backup regulator */
+  PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
+  
+  /* Workaround for the following hardware bug: */
+  /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
+  PWR->CSR1 |= PWR_CSR1_EIWUP;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till Backup regulator ready flag is set */  
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    } 
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Enables the Flash Power Down in Stop mode.
+  * @retval None
+  */
+void HAL_PWREx_EnableFlashPowerDown(void)
+{
+  /* Enable the Flash Power Down */
+  PWR->CR1 |= PWR_CR1_FPDS;
+}
+
+/**
+  * @brief Disables the Flash Power Down in Stop mode.
+  * @retval None
+  */
+void HAL_PWREx_DisableFlashPowerDown(void)
+{
+  /* Disable the Flash Power Down */
+  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
+}
+
+/**
+  * @brief Enables Main Regulator low voltage mode.
+  * @retval None
+  */
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
+{
+  /* Enable Main regulator low voltage */
+  PWR->CR1 |= PWR_CR1_MRUDS;
+}
+
+/**
+  * @brief Disables Main Regulator low voltage mode.
+  * @retval None
+  */
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
+{  
+  /* Disable Main regulator low voltage */
+  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
+}
+
+/**
+  * @brief Enables Low Power Regulator low voltage mode.
+  * @retval None
+  */
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
+{
+  /* Enable low power regulator */
+  PWR->CR1 |= PWR_CR1_LPUDS;
+}
+
+/**
+  * @brief Disables Low Power Regulator low voltage mode.
+  * @retval None
+  */
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
+{
+  /* Disable low power regulator */
+  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
+}
+
+/**
+  * @brief  Activates the Over-Drive mode.
+  * @note   This mode allows the CPU and the core logic to operate at a higher frequency
+  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).   
+  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
+  *         critical tasks and when the system clock source is either HSI or HSE. 
+  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
+  *         The peripheral clocks must be enabled once the Over-drive mode is activated.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
+{
+  uint32_t tickstart = 0;
+
+  __HAL_RCC_PWR_CLK_ENABLE();
+  
+  /* Enable the Over-drive to extend the clock frequency to 216 MHz */
+  __HAL_PWR_OVERDRIVE_ENABLE();
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  /* Enable the Over-drive switch */
+  __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  } 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivates the Over-Drive mode.
+  * @note   This mode allows the CPU and the core logic to operate at a higher frequency
+  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).    
+  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
+  *         critical tasks and when the system clock source is either HSI or HSE. 
+  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
+  *         The peripheral clocks must be enabled once the Over-drive mode is activated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
+{
+  uint32_t tickstart = 0;
+  
+  __HAL_RCC_PWR_CLK_ENABLE();
+    
+  /* Disable the Over-drive switch */
+  __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+ 
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  } 
+  
+  /* Disable the Over-drive */
+  __HAL_PWR_OVERDRIVE_DISABLE();
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enters in Under-Drive STOP mode.
+  * 
+  * @note    This mode can be selected only when the Under-Drive is already active 
+  *   
+  * @note    This mode is enabled only with STOP low power mode.
+  *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+  *          mode is only available when the main regulator or the low power regulator 
+  *          is in low voltage mode
+  *        
+  * @note   If the Under-drive mode was enabled, it is automatically disabled after 
+  *         exiting Stop mode. 
+  *         When the voltage regulator operates in Under-drive mode, an additional  
+  *         startup delay is induced when waking up from Stop mode.
+  *                    
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+  *   
+  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, 
+  *         the HSI RC oscillator is selected as system clock.
+  *           
+  * @note   When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.
+  *     
+  * @param  Regulator specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode 
+  *                 and Flash memory in power-down when the device is in Stop under-drive mode
+  *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode 
+  *                and Flash memory in power-down when the device is in Stop under-drive mode
+  * @param  STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
+  *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+  uint32_t tempreg = 0;
+  uint32_t tickstart = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+  
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  /* Enable the Under-drive Mode ---------------------------------------------*/
+  /* Clear Under-drive flag */
+  __HAL_PWR_CLEAR_ODRUDR_FLAG();
+  
+  /* Enable the Under-drive */ 
+  __HAL_PWR_UNDERDRIVE_ENABLE();
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for UnderDrive mode is ready */
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tempreg = PWR->CR1;
+  /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
+  tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
+  
+  /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
+  tempreg |= Regulator;
+  
+  /* Store the new value */
+  PWR->CR1 = tempreg;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_SLEEPENTRY_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief Returns Voltage Scaling Range.
+  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or 
+  *            PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
+  */  
+uint32_t HAL_PWREx_GetVoltageRange(void)
+{
+  return  (PWR->CR1 & PWR_CR1_VOS);
+}
+
+/**
+  * @brief Configures the main internal regulator output voltage.
+  * @param  VoltageScaling specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+  *                                                typical output voltage at 1.4 V,  
+  *                                                system frequency up to 216 MHz.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+  *                                                typical output voltage at 1.2 V,                
+  *                                                system frequency up to 180 MHz.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
+  *                                                typical output voltage at 1.00 V,                
+  *                                                system frequency up to 151 MHz.
+  * @note To update the system clock frequency(SYSCLK):
+  *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
+  *        - Call the HAL_RCC_OscConfig() to configure the PLL.
+  *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
+  *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().
+  * @note The scale can be modified only when the HSI or HSE clock source is selected 
+  *        as system clock source, otherwise the API returns HAL_ERROR.  
+  * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
+  *       value in the PWR_CR1 register are not taken in account.
+  * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
+  * @note The new voltage scale is active only when the PLL is ON.  
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+  uint32_t tickstart = 0;
+
+  assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
+
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* Check if the PLL is used as system clock or not */
+  if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+  {
+    /* Disable the main PLL */
+    __HAL_RCC_PLL_DISABLE();
+    
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();    
+    /* Wait till PLL is disabled */  
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Set Range */
+    __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+    
+    /* Enable the main PLL */
+    __HAL_RCC_PLL_ENABLE();
+    
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLL is ready */  
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      } 
+    }
+    
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();
+    while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+    {
+      if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      } 
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c
new file mode 100644
index 0000000..6c030ce
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c
@@ -0,0 +1,1239 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    [..]
+      After reset the device is running from Internal High Speed oscillator
+      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
+      and I-Cache are disabled, and all peripherals are off except internal
+      SRAM, Flash and JTAG.
+      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
+          all peripherals mapped on these buses are running at HSI speed.
+      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+      (+) All GPIOs are in input floating state, except the JTAG pins which
+          are assigned to be used for debug purpose.
+
+    [..]
+      Once the device started from reset, the user application has to:
+      (+) Configure the clock source to be used to drive the System clock
+          (if the application needs higher frequency/performance)
+      (+) Configure the System clock frequency and Flash settings
+      (+) Configure the AHB and APB buses prescalers
+      (+) Enable the clock for the peripheral(s) to be used
+      (+) Configure the clock source(s) for peripherals which clocks are not
+          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
+
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+          after the clock enable bit is set on the hardware register
+      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+          after the clock enable bit is set on the hardware register
+
+    [..]
+      Implemented Workaround:
+      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC RCC
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+
+#define MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT        GPIOA
+#define MCO1_PIN              GPIO_PIN_8
+
+#define MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
+#define MCO2_GPIO_PORT         GPIOC
+#define MCO2_PIN               GPIO_PIN_9
+
+/**
+  * @}
+  */
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+  @verbatim
+  ===============================================================================
+##### Initialization and de-initialization functions #####
+  ===============================================================================
+    [..]
+      This section provides functions allowing to configure the internal/external oscillators
+      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
+      and APB2).
+
+    [..] Internal/external clock and PLL configuration
+      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
+          the PLL as System clock source.
+
+      (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+          clock source.
+
+      (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
+          through the PLL as System clock source. Can be used also as RTC clock source.
+
+      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+      (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
+        (++) The first output is used to generate the high speed system clock (up to 216 MHz)
+        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+             the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
+
+      (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
+          and if a HSE clock failure occurs(HSE used directly or through PLL as System
+          clock source), the System clock is automatically switched to HSI and an interrupt
+          is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
+          (Non-Maskable Interrupt) exception vector.
+
+      (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
+          clock (through a configurable prescaler) on PA8 pin.
+
+      (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
+          clock (through a configurable prescaler) on PC9 pin.
+
+    [..] System, AHB and APB buses clocks configuration
+      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+          HSE and PLL.
+          The AHB clock (HCLK) is derived from System clock through configurable
+          prescaler and used to clock the CPU, memory and peripherals mapped
+          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+          from AHB clock through configurable prescalers and used to clock
+          the peripherals mapped on these buses. You can use
+          "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+          (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
+              from an external clock mapped on the I2S_CKIN pin.
+              You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
+          (+@)  SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
+              from an external clock mapped on the I2S_CKIN pin.
+               You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
+          (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
+              divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
+              macros to configure this clock.
+          (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
+              to work correctly, while the SDIO require a frequency equal or lower than
+              to 48. This clock is derived of the main PLL through PLLQ divider.
+          (+@) IWDG clock which is always the LSI clock.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL, PLLI2S and PLLSAI OFF
+  *            - AHB, APB1 and APB2 prescaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+  uint32_t tickstart;
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Set HSION bit to the reset value */
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+
+  /* Wait till HSI is ready */
+  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set HSITRIM[4:0] bits to the reset value */
+  SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset CFGR register */
+  CLEAR_REG(RCC->CFGR);
+
+  /* Wait till clock switch is ready */
+  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Clear HSEON, HSEBYP and CSSON bits */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
+
+  /* Wait till HSE is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Clear PLLON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+
+  /* Wait till PLL is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLLI2SON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+
+  /* Wait till PLLI2S is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLLSAI bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+
+  /* Wait till PLLSAI is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */
+  RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U;
+
+  /* Reset PLLI2SCFGR register to default value */
+  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
+
+  /* Reset PLLSAICFGR register to default value */
+  RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U;
+
+  /* Disable all interrupts */
+  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);
+
+  /* Clear all interrupt flags */
+  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);
+
+  /* Clear LSION bit */
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+
+  /* Reset all CSR flags */
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HSI_VALUE;
+
+  /* Adapt Systick interrupt period */
+  if (HAL_InitTick(uwTickPrio) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this function. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this function. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart;
+  uint32_t pll_config;
+  FlagStatus pwrclkchanged = RESET;
+
+  /* Check Null pointer */
+  if (RCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+  /*------------------------------- HSE Configuration ------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+    /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
+    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+    {
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+      /* Check the HSE State */
+      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+        {
+          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is bypassed or disabled */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+        {
+          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+    {
+      /* When HSI is used as system clock it will not disabled */
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the HSI State */
+      if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+        {
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+        {
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+      {
+        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+      {
+        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Update LSE configuration in Backup Domain control register    */
+    /* Requires to enable write access to Backup Domain of necessary */
+    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+    {
+      /* Enable Power Clock*/
+      __HAL_RCC_PWR_CLK_ENABLE();
+      pwrclkchanged = SET;
+    }
+
+    if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+    {
+      /* Enable write access to Backup domain */
+      PWR->CR1 |= PWR_CR1_DBP;
+
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+
+      while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+    /* Check the LSE State */
+    if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Restore clock configuration if changed */
+    if (pwrclkchanged == SET)
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+    {
+      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+#if defined (RCC_PLLCFGR_PLLR)
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+#endif
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+#if defined (RCC_PLLCFGR_PLLR)
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+                             RCC_OscInitStruct->PLL.PLLM,
+                             RCC_OscInitStruct->PLL.PLLN,
+                             RCC_OscInitStruct->PLL.PLLP,
+                             RCC_OscInitStruct->PLL.PLLQ,
+                             RCC_OscInitStruct->PLL.PLLR);
+#else
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+                             RCC_OscInitStruct->PLL.PLLM,
+                             RCC_OscInitStruct->PLL.PLLN,
+                             RCC_OscInitStruct->PLL.PLLP,
+                             RCC_OscInitStruct->PLL.PLLQ);
+#endif
+
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Do not return HAL_ERROR if request repeats the current configuration */
+      pll_config = RCC->PLLCFGR;
+#if defined (RCC_PLLCFGR_PLLR)
+      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+          (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+          (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+          (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
+          (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
+          (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
+          (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
+#else
+      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+          (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+          (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+          (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
+          (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
+          (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
+#endif
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
+  *         parameters in the RCC_ClkInitStruct.
+  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC peripheral.
+  * @param  FLatency FLASH Latency, this parameter depend on device selected
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
+  *
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  *
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after startup delay or PLL locked).
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready.
+  *         You can use HAL_RCC_GetClockConfig() function to know which clock is
+  *         currently used as system clock source.
+  * @note   Depending on the device voltage range, the software has to set correctly
+  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+  uint32_t tickstart = 0;
+
+  /* Check Null pointer */
+  if (RCC_ClkInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+  assert_param(IS_FLASH_LATENCY(FLatency));
+
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+     must be correctly programmed according to the frequency of the CPU clock
+     (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the CPU frequency */
+  if (FLatency > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if (__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+    /* Set the highest APBx dividers in order to ensure that we do not go through
+       a non-spec phase whatever we decrease or increase HCLK. */
+    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+    {
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+    }
+
+    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+    {
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+    }
+
+    /* Set the new HCLK clock divider */
+    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+  }
+
+  /*------------------------- SYSCLK Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+  {
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+    /* HSE is selected as System Clock Source */
+    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    {
+      /* Check the HSE ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* PLL is selected as System Clock Source */
+    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+    {
+      /* Check the PLL ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* HSI is selected as System Clock Source */
+    else
+    {
+      /* Check the HSI ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+
+    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+    {
+      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if (FLatency < __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if (__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+  }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+  }
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
+
+  /* Configure the source of time base considering new system clocks settings*/
+  HAL_InitTick(uwTickPrio);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+  *  @brief   RCC clocks control functions
+  *
+  @verbatim
+  ===============================================================================
+                  ##### Peripheral Control functions #####
+  ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
+  * @note   PA8/PC9 should be configured in alternate function mode.
+  * @param  RCC_MCOx specifies the output direction for the clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
+  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
+  * @param  RCC_MCOSource specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+  * @param  RCC_MCODiv specifies the MCOx prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  * @retval None
+  */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCOx));
+  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+  /* RCC_MCO1 */
+  if (RCC_MCOx == RCC_MCO1)
+  {
+    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+    /* MCO1 Clock Enable */
+    MCO1_CLK_ENABLE();
+
+    /* Configure the MCO1 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO1_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+  }
+  else
+  {
+    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+
+    /* MCO2 Clock Enable */
+    MCO2_CLK_ENABLE();
+
+    /* Configure the MCO2 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO2_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
+  }
+}
+
+/**
+  * @brief  Enables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+  * @brief  Disables the Clock Security System.
+  * @retval None
+  */
+void HAL_RCC_DisableCSS(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+  * @brief  Returns the SYSCLK frequency
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  * @note     (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+  *               16 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baudrate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t pllm = 0, pllvco = 0, pllp = 0;
+  uint32_t sysclockfreq = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
+    {
+      sysclockfreq = HSI_VALUE;
+      break;
+    }
+    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
+    {
+      sysclockfreq = HSE_VALUE;
+      break;
+    }
+    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock  source */
+    {
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+      SYSCLK = PLL_VCO / PLLP */
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
+
+      sysclockfreq = pllvco / pllp;
+      break;
+    }
+    default:
+    {
+      sysclockfreq = HSI_VALUE;
+      break;
+    }
+  }
+  return sysclockfreq;
+}
+
+/**
+  * @brief  Returns the HCLK frequency
+  * @note   Each time HCLK changes, this function must be called to update the
+  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+  return SystemCoreClock;
+}
+
+/**
+  * @brief  Returns the PCLK1 frequency
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
+}
+
+/**
+  * @brief  Returns the PCLK2 frequency
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK2 frequency
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+  * will be configured.
+  * @retval None
+  */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+  /* Get the HSE configuration -----------------------------------------------*/
+  if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+
+  /* Get the LSE configuration -----------------------------------------------*/
+  if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+  /* Get the PLL configuration -----------------------------------------------*/
+  if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> RCC_PLLCFGR_PLLP_Pos);
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
+#if defined (RCC_PLLCFGR_PLLR)
+  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
+#endif
+}
+
+/**
+  * @brief  Configures the RCC_ClkInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
+  * will be configured.
+  * @param  pFLatency Pointer on the Flash Latency.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+  /* Set all possible values for the Clock type parameter --------------------*/
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+  /* Get the HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+  * @brief This function handles the RCC CSS interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+  /* Check RCC CSSF flag  */
+  if (__HAL_RCC_GET_IT(RCC_IT_CSS))
+  {
+    /* RCC Clock Security System interrupt user callback */
+    HAL_RCC_CSSCallback();
+
+    /* Clear RCC CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+  }
+}
+
+/**
+  * @brief  RCC Clock Security System interrupt callback
+  * @retval None
+  */
+__weak void HAL_RCC_CSSCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RCC_CSSCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c
new file mode 100644
index 0000000..60b0a07
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c
@@ -0,0 +1,1773 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extension RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities RCC extension peripheral:
+  *           + Extended Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCCEx RCCEx
+  * @brief RCCEx HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Defines RCCEx Private Defines
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+
+/**
+  * @}
+  */
+
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+  * @{
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ *  @brief  Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+    [..]
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
+        the backup registers) and RCC_BDCR register will be set to their reset values.
+
+@endverbatim
+  * @{
+  */
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \
+    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || \
+    defined (STM32F750xx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0;
+  uint32_t tmpreg0 = 0;
+  uint32_t tmpreg1 = 0;
+  uint32_t plli2sused = 0;
+  uint32_t pllsaiused = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*----------------------------------- I2S configuration ----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
+
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
+
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1;
+    }
+  }
+
+  /*------------------------------------ SAI1 configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+    /* Configure SAI1 Clock source */
+    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
+    {
+      pllsaiused = 1;
+    }
+  }
+
+  /*------------------------------------ SAI2 configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+
+    /* Configure SAI2 Clock source */
+    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
+    {
+      pllsaiused = 1;
+    }
+  }
+
+  /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+  {
+      plli2sused = 1;
+  }
+
+  /*------------------------------------ RTC configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR1 |= PWR_CR1_DBP;
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait for Backup domain Write protection disable */
+    while((PWR->CR1 & PWR_CR1_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Reset the Backup domain only if the RTC Clock source selection is modified */
+    tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+
+    if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg0;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+
+  /*------------------------------------ TIM configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+
+  /*-------------------------------------- I2C1 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+    /* Configure the I2C1 clock source */
+    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+  }
+
+  /*-------------------------------------- I2C2 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+
+    /* Configure the I2C2 clock source */
+    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+  }
+
+  /*-------------------------------------- I2C3 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+
+    /* Configure the I2C3 clock source */
+    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+  }
+
+  /*-------------------------------------- I2C4 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+    /* Configure the I2C4 clock source */
+    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+  }
+
+  /*-------------------------------------- USART1 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+    /* Configure the USART1 clock source */
+    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+  }
+
+  /*-------------------------------------- USART2 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+
+    /* Configure the USART2 clock source */
+    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+  }
+
+  /*-------------------------------------- USART3 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+
+    /* Configure the USART3 clock source */
+    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+  }
+
+  /*-------------------------------------- UART4 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+
+    /* Configure the UART4 clock source */
+    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+  }
+
+  /*-------------------------------------- UART5 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+
+    /* Configure the UART5 clock source */
+    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+  }
+
+  /*-------------------------------------- USART6 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
+
+    /* Configure the USART6 clock source */
+    __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
+  }
+
+  /*-------------------------------------- UART7 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
+
+    /* Configure the UART7 clock source */
+    __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
+  }
+
+  /*-------------------------------------- UART8 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
+
+    /* Configure the UART8 clock source */
+    __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
+  }
+
+  /*--------------------------------------- CEC Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+    /* Configure the CEC clock source */
+    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+  }
+
+  /*-------------------------------------- CK48 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
+
+    /* Configure the CLK48 source */
+    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+
+    /* Enable the PLLSAI when it's used as clock source for CK48 */
+    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
+    {
+      pllsaiused = 1;
+    }
+  }
+
+  /*-------------------------------------- LTDC Configuration -----------------------------------*/
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+  {
+    pllsaiused = 1;
+  }
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+  /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
+
+    /* Configure the LTPIM1 clock source */
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+   }
+
+  /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
+
+    /* Configure the SDMMC1 clock source */
+    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
+  }
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+  /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
+
+    /* Configure the SDMMC2 clock source */
+    __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
+  }
+
+  /*------------------------------------- DFSDM1 Configuration -------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+  }
+
+  /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
+
+    /* Configure the DFSDM interface clock source */
+    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
+  }
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+  /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
+  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
+  if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* check for common PLLI2S Parameters */
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+    /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+      /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
+      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
+      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
+    {
+      /* Check for PLLI2S Parameters */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      /* Check for PLLI2S/DIVQ parameters */
+      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+      /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
+      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
+      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+    }
+
+    /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+
+     /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
+      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
+      /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
+    }
+
+    /*----------------- In Case of PLLI2S is just selected  -----------------*/
+    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+    {
+      /* Check for Parameters */
+      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
+      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
+  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
+  if(pllsaiused == 1)
+  {
+    /* Disable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLSAI is disabled */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Check the PLLSAI division factors */
+    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+    /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
+    {
+      /* check for PLLSAIQ Parameter */
+      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+      /* check for PLLSAI/DIVQ Parameter */
+      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+    }
+
+    /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
+    /* In Case of PLLI2S is selected as source clock for CK48 */
+    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+      /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
+      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+
+      /* Configure the PLLSAI division factors */
+      /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
+      /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
+    }
+
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+    /*---------------------------- LTDC configuration -------------------------------*/
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+    {
+      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+
+      /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
+      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
+
+      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+    }
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx  */
+
+    /* Enable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLSAI is ready */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
+  *         RCC configuration registers.
+  * @param  PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg = 0;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\
+                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
+                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
+                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\
+                                        RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\
+                                        RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\
+                                        RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\
+                                        RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\
+                                        RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\
+                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\
+                                        RCC_PERIPHCLK_CLK48    | RCC_PERIPHCLK_SDMMC2   |\
+                                        RCC_PERIPHCLK_DFSDM1   | RCC_PERIPHCLK_DFSDM1_AUDIO;
+#else
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\
+                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
+                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
+                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\
+                                        RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\
+                                        RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\
+                                        RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\
+                                        RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\
+                                        RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\
+                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\
+                                        RCC_PERIPHCLK_CLK48;
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+
+  /* Get the PLLSAI Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+
+  /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
+  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos);
+
+  /* Get the SAI1 clock configuration ----------------------------------------------*/
+  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+
+  /* Get the SAI2 clock configuration ----------------------------------------------*/
+  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+
+  /* Get the I2S clock configuration ------------------------------------------*/
+  PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
+
+  /* Get the I2C1 clock configuration ------------------------------------------*/
+  PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+
+  /* Get the I2C2 clock configuration ------------------------------------------*/
+  PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
+
+  /* Get the I2C3 clock configuration ------------------------------------------*/
+  PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
+
+  /* Get the I2C4 clock configuration ------------------------------------------*/
+  PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
+
+  /* Get the USART1 clock configuration ------------------------------------------*/
+  PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+
+  /* Get the USART2 clock configuration ------------------------------------------*/
+  PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
+
+  /* Get the USART3 clock configuration ------------------------------------------*/
+  PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
+
+  /* Get the UART4 clock configuration ------------------------------------------*/
+  PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
+
+  /* Get the UART5 clock configuration ------------------------------------------*/
+  PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
+
+  /* Get the USART6 clock configuration ------------------------------------------*/
+  PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
+
+  /* Get the UART7 clock configuration ------------------------------------------*/
+  PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
+
+  /* Get the UART8 clock configuration ------------------------------------------*/
+  PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
+
+  /* Get the LPTIM1 clock configuration ------------------------------------------*/
+  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+  /* Get the CEC clock configuration -----------------------------------------------*/
+  PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
+
+  /* Get the CK48 clock configuration -----------------------------------------------*/
+  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+  /* Get the SDMMC1 clock configuration -----------------------------------------------*/
+  PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+  /* Get the SDMMC2 clock configuration -----------------------------------------------*/
+  PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
+
+  /* Get the DFSDM clock configuration -----------------------------------------------*/
+  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
+
+  /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/
+  PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+  /* Get the RTC Clock configuration -----------------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+  /* Get the TIM Prescaler configuration --------------------------------------------*/
+  if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0;
+  uint32_t tmpreg0 = 0;
+  uint32_t plli2sused = 0;
+  uint32_t pllsaiused = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*----------------------------------- I2S configuration ----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
+
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
+
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1;
+    }
+  }
+
+  /*------------------------------------ SAI1 configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+    /* Configure SAI1 Clock source */
+    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
+    {
+      pllsaiused = 1;
+    }
+  }
+
+  /*------------------------------------ SAI2 configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+
+    /* Configure SAI2 Clock source */
+    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
+    {
+      pllsaiused = 1;
+    }
+  }
+
+  /*------------------------------------ RTC configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR1 |= PWR_CR1_DBP;
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait for Backup domain Write protection disable */
+    while((PWR->CR1 & PWR_CR1_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Reset the Backup domain only if the RTC Clock source selection is modified */
+    tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+
+    if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg0;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+
+  /*------------------------------------ TIM configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+
+  /*-------------------------------------- I2C1 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+    /* Configure the I2C1 clock source */
+    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+  }
+
+  /*-------------------------------------- I2C2 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+
+    /* Configure the I2C2 clock source */
+    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+  }
+
+  /*-------------------------------------- I2C3 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+
+    /* Configure the I2C3 clock source */
+    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+  }
+
+  /*-------------------------------------- USART1 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+    /* Configure the USART1 clock source */
+    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+  }
+
+  /*-------------------------------------- USART2 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+
+    /* Configure the USART2 clock source */
+    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+  }
+
+  /*-------------------------------------- USART3 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+
+    /* Configure the USART3 clock source */
+    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+  }
+
+  /*-------------------------------------- UART4 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+
+    /* Configure the UART4 clock source */
+    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+  }
+
+  /*-------------------------------------- UART5 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+
+    /* Configure the UART5 clock source */
+    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+  }
+
+  /*-------------------------------------- USART6 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
+
+    /* Configure the USART6 clock source */
+    __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
+  }
+
+  /*-------------------------------------- UART7 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
+
+    /* Configure the UART7 clock source */
+    __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
+  }
+
+  /*-------------------------------------- UART8 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
+
+    /* Configure the UART8 clock source */
+    __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
+  }
+
+  /*-------------------------------------- CK48 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
+
+    /* Configure the CLK48 source */
+    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+
+    /* Enable the PLLSAI when it's used as clock source for CK48 */
+    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
+    {
+      pllsaiused = 1;
+    }
+  }
+
+  /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
+
+    /* Configure the LTPIM1 clock source */
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+   }
+
+  /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
+
+    /* Configure the SDMMC1 clock source */
+    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
+  }
+
+  /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
+
+    /* Configure the SDMMC2 clock source */
+    __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
+  }
+
+  /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
+  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */
+  if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* check for common PLLI2S Parameters */
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+    /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+      /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
+      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
+    {
+      /* Check for PLLI2S Parameters */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      /* Check for PLLI2S/DIVQ parameters */
+      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+      /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
+      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0);
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+    }
+
+    /*----------------- In Case of PLLI2S is just selected  -----------------*/
+    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+    {
+      /* Check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
+  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
+  if(pllsaiused == 1)
+  {
+    /* Disable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLSAI is disabled */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Check the PLLSAI division factors */
+    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+    /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
+    {
+      /* check for PLLSAIQ Parameter */
+      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+      /* check for PLLSAI/DIVQ Parameter */
+      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ);
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+    }
+
+    /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
+    /* In Case of PLLI2S is selected as source clock for CK48 */
+    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+      /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
+      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+
+      /* Configure the PLLSAI division factors */
+      /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
+      /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0);
+    }
+
+    /* Enable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLSAI is ready */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
+  *         RCC configuration registers.
+  * @param  PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg = 0;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\
+                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
+                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
+                                        RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\
+                                        RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\
+                                        RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\
+                                        RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\
+                                        RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\
+                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\
+                                        RCC_PERIPHCLK_CLK48    | RCC_PERIPHCLK_SDMMC2;
+
+  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+
+  /* Get the PLLSAI Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+
+  /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
+  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos);
+
+  /* Get the SAI1 clock configuration ----------------------------------------------*/
+  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+
+  /* Get the SAI2 clock configuration ----------------------------------------------*/
+  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+
+  /* Get the I2S clock configuration ------------------------------------------*/
+  PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
+
+  /* Get the I2C1 clock configuration ------------------------------------------*/
+  PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+
+  /* Get the I2C2 clock configuration ------------------------------------------*/
+  PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
+
+  /* Get the I2C3 clock configuration ------------------------------------------*/
+  PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
+
+  /* Get the USART1 clock configuration ------------------------------------------*/
+  PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+
+  /* Get the USART2 clock configuration ------------------------------------------*/
+  PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
+
+  /* Get the USART3 clock configuration ------------------------------------------*/
+  PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
+
+  /* Get the UART4 clock configuration ------------------------------------------*/
+  PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
+
+  /* Get the UART5 clock configuration ------------------------------------------*/
+  PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
+
+  /* Get the USART6 clock configuration ------------------------------------------*/
+  PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
+
+  /* Get the UART7 clock configuration ------------------------------------------*/
+  PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
+
+  /* Get the UART8 clock configuration ------------------------------------------*/
+  PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
+
+  /* Get the LPTIM1 clock configuration ------------------------------------------*/
+  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+  /* Get the CK48 clock configuration -----------------------------------------------*/
+  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+  /* Get the SDMMC1 clock configuration -----------------------------------------------*/
+  PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
+
+  /* Get the SDMMC2 clock configuration -----------------------------------------------*/
+  PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
+
+  /* Get the RTC Clock configuration -----------------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+  /* Get the TIM Prescaler configuration --------------------------------------------*/
+  if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
+  *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  uint32_t tmpreg = 0;
+  /* This variable is used to store the SAI clock frequency (value in Hz) */
+  uint32_t frequency = 0;
+  /* This variable is used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0;
+  /* This variable is used to store the SAI clock source */
+  uint32_t saiclocksource = 0;
+
+  if (PeriphClk == RCC_PERIPHCLK_SAI1)
+  {
+    saiclocksource = RCC->DCKCFGR1;
+    saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
+    switch (saiclocksource)
+    {
+    case 0: /* PLLSAI is the clock source for SAI1 */
+      {
+        /* Configure the PLLSAI division factor */
+        /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+        {
+          /* In Case the PLL Source is HSI (Internal Clock) */
+          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+        }
+        else
+        {
+          /* In Case the PLL Source is HSE (External Clock) */
+          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+        }
+        /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+        /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+        tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
+        frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+
+        /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+        tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
+        frequency = frequency/(tmpreg);
+        break;
+      }
+    case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */
+      {
+        /* Configure the PLLI2S division factor */
+        /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+        {
+          /* In Case the PLL Source is HSI (Internal Clock) */
+          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+        }
+        else
+        {
+          /* In Case the PLL Source is HSE (External Clock) */
+          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+        }
+
+        /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+        /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+        tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
+        frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+
+        /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+        tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
+        frequency = frequency/(tmpreg);
+        break;
+      }
+    case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+        break;
+      }
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+    case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/
+      {
+        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+        {
+          /* In Case the main PLL Source is HSI */
+          frequency = HSI_VALUE;
+        }
+        else
+        {
+          /* In Case the main PLL Source is HSE */
+          frequency = HSE_VALUE;
+        }
+        break;
+      }
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+    default :
+      {
+        break;
+      }
+    }
+  }
+
+  if (PeriphClk == RCC_PERIPHCLK_SAI2)
+  {
+    saiclocksource = RCC->DCKCFGR1;
+    saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
+    switch (saiclocksource)
+    {
+    case 0: /* PLLSAI is the clock source for SAI*/
+      {
+        /* Configure the PLLSAI division factor */
+        /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+        {
+          /* In Case the PLL Source is HSI (Internal Clock) */
+          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+        }
+        else
+        {
+          /* In Case the PLL Source is HSE (External Clock) */
+          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+        }
+        /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+        /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+        tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
+        frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+
+        /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+        tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
+        frequency = frequency/(tmpreg);
+        break;
+      }
+    case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */
+      {
+        /* Configure the PLLI2S division factor */
+        /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+        {
+          /* In Case the PLL Source is HSI (Internal Clock) */
+          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+        }
+        else
+        {
+          /* In Case the PLL Source is HSE (External Clock) */
+          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+        }
+
+        /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+        /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+        tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
+        frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+
+        /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+        tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
+        frequency = frequency/(tmpreg);
+        break;
+      }
+    case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+        break;
+      }
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+    case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */
+      {
+        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+        {
+          /* In Case the main PLL Source is HSI */
+          frequency = HSI_VALUE;
+        }
+        else
+        {
+          /* In Case the main PLL Source is HSE */
+          frequency = HSE_VALUE;
+        }
+        break;
+      }
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+    default :
+      {
+        break;
+      }
+    }
+  }
+
+  return frequency;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+ *  @brief  Extended Clock management functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended clock management functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the
+    activation or deactivation of PLLI2S, PLLSAI.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable PLLI2S.
+  * @param  PLLI2SInit  pointer to an RCC_PLLI2SInitTypeDef structure that
+  *         contains the configuration information for the PLLI2S
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
+{
+  uint32_t tickstart;
+
+  /* Check for parameters */
+  assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));
+  assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));
+  assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+  assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+
+  /* Disable the PLLI2S */
+  __HAL_RCC_PLLI2S_DISABLE();
+
+  /* Wait till PLLI2S is disabled */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Configure the PLLI2S division factors */
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
+  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#else
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
+  /* I2SPCLK = PLLI2S_VCO / PLLI2SP */
+  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
+
+  /* Enable the PLLI2S */
+  __HAL_RCC_PLLI2S_ENABLE();
+
+  /* Wait till PLLI2S is ready */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+ return HAL_OK;
+}
+
+/**
+  * @brief  Disable PLLI2S.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
+{
+  uint32_t tickstart;
+
+  /* Disable the PLLI2S */
+  __HAL_RCC_PLLI2S_DISABLE();
+
+  /* Wait till PLLI2S is disabled */
+  tickstart = HAL_GetTick();
+  while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+  {
+    if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable PLLSAI.
+  * @param  PLLSAIInit  pointer to an RCC_PLLSAIInitTypeDef structure that
+  *         contains the configuration information for the PLLSAI
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit)
+{
+  uint32_t tickstart;
+
+  /* Check for parameters */
+  assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));
+  assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));
+  assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+  assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+  /* Disable the PLLSAI */
+  __HAL_RCC_PLLSAI_DISABLE();
+
+  /* Wait till PLLSAI is disabled */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Configure the PLLSAI division factors */
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
+  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
+  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ);
+#else
+  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
+  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
+                          PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
+
+  /* Enable the PLLSAI */
+  __HAL_RCC_PLLSAI_ENABLE();
+
+  /* Wait till PLLSAI is ready */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+ return HAL_OK;
+}
+
+/**
+  * @brief  Disable PLLSAI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
+{
+  uint32_t tickstart;
+
+  /* Disable the PLLSAI */
+  __HAL_RCC_PLLSAI_DISABLE();
+
+  /* Wait till PLLSAI is disabled */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+  {
+    if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c
new file mode 100644
index 0000000..4b9e95d
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c
@@ -0,0 +1,3224 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_sd.c
+  * @author  MCD Application Team
+  * @brief   SD card HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Secure Digital (SD) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver implements a high level communication layer for read and write from/to
+    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+    the user in HAL_SD_MspInit() function (MSP layer).
+    Basically, the MSP layer configuration should be the same as we provide in the
+    examples.
+    You can easily tailor this configuration according to hardware resources.
+
+  [..]
+    This driver is a generic layered driver for SDMMC memories which uses the HAL
+    SDMMC driver functions to interface with SD and uSD cards devices.
+    It is used as follows:
+
+    (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API:
+        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+        (##) SDMMC pins configuration for SD card
+            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+                  and according to your pin assignment;
+        (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
+             and HAL_SD_WriteBlocks_DMA() APIs).
+            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
+            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
+        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
+            (+++) Configure the SDMMC and DMA interrupt priorities using functions
+                  HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
+            (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+                  and __HAL_SD_DISABLE_IT() inside the communication process.
+            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+                  and __HAL_SD_CLEAR_IT()
+        (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
+             and HAL_SD_WriteBlocks_IT() APIs).
+            (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
+            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+                  and __HAL_SD_DISABLE_IT() inside the communication process.
+            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+                  and __HAL_SD_CLEAR_IT()
+    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+
+
+  *** SD Card Initialization and configuration ***
+  ================================================
+  [..]
+    To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+    SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
+    This function provide the following operations:
+
+    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
+        type (Standard Capacity or High Capacity). You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
+        The SD Card frequency (SDMMC_CK) is computed as follows:
+
+           SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
+
+        In initialization mode and according to the SD Card standard,
+        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+
+        This phase of initialization is done through SDMMC_Init() and
+        SDMMC_PowerState_ON() SDMMC low level APIs.
+
+    (#) Initialize the SD card. The API used is HAL_SD_InitCard().
+        This phase allows the card initialization and identification
+        and check the SD Card type (Standard Capacity or High Capacity)
+        The initialization flow is compatible with SD standard.
+
+        This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
+        of plug-off plug-in.
+
+    (#) Configure the SD Card Data transfer frequency. You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
+        In transfer mode and according to the SD Card standard, make sure that the
+        SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
+        To be able to use a frequency higher than 24MHz, you should use the SDMMC
+        peripheral in bypass mode. Refer to the corresponding reference manual
+        for more details.
+
+    (#) Select the corresponding SD Card according to the address read with the step 2.
+
+    (#) Configure the SD Card in wide bus mode: 4-bits data.
+
+  *** SD Card Read operation ***
+  ==============================
+  [..]
+    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+
+    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Rx interrupt event.
+
+    (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Rx interrupt event.
+
+  *** SD Card Write operation ***
+  ===============================
+  [..]
+    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+
+    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Tx interrupt event.
+
+    (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Tx interrupt event.
+
+  *** SD card status ***
+  ======================
+  [..]
+    (+) The SD Status contains status bits that are related to the SD Memory
+        Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
+
+  *** SD card information ***
+  ===========================
+  [..]
+    (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
+        It returns useful information about the SD card such as block size, card type,
+        block number ...
+
+  *** SD card CSD register ***
+  ============================
+    (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** SD card CID register ***
+  ============================
+    (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** SD HAL driver macros list ***
+  ==================================
+  [..]
+    Below the list of most used macros in SD HAL driver.
+
+    (+) __HAL_SD_ENABLE : Enable the SD device
+    (+) __HAL_SD_DISABLE : Disable the SD device
+    (+) __HAL_SD_DMA_ENABLE: Enable the SDMMC DMA transfer
+    (+) __HAL_SD_DMA_DISABLE: Disable the SDMMC DMA transfer
+    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
+    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
+    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
+    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
+
+    (@) You can refer to the SD HAL driver header file for more useful macros
+
+  *** Callback registration ***
+  =============================================
+  [..]
+    The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    Use Functions HAL_SD_RegisterCallback() to register a user callback,
+    it allows to register following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) MspInitCallback    : SD MspInit.
+      (+) MspDeInitCallback  : SD MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    Use function HAL_SD_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function. It allows to reset following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) MspInitCallback    : SD MspInit.
+      (+) MspDeInitCallback  : SD MspDeInit.
+    This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+    By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (surcharged) functions in the HAL_SD_Init
+    and  HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_SD_RegisterCallback before calling HAL_SD_DeInit
+    or HAL_SD_Init function.
+
+    When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (surcharged) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+#if defined(SDMMC1)
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SD
+  * @{
+  */
+
+#ifdef HAL_SD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup SD_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+  * @{
+  */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static void SD_PowerOFF(SD_HandleTypeDef *hsd);
+static void SD_Write_IT(SD_HandleTypeDef *hsd);
+static void SD_Read_IT(SD_HandleTypeDef *hsd);
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMAError(DMA_HandleTypeDef *hdma);
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma);
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SD_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SD_Exported_Functions_Group1
+ *  @brief   Initialization and de-initialization functions
+ *
+@verbatim
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize/de-initialize the SD
+    card device to be ready for use.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SD according to the specified parameters in the
+            SD_HandleTypeDef and create the associated handle.
+  * @param  hsd: Pointer to the SD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
+{
+  /* Check the SD handle allocation */
+  if(hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+  assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge));
+  assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
+
+  if(hsd->State == HAL_SD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsd->Lock = HAL_UNLOCKED;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+    /* Reset Callback pointers in HAL_SD_STATE_RESET only */
+    hsd->TxCpltCallback    = HAL_SD_TxCpltCallback;
+    hsd->RxCpltCallback    = HAL_SD_RxCpltCallback;
+    hsd->ErrorCallback     = HAL_SD_ErrorCallback;
+    hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+
+    if(hsd->MspInitCallback == NULL)
+    {
+      hsd->MspInitCallback = HAL_SD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hsd->MspInitCallback(hsd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_SD_MspInit(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+  }
+
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  /* Initialize the Card parameters */
+  if (HAL_SD_InitCard(hsd) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Initialize the error code */
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+  /* Initialize the SD operation */
+  hsd->Context = SD_CONTEXT_NONE;
+
+  /* Initialize the SD state */
+  hsd->State = HAL_SD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the SD Card.
+  * @param  hsd: Pointer to SD handle
+  * @note   This function initializes the SD card. It could be used when a card
+            re-initialization is needed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate;
+  HAL_StatusTypeDef status;
+  SD_InitTypeDef Init;
+  
+  /* Default SDMMC peripheral configuration for SD card initialization */
+  Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
+  Init.ClockBypass         = SDMMC_CLOCK_BYPASS_DISABLE;
+  Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  Init.BusWide             = SDMMC_BUS_WIDE_1B;
+  Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+  Init.ClockDiv            = SDMMC_INIT_CLK_DIV;
+
+  /* Initialize SDMMC peripheral interface with default configuration */
+  status = SDMMC_Init(hsd->Instance, Init);
+  if(status != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable SDMMC Clock */
+  __HAL_SD_DISABLE(hsd);
+
+  /* Set Power State to ON */
+  (void)SDMMC_PowerState_ON(hsd->Instance);
+
+  /* Enable SDMMC Clock */
+  __HAL_SD_ENABLE(hsd);
+
+  /* Required power up waiting time before starting the SD initialization  sequence */
+  HAL_Delay(2);
+
+  /* Identify card operating voltage */
+  errorstate = SD_PowerON(hsd);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  /* Card initialization */
+  errorstate = SD_InitCard(hsd);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initializes the SD card.
+  * @param  hsd: Pointer to SD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
+{
+  /* Check the SD handle allocation */
+  if(hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  /* Set SD power state to off */
+  SD_PowerOFF(hsd);
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+  if(hsd->MspDeInitCallback == NULL)
+  {
+    hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsd->MspDeInitCallback(hsd);
+#else
+  /* De-Initialize the MSP layer */
+  HAL_SD_MspDeInit(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+  hsd->State = HAL_SD_STATE_RESET;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initializes the SD MSP.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize SD MSP.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup SD_Exported_Functions_Group2
+ *  @brief   Data transfer functions
+ *
+@verbatim
+  ==============================================================================
+                        ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the data
+    transfer from/to SD card.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of SD blocks to read
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count, data, dataremaining;
+  uint32_t add = BlockAdd;
+  uint8_t *tempbuff = pData;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_ENABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    /* Read block(s) in polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Poll on SDMMC flags */
+    dataremaining = config.DataLength;
+    while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for(count = 0U; count < 8U; count++)
+        {
+          data = SDMMC_ReadFIFO(hsd->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          dataremaining--;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          dataremaining--;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          dataremaining--;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+          dataremaining--;
+        }
+      }
+
+      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+        hsd->State= HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Send stop transmission command in case of multiblock read */
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    {
+      if(hsd->SdCard.CardType != CARD_SECURED)
+      {
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          hsd->Context = SD_CONTEXT_NONE;
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Get error state */
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Empty FIFO if there is still any data */
+    while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U))
+    {
+      data = SDMMC_ReadFIFO(hsd->Instance);
+      *tempbuff = (uint8_t)(data & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+      *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+      *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+      *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+
+      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+        hsd->State= HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Allows to write block(s) to a specified address in a card. The Data
+  *         transfer is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of SD blocks to write
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count, data, dataremaining;
+  uint32_t add = BlockAdd;
+  uint8_t *tempbuff = pData;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_ENABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Write block(s) in polling mode */
+    dataremaining = config.DataLength;
+    while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U))
+      {
+        /* Write data to SDMMC Tx FIFO */
+        for(count = 0U; count < 8U; count++)
+        {
+          data = (uint32_t)(*tempbuff);
+          tempbuff++;
+          dataremaining--;
+          data |= ((uint32_t)(*tempbuff) << 8U);
+          tempbuff++;
+          dataremaining--;
+          data |= ((uint32_t)(*tempbuff) << 16U);
+          tempbuff++;
+          dataremaining--;
+          data |= ((uint32_t)(*tempbuff) << 24U);
+          tempbuff++;
+          dataremaining--;
+          (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+        }
+      }
+
+      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Send stop transmission command in case of multiblock write */
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    {
+      if(hsd->SdCard.CardType != CARD_SECURED)
+      {
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          hsd->Context = SD_CONTEXT_NONE;
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Get error state */
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Rx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pRxBuffPtr = pData;
+    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_ENABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    /* Read Blocks in IT mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Tx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pTxBuffPtr = pData;
+    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    /* Enable transfer interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_ENABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Rx
+  *         interrupt event.
+  * @param  hsd: Pointer SD handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+
+    /* Set the DMA transfer complete callback */
+    hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
+
+    /* Set the DMA error callback */
+    hsd->hdmarx->XferErrorCallback = SD_DMAError;
+
+    /* Set the DMA Abort callback */
+    hsd->hdmarx->XferAbortCallback = NULL;
+
+    /* Force DMA Direction */
+    hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
+    MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction);
+
+    /* Enable the DMA Channel */
+    if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
+    {
+      __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Enable SD DMA transfer */
+      __HAL_SD_DMA_ENABLE(hsd);
+
+      if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+      {
+        add *= 512U;
+      }
+
+      /* Configure the SD DPSM (Data Path State Machine) */
+      config.DataTimeOut   = SDMMC_DATATIMEOUT;
+      config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+      config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+      config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+      config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+      config.DPSM          = SDMMC_DPSM_ENABLE;
+      (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+      /* Read Blocks in DMA mode */
+      if(NumberOfBlocks > 1U)
+      {
+        hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+        /* Read Multi Block command */
+        errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+      }
+      else
+      {
+        hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+        /* Read Single Block command */
+        errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+      }
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Tx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    /* Enable SD Error interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR));   
+
+    /* Set the DMA transfer complete callback */
+    hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
+
+    /* Set the DMA error callback */
+    hsd->hdmatx->XferErrorCallback = SD_DMAError;
+
+    /* Set the DMA Abort callback */
+    hsd->hdmatx->XferAbortCallback = NULL;
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Enable SDMMC DMA transfer */
+    __HAL_SD_DMA_ENABLE(hsd);
+
+    /* Force DMA Direction */
+    hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
+    MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction);
+
+    /* Enable the DMA Channel */
+    if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
+    {
+      __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR));   
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Configure the SD DPSM (Data Path State Machine) */
+      config.DataTimeOut   = SDMMC_DATATIMEOUT;
+      config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+      config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+      config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+      config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+      config.DPSM          = SDMMC_DPSM_ENABLE;
+      (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Erases the specified memory area of the given SD card.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  BlockStartAdd: Start Block address
+  * @param  BlockEndAdd: End Block address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+  uint32_t errorstate;
+  uint32_t start_add = BlockStartAdd;
+  uint32_t end_add = BlockEndAdd;
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if(end_add < start_add)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+      return HAL_ERROR;
+    }
+
+    if(end_add > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Check if the card command class supports erase command */
+    if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Get start and end block for high capacity cards */
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      start_add *= 512U;
+      end_add   *= 512U;
+    }
+
+    /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+    if(hsd->SdCard.CardType != CARD_SECURED)
+    {
+      /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+
+      /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+    }
+
+    /* Send CMD38 ERASE */
+    errorstate = SDMMC_CmdErase(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  This function handles SD card interrupt request.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate;
+  uint32_t context = hsd->Context;
+
+  /* Check for SDMMC interrupt flags */
+  if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+  {
+    SD_Read_IT(hsd);
+  }
+
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
+
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND  | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+                             SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR  | SDMMC_IT_TXFIFOHE |\
+                             SDMMC_IT_RXFIFOHF);
+
+    hsd->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN);
+    
+    if((context & SD_CONTEXT_IT) != 0U)
+    {
+      if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->ErrorCallback(hsd);
+#else
+          HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->RxCpltCallback(hsd);
+#else
+        HAL_SD_RxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->TxCpltCallback(hsd);
+#else
+        HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else if((context & SD_CONTEXT_DMA) != 0U)
+    {
+      if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->ErrorCallback(hsd);
+#else
+          HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+        }
+      }
+      if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
+      {
+        /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+        in the SD DCTRL register */
+        hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+
+        hsd->State = HAL_SD_STATE_READY;
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->TxCpltCallback(hsd);
+#else
+        HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+  {
+    SD_Write_IT(hsd);
+  }
+
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
+  {
+    /* Set Error code */
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+    }
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+    }
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+    }
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+    }
+
+    /* Clear All flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    /* Disable all interrupts */
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+                             SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+
+    if((context & SD_CONTEXT_IT) != 0U)
+    {
+      /* Set the SD state to ready to be able to start again the process */
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->ErrorCallback(hsd);
+#else
+      HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+    }
+    else if((context & SD_CONTEXT_DMA) != 0U)
+    {
+      /* Abort the SD DMA channel */
+      if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        /* Set the DMA Tx abort callback */
+        hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+        /* Abort DMA in IT mode */
+        if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+        {
+          SD_DMATxAbort(hsd->hdmatx);
+        }
+      }
+      else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+        /* Set the DMA Rx abort callback */
+        hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+        /* Abort DMA in IT mode */
+        if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+        {
+          SD_DMARxAbort(hsd->hdmarx);
+        }
+      }
+      else
+      {
+        hsd->ErrorCode = HAL_SD_ERROR_NONE;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->AbortCpltCallback(hsd);
+#else
+        HAL_SD_AbortCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief return the SD state
+  * @param hsd: Pointer to sd handle
+  * @retval HAL state
+  */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
+{
+  return hsd->State;
+}
+
+/**
+* @brief  Return the SD error code
+* @param  hsd : Pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+* @retval SD Error Code
+*/
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
+{
+  return hsd->ErrorCode;
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_TxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_RxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SD error callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_ErrorCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SD Abort callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_AbortCallback can be implemented in the user file
+   */
+}
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User SD Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hsd : SD handle
+  * @param CallbackID : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID
+  *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID
+  *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID
+  *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID
+  *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID
+  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(pCallback == NULL)
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hsd);
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+    case HAL_SD_TX_CPLT_CB_ID :
+      hsd->TxCpltCallback = pCallback;
+      break;
+    case HAL_SD_RX_CPLT_CB_ID :
+      hsd->RxCpltCallback = pCallback;
+      break;
+    case HAL_SD_ERROR_CB_ID :
+      hsd->ErrorCallback = pCallback;
+      break;
+    case HAL_SD_ABORT_CB_ID :
+      hsd->AbortCpltCallback = pCallback;
+      break;
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = pCallback;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if (hsd->State == HAL_SD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = pCallback;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsd);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SD Callback
+  *         SD Callback is redirected to the weak (surcharged) predefined callback
+  * @param hsd : SD handle
+  * @param CallbackID : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID
+  *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID
+  *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID
+  *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID
+  *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID
+  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hsd);
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+    case HAL_SD_TX_CPLT_CB_ID :
+      hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+      break;
+    case HAL_SD_RX_CPLT_CB_ID :
+      hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+      break;
+    case HAL_SD_ERROR_CB_ID :
+      hsd->ErrorCallback = HAL_SD_ErrorCallback;
+      break;
+    case HAL_SD_ABORT_CB_ID :
+      hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+      break;
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = HAL_SD_MspInit;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if (hsd->State == HAL_SD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = HAL_SD_MspInit;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsd);
+  return status;
+}
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SD_Exported_Functions_Group3
+ *  @brief   management functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the SD card
+    operations and get the related information
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CID register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that  
+  *         contains all CID register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
+{
+  pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
+
+  pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
+
+  pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
+
+  pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
+
+  pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
+
+  pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
+
+  pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
+
+  pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
+
+  pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
+
+  pCID->Reserved2 = 1U;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CSD register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that  
+  *         contains all CSD register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
+{
+  pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
+
+  pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
+
+  pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
+
+  pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
+
+  pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
+
+  pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
+
+  pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
+
+  pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
+
+  pCSD->PartBlockRead   = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
+
+  pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
+
+  pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
+
+  pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
+
+  pCSD->Reserved2 = 0U; /*!< Reserved */
+
+  if(hsd->SdCard.CardType == CARD_SDSC)
+  {
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
+
+    pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
+
+    pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
+
+    pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
+
+    pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
+
+    pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
+
+    hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
+    hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+    hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+    hsd->SdCard.LogBlockNbr =  (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+    hsd->SdCard.LogBlockSize = 512U;
+  }
+  else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
+  {
+    /* Byte 7 */
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
+
+    hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
+    hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+    hsd->SdCard.BlockSize = 512U;
+    hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+
+  pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
+
+  pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
+
+  pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
+
+  pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
+
+  pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
+
+  pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
+
+  pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+
+  pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
+
+  pCSD->Reserved3 = 0;
+
+  pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
+
+  pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
+
+  pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
+
+  pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
+
+  pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
+
+  pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
+
+  pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+
+  pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
+
+  pCSD->Reserved4 = 1;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the SD status info.
+  * @param  hsd: Pointer to SD handle
+  * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that 
+  *         will contain the SD card status information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
+{
+  uint32_t sd_status[16];
+  uint32_t errorstate;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  errorstate = SD_SendSDStatus(hsd, sd_status);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
+
+    pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
+
+    pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
+
+    pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) << 8U) |
+                                  ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
+
+    pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
+
+    pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
+
+    pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
+
+    pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
+
+    pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
+
+    pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode = errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Gets the SD card info.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+  *         will contain the SD card status information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
+{
+  pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
+  pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
+  pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
+  pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
+  pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
+  pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
+  pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
+  pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables wide bus operation for the requested card if supported by
+  *         card.
+  * @param  hsd: Pointer to SD handle
+  * @param  WideMode: Specifies the SD card wide bus mode
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
+{
+  SDMMC_InitTypeDef Init;
+  uint32_t errorstate;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_BUS_WIDE(WideMode));
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  if(hsd->SdCard.CardType != CARD_SECURED)
+  {
+    if(WideMode == SDMMC_BUS_WIDE_8B)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+    else if(WideMode == SDMMC_BUS_WIDE_4B)
+    {
+      errorstate = SD_WideBus_Enable(hsd);
+
+      hsd->ErrorCode |= errorstate;
+    }
+    else if(WideMode == SDMMC_BUS_WIDE_1B)
+    {
+      errorstate = SD_WideBus_Disable(hsd);
+
+      hsd->ErrorCode |= errorstate;
+    }
+    else
+    {
+      /* WideMode is not a valid argument*/
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    }
+  }
+  else
+  {
+    /* MMC Card does not support this feature */
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+  }
+
+  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->State = HAL_SD_STATE_READY;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Configure the SDMMC peripheral */
+    Init.ClockEdge           = hsd->Init.ClockEdge;
+    Init.ClockBypass         = hsd->Init.ClockBypass;
+    Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
+    Init.BusWide             = WideMode;
+    Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+    Init.ClockDiv            = hsd->Init.ClockDiv;
+    (void)SDMMC_Init(hsd->Instance, Init);
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    status = HAL_ERROR;
+  }
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_READY;
+
+  return status;
+}
+
+/**
+  * @brief  Gets the current sd card data state.
+  * @param  hsd: pointer to SD handle
+  * @retval Card state
+  */
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
+{
+  uint32_t cardstate;
+  uint32_t errorstate;
+  uint32_t resp1 = 0;
+
+  errorstate = SD_SendStatus(hsd, &resp1);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= errorstate;
+  }
+
+  cardstate = ((resp1 >> 9U) & 0x0FU);
+
+  return (HAL_SD_CardStateTypeDef)cardstate;
+}
+
+/**
+  * @brief  Abort the current transfer and disable the SD.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStateTypeDef CardState;
+  uint32_t context = hsd->Context;
+
+  /* DIsable All interrupts */
+  __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+                           SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+  CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN);
+
+  if ((context & SD_CONTEXT_DMA) != 0U)
+  {
+    /* Disable the SD DMA request */
+    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+
+    /* Abort the SD DMA Tx channel */
+    if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+    {
+      if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK)
+      {
+        hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      }
+    }
+    /* Abort the SD DMA Rx channel */
+    else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+    {
+      if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK)
+      {
+        hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  hsd->State = HAL_SD_STATE_READY;
+
+  /* Initialize the SD operation */
+  hsd->Context = SD_CONTEXT_NONE;
+
+  CardState = HAL_SD_GetCardState(hsd);
+  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+  {
+    hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+  }
+  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the current transfer and disable the SD (IT mode).
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStateTypeDef CardState;
+  uint32_t context = hsd->Context;
+
+  /* Disable All interrupts */
+  __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+                           SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+
+  CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN);
+
+  if ((context & SD_CONTEXT_DMA) != 0U)
+  {
+    /* Disable the SD DMA request */
+    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+
+    /* Abort the SD DMA Tx channel */
+    if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+    {
+      hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+      if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+      {
+        hsd->hdmatx = NULL;
+      }
+    }
+    /* Abort the SD DMA Rx channel */
+    else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+    {
+      hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+      if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+      {
+        hsd->hdmarx = NULL;
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  /* No transfer ongoing on both DMA channels*/
+  else
+  {
+    /* Clear All flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    CardState = HAL_SD_GetCardState(hsd);
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->Context = SD_CONTEXT_NONE;
+    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+    {
+      hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+    }
+    if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->AbortCpltCallback(hsd);
+#else
+      HAL_SD_AbortCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  DMA SD transmit process complete callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+
+  /* Enable DATAEND Interrupt */
+  __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DATAEND));
+}
+
+/**
+  * @brief  DMA SD receive process complete callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  uint32_t errorstate;
+
+  /* Send stop command in multiblock write */
+  if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
+  {
+    errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      hsd->ErrorCode |= errorstate;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+      hsd->ErrorCallback(hsd);
+#else
+      HAL_SD_ErrorCallback(hsd);
+#endif
+    }
+  }
+
+  /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+  in the SD DCTRL register */
+  hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+
+  /* Clear all the static flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+  hsd->State = HAL_SD_STATE_READY;
+  hsd->Context = SD_CONTEXT_NONE;
+
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+  hsd->RxCpltCallback(hsd);
+#else
+  HAL_SD_RxCpltCallback(hsd);
+#endif
+}
+
+/**
+  * @brief  DMA SD communication error callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypeDef CardState;
+  uint32_t RxErrorCode, TxErrorCode;
+
+  /* if DMA error is FIFO error ignore it */
+  if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+  {
+    RxErrorCode = hsd->hdmarx->ErrorCode;
+    TxErrorCode = hsd->hdmatx->ErrorCode;  
+    if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
+    {
+      /* Clear All flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+
+      /* Disable All interrupts */
+      __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+        SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+
+      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      CardState = HAL_SD_GetCardState(hsd);
+      if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+      {
+        hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+      }
+
+      hsd->State= HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+    }
+
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->ErrorCallback(hsd);
+#else
+    HAL_SD_ErrorCallback(hsd);
+#endif
+  }
+}
+
+/**
+  * @brief  DMA SD Tx Abort callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypeDef CardState;
+
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+  CardState = HAL_SD_GetCardState(hsd);
+  hsd->State = HAL_SD_STATE_READY;
+  hsd->Context = SD_CONTEXT_NONE;
+  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+  {
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+  }
+
+  if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
+  {
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->AbortCpltCallback(hsd);
+#else
+    HAL_SD_AbortCallback(hsd);
+#endif
+  }
+  else
+  {
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->ErrorCallback(hsd);
+#else
+    HAL_SD_ErrorCallback(hsd);
+#endif
+  }
+}
+
+/**
+  * @brief  DMA SD Rx Abort callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypeDef CardState;
+
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+  CardState = HAL_SD_GetCardState(hsd);
+  hsd->State = HAL_SD_STATE_READY;
+  hsd->Context = SD_CONTEXT_NONE;
+  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+  {
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+  }
+
+  if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
+  {
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->AbortCpltCallback(hsd);
+#else
+    HAL_SD_AbortCallback(hsd);
+#endif
+  }
+  else
+  {
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->ErrorCallback(hsd);
+#else
+    HAL_SD_ErrorCallback(hsd);
+#endif
+  }
+}
+
+/**
+  * @brief  Initializes the sd card.
+  * @param  hsd: Pointer to SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardCSDTypeDef CSD;
+  uint32_t errorstate;
+  uint16_t sd_rca = 1U;
+
+  /* Check the power State */
+  if(SDMMC_GetPowerState(hsd->Instance) == 0U)
+  {
+    /* Power off */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+
+  if(hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Send CMD2 ALL_SEND_CID */
+    errorstate = SDMMC_CmdSendCID(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card identification number data */
+      hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+      hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+      hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+      hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+    }
+  }
+
+  if(hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Send CMD3 SET_REL_ADDR with argument 0 */
+    /* SD Card publishes its RCA. */
+    errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+  }
+  if(hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Get the SD card RCA */
+    hsd->SdCard.RelCardAdd = sd_rca;
+
+    /* Send CMD9 SEND_CSD with argument as card's RCA */
+    errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card Specific Data */
+      hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+      hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+      hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+      hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+    }
+  }
+
+  /* Get the Card Class */
+  hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U);
+
+  /* Get CSD parameters */
+  if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
+  {
+    return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+  }
+
+  /* Select the Card */
+  errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Configure SDMMC peripheral interface */
+  (void)SDMMC_Init(hsd->Instance, hsd->Init);
+
+  /* All cards are initialized */
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Enquires cards about their operating voltage and configures clock
+  *         controls and stores SD information that will be needed in future
+  *         in the SD handle.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
+{
+  __IO uint32_t count = 0U;
+  uint32_t response = 0U, validvoltage = 0U;
+  uint32_t errorstate;
+
+  /* CMD0: GO_IDLE_STATE */
+  errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
+  errorstate = SDMMC_CmdOperCond(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->SdCard.CardVersion = CARD_V1_X;
+    /* CMD0: GO_IDLE_STATE */
+    errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+  }
+  else
+  {
+    hsd->SdCard.CardVersion = CARD_V2_X;
+  }
+
+  if( hsd->SdCard.CardVersion == CARD_V2_X)
+  {
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+  }
+  /* SD CARD */
+  /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+  while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+  {
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send CMD41 */
+    errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+
+    /* Get command response */
+    response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+
+    /* Get operating voltage*/
+    validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+
+    count++;
+  }
+
+  if(count >= SDMMC_MAX_VOLT_TRIAL)
+  {
+    return HAL_SD_ERROR_INVALID_VOLTRANGE;
+  }
+
+  if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+  {
+    hsd->SdCard.CardType = CARD_SDHC_SDXC;
+  }
+  else
+  {
+    hsd->SdCard.CardType = CARD_SDSC;
+  }
+
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Turns the SDMMC output signals off.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+static void SD_PowerOFF(SD_HandleTypeDef *hsd)
+{
+  /* Set Power State to OFF */
+  (void)SDMMC_PowerState_OFF(hsd->Instance);
+}
+
+/**
+  * @brief  Send Status info command.
+  * @param  hsd: pointer to SD handle
+  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
+  *         SD Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t *pData = pSDstatus;
+
+  /* Check SD response */
+  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Set block size for card if it is not equal to current block size for card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Send CMD55 */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Configure the SD DPSM (Data Path State Machine) */
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 64U;
+  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDMMC_DPSM_ENABLE;
+  (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
+  errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Get status data */
+  while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
+  {
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+    {
+      for(count = 0U; count < 8U; count++)
+      {
+        *pData = SDMMC_ReadFIFO(hsd->Instance);
+        pData++;
+      }
+    }
+
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+  {
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+  {
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+  {
+    return HAL_SD_ERROR_RX_OVERRUN;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)))
+  {
+    *pData = SDMMC_ReadFIFO(hsd->Instance);
+    pData++;
+
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  /* Clear all the static status flags*/
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Returns the current card's status.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCardStatus: pointer to the buffer that will contain the SD card
+  *         status (Card Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+{
+  uint32_t errorstate;
+
+  if(pCardStatus == NULL)
+  {
+    return HAL_SD_ERROR_PARAM;
+  }
+
+  /* Send Status command */
+  errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Get SD card status */
+  *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Enables the SDMMC wide bus mode.
+  * @param  hsd: pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+{
+  uint32_t scr[2U] = {0U, 0U};
+  uint32_t errorstate;
+
+  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* If requested card supports wide bus operation */
+  if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA.*/
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    return HAL_SD_ERROR_NONE;
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+}
+
+/**
+  * @brief  Disables the SDMMC wide bus mode.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+{
+  uint32_t scr[2U] = {0U, 0U};
+  uint32_t errorstate;
+
+  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* If requested card supports 1 bit mode operation */
+  if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    return HAL_SD_ERROR_NONE;
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+}
+
+
+/**
+  * @brief  Finds the SD card SCR register value.
+  * @param  hsd: Pointer to SD handle
+  * @param  pSCR: pointer to the buffer that will contain the SCR value
+  * @retval error state
+  */
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t index = 0U;
+  uint32_t tempscr[2U] = {0U, 0U};
+  uint32_t *scr = pSCR;
+
+  /* Set Block Size To 8 Bytes */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Send CMD55 APP_CMD with argument as card's RCA */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 8U;
+  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDMMC_DPSM_ENABLE;
+  (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+  errorstate = SDMMC_CmdSendSCR(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT))
+  {
+    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))
+    {
+      *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);
+      index++;
+    }
+    else if(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXACT))
+    {
+      break;
+    }
+
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+    return HAL_SD_ERROR_RX_OVERRUN;
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
+            ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+    scr++;
+    *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
+            ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+
+  }
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Wrap up reading in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void SD_Read_IT(SD_HandleTypeDef *hsd)
+{
+  uint32_t count, data, dataremaining;
+  uint8_t* tmp;
+
+  tmp = hsd->pRxBuffPtr;
+  dataremaining = hsd->RxXferSize;
+
+  if (dataremaining > 0U)
+  {
+    /* Read data from SDMMC Rx FIFO */
+    for(count = 0U; count < 8U; count++)
+    {
+      data = SDMMC_ReadFIFO(hsd->Instance);
+      *tmp = (uint8_t)(data & 0xFFU);
+      tmp++;
+      dataremaining--;
+      *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+      tmp++;
+      dataremaining--;
+      *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+      tmp++;
+      dataremaining--;
+      *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+      tmp++;
+      dataremaining--;
+    }
+
+    hsd->pRxBuffPtr = tmp;
+    hsd->RxXferSize = dataremaining;
+  }
+}
+
+/**
+  * @brief  Wrap up writing in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void SD_Write_IT(SD_HandleTypeDef *hsd)
+{
+  uint32_t count, data, dataremaining;
+  uint8_t* tmp;
+
+  tmp = hsd->pTxBuffPtr;
+  dataremaining = hsd->TxXferSize;
+
+  if (dataremaining > 0U)
+  {
+    /* Write data to SDMMC Tx FIFO */
+    for(count = 0U; count < 8U; count++)
+    {
+      data = (uint32_t)(*tmp);
+      tmp++;
+      dataremaining--;
+      data |= ((uint32_t)(*tmp) << 8U);
+      tmp++;
+      dataremaining--;
+      data |= ((uint32_t)(*tmp) << 16U);
+      tmp++;
+      dataremaining--;
+      data |= ((uint32_t)(*tmp) << 24U);
+      tmp++;
+      dataremaining--;
+      (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+    }
+
+    hsd->pTxBuffPtr = tmp;
+    hsd->TxXferSize = dataremaining;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* SDMMC1 */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c
new file mode 100644
index 0000000..380ce78
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c
@@ -0,0 +1,7897 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + TIM Time Base Initialization
+  *           + TIM Time Base Start
+  *           + TIM Time Base Start Interruption
+  *           + TIM Time Base Start DMA
+  *           + TIM Output Compare/PWM Initialization
+  *           + TIM Output Compare/PWM Channel Configuration
+  *           + TIM Output Compare/PWM  Start
+  *           + TIM Output Compare/PWM  Start Interruption
+  *           + TIM Output Compare/PWM Start DMA
+  *           + TIM Input Capture Initialization
+  *           + TIM Input Capture Channel Configuration
+  *           + TIM Input Capture Start
+  *           + TIM Input Capture Start Interruption
+  *           + TIM Input Capture Start DMA
+  *           + TIM One Pulse Initialization
+  *           + TIM One Pulse Channel Configuration
+  *           + TIM One Pulse Start
+  *           + TIM Encoder Interface Initialization
+  *           + TIM Encoder Interface Start
+  *           + TIM Encoder Interface Start Interruption
+  *           + TIM Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + TIM OCRef clear configuration
+  *           + TIM External Clock configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include:
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output
+       (#) Synchronization circuit to control the timer with external signals and to interconnect
+            several timers together.
+       (#) Supports incremental encoder for positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+            Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+            in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+
+    *** Callback registration ***
+  =============================================
+
+  [..]
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+
+  [..]
+  Use Function HAL_TIM_RegisterCallback() to register a callback.
+  HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+
+  [..]
+  Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+
+  [..]
+  These functions allow to register/unregister following callbacks:
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+    (+) TriggerCallback                   : TIM Trigger Callback.
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+    (+) ErrorCallback                     : TIM Error Callback.
+    (+) CommutationCallback               : TIM Commutation Callback.
+    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+    (+) BreakCallback                     : TIM Break Callback.
+    (+) Break2Callback                    : TIM Break2 Callback.
+
+  [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+  examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init / DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+  [..]
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+    Exception done MspInit / MspDeInit that can be registered / unregistered
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available and all callbacks
+      are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM TIM
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+  * @{
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  const TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief    Time Base functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base.
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Base_MspInitCallback == NULL)
+    {
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Base peripheral
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Base_MspDeInitCallback == NULL)
+  {
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Base_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the DMA Period elapsed callbacks */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream */
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+                       Length) != HAL_OK)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief    TIM Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### TIM Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare.
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the TIM Output Compare.
+    (+) Stop the TIM Output Compare.
+    (+) Start the TIM Output Compare and enable interrupt.
+    (+) Stop the TIM Output Compare and disable interrupt.
+    (+) Start the TIM Output Compare and enable DMA transfer.
+    (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OC_MspInitCallback == NULL)
+    {
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OC_MspDeInitCallback == NULL)
+  {
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                       uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief    TIM PWM functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM PWM.
+    (+) De-initialize the TIM PWM.
+    (+) Start the TIM PWM.
+    (+) Stop the TIM PWM.
+    (+) Start the TIM PWM and enable interrupt.
+    (+) Stop the TIM PWM and disable interrupt.
+    (+) Start the TIM PWM and enable DMA transfer.
+    (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->PWM_MspInitCallback == NULL)
+    {
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->PWM_MspDeInitCallback == NULL)
+  {
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->PWM_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                        uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief    TIM Input Capture functions
+  *
+@verbatim
+  ==============================================================================
+              ##### TIM Input Capture functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture.
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the TIM Input Capture.
+   (+) Stop the TIM Input Capture.
+   (+) Start the TIM Input Capture and enable interrupt.
+   (+) Stop the TIM Input Capture and disable interrupt.
+   (+) Start the TIM Input Capture and enable DMA transfer.
+   (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->IC_MspInitCallback == NULL)
+    {
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->IC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->IC_MspDeInitCallback == NULL)
+  {
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->IC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture MSP.
+  * @param  htim TIM Input Capture handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Input Capture MSP.
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel state */
+  if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+      || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+  {
+    return HAL_BUSY;
+  }
+  else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+           && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief    TIM One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse.
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the TIM One Pulse.
+    (+) Stop the TIM One Pulse.
+    (+) Start the TIM One Pulse and enable interrupt.
+    (+) Stop the TIM One Pulse and disable interrupt.
+    (+) Start the TIM One Pulse and enable DMA transfer.
+    (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+  * @note   When the timer instance is initialized in One Pulse mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM One Pulse handle
+  * @param  OnePulseMode Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OnePulse_MspInitCallback == NULL)
+    {
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OnePulse_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM One Pulse
+  * @param  htim TIM One Pulse handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OnePulse_MspDeInitCallback == NULL)
+  {
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OnePulse_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief    TIM Encoder functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder.
+    (+) De-initialize the TIM Encoder.
+    (+) Start the TIM Encoder.
+    (+) Stop the TIM Encoder.
+    (+) Start the TIM Encoder and enable interrupt.
+    (+) Stop the TIM Encoder and disable interrupt.
+    (+) Start the TIM Encoder and enable DMA transfer.
+    (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+  * @note   When the timer instance is initialized in Encoder mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Encoder_MspInitCallback == NULL)
+    {
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the TIM Encoder interface
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Encoder_MspDeInitCallback == NULL)
+  {
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Encoder_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((pData1 == NULL) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((pData2 == NULL) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    default:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief    TIM IRQ handler management
+  *
+@verbatim
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================
+  [..]
+    This section provides Timer IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  uint32_t itsource = htim->Instance->DIER;
+  uint32_t itflag   = htim->Instance->SR;
+
+  /* Capture compare 1 event */
+  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
+  {
+    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
+    {
+      {
+        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        /* Output compare event */
+        else
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
+  {
+    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
+  {
+    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
+  {
+    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
+  {
+    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break input event */
+  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
+      ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
+  {
+    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
+      HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break2 input event */
+  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
+  {
+    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->Break2Callback(htim);
+#else
+      HAL_TIMEx_Break2Callback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
+  {
+    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM commutation event */
+  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
+  {
+    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief    TIM Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           const TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 4 in Output Compare */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 5 in Output Compare */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 6 in Output Compare */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+    TIM_TI2_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+    TIM_TI3_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_4)
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+    TIM_TI4_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM PWM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be configured
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            const TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 5 in PWM mode */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel5*/
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 6 in PWM mode */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel6 */
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM output channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel TIM input Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @note  To output a waveform with a minimum delay user can enable the fast
+  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+  *        output is forced in response to the edge detection on TIx input,
+  *        without taking in account the comparison.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  TIM_OC_InitTypeDef temp1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if (OutputChannel != InputChannel)
+  {
+    /* Process Locked */
+    __HAL_LOCK(htim);
+
+    htim->State = HAL_TIM_STATE_BUSY;
+
+    /* Extract the Output compare configuration from sConfig structure */
+    temp1.OCMode = sConfig->OCMode;
+    temp1.Pulse = sConfig->Pulse;
+    temp1.OCPolarity = sConfig->OCPolarity;
+    temp1.OCNPolarity = sConfig->OCNPolarity;
+    temp1.OCIdleState = sConfig->OCIdleState;
+    temp1.OCNIdleState = sConfig->OCNIdleState;
+
+    switch (OutputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_OC1_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_OC2_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+
+    if (status == HAL_OK)
+    {
+      switch (InputChannel)
+      {
+        case TIM_CHANNEL_1:
+        {
+          assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+          TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC1PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        case TIM_CHANNEL_2:
+        {
+          assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+          TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC2PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        default:
+          status = HAL_ERROR;
+          break;
+      }
+    }
+
+    htim->State = HAL_TIM_STATE_READY;
+
+    __HAL_UNLOCK(htim);
+
+    return status;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_OR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_AF1  (*)
+  *            @arg TIM_DMABASE_AF2  (*)
+  *         (*) value not defined in all devices
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                              uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                            ((BurstLength) >> 8U) + 1U);
+
+
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_OR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_AF1  (*)
+  *            @arg TIM_DMABASE_AF2  (*)
+  *         (*) value not defined in all devices
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                                   uint32_t  BurstLength,  uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_OR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_AF1  (*)
+  *            @arg TIM_DMABASE_AF2  (*)
+  *         (*) value not defined in all devices
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                           ((BurstLength) >> 8U) + 1U);
+
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_OR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_AF1  (*)
+  *            @arg TIM_DMABASE_AF2  (*)
+  *         (*) value not defined in all devices
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stop the DMA burst reading
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+  * @note   Basic timers can only generate an update event.
+  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+  * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+  *         only for timer instances supporting break input(s).
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           const TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (sClearInputConfig->ClearInputSource)
+  {
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Clear the OCREF clear selection bit and the the ETR Bits */
+      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+      {
+        htim->State = HAL_TIM_STATE_READY;
+        __HAL_UNLOCK(htim);
+        return HAL_ERROR;
+      }
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    switch (Channel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 1 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 1 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 2 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 2 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_3:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 3 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 3 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_4:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 4 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 4 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_5:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 5 */
+          SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 5 */
+          CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_6:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 6 */
+          SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 6 */
+          CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+        }
+        break;
+      }
+      default:
+        break;
+    }
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INTERNAL:
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI2:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1ED:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ITR0:
+    case TIM_CLOCKSOURCE_ITR1:
+    case TIM_CLOCKSOURCE_ITR2:
+    case TIM_CLOCKSOURCE_ITR3:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Disable Trigger Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode in interrupt mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+                                                const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Enable Trigger Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0U;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Return the capture 1 value */
+      tmpreg =  htim->Instance->CCR1;
+
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Return the capture 2 value */
+      tmpreg =   htim->Instance->CCR2;
+
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Return the capture 3 value */
+      tmpreg =   htim->Instance->CCR3;
+
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Return the capture 4 value */
+      tmpreg =   htim->Instance->CCR4;
+
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief    TIM Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================
+ [..]
+   This section provides TIM callback functions:
+   (+) TIM Period elapsed callback
+   (+) TIM Output Compare callback
+   (+) TIM Input capture callback
+   (+) TIM Trigger callback
+   (+) TIM Error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Period elapsed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @param pCallback pointer to the callback function
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback               = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback                = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback             = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback              = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback            = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback                = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                      = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback              = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback              = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback          = pCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        htim->Break2Callback                       = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a TIM callback
+  *         TIM callback is redirected to the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        /* Legacy weak Period Elapsed Callback */
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        /* Legacy weak Period Elapsed half complete Callback */
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        /* Legacy weak Trigger Callback */
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        /* Legacy weak Trigger half complete Callback */
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        /* Legacy weak IC Capture Callback */
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        /* Legacy weak IC Capture half complete Callback */
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        /* Legacy weak OC Delay Elapsed Callback */
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        /* Legacy weak PWM Pulse Finished Callback */
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        /* Legacy weak PWM Pulse Finished half complete Callback */
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        /* Legacy weak Error Callback */
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        /* Legacy weak Commutation Callback */
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        /* Legacy weak Commutation half complete Callback */
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        /* Legacy weak Break Callback */
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        /* Legacy weak Break2 Callback */
+        htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief   TIM Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim TIM Output Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim TIM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim TIM IC handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim TIM OPM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM handle
+  * @retval Active channel
+  */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
+{
+  return htim->Channel;
+}
+
+/**
+  * @brief  Return actual state of the TIM channel.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval TIM Channel state
+  */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_state;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+  return channel_state;
+}
+
+/**
+  * @brief  Return actual state of a DMA burst operation.
+  * @param  htim TIM handle
+  * @retval DMA burst state
+  */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+  return htim->DMABurstState;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureCallback(htim);
+#else
+  HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureHalfCpltCallback(htim);
+#else
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Period Elapse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerCallback(htim);
+#else
+  HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerHalfCpltCallback(htim);
+#else
+  HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+
+  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+  {
+    /* Clear the update flag */
+    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+  }
+}
+
+/**
+  * @brief  Timer Output Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 5 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+                              const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC5E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC5M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC5P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 16U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS5;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 8U);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR5 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 6 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+                              const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC6E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC6M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 20U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS6;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 10U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR6 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Slave Timer configuration function
+  * @param  htim TIM handle
+  * @param  sSlaveConfig Slave timer configuration
+  * @retval None
+  */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+    case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sSlaveConfig->TriggerPrescaler,
+                        sSlaveConfig->TriggerPolarity,
+                        sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;
+
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;
+      break;
+    }
+
+    case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_ITR0:
+    case TIM_TS_ITR1:
+    case TIM_TS_ITR2:
+    case TIM_TS_ITR3:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Select the Input */
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4U);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+  * @param  ExtTRGFilter External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+  /* Reset the TIM callback to the legacy weak callbacks */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c
new file mode 100644
index 0000000..0387644
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c
@@ -0,0 +1,2588 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
+  *           + Time Hall Sensor Interface Initialization
+  *           + Time Hall Sensor Interface Start
+  *           + Time Complementary signal break and dead time configuration
+  *           + Time Master and Slave synchronization configuration
+  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+  *           + Timer remapping capabilities configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..]
+    The Timer Extended features include:
+    (#) Complementary outputs with programmable dead-time for :
+        (++) Output Compare
+        (++) PWM generation (Edge and Center-aligned Mode)
+        (++) One-pulse mode output
+    (#) Synchronization circuit to control the timer with external signals and to
+        interconnect several timers together.
+    (#) Break input to put the timer output signals in reset state or in a known state.
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+        positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+              __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+         initialization function of this driver:
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+               Timer Hall Sensor Interface and the commutation event with the corresponding
+               Interrupt and DMA request if needed (Note that One Timer is used to interface
+               with the Hall sensor Interface and another Timer should be used to use
+               the commutation event).
+
+     (#) Activate the TIM peripheral using one of the start functions:
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+                HAL_TIMEx_OCN_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+                HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
+                HAL_TIMEx_HallSensor_Start_IT().
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  * @brief    Timer Hall Sensor functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Timer Hall Sensor functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure TIM HAL Sensor.
+    (+) De-initialize TIM HAL Sensor.
+    (+) Start the Hall Sensor Interface.
+    (+) Stop the Hall Sensor Interface.
+    (+) Start the Hall Sensor Interface and enable interrupts.
+    (+) Stop the Hall Sensor Interface and disable interrupts.
+    (+) Start the Hall Sensor Interface and enable DMA transfers.
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+  * @note   When the timer instance is initialized in Hall Sensor Interface mode,
+  *         timer channels 1 and channel 2 are reserved and cannot be used for
+  *         other purpose.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  sConfig TIM Hall Sensor configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
+{
+  TIM_OC_InitTypeDef OC_Config;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy week callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->HallSensor_MspInitCallback == NULL)
+    {
+      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->HallSensor_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+  /* Reset the IC1PSC Bits */
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+  /* Set the IC1PSC value */
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */
+  htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+  OC_Config.OCMode = TIM_OCMODE_PWM2;
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  OC_Config.Pulse = sConfig->Commutation_Delay;
+
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+    register to 101 */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Hall Sensor interface
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->HallSensor_MspDeInitCallback == NULL)
+  {
+    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->HallSensor_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1, 2 and 3
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the capture compare Interrupts 1 event */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the capture compare Interrupts event */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel state */
+  if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+      || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+  {
+    return HAL_BUSY;
+  }
+  else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+           && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Set the DMA Input Capture 1 Callbacks */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream for Capture 1*/
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  /* Enable the capture compare 1 Interrupt */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+  /* Disable the capture compare Interrupts 1 event */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Timer Complementary Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary Output Compare/PWM.
+    (+) Stop the Complementary Output Compare/PWM.
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                          uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  * @brief    Timer Complementary PWM functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Timer Complementary PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary PWM.
+    (+) Stop the Complementary PWM.
+    (+) Start the Complementary PWM and enable interrupts.
+    (+) Stop the Complementary PWM and disable interrupts.
+    (+) Start the Complementary PWM and enable DMA transfers.
+    (+) Stop the Complementary PWM and disable DMA transfers.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the
+  *         complementary output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                           uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+  *         output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the complementary PWM output */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  * @brief    Timer Complementary One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Timer Complementary One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to enable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM  channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to enable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  /* Enable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM  channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Configure the commutation event in case of use of the Hall sensor interface.
+      (+) Configure Output channels for OC and PWM mode.
+
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+      (+) Enable or disable channel grouping.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the TIM commutation event sequence.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with interrupt.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  /* Enable the Commutation Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with DMA.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Enable the Commutation DMA Request */
+  /* Set the DMA Commutation Callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Enable the Commutation DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+    /* Clear the MMS2 bits */
+    tmpcr2 &= ~TIM_CR2_MMS2;
+    /* Select the TRGO2 source*/
+    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+  }
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  htim TIM handle
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @note   Interrupts can be generated when an active level is detected on the
+  *         break input, the break 2 input or the system break input. Break
+  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+  uint32_t tmpbdtr = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+
+  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+    assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+    assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+
+    /* Set the BREAK2 input related BDTR bits */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+  }
+
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/**
+  * @brief  Configures the break input source.
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @param  sBreakInputConfig Break input source configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+                                             uint32_t BreakInput,
+                                             const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmporx;
+  uint32_t bkin_enable_mask;
+  uint32_t bkin_polarity_mask;
+  uint32_t bkin_enable_bitpos;
+  uint32_t bkin_polarity_bitpos;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+#if defined(DFSDM1_Channel0)
+  if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+  {
+    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+  }
+#else
+  assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+#endif /* DFSDM1_Channel0 */
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  switch (sBreakInputConfig->Source)
+  {
+    case TIM_BREAKINPUTSOURCE_BKIN:
+    {
+      bkin_enable_mask = TIM1_AF1_BKINE;
+      bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKINP;
+      bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+      break;
+    }
+#if defined(DFSDM1_Channel0)
+    case TIM_BREAKINPUTSOURCE_DFSDM1:
+    {
+      bkin_enable_mask = TIM1_AF1_BKDF1BKE;
+      bkin_enable_bitpos = TIM1_AF1_BKDF1BKE_Pos;
+      bkin_polarity_mask = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+#endif /* DFSDM1_Channel0 */
+
+    default:
+    {
+      bkin_enable_mask = 0U;
+      bkin_polarity_mask = 0U;
+      bkin_enable_bitpos = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+  }
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Get the TIMx_AF1 register value */
+      tmporx = htim->Instance->AF1;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+#if defined(DFSDM1_Channel0)
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+#endif /* DFSDM1_Channel0 */
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
+
+      /* Set TIMx_AF1 */
+      htim->Instance->AF1 = tmporx;
+      break;
+    }
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Get the TIMx_AF2 register value */
+      tmporx = htim->Instance->AF2;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+#if defined(DFSDM1_Channel0)
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+#endif /* DFSDM1_Channel0 */
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
+
+      /* Set TIMx_AF2 */
+      htim->Instance->AF2 = tmporx;
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+#endif /*TIM_BREAK_INPUT_SUPPORT */
+
+/**
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
+  *            @arg TIM_TIM2_ETH_PTP:   TIM2 ITR1 input is connected to ETH PTP trigger output.
+  *            @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
+  *            @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
+  *            @arg TIM_TIM5_GPIO:      TIM5 CH4 input is connected to dedicated Timer pin(default)
+  *            @arg TIM_TIM5_LSI:       TIM5 CH4 input is connected to LSI clock.
+  *            @arg TIM_TIM5_LSE:       TIM5 CH4 input is connected to LSE clock.
+  *            @arg TIM_TIM5_RTC:       TIM5 CH4 input is connected to RTC Output event.
+  *            @arg TIM_TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default)
+  *            @arg TIM_TIM11_SPDIF:    SPDIF Frame synchronous
+  *            @arg TIM_TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock
+  *                                     (HSE divided by a programmable prescaler)
+  *            @arg TIM_TIM11_MCO1:     TIM11 CH1 input is connected to MCO1
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_REMAP(Remap));
+
+  __HAL_LOCK(htim);
+
+  /* Set the Timer remapping configuration */
+  htim->Instance->OR = Remap;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Group channel 5 and channel 1, 2 or 3
+  * @param  htim TIM handle.
+  * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
+  *         This parameter can be any combination of the following values:
+  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_GROUPCH5(Channels));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Clear GC5Cx bit fields */
+  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+
+  /* Set GC5Cx bit fields */
+  htim->Instance->CCR5 |= Channels;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Extended Callbacks functions #####
+  ==============================================================================
+  [..]
+    This section provides Extended TIM callback functions:
+    (+) Timer Commutation callback
+    (+) Timer Break callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Commutation callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Commutation half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Break detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Break2 detection callback in non blocking mode
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_Break2Callback could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Extended Peripheral State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Hall Sensor interface handle state.
+  * @param  htim TIM Hall Sensor handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return actual state of the TIM complementary channel.
+  * @param  htim TIM handle
+  * @param  ChannelN TIM Complementary channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  * @retval TIM Complementary channel state
+  */
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN)
+{
+  HAL_TIM_ChannelStateTypeDef channel_state;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+
+  channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+
+  return channel_state;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationCallback(htim);
+#else
+  HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Commutation half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationHalfCpltCallback(htim);
+#else
+  HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback (complementary channel).
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA error callback (complementary channel)
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+  * @retval None
+  */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+  uint32_t tmp;
+
+  tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &=  ~tmp;
+
+  /* Set or reset the CCxNE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c
new file mode 100644
index 0000000..2f25caa
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c
@@ -0,0 +1,444 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_dma.h"
+#include "stm32f7xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL)    || \
+                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR)  || \
+                                                 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
+
+#if  defined(DMA_CHANNEL_SELECTION_8_15)
+#define IS_LL_DMA_CHANNEL(__VALUE__)            (((__VALUE__) == LL_DMA_CHANNEL_0)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_1)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_2)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_3)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_4)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_5)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_6)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_7)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_8)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_9)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_10)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_11)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_12)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_13)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_14)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_15))
+
+#else
+#define IS_LL_DMA_CHANNEL(__VALUE__)            (((__VALUE__) == LL_DMA_CHANNEL_0)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_1)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_2)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_3)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_4)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_5)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_6)  || \
+                                                 ((__VALUE__) == LL_DMA_CHANNEL_7))
+
+#endif /* DMA_CHANNEL_SELECTION_8_15 */
+
+#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)   ((((INSTANCE) == DMA1) && \
+                                                           (((STREAM) == LL_DMA_STREAM_0) || \
+                                                            ((STREAM) == LL_DMA_STREAM_1) || \
+                                                            ((STREAM) == LL_DMA_STREAM_2) || \
+                                                            ((STREAM) == LL_DMA_STREAM_3) || \
+                                                            ((STREAM) == LL_DMA_STREAM_4) || \
+                                                            ((STREAM) == LL_DMA_STREAM_5) || \
+                                                            ((STREAM) == LL_DMA_STREAM_6) || \
+                                                            ((STREAM) == LL_DMA_STREAM_7) || \
+                                                            ((STREAM) == LL_DMA_STREAM_ALL))) ||\
+                                                            (((INSTANCE) == DMA2) && \
+                                                          (((STREAM) == LL_DMA_STREAM_0) || \
+                                                           ((STREAM) == LL_DMA_STREAM_1) || \
+                                                           ((STREAM) == LL_DMA_STREAM_2) || \
+                                                           ((STREAM) == LL_DMA_STREAM_3) || \
+                                                           ((STREAM) == LL_DMA_STREAM_4) || \
+                                                           ((STREAM) == LL_DMA_STREAM_5) || \
+                                                           ((STREAM) == LL_DMA_STREAM_6) || \
+                                                           ((STREAM) == LL_DMA_STREAM_7) || \
+                                                           ((STREAM) == LL_DMA_STREAM_ALL))))
+
+#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
+                                          ((STATE) == LL_DMA_FIFOMODE_ENABLE))
+
+#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
+                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2)  || \
+                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4)  || \
+                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
+
+#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
+                                       ((BURST) == LL_DMA_MBURST_INC4)   || \
+                                       ((BURST) == LL_DMA_MBURST_INC8)   || \
+                                       ((BURST) == LL_DMA_MBURST_INC16))
+
+#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
+                                           ((BURST) == LL_DMA_PBURST_INC4)   || \
+                                           ((BURST) == LL_DMA_PBURST_INC8)   || \
+                                           ((BURST) == LL_DMA_PBURST_INC16))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the DMA registers to their default reset values.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  *         @arg @ref LL_DMA_STREAM_ALL
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are de-initialized
+  *          - ERROR: DMA registers are not de-initialized
+  */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
+  ErrorStatus status = SUCCESS;
+
+  /* Check the DMA Instance DMAx and Stream parameters*/
+  assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
+
+  if (Stream == LL_DMA_STREAM_ALL)
+  {
+    if (DMAx == DMA1)
+    {
+      /* Force reset of DMA clock */
+      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
+    }
+    else if (DMAx == DMA2)
+    {
+      /* Force reset of DMA clock */
+      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    /* Disable the selected Stream */
+    LL_DMA_DisableStream(DMAx,Stream);
+
+    /* Get the DMA Stream Instance */
+    tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
+
+    /* Reset DMAx_Streamy configuration register */
+    LL_DMA_WriteReg(tmp, CR, 0U);
+
+    /* Reset DMAx_Streamy remaining bytes register */
+    LL_DMA_WriteReg(tmp, NDTR, 0U);
+
+    /* Reset DMAx_Streamy peripheral address register */
+    LL_DMA_WriteReg(tmp, PAR, 0U);
+
+    /* Reset DMAx_Streamy memory address register */
+    LL_DMA_WriteReg(tmp, M0AR, 0U);
+
+    /* Reset DMAx_Streamy memory address register */
+    LL_DMA_WriteReg(tmp, M1AR, 0U);
+
+    /* Reset DMAx_Streamy FIFO control register */
+    LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
+
+    /* Reset Channel register field for DMAx Stream*/
+    LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
+
+    if(Stream == LL_DMA_STREAM_0)
+    {
+       /* Reset the Stream0 pending flags */
+       DMAx->LIFCR = 0x0000003FU;
+    }
+    else if(Stream == LL_DMA_STREAM_1)
+    {
+       /* Reset the Stream1 pending flags */
+       DMAx->LIFCR = 0x00000F40U;
+    }
+    else if(Stream == LL_DMA_STREAM_2)
+    {
+       /* Reset the Stream2 pending flags */
+       DMAx->LIFCR = 0x003F0000U;
+    }
+    else if(Stream == LL_DMA_STREAM_3)
+    {
+       /* Reset the Stream3 pending flags */
+       DMAx->LIFCR = 0x0F400000U;
+    }
+    else if(Stream == LL_DMA_STREAM_4)
+    {
+       /* Reset the Stream4 pending flags */
+       DMAx->HIFCR = 0x0000003FU;
+    }
+    else if(Stream == LL_DMA_STREAM_5)
+    {
+       /* Reset the Stream5 pending flags */
+       DMAx->HIFCR = 0x00000F40U;
+    }
+    else if(Stream == LL_DMA_STREAM_6)
+    {
+       /* Reset the Stream6 pending flags */
+       DMAx->HIFCR = 0x003F0000U;
+    }
+    else if(Stream == LL_DMA_STREAM_7)
+    {
+       /* Reset the Stream7 pending flags */
+       DMAx->HIFCR = 0x0F400000U;
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+  * @note   To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
+  *         @arg @ref __LL_DMA_GET_INSTANCE
+  *         @arg @ref __LL_DMA_GET_STREAM
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are initialized
+  *          - ERROR: Not applicable
+  */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Check the DMA Instance DMAx and Stream parameters*/
+  assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
+
+  /* Check the DMA parameters from DMA_InitStruct */
+  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+  assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+  assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+  assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+  assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+  assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+  assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
+  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+  assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
+  /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+     when FIFO mode is enabled */
+  if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
+  {
+    assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
+    assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
+    assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
+  }
+
+  /*---------------------------- DMAx SxCR Configuration ------------------------
+   * Configure DMAx_Streamy: data transfer direction, data transfer mode,
+   *                          peripheral and memory increment mode,
+   *                          data size alignment and  priority level with parameters :
+   * - Direction:      DMA_SxCR_DIR[1:0] bits
+   * - Mode:           DMA_SxCR_CIRC bit
+   * - PeriphOrM2MSrcIncMode:  DMA_SxCR_PINC bit
+   * - MemoryOrM2MDstIncMode:  DMA_SxCR_MINC bit
+   * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
+   * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
+   * - Priority:               DMA_SxCR_PL[1:0] bits
+   */
+  LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
+                        DMA_InitStruct->Mode                    | \
+                        DMA_InitStruct->PeriphOrM2MSrcIncMode   | \
+                        DMA_InitStruct->MemoryOrM2MDstIncMode   | \
+                        DMA_InitStruct->PeriphOrM2MSrcDataSize  | \
+                        DMA_InitStruct->MemoryOrM2MDstDataSize  | \
+                        DMA_InitStruct->Priority
+                        );
+
+  if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
+  {
+    /*---------------------------- DMAx SxFCR Configuration ------------------------
+     * Configure DMAx_Streamy:  fifo mode and fifo threshold with parameters :
+     * - FIFOMode:                DMA_SxFCR_DMDIS bit
+     * - FIFOThreshold:           DMA_SxFCR_FTH[1:0] bits
+     */
+    LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);   
+
+    /*---------------------------- DMAx SxCR Configuration --------------------------
+     * Configure DMAx_Streamy:  memory burst transfer with parameters :
+     * - MemBurst:                DMA_SxCR_MBURST[1:0] bits
+     */
+    LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst); 
+
+    /*---------------------------- DMAx SxCR Configuration --------------------------
+     * Configure DMAx_Streamy:  peripheral burst transfer with parameters :
+     * - PeriphBurst:             DMA_SxCR_PBURST[1:0] bits
+     */
+    LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
+  }
+
+  /*-------------------------- DMAx SxM0AR Configuration --------------------------
+   * Configure the memory or destination base address with parameter :
+   * - MemoryOrM2MDstAddress:     DMA_SxM0AR_M0A[31:0] bits
+   */
+  LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+  /*-------------------------- DMAx SxPAR Configuration ---------------------------
+   * Configure the peripheral or source base address with parameter :
+   * - PeriphOrM2MSrcAddress:     DMA_SxPAR_PA[31:0] bits
+   */
+  LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+  /*--------------------------- DMAx SxNDTR Configuration -------------------------
+   * Configure the peripheral base address with parameter :
+   * - NbData:                    DMA_SxNDT[15:0] bits
+   */
+  LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
+
+  /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
+   * Configure the peripheral base address with parameter :
+   * - PeriphRequest:             DMA_SxCR_CHSEL[3:0] bits
+   */
+  LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
+  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval None
+  */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Set DMA_InitStruct fields to default values */
+  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
+  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
+  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
+  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
+  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
+  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+  DMA_InitStruct->NbData                 = 0x00000000U;
+  DMA_InitStruct->Channel                = LL_DMA_CHANNEL_0;
+  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
+  DMA_InitStruct->FIFOMode               = LL_DMA_FIFOMODE_DISABLE;
+  DMA_InitStruct->FIFOThreshold          = LL_DMA_FIFOTHRESHOLD_1_4;
+  DMA_InitStruct->MemBurst               = LL_DMA_MBURST_SINGLE;
+  DMA_InitStruct->PeriphBurst            = LL_DMA_PBURST_SINGLE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c
new file mode 100644
index 0000000..f615e26
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c
@@ -0,0 +1,212 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_exti.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the EXTI registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: EXTI registers are de-initialized
+  *          - ERROR: not applicable
+  */
+uint32_t LL_EXTI_DeInit(void)
+{
+  /* Interrupt mask register set to default reset values */
+  LL_EXTI_WriteReg(IMR,   0x00000000U);
+  /* Event mask register set to default reset values */
+  LL_EXTI_WriteReg(EMR,   0x00000000U);
+  /* Rising Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(RTSR,  0x00000000U);
+  /* Falling Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(FTSR,  0x00000000U);
+  /* Software interrupt event register set to default reset values */
+  LL_EXTI_WriteReg(SWIER, 0x00000000U);
+  /* Pending register set to default reset values */
+  LL_EXTI_WriteReg(PR,    0x01FFFFFFU);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: EXTI registers are initialized
+  *          - ERROR: not applicable
+  */
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  /* Check the parameters */
+  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+  /* ENABLE LineCommand */
+  if (EXTI_InitStruct->LineCommand != DISABLE)
+  {
+    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+    /* Configure EXTI Lines in range from 0 to 31 */
+    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+    {
+      switch (EXTI_InitStruct->Mode)
+      {
+        case LL_EXTI_MODE_IT:
+          /* First Disable Event on provided Lines */
+          LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          /* Then Enable IT on provided Lines */
+          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        case LL_EXTI_MODE_EVENT:
+          /* First Disable IT on provided Lines */
+          LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+          /* Then Enable Event on provided Lines */
+          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        case LL_EXTI_MODE_IT_EVENT:
+          /* Directly Enable IT & Event on provided Lines */
+          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        default:
+          status = ERROR;
+          break;
+      }
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Rising Trigger on provided Lines */
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          default:
+            status = ERROR;
+            break;
+        }
+      }
+    }
+  }
+  /* DISABLE LineCommand */
+  else
+  {
+    /* De-configure EXTI Lines in range from 0 to 31 */
+    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
+  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval None
+  */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->LineCommand    = DISABLE;
+  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
+  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (EXTI) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c
new file mode 100644
index 0000000..2730301
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c
@@ -0,0 +1,300 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_gpio.h"
+#include "stm32f7xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
+
+/** @addtogroup GPIO_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
+                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_15 ))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize GPIO registers (Registers restored to their default values).
+  * @param  GPIOx GPIO Port
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are de-initialized
+  *          - ERROR:   Wrong GPIO Port
+  */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+  /* Force and Release reset on clock of GPIOx Port */
+  if (GPIOx == GPIOA)
+  {
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
+  }
+#if defined(GPIOD)
+  else if (GPIOx == GPIOD)
+  {
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
+  }
+#endif /* GPIOD */
+#if defined(GPIOE)
+  else if (GPIOx == GPIOE)
+  {
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
+  }
+#endif /* GPIOE */
+#if defined(GPIOF)
+  else if (GPIOx == GPIOF)
+  {
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
+  }
+#endif /* GPIOF */
+#if defined(GPIOG)
+  else if (GPIOx == GPIOG)
+  {
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
+  }
+#endif /* GPIOG */
+#if defined(GPIOH)
+  else if (GPIOx == GPIOH)
+  {
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
+  }
+#endif /* GPIOH */
+#if defined(GPIOI)
+  else if (GPIOx == GPIOI)
+  {
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOI);
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI);
+  }
+#endif /* GPIOI */
+#if defined(GPIOJ)
+  else if (GPIOx == GPIOJ)
+  {
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
+  }
+#endif /* GPIOJ */
+#if defined(GPIOK)
+  else if (GPIOx == GPIOK)
+  {
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOK);
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK);
+  }
+#endif /* GPIOK */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+  * @param  GPIOx GPIO Port
+  * @param  GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+  *         that contains the configuration information for the specified GPIO peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+  *          - ERROR:   Not applicable
+  */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  uint32_t pinpos     = 0x00000000U;
+  uint32_t currentpin = 0x00000000U;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+  /* ------------------------- Configure the port pins ---------------- */
+  /* Initialize  pinpos on first pin set */
+  pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+
+  /* Configure the port pins */
+  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+  {
+    /* Get current io position */
+    currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
+
+    if (currentpin)
+    {
+      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+        /* Speed mode configuration */
+        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+        /* Check Output mode parameters */
+        assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+        /* Output mode configuration*/
+        LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+      }
+
+      /* Pull-up Pull down resistor configuration*/
+      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+      {
+        /* Check Alternate parameter */
+        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+        /* Speed mode configuration */
+        if (POSITION_VAL(currentpin) < 0x00000008U)
+        {
+          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+        else
+        {
+          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+      }
+      /* Pin Mode configuration */
+      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+    }
+    pinpos++;
+  }
+  return (SUCCESS);
+}
+
+/**
+  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
+  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
+  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
+  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c
new file mode 100644
index 0000000..d96774d
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c
@@ -0,0 +1,1585 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_rcc.h"
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @addtogroup RCC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE))
+
+#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
+                                             || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \
+                                             || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \
+                                             || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE))
+
+#if defined(I2C4)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
+#else
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+#endif /* I2C4 */
+
+#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
+
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
+
+#if defined(SDMMC2)
+#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE))
+#else
+#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
+#endif /* SDMMC2 */
+
+#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
+
+#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
+
+#if defined(DFSDM1_Channel0)
+#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
+
+#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
+#endif /* DFSDM1_Channel0 */
+
+#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
+
+#if defined(CEC)
+#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
+#endif /* CEC */
+
+#if defined(DSI)
+#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
+#endif /* DSI */
+
+#if defined(LTDC)
+#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
+#endif /* LTDC */
+
+#if defined(SPDIFRX)
+#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
+#endif /* SPDIFRX */
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+  * @{
+  */
+uint32_t RCC_GetSystemClockFreq(void);
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+uint32_t RCC_PLL_GetFreqDomain_SAI(void);
+uint32_t RCC_PLL_GetFreqDomain_48M(void);
+#if defined(DSI)
+uint32_t RCC_PLL_GetFreqDomain_DSI(void);
+#endif /* DSI */
+uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
+uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
+#if defined(LTDC)
+uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
+#endif /* LTDC */
+uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
+uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
+#if defined(SPDIFRX)
+uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
+#endif /* SPDIFRX */
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Reset the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *         - HSI ON and used as system clock source
+  *         - HSE, PLL, PLLI2S, PLLSAI OFF
+  *         - AHB, APB1 and APB2 prescaler set to 1.
+  *         - CSS, MCO OFF
+  *         - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *         - Peripheral clocks
+  *         - LSI, LSE and RTC clocks
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RCC registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_RCC_DeInit(void)
+{
+  __IO uint32_t vl_mask;
+
+  /* Set HSION bit */
+  LL_RCC_HSI_Enable();
+
+  /* Wait for HSI READY bit */
+  while(LL_RCC_HSI_IsReady() != 1U)
+  {}
+
+  /* Reset CFGR register */
+  LL_RCC_WriteReg(CFGR, 0x00000000U);
+
+  /* Read CR register */
+  vl_mask = LL_RCC_ReadReg(CR);
+  
+  /* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */
+  CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON));
+
+  /* Write new value in CR register */
+  LL_RCC_WriteReg(CR, vl_mask);
+
+  /* Set HSITRIM bits to the reset value*/
+  LL_RCC_HSI_SetCalibTrimming(0x10U);
+
+  /* Wait for PLL READY bit to be reset */
+  while(LL_RCC_PLL_IsReady() != 0U)
+  {}
+
+  /* Wait for PLLI2S READY bit to be reset */
+  while(LL_RCC_PLLI2S_IsReady() != 0U)
+  {}
+
+  /* Wait for PLLSAI READY bit to be reset */
+  while(LL_RCC_PLLSAI_IsReady() != 0U)
+  {}
+
+  /* Reset PLLCFGR register */
+  LL_RCC_WriteReg(PLLCFGR, 0x24003010U);
+
+  /* Reset PLLI2SCFGR register */
+  LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U);
+
+  /* Reset PLLSAICFGR register */
+  LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U);
+
+  /* Disable all interrupts */
+  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);
+
+  /* Clear all interrupt flags */
+  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);
+
+  /* Clear LSION bit */
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+
+  /* Reset all CSR flags */
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+
+  return SUCCESS;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
+  *         and different peripheral clocks available on the device.
+  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+  * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
+  *         or HSI_VALUE(**) multiplied/divided by the PLL factors.
+  * @note   (**) HSI_VALUE is a constant defined in this file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  * @note   (***) HSE_VALUE is a constant defined in this file (default value
+  *               25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *               frequency of the crystal used. Otherwise, this function may
+  *               have wrong result.
+  * @note   The result of this function could be incorrect when using fractional
+  *         value for HSE crystal.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  * @{
+  */
+
+/**
+  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
+  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+  *         must be called to update structure fields. Otherwise, any
+  *         configuration based on this function will be incorrect.
+  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+  * @retval None
+  */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+  /* Get SYSCLK frequency */
+  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+  /* PCLK1 clock frequency */
+  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK2 clock frequency */
+  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+/**
+  * @brief  Return USARTx clock frequency
+  * @param  USARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE
+  * @retval USART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+  */
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+{
+  uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+
+  if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
+  {
+    /* USART1CLK clock frequency */
+    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+    {
+      case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
+        usart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          usart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          usart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART1_CLKSOURCE_PCLK2:  /* USART1 Clock is PCLK2 */
+      default:
+        usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+  else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
+  {
+    /* USART2CLK clock frequency */
+    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+    {
+      case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
+        usart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          usart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          usart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */
+      default:
+        usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+  else if (USARTxSource == LL_RCC_USART6_CLKSOURCE)
+  {
+    /* USART6CLK clock frequency */
+    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+    {
+      case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */
+        usart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_USART6_CLKSOURCE_HSI:    /* USART6 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          usart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART6_CLKSOURCE_LSE:    /* USART6 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          usart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART6_CLKSOURCE_PCLK2:  /* USART6 Clock is PCLK2 */
+      default:
+        usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+  else
+  {
+    if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
+    {
+      /* USART3CLK clock frequency */
+      switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+      {
+        case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
+          usart_frequency = RCC_GetSystemClockFreq();
+          break;
+
+        case LL_RCC_USART3_CLKSOURCE_HSI:    /* USART3 Clock is HSI Osc. */
+          if (LL_RCC_HSI_IsReady())
+          {
+            usart_frequency = HSI_VALUE;
+          }
+          break;
+
+        case LL_RCC_USART3_CLKSOURCE_LSE:    /* USART3 Clock is LSE Osc. */
+          if (LL_RCC_LSE_IsReady())
+          {
+            usart_frequency = LSE_VALUE;
+          }
+          break;
+
+        case LL_RCC_USART3_CLKSOURCE_PCLK1:  /* USART3 Clock is PCLK1 */
+        default:
+          usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+          break;
+      }
+    }
+  }
+  return usart_frequency;
+}
+
+/**
+  * @brief  Return UARTx clock frequency
+  * @param  UARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE
+  * @retval UART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+  */
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
+{
+  uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
+
+  if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
+  {
+    /* UART4CLK clock frequency */
+    switch (LL_RCC_GetUARTClockSource(UARTxSource))
+    {
+      case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
+        uart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_UART4_CLKSOURCE_HSI:    /* UART4 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          uart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_UART4_CLKSOURCE_LSE:    /* UART4 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          uart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_UART4_CLKSOURCE_PCLK1:  /* UART4 Clock is PCLK1 */
+      default:
+        uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+  else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
+  {
+    /* UART5CLK clock frequency */
+    switch (LL_RCC_GetUARTClockSource(UARTxSource))
+    {
+      case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
+        uart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_UART5_CLKSOURCE_HSI:    /* UART5 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          uart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_UART5_CLKSOURCE_LSE:    /* UART5 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          uart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_UART5_CLKSOURCE_PCLK1:  /* UART5 Clock is PCLK1 */
+      default:
+        uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+  else if (UARTxSource == LL_RCC_UART7_CLKSOURCE)
+  {
+    /* UART7CLK clock frequency */
+    switch (LL_RCC_GetUARTClockSource(UARTxSource))
+    {
+      case LL_RCC_UART7_CLKSOURCE_SYSCLK: /* UART7 Clock is System Clock */
+        uart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_UART7_CLKSOURCE_HSI:    /* UART7 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          uart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_UART7_CLKSOURCE_LSE:    /* UART7 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          uart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_UART7_CLKSOURCE_PCLK1:  /* UART7 Clock is PCLK1 */
+      default:
+        uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+  else
+  {
+    if (UARTxSource == LL_RCC_UART8_CLKSOURCE)
+    {
+      /* UART8CLK clock frequency */
+      switch (LL_RCC_GetUARTClockSource(UARTxSource))
+      {
+        case LL_RCC_UART8_CLKSOURCE_SYSCLK: /* UART8 Clock is System Clock */
+          uart_frequency = RCC_GetSystemClockFreq();
+          break;
+
+        case LL_RCC_UART8_CLKSOURCE_HSI:    /* UART8 Clock is HSI Osc. */
+          if (LL_RCC_HSI_IsReady())
+          {
+            uart_frequency = HSI_VALUE;
+          }
+          break;
+
+        case LL_RCC_UART8_CLKSOURCE_LSE:    /* UART8 Clock is LSE Osc. */
+          if (LL_RCC_LSE_IsReady())
+          {
+            uart_frequency = LSE_VALUE;
+          }
+          break;
+
+        case LL_RCC_UART8_CLKSOURCE_PCLK1:  /* UART8 Clock is PCLK1 */
+        default:
+          uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+          break;
+      }
+    }
+  }
+  return uart_frequency;
+}
+
+/**
+  * @brief  Return I2Cx clock frequency
+  * @param  I2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval I2C clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
+  */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+{
+  uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+
+  if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
+  {
+    /* I2C1 CLK clock frequency */
+    switch (LL_RCC_GetI2CClockSource(I2CxSource))
+    {
+      case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
+        i2c_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          i2c_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */
+      default:
+        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+  else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
+  {
+    /* I2C2 CLK clock frequency */
+    switch (LL_RCC_GetI2CClockSource(I2CxSource))
+    {
+      case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
+        i2c_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_I2C2_CLKSOURCE_HSI:    /* I2C2 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          i2c_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_I2C2_CLKSOURCE_PCLK1:  /* I2C2 Clock is PCLK1 */
+      default:
+        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+  else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
+  {
+    /* I2C3 CLK clock frequency */
+    switch (LL_RCC_GetI2CClockSource(I2CxSource))
+    {
+      case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
+        i2c_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_I2C3_CLKSOURCE_HSI:    /* I2C3 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          i2c_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_I2C3_CLKSOURCE_PCLK1:  /* I2C3 Clock is PCLK1 */
+      default:
+        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+#if defined(I2C4)
+  else
+  {
+    if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
+    {
+      /* I2C4 CLK clock frequency */
+      switch (LL_RCC_GetI2CClockSource(I2CxSource))
+      {
+        case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
+          i2c_frequency = RCC_GetSystemClockFreq();
+          break;
+
+        case LL_RCC_I2C4_CLKSOURCE_HSI:    /* I2C4 Clock is HSI Osc. */
+          if (LL_RCC_HSI_IsReady())
+          {
+            i2c_frequency = HSI_VALUE;
+          }
+          break;
+
+        case LL_RCC_I2C4_CLKSOURCE_PCLK1:  /* I2C4 Clock is PCLK1 */
+        default:
+          i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+          break;
+      }
+    }
+  }
+#else
+  else
+  {
+    /* Nothing to do */
+  }
+#endif /* I2C4 */
+
+  return i2c_frequency;
+}
+
+/**
+  * @brief  Return I2Sx clock frequency
+  * @param  I2SxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE
+  * @retval I2S clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLLI2S oscillator is not ready
+  */
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
+{
+  uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
+
+  if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
+  {
+    /* I2S1 CLK clock frequency */
+    switch (LL_RCC_GetI2SClockSource(I2SxSource))
+    {
+      case LL_RCC_I2S1_CLKSOURCE_PLLI2S:       /* I2S1 Clock is PLLI2S */
+        if (LL_RCC_PLLI2S_IsReady())
+        {
+          i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
+        }
+        break;
+
+      case LL_RCC_I2S1_CLKSOURCE_PIN:          /* I2S1 Clock is External clock */
+      default:
+        i2s_frequency = EXTERNAL_CLOCK_VALUE;
+        break;
+    }
+  }
+
+  return i2s_frequency;
+}
+
+/**
+  * @brief  Return LPTIMx clock frequency
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  * @retval LPTIM clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
+  */
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
+{
+  uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
+
+  if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
+  {
+    /* LPTIM1CLK clock frequency */
+    switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+    {
+      case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */
+        if (LL_RCC_LSI_IsReady())
+        {
+          lptim_frequency = LSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          lptim_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          lptim_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */
+      default:
+        lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+
+  return lptim_frequency;
+}
+
+/**
+  * @brief  Return SAIx clock frequency
+  * @param  SAIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE
+  * @retval SAI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
+  */
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
+{
+  uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
+
+  if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
+  {
+    /* SAI1CLK clock frequency */
+    switch (LL_RCC_GetSAIClockSource(SAIxSource))
+    {
+      case LL_RCC_SAI1_CLKSOURCE_PLLSAI:    /* PLLSAI clock used as SAI1 clock source */
+        if (LL_RCC_PLLSAI_IsReady())
+        {
+          sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
+        }
+        break;
+
+      case LL_RCC_SAI1_CLKSOURCE_PLLI2S:    /* PLLI2S clock used as SAI1 clock source */
+        if (LL_RCC_PLLI2S_IsReady())
+        {
+          sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
+        }
+        break;
+
+#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
+      case LL_RCC_SAI1_CLKSOURCE_PLLSRC:
+        switch (LL_RCC_PLL_GetMainSource())
+        {
+           case LL_RCC_PLLSOURCE_HSE:       /* HSE clock used as SAI1 clock source */
+             if (LL_RCC_HSE_IsReady())
+             {
+               sai_frequency = HSE_VALUE;
+             }
+             break;
+
+           case LL_RCC_PLLSOURCE_HSI:       /* HSI clock used as SAI1 clock source */
+           default:
+             if (LL_RCC_HSI_IsReady())
+             {
+               sai_frequency = HSI_VALUE;
+             }
+             break;
+        }
+        break;
+#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
+      case LL_RCC_SAI1_CLKSOURCE_PIN:        /* External input clock used as SAI1 clock source */
+        sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+        break;
+
+      default:
+        break;
+    }
+  }
+  else
+  {
+    if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
+    {
+      /* SAI2CLK clock frequency */
+      switch (LL_RCC_GetSAIClockSource(SAIxSource))
+      {
+      case LL_RCC_SAI2_CLKSOURCE_PLLSAI:    /* PLLSAI clock used as SAI2 clock source */
+        if (LL_RCC_PLLSAI_IsReady())
+        {
+          sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
+        }
+        break;
+
+      case LL_RCC_SAI2_CLKSOURCE_PLLI2S:    /* PLLI2S clock used as SAI2 clock source */
+        if (LL_RCC_PLLI2S_IsReady())
+        {
+          sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
+        }
+        break;
+
+#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
+      case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
+        switch (LL_RCC_PLL_GetMainSource())
+        {
+           case LL_RCC_PLLSOURCE_HSE:       /* HSE clock used as SAI2 clock source */
+             if (LL_RCC_HSE_IsReady())
+             {
+               sai_frequency = HSE_VALUE;
+             }
+             break;
+
+           case LL_RCC_PLLSOURCE_HSI:       /* HSI clock used as SAI2 clock source */
+           default:
+             if (LL_RCC_HSI_IsReady())
+             {
+               sai_frequency = HSI_VALUE;
+             }
+             break;
+        }
+        break;
+#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
+        case LL_RCC_SAI2_CLKSOURCE_PIN:      /* External input clock used as SAI2 clock source */
+          sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
+          break;
+
+      default:
+        break;
+      }
+    }
+  }
+
+  return sai_frequency;
+}
+
+/**
+  * @brief  Return SDMMCx clock frequency
+  * @param  SDMMCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval SDMMC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLL is not ready
+  */
+uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
+{
+  uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
+
+  if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE)
+  {
+    /* SDMMC1CLK clock frequency */
+    switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
+    {
+      case LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK:        /* PLL48 clock used as SDMMC1 clock source */
+        switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
+        {
+          case LL_RCC_CK48M_CLKSOURCE_PLL:         /* PLL clock used as 48Mhz domain clock */
+            if (LL_RCC_PLL_IsReady())
+            {
+              sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
+            }
+          break;
+
+          case LL_RCC_CK48M_CLKSOURCE_PLLSAI:      /* PLLSAI clock used as 48Mhz domain clock */
+          default:
+            if (LL_RCC_PLLSAI_IsReady())
+            {
+              sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
+            }
+            break;
+        }
+        break;
+
+      case LL_RCC_SDMMC1_CLKSOURCE_SYSCLK:        /* PLL clock used as SDMMC1 clock source */
+      default:
+      sdmmc_frequency = RCC_GetSystemClockFreq();
+      break;
+    }
+  }
+#if defined(SDMMC2)
+  else
+  {
+     /* SDMMC2CLK clock frequency */
+     switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
+     {
+       case LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK:        /* PLL48 clock used as SDMMC2 clock source */
+         switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
+         {
+           case LL_RCC_CK48M_CLKSOURCE_PLL:         /* PLL clock used as 48Mhz domain clock */
+             if (LL_RCC_PLL_IsReady())
+             {
+               sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
+             }
+           break;
+
+           case LL_RCC_CK48M_CLKSOURCE_PLLSAI:      /* PLLSAI clock used as 48Mhz domain clock */
+           default:
+             if (LL_RCC_PLLSAI_IsReady())
+             {
+               sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
+             }
+             break;
+         }
+         break;
+
+       case LL_RCC_SDMMC2_CLKSOURCE_SYSCLK:        /* PLL clock used as SDMMC2 clock source */
+       default:
+       sdmmc_frequency = RCC_GetSystemClockFreq();
+       break;
+     }
+  }
+#endif /* SDMMC2 */
+
+  return sdmmc_frequency;
+}
+
+/**
+  * @brief  Return RNGx clock frequency
+  * @param  RNGxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval RNG clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
+{
+  uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
+
+  /* RNGCLK clock frequency */
+  switch (LL_RCC_GetRNGClockSource(RNGxSource))
+  {
+    case LL_RCC_RNG_CLKSOURCE_PLL:           /* PLL clock used as RNG clock source */
+      if (LL_RCC_PLL_IsReady())
+      {
+        rng_frequency = RCC_PLL_GetFreqDomain_48M();
+      }
+      break;
+
+    case LL_RCC_RNG_CLKSOURCE_PLLSAI:       /* PLLSAI clock used as RNG clock source */
+    default:
+      if (LL_RCC_PLLSAI_IsReady())
+      {
+        rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
+      }
+      break;
+  }
+
+  return rng_frequency;
+}
+
+#if defined(CEC)
+/**
+  * @brief  Return CEC clock frequency
+  * @param  CECxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE
+  * @retval CEC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+  */
+uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
+{
+  uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
+
+  /* CECCLK clock frequency */
+  switch (LL_RCC_GetCECClockSource(CECxSource))
+  {
+    case LL_RCC_CEC_CLKSOURCE_LSE:           /* CEC Clock is LSE Osc. */
+      if (LL_RCC_LSE_IsReady())
+      {
+        cec_frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_CEC_CLKSOURCE_HSI_DIV488:    /* CEC Clock is HSI Osc. */
+    default:
+      if (LL_RCC_HSI_IsReady())
+      {
+        cec_frequency = HSI_VALUE/488U;
+      }
+      break;
+  }
+
+  return cec_frequency;
+}
+#endif /* CEC */
+
+/**
+  * @brief  Return USBx clock frequency
+  * @param  USBxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval USB clock frequency (in Hz)
+  */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+  uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+
+  /* USBCLK clock frequency */
+  switch (LL_RCC_GetUSBClockSource(USBxSource))
+  {
+    case LL_RCC_USB_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */
+      if (LL_RCC_PLL_IsReady())
+      {
+        usb_frequency = RCC_PLL_GetFreqDomain_48M();
+      }
+      break;
+
+    case LL_RCC_USB_CLKSOURCE_PLLSAI:       /* PLLSAI clock used as USB clock source */
+    default:
+      if (LL_RCC_PLLSAI_IsReady())
+      {
+        usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
+      }
+      break;
+  }
+
+  return usb_frequency;
+}
+
+#if defined(DFSDM1_Channel0)
+/**
+  * @brief  Return DFSDMx clock frequency
+  * @param  DFSDMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+  * @retval DFSDM clock frequency (in Hz)
+  */
+uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
+{
+  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
+
+  /* DFSDM1CLK clock frequency */
+  switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
+  {
+    case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:     /* DFSDM1 Clock is SYSCLK */
+      dfsdm_frequency = RCC_GetSystemClockFreq();
+      break;
+
+    case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:      /* DFSDM1 Clock is PCLK2 */
+    default:
+      dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+      break;
+  }
+
+  return dfsdm_frequency;
+}
+
+/**
+  * @brief  Return DFSDMx Audio clock frequency
+  * @param  DFSDMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+  * @retval DFSDM clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
+{
+  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
+
+  /* DFSDM1CLK clock frequency */
+  switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
+  {
+    case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1:     /* SAI1 clock used as DFSDM1 audio clock */
+      dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
+      break;
+
+    case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2:     /* SAI2 clock used as DFSDM1 audio clock */
+    default:
+      dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE);
+      break;
+  }
+
+  return dfsdm_frequency;
+}
+#endif /* DFSDM1_Channel0 */
+
+#if defined(DSI)
+/**
+  * @brief  Return DSI clock frequency
+  * @param  DSIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE
+  * @retval DSI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
+  */
+uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
+{
+  uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
+
+  /* DSICLK clock frequency */
+  switch (LL_RCC_GetDSIClockSource(DSIxSource))
+  {
+    case LL_RCC_DSI_CLKSOURCE_PLL:     /* DSI Clock is PLL Osc. */
+      if (LL_RCC_PLL_IsReady())
+      {
+        dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
+      }
+      break;
+
+    case LL_RCC_DSI_CLKSOURCE_PHY:    /* DSI Clock is DSI physical clock. */
+    default:
+      dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+      break;
+  }
+
+  return dsi_frequency;
+}
+#endif /* DSI */
+
+#if defined(LTDC)
+/**
+  * @brief  Return LTDC clock frequency
+  * @param  LTDCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LTDC_CLKSOURCE
+  * @retval LTDC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
+  */
+uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
+{
+  uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
+
+  if (LL_RCC_PLLSAI_IsReady())
+  {
+     ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
+  }
+
+  return ltdc_frequency;
+}
+#endif /* LTDC */
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Return SPDIFRX clock frequency
+  * @param  SPDIFRXxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
+  * @retval SPDIFRX clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
+{
+  uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
+
+  if (LL_RCC_PLLI2S_IsReady())
+  {
+     spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
+  }
+
+  return spdifrx_frequency;
+}
+#endif /* SPDIFRX */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Return SYSTEM clock frequency
+  * @retval SYSTEM clock frequency (in Hz)
+  */
+uint32_t RCC_GetSystemClockFreq(void)
+{
+  uint32_t frequency = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (LL_RCC_GetSysClkSource())
+  {
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
+      frequency = HSI_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
+      frequency = HSE_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
+      frequency = RCC_PLL_GetFreqDomain_SYS();
+      break;
+
+    default:
+      frequency = HSI_VALUE;
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return HCLK clock frequency
+  * @param  SYSCLK_Frequency SYSCLK clock frequency
+  * @retval HCLK clock frequency (in Hz)
+  */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+  /* HCLK clock frequency */
+  return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+  * @brief  Return PCLK1 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK1 clock frequency */
+  return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+  * @brief  Return PCLK2 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK2 clock frequency */
+  return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+  * @brief  Return PLL clock frequency used for system domain
+  * @retval PLL clock frequency (in Hz)
+  */
+uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+     SYSCLK = PLL_VCO / PLLP
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = HSI_VALUE;
+      break;
+  }
+  return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
+}
+
+/**
+  * @brief  Return PLL clock frequency used for 48 MHz domain
+  * @retval PLL clock frequency (in Hz)
+  */
+uint32_t RCC_PLL_GetFreqDomain_48M(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
+     48M Domain clock = PLL_VCO / PLLQ
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = HSI_VALUE;
+      break;
+  }
+  return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
+}
+
+#if defined(DSI)
+/**
+  * @brief  Return PLL clock frequency used for DSI clock
+  * @retval PLL clock frequency (in Hz)
+  */
+uint32_t RCC_PLL_GetFreqDomain_DSI(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+     DSICLK = PLL_VCO / PLLR
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+    default:
+      pllinputfreq = HSI_VALUE;
+      break;
+  }
+  return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
+}
+#endif /* DSI */
+
+/**
+  * @brief  Return PLLSAI clock frequency used for SAI1 and SAI2 domains
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
+     SAI1 and SAI2 domains clock  = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = HSI_VALUE;
+      break;
+  }
+  return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
+}
+
+/**
+  * @brief  Return PLLSAI clock frequency used for 48Mhz domain
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
+     48M Domain clock  = PLLSAI_VCO / PLLSAIP
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = HSI_VALUE;
+      break;
+  }
+  return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
+}
+
+#if defined(LTDC)
+/**
+  * @brief  Return PLLSAI clock frequency used for LTDC domain
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
+     LTDC Domain clock  = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = HSI_VALUE;
+      break;
+  }
+  return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
+}
+#endif /* LTDC */
+
+/**
+  * @brief  Return PLLI2S clock frequency used for SAI1 and SAI2 domains
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
+     SAI1 and SAI2 domains clock  = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLI2S clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLI2S clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = HSI_VALUE;
+      break;
+  }
+  return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
+}
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Return PLLI2S clock frequency used for SPDIFRX domain
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
+     SPDIFRX Domain clock  = PLLI2S_VCO / PLLI2SP
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLI2S clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLI2S clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = HSI_VALUE;
+      break;
+  }
+
+  return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
+}
+#endif /* SPDIFRX */
+
+/**
+  * @brief  Return PLLI2S clock frequency used for I2S domain
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
+     I2S Domain clock  = PLLI2S_VCO / PLLI2SR
+  */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLI2S clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLI2S clock source */
+    default:
+      pllinputfreq = HSI_VALUE;
+      break;
+  }
+  return __LL_RCC_CALC_PLLI2S_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+                                        LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c
new file mode 100644
index 0000000..82893db
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c
@@ -0,0 +1,1578 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_sdmmc.c
+  * @author  MCD Application Team
+  * @brief   SDMMC Low Layer HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the SDMMC peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                       ##### SDMMC peripheral features #####
+  ==============================================================================        
+    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
+         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
+         devices.
+    
+    [..] The SDMMC features include the following:
+         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
+             for three different databus modes: 1-bit (default), 4-bit and 8-bit
+         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
+         (+) Full compliance with SD Memory Card Specifications Version 2.0
+         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
+             different data bus modes: 1-bit (default) and 4-bit
+         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
+             Rev1.1)
+         (+) Data transfer up to 48 MHz for the 8 bit mode
+         (+) Data and command output enable signals to control external bidirectional drivers
+   
+                           ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver is a considered as a driver of service for external devices drivers 
+      that interfaces with the SDMMC peripheral.
+      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs 
+      is used in the device's driver to perform SDMMC operations and functionalities.
+   
+      This driver is almost transparent for the final user, it is only used to implement other
+      functionalities of the external device.
+   
+    [..]
+      (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,
+          PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the
+          PLL is well configured.
+          The SDMMC peripheral uses two clock signals:
+          (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
+          (++) APB2 bus clock (PCLK2)
+       
+          -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
+               Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
+  
+      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
+          peripheral.
+
+      (+) Enable the Power ON State using the SDMMC_PowerState_ON() 
+          function and disable it using the function SDMMC_PowerState_OFF().
+                
+      (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.
+  
+      (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT() 
+          and __SDMMC_DISABLE_IT() if you need to use interrupt mode. 
+  
+      (+) When using the DMA mode 
+          (++) Configure the DMA in the MSP layer of the external device
+          (++) Active the needed channel Request 
+          (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro
+               __SDMMC_DMA_DISABLE().
+  
+      (+) To control the CPSM (Command Path State Machine) and send 
+          commands to the card use the SDMMC_SendCommand(), 
+          SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
+          to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according 
+          to the selected command to be sent.
+          The parameters that should be filled are:
+           (++) Command Argument
+           (++) Command Index
+           (++) Command Response type
+           (++) Command Wait
+           (++) CPSM Status (Enable or Disable).
+  
+          -@@- To check if the command is well received, read the SDMMC_CMDRESP
+              register using the SDMMC_GetCommandResponse().
+              The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
+              SDMMC_GetResponse() function.
+  
+      (+) To control the DPSM (Data Path State Machine) and send/receive 
+           data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), 
+          SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.
+  
+    *** Read Operations ***
+    =======================
+    [..]
+      (#) First, user has to fill the data structure (pointer to
+          SDMMC_DataInitTypeDef) according to the selected data type to be received.
+          The parameters that should be filled are:
+           (++) Data TimeOut
+           (++) Data Length
+           (++) Data Block size
+           (++) Data Transfer direction: should be from card (To SDMMC)
+           (++) Data Transfer mode
+           (++) DPSM Status (Enable or Disable)
+                                     
+      (#) Configure the SDMMC resources to receive the data from the card
+          according to selected transfer mode (Refer to Step 8, 9 and 10).
+  
+      (#) Send the selected Read command (refer to step 11).
+                    
+      (#) Use the SDMMC flags/interrupts to check the transfer status.
+  
+    *** Write Operations ***
+    ========================
+    [..]
+     (#) First, user has to fill the data structure (pointer to
+         SDMMC_DataInitTypeDef) according to the selected data type to be received.
+         The parameters that should be filled are:
+          (++) Data TimeOut
+          (++) Data Length
+          (++) Data Block size
+          (++) Data Transfer direction:  should be to card (To CARD)
+          (++) Data Transfer mode
+          (++) DPSM Status (Enable or Disable)
+  
+     (#) Configure the SDMMC resources to send the data to the card according to 
+         selected transfer mode.
+                     
+     (#) Send the selected Write command.
+                    
+     (#) Use the SDMMC flags/interrupts to check the transfer status.
+       
+    *** Command management operations ***
+    =====================================
+    [..]
+     (#) The commands used for Read/Write/Erase operations are managed in 
+         separate functions. 
+         Each function allows to send the needed command with the related argument,
+         then check the response.
+         By the same approach, you could implement a command and check the response.
+  
+  @endverbatim
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+#if defined(SDMMC1)
+
+/** @addtogroup STM32F7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SDMMC_LL SDMMC Low Layer
+  * @brief Low layer module for SD
+  * @{
+  */
+
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization/de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SDMMC according to the specified
+  *         parameters in the SDMMC_InitTypeDef and create the associated handle.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Init: SDMMC initialization structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
+  assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); 
+  assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
+  
+  /* Set SDMMC configuration parameters */
+  tmpreg |= (Init.ClockEdge           |\
+             Init.ClockBypass         |\
+             Init.ClockPowerSave      |\
+             Init.BusWide             |\
+             Init.HardwareFlowControl |\
+             Init.ClockDiv
+             ); 
+  
+  /* Write to SDMMC CLKCR */
+  MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);  
+
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### I/O operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the SDMMC data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read data (word) from Rx FIFO in blocking mode (polling) 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
+{
+  /* Read data from Rx FIFO */ 
+  return (SDMMCx->FIFO);
+}
+
+/**
+  * @brief  Write data (word) to Tx FIFO in blocking mode (polling) 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  pWriteData: pointer to data to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
+{ 
+  /* Write data to FIFO */ 
+  SDMMCx->FIFO = *pWriteData;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the SDMMC data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set SDMMC Power state to ON. 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
+{  
+  /* Set power state to ON */ 
+  SDMMCx->POWER = SDMMC_POWER_PWRCTRL;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set SDMMC Power state to OFF. 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
+{
+  /* Set power state to OFF */
+  SDMMCx->POWER = (uint32_t)0x00000000;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get SDMMC Power state. 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Power status of the controller. The returned value can be one of the 
+  *         following values:
+  *            - 0x00: Power OFF
+  *            - 0x02: Power UP
+  *            - 0x03: Power ON 
+  */
+uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)  
+{
+  return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
+}
+
+/**
+  * @brief  Configure the SDMMC command path according to the specified parameters in
+  *         SDMMC_CmdInitTypeDef structure and send the command 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Command: pointer to a SDMMC_CmdInitTypeDef structure that contains 
+  *         the configuration information for the SDMMC command
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
+  assert_param(IS_SDMMC_RESPONSE(Command->Response));
+  assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
+  assert_param(IS_SDMMC_CPSM(Command->CPSM));
+
+  /* Set the SDMMC Argument value */
+  SDMMCx->ARG = Command->Argument;
+
+  /* Set SDMMC command parameters */
+  tmpreg |= (uint32_t)(Command->CmdIndex         |\
+                       Command->Response         |\
+                       Command->WaitForInterrupt |\
+                       Command->CPSM);
+  
+  /* Write to SDMMC CMD register */
+  MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Return the command index of last command for which response received
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Command index of the last command response received
+  */
+uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
+{
+  return (uint8_t)(SDMMCx->RESPCMD);
+}
+
+
+/**
+  * @brief  Return the response received from the card for the last command
+  * @param  SDMMCx: Pointer to SDMMC register base    
+  * @param  Response: Specifies the SDMMC response register. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_RESP1: Response Register 1
+  *            @arg SDMMC_RESP2: Response Register 2
+  *            @arg SDMMC_RESP3: Response Register 3
+  *            @arg SDMMC_RESP4: Response Register 4  
+  * @retval The Corresponding response register value
+  */
+uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_RESP(Response));
+  
+  /* Get the response */
+  tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response;
+  
+  return (*(__IO uint32_t *) tmp);
+}  
+
+/**
+  * @brief  Configure the SDMMC data path according to the specified 
+  *         parameters in the SDMMC_DataInitTypeDef.
+  * @param  SDMMCx: Pointer to SDMMC register base  
+  * @param  Data : pointer to a SDMMC_DataInitTypeDef structure 
+  *         that contains the configuration information for the SDMMC data.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
+  assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
+  assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
+  assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
+  assert_param(IS_SDMMC_DPSM(Data->DPSM));
+
+  /* Set the SDMMC Data TimeOut value */
+  SDMMCx->DTIMER = Data->DataTimeOut;
+
+  /* Set the SDMMC DataLength value */
+  SDMMCx->DLEN = Data->DataLength;
+
+  /* Set the SDMMC data configuration parameters */
+  tmpreg |= (uint32_t)(Data->DataBlockSize |\
+                       Data->TransferDir   |\
+                       Data->TransferMode  |\
+                       Data->DPSM);
+  
+  /* Write to SDMMC DCTRL */
+  MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->DCOUNT);
+}
+
+/**
+  * @brief  Get the FIFO data
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval Data received
+  */
+uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->FIFO);
+}
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDMMCx: Pointer to SDMMC register base   
+  * @param  SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
+  *          This parameter can be:
+  *            @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
+  *            @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
+  * @retval None
+  */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
+
+  /* Set SDMMC read wait mode */
+  MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SDMMC_LL_Group4 Command management functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                   ##### Commands management functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the needed commands.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send the Data Block Length command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)BlockSize;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Single Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Multi Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Single Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Multi Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command for SD and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command for SD and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Erase command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Stop Transfer command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD12 STOP_TRANSMISSION  */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Select Deselect command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @param  addr: Address of the card to be selected  
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD7 SDMMC_SEL_DESEL_CARD */
+  sdmmc_cmdinit.Argument         = (uint32_t)Addr;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Go Idle State command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_NO;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdError(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Operating Condition command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD8 to verify SD card interface operating condition */
+  /* Argument: - [31:12]: Reserved (shall be set to '0')
+  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+  - [7:0]: Check Pattern (recommended 0xAA) */
+  /* CMD Response: R7 */
+  sdmmc_cmdinit.Argument         = SDMMC_CHECK_PATTERN;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp7(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Application command to verify that that the next command 
+  *         is an application specific com-mand rather than a standard command
+  *         and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @param  Argument: Command Argument 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = (uint32_t)Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  /* If there is a HAL_ERROR, it is a MMC card, else
+  it is a SD card: SD card 2.0 (voltage range mismatch)
+     or SD card 1.x */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the command asking the accessed card to send its operating 
+  *         condition register (OCR)
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = SDMMC_VOLTAGE_WINDOW_SD | Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Bus Width command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @param  BusWidth: BusWidth
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = (uint32_t)BusWidth;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send SCR command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD51 SD_APP_SEND_SCR */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CID command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD2 ALL_SEND_CID */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD9 SEND_CSD */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @param  pRCA: Card RCA  
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD3 SD_CMD_SET_REL_ADDR */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Set Relative Address command to MMC card (not SD card).
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @param  RCA Card RCA
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD3 SD_CMD_SET_REL_ADDR */
+  sdmmc_cmdinit.Argument         = ((uint32_t)RCA << 16U);
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status register command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Sends host capacity support information and activates the card's 
+  *         initialization process. Send SDMMC_CMD_SEND_OP_COND command
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
+  /* CMD Response: R1 */
+  sdmmc_cmdinit.Argument         = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send EXT_CSD command and check the response.
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @param  Argument Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD9 SEND_CSD */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions
+ *  @brief   Responses functions
+ *
+@verbatim
+ ===============================================================================
+                   ##### Responses management functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the needed responses.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Checks for error conditions for R1 response.
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @param  SD_CMD: The sent command index  
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
+{
+  uint32_t response_r1;
+  uint32_t sta_reg;
+  
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The Timeout is expressed in ms */
+  uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+    
+  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+  
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  
+  /* Check response received is of desired command */
+  if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  
+  /* We have received response, retrieve it for analysis  */
+  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+  
+  if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+  {
+    return SDMMC_ERROR_NONE;
+  }
+  else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+  }
+  else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+  {
+    return SDMMC_ERROR_ADDR_MISALIGNED;
+  }
+  else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+  {
+    return SDMMC_ERROR_BLOCK_LEN_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+  {
+    return SDMMC_ERROR_ERASE_SEQ_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+  {
+    return SDMMC_ERROR_BAD_ERASE_PARAM;
+  }
+  else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+  {
+    return SDMMC_ERROR_WRITE_PROT_VIOLATION;
+  }
+  else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+  {
+    return SDMMC_ERROR_CARD_ECC_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+  {
+    return SDMMC_ERROR_CC_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+  {
+    return SDMMC_ERROR_STREAM_READ_UNDERRUN;
+  }
+  else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
+  }
+  else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+  {
+    return SDMMC_ERROR_CID_CSD_OVERWRITE;
+  }
+  else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+  {
+    return SDMMC_ERROR_WP_ERASE_SKIP;
+  }
+  else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+  {
+    return SDMMC_ERROR_CARD_ECC_DISABLED;
+  }
+  else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+  {
+    return SDMMC_ERROR_ERASE_RESET;
+  }
+  else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+  {
+    return SDMMC_ERROR_AKE_SEQ_ERR;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R2 (CID or CSD) response.
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+    
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  }
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R3 (OCR) response.
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+    
+  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else
+  {  
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  }
+  
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R6 (RCA) response.
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @param  SD_CMD: The sent command index
+  * @param  pRCA: Pointer to the variable that will contain the SD card relative 
+  *         address RCA   
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
+{
+  uint32_t response_r1;
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+    
+  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+  
+  /* Check response received is of desired command */
+  if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  
+  /* We have received response, retrieve it.  */
+  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+  
+  if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+  {
+    *pRCA = (uint16_t) (response_r1 >> 16);
+    
+    return SDMMC_ERROR_NONE;
+  }
+  else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R7 response.
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+    
+  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+  
+  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
+  }
+  
+  return SDMMC_ERROR_NONE;
+  
+}
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/  
+/** @addtogroup SD_Private_Functions
+  * @{
+  */
+    
+/**
+  * @brief  Checks for error conditions for CMD0.
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
+{
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    
+  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
+  
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  
+  return SDMMC_ERROR_NONE;
+}
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* SDMMC1 */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c
new file mode 100644
index 0000000..718c038
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c
@@ -0,0 +1,577 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_spi.c
+  * @author  MCD Application Team
+  * @brief   SPI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_spi.h"
+#include "stm32f7xx_ll_bus.h"
+#include "stm32f7xx_ll_rcc.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
+
+/** @addtogroup SPI_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Constants SPI Private Constants
+  * @{
+  */
+/* SPI registers Masks */
+#define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
+                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
+                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
+                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
+                                            SPI_CR1_BIDIMODE)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+  * @{
+  */
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
+                                                 || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
+                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+                                   || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+                                       || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+                                    || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT)          \
+                                  || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+                                  || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+                                       || ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+                                             || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SPI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the SPI registers to their default reset values.
+  * @param  SPIx SPI Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are de-initialized
+  *          - ERROR: SPI registers are not de-initialized
+  */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+  if (SPIx == SPI1)
+  {
+    /* Force reset of SPI clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+    /* Release reset of SPI clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+    status = SUCCESS;
+  }
+#endif /* SPI1 */
+#if defined(SPI2)
+  if (SPIx == SPI2)
+  {
+    /* Force reset of SPI clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+    /* Release reset of SPI clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+    status = SUCCESS;
+  }
+#endif /* SPI2 */
+#if defined(SPI3)
+  if (SPIx == SPI3)
+  {
+    /* Force reset of SPI clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+    /* Release reset of SPI clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+    status = SUCCESS;
+  }
+#endif /* SPI3 */
+#if defined(SPI4)
+  if (SPIx == SPI4)
+  {
+    /* Force reset of SPI clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+    /* Release reset of SPI clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+    status = SUCCESS;
+  }
+#endif /* SPI4 */
+#if defined(SPI5)
+  if (SPIx == SPI5)
+  {
+    /* Force reset of SPI clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
+
+    /* Release reset of SPI clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
+
+    status = SUCCESS;
+  }
+#endif /* SPI5 */
+#if defined(SPI6)
+  if (SPIx == SPI6)
+  {
+    /* Force reset of SPI clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
+
+    /* Release reset of SPI clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
+
+    status = SUCCESS;
+  }
+#endif /* SPI6 */
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+  *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  SPIx SPI Instance
+  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+  */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the SPI Instance SPIx*/
+  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+  /* Check the SPI parameters from SPI_InitStruct*/
+  assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+  assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+  assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+  assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+  assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+  assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+  assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+  assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+  assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+  if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+  {
+    /*---------------------------- SPIx CR1 Configuration ------------------------
+     * Configure SPIx CR1 with parameters:
+     * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+     * - Master/Slave Mode:  SPI_CR1_MSTR bit
+     * - ClockPolarity:      SPI_CR1_CPOL bit
+     * - ClockPhase:         SPI_CR1_CPHA bit
+     * - NSS management:     SPI_CR1_SSM bit
+     * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+     * - BitOrder:           SPI_CR1_LSBFIRST bit
+     * - CRCCalculation:     SPI_CR1_CRCEN bit
+     */
+    MODIFY_REG(SPIx->CR1,
+               SPI_CR1_CLEAR_MASK,
+               SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
+               SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+               SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+               SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+
+    /*---------------------------- SPIx CR2 Configuration ------------------------
+     * Configure SPIx CR2 with parameters:
+     * - DataWidth:          DS[3:0] bits
+     * - NSS management:     SSOE bit
+     */
+    MODIFY_REG(SPIx->CR2,
+               SPI_CR2_DS | SPI_CR2_SSOE,
+               SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
+
+    /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
+    if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
+    {
+      LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
+    }
+
+    /*---------------------------- SPIx CRCPR Configuration ----------------------
+     * Configure SPIx CRCPR with parameters:
+     * - CRCPoly:            CRCPOLY[15:0] bits
+     */
+    if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+    {
+      assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+      LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+    }
+    status = SUCCESS;
+  }
+
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
+  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+  * whose fields will be set to default values.
+  * @retval None
+  */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+  /* Set SPI_InitStruct fields to default values */
+  SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+  SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
+  SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
+  SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
+  SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
+  SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
+  SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
+  SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
+  SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
+  SPI_InitStruct->CRCPoly           = 7U;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2S_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Constants I2S Private Constants
+  * @{
+  */
+/* I2S registers Masks */
+#define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
+                                            SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
+                                            SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
+
+#define I2S_I2SPR_CLEAR_MASK               0x0002U
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Macros I2S Private Macros
+  * @{
+  */
+
+#define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)             \
+                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
+                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+
+#define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
+                                          || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+
+#define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)      \
+                                          || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
+                                          || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
+                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+
+#define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)     \
+                                          || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
+                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
+                                          || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)       \
+                                          && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+                                         || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
+
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
+                                               || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2S_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the SPI/I2S registers to their default reset values.
+  * @param  SPIx SPI Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are de-initialized
+  *          - ERROR: SPI registers are not de-initialized
+  */
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_DeInit(SPIx);
+}
+
+/**
+  * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
+  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+  *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  SPIx SPI Instance
+  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are Initialized
+  *          - ERROR: SPI registers are not Initialized
+  */
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+  uint32_t i2sdiv = 2U;
+  uint32_t i2sodd = 0U;
+  uint32_t packetlength = 1U;
+  uint32_t tmp;
+  uint32_t sourceclock;
+  ErrorStatus status = ERROR;
+
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+  assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+  assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+  assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+  assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+  assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+  assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+  if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
+  {
+    /*---------------------------- SPIx I2SCFGR Configuration --------------------
+     * Configure SPIx I2SCFGR with parameters:
+     * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
+     * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+     * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+     * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+     */
+
+    /* Write to SPIx I2SCFGR */
+    MODIFY_REG(SPIx->I2SCFGR,
+               I2S_I2SCFGR_CLEAR_MASK,
+               I2S_InitStruct->Mode | I2S_InitStruct->Standard |
+               I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+               SPI_I2SCFGR_I2SMOD);
+
+    /*---------------------------- SPIx I2SPR Configuration ----------------------
+     * Configure SPIx I2SPR with parameters:
+     * - MCLKOutput:    SPI_I2SPR_MCKOE bit
+     * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
+     */
+
+    /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+     * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
+     */
+    if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+    {
+      /* Check the frame length (For the Prescaler computing)
+       * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+       */
+      if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+      {
+        /* Packet length is 32 bits */
+        packetlength = 2U;
+      }
+
+      /* If an external I2S clock has to be used, the specific define should be set
+      in the project configuration or in the stm32f7xx_ll_rcc.h file */
+      /* Get the I2S source clock value */
+      sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
+
+      /* Compute the Real divider depending on the MCLK output state with a floating point */
+      if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+      {
+        /* MCLK output is enabled */
+        tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+      }
+      else
+      {
+        /* MCLK output is disabled */
+        tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+      }
+
+      /* Remove the floating point */
+      tmp = tmp / 10U;
+
+      /* Check the parity of the divider */
+      i2sodd = (tmp & (uint16_t)0x0001U);
+
+      /* Compute the i2sdiv prescaler */
+      i2sdiv = ((tmp - i2sodd) / 2U);
+
+      /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+      i2sodd = (i2sodd << 8U);
+    }
+
+    /* Test if the divider is 1 or 0 or greater than 0xFF */
+    if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+    {
+      /* Set the default values */
+      i2sdiv = 2U;
+      i2sodd = 0U;
+    }
+
+    /* Write to SPIx I2SPR register the computed value */
+    WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
+
+    status = SUCCESS;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
+  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+  *         whose fields will be set to default values.
+  * @retval None
+  */
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+  /*--------------- Reset I2S init structure parameters values -----------------*/
+  I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
+  I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
+  I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
+  I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
+  I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
+  I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
+}
+
+/**
+  * @brief  Set linear and parity prescaler.
+  * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+  *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+  * @param  SPIx SPI Instance
+  * @param  PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
+  * @param  PrescalerParity This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+  * @retval None
+  */
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+{
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+  assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+  assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+
+  /* Write to SPIx I2SPR */
+  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c
new file mode 100644
index 0000000..1e69b77
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c
@@ -0,0 +1,1380 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_tim.h"
+#include "stm32f7xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7)
+
+/** @addtogroup TIM_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup TIM_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+
+#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
+
+#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+                                      || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+
+#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+                                         || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+
+#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
+                                          || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+
+#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+
+#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+
+#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+
+#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+
+#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+                                                  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+                                         || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+
+#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+                                         || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+
+#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
+                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
+                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+
+#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+                                          || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+
+#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+                                             || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
+                                           || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
+
+#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
+                                              || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
+                                                     || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_LL_Private_Functions TIM Private Functions
+  * @{
+  */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup TIM_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Set TIMx registers to their reset values.
+  * @param  TIMx Timer instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: invalid TIMx instance
+  */
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
+{
+  ErrorStatus result = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(TIMx));
+
+  if (TIMx == TIM1)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+  }
+  else if (TIMx == TIM2)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+  }
+#if defined(TIM3)
+  else if (TIMx == TIM3)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+  }
+#endif /* TIM3 */
+#if defined(TIM4)
+  else if (TIMx == TIM4)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
+  }
+#endif /* TIM4 */
+#if defined(TIM5)
+  else if (TIMx == TIM5)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
+  }
+#endif /* TIM5 */
+#if defined(TIM6)
+  else if (TIMx == TIM6)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+  }
+#endif /* TIM6 */
+#if defined (TIM7)
+  else if (TIMx == TIM7)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+  }
+#endif /* TIM7 */
+#if defined(TIM8)
+  else if (TIMx == TIM8)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
+  }
+#endif /* TIM8 */
+#if defined(TIM9)
+  else if (TIMx == TIM9)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
+  }
+#endif /* TIM9 */
+#if defined(TIM10)
+  else if (TIMx == TIM10)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
+  }
+#endif /* TIM10 */
+#if defined(TIM11)
+  else if (TIMx == TIM11)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
+  }
+#endif /* TIM11 */
+#if defined(TIM12)
+  else if (TIMx == TIM12)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
+  }
+#endif /* TIM12 */
+#if defined(TIM13)
+  else if (TIMx == TIM13)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
+  }
+#endif /* TIM13 */
+#if defined(TIM14)
+  else if (TIMx == TIM14)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
+  }
+#endif /* TIM14 */
+  else
+  {
+    result = ERROR;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Set the fields of the time base unit configuration data structure
+  *         to their default values.
+  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
+  * @retval None
+  */
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+  /* Set the default configuration */
+  TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
+  TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
+  TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
+  TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
+  TIM_InitStruct->RepetitionCounter = 0x00000000U;
+}
+
+/**
+  * @brief  Configure the TIMx time base unit.
+  * @param  TIMx Timer Instance
+  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
+  *         (TIMx time base unit configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+  uint32_t tmpcr1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+  assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+
+  tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+  }
+
+  /* Write to TIMx CR1 */
+  LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+
+  /* Set the Autoreload value */
+  LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+
+  /* Set the Prescaler value */
+  LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter value (if applicable) immediately */
+  LL_TIM_GenerateEvent_UPDATE(TIMx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the fields of the TIMx output channel configuration data
+  *         structure to their default values.
+  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
+  *         (the output channel configuration data structure)
+  * @retval None
+  */
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+  /* Set the default configuration */
+  TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
+  TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
+  TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
+  TIM_OC_InitStruct->CompareValue = 0x00000000U;
+  TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
+  TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
+  TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
+  TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+}
+
+/**
+  * @brief  Configure the TIMx output channel.
+  * @param  TIMx Timer Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
+  *         data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx output channel is initialized
+  *          - ERROR: TIMx output channel is not initialized
+  */
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+  ErrorStatus result = ERROR;
+
+  switch (Channel)
+  {
+    case LL_TIM_CHANNEL_CH1:
+      result = OC1Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH2:
+      result = OC2Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH3:
+      result = OC3Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH4:
+      result = OC4Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH5:
+      result = OC5Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH6:
+      result = OC6Config(TIMx, TIM_OC_InitStruct);
+      break;
+    default:
+      break;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Set the fields of the TIMx input channel configuration data
+  *         structure to their default values.
+  * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
+  *         data structure)
+  * @retval None
+  */
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Set the default configuration */
+  TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+  * @brief  Configure the TIMx input channel.
+  * @param  TIMx Timer Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
+  *         structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx output channel is initialized
+  *          - ERROR: TIMx output channel is not initialized
+  */
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+{
+  ErrorStatus result = ERROR;
+
+  switch (Channel)
+  {
+    case LL_TIM_CHANNEL_CH1:
+      result = IC1Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH2:
+      result = IC2Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH3:
+      result = IC3Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH4:
+      result = IC4Config(TIMx, TIM_IC_InitStruct);
+      break;
+    default:
+      break;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Fills each TIM_EncoderInitStruct field with its default value
+  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
+  *         configuration data structure)
+  * @retval None
+  */
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+  /* Set the default configuration */
+  TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
+  TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
+  TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+  * @brief  Configure the encoder interface of the timer instance.
+  * @param  TIMx Timer Instance
+  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
+  *         configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+
+  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Configure TI1 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+
+  /* Configure TI2 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+
+  /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Set encoder mode */
+  LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the fields of the TIMx Hall sensor interface configuration data
+  *         structure to their default values.
+  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
+  *         configuration data structure)
+  * @retval None
+  */
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+  /* Set the default configuration */
+  TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
+  TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
+  TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
+  TIM_HallSensorInitStruct->CommutationDelay  = 0U;
+}
+
+/**
+  * @brief  Configure the Hall sensor interface of the timer instance.
+  * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
+  *       to the TI1 input channel
+  * @note TIMx slave mode controller is configured in reset mode.
+          Selected internal trigger is TI1F_ED.
+  * @note Channel 1 is configured as input, IC1 is mapped on TRC.
+  * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
+  *       between 2 changes on the inputs. It gives information about motor speed.
+  * @note Channel 2 is configured in output PWM 2 mode.
+  * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
+  * @note OC2REF is selected as trigger output on TRGO.
+  * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
+  *       when TIMx operates in Hall sensor interface mode.
+  * @param  TIMx Timer Instance
+  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
+  *         interface configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+  assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+
+  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
+
+  /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
+  tmpcr2 |= TIM_CR2_TI1S;
+
+  /* OC2REF signal is used as trigger output (TRGO) */
+  tmpcr2 |= LL_TIM_TRGO_OC2REF;
+
+  /* Configure the slave mode controller */
+  tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
+  tmpsmcr |= LL_TIM_TS_TI1F_ED;
+  tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+
+  /* Configure input channel 1 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
+  tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+
+  /* Configure input channel 2 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
+  tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+
+  /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
+  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx SMCR */
+  LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  /* Write to TIMx CCR2 */
+  LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the fields of the Break and Dead Time configuration data structure
+  *         to their default values.
+  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+  *         data structure)
+  * @retval None
+  */
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+  /* Set the default configuration */
+  TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
+  TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
+  TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
+  TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
+  TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
+  TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
+  TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
+  TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
+  TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
+  TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
+  TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+}
+
+/**
+  * @brief  Configure the Break and Dead Time feature of the timer instance.
+  * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
+  *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
+  *  can be necessary to configure all of them during the first write access to
+  *  the TIMx_BDTR register.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @param  TIMx Timer Instance
+  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+  *         data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Break and Dead Time is initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+  uint32_t tmpbdtr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+  assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+  assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+  assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+  assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+  assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+  assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+  the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+
+  if (IS_TIM_BKIN2_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
+    assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
+    assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+
+    /* Set the BREAK2 input related BDTR bit-fields */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+  }
+
+  /* Set TIMx_BDTR */
+  LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+
+  return SUCCESS;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+  *  @brief   Private functions
+  * @{
+  */
+/**
+  * @brief  Configure the TIMx output channel 1.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+
+  /* Set the Output Compare Mode */
+  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+    assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+    assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+
+    /* Set the complementary output Polarity */
+    MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
+
+    /* Set the complementary output State */
+    MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
+
+    /* Set the complementary output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 2.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+    assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+    assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+
+    /* Set the complementary output Polarity */
+    MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
+
+    /* Set the complementary output State */
+    MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
+
+    /* Set the complementary output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 3.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+    assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+    assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+
+    /* Set the complementary output Polarity */
+    MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
+
+    /* Set the complementary output State */
+    MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
+
+    /* Set the complementary output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR2 */
+  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 4.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR2 */
+  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 5.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr3;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC5_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+  /* Disable the Channel 5: Reset the CC5E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CCMR3 register value */
+  tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+    /* Set the Output Idle state */
+    MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
+
+  }
+
+  /* Write to TIMx CCMR3 */
+  LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 6.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr3;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC6_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+  /* Disable the Channel 5: Reset the CC6E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CCMR3 register value */
+  tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+    /* Set the Output Idle state */
+    MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
+  }
+
+  /* Write to TIMx CCMR3 */
+  LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 1.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR1,
+             (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+             (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 2.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR1,
+             (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+             ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 3.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR2,
+             (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+  /* Select the Polarity and set the CC3E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+             ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 4.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR2,
+             (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+  /* Select the Polarity and set the CC4E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC4P | TIM_CCER_CC4NP),
+             ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+
+  return SUCCESS;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM8 || TIM2 || TIM3 ||  TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c
new file mode 100644
index 0000000..8e34112
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c
@@ -0,0 +1,451 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_usart.c
+  * @author  MCD Application Team
+  * @brief   USART LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_usart.h"
+#include "stm32f7xx_ll_rcc.h"
+#include "stm32f7xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \
+ || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8)
+
+/** @addtogroup USART_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Constants
+  * @{
+  */
+
+/* Definition of default baudrate value used for USART initialisation */
+#define USART_DEFAULT_BAUDRATE          (9600U)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+  * @{
+  */
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ *              divided by the smallest oversampling used on the USART (i.e. 8)    */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U)
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+                                       || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+                                       || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+                                          || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+                                          || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+                                             || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+                                                 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+                                           || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+                                              || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+                                            || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_1) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup USART_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize USART registers (Registers restored to their default values).
+  * @param  USARTx USART Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are de-initialized
+  *          - ERROR: USART registers are not de-initialized
+  */
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+
+  if (USARTx == USART1)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+  }
+  else if (USARTx == USART2)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+  }
+  else if (USARTx == USART3)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+  }
+  else if (USARTx == UART4)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+  }
+  else if (USARTx == UART5)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+  }
+  else if (USARTx == USART6)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
+  }
+  else if (USARTx == UART7)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
+  }
+  else if (USARTx == UART8)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize USART registers according to the specified
+  *         parameters in USART_InitStruct.
+  * @note   As some bits in USART configuration registers can only be written when
+  *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+  *         this function. Otherwise, ERROR result will be returned.
+  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+  * @param  USARTx USART Instance
+  * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
+  *         that contains the configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /*---------------------------- USART CR1 Configuration ---------------------
+     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
+     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+     */
+    MODIFY_REG(USARTx->CR1,
+               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+    /*---------------------------- USART CR2 Configuration ---------------------
+     * Configure USARTx CR2 (Stop bits) with parameters:
+     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+     */
+    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+    /*---------------------------- USART CR3 Configuration ---------------------
+     * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
+     *   USART_InitStruct->HardwareFlowControl value.
+     */
+    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+    /*---------------------------- USART BRR Configuration ---------------------
+     * Retrieve Clock frequency used for USART Peripheral
+     */
+    if (USARTx == USART1)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
+    }
+    else if (USARTx == USART2)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
+    }
+    else if (USARTx == USART3)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
+    }
+    else if (USARTx == UART4)
+    {
+      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
+    }
+    else if (USARTx == UART5)
+    {
+      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
+    }
+    else if (USARTx == USART6)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART6_CLKSOURCE);
+    }
+    else if (USARTx == UART7)
+    {
+      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART7_CLKSOURCE);
+    }
+    else if (USARTx == UART8)
+    {
+      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART8_CLKSOURCE);
+    }
+    else
+    {
+      /* Nothing to do, as error code is already assigned to ERROR value */
+    }
+
+    /* Configure the USART Baud Rate :
+       - valid baud rate value (different from 0) is required
+       - Peripheral clock as returned by RCC service, should be valid (different from 0).
+    */
+    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+        && (USART_InitStruct->BaudRate != 0U))
+    {
+      status = SUCCESS;
+      LL_USART_SetBaudRate(USARTx,
+                           periphclk,
+                           USART_InitStruct->OverSampling,
+                           USART_InitStruct->BaudRate);
+
+      /* Check BRR is greater than or equal to 16d */
+      assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+    }
+  }
+  /* Endif (=> USART not in Disabled state => return ERROR) */
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+  * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
+  *                         whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+  /* Set USART_InitStruct fields to default values */
+  USART_InitStruct->BaudRate            = USART_DEFAULT_BAUDRATE;
+  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
+  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
+  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
+  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
+  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+  * @brief  Initialize USART Clock related settings according to the
+  *         specified parameters in the USART_ClockInitStruct.
+  * @note   As some bits in USART configuration registers can only be written when
+  *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+  *         this function. Otherwise, ERROR result will be returned.
+  * @param  USARTx USART Instance
+  * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *         that contains the Clock configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers related to Clock settings are initialized according
+  *                     to USART_ClockInitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check USART Instance and Clock signal output parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /* If USART Clock signal is disabled */
+    if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
+    {
+      /* Deactivate Clock signal delivery :
+       * - Disable Clock Output:        USART_CR2_CLKEN cleared
+       */
+      LL_USART_DisableSCLKOutput(USARTx);
+    }
+    else
+    {
+      /* Ensure USART instance is USART capable */
+      assert_param(IS_USART_INSTANCE(USARTx));
+
+      /* Check clock related parameters */
+      assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+      assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+      assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+      /*---------------------------- USART CR2 Configuration -----------------------
+       * Configure USARTx CR2 (Clock signal related bits) with parameters:
+       * - Enable Clock Output:         USART_CR2_CLKEN set
+       * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+       * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+       * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+       */
+      MODIFY_REG(USARTx->CR2,
+                 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+                 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
+                 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+    }
+  }
+  /* Else (USART not in Disabled state => return ERROR */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+  * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *                              whose fields will be set to default values.
+  * @retval None
+  */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  /* Set LL_USART_ClockInitStruct fields with default values */
+  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
+  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput =
+                                                                                  LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput =
+                                                                                  LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput =
+                                                                                  LL_USART_CLOCK_DISABLE */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c
new file mode 100644
index 0000000..263566e
--- /dev/null
+++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c
@@ -0,0 +1,752 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_ll_utils.c
+  * @author  MCD Application Team
+  * @brief   UTILS LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_utils.h"
+#include "stm32f7xx_ll_rcc.h"
+#include "stm32f7xx_ll_system.h"
+#include "stm32f7xx_ll_pwr.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32F7xx_LL_Driver
+  * @{
+  */
+
+/** @addtogroup UTILS_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+  * @{
+  */
+#define UTILS_MAX_FREQUENCY_SCALE1  216000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2  180000000U       /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE3  144000000U       /*!< Maximum frequency for system clock at power scale3, in Hz */
+
+/* Defines used for PLL range */
+#define UTILS_PLLVCO_INPUT_MIN         950000U       /*!< Frequency min for PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_INPUT_MAX        2100000U       /*!< Frequency max for PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_OUTPUT_MIN     100000000U       /*!< Frequency min for PLLVCO output, in Hz  */
+#define UTILS_PLLVCO_OUTPUT_MAX     432000000U       /*!< Frequency max for PLLVCO output, in Hz  */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MAX     26000000U        /*!< Frequency max for HSE frequency, in Hz   */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#define UTILS_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
+#define UTILS_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
+#define UTILS_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
+#define UTILS_SCALE1_LATENCY4_FREQ  120000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
+#define UTILS_SCALE1_LATENCY5_FREQ  150000000U      /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
+#define UTILS_SCALE1_LATENCY6_FREQ  180000000U      /*!< HCLK frequency to set FLASH latency 6 in power scale 1  with over-drive mode */
+#define UTILS_SCALE1_LATENCY7_FREQ  210000000U      /*!< HCLK frequency to set FLASH latency 7 in power scale 1  with over-drive mode */
+#define UTILS_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
+#define UTILS_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
+#define UTILS_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
+#define UTILS_SCALE2_LATENCY4_FREQ  120000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
+#define UTILS_SCALE2_LATENCY5_FREQ  150000000U      /*!< HCLK frequency to set FLASH latency 5 in power scale 2  */
+#define UTILS_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
+#define UTILS_SCALE3_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
+#define UTILS_SCALE3_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
+#define UTILS_SCALE3_LATENCY4_FREQ  120000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 3  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2)  \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_3)  \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_4)  \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_5)  \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_6)  \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_7)  \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_8)  \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_9)  \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
+
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((50 <= (__VALUE__)) && ((__VALUE__) <= 432))
+
+#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
+                                        || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
+                                        || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
+                                        || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
+
+#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
+
+#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
+
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
+                                              (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
+                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+  * @{
+  */
+static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+                                               LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
+  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  HCLKFrequency HCLK frequency in Hz
+  * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+  * @retval None
+  */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+  /* Use frequency provided in argument */
+  LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+  * @brief  This function provides accurate delay (in milliseconds) based
+  *         on SysTick counter flag
+  * @note   When a RTOS is used, it is recommended to avoid using blocking delay
+  *         and use rather osDelay service.
+  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+  *         will configure Systick to 1ms
+  * @param  Delay specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+void LL_mDelay(uint32_t Delay)
+{
+  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
+  /* Add this code to indicate that local variable is not used */
+  ((void)tmp);
+
+  /* Add a period to guaranty minimum wait */
+  if(Delay < LL_MAX_DELAY)
+  {
+    Delay++;
+  }
+
+  while (Delay)
+  {
+    if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+    {
+      Delay--;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_EF_SYSTEM
+  *  @brief    System Configuration functions
+  *
+  @verbatim
+ ===============================================================================
+           ##### System Configuration functions #####
+ ===============================================================================
+    [..]
+         System, AHB and APB buses clocks configuration
+
+         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 216000000 Hz.
+  @endverbatim
+  @internal
+             Depending on the device voltage range, the maximum frequency should be
+             adapted accordingly:
+             (++) +------------------------------------------------------------------------------------------------+
+             (++) |  Wait states   |                           HCLK clock frequency (MHz)                          |
+             (++) |                |-------------------------------------------------------------------------------|
+             (++) |  (Latency)     |   voltage range   |   voltage range   |   voltage range   |   voltage range   |
+             (++) |                |    2.7V - 3.6V    |    2.4V - 2.7V    |    2.1V - 2.7V    |    1.8V - 2.1V    |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |0WS(1CPU cycle) |   0 < HCLK <= 30  |   0 < HCLK <= 24  |   0 < HCLK <= 22  |   0 < HCLK <= 20  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |1WS(2CPU cycle) |  30 < HCLK <= 60  |  24 < HCLK <= 48  |  22 < HCLK <= 44  |  20 < HCLK <= 44  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |2WS(3CPU cycle) |  60 < HCLK <= 90  |  48 < HCLK <= 72  |  44 < HCLK <= 66  |  40 < HCLK <= 60  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |3WS(4CPU cycle) |  90 < HCLK <= 120 |  72 < HCLK <= 96  |  66 < HCLK <= 88  |  60 < HCLK <= 80  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |4WS(5CPU cycle) | 120 < HCLK <= 150 |  96 < HCLK <= 120 |  88 < HCLK <= 110 |  80 < HCLK <= 100 |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |5WS(6CPU cycle) | 150 < HCLK <= 180 | 120 < HCLK <= 144 | 110 < HCLK <= 132 | 100 < HCLK <= 120 |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |6WS(7CPU cycle) | 180 < HCLK <= 210 | 144 < HCLK <= 168 | 132 < HCLK <= 154 | 120 < HCLK <= 140 |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |7WS(8CPU cycle) | 210 < HCLK <= 216 | 168 < HCLK <= 192 | 154 < HCLK <= 176 | 140 < HCLK <= 160 |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |8WS(9CPU cycle) |        --         | 192 < HCLK <= 216 | 176 < HCLK <= 198 | 160 < HCLK <= 180 |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |9WS(10CPU cycle)|        --         |         --        | 198 < HCLK <= 216 |         --        |
+             (++) +------------------------------------------------------------------------------------------------+
+
+  @endinternal
+  * @{
+  */
+
+/**
+  * @brief  This function sets directly SystemCoreClock CMSIS variable.
+  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @retval None
+  */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+  /* HCLK clock frequency */
+  SystemCoreClock = HCLKFrequency;
+}
+
+/**
+  * @brief  Update number of Flash wait states in line with new frequency and current
+            voltage range.
+  * @note   This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
+  * @param  HCLK_Frequency  HCLK frequency
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Latency has been modified
+  *          - ERROR: Latency cannot be modified
+  */
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
+{
+  uint32_t timeout;
+  uint32_t getlatency;
+  uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
+  ErrorStatus status = SUCCESS;
+
+  /* Frequency cannot be equal to 0 */
+  if(HCLK_Frequency == 0U)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+    {
+      if(LL_PWR_IsEnabledOverDriveMode() != 0U)
+        {
+          if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ)
+          {
+            /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */
+            latency = LL_FLASH_LATENCY_7;
+          }
+          else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */
+          {
+            /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */
+            latency = LL_FLASH_LATENCY_6;
+          }
+        }
+      if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0))
+      {
+        /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */
+        latency = LL_FLASH_LATENCY_5;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0))
+      {
+        /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0))
+      {
+        /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0))
+      {
+        /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else
+      {
+        if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0))
+        {
+          /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
+          latency = LL_FLASH_LATENCY_1;
+        }
+        /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */
+      }
+    }
+    else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
+    {
+      if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)
+      {
+        /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cycles) */
+        latency = LL_FLASH_LATENCY_5;
+      }
+      else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)
+      {
+        /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
+      {
+        /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
+      {
+        /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else
+      {
+        if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
+        {
+          /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
+          latency = LL_FLASH_LATENCY_1;
+        }
+        /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
+      }
+    }
+    else /* Scale 3 */
+    {
+      if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ)
+      {
+        /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)
+      {
+        /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)
+      {
+        /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else
+      {
+        if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)
+        {
+          /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
+          latency = LL_FLASH_LATENCY_1;
+        }
+        /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */
+      }
+    }
+
+    if (status != ERROR)
+    {
+      LL_FLASH_SetLatency(latency);
+
+      /* Check that the new number of wait states is taken into account to access the Flash
+           memory by reading the FLASH_ACR register */
+      timeout = 2;
+      do
+      {
+      /* Wait for Flash latency to be updated */
+      getlatency = LL_FLASH_GetLatency();
+      timeout--;
+      } while ((getlatency != latency) && (timeout > 0));
+
+      if(getlatency != latency)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
+  * @note   The application need to ensure that PLL is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
+  *         - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz (PLLVCO_input = HSI frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLP: ensure that max frequency at 216000000 Hz is reach (PLLVCO_output / PLLP)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t pllfreq = 0U;
+
+  /* Check if one of the PLL is enabled */
+  if(UTILS_PLL_IsBusy() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+
+    /* Enable HSI if not enabled */
+    if(LL_RCC_HSI_IsReady() != 1U)
+    {
+      LL_RCC_HSI_Enable();
+      while (LL_RCC_HSI_IsReady() != 1U)
+      {
+        /* Wait for HSI ready */
+      }
+    }
+
+    /* Configure PLL */
+    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+                                UTILS_PLLInitStruct->PLLP);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function configures system clock with HSE as clock source of the PLL
+  * @note   The application need to ensure that PLL is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
+  *         - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLP: ensure that max frequency at 216000000 Hz is reached (PLLVCO_output / PLLP)
+  * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
+  * @param  HSEBypass This parameter can be one of the following values:
+  *         @arg @ref LL_UTILS_HSEBYPASS_ON
+  *         @arg @ref LL_UTILS_HSEBYPASS_OFF
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t pllfreq = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+  /* Check if one of the PLL is enabled */
+  if(UTILS_PLL_IsBusy() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+    /* Enable HSE if not enabled */
+    if(LL_RCC_HSE_IsReady() != 1U)
+    {
+      /* Check if need to enable HSE bypass feature or not */
+      if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
+      {
+        LL_RCC_HSE_EnableBypass();
+      }
+      else
+      {
+        LL_RCC_HSE_DisableBypass();
+      }
+
+      /* Enable HSE */
+      LL_RCC_HSE_Enable();
+      while (LL_RCC_HSE_IsReady() != 1U)
+      {
+        /* Wait for HSE ready */
+      }
+    }
+
+    /* Configure PLL */
+    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+                                UTILS_PLLInitStruct->PLLP);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_LL_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Function to check that PLL can be modified
+  * @param  PLL_InputFrequency  PLL input frequency (in Hz)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @retval PLL output frequency (in Hz)
+  */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+  uint32_t pllfreq = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
+  
+  /* Check different PLL parameters according to RM                          */
+  /*  - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz.   */
+  pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
+  assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
+
+  /*  - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz.*/
+  pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
+  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
+  
+  /*  - PLLP: ensure that max frequency at 216000000 Hz is reached     */
+  pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
+  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+
+  return pllfreq;
+}
+
+/**
+  * @brief  Function to check that PLL can be modified
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: PLL modification can be done
+  *          - ERROR: PLL is busy
+  */
+static ErrorStatus UTILS_PLL_IsBusy(void)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check if PLL is busy*/
+  if(LL_RCC_PLL_IsReady() != 0U)
+  {
+    /* PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  /* Check if PLLSAI is busy*/
+  if(LL_RCC_PLLSAI_IsReady() != 0U)
+  {
+    /* PLLSAI1 configuration cannot be modified */
+    status = ERROR;
+  }
+  /* Check if PLLI2S is busy*/
+  if(LL_RCC_PLLI2S_IsReady() != 0U)
+  {
+    /* PLLI2S configuration cannot be modified */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Function to enable PLL and switch system clock to PLL
+  * @param  SYSCLK_Frequency SYSCLK frequency
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: No problem to switch system to PLL
+  *          - ERROR: Problem to switch system to PLL
+  */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t hclk_frequency = 0U;
+
+  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+
+  /* Calculate HCLK frequency */
+  hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if(SystemCoreClock < hclk_frequency)
+  {
+    /* Set FLASH latency to highest latency */
+    status = LL_SetFlashLatency(hclk_frequency);
+  }
+
+  /* Update system clock configuration */
+  if(status == SUCCESS)
+  {
+    /* Enable PLL */
+    LL_RCC_PLL_Enable();
+    while (LL_RCC_PLL_IsReady() != 1U)
+    {
+      /* Wait for PLL ready */
+    }
+
+    /* Sysclk activation on the main PLL */
+    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+    {
+      /* Wait for system clock switch to PLL */
+    }
+
+    /* Set APB1 & APB2 prescaler*/
+    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+  }
+    
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(SystemCoreClock > hclk_frequency)
+  {
+    /* Set FLASH latency to lowest latency */
+    status = LL_SetFlashLatency(hclk_frequency);
+  }
+
+  /* Update SystemCoreClock variable */
+  if(status == SUCCESS)
+  {
+    LL_SetSystemCoreClock(hclk_frequency);
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/For_stm32.ioc b/For_stm32.ioc
new file mode 100644
index 0000000..7e5e5f0
--- /dev/null
+++ b/For_stm32.ioc
@@ -0,0 +1,539 @@
+#MicroXplorer Configuration settings - do not modify
+ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_9
+ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_8
+ADC1.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_2
+ADC1.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_10
+ADC1.Channel-4\#ChannelRegularConversion=ADC_CHANNEL_11
+ADC1.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV8
+ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master,ClockPrescaler,Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,NbrOfConversion,Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,Rank-3\#ChannelRegularConversion,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,Rank-4\#ChannelRegularConversion,Channel-4\#ChannelRegularConversion,SamplingTime-4\#ChannelRegularConversion
+ADC1.NbrOfConversion=5
+ADC1.NbrOfConversionFlag=1
+ADC1.Rank-0\#ChannelRegularConversion=1
+ADC1.Rank-1\#ChannelRegularConversion=2
+ADC1.Rank-2\#ChannelRegularConversion=3
+ADC1.Rank-3\#ChannelRegularConversion=4
+ADC1.Rank-4\#ChannelRegularConversion=5
+ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_480CYCLES
+ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_480CYCLES
+ADC1.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_480CYCLES
+ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_480CYCLES
+ADC1.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_480CYCLES
+ADC1.master=1
+ADC3.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_15
+ADC3.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV8
+ADC3.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler,NbrOfConversion
+ADC3.NbrOfConversion=1
+ADC3.NbrOfConversionFlag=1
+ADC3.Rank-0\#ChannelRegularConversion=1
+ADC3.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_480CYCLES
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+Dma.Request0=USART1_TX
+Dma.RequestsNb=1
+Dma.USART1_TX.0.Direction=DMA_MEMORY_TO_PERIPH
+Dma.USART1_TX.0.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.USART1_TX.0.Instance=DMA2_Stream7
+Dma.USART1_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.USART1_TX.0.MemInc=DMA_MINC_ENABLE
+Dma.USART1_TX.0.Mode=DMA_NORMAL
+Dma.USART1_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.USART1_TX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.USART1_TX.0.Priority=DMA_PRIORITY_VERY_HIGH
+Dma.USART1_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
+FATFS.BSP.number=1
+FATFS.IPParameters=_MAX_SS
+FATFS._MAX_SS=4096
+FATFS0.BSP.STBoard=false
+FATFS0.BSP.api=Unknown
+FATFS0.BSP.component=
+FATFS0.BSP.condition=
+FATFS0.BSP.instance=PD0
+FATFS0.BSP.ip=GPIO
+FATFS0.BSP.mode=Input
+FATFS0.BSP.name=Detect_SDIO
+FATFS0.BSP.semaphore=
+FATFS0.BSP.solution=PD0
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+Mcu.CPN=STM32F767ZIT6
+Mcu.Family=STM32F7
+Mcu.IP0=ADC1
+Mcu.IP1=ADC3
+Mcu.IP10=SPI5
+Mcu.IP11=SPI6
+Mcu.IP12=SYS
+Mcu.IP13=TIM2
+Mcu.IP14=TIM5
+Mcu.IP15=TIM6
+Mcu.IP16=TIM7
+Mcu.IP17=TIM10
+Mcu.IP18=USART1
+Mcu.IP2=CORTEX_M7
+Mcu.IP3=DMA
+Mcu.IP4=FATFS
+Mcu.IP5=NVIC
+Mcu.IP6=RCC
+Mcu.IP7=SDMMC1
+Mcu.IP8=SPI2
+Mcu.IP9=SPI4
+Mcu.IPNb=19
+Mcu.Name=STM32F767ZITx
+Mcu.Package=LQFP144
+Mcu.Pin0=PF5
+Mcu.Pin1=PF6
+Mcu.Pin10=PC2
+Mcu.Pin11=PC3
+Mcu.Pin12=PA0/WKUP
+Mcu.Pin13=PA1
+Mcu.Pin14=PA2
+Mcu.Pin15=PA3
+Mcu.Pin16=PA4
+Mcu.Pin17=PA5
+Mcu.Pin18=PA6
+Mcu.Pin19=PA7
+Mcu.Pin2=PF7
+Mcu.Pin20=PC4
+Mcu.Pin21=PC5
+Mcu.Pin22=PB0
+Mcu.Pin23=PB1
+Mcu.Pin24=PF11
+Mcu.Pin25=PF12
+Mcu.Pin26=PF13
+Mcu.Pin27=PF14
+Mcu.Pin28=PE10
+Mcu.Pin29=PE11
+Mcu.Pin3=PF8
+Mcu.Pin30=PE12
+Mcu.Pin31=PE13
+Mcu.Pin32=PE14
+Mcu.Pin33=PB10
+Mcu.Pin34=PB11
+Mcu.Pin35=PB12
+Mcu.Pin36=PB13
+Mcu.Pin37=PB14
+Mcu.Pin38=PB15
+Mcu.Pin39=PD8
+Mcu.Pin4=PF9
+Mcu.Pin40=PC8
+Mcu.Pin41=PC9
+Mcu.Pin42=PA8
+Mcu.Pin43=PA9
+Mcu.Pin44=PA10
+Mcu.Pin45=PA13
+Mcu.Pin46=PA14
+Mcu.Pin47=PC10
+Mcu.Pin48=PC11
+Mcu.Pin49=PC12
+Mcu.Pin5=PF10
+Mcu.Pin50=PD0
+Mcu.Pin51=PD1
+Mcu.Pin52=PD2
+Mcu.Pin53=PD7
+Mcu.Pin54=PB3
+Mcu.Pin55=PE1
+Mcu.Pin56=VP_FATFS_VS_SDIO
+Mcu.Pin57=VP_SYS_VS_Systick
+Mcu.Pin58=VP_TIM2_VS_ClockSourceINT
+Mcu.Pin59=VP_TIM5_VS_ClockSourceINT
+Mcu.Pin6=PH0/OSC_IN
+Mcu.Pin60=VP_TIM6_VS_ClockSourceINT
+Mcu.Pin61=VP_TIM7_VS_ClockSourceINT
+Mcu.Pin62=VP_TIM10_VS_ClockSourceINT
+Mcu.Pin7=PH1/OSC_OUT
+Mcu.Pin8=PC0
+Mcu.Pin9=PC1
+Mcu.PinsNb=63
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32F767ZITx
+MxCube.Version=6.10.0
+MxDb.Version=DB.6.0.100
+NVIC.ADC_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DMA2_Stream7_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
+NVIC.TIM1_UP_TIM10_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
+NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
+NVIC.TIM5_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
+NVIC.TIM6_DAC_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
+NVIC.TIM7_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
+NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PA0/WKUP.GPIOParameters=GPIO_Label
+PA0/WKUP.GPIO_Label=TECEN1
+PA0/WKUP.Locked=true
+PA0/WKUP.Signal=GPIO_Output
+PA1.GPIOParameters=GPIO_Label
+PA1.GPIO_Label=TECEN2
+PA1.Locked=true
+PA1.Signal=GPIO_Output
+PA10.Locked=true
+PA10.Mode=Asynchronous
+PA10.Signal=USART1_RX
+PA13.Mode=Trace_Asynchronous_SW
+PA13.Signal=SYS_JTMS-SWDIO
+PA14.Mode=Trace_Asynchronous_SW
+PA14.Signal=SYS_JTCK-SWCLK
+PA2.Locked=true
+PA2.Signal=ADCx_IN2
+PA3.GPIOParameters=GPIO_Label
+PA3.GPIO_Label=REF2_ON
+PA3.Locked=true
+PA3.Signal=GPIO_Output
+PA4.GPIOParameters=PinState,GPIO_Label
+PA4.GPIO_Label=DAC_TEC2_CS
+PA4.Locked=true
+PA4.PinState=GPIO_PIN_SET
+PA4.Signal=GPIO_Output
+PA5.Locked=true
+PA5.Mode=TX_Only_Simplex_Unidirect_Master
+PA5.Signal=SPI6_SCK
+PA6.GPIOParameters=GPIO_Label
+PA6.GPIO_Label=DAC_LD2_CS
+PA6.Locked=true
+PA6.Signal=GPIO_Output
+PA7.Locked=true
+PA7.Mode=TX_Only_Simplex_Unidirect_Master
+PA7.Signal=SPI6_MOSI
+PA8.GPIOParameters=GPIO_Label
+PA8.GPIO_Label=USB_FLAG
+PA8.Locked=true
+PA8.Signal=GPIO_Input
+PA9.Locked=true
+PA9.Mode=Asynchronous
+PA9.Signal=USART1_TX
+PB0.Locked=true
+PB0.Signal=ADCx_IN8
+PB1.Locked=true
+PB1.Signal=ADCx_IN9
+PB10.GPIOParameters=GPIO_Label
+PB10.GPIO_Label=REF0_EN
+PB10.Locked=true
+PB10.Signal=GPIO_Output
+PB11.GPIOParameters=GPIO_Label
+PB11.GPIO_Label=TEC1_PD
+PB11.Locked=true
+PB11.Signal=GPIO_Output
+PB12.GPIOParameters=PinState,GPIO_Label
+PB12.GPIO_Label=DAC_TEC1_CS
+PB12.Locked=true
+PB12.PinState=GPIO_PIN_SET
+PB12.Signal=GPIO_Output
+PB13.Locked=true
+PB13.Mode=TX_Only_Simplex_Unidirect_Master
+PB13.Signal=SPI2_SCK
+PB14.GPIOParameters=GPIO_Label
+PB14.GPIO_Label=DAC_LD1_CS
+PB14.Locked=true
+PB14.Signal=GPIO_Output
+PB15.Locked=true
+PB15.Mode=TX_Only_Simplex_Unidirect_Master
+PB15.Signal=SPI2_MOSI
+PB3.Mode=Trace_Asynchronous_SW
+PB3.Signal=SYS_JTDO-SWO
+PC0.Locked=true
+PC0.Signal=ADCx_IN10
+PC1.Locked=true
+PC1.Signal=ADCx_IN11
+PC10.Mode=SD_4_bits_Wide_bus
+PC10.Signal=SDMMC1_D2
+PC11.Mode=SD_4_bits_Wide_bus
+PC11.Signal=SDMMC1_D3
+PC12.Mode=SD_4_bits_Wide_bus
+PC12.Signal=SDMMC1_CK
+PC2.GPIOParameters=GPIO_Label
+PC2.GPIO_Label=EN_5V2
+PC2.Locked=true
+PC2.Signal=GPIO_Output
+PC3.GPIOParameters=GPIO_Speed,GPIO_Label
+PC3.GPIO_Label=EN_5V1
+PC3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC3.Locked=true
+PC3.Signal=GPIO_Output
+PC4.GPIOParameters=GPIO_Label
+PC4.GPIO_Label=LD2_EN
+PC4.Locked=true
+PC4.Signal=GPIO_Output
+PC5.GPIOParameters=GPIO_Label
+PC5.GPIO_Label=TEC2_PD
+PC5.Locked=true
+PC5.Signal=GPIO_Output
+PC8.Mode=SD_4_bits_Wide_bus
+PC8.Signal=SDMMC1_D0
+PC9.Mode=SD_4_bits_Wide_bus
+PC9.Signal=SDMMC1_D1
+PD0.GPIOParameters=GPIO_Label
+PD0.GPIO_Label=SDMMC1_EN
+PD0.Locked=true
+PD0.Signal=GPIO_Input
+PD1.GPIOParameters=GPIO_Label
+PD1.GPIO_Label=TEST_01
+PD1.Locked=true
+PD1.Signal=GPIO_Output
+PD2.Mode=SD_4_bits_Wide_bus
+PD2.Signal=SDMMC1_CMD
+PD7.Locked=true
+PD7.Signal=GPIO_Output
+PD8.GPIOParameters=GPIO_Label
+PD8.GPIO_Label=LD1_EN
+PD8.Locked=true
+PD8.Signal=GPIO_Output
+PE1.GPIOParameters=GPIO_Label
+PE1.GPIO_Label=FPGA_CONF_DONE
+PE1.Locked=true
+PE1.Signal=GPIO_Input
+PE10.GPIOParameters=GPIO_Label
+PE10.GPIO_Label=ADC_MPD1_CS
+PE10.Locked=true
+PE10.Signal=GPIO_Output
+PE11.GPIOParameters=GPIO_Label
+PE11.GPIO_Label=ADC_ThrLD1_CS
+PE11.Locked=true
+PE11.Signal=GPIO_Output
+PE12.Mode=RX_Only_Simplex_Unidirect_Master
+PE12.Signal=SPI4_SCK
+PE13.Locked=true
+PE13.Mode=RX_Only_Simplex_Unidirect_Master
+PE13.Signal=SPI4_MISO
+PE14.GPIOParameters=GPIO_Speed,PinState,GPIO_Label
+PE14.GPIO_Label=SPI4_CNV
+PE14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PE14.Locked=true
+PE14.PinState=GPIO_PIN_SET
+PE14.Signal=GPIO_Output
+PF10.GPIOParameters=GPIO_Label
+PF10.GPIO_Label=ADC_ThrLD2_CS
+PF10.Locked=true
+PF10.Signal=GPIO_Output
+PF11.GPIOParameters=GPIO_Label
+PF11.GPIO_Label=TEC2_FLAG1
+PF11.Locked=true
+PF11.Signal=GPIO_Input
+PF12.GPIOParameters=GPIO_Label
+PF12.GPIO_Label=TEC2_FLAG2
+PF12.Locked=true
+PF12.Signal=GPIO_Input
+PF13.GPIOParameters=GPIO_Label
+PF13.GPIO_Label=TEC1_FLAG1
+PF13.Locked=true
+PF13.Signal=GPIO_Input
+PF14.GPIOParameters=GPIO_Label
+PF14.GPIO_Label=TEC1_FLAG2
+PF14.Locked=true
+PF14.Signal=GPIO_Input
+PF5.Locked=true
+PF5.Mode=IN15
+PF5.Signal=ADC3_IN15
+PF6.GPIOParameters=GPIO_Label
+PF6.GPIO_Label=ADC_MPD2_CS
+PF6.Locked=true
+PF6.Signal=GPIO_Output
+PF7.Locked=true
+PF7.Mode=RX_Only_Simplex_Unidirect_Master
+PF7.Signal=SPI5_SCK
+PF8.Locked=true
+PF8.Mode=RX_Only_Simplex_Unidirect_Master
+PF8.Signal=SPI5_MISO
+PF9.GPIOParameters=GPIO_Label
+PF9.GPIO_Label=SPI5_CNV
+PF9.Locked=true
+PF9.Signal=GPIO_Output
+PH0/OSC_IN.Mode=HSE-External-Oscillator
+PH0/OSC_IN.Signal=RCC_OSC_IN
+PH1/OSC_OUT.Mode=HSE-External-Oscillator
+PH1/OSC_OUT.Signal=RCC_OSC_OUT
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32F767ZITx
+ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.17.2
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x2000
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=STM32CubeIDE
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=For_stm32.ioc
+ProjectManager.ProjectName=For_stm32
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x4000
+ProjectManager.TargetToolchain=STM32CubeIDE
+ProjectManager.ToolChainLocation=
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-LL-true,4-MX_SPI4_Init-SPI4-false-LL-true,5-MX_FATFS_Init-FATFS-false-HAL-false,6-MX_TIM2_Init-TIM2-false-LL-true,7-MX_TIM5_Init-TIM5-false-LL-true,8-MX_ADC1_Init-ADC1-false-HAL-true,9-MX_ADC3_Init-ADC3-false-HAL-true,10-MX_SPI2_Init-SPI2-false-LL-true,11-MX_SPI5_Init-SPI5-false-LL-true,12-MX_SPI6_Init-SPI6-false-LL-true,13-MX_USART1_UART_Init-USART1-false-LL-true,14-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,15-MX_TIM7_Init-TIM7-false-LL-true,16-MX_TIM6_Init-TIM6-false-LL-true,17-MX_TIM10_Init-TIM10-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+RCC.AHBFreq_Value=184000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV4
+RCC.APB1Freq_Value=46000000
+RCC.APB1TimFreq_Value=92000000
+RCC.APB2CLKDivider=RCC_HCLK_DIV2
+RCC.APB2Freq_Value=92000000
+RCC.APB2TimFreq_Value=184000000
+RCC.CECFreq_Value=32786.88524590164
+RCC.CortexFreq_Value=184000000
+RCC.DFSDMAudioFreq_Value=96000000
+RCC.DFSDMFreq_Value=92000000
+RCC.EthernetFreq_Value=184000000
+RCC.FCLKCortexFreq_Value=184000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=184000000
+RCC.HSE_VALUE=25000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=46000000
+RCC.I2C2Freq_Value=46000000
+RCC.I2C3Freq_Value=46000000
+RCC.I2C4Freq_Value=46000000
+RCC.I2SFreq_Value=26000000
+RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFTFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SN,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLRFreq_Value,PLLSAIP,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC2Freq_Value,SDMMCClockSelection,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value
+RCC.LCDTFTFreq_Value=48000000
+RCC.LPTIM1Freq_Value=46000000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO2PinFreq_Value=184000000
+RCC.PLLCLKFreq_Value=184000000
+RCC.PLLI2SN=52
+RCC.PLLI2SPCLKFreq_Value=26000000
+RCC.PLLI2SQCLKFreq_Value=26000000
+RCC.PLLI2SRCLKFreq_Value=26000000
+RCC.PLLI2SRoutputFreq_Value=26000000
+RCC.PLLM=25
+RCC.PLLN=368
+RCC.PLLQ=8
+RCC.PLLQCLKFreq_Value=46000000
+RCC.PLLQoutputFreq_Value=46000000
+RCC.PLLRFreq_Value=184000000
+RCC.PLLSAIP=RCC_PLLSAIP_DIV8
+RCC.PLLSAIPCLKFreq_Value=24000000
+RCC.PLLSAIQCLKFreq_Value=96000000
+RCC.PLLSAIRCLKFreq_Value=96000000
+RCC.PLLSAIoutputFreq_Value=24000000
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.RNGFreq_Value=46000000
+RCC.SAI1Freq_Value=96000000
+RCC.SAI2Freq_Value=96000000
+RCC.SDMMC2Freq_Value=184000000
+RCC.SDMMCClockSelection=RCC_SDMMC1CLKSOURCE_CLK48
+RCC.SDMMCFreq_Value=46000000
+RCC.SPDIFRXFreq_Value=26000000
+RCC.SYSCLKFreq_VALUE=184000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.UART4Freq_Value=46000000
+RCC.UART5Freq_Value=46000000
+RCC.UART7Freq_Value=46000000
+RCC.UART8Freq_Value=46000000
+RCC.USART1Freq_Value=92000000
+RCC.USART2Freq_Value=46000000
+RCC.USART3Freq_Value=46000000
+RCC.USART6Freq_Value=92000000
+RCC.USBFreq_Value=46000000
+RCC.VCOI2SOutputFreq_Value=52000000
+RCC.VCOInputFreq_Value=1000000
+RCC.VCOOutputFreq_Value=368000000
+RCC.VCOSAIOutputFreq_Value=192000000
+SDMMC1.ClockDiv=20
+SDMMC1.IPParameters=ClockDiv
+SH.ADCx_IN10.0=ADC1_IN10,IN10
+SH.ADCx_IN10.ConfNb=1
+SH.ADCx_IN11.0=ADC1_IN11,IN11
+SH.ADCx_IN11.ConfNb=1
+SH.ADCx_IN2.0=ADC1_IN2,IN2
+SH.ADCx_IN2.ConfNb=1
+SH.ADCx_IN8.0=ADC1_IN8,IN8
+SH.ADCx_IN8.ConfNb=1
+SH.ADCx_IN9.0=ADC1_IN9,IN9
+SH.ADCx_IN9.ConfNb=1
+SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8
+SPI2.CLKPhase=SPI_PHASE_2EDGE
+SPI2.CLKPolarity=SPI_POLARITY_HIGH
+SPI2.CalculateBaudRate=5.75 MBits/s
+SPI2.DataSize=SPI_DATASIZE_16BIT
+SPI2.Direction=SPI_DIRECTION_2LINES
+SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize,CLKPolarity,CLKPhase
+SPI2.Mode=SPI_MODE_MASTER
+SPI2.VirtualType=VM_MASTER
+SPI4.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
+SPI4.CLKPhase=SPI_PHASE_1EDGE
+SPI4.CLKPolarity=SPI_POLARITY_HIGH
+SPI4.CalculateBaudRate=5.75 MBits/s
+SPI4.DataSize=SPI_DATASIZE_16BIT
+SPI4.Direction=SPI_DIRECTION_2LINES_RXONLY
+SPI4.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize,CLKPolarity,CLKPhase,NSSPMode
+SPI4.Mode=SPI_MODE_MASTER
+SPI4.NSSPMode=SPI_NSS_PULSE_DISABLE
+SPI4.VirtualType=VM_MASTER
+SPI5.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
+SPI5.CLKPolarity=SPI_POLARITY_HIGH
+SPI5.CalculateBaudRate=5.75 MBits/s
+SPI5.DataSize=SPI_DATASIZE_16BIT
+SPI5.Direction=SPI_DIRECTION_2LINES_RXONLY
+SPI5.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,NSSPMode,CLKPolarity,DataSize
+SPI5.Mode=SPI_MODE_MASTER
+SPI5.NSSPMode=SPI_NSS_PULSE_DISABLE
+SPI5.VirtualType=VM_MASTER
+SPI6.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
+SPI6.CLKPhase=SPI_PHASE_2EDGE
+SPI6.CLKPolarity=SPI_POLARITY_HIGH
+SPI6.CalculateBaudRate=5.75 MBits/s
+SPI6.DataSize=SPI_DATASIZE_16BIT
+SPI6.Direction=SPI_DIRECTION_2LINES
+SPI6.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,CLKPolarity,DataSize,CLKPhase
+SPI6.Mode=SPI_MODE_MASTER
+SPI6.VirtualType=VM_MASTER
+TIM10.IPParameters=Period,Prescaler
+TIM10.Period=9
+TIM10.Prescaler=183
+TIM2.ClockDivision=TIM_CLOCKDIVISION_DIV1
+TIM2.IPParameters=Period,ClockDivision,Prescaler
+TIM2.Period=840000
+TIM2.Prescaler=1000
+TIM5.ClockDivision=TIM_CLOCKDIVISION_DIV1
+TIM5.IPParameters=ClockDivision,Prescaler,Period
+TIM5.Period=560
+TIM5.Prescaler=10000
+TIM6.IPParameters=Prescaler,Period,TIM_MasterOutputTrigger
+TIM6.Period=19
+TIM6.Prescaler=45999
+TIM6.TIM_MasterOutputTrigger=TIM_TRGO_ENABLE
+TIM7.IPParameters=Prescaler,Period,TIM_MasterOutputTrigger
+TIM7.Period=99
+TIM7.Prescaler=919
+TIM7.TIM_MasterOutputTrigger=TIM_TRGO_ENABLE
+USART1.IPParameters=VirtualMode-Asynchronous
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+VP_FATFS_VS_SDIO.Mode=SDIO
+VP_FATFS_VS_SDIO.Signal=FATFS_VS_SDIO
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_TIM10_VS_ClockSourceINT.Mode=Enable_Timer
+VP_TIM10_VS_ClockSourceINT.Signal=TIM10_VS_ClockSourceINT
+VP_TIM2_VS_ClockSourceINT.Mode=Internal
+VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
+VP_TIM5_VS_ClockSourceINT.Mode=Internal
+VP_TIM5_VS_ClockSourceINT.Signal=TIM5_VS_ClockSourceINT
+VP_TIM6_VS_ClockSourceINT.Mode=Enable_Timer
+VP_TIM6_VS_ClockSourceINT.Signal=TIM6_VS_ClockSourceINT
+VP_TIM7_VS_ClockSourceINT.Mode=Enable_Timer
+VP_TIM7_VS_ClockSourceINT.Signal=TIM7_VS_ClockSourceINT
+board=custom
diff --git a/Inc/File_Handling.h b/Inc/File_Handling.h
new file mode 100644
index 0000000..d157dd9
--- /dev/null
+++ b/Inc/File_Handling.h
@@ -0,0 +1,69 @@
+/*
+ * File_Handling_RTOS.h
+ *
+ *  Created on: 14-May-2020
+ *      Author: Controllerstech
+ */
+
+#ifndef FILE_HANDLING_RTOS_H_
+#define FILE_HANDLING_RTOS_H_
+
+#include "fatfs.h"
+#include 
+#include "stdio.h"
+#include "fatfs.h"
+
+
+/* mounts the sd card*/
+int Mount_SD (const TCHAR* path);
+
+/* unmounts the sd card*/
+int Unmount_SD (const TCHAR* path);
+
+/* Start node to be scanned (***also used as work area***) */
+FRESULT Scan_SD (char* pat);
+
+/* Only supports removing files from home directory. Directory remover to be added soon */
+FRESULT Format_SD (void);
+
+/* write the data to the file
+ * @ name : is the path to the file*/
+FRESULT Write_File (char *name, char *data);
+
+/* write the data to the file
+ * @ name : is the path to the file tooooooooooooooooooooooooooooooooooooooooooooooooo*/
+FRESULT Write_File_byte (char *name, uint8_t *data, unsigned int bytesize);
+
+/* read data from the file
+ * @ name : is the path to the file*/
+FRESULT Read_File (char *name);
+
+FRESULT Seek_Read_File (char *name, uint8_t *data, unsigned int bytesize, unsigned long goto_label);
+
+/* creates the file, if it does not exists
+ * @ name : is the path to the file*/
+FRESULT Create_File (char *name);
+
+/* Removes the file from the sd card
+ * @ name : is the path to the file*/
+FRESULT Remove_File (char *name);
+
+/* creates a directory
+ * @ name: is the path to the directory
+ */
+FRESULT Create_Dir (char *name);
+
+/* checks the free space in the sd card*/
+void Check_SD_Space (void);
+
+/* updates the file. write pointer is set to the end of the file
+ * @ name : is the path to the file
+ */
+FRESULT Update_File (char *name, char *data);
+
+FRESULT Update_File_float (char *name, float *data, unsigned int bytesize);
+
+FRESULT Update_File_byte (char *name, uint8_t *data, unsigned int bytesize);
+
+
+#endif /* FILE_HANDLING_RTOS_H_ */
diff --git a/Inc/bsp_driver_sd.h b/Inc/bsp_driver_sd.h
new file mode 100644
index 0000000..de81b56
--- /dev/null
+++ b/Inc/bsp_driver_sd.h
@@ -0,0 +1,89 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * @file    bsp_driver_sd.h (based on stm32756g_eval_sd.h)
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the bsp_driver_sd.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7_SD_H
+#define __STM32F7_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+#include "fatfs_platform.h"
+
+/* Exported types --------------------------------------------------------*/
+/**
+  * @brief SD Card information structure
+  */
+#define BSP_SD_CardInfo HAL_SD_CardInfoTypeDef
+
+/* Exported constants --------------------------------------------------------*/
+/**
+  * @brief  SD status structure definition
+  */
+#define   MSD_OK                        ((uint8_t)0x00)
+#define   MSD_ERROR                     ((uint8_t)0x01)
+#define   MSD_ERROR_SD_NOT_PRESENT      ((uint8_t)0x02)
+
+/**
+  * @brief  SD transfer state definition
+  */
+#define   SD_TRANSFER_OK                ((uint8_t)0x00)
+#define   SD_TRANSFER_BUSY              ((uint8_t)0x01)
+
+#define SD_PRESENT               ((uint8_t)0x01)
+#define SD_NOT_PRESENT           ((uint8_t)0x00)
+#define SD_DATATIMEOUT           ((uint32_t)100000000)
+
+#ifdef OLD_API
+/* kept to avoid issue when migrating old projects. */
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+#else
+/* USER CODE BEGIN BSP_H_CODE */
+
+/* Exported functions --------------------------------------------------------*/
+uint8_t BSP_SD_Init(void);
+uint8_t BSP_SD_ITConfig(void);
+uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout);
+uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout);
+uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks);
+uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks);
+uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr);
+uint8_t BSP_SD_GetCardState(void);
+void    BSP_SD_GetCardInfo(BSP_SD_CardInfo *CardInfo);
+uint8_t BSP_SD_IsDetected(void);
+
+/* These functions can be modified in case the current settings (e.g. DMA stream)
+   need to be changed for specific application needs */
+void    BSP_SD_AbortCallback(void);
+void    BSP_SD_WriteCpltCallback(void);
+void    BSP_SD_ReadCpltCallback(void);
+/* USER CODE END BSP_H_CODE */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7_SD_H */
diff --git a/Inc/fatfs.h b/Inc/fatfs.h
new file mode 100644
index 0000000..2127b61
--- /dev/null
+++ b/Inc/fatfs.h
@@ -0,0 +1,47 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file   fatfs.h
+  * @brief  Header for fatfs applications
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __fatfs_H
+#define __fatfs_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ff.h"
+#include "ff_gen_drv.h"
+#include "sd_diskio.h" /* defines SD_Driver as external */
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern uint8_t retSD; /* Return value for SD */
+extern char SDPath[4]; /* SD logical drive path */
+extern FATFS SDFatFS; /* File system object for SD logical drive */
+extern FIL SDFile; /* File object for SD */
+
+void MX_FATFS_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+#ifdef __cplusplus
+}
+#endif
+#endif /*__fatfs_H */
diff --git a/Inc/fatfs_platform.h b/Inc/fatfs_platform.h
new file mode 100644
index 0000000..2c362f0
--- /dev/null
+++ b/Inc/fatfs_platform.h
@@ -0,0 +1,27 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : fatfs_platform.h
+  * @brief          : fatfs_platform header file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+*/
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+/* Defines ------------------------------------------------------------------*/
+#define SD_PRESENT               ((uint8_t)0x01)  /* also in bsp_driver_sd.h */
+#define SD_NOT_PRESENT           ((uint8_t)0x00)  /* also in bsp_driver_sd.h */
+#define SD_DETECT_PIN         GPIO_PIN_0
+#define SD_DETECT_GPIO_PORT   GPIOD
+/* Prototypes ---------------------------------------------------------------*/
+uint8_t	BSP_PlatformIsDetected(void);
diff --git a/Inc/ffconf.h b/Inc/ffconf.h
new file mode 100644
index 0000000..98a96ff
--- /dev/null
+++ b/Inc/ffconf.h
@@ -0,0 +1,269 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  *  FatFs - Generic FAT file system module  R0.12c (C)ChaN, 2017
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+#ifndef _FFCONF
+#define _FFCONF 68300	/* Revision ID */
+
+/*-----------------------------------------------------------------------------/
+/ Additional user header to be used
+/-----------------------------------------------------------------------------*/
+
+#include "main.h"
+#include "stm32f7xx_hal.h"
+#include "bsp_driver_sd.h"
+
+/*-----------------------------------------------------------------------------/
+/ Function Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _FS_READONLY         0      /* 0:Read/Write or 1:Read only */
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/  Read-only configuration removes writing API functions, f_write(), f_sync(),
+/  f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/  and optional writing functions as well. */
+
+#define _FS_MINIMIZE         0      /* 0 to 3 */
+/* This option defines minimization level to remove some basic API functions.
+/
+/   0: All basic functions are enabled.
+/   1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
+/      are removed.
+/   2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/   3: f_lseek() function is removed in addition to 2. */
+
+#define _USE_STRFUNC         2      /* 0:Disable or 1-2:Enable */
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and
+/  f_printf().
+/
+/  0: Disable string functions.
+/  1: Enable without LF-CRLF conversion.
+/  2: Enable with LF-CRLF conversion. */
+
+#define _USE_FIND            0
+/* This option switches filtered directory read functions, f_findfirst() and
+/  f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
+
+#define _USE_MKFS            1
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+#define _USE_FASTSEEK        1
+/* This option switches fast seek feature. (0:Disable or 1:Enable) */
+
+#define	_USE_EXPAND		0
+/* This option switches f_expand function. (0:Disable or 1:Enable) */
+
+#define _USE_CHMOD		0
+/* This option switches attribute manipulation functions, f_chmod() and f_utime().
+/  (0:Disable or 1:Enable) Also _FS_READONLY needs to be 0 to enable this option. */
+
+#define _USE_LABEL           0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/  (0:Disable or 1:Enable) */
+
+#define _USE_FORWARD         0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+
+/*-----------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _CODE_PAGE         850
+/* This option specifies the OEM code page to be used on the target system.
+/  Incorrect setting of the code page can cause a file open failure.
+/
+/   1   - ASCII (No extended character. Non-LFN cfg. only)
+/   437 - U.S.
+/   720 - Arabic
+/   737 - Greek
+/   771 - KBL
+/   775 - Baltic
+/   850 - Latin 1
+/   852 - Latin 2
+/   855 - Cyrillic
+/   857 - Turkish
+/   860 - Portuguese
+/   861 - Icelandic
+/   862 - Hebrew
+/   863 - Canadian French
+/   864 - Arabic
+/   865 - Nordic
+/   866 - Russian
+/   869 - Greek 2
+/   932 - Japanese (DBCS)
+/   936 - Simplified Chinese (DBCS)
+/   949 - Korean (DBCS)
+/   950 - Traditional Chinese (DBCS)
+*/
+
+#define _USE_LFN     0    /* 0 to 3 */
+#define _MAX_LFN     255  /* Maximum LFN length to handle (12 to 255) */
+/* The _USE_LFN switches the support of long file name (LFN).
+/
+/   0: Disable support of LFN. _MAX_LFN has no effect.
+/   1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/   2: Enable LFN with dynamic working buffer on the STACK.
+/   3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/  To enable the LFN, Unicode handling functions (option/unicode.c) must be added
+/  to the project. The working buffer occupies (_MAX_LFN + 1) * 2 bytes and
+/  additional 608 bytes at exFAT enabled. _MAX_LFN can be in range from 12 to 255.
+/  It should be set 255 to support full featured LFN operations.
+/  When use stack for the working buffer, take care on stack overflow. When use heap
+/  memory for the working buffer, memory management functions, ff_memalloc() and
+/  ff_memfree(), must be added to the project. */
+
+#define _LFN_UNICODE    0 /* 0:ANSI/OEM or 1:Unicode */
+/* This option switches character encoding on the API. (0:ANSI/OEM or 1:UTF-16)
+/  To use Unicode string for the path name, enable LFN and set _LFN_UNICODE = 1.
+/  This option also affects behavior of string I/O functions. */
+
+#define _STRF_ENCODE    3
+/* When _LFN_UNICODE == 1, this option selects the character encoding ON THE FILE to
+/  be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
+/
+/  0: ANSI/OEM
+/  1: UTF-16LE
+/  2: UTF-16BE
+/  3: UTF-8
+/
+/  This option has no effect when _LFN_UNICODE == 0. */
+
+#define _FS_RPATH       0 /* 0 to 2 */
+/* This option configures support of relative path.
+/
+/   0: Disable relative path and remove related functions.
+/   1: Enable relative path. f_chdir() and f_chdrive() are available.
+/   2: f_getcwd() function is available in addition to 1.
+*/
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/----------------------------------------------------------------------------*/
+
+#define _VOLUMES    1
+/* Number of volumes (logical drives) to be used. */
+
+/* USER CODE BEGIN Volumes */
+#define _STR_VOLUME_ID          0	/* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */
+#define _VOLUME_STRS            "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
+/* _STR_VOLUME_ID switches string support of volume ID.
+/  When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
+/  number in the path name. _VOLUME_STRS defines the drive ID strings for each
+/  logical drives. Number of items must be equal to _VOLUMES. Valid characters for
+/  the drive ID strings are: A-Z and 0-9. */
+/* USER CODE END Volumes */
+
+#define _MULTI_PARTITION     0 /* 0:Single partition, 1:Multiple partition */
+/* This option switches support of multi-partition on a physical drive.
+/  By default (0), each logical drive number is bound to the same physical drive
+/  number and only an FAT volume found on the physical drive will be mounted.
+/  When multi-partition is enabled (1), each logical drive number can be bound to
+/  arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
+/  function will be available. */
+#define _MIN_SS    512  /* 512, 1024, 2048 or 4096 */
+#define _MAX_SS    4096  /* 512, 1024, 2048 or 4096 */
+/* These options configure the range of sector size to be supported. (512, 1024,
+/  2048 or 4096) Always set both 512 for most systems, all type of memory cards and
+/  harddisk. But a larger value may be required for on-board flash memory and some
+/  type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
+/  to variable sector size and GET_SECTOR_SIZE command must be implemented to the
+/  disk_ioctl() function. */
+
+#define	_USE_TRIM      0
+/* This option switches support of ATA-TRIM. (0:Disable or 1:Enable)
+/  To enable Trim function, also CTRL_TRIM command should be implemented to the
+/  disk_ioctl() function. */
+
+#define _FS_NOFSINFO    0 /* 0,1,2 or 3 */
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/  option, and f_getfree() function at first time after volume mount will force
+/  a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/  bit0=0: Use free cluster count in the FSINFO if available.
+/  bit0=1: Do not trust free cluster count in the FSINFO.
+/  bit1=0: Use last allocated cluster number in the FSINFO if available.
+/  bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/----------------------------------------------------------------------------*/
+
+#define _FS_TINY    0      /* 0:Normal or 1:Tiny */
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/  At the tiny configuration, size of file object (FIL) is reduced _MAX_SS bytes.
+/  Instead of private sector buffer eliminated from the file object, common sector
+/  buffer in the file system object (FATFS) is used for the file data transfer. */
+
+#define _FS_EXFAT	0
+/* This option switches support of exFAT file system. (0:Disable or 1:Enable)
+/  When enable exFAT, also LFN needs to be enabled. (_USE_LFN >= 1)
+/  Note that enabling exFAT discards C89 compatibility. */
+
+#define _FS_NORTC	0
+#define _NORTC_MON	6
+#define _NORTC_MDAY	4
+#define _NORTC_YEAR	2015
+/* The option _FS_NORTC switches timestamp functiton. If the system does not have
+/  any RTC function or valid timestamp is not needed, set _FS_NORTC = 1 to disable
+/  the timestamp function. All objects modified by FatFs will have a fixed timestamp
+/  defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time.
+/  To enable timestamp function (_FS_NORTC = 0), get_fattime() function need to be
+/  added to the project to get current time form real-time clock. _NORTC_MON,
+/  _NORTC_MDAY and _NORTC_YEAR have no effect.
+/  These options have no effect at read-only configuration (_FS_READONLY = 1). */
+
+#define _FS_LOCK    2     /* 0:Disable or >=1:Enable */
+/* The option _FS_LOCK switches file lock function to control duplicated file open
+/  and illegal operation to open objects. This option must be 0 when _FS_READONLY
+/  is 1.
+/
+/  0:  Disable file lock function. To avoid volume corruption, application program
+/      should avoid illegal open, remove and rename to the open objects.
+/  >0: Enable file lock function. The value defines how many files/sub-directories
+/      can be opened simultaneously under file lock control. Note that the file
+/      lock control is independent of re-entrancy. */
+
+#define _FS_REENTRANT    0  /* 0:Disable or 1:Enable */
+#define _FS_TIMEOUT      1000 /* Timeout period in unit of time ticks */
+#define _SYNC_t          NULL
+/* The option _FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
+/  module itself. Note that regardless of this option, file access to different
+/  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/  and f_fdisk() function, are always not re-entrant. Only file/directory access
+/  to the same volume is under control of this function.
+/
+/   0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
+/   1: Enable re-entrancy. Also user provided synchronization handlers,
+/      ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/      function, must be added to the project. Samples are available in
+/      option/syscall.c.
+/
+/  The _FS_TIMEOUT defines timeout period in unit of time tick.
+/  The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/  SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be
+/  included somewhere in the scope of ff.h. */
+
+/* define the ff_malloc ff_free macros as standard malloc free */
+#if !defined(ff_malloc) && !defined(ff_free)
+#include 
+#define ff_malloc  malloc
+#define ff_free  free
+#endif
+
+#endif /* _FFCONF */
diff --git a/Inc/main.h b/Inc/main.h
new file mode 100644
index 0000000..e41d604
--- /dev/null
+++ b/Inc/main.h
@@ -0,0 +1,236 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+#include "stm32f7xx_ll_dma.h"
+#include "stm32f7xx_ll_spi.h"
+#include "stm32f7xx_ll_tim.h"
+#include "stm32f7xx_ll_usart.h"
+#include "stm32f7xx_ll_rcc.h"
+#include "stm32f7xx_ll_bus.h"
+#include "stm32f7xx_ll_cortex.h"
+#include "stm32f7xx_ll_system.h"
+#include "stm32f7xx_ll_utils.h"
+#include "stm32f7xx_ll_pwr.h"
+#include "stm32f7xx_ll_gpio.h"
+
+#include "stm32f7xx_ll_exti.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define ADC_MPD2_CS_Pin GPIO_PIN_6
+#define ADC_MPD2_CS_GPIO_Port GPIOF
+#define SPI5_CNV_Pin GPIO_PIN_9
+#define SPI5_CNV_GPIO_Port GPIOF
+#define ADC_ThrLD2_CS_Pin GPIO_PIN_10
+#define ADC_ThrLD2_CS_GPIO_Port GPIOF
+#define EN_5V2_Pin GPIO_PIN_2
+#define EN_5V2_GPIO_Port GPIOC
+#define EN_5V1_Pin GPIO_PIN_3
+#define EN_5V1_GPIO_Port GPIOC
+#define TECEN1_Pin GPIO_PIN_0
+#define TECEN1_GPIO_Port GPIOA
+#define TECEN2_Pin GPIO_PIN_1
+#define TECEN2_GPIO_Port GPIOA
+#define REF2_ON_Pin GPIO_PIN_3
+#define REF2_ON_GPIO_Port GPIOA
+#define DAC_TEC2_CS_Pin GPIO_PIN_4
+#define DAC_TEC2_CS_GPIO_Port GPIOA
+#define DAC_LD2_CS_Pin GPIO_PIN_6
+#define DAC_LD2_CS_GPIO_Port GPIOA
+#define LD2_EN_Pin GPIO_PIN_4
+#define LD2_EN_GPIO_Port GPIOC
+#define TEC2_PD_Pin GPIO_PIN_5
+#define TEC2_PD_GPIO_Port GPIOC
+#define TEC2_FLAG1_Pin GPIO_PIN_11
+#define TEC2_FLAG1_GPIO_Port GPIOF
+#define TEC2_FLAG2_Pin GPIO_PIN_12
+#define TEC2_FLAG2_GPIO_Port GPIOF
+#define TEC1_FLAG1_Pin GPIO_PIN_13
+#define TEC1_FLAG1_GPIO_Port GPIOF
+#define TEC1_FLAG2_Pin GPIO_PIN_14
+#define TEC1_FLAG2_GPIO_Port GPIOF
+#define ADC_MPD1_CS_Pin GPIO_PIN_10
+#define ADC_MPD1_CS_GPIO_Port GPIOE
+#define ADC_ThrLD1_CS_Pin GPIO_PIN_11
+#define ADC_ThrLD1_CS_GPIO_Port GPIOE
+#define SPI4_CNV_Pin GPIO_PIN_14
+#define SPI4_CNV_GPIO_Port GPIOE
+#define REF0_EN_Pin GPIO_PIN_10
+#define REF0_EN_GPIO_Port GPIOB
+#define TEC1_PD_Pin GPIO_PIN_11
+#define TEC1_PD_GPIO_Port GPIOB
+#define DAC_TEC1_CS_Pin GPIO_PIN_12
+#define DAC_TEC1_CS_GPIO_Port GPIOB
+#define DAC_LD1_CS_Pin GPIO_PIN_14
+#define DAC_LD1_CS_GPIO_Port GPIOB
+#define LD1_EN_Pin GPIO_PIN_8
+#define LD1_EN_GPIO_Port GPIOD
+#define USB_FLAG_Pin GPIO_PIN_8
+#define USB_FLAG_GPIO_Port GPIOA
+#define SDMMC1_EN_Pin GPIO_PIN_0
+#define SDMMC1_EN_GPIO_Port GPIOD
+#define TEST_01_Pin GPIO_PIN_1
+#define TEST_01_GPIO_Port GPIOD
+#define FPGA_CONF_DONE_Pin GPIO_PIN_1
+#define FPGA_CONF_DONE_GPIO_Port GPIOE
+
+/* USER CODE BEGIN Private defines */
+	#define CL_16 15
+	#define DL_16 15
+	#define CL_8  30
+	#define DL_8  30
+	#define TSK_8 32
+	#define TSK_16 16
+
+	
+//	#define SD_Length 100
+	
+	#define HALT 0
+	#define DECODE_ENABLE 1
+	#define DEFAULT_ENABLE 2
+	#define TRANS_S_ENABLE 3
+	#define TRANS_ENABLE 4
+	#define REMOVE_FILE 5
+	#define STATE 6
+	#define WORK_ENABLE 7
+  #define DECODE_TASK 8
+  #define RUN_TASK 9
+	
+	#define SD_ERR 0x01	
+	#define UART_ERR 0x02
+	#define UART_DECODE_ERR 0x04
+	#define TEC1_ERR 0x08
+	#define TEC2_ERR 0x10
+	#define DEFAUL_ERR 0x20
+	#define REMOVE_ERR 0x40
+	
+	#define NO_MESS 0
+	#define MESS_01 1
+	#define MESS_02 2
+	#define MESS_03 3
+	
+	typedef struct{
+	
+		uint8_t WORK_EN;
+		uint8_t U5V1_EN;
+		uint8_t U5V2_EN;
+		uint8_t LD1_EN;
+		uint8_t LD2_EN;
+		uint8_t REF1_EN;
+		uint8_t REF2_EN;
+		uint8_t TEC1_EN;
+		uint8_t TEC2_EN;
+		uint8_t TS1_EN;
+		uint8_t TS2_EN;
+		uint8_t SD_EN;
+		uint8_t PI1_RD;
+		uint8_t PI2_RD;
+		
+		uint16_t AVERAGES;
+		uint16_t MES_ID;
+		
+	}Work_SetupTypeDef;
+	
+	typedef struct{
+		
+		uint16_t LD_TEMP;
+    float P_coef_temp;
+    float I_coef_temp;
+		uint16_t CURRENT;
+		
+	}LDx_SetupTypeDef;
+	
+	typedef struct{
+		
+		uint16_t LD_CURR_TEMP;
+		float e_integral;
+		uint16_t POWER;
+		
+	}LDx_ParamTypeDef;
+	
+	typedef enum _task_type_t
+  {
+    TT_CHANGE_CURR_1 = 0x1,
+    TT_CHANGE_CURR_2 = 0x2,
+    TT_CHANGE_TEMP_1 = 0x3,
+    TT_CHANGE_TEMP_2 = 0x4,
+  } task_type_t;
+  
+  typedef struct _task_t
+  {
+    task_type_t task_type;
+    float    min_param;
+    float    max_param;
+    float    delta_param; // change step between min_param and max_param
+    float    current_param; // current_param is iterating by summary with delta_param every interrupt
+    uint8_t  dt;          // microseconds
+    uint16_t tau;         // milliseconds or microseconds?
+    float    sec_param;
+    float    curr;
+    float    temp;
+    float    i_coef_1;
+    float    p_coef_1;
+    float    i_coef_2;
+    float    p_coef_2;
+  } task_t;
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
diff --git a/Inc/sd_diskio.h b/Inc/sd_diskio.h
new file mode 100644
index 0000000..47b48e0
--- /dev/null
+++ b/Inc/sd_diskio.h
@@ -0,0 +1,41 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    sd_diskio.h
+  * @brief   Header for sd_diskio.c module
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Note: code generation based on sd_diskio_template.h */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SD_DISKIO_H
+#define __SD_DISKIO_H
+
+/* USER CODE BEGIN firstSection */
+/* can be used to modify / undefine following code or add new definitions */
+/* USER CODE END firstSection */
+
+/* Includes ------------------------------------------------------------------*/
+#include "bsp_driver_sd.h"
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+extern const Diskio_drvTypeDef  SD_Driver;
+
+/* USER CODE BEGIN lastSection */
+/* can be used to modify / undefine previous code or add new definitions */
+/* USER CODE END lastSection */
+
+#endif /* __SD_DISKIO_H */
diff --git a/Inc/stm32_assert.h b/Inc/stm32_assert.h
new file mode 100644
index 0000000..c096d4b
--- /dev/null
+++ b/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @brief   STM32 assert file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
diff --git a/Inc/stm32f7xx_hal_conf.h b/Inc/stm32f7xx_hal_conf.h
new file mode 100644
index 0000000..b574ca8
--- /dev/null
+++ b/Inc/stm32f7xx_hal_conf.h
@@ -0,0 +1,484 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32f7xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_CONF_H
+#define __STM32F7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+
+  /* #define HAL_CRYP_MODULE_ENABLED */
+#define HAL_ADC_MODULE_ENABLED
+/* #define HAL_CAN_MODULE_ENABLED */
+/* #define HAL_CEC_MODULE_ENABLED */
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_DAC_MODULE_ENABLED */
+/* #define HAL_DCMI_MODULE_ENABLED */
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_RNG_MODULE_ENABLED */
+/* #define HAL_RTC_MODULE_ENABLED */
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+/* #define HAL_MMC_MODULE_ENABLED */
+/* #define HAL_SPDIFRX_MODULE_ENABLED */
+/* #define HAL_SPI_MODULE_ENABLED */
+#define HAL_TIM_MODULE_ENABLED
+/* #define HAL_UART_MODULE_ENABLED */
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+/* #define HAL_PCD_MODULE_ENABLED */
+/* #define HAL_HCD_MODULE_ENABLED */
+/* #define HAL_DFSDM_MODULE_ENABLED */
+/* #define HAL_DSI_MODULE_ENABLED */
+/* #define HAL_JPEG_MODULE_ENABLED */
+/* #define HAL_MDIOS_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_EXTI_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0U) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              0U
+#define  ART_ACCELERATOR_ENABLE        0U /* To enable instruction cache and prefetch */
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                 /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4U)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4U)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848_PHY_ADDRESS Address*/
+#define DP83848_PHY_ADDRESS
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FFU)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFFU)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFFU)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFFU)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+#define PHY_SR                          ((uint16_t))    /*!< PHY status register Offset                      */
+
+#define PHY_SPEED_STATUS                ((uint16_t))  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t))  /*!< PHY Duplex mask                                 */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f7xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32f7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
+  #include "stm32f7xx_hal_eth_legacy.h"
+#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32f7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32f7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_CONF_H */
+
diff --git a/Inc/stm32f7xx_it.h b/Inc/stm32f7xx_it.h
new file mode 100644
index 0000000..f6f782e
--- /dev/null
+++ b/Inc/stm32f7xx_it.h
@@ -0,0 +1,74 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_IT_H
+#define __STM32F7xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void ADC_IRQHandler(void);
+void TIM1_UP_TIM10_IRQHandler(void);
+void TIM2_IRQHandler(void);
+void USART1_IRQHandler(void);
+void TIM5_IRQHandler(void);
+void TIM6_DAC_IRQHandler(void);
+void TIM7_IRQHandler(void);
+void DMA2_Stream7_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_IT_H */
diff --git a/MDK-ARM/DebugConfig/For_stm32_STM32F767ZITx_2.0.0.dbgconf b/MDK-ARM/DebugConfig/For_stm32_STM32F767ZITx_2.0.0.dbgconf
new file mode 100644
index 0000000..5cba73a
--- /dev/null
+++ b/MDK-ARM/DebugConfig/For_stm32_STM32F767ZITx_2.0.0.dbgconf
@@ -0,0 +1,77 @@
+// File: STM32F76x_77x.dbgconf
+// Version: 1.0.0
+// Note: refer to STM32F76xxx STM32F77xxx reference manual (RM0410)
+//       refer to STM32F76xxx STM32F77xxx datasheets
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+//  Debug MCU configuration register (DBGMCU_CR)
+//     DBG_STANDBY               Debug standby mode
+//     DBG_STOP                  Debug stop mode
+//     DBG_SLEEP                 Debug sleep mode
+// 
+DbgMCU_CR = 0x00000007;
+
+//  Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
+//                                    Reserved bits must be kept at reset value
+//    DBG_CAN2_STOP             Debug CAN2 stopped when core is halted
+//    DBG_CAN1_STOP             Debug CAN1 stopped when core is halted
+//    DBG_I2C4_SMBUS_TIMEOUT    SMBUS timeout mode stopped when core is halted
+//    DBG_I2C3_SMBUS_TIMEOUT    SMBUS timeout mode stopped when core is halted
+//    DBG_I2C2_SMBUS_TIMEOUT    SMBUS timeout mode stopped when core is halted
+//    DBG_I2C1_SMBUS_TIMEOUT    SMBUS timeout mode stopped when core is halted
+//    DBG_CAN3_STOP             Debug CAN3 stopped when core is halted
+//    DBG_IWDG_STOP             Debug independent watchdog stopped when core is halted
+//    DBG_WWDG_STOP             Debug window watchdog stopped when core is halted
+//    DBG_RTC_STOP              RTC stopped when core is halted
+//     DBG_LPTIM1_STOP           LPTMI1 counter stopped when core is halted
+//     DBG_TIM14_STOP            TIM14 counter stopped when core is halted
+//     DBG_TIM13_STOP            TIM13 counter stopped when core is halted
+//     DBG_TIM12_STOP            TIM12 counter stopped when core is halted
+//     DBG_TIM7_STOP             TIM7 counter stopped when core is halted
+//     DBG_TIM6_STOP             TIM6 counter stopped when core is halted
+//     DBG_TIM5_STOP             TIM5 counter stopped when core is halted
+//     DBG_TIM4_STOP             TIM4 counter stopped when core is halted
+//     DBG_TIM3_STOP             TIM3 counter stopped when core is halted
+//     DBG_TIM2_STOP             TIM2 counter stopped when core is halted
+// 
+DbgMCU_APB1_Fz = 0x00000000;
+
+//  Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
+//                                    Reserved bits must be kept at reset value
+//    DBG_TIM11_STOP            TIM11 counter stopped when core is halted
+//    DBG_TIM10_STOP            TIM10 counter stopped when core is halted
+//    DBG_TIM9_STOP             TIM9 counter stopped when core is halted
+//     DBG_TIM8_STOP             TIM8 counter stopped when core is halted
+//     DBG_TIM1_STOP             TIM1 counter stopped when core is halted
+// 
+DbgMCU_APB2_Fz = 0x00000000;
+
+//  TPIU Pin Routing (TRACECLK fixed on Pin PE2)
+//    TRACECLK: Pin PE2
+//    TRACED0
+//      ETM Trace Data 0
+//       <0x00040003=> Pin PE3
+//       <0x00020001=> Pin PC1
+//       <0x0006000D=> Pin PG13
+//    TRACED1
+//      ETM Trace Data 1
+//       <0x00040004=> Pin PE4
+//       <0x00020008=> Pin PC8
+//       <0x0006000E=> Pin PG14
+//    TRACED2
+//      ETM Trace Data 2
+//       <0x00040005=> Pin PE5
+//       <0x00030002=> Pin PD2
+//    TRACED3
+//      ETM Trace Data 3
+//       <0x00040006=> Pin PE6
+//       <0x0002000C=> Pin PC12
+// 
+TraceClk_Pin = 0x00040002;
+TraceD0_Pin  = 0x00040003;
+TraceD1_Pin  = 0x00040004;
+TraceD2_Pin  = 0x00040005;
+TraceD3_Pin  = 0x00040006;
+
+// <<< end of configuration section >>>
diff --git a/MDK-ARM/EventRecorderStub.scvd b/MDK-ARM/EventRecorderStub.scvd
new file mode 100644
index 0000000..2956b29
--- /dev/null
+++ b/MDK-ARM/EventRecorderStub.scvd
@@ -0,0 +1,9 @@
+
+
+
+
+       
+  
+  
+
+
diff --git a/MDK-ARM/For_stm32.uvguix.User b/MDK-ARM/For_stm32.uvguix.User
new file mode 100644
index 0000000..1ab92db
--- /dev/null
+++ b/MDK-ARM/For_stm32.uvguix.User
@@ -0,0 +1,3698 @@
+
+
+
+  -6.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    D:\users\Viktor\PhD\MIPT\Stephan\SOFT\Low_grade\For_stm32\Inc
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diff --git a/MDK-ARM/For_stm32.uvguix.Viktor b/MDK-ARM/For_stm32.uvguix.Viktor
new file mode 100644
index 0000000..f74460e
--- /dev/null
+++ b/MDK-ARM/For_stm32.uvguix.Viktor
@@ -0,0 +1,3700 @@
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### uVision Project, (C) Keil Software

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diff --git a/MDK-ARM/For_stm32.uvguix.é¿¬Γ«α b/MDK-ARM/For_stm32.uvguix.é¿¬Γ«α
new file mode 100644
index 0000000..f593023
--- /dev/null
+++ b/MDK-ARM/For_stm32.uvguix.é¿¬Γ«α
@@ -0,0 +1,3583 @@
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+
+
+  -6.1
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diff --git a/MDK-ARM/For_stm32.uvoptx b/MDK-ARM/For_stm32.uvoptx
new file mode 100644
index 0000000..52f7d65
--- /dev/null
+++ b/MDK-ARM/For_stm32.uvoptx
@@ -0,0 +1,822 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc; *.md
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    For_stm32
+    0x4
+    ARM-ADS
+    
+      25000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        
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+        1
+        1
+        1
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+        1
+        1
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+        1
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+        0
+      
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+        1
+        1
+        1
+        1
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+        0
+      
+      
+        1
+        0
+        1
+      
+      18
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        6
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        STLink\ST-LINKIII-KEIL_SWO.dll
+      
+      
+        
+          0
+          ARMRTXEVENTFLAGS
+          -L70 -Z18 -C0 -M0 -T1
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          DLGUARM
+          (105=-1,-1,-1,-1,0)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20020000 -FC1000 -FN2 -FF0STM32F7x_2048 -FS08000000 -FL0200000 -FF1STM32F7xTCM_2048 -FS1200000 -FL1200000 -FP0($$Device:STM32F767ZITx$CMSIS\Flash\STM32F7x_2048.FLM) -FP1($$Device:STM32F767ZITx$CMSIS\Flash\STM32F7xTCM_2048.FLM))
+        
+        
+          0
+          ST-LINKIII-KEIL_SWO
+          -U33FF6A064246313349321057 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(5BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0STM32F7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32F767ZITx$CMSIS\Flash\STM32F7x_2048.FLM) -FF1STM32F7xTCM_2048.FLM -FS1200000 -FL1200000 -FP1($$Device:STM32F767ZITx$CMSIS\Flash\STM32F7xTCM_2048.FLM)
+        
+      
+      
+        
+          0
+          0
+          1437
+          1
+          
134221116

+          0
+          0
+          0
+          0
+          0
+          1
+          ../Src/main.c
+          
+          \\For_stm32\../Src/main.c\1437
+        
+        
+          1
+          0
+          1446
+          1
+          
0

+          0
+          0
+          0
+          0
+          0
+          0
+          ../Src/main.c
+          
+          
+        
+      
+      
+        
+          0
+          1
+          COMMAND
+        
+        
+          1
+          1
+          LD1_curr_setup
+        
+        
+          2
+          1
+          LD1_param
+        
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diff --git a/MDK-ARM/For_stm32.uvprojx b/MDK-ARM/For_stm32.uvprojx
new file mode 100644
index 0000000..cc09963
--- /dev/null
+++ b/MDK-ARM/For_stm32.uvprojx
@@ -0,0 +1,1159 @@
+
+
+
+  2.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      For_stm32
+      0x4
+      ARM-ADS
+      5060960::V5.06 update 7 (build 960)::ARMCC
+      1
+      
+        
+          STM32F767ZITx
+          STMicroelectronics
+          Keil.STM32F7xx_DFP.2.16.0
+          https://www.keil.com/pack/
+          IRAM(0x20000000-0x2007FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE TZ
+          
+          
+          
+          0
+          
+          
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+          $$Device:STM32F767ZITx$CMSIS\SVD\STM32F767.svd
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+          
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+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
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+          -MPU
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+          -pCM7
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+          
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+          BIN\UL2V8M.DLL
+          "" ()
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+            
+            
+              stm32f7xx_hal_pwr_ex.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c
+            
+            
+              stm32f7xx_hal_cortex.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c
+            
+            
+              stm32f7xx_hal.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c
+            
+            
+              stm32f7xx_hal_i2c.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c
+            
+            
+              stm32f7xx_hal_i2c_ex.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c
+            
+            
+              stm32f7xx_hal_exti.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c
+            
+            
+              stm32f7xx_ll_rcc.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c
+              
+                
+                  2
+                  0
+                  0
+                  0
+                  0
+                  1
+                  2
+                  2
+                  2
+                  2
+                  11
+                  
+                  
+                  1
+                
+                
+                  
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    
+                      
+                      
+                      
+                      
+                    
+                  
+                
+              
+            
+            
+              stm32f7xx_ll_utils.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c
+              
+                
+                  2
+                  0
+                  0
+                  0
+                  0
+                  1
+                  2
+                  2
+                  2
+                  2
+                  11
+                  
+                  
+                  1
+                
+                
+                  
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    
+                      
+                      
+                      
+                      
+                    
+                  
+                
+              
+            
+            
+              stm32f7xx_ll_exti.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c
+              
+                
+                  2
+                  0
+                  0
+                  0
+                  0
+                  1
+                  2
+                  2
+                  2
+                  2
+                  11
+                  
+                  
+                  1
+                
+                
+                  
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    
+                      
+                      
+                      
+                      
+                    
+                  
+                
+              
+            
+            
+              stm32f7xx_ll_gpio.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c
+              
+                
+                  2
+                  0
+                  0
+                  0
+                  0
+                  1
+                  2
+                  2
+                  2
+                  2
+                  11
+                  
+                  
+                  1
+                
+                
+                  
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    
+                      
+                      
+                      
+                      
+                    
+                  
+                
+              
+            
+            
+              stm32f7xx_ll_dma.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c
+              
+                
+                  2
+                  0
+                  0
+                  0
+                  0
+                  1
+                  2
+                  2
+                  2
+                  2
+                  11
+                  
+                  
+                  1
+                
+                
+                  
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    
+                      
+                      
+                      
+                      
+                    
+                  
+                
+              
+            
+            
+              stm32f7xx_ll_sdmmc.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c
+            
+            
+              stm32f7xx_hal_sd.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c
+            
+            
+              stm32f7xx_ll_spi.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c
+              
+                
+                  2
+                  0
+                  0
+                  0
+                  0
+                  1
+                  2
+                  2
+                  2
+                  2
+                  11
+                  
+                  
+                  1
+                
+                
+                  
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    
+                      
+                      
+                      
+                      
+                    
+                  
+                
+              
+            
+            
+              stm32f7xx_hal_tim.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c
+            
+            
+              stm32f7xx_hal_tim_ex.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c
+            
+            
+              stm32f7xx_ll_tim.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c
+              
+                
+                  2
+                  0
+                  0
+                  0
+                  0
+                  1
+                  2
+                  2
+                  2
+                  2
+                  11
+                  
+                  
+                  1
+                
+                
+                  
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    
+                      
+                      
+                      
+                      
+                    
+                  
+                
+              
+            
+            
+              stm32f7xx_ll_usart.c
+              1
+              ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c
+              
+                
+                  2
+                  0
+                  0
+                  0
+                  0
+                  1
+                  2
+                  2
+                  2
+                  2
+                  11
+                  
+                  
+                  1
+                
+                
+                  
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    0
+                    0
+                    2
+                    2
+                    2
+                    2
+                    2
+                    
+                      
+                      
+                      
+                      
+                    
+                  
+                
+              
+            
+          
+        
+        
+          Drivers/CMSIS
+          
+            
+              system_stm32f7xx.c
+              1
+              ../Src/system_stm32f7xx.c
+            
+          
+        
+        
+          Middlewares/FatFs
+          
+            
+              diskio.c
+              1
+              ../Middlewares/Third_Party/FatFs/src/diskio.c
+            
+            
+              ff.c
+              1
+              ../Middlewares/Third_Party/FatFs/src/ff.c
+            
+            
+              ff_gen_drv.c
+              1
+              ../Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
+            
+            
+              syscall.c
+              1
+              ../Middlewares/Third_Party/FatFs/src/option/syscall.c
+            
+          
+        
+        
+          ::CMSIS
+        
+      
+    
+  
+
+  
+    
+    
+      
+        
+        
+          
+        
+      
+    
+    
+  
+
+  
+    
+      
+        For_stm32
+        0
+        1
+      
+    
+  
+
+
diff --git a/MDK-ARM/For_stm32/ExtDll.iex b/MDK-ARM/For_stm32/ExtDll.iex
new file mode 100644
index 0000000..6c0896e
--- /dev/null
+++ b/MDK-ARM/For_stm32/ExtDll.iex
@@ -0,0 +1,2 @@
+[EXTDLL]
+Count=0
diff --git a/MDK-ARM/For_stm32/For_stm32.lnp b/MDK-ARM/For_stm32/For_stm32.lnp
new file mode 100644
index 0000000..4f55651
--- /dev/null
+++ b/MDK-ARM/For_stm32/For_stm32.lnp
@@ -0,0 +1,47 @@
+--cpu Cortex-M7.fp.dp
+"for_stm32\startup_stm32f767xx.o"
+"for_stm32\file_handling.o"
+"for_stm32\main.o"
+"for_stm32\bsp_driver_sd.o"
+"for_stm32\sd_diskio.o"
+"for_stm32\fatfs.o"
+"for_stm32\fatfs_platform.o"
+"for_stm32\stm32f7xx_it.o"
+"for_stm32\stm32f7xx_hal_msp.o"
+"for_stm32\stm32f7xx_hal_adc.o"
+"for_stm32\stm32f7xx_hal_adc_ex.o"
+"for_stm32\stm32f7xx_hal_rcc.o"
+"for_stm32\stm32f7xx_hal_rcc_ex.o"
+"for_stm32\stm32f7xx_hal_flash.o"
+"for_stm32\stm32f7xx_hal_flash_ex.o"
+"for_stm32\stm32f7xx_hal_gpio.o"
+"for_stm32\stm32f7xx_hal_dma.o"
+"for_stm32\stm32f7xx_hal_dma_ex.o"
+"for_stm32\stm32f7xx_hal_pwr.o"
+"for_stm32\stm32f7xx_hal_pwr_ex.o"
+"for_stm32\stm32f7xx_hal_cortex.o"
+"for_stm32\stm32f7xx_hal.o"
+"for_stm32\stm32f7xx_hal_i2c.o"
+"for_stm32\stm32f7xx_hal_i2c_ex.o"
+"for_stm32\stm32f7xx_hal_exti.o"
+"for_stm32\stm32f7xx_ll_rcc.o"
+"for_stm32\stm32f7xx_ll_utils.o"
+"for_stm32\stm32f7xx_ll_exti.o"
+"for_stm32\stm32f7xx_ll_gpio.o"
+"for_stm32\stm32f7xx_ll_dma.o"
+"for_stm32\stm32f7xx_ll_sdmmc.o"
+"for_stm32\stm32f7xx_hal_sd.o"
+"for_stm32\stm32f7xx_ll_spi.o"
+"for_stm32\stm32f7xx_hal_tim.o"
+"for_stm32\stm32f7xx_hal_tim_ex.o"
+"for_stm32\stm32f7xx_ll_tim.o"
+"for_stm32\stm32f7xx_ll_usart.o"
+"for_stm32\system_stm32f7xx.o"
+"for_stm32\diskio.o"
+"for_stm32\ff.o"
+"for_stm32\ff_gen_drv.o"
+"for_stm32\syscall.o"
+--strict --scatter "For_stm32\For_stm32.sct"
+--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+--list "For_stm32.map" -o For_stm32\For_stm32.axf
\ No newline at end of file
diff --git a/MDK-ARM/For_stm32/For_stm32.sct b/MDK-ARM/For_stm32/For_stm32.sct
new file mode 100644
index 0000000..bb4f637
--- /dev/null
+++ b/MDK-ARM/For_stm32/For_stm32.sct
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00200000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00200000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00080000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/MDK-ARM/For_stm32/For_stm32_sct.Bak b/MDK-ARM/For_stm32/For_stm32_sct.Bak
new file mode 100644
index 0000000..c668c36
--- /dev/null
+++ b/MDK-ARM/For_stm32/For_stm32_sct.Bak
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00200000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00200000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00080000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/MDK-ARM/For_stm32/bsp_driver_sd.crf b/MDK-ARM/For_stm32/bsp_driver_sd.crf
new file mode 100644
index 0000000..b97d78c
Binary files /dev/null and b/MDK-ARM/For_stm32/bsp_driver_sd.crf differ
diff --git a/MDK-ARM/For_stm32/diskio.crf b/MDK-ARM/For_stm32/diskio.crf
new file mode 100644
index 0000000..f9ca472
Binary files /dev/null and b/MDK-ARM/For_stm32/diskio.crf differ
diff --git a/MDK-ARM/For_stm32/fatfs.crf b/MDK-ARM/For_stm32/fatfs.crf
new file mode 100644
index 0000000..d309c69
Binary files /dev/null and b/MDK-ARM/For_stm32/fatfs.crf differ
diff --git a/MDK-ARM/For_stm32/fatfs_platform.crf b/MDK-ARM/For_stm32/fatfs_platform.crf
new file mode 100644
index 0000000..3eda6a1
Binary files /dev/null and b/MDK-ARM/For_stm32/fatfs_platform.crf differ
diff --git a/MDK-ARM/For_stm32/ff.crf b/MDK-ARM/For_stm32/ff.crf
new file mode 100644
index 0000000..75bd932
Binary files /dev/null and b/MDK-ARM/For_stm32/ff.crf differ
diff --git a/MDK-ARM/For_stm32/ff_gen_drv.crf b/MDK-ARM/For_stm32/ff_gen_drv.crf
new file mode 100644
index 0000000..50808bf
Binary files /dev/null and b/MDK-ARM/For_stm32/ff_gen_drv.crf differ
diff --git a/MDK-ARM/For_stm32/file_handling.crf b/MDK-ARM/For_stm32/file_handling.crf
new file mode 100644
index 0000000..b466ec0
Binary files /dev/null and b/MDK-ARM/For_stm32/file_handling.crf differ
diff --git a/MDK-ARM/For_stm32/main.crf b/MDK-ARM/For_stm32/main.crf
new file mode 100644
index 0000000..a06b131
Binary files /dev/null and b/MDK-ARM/For_stm32/main.crf differ
diff --git a/MDK-ARM/For_stm32/sd_diskio.crf b/MDK-ARM/For_stm32/sd_diskio.crf
new file mode 100644
index 0000000..3573dfb
Binary files /dev/null and b/MDK-ARM/For_stm32/sd_diskio.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal.crf b/MDK-ARM/For_stm32/stm32f7xx_hal.crf
new file mode 100644
index 0000000..e1b7ad8
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_adc.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_adc.crf
new file mode 100644
index 0000000..f3c29c2
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_adc.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_adc_ex.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_adc_ex.crf
new file mode 100644
index 0000000..76340b3
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_adc_ex.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_cortex.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_cortex.crf
new file mode 100644
index 0000000..e7c4eb0
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_cortex.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_dma.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_dma.crf
new file mode 100644
index 0000000..631dc82
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_dma.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_dma_ex.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_dma_ex.crf
new file mode 100644
index 0000000..12b0192
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_dma_ex.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_exti.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_exti.crf
new file mode 100644
index 0000000..9460855
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_exti.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_flash.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_flash.crf
new file mode 100644
index 0000000..64197e9
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_flash.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_flash_ex.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_flash_ex.crf
new file mode 100644
index 0000000..8ae7ac0
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_flash_ex.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_gpio.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_gpio.crf
new file mode 100644
index 0000000..e0c8d53
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_gpio.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_i2c.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_i2c.crf
new file mode 100644
index 0000000..5a8b951
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_i2c.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_i2c_ex.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_i2c_ex.crf
new file mode 100644
index 0000000..a3746ce
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_i2c_ex.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_msp.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_msp.crf
new file mode 100644
index 0000000..0175a9d
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_msp.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_pwr.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_pwr.crf
new file mode 100644
index 0000000..c82d454
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_pwr.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_pwr_ex.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_pwr_ex.crf
new file mode 100644
index 0000000..0126768
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_pwr_ex.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_rcc.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_rcc.crf
new file mode 100644
index 0000000..817f4de
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_rcc.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_rcc_ex.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_rcc_ex.crf
new file mode 100644
index 0000000..990bea4
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_rcc_ex.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_sd.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_sd.crf
new file mode 100644
index 0000000..78c31fe
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_sd.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_spi.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_spi.crf
new file mode 100644
index 0000000..bf3e443
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_spi.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_spi_ex.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_spi_ex.crf
new file mode 100644
index 0000000..8d55ae9
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_spi_ex.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_tim.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_tim.crf
new file mode 100644
index 0000000..f2f1cf4
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_tim.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_tim_ex.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_tim_ex.crf
new file mode 100644
index 0000000..85fdbf1
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_tim_ex.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_uart.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_uart.crf
new file mode 100644
index 0000000..e33d424
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_uart.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_hal_uart_ex.crf b/MDK-ARM/For_stm32/stm32f7xx_hal_uart_ex.crf
new file mode 100644
index 0000000..057310f
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_hal_uart_ex.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_it.crf b/MDK-ARM/For_stm32/stm32f7xx_it.crf
new file mode 100644
index 0000000..0ae975c
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_it.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_ll_adc.crf b/MDK-ARM/For_stm32/stm32f7xx_ll_adc.crf
new file mode 100644
index 0000000..c1c05bd
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_ll_adc.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_ll_dma.crf b/MDK-ARM/For_stm32/stm32f7xx_ll_dma.crf
new file mode 100644
index 0000000..38baa55
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_ll_dma.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_ll_exti.crf b/MDK-ARM/For_stm32/stm32f7xx_ll_exti.crf
new file mode 100644
index 0000000..beb57bc
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_ll_exti.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_ll_gpio.crf b/MDK-ARM/For_stm32/stm32f7xx_ll_gpio.crf
new file mode 100644
index 0000000..6f54542
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_ll_gpio.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_ll_rcc.crf b/MDK-ARM/For_stm32/stm32f7xx_ll_rcc.crf
new file mode 100644
index 0000000..ef951a6
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_ll_rcc.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_ll_sdmmc.crf b/MDK-ARM/For_stm32/stm32f7xx_ll_sdmmc.crf
new file mode 100644
index 0000000..4bd1a29
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_ll_sdmmc.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_ll_spi.crf b/MDK-ARM/For_stm32/stm32f7xx_ll_spi.crf
new file mode 100644
index 0000000..b53672b
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_ll_spi.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_ll_tim.crf b/MDK-ARM/For_stm32/stm32f7xx_ll_tim.crf
new file mode 100644
index 0000000..47ce695
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_ll_tim.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_ll_usart.crf b/MDK-ARM/For_stm32/stm32f7xx_ll_usart.crf
new file mode 100644
index 0000000..08fad1b
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_ll_usart.crf differ
diff --git a/MDK-ARM/For_stm32/stm32f7xx_ll_utils.crf b/MDK-ARM/For_stm32/stm32f7xx_ll_utils.crf
new file mode 100644
index 0000000..325be36
Binary files /dev/null and b/MDK-ARM/For_stm32/stm32f7xx_ll_utils.crf differ
diff --git a/MDK-ARM/For_stm32/syscall.crf b/MDK-ARM/For_stm32/syscall.crf
new file mode 100644
index 0000000..578a6da
Binary files /dev/null and b/MDK-ARM/For_stm32/syscall.crf differ
diff --git a/MDK-ARM/For_stm32/system_stm32f7xx.crf b/MDK-ARM/For_stm32/system_stm32f7xx.crf
new file mode 100644
index 0000000..b5633a6
Binary files /dev/null and b/MDK-ARM/For_stm32/system_stm32f7xx.crf differ
diff --git a/MDK-ARM/startup_stm32f767xx.s b/MDK-ARM/startup_stm32f767xx.s
new file mode 100644
index 0000000..c7dee5c
--- /dev/null
+++ b/MDK-ARM/startup_stm32f767xx.s
@@ -0,0 +1,502 @@
+;*******************************************************************************
+;* File Name          : startup_stm32f767xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32F767xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM7 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size		EQU     0x4000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size      EQU     0x2000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FMC_IRQHandler                    ; FMC                                             
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     0                                 ; Reserved                                     
+                DCD     RNG_IRQHandler                    ; Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     QUADSPI_IRQHandler                ; QUADSPI
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     0                                 ; Reserved
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     SDMMC2_IRQHandler                 ; SDMMC2
+                DCD     CAN3_TX_IRQHandler                ; CAN3 TX
+                DCD     CAN3_RX0_IRQHandler               ; CAN3 RX0
+                DCD     CAN3_RX1_IRQHandler               ; CAN3 RX1
+                DCD     CAN3_SCE_IRQHandler               ; CAN3 SCE
+                DCD     JPEG_IRQHandler                   ; JPEG
+                DCD     MDIOS_IRQHandler                  ; MDIOS
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FMC_IRQHandler                    [WEAK]                                             
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                                                                  
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]   
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]   
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK] 
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]
+                EXPORT  CAN3_TX_IRQHandler                [WEAK]
+                EXPORT  CAN3_RX0_IRQHandler               [WEAK]
+                EXPORT  CAN3_RX1_IRQHandler               [WEAK]
+                EXPORT  CAN3_SCE_IRQHandler               [WEAK]
+                EXPORT  JPEG_IRQHandler                   [WEAK]
+                EXPORT  MDIOS_IRQHandler                  [WEAK]
+                
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FMC_IRQHandler                                                            
+SDMMC1_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                                                                                
+RNG_IRQHandler
+FPU_IRQHandler  
+UART7_IRQHandler                  
+UART8_IRQHandler                  
+SPI4_IRQHandler                   
+SPI5_IRQHandler                   
+SPI6_IRQHandler                   
+SAI1_IRQHandler                 
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler   
+SAI2_IRQHandler        
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SDMMC2_IRQHandler
+CAN3_TX_IRQHandler
+CAN3_RX0_IRQHandler
+CAN3_RX1_IRQHandler
+CAN3_SCE_IRQHandler
+JPEG_IRQHandler
+MDIOS_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..8e79b95
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,225 @@
+##########################################################################################################################
+# File automatically-generated by tool: [projectgenerator] version: [4.5.0-B34] date: [Wed Dec 11 12:01:07 MSK 2024]
+##########################################################################################################################
+
+# ------------------------------------------------
+# Generic Makefile (based on gcc)
+#
+# ChangeLog :
+#	2017-02-10 - Several enhancements + project update mode
+#   2015-07-22 - first version
+# ------------------------------------------------
+
+######################################
+# target
+######################################
+TARGET = For_stm32
+
+
+######################################
+# building variables
+######################################
+# debug build?
+DEBUG = 1
+# optimization
+OPT = -Og
+
+
+#######################################
+# paths
+#######################################
+# Build path
+BUILD_DIR = build
+
+######################################
+# source
+######################################
+# C sources
+C_SOURCES =  \
+Src/main.c \
+Src/bsp_driver_sd.c \
+Src/sd_diskio.c \
+Src/fatfs.c \
+Src/fatfs_platform.c \
+Src/stm32f7xx_it.c \
+Src/stm32f7xx_hal_msp.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c \
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c \
+Src/system_stm32f7xx.c \
+Middlewares/Third_Party/FatFs/src/diskio.c \
+Middlewares/Third_Party/FatFs/src/ff.c \
+Middlewares/Third_Party/FatFs/src/ff_gen_drv.c \
+Middlewares/Third_Party/FatFs/src/option/syscall.c \
+Src/sysmem.c \
+Src/syscalls.c  
+
+# ASM sources
+ASM_SOURCES =  \
+startup_stm32f767xx.s
+
+# ASM sources
+ASMM_SOURCES = 
+
+
+#######################################
+# binaries
+#######################################
+PREFIX = arm-none-eabi-
+# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx)
+# either it can be added to the PATH environment variable.
+ifdef GCC_PATH
+CC = $(GCC_PATH)/$(PREFIX)gcc
+AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp
+CP = $(GCC_PATH)/$(PREFIX)objcopy
+SZ = $(GCC_PATH)/$(PREFIX)size
+else
+CC = $(PREFIX)gcc
+AS = $(PREFIX)gcc -x assembler-with-cpp
+CP = $(PREFIX)objcopy
+SZ = $(PREFIX)size
+endif
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary -S
+ 
+#######################################
+# CFLAGS
+#######################################
+# cpu
+CPU = -mcpu=cortex-m7
+
+# fpu
+FPU = -mfpu=fpv5-d16
+
+# float-abi
+FLOAT-ABI = -mfloat-abi=hard
+
+# mcu
+MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
+
+# macros for gcc
+# AS defines
+AS_DEFS = 
+
+# C defines
+C_DEFS =  \
+-DUSE_FULL_LL_DRIVER \
+-DUSE_HAL_DRIVER \
+-DSTM32F767xx
+
+
+# AS includes
+AS_INCLUDES = 
+
+# C includes
+C_INCLUDES =  \
+-IInc \
+-IDrivers/STM32F7xx_HAL_Driver/Inc \
+-IDrivers/STM32F7xx_HAL_Driver/Inc/Legacy \
+-IMiddlewares/Third_Party/FatFs/src \
+-IDrivers/CMSIS/Device/ST/STM32F7xx/Include \
+-IDrivers/CMSIS/Include
+
+
+# compile gcc flags
+ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
+
+CFLAGS += $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
+
+ifeq ($(DEBUG), 1)
+CFLAGS += -g -gdwarf-2
+endif
+
+
+# Generate dependency information
+CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
+
+
+#######################################
+# LDFLAGS
+#######################################
+# link script
+LDSCRIPT = STM32F767ZITx_FLASH.ld
+
+# libraries
+LIBS = -lc -lm -lnosys 
+LIBDIR = 
+LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
+
+# default action: build all
+all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
+
+
+#######################################
+# build the application
+#######################################
+# list of objects
+OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
+vpath %.c $(sort $(dir $(C_SOURCES)))
+# list of ASM program objects
+OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
+vpath %.s $(sort $(dir $(ASM_SOURCES)))
+OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASMM_SOURCES:.S=.o)))
+vpath %.S $(sort $(dir $(ASMM_SOURCES)))
+
+$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) 
+	$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
+
+$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
+	$(AS) -c $(CFLAGS) $< -o $@
+$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR)
+	$(AS) -c $(CFLAGS) $< -o $@
+
+$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
+	$(info    CC is $(CC))
+	$(info    OBJECTS is $(OBJECTS))
+	$(info    LDFLAGS is $(LDFLAGS))
+	$(CC) $(OBJECTS) $(LDFLAGS) -o $@
+	$(SZ) $@
+
+$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
+	$(HEX) $< $@
+	
+$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
+	$(BIN) $< $@	
+	
+$(BUILD_DIR):
+	mkdir $@		
+
+#######################################
+# clean up
+#######################################
+clean:
+	-rm -fR $(BUILD_DIR)
+  
+#######################################
+# dependencies
+#######################################
+-include $(wildcard $(BUILD_DIR)/*.d)
+
+# *** EOF ***
diff --git a/Middlewares/Third_Party/FatFs/src/diskio.c b/Middlewares/Third_Party/FatFs/src/diskio.c
new file mode 100644
index 0000000..6c0881f
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/diskio.c
@@ -0,0 +1,141 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs     (C)ChaN, 2017        */
+/*                                                                       */
+/*   Portions COPYRIGHT 2017 STMicroelectronics                          */
+/*   Portions Copyright (C) 2017, ChaN, all right reserved               */
+/*-----------------------------------------------------------------------*/
+/* If a working storage control module is available, it should be        */
+/* attached to the FatFs via a glue function rather than modifying it.   */
+/* This is an example of glue functions to attach various existing      */
+/* storage control modules to the FatFs module with a defined API.       */
+/*-----------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "diskio.h"
+#include "ff_gen_drv.h"
+
+#if defined ( __GNUC__ )
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif
+#endif
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern Disk_drvTypeDef  disk;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Gets Disk Status
+  * @param  pdrv: Physical drive number (0..)
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS disk_status (
+	BYTE pdrv		/* Physical drive number to identify the drive */
+)
+{
+  DSTATUS stat;
+
+  stat = disk.drv[pdrv]->disk_status(disk.lun[pdrv]);
+  return stat;
+}
+
+/**
+  * @brief  Initializes a Drive
+  * @param  pdrv: Physical drive number (0..)
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS disk_initialize (
+	BYTE pdrv				/* Physical drive nmuber to identify the drive */
+)
+{
+  DSTATUS stat = RES_OK;
+
+  if(disk.is_initialized[pdrv] == 0)
+  {
+    disk.is_initialized[pdrv] = 1;
+    stat = disk.drv[pdrv]->disk_initialize(disk.lun[pdrv]);
+  }
+  return stat;
+}
+
+/**
+  * @brief  Reads Sector(s)
+  * @param  pdrv: Physical drive number (0..)
+  * @param  *buff: Data buffer to store read data
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to read (1..128)
+  * @retval DRESULT: Operation result
+  */
+DRESULT disk_read (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	BYTE *buff,		/* Data buffer to store read data */
+	DWORD sector,	        /* Sector address in LBA */
+	UINT count		/* Number of sectors to read */
+)
+{
+  DRESULT res;
+
+  res = disk.drv[pdrv]->disk_read(disk.lun[pdrv], buff, sector, count);
+  return res;
+}
+
+/**
+  * @brief  Writes Sector(s)
+  * @param  pdrv: Physical drive number (0..)
+  * @param  *buff: Data to be written
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to write (1..128)
+  * @retval DRESULT: Operation result
+  */
+#if _USE_WRITE == 1
+DRESULT disk_write (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	const BYTE *buff,	/* Data to be written */
+	DWORD sector,		/* Sector address in LBA */
+	UINT count        	/* Number of sectors to write */
+)
+{
+  DRESULT res;
+
+  res = disk.drv[pdrv]->disk_write(disk.lun[pdrv], buff, sector, count);
+  return res;
+}
+#endif /* _USE_WRITE == 1 */
+
+/**
+  * @brief  I/O control operation
+  * @param  pdrv: Physical drive number (0..)
+  * @param  cmd: Control code
+  * @param  *buff: Buffer to send/receive control data
+  * @retval DRESULT: Operation result
+  */
+#if _USE_IOCTL == 1
+DRESULT disk_ioctl (
+	BYTE pdrv,		/* Physical drive nmuber (0..) */
+	BYTE cmd,		/* Control code */
+	void *buff		/* Buffer to send/receive control data */
+)
+{
+  DRESULT res;
+
+  res = disk.drv[pdrv]->disk_ioctl(disk.lun[pdrv], cmd, buff);
+  return res;
+}
+#endif /* _USE_IOCTL == 1 */
+
+/**
+  * @brief  Gets Time from RTC
+  * @param  None
+  * @retval Time in DWORD
+  */
+__weak DWORD get_fattime (void)
+{
+  return 0;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/Third_Party/FatFs/src/diskio.h b/Middlewares/Third_Party/FatFs/src/diskio.h
new file mode 100644
index 0000000..7a417d9
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/diskio.h
@@ -0,0 +1,80 @@
+/*-----------------------------------------------------------------------/
+/  Low level disk interface modlue include file   (C)ChaN, 2014          /
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO_DEFINED
+#define _DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _USE_WRITE	1	/* 1: Enable disk_write function */
+#define _USE_IOCTL	1	/* 1: Enable disk_ioctl function */
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Successful */
+	RES_ERROR,		/* 1: R/W Error */
+	RES_WRPRT,		/* 2: Write Protected */
+	RES_NOTRDY,		/* 3: Not Ready */
+	RES_PARERR		/* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+
+DSTATUS disk_initialize (BYTE pdrv);
+DSTATUS disk_status (BYTE pdrv);
+DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+DWORD get_fattime (void);
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+#define STA_PROTECT		0x04	/* Write protected */
+
+
+/* Command code for disk_ioctrl fucntion */
+
+/* Generic command (Used by FatFs) */
+#define CTRL_SYNC		0	/* Complete pending write process (needed at _FS_READONLY == 0) */
+#define GET_SECTOR_COUNT	1	/* Get media size (needed at _USE_MKFS == 1) */
+#define GET_SECTOR_SIZE		2	/* Get sector size (needed at _MAX_SS != _MIN_SS) */
+#define GET_BLOCK_SIZE		3	/* Get erase block size (needed at _USE_MKFS == 1) */
+#define CTRL_TRIM		4	/* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */
+
+/* Generic command (Not used by FatFs) */
+#define CTRL_POWER			5	/* Get/Set power status */
+#define CTRL_LOCK			6	/* Lock/Unlock media removal */
+#define CTRL_EJECT			7	/* Eject media */
+#define CTRL_FORMAT			8	/* Create physical format on the media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE		10	/* Get card type */
+#define MMC_GET_CSD			11	/* Get CSD */
+#define MMC_GET_CID			12	/* Get CID */
+#define MMC_GET_OCR			13	/* Get OCR */
+#define MMC_GET_SDSTAT		14	/* Get SD status */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV			20	/* Get F/W revision */
+#define ATA_GET_MODEL		21	/* Get model name */
+#define ATA_GET_SN			22	/* Get serial number */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Middlewares/Third_Party/FatFs/src/ff.c b/Middlewares/Third_Party/FatFs/src/ff.c
new file mode 100644
index 0000000..253de3c
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff.c
@@ -0,0 +1,6140 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT file system module  R0.12c                             /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2017, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+
+
+#include "ff.h"			/* Declarations of FatFs API */
+#include "diskio.h"		/* Declarations of device I/O functions */
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if _FATFS != 68300	/* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+
+/* DBCS code ranges and SBCS upper conversion tables */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 771	/* KBL */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Latin 1 */
+#define _DF1S	0
+#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \
+				0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \
+				0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \
+				0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \
+				0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 860	/* Portuguese */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \
+				0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 861	/* Icelandic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 863	/* Canadian-French */
+#define _DF1S	0
+#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \
+				0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \
+				0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 864	/* Arabic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 865	/* Nordic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 869	/* Greek 2 */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \
+				0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \
+				0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \
+				0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#if _USE_LFN != 0
+#error Cannot enable LFN without valid code page.
+#endif
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+/* Character code support macros */
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+#define IsDigit(c)	(((c)>='0')&&((c)<='9'))
+
+#if _DF1S != 0	/* Code page is DBCS */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* Code page is SBCS */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* Additional file attribute bits for internal use */
+#define	AM_VOL		0x08	/* Volume label */
+#define AM_LFN		0x0F	/* LFN entry */
+#define AM_MASK		0x3F	/* Mask of defined bits */
+
+
+/* Additional file access control and file status flags for internal use */
+#define FA_SEEKEND	0x20	/* Seek to end of the file on file open */
+#define FA_MODIFIED	0x40	/* File has been modified */
+#define FA_DIRTY	0x80	/* FIL.buf[] needs to be written-back */
+
+
+/* Name status flags in fn[] */
+#define NSFLAG		11		/* Index of the name status byte */
+#define NS_LOSS		0x01	/* Out of 8.3 format */
+#define NS_LFN		0x02	/* Force to create LFN entry */
+#define NS_LAST		0x04	/* Last segment */
+#define NS_BODY		0x08	/* Lower case flag (body) */
+#define NS_EXT		0x10	/* Lower case flag (ext) */
+#define NS_DOT		0x20	/* Dot entry */
+#define NS_NOLFN	0x40	/* Do not find LFN */
+#define NS_NONAME	0x80	/* Not followed */
+
+
+/* Limits and boundaries */
+#define MAX_DIR		0x200000		/* Max size of FAT directory */
+#define MAX_DIR_EX	0x10000000		/* Max size of exFAT directory */
+#define MAX_FAT12	0xFF5			/* Max FAT12 clusters (differs from specs, but correct for real DOS/Windows behavior) */
+#define	MAX_FAT16	0xFFF5			/* Max FAT16 clusters (differs from specs, but correct for real DOS/Windows behavior) */
+#define	MAX_FAT32	0x0FFFFFF5		/* Max FAT32 clusters (not specified, practical limit) */
+#define	MAX_EXFAT	0x7FFFFFFD		/* Max exFAT clusters (differs from specs, implementation limit) */
+
+
+/* FatFs refers the FAT structure as simple byte array instead of structure member
+/ because the C structure is not binary compatible between different platforms */
+
+#define BS_JmpBoot			0		/* x86 jump instruction (3-byte) */
+#define BS_OEMName			3		/* OEM name (8-byte) */
+#define BPB_BytsPerSec		11		/* Sector size [byte] (WORD) */
+#define BPB_SecPerClus		13		/* Cluster size [sector] (BYTE) */
+#define BPB_RsvdSecCnt		14		/* Size of reserved area [sector] (WORD) */
+#define BPB_NumFATs			16		/* Number of FATs (BYTE) */
+#define BPB_RootEntCnt		17		/* Size of root directory area for FAT12/16 [entry] (WORD) */
+#define BPB_TotSec16		19		/* Volume size (16-bit) [sector] (WORD) */
+#define BPB_Media			21		/* Media descriptor byte (BYTE) */
+#define BPB_FATSz16			22		/* FAT size (16-bit) [sector] (WORD) */
+#define BPB_SecPerTrk		24		/* Track size for int13h [sector] (WORD) */
+#define BPB_NumHeads		26		/* Number of heads for int13h (WORD) */
+#define BPB_HiddSec			28		/* Volume offset from top of the drive (DWORD) */
+#define BPB_TotSec32		32		/* Volume size (32-bit) [sector] (DWORD) */
+#define BS_DrvNum			36		/* Physical drive number for int13h (BYTE) */
+#define BS_NTres			37		/* Error flag (BYTE) */
+#define BS_BootSig			38		/* Extended boot signature (BYTE) */
+#define BS_VolID			39		/* Volume serial number (DWORD) */
+#define BS_VolLab			43		/* Volume label string (8-byte) */
+#define BS_FilSysType		54		/* File system type string (8-byte) */
+#define BS_BootCode			62		/* Boot code (448-byte) */
+#define BS_55AA				510		/* Signature word (WORD) */
+
+#define BPB_FATSz32			36		/* FAT32: FAT size [sector] (DWORD) */
+#define BPB_ExtFlags32		40		/* FAT32: Extended flags (WORD) */
+#define BPB_FSVer32			42		/* FAT32: File system version (WORD) */
+#define BPB_RootClus32		44		/* FAT32: Root directory cluster (DWORD) */
+#define BPB_FSInfo32		48		/* FAT32: Offset of FSINFO sector (WORD) */
+#define BPB_BkBootSec32		50		/* FAT32: Offset of backup boot sector (WORD) */
+#define BS_DrvNum32			64		/* FAT32: Physical drive number for int13h (BYTE) */
+#define BS_NTres32			65		/* FAT32: Error flag (BYTE) */
+#define BS_BootSig32		66		/* FAT32: Extended boot signature (BYTE) */
+#define BS_VolID32			67		/* FAT32: Volume serial number (DWORD) */
+#define BS_VolLab32			71		/* FAT32: Volume label string (8-byte) */
+#define BS_FilSysType32		82		/* FAT32: File system type string (8-byte) */
+#define BS_BootCode32		90		/* FAT32: Boot code (420-byte) */
+
+#define BPB_ZeroedEx		11		/* exFAT: MBZ field (53-byte) */
+#define BPB_VolOfsEx		64		/* exFAT: Volume offset from top of the drive [sector] (QWORD) */
+#define BPB_TotSecEx		72		/* exFAT: Volume size [sector] (QWORD) */
+#define BPB_FatOfsEx		80		/* exFAT: FAT offset from top of the volume [sector] (DWORD) */
+#define BPB_FatSzEx			84		/* exFAT: FAT size [sector] (DWORD) */
+#define BPB_DataOfsEx		88		/* exFAT: Data offset from top of the volume [sector] (DWORD) */
+#define BPB_NumClusEx		92		/* exFAT: Number of clusters (DWORD) */
+#define BPB_RootClusEx		96		/* exFAT: Root directory start cluster (DWORD) */
+#define BPB_VolIDEx			100		/* exFAT: Volume serial number (DWORD) */
+#define BPB_FSVerEx			104		/* exFAT: File system version (WORD) */
+#define BPB_VolFlagEx		106		/* exFAT: Volume flags (BYTE) */
+#define BPB_ActFatEx		107		/* exFAT: Active FAT flags (BYTE) */
+#define BPB_BytsPerSecEx	108		/* exFAT: Log2 of sector size in unit of byte (BYTE) */
+#define BPB_SecPerClusEx	109		/* exFAT: Log2 of cluster size in unit of sector (BYTE) */
+#define BPB_NumFATsEx		110		/* exFAT: Number of FATs (BYTE) */
+#define BPB_DrvNumEx		111		/* exFAT: Physical drive number for int13h (BYTE) */
+#define BPB_PercInUseEx		112		/* exFAT: Percent in use (BYTE) */
+#define	BPB_RsvdEx			113		/* exFAT: Reserved (7-byte) */
+#define BS_BootCodeEx		120		/* exFAT: Boot code (390-byte) */
+
+#define	DIR_Name			0		/* Short file name (11-byte) */
+#define	DIR_Attr			11		/* Attribute (BYTE) */
+#define	DIR_NTres			12		/* Lower case flag (BYTE) */
+#define DIR_CrtTime10		13		/* Created time sub-second (BYTE) */
+#define	DIR_CrtTime			14		/* Created time (DWORD) */
+#define DIR_LstAccDate		18		/* Last accessed date (WORD) */
+#define	DIR_FstClusHI		20		/* Higher 16-bit of first cluster (WORD) */
+#define	DIR_ModTime			22		/* Modified time (DWORD) */
+#define	DIR_FstClusLO		26		/* Lower 16-bit of first cluster (WORD) */
+#define	DIR_FileSize		28		/* File size (DWORD) */
+#define	LDIR_Ord			0		/* LFN: LFN order and LLE flag (BYTE) */
+#define	LDIR_Attr			11		/* LFN: LFN attribute (BYTE) */
+#define	LDIR_Type			12		/* LFN: Entry type (BYTE) */
+#define	LDIR_Chksum			13		/* LFN: Checksum of the SFN (BYTE) */
+#define	LDIR_FstClusLO		26		/* LFN: MBZ field (WORD) */
+#define	XDIR_Type			0		/* exFAT: Type of exFAT directory entry (BYTE) */
+#define	XDIR_NumLabel		1		/* exFAT: Number of volume label characters (BYTE) */
+#define	XDIR_Label			2		/* exFAT: Volume label (11-WORD) */
+#define	XDIR_CaseSum		4		/* exFAT: Sum of case conversion table (DWORD) */
+#define	XDIR_NumSec			1		/* exFAT: Number of secondary entries (BYTE) */
+#define	XDIR_SetSum			2		/* exFAT: Sum of the set of directory entries (WORD) */
+#define	XDIR_Attr			4		/* exFAT: File attribute (WORD) */
+#define	XDIR_CrtTime		8		/* exFAT: Created time (DWORD) */
+#define	XDIR_ModTime		12		/* exFAT: Modified time (DWORD) */
+#define	XDIR_AccTime		16		/* exFAT: Last accessed time (DWORD) */
+#define	XDIR_CrtTime10		20		/* exFAT: Created time subsecond (BYTE) */
+#define	XDIR_ModTime10		21		/* exFAT: Modified time subsecond (BYTE) */
+#define	XDIR_CrtTZ			22		/* exFAT: Created timezone (BYTE) */
+#define	XDIR_ModTZ			23		/* exFAT: Modified timezone (BYTE) */
+#define	XDIR_AccTZ			24		/* exFAT: Last accessed timezone (BYTE) */
+#define	XDIR_GenFlags		33		/* exFAT: General secondary flags (WORD) */
+#define	XDIR_NumName		35		/* exFAT: Number of file name characters (BYTE) */
+#define	XDIR_NameHash		36		/* exFAT: Hash of file name (WORD) */
+#define XDIR_ValidFileSize	40		/* exFAT: Valid file size (QWORD) */
+#define	XDIR_FstClus		52		/* exFAT: First cluster of the file data (DWORD) */
+#define	XDIR_FileSize		56		/* exFAT: File/Directory size (QWORD) */
+
+#define	SZDIRE				32		/* Size of a directory entry */
+#define	DDEM				0xE5	/* Deleted directory entry mark set to DIR_Name[0] */
+#define	RDDEM				0x05	/* Replacement of the character collides with DDEM */
+#define	LLEF				0x40	/* Last long entry flag in LDIR_Ord */
+
+#define	FSI_LeadSig			0		/* FAT32 FSI: Leading signature (DWORD) */
+#define	FSI_StrucSig		484		/* FAT32 FSI: Structure signature (DWORD) */
+#define	FSI_Free_Count		488		/* FAT32 FSI: Number of free clusters (DWORD) */
+#define	FSI_Nxt_Free		492		/* FAT32 FSI: Last allocated cluster (DWORD) */
+
+#define MBR_Table			446		/* MBR: Offset of partition table in the MBR */
+#define	SZ_PTE				16		/* MBR: Size of a partition table entry */
+#define PTE_Boot			0		/* MBR PTE: Boot indicator */
+#define PTE_StHead			1		/* MBR PTE: Start head */
+#define PTE_StSec			2		/* MBR PTE: Start sector */
+#define PTE_StCyl			3		/* MBR PTE: Start cylinder */
+#define PTE_System			4		/* MBR PTE: System ID */
+#define PTE_EdHead			5		/* MBR PTE: End head */
+#define PTE_EdSec			6		/* MBR PTE: End sector */
+#define PTE_EdCyl			7		/* MBR PTE: End cylinder */
+#define PTE_StLba			8		/* MBR PTE: Start in LBA */
+#define PTE_SizLba			12		/* MBR PTE: Size in LBA */
+
+
+/* Post process after fatal error on file operation */
+#define	ABORT(fs, res)		{ fp->err = (BYTE)(res); LEAVE_FF(fs, res); }
+
+
+/* Reentrancy related */
+#if _FS_REENTRANT
+#if _USE_LFN == 1
+#error Static LFN work area cannot be used at thread-safe configuration
+#endif
+#define	ENTER_FF(fs)		{ if (!lock_fs(fs)) return FR_TIMEOUT; }
+#define	LEAVE_FF(fs, res)	{ unlock_fs(fs, res); return res; }
+#else
+#define	ENTER_FF(fs)
+#define LEAVE_FF(fs, res)	return res
+#endif
+
+
+/* Definitions of volume - partition conversion */
+#if _MULTI_PARTITION
+#define LD2PD(vol) VolToPart[vol].pd	/* Get physical drive number */
+#define LD2PT(vol) VolToPart[vol].pt	/* Get partition index */
+#else
+#define LD2PD(vol) (BYTE)(vol)	/* Each logical drive is bound to the same physical drive number */
+#define LD2PT(vol) 0			/* Find first valid partition or in SFD */
+#endif
+
+
+/* Definitions of sector size */
+#if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096) || (_MIN_SS != 512 && _MIN_SS != 1024 && _MIN_SS != 2048 && _MIN_SS != 4096)
+#error Wrong sector size configuration
+#endif
+#if _MAX_SS == _MIN_SS
+#define	SS(fs)	((UINT)_MAX_SS)	/* Fixed sector size */
+#else
+#define	SS(fs)	((fs)->ssize)	/* Variable sector size */
+#endif
+
+
+/* Timestamp */
+#if _FS_NORTC == 1
+#if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < 1 || _NORTC_MDAY > 31
+#error Invalid _FS_NORTC settings
+#endif
+#define GET_FATTIME()	((DWORD)(_NORTC_YEAR - 1980) << 25 | (DWORD)_NORTC_MON << 21 | (DWORD)_NORTC_MDAY << 16)
+#else
+#define GET_FATTIME()	get_fattime()
+#endif
+
+
+/* File lock controls */
+#if _FS_LOCK != 0
+#if _FS_READONLY
+#error _FS_LOCK must be 0 at read-only configuration
+#endif
+typedef struct {
+	FATFS *fs;		/* Object ID 1, volume (NULL:blank entry) */
+	DWORD clu;		/* Object ID 2, containing directory (0:root) */
+	DWORD ofs;		/* Object ID 3, offset in the directory */
+	WORD ctr;		/* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Work Area
+
+---------------------------------------------------------------------------*/
+
+/* Remark: Variables defined here without initial value shall be guaranteed
+/  zero/null at start-up. If not, the linker option or start-up routine is
+/  not compliance with C standard. */
+
+#if _VOLUMES < 1 || _VOLUMES > 10
+#error Wrong _VOLUMES setting
+#endif
+static FATFS *FatFs[_VOLUMES];	/* Pointer to the file system objects (logical drives) */
+static WORD Fsid;				/* File system mount ID */
+
+#if _FS_RPATH != 0 && _VOLUMES >= 2
+static BYTE CurrVol;			/* Current drive */
+#endif
+
+#if _FS_LOCK != 0
+static FILESEM Files[_FS_LOCK];	/* Open object lock semaphores */
+#endif
+
+#if _USE_LFN == 0		/* Non-LFN configuration */
+#define	DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define	FREE_NAMBUF()
+
+#else					/* LFN configuration */
+#if _MAX_LFN < 12 || _MAX_LFN > 255
+#error Wrong _MAX_LFN value
+#endif
+#define MAXDIRB(nc)	((nc + 44U) / 15 * SZDIRE)
+
+#if _USE_LFN == 1		/* LFN enabled with static working buffer */
+#if _FS_EXFAT
+static BYTE	DirBuf[MAXDIRB(_MAX_LFN)];	/* Directory entry block scratchpad buffer */
+#endif
+static WCHAR LfnBuf[_MAX_LFN + 1];	/* LFN enabled with static working buffer */
+#define	DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define	FREE_NAMBUF()
+
+#elif _USE_LFN == 2 	/* LFN enabled with dynamic working buffer on the stack */
+#if _FS_EXFAT
+#define	DEF_NAMBUF		WCHAR lbuf[_MAX_LFN+1]; BYTE dbuf[MAXDIRB(_MAX_LFN)];
+#define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; }
+#define	FREE_NAMBUF()
+#else
+#define	DEF_NAMBUF		WCHAR lbuf[_MAX_LFN+1];
+#define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; }
+#define	FREE_NAMBUF()
+#endif
+
+#elif _USE_LFN == 3 	/* LFN enabled with dynamic working buffer on the heap */
+#if _FS_EXFAT
+#define	DEF_NAMBUF		WCHAR *lfn;
+#define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((_MAX_LFN+1)*2 + MAXDIRB(_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+_MAX_LFN+1); }
+#define	FREE_NAMBUF()	ff_memfree(lfn)
+#else
+#define	DEF_NAMBUF		WCHAR *lfn;
+#define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; }
+#define	FREE_NAMBUF()	ff_memfree(lfn)
+#endif
+
+#else
+#error Wrong _USE_LFN setting
+
+#endif
+#endif	/* else _USE_LFN == 0 */
+
+#ifdef _EXCVT
+static const BYTE ExCvt[] = _EXCVT;	/* Upper conversion table for SBCS extended characters */
+#endif
+
+
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------------------*/
+/* Load/Store multi-byte word in the FAT structure                       */
+/*-----------------------------------------------------------------------*/
+
+static
+WORD ld_word (const BYTE* ptr)	/*	 Load a 2-byte little-endian word */
+{
+	WORD rv;
+
+	rv = ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+
+static
+DWORD ld_dword (const BYTE* ptr)	/* Load a 4-byte little-endian word */
+{
+	DWORD rv;
+
+	rv = ptr[3];
+	rv = rv << 8 | ptr[2];
+	rv = rv << 8 | ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+
+#if _FS_EXFAT
+static
+QWORD ld_qword (const BYTE* ptr)	/* Load an 8-byte little-endian word */
+{
+	QWORD rv;
+
+	rv = ptr[7];
+	rv = rv << 8 | ptr[6];
+	rv = rv << 8 | ptr[5];
+	rv = rv << 8 | ptr[4];
+	rv = rv << 8 | ptr[3];
+	rv = rv << 8 | ptr[2];
+	rv = rv << 8 | ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+#endif
+
+#if !_FS_READONLY
+static
+void st_word (BYTE* ptr, WORD val)	/* Store a 2-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+
+static
+void st_dword (BYTE* ptr, DWORD val)	/* Store a 4-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+
+#if _FS_EXFAT
+static
+void st_qword (BYTE* ptr, QWORD val)	/* Store an 8-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+#endif
+#endif	/* !_FS_READONLY */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* String functions                                                      */
+/*-----------------------------------------------------------------------*/
+
+/* Copy memory to memory */
+static
+void mem_cpy (void* dst, const void* src, UINT cnt) {
+	BYTE *d = (BYTE*)dst;
+	const BYTE *s = (const BYTE*)src;
+
+	if (cnt) {
+		do {
+			*d++ = *s++;
+		} while (--cnt);
+	}
+}
+
+/* Fill memory block */
+static
+void mem_set (void* dst, int val, UINT cnt) {
+	BYTE *d = (BYTE*)dst;
+
+	do {
+		*d++ = (BYTE)val;
+	} while (--cnt);
+}
+
+/* Compare memory block */
+static
+int mem_cmp (const void* dst, const void* src, UINT cnt) {	/* ZR:same, NZ:different */
+	const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
+	int r = 0;
+
+	do {
+		r = *d++ - *s++;
+	} while (--cnt && r == 0);
+
+	return r;
+}
+
+/* Check if chr is contained in the string */
+static
+int chk_chr (const char* str, int chr) {	/* NZ:contained, ZR:not contained */
+	while (*str && *str != chr) str++;
+	return *str;
+}
+
+
+
+
+#if _FS_REENTRANT
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume                            */
+/*-----------------------------------------------------------------------*/
+static
+int lock_fs (
+	FATFS* fs		/* File system object */
+)
+{
+	return (fs && ff_req_grant(fs->sobj)) ? 1 : 0;
+}
+
+
+static
+void unlock_fs (
+	FATFS* fs,		/* File system object */
+	FRESULT res		/* Result code to be returned */
+)
+{
+	if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) {
+		ff_rel_grant(fs->sobj);
+	}
+}
+
+#endif
+
+
+
+#if _FS_LOCK != 0
+/*-----------------------------------------------------------------------*/
+/* File lock control functions                                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT chk_lock (	/* Check if the file can be accessed */
+	DIR* dp,		/* Directory object pointing the file to be checked */
+	int acc			/* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i, be;
+
+	/* Search file semaphore table */
+	for (i = be = 0; i < _FS_LOCK; i++) {
+		if (Files[i].fs) {	/* Existing entry */
+			if (Files[i].fs == dp->obj.fs &&	 	/* Check if the object matched with an open object */
+				Files[i].clu == dp->obj.sclust &&
+				Files[i].ofs == dp->dptr) break;
+		} else {			/* Blank entry */
+			be = 1;
+		}
+	}
+	if (i == _FS_LOCK) {	/* The object is not opened */
+		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new object? */
+	}
+
+	/* The object has been opened. Reject any open against writing file and all write mode open */
+	return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+
+static
+int enq_lock (void)	/* Check if an entry is available for a new object */
+{
+	UINT i;
+
+	for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+	return (i == _FS_LOCK) ? 0 : 1;
+}
+
+
+static
+UINT inc_lock (	/* Increment object open counter and returns its index (0:Internal error) */
+	DIR* dp,	/* Directory object pointing the file to register or increment */
+	int acc		/* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i;
+
+
+	for (i = 0; i < _FS_LOCK; i++) {	/* Find the object */
+		if (Files[i].fs == dp->obj.fs &&
+			Files[i].clu == dp->obj.sclust &&
+			Files[i].ofs == dp->dptr) break;
+	}
+
+	if (i == _FS_LOCK) {				/* Not opened. Register it as new. */
+		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+		if (i == _FS_LOCK) return 0;	/* No free entry to register (int err) */
+		Files[i].fs = dp->obj.fs;
+		Files[i].clu = dp->obj.sclust;
+		Files[i].ofs = dp->dptr;
+		Files[i].ctr = 0;
+	}
+
+	if (acc && Files[i].ctr) return 0;	/* Access violation (int err) */
+
+	Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1;	/* Set semaphore value */
+
+	return i + 1;
+}
+
+
+static
+FRESULT dec_lock (	/* Decrement object open counter */
+	UINT i			/* Semaphore index (1..) */
+)
+{
+	WORD n;
+	FRESULT res;
+
+
+	if (--i < _FS_LOCK) {	/* Shift index number origin from 0 */
+		n = Files[i].ctr;
+		if (n == 0x100) n = 0;		/* If write mode open, delete the entry */
+		if (n > 0) n--;				/* Decrement read mode open count */
+		Files[i].ctr = n;
+		if (n == 0) Files[i].fs = 0;	/* Delete the entry if open count gets zero */
+		res = FR_OK;
+	} else {
+		res = FR_INT_ERR;			/* Invalid index nunber */
+	}
+	return res;
+}
+
+
+static
+void clear_lock (	/* Clear lock entries of the volume */
+	FATFS *fs
+)
+{
+	UINT i;
+
+	for (i = 0; i < _FS_LOCK; i++) {
+		if (Files[i].fs == fs) Files[i].fs = 0;
+	}
+}
+
+#endif	/* _FS_LOCK != 0 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Move/Flush disk access window in the file system object               */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT sync_window (	/* Returns FR_OK or FR_DISK_ERROR */
+	FATFS* fs			/* File system object */
+)
+{
+	DWORD wsect;
+	UINT nf;
+	FRESULT res = FR_OK;
+
+
+	if (fs->wflag) {	/* Write back the sector if it is dirty */
+		wsect = fs->winsect;	/* Current sector number */
+		if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) {
+			res = FR_DISK_ERR;
+		} else {
+			fs->wflag = 0;
+			if (wsect - fs->fatbase < fs->fsize) {		/* Is it in the FAT area? */
+				for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
+					wsect += fs->fsize;
+					disk_write(fs->drv, fs->win, wsect, 1);
+				}
+			}
+		}
+	}
+	return res;
+}
+#endif
+
+
+static
+FRESULT move_window (	/* Returns FR_OK or FR_DISK_ERROR */
+	FATFS* fs,			/* File system object */
+	DWORD sector		/* Sector number to make appearance in the fs->win[] */
+)
+{
+	FRESULT res = FR_OK;
+
+
+	if (sector != fs->winsect) {	/* Window offset changed? */
+#if !_FS_READONLY
+		res = sync_window(fs);		/* Write-back changes */
+#endif
+		if (res == FR_OK) {			/* Fill sector window with new data */
+			if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) {
+				sector = 0xFFFFFFFF;	/* Invalidate window if data is not reliable */
+				res = FR_DISK_ERR;
+			}
+			fs->winsect = sector;
+		}
+	}
+	return res;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Synchronize file system and strage device                             */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT sync_fs (	/* FR_OK:succeeded, !=0:error */
+	FATFS* fs		/* File system object */
+)
+{
+	FRESULT res;
+
+
+	res = sync_window(fs);
+	if (res == FR_OK) {
+		/* Update FSInfo sector if needed */
+		if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) {
+			/* Create FSInfo structure */
+			mem_set(fs->win, 0, SS(fs));
+			st_word(fs->win + BS_55AA, 0xAA55);
+			st_dword(fs->win + FSI_LeadSig, 0x41615252);
+			st_dword(fs->win + FSI_StrucSig, 0x61417272);
+			st_dword(fs->win + FSI_Free_Count, fs->free_clst);
+			st_dword(fs->win + FSI_Nxt_Free, fs->last_clst);
+			/* Write it into the FSInfo sector */
+			fs->winsect = fs->volbase + 1;
+			disk_write(fs->drv, fs->win, fs->winsect, 1);
+			fs->fsi_flag = 0;
+		}
+		/* Make sure that no pending write process in the physical drive */
+		if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR;
+	}
+
+	return res;
+}
+
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0:Sector number, 0:Failed (invalid cluster#) */
+	FATFS* fs,		/* File system object */
+	DWORD clst		/* Cluster# to be converted */
+)
+{
+	clst -= 2;
+	if (clst >= fs->n_fatent - 2) return 0;		/* Invalid cluster# */
+	return clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD get_fat (	/* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */
+	_FDID* obj,	/* Corresponding object */
+	DWORD clst	/* Cluster number to get the value */
+)
+{
+	UINT wc, bc;
+	DWORD val;
+	FATFS *fs = obj->fs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent) {	/* Check if in valid range */
+		val = 1;	/* Internal error */
+
+	} else {
+		val = 0xFFFFFFFF;	/* Default value falls on disk error */
+
+		switch (fs->fs_type) {
+		case FS_FAT12 :
+			bc = (UINT)clst; bc += bc / 2;
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc = fs->win[bc++ % SS(fs)];
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc |= fs->win[bc % SS(fs)] << 8;
+			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+			break;
+
+		case FS_FAT16 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
+			val = ld_word(fs->win + clst * 2 % SS(fs));
+			break;
+
+		case FS_FAT32 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+			break;
+#if _FS_EXFAT
+		case FS_EXFAT :
+			if (obj->objsize) {
+				DWORD cofs = clst - obj->sclust;	/* Offset from start cluster */
+				DWORD clen = (DWORD)((obj->objsize - 1) / SS(fs)) / fs->csize;	/* Number of clusters - 1 */
+
+				if (obj->stat == 2) {	/* Is there no valid chain on the FAT? */
+					if (cofs <= clen) {
+						val = (cofs == clen) ? 0x7FFFFFFF : clst + 1;	/* Generate the value */
+						break;
+					}
+				}
+				if (obj->stat == 3 && cofs < obj->n_cont) {	/* Is it in the 1st fragment? */
+					val = clst + 1; 	/* Generate the value */
+					break;
+				}
+				if (obj->stat != 2) {	/* Get value from FAT if FAT chain is valid */
+					if (obj->n_frag != 0) {	/* Is it on the growing edge? */
+						val = 0x7FFFFFFF;	/* Generate EOC */
+					} else {
+						if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+						val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF;
+					}
+					break;
+				}
+			}
+			/* go to default */
+#endif
+		default:
+			val = 1;	/* Internal error */
+		}
+	}
+
+	return val;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of a FAT entry                              */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT put_fat (	/* FR_OK(0):succeeded, !=0:error */
+	FATFS* fs,		/* Corresponding file system object */
+	DWORD clst,		/* FAT index number (cluster number) to be changed */
+	DWORD val		/* New value to be set to the entry */
+)
+{
+	UINT bc;
+	BYTE *p;
+	FRESULT res = FR_INT_ERR;
+
+	if (clst >= 2 && clst < fs->n_fatent) {	/* Check if in valid range */
+		switch (fs->fs_type) {
+		case FS_FAT12 :	/* Bitfield items */
+			bc = (UINT)clst; bc += bc / 2;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = fs->win + bc++ % SS(fs);
+			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+			fs->wflag = 1;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = fs->win + bc % SS(fs);
+			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT16 :	/* WORD aligned items */
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+			if (res != FR_OK) break;
+			st_word(fs->win + clst * 2 % SS(fs), (WORD)val);
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT32 :	/* DWORD aligned items */
+#if _FS_EXFAT
+		case FS_EXFAT :
+#endif
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+			if (res != FR_OK) break;
+			if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+				val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000);
+			}
+			st_dword(fs->win + clst * 4 % SS(fs), val);
+			fs->wflag = 1;
+			break;
+		}
+	}
+	return res;
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+#if _FS_EXFAT && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* exFAT: Accessing FAT and Allocation Bitmap                            */
+/*-----------------------------------------------------------------------*/
+
+/*--------------------------------------*/
+/* Find a contiguous free cluster block */
+/*--------------------------------------*/
+
+static
+DWORD find_bitmap (	/* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */
+	FATFS* fs,	/* File system object */
+	DWORD clst,	/* Cluster number to scan from */
+	DWORD ncl	/* Number of contiguous clusters to find (1..) */
+)
+{
+	BYTE bm, bv;
+	UINT i;
+	DWORD val, scl, ctr;
+
+
+	clst -= 2;	/* The first bit in the bitmap corresponds to cluster #2 */
+	if (clst >= fs->n_fatent - 2) clst = 0;
+	scl = val = clst; ctr = 0;
+	for (;;) {
+		if (move_window(fs, fs->database + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF;	/* (assuming bitmap is located top of the cluster heap) */
+		i = val / 8 % SS(fs); bm = 1 << (val % 8);
+		do {
+			do {
+				bv = fs->win[i] & bm; bm <<= 1;		/* Get bit value */
+				if (++val >= fs->n_fatent - 2) {	/* Next cluster (with wrap-around) */
+					val = 0; bm = 0; i = SS(fs);
+				}
+				if (!bv) {	/* Is it a free cluster? */
+					if (++ctr == ncl) return scl + 2;	/* Check if run length is sufficient for required */
+				} else {
+					scl = val; ctr = 0;		/* Encountered a cluster in-use, restart to scan */
+				}
+				if (val == clst) return 0;	/* All cluster scanned? */
+			} while (bm);
+			bm = 1;
+		} while (++i < SS(fs));
+	}
+}
+
+
+/*----------------------------------------*/
+/* Set/Clear a block of allocation bitmap */
+/*----------------------------------------*/
+
+static
+FRESULT change_bitmap (
+	FATFS* fs,	/* File system object */
+	DWORD clst,	/* Cluster number to change from */
+	DWORD ncl,	/* Number of clusters to be changed */
+	int bv		/* bit value to be set (0 or 1) */
+)
+{
+	BYTE bm;
+	UINT i;
+	DWORD sect;
+
+	clst -= 2;	/* The first bit corresponds to cluster #2 */
+	sect = fs->database + clst / 8 / SS(fs);	/* Sector address (assuming bitmap is located top of the cluster heap) */
+	i = clst / 8 % SS(fs);						/* Byte offset in the sector */
+	bm = 1 << (clst % 8);						/* Bit mask in the byte */
+	for (;;) {
+		if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR;
+		do {
+			do {
+				if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR;	/* Is the bit expected value? */
+				fs->win[i] ^= bm;	/* Flip the bit */
+				fs->wflag = 1;
+				if (--ncl == 0) return FR_OK;	/* All bits processed? */
+			} while (bm <<= 1);		/* Next bit */
+			bm = 1;
+		} while (++i < SS(fs));		/* Next byte */
+		i = 0;
+	}
+}
+
+
+/*---------------------------------------------*/
+/* Fill the first fragment of the FAT chain    */
+/*---------------------------------------------*/
+
+static
+FRESULT fill_first_frag (
+	_FDID* obj	/* Pointer to the corresponding object */
+)
+{
+	FRESULT res;
+	DWORD cl, n;
+
+	if (obj->stat == 3) {	/* Has the object been changed 'fragmented'? */
+		for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) {	/* Create cluster chain on the FAT */
+			res = put_fat(obj->fs, cl, cl + 1);
+			if (res != FR_OK) return res;
+		}
+		obj->stat = 0;	/* Change status 'FAT chain is valid' */
+	}
+	return FR_OK;
+}
+
+
+/*---------------------------------------------*/
+/* Fill the last fragment of the FAT chain     */
+/*---------------------------------------------*/
+
+static
+FRESULT fill_last_frag (
+	_FDID* obj,	/* Pointer to the corresponding object */
+	DWORD lcl,	/* Last cluster of the fragment */
+	DWORD term	/* Value to set the last FAT entry */
+)
+{
+	FRESULT res;
+
+	while (obj->n_frag > 0) {	/* Create the last chain on the FAT */
+		res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term);
+		if (res != FR_OK) return res;
+		obj->n_frag--;
+	}
+	return FR_OK;
+}
+
+#endif	/* _FS_EXFAT && !_FS_READONLY */
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain                                 */
+/*-----------------------------------------------------------------------*/
+static
+FRESULT remove_chain (	/* FR_OK(0):succeeded, !=0:error */
+	_FDID* obj,			/* Corresponding object */
+	DWORD clst,			/* Cluster to remove a chain from */
+	DWORD pclst			/* Previous cluster of clst (0:an entire chain) */
+)
+{
+	FRESULT res = FR_OK;
+	DWORD nxt;
+	FATFS *fs = obj->fs;
+#if _FS_EXFAT || _USE_TRIM
+	DWORD scl = clst, ecl = clst;
+#endif
+#if _USE_TRIM
+	DWORD rt[2];
+#endif
+
+	if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Check if in valid range */
+
+	/* Mark the previous cluster 'EOC' on the FAT if it exists */
+	if (pclst && (!_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) {
+		res = put_fat(fs, pclst, 0xFFFFFFFF);
+		if (res != FR_OK) return res;
+	}
+
+	/* Remove the chain */
+	do {
+		nxt = get_fat(obj, clst);			/* Get cluster status */
+		if (nxt == 0) break;				/* Empty cluster? */
+		if (nxt == 1) return FR_INT_ERR;	/* Internal error? */
+		if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error? */
+		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+			res = put_fat(fs, clst, 0);		/* Mark the cluster 'free' on the FAT */
+			if (res != FR_OK) return res;
+		}
+		if (fs->free_clst < fs->n_fatent - 2) {	/* Update FSINFO */
+			fs->free_clst++;
+			fs->fsi_flag |= 1;
+		}
+#if _FS_EXFAT || _USE_TRIM
+		if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
+			ecl = nxt;
+		} else {				/* End of contiguous cluster block */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				res = change_bitmap(fs, scl, ecl - scl + 1, 0);	/* Mark the cluster block 'free' on the bitmap */
+				if (res != FR_OK) return res;
+			}
+#endif
+#if _USE_TRIM
+			rt[0] = clust2sect(fs, scl);					/* Start sector */
+			rt[1] = clust2sect(fs, ecl) + fs->csize - 1;	/* End sector */
+			disk_ioctl(fs->drv, CTRL_TRIM, rt);				/* Inform device the block can be erased */
+#endif
+			scl = ecl = nxt;
+		}
+#endif
+		clst = nxt;					/* Next cluster */
+	} while (clst < fs->n_fatent);	/* Repeat while not the last link */
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {
+		if (pclst == 0) {	/* Does the object have no chain? */
+			obj->stat = 0;		/* Change the object status 'initial' */
+		} else {
+			if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) {	/* Did the chain get contiguous? */
+				obj->stat = 2;	/* Change the object status 'contiguous' */
+			}
+		}
+	}
+#endif
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch a chain or Create a new chain                  */
+/*-----------------------------------------------------------------------*/
+static
+DWORD create_chain (	/* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+	_FDID* obj,			/* Corresponding object */
+	DWORD clst			/* Cluster# to stretch, 0:Create a new chain */
+)
+{
+	DWORD cs, ncl, scl;
+	FRESULT res;
+	FATFS *fs = obj->fs;
+
+
+	if (clst == 0) {	/* Create a new chain */
+		scl = fs->last_clst;				/* Get suggested cluster to start from */
+		if (scl == 0 || scl >= fs->n_fatent) scl = 1;
+	}
+	else {				/* Stretch current chain */
+		cs = get_fat(obj, clst);			/* Check the cluster status */
+		if (cs < 2) return 1;				/* Invalid FAT value */
+		if (cs == 0xFFFFFFFF) return cs;	/* A disk error occurred */
+		if (cs < fs->n_fatent) return cs;	/* It is already followed by next cluster */
+		scl = clst;
+	}
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		ncl = find_bitmap(fs, scl, 1);				/* Find a free cluster */
+		if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl;	/* No free cluster or hard error? */
+		res = change_bitmap(fs, ncl, 1, 1);			/* Mark the cluster 'in use' */
+		if (res == FR_INT_ERR) return 1;
+		if (res == FR_DISK_ERR) return 0xFFFFFFFF;
+		if (clst == 0) {							/* Is it a new chain? */
+			obj->stat = 2;							/* Set status 'contiguous' */
+		} else {									/* It is a stretched chain */
+			if (obj->stat == 2 && ncl != scl + 1) {	/* Is the chain got fragmented? */
+				obj->n_cont = scl - obj->sclust;	/* Set size of the contiguous part */
+				obj->stat = 3;						/* Change status 'just fragmented' */
+			}
+		}
+		if (obj->stat != 2) {	/* Is the file non-contiguous? */
+			if (ncl == clst + 1) {	/* Is the cluster next to previous one? */
+				obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2;	/* Increment size of last framgent */
+			} else {				/* New fragment */
+				if (obj->n_frag == 0) obj->n_frag = 1;
+				res = fill_last_frag(obj, clst, ncl);	/* Fill last fragment on the FAT and link it to new one */
+				if (res == FR_OK) obj->n_frag = 1;
+			}
+		}
+	} else
+#endif
+	{	/* On the FAT12/16/32 volume */
+		ncl = scl;	/* Start cluster */
+		for (;;) {
+			ncl++;							/* Next cluster */
+			if (ncl >= fs->n_fatent) {		/* Check wrap-around */
+				ncl = 2;
+				if (ncl > scl) return 0;	/* No free cluster */
+			}
+			cs = get_fat(obj, ncl);			/* Get the cluster status */
+			if (cs == 0) break;				/* Found a free cluster */
+			if (cs == 1 || cs == 0xFFFFFFFF) return cs;	/* An error occurred */
+			if (ncl == scl) return 0;		/* No free cluster */
+		}
+		res = put_fat(fs, ncl, 0xFFFFFFFF);	/* Mark the new cluster 'EOC' */
+		if (res == FR_OK && clst != 0) {
+			res = put_fat(fs, clst, ncl);	/* Link it from the previous one if needed */
+		}
+	}
+
+	if (res == FR_OK) {			/* Update FSINFO if function succeeded. */
+		fs->last_clst = ncl;
+		if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--;
+		fs->fsi_flag |= 1;
+	} else {
+		ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;	/* Failed. Generate error status */
+	}
+
+	return ncl;		/* Return new cluster number or error status */
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+#if _USE_FASTSEEK
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table        */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clmt_clust (	/* <2:Error, >=2:Cluster number */
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t ofs		/* File offset to be converted to cluster# */
+)
+{
+	DWORD cl, ncl, *tbl;
+	FATFS *fs = fp->obj.fs;
+
+
+	tbl = fp->cltbl + 1;	/* Top of CLMT */
+	cl = (DWORD)(ofs / SS(fs) / fs->csize);	/* Cluster order from top of the file */
+	for (;;) {
+		ncl = *tbl++;			/* Number of cluters in the fragment */
+		if (ncl == 0) return 0;	/* End of table? (error) */
+		if (cl < ncl) break;	/* In this fragment? */
+		cl -= ncl; tbl++;		/* Next fragment */
+	}
+	return cl + *tbl;	/* Return the cluster number */
+}
+
+#endif	/* _USE_FASTSEEK */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index                              */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_sdi (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,		/* Pointer to directory object */
+	DWORD ofs		/* Offset of directory table */
+)
+{
+	DWORD csz, clst;
+	FATFS *fs = dp->obj.fs;
+
+
+	if (ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) {	/* Check range of offset and alignment */
+		return FR_INT_ERR;
+	}
+	dp->dptr = ofs;				/* Set current offset */
+	clst = dp->obj.sclust;		/* Table start cluster (0:root) */
+	if (clst == 0 && fs->fs_type >= FS_FAT32) {	/* Replace cluster# 0 with root cluster# */
+		clst = fs->dirbase;
+		if (_FS_EXFAT) dp->obj.stat = 0;	/* exFAT: Root dir has an FAT chain */
+	}
+
+	if (clst == 0) {	/* Static table (root-directory in FAT12/16) */
+		if (ofs / SZDIRE >= fs->n_rootdir)	return FR_INT_ERR;	/* Is index out of range? */
+		dp->sect = fs->dirbase;
+
+	} else {			/* Dynamic table (sub-directory or root-directory in FAT32+) */
+		csz = (DWORD)fs->csize * SS(fs);	/* Bytes per cluster */
+		while (ofs >= csz) {				/* Follow cluster chain */
+			clst = get_fat(&dp->obj, clst);				/* Get next cluster */
+			if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+			if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Reached to end of table or internal error */
+			ofs -= csz;
+		}
+		dp->sect = clust2sect(fs, clst);
+	}
+	dp->clust = clst;					/* Current cluster# */
+	if (!dp->sect) return FR_INT_ERR;
+	dp->sect += ofs / SS(fs);			/* Sector# of the directory entry */
+	dp->dir = fs->win + (ofs % SS(fs));	/* Pointer to the entry in the win[] */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory table index next                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
+	DIR* dp,		/* Pointer to the directory object */
+	int stretch		/* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+	DWORD ofs, clst;
+	FATFS *fs = dp->obj.fs;
+#if !_FS_READONLY
+	UINT n;
+#endif
+
+	ofs = dp->dptr + SZDIRE;	/* Next entry */
+	if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) return FR_NO_FILE;	/* Report EOT when offset has reached max value */
+
+	if (ofs % SS(fs) == 0) {	/* Sector changed? */
+		dp->sect++;				/* Next sector */
+
+		if (!dp->clust) {		/* Static table */
+			if (ofs / SZDIRE >= fs->n_rootdir) {	/* Report EOT if it reached end of static table */
+				dp->sect = 0; return FR_NO_FILE;
+			}
+		}
+		else {					/* Dynamic table */
+			if ((ofs / SS(fs) & (fs->csize - 1)) == 0) {		/* Cluster changed? */
+				clst = get_fat(&dp->obj, dp->clust);			/* Get next cluster */
+				if (clst <= 1) return FR_INT_ERR;				/* Internal error */
+				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;		/* Disk error */
+				if (clst >= fs->n_fatent) {						/* Reached end of dynamic table */
+#if !_FS_READONLY
+					if (!stretch) {								/* If no stretch, report EOT */
+						dp->sect = 0; return FR_NO_FILE;
+					}
+					clst = create_chain(&dp->obj, dp->clust);	/* Allocate a cluster */
+					if (clst == 0) return FR_DENIED;			/* No free cluster */
+					if (clst == 1) return FR_INT_ERR;			/* Internal error */
+					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+					/* Clean-up the stretched table */
+					if (_FS_EXFAT) dp->obj.stat |= 4;			/* The directory needs to be updated */
+					if (sync_window(fs) != FR_OK) return FR_DISK_ERR;	/* Flush disk access window */
+					mem_set(fs->win, 0, SS(fs));				/* Clear window buffer */
+					for (n = 0, fs->winsect = clust2sect(fs, clst); n < fs->csize; n++, fs->winsect++) {	/* Fill the new cluster with 0 */
+						fs->wflag = 1;
+						if (sync_window(fs) != FR_OK) return FR_DISK_ERR;
+					}
+					fs->winsect -= n;							/* Restore window offset */
+#else
+					if (!stretch) dp->sect = 0;					/* (this line is to suppress compiler warning) */
+					dp->sect = 0; return FR_NO_FILE;			/* Report EOT */
+#endif
+				}
+				dp->clust = clst;		/* Initialize data for new cluster */
+				dp->sect = clust2sect(fs, clst);
+			}
+		}
+	}
+	dp->dptr = ofs;						/* Current entry */
+	dp->dir = fs->win + ofs % SS(fs);	/* Pointer to the entry in the win[] */
+
+	return FR_OK;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Reserve a block of directory entries             */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_alloc (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,		/* Pointer to the directory object */
+	UINT nent		/* Number of contiguous entries to allocate */
+)
+{
+	FRESULT res;
+	UINT n;
+	FATFS *fs = dp->obj.fs;
+
+
+	res = dir_sdi(dp, 0);
+	if (res == FR_OK) {
+		n = 0;
+		do {
+			res = move_window(fs, dp->sect);
+			if (res != FR_OK) break;
+#if _FS_EXFAT
+			if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) {
+#else
+			if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) {
+#endif
+				if (++n == nent) break;	/* A block of contiguous free entries is found */
+			} else {
+				n = 0;					/* Not a blank entry. Restart to search */
+			}
+			res = dir_next(dp, 1);
+		} while (res == FR_OK);	/* Next entry with table stretch enabled */
+	}
+
+	if (res == FR_NO_FILE) res = FR_DENIED;	/* No directory entry to allocate */
+	return res;
+}
+
+#endif	/* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT: Directory handling - Load/Store start cluster number             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD ld_clust (	/* Returns the top cluster value of the SFN entry */
+	FATFS* fs,		/* Pointer to the fs object */
+	const BYTE* dir	/* Pointer to the key entry */
+)
+{
+	DWORD cl;
+
+	cl = ld_word(dir + DIR_FstClusLO);
+	if (fs->fs_type == FS_FAT32) {
+		cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
+	}
+
+	return cl;
+}
+
+
+#if !_FS_READONLY
+static
+void st_clust (
+	FATFS* fs,	/* Pointer to the fs object */
+	BYTE* dir,	/* Pointer to the key entry */
+	DWORD cl	/* Value to be set */
+)
+{
+	st_word(dir + DIR_FstClusLO, (WORD)cl);
+	if (fs->fs_type == FS_FAT32) {
+		st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16));
+	}
+}
+#endif
+
+
+
+#if _USE_LFN != 0
+/*------------------------------------------------------------------------*/
+/* FAT-LFN: LFN handling                                                  */
+/*------------------------------------------------------------------------*/
+static
+const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30};	/* Offset of LFN characters in the directory entry */
+
+
+/*--------------------------------------------------------*/
+/* FAT-LFN: Compare a part of file name with an LFN entry */
+/*--------------------------------------------------------*/
+static
+int cmp_lfn (				/* 1:matched, 0:not matched */
+	const WCHAR* lfnbuf,	/* Pointer to the LFN working buffer to be compared */
+	BYTE* dir				/* Pointer to the directory entry containing the part of LFN */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO */
+
+	i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc) {
+			if (i >= _MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) {	/* Compare it */
+				return 0;					/* Not matched */
+			}
+			wc = uc;
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0;	/* Last segment matched but different length */
+
+	return 1;		/* The part of LFN matched */
+}
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT
+/*-----------------------------------------------------*/
+/* FAT-LFN: Pick a part of file name from an LFN entry */
+/*-----------------------------------------------------*/
+static
+int pick_lfn (			/* 1:succeeded, 0:buffer overflow or invalid LFN entry */
+	WCHAR* lfnbuf,		/* Pointer to the LFN working buffer */
+	BYTE* dir			/* Pointer to the LFN entry */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO is 0 */
+
+	i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc) {
+			if (i >= _MAX_LFN) return 0;	/* Buffer overflow? */
+			lfnbuf[i++] = wc = uc;			/* Store it */
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if (dir[LDIR_Ord] & LLEF) {				/* Put terminator if it is the last LFN part */
+		if (i >= _MAX_LFN) return 0;		/* Buffer overflow? */
+		lfnbuf[i] = 0;
+	}
+
+	return 1;		/* The part of LFN is valid */
+}
+#endif
+
+
+#if !_FS_READONLY
+/*-----------------------------------------*/
+/* FAT-LFN: Create an entry of LFN entries */
+/*-----------------------------------------*/
+static
+void put_lfn (
+	const WCHAR* lfn,	/* Pointer to the LFN */
+	BYTE* dir,			/* Pointer to the LFN entry to be created */
+	BYTE ord,			/* LFN order (1-20) */
+	BYTE sum			/* Checksum of the corresponding SFN */
+)
+{
+	UINT i, s;
+	WCHAR wc;
+
+
+	dir[LDIR_Chksum] = sum;			/* Set checksum */
+	dir[LDIR_Attr] = AM_LFN;		/* Set attribute. LFN entry */
+	dir[LDIR_Type] = 0;
+	st_word(dir + LDIR_FstClusLO, 0);
+
+	i = (ord - 1) * 13;				/* Get offset in the LFN working buffer */
+	s = wc = 0;
+	do {
+		if (wc != 0xFFFF) wc = lfn[i++];	/* Get an effective character */
+		st_word(dir + LfnOfs[s], wc);		/* Put it */
+		if (wc == 0) wc = 0xFFFF;		/* Padding characters for left locations */
+	} while (++s < 13);
+	if (wc == 0xFFFF || !lfn[i]) ord |= LLEF;	/* Last LFN part is the start of LFN sequence */
+	dir[LDIR_Ord] = ord;			/* Set the LFN order */
+}
+
+#endif	/* !_FS_READONLY */
+#endif	/* _USE_LFN != 0 */
+
+
+
+#if _USE_LFN != 0 && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Create a Numbered SFN                                        */
+/*-----------------------------------------------------------------------*/
+
+static
+void gen_numname (
+	BYTE* dst,			/* Pointer to the buffer to store numbered SFN */
+	const BYTE* src,	/* Pointer to SFN */
+	const WCHAR* lfn,	/* Pointer to LFN */
+	UINT seq			/* Sequence number */
+)
+{
+	BYTE ns[8], c;
+	UINT i, j;
+	WCHAR wc;
+	DWORD sr;
+
+
+	mem_cpy(dst, src, 11);
+
+	if (seq > 5) {	/* In case of many collisions, generate a hash number instead of sequential number */
+		sr = seq;
+		while (*lfn) {	/* Create a CRC */
+			wc = *lfn++;
+			for (i = 0; i < 16; i++) {
+				sr = (sr << 1) + (wc & 1);
+				wc >>= 1;
+				if (sr & 0x10000) sr ^= 0x11021;
+			}
+		}
+		seq = (UINT)sr;
+	}
+
+	/* itoa (hexdecimal) */
+	i = 7;
+	do {
+		c = (BYTE)((seq % 16) + '0');
+		if (c > '9') c += 7;
+		ns[i--] = c;
+		seq /= 16;
+	} while (seq);
+	ns[i] = '~';
+
+	/* Append the number */
+	for (j = 0; j < i && dst[j] != ' '; j++) {
+		if (IsDBCS1(dst[j])) {
+			if (j == i - 1) break;
+			j++;
+		}
+	}
+	do {
+		dst[j++] = (i < 8) ? ns[i++] : ' ';
+	} while (j < 8);
+}
+#endif	/* _USE_LFN != 0 && !_FS_READONLY */
+
+
+
+#if _USE_LFN != 0
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Calculate checksum of an SFN entry                           */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE sum_sfn (
+	const BYTE* dir		/* Pointer to the SFN entry */
+)
+{
+	BYTE sum = 0;
+	UINT n = 11;
+
+	do {
+		sum = (sum >> 1) + (sum << 7) + *dir++;
+	} while (--n);
+	return sum;
+}
+
+#endif	/* _USE_LFN != 0 */
+
+
+
+#if _FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* exFAT: Checksum                                                       */
+/*-----------------------------------------------------------------------*/
+
+static
+WORD xdir_sum (			/* Get checksum of the directoly block */
+	const BYTE* dir		/* Directory entry block to be calculated */
+)
+{
+	UINT i, szblk;
+	WORD sum;
+
+
+	szblk = (dir[XDIR_NumSec] + 1) * SZDIRE;
+	for (i = sum = 0; i < szblk; i++) {
+		if (i == XDIR_SetSum) {	/* Skip sum field */
+			i++;
+		} else {
+			sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i];
+		}
+	}
+	return sum;
+}
+
+
+
+static
+WORD xname_sum (		/* Get check sum (to be used as hash) of the name */
+	const WCHAR* name	/* File name to be calculated */
+)
+{
+	WCHAR chr;
+	WORD sum = 0;
+
+
+	while ((chr = *name++) != 0) {
+		chr = ff_wtoupper(chr);		/* File name needs to be ignored case */
+		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF);
+		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8);
+	}
+	return sum;
+}
+
+
+#if !_FS_READONLY && _USE_MKFS
+static
+DWORD xsum32 (
+	BYTE  dat,	/* Data to be sumed */
+	DWORD sum	/* Previous value */
+)
+{
+	sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat;
+	return sum;
+}
+#endif
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
+/*------------------------------------------------------*/
+/* exFAT: Get object information from a directory block */
+/*------------------------------------------------------*/
+
+static
+void get_xdir_info (
+	BYTE* dirb,			/* Pointer to the direcotry entry block 85+C0+C1s */
+	FILINFO* fno		/* Buffer to store the extracted file information */
+)
+{
+	UINT di, si;
+	WCHAR w;
+#if !_LFN_UNICODE
+	UINT nc;
+#endif
+
+	/* Get file name */
+	di = 0;
+#if _LFN_UNICODE
+	for (si = SZDIRE * 2; di < dirb[XDIR_NumName]; si += 2, di++) {
+		if ((si % SZDIRE) == 0) si += 2;		/* Skip entry type field */
+		w = ld_word(dirb + si);					/* Get a character */
+		if (di >= _MAX_LFN) { di = 0; break; }	/* Buffer overflow --> inaccessible object name */
+		fno->fname[di] = w;						/* Store it */
+	}
+#else
+	for (si = SZDIRE * 2, nc = 0; nc < dirb[XDIR_NumName]; si += 2, nc++) {
+		if ((si % SZDIRE) == 0) si += 2;		/* Skip entry type field */
+		w = ff_convert(ld_word(dirb + si), 0);	/* Get a character and Unicode -> OEM */
+		if (_DF1S && w >= 0x100) {				/* Is it a double byte char? (always false at SBCS cfg) */
+			fno->fname[di++] = (char)(w >> 8);	/* Put 1st byte of the DBC */
+		}
+		if (w == 0 || di >= _MAX_LFN) { di = 0; break; }	/* Invalid char or buffer overflow --> inaccessible object name */
+		fno->fname[di++] = (char)w;
+	}
+#endif
+	if (di == 0) fno->fname[di++] = '?';	/* Inaccessible object name? */
+	fno->fname[di] = 0;						/* Terminate file name */
+
+	fno->altname[0] = 0;							/* No SFN */
+	fno->fattrib = dirb[XDIR_Attr];					/* Attribute */
+	fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(dirb + XDIR_FileSize);	/* Size */
+	fno->ftime = ld_word(dirb + XDIR_ModTime + 0);	/* Time */
+	fno->fdate = ld_word(dirb + XDIR_ModTime + 2);	/* Date */
+}
+
+#endif	/* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */
+
+
+/*-----------------------------------*/
+/* exFAT: Get a directry entry block */
+/*-----------------------------------*/
+
+static
+FRESULT load_xdir (	/* FR_INT_ERR: invalid entry block */
+	DIR* dp			/* Pointer to the reading direcotry object pointing the 85 entry */
+)
+{
+	FRESULT res;
+	UINT i, sz_ent;
+	BYTE* dirb = dp->obj.fs->dirbuf;	/* Pointer to the on-memory direcotry entry block 85+C0+C1s */
+
+
+	/* Load 85 entry */
+	res = move_window(dp->obj.fs, dp->sect);
+	if (res != FR_OK) return res;
+	if (dp->dir[XDIR_Type] != 0x85) return FR_INT_ERR;
+	mem_cpy(dirb + 0, dp->dir, SZDIRE);
+	sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE;
+	if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR;
+
+	/* Load C0 entry */
+	res = dir_next(dp, 0);
+	if (res != FR_OK) return res;
+	res = move_window(dp->obj.fs, dp->sect);
+	if (res != FR_OK) return res;
+	if (dp->dir[XDIR_Type] != 0xC0) return FR_INT_ERR;
+	mem_cpy(dirb + SZDIRE, dp->dir, SZDIRE);
+	if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR;
+
+	/* Load C1 entries */
+	i = SZDIRE * 2;	/* C1 offset */
+	do {
+		res = dir_next(dp, 0);
+		if (res != FR_OK) return res;
+		res = move_window(dp->obj.fs, dp->sect);
+		if (res != FR_OK) return res;
+		if (dp->dir[XDIR_Type] != 0xC1) return FR_INT_ERR;
+		if (i < MAXDIRB(_MAX_LFN)) mem_cpy(dirb + i, dp->dir, SZDIRE);
+	} while ((i += SZDIRE) < sz_ent);
+
+	/* Sanity check (do it when accessible object name) */
+	if (i <= MAXDIRB(_MAX_LFN)) {
+		if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR;
+	}
+	return FR_OK;
+}
+
+
+#if !_FS_READONLY || _FS_RPATH != 0
+/*------------------------------------------------*/
+/* exFAT: Load the object's directory entry block */
+/*------------------------------------------------*/
+static
+FRESULT load_obj_dir (
+	DIR* dp,			/* Blank directory object to be used to access containing direcotry */
+	const _FDID* obj	/* Object with its containing directory information */
+)
+{
+	FRESULT res;
+
+	/* Open object containing directory */
+	dp->obj.fs = obj->fs;
+	dp->obj.sclust = obj->c_scl;
+	dp->obj.stat = (BYTE)obj->c_size;
+	dp->obj.objsize = obj->c_size & 0xFFFFFF00;
+	dp->blk_ofs = obj->c_ofs;
+
+	res = dir_sdi(dp, dp->blk_ofs);	/* Goto object's entry block */
+	if (res == FR_OK) {
+		res = load_xdir(dp);		/* Load the object's entry block */
+	}
+	return res;
+}
+#endif
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------*/
+/* exFAT: Store the directory block to the media */
+/*-----------------------------------------------*/
+static
+FRESULT store_xdir (
+	DIR* dp				/* Pointer to the direcotry object */
+)
+{
+	FRESULT res;
+	UINT nent;
+	BYTE* dirb = dp->obj.fs->dirbuf;	/* Pointer to the direcotry entry block 85+C0+C1s */
+
+	/* Create set sum */
+	st_word(dirb + XDIR_SetSum, xdir_sum(dirb));
+	nent = dirb[XDIR_NumSec] + 1;
+
+	/* Store the set of directory to the volume */
+	res = dir_sdi(dp, dp->blk_ofs);
+	while (res == FR_OK) {
+		res = move_window(dp->obj.fs, dp->sect);
+		if (res != FR_OK) break;
+		mem_cpy(dp->dir, dirb, SZDIRE);
+		dp->obj.fs->wflag = 1;
+		if (--nent == 0) break;
+		dirb += SZDIRE;
+		res = dir_next(dp, 0);
+	}
+	return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR;
+}
+
+
+
+/*-------------------------------------------*/
+/* exFAT: Create a new directory enrty block */
+/*-------------------------------------------*/
+
+static
+void create_xdir (
+	BYTE* dirb,			/* Pointer to the direcotry entry block buffer */
+	const WCHAR* lfn	/* Pointer to the nul terminated file name */
+)
+{
+	UINT i;
+	BYTE nb, nc;
+	WCHAR chr;
+
+
+	/* Create 85+C0 entry */
+	mem_set(dirb, 0, 2 * SZDIRE);
+	dirb[XDIR_Type] = 0x85;
+	dirb[XDIR_Type + SZDIRE] = 0xC0;
+
+	/* Create C1 entries */
+	nc = 0; nb = 1; chr = 1; i = SZDIRE * 2;
+	do {
+		dirb[i++] = 0xC1; dirb[i++] = 0;	/* Entry type C1 */
+		do {	/* Fill name field */
+			if (chr && (chr = lfn[nc]) != 0) nc++;	/* Get a character if exist */
+			st_word(dirb + i, chr); 		/* Store it */
+		} while ((i += 2) % SZDIRE != 0);
+		nb++;
+	} while (lfn[nc]);	/* Fill next entry if any char follows */
+
+	dirb[XDIR_NumName] = nc;	/* Set name length */
+	dirb[XDIR_NumSec] = nb;		/* Set block length */
+	st_word(dirb + XDIR_NameHash, xname_sum(lfn));	/* Set name hash */
+}
+
+#endif	/* !_FS_READONLY */
+#endif	/* _FS_EXFAT */
+
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_read (
+	DIR* dp,		/* Pointer to the directory object */
+	int vol			/* Filtered by 0:file/directory or 1:volume label */
+)
+{
+	FRESULT res = FR_NO_FILE;
+	FATFS *fs = dp->obj.fs;
+	BYTE a, c;
+#if _USE_LFN != 0
+	BYTE ord = 0xFF, sum = 0xFF;
+#endif
+
+	while (dp->sect) {
+		res = move_window(fs, dp->sect);
+		if (res != FR_OK) break;
+		c = dp->dir[DIR_Name];	/* Test for the entry type */
+		if (c == 0) {
+			res = FR_NO_FILE; break; /* Reached to end of the directory */
+		}
+#if _FS_EXFAT
+		if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+			if (_USE_LABEL && vol) {
+				if (c == 0x83) break;	/* Volume label entry? */
+			} else {
+				if (c == 0x85) {		/* Start of the file entry block? */
+					dp->blk_ofs = dp->dptr;	/* Get location of the block */
+					res = load_xdir(dp);	/* Load the entry block */
+					if (res == FR_OK) {
+						dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK;	/* Get attribute */
+					}
+					break;
+				}
+			}
+		} else
+#endif
+		{	/* On the FAT12/16/32 volume */
+			dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;	/* Get attribute */
+#if _USE_LFN != 0	/* LFN configuration */
+			if (c == DDEM || c == '.' || (int)((a & ~AM_ARC) == AM_VOL) != vol) {	/* An entry without valid data */
+				ord = 0xFF;
+			} else {
+				if (a == AM_LFN) {			/* An LFN entry is found */
+					if (c & LLEF) {			/* Is it start of an LFN sequence? */
+						sum = dp->dir[LDIR_Chksum];
+						c &= (BYTE)~LLEF; ord = c;
+						dp->blk_ofs = dp->dptr;
+					}
+					/* Check LFN validity and capture it */
+					ord = (c == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+				} else {					/* An SFN entry is found */
+					if (ord || sum != sum_sfn(dp->dir)) {	/* Is there a valid LFN? */
+						dp->blk_ofs = 0xFFFFFFFF;			/* It has no LFN. */
+					}
+					break;
+				}
+			}
+#else		/* Non LFN configuration */
+			if (c != DDEM && c != '.' && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol) {	/* Is it a valid entry? */
+				break;
+			}
+#endif
+		}
+		res = dir_next(dp, 0);		/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dp->sect = 0;		/* Terminate the read operation on error or EOT */
+	return res;
+}
+
+#endif	/* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp			/* Pointer to the directory object with the file name */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+	BYTE c;
+#if _USE_LFN != 0
+	BYTE a, ord, sum;
+#endif
+
+	res = dir_sdi(dp, 0);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		BYTE nc;
+		UINT di, ni;
+		WORD hash = xname_sum(fs->lfnbuf);		/* Hash value of the name to find */
+
+		while ((res = dir_read(dp, 0)) == FR_OK) {	/* Read an item */
+#if _MAX_LFN < 255
+			if (fs->dirbuf[XDIR_NumName] > _MAX_LFN) continue;			/* Skip comparison if inaccessible object name */
+#endif
+			if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue;	/* Skip comparison if hash mismatched */
+			for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) {	/* Compare the name */
+				if ((di % SZDIRE) == 0) di += 2;
+				if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break;
+			}
+			if (nc == 0 && !fs->lfnbuf[ni]) break;	/* Name matched? */
+		}
+		return res;
+	}
+#endif
+	/* On the FAT12/16/32 volume */
+#if _USE_LFN != 0
+	ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+#endif
+	do {
+		res = move_window(fs, dp->sect);
+		if (res != FR_OK) break;
+		c = dp->dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+#if _USE_LFN != 0	/* LFN configuration */
+		dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;
+		if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) {	/* An entry without valid data */
+			ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+		} else {
+			if (a == AM_LFN) {			/* An LFN entry is found */
+				if (!(dp->fn[NSFLAG] & NS_NOLFN)) {
+					if (c & LLEF) {		/* Is it start of LFN sequence? */
+						sum = dp->dir[LDIR_Chksum];
+						c &= (BYTE)~LLEF; ord = c;	/* LFN start order */
+						dp->blk_ofs = dp->dptr;	/* Start offset of LFN */
+					}
+					/* Check validity of the LFN entry and compare it with given name */
+					ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+				}
+			} else {					/* An SFN entry is found */
+				if (!ord && sum == sum_sfn(dp->dir)) break;	/* LFN matched? */
+				if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* SFN matched? */
+				ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+			}
+		}
+#else		/* Non LFN configuration */
+		dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK;
+		if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* Is it a valid entry? */
+#endif
+		res = dir_next(dp, 0);	/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory                                   */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_register (	/* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */
+	DIR* dp				/* Target directory with object name to be created */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+#if _USE_LFN != 0	/* LFN configuration */
+	UINT n, nlen, nent;
+	BYTE sn[12], sum;
+
+
+	if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME;	/* Check name validity */
+	for (nlen = 0; fs->lfnbuf[nlen]; nlen++) ;	/* Get lfn length */
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		DIR dj;
+
+		nent = (nlen + 14) / 15 + 2;	/* Number of entries to allocate (85+C0+C1s) */
+		res = dir_alloc(dp, nent);		/* Allocate entries */
+		if (res != FR_OK) return res;
+		dp->blk_ofs = dp->dptr - SZDIRE * (nent - 1);	/* Set the allocated entry block offset */
+
+		if (dp->obj.sclust != 0 && (dp->obj.stat & 4)) {	/* Has the sub-directory been stretched? */
+			dp->obj.objsize += (DWORD)fs->csize * SS(fs);	/* Increase the directory size by cluster size */
+			res = fill_first_frag(&dp->obj);				/* Fill first fragment on the FAT if needed */
+			if (res != FR_OK) return res;
+			res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+			if (res != FR_OK) return res;
+			res = load_obj_dir(&dj, &dp->obj);				/* Load the object status */
+			if (res != FR_OK) return res;
+			st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize);		/* Update the allocation status */
+			st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize);
+			fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1;
+			res = store_xdir(&dj);							/* Store the object status */
+			if (res != FR_OK) return res;
+		}
+
+		create_xdir(fs->dirbuf, fs->lfnbuf);	/* Create on-memory directory block to be written later */
+		return FR_OK;
+	}
+#endif
+	/* On the FAT12/16/32 volume */
+	mem_cpy(sn, dp->fn, 12);
+	if (sn[NSFLAG] & NS_LOSS) {			/* When LFN is out of 8.3 format, generate a numbered name */
+		dp->fn[NSFLAG] = NS_NOLFN;		/* Find only SFN */
+		for (n = 1; n < 100; n++) {
+			gen_numname(dp->fn, sn, fs->lfnbuf, n);	/* Generate a numbered name */
+			res = dir_find(dp);				/* Check if the name collides with existing SFN */
+			if (res != FR_OK) break;
+		}
+		if (n == 100) return FR_DENIED;		/* Abort if too many collisions */
+		if (res != FR_NO_FILE) return res;	/* Abort if the result is other than 'not collided' */
+		dp->fn[NSFLAG] = sn[NSFLAG];
+	}
+
+	/* Create an SFN with/without LFNs. */
+	nent = (sn[NSFLAG] & NS_LFN) ? (nlen + 12) / 13 + 1 : 1;	/* Number of entries to allocate */
+	res = dir_alloc(dp, nent);		/* Allocate entries */
+	if (res == FR_OK && --nent) {	/* Set LFN entry if needed */
+		res = dir_sdi(dp, dp->dptr - nent * SZDIRE);
+		if (res == FR_OK) {
+			sum = sum_sfn(dp->fn);	/* Checksum value of the SFN tied to the LFN */
+			do {					/* Store LFN entries in bottom first */
+				res = move_window(fs, dp->sect);
+				if (res != FR_OK) break;
+				put_lfn(fs->lfnbuf, dp->dir, (BYTE)nent, sum);
+				fs->wflag = 1;
+				res = dir_next(dp, 0);	/* Next entry */
+			} while (res == FR_OK && --nent);
+		}
+	}
+
+#else	/* Non LFN configuration */
+	res = dir_alloc(dp, 1);		/* Allocate an entry for SFN */
+
+#endif
+
+	/* Set SFN entry */
+	if (res == FR_OK) {
+		res = move_window(fs, dp->sect);
+		if (res == FR_OK) {
+			mem_set(dp->dir, 0, SZDIRE);	/* Clean the entry */
+			mem_cpy(dp->dir + DIR_Name, dp->fn, 11);	/* Put SFN */
+#if _USE_LFN != 0
+			dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT);	/* Put NT flag */
+#endif
+			fs->wflag = 1;
+		}
+	}
+
+	return res;
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+#if !_FS_READONLY && _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory                                   */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_remove (	/* FR_OK:Succeeded, FR_DISK_ERR:A disk error */
+	DIR* dp				/* Directory object pointing the entry to be removed */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+#if _USE_LFN != 0	/* LFN configuration */
+	DWORD last = dp->dptr;
+
+	res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs);	/* Goto top of the entry block if LFN is exist */
+	if (res == FR_OK) {
+		do {
+			res = move_window(fs, dp->sect);
+			if (res != FR_OK) break;
+			/* Mark an entry 'deleted' */
+			if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+				dp->dir[XDIR_Type] &= 0x7F;
+			} else {									/* On the FAT12/16/32 volume */
+				dp->dir[DIR_Name] = DDEM;
+			}
+			fs->wflag = 1;
+			if (dp->dptr >= last) break;	/* If reached last entry then all entries of the object has been deleted. */
+			res = dir_next(dp, 0);	/* Next entry */
+		} while (res == FR_OK);
+		if (res == FR_NO_FILE) res = FR_INT_ERR;
+	}
+#else			/* Non LFN configuration */
+
+	res = move_window(fs, dp->sect);
+	if (res == FR_OK) {
+		dp->dir[DIR_Name] = DDEM;
+		fs->wflag = 1;
+	}
+#endif
+
+	return res;
+}
+
+#endif /* !_FS_READONLY && _FS_MINIMIZE == 0 */
+
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+
+static
+void get_fileinfo (		/* No return code */
+	DIR* dp,			/* Pointer to the directory object */
+	FILINFO* fno	 	/* Pointer to the file information to be filled */
+)
+{
+	UINT i, j;
+	TCHAR c;
+	DWORD tm;
+#if _USE_LFN != 0
+	WCHAR w, lfv;
+	FATFS *fs = dp->obj.fs;
+#endif
+
+
+	fno->fname[0] = 0;		/* Invaidate file info */
+	if (!dp->sect) return;	/* Exit if read pointer has reached end of directory */
+
+#if _USE_LFN != 0	/* LFN configuration */
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		get_xdir_info(fs->dirbuf, fno);
+		return;
+	} else
+#endif
+	{	/* On the FAT12/16/32 volume */
+		if (dp->blk_ofs != 0xFFFFFFFF) {	/* Get LFN if available */
+			i = j = 0;
+			while ((w = fs->lfnbuf[j++]) != 0) {	/* Get an LFN character */
+#if !_LFN_UNICODE
+				w = ff_convert(w, 0);		/* Unicode -> OEM */
+				if (w == 0) { i = 0; break; }	/* No LFN if it could not be converted */
+				if (_DF1S && w >= 0x100) {	/* Put 1st byte if it is a DBC (always false at SBCS cfg) */
+					fno->fname[i++] = (char)(w >> 8);
+				}
+#endif
+				if (i >= _MAX_LFN) { i = 0; break; }	/* No LFN if buffer overflow */
+				fno->fname[i++] = (TCHAR)w;
+			}
+			fno->fname[i] = 0;	/* Terminate the LFN */
+		}
+	}
+
+	i = j = 0;
+	lfv = fno->fname[i];	/* LFN is exist if non-zero */
+	while (i < 11) {		/* Copy name body and extension */
+		c = (TCHAR)dp->dir[i++];
+		if (c == ' ') continue;				/* Skip padding spaces */
+		if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+		if (i == 9) {						/* Insert a . if extension is exist */
+			if (!lfv) fno->fname[j] = '.';
+			fno->altname[j++] = '.';
+		}
+#if _LFN_UNICODE
+		if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dp->dir[i])) {
+			c = c << 8 | dp->dir[i++];
+		}
+		c = ff_convert(c, 1);	/* OEM -> Unicode */
+		if (!c) c = '?';
+#endif
+		fno->altname[j] = c;
+		if (!lfv) {
+			if (IsUpper(c) && (dp->dir[DIR_NTres] & ((i >= 9) ? NS_EXT : NS_BODY))) {
+				c += 0x20;			/* To lower */
+			}
+			fno->fname[j] = c;
+		}
+		j++;
+	}
+	if (!lfv) {
+		fno->fname[j] = 0;
+		if (!dp->dir[DIR_NTres]) j = 0;	/* Altname is no longer needed if neither LFN nor case info is exist. */
+	}
+	fno->altname[j] = 0;	/* Terminate the SFN */
+
+#else	/* Non-LFN configuration */
+	i = j = 0;
+	while (i < 11) {		/* Copy name body and extension */
+		c = (TCHAR)dp->dir[i++];
+		if (c == ' ') continue;				/* Skip padding spaces */
+		if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+		if (i == 9) fno->fname[j++] = '.';	/* Insert a . if extension is exist */
+		fno->fname[j++] = c;
+	}
+	fno->fname[j] = 0;
+#endif
+
+	fno->fattrib = dp->dir[DIR_Attr];				/* Attribute */
+	fno->fsize = ld_dword(dp->dir + DIR_FileSize);	/* Size */
+	tm = ld_dword(dp->dir + DIR_ModTime);			/* Timestamp */
+	fno->ftime = (WORD)tm; fno->fdate = (WORD)(tm >> 16);
+}
+
+#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */
+
+
+
+#if _USE_FIND && _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Pattern matching                                                      */
+/*-----------------------------------------------------------------------*/
+
+static
+WCHAR get_achar (		/* Get a character and advances ptr 1 or 2 */
+	const TCHAR** ptr	/* Pointer to pointer to the SBCS/DBCS/Unicode string */
+)
+{
+#if !_LFN_UNICODE
+	WCHAR chr;
+
+	chr = (BYTE)*(*ptr)++;					/* Get a byte */
+	if (IsLower(chr)) chr -= 0x20;			/* To upper ASCII char */
+#ifdef _EXCVT
+	if (chr >= 0x80) chr = ExCvt[chr - 0x80];	/* To upper SBCS extended char */
+#else
+	if (IsDBCS1(chr) && IsDBCS2(**ptr)) {		/* Get DBC 2nd byte if needed */
+		chr = chr << 8 | (BYTE)*(*ptr)++;
+	}
+#endif
+	return chr;
+#else
+	return ff_wtoupper(*(*ptr)++);			/* Get a word and to upper */
+#endif
+}
+
+
+static
+int pattern_matching (	/* 0:not matched, 1:matched */
+	const TCHAR* pat,	/* Matching pattern */
+	const TCHAR* nam,	/* String to be tested */
+	int skip,			/* Number of pre-skip chars (number of ?s) */
+	int inf				/* Infinite search (* specified) */
+)
+{
+	const TCHAR *pp, *np;
+	WCHAR pc, nc;
+	int nm, nx;
+
+
+	while (skip--) {				/* Pre-skip name chars */
+		if (!get_achar(&nam)) return 0;	/* Branch mismatched if less name chars */
+	}
+	if (!*pat && inf) return 1;		/* (short circuit) */
+
+	do {
+		pp = pat; np = nam;			/* Top of pattern and name to match */
+		for (;;) {
+			if (*pp == '?' || *pp == '*') {	/* Wildcard? */
+				nm = nx = 0;
+				do {				/* Analyze the wildcard chars */
+					if (*pp++ == '?') nm++; else nx = 1;
+				} while (*pp == '?' || *pp == '*');
+				if (pattern_matching(pp, np, nm, nx)) return 1;	/* Test new branch (recurs upto number of wildcard blocks in the pattern) */
+				nc = *np; break;	/* Branch mismatched */
+			}
+			pc = get_achar(&pp);	/* Get a pattern char */
+			nc = get_achar(&np);	/* Get a name char */
+			if (pc != nc) break;	/* Branch mismatched? */
+			if (pc == 0) return 1;	/* Branch matched? (matched at end of both strings) */
+		}
+		get_achar(&nam);			/* nam++ */
+	} while (inf && nc);			/* Retry until end of name if infinite search is specified */
+
+	return 0;
+}
+
+#endif /* _USE_FIND && _FS_MINIMIZE <= 1 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a top segment and create the object name in directory form       */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT create_name (	/* FR_OK: successful, FR_INVALID_NAME: could not create */
+	DIR* dp,			/* Pointer to the directory object */
+	const TCHAR** path	/* Pointer to pointer to the segment in the path string */
+)
+{
+#if _USE_LFN != 0	/* LFN configuration */
+	BYTE b, cf;
+	WCHAR w, *lfn;
+	UINT i, ni, si, di;
+	const TCHAR *p;
+
+	/* Create LFN in Unicode */
+	p = *path; lfn = dp->obj.fs->lfnbuf; si = di = 0;
+	for (;;) {
+		w = p[si++];					/* Get a character */
+		if (w < ' ') break;				/* Break if end of the path name */
+		if (w == '/' || w == '\\') {	/* Break if a separator is found */
+			while (p[si] == '/' || p[si] == '\\') si++;	/* Skip duplicated separator if exist */
+			break;
+		}
+		if (di >= _MAX_LFN) return FR_INVALID_NAME;	/* Reject too long name */
+#if !_LFN_UNICODE
+		w &= 0xFF;
+		if (IsDBCS1(w)) {				/* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+			b = (BYTE)p[si++];			/* Get 2nd byte */
+			w = (w << 8) + b;			/* Create a DBC */
+			if (!IsDBCS2(b)) return FR_INVALID_NAME;	/* Reject invalid sequence */
+		}
+		w = ff_convert(w, 1);			/* Convert ANSI/OEM to Unicode */
+		if (!w) return FR_INVALID_NAME;	/* Reject invalid code */
+#endif
+		if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) return FR_INVALID_NAME;	/* Reject illegal characters for LFN */
+		lfn[di++] = w;					/* Store the Unicode character */
+	}
+	*path = &p[si];						/* Return pointer to the next segment */
+	cf = (w < ' ') ? NS_LAST : 0;		/* Set last segment flag if end of the path */
+#if _FS_RPATH != 0
+	if ((di == 1 && lfn[di - 1] == '.') ||
+		(di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) {	/* Is this segment a dot name? */
+		lfn[di] = 0;
+		for (i = 0; i < 11; i++)		/* Create dot name for SFN entry */
+			dp->fn[i] = (i < di) ? '.' : ' ';
+		dp->fn[i] = cf | NS_DOT;		/* This is a dot entry */
+		return FR_OK;
+	}
+#endif
+	while (di) {						/* Snip off trailing spaces and dots if exist */
+		w = lfn[di - 1];
+		if (w != ' ' && w != '.') break;
+		di--;
+	}
+	lfn[di] = 0;						/* LFN is created */
+	if (di == 0) return FR_INVALID_NAME;	/* Reject nul name */
+
+	/* Create SFN in directory form */
+	mem_set(dp->fn, ' ', 11);
+	for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ;	/* Strip leading spaces and dots */
+	if (si) cf |= NS_LOSS | NS_LFN;
+	while (di && lfn[di - 1] != '.') di--;	/* Find extension (di<=si: no extension) */
+
+	i = b = 0; ni = 8;
+	for (;;) {
+		w = lfn[si++];					/* Get an LFN character */
+		if (!w) break;					/* Break on end of the LFN */
+		if (w == ' ' || (w == '.' && si != di)) {	/* Remove spaces and dots */
+			cf |= NS_LOSS | NS_LFN; continue;
+		}
+
+		if (i >= ni || si == di) {		/* Extension or end of SFN */
+			if (ni == 11) {				/* Long extension */
+				cf |= NS_LOSS | NS_LFN; break;
+			}
+			if (si != di) cf |= NS_LOSS | NS_LFN;	/* Out of 8.3 format */
+			if (si > di) break;			/* No extension */
+			si = di; i = 8; ni = 11;	/* Enter extension section */
+			b <<= 2; continue;
+		}
+
+		if (w >= 0x80) {				/* Non ASCII character */
+#ifdef _EXCVT
+			w = ff_convert(w, 0);		/* Unicode -> OEM code */
+			if (w) w = ExCvt[w - 0x80];	/* Convert extended character to upper (SBCS) */
+#else
+			w = ff_convert(ff_wtoupper(w), 0);	/* Upper converted Unicode -> OEM code */
+#endif
+			cf |= NS_LFN;				/* Force create LFN entry */
+		}
+
+		if (_DF1S && w >= 0x100) {		/* Is this DBC? (always false at SBCS cfg) */
+			if (i >= ni - 1) {
+				cf |= NS_LOSS | NS_LFN; i = ni; continue;
+			}
+			dp->fn[i++] = (BYTE)(w >> 8);
+		} else {						/* SBC */
+			if (!w || chk_chr("+,;=[]", w)) {	/* Replace illegal characters for SFN */
+				w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+			} else {
+				if (IsUpper(w)) {		/* ASCII large capital */
+					b |= 2;
+				} else {
+					if (IsLower(w)) {	/* ASCII small capital */
+						b |= 1; w -= 0x20;
+					}
+				}
+			}
+		}
+		dp->fn[i++] = (BYTE)w;
+	}
+
+	if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with RDDEM */
+
+	if (ni == 8) b <<= 2;
+	if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN;	/* Create LFN entry when there are composite capitals */
+	if (!(cf & NS_LFN)) {						/* When LFN is in 8.3 format without extended character, NT flags are created */
+		if ((b & 0x03) == 0x01) cf |= NS_EXT;	/* NT flag (Extension has only small capital) */
+		if ((b & 0x0C) == 0x04) cf |= NS_BODY;	/* NT flag (Filename has only small capital) */
+	}
+
+	dp->fn[NSFLAG] = cf;	/* SFN is created */
+
+	return FR_OK;
+
+
+#else	/* _USE_LFN != 0 : Non-LFN configuration */
+	BYTE c, d, *sfn;
+	UINT ni, si, i;
+	const char *p;
+
+	/* Create file name in directory form */
+	p = *path; sfn = dp->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+#if _FS_RPATH != 0
+	if (p[si] == '.') { /* Is this a dot entry? */
+		for (;;) {
+			c = (BYTE)p[si++];
+			if (c != '.' || si >= 3) break;
+			sfn[i++] = c;
+		}
+		if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
+		*path = p + si;								/* Return pointer to the next segment */
+		sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT;	/* Set last segment flag if end of the path */
+		return FR_OK;
+	}
+#endif
+	for (;;) {
+		c = (BYTE)p[si++];
+		if (c <= ' ') break; 			/* Break if end of the path name */
+		if (c == '/' || c == '\\') {	/* Break if a separator is found */
+			while (p[si] == '/' || p[si] == '\\') si++;	/* Skip duplicated separator if exist */
+			break;
+		}
+		if (c == '.' || i >= ni) {		/* End of body or over size? */
+			if (ni == 11 || c != '.') return FR_INVALID_NAME;	/* Over size or invalid dot */
+			i = 8; ni = 11;				/* Goto extension */
+			continue;
+		}
+		if (c >= 0x80) {				/* Extended character? */
+#ifdef _EXCVT
+			c = ExCvt[c - 0x80];		/* To upper extended characters (SBCS cfg) */
+#else
+#if !_DF1S
+			return FR_INVALID_NAME;		/* Reject extended characters (ASCII only cfg) */
+#endif
+#endif
+		}
+		if (IsDBCS1(c)) {				/* Check if it is a DBC 1st byte (always false at SBCS cfg.) */
+			d = (BYTE)p[si++];			/* Get 2nd byte */
+			if (!IsDBCS2(d) || i >= ni - 1) return FR_INVALID_NAME;	/* Reject invalid DBC */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* SBC */
+			if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) return FR_INVALID_NAME;	/* Reject illegal chrs for SFN */
+			if (IsLower(c)) c -= 0x20;	/* To upper */
+			sfn[i++] = c;
+		}
+	}
+	*path = p + si;						/* Return pointer to the next segment */
+	if (i == 0) return FR_INVALID_NAME;	/* Reject nul string */
+
+	if (sfn[0] == DDEM) sfn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with RDDEM */
+	sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0;		/* Set last segment flag if end of the path */
+
+	return FR_OK;
+#endif /* _USE_LFN != 0 */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR* dp,			/* Directory object to return last directory and found object */
+	const TCHAR* path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+	BYTE ns;
+	_FDID *obj = &dp->obj;
+	FATFS *fs = obj->fs;
+
+
+#if _FS_RPATH != 0
+	if (*path != '/' && *path != '\\') {	/* Without heading separator */
+		obj->sclust = fs->cdir;				/* Start from current directory */
+	} else
+#endif
+	{										/* With heading separator */
+		while (*path == '/' || *path == '\\') path++;	/* Strip heading separator */
+		obj->sclust = 0;					/* Start from root directory */
+	}
+#if _FS_EXFAT
+	obj->n_frag = 0;	/* Invalidate last fragment counter of the object */
+#if _FS_RPATH != 0
+	if (fs->fs_type == FS_EXFAT && obj->sclust) {	/* Retrieve the sub-directory status if needed */
+		DIR dj;
+
+		obj->c_scl = fs->cdc_scl;
+		obj->c_size = fs->cdc_size;
+		obj->c_ofs = fs->cdc_ofs;
+		res = load_obj_dir(&dj, obj);
+		if (res != FR_OK) return res;
+		obj->objsize = ld_dword(fs->dirbuf + XDIR_FileSize);
+		obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+	}
+#endif
+#endif
+
+	if ((UINT)*path < ' ') {				/* Null path name is the origin directory itself */
+		dp->fn[NSFLAG] = NS_NONAME;
+		res = dir_sdi(dp, 0);
+
+	} else {								/* Follow path */
+		for (;;) {
+			res = create_name(dp, &path);	/* Get a segment name of the path */
+			if (res != FR_OK) break;
+			res = dir_find(dp);				/* Find an object with the segment name */
+			ns = dp->fn[NSFLAG];
+			if (res != FR_OK) {				/* Failed to find the object */
+				if (res == FR_NO_FILE) {	/* Object is not found */
+					if (_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, stay there */
+						if (!(ns & NS_LAST)) continue;	/* Continue to follow if not last segment */
+						dp->fn[NSFLAG] = NS_NONAME;
+						res = FR_OK;
+					} else {							/* Could not find the object */
+						if (!(ns & NS_LAST)) res = FR_NO_PATH;	/* Adjust error code if not last segment */
+					}
+				}
+				break;
+			}
+			if (ns & NS_LAST) break;			/* Last segment matched. Function completed. */
+			/* Get into the sub-directory */
+			if (!(obj->attr & AM_DIR)) {		/* It is not a sub-directory and cannot follow */
+				res = FR_NO_PATH; break;
+			}
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {		/* Save containing directory information for next dir */
+				obj->c_scl = obj->sclust;
+				obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat;
+				obj->c_ofs = dp->blk_ofs;
+				obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Open next directory */
+				obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+				obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+			} else
+#endif
+			{
+				obj->sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs));	/* Open next directory */
+			}
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get logical drive number from path name                               */
+/*-----------------------------------------------------------------------*/
+
+static
+int get_ldnumber (		/* Returns logical drive number (-1:invalid drive) */
+	const TCHAR** path	/* Pointer to pointer to the path name */
+)
+{
+	const TCHAR *tp, *tt;
+	UINT i;
+	int vol = -1;
+#if _STR_VOLUME_ID		/* Find string drive id */
+	static const char* const volid[] = {_VOLUME_STRS};
+	const char *sp;
+	char c;
+	TCHAR tc;
+#endif
+
+
+	if (*path) {	/* If the pointer is not a null */
+		for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ;	/* Find ':' in the path */
+		if (*tt == ':') {	/* If a ':' is exist in the path name */
+			tp = *path;
+			i = *tp++ - '0';
+			if (i < 10 && tp == tt) {	/* Is there a numeric drive id? */
+				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+					vol = (int)i;
+					*path = ++tt;
+				}
+			}
+#if _STR_VOLUME_ID
+			 else {	/* No numeric drive number, find string drive id */
+				i = 0; tt++;
+				do {
+					sp = volid[i]; tp = *path;
+					do {	/* Compare a string drive id with path name */
+						c = *sp++; tc = *tp++;
+						if (IsLower(tc)) tc -= 0x20;
+					} while (c && (TCHAR)c == tc);
+				} while ((c || tp != tt) && ++i < _VOLUMES);	/* Repeat for each id until pattern match */
+				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+					vol = (int)i;
+					*path = tt;
+				}
+			}
+#endif
+			return vol;
+		}
+#if _FS_RPATH != 0 && _VOLUMES >= 2
+		vol = CurrVol;	/* Current drive */
+#else
+		vol = 0;		/* Drive 0 */
+#endif
+	}
+	return vol;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Load a sector and check if it is an FAT boot sector                   */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:FAT, 1:exFAT, 2:Valid BS but not FAT, 3:Not a BS, 4:Disk error */
+	FATFS* fs,	/* File system object */
+	DWORD sect	/* Sector# (lba) to load and check if it is an FAT-VBR or not */
+)
+{
+	fs->wflag = 0; fs->winsect = 0xFFFFFFFF;		/* Invaidate window */
+	if (move_window(fs, sect) != FR_OK) return 4;	/* Load boot record */
+
+	if (ld_word(fs->win + BS_55AA) != 0xAA55) return 3;	/* Check boot record signature (always placed here even if the sector size is >512) */
+
+	if (fs->win[BS_JmpBoot] == 0xE9 || (fs->win[BS_JmpBoot] == 0xEB && fs->win[BS_JmpBoot + 2] == 0x90)) {
+		if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0;	/* Check "FAT" string */
+		if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0;			/* Check "FAT3" string */
+	}
+#if _FS_EXFAT
+	if (!mem_cmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11)) return 1;
+#endif
+	return 2;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Find logical drive and check if the volume is mounted                 */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
+	const TCHAR** path,	/* Pointer to pointer to the path name (drive number) */
+	FATFS** rfs,		/* Pointer to pointer to the found file system object */
+	BYTE mode			/* !=0: Check write protection for write access */
+)
+{
+	BYTE fmt, *pt;
+	int vol;
+	DSTATUS stat;
+	DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4];
+	WORD nrsv;
+	FATFS *fs;
+	UINT i;
+
+
+	/* Get logical drive number */
+	*rfs = 0;
+	vol = get_ldnumber(path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	/* Check if the file system object is valid or not */
+	fs = FatFs[vol];					/* Get pointer to the file system object */
+	if (!fs) return FR_NOT_ENABLED;		/* Is the file system object available? */
+
+	ENTER_FF(fs);						/* Lock the volume */
+	*rfs = fs;							/* Return pointer to the file system object */
+
+	mode &= (BYTE)~FA_READ;				/* Desired access mode, write access or not */
+	if (fs->fs_type) {					/* If the volume has been mounted */
+		stat = disk_status(fs->drv);
+		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
+			if (!_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
+				return FR_WRITE_PROTECTED;
+			}
+			return FR_OK;				/* The file system object is valid */
+		}
+	}
+
+	/* The file system object is not valid. */
+	/* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */
+
+	fs->fs_type = 0;					/* Clear the file system object */
+	fs->drv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
+	stat = disk_initialize(fs->drv);	/* Initialize the physical drive */
+	if (stat & STA_NOINIT) { 			/* Check if the initialization succeeded */
+		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
+	}
+	if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
+		return FR_WRITE_PROTECTED;
+	}
+#if _MAX_SS != _MIN_SS					/* Get sector size (multiple sector size cfg only) */
+	if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR;
+	if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+#endif
+
+	/* Find an FAT partition on the drive. Supports only generic partitioning rules, FDISK and SFD. */
+	bsect = 0;
+	fmt = check_fs(fs, bsect);			/* Load sector 0 and check if it is an FAT-VBR as SFD */
+	if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) {	/* Not an FAT-VBR or forced partition number */
+		for (i = 0; i < 4; i++) {		/* Get partition offset */
+			pt = fs->win + (MBR_Table + i * SZ_PTE);
+			br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
+		}
+		i = LD2PT(vol);					/* Partition number: 0:auto, 1-4:forced */
+		if (i) i--;
+		do {							/* Find an FAT volume */
+			bsect = br[i];
+			fmt = bsect ? check_fs(fs, bsect) : 3;	/* Check the partition */
+		} while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
+	}
+	if (fmt == 4) return FR_DISK_ERR;		/* An error occured in the disk I/O layer */
+	if (fmt >= 2) return FR_NO_FILESYSTEM;	/* No FAT volume is found */
+
+	/* An FAT volume is found (bsect). Following code initializes the file system object */
+
+#if _FS_EXFAT
+	if (fmt == 1) {
+		QWORD maxlba;
+
+		for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ;	/* Check zero filler */
+		if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM;
+
+		if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM;	/* Check exFAT revision (Must be 1.0) */
+
+		if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) {	/* (BPB_BytsPerSecEx must be equal to the physical sector size) */
+			return FR_NO_FILESYSTEM;
+		}
+
+		maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect;	/* Last LBA + 1 of the volume */
+		if (maxlba >= 0x100000000) return FR_NO_FILESYSTEM;	/* (It cannot be handled in 32-bit LBA) */
+
+		fs->fsize = ld_dword(fs->win + BPB_FatSzEx);	/* Number of sectors per FAT */
+
+		fs->n_fats = fs->win[BPB_NumFATsEx];			/* Number of FATs */
+		if (fs->n_fats != 1) return FR_NO_FILESYSTEM;	/* (Supports only 1 FAT) */
+
+		fs->csize = 1 << fs->win[BPB_SecPerClusEx];		/* Cluster size */
+		if (fs->csize == 0)	return FR_NO_FILESYSTEM;	/* (Must be 1..32768) */
+
+		nclst = ld_dword(fs->win + BPB_NumClusEx);		/* Number of clusters */
+		if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM;	/* (Too many clusters) */
+		fs->n_fatent = nclst + 2;
+
+		/* Boundaries and Limits */
+		fs->volbase = bsect;
+		fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx);
+		fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx);
+		if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM;	/* (Volume size must not be smaller than the size requiered) */
+		fs->dirbase = ld_dword(fs->win + BPB_RootClusEx);
+
+		/* Check if bitmap location is in assumption (at the first cluster) */
+		if (move_window(fs, clust2sect(fs, fs->dirbase)) != FR_OK) return FR_DISK_ERR;
+		for (i = 0; i < SS(fs); i += SZDIRE) {
+			if (fs->win[i] == 0x81 && ld_dword(fs->win + i + 20) == 2) break;	/* 81 entry with cluster #2? */
+		}
+		if (i == SS(fs)) return FR_NO_FILESYSTEM;
+#if !_FS_READONLY
+		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+#endif
+		fmt = FS_EXFAT;			/* FAT sub-type */
+	} else
+#endif	/* _FS_EXFAT */
+	{
+		if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_BytsPerSec must be equal to the physical sector size) */
+
+		fasize = ld_word(fs->win + BPB_FATSz16);		/* Number of sectors per FAT */
+		if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
+		fs->fsize = fasize;
+
+		fs->n_fats = fs->win[BPB_NumFATs];				/* Number of FATs */
+		if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM;	/* (Must be 1 or 2) */
+		fasize *= fs->n_fats;							/* Number of sectors for FAT area */
+
+		fs->csize = fs->win[BPB_SecPerClus];			/* Cluster size */
+		if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM;	/* (Must be power of 2) */
+
+		fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt);	/* Number of root directory entries */
+		if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM;	/* (Must be sector aligned) */
+
+		tsect = ld_word(fs->win + BPB_TotSec16);		/* Number of sectors on the volume */
+		if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
+
+		nrsv = ld_word(fs->win + BPB_RsvdSecCnt);		/* Number of reserved sectors */
+		if (nrsv == 0) return FR_NO_FILESYSTEM;			/* (Must not be 0) */
+
+		/* Determine the FAT sub type */
+		sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE);	/* RSV + FAT + DIR */
+		if (tsect < sysect) return FR_NO_FILESYSTEM;	/* (Invalid volume size) */
+		nclst = (tsect - sysect) / fs->csize;			/* Number of clusters */
+		if (nclst == 0) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
+		fmt = FS_FAT32;
+		if (nclst <= MAX_FAT16) fmt = FS_FAT16;
+		if (nclst <= MAX_FAT12) fmt = FS_FAT12;
+
+		/* Boundaries and Limits */
+		fs->n_fatent = nclst + 2;						/* Number of FAT entries */
+		fs->volbase = bsect;							/* Volume start sector */
+		fs->fatbase = bsect + nrsv; 					/* FAT start sector */
+		fs->database = bsect + sysect;					/* Data start sector */
+		if (fmt == FS_FAT32) {
+			if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM;	/* (Must be FAT32 revision 0.0) */
+			if (fs->n_rootdir) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
+			fs->dirbase = ld_dword(fs->win + BPB_RootClus32);	/* Root directory start cluster */
+			szbfat = fs->n_fatent * 4;					/* (Needed FAT size) */
+		} else {
+			if (fs->n_rootdir == 0)	return FR_NO_FILESYSTEM;/* (BPB_RootEntCnt must not be 0) */
+			fs->dirbase = fs->fatbase + fasize;			/* Root directory start sector */
+			szbfat = (fmt == FS_FAT16) ?				/* (Needed FAT size) */
+				fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+		}
+		if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_FATSz must not be less than the size needed) */
+
+#if !_FS_READONLY
+		/* Get FSINFO if available */
+		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+		fs->fsi_flag = 0x80;
+#if (_FS_NOFSINFO & 3) != 3
+		if (fmt == FS_FAT32				/* Enable FSINFO only if FAT32 and BPB_FSInfo32 == 1 */
+			&& ld_word(fs->win + BPB_FSInfo32) == 1
+			&& move_window(fs, bsect + 1) == FR_OK)
+		{
+			fs->fsi_flag = 0;
+			if (ld_word(fs->win + BS_55AA) == 0xAA55	/* Load FSINFO data if available */
+				&& ld_dword(fs->win + FSI_LeadSig) == 0x41615252
+				&& ld_dword(fs->win + FSI_StrucSig) == 0x61417272)
+			{
+#if (_FS_NOFSINFO & 1) == 0
+				fs->free_clst = ld_dword(fs->win + FSI_Free_Count);
+#endif
+#if (_FS_NOFSINFO & 2) == 0
+				fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free);
+#endif
+			}
+		}
+#endif	/* (_FS_NOFSINFO & 3) != 3 */
+#endif	/* !_FS_READONLY */
+	}
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+	fs->id = ++Fsid;		/* File system mount ID */
+#if _USE_LFN == 1
+	fs->lfnbuf = LfnBuf;	/* Static LFN working buffer */
+#if _FS_EXFAT
+	fs->dirbuf = DirBuf;	/* Static directory block scratchpad buuffer */
+#endif
+#endif
+#if _FS_RPATH != 0
+	fs->cdir = 0;			/* Initialize current directory */
+#endif
+#if _FS_LOCK != 0			/* Clear file lock semaphores */
+	clear_lock(fs);
+#endif
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/directory object is valid or not                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT validate (	/* Returns FR_OK or FR_INVALID_OBJECT */
+	_FDID* obj,		/* Pointer to the _OBJ, the 1st member in the FIL/DIR object, to check validity */
+	FATFS** fs		/* Pointer to pointer to the owner file system object to return */
+)
+{
+	FRESULT res = FR_INVALID_OBJECT;
+
+
+	if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) {	/* Test if the object is valid */
+#if _FS_REENTRANT
+		if (lock_fs(obj->fs)) {	/* Obtain the filesystem object */
+			if (!(disk_status(obj->fs->drv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */
+				res = FR_OK;
+			} else {
+				unlock_fs(obj->fs, FR_OK);
+			}
+		} else {
+			res = FR_TIMEOUT;
+		}
+#else
+		if (!(disk_status(obj->fs->drv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */
+			res = FR_OK;
+		}
+#endif
+	}
+	*fs = (res == FR_OK) ? obj->fs : 0;	/* Corresponding filesystem object */
+	return res;
+}
+
+
+
+
+/*---------------------------------------------------------------------------
+
+   Public Functions (FatFs API)
+
+----------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+	FATFS* fs,			/* Pointer to the file system object (NULL:unmount)*/
+	const TCHAR* path,	/* Logical drive number to be mounted/unmounted */
+	BYTE opt			/* Mode option 0:Do not mount (delayed mount), 1:Mount immediately */
+)
+{
+	FATFS *cfs;
+	int vol;
+	FRESULT res;
+	const TCHAR *rp = path;
+
+
+	/* Get logical drive number */
+	vol = get_ldnumber(&rp);
+	if (vol < 0) return FR_INVALID_DRIVE;
+	cfs = FatFs[vol];					/* Pointer to fs object */
+
+	if (cfs) {
+#if _FS_LOCK != 0
+		clear_lock(cfs);
+#endif
+#if _FS_REENTRANT						/* Discard sync object of the current volume */
+		if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR;
+#endif
+		cfs->fs_type = 0;				/* Clear old fs object */
+	}
+
+	if (fs) {
+		fs->fs_type = 0;				/* Clear new fs object */
+#if _FS_REENTRANT						/* Create sync object for the new volume */
+		if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR;
+#endif
+	}
+	FatFs[vol] = fs;					/* Register new fs object */
+
+	if (!fs || opt != 1) return FR_OK;	/* Do not mount now, it will be mounted later */
+
+	res = find_volume(&path, &fs, 0);	/* Force mounted the volume */
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+	FIL* fp,			/* Pointer to the blank file object */
+	const TCHAR* path,	/* Pointer to the file name */
+	BYTE mode			/* Access mode and file open mode flags */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+#if !_FS_READONLY
+	DWORD dw, cl, bcs, clst, sc;
+	FSIZE_t ofs;
+#endif
+	DEF_NAMBUF
+
+
+	if (!fp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive */
+	mode &= _FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND | FA_SEEKEND;
+	res = find_volume(&path, &fs, mode);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+#if !_FS_READONLY	/* R/W configuration */
+		if (res == FR_OK) {
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+				res = FR_INVALID_NAME;
+			}
+#if _FS_LOCK != 0
+			else {
+				res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+			}
+#endif
+		}
+		/* Create or Open a file */
+		if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+			if (res != FR_OK) {					/* No file, create new */
+				if (res == FR_NO_FILE) {		/* There is no file to open, create a new entry */
+#if _FS_LOCK != 0
+					res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+					res = dir_register(&dj);
+#endif
+				}
+				mode |= FA_CREATE_ALWAYS;		/* File is created */
+			}
+			else {								/* Any object is already existing */
+				if (dj.obj.attr & (AM_RDO | AM_DIR)) {	/* Cannot overwrite it (R/O or DIR) */
+					res = FR_DENIED;
+				} else {
+					if (mode & FA_CREATE_NEW) res = FR_EXIST;	/* Cannot create as new file */
+				}
+			}
+			if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) {	/* Truncate it if overwrite mode */
+				dw = GET_FATTIME();
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					/* Get current allocation info */
+					fp->obj.fs = fs;
+					fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus);
+					fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+					fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+					fp->obj.n_frag = 0;
+					/* Initialize directory entry block */
+					st_dword(fs->dirbuf + XDIR_CrtTime, dw);	/* Set created time */
+					fs->dirbuf[XDIR_CrtTime10] = 0;
+					st_dword(fs->dirbuf + XDIR_ModTime, dw);	/* Set modified time */
+					fs->dirbuf[XDIR_ModTime10] = 0;
+					fs->dirbuf[XDIR_Attr] = AM_ARC;				/* Reset attribute */
+					st_dword(fs->dirbuf + XDIR_FstClus, 0);		/* Reset file allocation info */
+					st_qword(fs->dirbuf + XDIR_FileSize, 0);
+					st_qword(fs->dirbuf + XDIR_ValidFileSize, 0);
+					fs->dirbuf[XDIR_GenFlags] = 1;
+					res = store_xdir(&dj);
+					if (res == FR_OK && fp->obj.sclust) {		/* Remove the cluster chain if exist */
+						res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+						fs->last_clst = fp->obj.sclust - 1;		/* Reuse the cluster hole */
+					}
+				} else
+#endif
+				{
+					/* Clean directory info */
+					st_dword(dj.dir + DIR_CrtTime, dw);	/* Set created time */
+					st_dword(dj.dir + DIR_ModTime, dw);	/* Set modified time */
+					dj.dir[DIR_Attr] = AM_ARC;			/* Reset attribute */
+					cl = ld_clust(fs, dj.dir);			/* Get cluster chain */
+					st_clust(fs, dj.dir, 0);			/* Reset file allocation info */
+					st_dword(dj.dir + DIR_FileSize, 0);
+					fs->wflag = 1;
+
+					if (cl) {							/* Remove the cluster chain if exist */
+						dw = fs->winsect;
+						res = remove_chain(&dj.obj, cl, 0);
+						if (res == FR_OK) {
+							res = move_window(fs, dw);
+							fs->last_clst = cl - 1;		/* Reuse the cluster hole */
+						}
+					}
+				}
+			}
+		}
+		else {	/* Open an existing file */
+			if (res == FR_OK) {					/* Following succeeded */
+				if (dj.obj.attr & AM_DIR) {		/* It is a directory */
+					res = FR_NO_FILE;
+				} else {
+					if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* R/O violation */
+						res = FR_DENIED;
+					}
+				}
+			}
+		}
+		if (res == FR_OK) {
+			if (mode & FA_CREATE_ALWAYS)		/* Set file change flag if created or overwritten */
+				mode |= FA_MODIFIED;
+			fp->dir_sect = fs->winsect;			/* Pointer to the directory entry */
+			fp->dir_ptr = dj.dir;
+#if _FS_LOCK != 0
+			fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+			if (!fp->obj.lockid) res = FR_INT_ERR;
+#endif
+		}
+#else		/* R/O configuration */
+		if (res == FR_OK) {
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+				res = FR_INVALID_NAME;
+			} else {
+				if (dj.obj.attr & AM_DIR) {		/* It is a directory */
+					res = FR_NO_FILE;
+				}
+			}
+		}
+#endif
+
+		if (res == FR_OK) {
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				fp->obj.c_scl = dj.obj.sclust;							/* Get containing directory info */
+				fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+				fp->obj.c_ofs = dj.blk_ofs;
+				fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Get object allocation info */
+				fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+				fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+			} else
+#endif
+			{
+				fp->obj.sclust = ld_clust(fs, dj.dir);					/* Get object allocation info */
+				fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+			}
+#if _USE_FASTSEEK
+			fp->cltbl = 0;			/* Disable fast seek mode */
+#endif
+			fp->obj.fs = fs;	 	/* Validate the file object */
+			fp->obj.id = fs->id;
+			fp->flag = mode;		/* Set file access mode */
+			fp->err = 0;			/* Clear error flag */
+			fp->sect = 0;			/* Invalidate current data sector */
+			fp->fptr = 0;			/* Set file pointer top of the file */
+#if !_FS_READONLY
+#if !_FS_TINY
+			mem_set(fp->buf, 0, _MAX_SS);	/* Clear sector buffer */
+#endif
+			if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) {	/* Seek to end of file if FA_OPEN_APPEND is specified */
+				fp->fptr = fp->obj.objsize;			/* Offset to seek */
+				bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size in byte */
+				clst = fp->obj.sclust;				/* Follow the cluster chain */
+				for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
+					clst = get_fat(&fp->obj, clst);
+					if (clst <= 1) res = FR_INT_ERR;
+					if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
+				}
+				fp->clust = clst;
+				if (res == FR_OK && ofs % SS(fs)) {	/* Fill sector buffer if not on the sector boundary */
+					if ((sc = clust2sect(fs, clst)) == 0) {
+						res = FR_INT_ERR;
+					} else {
+						fp->sect = sc + (DWORD)(ofs / SS(fs));
+#if !_FS_TINY
+						if (disk_read(fs->drv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR;
+#endif
+					}
+				}
+			}
+#endif
+		}
+
+		FREE_NAMBUF();
+	}
+
+	if (res != FR_OK) fp->obj.fs = 0;	/* Invalidate file object on error */
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+	FIL* fp, 	/* Pointer to the file object */
+	void* buff,	/* Pointer to data buffer */
+	UINT btr,	/* Number of bytes to read */
+	UINT* br	/* Pointer to number of bytes read */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, sect;
+	FSIZE_t remain;
+	UINT rcnt, cc, csect;
+	BYTE *rbuff = (BYTE*)buff;
+
+
+	*br = 0;	/* Clear read byte counter */
+	res = validate(&fp->obj, &fs);				/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+	remain = fp->obj.objsize - fp->fptr;
+	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+
+	for ( ;  btr;								/* Repeat until all data read */
+		rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+		if (fp->fptr % SS(fs) == 0) {			/* On the sector boundary? */
+			csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (csect == 0) {					/* On the cluster boundary? */
+				if (fp->fptr == 0) {			/* On the top of the file? */
+					clst = fp->obj.sclust;		/* Follow cluster chain from the origin */
+				} else {						/* Middle or end of the file */
+#if _USE_FASTSEEK
+					if (fp->cltbl) {
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					} else
+#endif
+					{
+						clst = get_fat(&fp->obj, fp->clust);	/* Follow cluster chain on the FAT */
+					}
+				}
+				if (clst < 2) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs, fp->clust);	/* Get current sector */
+			if (!sect) ABORT(fs, FR_INT_ERR);
+			sect += csect;
+			cc = btr / SS(fs);					/* When remaining bytes >= sector size, */
+			if (cc) {							/* Read maximum contiguous sectors directly */
+				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+					cc = fs->csize - csect;
+				}
+				if (disk_read(fs->drv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if _FS_TINY
+				if (fs->wflag && fs->winsect - sect < cc) {
+					mem_cpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs));
+				}
+#else
+				if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) {
+					mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+				}
+#endif
+#endif
+				rcnt = SS(fs) * cc;				/* Number of bytes transferred */
+				continue;
+			}
+#if !_FS_TINY
+			if (fp->sect != sect) {			/* Load data sector if not in cache */
+#if !_FS_READONLY
+				if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+					if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+					fp->flag &= (BYTE)~FA_DIRTY;
+				}
+#endif
+				if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK)	ABORT(fs, FR_DISK_ERR);	/* Fill sector cache */
+			}
+#endif
+			fp->sect = sect;
+		}
+		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+		if (rcnt > btr) rcnt = btr;					/* Clip it by btr if needed */
+#if _FS_TINY
+		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+		mem_cpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+#else
+		mem_cpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+#endif
+	}
+
+	LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+	FIL* fp,			/* Pointer to the file object */
+	const void* buff,	/* Pointer to the data to be written */
+	UINT btw,			/* Number of bytes to write */
+	UINT* bw			/* Pointer to number of bytes written */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, sect;
+	UINT wcnt, cc, csect;
+	const BYTE *wbuff = (const BYTE*)buff;
+
+
+	*bw = 0;	/* Clear write byte counter */
+	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	/* Check fptr wrap-around (file size cannot reach 4GiB on FATxx) */
+	if ((!_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) {
+		btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
+	}
+
+	for ( ;  btw;							/* Repeat until all data written */
+		wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize, *bw += wcnt, btw -= wcnt) {
+		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+			csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1);	/* Sector offset in the cluster */
+			if (csect == 0) {				/* On the cluster boundary? */
+				if (fp->fptr == 0) {		/* On the top of the file? */
+					clst = fp->obj.sclust;	/* Follow from the origin */
+					if (clst == 0) {		/* If no cluster is allocated, */
+						clst = create_chain(&fp->obj, 0);	/* create a new cluster chain */
+					}
+				} else {					/* On the middle or end of the file */
+#if _USE_FASTSEEK
+					if (fp->cltbl) {
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					} else
+#endif
+					{
+						clst = create_chain(&fp->obj, fp->clust);	/* Follow or stretch cluster chain on the FAT */
+					}
+				}
+				if (clst == 0) break;		/* Could not allocate a new cluster (disk full) */
+				if (clst == 1) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;			/* Update current cluster */
+				if (fp->obj.sclust == 0) fp->obj.sclust = clst;	/* Set start cluster if the first write */
+			}
+#if _FS_TINY
+			if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Write-back sector cache */
+#else
+			if (fp->flag & FA_DIRTY) {		/* Write-back sector cache */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			sect = clust2sect(fs, fp->clust);	/* Get current sector */
+			if (!sect) ABORT(fs, FR_INT_ERR);
+			sect += csect;
+			cc = btw / SS(fs);				/* When remaining bytes >= sector size, */
+			if (cc) {						/* Write maximum contiguous sectors directly */
+				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+					cc = fs->csize - csect;
+				}
+				if (disk_write(fs->drv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if _FS_MINIMIZE <= 2
+#if _FS_TINY
+				if (fs->winsect - sect < cc) {	/* Refill sector cache if it gets invalidated by the direct write */
+					mem_cpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs));
+					fs->wflag = 0;
+				}
+#else
+				if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+					mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
+					fp->flag &= (BYTE)~FA_DIRTY;
+				}
+#endif
+#endif
+				wcnt = SS(fs) * cc;		/* Number of bytes transferred */
+				continue;
+			}
+#if _FS_TINY
+			if (fp->fptr >= fp->obj.objsize) {	/* Avoid silly cache filling on the growing edge */
+				if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);
+				fs->winsect = sect;
+			}
+#else
+			if (fp->sect != sect && 		/* Fill sector cache with file data */
+				fp->fptr < fp->obj.objsize &&
+				disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) {
+					ABORT(fs, FR_DISK_ERR);
+			}
+#endif
+			fp->sect = sect;
+		}
+		wcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+		if (wcnt > btw) wcnt = btw;					/* Clip it by btw if needed */
+#if _FS_TINY
+		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+		mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+		fs->wflag = 1;
+#else
+		mem_cpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+		fp->flag |= FA_DIRTY;
+#endif
+	}
+
+	fp->flag |= FA_MODIFIED;				/* Set file change flag */
+
+	LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File                                                  */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD tm;
+	BYTE *dir;
+#if _FS_EXFAT
+	DIR dj;
+	DEF_NAMBUF
+#endif
+
+	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+	if (res == FR_OK) {
+		if (fp->flag & FA_MODIFIED) {	/* Is there any change to the file? */
+#if !_FS_TINY
+			if (fp->flag & FA_DIRTY) {	/* Write-back cached data if needed */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			/* Update the directory entry */
+			tm = GET_FATTIME();				/* Modified time */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				res = fill_first_frag(&fp->obj);	/* Fill first fragment on the FAT if needed */
+				if (res == FR_OK) {
+					res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+				}
+				if (res == FR_OK) {
+					INIT_NAMBUF(fs);
+					res = load_obj_dir(&dj, &fp->obj);	/* Load directory entry block */
+					if (res == FR_OK) {
+						fs->dirbuf[XDIR_Attr] |= AM_ARC;				/* Set archive bit */
+						fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1;	/* Update file allocation info */
+						st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust);
+						st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize);
+						st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize);
+						st_dword(fs->dirbuf + XDIR_ModTime, tm);		/* Update modified time */
+						fs->dirbuf[XDIR_ModTime10] = 0;
+						st_dword(fs->dirbuf + XDIR_AccTime, 0);
+						res = store_xdir(&dj);	/* Restore it to the directory */
+						if (res == FR_OK) {
+							res = sync_fs(fs);
+							fp->flag &= (BYTE)~FA_MODIFIED;
+						}
+					}
+					FREE_NAMBUF();
+				}
+			} else
+#endif
+			{
+				res = move_window(fs, fp->dir_sect);
+				if (res == FR_OK) {
+					dir = fp->dir_ptr;
+					dir[DIR_Attr] |= AM_ARC;						/* Set archive bit */
+					st_clust(fp->obj.fs, dir, fp->obj.sclust);		/* Update file allocation info  */
+					st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize);	/* Update file size */
+					st_dword(dir + DIR_ModTime, tm);				/* Update modified time */
+					st_word(dir + DIR_LstAccDate, 0);
+					fs->wflag = 1;
+					res = sync_fs(fs);					/* Restore it to the directory */
+					fp->flag &= (BYTE)~FA_MODIFIED;
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+	FIL* fp		/* Pointer to the file object to be closed */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+
+#if !_FS_READONLY
+	res = f_sync(fp);					/* Flush cached data */
+	if (res == FR_OK)
+#endif
+	{
+		res = validate(&fp->obj, &fs);	/* Lock volume */
+		if (res == FR_OK) {
+#if _FS_LOCK != 0
+			res = dec_lock(fp->obj.lockid);	/* Decrement file open counter */
+			if (res == FR_OK)
+#endif
+			{
+				fp->obj.fs = 0;			/* Invalidate file object */
+			}
+#if _FS_REENTRANT
+			unlock_fs(fs, FR_OK);		/* Unlock volume */
+#endif
+		}
+	}
+	return res;
+}
+
+
+
+
+#if _FS_RPATH >= 1
+/*-----------------------------------------------------------------------*/
+/* Change Current Directory or Current Drive, Get Current Directory      */
+/*-----------------------------------------------------------------------*/
+
+#if _VOLUMES >= 2
+FRESULT f_chdrive (
+	const TCHAR* path		/* Drive number */
+)
+{
+	int vol;
+
+
+	/* Get logical drive number */
+	vol = get_ldnumber(&path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	CurrVol = (BYTE)vol;	/* Set it as current volume */
+
+	return FR_OK;
+}
+#endif
+
+
+FRESULT f_chdir (
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	DEF_NAMBUF
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);		/* Follow the path */
+		if (res == FR_OK) {					/* Follow completed */
+			if (dj.fn[NSFLAG] & NS_NONAME) {
+				fs->cdir = dj.obj.sclust;	/* It is the start directory itself */
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					fs->cdc_scl = dj.obj.c_scl;
+					fs->cdc_size = dj.obj.c_size;
+					fs->cdc_ofs = dj.obj.c_ofs;
+				}
+#endif
+			} else {
+				if (dj.obj.attr & AM_DIR) {	/* It is a sub-directory */
+#if _FS_EXFAT
+					if (fs->fs_type == FS_EXFAT) {
+						fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus);		/* Sub-directory cluster */
+						fs->cdc_scl = dj.obj.sclust;						/* Save containing directory information */
+						fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+						fs->cdc_ofs = dj.blk_ofs;
+					} else
+#endif
+					{
+						fs->cdir = ld_clust(fs, dj.dir);					/* Sub-directory cluster */
+					}
+				} else {
+					res = FR_NO_PATH;		/* Reached but a file */
+				}
+			}
+		}
+		FREE_NAMBUF();
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+#if _FS_RPATH >= 2
+FRESULT f_getcwd (
+	TCHAR* buff,	/* Pointer to the directory path */
+	UINT len		/* Size of path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	UINT i, n;
+	DWORD ccl;
+	TCHAR *tp;
+	FILINFO fno;
+	DEF_NAMBUF
+
+
+	*buff = 0;
+	/* Get logical drive */
+	res = find_volume((const TCHAR**)&buff, &fs, 0);	/* Get current volume */
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		i = len;			/* Bottom of buffer (directory stack base) */
+		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {	/* (Cannot do getcwd on exFAT and returns root path) */
+			dj.obj.sclust = fs->cdir;				/* Start to follow upper directory from current directory */
+			while ((ccl = dj.obj.sclust) != 0) {	/* Repeat while current directory is a sub-directory */
+				res = dir_sdi(&dj, 1 * SZDIRE);	/* Get parent directory */
+				if (res != FR_OK) break;
+				res = move_window(fs, dj.sect);
+				if (res != FR_OK) break;
+				dj.obj.sclust = ld_clust(fs, dj.dir);	/* Goto parent directory */
+				res = dir_sdi(&dj, 0);
+				if (res != FR_OK) break;
+				do {							/* Find the entry links to the child directory */
+					res = dir_read(&dj, 0);
+					if (res != FR_OK) break;
+					if (ccl == ld_clust(fs, dj.dir)) break;	/* Found the entry */
+					res = dir_next(&dj, 0);
+				} while (res == FR_OK);
+				if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+				if (res != FR_OK) break;
+				get_fileinfo(&dj, &fno);		/* Get the directory name and push it to the buffer */
+				for (n = 0; fno.fname[n]; n++) ;
+				if (i < n + 3) {
+					res = FR_NOT_ENOUGH_CORE; break;
+				}
+				while (n) buff[--i] = fno.fname[--n];
+				buff[--i] = '/';
+			}
+		}
+		tp = buff;
+		if (res == FR_OK) {
+#if _VOLUMES >= 2
+			*tp++ = '0' + CurrVol;			/* Put drive number */
+			*tp++ = ':';
+#endif
+			if (i == len) {					/* Root-directory */
+				*tp++ = '/';
+			} else {						/* Sub-directroy */
+				do		/* Add stacked path str */
+					*tp++ = buff[i++];
+				while (i < len);
+			}
+		}
+		*tp = 0;
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* _FS_RPATH >= 2 */
+#endif /* _FS_RPATH >= 1 */
+
+
+
+#if _FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t ofs		/* File pointer from top of file */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, bcs, nsect;
+	FSIZE_t ifptr;
+#if _USE_FASTSEEK
+	DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
+#endif
+
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res == FR_OK) res = (FRESULT)fp->err;
+#if _FS_EXFAT && !_FS_READONLY
+	if (res == FR_OK && fs->fs_type == FS_EXFAT) {
+		res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+	}
+#endif
+	if (res != FR_OK) LEAVE_FF(fs, res);
+
+#if _USE_FASTSEEK
+	if (fp->cltbl) {	/* Fast seek */
+		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
+			tbl = fp->cltbl;
+			tlen = *tbl++; ulen = 2;	/* Given table size and required table size */
+			cl = fp->obj.sclust;		/* Origin of the chain */
+			if (cl) {
+				do {
+					/* Get a fragment */
+					tcl = cl; ncl = 0; ulen += 2;	/* Top, length and used items */
+					do {
+						pcl = cl; ncl++;
+						cl = get_fat(&fp->obj, cl);
+						if (cl <= 1) ABORT(fs, FR_INT_ERR);
+						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					} while (cl == pcl + 1);
+					if (ulen <= tlen) {		/* Store the length and top of the fragment */
+						*tbl++ = ncl; *tbl++ = tcl;
+					}
+				} while (cl < fs->n_fatent);	/* Repeat until end of chain */
+			}
+			*fp->cltbl = ulen;	/* Number of items used */
+			if (ulen <= tlen) {
+				*tbl = 0;		/* Terminate table */
+			} else {
+				res = FR_NOT_ENOUGH_CORE;	/* Given table size is smaller than required */
+			}
+		} else {						/* Fast seek */
+			if (ofs > fp->obj.objsize) ofs = fp->obj.objsize;	/* Clip offset at the file size */
+			fp->fptr = ofs;				/* Set file pointer */
+			if (ofs) {
+				fp->clust = clmt_clust(fp, ofs - 1);
+				dsc = clust2sect(fs, fp->clust);
+				if (!dsc) ABORT(fs, FR_INT_ERR);
+				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+					if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+						if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+						fp->flag &= (BYTE)~FA_DIRTY;
+					}
+#endif
+					if (disk_read(fs->drv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Load current sector */
+#endif
+					fp->sect = dsc;
+				}
+			}
+		}
+	} else
+#endif
+
+	/* Normal Seek */
+	{
+#if _FS_EXFAT
+		if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF;	/* Clip at 4GiB-1 if at FATxx */
+#endif
+		if (ofs > fp->obj.objsize && (_FS_READONLY || !(fp->flag & FA_WRITE))) {	/* In read-only mode, clip offset with the file size */
+			ofs = fp->obj.objsize;
+		}
+		ifptr = fp->fptr;
+		fp->fptr = nsect = 0;
+		if (ofs) {
+			bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size (byte) */
+			if (ifptr > 0 &&
+				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+				fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1);	/* start from the current cluster */
+				ofs -= fp->fptr;
+				clst = fp->clust;
+			} else {									/* When seek to back cluster, */
+				clst = fp->obj.sclust;					/* start from the first cluster */
+#if !_FS_READONLY
+				if (clst == 0) {						/* If no cluster chain, create a new chain */
+					clst = create_chain(&fp->obj, 0);
+					if (clst == 1) ABORT(fs, FR_INT_ERR);
+					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					fp->obj.sclust = clst;
+				}
+#endif
+				fp->clust = clst;
+			}
+			if (clst != 0) {
+				while (ofs > bcs) {						/* Cluster following loop */
+					ofs -= bcs; fp->fptr += bcs;
+#if !_FS_READONLY
+					if (fp->flag & FA_WRITE) {			/* Check if in write mode or not */
+						if (_FS_EXFAT && fp->fptr > fp->obj.objsize) {	/* No FAT chain object needs correct objsize to generate FAT value */
+							fp->obj.objsize = fp->fptr;
+							fp->flag |= FA_MODIFIED;
+						}
+						clst = create_chain(&fp->obj, clst);	/* Follow chain with forceed stretch */
+						if (clst == 0) {				/* Clip file size in case of disk full */
+							ofs = 0; break;
+						}
+					} else
+#endif
+					{
+						clst = get_fat(&fp->obj, clst);	/* Follow cluster chain if not in write mode */
+					}
+					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+					fp->clust = clst;
+				}
+				fp->fptr += ofs;
+				if (ofs % SS(fs)) {
+					nsect = clust2sect(fs, clst);	/* Current sector */
+					if (!nsect) ABORT(fs, FR_INT_ERR);
+					nsect += (DWORD)(ofs / SS(fs));
+				}
+			}
+		}
+		if (!_FS_READONLY && fp->fptr > fp->obj.objsize) {		/* Set file change flag if the file size is extended */
+			fp->obj.objsize = fp->fptr;
+			fp->flag |= FA_MODIFIED;
+		}
+		if (fp->fptr % SS(fs) && nsect != fp->sect) {	/* Fill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+			if (fp->flag & FA_DIRTY) {			/* Write-back dirty sector cache */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			if (disk_read(fs->drv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Fill sector cache */
+#endif
+			fp->sect = nsect;
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directory Object                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+	DIR* dp,			/* Pointer to directory object to create */
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	_FDID *obj;
+	DEF_NAMBUF
+
+
+	if (!dp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive */
+	obj = &dp->obj;
+	res = find_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		obj->fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(dp, path);			/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (!(dp->fn[NSFLAG] & NS_NONAME)) {	/* It is not the origin directory itself */
+				if (obj->attr & AM_DIR) {		/* This object is a sub-directory */
+#if _FS_EXFAT
+					if (fs->fs_type == FS_EXFAT) {
+						obj->c_scl = obj->sclust;							/* Get containing directory inforamation */
+						obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat;
+						obj->c_ofs = dp->blk_ofs;
+						obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Get object allocation info */
+						obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+						obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+					} else
+#endif
+					{
+						obj->sclust = ld_clust(fs, dp->dir);	/* Get object allocation info */
+					}
+				} else {						/* This object is a file */
+					res = FR_NO_PATH;
+				}
+			}
+			if (res == FR_OK) {
+				obj->id = fs->id;
+				res = dir_sdi(dp, 0);			/* Rewind directory */
+#if _FS_LOCK != 0
+				if (res == FR_OK) {
+					if (obj->sclust) {
+						obj->lockid = inc_lock(dp, 0);	/* Lock the sub directory */
+						if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES;
+					} else {
+						obj->lockid = 0;	/* Root directory need not to be locked */
+					}
+				}
+#endif
+			}
+		}
+		FREE_NAMBUF();
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+	if (res != FR_OK) obj->fs = 0;		/* Invalidate the directory object if function faild */
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close Directory                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_closedir (
+	DIR *dp		/* Pointer to the directory object to be closed */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+
+
+	res = validate(&dp->obj, &fs);			/* Check validity of the file object */
+	if (res == FR_OK) {
+#if _FS_LOCK != 0
+		if (dp->obj.lockid) {				/* Decrement sub-directory open counter */
+			res = dec_lock(dp->obj.lockid);
+		}
+		if (res == FR_OK)
+#endif
+		{
+			dp->obj.fs = 0;			/* Invalidate directory object */
+		}
+#if _FS_REENTRANT
+		unlock_fs(fs, FR_OK);		/* Unlock volume */
+#endif
+	}
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entries in Sequence                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+	DIR* dp,			/* Pointer to the open directory object */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	res = validate(&dp->obj, &fs);	/* Check validity of the directory object */
+	if (res == FR_OK) {
+		if (!fno) {
+			res = dir_sdi(dp, 0);			/* Rewind the directory object */
+		} else {
+			INIT_NAMBUF(fs);
+			res = dir_read(dp, 0);			/* Read an item */
+			if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory */
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dp, fno);		/* Get the object information */
+				res = dir_next(dp, 0);		/* Increment index for next */
+				if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory now */
+			}
+			FREE_NAMBUF();
+		}
+	}
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if _USE_FIND
+/*-----------------------------------------------------------------------*/
+/* Find Next File                                                        */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findnext (
+	DIR* dp,		/* Pointer to the open directory object */
+	FILINFO* fno	/* Pointer to the file information structure */
+)
+{
+	FRESULT res;
+
+
+	for (;;) {
+		res = f_readdir(dp, fno);		/* Get a directory item */
+		if (res != FR_OK || !fno || !fno->fname[0]) break;	/* Terminate if any error or end of directory */
+		if (pattern_matching(dp->pat, fno->fname, 0, 0)) break;		/* Test for the file name */
+#if _USE_LFN != 0 && _USE_FIND == 2
+		if (pattern_matching(dp->pat, fno->altname, 0, 0)) break;	/* Test for alternative name if exist */
+#endif
+	}
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Find First File                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findfirst (
+	DIR* dp,				/* Pointer to the blank directory object */
+	FILINFO* fno,			/* Pointer to the file information structure */
+	const TCHAR* path,		/* Pointer to the directory to open */
+	const TCHAR* pattern	/* Pointer to the matching pattern */
+)
+{
+	FRESULT res;
+
+
+	dp->pat = pattern;		/* Save pointer to pattern string */
+	res = f_opendir(dp, path);		/* Open the target directory */
+	if (res == FR_OK) {
+		res = f_findnext(dp, fno);	/* Find the first item */
+	}
+	return res;
+}
+
+#endif	/* _USE_FIND */
+
+
+
+#if _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+	const TCHAR* path,	/* Pointer to the file path */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	DIR dj;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &dj.obj.fs, 0);
+	if (res == FR_OK) {
+		INIT_NAMBUF(dj.obj.fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK) {				/* Follow completed */
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* It is origin directory */
+				res = FR_INVALID_NAME;
+			} else {							/* Found an object */
+				if (fno) get_fileinfo(&dj, fno);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(dj.obj.fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters                                           */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+	const TCHAR* path,	/* Path name of the logical drive number */
+	DWORD* nclst,		/* Pointer to a variable to return number of free clusters */
+	FATFS** fatfs		/* Pointer to return pointer to corresponding file system object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD nfree, clst, sect, stat;
+	UINT i;
+	BYTE *p;
+	_FDID obj;
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		*fatfs = fs;				/* Return ptr to the fs object */
+		/* If free_clst is valid, return it without full cluster scan */
+		if (fs->free_clst <= fs->n_fatent - 2) {
+			*nclst = fs->free_clst;
+		} else {
+			/* Get number of free clusters */
+			nfree = 0;
+			if (fs->fs_type == FS_FAT12) {	/* FAT12: Sector unalighed FAT entries */
+				clst = 2; obj.fs = fs;
+				do {
+					stat = get_fat(&obj, clst);
+					if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+					if (stat == 1) { res = FR_INT_ERR; break; }
+					if (stat == 0) nfree++;
+				} while (++clst < fs->n_fatent);
+			} else {
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {	/* exFAT: Scan bitmap table */
+					BYTE bm;
+					UINT b;
+
+					clst = fs->n_fatent - 2;
+					sect = fs->database;
+					i = 0;
+					do {
+						if (i == 0 && (res = move_window(fs, sect++)) != FR_OK) break;
+						for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) {
+							if (!(bm & 1)) nfree++;
+							bm >>= 1;
+						}
+						i = (i + 1) % SS(fs);
+					} while (clst);
+				} else
+#endif
+				{	/* FAT16/32: Sector alighed FAT entries */
+					clst = fs->n_fatent; sect = fs->fatbase;
+					i = 0; p = 0;
+					do {
+						if (i == 0) {
+							res = move_window(fs, sect++);
+							if (res != FR_OK) break;
+							p = fs->win;
+							i = SS(fs);
+						}
+						if (fs->fs_type == FS_FAT16) {
+							if (ld_word(p) == 0) nfree++;
+							p += 2; i -= 2;
+						} else {
+							if ((ld_dword(p) & 0x0FFFFFFF) == 0) nfree++;
+							p += 4; i -= 4;
+						}
+					} while (--clst);
+				}
+			}
+			*nclst = nfree;			/* Return the free clusters */
+			fs->free_clst = nfree;	/* Now free_clst is valid */
+			fs->fsi_flag |= 1;		/* FSInfo is to be updated */
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File                                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD ncl;
+
+
+	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	if (fp->fptr < fp->obj.objsize) {	/* Process when fptr is not on the eof */
+		if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+			res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+			fp->obj.sclust = 0;
+		} else {				/* When truncate a part of the file, remove remaining clusters */
+			ncl = get_fat(&fp->obj, fp->clust);
+			res = FR_OK;
+			if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+			if (ncl == 1) res = FR_INT_ERR;
+			if (res == FR_OK && ncl < fs->n_fatent) {
+				res = remove_chain(&fp->obj, ncl, fp->clust);
+			}
+		}
+		fp->obj.objsize = fp->fptr;	/* Set file size to current R/W point */
+		fp->flag |= FA_MODIFIED;
+#if !_FS_TINY
+		if (res == FR_OK && (fp->flag & FA_DIRTY)) {
+			if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) {
+				res = FR_DISK_ERR;
+			} else {
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+		}
+#endif
+		if (res != FR_OK) ABORT(fs, res);
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File/Directory                                               */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+	const TCHAR* path		/* Pointer to the file or directory path */
+)
+{
+	FRESULT res;
+	DIR dj, sdj;
+	DWORD dclst = 0;
+	FATFS *fs;
+#if _FS_EXFAT
+	_FDID obj;
+#endif
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, FA_WRITE);
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);		/* Follow the file path */
+		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) {
+			res = FR_INVALID_NAME;			/* Cannot remove dot entry */
+		}
+#if _FS_LOCK != 0
+		if (res == FR_OK) res = chk_lock(&dj, 2);	/* Check if it is an open object */
+#endif
+		if (res == FR_OK) {					/* The object is accessible */
+			if (dj.fn[NSFLAG] & NS_NONAME) {
+				res = FR_INVALID_NAME;		/* Cannot remove the origin directory */
+			} else {
+				if (dj.obj.attr & AM_RDO) {
+					res = FR_DENIED;		/* Cannot remove R/O object */
+				}
+			}
+			if (res == FR_OK) {
+#if _FS_EXFAT
+				obj.fs = fs;
+				if (fs->fs_type == FS_EXFAT) {
+					obj.sclust = dclst = ld_dword(fs->dirbuf + XDIR_FstClus);
+					obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+					obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+				} else
+#endif
+				{
+					dclst = ld_clust(fs, dj.dir);
+				}
+				if (dj.obj.attr & AM_DIR) {			/* Is it a sub-directory? */
+#if _FS_RPATH != 0
+					if (dclst == fs->cdir) {		 		/* Is it the current directory? */
+						res = FR_DENIED;
+					} else
+#endif
+					{
+						sdj.obj.fs = fs;						/* Open the sub-directory */
+						sdj.obj.sclust = dclst;
+#if _FS_EXFAT
+						if (fs->fs_type == FS_EXFAT) {
+							sdj.obj.objsize = obj.objsize;
+							sdj.obj.stat = obj.stat;
+						}
+#endif
+						res = dir_sdi(&sdj, 0);
+						if (res == FR_OK) {
+							res = dir_read(&sdj, 0);			/* Read an item */
+							if (res == FR_OK) res = FR_DENIED;	/* Not empty? */
+							if (res == FR_NO_FILE) res = FR_OK;	/* Empty? */
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&dj);			/* Remove the directory entry */
+				if (res == FR_OK && dclst) {	/* Remove the cluster chain if exist */
+#if _FS_EXFAT
+					res = remove_chain(&obj, dclst, 0);
+#else
+					res = remove_chain(&dj.obj, dclst, 0);
+#endif
+				}
+				if (res == FR_OK) res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory                                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+	const TCHAR* path		/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	BYTE *dir;
+	UINT n;
+	DWORD dsc, dcl, pcl, tm;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, FA_WRITE);
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);			/* Follow the file path */
+		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
+		if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) {
+			res = FR_INVALID_NAME;
+		}
+		if (res == FR_NO_FILE) {				/* Can create a new directory */
+			dcl = create_chain(&dj.obj, 0);		/* Allocate a cluster for the new directory table */
+			dj.obj.objsize = (DWORD)fs->csize * SS(fs);
+			res = FR_OK;
+			if (dcl == 0) res = FR_DENIED;		/* No space to allocate a new cluster */
+			if (dcl == 1) res = FR_INT_ERR;
+			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+			if (res == FR_OK) res = sync_window(fs);	/* Flush FAT */
+			tm = GET_FATTIME();
+			if (res == FR_OK) {					/* Initialize the new directory table */
+				dsc = clust2sect(fs, dcl);
+				dir = fs->win;
+				mem_set(dir, 0, SS(fs));
+				if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+					mem_set(dir + DIR_Name, ' ', 11);	/* Create "." entry */
+					dir[DIR_Name] = '.';
+					dir[DIR_Attr] = AM_DIR;
+					st_dword(dir + DIR_ModTime, tm);
+					st_clust(fs, dir, dcl);
+					mem_cpy(dir + SZDIRE, dir, SZDIRE); 	/* Create ".." entry */
+					dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust;
+					if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0;
+					st_clust(fs, dir + SZDIRE, pcl);
+				}
+				for (n = fs->csize; n; n--) {	/* Write dot entries and clear following sectors */
+					fs->winsect = dsc++;
+					fs->wflag = 1;
+					res = sync_window(fs);
+					if (res != FR_OK) break;
+					mem_set(dir, 0, SS(fs));
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_register(&dj);	/* Register the object to the directoy */
+			}
+			if (res == FR_OK) {
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {	/* Initialize directory entry block */
+					st_dword(fs->dirbuf + XDIR_ModTime, tm);	/* Created time */
+					st_dword(fs->dirbuf + XDIR_FstClus, dcl);	/* Table start cluster */
+					st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)dj.obj.objsize);	/* File size needs to be valid */
+					st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)dj.obj.objsize);
+					fs->dirbuf[XDIR_GenFlags] = 3;				/* Initialize the object flag (contiguous) */
+					fs->dirbuf[XDIR_Attr] = AM_DIR;				/* Attribute */
+					res = store_xdir(&dj);
+				} else
+#endif
+				{
+					dir = dj.dir;
+					st_dword(dir + DIR_ModTime, tm);	/* Created time */
+					st_clust(fs, dir, dcl);				/* Table start cluster */
+					dir[DIR_Attr] = AM_DIR;				/* Attribute */
+					fs->wflag = 1;
+				}
+				if (res == FR_OK) {
+					res = sync_fs(fs);
+				}
+			} else {
+				remove_chain(&dj.obj, dcl, 0);		/* Could not register, remove cluster chain */
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Rename a File/Directory                                               */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+	const TCHAR* path_old,	/* Pointer to the object name to be renamed */
+	const TCHAR* path_new	/* Pointer to the new name */
+)
+{
+	FRESULT res;
+	DIR djo, djn;
+	FATFS *fs;
+	BYTE buf[_FS_EXFAT ? SZDIRE * 2 : 24], *dir;
+	DWORD dw;
+	DEF_NAMBUF
+
+
+	get_ldnumber(&path_new);						/* Snip drive number of new name off */
+	res = find_volume(&path_old, &fs, FA_WRITE);	/* Get logical drive of the old object */
+	if (res == FR_OK) {
+		djo.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&djo, path_old);		/* Check old object */
+		if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check validity of name */
+#if _FS_LOCK != 0
+		if (res == FR_OK) {
+			res = chk_lock(&djo, 2);
+		}
+#endif
+		if (res == FR_OK) {						/* Object to be renamed is found */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {	/* At exFAT */
+				BYTE nf, nn;
+				WORD nh;
+
+				mem_cpy(buf, fs->dirbuf, SZDIRE * 2);	/* Save 85+C0 entry of old object */
+				mem_cpy(&djn, &djo, sizeof djo);
+				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+				}
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+						nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName];
+						nh = ld_word(fs->dirbuf + XDIR_NameHash);
+						mem_cpy(fs->dirbuf, buf, SZDIRE * 2);
+						fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn;
+						st_word(fs->dirbuf + XDIR_NameHash, nh);
+/* Start of critical section where an interruption can cause a cross-link */
+						res = store_xdir(&djn);
+					}
+				}
+			} else
+#endif
+			{	/* At FAT12/FAT16/FAT32 */
+				mem_cpy(buf, djo.dir + DIR_Attr, 21);	/* Save information about the object except name */
+				mem_cpy(&djn, &djo, sizeof (DIR));		/* Duplicate the directory object */
+				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+				}
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+						dir = djn.dir;					/* Copy information about object except name */
+						mem_cpy(dir + 13, buf + 2, 19);
+						dir[DIR_Attr] = buf[0] | AM_ARC;
+						fs->wflag = 1;
+						if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) {	/* Update .. entry in the sub-directory if needed */
+							dw = clust2sect(fs, ld_clust(fs, dir));
+							if (!dw) {
+								res = FR_INT_ERR;
+							} else {
+/* Start of critical section where an interruption can cause a cross-link */
+								res = move_window(fs, dw);
+								dir = fs->win + SZDIRE * 1;	/* Ptr to .. entry */
+								if (res == FR_OK && dir[1] == '.') {
+									st_clust(fs, dir, djn.obj.sclust);
+									fs->wflag = 1;
+								}
+							}
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&djo);		/* Remove old entry */
+				if (res == FR_OK) {
+					res = sync_fs(fs);
+				}
+			}
+/* End of the critical section */
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _FS_MINIMIZE == 0 */
+#endif /* _FS_MINIMIZE <= 1 */
+#endif /* _FS_MINIMIZE <= 2 */
+
+
+
+#if _USE_CHMOD && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Change Attribute                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+	const TCHAR* path,	/* Pointer to the file path */
+	BYTE attr,			/* Attribute bits */
+	BYTE mask			/* Attribute mask to change */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	res = find_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check object validity */
+		if (res == FR_OK) {
+			mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC;	/* Valid attribute mask */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				res = store_xdir(&dj);
+			} else
+#endif
+			{
+				dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				fs->wflag = 1;
+			}
+			if (res == FR_OK) {
+				res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+	const TCHAR* path,	/* Pointer to the file/directory name */
+	const FILINFO* fno	/* Pointer to the time stamp to be set */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	res = find_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check object validity */
+		if (res == FR_OK) {
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+				res = store_xdir(&dj);
+			} else
+#endif
+			{
+				st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+				fs->wflag = 1;
+			}
+			if (res == FR_OK) {
+				res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif	/* _USE_CHMOD && !_FS_READONLY */
+
+
+
+#if _USE_LABEL
+/*-----------------------------------------------------------------------*/
+/* Get Volume Label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getlabel (
+	const TCHAR* path,	/* Path name of the logical drive number */
+	TCHAR* label,		/* Pointer to a buffer to return the volume label */
+	DWORD* vsn			/* Pointer to a variable to return the volume serial number */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	UINT si, di;
+#if _LFN_UNICODE || _FS_EXFAT
+	WCHAR w;
+#endif
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, 0);
+
+	/* Get volume label */
+	if (res == FR_OK && label) {
+		dj.obj.fs = fs; dj.obj.sclust = 0;	/* Open root directory */
+		res = dir_sdi(&dj, 0);
+		if (res == FR_OK) {
+		 	res = dir_read(&dj, 1);			/* Find a volume label entry */
+		 	if (res == FR_OK) {
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					for (si = di = 0; si < dj.dir[XDIR_NumLabel]; si++) {	/* Extract volume label from 83 entry */
+						w = ld_word(dj.dir + XDIR_Label + si * 2);
+#if _LFN_UNICODE
+						label[di++] = w;
+#else
+						w = ff_convert(w, 0);	/* Unicode -> OEM */
+						if (w == 0) w = '?';	/* Replace wrong character */
+						if (_DF1S && w >= 0x100) label[di++] = (char)(w >> 8);
+						label[di++] = (char)w;
+#endif
+					}
+					label[di] = 0;
+				} else
+#endif
+				{
+					si = di = 0;		/* Extract volume label from AM_VOL entry with code comversion */
+					do {
+#if _LFN_UNICODE
+						w = (si < 11) ? dj.dir[si++] : ' ';
+						if (IsDBCS1(w) && si < 11 && IsDBCS2(dj.dir[si])) {
+							w = w << 8 | dj.dir[si++];
+						}
+						label[di++] = ff_convert(w, 1);	/* OEM -> Unicode */
+#else
+						label[di++] = dj.dir[si++];
+#endif
+					} while (di < 11);
+					do {				/* Truncate trailing spaces */
+						label[di] = 0;
+						if (di == 0) break;
+					} while (label[--di] == ' ');
+				}
+			}
+		}
+		if (res == FR_NO_FILE) {	/* No label entry and return nul string */
+			label[0] = 0;
+			res = FR_OK;
+		}
+	}
+
+	/* Get volume serial number */
+	if (res == FR_OK && vsn) {
+		res = move_window(fs, fs->volbase);
+		if (res == FR_OK) {
+			switch (fs->fs_type) {
+			case FS_EXFAT:
+				di = BPB_VolIDEx; break;
+
+			case FS_FAT32:
+				di = BS_VolID32; break;
+
+			default:
+				di = BS_VolID;
+			}
+			*vsn = ld_dword(fs->win + di);
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Set Volume Label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_setlabel (
+	const TCHAR* label	/* Pointer to the volume label to set */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	BYTE dirvn[22];
+	UINT i, j, slen;
+	WCHAR w;
+	static const char badchr[] = "\"*+,.:;<=>\?[]|\x7F";
+
+
+	/* Get logical drive */
+	res = find_volume(&label, &fs, FA_WRITE);
+	if (res != FR_OK) LEAVE_FF(fs, res);
+	dj.obj.fs = fs;
+
+	/* Get length of given volume label */
+	for (slen = 0; (UINT)label[slen] >= ' '; slen++) ;	/* Get name length */
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		for (i = j = 0; i < slen; ) {	/* Create volume label in directory form */
+			w = label[i++];
+#if !_LFN_UNICODE
+			if (IsDBCS1(w)) {
+				w = (i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0;
+			}
+			w = ff_convert(w, 1);
+#endif
+			if (w == 0 || chk_chr(badchr, w) || j == 22) {	/* Check validity check validity of the volume label */
+				LEAVE_FF(fs, FR_INVALID_NAME);
+			}
+			st_word(dirvn + j, w); j += 2;
+		}
+		slen = j;
+	} else
+#endif
+	{	/* On the FAT12/16/32 volume */
+		for ( ; slen && label[slen - 1] == ' '; slen--) ;	/* Remove trailing spaces */
+		if (slen) {		/* Is there a volume label to be set? */
+			dirvn[0] = 0; i = j = 0;	/* Create volume label in directory form */
+			do {
+#if _LFN_UNICODE
+				w = ff_convert(ff_wtoupper(label[i++]), 0);
+#else
+				w = (BYTE)label[i++];
+				if (IsDBCS1(w)) {
+					w = (j < 10 && i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0;
+				}
+#if _USE_LFN != 0
+				w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0);
+#else
+				if (IsLower(w)) w -= 0x20;			/* To upper ASCII characters */
+#ifdef _EXCVT
+				if (w >= 0x80) w = ExCvt[w - 0x80];	/* To upper extended characters (SBCS cfg) */
+#else
+				if (!_DF1S && w >= 0x80) w = 0;		/* Reject extended characters (ASCII cfg) */
+#endif
+#endif
+#endif
+				if (w == 0 || chk_chr(badchr, w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) {	/* Reject invalid characters for volume label */
+					LEAVE_FF(fs, FR_INVALID_NAME);
+				}
+				if (w >= 0x100) dirvn[j++] = (BYTE)(w >> 8);
+				dirvn[j++] = (BYTE)w;
+			} while (i < slen);
+			while (j < 11) dirvn[j++] = ' ';	/* Fill remaining name field */
+			if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME);	/* Reject illegal name (heading DDEM) */
+		}
+	}
+
+	/* Set volume label */
+	dj.obj.sclust = 0;		/* Open root directory */
+	res = dir_sdi(&dj, 0);
+	if (res == FR_OK) {
+		res = dir_read(&dj, 1);	/* Get volume label entry */
+		if (res == FR_OK) {
+			if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+				dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2);	/* Change the volume label */
+				mem_cpy(dj.dir + XDIR_Label, dirvn, slen);
+			} else {
+				if (slen) {
+					mem_cpy(dj.dir, dirvn, 11);	/* Change the volume label */
+				} else {
+					dj.dir[DIR_Name] = DDEM;	/* Remove the volume label */
+				}
+			}
+			fs->wflag = 1;
+			res = sync_fs(fs);
+		} else {			/* No volume label entry is found or error */
+			if (res == FR_NO_FILE) {
+				res = FR_OK;
+				if (slen) {	/* Create a volume label entry */
+					res = dir_alloc(&dj, 1);	/* Allocate an entry */
+					if (res == FR_OK) {
+						mem_set(dj.dir, 0, SZDIRE);	/* Clear the entry */
+						if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+							dj.dir[XDIR_Type] = 0x83;		/* Create 83 entry */
+							dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2);
+							mem_cpy(dj.dir + XDIR_Label, dirvn, slen);
+						} else {
+							dj.dir[DIR_Attr] = AM_VOL;		/* Create volume label entry */
+							mem_cpy(dj.dir, dirvn, 11);
+						}
+						fs->wflag = 1;
+						res = sync_fs(fs);
+					}
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_LABEL */
+
+
+
+#if _USE_EXPAND && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Allocate a Contiguous Blocks to the File                              */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_expand (
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t fsz,	/* File size to be expanded to */
+	BYTE opt		/* Operation mode 0:Find and prepare or 1:Find and allocate */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD n, clst, stcl, scl, ncl, tcl, lclst;
+
+
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);
+#if _FS_EXFAT
+	if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED);	/* Check if in size limit */
+#endif
+	n = (DWORD)fs->csize * SS(fs);	/* Cluster size */
+	tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0);	/* Number of clusters required */
+	stcl = fs->last_clst; lclst = 0;
+	if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2;
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {
+		scl = find_bitmap(fs, stcl, tcl);			/* Find a contiguous cluster block */
+		if (scl == 0) res = FR_DENIED;				/* No contiguous cluster block was found */
+		if (scl == 0xFFFFFFFF) res = FR_DISK_ERR;
+		if (res == FR_OK) {	/* A contiguous free area is found */
+			if (opt) {		/* Allocate it now */
+				res = change_bitmap(fs, scl, tcl, 1);	/* Mark the cluster block 'in use' */
+				lclst = scl + tcl - 1;
+			} else {		/* Set it as suggested point for next allocation */
+				lclst = scl - 1;
+			}
+		}
+	} else
+#endif
+	{
+		scl = clst = stcl; ncl = 0;
+		for (;;) {	/* Find a contiguous cluster block */
+			n = get_fat(&fp->obj, clst);
+			if (++clst >= fs->n_fatent) clst = 2;
+			if (n == 1) { res = FR_INT_ERR; break; }
+			if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+			if (n == 0) {	/* Is it a free cluster? */
+				if (++ncl == tcl) break;	/* Break if a contiguous cluster block is found */
+			} else {
+				scl = clst; ncl = 0;		/* Not a free cluster */
+			}
+			if (clst == stcl) { res = FR_DENIED; break; }	/* No contiguous cluster? */
+		}
+		if (res == FR_OK) {	/* A contiguous free area is found */
+			if (opt) {		/* Allocate it now */
+				for (clst = scl, n = tcl; n; clst++, n--) {	/* Create a cluster chain on the FAT */
+					res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1);
+					if (res != FR_OK) break;
+					lclst = clst;
+				}
+			} else {		/* Set it as suggested point for next allocation */
+				lclst = scl - 1;
+			}
+		}
+	}
+
+	if (res == FR_OK) {
+		fs->last_clst = lclst;		/* Set suggested start cluster to start next */
+		if (opt) {	/* Is it allocated now? */
+			fp->obj.sclust = scl;		/* Update object allocation information */
+			fp->obj.objsize = fsz;
+			if (_FS_EXFAT) fp->obj.stat = 2;	/* Set status 'contiguous chain' */
+			fp->flag |= FA_MODIFIED;
+			if (fs->free_clst <= fs->n_fatent - 2) {	/* Update FSINFO */
+				fs->free_clst -= tcl;
+				fs->fsi_flag |= 1;
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* _USE_EXPAND && !_FS_READONLY */
+
+
+
+#if _USE_FORWARD
+/*-----------------------------------------------------------------------*/
+/* Forward data to the stream directly                                   */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_forward (
+	FIL* fp, 						/* Pointer to the file object */
+	UINT (*func)(const BYTE*,UINT),	/* Pointer to the streaming function */
+	UINT btf,						/* Number of bytes to forward */
+	UINT* bf						/* Pointer to number of bytes forwarded */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, sect;
+	FSIZE_t remain;
+	UINT rcnt, csect;
+	BYTE *dbuf;
+
+
+	*bf = 0;	/* Clear transfer byte counter */
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	remain = fp->obj.objsize - fp->fptr;
+	if (btf > remain) btf = (UINT)remain;			/* Truncate btf by remaining bytes */
+
+	for ( ;  btf && (*func)(0, 0);					/* Repeat until all data transferred or stream goes busy */
+		fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) {
+		csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+		if (fp->fptr % SS(fs) == 0) {				/* On the sector boundary? */
+			if (csect == 0) {						/* On the cluster boundary? */
+				clst = (fp->fptr == 0) ?			/* On the top of the file? */
+					fp->obj.sclust : get_fat(&fp->obj, fp->clust);
+				if (clst <= 1) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;					/* Update current cluster */
+			}
+		}
+		sect = clust2sect(fs, fp->clust);			/* Get current data sector */
+		if (!sect) ABORT(fs, FR_INT_ERR);
+		sect += csect;
+#if _FS_TINY
+		if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window to the file data */
+		dbuf = fs->win;
+#else
+		if (fp->sect != sect) {		/* Fill sector cache with file data */
+#if !_FS_READONLY
+			if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+		}
+		dbuf = fp->buf;
+#endif
+		fp->sect = sect;
+		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+		if (rcnt > btf) rcnt = btf;					/* Clip it by btr if needed */
+		rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt);	/* Forward the file data */
+		if (!rcnt) ABORT(fs, FR_INT_ERR);
+	}
+
+	LEAVE_FF(fs, FR_OK);
+}
+#endif /* _USE_FORWARD */
+
+
+
+#if _USE_MKFS && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Create an FAT/exFAT volume                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkfs (
+	const TCHAR* path,	/* Logical drive number */
+	BYTE opt,			/* Format option */
+	DWORD au,			/* Size of allocation unit (cluster) [byte] */
+	void* work,			/* Pointer to working buffer */
+	UINT len			/* Size of working buffer */
+)
+{
+	const UINT n_fats = 1;		/* Number of FATs for FAT12/16/32 volume (1 or 2) */
+	const UINT n_rootdir = 512;	/* Number of root directory entries for FAT12/16 volume */
+	static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0};	/* Cluster size boundary for FAT12/16 volume (4Ks unit) */
+	static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0};	/* Cluster size boundary for FAT32 volume (128Ks unit) */
+	BYTE fmt, sys, *buf, *pte, pdrv, part;
+	WORD ss;
+	DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n;
+	DWORD b_vol, b_fat, b_data;				/* Base LBA for volume, fat, data */
+	DWORD sz_vol, sz_rsv, sz_fat, sz_dir;	/* Size for volume, fat, dir, data */
+	UINT i;
+	int vol;
+	DSTATUS stat;
+#if _USE_TRIM || _FS_EXFAT
+	DWORD tbl[3];
+#endif
+
+
+	/* Check mounted drive and clear work area */
+	vol = get_ldnumber(&path);					/* Get target logical drive */
+	if (vol < 0) return FR_INVALID_DRIVE;
+	if (FatFs[vol]) FatFs[vol]->fs_type = 0;	/* Clear the volume */
+	pdrv = LD2PD(vol);	/* Physical drive */
+	part = LD2PT(vol);	/* Partition (0:create as new, 1-4:get from partition table) */
+
+	/* Check physical drive status */
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & (sz_blk - 1))) sz_blk = 1;	/* Erase block to align data area */
+#if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR;
+	if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+#else
+	ss = _MAX_SS;
+#endif
+	if ((au != 0 && au < ss) || au > 0x1000000 || (au & (au - 1))) return FR_INVALID_PARAMETER;	/* Check if au is valid */
+	au /= ss;	/* Cluster size in unit of sector */
+
+	/* Get working buffer */
+	buf = (BYTE*)work;		/* Working buffer */
+	sz_buf = len / ss;		/* Size of working buffer (sector) */
+	szb_buf = sz_buf * ss;	/* Size of working buffer (byte) */
+	if (!szb_buf) return FR_MKFS_ABORTED;
+
+	/* Determine where the volume to be located (b_vol, sz_vol) */
+	if (_MULTI_PARTITION && part != 0) {
+		/* Get partition information from partition table in the MBR */
+		if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Load MBR */
+		if (ld_word(buf + BS_55AA) != 0xAA55) return FR_MKFS_ABORTED;	/* Check if MBR is valid */
+		pte = buf + (MBR_Table + (part - 1) * SZ_PTE);
+		if (!pte[PTE_System]) return FR_MKFS_ABORTED;	/* No partition? */
+		b_vol = ld_dword(pte + PTE_StLba);		/* Get volume start sector */
+		sz_vol = ld_dword(pte + PTE_SizLba);	/* Get volume size */
+	} else {
+		/* Create a single-partition in this function */
+		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) return FR_DISK_ERR;
+		b_vol = (opt & FM_SFD) ? 0 : 63;		/* Volume start sector */
+		if (sz_vol < b_vol) return FR_MKFS_ABORTED;
+		sz_vol -= b_vol;						/* Volume size */
+	}
+	if (sz_vol < 128) return FR_MKFS_ABORTED;	/* Check if volume size is >=128s */
+
+	/* Pre-determine the FAT type */
+	do {
+		if (_FS_EXFAT && (opt & FM_EXFAT)) {	/* exFAT possible? */
+			if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) {	/* exFAT only, vol >= 64Ms or au > 128s ? */
+				fmt = FS_EXFAT; break;
+			}
+		}
+		if (au > 128) return FR_INVALID_PARAMETER;	/* Too large au for FAT/FAT32 */
+		if (opt & FM_FAT32) {	/* FAT32 possible? */
+			if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) {	/* FAT32 only or no-FAT? */
+				fmt = FS_FAT32; break;
+			}
+		}
+		if (!(opt & FM_FAT)) return FR_INVALID_PARAMETER;	/* no-FAT? */
+		fmt = FS_FAT16;
+	} while (0);
+
+#if _FS_EXFAT
+	if (fmt == FS_EXFAT) {	/* Create an exFAT volume */
+		DWORD szb_bit, szb_case, sum, nb, cl;
+		WCHAR ch, si;
+		UINT j, st;
+		BYTE b;
+
+		if (sz_vol < 0x1000) return FR_MKFS_ABORTED;	/* Too small volume? */
+#if _USE_TRIM
+		tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1;	/* Inform the device the volume area may be erased */
+		disk_ioctl(pdrv, CTRL_TRIM, tbl);
+#endif
+		/* Determine FAT location, data location and number of clusters */
+		if (!au) {	/* au auto-selection */
+			au = 8;
+			if (sz_vol >= 0x80000) au = 64;		/* >= 512Ks */
+			if (sz_vol >= 0x4000000) au = 256;	/* >= 64Ms */
+		}
+		b_fat = b_vol + 32;										/* FAT start at offset 32 */
+		sz_fat = ((sz_vol / au + 2) * 4 + ss - 1) / ss;			/* Number of FAT sectors */
+		b_data = (b_fat + sz_fat + sz_blk - 1) & ~(sz_blk - 1);	/* Align data area to the erase block boundary */
+		if (b_data >= sz_vol / 2) return FR_MKFS_ABORTED;		/* Too small volume? */
+		n_clst = (sz_vol - (b_data - b_vol)) / au;				/* Number of clusters */
+		if (n_clst <16) return FR_MKFS_ABORTED;					/* Too few clusters? */
+		if (n_clst > MAX_EXFAT) return FR_MKFS_ABORTED;			/* Too many clusters? */
+
+		szb_bit = (n_clst + 7) / 8;						/* Size of allocation bitmap */
+		tbl[0] = (szb_bit + au * ss - 1) / (au * ss);	/* Number of allocation bitmap clusters */
+
+		/* Create a compressed up-case table */
+		sect = b_data + au * tbl[0];	/* Table start sector */
+		sum = 0;						/* Table checksum to be stored in the 82 entry */
+		st = si = i = j = szb_case = 0;
+		do {
+			switch (st) {
+			case 0:
+				ch = ff_wtoupper(si);	/* Get an up-case char */
+				if (ch != si) {
+					si++; break;		/* Store the up-case char if exist */
+				}
+				for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ;	/* Get run length of no-case block */
+				if (j >= 128) {
+					ch = 0xFFFF; st = 2; break;	/* Compress the no-case block if run is >= 128 */
+				}
+				st = 1;			/* Do not compress short run */
+				/* go to next case */
+			case 1:
+				ch = si++;		/* Fill the short run */
+				if (--j == 0) st = 0;
+				break;
+
+			default:
+				ch = (WCHAR)j; si += j;	/* Number of chars to skip */
+				st = 0;
+			}
+			sum = xsum32(buf[i + 0] = (BYTE)ch, sum);		/* Put it into the write buffer */
+			sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum);
+			i += 2; szb_case += 2;
+			if (!si || i == szb_buf) {		/* Write buffered data when buffer full or end of process */
+				n = (i + ss - 1) / ss;
+				if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+				sect += n; i = 0;
+			}
+		} while (si);
+		tbl[1] = (szb_case + au * ss - 1) / (au * ss);	/* Number of up-case table clusters */
+		tbl[2] = 1;										/* Number of root dir clusters */
+
+		/* Initialize the allocation bitmap */
+		sect = b_data; nsect = (szb_bit + ss - 1) / ss;	/* Start of bitmap and number of sectors */
+		nb = tbl[0] + tbl[1] + tbl[2];					/* Number of clusters in-use by system */
+		do {
+			mem_set(buf, 0, szb_buf);
+			for (i = 0; nb >= 8 && i < szb_buf; buf[i++] = 0xFF, nb -= 8) ;
+			for (b = 1; nb && i < szb_buf; buf[i] |= b, b <<= 1, nb--) ;
+			n = (nsect > sz_buf) ? sz_buf : nsect;		/* Write the buffered data */
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Initialize the FAT */
+		sect = b_fat; nsect = sz_fat;	/* Start of FAT and number of FAT sectors */
+		j = nb = cl = 0;
+		do {
+			mem_set(buf, 0, szb_buf); i = 0;	/* Clear work area and reset write index */
+			if (cl == 0) {	/* Set entry 0 and 1 */
+				st_dword(buf + i, 0xFFFFFFF8); i += 4; cl++;
+				st_dword(buf + i, 0xFFFFFFFF); i += 4; cl++;
+			}
+			do {			/* Create chains of bitmap, up-case and root dir */
+				while (nb && i < szb_buf) {			/* Create a chain */
+					st_dword(buf + i, (nb > 1) ? cl + 1 : 0xFFFFFFFF);
+					i += 4; cl++; nb--;
+				}
+				if (!nb && j < 3) nb = tbl[j++];	/* Next chain */
+			} while (nb && i < szb_buf);
+			n = (nsect > sz_buf) ? sz_buf : nsect;	/* Write the buffered data */
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Initialize the root directory */
+		mem_set(buf, 0, szb_buf);
+		buf[SZDIRE * 0 + 0] = 0x83;		/* 83 entry (volume label) */
+		buf[SZDIRE * 1 + 0] = 0x81;		/* 81 entry (allocation bitmap) */
+		st_dword(buf + SZDIRE * 1 + 20, 2);
+		st_dword(buf + SZDIRE * 1 + 24, szb_bit);
+		buf[SZDIRE * 2 + 0] = 0x82;		/* 82 entry (up-case table) */
+		st_dword(buf + SZDIRE * 2 + 4, sum);
+		st_dword(buf + SZDIRE * 2 + 20, 2 + tbl[0]);
+		st_dword(buf + SZDIRE * 2 + 24, szb_case);
+		sect = b_data + au * (tbl[0] + tbl[1]);	nsect = au;	/* Start of the root directory and number of sectors */
+		do {	/* Fill root directory sectors */
+			n = (nsect > sz_buf) ? sz_buf : nsect;
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+			mem_set(buf, 0, ss);
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Create two set of the exFAT VBR blocks */
+		sect = b_vol;
+		for (n = 0; n < 2; n++) {
+			/* Main record (+0) */
+			mem_set(buf, 0, ss);
+			mem_cpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11);	/* Boot jump code (x86), OEM name */
+			st_dword(buf + BPB_VolOfsEx, b_vol);					/* Volume offset in the physical drive [sector] */
+			st_dword(buf + BPB_TotSecEx, sz_vol);					/* Volume size [sector] */
+			st_dword(buf + BPB_FatOfsEx, b_fat - b_vol);			/* FAT offset [sector] */
+			st_dword(buf + BPB_FatSzEx, sz_fat);					/* FAT size [sector] */
+			st_dword(buf + BPB_DataOfsEx, b_data - b_vol);			/* Data offset [sector] */
+			st_dword(buf + BPB_NumClusEx, n_clst);					/* Number of clusters */
+			st_dword(buf + BPB_RootClusEx, 2 + tbl[0] + tbl[1]);	/* Root dir cluster # */
+			st_dword(buf + BPB_VolIDEx, GET_FATTIME());				/* VSN */
+			st_word(buf + BPB_FSVerEx, 0x100);						/* File system version (1.00) */
+			for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ;	/* Log2 of sector size [byte] */
+			for (buf[BPB_SecPerClusEx] = 0, i = au; i >>= 1; buf[BPB_SecPerClusEx]++) ;	/* Log2 of cluster size [sector] */
+			buf[BPB_NumFATsEx] = 1;					/* Number of FATs */
+			buf[BPB_DrvNumEx] = 0x80;				/* Drive number (for int13) */
+			st_word(buf + BS_BootCodeEx, 0xFEEB);	/* Boot code (x86) */
+			st_word(buf + BS_55AA, 0xAA55);			/* Signature (placed here regardless of sector size) */
+			for (i = sum = 0; i < ss; i++) {		/* VBR checksum */
+				if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum);
+			}
+			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+			/* Extended bootstrap record (+1..+8) */
+			mem_set(buf, 0, ss);
+			st_word(buf + ss - 2, 0xAA55);	/* Signature (placed at end of sector) */
+			for (j = 1; j < 9; j++) {
+				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+			}
+			/* OEM/Reserved record (+9..+10) */
+			mem_set(buf, 0, ss);
+			for ( ; j < 11; j++) {
+				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+			}
+			/* Sum record (+11) */
+			for (i = 0; i < ss; i += 4) st_dword(buf + i, sum);		/* Fill with checksum value */
+			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+		}
+
+	} else
+#endif	/* _FS_EXFAT */
+	{	/* Create an FAT12/16/32 volume */
+		do {
+			pau = au;
+			/* Pre-determine number of clusters and FAT sub-type */
+			if (fmt == FS_FAT32) {	/* FAT32 volume */
+				if (!pau) {	/* au auto-selection */
+					n = sz_vol / 0x20000;	/* Volume size in unit of 128KS */
+					for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+				}
+				n_clst = sz_vol / pau;	/* Number of clusters */
+				sz_fat = (n_clst * 4 + 8 + ss - 1) / ss;	/* FAT size [sector] */
+				sz_rsv = 32;	/* Number of reserved sectors */
+				sz_dir = 0;		/* No static directory */
+				if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) return FR_MKFS_ABORTED;
+			} else {				/* FAT12/16 volume */
+				if (!pau) {	/* au auto-selection */
+					n = sz_vol / 0x1000;	/* Volume size in unit of 4KS */
+					for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+				}
+				n_clst = sz_vol / pau;
+				if (n_clst > MAX_FAT12) {
+					n = n_clst * 2 + 4;		/* FAT size [byte] */
+				} else {
+					fmt = FS_FAT12;
+					n = (n_clst * 3 + 1) / 2 + 3;	/* FAT size [byte] */
+				}
+				sz_fat = (n + ss - 1) / ss;		/* FAT size [sector] */
+				sz_rsv = 1;						/* Number of reserved sectors */
+				sz_dir = (DWORD)n_rootdir * SZDIRE / ss;	/* Rootdir size [sector] */
+			}
+			b_fat = b_vol + sz_rsv;						/* FAT base */
+			b_data = b_fat + sz_fat * n_fats + sz_dir;	/* Data base */
+
+			/* Align data base to erase block boundary (for flash memory media) */
+			n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data;	/* Next nearest erase block from current data base */
+			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
+				sz_rsv += n; b_fat += n;
+			} else {					/* FAT12/16: Expand FAT size */
+				sz_fat += n / n_fats;
+			}
+
+			/* Determine number of clusters and final check of validity of the FAT sub-type */
+			if (sz_vol < b_data + pau * 16 - b_vol) return FR_MKFS_ABORTED;	/* Too small volume */
+			n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau;
+			if (fmt == FS_FAT32) {
+				if (n_clst <= MAX_FAT16) {	/* Too few clusters for FAT32 */
+					if (!au && (au = pau / 2) != 0) continue;	/* Adjust cluster size and retry */
+					return FR_MKFS_ABORTED;
+				}
+			}
+			if (fmt == FS_FAT16) {
+				if (n_clst > MAX_FAT16) {	/* Too many clusters for FAT16 */
+					if (!au && (pau * 2) <= 64) {
+						au = pau * 2; continue;		/* Adjust cluster size and retry */
+					}
+					if ((opt & FM_FAT32)) {
+						fmt = FS_FAT32; continue;	/* Switch type to FAT32 and retry */
+					}
+					if (!au && (au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+					return FR_MKFS_ABORTED;
+				}
+				if  (n_clst <= MAX_FAT12) {	/* Too few clusters for FAT16 */
+					if (!au && (au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+					return FR_MKFS_ABORTED;
+				}
+			}
+			if (fmt == FS_FAT12 && n_clst > MAX_FAT12) return FR_MKFS_ABORTED;	/* Too many clusters for FAT12 */
+
+			/* Ok, it is the valid cluster configuration */
+			break;
+		} while (1);
+
+#if _USE_TRIM
+		tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1;	/* Inform the device the volume area can be erased */
+		disk_ioctl(pdrv, CTRL_TRIM, tbl);
+#endif
+		/* Create FAT VBR */
+		mem_set(buf, 0, ss);
+		mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */
+		st_word(buf + BPB_BytsPerSec, ss);				/* Sector size [byte] */
+		buf[BPB_SecPerClus] = (BYTE)pau;				/* Cluster size [sector] */
+		st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv);	/* Size of reserved area */
+		buf[BPB_NumFATs] = (BYTE)n_fats;				/* Number of FATs */
+		st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir));	/* Number of root directory entries */
+		if (sz_vol < 0x10000) {
+			st_word(buf + BPB_TotSec16, (WORD)sz_vol);	/* Volume size in 16-bit LBA */
+		} else {
+			st_dword(buf + BPB_TotSec32, sz_vol);		/* Volume size in 32-bit LBA */
+		}
+		buf[BPB_Media] = 0xF8;							/* Media descriptor byte */
+		st_word(buf + BPB_SecPerTrk, 63);				/* Number of sectors per track (for int13) */
+		st_word(buf + BPB_NumHeads, 255);				/* Number of heads (for int13) */
+		st_dword(buf + BPB_HiddSec, b_vol);				/* Volume offset in the physical drive [sector] */
+		if (fmt == FS_FAT32) {
+			st_dword(buf + BS_VolID32, GET_FATTIME());	/* VSN */
+			st_dword(buf + BPB_FATSz32, sz_fat);		/* FAT size [sector] */
+			st_dword(buf + BPB_RootClus32, 2);			/* Root directory cluster # (2) */
+			st_word(buf + BPB_FSInfo32, 1);				/* Offset of FSINFO sector (VBR + 1) */
+			st_word(buf + BPB_BkBootSec32, 6);			/* Offset of backup VBR (VBR + 6) */
+			buf[BS_DrvNum32] = 0x80;					/* Drive number (for int13) */
+			buf[BS_BootSig32] = 0x29;					/* Extended boot signature */
+			mem_cpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+		} else {
+			st_dword(buf + BS_VolID, GET_FATTIME());	/* VSN */
+			st_word(buf + BPB_FATSz16, (WORD)sz_fat);	/* FAT size [sector] */
+			buf[BS_DrvNum] = 0x80;						/* Drive number (for int13) */
+			buf[BS_BootSig] = 0x29;						/* Extended boot signature */
+			mem_cpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+		}
+		st_word(buf + BS_55AA, 0xAA55);					/* Signature (offset is fixed here regardless of sector size) */
+		if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the VBR sector */
+
+		/* Create FSINFO record if needed */
+		if (fmt == FS_FAT32) {
+			disk_write(pdrv, buf, b_vol + 6, 1);		/* Write backup VBR (VBR + 6) */
+			mem_set(buf, 0, ss);
+			st_dword(buf + FSI_LeadSig, 0x41615252);
+			st_dword(buf + FSI_StrucSig, 0x61417272);
+			st_dword(buf + FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
+			st_dword(buf + FSI_Nxt_Free, 2);			/* Last allocated cluster# */
+			st_word(buf + BS_55AA, 0xAA55);
+			disk_write(pdrv, buf, b_vol + 7, 1);		/* Write backup FSINFO (VBR + 7) */
+			disk_write(pdrv, buf, b_vol + 1, 1);		/* Write original FSINFO (VBR + 1) */
+		}
+
+		/* Initialize FAT area */
+		mem_set(buf, 0, (UINT)szb_buf);
+		sect = b_fat;		/* FAT start sector */
+		for (i = 0; i < n_fats; i++) {			/* Initialize FATs each */
+			if (fmt == FS_FAT32) {
+				st_dword(buf + 0, 0xFFFFFFF8);	/* Entry 0 */
+				st_dword(buf + 4, 0xFFFFFFFF);	/* Entry 1 */
+				st_dword(buf + 8, 0x0FFFFFFF);	/* Entry 2 (root directory) */
+			} else {
+				st_dword(buf + 0, (fmt == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8);	/* Entry 0 and 1 */
+			}
+			nsect = sz_fat;		/* Number of FAT sectors */
+			do {	/* Fill FAT sectors */
+				n = (nsect > sz_buf) ? sz_buf : nsect;
+				if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+				mem_set(buf, 0, ss);
+				sect += n; nsect -= n;
+			} while (nsect);
+		}
+
+		/* Initialize root directory (fill with zero) */
+		nsect = (fmt == FS_FAT32) ? pau : sz_dir;	/* Number of root directory sectors */
+		do {
+			n = (nsect > sz_buf) ? sz_buf : nsect;
+			if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+			sect += n; nsect -= n;
+		} while (nsect);
+	}
+
+	/* Determine system ID in the partition table */
+	if (_FS_EXFAT && fmt == FS_EXFAT) {
+		sys = 0x07;			/* HPFS/NTFS/exFAT */
+	} else {
+		if (fmt == FS_FAT32) {
+			sys = 0x0C;		/* FAT32X */
+		} else {
+			if (sz_vol >= 0x10000) {
+				sys = 0x06;	/* FAT12/16 (>=64KS) */
+			} else {
+				sys = (fmt == FS_FAT16) ? 0x04 : 0x01;	/* FAT16 (<64KS) : FAT12 (<64KS) */
+			}
+		}
+	}
+
+	/* Update partition information */
+	if (_MULTI_PARTITION && part != 0) {	/* Created in the existing partition */
+		/* Update system ID in the partition table */
+		if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Read the MBR */
+		buf[MBR_Table + (part - 1) * SZ_PTE + PTE_System] = sys;		/* Set system ID */
+		if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Write it back to the MBR */
+	} else {								/* Created as a new single partition */
+		if (!(opt & FM_SFD)) {	/* Create partition table if in FDISK format */
+			mem_set(buf, 0, ss);
+			st_word(buf + BS_55AA, 0xAA55);		/* MBR signature */
+			pte = buf + MBR_Table;				/* Create partition table for single partition in the drive */
+			pte[PTE_Boot] = 0;					/* Boot indicator */
+			pte[PTE_StHead] = 1;				/* Start head */
+			pte[PTE_StSec] = 1;					/* Start sector */
+			pte[PTE_StCyl] = 0;					/* Start cylinder */
+			pte[PTE_System] = sys;				/* System type */
+			n = (b_vol + sz_vol) / (63 * 255);	/* (End CHS may be invalid) */
+			pte[PTE_EdHead] = 254;				/* End head */
+			pte[PTE_EdSec] = (BYTE)(n >> 2 | 63);	/* End sector */
+			pte[PTE_EdCyl] = (BYTE)n;			/* End cylinder */
+			st_dword(pte + PTE_StLba, b_vol);	/* Start offset in LBA */
+			st_dword(pte + PTE_SizLba, sz_vol);	/* Size in sectors */
+			if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the MBR */
+		}
+	}
+
+	if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) return FR_DISK_ERR;
+
+	return FR_OK;
+}
+
+
+
+#if _MULTI_PARTITION
+/*-----------------------------------------------------------------------*/
+/* Create partition table on the physical drive                          */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_fdisk (
+	BYTE pdrv,			/* Physical drive number */
+	const DWORD* szt,	/* Pointer to the size table for each partitions */
+	void* work			/* Pointer to the working buffer */
+)
+{
+	UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
+	BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
+	DSTATUS stat;
+	DWORD sz_disk, sz_part, s_part;
+
+
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+	if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
+
+	/* Determine the CHS without any consideration of the drive geometry */
+	for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
+	if (n == 256) n--;
+	e_hd = n - 1;
+	sz_cyl = 63 * n;
+	tot_cyl = sz_disk / sz_cyl;
+
+	/* Create partition table */
+	mem_set(buf, 0, _MAX_SS);
+	p = buf + MBR_Table; b_cyl = 0;
+	for (i = 0; i < 4; i++, p += SZ_PTE) {
+		p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl;	/* Number of cylinders */
+		if (!p_cyl) continue;
+		s_part = (DWORD)sz_cyl * b_cyl;
+		sz_part = (DWORD)sz_cyl * p_cyl;
+		if (i == 0) {	/* Exclude first track of cylinder 0 */
+			s_hd = 1;
+			s_part += 63; sz_part -= 63;
+		} else {
+			s_hd = 0;
+		}
+		e_cyl = b_cyl + p_cyl - 1;	/* End cylinder */
+		if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER;
+
+		/* Set partition table */
+		p[1] = s_hd;						/* Start head */
+		p[2] = (BYTE)((b_cyl >> 2) + 1);	/* Start sector */
+		p[3] = (BYTE)b_cyl;					/* Start cylinder */
+		p[4] = 0x07;						/* System type (temporary setting) */
+		p[5] = e_hd;						/* End head */
+		p[6] = (BYTE)((e_cyl >> 2) + 63);	/* End sector */
+		p[7] = (BYTE)e_cyl;					/* End cylinder */
+		st_dword(p + 8, s_part);			/* Start sector in LBA */
+		st_dword(p + 12, sz_part);			/* Number of sectors */
+
+		/* Next partition */
+		b_cyl += p_cyl;
+	}
+	st_word(p, 0xAA55);
+
+	/* Write it to the MBR */
+	return (disk_write(pdrv, buf, 0, 1) != RES_OK || disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) ? FR_DISK_ERR : FR_OK;
+}
+
+#endif /* _MULTI_PARTITION */
+#endif /* _USE_MKFS && !_FS_READONLY */
+
+
+
+
+#if _USE_STRFUNC
+/*-----------------------------------------------------------------------*/
+/* Get a string from the file                                            */
+/*-----------------------------------------------------------------------*/
+
+TCHAR* f_gets (
+	TCHAR* buff,	/* Pointer to the string buffer to read */
+	int len,		/* Size of string buffer (characters) */
+	FIL* fp			/* Pointer to the file object */
+)
+{
+	int n = 0;
+	TCHAR c, *p = buff;
+	BYTE s[2];
+	UINT rc;
+
+
+	while (n < len - 1) {	/* Read characters until buffer gets filled */
+#if _LFN_UNICODE
+#if _STRF_ENCODE == 3		/* Read a character in UTF-8 */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+		if (c >= 0x80) {
+			if (c < 0xC0) continue;	/* Skip stray trailer */
+			if (c < 0xE0) {			/* Two-byte sequence (0x80-0x7FF) */
+				f_read(fp, s, 1, &rc);
+				if (rc != 1) break;
+				c = (c & 0x1F) << 6 | (s[0] & 0x3F);
+				if (c < 0x80) c = '?';	/* Reject invalid code range */
+			} else {
+				if (c < 0xF0) {		/* Three-byte sequence (0x800-0xFFFF) */
+					f_read(fp, s, 2, &rc);
+					if (rc != 2) break;
+					c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F);
+					if (c < 0x800) c = '?';	/* Reject invalid code range */
+				} else {			/* Reject four-byte sequence */
+					c = '?';
+				}
+			}
+		}
+#elif _STRF_ENCODE == 2		/* Read a character in UTF-16BE */
+		f_read(fp, s, 2, &rc);
+		if (rc != 2) break;
+		c = s[1] + (s[0] << 8);
+#elif _STRF_ENCODE == 1		/* Read a character in UTF-16LE */
+		f_read(fp, s, 2, &rc);
+		if (rc != 2) break;
+		c = s[0] + (s[1] << 8);
+#else						/* Read a character in ANSI/OEM */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+		if (IsDBCS1(c)) {
+			f_read(fp, s, 1, &rc);
+			if (rc != 1) break;
+			c = (c << 8) + s[0];
+		}
+		c = ff_convert(c, 1);	/* OEM -> Unicode */
+		if (!c) c = '?';
+#endif
+#else						/* Read a character without conversion */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+#endif
+		if (_USE_STRFUNC == 2 && c == '\r') continue;	/* Strip '\r' */
+		*p++ = c;
+		n++;
+		if (c == '\n') break;		/* Break on EOL */
+	}
+	*p = 0;
+	return n ? buff : 0;			/* When no data read (eof or error), return with error. */
+}
+
+
+
+
+#if !_FS_READONLY
+#include 
+/*-----------------------------------------------------------------------*/
+/* Put a character to the file                                           */
+/*-----------------------------------------------------------------------*/
+
+typedef struct {
+	FIL *fp;		/* Ptr to the writing file */
+	int idx, nchr;	/* Write index of buf[] (-1:error), number of chars written */
+	BYTE buf[64];	/* Write buffer */
+} putbuff;
+
+
+static
+void putc_bfd (		/* Buffered write with code conversion */
+	putbuff* pb,
+	TCHAR c
+)
+{
+	UINT bw;
+	int i;
+
+
+	if (_USE_STRFUNC == 2 && c == '\n') {	 /* LF -> CRLF conversion */
+		putc_bfd(pb, '\r');
+	}
+
+	i = pb->idx;		/* Write index of pb->buf[] */
+	if (i < 0) return;
+
+#if _LFN_UNICODE
+#if _STRF_ENCODE == 3			/* Write a character in UTF-8 */
+	if (c < 0x80) {				/* 7-bit */
+		pb->buf[i++] = (BYTE)c;
+	} else {
+		if (c < 0x800) {		/* 11-bit */
+			pb->buf[i++] = (BYTE)(0xC0 | c >> 6);
+		} else {				/* 16-bit */
+			pb->buf[i++] = (BYTE)(0xE0 | c >> 12);
+			pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F));
+		}
+		pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F));
+	}
+#elif _STRF_ENCODE == 2			/* Write a character in UTF-16BE */
+	pb->buf[i++] = (BYTE)(c >> 8);
+	pb->buf[i++] = (BYTE)c;
+#elif _STRF_ENCODE == 1			/* Write a character in UTF-16LE */
+	pb->buf[i++] = (BYTE)c;
+	pb->buf[i++] = (BYTE)(c >> 8);
+#else							/* Write a character in ANSI/OEM */
+	c = ff_convert(c, 0);	/* Unicode -> OEM */
+	if (!c) c = '?';
+	if (c >= 0x100)
+		pb->buf[i++] = (BYTE)(c >> 8);
+	pb->buf[i++] = (BYTE)c;
+#endif
+#else							/* Write a character without conversion */
+	pb->buf[i++] = (BYTE)c;
+#endif
+
+	if (i >= (int)(sizeof pb->buf) - 3) {	/* Write buffered characters to the file */
+		f_write(pb->fp, pb->buf, (UINT)i, &bw);
+		i = (bw == (UINT)i) ? 0 : -1;
+	}
+	pb->idx = i;
+	pb->nchr++;
+}
+
+
+static
+int putc_flush (		/* Flush left characters in the buffer */
+	putbuff* pb
+)
+{
+	UINT nw;
+
+	if (   pb->idx >= 0	/* Flush buffered characters to the file */
+		&& f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
+		&& (UINT)pb->idx == nw) return pb->nchr;
+	return EOF;
+}
+
+
+static
+void putc_init (		/* Initialize write buffer */
+	putbuff* pb,
+	FIL* fp
+)
+{
+	pb->fp = fp;
+	pb->nchr = pb->idx = 0;
+}
+
+
+
+int f_putc (
+	TCHAR c,	/* A character to be output */
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	putbuff pb;
+
+
+	putc_init(&pb, fp);
+	putc_bfd(&pb, c);	/* Put the character */
+	return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a string to the file                                              */
+/*-----------------------------------------------------------------------*/
+
+int f_puts (
+	const TCHAR* str,	/* Pointer to the string to be output */
+	FIL* fp				/* Pointer to the file object */
+)
+{
+	putbuff pb;
+
+
+	putc_init(&pb, fp);
+	while (*str) putc_bfd(&pb, *str++);		/* Put the string */
+	return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a formatted string to the file                                    */
+/*-----------------------------------------------------------------------*/
+
+int f_printf (
+	FIL* fp,			/* Pointer to the file object */
+	const TCHAR* fmt,	/* Pointer to the format string */
+	...					/* Optional arguments... */
+)
+{
+	va_list arp;
+	putbuff pb;
+	BYTE f, r;
+	UINT i, j, w;
+	DWORD v;
+	TCHAR c, d, str[32], *p;
+
+
+	putc_init(&pb, fp);
+
+	va_start(arp, fmt);
+
+	for (;;) {
+		c = *fmt++;
+		if (c == 0) break;			/* End of string */
+		if (c != '%') {				/* Non escape character */
+			putc_bfd(&pb, c);
+			continue;
+		}
+		w = f = 0;
+		c = *fmt++;
+		if (c == '0') {				/* Flag: '0' padding */
+			f = 1; c = *fmt++;
+		} else {
+			if (c == '-') {			/* Flag: left justified */
+				f = 2; c = *fmt++;
+			}
+		}
+		while (IsDigit(c)) {		/* Precision */
+			w = w * 10 + c - '0';
+			c = *fmt++;
+		}
+		if (c == 'l' || c == 'L') {	/* Prefix: Size is long int */
+			f |= 4; c = *fmt++;
+		}
+		if (!c) break;
+		d = c;
+		if (IsLower(d)) d -= 0x20;
+		switch (d) {				/* Type is... */
+		case 'S' :					/* String */
+			p = va_arg(arp, TCHAR*);
+			for (j = 0; p[j]; j++) ;
+			if (!(f & 2)) {
+				while (j++ < w) putc_bfd(&pb, ' ');
+			}
+			while (*p) putc_bfd(&pb, *p++);
+			while (j++ < w) putc_bfd(&pb, ' ');
+			continue;
+
+		case 'C' :					/* Character */
+			putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue;
+
+		case 'B' :					/* Binary */
+			r = 2; break;
+
+		case 'O' :					/* Octal */
+			r = 8; break;
+
+		case 'D' :					/* Signed decimal */
+		case 'U' :					/* Unsigned decimal */
+			r = 10; break;
+
+		case 'X' :					/* Hexdecimal */
+			r = 16; break;
+
+		default:					/* Unknown type (pass-through) */
+			putc_bfd(&pb, c); continue;
+		}
+
+		/* Get an argument and put it in numeral */
+		v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int));
+		if (d == 'D' && (v & 0x80000000)) {
+			v = 0 - v;
+			f |= 8;
+		}
+		i = 0;
+		do {
+			d = (TCHAR)(v % r); v /= r;
+			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+			str[i++] = d + '0';
+		} while (v && i < sizeof str / sizeof str[0]);
+		if (f & 8) str[i++] = '-';
+		j = i; d = (f & 1) ? '0' : ' ';
+		while (!(f & 2) && j++ < w) putc_bfd(&pb, d);
+		do {
+			putc_bfd(&pb, str[--i]);
+		} while (i);
+		while (j++ < w) putc_bfd(&pb, d);
+	}
+
+	va_end(arp);
+
+	return putc_flush(&pb);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_STRFUNC */
diff --git a/Middlewares/Third_Party/FatFs/src/ff.h b/Middlewares/Third_Party/FatFs/src/ff.h
new file mode 100644
index 0000000..a233e16
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff.h
@@ -0,0 +1,361 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT file system module  R0.12c                             /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2017, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+
+
+#ifndef _FATFS
+#define _FATFS	68300	/* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "integer.h"	/* Basic integer types */
+#include "ffconf.h"		/* FatFs configuration options */
+
+#if _FATFS != _FFCONF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if _MULTI_PARTITION		/* Multiple partition configuration */
+typedef struct {
+	BYTE pd;	/* Physical drive number */
+	BYTE pt;	/* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[];	/* Volume - Partition resolution table */
+#endif
+
+
+
+/* Type of path name strings on FatFs API */
+
+#if _LFN_UNICODE			/* Unicode (UTF-16) string */
+#if _USE_LFN == 0
+#error _LFN_UNICODE must be 0 at non-LFN cfg.
+#endif
+#ifndef _INC_TCHAR
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#endif
+#else						/* ANSI/OEM string */
+#ifndef _INC_TCHAR
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+#endif
+
+
+
+/* Type of file size variables */
+
+#if _FS_EXFAT
+#if _USE_LFN == 0
+#error LFN must be enabled when enable exFAT
+#endif
+typedef QWORD FSIZE_t;
+#else
+typedef DWORD FSIZE_t;
+#endif
+
+
+
+/* File system object structure (FATFS) */
+
+typedef struct {
+	BYTE	fs_type;		/* File system type (0:N/A) */
+	BYTE	drv;			/* Physical drive number */
+	BYTE	n_fats;			/* Number of FATs (1 or 2) */
+	BYTE	wflag;			/* win[] flag (b0:dirty) */
+	BYTE	fsi_flag;		/* FSINFO flags (b7:disabled, b0:dirty) */
+	WORD	id;				/* File system mount ID */
+	WORD	n_rootdir;		/* Number of root directory entries (FAT12/16) */
+	WORD	csize;			/* Cluster size [sectors] */
+#if _MAX_SS != _MIN_SS
+	WORD	ssize;			/* Sector size (512, 1024, 2048 or 4096) */
+#endif
+#if _USE_LFN != 0
+	WCHAR*	lfnbuf;			/* LFN working buffer */
+#endif
+#if _FS_EXFAT
+	BYTE*	dirbuf;			/* Directory entry block scratchpad buffer */
+#endif
+#if _FS_REENTRANT
+	_SYNC_t	sobj;			/* Identifier of sync object */
+#endif
+#if !_FS_READONLY
+	DWORD	last_clst;		/* Last allocated cluster */
+	DWORD	free_clst;		/* Number of free clusters */
+#endif
+#if _FS_RPATH != 0
+	DWORD	cdir;			/* Current directory start cluster (0:root) */
+#if _FS_EXFAT
+	DWORD	cdc_scl;		/* Containing directory start cluster (invalid when cdir is 0) */
+	DWORD	cdc_size;		/* b31-b8:Size of containing directory, b7-b0: Chain status */
+	DWORD	cdc_ofs;		/* Offset in the containing directory (invalid when cdir is 0) */
+#endif
+#endif
+	DWORD	n_fatent;		/* Number of FAT entries (number of clusters + 2) */
+	DWORD	fsize;			/* Size of an FAT [sectors] */
+	DWORD	volbase;		/* Volume base sector */
+	DWORD	fatbase;		/* FAT base sector */
+	DWORD	dirbase;		/* Root directory base sector/cluster */
+	DWORD	database;		/* Data base sector */
+	DWORD	winsect;		/* Current sector appearing in the win[] */
+	BYTE	win[_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */
+} FATFS;
+
+
+
+/* Object ID and allocation information (_FDID) */
+
+typedef struct {
+	FATFS*	fs;			/* Pointer to the owner file system object */
+	WORD	id;			/* Owner file system mount ID */
+	BYTE	attr;		/* Object attribute */
+	BYTE	stat;		/* Object chain status (b1-0: =0:not contiguous, =2:contiguous (no data on FAT), =3:flagmented in this session, b2:sub-directory stretched) */
+	DWORD	sclust;		/* Object start cluster (0:no cluster or root directory) */
+	FSIZE_t	objsize;	/* Object size (valid when sclust != 0) */
+#if _FS_EXFAT
+	DWORD	n_cont;		/* Size of first fragment, clusters - 1 (valid when stat == 3) */
+	DWORD	n_frag;		/* Size of last fragment needs to be written (valid when not zero) */
+	DWORD	c_scl;		/* Containing directory start cluster (valid when sclust != 0) */
+	DWORD	c_size;		/* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
+	DWORD	c_ofs;		/* Offset in the containing directory (valid when sclust != 0 and non-directory object) */
+#endif
+#if _FS_LOCK != 0
+	UINT	lockid;		/* File lock ID origin from 1 (index of file semaphore table Files[]) */
+#endif
+} _FDID;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+	_FDID	obj;			/* Object identifier (must be the 1st member to detect invalid object pointer) */
+	BYTE	flag;			/* File status flags */
+	BYTE	err;			/* Abort flag (error code) */
+	FSIZE_t	fptr;			/* File read/write pointer (Zeroed on file open) */
+	DWORD	clust;			/* Current cluster of fpter (invalid when fptr is 0) */
+	DWORD	sect;			/* Sector number appearing in buf[] (0:invalid) */
+#if !_FS_READONLY
+	DWORD	dir_sect;		/* Sector number containing the directory entry */
+	BYTE*	dir_ptr;		/* Pointer to the directory entry in the win[] */
+#endif
+#if _USE_FASTSEEK
+	DWORD*	cltbl;			/* Pointer to the cluster link map table (nulled on open, set by application) */
+#endif
+#if !_FS_TINY
+	BYTE	buf[_MAX_SS];	/* File private data read/write window */
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+	_FDID	obj;			/* Object identifier */
+	DWORD	dptr;			/* Current read/write offset */
+	DWORD	clust;			/* Current cluster */
+	DWORD	sect;			/* Current sector (0:Read operation has terminated) */
+	BYTE*	dir;			/* Pointer to the directory item in the win[] */
+	BYTE	fn[12];			/* SFN (in/out) {body[8],ext[3],status[1]} */
+#if _USE_LFN != 0
+	DWORD	blk_ofs;		/* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
+#endif
+#if _USE_FIND
+	const TCHAR* pat;		/* Pointer to the name matching pattern */
+#endif
+} DIR;
+
+
+
+/* File information structure (FILINFO) */
+
+typedef struct {
+	FSIZE_t	fsize;			/* File size */
+	WORD	fdate;			/* Modified date */
+	WORD	ftime;			/* Modified time */
+	BYTE	fattrib;		/* File attribute */
+#if _USE_LFN != 0
+	TCHAR	altname[13];			/* Alternative file name */
+	TCHAR	fname[_MAX_LFN + 1];	/* Primary file name */
+#else
+	TCHAR	fname[13];		/* File name */
+#endif
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,				/* (0) Succeeded */
+	FR_DISK_ERR,			/* (1) A hard error occurred in the low level disk I/O layer */
+	FR_INT_ERR,				/* (2) Assertion failed */
+	FR_NOT_READY,			/* (3) The physical drive cannot work */
+	FR_NO_FILE,				/* (4) Could not find the file */
+	FR_NO_PATH,				/* (5) Could not find the path */
+	FR_INVALID_NAME,		/* (6) The path name format is invalid */
+	FR_DENIED,				/* (7) Access denied due to prohibited access or directory full */
+	FR_EXIST,				/* (8) Access denied due to prohibited access */
+	FR_INVALID_OBJECT,		/* (9) The file/directory object is invalid */
+	FR_WRITE_PROTECTED,		/* (10) The physical drive is write protected */
+	FR_INVALID_DRIVE,		/* (11) The logical drive number is invalid */
+	FR_NOT_ENABLED,			/* (12) The volume has no work area */
+	FR_NO_FILESYSTEM,		/* (13) There is no valid FAT volume */
+	FR_MKFS_ABORTED,		/* (14) The f_mkfs() aborted due to any problem */
+	FR_TIMEOUT,				/* (15) Could not get a grant to access the volume within defined period */
+	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
+	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
+	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > _FS_LOCK */
+	FR_INVALID_PARAMETER	/* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface                           */
+
+FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a file */
+FRESULT f_close (FIL* fp);											/* Close an open file object */
+FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from the file */
+FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to the file */
+FRESULT f_lseek (FIL* fp, FSIZE_t ofs);								/* Move file pointer of the file object */
+FRESULT f_truncate (FIL* fp);										/* Truncate the file */
+FRESULT f_sync (FIL* fp);											/* Flush cached data of the writing file */
+FRESULT f_opendir (DIR* dp, const TCHAR* path);						/* Open a directory */
+FRESULT f_closedir (DIR* dp);										/* Close an open directory */
+FRESULT f_readdir (DIR* dp, FILINFO* fno);							/* Read a directory item */
+FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern);	/* Find first file */
+FRESULT f_findnext (DIR* dp, FILINFO* fno);							/* Find next file */
+FRESULT f_mkdir (const TCHAR* path);								/* Create a sub directory */
+FRESULT f_unlink (const TCHAR* path);								/* Delete an existing file or directory */
+FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new);	/* Rename/Move a file or directory */
+FRESULT f_stat (const TCHAR* path, FILINFO* fno);					/* Get file status */
+FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask);			/* Change attribute of a file/dir */
+FRESULT f_utime (const TCHAR* path, const FILINFO* fno);			/* Change timestamp of a file/dir */
+FRESULT f_chdir (const TCHAR* path);								/* Change current directory */
+FRESULT f_chdrive (const TCHAR* path);								/* Change current drive */
+FRESULT f_getcwd (TCHAR* buff, UINT len);							/* Get current directory */
+FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get number of free clusters on the drive */
+FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
+FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
+FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
+FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt);					/* Allocate a contiguous block to the file */
+FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
+FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len);	/* Create a FAT volume */
+FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work);			/* Divide a physical drive into some partitions */
+int f_putc (TCHAR c, FIL* fp);										/* Put a character to the file */
+int f_puts (const TCHAR* str, FIL* cp);								/* Put a string to the file */
+int f_printf (FIL* fp, const TCHAR* str, ...);						/* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR* buff, int len, FIL* fp);						/* Get a string from the file */
+
+#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
+#define f_error(fp) ((fp)->err)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->obj.objsize)
+#define f_rewind(fp) f_lseek((fp), 0)
+#define f_rewinddir(dp) f_readdir((dp), 0)
+#define f_rmdir(path) f_unlink(path)
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions                            */
+
+/* RTC function */
+#if !_FS_READONLY && !_FS_NORTC
+DWORD get_fattime (void);
+#endif
+
+/* Unicode support functions */
+#if _USE_LFN != 0						/* Unicode - OEM code conversion */
+WCHAR ff_convert (WCHAR chr, UINT dir);	/* OEM-Unicode bidirectional conversion */
+WCHAR ff_wtoupper (WCHAR chr);			/* Unicode upper-case conversion */
+#if _USE_LFN == 3						/* Memory functions */
+void* ff_memalloc (UINT msize);			/* Allocate memory block */
+void ff_memfree (void* mblock);			/* Free memory block */
+#endif
+#endif
+
+/* Sync functions */
+#if _FS_REENTRANT
+int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj);	/* Create a sync object */
+int ff_req_grant (_SYNC_t sobj);				/* Lock sync object */
+void ff_rel_grant (_SYNC_t sobj);				/* Unlock sync object */
+int ff_del_syncobj (_SYNC_t sobj);				/* Delete a sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+
+/* File access mode and open method flags (3rd argument of f_open) */
+#define	FA_READ				0x01
+#define	FA_WRITE			0x02
+#define	FA_OPEN_EXISTING	0x00
+#define	FA_CREATE_NEW		0x04
+#define	FA_CREATE_ALWAYS	0x08
+#define	FA_OPEN_ALWAYS		0x10
+#define	FA_OPEN_APPEND		0x30
+
+/* Fast seek controls (2nd argument of f_lseek) */
+#define CREATE_LINKMAP	((FSIZE_t)0 - 1)
+
+/* Format options (2nd argument of f_mkfs) */
+#define FM_FAT		0x01
+#define FM_FAT32	0x02
+#define FM_EXFAT	0x04
+#define FM_ANY		0x07
+#define FM_SFD		0x08
+
+/* Filesystem type (FATFS.fs_type) */
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+#define FS_EXFAT	4
+
+/* File attribute bits for directory entry (FILINFO.fattrib) */
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FATFS */
diff --git a/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
new file mode 100644
index 0000000..1036ef4
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
@@ -0,0 +1,122 @@
+/**
+  ******************************************************************************
+  * @file    ff_gen_drv.c
+  * @author  MCD Application Team
+  * @brief   FatFs generic low level driver.
+  *****************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+**/
+/* Includes ------------------------------------------------------------------*/
+#include "ff_gen_drv.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+Disk_drvTypeDef disk = {{0},{0},{0},0};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Links a compatible diskio driver/lun id and increments the number of active
+  *         linked drivers.
+  * @note   The number of linked drivers (volumes) is up to 10 due to FatFs limits.
+  * @param  drv: pointer to the disk IO Driver structure
+  * @param  path: pointer to the logical drive path
+  * @param  lun : only used for USB Key Disk to add multi-lun management
+            else the parameter must be equal to 0
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, uint8_t lun)
+{
+  uint8_t ret = 1;
+  uint8_t DiskNum = 0;
+
+  if(disk.nbr < _VOLUMES)
+  {
+    disk.is_initialized[disk.nbr] = 0;
+    disk.drv[disk.nbr] = drv;
+    disk.lun[disk.nbr] = lun;
+    DiskNum = disk.nbr++;
+    path[0] = DiskNum + '0';
+    path[1] = ':';
+    path[2] = '/';
+    path[3] = 0;
+    ret = 0;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Links a compatible diskio driver and increments the number of active
+  *         linked drivers.
+  * @note   The number of linked drivers (volumes) is up to 10 due to FatFs limits
+  * @param  drv: pointer to the disk IO Driver structure
+  * @param  path: pointer to the logical drive path
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path)
+{
+  return FATFS_LinkDriverEx(drv, path, 0);
+}
+
+/**
+  * @brief  Unlinks a diskio driver and decrements the number of active linked
+  *         drivers.
+  * @param  path: pointer to the logical drive path
+  * @param  lun : not used
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_UnLinkDriverEx(char *path, uint8_t lun)
+{
+  uint8_t DiskNum = 0;
+  uint8_t ret = 1;
+
+  if(disk.nbr >= 1)
+  {
+    DiskNum = path[0] - '0';
+    if(disk.drv[DiskNum] != 0)
+    {
+      disk.drv[DiskNum] = 0;
+      disk.lun[DiskNum] = 0;
+      disk.nbr--;
+      ret = 0;
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Unlinks a diskio driver and decrements the number of active linked
+  *         drivers.
+  * @param  path: pointer to the logical drive path
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_UnLinkDriver(char *path)
+{
+  return FATFS_UnLinkDriverEx(path, 0);
+}
+
+/**
+  * @brief  Gets number of linked drivers to the FatFs module.
+  * @param  None
+  * @retval Number of attached drivers.
+  */
+uint8_t FATFS_GetAttachedDriversNbr(void)
+{
+  return disk.nbr;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h
new file mode 100644
index 0000000..65d879c
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h
@@ -0,0 +1,80 @@
+/**
+  ******************************************************************************
+  * @file    ff_gen_drv.h
+  * @author  MCD Application Team
+  * @brief   Header for ff_gen_drv.c module.
+  *****************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+**/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FF_GEN_DRV_H
+#define __FF_GEN_DRV_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "diskio.h"
+#include "ff.h"
+#include "stdint.h"
+
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  Disk IO Driver structure definition
+  */
+typedef struct
+{
+  DSTATUS (*disk_initialize) (BYTE);                     /*!< Initialize Disk Drive                     */
+  DSTATUS (*disk_status)     (BYTE);                     /*!< Get Disk Status                           */
+  DRESULT (*disk_read)       (BYTE, BYTE*, DWORD, UINT);       /*!< Read Sector(s)                            */
+#if _USE_WRITE == 1
+  DRESULT (*disk_write)      (BYTE, const BYTE*, DWORD, UINT); /*!< Write Sector(s) when _USE_WRITE = 0       */
+#endif /* _USE_WRITE == 1 */
+#if _USE_IOCTL == 1
+  DRESULT (*disk_ioctl)      (BYTE, BYTE, void*);              /*!< I/O control operation when _USE_IOCTL = 1 */
+#endif /* _USE_IOCTL == 1 */
+
+}Diskio_drvTypeDef;
+
+/**
+  * @brief  Global Disk IO Drivers structure definition
+  */
+typedef struct
+{
+  uint8_t                 is_initialized[_VOLUMES];
+  const Diskio_drvTypeDef *drv[_VOLUMES];
+  uint8_t                 lun[_VOLUMES];
+  volatile uint8_t        nbr;
+
+}Disk_drvTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path);
+uint8_t FATFS_UnLinkDriver(char *path);
+uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, BYTE lun);
+uint8_t FATFS_UnLinkDriverEx(char *path, BYTE lun);
+uint8_t FATFS_GetAttachedDriversNbr(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FF_GEN_DRV_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/Third_Party/FatFs/src/integer.h b/Middlewares/Third_Party/FatFs/src/integer.h
new file mode 100644
index 0000000..d8e911c
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/integer.h
@@ -0,0 +1,38 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _FF_INTEGER
+#define _FF_INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include 
+#include 
+typedef unsigned __int64 QWORD;
+
+
+#else			/* Embedded platform */
+
+/* These types MUST be 16-bit or 32-bit */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* This type MUST be 8-bit */
+typedef unsigned char	BYTE;
+
+/* These types MUST be 16-bit */
+typedef short			SHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types MUST be 32-bit */
+typedef long			LONG;
+typedef unsigned long	DWORD;
+
+/* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */
+typedef unsigned long long QWORD;
+
+#endif
+
+#endif
diff --git a/Middlewares/Third_Party/FatFs/src/option/syscall.c b/Middlewares/Third_Party/FatFs/src/option/syscall.c
new file mode 100644
index 0000000..327d941
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/option/syscall.c
@@ -0,0 +1,177 @@
+/*------------------------------------------------------------------------*/
+/* Sample code of OS dependent controls for FatFs                         */
+/* (C)ChaN, 2014                                                          */
+/*   Portions COPYRIGHT 2017 STMicroelectronics                           */
+/*   Portions Copyright (C) 2014, ChaN, all right reserved                */
+/*------------------------------------------------------------------------*/
+
+/**
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+**/
+
+
+
+#include "../ff.h"
+
+
+#if _FS_REENTRANT
+/*------------------------------------------------------------------------*/
+/* Create a Synchronization Object                                        */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to create a new
+/  synchronization object, such as semaphore and mutex. When a 0 is returned,
+/  the f_mount() function fails with FR_INT_ERR.
+*/
+
+int ff_cre_syncobj (	/* 1:Function succeeded, 0:Could not create the sync object */
+	BYTE vol,			/* Corresponding volume (logical drive number) */
+	_SYNC_t *sobj		/* Pointer to return the created sync object */
+)
+{
+
+    int ret;
+#if _USE_MUTEX
+
+#if (osCMSIS < 0x20000U)
+    osMutexDef(MTX);
+    *sobj = osMutexCreate(osMutex(MTX));
+#else
+    *sobj = osMutexNew(NULL);
+#endif
+
+#else
+
+#if (osCMSIS < 0x20000U)
+    osSemaphoreDef(SEM);
+    *sobj = osSemaphoreCreate(osSemaphore(SEM), 1);
+#else
+    *sobj = osSemaphoreNew(1, 1, NULL);
+#endif
+
+#endif
+    ret = (*sobj != NULL);
+
+    return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Delete a Synchronization Object                                        */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to delete a synchronization
+/  object that created with ff_cre_syncobj() function. When a 0 is returned,
+/  the f_mount() function fails with FR_INT_ERR.
+*/
+
+int ff_del_syncobj (	/* 1:Function succeeded, 0:Could not delete due to any error */
+	_SYNC_t sobj		/* Sync object tied to the logical drive to be deleted */
+)
+{
+#if _USE_MUTEX
+    osMutexDelete (sobj);
+#else
+    osSemaphoreDelete (sobj);
+#endif
+    return 1;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Request Grant to Access the Volume                                     */
+/*------------------------------------------------------------------------*/
+/* This function is called on entering file functions to lock the volume.
+/  When a 0 is returned, the file function fails with FR_TIMEOUT.
+*/
+
+int ff_req_grant (	/* 1:Got a grant to access the volume, 0:Could not get a grant */
+	_SYNC_t sobj	/* Sync object to wait */
+)
+{
+  int ret = 0;
+#if (osCMSIS < 0x20000U)
+
+#if _USE_MUTEX
+  if(osMutexWait(sobj, _FS_TIMEOUT) == osOK)
+#else
+  if(osSemaphoreWait(sobj, _FS_TIMEOUT) == osOK)
+#endif
+
+#else
+
+#if _USE_MUTEX
+   if(osMutexAcquire(sobj, _FS_TIMEOUT) == osOK)
+#else
+   if(osSemaphoreAcquire(sobj, _FS_TIMEOUT) == osOK)
+#endif
+
+#endif
+  {
+    ret = 1;
+  }
+
+  return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Release Grant to Access the Volume                                     */
+/*------------------------------------------------------------------------*/
+/* This function is called on leaving file functions to unlock the volume.
+*/
+
+void ff_rel_grant (
+	_SYNC_t sobj	/* Sync object to be signaled */
+)
+{
+#if _USE_MUTEX
+  osMutexRelease(sobj);
+#else
+  osSemaphoreRelease(sobj);
+#endif
+}
+
+#endif
+
+
+
+
+#if _USE_LFN == 3	/* LFN with a working buffer on the heap */
+/*------------------------------------------------------------------------*/
+/* Allocate a memory block                                                */
+/*------------------------------------------------------------------------*/
+/* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE.
+*/
+
+void* ff_memalloc (	/* Returns pointer to the allocated memory block */
+	UINT msize		/* Number of bytes to allocate */
+)
+{
+	return ff_malloc(msize);	/* Allocate a new memory block with POSIX API */
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Free a memory block                                                    */
+/*------------------------------------------------------------------------*/
+
+void ff_memfree (
+	void* mblock	/* Pointer to the memory block to free */
+)
+{
+	ff_free(mblock);	/* Discard the memory block with POSIX API */
+}
+
+#endif
diff --git a/STM32F767ZITx_FLASH.ld b/STM32F767ZITx_FLASH.ld
new file mode 100644
index 0000000..27cee92
--- /dev/null
+++ b/STM32F767ZITx_FLASH.ld
@@ -0,0 +1,188 @@
+/*
+******************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Author		: STM32CubeMX
+**
+**  Abstract    : Linker script for STM32F767ZITx series
+**                2048Kbytes FLASH and 512Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** 
© COPYRIGHT(c) 2019 STMicroelectronics

+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x2000;      /* required amount of heap  */
+_Min_Stack_Size = 0x4000; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 512K
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 2048K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+}
+
+
diff --git a/Src/File_Handling.c b/Src/File_Handling.c
new file mode 100644
index 0000000..1cc0f2a
--- /dev/null
+++ b/Src/File_Handling.c
@@ -0,0 +1,709 @@
+/*
+ * File_Handling_RTOS.c
+ *
+ *  Created on: 14-May-2020
+ *      Author: Controllerstech
+ */
+
+#include 
+#include "stm32f7xx_hal.h"
+
+#define UART USART1
+
+
+
+/* =============================>>>>>>>> NO CHANGES AFTER THIS LINE =====================================>>>>>>> */
+
+FATFS fs;  // file system
+FIL fil; // File
+FILINFO fno;
+extern FRESULT fresult;  // result
+extern unsigned long sizeoffile;
+UINT br, bw;  // File read/write count
+
+/**** capacity related *****/
+FATFS *pfs;
+DWORD fre_clust;
+uint32_t total, free_space;
+
+
+void Send_Uart (char *string)
+{
+	//HAL_UART_Transmit(UART, (uint8_t *)string, strlen (string), HAL_MAX_DELAY);
+}
+
+
+
+int Mount_SD (const TCHAR* path)
+{
+	fresult = f_mount(&fs, path, 1);
+	if (fresult != FR_OK) return 1;
+	else return 0;
+}
+
+int Unmount_SD (const TCHAR* path)
+{
+	fresult = f_mount(NULL, path, 1);
+	if (fresult == FR_OK) return 0;//Send_Uart ("SD CARD UNMOUNTED successfully...\n\n\n");
+	return 1;//else Send_Uart("ERROR!!! in UNMOUNTING SD CARD\n\n\n");
+}
+
+/* Start node to be scanned (***also used as work area***) */
+FRESULT Scan_SD (char* pat)
+{
+    DIR dir;
+    UINT i;
+    char *path = malloc(20*sizeof (char));
+    sprintf (path, "%s",pat);
+
+    fresult = f_opendir(&dir, path);                       /* Open the directory */
+    if (fresult == FR_OK)
+    {
+        for (;;)
+        {
+            fresult = f_readdir(&dir, &fno);                   /* Read a directory item */
+            if (fresult != FR_OK || fno.fname[0] == 0) break;  /* Break on error or end of dir */
+            if (fno.fattrib & AM_DIR)     /* It is a directory */
+            {
+            	if (!(strcmp ("SYSTEM~1", fno.fname))) continue;
+            	char *buf = malloc(30*sizeof(char));
+            	sprintf (buf, "Dir: %s\r\n", fno.fname);
+            	Send_Uart(buf);
+            	free(buf);
+                i = strlen(path);
+                sprintf(&path[i], "/%s", fno.fname);
+                fresult = Scan_SD(path);                     /* Enter the directory */
+                if (fresult != FR_OK) break;
+                path[i] = 0;
+            }
+            else
+            {   /* It is a file. */
+           	   char *buf = malloc(30*sizeof(char));
+               sprintf(buf,"File: %s/%s\n", path, fno.fname);
+               Send_Uart(buf);
+               free(buf);
+            }
+        }
+        f_closedir(&dir);
+    }
+    free(path);
+    return fresult;
+}
+
+/* Only supports removing files from home directory */
+FRESULT Format_SD (void)
+{
+    DIR dir;
+    char *path = malloc(20*sizeof (char));
+    sprintf (path, "%s","/");
+
+    fresult = f_opendir(&dir, path);                       /* Open the directory */
+    if (fresult == FR_OK)
+    {
+        for (;;)
+        {
+            fresult = f_readdir(&dir, &fno);                   /* Read a directory item */
+            if (fresult != FR_OK || fno.fname[0] == 0) break;  /* Break on error or end of dir */
+            if (fno.fattrib & AM_DIR)     /* It is a directory */
+            {
+            	if (!(strcmp ("SYSTEM~1", fno.fname))) continue;
+            	fresult = f_unlink(fno.fname);
+            	if (fresult == FR_DENIED) continue;
+            }
+            else
+            {   /* It is a file. */
+               fresult = f_unlink(fno.fname);
+            }
+        }
+        f_closedir(&dir);
+    }
+    free(path);
+    return fresult;
+}
+
+
+
+
+FRESULT Write_File (char *name, char *data)
+{
+
+	/**** check whether the file exists or not ****/
+	fresult = f_stat (name, &fno);
+	if (fresult != FR_OK)
+	{
+		char *buf = malloc(100*sizeof(char));
+		//sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name);
+		//Send_Uart (buf);
+	    free(buf);
+	    return fresult;
+	}
+
+	else
+	{
+	    /* Create a file with read write access and open it */
+	    fresult = f_open(&fil, name, FA_OPEN_EXISTING | FA_WRITE);
+	    if (fresult != FR_OK)
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name);
+	    	//Send_Uart(buf);
+	        free(buf);
+	        return fresult;
+	    }
+
+	    else
+	    {
+	    	fresult = f_write(&fil, data, strlen(data), &bw);
+	    	if (fresult != FR_OK)
+	    	{
+	    		char *buf = malloc(100*sizeof(char));
+	    		//sprintf (buf, "ERROR!!! No. %d while writing to the FILE *%s*\n\n", fresult, name);
+	    		//Send_Uart(buf);
+	    		free(buf);
+	    	}
+
+	    	/* Close file */
+	    	fresult = f_close(&fil);
+	    	if (fresult != FR_OK)
+	    	{
+	    		char *buf = malloc(100*sizeof(char));
+	    		//sprintf (buf, "ERROR!!! No. %d in closing file *%s* after writing it\n\n", fresult, name);
+	    		//Send_Uart(buf);
+	    		free(buf);
+	    	}
+	    	else
+	    	{
+	    		char *buf = malloc(100*sizeof(char));
+	    		//sprintf (buf, "File *%s* is WRITTEN and CLOSED successfully\n", name);
+	    		//Send_Uart(buf);
+	    		free(buf);
+	    	}
+	    }
+	    return fresult;
+	}
+}
+
+FRESULT Write_File_byte (char *name, uint8_t *data, unsigned int bytesize)
+{
+
+	/**** check whether the file exists or not ****/
+	fresult = f_stat (name, &fno);
+	if (fresult != FR_OK)
+	{
+		char *buf = malloc(100*sizeof(char));
+		//sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name);
+		//Send_Uart (buf);
+	    free(buf);
+	    return fresult;
+	}
+
+	else
+	{
+	    /* Create a file with read write access and open it */
+	    fresult = f_open(&fil, name, FA_OPEN_EXISTING | FA_WRITE);
+	    if (fresult != FR_OK)
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name);
+	    	//Send_Uart(buf);
+	        free(buf);
+	        return fresult;
+	    }
+
+	    else
+	    {
+	    	fresult = f_write(&fil, data, bytesize, &bw);
+	    	if (fresult != FR_OK)
+	    	{
+	    		char *buf = malloc(100*sizeof(char));
+	    		//sprintf (buf, "ERROR!!! No. %d while writing to the FILE *%s*\n\n", fresult, name);
+	    		//Send_Uart(buf);
+	    		free(buf);
+	    	}
+
+	    	/* Close file */
+	    	fresult = f_close(&fil);
+	    	if (fresult != FR_OK)
+	    	{
+	    		char *buf = malloc(100*sizeof(char));
+	    		//sprintf (buf, "ERROR!!! No. %d in closing file *%s* after writing it\n\n", fresult, name);
+	    		//Send_Uart(buf);
+	    		free(buf);
+	    	}
+	    	else
+	    	{
+	    		char *buf = malloc(100*sizeof(char));
+	    		//sprintf (buf, "File *%s* is WRITTEN and CLOSED successfully\n", name);
+	    		//Send_Uart(buf);
+	    		free(buf);
+	    	}
+	    }
+	    return fresult;
+	}
+}
+
+FRESULT Read_File (char *name)
+{
+	/**** check whether the file exists or not ****/
+	fresult = f_stat (name, &fno);
+	if (fresult != FR_OK)
+	{
+		char *buf = malloc(100*sizeof(char));
+		sprintf (buf, "ERRROR!!! *%s* does not exists\n\n", name);
+		Send_Uart (buf);
+		free(buf);
+	    return fresult;
+	}
+
+	else
+	{
+		/* Open file to read */
+		fresult = f_open(&fil, name, FA_READ);
+
+		if (fresult != FR_OK)
+		{
+			char *buf = malloc(100*sizeof(char));
+			sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name);
+		    Send_Uart(buf);
+		    free(buf);
+		    return fresult;
+		}
+
+		/* Read data from the file
+		* see the function details for the arguments */
+
+		char *buffer = malloc(sizeof(f_size(&fil)));
+		fresult = f_read (&fil, buffer, f_size(&fil), &br);
+		if (fresult != FR_OK)
+		{
+			char *buf = malloc(100*sizeof(char));
+			free(buffer);
+		 	sprintf (buf, "ERROR!!! No. %d in reading file *%s*\n\n", fresult, name);
+		  	Send_Uart(buffer);
+		  	free(buf);
+		}
+
+		else
+		{
+			Send_Uart(buffer);
+			free(buffer);
+
+			/* Close file */
+			fresult = f_close(&fil);
+			if (fresult != FR_OK)
+			{
+				char *buf = malloc(100*sizeof(char));
+				sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name);
+				Send_Uart(buf);
+				free(buf);
+			}
+			else
+			{
+				char *buf = malloc(100*sizeof(char));
+				sprintf (buf, "File *%s* CLOSED successfully\n", name);
+				Send_Uart(buf);
+				free(buf);
+			}
+		}
+	    return fresult;
+	}
+}
+
+FRESULT Seek_Read_File (char *name, uint8_t *data, unsigned int bytesize, unsigned long goto_label)
+{
+	/**** check whether the file exists or not ****/
+	fresult = f_stat (name, &fno);
+	if (fresult != FR_OK)
+	{
+		char *buf = malloc(100*sizeof(char));
+		sprintf (buf, "ERRROR!!! *%s* does not exists\n\n", name);
+		//Send_Uart (buf);
+		free(buf);
+	    return fresult;
+	}
+
+	else
+	{
+		/* Open file to read */
+		fresult = f_open(&fil, name, FA_READ);
+
+		if (fresult != FR_OK)
+		{
+			char *buf = malloc(100*sizeof(char));
+			sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name);
+		    //Send_Uart(buf);
+		    free(buf);
+		    return fresult;
+		}
+
+		/* Read data from the file
+		* see the function details for the arguments */
+
+		//char *buffer = malloc(sizeof(f_size(&fil)));
+		fresult =  f_lseek (&fil, goto_label);								/* Move file pointer of the file object */
+		if (fresult != FR_OK)
+		{
+			char *buf = malloc(100*sizeof(char));
+			//free(buffer);
+		 	sprintf (buf, "ERROR!!! Can't seek the file:   *%s*\n\n", name);
+		  //Send_Uart(buffer);
+		  free(buf);
+			return fresult;
+		}
+		fresult = f_read (&fil, data, bytesize, &br);
+		if (fresult != FR_OK)
+		{
+			char *buf = malloc(100*sizeof(char));
+			//free(buffer);
+		 	sprintf (buf, "ERROR!!! No. %d in reading file *%s*\n\n", fresult, name);
+		  //Send_Uart(buffer);
+		  free(buf);
+			
+		}
+
+		else
+		{
+			//Send_Uart(buffer);
+			//free(buffer);
+			if (goto_label==0)//Set size of file in first 4 bytes
+			{
+				sizeoffile = f_size(&fil);
+				data[0] = (uint8_t) (sizeoffile&0xff);
+				data[1] = (uint8_t) ((sizeoffile>>8)&0xff);
+				data[2] = (uint8_t) ((sizeoffile>>16)&0xff);
+				data[3] = (uint8_t) ((sizeoffile>>24)&0xff);
+			}
+			
+			/* Close file */
+			fresult = f_close(&fil);
+			if (fresult != FR_OK)
+			{
+				char *buf = malloc(100*sizeof(char));
+				sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name);
+				//Send_Uart(buf);
+				free(buf);
+			}
+			else
+			{
+				char *buf = malloc(100*sizeof(char));
+				sprintf (buf, "File *%s* CLOSED successfully\n", name);
+				//Send_Uart(buf);
+				free(buf);
+			}
+		}
+	    return fresult;
+	}
+}
+
+FRESULT Create_File (char *name)
+{
+	fresult = f_stat (name, &fno);
+	if (fresult == FR_OK)
+	{
+		char *buf = malloc(100*sizeof(char));
+		//sprintf (buf, "ERROR!!! *%s* already exists!!!!\n use Update_File \n\n",name);
+		//Send_Uart(buf);
+		free(buf);
+	    return fresult;
+	}
+	else
+	{
+		fresult = f_open(&fil, name, FA_CREATE_ALWAYS|FA_READ|FA_WRITE);
+		if (fresult != FR_OK)
+		{
+			char *buf = malloc(100*sizeof(char));
+			//sprintf (buf, "ERROR!!! No. %d in creating file *%s*\n\n", fresult, name);
+			//Send_Uart(buf);
+			free(buf);
+		    return fresult;
+		}
+		else
+		{
+			char *buf = malloc(100*sizeof(char));
+			//sprintf (buf, "*%s* created successfully\n Now use Write_File to write data\n",name);
+			//Send_Uart(buf);
+			free(buf);
+		}
+
+		fresult = f_close(&fil);
+		if (fresult != FR_OK)
+		{
+			char *buf = malloc(100*sizeof(char));
+			//sprintf (buf, "ERROR No. %d in closing file *%s*\n\n", fresult, name);
+			//Send_Uart(buf);
+			free(buf);
+		}
+		else
+		{
+			char *buf = malloc(100*sizeof(char));
+			//sprintf (buf, "File *%s* CLOSED successfully\n", name);
+			//Send_Uart(buf);
+			free(buf);
+		}
+	}
+    return fresult;
+}
+
+FRESULT Update_File (char *name, char *data)
+{
+	/**** check whether the file exists or not ****/
+	fresult = f_stat (name, &fno);
+	if (fresult != FR_OK)
+	{
+		char *buf = malloc(100*sizeof(char));
+		//sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name);
+		//Send_Uart (buf);
+		free(buf);
+	    return fresult;
+	}
+
+	else
+	{
+		 /* Create a file with read write access and open it */
+	    fresult = f_open(&fil, name, FA_OPEN_APPEND | FA_WRITE);
+	    if (fresult != FR_OK)
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name);
+	    	//Send_Uart(buf);
+	        free(buf);
+	        return fresult;
+	    }
+
+	    /* Writing text */
+	    fresult = f_write(&fil, data, strlen (data), &bw);
+	    if (fresult != FR_OK)
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "ERROR!!! No. %d in writing file *%s*\n\n", fresult, name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	    }
+
+	    else
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "*%s* UPDATED successfully\n", name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	    }
+
+	    /* Close file */
+	    fresult = f_close(&fil);
+	    if (fresult != FR_OK)
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	    }
+	    else
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "File *%s* CLOSED successfully\n", name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	     }
+	}
+    return fresult;
+}
+
+FRESULT Remove_File (char *name)
+{
+	/**** check whether the file exists or not ****/
+	fresult = f_stat (name, &fno);
+	if (fresult != FR_OK)
+	{
+		char *buf = malloc(100*sizeof(char));
+		sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name);
+		Send_Uart (buf);
+		free(buf);
+		return fresult;
+	}
+
+	else
+	{
+		fresult = f_unlink (name);
+		if (fresult == FR_OK)
+		{
+			char *buf = malloc(100*sizeof(char));
+			sprintf (buf, "*%s* has been removed successfully\n", name);
+			Send_Uart (buf);
+			free(buf);
+		}
+
+		else
+		{
+			char *buf = malloc(100*sizeof(char));
+			sprintf (buf, "ERROR No. %d in removing *%s*\n\n",fresult, name);
+			Send_Uart (buf);
+			free(buf);
+		}
+	}
+	return fresult;
+}
+
+FRESULT Create_Dir (char *name)
+{
+    fresult = f_mkdir(name);
+    if (fresult == FR_OK)
+    {
+    	char *buf = malloc(100*sizeof(char));
+    	sprintf (buf, "*%s* has been created successfully\n", name);
+    	Send_Uart (buf);
+    	free(buf);
+    }
+    else
+    {
+    	char *buf = malloc(100*sizeof(char));
+    	sprintf (buf, "ERROR No. %d in creating directory *%s*\n\n", fresult,name);
+    	Send_Uart(buf);
+    	free(buf);
+    }
+    return fresult;
+}
+
+void Check_SD_Space (void)
+{
+    /* Check free space */
+    f_getfree("", &fre_clust, &pfs);
+
+    total = (uint32_t)((pfs->n_fatent - 2) * pfs->csize * 0.5);
+    char *buf = malloc(30*sizeof(char));
+    sprintf (buf, "SD CARD Total Size: \t%lu\n",total);
+    Send_Uart(buf);
+    free(buf);
+    free_space = (uint32_t)(fre_clust * pfs->csize * 0.5);
+    buf = malloc(30*sizeof(char));
+    sprintf (buf, "SD CARD Free Space: \t%lu\n",free_space);
+    Send_Uart(buf);
+    free(buf);
+}
+
+FRESULT Update_File_float (char *name, float *data, unsigned int bytesize)
+{
+	/**** check whether the file exists or not ****/
+	fresult = f_stat (name, &fno);
+	if (fresult != FR_OK)
+	{
+		char *buf = malloc(100*sizeof(char));
+		//sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name);
+		//Send_Uart (buf);
+		free(buf);
+	    return fresult;
+	}
+
+	else
+	{
+		 /* Create a file with read write access and open it */
+	    fresult = f_open(&fil, name, FA_OPEN_APPEND | FA_WRITE);
+	    if (fresult != FR_OK)
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name);
+	    	//Send_Uart(buf);
+	        free(buf);
+	        return fresult;
+	    }
+
+	    /* Writing text */
+	    fresult = f_write(&fil, data, bytesize, &bw);
+	    if (fresult != FR_OK)
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "ERROR!!! No. %d in writing file *%s*\n\n", fresult, name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	    }
+
+	    else
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "*%s* UPDATED successfully\n", name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	    }
+
+	    /* Close file */
+	    fresult = f_close(&fil);
+	    if (fresult != FR_OK)
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	    }
+	    else
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "File *%s* CLOSED successfully\n", name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	     }
+	}
+    return fresult;
+}
+
+FRESULT Update_File_byte (char *name, uint8_t *data, unsigned int bytesize)
+{
+	/**** check whether the file exists or not ****/
+	fresult = f_stat (name, &fno);
+	if (fresult != FR_OK)
+	{
+		char *buf = malloc(100*sizeof(char));
+		//sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name);
+		//Send_Uart (buf);
+		free(buf);
+	    return fresult;
+	}
+
+	else
+	{
+		 /* Create a file with read write access and open it */
+	    fresult = f_open(&fil, name, FA_OPEN_APPEND | FA_WRITE);
+	    if (fresult != FR_OK)
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name);
+	    	//Send_Uart(buf);
+	        free(buf);
+	        return fresult;
+	    }
+
+	    /* Writing text */
+	    fresult = f_write(&fil, data, bytesize, &bw);
+	    if (fresult != FR_OK)
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "ERROR!!! No. %d in writing file *%s*\n\n", fresult, name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	    }
+
+	    else
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "*%s* UPDATED successfully\n", name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	    }
+
+	    /* Close file */
+	    fresult = f_close(&fil);
+	    if (fresult != FR_OK)
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	    }
+	    else
+	    {
+	    	char *buf = malloc(100*sizeof(char));
+	    	//sprintf (buf, "File *%s* CLOSED successfully\n", name);
+	    	//Send_Uart(buf);
+	    	free(buf);
+	     }
+	}
+    return fresult;
+}
diff --git a/Src/bsp_driver_sd.c b/Src/bsp_driver_sd.c
new file mode 100644
index 0000000..f3d988b
--- /dev/null
+++ b/Src/bsp_driver_sd.c
@@ -0,0 +1,314 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    bsp_driver_sd.c for F7 (based on stm32756g_eval_sd.c)
+ * @brief   This file includes a generic uSD card driver.
+ *          To be completed by the user according to the board used for the project.
+ * @note    Some functions generated as weak: they can be overridden by
+ *          - code in user files
+ *          - or BSP code from the FW pack files
+ *          if such files are added to the generated project (by the user).
+ ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+#ifdef OLD_API
+/* kept to avoid issue when migrating old projects. */
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+#else
+/* USER CODE BEGIN FirstSection */
+/* can be used to modify / undefine following code or add new definitions */
+/* USER CODE END FirstSection */
+/* Includes ------------------------------------------------------------------*/
+#include "bsp_driver_sd.h"
+
+/* Extern variables ---------------------------------------------------------*/
+
+extern SD_HandleTypeDef hsd1;
+
+/* USER CODE BEGIN BeforeInitSection */
+/* can be used to modify / undefine following code or add code */
+/* USER CODE END BeforeInitSection */
+/**
+  * @brief  Initializes the SD card device.
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_Init(void)
+{
+  uint8_t sd_state = MSD_OK;
+  /* Check if the SD card is plugged in the slot */
+  if (BSP_SD_IsDetected() != SD_PRESENT)
+  {
+    return MSD_ERROR_SD_NOT_PRESENT;
+  }
+  /* HAL SD initialization */
+  sd_state = HAL_SD_Init(&hsd1);
+  /* Configure SD Bus width (4 bits mode selected) */
+  if (sd_state == MSD_OK)
+  {
+    /* Enable wide operation */
+    if (HAL_SD_ConfigWideBusOperation(&hsd1, SDMMC_BUS_WIDE_4B) != HAL_OK)
+    {
+      sd_state = MSD_ERROR;
+    }
+  }
+
+  return sd_state;
+}
+/* USER CODE BEGIN AfterInitSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END AfterInitSection */
+
+/* USER CODE BEGIN InterruptMode */
+/**
+  * @brief  Configures Interrupt mode for SD detection pin.
+  * @retval Returns 0
+  */
+__weak uint8_t BSP_SD_ITConfig(void)
+{
+  /* Code to be updated by the user or replaced by one from the FW pack (in a stmxxxx_sd.c file) */
+
+  return (uint8_t)0;
+}
+
+/* USER CODE END InterruptMode */
+
+/* USER CODE BEGIN BeforeReadBlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeReadBlocksSection */
+/**
+  * @brief  Reads block(s) from a specified address in an SD card, in polling mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  ReadAddr: Address from where data is to be read
+  * @param  NumOfBlocks: Number of SD blocks to read
+  * @param  Timeout: Timeout for read operation
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout)
+{
+  uint8_t sd_state = MSD_OK;
+
+  if (HAL_SD_ReadBlocks(&hsd1, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeWriteBlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeWriteBlocksSection */
+/**
+  * @brief  Writes block(s) to a specified address in an SD card, in polling mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  WriteAddr: Address from where data is to be written
+  * @param  NumOfBlocks: Number of SD blocks to write
+  * @param  Timeout: Timeout for write operation
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout)
+{
+  uint8_t sd_state = MSD_OK;
+
+  if (HAL_SD_WriteBlocks(&hsd1, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeReadDMABlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeReadDMABlocksSection */
+/**
+  * @brief  Reads block(s) from a specified address in an SD card, in DMA mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  ReadAddr: Address from where data is to be read
+  * @param  NumOfBlocks: Number of SD blocks to read
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks)
+{
+  uint8_t sd_state = MSD_OK;
+
+  /* Read block(s) in DMA transfer mode */
+  if (HAL_SD_ReadBlocks_DMA(&hsd1, (uint8_t *)pData, ReadAddr, NumOfBlocks) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeWriteDMABlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeWriteDMABlocksSection */
+/**
+  * @brief  Writes block(s) to a specified address in an SD card, in DMA mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  WriteAddr: Address from where data is to be written
+  * @param  NumOfBlocks: Number of SD blocks to write
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks)
+{
+  uint8_t sd_state = MSD_OK;
+
+  /* Write block(s) in DMA transfer mode */
+  if (HAL_SD_WriteBlocks_DMA(&hsd1, (uint8_t *)pData, WriteAddr, NumOfBlocks) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeEraseSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeEraseSection */
+/**
+  * @brief  Erases the specified memory area of the given SD card.
+  * @param  StartAddr: Start byte address
+  * @param  EndAddr: End byte address
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr)
+{
+  uint8_t sd_state = MSD_OK;
+
+  if (HAL_SD_Erase(&hsd1, StartAddr, EndAddr) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeGetCardStateSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeGetCardStateSection */
+
+/**
+  * @brief  Gets the current SD card data status.
+  * @param  None
+  * @retval Data transfer state.
+  *          This value can be one of the following values:
+  *            @arg  SD_TRANSFER_OK: No data transfer is acting
+  *            @arg  SD_TRANSFER_BUSY: Data transfer is acting
+  */
+__weak uint8_t BSP_SD_GetCardState(void)
+{
+  return ((HAL_SD_GetCardState(&hsd1) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY);
+}
+
+/**
+  * @brief  Get SD information about specific SD card.
+  * @param  CardInfo: Pointer to HAL_SD_CardInfoTypedef structure
+  * @retval None
+  */
+__weak void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo)
+{
+  /* Get SD card Information */
+  HAL_SD_GetCardInfo(&hsd1, CardInfo);
+}
+
+/* USER CODE BEGIN BeforeCallBacksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeCallBacksSection */
+/**
+  * @brief SD Abort callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_AbortCallback();
+}
+
+/**
+  * @brief Tx Transfer completed callback
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_WriteCpltCallback();
+}
+
+/**
+  * @brief Rx Transfer completed callback
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_ReadCpltCallback();
+}
+
+/* USER CODE BEGIN CallBacksSection_C */
+/**
+  * @brief BSP SD Abort callback
+  * @retval None
+  * @note empty (up to the user to fill it in or to remove it if useless)
+  */
+__weak void BSP_SD_AbortCallback(void)
+{
+
+}
+
+/**
+  * @brief BSP Tx Transfer completed callback
+  * @retval None
+  * @note empty (up to the user to fill it in or to remove it if useless)
+  */
+__weak void BSP_SD_WriteCpltCallback(void)
+{
+
+}
+
+/**
+  * @brief BSP Rx Transfer completed callback
+  * @retval None
+  * @note empty (up to the user to fill it in or to remove it if useless)
+  */
+__weak void BSP_SD_ReadCpltCallback(void)
+{
+
+}
+/* USER CODE END CallBacksSection_C */
+#endif
+
+/**
+ * @brief  Detects if SD card is correctly plugged in the memory slot or not.
+ * @param  None
+ * @retval Returns if SD is detected or not
+ */
+__weak uint8_t BSP_SD_IsDetected(void)
+{
+  __IO uint8_t status = SD_PRESENT;
+
+  if (BSP_PlatformIsDetected() == 0x0)
+  {
+    status = SD_NOT_PRESENT;
+  }
+
+  return status;
+}
+
+/* USER CODE BEGIN AdditionalCode */
+/* user code can be inserted here */
+/* USER CODE END AdditionalCode */
diff --git a/Src/fatfs.c b/Src/fatfs.c
new file mode 100644
index 0000000..42e8d67
--- /dev/null
+++ b/Src/fatfs.c
@@ -0,0 +1,54 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file   fatfs.c
+  * @brief  Code for fatfs applications
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+#include "fatfs.h"
+
+uint8_t retSD;    /* Return value for SD */
+char SDPath[4];   /* SD logical drive path */
+FATFS SDFatFS;    /* File system object for SD logical drive */
+FIL SDFile;       /* File object for SD */
+
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+void MX_FATFS_Init(void)
+{
+  /*## FatFS: Link the SD driver ###########################*/
+  retSD = FATFS_LinkDriver(&SD_Driver, SDPath);
+
+  /* USER CODE BEGIN Init */
+  /* additional user code for init */
+  /* USER CODE END Init */
+}
+
+/**
+  * @brief  Gets Time from RTC
+  * @param  None
+  * @retval Time in DWORD
+  */
+DWORD get_fattime(void)
+{
+  /* USER CODE BEGIN get_fattime */
+  return 0;
+  /* USER CODE END get_fattime */
+}
+
+/* USER CODE BEGIN Application */
+
+/* USER CODE END Application */
diff --git a/Src/fatfs_platform.c b/Src/fatfs_platform.c
new file mode 100644
index 0000000..d2e02a6
--- /dev/null
+++ b/Src/fatfs_platform.c
@@ -0,0 +1,32 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : fatfs_platform.c
+  * @brief          : fatfs_platform source file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+*/
+/* USER CODE END Header */
+#include "fatfs_platform.h"
+
+uint8_t	BSP_PlatformIsDetected(void) {
+    uint8_t status = SD_PRESENT;
+    /* Check SD card detect pin */
+    if(HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != GPIO_PIN_RESET)
+    {
+        status = SD_NOT_PRESENT;
+    }
+    /* USER CODE BEGIN 1 */
+    /* user code can be inserted here */
+    /* USER CODE END 1 */
+    return status;
+}
diff --git a/Src/main.c b/Src/main.c
new file mode 100644
index 0000000..efbdfe5
--- /dev/null
+++ b/Src/main.c
@@ -0,0 +1,2244 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "fatfs.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+//	#include "math.h"
+	#include "File_Handling.h"
+	#include 
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+ADC_HandleTypeDef hadc3;
+
+SD_HandleTypeDef hsd1;
+
+TIM_HandleTypeDef htim10;
+
+/* USER CODE BEGIN PV */
+uint32_t TO6, TO6_before, TO6_stop, TO6_uart, SD_SEEK, SD_SLIDE, temp32, TO7, TO7_before, TO7_PID, TO10, TO10_counter, TIM10_period;//timer 6 ticks & SD FILE COUNTER
+uint8_t uart_buf, CPU_state, CPU_state_old, UART_transmission_request, State_Data[2], UART_DATA[DL_8], flg_tmt, u_tx_flg, u_rx_flg, TIM10_coflag;
+uint16_t UART_rec_incr, UART_header, CS_result, temp16, Long_Data[DL_16], COMMAND[CL_16];//, SD_matr[SD_Length][DL_16];
+FRESULT fresult;  // result
+int test;
+unsigned long fgoto, sizeoffile;//file pointer of the file object & size of file FPGA_RECEIVE_DATA_SIZE_32*FPGA_RECEIVE_WORD_SIZE_8+4+2
+
+LDx_SetupTypeDef LD1_curr_setup, LD2_curr_setup, LD1_def_setup, LD2_def_setup;
+Work_SetupTypeDef Curr_setup, Def_setup;
+LDx_ParamTypeDef LD1_param, LD2_param;
+
+task_t task;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_SPI4_Init(void);
+static void MX_TIM2_Init(void);
+static void MX_TIM5_Init(void);
+static void MX_ADC1_Init(void);
+static void MX_ADC3_Init(void);
+static void MX_SPI2_Init(void);
+static void MX_SPI5_Init(void);
+static void MX_SPI6_Init(void);
+static void MX_USART1_UART_Init(void);
+static void MX_SDMMC1_SD_Init(void);
+static void MX_TIM7_Init(void);
+static void MX_TIM6_Init(void);
+static void MX_TIM10_Init(void);
+/* USER CODE BEGIN PFP */
+static void Init_params(void);
+static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_curr_setup, Work_SetupTypeDef *Curr_setup);
+static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_curr_setup, Work_SetupTypeDef *Curr_setup);
+static void Set_LTEC(uint8_t num, uint16_t DATA);
+static uint16_t MPhD_T(uint8_t num);
+static uint16_t Get_ADC(uint8_t num);
+static uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results, uint8_t num);
+uint8_t CheckChecksum(uint16_t *pbuff);
+uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len);
+//int SD_Init(void);
+int SD_SAVE(uint16_t *pbuff);
+//uint32_t Get_Length(void);
+int SD_READ(uint16_t *pbuff);
+int SD_REMOVE(void);
+void USART_TX (uint8_t* dt, uint16_t sz);
+void USART_TX_DMA (uint16_t sz);
+static void Stop_TIM10();
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+	HAL_StatusTypeDef st;
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+	/*I hope you don't forget that first - MX_DMA_Init(); and than - MX_USART1_UART_Init();*/
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+	
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_SPI4_Init();
+  MX_FATFS_Init();
+  MX_TIM2_Init();
+  MX_TIM5_Init();
+  MX_ADC1_Init();
+  MX_ADC3_Init();
+  MX_SPI2_Init();
+  MX_SPI5_Init();
+  MX_SPI6_Init();
+  MX_USART1_UART_Init();
+  MX_SDMMC1_SD_Init();
+  MX_TIM7_Init();
+  MX_TIM6_Init();
+  MX_TIM10_Init();
+  /* USER CODE BEGIN 2 */
+	Init_params();
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+		if ((HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin)==GPIO_PIN_SET)&&(u_rx_flg == 0))
+		{
+			//NVIC_DisableIRQ(USART1_IRQn);
+			LL_USART_EnableIT_PE(USART1);
+			LL_USART_EnableIT_RXNE(USART1);
+			LL_USART_EnableIT_ERROR(USART1);
+			NVIC_SetPriority(USART1_IRQn, 0);
+			NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag...
+			u_rx_flg = 1;
+		}
+//		else
+//		{
+//			//NVIC_DisableIRQ(USART1_IRQn);
+//			u_rx_flg = 0;
+//		}
+			switch (CPU_state)
+			{
+				case HALT://0 - Default state
+					CPU_state_old = HALT;//Save main current cycle
+					task.current_param = task.min_param;
+					Stop_TIM10();
+				break;
+				case DECODE_ENABLE://1 - Decode rec. message
+					CS_result = CalculateChecksum(COMMAND, CL_16-2);
+					if (CheckChecksum(COMMAND))
+					{
+						LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC & TEC1
+						LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2
+						Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup);
+						TO6_before = TO6;
+						//LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP;
+						//LD2_param.LD_TEMP_Before = LD2_param.LD_TEMP;
+						CPU_state = WORK_ENABLE;
+						CPU_state_old = WORK_ENABLE;//Save main current cycle
+					}
+					else
+					{
+						State_Data[0] |= UART_DECODE_ERR;
+						CPU_state = DEFAULT_ENABLE;
+						CPU_state_old = HALT;//Save main current cycle
+					}
+					UART_transmission_request = MESS_01;
+				break;
+				case DEFAULT_ENABLE://2 - Go to HALT
+					//Set current setup to default
+					task.current_param = task.min_param;
+					Stop_TIM10();
+					Init_params();
+					LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1
+					LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2
+					CPU_state = HALT;
+					CPU_state_old = HALT;//Save main current cycle
+					UART_transmission_request = MESS_01;
+				break;
+				case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting!
+					temp16 = SD_READ(&Long_Data[0]);
+					State_Data[0]|=temp16&0xff;
+					if (temp16==0)
+					{	
+						UART_transmission_request = MESS_03;
+					}
+					else
+					{
+						UART_transmission_request = MESS_01;
+					}
+					CPU_state_old = HALT;
+					CPU_state = CPU_state_old;//Return to main current cycle
+				break;
+				case TRANS_ENABLE://4 - Transmith current packet
+					UART_transmission_request = MESS_02;
+					CPU_state = CPU_state_old;//Return to main current cycle
+				break;
+				case REMOVE_FILE://5 - Remove file from SD
+					State_Data[0]|=SD_REMOVE()&0xff;
+					UART_transmission_request = MESS_01;
+					CPU_state = CPU_state_old;
+				break;
+				case STATE://6 - Transmith state message
+					UART_transmission_request = MESS_01;
+					CPU_state = CPU_state_old;//Return to main current cycle
+				break;
+				case WORK_ENABLE://7 - Main work cycle
+					task.current_param = task.min_param;
+					Stop_TIM10();
+					if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz)
+					{
+						TO7_before = TO7;
+						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+						
+						//Correct temperature in all pulses
+						(void) MPhD_T(3);
+						LD1_param.LD_CURR_TEMP = MPhD_T(3);
+						(void) MPhD_T(4);
+						LD2_param.LD_CURR_TEMP = MPhD_T(4);
+						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+						Set_LTEC(3, temp16);//Drive Laser TEC 1
+						temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2);
+						Set_LTEC(4, temp16);//Drive Laser TEC 2
+						
+						Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data
+						Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data
+
+						Set_LTEC(1,LD1_curr_setup.CURRENT);//Drive Laser diode 1
+						Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2
+
+						//Prepare DATA of internals ADCs
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(0);
+						temp16 = Get_ADC(1);
+						Long_Data[7] = temp16;
+						
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(1);
+						Long_Data[8] = temp16;
+						
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(1);
+						Long_Data[9] = temp16;
+						
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(1);
+						Long_Data[10] = temp16;
+						
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(1);
+						Long_Data[11] = temp16;
+						temp16 = Get_ADC(2);
+						
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(3);
+						temp16 = Get_ADC(4);
+						Long_Data[12] = temp16;
+						temp16 = Get_ADC(5);
+													
+						//Put the timer tick to Long_Data:
+						TO6_stop = TO6;
+						Long_Data[3] = (TO6_stop)&0xffff;
+						Long_Data[4] = (TO6_stop>>16)&0xffff;
+						
+						//Put the average temperature of LD1 to Long_Data:
+						Long_Data[5] = LD1_param.LD_CURR_TEMP;
+						
+						//Put the average temperature of LD2 to Long_Data:
+						Long_Data[6] = LD2_param.LD_CURR_TEMP;
+
+						if (Curr_setup.SD_EN==1)
+						{
+							CS_result = CalculateChecksum(&Long_Data[1], DL_16-2);
+							Long_Data[DL_16-1] = CS_result;
+							temp16 = SD_SAVE(&Long_Data[0]);
+							State_Data[0]|=temp16&0xff;
+						}
+						CPU_state_old = WORK_ENABLE;//Save main current cycle
+					}
+				break;
+				case DECODE_TASK:
+					if (CheckChecksum(COMMAND))
+					{
+						Decode_task(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup);
+						TO6_before = TO6;
+						CPU_state = RUN_TASK;
+						CPU_state_old = RUN_TASK;//Save main current cycle
+					}
+					else
+					{
+						State_Data[0] |= UART_DECODE_ERR;
+						CPU_state = DEFAULT_ENABLE;
+						CPU_state_old = HALT;//Save main current cycle
+					}
+					UART_transmission_request = MESS_01;
+				break;
+				case RUN_TASK:
+					switch (task.task_type)
+					{
+					case TT_CHANGE_CURR_1:
+						Set_LTEC(TT_CHANGE_CURR_2, task.curr);
+						(void) MPhD_T(TT_CHANGE_TEMP_1);
+						LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1);
+						(void) MPhD_T(TT_CHANGE_TEMP_2);
+						LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2);
+						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+						Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1
+						temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2);
+						Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2
+
+						// Toggle pin for oscilloscope
+						HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET);
+						HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET);
+		
+						st = HAL_TIM_Base_Start_IT(&htim10);
+						if (st != HAL_OK)
+							while(1);
+						while (task.current_param < task.max_param)
+						{
+							if (TIM10_coflag)
+							{
+								Set_LTEC(TT_CHANGE_CURR_1, task.current_param);
+								task.current_param += task.delta_param;
+								TO10 = 0;
+								TIM10_coflag = 0;
+							}
+						}
+						Stop_TIM10();
+						task.current_param = task.min_param;
+						Set_LTEC(TT_CHANGE_CURR_1, task.current_param);
+						if (task.tau > 3)
+						{
+							TIM10_period = htim10.Init.Period;
+							htim10.Init.Period = 9999;
+							TO10_counter = (task.tau - 1) * 100;
+						}
+						HAL_TIM_Base_Start_IT(&htim10);
+					break;
+					case TT_CHANGE_CURR_2:
+						Set_LTEC(TT_CHANGE_CURR_1, task.curr);
+						(void) MPhD_T(TT_CHANGE_TEMP_1);
+						LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1);
+						(void) MPhD_T(TT_CHANGE_TEMP_2);
+						LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2);
+						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+						Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1
+						temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2);
+						Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2
+
+						// Toggle pin for oscilloscope
+						HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET);
+						HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET);
+
+						st = HAL_TIM_Base_Start_IT(&htim10);
+						if (st != HAL_OK)
+							while(1);
+						while (task.current_param < task.max_param)
+						{
+							if (TIM10_coflag)
+							{
+								Set_LTEC(TT_CHANGE_CURR_2, task.current_param);
+								task.current_param += task.delta_param;
+								TO10 = 0;
+								TIM10_coflag = 0;
+							}
+						}
+						Stop_TIM10();
+						task.current_param = task.min_param;
+						Set_LTEC(TT_CHANGE_CURR_2, task.current_param);
+						if (task.tau > 3)
+						{
+							TIM10_period = htim10.Init.Period;
+							htim10.Init.Period = 9999;
+							TO10_counter = (task.tau - 1) * 100;
+						}
+						HAL_TIM_Base_Start_IT(&htim10);
+					break;
+					case TT_CHANGE_TEMP_1:
+						// isn't implemented
+					break;
+					case TT_CHANGE_TEMP_2:
+						// isn't implemented
+					break;
+					}
+	
+					if (TO7>TO7_before)
+					{
+						TO7_before = TO7;
+						
+						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+						
+						Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data
+						Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data
+	
+						//Prepare DATA of internals ADCs
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(0);
+						temp16 = Get_ADC(1);
+						Long_Data[7] = temp16;
+						
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(1);
+						Long_Data[8] = temp16;
+						
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(1);
+						Long_Data[9] = temp16;
+						
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(1);
+						Long_Data[10] = temp16;
+						
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(1);
+						Long_Data[11] = temp16;
+						temp16 = Get_ADC(2);
+						
+						//Put the temperature of LD2 to Long_Data:
+						temp16 = Get_ADC(3);
+						temp16 = Get_ADC(4);
+						Long_Data[12] = temp16;
+						temp16 = Get_ADC(5);
+													
+						//Put the timer tick to Long_Data:
+						TO6_stop = TO6;
+						Long_Data[3] = (TO6_stop)&0xffff;
+						Long_Data[4] = (TO6_stop>>16)&0xffff;
+						
+						//Put the average temperature of LD1 to Long_Data:
+						Long_Data[5] = LD1_param.LD_CURR_TEMP;
+						
+						//Put the average temperature of LD2 to Long_Data:
+						Long_Data[6] = LD2_param.LD_CURR_TEMP;
+					}
+					while (!TIM10_coflag);
+					
+					Stop_TIM10();
+					
+					if (task.tau > 3)
+					{
+						htim10.Init.Period = TIM10_period;
+						TO10_counter = task.dt / 10 - 1;
+					}
+					
+					CPU_state_old = RUN_TASK;
+        break;
+			}
+			
+		switch (UART_transmission_request)
+		{
+			case MESS_01://Default state
+				USART_TX(State_Data,2);
+				//HAL_UART_Transmit(&huart1, State_Data, 2, 10);
+				State_Data[0]=0;
+				State_Data[1]=0;//All OK!
+				UART_transmission_request = NO_MESS;
+			break;
+			case MESS_02://Transmith packet
+				
+				//Find CS and put to Long_Data:
+				CS_result = CalculateChecksum(&Long_Data[1], DL_16-2);
+				Long_Data[DL_16-1] = CS_result;
+				
+				for (uint16_t i = 0; i < DL_16; i++)
+				{
+					UART_DATA[i*2] = (Long_Data[i])&0xff;
+					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+				}
+				//HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0);
+				//HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
+				//HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8);
+				//huart1.gState = HAL_UART_STATE_READY;
+				//hdma_usart1_tx.State=HAL_DMA_STATE_BUSY;
+				USART_TX_DMA (DL_8);//Send data by USART using DMA
+				UART_transmission_request = NO_MESS;
+			break;
+			case MESS_03://Transmith saved packet
+				for (uint16_t i = 0; i < DL_16; i++)
+				{
+					UART_DATA[i*2] = (Long_Data[i])&0xff;
+					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+				}
+				//HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
+				//HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8);
+				//huart1.gState = HAL_UART_STATE_READY;
+				//hdma_usart1_tx.State=HAL_DMA_STATE_BUSY;
+				USART_TX_DMA (DL_8);//Send data by USART using DMA
+				UART_transmission_request = NO_MESS;
+			break;			
+		}
+    if ((flg_tmt==1)&&((TO6-TO6_uart)>100))//Uart timeout handle. if timeout beetween zero byte of command and right now longer than 1 sec.:
+		{
+			UART_rec_incr = 0;//Reset uart command counter
+			State_Data[0] |= UART_ERR;//timeout error!
+			UART_transmission_request = MESS_01;//Send status
+			flg_tmt = 0;//Reset timeout flag
+		}
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 25;
+  RCC_OscInitStruct.PLL.PLLN = 368;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 8;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Activate the Over-Drive mode
+  */
+  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+
+  /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8;
+  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.NbrOfConversion = 5;
+  hadc1.Init.DMAContinuousRequests = DISABLE;
+  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
+  */
+  sConfig.Channel = ADC_CHANNEL_9;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
+  */
+  sConfig.Channel = ADC_CHANNEL_8;
+  sConfig.Rank = ADC_REGULAR_RANK_2;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
+  */
+  sConfig.Channel = ADC_CHANNEL_2;
+  sConfig.Rank = ADC_REGULAR_RANK_3;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
+  */
+  sConfig.Channel = ADC_CHANNEL_10;
+  sConfig.Rank = ADC_REGULAR_RANK_4;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
+  */
+  sConfig.Channel = ADC_CHANNEL_11;
+  sConfig.Rank = ADC_REGULAR_RANK_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief ADC3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC3_Init(void)
+{
+
+  /* USER CODE BEGIN ADC3_Init 0 */
+
+  /* USER CODE END ADC3_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC3_Init 1 */
+
+  /* USER CODE END ADC3_Init 1 */
+
+  /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
+  */
+  hadc3.Instance = ADC3;
+  hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8;
+  hadc3.Init.Resolution = ADC_RESOLUTION_12B;
+  hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc3.Init.ContinuousConvMode = DISABLE;
+  hadc3.Init.DiscontinuousConvMode = DISABLE;
+  hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc3.Init.NbrOfConversion = 1;
+  hadc3.Init.DMAContinuousRequests = DISABLE;
+  hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  if (HAL_ADC_Init(&hadc3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
+  */
+  sConfig.Channel = ADC_CHANNEL_15;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
+  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC3_Init 2 */
+
+  /* USER CODE END ADC3_Init 2 */
+
+}
+
+/**
+  * @brief SDMMC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SDMMC1_SD_Init(void)
+{
+
+  /* USER CODE BEGIN SDMMC1_Init 0 */
+
+  /* USER CODE END SDMMC1_Init 0 */
+
+  /* USER CODE BEGIN SDMMC1_Init 1 */
+
+  /* USER CODE END SDMMC1_Init 1 */
+  hsd1.Instance = SDMMC1;
+  hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
+  hsd1.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE;
+  hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B;
+  hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+  hsd1.Init.ClockDiv = 20;
+  /* USER CODE BEGIN SDMMC1_Init 2 */
+
+  /* USER CODE END SDMMC1_Init 2 */
+
+}
+
+/**
+  * @brief SPI2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI2_Init(void)
+{
+
+  /* USER CODE BEGIN SPI2_Init 0 */
+
+  /* USER CODE END SPI2_Init 0 */
+
+  LL_SPI_InitTypeDef SPI_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2);
+
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB);
+  /**SPI2 GPIO Configuration
+  PB13   ------> SPI2_SCK
+  PB15   ------> SPI2_MOSI
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_13;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+  LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_15;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+  LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI2_Init 1 */
+
+  /* USER CODE END SPI2_Init 1 */
+  /* SPI2 parameter configuration*/
+  SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX;
+  SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+  SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+  SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+  SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE;
+  SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+  SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8;
+  SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+  SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+  SPI_InitStruct.CRCPoly = 7;
+  LL_SPI_Init(SPI2, &SPI_InitStruct);
+  LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA);
+  LL_SPI_DisableNSSPulseMgt(SPI2);
+  /* USER CODE BEGIN SPI2_Init 2 */
+
+  /* USER CODE END SPI2_Init 2 */
+
+}
+
+/**
+  * @brief SPI4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI4_Init(void)
+{
+
+  /* USER CODE BEGIN SPI4_Init 0 */
+
+  /* USER CODE END SPI4_Init 0 */
+
+  LL_SPI_InitTypeDef SPI_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI4);
+
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOE);
+  /**SPI4 GPIO Configuration
+  PE12   ------> SPI4_SCK
+  PE13   ------> SPI4_MISO
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_12;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+  LL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_13;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+  LL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI4_Init 1 */
+
+  /* USER CODE END SPI4_Init 1 */
+  /* SPI4 parameter configuration*/
+  SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX;
+  SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+  SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+  SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+  SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
+  SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+  SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+  SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+  SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+  SPI_InitStruct.CRCPoly = 7;
+  LL_SPI_Init(SPI4, &SPI_InitStruct);
+  LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA);
+  LL_SPI_DisableNSSPulseMgt(SPI4);
+  /* USER CODE BEGIN SPI4_Init 2 */
+
+  /* USER CODE END SPI4_Init 2 */
+
+}
+
+/**
+  * @brief SPI5 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI5_Init(void)
+{
+
+  /* USER CODE BEGIN SPI5_Init 0 */
+
+  /* USER CODE END SPI5_Init 0 */
+
+  LL_SPI_InitTypeDef SPI_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI5);
+
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF);
+  /**SPI5 GPIO Configuration
+  PF7   ------> SPI5_SCK
+  PF8   ------> SPI5_MISO
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_7;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+  LL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_8;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+  LL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI5_Init 1 */
+
+  /* USER CODE END SPI5_Init 1 */
+  /* SPI5 parameter configuration*/
+  SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX;
+  SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+  SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+  SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+  SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
+  SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+  SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+  SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+  SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+  SPI_InitStruct.CRCPoly = 7;
+  LL_SPI_Init(SPI5, &SPI_InitStruct);
+  LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA);
+  LL_SPI_DisableNSSPulseMgt(SPI5);
+  /* USER CODE BEGIN SPI5_Init 2 */
+
+  /* USER CODE END SPI5_Init 2 */
+
+}
+
+/**
+  * @brief SPI6 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI6_Init(void)
+{
+
+  /* USER CODE BEGIN SPI6_Init 0 */
+
+  /* USER CODE END SPI6_Init 0 */
+
+  LL_SPI_InitTypeDef SPI_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI6);
+
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);
+  /**SPI6 GPIO Configuration
+  PA5   ------> SPI6_SCK
+  PA7   ------> SPI6_MOSI
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_5;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_8;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_7;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_8;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI6_Init 1 */
+
+  /* USER CODE END SPI6_Init 1 */
+  /* SPI6 parameter configuration*/
+  SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX;
+  SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+  SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+  SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+  SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE;
+  SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+  SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+  SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+  SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+  SPI_InitStruct.CRCPoly = 7;
+  LL_SPI_Init(SPI6, &SPI_InitStruct);
+  LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA);
+  LL_SPI_DisableNSSPulseMgt(SPI6);
+  /* USER CODE BEGIN SPI6_Init 2 */
+
+  /* USER CODE END SPI6_Init 2 */
+
+}
+
+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  LL_TIM_InitTypeDef TIM_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
+
+  /* TIM2 interrupt Init */
+  NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(TIM2_IRQn);
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  TIM_InitStruct.Prescaler = 1000;
+  TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+  TIM_InitStruct.Autoreload = 840000;
+  TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+  LL_TIM_Init(TIM2, &TIM_InitStruct);
+  LL_TIM_DisableARRPreload(TIM2);
+  LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
+  LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET);
+  LL_TIM_DisableMasterSlaveMode(TIM2);
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+
+}
+
+/**
+  * @brief TIM5 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM5_Init(void)
+{
+
+  /* USER CODE BEGIN TIM5_Init 0 */
+
+  /* USER CODE END TIM5_Init 0 */
+
+  LL_TIM_InitTypeDef TIM_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5);
+
+  /* TIM5 interrupt Init */
+  NVIC_SetPriority(TIM5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(TIM5_IRQn);
+
+  /* USER CODE BEGIN TIM5_Init 1 */
+
+  /* USER CODE END TIM5_Init 1 */
+  TIM_InitStruct.Prescaler = 10000;
+  TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+  TIM_InitStruct.Autoreload = 560;
+  TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+  LL_TIM_Init(TIM5, &TIM_InitStruct);
+  LL_TIM_DisableARRPreload(TIM5);
+  LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL);
+  LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET);
+  LL_TIM_DisableMasterSlaveMode(TIM5);
+  /* USER CODE BEGIN TIM5_Init 2 */
+
+  /* USER CODE END TIM5_Init 2 */
+
+}
+
+/**
+  * @brief TIM6 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM6_Init(void)
+{
+
+  /* USER CODE BEGIN TIM6_Init 0 */
+
+  /* USER CODE END TIM6_Init 0 */
+
+  LL_TIM_InitTypeDef TIM_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6);
+
+  /* TIM6 interrupt Init */
+  NVIC_SetPriority(TIM6_DAC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(TIM6_DAC_IRQn);
+
+  /* USER CODE BEGIN TIM6_Init 1 */
+
+  /* USER CODE END TIM6_Init 1 */
+  TIM_InitStruct.Prescaler = 45999;
+  TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+  TIM_InitStruct.Autoreload = 19;
+  LL_TIM_Init(TIM6, &TIM_InitStruct);
+  LL_TIM_DisableARRPreload(TIM6);
+  LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE);
+  LL_TIM_DisableMasterSlaveMode(TIM6);
+  /* USER CODE BEGIN TIM6_Init 2 */
+
+  /* USER CODE END TIM6_Init 2 */
+
+}
+
+/**
+  * @brief TIM7 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM7_Init(void)
+{
+
+  /* USER CODE BEGIN TIM7_Init 0 */
+
+  /* USER CODE END TIM7_Init 0 */
+
+  LL_TIM_InitTypeDef TIM_InitStruct = {0};
+
+  /* Peripheral clock enable */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7);
+
+  /* TIM7 interrupt Init */
+  NVIC_SetPriority(TIM7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(TIM7_IRQn);
+
+  /* USER CODE BEGIN TIM7_Init 1 */
+
+  /* USER CODE END TIM7_Init 1 */
+  TIM_InitStruct.Prescaler = 919;
+  TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+  TIM_InitStruct.Autoreload = 99;
+  LL_TIM_Init(TIM7, &TIM_InitStruct);
+  LL_TIM_DisableARRPreload(TIM7);
+  LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE);
+  LL_TIM_DisableMasterSlaveMode(TIM7);
+  /* USER CODE BEGIN TIM7_Init 2 */
+
+  /* USER CODE END TIM7_Init 2 */
+
+}
+
+/**
+  * @brief TIM10 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM10_Init(void)
+{
+
+  /* USER CODE BEGIN TIM10_Init 0 */
+
+  /* USER CODE END TIM10_Init 0 */
+
+  /* USER CODE BEGIN TIM10_Init 1 */
+
+  /* USER CODE END TIM10_Init 1 */
+  htim10.Instance = TIM10;
+  htim10.Init.Prescaler = 183;
+  htim10.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim10.Init.Period = 9;
+  htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim10) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM10_Init 2 */
+
+  /* USER CODE END TIM10_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  LL_USART_InitTypeDef USART_InitStruct = {0};
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Initializes the peripherals clock
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+  PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* Peripheral clock enable */
+  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
+
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);
+  /**USART1 GPIO Configuration
+  PA9   ------> USART1_TX
+  PA10   ------> USART1_RX
+  */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_9;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_10;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USART1 DMA Init */
+
+  /* USART1_TX Init */
+  LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_7, LL_DMA_CHANNEL_4);
+
+  LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_7, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+
+  LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_7, LL_DMA_PRIORITY_VERYHIGH);
+
+  LL_DMA_SetMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MODE_NORMAL);
+
+  LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_PERIPH_NOINCREMENT);
+
+  LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MEMORY_INCREMENT);
+
+  LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_7, LL_DMA_PDATAALIGN_BYTE);
+
+  LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_7, LL_DMA_MDATAALIGN_BYTE);
+
+  LL_DMA_DisableFifoMode(DMA2, LL_DMA_STREAM_7);
+
+  /* USART1 interrupt Init */
+  NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(USART1_IRQn);
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  USART_InitStruct.BaudRate = 115200;
+  USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
+  USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
+  USART_InitStruct.Parity = LL_USART_PARITY_NONE;
+  USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
+  USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+  USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
+  LL_USART_Init(USART1, &USART_InitStruct);
+  LL_USART_ConfigAsyncMode(USART1);
+  LL_USART_Enable(USART1);
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void)
+{
+
+  /* Init with LL driver */
+  /* DMA controller clock enable */
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2);
+
+  /* DMA interrupt init */
+  /* DMA2_Stream7_IRQn interrupt configuration */
+  NVIC_SetPriority(DMA2_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+  NVIC_EnableIRQ(DMA2_Stream7_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+/* USER CODE BEGIN MX_GPIO_Init_1 */
+/* USER CODE END MX_GPIO_Init_1 */
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOF, ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOC, EN_5V2_Pin|EN_5V1_Pin|LD2_EN_Pin|TEC2_PD_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOA, TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_LD2_CS_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOE, ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, REF0_EN_Pin|TEC1_PD_Pin|DAC_LD1_CS_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOD, LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7, GPIO_PIN_RESET);
+
+  /*Configure GPIO pins : ADC_MPD2_CS_Pin SPI5_CNV_Pin ADC_ThrLD2_CS_Pin */
+  GPIO_InitStruct.Pin = ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : EN_5V2_Pin LD2_EN_Pin TEC2_PD_Pin */
+  GPIO_InitStruct.Pin = EN_5V2_Pin|LD2_EN_Pin|TEC2_PD_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : EN_5V1_Pin */
+  GPIO_InitStruct.Pin = EN_5V1_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  HAL_GPIO_Init(EN_5V1_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : TECEN1_Pin TECEN2_Pin REF2_ON_Pin DAC_TEC2_CS_Pin
+                           DAC_LD2_CS_Pin */
+  GPIO_InitStruct.Pin = TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_TEC2_CS_Pin
+                          |DAC_LD2_CS_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : TEC2_FLAG1_Pin TEC2_FLAG2_Pin TEC1_FLAG1_Pin TEC1_FLAG2_Pin */
+  GPIO_InitStruct.Pin = TEC2_FLAG1_Pin|TEC2_FLAG2_Pin|TEC1_FLAG1_Pin|TEC1_FLAG2_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : ADC_MPD1_CS_Pin ADC_ThrLD1_CS_Pin */
+  GPIO_InitStruct.Pin = ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : SPI4_CNV_Pin */
+  GPIO_InitStruct.Pin = SPI4_CNV_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  HAL_GPIO_Init(SPI4_CNV_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : REF0_EN_Pin TEC1_PD_Pin DAC_TEC1_CS_Pin DAC_LD1_CS_Pin */
+  GPIO_InitStruct.Pin = REF0_EN_Pin|TEC1_PD_Pin|DAC_TEC1_CS_Pin|DAC_LD1_CS_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : LD1_EN_Pin TEST_01_Pin PD7 */
+  GPIO_InitStruct.Pin = LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : USB_FLAG_Pin */
+  GPIO_InitStruct.Pin = USB_FLAG_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(USB_FLAG_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : SDMMC1_EN_Pin */
+  GPIO_InitStruct.Pin = SDMMC1_EN_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(SDMMC1_EN_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : FPGA_CONF_DONE_Pin */
+  GPIO_InitStruct.Pin = FPGA_CONF_DONE_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(FPGA_CONF_DONE_GPIO_Port, &GPIO_InitStruct);
+
+/* USER CODE BEGIN MX_GPIO_Init_2 */
+/* USER CODE END MX_GPIO_Init_2 */
+}
+
+/* USER CODE BEGIN 4 */
+
+//void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
+
+//	UART_transmission_request = NO_MESS;
+
+//}
+
+static void Init_params(void)
+{
+	TO6 = 0;
+	TO7 = 0;
+	TO7_before = 0;
+	TO6_before = 0;
+	TO6_uart = 0;
+	flg_tmt = 0;
+	UART_rec_incr = 0;
+	fgoto = 0;
+	sizeoffile = 0;
+	u_tx_flg = 0;
+	u_rx_flg = 0;
+	//State_Data[0]=0;
+	//State_Data[1]=0;//All OK!
+	for (uint16_t i=0; iWORK_EN = ((uint8_t)((*temp2)>>0))&0x01;
+	Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01;
+	Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01;
+	Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01;
+	Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01;
+	Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01;
+	Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01;
+	Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01;
+	Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01;
+	Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01;
+	Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01;
+	Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01;
+	Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01;
+	Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01;
+	
+	temp2++;
+	LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2);
+	temp2++;
+	LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2);
+	temp2++;
+	temp2++;
+	temp2++;
+	Curr_setup->AVERAGES = (uint16_t)(*temp2);
+	temp2++;
+	LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint16_t)(*temp2))*((float)(10)));
+	temp2++;
+	LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint16_t)(*temp2))*((float)(10)));
+	temp2++;
+	LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint16_t)(*temp2))*((float)(10)));
+	temp2++;
+	LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint16_t)(*temp2))*((float)(10)));
+	temp2++;
+	Long_Data[13] = (uint16_t)(*temp2);//Message ID
+	temp2++;
+	LD1_curr_setup->CURRENT = (uint16_t)(*temp2);
+	temp2++;
+	LD2_curr_setup->CURRENT = (uint16_t)(*temp2);
+	temp2++;
+	
+	if (Curr_setup->U5V1_EN)
+	{
+		HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_SET);
+	}
+	else
+	{
+		HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_RESET);
+	}
+	
+	if (Curr_setup->U5V2_EN)
+	{
+		HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_SET);
+	}
+	else
+	{
+		HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET);
+	}
+	
+	if (Curr_setup->LD1_EN)
+	{
+		HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_SET);
+		//LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC
+	}
+	else
+	{
+		HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET);
+		//LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC
+	}
+	
+	if (Curr_setup->LD2_EN)
+	{
+		HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_SET);
+		//LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC
+	}
+	else
+	{
+		HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET);
+		//LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC
+	}
+	
+	if (Curr_setup->REF1_EN)
+	{
+		HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_SET);
+	}
+	else
+	{
+		HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET);
+	}
+	
+	if (Curr_setup->REF2_EN)
+	{
+		HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_SET);
+	}
+	else
+	{
+		HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET);
+	}
+	
+	if ((Curr_setup->TS1_EN)&&(Curr_setup->TEC1_EN))
+	{
+		Set_LTEC(3,32767);
+		Set_LTEC(3,32767);
+		HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET);
+		HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET);
+	}
+	else
+	{
+		HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET);
+		HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET);		
+	}
+	
+	if ((Curr_setup->TS2_EN)&&(Curr_setup->TEC2_EN))
+	{
+		Set_LTEC(4,32767);
+		Set_LTEC(4,32767);
+		HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET);
+		HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET);
+	}
+	else
+	{
+		HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET);
+		HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET);		
+	}
+	
+	if (Curr_setup->PI1_RD==0)
+	{
+		LD1_curr_setup->P_coef_temp = 10;
+		LD1_curr_setup->I_coef_temp = 0.01;
+	}
+	
+	if (Curr_setup->PI2_RD==0)
+	{
+		LD2_curr_setup->P_coef_temp = 10;
+		LD2_curr_setup->I_coef_temp = 0.01;
+	}
+}
+
+static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_curr_setup, Work_SetupTypeDef *Curr_setup)
+{
+	uint16_t *temp2;
+
+	temp2 = (uint16_t *)Command;
+	Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01;
+	Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01;
+	Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01;
+	Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01;
+	Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01;
+	Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01;
+	Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01;
+	Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01;
+	Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01;
+	Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01;
+	Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01;
+	Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01;
+	Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01;
+	Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01;
+
+	temp2++;
+	task.task_type   = (uint8_t)(*temp2); temp2++;
+	task.min_param   = (float)(*temp2); temp2++;
+	task.max_param   = (float)(*temp2); temp2++;
+	task.delta_param = (float)(*temp2); temp2++;
+	task.dt          = (float)(*temp2) / 100.0; temp2++;
+	task.sec_param   = (float)(*temp2); temp2++;
+	task.curr        = (float)(*temp2); temp2++;
+	task.temp        = (float)(*temp2); temp2++;
+	task.tau         = (float)(*temp2); temp2++;
+	task.p_coef_1    = (float)(*temp2) * 256.0; temp2++;
+	task.i_coef_1    = (float)(*temp2) * 256.0; temp2++;
+	task.p_coef_2    = (float)(*temp2) * 256.0; temp2++;
+	task.i_coef_2    = (float)(*temp2) * 256.0; temp2++;
+	
+	TO10_counter = task.dt / 10 - 1;
+}
+
+void Set_LTEC(uint8_t num, uint16_t DATA)
+{
+	uint32_t tmp32;
+	switch (num)
+	{
+		case 1:
+			HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_RESET);//Start operation with LDAC1
+			//tmp32=0;
+			//while(tmp32<500){tmp32++;}
+			tmp32 = 0;
+			while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle will be end.
+			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+			tmp32 = 0;
+			while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle will be end.
+			(void) SPI2->DR;
+		break;
+		case 2:
+			HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_RESET);//Start operation with LDAC1
+			//tmp32=0;
+			//while(tmp32<500){tmp32++;}
+			tmp32 = 0;
+			while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle will be end.
+			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+			tmp32 = 0;
+			while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle will be end.
+			(void) SPI6->DR;
+		break;
+		case 3:
+			HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_RESET);//Start operation with LDAC1
+			//tmp32=0;
+			//while(tmp32<500){tmp32++;}
+			tmp32 = 0;
+			while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle will be end.
+			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+			tmp32 = 0;
+			while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle will be end.
+			(void) SPI2->DR;
+		break;
+		case 4:
+			HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_RESET);//Start operation with LDAC1
+			//tmp32=0;
+			//while(tmp32<500){tmp32++;}
+			tmp32 = 0;
+			while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle will be end.
+			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+			tmp32 = 0;
+			while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle will be end.
+			(void) SPI6->DR;
+		break;
+	}
+	HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1
+	HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2
+	HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1
+	HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2
+}
+static uint16_t MPhD_T(uint8_t num)
+{
+	uint16_t P;
+	uint32_t tmp32;
+	HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion
+	HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion
+	tmp32=0;
+	while(tmp32<500){tmp32++;}
+	HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conversion
+	HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conversion
+	tmp32=0;
+	while(tmp32<500){tmp32++;}
+	if (num==1)//MPD1
+	{
+		HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET);
+		HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET);
+		tmp32=0;
+		while(tmp32<500){tmp32++;}
+		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We can do that only by transmitting data... 
+		LL_SPI_Enable(SPI4);//Enable SPI for MPhD1 ADC
+		tmp32 = 0;
+		while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle will be end.
+		LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC
+		while(tmp32<500){tmp32++;}
+		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+		HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET);
+		P = LL_SPI_ReceiveData16(SPI4);
+	}
+	else if (num==2)//MPD2
+	{
+		HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET);
+		HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET);
+		tmp32=0;
+		while(tmp32<500){tmp32++;}
+		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We can do that only by transmitting data... 
+		LL_SPI_Enable(SPI5);//Enable SPI for MPhD2 ADC
+		tmp32 = 0;
+		while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle will be end.
+		LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC
+		while(tmp32<500){tmp32++;}
+		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+		HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET);
+		P = LL_SPI_ReceiveData16(SPI5);
+	}
+	else if (num==3)//ThrLD1
+	{
+		HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET);
+		HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET);
+		tmp32=0;
+		while(tmp32<500){tmp32++;}
+		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We can do that only by transmitting data... 
+		LL_SPI_Enable(SPI4);//Enable SPI for ThrLD1 ADC
+		tmp32 = 0;
+		while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle will be end.
+		LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC
+		while(tmp32<500){tmp32++;}
+		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+		HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET);
+		P = LL_SPI_ReceiveData16(SPI4);
+	}
+	else if (num==4)//ThrLD2
+	{
+		HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET);
+		HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET);
+		tmp32=0;
+		while(tmp32<500){tmp32++;}
+		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We can do that only by transmitting data... 
+		LL_SPI_Enable(SPI5);//Enable SPI for ThrLD2 ADC
+		tmp32 = 0;
+		while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle will be end.
+		LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC
+		while(tmp32<500){tmp32++;}
+		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+		HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET);
+		P = LL_SPI_ReceiveData16(SPI5);
+	}
+	/*float I_LD, Ith, I0m, T0m, Inorm, Tnorm1, Tnorm2, P, T_C, A, Pnorm;
+	
+	Inorm = (float) (65535) / (float) (100);
+	Tnorm1 = (float) (65535) / (float) (50);
+	Tnorm2 = 4;
+	Pnorm = (float)(65535) / (float)(20);
+	I0m = 8.1568;//@4 C - lowest temperature of system
+	T0m = 48.6282;
+	T_C = (float) (T_LD) / Tnorm1 + Tnorm2;
+	
+	Ith = I0m * expf(T_C/T0m);
+	I_LD = (float) (C_LD) / Inorm;
+	
+	if (I_LD > Ith)
+	{
+		A = (float) (2.24276128270098e-07) * T_C * T_C * T_C  - (float) (4.73392579025590e-05) * T_C * T_C + (float) (0.00157250618257057) * T_C + (float) (0.228565407377466);
+		P = A * (I_LD - Ith) * Pnorm;
+	}
+	else
+	{
+		P = 0;
+	}	*/
+	return P;
+}
+/*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Timer)
+{
+	uint16_t Result;
+//	uint8_t randf;
+	
+	randf = 0;
+	for (uint8_t i = 0; i < 32; i++)
+	{
+		randf = ((Timer>>i)&0x0001)^randf;
+	}
+	
+	Result = ((float)(T_LD - T_LD_before))*((float)(1-expf(((float)(Timer_before)-(float)(Timer))/((float)(100))))) + T_LD_before + (float)(randf);
+	
+	return (uint16_t)(Result);
+}*/
+static uint16_t Get_ADC(uint8_t num)
+{
+	uint16_t OUT;
+	switch (num)
+		{
+			case 0:
+				HAL_ADC_Start(&hadc1); // Power on
+			break;
+			case 1:
+				HAL_ADC_PollForConversion(&hadc1, 100); // Waiting for conversion
+        OUT = HAL_ADC_GetValue(&hadc1); // Get value adc
+			break;
+			case 2:
+				HAL_ADC_Stop(&hadc1); // Power off
+			break;
+			case 3:
+				HAL_ADC_Start(&hadc3); // Power on
+			break;
+			case 4:
+				HAL_ADC_PollForConversion(&hadc3, 100); // Waiting for conversion
+        OUT = HAL_ADC_GetValue(&hadc3); // Get value adc
+			break;
+			case 5:
+        HAL_ADC_Stop(&hadc3); // Power off
+			break;
+		}
+	return OUT;
+}
+uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results, uint8_t num)
+{			
+	int e_pid;
+	float P_coef_current;//, I_coef_current;
+	float e_integral;
+	int x_output;
+	
+	e_pid =  (int) LDx_results->LD_CURR_TEMP - (int) LDx_curr_setup->LD_TEMP;
+
+	e_integral = LDx_results->e_integral;
+	
+	if((e_pid < 3000) && (e_pid > - 3000)){
+		e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100;//100 - timer is too fast
+	}
+	P_coef_current = LDx_curr_setup->P_coef_temp;
+	
+	if (e_integral > 32000){
+			e_integral = 32000;
+	}
+	else if (e_integral < - 32000){
+			e_integral = -32000;
+	}
+	LDx_results->e_integral = e_integral;
+	
+	x_output = 32768 + P_coef_current * e_pid + (int)e_integral;//32768 - P_coef_current * e_pid - (int)e_integral;//
+	
+	if(x_output < 1000){
+		x_output = 8800;
+	}
+	else if(x_output > 56800){
+		x_output = 56800;
+	}
+	
+	if (num==2)
+		TO7_PID = TO7;//Save current time only on 2nd laser
+	
+	return (uint16_t)x_output;
+}
+uint8_t CheckChecksum(uint16_t *pbuff)
+{
+  uint16_t cl_ind;
+
+  switch (UART_header)
+  {
+    case 0x7777:
+      cl_ind = TSK_16 - 2;
+    break;
+    case 0x1111:
+      cl_ind = CL_16 - 2;
+    break;
+    default:
+      return 0;
+    break;
+  }
+
+  CS_result = CalculateChecksum(pbuff, cl_ind);
+
+  return ((CS_result == COMMAND[cl_ind]) ? 1 : 0);
+}
+uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len)
+{
+	short  i;
+	uint16_t cs = *pbuff;
+  
+ 	for(i = 1; i < len; i++)
+	{
+		cs ^= *(pbuff+i);
+	}
+	return cs;
+}
+
+/*int SD_Init(void)
+{
+	int test=0;
+	if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET)
+	{
+		test = Mount_SD("/");
+		if (test == 0) //0 - suc
+		{
+			//Format_SD();
+			test = Create_File("FILE1.TXT"); // 0 -suc
+			//Create_File("FILE2.TXT");
+			Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Viktor. Part ?01 (for DFB-1550-14BF lasers). Parameters of plate: Ilaser: 0...66.7 mA; Vlaser: 0...2 V; Itec: -1.27...1.27 A; Vtec: -2.56...2.56 V; IMphD: 0...519 uA; Tint: -1.2...+45.8 C; Text: -25.8...+43.4 C. Place for your advertising:..................................................................................................................................");
+			test = Unmount_SD("/"); // 0 - succ
+			return test;
+		}
+		else
+		{
+			return 1;
+		}
+	}
+	else
+	{
+		return 1;
+	}
+}*/
+
+int SD_SAVE(uint16_t *pbuff)
+{
+	int test=0;
+	if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET)
+	{
+		test = Mount_SD("/");
+		if (test == 0) //0 - suc
+		{
+			//Format_SD();
+			test = Update_File_byte("FILE1.TXT", (uint8_t *)pbuff, DL_8);
+			test = Unmount_SD("/"); // 0 - succ
+			return test;
+		}
+		else
+		{
+			return 1;
+		}
+	}
+	else
+	{
+		return 1;
+	}
+}
+
+
+
+//uint32_t Get_Length(void)
+//{
+//	return SD_matr[0][0] + ((uint32_t) (SD_matr[0][1])<<16);
+//}
+
+int SD_READ(uint16_t *pbuff)
+{
+	int test=0;
+	if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET)
+	{
+		test = Mount_SD("/");
+		if (test == 0) //0 - suc
+		{
+			//Format_SD();
+			test = Seek_Read_File ("FILE1.TXT", (uint8_t *)pbuff, DL_8, fgoto);//Read next 246 bytes
+			fgoto+=DL_8;
+			test = Unmount_SD("/"); // 0 - succ
+			return test;
+		}
+		else
+		{
+			return 1;
+		}
+	}
+	else
+	{
+		return 1;
+	}
+	
+/*	for (uint16_t j = 0; j < DL_16; j++)
+	{
+		*(pbuff+j) = SD_matr[SD_SLIDE][j];
+	}
+	if (SD_SLIDEInstance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+
+  /* USER CODE END ADC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**ADC1 GPIO Configuration
+    PC0     ------> ADC1_IN10
+    PC1     ------> ADC1_IN11
+    PA2     ------> ADC1_IN2
+    PB0     ------> ADC1_IN8
+    PB1     ------> ADC1_IN9
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* ADC1 interrupt Init */
+    HAL_NVIC_SetPriority(ADC_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(ADC_IRQn);
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+  else if(hadc->Instance==ADC3)
+  {
+  /* USER CODE BEGIN ADC3_MspInit 0 */
+
+  /* USER CODE END ADC3_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC3_CLK_ENABLE();
+
+    __HAL_RCC_GPIOF_CLK_ENABLE();
+    /**ADC3 GPIO Configuration
+    PF5     ------> ADC3_IN15
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+    /* ADC3 interrupt Init */
+    HAL_NVIC_SetPriority(ADC_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(ADC_IRQn);
+  /* USER CODE BEGIN ADC3_MspInit 1 */
+
+  /* USER CODE END ADC3_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ADC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+  /* USER CODE END ADC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ADC1_CLK_DISABLE();
+
+    /**ADC1 GPIO Configuration
+    PC0     ------> ADC1_IN10
+    PC1     ------> ADC1_IN11
+    PA2     ------> ADC1_IN2
+    PB0     ------> ADC1_IN8
+    PB1     ------> ADC1_IN9
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_1);
+
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1);
+
+    /* ADC1 interrupt DeInit */
+  /* USER CODE BEGIN ADC1:ADC_IRQn disable */
+    /**
+    * Uncomment the line below to disable the "ADC_IRQn" interrupt
+    * Be aware, disabling shared interrupt may affect other IPs
+    */
+    /* HAL_NVIC_DisableIRQ(ADC_IRQn); */
+  /* USER CODE END ADC1:ADC_IRQn disable */
+
+  /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+  /* USER CODE END ADC1_MspDeInit 1 */
+  }
+  else if(hadc->Instance==ADC3)
+  {
+  /* USER CODE BEGIN ADC3_MspDeInit 0 */
+
+  /* USER CODE END ADC3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ADC3_CLK_DISABLE();
+
+    /**ADC3 GPIO Configuration
+    PF5     ------> ADC3_IN15
+    */
+    HAL_GPIO_DeInit(GPIOF, GPIO_PIN_5);
+
+    /* ADC3 interrupt DeInit */
+  /* USER CODE BEGIN ADC3:ADC_IRQn disable */
+    /**
+    * Uncomment the line below to disable the "ADC_IRQn" interrupt
+    * Be aware, disabling shared interrupt may affect other IPs
+    */
+    /* HAL_NVIC_DisableIRQ(ADC_IRQn); */
+  /* USER CODE END ADC3:ADC_IRQn disable */
+
+  /* USER CODE BEGIN ADC3_MspDeInit 1 */
+
+  /* USER CODE END ADC3_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(hsd->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspInit 0 */
+
+  /* USER CODE END SDMMC1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_CLK48;
+    PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+    PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_SDMMC1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**SDMMC1 GPIO Configuration
+    PC8     ------> SDMMC1_D0
+    PC9     ------> SDMMC1_D1
+    PC10     ------> SDMMC1_D2
+    PC11     ------> SDMMC1_D3
+    PC12     ------> SDMMC1_CK
+    PD2     ------> SDMMC1_CMD
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
+                          |GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SDMMC1_MspInit 1 */
+
+  /* USER CODE END SDMMC1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
+{
+  if(hsd->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspDeInit 0 */
+
+  /* USER CODE END SDMMC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SDMMC1_CLK_DISABLE();
+
+    /**SDMMC1 GPIO Configuration
+    PC8     ------> SDMMC1_D0
+    PC9     ------> SDMMC1_D1
+    PC10     ------> SDMMC1_D2
+    PC11     ------> SDMMC1_D3
+    PC12     ------> SDMMC1_CK
+    PD2     ------> SDMMC1_CMD
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
+                          |GPIO_PIN_12);
+
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
+
+  /* USER CODE BEGIN SDMMC1_MspDeInit 1 */
+
+  /* USER CODE END SDMMC1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Base MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM10)
+  {
+  /* USER CODE BEGIN TIM10_MspInit 0 */
+
+  /* USER CODE END TIM10_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM10_CLK_ENABLE();
+    /* TIM10 interrupt Init */
+    HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
+  /* USER CODE BEGIN TIM10_MspInit 1 */
+
+  /* USER CODE END TIM10_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Base MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM10)
+  {
+  /* USER CODE BEGIN TIM10_MspDeInit 0 */
+
+  /* USER CODE END TIM10_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM10_CLK_DISABLE();
+
+    /* TIM10 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);
+  /* USER CODE BEGIN TIM10_MspDeInit 1 */
+
+  /* USER CODE END TIM10_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Src/stm32f7xx_it.c b/Src/stm32f7xx_it.c
new file mode 100644
index 0000000..e5ec1a3
--- /dev/null
+++ b/Src/stm32f7xx_it.c
@@ -0,0 +1,496 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f7xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+	extern uint32_t TO6, TO7, TO6_uart, TO10, TO10_counter;
+	extern uint16_t UART_rec_incr, UART_header, COMMAND[CL_16];
+	extern uint8_t uart_buf, flg_tmt, CPU_state, State_Data[2], UART_transmission_request, u_tx_flg, TIM10_coflag;
+	extern  task_t task;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+void UART_RxCpltCallback(void);
+void DMA2_Stream7_TransferComplete(void);
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern ADC_HandleTypeDef hadc1;
+extern ADC_HandleTypeDef hadc3;
+extern TIM_HandleTypeDef htim10;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M7 Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+  while (1)
+  {
+  }
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F7xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32f7xx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles ADC1, ADC2 and ADC3 global interrupts.
+  */
+void ADC_IRQHandler(void)
+{
+  /* USER CODE BEGIN ADC_IRQn 0 */
+
+  /* USER CODE END ADC_IRQn 0 */
+  HAL_ADC_IRQHandler(&hadc1);
+  HAL_ADC_IRQHandler(&hadc3);
+  /* USER CODE BEGIN ADC_IRQn 1 */
+
+  /* USER CODE END ADC_IRQn 1 */
+}
+
+/**
+  * @brief This function handles TIM1 update interrupt and TIM10 global interrupt.
+  */
+void TIM1_UP_TIM10_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */
+	TO10++;
+	if (TO10 == TO10_counter)
+		TIM10_coflag = 1;
+  /* USER CODE END TIM1_UP_TIM10_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim10);
+  /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */
+
+  /* USER CODE END TIM1_UP_TIM10_IRQn 1 */
+}
+
+/**
+  * @brief This function handles TIM2 global interrupt.
+  */
+void TIM2_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM2_IRQn 0 */
+
+  /* USER CODE END TIM2_IRQn 0 */
+  /* USER CODE BEGIN TIM2_IRQn 1 */
+
+  /* USER CODE END TIM2_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+  volatile uint8_t temp;
+  if(LL_USART_IsActiveFlag_RXNE(USART1) && LL_USART_IsEnabledIT_RXNE(USART1))
+  {
+    UART_RxCpltCallback();
+  }
+  else
+  {
+    if(LL_USART_IsActiveFlag_ORE(USART1))
+    {
+      //temp = USART1->RDR;
+      temp+= LL_USART_ReceiveData8(USART1);
+    }
+    else if(LL_USART_IsActiveFlag_FE(USART1))
+    {
+      //(void) USART1->RDR;
+      temp+= LL_USART_ReceiveData8(USART1);
+    }
+    else if(LL_USART_IsActiveFlag_NE(USART1))
+    {
+      //(void) USART1->RDR;
+      temp+= LL_USART_ReceiveData8(USART1);
+    }
+    else if(LL_USART_IsActiveFlag_PE(USART1))
+    {
+      //(void) USART1->RDR;
+      temp+= LL_USART_ReceiveData8(USART1);
+    }
+    else
+    {
+      if(LL_USART_IsActiveFlag_TC(USART6) && LL_USART_IsEnabledIT_TC(USART6))
+      {		
+        LL_USART_ClearFlag_TC(USART1);
+        //test_counter += 1;
+        //if(UART_transmission_busy == 1){
+        LL_USART_DisableIT_TC(USART1);
+        //UART_transmission_busy = 0;
+      }
+    }
+  }
+	
+  /* USER CODE END USART1_IRQn 0 */
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles TIM5 global interrupt.
+  */
+void TIM5_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM5_IRQn 0 */
+
+  /* USER CODE END TIM5_IRQn 0 */
+  /* USER CODE BEGIN TIM5_IRQn 1 */
+
+  /* USER CODE END TIM5_IRQn 1 */
+}
+
+/**
+  * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
+  */
+void TIM6_DAC_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
+
+  /* USER CODE END TIM6_DAC_IRQn 0 */
+
+  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
+  if(LL_TIM_IsActiveFlag_UPDATE(TIM6))
+  {
+    LL_TIM_ClearFlag_UPDATE(TIM6);
+    TO6++;//increment tick
+    //10 ms or 100 Hz
+    HAL_GPIO_TogglePin(TEST_01_GPIO_Port, TEST_01_Pin);
+    //HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_12);
+  }
+  /* USER CODE END TIM6_DAC_IRQn 1 */
+}
+
+/**
+  * @brief This function handles TIM7 global interrupt.
+  */
+void TIM7_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM7_IRQn 0 */
+
+  /* USER CODE END TIM7_IRQn 0 */
+  /* USER CODE BEGIN TIM7_IRQn 1 */
+  if(LL_TIM_IsActiveFlag_UPDATE(TIM7))
+  {
+    LL_TIM_ClearFlag_UPDATE(TIM7);
+    TO7++;
+    //1 ms or 1000 Hz
+    //HAL_GPIO_TogglePin(TEST_01_GPIO_Port, TEST_01_Pin);
+  }
+  /* USER CODE END TIM7_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 stream7 global interrupt.
+  */
+void DMA2_Stream7_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
+  if(LL_DMA_IsActiveFlag_TC7(DMA2) == 1)
+  {
+    DMA2_Stream7_TransferComplete();
+    u_tx_flg = 0;//indicate that transfer compete
+  }
+  else if(LL_DMA_IsActiveFlag_TE7(DMA2) == 1)
+  {
+    LL_DMA_ClearFlag_TE7(DMA2);
+  }
+  /* USER CODE END DMA2_Stream7_IRQn 0 */
+
+  /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */
+
+  /* USER CODE END DMA2_Stream7_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+void UART_RxCpltCallback(void)
+{
+    uart_buf = LL_USART_ReceiveData8(USART1);
+    switch (UART_rec_incr)
+    {
+    case 0:
+        TO6_uart = TO6;//Save the time of start rec. command
+        flg_tmt = 1;//Set the timeout flag
+        UART_header = uart_buf;
+        UART_rec_incr++;
+    break;
+    case 1:
+        UART_header += ((uint16_t)uart_buf<<8);
+        switch (UART_header)
+        {
+        case 0x1111: //received long packet
+            UART_rec_incr = 2;//timeout flag is still setting!
+        break;
+        case 0x2222: //Back to default
+            UART_rec_incr = 0;
+            flg_tmt = 0;//Reset the timeout flag
+            CPU_state = DEFAULT_ENABLE;
+        break;
+        case 0x3333: //Transmith saved DATA
+            UART_rec_incr = 0;
+            flg_tmt = 0;//Reset the timeout flag
+            CPU_state = TRANS_S_ENABLE;
+        break;
+        case 0x4444: //Received packet
+            UART_rec_incr = 0;
+            flg_tmt = 0;//Reset the timeout flag
+            CPU_state = TRANS_ENABLE;
+        break;
+        case 0x5555: //Erase saved DATA
+            UART_rec_incr = 0;
+            flg_tmt = 0;//Reset the timeout flag
+            CPU_state = REMOVE_FILE;
+        break;
+        case 0x6666: //Request state
+            UART_rec_incr = 0;
+            flg_tmt = 0;//Reset the timeout flag
+            CPU_state = STATE;
+        break;
+        case 0x7777:
+            UART_rec_incr = 2;//timeout flag is still setting!
+            break;
+        default: //error decoding header
+            UART_rec_incr = 0;
+            flg_tmt = 0;//Reset the timeout flag
+            //UART_transmission_request = MESS_01;
+            //CPU_state = HALT;
+            State_Data[0] |= UART_ERR;
+            CPU_state = DEFAULT_ENABLE;//Parking system and send error state!
+        break;
+        }
+    break;
+
+    case (CL_8 - 1):
+        if (UART_header == 0x1111)
+        {
+            if ((UART_rec_incr & 0x0001) > 0)
+                COMMAND[(UART_rec_incr >> 1) - 1] += ((uint16_t)(uart_buf)) << 8;
+            else
+                COMMAND[(UART_rec_incr >> 1) - 1] = (uint16_t)(uart_buf);
+            CPU_state = DECODE_ENABLE;
+            UART_rec_incr = 0;
+            flg_tmt = 0;//Reset the timeout flag
+        }
+        else
+        {
+            if ((UART_rec_incr&0x0001)>0)
+                COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+            else
+                COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf);
+           UART_rec_incr++;
+           UART_transmission_request = NO_MESS;
+        }
+    break;
+    case (TSK_8 - 1):
+        if (UART_header == 0x7777)
+        {
+            if ((UART_rec_incr&0x0001)>0)
+    	          COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+    	      else
+                COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf);
+            CPU_state = DECODE_TASK;
+            UART_rec_incr = 0;
+            flg_tmt = 0;//Reset the timeout flag
+        }
+        else
+        {
+            if ((UART_rec_incr&0x0001)>0)
+                COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+            else
+                COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf);
+            UART_rec_incr++;
+            UART_transmission_request = NO_MESS;
+        }
+    break;
+    default:
+        if ((UART_rec_incr&0x0001)>0)
+            COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+        else
+            COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf);
+        UART_rec_incr++;
+        UART_transmission_request = NO_MESS;
+    break;
+    }
+//    HAL_UART_Receive_IT(&huart1, &uart_buf, 1);
+}
+
+//-----------------------------------------------
+void DMA2_Stream7_TransferComplete(void)
+{
+  LL_DMA_ClearFlag_TC7(DMA2);
+}
+//-----------------------------------------------
+/* USER CODE END 1 */
diff --git a/Src/syscalls.c b/Src/syscalls.c
new file mode 100644
index 0000000..e33a849
--- /dev/null
+++ b/Src/syscalls.c
@@ -0,0 +1,176 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeMX
+ * @brief     Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2020-2024 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+  return 1;
+}
+
+int _kill(int pid, int sig)
+{
+  (void)pid;
+  (void)sig;
+  errno = EINVAL;
+  return -1;
+}
+
+void _exit (int status)
+{
+  _kill(status, -1);
+  while (1) {}    /* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+  (void)file;
+  int DataIdx;
+
+  for (DataIdx = 0; DataIdx < len; DataIdx++)
+  {
+    *ptr++ = __io_getchar();
+  }
+
+  return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+  (void)file;
+  int DataIdx;
+
+  for (DataIdx = 0; DataIdx < len; DataIdx++)
+  {
+    __io_putchar(*ptr++);
+  }
+  return len;
+}
+
+int _close(int file)
+{
+  (void)file;
+  return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+  (void)file;
+  st->st_mode = S_IFCHR;
+  return 0;
+}
+
+int _isatty(int file)
+{
+  (void)file;
+  return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+  (void)file;
+  (void)ptr;
+  (void)dir;
+  return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+  (void)path;
+  (void)flags;
+  /* Pretend like we always fail */
+  return -1;
+}
+
+int _wait(int *status)
+{
+  (void)status;
+  errno = ECHILD;
+  return -1;
+}
+
+int _unlink(char *name)
+{
+  (void)name;
+  errno = ENOENT;
+  return -1;
+}
+
+int _times(struct tms *buf)
+{
+  (void)buf;
+  return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+  (void)file;
+  st->st_mode = S_IFCHR;
+  return 0;
+}
+
+int _link(char *old, char *new)
+{
+  (void)old;
+  (void)new;
+  errno = EMLINK;
+  return -1;
+}
+
+int _fork(void)
+{
+  errno = EAGAIN;
+  return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+  (void)name;
+  (void)argv;
+  (void)env;
+  errno = ENOMEM;
+  return -1;
+}
diff --git a/Src/sysmem.c b/Src/sysmem.c
new file mode 100644
index 0000000..246470e
--- /dev/null
+++ b/Src/sysmem.c
@@ -0,0 +1,79 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Generated by STM32CubeMX
+ * @brief     System Memory calls file
+ *
+ *            For more information about which C functions
+ *            need which of these lowlevel functions
+ *            please consult the newlib libc manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2024 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include 
+#include 
+
+/**
+ * Pointer to the current high watermark of the heap usage
+ */
+static uint8_t *__sbrk_heap_end = NULL;
+
+/**
+ * @brief _sbrk() allocates memory to the newlib heap and is used by malloc
+ *        and others from the C library
+ *
+ * @verbatim
+ * ############################################################################
+ * #  .data  #  .bss  #       newlib heap       #          MSP stack          #
+ * #         #        #                         # Reserved by _Min_Stack_Size #
+ * ############################################################################
+ * ^-- RAM start      ^-- _end                             _estack, RAM end --^
+ * @endverbatim
+ *
+ * This implementation starts allocating at the '_end' linker symbol
+ * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
+ * The implementation considers '_estack' linker symbol to be RAM end
+ * NOTE: If the MSP stack, at any point during execution, grows larger than the
+ * reserved size, please increase the '_Min_Stack_Size'.
+ *
+ * @param incr Memory size
+ * @return Pointer to allocated memory
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+  extern uint8_t _end; /* Symbol defined in the linker script */
+  extern uint8_t _estack; /* Symbol defined in the linker script */
+  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+  const uint8_t *max_heap = (uint8_t *)stack_limit;
+  uint8_t *prev_heap_end;
+
+  /* Initialize heap end at first call */
+  if (NULL == __sbrk_heap_end)
+  {
+    __sbrk_heap_end = &_end;
+  }
+
+  /* Protect heap from growing into the reserved MSP stack */
+  if (__sbrk_heap_end + incr > max_heap)
+  {
+    errno = ENOMEM;
+    return (void *)-1;
+  }
+
+  prev_heap_end = __sbrk_heap_end;
+  __sbrk_heap_end += incr;
+
+  return (void *)prev_heap_end;
+}
diff --git a/Src/system_stm32f7xx.c b/Src/system_stm32f7xx.c
new file mode 100644
index 0000000..c004f47
--- /dev/null
+++ b/Src/system_stm32f7xx.c
@@ -0,0 +1,259 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f7xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f7xx.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in Flash or Sram, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   RAMDTCM_BASE    /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Variables
+  * @{
+  */
+
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 16000000;
+  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+  const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/build/For_stm32.map b/build/For_stm32.map
new file mode 100644
index 0000000..2a07e4f
--- /dev/null
+++ b/build/For_stm32.map
@@ -0,0 +1,4199 @@
+Archive member included to satisfy reference by file (symbol)
+
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+/usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-errno.o)
+                              build/sysmem.o (__errno)
+/usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-exit.o)
+                              /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (exit)
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+                              /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (__libc_fini_array)
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+                              /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-exit.o) (_global_impure_ptr)
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+Memory Configuration
+
+Name             Origin             Length             Attributes
+RAM              0x0000000020000000 0x0000000000080000 xrw
+FLASH            0x0000000008000000 0x0000000000200000 xr
+*default*        0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crti.o
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+LOAD build/main.o
+LOAD build/bsp_driver_sd.o
+LOAD build/sd_diskio.o
+LOAD build/fatfs.o
+LOAD build/fatfs_platform.o
+LOAD build/stm32f7xx_it.o
+LOAD build/stm32f7xx_hal_msp.o
+LOAD build/stm32f7xx_hal_adc.o
+LOAD build/stm32f7xx_hal_adc_ex.o
+LOAD build/stm32f7xx_hal_rcc.o
+LOAD build/stm32f7xx_hal_rcc_ex.o
+LOAD build/stm32f7xx_hal_flash.o
+LOAD build/stm32f7xx_hal_flash_ex.o
+LOAD build/stm32f7xx_hal_gpio.o
+LOAD build/stm32f7xx_hal_dma.o
+LOAD build/stm32f7xx_hal_dma_ex.o
+LOAD build/stm32f7xx_hal_pwr.o
+LOAD build/stm32f7xx_hal_pwr_ex.o
+LOAD build/stm32f7xx_hal_cortex.o
+LOAD build/stm32f7xx_hal.o
+LOAD build/stm32f7xx_hal_i2c.o
+LOAD build/stm32f7xx_hal_i2c_ex.o
+LOAD build/stm32f7xx_hal_exti.o
+LOAD build/stm32f7xx_ll_rcc.o
+LOAD build/stm32f7xx_ll_utils.o
+LOAD build/stm32f7xx_ll_exti.o
+LOAD build/stm32f7xx_ll_gpio.o
+LOAD build/stm32f7xx_ll_dma.o
+LOAD build/stm32f7xx_ll_sdmmc.o
+LOAD build/stm32f7xx_hal_sd.o
+LOAD build/stm32f7xx_ll_spi.o
+LOAD build/stm32f7xx_hal_tim.o
+LOAD build/stm32f7xx_hal_tim_ex.o
+LOAD build/stm32f7xx_ll_tim.o
+LOAD build/stm32f7xx_ll_usart.o
+LOAD build/system_stm32f7xx.o
+LOAD build/diskio.o
+LOAD build/ff.o
+LOAD build/ff_gen_drv.o
+LOAD build/syscall.o
+LOAD build/sysmem.o
+LOAD build/syscalls.o
+LOAD build/startup_stm32f767xx.o
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libm.a
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libnosys.a
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a
+END GROUP
+START GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a
+END GROUP
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtend.o
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtn.o
+                0x0000000020080000                _estack = (ORIGIN (RAM) + LENGTH (RAM))
+                0x0000000000002000                _Min_Heap_Size = 0x2000
+                0x0000000000004000                _Min_Stack_Size = 0x4000
+
+.isr_vector     0x0000000008000000      0x1f8
+                0x0000000008000000                . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x0000000008000000      0x1f8 build/startup_stm32f767xx.o
+                0x0000000008000000                g_pfnVectors
+                0x00000000080001f8                . = ALIGN (0x4)
+
+.text           0x00000000080001f8     0x65b4
+                0x00000000080001f8                . = ALIGN (0x4)
+ *(.text)
+ .text          0x00000000080001f8       0x88 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+ .text          0x0000000008000280       0x48 /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o)
+                0x0000000008000280                __libc_init_array
+ .text          0x00000000080002c8       0xa4 /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-memset.o)
+                0x00000000080002c8                memset
+ .text          0x000000000800036c       0x30 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o)
+                0x000000000800036c                __aeabi_uldivmod
+ .text          0x000000000800039c      0x2d0 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o)
+                0x000000000800039c                __udivmoddi4
+ .text          0x000000000800066c        0x4 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o)
+                0x000000000800066c                __aeabi_ldiv0
+                0x000000000800066c                __aeabi_idiv0
+ *(.text*)
+ .text.NVIC_EncodePriority
+                0x0000000008000670       0x36 build/main.o
+ *fill*         0x00000000080006a6        0x2 
+ .text.MX_SDMMC1_SD_Init
+                0x00000000080006a8       0x24 build/main.o
+ .text.MX_DMA_Init
+                0x00000000080006cc       0x48 build/main.o
+ *fill*         0x0000000008000714        0x4 
+ .text.Decode_task
+                0x0000000008000718      0x168 build/main.o
+ .text.PID_Controller_Temp
+                0x0000000008000880       0xe4 build/main.o
+ .text.Set_LTEC
+                0x0000000008000964      0x158 build/main.o
+ .text.MPhD_T   0x0000000008000abc      0x224 build/main.o
+ .text.MX_GPIO_Init
+                0x0000000008000ce0      0x210 build/main.o
+ .text.MX_SPI4_Init
+                0x0000000008000ef0       0xd4 build/main.o
+ .text.MX_SPI2_Init
+                0x0000000008000fc4       0xd0 build/main.o
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+                0x00000000080060c8       0x90 build/stm32f7xx_hal_tim.o
+                0x00000000080060c8                HAL_TIM_Base_Start_IT
+ .text.HAL_TIM_Base_Stop_IT
+                0x0000000008006158       0x32 build/stm32f7xx_hal_tim.o
+                0x0000000008006158                HAL_TIM_Base_Stop_IT
+ .text.HAL_TIM_PeriodElapsedCallback
+                0x000000000800618a        0x2 build/stm32f7xx_hal_tim.o
+                0x000000000800618a                HAL_TIM_PeriodElapsedCallback
+ .text.HAL_TIM_OC_DelayElapsedCallback
+                0x000000000800618c        0x2 build/stm32f7xx_hal_tim.o
+                0x000000000800618c                HAL_TIM_OC_DelayElapsedCallback
+ .text.HAL_TIM_IC_CaptureCallback
+                0x000000000800618e        0x2 build/stm32f7xx_hal_tim.o
+                0x000000000800618e                HAL_TIM_IC_CaptureCallback
+ .text.HAL_TIM_PWM_PulseFinishedCallback
+                0x0000000008006190        0x2 build/stm32f7xx_hal_tim.o
+                0x0000000008006190                HAL_TIM_PWM_PulseFinishedCallback
+ .text.HAL_TIM_TriggerCallback
+                0x0000000008006192        0x2 build/stm32f7xx_hal_tim.o
+                0x0000000008006192                HAL_TIM_TriggerCallback
+ .text.HAL_TIM_IRQHandler
+                0x0000000008006194      0x17a build/stm32f7xx_hal_tim.o
+                0x0000000008006194                HAL_TIM_IRQHandler
+ *fill*         0x000000000800630e        0x2 
+ .text.TIM_Base_SetConfig
+                0x0000000008006310      0x120 build/stm32f7xx_hal_tim.o
+                0x0000000008006310                TIM_Base_SetConfig
+ .text.HAL_TIM_Base_Init
+                0x0000000008006430       0x60 build/stm32f7xx_hal_tim.o
+                0x0000000008006430                HAL_TIM_Base_Init
+ .text.HAL_TIMEx_CommutCallback
+                0x0000000008006490        0x2 build/stm32f7xx_hal_tim_ex.o
+                0x0000000008006490                HAL_TIMEx_CommutCallback
+ .text.HAL_TIMEx_BreakCallback
+                0x0000000008006492        0x2 build/stm32f7xx_hal_tim_ex.o
+                0x0000000008006492                HAL_TIMEx_BreakCallback
+ .text.HAL_TIMEx_Break2Callback
+                0x0000000008006494        0x2 build/stm32f7xx_hal_tim_ex.o
+                0x0000000008006494                HAL_TIMEx_Break2Callback
+ *fill*         0x0000000008006496        0x2 
+ .text.LL_TIM_Init
+                0x0000000008006498      0x110 build/stm32f7xx_ll_tim.o
+                0x0000000008006498                LL_TIM_Init
+ .text.LL_USART_Init
+                0x00000000080065a8      0x124 build/stm32f7xx_ll_usart.o
+                0x00000000080065a8                LL_USART_Init
+ .text.SystemInit
+                0x00000000080066cc       0x14 build/system_stm32f7xx.o
+                0x00000000080066cc                SystemInit
+ .text.FATFS_LinkDriverEx
+                0x00000000080066e0       0x54 build/ff_gen_drv.o
+                0x00000000080066e0                FATFS_LinkDriverEx
+ .text.FATFS_LinkDriver
+                0x0000000008006734        0xa build/ff_gen_drv.o
+                0x0000000008006734                FATFS_LinkDriver
+ *fill*         0x000000000800673e        0x2 
+ .text.Reset_Handler
+                0x0000000008006740       0x50 build/startup_stm32f767xx.o
+                0x0000000008006740                Reset_Handler
+ .text.Default_Handler
+                0x0000000008006790        0x2 build/startup_stm32f767xx.o
+                0x0000000008006790                RTC_Alarm_IRQHandler
+                0x0000000008006790                EXTI2_IRQHandler
+                0x0000000008006790                TIM8_CC_IRQHandler
+                0x0000000008006790                UART8_IRQHandler
+                0x0000000008006790                SPI4_IRQHandler
+                0x0000000008006790                TIM1_CC_IRQHandler
+                0x0000000008006790                DMA2_Stream5_IRQHandler
+                0x0000000008006790                JPEG_IRQHandler
+                0x0000000008006790                DMA1_Stream5_IRQHandler
+                0x0000000008006790                CAN3_RX1_IRQHandler
+                0x0000000008006790                PVD_IRQHandler
+                0x0000000008006790                TAMP_STAMP_IRQHandler
+                0x0000000008006790                CAN2_RX1_IRQHandler
+                0x0000000008006790                EXTI3_IRQHandler
+                0x0000000008006790                TIM8_TRG_COM_TIM14_IRQHandler
+                0x0000000008006790                DFSDM1_FLT1_IRQHandler
+                0x0000000008006790                TIM8_UP_TIM13_IRQHandler
+                0x0000000008006790                I2C3_ER_IRQHandler
+                0x0000000008006790                DFSDM1_FLT2_IRQHandler
+                0x0000000008006790                EXTI0_IRQHandler
+                0x0000000008006790                I2C2_EV_IRQHandler
+                0x0000000008006790                DMA1_Stream2_IRQHandler
+                0x0000000008006790                CAN1_RX0_IRQHandler
+                0x0000000008006790                FPU_IRQHandler
+                0x0000000008006790                OTG_HS_WKUP_IRQHandler
+                0x0000000008006790                CAN3_SCE_IRQHandler
+                0x0000000008006790                LTDC_ER_IRQHandler
+                0x0000000008006790                CAN2_SCE_IRQHandler
+                0x0000000008006790                DMA2_Stream2_IRQHandler
+                0x0000000008006790                SPI1_IRQHandler
+                0x0000000008006790                TIM1_BRK_TIM9_IRQHandler
+                0x0000000008006790                DCMI_IRQHandler
+                0x0000000008006790                CAN2_RX0_IRQHandler
+                0x0000000008006790                DMA2_Stream3_IRQHandler
+                0x0000000008006790                SAI2_IRQHandler
+                0x0000000008006790                DFSDM1_FLT3_IRQHandler
+                0x0000000008006790                USART6_IRQHandler
+                0x0000000008006790                CAN3_RX0_IRQHandler
+                0x0000000008006790                USART3_IRQHandler
+                0x0000000008006790                CAN1_RX1_IRQHandler
+                0x0000000008006790                UART5_IRQHandler
+                0x0000000008006790                DMA2_Stream0_IRQHandler
+                0x0000000008006790                TIM4_IRQHandler
+                0x0000000008006790                QUADSPI_IRQHandler
+                0x0000000008006790                I2C1_EV_IRQHandler
+                0x0000000008006790                DMA1_Stream6_IRQHandler
+                0x0000000008006790                DMA1_Stream1_IRQHandler
+                0x0000000008006790                UART4_IRQHandler
+                0x0000000008006790                TIM3_IRQHandler
+                0x0000000008006790                RCC_IRQHandler
+                0x0000000008006790                TIM8_BRK_TIM12_IRQHandler
+                0x0000000008006790                Default_Handler
+                0x0000000008006790                CEC_IRQHandler
+                0x0000000008006790                EXTI15_10_IRQHandler
+                0x0000000008006790                DMA1_Stream7_IRQHandler
+                0x0000000008006790                SPI5_IRQHandler
+                0x0000000008006790                SDMMC1_IRQHandler
+                0x0000000008006790                CAN2_TX_IRQHandler
+                0x0000000008006790                I2C3_EV_IRQHandler
+                0x0000000008006790                EXTI9_5_IRQHandler
+                0x0000000008006790                RTC_WKUP_IRQHandler
+                0x0000000008006790                LTDC_IRQHandler
+                0x0000000008006790                ETH_WKUP_IRQHandler
+                0x0000000008006790                SPDIF_RX_IRQHandler
+                0x0000000008006790                SPI2_IRQHandler
+                0x0000000008006790                OTG_HS_EP1_IN_IRQHandler
+                0x0000000008006790                DMA1_Stream0_IRQHandler
+                0x0000000008006790                CAN1_TX_IRQHandler
+                0x0000000008006790                EXTI4_IRQHandler
+                0x0000000008006790                RNG_IRQHandler
+                0x0000000008006790                ETH_IRQHandler
+                0x0000000008006790                OTG_HS_EP1_OUT_IRQHandler
+                0x0000000008006790                WWDG_IRQHandler
+                0x0000000008006790                SPI6_IRQHandler
+                0x0000000008006790                MDIOS_IRQHandler
+                0x0000000008006790                I2C4_EV_IRQHandler
+                0x0000000008006790                CAN3_TX_IRQHandler
+                0x0000000008006790                OTG_FS_WKUP_IRQHandler
+                0x0000000008006790                TIM1_TRG_COM_TIM11_IRQHandler
+                0x0000000008006790                OTG_HS_IRQHandler
+                0x0000000008006790                DMA2D_IRQHandler
+                0x0000000008006790                EXTI1_IRQHandler
+                0x0000000008006790                SDMMC2_IRQHandler
+                0x0000000008006790                UART7_IRQHandler
+                0x0000000008006790                USART2_IRQHandler
+                0x0000000008006790                DFSDM1_FLT0_IRQHandler
+                0x0000000008006790                I2C2_ER_IRQHandler
+                0x0000000008006790                DMA2_Stream1_IRQHandler
+                0x0000000008006790                CAN1_SCE_IRQHandler
+                0x0000000008006790                FLASH_IRQHandler
+                0x0000000008006790                DMA2_Stream4_IRQHandler
+                0x0000000008006790                OTG_FS_IRQHandler
+                0x0000000008006790                SPI3_IRQHandler
+                0x0000000008006790                DMA1_Stream4_IRQHandler
+                0x0000000008006790                I2C1_ER_IRQHandler
+                0x0000000008006790                FMC_IRQHandler
+                0x0000000008006790                LPTIM1_IRQHandler
+                0x0000000008006790                I2C4_ER_IRQHandler
+                0x0000000008006790                DMA2_Stream6_IRQHandler
+                0x0000000008006790                SAI1_IRQHandler
+                0x0000000008006790                DMA1_Stream3_IRQHandler
+ *(.glue_7)
+ .glue_7        0x0000000008006792        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x0000000008006792        0x0 linker stubs
+ *(.eh_frame)
+ *fill*         0x0000000008006792        0x2 
+ .eh_frame      0x0000000008006794        0x0 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+ *(.init)
+ .init          0x0000000008006794        0x4 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crti.o
+                0x0000000008006794                _init
+ .init          0x0000000008006798        0x8 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtn.o
+ *(.fini)
+ .fini          0x00000000080067a0        0x4 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crti.o
+                0x00000000080067a0                _fini
+ .fini          0x00000000080067a4        0x8 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtn.o
+                0x00000000080067ac                . = ALIGN (0x4)
+                0x00000000080067ac                _etext = .
+
+.vfp11_veneer   0x00000000080067ac        0x0
+ .vfp11_veneer  0x00000000080067ac        0x0 linker stubs
+
+.v4_bx          0x00000000080067ac        0x0
+ .v4_bx         0x00000000080067ac        0x0 linker stubs
+
+.iplt           0x00000000080067ac        0x0
+ .iplt          0x00000000080067ac        0x0 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+
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+                0x00000000080067ac                . = ALIGN (0x4)
+ *(.rodata)
+ *(.rodata*)
+ .rodata.Decode_uart.str1.4
+                0x00000000080067ac       0x10 build/main.o
+ .rodata.SD_SAVE.str1.4
+                0x00000000080067bc        0xa build/main.o
+ *fill*         0x00000000080067c6        0x2 
+ .rodata.SD_Driver
+                0x00000000080067c8       0x14 build/sd_diskio.o
+                0x00000000080067c8                SD_Driver
+ .rodata.AHBPrescTable
+                0x00000000080067dc       0x10 build/system_stm32f7xx.o
+                0x00000000080067dc                AHBPrescTable
+ .rodata.APBPrescTable
+                0x00000000080067ec        0x8 build/system_stm32f7xx.o
+                0x00000000080067ec                APBPrescTable
+                0x00000000080067f4                . = ALIGN (0x4)
+
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+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
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+                0x00000000080067f4                __exidx_start = .
+ *(.ARM.exidx*)
+ .ARM.exidx     0x00000000080067f4        0x8 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o)
+                0x00000000080067fc                __exidx_end = .
+
+.rel.dyn        0x00000000080067fc        0x0
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+
+.preinit_array  0x00000000080067fc        0x0
+                0x00000000080067fc                PROVIDE (__preinit_array_start = .)
+ *(.preinit_array*)
+                0x00000000080067fc                PROVIDE (__preinit_array_end = .)
+
+.init_array     0x00000000080067fc        0x4
+                0x00000000080067fc                PROVIDE (__init_array_start = .)
+ *(SORT_BY_NAME(.init_array.*))
+ *(.init_array*)
+ .init_array    0x00000000080067fc        0x4 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+                0x0000000008006800                PROVIDE (__init_array_end = .)
+
+.fini_array     0x0000000008006800        0x4
+                0x0000000008006800                PROVIDE (__fini_array_start = .)
+ *(SORT_BY_NAME(.fini_array.*))
+ *(.fini_array*)
+ .fini_array    0x0000000008006800        0x4 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+                0x0000000008006804                PROVIDE (__fini_array_end = .)
+                0x0000000008006804                _sidata = LOADADDR (.data)
+
+.data           0x0000000020000000        0xc load address 0x0000000008006804
+                0x0000000020000000                . = ALIGN (0x4)
+                0x0000000020000000                _sdata = .
+ *(.data)
+ *(.data*)
+ .data.Stat     0x0000000020000000        0x1 build/sd_diskio.o
+ .data.uwTickFreq
+                0x0000000020000001        0x1 build/stm32f7xx_hal.o
+                0x0000000020000001                uwTickFreq
+ *fill*         0x0000000020000002        0x2 
+ .data.uwTickPrio
+                0x0000000020000004        0x4 build/stm32f7xx_hal.o
+                0x0000000020000004                uwTickPrio
+ .data.SystemCoreClock
+                0x0000000020000008        0x4 build/system_stm32f7xx.o
+                0x0000000020000008                SystemCoreClock
+                0x000000002000000c                . = ALIGN (0x4)
+                0x000000002000000c                _edata = .
+
+.tm_clone_table
+                0x000000002000000c        0x0 load address 0x0000000008006810
+ .tm_clone_table
+                0x000000002000000c        0x0 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+ .tm_clone_table
+                0x000000002000000c        0x0 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtend.o
+
+.igot.plt       0x000000002000000c        0x0 load address 0x0000000008006810
+ .igot.plt      0x000000002000000c        0x0 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+                0x000000002000000c                . = ALIGN (0x4)
+
+.bss            0x000000002000000c      0x2fc load address 0x0000000008006810
+                0x000000002000000c                _sbss = .
+                0x000000002000000c                __bss_start__ = _sbss
+ *(.bss)
+ .bss           0x000000002000000c       0x1c /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+ *(.bss*)
+ .bss.COMMAND   0x0000000020000028       0x1e build/main.o
+                0x0000000020000028                COMMAND
+ .bss.CPU_state
+                0x0000000020000046        0x1 build/main.o
+                0x0000000020000046                CPU_state
+ .bss.CPU_state_old
+                0x0000000020000047        0x1 build/main.o
+                0x0000000020000047                CPU_state_old
+ .bss.CS_result
+                0x0000000020000048        0x2 build/main.o
+                0x0000000020000048                CS_result
+ *fill*         0x000000002000004a        0x2 
+ .bss.Curr_setup
+                0x000000002000004c       0x12 build/main.o
+                0x000000002000004c                Curr_setup
+ *fill*         0x000000002000005e        0x2 
+ .bss.Def_setup
+                0x0000000020000060       0x12 build/main.o
+                0x0000000020000060                Def_setup
+ *fill*         0x0000000020000072        0x2 
+ .bss.LD1_curr_setup
+                0x0000000020000074       0x10 build/main.o
+                0x0000000020000074                LD1_curr_setup
+ .bss.LD1_def_setup
+                0x0000000020000084       0x10 build/main.o
+                0x0000000020000084                LD1_def_setup
+ .bss.LD1_param
+                0x0000000020000094        0xc build/main.o
+                0x0000000020000094                LD1_param
+ .bss.LD2_curr_setup
+                0x00000000200000a0       0x10 build/main.o
+                0x00000000200000a0                LD2_curr_setup
+ .bss.LD2_def_setup
+                0x00000000200000b0       0x10 build/main.o
+                0x00000000200000b0                LD2_def_setup
+ .bss.LD2_param
+                0x00000000200000c0        0xc build/main.o
+                0x00000000200000c0                LD2_param
+ .bss.Long_Data
+                0x00000000200000cc       0x1e build/main.o
+                0x00000000200000cc                Long_Data
+ *fill*         0x00000000200000ea        0x2 
+ .bss.SD_SEEK   0x00000000200000ec        0x4 build/main.o
+                0x00000000200000ec                SD_SEEK
+ .bss.SD_SLIDE  0x00000000200000f0        0x4 build/main.o
+                0x00000000200000f0                SD_SLIDE
+ .bss.State_Data
+                0x00000000200000f4        0x2 build/main.o
+                0x00000000200000f4                State_Data
+ .bss.TIM10_coflag
+                0x00000000200000f6        0x1 build/main.o
+                0x00000000200000f6                TIM10_coflag
+ *fill*         0x00000000200000f7        0x1 
+ .bss.TIM10_period
+                0x00000000200000f8        0x4 build/main.o
+                0x00000000200000f8                TIM10_period
+ .bss.TO10      0x00000000200000fc        0x4 build/main.o
+                0x00000000200000fc                TO10
+ .bss.TO10_counter
+                0x0000000020000100        0x4 build/main.o
+                0x0000000020000100                TO10_counter
+ .bss.TO6       0x0000000020000104        0x4 build/main.o
+                0x0000000020000104                TO6
+ .bss.TO6_before
+                0x0000000020000108        0x4 build/main.o
+                0x0000000020000108                TO6_before
+ .bss.TO6_stop  0x000000002000010c        0x4 build/main.o
+                0x000000002000010c                TO6_stop
+ .bss.TO6_uart  0x0000000020000110        0x4 build/main.o
+                0x0000000020000110                TO6_uart
+ .bss.TO7       0x0000000020000114        0x4 build/main.o
+                0x0000000020000114                TO7
+ .bss.TO7_PID   0x0000000020000118        0x4 build/main.o
+                0x0000000020000118                TO7_PID
+ .bss.TO7_before
+                0x000000002000011c        0x4 build/main.o
+                0x000000002000011c                TO7_before
+ .bss.UART_DATA
+                0x0000000020000120       0x1e build/main.o
+                0x0000000020000120                UART_DATA
+ .bss.UART_header
+                0x000000002000013e        0x2 build/main.o
+                0x000000002000013e                UART_header
+ .bss.UART_rec_incr
+                0x0000000020000140        0x2 build/main.o
+                0x0000000020000140                UART_rec_incr
+ .bss.UART_transmission_request
+                0x0000000020000142        0x1 build/main.o
+                0x0000000020000142                UART_transmission_request
+ *fill*         0x0000000020000143        0x1 
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+                0x0000000020000144                fgoto
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+                0x0000000020000148                flg_tmt
+ *fill*         0x0000000020000149        0x3 
+ .bss.hadc1     0x000000002000014c       0x48 build/main.o
+                0x000000002000014c                hadc1
+ .bss.hadc3     0x0000000020000194       0x48 build/main.o
+                0x0000000020000194                hadc3
+ .bss.hsd1      0x00000000200001dc       0x84 build/main.o
+                0x00000000200001dc                hsd1
+ .bss.htim10    0x0000000020000260       0x4c build/main.o
+                0x0000000020000260                htim10
+ .bss.sizeoffile
+                0x00000000200002ac        0x4 build/main.o
+                0x00000000200002ac                sizeoffile
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+                0x00000000200002b0                task
+ .bss.temp16    0x00000000200002e4        0x2 build/main.o
+                0x00000000200002e4                temp16
+ *fill*         0x00000000200002e6        0x2 
+ .bss.test      0x00000000200002e8        0x4 build/main.o
+                0x00000000200002e8                test
+ .bss.u_rx_flg  0x00000000200002ec        0x1 build/main.o
+                0x00000000200002ec                u_rx_flg
+ .bss.u_tx_flg  0x00000000200002ed        0x1 build/main.o
+                0x00000000200002ed                u_tx_flg
+ .bss.uart_buf  0x00000000200002ee        0x1 build/main.o
+                0x00000000200002ee                uart_buf
+ *fill*         0x00000000200002ef        0x1 
+ .bss.SDPath    0x00000000200002f0        0x4 build/fatfs.o
+                0x00000000200002f0                SDPath
+ .bss.retSD     0x00000000200002f4        0x1 build/fatfs.o
+                0x00000000200002f4                retSD
+ *fill*         0x00000000200002f5        0x3 
+ .bss.uwTick    0x00000000200002f8        0x4 build/stm32f7xx_hal.o
+                0x00000000200002f8                uwTick
+ .bss.disk      0x00000000200002fc        0xc build/ff_gen_drv.o
+                0x00000000200002fc                disk
+ *(COMMON)
+                0x0000000020000308                . = ALIGN (0x4)
+                0x0000000020000308                _ebss = .
+                0x0000000020000308                __bss_end__ = _ebss
+
+._user_heap_stack
+                0x0000000020000308     0x6000 load address 0x0000000008006810
+                0x0000000020000308                . = ALIGN (0x8)
+                [!provide]                        PROVIDE (end = .)
+                0x0000000020000308                PROVIDE (_end = .)
+                0x0000000020002308                . = (. + _Min_Heap_Size)
+ *fill*         0x0000000020000308     0x2000 
+                0x0000000020006308                . = (. + _Min_Stack_Size)
+ *fill*         0x0000000020002308     0x4000 
+                0x0000000020006308                . = ALIGN (0x8)
+
+/DISCARD/
+ libc.a(*)
+ libm.a(*)
+ libgcc.a(*)
+OUTPUT(build/For_stm32.elf elf32-littlearm)
+LOAD linker stubs
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libm.a
+LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a
+
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+ .debug_line    0x0000000000017892       0x60 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o)
+
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+
+Cross Reference Table
+
+Symbol                                            File
+ADC_IRQHandler                                    build/stm32f7xx_it.o
+AHBPrescTable                                     build/system_stm32f7xx.o
+                                                  build/stm32f7xx_ll_utils.o
+                                                  build/stm32f7xx_ll_rcc.o
+                                                  build/stm32f7xx_hal_rcc.o
+APBPrescTable                                     build/system_stm32f7xx.o
+                                                  build/stm32f7xx_ll_rcc.o
+                                                  build/stm32f7xx_hal_rcc.o
+BSP_PlatformIsDetected                            build/fatfs_platform.o
+                                                  build/bsp_driver_sd.o
+BSP_SD_AbortCallback                              build/bsp_driver_sd.o
+BSP_SD_Erase                                      build/bsp_driver_sd.o
+BSP_SD_GetCardInfo                                build/bsp_driver_sd.o
+                                                  build/sd_diskio.o
+BSP_SD_GetCardState                               build/bsp_driver_sd.o
+                                                  build/sd_diskio.o
+BSP_SD_ITConfig                                   build/bsp_driver_sd.o
+BSP_SD_Init                                       build/bsp_driver_sd.o
+                                                  build/sd_diskio.o
+BSP_SD_IsDetected                                 build/bsp_driver_sd.o
+BSP_SD_ReadBlocks                                 build/bsp_driver_sd.o
+                                                  build/sd_diskio.o
+BSP_SD_ReadBlocks_DMA                             build/bsp_driver_sd.o
+BSP_SD_ReadCpltCallback                           build/bsp_driver_sd.o
+BSP_SD_WriteBlocks                                build/bsp_driver_sd.o
+                                                  build/sd_diskio.o
+BSP_SD_WriteBlocks_DMA                            build/bsp_driver_sd.o
+BSP_SD_WriteCpltCallback                          build/bsp_driver_sd.o
+BusFault_Handler                                  build/stm32f7xx_it.o
+CAN1_RX0_IRQHandler                               build/startup_stm32f767xx.o
+CAN1_RX1_IRQHandler                               build/startup_stm32f767xx.o
+CAN1_SCE_IRQHandler                               build/startup_stm32f767xx.o
+CAN1_TX_IRQHandler                                build/startup_stm32f767xx.o
+CAN2_RX0_IRQHandler                               build/startup_stm32f767xx.o
+CAN2_RX1_IRQHandler                               build/startup_stm32f767xx.o
+CAN2_SCE_IRQHandler                               build/startup_stm32f767xx.o
+CAN2_TX_IRQHandler                                build/startup_stm32f767xx.o
+CAN3_RX0_IRQHandler                               build/startup_stm32f767xx.o
+CAN3_RX1_IRQHandler                               build/startup_stm32f767xx.o
+CAN3_SCE_IRQHandler                               build/startup_stm32f767xx.o
+CAN3_TX_IRQHandler                                build/startup_stm32f767xx.o
+CEC_IRQHandler                                    build/startup_stm32f767xx.o
+COMMAND                                           build/main.o
+                                                  build/stm32f7xx_it.o
+CPU_state                                         build/main.o
+                                                  build/stm32f7xx_it.o
+CPU_state_old                                     build/main.o
+CS_result                                         build/main.o
+CalculateChecksum                                 build/main.o
+CheckChecksum                                     build/main.o
+Create_File                                       build/main.o
+Curr_setup                                        build/main.o
+DCMI_IRQHandler                                   build/startup_stm32f767xx.o
+DFSDM1_FLT0_IRQHandler                            build/startup_stm32f767xx.o
+DFSDM1_FLT1_IRQHandler                            build/startup_stm32f767xx.o
+DFSDM1_FLT2_IRQHandler                            build/startup_stm32f767xx.o
+DFSDM1_FLT3_IRQHandler                            build/startup_stm32f767xx.o
+DMA1_Stream0_IRQHandler                           build/startup_stm32f767xx.o
+DMA1_Stream1_IRQHandler                           build/startup_stm32f767xx.o
+DMA1_Stream2_IRQHandler                           build/startup_stm32f767xx.o
+DMA1_Stream3_IRQHandler                           build/startup_stm32f767xx.o
+DMA1_Stream4_IRQHandler                           build/startup_stm32f767xx.o
+DMA1_Stream5_IRQHandler                           build/startup_stm32f767xx.o
+DMA1_Stream6_IRQHandler                           build/startup_stm32f767xx.o
+DMA1_Stream7_IRQHandler                           build/startup_stm32f767xx.o
+DMA2D_IRQHandler                                  build/startup_stm32f767xx.o
+DMA2_Stream0_IRQHandler                           build/startup_stm32f767xx.o
+DMA2_Stream1_IRQHandler                           build/startup_stm32f767xx.o
+DMA2_Stream2_IRQHandler                           build/startup_stm32f767xx.o
+DMA2_Stream3_IRQHandler                           build/startup_stm32f767xx.o
+DMA2_Stream4_IRQHandler                           build/startup_stm32f767xx.o
+DMA2_Stream5_IRQHandler                           build/startup_stm32f767xx.o
+DMA2_Stream6_IRQHandler                           build/startup_stm32f767xx.o
+DMA2_Stream7_IRQHandler                           build/stm32f7xx_it.o
+DMA2_Stream7_TransferComplete                     build/stm32f7xx_it.o
+DebugMon_Handler                                  build/stm32f7xx_it.o
+Def_setup                                         build/main.o
+Default_Handler                                   build/startup_stm32f767xx.o
+ETH_IRQHandler                                    build/startup_stm32f767xx.o
+ETH_WKUP_IRQHandler                               build/startup_stm32f767xx.o
+EXTI0_IRQHandler                                  build/startup_stm32f767xx.o
+EXTI15_10_IRQHandler                              build/startup_stm32f767xx.o
+EXTI1_IRQHandler                                  build/startup_stm32f767xx.o
+EXTI2_IRQHandler                                  build/startup_stm32f767xx.o
+EXTI3_IRQHandler                                  build/startup_stm32f767xx.o
+EXTI4_IRQHandler                                  build/startup_stm32f767xx.o
+EXTI9_5_IRQHandler                                build/startup_stm32f767xx.o
+Error_Handler                                     build/main.o
+                                                  build/stm32f7xx_hal_msp.o
+FATFS_GetAttachedDriversNbr                       build/ff_gen_drv.o
+FATFS_LinkDriver                                  build/ff_gen_drv.o
+                                                  build/fatfs.o
+FATFS_LinkDriverEx                                build/ff_gen_drv.o
+FATFS_UnLinkDriver                                build/ff_gen_drv.o
+FATFS_UnLinkDriverEx                              build/ff_gen_drv.o
+FLASH_Erase_Sector                                build/stm32f7xx_hal_flash_ex.o
+                                                  build/stm32f7xx_hal_flash.o
+FLASH_IRQHandler                                  build/startup_stm32f767xx.o
+FLASH_WaitForLastOperation                        build/stm32f7xx_hal_flash.o
+                                                  build/stm32f7xx_hal_flash_ex.o
+FMC_IRQHandler                                    build/startup_stm32f767xx.o
+FPU_IRQHandler                                    build/startup_stm32f767xx.o
+HAL_ADCEx_InjectedConfigChannel                   build/stm32f7xx_hal_adc_ex.o
+HAL_ADCEx_InjectedConvCpltCallback                build/stm32f7xx_hal_adc_ex.o
+                                                  build/stm32f7xx_hal_adc.o
+HAL_ADCEx_InjectedGetValue                        build/stm32f7xx_hal_adc_ex.o
+HAL_ADCEx_InjectedPollForConversion               build/stm32f7xx_hal_adc_ex.o
+HAL_ADCEx_InjectedStart                           build/stm32f7xx_hal_adc_ex.o
+HAL_ADCEx_InjectedStart_IT                        build/stm32f7xx_hal_adc_ex.o
+HAL_ADCEx_InjectedStop                            build/stm32f7xx_hal_adc_ex.o
+HAL_ADCEx_InjectedStop_IT                         build/stm32f7xx_hal_adc_ex.o
+HAL_ADCEx_MultiModeConfigChannel                  build/stm32f7xx_hal_adc_ex.o
+HAL_ADCEx_MultiModeGetValue                       build/stm32f7xx_hal_adc_ex.o
+HAL_ADCEx_MultiModeStart_DMA                      build/stm32f7xx_hal_adc_ex.o
+HAL_ADCEx_MultiModeStop_DMA                       build/stm32f7xx_hal_adc_ex.o
+HAL_ADC_AnalogWDGConfig                           build/stm32f7xx_hal_adc.o
+HAL_ADC_ConfigChannel                             build/stm32f7xx_hal_adc.o
+                                                  build/main.o
+HAL_ADC_ConvCpltCallback                          build/stm32f7xx_hal_adc.o
+                                                  build/stm32f7xx_hal_adc_ex.o
+HAL_ADC_ConvHalfCpltCallback                      build/stm32f7xx_hal_adc.o
+                                                  build/stm32f7xx_hal_adc_ex.o
+HAL_ADC_DeInit                                    build/stm32f7xx_hal_adc.o
+HAL_ADC_ErrorCallback                             build/stm32f7xx_hal_adc.o
+                                                  build/stm32f7xx_hal_adc_ex.o
+HAL_ADC_GetError                                  build/stm32f7xx_hal_adc.o
+HAL_ADC_GetState                                  build/stm32f7xx_hal_adc.o
+HAL_ADC_GetValue                                  build/stm32f7xx_hal_adc.o
+                                                  build/main.o
+HAL_ADC_IRQHandler                                build/stm32f7xx_hal_adc.o
+                                                  build/stm32f7xx_it.o
+HAL_ADC_Init                                      build/stm32f7xx_hal_adc.o
+                                                  build/main.o
+HAL_ADC_LevelOutOfWindowCallback                  build/stm32f7xx_hal_adc.o
+HAL_ADC_MspDeInit                                 build/stm32f7xx_hal_msp.o
+HAL_ADC_MspInit                                   build/stm32f7xx_hal_msp.o
+HAL_ADC_PollForConversion                         build/stm32f7xx_hal_adc.o
+                                                  build/main.o
+HAL_ADC_PollForEvent                              build/stm32f7xx_hal_adc.o
+HAL_ADC_Start                                     build/stm32f7xx_hal_adc.o
+                                                  build/main.o
+HAL_ADC_Start_DMA                                 build/stm32f7xx_hal_adc.o
+HAL_ADC_Start_IT                                  build/stm32f7xx_hal_adc.o
+HAL_ADC_Stop                                      build/stm32f7xx_hal_adc.o
+                                                  build/main.o
+HAL_ADC_Stop_DMA                                  build/stm32f7xx_hal_adc.o
+HAL_ADC_Stop_IT                                   build/stm32f7xx_hal_adc.o
+HAL_DBGMCU_DisableDBGSleepMode                    build/stm32f7xx_hal.o
+HAL_DBGMCU_DisableDBGStandbyMode                  build/stm32f7xx_hal.o
+HAL_DBGMCU_DisableDBGStopMode                     build/stm32f7xx_hal.o
+HAL_DBGMCU_EnableDBGSleepMode                     build/stm32f7xx_hal.o
+HAL_DBGMCU_EnableDBGStandbyMode                   build/stm32f7xx_hal.o
+HAL_DBGMCU_EnableDBGStopMode                      build/stm32f7xx_hal.o
+HAL_DMAEx_ChangeMemory                            build/stm32f7xx_hal_dma_ex.o
+HAL_DMAEx_MultiBufferStart                        build/stm32f7xx_hal_dma_ex.o
+HAL_DMAEx_MultiBufferStart_IT                     build/stm32f7xx_hal_dma_ex.o
+HAL_DMA_Abort                                     build/stm32f7xx_hal_dma.o
+                                                  build/stm32f7xx_hal_sd.o
+                                                  build/stm32f7xx_hal_adc_ex.o
+                                                  build/stm32f7xx_hal_adc.o
+HAL_DMA_Abort_IT                                  build/stm32f7xx_hal_dma.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+                                                  build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_sd.o
+                                                  build/stm32f7xx_hal_i2c.o
+HAL_DMA_DeInit                                    build/stm32f7xx_hal_dma.o
+HAL_DMA_GetError                                  build/stm32f7xx_hal_dma.o
+                                                  build/stm32f7xx_hal_sd.o
+                                                  build/stm32f7xx_hal_i2c.o
+HAL_DMA_GetState                                  build/stm32f7xx_hal_dma.o
+                                                  build/stm32f7xx_hal_i2c.o
+HAL_DMA_IRQHandler                                build/stm32f7xx_hal_dma.o
+HAL_DMA_Init                                      build/stm32f7xx_hal_dma.o
+HAL_DMA_PollForTransfer                           build/stm32f7xx_hal_dma.o
+HAL_DMA_RegisterCallback                          build/stm32f7xx_hal_dma.o
+HAL_DMA_Start                                     build/stm32f7xx_hal_dma.o
+HAL_DMA_Start_IT                                  build/stm32f7xx_hal_dma.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+                                                  build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_sd.o
+                                                  build/stm32f7xx_hal_i2c.o
+                                                  build/stm32f7xx_hal_adc_ex.o
+                                                  build/stm32f7xx_hal_adc.o
+HAL_DMA_UnRegisterCallback                        build/stm32f7xx_hal_dma.o
+HAL_DeInit                                        build/stm32f7xx_hal.o
+HAL_Delay                                         build/stm32f7xx_hal.o
+                                                  build/stm32f7xx_hal_sd.o
+HAL_DisableCompensationCell                       build/stm32f7xx_hal.o
+HAL_DisableFMCMemorySwapping                      build/stm32f7xx_hal.o
+HAL_DisableMemorySwappingBank                     build/stm32f7xx_hal.o
+HAL_EXTI_ClearConfigLine                          build/stm32f7xx_hal_exti.o
+HAL_EXTI_ClearPending                             build/stm32f7xx_hal_exti.o
+HAL_EXTI_GenerateSWI                              build/stm32f7xx_hal_exti.o
+HAL_EXTI_GetConfigLine                            build/stm32f7xx_hal_exti.o
+HAL_EXTI_GetHandle                                build/stm32f7xx_hal_exti.o
+HAL_EXTI_GetPending                               build/stm32f7xx_hal_exti.o
+HAL_EXTI_IRQHandler                               build/stm32f7xx_hal_exti.o
+HAL_EXTI_RegisterCallback                         build/stm32f7xx_hal_exti.o
+HAL_EXTI_SetConfigLine                            build/stm32f7xx_hal_exti.o
+HAL_EnableCompensationCell                        build/stm32f7xx_hal.o
+HAL_EnableFMCMemorySwapping                       build/stm32f7xx_hal.o
+HAL_EnableMemorySwappingBank                      build/stm32f7xx_hal.o
+HAL_FLASHEx_Erase                                 build/stm32f7xx_hal_flash_ex.o
+HAL_FLASHEx_Erase_IT                              build/stm32f7xx_hal_flash_ex.o
+HAL_FLASHEx_OBGetConfig                           build/stm32f7xx_hal_flash_ex.o
+HAL_FLASHEx_OBProgram                             build/stm32f7xx_hal_flash_ex.o
+HAL_FLASH_EndOfOperationCallback                  build/stm32f7xx_hal_flash.o
+HAL_FLASH_GetError                                build/stm32f7xx_hal_flash.o
+HAL_FLASH_IRQHandler                              build/stm32f7xx_hal_flash.o
+HAL_FLASH_Lock                                    build/stm32f7xx_hal_flash.o
+HAL_FLASH_OB_Launch                               build/stm32f7xx_hal_flash.o
+HAL_FLASH_OB_Lock                                 build/stm32f7xx_hal_flash.o
+HAL_FLASH_OB_Unlock                               build/stm32f7xx_hal_flash.o
+HAL_FLASH_OperationErrorCallback                  build/stm32f7xx_hal_flash.o
+HAL_FLASH_Program                                 build/stm32f7xx_hal_flash.o
+HAL_FLASH_Program_IT                              build/stm32f7xx_hal_flash.o
+HAL_FLASH_Unlock                                  build/stm32f7xx_hal_flash.o
+HAL_GPIO_DeInit                                   build/stm32f7xx_hal_gpio.o
+                                                  build/stm32f7xx_hal_msp.o
+HAL_GPIO_EXTI_Callback                            build/stm32f7xx_hal_gpio.o
+HAL_GPIO_EXTI_IRQHandler                          build/stm32f7xx_hal_gpio.o
+HAL_GPIO_Init                                     build/stm32f7xx_hal_gpio.o
+                                                  build/stm32f7xx_hal_rcc.o
+                                                  build/stm32f7xx_hal_msp.o
+                                                  build/main.o
+HAL_GPIO_LockPin                                  build/stm32f7xx_hal_gpio.o
+HAL_GPIO_ReadPin                                  build/stm32f7xx_hal_gpio.o
+                                                  build/fatfs_platform.o
+                                                  build/main.o
+HAL_GPIO_TogglePin                                build/stm32f7xx_hal_gpio.o
+                                                  build/stm32f7xx_it.o
+HAL_GPIO_WritePin                                 build/stm32f7xx_hal_gpio.o
+                                                  build/main.o
+HAL_GetDEVID                                      build/stm32f7xx_hal.o
+HAL_GetHalVersion                                 build/stm32f7xx_hal.o
+HAL_GetREVID                                      build/stm32f7xx_hal.o
+HAL_GetTick                                       build/stm32f7xx_hal.o
+                                                  build/stm32f7xx_hal_sd.o
+                                                  build/stm32f7xx_hal_i2c.o
+                                                  build/stm32f7xx_hal_pwr_ex.o
+                                                  build/stm32f7xx_hal_dma.o
+                                                  build/stm32f7xx_hal_flash.o
+                                                  build/stm32f7xx_hal_rcc_ex.o
+                                                  build/stm32f7xx_hal_rcc.o
+                                                  build/stm32f7xx_hal_adc_ex.o
+                                                  build/stm32f7xx_hal_adc.o
+HAL_GetTickFreq                                   build/stm32f7xx_hal.o
+HAL_GetTickPrio                                   build/stm32f7xx_hal.o
+HAL_GetUIDw0                                      build/stm32f7xx_hal.o
+HAL_GetUIDw1                                      build/stm32f7xx_hal.o
+HAL_GetUIDw2                                      build/stm32f7xx_hal.o
+HAL_I2CEx_ConfigAnalogFilter                      build/stm32f7xx_hal_i2c_ex.o
+HAL_I2CEx_ConfigDigitalFilter                     build/stm32f7xx_hal_i2c_ex.o
+HAL_I2CEx_DisableFastModePlus                     build/stm32f7xx_hal_i2c_ex.o
+HAL_I2CEx_EnableFastModePlus                      build/stm32f7xx_hal_i2c_ex.o
+HAL_I2C_AbortCpltCallback                         build/stm32f7xx_hal_i2c.o
+HAL_I2C_AddrCallback                              build/stm32f7xx_hal_i2c.o
+HAL_I2C_DeInit                                    build/stm32f7xx_hal_i2c.o
+HAL_I2C_DisableListen_IT                          build/stm32f7xx_hal_i2c.o
+HAL_I2C_ER_IRQHandler                             build/stm32f7xx_hal_i2c.o
+HAL_I2C_EV_IRQHandler                             build/stm32f7xx_hal_i2c.o
+HAL_I2C_EnableListen_IT                           build/stm32f7xx_hal_i2c.o
+HAL_I2C_ErrorCallback                             build/stm32f7xx_hal_i2c.o
+HAL_I2C_GetError                                  build/stm32f7xx_hal_i2c.o
+HAL_I2C_GetMode                                   build/stm32f7xx_hal_i2c.o
+HAL_I2C_GetState                                  build/stm32f7xx_hal_i2c.o
+HAL_I2C_Init                                      build/stm32f7xx_hal_i2c.o
+HAL_I2C_IsDeviceReady                             build/stm32f7xx_hal_i2c.o
+HAL_I2C_ListenCpltCallback                        build/stm32f7xx_hal_i2c.o
+HAL_I2C_MasterRxCpltCallback                      build/stm32f7xx_hal_i2c.o
+HAL_I2C_MasterTxCpltCallback                      build/stm32f7xx_hal_i2c.o
+HAL_I2C_Master_Abort_IT                           build/stm32f7xx_hal_i2c.o
+HAL_I2C_Master_Receive                            build/stm32f7xx_hal_i2c.o
+HAL_I2C_Master_Receive_DMA                        build/stm32f7xx_hal_i2c.o
+HAL_I2C_Master_Receive_IT                         build/stm32f7xx_hal_i2c.o
+HAL_I2C_Master_Seq_Receive_DMA                    build/stm32f7xx_hal_i2c.o
+HAL_I2C_Master_Seq_Receive_IT                     build/stm32f7xx_hal_i2c.o
+HAL_I2C_Master_Seq_Transmit_DMA                   build/stm32f7xx_hal_i2c.o
+HAL_I2C_Master_Seq_Transmit_IT                    build/stm32f7xx_hal_i2c.o
+HAL_I2C_Master_Transmit                           build/stm32f7xx_hal_i2c.o
+HAL_I2C_Master_Transmit_DMA                       build/stm32f7xx_hal_i2c.o
+HAL_I2C_Master_Transmit_IT                        build/stm32f7xx_hal_i2c.o
+HAL_I2C_MemRxCpltCallback                         build/stm32f7xx_hal_i2c.o
+HAL_I2C_MemTxCpltCallback                         build/stm32f7xx_hal_i2c.o
+HAL_I2C_Mem_Read                                  build/stm32f7xx_hal_i2c.o
+HAL_I2C_Mem_Read_DMA                              build/stm32f7xx_hal_i2c.o
+HAL_I2C_Mem_Read_IT                               build/stm32f7xx_hal_i2c.o
+HAL_I2C_Mem_Write                                 build/stm32f7xx_hal_i2c.o
+HAL_I2C_Mem_Write_DMA                             build/stm32f7xx_hal_i2c.o
+HAL_I2C_Mem_Write_IT                              build/stm32f7xx_hal_i2c.o
+HAL_I2C_MspDeInit                                 build/stm32f7xx_hal_i2c.o
+HAL_I2C_MspInit                                   build/stm32f7xx_hal_i2c.o
+HAL_I2C_SlaveRxCpltCallback                       build/stm32f7xx_hal_i2c.o
+HAL_I2C_SlaveTxCpltCallback                       build/stm32f7xx_hal_i2c.o
+HAL_I2C_Slave_Receive                             build/stm32f7xx_hal_i2c.o
+HAL_I2C_Slave_Receive_DMA                         build/stm32f7xx_hal_i2c.o
+HAL_I2C_Slave_Receive_IT                          build/stm32f7xx_hal_i2c.o
+HAL_I2C_Slave_Seq_Receive_DMA                     build/stm32f7xx_hal_i2c.o
+HAL_I2C_Slave_Seq_Receive_IT                      build/stm32f7xx_hal_i2c.o
+HAL_I2C_Slave_Seq_Transmit_DMA                    build/stm32f7xx_hal_i2c.o
+HAL_I2C_Slave_Seq_Transmit_IT                     build/stm32f7xx_hal_i2c.o
+HAL_I2C_Slave_Transmit                            build/stm32f7xx_hal_i2c.o
+HAL_I2C_Slave_Transmit_DMA                        build/stm32f7xx_hal_i2c.o
+HAL_I2C_Slave_Transmit_IT                         build/stm32f7xx_hal_i2c.o
+HAL_IncTick                                       build/stm32f7xx_hal.o
+                                                  build/stm32f7xx_it.o
+HAL_Init                                          build/stm32f7xx_hal.o
+                                                  build/main.o
+HAL_InitTick                                      build/stm32f7xx_hal.o
+                                                  build/stm32f7xx_hal_rcc.o
+HAL_MPU_ConfigRegion                              build/stm32f7xx_hal_cortex.o
+HAL_MPU_Disable                                   build/stm32f7xx_hal_cortex.o
+HAL_MPU_DisableRegion                             build/stm32f7xx_hal_cortex.o
+HAL_MPU_Enable                                    build/stm32f7xx_hal_cortex.o
+HAL_MPU_EnableRegion                              build/stm32f7xx_hal_cortex.o
+HAL_MspDeInit                                     build/stm32f7xx_hal.o
+HAL_MspInit                                       build/stm32f7xx_hal_msp.o
+HAL_NVIC_ClearPendingIRQ                          build/stm32f7xx_hal_cortex.o
+HAL_NVIC_DisableIRQ                               build/stm32f7xx_hal_cortex.o
+                                                  build/stm32f7xx_hal_msp.o
+HAL_NVIC_EnableIRQ                                build/stm32f7xx_hal_cortex.o
+                                                  build/stm32f7xx_hal_msp.o
+HAL_NVIC_GetActive                                build/stm32f7xx_hal_cortex.o
+HAL_NVIC_GetPendingIRQ                            build/stm32f7xx_hal_cortex.o
+HAL_NVIC_GetPriority                              build/stm32f7xx_hal_cortex.o
+HAL_NVIC_GetPriorityGrouping                      build/stm32f7xx_hal_cortex.o
+HAL_NVIC_SetPendingIRQ                            build/stm32f7xx_hal_cortex.o
+HAL_NVIC_SetPriority                              build/stm32f7xx_hal_cortex.o
+                                                  build/stm32f7xx_hal.o
+                                                  build/stm32f7xx_hal_msp.o
+HAL_NVIC_SetPriorityGrouping                      build/stm32f7xx_hal_cortex.o
+                                                  build/stm32f7xx_hal.o
+HAL_NVIC_SystemReset                              build/stm32f7xx_hal_cortex.o
+HAL_PWREx_ControlVoltageScaling                   build/stm32f7xx_hal_pwr_ex.o
+HAL_PWREx_DisableBkUpReg                          build/stm32f7xx_hal_pwr_ex.o
+HAL_PWREx_DisableFlashPowerDown                   build/stm32f7xx_hal_pwr_ex.o
+HAL_PWREx_DisableLowRegulatorLowVoltage           build/stm32f7xx_hal_pwr_ex.o
+HAL_PWREx_DisableMainRegulatorLowVoltage          build/stm32f7xx_hal_pwr_ex.o
+HAL_PWREx_DisableOverDrive                        build/stm32f7xx_hal_pwr_ex.o
+HAL_PWREx_EnableBkUpReg                           build/stm32f7xx_hal_pwr_ex.o
+HAL_PWREx_EnableFlashPowerDown                    build/stm32f7xx_hal_pwr_ex.o
+HAL_PWREx_EnableLowRegulatorLowVoltage            build/stm32f7xx_hal_pwr_ex.o
+HAL_PWREx_EnableMainRegulatorLowVoltage           build/stm32f7xx_hal_pwr_ex.o
+HAL_PWREx_EnableOverDrive                         build/stm32f7xx_hal_pwr_ex.o
+                                                  build/main.o
+HAL_PWREx_EnterUnderDriveSTOPMode                 build/stm32f7xx_hal_pwr_ex.o
+HAL_PWREx_GetVoltageRange                         build/stm32f7xx_hal_pwr_ex.o
+HAL_PWR_ConfigPVD                                 build/stm32f7xx_hal_pwr.o
+HAL_PWR_DeInit                                    build/stm32f7xx_hal_pwr.o
+HAL_PWR_DisableBkUpAccess                         build/stm32f7xx_hal_pwr.o
+HAL_PWR_DisablePVD                                build/stm32f7xx_hal_pwr.o
+HAL_PWR_DisableSEVOnPend                          build/stm32f7xx_hal_pwr.o
+HAL_PWR_DisableSleepOnExit                        build/stm32f7xx_hal_pwr.o
+HAL_PWR_DisableWakeUpPin                          build/stm32f7xx_hal_pwr.o
+HAL_PWR_EnableBkUpAccess                          build/stm32f7xx_hal_pwr.o
+HAL_PWR_EnablePVD                                 build/stm32f7xx_hal_pwr.o
+HAL_PWR_EnableSEVOnPend                           build/stm32f7xx_hal_pwr.o
+HAL_PWR_EnableSleepOnExit                         build/stm32f7xx_hal_pwr.o
+HAL_PWR_EnableWakeUpPin                           build/stm32f7xx_hal_pwr.o
+HAL_PWR_EnterSLEEPMode                            build/stm32f7xx_hal_pwr.o
+HAL_PWR_EnterSTANDBYMode                          build/stm32f7xx_hal_pwr.o
+HAL_PWR_EnterSTOPMode                             build/stm32f7xx_hal_pwr.o
+HAL_PWR_PVDCallback                               build/stm32f7xx_hal_pwr.o
+HAL_PWR_PVD_IRQHandler                            build/stm32f7xx_hal_pwr.o
+HAL_RCCEx_DisablePLLI2S                           build/stm32f7xx_hal_rcc_ex.o
+HAL_RCCEx_DisablePLLSAI                           build/stm32f7xx_hal_rcc_ex.o
+HAL_RCCEx_EnablePLLI2S                            build/stm32f7xx_hal_rcc_ex.o
+HAL_RCCEx_EnablePLLSAI                            build/stm32f7xx_hal_rcc_ex.o
+HAL_RCCEx_GetPeriphCLKConfig                      build/stm32f7xx_hal_rcc_ex.o
+HAL_RCCEx_GetPeriphCLKFreq                        build/stm32f7xx_hal_rcc_ex.o
+HAL_RCCEx_PeriphCLKConfig                         build/stm32f7xx_hal_rcc_ex.o
+                                                  build/stm32f7xx_hal_msp.o
+                                                  build/main.o
+HAL_RCC_CSSCallback                               build/stm32f7xx_hal_rcc.o
+HAL_RCC_ClockConfig                               build/stm32f7xx_hal_rcc.o
+                                                  build/main.o
+HAL_RCC_DeInit                                    build/stm32f7xx_hal_rcc.o
+HAL_RCC_DisableCSS                                build/stm32f7xx_hal_rcc.o
+HAL_RCC_EnableCSS                                 build/stm32f7xx_hal_rcc.o
+HAL_RCC_GetClockConfig                            build/stm32f7xx_hal_rcc.o
+HAL_RCC_GetHCLKFreq                               build/stm32f7xx_hal_rcc.o
+HAL_RCC_GetOscConfig                              build/stm32f7xx_hal_rcc.o
+HAL_RCC_GetPCLK1Freq                              build/stm32f7xx_hal_rcc.o
+HAL_RCC_GetPCLK2Freq                              build/stm32f7xx_hal_rcc.o
+HAL_RCC_GetSysClockFreq                           build/stm32f7xx_hal_rcc.o
+HAL_RCC_MCOConfig                                 build/stm32f7xx_hal_rcc.o
+HAL_RCC_NMI_IRQHandler                            build/stm32f7xx_hal_rcc.o
+HAL_RCC_OscConfig                                 build/stm32f7xx_hal_rcc.o
+                                                  build/main.o
+HAL_ResumeTick                                    build/stm32f7xx_hal.o
+HAL_SD_Abort                                      build/stm32f7xx_hal_sd.o
+HAL_SD_AbortCallback                              build/bsp_driver_sd.o
+HAL_SD_Abort_IT                                   build/stm32f7xx_hal_sd.o
+HAL_SD_ConfigWideBusOperation                     build/stm32f7xx_hal_sd.o
+                                                  build/bsp_driver_sd.o
+HAL_SD_DeInit                                     build/stm32f7xx_hal_sd.o
+HAL_SD_Erase                                      build/stm32f7xx_hal_sd.o
+                                                  build/bsp_driver_sd.o
+HAL_SD_ErrorCallback                              build/stm32f7xx_hal_sd.o
+HAL_SD_GetCardCID                                 build/stm32f7xx_hal_sd.o
+HAL_SD_GetCardCSD                                 build/stm32f7xx_hal_sd.o
+HAL_SD_GetCardInfo                                build/stm32f7xx_hal_sd.o
+                                                  build/bsp_driver_sd.o
+HAL_SD_GetCardState                               build/stm32f7xx_hal_sd.o
+                                                  build/bsp_driver_sd.o
+HAL_SD_GetCardStatus                              build/stm32f7xx_hal_sd.o
+HAL_SD_GetError                                   build/stm32f7xx_hal_sd.o
+HAL_SD_GetState                                   build/stm32f7xx_hal_sd.o
+HAL_SD_IRQHandler                                 build/stm32f7xx_hal_sd.o
+HAL_SD_Init                                       build/stm32f7xx_hal_sd.o
+                                                  build/bsp_driver_sd.o
+HAL_SD_InitCard                                   build/stm32f7xx_hal_sd.o
+HAL_SD_MspDeInit                                  build/stm32f7xx_hal_msp.o
+HAL_SD_MspInit                                    build/stm32f7xx_hal_msp.o
+HAL_SD_ReadBlocks                                 build/stm32f7xx_hal_sd.o
+                                                  build/bsp_driver_sd.o
+HAL_SD_ReadBlocks_DMA                             build/stm32f7xx_hal_sd.o
+                                                  build/bsp_driver_sd.o
+HAL_SD_ReadBlocks_IT                              build/stm32f7xx_hal_sd.o
+HAL_SD_RxCpltCallback                             build/bsp_driver_sd.o
+HAL_SD_TxCpltCallback                             build/bsp_driver_sd.o
+HAL_SD_WriteBlocks                                build/stm32f7xx_hal_sd.o
+                                                  build/bsp_driver_sd.o
+HAL_SD_WriteBlocks_DMA                            build/stm32f7xx_hal_sd.o
+                                                  build/bsp_driver_sd.o
+HAL_SD_WriteBlocks_IT                             build/stm32f7xx_hal_sd.o
+HAL_SYSTICK_CLKSourceConfig                       build/stm32f7xx_hal_cortex.o
+HAL_SYSTICK_Callback                              build/stm32f7xx_hal_cortex.o
+HAL_SYSTICK_Config                                build/stm32f7xx_hal_cortex.o
+                                                  build/stm32f7xx_hal.o
+HAL_SYSTICK_IRQHandler                            build/stm32f7xx_hal_cortex.o
+HAL_SetTickFreq                                   build/stm32f7xx_hal.o
+HAL_SuspendTick                                   build/stm32f7xx_hal.o
+HAL_TIMEx_Break2Callback                          build/stm32f7xx_hal_tim_ex.o
+                                                  build/stm32f7xx_hal_tim.o
+HAL_TIMEx_BreakCallback                           build/stm32f7xx_hal_tim_ex.o
+                                                  build/stm32f7xx_hal_tim.o
+HAL_TIMEx_CommutCallback                          build/stm32f7xx_hal_tim_ex.o
+                                                  build/stm32f7xx_hal_tim.o
+HAL_TIMEx_CommutHalfCpltCallback                  build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_ConfigBreakDeadTime                     build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_ConfigBreakInput                        build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_ConfigCommutEvent                       build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_ConfigCommutEvent_DMA                   build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_ConfigCommutEvent_IT                    build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_GetChannelNState                        build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_GroupChannel5                           build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_DeInit                       build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_GetState                     build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Init                         build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_MspDeInit                    build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_MspInit                      build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Start                        build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Start_DMA                    build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Start_IT                     build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Stop                         build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Stop_DMA                     build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_HallSensor_Stop_IT                      build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_MasterConfigSynchronization             build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_OCN_Start                               build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_OCN_Start_DMA                           build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_OCN_Start_IT                            build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_OCN_Stop                                build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_OCN_Stop_DMA                            build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_OCN_Stop_IT                             build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_OnePulseN_Start                         build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_OnePulseN_Start_IT                      build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_OnePulseN_Stop                          build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_OnePulseN_Stop_IT                       build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Start                              build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Start_DMA                          build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Start_IT                           build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Stop                               build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Stop_DMA                           build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_PWMN_Stop_IT                            build/stm32f7xx_hal_tim_ex.o
+HAL_TIMEx_RemapConfig                             build/stm32f7xx_hal_tim_ex.o
+HAL_TIM_Base_DeInit                               build/stm32f7xx_hal_tim.o
+HAL_TIM_Base_GetState                             build/stm32f7xx_hal_tim.o
+HAL_TIM_Base_Init                                 build/stm32f7xx_hal_tim.o
+                                                  build/main.o
+HAL_TIM_Base_MspDeInit                            build/stm32f7xx_hal_msp.o
+HAL_TIM_Base_MspInit                              build/stm32f7xx_hal_msp.o
+HAL_TIM_Base_Start                                build/stm32f7xx_hal_tim.o
+HAL_TIM_Base_Start_DMA                            build/stm32f7xx_hal_tim.o
+HAL_TIM_Base_Start_IT                             build/stm32f7xx_hal_tim.o
+                                                  build/main.o
+HAL_TIM_Base_Stop                                 build/stm32f7xx_hal_tim.o
+HAL_TIM_Base_Stop_DMA                             build/stm32f7xx_hal_tim.o
+HAL_TIM_Base_Stop_IT                              build/stm32f7xx_hal_tim.o
+                                                  build/main.o
+HAL_TIM_ConfigClockSource                         build/stm32f7xx_hal_tim.o
+HAL_TIM_ConfigOCrefClear                          build/stm32f7xx_hal_tim.o
+HAL_TIM_ConfigTI1Input                            build/stm32f7xx_hal_tim.o
+HAL_TIM_DMABurstState                             build/stm32f7xx_hal_tim.o
+HAL_TIM_DMABurst_MultiReadStart                   build/stm32f7xx_hal_tim.o
+HAL_TIM_DMABurst_MultiWriteStart                  build/stm32f7xx_hal_tim.o
+HAL_TIM_DMABurst_ReadStart                        build/stm32f7xx_hal_tim.o
+HAL_TIM_DMABurst_ReadStop                         build/stm32f7xx_hal_tim.o
+HAL_TIM_DMABurst_WriteStart                       build/stm32f7xx_hal_tim.o
+HAL_TIM_DMABurst_WriteStop                        build/stm32f7xx_hal_tim.o
+HAL_TIM_Encoder_DeInit                            build/stm32f7xx_hal_tim.o
+HAL_TIM_Encoder_GetState                          build/stm32f7xx_hal_tim.o
+HAL_TIM_Encoder_Init                              build/stm32f7xx_hal_tim.o
+HAL_TIM_Encoder_MspDeInit                         build/stm32f7xx_hal_tim.o
+HAL_TIM_Encoder_MspInit                           build/stm32f7xx_hal_tim.o
+HAL_TIM_Encoder_Start                             build/stm32f7xx_hal_tim.o
+HAL_TIM_Encoder_Start_DMA                         build/stm32f7xx_hal_tim.o
+HAL_TIM_Encoder_Start_IT                          build/stm32f7xx_hal_tim.o
+HAL_TIM_Encoder_Stop                              build/stm32f7xx_hal_tim.o
+HAL_TIM_Encoder_Stop_DMA                          build/stm32f7xx_hal_tim.o
+HAL_TIM_Encoder_Stop_IT                           build/stm32f7xx_hal_tim.o
+HAL_TIM_ErrorCallback                             build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+HAL_TIM_GenerateEvent                             build/stm32f7xx_hal_tim.o
+HAL_TIM_GetActiveChannel                          build/stm32f7xx_hal_tim.o
+HAL_TIM_GetChannelState                           build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_CaptureCallback                        build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_CaptureHalfCpltCallback                build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_ConfigChannel                          build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_DeInit                                 build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_GetState                               build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_Init                                   build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_MspDeInit                              build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_MspInit                                build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_Start                                  build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_Start_DMA                              build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_Start_IT                               build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_Stop                                   build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_Stop_DMA                               build/stm32f7xx_hal_tim.o
+HAL_TIM_IC_Stop_IT                                build/stm32f7xx_hal_tim.o
+HAL_TIM_IRQHandler                                build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_it.o
+HAL_TIM_OC_ConfigChannel                          build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_DeInit                                 build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_DelayElapsedCallback                   build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_GetState                               build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_Init                                   build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_MspDeInit                              build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_MspInit                                build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_Start                                  build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_Start_DMA                              build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_Start_IT                               build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_Stop                                   build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_Stop_DMA                               build/stm32f7xx_hal_tim.o
+HAL_TIM_OC_Stop_IT                                build/stm32f7xx_hal_tim.o
+HAL_TIM_OnePulse_ConfigChannel                    build/stm32f7xx_hal_tim.o
+HAL_TIM_OnePulse_DeInit                           build/stm32f7xx_hal_tim.o
+HAL_TIM_OnePulse_GetState                         build/stm32f7xx_hal_tim.o
+HAL_TIM_OnePulse_Init                             build/stm32f7xx_hal_tim.o
+HAL_TIM_OnePulse_MspDeInit                        build/stm32f7xx_hal_tim.o
+HAL_TIM_OnePulse_MspInit                          build/stm32f7xx_hal_tim.o
+HAL_TIM_OnePulse_Start                            build/stm32f7xx_hal_tim.o
+HAL_TIM_OnePulse_Start_IT                         build/stm32f7xx_hal_tim.o
+HAL_TIM_OnePulse_Stop                             build/stm32f7xx_hal_tim.o
+HAL_TIM_OnePulse_Stop_IT                          build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_ConfigChannel                         build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_DeInit                                build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_GetState                              build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_Init                                  build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_MspDeInit                             build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_MspInit                               build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_PulseFinishedCallback                 build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+HAL_TIM_PWM_PulseFinishedHalfCpltCallback         build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_Start                                 build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_Start_DMA                             build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_Start_IT                              build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_Stop                                  build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_Stop_DMA                              build/stm32f7xx_hal_tim.o
+HAL_TIM_PWM_Stop_IT                               build/stm32f7xx_hal_tim.o
+HAL_TIM_PeriodElapsedCallback                     build/stm32f7xx_hal_tim.o
+HAL_TIM_PeriodElapsedHalfCpltCallback             build/stm32f7xx_hal_tim.o
+HAL_TIM_ReadCapturedValue                         build/stm32f7xx_hal_tim.o
+HAL_TIM_SlaveConfigSynchro                        build/stm32f7xx_hal_tim.o
+HAL_TIM_SlaveConfigSynchro_IT                     build/stm32f7xx_hal_tim.o
+HAL_TIM_TriggerCallback                           build/stm32f7xx_hal_tim.o
+HAL_TIM_TriggerHalfCpltCallback                   build/stm32f7xx_hal_tim.o
+HardFault_Handler                                 build/stm32f7xx_it.o
+I2C1_ER_IRQHandler                                build/startup_stm32f767xx.o
+I2C1_EV_IRQHandler                                build/startup_stm32f767xx.o
+I2C2_ER_IRQHandler                                build/startup_stm32f767xx.o
+I2C2_EV_IRQHandler                                build/startup_stm32f767xx.o
+I2C3_ER_IRQHandler                                build/startup_stm32f767xx.o
+I2C3_EV_IRQHandler                                build/startup_stm32f767xx.o
+I2C4_ER_IRQHandler                                build/startup_stm32f767xx.o
+I2C4_EV_IRQHandler                                build/startup_stm32f767xx.o
+JPEG_IRQHandler                                   build/startup_stm32f767xx.o
+LD1_curr_setup                                    build/main.o
+LD1_def_setup                                     build/main.o
+LD1_param                                         build/main.o
+LD2_curr_setup                                    build/main.o
+LD2_def_setup                                     build/main.o
+LD2_param                                         build/main.o
+LL_DMA_DeInit                                     build/stm32f7xx_ll_dma.o
+LL_DMA_Init                                       build/stm32f7xx_ll_dma.o
+LL_DMA_StructInit                                 build/stm32f7xx_ll_dma.o
+LL_EXTI_DeInit                                    build/stm32f7xx_ll_exti.o
+LL_EXTI_Init                                      build/stm32f7xx_ll_exti.o
+LL_EXTI_StructInit                                build/stm32f7xx_ll_exti.o
+LL_GPIO_DeInit                                    build/stm32f7xx_ll_gpio.o
+LL_GPIO_Init                                      build/stm32f7xx_ll_gpio.o
+                                                  build/main.o
+LL_GPIO_StructInit                                build/stm32f7xx_ll_gpio.o
+LL_I2S_ConfigPrescaler                            build/stm32f7xx_ll_spi.o
+LL_I2S_DeInit                                     build/stm32f7xx_ll_spi.o
+LL_I2S_Init                                       build/stm32f7xx_ll_spi.o
+LL_I2S_StructInit                                 build/stm32f7xx_ll_spi.o
+LL_Init1msTick                                    build/stm32f7xx_ll_utils.o
+LL_PLL_ConfigSystemClock_HSE                      build/stm32f7xx_ll_utils.o
+LL_PLL_ConfigSystemClock_HSI                      build/stm32f7xx_ll_utils.o
+LL_RCC_DeInit                                     build/stm32f7xx_ll_rcc.o
+LL_RCC_GetCECClockFreq                            build/stm32f7xx_ll_rcc.o
+LL_RCC_GetDFSDMAudioClockFreq                     build/stm32f7xx_ll_rcc.o
+LL_RCC_GetDFSDMClockFreq                          build/stm32f7xx_ll_rcc.o
+LL_RCC_GetI2CClockFreq                            build/stm32f7xx_ll_rcc.o
+LL_RCC_GetI2SClockFreq                            build/stm32f7xx_ll_rcc.o
+                                                  build/stm32f7xx_ll_spi.o
+LL_RCC_GetLPTIMClockFreq                          build/stm32f7xx_ll_rcc.o
+LL_RCC_GetLTDCClockFreq                           build/stm32f7xx_ll_rcc.o
+LL_RCC_GetRNGClockFreq                            build/stm32f7xx_ll_rcc.o
+LL_RCC_GetSAIClockFreq                            build/stm32f7xx_ll_rcc.o
+LL_RCC_GetSDMMCClockFreq                          build/stm32f7xx_ll_rcc.o
+LL_RCC_GetSPDIFRXClockFreq                        build/stm32f7xx_ll_rcc.o
+LL_RCC_GetSystemClocksFreq                        build/stm32f7xx_ll_rcc.o
+LL_RCC_GetUARTClockFreq                           build/stm32f7xx_ll_rcc.o
+                                                  build/stm32f7xx_ll_usart.o
+LL_RCC_GetUSARTClockFreq                          build/stm32f7xx_ll_rcc.o
+                                                  build/stm32f7xx_ll_usart.o
+LL_RCC_GetUSBClockFreq                            build/stm32f7xx_ll_rcc.o
+LL_SPI_DeInit                                     build/stm32f7xx_ll_spi.o
+LL_SPI_Init                                       build/stm32f7xx_ll_spi.o
+                                                  build/main.o
+LL_SPI_StructInit                                 build/stm32f7xx_ll_spi.o
+LL_SetFlashLatency                                build/stm32f7xx_ll_utils.o
+LL_SetSystemCoreClock                             build/stm32f7xx_ll_utils.o
+LL_TIM_BDTR_Init                                  build/stm32f7xx_ll_tim.o
+LL_TIM_BDTR_StructInit                            build/stm32f7xx_ll_tim.o
+LL_TIM_DeInit                                     build/stm32f7xx_ll_tim.o
+LL_TIM_ENCODER_Init                               build/stm32f7xx_ll_tim.o
+LL_TIM_ENCODER_StructInit                         build/stm32f7xx_ll_tim.o
+LL_TIM_HALLSENSOR_Init                            build/stm32f7xx_ll_tim.o
+LL_TIM_HALLSENSOR_StructInit                      build/stm32f7xx_ll_tim.o
+LL_TIM_IC_Init                                    build/stm32f7xx_ll_tim.o
+LL_TIM_IC_StructInit                              build/stm32f7xx_ll_tim.o
+LL_TIM_Init                                       build/stm32f7xx_ll_tim.o
+                                                  build/main.o
+LL_TIM_OC_Init                                    build/stm32f7xx_ll_tim.o
+LL_TIM_OC_StructInit                              build/stm32f7xx_ll_tim.o
+LL_TIM_StructInit                                 build/stm32f7xx_ll_tim.o
+LL_USART_ClockInit                                build/stm32f7xx_ll_usart.o
+LL_USART_ClockStructInit                          build/stm32f7xx_ll_usart.o
+LL_USART_DeInit                                   build/stm32f7xx_ll_usart.o
+LL_USART_Init                                     build/stm32f7xx_ll_usart.o
+                                                  build/main.o
+LL_USART_StructInit                               build/stm32f7xx_ll_usart.o
+LL_mDelay                                         build/stm32f7xx_ll_utils.o
+LPTIM1_IRQHandler                                 build/startup_stm32f767xx.o
+LTDC_ER_IRQHandler                                build/startup_stm32f767xx.o
+LTDC_IRQHandler                                   build/startup_stm32f767xx.o
+Long_Data                                         build/main.o
+MDIOS_IRQHandler                                  build/startup_stm32f767xx.o
+MX_FATFS_Init                                     build/fatfs.o
+                                                  build/main.o
+MemManage_Handler                                 build/stm32f7xx_it.o
+Mount_SD                                          build/main.o
+NMI_Handler                                       build/stm32f7xx_it.o
+OTG_FS_IRQHandler                                 build/startup_stm32f767xx.o
+OTG_FS_WKUP_IRQHandler                            build/startup_stm32f767xx.o
+OTG_HS_EP1_IN_IRQHandler                          build/startup_stm32f767xx.o
+OTG_HS_EP1_OUT_IRQHandler                         build/startup_stm32f767xx.o
+OTG_HS_IRQHandler                                 build/startup_stm32f767xx.o
+OTG_HS_WKUP_IRQHandler                            build/startup_stm32f767xx.o
+PVD_IRQHandler                                    build/startup_stm32f767xx.o
+PendSV_Handler                                    build/stm32f7xx_it.o
+QUADSPI_IRQHandler                                build/startup_stm32f767xx.o
+RCC_GetHCLKClockFreq                              build/stm32f7xx_ll_rcc.o
+RCC_GetPCLK1ClockFreq                             build/stm32f7xx_ll_rcc.o
+RCC_GetPCLK2ClockFreq                             build/stm32f7xx_ll_rcc.o
+RCC_GetSystemClockFreq                            build/stm32f7xx_ll_rcc.o
+RCC_IRQHandler                                    build/startup_stm32f767xx.o
+RCC_PLLI2S_GetFreqDomain_I2S                      build/stm32f7xx_ll_rcc.o
+RCC_PLLI2S_GetFreqDomain_SAI                      build/stm32f7xx_ll_rcc.o
+RCC_PLLI2S_GetFreqDomain_SPDIFRX                  build/stm32f7xx_ll_rcc.o
+RCC_PLLSAI_GetFreqDomain_48M                      build/stm32f7xx_ll_rcc.o
+RCC_PLLSAI_GetFreqDomain_LTDC                     build/stm32f7xx_ll_rcc.o
+RCC_PLLSAI_GetFreqDomain_SAI                      build/stm32f7xx_ll_rcc.o
+RCC_PLL_GetFreqDomain_48M                         build/stm32f7xx_ll_rcc.o
+RCC_PLL_GetFreqDomain_SYS                         build/stm32f7xx_ll_rcc.o
+RNG_IRQHandler                                    build/startup_stm32f767xx.o
+RTC_Alarm_IRQHandler                              build/startup_stm32f767xx.o
+RTC_WKUP_IRQHandler                               build/startup_stm32f767xx.o
+Remove_File                                       build/main.o
+Reset_Handler                                     build/startup_stm32f767xx.o
+SAI1_IRQHandler                                   build/startup_stm32f767xx.o
+SAI2_IRQHandler                                   build/startup_stm32f767xx.o
+SDFatFS                                           build/fatfs.o
+SDFile                                            build/fatfs.o
+SDMMC1_IRQHandler                                 build/startup_stm32f767xx.o
+SDMMC2_IRQHandler                                 build/startup_stm32f767xx.o
+SDMMC_CmdAppCommand                               build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdAppOperCommand                           build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdBlockLength                              build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdBusWidth                                 build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdErase                                    build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdEraseEndAdd                              build/stm32f7xx_ll_sdmmc.o
+SDMMC_CmdEraseStartAdd                            build/stm32f7xx_ll_sdmmc.o
+SDMMC_CmdGoIdleState                              build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdOpCondition                              build/stm32f7xx_ll_sdmmc.o
+SDMMC_CmdOperCond                                 build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdReadMultiBlock                           build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdReadSingleBlock                          build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdSDEraseEndAdd                            build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdSDEraseStartAdd                          build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdSelDesel                                 build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdSendCID                                  build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdSendCSD                                  build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdSendEXTCSD                               build/stm32f7xx_ll_sdmmc.o
+SDMMC_CmdSendSCR                                  build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdSendStatus                               build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdSetRelAdd                                build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdSetRelAddMmc                             build/stm32f7xx_ll_sdmmc.o
+SDMMC_CmdStatusRegister                           build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdStopTransfer                             build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdSwitch                                   build/stm32f7xx_ll_sdmmc.o
+SDMMC_CmdWriteMultiBlock                          build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_CmdWriteSingleBlock                         build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_ConfigData                                  build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_GetCmdResp1                                 build/stm32f7xx_ll_sdmmc.o
+SDMMC_GetCmdResp2                                 build/stm32f7xx_ll_sdmmc.o
+SDMMC_GetCmdResp3                                 build/stm32f7xx_ll_sdmmc.o
+SDMMC_GetCmdResp6                                 build/stm32f7xx_ll_sdmmc.o
+SDMMC_GetCmdResp7                                 build/stm32f7xx_ll_sdmmc.o
+SDMMC_GetCommandResponse                          build/stm32f7xx_ll_sdmmc.o
+SDMMC_GetDataCounter                              build/stm32f7xx_ll_sdmmc.o
+SDMMC_GetFIFOCount                                build/stm32f7xx_ll_sdmmc.o
+SDMMC_GetPowerState                               build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_GetResponse                                 build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_Init                                        build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_PowerState_OFF                              build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_PowerState_ON                               build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_ReadFIFO                                    build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDMMC_SendCommand                                 build/stm32f7xx_ll_sdmmc.o
+SDMMC_SetSDMMCReadWaitMode                        build/stm32f7xx_ll_sdmmc.o
+SDMMC_WriteFIFO                                   build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_hal_sd.o
+SDPath                                            build/fatfs.o
+SD_Driver                                         build/sd_diskio.o
+                                                  build/fatfs.o
+SD_READ                                           build/main.o
+SD_REMOVE                                         build/main.o
+SD_SAVE                                           build/main.o
+SD_SEEK                                           build/main.o
+SD_SLIDE                                          build/main.o
+SD_initialize                                     build/sd_diskio.o
+SD_ioctl                                          build/sd_diskio.o
+SD_read                                           build/sd_diskio.o
+SD_status                                         build/sd_diskio.o
+SD_write                                          build/sd_diskio.o
+SPDIF_RX_IRQHandler                               build/startup_stm32f767xx.o
+SPI1_IRQHandler                                   build/startup_stm32f767xx.o
+SPI2_IRQHandler                                   build/startup_stm32f767xx.o
+SPI3_IRQHandler                                   build/startup_stm32f767xx.o
+SPI4_IRQHandler                                   build/startup_stm32f767xx.o
+SPI5_IRQHandler                                   build/startup_stm32f767xx.o
+SPI6_IRQHandler                                   build/startup_stm32f767xx.o
+SVC_Handler                                       build/stm32f7xx_it.o
+Seek_Read_File                                    build/main.o
+State_Data                                        build/main.o
+                                                  build/stm32f7xx_it.o
+SysTick_Handler                                   build/stm32f7xx_it.o
+SystemClock_Config                                build/main.o
+SystemCoreClock                                   build/system_stm32f7xx.o
+                                                  build/stm32f7xx_ll_sdmmc.o
+                                                  build/stm32f7xx_ll_utils.o
+                                                  build/stm32f7xx_hal.o
+                                                  build/stm32f7xx_hal_dma.o
+                                                  build/stm32f7xx_hal_rcc.o
+                                                  build/stm32f7xx_hal_adc_ex.o
+                                                  build/stm32f7xx_hal_adc.o
+SystemCoreClockUpdate                             build/system_stm32f7xx.o
+SystemInit                                        build/system_stm32f7xx.o
+                                                  build/startup_stm32f767xx.o
+TAMP_STAMP_IRQHandler                             build/startup_stm32f767xx.o
+TIM10_coflag                                      build/main.o
+                                                  build/stm32f7xx_it.o
+TIM10_period                                      build/main.o
+TIM1_BRK_TIM9_IRQHandler                          build/startup_stm32f767xx.o
+TIM1_CC_IRQHandler                                build/startup_stm32f767xx.o
+TIM1_TRG_COM_TIM11_IRQHandler                     build/startup_stm32f767xx.o
+TIM1_UP_TIM10_IRQHandler                          build/stm32f7xx_it.o
+TIM2_IRQHandler                                   build/stm32f7xx_it.o
+TIM3_IRQHandler                                   build/startup_stm32f767xx.o
+TIM4_IRQHandler                                   build/startup_stm32f767xx.o
+TIM5_IRQHandler                                   build/stm32f7xx_it.o
+TIM6_DAC_IRQHandler                               build/stm32f7xx_it.o
+TIM7_IRQHandler                                   build/stm32f7xx_it.o
+TIM8_BRK_TIM12_IRQHandler                         build/startup_stm32f767xx.o
+TIM8_CC_IRQHandler                                build/startup_stm32f767xx.o
+TIM8_TRG_COM_TIM14_IRQHandler                     build/startup_stm32f767xx.o
+TIM8_UP_TIM13_IRQHandler                          build/startup_stm32f767xx.o
+TIMEx_DMACommutationCplt                          build/stm32f7xx_hal_tim_ex.o
+                                                  build/stm32f7xx_hal_tim.o
+TIMEx_DMACommutationHalfCplt                      build/stm32f7xx_hal_tim_ex.o
+                                                  build/stm32f7xx_hal_tim.o
+TIM_Base_SetConfig                                build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+TIM_CCxChannelCmd                                 build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+TIM_DMACaptureCplt                                build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+TIM_DMACaptureHalfCplt                            build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+TIM_DMADelayPulseHalfCplt                         build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+TIM_DMAError                                      build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+TIM_ETR_SetConfig                                 build/stm32f7xx_hal_tim.o
+TIM_OC2_SetConfig                                 build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+TIM_TI1_SetConfig                                 build/stm32f7xx_hal_tim.o
+                                                  build/stm32f7xx_hal_tim_ex.o
+TO10                                              build/main.o
+                                                  build/stm32f7xx_it.o
+TO10_counter                                      build/main.o
+                                                  build/stm32f7xx_it.o
+TO6                                               build/main.o
+                                                  build/stm32f7xx_it.o
+TO6_before                                        build/main.o
+TO6_stop                                          build/main.o
+TO6_uart                                          build/main.o
+                                                  build/stm32f7xx_it.o
+TO7                                               build/main.o
+                                                  build/stm32f7xx_it.o
+TO7_PID                                           build/main.o
+TO7_before                                        build/main.o
+UART4_IRQHandler                                  build/startup_stm32f767xx.o
+UART5_IRQHandler                                  build/startup_stm32f767xx.o
+UART7_IRQHandler                                  build/startup_stm32f767xx.o
+UART8_IRQHandler                                  build/startup_stm32f767xx.o
+UART_DATA                                         build/main.o
+UART_RxCpltCallback                               build/stm32f7xx_it.o
+UART_header                                       build/main.o
+                                                  build/stm32f7xx_it.o
+UART_rec_incr                                     build/main.o
+                                                  build/stm32f7xx_it.o
+UART_transmission_request                         build/main.o
+                                                  build/stm32f7xx_it.o
+USART1_IRQHandler                                 build/stm32f7xx_it.o
+USART2_IRQHandler                                 build/startup_stm32f767xx.o
+USART3_IRQHandler                                 build/startup_stm32f767xx.o
+USART6_IRQHandler                                 build/startup_stm32f767xx.o
+USART_TX                                          build/main.o
+USART_TX_DMA                                      build/main.o
+Unmount_SD                                        build/main.o
+Update_File_byte                                  build/main.o
+UsageFault_Handler                                build/stm32f7xx_it.o
+WWDG_IRQHandler                                   build/startup_stm32f767xx.o
+Write_File_byte                                   build/main.o
+_ITM_deregisterTMCloneTable                       /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+_ITM_registerTMCloneTable                         /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+_Min_Stack_Size                                   build/sysmem.o
+__TMC_END__                                       /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtend.o
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+__aeabi_idiv0                                     /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o)
+__aeabi_ldiv0                                     /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o)
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o)
+__aeabi_uldivmod                                  /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o)
+                                                  build/stm32f7xx_hal_rcc.o
+__atexit_dummy                                    /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o)
+__bss_end__                                       /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+__bss_start__                                     /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+__call_exitprocs                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__call_atexit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-exit.o)
+__deregister_frame_info                           /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+__dso_handle                                      /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+__env                                             build/syscalls.o
+__errno                                           /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-errno.o)
+                                                  build/syscalls.o
+                                                  build/sysmem.o
+__fini_array_end                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-fini.o)
+__fini_array_start                                /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-fini.o)
+__init_array_end                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o)
+__init_array_start                                /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o)
+__io_getchar                                      build/syscalls.o
+__io_putchar                                      build/syscalls.o
+__libc_fini_array                                 /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-fini.o)
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+__libc_init_array                                 /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o)
+                                                  build/startup_stm32f767xx.o
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+__on_exit_args                                    /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o)
+__preinit_array_end                               /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o)
+__preinit_array_start                             /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o)
+__register_exitproc                               /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-atexit.o)
+__register_frame_info                             /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+__sf_fake_stderr                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o)
+__sf_fake_stdin                                   /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o)
+__sf_fake_stdout                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o)
+__stack                                           /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+__udivmoddi4                                      /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o)
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o)
+_close                                            build/syscalls.o
+_ebss                                             build/startup_stm32f767xx.o
+_edata                                            build/startup_stm32f767xx.o
+_end                                              build/sysmem.o
+_estack                                           build/startup_stm32f767xx.o
+                                                  build/sysmem.o
+_execve                                           build/syscalls.o
+_exit                                             build/syscalls.o
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-exit.o)
+_fini                                             /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crti.o
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-fini.o)
+_fork                                             build/syscalls.o
+_fstat                                            build/syscalls.o
+_getpid                                           build/syscalls.o
+_global_atexit                                    /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__call_atexit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o)
+_global_impure_ptr                                /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o)
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-exit.o)
+_impure_ptr                                       /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o)
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-errno.o)
+_init                                             /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+dp/hard/crti.o
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o)
+_isatty                                           build/syscalls.o
+_kill                                             build/syscalls.o
+_link                                             build/syscalls.o
+_lseek                                            build/syscalls.o
+_mainCRTStartup                                   /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+_open                                             build/syscalls.o
+_read                                             build/syscalls.o
+_sbrk                                             build/sysmem.o
+_sbss                                             build/startup_stm32f767xx.o
+_sdata                                            build/startup_stm32f767xx.o
+_sidata                                           build/startup_stm32f767xx.o
+_stack_init                                       /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+_start                                            /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+_stat                                             build/syscalls.o
+_times                                            build/syscalls.o
+_unlink                                           build/syscalls.o
+_wait                                             build/syscalls.o
+_write                                            build/syscalls.o
+atexit                                            /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-atexit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+disk                                              build/ff_gen_drv.o
+                                                  build/diskio.o
+disk_initialize                                   build/diskio.o
+                                                  build/ff.o
+disk_ioctl                                        build/diskio.o
+                                                  build/ff.o
+disk_read                                         build/diskio.o
+                                                  build/ff.o
+disk_status                                       build/diskio.o
+                                                  build/ff.o
+disk_write                                        build/diskio.o
+                                                  build/ff.o
+environ                                           build/syscalls.o
+exit                                              /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-exit.o)
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+f_close                                           build/ff.o
+f_closedir                                        build/ff.o
+f_getfree                                         build/ff.o
+f_gets                                            build/ff.o
+f_lseek                                           build/ff.o
+f_mkdir                                           build/ff.o
+f_mkfs                                            build/ff.o
+f_mount                                           build/ff.o
+f_open                                            build/ff.o
+f_opendir                                         build/ff.o
+f_printf                                          build/ff.o
+f_putc                                            build/ff.o
+f_puts                                            build/ff.o
+f_read                                            build/ff.o
+f_readdir                                         build/ff.o
+f_rename                                          build/ff.o
+f_stat                                            build/ff.o
+f_sync                                            build/ff.o
+f_truncate                                        build/ff.o
+f_unlink                                          build/ff.o
+f_write                                           build/ff.o
+fgoto                                             build/main.o
+flg_tmt                                           build/main.o
+                                                  build/stm32f7xx_it.o
+fresult                                           build/main.o
+g_pfnVectors                                      build/startup_stm32f767xx.o
+get_fattime                                       build/fatfs.o
+                                                  build/ff.o
+hadc1                                             build/main.o
+                                                  build/stm32f7xx_it.o
+hadc3                                             build/main.o
+                                                  build/stm32f7xx_it.o
+hardware_init_hook                                /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+hsd1                                              build/main.o
+                                                  build/bsp_driver_sd.o
+htim10                                            build/main.o
+                                                  build/stm32f7xx_it.o
+initialise_monitor_handles                        build/syscalls.o
+main                                              build/main.o
+                                                  build/startup_stm32f767xx.o
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+malloc                                            /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o)
+memset                                            /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-memset.o)
+                                                  build/stm32f7xx_hal_msp.o
+                                                  build/main.o
+                                                  /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+pFlash                                            build/stm32f7xx_hal_flash.o
+                                                  build/stm32f7xx_hal_flash_ex.o
+retSD                                             build/fatfs.o
+sizeoffile                                        build/main.o
+software_init_hook                                /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+task                                              build/main.o
+temp16                                            build/main.o
+temp32                                            build/main.o
+test                                              build/main.o
+u_rx_flg                                          build/main.o
+u_tx_flg                                          build/main.o
+                                                  build/stm32f7xx_it.o
+uart_buf                                          build/main.o
+                                                  build/stm32f7xx_it.o
+uwTick                                            build/stm32f7xx_hal.o
+uwTickFreq                                        build/stm32f7xx_hal.o
+uwTickPrio                                        build/stm32f7xx_hal.o
+                                                  build/stm32f7xx_hal_rcc.o
diff --git a/build/bsp_driver_sd.d b/build/bsp_driver_sd.d
new file mode 100644
index 0000000..dc0eede
--- /dev/null
+++ b/build/bsp_driver_sd.d
@@ -0,0 +1,66 @@
+build/bsp_driver_sd.o: Src/bsp_driver_sd.c Inc/bsp_driver_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Inc/fatfs_platform.h
+Inc/bsp_driver_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Inc/fatfs_platform.h:
diff --git a/build/bsp_driver_sd.lst b/build/bsp_driver_sd.lst
new file mode 100644
index 0000000..6c28aed
--- /dev/null
+++ b/build/bsp_driver_sd.lst
@@ -0,0 +1,1087 @@
+ARM GAS  /tmp/cckWiXI8.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"bsp_driver_sd.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.BSP_SD_ITConfig,"ax",%progbits
+  17              		.align	1
+  18              		.weak	BSP_SD_ITConfig
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	BSP_SD_ITConfig:
+  26              	.LFB142:
+  27              		.file 1 "Src/bsp_driver_sd.c"
+   1:Src/bsp_driver_sd.c **** /* USER CODE BEGIN Header */
+   2:Src/bsp_driver_sd.c **** /**
+   3:Src/bsp_driver_sd.c ****  ******************************************************************************
+   4:Src/bsp_driver_sd.c ****  * @file    bsp_driver_sd.c for F7 (based on stm32756g_eval_sd.c)
+   5:Src/bsp_driver_sd.c ****  * @brief   This file includes a generic uSD card driver.
+   6:Src/bsp_driver_sd.c ****  *          To be completed by the user according to the board used for the project.
+   7:Src/bsp_driver_sd.c ****  * @note    Some functions generated as weak: they can be overridden by
+   8:Src/bsp_driver_sd.c ****  *          - code in user files
+   9:Src/bsp_driver_sd.c ****  *          - or BSP code from the FW pack files
+  10:Src/bsp_driver_sd.c ****  *          if such files are added to the generated project (by the user).
+  11:Src/bsp_driver_sd.c ****  ******************************************************************************
+  12:Src/bsp_driver_sd.c ****   * @attention
+  13:Src/bsp_driver_sd.c ****   *
+  14:Src/bsp_driver_sd.c ****   * Copyright (c) 2023 STMicroelectronics.
+  15:Src/bsp_driver_sd.c ****   * All rights reserved.
+  16:Src/bsp_driver_sd.c ****   *
+  17:Src/bsp_driver_sd.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  18:Src/bsp_driver_sd.c ****   * in the root directory of this software component.
+  19:Src/bsp_driver_sd.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  20:Src/bsp_driver_sd.c ****   *
+  21:Src/bsp_driver_sd.c ****  ******************************************************************************
+  22:Src/bsp_driver_sd.c ****  */
+  23:Src/bsp_driver_sd.c **** /* USER CODE END Header */
+  24:Src/bsp_driver_sd.c **** 
+  25:Src/bsp_driver_sd.c **** #ifdef OLD_API
+  26:Src/bsp_driver_sd.c **** /* kept to avoid issue when migrating old projects. */
+  27:Src/bsp_driver_sd.c **** /* USER CODE BEGIN 0 */
+  28:Src/bsp_driver_sd.c **** 
+  29:Src/bsp_driver_sd.c **** /* USER CODE END 0 */
+  30:Src/bsp_driver_sd.c **** #else
+  31:Src/bsp_driver_sd.c **** /* USER CODE BEGIN FirstSection */
+ARM GAS  /tmp/cckWiXI8.s 			page 2
+
+
+  32:Src/bsp_driver_sd.c **** /* can be used to modify / undefine following code or add new definitions */
+  33:Src/bsp_driver_sd.c **** /* USER CODE END FirstSection */
+  34:Src/bsp_driver_sd.c **** /* Includes ------------------------------------------------------------------*/
+  35:Src/bsp_driver_sd.c **** #include "bsp_driver_sd.h"
+  36:Src/bsp_driver_sd.c **** 
+  37:Src/bsp_driver_sd.c **** /* Extern variables ---------------------------------------------------------*/
+  38:Src/bsp_driver_sd.c **** 
+  39:Src/bsp_driver_sd.c **** extern SD_HandleTypeDef hsd1;
+  40:Src/bsp_driver_sd.c **** 
+  41:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeInitSection */
+  42:Src/bsp_driver_sd.c **** /* can be used to modify / undefine following code or add code */
+  43:Src/bsp_driver_sd.c **** /* USER CODE END BeforeInitSection */
+  44:Src/bsp_driver_sd.c **** /**
+  45:Src/bsp_driver_sd.c ****   * @brief  Initializes the SD card device.
+  46:Src/bsp_driver_sd.c ****   * @retval SD status
+  47:Src/bsp_driver_sd.c ****   */
+  48:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_Init(void)
+  49:Src/bsp_driver_sd.c **** {
+  50:Src/bsp_driver_sd.c ****   uint8_t sd_state = MSD_OK;
+  51:Src/bsp_driver_sd.c ****   /* Check if the SD card is plugged in the slot */
+  52:Src/bsp_driver_sd.c ****   if (BSP_SD_IsDetected() != SD_PRESENT)
+  53:Src/bsp_driver_sd.c ****   {
+  54:Src/bsp_driver_sd.c ****     return MSD_ERROR_SD_NOT_PRESENT;
+  55:Src/bsp_driver_sd.c ****   }
+  56:Src/bsp_driver_sd.c ****   /* HAL SD initialization */
+  57:Src/bsp_driver_sd.c ****   sd_state = HAL_SD_Init(&hsd1);
+  58:Src/bsp_driver_sd.c ****   /* Configure SD Bus width (4 bits mode selected) */
+  59:Src/bsp_driver_sd.c ****   if (sd_state == MSD_OK)
+  60:Src/bsp_driver_sd.c ****   {
+  61:Src/bsp_driver_sd.c ****     /* Enable wide operation */
+  62:Src/bsp_driver_sd.c ****     if (HAL_SD_ConfigWideBusOperation(&hsd1, SDMMC_BUS_WIDE_4B) != HAL_OK)
+  63:Src/bsp_driver_sd.c ****     {
+  64:Src/bsp_driver_sd.c ****       sd_state = MSD_ERROR;
+  65:Src/bsp_driver_sd.c ****     }
+  66:Src/bsp_driver_sd.c ****   }
+  67:Src/bsp_driver_sd.c **** 
+  68:Src/bsp_driver_sd.c ****   return sd_state;
+  69:Src/bsp_driver_sd.c **** }
+  70:Src/bsp_driver_sd.c **** /* USER CODE BEGIN AfterInitSection */
+  71:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */
+  72:Src/bsp_driver_sd.c **** /* USER CODE END AfterInitSection */
+  73:Src/bsp_driver_sd.c **** 
+  74:Src/bsp_driver_sd.c **** /* USER CODE BEGIN InterruptMode */
+  75:Src/bsp_driver_sd.c **** /**
+  76:Src/bsp_driver_sd.c ****   * @brief  Configures Interrupt mode for SD detection pin.
+  77:Src/bsp_driver_sd.c ****   * @retval Returns 0
+  78:Src/bsp_driver_sd.c ****   */
+  79:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_ITConfig(void)
+  80:Src/bsp_driver_sd.c **** {
+  28              		.loc 1 80 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  81:Src/bsp_driver_sd.c ****   /* Code to be updated by the user or replaced by one from the FW pack (in a stmxxxx_sd.c file) */
+  82:Src/bsp_driver_sd.c **** 
+  83:Src/bsp_driver_sd.c ****   return (uint8_t)0;
+ARM GAS  /tmp/cckWiXI8.s 			page 3
+
+
+  33              		.loc 1 83 3 view .LVU1
+  84:Src/bsp_driver_sd.c **** }
+  34              		.loc 1 84 1 is_stmt 0 view .LVU2
+  35 0000 0020     		movs	r0, #0
+  36 0002 7047     		bx	lr
+  37              		.cfi_endproc
+  38              	.LFE142:
+  40              		.section	.text.BSP_SD_ReadBlocks,"ax",%progbits
+  41              		.align	1
+  42              		.weak	BSP_SD_ReadBlocks
+  43              		.syntax unified
+  44              		.thumb
+  45              		.thumb_func
+  46              		.fpu fpv5-d16
+  48              	BSP_SD_ReadBlocks:
+  49              	.LVL0:
+  50              	.LFB143:
+  85:Src/bsp_driver_sd.c **** 
+  86:Src/bsp_driver_sd.c **** /* USER CODE END InterruptMode */
+  87:Src/bsp_driver_sd.c **** 
+  88:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeReadBlocksSection */
+  89:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */
+  90:Src/bsp_driver_sd.c **** /* USER CODE END BeforeReadBlocksSection */
+  91:Src/bsp_driver_sd.c **** /**
+  92:Src/bsp_driver_sd.c ****   * @brief  Reads block(s) from a specified address in an SD card, in polling mode.
+  93:Src/bsp_driver_sd.c ****   * @param  pData: Pointer to the buffer that will contain the data to transmit
+  94:Src/bsp_driver_sd.c ****   * @param  ReadAddr: Address from where data is to be read
+  95:Src/bsp_driver_sd.c ****   * @param  NumOfBlocks: Number of SD blocks to read
+  96:Src/bsp_driver_sd.c ****   * @param  Timeout: Timeout for read operation
+  97:Src/bsp_driver_sd.c ****   * @retval SD status
+  98:Src/bsp_driver_sd.c ****   */
+  99:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t
+ 100:Src/bsp_driver_sd.c **** {
+  51              		.loc 1 100 1 is_stmt 1 view -0
+  52              		.cfi_startproc
+  53              		@ args = 0, pretend = 0, frame = 0
+  54              		@ frame_needed = 0, uses_anonymous_args = 0
+  55              		.loc 1 100 1 is_stmt 0 view .LVU4
+  56 0000 00B5     		push	{lr}
+  57              	.LCFI0:
+  58              		.cfi_def_cfa_offset 4
+  59              		.cfi_offset 14, -4
+  60 0002 83B0     		sub	sp, sp, #12
+  61              	.LCFI1:
+  62              		.cfi_def_cfa_offset 16
+ 101:Src/bsp_driver_sd.c ****   uint8_t sd_state = MSD_OK;
+  63              		.loc 1 101 3 is_stmt 1 view .LVU5
+  64              	.LVL1:
+ 102:Src/bsp_driver_sd.c **** 
+ 103:Src/bsp_driver_sd.c ****   if (HAL_SD_ReadBlocks(&hsd1, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) != HAL_OK)
+  65              		.loc 1 103 3 view .LVU6
+  66              		.loc 1 103 7 is_stmt 0 view .LVU7
+  67 0004 0093     		str	r3, [sp]
+  68 0006 1346     		mov	r3, r2
+  69              	.LVL2:
+  70              		.loc 1 103 7 view .LVU8
+  71 0008 0A46     		mov	r2, r1
+ARM GAS  /tmp/cckWiXI8.s 			page 4
+
+
+  72              	.LVL3:
+  73              		.loc 1 103 7 view .LVU9
+  74 000a 0146     		mov	r1, r0
+  75              	.LVL4:
+  76              		.loc 1 103 7 view .LVU10
+  77 000c 0348     		ldr	r0, .L6
+  78              	.LVL5:
+  79              		.loc 1 103 7 view .LVU11
+  80 000e FFF7FEFF 		bl	HAL_SD_ReadBlocks
+  81              	.LVL6:
+  82              		.loc 1 103 6 view .LVU12
+  83 0012 00B1     		cbz	r0, .L3
+ 104:Src/bsp_driver_sd.c ****   {
+ 105:Src/bsp_driver_sd.c ****     sd_state = MSD_ERROR;
+  84              		.loc 1 105 14 view .LVU13
+  85 0014 0120     		movs	r0, #1
+  86              	.L3:
+  87              	.LVL7:
+ 106:Src/bsp_driver_sd.c ****   }
+ 107:Src/bsp_driver_sd.c **** 
+ 108:Src/bsp_driver_sd.c ****   return sd_state;
+  88              		.loc 1 108 3 is_stmt 1 view .LVU14
+ 109:Src/bsp_driver_sd.c **** }
+  89              		.loc 1 109 1 is_stmt 0 view .LVU15
+  90 0016 03B0     		add	sp, sp, #12
+  91              	.LCFI2:
+  92              		.cfi_def_cfa_offset 4
+  93              		@ sp needed
+  94 0018 5DF804FB 		ldr	pc, [sp], #4
+  95              	.L7:
+  96              		.align	2
+  97              	.L6:
+  98 001c 00000000 		.word	hsd1
+  99              		.cfi_endproc
+ 100              	.LFE143:
+ 102              		.section	.text.BSP_SD_WriteBlocks,"ax",%progbits
+ 103              		.align	1
+ 104              		.weak	BSP_SD_WriteBlocks
+ 105              		.syntax unified
+ 106              		.thumb
+ 107              		.thumb_func
+ 108              		.fpu fpv5-d16
+ 110              	BSP_SD_WriteBlocks:
+ 111              	.LVL8:
+ 112              	.LFB144:
+ 110:Src/bsp_driver_sd.c **** 
+ 111:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeWriteBlocksSection */
+ 112:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */
+ 113:Src/bsp_driver_sd.c **** /* USER CODE END BeforeWriteBlocksSection */
+ 114:Src/bsp_driver_sd.c **** /**
+ 115:Src/bsp_driver_sd.c ****   * @brief  Writes block(s) to a specified address in an SD card, in polling mode.
+ 116:Src/bsp_driver_sd.c ****   * @param  pData: Pointer to the buffer that will contain the data to transmit
+ 117:Src/bsp_driver_sd.c ****   * @param  WriteAddr: Address from where data is to be written
+ 118:Src/bsp_driver_sd.c ****   * @param  NumOfBlocks: Number of SD blocks to write
+ 119:Src/bsp_driver_sd.c ****   * @param  Timeout: Timeout for write operation
+ 120:Src/bsp_driver_sd.c ****   * @retval SD status
+ 121:Src/bsp_driver_sd.c ****   */
+ARM GAS  /tmp/cckWiXI8.s 			page 5
+
+
+ 122:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32
+ 123:Src/bsp_driver_sd.c **** {
+ 113              		.loc 1 123 1 is_stmt 1 view -0
+ 114              		.cfi_startproc
+ 115              		@ args = 0, pretend = 0, frame = 0
+ 116              		@ frame_needed = 0, uses_anonymous_args = 0
+ 117              		.loc 1 123 1 is_stmt 0 view .LVU17
+ 118 0000 00B5     		push	{lr}
+ 119              	.LCFI3:
+ 120              		.cfi_def_cfa_offset 4
+ 121              		.cfi_offset 14, -4
+ 122 0002 83B0     		sub	sp, sp, #12
+ 123              	.LCFI4:
+ 124              		.cfi_def_cfa_offset 16
+ 124:Src/bsp_driver_sd.c ****   uint8_t sd_state = MSD_OK;
+ 125              		.loc 1 124 3 is_stmt 1 view .LVU18
+ 126              	.LVL9:
+ 125:Src/bsp_driver_sd.c **** 
+ 126:Src/bsp_driver_sd.c ****   if (HAL_SD_WriteBlocks(&hsd1, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK)
+ 127              		.loc 1 126 3 view .LVU19
+ 128              		.loc 1 126 7 is_stmt 0 view .LVU20
+ 129 0004 0093     		str	r3, [sp]
+ 130 0006 1346     		mov	r3, r2
+ 131              	.LVL10:
+ 132              		.loc 1 126 7 view .LVU21
+ 133 0008 0A46     		mov	r2, r1
+ 134              	.LVL11:
+ 135              		.loc 1 126 7 view .LVU22
+ 136 000a 0146     		mov	r1, r0
+ 137              	.LVL12:
+ 138              		.loc 1 126 7 view .LVU23
+ 139 000c 0348     		ldr	r0, .L12
+ 140              	.LVL13:
+ 141              		.loc 1 126 7 view .LVU24
+ 142 000e FFF7FEFF 		bl	HAL_SD_WriteBlocks
+ 143              	.LVL14:
+ 144              		.loc 1 126 6 view .LVU25
+ 145 0012 00B1     		cbz	r0, .L9
+ 127:Src/bsp_driver_sd.c ****   {
+ 128:Src/bsp_driver_sd.c ****     sd_state = MSD_ERROR;
+ 146              		.loc 1 128 14 view .LVU26
+ 147 0014 0120     		movs	r0, #1
+ 148              	.L9:
+ 149              	.LVL15:
+ 129:Src/bsp_driver_sd.c ****   }
+ 130:Src/bsp_driver_sd.c **** 
+ 131:Src/bsp_driver_sd.c ****   return sd_state;
+ 150              		.loc 1 131 3 is_stmt 1 view .LVU27
+ 132:Src/bsp_driver_sd.c **** }
+ 151              		.loc 1 132 1 is_stmt 0 view .LVU28
+ 152 0016 03B0     		add	sp, sp, #12
+ 153              	.LCFI5:
+ 154              		.cfi_def_cfa_offset 4
+ 155              		@ sp needed
+ 156 0018 5DF804FB 		ldr	pc, [sp], #4
+ 157              	.L13:
+ 158              		.align	2
+ARM GAS  /tmp/cckWiXI8.s 			page 6
+
+
+ 159              	.L12:
+ 160 001c 00000000 		.word	hsd1
+ 161              		.cfi_endproc
+ 162              	.LFE144:
+ 164              		.section	.text.BSP_SD_ReadBlocks_DMA,"ax",%progbits
+ 165              		.align	1
+ 166              		.weak	BSP_SD_ReadBlocks_DMA
+ 167              		.syntax unified
+ 168              		.thumb
+ 169              		.thumb_func
+ 170              		.fpu fpv5-d16
+ 172              	BSP_SD_ReadBlocks_DMA:
+ 173              	.LVL16:
+ 174              	.LFB145:
+ 133:Src/bsp_driver_sd.c **** 
+ 134:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeReadDMABlocksSection */
+ 135:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */
+ 136:Src/bsp_driver_sd.c **** /* USER CODE END BeforeReadDMABlocksSection */
+ 137:Src/bsp_driver_sd.c **** /**
+ 138:Src/bsp_driver_sd.c ****   * @brief  Reads block(s) from a specified address in an SD card, in DMA mode.
+ 139:Src/bsp_driver_sd.c ****   * @param  pData: Pointer to the buffer that will contain the data to transmit
+ 140:Src/bsp_driver_sd.c ****   * @param  ReadAddr: Address from where data is to be read
+ 141:Src/bsp_driver_sd.c ****   * @param  NumOfBlocks: Number of SD blocks to read
+ 142:Src/bsp_driver_sd.c ****   * @retval SD status
+ 143:Src/bsp_driver_sd.c ****   */
+ 144:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks)
+ 145:Src/bsp_driver_sd.c **** {
+ 175              		.loc 1 145 1 is_stmt 1 view -0
+ 176              		.cfi_startproc
+ 177              		@ args = 0, pretend = 0, frame = 0
+ 178              		@ frame_needed = 0, uses_anonymous_args = 0
+ 179              		.loc 1 145 1 is_stmt 0 view .LVU30
+ 180 0000 08B5     		push	{r3, lr}
+ 181              	.LCFI6:
+ 182              		.cfi_def_cfa_offset 8
+ 183              		.cfi_offset 3, -8
+ 184              		.cfi_offset 14, -4
+ 185 0002 1346     		mov	r3, r2
+ 146:Src/bsp_driver_sd.c ****   uint8_t sd_state = MSD_OK;
+ 186              		.loc 1 146 3 is_stmt 1 view .LVU31
+ 187              	.LVL17:
+ 147:Src/bsp_driver_sd.c **** 
+ 148:Src/bsp_driver_sd.c ****   /* Read block(s) in DMA transfer mode */
+ 149:Src/bsp_driver_sd.c ****   if (HAL_SD_ReadBlocks_DMA(&hsd1, (uint8_t *)pData, ReadAddr, NumOfBlocks) != HAL_OK)
+ 188              		.loc 1 149 3 view .LVU32
+ 189              		.loc 1 149 7 is_stmt 0 view .LVU33
+ 190 0004 0A46     		mov	r2, r1
+ 191              	.LVL18:
+ 192              		.loc 1 149 7 view .LVU34
+ 193 0006 0146     		mov	r1, r0
+ 194              	.LVL19:
+ 195              		.loc 1 149 7 view .LVU35
+ 196 0008 0248     		ldr	r0, .L18
+ 197              	.LVL20:
+ 198              		.loc 1 149 7 view .LVU36
+ 199 000a FFF7FEFF 		bl	HAL_SD_ReadBlocks_DMA
+ 200              	.LVL21:
+ARM GAS  /tmp/cckWiXI8.s 			page 7
+
+
+ 201              		.loc 1 149 6 view .LVU37
+ 202 000e 00B1     		cbz	r0, .L15
+ 150:Src/bsp_driver_sd.c ****   {
+ 151:Src/bsp_driver_sd.c ****     sd_state = MSD_ERROR;
+ 203              		.loc 1 151 14 view .LVU38
+ 204 0010 0120     		movs	r0, #1
+ 205              	.L15:
+ 206              	.LVL22:
+ 152:Src/bsp_driver_sd.c ****   }
+ 153:Src/bsp_driver_sd.c **** 
+ 154:Src/bsp_driver_sd.c ****   return sd_state;
+ 207              		.loc 1 154 3 is_stmt 1 view .LVU39
+ 155:Src/bsp_driver_sd.c **** }
+ 208              		.loc 1 155 1 is_stmt 0 view .LVU40
+ 209 0012 08BD     		pop	{r3, pc}
+ 210              	.L19:
+ 211              		.align	2
+ 212              	.L18:
+ 213 0014 00000000 		.word	hsd1
+ 214              		.cfi_endproc
+ 215              	.LFE145:
+ 217              		.section	.text.BSP_SD_WriteBlocks_DMA,"ax",%progbits
+ 218              		.align	1
+ 219              		.weak	BSP_SD_WriteBlocks_DMA
+ 220              		.syntax unified
+ 221              		.thumb
+ 222              		.thumb_func
+ 223              		.fpu fpv5-d16
+ 225              	BSP_SD_WriteBlocks_DMA:
+ 226              	.LVL23:
+ 227              	.LFB146:
+ 156:Src/bsp_driver_sd.c **** 
+ 157:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeWriteDMABlocksSection */
+ 158:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */
+ 159:Src/bsp_driver_sd.c **** /* USER CODE END BeforeWriteDMABlocksSection */
+ 160:Src/bsp_driver_sd.c **** /**
+ 161:Src/bsp_driver_sd.c ****   * @brief  Writes block(s) to a specified address in an SD card, in DMA mode.
+ 162:Src/bsp_driver_sd.c ****   * @param  pData: Pointer to the buffer that will contain the data to transmit
+ 163:Src/bsp_driver_sd.c ****   * @param  WriteAddr: Address from where data is to be written
+ 164:Src/bsp_driver_sd.c ****   * @param  NumOfBlocks: Number of SD blocks to write
+ 165:Src/bsp_driver_sd.c ****   * @retval SD status
+ 166:Src/bsp_driver_sd.c ****   */
+ 167:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks)
+ 168:Src/bsp_driver_sd.c **** {
+ 228              		.loc 1 168 1 is_stmt 1 view -0
+ 229              		.cfi_startproc
+ 230              		@ args = 0, pretend = 0, frame = 0
+ 231              		@ frame_needed = 0, uses_anonymous_args = 0
+ 232              		.loc 1 168 1 is_stmt 0 view .LVU42
+ 233 0000 08B5     		push	{r3, lr}
+ 234              	.LCFI7:
+ 235              		.cfi_def_cfa_offset 8
+ 236              		.cfi_offset 3, -8
+ 237              		.cfi_offset 14, -4
+ 238 0002 1346     		mov	r3, r2
+ 169:Src/bsp_driver_sd.c ****   uint8_t sd_state = MSD_OK;
+ 239              		.loc 1 169 3 is_stmt 1 view .LVU43
+ARM GAS  /tmp/cckWiXI8.s 			page 8
+
+
+ 240              	.LVL24:
+ 170:Src/bsp_driver_sd.c **** 
+ 171:Src/bsp_driver_sd.c ****   /* Write block(s) in DMA transfer mode */
+ 172:Src/bsp_driver_sd.c ****   if (HAL_SD_WriteBlocks_DMA(&hsd1, (uint8_t *)pData, WriteAddr, NumOfBlocks) != HAL_OK)
+ 241              		.loc 1 172 3 view .LVU44
+ 242              		.loc 1 172 7 is_stmt 0 view .LVU45
+ 243 0004 0A46     		mov	r2, r1
+ 244              	.LVL25:
+ 245              		.loc 1 172 7 view .LVU46
+ 246 0006 0146     		mov	r1, r0
+ 247              	.LVL26:
+ 248              		.loc 1 172 7 view .LVU47
+ 249 0008 0248     		ldr	r0, .L24
+ 250              	.LVL27:
+ 251              		.loc 1 172 7 view .LVU48
+ 252 000a FFF7FEFF 		bl	HAL_SD_WriteBlocks_DMA
+ 253              	.LVL28:
+ 254              		.loc 1 172 6 view .LVU49
+ 255 000e 00B1     		cbz	r0, .L21
+ 173:Src/bsp_driver_sd.c ****   {
+ 174:Src/bsp_driver_sd.c ****     sd_state = MSD_ERROR;
+ 256              		.loc 1 174 14 view .LVU50
+ 257 0010 0120     		movs	r0, #1
+ 258              	.L21:
+ 259              	.LVL29:
+ 175:Src/bsp_driver_sd.c ****   }
+ 176:Src/bsp_driver_sd.c **** 
+ 177:Src/bsp_driver_sd.c ****   return sd_state;
+ 260              		.loc 1 177 3 is_stmt 1 view .LVU51
+ 178:Src/bsp_driver_sd.c **** }
+ 261              		.loc 1 178 1 is_stmt 0 view .LVU52
+ 262 0012 08BD     		pop	{r3, pc}
+ 263              	.L25:
+ 264              		.align	2
+ 265              	.L24:
+ 266 0014 00000000 		.word	hsd1
+ 267              		.cfi_endproc
+ 268              	.LFE146:
+ 270              		.section	.text.BSP_SD_Erase,"ax",%progbits
+ 271              		.align	1
+ 272              		.weak	BSP_SD_Erase
+ 273              		.syntax unified
+ 274              		.thumb
+ 275              		.thumb_func
+ 276              		.fpu fpv5-d16
+ 278              	BSP_SD_Erase:
+ 279              	.LVL30:
+ 280              	.LFB147:
+ 179:Src/bsp_driver_sd.c **** 
+ 180:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeEraseSection */
+ 181:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */
+ 182:Src/bsp_driver_sd.c **** /* USER CODE END BeforeEraseSection */
+ 183:Src/bsp_driver_sd.c **** /**
+ 184:Src/bsp_driver_sd.c ****   * @brief  Erases the specified memory area of the given SD card.
+ 185:Src/bsp_driver_sd.c ****   * @param  StartAddr: Start byte address
+ 186:Src/bsp_driver_sd.c ****   * @param  EndAddr: End byte address
+ 187:Src/bsp_driver_sd.c ****   * @retval SD status
+ARM GAS  /tmp/cckWiXI8.s 			page 9
+
+
+ 188:Src/bsp_driver_sd.c ****   */
+ 189:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr)
+ 190:Src/bsp_driver_sd.c **** {
+ 281              		.loc 1 190 1 is_stmt 1 view -0
+ 282              		.cfi_startproc
+ 283              		@ args = 0, pretend = 0, frame = 0
+ 284              		@ frame_needed = 0, uses_anonymous_args = 0
+ 285              		.loc 1 190 1 is_stmt 0 view .LVU54
+ 286 0000 08B5     		push	{r3, lr}
+ 287              	.LCFI8:
+ 288              		.cfi_def_cfa_offset 8
+ 289              		.cfi_offset 3, -8
+ 290              		.cfi_offset 14, -4
+ 291 0002 0A46     		mov	r2, r1
+ 191:Src/bsp_driver_sd.c ****   uint8_t sd_state = MSD_OK;
+ 292              		.loc 1 191 3 is_stmt 1 view .LVU55
+ 293              	.LVL31:
+ 192:Src/bsp_driver_sd.c **** 
+ 193:Src/bsp_driver_sd.c ****   if (HAL_SD_Erase(&hsd1, StartAddr, EndAddr) != HAL_OK)
+ 294              		.loc 1 193 3 view .LVU56
+ 295              		.loc 1 193 7 is_stmt 0 view .LVU57
+ 296 0004 0146     		mov	r1, r0
+ 297              	.LVL32:
+ 298              		.loc 1 193 7 view .LVU58
+ 299 0006 0348     		ldr	r0, .L30
+ 300              	.LVL33:
+ 301              		.loc 1 193 7 view .LVU59
+ 302 0008 FFF7FEFF 		bl	HAL_SD_Erase
+ 303              	.LVL34:
+ 304              		.loc 1 193 6 view .LVU60
+ 305 000c 00B1     		cbz	r0, .L27
+ 194:Src/bsp_driver_sd.c ****   {
+ 195:Src/bsp_driver_sd.c ****     sd_state = MSD_ERROR;
+ 306              		.loc 1 195 14 view .LVU61
+ 307 000e 0120     		movs	r0, #1
+ 308              	.L27:
+ 309              	.LVL35:
+ 196:Src/bsp_driver_sd.c ****   }
+ 197:Src/bsp_driver_sd.c **** 
+ 198:Src/bsp_driver_sd.c ****   return sd_state;
+ 310              		.loc 1 198 3 is_stmt 1 view .LVU62
+ 199:Src/bsp_driver_sd.c **** }
+ 311              		.loc 1 199 1 is_stmt 0 view .LVU63
+ 312 0010 08BD     		pop	{r3, pc}
+ 313              	.L31:
+ 314 0012 00BF     		.align	2
+ 315              	.L30:
+ 316 0014 00000000 		.word	hsd1
+ 317              		.cfi_endproc
+ 318              	.LFE147:
+ 320              		.section	.text.BSP_SD_GetCardState,"ax",%progbits
+ 321              		.align	1
+ 322              		.weak	BSP_SD_GetCardState
+ 323              		.syntax unified
+ 324              		.thumb
+ 325              		.thumb_func
+ 326              		.fpu fpv5-d16
+ARM GAS  /tmp/cckWiXI8.s 			page 10
+
+
+ 328              	BSP_SD_GetCardState:
+ 329              	.LFB148:
+ 200:Src/bsp_driver_sd.c **** 
+ 201:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeGetCardStateSection */
+ 202:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */
+ 203:Src/bsp_driver_sd.c **** /* USER CODE END BeforeGetCardStateSection */
+ 204:Src/bsp_driver_sd.c **** 
+ 205:Src/bsp_driver_sd.c **** /**
+ 206:Src/bsp_driver_sd.c ****   * @brief  Gets the current SD card data status.
+ 207:Src/bsp_driver_sd.c ****   * @param  None
+ 208:Src/bsp_driver_sd.c ****   * @retval Data transfer state.
+ 209:Src/bsp_driver_sd.c ****   *          This value can be one of the following values:
+ 210:Src/bsp_driver_sd.c ****   *            @arg  SD_TRANSFER_OK: No data transfer is acting
+ 211:Src/bsp_driver_sd.c ****   *            @arg  SD_TRANSFER_BUSY: Data transfer is acting
+ 212:Src/bsp_driver_sd.c ****   */
+ 213:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_GetCardState(void)
+ 214:Src/bsp_driver_sd.c **** {
+ 330              		.loc 1 214 1 is_stmt 1 view -0
+ 331              		.cfi_startproc
+ 332              		@ args = 0, pretend = 0, frame = 0
+ 333              		@ frame_needed = 0, uses_anonymous_args = 0
+ 334 0000 08B5     		push	{r3, lr}
+ 335              	.LCFI9:
+ 336              		.cfi_def_cfa_offset 8
+ 337              		.cfi_offset 3, -8
+ 338              		.cfi_offset 14, -4
+ 215:Src/bsp_driver_sd.c ****   return ((HAL_SD_GetCardState(&hsd1) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY
+ 339              		.loc 1 215 3 view .LVU65
+ 340              		.loc 1 215 12 is_stmt 0 view .LVU66
+ 341 0002 0348     		ldr	r0, .L34
+ 342 0004 FFF7FEFF 		bl	HAL_SD_GetCardState
+ 343              	.LVL36:
+ 216:Src/bsp_driver_sd.c **** }
+ 344              		.loc 1 216 1 view .LVU67
+ 345 0008 0438     		subs	r0, r0, #4
+ 346 000a 18BF     		it	ne
+ 347 000c 0120     		movne	r0, #1
+ 348 000e 08BD     		pop	{r3, pc}
+ 349              	.L35:
+ 350              		.align	2
+ 351              	.L34:
+ 352 0010 00000000 		.word	hsd1
+ 353              		.cfi_endproc
+ 354              	.LFE148:
+ 356              		.section	.text.BSP_SD_GetCardInfo,"ax",%progbits
+ 357              		.align	1
+ 358              		.weak	BSP_SD_GetCardInfo
+ 359              		.syntax unified
+ 360              		.thumb
+ 361              		.thumb_func
+ 362              		.fpu fpv5-d16
+ 364              	BSP_SD_GetCardInfo:
+ 365              	.LVL37:
+ 366              	.LFB149:
+ 217:Src/bsp_driver_sd.c **** 
+ 218:Src/bsp_driver_sd.c **** /**
+ 219:Src/bsp_driver_sd.c ****   * @brief  Get SD information about specific SD card.
+ARM GAS  /tmp/cckWiXI8.s 			page 11
+
+
+ 220:Src/bsp_driver_sd.c ****   * @param  CardInfo: Pointer to HAL_SD_CardInfoTypedef structure
+ 221:Src/bsp_driver_sd.c ****   * @retval None
+ 222:Src/bsp_driver_sd.c ****   */
+ 223:Src/bsp_driver_sd.c **** __weak void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo)
+ 224:Src/bsp_driver_sd.c **** {
+ 367              		.loc 1 224 1 is_stmt 1 view -0
+ 368              		.cfi_startproc
+ 369              		@ args = 0, pretend = 0, frame = 0
+ 370              		@ frame_needed = 0, uses_anonymous_args = 0
+ 371              		.loc 1 224 1 is_stmt 0 view .LVU69
+ 372 0000 08B5     		push	{r3, lr}
+ 373              	.LCFI10:
+ 374              		.cfi_def_cfa_offset 8
+ 375              		.cfi_offset 3, -8
+ 376              		.cfi_offset 14, -4
+ 377 0002 0146     		mov	r1, r0
+ 225:Src/bsp_driver_sd.c ****   /* Get SD card Information */
+ 226:Src/bsp_driver_sd.c ****   HAL_SD_GetCardInfo(&hsd1, CardInfo);
+ 378              		.loc 1 226 3 is_stmt 1 view .LVU70
+ 379 0004 0148     		ldr	r0, .L38
+ 380              	.LVL38:
+ 381              		.loc 1 226 3 is_stmt 0 view .LVU71
+ 382 0006 FFF7FEFF 		bl	HAL_SD_GetCardInfo
+ 383              	.LVL39:
+ 227:Src/bsp_driver_sd.c **** }
+ 384              		.loc 1 227 1 view .LVU72
+ 385 000a 08BD     		pop	{r3, pc}
+ 386              	.L39:
+ 387              		.align	2
+ 388              	.L38:
+ 389 000c 00000000 		.word	hsd1
+ 390              		.cfi_endproc
+ 391              	.LFE149:
+ 393              		.section	.text.BSP_SD_AbortCallback,"ax",%progbits
+ 394              		.align	1
+ 395              		.weak	BSP_SD_AbortCallback
+ 396              		.syntax unified
+ 397              		.thumb
+ 398              		.thumb_func
+ 399              		.fpu fpv5-d16
+ 401              	BSP_SD_AbortCallback:
+ 402              	.LFB153:
+ 228:Src/bsp_driver_sd.c **** 
+ 229:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeCallBacksSection */
+ 230:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */
+ 231:Src/bsp_driver_sd.c **** /* USER CODE END BeforeCallBacksSection */
+ 232:Src/bsp_driver_sd.c **** /**
+ 233:Src/bsp_driver_sd.c ****   * @brief SD Abort callbacks
+ 234:Src/bsp_driver_sd.c ****   * @param hsd: SD handle
+ 235:Src/bsp_driver_sd.c ****   * @retval None
+ 236:Src/bsp_driver_sd.c ****   */
+ 237:Src/bsp_driver_sd.c **** void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+ 238:Src/bsp_driver_sd.c **** {
+ 239:Src/bsp_driver_sd.c ****   BSP_SD_AbortCallback();
+ 240:Src/bsp_driver_sd.c **** }
+ 241:Src/bsp_driver_sd.c **** 
+ 242:Src/bsp_driver_sd.c **** /**
+ARM GAS  /tmp/cckWiXI8.s 			page 12
+
+
+ 243:Src/bsp_driver_sd.c ****   * @brief Tx Transfer completed callback
+ 244:Src/bsp_driver_sd.c ****   * @param hsd: SD handle
+ 245:Src/bsp_driver_sd.c ****   * @retval None
+ 246:Src/bsp_driver_sd.c ****   */
+ 247:Src/bsp_driver_sd.c **** void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+ 248:Src/bsp_driver_sd.c **** {
+ 249:Src/bsp_driver_sd.c ****   BSP_SD_WriteCpltCallback();
+ 250:Src/bsp_driver_sd.c **** }
+ 251:Src/bsp_driver_sd.c **** 
+ 252:Src/bsp_driver_sd.c **** /**
+ 253:Src/bsp_driver_sd.c ****   * @brief Rx Transfer completed callback
+ 254:Src/bsp_driver_sd.c ****   * @param hsd: SD handle
+ 255:Src/bsp_driver_sd.c ****   * @retval None
+ 256:Src/bsp_driver_sd.c ****   */
+ 257:Src/bsp_driver_sd.c **** void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+ 258:Src/bsp_driver_sd.c **** {
+ 259:Src/bsp_driver_sd.c ****   BSP_SD_ReadCpltCallback();
+ 260:Src/bsp_driver_sd.c **** }
+ 261:Src/bsp_driver_sd.c **** 
+ 262:Src/bsp_driver_sd.c **** /* USER CODE BEGIN CallBacksSection_C */
+ 263:Src/bsp_driver_sd.c **** /**
+ 264:Src/bsp_driver_sd.c ****   * @brief BSP SD Abort callback
+ 265:Src/bsp_driver_sd.c ****   * @retval None
+ 266:Src/bsp_driver_sd.c ****   * @note empty (up to the user to fill it in or to remove it if useless)
+ 267:Src/bsp_driver_sd.c ****   */
+ 268:Src/bsp_driver_sd.c **** __weak void BSP_SD_AbortCallback(void)
+ 269:Src/bsp_driver_sd.c **** {
+ 403              		.loc 1 269 1 is_stmt 1 view -0
+ 404              		.cfi_startproc
+ 405              		@ args = 0, pretend = 0, frame = 0
+ 406              		@ frame_needed = 0, uses_anonymous_args = 0
+ 407              		@ link register save eliminated.
+ 270:Src/bsp_driver_sd.c **** 
+ 271:Src/bsp_driver_sd.c **** }
+ 408              		.loc 1 271 1 view .LVU74
+ 409 0000 7047     		bx	lr
+ 410              		.cfi_endproc
+ 411              	.LFE153:
+ 413              		.section	.text.HAL_SD_AbortCallback,"ax",%progbits
+ 414              		.align	1
+ 415              		.global	HAL_SD_AbortCallback
+ 416              		.syntax unified
+ 417              		.thumb
+ 418              		.thumb_func
+ 419              		.fpu fpv5-d16
+ 421              	HAL_SD_AbortCallback:
+ 422              	.LVL40:
+ 423              	.LFB150:
+ 238:Src/bsp_driver_sd.c ****   BSP_SD_AbortCallback();
+ 424              		.loc 1 238 1 view -0
+ 425              		.cfi_startproc
+ 426              		@ args = 0, pretend = 0, frame = 0
+ 427              		@ frame_needed = 0, uses_anonymous_args = 0
+ 238:Src/bsp_driver_sd.c ****   BSP_SD_AbortCallback();
+ 428              		.loc 1 238 1 is_stmt 0 view .LVU76
+ 429 0000 08B5     		push	{r3, lr}
+ 430              	.LCFI11:
+ARM GAS  /tmp/cckWiXI8.s 			page 13
+
+
+ 431              		.cfi_def_cfa_offset 8
+ 432              		.cfi_offset 3, -8
+ 433              		.cfi_offset 14, -4
+ 239:Src/bsp_driver_sd.c **** }
+ 434              		.loc 1 239 3 is_stmt 1 view .LVU77
+ 435 0002 FFF7FEFF 		bl	BSP_SD_AbortCallback
+ 436              	.LVL41:
+ 240:Src/bsp_driver_sd.c **** 
+ 437              		.loc 1 240 1 is_stmt 0 view .LVU78
+ 438 0006 08BD     		pop	{r3, pc}
+ 439              		.cfi_endproc
+ 440              	.LFE150:
+ 442              		.section	.text.BSP_SD_WriteCpltCallback,"ax",%progbits
+ 443              		.align	1
+ 444              		.weak	BSP_SD_WriteCpltCallback
+ 445              		.syntax unified
+ 446              		.thumb
+ 447              		.thumb_func
+ 448              		.fpu fpv5-d16
+ 450              	BSP_SD_WriteCpltCallback:
+ 451              	.LFB154:
+ 272:Src/bsp_driver_sd.c **** 
+ 273:Src/bsp_driver_sd.c **** /**
+ 274:Src/bsp_driver_sd.c ****   * @brief BSP Tx Transfer completed callback
+ 275:Src/bsp_driver_sd.c ****   * @retval None
+ 276:Src/bsp_driver_sd.c ****   * @note empty (up to the user to fill it in or to remove it if useless)
+ 277:Src/bsp_driver_sd.c ****   */
+ 278:Src/bsp_driver_sd.c **** __weak void BSP_SD_WriteCpltCallback(void)
+ 279:Src/bsp_driver_sd.c **** {
+ 452              		.loc 1 279 1 is_stmt 1 view -0
+ 453              		.cfi_startproc
+ 454              		@ args = 0, pretend = 0, frame = 0
+ 455              		@ frame_needed = 0, uses_anonymous_args = 0
+ 456              		@ link register save eliminated.
+ 280:Src/bsp_driver_sd.c **** 
+ 281:Src/bsp_driver_sd.c **** }
+ 457              		.loc 1 281 1 view .LVU80
+ 458 0000 7047     		bx	lr
+ 459              		.cfi_endproc
+ 460              	.LFE154:
+ 462              		.section	.text.HAL_SD_TxCpltCallback,"ax",%progbits
+ 463              		.align	1
+ 464              		.global	HAL_SD_TxCpltCallback
+ 465              		.syntax unified
+ 466              		.thumb
+ 467              		.thumb_func
+ 468              		.fpu fpv5-d16
+ 470              	HAL_SD_TxCpltCallback:
+ 471              	.LVL42:
+ 472              	.LFB151:
+ 248:Src/bsp_driver_sd.c ****   BSP_SD_WriteCpltCallback();
+ 473              		.loc 1 248 1 view -0
+ 474              		.cfi_startproc
+ 475              		@ args = 0, pretend = 0, frame = 0
+ 476              		@ frame_needed = 0, uses_anonymous_args = 0
+ 248:Src/bsp_driver_sd.c ****   BSP_SD_WriteCpltCallback();
+ 477              		.loc 1 248 1 is_stmt 0 view .LVU82
+ARM GAS  /tmp/cckWiXI8.s 			page 14
+
+
+ 478 0000 08B5     		push	{r3, lr}
+ 479              	.LCFI12:
+ 480              		.cfi_def_cfa_offset 8
+ 481              		.cfi_offset 3, -8
+ 482              		.cfi_offset 14, -4
+ 249:Src/bsp_driver_sd.c **** }
+ 483              		.loc 1 249 3 is_stmt 1 view .LVU83
+ 484 0002 FFF7FEFF 		bl	BSP_SD_WriteCpltCallback
+ 485              	.LVL43:
+ 250:Src/bsp_driver_sd.c **** 
+ 486              		.loc 1 250 1 is_stmt 0 view .LVU84
+ 487 0006 08BD     		pop	{r3, pc}
+ 488              		.cfi_endproc
+ 489              	.LFE151:
+ 491              		.section	.text.BSP_SD_ReadCpltCallback,"ax",%progbits
+ 492              		.align	1
+ 493              		.weak	BSP_SD_ReadCpltCallback
+ 494              		.syntax unified
+ 495              		.thumb
+ 496              		.thumb_func
+ 497              		.fpu fpv5-d16
+ 499              	BSP_SD_ReadCpltCallback:
+ 500              	.LFB155:
+ 282:Src/bsp_driver_sd.c **** 
+ 283:Src/bsp_driver_sd.c **** /**
+ 284:Src/bsp_driver_sd.c ****   * @brief BSP Rx Transfer completed callback
+ 285:Src/bsp_driver_sd.c ****   * @retval None
+ 286:Src/bsp_driver_sd.c ****   * @note empty (up to the user to fill it in or to remove it if useless)
+ 287:Src/bsp_driver_sd.c ****   */
+ 288:Src/bsp_driver_sd.c **** __weak void BSP_SD_ReadCpltCallback(void)
+ 289:Src/bsp_driver_sd.c **** {
+ 501              		.loc 1 289 1 is_stmt 1 view -0
+ 502              		.cfi_startproc
+ 503              		@ args = 0, pretend = 0, frame = 0
+ 504              		@ frame_needed = 0, uses_anonymous_args = 0
+ 505              		@ link register save eliminated.
+ 290:Src/bsp_driver_sd.c **** 
+ 291:Src/bsp_driver_sd.c **** }
+ 506              		.loc 1 291 1 view .LVU86
+ 507 0000 7047     		bx	lr
+ 508              		.cfi_endproc
+ 509              	.LFE155:
+ 511              		.section	.text.HAL_SD_RxCpltCallback,"ax",%progbits
+ 512              		.align	1
+ 513              		.global	HAL_SD_RxCpltCallback
+ 514              		.syntax unified
+ 515              		.thumb
+ 516              		.thumb_func
+ 517              		.fpu fpv5-d16
+ 519              	HAL_SD_RxCpltCallback:
+ 520              	.LVL44:
+ 521              	.LFB152:
+ 258:Src/bsp_driver_sd.c ****   BSP_SD_ReadCpltCallback();
+ 522              		.loc 1 258 1 view -0
+ 523              		.cfi_startproc
+ 524              		@ args = 0, pretend = 0, frame = 0
+ 525              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cckWiXI8.s 			page 15
+
+
+ 258:Src/bsp_driver_sd.c ****   BSP_SD_ReadCpltCallback();
+ 526              		.loc 1 258 1 is_stmt 0 view .LVU88
+ 527 0000 08B5     		push	{r3, lr}
+ 528              	.LCFI13:
+ 529              		.cfi_def_cfa_offset 8
+ 530              		.cfi_offset 3, -8
+ 531              		.cfi_offset 14, -4
+ 259:Src/bsp_driver_sd.c **** }
+ 532              		.loc 1 259 3 is_stmt 1 view .LVU89
+ 533 0002 FFF7FEFF 		bl	BSP_SD_ReadCpltCallback
+ 534              	.LVL45:
+ 260:Src/bsp_driver_sd.c **** 
+ 535              		.loc 1 260 1 is_stmt 0 view .LVU90
+ 536 0006 08BD     		pop	{r3, pc}
+ 537              		.cfi_endproc
+ 538              	.LFE152:
+ 540              		.section	.text.BSP_SD_IsDetected,"ax",%progbits
+ 541              		.align	1
+ 542              		.weak	BSP_SD_IsDetected
+ 543              		.syntax unified
+ 544              		.thumb
+ 545              		.thumb_func
+ 546              		.fpu fpv5-d16
+ 548              	BSP_SD_IsDetected:
+ 549              	.LFB156:
+ 292:Src/bsp_driver_sd.c **** /* USER CODE END CallBacksSection_C */
+ 293:Src/bsp_driver_sd.c **** #endif
+ 294:Src/bsp_driver_sd.c **** 
+ 295:Src/bsp_driver_sd.c **** /**
+ 296:Src/bsp_driver_sd.c ****  * @brief  Detects if SD card is correctly plugged in the memory slot or not.
+ 297:Src/bsp_driver_sd.c ****  * @param  None
+ 298:Src/bsp_driver_sd.c ****  * @retval Returns if SD is detected or not
+ 299:Src/bsp_driver_sd.c ****  */
+ 300:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_IsDetected(void)
+ 301:Src/bsp_driver_sd.c **** {
+ 550              		.loc 1 301 1 is_stmt 1 view -0
+ 551              		.cfi_startproc
+ 552              		@ args = 0, pretend = 0, frame = 8
+ 553              		@ frame_needed = 0, uses_anonymous_args = 0
+ 554 0000 00B5     		push	{lr}
+ 555              	.LCFI14:
+ 556              		.cfi_def_cfa_offset 4
+ 557              		.cfi_offset 14, -4
+ 558 0002 83B0     		sub	sp, sp, #12
+ 559              	.LCFI15:
+ 560              		.cfi_def_cfa_offset 16
+ 302:Src/bsp_driver_sd.c ****   __IO uint8_t status = SD_PRESENT;
+ 561              		.loc 1 302 3 view .LVU92
+ 562              		.loc 1 302 16 is_stmt 0 view .LVU93
+ 563 0004 0123     		movs	r3, #1
+ 564 0006 8DF80730 		strb	r3, [sp, #7]
+ 303:Src/bsp_driver_sd.c **** 
+ 304:Src/bsp_driver_sd.c ****   if (BSP_PlatformIsDetected() == 0x0)
+ 565              		.loc 1 304 3 is_stmt 1 view .LVU94
+ 566              		.loc 1 304 7 is_stmt 0 view .LVU95
+ 567 000a FFF7FEFF 		bl	BSP_PlatformIsDetected
+ 568              	.LVL46:
+ARM GAS  /tmp/cckWiXI8.s 			page 16
+
+
+ 569              		.loc 1 304 6 view .LVU96
+ 570 000e 10B9     		cbnz	r0, .L50
+ 305:Src/bsp_driver_sd.c ****   {
+ 306:Src/bsp_driver_sd.c ****     status = SD_NOT_PRESENT;
+ 571              		.loc 1 306 5 is_stmt 1 view .LVU97
+ 572              		.loc 1 306 12 is_stmt 0 view .LVU98
+ 573 0010 0023     		movs	r3, #0
+ 574 0012 8DF80730 		strb	r3, [sp, #7]
+ 575              	.L50:
+ 307:Src/bsp_driver_sd.c ****   }
+ 308:Src/bsp_driver_sd.c **** 
+ 309:Src/bsp_driver_sd.c ****   return status;
+ 576              		.loc 1 309 3 is_stmt 1 view .LVU99
+ 577              		.loc 1 309 10 is_stmt 0 view .LVU100
+ 578 0016 9DF80700 		ldrb	r0, [sp, #7]	@ zero_extendqisi2
+ 310:Src/bsp_driver_sd.c **** }
+ 579              		.loc 1 310 1 view .LVU101
+ 580 001a 03B0     		add	sp, sp, #12
+ 581              	.LCFI16:
+ 582              		.cfi_def_cfa_offset 4
+ 583              		@ sp needed
+ 584 001c 5DF804FB 		ldr	pc, [sp], #4
+ 585              		.cfi_endproc
+ 586              	.LFE156:
+ 588              		.section	.text.BSP_SD_Init,"ax",%progbits
+ 589              		.align	1
+ 590              		.weak	BSP_SD_Init
+ 591              		.syntax unified
+ 592              		.thumb
+ 593              		.thumb_func
+ 594              		.fpu fpv5-d16
+ 596              	BSP_SD_Init:
+ 597              	.LFB141:
+  49:Src/bsp_driver_sd.c ****   uint8_t sd_state = MSD_OK;
+ 598              		.loc 1 49 1 is_stmt 1 view -0
+ 599              		.cfi_startproc
+ 600              		@ args = 0, pretend = 0, frame = 0
+ 601              		@ frame_needed = 0, uses_anonymous_args = 0
+ 602 0000 38B5     		push	{r3, r4, r5, lr}
+ 603              	.LCFI17:
+ 604              		.cfi_def_cfa_offset 16
+ 605              		.cfi_offset 3, -16
+ 606              		.cfi_offset 4, -12
+ 607              		.cfi_offset 5, -8
+ 608              		.cfi_offset 14, -4
+  50:Src/bsp_driver_sd.c ****   /* Check if the SD card is plugged in the slot */
+ 609              		.loc 1 50 3 view .LVU103
+ 610              	.LVL47:
+  52:Src/bsp_driver_sd.c ****   {
+ 611              		.loc 1 52 3 view .LVU104
+  52:Src/bsp_driver_sd.c ****   {
+ 612              		.loc 1 52 7 is_stmt 0 view .LVU105
+ 613 0002 FFF7FEFF 		bl	BSP_SD_IsDetected
+ 614              	.LVL48:
+  52:Src/bsp_driver_sd.c ****   {
+ 615              		.loc 1 52 6 view .LVU106
+ 616 0006 0128     		cmp	r0, #1
+ARM GAS  /tmp/cckWiXI8.s 			page 17
+
+
+ 617 0008 02D0     		beq	.L57
+  54:Src/bsp_driver_sd.c ****   }
+ 618              		.loc 1 54 12 view .LVU107
+ 619 000a 0225     		movs	r5, #2
+ 620              	.LVL49:
+ 621              	.L53:
+  69:Src/bsp_driver_sd.c **** /* USER CODE BEGIN AfterInitSection */
+ 622              		.loc 1 69 1 view .LVU108
+ 623 000c 2846     		mov	r0, r5
+ 624 000e 38BD     		pop	{r3, r4, r5, pc}
+ 625              	.LVL50:
+ 626              	.L57:
+  69:Src/bsp_driver_sd.c **** /* USER CODE BEGIN AfterInitSection */
+ 627              		.loc 1 69 1 view .LVU109
+ 628 0010 0446     		mov	r4, r0
+  57:Src/bsp_driver_sd.c ****   /* Configure SD Bus width (4 bits mode selected) */
+ 629              		.loc 1 57 3 is_stmt 1 view .LVU110
+  57:Src/bsp_driver_sd.c ****   /* Configure SD Bus width (4 bits mode selected) */
+ 630              		.loc 1 57 14 is_stmt 0 view .LVU111
+ 631 0012 0748     		ldr	r0, .L58
+ 632 0014 FFF7FEFF 		bl	HAL_SD_Init
+ 633              	.LVL51:
+  59:Src/bsp_driver_sd.c ****   {
+ 634              		.loc 1 59 3 is_stmt 1 view .LVU112
+  59:Src/bsp_driver_sd.c ****   {
+ 635              		.loc 1 59 6 is_stmt 0 view .LVU113
+ 636 0018 0546     		mov	r5, r0
+ 637 001a 0028     		cmp	r0, #0
+ 638 001c F6D1     		bne	.L53
+  62:Src/bsp_driver_sd.c ****     {
+ 639              		.loc 1 62 5 is_stmt 1 view .LVU114
+  62:Src/bsp_driver_sd.c ****     {
+ 640              		.loc 1 62 9 is_stmt 0 view .LVU115
+ 641 001e 4FF40061 		mov	r1, #2048
+ 642 0022 0348     		ldr	r0, .L58
+ 643              	.LVL52:
+  62:Src/bsp_driver_sd.c ****     {
+ 644              		.loc 1 62 9 view .LVU116
+ 645 0024 FFF7FEFF 		bl	HAL_SD_ConfigWideBusOperation
+ 646              	.LVL53:
+  62:Src/bsp_driver_sd.c ****     {
+ 647              		.loc 1 62 8 view .LVU117
+ 648 0028 0028     		cmp	r0, #0
+ 649 002a EFD0     		beq	.L53
+  64:Src/bsp_driver_sd.c ****     }
+ 650              		.loc 1 64 16 view .LVU118
+ 651 002c 2546     		mov	r5, r4
+ 652 002e EDE7     		b	.L53
+ 653              	.L59:
+ 654              		.align	2
+ 655              	.L58:
+ 656 0030 00000000 		.word	hsd1
+ 657              		.cfi_endproc
+ 658              	.LFE141:
+ 660              		.text
+ 661              	.Letext0:
+ 662              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ARM GAS  /tmp/cckWiXI8.s 			page 18
+
+
+ 663              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 664              		.file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 665              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 666              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h"
+ 667              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h"
+ 668              		.file 8 "Inc/fatfs_platform.h"
+ARM GAS  /tmp/cckWiXI8.s 			page 19
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 bsp_driver_sd.c
+     /tmp/cckWiXI8.s:17     .text.BSP_SD_ITConfig:0000000000000000 $t
+     /tmp/cckWiXI8.s:25     .text.BSP_SD_ITConfig:0000000000000000 BSP_SD_ITConfig
+     /tmp/cckWiXI8.s:41     .text.BSP_SD_ReadBlocks:0000000000000000 $t
+     /tmp/cckWiXI8.s:48     .text.BSP_SD_ReadBlocks:0000000000000000 BSP_SD_ReadBlocks
+     /tmp/cckWiXI8.s:98     .text.BSP_SD_ReadBlocks:000000000000001c $d
+     /tmp/cckWiXI8.s:103    .text.BSP_SD_WriteBlocks:0000000000000000 $t
+     /tmp/cckWiXI8.s:110    .text.BSP_SD_WriteBlocks:0000000000000000 BSP_SD_WriteBlocks
+     /tmp/cckWiXI8.s:160    .text.BSP_SD_WriteBlocks:000000000000001c $d
+     /tmp/cckWiXI8.s:165    .text.BSP_SD_ReadBlocks_DMA:0000000000000000 $t
+     /tmp/cckWiXI8.s:172    .text.BSP_SD_ReadBlocks_DMA:0000000000000000 BSP_SD_ReadBlocks_DMA
+     /tmp/cckWiXI8.s:213    .text.BSP_SD_ReadBlocks_DMA:0000000000000014 $d
+     /tmp/cckWiXI8.s:218    .text.BSP_SD_WriteBlocks_DMA:0000000000000000 $t
+     /tmp/cckWiXI8.s:225    .text.BSP_SD_WriteBlocks_DMA:0000000000000000 BSP_SD_WriteBlocks_DMA
+     /tmp/cckWiXI8.s:266    .text.BSP_SD_WriteBlocks_DMA:0000000000000014 $d
+     /tmp/cckWiXI8.s:271    .text.BSP_SD_Erase:0000000000000000 $t
+     /tmp/cckWiXI8.s:278    .text.BSP_SD_Erase:0000000000000000 BSP_SD_Erase
+     /tmp/cckWiXI8.s:316    .text.BSP_SD_Erase:0000000000000014 $d
+     /tmp/cckWiXI8.s:321    .text.BSP_SD_GetCardState:0000000000000000 $t
+     /tmp/cckWiXI8.s:328    .text.BSP_SD_GetCardState:0000000000000000 BSP_SD_GetCardState
+     /tmp/cckWiXI8.s:352    .text.BSP_SD_GetCardState:0000000000000010 $d
+     /tmp/cckWiXI8.s:357    .text.BSP_SD_GetCardInfo:0000000000000000 $t
+     /tmp/cckWiXI8.s:364    .text.BSP_SD_GetCardInfo:0000000000000000 BSP_SD_GetCardInfo
+     /tmp/cckWiXI8.s:389    .text.BSP_SD_GetCardInfo:000000000000000c $d
+     /tmp/cckWiXI8.s:394    .text.BSP_SD_AbortCallback:0000000000000000 $t
+     /tmp/cckWiXI8.s:401    .text.BSP_SD_AbortCallback:0000000000000000 BSP_SD_AbortCallback
+     /tmp/cckWiXI8.s:414    .text.HAL_SD_AbortCallback:0000000000000000 $t
+     /tmp/cckWiXI8.s:421    .text.HAL_SD_AbortCallback:0000000000000000 HAL_SD_AbortCallback
+     /tmp/cckWiXI8.s:443    .text.BSP_SD_WriteCpltCallback:0000000000000000 $t
+     /tmp/cckWiXI8.s:450    .text.BSP_SD_WriteCpltCallback:0000000000000000 BSP_SD_WriteCpltCallback
+     /tmp/cckWiXI8.s:463    .text.HAL_SD_TxCpltCallback:0000000000000000 $t
+     /tmp/cckWiXI8.s:470    .text.HAL_SD_TxCpltCallback:0000000000000000 HAL_SD_TxCpltCallback
+     /tmp/cckWiXI8.s:492    .text.BSP_SD_ReadCpltCallback:0000000000000000 $t
+     /tmp/cckWiXI8.s:499    .text.BSP_SD_ReadCpltCallback:0000000000000000 BSP_SD_ReadCpltCallback
+     /tmp/cckWiXI8.s:512    .text.HAL_SD_RxCpltCallback:0000000000000000 $t
+     /tmp/cckWiXI8.s:519    .text.HAL_SD_RxCpltCallback:0000000000000000 HAL_SD_RxCpltCallback
+     /tmp/cckWiXI8.s:541    .text.BSP_SD_IsDetected:0000000000000000 $t
+     /tmp/cckWiXI8.s:548    .text.BSP_SD_IsDetected:0000000000000000 BSP_SD_IsDetected
+     /tmp/cckWiXI8.s:589    .text.BSP_SD_Init:0000000000000000 $t
+     /tmp/cckWiXI8.s:596    .text.BSP_SD_Init:0000000000000000 BSP_SD_Init
+     /tmp/cckWiXI8.s:656    .text.BSP_SD_Init:0000000000000030 $d
+
+UNDEFINED SYMBOLS
+HAL_SD_ReadBlocks
+hsd1
+HAL_SD_WriteBlocks
+HAL_SD_ReadBlocks_DMA
+HAL_SD_WriteBlocks_DMA
+HAL_SD_Erase
+HAL_SD_GetCardState
+HAL_SD_GetCardInfo
+BSP_PlatformIsDetected
+HAL_SD_Init
+HAL_SD_ConfigWideBusOperation
diff --git a/build/bsp_driver_sd.o b/build/bsp_driver_sd.o
new file mode 100644
index 0000000..a99105c
Binary files /dev/null and b/build/bsp_driver_sd.o differ
diff --git a/build/diskio.d b/build/diskio.d
new file mode 100644
index 0000000..d60839f
--- /dev/null
+++ b/build/diskio.d
@@ -0,0 +1,100 @@
+build/diskio.o: Middlewares/Third_Party/FatFs/src/diskio.c \
+ Middlewares/Third_Party/FatFs/src/diskio.h \
+ Middlewares/Third_Party/FatFs/src/integer.h \
+ Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \
+ Middlewares/Third_Party/FatFs/src/ff.h Inc/ffconf.h Inc/main.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/bsp_driver_sd.h \
+ Inc/fatfs_platform.h
+Middlewares/Third_Party/FatFs/src/diskio.h:
+Middlewares/Third_Party/FatFs/src/integer.h:
+Middlewares/Third_Party/FatFs/src/ff_gen_drv.h:
+Middlewares/Third_Party/FatFs/src/ff.h:
+Inc/ffconf.h:
+Inc/main.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h:
+Inc/bsp_driver_sd.h:
+Inc/fatfs_platform.h:
diff --git a/build/diskio.lst b/build/diskio.lst
new file mode 100644
index 0000000..a5f04e5
--- /dev/null
+++ b/build/diskio.lst
@@ -0,0 +1,478 @@
+ARM GAS  /tmp/ccQS9hBN.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"diskio.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.disk_status,"ax",%progbits
+  17              		.align	1
+  18              		.global	disk_status
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	disk_status:
+  26              	.LVL0:
+  27              	.LFB1183:
+  28              		.file 1 "Middlewares/Third_Party/FatFs/src/diskio.c"
+   1:Middlewares/Third_Party/FatFs/src/diskio.c **** /*-----------------------------------------------------------------------*/
+   2:Middlewares/Third_Party/FatFs/src/diskio.c **** /* Low level disk I/O module skeleton for FatFs     (C)ChaN, 2017        */
+   3:Middlewares/Third_Party/FatFs/src/diskio.c **** /*                                                                       */
+   4:Middlewares/Third_Party/FatFs/src/diskio.c **** /*   Portions COPYRIGHT 2017 STMicroelectronics                          */
+   5:Middlewares/Third_Party/FatFs/src/diskio.c **** /*   Portions Copyright (C) 2017, ChaN, all right reserved               */
+   6:Middlewares/Third_Party/FatFs/src/diskio.c **** /*-----------------------------------------------------------------------*/
+   7:Middlewares/Third_Party/FatFs/src/diskio.c **** /* If a working storage control module is available, it should be        */
+   8:Middlewares/Third_Party/FatFs/src/diskio.c **** /* attached to the FatFs via a glue function rather than modifying it.   */
+   9:Middlewares/Third_Party/FatFs/src/diskio.c **** /* This is an example of glue functions to attach various existing      */
+  10:Middlewares/Third_Party/FatFs/src/diskio.c **** /* storage control modules to the FatFs module with a defined API.       */
+  11:Middlewares/Third_Party/FatFs/src/diskio.c **** /*-----------------------------------------------------------------------*/
+  12:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+  13:Middlewares/Third_Party/FatFs/src/diskio.c **** /* Includes ------------------------------------------------------------------*/
+  14:Middlewares/Third_Party/FatFs/src/diskio.c **** #include "diskio.h"
+  15:Middlewares/Third_Party/FatFs/src/diskio.c **** #include "ff_gen_drv.h"
+  16:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+  17:Middlewares/Third_Party/FatFs/src/diskio.c **** #if defined ( __GNUC__ )
+  18:Middlewares/Third_Party/FatFs/src/diskio.c **** #ifndef __weak
+  19:Middlewares/Third_Party/FatFs/src/diskio.c **** #define __weak __attribute__((weak))
+  20:Middlewares/Third_Party/FatFs/src/diskio.c **** #endif
+  21:Middlewares/Third_Party/FatFs/src/diskio.c **** #endif
+  22:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+  23:Middlewares/Third_Party/FatFs/src/diskio.c **** /* Private typedef -----------------------------------------------------------*/
+  24:Middlewares/Third_Party/FatFs/src/diskio.c **** /* Private define ------------------------------------------------------------*/
+  25:Middlewares/Third_Party/FatFs/src/diskio.c **** /* Private variables ---------------------------------------------------------*/
+  26:Middlewares/Third_Party/FatFs/src/diskio.c **** extern Disk_drvTypeDef  disk;
+  27:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+  28:Middlewares/Third_Party/FatFs/src/diskio.c **** /* Private function prototypes -----------------------------------------------*/
+  29:Middlewares/Third_Party/FatFs/src/diskio.c **** /* Private functions ---------------------------------------------------------*/
+  30:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+ARM GAS  /tmp/ccQS9hBN.s 			page 2
+
+
+  31:Middlewares/Third_Party/FatFs/src/diskio.c **** /**
+  32:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @brief  Gets Disk Status
+  33:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  pdrv: Physical drive number (0..)
+  34:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @retval DSTATUS: Operation status
+  35:Middlewares/Third_Party/FatFs/src/diskio.c ****   */
+  36:Middlewares/Third_Party/FatFs/src/diskio.c **** DSTATUS disk_status (
+  37:Middlewares/Third_Party/FatFs/src/diskio.c **** 	BYTE pdrv		/* Physical drive number to identify the drive */
+  38:Middlewares/Third_Party/FatFs/src/diskio.c **** )
+  39:Middlewares/Third_Party/FatFs/src/diskio.c **** {
+  29              		.loc 1 39 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		.loc 1 39 1 is_stmt 0 view .LVU1
+  34 0000 08B5     		push	{r3, lr}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 8
+  37              		.cfi_offset 3, -8
+  38              		.cfi_offset 14, -4
+  40:Middlewares/Third_Party/FatFs/src/diskio.c ****   DSTATUS stat;
+  39              		.loc 1 40 3 is_stmt 1 view .LVU2
+  41:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+  42:Middlewares/Third_Party/FatFs/src/diskio.c ****   stat = disk.drv[pdrv]->disk_status(disk.lun[pdrv]);
+  40              		.loc 1 42 3 view .LVU3
+  41              		.loc 1 42 18 is_stmt 0 view .LVU4
+  42 0002 044B     		ldr	r3, .L3
+  43 0004 03EB8002 		add	r2, r3, r0, lsl #2
+  44 0008 5268     		ldr	r2, [r2, #4]
+  45              		.loc 1 42 24 view .LVU5
+  46 000a 5268     		ldr	r2, [r2, #4]
+  47              		.loc 1 42 10 view .LVU6
+  48 000c 0344     		add	r3, r3, r0
+  49 000e 187A     		ldrb	r0, [r3, #8]	@ zero_extendqisi2
+  50              	.LVL1:
+  51              		.loc 1 42 10 view .LVU7
+  52 0010 9047     		blx	r2
+  53              	.LVL2:
+  43:Middlewares/Third_Party/FatFs/src/diskio.c ****   return stat;
+  54              		.loc 1 43 3 is_stmt 1 view .LVU8
+  44:Middlewares/Third_Party/FatFs/src/diskio.c **** }
+  55              		.loc 1 44 1 is_stmt 0 view .LVU9
+  56 0012 08BD     		pop	{r3, pc}
+  57              	.L4:
+  58              		.align	2
+  59              	.L3:
+  60 0014 00000000 		.word	disk
+  61              		.cfi_endproc
+  62              	.LFE1183:
+  64              		.section	.text.disk_initialize,"ax",%progbits
+  65              		.align	1
+  66              		.global	disk_initialize
+  67              		.syntax unified
+  68              		.thumb
+  69              		.thumb_func
+  70              		.fpu fpv5-d16
+  72              	disk_initialize:
+  73              	.LVL3:
+ARM GAS  /tmp/ccQS9hBN.s 			page 3
+
+
+  74              	.LFB1184:
+  45:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+  46:Middlewares/Third_Party/FatFs/src/diskio.c **** /**
+  47:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @brief  Initializes a Drive
+  48:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  pdrv: Physical drive number (0..)
+  49:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @retval DSTATUS: Operation status
+  50:Middlewares/Third_Party/FatFs/src/diskio.c ****   */
+  51:Middlewares/Third_Party/FatFs/src/diskio.c **** DSTATUS disk_initialize (
+  52:Middlewares/Third_Party/FatFs/src/diskio.c **** 	BYTE pdrv				/* Physical drive nmuber to identify the drive */
+  53:Middlewares/Third_Party/FatFs/src/diskio.c **** )
+  54:Middlewares/Third_Party/FatFs/src/diskio.c **** {
+  75              		.loc 1 54 1 is_stmt 1 view -0
+  76              		.cfi_startproc
+  77              		@ args = 0, pretend = 0, frame = 0
+  78              		@ frame_needed = 0, uses_anonymous_args = 0
+  79              		.loc 1 54 1 is_stmt 0 view .LVU11
+  80 0000 08B5     		push	{r3, lr}
+  81              	.LCFI1:
+  82              		.cfi_def_cfa_offset 8
+  83              		.cfi_offset 3, -8
+  84              		.cfi_offset 14, -4
+  55:Middlewares/Third_Party/FatFs/src/diskio.c ****   DSTATUS stat = RES_OK;
+  85              		.loc 1 55 3 is_stmt 1 view .LVU12
+  86              	.LVL4:
+  56:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+  57:Middlewares/Third_Party/FatFs/src/diskio.c ****   if(disk.is_initialized[pdrv] == 0)
+  87              		.loc 1 57 3 view .LVU13
+  88              		.loc 1 57 25 is_stmt 0 view .LVU14
+  89 0002 084B     		ldr	r3, .L9
+  90 0004 1B5C     		ldrb	r3, [r3, r0]	@ zero_extendqisi2
+  91              		.loc 1 57 5 view .LVU15
+  92 0006 53B9     		cbnz	r3, .L7
+  58:Middlewares/Third_Party/FatFs/src/diskio.c ****   {
+  59:Middlewares/Third_Party/FatFs/src/diskio.c ****     disk.is_initialized[pdrv] = 1;
+  93              		.loc 1 59 5 is_stmt 1 view .LVU16
+  94              		.loc 1 59 31 is_stmt 0 view .LVU17
+  95 0008 064B     		ldr	r3, .L9
+  96 000a 0122     		movs	r2, #1
+  97 000c 1A54     		strb	r2, [r3, r0]
+  60:Middlewares/Third_Party/FatFs/src/diskio.c ****     stat = disk.drv[pdrv]->disk_initialize(disk.lun[pdrv]);
+  98              		.loc 1 60 5 is_stmt 1 view .LVU18
+  99              		.loc 1 60 20 is_stmt 0 view .LVU19
+ 100 000e 03EB8002 		add	r2, r3, r0, lsl #2
+ 101 0012 5268     		ldr	r2, [r2, #4]
+ 102              		.loc 1 60 26 view .LVU20
+ 103 0014 1268     		ldr	r2, [r2]
+ 104              		.loc 1 60 12 view .LVU21
+ 105 0016 1844     		add	r0, r0, r3
+ 106              	.LVL5:
+ 107              		.loc 1 60 12 view .LVU22
+ 108 0018 007A     		ldrb	r0, [r0, #8]	@ zero_extendqisi2
+ 109 001a 9047     		blx	r2
+ 110              	.LVL6:
+ 111              	.L6:
+  61:Middlewares/Third_Party/FatFs/src/diskio.c ****   }
+  62:Middlewares/Third_Party/FatFs/src/diskio.c ****   return stat;
+ 112              		.loc 1 62 3 is_stmt 1 view .LVU23
+ARM GAS  /tmp/ccQS9hBN.s 			page 4
+
+
+  63:Middlewares/Third_Party/FatFs/src/diskio.c **** }
+ 113              		.loc 1 63 1 is_stmt 0 view .LVU24
+ 114 001c 08BD     		pop	{r3, pc}
+ 115              	.LVL7:
+ 116              	.L7:
+  55:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+ 117              		.loc 1 55 11 view .LVU25
+ 118 001e 0020     		movs	r0, #0
+ 119              	.LVL8:
+  55:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+ 120              		.loc 1 55 11 view .LVU26
+ 121 0020 FCE7     		b	.L6
+ 122              	.L10:
+ 123 0022 00BF     		.align	2
+ 124              	.L9:
+ 125 0024 00000000 		.word	disk
+ 126              		.cfi_endproc
+ 127              	.LFE1184:
+ 129              		.section	.text.disk_read,"ax",%progbits
+ 130              		.align	1
+ 131              		.global	disk_read
+ 132              		.syntax unified
+ 133              		.thumb
+ 134              		.thumb_func
+ 135              		.fpu fpv5-d16
+ 137              	disk_read:
+ 138              	.LVL9:
+ 139              	.LFB1185:
+  64:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+  65:Middlewares/Third_Party/FatFs/src/diskio.c **** /**
+  66:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @brief  Reads Sector(s)
+  67:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  pdrv: Physical drive number (0..)
+  68:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  *buff: Data buffer to store read data
+  69:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  sector: Sector address (LBA)
+  70:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  count: Number of sectors to read (1..128)
+  71:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @retval DRESULT: Operation result
+  72:Middlewares/Third_Party/FatFs/src/diskio.c ****   */
+  73:Middlewares/Third_Party/FatFs/src/diskio.c **** DRESULT disk_read (
+  74:Middlewares/Third_Party/FatFs/src/diskio.c **** 	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+  75:Middlewares/Third_Party/FatFs/src/diskio.c **** 	BYTE *buff,		/* Data buffer to store read data */
+  76:Middlewares/Third_Party/FatFs/src/diskio.c **** 	DWORD sector,	        /* Sector address in LBA */
+  77:Middlewares/Third_Party/FatFs/src/diskio.c **** 	UINT count		/* Number of sectors to read */
+  78:Middlewares/Third_Party/FatFs/src/diskio.c **** )
+  79:Middlewares/Third_Party/FatFs/src/diskio.c **** {
+ 140              		.loc 1 79 1 is_stmt 1 view -0
+ 141              		.cfi_startproc
+ 142              		@ args = 0, pretend = 0, frame = 0
+ 143              		@ frame_needed = 0, uses_anonymous_args = 0
+ 144              		.loc 1 79 1 is_stmt 0 view .LVU28
+ 145 0000 38B5     		push	{r3, r4, r5, lr}
+ 146              	.LCFI2:
+ 147              		.cfi_def_cfa_offset 16
+ 148              		.cfi_offset 3, -16
+ 149              		.cfi_offset 4, -12
+ 150              		.cfi_offset 5, -8
+ 151              		.cfi_offset 14, -4
+  80:Middlewares/Third_Party/FatFs/src/diskio.c ****   DRESULT res;
+ARM GAS  /tmp/ccQS9hBN.s 			page 5
+
+
+ 152              		.loc 1 80 3 is_stmt 1 view .LVU29
+  81:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+  82:Middlewares/Third_Party/FatFs/src/diskio.c ****   res = disk.drv[pdrv]->disk_read(disk.lun[pdrv], buff, sector, count);
+ 153              		.loc 1 82 3 view .LVU30
+ 154              		.loc 1 82 17 is_stmt 0 view .LVU31
+ 155 0002 044C     		ldr	r4, .L13
+ 156 0004 04EB8005 		add	r5, r4, r0, lsl #2
+ 157 0008 6D68     		ldr	r5, [r5, #4]
+ 158              		.loc 1 82 23 view .LVU32
+ 159 000a AD68     		ldr	r5, [r5, #8]
+ 160              		.loc 1 82 9 view .LVU33
+ 161 000c 0444     		add	r4, r4, r0
+ 162 000e 207A     		ldrb	r0, [r4, #8]	@ zero_extendqisi2
+ 163              	.LVL10:
+ 164              		.loc 1 82 9 view .LVU34
+ 165 0010 A847     		blx	r5
+ 166              	.LVL11:
+  83:Middlewares/Third_Party/FatFs/src/diskio.c ****   return res;
+ 167              		.loc 1 83 3 is_stmt 1 view .LVU35
+  84:Middlewares/Third_Party/FatFs/src/diskio.c **** }
+ 168              		.loc 1 84 1 is_stmt 0 view .LVU36
+ 169 0012 38BD     		pop	{r3, r4, r5, pc}
+ 170              	.L14:
+ 171              		.align	2
+ 172              	.L13:
+ 173 0014 00000000 		.word	disk
+ 174              		.cfi_endproc
+ 175              	.LFE1185:
+ 177              		.section	.text.disk_write,"ax",%progbits
+ 178              		.align	1
+ 179              		.global	disk_write
+ 180              		.syntax unified
+ 181              		.thumb
+ 182              		.thumb_func
+ 183              		.fpu fpv5-d16
+ 185              	disk_write:
+ 186              	.LVL12:
+ 187              	.LFB1186:
+  85:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+  86:Middlewares/Third_Party/FatFs/src/diskio.c **** /**
+  87:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @brief  Writes Sector(s)
+  88:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  pdrv: Physical drive number (0..)
+  89:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  *buff: Data to be written
+  90:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  sector: Sector address (LBA)
+  91:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  count: Number of sectors to write (1..128)
+  92:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @retval DRESULT: Operation result
+  93:Middlewares/Third_Party/FatFs/src/diskio.c ****   */
+  94:Middlewares/Third_Party/FatFs/src/diskio.c **** #if _USE_WRITE == 1
+  95:Middlewares/Third_Party/FatFs/src/diskio.c **** DRESULT disk_write (
+  96:Middlewares/Third_Party/FatFs/src/diskio.c **** 	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+  97:Middlewares/Third_Party/FatFs/src/diskio.c **** 	const BYTE *buff,	/* Data to be written */
+  98:Middlewares/Third_Party/FatFs/src/diskio.c **** 	DWORD sector,		/* Sector address in LBA */
+  99:Middlewares/Third_Party/FatFs/src/diskio.c **** 	UINT count        	/* Number of sectors to write */
+ 100:Middlewares/Third_Party/FatFs/src/diskio.c **** )
+ 101:Middlewares/Third_Party/FatFs/src/diskio.c **** {
+ 188              		.loc 1 101 1 is_stmt 1 view -0
+ 189              		.cfi_startproc
+ARM GAS  /tmp/ccQS9hBN.s 			page 6
+
+
+ 190              		@ args = 0, pretend = 0, frame = 0
+ 191              		@ frame_needed = 0, uses_anonymous_args = 0
+ 192              		.loc 1 101 1 is_stmt 0 view .LVU38
+ 193 0000 38B5     		push	{r3, r4, r5, lr}
+ 194              	.LCFI3:
+ 195              		.cfi_def_cfa_offset 16
+ 196              		.cfi_offset 3, -16
+ 197              		.cfi_offset 4, -12
+ 198              		.cfi_offset 5, -8
+ 199              		.cfi_offset 14, -4
+ 102:Middlewares/Third_Party/FatFs/src/diskio.c ****   DRESULT res;
+ 200              		.loc 1 102 3 is_stmt 1 view .LVU39
+ 103:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+ 104:Middlewares/Third_Party/FatFs/src/diskio.c ****   res = disk.drv[pdrv]->disk_write(disk.lun[pdrv], buff, sector, count);
+ 201              		.loc 1 104 3 view .LVU40
+ 202              		.loc 1 104 17 is_stmt 0 view .LVU41
+ 203 0002 044C     		ldr	r4, .L17
+ 204 0004 04EB8005 		add	r5, r4, r0, lsl #2
+ 205 0008 6D68     		ldr	r5, [r5, #4]
+ 206              		.loc 1 104 23 view .LVU42
+ 207 000a ED68     		ldr	r5, [r5, #12]
+ 208              		.loc 1 104 9 view .LVU43
+ 209 000c 0444     		add	r4, r4, r0
+ 210 000e 207A     		ldrb	r0, [r4, #8]	@ zero_extendqisi2
+ 211              	.LVL13:
+ 212              		.loc 1 104 9 view .LVU44
+ 213 0010 A847     		blx	r5
+ 214              	.LVL14:
+ 105:Middlewares/Third_Party/FatFs/src/diskio.c ****   return res;
+ 215              		.loc 1 105 3 is_stmt 1 view .LVU45
+ 106:Middlewares/Third_Party/FatFs/src/diskio.c **** }
+ 216              		.loc 1 106 1 is_stmt 0 view .LVU46
+ 217 0012 38BD     		pop	{r3, r4, r5, pc}
+ 218              	.L18:
+ 219              		.align	2
+ 220              	.L17:
+ 221 0014 00000000 		.word	disk
+ 222              		.cfi_endproc
+ 223              	.LFE1186:
+ 225              		.section	.text.disk_ioctl,"ax",%progbits
+ 226              		.align	1
+ 227              		.global	disk_ioctl
+ 228              		.syntax unified
+ 229              		.thumb
+ 230              		.thumb_func
+ 231              		.fpu fpv5-d16
+ 233              	disk_ioctl:
+ 234              	.LVL15:
+ 235              	.LFB1187:
+ 107:Middlewares/Third_Party/FatFs/src/diskio.c **** #endif /* _USE_WRITE == 1 */
+ 108:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+ 109:Middlewares/Third_Party/FatFs/src/diskio.c **** /**
+ 110:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @brief  I/O control operation
+ 111:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  pdrv: Physical drive number (0..)
+ 112:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  cmd: Control code
+ 113:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  *buff: Buffer to send/receive control data
+ 114:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @retval DRESULT: Operation result
+ARM GAS  /tmp/ccQS9hBN.s 			page 7
+
+
+ 115:Middlewares/Third_Party/FatFs/src/diskio.c ****   */
+ 116:Middlewares/Third_Party/FatFs/src/diskio.c **** #if _USE_IOCTL == 1
+ 117:Middlewares/Third_Party/FatFs/src/diskio.c **** DRESULT disk_ioctl (
+ 118:Middlewares/Third_Party/FatFs/src/diskio.c **** 	BYTE pdrv,		/* Physical drive nmuber (0..) */
+ 119:Middlewares/Third_Party/FatFs/src/diskio.c **** 	BYTE cmd,		/* Control code */
+ 120:Middlewares/Third_Party/FatFs/src/diskio.c **** 	void *buff		/* Buffer to send/receive control data */
+ 121:Middlewares/Third_Party/FatFs/src/diskio.c **** )
+ 122:Middlewares/Third_Party/FatFs/src/diskio.c **** {
+ 236              		.loc 1 122 1 is_stmt 1 view -0
+ 237              		.cfi_startproc
+ 238              		@ args = 0, pretend = 0, frame = 0
+ 239              		@ frame_needed = 0, uses_anonymous_args = 0
+ 240              		.loc 1 122 1 is_stmt 0 view .LVU48
+ 241 0000 10B5     		push	{r4, lr}
+ 242              	.LCFI4:
+ 243              		.cfi_def_cfa_offset 8
+ 244              		.cfi_offset 4, -8
+ 245              		.cfi_offset 14, -4
+ 123:Middlewares/Third_Party/FatFs/src/diskio.c ****   DRESULT res;
+ 246              		.loc 1 123 3 is_stmt 1 view .LVU49
+ 124:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+ 125:Middlewares/Third_Party/FatFs/src/diskio.c ****   res = disk.drv[pdrv]->disk_ioctl(disk.lun[pdrv], cmd, buff);
+ 247              		.loc 1 125 3 view .LVU50
+ 248              		.loc 1 125 17 is_stmt 0 view .LVU51
+ 249 0002 044B     		ldr	r3, .L21
+ 250 0004 03EB8004 		add	r4, r3, r0, lsl #2
+ 251 0008 6468     		ldr	r4, [r4, #4]
+ 252              		.loc 1 125 23 view .LVU52
+ 253 000a 2469     		ldr	r4, [r4, #16]
+ 254              		.loc 1 125 9 view .LVU53
+ 255 000c 0344     		add	r3, r3, r0
+ 256 000e 187A     		ldrb	r0, [r3, #8]	@ zero_extendqisi2
+ 257              	.LVL16:
+ 258              		.loc 1 125 9 view .LVU54
+ 259 0010 A047     		blx	r4
+ 260              	.LVL17:
+ 126:Middlewares/Third_Party/FatFs/src/diskio.c ****   return res;
+ 261              		.loc 1 126 3 is_stmt 1 view .LVU55
+ 127:Middlewares/Third_Party/FatFs/src/diskio.c **** }
+ 262              		.loc 1 127 1 is_stmt 0 view .LVU56
+ 263 0012 10BD     		pop	{r4, pc}
+ 264              	.L22:
+ 265              		.align	2
+ 266              	.L21:
+ 267 0014 00000000 		.word	disk
+ 268              		.cfi_endproc
+ 269              	.LFE1187:
+ 271              		.section	.text.get_fattime,"ax",%progbits
+ 272              		.align	1
+ 273              		.weak	get_fattime
+ 274              		.syntax unified
+ 275              		.thumb
+ 276              		.thumb_func
+ 277              		.fpu fpv5-d16
+ 279              	get_fattime:
+ 280              	.LFB1188:
+ 128:Middlewares/Third_Party/FatFs/src/diskio.c **** #endif /* _USE_IOCTL == 1 */
+ARM GAS  /tmp/ccQS9hBN.s 			page 8
+
+
+ 129:Middlewares/Third_Party/FatFs/src/diskio.c **** 
+ 130:Middlewares/Third_Party/FatFs/src/diskio.c **** /**
+ 131:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @brief  Gets Time from RTC
+ 132:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @param  None
+ 133:Middlewares/Third_Party/FatFs/src/diskio.c ****   * @retval Time in DWORD
+ 134:Middlewares/Third_Party/FatFs/src/diskio.c ****   */
+ 135:Middlewares/Third_Party/FatFs/src/diskio.c **** __weak DWORD get_fattime (void)
+ 136:Middlewares/Third_Party/FatFs/src/diskio.c **** {
+ 281              		.loc 1 136 1 is_stmt 1 view -0
+ 282              		.cfi_startproc
+ 283              		@ args = 0, pretend = 0, frame = 0
+ 284              		@ frame_needed = 0, uses_anonymous_args = 0
+ 285              		@ link register save eliminated.
+ 137:Middlewares/Third_Party/FatFs/src/diskio.c ****   return 0;
+ 286              		.loc 1 137 3 view .LVU58
+ 138:Middlewares/Third_Party/FatFs/src/diskio.c **** }
+ 287              		.loc 1 138 1 is_stmt 0 view .LVU59
+ 288 0000 0020     		movs	r0, #0
+ 289 0002 7047     		bx	lr
+ 290              		.cfi_endproc
+ 291              	.LFE1188:
+ 293              		.text
+ 294              	.Letext0:
+ 295              		.file 2 "Middlewares/Third_Party/FatFs/src/integer.h"
+ 296              		.file 3 "Middlewares/Third_Party/FatFs/src/diskio.h"
+ 297              		.file 4 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 298              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h"
+ 299              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h"
+ 300              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+ 301              		.file 8 "Middlewares/Third_Party/FatFs/src/ff_gen_drv.h"
+ARM GAS  /tmp/ccQS9hBN.s 			page 9
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 diskio.c
+     /tmp/ccQS9hBN.s:17     .text.disk_status:0000000000000000 $t
+     /tmp/ccQS9hBN.s:25     .text.disk_status:0000000000000000 disk_status
+     /tmp/ccQS9hBN.s:60     .text.disk_status:0000000000000014 $d
+     /tmp/ccQS9hBN.s:65     .text.disk_initialize:0000000000000000 $t
+     /tmp/ccQS9hBN.s:72     .text.disk_initialize:0000000000000000 disk_initialize
+     /tmp/ccQS9hBN.s:125    .text.disk_initialize:0000000000000024 $d
+     /tmp/ccQS9hBN.s:130    .text.disk_read:0000000000000000 $t
+     /tmp/ccQS9hBN.s:137    .text.disk_read:0000000000000000 disk_read
+     /tmp/ccQS9hBN.s:173    .text.disk_read:0000000000000014 $d
+     /tmp/ccQS9hBN.s:178    .text.disk_write:0000000000000000 $t
+     /tmp/ccQS9hBN.s:185    .text.disk_write:0000000000000000 disk_write
+     /tmp/ccQS9hBN.s:221    .text.disk_write:0000000000000014 $d
+     /tmp/ccQS9hBN.s:226    .text.disk_ioctl:0000000000000000 $t
+     /tmp/ccQS9hBN.s:233    .text.disk_ioctl:0000000000000000 disk_ioctl
+     /tmp/ccQS9hBN.s:267    .text.disk_ioctl:0000000000000014 $d
+     /tmp/ccQS9hBN.s:272    .text.get_fattime:0000000000000000 $t
+     /tmp/ccQS9hBN.s:279    .text.get_fattime:0000000000000000 get_fattime
+
+UNDEFINED SYMBOLS
+disk
diff --git a/build/diskio.o b/build/diskio.o
new file mode 100644
index 0000000..84cf07d
Binary files /dev/null and b/build/diskio.o differ
diff --git a/build/fatfs.d b/build/fatfs.d
new file mode 100644
index 0000000..d83b373
--- /dev/null
+++ b/build/fatfs.d
@@ -0,0 +1,103 @@
+build/fatfs.o: Src/fatfs.c Inc/fatfs.h \
+ Middlewares/Third_Party/FatFs/src/ff.h \
+ Middlewares/Third_Party/FatFs/src/integer.h Inc/ffconf.h Inc/main.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/bsp_driver_sd.h \
+ Inc/fatfs_platform.h Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \
+ Middlewares/Third_Party/FatFs/src/diskio.h \
+ Middlewares/Third_Party/FatFs/src/ff.h Inc/sd_diskio.h
+Inc/fatfs.h:
+Middlewares/Third_Party/FatFs/src/ff.h:
+Middlewares/Third_Party/FatFs/src/integer.h:
+Inc/ffconf.h:
+Inc/main.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h:
+Inc/bsp_driver_sd.h:
+Inc/fatfs_platform.h:
+Middlewares/Third_Party/FatFs/src/ff_gen_drv.h:
+Middlewares/Third_Party/FatFs/src/diskio.h:
+Middlewares/Third_Party/FatFs/src/ff.h:
+Inc/sd_diskio.h:
diff --git a/build/fatfs.lst b/build/fatfs.lst
new file mode 100644
index 0000000..211ef55
--- /dev/null
+++ b/build/fatfs.lst
@@ -0,0 +1,196 @@
+ARM GAS  /tmp/ccj14z6F.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"fatfs.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.MX_FATFS_Init,"ax",%progbits
+  17              		.align	1
+  18              		.global	MX_FATFS_Init
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	MX_FATFS_Init:
+  26              	.LFB1183:
+  27              		.file 1 "Src/fatfs.c"
+   1:Src/fatfs.c   **** /* USER CODE BEGIN Header */
+   2:Src/fatfs.c   **** /**
+   3:Src/fatfs.c   ****   ******************************************************************************
+   4:Src/fatfs.c   ****   * @file   fatfs.c
+   5:Src/fatfs.c   ****   * @brief  Code for fatfs applications
+   6:Src/fatfs.c   ****   ******************************************************************************
+   7:Src/fatfs.c   ****   * @attention
+   8:Src/fatfs.c   ****   *
+   9:Src/fatfs.c   ****   * Copyright (c) 2023 STMicroelectronics.
+  10:Src/fatfs.c   ****   * All rights reserved.
+  11:Src/fatfs.c   ****   *
+  12:Src/fatfs.c   ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Src/fatfs.c   ****   * in the root directory of this software component.
+  14:Src/fatfs.c   ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Src/fatfs.c   ****   *
+  16:Src/fatfs.c   ****   ******************************************************************************
+  17:Src/fatfs.c   ****   */
+  18:Src/fatfs.c   **** /* USER CODE END Header */
+  19:Src/fatfs.c   **** #include "fatfs.h"
+  20:Src/fatfs.c   **** 
+  21:Src/fatfs.c   **** uint8_t retSD;    /* Return value for SD */
+  22:Src/fatfs.c   **** char SDPath[4];   /* SD logical drive path */
+  23:Src/fatfs.c   **** FATFS SDFatFS;    /* File system object for SD logical drive */
+  24:Src/fatfs.c   **** FIL SDFile;       /* File object for SD */
+  25:Src/fatfs.c   **** 
+  26:Src/fatfs.c   **** /* USER CODE BEGIN Variables */
+  27:Src/fatfs.c   **** 
+  28:Src/fatfs.c   **** /* USER CODE END Variables */
+  29:Src/fatfs.c   **** 
+  30:Src/fatfs.c   **** void MX_FATFS_Init(void)
+  31:Src/fatfs.c   **** {
+ARM GAS  /tmp/ccj14z6F.s 			page 2
+
+
+  28              		.loc 1 31 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32 0000 08B5     		push	{r3, lr}
+  33              	.LCFI0:
+  34              		.cfi_def_cfa_offset 8
+  35              		.cfi_offset 3, -8
+  36              		.cfi_offset 14, -4
+  32:Src/fatfs.c   ****   /*## FatFS: Link the SD driver ###########################*/
+  33:Src/fatfs.c   ****   retSD = FATFS_LinkDriver(&SD_Driver, SDPath);
+  37              		.loc 1 33 3 view .LVU1
+  38              		.loc 1 33 11 is_stmt 0 view .LVU2
+  39 0002 0349     		ldr	r1, .L3
+  40 0004 0348     		ldr	r0, .L3+4
+  41 0006 FFF7FEFF 		bl	FATFS_LinkDriver
+  42              	.LVL0:
+  43              		.loc 1 33 9 view .LVU3
+  44 000a 034B     		ldr	r3, .L3+8
+  45 000c 1870     		strb	r0, [r3]
+  34:Src/fatfs.c   **** 
+  35:Src/fatfs.c   ****   /* USER CODE BEGIN Init */
+  36:Src/fatfs.c   ****   /* additional user code for init */
+  37:Src/fatfs.c   ****   /* USER CODE END Init */
+  38:Src/fatfs.c   **** }
+  46              		.loc 1 38 1 view .LVU4
+  47 000e 08BD     		pop	{r3, pc}
+  48              	.L4:
+  49              		.align	2
+  50              	.L3:
+  51 0010 00000000 		.word	.LANCHOR0
+  52 0014 00000000 		.word	SD_Driver
+  53 0018 00000000 		.word	.LANCHOR1
+  54              		.cfi_endproc
+  55              	.LFE1183:
+  57              		.section	.text.get_fattime,"ax",%progbits
+  58              		.align	1
+  59              		.global	get_fattime
+  60              		.syntax unified
+  61              		.thumb
+  62              		.thumb_func
+  63              		.fpu fpv5-d16
+  65              	get_fattime:
+  66              	.LFB1184:
+  39:Src/fatfs.c   **** 
+  40:Src/fatfs.c   **** /**
+  41:Src/fatfs.c   ****   * @brief  Gets Time from RTC
+  42:Src/fatfs.c   ****   * @param  None
+  43:Src/fatfs.c   ****   * @retval Time in DWORD
+  44:Src/fatfs.c   ****   */
+  45:Src/fatfs.c   **** DWORD get_fattime(void)
+  46:Src/fatfs.c   **** {
+  67              		.loc 1 46 1 is_stmt 1 view -0
+  68              		.cfi_startproc
+  69              		@ args = 0, pretend = 0, frame = 0
+  70              		@ frame_needed = 0, uses_anonymous_args = 0
+  71              		@ link register save eliminated.
+ARM GAS  /tmp/ccj14z6F.s 			page 3
+
+
+  47:Src/fatfs.c   ****   /* USER CODE BEGIN get_fattime */
+  48:Src/fatfs.c   ****   return 0;
+  72              		.loc 1 48 3 view .LVU6
+  49:Src/fatfs.c   ****   /* USER CODE END get_fattime */
+  50:Src/fatfs.c   **** }
+  73              		.loc 1 50 1 is_stmt 0 view .LVU7
+  74 0000 0020     		movs	r0, #0
+  75 0002 7047     		bx	lr
+  76              		.cfi_endproc
+  77              	.LFE1184:
+  79              		.global	SDFile
+  80              		.global	SDFatFS
+  81              		.global	SDPath
+  82              		.global	retSD
+  83              		.section	.bss.SDFatFS,"aw",%nobits
+  84              		.align	2
+  87              	SDFatFS:
+  88 0000 00000000 		.space	4148
+  88      00000000 
+  88      00000000 
+  88      00000000 
+  88      00000000 
+  89              		.section	.bss.SDFile,"aw",%nobits
+  90              		.align	2
+  93              	SDFile:
+  94 0000 00000000 		.space	4144
+  94      00000000 
+  94      00000000 
+  94      00000000 
+  94      00000000 
+  95              		.section	.bss.SDPath,"aw",%nobits
+  96              		.align	2
+  97              		.set	.LANCHOR0,. + 0
+ 100              	SDPath:
+ 101 0000 00000000 		.space	4
+ 102              		.section	.bss.retSD,"aw",%nobits
+ 103              		.set	.LANCHOR1,. + 0
+ 106              	retSD:
+ 107 0000 00       		.space	1
+ 108              		.text
+ 109              	.Letext0:
+ 110              		.file 2 "Middlewares/Third_Party/FatFs/src/integer.h"
+ 111              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 112              		.file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h"
+ 113              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h"
+ 114              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+ 115              		.file 7 "Middlewares/Third_Party/FatFs/src/ff.h"
+ 116              		.file 8 "Middlewares/Third_Party/FatFs/src/diskio.h"
+ 117              		.file 9 "Middlewares/Third_Party/FatFs/src/ff_gen_drv.h"
+ 118              		.file 10 "Inc/sd_diskio.h"
+ 119              		.file 11 "Inc/fatfs.h"
+ARM GAS  /tmp/ccj14z6F.s 			page 4
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 fatfs.c
+     /tmp/ccj14z6F.s:17     .text.MX_FATFS_Init:0000000000000000 $t
+     /tmp/ccj14z6F.s:25     .text.MX_FATFS_Init:0000000000000000 MX_FATFS_Init
+     /tmp/ccj14z6F.s:51     .text.MX_FATFS_Init:0000000000000010 $d
+     /tmp/ccj14z6F.s:58     .text.get_fattime:0000000000000000 $t
+     /tmp/ccj14z6F.s:65     .text.get_fattime:0000000000000000 get_fattime
+     /tmp/ccj14z6F.s:93     .bss.SDFile:0000000000000000 SDFile
+     /tmp/ccj14z6F.s:87     .bss.SDFatFS:0000000000000000 SDFatFS
+     /tmp/ccj14z6F.s:100    .bss.SDPath:0000000000000000 SDPath
+     /tmp/ccj14z6F.s:106    .bss.retSD:0000000000000000 retSD
+     /tmp/ccj14z6F.s:84     .bss.SDFatFS:0000000000000000 $d
+     /tmp/ccj14z6F.s:90     .bss.SDFile:0000000000000000 $d
+     /tmp/ccj14z6F.s:96     .bss.SDPath:0000000000000000 $d
+     /tmp/ccj14z6F.s:107    .bss.retSD:0000000000000000 $d
+
+UNDEFINED SYMBOLS
+FATFS_LinkDriver
+SD_Driver
diff --git a/build/fatfs.o b/build/fatfs.o
new file mode 100644
index 0000000..17838c3
Binary files /dev/null and b/build/fatfs.o differ
diff --git a/build/fatfs_platform.d b/build/fatfs_platform.d
new file mode 100644
index 0000000..ad61434
--- /dev/null
+++ b/build/fatfs_platform.d
@@ -0,0 +1,64 @@
+build/fatfs_platform.o: Src/fatfs_platform.c Inc/fatfs_platform.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Inc/fatfs_platform.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/fatfs_platform.lst b/build/fatfs_platform.lst
new file mode 100644
index 0000000..67de266
--- /dev/null
+++ b/build/fatfs_platform.lst
@@ -0,0 +1,119 @@
+ARM GAS  /tmp/ccwVewTq.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"fatfs_platform.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.BSP_PlatformIsDetected,"ax",%progbits
+  17              		.align	1
+  18              		.global	BSP_PlatformIsDetected
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	BSP_PlatformIsDetected:
+  26              	.LFB141:
+  27              		.file 1 "Src/fatfs_platform.c"
+   1:Src/fatfs_platform.c **** /* USER CODE BEGIN Header */
+   2:Src/fatfs_platform.c **** /**
+   3:Src/fatfs_platform.c ****   ******************************************************************************
+   4:Src/fatfs_platform.c ****   * @file           : fatfs_platform.c
+   5:Src/fatfs_platform.c ****   * @brief          : fatfs_platform source file
+   6:Src/fatfs_platform.c ****   ******************************************************************************
+   7:Src/fatfs_platform.c ****   * @attention
+   8:Src/fatfs_platform.c ****   *
+   9:Src/fatfs_platform.c ****   * Copyright (c) 2023 STMicroelectronics.
+  10:Src/fatfs_platform.c ****   * All rights reserved.
+  11:Src/fatfs_platform.c ****   *
+  12:Src/fatfs_platform.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Src/fatfs_platform.c ****   * in the root directory of this software component.
+  14:Src/fatfs_platform.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Src/fatfs_platform.c ****   *
+  16:Src/fatfs_platform.c ****   ******************************************************************************
+  17:Src/fatfs_platform.c **** */
+  18:Src/fatfs_platform.c **** /* USER CODE END Header */
+  19:Src/fatfs_platform.c **** #include "fatfs_platform.h"
+  20:Src/fatfs_platform.c **** 
+  21:Src/fatfs_platform.c **** uint8_t	BSP_PlatformIsDetected(void) {
+  28              		.loc 1 21 38 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32 0000 08B5     		push	{r3, lr}
+  33              	.LCFI0:
+  34              		.cfi_def_cfa_offset 8
+  35              		.cfi_offset 3, -8
+  36              		.cfi_offset 14, -4
+  22:Src/fatfs_platform.c ****     uint8_t status = SD_PRESENT;
+ARM GAS  /tmp/ccwVewTq.s 			page 2
+
+
+  37              		.loc 1 22 5 view .LVU1
+  38              	.LVL0:
+  23:Src/fatfs_platform.c ****     /* Check SD card detect pin */
+  24:Src/fatfs_platform.c ****     if(HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != GPIO_PIN_RESET)
+  39              		.loc 1 24 5 view .LVU2
+  40              		.loc 1 24 8 is_stmt 0 view .LVU3
+  41 0002 0121     		movs	r1, #1
+  42 0004 0348     		ldr	r0, .L5
+  43 0006 FFF7FEFF 		bl	HAL_GPIO_ReadPin
+  44              	.LVL1:
+  45              		.loc 1 24 7 view .LVU4
+  46 000a 08B9     		cbnz	r0, .L3
+  22:Src/fatfs_platform.c ****     uint8_t status = SD_PRESENT;
+  47              		.loc 1 22 13 view .LVU5
+  48 000c 0120     		movs	r0, #1
+  49              	.L2:
+  50              	.LVL2:
+  25:Src/fatfs_platform.c ****     {
+  26:Src/fatfs_platform.c ****         status = SD_NOT_PRESENT;
+  27:Src/fatfs_platform.c ****     }
+  28:Src/fatfs_platform.c ****     /* USER CODE BEGIN 1 */
+  29:Src/fatfs_platform.c ****     /* user code can be inserted here */
+  30:Src/fatfs_platform.c ****     /* USER CODE END 1 */
+  31:Src/fatfs_platform.c ****     return status;
+  51              		.loc 1 31 5 is_stmt 1 view .LVU6
+  32:Src/fatfs_platform.c **** }
+  52              		.loc 1 32 1 is_stmt 0 view .LVU7
+  53 000e 08BD     		pop	{r3, pc}
+  54              	.LVL3:
+  55              	.L3:
+  26:Src/fatfs_platform.c ****     }
+  56              		.loc 1 26 16 view .LVU8
+  57 0010 0020     		movs	r0, #0
+  58 0012 FCE7     		b	.L2
+  59              	.L6:
+  60              		.align	2
+  61              	.L5:
+  62 0014 000C0240 		.word	1073875968
+  63              		.cfi_endproc
+  64              	.LFE141:
+  66              		.text
+  67              	.Letext0:
+  68              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+  69              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+  70              		.file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h"
+ARM GAS  /tmp/ccwVewTq.s 			page 3
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 fatfs_platform.c
+     /tmp/ccwVewTq.s:17     .text.BSP_PlatformIsDetected:0000000000000000 $t
+     /tmp/ccwVewTq.s:25     .text.BSP_PlatformIsDetected:0000000000000000 BSP_PlatformIsDetected
+     /tmp/ccwVewTq.s:62     .text.BSP_PlatformIsDetected:0000000000000014 $d
+
+UNDEFINED SYMBOLS
+HAL_GPIO_ReadPin
diff --git a/build/fatfs_platform.o b/build/fatfs_platform.o
new file mode 100644
index 0000000..0a4702d
Binary files /dev/null and b/build/fatfs_platform.o differ
diff --git a/build/ff.d b/build/ff.d
new file mode 100644
index 0000000..ebbb95d
--- /dev/null
+++ b/build/ff.d
@@ -0,0 +1,97 @@
+build/ff.o: Middlewares/Third_Party/FatFs/src/ff.c \
+ Middlewares/Third_Party/FatFs/src/ff.h \
+ Middlewares/Third_Party/FatFs/src/integer.h Inc/ffconf.h Inc/main.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/bsp_driver_sd.h \
+ Inc/fatfs_platform.h Middlewares/Third_Party/FatFs/src/diskio.h
+Middlewares/Third_Party/FatFs/src/ff.h:
+Middlewares/Third_Party/FatFs/src/integer.h:
+Inc/ffconf.h:
+Inc/main.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h:
+Inc/bsp_driver_sd.h:
+Inc/fatfs_platform.h:
+Middlewares/Third_Party/FatFs/src/diskio.h:
diff --git a/build/ff.lst b/build/ff.lst
new file mode 100644
index 0000000..5c81ddb
--- /dev/null
+++ b/build/ff.lst
@@ -0,0 +1,22715 @@
+ARM GAS  /tmp/cc5lWXRL.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"ff.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.ld_word,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	ld_word:
+  25              	.LVL0:
+  26              	.LFB1183:
+  27              		.file 1 "Middlewares/Third_Party/FatFs/src/ff.c"
+   1:Middlewares/Third_Party/FatFs/src/ff.c **** /*----------------------------------------------------------------------------/
+   2:Middlewares/Third_Party/FatFs/src/ff.c **** /  FatFs - Generic FAT file system module  R0.12c                             /
+   3:Middlewares/Third_Party/FatFs/src/ff.c **** /-----------------------------------------------------------------------------/
+   4:Middlewares/Third_Party/FatFs/src/ff.c **** /
+   5:Middlewares/Third_Party/FatFs/src/ff.c **** / Copyright (C) 2017, ChaN, all right reserved.
+   6:Middlewares/Third_Party/FatFs/src/ff.c **** /
+   7:Middlewares/Third_Party/FatFs/src/ff.c **** / FatFs module is an open source software. Redistribution and use of FatFs in
+   8:Middlewares/Third_Party/FatFs/src/ff.c **** / source and binary forms, with or without modification, are permitted provided
+   9:Middlewares/Third_Party/FatFs/src/ff.c **** / that the following condition is met:
+  10:Middlewares/Third_Party/FatFs/src/ff.c **** /
+  11:Middlewares/Third_Party/FatFs/src/ff.c **** / 1. Redistributions of source code must retain the above copyright notice,
+  12:Middlewares/Third_Party/FatFs/src/ff.c **** /    this condition and the following disclaimer.
+  13:Middlewares/Third_Party/FatFs/src/ff.c **** /
+  14:Middlewares/Third_Party/FatFs/src/ff.c **** / This software is provided by the copyright holder and contributors "AS IS"
+  15:Middlewares/Third_Party/FatFs/src/ff.c **** / and any warranties related to this software are DISCLAIMED.
+  16:Middlewares/Third_Party/FatFs/src/ff.c **** / The copyright owner or contributors be NOT LIABLE for any damages caused
+  17:Middlewares/Third_Party/FatFs/src/ff.c **** / by use of this software.
+  18:Middlewares/Third_Party/FatFs/src/ff.c **** /----------------------------------------------------------------------------*/
+  19:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  20:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  21:Middlewares/Third_Party/FatFs/src/ff.c **** #include "ff.h"			/* Declarations of FatFs API */
+  22:Middlewares/Third_Party/FatFs/src/ff.c **** #include "diskio.h"		/* Declarations of device I/O functions */
+  23:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  24:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  25:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------------------------------------------
+  26:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  27:Middlewares/Third_Party/FatFs/src/ff.c ****    Module Private Definitions
+  28:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  29:Middlewares/Third_Party/FatFs/src/ff.c **** ---------------------------------------------------------------------------*/
+  30:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  31:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FATFS != 68300	/* Revision ID */
+ARM GAS  /tmp/cc5lWXRL.s 			page 2
+
+
+  32:Middlewares/Third_Party/FatFs/src/ff.c **** #error Wrong include file (ff.h).
+  33:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+  34:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  35:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  36:Middlewares/Third_Party/FatFs/src/ff.c **** /* DBCS code ranges and SBCS upper conversion tables */
+  37:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  38:Middlewares/Third_Party/FatFs/src/ff.c **** #if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+  39:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0x81	/* DBC 1st byte range 1 start */
+  40:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+  41:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+  42:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+  43:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+  44:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+  45:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+  46:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+  47:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  48:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+  49:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0x81
+  50:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1E	0xFE
+  51:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1S	0x40
+  52:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1E	0x7E
+  53:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2S	0x80
+  54:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2E	0xFE
+  55:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  56:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 949	/* Korean */
+  57:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0x81
+  58:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1E	0xFE
+  59:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1S	0x41
+  60:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1E	0x5A
+  61:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2S	0x61
+  62:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2E	0x7A
+  63:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS3S	0x81
+  64:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS3E	0xFE
+  65:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  66:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+  67:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0x81
+  68:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1E	0xFE
+  69:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1S	0x40
+  70:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1E	0x7E
+  71:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2S	0xA1
+  72:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2E	0xFE
+  73:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  74:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 437	/* U.S. */
+  75:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+  76:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+  77:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+  78:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+  79:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+  80:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+  81:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+  82:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+  83:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+  84:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  85:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 720	/* Arabic */
+  86:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+  87:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+  88:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ARM GAS  /tmp/cc5lWXRL.s 			page 3
+
+
+  89:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+  90:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+  91:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+  92:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+  93:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+  94:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+  95:Middlewares/Third_Party/FatFs/src/ff.c **** 
+  96:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 737	/* Greek */
+  97:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+  98:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+  99:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+ 100:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \
+ 101:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 102:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 103:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 104:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 105:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+ 106:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 107:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 771	/* KBL */
+ 108:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 109:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 110:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 111:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 112:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 113:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 114:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \
+ 115:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 116:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF}
+ 117:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 118:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 775	/* Baltic */
+ 119:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 120:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \
+ 121:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 122:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 123:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 124:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 125:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 126:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \
+ 127:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+ 128:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 129:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 850	/* Latin 1 */
+ 130:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 131:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \
+ 132:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \
+ 133:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 134:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 135:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 136:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \
+ 137:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \
+ 138:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+ 139:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 140:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 852	/* Latin 2 */
+ 141:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 142:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \
+ 143:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \
+ 144:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \
+ 145:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+ARM GAS  /tmp/cc5lWXRL.s 			page 4
+
+
+ 146:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 147:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 148:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \
+ 149:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+ 150:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 151:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 855	/* Cyrillic */
+ 152:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 153:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \
+ 154:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+ 155:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \
+ 156:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+ 157:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 158:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+ 159:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \
+ 160:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+ 161:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 162:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 857	/* Turkish */
+ 163:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 164:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \
+ 165:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+ 166:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 167:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 168:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 169:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 170:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \
+ 171:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+ 172:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 173:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 860	/* Portuguese */
+ 174:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 175:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \
+ 176:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 177:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 178:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 179:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 180:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 181:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 182:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+ 183:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 184:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 861	/* Icelandic */
+ 185:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 186:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \
+ 187:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 188:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 189:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 190:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 191:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 192:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 193:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+ 194:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 195:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 862	/* Hebrew */
+ 196:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 197:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 198:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 199:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 200:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 201:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 202:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ARM GAS  /tmp/cc5lWXRL.s 			page 5
+
+
+ 203:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 204:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+ 205:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 206:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 863	/* Canadian-French */
+ 207:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 208:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \
+ 209:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \
+ 210:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 211:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 212:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 213:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 214:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 215:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+ 216:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 217:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 864	/* Arabic */
+ 218:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 219:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+ 220:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 221:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 222:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 223:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 224:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 225:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 226:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+ 227:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 228:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 865	/* Nordic */
+ 229:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 230:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+ 231:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 232:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 233:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 234:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 235:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 236:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 237:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+ 238:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 239:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 866	/* Russian */
+ 240:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 241:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 242:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 243:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 244:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 245:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 246:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 247:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 248:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+ 249:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 250:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 869	/* Greek 2 */
+ 251:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 252:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 253:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \
+ 254:Middlewares/Third_Party/FatFs/src/ff.c **** 				0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 255:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 256:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 257:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \
+ 258:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \
+ 259:Middlewares/Third_Party/FatFs/src/ff.c **** 				0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF}
+ARM GAS  /tmp/cc5lWXRL.s 			page 6
+
+
+ 260:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 261:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+ 262:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+ 263:Middlewares/Third_Party/FatFs/src/ff.c **** #error Cannot enable LFN without valid code page.
+ 264:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 265:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S	0
+ 266:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 267:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 268:Middlewares/Third_Party/FatFs/src/ff.c **** #error Unknown code page
+ 269:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 270:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 271:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 272:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 273:Middlewares/Third_Party/FatFs/src/ff.c **** /* Character code support macros */
+ 274:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+ 275:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsLower(c)	(((c)>='a')&&((c)<='z'))
+ 276:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDigit(c)	(((c)>='0')&&((c)<='9'))
+ 277:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 278:Middlewares/Third_Party/FatFs/src/ff.c **** #if _DF1S != 0	/* Code page is DBCS */
+ 279:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 280:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _DF2S	/* Two 1st byte areas */
+ 281:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) 
+ 282:Middlewares/Third_Party/FatFs/src/ff.c **** #else			/* One 1st byte area */
+ 283:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+ 284:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 285:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 286:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _DS3S	/* Three 2nd byte areas */
+ 287:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) 
+ 288:Middlewares/Third_Party/FatFs/src/ff.c **** #else			/* Two 2nd byte areas */
+ 289:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) 
+ 290:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 291:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 292:Middlewares/Third_Party/FatFs/src/ff.c **** #else			/* Code page is SBCS */
+ 293:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 294:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS1(c)	0
+ 295:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS2(c)	0
+ 296:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 297:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _DF1S */
+ 298:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 299:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 300:Middlewares/Third_Party/FatFs/src/ff.c **** /* Additional file attribute bits for internal use */
+ 301:Middlewares/Third_Party/FatFs/src/ff.c **** #define	AM_VOL		0x08	/* Volume label */
+ 302:Middlewares/Third_Party/FatFs/src/ff.c **** #define AM_LFN		0x0F	/* LFN entry */
+ 303:Middlewares/Third_Party/FatFs/src/ff.c **** #define AM_MASK		0x3F	/* Mask of defined bits */
+ 304:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 305:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 306:Middlewares/Third_Party/FatFs/src/ff.c **** /* Additional file access control and file status flags for internal use */
+ 307:Middlewares/Third_Party/FatFs/src/ff.c **** #define FA_SEEKEND	0x20	/* Seek to end of the file on file open */
+ 308:Middlewares/Third_Party/FatFs/src/ff.c **** #define FA_MODIFIED	0x40	/* File has been modified */
+ 309:Middlewares/Third_Party/FatFs/src/ff.c **** #define FA_DIRTY	0x80	/* FIL.buf[] needs to be written-back */
+ 310:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 311:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 312:Middlewares/Third_Party/FatFs/src/ff.c **** /* Name status flags in fn[] */
+ 313:Middlewares/Third_Party/FatFs/src/ff.c **** #define NSFLAG		11		/* Index of the name status byte */
+ 314:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_LOSS		0x01	/* Out of 8.3 format */
+ 315:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_LFN		0x02	/* Force to create LFN entry */
+ 316:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_LAST		0x04	/* Last segment */
+ARM GAS  /tmp/cc5lWXRL.s 			page 7
+
+
+ 317:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_BODY		0x08	/* Lower case flag (body) */
+ 318:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_EXT		0x10	/* Lower case flag (ext) */
+ 319:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_DOT		0x20	/* Dot entry */
+ 320:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_NOLFN	0x40	/* Do not find LFN */
+ 321:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_NONAME	0x80	/* Not followed */
+ 322:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 323:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 324:Middlewares/Third_Party/FatFs/src/ff.c **** /* Limits and boundaries */
+ 325:Middlewares/Third_Party/FatFs/src/ff.c **** #define MAX_DIR		0x200000		/* Max size of FAT directory */
+ 326:Middlewares/Third_Party/FatFs/src/ff.c **** #define MAX_DIR_EX	0x10000000		/* Max size of exFAT directory */
+ 327:Middlewares/Third_Party/FatFs/src/ff.c **** #define MAX_FAT12	0xFF5			/* Max FAT12 clusters (differs from specs, but correct for real DOS/Windo
+ 328:Middlewares/Third_Party/FatFs/src/ff.c **** #define	MAX_FAT16	0xFFF5			/* Max FAT16 clusters (differs from specs, but correct for real DOS/Wind
+ 329:Middlewares/Third_Party/FatFs/src/ff.c **** #define	MAX_FAT32	0x0FFFFFF5		/* Max FAT32 clusters (not specified, practical limit) */
+ 330:Middlewares/Third_Party/FatFs/src/ff.c **** #define	MAX_EXFAT	0x7FFFFFFD		/* Max exFAT clusters (differs from specs, implementation limit) */
+ 331:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 332:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 333:Middlewares/Third_Party/FatFs/src/ff.c **** /* FatFs refers the FAT structure as simple byte array instead of structure member
+ 334:Middlewares/Third_Party/FatFs/src/ff.c **** / because the C structure is not binary compatible between different platforms */
+ 335:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 336:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_JmpBoot			0		/* x86 jump instruction (3-byte) */
+ 337:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_OEMName			3		/* OEM name (8-byte) */
+ 338:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_BytsPerSec		11		/* Sector size [byte] (WORD) */
+ 339:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_SecPerClus		13		/* Cluster size [sector] (BYTE) */
+ 340:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_RsvdSecCnt		14		/* Size of reserved area [sector] (WORD) */
+ 341:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_NumFATs			16		/* Number of FATs (BYTE) */
+ 342:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_RootEntCnt		17		/* Size of root directory area for FAT12/16 [entry] (WORD) */
+ 343:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_TotSec16		19		/* Volume size (16-bit) [sector] (WORD) */
+ 344:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_Media			21		/* Media descriptor byte (BYTE) */
+ 345:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FATSz16			22		/* FAT size (16-bit) [sector] (WORD) */
+ 346:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_SecPerTrk		24		/* Track size for int13h [sector] (WORD) */
+ 347:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_NumHeads		26		/* Number of heads for int13h (WORD) */
+ 348:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_HiddSec			28		/* Volume offset from top of the drive (DWORD) */
+ 349:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_TotSec32		32		/* Volume size (32-bit) [sector] (DWORD) */
+ 350:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_DrvNum			36		/* Physical drive number for int13h (BYTE) */
+ 351:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_NTres			37		/* Error flag (BYTE) */
+ 352:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_BootSig			38		/* Extended boot signature (BYTE) */
+ 353:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_VolID			39		/* Volume serial number (DWORD) */
+ 354:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_VolLab			43		/* Volume label string (8-byte) */
+ 355:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_FilSysType		54		/* File system type string (8-byte) */
+ 356:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_BootCode			62		/* Boot code (448-byte) */
+ 357:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_55AA				510		/* Signature word (WORD) */
+ 358:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 359:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FATSz32			36		/* FAT32: FAT size [sector] (DWORD) */
+ 360:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_ExtFlags32		40		/* FAT32: Extended flags (WORD) */
+ 361:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FSVer32			42		/* FAT32: File system version (WORD) */
+ 362:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_RootClus32		44		/* FAT32: Root directory cluster (DWORD) */
+ 363:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FSInfo32		48		/* FAT32: Offset of FSINFO sector (WORD) */
+ 364:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_BkBootSec32		50		/* FAT32: Offset of backup boot sector (WORD) */
+ 365:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_DrvNum32			64		/* FAT32: Physical drive number for int13h (BYTE) */
+ 366:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_NTres32			65		/* FAT32: Error flag (BYTE) */
+ 367:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_BootSig32		66		/* FAT32: Extended boot signature (BYTE) */
+ 368:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_VolID32			67		/* FAT32: Volume serial number (DWORD) */
+ 369:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_VolLab32			71		/* FAT32: Volume label string (8-byte) */
+ 370:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_FilSysType32		82		/* FAT32: File system type string (8-byte) */
+ 371:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_BootCode32		90		/* FAT32: Boot code (420-byte) */
+ 372:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 373:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_ZeroedEx		11		/* exFAT: MBZ field (53-byte) */
+ARM GAS  /tmp/cc5lWXRL.s 			page 8
+
+
+ 374:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_VolOfsEx		64		/* exFAT: Volume offset from top of the drive [sector] (QWORD) */
+ 375:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_TotSecEx		72		/* exFAT: Volume size [sector] (QWORD) */
+ 376:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FatOfsEx		80		/* exFAT: FAT offset from top of the volume [sector] (DWORD) */
+ 377:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FatSzEx			84		/* exFAT: FAT size [sector] (DWORD) */
+ 378:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_DataOfsEx		88		/* exFAT: Data offset from top of the volume [sector] (DWORD) */
+ 379:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_NumClusEx		92		/* exFAT: Number of clusters (DWORD) */
+ 380:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_RootClusEx		96		/* exFAT: Root directory start cluster (DWORD) */
+ 381:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_VolIDEx			100		/* exFAT: Volume serial number (DWORD) */
+ 382:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FSVerEx			104		/* exFAT: File system version (WORD) */
+ 383:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_VolFlagEx		106		/* exFAT: Volume flags (BYTE) */
+ 384:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_ActFatEx		107		/* exFAT: Active FAT flags (BYTE) */
+ 385:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_BytsPerSecEx	108		/* exFAT: Log2 of sector size in unit of byte (BYTE) */
+ 386:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_SecPerClusEx	109		/* exFAT: Log2 of cluster size in unit of sector (BYTE) */
+ 387:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_NumFATsEx		110		/* exFAT: Number of FATs (BYTE) */
+ 388:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_DrvNumEx		111		/* exFAT: Physical drive number for int13h (BYTE) */
+ 389:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_PercInUseEx		112		/* exFAT: Percent in use (BYTE) */
+ 390:Middlewares/Third_Party/FatFs/src/ff.c **** #define	BPB_RsvdEx			113		/* exFAT: Reserved (7-byte) */
+ 391:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_BootCodeEx		120		/* exFAT: Boot code (390-byte) */
+ 392:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 393:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DIR_Name			0		/* Short file name (11-byte) */
+ 394:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DIR_Attr			11		/* Attribute (BYTE) */
+ 395:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DIR_NTres			12		/* Lower case flag (BYTE) */
+ 396:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_CrtTime10		13		/* Created time sub-second (BYTE) */
+ 397:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DIR_CrtTime			14		/* Created time (DWORD) */
+ 398:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_LstAccDate		18		/* Last accessed date (WORD) */
+ 399:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DIR_FstClusHI		20		/* Higher 16-bit of first cluster (WORD) */
+ 400:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DIR_ModTime			22		/* Modified time (DWORD) */
+ 401:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DIR_FstClusLO		26		/* Lower 16-bit of first cluster (WORD) */
+ 402:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DIR_FileSize		28		/* File size (DWORD) */
+ 403:Middlewares/Third_Party/FatFs/src/ff.c **** #define	LDIR_Ord			0		/* LFN: LFN order and LLE flag (BYTE) */
+ 404:Middlewares/Third_Party/FatFs/src/ff.c **** #define	LDIR_Attr			11		/* LFN: LFN attribute (BYTE) */
+ 405:Middlewares/Third_Party/FatFs/src/ff.c **** #define	LDIR_Type			12		/* LFN: Entry type (BYTE) */
+ 406:Middlewares/Third_Party/FatFs/src/ff.c **** #define	LDIR_Chksum			13		/* LFN: Checksum of the SFN (BYTE) */
+ 407:Middlewares/Third_Party/FatFs/src/ff.c **** #define	LDIR_FstClusLO		26		/* LFN: MBZ field (WORD) */
+ 408:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_Type			0		/* exFAT: Type of exFAT directory entry (BYTE) */
+ 409:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_NumLabel		1		/* exFAT: Number of volume label characters (BYTE) */
+ 410:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_Label			2		/* exFAT: Volume label (11-WORD) */
+ 411:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_CaseSum		4		/* exFAT: Sum of case conversion table (DWORD) */
+ 412:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_NumSec			1		/* exFAT: Number of secondary entries (BYTE) */
+ 413:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_SetSum			2		/* exFAT: Sum of the set of directory entries (WORD) */
+ 414:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_Attr			4		/* exFAT: File attribute (WORD) */
+ 415:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_CrtTime		8		/* exFAT: Created time (DWORD) */
+ 416:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_ModTime		12		/* exFAT: Modified time (DWORD) */
+ 417:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_AccTime		16		/* exFAT: Last accessed time (DWORD) */
+ 418:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_CrtTime10		20		/* exFAT: Created time subsecond (BYTE) */
+ 419:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_ModTime10		21		/* exFAT: Modified time subsecond (BYTE) */
+ 420:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_CrtTZ			22		/* exFAT: Created timezone (BYTE) */
+ 421:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_ModTZ			23		/* exFAT: Modified timezone (BYTE) */
+ 422:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_AccTZ			24		/* exFAT: Last accessed timezone (BYTE) */
+ 423:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_GenFlags		33		/* exFAT: General secondary flags (WORD) */
+ 424:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_NumName		35		/* exFAT: Number of file name characters (BYTE) */
+ 425:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_NameHash		36		/* exFAT: Hash of file name (WORD) */
+ 426:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_ValidFileSize	40		/* exFAT: Valid file size (QWORD) */
+ 427:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_FstClus		52		/* exFAT: First cluster of the file data (DWORD) */
+ 428:Middlewares/Third_Party/FatFs/src/ff.c **** #define	XDIR_FileSize		56		/* exFAT: File/Directory size (QWORD) */
+ 429:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 430:Middlewares/Third_Party/FatFs/src/ff.c **** #define	SZDIRE				32		/* Size of a directory entry */
+ARM GAS  /tmp/cc5lWXRL.s 			page 9
+
+
+ 431:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DDEM				0xE5	/* Deleted directory entry mark set to DIR_Name[0] */
+ 432:Middlewares/Third_Party/FatFs/src/ff.c **** #define	RDDEM				0x05	/* Replacement of the character collides with DDEM */
+ 433:Middlewares/Third_Party/FatFs/src/ff.c **** #define	LLEF				0x40	/* Last long entry flag in LDIR_Ord */
+ 434:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 435:Middlewares/Third_Party/FatFs/src/ff.c **** #define	FSI_LeadSig			0		/* FAT32 FSI: Leading signature (DWORD) */
+ 436:Middlewares/Third_Party/FatFs/src/ff.c **** #define	FSI_StrucSig		484		/* FAT32 FSI: Structure signature (DWORD) */
+ 437:Middlewares/Third_Party/FatFs/src/ff.c **** #define	FSI_Free_Count		488		/* FAT32 FSI: Number of free clusters (DWORD) */
+ 438:Middlewares/Third_Party/FatFs/src/ff.c **** #define	FSI_Nxt_Free		492		/* FAT32 FSI: Last allocated cluster (DWORD) */
+ 439:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 440:Middlewares/Third_Party/FatFs/src/ff.c **** #define MBR_Table			446		/* MBR: Offset of partition table in the MBR */
+ 441:Middlewares/Third_Party/FatFs/src/ff.c **** #define	SZ_PTE				16		/* MBR: Size of a partition table entry */
+ 442:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_Boot			0		/* MBR PTE: Boot indicator */
+ 443:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_StHead			1		/* MBR PTE: Start head */
+ 444:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_StSec			2		/* MBR PTE: Start sector */
+ 445:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_StCyl			3		/* MBR PTE: Start cylinder */
+ 446:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_System			4		/* MBR PTE: System ID */
+ 447:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_EdHead			5		/* MBR PTE: End head */
+ 448:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_EdSec			6		/* MBR PTE: End sector */
+ 449:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_EdCyl			7		/* MBR PTE: End cylinder */
+ 450:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_StLba			8		/* MBR PTE: Start in LBA */
+ 451:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_SizLba			12		/* MBR PTE: Size in LBA */
+ 452:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 453:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 454:Middlewares/Third_Party/FatFs/src/ff.c **** /* Post process after fatal error on file operation */
+ 455:Middlewares/Third_Party/FatFs/src/ff.c **** #define	ABORT(fs, res)		{ fp->err = (BYTE)(res); LEAVE_FF(fs, res); }
+ 456:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 457:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 458:Middlewares/Third_Party/FatFs/src/ff.c **** /* Reentrancy related */
+ 459:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+ 460:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1
+ 461:Middlewares/Third_Party/FatFs/src/ff.c **** #error Static LFN work area cannot be used at thread-safe configuration
+ 462:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 463:Middlewares/Third_Party/FatFs/src/ff.c **** #define	ENTER_FF(fs)		{ if (!lock_fs(fs)) return FR_TIMEOUT; }
+ 464:Middlewares/Third_Party/FatFs/src/ff.c **** #define	LEAVE_FF(fs, res)	{ unlock_fs(fs, res); return res; }
+ 465:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 466:Middlewares/Third_Party/FatFs/src/ff.c **** #define	ENTER_FF(fs)
+ 467:Middlewares/Third_Party/FatFs/src/ff.c **** #define LEAVE_FF(fs, res)	return res
+ 468:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 469:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 470:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 471:Middlewares/Third_Party/FatFs/src/ff.c **** /* Definitions of volume - partition conversion */
+ 472:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MULTI_PARTITION
+ 473:Middlewares/Third_Party/FatFs/src/ff.c **** #define LD2PD(vol) VolToPart[vol].pd	/* Get physical drive number */
+ 474:Middlewares/Third_Party/FatFs/src/ff.c **** #define LD2PT(vol) VolToPart[vol].pt	/* Get partition index */
+ 475:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 476:Middlewares/Third_Party/FatFs/src/ff.c **** #define LD2PD(vol) (BYTE)(vol)	/* Each logical drive is bound to the same physical drive number */
+ 477:Middlewares/Third_Party/FatFs/src/ff.c **** #define LD2PT(vol) 0			/* Find first valid partition or in SFD */
+ 478:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 479:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 480:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 481:Middlewares/Third_Party/FatFs/src/ff.c **** /* Definitions of sector size */
+ 482:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096
+ 483:Middlewares/Third_Party/FatFs/src/ff.c **** #error Wrong sector size configuration
+ 484:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 485:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS == _MIN_SS
+ 486:Middlewares/Third_Party/FatFs/src/ff.c **** #define	SS(fs)	((UINT)_MAX_SS)	/* Fixed sector size */
+ 487:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ARM GAS  /tmp/cc5lWXRL.s 			page 10
+
+
+ 488:Middlewares/Third_Party/FatFs/src/ff.c **** #define	SS(fs)	((fs)->ssize)	/* Variable sector size */
+ 489:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 490:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 491:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 492:Middlewares/Third_Party/FatFs/src/ff.c **** /* Timestamp */
+ 493:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_NORTC == 1
+ 494:Middlewares/Third_Party/FatFs/src/ff.c **** #if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < 
+ 495:Middlewares/Third_Party/FatFs/src/ff.c **** #error Invalid _FS_NORTC settings
+ 496:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 497:Middlewares/Third_Party/FatFs/src/ff.c **** #define GET_FATTIME()	((DWORD)(_NORTC_YEAR - 1980) << 25 | (DWORD)_NORTC_MON << 21 | (DWORD)_NORTC_
+ 498:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 499:Middlewares/Third_Party/FatFs/src/ff.c **** #define GET_FATTIME()	get_fattime()
+ 500:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 501:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 502:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 503:Middlewares/Third_Party/FatFs/src/ff.c **** /* File lock controls */
+ 504:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 505:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_READONLY
+ 506:Middlewares/Third_Party/FatFs/src/ff.c **** #error _FS_LOCK must be 0 at read-only configuration
+ 507:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 508:Middlewares/Third_Party/FatFs/src/ff.c **** typedef struct {
+ 509:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;		/* Object ID 1, volume (NULL:blank entry) */
+ 510:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clu;		/* Object ID 2, containing directory (0:root) */
+ 511:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD ofs;		/* Object ID 3, offset in the directory */
+ 512:Middlewares/Third_Party/FatFs/src/ff.c **** 	WORD ctr;		/* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */
+ 513:Middlewares/Third_Party/FatFs/src/ff.c **** } FILESEM;
+ 514:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 515:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 516:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 517:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 518:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 519:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 520:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------------------------------------------
+ 521:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 522:Middlewares/Third_Party/FatFs/src/ff.c ****    Module Private Work Area
+ 523:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 524:Middlewares/Third_Party/FatFs/src/ff.c **** ---------------------------------------------------------------------------*/
+ 525:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 526:Middlewares/Third_Party/FatFs/src/ff.c **** /* Remark: Variables defined here without initial value shall be guaranteed
+ 527:Middlewares/Third_Party/FatFs/src/ff.c **** /  zero/null at start-up. If not, the linker option or start-up routine is
+ 528:Middlewares/Third_Party/FatFs/src/ff.c **** /  not compliance with C standard. */
+ 529:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 530:Middlewares/Third_Party/FatFs/src/ff.c **** #if _VOLUMES < 1 || _VOLUMES > 10
+ 531:Middlewares/Third_Party/FatFs/src/ff.c **** #error Wrong _VOLUMES setting
+ 532:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 533:Middlewares/Third_Party/FatFs/src/ff.c **** static FATFS *FatFs[_VOLUMES];	/* Pointer to the file system objects (logical drives) */
+ 534:Middlewares/Third_Party/FatFs/src/ff.c **** static WORD Fsid;				/* File system mount ID */
+ 535:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 536:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 && _VOLUMES >= 2
+ 537:Middlewares/Third_Party/FatFs/src/ff.c **** static BYTE CurrVol;			/* Current drive */
+ 538:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 539:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 540:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 541:Middlewares/Third_Party/FatFs/src/ff.c **** static FILESEM Files[_FS_LOCK];	/* Open object lock semaphores */
+ 542:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 543:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 544:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 0		/* Non-LFN configuration */
+ARM GAS  /tmp/cc5lWXRL.s 			page 11
+
+
+ 545:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DEF_NAMBUF
+ 546:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs)
+ 547:Middlewares/Third_Party/FatFs/src/ff.c **** #define	FREE_NAMBUF()
+ 548:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 549:Middlewares/Third_Party/FatFs/src/ff.c **** #else					/* LFN configuration */
+ 550:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_LFN < 12 || _MAX_LFN > 255
+ 551:Middlewares/Third_Party/FatFs/src/ff.c **** #error Wrong _MAX_LFN value
+ 552:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 553:Middlewares/Third_Party/FatFs/src/ff.c **** #define MAXDIRB(nc)	((nc + 44U) / 15 * SZDIRE)
+ 554:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 555:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1		/* LFN enabled with static working buffer */
+ 556:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 557:Middlewares/Third_Party/FatFs/src/ff.c **** static BYTE	DirBuf[MAXDIRB(_MAX_LFN)];	/* Directory entry block scratchpad buffer */
+ 558:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 559:Middlewares/Third_Party/FatFs/src/ff.c **** static WCHAR LfnBuf[_MAX_LFN + 1];	/* LFN enabled with static working buffer */
+ 560:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DEF_NAMBUF
+ 561:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs)
+ 562:Middlewares/Third_Party/FatFs/src/ff.c **** #define	FREE_NAMBUF()
+ 563:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 564:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _USE_LFN == 2 	/* LFN enabled with dynamic working buffer on the stack */
+ 565:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 566:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DEF_NAMBUF		WCHAR lbuf[_MAX_LFN+1]; BYTE dbuf[MAXDIRB(_MAX_LFN)];
+ 567:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; }
+ 568:Middlewares/Third_Party/FatFs/src/ff.c **** #define	FREE_NAMBUF()
+ 569:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 570:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DEF_NAMBUF		WCHAR lbuf[_MAX_LFN+1];
+ 571:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; }
+ 572:Middlewares/Third_Party/FatFs/src/ff.c **** #define	FREE_NAMBUF()
+ 573:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 574:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 575:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _USE_LFN == 3 	/* LFN enabled with dynamic working buffer on the heap */
+ 576:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 577:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DEF_NAMBUF		WCHAR *lfn;
+ 578:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((_MAX_LFN+1)*2 + MAXDIRB(_MAX_LFN)); if (!lfn) LEAVE_FF
+ 579:Middlewares/Third_Party/FatFs/src/ff.c **** #define	FREE_NAMBUF()	ff_memfree(lfn)
+ 580:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 581:Middlewares/Third_Party/FatFs/src/ff.c **** #define	DEF_NAMBUF		WCHAR *lfn;
+ 582:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_C
+ 583:Middlewares/Third_Party/FatFs/src/ff.c **** #define	FREE_NAMBUF()	ff_memfree(lfn)
+ 584:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 585:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 586:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 587:Middlewares/Third_Party/FatFs/src/ff.c **** #error Wrong _USE_LFN setting
+ 588:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 589:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 590:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* else _USE_LFN == 0 */
+ 591:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 592:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT
+ 593:Middlewares/Third_Party/FatFs/src/ff.c **** static const BYTE ExCvt[] = _EXCVT;	/* Upper conversion table for SBCS extended characters */
+ 594:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 595:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 596:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 597:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 598:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 599:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 600:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 601:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------------------------------------------
+ARM GAS  /tmp/cc5lWXRL.s 			page 12
+
+
+ 602:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 603:Middlewares/Third_Party/FatFs/src/ff.c ****    Module Private Functions
+ 604:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 605:Middlewares/Third_Party/FatFs/src/ff.c **** ---------------------------------------------------------------------------*/
+ 606:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 607:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 608:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 609:Middlewares/Third_Party/FatFs/src/ff.c **** /* Load/Store multi-byte word in the FAT structure                       */
+ 610:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 611:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 612:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 613:Middlewares/Third_Party/FatFs/src/ff.c **** WORD ld_word (const BYTE* ptr)	/*	 Load a 2-byte little-endian word */
+ 614:Middlewares/Third_Party/FatFs/src/ff.c **** {
+  28              		.loc 1 614 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+ 615:Middlewares/Third_Party/FatFs/src/ff.c **** 	WORD rv;
+  33              		.loc 1 615 2 view .LVU1
+ 616:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 617:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = ptr[1];
+  34              		.loc 1 617 2 view .LVU2
+  35              		.loc 1 617 10 is_stmt 0 view .LVU3
+  36 0000 4278     		ldrb	r2, [r0, #1]	@ zero_extendqisi2
+  37              	.LVL1:
+ 618:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = rv << 8 | ptr[0];
+  38              		.loc 1 618 2 is_stmt 1 view .LVU4
+  39              		.loc 1 618 20 is_stmt 0 view .LVU5
+  40 0002 0078     		ldrb	r0, [r0]	@ zero_extendqisi2
+  41              	.LVL2:
+ 619:Middlewares/Third_Party/FatFs/src/ff.c **** 	return rv;
+  42              		.loc 1 619 2 is_stmt 1 view .LVU6
+ 620:Middlewares/Third_Party/FatFs/src/ff.c **** }
+  43              		.loc 1 620 1 is_stmt 0 view .LVU7
+  44 0004 40EA0220 		orr	r0, r0, r2, lsl #8
+  45              	.LVL3:
+  46              		.loc 1 620 1 view .LVU8
+  47 0008 7047     		bx	lr
+  48              		.cfi_endproc
+  49              	.LFE1183:
+  51              		.section	.text.ld_dword,"ax",%progbits
+  52              		.align	1
+  53              		.syntax unified
+  54              		.thumb
+  55              		.thumb_func
+  56              		.fpu fpv5-d16
+  58              	ld_dword:
+  59              	.LVL4:
+  60              	.LFB1184:
+ 621:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 622:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 623:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ld_dword (const BYTE* ptr)	/* Load a 4-byte little-endian word */
+ 624:Middlewares/Third_Party/FatFs/src/ff.c **** {
+  61              		.loc 1 624 1 is_stmt 1 view -0
+  62              		.cfi_startproc
+  63              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/cc5lWXRL.s 			page 13
+
+
+  64              		@ frame_needed = 0, uses_anonymous_args = 0
+  65              		@ link register save eliminated.
+ 625:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD rv;
+  66              		.loc 1 625 2 view .LVU10
+ 626:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 627:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = ptr[3];
+  67              		.loc 1 627 2 view .LVU11
+  68              		.loc 1 627 10 is_stmt 0 view .LVU12
+  69 0000 C278     		ldrb	r2, [r0, #3]	@ zero_extendqisi2
+  70              	.LVL5:
+ 628:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = rv << 8 | ptr[2];
+  71              		.loc 1 628 2 is_stmt 1 view .LVU13
+  72              		.loc 1 628 20 is_stmt 0 view .LVU14
+  73 0002 8378     		ldrb	r3, [r0, #2]	@ zero_extendqisi2
+  74              		.loc 1 628 5 view .LVU15
+  75 0004 43EA0222 		orr	r2, r3, r2, lsl #8
+  76              	.LVL6:
+ 629:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = rv << 8 | ptr[1];
+  77              		.loc 1 629 2 is_stmt 1 view .LVU16
+  78              		.loc 1 629 20 is_stmt 0 view .LVU17
+  79 0008 4378     		ldrb	r3, [r0, #1]	@ zero_extendqisi2
+  80              		.loc 1 629 5 view .LVU18
+  81 000a 43EA0223 		orr	r3, r3, r2, lsl #8
+  82              	.LVL7:
+ 630:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = rv << 8 | ptr[0];
+  83              		.loc 1 630 2 is_stmt 1 view .LVU19
+  84              		.loc 1 630 20 is_stmt 0 view .LVU20
+  85 000e 0078     		ldrb	r0, [r0]	@ zero_extendqisi2
+  86              	.LVL8:
+ 631:Middlewares/Third_Party/FatFs/src/ff.c **** 	return rv;
+  87              		.loc 1 631 2 is_stmt 1 view .LVU21
+ 632:Middlewares/Third_Party/FatFs/src/ff.c **** }
+  88              		.loc 1 632 1 is_stmt 0 view .LVU22
+  89 0010 40EA0320 		orr	r0, r0, r3, lsl #8
+  90              	.LVL9:
+  91              		.loc 1 632 1 view .LVU23
+  92 0014 7047     		bx	lr
+  93              		.cfi_endproc
+  94              	.LFE1184:
+  96              		.section	.text.st_word,"ax",%progbits
+  97              		.align	1
+  98              		.syntax unified
+  99              		.thumb
+ 100              		.thumb_func
+ 101              		.fpu fpv5-d16
+ 103              	st_word:
+ 104              	.LVL10:
+ 105              	.LFB1185:
+ 633:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 634:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 635:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 636:Middlewares/Third_Party/FatFs/src/ff.c **** QWORD ld_qword (const BYTE* ptr)	/* Load an 8-byte little-endian word */
+ 637:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 638:Middlewares/Third_Party/FatFs/src/ff.c **** 	QWORD rv;
+ 639:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 640:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = ptr[7];
+ 641:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = rv << 8 | ptr[6];
+ARM GAS  /tmp/cc5lWXRL.s 			page 14
+
+
+ 642:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = rv << 8 | ptr[5];
+ 643:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = rv << 8 | ptr[4];
+ 644:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = rv << 8 | ptr[3];
+ 645:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = rv << 8 | ptr[2];
+ 646:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = rv << 8 | ptr[1];
+ 647:Middlewares/Third_Party/FatFs/src/ff.c **** 	rv = rv << 8 | ptr[0];
+ 648:Middlewares/Third_Party/FatFs/src/ff.c **** 	return rv;
+ 649:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 650:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 651:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 652:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 653:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 654:Middlewares/Third_Party/FatFs/src/ff.c **** void st_word (BYTE* ptr, WORD val)	/* Store a 2-byte word in little-endian */
+ 655:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 106              		.loc 1 655 1 is_stmt 1 view -0
+ 107              		.cfi_startproc
+ 108              		@ args = 0, pretend = 0, frame = 0
+ 109              		@ frame_needed = 0, uses_anonymous_args = 0
+ 110              		@ link register save eliminated.
+ 656:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val; val >>= 8;
+ 111              		.loc 1 656 2 view .LVU25
+ 112              		.loc 1 656 9 is_stmt 0 view .LVU26
+ 113 0000 0170     		strb	r1, [r0]
+ 114              		.loc 1 656 22 is_stmt 1 view .LVU27
+ 115              	.LVL11:
+ 657:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val;
+ 116              		.loc 1 657 2 view .LVU28
+ 117              		.loc 1 657 11 is_stmt 0 view .LVU29
+ 118 0002 090A     		lsrs	r1, r1, #8
+ 119              	.LVL12:
+ 120              		.loc 1 657 9 view .LVU30
+ 121 0004 4170     		strb	r1, [r0, #1]
+ 658:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 122              		.loc 1 658 1 view .LVU31
+ 123 0006 7047     		bx	lr
+ 124              		.cfi_endproc
+ 125              	.LFE1185:
+ 127              		.section	.text.st_dword,"ax",%progbits
+ 128              		.align	1
+ 129              		.syntax unified
+ 130              		.thumb
+ 131              		.thumb_func
+ 132              		.fpu fpv5-d16
+ 134              	st_dword:
+ 135              	.LVL13:
+ 136              	.LFB1186:
+ 659:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 660:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 661:Middlewares/Third_Party/FatFs/src/ff.c **** void st_dword (BYTE* ptr, DWORD val)	/* Store a 4-byte word in little-endian */
+ 662:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 137              		.loc 1 662 1 is_stmt 1 view -0
+ 138              		.cfi_startproc
+ 139              		@ args = 0, pretend = 0, frame = 0
+ 140              		@ frame_needed = 0, uses_anonymous_args = 0
+ 141              		@ link register save eliminated.
+ 663:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val; val >>= 8;
+ 142              		.loc 1 663 2 view .LVU33
+ARM GAS  /tmp/cc5lWXRL.s 			page 15
+
+
+ 143              		.loc 1 663 9 is_stmt 0 view .LVU34
+ 144 0000 0170     		strb	r1, [r0]
+ 145              		.loc 1 663 22 is_stmt 1 view .LVU35
+ 146              	.LVL14:
+ 664:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val; val >>= 8;
+ 147              		.loc 1 664 2 view .LVU36
+ 148              		.loc 1 664 11 is_stmt 0 view .LVU37
+ 149 0002 C1F30723 		ubfx	r3, r1, #8, #8
+ 150              		.loc 1 664 9 view .LVU38
+ 151 0006 4370     		strb	r3, [r0, #1]
+ 152              		.loc 1 664 22 is_stmt 1 view .LVU39
+ 153              	.LVL15:
+ 665:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val; val >>= 8;
+ 154              		.loc 1 665 2 view .LVU40
+ 155              		.loc 1 665 11 is_stmt 0 view .LVU41
+ 156 0008 C1F30743 		ubfx	r3, r1, #16, #8
+ 157              		.loc 1 665 9 view .LVU42
+ 158 000c 8370     		strb	r3, [r0, #2]
+ 159              		.loc 1 665 22 is_stmt 1 view .LVU43
+ 160              	.LVL16:
+ 666:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val;
+ 161              		.loc 1 666 2 view .LVU44
+ 162              		.loc 1 666 11 is_stmt 0 view .LVU45
+ 163 000e 090E     		lsrs	r1, r1, #24
+ 164              	.LVL17:
+ 165              		.loc 1 666 9 view .LVU46
+ 166 0010 C170     		strb	r1, [r0, #3]
+ 667:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 167              		.loc 1 667 1 view .LVU47
+ 168 0012 7047     		bx	lr
+ 169              		.cfi_endproc
+ 170              	.LFE1186:
+ 172              		.section	.text.mem_cpy,"ax",%progbits
+ 173              		.align	1
+ 174              		.syntax unified
+ 175              		.thumb
+ 176              		.thumb_func
+ 177              		.fpu fpv5-d16
+ 179              	mem_cpy:
+ 180              	.LVL18:
+ 181              	.LFB1187:
+ 668:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 669:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 670:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 671:Middlewares/Third_Party/FatFs/src/ff.c **** void st_qword (BYTE* ptr, QWORD val)	/* Store an 8-byte word in little-endian */
+ 672:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 673:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val; val >>= 8;
+ 674:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val; val >>= 8;
+ 675:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val; val >>= 8;
+ 676:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val; val >>= 8;
+ 677:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val; val >>= 8;
+ 678:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val; val >>= 8;
+ 679:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val; val >>= 8;
+ 680:Middlewares/Third_Party/FatFs/src/ff.c **** 	*ptr++ = (BYTE)val;
+ 681:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 682:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 683:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* !_FS_READONLY */
+ARM GAS  /tmp/cc5lWXRL.s 			page 16
+
+
+ 684:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 685:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 686:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 687:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 688:Middlewares/Third_Party/FatFs/src/ff.c **** /* String functions                                                      */
+ 689:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 690:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 691:Middlewares/Third_Party/FatFs/src/ff.c **** /* Copy memory to memory */
+ 692:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 693:Middlewares/Third_Party/FatFs/src/ff.c **** void mem_cpy (void* dst, const void* src, UINT cnt) {
+ 182              		.loc 1 693 53 is_stmt 1 view -0
+ 183              		.cfi_startproc
+ 184              		@ args = 0, pretend = 0, frame = 0
+ 185              		@ frame_needed = 0, uses_anonymous_args = 0
+ 186              		@ link register save eliminated.
+ 694:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *d = (BYTE*)dst;
+ 187              		.loc 1 694 2 view .LVU49
+ 695:Middlewares/Third_Party/FatFs/src/ff.c **** 	const BYTE *s = (const BYTE*)src;
+ 188              		.loc 1 695 2 view .LVU50
+ 696:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 697:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (cnt) {
+ 189              		.loc 1 697 2 view .LVU51
+ 190              		.loc 1 697 5 is_stmt 0 view .LVU52
+ 191 0000 9446     		mov	ip, r2
+ 192 0002 32B1     		cbz	r2, .L5
+ 193              	.LVL19:
+ 194              	.L7:
+ 698:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+ 195              		.loc 1 698 3 is_stmt 1 discriminator 1 view .LVU53
+ 699:Middlewares/Third_Party/FatFs/src/ff.c **** 			*d++ = *s++;
+ 196              		.loc 1 699 4 discriminator 1 view .LVU54
+ 197              		.loc 1 699 11 is_stmt 0 discriminator 1 view .LVU55
+ 198 0004 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 199 0006 0131     		adds	r1, r1, #1
+ 200              	.LVL20:
+ 201              		.loc 1 699 9 discriminator 1 view .LVU56
+ 202 0008 0270     		strb	r2, [r0]
+ 203 000a 0130     		adds	r0, r0, #1
+ 204              	.LVL21:
+ 700:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (--cnt);
+ 205              		.loc 1 700 11 is_stmt 1 discriminator 1 view .LVU57
+ 206              		.loc 1 700 3 is_stmt 0 discriminator 1 view .LVU58
+ 207 000c BCF1010C 		subs	ip, ip, #1
+ 208              	.LVL22:
+ 209              		.loc 1 700 3 discriminator 1 view .LVU59
+ 210 0010 F8D1     		bne	.L7
+ 211              	.LVL23:
+ 212              	.L5:
+ 701:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 702:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 213              		.loc 1 702 1 view .LVU60
+ 214 0012 7047     		bx	lr
+ 215              		.cfi_endproc
+ 216              	.LFE1187:
+ 218              		.section	.text.mem_set,"ax",%progbits
+ 219              		.align	1
+ 220              		.syntax unified
+ARM GAS  /tmp/cc5lWXRL.s 			page 17
+
+
+ 221              		.thumb
+ 222              		.thumb_func
+ 223              		.fpu fpv5-d16
+ 225              	mem_set:
+ 226              	.LFB1188:
+ 703:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 704:Middlewares/Third_Party/FatFs/src/ff.c **** /* Fill memory block */
+ 705:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 706:Middlewares/Third_Party/FatFs/src/ff.c **** void mem_set (void* dst, int val, UINT cnt) {
+ 227              		.loc 1 706 45 is_stmt 1 view -0
+ 228              		.cfi_startproc
+ 229              		@ args = 0, pretend = 0, frame = 0
+ 230              		@ frame_needed = 0, uses_anonymous_args = 0
+ 231              		@ link register save eliminated.
+ 232              	.LVL24:
+ 233              	.L9:
+ 707:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *d = (BYTE*)dst;
+ 708:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 709:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+ 234              		.loc 1 709 2 discriminator 1 view .LVU62
+ 710:Middlewares/Third_Party/FatFs/src/ff.c **** 		*d++ = (BYTE)val;
+ 235              		.loc 1 710 3 discriminator 1 view .LVU63
+ 236              		.loc 1 710 8 is_stmt 0 discriminator 1 view .LVU64
+ 237 0000 0170     		strb	r1, [r0]
+ 238 0002 0130     		adds	r0, r0, #1
+ 711:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (--cnt);
+ 239              		.loc 1 711 10 is_stmt 1 discriminator 1 view .LVU65
+ 240              	.LVL25:
+ 241              		.loc 1 711 2 is_stmt 0 discriminator 1 view .LVU66
+ 242 0004 013A     		subs	r2, r2, #1
+ 243              	.LVL26:
+ 244              		.loc 1 711 2 discriminator 1 view .LVU67
+ 245 0006 FBD1     		bne	.L9
+ 712:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 246              		.loc 1 712 1 view .LVU68
+ 247 0008 7047     		bx	lr
+ 248              		.cfi_endproc
+ 249              	.LFE1188:
+ 251              		.section	.text.mem_cmp,"ax",%progbits
+ 252              		.align	1
+ 253              		.syntax unified
+ 254              		.thumb
+ 255              		.thumb_func
+ 256              		.fpu fpv5-d16
+ 258              	mem_cmp:
+ 259              	.LVL27:
+ 260              	.LFB1189:
+ 713:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 714:Middlewares/Third_Party/FatFs/src/ff.c **** /* Compare memory block */
+ 715:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 716:Middlewares/Third_Party/FatFs/src/ff.c **** int mem_cmp (const void* dst, const void* src, UINT cnt) {	/* ZR:same, NZ:different */
+ 261              		.loc 1 716 58 is_stmt 1 view -0
+ 262              		.cfi_startproc
+ 263              		@ args = 0, pretend = 0, frame = 0
+ 264              		@ frame_needed = 0, uses_anonymous_args = 0
+ 265              		@ link register save eliminated.
+ 266              		.loc 1 716 58 is_stmt 0 view .LVU70
+ARM GAS  /tmp/cc5lWXRL.s 			page 18
+
+
+ 267 0000 8446     		mov	ip, r0
+ 717:Middlewares/Third_Party/FatFs/src/ff.c **** 	const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
+ 268              		.loc 1 717 2 is_stmt 1 view .LVU71
+ 269              	.LVL28:
+ 718:Middlewares/Third_Party/FatFs/src/ff.c **** 	int r = 0;
+ 270              		.loc 1 718 2 view .LVU72
+ 271              	.L12:
+ 719:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 720:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+ 272              		.loc 1 720 2 discriminator 2 view .LVU73
+ 721:Middlewares/Third_Party/FatFs/src/ff.c **** 		r = *d++ - *s++;
+ 273              		.loc 1 721 3 discriminator 2 view .LVU74
+ 274              		.loc 1 721 7 is_stmt 0 discriminator 2 view .LVU75
+ 275 0002 9CF80000 		ldrb	r0, [ip]	@ zero_extendqisi2
+ 276 0006 0CF1010C 		add	ip, ip, #1
+ 277              	.LVL29:
+ 278              		.loc 1 721 14 discriminator 2 view .LVU76
+ 279 000a 0B78     		ldrb	r3, [r1]	@ zero_extendqisi2
+ 280 000c 0131     		adds	r1, r1, #1
+ 281              	.LVL30:
+ 282              		.loc 1 721 5 discriminator 2 view .LVU77
+ 283 000e C01A     		subs	r0, r0, r3
+ 284              	.LVL31:
+ 722:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (--cnt && r == 0);
+ 285              		.loc 1 722 10 is_stmt 1 discriminator 2 view .LVU78
+ 286              		.loc 1 722 2 is_stmt 0 discriminator 2 view .LVU79
+ 287 0010 013A     		subs	r2, r2, #1
+ 288              	.LVL32:
+ 289              		.loc 1 722 2 discriminator 2 view .LVU80
+ 290 0012 01D0     		beq	.L10
+ 291              		.loc 1 722 17 discriminator 1 view .LVU81
+ 292 0014 0028     		cmp	r0, #0
+ 293 0016 F4D0     		beq	.L12
+ 294              	.L10:
+ 723:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 724:Middlewares/Third_Party/FatFs/src/ff.c **** 	return r;
+ 725:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 295              		.loc 1 725 1 view .LVU82
+ 296 0018 7047     		bx	lr
+ 297              		.cfi_endproc
+ 298              	.LFE1189:
+ 300              		.section	.text.chk_chr,"ax",%progbits
+ 301              		.align	1
+ 302              		.syntax unified
+ 303              		.thumb
+ 304              		.thumb_func
+ 305              		.fpu fpv5-d16
+ 307              	chk_chr:
+ 308              	.LVL33:
+ 309              	.LFB1190:
+ 726:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 727:Middlewares/Third_Party/FatFs/src/ff.c **** /* Check if chr is contained in the string */
+ 728:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 729:Middlewares/Third_Party/FatFs/src/ff.c **** int chk_chr (const char* str, int chr) {	/* NZ:contained, ZR:not contained */
+ 310              		.loc 1 729 40 is_stmt 1 view -0
+ 311              		.cfi_startproc
+ 312              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/cc5lWXRL.s 			page 19
+
+
+ 313              		@ frame_needed = 0, uses_anonymous_args = 0
+ 314              		@ link register save eliminated.
+ 315              		.loc 1 729 40 is_stmt 0 view .LVU84
+ 316 0000 0346     		mov	r3, r0
+ 730:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (*str && *str != chr) str++;
+ 317              		.loc 1 730 2 is_stmt 1 view .LVU85
+ 318              		.loc 1 730 8 is_stmt 0 view .LVU86
+ 319 0002 00E0     		b	.L14
+ 320              	.LVL34:
+ 321              	.L16:
+ 322              		.loc 1 730 30 is_stmt 1 discriminator 3 view .LVU87
+ 323              		.loc 1 730 33 is_stmt 0 discriminator 3 view .LVU88
+ 324 0004 0133     		adds	r3, r3, #1
+ 325              	.LVL35:
+ 326              	.L14:
+ 327              		.loc 1 730 8 is_stmt 1 discriminator 1 view .LVU89
+ 328              		.loc 1 730 9 is_stmt 0 discriminator 1 view .LVU90
+ 329 0006 1878     		ldrb	r0, [r3]	@ zero_extendqisi2
+ 330              		.loc 1 730 8 discriminator 1 view .LVU91
+ 331 0008 08B1     		cbz	r0, .L15
+ 332              		.loc 1 730 14 discriminator 2 view .LVU92
+ 333 000a 8842     		cmp	r0, r1
+ 334 000c FAD1     		bne	.L16
+ 335              	.L15:
+ 731:Middlewares/Third_Party/FatFs/src/ff.c **** 	return *str;
+ 336              		.loc 1 731 2 is_stmt 1 view .LVU93
+ 732:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 337              		.loc 1 732 1 is_stmt 0 view .LVU94
+ 338 000e 7047     		bx	lr
+ 339              		.cfi_endproc
+ 340              	.LFE1190:
+ 342              		.section	.text.chk_lock,"ax",%progbits
+ 343              		.align	1
+ 344              		.syntax unified
+ 345              		.thumb
+ 346              		.thumb_func
+ 347              		.fpu fpv5-d16
+ 349              	chk_lock:
+ 350              	.LVL36:
+ 351              	.LFB1191:
+ 733:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 734:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 735:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 736:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 737:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+ 738:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 739:Middlewares/Third_Party/FatFs/src/ff.c **** /* Request/Release grant to access the volume                            */
+ 740:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 741:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 742:Middlewares/Third_Party/FatFs/src/ff.c **** int lock_fs (
+ 743:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs		/* File system object */
+ 744:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ 745:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 746:Middlewares/Third_Party/FatFs/src/ff.c **** 	return (fs && ff_req_grant(fs->sobj)) ? 1 : 0;
+ 747:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 748:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 749:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 20
+
+
+ 750:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 751:Middlewares/Third_Party/FatFs/src/ff.c **** void unlock_fs (
+ 752:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs,		/* File system object */
+ 753:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res		/* Result code to be returned */
+ 754:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ 755:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 756:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) {
+ 757:Middlewares/Third_Party/FatFs/src/ff.c **** 		ff_rel_grant(fs->sobj);
+ 758:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 759:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 760:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 761:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 762:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 763:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 764:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 765:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 766:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 767:Middlewares/Third_Party/FatFs/src/ff.c **** /* File lock control functions                                           */
+ 768:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 769:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 770:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 771:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT chk_lock (	/* Check if the file can be accessed */
+ 772:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,		/* Directory object pointing the file to be checked */
+ 773:Middlewares/Third_Party/FatFs/src/ff.c **** 	int acc			/* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */
+ 774:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ 775:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 352              		.loc 1 775 1 is_stmt 1 view -0
+ 353              		.cfi_startproc
+ 354              		@ args = 0, pretend = 0, frame = 0
+ 355              		@ frame_needed = 0, uses_anonymous_args = 0
+ 356              		@ link register save eliminated.
+ 357              		.loc 1 775 1 is_stmt 0 view .LVU96
+ 358 0000 10B4     		push	{r4}
+ 359              	.LCFI0:
+ 360              		.cfi_def_cfa_offset 4
+ 361              		.cfi_offset 4, -4
+ 776:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, be;
+ 362              		.loc 1 776 2 is_stmt 1 view .LVU97
+ 777:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 778:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Search file semaphore table */
+ 779:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (i = be = 0; i < _FS_LOCK; i++) {
+ 363              		.loc 1 779 2 view .LVU98
+ 364              	.LVL37:
+ 365              		.loc 1 779 14 is_stmt 0 view .LVU99
+ 366 0002 4FF0000C 		mov	ip, #0
+ 367              		.loc 1 779 9 view .LVU100
+ 368 0006 6346     		mov	r3, ip
+ 369              		.loc 1 779 2 view .LVU101
+ 370 0008 02E0     		b	.L18
+ 371              	.LVL38:
+ 372              	.L25:
+ 780:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs) {	/* Existing entry */
+ 781:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (Files[i].fs == dp->obj.fs &&	 	/* Check if the object matched with an open object */
+ 782:Middlewares/Third_Party/FatFs/src/ff.c **** 				Files[i].clu == dp->obj.sclust &&
+ 783:Middlewares/Third_Party/FatFs/src/ff.c **** 				Files[i].ofs == dp->dptr) break;
+ 784:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {			/* Blank entry */
+ 785:Middlewares/Third_Party/FatFs/src/ff.c **** 			be = 1;
+ARM GAS  /tmp/cc5lWXRL.s 			page 21
+
+
+ 373              		.loc 1 785 7 view .LVU102
+ 374 000a 4FF0010C 		mov	ip, #1
+ 375              	.LVL39:
+ 376              	.L19:
+ 779:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs) {	/* Existing entry */
+ 377              		.loc 1 779 33 is_stmt 1 discriminator 2 view .LVU103
+ 779:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs) {	/* Existing entry */
+ 378              		.loc 1 779 34 is_stmt 0 discriminator 2 view .LVU104
+ 379 000e 0133     		adds	r3, r3, #1
+ 380              	.LVL40:
+ 381              	.L18:
+ 779:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs) {	/* Existing entry */
+ 382              		.loc 1 779 19 is_stmt 1 discriminator 1 view .LVU105
+ 779:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs) {	/* Existing entry */
+ 383              		.loc 1 779 2 is_stmt 0 discriminator 1 view .LVU106
+ 384 0010 012B     		cmp	r3, #1
+ 385 0012 15D8     		bhi	.L20
+ 780:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs) {	/* Existing entry */
+ 386              		.loc 1 780 3 is_stmt 1 view .LVU107
+ 780:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs) {	/* Existing entry */
+ 387              		.loc 1 780 15 is_stmt 0 view .LVU108
+ 388 0014 1A01     		lsls	r2, r3, #4
+ 389 0016 184C     		ldr	r4, .L32
+ 390 0018 A258     		ldr	r2, [r4, r2]
+ 780:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs) {	/* Existing entry */
+ 391              		.loc 1 780 6 view .LVU109
+ 392 001a 002A     		cmp	r2, #0
+ 393 001c F5D0     		beq	.L25
+ 781:Middlewares/Third_Party/FatFs/src/ff.c **** 				Files[i].clu == dp->obj.sclust &&
+ 394              		.loc 1 781 4 is_stmt 1 view .LVU110
+ 781:Middlewares/Third_Party/FatFs/src/ff.c **** 				Files[i].clu == dp->obj.sclust &&
+ 395              		.loc 1 781 30 is_stmt 0 view .LVU111
+ 396 001e 0468     		ldr	r4, [r0]
+ 781:Middlewares/Third_Party/FatFs/src/ff.c **** 				Files[i].clu == dp->obj.sclust &&
+ 397              		.loc 1 781 7 view .LVU112
+ 398 0020 A242     		cmp	r2, r4
+ 399 0022 F4D1     		bne	.L19
+ 782:Middlewares/Third_Party/FatFs/src/ff.c **** 				Files[i].ofs == dp->dptr) break;
+ 400              		.loc 1 782 13 discriminator 1 view .LVU113
+ 401 0024 144A     		ldr	r2, .L32
+ 402 0026 02EB0312 		add	r2, r2, r3, lsl #4
+ 403 002a 5468     		ldr	r4, [r2, #4]
+ 782:Middlewares/Third_Party/FatFs/src/ff.c **** 				Files[i].ofs == dp->dptr) break;
+ 404              		.loc 1 782 28 discriminator 1 view .LVU114
+ 405 002c 8268     		ldr	r2, [r0, #8]
+ 781:Middlewares/Third_Party/FatFs/src/ff.c **** 				Files[i].clu == dp->obj.sclust &&
+ 406              		.loc 1 781 34 discriminator 1 view .LVU115
+ 407 002e 9442     		cmp	r4, r2
+ 408 0030 EDD1     		bne	.L19
+ 783:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {			/* Blank entry */
+ 409              		.loc 1 783 13 view .LVU116
+ 410 0032 114A     		ldr	r2, .L32
+ 411 0034 02EB0312 		add	r2, r2, r3, lsl #4
+ 412 0038 9468     		ldr	r4, [r2, #8]
+ 783:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {			/* Blank entry */
+ 413              		.loc 1 783 23 view .LVU117
+ 414 003a 4269     		ldr	r2, [r0, #20]
+ARM GAS  /tmp/cc5lWXRL.s 			page 22
+
+
+ 782:Middlewares/Third_Party/FatFs/src/ff.c **** 				Files[i].ofs == dp->dptr) break;
+ 415              		.loc 1 782 36 view .LVU118
+ 416 003c 9442     		cmp	r4, r2
+ 417 003e E6D1     		bne	.L19
+ 418              	.L20:
+ 786:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 787:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 788:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (i == _FS_LOCK) {	/* The object is not opened */
+ 419              		.loc 1 788 2 is_stmt 1 view .LVU119
+ 420              		.loc 1 788 5 is_stmt 0 view .LVU120
+ 421 0040 022B     		cmp	r3, #2
+ 422 0042 0BD0     		beq	.L30
+ 789:Middlewares/Third_Party/FatFs/src/ff.c **** 		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new objec
+ 790:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 791:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 792:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* The object has been opened. Reject any open against writing file and all write mode open */
+ 793:Middlewares/Third_Party/FatFs/src/ff.c **** 	return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+ 423              		.loc 1 793 2 is_stmt 1 view .LVU121
+ 424              		.loc 1 793 52 is_stmt 0 view .LVU122
+ 425 0044 B1B9     		cbnz	r1, .L27
+ 426              		.loc 1 793 25 discriminator 2 view .LVU123
+ 427 0046 0C4A     		ldr	r2, .L32
+ 428 0048 02EB0313 		add	r3, r2, r3, lsl #4
+ 429              	.LVL41:
+ 430              		.loc 1 793 25 discriminator 2 view .LVU124
+ 431 004c 9B89     		ldrh	r3, [r3, #12]
+ 432              		.loc 1 793 14 discriminator 2 view .LVU125
+ 433 004e B3F5807F 		cmp	r3, #256
+ 434 0052 0DD0     		beq	.L31
+ 435              		.loc 1 793 52 view .LVU126
+ 436 0054 0020     		movs	r0, #0
+ 437              	.LVL42:
+ 438              	.L24:
+ 794:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 439              		.loc 1 794 1 view .LVU127
+ 440 0056 5DF8044B 		ldr	r4, [sp], #4
+ 441              	.LCFI1:
+ 442              		.cfi_remember_state
+ 443              		.cfi_restore 4
+ 444              		.cfi_def_cfa_offset 0
+ 445 005a 7047     		bx	lr
+ 446              	.LVL43:
+ 447              	.L30:
+ 448              	.LCFI2:
+ 449              		.cfi_restore_state
+ 789:Middlewares/Third_Party/FatFs/src/ff.c **** 		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new objec
+ 450              		.loc 1 789 3 is_stmt 1 view .LVU128
+ 789:Middlewares/Third_Party/FatFs/src/ff.c **** 		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new objec
+ 451              		.loc 1 789 14 is_stmt 0 view .LVU129
+ 452 005c 0229     		cmp	r1, #2
+ 453 005e 14BF     		ite	ne
+ 454 0060 6346     		movne	r3, ip
+ 455 0062 4CF00103 		orreq	r3, ip, #1
+ 456              	.LVL44:
+ 789:Middlewares/Third_Party/FatFs/src/ff.c **** 		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new objec
+ 457              		.loc 1 789 35 view .LVU130
+ 458 0066 0BB1     		cbz	r3, .L26
+ARM GAS  /tmp/cc5lWXRL.s 			page 23
+
+
+ 459 0068 0020     		movs	r0, #0
+ 460              	.LVL45:
+ 789:Middlewares/Third_Party/FatFs/src/ff.c **** 		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new objec
+ 461              		.loc 1 789 35 view .LVU131
+ 462 006a F4E7     		b	.L24
+ 463              	.LVL46:
+ 464              	.L26:
+ 789:Middlewares/Third_Party/FatFs/src/ff.c **** 		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new objec
+ 465              		.loc 1 789 35 view .LVU132
+ 466 006c 1220     		movs	r0, #18
+ 467              	.LVL47:
+ 789:Middlewares/Third_Party/FatFs/src/ff.c **** 		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new objec
+ 468              		.loc 1 789 35 view .LVU133
+ 469 006e F2E7     		b	.L24
+ 470              	.LVL48:
+ 471              	.L31:
+ 793:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 472              		.loc 1 793 52 view .LVU134
+ 473 0070 1020     		movs	r0, #16
+ 474              	.LVL49:
+ 793:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 475              		.loc 1 793 52 view .LVU135
+ 476 0072 F0E7     		b	.L24
+ 477              	.LVL50:
+ 478              	.L27:
+ 793:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 479              		.loc 1 793 52 view .LVU136
+ 480 0074 1020     		movs	r0, #16
+ 481              	.LVL51:
+ 793:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 482              		.loc 1 793 52 view .LVU137
+ 483 0076 EEE7     		b	.L24
+ 484              	.L33:
+ 485              		.align	2
+ 486              	.L32:
+ 487 0078 00000000 		.word	.LANCHOR0
+ 488              		.cfi_endproc
+ 489              	.LFE1191:
+ 491              		.section	.text.enq_lock,"ax",%progbits
+ 492              		.align	1
+ 493              		.syntax unified
+ 494              		.thumb
+ 495              		.thumb_func
+ 496              		.fpu fpv5-d16
+ 498              	enq_lock:
+ 499              	.LFB1192:
+ 795:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 796:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 797:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 798:Middlewares/Third_Party/FatFs/src/ff.c **** int enq_lock (void)	/* Check if an entry is available for a new object */
+ 799:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 500              		.loc 1 799 1 is_stmt 1 view -0
+ 501              		.cfi_startproc
+ 502              		@ args = 0, pretend = 0, frame = 0
+ 503              		@ frame_needed = 0, uses_anonymous_args = 0
+ 504              		@ link register save eliminated.
+ 800:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+ARM GAS  /tmp/cc5lWXRL.s 			page 24
+
+
+ 505              		.loc 1 800 2 view .LVU139
+ 801:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 802:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ 506              		.loc 1 802 2 view .LVU140
+ 507              	.LVL52:
+ 508              		.loc 1 802 9 is_stmt 0 view .LVU141
+ 509 0000 0020     		movs	r0, #0
+ 510              		.loc 1 802 2 view .LVU142
+ 511 0002 00E0     		b	.L35
+ 512              	.LVL53:
+ 513              	.L37:
+ 514              		.loc 1 802 48 is_stmt 1 discriminator 4 view .LVU143
+ 515              		.loc 1 802 43 discriminator 4 view .LVU144
+ 516              		.loc 1 802 44 is_stmt 0 discriminator 4 view .LVU145
+ 517 0004 0130     		adds	r0, r0, #1
+ 518              	.LVL54:
+ 519              	.L35:
+ 520              		.loc 1 802 14 is_stmt 1 discriminator 1 view .LVU146
+ 521              		.loc 1 802 2 is_stmt 0 discriminator 1 view .LVU147
+ 522 0006 0128     		cmp	r0, #1
+ 523 0008 04D8     		bhi	.L36
+ 524              		.loc 1 802 38 discriminator 3 view .LVU148
+ 525 000a 0301     		lsls	r3, r0, #4
+ 526 000c 034A     		ldr	r2, .L38
+ 527 000e D358     		ldr	r3, [r2, r3]
+ 528              		.loc 1 802 27 discriminator 3 view .LVU149
+ 529 0010 002B     		cmp	r3, #0
+ 530 0012 F7D1     		bne	.L37
+ 531              	.L36:
+ 803:Middlewares/Third_Party/FatFs/src/ff.c **** 	return (i == _FS_LOCK) ? 0 : 1;
+ 532              		.loc 1 803 2 is_stmt 1 view .LVU150
+ 804:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 533              		.loc 1 804 1 is_stmt 0 view .LVU151
+ 534 0014 0238     		subs	r0, r0, #2
+ 535              	.LVL55:
+ 536              		.loc 1 804 1 view .LVU152
+ 537 0016 18BF     		it	ne
+ 538 0018 0120     		movne	r0, #1
+ 539              	.LVL56:
+ 540              		.loc 1 804 1 view .LVU153
+ 541 001a 7047     		bx	lr
+ 542              	.L39:
+ 543              		.align	2
+ 544              	.L38:
+ 545 001c 00000000 		.word	.LANCHOR0
+ 546              		.cfi_endproc
+ 547              	.LFE1192:
+ 549              		.section	.text.inc_lock,"ax",%progbits
+ 550              		.align	1
+ 551              		.syntax unified
+ 552              		.thumb
+ 553              		.thumb_func
+ 554              		.fpu fpv5-d16
+ 556              	inc_lock:
+ 557              	.LVL57:
+ 558              	.LFB1193:
+ 805:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 25
+
+
+ 806:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 807:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 808:Middlewares/Third_Party/FatFs/src/ff.c **** UINT inc_lock (	/* Increment object open counter and returns its index (0:Internal error) */
+ 809:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,	/* Directory object pointing the file to register or increment */
+ 810:Middlewares/Third_Party/FatFs/src/ff.c **** 	int acc		/* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+ 811:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ 812:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 559              		.loc 1 812 1 is_stmt 1 view -0
+ 560              		.cfi_startproc
+ 561              		@ args = 0, pretend = 0, frame = 0
+ 562              		@ frame_needed = 0, uses_anonymous_args = 0
+ 563              		@ link register save eliminated.
+ 564              		.loc 1 812 1 is_stmt 0 view .LVU155
+ 565 0000 70B4     		push	{r4, r5, r6}
+ 566              	.LCFI3:
+ 567              		.cfi_def_cfa_offset 12
+ 568              		.cfi_offset 4, -12
+ 569              		.cfi_offset 5, -8
+ 570              		.cfi_offset 6, -4
+ 813:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+ 571              		.loc 1 813 2 is_stmt 1 view .LVU156
+ 814:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 815:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 816:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (i = 0; i < _FS_LOCK; i++) {	/* Find the object */
+ 572              		.loc 1 816 2 view .LVU157
+ 573              	.LVL58:
+ 574              		.loc 1 816 9 is_stmt 0 view .LVU158
+ 575 0002 0023     		movs	r3, #0
+ 576              		.loc 1 816 2 view .LVU159
+ 577 0004 00E0     		b	.L41
+ 578              	.LVL59:
+ 579              	.L42:
+ 580              		.loc 1 816 28 is_stmt 1 discriminator 2 view .LVU160
+ 581              		.loc 1 816 29 is_stmt 0 discriminator 2 view .LVU161
+ 582 0006 0133     		adds	r3, r3, #1
+ 583              	.LVL60:
+ 584              	.L41:
+ 585              		.loc 1 816 14 is_stmt 1 discriminator 1 view .LVU162
+ 586              		.loc 1 816 2 is_stmt 0 discriminator 1 view .LVU163
+ 587 0008 012B     		cmp	r3, #1
+ 588 000a 13D8     		bhi	.L43
+ 817:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == dp->obj.fs &&
+ 589              		.loc 1 817 3 is_stmt 1 view .LVU164
+ 590              		.loc 1 817 15 is_stmt 0 view .LVU165
+ 591 000c 1A01     		lsls	r2, r3, #4
+ 592 000e 244C     		ldr	r4, .L58
+ 593 0010 A458     		ldr	r4, [r4, r2]
+ 594              		.loc 1 817 29 view .LVU166
+ 595 0012 0268     		ldr	r2, [r0]
+ 596              		.loc 1 817 6 view .LVU167
+ 597 0014 9442     		cmp	r4, r2
+ 598 0016 F6D1     		bne	.L42
+ 818:Middlewares/Third_Party/FatFs/src/ff.c **** 			Files[i].clu == dp->obj.sclust &&
+ 599              		.loc 1 818 12 discriminator 1 view .LVU168
+ 600 0018 214A     		ldr	r2, .L58
+ 601 001a 02EB0312 		add	r2, r2, r3, lsl #4
+ 602 001e 5468     		ldr	r4, [r2, #4]
+ARM GAS  /tmp/cc5lWXRL.s 			page 26
+
+
+ 603              		.loc 1 818 27 discriminator 1 view .LVU169
+ 604 0020 8268     		ldr	r2, [r0, #8]
+ 817:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == dp->obj.fs &&
+ 605              		.loc 1 817 33 discriminator 1 view .LVU170
+ 606 0022 9442     		cmp	r4, r2
+ 607 0024 EFD1     		bne	.L42
+ 819:Middlewares/Third_Party/FatFs/src/ff.c **** 			Files[i].ofs == dp->dptr) break;
+ 608              		.loc 1 819 12 view .LVU171
+ 609 0026 1E4A     		ldr	r2, .L58
+ 610 0028 02EB0312 		add	r2, r2, r3, lsl #4
+ 611 002c 9468     		ldr	r4, [r2, #8]
+ 612              		.loc 1 819 22 view .LVU172
+ 613 002e 4269     		ldr	r2, [r0, #20]
+ 818:Middlewares/Third_Party/FatFs/src/ff.c **** 			Files[i].clu == dp->obj.sclust &&
+ 614              		.loc 1 818 35 view .LVU173
+ 615 0030 9442     		cmp	r4, r2
+ 616 0032 E8D1     		bne	.L42
+ 617              	.L43:
+ 820:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 821:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 822:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (i == _FS_LOCK) {				/* Not opened. Register it as new. */
+ 618              		.loc 1 822 2 is_stmt 1 view .LVU174
+ 619              		.loc 1 822 5 is_stmt 0 view .LVU175
+ 620 0034 022B     		cmp	r3, #2
+ 621 0036 0DD0     		beq	.L57
+ 622              	.LVL61:
+ 623              	.L46:
+ 823:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ 824:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i == _FS_LOCK) return 0;	/* No free entry to register (int err) */
+ 825:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].fs = dp->obj.fs;
+ 826:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].clu = dp->obj.sclust;
+ 827:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].ofs = dp->dptr;
+ 828:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].ctr = 0;
+ 829:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 830:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 831:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (acc && Files[i].ctr) return 0;	/* Access violation (int err) */
+ 624              		.loc 1 831 2 is_stmt 1 view .LVU176
+ 625              		.loc 1 831 5 is_stmt 0 view .LVU177
+ 626 0038 21B1     		cbz	r1, .L50
+ 627              		.loc 1 831 21 discriminator 1 view .LVU178
+ 628 003a 194A     		ldr	r2, .L58
+ 629 003c 02EB0312 		add	r2, r2, r3, lsl #4
+ 630 0040 9289     		ldrh	r2, [r2, #12]
+ 631              		.loc 1 831 10 discriminator 1 view .LVU179
+ 632 0042 52BB     		cbnz	r2, .L54
+ 633              	.L50:
+ 832:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 833:Middlewares/Third_Party/FatFs/src/ff.c **** 	Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1;	/* Set semaphore value */
+ 634              		.loc 1 833 2 is_stmt 1 view .LVU180
+ 635              		.loc 1 833 15 is_stmt 0 view .LVU181
+ 636 0044 F1B9     		cbnz	r1, .L55
+ 637              		.loc 1 833 39 discriminator 1 view .LVU182
+ 638 0046 164A     		ldr	r2, .L58
+ 639 0048 02EB0312 		add	r2, r2, r3, lsl #4
+ 640 004c 9189     		ldrh	r1, [r2, #12]
+ 641              	.LVL62:
+ 642              		.loc 1 833 15 discriminator 1 view .LVU183
+ARM GAS  /tmp/cc5lWXRL.s 			page 27
+
+
+ 643 004e 0131     		adds	r1, r1, #1
+ 644 0050 89B2     		uxth	r1, r1
+ 645 0052 19E0     		b	.L51
+ 646              	.LVL63:
+ 647              	.L57:
+ 823:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ 648              		.loc 1 823 10 view .LVU184
+ 649 0054 0023     		movs	r3, #0
+ 650              	.LVL64:
+ 651              	.L45:
+ 823:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ 652              		.loc 1 823 15 is_stmt 1 discriminator 1 view .LVU185
+ 823:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ 653              		.loc 1 823 3 is_stmt 0 discriminator 1 view .LVU186
+ 654 0056 012B     		cmp	r3, #1
+ 655 0058 05D8     		bhi	.L47
+ 823:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ 656              		.loc 1 823 39 discriminator 3 view .LVU187
+ 657 005a 1A01     		lsls	r2, r3, #4
+ 658 005c 104C     		ldr	r4, .L58
+ 659 005e A258     		ldr	r2, [r4, r2]
+ 823:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ 660              		.loc 1 823 28 discriminator 3 view .LVU188
+ 661 0060 0AB1     		cbz	r2, .L47
+ 823:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ 662              		.loc 1 823 49 is_stmt 1 discriminator 4 view .LVU189
+ 823:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ 663              		.loc 1 823 44 discriminator 4 view .LVU190
+ 823:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ 664              		.loc 1 823 45 is_stmt 0 discriminator 4 view .LVU191
+ 665 0062 0133     		adds	r3, r3, #1
+ 666              	.LVL65:
+ 823:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ 667              		.loc 1 823 45 discriminator 4 view .LVU192
+ 668 0064 F7E7     		b	.L45
+ 669              	.L47:
+ 824:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].fs = dp->obj.fs;
+ 670              		.loc 1 824 3 is_stmt 1 view .LVU193
+ 824:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].fs = dp->obj.fs;
+ 671              		.loc 1 824 6 is_stmt 0 view .LVU194
+ 672 0066 022B     		cmp	r3, #2
+ 673 0068 15D0     		beq	.L53
+ 825:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].clu = dp->obj.sclust;
+ 674              		.loc 1 825 3 is_stmt 1 view .LVU195
+ 825:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].clu = dp->obj.sclust;
+ 675              		.loc 1 825 15 is_stmt 0 view .LVU196
+ 676 006a 0D4D     		ldr	r5, .L58
+ 677 006c 1C01     		lsls	r4, r3, #4
+ 678 006e 05EB0312 		add	r2, r5, r3, lsl #4
+ 679 0072 0668     		ldr	r6, [r0]
+ 680 0074 2E51     		str	r6, [r5, r4]
+ 826:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].ofs = dp->dptr;
+ 681              		.loc 1 826 3 is_stmt 1 view .LVU197
+ 826:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].ofs = dp->dptr;
+ 682              		.loc 1 826 25 is_stmt 0 view .LVU198
+ 683 0076 8468     		ldr	r4, [r0, #8]
+ 826:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].ofs = dp->dptr;
+ARM GAS  /tmp/cc5lWXRL.s 			page 28
+
+
+ 684              		.loc 1 826 16 view .LVU199
+ 685 0078 5460     		str	r4, [r2, #4]
+ 827:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].ctr = 0;
+ 686              		.loc 1 827 3 is_stmt 1 view .LVU200
+ 827:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].ctr = 0;
+ 687              		.loc 1 827 20 is_stmt 0 view .LVU201
+ 688 007a 4069     		ldr	r0, [r0, #20]
+ 689              	.LVL66:
+ 827:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].ctr = 0;
+ 690              		.loc 1 827 16 view .LVU202
+ 691 007c 9060     		str	r0, [r2, #8]
+ 828:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 692              		.loc 1 828 3 is_stmt 1 view .LVU203
+ 828:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 693              		.loc 1 828 16 is_stmt 0 view .LVU204
+ 694 007e 0020     		movs	r0, #0
+ 695 0080 9081     		strh	r0, [r2, #12]	@ movhi
+ 696 0082 D9E7     		b	.L46
+ 697              	.L55:
+ 698              		.loc 1 833 15 view .LVU205
+ 699 0084 4FF48071 		mov	r1, #256
+ 700              	.LVL67:
+ 701              	.L51:
+ 702              		.loc 1 833 15 discriminator 4 view .LVU206
+ 703 0088 054A     		ldr	r2, .L58
+ 704 008a 02EB0312 		add	r2, r2, r3, lsl #4
+ 705 008e 9181     		strh	r1, [r2, #12]	@ movhi
+ 834:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 835:Middlewares/Third_Party/FatFs/src/ff.c **** 	return i + 1;
+ 706              		.loc 1 835 2 is_stmt 1 discriminator 4 view .LVU207
+ 707              		.loc 1 835 11 is_stmt 0 discriminator 4 view .LVU208
+ 708 0090 581C     		adds	r0, r3, #1
+ 709              	.L40:
+ 836:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 710              		.loc 1 836 1 view .LVU209
+ 711 0092 70BC     		pop	{r4, r5, r6}
+ 712              	.LCFI4:
+ 713              		.cfi_remember_state
+ 714              		.cfi_restore 6
+ 715              		.cfi_restore 5
+ 716              		.cfi_restore 4
+ 717              		.cfi_def_cfa_offset 0
+ 718 0094 7047     		bx	lr
+ 719              	.LVL68:
+ 720              	.L53:
+ 721              	.LCFI5:
+ 722              		.cfi_restore_state
+ 824:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].fs = dp->obj.fs;
+ 723              		.loc 1 824 29 view .LVU210
+ 724 0096 0020     		movs	r0, #0
+ 725              	.LVL69:
+ 824:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].fs = dp->obj.fs;
+ 726              		.loc 1 824 29 view .LVU211
+ 727 0098 FBE7     		b	.L40
+ 728              	.L54:
+ 831:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 729              		.loc 1 831 34 view .LVU212
+ARM GAS  /tmp/cc5lWXRL.s 			page 29
+
+
+ 730 009a 0020     		movs	r0, #0
+ 731 009c F9E7     		b	.L40
+ 732              	.L59:
+ 733 009e 00BF     		.align	2
+ 734              	.L58:
+ 735 00a0 00000000 		.word	.LANCHOR0
+ 736              		.cfi_endproc
+ 737              	.LFE1193:
+ 739              		.section	.text.dec_lock,"ax",%progbits
+ 740              		.align	1
+ 741              		.syntax unified
+ 742              		.thumb
+ 743              		.thumb_func
+ 744              		.fpu fpv5-d16
+ 746              	dec_lock:
+ 747              	.LVL70:
+ 748              	.LFB1194:
+ 837:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 838:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 839:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 840:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dec_lock (	/* Decrement object open counter */
+ 841:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i			/* Semaphore index (1..) */
+ 842:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ 843:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 749              		.loc 1 843 1 is_stmt 1 view -0
+ 750              		.cfi_startproc
+ 751              		@ args = 0, pretend = 0, frame = 0
+ 752              		@ frame_needed = 0, uses_anonymous_args = 0
+ 753              		@ link register save eliminated.
+ 844:Middlewares/Third_Party/FatFs/src/ff.c **** 	WORD n;
+ 754              		.loc 1 844 2 view .LVU214
+ 845:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 755              		.loc 1 845 2 view .LVU215
+ 846:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 847:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 848:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (--i < _FS_LOCK) {	/* Shift index number origin from 0 */
+ 756              		.loc 1 848 2 view .LVU216
+ 757              		.loc 1 848 5 is_stmt 0 view .LVU217
+ 758 0000 0138     		subs	r0, r0, #1
+ 759              	.LVL71:
+ 760              		.loc 1 848 5 view .LVU218
+ 761 0002 0128     		cmp	r0, #1
+ 762 0004 15D8     		bhi	.L63
+ 849:Middlewares/Third_Party/FatFs/src/ff.c **** 		n = Files[i].ctr;
+ 763              		.loc 1 849 3 is_stmt 1 view .LVU219
+ 764              		.loc 1 849 5 is_stmt 0 view .LVU220
+ 765 0006 0D4B     		ldr	r3, .L66
+ 766 0008 03EB0013 		add	r3, r3, r0, lsl #4
+ 767 000c 9B89     		ldrh	r3, [r3, #12]
+ 768              	.LVL72:
+ 850:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (n == 0x100) n = 0;		/* If write mode open, delete the entry */
+ 769              		.loc 1 850 3 is_stmt 1 view .LVU221
+ 770              		.loc 1 850 6 is_stmt 0 view .LVU222
+ 771 000e B3F5807F 		cmp	r3, #256
+ 772 0012 03D0     		beq	.L64
+ 851:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (n > 0) n--;				/* Decrement read mode open count */
+ 773              		.loc 1 851 3 is_stmt 1 view .LVU223
+ARM GAS  /tmp/cc5lWXRL.s 			page 30
+
+
+ 774              		.loc 1 851 6 is_stmt 0 view .LVU224
+ 775 0014 1BB1     		cbz	r3, .L62
+ 776              		.loc 1 851 14 is_stmt 1 discriminator 1 view .LVU225
+ 777              		.loc 1 851 15 is_stmt 0 discriminator 1 view .LVU226
+ 778 0016 013B     		subs	r3, r3, #1
+ 779              	.LVL73:
+ 780              		.loc 1 851 15 discriminator 1 view .LVU227
+ 781 0018 9BB2     		uxth	r3, r3
+ 782              	.LVL74:
+ 783              		.loc 1 851 15 discriminator 1 view .LVU228
+ 784 001a 00E0     		b	.L62
+ 785              	.L64:
+ 850:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (n == 0x100) n = 0;		/* If write mode open, delete the entry */
+ 786              		.loc 1 850 21 view .LVU229
+ 787 001c 0023     		movs	r3, #0
+ 788              	.LVL75:
+ 789              	.L62:
+ 852:Middlewares/Third_Party/FatFs/src/ff.c **** 		Files[i].ctr = n;
+ 790              		.loc 1 852 3 is_stmt 1 view .LVU230
+ 791              		.loc 1 852 16 is_stmt 0 view .LVU231
+ 792 001e 074A     		ldr	r2, .L66
+ 793 0020 02EB0012 		add	r2, r2, r0, lsl #4
+ 794 0024 9381     		strh	r3, [r2, #12]	@ movhi
+ 853:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (n == 0) Files[i].fs = 0;	/* Delete the entry if open count gets zero */
+ 795              		.loc 1 853 3 is_stmt 1 view .LVU232
+ 796              		.loc 1 853 6 is_stmt 0 view .LVU233
+ 797 0026 33B9     		cbnz	r3, .L65
+ 798              		.loc 1 853 15 is_stmt 1 discriminator 1 view .LVU234
+ 799              		.loc 1 853 27 is_stmt 0 discriminator 1 view .LVU235
+ 800 0028 0301     		lsls	r3, r0, #4
+ 801              	.LVL76:
+ 802              		.loc 1 853 27 discriminator 1 view .LVU236
+ 803 002a 0020     		movs	r0, #0
+ 804              	.LVL77:
+ 805              		.loc 1 853 27 discriminator 1 view .LVU237
+ 806 002c 034A     		ldr	r2, .L66
+ 807              	.LVL78:
+ 808              		.loc 1 853 27 discriminator 1 view .LVU238
+ 809 002e D050     		str	r0, [r2, r3]
+ 810 0030 7047     		bx	lr
+ 811              	.LVL79:
+ 812              	.L63:
+ 854:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = FR_OK;
+ 855:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else {
+ 856:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = FR_INT_ERR;			/* Invalid index nunber */
+ 813              		.loc 1 856 7 view .LVU239
+ 814 0032 0220     		movs	r0, #2
+ 815              	.LVL80:
+ 816              		.loc 1 856 7 view .LVU240
+ 817 0034 7047     		bx	lr
+ 818              	.LVL81:
+ 819              	.L65:
+ 854:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = FR_OK;
+ 820              		.loc 1 854 7 view .LVU241
+ 821 0036 0020     		movs	r0, #0
+ 822              	.LVL82:
+ 857:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ARM GAS  /tmp/cc5lWXRL.s 			page 31
+
+
+ 858:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 823              		.loc 1 858 2 is_stmt 1 view .LVU242
+ 859:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 824              		.loc 1 859 1 is_stmt 0 view .LVU243
+ 825 0038 7047     		bx	lr
+ 826              	.L67:
+ 827 003a 00BF     		.align	2
+ 828              	.L66:
+ 829 003c 00000000 		.word	.LANCHOR0
+ 830              		.cfi_endproc
+ 831              	.LFE1194:
+ 833              		.section	.text.clear_lock,"ax",%progbits
+ 834              		.align	1
+ 835              		.syntax unified
+ 836              		.thumb
+ 837              		.thumb_func
+ 838              		.fpu fpv5-d16
+ 840              	clear_lock:
+ 841              	.LVL83:
+ 842              	.LFB1195:
+ 860:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 861:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 862:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 863:Middlewares/Third_Party/FatFs/src/ff.c **** void clear_lock (	/* Clear lock entries of the volume */
+ 864:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs
+ 865:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ 866:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 843              		.loc 1 866 1 is_stmt 1 view -0
+ 844              		.cfi_startproc
+ 845              		@ args = 0, pretend = 0, frame = 0
+ 846              		@ frame_needed = 0, uses_anonymous_args = 0
+ 847              		@ link register save eliminated.
+ 867:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+ 848              		.loc 1 867 2 view .LVU245
+ 868:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 869:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (i = 0; i < _FS_LOCK; i++) {
+ 849              		.loc 1 869 2 view .LVU246
+ 850              		.loc 1 869 9 is_stmt 0 view .LVU247
+ 851 0000 0023     		movs	r3, #0
+ 852              		.loc 1 869 2 view .LVU248
+ 853 0002 03E0     		b	.L73
+ 854              	.LVL84:
+ 855              	.L80:
+ 856              	.LCFI6:
+ 857              		.cfi_def_cfa_offset 4
+ 858              		.cfi_offset 4, -4
+ 870:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 871:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 872:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 859              		.loc 1 872 1 view .LVU249
+ 860 0004 5DF8044B 		ldr	r4, [sp], #4
+ 861              	.LCFI7:
+ 862              		.cfi_restore 4
+ 863              		.cfi_def_cfa_offset 0
+ 864 0008 7047     		bx	lr
+ 865              	.L79:
+ 869:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ARM GAS  /tmp/cc5lWXRL.s 			page 32
+
+
+ 866              		.loc 1 869 28 is_stmt 1 view .LVU250
+ 869:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 867              		.loc 1 869 29 is_stmt 0 view .LVU251
+ 868 000a 0133     		adds	r3, r3, #1
+ 869              	.LVL85:
+ 870              	.L73:
+ 869:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 871              		.loc 1 869 14 is_stmt 1 view .LVU252
+ 869:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 872              		.loc 1 869 2 is_stmt 0 view .LVU253
+ 873 000c 012B     		cmp	r3, #1
+ 874 000e 11D8     		bhi	.L78
+ 870:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 875              		.loc 1 870 3 is_stmt 1 view .LVU254
+ 870:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 876              		.loc 1 870 15 is_stmt 0 view .LVU255
+ 877 0010 1A01     		lsls	r2, r3, #4
+ 878 0012 0949     		ldr	r1, .L81
+ 879 0014 8A58     		ldr	r2, [r1, r2]
+ 870:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 880              		.loc 1 870 6 view .LVU256
+ 881 0016 8242     		cmp	r2, r0
+ 882 0018 F7D1     		bne	.L79
+ 866:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+ 883              		.loc 1 866 1 view .LVU257
+ 884 001a 10B4     		push	{r4}
+ 885              	.LCFI8:
+ 886              		.cfi_def_cfa_offset 4
+ 887              		.cfi_offset 4, -4
+ 888              	.L74:
+ 870:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 889              		.loc 1 870 26 is_stmt 1 discriminator 1 view .LVU258
+ 870:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 890              		.loc 1 870 38 is_stmt 0 discriminator 1 view .LVU259
+ 891 001c 1A01     		lsls	r2, r3, #4
+ 892 001e 0024     		movs	r4, #0
+ 893 0020 8C50     		str	r4, [r1, r2]
+ 894              	.L70:
+ 869:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 895              		.loc 1 869 28 is_stmt 1 discriminator 2 view .LVU260
+ 869:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 896              		.loc 1 869 29 is_stmt 0 discriminator 2 view .LVU261
+ 897 0022 0133     		adds	r3, r3, #1
+ 898              	.LVL86:
+ 869:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 899              		.loc 1 869 14 is_stmt 1 discriminator 2 view .LVU262
+ 869:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 900              		.loc 1 869 2 is_stmt 0 discriminator 2 view .LVU263
+ 901 0024 012B     		cmp	r3, #1
+ 902 0026 EDD8     		bhi	.L80
+ 870:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 903              		.loc 1 870 3 is_stmt 1 view .LVU264
+ 870:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 904              		.loc 1 870 15 is_stmt 0 view .LVU265
+ 905 0028 1A01     		lsls	r2, r3, #4
+ 906 002a 0349     		ldr	r1, .L81
+ 907 002c 8A58     		ldr	r2, [r1, r2]
+ARM GAS  /tmp/cc5lWXRL.s 			page 33
+
+
+ 870:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 908              		.loc 1 870 6 view .LVU266
+ 909 002e 8242     		cmp	r2, r0
+ 910 0030 F7D1     		bne	.L70
+ 911 0032 F3E7     		b	.L74
+ 912              	.L78:
+ 913              	.LCFI9:
+ 914              		.cfi_def_cfa_offset 0
+ 915              		.cfi_restore 4
+ 870:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (Files[i].fs == fs) Files[i].fs = 0;
+ 916              		.loc 1 870 6 view .LVU267
+ 917 0034 7047     		bx	lr
+ 918              	.L82:
+ 919 0036 00BF     		.align	2
+ 920              	.L81:
+ 921 0038 00000000 		.word	.LANCHOR0
+ 922              		.cfi_endproc
+ 923              	.LFE1195:
+ 925              		.section	.text.clust2sect,"ax",%progbits
+ 926              		.align	1
+ 927              		.syntax unified
+ 928              		.thumb
+ 929              		.thumb_func
+ 930              		.fpu fpv5-d16
+ 932              	clust2sect:
+ 933              	.LVL87:
+ 934              	.LFB1199:
+ 873:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 874:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _FS_LOCK != 0 */
+ 875:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 876:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 877:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 878:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 879:Middlewares/Third_Party/FatFs/src/ff.c **** /* Move/Flush disk access window in the file system object               */
+ 880:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 881:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 882:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 883:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT sync_window (	/* Returns FR_OK or FR_DISK_ERROR */
+ 884:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs			/* File system object */
+ 885:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ 886:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 887:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD wsect;
+ 888:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT nf;
+ 889:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_OK;
+ 890:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 891:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 892:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->wflag) {	/* Write back the sector if it is dirty */
+ 893:Middlewares/Third_Party/FatFs/src/ff.c **** 		wsect = fs->winsect;	/* Current sector number */
+ 894:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) {
+ 895:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_DISK_ERR;
+ 896:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 897:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 0;
+ 898:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (wsect - fs->fatbase < fs->fsize) {		/* Is it in the FAT area? */
+ 899:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
+ 900:Middlewares/Third_Party/FatFs/src/ff.c **** 					wsect += fs->fsize;
+ 901:Middlewares/Third_Party/FatFs/src/ff.c **** 					disk_write(fs->drv, fs->win, wsect, 1);
+ 902:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ARM GAS  /tmp/cc5lWXRL.s 			page 34
+
+
+ 903:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 904:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 905:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 906:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 907:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 908:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 909:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 910:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 911:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 912:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT move_window (	/* Returns FR_OK or FR_DISK_ERROR */
+ 913:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs,			/* File system object */
+ 914:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD sector		/* Sector number to make appearance in the fs->win[] */
+ 915:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ 916:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 917:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_OK;
+ 918:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 919:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 920:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (sector != fs->winsect) {	/* Window offset changed? */
+ 921:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 922:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = sync_window(fs);		/* Write-back changes */
+ 923:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 924:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {			/* Fill sector window with new data */
+ 925:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) {
+ 926:Middlewares/Third_Party/FatFs/src/ff.c **** 				sector = 0xFFFFFFFF;	/* Invalidate window if data is not reliable */
+ 927:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_DISK_ERR;
+ 928:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 929:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->winsect = sector;
+ 930:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 931:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 932:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 933:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 934:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 935:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 936:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 937:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 938:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 939:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 940:Middlewares/Third_Party/FatFs/src/ff.c **** /* Synchronize file system and strage device                             */
+ 941:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 942:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 943:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 944:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT sync_fs (	/* FR_OK:succeeded, !=0:error */
+ 945:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs		/* File system object */
+ 946:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ 947:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 948:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 949:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 950:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 951:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = sync_window(fs);
+ 952:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 953:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Update FSInfo sector if needed */
+ 954:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) {
+ 955:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Create FSInfo structure */
+ 956:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(fs->win, 0, SS(fs));
+ 957:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(fs->win + BS_55AA, 0xAA55);
+ 958:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(fs->win + FSI_LeadSig, 0x41615252);
+ 959:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(fs->win + FSI_StrucSig, 0x61417272);
+ARM GAS  /tmp/cc5lWXRL.s 			page 35
+
+
+ 960:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(fs->win + FSI_Free_Count, fs->free_clst);
+ 961:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(fs->win + FSI_Nxt_Free, fs->last_clst);
+ 962:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Write it into the FSInfo sector */
+ 963:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->winsect = fs->volbase + 1;
+ 964:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(fs->drv, fs->win, fs->winsect, 1);
+ 965:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->fsi_flag = 0;
+ 966:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 967:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Make sure that no pending write process in the physical drive */
+ 968:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR;
+ 969:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 970:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 971:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 972:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 973:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 974:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 975:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 976:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 977:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 978:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 979:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get sector# from cluster#                                             */
+ 980:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 981:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 982:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ 983:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clust2sect (	/* !=0:Sector number, 0:Failed (invalid cluster#) */
+ 984:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs,		/* File system object */
+ 985:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst		/* Cluster# to be converted */
+ 986:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ 987:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 935              		.loc 1 987 1 is_stmt 1 view -0
+ 936              		.cfi_startproc
+ 937              		@ args = 0, pretend = 0, frame = 0
+ 938              		@ frame_needed = 0, uses_anonymous_args = 0
+ 939              		@ link register save eliminated.
+ 988:Middlewares/Third_Party/FatFs/src/ff.c **** 	clst -= 2;
+ 940              		.loc 1 988 2 view .LVU269
+ 941              		.loc 1 988 7 is_stmt 0 view .LVU270
+ 942 0000 0239     		subs	r1, r1, #2
+ 943              	.LVL88:
+ 989:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (clst >= fs->n_fatent - 2) return 0;		/* Invalid cluster# */
+ 944              		.loc 1 989 2 is_stmt 1 view .LVU271
+ 945              		.loc 1 989 16 is_stmt 0 view .LVU272
+ 946 0002 8369     		ldr	r3, [r0, #24]
+ 947              		.loc 1 989 27 view .LVU273
+ 948 0004 023B     		subs	r3, r3, #2
+ 949              		.loc 1 989 5 view .LVU274
+ 950 0006 8B42     		cmp	r3, r1
+ 951 0008 04D9     		bls	.L85
+ 990:Middlewares/Third_Party/FatFs/src/ff.c **** 	return clst * fs->csize + fs->database;
+ 952              		.loc 1 990 2 is_stmt 1 view .LVU275
+ 953              		.loc 1 990 18 is_stmt 0 view .LVU276
+ 954 000a 4389     		ldrh	r3, [r0, #10]
+ 955              		.loc 1 990 30 view .LVU277
+ 956 000c C06A     		ldr	r0, [r0, #44]
+ 957              	.LVL89:
+ 958              		.loc 1 990 26 view .LVU278
+ 959 000e 01FB0300 		mla	r0, r1, r3, r0
+ 960 0012 7047     		bx	lr
+ARM GAS  /tmp/cc5lWXRL.s 			page 36
+
+
+ 961              	.LVL90:
+ 962              	.L85:
+ 989:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (clst >= fs->n_fatent - 2) return 0;		/* Invalid cluster# */
+ 963              		.loc 1 989 39 view .LVU279
+ 964 0014 0020     		movs	r0, #0
+ 965              	.LVL91:
+ 991:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 966              		.loc 1 991 1 view .LVU280
+ 967 0016 7047     		bx	lr
+ 968              		.cfi_endproc
+ 969              	.LFE1199:
+ 971              		.section	.text.clmt_clust,"ax",%progbits
+ 972              		.align	1
+ 973              		.syntax unified
+ 974              		.thumb
+ 975              		.thumb_func
+ 976              		.fpu fpv5-d16
+ 978              	clmt_clust:
+ 979              	.LVL92:
+ 980              	.LFB1204:
+ 992:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 993:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 994:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 995:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 996:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 997:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT access - Read value of a FAT entry                                */
+ 998:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ 999:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1000:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1001:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD get_fat (	/* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */
+1002:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID* obj,	/* Corresponding object */
+1003:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst	/* Cluster number to get the value */
+1004:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1005:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1006:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT wc, bc;
+1007:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD val;
+1008:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = obj->fs;
+1009:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1010:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1011:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (clst < 2 || clst >= fs->n_fatent) {	/* Check if in valid range */
+1012:Middlewares/Third_Party/FatFs/src/ff.c **** 		val = 1;	/* Internal error */
+1013:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1014:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else {
+1015:Middlewares/Third_Party/FatFs/src/ff.c **** 		val = 0xFFFFFFFF;	/* Default value falls on disk error */
+1016:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1017:Middlewares/Third_Party/FatFs/src/ff.c **** 		switch (fs->fs_type) {
+1018:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT12 :
+1019:Middlewares/Third_Party/FatFs/src/ff.c **** 			bc = (UINT)clst; bc += bc / 2;
+1020:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+1021:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc = fs->win[bc++ % SS(fs)];
+1022:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+1023:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc |= fs->win[bc % SS(fs)] << 8;
+1024:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+1025:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+1026:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1027:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT16 :
+1028:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
+ARM GAS  /tmp/cc5lWXRL.s 			page 37
+
+
+1029:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_word(fs->win + clst * 2 % SS(fs));
+1030:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+1031:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1032:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT32 :
+1033:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+1034:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+1035:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+1036:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+1037:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_EXFAT :
+1038:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (obj->objsize) {
+1039:Middlewares/Third_Party/FatFs/src/ff.c **** 				DWORD cofs = clst - obj->sclust;	/* Offset from start cluster */
+1040:Middlewares/Third_Party/FatFs/src/ff.c **** 				DWORD clen = (DWORD)((obj->objsize - 1) / SS(fs)) / fs->csize;	/* Number of clusters - 1 */
+1041:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1042:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (obj->stat == 2) {	/* Is there no valid chain on the FAT? */
+1043:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (cofs <= clen) {
+1044:Middlewares/Third_Party/FatFs/src/ff.c **** 						val = (cofs == clen) ? 0x7FFFFFFF : clst + 1;	/* Generate the value */
+1045:Middlewares/Third_Party/FatFs/src/ff.c **** 						break;
+1046:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+1047:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+1048:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (obj->stat == 3 && cofs < obj->n_cont) {	/* Is it in the 1st fragment? */
+1049:Middlewares/Third_Party/FatFs/src/ff.c **** 					val = clst + 1; 	/* Generate the value */
+1050:Middlewares/Third_Party/FatFs/src/ff.c **** 					break;
+1051:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+1052:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (obj->stat != 2) {	/* Get value from FAT if FAT chain is valid */
+1053:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (obj->n_frag != 0) {	/* Is it on the growing edge? */
+1054:Middlewares/Third_Party/FatFs/src/ff.c **** 						val = 0x7FFFFFFF;	/* Generate EOC */
+1055:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else {
+1056:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+1057:Middlewares/Third_Party/FatFs/src/ff.c **** 						val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF;
+1058:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+1059:Middlewares/Third_Party/FatFs/src/ff.c **** 					break;
+1060:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+1061:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1062:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* go to default */
+1063:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1064:Middlewares/Third_Party/FatFs/src/ff.c **** 		default:
+1065:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = 1;	/* Internal error */
+1066:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1067:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1068:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1069:Middlewares/Third_Party/FatFs/src/ff.c **** 	return val;
+1070:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1071:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1072:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1073:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1074:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1075:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+1076:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1077:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT access - Change value of a FAT entry                              */
+1078:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1079:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1080:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1081:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT put_fat (	/* FR_OK(0):succeeded, !=0:error */
+1082:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs,		/* Corresponding file system object */
+1083:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst,		/* FAT index number (cluster number) to be changed */
+1084:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD val		/* New value to be set to the entry */
+1085:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ARM GAS  /tmp/cc5lWXRL.s 			page 38
+
+
+1086:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1087:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT bc;
+1088:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *p;
+1089:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_INT_ERR;
+1090:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1091:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (clst >= 2 && clst < fs->n_fatent) {	/* Check if in valid range */
+1092:Middlewares/Third_Party/FatFs/src/ff.c **** 		switch (fs->fs_type) {
+1093:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT12 :	/* Bitfield items */
+1094:Middlewares/Third_Party/FatFs/src/ff.c **** 			bc = (UINT)clst; bc += bc / 2;
+1095:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+1096:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+1097:Middlewares/Third_Party/FatFs/src/ff.c **** 			p = fs->win + bc++ % SS(fs);
+1098:Middlewares/Third_Party/FatFs/src/ff.c **** 			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+1099:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+1100:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+1101:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+1102:Middlewares/Third_Party/FatFs/src/ff.c **** 			p = fs->win + bc % SS(fs);
+1103:Middlewares/Third_Party/FatFs/src/ff.c **** 			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+1104:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+1105:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+1106:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1107:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT16 :	/* WORD aligned items */
+1108:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+1109:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+1110:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(fs->win + clst * 2 % SS(fs), (WORD)val);
+1111:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+1112:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+1113:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1114:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT32 :	/* DWORD aligned items */
+1115:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+1116:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_EXFAT :
+1117:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1118:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+1119:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+1120:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+1121:Middlewares/Third_Party/FatFs/src/ff.c **** 				val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000);
+1122:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1123:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(fs->win + clst * 4 % SS(fs), val);
+1124:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+1125:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+1126:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1127:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1128:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+1129:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1130:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1131:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */
+1132:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1133:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1134:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1135:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1136:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY
+1137:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1138:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Accessing FAT and Allocation Bitmap                            */
+1139:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1140:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1141:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------*/
+1142:Middlewares/Third_Party/FatFs/src/ff.c **** /* Find a contiguous free cluster block */
+ARM GAS  /tmp/cc5lWXRL.s 			page 39
+
+
+1143:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------*/
+1144:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1145:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1146:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD find_bitmap (	/* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */
+1147:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs,	/* File system object */
+1148:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst,	/* Cluster number to scan from */
+1149:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD ncl	/* Number of contiguous clusters to find (1..) */
+1150:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1151:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1152:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE bm, bv;
+1153:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+1154:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD val, scl, ctr;
+1155:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1156:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1157:Middlewares/Third_Party/FatFs/src/ff.c **** 	clst -= 2;	/* The first bit in the bitmap corresponds to cluster #2 */
+1158:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (clst >= fs->n_fatent - 2) clst = 0;
+1159:Middlewares/Third_Party/FatFs/src/ff.c **** 	scl = val = clst; ctr = 0;
+1160:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (;;) {
+1161:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (move_window(fs, fs->database + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF;	/* (assuming bi
+1162:Middlewares/Third_Party/FatFs/src/ff.c **** 		i = val / 8 % SS(fs); bm = 1 << (val % 8);
+1163:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+1164:Middlewares/Third_Party/FatFs/src/ff.c **** 			do {
+1165:Middlewares/Third_Party/FatFs/src/ff.c **** 				bv = fs->win[i] & bm; bm <<= 1;		/* Get bit value */
+1166:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (++val >= fs->n_fatent - 2) {	/* Next cluster (with wrap-around) */
+1167:Middlewares/Third_Party/FatFs/src/ff.c **** 					val = 0; bm = 0; i = SS(fs);
+1168:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+1169:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!bv) {	/* Is it a free cluster? */
+1170:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (++ctr == ncl) return scl + 2;	/* Check if run length is sufficient for required */
+1171:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+1172:Middlewares/Third_Party/FatFs/src/ff.c **** 					scl = val; ctr = 0;		/* Encountered a cluster in-use, restart to scan */
+1173:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+1174:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (val == clst) return 0;	/* All cluster scanned? */
+1175:Middlewares/Third_Party/FatFs/src/ff.c **** 			} while (bm);
+1176:Middlewares/Third_Party/FatFs/src/ff.c **** 			bm = 1;
+1177:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (++i < SS(fs));
+1178:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1179:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1180:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1181:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1182:Middlewares/Third_Party/FatFs/src/ff.c **** /*----------------------------------------*/
+1183:Middlewares/Third_Party/FatFs/src/ff.c **** /* Set/Clear a block of allocation bitmap */
+1184:Middlewares/Third_Party/FatFs/src/ff.c **** /*----------------------------------------*/
+1185:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1186:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1187:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT change_bitmap (
+1188:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs,	/* File system object */
+1189:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst,	/* Cluster number to change from */
+1190:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD ncl,	/* Number of clusters to be changed */
+1191:Middlewares/Third_Party/FatFs/src/ff.c **** 	int bv		/* bit value to be set (0 or 1) */
+1192:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1193:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1194:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE bm;
+1195:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+1196:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD sect;
+1197:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1198:Middlewares/Third_Party/FatFs/src/ff.c **** 	clst -= 2;	/* The first bit corresponds to cluster #2 */
+1199:Middlewares/Third_Party/FatFs/src/ff.c **** 	sect = fs->database + clst / 8 / SS(fs);	/* Sector address (assuming bitmap is located top of the 
+ARM GAS  /tmp/cc5lWXRL.s 			page 40
+
+
+1200:Middlewares/Third_Party/FatFs/src/ff.c **** 	i = clst / 8 % SS(fs);						/* Byte offset in the sector */
+1201:Middlewares/Third_Party/FatFs/src/ff.c **** 	bm = 1 << (clst % 8);						/* Bit mask in the byte */
+1202:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (;;) {
+1203:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR;
+1204:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+1205:Middlewares/Third_Party/FatFs/src/ff.c **** 			do {
+1206:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR;	/* Is the bit expected value? */
+1207:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->win[i] ^= bm;	/* Flip the bit */
+1208:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->wflag = 1;
+1209:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (--ncl == 0) return FR_OK;	/* All bits processed? */
+1210:Middlewares/Third_Party/FatFs/src/ff.c **** 			} while (bm <<= 1);		/* Next bit */
+1211:Middlewares/Third_Party/FatFs/src/ff.c **** 			bm = 1;
+1212:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (++i < SS(fs));		/* Next byte */
+1213:Middlewares/Third_Party/FatFs/src/ff.c **** 		i = 0;
+1214:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1215:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1216:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1217:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1218:Middlewares/Third_Party/FatFs/src/ff.c **** /*---------------------------------------------*/
+1219:Middlewares/Third_Party/FatFs/src/ff.c **** /* Fill the first fragment of the FAT chain    */
+1220:Middlewares/Third_Party/FatFs/src/ff.c **** /*---------------------------------------------*/
+1221:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1222:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1223:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT fill_first_frag (
+1224:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID* obj	/* Pointer to the corresponding object */
+1225:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1226:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1227:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+1228:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD cl, n;
+1229:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1230:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (obj->stat == 3) {	/* Has the object been changed 'fragmented'? */
+1231:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) {	/* Create cluster chain on the FAT */
+1232:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = put_fat(obj->fs, cl, cl + 1);
+1233:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) return res;
+1234:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1235:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->stat = 0;	/* Change status 'FAT chain is valid' */
+1236:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1237:Middlewares/Third_Party/FatFs/src/ff.c **** 	return FR_OK;
+1238:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1239:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1240:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1241:Middlewares/Third_Party/FatFs/src/ff.c **** /*---------------------------------------------*/
+1242:Middlewares/Third_Party/FatFs/src/ff.c **** /* Fill the last fragment of the FAT chain     */
+1243:Middlewares/Third_Party/FatFs/src/ff.c **** /*---------------------------------------------*/
+1244:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1245:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1246:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT fill_last_frag (
+1247:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID* obj,	/* Pointer to the corresponding object */
+1248:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD lcl,	/* Last cluster of the fragment */
+1249:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD term	/* Value to set the last FAT entry */
+1250:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1251:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1252:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+1253:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1254:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (obj->n_frag > 0) {	/* Create the last chain on the FAT */
+1255:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term);
+1256:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) return res;
+ARM GAS  /tmp/cc5lWXRL.s 			page 41
+
+
+1257:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->n_frag--;
+1258:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1259:Middlewares/Third_Party/FatFs/src/ff.c **** 	return FR_OK;
+1260:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1261:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1262:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _FS_EXFAT && !_FS_READONLY */
+1263:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1264:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1265:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1266:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+1267:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1268:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT handling - Remove a cluster chain                                 */
+1269:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1270:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1271:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT remove_chain (	/* FR_OK(0):succeeded, !=0:error */
+1272:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID* obj,			/* Corresponding object */
+1273:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst,			/* Cluster to remove a chain from */
+1274:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD pclst			/* Previous cluster of clst (0:an entire chain) */
+1275:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1276:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1277:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_OK;
+1278:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD nxt;
+1279:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = obj->fs;
+1280:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT || _USE_TRIM
+1281:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD scl = clst, ecl = clst;
+1282:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1283:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM
+1284:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD rt[2];
+1285:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1286:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1287:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Check if in valid range */
+1288:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1289:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Mark the previous cluster 'EOC' on the FAT if it exists */
+1290:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (pclst && (!_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) {
+1291:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = put_fat(fs, pclst, 0xFFFFFFFF);
+1292:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) return res;
+1293:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1294:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1295:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Remove the chain */
+1296:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+1297:Middlewares/Third_Party/FatFs/src/ff.c **** 		nxt = get_fat(obj, clst);			/* Get cluster status */
+1298:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 0) break;				/* Empty cluster? */
+1299:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 1) return FR_INT_ERR;	/* Internal error? */
+1300:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error? */
+1301:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+1302:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = put_fat(fs, clst, 0);		/* Mark the cluster 'free' on the FAT */
+1303:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) return res;
+1304:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1305:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->free_clst < fs->n_fatent - 2) {	/* Update FSINFO */
+1306:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->free_clst++;
+1307:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->fsi_flag |= 1;
+1308:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1309:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT || _USE_TRIM
+1310:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
+1311:Middlewares/Third_Party/FatFs/src/ff.c **** 			ecl = nxt;
+1312:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {				/* End of contiguous cluster block */
+1313:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ARM GAS  /tmp/cc5lWXRL.s 			page 42
+
+
+1314:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->fs_type == FS_EXFAT) {
+1315:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = change_bitmap(fs, scl, ecl - scl + 1, 0);	/* Mark the cluster block 'free' on the bitmap 
+1316:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res != FR_OK) return res;
+1317:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1318:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1319:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM
+1320:Middlewares/Third_Party/FatFs/src/ff.c **** 			rt[0] = clust2sect(fs, scl);					/* Start sector */
+1321:Middlewares/Third_Party/FatFs/src/ff.c **** 			rt[1] = clust2sect(fs, ecl) + fs->csize - 1;	/* End sector */
+1322:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_ioctl(fs->drv, CTRL_TRIM, rt);				/* Inform device the block can be erased */
+1323:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1324:Middlewares/Third_Party/FatFs/src/ff.c **** 			scl = ecl = nxt;
+1325:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1326:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1327:Middlewares/Third_Party/FatFs/src/ff.c **** 		clst = nxt;					/* Next cluster */
+1328:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (clst < fs->n_fatent);	/* Repeat while not the last link */
+1329:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1330:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+1331:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type == FS_EXFAT) {
+1332:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (pclst == 0) {	/* Does the object have no chain? */
+1333:Middlewares/Third_Party/FatFs/src/ff.c **** 			obj->stat = 0;		/* Change the object status 'initial' */
+1334:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+1335:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) {	/* Did the c
+1336:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->stat = 2;	/* Change the object status 'contiguous' */
+1337:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1338:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1339:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1340:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1341:Middlewares/Third_Party/FatFs/src/ff.c **** 	return FR_OK;
+1342:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1343:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1344:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1345:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1346:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1347:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1348:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT handling - Stretch a chain or Create a new chain                  */
+1349:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1350:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1351:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD create_chain (	/* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster
+1352:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID* obj,			/* Corresponding object */
+1353:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst			/* Cluster# to stretch, 0:Create a new chain */
+1354:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1355:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1356:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD cs, ncl, scl;
+1357:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+1358:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = obj->fs;
+1359:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1360:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1361:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (clst == 0) {	/* Create a new chain */
+1362:Middlewares/Third_Party/FatFs/src/ff.c **** 		scl = fs->last_clst;				/* Get suggested cluster to start from */
+1363:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (scl == 0 || scl >= fs->n_fatent) scl = 1;
+1364:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1365:Middlewares/Third_Party/FatFs/src/ff.c **** 	else {				/* Stretch current chain */
+1366:Middlewares/Third_Party/FatFs/src/ff.c **** 		cs = get_fat(obj, clst);			/* Check the cluster status */
+1367:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cs < 2) return 1;				/* Invalid FAT value */
+1368:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cs == 0xFFFFFFFF) return cs;	/* A disk error occurred */
+1369:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cs < fs->n_fatent) return cs;	/* It is already followed by next cluster */
+1370:Middlewares/Third_Party/FatFs/src/ff.c **** 		scl = clst;
+ARM GAS  /tmp/cc5lWXRL.s 			page 43
+
+
+1371:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1372:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1373:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+1374:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+1375:Middlewares/Third_Party/FatFs/src/ff.c **** 		ncl = find_bitmap(fs, scl, 1);				/* Find a free cluster */
+1376:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl;	/* No free cluster or hard error? */
+1377:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = change_bitmap(fs, ncl, 1, 1);			/* Mark the cluster 'in use' */
+1378:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_INT_ERR) return 1;
+1379:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_DISK_ERR) return 0xFFFFFFFF;
+1380:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (clst == 0) {							/* Is it a new chain? */
+1381:Middlewares/Third_Party/FatFs/src/ff.c **** 			obj->stat = 2;							/* Set status 'contiguous' */
+1382:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {									/* It is a stretched chain */
+1383:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (obj->stat == 2 && ncl != scl + 1) {	/* Is the chain got fragmented? */
+1384:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->n_cont = scl - obj->sclust;	/* Set size of the contiguous part */
+1385:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->stat = 3;						/* Change status 'just fragmented' */
+1386:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1387:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1388:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (obj->stat != 2) {	/* Is the file non-contiguous? */
+1389:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl == clst + 1) {	/* Is the cluster next to previous one? */
+1390:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2;	/* Increment size of last framgent */
+1391:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {				/* New fragment */
+1392:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (obj->n_frag == 0) obj->n_frag = 1;
+1393:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = fill_last_frag(obj, clst, ncl);	/* Fill last fragment on the FAT and link it to new one *
+1394:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) obj->n_frag = 1;
+1395:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1396:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1397:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else
+1398:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1399:Middlewares/Third_Party/FatFs/src/ff.c **** 	{	/* On the FAT12/16/32 volume */
+1400:Middlewares/Third_Party/FatFs/src/ff.c **** 		ncl = scl;	/* Start cluster */
+1401:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (;;) {
+1402:Middlewares/Third_Party/FatFs/src/ff.c **** 			ncl++;							/* Next cluster */
+1403:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl >= fs->n_fatent) {		/* Check wrap-around */
+1404:Middlewares/Third_Party/FatFs/src/ff.c **** 				ncl = 2;
+1405:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (ncl > scl) return 0;	/* No free cluster */
+1406:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1407:Middlewares/Third_Party/FatFs/src/ff.c **** 			cs = get_fat(obj, ncl);			/* Get the cluster status */
+1408:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cs == 0) break;				/* Found a free cluster */
+1409:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cs == 1 || cs == 0xFFFFFFFF) return cs;	/* An error occurred */
+1410:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl == scl) return 0;		/* No free cluster */
+1411:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1412:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = put_fat(fs, ncl, 0xFFFFFFFF);	/* Mark the new cluster 'EOC' */
+1413:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK && clst != 0) {
+1414:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = put_fat(fs, clst, ncl);	/* Link it from the previous one if needed */
+1415:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1416:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1417:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1418:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {			/* Update FSINFO if function succeeded. */
+1419:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->last_clst = ncl;
+1420:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--;
+1421:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag |= 1;
+1422:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else {
+1423:Middlewares/Third_Party/FatFs/src/ff.c **** 		ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;	/* Failed. Generate error status */
+1424:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1425:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1426:Middlewares/Third_Party/FatFs/src/ff.c **** 	return ncl;		/* Return new cluster number or error status */
+1427:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ARM GAS  /tmp/cc5lWXRL.s 			page 44
+
+
+1428:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */
+1430:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1431:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1432:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1433:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1434:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK
+1435:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1436:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT handling - Convert offset into cluster with link map table        */
+1437:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1438:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1439:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1440:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clmt_clust (	/* <2:Error, >=2:Cluster number */
+1441:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp,		/* Pointer to the file object */
+1442:Middlewares/Third_Party/FatFs/src/ff.c **** 	FSIZE_t ofs		/* File offset to be converted to cluster# */
+1443:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1444:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 981              		.loc 1 1444 1 is_stmt 1 view -0
+ 982              		.cfi_startproc
+ 983              		@ args = 0, pretend = 0, frame = 0
+ 984              		@ frame_needed = 0, uses_anonymous_args = 0
+ 985              		@ link register save eliminated.
+1445:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD cl, ncl, *tbl;
+ 986              		.loc 1 1445 2 view .LVU282
+1446:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = fp->obj.fs;
+ 987              		.loc 1 1446 2 view .LVU283
+ 988              		.loc 1 1446 9 is_stmt 0 view .LVU284
+ 989 0000 0268     		ldr	r2, [r0]
+ 990              	.LVL93:
+1447:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1448:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1449:Middlewares/Third_Party/FatFs/src/ff.c **** 	tbl = fp->cltbl + 1;	/* Top of CLMT */
+ 991              		.loc 1 1449 2 is_stmt 1 view .LVU285
+ 992              		.loc 1 1449 10 is_stmt 0 view .LVU286
+ 993 0002 C36A     		ldr	r3, [r0, #44]
+ 994              		.loc 1 1449 6 view .LVU287
+ 995 0004 0433     		adds	r3, r3, #4
+ 996              	.LVL94:
+1450:Middlewares/Third_Party/FatFs/src/ff.c **** 	cl = (DWORD)(ofs / SS(fs) / fs->csize);	/* Cluster order from top of the file */
+ 997              		.loc 1 1450 2 is_stmt 1 view .LVU288
+ 998              		.loc 1 1450 21 is_stmt 0 view .LVU289
+ 999 0006 9089     		ldrh	r0, [r2, #12]
+ 1000              	.LVL95:
+ 1001              		.loc 1 1450 19 view .LVU290
+ 1002 0008 B1FBF0F1 		udiv	r1, r1, r0
+ 1003              	.LVL96:
+ 1004              		.loc 1 1450 32 view .LVU291
+ 1005 000c 5289     		ldrh	r2, [r2, #10]
+ 1006              	.LVL97:
+ 1007              		.loc 1 1450 5 view .LVU292
+ 1008 000e B1FBF2F1 		udiv	r1, r1, r2
+ 1009              	.LVL98:
+ 1010              		.loc 1 1450 5 view .LVU293
+ 1011 0012 01E0     		b	.L89
+ 1012              	.LVL99:
+ 1013              	.L90:
+1451:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (;;) {
+ARM GAS  /tmp/cc5lWXRL.s 			page 45
+
+
+1452:Middlewares/Third_Party/FatFs/src/ff.c **** 		ncl = *tbl++;			/* Number of cluters in the fragment */
+1453:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ncl == 0) return 0;	/* End of table? (error) */
+1454:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cl < ncl) break;	/* In this fragment? */
+1455:Middlewares/Third_Party/FatFs/src/ff.c **** 		cl -= ncl; tbl++;		/* Next fragment */
+ 1014              		.loc 1 1455 3 is_stmt 1 view .LVU294
+ 1015              		.loc 1 1455 6 is_stmt 0 view .LVU295
+ 1016 0014 091A     		subs	r1, r1, r0
+ 1017              	.LVL100:
+ 1018              		.loc 1 1455 14 is_stmt 1 view .LVU296
+ 1019              		.loc 1 1455 17 is_stmt 0 view .LVU297
+ 1020 0016 0833     		adds	r3, r3, #8
+ 1021              	.LVL101:
+1451:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (;;) {
+ 1022              		.loc 1 1451 8 is_stmt 1 view .LVU298
+ 1023              	.L89:
+1451:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (;;) {
+ 1024              		.loc 1 1451 2 view .LVU299
+1452:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ncl == 0) return 0;	/* End of table? (error) */
+ 1025              		.loc 1 1452 3 view .LVU300
+1452:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ncl == 0) return 0;	/* End of table? (error) */
+ 1026              		.loc 1 1452 7 is_stmt 0 view .LVU301
+ 1027 0018 1868     		ldr	r0, [r3]
+ 1028              	.LVL102:
+1453:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cl < ncl) break;	/* In this fragment? */
+ 1029              		.loc 1 1453 3 is_stmt 1 view .LVU302
+1453:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cl < ncl) break;	/* In this fragment? */
+ 1030              		.loc 1 1453 6 is_stmt 0 view .LVU303
+ 1031 001a 18B1     		cbz	r0, .L86
+1454:Middlewares/Third_Party/FatFs/src/ff.c **** 		cl -= ncl; tbl++;		/* Next fragment */
+ 1032              		.loc 1 1454 3 is_stmt 1 view .LVU304
+1454:Middlewares/Third_Party/FatFs/src/ff.c **** 		cl -= ncl; tbl++;		/* Next fragment */
+ 1033              		.loc 1 1454 6 is_stmt 0 view .LVU305
+ 1034 001c 8142     		cmp	r1, r0
+ 1035 001e F9D2     		bcs	.L90
+1456:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1457:Middlewares/Third_Party/FatFs/src/ff.c **** 	return cl + *tbl;	/* Return the cluster number */
+ 1036              		.loc 1 1457 2 is_stmt 1 view .LVU306
+ 1037              		.loc 1 1457 14 is_stmt 0 view .LVU307
+ 1038 0020 5868     		ldr	r0, [r3, #4]
+ 1039              	.LVL103:
+ 1040              		.loc 1 1457 12 view .LVU308
+ 1041 0022 0844     		add	r0, r0, r1
+ 1042              	.L86:
+1458:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 1043              		.loc 1 1458 1 view .LVU309
+ 1044 0024 7047     		bx	lr
+ 1045              		.cfi_endproc
+ 1046              	.LFE1204:
+ 1048              		.section	.text.ld_clust,"ax",%progbits
+ 1049              		.align	1
+ 1050              		.syntax unified
+ 1051              		.thumb
+ 1052              		.thumb_func
+ 1053              		.fpu fpv5-d16
+ 1055              	ld_clust:
+ 1056              	.LVL104:
+ 1057              	.LFB1208:
+ARM GAS  /tmp/cc5lWXRL.s 			page 46
+
+
+1459:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1460:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _USE_FASTSEEK */
+1461:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1462:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1463:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1464:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1465:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1466:Middlewares/Third_Party/FatFs/src/ff.c **** /* Directory handling - Set directory index                              */
+1467:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1468:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1469:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1470:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_sdi (	/* FR_OK(0):succeeded, !=0:error */
+1471:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,		/* Pointer to directory object */
+1472:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD ofs		/* Offset of directory table */
+1473:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1474:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1475:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD csz, clst;
+1476:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+1477:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1478:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1479:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE)
+1480:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_INT_ERR;
+1481:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1482:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->dptr = ofs;				/* Set current offset */
+1483:Middlewares/Third_Party/FatFs/src/ff.c **** 	clst = dp->obj.sclust;		/* Table start cluster (0:root) */
+1484:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (clst == 0 && fs->fs_type >= FS_FAT32) {	/* Replace cluster# 0 with root cluster# */
+1485:Middlewares/Third_Party/FatFs/src/ff.c **** 		clst = fs->dirbase;
+1486:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_EXFAT) dp->obj.stat = 0;	/* exFAT: Root dir has an FAT chain */
+1487:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1488:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1489:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (clst == 0) {	/* Static table (root-directory in FAT12/16) */
+1490:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs / SZDIRE >= fs->n_rootdir)	return FR_INT_ERR;	/* Is index out of range? */
+1491:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect = fs->dirbase;
+1492:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1493:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else {			/* Dynamic table (sub-directory or root-directory in FAT32+) */
+1494:Middlewares/Third_Party/FatFs/src/ff.c **** 		csz = (DWORD)fs->csize * SS(fs);	/* Bytes per cluster */
+1495:Middlewares/Third_Party/FatFs/src/ff.c **** 		while (ofs >= csz) {				/* Follow cluster chain */
+1496:Middlewares/Third_Party/FatFs/src/ff.c **** 			clst = get_fat(&dp->obj, clst);				/* Get next cluster */
+1497:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+1498:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Reached to end of table or internal 
+1499:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs -= csz;
+1500:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1501:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect = clust2sect(fs, clst);
+1502:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1503:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->clust = clst;					/* Current cluster# */
+1504:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!dp->sect) return FR_INT_ERR;
+1505:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->sect += ofs / SS(fs);			/* Sector# of the directory entry */
+1506:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->dir = fs->win + (ofs % SS(fs));	/* Pointer to the entry in the win[] */
+1507:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1508:Middlewares/Third_Party/FatFs/src/ff.c **** 	return FR_OK;
+1509:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1510:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1511:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1512:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1513:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1514:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1515:Middlewares/Third_Party/FatFs/src/ff.c **** /* Directory handling - Move directory table index next                  */
+ARM GAS  /tmp/cc5lWXRL.s 			page 47
+
+
+1516:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1517:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1518:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1519:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_next (	/* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
+1520:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,		/* Pointer to the directory object */
+1521:Middlewares/Third_Party/FatFs/src/ff.c **** 	int stretch		/* 0: Do not stretch table, 1: Stretch table if needed */
+1522:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1523:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1524:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD ofs, clst;
+1525:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+1526:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+1527:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT n;
+1528:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1529:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1530:Middlewares/Third_Party/FatFs/src/ff.c **** 	ofs = dp->dptr + SZDIRE;	/* Next entry */
+1531:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) re
+1532:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1533:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (ofs % SS(fs) == 0) {	/* Sector changed? */
+1534:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect++;				/* Next sector */
+1535:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1536:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!dp->clust) {		/* Static table */
+1537:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ofs / SZDIRE >= fs->n_rootdir) {	/* Report EOT if it reached end of static table */
+1538:Middlewares/Third_Party/FatFs/src/ff.c **** 				dp->sect = 0; return FR_NO_FILE;
+1539:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1540:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1541:Middlewares/Third_Party/FatFs/src/ff.c **** 		else {					/* Dynamic table */
+1542:Middlewares/Third_Party/FatFs/src/ff.c **** 			if ((ofs / SS(fs) & (fs->csize - 1)) == 0) {		/* Cluster changed? */
+1543:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = get_fat(&dp->obj, dp->clust);			/* Get next cluster */
+1544:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst <= 1) return FR_INT_ERR;				/* Internal error */
+1545:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;		/* Disk error */
+1546:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst >= fs->n_fatent) {						/* Reached end of dynamic table */
+1547:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+1548:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!stretch) {								/* If no stretch, report EOT */
+1549:Middlewares/Third_Party/FatFs/src/ff.c **** 						dp->sect = 0; return FR_NO_FILE;
+1550:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+1551:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = create_chain(&dp->obj, dp->clust);	/* Allocate a cluster */
+1552:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0) return FR_DENIED;			/* No free cluster */
+1553:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 1) return FR_INT_ERR;			/* Internal error */
+1554:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+1555:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Clean-up the stretched table */
+1556:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (_FS_EXFAT) dp->obj.stat |= 4;			/* The directory needs to be updated */
+1557:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (sync_window(fs) != FR_OK) return FR_DISK_ERR;	/* Flush disk access window */
+1558:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_set(fs->win, 0, SS(fs));				/* Clear window buffer */
+1559:Middlewares/Third_Party/FatFs/src/ff.c **** 					for (n = 0, fs->winsect = clust2sect(fs, clst); n < fs->csize; n++, fs->winsect++) {	/* Fill t
+1560:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+1561:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (sync_window(fs) != FR_OK) return FR_DISK_ERR;
+1562:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+1563:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->winsect -= n;							/* Restore window offset */
+1564:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+1565:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!stretch) dp->sect = 0;					/* (this line is to suppress compiler warning) */
+1566:Middlewares/Third_Party/FatFs/src/ff.c **** 					dp->sect = 0; return FR_NO_FILE;			/* Report EOT */
+1567:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+1569:Middlewares/Third_Party/FatFs/src/ff.c **** 				dp->clust = clst;		/* Initialize data for new cluster */
+1570:Middlewares/Third_Party/FatFs/src/ff.c **** 				dp->sect = clust2sect(fs, clst);
+1571:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1572:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ARM GAS  /tmp/cc5lWXRL.s 			page 48
+
+
+1573:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1574:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->dptr = ofs;						/* Current entry */
+1575:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->dir = fs->win + ofs % SS(fs);	/* Pointer to the entry in the win[] */
+1576:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1577:Middlewares/Third_Party/FatFs/src/ff.c **** 	return FR_OK;
+1578:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1579:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1580:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1581:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1582:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1583:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+1584:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1585:Middlewares/Third_Party/FatFs/src/ff.c **** /* Directory handling - Reserve a block of directory entries             */
+1586:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1587:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1588:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1589:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_alloc (	/* FR_OK(0):succeeded, !=0:error */
+1590:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,		/* Pointer to the directory object */
+1591:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT nent		/* Number of contiguous entries to allocate */
+1592:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1593:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1594:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+1595:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT n;
+1596:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+1597:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1598:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1599:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = dir_sdi(dp, 0);
+1600:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+1601:Middlewares/Third_Party/FatFs/src/ff.c **** 		n = 0;
+1602:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+1603:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, dp->sect);
+1604:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+1605:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+1606:Middlewares/Third_Party/FatFs/src/ff.c **** 			if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name
+1607:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+1608:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) {
+1609:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1610:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (++n == nent) break;	/* A block of contiguous free entries is found */
+1611:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+1612:Middlewares/Third_Party/FatFs/src/ff.c **** 				n = 0;					/* Not a blank entry. Restart to search */
+1613:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1614:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dir_next(dp, 1);
+1615:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (res == FR_OK);	/* Next entry with table stretch enabled */
+1616:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1617:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1618:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_NO_FILE) res = FR_DENIED;	/* No directory entry to allocate */
+1619:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+1620:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1621:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1622:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* !_FS_READONLY */
+1623:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1624:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1625:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1626:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1627:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1628:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT: Directory handling - Load/Store start cluster number             */
+1629:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ARM GAS  /tmp/cc5lWXRL.s 			page 49
+
+
+1630:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1631:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1632:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ld_clust (	/* Returns the top cluster value of the SFN entry */
+1633:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs,		/* Pointer to the fs object */
+1634:Middlewares/Third_Party/FatFs/src/ff.c **** 	const BYTE* dir	/* Pointer to the key entry */
+1635:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1636:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 1058              		.loc 1 1636 1 is_stmt 1 view -0
+ 1059              		.cfi_startproc
+ 1060              		@ args = 0, pretend = 0, frame = 0
+ 1061              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1062              		.loc 1 1636 1 is_stmt 0 view .LVU311
+ 1063 0000 70B5     		push	{r4, r5, r6, lr}
+ 1064              	.LCFI10:
+ 1065              		.cfi_def_cfa_offset 16
+ 1066              		.cfi_offset 4, -16
+ 1067              		.cfi_offset 5, -12
+ 1068              		.cfi_offset 6, -8
+ 1069              		.cfi_offset 14, -4
+ 1070 0002 0646     		mov	r6, r0
+ 1071 0004 0D46     		mov	r5, r1
+1637:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD cl;
+ 1072              		.loc 1 1637 2 is_stmt 1 view .LVU312
+1638:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1639:Middlewares/Third_Party/FatFs/src/ff.c **** 	cl = ld_word(dir + DIR_FstClusLO);
+ 1073              		.loc 1 1639 2 view .LVU313
+ 1074              		.loc 1 1639 7 is_stmt 0 view .LVU314
+ 1075 0006 01F11A00 		add	r0, r1, #26
+ 1076              	.LVL105:
+ 1077              		.loc 1 1639 7 view .LVU315
+ 1078 000a FFF7FEFF 		bl	ld_word
+ 1079              	.LVL106:
+1640:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type == FS_FAT32) {
+ 1080              		.loc 1 1640 2 is_stmt 1 view .LVU316
+ 1081              		.loc 1 1640 8 is_stmt 0 view .LVU317
+ 1082 000e 3378     		ldrb	r3, [r6]	@ zero_extendqisi2
+ 1083              		.loc 1 1640 5 view .LVU318
+ 1084 0010 032B     		cmp	r3, #3
+ 1085 0012 00D0     		beq	.L94
+ 1086              	.LVL107:
+ 1087              	.L91:
+1641:Middlewares/Third_Party/FatFs/src/ff.c **** 		cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
+1642:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1643:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1644:Middlewares/Third_Party/FatFs/src/ff.c **** 	return cl;
+1645:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 1088              		.loc 1 1645 1 view .LVU319
+ 1089 0014 70BD     		pop	{r4, r5, r6, pc}
+ 1090              	.LVL108:
+ 1091              	.L94:
+ 1092              		.loc 1 1645 1 view .LVU320
+ 1093 0016 0446     		mov	r4, r0
+1641:Middlewares/Third_Party/FatFs/src/ff.c **** 		cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
+ 1094              		.loc 1 1641 3 is_stmt 1 view .LVU321
+1641:Middlewares/Third_Party/FatFs/src/ff.c **** 		cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
+ 1095              		.loc 1 1641 16 is_stmt 0 view .LVU322
+ 1096 0018 05F11400 		add	r0, r5, #20
+ARM GAS  /tmp/cc5lWXRL.s 			page 50
+
+
+ 1097              	.LVL109:
+1641:Middlewares/Third_Party/FatFs/src/ff.c **** 		cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
+ 1098              		.loc 1 1641 16 view .LVU323
+ 1099 001c FFF7FEFF 		bl	ld_word
+ 1100              	.LVL110:
+1641:Middlewares/Third_Party/FatFs/src/ff.c **** 		cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
+ 1101              		.loc 1 1641 6 view .LVU324
+ 1102 0020 44EA0040 		orr	r0, r4, r0, lsl #16
+ 1103              	.LVL111:
+1644:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 1104              		.loc 1 1644 2 is_stmt 1 view .LVU325
+1644:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 1105              		.loc 1 1644 9 is_stmt 0 view .LVU326
+ 1106 0024 F6E7     		b	.L91
+ 1107              		.cfi_endproc
+ 1108              	.LFE1208:
+ 1110              		.section	.text.st_clust,"ax",%progbits
+ 1111              		.align	1
+ 1112              		.syntax unified
+ 1113              		.thumb
+ 1114              		.thumb_func
+ 1115              		.fpu fpv5-d16
+ 1117              	st_clust:
+ 1118              	.LVL112:
+ 1119              	.LFB1209:
+1646:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1647:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1648:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+1649:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1650:Middlewares/Third_Party/FatFs/src/ff.c **** void st_clust (
+1651:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs,	/* Pointer to the fs object */
+1652:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE* dir,	/* Pointer to the key entry */
+1653:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD cl	/* Value to be set */
+1654:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1655:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 1120              		.loc 1 1655 1 is_stmt 1 view -0
+ 1121              		.cfi_startproc
+ 1122              		@ args = 0, pretend = 0, frame = 0
+ 1123              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1124              		.loc 1 1655 1 is_stmt 0 view .LVU328
+ 1125 0000 70B5     		push	{r4, r5, r6, lr}
+ 1126              	.LCFI11:
+ 1127              		.cfi_def_cfa_offset 16
+ 1128              		.cfi_offset 4, -16
+ 1129              		.cfi_offset 5, -12
+ 1130              		.cfi_offset 6, -8
+ 1131              		.cfi_offset 14, -4
+ 1132 0002 0646     		mov	r6, r0
+ 1133 0004 0C46     		mov	r4, r1
+ 1134 0006 1546     		mov	r5, r2
+1656:Middlewares/Third_Party/FatFs/src/ff.c **** 	st_word(dir + DIR_FstClusLO, (WORD)cl);
+ 1135              		.loc 1 1656 2 is_stmt 1 view .LVU329
+ 1136 0008 91B2     		uxth	r1, r2
+ 1137              	.LVL113:
+ 1138              		.loc 1 1656 2 is_stmt 0 view .LVU330
+ 1139 000a 04F11A00 		add	r0, r4, #26
+ 1140              	.LVL114:
+ARM GAS  /tmp/cc5lWXRL.s 			page 51
+
+
+ 1141              		.loc 1 1656 2 view .LVU331
+ 1142 000e FFF7FEFF 		bl	st_word
+ 1143              	.LVL115:
+1657:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type == FS_FAT32) {
+ 1144              		.loc 1 1657 2 is_stmt 1 view .LVU332
+ 1145              		.loc 1 1657 8 is_stmt 0 view .LVU333
+ 1146 0012 3378     		ldrb	r3, [r6]	@ zero_extendqisi2
+ 1147              		.loc 1 1657 5 view .LVU334
+ 1148 0014 032B     		cmp	r3, #3
+ 1149 0016 00D0     		beq	.L98
+ 1150              	.L95:
+1658:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16));
+1659:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1660:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 1151              		.loc 1 1660 1 view .LVU335
+ 1152 0018 70BD     		pop	{r4, r5, r6, pc}
+ 1153              	.LVL116:
+ 1154              	.L98:
+1658:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16));
+ 1155              		.loc 1 1658 3 is_stmt 1 view .LVU336
+ 1156 001a 290C     		lsrs	r1, r5, #16
+ 1157 001c 04F11400 		add	r0, r4, #20
+ 1158 0020 FFF7FEFF 		bl	st_word
+ 1159              	.LVL117:
+ 1160              		.loc 1 1660 1 is_stmt 0 view .LVU337
+ 1161 0024 F8E7     		b	.L95
+ 1162              		.cfi_endproc
+ 1163              	.LFE1209:
+ 1165              		.section	.text.get_fileinfo,"ax",%progbits
+ 1166              		.align	1
+ 1167              		.syntax unified
+ 1168              		.thumb
+ 1169              		.thumb_func
+ 1170              		.fpu fpv5-d16
+ 1172              	get_fileinfo:
+ 1173              	.LVL118:
+ 1174              	.LFB1214:
+1661:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1662:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1663:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1664:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1665:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+1666:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------------------------------*/
+1667:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: LFN handling                                                  */
+1668:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------------------------------*/
+1669:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1670:Middlewares/Third_Party/FatFs/src/ff.c **** const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30};	/* Offset of LFN characters in the direc
+1671:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1672:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1673:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------------------------*/
+1674:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: Compare a part of file name with an LFN entry */
+1675:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------------------------*/
+1676:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1677:Middlewares/Third_Party/FatFs/src/ff.c **** int cmp_lfn (				/* 1:matched, 0:not matched */
+1678:Middlewares/Third_Party/FatFs/src/ff.c **** 	const WCHAR* lfnbuf,	/* Pointer to the LFN working buffer to be compared */
+1679:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE* dir				/* Pointer to the directory entry containing the part of LFN */
+1680:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ARM GAS  /tmp/cc5lWXRL.s 			page 52
+
+
+1681:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1682:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, s;
+1683:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR wc, uc;
+1684:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1685:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1686:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO */
+1687:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1688:Middlewares/Third_Party/FatFs/src/ff.c **** 	i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13;	/* Offset in the LFN buffer */
+1689:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1690:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+1691:Middlewares/Third_Party/FatFs/src/ff.c **** 		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+1692:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (wc) {
+1693:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (i >= _MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) {	/* Compare it */
+1694:Middlewares/Third_Party/FatFs/src/ff.c **** 				return 0;					/* Not matched */
+1695:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1696:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc = uc;
+1697:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+1698:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (uc != 0xFFFF) return 0;		/* Check filler */
+1699:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1700:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1701:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1702:Middlewares/Third_Party/FatFs/src/ff.c **** 	if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0;	/* Last segment matched but different len
+1703:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1704:Middlewares/Third_Party/FatFs/src/ff.c **** 	return 1;		/* The part of LFN matched */
+1705:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1706:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1707:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1708:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT
+1709:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------*/
+1710:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: Pick a part of file name from an LFN entry */
+1711:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------*/
+1712:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1713:Middlewares/Third_Party/FatFs/src/ff.c **** int pick_lfn (			/* 1:succeeded, 0:buffer overflow or invalid LFN entry */
+1714:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR* lfnbuf,		/* Pointer to the LFN working buffer */
+1715:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE* dir			/* Pointer to the LFN entry */
+1716:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1717:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1718:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, s;
+1719:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR wc, uc;
+1720:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1721:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1722:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO is 0 */
+1723:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1724:Middlewares/Third_Party/FatFs/src/ff.c **** 	i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13;	/* Offset in the LFN buffer */
+1725:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1726:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+1727:Middlewares/Third_Party/FatFs/src/ff.c **** 		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+1728:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (wc) {
+1729:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (i >= _MAX_LFN) return 0;	/* Buffer overflow? */
+1730:Middlewares/Third_Party/FatFs/src/ff.c **** 			lfnbuf[i++] = wc = uc;			/* Store it */
+1731:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+1732:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (uc != 0xFFFF) return 0;		/* Check filler */
+1733:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1734:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1735:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1736:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (dir[LDIR_Ord] & LLEF) {				/* Put terminator if it is the last LFN part */
+1737:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i >= _MAX_LFN) return 0;		/* Buffer overflow? */
+ARM GAS  /tmp/cc5lWXRL.s 			page 53
+
+
+1738:Middlewares/Third_Party/FatFs/src/ff.c **** 		lfnbuf[i] = 0;
+1739:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1740:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1741:Middlewares/Third_Party/FatFs/src/ff.c **** 	return 1;		/* The part of LFN is valid */
+1742:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1743:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1744:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1745:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1746:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+1747:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------*/
+1748:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: Create an entry of LFN entries */
+1749:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------*/
+1750:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1751:Middlewares/Third_Party/FatFs/src/ff.c **** void put_lfn (
+1752:Middlewares/Third_Party/FatFs/src/ff.c **** 	const WCHAR* lfn,	/* Pointer to the LFN */
+1753:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE* dir,			/* Pointer to the LFN entry to be created */
+1754:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE ord,			/* LFN order (1-20) */
+1755:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE sum			/* Checksum of the corresponding SFN */
+1756:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1757:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1758:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, s;
+1759:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR wc;
+1760:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1761:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1762:Middlewares/Third_Party/FatFs/src/ff.c **** 	dir[LDIR_Chksum] = sum;			/* Set checksum */
+1763:Middlewares/Third_Party/FatFs/src/ff.c **** 	dir[LDIR_Attr] = AM_LFN;		/* Set attribute. LFN entry */
+1764:Middlewares/Third_Party/FatFs/src/ff.c **** 	dir[LDIR_Type] = 0;
+1765:Middlewares/Third_Party/FatFs/src/ff.c **** 	st_word(dir + LDIR_FstClusLO, 0);
+1766:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1767:Middlewares/Third_Party/FatFs/src/ff.c **** 	i = (ord - 1) * 13;				/* Get offset in the LFN working buffer */
+1768:Middlewares/Third_Party/FatFs/src/ff.c **** 	s = wc = 0;
+1769:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+1770:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (wc != 0xFFFF) wc = lfn[i++];	/* Get an effective character */
+1771:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(dir + LfnOfs[s], wc);		/* Put it */
+1772:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (wc == 0) wc = 0xFFFF;		/* Padding characters for left locations */
+1773:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (++s < 13);
+1774:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (wc == 0xFFFF || !lfn[i]) ord |= LLEF;	/* Last LFN part is the start of LFN sequence */
+1775:Middlewares/Third_Party/FatFs/src/ff.c **** 	dir[LDIR_Ord] = ord;			/* Set the LFN order */
+1776:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1777:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1778:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* !_FS_READONLY */
+1779:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _USE_LFN != 0 */
+1780:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1781:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1782:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1783:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 && !_FS_READONLY
+1784:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1785:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: Create a Numbered SFN                                        */
+1786:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1787:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1788:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1789:Middlewares/Third_Party/FatFs/src/ff.c **** void gen_numname (
+1790:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE* dst,			/* Pointer to the buffer to store numbered SFN */
+1791:Middlewares/Third_Party/FatFs/src/ff.c **** 	const BYTE* src,	/* Pointer to SFN */
+1792:Middlewares/Third_Party/FatFs/src/ff.c **** 	const WCHAR* lfn,	/* Pointer to LFN */
+1793:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT seq			/* Sequence number */
+1794:Middlewares/Third_Party/FatFs/src/ff.c **** )
+ARM GAS  /tmp/cc5lWXRL.s 			page 54
+
+
+1795:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1796:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE ns[8], c;
+1797:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, j;
+1798:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR wc;
+1799:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD sr;
+1800:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1801:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1802:Middlewares/Third_Party/FatFs/src/ff.c **** 	mem_cpy(dst, src, 11);
+1803:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1804:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (seq > 5) {	/* In case of many collisions, generate a hash number instead of sequential number 
+1805:Middlewares/Third_Party/FatFs/src/ff.c **** 		sr = seq;
+1806:Middlewares/Third_Party/FatFs/src/ff.c **** 		while (*lfn) {	/* Create a CRC */
+1807:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc = *lfn++;
+1808:Middlewares/Third_Party/FatFs/src/ff.c **** 			for (i = 0; i < 16; i++) {
+1809:Middlewares/Third_Party/FatFs/src/ff.c **** 				sr = (sr << 1) + (wc & 1);
+1810:Middlewares/Third_Party/FatFs/src/ff.c **** 				wc >>= 1;
+1811:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (sr & 0x10000) sr ^= 0x11021;
+1812:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+1813:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1814:Middlewares/Third_Party/FatFs/src/ff.c **** 		seq = (UINT)sr;
+1815:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1816:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1817:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* itoa (hexdecimal) */
+1818:Middlewares/Third_Party/FatFs/src/ff.c **** 	i = 7;
+1819:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+1820:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = (BYTE)((seq % 16) + '0');
+1821:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c > '9') c += 7;
+1822:Middlewares/Third_Party/FatFs/src/ff.c **** 		ns[i--] = c;
+1823:Middlewares/Third_Party/FatFs/src/ff.c **** 		seq /= 16;
+1824:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (seq);
+1825:Middlewares/Third_Party/FatFs/src/ff.c **** 	ns[i] = '~';
+1826:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1827:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Append the number */
+1828:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (j = 0; j < i && dst[j] != ' '; j++) {
+1829:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (IsDBCS1(dst[j])) {
+1830:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (j == i - 1) break;
+1831:Middlewares/Third_Party/FatFs/src/ff.c **** 			j++;
+1832:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1833:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1834:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+1835:Middlewares/Third_Party/FatFs/src/ff.c **** 		dst[j++] = (i < 8) ? ns[i++] : ' ';
+1836:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (j < 8);
+1837:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1838:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _USE_LFN != 0 && !_FS_READONLY */
+1839:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1840:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1841:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+1843:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1844:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: Calculate checksum of an SFN entry                           */
+1845:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1846:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1847:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1848:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE sum_sfn (
+1849:Middlewares/Third_Party/FatFs/src/ff.c **** 	const BYTE* dir		/* Pointer to the SFN entry */
+1850:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1851:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ARM GAS  /tmp/cc5lWXRL.s 			page 55
+
+
+1852:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE sum = 0;
+1853:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT n = 11;
+1854:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1855:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+1856:Middlewares/Third_Party/FatFs/src/ff.c **** 		sum = (sum >> 1) + (sum << 7) + *dir++;
+1857:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (--n);
+1858:Middlewares/Third_Party/FatFs/src/ff.c **** 	return sum;
+1859:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1860:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1861:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _USE_LFN != 0 */
+1862:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1863:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1864:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1865:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+1866:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1867:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Checksum                                                       */
+1868:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+1869:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1870:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1871:Middlewares/Third_Party/FatFs/src/ff.c **** WORD xdir_sum (			/* Get checksum of the directoly block */
+1872:Middlewares/Third_Party/FatFs/src/ff.c **** 	const BYTE* dir		/* Directory entry block to be calculated */
+1873:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1874:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1875:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, szblk;
+1876:Middlewares/Third_Party/FatFs/src/ff.c **** 	WORD sum;
+1877:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1878:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1879:Middlewares/Third_Party/FatFs/src/ff.c **** 	szblk = (dir[XDIR_NumSec] + 1) * SZDIRE;
+1880:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (i = sum = 0; i < szblk; i++) {
+1881:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i == XDIR_SetSum) {	/* Skip sum field */
+1882:Middlewares/Third_Party/FatFs/src/ff.c **** 			i++;
+1883:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+1884:Middlewares/Third_Party/FatFs/src/ff.c **** 			sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i];
+1885:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1886:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1887:Middlewares/Third_Party/FatFs/src/ff.c **** 	return sum;
+1888:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1889:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1890:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1891:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1892:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1893:Middlewares/Third_Party/FatFs/src/ff.c **** WORD xname_sum (		/* Get check sum (to be used as hash) of the name */
+1894:Middlewares/Third_Party/FatFs/src/ff.c **** 	const WCHAR* name	/* File name to be calculated */
+1895:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1896:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1897:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR chr;
+1898:Middlewares/Third_Party/FatFs/src/ff.c **** 	WORD sum = 0;
+1899:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1900:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1901:Middlewares/Third_Party/FatFs/src/ff.c **** 	while ((chr = *name++) != 0) {
+1902:Middlewares/Third_Party/FatFs/src/ff.c **** 		chr = ff_wtoupper(chr);		/* File name needs to be ignored case */
+1903:Middlewares/Third_Party/FatFs/src/ff.c **** 		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF);
+1904:Middlewares/Third_Party/FatFs/src/ff.c **** 		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8);
+1905:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1906:Middlewares/Third_Party/FatFs/src/ff.c **** 	return sum;
+1907:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1908:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 56
+
+
+1909:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1910:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _USE_MKFS
+1911:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1912:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD xsum32 (
+1913:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE  dat,	/* Data to be sumed */
+1914:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD sum	/* Previous value */
+1915:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1916:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1917:Middlewares/Third_Party/FatFs/src/ff.c **** 	sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat;
+1918:Middlewares/Third_Party/FatFs/src/ff.c **** 	return sum;
+1919:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1920:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1921:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1922:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1923:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
+1924:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------------*/
+1925:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Get object information from a directory block */
+1926:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------------*/
+1927:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1928:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1929:Middlewares/Third_Party/FatFs/src/ff.c **** void get_xdir_info (
+1930:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE* dirb,			/* Pointer to the direcotry entry block 85+C0+C1s */
+1931:Middlewares/Third_Party/FatFs/src/ff.c **** 	FILINFO* fno		/* Buffer to store the extracted file information */
+1932:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1933:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1934:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT di, si;
+1935:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR w;
+1936:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_LFN_UNICODE
+1937:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT nc;
+1938:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1939:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1940:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get file name */
+1941:Middlewares/Third_Party/FatFs/src/ff.c **** 	di = 0;
+1942:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+1943:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (si = SZDIRE * 2; di < dirb[XDIR_NumName]; si += 2, di++) {
+1944:Middlewares/Third_Party/FatFs/src/ff.c **** 		if ((si % SZDIRE) == 0) si += 2;		/* Skip entry type field */
+1945:Middlewares/Third_Party/FatFs/src/ff.c **** 		w = ld_word(dirb + si);					/* Get a character */
+1946:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (di >= _MAX_LFN) { di = 0; break; }	/* Buffer overflow --> inaccessible object name */
+1947:Middlewares/Third_Party/FatFs/src/ff.c **** 		fno->fname[di] = w;						/* Store it */
+1948:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1949:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+1950:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (si = SZDIRE * 2, nc = 0; nc < dirb[XDIR_NumName]; si += 2, nc++) {
+1951:Middlewares/Third_Party/FatFs/src/ff.c **** 		if ((si % SZDIRE) == 0) si += 2;		/* Skip entry type field */
+1952:Middlewares/Third_Party/FatFs/src/ff.c **** 		w = ff_convert(ld_word(dirb + si), 0);	/* Get a character and Unicode -> OEM */
+1953:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_DF1S && w >= 0x100) {				/* Is it a double byte char? (always false at SBCS cfg) */
+1954:Middlewares/Third_Party/FatFs/src/ff.c **** 			fno->fname[di++] = (char)(w >> 8);	/* Put 1st byte of the DBC */
+1955:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+1956:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (w == 0 || di >= _MAX_LFN) { di = 0; break; }	/* Invalid char or buffer overflow --> inaccessi
+1957:Middlewares/Third_Party/FatFs/src/ff.c **** 		fno->fname[di++] = (char)w;
+1958:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+1959:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+1960:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (di == 0) fno->fname[di++] = '?';	/* Inaccessible object name? */
+1961:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->fname[di] = 0;						/* Terminate file name */
+1962:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1963:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->altname[0] = 0;							/* No SFN */
+1964:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->fattrib = dirb[XDIR_Attr];					/* Attribute */
+1965:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(dirb + XDIR_FileSize);	/* Size */
+ARM GAS  /tmp/cc5lWXRL.s 			page 57
+
+
+1966:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->ftime = ld_word(dirb + XDIR_ModTime + 0);	/* Time */
+1967:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->fdate = ld_word(dirb + XDIR_ModTime + 2);	/* Date */
+1968:Middlewares/Third_Party/FatFs/src/ff.c **** }
+1969:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1970:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */
+1971:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1972:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1973:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------*/
+1974:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Get a directry entry block */
+1975:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------*/
+1976:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1977:Middlewares/Third_Party/FatFs/src/ff.c **** static
+1978:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT load_xdir (	/* FR_INT_ERR: invalid entry block */
+1979:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp			/* Pointer to the reading direcotry object pointing the 85 entry */
+1980:Middlewares/Third_Party/FatFs/src/ff.c **** )
+1981:Middlewares/Third_Party/FatFs/src/ff.c **** {
+1982:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+1983:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, sz_ent;
+1984:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE* dirb = dp->obj.fs->dirbuf;	/* Pointer to the on-memory direcotry entry block 85+C0+C1s */
+1985:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1986:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1987:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Load 85 entry */
+1988:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = move_window(dp->obj.fs, dp->sect);
+1989:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK) return res;
+1990:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (dp->dir[XDIR_Type] != 0x85) return FR_INT_ERR;
+1991:Middlewares/Third_Party/FatFs/src/ff.c **** 	mem_cpy(dirb + 0, dp->dir, SZDIRE);
+1992:Middlewares/Third_Party/FatFs/src/ff.c **** 	sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE;
+1993:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR;
+1994:Middlewares/Third_Party/FatFs/src/ff.c **** 
+1995:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Load C0 entry */
+1996:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = dir_next(dp, 0);
+1997:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK) return res;
+1998:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = move_window(dp->obj.fs, dp->sect);
+1999:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK) return res;
+2000:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (dp->dir[XDIR_Type] != 0xC0) return FR_INT_ERR;
+2001:Middlewares/Third_Party/FatFs/src/ff.c **** 	mem_cpy(dirb + SZDIRE, dp->dir, SZDIRE);
+2002:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR;
+2003:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2004:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Load C1 entries */
+2005:Middlewares/Third_Party/FatFs/src/ff.c **** 	i = SZDIRE * 2;	/* C1 offset */
+2006:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+2007:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = dir_next(dp, 0);
+2008:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) return res;
+2009:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(dp->obj.fs, dp->sect);
+2010:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) return res;
+2011:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (dp->dir[XDIR_Type] != 0xC1) return FR_INT_ERR;
+2012:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i < MAXDIRB(_MAX_LFN)) mem_cpy(dirb + i, dp->dir, SZDIRE);
+2013:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while ((i += SZDIRE) < sz_ent);
+2014:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2015:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Sanity check (do it when accessible object name) */
+2016:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (i <= MAXDIRB(_MAX_LFN)) {
+2017:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR;
+2018:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2019:Middlewares/Third_Party/FatFs/src/ff.c **** 	return FR_OK;
+2020:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2021:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2022:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 58
+
+
+2023:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY || _FS_RPATH != 0
+2024:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------*/
+2025:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Load the object's directory entry block */
+2026:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------*/
+2027:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2028:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT load_obj_dir (
+2029:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,			/* Blank directory object to be used to access containing direcotry */
+2030:Middlewares/Third_Party/FatFs/src/ff.c **** 	const _FDID* obj	/* Object with its containing directory information */
+2031:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2032:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2033:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+2034:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2035:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Open object containing directory */
+2036:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->obj.fs = obj->fs;
+2037:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->obj.sclust = obj->c_scl;
+2038:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->obj.stat = (BYTE)obj->c_size;
+2039:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->obj.objsize = obj->c_size & 0xFFFFFF00;
+2040:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->blk_ofs = obj->c_ofs;
+2041:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2042:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = dir_sdi(dp, dp->blk_ofs);	/* Goto object's entry block */
+2043:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+2044:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = load_xdir(dp);		/* Load the object's entry block */
+2045:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2046:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+2047:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2048:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2049:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2050:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2051:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+2052:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------*/
+2053:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Store the directory block to the media */
+2054:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------*/
+2055:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2056:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT store_xdir (
+2057:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp				/* Pointer to the direcotry object */
+2058:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2059:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2060:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+2061:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT nent;
+2062:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE* dirb = dp->obj.fs->dirbuf;	/* Pointer to the direcotry entry block 85+C0+C1s */
+2063:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2064:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Create set sum */
+2065:Middlewares/Third_Party/FatFs/src/ff.c **** 	st_word(dirb + XDIR_SetSum, xdir_sum(dirb));
+2066:Middlewares/Third_Party/FatFs/src/ff.c **** 	nent = dirb[XDIR_NumSec] + 1;
+2067:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2068:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Store the set of directory to the volume */
+2069:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = dir_sdi(dp, dp->blk_ofs);
+2070:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (res == FR_OK) {
+2071:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(dp->obj.fs, dp->sect);
+2072:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+2073:Middlewares/Third_Party/FatFs/src/ff.c **** 		mem_cpy(dp->dir, dirb, SZDIRE);
+2074:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->obj.fs->wflag = 1;
+2075:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (--nent == 0) break;
+2076:Middlewares/Third_Party/FatFs/src/ff.c **** 		dirb += SZDIRE;
+2077:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = dir_next(dp, 0);
+2078:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2079:Middlewares/Third_Party/FatFs/src/ff.c **** 	return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR;
+ARM GAS  /tmp/cc5lWXRL.s 			page 59
+
+
+2080:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2081:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2082:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2083:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2084:Middlewares/Third_Party/FatFs/src/ff.c **** /*-------------------------------------------*/
+2085:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Create a new directory enrty block */
+2086:Middlewares/Third_Party/FatFs/src/ff.c **** /*-------------------------------------------*/
+2087:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2088:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2089:Middlewares/Third_Party/FatFs/src/ff.c **** void create_xdir (
+2090:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE* dirb,			/* Pointer to the direcotry entry block buffer */
+2091:Middlewares/Third_Party/FatFs/src/ff.c **** 	const WCHAR* lfn	/* Pointer to the nul terminated file name */
+2092:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2093:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2094:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+2095:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE nb, nc;
+2096:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR chr;
+2097:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2098:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2099:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Create 85+C0 entry */
+2100:Middlewares/Third_Party/FatFs/src/ff.c **** 	mem_set(dirb, 0, 2 * SZDIRE);
+2101:Middlewares/Third_Party/FatFs/src/ff.c **** 	dirb[XDIR_Type] = 0x85;
+2102:Middlewares/Third_Party/FatFs/src/ff.c **** 	dirb[XDIR_Type + SZDIRE] = 0xC0;
+2103:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2104:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Create C1 entries */
+2105:Middlewares/Third_Party/FatFs/src/ff.c **** 	nc = 0; nb = 1; chr = 1; i = SZDIRE * 2;
+2106:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+2107:Middlewares/Third_Party/FatFs/src/ff.c **** 		dirb[i++] = 0xC1; dirb[i++] = 0;	/* Entry type C1 */
+2108:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {	/* Fill name field */
+2109:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (chr && (chr = lfn[nc]) != 0) nc++;	/* Get a character if exist */
+2110:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(dirb + i, chr); 		/* Store it */
+2111:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while ((i += 2) % SZDIRE != 0);
+2112:Middlewares/Third_Party/FatFs/src/ff.c **** 		nb++;
+2113:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (lfn[nc]);	/* Fill next entry if any char follows */
+2114:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2115:Middlewares/Third_Party/FatFs/src/ff.c **** 	dirb[XDIR_NumName] = nc;	/* Set name length */
+2116:Middlewares/Third_Party/FatFs/src/ff.c **** 	dirb[XDIR_NumSec] = nb;		/* Set block length */
+2117:Middlewares/Third_Party/FatFs/src/ff.c **** 	st_word(dirb + XDIR_NameHash, xname_sum(lfn));	/* Set name hash */
+2118:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2119:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2120:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* !_FS_READONLY */
+2121:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _FS_EXFAT */
+2122:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2123:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2124:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2125:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT
+2126:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2127:Middlewares/Third_Party/FatFs/src/ff.c **** /* Read an object from the directory                                     */
+2128:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2129:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2130:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2131:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_read (
+2132:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,		/* Pointer to the directory object */
+2133:Middlewares/Third_Party/FatFs/src/ff.c **** 	int vol			/* Filtered by 0:file/directory or 1:volume label */
+2134:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2135:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2136:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_NO_FILE;
+ARM GAS  /tmp/cc5lWXRL.s 			page 60
+
+
+2137:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+2138:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE a, c;
+2139:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+2140:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE ord = 0xFF, sum = 0xFF;
+2141:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2142:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2143:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (dp->sect) {
+2144:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, dp->sect);
+2145:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+2146:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = dp->dir[DIR_Name];	/* Test for the entry type */
+2147:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == 0) {
+2148:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_NO_FILE; break; /* Reached to end of the directory */
+2149:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2150:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+2151:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+2152:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (_USE_LABEL && vol) {
+2153:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (c == 0x83) break;	/* Volume label entry? */
+2154:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+2155:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (c == 0x85) {		/* Start of the file entry block? */
+2156:Middlewares/Third_Party/FatFs/src/ff.c **** 					dp->blk_ofs = dp->dptr;	/* Get location of the block */
+2157:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = load_xdir(dp);	/* Load the entry block */
+2158:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res == FR_OK) {
+2159:Middlewares/Third_Party/FatFs/src/ff.c **** 						dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK;	/* Get attribute */
+2160:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+2161:Middlewares/Third_Party/FatFs/src/ff.c **** 					break;
+2162:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+2163:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2164:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else
+2165:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2166:Middlewares/Third_Party/FatFs/src/ff.c **** 		{	/* On the FAT12/16/32 volume */
+2167:Middlewares/Third_Party/FatFs/src/ff.c **** 			dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;	/* Get attribute */
+2168:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+2169:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (c == DDEM || c == '.' || (int)((a & ~AM_ARC) == AM_VOL) != vol) {	/* An entry without valid 
+2170:Middlewares/Third_Party/FatFs/src/ff.c **** 				ord = 0xFF;
+2171:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+2172:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (a == AM_LFN) {			/* An LFN entry is found */
+2173:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (c & LLEF) {			/* Is it start of an LFN sequence? */
+2174:Middlewares/Third_Party/FatFs/src/ff.c **** 						sum = dp->dir[LDIR_Chksum];
+2175:Middlewares/Third_Party/FatFs/src/ff.c **** 						c &= (BYTE)~LLEF; ord = c;
+2176:Middlewares/Third_Party/FatFs/src/ff.c **** 						dp->blk_ofs = dp->dptr;
+2177:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+2178:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Check LFN validity and capture it */
+2179:Middlewares/Third_Party/FatFs/src/ff.c **** 					ord = (c == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0
+2180:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {					/* An SFN entry is found */
+2181:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (ord || sum != sum_sfn(dp->dir)) {	/* Is there a valid LFN? */
+2182:Middlewares/Third_Party/FatFs/src/ff.c **** 						dp->blk_ofs = 0xFFFFFFFF;			/* It has no LFN. */
+2183:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+2184:Middlewares/Third_Party/FatFs/src/ff.c **** 					break;
+2185:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+2186:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2187:Middlewares/Third_Party/FatFs/src/ff.c **** #else		/* Non LFN configuration */
+2188:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (c != DDEM && c != '.' && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol) {	/* Is it a 
+2189:Middlewares/Third_Party/FatFs/src/ff.c **** 				break;
+2190:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2191:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2192:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2193:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = dir_next(dp, 0);		/* Next entry */
+ARM GAS  /tmp/cc5lWXRL.s 			page 61
+
+
+2194:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+2195:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2196:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2197:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK) dp->sect = 0;		/* Terminate the read operation on error or EOT */
+2198:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+2199:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2200:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2201:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */
+2202:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2203:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2204:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2205:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2206:Middlewares/Third_Party/FatFs/src/ff.c **** /* Directory handling - Find an object in the directory                  */
+2207:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2208:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2209:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2210:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_find (	/* FR_OK(0):succeeded, !=0:error */
+2211:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp			/* Pointer to the directory object with the file name */
+2212:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2213:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2214:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+2215:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+2216:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE c;
+2217:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+2218:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE a, ord, sum;
+2219:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2220:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2221:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = dir_sdi(dp, 0);			/* Rewind directory object */
+2222:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK) return res;
+2223:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+2224:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+2225:Middlewares/Third_Party/FatFs/src/ff.c **** 		BYTE nc;
+2226:Middlewares/Third_Party/FatFs/src/ff.c **** 		UINT di, ni;
+2227:Middlewares/Third_Party/FatFs/src/ff.c **** 		WORD hash = xname_sum(fs->lfnbuf);		/* Hash value of the name to find */
+2228:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2229:Middlewares/Third_Party/FatFs/src/ff.c **** 		while ((res = dir_read(dp, 0)) == FR_OK) {	/* Read an item */
+2230:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_LFN < 255
+2231:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->dirbuf[XDIR_NumName] > _MAX_LFN) continue;			/* Skip comparison if inaccessible object n
+2232:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2233:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue;	/* Skip comparison if hash mismatched
+2234:Middlewares/Third_Party/FatFs/src/ff.c **** 			for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) {	/* Compa
+2235:Middlewares/Third_Party/FatFs/src/ff.c **** 				if ((di % SZDIRE) == 0) di += 2;
+2236:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break;
+2237:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2238:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (nc == 0 && !fs->lfnbuf[ni]) break;	/* Name matched? */
+2239:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2240:Middlewares/Third_Party/FatFs/src/ff.c **** 		return res;
+2241:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2242:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2243:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* On the FAT12/16/32 volume */
+2244:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+2245:Middlewares/Third_Party/FatFs/src/ff.c **** 	ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+2246:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2247:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+2248:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, dp->sect);
+2249:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+2250:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = dp->dir[DIR_Name];
+ARM GAS  /tmp/cc5lWXRL.s 			page 62
+
+
+2251:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+2252:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+2253:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;
+2254:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) {	/* An entry without valid data */
+2255:Middlewares/Third_Party/FatFs/src/ff.c **** 			ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+2256:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+2257:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (a == AM_LFN) {			/* An LFN entry is found */
+2258:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!(dp->fn[NSFLAG] & NS_NOLFN)) {
+2259:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (c & LLEF) {		/* Is it start of LFN sequence? */
+2260:Middlewares/Third_Party/FatFs/src/ff.c **** 						sum = dp->dir[LDIR_Chksum];
+2261:Middlewares/Third_Party/FatFs/src/ff.c **** 						c &= (BYTE)~LLEF; ord = c;	/* LFN start order */
+2262:Middlewares/Third_Party/FatFs/src/ff.c **** 						dp->blk_ofs = dp->dptr;	/* Start offset of LFN */
+2263:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+2264:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Check validity of the LFN entry and compare it with given name */
+2265:Middlewares/Third_Party/FatFs/src/ff.c **** 					ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0x
+2266:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+2267:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {					/* An SFN entry is found */
+2268:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!ord && sum == sum_sfn(dp->dir)) break;	/* LFN matched? */
+2269:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* SFN matched? */
+2270:Middlewares/Third_Party/FatFs/src/ff.c **** 				ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+2271:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2272:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2273:Middlewares/Third_Party/FatFs/src/ff.c **** #else		/* Non LFN configuration */
+2274:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK;
+2275:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* Is it a valid entry
+2276:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2277:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = dir_next(dp, 0);	/* Next entry */
+2278:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (res == FR_OK);
+2279:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2280:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+2281:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2282:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2283:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2284:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2285:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2286:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+2287:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2288:Middlewares/Third_Party/FatFs/src/ff.c **** /* Register an object to the directory                                   */
+2289:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2290:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2291:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2292:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_register (	/* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DI
+2293:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp				/* Target directory with object name to be created */
+2294:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2295:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2296:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+2297:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+2298:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+2299:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT n, nlen, nent;
+2300:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE sn[12], sum;
+2301:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2302:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2303:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME;	/* Check name validity */
+2304:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (nlen = 0; fs->lfnbuf[nlen]; nlen++) ;	/* Get lfn length */
+2305:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2306:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+2307:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+ARM GAS  /tmp/cc5lWXRL.s 			page 63
+
+
+2308:Middlewares/Third_Party/FatFs/src/ff.c **** 		DIR dj;
+2309:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2310:Middlewares/Third_Party/FatFs/src/ff.c **** 		nent = (nlen + 14) / 15 + 2;	/* Number of entries to allocate (85+C0+C1s) */
+2311:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = dir_alloc(dp, nent);		/* Allocate entries */
+2312:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) return res;
+2313:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->blk_ofs = dp->dptr - SZDIRE * (nent - 1);	/* Set the allocated entry block offset */
+2314:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2315:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (dp->obj.sclust != 0 && (dp->obj.stat & 4)) {	/* Has the sub-directory been stretched? */
+2316:Middlewares/Third_Party/FatFs/src/ff.c **** 			dp->obj.objsize += (DWORD)fs->csize * SS(fs);	/* Increase the directory size by cluster size */
+2317:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = fill_first_frag(&dp->obj);				/* Fill first fragment on the FAT if needed */
+2318:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) return res;
+2319:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if neede
+2320:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) return res;
+2321:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = load_obj_dir(&dj, &dp->obj);				/* Load the object status */
+2322:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) return res;
+2323:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize);		/* Update the allocation status */
+2324:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize);
+2325:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1;
+2326:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = store_xdir(&dj);							/* Store the object status */
+2327:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) return res;
+2328:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2329:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2330:Middlewares/Third_Party/FatFs/src/ff.c **** 		create_xdir(fs->dirbuf, fs->lfnbuf);	/* Create on-memory directory block to be written later */
+2331:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_OK;
+2332:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2333:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2334:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* On the FAT12/16/32 volume */
+2335:Middlewares/Third_Party/FatFs/src/ff.c **** 	mem_cpy(sn, dp->fn, 12);
+2336:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (sn[NSFLAG] & NS_LOSS) {			/* When LFN is out of 8.3 format, generate a numbered name */
+2337:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->fn[NSFLAG] = NS_NOLFN;		/* Find only SFN */
+2338:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (n = 1; n < 100; n++) {
+2339:Middlewares/Third_Party/FatFs/src/ff.c **** 			gen_numname(dp->fn, sn, fs->lfnbuf, n);	/* Generate a numbered name */
+2340:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dir_find(dp);				/* Check if the name collides with existing SFN */
+2341:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+2342:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2343:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (n == 100) return FR_DENIED;		/* Abort if too many collisions */
+2344:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_NO_FILE) return res;	/* Abort if the result is other than 'not collided' */
+2345:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->fn[NSFLAG] = sn[NSFLAG];
+2346:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2347:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2348:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Create an SFN with/without LFNs. */
+2349:Middlewares/Third_Party/FatFs/src/ff.c **** 	nent = (sn[NSFLAG] & NS_LFN) ? (nlen + 12) / 13 + 1 : 1;	/* Number of entries to allocate */
+2350:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = dir_alloc(dp, nent);		/* Allocate entries */
+2351:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK && --nent) {	/* Set LFN entry if needed */
+2352:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = dir_sdi(dp, dp->dptr - nent * SZDIRE);
+2353:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+2354:Middlewares/Third_Party/FatFs/src/ff.c **** 			sum = sum_sfn(dp->fn);	/* Checksum value of the SFN tied to the LFN */
+2355:Middlewares/Third_Party/FatFs/src/ff.c **** 			do {					/* Store LFN entries in bottom first */
+2356:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = move_window(fs, dp->sect);
+2357:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res != FR_OK) break;
+2358:Middlewares/Third_Party/FatFs/src/ff.c **** 				put_lfn(fs->lfnbuf, dp->dir, (BYTE)nent, sum);
+2359:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->wflag = 1;
+2360:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_next(dp, 0);	/* Next entry */
+2361:Middlewares/Third_Party/FatFs/src/ff.c **** 			} while (res == FR_OK && --nent);
+2362:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2363:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2364:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 64
+
+
+2365:Middlewares/Third_Party/FatFs/src/ff.c **** #else	/* Non LFN configuration */
+2366:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = dir_alloc(dp, 1);		/* Allocate an entry for SFN */
+2367:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2368:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2369:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2370:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Set SFN entry */
+2371:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+2372:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, dp->sect);
+2373:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+2374:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(dp->dir, 0, SZDIRE);	/* Clean the entry */
+2375:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_cpy(dp->dir + DIR_Name, dp->fn, 11);	/* Put SFN */
+2376:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+2377:Middlewares/Third_Party/FatFs/src/ff.c **** 			dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT);	/* Put NT flag */
+2378:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2379:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+2380:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2381:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2382:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2383:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+2384:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2385:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2386:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */
+2387:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2388:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2389:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2390:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE == 0
+2391:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2392:Middlewares/Third_Party/FatFs/src/ff.c **** /* Remove an object from the directory                                   */
+2393:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2394:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2395:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2396:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_remove (	/* FR_OK:Succeeded, FR_DISK_ERR:A disk error */
+2397:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp				/* Directory object pointing the entry to be removed */
+2398:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2399:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2400:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+2401:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+2402:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+2403:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD last = dp->dptr;
+2404:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2405:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs);	/* Goto top of the entry blo
+2406:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+2407:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+2408:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, dp->sect);
+2409:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+2410:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Mark an entry 'deleted' */
+2411:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+2412:Middlewares/Third_Party/FatFs/src/ff.c **** 				dp->dir[XDIR_Type] &= 0x7F;
+2413:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {									/* On the FAT12/16/32 volume */
+2414:Middlewares/Third_Party/FatFs/src/ff.c **** 				dp->dir[DIR_Name] = DDEM;
+2415:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2416:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+2417:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dp->dptr >= last) break;	/* If reached last entry then all entries of the object has been de
+2418:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dir_next(dp, 0);	/* Next entry */
+2419:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (res == FR_OK);
+2420:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_NO_FILE) res = FR_INT_ERR;
+2421:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ARM GAS  /tmp/cc5lWXRL.s 			page 65
+
+
+2422:Middlewares/Third_Party/FatFs/src/ff.c **** #else			/* Non LFN configuration */
+2423:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2424:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = move_window(fs, dp->sect);
+2425:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+2426:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->dir[DIR_Name] = DDEM;
+2427:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->wflag = 1;
+2428:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2430:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2431:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+2432:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2433:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2434:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY && _FS_MINIMIZE == 0 */
+2435:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2436:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2437:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2438:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
+2439:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2440:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get file information from directory entry                             */
+2441:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2442:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2443:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2444:Middlewares/Third_Party/FatFs/src/ff.c **** void get_fileinfo (		/* No return code */
+2445:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,			/* Pointer to the directory object */
+2446:Middlewares/Third_Party/FatFs/src/ff.c **** 	FILINFO* fno	 	/* Pointer to the file information to be filled */
+2447:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2448:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 1175              		.loc 1 2448 1 is_stmt 1 view -0
+ 1176              		.cfi_startproc
+ 1177              		@ args = 0, pretend = 0, frame = 0
+ 1178              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1179              		.loc 1 2448 1 is_stmt 0 view .LVU339
+ 1180 0000 38B5     		push	{r3, r4, r5, lr}
+ 1181              	.LCFI12:
+ 1182              		.cfi_def_cfa_offset 16
+ 1183              		.cfi_offset 3, -16
+ 1184              		.cfi_offset 4, -12
+ 1185              		.cfi_offset 5, -8
+ 1186              		.cfi_offset 14, -4
+2449:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, j;
+ 1187              		.loc 1 2449 2 is_stmt 1 view .LVU340
+2450:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR c;
+ 1188              		.loc 1 2450 2 view .LVU341
+2451:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD tm;
+ 1189              		.loc 1 2451 2 view .LVU342
+2452:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+2453:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR w, lfv;
+2454:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+2455:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2456:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2457:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2458:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->fname[0] = 0;		/* Invaidate file info */
+ 1190              		.loc 1 2458 2 view .LVU343
+ 1191              		.loc 1 2458 16 is_stmt 0 view .LVU344
+ 1192 0002 0023     		movs	r3, #0
+ 1193 0004 4B72     		strb	r3, [r1, #9]
+2459:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!dp->sect) return;	/* Exit if read pointer has reached end of directory */
+ARM GAS  /tmp/cc5lWXRL.s 			page 66
+
+
+ 1194              		.loc 1 2459 2 is_stmt 1 view .LVU345
+ 1195              		.loc 1 2459 9 is_stmt 0 view .LVU346
+ 1196 0006 C369     		ldr	r3, [r0, #28]
+ 1197              		.loc 1 2459 5 view .LVU347
+ 1198 0008 73B3     		cbz	r3, .L99
+ 1199 000a 0546     		mov	r5, r0
+ 1200 000c 0C46     		mov	r4, r1
+2460:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2461:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+2462:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+2463:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+2464:Middlewares/Third_Party/FatFs/src/ff.c **** 		get_xdir_info(fs->dirbuf, fno);
+2465:Middlewares/Third_Party/FatFs/src/ff.c **** 		return;
+2466:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else
+2467:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2468:Middlewares/Third_Party/FatFs/src/ff.c **** 	{	/* On the FAT12/16/32 volume */
+2469:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (dp->blk_ofs != 0xFFFFFFFF) {	/* Get LFN if available */
+2470:Middlewares/Third_Party/FatFs/src/ff.c **** 			i = j = 0;
+2471:Middlewares/Third_Party/FatFs/src/ff.c **** 			while ((w = fs->lfnbuf[j++]) != 0) {	/* Get an LFN character */
+2472:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_LFN_UNICODE
+2473:Middlewares/Third_Party/FatFs/src/ff.c **** 				w = ff_convert(w, 0);		/* Unicode -> OEM */
+2474:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (w == 0) { i = 0; break; }	/* No LFN if it could not be converted */
+2475:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (_DF1S && w >= 0x100) {	/* Put 1st byte if it is a DBC (always false at SBCS cfg) */
+2476:Middlewares/Third_Party/FatFs/src/ff.c **** 					fno->fname[i++] = (char)(w >> 8);
+2477:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+2478:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2479:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (i >= _MAX_LFN) { i = 0; break; }	/* No LFN if buffer overflow */
+2480:Middlewares/Third_Party/FatFs/src/ff.c **** 				fno->fname[i++] = (TCHAR)w;
+2481:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2482:Middlewares/Third_Party/FatFs/src/ff.c **** 			fno->fname[i] = 0;	/* Terminate the LFN */
+2483:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2484:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2485:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2486:Middlewares/Third_Party/FatFs/src/ff.c **** 	i = j = 0;
+2487:Middlewares/Third_Party/FatFs/src/ff.c **** 	lfv = fno->fname[i];	/* LFN is exist if non-zero */
+2488:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (i < 11) {		/* Copy name body and extension */
+2489:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = (TCHAR)dp->dir[i++];
+2490:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == ' ') continue;				/* Skip padding spaces */
+2491:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+2492:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i == 9) {						/* Insert a . if extension is exist */
+2493:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!lfv) fno->fname[j] = '.';
+2494:Middlewares/Third_Party/FatFs/src/ff.c **** 			fno->altname[j++] = '.';
+2495:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2496:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+2497:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dp->dir[i])) {
+2498:Middlewares/Third_Party/FatFs/src/ff.c **** 			c = c << 8 | dp->dir[i++];
+2499:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2500:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = ff_convert(c, 1);	/* OEM -> Unicode */
+2501:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!c) c = '?';
+2502:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2503:Middlewares/Third_Party/FatFs/src/ff.c **** 		fno->altname[j] = c;
+2504:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!lfv) {
+2505:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (IsUpper(c) && (dp->dir[DIR_NTres] & ((i >= 9) ? NS_EXT : NS_BODY))) {
+2506:Middlewares/Third_Party/FatFs/src/ff.c **** 				c += 0x20;			/* To lower */
+2507:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2508:Middlewares/Third_Party/FatFs/src/ff.c **** 			fno->fname[j] = c;
+2509:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ARM GAS  /tmp/cc5lWXRL.s 			page 67
+
+
+2510:Middlewares/Third_Party/FatFs/src/ff.c **** 		j++;
+2511:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2512:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!lfv) {
+2513:Middlewares/Third_Party/FatFs/src/ff.c **** 		fno->fname[j] = 0;
+2514:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!dp->dir[DIR_NTres]) j = 0;	/* Altname is no longer needed if neither LFN nor case info is ex
+2515:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2516:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->altname[j] = 0;	/* Terminate the SFN */
+2517:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2518:Middlewares/Third_Party/FatFs/src/ff.c **** #else	/* Non-LFN configuration */
+2519:Middlewares/Third_Party/FatFs/src/ff.c **** 	i = j = 0;
+ 1201              		.loc 1 2519 8 view .LVU348
+ 1202 000e 0022     		movs	r2, #0
+ 1203              		.loc 1 2519 4 view .LVU349
+ 1204 0010 1346     		mov	r3, r2
+ 1205 0012 06E0     		b	.L101
+ 1206              	.LVL119:
+ 1207              	.L103:
+2520:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (i < 11) {		/* Copy name body and extension */
+2521:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = (TCHAR)dp->dir[i++];
+2522:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == ' ') continue;				/* Skip padding spaces */
+2523:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+2524:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i == 9) fno->fname[j++] = '.';	/* Insert a . if extension is exist */
+ 1208              		.loc 1 2524 3 is_stmt 1 view .LVU350
+ 1209              		.loc 1 2524 6 is_stmt 0 view .LVU351
+ 1210 0014 BCF1090F 		cmp	ip, #9
+ 1211 0018 0FD0     		beq	.L108
+ 1212              	.L104:
+2525:Middlewares/Third_Party/FatFs/src/ff.c **** 		fno->fname[j++] = c;
+ 1213              		.loc 1 2525 3 is_stmt 1 view .LVU352
+ 1214              	.LVL120:
+ 1215              		.loc 1 2525 19 is_stmt 0 view .LVU353
+ 1216 001a A118     		adds	r1, r4, r2
+ 1217 001c 4B72     		strb	r3, [r1, #9]
+ 1218              		.loc 1 2525 15 view .LVU354
+ 1219 001e 0132     		adds	r2, r2, #1
+ 1220              	.LVL121:
+ 1221              	.L102:
+ 1222              		.loc 1 2525 15 view .LVU355
+ 1223 0020 6346     		mov	r3, ip
+ 1224              	.LVL122:
+ 1225              	.L101:
+2520:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (i < 11) {		/* Copy name body and extension */
+ 1226              		.loc 1 2520 8 is_stmt 1 view .LVU356
+ 1227 0022 0A2B     		cmp	r3, #10
+ 1228 0024 0ED8     		bhi	.L109
+2521:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == ' ') continue;				/* Skip padding spaces */
+ 1229              		.loc 1 2521 3 view .LVU357
+2521:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == ' ') continue;				/* Skip padding spaces */
+ 1230              		.loc 1 2521 23 is_stmt 0 view .LVU358
+ 1231 0026 03F1010C 		add	ip, r3, #1
+ 1232              	.LVL123:
+2521:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == ' ') continue;				/* Skip padding spaces */
+ 1233              		.loc 1 2521 5 view .LVU359
+ 1234 002a 296A     		ldr	r1, [r5, #32]
+ 1235 002c CB5C     		ldrb	r3, [r1, r3]	@ zero_extendqisi2
+ 1236              	.LVL124:
+2522:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+ARM GAS  /tmp/cc5lWXRL.s 			page 68
+
+
+ 1237              		.loc 1 2522 3 is_stmt 1 view .LVU360
+2522:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+ 1238              		.loc 1 2522 6 is_stmt 0 view .LVU361
+ 1239 002e 202B     		cmp	r3, #32
+ 1240 0030 F6D0     		beq	.L102
+2523:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i == 9) fno->fname[j++] = '.';	/* Insert a . if extension is exist */
+ 1241              		.loc 1 2523 3 is_stmt 1 view .LVU362
+2523:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i == 9) fno->fname[j++] = '.';	/* Insert a . if extension is exist */
+ 1242              		.loc 1 2523 6 is_stmt 0 view .LVU363
+ 1243 0032 052B     		cmp	r3, #5
+ 1244 0034 EED1     		bne	.L103
+2523:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i == 9) fno->fname[j++] = '.';	/* Insert a . if extension is exist */
+ 1245              		.loc 1 2523 21 view .LVU364
+ 1246 0036 E523     		movs	r3, #229
+ 1247              	.LVL125:
+2523:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i == 9) fno->fname[j++] = '.';	/* Insert a . if extension is exist */
+ 1248              		.loc 1 2523 21 view .LVU365
+ 1249 0038 ECE7     		b	.L103
+ 1250              	.LVL126:
+ 1251              	.L108:
+2524:Middlewares/Third_Party/FatFs/src/ff.c **** 		fno->fname[j++] = c;
+ 1252              		.loc 1 2524 15 is_stmt 1 discriminator 1 view .LVU366
+2524:Middlewares/Third_Party/FatFs/src/ff.c **** 		fno->fname[j++] = c;
+ 1253              		.loc 1 2524 31 is_stmt 0 discriminator 1 view .LVU367
+ 1254 003a A118     		adds	r1, r4, r2
+ 1255 003c 2E20     		movs	r0, #46
+ 1256 003e 4872     		strb	r0, [r1, #9]
+2524:Middlewares/Third_Party/FatFs/src/ff.c **** 		fno->fname[j++] = c;
+ 1257              		.loc 1 2524 27 discriminator 1 view .LVU368
+ 1258 0040 0132     		adds	r2, r2, #1
+ 1259              	.LVL127:
+2524:Middlewares/Third_Party/FatFs/src/ff.c **** 		fno->fname[j++] = c;
+ 1260              		.loc 1 2524 27 discriminator 1 view .LVU369
+ 1261 0042 EAE7     		b	.L104
+ 1262              	.LVL128:
+ 1263              	.L109:
+2526:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2527:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->fname[j] = 0;
+ 1264              		.loc 1 2527 2 is_stmt 1 view .LVU370
+ 1265              		.loc 1 2527 16 is_stmt 0 view .LVU371
+ 1266 0044 2244     		add	r2, r2, r4
+ 1267              	.LVL129:
+ 1268              		.loc 1 2527 16 view .LVU372
+ 1269 0046 0023     		movs	r3, #0
+ 1270              	.LVL130:
+ 1271              		.loc 1 2527 16 view .LVU373
+ 1272 0048 5372     		strb	r3, [r2, #9]
+2528:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2529:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2530:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->fattrib = dp->dir[DIR_Attr];				/* Attribute */
+ 1273              		.loc 1 2530 2 is_stmt 1 view .LVU374
+ 1274              		.loc 1 2530 19 is_stmt 0 view .LVU375
+ 1275 004a 2B6A     		ldr	r3, [r5, #32]
+ 1276              		.loc 1 2530 15 view .LVU376
+ 1277 004c DB7A     		ldrb	r3, [r3, #11]	@ zero_extendqisi2
+ 1278 004e 2372     		strb	r3, [r4, #8]
+2531:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->fsize = ld_dword(dp->dir + DIR_FileSize);	/* Size */
+ARM GAS  /tmp/cc5lWXRL.s 			page 69
+
+
+ 1279              		.loc 1 2531 2 is_stmt 1 view .LVU377
+ 1280              		.loc 1 2531 26 is_stmt 0 view .LVU378
+ 1281 0050 286A     		ldr	r0, [r5, #32]
+ 1282              		.loc 1 2531 15 view .LVU379
+ 1283 0052 1C30     		adds	r0, r0, #28
+ 1284 0054 FFF7FEFF 		bl	ld_dword
+ 1285              	.LVL131:
+ 1286              		.loc 1 2531 13 view .LVU380
+ 1287 0058 2060     		str	r0, [r4]
+2532:Middlewares/Third_Party/FatFs/src/ff.c **** 	tm = ld_dword(dp->dir + DIR_ModTime);			/* Timestamp */
+ 1288              		.loc 1 2532 2 is_stmt 1 view .LVU381
+ 1289              		.loc 1 2532 18 is_stmt 0 view .LVU382
+ 1290 005a 286A     		ldr	r0, [r5, #32]
+ 1291              		.loc 1 2532 7 view .LVU383
+ 1292 005c 1630     		adds	r0, r0, #22
+ 1293 005e FFF7FEFF 		bl	ld_dword
+ 1294              	.LVL132:
+2533:Middlewares/Third_Party/FatFs/src/ff.c **** 	fno->ftime = (WORD)tm; fno->fdate = (WORD)(tm >> 16);
+ 1295              		.loc 1 2533 2 is_stmt 1 view .LVU384
+ 1296              		.loc 1 2533 13 is_stmt 0 view .LVU385
+ 1297 0062 E080     		strh	r0, [r4, #6]	@ movhi
+ 1298              		.loc 1 2533 25 is_stmt 1 view .LVU386
+ 1299              		.loc 1 2533 38 is_stmt 0 view .LVU387
+ 1300 0064 000C     		lsrs	r0, r0, #16
+ 1301              	.LVL133:
+ 1302              		.loc 1 2533 36 view .LVU388
+ 1303 0066 A080     		strh	r0, [r4, #4]	@ movhi
+ 1304              	.LVL134:
+ 1305              	.L99:
+2534:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 1306              		.loc 1 2534 1 view .LVU389
+ 1307 0068 38BD     		pop	{r3, r4, r5, pc}
+ 1308              		.cfi_endproc
+ 1309              	.LFE1214:
+ 1311              		.section	.rodata.create_name.str1.4,"aMS",%progbits,1
+ 1312              		.align	2
+ 1313              	.LC0:
+ 1314 0000 222A2B2C 		.ascii	"\"*+,:;<=>?[]|\177\000"
+ 1314      3A3B3C3D 
+ 1314      3E3F5B5D 
+ 1314      7C7F00
+ 1315              		.section	.text.create_name,"ax",%progbits
+ 1316              		.align	1
+ 1317              		.syntax unified
+ 1318              		.thumb
+ 1319              		.thumb_func
+ 1320              		.fpu fpv5-d16
+ 1322              	create_name:
+ 1323              	.LVL135:
+ 1324              	.LFB1215:
+2535:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2536:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */
+2537:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2538:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2539:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2540:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FIND && _FS_MINIMIZE <= 1
+2541:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ARM GAS  /tmp/cc5lWXRL.s 			page 70
+
+
+2542:Middlewares/Third_Party/FatFs/src/ff.c **** /* Pattern matching                                                      */
+2543:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2544:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2545:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2546:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR get_achar (		/* Get a character and advances ptr 1 or 2 */
+2547:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR** ptr	/* Pointer to pointer to the SBCS/DBCS/Unicode string */
+2548:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2549:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2550:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_LFN_UNICODE
+2551:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR chr;
+2552:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2553:Middlewares/Third_Party/FatFs/src/ff.c **** 	chr = (BYTE)*(*ptr)++;					/* Get a byte */
+2554:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (IsLower(chr)) chr -= 0x20;			/* To upper ASCII char */
+2555:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT
+2556:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (chr >= 0x80) chr = ExCvt[chr - 0x80];	/* To upper SBCS extended char */
+2557:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+2558:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (IsDBCS1(chr) && IsDBCS2(**ptr)) {		/* Get DBC 2nd byte if needed */
+2559:Middlewares/Third_Party/FatFs/src/ff.c **** 		chr = chr << 8 | (BYTE)*(*ptr)++;
+2560:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2561:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2562:Middlewares/Third_Party/FatFs/src/ff.c **** 	return chr;
+2563:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+2564:Middlewares/Third_Party/FatFs/src/ff.c **** 	return ff_wtoupper(*(*ptr)++);			/* Get a word and to upper */
+2565:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2566:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2567:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2568:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2569:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2570:Middlewares/Third_Party/FatFs/src/ff.c **** int pattern_matching (	/* 0:not matched, 1:matched */
+2571:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* pat,	/* Matching pattern */
+2572:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* nam,	/* String to be tested */
+2573:Middlewares/Third_Party/FatFs/src/ff.c **** 	int skip,			/* Number of pre-skip chars (number of ?s) */
+2574:Middlewares/Third_Party/FatFs/src/ff.c **** 	int inf				/* Infinite search (* specified) */
+2575:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2576:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2577:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR *pp, *np;
+2578:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR pc, nc;
+2579:Middlewares/Third_Party/FatFs/src/ff.c **** 	int nm, nx;
+2580:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2581:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2582:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (skip--) {				/* Pre-skip name chars */
+2583:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!get_achar(&nam)) return 0;	/* Branch mismatched if less name chars */
+2584:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2585:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!*pat && inf) return 1;		/* (short circuit) */
+2586:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2587:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+2588:Middlewares/Third_Party/FatFs/src/ff.c **** 		pp = pat; np = nam;			/* Top of pattern and name to match */
+2589:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (;;) {
+2590:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (*pp == '?' || *pp == '*') {	/* Wildcard? */
+2591:Middlewares/Third_Party/FatFs/src/ff.c **** 				nm = nx = 0;
+2592:Middlewares/Third_Party/FatFs/src/ff.c **** 				do {				/* Analyze the wildcard chars */
+2593:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (*pp++ == '?') nm++; else nx = 1;
+2594:Middlewares/Third_Party/FatFs/src/ff.c **** 				} while (*pp == '?' || *pp == '*');
+2595:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (pattern_matching(pp, np, nm, nx)) return 1;	/* Test new branch (recurs upto number of wildc
+2596:Middlewares/Third_Party/FatFs/src/ff.c **** 				nc = *np; break;	/* Branch mismatched */
+2597:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2598:Middlewares/Third_Party/FatFs/src/ff.c **** 			pc = get_achar(&pp);	/* Get a pattern char */
+ARM GAS  /tmp/cc5lWXRL.s 			page 71
+
+
+2599:Middlewares/Third_Party/FatFs/src/ff.c **** 			nc = get_achar(&np);	/* Get a name char */
+2600:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (pc != nc) break;	/* Branch mismatched? */
+2601:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (pc == 0) return 1;	/* Branch matched? (matched at end of both strings) */
+2602:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2603:Middlewares/Third_Party/FatFs/src/ff.c **** 		get_achar(&nam);			/* nam++ */
+2604:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (inf && nc);			/* Retry until end of name if infinite search is specified */
+2605:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2606:Middlewares/Third_Party/FatFs/src/ff.c **** 	return 0;
+2607:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2608:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2609:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_FIND && _FS_MINIMIZE <= 1 */
+2610:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2611:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2612:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2613:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2614:Middlewares/Third_Party/FatFs/src/ff.c **** /* Pick a top segment and create the object name in directory form       */
+2615:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2616:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2617:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2618:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT create_name (	/* FR_OK: successful, FR_INVALID_NAME: could not create */
+2619:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,			/* Pointer to the directory object */
+2620:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR** path	/* Pointer to pointer to the segment in the path string */
+2621:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2622:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 1325              		.loc 1 2622 1 is_stmt 1 view -0
+ 1326              		.cfi_startproc
+ 1327              		@ args = 0, pretend = 0, frame = 0
+ 1328              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1329              		.loc 1 2622 1 is_stmt 0 view .LVU391
+ 1330 0000 2DE9F84F 		push	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 1331              	.LCFI13:
+ 1332              		.cfi_def_cfa_offset 40
+ 1333              		.cfi_offset 3, -40
+ 1334              		.cfi_offset 4, -36
+ 1335              		.cfi_offset 5, -32
+ 1336              		.cfi_offset 6, -28
+ 1337              		.cfi_offset 7, -24
+ 1338              		.cfi_offset 8, -20
+ 1339              		.cfi_offset 9, -16
+ 1340              		.cfi_offset 10, -12
+ 1341              		.cfi_offset 11, -8
+ 1342              		.cfi_offset 14, -4
+ 1343 0004 8146     		mov	r9, r0
+ 1344 0006 8A46     		mov	r10, r1
+2623:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+2624:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE b, cf;
+2625:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR w, *lfn;
+2626:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, ni, si, di;
+2627:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR *p;
+2628:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2629:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Create LFN in Unicode */
+2630:Middlewares/Third_Party/FatFs/src/ff.c **** 	p = *path; lfn = dp->obj.fs->lfnbuf; si = di = 0;
+2631:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (;;) {
+2632:Middlewares/Third_Party/FatFs/src/ff.c **** 		w = p[si++];					/* Get a character */
+2633:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (w < ' ') break;				/* Break if end of the path name */
+2634:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (w == '/' || w == '\\') {	/* Break if a separator is found */
+2635:Middlewares/Third_Party/FatFs/src/ff.c **** 			while (p[si] == '/' || p[si] == '\\') si++;	/* Skip duplicated separator if exist */
+ARM GAS  /tmp/cc5lWXRL.s 			page 72
+
+
+2636:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+2637:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2638:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (di >= _MAX_LFN) return FR_INVALID_NAME;	/* Reject too long name */
+2639:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_LFN_UNICODE
+2640:Middlewares/Third_Party/FatFs/src/ff.c **** 		w &= 0xFF;
+2641:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (IsDBCS1(w)) {				/* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+2642:Middlewares/Third_Party/FatFs/src/ff.c **** 			b = (BYTE)p[si++];			/* Get 2nd byte */
+2643:Middlewares/Third_Party/FatFs/src/ff.c **** 			w = (w << 8) + b;			/* Create a DBC */
+2644:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!IsDBCS2(b)) return FR_INVALID_NAME;	/* Reject invalid sequence */
+2645:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2646:Middlewares/Third_Party/FatFs/src/ff.c **** 		w = ff_convert(w, 1);			/* Convert ANSI/OEM to Unicode */
+2647:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!w) return FR_INVALID_NAME;	/* Reject invalid code */
+2648:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2649:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) return FR_INVALID_NAME;	/* Reject illegal characters
+2650:Middlewares/Third_Party/FatFs/src/ff.c **** 		lfn[di++] = w;					/* Store the Unicode character */
+2651:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2652:Middlewares/Third_Party/FatFs/src/ff.c **** 	*path = &p[si];						/* Return pointer to the next segment */
+2653:Middlewares/Third_Party/FatFs/src/ff.c **** 	cf = (w < ' ') ? NS_LAST : 0;		/* Set last segment flag if end of the path */
+2654:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0
+2655:Middlewares/Third_Party/FatFs/src/ff.c **** 	if ((di == 1 && lfn[di - 1] == '.') ||
+2656:Middlewares/Third_Party/FatFs/src/ff.c **** 		(di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) {	/* Is this segment a dot name? */
+2657:Middlewares/Third_Party/FatFs/src/ff.c **** 		lfn[di] = 0;
+2658:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < 11; i++)		/* Create dot name for SFN entry */
+2659:Middlewares/Third_Party/FatFs/src/ff.c **** 			dp->fn[i] = (i < di) ? '.' : ' ';
+2660:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->fn[i] = cf | NS_DOT;		/* This is a dot entry */
+2661:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_OK;
+2662:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2663:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2664:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (di) {						/* Snip off trailing spaces and dots if exist */
+2665:Middlewares/Third_Party/FatFs/src/ff.c **** 		w = lfn[di - 1];
+2666:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (w != ' ' && w != '.') break;
+2667:Middlewares/Third_Party/FatFs/src/ff.c **** 		di--;
+2668:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2669:Middlewares/Third_Party/FatFs/src/ff.c **** 	lfn[di] = 0;						/* LFN is created */
+2670:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (di == 0) return FR_INVALID_NAME;	/* Reject nul name */
+2671:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2672:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Create SFN in directory form */
+2673:Middlewares/Third_Party/FatFs/src/ff.c **** 	mem_set(dp->fn, ' ', 11);
+2674:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ;	/* Strip leading spaces and dots */
+2675:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (si) cf |= NS_LOSS | NS_LFN;
+2676:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (di && lfn[di - 1] != '.') di--;	/* Find extension (di<=si: no extension) */
+2677:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2678:Middlewares/Third_Party/FatFs/src/ff.c **** 	i = b = 0; ni = 8;
+2679:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (;;) {
+2680:Middlewares/Third_Party/FatFs/src/ff.c **** 		w = lfn[si++];					/* Get an LFN character */
+2681:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!w) break;					/* Break on end of the LFN */
+2682:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (w == ' ' || (w == '.' && si != di)) {	/* Remove spaces and dots */
+2683:Middlewares/Third_Party/FatFs/src/ff.c **** 			cf |= NS_LOSS | NS_LFN; continue;
+2684:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2685:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2686:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i >= ni || si == di) {		/* Extension or end of SFN */
+2687:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ni == 11) {				/* Long extension */
+2688:Middlewares/Third_Party/FatFs/src/ff.c **** 				cf |= NS_LOSS | NS_LFN; break;
+2689:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2690:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (si != di) cf |= NS_LOSS | NS_LFN;	/* Out of 8.3 format */
+2691:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (si > di) break;			/* No extension */
+2692:Middlewares/Third_Party/FatFs/src/ff.c **** 			si = di; i = 8; ni = 11;	/* Enter extension section */
+ARM GAS  /tmp/cc5lWXRL.s 			page 73
+
+
+2693:Middlewares/Third_Party/FatFs/src/ff.c **** 			b <<= 2; continue;
+2694:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2695:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2696:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (w >= 0x80) {				/* Non ASCII character */
+2697:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT
+2698:Middlewares/Third_Party/FatFs/src/ff.c **** 			w = ff_convert(w, 0);		/* Unicode -> OEM code */
+2699:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (w) w = ExCvt[w - 0x80];	/* Convert extended character to upper (SBCS) */
+2700:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+2701:Middlewares/Third_Party/FatFs/src/ff.c **** 			w = ff_convert(ff_wtoupper(w), 0);	/* Upper converted Unicode -> OEM code */
+2702:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2703:Middlewares/Third_Party/FatFs/src/ff.c **** 			cf |= NS_LFN;				/* Force create LFN entry */
+2704:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2705:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2706:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_DF1S && w >= 0x100) {		/* Is this DBC? (always false at SBCS cfg) */
+2707:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (i >= ni - 1) {
+2708:Middlewares/Third_Party/FatFs/src/ff.c **** 				cf |= NS_LOSS | NS_LFN; i = ni; continue;
+2709:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2710:Middlewares/Third_Party/FatFs/src/ff.c **** 			dp->fn[i++] = (BYTE)(w >> 8);
+2711:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {						/* SBC */
+2712:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!w || chk_chr("+,;=[]", w)) {	/* Replace illegal characters for SFN */
+2713:Middlewares/Third_Party/FatFs/src/ff.c **** 				w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+2714:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+2715:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (IsUpper(w)) {		/* ASCII large capital */
+2716:Middlewares/Third_Party/FatFs/src/ff.c **** 					b |= 2;
+2717:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+2718:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (IsLower(w)) {	/* ASCII small capital */
+2719:Middlewares/Third_Party/FatFs/src/ff.c **** 						b |= 1; w -= 0x20;
+2720:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+2721:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+2722:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2723:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2724:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->fn[i++] = (BYTE)w;
+2725:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2726:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2727:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM;	/* If the first character collides with DDEM, replace it
+2728:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2729:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (ni == 8) b <<= 2;
+2730:Middlewares/Third_Party/FatFs/src/ff.c **** 	if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN;	/* Create LFN entry when there are com
+2731:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(cf & NS_LFN)) {						/* When LFN is in 8.3 format without extended character, NT flags are c
+2732:Middlewares/Third_Party/FatFs/src/ff.c **** 		if ((b & 0x03) == 0x01) cf |= NS_EXT;	/* NT flag (Extension has only small capital) */
+2733:Middlewares/Third_Party/FatFs/src/ff.c **** 		if ((b & 0x0C) == 0x04) cf |= NS_BODY;	/* NT flag (Filename has only small capital) */
+2734:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2735:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2736:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->fn[NSFLAG] = cf;	/* SFN is created */
+2737:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2738:Middlewares/Third_Party/FatFs/src/ff.c **** 	return FR_OK;
+2739:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2740:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2741:Middlewares/Third_Party/FatFs/src/ff.c **** #else	/* _USE_LFN != 0 : Non-LFN configuration */
+2742:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE c, d, *sfn;
+ 1345              		.loc 1 2742 2 is_stmt 1 view .LVU392
+2743:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT ni, si, i;
+ 1346              		.loc 1 2743 2 view .LVU393
+2744:Middlewares/Third_Party/FatFs/src/ff.c **** 	const char *p;
+ 1347              		.loc 1 2744 2 view .LVU394
+2745:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2746:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Create file name in directory form */
+ARM GAS  /tmp/cc5lWXRL.s 			page 74
+
+
+2747:Middlewares/Third_Party/FatFs/src/ff.c **** 	p = *path; sfn = dp->fn;
+ 1348              		.loc 1 2747 2 view .LVU395
+ 1349              		.loc 1 2747 4 is_stmt 0 view .LVU396
+ 1350 0008 D1F80080 		ldr	r8, [r1]
+ 1351              	.LVL136:
+ 1352              		.loc 1 2747 13 is_stmt 1 view .LVU397
+ 1353              		.loc 1 2747 17 is_stmt 0 view .LVU398
+ 1354 000c 00F1240B 		add	fp, r0, #36
+ 1355              	.LVL137:
+2748:Middlewares/Third_Party/FatFs/src/ff.c **** 	mem_set(sfn, ' ', 11);
+ 1356              		.loc 1 2748 2 is_stmt 1 view .LVU399
+ 1357 0010 0B22     		movs	r2, #11
+ 1358 0012 2021     		movs	r1, #32
+ 1359              	.LVL138:
+ 1360              		.loc 1 2748 2 is_stmt 0 view .LVU400
+ 1361 0014 5846     		mov	r0, fp
+ 1362              	.LVL139:
+ 1363              		.loc 1 2748 2 view .LVU401
+ 1364 0016 FFF7FEFF 		bl	mem_set
+ 1365              	.LVL140:
+2749:Middlewares/Third_Party/FatFs/src/ff.c **** 	si = i = 0; ni = 8;
+ 1366              		.loc 1 2749 2 is_stmt 1 view .LVU402
+ 1367              		.loc 1 2749 14 view .LVU403
+ 1368              		.loc 1 2749 9 is_stmt 0 view .LVU404
+ 1369 001a 0025     		movs	r5, #0
+ 1370              		.loc 1 2749 5 view .LVU405
+ 1371 001c 2B46     		mov	r3, r5
+ 1372              		.loc 1 2749 17 view .LVU406
+ 1373 001e 0827     		movs	r7, #8
+ 1374 0020 29E0     		b	.L111
+ 1375              	.LVL141:
+ 1376              	.L115:
+2750:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0
+2751:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (p[si] == '.') { /* Is this a dot entry? */
+2752:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (;;) {
+2753:Middlewares/Third_Party/FatFs/src/ff.c **** 			c = (BYTE)p[si++];
+2754:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (c != '.' || si >= 3) break;
+2755:Middlewares/Third_Party/FatFs/src/ff.c **** 			sfn[i++] = c;
+2756:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2757:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
+2758:Middlewares/Third_Party/FatFs/src/ff.c **** 		*path = p + si;								/* Return pointer to the next segment */
+2759:Middlewares/Third_Party/FatFs/src/ff.c **** 		sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT;	/* Set last segment flag if end of the path
+2760:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_OK;
+2761:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2762:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2763:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (;;) {
+2764:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = (BYTE)p[si++];
+2765:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c <= ' ') break; 			/* Break if end of the path name */
+2766:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == '/' || c == '\\') {	/* Break if a separator is found */
+2767:Middlewares/Third_Party/FatFs/src/ff.c **** 			while (p[si] == '/' || p[si] == '\\') si++;	/* Skip duplicated separator if exist */
+ 1377              		.loc 1 2767 42 is_stmt 1 discriminator 2 view .LVU407
+ 1378              		.loc 1 2767 44 is_stmt 0 discriminator 2 view .LVU408
+ 1379 0022 0136     		adds	r6, r6, #1
+ 1380              	.LVL142:
+ 1381              	.L113:
+ 1382              		.loc 1 2767 10 is_stmt 1 discriminator 1 view .LVU409
+ 1383              		.loc 1 2767 12 is_stmt 0 discriminator 1 view .LVU410
+ARM GAS  /tmp/cc5lWXRL.s 			page 75
+
+
+ 1384 0024 18F80630 		ldrb	r3, [r8, r6]	@ zero_extendqisi2
+ 1385              		.loc 1 2767 10 discriminator 1 view .LVU411
+ 1386 0028 5C2B     		cmp	r3, #92
+ 1387 002a 18BF     		it	ne
+ 1388 002c 2F2B     		cmpne	r3, #47
+ 1389 002e F8D0     		beq	.L115
+ 1390              	.L112:
+2768:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+2769:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2770:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == '.' || i >= ni) {		/* End of body or over size? */
+2771:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ni == 11 || c != '.') return FR_INVALID_NAME;	/* Over size or invalid dot */
+2772:Middlewares/Third_Party/FatFs/src/ff.c **** 			i = 8; ni = 11;				/* Goto extension */
+2773:Middlewares/Third_Party/FatFs/src/ff.c **** 			continue;
+2774:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2775:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c >= 0x80) {				/* Extended character? */
+2776:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT
+2777:Middlewares/Third_Party/FatFs/src/ff.c **** 			c = ExCvt[c - 0x80];		/* To upper extended characters (SBCS cfg) */
+2778:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+2779:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_DF1S
+2780:Middlewares/Third_Party/FatFs/src/ff.c **** 			return FR_INVALID_NAME;		/* Reject extended characters (ASCII only cfg) */
+2781:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2782:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2783:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2784:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (IsDBCS1(c)) {				/* Check if it is a DBC 1st byte (always false at SBCS cfg.) */
+2785:Middlewares/Third_Party/FatFs/src/ff.c **** 			d = (BYTE)p[si++];			/* Get 2nd byte */
+2786:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!IsDBCS2(d) || i >= ni - 1) return FR_INVALID_NAME;	/* Reject invalid DBC */
+2787:Middlewares/Third_Party/FatFs/src/ff.c **** 			sfn[i++] = c;
+2788:Middlewares/Third_Party/FatFs/src/ff.c **** 			sfn[i++] = d;
+2789:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {						/* SBC */
+2790:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) return FR_INVALID_NAME;	/* Reject illegal chrs for SFN */
+2791:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (IsLower(c)) c -= 0x20;	/* To upper */
+2792:Middlewares/Third_Party/FatFs/src/ff.c **** 			sfn[i++] = c;
+2793:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2794:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2795:Middlewares/Third_Party/FatFs/src/ff.c **** 	*path = p + si;						/* Return pointer to the next segment */
+ 1391              		.loc 1 2795 2 is_stmt 1 view .LVU412
+ 1392              		.loc 1 2795 12 is_stmt 0 view .LVU413
+ 1393 0030 4644     		add	r6, r6, r8
+ 1394              	.LVL143:
+ 1395              		.loc 1 2795 8 view .LVU414
+ 1396 0032 CAF80060 		str	r6, [r10]
+2796:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (i == 0) return FR_INVALID_NAME;	/* Reject nul string */
+ 1397              		.loc 1 2796 2 is_stmt 1 view .LVU415
+ 1398              		.loc 1 2796 5 is_stmt 0 view .LVU416
+ 1399 0036 002D     		cmp	r5, #0
+ 1400 0038 44D0     		beq	.L125
+2797:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2798:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (sfn[0] == DDEM) sfn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with 
+ 1401              		.loc 1 2798 2 is_stmt 1 view .LVU417
+ 1402              		.loc 1 2798 9 is_stmt 0 view .LVU418
+ 1403 003a 99F82430 		ldrb	r3, [r9, #36]	@ zero_extendqisi2
+ 1404              		.loc 1 2798 5 view .LVU419
+ 1405 003e E52B     		cmp	r3, #229
+ 1406 0040 35D0     		beq	.L129
+ 1407              	.L121:
+2799:Middlewares/Third_Party/FatFs/src/ff.c **** 	sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0;		/* Set last segment flag if end of the path */
+ 1408              		.loc 1 2799 2 is_stmt 1 view .LVU420
+ARM GAS  /tmp/cc5lWXRL.s 			page 76
+
+
+ 1409              		.loc 1 2799 14 is_stmt 0 view .LVU421
+ 1410 0042 202C     		cmp	r4, #32
+ 1411 0044 37D8     		bhi	.L126
+ 1412 0046 0423     		movs	r3, #4
+ 1413              	.L122:
+ 1414              		.loc 1 2799 14 discriminator 4 view .LVU422
+ 1415 0048 89F82F30 		strb	r3, [r9, #47]
+2800:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2801:Middlewares/Third_Party/FatFs/src/ff.c **** 	return FR_OK;
+ 1416              		.loc 1 2801 2 is_stmt 1 discriminator 4 view .LVU423
+ 1417              		.loc 1 2801 9 is_stmt 0 discriminator 4 view .LVU424
+ 1418 004c 0020     		movs	r0, #0
+ 1419 004e 35E0     		b	.L117
+ 1420              	.LVL144:
+ 1421              	.L116:
+2775:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT
+ 1422              		.loc 1 2775 3 is_stmt 1 view .LVU425
+2775:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT
+ 1423              		.loc 1 2775 6 is_stmt 0 view .LVU426
+ 1424 0050 14F0800F 		tst	r4, #128
+ 1425 0054 27D1     		bne	.L130
+ 1426              	.L119:
+2784:Middlewares/Third_Party/FatFs/src/ff.c **** 			d = (BYTE)p[si++];			/* Get 2nd byte */
+ 1427              		.loc 1 2784 3 is_stmt 1 view .LVU427
+2790:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (IsLower(c)) c -= 0x20;	/* To upper */
+ 1428              		.loc 1 2790 4 view .LVU428
+2790:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (IsLower(c)) c -= 0x20;	/* To upper */
+ 1429              		.loc 1 2790 8 is_stmt 0 view .LVU429
+ 1430 0056 2146     		mov	r1, r4
+ 1431 0058 1B48     		ldr	r0, .L131
+ 1432 005a FFF7FEFF 		bl	chk_chr
+ 1433              	.LVL145:
+2790:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (IsLower(c)) c -= 0x20;	/* To upper */
+ 1434              		.loc 1 2790 7 view .LVU430
+ 1435 005e 78BB     		cbnz	r0, .L124
+2791:Middlewares/Third_Party/FatFs/src/ff.c **** 			sfn[i++] = c;
+ 1436              		.loc 1 2791 4 is_stmt 1 view .LVU431
+2791:Middlewares/Third_Party/FatFs/src/ff.c **** 			sfn[i++] = c;
+ 1437              		.loc 1 2791 8 is_stmt 0 view .LVU432
+ 1438 0060 A4F16103 		sub	r3, r4, #97
+ 1439 0064 DBB2     		uxtb	r3, r3
+2791:Middlewares/Third_Party/FatFs/src/ff.c **** 			sfn[i++] = c;
+ 1440              		.loc 1 2791 7 view .LVU433
+ 1441 0066 192B     		cmp	r3, #25
+ 1442 0068 01D8     		bhi	.L120
+2791:Middlewares/Third_Party/FatFs/src/ff.c **** 			sfn[i++] = c;
+ 1443              		.loc 1 2791 20 is_stmt 1 discriminator 1 view .LVU434
+2791:Middlewares/Third_Party/FatFs/src/ff.c **** 			sfn[i++] = c;
+ 1444              		.loc 1 2791 22 is_stmt 0 discriminator 1 view .LVU435
+ 1445 006a 203C     		subs	r4, r4, #32
+ 1446              	.LVL146:
+2791:Middlewares/Third_Party/FatFs/src/ff.c **** 			sfn[i++] = c;
+ 1447              		.loc 1 2791 22 discriminator 1 view .LVU436
+ 1448 006c E4B2     		uxtb	r4, r4
+ 1449              	.LVL147:
+ 1450              	.L120:
+2792:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ARM GAS  /tmp/cc5lWXRL.s 			page 77
+
+
+ 1451              		.loc 1 2792 4 is_stmt 1 view .LVU437
+2792:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 1452              		.loc 1 2792 13 is_stmt 0 view .LVU438
+ 1453 006e 0BF80540 		strb	r4, [fp, r5]
+2792:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 1454              		.loc 1 2792 9 view .LVU439
+ 1455 0072 0135     		adds	r5, r5, #1
+ 1456              	.LVL148:
+ 1457              	.L118:
+2772:Middlewares/Third_Party/FatFs/src/ff.c **** 			continue;
+ 1458              		.loc 1 2772 14 view .LVU440
+ 1459 0074 3346     		mov	r3, r6
+ 1460              	.LVL149:
+ 1461              	.L111:
+2763:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = (BYTE)p[si++];
+ 1462              		.loc 1 2763 2 is_stmt 1 view .LVU441
+2764:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c <= ' ') break; 			/* Break if end of the path name */
+ 1463              		.loc 1 2764 3 view .LVU442
+2764:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c <= ' ') break; 			/* Break if end of the path name */
+ 1464              		.loc 1 2764 17 is_stmt 0 view .LVU443
+ 1465 0076 5E1C     		adds	r6, r3, #1
+ 1466              	.LVL150:
+2764:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c <= ' ') break; 			/* Break if end of the path name */
+ 1467              		.loc 1 2764 5 view .LVU444
+ 1468 0078 18F80340 		ldrb	r4, [r8, r3]	@ zero_extendqisi2
+ 1469              	.LVL151:
+2765:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == '/' || c == '\\') {	/* Break if a separator is found */
+ 1470              		.loc 1 2765 3 is_stmt 1 view .LVU445
+2765:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == '/' || c == '\\') {	/* Break if a separator is found */
+ 1471              		.loc 1 2765 6 is_stmt 0 view .LVU446
+ 1472 007c 202C     		cmp	r4, #32
+ 1473 007e D7D9     		bls	.L112
+2766:Middlewares/Third_Party/FatFs/src/ff.c **** 			while (p[si] == '/' || p[si] == '\\') si++;	/* Skip duplicated separator if exist */
+ 1474              		.loc 1 2766 3 is_stmt 1 view .LVU447
+2766:Middlewares/Third_Party/FatFs/src/ff.c **** 			while (p[si] == '/' || p[si] == '\\') si++;	/* Skip duplicated separator if exist */
+ 1475              		.loc 1 2766 6 is_stmt 0 view .LVU448
+ 1476 0080 5C2C     		cmp	r4, #92
+ 1477 0082 18BF     		it	ne
+ 1478 0084 2F2C     		cmpne	r4, #47
+ 1479 0086 CDD0     		beq	.L113
+2770:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ni == 11 || c != '.') return FR_INVALID_NAME;	/* Over size or invalid dot */
+ 1480              		.loc 1 2770 3 is_stmt 1 view .LVU449
+2770:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ni == 11 || c != '.') return FR_INVALID_NAME;	/* Over size or invalid dot */
+ 1481              		.loc 1 2770 6 is_stmt 0 view .LVU450
+ 1482 0088 2E2C     		cmp	r4, #46
+ 1483 008a 18BF     		it	ne
+ 1484 008c AF42     		cmpne	r7, r5
+ 1485 008e DFD8     		bhi	.L116
+2771:Middlewares/Third_Party/FatFs/src/ff.c **** 			i = 8; ni = 11;				/* Goto extension */
+ 1486              		.loc 1 2771 4 is_stmt 1 view .LVU451
+2771:Middlewares/Third_Party/FatFs/src/ff.c **** 			i = 8; ni = 11;				/* Goto extension */
+ 1487              		.loc 1 2771 22 is_stmt 0 view .LVU452
+ 1488 0090 2E3C     		subs	r4, r4, #46
+ 1489              	.LVL152:
+2771:Middlewares/Third_Party/FatFs/src/ff.c **** 			i = 8; ni = 11;				/* Goto extension */
+ 1490              		.loc 1 2771 22 view .LVU453
+ 1491 0092 18BF     		it	ne
+ARM GAS  /tmp/cc5lWXRL.s 			page 78
+
+
+ 1492 0094 0124     		movne	r4, #1
+ 1493              	.LVL153:
+2771:Middlewares/Third_Party/FatFs/src/ff.c **** 			i = 8; ni = 11;				/* Goto extension */
+ 1494              		.loc 1 2771 17 view .LVU454
+ 1495 0096 0B2F     		cmp	r7, #11
+ 1496 0098 08BF     		it	eq
+ 1497 009a 44F00104 		orreq	r4, r4, #1
+2771:Middlewares/Third_Party/FatFs/src/ff.c **** 			i = 8; ni = 11;				/* Goto extension */
+ 1498              		.loc 1 2771 7 view .LVU455
+ 1499 009e 64B9     		cbnz	r4, .L123
+2772:Middlewares/Third_Party/FatFs/src/ff.c **** 			continue;
+ 1500              		.loc 1 2772 6 view .LVU456
+ 1501 00a0 0825     		movs	r5, #8
+ 1502              	.LVL154:
+2772:Middlewares/Third_Party/FatFs/src/ff.c **** 			continue;
+ 1503              		.loc 1 2772 14 view .LVU457
+ 1504 00a2 0B27     		movs	r7, #11
+ 1505              	.LVL155:
+2772:Middlewares/Third_Party/FatFs/src/ff.c **** 			continue;
+ 1506              		.loc 1 2772 14 view .LVU458
+ 1507 00a4 E6E7     		b	.L118
+ 1508              	.LVL156:
+ 1509              	.L130:
+2777:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 1510              		.loc 1 2777 4 is_stmt 1 view .LVU459
+2777:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 1511              		.loc 1 2777 16 is_stmt 0 view .LVU460
+ 1512 00a6 803C     		subs	r4, r4, #128
+ 1513              	.LVL157:
+2777:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 1514              		.loc 1 2777 6 view .LVU461
+ 1515 00a8 084B     		ldr	r3, .L131+4
+ 1516 00aa 1C5D     		ldrb	r4, [r3, r4]	@ zero_extendqisi2
+ 1517              	.LVL158:
+2777:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 1518              		.loc 1 2777 6 view .LVU462
+ 1519 00ac D3E7     		b	.L119
+ 1520              	.LVL159:
+ 1521              	.L129:
+2798:Middlewares/Third_Party/FatFs/src/ff.c **** 	sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0;		/* Set last segment flag if end of the path */
+ 1522              		.loc 1 2798 22 is_stmt 1 discriminator 1 view .LVU463
+2798:Middlewares/Third_Party/FatFs/src/ff.c **** 	sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0;		/* Set last segment flag if end of the path */
+ 1523              		.loc 1 2798 29 is_stmt 0 discriminator 1 view .LVU464
+ 1524 00ae 0523     		movs	r3, #5
+ 1525 00b0 89F82430 		strb	r3, [r9, #36]
+ 1526 00b4 C5E7     		b	.L121
+ 1527              	.L126:
+2799:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1528              		.loc 1 2799 14 view .LVU465
+ 1529 00b6 0023     		movs	r3, #0
+ 1530 00b8 C6E7     		b	.L122
+ 1531              	.LVL160:
+ 1532              	.L123:
+2771:Middlewares/Third_Party/FatFs/src/ff.c **** 			i = 8; ni = 11;				/* Goto extension */
+ 1533              		.loc 1 2771 37 view .LVU466
+ 1534 00ba 0620     		movs	r0, #6
+ 1535              	.LVL161:
+ARM GAS  /tmp/cc5lWXRL.s 			page 79
+
+
+ 1536              	.L117:
+2802:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_LFN != 0 */
+2803:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 1537              		.loc 1 2803 1 view .LVU467
+ 1538 00bc BDE8F88F 		pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 1539              	.LVL162:
+ 1540              	.L124:
+2790:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (IsLower(c)) c -= 0x20;	/* To upper */
+ 1541              		.loc 1 2790 50 view .LVU468
+ 1542 00c0 0620     		movs	r0, #6
+ 1543 00c2 FBE7     		b	.L117
+ 1544              	.LVL163:
+ 1545              	.L125:
+2796:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1546              		.loc 1 2796 21 view .LVU469
+ 1547 00c4 0620     		movs	r0, #6
+ 1548 00c6 F9E7     		b	.L117
+ 1549              	.L132:
+ 1550              		.align	2
+ 1551              	.L131:
+ 1552 00c8 00000000 		.word	.LC0
+ 1553 00cc 00000000 		.word	.LANCHOR1
+ 1554              		.cfi_endproc
+ 1555              	.LFE1215:
+ 1557              		.section	.text.get_ldnumber,"ax",%progbits
+ 1558              		.align	1
+ 1559              		.syntax unified
+ 1560              		.thumb
+ 1561              		.thumb_func
+ 1562              		.fpu fpv5-d16
+ 1564              	get_ldnumber:
+ 1565              	.LVL164:
+ 1566              	.LFB1217:
+2804:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2805:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2806:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2807:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2808:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2809:Middlewares/Third_Party/FatFs/src/ff.c **** /* Follow a file path                                                    */
+2810:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2811:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2812:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2813:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+2814:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,			/* Directory object to return last directory and found object */
+2815:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path	/* Full-path string to find a file or directory */
+2816:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2817:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2818:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+2819:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE ns;
+2820:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID *obj = &dp->obj;
+2821:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = obj->fs;
+2822:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2823:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2824:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0
+2825:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (*path != '/' && *path != '\\') {	/* Without heading separator */
+2826:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->sclust = fs->cdir;				/* Start from current directory */
+2827:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else
+ARM GAS  /tmp/cc5lWXRL.s 			page 80
+
+
+2828:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2829:Middlewares/Third_Party/FatFs/src/ff.c **** 	{										/* With heading separator */
+2830:Middlewares/Third_Party/FatFs/src/ff.c **** 		while (*path == '/' || *path == '\\') path++;	/* Strip heading separator */
+2831:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->sclust = 0;					/* Start from root directory */
+2832:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2833:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+2834:Middlewares/Third_Party/FatFs/src/ff.c **** 	obj->n_frag = 0;	/* Invalidate last fragment counter of the object */
+2835:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0
+2836:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type == FS_EXFAT && obj->sclust) {	/* Retrieve the sub-directory status if needed */
+2837:Middlewares/Third_Party/FatFs/src/ff.c **** 		DIR dj;
+2838:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2839:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->c_scl = fs->cdc_scl;
+2840:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->c_size = fs->cdc_size;
+2841:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->c_ofs = fs->cdc_ofs;
+2842:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = load_obj_dir(&dj, obj);
+2843:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) return res;
+2844:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->objsize = ld_dword(fs->dirbuf + XDIR_FileSize);
+2845:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+2846:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2847:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2848:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2849:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2850:Middlewares/Third_Party/FatFs/src/ff.c **** 	if ((UINT)*path < ' ') {				/* Null path name is the origin directory itself */
+2851:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->fn[NSFLAG] = NS_NONAME;
+2852:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = dir_sdi(dp, 0);
+2853:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2854:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else {								/* Follow path */
+2855:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (;;) {
+2856:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = create_name(dp, &path);	/* Get a segment name of the path */
+2857:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+2858:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dir_find(dp);				/* Find an object with the segment name */
+2859:Middlewares/Third_Party/FatFs/src/ff.c **** 			ns = dp->fn[NSFLAG];
+2860:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) {				/* Failed to find the object */
+2861:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) {	/* Object is not found */
+2862:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, stay there */
+2863:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (!(ns & NS_LAST)) continue;	/* Continue to follow if not last segment */
+2864:Middlewares/Third_Party/FatFs/src/ff.c **** 						dp->fn[NSFLAG] = NS_NONAME;
+2865:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = FR_OK;
+2866:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else {							/* Could not find the object */
+2867:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (!(ns & NS_LAST)) res = FR_NO_PATH;	/* Adjust error code if not last segment */
+2868:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+2869:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+2870:Middlewares/Third_Party/FatFs/src/ff.c **** 				break;
+2871:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2872:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ns & NS_LAST) break;			/* Last segment matched. Function completed. */
+2873:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Get into the sub-directory */
+2874:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!(obj->attr & AM_DIR)) {		/* It is not a sub-directory and cannot follow */
+2875:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_NO_PATH; break;
+2876:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2877:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+2878:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->fs_type == FS_EXFAT) {		/* Save containing directory information for next dir */
+2879:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->c_scl = obj->sclust;
+2880:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat;
+2881:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->c_ofs = dp->blk_ofs;
+2882:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Open next directory */
+2883:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+2884:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+ARM GAS  /tmp/cc5lWXRL.s 			page 81
+
+
+2885:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else
+2886:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2887:Middlewares/Third_Party/FatFs/src/ff.c **** 			{
+2888:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs));	/* Open next directory */
+2889:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2890:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2891:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2892:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2893:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+2894:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2895:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2896:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2897:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2898:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2899:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2900:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive number from path name                               */
+2901:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2902:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2903:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2904:Middlewares/Third_Party/FatFs/src/ff.c **** int get_ldnumber (		/* Returns logical drive number (-1:invalid drive) */
+2905:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR** path	/* Pointer to pointer to the path name */
+2906:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2907:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 1567              		.loc 1 2907 1 is_stmt 1 view -0
+ 1568              		.cfi_startproc
+ 1569              		@ args = 0, pretend = 0, frame = 0
+ 1570              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1571              		@ link register save eliminated.
+ 1572              		.loc 1 2907 1 is_stmt 0 view .LVU471
+ 1573 0000 0146     		mov	r1, r0
+2908:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR *tp, *tt;
+ 1574              		.loc 1 2908 2 is_stmt 1 view .LVU472
+2909:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+ 1575              		.loc 1 2909 2 view .LVU473
+2910:Middlewares/Third_Party/FatFs/src/ff.c **** 	int vol = -1;
+ 1576              		.loc 1 2910 2 view .LVU474
+ 1577              	.LVL165:
+2911:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STR_VOLUME_ID		/* Find string drive id */
+2912:Middlewares/Third_Party/FatFs/src/ff.c **** 	static const char* const volid[] = {_VOLUME_STRS};
+2913:Middlewares/Third_Party/FatFs/src/ff.c **** 	const char *sp;
+2914:Middlewares/Third_Party/FatFs/src/ff.c **** 	char c;
+2915:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR tc;
+2916:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2917:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2918:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2919:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (*path) {	/* If the pointer is not a null */
+ 1578              		.loc 1 2919 2 view .LVU475
+ 1579              		.loc 1 2919 6 is_stmt 0 view .LVU476
+ 1580 0002 0068     		ldr	r0, [r0]
+ 1581              	.LVL166:
+ 1582              		.loc 1 2919 5 view .LVU477
+ 1583 0004 08B1     		cbz	r0, .L142
+2920:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ;	/* Find ':' in the pa
+ 1584              		.loc 1 2920 11 view .LVU478
+ 1585 0006 0246     		mov	r2, r0
+ 1586 0008 03E0     		b	.L134
+ 1587              	.L142:
+ARM GAS  /tmp/cc5lWXRL.s 			page 82
+
+
+2910:Middlewares/Third_Party/FatFs/src/ff.c **** 	int vol = -1;
+ 1588              		.loc 1 2910 6 view .LVU479
+ 1589 000a 4FF0FF30 		mov	r0, #-1
+ 1590 000e 7047     		bx	lr
+ 1591              	.LVL167:
+ 1592              	.L136:
+ 1593              		.loc 1 2920 77 is_stmt 1 discriminator 3 view .LVU480
+ 1594              		.loc 1 2920 71 discriminator 3 view .LVU481
+ 1595              		.loc 1 2920 73 is_stmt 0 discriminator 3 view .LVU482
+ 1596 0010 0132     		adds	r2, r2, #1
+ 1597              	.LVL168:
+ 1598              	.L134:
+ 1599              		.loc 1 2920 20 is_stmt 1 discriminator 1 view .LVU483
+ 1600              		.loc 1 2920 26 is_stmt 0 discriminator 1 view .LVU484
+ 1601 0012 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
+ 1602              		.loc 1 2920 3 discriminator 1 view .LVU485
+ 1603 0014 3A2B     		cmp	r3, #58
+ 1604 0016 18BF     		it	ne
+ 1605 0018 202B     		cmpne	r3, #32
+ 1606 001a F9D8     		bhi	.L136
+2921:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (*tt == ':') {	/* If a ':' is exist in the path name */
+ 1607              		.loc 1 2921 3 is_stmt 1 view .LVU486
+ 1608              		.loc 1 2921 6 is_stmt 0 view .LVU487
+ 1609 001c 3A2B     		cmp	r3, #58
+ 1610 001e 01D0     		beq	.L143
+2922:Middlewares/Third_Party/FatFs/src/ff.c **** 			tp = *path;
+2923:Middlewares/Third_Party/FatFs/src/ff.c **** 			i = *tp++ - '0';
+2924:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (i < 10 && tp == tt) {	/* Is there a numeric drive id? */
+2925:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+2926:Middlewares/Third_Party/FatFs/src/ff.c **** 					vol = (int)i;
+2927:Middlewares/Third_Party/FatFs/src/ff.c **** 					*path = ++tt;
+2928:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+2929:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2930:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STR_VOLUME_ID
+2931:Middlewares/Third_Party/FatFs/src/ff.c **** 			 else {	/* No numeric drive number, find string drive id */
+2932:Middlewares/Third_Party/FatFs/src/ff.c **** 				i = 0; tt++;
+2933:Middlewares/Third_Party/FatFs/src/ff.c **** 				do {
+2934:Middlewares/Third_Party/FatFs/src/ff.c **** 					sp = volid[i]; tp = *path;
+2935:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {	/* Compare a string drive id with path name */
+2936:Middlewares/Third_Party/FatFs/src/ff.c **** 						c = *sp++; tc = *tp++;
+2937:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (IsLower(tc)) tc -= 0x20;
+2938:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (c && (TCHAR)c == tc);
+2939:Middlewares/Third_Party/FatFs/src/ff.c **** 				} while ((c || tp != tt) && ++i < _VOLUMES);	/* Repeat for each id until pattern match */
+2940:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+2941:Middlewares/Third_Party/FatFs/src/ff.c **** 					vol = (int)i;
+2942:Middlewares/Third_Party/FatFs/src/ff.c **** 					*path = tt;
+2943:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+2944:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+2945:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2946:Middlewares/Third_Party/FatFs/src/ff.c **** 			return vol;
+2947:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+2948:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 && _VOLUMES >= 2
+2949:Middlewares/Third_Party/FatFs/src/ff.c **** 		vol = CurrVol;	/* Current drive */
+2950:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+2951:Middlewares/Third_Party/FatFs/src/ff.c **** 		vol = 0;		/* Drive 0 */
+ 1611              		.loc 1 2951 7 view .LVU488
+ 1612 0020 0020     		movs	r0, #0
+ARM GAS  /tmp/cc5lWXRL.s 			page 83
+
+
+ 1613              	.LVL169:
+2952:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2953:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2954:Middlewares/Third_Party/FatFs/src/ff.c **** 	return vol;
+2955:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 1614              		.loc 1 2955 1 view .LVU489
+ 1615 0022 7047     		bx	lr
+ 1616              	.LVL170:
+ 1617              	.L143:
+2922:Middlewares/Third_Party/FatFs/src/ff.c **** 			tp = *path;
+ 1618              		.loc 1 2922 4 is_stmt 1 view .LVU490
+2923:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (i < 10 && tp == tt) {	/* Is there a numeric drive id? */
+ 1619              		.loc 1 2923 4 view .LVU491
+2923:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (i < 10 && tp == tt) {	/* Is there a numeric drive id? */
+ 1620              		.loc 1 2923 11 is_stmt 0 view .LVU492
+ 1621 0024 0346     		mov	r3, r0
+ 1622              	.LVL171:
+2923:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (i < 10 && tp == tt) {	/* Is there a numeric drive id? */
+ 1623              		.loc 1 2923 8 view .LVU493
+ 1624 0026 13F8010B 		ldrb	r0, [r3], #1	@ zero_extendqisi2
+ 1625              	.LVL172:
+2923:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (i < 10 && tp == tt) {	/* Is there a numeric drive id? */
+ 1626              		.loc 1 2923 14 view .LVU494
+ 1627 002a 3038     		subs	r0, r0, #48
+ 1628              	.LVL173:
+2924:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+ 1629              		.loc 1 2924 4 is_stmt 1 view .LVU495
+2924:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+ 1630              		.loc 1 2924 7 is_stmt 0 view .LVU496
+ 1631 002c 0928     		cmp	r0, #9
+ 1632 002e 98BF     		it	ls
+ 1633 0030 9A42     		cmpls	r2, r3
+ 1634 0032 03D1     		bne	.L140
+2925:Middlewares/Third_Party/FatFs/src/ff.c **** 					vol = (int)i;
+ 1635              		.loc 1 2925 5 is_stmt 1 view .LVU497
+2925:Middlewares/Third_Party/FatFs/src/ff.c **** 					vol = (int)i;
+ 1636              		.loc 1 2925 8 is_stmt 0 view .LVU498
+ 1637 0034 28B9     		cbnz	r0, .L141
+2926:Middlewares/Third_Party/FatFs/src/ff.c **** 					*path = ++tt;
+ 1638              		.loc 1 2926 6 is_stmt 1 view .LVU499
+ 1639              	.LVL174:
+2927:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 1640              		.loc 1 2927 6 view .LVU500
+2927:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 1641              		.loc 1 2927 12 is_stmt 0 view .LVU501
+ 1642 0036 0132     		adds	r2, r2, #1
+ 1643              	.LVL175:
+2927:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 1644              		.loc 1 2927 12 view .LVU502
+ 1645 0038 0A60     		str	r2, [r1]
+ 1646 003a 7047     		bx	lr
+ 1647              	.LVL176:
+ 1648              	.L140:
+2910:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STR_VOLUME_ID		/* Find string drive id */
+ 1649              		.loc 1 2910 6 view .LVU503
+ 1650 003c 4FF0FF30 		mov	r0, #-1
+ 1651              	.LVL177:
+ARM GAS  /tmp/cc5lWXRL.s 			page 84
+
+
+2910:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STR_VOLUME_ID		/* Find string drive id */
+ 1652              		.loc 1 2910 6 view .LVU504
+ 1653 0040 7047     		bx	lr
+ 1654              	.LVL178:
+ 1655              	.L141:
+2910:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STR_VOLUME_ID		/* Find string drive id */
+ 1656              		.loc 1 2910 6 view .LVU505
+ 1657 0042 4FF0FF30 		mov	r0, #-1
+ 1658              	.LVL179:
+2946:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 1659              		.loc 1 2946 4 is_stmt 1 view .LVU506
+2946:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 1660              		.loc 1 2946 11 is_stmt 0 view .LVU507
+ 1661 0046 7047     		bx	lr
+ 1662              		.cfi_endproc
+ 1663              	.LFE1217:
+ 1665              		.section	.text.putc_init,"ax",%progbits
+ 1666              		.align	1
+ 1667              		.syntax unified
+ 1668              		.thumb
+ 1669              		.thumb_func
+ 1670              		.fpu fpv5-d16
+ 1672              	putc_init:
+ 1673              	.LVL180:
+ 1674              	.LFB1241:
+2956:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2957:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2958:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2959:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2960:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2961:Middlewares/Third_Party/FatFs/src/ff.c **** /* Load a sector and check if it is an FAT boot sector                   */
+2962:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2963:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2964:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2965:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE check_fs (	/* 0:FAT, 1:exFAT, 2:Valid BS but not FAT, 3:Not a BS, 4:Disk error */
+2966:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs,	/* File system object */
+2967:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD sect	/* Sector# (lba) to load and check if it is an FAT-VBR or not */
+2968:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2969:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2970:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->wflag = 0; fs->winsect = 0xFFFFFFFF;		/* Invaidate window */
+2971:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (move_window(fs, sect) != FR_OK) return 4;	/* Load boot record */
+2972:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2973:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (ld_word(fs->win + BS_55AA) != 0xAA55) return 3;	/* Check boot record signature (always placed 
+2974:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2975:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->win[BS_JmpBoot] == 0xE9 || (fs->win[BS_JmpBoot] == 0xEB && fs->win[BS_JmpBoot + 2] == 0x90
+2976:Middlewares/Third_Party/FatFs/src/ff.c **** 		if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0;	/* Check "FAT" string *
+2977:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0;			/* Check "FAT3" string */
+2978:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+2979:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+2980:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!mem_cmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11)) return 1;
+2981:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+2982:Middlewares/Third_Party/FatFs/src/ff.c **** 	return 2;
+2983:Middlewares/Third_Party/FatFs/src/ff.c **** }
+2984:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2985:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2986:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2987:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 85
+
+
+2988:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2989:Middlewares/Third_Party/FatFs/src/ff.c **** /* Find logical drive and check if the volume is mounted                 */
+2990:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+2991:Middlewares/Third_Party/FatFs/src/ff.c **** 
+2992:Middlewares/Third_Party/FatFs/src/ff.c **** static
+2993:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
+2994:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR** path,	/* Pointer to pointer to the path name (drive number) */
+2995:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS** rfs,		/* Pointer to pointer to the found file system object */
+2996:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE mode			/* !=0: Check write protection for write access */
+2997:Middlewares/Third_Party/FatFs/src/ff.c **** )
+2998:Middlewares/Third_Party/FatFs/src/ff.c **** {
+2999:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE fmt, *pt;
+3000:Middlewares/Third_Party/FatFs/src/ff.c **** 	int vol;
+3001:Middlewares/Third_Party/FatFs/src/ff.c **** 	DSTATUS stat;
+3002:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4];
+3003:Middlewares/Third_Party/FatFs/src/ff.c **** 	WORD nrsv;
+3004:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+3005:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+3006:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3007:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3008:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive number */
+3009:Middlewares/Third_Party/FatFs/src/ff.c **** 	*rfs = 0;
+3010:Middlewares/Third_Party/FatFs/src/ff.c **** 	vol = get_ldnumber(path);
+3011:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+3012:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3013:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Check if the file system object is valid or not */
+3014:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs = FatFs[vol];					/* Get pointer to the file system object */
+3015:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!fs) return FR_NOT_ENABLED;		/* Is the file system object available? */
+3016:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3017:Middlewares/Third_Party/FatFs/src/ff.c **** 	ENTER_FF(fs);						/* Lock the volume */
+3018:Middlewares/Third_Party/FatFs/src/ff.c **** 	*rfs = fs;							/* Return pointer to the file system object */
+3019:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3020:Middlewares/Third_Party/FatFs/src/ff.c **** 	mode &= (BYTE)~FA_READ;				/* Desired access mode, write access or not */
+3021:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type) {					/* If the volume has been mounted */
+3022:Middlewares/Third_Party/FatFs/src/ff.c **** 		stat = disk_status(fs->drv);
+3023:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
+3024:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
+3025:Middlewares/Third_Party/FatFs/src/ff.c **** 				return FR_WRITE_PROTECTED;
+3026:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3027:Middlewares/Third_Party/FatFs/src/ff.c **** 			return FR_OK;				/* The file system object is valid */
+3028:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3029:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3030:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3031:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* The file system object is not valid. */
+3032:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */
+3033:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3034:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->fs_type = 0;					/* Clear the file system object */
+3035:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->drv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
+3036:Middlewares/Third_Party/FatFs/src/ff.c **** 	stat = disk_initialize(fs->drv);	/* Initialize the physical drive */
+3037:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_NOINIT) { 			/* Check if the initialization succeeded */
+3038:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
+3039:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3040:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
+3041:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_WRITE_PROTECTED;
+3042:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3043:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS					/* Get sector size (multiple sector size cfg only) */
+3044:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR;
+ARM GAS  /tmp/cc5lWXRL.s 			page 86
+
+
+3045:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+3046:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3047:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3048:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Find an FAT partition on the drive. Supports only generic partitioning rules, FDISK and SFD. */
+3049:Middlewares/Third_Party/FatFs/src/ff.c **** 	bsect = 0;
+3050:Middlewares/Third_Party/FatFs/src/ff.c **** 	fmt = check_fs(fs, bsect);			/* Load sector 0 and check if it is an FAT-VBR as SFD */
+3051:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) {	/* Not an FAT-VBR or forced partition number */
+3052:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < 4; i++) {		/* Get partition offset */
+3053:Middlewares/Third_Party/FatFs/src/ff.c **** 			pt = fs->win + (MBR_Table + i * SZ_PTE);
+3054:Middlewares/Third_Party/FatFs/src/ff.c **** 			br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
+3055:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3056:Middlewares/Third_Party/FatFs/src/ff.c **** 		i = LD2PT(vol);					/* Partition number: 0:auto, 1-4:forced */
+3057:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i) i--;
+3058:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {							/* Find an FAT volume */
+3059:Middlewares/Third_Party/FatFs/src/ff.c **** 			bsect = br[i];
+3060:Middlewares/Third_Party/FatFs/src/ff.c **** 			fmt = bsect ? check_fs(fs, bsect) : 3;	/* Check the partition */
+3061:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
+3062:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3063:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fmt == 4) return FR_DISK_ERR;		/* An error occured in the disk I/O layer */
+3064:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fmt >= 2) return FR_NO_FILESYSTEM;	/* No FAT volume is found */
+3065:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3066:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* An FAT volume is found (bsect). Following code initializes the file system object */
+3067:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3068:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+3069:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fmt == 1) {
+3070:Middlewares/Third_Party/FatFs/src/ff.c **** 		QWORD maxlba;
+3071:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3072:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ;	/* Check zero filler */
+3073:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM;
+3074:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3075:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM;	/* Check exFAT revision (Mu
+3076:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3077:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) {	/* (BPB_BytsPerSecEx must be equal to the physica
+3078:Middlewares/Third_Party/FatFs/src/ff.c **** 			return FR_NO_FILESYSTEM;
+3079:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3080:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3081:Middlewares/Third_Party/FatFs/src/ff.c **** 		maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect;	/* Last LBA + 1 of the volume */
+3082:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (maxlba >= 0x100000000) return FR_NO_FILESYSTEM;	/* (It cannot be handled in 32-bit LBA) */
+3083:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3084:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsize = ld_dword(fs->win + BPB_FatSzEx);	/* Number of sectors per FAT */
+3085:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3086:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->n_fats = fs->win[BPB_NumFATsEx];			/* Number of FATs */
+3087:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->n_fats != 1) return FR_NO_FILESYSTEM;	/* (Supports only 1 FAT) */
+3088:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3089:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->csize = 1 << fs->win[BPB_SecPerClusEx];		/* Cluster size */
+3090:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->csize == 0)	return FR_NO_FILESYSTEM;	/* (Must be 1..32768) */
+3091:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3092:Middlewares/Third_Party/FatFs/src/ff.c **** 		nclst = ld_dword(fs->win + BPB_NumClusEx);		/* Number of clusters */
+3093:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM;	/* (Too many clusters) */
+3094:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->n_fatent = nclst + 2;
+3095:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3096:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Boundaries and Limits */
+3097:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->volbase = bsect;
+3098:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx);
+3099:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx);
+3100:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM;	/* (Volume size mu
+3101:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->dirbase = ld_dword(fs->win + BPB_RootClusEx);
+ARM GAS  /tmp/cc5lWXRL.s 			page 87
+
+
+3102:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3103:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Check if bitmap location is in assumption (at the first cluster) */
+3104:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (move_window(fs, clust2sect(fs, fs->dirbase)) != FR_OK) return FR_DISK_ERR;
+3105:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < SS(fs); i += SZDIRE) {
+3106:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->win[i] == 0x81 && ld_dword(fs->win + i + 20) == 2) break;	/* 81 entry with cluster #2? *
+3107:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3108:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i == SS(fs)) return FR_NO_FILESYSTEM;
+3109:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+3110:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+3111:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3112:Middlewares/Third_Party/FatFs/src/ff.c **** 		fmt = FS_EXFAT;			/* FAT sub-type */
+3113:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else
+3114:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _FS_EXFAT */
+3115:Middlewares/Third_Party/FatFs/src/ff.c **** 	{
+3116:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_BytsPerSec must
+3117:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3118:Middlewares/Third_Party/FatFs/src/ff.c **** 		fasize = ld_word(fs->win + BPB_FATSz16);		/* Number of sectors per FAT */
+3119:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
+3120:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsize = fasize;
+3121:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3122:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->n_fats = fs->win[BPB_NumFATs];				/* Number of FATs */
+3123:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM;	/* (Must be 1 or 2) */
+3124:Middlewares/Third_Party/FatFs/src/ff.c **** 		fasize *= fs->n_fats;							/* Number of sectors for FAT area */
+3125:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3126:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->csize = fs->win[BPB_SecPerClus];			/* Cluster size */
+3127:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM;	/* (Must be power o
+3128:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3129:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt);	/* Number of root directory entries */
+3130:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM;	/* (Must be sector aligned) */
+3131:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3132:Middlewares/Third_Party/FatFs/src/ff.c **** 		tsect = ld_word(fs->win + BPB_TotSec16);		/* Number of sectors on the volume */
+3133:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
+3134:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3135:Middlewares/Third_Party/FatFs/src/ff.c **** 		nrsv = ld_word(fs->win + BPB_RsvdSecCnt);		/* Number of reserved sectors */
+3136:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nrsv == 0) return FR_NO_FILESYSTEM;			/* (Must not be 0) */
+3137:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3138:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Determine the FAT sub type */
+3139:Middlewares/Third_Party/FatFs/src/ff.c **** 		sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE);	/* RSV + FAT + DIR */
+3140:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (tsect < sysect) return FR_NO_FILESYSTEM;	/* (Invalid volume size) */
+3141:Middlewares/Third_Party/FatFs/src/ff.c **** 		nclst = (tsect - sysect) / fs->csize;			/* Number of clusters */
+3142:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst == 0) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
+3143:Middlewares/Third_Party/FatFs/src/ff.c **** 		fmt = FS_FAT32;
+3144:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst <= MAX_FAT16) fmt = FS_FAT16;
+3145:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst <= MAX_FAT12) fmt = FS_FAT12;
+3146:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3147:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Boundaries and Limits */
+3148:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->n_fatent = nclst + 2;						/* Number of FAT entries */
+3149:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->volbase = bsect;							/* Volume start sector */
+3150:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fatbase = bsect + nrsv; 					/* FAT start sector */
+3151:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->database = bsect + sysect;					/* Data start sector */
+3152:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fmt == FS_FAT32) {
+3153:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM;	/* (Must be FAT32 revision 0.0
+3154:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->n_rootdir) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
+3155:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->dirbase = ld_dword(fs->win + BPB_RootClus32);	/* Root directory start cluster */
+3156:Middlewares/Third_Party/FatFs/src/ff.c **** 			szbfat = fs->n_fatent * 4;					/* (Needed FAT size) */
+3157:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+3158:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->n_rootdir == 0)	return FR_NO_FILESYSTEM;/* (BPB_RootEntCnt must not be 0) */
+ARM GAS  /tmp/cc5lWXRL.s 			page 88
+
+
+3159:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->dirbase = fs->fatbase + fasize;			/* Root directory start sector */
+3160:Middlewares/Third_Party/FatFs/src/ff.c **** 			szbfat = (fmt == FS_FAT16) ?				/* (Needed FAT size) */
+3161:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+3162:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3163:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_FATSz must not
+3164:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3165:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+3166:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Get FSINFO if available */
+3167:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+3168:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag = 0x80;
+3169:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_FS_NOFSINFO & 3) != 3
+3170:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fmt == FS_FAT32				/* Enable FSINFO only if FAT32 and BPB_FSInfo32 == 1 */
+3171:Middlewares/Third_Party/FatFs/src/ff.c **** 			&& ld_word(fs->win + BPB_FSInfo32) == 1
+3172:Middlewares/Third_Party/FatFs/src/ff.c **** 			&& move_window(fs, bsect + 1) == FR_OK)
+3173:Middlewares/Third_Party/FatFs/src/ff.c **** 		{
+3174:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->fsi_flag = 0;
+3175:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ld_word(fs->win + BS_55AA) == 0xAA55	/* Load FSINFO data if available */
+3176:Middlewares/Third_Party/FatFs/src/ff.c **** 				&& ld_dword(fs->win + FSI_LeadSig) == 0x41615252
+3177:Middlewares/Third_Party/FatFs/src/ff.c **** 				&& ld_dword(fs->win + FSI_StrucSig) == 0x61417272)
+3178:Middlewares/Third_Party/FatFs/src/ff.c **** 			{
+3179:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_FS_NOFSINFO & 1) == 0
+3180:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->free_clst = ld_dword(fs->win + FSI_Free_Count);
+3181:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3182:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_FS_NOFSINFO & 2) == 0
+3183:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free);
+3184:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3185:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3186:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3187:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* (_FS_NOFSINFO & 3) != 3 */
+3188:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* !_FS_READONLY */
+3189:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3190:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3191:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->fs_type = fmt;		/* FAT sub-type */
+3192:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->id = ++Fsid;		/* File system mount ID */
+3193:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1
+3194:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->lfnbuf = LfnBuf;	/* Static LFN working buffer */
+3195:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+3196:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->dirbuf = DirBuf;	/* Static directory block scratchpad buuffer */
+3197:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3198:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3199:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0
+3200:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->cdir = 0;			/* Initialize current directory */
+3201:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3202:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0			/* Clear file lock semaphores */
+3203:Middlewares/Third_Party/FatFs/src/ff.c **** 	clear_lock(fs);
+3204:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3205:Middlewares/Third_Party/FatFs/src/ff.c **** 	return FR_OK;
+3206:Middlewares/Third_Party/FatFs/src/ff.c **** }
+3207:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3208:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3209:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3210:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3211:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3212:Middlewares/Third_Party/FatFs/src/ff.c **** /* Check if the file/directory object is valid or not                    */
+3213:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3214:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3215:Middlewares/Third_Party/FatFs/src/ff.c **** static
+ARM GAS  /tmp/cc5lWXRL.s 			page 89
+
+
+3216:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT validate (	/* Returns FR_OK or FR_INVALID_OBJECT */
+3217:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID* obj,		/* Pointer to the _OBJ, the 1st member in the FIL/DIR object, to check validity */
+3218:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS** fs		/* Pointer to pointer to the owner file system object to return */
+3219:Middlewares/Third_Party/FatFs/src/ff.c **** )
+3220:Middlewares/Third_Party/FatFs/src/ff.c **** {
+3221:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_INVALID_OBJECT;
+3222:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3223:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3224:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) {	/* Test if the object is valid
+3225:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+3226:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (lock_fs(obj->fs)) {	/* Obtain the filesystem object */
+3227:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!(disk_status(obj->fs->drv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialize
+3228:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_OK;
+3229:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+3230:Middlewares/Third_Party/FatFs/src/ff.c **** 				unlock_fs(obj->fs, FR_OK);
+3231:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3232:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+3233:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_TIMEOUT;
+3234:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3235:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+3236:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(disk_status(obj->fs->drv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized
+3237:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+3238:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3239:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3240:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3241:Middlewares/Third_Party/FatFs/src/ff.c **** 	*fs = (res == FR_OK) ? obj->fs : 0;	/* Corresponding filesystem object */
+3242:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+3243:Middlewares/Third_Party/FatFs/src/ff.c **** }
+3244:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3245:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3246:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3247:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3248:Middlewares/Third_Party/FatFs/src/ff.c **** /*---------------------------------------------------------------------------
+3249:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3250:Middlewares/Third_Party/FatFs/src/ff.c ****    Public Functions (FatFs API)
+3251:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3252:Middlewares/Third_Party/FatFs/src/ff.c **** ----------------------------------------------------------------------------*/
+3253:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3254:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3255:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3256:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3257:Middlewares/Third_Party/FatFs/src/ff.c **** /* Mount/Unmount a Logical Drive                                         */
+3258:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3259:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3260:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_mount (
+3261:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS* fs,			/* Pointer to the file system object (NULL:unmount)*/
+3262:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path,	/* Logical drive number to be mounted/unmounted */
+3263:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE opt			/* Mode option 0:Do not mount (delayed mount), 1:Mount immediately */
+3264:Middlewares/Third_Party/FatFs/src/ff.c **** )
+3265:Middlewares/Third_Party/FatFs/src/ff.c **** {
+3266:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *cfs;
+3267:Middlewares/Third_Party/FatFs/src/ff.c **** 	int vol;
+3268:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+3269:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR *rp = path;
+3270:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3271:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3272:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive number */
+ARM GAS  /tmp/cc5lWXRL.s 			page 90
+
+
+3273:Middlewares/Third_Party/FatFs/src/ff.c **** 	vol = get_ldnumber(&rp);
+3274:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+3275:Middlewares/Third_Party/FatFs/src/ff.c **** 	cfs = FatFs[vol];					/* Pointer to fs object */
+3276:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3277:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (cfs) {
+3278:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+3279:Middlewares/Third_Party/FatFs/src/ff.c **** 		clear_lock(cfs);
+3280:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3281:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT						/* Discard sync object of the current volume */
+3282:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR;
+3283:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3284:Middlewares/Third_Party/FatFs/src/ff.c **** 		cfs->fs_type = 0;				/* Clear old fs object */
+3285:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3286:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3287:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs) {
+3288:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fs_type = 0;				/* Clear new fs object */
+3289:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT						/* Create sync object for the new volume */
+3290:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR;
+3291:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3292:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3293:Middlewares/Third_Party/FatFs/src/ff.c **** 	FatFs[vol] = fs;					/* Register new fs object */
+3294:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3295:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!fs || opt != 1) return FR_OK;	/* Do not mount now, it will be mounted later */
+3296:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3297:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, 0);	/* Force mounted the volume */
+3298:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+3299:Middlewares/Third_Party/FatFs/src/ff.c **** }
+3300:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3301:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3302:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3303:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3304:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3305:Middlewares/Third_Party/FatFs/src/ff.c **** /* Open or Create a File                                                 */
+3306:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3307:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3308:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_open (
+3309:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp,			/* Pointer to the blank file object */
+3310:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path,	/* Pointer to the file name */
+3311:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE mode			/* Access mode and file open mode flags */
+3312:Middlewares/Third_Party/FatFs/src/ff.c **** )
+3313:Middlewares/Third_Party/FatFs/src/ff.c **** {
+3314:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+3315:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+3316:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+3317:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+3318:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD dw, cl, bcs, clst, sc;
+3319:Middlewares/Third_Party/FatFs/src/ff.c **** 	FSIZE_t ofs;
+3320:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3321:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+3322:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3323:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3324:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!fp) return FR_INVALID_OBJECT;
+3325:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3326:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive */
+3327:Middlewares/Third_Party/FatFs/src/ff.c **** 	mode &= _FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_A
+3328:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, mode);
+3329:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ARM GAS  /tmp/cc5lWXRL.s 			page 91
+
+
+3330:Middlewares/Third_Party/FatFs/src/ff.c **** 		dj.obj.fs = fs;
+3331:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+3332:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&dj, path);	/* Follow the file path */
+3333:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY	/* R/W configuration */
+3334:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+3335:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+3336:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;
+3337:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3338:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+3339:Middlewares/Third_Party/FatFs/src/ff.c **** 			else {
+3340:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+3341:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3342:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3343:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3344:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Create or Open a file */
+3345:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+3346:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) {					/* No file, create new */
+3347:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) {		/* There is no file to open, create a new entry */
+3348:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+3349:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+3350:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+3351:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = dir_register(&dj);
+3352:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3353:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3354:Middlewares/Third_Party/FatFs/src/ff.c **** 				mode |= FA_CREATE_ALWAYS;		/* File is created */
+3355:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3356:Middlewares/Third_Party/FatFs/src/ff.c **** 			else {								/* Any object is already existing */
+3357:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (dj.obj.attr & (AM_RDO | AM_DIR)) {	/* Cannot overwrite it (R/O or DIR) */
+3358:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_DENIED;
+3359:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+3360:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (mode & FA_CREATE_NEW) res = FR_EXIST;	/* Cannot create as new file */
+3361:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3362:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3363:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) {	/* Truncate it if overwrite mode */
+3364:Middlewares/Third_Party/FatFs/src/ff.c **** 				dw = GET_FATTIME();
+3365:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+3366:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fs->fs_type == FS_EXFAT) {
+3367:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Get current allocation info */
+3368:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.fs = fs;
+3369:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus);
+3370:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+3371:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+3372:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.n_frag = 0;
+3373:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Initialize directory entry block */
+3374:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(fs->dirbuf + XDIR_CrtTime, dw);	/* Set created time */
+3375:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->dirbuf[XDIR_CrtTime10] = 0;
+3376:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(fs->dirbuf + XDIR_ModTime, dw);	/* Set modified time */
+3377:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->dirbuf[XDIR_ModTime10] = 0;
+3378:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->dirbuf[XDIR_Attr] = AM_ARC;				/* Reset attribute */
+3379:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(fs->dirbuf + XDIR_FstClus, 0);		/* Reset file allocation info */
+3380:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_qword(fs->dirbuf + XDIR_FileSize, 0);
+3381:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_qword(fs->dirbuf + XDIR_ValidFileSize, 0);
+3382:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->dirbuf[XDIR_GenFlags] = 1;
+3383:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = store_xdir(&dj);
+3384:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res == FR_OK && fp->obj.sclust) {		/* Remove the cluster chain if exist */
+3385:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+3386:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->last_clst = fp->obj.sclust - 1;		/* Reuse the cluster hole */
+ARM GAS  /tmp/cc5lWXRL.s 			page 92
+
+
+3387:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+3388:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else
+3389:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3390:Middlewares/Third_Party/FatFs/src/ff.c **** 				{
+3391:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Clean directory info */
+3392:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dj.dir + DIR_CrtTime, dw);	/* Set created time */
+3393:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dj.dir + DIR_ModTime, dw);	/* Set modified time */
+3394:Middlewares/Third_Party/FatFs/src/ff.c **** 					dj.dir[DIR_Attr] = AM_ARC;			/* Reset attribute */
+3395:Middlewares/Third_Party/FatFs/src/ff.c **** 					cl = ld_clust(fs, dj.dir);			/* Get cluster chain */
+3396:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dj.dir, 0);			/* Reset file allocation info */
+3397:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dj.dir + DIR_FileSize, 0);
+3398:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+3399:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3400:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (cl) {							/* Remove the cluster chain if exist */
+3401:Middlewares/Third_Party/FatFs/src/ff.c **** 						dw = fs->winsect;
+3402:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = remove_chain(&dj.obj, cl, 0);
+3403:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (res == FR_OK) {
+3404:Middlewares/Third_Party/FatFs/src/ff.c **** 							res = move_window(fs, dw);
+3405:Middlewares/Third_Party/FatFs/src/ff.c **** 							fs->last_clst = cl - 1;		/* Reuse the cluster hole */
+3406:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+3407:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+3408:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3409:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3410:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3411:Middlewares/Third_Party/FatFs/src/ff.c **** 		else {	/* Open an existing file */
+3412:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {					/* Following succeeded */
+3413:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (dj.obj.attr & AM_DIR) {		/* It is a directory */
+3414:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_NO_FILE;
+3415:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+3416:Middlewares/Third_Party/FatFs/src/ff.c **** 					if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* R/O violation */
+3417:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = FR_DENIED;
+3418:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+3419:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3420:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3421:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3422:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+3423:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (mode & FA_CREATE_ALWAYS)		/* Set file change flag if created or overwritten */
+3424:Middlewares/Third_Party/FatFs/src/ff.c **** 				mode |= FA_MODIFIED;
+3425:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->dir_sect = fs->winsect;			/* Pointer to the directory entry */
+3426:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->dir_ptr = dj.dir;
+3427:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+3428:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+3429:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!fp->obj.lockid) res = FR_INT_ERR;
+3430:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3431:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3432:Middlewares/Third_Party/FatFs/src/ff.c **** #else		/* R/O configuration */
+3433:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+3434:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+3435:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;
+3436:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+3437:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (dj.obj.attr & AM_DIR) {		/* It is a directory */
+3438:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_NO_FILE;
+3439:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3440:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3441:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3442:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3443:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 93
+
+
+3444:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+3445:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+3446:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->fs_type == FS_EXFAT) {
+3447:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.c_scl = dj.obj.sclust;							/* Get containing directory info */
+3448:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+3449:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.c_ofs = dj.blk_ofs;
+3450:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Get object allocation info */
+3451:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+3452:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+3453:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else
+3454:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3455:Middlewares/Third_Party/FatFs/src/ff.c **** 			{
+3456:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.sclust = ld_clust(fs, dj.dir);					/* Get object allocation info */
+3457:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+3458:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3459:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK
+3460:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->cltbl = 0;			/* Disable fast seek mode */
+3461:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3462:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.fs = fs;	 	/* Validate the file object */
+3463:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.id = fs->id;
+3464:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->flag = mode;		/* Set file access mode */
+3465:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->err = 0;			/* Clear error flag */
+3466:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->sect = 0;			/* Invalidate current data sector */
+3467:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->fptr = 0;			/* Set file pointer top of the file */
+3468:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+3469:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+3470:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(fp->buf, 0, _MAX_SS);	/* Clear sector buffer */
+3471:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3472:Middlewares/Third_Party/FatFs/src/ff.c **** 			if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) {	/* Seek to end of file if FA_OPEN_APPEND is sp
+3473:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr = fp->obj.objsize;			/* Offset to seek */
+3474:Middlewares/Third_Party/FatFs/src/ff.c **** 				bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size in byte */
+3475:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = fp->obj.sclust;				/* Follow the cluster chain */
+3476:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
+3477:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = get_fat(&fp->obj, clst);
+3478:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst <= 1) res = FR_INT_ERR;
+3479:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
+3480:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3481:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;
+3482:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK && ofs % SS(fs)) {	/* Fill sector buffer if not on the sector boundary */
+3483:Middlewares/Third_Party/FatFs/src/ff.c **** 					if ((sc = clust2sect(fs, clst)) == 0) {
+3484:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = FR_INT_ERR;
+3485:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else {
+3486:Middlewares/Third_Party/FatFs/src/ff.c **** 						fp->sect = sc + (DWORD)(ofs / SS(fs));
+3487:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+3488:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (disk_read(fs->drv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR;
+3489:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3490:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+3491:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3492:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3493:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3494:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3495:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3496:Middlewares/Third_Party/FatFs/src/ff.c **** 		FREE_NAMBUF();
+3497:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3498:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3499:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK) fp->obj.fs = 0;	/* Invalidate file object on error */
+3500:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 94
+
+
+3501:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+3502:Middlewares/Third_Party/FatFs/src/ff.c **** }
+3503:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3504:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3505:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3506:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3507:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3508:Middlewares/Third_Party/FatFs/src/ff.c **** /* Read File                                                             */
+3509:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3510:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3511:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_read (
+3512:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp, 	/* Pointer to the file object */
+3513:Middlewares/Third_Party/FatFs/src/ff.c **** 	void* buff,	/* Pointer to data buffer */
+3514:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT btr,	/* Number of bytes to read */
+3515:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT* br	/* Pointer to number of bytes read */
+3516:Middlewares/Third_Party/FatFs/src/ff.c **** )
+3517:Middlewares/Third_Party/FatFs/src/ff.c **** {
+3518:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+3519:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+3520:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst, sect;
+3521:Middlewares/Third_Party/FatFs/src/ff.c **** 	FSIZE_t remain;
+3522:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT rcnt, cc, csect;
+3523:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *rbuff = (BYTE*)buff;
+3524:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3525:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3526:Middlewares/Third_Party/FatFs/src/ff.c **** 	*br = 0;	/* Clear read byte counter */
+3527:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);				/* Check validity of the file object */
+3528:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+3529:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+3530:Middlewares/Third_Party/FatFs/src/ff.c **** 	remain = fp->obj.objsize - fp->fptr;
+3531:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+3532:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3533:Middlewares/Third_Party/FatFs/src/ff.c **** 	for ( ;  btr;								/* Repeat until all data read */
+3534:Middlewares/Third_Party/FatFs/src/ff.c **** 		rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+3535:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {			/* On the sector boundary? */
+3536:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+3537:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (csect == 0) {					/* On the cluster boundary? */
+3538:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr == 0) {			/* On the top of the file? */
+3539:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = fp->obj.sclust;		/* Follow cluster chain from the origin */
+3540:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {						/* Middle or end of the file */
+3541:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK
+3542:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (fp->cltbl) {
+3543:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+3544:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else
+3545:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3546:Middlewares/Third_Party/FatFs/src/ff.c **** 					{
+3547:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = get_fat(&fp->obj, fp->clust);	/* Follow cluster chain on the FAT */
+3548:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+3549:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3550:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst < 2) ABORT(fs, FR_INT_ERR);
+3551:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+3552:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;				/* Update current cluster */
+3553:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3554:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect = clust2sect(fs, fp->clust);	/* Get current sector */
+3555:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!sect) ABORT(fs, FR_INT_ERR);
+3556:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+3557:Middlewares/Third_Party/FatFs/src/ff.c **** 			cc = btr / SS(fs);					/* When remaining bytes >= sector size, */
+ARM GAS  /tmp/cc5lWXRL.s 			page 95
+
+
+3558:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cc) {							/* Read maximum contiguous sectors directly */
+3559:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+3560:Middlewares/Third_Party/FatFs/src/ff.c **** 					cc = fs->csize - csect;
+3561:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3562:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_read(fs->drv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+3563:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it 
+3564:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+3565:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fs->wflag && fs->winsect - sect < cc) {
+3566:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs));
+3567:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3568:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+3569:Middlewares/Third_Party/FatFs/src/ff.c **** 				if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) {
+3570:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+3571:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3572:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3573:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3574:Middlewares/Third_Party/FatFs/src/ff.c **** 				rcnt = SS(fs) * cc;				/* Number of bytes transferred */
+3575:Middlewares/Third_Party/FatFs/src/ff.c **** 				continue;
+3576:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3577:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+3578:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fp->sect != sect) {			/* Load data sector if not in cache */
+3579:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+3580:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+3581:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+3582:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+3583:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3584:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3585:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK)	ABORT(fs, FR_DISK_ERR);	/* Fill sector cach
+3586:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3587:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3588:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->sect = sect;
+3589:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3590:Middlewares/Third_Party/FatFs/src/ff.c **** 		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+3591:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rcnt > btr) rcnt = btr;					/* Clip it by btr if needed */
+3592:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+3593:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+3594:Middlewares/Third_Party/FatFs/src/ff.c **** 		mem_cpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+3595:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+3596:Middlewares/Third_Party/FatFs/src/ff.c **** 		mem_cpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+3597:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3598:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3599:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3600:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, FR_OK);
+3601:Middlewares/Third_Party/FatFs/src/ff.c **** }
+3602:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3603:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3604:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3605:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3606:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+3607:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3608:Middlewares/Third_Party/FatFs/src/ff.c **** /* Write File                                                            */
+3609:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3610:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3611:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_write (
+3612:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp,			/* Pointer to the file object */
+3613:Middlewares/Third_Party/FatFs/src/ff.c **** 	const void* buff,	/* Pointer to the data to be written */
+3614:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT btw,			/* Number of bytes to write */
+ARM GAS  /tmp/cc5lWXRL.s 			page 96
+
+
+3615:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT* bw			/* Pointer to number of bytes written */
+3616:Middlewares/Third_Party/FatFs/src/ff.c **** )
+3617:Middlewares/Third_Party/FatFs/src/ff.c **** {
+3618:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+3619:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+3620:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst, sect;
+3621:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT wcnt, cc, csect;
+3622:Middlewares/Third_Party/FatFs/src/ff.c **** 	const BYTE *wbuff = (const BYTE*)buff;
+3623:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3624:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3625:Middlewares/Third_Party/FatFs/src/ff.c **** 	*bw = 0;	/* Clear write byte counter */
+3626:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
+3627:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+3628:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+3629:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3630:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Check fptr wrap-around (file size cannot reach 4GiB on FATxx) */
+3631:Middlewares/Third_Party/FatFs/src/ff.c **** 	if ((!_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) {
+3632:Middlewares/Third_Party/FatFs/src/ff.c **** 		btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
+3633:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3634:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3635:Middlewares/Third_Party/FatFs/src/ff.c **** 	for ( ;  btw;							/* Repeat until all data written */
+3636:Middlewares/Third_Party/FatFs/src/ff.c **** 		wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->
+3637:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+3638:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1);	/* Sector offset in the cluster */
+3639:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (csect == 0) {				/* On the cluster boundary? */
+3640:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr == 0) {		/* On the top of the file? */
+3641:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = fp->obj.sclust;	/* Follow from the origin */
+3642:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0) {		/* If no cluster is allocated, */
+3643:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = create_chain(&fp->obj, 0);	/* create a new cluster chain */
+3644:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+3645:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {					/* On the middle or end of the file */
+3646:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK
+3647:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (fp->cltbl) {
+3648:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+3649:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else
+3650:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3651:Middlewares/Third_Party/FatFs/src/ff.c **** 					{
+3652:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = create_chain(&fp->obj, fp->clust);	/* Follow or stretch cluster chain on the FAT */
+3653:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+3654:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3655:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0) break;		/* Could not allocate a new cluster (disk full) */
+3656:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 1) ABORT(fs, FR_INT_ERR);
+3657:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+3658:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;			/* Update current cluster */
+3659:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->obj.sclust == 0) fp->obj.sclust = clst;	/* Set start cluster if the first write */
+3660:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3661:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+3662:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Write-back s
+3663:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+3664:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fp->flag & FA_DIRTY) {		/* Write-back sector cache */
+3665:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+3666:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+3667:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3668:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3669:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect = clust2sect(fs, fp->clust);	/* Get current sector */
+3670:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!sect) ABORT(fs, FR_INT_ERR);
+3671:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ARM GAS  /tmp/cc5lWXRL.s 			page 97
+
+
+3672:Middlewares/Third_Party/FatFs/src/ff.c **** 			cc = btw / SS(fs);				/* When remaining bytes >= sector size, */
+3673:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cc) {						/* Write maximum contiguous sectors directly */
+3674:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+3675:Middlewares/Third_Party/FatFs/src/ff.c **** 					cc = fs->csize - csect;
+3676:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3677:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+3678:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2
+3679:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+3680:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fs->winsect - sect < cc) {	/* Refill sector cache if it gets invalidated by the direct writ
+3681:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs));
+3682:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 0;
+3683:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3684:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+3685:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write *
+3686:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
+3687:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+3688:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3689:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3690:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3691:Middlewares/Third_Party/FatFs/src/ff.c **** 				wcnt = SS(fs) * cc;		/* Number of bytes transferred */
+3692:Middlewares/Third_Party/FatFs/src/ff.c **** 				continue;
+3693:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3694:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+3695:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fp->fptr >= fp->obj.objsize) {	/* Avoid silly cache filling on the growing edge */
+3696:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);
+3697:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->winsect = sect;
+3698:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3699:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+3700:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fp->sect != sect && 		/* Fill sector cache with file data */
+3701:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr < fp->obj.objsize &&
+3702:Middlewares/Third_Party/FatFs/src/ff.c **** 				disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) {
+3703:Middlewares/Third_Party/FatFs/src/ff.c **** 					ABORT(fs, FR_DISK_ERR);
+3704:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3705:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3706:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->sect = sect;
+3707:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3708:Middlewares/Third_Party/FatFs/src/ff.c **** 		wcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+3709:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (wcnt > btw) wcnt = btw;					/* Clip it by btw if needed */
+3710:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+3711:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+3712:Middlewares/Third_Party/FatFs/src/ff.c **** 		mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+3713:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->wflag = 1;
+3714:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+3715:Middlewares/Third_Party/FatFs/src/ff.c **** 		mem_cpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+3716:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->flag |= FA_DIRTY;
+3717:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3718:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3719:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3720:Middlewares/Third_Party/FatFs/src/ff.c **** 	fp->flag |= FA_MODIFIED;				/* Set file change flag */
+3721:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3722:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, FR_OK);
+3723:Middlewares/Third_Party/FatFs/src/ff.c **** }
+3724:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3725:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3726:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3727:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3728:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ARM GAS  /tmp/cc5lWXRL.s 			page 98
+
+
+3729:Middlewares/Third_Party/FatFs/src/ff.c **** /* Synchronize the File                                                  */
+3730:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3731:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3732:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_sync (
+3733:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp		/* Pointer to the file object */
+3734:Middlewares/Third_Party/FatFs/src/ff.c **** )
+3735:Middlewares/Third_Party/FatFs/src/ff.c **** {
+3736:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+3737:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+3738:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD tm;
+3739:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *dir;
+3740:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+3741:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+3742:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+3743:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3744:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3745:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+3746:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+3747:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->flag & FA_MODIFIED) {	/* Is there any change to the file? */
+3748:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+3749:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fp->flag & FA_DIRTY) {	/* Write-back cached data if needed */
+3750:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR);
+3751:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+3752:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3753:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3754:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Update the directory entry */
+3755:Middlewares/Third_Party/FatFs/src/ff.c **** 			tm = GET_FATTIME();				/* Modified time */
+3756:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+3757:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->fs_type == FS_EXFAT) {
+3758:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = fill_first_frag(&fp->obj);	/* Fill first fragment on the FAT if needed */
+3759:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {
+3760:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if nee
+3761:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3762:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {
+3763:Middlewares/Third_Party/FatFs/src/ff.c **** 					INIT_NAMBUF(fs);
+3764:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = load_obj_dir(&dj, &fp->obj);	/* Load directory entry block */
+3765:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res == FR_OK) {
+3766:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->dirbuf[XDIR_Attr] |= AM_ARC;				/* Set archive bit */
+3767:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1;	/* Update file allocation info */
+3768:Middlewares/Third_Party/FatFs/src/ff.c **** 						st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust);
+3769:Middlewares/Third_Party/FatFs/src/ff.c **** 						st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize);
+3770:Middlewares/Third_Party/FatFs/src/ff.c **** 						st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize);
+3771:Middlewares/Third_Party/FatFs/src/ff.c **** 						st_dword(fs->dirbuf + XDIR_ModTime, tm);		/* Update modified time */
+3772:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->dirbuf[XDIR_ModTime10] = 0;
+3773:Middlewares/Third_Party/FatFs/src/ff.c **** 						st_dword(fs->dirbuf + XDIR_AccTime, 0);
+3774:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = store_xdir(&dj);	/* Restore it to the directory */
+3775:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (res == FR_OK) {
+3776:Middlewares/Third_Party/FatFs/src/ff.c **** 							res = sync_fs(fs);
+3777:Middlewares/Third_Party/FatFs/src/ff.c **** 							fp->flag &= (BYTE)~FA_MODIFIED;
+3778:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+3779:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+3780:Middlewares/Third_Party/FatFs/src/ff.c **** 					FREE_NAMBUF();
+3781:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3782:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else
+3783:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3784:Middlewares/Third_Party/FatFs/src/ff.c **** 			{
+3785:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = move_window(fs, fp->dir_sect);
+ARM GAS  /tmp/cc5lWXRL.s 			page 99
+
+
+3786:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {
+3787:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir = fp->dir_ptr;
+3788:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[DIR_Attr] |= AM_ARC;						/* Set archive bit */
+3789:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fp->obj.fs, dir, fp->obj.sclust);		/* Update file allocation info  */
+3790:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize);	/* Update file size */
+3791:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dir + DIR_ModTime, tm);				/* Update modified time */
+3792:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_word(dir + DIR_LstAccDate, 0);
+3793:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+3794:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = sync_fs(fs);					/* Restore it to the directory */
+3795:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_MODIFIED;
+3796:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3797:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3798:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3799:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3800:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3801:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+3802:Middlewares/Third_Party/FatFs/src/ff.c **** }
+3803:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3804:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */
+3805:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3806:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3807:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3808:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3809:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3810:Middlewares/Third_Party/FatFs/src/ff.c **** /* Close File                                                            */
+3811:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3812:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3813:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_close (
+3814:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp		/* Pointer to the file object to be closed */
+3815:Middlewares/Third_Party/FatFs/src/ff.c **** )
+3816:Middlewares/Third_Party/FatFs/src/ff.c **** {
+3817:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+3818:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+3819:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3820:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+3821:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = f_sync(fp);					/* Flush cached data */
+3822:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK)
+3823:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3824:Middlewares/Third_Party/FatFs/src/ff.c **** 	{
+3825:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = validate(&fp->obj, &fs);	/* Lock volume */
+3826:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+3827:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+3828:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dec_lock(fp->obj.lockid);	/* Decrement file open counter */
+3829:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK)
+3830:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3831:Middlewares/Third_Party/FatFs/src/ff.c **** 			{
+3832:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.fs = 0;			/* Invalidate file object */
+3833:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3834:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+3835:Middlewares/Third_Party/FatFs/src/ff.c **** 			unlock_fs(fs, FR_OK);		/* Unlock volume */
+3836:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3837:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3838:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3839:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+3840:Middlewares/Third_Party/FatFs/src/ff.c **** }
+3841:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3842:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 100
+
+
+3843:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3844:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3845:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH >= 1
+3846:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3847:Middlewares/Third_Party/FatFs/src/ff.c **** /* Change Current Directory or Current Drive, Get Current Directory      */
+3848:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3849:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3850:Middlewares/Third_Party/FatFs/src/ff.c **** #if _VOLUMES >= 2
+3851:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_chdrive (
+3852:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path		/* Drive number */
+3853:Middlewares/Third_Party/FatFs/src/ff.c **** )
+3854:Middlewares/Third_Party/FatFs/src/ff.c **** {
+3855:Middlewares/Third_Party/FatFs/src/ff.c **** 	int vol;
+3856:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3857:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3858:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive number */
+3859:Middlewares/Third_Party/FatFs/src/ff.c **** 	vol = get_ldnumber(&path);
+3860:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+3861:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3862:Middlewares/Third_Party/FatFs/src/ff.c **** 	CurrVol = (BYTE)vol;	/* Set it as current volume */
+3863:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3864:Middlewares/Third_Party/FatFs/src/ff.c **** 	return FR_OK;
+3865:Middlewares/Third_Party/FatFs/src/ff.c **** }
+3866:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3867:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3868:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3869:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_chdir (
+3870:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path	/* Pointer to the directory path */
+3871:Middlewares/Third_Party/FatFs/src/ff.c **** )
+3872:Middlewares/Third_Party/FatFs/src/ff.c **** {
+3873:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+3874:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+3875:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+3876:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+3877:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3878:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive */
+3879:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, 0);
+3880:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+3881:Middlewares/Third_Party/FatFs/src/ff.c **** 		dj.obj.fs = fs;
+3882:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+3883:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&dj, path);		/* Follow the path */
+3884:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {					/* Follow completed */
+3885:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dj.fn[NSFLAG] & NS_NONAME) {
+3886:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->cdir = dj.obj.sclust;	/* It is the start directory itself */
+3887:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+3888:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fs->fs_type == FS_EXFAT) {
+3889:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->cdc_scl = dj.obj.c_scl;
+3890:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->cdc_size = dj.obj.c_size;
+3891:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->cdc_ofs = dj.obj.c_ofs;
+3892:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3893:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3894:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+3895:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (dj.obj.attr & AM_DIR) {	/* It is a sub-directory */
+3896:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+3897:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (fs->fs_type == FS_EXFAT) {
+3898:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus);		/* Sub-directory cluster */
+3899:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->cdc_scl = dj.obj.sclust;						/* Save containing directory information */
+ARM GAS  /tmp/cc5lWXRL.s 			page 101
+
+
+3900:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+3901:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->cdc_ofs = dj.blk_ofs;
+3902:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else
+3903:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3904:Middlewares/Third_Party/FatFs/src/ff.c **** 					{
+3905:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->cdir = ld_clust(fs, dj.dir);					/* Sub-directory cluster */
+3906:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+3907:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+3908:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_NO_PATH;		/* Reached but a file */
+3909:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3910:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3911:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3912:Middlewares/Third_Party/FatFs/src/ff.c **** 		FREE_NAMBUF();
+3913:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_NO_FILE) res = FR_NO_PATH;
+3914:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3915:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3916:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+3917:Middlewares/Third_Party/FatFs/src/ff.c **** }
+3918:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3919:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3920:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH >= 2
+3921:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_getcwd (
+3922:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR* buff,	/* Pointer to the directory path */
+3923:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT len		/* Size of path */
+3924:Middlewares/Third_Party/FatFs/src/ff.c **** )
+3925:Middlewares/Third_Party/FatFs/src/ff.c **** {
+3926:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+3927:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+3928:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+3929:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, n;
+3930:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD ccl;
+3931:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR *tp;
+3932:Middlewares/Third_Party/FatFs/src/ff.c **** 	FILINFO fno;
+3933:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+3934:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3935:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3936:Middlewares/Third_Party/FatFs/src/ff.c **** 	*buff = 0;
+3937:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive */
+3938:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume((const TCHAR**)&buff, &fs, 0);	/* Get current volume */
+3939:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+3940:Middlewares/Third_Party/FatFs/src/ff.c **** 		dj.obj.fs = fs;
+3941:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+3942:Middlewares/Third_Party/FatFs/src/ff.c **** 		i = len;			/* Bottom of buffer (directory stack base) */
+3943:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {	/* (Cannot do getcwd on exFAT and returns root path)
+3944:Middlewares/Third_Party/FatFs/src/ff.c **** 			dj.obj.sclust = fs->cdir;				/* Start to follow upper directory from current directory */
+3945:Middlewares/Third_Party/FatFs/src/ff.c **** 			while ((ccl = dj.obj.sclust) != 0) {	/* Repeat while current directory is a sub-directory */
+3946:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_sdi(&dj, 1 * SZDIRE);	/* Get parent directory */
+3947:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res != FR_OK) break;
+3948:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = move_window(fs, dj.sect);
+3949:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res != FR_OK) break;
+3950:Middlewares/Third_Party/FatFs/src/ff.c **** 				dj.obj.sclust = ld_clust(fs, dj.dir);	/* Goto parent directory */
+3951:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_sdi(&dj, 0);
+3952:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res != FR_OK) break;
+3953:Middlewares/Third_Party/FatFs/src/ff.c **** 				do {							/* Find the entry links to the child directory */
+3954:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = dir_read(&dj, 0);
+3955:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res != FR_OK) break;
+3956:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (ccl == ld_clust(fs, dj.dir)) break;	/* Found the entry */
+ARM GAS  /tmp/cc5lWXRL.s 			page 102
+
+
+3957:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = dir_next(&dj, 0);
+3958:Middlewares/Third_Party/FatFs/src/ff.c **** 				} while (res == FR_OK);
+3959:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+3960:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res != FR_OK) break;
+3961:Middlewares/Third_Party/FatFs/src/ff.c **** 				get_fileinfo(&dj, &fno);		/* Get the directory name and push it to the buffer */
+3962:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (n = 0; fno.fname[n]; n++) ;
+3963:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (i < n + 3) {
+3964:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_NOT_ENOUGH_CORE; break;
+3965:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+3966:Middlewares/Third_Party/FatFs/src/ff.c **** 				while (n) buff[--i] = fno.fname[--n];
+3967:Middlewares/Third_Party/FatFs/src/ff.c **** 				buff[--i] = '/';
+3968:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3969:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3970:Middlewares/Third_Party/FatFs/src/ff.c **** 		tp = buff;
+3971:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+3972:Middlewares/Third_Party/FatFs/src/ff.c **** #if _VOLUMES >= 2
+3973:Middlewares/Third_Party/FatFs/src/ff.c **** 			*tp++ = '0' + CurrVol;			/* Put drive number */
+3974:Middlewares/Third_Party/FatFs/src/ff.c **** 			*tp++ = ':';
+3975:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+3976:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (i == len) {					/* Root-directory */
+3977:Middlewares/Third_Party/FatFs/src/ff.c **** 				*tp++ = '/';
+3978:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {						/* Sub-directroy */
+3979:Middlewares/Third_Party/FatFs/src/ff.c **** 				do		/* Add stacked path str */
+3980:Middlewares/Third_Party/FatFs/src/ff.c **** 					*tp++ = buff[i++];
+3981:Middlewares/Third_Party/FatFs/src/ff.c **** 				while (i < len);
+3982:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+3983:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+3984:Middlewares/Third_Party/FatFs/src/ff.c **** 		*tp = 0;
+3985:Middlewares/Third_Party/FatFs/src/ff.c **** 		FREE_NAMBUF();
+3986:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+3987:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3988:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+3989:Middlewares/Third_Party/FatFs/src/ff.c **** }
+3990:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3991:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_RPATH >= 2 */
+3992:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_RPATH >= 1 */
+3993:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3994:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3995:Middlewares/Third_Party/FatFs/src/ff.c **** 
+3996:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2
+3997:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+3998:Middlewares/Third_Party/FatFs/src/ff.c **** /* Seek File R/W Pointer                                                 */
+3999:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4000:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4001:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_lseek (
+4002:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp,		/* Pointer to the file object */
+4003:Middlewares/Third_Party/FatFs/src/ff.c **** 	FSIZE_t ofs		/* File pointer from top of file */
+4004:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4005:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4006:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4007:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4008:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst, bcs, nsect;
+4009:Middlewares/Third_Party/FatFs/src/ff.c **** 	FSIZE_t ifptr;
+4010:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK
+4011:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
+4012:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4013:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 103
+
+
+4014:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+4015:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) res = (FRESULT)fp->err;
+4016:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY
+4017:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK && fs->fs_type == FS_EXFAT) {
+4018:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed
+4019:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4020:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4021:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK) LEAVE_FF(fs, res);
+4022:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4023:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK
+4024:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fp->cltbl) {	/* Fast seek */
+4025:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
+4026:Middlewares/Third_Party/FatFs/src/ff.c **** 			tbl = fp->cltbl;
+4027:Middlewares/Third_Party/FatFs/src/ff.c **** 			tlen = *tbl++; ulen = 2;	/* Given table size and required table size */
+4028:Middlewares/Third_Party/FatFs/src/ff.c **** 			cl = fp->obj.sclust;		/* Origin of the chain */
+4029:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cl) {
+4030:Middlewares/Third_Party/FatFs/src/ff.c **** 				do {
+4031:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Get a fragment */
+4032:Middlewares/Third_Party/FatFs/src/ff.c **** 					tcl = cl; ncl = 0; ulen += 2;	/* Top, length and used items */
+4033:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+4034:Middlewares/Third_Party/FatFs/src/ff.c **** 						pcl = cl; ncl++;
+4035:Middlewares/Third_Party/FatFs/src/ff.c **** 						cl = get_fat(&fp->obj, cl);
+4036:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl <= 1) ABORT(fs, FR_INT_ERR);
+4037:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+4038:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (cl == pcl + 1);
+4039:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (ulen <= tlen) {		/* Store the length and top of the fragment */
+4040:Middlewares/Third_Party/FatFs/src/ff.c **** 						*tbl++ = ncl; *tbl++ = tcl;
+4041:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+4042:Middlewares/Third_Party/FatFs/src/ff.c **** 				} while (cl < fs->n_fatent);	/* Repeat until end of chain */
+4043:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4044:Middlewares/Third_Party/FatFs/src/ff.c **** 			*fp->cltbl = ulen;	/* Number of items used */
+4045:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ulen <= tlen) {
+4046:Middlewares/Third_Party/FatFs/src/ff.c **** 				*tbl = 0;		/* Terminate table */
+4047:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+4048:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_NOT_ENOUGH_CORE;	/* Given table size is smaller than required */
+4049:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4050:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {						/* Fast seek */
+4051:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ofs > fp->obj.objsize) ofs = fp->obj.objsize;	/* Clip offset at the file size */
+4052:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->fptr = ofs;				/* Set file pointer */
+4053:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ofs) {
+4054:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clmt_clust(fp, ofs - 1);
+4055:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc = clust2sect(fs, fp->clust);
+4056:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!dsc) ABORT(fs, FR_INT_ERR);
+4057:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+4058:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+4059:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+4060:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+4061:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+4062:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+4063:Middlewares/Third_Party/FatFs/src/ff.c **** 						fp->flag &= (BYTE)~FA_DIRTY;
+4064:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+4065:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4066:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (disk_read(fs->drv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Load current sec
+4067:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4068:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->sect = dsc;
+4069:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4070:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ARM GAS  /tmp/cc5lWXRL.s 			page 104
+
+
+4071:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4072:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else
+4073:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4074:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4075:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Normal Seek */
+4076:Middlewares/Third_Party/FatFs/src/ff.c **** 	{
+4077:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4078:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF;	/* Clip at 4GiB-1 if at FATx
+4079:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4080:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs > fp->obj.objsize && (_FS_READONLY || !(fp->flag & FA_WRITE))) {	/* In read-only mode, cl
+4081:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs = fp->obj.objsize;
+4082:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4083:Middlewares/Third_Party/FatFs/src/ff.c **** 		ifptr = fp->fptr;
+4084:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->fptr = nsect = 0;
+4085:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs) {
+4086:Middlewares/Third_Party/FatFs/src/ff.c **** 			bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size (byte) */
+4087:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ifptr > 0 &&
+4088:Middlewares/Third_Party/FatFs/src/ff.c **** 				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+4089:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1);	/* start from the current cluster */
+4090:Middlewares/Third_Party/FatFs/src/ff.c **** 				ofs -= fp->fptr;
+4091:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = fp->clust;
+4092:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {									/* When seek to back cluster, */
+4093:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = fp->obj.sclust;					/* start from the first cluster */
+4094:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+4095:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0) {						/* If no cluster chain, create a new chain */
+4096:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = create_chain(&fp->obj, 0);
+4097:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 1) ABORT(fs, FR_INT_ERR);
+4098:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+4099:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.sclust = clst;
+4100:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4101:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4102:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;
+4103:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4104:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (clst != 0) {
+4105:Middlewares/Third_Party/FatFs/src/ff.c **** 				while (ofs > bcs) {						/* Cluster following loop */
+4106:Middlewares/Third_Party/FatFs/src/ff.c **** 					ofs -= bcs; fp->fptr += bcs;
+4107:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+4108:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (fp->flag & FA_WRITE) {			/* Check if in write mode or not */
+4109:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (_FS_EXFAT && fp->fptr > fp->obj.objsize) {	/* No FAT chain object needs correct objsize t
+4110:Middlewares/Third_Party/FatFs/src/ff.c **** 							fp->obj.objsize = fp->fptr;
+4111:Middlewares/Third_Party/FatFs/src/ff.c **** 							fp->flag |= FA_MODIFIED;
+4112:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+4113:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = create_chain(&fp->obj, clst);	/* Follow chain with forceed stretch */
+4114:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (clst == 0) {				/* Clip file size in case of disk full */
+4115:Middlewares/Third_Party/FatFs/src/ff.c **** 							ofs = 0; break;
+4116:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+4117:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else
+4118:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4119:Middlewares/Third_Party/FatFs/src/ff.c **** 					{
+4120:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = get_fat(&fp->obj, clst);	/* Follow cluster chain if not in write mode */
+4121:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+4122:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+4123:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+4124:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->clust = clst;
+4125:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4126:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr += ofs;
+4127:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (ofs % SS(fs)) {
+ARM GAS  /tmp/cc5lWXRL.s 			page 105
+
+
+4128:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect = clust2sect(fs, clst);	/* Current sector */
+4129:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!nsect) ABORT(fs, FR_INT_ERR);
+4130:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect += (DWORD)(ofs / SS(fs));
+4131:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4132:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4133:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4134:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!_FS_READONLY && fp->fptr > fp->obj.objsize) {		/* Set file change flag if the file size is e
+4135:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.objsize = fp->fptr;
+4136:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->flag |= FA_MODIFIED;
+4137:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4138:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) && nsect != fp->sect) {	/* Fill sector cache if needed */
+4139:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+4140:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+4141:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fp->flag & FA_DIRTY) {			/* Write-back dirty sector cache */
+4142:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+4143:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+4144:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4145:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4146:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_read(fs->drv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Fill sector cach
+4147:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4148:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->sect = nsect;
+4149:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4150:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4151:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4152:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+4153:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4154:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4155:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4156:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4157:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 1
+4158:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4159:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create a Directory Object                                             */
+4160:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4161:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4162:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_opendir (
+4163:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,			/* Pointer to directory object to create */
+4164:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path	/* Pointer to the directory path */
+4165:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4166:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4167:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4168:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4169:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID *obj;
+4170:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+4171:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4172:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4173:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!dp) return FR_INVALID_OBJECT;
+4174:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4175:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive */
+4176:Middlewares/Third_Party/FatFs/src/ff.c **** 	obj = &dp->obj;
+4177:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, 0);
+4178:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+4179:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->fs = fs;
+4180:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+4181:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(dp, path);			/* Follow the path to the directory */
+4182:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {						/* Follow completed */
+4183:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!(dp->fn[NSFLAG] & NS_NONAME)) {	/* It is not the origin directory itself */
+4184:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (obj->attr & AM_DIR) {		/* This object is a sub-directory */
+ARM GAS  /tmp/cc5lWXRL.s 			page 106
+
+
+4185:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4186:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (fs->fs_type == FS_EXFAT) {
+4187:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->c_scl = obj->sclust;							/* Get containing directory inforamation */
+4188:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat;
+4189:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->c_ofs = dp->blk_ofs;
+4190:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Get object allocation info */
+4191:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+4192:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+4193:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else
+4194:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4195:Middlewares/Third_Party/FatFs/src/ff.c **** 					{
+4196:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->sclust = ld_clust(fs, dp->dir);	/* Get object allocation info */
+4197:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+4198:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {						/* This object is a file */
+4199:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_NO_PATH;
+4200:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4201:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4202:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {
+4203:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->id = fs->id;
+4204:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_sdi(dp, 0);			/* Rewind directory */
+4205:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+4206:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {
+4207:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (obj->sclust) {
+4208:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->lockid = inc_lock(dp, 0);	/* Lock the sub directory */
+4209:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES;
+4210:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else {
+4211:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->lockid = 0;	/* Root directory need not to be locked */
+4212:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+4213:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4214:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4215:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4216:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4217:Middlewares/Third_Party/FatFs/src/ff.c **** 		FREE_NAMBUF();
+4218:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_NO_FILE) res = FR_NO_PATH;
+4219:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4220:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK) obj->fs = 0;		/* Invalidate the directory object if function faild */
+4221:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4222:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+4223:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4224:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4225:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4226:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4227:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4228:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4229:Middlewares/Third_Party/FatFs/src/ff.c **** /* Close Directory                                                       */
+4230:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4231:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4232:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_closedir (
+4233:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR *dp		/* Pointer to the directory object to be closed */
+4234:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4235:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4236:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4237:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4238:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4239:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4240:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&dp->obj, &fs);			/* Check validity of the file object */
+4241:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ARM GAS  /tmp/cc5lWXRL.s 			page 107
+
+
+4242:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+4243:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (dp->obj.lockid) {				/* Decrement sub-directory open counter */
+4244:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dec_lock(dp->obj.lockid);
+4245:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4246:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK)
+4247:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4248:Middlewares/Third_Party/FatFs/src/ff.c **** 		{
+4249:Middlewares/Third_Party/FatFs/src/ff.c **** 			dp->obj.fs = 0;			/* Invalidate directory object */
+4250:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4251:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+4252:Middlewares/Third_Party/FatFs/src/ff.c **** 		unlock_fs(fs, FR_OK);		/* Unlock volume */
+4253:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4254:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4255:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+4256:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4257:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4258:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4259:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4260:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4261:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4262:Middlewares/Third_Party/FatFs/src/ff.c **** /* Read Directory Entries in Sequence                                    */
+4263:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4264:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4265:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_readdir (
+4266:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,			/* Pointer to the open directory object */
+4267:Middlewares/Third_Party/FatFs/src/ff.c **** 	FILINFO* fno		/* Pointer to file information to return */
+4268:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4269:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4270:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4271:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4272:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+4273:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4274:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4275:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&dp->obj, &fs);	/* Check validity of the directory object */
+4276:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+4277:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!fno) {
+4278:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dir_sdi(dp, 0);			/* Rewind the directory object */
+4279:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+4280:Middlewares/Third_Party/FatFs/src/ff.c **** 			INIT_NAMBUF(fs);
+4281:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dir_read(dp, 0);			/* Read an item */
+4282:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory */
+4283:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {				/* A valid entry is found */
+4284:Middlewares/Third_Party/FatFs/src/ff.c **** 				get_fileinfo(dp, fno);		/* Get the object information */
+4285:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_next(dp, 0);		/* Increment index for next */
+4286:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory now */
+4287:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4288:Middlewares/Third_Party/FatFs/src/ff.c **** 			FREE_NAMBUF();
+4289:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4290:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4291:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+4292:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4293:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4294:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4295:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4296:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FIND
+4297:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4298:Middlewares/Third_Party/FatFs/src/ff.c **** /* Find Next File                                                        */
+ARM GAS  /tmp/cc5lWXRL.s 			page 108
+
+
+4299:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4300:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4301:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_findnext (
+4302:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,		/* Pointer to the open directory object */
+4303:Middlewares/Third_Party/FatFs/src/ff.c **** 	FILINFO* fno	/* Pointer to the file information structure */
+4304:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4305:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4306:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4307:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4308:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4309:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (;;) {
+4310:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = f_readdir(dp, fno);		/* Get a directory item */
+4311:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK || !fno || !fno->fname[0]) break;	/* Terminate if any error or end of directory 
+4312:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (pattern_matching(dp->pat, fno->fname, 0, 0)) break;		/* Test for the file name */
+4313:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 && _USE_FIND == 2
+4314:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (pattern_matching(dp->pat, fno->altname, 0, 0)) break;	/* Test for alternative name if exist *
+4315:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4316:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4317:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+4318:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4319:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4320:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4321:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4322:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4323:Middlewares/Third_Party/FatFs/src/ff.c **** /* Find First File                                                       */
+4324:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4325:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4326:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_findfirst (
+4327:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR* dp,				/* Pointer to the blank directory object */
+4328:Middlewares/Third_Party/FatFs/src/ff.c **** 	FILINFO* fno,			/* Pointer to the file information structure */
+4329:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path,		/* Pointer to the directory to open */
+4330:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* pattern	/* Pointer to the matching pattern */
+4331:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4332:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4333:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4334:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4335:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4336:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->pat = pattern;		/* Save pointer to pattern string */
+4337:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = f_opendir(dp, path);		/* Open the target directory */
+4338:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+4339:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = f_findnext(dp, fno);	/* Find the first item */
+4340:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4341:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+4342:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4343:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4344:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _USE_FIND */
+4345:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4346:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4347:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4348:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE == 0
+4349:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4350:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get File Status                                                       */
+4351:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4352:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4353:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_stat (
+4354:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path,	/* Pointer to the file path */
+4355:Middlewares/Third_Party/FatFs/src/ff.c **** 	FILINFO* fno		/* Pointer to file information to return */
+ARM GAS  /tmp/cc5lWXRL.s 			page 109
+
+
+4356:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4357:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4358:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4359:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+4360:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+4361:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4362:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4363:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive */
+4364:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &dj.obj.fs, 0);
+4365:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+4366:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(dj.obj.fs);
+4367:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&dj, path);	/* Follow the file path */
+4368:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {				/* Follow completed */
+4369:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dj.fn[NSFLAG] & NS_NONAME) {	/* It is origin directory */
+4370:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;
+4371:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {							/* Found an object */
+4372:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fno) get_fileinfo(&dj, fno);
+4373:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4374:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4375:Middlewares/Third_Party/FatFs/src/ff.c **** 		FREE_NAMBUF();
+4376:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4377:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4378:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(dj.obj.fs, res);
+4379:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4380:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4381:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4382:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4383:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+4384:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4385:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get Number of Free Clusters                                           */
+4386:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4387:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4388:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_getfree (
+4389:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path,	/* Path name of the logical drive number */
+4390:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD* nclst,		/* Pointer to a variable to return number of free clusters */
+4391:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS** fatfs		/* Pointer to return pointer to corresponding file system object */
+4392:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4393:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4394:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4395:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4396:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD nfree, clst, sect, stat;
+4397:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+4398:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *p;
+4399:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID obj;
+4400:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4401:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4402:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive */
+4403:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, 0);
+4404:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+4405:Middlewares/Third_Party/FatFs/src/ff.c **** 		*fatfs = fs;				/* Return ptr to the fs object */
+4406:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* If free_clst is valid, return it without full cluster scan */
+4407:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->free_clst <= fs->n_fatent - 2) {
+4408:Middlewares/Third_Party/FatFs/src/ff.c **** 			*nclst = fs->free_clst;
+4409:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+4410:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Get number of free clusters */
+4411:Middlewares/Third_Party/FatFs/src/ff.c **** 			nfree = 0;
+4412:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->fs_type == FS_FAT12) {	/* FAT12: Sector unalighed FAT entries */
+ARM GAS  /tmp/cc5lWXRL.s 			page 110
+
+
+4413:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = 2; obj.fs = fs;
+4414:Middlewares/Third_Party/FatFs/src/ff.c **** 				do {
+4415:Middlewares/Third_Party/FatFs/src/ff.c **** 					stat = get_fat(&obj, clst);
+4416:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+4417:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (stat == 1) { res = FR_INT_ERR; break; }
+4418:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (stat == 0) nfree++;
+4419:Middlewares/Third_Party/FatFs/src/ff.c **** 				} while (++clst < fs->n_fatent);
+4420:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+4421:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4422:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fs->fs_type == FS_EXFAT) {	/* exFAT: Scan bitmap table */
+4423:Middlewares/Third_Party/FatFs/src/ff.c **** 					BYTE bm;
+4424:Middlewares/Third_Party/FatFs/src/ff.c **** 					UINT b;
+4425:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4426:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = fs->n_fatent - 2;
+4427:Middlewares/Third_Party/FatFs/src/ff.c **** 					sect = fs->database;
+4428:Middlewares/Third_Party/FatFs/src/ff.c **** 					i = 0;
+4429:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+4430:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (i == 0 && (res = move_window(fs, sect++)) != FR_OK) break;
+4431:Middlewares/Third_Party/FatFs/src/ff.c **** 						for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) {
+4432:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (!(bm & 1)) nfree++;
+4433:Middlewares/Third_Party/FatFs/src/ff.c **** 							bm >>= 1;
+4434:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+4435:Middlewares/Third_Party/FatFs/src/ff.c **** 						i = (i + 1) % SS(fs);
+4436:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (clst);
+4437:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else
+4438:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4439:Middlewares/Third_Party/FatFs/src/ff.c **** 				{	/* FAT16/32: Sector alighed FAT entries */
+4440:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = fs->n_fatent; sect = fs->fatbase;
+4441:Middlewares/Third_Party/FatFs/src/ff.c **** 					i = 0; p = 0;
+4442:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+4443:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (i == 0) {
+4444:Middlewares/Third_Party/FatFs/src/ff.c **** 							res = move_window(fs, sect++);
+4445:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res != FR_OK) break;
+4446:Middlewares/Third_Party/FatFs/src/ff.c **** 							p = fs->win;
+4447:Middlewares/Third_Party/FatFs/src/ff.c **** 							i = SS(fs);
+4448:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+4449:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (fs->fs_type == FS_FAT16) {
+4450:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (ld_word(p) == 0) nfree++;
+4451:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 2; i -= 2;
+4452:Middlewares/Third_Party/FatFs/src/ff.c **** 						} else {
+4453:Middlewares/Third_Party/FatFs/src/ff.c **** 							if ((ld_dword(p) & 0x0FFFFFFF) == 0) nfree++;
+4454:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 4; i -= 4;
+4455:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+4456:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (--clst);
+4457:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4458:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4459:Middlewares/Third_Party/FatFs/src/ff.c **** 			*nclst = nfree;			/* Return the free clusters */
+4460:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->free_clst = nfree;	/* Now free_clst is valid */
+4461:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->fsi_flag |= 1;		/* FSInfo is to be updated */
+4462:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4463:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4464:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4465:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+4466:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4467:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4468:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4469:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 111
+
+
+4470:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4471:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4472:Middlewares/Third_Party/FatFs/src/ff.c **** /* Truncate File                                                         */
+4473:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4474:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4475:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_truncate (
+4476:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp		/* Pointer to the file object */
+4477:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4478:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4479:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4480:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4481:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD ncl;
+4482:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4483:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4484:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+4485:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+4486:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+4487:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4488:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fp->fptr < fp->obj.objsize) {	/* Process when fptr is not on the eof */
+4489:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+4490:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+4491:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.sclust = 0;
+4492:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {				/* When truncate a part of the file, remove remaining clusters */
+4493:Middlewares/Third_Party/FatFs/src/ff.c **** 			ncl = get_fat(&fp->obj, fp->clust);
+4494:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+4495:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+4496:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl == 1) res = FR_INT_ERR;
+4497:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK && ncl < fs->n_fatent) {
+4498:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = remove_chain(&fp->obj, ncl, fp->clust);
+4499:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4500:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4501:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->obj.objsize = fp->fptr;	/* Set file size to current R/W point */
+4502:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->flag |= FA_MODIFIED;
+4503:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+4504:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK && (fp->flag & FA_DIRTY)) {
+4505:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) {
+4506:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_DISK_ERR;
+4507:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+4508:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+4509:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4510:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4511:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4512:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) ABORT(fs, res);
+4513:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4514:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4515:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+4516:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4517:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4518:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4519:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4520:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4521:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4522:Middlewares/Third_Party/FatFs/src/ff.c **** /* Delete a File/Directory                                               */
+4523:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4524:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4525:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_unlink (
+4526:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path		/* Pointer to the file or directory path */
+ARM GAS  /tmp/cc5lWXRL.s 			page 112
+
+
+4527:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4528:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4529:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4530:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj, sdj;
+4531:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD dclst = 0;
+4532:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4533:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4534:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID obj;
+4535:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4536:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+4537:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4538:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4539:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive */
+4540:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, FA_WRITE);
+4541:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.fs = fs;
+4542:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+4543:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+4544:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&dj, path);		/* Follow the file path */
+4545:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) {
+4546:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_INVALID_NAME;			/* Cannot remove dot entry */
+4547:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4548:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+4549:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) res = chk_lock(&dj, 2);	/* Check if it is an open object */
+4550:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4551:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {					/* The object is accessible */
+4552:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dj.fn[NSFLAG] & NS_NONAME) {
+4553:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;		/* Cannot remove the origin directory */
+4554:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+4555:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (dj.obj.attr & AM_RDO) {
+4556:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_DENIED;		/* Cannot remove R/O object */
+4557:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4558:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4559:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {
+4560:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4561:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj.fs = fs;
+4562:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fs->fs_type == FS_EXFAT) {
+4563:Middlewares/Third_Party/FatFs/src/ff.c **** 					obj.sclust = dclst = ld_dword(fs->dirbuf + XDIR_FstClus);
+4564:Middlewares/Third_Party/FatFs/src/ff.c **** 					obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+4565:Middlewares/Third_Party/FatFs/src/ff.c **** 					obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+4566:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else
+4567:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4568:Middlewares/Third_Party/FatFs/src/ff.c **** 				{
+4569:Middlewares/Third_Party/FatFs/src/ff.c **** 					dclst = ld_clust(fs, dj.dir);
+4570:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4571:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (dj.obj.attr & AM_DIR) {			/* Is it a sub-directory? */
+4572:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0
+4573:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (dclst == fs->cdir) {		 		/* Is it the current directory? */
+4574:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = FR_DENIED;
+4575:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else
+4576:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4577:Middlewares/Third_Party/FatFs/src/ff.c **** 					{
+4578:Middlewares/Third_Party/FatFs/src/ff.c **** 						sdj.obj.fs = fs;						/* Open the sub-directory */
+4579:Middlewares/Third_Party/FatFs/src/ff.c **** 						sdj.obj.sclust = dclst;
+4580:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4581:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (fs->fs_type == FS_EXFAT) {
+4582:Middlewares/Third_Party/FatFs/src/ff.c **** 							sdj.obj.objsize = obj.objsize;
+4583:Middlewares/Third_Party/FatFs/src/ff.c **** 							sdj.obj.stat = obj.stat;
+ARM GAS  /tmp/cc5lWXRL.s 			page 113
+
+
+4584:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+4585:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4586:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = dir_sdi(&sdj, 0);
+4587:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (res == FR_OK) {
+4588:Middlewares/Third_Party/FatFs/src/ff.c **** 							res = dir_read(&sdj, 0);			/* Read an item */
+4589:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res == FR_OK) res = FR_DENIED;	/* Not empty? */
+4590:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res == FR_NO_FILE) res = FR_OK;	/* Empty? */
+4591:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+4592:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+4593:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4594:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4595:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {
+4596:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_remove(&dj);			/* Remove the directory entry */
+4597:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK && dclst) {	/* Remove the cluster chain if exist */
+4598:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4599:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = remove_chain(&obj, dclst, 0);
+4600:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+4601:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = remove_chain(&dj.obj, dclst, 0);
+4602:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4603:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4604:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) res = sync_fs(fs);
+4605:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4606:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4607:Middlewares/Third_Party/FatFs/src/ff.c **** 		FREE_NAMBUF();
+4608:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4609:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4610:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+4611:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4612:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4613:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4614:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4615:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4616:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4617:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create a Directory                                                    */
+4618:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4619:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4620:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_mkdir (
+4621:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path		/* Pointer to the directory path */
+4622:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4623:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4624:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4625:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+4626:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4627:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *dir;
+4628:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT n;
+4629:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD dsc, dcl, pcl, tm;
+4630:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+4631:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4632:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4633:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive */
+4634:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, FA_WRITE);
+4635:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.fs = fs;
+4636:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+4637:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+4638:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&dj, path);			/* Follow the file path */
+4639:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
+4640:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) {
+ARM GAS  /tmp/cc5lWXRL.s 			page 114
+
+
+4641:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_INVALID_NAME;
+4642:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4643:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_NO_FILE) {				/* Can create a new directory */
+4644:Middlewares/Third_Party/FatFs/src/ff.c **** 			dcl = create_chain(&dj.obj, 0);		/* Allocate a cluster for the new directory table */
+4645:Middlewares/Third_Party/FatFs/src/ff.c **** 			dj.obj.objsize = (DWORD)fs->csize * SS(fs);
+4646:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+4647:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dcl == 0) res = FR_DENIED;		/* No space to allocate a new cluster */
+4648:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dcl == 1) res = FR_INT_ERR;
+4649:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+4650:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) res = sync_window(fs);	/* Flush FAT */
+4651:Middlewares/Third_Party/FatFs/src/ff.c **** 			tm = GET_FATTIME();
+4652:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {					/* Initialize the new directory table */
+4653:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc = clust2sect(fs, dcl);
+4654:Middlewares/Third_Party/FatFs/src/ff.c **** 				dir = fs->win;
+4655:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_set(dir, 0, SS(fs));
+4656:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+4657:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_set(dir + DIR_Name, ' ', 11);	/* Create "." entry */
+4658:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[DIR_Name] = '.';
+4659:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[DIR_Attr] = AM_DIR;
+4660:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dir + DIR_ModTime, tm);
+4661:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir, dcl);
+4662:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(dir + SZDIRE, dir, SZDIRE); 	/* Create ".." entry */
+4663:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust;
+4664:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0;
+4665:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir + SZDIRE, pcl);
+4666:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4667:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (n = fs->csize; n; n--) {	/* Write dot entries and clear following sectors */
+4668:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->winsect = dsc++;
+4669:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+4670:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = sync_window(fs);
+4671:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res != FR_OK) break;
+4672:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_set(dir, 0, SS(fs));
+4673:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4674:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4675:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {
+4676:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_register(&dj);	/* Register the object to the directoy */
+4677:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4678:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {
+4679:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4680:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fs->fs_type == FS_EXFAT) {	/* Initialize directory entry block */
+4681:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(fs->dirbuf + XDIR_ModTime, tm);	/* Created time */
+4682:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(fs->dirbuf + XDIR_FstClus, dcl);	/* Table start cluster */
+4683:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)dj.obj.objsize);	/* File size needs to be valid */
+4684:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)dj.obj.objsize);
+4685:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->dirbuf[XDIR_GenFlags] = 3;				/* Initialize the object flag (contiguous) */
+4686:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->dirbuf[XDIR_Attr] = AM_DIR;				/* Attribute */
+4687:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = store_xdir(&dj);
+4688:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else
+4689:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4690:Middlewares/Third_Party/FatFs/src/ff.c **** 				{
+4691:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir = dj.dir;
+4692:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dir + DIR_ModTime, tm);	/* Created time */
+4693:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir, dcl);				/* Table start cluster */
+4694:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[DIR_Attr] = AM_DIR;				/* Attribute */
+4695:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+4696:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4697:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {
+ARM GAS  /tmp/cc5lWXRL.s 			page 115
+
+
+4698:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = sync_fs(fs);
+4699:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4700:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+4701:Middlewares/Third_Party/FatFs/src/ff.c **** 				remove_chain(&dj.obj, dcl, 0);		/* Could not register, remove cluster chain */
+4702:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4703:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4704:Middlewares/Third_Party/FatFs/src/ff.c **** 		FREE_NAMBUF();
+4705:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4706:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4707:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+4708:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4709:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4710:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4711:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4712:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4713:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4714:Middlewares/Third_Party/FatFs/src/ff.c **** /* Rename a File/Directory                                               */
+4715:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4716:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4717:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_rename (
+4718:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path_old,	/* Pointer to the object name to be renamed */
+4719:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path_new	/* Pointer to the new name */
+4720:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4721:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4722:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4723:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR djo, djn;
+4724:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4725:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE buf[_FS_EXFAT ? SZDIRE * 2 : 24], *dir;
+4726:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD dw;
+4727:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+4728:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4729:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4730:Middlewares/Third_Party/FatFs/src/ff.c **** 	get_ldnumber(&path_new);						/* Snip drive number of new name off */
+4731:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path_old, &fs, FA_WRITE);	/* Get logical drive of the old object */
+4732:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+4733:Middlewares/Third_Party/FatFs/src/ff.c **** 		djo.obj.fs = fs;
+4734:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+4735:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&djo, path_old);		/* Check old object */
+4736:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check vali
+4737:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+4738:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+4739:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = chk_lock(&djo, 2);
+4740:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4741:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4742:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {						/* Object to be renamed is found */
+4743:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4744:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->fs_type == FS_EXFAT) {	/* At exFAT */
+4745:Middlewares/Third_Party/FatFs/src/ff.c **** 				BYTE nf, nn;
+4746:Middlewares/Third_Party/FatFs/src/ff.c **** 				WORD nh;
+4747:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4748:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_cpy(buf, fs->dirbuf, SZDIRE * 2);	/* Save 85+C0 entry of old object */
+4749:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_cpy(&djn, &djo, sizeof djo);
+4750:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+4751:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+4752:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+4753:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4754:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+ARM GAS  /tmp/cc5lWXRL.s 			page 116
+
+
+4755:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = dir_register(&djn);			/* Register the new entry */
+4756:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res == FR_OK) {
+4757:Middlewares/Third_Party/FatFs/src/ff.c **** 						nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName];
+4758:Middlewares/Third_Party/FatFs/src/ff.c **** 						nh = ld_word(fs->dirbuf + XDIR_NameHash);
+4759:Middlewares/Third_Party/FatFs/src/ff.c **** 						mem_cpy(fs->dirbuf, buf, SZDIRE * 2);
+4760:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn;
+4761:Middlewares/Third_Party/FatFs/src/ff.c **** 						st_word(fs->dirbuf + XDIR_NameHash, nh);
+4762:Middlewares/Third_Party/FatFs/src/ff.c **** /* Start of critical section where an interruption can cause a cross-link */
+4763:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = store_xdir(&djn);
+4764:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+4765:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4766:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else
+4767:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4768:Middlewares/Third_Party/FatFs/src/ff.c **** 			{	/* At FAT12/FAT16/FAT32 */
+4769:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_cpy(buf, djo.dir + DIR_Attr, 21);	/* Save information about the object except name */
+4770:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_cpy(&djn, &djo, sizeof (DIR));		/* Duplicate the directory object */
+4771:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+4772:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+4773:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+4774:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4775:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+4776:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = dir_register(&djn);			/* Register the new entry */
+4777:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res == FR_OK) {
+4778:Middlewares/Third_Party/FatFs/src/ff.c **** 						dir = djn.dir;					/* Copy information about object except name */
+4779:Middlewares/Third_Party/FatFs/src/ff.c **** 						mem_cpy(dir + 13, buf + 2, 19);
+4780:Middlewares/Third_Party/FatFs/src/ff.c **** 						dir[DIR_Attr] = buf[0] | AM_ARC;
+4781:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+4782:Middlewares/Third_Party/FatFs/src/ff.c **** 						if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) {	/* Update .. entry in the
+4783:Middlewares/Third_Party/FatFs/src/ff.c **** 							dw = clust2sect(fs, ld_clust(fs, dir));
+4784:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (!dw) {
+4785:Middlewares/Third_Party/FatFs/src/ff.c **** 								res = FR_INT_ERR;
+4786:Middlewares/Third_Party/FatFs/src/ff.c **** 							} else {
+4787:Middlewares/Third_Party/FatFs/src/ff.c **** /* Start of critical section where an interruption can cause a cross-link */
+4788:Middlewares/Third_Party/FatFs/src/ff.c **** 								res = move_window(fs, dw);
+4789:Middlewares/Third_Party/FatFs/src/ff.c **** 								dir = fs->win + SZDIRE * 1;	/* Ptr to .. entry */
+4790:Middlewares/Third_Party/FatFs/src/ff.c **** 								if (res == FR_OK && dir[1] == '.') {
+4791:Middlewares/Third_Party/FatFs/src/ff.c **** 									st_clust(fs, dir, djn.obj.sclust);
+4792:Middlewares/Third_Party/FatFs/src/ff.c **** 									fs->wflag = 1;
+4793:Middlewares/Third_Party/FatFs/src/ff.c **** 								}
+4794:Middlewares/Third_Party/FatFs/src/ff.c **** 							}
+4795:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+4796:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+4797:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4798:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4799:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {
+4800:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_remove(&djo);		/* Remove old entry */
+4801:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {
+4802:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = sync_fs(fs);
+4803:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4804:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4805:Middlewares/Third_Party/FatFs/src/ff.c **** /* End of the critical section */
+4806:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4807:Middlewares/Third_Party/FatFs/src/ff.c **** 		FREE_NAMBUF();
+4808:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4809:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4810:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+4811:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ARM GAS  /tmp/cc5lWXRL.s 			page 117
+
+
+4812:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4813:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */
+4814:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_MINIMIZE == 0 */
+4815:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_MINIMIZE <= 1 */
+4816:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_MINIMIZE <= 2 */
+4817:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4818:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4819:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4820:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_CHMOD && !_FS_READONLY
+4821:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4822:Middlewares/Third_Party/FatFs/src/ff.c **** /* Change Attribute                                                      */
+4823:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4824:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4825:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_chmod (
+4826:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path,	/* Pointer to the file path */
+4827:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE attr,			/* Attribute bits */
+4828:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE mask			/* Attribute mask to change */
+4829:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4830:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4831:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4832:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+4833:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4834:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+4835:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4836:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4837:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+4838:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.fs = fs;
+4839:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+4840:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+4841:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&dj, path);	/* Follow the file path */
+4842:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check objec
+4843:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+4844:Middlewares/Third_Party/FatFs/src/ff.c **** 			mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC;	/* Valid attribute mask */
+4845:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4846:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->fs_type == FS_EXFAT) {
+4847:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask);	/* Apply attribu
+4848:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = store_xdir(&dj);
+4849:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else
+4850:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4851:Middlewares/Third_Party/FatFs/src/ff.c **** 			{
+4852:Middlewares/Third_Party/FatFs/src/ff.c **** 				dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask);	/* Apply attribute change 
+4853:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->wflag = 1;
+4854:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4855:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {
+4856:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = sync_fs(fs);
+4857:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4858:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4859:Middlewares/Third_Party/FatFs/src/ff.c **** 		FREE_NAMBUF();
+4860:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4861:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4862:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+4863:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4864:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4865:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4866:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4867:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4868:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+ARM GAS  /tmp/cc5lWXRL.s 			page 118
+
+
+4869:Middlewares/Third_Party/FatFs/src/ff.c **** /* Change Timestamp                                                      */
+4870:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4871:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4872:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_utime (
+4873:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path,	/* Pointer to the file/directory name */
+4874:Middlewares/Third_Party/FatFs/src/ff.c **** 	const FILINFO* fno	/* Pointer to the time stamp to be set */
+4875:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4876:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4877:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+4878:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+4879:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4880:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+4881:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4882:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4883:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+4884:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.fs = fs;
+4885:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+4886:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+4887:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&dj, path);	/* Follow the file path */
+4888:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check objec
+4889:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+4890:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4891:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->fs_type == FS_EXFAT) {
+4892:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+4893:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = store_xdir(&dj);
+4894:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else
+4895:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4896:Middlewares/Third_Party/FatFs/src/ff.c **** 			{
+4897:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+4898:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->wflag = 1;
+4899:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4900:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {
+4901:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = sync_fs(fs);
+4902:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4903:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4904:Middlewares/Third_Party/FatFs/src/ff.c **** 		FREE_NAMBUF();
+4905:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4906:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4907:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+4908:Middlewares/Third_Party/FatFs/src/ff.c **** }
+4909:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4910:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _USE_CHMOD && !_FS_READONLY */
+4911:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4912:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4913:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4914:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LABEL
+4915:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4916:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get Volume Label                                                      */
+4917:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+4918:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4919:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_getlabel (
+4920:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path,	/* Path name of the logical drive number */
+4921:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR* label,		/* Pointer to a buffer to return the volume label */
+4922:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD* vsn			/* Pointer to a variable to return the volume serial number */
+4923:Middlewares/Third_Party/FatFs/src/ff.c **** )
+4924:Middlewares/Third_Party/FatFs/src/ff.c **** {
+4925:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ARM GAS  /tmp/cc5lWXRL.s 			page 119
+
+
+4926:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+4927:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+4928:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT si, di;
+4929:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE || _FS_EXFAT
+4930:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR w;
+4931:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4932:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4933:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive */
+4934:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, 0);
+4935:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4936:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get volume label */
+4937:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK && label) {
+4938:Middlewares/Third_Party/FatFs/src/ff.c **** 		dj.obj.fs = fs; dj.obj.sclust = 0;	/* Open root directory */
+4939:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = dir_sdi(&dj, 0);
+4940:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+4941:Middlewares/Third_Party/FatFs/src/ff.c **** 		 	res = dir_read(&dj, 1);			/* Find a volume label entry */
+4942:Middlewares/Third_Party/FatFs/src/ff.c **** 		 	if (res == FR_OK) {
+4943:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+4944:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fs->fs_type == FS_EXFAT) {
+4945:Middlewares/Third_Party/FatFs/src/ff.c **** 					for (si = di = 0; si < dj.dir[XDIR_NumLabel]; si++) {	/* Extract volume label from 83 entry */
+4946:Middlewares/Third_Party/FatFs/src/ff.c **** 						w = ld_word(dj.dir + XDIR_Label + si * 2);
+4947:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+4948:Middlewares/Third_Party/FatFs/src/ff.c **** 						label[di++] = w;
+4949:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+4950:Middlewares/Third_Party/FatFs/src/ff.c **** 						w = ff_convert(w, 0);	/* Unicode -> OEM */
+4951:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (w == 0) w = '?';	/* Replace wrong character */
+4952:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (_DF1S && w >= 0x100) label[di++] = (char)(w >> 8);
+4953:Middlewares/Third_Party/FatFs/src/ff.c **** 						label[di++] = (char)w;
+4954:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4955:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+4956:Middlewares/Third_Party/FatFs/src/ff.c **** 					label[di] = 0;
+4957:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else
+4958:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4959:Middlewares/Third_Party/FatFs/src/ff.c **** 				{
+4960:Middlewares/Third_Party/FatFs/src/ff.c **** 					si = di = 0;		/* Extract volume label from AM_VOL entry with code comversion */
+4961:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+4962:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+4963:Middlewares/Third_Party/FatFs/src/ff.c **** 						w = (si < 11) ? dj.dir[si++] : ' ';
+4964:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (IsDBCS1(w) && si < 11 && IsDBCS2(dj.dir[si])) {
+4965:Middlewares/Third_Party/FatFs/src/ff.c **** 							w = w << 8 | dj.dir[si++];
+4966:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+4967:Middlewares/Third_Party/FatFs/src/ff.c **** 						label[di++] = ff_convert(w, 1);	/* OEM -> Unicode */
+4968:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+4969:Middlewares/Third_Party/FatFs/src/ff.c **** 						label[di++] = dj.dir[si++];
+4970:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+4971:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (di < 11);
+4972:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {				/* Truncate trailing spaces */
+4973:Middlewares/Third_Party/FatFs/src/ff.c **** 						label[di] = 0;
+4974:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (di == 0) break;
+4975:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (label[--di] == ' ');
+4976:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+4977:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4978:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+4979:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_NO_FILE) {	/* No label entry and return nul string */
+4980:Middlewares/Third_Party/FatFs/src/ff.c **** 			label[0] = 0;
+4981:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+4982:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ARM GAS  /tmp/cc5lWXRL.s 			page 120
+
+
+4983:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+4984:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4985:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get volume serial number */
+4986:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK && vsn) {
+4987:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, fs->volbase);
+4988:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+4989:Middlewares/Third_Party/FatFs/src/ff.c **** 			switch (fs->fs_type) {
+4990:Middlewares/Third_Party/FatFs/src/ff.c **** 			case FS_EXFAT:
+4991:Middlewares/Third_Party/FatFs/src/ff.c **** 				di = BPB_VolIDEx; break;
+4992:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4993:Middlewares/Third_Party/FatFs/src/ff.c **** 			case FS_FAT32:
+4994:Middlewares/Third_Party/FatFs/src/ff.c **** 				di = BS_VolID32; break;
+4995:Middlewares/Third_Party/FatFs/src/ff.c **** 
+4996:Middlewares/Third_Party/FatFs/src/ff.c **** 			default:
+4997:Middlewares/Third_Party/FatFs/src/ff.c **** 				di = BS_VolID;
+4998:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+4999:Middlewares/Third_Party/FatFs/src/ff.c **** 			*vsn = ld_dword(fs->win + di);
+5000:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5001:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5002:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5003:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+5004:Middlewares/Third_Party/FatFs/src/ff.c **** }
+5005:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5006:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5007:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5008:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+5009:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5010:Middlewares/Third_Party/FatFs/src/ff.c **** /* Set Volume Label                                                      */
+5011:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5012:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5013:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_setlabel (
+5014:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* label	/* Pointer to the volume label to set */
+5015:Middlewares/Third_Party/FatFs/src/ff.c **** )
+5016:Middlewares/Third_Party/FatFs/src/ff.c **** {
+5017:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+5018:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+5019:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+5020:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE dirvn[22];
+5021:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, j, slen;
+5022:Middlewares/Third_Party/FatFs/src/ff.c **** 	WCHAR w;
+5023:Middlewares/Third_Party/FatFs/src/ff.c **** 	static const char badchr[] = "\"*+,.:;<=>\?[]|\x7F";
+5024:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5025:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5026:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get logical drive */
+5027:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&label, &fs, FA_WRITE);
+5028:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK) LEAVE_FF(fs, res);
+5029:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.fs = fs;
+5030:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5031:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get length of given volume label */
+5032:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (slen = 0; (UINT)label[slen] >= ' '; slen++) ;	/* Get name length */
+5033:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5034:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+5035:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+5036:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = j = 0; i < slen; ) {	/* Create volume label in directory form */
+5037:Middlewares/Third_Party/FatFs/src/ff.c **** 			w = label[i++];
+5038:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_LFN_UNICODE
+5039:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (IsDBCS1(w)) {
+ARM GAS  /tmp/cc5lWXRL.s 			page 121
+
+
+5040:Middlewares/Third_Party/FatFs/src/ff.c **** 				w = (i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0;
+5041:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5042:Middlewares/Third_Party/FatFs/src/ff.c **** 			w = ff_convert(w, 1);
+5043:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5044:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (w == 0 || chk_chr(badchr, w) || j == 22) {	/* Check validity check validity of the volume la
+5045:Middlewares/Third_Party/FatFs/src/ff.c **** 				LEAVE_FF(fs, FR_INVALID_NAME);
+5046:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5047:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(dirvn + j, w); j += 2;
+5048:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5049:Middlewares/Third_Party/FatFs/src/ff.c **** 		slen = j;
+5050:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else
+5051:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5052:Middlewares/Third_Party/FatFs/src/ff.c **** 	{	/* On the FAT12/16/32 volume */
+5053:Middlewares/Third_Party/FatFs/src/ff.c **** 		for ( ; slen && label[slen - 1] == ' '; slen--) ;	/* Remove trailing spaces */
+5054:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (slen) {		/* Is there a volume label to be set? */
+5055:Middlewares/Third_Party/FatFs/src/ff.c **** 			dirvn[0] = 0; i = j = 0;	/* Create volume label in directory form */
+5056:Middlewares/Third_Party/FatFs/src/ff.c **** 			do {
+5057:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+5058:Middlewares/Third_Party/FatFs/src/ff.c **** 				w = ff_convert(ff_wtoupper(label[i++]), 0);
+5059:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+5060:Middlewares/Third_Party/FatFs/src/ff.c **** 				w = (BYTE)label[i++];
+5061:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (IsDBCS1(w)) {
+5062:Middlewares/Third_Party/FatFs/src/ff.c **** 					w = (j < 10 && i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0;
+5063:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5064:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+5065:Middlewares/Third_Party/FatFs/src/ff.c **** 				w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0);
+5066:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+5067:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (IsLower(w)) w -= 0x20;			/* To upper ASCII characters */
+5068:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT
+5069:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (w >= 0x80) w = ExCvt[w - 0x80];	/* To upper extended characters (SBCS cfg) */
+5070:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+5071:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!_DF1S && w >= 0x80) w = 0;		/* Reject extended characters (ASCII cfg) */
+5072:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5073:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5074:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5075:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (w == 0 || chk_chr(badchr, w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) {	/* Reject invalid ch
+5076:Middlewares/Third_Party/FatFs/src/ff.c **** 					LEAVE_FF(fs, FR_INVALID_NAME);
+5077:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5078:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (w >= 0x100) dirvn[j++] = (BYTE)(w >> 8);
+5079:Middlewares/Third_Party/FatFs/src/ff.c **** 				dirvn[j++] = (BYTE)w;
+5080:Middlewares/Third_Party/FatFs/src/ff.c **** 			} while (i < slen);
+5081:Middlewares/Third_Party/FatFs/src/ff.c **** 			while (j < 11) dirvn[j++] = ' ';	/* Fill remaining name field */
+5082:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME);	/* Reject illegal name (heading DDEM) */
+5083:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5084:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5085:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5086:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Set volume label */
+5087:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.sclust = 0;		/* Open root directory */
+5088:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = dir_sdi(&dj, 0);
+5089:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+5090:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = dir_read(&dj, 1);	/* Get volume label entry */
+5091:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+5092:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+5093:Middlewares/Third_Party/FatFs/src/ff.c **** 				dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2);	/* Change the volume label */
+5094:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_cpy(dj.dir + XDIR_Label, dirvn, slen);
+5095:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+5096:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (slen) {
+ARM GAS  /tmp/cc5lWXRL.s 			page 122
+
+
+5097:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(dj.dir, dirvn, 11);	/* Change the volume label */
+5098:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+5099:Middlewares/Third_Party/FatFs/src/ff.c **** 					dj.dir[DIR_Name] = DDEM;	/* Remove the volume label */
+5100:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5101:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5102:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+5103:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = sync_fs(fs);
+5104:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {			/* No volume label entry is found or error */
+5105:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_NO_FILE) {
+5106:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_OK;
+5107:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (slen) {	/* Create a volume label entry */
+5108:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = dir_alloc(&dj, 1);	/* Allocate an entry */
+5109:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res == FR_OK) {
+5110:Middlewares/Third_Party/FatFs/src/ff.c **** 						mem_set(dj.dir, 0, SZDIRE);	/* Clear the entry */
+5111:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+5112:Middlewares/Third_Party/FatFs/src/ff.c **** 							dj.dir[XDIR_Type] = 0x83;		/* Create 83 entry */
+5113:Middlewares/Third_Party/FatFs/src/ff.c **** 							dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2);
+5114:Middlewares/Third_Party/FatFs/src/ff.c **** 							mem_cpy(dj.dir + XDIR_Label, dirvn, slen);
+5115:Middlewares/Third_Party/FatFs/src/ff.c **** 						} else {
+5116:Middlewares/Third_Party/FatFs/src/ff.c **** 							dj.dir[DIR_Attr] = AM_VOL;		/* Create volume label entry */
+5117:Middlewares/Third_Party/FatFs/src/ff.c **** 							mem_cpy(dj.dir, dirvn, 11);
+5118:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+5119:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+5120:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = sync_fs(fs);
+5121:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+5122:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5123:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5124:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5125:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5126:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5127:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+5128:Middlewares/Third_Party/FatFs/src/ff.c **** }
+5129:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5130:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */
+5131:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_LABEL */
+5132:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5133:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5134:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5135:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_EXPAND && !_FS_READONLY
+5136:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5137:Middlewares/Third_Party/FatFs/src/ff.c **** /* Allocate a Contiguous Blocks to the File                              */
+5138:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5139:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5140:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_expand (
+5141:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp,		/* Pointer to the file object */
+5142:Middlewares/Third_Party/FatFs/src/ff.c **** 	FSIZE_t fsz,	/* File size to be expanded to */
+5143:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE opt		/* Operation mode 0:Find and prepare or 1:Find and allocate */
+5144:Middlewares/Third_Party/FatFs/src/ff.c **** )
+5145:Middlewares/Third_Party/FatFs/src/ff.c **** {
+5146:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+5147:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+5148:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD n, clst, stcl, scl, ncl, tcl, lclst;
+5149:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5150:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5151:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+5152:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+5153:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);
+ARM GAS  /tmp/cc5lWXRL.s 			page 123
+
+
+5154:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+5155:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED);	/* Check if in size li
+5156:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5157:Middlewares/Third_Party/FatFs/src/ff.c **** 	n = (DWORD)fs->csize * SS(fs);	/* Cluster size */
+5158:Middlewares/Third_Party/FatFs/src/ff.c **** 	tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0);	/* Number of clusters required */
+5159:Middlewares/Third_Party/FatFs/src/ff.c **** 	stcl = fs->last_clst; lclst = 0;
+5160:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2;
+5161:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5162:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+5163:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type == FS_EXFAT) {
+5164:Middlewares/Third_Party/FatFs/src/ff.c **** 		scl = find_bitmap(fs, stcl, tcl);			/* Find a contiguous cluster block */
+5165:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (scl == 0) res = FR_DENIED;				/* No contiguous cluster block was found */
+5166:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (scl == 0xFFFFFFFF) res = FR_DISK_ERR;
+5167:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {	/* A contiguous free area is found */
+5168:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (opt) {		/* Allocate it now */
+5169:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = change_bitmap(fs, scl, tcl, 1);	/* Mark the cluster block 'in use' */
+5170:Middlewares/Third_Party/FatFs/src/ff.c **** 				lclst = scl + tcl - 1;
+5171:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {		/* Set it as suggested point for next allocation */
+5172:Middlewares/Third_Party/FatFs/src/ff.c **** 				lclst = scl - 1;
+5173:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5174:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5175:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else
+5176:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5177:Middlewares/Third_Party/FatFs/src/ff.c **** 	{
+5178:Middlewares/Third_Party/FatFs/src/ff.c **** 		scl = clst = stcl; ncl = 0;
+5179:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (;;) {	/* Find a contiguous cluster block */
+5180:Middlewares/Third_Party/FatFs/src/ff.c **** 			n = get_fat(&fp->obj, clst);
+5181:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (++clst >= fs->n_fatent) clst = 2;
+5182:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (n == 1) { res = FR_INT_ERR; break; }
+5183:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+5184:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (n == 0) {	/* Is it a free cluster? */
+5185:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (++ncl == tcl) break;	/* Break if a contiguous cluster block is found */
+5186:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+5187:Middlewares/Third_Party/FatFs/src/ff.c **** 				scl = clst; ncl = 0;		/* Not a free cluster */
+5188:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5189:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (clst == stcl) { res = FR_DENIED; break; }	/* No contiguous cluster? */
+5190:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5191:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {	/* A contiguous free area is found */
+5192:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (opt) {		/* Allocate it now */
+5193:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (clst = scl, n = tcl; n; clst++, n--) {	/* Create a cluster chain on the FAT */
+5194:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1);
+5195:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res != FR_OK) break;
+5196:Middlewares/Third_Party/FatFs/src/ff.c **** 					lclst = clst;
+5197:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5198:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {		/* Set it as suggested point for next allocation */
+5199:Middlewares/Third_Party/FatFs/src/ff.c **** 				lclst = scl - 1;
+5200:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5201:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5202:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5203:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5204:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+5205:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->last_clst = lclst;		/* Set suggested start cluster to start next */
+5206:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (opt) {	/* Is it allocated now? */
+5207:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.sclust = scl;		/* Update object allocation information */
+5208:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.objsize = fsz;
+5209:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (_FS_EXFAT) fp->obj.stat = 2;	/* Set status 'contiguous chain' */
+5210:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->flag |= FA_MODIFIED;
+ARM GAS  /tmp/cc5lWXRL.s 			page 124
+
+
+5211:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->free_clst <= fs->n_fatent - 2) {	/* Update FSINFO */
+5212:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->free_clst -= tcl;
+5213:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->fsi_flag |= 1;
+5214:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5215:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5216:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5217:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5218:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+5219:Middlewares/Third_Party/FatFs/src/ff.c **** }
+5220:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5221:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_EXPAND && !_FS_READONLY */
+5222:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5223:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5224:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5225:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FORWARD
+5226:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5227:Middlewares/Third_Party/FatFs/src/ff.c **** /* Forward data to the stream directly                                   */
+5228:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5229:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5230:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_forward (
+5231:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp, 						/* Pointer to the file object */
+5232:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT (*func)(const BYTE*,UINT),	/* Pointer to the streaming function */
+5233:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT btf,						/* Number of bytes to forward */
+5234:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT* bf						/* Pointer to number of bytes forwarded */
+5235:Middlewares/Third_Party/FatFs/src/ff.c **** )
+5236:Middlewares/Third_Party/FatFs/src/ff.c **** {
+5237:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+5238:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+5239:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst, sect;
+5240:Middlewares/Third_Party/FatFs/src/ff.c **** 	FSIZE_t remain;
+5241:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT rcnt, csect;
+5242:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *dbuf;
+5243:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5244:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5245:Middlewares/Third_Party/FatFs/src/ff.c **** 	*bf = 0;	/* Clear transfer byte counter */
+5246:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+5247:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+5248:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+5249:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5250:Middlewares/Third_Party/FatFs/src/ff.c **** 	remain = fp->obj.objsize - fp->fptr;
+5251:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (btf > remain) btf = (UINT)remain;			/* Truncate btf by remaining bytes */
+5252:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5253:Middlewares/Third_Party/FatFs/src/ff.c **** 	for ( ;  btf && (*func)(0, 0);					/* Repeat until all data transferred or stream goes busy */
+5254:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) {
+5255:Middlewares/Third_Party/FatFs/src/ff.c **** 		csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+5256:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {				/* On the sector boundary? */
+5257:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (csect == 0) {						/* On the cluster boundary? */
+5258:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = (fp->fptr == 0) ?			/* On the top of the file? */
+5259:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.sclust : get_fat(&fp->obj, fp->clust);
+5260:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst <= 1) ABORT(fs, FR_INT_ERR);
+5261:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+5262:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;					/* Update current cluster */
+5263:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5264:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5265:Middlewares/Third_Party/FatFs/src/ff.c **** 		sect = clust2sect(fs, fp->clust);			/* Get current data sector */
+5266:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!sect) ABORT(fs, FR_INT_ERR);
+5267:Middlewares/Third_Party/FatFs/src/ff.c **** 		sect += csect;
+ARM GAS  /tmp/cc5lWXRL.s 			page 125
+
+
+5268:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+5269:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window to the file dat
+5270:Middlewares/Third_Party/FatFs/src/ff.c **** 		dbuf = fs->win;
+5271:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+5272:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->sect != sect) {		/* Fill sector cache with file data */
+5273:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+5274:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+5275:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+5276:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+5277:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5278:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5279:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+5280:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5281:Middlewares/Third_Party/FatFs/src/ff.c **** 		dbuf = fp->buf;
+5282:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5283:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->sect = sect;
+5284:Middlewares/Third_Party/FatFs/src/ff.c **** 		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+5285:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rcnt > btf) rcnt = btf;					/* Clip it by btr if needed */
+5286:Middlewares/Third_Party/FatFs/src/ff.c **** 		rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt);	/* Forward the file data */
+5287:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!rcnt) ABORT(fs, FR_INT_ERR);
+5288:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5289:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5290:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, FR_OK);
+5291:Middlewares/Third_Party/FatFs/src/ff.c **** }
+5292:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_FORWARD */
+5293:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5294:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5295:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5296:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_MKFS && !_FS_READONLY
+5297:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5298:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create an FAT/exFAT volume                                            */
+5299:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5300:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5301:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_mkfs (
+5302:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* path,	/* Logical drive number */
+5303:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE opt,			/* Format option */
+5304:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD au,			/* Size of allocation unit (cluster) [byte] */
+5305:Middlewares/Third_Party/FatFs/src/ff.c **** 	void* work,			/* Pointer to working buffer */
+5306:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT len			/* Size of working buffer */
+5307:Middlewares/Third_Party/FatFs/src/ff.c **** )
+5308:Middlewares/Third_Party/FatFs/src/ff.c **** {
+5309:Middlewares/Third_Party/FatFs/src/ff.c **** 	const UINT n_fats = 1;		/* Number of FATs for FAT12/16/32 volume (1 or 2) */
+5310:Middlewares/Third_Party/FatFs/src/ff.c **** 	const UINT n_rootdir = 512;	/* Number of root directory entries for FAT12/16 volume */
+5311:Middlewares/Third_Party/FatFs/src/ff.c **** 	static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0};	/* Cluster size boundary for FAT12/16 volum
+5312:Middlewares/Third_Party/FatFs/src/ff.c **** 	static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0};	/* Cluster size boundary for FAT32 volume (12
+5313:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE fmt, sys, *buf, *pte, pdrv, part;
+5314:Middlewares/Third_Party/FatFs/src/ff.c **** 	WORD ss;
+5315:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n;
+5316:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD b_vol, b_fat, b_data;				/* Base LBA for volume, fat, data */
+5317:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD sz_vol, sz_rsv, sz_fat, sz_dir;	/* Size for volume, fat, dir, data */
+5318:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+5319:Middlewares/Third_Party/FatFs/src/ff.c **** 	int vol;
+5320:Middlewares/Third_Party/FatFs/src/ff.c **** 	DSTATUS stat;
+5321:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM || _FS_EXFAT
+5322:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD tbl[3];
+5323:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5324:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 126
+
+
+5325:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5326:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Check mounted drive and clear work area */
+5327:Middlewares/Third_Party/FatFs/src/ff.c **** 	vol = get_ldnumber(&path);					/* Get target logical drive */
+5328:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+5329:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (FatFs[vol]) FatFs[vol]->fs_type = 0;	/* Clear the volume */
+5330:Middlewares/Third_Party/FatFs/src/ff.c **** 	pdrv = LD2PD(vol);	/* Physical drive */
+5331:Middlewares/Third_Party/FatFs/src/ff.c **** 	part = LD2PT(vol);	/* Partition (0:create as new, 1-4:get from partition table) */
+5332:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5333:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Check physical drive status */
+5334:Middlewares/Third_Party/FatFs/src/ff.c **** 	stat = disk_initialize(pdrv);
+5335:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_NOINIT) return FR_NOT_READY;
+5336:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & 
+5338:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+5339:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR;
+5340:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+5341:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+5342:Middlewares/Third_Party/FatFs/src/ff.c **** 	ss = _MAX_SS;
+5343:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5344:Middlewares/Third_Party/FatFs/src/ff.c **** 	if ((au != 0 && au < ss) || au > 0x1000000 || (au & (au - 1))) return FR_INVALID_PARAMETER;	/* Che
+5345:Middlewares/Third_Party/FatFs/src/ff.c **** 	au /= ss;	/* Cluster size in unit of sector */
+5346:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5347:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Get working buffer */
+5348:Middlewares/Third_Party/FatFs/src/ff.c **** 	buf = (BYTE*)work;		/* Working buffer */
+5349:Middlewares/Third_Party/FatFs/src/ff.c **** 	sz_buf = len / ss;		/* Size of working buffer (sector) */
+5350:Middlewares/Third_Party/FatFs/src/ff.c **** 	szb_buf = sz_buf * ss;	/* Size of working buffer (byte) */
+5351:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!szb_buf) return FR_MKFS_ABORTED;
+5352:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5353:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Determine where the volume to be located (b_vol, sz_vol) */
+5354:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (_MULTI_PARTITION && part != 0) {
+5355:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Get partition information from partition table in the MBR */
+5356:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Load MBR */
+5357:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ld_word(buf + BS_55AA) != 0xAA55) return FR_MKFS_ABORTED;	/* Check if MBR is valid */
+5358:Middlewares/Third_Party/FatFs/src/ff.c **** 		pte = buf + (MBR_Table + (part - 1) * SZ_PTE);
+5359:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!pte[PTE_System]) return FR_MKFS_ABORTED;	/* No partition? */
+5360:Middlewares/Third_Party/FatFs/src/ff.c **** 		b_vol = ld_dword(pte + PTE_StLba);		/* Get volume start sector */
+5361:Middlewares/Third_Party/FatFs/src/ff.c **** 		sz_vol = ld_dword(pte + PTE_SizLba);	/* Get volume size */
+5362:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else {
+5363:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Create a single-partition in this function */
+5364:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) return FR_DISK_ERR;
+5365:Middlewares/Third_Party/FatFs/src/ff.c **** 		b_vol = (opt & FM_SFD) ? 0 : 63;		/* Volume start sector */
+5366:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (sz_vol < b_vol) return FR_MKFS_ABORTED;
+5367:Middlewares/Third_Party/FatFs/src/ff.c **** 		sz_vol -= b_vol;						/* Volume size */
+5368:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5369:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (sz_vol < 128) return FR_MKFS_ABORTED;	/* Check if volume size is >=128s */
+5370:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5371:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Pre-determine the FAT type */
+5372:Middlewares/Third_Party/FatFs/src/ff.c **** 	do {
+5373:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_EXFAT && (opt & FM_EXFAT)) {	/* exFAT possible? */
+5374:Middlewares/Third_Party/FatFs/src/ff.c **** 			if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) {	/* exFAT only, vol >= 64Ms 
+5375:Middlewares/Third_Party/FatFs/src/ff.c **** 				fmt = FS_EXFAT; break;
+5376:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5377:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5378:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (au > 128) return FR_INVALID_PARAMETER;	/* Too large au for FAT/FAT32 */
+5379:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (opt & FM_FAT32) {	/* FAT32 possible? */
+5380:Middlewares/Third_Party/FatFs/src/ff.c **** 			if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) {	/* FAT32 only or no-FAT? */
+5381:Middlewares/Third_Party/FatFs/src/ff.c **** 				fmt = FS_FAT32; break;
+ARM GAS  /tmp/cc5lWXRL.s 			page 127
+
+
+5382:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5383:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5384:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(opt & FM_FAT)) return FR_INVALID_PARAMETER;	/* no-FAT? */
+5385:Middlewares/Third_Party/FatFs/src/ff.c **** 		fmt = FS_FAT16;
+5386:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (0);
+5387:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5388:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+5389:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fmt == FS_EXFAT) {	/* Create an exFAT volume */
+5390:Middlewares/Third_Party/FatFs/src/ff.c **** 		DWORD szb_bit, szb_case, sum, nb, cl;
+5391:Middlewares/Third_Party/FatFs/src/ff.c **** 		WCHAR ch, si;
+5392:Middlewares/Third_Party/FatFs/src/ff.c **** 		UINT j, st;
+5393:Middlewares/Third_Party/FatFs/src/ff.c **** 		BYTE b;
+5394:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5395:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (sz_vol < 0x1000) return FR_MKFS_ABORTED;	/* Too small volume? */
+5396:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM
+5397:Middlewares/Third_Party/FatFs/src/ff.c **** 		tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1;	/* Inform the device the volume area may be erased *
+5398:Middlewares/Third_Party/FatFs/src/ff.c **** 		disk_ioctl(pdrv, CTRL_TRIM, tbl);
+5399:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5400:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Determine FAT location, data location and number of clusters */
+5401:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!au) {	/* au auto-selection */
+5402:Middlewares/Third_Party/FatFs/src/ff.c **** 			au = 8;
+5403:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (sz_vol >= 0x80000) au = 64;		/* >= 512Ks */
+5404:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (sz_vol >= 0x4000000) au = 256;	/* >= 64Ms */
+5405:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5406:Middlewares/Third_Party/FatFs/src/ff.c **** 		b_fat = b_vol + 32;										/* FAT start at offset 32 */
+5407:Middlewares/Third_Party/FatFs/src/ff.c **** 		sz_fat = ((sz_vol / au + 2) * 4 + ss - 1) / ss;			/* Number of FAT sectors */
+5408:Middlewares/Third_Party/FatFs/src/ff.c **** 		b_data = (b_fat + sz_fat + sz_blk - 1) & ~(sz_blk - 1);	/* Align data area to the erase block bou
+5409:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (b_data >= sz_vol / 2) return FR_MKFS_ABORTED;		/* Too small volume? */
+5410:Middlewares/Third_Party/FatFs/src/ff.c **** 		n_clst = (sz_vol - (b_data - b_vol)) / au;				/* Number of clusters */
+5411:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (n_clst <16) return FR_MKFS_ABORTED;					/* Too few clusters? */
+5412:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (n_clst > MAX_EXFAT) return FR_MKFS_ABORTED;			/* Too many clusters? */
+5413:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5414:Middlewares/Third_Party/FatFs/src/ff.c **** 		szb_bit = (n_clst + 7) / 8;						/* Size of allocation bitmap */
+5415:Middlewares/Third_Party/FatFs/src/ff.c **** 		tbl[0] = (szb_bit + au * ss - 1) / (au * ss);	/* Number of allocation bitmap clusters */
+5416:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5417:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Create a compressed up-case table */
+5418:Middlewares/Third_Party/FatFs/src/ff.c **** 		sect = b_data + au * tbl[0];	/* Table start sector */
+5419:Middlewares/Third_Party/FatFs/src/ff.c **** 		sum = 0;						/* Table checksum to be stored in the 82 entry */
+5420:Middlewares/Third_Party/FatFs/src/ff.c **** 		st = si = i = j = szb_case = 0;
+5421:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+5422:Middlewares/Third_Party/FatFs/src/ff.c **** 			switch (st) {
+5423:Middlewares/Third_Party/FatFs/src/ff.c **** 			case 0:
+5424:Middlewares/Third_Party/FatFs/src/ff.c **** 				ch = ff_wtoupper(si);	/* Get an up-case char */
+5425:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (ch != si) {
+5426:Middlewares/Third_Party/FatFs/src/ff.c **** 					si++; break;		/* Store the up-case char if exist */
+5427:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5428:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ;	/* Get r
+5429:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (j >= 128) {
+5430:Middlewares/Third_Party/FatFs/src/ff.c **** 					ch = 0xFFFF; st = 2; break;	/* Compress the no-case block if run is >= 128 */
+5431:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5432:Middlewares/Third_Party/FatFs/src/ff.c **** 				st = 1;			/* Do not compress short run */
+5433:Middlewares/Third_Party/FatFs/src/ff.c **** 				/* go to next case */
+5434:Middlewares/Third_Party/FatFs/src/ff.c **** 			case 1:
+5435:Middlewares/Third_Party/FatFs/src/ff.c **** 				ch = si++;		/* Fill the short run */
+5436:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (--j == 0) st = 0;
+5437:Middlewares/Third_Party/FatFs/src/ff.c **** 				break;
+5438:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 128
+
+
+5439:Middlewares/Third_Party/FatFs/src/ff.c **** 			default:
+5440:Middlewares/Third_Party/FatFs/src/ff.c **** 				ch = (WCHAR)j; si += j;	/* Number of chars to skip */
+5441:Middlewares/Third_Party/FatFs/src/ff.c **** 				st = 0;
+5442:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5443:Middlewares/Third_Party/FatFs/src/ff.c **** 			sum = xsum32(buf[i + 0] = (BYTE)ch, sum);		/* Put it into the write buffer */
+5444:Middlewares/Third_Party/FatFs/src/ff.c **** 			sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum);
+5445:Middlewares/Third_Party/FatFs/src/ff.c **** 			i += 2; szb_case += 2;
+5446:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!si || i == szb_buf) {		/* Write buffered data when buffer full or end of process */
+5447:Middlewares/Third_Party/FatFs/src/ff.c **** 				n = (i + ss - 1) / ss;
+5448:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+5449:Middlewares/Third_Party/FatFs/src/ff.c **** 				sect += n; i = 0;
+5450:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5451:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (si);
+5452:Middlewares/Third_Party/FatFs/src/ff.c **** 		tbl[1] = (szb_case + au * ss - 1) / (au * ss);	/* Number of up-case table clusters */
+5453:Middlewares/Third_Party/FatFs/src/ff.c **** 		tbl[2] = 1;										/* Number of root dir clusters */
+5454:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5455:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Initialize the allocation bitmap */
+5456:Middlewares/Third_Party/FatFs/src/ff.c **** 		sect = b_data; nsect = (szb_bit + ss - 1) / ss;	/* Start of bitmap and number of sectors */
+5457:Middlewares/Third_Party/FatFs/src/ff.c **** 		nb = tbl[0] + tbl[1] + tbl[2];					/* Number of clusters in-use by system */
+5458:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+5459:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, szb_buf);
+5460:Middlewares/Third_Party/FatFs/src/ff.c **** 			for (i = 0; nb >= 8 && i < szb_buf; buf[i++] = 0xFF, nb -= 8) ;
+5461:Middlewares/Third_Party/FatFs/src/ff.c **** 			for (b = 1; nb && i < szb_buf; buf[i] |= b, b <<= 1, nb--) ;
+5462:Middlewares/Third_Party/FatFs/src/ff.c **** 			n = (nsect > sz_buf) ? sz_buf : nsect;		/* Write the buffered data */
+5463:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+5464:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += n; nsect -= n;
+5465:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (nsect);
+5466:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5467:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Initialize the FAT */
+5468:Middlewares/Third_Party/FatFs/src/ff.c **** 		sect = b_fat; nsect = sz_fat;	/* Start of FAT and number of FAT sectors */
+5469:Middlewares/Third_Party/FatFs/src/ff.c **** 		j = nb = cl = 0;
+5470:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+5471:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, szb_buf); i = 0;	/* Clear work area and reset write index */
+5472:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cl == 0) {	/* Set entry 0 and 1 */
+5473:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(buf + i, 0xFFFFFFF8); i += 4; cl++;
+5474:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(buf + i, 0xFFFFFFFF); i += 4; cl++;
+5475:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5476:Middlewares/Third_Party/FatFs/src/ff.c **** 			do {			/* Create chains of bitmap, up-case and root dir */
+5477:Middlewares/Third_Party/FatFs/src/ff.c **** 				while (nb && i < szb_buf) {			/* Create a chain */
+5478:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(buf + i, (nb > 1) ? cl + 1 : 0xFFFFFFFF);
+5479:Middlewares/Third_Party/FatFs/src/ff.c **** 					i += 4; cl++; nb--;
+5480:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5481:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!nb && j < 3) nb = tbl[j++];	/* Next chain */
+5482:Middlewares/Third_Party/FatFs/src/ff.c **** 			} while (nb && i < szb_buf);
+5483:Middlewares/Third_Party/FatFs/src/ff.c **** 			n = (nsect > sz_buf) ? sz_buf : nsect;	/* Write the buffered data */
+5484:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+5485:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += n; nsect -= n;
+5486:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (nsect);
+5487:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5488:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Initialize the root directory */
+5489:Middlewares/Third_Party/FatFs/src/ff.c **** 		mem_set(buf, 0, szb_buf);
+5490:Middlewares/Third_Party/FatFs/src/ff.c **** 		buf[SZDIRE * 0 + 0] = 0x83;		/* 83 entry (volume label) */
+5491:Middlewares/Third_Party/FatFs/src/ff.c **** 		buf[SZDIRE * 1 + 0] = 0x81;		/* 81 entry (allocation bitmap) */
+5492:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_dword(buf + SZDIRE * 1 + 20, 2);
+5493:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_dword(buf + SZDIRE * 1 + 24, szb_bit);
+5494:Middlewares/Third_Party/FatFs/src/ff.c **** 		buf[SZDIRE * 2 + 0] = 0x82;		/* 82 entry (up-case table) */
+5495:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_dword(buf + SZDIRE * 2 + 4, sum);
+ARM GAS  /tmp/cc5lWXRL.s 			page 129
+
+
+5496:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_dword(buf + SZDIRE * 2 + 20, 2 + tbl[0]);
+5497:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_dword(buf + SZDIRE * 2 + 24, szb_case);
+5498:Middlewares/Third_Party/FatFs/src/ff.c **** 		sect = b_data + au * (tbl[0] + tbl[1]);	nsect = au;	/* Start of the root directory and number of 
+5499:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {	/* Fill root directory sectors */
+5500:Middlewares/Third_Party/FatFs/src/ff.c **** 			n = (nsect > sz_buf) ? sz_buf : nsect;
+5501:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+5502:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, ss);
+5503:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += n; nsect -= n;
+5504:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (nsect);
+5505:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5506:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Create two set of the exFAT VBR blocks */
+5507:Middlewares/Third_Party/FatFs/src/ff.c **** 		sect = b_vol;
+5508:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (n = 0; n < 2; n++) {
+5509:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Main record (+0) */
+5510:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, ss);
+5511:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_cpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11);	/* Boot jump code (x86), OEM name */
+5512:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_VolOfsEx, b_vol);					/* Volume offset in the physical drive [sector] */
+5513:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_TotSecEx, sz_vol);					/* Volume size [sector] */
+5514:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_FatOfsEx, b_fat - b_vol);			/* FAT offset [sector] */
+5515:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_FatSzEx, sz_fat);					/* FAT size [sector] */
+5516:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_DataOfsEx, b_data - b_vol);			/* Data offset [sector] */
+5517:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_NumClusEx, n_clst);					/* Number of clusters */
+5518:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_RootClusEx, 2 + tbl[0] + tbl[1]);	/* Root dir cluster # */
+5519:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_VolIDEx, GET_FATTIME());				/* VSN */
+5520:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BPB_FSVerEx, 0x100);						/* File system version (1.00) */
+5521:Middlewares/Third_Party/FatFs/src/ff.c **** 			for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ;	/* Log2 of sector si
+5522:Middlewares/Third_Party/FatFs/src/ff.c **** 			for (buf[BPB_SecPerClusEx] = 0, i = au; i >>= 1; buf[BPB_SecPerClusEx]++) ;	/* Log2 of cluster s
+5523:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BPB_NumFATsEx] = 1;					/* Number of FATs */
+5524:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BPB_DrvNumEx] = 0x80;				/* Drive number (for int13) */
+5525:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BS_BootCodeEx, 0xFEEB);	/* Boot code (x86) */
+5526:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BS_55AA, 0xAA55);			/* Signature (placed here regardless of sector size) */
+5527:Middlewares/Third_Party/FatFs/src/ff.c **** 			for (i = sum = 0; i < ss; i++) {		/* VBR checksum */
+5528:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], 
+5529:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5530:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+5531:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Extended bootstrap record (+1..+8) */
+5532:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, ss);
+5533:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + ss - 2, 0xAA55);	/* Signature (placed at end of sector) */
+5534:Middlewares/Third_Party/FatFs/src/ff.c **** 			for (j = 1; j < 9; j++) {
+5535:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+5536:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+5537:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5538:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* OEM/Reserved record (+9..+10) */
+5539:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, ss);
+5540:Middlewares/Third_Party/FatFs/src/ff.c **** 			for ( ; j < 11; j++) {
+5541:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+5542:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+5543:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5544:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Sum record (+11) */
+5545:Middlewares/Third_Party/FatFs/src/ff.c **** 			for (i = 0; i < ss; i += 4) st_dword(buf + i, sum);		/* Fill with checksum value */
+5546:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+5547:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5548:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5549:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else
+5550:Middlewares/Third_Party/FatFs/src/ff.c **** #endif	/* _FS_EXFAT */
+5551:Middlewares/Third_Party/FatFs/src/ff.c **** 	{	/* Create an FAT12/16/32 volume */
+5552:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+ARM GAS  /tmp/cc5lWXRL.s 			page 130
+
+
+5553:Middlewares/Third_Party/FatFs/src/ff.c **** 			pau = au;
+5554:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Pre-determine number of clusters and FAT sub-type */
+5555:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {	/* FAT32 volume */
+5556:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!pau) {	/* au auto-selection */
+5557:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = sz_vol / 0x20000;	/* Volume size in unit of 128KS */
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 					for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+5559:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5560:Middlewares/Third_Party/FatFs/src/ff.c **** 				n_clst = sz_vol / pau;	/* Number of clusters */
+5561:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_fat = (n_clst * 4 + 8 + ss - 1) / ss;	/* FAT size [sector] */
+5562:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv = 32;	/* Number of reserved sectors */
+5563:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_dir = 0;		/* No static directory */
+5564:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) return FR_MKFS_ABORTED;
+5565:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {				/* FAT12/16 volume */
+5566:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!pau) {	/* au auto-selection */
+5567:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = sz_vol / 0x1000;	/* Volume size in unit of 4KS */
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 					for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+5569:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5570:Middlewares/Third_Party/FatFs/src/ff.c **** 				n_clst = sz_vol / pau;
+5571:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst > MAX_FAT12) {
+5572:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = n_clst * 2 + 4;		/* FAT size [byte] */
+5573:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+5574:Middlewares/Third_Party/FatFs/src/ff.c **** 					fmt = FS_FAT12;
+5575:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = (n_clst * 3 + 1) / 2 + 3;	/* FAT size [byte] */
+5576:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5577:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_fat = (n + ss - 1) / ss;		/* FAT size [sector] */
+5578:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv = 1;						/* Number of reserved sectors */
+5579:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_dir = (DWORD)n_rootdir * SZDIRE / ss;	/* Rootdir size [sector] */
+5580:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5581:Middlewares/Third_Party/FatFs/src/ff.c **** 			b_fat = b_vol + sz_rsv;						/* FAT base */
+5582:Middlewares/Third_Party/FatFs/src/ff.c **** 			b_data = b_fat + sz_fat * n_fats + sz_dir;	/* Data base */
+5583:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5584:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Align data base to erase block boundary (for flash memory media) */
+5585:Middlewares/Third_Party/FatFs/src/ff.c **** 			n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data;	/* Next nearest erase block from current d
+5586:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
+5587:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv += n; b_fat += n;
+5588:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {					/* FAT12/16: Expand FAT size */
+5589:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_fat += n / n_fats;
+5590:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5591:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5592:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Determine number of clusters and final check of validity of the FAT sub-type */
+5593:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (sz_vol < b_data + pau * 16 - b_vol) return FR_MKFS_ABORTED;	/* Too small volume */
+5594:Middlewares/Third_Party/FatFs/src/ff.c **** 			n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau;
+5595:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+5596:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst <= MAX_FAT16) {	/* Too few clusters for FAT32 */
+5597:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!au && (au = pau / 2) != 0) continue;	/* Adjust cluster size and retry */
+5598:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+5599:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5600:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5601:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT16) {
+5602:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst > MAX_FAT16) {	/* Too many clusters for FAT16 */
+5603:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!au && (pau * 2) <= 64) {
+5604:Middlewares/Third_Party/FatFs/src/ff.c **** 						au = pau * 2; continue;		/* Adjust cluster size and retry */
+5605:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+5606:Middlewares/Third_Party/FatFs/src/ff.c **** 					if ((opt & FM_FAT32)) {
+5607:Middlewares/Third_Party/FatFs/src/ff.c **** 						fmt = FS_FAT32; continue;	/* Switch type to FAT32 and retry */
+5608:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+5609:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!au && (au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+ARM GAS  /tmp/cc5lWXRL.s 			page 131
+
+
+5610:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+5611:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5612:Middlewares/Third_Party/FatFs/src/ff.c **** 				if  (n_clst <= MAX_FAT12) {	/* Too few clusters for FAT16 */
+5613:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!au && (au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+5614:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+5615:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5616:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5617:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT12 && n_clst > MAX_FAT12) return FR_MKFS_ABORTED;	/* Too many clusters for FAT1
+5618:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5619:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Ok, it is the valid cluster configuration */
+5620:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+5621:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (1);
+5622:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5623:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM
+5624:Middlewares/Third_Party/FatFs/src/ff.c **** 		tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1;	/* Inform the device the volume area can be erased *
+5625:Middlewares/Third_Party/FatFs/src/ff.c **** 		disk_ioctl(pdrv, CTRL_TRIM, tbl);
+5626:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5627:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Create FAT VBR */
+5628:Middlewares/Third_Party/FatFs/src/ff.c **** 		mem_set(buf, 0, ss);
+5629:Middlewares/Third_Party/FatFs/src/ff.c **** 		mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */
+5630:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_BytsPerSec, ss);				/* Sector size [byte] */
+5631:Middlewares/Third_Party/FatFs/src/ff.c **** 		buf[BPB_SecPerClus] = (BYTE)pau;				/* Cluster size [sector] */
+5632:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv);	/* Size of reserved area */
+5633:Middlewares/Third_Party/FatFs/src/ff.c **** 		buf[BPB_NumFATs] = (BYTE)n_fats;				/* Number of FATs */
+5634:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir));	/* Number of root direc
+5635:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (sz_vol < 0x10000) {
+5636:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BPB_TotSec16, (WORD)sz_vol);	/* Volume size in 16-bit LBA */
+5637:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+5638:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_TotSec32, sz_vol);		/* Volume size in 32-bit LBA */
+5639:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5640:Middlewares/Third_Party/FatFs/src/ff.c **** 		buf[BPB_Media] = 0xF8;							/* Media descriptor byte */
+5641:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_SecPerTrk, 63);				/* Number of sectors per track (for int13) */
+5642:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_NumHeads, 255);				/* Number of heads (for int13) */
+5643:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_dword(buf + BPB_HiddSec, b_vol);				/* Volume offset in the physical drive [sector] */
+5644:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fmt == FS_FAT32) {
+5645:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BS_VolID32, GET_FATTIME());	/* VSN */
+5646:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_FATSz32, sz_fat);		/* FAT size [sector] */
+5647:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_RootClus32, 2);			/* Root directory cluster # (2) */
+5648:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BPB_FSInfo32, 1);				/* Offset of FSINFO sector (VBR + 1) */
+5649:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BPB_BkBootSec32, 6);			/* Offset of backup VBR (VBR + 6) */
+5650:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BS_DrvNum32] = 0x80;					/* Drive number (for int13) */
+5651:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BS_BootSig32] = 0x29;					/* Extended boot signature */
+5652:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_cpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+5653:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+5654:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BS_VolID, GET_FATTIME());	/* VSN */
+5655:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BPB_FATSz16, (WORD)sz_fat);	/* FAT size [sector] */
+5656:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BS_DrvNum] = 0x80;						/* Drive number (for int13) */
+5657:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BS_BootSig] = 0x29;						/* Extended boot signature */
+5658:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_cpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+5659:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5660:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BS_55AA, 0xAA55);					/* Signature (offset is fixed here regardless of sector size)
+5661:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the VBR sector 
+5662:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5663:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Create FSINFO record if needed */
+5664:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fmt == FS_FAT32) {
+5665:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(pdrv, buf, b_vol + 6, 1);		/* Write backup VBR (VBR + 6) */
+5666:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, ss);
+ARM GAS  /tmp/cc5lWXRL.s 			page 132
+
+
+5667:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + FSI_LeadSig, 0x41615252);
+5668:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + FSI_StrucSig, 0x61417272);
+5669:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
+5670:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + FSI_Nxt_Free, 2);			/* Last allocated cluster# */
+5671:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BS_55AA, 0xAA55);
+5672:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(pdrv, buf, b_vol + 7, 1);		/* Write backup FSINFO (VBR + 7) */
+5673:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(pdrv, buf, b_vol + 1, 1);		/* Write original FSINFO (VBR + 1) */
+5674:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5675:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5676:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Initialize FAT area */
+5677:Middlewares/Third_Party/FatFs/src/ff.c **** 		mem_set(buf, 0, (UINT)szb_buf);
+5678:Middlewares/Third_Party/FatFs/src/ff.c **** 		sect = b_fat;		/* FAT start sector */
+5679:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < n_fats; i++) {			/* Initialize FATs each */
+5680:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+5681:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(buf + 0, 0xFFFFFFF8);	/* Entry 0 */
+5682:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(buf + 4, 0xFFFFFFFF);	/* Entry 1 */
+5683:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(buf + 8, 0x0FFFFFFF);	/* Entry 2 (root directory) */
+5684:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+5685:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(buf + 0, (fmt == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8);	/* Entry 0 and 1 */
+5686:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5687:Middlewares/Third_Party/FatFs/src/ff.c **** 			nsect = sz_fat;		/* Number of FAT sectors */
+5688:Middlewares/Third_Party/FatFs/src/ff.c **** 			do {	/* Fill FAT sectors */
+5689:Middlewares/Third_Party/FatFs/src/ff.c **** 				n = (nsect > sz_buf) ? sz_buf : nsect;
+5690:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+5691:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_set(buf, 0, ss);
+5692:Middlewares/Third_Party/FatFs/src/ff.c **** 				sect += n; nsect -= n;
+5693:Middlewares/Third_Party/FatFs/src/ff.c **** 			} while (nsect);
+5694:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5695:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5696:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Initialize root directory (fill with zero) */
+5697:Middlewares/Third_Party/FatFs/src/ff.c **** 		nsect = (fmt == FS_FAT32) ? pau : sz_dir;	/* Number of root directory sectors */
+5698:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+5699:Middlewares/Third_Party/FatFs/src/ff.c **** 			n = (nsect > sz_buf) ? sz_buf : nsect;
+5700:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+5701:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += n; nsect -= n;
+5702:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (nsect);
+5703:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5704:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5705:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Determine system ID in the partition table */
+5706:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (_FS_EXFAT && fmt == FS_EXFAT) {
+5707:Middlewares/Third_Party/FatFs/src/ff.c **** 		sys = 0x07;			/* HPFS/NTFS/exFAT */
+5708:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else {
+5709:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fmt == FS_FAT32) {
+5710:Middlewares/Third_Party/FatFs/src/ff.c **** 			sys = 0x0C;		/* FAT32X */
+5711:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+5712:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (sz_vol >= 0x10000) {
+5713:Middlewares/Third_Party/FatFs/src/ff.c **** 				sys = 0x06;	/* FAT12/16 (>=64KS) */
+5714:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+5715:Middlewares/Third_Party/FatFs/src/ff.c **** 				sys = (fmt == FS_FAT16) ? 0x04 : 0x01;	/* FAT16 (<64KS) : FAT12 (<64KS) */
+5716:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5717:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5718:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5719:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5720:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Update partition information */
+5721:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (_MULTI_PARTITION && part != 0) {	/* Created in the existing partition */
+5722:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Update system ID in the partition table */
+5723:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Read the MBR */
+ARM GAS  /tmp/cc5lWXRL.s 			page 133
+
+
+5724:Middlewares/Third_Party/FatFs/src/ff.c **** 		buf[MBR_Table + (part - 1) * SZ_PTE + PTE_System] = sys;		/* Set system ID */
+5725:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Write it back to the MBR */
+5726:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else {								/* Created as a new single partition */
+5727:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(opt & FM_SFD)) {	/* Create partition table if in FDISK format */
+5728:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, ss);
+5729:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BS_55AA, 0xAA55);		/* MBR signature */
+5730:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte = buf + MBR_Table;				/* Create partition table for single partition in the drive */
+5731:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_Boot] = 0;					/* Boot indicator */
+5732:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_StHead] = 1;				/* Start head */
+5733:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_StSec] = 1;					/* Start sector */
+5734:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_StCyl] = 0;					/* Start cylinder */
+5735:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_System] = sys;				/* System type */
+5736:Middlewares/Third_Party/FatFs/src/ff.c **** 			n = (b_vol + sz_vol) / (63 * 255);	/* (End CHS may be invalid) */
+5737:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdHead] = 254;				/* End head */
+5738:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdSec] = (BYTE)(n >> 2 | 63);	/* End sector */
+5739:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdCyl] = (BYTE)n;			/* End cylinder */
+5740:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(pte + PTE_StLba, b_vol);	/* Start offset in LBA */
+5741:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(pte + PTE_SizLba, sz_vol);	/* Size in sectors */
+5742:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the MBR */
+5743:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5744:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5745:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5746:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) return FR_DISK_ERR;
+5747:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5748:Middlewares/Third_Party/FatFs/src/ff.c **** 	return FR_OK;
+5749:Middlewares/Third_Party/FatFs/src/ff.c **** }
+5750:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5751:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5752:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5753:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MULTI_PARTITION
+5754:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5755:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create partition table on the physical drive                          */
+5756:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5757:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5758:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_fdisk (
+5759:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE pdrv,			/* Physical drive number */
+5760:Middlewares/Third_Party/FatFs/src/ff.c **** 	const DWORD* szt,	/* Pointer to the size table for each partitions */
+5761:Middlewares/Third_Party/FatFs/src/ff.c **** 	void* work			/* Pointer to the working buffer */
+5762:Middlewares/Third_Party/FatFs/src/ff.c **** )
+5763:Middlewares/Third_Party/FatFs/src/ff.c **** {
+5764:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
+5765:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
+5766:Middlewares/Third_Party/FatFs/src/ff.c **** 	DSTATUS stat;
+5767:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD sz_disk, sz_part, s_part;
+5768:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5769:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5770:Middlewares/Third_Party/FatFs/src/ff.c **** 	stat = disk_initialize(pdrv);
+5771:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_NOINIT) return FR_NOT_READY;
+5772:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+5773:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
+5774:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5775:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Determine the CHS without any consideration of the drive geometry */
+5776:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
+5777:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (n == 256) n--;
+5778:Middlewares/Third_Party/FatFs/src/ff.c **** 	e_hd = n - 1;
+5779:Middlewares/Third_Party/FatFs/src/ff.c **** 	sz_cyl = 63 * n;
+5780:Middlewares/Third_Party/FatFs/src/ff.c **** 	tot_cyl = sz_disk / sz_cyl;
+ARM GAS  /tmp/cc5lWXRL.s 			page 134
+
+
+5781:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5782:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Create partition table */
+5783:Middlewares/Third_Party/FatFs/src/ff.c **** 	mem_set(buf, 0, _MAX_SS);
+5784:Middlewares/Third_Party/FatFs/src/ff.c **** 	p = buf + MBR_Table; b_cyl = 0;
+5785:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (i = 0; i < 4; i++, p += SZ_PTE) {
+5786:Middlewares/Third_Party/FatFs/src/ff.c **** 		p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl;	/* Number of cylinder
+5787:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!p_cyl) continue;
+5788:Middlewares/Third_Party/FatFs/src/ff.c **** 		s_part = (DWORD)sz_cyl * b_cyl;
+5789:Middlewares/Third_Party/FatFs/src/ff.c **** 		sz_part = (DWORD)sz_cyl * p_cyl;
+5790:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (i == 0) {	/* Exclude first track of cylinder 0 */
+5791:Middlewares/Third_Party/FatFs/src/ff.c **** 			s_hd = 1;
+5792:Middlewares/Third_Party/FatFs/src/ff.c **** 			s_part += 63; sz_part -= 63;
+5793:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+5794:Middlewares/Third_Party/FatFs/src/ff.c **** 			s_hd = 0;
+5795:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5796:Middlewares/Third_Party/FatFs/src/ff.c **** 		e_cyl = b_cyl + p_cyl - 1;	/* End cylinder */
+5797:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER;
+5798:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5799:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Set partition table */
+5800:Middlewares/Third_Party/FatFs/src/ff.c **** 		p[1] = s_hd;						/* Start head */
+5801:Middlewares/Third_Party/FatFs/src/ff.c **** 		p[2] = (BYTE)((b_cyl >> 2) + 1);	/* Start sector */
+5802:Middlewares/Third_Party/FatFs/src/ff.c **** 		p[3] = (BYTE)b_cyl;					/* Start cylinder */
+5803:Middlewares/Third_Party/FatFs/src/ff.c **** 		p[4] = 0x07;						/* System type (temporary setting) */
+5804:Middlewares/Third_Party/FatFs/src/ff.c **** 		p[5] = e_hd;						/* End head */
+5805:Middlewares/Third_Party/FatFs/src/ff.c **** 		p[6] = (BYTE)((e_cyl >> 2) + 63);	/* End sector */
+5806:Middlewares/Third_Party/FatFs/src/ff.c **** 		p[7] = (BYTE)e_cyl;					/* End cylinder */
+5807:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_dword(p + 8, s_part);			/* Start sector in LBA */
+5808:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_dword(p + 12, sz_part);			/* Number of sectors */
+5809:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5810:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Next partition */
+5811:Middlewares/Third_Party/FatFs/src/ff.c **** 		b_cyl += p_cyl;
+5812:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5813:Middlewares/Third_Party/FatFs/src/ff.c **** 	st_word(p, 0xAA55);
+5814:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5815:Middlewares/Third_Party/FatFs/src/ff.c **** 	/* Write it to the MBR */
+5816:Middlewares/Third_Party/FatFs/src/ff.c **** 	return (disk_write(pdrv, buf, 0, 1) != RES_OK || disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) ? FR_DI
+5817:Middlewares/Third_Party/FatFs/src/ff.c **** }
+5818:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5819:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _MULTI_PARTITION */
+5820:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_MKFS && !_FS_READONLY */
+5821:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5822:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5823:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5824:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5825:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_STRFUNC
+5826:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5827:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get a string from the file                                            */
+5828:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5829:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5830:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR* f_gets (
+5831:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR* buff,	/* Pointer to the string buffer to read */
+5832:Middlewares/Third_Party/FatFs/src/ff.c **** 	int len,		/* Size of string buffer (characters) */
+5833:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp			/* Pointer to the file object */
+5834:Middlewares/Third_Party/FatFs/src/ff.c **** )
+5835:Middlewares/Third_Party/FatFs/src/ff.c **** {
+5836:Middlewares/Third_Party/FatFs/src/ff.c **** 	int n = 0;
+5837:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR c, *p = buff;
+ARM GAS  /tmp/cc5lWXRL.s 			page 135
+
+
+5838:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE s[2];
+5839:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT rc;
+5840:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5841:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5842:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (n < len - 1) {	/* Read characters until buffer gets filled */
+5843:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+5844:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STRF_ENCODE == 3		/* Read a character in UTF-8 */
+5845:Middlewares/Third_Party/FatFs/src/ff.c **** 		f_read(fp, s, 1, &rc);
+5846:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rc != 1) break;
+5847:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = s[0];
+5848:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c >= 0x80) {
+5849:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (c < 0xC0) continue;	/* Skip stray trailer */
+5850:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (c < 0xE0) {			/* Two-byte sequence (0x80-0x7FF) */
+5851:Middlewares/Third_Party/FatFs/src/ff.c **** 				f_read(fp, s, 1, &rc);
+5852:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (rc != 1) break;
+5853:Middlewares/Third_Party/FatFs/src/ff.c **** 				c = (c & 0x1F) << 6 | (s[0] & 0x3F);
+5854:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (c < 0x80) c = '?';	/* Reject invalid code range */
+5855:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+5856:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (c < 0xF0) {		/* Three-byte sequence (0x800-0xFFFF) */
+5857:Middlewares/Third_Party/FatFs/src/ff.c **** 					f_read(fp, s, 2, &rc);
+5858:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (rc != 2) break;
+5859:Middlewares/Third_Party/FatFs/src/ff.c **** 					c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F);
+5860:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (c < 0x800) c = '?';	/* Reject invalid code range */
+5861:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {			/* Reject four-byte sequence */
+5862:Middlewares/Third_Party/FatFs/src/ff.c **** 					c = '?';
+5863:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+5864:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+5865:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5866:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _STRF_ENCODE == 2		/* Read a character in UTF-16BE */
+5867:Middlewares/Third_Party/FatFs/src/ff.c **** 		f_read(fp, s, 2, &rc);
+5868:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rc != 2) break;
+5869:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = s[1] + (s[0] << 8);
+5870:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _STRF_ENCODE == 1		/* Read a character in UTF-16LE */
+5871:Middlewares/Third_Party/FatFs/src/ff.c **** 		f_read(fp, s, 2, &rc);
+5872:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rc != 2) break;
+5873:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = s[0] + (s[1] << 8);
+5874:Middlewares/Third_Party/FatFs/src/ff.c **** #else						/* Read a character in ANSI/OEM */
+5875:Middlewares/Third_Party/FatFs/src/ff.c **** 		f_read(fp, s, 1, &rc);
+5876:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rc != 1) break;
+5877:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = s[0];
+5878:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (IsDBCS1(c)) {
+5879:Middlewares/Third_Party/FatFs/src/ff.c **** 			f_read(fp, s, 1, &rc);
+5880:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (rc != 1) break;
+5881:Middlewares/Third_Party/FatFs/src/ff.c **** 			c = (c << 8) + s[0];
+5882:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5883:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = ff_convert(c, 1);	/* OEM -> Unicode */
+5884:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!c) c = '?';
+5885:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5886:Middlewares/Third_Party/FatFs/src/ff.c **** #else						/* Read a character without conversion */
+5887:Middlewares/Third_Party/FatFs/src/ff.c **** 		f_read(fp, s, 1, &rc);
+5888:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rc != 1) break;
+5889:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = s[0];
+5890:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5891:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_USE_STRFUNC == 2 && c == '\r') continue;	/* Strip '\r' */
+5892:Middlewares/Third_Party/FatFs/src/ff.c **** 		*p++ = c;
+5893:Middlewares/Third_Party/FatFs/src/ff.c **** 		n++;
+5894:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == '\n') break;		/* Break on EOL */
+ARM GAS  /tmp/cc5lWXRL.s 			page 136
+
+
+5895:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5896:Middlewares/Third_Party/FatFs/src/ff.c **** 	*p = 0;
+5897:Middlewares/Third_Party/FatFs/src/ff.c **** 	return n ? buff : 0;			/* When no data read (eof or error), return with error. */
+5898:Middlewares/Third_Party/FatFs/src/ff.c **** }
+5899:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5900:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5901:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5902:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5903:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+5904:Middlewares/Third_Party/FatFs/src/ff.c **** #include 
+5905:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5906:Middlewares/Third_Party/FatFs/src/ff.c **** /* Put a character to the file                                           */
+5907:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+5908:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5909:Middlewares/Third_Party/FatFs/src/ff.c **** typedef struct {
+5910:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL *fp;		/* Ptr to the writing file */
+5911:Middlewares/Third_Party/FatFs/src/ff.c **** 	int idx, nchr;	/* Write index of buf[] (-1:error), number of chars written */
+5912:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE buf[64];	/* Write buffer */
+5913:Middlewares/Third_Party/FatFs/src/ff.c **** } putbuff;
+5914:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5915:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5916:Middlewares/Third_Party/FatFs/src/ff.c **** static
+5917:Middlewares/Third_Party/FatFs/src/ff.c **** void putc_bfd (		/* Buffered write with code conversion */
+5918:Middlewares/Third_Party/FatFs/src/ff.c **** 	putbuff* pb,
+5919:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR c
+5920:Middlewares/Third_Party/FatFs/src/ff.c **** )
+5921:Middlewares/Third_Party/FatFs/src/ff.c **** {
+5922:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT bw;
+5923:Middlewares/Third_Party/FatFs/src/ff.c **** 	int i;
+5924:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5925:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5926:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (_USE_STRFUNC == 2 && c == '\n') {	 /* LF -> CRLF conversion */
+5927:Middlewares/Third_Party/FatFs/src/ff.c **** 		putc_bfd(pb, '\r');
+5928:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5929:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5930:Middlewares/Third_Party/FatFs/src/ff.c **** 	i = pb->idx;		/* Write index of pb->buf[] */
+5931:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (i < 0) return;
+5932:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5933:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+5934:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STRF_ENCODE == 3			/* Write a character in UTF-8 */
+5935:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (c < 0x80) {				/* 7-bit */
+5936:Middlewares/Third_Party/FatFs/src/ff.c **** 		pb->buf[i++] = (BYTE)c;
+5937:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else {
+5938:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c < 0x800) {		/* 11-bit */
+5939:Middlewares/Third_Party/FatFs/src/ff.c **** 			pb->buf[i++] = (BYTE)(0xC0 | c >> 6);
+5940:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {				/* 16-bit */
+5941:Middlewares/Third_Party/FatFs/src/ff.c **** 			pb->buf[i++] = (BYTE)(0xE0 | c >> 12);
+5942:Middlewares/Third_Party/FatFs/src/ff.c **** 			pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F));
+5943:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+5944:Middlewares/Third_Party/FatFs/src/ff.c **** 		pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F));
+5945:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5946:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _STRF_ENCODE == 2			/* Write a character in UTF-16BE */
+5947:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->buf[i++] = (BYTE)(c >> 8);
+5948:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->buf[i++] = (BYTE)c;
+5949:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _STRF_ENCODE == 1			/* Write a character in UTF-16LE */
+5950:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->buf[i++] = (BYTE)c;
+5951:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->buf[i++] = (BYTE)(c >> 8);
+ARM GAS  /tmp/cc5lWXRL.s 			page 137
+
+
+5952:Middlewares/Third_Party/FatFs/src/ff.c **** #else							/* Write a character in ANSI/OEM */
+5953:Middlewares/Third_Party/FatFs/src/ff.c **** 	c = ff_convert(c, 0);	/* Unicode -> OEM */
+5954:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!c) c = '?';
+5955:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (c >= 0x100)
+5956:Middlewares/Third_Party/FatFs/src/ff.c **** 		pb->buf[i++] = (BYTE)(c >> 8);
+5957:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->buf[i++] = (BYTE)c;
+5958:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5959:Middlewares/Third_Party/FatFs/src/ff.c **** #else							/* Write a character without conversion */
+5960:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->buf[i++] = (BYTE)c;
+5961:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+5962:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5963:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (i >= (int)(sizeof pb->buf) - 3) {	/* Write buffered characters to the file */
+5964:Middlewares/Third_Party/FatFs/src/ff.c **** 		f_write(pb->fp, pb->buf, (UINT)i, &bw);
+5965:Middlewares/Third_Party/FatFs/src/ff.c **** 		i = (bw == (UINT)i) ? 0 : -1;
+5966:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+5967:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->idx = i;
+5968:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->nchr++;
+5969:Middlewares/Third_Party/FatFs/src/ff.c **** }
+5970:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5971:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5972:Middlewares/Third_Party/FatFs/src/ff.c **** static
+5973:Middlewares/Third_Party/FatFs/src/ff.c **** int putc_flush (		/* Flush left characters in the buffer */
+5974:Middlewares/Third_Party/FatFs/src/ff.c **** 	putbuff* pb
+5975:Middlewares/Third_Party/FatFs/src/ff.c **** )
+5976:Middlewares/Third_Party/FatFs/src/ff.c **** {
+5977:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT nw;
+5978:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5979:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (   pb->idx >= 0	/* Flush buffered characters to the file */
+5980:Middlewares/Third_Party/FatFs/src/ff.c **** 		&& f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
+5981:Middlewares/Third_Party/FatFs/src/ff.c **** 		&& (UINT)pb->idx == nw) return pb->nchr;
+5982:Middlewares/Third_Party/FatFs/src/ff.c **** 	return EOF;
+5983:Middlewares/Third_Party/FatFs/src/ff.c **** }
+5984:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5985:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5986:Middlewares/Third_Party/FatFs/src/ff.c **** static
+5987:Middlewares/Third_Party/FatFs/src/ff.c **** void putc_init (		/* Initialize write buffer */
+5988:Middlewares/Third_Party/FatFs/src/ff.c **** 	putbuff* pb,
+5989:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp
+5990:Middlewares/Third_Party/FatFs/src/ff.c **** )
+5991:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 1675              		.loc 1 5991 1 is_stmt 1 view -0
+ 1676              		.cfi_startproc
+ 1677              		@ args = 0, pretend = 0, frame = 0
+ 1678              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1679              		@ link register save eliminated.
+5992:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->fp = fp;
+ 1680              		.loc 1 5992 2 view .LVU509
+ 1681              		.loc 1 5992 9 is_stmt 0 view .LVU510
+ 1682 0000 0160     		str	r1, [r0]
+5993:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->nchr = pb->idx = 0;
+ 1683              		.loc 1 5993 2 is_stmt 1 view .LVU511
+ 1684              		.loc 1 5993 21 is_stmt 0 view .LVU512
+ 1685 0002 0023     		movs	r3, #0
+ 1686 0004 4360     		str	r3, [r0, #4]
+ 1687              		.loc 1 5993 11 view .LVU513
+ 1688 0006 8360     		str	r3, [r0, #8]
+5994:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ARM GAS  /tmp/cc5lWXRL.s 			page 138
+
+
+ 1689              		.loc 1 5994 1 view .LVU514
+ 1690 0008 7047     		bx	lr
+ 1691              		.cfi_endproc
+ 1692              	.LFE1241:
+ 1694              		.section	.text.validate,"ax",%progbits
+ 1695              		.align	1
+ 1696              		.syntax unified
+ 1697              		.thumb
+ 1698              		.thumb_func
+ 1699              		.fpu fpv5-d16
+ 1701              	validate:
+ 1702              	.LVL181:
+ 1703              	.LFB1220:
+3220:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_INVALID_OBJECT;
+ 1704              		.loc 1 3220 1 is_stmt 1 view -0
+ 1705              		.cfi_startproc
+ 1706              		@ args = 0, pretend = 0, frame = 0
+ 1707              		@ frame_needed = 0, uses_anonymous_args = 0
+3220:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_INVALID_OBJECT;
+ 1708              		.loc 1 3220 1 is_stmt 0 view .LVU516
+ 1709 0000 38B5     		push	{r3, r4, r5, lr}
+ 1710              	.LCFI14:
+ 1711              		.cfi_def_cfa_offset 16
+ 1712              		.cfi_offset 3, -16
+ 1713              		.cfi_offset 4, -12
+ 1714              		.cfi_offset 5, -8
+ 1715              		.cfi_offset 14, -4
+ 1716 0002 0D46     		mov	r5, r1
+3221:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1717              		.loc 1 3221 2 is_stmt 1 view .LVU517
+ 1718              	.LVL182:
+3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+ 1719              		.loc 1 3224 2 view .LVU518
+3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+ 1720              		.loc 1 3224 5 is_stmt 0 view .LVU519
+ 1721 0004 0446     		mov	r4, r0
+ 1722 0006 98B1     		cbz	r0, .L147
+3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+ 1723              		.loc 1 3224 16 discriminator 1 view .LVU520
+ 1724 0008 0368     		ldr	r3, [r0]
+3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+ 1725              		.loc 1 3224 10 discriminator 1 view .LVU521
+ 1726 000a 9BB1     		cbz	r3, .L148
+3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+ 1727              		.loc 1 3224 31 discriminator 2 view .LVU522
+ 1728 000c 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
+3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+ 1729              		.loc 1 3224 21 discriminator 2 view .LVU523
+ 1730 000e A2B1     		cbz	r2, .L149
+3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+ 1731              		.loc 1 3224 47 discriminator 3 view .LVU524
+ 1732 0010 8188     		ldrh	r1, [r0, #4]
+ 1733              	.LVL183:
+3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+ 1734              		.loc 1 3224 62 discriminator 3 view .LVU525
+ 1735 0012 DA88     		ldrh	r2, [r3, #6]
+3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT
+ARM GAS  /tmp/cc5lWXRL.s 			page 139
+
+
+ 1736              		.loc 1 3224 41 discriminator 3 view .LVU526
+ 1737 0014 9142     		cmp	r1, r2
+ 1738 0016 03D0     		beq	.L153
+3221:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1739              		.loc 1 3221 10 view .LVU527
+ 1740 0018 0920     		movs	r0, #9
+ 1741              	.LVL184:
+3241:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 1742              		.loc 1 3241 33 view .LVU528
+ 1743 001a 0024     		movs	r4, #0
+ 1744              	.LVL185:
+ 1745              	.L146:
+3241:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 1746              		.loc 1 3241 6 discriminator 4 view .LVU529
+ 1747 001c 2C60     		str	r4, [r5]
+3242:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 1748              		.loc 1 3242 2 is_stmt 1 discriminator 4 view .LVU530
+3243:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1749              		.loc 1 3243 1 is_stmt 0 discriminator 4 view .LVU531
+ 1750 001e 38BD     		pop	{r3, r4, r5, pc}
+ 1751              	.LVL186:
+ 1752              	.L153:
+3236:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+ 1753              		.loc 1 3236 3 is_stmt 1 view .LVU532
+3236:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+ 1754              		.loc 1 3236 9 is_stmt 0 view .LVU533
+ 1755 0020 5878     		ldrb	r0, [r3, #1]	@ zero_extendqisi2
+ 1756              	.LVL187:
+3236:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+ 1757              		.loc 1 3236 9 view .LVU534
+ 1758 0022 FFF7FEFF 		bl	disk_status
+ 1759              	.LVL188:
+3236:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+ 1760              		.loc 1 3236 6 view .LVU535
+ 1761 0026 10F00100 		ands	r0, r0, #1
+ 1762 002a 09D1     		bne	.L151
+3237:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 1763              		.loc 1 3237 4 is_stmt 1 view .LVU536
+ 1764              	.LVL189:
+3241:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 1765              		.loc 1 3241 2 view .LVU537
+3241:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 1766              		.loc 1 3241 33 is_stmt 0 view .LVU538
+ 1767 002c 2468     		ldr	r4, [r4]
+ 1768              	.LVL190:
+3241:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 1769              		.loc 1 3241 33 view .LVU539
+ 1770 002e F5E7     		b	.L146
+ 1771              	.LVL191:
+ 1772              	.L147:
+3221:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1773              		.loc 1 3221 10 view .LVU540
+ 1774 0030 0920     		movs	r0, #9
+ 1775              	.LVL192:
+3221:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1776              		.loc 1 3221 10 view .LVU541
+ 1777 0032 F3E7     		b	.L146
+ARM GAS  /tmp/cc5lWXRL.s 			page 140
+
+
+ 1778              	.LVL193:
+ 1779              	.L148:
+3241:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 1780              		.loc 1 3241 33 view .LVU542
+ 1781 0034 1C46     		mov	r4, r3
+3221:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1782              		.loc 1 3221 10 view .LVU543
+ 1783 0036 0920     		movs	r0, #9
+ 1784              	.LVL194:
+3221:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1785              		.loc 1 3221 10 view .LVU544
+ 1786 0038 F0E7     		b	.L146
+ 1787              	.LVL195:
+ 1788              	.L149:
+3221:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1789              		.loc 1 3221 10 view .LVU545
+ 1790 003a 0920     		movs	r0, #9
+ 1791              	.LVL196:
+3241:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 1792              		.loc 1 3241 33 view .LVU546
+ 1793 003c 0024     		movs	r4, #0
+ 1794              	.LVL197:
+3241:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 1795              		.loc 1 3241 33 view .LVU547
+ 1796 003e EDE7     		b	.L146
+ 1797              	.LVL198:
+ 1798              	.L151:
+3221:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1799              		.loc 1 3221 10 view .LVU548
+ 1800 0040 0920     		movs	r0, #9
+3241:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 1801              		.loc 1 3241 33 view .LVU549
+ 1802 0042 0024     		movs	r4, #0
+ 1803              	.LVL199:
+3241:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 1804              		.loc 1 3241 33 view .LVU550
+ 1805 0044 EAE7     		b	.L146
+ 1806              		.cfi_endproc
+ 1807              	.LFE1220:
+ 1809              		.section	.text.sync_window,"ax",%progbits
+ 1810              		.align	1
+ 1811              		.syntax unified
+ 1812              		.thumb
+ 1813              		.thumb_func
+ 1814              		.fpu fpv5-d16
+ 1816              	sync_window:
+ 1817              	.LVL200:
+ 1818              	.LFB1196:
+ 886:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD wsect;
+ 1819              		.loc 1 886 1 is_stmt 1 view -0
+ 1820              		.cfi_startproc
+ 1821              		@ args = 0, pretend = 0, frame = 0
+ 1822              		@ frame_needed = 0, uses_anonymous_args = 0
+ 886:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD wsect;
+ 1823              		.loc 1 886 1 is_stmt 0 view .LVU552
+ 1824 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 1825              	.LCFI15:
+ARM GAS  /tmp/cc5lWXRL.s 			page 141
+
+
+ 1826              		.cfi_def_cfa_offset 24
+ 1827              		.cfi_offset 4, -24
+ 1828              		.cfi_offset 5, -20
+ 1829              		.cfi_offset 6, -16
+ 1830              		.cfi_offset 7, -12
+ 1831              		.cfi_offset 8, -8
+ 1832              		.cfi_offset 14, -4
+ 887:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT nf;
+ 1833              		.loc 1 887 2 is_stmt 1 view .LVU553
+ 888:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_OK;
+ 1834              		.loc 1 888 2 view .LVU554
+ 889:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1835              		.loc 1 889 2 view .LVU555
+ 1836              	.LVL201:
+ 892:Middlewares/Third_Party/FatFs/src/ff.c **** 		wsect = fs->winsect;	/* Current sector number */
+ 1837              		.loc 1 892 2 view .LVU556
+ 892:Middlewares/Third_Party/FatFs/src/ff.c **** 		wsect = fs->winsect;	/* Current sector number */
+ 1838              		.loc 1 892 8 is_stmt 0 view .LVU557
+ 1839 0004 C578     		ldrb	r5, [r0, #3]	@ zero_extendqisi2
+ 892:Middlewares/Third_Party/FatFs/src/ff.c **** 		wsect = fs->winsect;	/* Current sector number */
+ 1840              		.loc 1 892 5 view .LVU558
+ 1841 0006 15B9     		cbnz	r5, .L160
+ 1842              	.LVL202:
+ 1843              	.L155:
+ 906:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 1844              		.loc 1 906 2 is_stmt 1 view .LVU559
+ 907:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 1845              		.loc 1 907 1 is_stmt 0 view .LVU560
+ 1846 0008 2846     		mov	r0, r5
+ 1847 000a BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 1848              	.LVL203:
+ 1849              	.L160:
+ 907:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 1850              		.loc 1 907 1 view .LVU561
+ 1851 000e 0446     		mov	r4, r0
+ 893:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) {
+ 1852              		.loc 1 893 3 is_stmt 1 view .LVU562
+ 893:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) {
+ 1853              		.loc 1 893 9 is_stmt 0 view .LVU563
+ 1854 0010 076B     		ldr	r7, [r0, #48]
+ 1855              	.LVL204:
+ 894:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_DISK_ERR;
+ 1856              		.loc 1 894 3 is_stmt 1 view .LVU564
+ 894:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_DISK_ERR;
+ 1857              		.loc 1 894 29 is_stmt 0 view .LVU565
+ 1858 0012 00F13408 		add	r8, r0, #52
+ 894:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_DISK_ERR;
+ 1859              		.loc 1 894 7 view .LVU566
+ 1860 0016 0123     		movs	r3, #1
+ 1861 0018 3A46     		mov	r2, r7
+ 1862 001a 4146     		mov	r1, r8
+ 1863 001c 4078     		ldrb	r0, [r0, #1]	@ zero_extendqisi2
+ 1864              	.LVL205:
+ 894:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_DISK_ERR;
+ 1865              		.loc 1 894 7 view .LVU567
+ 1866 001e FFF7FEFF 		bl	disk_write
+ 1867              	.LVL206:
+ARM GAS  /tmp/cc5lWXRL.s 			page 142
+
+
+ 894:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_DISK_ERR;
+ 1868              		.loc 1 894 6 view .LVU568
+ 1869 0022 0546     		mov	r5, r0
+ 1870 0024 A0B9     		cbnz	r0, .L158
+ 897:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (wsect - fs->fatbase < fs->fsize) {		/* Is it in the FAT area? */
+ 1871              		.loc 1 897 4 is_stmt 1 view .LVU569
+ 897:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (wsect - fs->fatbase < fs->fsize) {		/* Is it in the FAT area? */
+ 1872              		.loc 1 897 14 is_stmt 0 view .LVU570
+ 1873 0026 0023     		movs	r3, #0
+ 1874 0028 E370     		strb	r3, [r4, #3]
+ 898:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
+ 1875              		.loc 1 898 4 is_stmt 1 view .LVU571
+ 898:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
+ 1876              		.loc 1 898 18 is_stmt 0 view .LVU572
+ 1877 002a 636A     		ldr	r3, [r4, #36]
+ 898:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
+ 1878              		.loc 1 898 14 view .LVU573
+ 1879 002c FB1A     		subs	r3, r7, r3
+ 898:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
+ 1880              		.loc 1 898 32 view .LVU574
+ 1881 002e E269     		ldr	r2, [r4, #28]
+ 898:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
+ 1882              		.loc 1 898 7 view .LVU575
+ 1883 0030 9342     		cmp	r3, r2
+ 1884 0032 E9D2     		bcs	.L155
+ 899:Middlewares/Third_Party/FatFs/src/ff.c **** 					wsect += fs->fsize;
+ 1885              		.loc 1 899 5 is_stmt 1 view .LVU576
+ 899:Middlewares/Third_Party/FatFs/src/ff.c **** 					wsect += fs->fsize;
+ 1886              		.loc 1 899 17 is_stmt 0 view .LVU577
+ 1887 0034 A678     		ldrb	r6, [r4, #2]	@ zero_extendqisi2
+ 1888              	.LVL207:
+ 899:Middlewares/Third_Party/FatFs/src/ff.c **** 					wsect += fs->fsize;
+ 1889              		.loc 1 899 5 view .LVU578
+ 1890 0036 08E0     		b	.L156
+ 1891              	.L157:
+ 900:Middlewares/Third_Party/FatFs/src/ff.c **** 					disk_write(fs->drv, fs->win, wsect, 1);
+ 1892              		.loc 1 900 6 is_stmt 1 discriminator 3 view .LVU579
+ 900:Middlewares/Third_Party/FatFs/src/ff.c **** 					disk_write(fs->drv, fs->win, wsect, 1);
+ 1893              		.loc 1 900 17 is_stmt 0 discriminator 3 view .LVU580
+ 1894 0038 E369     		ldr	r3, [r4, #28]
+ 900:Middlewares/Third_Party/FatFs/src/ff.c **** 					disk_write(fs->drv, fs->win, wsect, 1);
+ 1895              		.loc 1 900 12 discriminator 3 view .LVU581
+ 1896 003a 1F44     		add	r7, r7, r3
+ 1897              	.LVL208:
+ 901:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 1898              		.loc 1 901 6 is_stmt 1 discriminator 3 view .LVU582
+ 1899 003c 0123     		movs	r3, #1
+ 1900 003e 3A46     		mov	r2, r7
+ 1901 0040 4146     		mov	r1, r8
+ 1902 0042 6078     		ldrb	r0, [r4, #1]	@ zero_extendqisi2
+ 1903 0044 FFF7FEFF 		bl	disk_write
+ 1904              	.LVL209:
+ 899:Middlewares/Third_Party/FatFs/src/ff.c **** 					wsect += fs->fsize;
+ 1905              		.loc 1 899 36 discriminator 3 view .LVU583
+ 899:Middlewares/Third_Party/FatFs/src/ff.c **** 					wsect += fs->fsize;
+ 1906              		.loc 1 899 38 is_stmt 0 discriminator 3 view .LVU584
+ 1907 0048 013E     		subs	r6, r6, #1
+ARM GAS  /tmp/cc5lWXRL.s 			page 143
+
+
+ 1908              	.LVL210:
+ 1909              	.L156:
+ 899:Middlewares/Third_Party/FatFs/src/ff.c **** 					wsect += fs->fsize;
+ 1910              		.loc 1 899 27 is_stmt 1 discriminator 1 view .LVU585
+ 899:Middlewares/Third_Party/FatFs/src/ff.c **** 					wsect += fs->fsize;
+ 1911              		.loc 1 899 5 is_stmt 0 discriminator 1 view .LVU586
+ 1912 004a 012E     		cmp	r6, #1
+ 1913 004c F4D8     		bhi	.L157
+ 899:Middlewares/Third_Party/FatFs/src/ff.c **** 					wsect += fs->fsize;
+ 1914              		.loc 1 899 5 discriminator 1 view .LVU587
+ 1915 004e DBE7     		b	.L155
+ 1916              	.LVL211:
+ 1917              	.L158:
+ 895:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 1918              		.loc 1 895 8 view .LVU588
+ 1919 0050 0125     		movs	r5, #1
+ 1920 0052 D9E7     		b	.L155
+ 1921              		.cfi_endproc
+ 1922              	.LFE1196:
+ 1924              		.section	.text.move_window,"ax",%progbits
+ 1925              		.align	1
+ 1926              		.syntax unified
+ 1927              		.thumb
+ 1928              		.thumb_func
+ 1929              		.fpu fpv5-d16
+ 1931              	move_window:
+ 1932              	.LVL212:
+ 1933              	.LFB1197:
+ 916:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_OK;
+ 1934              		.loc 1 916 1 is_stmt 1 view -0
+ 1935              		.cfi_startproc
+ 1936              		@ args = 0, pretend = 0, frame = 0
+ 1937              		@ frame_needed = 0, uses_anonymous_args = 0
+ 916:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_OK;
+ 1938              		.loc 1 916 1 is_stmt 0 view .LVU590
+ 1939 0000 70B5     		push	{r4, r5, r6, lr}
+ 1940              	.LCFI16:
+ 1941              		.cfi_def_cfa_offset 16
+ 1942              		.cfi_offset 4, -16
+ 1943              		.cfi_offset 5, -12
+ 1944              		.cfi_offset 6, -8
+ 1945              		.cfi_offset 14, -4
+ 917:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1946              		.loc 1 917 2 is_stmt 1 view .LVU591
+ 1947              	.LVL213:
+ 920:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 1948              		.loc 1 920 2 view .LVU592
+ 920:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 1949              		.loc 1 920 18 is_stmt 0 view .LVU593
+ 1950 0002 036B     		ldr	r3, [r0, #48]
+ 920:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 1951              		.loc 1 920 5 view .LVU594
+ 1952 0004 8B42     		cmp	r3, r1
+ 1953 0006 02D1     		bne	.L167
+ 917:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1954              		.loc 1 917 10 view .LVU595
+ 1955 0008 0026     		movs	r6, #0
+ARM GAS  /tmp/cc5lWXRL.s 			page 144
+
+
+ 1956              	.LVL214:
+ 1957              	.L162:
+ 932:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 1958              		.loc 1 932 2 is_stmt 1 view .LVU596
+ 933:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1959              		.loc 1 933 1 is_stmt 0 view .LVU597
+ 1960 000a 3046     		mov	r0, r6
+ 1961 000c 70BD     		pop	{r4, r5, r6, pc}
+ 1962              	.LVL215:
+ 1963              	.L167:
+ 933:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 1964              		.loc 1 933 1 view .LVU598
+ 1965 000e 0446     		mov	r4, r0
+ 1966 0010 0D46     		mov	r5, r1
+ 922:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 1967              		.loc 1 922 3 is_stmt 1 view .LVU599
+ 922:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 1968              		.loc 1 922 9 is_stmt 0 view .LVU600
+ 1969 0012 FFF7FEFF 		bl	sync_window
+ 1970              	.LVL216:
+ 924:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) {
+ 1971              		.loc 1 924 3 is_stmt 1 view .LVU601
+ 924:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) {
+ 1972              		.loc 1 924 6 is_stmt 0 view .LVU602
+ 1973 0016 0646     		mov	r6, r0
+ 1974 0018 0028     		cmp	r0, #0
+ 1975 001a F6D1     		bne	.L162
+ 925:Middlewares/Third_Party/FatFs/src/ff.c **** 				sector = 0xFFFFFFFF;	/* Invalidate window if data is not reliable */
+ 1976              		.loc 1 925 4 is_stmt 1 view .LVU603
+ 925:Middlewares/Third_Party/FatFs/src/ff.c **** 				sector = 0xFFFFFFFF;	/* Invalidate window if data is not reliable */
+ 1977              		.loc 1 925 8 is_stmt 0 view .LVU604
+ 1978 001c 0123     		movs	r3, #1
+ 1979 001e 2A46     		mov	r2, r5
+ 1980 0020 04F13401 		add	r1, r4, #52
+ 1981 0024 6078     		ldrb	r0, [r4, #1]	@ zero_extendqisi2
+ 1982              	.LVL217:
+ 925:Middlewares/Third_Party/FatFs/src/ff.c **** 				sector = 0xFFFFFFFF;	/* Invalidate window if data is not reliable */
+ 1983              		.loc 1 925 8 view .LVU605
+ 1984 0026 FFF7FEFF 		bl	disk_read
+ 1985              	.LVL218:
+ 925:Middlewares/Third_Party/FatFs/src/ff.c **** 				sector = 0xFFFFFFFF;	/* Invalidate window if data is not reliable */
+ 1986              		.loc 1 925 7 view .LVU606
+ 1987 002a 10B1     		cbz	r0, .L163
+ 927:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 1988              		.loc 1 927 9 view .LVU607
+ 1989 002c 0126     		movs	r6, #1
+ 926:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_DISK_ERR;
+ 1990              		.loc 1 926 12 view .LVU608
+ 1991 002e 4FF0FF35 		mov	r5, #-1
+ 1992              	.LVL219:
+ 1993              	.L163:
+ 929:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 1994              		.loc 1 929 4 is_stmt 1 view .LVU609
+ 929:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 1995              		.loc 1 929 16 is_stmt 0 view .LVU610
+ 1996 0032 2563     		str	r5, [r4, #48]
+ 1997 0034 E9E7     		b	.L162
+ARM GAS  /tmp/cc5lWXRL.s 			page 145
+
+
+ 1998              		.cfi_endproc
+ 1999              	.LFE1197:
+ 2001              		.section	.text.check_fs,"ax",%progbits
+ 2002              		.align	1
+ 2003              		.syntax unified
+ 2004              		.thumb
+ 2005              		.thumb_func
+ 2006              		.fpu fpv5-d16
+ 2008              	check_fs:
+ 2009              	.LVL220:
+ 2010              	.LFB1218:
+2969:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->wflag = 0; fs->winsect = 0xFFFFFFFF;		/* Invaidate window */
+ 2011              		.loc 1 2969 1 is_stmt 1 view -0
+ 2012              		.cfi_startproc
+ 2013              		@ args = 0, pretend = 0, frame = 0
+ 2014              		@ frame_needed = 0, uses_anonymous_args = 0
+2969:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->wflag = 0; fs->winsect = 0xFFFFFFFF;		/* Invaidate window */
+ 2015              		.loc 1 2969 1 is_stmt 0 view .LVU612
+ 2016 0000 38B5     		push	{r3, r4, r5, lr}
+ 2017              	.LCFI17:
+ 2018              		.cfi_def_cfa_offset 16
+ 2019              		.cfi_offset 3, -16
+ 2020              		.cfi_offset 4, -12
+ 2021              		.cfi_offset 5, -8
+ 2022              		.cfi_offset 14, -4
+ 2023 0002 0446     		mov	r4, r0
+2970:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (move_window(fs, sect) != FR_OK) return 4;	/* Load boot record */
+ 2024              		.loc 1 2970 2 is_stmt 1 view .LVU613
+2970:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (move_window(fs, sect) != FR_OK) return 4;	/* Load boot record */
+ 2025              		.loc 1 2970 12 is_stmt 0 view .LVU614
+ 2026 0004 0023     		movs	r3, #0
+ 2027 0006 C370     		strb	r3, [r0, #3]
+2970:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (move_window(fs, sect) != FR_OK) return 4;	/* Load boot record */
+ 2028              		.loc 1 2970 17 is_stmt 1 view .LVU615
+2970:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (move_window(fs, sect) != FR_OK) return 4;	/* Load boot record */
+ 2029              		.loc 1 2970 29 is_stmt 0 view .LVU616
+ 2030 0008 4FF0FF33 		mov	r3, #-1
+ 2031 000c 0363     		str	r3, [r0, #48]
+2971:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2032              		.loc 1 2971 2 is_stmt 1 view .LVU617
+2971:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2033              		.loc 1 2971 6 is_stmt 0 view .LVU618
+ 2034 000e FFF7FEFF 		bl	move_window
+ 2035              	.LVL221:
+2971:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2036              		.loc 1 2971 5 view .LVU619
+ 2037 0012 30BB     		cbnz	r0, .L171
+ 2038 0014 0546     		mov	r5, r0
+2973:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2039              		.loc 1 2973 2 is_stmt 1 view .LVU620
+2973:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2040              		.loc 1 2973 6 is_stmt 0 view .LVU621
+ 2041 0016 04F23220 		addw	r0, r4, #562
+ 2042 001a FFF7FEFF 		bl	ld_word
+ 2043              	.LVL222:
+2973:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2044              		.loc 1 2973 5 view .LVU622
+ARM GAS  /tmp/cc5lWXRL.s 			page 146
+
+
+ 2045 001e 4AF65523 		movw	r3, #43605
+ 2046 0022 9842     		cmp	r0, r3
+ 2047 0024 1FD1     		bne	.L172
+2975:Middlewares/Third_Party/FatFs/src/ff.c **** 		if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0;	/* Check "FAT" string *
+ 2048              		.loc 1 2975 2 is_stmt 1 view .LVU623
+2975:Middlewares/Third_Party/FatFs/src/ff.c **** 		if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0;	/* Check "FAT" string *
+ 2049              		.loc 1 2975 13 is_stmt 0 view .LVU624
+ 2050 0026 94F83430 		ldrb	r3, [r4, #52]	@ zero_extendqisi2
+2975:Middlewares/Third_Party/FatFs/src/ff.c **** 		if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0;	/* Check "FAT" string *
+ 2051              		.loc 1 2975 5 view .LVU625
+ 2052 002a E92B     		cmp	r3, #233
+ 2053 002c 07D0     		beq	.L170
+2975:Middlewares/Third_Party/FatFs/src/ff.c **** 		if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0;	/* Check "FAT" string *
+ 2054              		.loc 1 2975 66 discriminator 1 view .LVU626
+ 2055 002e 636B     		ldr	r3, [r4, #52]
+ 2056 0030 03F0FF13 		and	r3, r3, #16711935
+2975:Middlewares/Third_Party/FatFs/src/ff.c **** 		if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0;	/* Check "FAT" string *
+ 2057              		.loc 1 2975 34 discriminator 1 view .LVU627
+ 2058 0034 0D4A     		ldr	r2, .L175
+ 2059 0036 9342     		cmp	r3, r2
+ 2060 0038 01D0     		beq	.L170
+2982:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 2061              		.loc 1 2982 9 view .LVU628
+ 2062 003a 0225     		movs	r5, #2
+ 2063 003c 14E0     		b	.L169
+ 2064              	.L170:
+2976:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0;			/* Check "FAT3" string */
+ 2065              		.loc 1 2976 3 is_stmt 1 view .LVU629
+2976:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0;			/* Check "FAT3" string */
+ 2066              		.loc 1 2976 8 is_stmt 0 view .LVU630
+ 2067 003e 04F16A00 		add	r0, r4, #106
+ 2068 0042 FFF7FEFF 		bl	ld_dword
+ 2069              	.LVL223:
+2976:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0;			/* Check "FAT3" string */
+ 2070              		.loc 1 2976 42 view .LVU631
+ 2071 0046 20F07F40 		bic	r0, r0, #-16777216
+2976:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0;			/* Check "FAT3" string */
+ 2072              		.loc 1 2976 6 view .LVU632
+ 2073 004a 094B     		ldr	r3, .L175+4
+ 2074 004c 9842     		cmp	r0, r3
+ 2075 004e 0BD0     		beq	.L169
+2977:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 2076              		.loc 1 2977 3 is_stmt 1 view .LVU633
+2977:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 2077              		.loc 1 2977 7 is_stmt 0 view .LVU634
+ 2078 0050 04F18600 		add	r0, r4, #134
+ 2079 0054 FFF7FEFF 		bl	ld_dword
+ 2080              	.LVL224:
+2977:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 2081              		.loc 1 2977 6 view .LVU635
+ 2082 0058 064B     		ldr	r3, .L175+8
+ 2083 005a 9842     		cmp	r0, r3
+ 2084 005c 04D0     		beq	.L169
+2982:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 2085              		.loc 1 2982 9 view .LVU636
+ 2086 005e 0225     		movs	r5, #2
+ 2087 0060 02E0     		b	.L169
+ARM GAS  /tmp/cc5lWXRL.s 			page 147
+
+
+ 2088              	.L171:
+2971:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2089              		.loc 1 2971 45 view .LVU637
+ 2090 0062 0425     		movs	r5, #4
+ 2091 0064 00E0     		b	.L169
+ 2092              	.L172:
+2973:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2093              		.loc 1 2973 51 view .LVU638
+ 2094 0066 0325     		movs	r5, #3
+ 2095              	.L169:
+2983:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2096              		.loc 1 2983 1 view .LVU639
+ 2097 0068 2846     		mov	r0, r5
+ 2098 006a 38BD     		pop	{r3, r4, r5, pc}
+ 2099              	.LVL225:
+ 2100              	.L176:
+2983:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2101              		.loc 1 2983 1 view .LVU640
+ 2102              		.align	2
+ 2103              	.L175:
+ 2104 006c EB009000 		.word	9437419
+ 2105 0070 46415400 		.word	5521734
+ 2106 0074 46415433 		.word	861159750
+ 2107              		.cfi_endproc
+ 2108              	.LFE1218:
+ 2110              		.section	.text.find_volume,"ax",%progbits
+ 2111              		.align	1
+ 2112              		.syntax unified
+ 2113              		.thumb
+ 2114              		.thumb_func
+ 2115              		.fpu fpv5-d16
+ 2117              	find_volume:
+ 2118              	.LVL226:
+ 2119              	.LFB1219:
+2998:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE fmt, *pt;
+ 2120              		.loc 1 2998 1 is_stmt 1 view -0
+ 2121              		.cfi_startproc
+ 2122              		@ args = 0, pretend = 0, frame = 24
+ 2123              		@ frame_needed = 0, uses_anonymous_args = 0
+2998:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE fmt, *pt;
+ 2124              		.loc 1 2998 1 is_stmt 0 view .LVU642
+ 2125 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 2126              	.LCFI18:
+ 2127              		.cfi_def_cfa_offset 36
+ 2128              		.cfi_offset 4, -36
+ 2129              		.cfi_offset 5, -32
+ 2130              		.cfi_offset 6, -28
+ 2131              		.cfi_offset 7, -24
+ 2132              		.cfi_offset 8, -20
+ 2133              		.cfi_offset 9, -16
+ 2134              		.cfi_offset 10, -12
+ 2135              		.cfi_offset 11, -8
+ 2136              		.cfi_offset 14, -4
+ 2137 0004 87B0     		sub	sp, sp, #28
+ 2138              	.LCFI19:
+ 2139              		.cfi_def_cfa_offset 64
+ 2140 0006 0D46     		mov	r5, r1
+ARM GAS  /tmp/cc5lWXRL.s 			page 148
+
+
+ 2141 0008 1646     		mov	r6, r2
+2999:Middlewares/Third_Party/FatFs/src/ff.c **** 	int vol;
+ 2142              		.loc 1 2999 2 is_stmt 1 view .LVU643
+3000:Middlewares/Third_Party/FatFs/src/ff.c **** 	DSTATUS stat;
+ 2143              		.loc 1 3000 2 view .LVU644
+3001:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4];
+ 2144              		.loc 1 3001 2 view .LVU645
+3002:Middlewares/Third_Party/FatFs/src/ff.c **** 	WORD nrsv;
+ 2145              		.loc 1 3002 2 view .LVU646
+3003:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 2146              		.loc 1 3003 2 view .LVU647
+3004:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+ 2147              		.loc 1 3004 2 view .LVU648
+3005:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2148              		.loc 1 3005 2 view .LVU649
+3009:Middlewares/Third_Party/FatFs/src/ff.c **** 	vol = get_ldnumber(path);
+ 2149              		.loc 1 3009 2 view .LVU650
+3009:Middlewares/Third_Party/FatFs/src/ff.c **** 	vol = get_ldnumber(path);
+ 2150              		.loc 1 3009 7 is_stmt 0 view .LVU651
+ 2151 000a 0023     		movs	r3, #0
+ 2152 000c 0B60     		str	r3, [r1]
+3010:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+ 2153              		.loc 1 3010 2 is_stmt 1 view .LVU652
+3010:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+ 2154              		.loc 1 3010 8 is_stmt 0 view .LVU653
+ 2155 000e FFF7FEFF 		bl	get_ldnumber
+ 2156              	.LVL227:
+3011:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2157              		.loc 1 3011 2 is_stmt 1 view .LVU654
+3011:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2158              		.loc 1 3011 5 is_stmt 0 view .LVU655
+ 2159 0012 071E     		subs	r7, r0, #0
+ 2160 0014 C0F26681 		blt	.L195
+3014:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!fs) return FR_NOT_ENABLED;		/* Is the file system object available? */
+ 2161              		.loc 1 3014 2 is_stmt 1 view .LVU656
+3014:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!fs) return FR_NOT_ENABLED;		/* Is the file system object available? */
+ 2162              		.loc 1 3014 5 is_stmt 0 view .LVU657
+ 2163 0018 BF4B     		ldr	r3, .L229
+ 2164 001a 53F82740 		ldr	r4, [r3, r7, lsl #2]
+ 2165              	.LVL228:
+3015:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2166              		.loc 1 3015 2 is_stmt 1 view .LVU658
+3015:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2167              		.loc 1 3015 5 is_stmt 0 view .LVU659
+ 2168 001e 002C     		cmp	r4, #0
+ 2169 0020 00F06581 		beq	.L196
+3017:Middlewares/Third_Party/FatFs/src/ff.c **** 	*rfs = fs;							/* Return pointer to the file system object */
+ 2170              		.loc 1 3017 14 is_stmt 1 view .LVU660
+3018:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2171              		.loc 1 3018 2 view .LVU661
+3018:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2172              		.loc 1 3018 7 is_stmt 0 view .LVU662
+ 2173 0024 2C60     		str	r4, [r5]
+3020:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type) {					/* If the volume has been mounted */
+ 2174              		.loc 1 3020 2 is_stmt 1 view .LVU663
+3020:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fs->fs_type) {					/* If the volume has been mounted */
+ 2175              		.loc 1 3020 7 is_stmt 0 view .LVU664
+ARM GAS  /tmp/cc5lWXRL.s 			page 149
+
+
+ 2176 0026 06F0FE06 		and	r6, r6, #254
+ 2177              	.LVL229:
+3021:Middlewares/Third_Party/FatFs/src/ff.c **** 		stat = disk_status(fs->drv);
+ 2178              		.loc 1 3021 2 is_stmt 1 view .LVU665
+3021:Middlewares/Third_Party/FatFs/src/ff.c **** 		stat = disk_status(fs->drv);
+ 2179              		.loc 1 3021 8 is_stmt 0 view .LVU666
+ 2180 002a 2378     		ldrb	r3, [r4]	@ zero_extendqisi2
+3021:Middlewares/Third_Party/FatFs/src/ff.c **** 		stat = disk_status(fs->drv);
+ 2181              		.loc 1 3021 5 view .LVU667
+ 2182 002c 73B1     		cbz	r3, .L179
+3022:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
+ 2183              		.loc 1 3022 3 is_stmt 1 view .LVU668
+3022:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
+ 2184              		.loc 1 3022 10 is_stmt 0 view .LVU669
+ 2185 002e 6078     		ldrb	r0, [r4, #1]	@ zero_extendqisi2
+ 2186              	.LVL230:
+3022:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
+ 2187              		.loc 1 3022 10 view .LVU670
+ 2188 0030 FFF7FEFF 		bl	disk_status
+ 2189              	.LVL231:
+3023:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
+ 2190              		.loc 1 3023 3 is_stmt 1 view .LVU671
+3023:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
+ 2191              		.loc 1 3023 6 is_stmt 0 view .LVU672
+ 2192 0034 10F00105 		ands	r5, r0, #1
+ 2193              	.LVL232:
+3023:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
+ 2194              		.loc 1 3023 6 view .LVU673
+ 2195 0038 08D1     		bne	.L179
+3024:Middlewares/Third_Party/FatFs/src/ff.c **** 				return FR_WRITE_PROTECTED;
+ 2196              		.loc 1 3024 4 is_stmt 1 view .LVU674
+3024:Middlewares/Third_Party/FatFs/src/ff.c **** 				return FR_WRITE_PROTECTED;
+ 2197              		.loc 1 3024 7 is_stmt 0 view .LVU675
+ 2198 003a 002E     		cmp	r6, #0
+ 2199 003c 00F05381 		beq	.L178
+3024:Middlewares/Third_Party/FatFs/src/ff.c **** 				return FR_WRITE_PROTECTED;
+ 2200              		.loc 1 3024 30 discriminator 1 view .LVU676
+ 2201 0040 10F0040F 		tst	r0, #4
+ 2202 0044 00F04F81 		beq	.L178
+3025:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 2203              		.loc 1 3025 12 view .LVU677
+ 2204 0048 0A25     		movs	r5, #10
+ 2205 004a 4CE1     		b	.L178
+ 2206              	.LVL233:
+ 2207              	.L179:
+3034:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->drv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
+ 2208              		.loc 1 3034 2 is_stmt 1 view .LVU678
+3034:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->drv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
+ 2209              		.loc 1 3034 14 is_stmt 0 view .LVU679
+ 2210 004c 0023     		movs	r3, #0
+ 2211 004e 2370     		strb	r3, [r4]
+3035:Middlewares/Third_Party/FatFs/src/ff.c **** 	stat = disk_initialize(fs->drv);	/* Initialize the physical drive */
+ 2212              		.loc 1 3035 2 is_stmt 1 view .LVU680
+3035:Middlewares/Third_Party/FatFs/src/ff.c **** 	stat = disk_initialize(fs->drv);	/* Initialize the physical drive */
+ 2213              		.loc 1 3035 12 is_stmt 0 view .LVU681
+ 2214 0050 F8B2     		uxtb	r0, r7
+3035:Middlewares/Third_Party/FatFs/src/ff.c **** 	stat = disk_initialize(fs->drv);	/* Initialize the physical drive */
+ARM GAS  /tmp/cc5lWXRL.s 			page 150
+
+
+ 2215              		.loc 1 3035 10 view .LVU682
+ 2216 0052 6070     		strb	r0, [r4, #1]
+3036:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_NOINIT) { 			/* Check if the initialization succeeded */
+ 2217              		.loc 1 3036 2 is_stmt 1 view .LVU683
+3036:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_NOINIT) { 			/* Check if the initialization succeeded */
+ 2218              		.loc 1 3036 9 is_stmt 0 view .LVU684
+ 2219 0054 FFF7FEFF 		bl	disk_initialize
+ 2220              	.LVL234:
+3037:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
+ 2221              		.loc 1 3037 2 is_stmt 1 view .LVU685
+3037:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
+ 2222              		.loc 1 3037 5 is_stmt 0 view .LVU686
+ 2223 0058 10F0010F 		tst	r0, #1
+ 2224 005c 40F04981 		bne	.L198
+3040:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_WRITE_PROTECTED;
+ 2225              		.loc 1 3040 2 is_stmt 1 view .LVU687
+3040:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_WRITE_PROTECTED;
+ 2226              		.loc 1 3040 5 is_stmt 0 view .LVU688
+ 2227 0060 1EB1     		cbz	r6, .L180
+3040:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_WRITE_PROTECTED;
+ 2228              		.loc 1 3040 28 discriminator 1 view .LVU689
+ 2229 0062 10F0040F 		tst	r0, #4
+ 2230 0066 40F04681 		bne	.L199
+ 2231              	.L180:
+3044:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+ 2232              		.loc 1 3044 2 is_stmt 1 view .LVU690
+3044:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+ 2233              		.loc 1 3044 6 is_stmt 0 view .LVU691
+ 2234 006a 04F10C02 		add	r2, r4, #12
+ 2235 006e 0221     		movs	r1, #2
+ 2236 0070 6078     		ldrb	r0, [r4, #1]	@ zero_extendqisi2
+ 2237              	.LVL235:
+3044:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+ 2238              		.loc 1 3044 6 view .LVU692
+ 2239 0072 FFF7FEFF 		bl	disk_ioctl
+ 2240              	.LVL236:
+3044:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+ 2241              		.loc 1 3044 5 view .LVU693
+ 2242 0076 0546     		mov	r5, r0
+ 2243 0078 0028     		cmp	r0, #0
+ 2244 007a 40F03E81 		bne	.L200
+3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2245              		.loc 1 3045 2 is_stmt 1 view .LVU694
+3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2246              		.loc 1 3045 6 is_stmt 0 view .LVU695
+ 2247 007e A289     		ldrh	r2, [r4, #12]
+3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2248              		.loc 1 3045 23 view .LVU696
+ 2249 0080 A2F50073 		sub	r3, r2, #512
+ 2250 0084 9BB2     		uxth	r3, r3
+3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2251              		.loc 1 3045 5 view .LVU697
+ 2252 0086 B3F5606F 		cmp	r3, #3584
+ 2253 008a 00F23881 		bhi	.L201
+3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2254              		.loc 1 3045 64 discriminator 2 view .LVU698
+ 2255 008e 531E     		subs	r3, r2, #1
+ARM GAS  /tmp/cc5lWXRL.s 			page 151
+
+
+3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2256              		.loc 1 3045 43 discriminator 2 view .LVU699
+ 2257 0090 1A42     		tst	r2, r3
+ 2258 0092 01D0     		beq	.L223
+3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2259              		.loc 1 3045 78 view .LVU700
+ 2260 0094 0125     		movs	r5, #1
+ 2261 0096 26E1     		b	.L178
+ 2262              	.L223:
+3049:Middlewares/Third_Party/FatFs/src/ff.c **** 	fmt = check_fs(fs, bsect);			/* Load sector 0 and check if it is an FAT-VBR as SFD */
+ 2263              		.loc 1 3049 2 is_stmt 1 view .LVU701
+ 2264              	.LVL237:
+3050:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) {	/* Not an FAT-VBR or forced partition number */
+ 2265              		.loc 1 3050 2 view .LVU702
+3050:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) {	/* Not an FAT-VBR or forced partition number */
+ 2266              		.loc 1 3050 8 is_stmt 0 view .LVU703
+ 2267 0098 0021     		movs	r1, #0
+ 2268 009a 2046     		mov	r0, r4
+ 2269 009c FFF7FEFF 		bl	check_fs
+ 2270              	.LVL238:
+3051:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < 4; i++) {		/* Get partition offset */
+ 2271              		.loc 1 3051 2 is_stmt 1 view .LVU704
+3051:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < 4; i++) {		/* Get partition offset */
+ 2272              		.loc 1 3051 5 is_stmt 0 view .LVU705
+ 2273 00a0 0228     		cmp	r0, #2
+ 2274 00a2 00F0C180 		beq	.L203
+3049:Middlewares/Third_Party/FatFs/src/ff.c **** 	fmt = check_fs(fs, bsect);			/* Load sector 0 and check if it is an FAT-VBR as SFD */
+ 2275              		.loc 1 3049 8 view .LVU706
+ 2276 00a6 0026     		movs	r6, #0
+ 2277              	.LVL239:
+ 2278              	.L182:
+3063:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fmt >= 2) return FR_NO_FILESYSTEM;	/* No FAT volume is found */
+ 2279              		.loc 1 3063 2 is_stmt 1 view .LVU707
+3063:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fmt >= 2) return FR_NO_FILESYSTEM;	/* No FAT volume is found */
+ 2280              		.loc 1 3063 5 is_stmt 0 view .LVU708
+ 2281 00a8 0428     		cmp	r0, #4
+ 2282 00aa 00F02A81 		beq	.L206
+3064:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2283              		.loc 1 3064 2 is_stmt 1 view .LVU709
+3064:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2284              		.loc 1 3064 5 is_stmt 0 view .LVU710
+ 2285 00ae 0128     		cmp	r0, #1
+ 2286 00b0 00F22981 		bhi	.L207
+3116:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2287              		.loc 1 3116 3 is_stmt 1 view .LVU711
+3116:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2288              		.loc 1 3116 7 is_stmt 0 view .LVU712
+ 2289 00b4 04F13F00 		add	r0, r4, #63
+ 2290              	.LVL240:
+3116:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2291              		.loc 1 3116 7 view .LVU713
+ 2292 00b8 FFF7FEFF 		bl	ld_word
+ 2293              	.LVL241:
+3116:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2294              		.loc 1 3116 44 view .LVU714
+ 2295 00bc B4F80C80 		ldrh	r8, [r4, #12]
+3116:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ARM GAS  /tmp/cc5lWXRL.s 			page 152
+
+
+ 2296              		.loc 1 3116 6 view .LVU715
+ 2297 00c0 4045     		cmp	r0, r8
+ 2298 00c2 40F02281 		bne	.L208
+3118:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
+ 2299              		.loc 1 3118 3 is_stmt 1 view .LVU716
+3118:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
+ 2300              		.loc 1 3118 12 is_stmt 0 view .LVU717
+ 2301 00c6 04F14A00 		add	r0, r4, #74
+ 2302 00ca FFF7FEFF 		bl	ld_word
+ 2303              	.LVL242:
+3118:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
+ 2304              		.loc 1 3118 10 view .LVU718
+ 2305 00ce 0746     		mov	r7, r0
+ 2306              	.LVL243:
+3119:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsize = fasize;
+ 2307              		.loc 1 3119 3 is_stmt 1 view .LVU719
+3119:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsize = fasize;
+ 2308              		.loc 1 3119 6 is_stmt 0 view .LVU720
+ 2309 00d0 20B9     		cbnz	r0, .L187
+3119:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsize = fasize;
+ 2310              		.loc 1 3119 20 is_stmt 1 discriminator 1 view .LVU721
+3119:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsize = fasize;
+ 2311              		.loc 1 3119 29 is_stmt 0 discriminator 1 view .LVU722
+ 2312 00d2 04F15800 		add	r0, r4, #88
+ 2313              	.LVL244:
+3119:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsize = fasize;
+ 2314              		.loc 1 3119 29 discriminator 1 view .LVU723
+ 2315 00d6 FFF7FEFF 		bl	ld_dword
+ 2316              	.LVL245:
+ 2317 00da 0746     		mov	r7, r0
+ 2318              	.LVL246:
+ 2319              	.L187:
+3120:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2320              		.loc 1 3120 3 is_stmt 1 view .LVU724
+3120:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2321              		.loc 1 3120 13 is_stmt 0 view .LVU725
+ 2322 00dc E761     		str	r7, [r4, #28]
+3122:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM;	/* (Must be 1 or 2) */
+ 2323              		.loc 1 3122 3 is_stmt 1 view .LVU726
+3122:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM;	/* (Must be 1 or 2) */
+ 2324              		.loc 1 3122 23 is_stmt 0 view .LVU727
+ 2325 00de 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+3122:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM;	/* (Must be 1 or 2) */
+ 2326              		.loc 1 3122 14 view .LVU728
+ 2327 00e2 A270     		strb	r2, [r4, #2]
+3123:Middlewares/Third_Party/FatFs/src/ff.c **** 		fasize *= fs->n_fats;							/* Number of sectors for FAT area */
+ 2328              		.loc 1 3123 3 is_stmt 1 view .LVU729
+3123:Middlewares/Third_Party/FatFs/src/ff.c **** 		fasize *= fs->n_fats;							/* Number of sectors for FAT area */
+ 2329              		.loc 1 3123 23 is_stmt 0 view .LVU730
+ 2330 00e4 531E     		subs	r3, r2, #1
+ 2331 00e6 DBB2     		uxtb	r3, r3
+3123:Middlewares/Third_Party/FatFs/src/ff.c **** 		fasize *= fs->n_fats;							/* Number of sectors for FAT area */
+ 2332              		.loc 1 3123 6 view .LVU731
+ 2333 00e8 012B     		cmp	r3, #1
+ 2334 00ea 00F21081 		bhi	.L209
+3124:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2335              		.loc 1 3124 3 is_stmt 1 view .LVU732
+ARM GAS  /tmp/cc5lWXRL.s 			page 153
+
+
+3124:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2336              		.loc 1 3124 10 is_stmt 0 view .LVU733
+ 2337 00ee 07FB02F3 		mul	r3, r7, r2
+ 2338 00f2 0093     		str	r3, [sp]
+ 2339              	.LVL247:
+3126:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM;	/* (Must be power o
+ 2340              		.loc 1 3126 3 is_stmt 1 view .LVU734
+3126:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM;	/* (Must be power o
+ 2341              		.loc 1 3126 22 is_stmt 0 view .LVU735
+ 2342 00f4 94F84190 		ldrb	r9, [r4, #65]	@ zero_extendqisi2
+3126:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM;	/* (Must be power o
+ 2343              		.loc 1 3126 13 view .LVU736
+ 2344 00f8 A4F80A90 		strh	r9, [r4, #10]	@ movhi
+3127:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2345              		.loc 1 3127 3 is_stmt 1 view .LVU737
+3127:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2346              		.loc 1 3127 6 is_stmt 0 view .LVU738
+ 2347 00fc B9F1000F 		cmp	r9, #0
+ 2348 0100 00F00781 		beq	.L210
+3127:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2349              		.loc 1 3127 49 discriminator 2 view .LVU739
+ 2350 0104 09F1FF33 		add	r3, r9, #-1
+ 2351              	.LVL248:
+3127:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2352              		.loc 1 3127 22 discriminator 2 view .LVU740
+ 2353 0108 19EA030F 		tst	r9, r3
+ 2354 010c 40F00C81 		bne	.L211
+3129:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM;	/* (Must be sector aligned) */
+ 2355              		.loc 1 3129 3 is_stmt 1 view .LVU741
+3129:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM;	/* (Must be sector aligned) */
+ 2356              		.loc 1 3129 19 is_stmt 0 view .LVU742
+ 2357 0110 04F14500 		add	r0, r4, #69
+ 2358 0114 FFF7FEFF 		bl	ld_word
+ 2359              	.LVL249:
+ 2360 0118 8246     		mov	r10, r0
+3129:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM;	/* (Must be sector aligned) */
+ 2361              		.loc 1 3129 17 view .LVU743
+ 2362 011a 2081     		strh	r0, [r4, #8]	@ movhi
+3130:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2363              		.loc 1 3130 3 is_stmt 1 view .LVU744
+3130:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2364              		.loc 1 3130 7 is_stmt 0 view .LVU745
+ 2365 011c 4FEA581B 		lsr	fp, r8, #5
+ 2366 0120 B0FBFBF3 		udiv	r3, r0, fp
+ 2367 0124 0BFB1303 		mls	r3, fp, r3, r0
+ 2368 0128 9BB2     		uxth	r3, r3
+3130:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2369              		.loc 1 3130 6 view .LVU746
+ 2370 012a 002B     		cmp	r3, #0
+ 2371 012c 40F0FE80 		bne	.L212
+3132:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
+ 2372              		.loc 1 3132 3 is_stmt 1 view .LVU747
+3132:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
+ 2373              		.loc 1 3132 11 is_stmt 0 view .LVU748
+ 2374 0130 04F14700 		add	r0, r4, #71
+ 2375 0134 FFF7FEFF 		bl	ld_word
+ 2376              	.LVL250:
+ARM GAS  /tmp/cc5lWXRL.s 			page 154
+
+
+3132:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
+ 2377              		.loc 1 3132 9 view .LVU749
+ 2378 0138 0190     		str	r0, [sp, #4]
+ 2379              	.LVL251:
+3133:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2380              		.loc 1 3133 3 is_stmt 1 view .LVU750
+3133:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2381              		.loc 1 3133 6 is_stmt 0 view .LVU751
+ 2382 013a 20B9     		cbnz	r0, .L188
+3133:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2383              		.loc 1 3133 19 is_stmt 1 discriminator 1 view .LVU752
+3133:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2384              		.loc 1 3133 27 is_stmt 0 discriminator 1 view .LVU753
+ 2385 013c 04F15400 		add	r0, r4, #84
+ 2386              	.LVL252:
+3133:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2387              		.loc 1 3133 27 discriminator 1 view .LVU754
+ 2388 0140 FFF7FEFF 		bl	ld_dword
+ 2389              	.LVL253:
+ 2390 0144 0190     		str	r0, [sp, #4]
+ 2391              	.LVL254:
+ 2392              	.L188:
+3135:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nrsv == 0) return FR_NO_FILESYSTEM;			/* (Must not be 0) */
+ 2393              		.loc 1 3135 3 is_stmt 1 view .LVU755
+3135:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nrsv == 0) return FR_NO_FILESYSTEM;			/* (Must not be 0) */
+ 2394              		.loc 1 3135 10 is_stmt 0 view .LVU756
+ 2395 0146 04F14200 		add	r0, r4, #66
+ 2396 014a FFF7FEFF 		bl	ld_word
+ 2397              	.LVL255:
+3136:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2398              		.loc 1 3136 3 is_stmt 1 view .LVU757
+3136:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2399              		.loc 1 3136 6 is_stmt 0 view .LVU758
+ 2400 014e 0146     		mov	r1, r0
+ 2401 0150 0028     		cmp	r0, #0
+ 2402 0152 00F0ED80 		beq	.L213
+3139:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (tsect < sysect) return FR_NO_FILESYSTEM;	/* (Invalid volume size) */
+ 2403              		.loc 1 3139 3 is_stmt 1 view .LVU759
+3139:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (tsect < sysect) return FR_NO_FILESYSTEM;	/* (Invalid volume size) */
+ 2404              		.loc 1 3139 17 is_stmt 0 view .LVU760
+ 2405 0156 009B     		ldr	r3, [sp]
+ 2406 0158 C318     		adds	r3, r0, r3
+3139:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (tsect < sysect) return FR_NO_FILESYSTEM;	/* (Invalid volume size) */
+ 2407              		.loc 1 3139 42 view .LVU761
+ 2408 015a BAFBFBFB 		udiv	fp, r10, fp
+3139:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (tsect < sysect) return FR_NO_FILESYSTEM;	/* (Invalid volume size) */
+ 2409              		.loc 1 3139 10 view .LVU762
+ 2410 015e 5B44     		add	r3, r3, fp
+ 2411              	.LVL256:
+3140:Middlewares/Third_Party/FatFs/src/ff.c **** 		nclst = (tsect - sysect) / fs->csize;			/* Number of clusters */
+ 2412              		.loc 1 3140 3 is_stmt 1 view .LVU763
+3140:Middlewares/Third_Party/FatFs/src/ff.c **** 		nclst = (tsect - sysect) / fs->csize;			/* Number of clusters */
+ 2413              		.loc 1 3140 6 is_stmt 0 view .LVU764
+ 2414 0160 019A     		ldr	r2, [sp, #4]
+ 2415 0162 9A42     		cmp	r2, r3
+ 2416 0164 C0F0E680 		bcc	.L214
+3141:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst == 0) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
+ARM GAS  /tmp/cc5lWXRL.s 			page 155
+
+
+ 2417              		.loc 1 3141 3 is_stmt 1 view .LVU765
+3141:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst == 0) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
+ 2418              		.loc 1 3141 18 is_stmt 0 view .LVU766
+ 2419 0168 D21A     		subs	r2, r2, r3
+3141:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst == 0) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
+ 2420              		.loc 1 3141 9 view .LVU767
+ 2421 016a B2FBF9F0 		udiv	r0, r2, r9
+ 2422              	.LVL257:
+3142:Middlewares/Third_Party/FatFs/src/ff.c **** 		fmt = FS_FAT32;
+ 2423              		.loc 1 3142 3 is_stmt 1 view .LVU768
+3142:Middlewares/Third_Party/FatFs/src/ff.c **** 		fmt = FS_FAT32;
+ 2424              		.loc 1 3142 6 is_stmt 0 view .LVU769
+ 2425 016e 4A45     		cmp	r2, r9
+ 2426 0170 C0F0E280 		bcc	.L215
+3143:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst <= MAX_FAT16) fmt = FS_FAT16;
+ 2427              		.loc 1 3143 3 is_stmt 1 view .LVU770
+ 2428              	.LVL258:
+3144:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst <= MAX_FAT12) fmt = FS_FAT12;
+ 2429              		.loc 1 3144 3 view .LVU771
+3144:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst <= MAX_FAT12) fmt = FS_FAT12;
+ 2430              		.loc 1 3144 6 is_stmt 0 view .LVU772
+ 2431 0174 4FF6F572 		movw	r2, #65525
+ 2432 0178 9042     		cmp	r0, r2
+ 2433 017a 6DD9     		bls	.L216
+3143:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst <= MAX_FAT16) fmt = FS_FAT16;
+ 2434              		.loc 1 3143 7 view .LVU773
+ 2435 017c 4FF0030B 		mov	fp, #3
+ 2436              	.L189:
+ 2437              	.LVL259:
+3145:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2438              		.loc 1 3145 3 is_stmt 1 view .LVU774
+3145:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2439              		.loc 1 3145 6 is_stmt 0 view .LVU775
+ 2440 0180 40F6F572 		movw	r2, #4085
+ 2441 0184 9042     		cmp	r0, r2
+ 2442 0186 01D8     		bhi	.L190
+3145:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2443              		.loc 1 3145 31 view .LVU776
+ 2444 0188 4FF0010B 		mov	fp, #1
+ 2445              	.LVL260:
+ 2446              	.L190:
+3148:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->volbase = bsect;							/* Volume start sector */
+ 2447              		.loc 1 3148 3 is_stmt 1 view .LVU777
+3148:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->volbase = bsect;							/* Volume start sector */
+ 2448              		.loc 1 3148 24 is_stmt 0 view .LVU778
+ 2449 018c 00F10209 		add	r9, r0, #2
+3148:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->volbase = bsect;							/* Volume start sector */
+ 2450              		.loc 1 3148 16 view .LVU779
+ 2451 0190 C4F81890 		str	r9, [r4, #24]
+3149:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fatbase = bsect + nrsv; 					/* FAT start sector */
+ 2452              		.loc 1 3149 3 is_stmt 1 view .LVU780
+3149:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fatbase = bsect + nrsv; 					/* FAT start sector */
+ 2453              		.loc 1 3149 15 is_stmt 0 view .LVU781
+ 2454 0194 2662     		str	r6, [r4, #32]
+3150:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->database = bsect + sysect;					/* Data start sector */
+ 2455              		.loc 1 3150 3 is_stmt 1 view .LVU782
+3150:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->database = bsect + sysect;					/* Data start sector */
+ARM GAS  /tmp/cc5lWXRL.s 			page 156
+
+
+ 2456              		.loc 1 3150 23 is_stmt 0 view .LVU783
+ 2457 0196 8A19     		adds	r2, r1, r6
+3150:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->database = bsect + sysect;					/* Data start sector */
+ 2458              		.loc 1 3150 15 view .LVU784
+ 2459 0198 6262     		str	r2, [r4, #36]
+3151:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fmt == FS_FAT32) {
+ 2460              		.loc 1 3151 3 is_stmt 1 view .LVU785
+3151:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fmt == FS_FAT32) {
+ 2461              		.loc 1 3151 24 is_stmt 0 view .LVU786
+ 2462 019a 3344     		add	r3, r3, r6
+ 2463              	.LVL261:
+3151:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fmt == FS_FAT32) {
+ 2464              		.loc 1 3151 16 view .LVU787
+ 2465 019c E362     		str	r3, [r4, #44]
+3152:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM;	/* (Must be FAT32 revision 0.0
+ 2466              		.loc 1 3152 3 is_stmt 1 view .LVU788
+3152:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM;	/* (Must be FAT32 revision 0.0
+ 2467              		.loc 1 3152 6 is_stmt 0 view .LVU789
+ 2468 019e BBF1030F 		cmp	fp, #3
+ 2469 01a2 5CD0     		beq	.L224
+3158:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->dirbase = fs->fatbase + fasize;			/* Root directory start sector */
+ 2470              		.loc 1 3158 4 is_stmt 1 view .LVU790
+3158:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->dirbase = fs->fatbase + fasize;			/* Root directory start sector */
+ 2471              		.loc 1 3158 7 is_stmt 0 view .LVU791
+ 2472 01a4 BAF1000F 		cmp	r10, #0
+ 2473 01a8 00F0CC80 		beq	.L220
+3159:Middlewares/Third_Party/FatFs/src/ff.c **** 			szbfat = (fmt == FS_FAT16) ?				/* (Needed FAT size) */
+ 2474              		.loc 1 3159 4 is_stmt 1 view .LVU792
+3159:Middlewares/Third_Party/FatFs/src/ff.c **** 			szbfat = (fmt == FS_FAT16) ?				/* (Needed FAT size) */
+ 2475              		.loc 1 3159 30 is_stmt 0 view .LVU793
+ 2476 01ac 009B     		ldr	r3, [sp]
+ 2477 01ae 1A44     		add	r2, r2, r3
+3159:Middlewares/Third_Party/FatFs/src/ff.c **** 			szbfat = (fmt == FS_FAT16) ?				/* (Needed FAT size) */
+ 2478              		.loc 1 3159 16 view .LVU794
+ 2479 01b0 A262     		str	r2, [r4, #40]
+3160:Middlewares/Third_Party/FatFs/src/ff.c **** 				fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+ 2480              		.loc 1 3160 4 is_stmt 1 view .LVU795
+3161:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2481              		.loc 1 3161 22 is_stmt 0 view .LVU796
+ 2482 01b2 BBF1020F 		cmp	fp, #2
+ 2483 01b6 63D0     		beq	.L225
+3161:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2484              		.loc 1 3161 37 discriminator 2 view .LVU797
+ 2485 01b8 09EB4902 		add	r2, r9, r9, lsl #1
+3161:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2486              		.loc 1 3161 61 discriminator 2 view .LVU798
+ 2487 01bc 09F00103 		and	r3, r9, #1
+3161:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2488              		.loc 1 3161 22 discriminator 2 view .LVU799
+ 2489 01c0 03EB5203 		add	r3, r3, r2, lsr #1
+ 2490              	.LVL262:
+ 2491              	.L192:
+3163:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2492              		.loc 1 3163 3 is_stmt 1 view .LVU800
+3163:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2493              		.loc 1 3163 27 is_stmt 0 view .LVU801
+ 2494 01c4 4344     		add	r3, r3, r8
+ARM GAS  /tmp/cc5lWXRL.s 			page 157
+
+
+ 2495              	.LVL263:
+3163:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2496              		.loc 1 3163 27 view .LVU802
+ 2497 01c6 013B     		subs	r3, r3, #1
+3163:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2498              		.loc 1 3163 43 view .LVU803
+ 2499 01c8 B3FBF8F8 		udiv	r8, r3, r8
+3163:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2500              		.loc 1 3163 6 view .LVU804
+ 2501 01cc B845     		cmp	r8, r7
+ 2502 01ce 00F2BB80 		bhi	.L221
+3167:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag = 0x80;
+ 2503              		.loc 1 3167 3 is_stmt 1 view .LVU805
+3167:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag = 0x80;
+ 2504              		.loc 1 3167 33 is_stmt 0 view .LVU806
+ 2505 01d2 4FF0FF33 		mov	r3, #-1
+ 2506 01d6 6361     		str	r3, [r4, #20]
+3167:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag = 0x80;
+ 2507              		.loc 1 3167 17 view .LVU807
+ 2508 01d8 2361     		str	r3, [r4, #16]
+3168:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_FS_NOFSINFO & 3) != 3
+ 2509              		.loc 1 3168 3 is_stmt 1 view .LVU808
+3168:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_FS_NOFSINFO & 3) != 3
+ 2510              		.loc 1 3168 16 is_stmt 0 view .LVU809
+ 2511 01da 8023     		movs	r3, #128
+ 2512 01dc 2371     		strb	r3, [r4, #4]
+3170:Middlewares/Third_Party/FatFs/src/ff.c **** 			&& ld_word(fs->win + BPB_FSInfo32) == 1
+ 2513              		.loc 1 3170 3 is_stmt 1 view .LVU810
+3170:Middlewares/Third_Party/FatFs/src/ff.c **** 			&& ld_word(fs->win + BPB_FSInfo32) == 1
+ 2514              		.loc 1 3170 6 is_stmt 0 view .LVU811
+ 2515 01de BBF1030F 		cmp	fp, #3
+ 2516 01e2 50D0     		beq	.L226
+ 2517              	.L194:
+3191:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->id = ++Fsid;		/* File system mount ID */
+ 2518              		.loc 1 3191 2 is_stmt 1 view .LVU812
+3191:Middlewares/Third_Party/FatFs/src/ff.c **** 	fs->id = ++Fsid;		/* File system mount ID */
+ 2519              		.loc 1 3191 14 is_stmt 0 view .LVU813
+ 2520 01e4 84F800B0 		strb	fp, [r4]
+3192:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1
+ 2521              		.loc 1 3192 2 is_stmt 1 view .LVU814
+3192:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1
+ 2522              		.loc 1 3192 11 is_stmt 0 view .LVU815
+ 2523 01e8 4C4A     		ldr	r2, .L229+4
+ 2524 01ea 1388     		ldrh	r3, [r2]
+ 2525 01ec 0133     		adds	r3, r3, #1
+ 2526 01ee 9BB2     		uxth	r3, r3
+3192:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1
+ 2527              		.loc 1 3192 9 view .LVU816
+ 2528 01f0 1380     		strh	r3, [r2]	@ movhi
+ 2529 01f2 E380     		strh	r3, [r4, #6]	@ movhi
+3203:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2530              		.loc 1 3203 2 is_stmt 1 view .LVU817
+ 2531 01f4 2046     		mov	r0, r4
+ 2532 01f6 FFF7FEFF 		bl	clear_lock
+ 2533              	.LVL264:
+3205:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 2534              		.loc 1 3205 2 view .LVU818
+ARM GAS  /tmp/cc5lWXRL.s 			page 158
+
+
+3205:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 2535              		.loc 1 3205 9 is_stmt 0 view .LVU819
+ 2536 01fa 74E0     		b	.L178
+ 2537              	.LVL265:
+ 2538              	.L204:
+3054:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2539              		.loc 1 3054 54 view .LVU820
+ 2540 01fc 0020     		movs	r0, #0
+ 2541              	.LVL266:
+ 2542              	.L183:
+3054:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2543              		.loc 1 3054 10 discriminator 4 view .LVU821
+ 2544 01fe 06AB     		add	r3, sp, #24
+ 2545 0200 03EB8603 		add	r3, r3, r6, lsl #2
+ 2546 0204 43F8100C 		str	r0, [r3, #-16]
+3052:Middlewares/Third_Party/FatFs/src/ff.c **** 			pt = fs->win + (MBR_Table + i * SZ_PTE);
+ 2547              		.loc 1 3052 22 is_stmt 1 discriminator 4 view .LVU822
+3052:Middlewares/Third_Party/FatFs/src/ff.c **** 			pt = fs->win + (MBR_Table + i * SZ_PTE);
+ 2548              		.loc 1 3052 23 is_stmt 0 discriminator 4 view .LVU823
+ 2549 0208 0136     		adds	r6, r6, #1
+ 2550              	.LVL267:
+ 2551              	.L181:
+3052:Middlewares/Third_Party/FatFs/src/ff.c **** 			pt = fs->win + (MBR_Table + i * SZ_PTE);
+ 2552              		.loc 1 3052 15 is_stmt 1 discriminator 2 view .LVU824
+3052:Middlewares/Third_Party/FatFs/src/ff.c **** 			pt = fs->win + (MBR_Table + i * SZ_PTE);
+ 2553              		.loc 1 3052 3 is_stmt 0 discriminator 2 view .LVU825
+ 2554 020a 032E     		cmp	r6, #3
+ 2555 020c 0ED8     		bhi	.L227
+3053:Middlewares/Third_Party/FatFs/src/ff.c **** 			br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
+ 2556              		.loc 1 3053 4 is_stmt 1 view .LVU826
+3053:Middlewares/Third_Party/FatFs/src/ff.c **** 			br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
+ 2557              		.loc 1 3053 9 is_stmt 0 view .LVU827
+ 2558 020e 04F13400 		add	r0, r4, #52
+3053:Middlewares/Third_Party/FatFs/src/ff.c **** 			br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
+ 2559              		.loc 1 3053 34 view .LVU828
+ 2560 0212 3301     		lsls	r3, r6, #4
+3053:Middlewares/Third_Party/FatFs/src/ff.c **** 			br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
+ 2561              		.loc 1 3053 30 view .LVU829
+ 2562 0214 03F5DF73 		add	r3, r3, #446
+3053:Middlewares/Third_Party/FatFs/src/ff.c **** 			br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
+ 2563              		.loc 1 3053 7 view .LVU830
+ 2564 0218 1844     		add	r0, r0, r3
+ 2565              	.LVL268:
+3054:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2566              		.loc 1 3054 4 is_stmt 1 view .LVU831
+3054:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2567              		.loc 1 3054 14 is_stmt 0 view .LVU832
+ 2568 021a 0379     		ldrb	r3, [r0, #4]	@ zero_extendqisi2
+3054:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2569              		.loc 1 3054 54 view .LVU833
+ 2570 021c 002B     		cmp	r3, #0
+ 2571 021e EDD0     		beq	.L204
+3054:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2572              		.loc 1 3054 29 discriminator 1 view .LVU834
+ 2573 0220 0830     		adds	r0, r0, #8
+ 2574              	.LVL269:
+3054:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ARM GAS  /tmp/cc5lWXRL.s 			page 159
+
+
+ 2575              		.loc 1 3054 29 discriminator 1 view .LVU835
+ 2576 0222 FFF7FEFF 		bl	ld_dword
+ 2577              	.LVL270:
+3054:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2578              		.loc 1 3054 29 discriminator 1 view .LVU836
+ 2579 0226 EAE7     		b	.L183
+ 2580              	.LVL271:
+ 2581              	.L203:
+3052:Middlewares/Third_Party/FatFs/src/ff.c **** 			pt = fs->win + (MBR_Table + i * SZ_PTE);
+ 2582              		.loc 1 3052 10 view .LVU837
+ 2583 0228 0026     		movs	r6, #0
+ 2584              	.LVL272:
+3052:Middlewares/Third_Party/FatFs/src/ff.c **** 			pt = fs->win + (MBR_Table + i * SZ_PTE);
+ 2585              		.loc 1 3052 10 view .LVU838
+ 2586 022a EEE7     		b	.L181
+ 2587              	.LVL273:
+ 2588              	.L227:
+3052:Middlewares/Third_Party/FatFs/src/ff.c **** 			pt = fs->win + (MBR_Table + i * SZ_PTE);
+ 2589              		.loc 1 3052 10 view .LVU839
+ 2590 022c 0027     		movs	r7, #0
+ 2591              	.LVL274:
+3052:Middlewares/Third_Party/FatFs/src/ff.c **** 			pt = fs->win + (MBR_Table + i * SZ_PTE);
+ 2592              		.loc 1 3052 10 view .LVU840
+ 2593 022e 0AE0     		b	.L186
+ 2594              	.LVL275:
+ 2595              	.L228:
+3060:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
+ 2596              		.loc 1 3060 18 discriminator 1 view .LVU841
+ 2597 0230 3146     		mov	r1, r6
+ 2598 0232 2046     		mov	r0, r4
+ 2599 0234 FFF7FEFF 		bl	check_fs
+ 2600              	.LVL276:
+3061:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 2601              		.loc 1 3061 11 is_stmt 1 discriminator 1 view .LVU842
+3061:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 2602              		.loc 1 3061 3 is_stmt 0 discriminator 1 view .LVU843
+ 2603 0238 0128     		cmp	r0, #1
+ 2604 023a 7FF635AF 		bls	.L182
+ 2605              	.LVL277:
+ 2606              	.L185:
+3061:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 2607              		.loc 1 3061 40 discriminator 1 view .LVU844
+ 2608 023e 0137     		adds	r7, r7, #1
+ 2609              	.LVL278:
+3061:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 2610              		.loc 1 3061 40 discriminator 1 view .LVU845
+ 2611 0240 032F     		cmp	r7, #3
+ 2612 0242 3FF631AF 		bhi	.L182
+ 2613              	.LVL279:
+ 2614              	.L186:
+3058:Middlewares/Third_Party/FatFs/src/ff.c **** 			bsect = br[i];
+ 2615              		.loc 1 3058 3 is_stmt 1 view .LVU846
+3059:Middlewares/Third_Party/FatFs/src/ff.c **** 			fmt = bsect ? check_fs(fs, bsect) : 3;	/* Check the partition */
+ 2616              		.loc 1 3059 4 view .LVU847
+3059:Middlewares/Third_Party/FatFs/src/ff.c **** 			fmt = bsect ? check_fs(fs, bsect) : 3;	/* Check the partition */
+ 2617              		.loc 1 3059 10 is_stmt 0 view .LVU848
+ 2618 0246 06AB     		add	r3, sp, #24
+ARM GAS  /tmp/cc5lWXRL.s 			page 160
+
+
+ 2619 0248 03EB8703 		add	r3, r3, r7, lsl #2
+ 2620 024c 53F8106C 		ldr	r6, [r3, #-16]
+ 2621              	.LVL280:
+3060:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
+ 2622              		.loc 1 3060 4 is_stmt 1 view .LVU849
+3060:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
+ 2623              		.loc 1 3060 8 is_stmt 0 view .LVU850
+ 2624 0250 002E     		cmp	r6, #0
+ 2625 0252 EDD1     		bne	.L228
+ 2626 0254 0320     		movs	r0, #3
+ 2627 0256 F2E7     		b	.L185
+ 2628              	.LVL281:
+ 2629              	.L216:
+3144:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nclst <= MAX_FAT12) fmt = FS_FAT12;
+ 2630              		.loc 1 3144 31 view .LVU851
+ 2631 0258 4FF0020B 		mov	fp, #2
+ 2632 025c 90E7     		b	.L189
+ 2633              	.LVL282:
+ 2634              	.L224:
+3153:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->n_rootdir) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
+ 2635              		.loc 1 3153 4 is_stmt 1 view .LVU852
+3153:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->n_rootdir) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
+ 2636              		.loc 1 3153 8 is_stmt 0 view .LVU853
+ 2637 025e 04F15E00 		add	r0, r4, #94
+ 2638              	.LVL283:
+3153:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->n_rootdir) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
+ 2639              		.loc 1 3153 8 view .LVU854
+ 2640 0262 FFF7FEFF 		bl	ld_word
+ 2641              	.LVL284:
+3153:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->n_rootdir) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
+ 2642              		.loc 1 3153 7 view .LVU855
+ 2643 0266 0028     		cmp	r0, #0
+ 2644 0268 68D1     		bne	.L218
+3154:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->dirbase = ld_dword(fs->win + BPB_RootClus32);	/* Root directory start cluster */
+ 2645              		.loc 1 3154 4 is_stmt 1 view .LVU856
+3154:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->dirbase = ld_dword(fs->win + BPB_RootClus32);	/* Root directory start cluster */
+ 2646              		.loc 1 3154 7 is_stmt 0 view .LVU857
+ 2647 026a BAF1000F 		cmp	r10, #0
+ 2648 026e 67D1     		bne	.L219
+3155:Middlewares/Third_Party/FatFs/src/ff.c **** 			szbfat = fs->n_fatent * 4;					/* (Needed FAT size) */
+ 2649              		.loc 1 3155 4 is_stmt 1 view .LVU858
+3155:Middlewares/Third_Party/FatFs/src/ff.c **** 			szbfat = fs->n_fatent * 4;					/* (Needed FAT size) */
+ 2650              		.loc 1 3155 18 is_stmt 0 view .LVU859
+ 2651 0270 04F16000 		add	r0, r4, #96
+ 2652 0274 FFF7FEFF 		bl	ld_dword
+ 2653              	.LVL285:
+3155:Middlewares/Third_Party/FatFs/src/ff.c **** 			szbfat = fs->n_fatent * 4;					/* (Needed FAT size) */
+ 2654              		.loc 1 3155 16 view .LVU860
+ 2655 0278 A062     		str	r0, [r4, #40]
+3156:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 2656              		.loc 1 3156 4 is_stmt 1 view .LVU861
+3156:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 2657              		.loc 1 3156 11 is_stmt 0 view .LVU862
+ 2658 027a 4FEA8903 		lsl	r3, r9, #2
+ 2659              	.LVL286:
+3156:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 2660              		.loc 1 3156 11 view .LVU863
+ARM GAS  /tmp/cc5lWXRL.s 			page 161
+
+
+ 2661 027e A1E7     		b	.L192
+ 2662              	.LVL287:
+ 2663              	.L225:
+3161:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 2664              		.loc 1 3161 22 discriminator 1 view .LVU864
+ 2665 0280 4FEA4903 		lsl	r3, r9, #1
+ 2666 0284 9EE7     		b	.L192
+ 2667              	.LVL288:
+ 2668              	.L226:
+3171:Middlewares/Third_Party/FatFs/src/ff.c **** 			&& move_window(fs, bsect + 1) == FR_OK)
+ 2669              		.loc 1 3171 7 view .LVU865
+ 2670 0286 04F16400 		add	r0, r4, #100
+ 2671 028a FFF7FEFF 		bl	ld_word
+ 2672              	.LVL289:
+3171:Middlewares/Third_Party/FatFs/src/ff.c **** 			&& move_window(fs, bsect + 1) == FR_OK)
+ 2673              		.loc 1 3171 4 view .LVU866
+ 2674 028e 0128     		cmp	r0, #1
+ 2675 0290 A8D1     		bne	.L194
+3172:Middlewares/Third_Party/FatFs/src/ff.c **** 		{
+ 2676              		.loc 1 3172 7 view .LVU867
+ 2677 0292 711C     		adds	r1, r6, #1
+ 2678 0294 2046     		mov	r0, r4
+ 2679 0296 FFF7FEFF 		bl	move_window
+ 2680              	.LVL290:
+3172:Middlewares/Third_Party/FatFs/src/ff.c **** 		{
+ 2681              		.loc 1 3172 4 view .LVU868
+ 2682 029a 0028     		cmp	r0, #0
+ 2683 029c A2D1     		bne	.L194
+3174:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ld_word(fs->win + BS_55AA) == 0xAA55	/* Load FSINFO data if available */
+ 2684              		.loc 1 3174 4 is_stmt 1 view .LVU869
+3174:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ld_word(fs->win + BS_55AA) == 0xAA55	/* Load FSINFO data if available */
+ 2685              		.loc 1 3174 17 is_stmt 0 view .LVU870
+ 2686 029e 0023     		movs	r3, #0
+ 2687 02a0 2371     		strb	r3, [r4, #4]
+3175:Middlewares/Third_Party/FatFs/src/ff.c **** 				&& ld_dword(fs->win + FSI_LeadSig) == 0x41615252
+ 2688              		.loc 1 3175 4 is_stmt 1 view .LVU871
+3175:Middlewares/Third_Party/FatFs/src/ff.c **** 				&& ld_dword(fs->win + FSI_LeadSig) == 0x41615252
+ 2689              		.loc 1 3175 8 is_stmt 0 view .LVU872
+ 2690 02a2 04F23220 		addw	r0, r4, #562
+ 2691 02a6 FFF7FEFF 		bl	ld_word
+ 2692              	.LVL291:
+3175:Middlewares/Third_Party/FatFs/src/ff.c **** 				&& ld_dword(fs->win + FSI_LeadSig) == 0x41615252
+ 2693              		.loc 1 3175 7 view .LVU873
+ 2694 02aa 4AF65523 		movw	r3, #43605
+ 2695 02ae 9842     		cmp	r0, r3
+ 2696 02b0 98D1     		bne	.L194
+3176:Middlewares/Third_Party/FatFs/src/ff.c **** 				&& ld_dword(fs->win + FSI_StrucSig) == 0x61417272)
+ 2697              		.loc 1 3176 8 view .LVU874
+ 2698 02b2 04F13400 		add	r0, r4, #52
+ 2699 02b6 FFF7FEFF 		bl	ld_dword
+ 2700              	.LVL292:
+3176:Middlewares/Third_Party/FatFs/src/ff.c **** 				&& ld_dword(fs->win + FSI_StrucSig) == 0x61417272)
+ 2701              		.loc 1 3176 5 view .LVU875
+ 2702 02ba 194B     		ldr	r3, .L229+8
+ 2703 02bc 9842     		cmp	r0, r3
+ 2704 02be 91D1     		bne	.L194
+3177:Middlewares/Third_Party/FatFs/src/ff.c **** 			{
+ARM GAS  /tmp/cc5lWXRL.s 			page 162
+
+
+ 2705              		.loc 1 3177 8 view .LVU876
+ 2706 02c0 04F50670 		add	r0, r4, #536
+ 2707 02c4 FFF7FEFF 		bl	ld_dword
+ 2708              	.LVL293:
+3177:Middlewares/Third_Party/FatFs/src/ff.c **** 			{
+ 2709              		.loc 1 3177 5 view .LVU877
+ 2710 02c8 164B     		ldr	r3, .L229+12
+ 2711 02ca 9842     		cmp	r0, r3
+ 2712 02cc 8AD1     		bne	.L194
+3180:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2713              		.loc 1 3180 5 is_stmt 1 view .LVU878
+3180:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2714              		.loc 1 3180 21 is_stmt 0 view .LVU879
+ 2715 02ce 04F50770 		add	r0, r4, #540
+ 2716 02d2 FFF7FEFF 		bl	ld_dword
+ 2717              	.LVL294:
+3180:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2718              		.loc 1 3180 19 view .LVU880
+ 2719 02d6 6061     		str	r0, [r4, #20]
+3183:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2720              		.loc 1 3183 5 is_stmt 1 view .LVU881
+3183:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2721              		.loc 1 3183 21 is_stmt 0 view .LVU882
+ 2722 02d8 04F50870 		add	r0, r4, #544
+ 2723 02dc FFF7FEFF 		bl	ld_dword
+ 2724              	.LVL295:
+3183:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2725              		.loc 1 3183 19 view .LVU883
+ 2726 02e0 2061     		str	r0, [r4, #16]
+ 2727 02e2 7FE7     		b	.L194
+ 2728              	.LVL296:
+ 2729              	.L195:
+3011:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2730              		.loc 1 3011 22 view .LVU884
+ 2731 02e4 0B25     		movs	r5, #11
+ 2732              	.LVL297:
+ 2733              	.L178:
+3206:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2734              		.loc 1 3206 1 view .LVU885
+ 2735 02e6 2846     		mov	r0, r5
+ 2736 02e8 07B0     		add	sp, sp, #28
+ 2737              	.LCFI20:
+ 2738              		.cfi_remember_state
+ 2739              		.cfi_def_cfa_offset 36
+ 2740              		@ sp needed
+ 2741 02ea BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 2742              	.LVL298:
+ 2743              	.L196:
+ 2744              	.LCFI21:
+ 2745              		.cfi_restore_state
+3015:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2746              		.loc 1 3015 18 view .LVU886
+ 2747 02ee 0C25     		movs	r5, #12
+ 2748              	.LVL299:
+3015:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2749              		.loc 1 3015 18 view .LVU887
+ 2750 02f0 F9E7     		b	.L178
+ARM GAS  /tmp/cc5lWXRL.s 			page 163
+
+
+ 2751              	.LVL300:
+ 2752              	.L198:
+3038:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 2753              		.loc 1 3038 10 view .LVU888
+ 2754 02f2 0325     		movs	r5, #3
+ 2755 02f4 F7E7     		b	.L178
+ 2756              	.L199:
+3041:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 2757              		.loc 1 3041 10 view .LVU889
+ 2758 02f6 0A25     		movs	r5, #10
+ 2759 02f8 F5E7     		b	.L178
+ 2760              	.LVL301:
+ 2761              	.L200:
+3044:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+ 2762              		.loc 1 3044 70 view .LVU890
+ 2763 02fa 0125     		movs	r5, #1
+ 2764 02fc F3E7     		b	.L178
+ 2765              	.L201:
+3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 2766              		.loc 1 3045 78 view .LVU891
+ 2767 02fe 0125     		movs	r5, #1
+ 2768 0300 F1E7     		b	.L178
+ 2769              	.LVL302:
+ 2770              	.L206:
+3063:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (fmt >= 2) return FR_NO_FILESYSTEM;	/* No FAT volume is found */
+ 2771              		.loc 1 3063 23 view .LVU892
+ 2772 0302 0125     		movs	r5, #1
+ 2773 0304 EFE7     		b	.L178
+ 2774              	.L207:
+3064:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2775              		.loc 1 3064 23 view .LVU893
+ 2776 0306 0D25     		movs	r5, #13
+ 2777 0308 EDE7     		b	.L178
+ 2778              	.LVL303:
+ 2779              	.L208:
+3116:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2780              		.loc 1 3116 59 view .LVU894
+ 2781 030a 0D25     		movs	r5, #13
+ 2782 030c EBE7     		b	.L178
+ 2783              	.LVL304:
+ 2784              	.L209:
+3123:Middlewares/Third_Party/FatFs/src/ff.c **** 		fasize *= fs->n_fats;							/* Number of sectors for FAT area */
+ 2785              		.loc 1 3123 50 view .LVU895
+ 2786 030e 0D25     		movs	r5, #13
+ 2787 0310 E9E7     		b	.L178
+ 2788              	.LVL305:
+ 2789              	.L210:
+3127:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2790              		.loc 1 3127 63 view .LVU896
+ 2791 0312 0D25     		movs	r5, #13
+ 2792 0314 E7E7     		b	.L178
+ 2793              	.L230:
+ 2794 0316 00BF     		.align	2
+ 2795              	.L229:
+ 2796 0318 00000000 		.word	.LANCHOR2
+ 2797 031c 00000000 		.word	.LANCHOR3
+ 2798 0320 52526141 		.word	1096897106
+ARM GAS  /tmp/cc5lWXRL.s 			page 164
+
+
+ 2799 0324 72724161 		.word	1631679090
+ 2800              	.LVL306:
+ 2801              	.L211:
+3127:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2802              		.loc 1 3127 63 view .LVU897
+ 2803 0328 0D25     		movs	r5, #13
+ 2804 032a DCE7     		b	.L178
+ 2805              	.L212:
+3130:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2806              		.loc 1 3130 49 view .LVU898
+ 2807 032c 0D25     		movs	r5, #13
+ 2808 032e DAE7     		b	.L178
+ 2809              	.LVL307:
+ 2810              	.L213:
+3136:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2811              		.loc 1 3136 25 view .LVU899
+ 2812 0330 0D25     		movs	r5, #13
+ 2813 0332 D8E7     		b	.L178
+ 2814              	.LVL308:
+ 2815              	.L214:
+3140:Middlewares/Third_Party/FatFs/src/ff.c **** 		nclst = (tsect - sysect) / fs->csize;			/* Number of clusters */
+ 2816              		.loc 1 3140 30 view .LVU900
+ 2817 0334 0D25     		movs	r5, #13
+ 2818 0336 D6E7     		b	.L178
+ 2819              	.LVL309:
+ 2820              	.L215:
+3142:Middlewares/Third_Party/FatFs/src/ff.c **** 		fmt = FS_FAT32;
+ 2821              		.loc 1 3142 26 view .LVU901
+ 2822 0338 0D25     		movs	r5, #13
+ 2823 033a D4E7     		b	.L178
+ 2824              	.LVL310:
+ 2825              	.L218:
+3153:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->n_rootdir) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
+ 2826              		.loc 1 3153 52 view .LVU902
+ 2827 033c 0D25     		movs	r5, #13
+ 2828 033e D2E7     		b	.L178
+ 2829              	.L219:
+3154:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->dirbase = ld_dword(fs->win + BPB_RootClus32);	/* Root directory start cluster */
+ 2830              		.loc 1 3154 30 view .LVU903
+ 2831 0340 0D25     		movs	r5, #13
+ 2832 0342 D0E7     		b	.L178
+ 2833              	.LVL311:
+ 2834              	.L220:
+3158:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->dirbase = fs->fatbase + fasize;			/* Root directory start sector */
+ 2835              		.loc 1 3158 35 view .LVU904
+ 2836 0344 0D25     		movs	r5, #13
+ 2837 0346 CEE7     		b	.L178
+ 2838              	.LVL312:
+ 2839              	.L221:
+3163:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2840              		.loc 1 3163 60 view .LVU905
+ 2841 0348 0D25     		movs	r5, #13
+ 2842 034a CCE7     		b	.L178
+ 2843              		.cfi_endproc
+ 2844              	.LFE1219:
+ 2846              		.section	.text.put_fat,"ax",%progbits
+ 2847              		.align	1
+ARM GAS  /tmp/cc5lWXRL.s 			page 165
+
+
+ 2848              		.syntax unified
+ 2849              		.thumb
+ 2850              		.thumb_func
+ 2851              		.fpu fpv5-d16
+ 2853              	put_fat:
+ 2854              	.LVL313:
+ 2855              	.LFB1201:
+1086:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT bc;
+ 2856              		.loc 1 1086 1 is_stmt 1 view -0
+ 2857              		.cfi_startproc
+ 2858              		@ args = 0, pretend = 0, frame = 0
+ 2859              		@ frame_needed = 0, uses_anonymous_args = 0
+1086:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT bc;
+ 2860              		.loc 1 1086 1 is_stmt 0 view .LVU907
+ 2861 0000 2DE9F047 		push	{r4, r5, r6, r7, r8, r9, r10, lr}
+ 2862              	.LCFI22:
+ 2863              		.cfi_def_cfa_offset 32
+ 2864              		.cfi_offset 4, -32
+ 2865              		.cfi_offset 5, -28
+ 2866              		.cfi_offset 6, -24
+ 2867              		.cfi_offset 7, -20
+ 2868              		.cfi_offset 8, -16
+ 2869              		.cfi_offset 9, -12
+ 2870              		.cfi_offset 10, -8
+ 2871              		.cfi_offset 14, -4
+1087:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *p;
+ 2872              		.loc 1 1087 2 is_stmt 1 view .LVU908
+1088:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_INT_ERR;
+ 2873              		.loc 1 1088 2 view .LVU909
+1089:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2874              		.loc 1 1089 2 view .LVU910
+ 2875              	.LVL314:
+1091:Middlewares/Third_Party/FatFs/src/ff.c **** 		switch (fs->fs_type) {
+ 2876              		.loc 1 1091 2 view .LVU911
+1091:Middlewares/Third_Party/FatFs/src/ff.c **** 		switch (fs->fs_type) {
+ 2877              		.loc 1 1091 5 is_stmt 0 view .LVU912
+ 2878 0004 0129     		cmp	r1, #1
+ 2879 0006 40F29680 		bls	.L239
+ 2880 000a 0446     		mov	r4, r0
+ 2881 000c 0D46     		mov	r5, r1
+ 2882 000e 1746     		mov	r7, r2
+1091:Middlewares/Third_Party/FatFs/src/ff.c **** 		switch (fs->fs_type) {
+ 2883              		.loc 1 1091 28 discriminator 1 view .LVU913
+ 2884 0010 8369     		ldr	r3, [r0, #24]
+1091:Middlewares/Third_Party/FatFs/src/ff.c **** 		switch (fs->fs_type) {
+ 2885              		.loc 1 1091 16 discriminator 1 view .LVU914
+ 2886 0012 8B42     		cmp	r3, r1
+ 2887 0014 40F29180 		bls	.L240
+1092:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT12 :	/* Bitfield items */
+ 2888              		.loc 1 1092 3 is_stmt 1 view .LVU915
+1092:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT12 :	/* Bitfield items */
+ 2889              		.loc 1 1092 13 is_stmt 0 view .LVU916
+ 2890 0018 0378     		ldrb	r3, [r0]	@ zero_extendqisi2
+1092:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT12 :	/* Bitfield items */
+ 2891              		.loc 1 1092 3 view .LVU917
+ 2892 001a 022B     		cmp	r3, #2
+ 2893 001c 4FD0     		beq	.L233
+ARM GAS  /tmp/cc5lWXRL.s 			page 166
+
+
+ 2894 001e 032B     		cmp	r3, #3
+ 2895 0020 67D0     		beq	.L234
+ 2896 0022 012B     		cmp	r3, #1
+ 2897 0024 03D0     		beq	.L243
+ 2898 0026 0226     		movs	r6, #2
+ 2899              	.LVL315:
+ 2900              	.L232:
+1128:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 2901              		.loc 1 1128 2 is_stmt 1 view .LVU918
+1129:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 2902              		.loc 1 1129 1 is_stmt 0 view .LVU919
+ 2903 0028 3046     		mov	r0, r6
+ 2904 002a BDE8F087 		pop	{r4, r5, r6, r7, r8, r9, r10, pc}
+ 2905              	.LVL316:
+ 2906              	.L243:
+1094:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ 2907              		.loc 1 1094 4 is_stmt 1 view .LVU920
+1094:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ 2908              		.loc 1 1094 21 view .LVU921
+1094:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ 2909              		.loc 1 1094 24 is_stmt 0 view .LVU922
+ 2910 002e 01EB5108 		add	r8, r1, r1, lsr #1
+ 2911              	.LVL317:
+1095:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 2912              		.loc 1 1095 4 is_stmt 1 view .LVU923
+1095:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 2913              		.loc 1 1095 28 is_stmt 0 view .LVU924
+ 2914 0032 416A     		ldr	r1, [r0, #36]
+ 2915              	.LVL318:
+1095:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 2916              		.loc 1 1095 46 view .LVU925
+ 2917 0034 8389     		ldrh	r3, [r0, #12]
+1095:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 2918              		.loc 1 1095 44 view .LVU926
+ 2919 0036 B8FBF3F3 		udiv	r3, r8, r3
+1095:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 2920              		.loc 1 1095 10 view .LVU927
+ 2921 003a 1944     		add	r1, r1, r3
+ 2922 003c FFF7FEFF 		bl	move_window
+ 2923              	.LVL319:
+1096:Middlewares/Third_Party/FatFs/src/ff.c **** 			p = fs->win + bc++ % SS(fs);
+ 2924              		.loc 1 1096 4 is_stmt 1 view .LVU928
+1096:Middlewares/Third_Party/FatFs/src/ff.c **** 			p = fs->win + bc++ % SS(fs);
+ 2925              		.loc 1 1096 7 is_stmt 0 view .LVU929
+ 2926 0040 0646     		mov	r6, r0
+ 2927 0042 0028     		cmp	r0, #0
+ 2928 0044 F0D1     		bne	.L232
+1097:Middlewares/Third_Party/FatFs/src/ff.c **** 			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+ 2929              		.loc 1 1097 4 is_stmt 1 view .LVU930
+1097:Middlewares/Third_Party/FatFs/src/ff.c **** 			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+ 2930              		.loc 1 1097 8 is_stmt 0 view .LVU931
+ 2931 0046 04F1340A 		add	r10, r4, #52
+1097:Middlewares/Third_Party/FatFs/src/ff.c **** 			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+ 2932              		.loc 1 1097 20 view .LVU932
+ 2933 004a 08F10109 		add	r9, r8, #1
+ 2934              	.LVL320:
+1097:Middlewares/Third_Party/FatFs/src/ff.c **** 			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+ARM GAS  /tmp/cc5lWXRL.s 			page 167
+
+
+ 2935              		.loc 1 1097 25 view .LVU933
+ 2936 004e A389     		ldrh	r3, [r4, #12]
+1097:Middlewares/Third_Party/FatFs/src/ff.c **** 			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+ 2937              		.loc 1 1097 23 view .LVU934
+ 2938 0050 B8FBF3F2 		udiv	r2, r8, r3
+ 2939 0054 03FB1288 		mls	r8, r3, r2, r8
+ 2940              	.LVL321:
+1098:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2941              		.loc 1 1098 4 is_stmt 1 view .LVU935
+1098:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2942              		.loc 1 1098 7 is_stmt 0 view .LVU936
+ 2943 0058 15F00105 		ands	r5, r5, #1
+ 2944              	.LVL322:
+1098:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2945              		.loc 1 1098 7 view .LVU937
+ 2946 005c 24D0     		beq	.L235
+1098:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2947              		.loc 1 1098 24 discriminator 1 view .LVU938
+ 2948 005e 1AF90830 		ldrsb	r3, [r10, r8]
+1098:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2949              		.loc 1 1098 27 discriminator 1 view .LVU939
+ 2950 0062 03F00F03 		and	r3, r3, #15
+1098:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2951              		.loc 1 1098 48 discriminator 1 view .LVU940
+ 2952 0066 3A01     		lsls	r2, r7, #4
+ 2953 0068 02F47F62 		and	r2, r2, #4080
+1098:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2954              		.loc 1 1098 35 discriminator 1 view .LVU941
+ 2955 006c 1343     		orrs	r3, r3, r2
+1098:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2956              		.loc 1 1098 7 discriminator 1 view .LVU942
+ 2957 006e DBB2     		uxtb	r3, r3
+ 2958              	.L236:
+1098:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2959              		.loc 1 1098 7 discriminator 4 view .LVU943
+ 2960 0070 0AF80830 		strb	r3, [r10, r8]
+1099:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ 2961              		.loc 1 1099 4 is_stmt 1 discriminator 4 view .LVU944
+1099:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ 2962              		.loc 1 1099 14 is_stmt 0 discriminator 4 view .LVU945
+ 2963 0074 0123     		movs	r3, #1
+ 2964 0076 E370     		strb	r3, [r4, #3]
+1100:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 2965              		.loc 1 1100 4 is_stmt 1 discriminator 4 view .LVU946
+1100:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 2966              		.loc 1 1100 28 is_stmt 0 discriminator 4 view .LVU947
+ 2967 0078 616A     		ldr	r1, [r4, #36]
+1100:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 2968              		.loc 1 1100 46 discriminator 4 view .LVU948
+ 2969 007a A389     		ldrh	r3, [r4, #12]
+1100:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 2970              		.loc 1 1100 44 discriminator 4 view .LVU949
+ 2971 007c B9FBF3F3 		udiv	r3, r9, r3
+1100:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 2972              		.loc 1 1100 10 discriminator 4 view .LVU950
+ 2973 0080 1944     		add	r1, r1, r3
+ 2974 0082 2046     		mov	r0, r4
+ARM GAS  /tmp/cc5lWXRL.s 			page 168
+
+
+ 2975              	.LVL323:
+1100:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 2976              		.loc 1 1100 10 discriminator 4 view .LVU951
+ 2977 0084 FFF7FEFF 		bl	move_window
+ 2978              	.LVL324:
+1101:Middlewares/Third_Party/FatFs/src/ff.c **** 			p = fs->win + bc % SS(fs);
+ 2979              		.loc 1 1101 4 is_stmt 1 discriminator 4 view .LVU952
+1101:Middlewares/Third_Party/FatFs/src/ff.c **** 			p = fs->win + bc % SS(fs);
+ 2980              		.loc 1 1101 7 is_stmt 0 discriminator 4 view .LVU953
+ 2981 0088 0646     		mov	r6, r0
+ 2982 008a 0028     		cmp	r0, #0
+ 2983 008c CCD1     		bne	.L232
+1102:Middlewares/Third_Party/FatFs/src/ff.c **** 			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+ 2984              		.loc 1 1102 4 is_stmt 1 view .LVU954
+1102:Middlewares/Third_Party/FatFs/src/ff.c **** 			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+ 2985              		.loc 1 1102 23 is_stmt 0 view .LVU955
+ 2986 008e A389     		ldrh	r3, [r4, #12]
+1102:Middlewares/Third_Party/FatFs/src/ff.c **** 			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+ 2987              		.loc 1 1102 21 view .LVU956
+ 2988 0090 B9FBF3F2 		udiv	r2, r9, r3
+ 2989 0094 03FB1299 		mls	r9, r3, r2, r9
+ 2990              	.LVL325:
+1103:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2991              		.loc 1 1103 4 is_stmt 1 view .LVU957
+1103:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2992              		.loc 1 1103 7 is_stmt 0 view .LVU958
+ 2993 0098 45B1     		cbz	r5, .L237
+1103:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2994              		.loc 1 1103 7 discriminator 1 view .LVU959
+ 2995 009a C7F30712 		ubfx	r2, r7, #4, #8
+ 2996              	.LVL326:
+ 2997              	.L238:
+1103:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 2998              		.loc 1 1103 7 discriminator 4 view .LVU960
+ 2999 009e 0AF80920 		strb	r2, [r10, r9]
+1104:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3000              		.loc 1 1104 4 is_stmt 1 discriminator 4 view .LVU961
+1104:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3001              		.loc 1 1104 14 is_stmt 0 discriminator 4 view .LVU962
+ 3002 00a2 0123     		movs	r3, #1
+ 3003 00a4 E370     		strb	r3, [r4, #3]
+1105:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3004              		.loc 1 1105 4 is_stmt 1 discriminator 4 view .LVU963
+ 3005 00a6 BFE7     		b	.L232
+ 3006              	.LVL327:
+ 3007              	.L235:
+1098:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3008              		.loc 1 1098 7 is_stmt 0 discriminator 2 view .LVU964
+ 3009 00a8 FBB2     		uxtb	r3, r7
+ 3010 00aa E1E7     		b	.L236
+ 3011              	.LVL328:
+ 3012              	.L237:
+1103:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3013              		.loc 1 1103 43 discriminator 2 view .LVU965
+ 3014 00ac 1AF90920 		ldrsb	r2, [r10, r9]
+1103:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3015              		.loc 1 1103 46 discriminator 2 view .LVU966
+ARM GAS  /tmp/cc5lWXRL.s 			page 169
+
+
+ 3016 00b0 22F00F02 		bic	r2, r2, #15
+1103:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3017              		.loc 1 1103 74 discriminator 2 view .LVU967
+ 3018 00b4 C7F30327 		ubfx	r7, r7, #8, #4
+ 3019              	.LVL329:
+1103:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3020              		.loc 1 1103 54 discriminator 2 view .LVU968
+ 3021 00b8 3A43     		orrs	r2, r2, r7
+1103:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3022              		.loc 1 1103 7 discriminator 2 view .LVU969
+ 3023 00ba D2B2     		uxtb	r2, r2
+ 3024 00bc EFE7     		b	.L238
+ 3025              	.LVL330:
+ 3026              	.L233:
+1108:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3027              		.loc 1 1108 4 is_stmt 1 view .LVU970
+1108:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3028              		.loc 1 1108 28 is_stmt 0 view .LVU971
+ 3029 00be 416A     		ldr	r1, [r0, #36]
+ 3030              	.LVL331:
+1108:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3031              		.loc 1 1108 49 view .LVU972
+ 3032 00c0 8389     		ldrh	r3, [r0, #12]
+1108:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3033              		.loc 1 1108 56 view .LVU973
+ 3034 00c2 5B08     		lsrs	r3, r3, #1
+1108:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3035              		.loc 1 1108 46 view .LVU974
+ 3036 00c4 B5FBF3F3 		udiv	r3, r5, r3
+1108:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3037              		.loc 1 1108 10 view .LVU975
+ 3038 00c8 1944     		add	r1, r1, r3
+ 3039 00ca FFF7FEFF 		bl	move_window
+ 3040              	.LVL332:
+1109:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(fs->win + clst * 2 % SS(fs), (WORD)val);
+ 3041              		.loc 1 1109 4 is_stmt 1 view .LVU976
+1109:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(fs->win + clst * 2 % SS(fs), (WORD)val);
+ 3042              		.loc 1 1109 7 is_stmt 0 view .LVU977
+ 3043 00ce 0646     		mov	r6, r0
+ 3044 00d0 0028     		cmp	r0, #0
+ 3045 00d2 A9D1     		bne	.L232
+1110:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3046              		.loc 1 1110 4 is_stmt 1 view .LVU978
+1110:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3047              		.loc 1 1110 12 is_stmt 0 view .LVU979
+ 3048 00d4 04F13400 		add	r0, r4, #52
+ 3049              	.LVL333:
+1110:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3050              		.loc 1 1110 27 view .LVU980
+ 3051 00d8 6D00     		lsls	r5, r5, #1
+ 3052              	.LVL334:
+1110:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3053              		.loc 1 1110 33 view .LVU981
+ 3054 00da A389     		ldrh	r3, [r4, #12]
+1110:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3055              		.loc 1 1110 31 view .LVU982
+ 3056 00dc B5FBF3F2 		udiv	r2, r5, r3
+ARM GAS  /tmp/cc5lWXRL.s 			page 170
+
+
+ 3057 00e0 03FB1255 		mls	r5, r3, r2, r5
+1110:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3058              		.loc 1 1110 4 view .LVU983
+ 3059 00e4 B9B2     		uxth	r1, r7
+ 3060 00e6 2844     		add	r0, r0, r5
+ 3061 00e8 FFF7FEFF 		bl	st_word
+ 3062              	.LVL335:
+1111:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3063              		.loc 1 1111 4 is_stmt 1 view .LVU984
+1111:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3064              		.loc 1 1111 14 is_stmt 0 view .LVU985
+ 3065 00ec 0123     		movs	r3, #1
+ 3066 00ee E370     		strb	r3, [r4, #3]
+1112:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3067              		.loc 1 1112 4 is_stmt 1 view .LVU986
+ 3068 00f0 9AE7     		b	.L232
+ 3069              	.LVL336:
+ 3070              	.L234:
+1118:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3071              		.loc 1 1118 4 view .LVU987
+1118:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3072              		.loc 1 1118 28 is_stmt 0 view .LVU988
+ 3073 00f2 416A     		ldr	r1, [r0, #36]
+ 3074              	.LVL337:
+1118:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3075              		.loc 1 1118 49 view .LVU989
+ 3076 00f4 8389     		ldrh	r3, [r0, #12]
+1118:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3077              		.loc 1 1118 56 view .LVU990
+ 3078 00f6 9B08     		lsrs	r3, r3, #2
+1118:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3079              		.loc 1 1118 46 view .LVU991
+ 3080 00f8 B5FBF3F3 		udiv	r3, r5, r3
+1118:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 3081              		.loc 1 1118 10 view .LVU992
+ 3082 00fc 1944     		add	r1, r1, r3
+ 3083 00fe FFF7FEFF 		bl	move_window
+ 3084              	.LVL338:
+1119:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+ 3085              		.loc 1 1119 4 is_stmt 1 view .LVU993
+1119:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+ 3086              		.loc 1 1119 7 is_stmt 0 view .LVU994
+ 3087 0102 0646     		mov	r6, r0
+ 3088 0104 0028     		cmp	r0, #0
+ 3089 0106 8FD1     		bne	.L232
+1120:Middlewares/Third_Party/FatFs/src/ff.c **** 				val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000);
+ 3090              		.loc 1 1120 4 is_stmt 1 view .LVU995
+1121:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 3091              		.loc 1 1121 5 view .LVU996
+1121:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 3092              		.loc 1 1121 16 is_stmt 0 view .LVU997
+ 3093 0108 27F07047 		bic	r7, r7, #-268435456
+ 3094              	.LVL339:
+1121:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 3095              		.loc 1 1121 42 view .LVU998
+ 3096 010c 04F13403 		add	r3, r4, #52
+1121:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ARM GAS  /tmp/cc5lWXRL.s 			page 171
+
+
+ 3097              		.loc 1 1121 57 view .LVU999
+ 3098 0110 AD00     		lsls	r5, r5, #2
+ 3099              	.LVL340:
+1121:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 3100              		.loc 1 1121 63 view .LVU1000
+ 3101 0112 A289     		ldrh	r2, [r4, #12]
+1121:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 3102              		.loc 1 1121 61 view .LVU1001
+ 3103 0114 B5FBF2F1 		udiv	r1, r5, r2
+ 3104 0118 02FB1155 		mls	r5, r2, r1, r5
+1121:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 3105              		.loc 1 1121 33 view .LVU1002
+ 3106 011c 1D44     		add	r5, r5, r3
+ 3107 011e 2846     		mov	r0, r5
+ 3108              	.LVL341:
+1121:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 3109              		.loc 1 1121 33 view .LVU1003
+ 3110 0120 FFF7FEFF 		bl	ld_dword
+ 3111              	.LVL342:
+1121:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 3112              		.loc 1 1121 71 view .LVU1004
+ 3113 0124 00F07041 		and	r1, r0, #-268435456
+ 3114              	.LVL343:
+1123:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3115              		.loc 1 1123 4 is_stmt 1 view .LVU1005
+ 3116 0128 3943     		orrs	r1, r1, r7
+ 3117              	.LVL344:
+1123:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->wflag = 1;
+ 3118              		.loc 1 1123 4 is_stmt 0 view .LVU1006
+ 3119 012a 2846     		mov	r0, r5
+ 3120 012c FFF7FEFF 		bl	st_dword
+ 3121              	.LVL345:
+1124:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3122              		.loc 1 1124 4 is_stmt 1 view .LVU1007
+1124:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3123              		.loc 1 1124 14 is_stmt 0 view .LVU1008
+ 3124 0130 0123     		movs	r3, #1
+ 3125 0132 E370     		strb	r3, [r4, #3]
+1125:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3126              		.loc 1 1125 4 is_stmt 1 view .LVU1009
+ 3127 0134 78E7     		b	.L232
+ 3128              	.LVL346:
+ 3129              	.L239:
+1089:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3130              		.loc 1 1089 10 is_stmt 0 view .LVU1010
+ 3131 0136 0226     		movs	r6, #2
+ 3132 0138 76E7     		b	.L232
+ 3133              	.L240:
+1089:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3134              		.loc 1 1089 10 view .LVU1011
+ 3135 013a 0226     		movs	r6, #2
+ 3136 013c 74E7     		b	.L232
+ 3137              		.cfi_endproc
+ 3138              	.LFE1201:
+ 3140              		.section	.text.get_fat,"ax",%progbits
+ 3141              		.align	1
+ 3142              		.syntax unified
+ARM GAS  /tmp/cc5lWXRL.s 			page 172
+
+
+ 3143              		.thumb
+ 3144              		.thumb_func
+ 3145              		.fpu fpv5-d16
+ 3147              	get_fat:
+ 3148              	.LVL347:
+ 3149              	.LFB1200:
+1005:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT wc, bc;
+ 3150              		.loc 1 1005 1 is_stmt 1 view -0
+ 3151              		.cfi_startproc
+ 3152              		@ args = 0, pretend = 0, frame = 0
+ 3153              		@ frame_needed = 0, uses_anonymous_args = 0
+1005:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT wc, bc;
+ 3154              		.loc 1 1005 1 is_stmt 0 view .LVU1013
+ 3155 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 3156              	.LCFI23:
+ 3157              		.cfi_def_cfa_offset 24
+ 3158              		.cfi_offset 3, -24
+ 3159              		.cfi_offset 4, -20
+ 3160              		.cfi_offset 5, -16
+ 3161              		.cfi_offset 6, -12
+ 3162              		.cfi_offset 7, -8
+ 3163              		.cfi_offset 14, -4
+1006:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD val;
+ 3164              		.loc 1 1006 2 is_stmt 1 view .LVU1014
+1007:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = obj->fs;
+ 3165              		.loc 1 1007 2 view .LVU1015
+1008:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3166              		.loc 1 1008 2 view .LVU1016
+1008:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3167              		.loc 1 1008 9 is_stmt 0 view .LVU1017
+ 3168 0002 0568     		ldr	r5, [r0]
+ 3169              	.LVL348:
+1011:Middlewares/Third_Party/FatFs/src/ff.c **** 		val = 1;	/* Internal error */
+ 3170              		.loc 1 1011 2 is_stmt 1 view .LVU1018
+1011:Middlewares/Third_Party/FatFs/src/ff.c **** 		val = 1;	/* Internal error */
+ 3171              		.loc 1 1011 5 is_stmt 0 view .LVU1019
+ 3172 0004 0129     		cmp	r1, #1
+ 3173 0006 6CD9     		bls	.L249
+ 3174 0008 0C46     		mov	r4, r1
+1011:Middlewares/Third_Party/FatFs/src/ff.c **** 		val = 1;	/* Internal error */
+ 3175              		.loc 1 1011 28 discriminator 1 view .LVU1020
+ 3176 000a AB69     		ldr	r3, [r5, #24]
+1011:Middlewares/Third_Party/FatFs/src/ff.c **** 		val = 1;	/* Internal error */
+ 3177              		.loc 1 1011 15 discriminator 1 view .LVU1021
+ 3178 000c 8B42     		cmp	r3, r1
+ 3179 000e 6AD9     		bls	.L250
+1015:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3180              		.loc 1 1015 3 is_stmt 1 view .LVU1022
+ 3181              	.LVL349:
+1017:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT12 :
+ 3182              		.loc 1 1017 3 view .LVU1023
+1017:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT12 :
+ 3183              		.loc 1 1017 13 is_stmt 0 view .LVU1024
+ 3184 0010 2B78     		ldrb	r3, [r5]	@ zero_extendqisi2
+1017:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT12 :
+ 3185              		.loc 1 1017 3 view .LVU1025
+ 3186 0012 022B     		cmp	r3, #2
+ARM GAS  /tmp/cc5lWXRL.s 			page 173
+
+
+ 3187 0014 37D0     		beq	.L246
+ 3188 0016 032B     		cmp	r3, #3
+ 3189 0018 4BD0     		beq	.L247
+ 3190 001a 012B     		cmp	r3, #1
+ 3191 001c 01D0     		beq	.L257
+ 3192 001e 0120     		movs	r0, #1
+ 3193              	.LVL350:
+1017:Middlewares/Third_Party/FatFs/src/ff.c **** 		case FS_FAT12 :
+ 3194              		.loc 1 1017 3 view .LVU1026
+ 3195 0020 60E0     		b	.L244
+ 3196              	.LVL351:
+ 3197              	.L257:
+1019:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+ 3198              		.loc 1 1019 4 is_stmt 1 view .LVU1027
+1019:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+ 3199              		.loc 1 1019 21 view .LVU1028
+1019:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+ 3200              		.loc 1 1019 24 is_stmt 0 view .LVU1029
+ 3201 0022 01EB5106 		add	r6, r1, r1, lsr #1
+ 3202              	.LVL352:
+1020:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc = fs->win[bc++ % SS(fs)];
+ 3203              		.loc 1 1020 4 is_stmt 1 view .LVU1030
+1020:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc = fs->win[bc++ % SS(fs)];
+ 3204              		.loc 1 1020 26 is_stmt 0 view .LVU1031
+ 3205 0026 696A     		ldr	r1, [r5, #36]
+ 3206              	.LVL353:
+1020:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc = fs->win[bc++ % SS(fs)];
+ 3207              		.loc 1 1020 44 view .LVU1032
+ 3208 0028 AB89     		ldrh	r3, [r5, #12]
+1020:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc = fs->win[bc++ % SS(fs)];
+ 3209              		.loc 1 1020 42 view .LVU1033
+ 3210 002a B6FBF3F3 		udiv	r3, r6, r3
+1020:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc = fs->win[bc++ % SS(fs)];
+ 3211              		.loc 1 1020 8 view .LVU1034
+ 3212 002e 1944     		add	r1, r1, r3
+ 3213 0030 2846     		mov	r0, r5
+ 3214              	.LVL354:
+1020:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc = fs->win[bc++ % SS(fs)];
+ 3215              		.loc 1 1020 8 view .LVU1035
+ 3216 0032 FFF7FEFF 		bl	move_window
+ 3217              	.LVL355:
+1020:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc = fs->win[bc++ % SS(fs)];
+ 3218              		.loc 1 1020 7 view .LVU1036
+ 3219 0036 10B1     		cbz	r0, .L258
+1015:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3220              		.loc 1 1015 7 view .LVU1037
+ 3221 0038 4FF0FF30 		mov	r0, #-1
+ 3222 003c 52E0     		b	.L244
+ 3223              	.L258:
+1021:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+ 3224              		.loc 1 1021 4 is_stmt 1 view .LVU1038
+1021:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+ 3225              		.loc 1 1021 19 is_stmt 0 view .LVU1039
+ 3226 003e 771C     		adds	r7, r6, #1
+ 3227              	.LVL356:
+1021:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+ 3228              		.loc 1 1021 24 view .LVU1040
+ARM GAS  /tmp/cc5lWXRL.s 			page 174
+
+
+ 3229 0040 AB89     		ldrh	r3, [r5, #12]
+1021:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+ 3230              		.loc 1 1021 22 view .LVU1041
+ 3231 0042 B6FBF3F2 		udiv	r2, r6, r3
+ 3232 0046 03FB1266 		mls	r6, r3, r2, r6
+1021:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+ 3233              		.loc 1 1021 16 view .LVU1042
+ 3234 004a 2E44     		add	r6, r6, r5
+ 3235 004c 96F83460 		ldrb	r6, [r6, #52]	@ zero_extendqisi2
+ 3236              	.LVL357:
+1022:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc |= fs->win[bc % SS(fs)] << 8;
+ 3237              		.loc 1 1022 4 is_stmt 1 view .LVU1043
+1022:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc |= fs->win[bc % SS(fs)] << 8;
+ 3238              		.loc 1 1022 26 is_stmt 0 view .LVU1044
+ 3239 0050 696A     		ldr	r1, [r5, #36]
+1022:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc |= fs->win[bc % SS(fs)] << 8;
+ 3240              		.loc 1 1022 42 view .LVU1045
+ 3241 0052 B7FBF3F3 		udiv	r3, r7, r3
+1022:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc |= fs->win[bc % SS(fs)] << 8;
+ 3242              		.loc 1 1022 8 view .LVU1046
+ 3243 0056 1944     		add	r1, r1, r3
+ 3244 0058 2846     		mov	r0, r5
+ 3245 005a FFF7FEFF 		bl	move_window
+ 3246              	.LVL358:
+1022:Middlewares/Third_Party/FatFs/src/ff.c **** 			wc |= fs->win[bc % SS(fs)] << 8;
+ 3247              		.loc 1 1022 7 view .LVU1047
+ 3248 005e 0028     		cmp	r0, #0
+ 3249 0060 43D1     		bne	.L253
+1023:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+ 3250              		.loc 1 1023 4 is_stmt 1 view .LVU1048
+1023:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+ 3251              		.loc 1 1023 23 is_stmt 0 view .LVU1049
+ 3252 0062 AB89     		ldrh	r3, [r5, #12]
+1023:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+ 3253              		.loc 1 1023 21 view .LVU1050
+ 3254 0064 B7FBF3F2 		udiv	r2, r7, r3
+ 3255 0068 03FB1277 		mls	r7, r3, r2, r7
+ 3256              	.LVL359:
+1023:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+ 3257              		.loc 1 1023 17 view .LVU1051
+ 3258 006c 3D44     		add	r5, r5, r7
+ 3259              	.LVL360:
+1023:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+ 3260              		.loc 1 1023 17 view .LVU1052
+ 3261 006e 95F83400 		ldrb	r0, [r5, #52]	@ zero_extendqisi2
+1023:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+ 3262              		.loc 1 1023 7 view .LVU1053
+ 3263 0072 46EA0020 		orr	r0, r6, r0, lsl #8
+ 3264              	.LVL361:
+1024:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3265              		.loc 1 1024 4 is_stmt 1 view .LVU1054
+1024:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3266              		.loc 1 1024 33 is_stmt 0 view .LVU1055
+ 3267 0076 14F0010F 		tst	r4, #1
+ 3268 007a 01D0     		beq	.L248
+1024:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3269              		.loc 1 1024 33 discriminator 1 view .LVU1056
+ARM GAS  /tmp/cc5lWXRL.s 			page 175
+
+
+ 3270 007c 0009     		lsrs	r0, r0, #4
+ 3271              	.LVL362:
+1024:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3272              		.loc 1 1024 33 discriminator 1 view .LVU1057
+ 3273 007e 31E0     		b	.L244
+ 3274              	.LVL363:
+ 3275              	.L248:
+1024:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3276              		.loc 1 1024 33 discriminator 2 view .LVU1058
+ 3277 0080 C0F30B00 		ubfx	r0, r0, #0, #12
+ 3278              	.LVL364:
+1024:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3279              		.loc 1 1024 33 discriminator 2 view .LVU1059
+ 3280 0084 2EE0     		b	.L244
+ 3281              	.LVL365:
+ 3282              	.L246:
+1028:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_word(fs->win + clst * 2 % SS(fs));
+ 3283              		.loc 1 1028 4 is_stmt 1 view .LVU1060
+1028:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_word(fs->win + clst * 2 % SS(fs));
+ 3284              		.loc 1 1028 26 is_stmt 0 view .LVU1061
+ 3285 0086 696A     		ldr	r1, [r5, #36]
+ 3286              	.LVL366:
+1028:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_word(fs->win + clst * 2 % SS(fs));
+ 3287              		.loc 1 1028 47 view .LVU1062
+ 3288 0088 AB89     		ldrh	r3, [r5, #12]
+1028:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_word(fs->win + clst * 2 % SS(fs));
+ 3289              		.loc 1 1028 54 view .LVU1063
+ 3290 008a 5B08     		lsrs	r3, r3, #1
+1028:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_word(fs->win + clst * 2 % SS(fs));
+ 3291              		.loc 1 1028 44 view .LVU1064
+ 3292 008c B4FBF3F3 		udiv	r3, r4, r3
+1028:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_word(fs->win + clst * 2 % SS(fs));
+ 3293              		.loc 1 1028 8 view .LVU1065
+ 3294 0090 1944     		add	r1, r1, r3
+ 3295 0092 2846     		mov	r0, r5
+ 3296              	.LVL367:
+1028:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_word(fs->win + clst * 2 % SS(fs));
+ 3297              		.loc 1 1028 8 view .LVU1066
+ 3298 0094 FFF7FEFF 		bl	move_window
+ 3299              	.LVL368:
+1028:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_word(fs->win + clst * 2 % SS(fs));
+ 3300              		.loc 1 1028 7 view .LVU1067
+ 3301 0098 50BB     		cbnz	r0, .L254
+1029:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3302              		.loc 1 1029 4 is_stmt 1 view .LVU1068
+1029:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3303              		.loc 1 1029 18 is_stmt 0 view .LVU1069
+ 3304 009a 05F13400 		add	r0, r5, #52
+1029:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3305              		.loc 1 1029 33 view .LVU1070
+ 3306 009e 6400     		lsls	r4, r4, #1
+ 3307              	.LVL369:
+1029:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3308              		.loc 1 1029 39 view .LVU1071
+ 3309 00a0 AB89     		ldrh	r3, [r5, #12]
+1029:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3310              		.loc 1 1029 37 view .LVU1072
+ARM GAS  /tmp/cc5lWXRL.s 			page 176
+
+
+ 3311 00a2 B4FBF3F2 		udiv	r2, r4, r3
+ 3312 00a6 03FB1244 		mls	r4, r3, r2, r4
+1029:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3313              		.loc 1 1029 10 view .LVU1073
+ 3314 00aa 2044     		add	r0, r0, r4
+ 3315 00ac FFF7FEFF 		bl	ld_word
+ 3316              	.LVL370:
+1030:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3317              		.loc 1 1030 4 is_stmt 1 view .LVU1074
+ 3318 00b0 18E0     		b	.L244
+ 3319              	.LVL371:
+ 3320              	.L247:
+1033:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+ 3321              		.loc 1 1033 4 view .LVU1075
+1033:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+ 3322              		.loc 1 1033 26 is_stmt 0 view .LVU1076
+ 3323 00b2 696A     		ldr	r1, [r5, #36]
+ 3324              	.LVL372:
+1033:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+ 3325              		.loc 1 1033 47 view .LVU1077
+ 3326 00b4 AB89     		ldrh	r3, [r5, #12]
+1033:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+ 3327              		.loc 1 1033 54 view .LVU1078
+ 3328 00b6 9B08     		lsrs	r3, r3, #2
+1033:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+ 3329              		.loc 1 1033 44 view .LVU1079
+ 3330 00b8 B4FBF3F3 		udiv	r3, r4, r3
+1033:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+ 3331              		.loc 1 1033 8 view .LVU1080
+ 3332 00bc 1944     		add	r1, r1, r3
+ 3333 00be 2846     		mov	r0, r5
+ 3334              	.LVL373:
+1033:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+ 3335              		.loc 1 1033 8 view .LVU1081
+ 3336 00c0 FFF7FEFF 		bl	move_window
+ 3337              	.LVL374:
+1033:Middlewares/Third_Party/FatFs/src/ff.c **** 			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+ 3338              		.loc 1 1033 7 view .LVU1082
+ 3339 00c4 B8B9     		cbnz	r0, .L255
+1034:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3340              		.loc 1 1034 4 is_stmt 1 view .LVU1083
+1034:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3341              		.loc 1 1034 19 is_stmt 0 view .LVU1084
+ 3342 00c6 05F13400 		add	r0, r5, #52
+1034:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3343              		.loc 1 1034 34 view .LVU1085
+ 3344 00ca A400     		lsls	r4, r4, #2
+ 3345              	.LVL375:
+1034:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3346              		.loc 1 1034 40 view .LVU1086
+ 3347 00cc AB89     		ldrh	r3, [r5, #12]
+1034:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3348              		.loc 1 1034 38 view .LVU1087
+ 3349 00ce B4FBF3F2 		udiv	r2, r4, r3
+ 3350 00d2 03FB1244 		mls	r4, r3, r2, r4
+1034:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3351              		.loc 1 1034 10 view .LVU1088
+ARM GAS  /tmp/cc5lWXRL.s 			page 177
+
+
+ 3352 00d6 2044     		add	r0, r0, r4
+ 3353 00d8 FFF7FEFF 		bl	ld_dword
+ 3354              	.LVL376:
+1034:Middlewares/Third_Party/FatFs/src/ff.c **** 			break;
+ 3355              		.loc 1 1034 8 view .LVU1089
+ 3356 00dc 20F07040 		bic	r0, r0, #-268435456
+ 3357              	.LVL377:
+1035:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 3358              		.loc 1 1035 4 is_stmt 1 view .LVU1090
+ 3359 00e0 00E0     		b	.L244
+ 3360              	.LVL378:
+ 3361              	.L249:
+1012:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3362              		.loc 1 1012 7 is_stmt 0 view .LVU1091
+ 3363 00e2 0120     		movs	r0, #1
+ 3364              	.LVL379:
+ 3365              	.L244:
+1070:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3366              		.loc 1 1070 1 view .LVU1092
+ 3367 00e4 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 3368              	.LVL380:
+ 3369              	.L250:
+1012:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3370              		.loc 1 1012 7 view .LVU1093
+ 3371 00e6 0120     		movs	r0, #1
+ 3372              	.LVL381:
+1012:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3373              		.loc 1 1012 7 view .LVU1094
+ 3374 00e8 FCE7     		b	.L244
+ 3375              	.LVL382:
+ 3376              	.L253:
+1015:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3377              		.loc 1 1015 7 view .LVU1095
+ 3378 00ea 4FF0FF30 		mov	r0, #-1
+ 3379 00ee F9E7     		b	.L244
+ 3380              	.LVL383:
+ 3381              	.L254:
+1015:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3382              		.loc 1 1015 7 view .LVU1096
+ 3383 00f0 4FF0FF30 		mov	r0, #-1
+ 3384 00f4 F6E7     		b	.L244
+ 3385              	.L255:
+1015:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3386              		.loc 1 1015 7 view .LVU1097
+ 3387 00f6 4FF0FF30 		mov	r0, #-1
+1069:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 3388              		.loc 1 1069 2 is_stmt 1 view .LVU1098
+1069:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 3389              		.loc 1 1069 9 is_stmt 0 view .LVU1099
+ 3390 00fa F3E7     		b	.L244
+ 3391              		.cfi_endproc
+ 3392              	.LFE1200:
+ 3394              		.section	.text.dir_sdi,"ax",%progbits
+ 3395              		.align	1
+ 3396              		.syntax unified
+ 3397              		.thumb
+ 3398              		.thumb_func
+ARM GAS  /tmp/cc5lWXRL.s 			page 178
+
+
+ 3399              		.fpu fpv5-d16
+ 3401              	dir_sdi:
+ 3402              	.LVL384:
+ 3403              	.LFB1205:
+1474:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD csz, clst;
+ 3404              		.loc 1 1474 1 is_stmt 1 view -0
+ 3405              		.cfi_startproc
+ 3406              		@ args = 0, pretend = 0, frame = 0
+ 3407              		@ frame_needed = 0, uses_anonymous_args = 0
+1474:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD csz, clst;
+ 3408              		.loc 1 1474 1 is_stmt 0 view .LVU1101
+ 3409 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 3410              	.LCFI24:
+ 3411              		.cfi_def_cfa_offset 24
+ 3412              		.cfi_offset 4, -24
+ 3413              		.cfi_offset 5, -20
+ 3414              		.cfi_offset 6, -16
+ 3415              		.cfi_offset 7, -12
+ 3416              		.cfi_offset 8, -8
+ 3417              		.cfi_offset 14, -4
+1475:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+ 3418              		.loc 1 1475 2 is_stmt 1 view .LVU1102
+1476:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3419              		.loc 1 1476 2 view .LVU1103
+1476:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3420              		.loc 1 1476 9 is_stmt 0 view .LVU1104
+ 3421 0004 D0F80080 		ldr	r8, [r0]
+ 3422              	.LVL385:
+1479:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_INT_ERR;
+ 3423              		.loc 1 1479 2 is_stmt 1 view .LVU1105
+1479:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_INT_ERR;
+ 3424              		.loc 1 1479 5 is_stmt 0 view .LVU1106
+ 3425 0008 B1F5001F 		cmp	r1, #2097152
+ 3426 000c 4AD2     		bcs	.L266
+ 3427 000e 0746     		mov	r7, r0
+ 3428 0010 0E46     		mov	r6, r1
+1479:Middlewares/Third_Party/FatFs/src/ff.c **** 		return FR_INT_ERR;
+ 3429              		.loc 1 1479 84 discriminator 1 view .LVU1107
+ 3430 0012 11F01F0F 		tst	r1, #31
+ 3431 0016 47D1     		bne	.L267
+1482:Middlewares/Third_Party/FatFs/src/ff.c **** 	clst = dp->obj.sclust;		/* Table start cluster (0:root) */
+ 3432              		.loc 1 1482 2 is_stmt 1 view .LVU1108
+1482:Middlewares/Third_Party/FatFs/src/ff.c **** 	clst = dp->obj.sclust;		/* Table start cluster (0:root) */
+ 3433              		.loc 1 1482 11 is_stmt 0 view .LVU1109
+ 3434 0018 4161     		str	r1, [r0, #20]
+1483:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (clst == 0 && fs->fs_type >= FS_FAT32) {	/* Replace cluster# 0 with root cluster# */
+ 3435              		.loc 1 1483 2 is_stmt 1 view .LVU1110
+1483:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (clst == 0 && fs->fs_type >= FS_FAT32) {	/* Replace cluster# 0 with root cluster# */
+ 3436              		.loc 1 1483 7 is_stmt 0 view .LVU1111
+ 3437 001a 8468     		ldr	r4, [r0, #8]
+ 3438              	.LVL386:
+1484:Middlewares/Third_Party/FatFs/src/ff.c **** 		clst = fs->dirbase;
+ 3439              		.loc 1 1484 2 is_stmt 1 view .LVU1112
+1484:Middlewares/Third_Party/FatFs/src/ff.c **** 		clst = fs->dirbase;
+ 3440              		.loc 1 1484 5 is_stmt 0 view .LVU1113
+ 3441 001c 2CB9     		cbnz	r4, .L261
+1484:Middlewares/Third_Party/FatFs/src/ff.c **** 		clst = fs->dirbase;
+ARM GAS  /tmp/cc5lWXRL.s 			page 179
+
+
+ 3442              		.loc 1 1484 21 discriminator 1 view .LVU1114
+ 3443 001e 98F80030 		ldrb	r3, [r8]	@ zero_extendqisi2
+1484:Middlewares/Third_Party/FatFs/src/ff.c **** 		clst = fs->dirbase;
+ 3444              		.loc 1 1484 16 discriminator 1 view .LVU1115
+ 3445 0022 022B     		cmp	r3, #2
+ 3446 0024 01D9     		bls	.L261
+1485:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_EXFAT) dp->obj.stat = 0;	/* exFAT: Root dir has an FAT chain */
+ 3447              		.loc 1 1485 3 is_stmt 1 view .LVU1116
+1485:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_EXFAT) dp->obj.stat = 0;	/* exFAT: Root dir has an FAT chain */
+ 3448              		.loc 1 1485 8 is_stmt 0 view .LVU1117
+ 3449 0026 D8F82840 		ldr	r4, [r8, #40]
+ 3450              	.LVL387:
+1486:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3451              		.loc 1 1486 3 is_stmt 1 view .LVU1118
+ 3452              	.L261:
+1489:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs / SZDIRE >= fs->n_rootdir)	return FR_INT_ERR;	/* Is index out of range? */
+ 3453              		.loc 1 1489 2 view .LVU1119
+1489:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs / SZDIRE >= fs->n_rootdir)	return FR_INT_ERR;	/* Is index out of range? */
+ 3454              		.loc 1 1489 5 is_stmt 0 view .LVU1120
+ 3455 002a ECB9     		cbnz	r4, .L262
+1490:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect = fs->dirbase;
+ 3456              		.loc 1 1490 3 is_stmt 1 view .LVU1121
+1490:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect = fs->dirbase;
+ 3457              		.loc 1 1490 25 is_stmt 0 view .LVU1122
+ 3458 002c B8F80830 		ldrh	r3, [r8, #8]
+1490:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect = fs->dirbase;
+ 3459              		.loc 1 1490 6 view .LVU1123
+ 3460 0030 B3EB561F 		cmp	r3, r6, lsr #5
+ 3461 0034 3AD9     		bls	.L268
+1491:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3462              		.loc 1 1491 3 is_stmt 1 view .LVU1124
+1491:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3463              		.loc 1 1491 16 is_stmt 0 view .LVU1125
+ 3464 0036 D8F82830 		ldr	r3, [r8, #40]
+1491:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3465              		.loc 1 1491 12 view .LVU1126
+ 3466 003a FB61     		str	r3, [r7, #28]
+ 3467              	.LVL388:
+ 3468              	.L263:
+1503:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!dp->sect) return FR_INT_ERR;
+ 3469              		.loc 1 1503 2 is_stmt 1 view .LVU1127
+1503:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!dp->sect) return FR_INT_ERR;
+ 3470              		.loc 1 1503 12 is_stmt 0 view .LVU1128
+ 3471 003c BC61     		str	r4, [r7, #24]
+1504:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->sect += ofs / SS(fs);			/* Sector# of the directory entry */
+ 3472              		.loc 1 1504 2 is_stmt 1 view .LVU1129
+1504:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->sect += ofs / SS(fs);			/* Sector# of the directory entry */
+ 3473              		.loc 1 1504 9 is_stmt 0 view .LVU1130
+ 3474 003e FB69     		ldr	r3, [r7, #28]
+1504:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->sect += ofs / SS(fs);			/* Sector# of the directory entry */
+ 3475              		.loc 1 1504 5 view .LVU1131
+ 3476 0040 E3B3     		cbz	r3, .L272
+1505:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->dir = fs->win + (ofs % SS(fs));	/* Pointer to the entry in the win[] */
+ 3477              		.loc 1 1505 2 is_stmt 1 view .LVU1132
+1505:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->dir = fs->win + (ofs % SS(fs));	/* Pointer to the entry in the win[] */
+ 3478              		.loc 1 1505 20 is_stmt 0 view .LVU1133
+ 3479 0042 B8F80C20 		ldrh	r2, [r8, #12]
+ARM GAS  /tmp/cc5lWXRL.s 			page 180
+
+
+1505:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->dir = fs->win + (ofs % SS(fs));	/* Pointer to the entry in the win[] */
+ 3480              		.loc 1 1505 18 view .LVU1134
+ 3481 0046 B6FBF2F2 		udiv	r2, r6, r2
+1505:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->dir = fs->win + (ofs % SS(fs));	/* Pointer to the entry in the win[] */
+ 3482              		.loc 1 1505 11 view .LVU1135
+ 3483 004a 1344     		add	r3, r3, r2
+ 3484 004c FB61     		str	r3, [r7, #28]
+1506:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3485              		.loc 1 1506 2 is_stmt 1 view .LVU1136
+1506:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3486              		.loc 1 1506 12 is_stmt 0 view .LVU1137
+ 3487 004e 08F13403 		add	r3, r8, #52
+1506:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3488              		.loc 1 1506 29 view .LVU1138
+ 3489 0052 B8F80C10 		ldrh	r1, [r8, #12]
+1506:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3490              		.loc 1 1506 27 view .LVU1139
+ 3491 0056 B6FBF1F2 		udiv	r2, r6, r1
+ 3492 005a 01FB1261 		mls	r1, r1, r2, r6
+1506:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3493              		.loc 1 1506 20 view .LVU1140
+ 3494 005e 1944     		add	r1, r1, r3
+1506:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3495              		.loc 1 1506 10 view .LVU1141
+ 3496 0060 3962     		str	r1, [r7, #32]
+1508:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 3497              		.loc 1 1508 2 is_stmt 1 view .LVU1142
+1508:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 3498              		.loc 1 1508 9 is_stmt 0 view .LVU1143
+ 3499 0062 0020     		movs	r0, #0
+ 3500              	.LVL389:
+ 3501              	.L260:
+1509:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3502              		.loc 1 1509 1 view .LVU1144
+ 3503 0064 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 3504              	.LVL390:
+ 3505              	.L262:
+1494:Middlewares/Third_Party/FatFs/src/ff.c **** 		while (ofs >= csz) {				/* Follow cluster chain */
+ 3506              		.loc 1 1494 3 is_stmt 1 view .LVU1145
+1494:Middlewares/Third_Party/FatFs/src/ff.c **** 		while (ofs >= csz) {				/* Follow cluster chain */
+ 3507              		.loc 1 1494 18 is_stmt 0 view .LVU1146
+ 3508 0068 B8F80A50 		ldrh	r5, [r8, #10]
+1494:Middlewares/Third_Party/FatFs/src/ff.c **** 		while (ofs >= csz) {				/* Follow cluster chain */
+ 3509              		.loc 1 1494 28 view .LVU1147
+ 3510 006c B8F80C30 		ldrh	r3, [r8, #12]
+1494:Middlewares/Third_Party/FatFs/src/ff.c **** 		while (ofs >= csz) {				/* Follow cluster chain */
+ 3511              		.loc 1 1494 7 view .LVU1148
+ 3512 0070 03FB05F5 		mul	r5, r3, r5
+ 3513              	.LVL391:
+1495:Middlewares/Third_Party/FatFs/src/ff.c **** 			clst = get_fat(&dp->obj, clst);				/* Get next cluster */
+ 3514              		.loc 1 1495 3 is_stmt 1 view .LVU1149
+ 3515              	.L264:
+1495:Middlewares/Third_Party/FatFs/src/ff.c **** 			clst = get_fat(&dp->obj, clst);				/* Get next cluster */
+ 3516              		.loc 1 1495 9 view .LVU1150
+ 3517 0074 AE42     		cmp	r6, r5
+ 3518 0076 0FD3     		bcc	.L274
+1496:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+ARM GAS  /tmp/cc5lWXRL.s 			page 181
+
+
+ 3519              		.loc 1 1496 4 view .LVU1151
+1496:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+ 3520              		.loc 1 1496 11 is_stmt 0 view .LVU1152
+ 3521 0078 2146     		mov	r1, r4
+ 3522 007a 3846     		mov	r0, r7
+ 3523 007c FFF7FEFF 		bl	get_fat
+ 3524              	.LVL392:
+ 3525 0080 0446     		mov	r4, r0
+ 3526              	.LVL393:
+1497:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Reached to end of table or internal 
+ 3527              		.loc 1 1497 4 is_stmt 1 view .LVU1153
+1497:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Reached to end of table or internal 
+ 3528              		.loc 1 1497 7 is_stmt 0 view .LVU1154
+ 3529 0082 B0F1FF3F 		cmp	r0, #-1
+ 3530 0086 13D0     		beq	.L269
+1498:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs -= csz;
+ 3531              		.loc 1 1498 4 is_stmt 1 view .LVU1155
+1498:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs -= csz;
+ 3532              		.loc 1 1498 7 is_stmt 0 view .LVU1156
+ 3533 0088 0128     		cmp	r0, #1
+ 3534 008a 13D9     		bls	.L270
+1498:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs -= csz;
+ 3535              		.loc 1 1498 30 discriminator 2 view .LVU1157
+ 3536 008c D8F81830 		ldr	r3, [r8, #24]
+1498:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs -= csz;
+ 3537              		.loc 1 1498 17 discriminator 2 view .LVU1158
+ 3538 0090 8342     		cmp	r3, r0
+ 3539 0092 11D9     		bls	.L271
+1499:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3540              		.loc 1 1499 4 is_stmt 1 view .LVU1159
+1499:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3541              		.loc 1 1499 8 is_stmt 0 view .LVU1160
+ 3542 0094 761B     		subs	r6, r6, r5
+ 3543              	.LVL394:
+1499:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3544              		.loc 1 1499 8 view .LVU1161
+ 3545 0096 EDE7     		b	.L264
+ 3546              	.LVL395:
+ 3547              	.L274:
+1501:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3548              		.loc 1 1501 3 is_stmt 1 view .LVU1162
+1501:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3549              		.loc 1 1501 14 is_stmt 0 view .LVU1163
+ 3550 0098 2146     		mov	r1, r4
+ 3551 009a 4046     		mov	r0, r8
+ 3552 009c FFF7FEFF 		bl	clust2sect
+ 3553              	.LVL396:
+1501:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3554              		.loc 1 1501 12 view .LVU1164
+ 3555 00a0 F861     		str	r0, [r7, #28]
+ 3556 00a2 CBE7     		b	.L263
+ 3557              	.LVL397:
+ 3558              	.L266:
+1480:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3559              		.loc 1 1480 10 view .LVU1165
+ 3560 00a4 0220     		movs	r0, #2
+ 3561              	.LVL398:
+ARM GAS  /tmp/cc5lWXRL.s 			page 182
+
+
+1480:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3562              		.loc 1 1480 10 view .LVU1166
+ 3563 00a6 DDE7     		b	.L260
+ 3564              	.LVL399:
+ 3565              	.L267:
+1480:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3566              		.loc 1 1480 10 view .LVU1167
+ 3567 00a8 0220     		movs	r0, #2
+ 3568              	.LVL400:
+1480:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3569              		.loc 1 1480 10 view .LVU1168
+ 3570 00aa DBE7     		b	.L260
+ 3571              	.LVL401:
+ 3572              	.L268:
+1490:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect = fs->dirbase;
+ 3573              		.loc 1 1490 45 view .LVU1169
+ 3574 00ac 0220     		movs	r0, #2
+ 3575              	.LVL402:
+1490:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect = fs->dirbase;
+ 3576              		.loc 1 1490 45 view .LVU1170
+ 3577 00ae D9E7     		b	.L260
+ 3578              	.LVL403:
+ 3579              	.L269:
+1497:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Reached to end of table or internal 
+ 3580              		.loc 1 1497 35 view .LVU1171
+ 3581 00b0 0120     		movs	r0, #1
+ 3582              	.LVL404:
+1497:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Reached to end of table or internal 
+ 3583              		.loc 1 1497 35 view .LVU1172
+ 3584 00b2 D7E7     		b	.L260
+ 3585              	.LVL405:
+ 3586              	.L270:
+1498:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs -= csz;
+ 3587              		.loc 1 1498 49 view .LVU1173
+ 3588 00b4 0220     		movs	r0, #2
+ 3589              	.LVL406:
+1498:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs -= csz;
+ 3590              		.loc 1 1498 49 view .LVU1174
+ 3591 00b6 D5E7     		b	.L260
+ 3592              	.LVL407:
+ 3593              	.L271:
+1498:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs -= csz;
+ 3594              		.loc 1 1498 49 view .LVU1175
+ 3595 00b8 0220     		movs	r0, #2
+ 3596              	.LVL408:
+1498:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs -= csz;
+ 3597              		.loc 1 1498 49 view .LVU1176
+ 3598 00ba D3E7     		b	.L260
+ 3599              	.LVL409:
+ 3600              	.L272:
+1504:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->sect += ofs / SS(fs);			/* Sector# of the directory entry */
+ 3601              		.loc 1 1504 24 view .LVU1177
+ 3602 00bc 0220     		movs	r0, #2
+ 3603 00be D1E7     		b	.L260
+ 3604              		.cfi_endproc
+ 3605              	.LFE1205:
+ 3607              		.section	.text.create_chain,"ax",%progbits
+ARM GAS  /tmp/cc5lWXRL.s 			page 183
+
+
+ 3608              		.align	1
+ 3609              		.syntax unified
+ 3610              		.thumb
+ 3611              		.thumb_func
+ 3612              		.fpu fpv5-d16
+ 3614              	create_chain:
+ 3615              	.LVL410:
+ 3616              	.LFB1203:
+1355:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD cs, ncl, scl;
+ 3617              		.loc 1 1355 1 is_stmt 1 view -0
+ 3618              		.cfi_startproc
+ 3619              		@ args = 0, pretend = 0, frame = 0
+ 3620              		@ frame_needed = 0, uses_anonymous_args = 0
+1355:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD cs, ncl, scl;
+ 3621              		.loc 1 1355 1 is_stmt 0 view .LVU1179
+ 3622 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 3623              	.LCFI25:
+ 3624              		.cfi_def_cfa_offset 24
+ 3625              		.cfi_offset 4, -24
+ 3626              		.cfi_offset 5, -20
+ 3627              		.cfi_offset 6, -16
+ 3628              		.cfi_offset 7, -12
+ 3629              		.cfi_offset 8, -8
+ 3630              		.cfi_offset 14, -4
+ 3631 0004 0546     		mov	r5, r0
+1356:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 3632              		.loc 1 1356 2 is_stmt 1 view .LVU1180
+1357:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = obj->fs;
+ 3633              		.loc 1 1357 2 view .LVU1181
+1358:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3634              		.loc 1 1358 2 view .LVU1182
+1358:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3635              		.loc 1 1358 9 is_stmt 0 view .LVU1183
+ 3636 0006 0668     		ldr	r6, [r0]
+ 3637              	.LVL411:
+1361:Middlewares/Third_Party/FatFs/src/ff.c **** 		scl = fs->last_clst;				/* Get suggested cluster to start from */
+ 3638              		.loc 1 1361 2 is_stmt 1 view .LVU1184
+1361:Middlewares/Third_Party/FatFs/src/ff.c **** 		scl = fs->last_clst;				/* Get suggested cluster to start from */
+ 3639              		.loc 1 1361 5 is_stmt 0 view .LVU1185
+ 3640 0008 0F46     		mov	r7, r1
+ 3641 000a 51B9     		cbnz	r1, .L276
+1362:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (scl == 0 || scl >= fs->n_fatent) scl = 1;
+ 3642              		.loc 1 1362 3 is_stmt 1 view .LVU1186
+1362:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (scl == 0 || scl >= fs->n_fatent) scl = 1;
+ 3643              		.loc 1 1362 7 is_stmt 0 view .LVU1187
+ 3644 000c D6F81080 		ldr	r8, [r6, #16]
+ 3645              	.LVL412:
+1363:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3646              		.loc 1 1363 3 is_stmt 1 view .LVU1188
+1363:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3647              		.loc 1 1363 6 is_stmt 0 view .LVU1189
+ 3648 0010 B8F1000F 		cmp	r8, #0
+ 3649 0014 12D0     		beq	.L285
+1363:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3650              		.loc 1 1363 28 discriminator 2 view .LVU1190
+ 3651 0016 B369     		ldr	r3, [r6, #24]
+1363:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ARM GAS  /tmp/cc5lWXRL.s 			page 184
+
+
+ 3652              		.loc 1 1363 16 discriminator 2 view .LVU1191
+ 3653 0018 4345     		cmp	r3, r8
+ 3654 001a 11D8     		bhi	.L277
+1363:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3655              		.loc 1 1363 44 view .LVU1192
+ 3656 001c 4FF00108 		mov	r8, #1
+ 3657              	.LVL413:
+1363:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3658              		.loc 1 1363 44 view .LVU1193
+ 3659 0020 0EE0     		b	.L277
+ 3660              	.LVL414:
+ 3661              	.L276:
+1366:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cs < 2) return 1;				/* Invalid FAT value */
+ 3662              		.loc 1 1366 3 is_stmt 1 view .LVU1194
+1366:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cs < 2) return 1;				/* Invalid FAT value */
+ 3663              		.loc 1 1366 8 is_stmt 0 view .LVU1195
+ 3664 0022 FFF7FEFF 		bl	get_fat
+ 3665              	.LVL415:
+1366:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cs < 2) return 1;				/* Invalid FAT value */
+ 3666              		.loc 1 1366 8 view .LVU1196
+ 3667 0026 0346     		mov	r3, r0
+ 3668              	.LVL416:
+1367:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cs == 0xFFFFFFFF) return cs;	/* A disk error occurred */
+ 3669              		.loc 1 1367 3 is_stmt 1 view .LVU1197
+1367:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cs == 0xFFFFFFFF) return cs;	/* A disk error occurred */
+ 3670              		.loc 1 1367 6 is_stmt 0 view .LVU1198
+ 3671 0028 0128     		cmp	r0, #1
+ 3672 002a 4CD9     		bls	.L287
+1368:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cs < fs->n_fatent) return cs;	/* It is already followed by next cluster */
+ 3673              		.loc 1 1368 3 is_stmt 1 view .LVU1199
+1368:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cs < fs->n_fatent) return cs;	/* It is already followed by next cluster */
+ 3674              		.loc 1 1368 6 is_stmt 0 view .LVU1200
+ 3675 002c B0F1FF3F 		cmp	r0, #-1
+ 3676 0030 4ED0     		beq	.L275
+1369:Middlewares/Third_Party/FatFs/src/ff.c **** 		scl = clst;
+ 3677              		.loc 1 1369 3 is_stmt 1 view .LVU1201
+1369:Middlewares/Third_Party/FatFs/src/ff.c **** 		scl = clst;
+ 3678              		.loc 1 1369 14 is_stmt 0 view .LVU1202
+ 3679 0032 B269     		ldr	r2, [r6, #24]
+1369:Middlewares/Third_Party/FatFs/src/ff.c **** 		scl = clst;
+ 3680              		.loc 1 1369 6 view .LVU1203
+ 3681 0034 8242     		cmp	r2, r0
+ 3682 0036 4BD8     		bhi	.L275
+1370:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3683              		.loc 1 1370 7 view .LVU1204
+ 3684 0038 B846     		mov	r8, r7
+ 3685 003a 01E0     		b	.L277
+ 3686              	.LVL417:
+ 3687              	.L285:
+1363:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3688              		.loc 1 1363 44 view .LVU1205
+ 3689 003c 4FF00108 		mov	r8, #1
+ 3690              	.LVL418:
+ 3691              	.L277:
+1400:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (;;) {
+ 3692              		.loc 1 1400 3 is_stmt 1 view .LVU1206
+1400:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (;;) {
+ARM GAS  /tmp/cc5lWXRL.s 			page 185
+
+
+ 3693              		.loc 1 1400 7 is_stmt 0 view .LVU1207
+ 3694 0040 4446     		mov	r4, r8
+ 3695 0042 0CE0     		b	.L281
+ 3696              	.LVL419:
+ 3697              	.L279:
+1407:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cs == 0) break;				/* Found a free cluster */
+ 3698              		.loc 1 1407 4 is_stmt 1 view .LVU1208
+1407:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cs == 0) break;				/* Found a free cluster */
+ 3699              		.loc 1 1407 9 is_stmt 0 view .LVU1209
+ 3700 0044 2146     		mov	r1, r4
+ 3701 0046 2846     		mov	r0, r5
+ 3702 0048 FFF7FEFF 		bl	get_fat
+ 3703              	.LVL420:
+1408:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cs == 1 || cs == 0xFFFFFFFF) return cs;	/* An error occurred */
+ 3704              		.loc 1 1408 4 is_stmt 1 view .LVU1210
+1408:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cs == 1 || cs == 0xFFFFFFFF) return cs;	/* An error occurred */
+ 3705              		.loc 1 1408 7 is_stmt 0 view .LVU1211
+ 3706 004c 0346     		mov	r3, r0
+ 3707 004e 78B1     		cbz	r0, .L280
+1409:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl == scl) return 0;		/* No free cluster */
+ 3708              		.loc 1 1409 4 is_stmt 1 view .LVU1212
+1409:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl == scl) return 0;		/* No free cluster */
+ 3709              		.loc 1 1409 7 is_stmt 0 view .LVU1213
+ 3710 0050 B0F1FF3F 		cmp	r0, #-1
+ 3711 0054 18BF     		it	ne
+ 3712 0056 0128     		cmpne	r0, #1
+ 3713 0058 3AD0     		beq	.L275
+1410:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3714              		.loc 1 1410 4 is_stmt 1 view .LVU1214
+1410:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3715              		.loc 1 1410 7 is_stmt 0 view .LVU1215
+ 3716 005a 4445     		cmp	r4, r8
+ 3717 005c 37D0     		beq	.L292
+ 3718              	.LVL421:
+ 3719              	.L281:
+1401:Middlewares/Third_Party/FatFs/src/ff.c **** 			ncl++;							/* Next cluster */
+ 3720              		.loc 1 1401 3 is_stmt 1 view .LVU1216
+1402:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl >= fs->n_fatent) {		/* Check wrap-around */
+ 3721              		.loc 1 1402 4 view .LVU1217
+1402:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl >= fs->n_fatent) {		/* Check wrap-around */
+ 3722              		.loc 1 1402 7 is_stmt 0 view .LVU1218
+ 3723 005e 0134     		adds	r4, r4, #1
+ 3724              	.LVL422:
+1403:Middlewares/Third_Party/FatFs/src/ff.c **** 				ncl = 2;
+ 3725              		.loc 1 1403 4 is_stmt 1 view .LVU1219
+1403:Middlewares/Third_Party/FatFs/src/ff.c **** 				ncl = 2;
+ 3726              		.loc 1 1403 17 is_stmt 0 view .LVU1220
+ 3727 0060 B369     		ldr	r3, [r6, #24]
+1403:Middlewares/Third_Party/FatFs/src/ff.c **** 				ncl = 2;
+ 3728              		.loc 1 1403 7 view .LVU1221
+ 3729 0062 A342     		cmp	r3, r4
+ 3730 0064 EED8     		bhi	.L279
+1404:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (ncl > scl) return 0;	/* No free cluster */
+ 3731              		.loc 1 1404 5 is_stmt 1 view .LVU1222
+ 3732              	.LVL423:
+1405:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 3733              		.loc 1 1405 5 view .LVU1223
+ARM GAS  /tmp/cc5lWXRL.s 			page 186
+
+
+1405:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 3734              		.loc 1 1405 8 is_stmt 0 view .LVU1224
+ 3735 0066 B8F1010F 		cmp	r8, #1
+ 3736 006a 2ED9     		bls	.L288
+1404:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (ncl > scl) return 0;	/* No free cluster */
+ 3737              		.loc 1 1404 9 view .LVU1225
+ 3738 006c 0224     		movs	r4, #2
+ 3739 006e E9E7     		b	.L279
+ 3740              	.LVL424:
+ 3741              	.L280:
+1412:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK && clst != 0) {
+ 3742              		.loc 1 1412 3 is_stmt 1 view .LVU1226
+1412:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK && clst != 0) {
+ 3743              		.loc 1 1412 9 is_stmt 0 view .LVU1227
+ 3744 0070 4FF0FF32 		mov	r2, #-1
+ 3745 0074 2146     		mov	r1, r4
+ 3746 0076 3046     		mov	r0, r6
+ 3747              	.LVL425:
+1412:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK && clst != 0) {
+ 3748              		.loc 1 1412 9 view .LVU1228
+ 3749 0078 FFF7FEFF 		bl	put_fat
+ 3750              	.LVL426:
+1413:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = put_fat(fs, clst, ncl);	/* Link it from the previous one if needed */
+ 3751              		.loc 1 1413 3 is_stmt 1 view .LVU1229
+1413:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = put_fat(fs, clst, ncl);	/* Link it from the previous one if needed */
+ 3752              		.loc 1 1413 11 is_stmt 0 view .LVU1230
+ 3753 007c 0346     		mov	r3, r0
+1413:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = put_fat(fs, clst, ncl);	/* Link it from the previous one if needed */
+ 3754              		.loc 1 1413 20 view .LVU1231
+ 3755 007e B0FA80F0 		clz	r0, r0
+ 3756              	.LVL427:
+1413:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = put_fat(fs, clst, ncl);	/* Link it from the previous one if needed */
+ 3757              		.loc 1 1413 20 view .LVU1232
+ 3758 0082 4009     		lsrs	r0, r0, #5
+ 3759 0084 002F     		cmp	r7, #0
+ 3760 0086 08BF     		it	eq
+ 3761 0088 0020     		moveq	r0, #0
+1413:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = put_fat(fs, clst, ncl);	/* Link it from the previous one if needed */
+ 3762              		.loc 1 1413 6 view .LVU1233
+ 3763 008a 70B9     		cbnz	r0, .L293
+ 3764              	.L282:
+ 3765              	.LVL428:
+1418:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->last_clst = ncl;
+ 3766              		.loc 1 1418 2 is_stmt 1 view .LVU1234
+1418:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->last_clst = ncl;
+ 3767              		.loc 1 1418 5 is_stmt 0 view .LVU1235
+ 3768 008c A3B9     		cbnz	r3, .L283
+1419:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--;
+ 3769              		.loc 1 1419 3 is_stmt 1 view .LVU1236
+1419:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--;
+ 3770              		.loc 1 1419 17 is_stmt 0 view .LVU1237
+ 3771 008e 3461     		str	r4, [r6, #16]
+1420:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag |= 1;
+ 3772              		.loc 1 1420 3 is_stmt 1 view .LVU1238
+1420:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag |= 1;
+ 3773              		.loc 1 1420 9 is_stmt 0 view .LVU1239
+ 3774 0090 7269     		ldr	r2, [r6, #20]
+ARM GAS  /tmp/cc5lWXRL.s 			page 187
+
+
+1420:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag |= 1;
+ 3775              		.loc 1 1420 26 view .LVU1240
+ 3776 0092 B369     		ldr	r3, [r6, #24]
+ 3777              	.LVL429:
+1420:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag |= 1;
+ 3778              		.loc 1 1420 37 view .LVU1241
+ 3779 0094 023B     		subs	r3, r3, #2
+1420:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag |= 1;
+ 3780              		.loc 1 1420 6 view .LVU1242
+ 3781 0096 9A42     		cmp	r2, r3
+ 3782 0098 01D8     		bhi	.L284
+1420:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag |= 1;
+ 3783              		.loc 1 1420 42 is_stmt 1 discriminator 1 view .LVU1243
+1420:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fsi_flag |= 1;
+ 3784              		.loc 1 1420 55 is_stmt 0 discriminator 1 view .LVU1244
+ 3785 009a 013A     		subs	r2, r2, #1
+ 3786 009c 7261     		str	r2, [r6, #20]
+ 3787              	.L284:
+1421:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else {
+ 3788              		.loc 1 1421 3 is_stmt 1 view .LVU1245
+1421:Middlewares/Third_Party/FatFs/src/ff.c **** 	} else {
+ 3789              		.loc 1 1421 16 is_stmt 0 view .LVU1246
+ 3790 009e 3379     		ldrb	r3, [r6, #4]	@ zero_extendqisi2
+ 3791 00a0 43F00103 		orr	r3, r3, #1
+ 3792 00a4 3371     		strb	r3, [r6, #4]
+ 3793 00a6 2346     		mov	r3, r4
+ 3794 00a8 12E0     		b	.L275
+ 3795              	.L293:
+1414:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3796              		.loc 1 1414 4 is_stmt 1 view .LVU1247
+1414:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3797              		.loc 1 1414 10 is_stmt 0 view .LVU1248
+ 3798 00aa 2246     		mov	r2, r4
+ 3799 00ac 3946     		mov	r1, r7
+ 3800 00ae 3046     		mov	r0, r6
+ 3801 00b0 FFF7FEFF 		bl	put_fat
+ 3802              	.LVL430:
+ 3803 00b4 0346     		mov	r3, r0
+ 3804              	.LVL431:
+1414:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3805              		.loc 1 1414 10 view .LVU1249
+ 3806 00b6 E9E7     		b	.L282
+ 3807              	.L283:
+1423:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3808              		.loc 1 1423 3 is_stmt 1 view .LVU1250
+1423:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3809              		.loc 1 1423 43 is_stmt 0 view .LVU1251
+ 3810 00b8 012B     		cmp	r3, #1
+ 3811 00ba 01D0     		beq	.L294
+ 3812 00bc 0123     		movs	r3, #1
+ 3813              	.LVL432:
+1423:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3814              		.loc 1 1423 43 view .LVU1252
+ 3815 00be 07E0     		b	.L275
+ 3816              	.LVL433:
+ 3817              	.L294:
+1423:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ARM GAS  /tmp/cc5lWXRL.s 			page 188
+
+
+ 3818              		.loc 1 1423 43 view .LVU1253
+ 3819 00c0 4FF0FF33 		mov	r3, #-1
+ 3820              	.LVL434:
+1423:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3821              		.loc 1 1423 43 view .LVU1254
+ 3822 00c4 04E0     		b	.L275
+ 3823              	.LVL435:
+ 3824              	.L287:
+1367:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (cs == 0xFFFFFFFF) return cs;	/* A disk error occurred */
+ 3825              		.loc 1 1367 22 view .LVU1255
+ 3826 00c6 0123     		movs	r3, #1
+ 3827 00c8 02E0     		b	.L275
+ 3828              	.LVL436:
+ 3829              	.L288:
+1405:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 3830              		.loc 1 1405 27 view .LVU1256
+ 3831 00ca 0023     		movs	r3, #0
+ 3832 00cc 00E0     		b	.L275
+ 3833              	.LVL437:
+ 3834              	.L292:
+1410:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3835              		.loc 1 1410 27 view .LVU1257
+ 3836 00ce 0023     		movs	r3, #0
+ 3837              	.LVL438:
+ 3838              	.L275:
+1427:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3839              		.loc 1 1427 1 view .LVU1258
+ 3840 00d0 1846     		mov	r0, r3
+ 3841 00d2 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+1427:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3842              		.loc 1 1427 1 view .LVU1259
+ 3843              		.cfi_endproc
+ 3844              	.LFE1203:
+ 3846              		.section	.text.remove_chain,"ax",%progbits
+ 3847              		.align	1
+ 3848              		.syntax unified
+ 3849              		.thumb
+ 3850              		.thumb_func
+ 3851              		.fpu fpv5-d16
+ 3853              	remove_chain:
+ 3854              	.LVL439:
+ 3855              	.LFB1202:
+1276:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_OK;
+ 3856              		.loc 1 1276 1 is_stmt 1 view -0
+ 3857              		.cfi_startproc
+ 3858              		@ args = 0, pretend = 0, frame = 0
+ 3859              		@ frame_needed = 0, uses_anonymous_args = 0
+1276:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_OK;
+ 3860              		.loc 1 1276 1 is_stmt 0 view .LVU1261
+ 3861 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 3862              	.LCFI26:
+ 3863              		.cfi_def_cfa_offset 24
+ 3864              		.cfi_offset 3, -24
+ 3865              		.cfi_offset 4, -20
+ 3866              		.cfi_offset 5, -16
+ 3867              		.cfi_offset 6, -12
+ 3868              		.cfi_offset 7, -8
+ARM GAS  /tmp/cc5lWXRL.s 			page 189
+
+
+ 3869              		.cfi_offset 14, -4
+ 3870 0002 0C46     		mov	r4, r1
+1277:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD nxt;
+ 3871              		.loc 1 1277 2 is_stmt 1 view .LVU1262
+ 3872              	.LVL440:
+1278:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = obj->fs;
+ 3873              		.loc 1 1278 2 view .LVU1263
+1279:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT || _USE_TRIM
+ 3874              		.loc 1 1279 2 view .LVU1264
+1279:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT || _USE_TRIM
+ 3875              		.loc 1 1279 9 is_stmt 0 view .LVU1265
+ 3876 0004 0568     		ldr	r5, [r0]
+ 3877              	.LVL441:
+1287:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3878              		.loc 1 1287 2 is_stmt 1 view .LVU1266
+1287:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3879              		.loc 1 1287 5 is_stmt 0 view .LVU1267
+ 3880 0006 0129     		cmp	r1, #1
+ 3881 0008 2ED9     		bls	.L300
+ 3882 000a 0646     		mov	r6, r0
+ 3883 000c 1146     		mov	r1, r2
+ 3884              	.LVL442:
+1287:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3885              		.loc 1 1287 28 discriminator 2 view .LVU1268
+ 3886 000e AB69     		ldr	r3, [r5, #24]
+1287:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3887              		.loc 1 1287 15 discriminator 2 view .LVU1269
+ 3888 0010 A342     		cmp	r3, r4
+ 3889 0012 2BD9     		bls	.L301
+1290:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = put_fat(fs, pclst, 0xFFFFFFFF);
+ 3890              		.loc 1 1290 2 is_stmt 1 view .LVU1270
+1290:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = put_fat(fs, pclst, 0xFFFFFFFF);
+ 3891              		.loc 1 1290 5 is_stmt 0 view .LVU1271
+ 3892 0014 4AB1     		cbz	r2, .L299
+1291:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) return res;
+ 3893              		.loc 1 1291 3 is_stmt 1 view .LVU1272
+1291:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) return res;
+ 3894              		.loc 1 1291 9 is_stmt 0 view .LVU1273
+ 3895 0016 4FF0FF32 		mov	r2, #-1
+ 3896              	.LVL443:
+1291:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) return res;
+ 3897              		.loc 1 1291 9 view .LVU1274
+ 3898 001a 2846     		mov	r0, r5
+ 3899              	.LVL444:
+1291:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) return res;
+ 3900              		.loc 1 1291 9 view .LVU1275
+ 3901 001c FFF7FEFF 		bl	put_fat
+ 3902              	.LVL445:
+1292:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3903              		.loc 1 1292 3 is_stmt 1 view .LVU1276
+1292:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 3904              		.loc 1 1292 6 is_stmt 0 view .LVU1277
+ 3905 0020 0746     		mov	r7, r0
+ 3906 0022 10B1     		cbz	r0, .L299
+ 3907 0024 23E0     		b	.L296
+ 3908              	.LVL446:
+ 3909              	.L298:
+ARM GAS  /tmp/cc5lWXRL.s 			page 190
+
+
+1327:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (clst < fs->n_fatent);	/* Repeat while not the last link */
+ 3910              		.loc 1 1327 3 is_stmt 1 view .LVU1278
+1328:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3911              		.loc 1 1328 10 view .LVU1279
+1328:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3912              		.loc 1 1328 2 is_stmt 0 view .LVU1280
+ 3913 0026 A242     		cmp	r2, r4
+ 3914 0028 21D9     		bls	.L296
+ 3915              	.LVL447:
+ 3916              	.L299:
+1296:Middlewares/Third_Party/FatFs/src/ff.c **** 		nxt = get_fat(obj, clst);			/* Get cluster status */
+ 3917              		.loc 1 1296 2 is_stmt 1 view .LVU1281
+1297:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 0) break;				/* Empty cluster? */
+ 3918              		.loc 1 1297 3 view .LVU1282
+ 3919 002a 2746     		mov	r7, r4
+1297:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 0) break;				/* Empty cluster? */
+ 3920              		.loc 1 1297 9 is_stmt 0 view .LVU1283
+ 3921 002c 2146     		mov	r1, r4
+ 3922 002e 3046     		mov	r0, r6
+ 3923 0030 FFF7FEFF 		bl	get_fat
+ 3924              	.LVL448:
+1298:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 1) return FR_INT_ERR;	/* Internal error? */
+ 3925              		.loc 1 1298 3 is_stmt 1 view .LVU1284
+1298:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 1) return FR_INT_ERR;	/* Internal error? */
+ 3926              		.loc 1 1298 6 is_stmt 0 view .LVU1285
+ 3927 0034 0446     		mov	r4, r0
+ 3928              	.LVL449:
+1298:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 1) return FR_INT_ERR;	/* Internal error? */
+ 3929              		.loc 1 1298 6 view .LVU1286
+ 3930 0036 E0B1     		cbz	r0, .L302
+1299:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error? */
+ 3931              		.loc 1 1299 3 is_stmt 1 view .LVU1287
+1299:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error? */
+ 3932              		.loc 1 1299 6 is_stmt 0 view .LVU1288
+ 3933 0038 0128     		cmp	r0, #1
+ 3934 003a 1CD0     		beq	.L303
+1300:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+ 3935              		.loc 1 1300 3 is_stmt 1 view .LVU1289
+1300:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+ 3936              		.loc 1 1300 6 is_stmt 0 view .LVU1290
+ 3937 003c B0F1FF3F 		cmp	r0, #-1
+ 3938 0040 1BD0     		beq	.L304
+1301:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = put_fat(fs, clst, 0);		/* Mark the cluster 'free' on the FAT */
+ 3939              		.loc 1 1301 3 is_stmt 1 view .LVU1291
+1302:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) return res;
+ 3940              		.loc 1 1302 4 view .LVU1292
+1302:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) return res;
+ 3941              		.loc 1 1302 10 is_stmt 0 view .LVU1293
+ 3942 0042 0022     		movs	r2, #0
+ 3943 0044 3946     		mov	r1, r7
+ 3944 0046 2846     		mov	r0, r5
+ 3945              	.LVL450:
+1302:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) return res;
+ 3946              		.loc 1 1302 10 view .LVU1294
+ 3947 0048 FFF7FEFF 		bl	put_fat
+ 3948              	.LVL451:
+1303:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ARM GAS  /tmp/cc5lWXRL.s 			page 191
+
+
+ 3949              		.loc 1 1303 4 is_stmt 1 view .LVU1295
+1303:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3950              		.loc 1 1303 7 is_stmt 0 view .LVU1296
+ 3951 004c 0746     		mov	r7, r0
+ 3952              	.LVL452:
+1303:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3953              		.loc 1 1303 7 view .LVU1297
+ 3954 004e 70B9     		cbnz	r0, .L296
+1305:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->free_clst++;
+ 3955              		.loc 1 1305 3 is_stmt 1 view .LVU1298
+1305:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->free_clst++;
+ 3956              		.loc 1 1305 9 is_stmt 0 view .LVU1299
+ 3957 0050 6B69     		ldr	r3, [r5, #20]
+1305:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->free_clst++;
+ 3958              		.loc 1 1305 25 view .LVU1300
+ 3959 0052 AA69     		ldr	r2, [r5, #24]
+1305:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->free_clst++;
+ 3960              		.loc 1 1305 36 view .LVU1301
+ 3961 0054 911E     		subs	r1, r2, #2
+1305:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->free_clst++;
+ 3962              		.loc 1 1305 6 view .LVU1302
+ 3963 0056 8B42     		cmp	r3, r1
+ 3964 0058 E5D2     		bcs	.L298
+1306:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->fsi_flag |= 1;
+ 3965              		.loc 1 1306 4 is_stmt 1 view .LVU1303
+1306:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->fsi_flag |= 1;
+ 3966              		.loc 1 1306 17 is_stmt 0 view .LVU1304
+ 3967 005a 0133     		adds	r3, r3, #1
+ 3968 005c 6B61     		str	r3, [r5, #20]
+1307:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3969              		.loc 1 1307 4 is_stmt 1 view .LVU1305
+1307:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 3970              		.loc 1 1307 17 is_stmt 0 view .LVU1306
+ 3971 005e 2B79     		ldrb	r3, [r5, #4]	@ zero_extendqisi2
+ 3972 0060 43F00103 		orr	r3, r3, #1
+ 3973 0064 2B71     		strb	r3, [r5, #4]
+ 3974 0066 DEE7     		b	.L298
+ 3975              	.LVL453:
+ 3976              	.L300:
+1287:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3977              		.loc 1 1287 47 view .LVU1307
+ 3978 0068 0227     		movs	r7, #2
+ 3979 006a 00E0     		b	.L296
+ 3980              	.LVL454:
+ 3981              	.L301:
+1287:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3982              		.loc 1 1287 47 view .LVU1308
+ 3983 006c 0227     		movs	r7, #2
+ 3984              	.LVL455:
+ 3985              	.L296:
+1342:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 3986              		.loc 1 1342 1 view .LVU1309
+ 3987 006e 3846     		mov	r0, r7
+ 3988 0070 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 3989              	.LVL456:
+ 3990              	.L302:
+1341:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ARM GAS  /tmp/cc5lWXRL.s 			page 192
+
+
+ 3991              		.loc 1 1341 9 view .LVU1310
+ 3992 0072 0027     		movs	r7, #0
+ 3993              	.LVL457:
+1341:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 3994              		.loc 1 1341 9 view .LVU1311
+ 3995 0074 FBE7     		b	.L296
+ 3996              	.LVL458:
+ 3997              	.L303:
+1299:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error? */
+ 3998              		.loc 1 1299 24 view .LVU1312
+ 3999 0076 0227     		movs	r7, #2
+ 4000              	.LVL459:
+1299:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error? */
+ 4001              		.loc 1 1299 24 view .LVU1313
+ 4002 0078 F9E7     		b	.L296
+ 4003              	.LVL460:
+ 4004              	.L304:
+1300:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+ 4005              		.loc 1 1300 33 view .LVU1314
+ 4006 007a 0127     		movs	r7, #1
+ 4007              	.LVL461:
+1300:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+ 4008              		.loc 1 1300 33 view .LVU1315
+ 4009 007c F7E7     		b	.L296
+ 4010              		.cfi_endproc
+ 4011              	.LFE1202:
+ 4013              		.section	.text.dir_remove,"ax",%progbits
+ 4014              		.align	1
+ 4015              		.syntax unified
+ 4016              		.thumb
+ 4017              		.thumb_func
+ 4018              		.fpu fpv5-d16
+ 4020              	dir_remove:
+ 4021              	.LVL462:
+ 4022              	.LFB1213:
+2399:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 4023              		.loc 1 2399 1 is_stmt 1 view -0
+ 4024              		.cfi_startproc
+ 4025              		@ args = 0, pretend = 0, frame = 0
+ 4026              		@ frame_needed = 0, uses_anonymous_args = 0
+2399:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 4027              		.loc 1 2399 1 is_stmt 0 view .LVU1317
+ 4028 0000 38B5     		push	{r3, r4, r5, lr}
+ 4029              	.LCFI27:
+ 4030              		.cfi_def_cfa_offset 16
+ 4031              		.cfi_offset 3, -16
+ 4032              		.cfi_offset 4, -12
+ 4033              		.cfi_offset 5, -8
+ 4034              		.cfi_offset 14, -4
+ 4035 0002 0446     		mov	r4, r0
+2400:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+ 4036              		.loc 1 2400 2 is_stmt 1 view .LVU1318
+2401:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+ 4037              		.loc 1 2401 2 view .LVU1319
+2401:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+ 4038              		.loc 1 2401 9 is_stmt 0 view .LVU1320
+ 4039 0004 0568     		ldr	r5, [r0]
+ARM GAS  /tmp/cc5lWXRL.s 			page 193
+
+
+ 4040              	.LVL463:
+2424:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 4041              		.loc 1 2424 2 is_stmt 1 view .LVU1321
+2424:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 4042              		.loc 1 2424 8 is_stmt 0 view .LVU1322
+ 4043 0006 C169     		ldr	r1, [r0, #28]
+ 4044 0008 2846     		mov	r0, r5
+ 4045              	.LVL464:
+2424:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 4046              		.loc 1 2424 8 view .LVU1323
+ 4047 000a FFF7FEFF 		bl	move_window
+ 4048              	.LVL465:
+2425:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->dir[DIR_Name] = DDEM;
+ 4049              		.loc 1 2425 2 is_stmt 1 view .LVU1324
+2425:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->dir[DIR_Name] = DDEM;
+ 4050              		.loc 1 2425 5 is_stmt 0 view .LVU1325
+ 4051 000e 20B9     		cbnz	r0, .L307
+2426:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->wflag = 1;
+ 4052              		.loc 1 2426 3 is_stmt 1 view .LVU1326
+2426:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->wflag = 1;
+ 4053              		.loc 1 2426 5 is_stmt 0 view .LVU1327
+ 4054 0010 236A     		ldr	r3, [r4, #32]
+2426:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->wflag = 1;
+ 4055              		.loc 1 2426 21 view .LVU1328
+ 4056 0012 E522     		movs	r2, #229
+ 4057 0014 1A70     		strb	r2, [r3]
+2427:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 4058              		.loc 1 2427 3 is_stmt 1 view .LVU1329
+2427:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 4059              		.loc 1 2427 13 is_stmt 0 view .LVU1330
+ 4060 0016 0123     		movs	r3, #1
+ 4061 0018 EB70     		strb	r3, [r5, #3]
+ 4062              	.L307:
+2431:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 4063              		.loc 1 2431 2 is_stmt 1 view .LVU1331
+2432:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4064              		.loc 1 2432 1 is_stmt 0 view .LVU1332
+ 4065 001a 38BD     		pop	{r3, r4, r5, pc}
+2432:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4066              		.loc 1 2432 1 view .LVU1333
+ 4067              		.cfi_endproc
+ 4068              	.LFE1213:
+ 4070              		.section	.text.dir_next,"ax",%progbits
+ 4071              		.align	1
+ 4072              		.syntax unified
+ 4073              		.thumb
+ 4074              		.thumb_func
+ 4075              		.fpu fpv5-d16
+ 4077              	dir_next:
+ 4078              	.LVL466:
+ 4079              	.LFB1206:
+1523:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD ofs, clst;
+ 4080              		.loc 1 1523 1 is_stmt 1 view -0
+ 4081              		.cfi_startproc
+ 4082              		@ args = 0, pretend = 0, frame = 0
+ 4083              		@ frame_needed = 0, uses_anonymous_args = 0
+1523:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD ofs, clst;
+ARM GAS  /tmp/cc5lWXRL.s 			page 194
+
+
+ 4084              		.loc 1 1523 1 is_stmt 0 view .LVU1335
+ 4085 0000 2DE9F843 		push	{r3, r4, r5, r6, r7, r8, r9, lr}
+ 4086              	.LCFI28:
+ 4087              		.cfi_def_cfa_offset 32
+ 4088              		.cfi_offset 3, -32
+ 4089              		.cfi_offset 4, -28
+ 4090              		.cfi_offset 5, -24
+ 4091              		.cfi_offset 6, -20
+ 4092              		.cfi_offset 7, -16
+ 4093              		.cfi_offset 8, -12
+ 4094              		.cfi_offset 9, -8
+ 4095              		.cfi_offset 14, -4
+1524:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+ 4096              		.loc 1 1524 2 is_stmt 1 view .LVU1336
+1525:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 4097              		.loc 1 1525 2 view .LVU1337
+1525:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 4098              		.loc 1 1525 9 is_stmt 0 view .LVU1338
+ 4099 0004 0668     		ldr	r6, [r0]
+ 4100              	.LVL467:
+1527:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 4101              		.loc 1 1527 2 is_stmt 1 view .LVU1339
+1530:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) re
+ 4102              		.loc 1 1530 2 view .LVU1340
+1530:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) re
+ 4103              		.loc 1 1530 10 is_stmt 0 view .LVU1341
+ 4104 0006 4469     		ldr	r4, [r0, #20]
+ 4105              	.LVL468:
+1531:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4106              		.loc 1 1531 2 is_stmt 1 view .LVU1342
+1531:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4107              		.loc 1 1531 9 is_stmt 0 view .LVU1343
+ 4108 0008 C369     		ldr	r3, [r0, #28]
+1531:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4109              		.loc 1 1531 5 view .LVU1344
+ 4110 000a 002B     		cmp	r3, #0
+ 4111 000c 74D0     		beq	.L317
+ 4112 000e 0546     		mov	r5, r0
+ 4113 0010 0F46     		mov	r7, r1
+ 4114 0012 2034     		adds	r4, r4, #32
+ 4115              	.LVL469:
+1531:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4116              		.loc 1 1531 16 discriminator 2 view .LVU1345
+ 4117 0014 B4F5001F 		cmp	r4, #2097152
+ 4118 0018 70D2     		bcs	.L318
+1533:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect++;				/* Next sector */
+ 4119              		.loc 1 1533 2 is_stmt 1 view .LVU1346
+1533:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect++;				/* Next sector */
+ 4120              		.loc 1 1533 12 is_stmt 0 view .LVU1347
+ 4121 001a B189     		ldrh	r1, [r6, #12]
+ 4122              	.LVL470:
+1533:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect++;				/* Next sector */
+ 4123              		.loc 1 1533 10 view .LVU1348
+ 4124 001c B4FBF1F2 		udiv	r2, r4, r1
+ 4125 0020 01FB1242 		mls	r2, r1, r2, r4
+1533:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->sect++;				/* Next sector */
+ 4126              		.loc 1 1533 5 view .LVU1349
+ARM GAS  /tmp/cc5lWXRL.s 			page 195
+
+
+ 4127 0024 3AB9     		cbnz	r2, .L311
+1534:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4128              		.loc 1 1534 3 is_stmt 1 view .LVU1350
+1534:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4129              		.loc 1 1534 11 is_stmt 0 view .LVU1351
+ 4130 0026 0133     		adds	r3, r3, #1
+ 4131 0028 C361     		str	r3, [r0, #28]
+1536:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ofs / SZDIRE >= fs->n_rootdir) {	/* Report EOT if it reached end of static table */
+ 4132              		.loc 1 1536 3 is_stmt 1 view .LVU1352
+1536:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ofs / SZDIRE >= fs->n_rootdir) {	/* Report EOT if it reached end of static table */
+ 4133              		.loc 1 1536 10 is_stmt 0 view .LVU1353
+ 4134 002a 8169     		ldr	r1, [r0, #24]
+1536:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ofs / SZDIRE >= fs->n_rootdir) {	/* Report EOT if it reached end of static table */
+ 4135              		.loc 1 1536 6 view .LVU1354
+ 4136 002c A1B9     		cbnz	r1, .L312
+1537:Middlewares/Third_Party/FatFs/src/ff.c **** 				dp->sect = 0; return FR_NO_FILE;
+ 4137              		.loc 1 1537 4 is_stmt 1 view .LVU1355
+1537:Middlewares/Third_Party/FatFs/src/ff.c **** 				dp->sect = 0; return FR_NO_FILE;
+ 4138              		.loc 1 1537 26 is_stmt 0 view .LVU1356
+ 4139 002e 3389     		ldrh	r3, [r6, #8]
+1537:Middlewares/Third_Party/FatFs/src/ff.c **** 				dp->sect = 0; return FR_NO_FILE;
+ 4140              		.loc 1 1537 7 view .LVU1357
+ 4141 0030 B3EB541F 		cmp	r3, r4, lsr #5
+ 4142 0034 0CD9     		bls	.L327
+ 4143              	.LVL471:
+ 4144              	.L311:
+1574:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->dir = fs->win + ofs % SS(fs);	/* Pointer to the entry in the win[] */
+ 4145              		.loc 1 1574 2 is_stmt 1 view .LVU1358
+1574:Middlewares/Third_Party/FatFs/src/ff.c **** 	dp->dir = fs->win + ofs % SS(fs);	/* Pointer to the entry in the win[] */
+ 4146              		.loc 1 1574 11 is_stmt 0 view .LVU1359
+ 4147 0036 6C61     		str	r4, [r5, #20]
+1575:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4148              		.loc 1 1575 2 is_stmt 1 view .LVU1360
+1575:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4149              		.loc 1 1575 12 is_stmt 0 view .LVU1361
+ 4150 0038 06F13403 		add	r3, r6, #52
+1575:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4151              		.loc 1 1575 28 view .LVU1362
+ 4152 003c B289     		ldrh	r2, [r6, #12]
+1575:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4153              		.loc 1 1575 26 view .LVU1363
+ 4154 003e B4FBF2F1 		udiv	r1, r4, r2
+ 4155 0042 02FB1144 		mls	r4, r2, r1, r4
+ 4156              	.LVL472:
+1575:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4157              		.loc 1 1575 20 view .LVU1364
+ 4158 0046 1C44     		add	r4, r4, r3
+1575:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4159              		.loc 1 1575 10 view .LVU1365
+ 4160 0048 2C62     		str	r4, [r5, #32]
+1577:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 4161              		.loc 1 1577 2 is_stmt 1 view .LVU1366
+1577:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 4162              		.loc 1 1577 9 is_stmt 0 view .LVU1367
+ 4163 004a 0020     		movs	r0, #0
+ 4164              	.LVL473:
+ 4165              	.L310:
+ARM GAS  /tmp/cc5lWXRL.s 			page 196
+
+
+1578:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4166              		.loc 1 1578 1 view .LVU1368
+ 4167 004c BDE8F883 		pop	{r3, r4, r5, r6, r7, r8, r9, pc}
+ 4168              	.LVL474:
+ 4169              	.L327:
+1538:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4170              		.loc 1 1538 5 is_stmt 1 view .LVU1369
+1538:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4171              		.loc 1 1538 14 is_stmt 0 view .LVU1370
+ 4172 0050 0023     		movs	r3, #0
+ 4173 0052 C361     		str	r3, [r0, #28]
+1538:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4174              		.loc 1 1538 19 is_stmt 1 view .LVU1371
+1538:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4175              		.loc 1 1538 26 is_stmt 0 view .LVU1372
+ 4176 0054 0420     		movs	r0, #4
+ 4177              	.LVL475:
+1538:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4178              		.loc 1 1538 26 view .LVU1373
+ 4179 0056 F9E7     		b	.L310
+ 4180              	.LVL476:
+ 4181              	.L312:
+1542:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = get_fat(&dp->obj, dp->clust);			/* Get next cluster */
+ 4182              		.loc 1 1542 4 is_stmt 1 view .LVU1374
+1542:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = get_fat(&dp->obj, dp->clust);			/* Get next cluster */
+ 4183              		.loc 1 1542 15 is_stmt 0 view .LVU1375
+ 4184 0058 B289     		ldrh	r2, [r6, #12]
+1542:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = get_fat(&dp->obj, dp->clust);			/* Get next cluster */
+ 4185              		.loc 1 1542 13 view .LVU1376
+ 4186 005a B4FBF2F2 		udiv	r2, r4, r2
+1542:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = get_fat(&dp->obj, dp->clust);			/* Get next cluster */
+ 4187              		.loc 1 1542 27 view .LVU1377
+ 4188 005e 7389     		ldrh	r3, [r6, #10]
+1542:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = get_fat(&dp->obj, dp->clust);			/* Get next cluster */
+ 4189              		.loc 1 1542 35 view .LVU1378
+ 4190 0060 013B     		subs	r3, r3, #1
+1542:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = get_fat(&dp->obj, dp->clust);			/* Get next cluster */
+ 4191              		.loc 1 1542 7 view .LVU1379
+ 4192 0062 12EA0308 		ands	r8, r2, r3
+ 4193 0066 E6D1     		bne	.L311
+1543:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst <= 1) return FR_INT_ERR;				/* Internal error */
+ 4194              		.loc 1 1543 5 is_stmt 1 view .LVU1380
+1543:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst <= 1) return FR_INT_ERR;				/* Internal error */
+ 4195              		.loc 1 1543 12 is_stmt 0 view .LVU1381
+ 4196 0068 FFF7FEFF 		bl	get_fat
+ 4197              	.LVL477:
+1543:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst <= 1) return FR_INT_ERR;				/* Internal error */
+ 4198              		.loc 1 1543 12 view .LVU1382
+ 4199 006c 8146     		mov	r9, r0
+ 4200              	.LVL478:
+1544:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;		/* Disk error */
+ 4201              		.loc 1 1544 5 is_stmt 1 view .LVU1383
+1544:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;		/* Disk error */
+ 4202              		.loc 1 1544 8 is_stmt 0 view .LVU1384
+ 4203 006e 0128     		cmp	r0, #1
+ 4204 0070 46D9     		bls	.L319
+1545:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst >= fs->n_fatent) {						/* Reached end of dynamic table */
+ARM GAS  /tmp/cc5lWXRL.s 			page 197
+
+
+ 4205              		.loc 1 1545 5 is_stmt 1 view .LVU1385
+1545:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst >= fs->n_fatent) {						/* Reached end of dynamic table */
+ 4206              		.loc 1 1545 8 is_stmt 0 view .LVU1386
+ 4207 0072 B0F1FF3F 		cmp	r0, #-1
+ 4208 0076 45D0     		beq	.L320
+1546:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 4209              		.loc 1 1546 5 is_stmt 1 view .LVU1387
+1546:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 4210              		.loc 1 1546 19 is_stmt 0 view .LVU1388
+ 4211 0078 B369     		ldr	r3, [r6, #24]
+1546:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 4212              		.loc 1 1546 8 view .LVU1389
+ 4213 007a 8342     		cmp	r3, r0
+ 4214 007c 34D8     		bhi	.L313
+1548:Middlewares/Third_Party/FatFs/src/ff.c **** 						dp->sect = 0; return FR_NO_FILE;
+ 4215              		.loc 1 1548 6 is_stmt 1 view .LVU1390
+1548:Middlewares/Third_Party/FatFs/src/ff.c **** 						dp->sect = 0; return FR_NO_FILE;
+ 4216              		.loc 1 1548 9 is_stmt 0 view .LVU1391
+ 4217 007e 8FB1     		cbz	r7, .L328
+1551:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0) return FR_DENIED;			/* No free cluster */
+ 4218              		.loc 1 1551 6 is_stmt 1 view .LVU1392
+1551:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0) return FR_DENIED;			/* No free cluster */
+ 4219              		.loc 1 1551 13 is_stmt 0 view .LVU1393
+ 4220 0080 A969     		ldr	r1, [r5, #24]
+ 4221 0082 2846     		mov	r0, r5
+ 4222              	.LVL479:
+1551:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0) return FR_DENIED;			/* No free cluster */
+ 4223              		.loc 1 1551 13 view .LVU1394
+ 4224 0084 FFF7FEFF 		bl	create_chain
+ 4225              	.LVL480:
+1552:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 1) return FR_INT_ERR;			/* Internal error */
+ 4226              		.loc 1 1552 6 is_stmt 1 view .LVU1395
+1552:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 1) return FR_INT_ERR;			/* Internal error */
+ 4227              		.loc 1 1552 9 is_stmt 0 view .LVU1396
+ 4228 0088 8146     		mov	r9, r0
+ 4229 008a 0028     		cmp	r0, #0
+ 4230 008c 3CD0     		beq	.L321
+1553:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+ 4231              		.loc 1 1553 6 is_stmt 1 view .LVU1397
+1553:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+ 4232              		.loc 1 1553 9 is_stmt 0 view .LVU1398
+ 4233 008e 0128     		cmp	r0, #1
+ 4234 0090 3CD0     		beq	.L322
+1554:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Clean-up the stretched table */
+ 4235              		.loc 1 1554 6 is_stmt 1 view .LVU1399
+1554:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Clean-up the stretched table */
+ 4236              		.loc 1 1554 9 is_stmt 0 view .LVU1400
+ 4237 0092 B0F1FF3F 		cmp	r0, #-1
+ 4238 0096 3BD0     		beq	.L323
+1556:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (sync_window(fs) != FR_OK) return FR_DISK_ERR;	/* Flush disk access window */
+ 4239              		.loc 1 1556 6 is_stmt 1 view .LVU1401
+1557:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_set(fs->win, 0, SS(fs));				/* Clear window buffer */
+ 4240              		.loc 1 1557 6 view .LVU1402
+1557:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_set(fs->win, 0, SS(fs));				/* Clear window buffer */
+ 4241              		.loc 1 1557 10 is_stmt 0 view .LVU1403
+ 4242 0098 3046     		mov	r0, r6
+ 4243              	.LVL481:
+ARM GAS  /tmp/cc5lWXRL.s 			page 198
+
+
+1557:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_set(fs->win, 0, SS(fs));				/* Clear window buffer */
+ 4244              		.loc 1 1557 10 view .LVU1404
+ 4245 009a FFF7FEFF 		bl	sync_window
+ 4246              	.LVL482:
+1557:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_set(fs->win, 0, SS(fs));				/* Clear window buffer */
+ 4247              		.loc 1 1557 9 view .LVU1405
+ 4248 009e 28B1     		cbz	r0, .L329
+1557:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_set(fs->win, 0, SS(fs));				/* Clear window buffer */
+ 4249              		.loc 1 1557 43 view .LVU1406
+ 4250 00a0 0120     		movs	r0, #1
+ 4251 00a2 D3E7     		b	.L310
+ 4252              	.LVL483:
+ 4253              	.L328:
+1549:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4254              		.loc 1 1549 7 is_stmt 1 view .LVU1407
+1549:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4255              		.loc 1 1549 16 is_stmt 0 view .LVU1408
+ 4256 00a4 0023     		movs	r3, #0
+ 4257 00a6 EB61     		str	r3, [r5, #28]
+1549:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4258              		.loc 1 1549 21 is_stmt 1 view .LVU1409
+1549:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4259              		.loc 1 1549 28 is_stmt 0 view .LVU1410
+ 4260 00a8 0420     		movs	r0, #4
+ 4261              	.LVL484:
+1549:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4262              		.loc 1 1549 28 view .LVU1411
+ 4263 00aa CFE7     		b	.L310
+ 4264              	.L329:
+1558:Middlewares/Third_Party/FatFs/src/ff.c **** 					for (n = 0, fs->winsect = clust2sect(fs, clst); n < fs->csize; n++, fs->winsect++) {	/* Fill t
+ 4265              		.loc 1 1558 6 is_stmt 1 view .LVU1412
+ 4266 00ac B289     		ldrh	r2, [r6, #12]
+ 4267 00ae 0021     		movs	r1, #0
+ 4268 00b0 06F13400 		add	r0, r6, #52
+ 4269 00b4 FFF7FEFF 		bl	mem_set
+ 4270              	.LVL485:
+1559:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 4271              		.loc 1 1559 6 view .LVU1413
+1559:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 4272              		.loc 1 1559 32 is_stmt 0 view .LVU1414
+ 4273 00b8 4946     		mov	r1, r9
+ 4274 00ba 3046     		mov	r0, r6
+ 4275 00bc FFF7FEFF 		bl	clust2sect
+ 4276              	.LVL486:
+1559:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 4277              		.loc 1 1559 30 view .LVU1415
+ 4278 00c0 3063     		str	r0, [r6, #48]
+ 4279              	.LVL487:
+ 4280              	.L315:
+1559:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 4281              		.loc 1 1559 54 is_stmt 1 discriminator 1 view .LVU1416
+1559:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 4282              		.loc 1 1559 60 is_stmt 0 discriminator 1 view .LVU1417
+ 4283 00c2 7389     		ldrh	r3, [r6, #10]
+1559:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 4284              		.loc 1 1559 6 discriminator 1 view .LVU1418
+ 4285 00c4 9845     		cmp	r8, r3
+ARM GAS  /tmp/cc5lWXRL.s 			page 199
+
+
+ 4286 00c6 0BD2     		bcs	.L330
+1560:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (sync_window(fs) != FR_OK) return FR_DISK_ERR;
+ 4287              		.loc 1 1560 7 is_stmt 1 view .LVU1419
+1560:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (sync_window(fs) != FR_OK) return FR_DISK_ERR;
+ 4288              		.loc 1 1560 17 is_stmt 0 view .LVU1420
+ 4289 00c8 0123     		movs	r3, #1
+ 4290 00ca F370     		strb	r3, [r6, #3]
+1561:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4291              		.loc 1 1561 7 is_stmt 1 view .LVU1421
+1561:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4292              		.loc 1 1561 11 is_stmt 0 view .LVU1422
+ 4293 00cc 3046     		mov	r0, r6
+ 4294 00ce FFF7FEFF 		bl	sync_window
+ 4295              	.LVL488:
+1561:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4296              		.loc 1 1561 10 view .LVU1423
+ 4297 00d2 F8B9     		cbnz	r0, .L325
+1559:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 4298              		.loc 1 1559 69 is_stmt 1 discriminator 2 view .LVU1424
+1559:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 4299              		.loc 1 1559 70 is_stmt 0 discriminator 2 view .LVU1425
+ 4300 00d4 08F10108 		add	r8, r8, #1
+ 4301              	.LVL489:
+1559:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 4302              		.loc 1 1559 76 discriminator 2 view .LVU1426
+ 4303 00d8 336B     		ldr	r3, [r6, #48]
+1559:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 4304              		.loc 1 1559 85 discriminator 2 view .LVU1427
+ 4305 00da 0133     		adds	r3, r3, #1
+ 4306 00dc 3363     		str	r3, [r6, #48]
+ 4307 00de F0E7     		b	.L315
+ 4308              	.L330:
+1563:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 4309              		.loc 1 1563 6 is_stmt 1 view .LVU1428
+1563:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 4310              		.loc 1 1563 18 is_stmt 0 view .LVU1429
+ 4311 00e0 336B     		ldr	r3, [r6, #48]
+ 4312 00e2 A3EB0803 		sub	r3, r3, r8
+ 4313 00e6 3363     		str	r3, [r6, #48]
+ 4314              	.LVL490:
+ 4315              	.L313:
+1569:Middlewares/Third_Party/FatFs/src/ff.c **** 				dp->sect = clust2sect(fs, clst);
+ 4316              		.loc 1 1569 5 is_stmt 1 view .LVU1430
+1569:Middlewares/Third_Party/FatFs/src/ff.c **** 				dp->sect = clust2sect(fs, clst);
+ 4317              		.loc 1 1569 15 is_stmt 0 view .LVU1431
+ 4318 00e8 C5F81890 		str	r9, [r5, #24]
+1570:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4319              		.loc 1 1570 5 is_stmt 1 view .LVU1432
+1570:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4320              		.loc 1 1570 16 is_stmt 0 view .LVU1433
+ 4321 00ec 4946     		mov	r1, r9
+ 4322 00ee 3046     		mov	r0, r6
+ 4323 00f0 FFF7FEFF 		bl	clust2sect
+ 4324              	.LVL491:
+1570:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4325              		.loc 1 1570 14 view .LVU1434
+ 4326 00f4 E861     		str	r0, [r5, #28]
+ARM GAS  /tmp/cc5lWXRL.s 			page 200
+
+
+ 4327 00f6 9EE7     		b	.L311
+ 4328              	.LVL492:
+ 4329              	.L317:
+1531:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4330              		.loc 1 1531 105 view .LVU1435
+ 4331 00f8 0420     		movs	r0, #4
+ 4332              	.LVL493:
+1531:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4333              		.loc 1 1531 105 view .LVU1436
+ 4334 00fa A7E7     		b	.L310
+ 4335              	.LVL494:
+ 4336              	.L318:
+1531:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4337              		.loc 1 1531 105 view .LVU1437
+ 4338 00fc 0420     		movs	r0, #4
+ 4339              	.LVL495:
+1531:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4340              		.loc 1 1531 105 view .LVU1438
+ 4341 00fe A5E7     		b	.L310
+ 4342              	.LVL496:
+ 4343              	.L319:
+1544:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;		/* Disk error */
+ 4344              		.loc 1 1544 27 view .LVU1439
+ 4345 0100 0220     		movs	r0, #2
+ 4346              	.LVL497:
+1544:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;		/* Disk error */
+ 4347              		.loc 1 1544 27 view .LVU1440
+ 4348 0102 A3E7     		b	.L310
+ 4349              	.LVL498:
+ 4350              	.L320:
+1545:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst >= fs->n_fatent) {						/* Reached end of dynamic table */
+ 4351              		.loc 1 1545 36 view .LVU1441
+ 4352 0104 0120     		movs	r0, #1
+ 4353              	.LVL499:
+1545:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst >= fs->n_fatent) {						/* Reached end of dynamic table */
+ 4354              		.loc 1 1545 36 view .LVU1442
+ 4355 0106 A1E7     		b	.L310
+ 4356              	.LVL500:
+ 4357              	.L321:
+1552:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 1) return FR_INT_ERR;			/* Internal error */
+ 4358              		.loc 1 1552 28 view .LVU1443
+ 4359 0108 0720     		movs	r0, #7
+ 4360              	.LVL501:
+1552:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 1) return FR_INT_ERR;			/* Internal error */
+ 4361              		.loc 1 1552 28 view .LVU1444
+ 4362 010a 9FE7     		b	.L310
+ 4363              	.LVL502:
+ 4364              	.L322:
+1553:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+ 4365              		.loc 1 1553 28 view .LVU1445
+ 4366 010c 0220     		movs	r0, #2
+ 4367              	.LVL503:
+1553:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+ 4368              		.loc 1 1553 28 view .LVU1446
+ 4369 010e 9DE7     		b	.L310
+ 4370              	.LVL504:
+ 4371              	.L323:
+ARM GAS  /tmp/cc5lWXRL.s 			page 201
+
+
+1554:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Clean-up the stretched table */
+ 4372              		.loc 1 1554 37 view .LVU1447
+ 4373 0110 0120     		movs	r0, #1
+ 4374              	.LVL505:
+1554:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Clean-up the stretched table */
+ 4375              		.loc 1 1554 37 view .LVU1448
+ 4376 0112 9BE7     		b	.L310
+ 4377              	.LVL506:
+ 4378              	.L325:
+1561:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4379              		.loc 1 1561 44 view .LVU1449
+ 4380 0114 0120     		movs	r0, #1
+ 4381 0116 99E7     		b	.L310
+ 4382              		.cfi_endproc
+ 4383              	.LFE1206:
+ 4385              		.section	.text.dir_find,"ax",%progbits
+ 4386              		.align	1
+ 4387              		.syntax unified
+ 4388              		.thumb
+ 4389              		.thumb_func
+ 4390              		.fpu fpv5-d16
+ 4392              	dir_find:
+ 4393              	.LVL507:
+ 4394              	.LFB1211:
+2213:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 4395              		.loc 1 2213 1 is_stmt 1 view -0
+ 4396              		.cfi_startproc
+ 4397              		@ args = 0, pretend = 0, frame = 0
+ 4398              		@ frame_needed = 0, uses_anonymous_args = 0
+2213:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 4399              		.loc 1 2213 1 is_stmt 0 view .LVU1451
+ 4400 0000 70B5     		push	{r4, r5, r6, lr}
+ 4401              	.LCFI29:
+ 4402              		.cfi_def_cfa_offset 16
+ 4403              		.cfi_offset 4, -16
+ 4404              		.cfi_offset 5, -12
+ 4405              		.cfi_offset 6, -8
+ 4406              		.cfi_offset 14, -4
+ 4407 0002 0446     		mov	r4, r0
+2214:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+ 4408              		.loc 1 2214 2 is_stmt 1 view .LVU1452
+2215:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE c;
+ 4409              		.loc 1 2215 2 view .LVU1453
+2215:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE c;
+ 4410              		.loc 1 2215 9 is_stmt 0 view .LVU1454
+ 4411 0004 0668     		ldr	r6, [r0]
+ 4412              	.LVL508:
+2216:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+ 4413              		.loc 1 2216 2 is_stmt 1 view .LVU1455
+2221:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK) return res;
+ 4414              		.loc 1 2221 2 view .LVU1456
+2221:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK) return res;
+ 4415              		.loc 1 2221 8 is_stmt 0 view .LVU1457
+ 4416 0006 0021     		movs	r1, #0
+ 4417 0008 FFF7FEFF 		bl	dir_sdi
+ 4418              	.LVL509:
+2222:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ARM GAS  /tmp/cc5lWXRL.s 			page 202
+
+
+ 4419              		.loc 1 2222 2 is_stmt 1 view .LVU1458
+2222:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 4420              		.loc 1 2222 5 is_stmt 0 view .LVU1459
+ 4421 000c 0546     		mov	r5, r0
+ 4422 000e 40B1     		cbz	r0, .L334
+ 4423              	.LVL510:
+ 4424              	.L332:
+2281:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4425              		.loc 1 2281 1 view .LVU1460
+ 4426 0010 2846     		mov	r0, r5
+ 4427 0012 70BD     		pop	{r4, r5, r6, pc}
+ 4428              	.LVL511:
+ 4429              	.L333:
+2277:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (res == FR_OK);
+ 4430              		.loc 1 2277 3 is_stmt 1 view .LVU1461
+2277:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (res == FR_OK);
+ 4431              		.loc 1 2277 9 is_stmt 0 view .LVU1462
+ 4432 0014 0021     		movs	r1, #0
+ 4433 0016 2046     		mov	r0, r4
+ 4434 0018 FFF7FEFF 		bl	dir_next
+ 4435              	.LVL512:
+2278:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4436              		.loc 1 2278 10 is_stmt 1 view .LVU1463
+2278:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4437              		.loc 1 2278 2 is_stmt 0 view .LVU1464
+ 4438 001c 0546     		mov	r5, r0
+ 4439 001e 0028     		cmp	r0, #0
+ 4440 0020 F6D1     		bne	.L332
+ 4441              	.L334:
+2247:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, dp->sect);
+ 4442              		.loc 1 2247 2 is_stmt 1 view .LVU1465
+2248:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+ 4443              		.loc 1 2248 3 view .LVU1466
+2248:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+ 4444              		.loc 1 2248 9 is_stmt 0 view .LVU1467
+ 4445 0022 E169     		ldr	r1, [r4, #28]
+ 4446 0024 3046     		mov	r0, r6
+ 4447              	.LVL513:
+2248:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+ 4448              		.loc 1 2248 9 view .LVU1468
+ 4449 0026 FFF7FEFF 		bl	move_window
+ 4450              	.LVL514:
+2249:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = dp->dir[DIR_Name];
+ 4451              		.loc 1 2249 3 is_stmt 1 view .LVU1469
+2249:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = dp->dir[DIR_Name];
+ 4452              		.loc 1 2249 6 is_stmt 0 view .LVU1470
+ 4453 002a 0546     		mov	r5, r0
+ 4454 002c 0028     		cmp	r0, #0
+ 4455 002e EFD1     		bne	.L332
+2250:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+ 4456              		.loc 1 2250 3 is_stmt 1 view .LVU1471
+2250:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+ 4457              		.loc 1 2250 9 is_stmt 0 view .LVU1472
+ 4458 0030 206A     		ldr	r0, [r4, #32]
+ 4459              	.LVL515:
+2250:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+ 4460              		.loc 1 2250 5 view .LVU1473
+ARM GAS  /tmp/cc5lWXRL.s 			page 203
+
+
+ 4461 0032 0378     		ldrb	r3, [r0]	@ zero_extendqisi2
+ 4462              	.LVL516:
+2251:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+ 4463              		.loc 1 2251 3 is_stmt 1 view .LVU1474
+2251:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+ 4464              		.loc 1 2251 6 is_stmt 0 view .LVU1475
+ 4465 0034 7BB1     		cbz	r3, .L335
+2274:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* Is it a valid entry
+ 4466              		.loc 1 2274 3 is_stmt 1 view .LVU1476
+2274:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* Is it a valid entry
+ 4467              		.loc 1 2274 25 is_stmt 0 view .LVU1477
+ 4468 0036 C37A     		ldrb	r3, [r0, #11]	@ zero_extendqisi2
+ 4469              	.LVL517:
+2274:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* Is it a valid entry
+ 4470              		.loc 1 2274 36 view .LVU1478
+ 4471 0038 03F03F03 		and	r3, r3, #63
+2274:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* Is it a valid entry
+ 4472              		.loc 1 2274 16 view .LVU1479
+ 4473 003c A371     		strb	r3, [r4, #6]
+ 4474              	.LVL518:
+2275:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 4475              		.loc 1 2275 3 is_stmt 1 view .LVU1480
+2275:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 4476              		.loc 1 2275 16 is_stmt 0 view .LVU1481
+ 4477 003e C37A     		ldrb	r3, [r0, #11]	@ zero_extendqisi2
+2275:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 4478              		.loc 1 2275 6 view .LVU1482
+ 4479 0040 13F0080F 		tst	r3, #8
+ 4480 0044 E6D1     		bne	.L333
+2275:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 4481              		.loc 1 2275 41 discriminator 1 view .LVU1483
+ 4482 0046 0B22     		movs	r2, #11
+ 4483 0048 04F12401 		add	r1, r4, #36
+ 4484 004c FFF7FEFF 		bl	mem_cmp
+ 4485              	.LVL519:
+2275:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 4486              		.loc 1 2275 37 discriminator 1 view .LVU1484
+ 4487 0050 0028     		cmp	r0, #0
+ 4488 0052 DFD1     		bne	.L333
+ 4489 0054 DCE7     		b	.L332
+ 4490              	.LVL520:
+ 4491              	.L335:
+2251:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+ 4492              		.loc 1 2251 21 view .LVU1485
+ 4493 0056 0425     		movs	r5, #4
+ 4494 0058 DAE7     		b	.L332
+ 4495              		.cfi_endproc
+ 4496              	.LFE1211:
+ 4498              		.section	.text.follow_path,"ax",%progbits
+ 4499              		.align	1
+ 4500              		.syntax unified
+ 4501              		.thumb
+ 4502              		.thumb_func
+ 4503              		.fpu fpv5-d16
+ 4505              	follow_path:
+ 4506              	.LVL521:
+ 4507              	.LFB1216:
+ARM GAS  /tmp/cc5lWXRL.s 			page 204
+
+
+2817:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 4508              		.loc 1 2817 1 is_stmt 1 view -0
+ 4509              		.cfi_startproc
+ 4510              		@ args = 0, pretend = 0, frame = 8
+ 4511              		@ frame_needed = 0, uses_anonymous_args = 0
+2817:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 4512              		.loc 1 2817 1 is_stmt 0 view .LVU1487
+ 4513 0000 30B5     		push	{r4, r5, lr}
+ 4514              	.LCFI30:
+ 4515              		.cfi_def_cfa_offset 12
+ 4516              		.cfi_offset 4, -12
+ 4517              		.cfi_offset 5, -8
+ 4518              		.cfi_offset 14, -4
+ 4519 0002 83B0     		sub	sp, sp, #12
+ 4520              	.LCFI31:
+ 4521              		.cfi_def_cfa_offset 24
+ 4522 0004 0446     		mov	r4, r0
+ 4523 0006 0191     		str	r1, [sp, #4]
+2818:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE ns;
+ 4524              		.loc 1 2818 2 is_stmt 1 view .LVU1488
+2819:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID *obj = &dp->obj;
+ 4525              		.loc 1 2819 2 view .LVU1489
+2820:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = obj->fs;
+ 4526              		.loc 1 2820 2 view .LVU1490
+ 4527              	.LVL522:
+2821:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4528              		.loc 1 2821 2 view .LVU1491
+2821:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4529              		.loc 1 2821 9 is_stmt 0 view .LVU1492
+ 4530 0008 0568     		ldr	r5, [r0]
+ 4531              	.LVL523:
+2830:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->sclust = 0;					/* Start from root directory */
+ 4532              		.loc 1 2830 3 is_stmt 1 view .LVU1493
+2830:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->sclust = 0;					/* Start from root directory */
+ 4533              		.loc 1 2830 9 is_stmt 0 view .LVU1494
+ 4534 000a 01E0     		b	.L338
+ 4535              	.L339:
+2830:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->sclust = 0;					/* Start from root directory */
+ 4536              		.loc 1 2830 41 is_stmt 1 discriminator 2 view .LVU1495
+2830:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->sclust = 0;					/* Start from root directory */
+ 4537              		.loc 1 2830 45 is_stmt 0 discriminator 2 view .LVU1496
+ 4538 000c 0133     		adds	r3, r3, #1
+ 4539 000e 0193     		str	r3, [sp, #4]
+ 4540              	.L338:
+2830:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->sclust = 0;					/* Start from root directory */
+ 4541              		.loc 1 2830 9 is_stmt 1 discriminator 1 view .LVU1497
+2830:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->sclust = 0;					/* Start from root directory */
+ 4542              		.loc 1 2830 10 is_stmt 0 discriminator 1 view .LVU1498
+ 4543 0010 019B     		ldr	r3, [sp, #4]
+ 4544 0012 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
+2830:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->sclust = 0;					/* Start from root directory */
+ 4545              		.loc 1 2830 9 discriminator 1 view .LVU1499
+ 4546 0014 5C2A     		cmp	r2, #92
+ 4547 0016 18BF     		it	ne
+ 4548 0018 2F2A     		cmpne	r2, #47
+ 4549 001a F7D0     		beq	.L339
+2831:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ARM GAS  /tmp/cc5lWXRL.s 			page 205
+
+
+ 4550              		.loc 1 2831 3 is_stmt 1 view .LVU1500
+2831:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 4551              		.loc 1 2831 15 is_stmt 0 view .LVU1501
+ 4552 001c 0022     		movs	r2, #0
+ 4553 001e A260     		str	r2, [r4, #8]
+2850:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->fn[NSFLAG] = NS_NONAME;
+ 4554              		.loc 1 2850 2 is_stmt 1 view .LVU1502
+2850:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->fn[NSFLAG] = NS_NONAME;
+ 4555              		.loc 1 2850 12 is_stmt 0 view .LVU1503
+ 4556 0020 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+2850:Middlewares/Third_Party/FatFs/src/ff.c **** 		dp->fn[NSFLAG] = NS_NONAME;
+ 4557              		.loc 1 2850 5 view .LVU1504
+ 4558 0022 1F2B     		cmp	r3, #31
+ 4559 0024 21D9     		bls	.L346
+ 4560              	.LVL524:
+ 4561              	.L340:
+2855:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = create_name(dp, &path);	/* Get a segment name of the path */
+ 4562              		.loc 1 2855 3 is_stmt 1 view .LVU1505
+2856:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 4563              		.loc 1 2856 4 view .LVU1506
+2856:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 4564              		.loc 1 2856 10 is_stmt 0 view .LVU1507
+ 4565 0026 01A9     		add	r1, sp, #4
+ 4566 0028 2046     		mov	r0, r4
+ 4567 002a FFF7FEFF 		bl	create_name
+ 4568              	.LVL525:
+2857:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dir_find(dp);				/* Find an object with the segment name */
+ 4569              		.loc 1 2857 4 is_stmt 1 view .LVU1508
+2857:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dir_find(dp);				/* Find an object with the segment name */
+ 4570              		.loc 1 2857 7 is_stmt 0 view .LVU1509
+ 4571 002e 0346     		mov	r3, r0
+ 4572 0030 18BB     		cbnz	r0, .L341
+2858:Middlewares/Third_Party/FatFs/src/ff.c **** 			ns = dp->fn[NSFLAG];
+ 4573              		.loc 1 2858 4 is_stmt 1 view .LVU1510
+2858:Middlewares/Third_Party/FatFs/src/ff.c **** 			ns = dp->fn[NSFLAG];
+ 4574              		.loc 1 2858 10 is_stmt 0 view .LVU1511
+ 4575 0032 2046     		mov	r0, r4
+ 4576              	.LVL526:
+2858:Middlewares/Third_Party/FatFs/src/ff.c **** 			ns = dp->fn[NSFLAG];
+ 4577              		.loc 1 2858 10 view .LVU1512
+ 4578 0034 FFF7FEFF 		bl	dir_find
+ 4579              	.LVL527:
+2859:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) {				/* Failed to find the object */
+ 4580              		.loc 1 2859 4 is_stmt 1 view .LVU1513
+2859:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) {				/* Failed to find the object */
+ 4581              		.loc 1 2859 7 is_stmt 0 view .LVU1514
+ 4582 0038 94F82F20 		ldrb	r2, [r4, #47]	@ zero_extendqisi2
+ 4583              	.LVL528:
+2860:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) {	/* Object is not found */
+ 4584              		.loc 1 2860 4 is_stmt 1 view .LVU1515
+2860:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) {	/* Object is not found */
+ 4585              		.loc 1 2860 7 is_stmt 0 view .LVU1516
+ 4586 003c 0346     		mov	r3, r0
+ 4587 003e F8B9     		cbnz	r0, .L347
+2872:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Get into the sub-directory */
+ 4588              		.loc 1 2872 4 is_stmt 1 view .LVU1517
+2872:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Get into the sub-directory */
+ARM GAS  /tmp/cc5lWXRL.s 			page 206
+
+
+ 4589              		.loc 1 2872 7 is_stmt 0 view .LVU1518
+ 4590 0040 12F0040F 		tst	r2, #4
+ 4591 0044 19D1     		bne	.L341
+2874:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_NO_PATH; break;
+ 4592              		.loc 1 2874 4 is_stmt 1 view .LVU1519
+2874:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_NO_PATH; break;
+ 4593              		.loc 1 2874 13 is_stmt 0 view .LVU1520
+ 4594 0046 A379     		ldrb	r3, [r4, #6]	@ zero_extendqisi2
+2874:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_NO_PATH; break;
+ 4595              		.loc 1 2874 7 view .LVU1521
+ 4596 0048 13F0100F 		tst	r3, #16
+ 4597 004c 1FD0     		beq	.L344
+2888:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4598              		.loc 1 2888 5 is_stmt 1 view .LVU1522
+2888:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4599              		.loc 1 2888 32 is_stmt 0 view .LVU1523
+ 4600 004e 05F13403 		add	r3, r5, #52
+2888:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4601              		.loc 1 2888 44 view .LVU1524
+ 4602 0052 6169     		ldr	r1, [r4, #20]
+2888:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4603              		.loc 1 2888 53 view .LVU1525
+ 4604 0054 AA89     		ldrh	r2, [r5, #12]
+ 4605              	.LVL529:
+2888:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4606              		.loc 1 2888 51 view .LVU1526
+ 4607 0056 B1FBF2F0 		udiv	r0, r1, r2
+ 4608              	.LVL530:
+2888:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4609              		.loc 1 2888 51 view .LVU1527
+ 4610 005a 02FB1011 		mls	r1, r2, r0, r1
+2888:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4611              		.loc 1 2888 19 view .LVU1528
+ 4612 005e 1944     		add	r1, r1, r3
+ 4613 0060 2846     		mov	r0, r5
+ 4614 0062 FFF7FEFF 		bl	ld_clust
+ 4615              	.LVL531:
+2888:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4616              		.loc 1 2888 17 view .LVU1529
+ 4617 0066 A060     		str	r0, [r4, #8]
+2855:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = create_name(dp, &path);	/* Get a segment name of the path */
+ 4618              		.loc 1 2855 9 is_stmt 1 view .LVU1530
+2856:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 4619              		.loc 1 2856 8 is_stmt 0 view .LVU1531
+ 4620 0068 DDE7     		b	.L340
+ 4621              	.LVL532:
+ 4622              	.L346:
+2851:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = dir_sdi(dp, 0);
+ 4623              		.loc 1 2851 3 is_stmt 1 view .LVU1532
+2851:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = dir_sdi(dp, 0);
+ 4624              		.loc 1 2851 18 is_stmt 0 view .LVU1533
+ 4625 006a 8023     		movs	r3, #128
+ 4626 006c 84F82F30 		strb	r3, [r4, #47]
+2852:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4627              		.loc 1 2852 3 is_stmt 1 view .LVU1534
+2852:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4628              		.loc 1 2852 9 is_stmt 0 view .LVU1535
+ARM GAS  /tmp/cc5lWXRL.s 			page 207
+
+
+ 4629 0070 1146     		mov	r1, r2
+ 4630              	.LVL533:
+2852:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4631              		.loc 1 2852 9 view .LVU1536
+ 4632 0072 2046     		mov	r0, r4
+ 4633              	.LVL534:
+2852:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4634              		.loc 1 2852 9 view .LVU1537
+ 4635 0074 FFF7FEFF 		bl	dir_sdi
+ 4636              	.LVL535:
+ 4637 0078 0346     		mov	r3, r0
+ 4638              	.LVL536:
+ 4639              	.L341:
+2893:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 4640              		.loc 1 2893 2 is_stmt 1 view .LVU1538
+2894:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4641              		.loc 1 2894 1 is_stmt 0 view .LVU1539
+ 4642 007a 1846     		mov	r0, r3
+ 4643 007c 03B0     		add	sp, sp, #12
+ 4644              	.LCFI32:
+ 4645              		.cfi_remember_state
+ 4646              		.cfi_def_cfa_offset 12
+ 4647              		@ sp needed
+ 4648 007e 30BD     		pop	{r4, r5, pc}
+ 4649              	.LVL537:
+ 4650              	.L347:
+ 4651              	.LCFI33:
+ 4652              		.cfi_restore_state
+2861:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, stay there */
+ 4653              		.loc 1 2861 5 is_stmt 1 view .LVU1540
+2861:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, stay there */
+ 4654              		.loc 1 2861 8 is_stmt 0 view .LVU1541
+ 4655 0080 0428     		cmp	r0, #4
+ 4656 0082 FAD1     		bne	.L341
+2862:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (!(ns & NS_LAST)) continue;	/* Continue to follow if not last segment */
+ 4657              		.loc 1 2862 6 is_stmt 1 view .LVU1542
+2867:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4658              		.loc 1 2867 7 view .LVU1543
+2867:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4659              		.loc 1 2867 10 is_stmt 0 view .LVU1544
+ 4660 0084 12F0040F 		tst	r2, #4
+ 4661 0088 F7D1     		bne	.L341
+2867:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 4662              		.loc 1 2867 32 view .LVU1545
+ 4663 008a 0523     		movs	r3, #5
+ 4664 008c F5E7     		b	.L341
+ 4665              	.L344:
+2875:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4666              		.loc 1 2875 9 view .LVU1546
+ 4667 008e 0523     		movs	r3, #5
+ 4668 0090 F3E7     		b	.L341
+ 4669              		.cfi_endproc
+ 4670              	.LFE1216:
+ 4672              		.section	.text.dir_alloc,"ax",%progbits
+ 4673              		.align	1
+ 4674              		.syntax unified
+ 4675              		.thumb
+ARM GAS  /tmp/cc5lWXRL.s 			page 208
+
+
+ 4676              		.thumb_func
+ 4677              		.fpu fpv5-d16
+ 4679              	dir_alloc:
+ 4680              	.LVL538:
+ 4681              	.LFB1207:
+1593:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 4682              		.loc 1 1593 1 is_stmt 1 view -0
+ 4683              		.cfi_startproc
+ 4684              		@ args = 0, pretend = 0, frame = 0
+ 4685              		@ frame_needed = 0, uses_anonymous_args = 0
+1593:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 4686              		.loc 1 1593 1 is_stmt 0 view .LVU1548
+ 4687 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 4688              	.LCFI34:
+ 4689              		.cfi_def_cfa_offset 24
+ 4690              		.cfi_offset 3, -24
+ 4691              		.cfi_offset 4, -20
+ 4692              		.cfi_offset 5, -16
+ 4693              		.cfi_offset 6, -12
+ 4694              		.cfi_offset 7, -8
+ 4695              		.cfi_offset 14, -4
+ 4696 0002 0446     		mov	r4, r0
+ 4697 0004 0E46     		mov	r6, r1
+1594:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT n;
+ 4698              		.loc 1 1594 2 is_stmt 1 view .LVU1549
+1595:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+ 4699              		.loc 1 1595 2 view .LVU1550
+1596:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4700              		.loc 1 1596 2 view .LVU1551
+1596:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4701              		.loc 1 1596 9 is_stmt 0 view .LVU1552
+ 4702 0006 0768     		ldr	r7, [r0]
+ 4703              	.LVL539:
+1599:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 4704              		.loc 1 1599 2 is_stmt 1 view .LVU1553
+1599:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 4705              		.loc 1 1599 8 is_stmt 0 view .LVU1554
+ 4706 0008 0021     		movs	r1, #0
+ 4707              	.LVL540:
+1599:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 4708              		.loc 1 1599 8 view .LVU1555
+ 4709 000a FFF7FEFF 		bl	dir_sdi
+ 4710              	.LVL541:
+1600:Middlewares/Third_Party/FatFs/src/ff.c **** 		n = 0;
+ 4711              		.loc 1 1600 2 is_stmt 1 view .LVU1556
+1600:Middlewares/Third_Party/FatFs/src/ff.c **** 		n = 0;
+ 4712              		.loc 1 1600 5 is_stmt 0 view .LVU1557
+ 4713 000e 0246     		mov	r2, r0
+ 4714 0010 B8B9     		cbnz	r0, .L349
+1601:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+ 4715              		.loc 1 1601 5 view .LVU1558
+ 4716 0012 0025     		movs	r5, #0
+ 4717 0014 06E0     		b	.L351
+ 4718              	.LVL542:
+ 4719              	.L353:
+1612:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 4720              		.loc 1 1612 7 view .LVU1559
+ARM GAS  /tmp/cc5lWXRL.s 			page 209
+
+
+ 4721 0016 0025     		movs	r5, #0
+ 4722              	.LVL543:
+ 4723              	.L350:
+1614:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (res == FR_OK);	/* Next entry with table stretch enabled */
+ 4724              		.loc 1 1614 4 is_stmt 1 view .LVU1560
+1614:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (res == FR_OK);	/* Next entry with table stretch enabled */
+ 4725              		.loc 1 1614 10 is_stmt 0 view .LVU1561
+ 4726 0018 0121     		movs	r1, #1
+ 4727 001a 2046     		mov	r0, r4
+ 4728              	.LVL544:
+1614:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (res == FR_OK);	/* Next entry with table stretch enabled */
+ 4729              		.loc 1 1614 10 view .LVU1562
+ 4730 001c FFF7FEFF 		bl	dir_next
+ 4731              	.LVL545:
+1615:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 4732              		.loc 1 1615 11 is_stmt 1 view .LVU1563
+1615:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 4733              		.loc 1 1615 3 is_stmt 0 view .LVU1564
+ 4734 0020 0246     		mov	r2, r0
+ 4735 0022 70B9     		cbnz	r0, .L349
+ 4736              	.LVL546:
+ 4737              	.L351:
+1602:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = move_window(fs, dp->sect);
+ 4738              		.loc 1 1602 3 is_stmt 1 view .LVU1565
+1603:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 4739              		.loc 1 1603 4 view .LVU1566
+1603:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 4740              		.loc 1 1603 10 is_stmt 0 view .LVU1567
+ 4741 0024 E169     		ldr	r1, [r4, #28]
+ 4742 0026 3846     		mov	r0, r7
+ 4743              	.LVL547:
+1603:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) break;
+ 4744              		.loc 1 1603 10 view .LVU1568
+ 4745 0028 FFF7FEFF 		bl	move_window
+ 4746              	.LVL548:
+1604:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 4747              		.loc 1 1604 4 is_stmt 1 view .LVU1569
+1604:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 4748              		.loc 1 1604 7 is_stmt 0 view .LVU1570
+ 4749 002c 0246     		mov	r2, r0
+ 4750 002e 40B9     		cbnz	r0, .L349
+1608:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 4751              		.loc 1 1608 4 is_stmt 1 view .LVU1571
+1608:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 4752              		.loc 1 1608 10 is_stmt 0 view .LVU1572
+ 4753 0030 236A     		ldr	r3, [r4, #32]
+1608:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 4754              		.loc 1 1608 15 view .LVU1573
+ 4755 0032 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+1608:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 4756              		.loc 1 1608 7 view .LVU1574
+ 4757 0034 002B     		cmp	r3, #0
+ 4758 0036 18BF     		it	ne
+ 4759 0038 E52B     		cmpne	r3, #229
+ 4760 003a ECD1     		bne	.L353
+1610:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 4761              		.loc 1 1610 5 is_stmt 1 view .LVU1575
+ARM GAS  /tmp/cc5lWXRL.s 			page 210
+
+
+1610:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 4762              		.loc 1 1610 8 is_stmt 0 view .LVU1576
+ 4763 003c 0135     		adds	r5, r5, #1
+ 4764              	.LVL549:
+1610:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 4765              		.loc 1 1610 8 view .LVU1577
+ 4766 003e B542     		cmp	r5, r6
+ 4767 0040 EAD1     		bne	.L350
+ 4768              	.LVL550:
+ 4769              	.L349:
+1618:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 4770              		.loc 1 1618 2 is_stmt 1 view .LVU1578
+1618:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 4771              		.loc 1 1618 5 is_stmt 0 view .LVU1579
+ 4772 0042 042A     		cmp	r2, #4
+ 4773 0044 01D0     		beq	.L356
+ 4774              	.LVL551:
+ 4775              	.L352:
+1619:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 4776              		.loc 1 1619 2 is_stmt 1 view .LVU1580
+1620:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4777              		.loc 1 1620 1 is_stmt 0 view .LVU1581
+ 4778 0046 1046     		mov	r0, r2
+ 4779 0048 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 4780              	.LVL552:
+ 4781              	.L356:
+1618:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 4782              		.loc 1 1618 29 view .LVU1582
+ 4783 004a 0722     		movs	r2, #7
+ 4784              	.LVL553:
+1618:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 4785              		.loc 1 1618 29 view .LVU1583
+ 4786 004c FBE7     		b	.L352
+ 4787              		.cfi_endproc
+ 4788              	.LFE1207:
+ 4790              		.section	.text.dir_register,"ax",%progbits
+ 4791              		.align	1
+ 4792              		.syntax unified
+ 4793              		.thumb
+ 4794              		.thumb_func
+ 4795              		.fpu fpv5-d16
+ 4797              	dir_register:
+ 4798              	.LVL554:
+ 4799              	.LFB1212:
+2295:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 4800              		.loc 1 2295 1 is_stmt 1 view -0
+ 4801              		.cfi_startproc
+ 4802              		@ args = 0, pretend = 0, frame = 0
+ 4803              		@ frame_needed = 0, uses_anonymous_args = 0
+2295:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 4804              		.loc 1 2295 1 is_stmt 0 view .LVU1585
+ 4805 0000 70B5     		push	{r4, r5, r6, lr}
+ 4806              	.LCFI35:
+ 4807              		.cfi_def_cfa_offset 16
+ 4808              		.cfi_offset 4, -16
+ 4809              		.cfi_offset 5, -12
+ 4810              		.cfi_offset 6, -8
+ARM GAS  /tmp/cc5lWXRL.s 			page 211
+
+
+ 4811              		.cfi_offset 14, -4
+ 4812 0002 0446     		mov	r4, r0
+2296:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+ 4813              		.loc 1 2296 2 is_stmt 1 view .LVU1586
+2297:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+ 4814              		.loc 1 2297 2 view .LVU1587
+2297:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+ 4815              		.loc 1 2297 9 is_stmt 0 view .LVU1588
+ 4816 0004 0668     		ldr	r6, [r0]
+ 4817              	.LVL555:
+2366:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4818              		.loc 1 2366 2 is_stmt 1 view .LVU1589
+2366:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4819              		.loc 1 2366 8 is_stmt 0 view .LVU1590
+ 4820 0006 0121     		movs	r1, #1
+ 4821 0008 FFF7FEFF 		bl	dir_alloc
+ 4822              	.LVL556:
+2371:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, dp->sect);
+ 4823              		.loc 1 2371 2 is_stmt 1 view .LVU1591
+2371:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, dp->sect);
+ 4824              		.loc 1 2371 5 is_stmt 0 view .LVU1592
+ 4825 000c 0546     		mov	r5, r0
+ 4826 000e 08B1     		cbz	r0, .L360
+ 4827              	.LVL557:
+ 4828              	.L358:
+2383:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 4829              		.loc 1 2383 2 is_stmt 1 view .LVU1593
+2384:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4830              		.loc 1 2384 1 is_stmt 0 view .LVU1594
+ 4831 0010 2846     		mov	r0, r5
+ 4832 0012 70BD     		pop	{r4, r5, r6, pc}
+ 4833              	.LVL558:
+ 4834              	.L360:
+2372:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+ 4835              		.loc 1 2372 3 is_stmt 1 view .LVU1595
+2372:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+ 4836              		.loc 1 2372 9 is_stmt 0 view .LVU1596
+ 4837 0014 E169     		ldr	r1, [r4, #28]
+ 4838 0016 3046     		mov	r0, r6
+ 4839              	.LVL559:
+2372:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+ 4840              		.loc 1 2372 9 view .LVU1597
+ 4841 0018 FFF7FEFF 		bl	move_window
+ 4842              	.LVL560:
+2373:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(dp->dir, 0, SZDIRE);	/* Clean the entry */
+ 4843              		.loc 1 2373 3 is_stmt 1 view .LVU1598
+2373:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(dp->dir, 0, SZDIRE);	/* Clean the entry */
+ 4844              		.loc 1 2373 6 is_stmt 0 view .LVU1599
+ 4845 001c 0546     		mov	r5, r0
+ 4846 001e 0028     		cmp	r0, #0
+ 4847 0020 F6D1     		bne	.L358
+2374:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_cpy(dp->dir + DIR_Name, dp->fn, 11);	/* Put SFN */
+ 4848              		.loc 1 2374 4 is_stmt 1 view .LVU1600
+ 4849 0022 2022     		movs	r2, #32
+ 4850 0024 0021     		movs	r1, #0
+ 4851 0026 206A     		ldr	r0, [r4, #32]
+ 4852              	.LVL561:
+ARM GAS  /tmp/cc5lWXRL.s 			page 212
+
+
+2374:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_cpy(dp->dir + DIR_Name, dp->fn, 11);	/* Put SFN */
+ 4853              		.loc 1 2374 4 is_stmt 0 view .LVU1601
+ 4854 0028 FFF7FEFF 		bl	mem_set
+ 4855              	.LVL562:
+2375:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+ 4856              		.loc 1 2375 4 is_stmt 1 view .LVU1602
+ 4857 002c 0B22     		movs	r2, #11
+ 4858 002e 04F12401 		add	r1, r4, #36
+ 4859 0032 206A     		ldr	r0, [r4, #32]
+ 4860 0034 FFF7FEFF 		bl	mem_cpy
+ 4861              	.LVL563:
+2379:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 4862              		.loc 1 2379 4 view .LVU1603
+2379:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 4863              		.loc 1 2379 14 is_stmt 0 view .LVU1604
+ 4864 0038 0123     		movs	r3, #1
+ 4865 003a F370     		strb	r3, [r6, #3]
+ 4866 003c E8E7     		b	.L358
+ 4867              		.cfi_endproc
+ 4868              	.LFE1212:
+ 4870              		.section	.text.dir_read,"ax",%progbits
+ 4871              		.align	1
+ 4872              		.syntax unified
+ 4873              		.thumb
+ 4874              		.thumb_func
+ 4875              		.fpu fpv5-d16
+ 4877              	dir_read:
+ 4878              	.LVL564:
+ 4879              	.LFB1210:
+2135:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_NO_FILE;
+ 4880              		.loc 1 2135 1 is_stmt 1 view -0
+ 4881              		.cfi_startproc
+ 4882              		@ args = 0, pretend = 0, frame = 0
+ 4883              		@ frame_needed = 0, uses_anonymous_args = 0
+2135:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res = FR_NO_FILE;
+ 4884              		.loc 1 2135 1 is_stmt 0 view .LVU1606
+ 4885 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 4886              	.LCFI36:
+ 4887              		.cfi_def_cfa_offset 24
+ 4888              		.cfi_offset 3, -24
+ 4889              		.cfi_offset 4, -20
+ 4890              		.cfi_offset 5, -16
+ 4891              		.cfi_offset 6, -12
+ 4892              		.cfi_offset 7, -8
+ 4893              		.cfi_offset 14, -4
+ 4894 0002 0446     		mov	r4, r0
+ 4895 0004 0E46     		mov	r6, r1
+2136:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+ 4896              		.loc 1 2136 2 is_stmt 1 view .LVU1607
+ 4897              	.LVL565:
+2137:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE a, c;
+ 4898              		.loc 1 2137 2 view .LVU1608
+2137:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE a, c;
+ 4899              		.loc 1 2137 9 is_stmt 0 view .LVU1609
+ 4900 0006 0568     		ldr	r5, [r0]
+ 4901              	.LVL566:
+2138:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0
+ARM GAS  /tmp/cc5lWXRL.s 			page 213
+
+
+ 4902              		.loc 1 2138 2 is_stmt 1 view .LVU1610
+2143:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, dp->sect);
+ 4903              		.loc 1 2143 2 view .LVU1611
+2136:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs = dp->obj.fs;
+ 4904              		.loc 1 2136 10 is_stmt 0 view .LVU1612
+ 4905 0008 0427     		movs	r7, #4
+2143:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, dp->sect);
+ 4906              		.loc 1 2143 8 view .LVU1613
+ 4907 000a 05E0     		b	.L362
+ 4908              	.LVL567:
+ 4909              	.L364:
+2193:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+ 4910              		.loc 1 2193 3 is_stmt 1 view .LVU1614
+2193:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+ 4911              		.loc 1 2193 9 is_stmt 0 view .LVU1615
+ 4912 000c 0021     		movs	r1, #0
+ 4913 000e 2046     		mov	r0, r4
+ 4914              	.LVL568:
+2193:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+ 4915              		.loc 1 2193 9 view .LVU1616
+ 4916 0010 FFF7FEFF 		bl	dir_next
+ 4917              	.LVL569:
+2194:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 4918              		.loc 1 2194 3 is_stmt 1 view .LVU1617
+2194:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 4919              		.loc 1 2194 6 is_stmt 0 view .LVU1618
+ 4920 0014 0746     		mov	r7, r0
+ 4921 0016 E8B9     		cbnz	r0, .L363
+ 4922              	.LVL570:
+ 4923              	.L362:
+2143:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, dp->sect);
+ 4924              		.loc 1 2143 8 is_stmt 1 view .LVU1619
+2143:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, dp->sect);
+ 4925              		.loc 1 2143 11 is_stmt 0 view .LVU1620
+ 4926 0018 E169     		ldr	r1, [r4, #28]
+2143:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = move_window(fs, dp->sect);
+ 4927              		.loc 1 2143 8 view .LVU1621
+ 4928 001a D9B1     		cbz	r1, .L363
+2144:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+ 4929              		.loc 1 2144 3 is_stmt 1 view .LVU1622
+2144:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res != FR_OK) break;
+ 4930              		.loc 1 2144 9 is_stmt 0 view .LVU1623
+ 4931 001c 2846     		mov	r0, r5
+ 4932 001e FFF7FEFF 		bl	move_window
+ 4933              	.LVL571:
+2145:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = dp->dir[DIR_Name];	/* Test for the entry type */
+ 4934              		.loc 1 2145 3 is_stmt 1 view .LVU1624
+2145:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = dp->dir[DIR_Name];	/* Test for the entry type */
+ 4935              		.loc 1 2145 6 is_stmt 0 view .LVU1625
+ 4936 0022 0746     		mov	r7, r0
+ 4937 0024 B0B9     		cbnz	r0, .L363
+2146:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == 0) {
+ 4938              		.loc 1 2146 3 is_stmt 1 view .LVU1626
+2146:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == 0) {
+ 4939              		.loc 1 2146 9 is_stmt 0 view .LVU1627
+ 4940 0026 236A     		ldr	r3, [r4, #32]
+2146:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == 0) {
+ARM GAS  /tmp/cc5lWXRL.s 			page 214
+
+
+ 4941              		.loc 1 2146 5 view .LVU1628
+ 4942 0028 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
+ 4943              	.LVL572:
+2147:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_NO_FILE; break; /* Reached to end of the directory */
+ 4944              		.loc 1 2147 3 is_stmt 1 view .LVU1629
+2147:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_NO_FILE; break; /* Reached to end of the directory */
+ 4945              		.loc 1 2147 6 is_stmt 0 view .LVU1630
+ 4946 002a 92B1     		cbz	r2, .L367
+2167:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+ 4947              		.loc 1 2167 4 is_stmt 1 view .LVU1631
+2167:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+ 4948              		.loc 1 2167 30 is_stmt 0 view .LVU1632
+ 4949 002c DB7A     		ldrb	r3, [r3, #11]	@ zero_extendqisi2
+2167:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+ 4950              		.loc 1 2167 21 view .LVU1633
+ 4951 002e 03F03F03 		and	r3, r3, #63
+ 4952              	.LVL573:
+2167:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0	/* LFN configuration */
+ 4953              		.loc 1 2167 17 view .LVU1634
+ 4954 0032 A371     		strb	r3, [r4, #6]
+2188:Middlewares/Third_Party/FatFs/src/ff.c **** 				break;
+ 4955              		.loc 1 2188 4 is_stmt 1 view .LVU1635
+2188:Middlewares/Third_Party/FatFs/src/ff.c **** 				break;
+ 4956              		.loc 1 2188 7 is_stmt 0 view .LVU1636
+ 4957 0034 E52A     		cmp	r2, #229
+ 4958 0036 18BF     		it	ne
+ 4959 0038 2E2A     		cmpne	r2, #46
+ 4960 003a E7D0     		beq	.L364
+2188:Middlewares/Third_Party/FatFs/src/ff.c **** 				break;
+ 4961              		.loc 1 2188 30 discriminator 1 view .LVU1637
+ 4962 003c 0F2B     		cmp	r3, #15
+ 4963 003e E5D0     		beq	.L364
+2188:Middlewares/Third_Party/FatFs/src/ff.c **** 				break;
+ 4964              		.loc 1 2188 57 discriminator 2 view .LVU1638
+ 4965 0040 23F02003 		bic	r3, r3, #32
+ 4966              	.LVL574:
+2188:Middlewares/Third_Party/FatFs/src/ff.c **** 				break;
+ 4967              		.loc 1 2188 48 discriminator 2 view .LVU1639
+ 4968 0044 082B     		cmp	r3, #8
+ 4969 0046 14BF     		ite	ne
+ 4970 0048 0023     		movne	r3, #0
+ 4971 004a 0123     		moveq	r3, #1
+2188:Middlewares/Third_Party/FatFs/src/ff.c **** 				break;
+ 4972              		.loc 1 2188 45 discriminator 2 view .LVU1640
+ 4973 004c B342     		cmp	r3, r6
+ 4974 004e DDD1     		bne	.L364
+ 4975 0050 00E0     		b	.L363
+ 4976              	.LVL575:
+ 4977              	.L367:
+2148:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 4978              		.loc 1 2148 8 view .LVU1641
+ 4979 0052 0427     		movs	r7, #4
+ 4980              	.LVL576:
+ 4981              	.L363:
+2197:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 4982              		.loc 1 2197 2 is_stmt 1 view .LVU1642
+2197:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ARM GAS  /tmp/cc5lWXRL.s 			page 215
+
+
+ 4983              		.loc 1 2197 5 is_stmt 0 view .LVU1643
+ 4984 0054 0FB1     		cbz	r7, .L366
+2197:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 4985              		.loc 1 2197 20 is_stmt 1 discriminator 1 view .LVU1644
+2197:Middlewares/Third_Party/FatFs/src/ff.c **** 	return res;
+ 4986              		.loc 1 2197 29 is_stmt 0 discriminator 1 view .LVU1645
+ 4987 0056 0023     		movs	r3, #0
+ 4988 0058 E361     		str	r3, [r4, #28]
+ 4989              	.L366:
+2198:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 4990              		.loc 1 2198 2 is_stmt 1 view .LVU1646
+2199:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4991              		.loc 1 2199 1 is_stmt 0 view .LVU1647
+ 4992 005a 3846     		mov	r0, r7
+ 4993 005c F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+2199:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 4994              		.loc 1 2199 1 view .LVU1648
+ 4995              		.cfi_endproc
+ 4996              	.LFE1210:
+ 4998              		.section	.text.sync_fs,"ax",%progbits
+ 4999              		.align	1
+ 5000              		.syntax unified
+ 5001              		.thumb
+ 5002              		.thumb_func
+ 5003              		.fpu fpv5-d16
+ 5005              	sync_fs:
+ 5006              	.LVL577:
+ 5007              	.LFB1198:
+ 947:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 5008              		.loc 1 947 1 is_stmt 1 view -0
+ 5009              		.cfi_startproc
+ 5010              		@ args = 0, pretend = 0, frame = 0
+ 5011              		@ frame_needed = 0, uses_anonymous_args = 0
+ 947:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 5012              		.loc 1 947 1 is_stmt 0 view .LVU1650
+ 5013 0000 70B5     		push	{r4, r5, r6, lr}
+ 5014              	.LCFI37:
+ 5015              		.cfi_def_cfa_offset 16
+ 5016              		.cfi_offset 4, -16
+ 5017              		.cfi_offset 5, -12
+ 5018              		.cfi_offset 6, -8
+ 5019              		.cfi_offset 14, -4
+ 5020 0002 0446     		mov	r4, r0
+ 948:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5021              		.loc 1 948 2 is_stmt 1 view .LVU1651
+ 951:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 5022              		.loc 1 951 2 view .LVU1652
+ 951:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 5023              		.loc 1 951 8 is_stmt 0 view .LVU1653
+ 5024 0004 FFF7FEFF 		bl	sync_window
+ 5025              	.LVL578:
+ 952:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Update FSInfo sector if needed */
+ 5026              		.loc 1 952 2 is_stmt 1 view .LVU1654
+ 952:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Update FSInfo sector if needed */
+ 5027              		.loc 1 952 5 is_stmt 0 view .LVU1655
+ 5028 0008 0546     		mov	r5, r0
+ 5029 000a 48B9     		cbnz	r0, .L370
+ARM GAS  /tmp/cc5lWXRL.s 			page 216
+
+
+ 954:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Create FSInfo structure */
+ 5030              		.loc 1 954 3 is_stmt 1 view .LVU1656
+ 954:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Create FSInfo structure */
+ 5031              		.loc 1 954 9 is_stmt 0 view .LVU1657
+ 5032 000c 2378     		ldrb	r3, [r4]	@ zero_extendqisi2
+ 954:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Create FSInfo structure */
+ 5033              		.loc 1 954 6 view .LVU1658
+ 5034 000e 032B     		cmp	r3, #3
+ 5035 0010 08D0     		beq	.L374
+ 5036              	.LVL579:
+ 5037              	.L371:
+ 968:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 5038              		.loc 1 968 3 is_stmt 1 view .LVU1659
+ 968:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 5039              		.loc 1 968 7 is_stmt 0 view .LVU1660
+ 5040 0012 0022     		movs	r2, #0
+ 5041 0014 1146     		mov	r1, r2
+ 5042 0016 6078     		ldrb	r0, [r4, #1]	@ zero_extendqisi2
+ 5043 0018 FFF7FEFF 		bl	disk_ioctl
+ 5044              	.LVL580:
+ 968:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 5045              		.loc 1 968 6 view .LVU1661
+ 5046 001c 00B1     		cbz	r0, .L370
+ 968:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 5047              		.loc 1 968 56 view .LVU1662
+ 5048 001e 0125     		movs	r5, #1
+ 5049              	.L370:
+ 5050              	.LVL581:
+ 971:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 5051              		.loc 1 971 2 is_stmt 1 view .LVU1663
+ 972:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5052              		.loc 1 972 1 is_stmt 0 view .LVU1664
+ 5053 0020 2846     		mov	r0, r5
+ 5054 0022 70BD     		pop	{r4, r5, r6, pc}
+ 5055              	.LVL582:
+ 5056              	.L374:
+ 954:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Create FSInfo structure */
+ 5057              		.loc 1 954 36 discriminator 1 view .LVU1665
+ 5058 0024 2379     		ldrb	r3, [r4, #4]	@ zero_extendqisi2
+ 954:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Create FSInfo structure */
+ 5059              		.loc 1 954 31 discriminator 1 view .LVU1666
+ 5060 0026 012B     		cmp	r3, #1
+ 5061 0028 F3D1     		bne	.L371
+ 956:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(fs->win + BS_55AA, 0xAA55);
+ 5062              		.loc 1 956 4 is_stmt 1 view .LVU1667
+ 956:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(fs->win + BS_55AA, 0xAA55);
+ 5063              		.loc 1 956 14 is_stmt 0 view .LVU1668
+ 5064 002a 04F13406 		add	r6, r4, #52
+ 956:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(fs->win + BS_55AA, 0xAA55);
+ 5065              		.loc 1 956 4 view .LVU1669
+ 5066 002e A289     		ldrh	r2, [r4, #12]
+ 5067 0030 0021     		movs	r1, #0
+ 5068 0032 3046     		mov	r0, r6
+ 5069              	.LVL583:
+ 956:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(fs->win + BS_55AA, 0xAA55);
+ 5070              		.loc 1 956 4 view .LVU1670
+ 5071 0034 FFF7FEFF 		bl	mem_set
+ARM GAS  /tmp/cc5lWXRL.s 			page 217
+
+
+ 5072              	.LVL584:
+ 957:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(fs->win + FSI_LeadSig, 0x41615252);
+ 5073              		.loc 1 957 4 is_stmt 1 view .LVU1671
+ 5074 0038 4AF65521 		movw	r1, #43605
+ 5075 003c 04F23220 		addw	r0, r4, #562
+ 5076 0040 FFF7FEFF 		bl	st_word
+ 5077              	.LVL585:
+ 958:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(fs->win + FSI_StrucSig, 0x61417272);
+ 5078              		.loc 1 958 4 view .LVU1672
+ 5079 0044 0E49     		ldr	r1, .L375
+ 5080 0046 3046     		mov	r0, r6
+ 5081 0048 FFF7FEFF 		bl	st_dword
+ 5082              	.LVL586:
+ 959:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(fs->win + FSI_Free_Count, fs->free_clst);
+ 5083              		.loc 1 959 4 view .LVU1673
+ 5084 004c 0D49     		ldr	r1, .L375+4
+ 5085 004e 04F50670 		add	r0, r4, #536
+ 5086 0052 FFF7FEFF 		bl	st_dword
+ 5087              	.LVL587:
+ 960:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(fs->win + FSI_Nxt_Free, fs->last_clst);
+ 5088              		.loc 1 960 4 view .LVU1674
+ 5089 0056 6169     		ldr	r1, [r4, #20]
+ 5090 0058 04F50770 		add	r0, r4, #540
+ 5091 005c FFF7FEFF 		bl	st_dword
+ 5092              	.LVL588:
+ 961:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Write it into the FSInfo sector */
+ 5093              		.loc 1 961 4 view .LVU1675
+ 5094 0060 2169     		ldr	r1, [r4, #16]
+ 5095 0062 04F50870 		add	r0, r4, #544
+ 5096 0066 FFF7FEFF 		bl	st_dword
+ 5097              	.LVL589:
+ 963:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(fs->drv, fs->win, fs->winsect, 1);
+ 5098              		.loc 1 963 4 view .LVU1676
+ 963:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(fs->drv, fs->win, fs->winsect, 1);
+ 5099              		.loc 1 963 20 is_stmt 0 view .LVU1677
+ 5100 006a 226A     		ldr	r2, [r4, #32]
+ 963:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(fs->drv, fs->win, fs->winsect, 1);
+ 5101              		.loc 1 963 30 view .LVU1678
+ 5102 006c 0132     		adds	r2, r2, #1
+ 963:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(fs->drv, fs->win, fs->winsect, 1);
+ 5103              		.loc 1 963 16 view .LVU1679
+ 5104 006e 2263     		str	r2, [r4, #48]
+ 964:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->fsi_flag = 0;
+ 5105              		.loc 1 964 4 is_stmt 1 view .LVU1680
+ 5106 0070 0123     		movs	r3, #1
+ 5107 0072 3146     		mov	r1, r6
+ 5108 0074 6078     		ldrb	r0, [r4, #1]	@ zero_extendqisi2
+ 5109 0076 FFF7FEFF 		bl	disk_write
+ 5110              	.LVL590:
+ 965:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 5111              		.loc 1 965 4 view .LVU1681
+ 965:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 5112              		.loc 1 965 17 is_stmt 0 view .LVU1682
+ 5113 007a 0023     		movs	r3, #0
+ 5114 007c 2371     		strb	r3, [r4, #4]
+ 5115 007e C8E7     		b	.L371
+ 5116              	.L376:
+ARM GAS  /tmp/cc5lWXRL.s 			page 218
+
+
+ 5117              		.align	2
+ 5118              	.L375:
+ 5119 0080 52526141 		.word	1096897106
+ 5120 0084 72724161 		.word	1631679090
+ 5121              		.cfi_endproc
+ 5122              	.LFE1198:
+ 5124              		.section	.text.f_mount,"ax",%progbits
+ 5125              		.align	1
+ 5126              		.global	f_mount
+ 5127              		.syntax unified
+ 5128              		.thumb
+ 5129              		.thumb_func
+ 5130              		.fpu fpv5-d16
+ 5132              	f_mount:
+ 5133              	.LVL591:
+ 5134              	.LFB1221:
+3265:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *cfs;
+ 5135              		.loc 1 3265 1 is_stmt 1 view -0
+ 5136              		.cfi_startproc
+ 5137              		@ args = 0, pretend = 0, frame = 16
+ 5138              		@ frame_needed = 0, uses_anonymous_args = 0
+3265:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *cfs;
+ 5139              		.loc 1 3265 1 is_stmt 0 view .LVU1684
+ 5140 0000 70B5     		push	{r4, r5, r6, lr}
+ 5141              	.LCFI38:
+ 5142              		.cfi_def_cfa_offset 16
+ 5143              		.cfi_offset 4, -16
+ 5144              		.cfi_offset 5, -12
+ 5145              		.cfi_offset 6, -8
+ 5146              		.cfi_offset 14, -4
+ 5147 0002 84B0     		sub	sp, sp, #16
+ 5148              	.LCFI39:
+ 5149              		.cfi_def_cfa_offset 32
+ 5150 0004 0190     		str	r0, [sp, #4]
+ 5151 0006 0091     		str	r1, [sp]
+ 5152 0008 1646     		mov	r6, r2
+3266:Middlewares/Third_Party/FatFs/src/ff.c **** 	int vol;
+ 5153              		.loc 1 3266 2 is_stmt 1 view .LVU1685
+3267:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 5154              		.loc 1 3267 2 view .LVU1686
+3268:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR *rp = path;
+ 5155              		.loc 1 3268 2 view .LVU1687
+3269:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5156              		.loc 1 3269 2 view .LVU1688
+3269:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5157              		.loc 1 3269 15 is_stmt 0 view .LVU1689
+ 5158 000a 0391     		str	r1, [sp, #12]
+3273:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+ 5159              		.loc 1 3273 2 is_stmt 1 view .LVU1690
+3273:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+ 5160              		.loc 1 3273 8 is_stmt 0 view .LVU1691
+ 5161 000c 03A8     		add	r0, sp, #12
+ 5162              	.LVL592:
+3273:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+ 5163              		.loc 1 3273 8 view .LVU1692
+ 5164 000e FFF7FEFF 		bl	get_ldnumber
+ 5165              	.LVL593:
+ARM GAS  /tmp/cc5lWXRL.s 			page 219
+
+
+3274:Middlewares/Third_Party/FatFs/src/ff.c **** 	cfs = FatFs[vol];					/* Pointer to fs object */
+ 5166              		.loc 1 3274 2 is_stmt 1 view .LVU1693
+3274:Middlewares/Third_Party/FatFs/src/ff.c **** 	cfs = FatFs[vol];					/* Pointer to fs object */
+ 5167              		.loc 1 3274 5 is_stmt 0 view .LVU1694
+ 5168 0012 041E     		subs	r4, r0, #0
+ 5169 0014 20DB     		blt	.L381
+3275:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5170              		.loc 1 3275 2 is_stmt 1 view .LVU1695
+3275:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5171              		.loc 1 3275 6 is_stmt 0 view .LVU1696
+ 5172 0016 114B     		ldr	r3, .L385
+ 5173 0018 53F82450 		ldr	r5, [r3, r4, lsl #2]
+ 5174              	.LVL594:
+3277:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 5175              		.loc 1 3277 2 is_stmt 1 view .LVU1697
+3277:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 5176              		.loc 1 3277 5 is_stmt 0 view .LVU1698
+ 5177 001c 25B1     		cbz	r5, .L379
+3279:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5178              		.loc 1 3279 3 is_stmt 1 view .LVU1699
+ 5179 001e 2846     		mov	r0, r5
+ 5180              	.LVL595:
+3279:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5181              		.loc 1 3279 3 is_stmt 0 view .LVU1700
+ 5182 0020 FFF7FEFF 		bl	clear_lock
+ 5183              	.LVL596:
+3284:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 5184              		.loc 1 3284 3 is_stmt 1 view .LVU1701
+3284:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 5185              		.loc 1 3284 16 is_stmt 0 view .LVU1702
+ 5186 0024 0023     		movs	r3, #0
+ 5187 0026 2B70     		strb	r3, [r5]
+ 5188              	.L379:
+3287:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fs_type = 0;				/* Clear new fs object */
+ 5189              		.loc 1 3287 2 is_stmt 1 view .LVU1703
+3287:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fs_type = 0;				/* Clear new fs object */
+ 5190              		.loc 1 3287 6 is_stmt 0 view .LVU1704
+ 5191 0028 019B     		ldr	r3, [sp, #4]
+3287:Middlewares/Third_Party/FatFs/src/ff.c **** 		fs->fs_type = 0;				/* Clear new fs object */
+ 5192              		.loc 1 3287 5 view .LVU1705
+ 5193 002a 0BB1     		cbz	r3, .L380
+3288:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT						/* Create sync object for the new volume */
+ 5194              		.loc 1 3288 3 is_stmt 1 view .LVU1706
+3288:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT						/* Create sync object for the new volume */
+ 5195              		.loc 1 3288 15 is_stmt 0 view .LVU1707
+ 5196 002c 0022     		movs	r2, #0
+ 5197 002e 1A70     		strb	r2, [r3]
+ 5198              	.L380:
+3293:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5199              		.loc 1 3293 2 is_stmt 1 view .LVU1708
+3293:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5200              		.loc 1 3293 13 is_stmt 0 view .LVU1709
+ 5201 0030 019B     		ldr	r3, [sp, #4]
+ 5202 0032 0A4A     		ldr	r2, .L385
+ 5203 0034 42F82430 		str	r3, [r2, r4, lsl #2]
+3295:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5204              		.loc 1 3295 2 is_stmt 1 view .LVU1710
+ARM GAS  /tmp/cc5lWXRL.s 			page 220
+
+
+3295:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5205              		.loc 1 3295 17 is_stmt 0 view .LVU1711
+ 5206 0038 721E     		subs	r2, r6, #1
+ 5207 003a 18BF     		it	ne
+ 5208 003c 0122     		movne	r2, #1
+3295:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5209              		.loc 1 3295 10 view .LVU1712
+ 5210 003e 002B     		cmp	r3, #0
+ 5211 0040 08BF     		it	eq
+ 5212 0042 42F00102 		orreq	r2, r2, #1
+3295:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5213              		.loc 1 3295 5 view .LVU1713
+ 5214 0046 12B1     		cbz	r2, .L384
+3295:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5215              		.loc 1 3295 30 view .LVU1714
+ 5216 0048 0020     		movs	r0, #0
+ 5217              	.LVL597:
+ 5218              	.L378:
+3299:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5219              		.loc 1 3299 1 view .LVU1715
+ 5220 004a 04B0     		add	sp, sp, #16
+ 5221              	.LCFI40:
+ 5222              		.cfi_remember_state
+ 5223              		.cfi_def_cfa_offset 16
+ 5224              		@ sp needed
+ 5225 004c 70BD     		pop	{r4, r5, r6, pc}
+ 5226              	.LVL598:
+ 5227              	.L384:
+ 5228              	.LCFI41:
+ 5229              		.cfi_restore_state
+3297:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+ 5230              		.loc 1 3297 2 is_stmt 1 view .LVU1716
+3297:Middlewares/Third_Party/FatFs/src/ff.c **** 	LEAVE_FF(fs, res);
+ 5231              		.loc 1 3297 8 is_stmt 0 view .LVU1717
+ 5232 004e 01A9     		add	r1, sp, #4
+ 5233 0050 6846     		mov	r0, sp
+ 5234 0052 FFF7FEFF 		bl	find_volume
+ 5235              	.LVL599:
+3298:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 5236              		.loc 1 3298 2 is_stmt 1 view .LVU1718
+ 5237 0056 F8E7     		b	.L378
+ 5238              	.LVL600:
+ 5239              	.L381:
+3274:Middlewares/Third_Party/FatFs/src/ff.c **** 	cfs = FatFs[vol];					/* Pointer to fs object */
+ 5240              		.loc 1 3274 22 is_stmt 0 view .LVU1719
+ 5241 0058 0B20     		movs	r0, #11
+ 5242              	.LVL601:
+3274:Middlewares/Third_Party/FatFs/src/ff.c **** 	cfs = FatFs[vol];					/* Pointer to fs object */
+ 5243              		.loc 1 3274 22 view .LVU1720
+ 5244 005a F6E7     		b	.L378
+ 5245              	.L386:
+ 5246              		.align	2
+ 5247              	.L385:
+ 5248 005c 00000000 		.word	.LANCHOR2
+ 5249              		.cfi_endproc
+ 5250              	.LFE1221:
+ 5252              		.section	.text.f_open,"ax",%progbits
+ARM GAS  /tmp/cc5lWXRL.s 			page 221
+
+
+ 5253              		.align	1
+ 5254              		.global	f_open
+ 5255              		.syntax unified
+ 5256              		.thumb
+ 5257              		.thumb_func
+ 5258              		.fpu fpv5-d16
+ 5260              	f_open:
+ 5261              	.LVL602:
+ 5262              	.LFB1222:
+3313:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 5263              		.loc 1 3313 1 is_stmt 1 view -0
+ 5264              		.cfi_startproc
+ 5265              		@ args = 0, pretend = 0, frame = 64
+ 5266              		@ frame_needed = 0, uses_anonymous_args = 0
+3313:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 5267              		.loc 1 3313 1 is_stmt 0 view .LVU1722
+ 5268 0000 2DE9F043 		push	{r4, r5, r6, r7, r8, r9, lr}
+ 5269              	.LCFI42:
+ 5270              		.cfi_def_cfa_offset 28
+ 5271              		.cfi_offset 4, -28
+ 5272              		.cfi_offset 5, -24
+ 5273              		.cfi_offset 6, -20
+ 5274              		.cfi_offset 7, -16
+ 5275              		.cfi_offset 8, -12
+ 5276              		.cfi_offset 9, -8
+ 5277              		.cfi_offset 14, -4
+ 5278 0004 91B0     		sub	sp, sp, #68
+ 5279              	.LCFI43:
+ 5280              		.cfi_def_cfa_offset 96
+ 5281 0006 0191     		str	r1, [sp, #4]
+3314:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+ 5282              		.loc 1 3314 2 is_stmt 1 view .LVU1723
+3315:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 5283              		.loc 1 3315 2 view .LVU1724
+3316:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 5284              		.loc 1 3316 2 view .LVU1725
+3318:Middlewares/Third_Party/FatFs/src/ff.c **** 	FSIZE_t ofs;
+ 5285              		.loc 1 3318 2 view .LVU1726
+3319:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5286              		.loc 1 3319 2 view .LVU1727
+3324:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5287              		.loc 1 3324 2 view .LVU1728
+3324:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5288              		.loc 1 3324 5 is_stmt 0 view .LVU1729
+ 5289 0008 0028     		cmp	r0, #0
+ 5290 000a 00F01581 		beq	.L403
+ 5291 000e 1546     		mov	r5, r2
+ 5292 0010 0646     		mov	r6, r0
+3327:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, mode);
+ 5293              		.loc 1 3327 2 is_stmt 1 view .LVU1730
+3327:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, mode);
+ 5294              		.loc 1 3327 7 is_stmt 0 view .LVU1731
+ 5295 0012 02F03F07 		and	r7, r2, #63
+ 5296              	.LVL603:
+3328:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 5297              		.loc 1 3328 2 is_stmt 1 view .LVU1732
+3328:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ARM GAS  /tmp/cc5lWXRL.s 			page 222
+
+
+ 5298              		.loc 1 3328 8 is_stmt 0 view .LVU1733
+ 5299 0016 3A46     		mov	r2, r7
+ 5300 0018 03A9     		add	r1, sp, #12
+ 5301              	.LVL604:
+3328:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 5302              		.loc 1 3328 8 view .LVU1734
+ 5303 001a 01A8     		add	r0, sp, #4
+ 5304              	.LVL605:
+3328:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 5305              		.loc 1 3328 8 view .LVU1735
+ 5306 001c FFF7FEFF 		bl	find_volume
+ 5307              	.LVL606:
+3329:Middlewares/Third_Party/FatFs/src/ff.c **** 		dj.obj.fs = fs;
+ 5308              		.loc 1 3329 2 is_stmt 1 view .LVU1736
+3329:Middlewares/Third_Party/FatFs/src/ff.c **** 		dj.obj.fs = fs;
+ 5309              		.loc 1 3329 5 is_stmt 0 view .LVU1737
+ 5310 0020 0446     		mov	r4, r0
+ 5311 0022 30B1     		cbz	r0, .L416
+ 5312              	.LVL607:
+ 5313              	.L389:
+3496:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 5314              		.loc 1 3496 16 is_stmt 1 view .LVU1738
+3499:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5315              		.loc 1 3499 2 view .LVU1739
+3499:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5316              		.loc 1 3499 5 is_stmt 0 view .LVU1740
+ 5317 0024 0CB1     		cbz	r4, .L388
+ 5318              	.LVL608:
+ 5319              	.L402:
+3499:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5320              		.loc 1 3499 20 is_stmt 1 discriminator 1 view .LVU1741
+3499:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5321              		.loc 1 3499 31 is_stmt 0 discriminator 1 view .LVU1742
+ 5322 0026 0023     		movs	r3, #0
+ 5323 0028 3360     		str	r3, [r6]
+ 5324              	.LVL609:
+ 5325              	.L388:
+3502:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5326              		.loc 1 3502 1 view .LVU1743
+ 5327 002a 2046     		mov	r0, r4
+ 5328 002c 11B0     		add	sp, sp, #68
+ 5329              	.LCFI44:
+ 5330              		.cfi_remember_state
+ 5331              		.cfi_def_cfa_offset 28
+ 5332              		@ sp needed
+ 5333 002e BDE8F083 		pop	{r4, r5, r6, r7, r8, r9, pc}
+ 5334              	.LVL610:
+ 5335              	.L416:
+ 5336              	.LCFI45:
+ 5337              		.cfi_restore_state
+3330:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+ 5338              		.loc 1 3330 3 is_stmt 1 view .LVU1744
+3330:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+ 5339              		.loc 1 3330 13 is_stmt 0 view .LVU1745
+ 5340 0032 039B     		ldr	r3, [sp, #12]
+ 5341 0034 0493     		str	r3, [sp, #16]
+3331:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&dj, path);	/* Follow the file path */
+ARM GAS  /tmp/cc5lWXRL.s 			page 223
+
+
+ 5342              		.loc 1 3331 18 is_stmt 1 view .LVU1746
+3332:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY	/* R/W configuration */
+ 5343              		.loc 1 3332 3 view .LVU1747
+3332:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY	/* R/W configuration */
+ 5344              		.loc 1 3332 9 is_stmt 0 view .LVU1748
+ 5345 0036 0199     		ldr	r1, [sp, #4]
+ 5346 0038 04A8     		add	r0, sp, #16
+ 5347              	.LVL611:
+3332:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY	/* R/W configuration */
+ 5348              		.loc 1 3332 9 view .LVU1749
+ 5349 003a FFF7FEFF 		bl	follow_path
+ 5350              	.LVL612:
+3334:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+ 5351              		.loc 1 3334 3 is_stmt 1 view .LVU1750
+3334:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+ 5352              		.loc 1 3334 6 is_stmt 0 view .LVU1751
+ 5353 003e 0446     		mov	r4, r0
+ 5354 0040 60B9     		cbnz	r0, .L390
+3335:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;
+ 5355              		.loc 1 3335 4 is_stmt 1 view .LVU1752
+3335:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;
+ 5356              		.loc 1 3335 8 is_stmt 0 view .LVU1753
+ 5357 0042 9DF93F30 		ldrsb	r3, [sp, #63]
+3335:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;
+ 5358              		.loc 1 3335 7 view .LVU1754
+ 5359 0046 002B     		cmp	r3, #0
+ 5360 0048 50DB     		blt	.L404
+3340:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 5361              		.loc 1 3340 5 is_stmt 1 view .LVU1755
+3340:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 5362              		.loc 1 3340 11 is_stmt 0 view .LVU1756
+ 5363 004a 37F00103 		bics	r3, r7, #1
+ 5364 004e 14BF     		ite	ne
+ 5365 0050 0121     		movne	r1, #1
+ 5366 0052 0021     		moveq	r1, #0
+ 5367 0054 04A8     		add	r0, sp, #16
+ 5368              	.LVL613:
+3340:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 5369              		.loc 1 3340 11 view .LVU1757
+ 5370 0056 FFF7FEFF 		bl	chk_lock
+ 5371              	.LVL614:
+ 5372 005a 0446     		mov	r4, r0
+ 5373              	.LVL615:
+ 5374              	.L390:
+3345:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) {					/* No file, create new */
+ 5375              		.loc 1 3345 3 is_stmt 1 view .LVU1758
+3345:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res != FR_OK) {					/* No file, create new */
+ 5376              		.loc 1 3345 6 is_stmt 0 view .LVU1759
+ 5377 005c 15F01C0F 		tst	r5, #28
+ 5378 0060 5AD0     		beq	.L391
+3346:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) {		/* There is no file to open, create a new entry */
+ 5379              		.loc 1 3346 4 is_stmt 1 view .LVU1760
+3346:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) {		/* There is no file to open, create a new entry */
+ 5380              		.loc 1 3346 7 is_stmt 0 view .LVU1761
+ 5381 0062 002C     		cmp	r4, #0
+ 5382 0064 4ED0     		beq	.L392
+3347:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ARM GAS  /tmp/cc5lWXRL.s 			page 224
+
+
+ 5383              		.loc 1 3347 5 is_stmt 1 view .LVU1762
+3347:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 5384              		.loc 1 3347 8 is_stmt 0 view .LVU1763
+ 5385 0066 042C     		cmp	r4, #4
+ 5386 0068 42D0     		beq	.L417
+ 5387              	.LVL616:
+ 5388              	.L393:
+3354:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 5389              		.loc 1 3354 5 is_stmt 1 view .LVU1764
+3354:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 5390              		.loc 1 3354 10 is_stmt 0 view .LVU1765
+ 5391 006a 47F00807 		orr	r7, r7, #8
+ 5392              	.LVL617:
+ 5393              	.L394:
+3363:Middlewares/Third_Party/FatFs/src/ff.c **** 				dw = GET_FATTIME();
+ 5394              		.loc 1 3363 4 is_stmt 1 view .LVU1766
+3363:Middlewares/Third_Party/FatFs/src/ff.c **** 				dw = GET_FATTIME();
+ 5395              		.loc 1 3363 7 is_stmt 0 view .LVU1767
+ 5396 006e 002C     		cmp	r4, #0
+ 5397 0070 61D1     		bne	.L395
+3363:Middlewares/Third_Party/FatFs/src/ff.c **** 				dw = GET_FATTIME();
+ 5398              		.loc 1 3363 21 discriminator 1 view .LVU1768
+ 5399 0072 17F0080F 		tst	r7, #8
+ 5400 0076 5ED0     		beq	.L395
+3364:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 5401              		.loc 1 3364 5 is_stmt 1 view .LVU1769
+3364:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 5402              		.loc 1 3364 10 is_stmt 0 view .LVU1770
+ 5403 0078 FFF7FEFF 		bl	get_fattime
+ 5404              	.LVL618:
+ 5405 007c 0546     		mov	r5, r0
+ 5406              	.LVL619:
+3392:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dj.dir + DIR_ModTime, dw);	/* Set modified time */
+ 5407              		.loc 1 3392 6 is_stmt 1 view .LVU1771
+ 5408 007e 0146     		mov	r1, r0
+ 5409 0080 0C98     		ldr	r0, [sp, #48]
+ 5410              	.LVL620:
+3392:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dj.dir + DIR_ModTime, dw);	/* Set modified time */
+ 5411              		.loc 1 3392 6 is_stmt 0 view .LVU1772
+ 5412 0082 0E30     		adds	r0, r0, #14
+ 5413 0084 FFF7FEFF 		bl	st_dword
+ 5414              	.LVL621:
+3393:Middlewares/Third_Party/FatFs/src/ff.c **** 					dj.dir[DIR_Attr] = AM_ARC;			/* Reset attribute */
+ 5415              		.loc 1 3393 6 is_stmt 1 view .LVU1773
+ 5416 0088 2946     		mov	r1, r5
+ 5417 008a 0C98     		ldr	r0, [sp, #48]
+ 5418 008c 1630     		adds	r0, r0, #22
+ 5419 008e FFF7FEFF 		bl	st_dword
+ 5420              	.LVL622:
+3394:Middlewares/Third_Party/FatFs/src/ff.c **** 					cl = ld_clust(fs, dj.dir);			/* Get cluster chain */
+ 5421              		.loc 1 3394 6 view .LVU1774
+3394:Middlewares/Third_Party/FatFs/src/ff.c **** 					cl = ld_clust(fs, dj.dir);			/* Get cluster chain */
+ 5422              		.loc 1 3394 23 is_stmt 0 view .LVU1775
+ 5423 0092 0C9B     		ldr	r3, [sp, #48]
+ 5424 0094 2022     		movs	r2, #32
+ 5425 0096 DA72     		strb	r2, [r3, #11]
+3395:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dj.dir, 0);			/* Reset file allocation info */
+ARM GAS  /tmp/cc5lWXRL.s 			page 225
+
+
+ 5426              		.loc 1 3395 6 is_stmt 1 view .LVU1776
+3395:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dj.dir, 0);			/* Reset file allocation info */
+ 5427              		.loc 1 3395 11 is_stmt 0 view .LVU1777
+ 5428 0098 DDF80C80 		ldr	r8, [sp, #12]
+3395:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dj.dir, 0);			/* Reset file allocation info */
+ 5429              		.loc 1 3395 26 view .LVU1778
+ 5430 009c DDF83090 		ldr	r9, [sp, #48]
+3395:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dj.dir, 0);			/* Reset file allocation info */
+ 5431              		.loc 1 3395 11 view .LVU1779
+ 5432 00a0 4946     		mov	r1, r9
+ 5433 00a2 4046     		mov	r0, r8
+ 5434 00a4 FFF7FEFF 		bl	ld_clust
+ 5435              	.LVL623:
+ 5436 00a8 0546     		mov	r5, r0
+ 5437              	.LVL624:
+3396:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dj.dir + DIR_FileSize, 0);
+ 5438              		.loc 1 3396 6 is_stmt 1 view .LVU1780
+ 5439 00aa 0022     		movs	r2, #0
+ 5440 00ac 4946     		mov	r1, r9
+ 5441 00ae 4046     		mov	r0, r8
+ 5442              	.LVL625:
+3396:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dj.dir + DIR_FileSize, 0);
+ 5443              		.loc 1 3396 6 is_stmt 0 view .LVU1781
+ 5444 00b0 FFF7FEFF 		bl	st_clust
+ 5445              	.LVL626:
+3397:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+ 5446              		.loc 1 3397 6 is_stmt 1 view .LVU1782
+ 5447 00b4 0021     		movs	r1, #0
+ 5448 00b6 0C98     		ldr	r0, [sp, #48]
+ 5449 00b8 1C30     		adds	r0, r0, #28
+ 5450 00ba FFF7FEFF 		bl	st_dword
+ 5451              	.LVL627:
+3398:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5452              		.loc 1 3398 6 view .LVU1783
+3398:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5453              		.loc 1 3398 16 is_stmt 0 view .LVU1784
+ 5454 00be 039B     		ldr	r3, [sp, #12]
+ 5455 00c0 0122     		movs	r2, #1
+ 5456 00c2 DA70     		strb	r2, [r3, #3]
+3400:Middlewares/Third_Party/FatFs/src/ff.c **** 						dw = fs->winsect;
+ 5457              		.loc 1 3400 6 is_stmt 1 view .LVU1785
+3400:Middlewares/Third_Party/FatFs/src/ff.c **** 						dw = fs->winsect;
+ 5458              		.loc 1 3400 9 is_stmt 0 view .LVU1786
+ 5459 00c4 BDB3     		cbz	r5, .L395
+3401:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = remove_chain(&dj.obj, cl, 0);
+ 5460              		.loc 1 3401 7 is_stmt 1 view .LVU1787
+3401:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = remove_chain(&dj.obj, cl, 0);
+ 5461              		.loc 1 3401 14 is_stmt 0 view .LVU1788
+ 5462 00c6 039B     		ldr	r3, [sp, #12]
+3401:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = remove_chain(&dj.obj, cl, 0);
+ 5463              		.loc 1 3401 10 view .LVU1789
+ 5464 00c8 D3F83080 		ldr	r8, [r3, #48]
+ 5465              	.LVL628:
+3402:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (res == FR_OK) {
+ 5466              		.loc 1 3402 7 is_stmt 1 view .LVU1790
+3402:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (res == FR_OK) {
+ 5467              		.loc 1 3402 13 is_stmt 0 view .LVU1791
+ARM GAS  /tmp/cc5lWXRL.s 			page 226
+
+
+ 5468 00cc 0022     		movs	r2, #0
+ 5469 00ce 2946     		mov	r1, r5
+ 5470 00d0 04A8     		add	r0, sp, #16
+ 5471 00d2 FFF7FEFF 		bl	remove_chain
+ 5472              	.LVL629:
+3403:Middlewares/Third_Party/FatFs/src/ff.c **** 							res = move_window(fs, dw);
+ 5473              		.loc 1 3403 7 is_stmt 1 view .LVU1792
+3403:Middlewares/Third_Party/FatFs/src/ff.c **** 							res = move_window(fs, dw);
+ 5474              		.loc 1 3403 10 is_stmt 0 view .LVU1793
+ 5475 00d6 0446     		mov	r4, r0
+ 5476 00d8 68BB     		cbnz	r0, .L395
+3404:Middlewares/Third_Party/FatFs/src/ff.c **** 							fs->last_clst = cl - 1;		/* Reuse the cluster hole */
+ 5477              		.loc 1 3404 8 is_stmt 1 view .LVU1794
+3404:Middlewares/Third_Party/FatFs/src/ff.c **** 							fs->last_clst = cl - 1;		/* Reuse the cluster hole */
+ 5478              		.loc 1 3404 14 is_stmt 0 view .LVU1795
+ 5479 00da 4146     		mov	r1, r8
+ 5480 00dc 0398     		ldr	r0, [sp, #12]
+ 5481              	.LVL630:
+3404:Middlewares/Third_Party/FatFs/src/ff.c **** 							fs->last_clst = cl - 1;		/* Reuse the cluster hole */
+ 5482              		.loc 1 3404 14 view .LVU1796
+ 5483 00de FFF7FEFF 		bl	move_window
+ 5484              	.LVL631:
+ 5485 00e2 0446     		mov	r4, r0
+ 5486              	.LVL632:
+3405:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 5487              		.loc 1 3405 8 is_stmt 1 view .LVU1797
+3405:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 5488              		.loc 1 3405 27 is_stmt 0 view .LVU1798
+ 5489 00e4 013D     		subs	r5, r5, #1
+ 5490              	.LVL633:
+3405:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 5491              		.loc 1 3405 22 view .LVU1799
+ 5492 00e6 039B     		ldr	r3, [sp, #12]
+ 5493 00e8 1D61     		str	r5, [r3, #16]
+ 5494 00ea 24E0     		b	.L395
+ 5495              	.LVL634:
+ 5496              	.L404:
+3336:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 5497              		.loc 1 3336 9 view .LVU1800
+ 5498 00ec 0624     		movs	r4, #6
+ 5499 00ee B5E7     		b	.L390
+ 5500              	.LVL635:
+ 5501              	.L417:
+3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 5502              		.loc 1 3349 6 is_stmt 1 view .LVU1801
+3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 5503              		.loc 1 3349 12 is_stmt 0 view .LVU1802
+ 5504 00f0 FFF7FEFF 		bl	enq_lock
+ 5505              	.LVL636:
+3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 5506              		.loc 1 3349 43 view .LVU1803
+ 5507 00f4 08B9     		cbnz	r0, .L418
+ 5508 00f6 1224     		movs	r4, #18
+ 5509              	.LVL637:
+3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 5510              		.loc 1 3349 43 view .LVU1804
+ 5511 00f8 B7E7     		b	.L393
+ARM GAS  /tmp/cc5lWXRL.s 			page 227
+
+
+ 5512              	.LVL638:
+ 5513              	.L418:
+3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 5514              		.loc 1 3349 25 discriminator 1 view .LVU1805
+ 5515 00fa 04A8     		add	r0, sp, #16
+ 5516 00fc FFF7FEFF 		bl	dir_register
+ 5517              	.LVL639:
+ 5518 0100 0446     		mov	r4, r0
+ 5519              	.LVL640:
+3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 5520              		.loc 1 3349 25 discriminator 1 view .LVU1806
+ 5521 0102 B2E7     		b	.L393
+ 5522              	.LVL641:
+ 5523              	.L392:
+3357:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_DENIED;
+ 5524              		.loc 1 3357 5 is_stmt 1 view .LVU1807
+3357:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_DENIED;
+ 5525              		.loc 1 3357 15 is_stmt 0 view .LVU1808
+ 5526 0104 9DF81630 		ldrb	r3, [sp, #22]	@ zero_extendqisi2
+3357:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_DENIED;
+ 5527              		.loc 1 3357 8 view .LVU1809
+ 5528 0108 13F0110F 		tst	r3, #17
+ 5529 010c 12D1     		bne	.L406
+3360:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 5530              		.loc 1 3360 6 is_stmt 1 view .LVU1810
+3360:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 5531              		.loc 1 3360 9 is_stmt 0 view .LVU1811
+ 5532 010e 15F0040F 		tst	r5, #4
+ 5533 0112 ACD0     		beq	.L394
+3360:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 5534              		.loc 1 3360 36 view .LVU1812
+ 5535 0114 0824     		movs	r4, #8
+ 5536              	.LVL642:
+3360:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 5537              		.loc 1 3360 36 view .LVU1813
+ 5538 0116 0EE0     		b	.L395
+ 5539              	.LVL643:
+ 5540              	.L391:
+3412:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (dj.obj.attr & AM_DIR) {		/* It is a directory */
+ 5541              		.loc 1 3412 4 is_stmt 1 view .LVU1814
+3412:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (dj.obj.attr & AM_DIR) {		/* It is a directory */
+ 5542              		.loc 1 3412 7 is_stmt 0 view .LVU1815
+ 5543 0118 6CB9     		cbnz	r4, .L395
+3413:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_NO_FILE;
+ 5544              		.loc 1 3413 5 is_stmt 1 view .LVU1816
+3413:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_NO_FILE;
+ 5545              		.loc 1 3413 15 is_stmt 0 view .LVU1817
+ 5546 011a 9DF81630 		ldrb	r3, [sp, #22]	@ zero_extendqisi2
+3413:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_NO_FILE;
+ 5547              		.loc 1 3413 8 view .LVU1818
+ 5548 011e 13F0100F 		tst	r3, #16
+ 5549 0122 4ED1     		bne	.L408
+3416:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = FR_DENIED;
+ 5550              		.loc 1 3416 6 is_stmt 1 view .LVU1819
+3416:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = FR_DENIED;
+ 5551              		.loc 1 3416 9 is_stmt 0 view .LVU1820
+ 5552 0124 15F0020F 		tst	r5, #2
+ARM GAS  /tmp/cc5lWXRL.s 			page 228
+
+
+ 5553 0128 05D0     		beq	.L395
+3416:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = FR_DENIED;
+ 5554              		.loc 1 3416 28 discriminator 1 view .LVU1821
+ 5555 012a 13F0010F 		tst	r3, #1
+ 5556 012e 02D0     		beq	.L395
+3417:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 5557              		.loc 1 3417 11 view .LVU1822
+ 5558 0130 0724     		movs	r4, #7
+ 5559              	.LVL644:
+3417:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 5560              		.loc 1 3417 11 view .LVU1823
+ 5561 0132 16E0     		b	.L396
+ 5562              	.LVL645:
+ 5563              	.L406:
+3358:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+ 5564              		.loc 1 3358 10 view .LVU1824
+ 5565 0134 0724     		movs	r4, #7
+ 5566              	.LVL646:
+ 5567              	.L395:
+3422:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (mode & FA_CREATE_ALWAYS)		/* Set file change flag if created or overwritten */
+ 5568              		.loc 1 3422 3 is_stmt 1 view .LVU1825
+3422:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (mode & FA_CREATE_ALWAYS)		/* Set file change flag if created or overwritten */
+ 5569              		.loc 1 3422 6 is_stmt 0 view .LVU1826
+ 5570 0136 A4B9     		cbnz	r4, .L396
+3423:Middlewares/Third_Party/FatFs/src/ff.c **** 				mode |= FA_MODIFIED;
+ 5571              		.loc 1 3423 4 is_stmt 1 view .LVU1827
+3423:Middlewares/Third_Party/FatFs/src/ff.c **** 				mode |= FA_MODIFIED;
+ 5572              		.loc 1 3423 7 is_stmt 0 view .LVU1828
+ 5573 0138 17F0080F 		tst	r7, #8
+ 5574 013c 01D0     		beq	.L397
+3424:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->dir_sect = fs->winsect;			/* Pointer to the directory entry */
+ 5575              		.loc 1 3424 5 is_stmt 1 view .LVU1829
+3424:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->dir_sect = fs->winsect;			/* Pointer to the directory entry */
+ 5576              		.loc 1 3424 10 is_stmt 0 view .LVU1830
+ 5577 013e 47F04007 		orr	r7, r7, #64
+ 5578              	.LVL647:
+ 5579              	.L397:
+3425:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->dir_ptr = dj.dir;
+ 5580              		.loc 1 3425 4 is_stmt 1 view .LVU1831
+3425:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->dir_ptr = dj.dir;
+ 5581              		.loc 1 3425 21 is_stmt 0 view .LVU1832
+ 5582 0142 039B     		ldr	r3, [sp, #12]
+ 5583 0144 1B6B     		ldr	r3, [r3, #48]
+3425:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->dir_ptr = dj.dir;
+ 5584              		.loc 1 3425 17 view .LVU1833
+ 5585 0146 7362     		str	r3, [r6, #36]
+3426:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 5586              		.loc 1 3426 4 is_stmt 1 view .LVU1834
+3426:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 5587              		.loc 1 3426 20 is_stmt 0 view .LVU1835
+ 5588 0148 0C9B     		ldr	r3, [sp, #48]
+3426:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 5589              		.loc 1 3426 16 view .LVU1836
+ 5590 014a B362     		str	r3, [r6, #40]
+3428:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!fp->obj.lockid) res = FR_INT_ERR;
+ 5591              		.loc 1 3428 4 is_stmt 1 view .LVU1837
+3428:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!fp->obj.lockid) res = FR_INT_ERR;
+ARM GAS  /tmp/cc5lWXRL.s 			page 229
+
+
+ 5592              		.loc 1 3428 21 is_stmt 0 view .LVU1838
+ 5593 014c 37F00103 		bics	r3, r7, #1
+ 5594 0150 14BF     		ite	ne
+ 5595 0152 0121     		movne	r1, #1
+ 5596 0154 0021     		moveq	r1, #0
+ 5597 0156 04A8     		add	r0, sp, #16
+ 5598 0158 FFF7FEFF 		bl	inc_lock
+ 5599              	.LVL648:
+3428:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!fp->obj.lockid) res = FR_INT_ERR;
+ 5600              		.loc 1 3428 19 view .LVU1839
+ 5601 015c 3061     		str	r0, [r6, #16]
+3429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5602              		.loc 1 3429 4 is_stmt 1 view .LVU1840
+3429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5603              		.loc 1 3429 7 is_stmt 0 view .LVU1841
+ 5604 015e 0028     		cmp	r0, #0
+ 5605 0160 68D0     		beq	.L410
+ 5606              	.LVL649:
+ 5607              	.L396:
+3444:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 5608              		.loc 1 3444 3 is_stmt 1 view .LVU1842
+3444:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 5609              		.loc 1 3444 6 is_stmt 0 view .LVU1843
+ 5610 0162 002C     		cmp	r4, #0
+ 5611 0164 7FF45EAF 		bne	.L389
+3456:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+ 5612              		.loc 1 3456 5 is_stmt 1 view .LVU1844
+3456:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+ 5613              		.loc 1 3456 22 is_stmt 0 view .LVU1845
+ 5614 0168 039D     		ldr	r5, [sp, #12]
+3456:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+ 5615              		.loc 1 3456 37 view .LVU1846
+ 5616 016a DDF83080 		ldr	r8, [sp, #48]
+3456:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+ 5617              		.loc 1 3456 22 view .LVU1847
+ 5618 016e 4146     		mov	r1, r8
+ 5619 0170 2846     		mov	r0, r5
+ 5620 0172 FFF7FEFF 		bl	ld_clust
+ 5621              	.LVL650:
+3456:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+ 5622              		.loc 1 3456 20 view .LVU1848
+ 5623 0176 B060     		str	r0, [r6, #8]
+3457:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 5624              		.loc 1 3457 5 is_stmt 1 view .LVU1849
+3457:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 5625              		.loc 1 3457 23 is_stmt 0 view .LVU1850
+ 5626 0178 08F11C00 		add	r0, r8, #28
+ 5627 017c FFF7FEFF 		bl	ld_dword
+ 5628              	.LVL651:
+3457:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 5629              		.loc 1 3457 21 view .LVU1851
+ 5630 0180 F060     		str	r0, [r6, #12]
+3460:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5631              		.loc 1 3460 4 is_stmt 1 view .LVU1852
+3460:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5632              		.loc 1 3460 14 is_stmt 0 view .LVU1853
+ 5633 0182 0021     		movs	r1, #0
+ARM GAS  /tmp/cc5lWXRL.s 			page 230
+
+
+ 5634 0184 F162     		str	r1, [r6, #44]
+3462:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.id = fs->id;
+ 5635              		.loc 1 3462 4 is_stmt 1 view .LVU1854
+3462:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.id = fs->id;
+ 5636              		.loc 1 3462 15 is_stmt 0 view .LVU1855
+ 5637 0186 3560     		str	r5, [r6]
+3463:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->flag = mode;		/* Set file access mode */
+ 5638              		.loc 1 3463 4 is_stmt 1 view .LVU1856
+3463:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->flag = mode;		/* Set file access mode */
+ 5639              		.loc 1 3463 19 is_stmt 0 view .LVU1857
+ 5640 0188 EB88     		ldrh	r3, [r5, #6]
+3463:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->flag = mode;		/* Set file access mode */
+ 5641              		.loc 1 3463 15 view .LVU1858
+ 5642 018a B380     		strh	r3, [r6, #4]	@ movhi
+3464:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->err = 0;			/* Clear error flag */
+ 5643              		.loc 1 3464 4 is_stmt 1 view .LVU1859
+3464:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->err = 0;			/* Clear error flag */
+ 5644              		.loc 1 3464 13 is_stmt 0 view .LVU1860
+ 5645 018c 3775     		strb	r7, [r6, #20]
+3465:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->sect = 0;			/* Invalidate current data sector */
+ 5646              		.loc 1 3465 4 is_stmt 1 view .LVU1861
+3465:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->sect = 0;			/* Invalidate current data sector */
+ 5647              		.loc 1 3465 12 is_stmt 0 view .LVU1862
+ 5648 018e 7175     		strb	r1, [r6, #21]
+3466:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->fptr = 0;			/* Set file pointer top of the file */
+ 5649              		.loc 1 3466 4 is_stmt 1 view .LVU1863
+3466:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->fptr = 0;			/* Set file pointer top of the file */
+ 5650              		.loc 1 3466 13 is_stmt 0 view .LVU1864
+ 5651 0190 3162     		str	r1, [r6, #32]
+3467:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 5652              		.loc 1 3467 4 is_stmt 1 view .LVU1865
+3467:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 5653              		.loc 1 3467 13 is_stmt 0 view .LVU1866
+ 5654 0192 B161     		str	r1, [r6, #24]
+3470:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5655              		.loc 1 3470 4 is_stmt 1 view .LVU1867
+3470:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5656              		.loc 1 3470 14 is_stmt 0 view .LVU1868
+ 5657 0194 06F13008 		add	r8, r6, #48
+3470:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5658              		.loc 1 3470 4 view .LVU1869
+ 5659 0198 4FF48052 		mov	r2, #4096
+ 5660 019c 4046     		mov	r0, r8
+ 5661 019e FFF7FEFF 		bl	mem_set
+ 5662              	.LVL652:
+3472:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr = fp->obj.objsize;			/* Offset to seek */
+ 5663              		.loc 1 3472 4 is_stmt 1 view .LVU1870
+3472:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr = fp->obj.objsize;			/* Offset to seek */
+ 5664              		.loc 1 3472 7 is_stmt 0 view .LVU1871
+ 5665 01a2 17F0200F 		tst	r7, #32
+ 5666 01a6 3FF43DAF 		beq	.L389
+3472:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr = fp->obj.objsize;			/* Offset to seek */
+ 5667              		.loc 1 3472 38 discriminator 1 view .LVU1872
+ 5668 01aa F568     		ldr	r5, [r6, #12]
+3472:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr = fp->obj.objsize;			/* Offset to seek */
+ 5669              		.loc 1 3472 28 discriminator 1 view .LVU1873
+ 5670 01ac 002D     		cmp	r5, #0
+ARM GAS  /tmp/cc5lWXRL.s 			page 231
+
+
+ 5671 01ae 3FF439AF 		beq	.L389
+3473:Middlewares/Third_Party/FatFs/src/ff.c **** 				bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size in byte */
+ 5672              		.loc 1 3473 5 is_stmt 1 view .LVU1874
+3473:Middlewares/Third_Party/FatFs/src/ff.c **** 				bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size in byte */
+ 5673              		.loc 1 3473 14 is_stmt 0 view .LVU1875
+ 5674 01b2 B561     		str	r5, [r6, #24]
+3474:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = fp->obj.sclust;				/* Follow the cluster chain */
+ 5675              		.loc 1 3474 5 is_stmt 1 view .LVU1876
+3474:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = fp->obj.sclust;				/* Follow the cluster chain */
+ 5676              		.loc 1 3474 20 is_stmt 0 view .LVU1877
+ 5677 01b4 039B     		ldr	r3, [sp, #12]
+ 5678 01b6 5F89     		ldrh	r7, [r3, #10]
+ 5679              	.LVL653:
+3474:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = fp->obj.sclust;				/* Follow the cluster chain */
+ 5680              		.loc 1 3474 30 view .LVU1878
+ 5681 01b8 9B89     		ldrh	r3, [r3, #12]
+3474:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = fp->obj.sclust;				/* Follow the cluster chain */
+ 5682              		.loc 1 3474 9 view .LVU1879
+ 5683 01ba 03FB07F7 		mul	r7, r3, r7
+ 5684              	.LVL654:
+3475:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
+ 5685              		.loc 1 3475 5 is_stmt 1 view .LVU1880
+3475:Middlewares/Third_Party/FatFs/src/ff.c **** 				for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
+ 5686              		.loc 1 3475 10 is_stmt 0 view .LVU1881
+ 5687 01be B168     		ldr	r1, [r6, #8]
+ 5688              	.LVL655:
+3476:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = get_fat(&fp->obj, clst);
+ 5689              		.loc 1 3476 5 is_stmt 1 view .LVU1882
+3476:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = get_fat(&fp->obj, clst);
+ 5690              		.loc 1 3476 5 is_stmt 0 view .LVU1883
+ 5691 01c0 05E0     		b	.L398
+ 5692              	.LVL656:
+ 5693              	.L408:
+3414:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+ 5694              		.loc 1 3414 10 view .LVU1884
+ 5695 01c2 0424     		movs	r4, #4
+ 5696              	.LVL657:
+3414:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+ 5697              		.loc 1 3414 10 view .LVU1885
+ 5698 01c4 CDE7     		b	.L396
+ 5699              	.LVL658:
+ 5700              	.L399:
+3479:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 5701              		.loc 1 3479 6 is_stmt 1 view .LVU1886
+3479:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 5702              		.loc 1 3479 9 is_stmt 0 view .LVU1887
+ 5703 01c6 B1F1FF3F 		cmp	r1, #-1
+ 5704 01ca 0FD0     		beq	.L419
+ 5705              	.LVL659:
+ 5706              	.L400:
+3476:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = get_fat(&fp->obj, clst);
+ 5707              		.loc 1 3476 60 is_stmt 1 discriminator 2 view .LVU1888
+3476:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = get_fat(&fp->obj, clst);
+ 5708              		.loc 1 3476 64 is_stmt 0 discriminator 2 view .LVU1889
+ 5709 01cc ED1B     		subs	r5, r5, r7
+ 5710              	.LVL660:
+ 5711              	.L398:
+ARM GAS  /tmp/cc5lWXRL.s 			page 232
+
+
+3476:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = get_fat(&fp->obj, clst);
+ 5712              		.loc 1 3476 33 is_stmt 1 discriminator 1 view .LVU1890
+3476:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = get_fat(&fp->obj, clst);
+ 5713              		.loc 1 3476 46 is_stmt 0 discriminator 1 view .LVU1891
+ 5714 01ce B4FA84F3 		clz	r3, r4
+ 5715 01d2 5B09     		lsrs	r3, r3, #5
+ 5716 01d4 BD42     		cmp	r5, r7
+ 5717 01d6 98BF     		it	ls
+ 5718 01d8 0023     		movls	r3, #0
+3476:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = get_fat(&fp->obj, clst);
+ 5719              		.loc 1 3476 5 discriminator 1 view .LVU1892
+ 5720 01da 4BB1     		cbz	r3, .L420
+3477:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst <= 1) res = FR_INT_ERR;
+ 5721              		.loc 1 3477 6 is_stmt 1 view .LVU1893
+3477:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst <= 1) res = FR_INT_ERR;
+ 5722              		.loc 1 3477 13 is_stmt 0 view .LVU1894
+ 5723 01dc 3046     		mov	r0, r6
+ 5724 01de FFF7FEFF 		bl	get_fat
+ 5725              	.LVL661:
+3477:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst <= 1) res = FR_INT_ERR;
+ 5726              		.loc 1 3477 13 view .LVU1895
+ 5727 01e2 0146     		mov	r1, r0
+ 5728              	.LVL662:
+3478:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
+ 5729              		.loc 1 3478 6 is_stmt 1 view .LVU1896
+3478:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
+ 5730              		.loc 1 3478 9 is_stmt 0 view .LVU1897
+ 5731 01e4 0128     		cmp	r0, #1
+ 5732 01e6 EED8     		bhi	.L399
+3478:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
+ 5733              		.loc 1 3478 25 view .LVU1898
+ 5734 01e8 0224     		movs	r4, #2
+ 5735              	.LVL663:
+3478:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
+ 5736              		.loc 1 3478 25 view .LVU1899
+ 5737 01ea ECE7     		b	.L399
+ 5738              	.LVL664:
+ 5739              	.L419:
+3479:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 5740              		.loc 1 3479 34 view .LVU1900
+ 5741 01ec 0124     		movs	r4, #1
+ 5742              	.LVL665:
+3479:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 5743              		.loc 1 3479 34 view .LVU1901
+ 5744 01ee EDE7     		b	.L400
+ 5745              	.LVL666:
+ 5746              	.L420:
+3481:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK && ofs % SS(fs)) {	/* Fill sector buffer if not on the sector boundary */
+ 5747              		.loc 1 3481 5 is_stmt 1 view .LVU1902
+3481:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK && ofs % SS(fs)) {	/* Fill sector buffer if not on the sector boundary */
+ 5748              		.loc 1 3481 15 is_stmt 0 view .LVU1903
+ 5749 01f0 F161     		str	r1, [r6, #28]
+3482:Middlewares/Third_Party/FatFs/src/ff.c **** 					if ((sc = clust2sect(fs, clst)) == 0) {
+ 5750              		.loc 1 3482 5 is_stmt 1 view .LVU1904
+3482:Middlewares/Third_Party/FatFs/src/ff.c **** 					if ((sc = clust2sect(fs, clst)) == 0) {
+ 5751              		.loc 1 3482 8 is_stmt 0 view .LVU1905
+ 5752 01f2 002C     		cmp	r4, #0
+ARM GAS  /tmp/cc5lWXRL.s 			page 233
+
+
+ 5753 01f4 7FF416AF 		bne	.L389
+3482:Middlewares/Third_Party/FatFs/src/ff.c **** 					if ((sc = clust2sect(fs, clst)) == 0) {
+ 5754              		.loc 1 3482 31 discriminator 1 view .LVU1906
+ 5755 01f8 039F     		ldr	r7, [sp, #12]
+ 5756              	.LVL667:
+3482:Middlewares/Third_Party/FatFs/src/ff.c **** 					if ((sc = clust2sect(fs, clst)) == 0) {
+ 5757              		.loc 1 3482 31 discriminator 1 view .LVU1907
+ 5758 01fa B7F80C90 		ldrh	r9, [r7, #12]
+3482:Middlewares/Third_Party/FatFs/src/ff.c **** 					if ((sc = clust2sect(fs, clst)) == 0) {
+ 5759              		.loc 1 3482 29 discriminator 1 view .LVU1908
+ 5760 01fe B5FBF9F3 		udiv	r3, r5, r9
+ 5761 0202 09FB1353 		mls	r3, r9, r3, r5
+3482:Middlewares/Third_Party/FatFs/src/ff.c **** 					if ((sc = clust2sect(fs, clst)) == 0) {
+ 5762              		.loc 1 3482 22 discriminator 1 view .LVU1909
+ 5763 0206 002B     		cmp	r3, #0
+ 5764 0208 3FF40CAF 		beq	.L389
+3483:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = FR_INT_ERR;
+ 5765              		.loc 1 3483 6 is_stmt 1 view .LVU1910
+3483:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = FR_INT_ERR;
+ 5766              		.loc 1 3483 16 is_stmt 0 view .LVU1911
+ 5767 020c 3846     		mov	r0, r7
+ 5768 020e FFF7FEFF 		bl	clust2sect
+ 5769              	.LVL668:
+3483:Middlewares/Third_Party/FatFs/src/ff.c **** 						res = FR_INT_ERR;
+ 5770              		.loc 1 3483 9 view .LVU1912
+ 5771 0212 08B9     		cbnz	r0, .L421
+3484:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else {
+ 5772              		.loc 1 3484 11 view .LVU1913
+ 5773 0214 0224     		movs	r4, #2
+ 5774              	.LVL669:
+3484:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else {
+ 5775              		.loc 1 3484 11 view .LVU1914
+ 5776 0216 06E7     		b	.L402
+ 5777              	.LVL670:
+ 5778              	.L421:
+3486:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 5779              		.loc 1 3486 7 is_stmt 1 view .LVU1915
+3486:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 5780              		.loc 1 3486 23 is_stmt 0 view .LVU1916
+ 5781 0218 B5FBF9F2 		udiv	r2, r5, r9
+3486:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 5782              		.loc 1 3486 21 view .LVU1917
+ 5783 021c 0244     		add	r2, r2, r0
+3486:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 5784              		.loc 1 3486 16 view .LVU1918
+ 5785 021e 3262     		str	r2, [r6, #32]
+3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5786              		.loc 1 3488 7 is_stmt 1 view .LVU1919
+3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5787              		.loc 1 3488 11 is_stmt 0 view .LVU1920
+ 5788 0220 0123     		movs	r3, #1
+ 5789 0222 4146     		mov	r1, r8
+ 5790 0224 7878     		ldrb	r0, [r7, #1]	@ zero_extendqisi2
+ 5791              	.LVL671:
+3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5792              		.loc 1 3488 11 view .LVU1921
+ 5793 0226 FFF7FEFF 		bl	disk_read
+ARM GAS  /tmp/cc5lWXRL.s 			page 234
+
+
+ 5794              	.LVL672:
+3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5795              		.loc 1 3488 10 view .LVU1922
+ 5796 022a 0028     		cmp	r0, #0
+ 5797 022c 3FF4FAAE 		beq	.L389
+3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5798              		.loc 1 3488 67 view .LVU1923
+ 5799 0230 0124     		movs	r4, #1
+ 5800              	.LVL673:
+3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5801              		.loc 1 3488 67 view .LVU1924
+ 5802 0232 F8E6     		b	.L402
+ 5803              	.LVL674:
+ 5804              	.L410:
+3429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5805              		.loc 1 3429 29 view .LVU1925
+ 5806 0234 0224     		movs	r4, #2
+ 5807              	.LVL675:
+3429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 5808              		.loc 1 3429 29 view .LVU1926
+ 5809 0236 F5E6     		b	.L389
+ 5810              	.LVL676:
+ 5811              	.L403:
+3324:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5812              		.loc 1 3324 18 view .LVU1927
+ 5813 0238 0924     		movs	r4, #9
+ 5814 023a F6E6     		b	.L388
+ 5815              		.cfi_endproc
+ 5816              	.LFE1222:
+ 5818              		.section	.text.f_read,"ax",%progbits
+ 5819              		.align	1
+ 5820              		.global	f_read
+ 5821              		.syntax unified
+ 5822              		.thumb
+ 5823              		.thumb_func
+ 5824              		.fpu fpv5-d16
+ 5826              	f_read:
+ 5827              	.LVL677:
+ 5828              	.LFB1223:
+3517:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 5829              		.loc 1 3517 1 is_stmt 1 view -0
+ 5830              		.cfi_startproc
+ 5831              		@ args = 0, pretend = 0, frame = 16
+ 5832              		@ frame_needed = 0, uses_anonymous_args = 0
+3517:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 5833              		.loc 1 3517 1 is_stmt 0 view .LVU1929
+ 5834 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 5835              	.LCFI46:
+ 5836              		.cfi_def_cfa_offset 36
+ 5837              		.cfi_offset 4, -36
+ 5838              		.cfi_offset 5, -32
+ 5839              		.cfi_offset 6, -28
+ 5840              		.cfi_offset 7, -24
+ 5841              		.cfi_offset 8, -20
+ 5842              		.cfi_offset 9, -16
+ 5843              		.cfi_offset 10, -12
+ 5844              		.cfi_offset 11, -8
+ARM GAS  /tmp/cc5lWXRL.s 			page 235
+
+
+ 5845              		.cfi_offset 14, -4
+ 5846 0004 85B0     		sub	sp, sp, #20
+ 5847              	.LCFI47:
+ 5848              		.cfi_def_cfa_offset 56
+ 5849 0006 0446     		mov	r4, r0
+ 5850 0008 0F46     		mov	r7, r1
+ 5851 000a 1546     		mov	r5, r2
+ 5852 000c 9846     		mov	r8, r3
+3518:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 5853              		.loc 1 3518 2 is_stmt 1 view .LVU1930
+3519:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst, sect;
+ 5854              		.loc 1 3519 2 view .LVU1931
+3520:Middlewares/Third_Party/FatFs/src/ff.c **** 	FSIZE_t remain;
+ 5855              		.loc 1 3520 2 view .LVU1932
+3521:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT rcnt, cc, csect;
+ 5856              		.loc 1 3521 2 view .LVU1933
+3522:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *rbuff = (BYTE*)buff;
+ 5857              		.loc 1 3522 2 view .LVU1934
+3523:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5858              		.loc 1 3523 2 view .LVU1935
+ 5859              	.LVL678:
+3526:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);				/* Check validity of the file object */
+ 5860              		.loc 1 3526 2 view .LVU1936
+3526:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);				/* Check validity of the file object */
+ 5861              		.loc 1 3526 6 is_stmt 0 view .LVU1937
+ 5862 000e 0023     		movs	r3, #0
+ 5863              	.LVL679:
+3526:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);				/* Check validity of the file object */
+ 5864              		.loc 1 3526 6 view .LVU1938
+ 5865 0010 C8F80030 		str	r3, [r8]
+3527:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+ 5866              		.loc 1 3527 2 is_stmt 1 view .LVU1939
+3527:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+ 5867              		.loc 1 3527 8 is_stmt 0 view .LVU1940
+ 5868 0014 03A9     		add	r1, sp, #12
+ 5869              	.LVL680:
+3527:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+ 5870              		.loc 1 3527 8 view .LVU1941
+ 5871 0016 FFF7FEFF 		bl	validate
+ 5872              	.LVL681:
+3528:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+ 5873              		.loc 1 3528 2 is_stmt 1 view .LVU1942
+3528:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+ 5874              		.loc 1 3528 5 is_stmt 0 view .LVU1943
+ 5875 001a 0190     		str	r0, [sp, #4]
+ 5876 001c 0028     		cmp	r0, #0
+ 5877 001e 40F0B980 		bne	.L425
+3528:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+ 5878              		.loc 1 3528 27 discriminator 2 view .LVU1944
+ 5879 0022 637D     		ldrb	r3, [r4, #21]	@ zero_extendqisi2
+ 5880 0024 0193     		str	r3, [sp, #4]
+ 5881              	.LVL682:
+3528:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+ 5882              		.loc 1 3528 19 discriminator 2 view .LVU1945
+ 5883 0026 002B     		cmp	r3, #0
+ 5884 0028 40F0B480 		bne	.L425
+3529:Middlewares/Third_Party/FatFs/src/ff.c **** 	remain = fp->obj.objsize - fp->fptr;
+ARM GAS  /tmp/cc5lWXRL.s 			page 236
+
+
+ 5885              		.loc 1 3529 2 is_stmt 1 view .LVU1946
+3529:Middlewares/Third_Party/FatFs/src/ff.c **** 	remain = fp->obj.objsize - fp->fptr;
+ 5886              		.loc 1 3529 10 is_stmt 0 view .LVU1947
+ 5887 002c 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 5888              	.LVL683:
+3529:Middlewares/Third_Party/FatFs/src/ff.c **** 	remain = fp->obj.objsize - fp->fptr;
+ 5889              		.loc 1 3529 5 view .LVU1948
+ 5890 002e 13F0010F 		tst	r3, #1
+ 5891 0032 00F0CE80 		beq	.L447
+3530:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+ 5892              		.loc 1 3530 2 is_stmt 1 view .LVU1949
+3530:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+ 5893              		.loc 1 3530 18 is_stmt 0 view .LVU1950
+ 5894 0036 E668     		ldr	r6, [r4, #12]
+3530:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+ 5895              		.loc 1 3530 31 view .LVU1951
+ 5896 0038 A369     		ldr	r3, [r4, #24]
+3530:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+ 5897              		.loc 1 3530 9 view .LVU1952
+ 5898 003a F61A     		subs	r6, r6, r3
+ 5899              	.LVL684:
+3531:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5900              		.loc 1 3531 2 is_stmt 1 view .LVU1953
+3531:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5901              		.loc 1 3531 5 is_stmt 0 view .LVU1954
+ 5902 003c AE42     		cmp	r6, r5
+ 5903 003e 67D3     		bcc	.L445
+ 5904 0040 2E46     		mov	r6, r5
+ 5905              	.LVL685:
+3531:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 5906              		.loc 1 3531 5 view .LVU1955
+ 5907 0042 65E0     		b	.L445
+ 5908              	.LVL686:
+ 5909              	.L430:
+3542:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+ 5910              		.loc 1 3542 6 is_stmt 1 view .LVU1956
+3542:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+ 5911              		.loc 1 3542 12 is_stmt 0 view .LVU1957
+ 5912 0044 E36A     		ldr	r3, [r4, #44]
+3542:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+ 5913              		.loc 1 3542 9 view .LVU1958
+ 5914 0046 1BB1     		cbz	r3, .L432
+3543:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else
+ 5915              		.loc 1 3543 7 is_stmt 1 view .LVU1959
+3543:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else
+ 5916              		.loc 1 3543 14 is_stmt 0 view .LVU1960
+ 5917 0048 2046     		mov	r0, r4
+ 5918 004a FFF7FEFF 		bl	clmt_clust
+ 5919              	.LVL687:
+3543:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else
+ 5920              		.loc 1 3543 14 view .LVU1961
+ 5921 004e 73E0     		b	.L431
+ 5922              	.LVL688:
+ 5923              	.L432:
+3547:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 5924              		.loc 1 3547 7 is_stmt 1 view .LVU1962
+3547:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ARM GAS  /tmp/cc5lWXRL.s 			page 237
+
+
+ 5925              		.loc 1 3547 14 is_stmt 0 view .LVU1963
+ 5926 0050 E169     		ldr	r1, [r4, #28]
+ 5927 0052 2046     		mov	r0, r4
+ 5928 0054 FFF7FEFF 		bl	get_fat
+ 5929              	.LVL689:
+3547:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 5930              		.loc 1 3547 14 view .LVU1964
+ 5931 0058 6EE0     		b	.L431
+ 5932              	.L454:
+3550:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 5933              		.loc 1 3550 19 is_stmt 1 discriminator 1 view .LVU1965
+ 5934 005a 4FF0020A 		mov	r10, #2
+ 5935 005e 84F815A0 		strb	r10, [r4, #21]
+3550:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 5936              		.loc 1 3550 19 discriminator 1 view .LVU1966
+ 5937 0062 CDF804A0 		str	r10, [sp, #4]
+ 5938              	.LVL690:
+3550:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 5939              		.loc 1 3550 19 is_stmt 0 discriminator 1 view .LVU1967
+ 5940 0066 95E0     		b	.L425
+ 5941              	.LVL691:
+ 5942              	.L455:
+3551:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;				/* Update current cluster */
+ 5943              		.loc 1 3551 29 is_stmt 1 discriminator 1 view .LVU1968
+ 5944 0068 4FF0010A 		mov	r10, #1
+ 5945 006c 84F815A0 		strb	r10, [r4, #21]
+3551:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;				/* Update current cluster */
+ 5946              		.loc 1 3551 29 discriminator 1 view .LVU1969
+ 5947 0070 CDF804A0 		str	r10, [sp, #4]
+ 5948              	.LVL692:
+3551:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;				/* Update current cluster */
+ 5949              		.loc 1 3551 29 is_stmt 0 discriminator 1 view .LVU1970
+ 5950 0074 8EE0     		b	.L425
+ 5951              	.LVL693:
+ 5952              	.L456:
+3555:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 5953              		.loc 1 3555 15 is_stmt 1 discriminator 1 view .LVU1971
+ 5954 0076 4FF0020A 		mov	r10, #2
+ 5955 007a 84F815A0 		strb	r10, [r4, #21]
+3555:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 5956              		.loc 1 3555 15 discriminator 1 view .LVU1972
+ 5957 007e CDF804A0 		str	r10, [sp, #4]
+ 5958              	.LVL694:
+3555:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 5959              		.loc 1 3555 15 is_stmt 0 discriminator 1 view .LVU1973
+ 5960 0082 87E0     		b	.L425
+ 5961              	.LVL695:
+ 5962              	.L438:
+3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it 
+ 5963              		.loc 1 3562 78 is_stmt 1 discriminator 2 view .LVU1974
+3569:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+ 5964              		.loc 1 3569 5 discriminator 2 view .LVU1975
+3569:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+ 5965              		.loc 1 3569 9 is_stmt 0 discriminator 2 view .LVU1976
+ 5966 0084 94F91430 		ldrsb	r3, [r4, #20]
+3569:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+ 5967              		.loc 1 3569 8 discriminator 2 view .LVU1977
+ARM GAS  /tmp/cc5lWXRL.s 			page 238
+
+
+ 5968 0088 002B     		cmp	r3, #0
+ 5969 008a 04DB     		blt	.L451
+ 5970              	.L439:
+3574:Middlewares/Third_Party/FatFs/src/ff.c **** 				continue;
+ 5971              		.loc 1 3574 5 is_stmt 1 view .LVU1978
+3574:Middlewares/Third_Party/FatFs/src/ff.c **** 				continue;
+ 5972              		.loc 1 3574 12 is_stmt 0 view .LVU1979
+ 5973 008c 039B     		ldr	r3, [sp, #12]
+ 5974 008e 9D89     		ldrh	r5, [r3, #12]
+ 5975              	.LVL696:
+3574:Middlewares/Third_Party/FatFs/src/ff.c **** 				continue;
+ 5976              		.loc 1 3574 10 view .LVU1980
+ 5977 0090 0AFB05F5 		mul	r5, r10, r5
+ 5978              	.LVL697:
+3575:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 5979              		.loc 1 3575 5 is_stmt 1 view .LVU1981
+ 5980 0094 32E0     		b	.L440
+ 5981              	.LVL698:
+ 5982              	.L451:
+3569:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+ 5983              		.loc 1 3569 36 is_stmt 0 discriminator 1 view .LVU1982
+ 5984 0096 206A     		ldr	r0, [r4, #32]
+3569:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+ 5985              		.loc 1 3569 43 discriminator 1 view .LVU1983
+ 5986 0098 A0EB0900 		sub	r0, r0, r9
+3569:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+ 5987              		.loc 1 3569 31 discriminator 1 view .LVU1984
+ 5988 009c 5045     		cmp	r0, r10
+ 5989 009e F5D2     		bcs	.L439
+3570:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 5990              		.loc 1 3570 6 is_stmt 1 view .LVU1985
+3570:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 5991              		.loc 1 3570 43 is_stmt 0 view .LVU1986
+ 5992 00a0 039B     		ldr	r3, [sp, #12]
+ 5993 00a2 9A89     		ldrh	r2, [r3, #12]
+3570:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 5994              		.loc 1 3570 6 view .LVU1987
+ 5995 00a4 04F13001 		add	r1, r4, #48
+ 5996 00a8 02FB0070 		mla	r0, r2, r0, r7
+ 5997 00ac FFF7FEFF 		bl	mem_cpy
+ 5998              	.LVL699:
+ 5999 00b0 ECE7     		b	.L439
+ 6000              	.L436:
+3578:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 6001              		.loc 1 3578 4 is_stmt 1 view .LVU1988
+3578:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 6002              		.loc 1 3578 10 is_stmt 0 view .LVU1989
+ 6003 00b2 226A     		ldr	r2, [r4, #32]
+3578:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 6004              		.loc 1 3578 7 view .LVU1990
+ 6005 00b4 4A45     		cmp	r2, r9
+ 6006 00b6 0DD0     		beq	.L441
+3580:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 6007              		.loc 1 3580 5 is_stmt 1 view .LVU1991
+3580:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 6008              		.loc 1 3580 9 is_stmt 0 view .LVU1992
+ 6009 00b8 94F91430 		ldrsb	r3, [r4, #20]
+ARM GAS  /tmp/cc5lWXRL.s 			page 239
+
+
+3580:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 6010              		.loc 1 3580 8 view .LVU1993
+ 6011 00bc 002B     		cmp	r3, #0
+ 6012 00be 6DDB     		blt	.L452
+ 6013              	.L442:
+3585:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6014              		.loc 1 3585 5 is_stmt 1 view .LVU1994
+3585:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6015              		.loc 1 3585 9 is_stmt 0 view .LVU1995
+ 6016 00c0 0123     		movs	r3, #1
+ 6017 00c2 4A46     		mov	r2, r9
+ 6018 00c4 04F13001 		add	r1, r4, #48
+ 6019 00c8 0398     		ldr	r0, [sp, #12]
+ 6020 00ca 4078     		ldrb	r0, [r0, #1]	@ zero_extendqisi2
+ 6021 00cc FFF7FEFF 		bl	disk_read
+ 6022              	.LVL700:
+3585:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6023              		.loc 1 3585 8 view .LVU1996
+ 6024 00d0 0028     		cmp	r0, #0
+ 6025 00d2 77D1     		bne	.L453
+ 6026              	.L441:
+3585:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6027              		.loc 1 3585 79 is_stmt 1 discriminator 2 view .LVU1997
+3588:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 6028              		.loc 1 3588 4 discriminator 2 view .LVU1998
+3588:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 6029              		.loc 1 3588 13 is_stmt 0 discriminator 2 view .LVU1999
+ 6030 00d4 C4F82090 		str	r9, [r4, #32]
+ 6031              	.LVL701:
+ 6032              	.L428:
+3590:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rcnt > btr) rcnt = btr;					/* Clip it by btr if needed */
+ 6033              		.loc 1 3590 3 is_stmt 1 view .LVU2000
+3590:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rcnt > btr) rcnt = btr;					/* Clip it by btr if needed */
+ 6034              		.loc 1 3590 10 is_stmt 0 view .LVU2001
+ 6035 00d8 039B     		ldr	r3, [sp, #12]
+ 6036 00da 9D89     		ldrh	r5, [r3, #12]
+3590:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rcnt > btr) rcnt = btr;					/* Clip it by btr if needed */
+ 6037              		.loc 1 3590 27 view .LVU2002
+ 6038 00dc A369     		ldr	r3, [r4, #24]
+3590:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rcnt > btr) rcnt = btr;					/* Clip it by btr if needed */
+ 6039              		.loc 1 3590 34 view .LVU2003
+ 6040 00de B3FBF5F1 		udiv	r1, r3, r5
+ 6041 00e2 05FB1133 		mls	r3, r5, r1, r3
+3590:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rcnt > btr) rcnt = btr;					/* Clip it by btr if needed */
+ 6042              		.loc 1 3590 8 view .LVU2004
+ 6043 00e6 ED1A     		subs	r5, r5, r3
+ 6044              	.LVL702:
+3591:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+ 6045              		.loc 1 3591 3 is_stmt 1 view .LVU2005
+3591:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+ 6046              		.loc 1 3591 6 is_stmt 0 view .LVU2006
+ 6047 00e8 AE42     		cmp	r6, r5
+ 6048 00ea 00D2     		bcs	.L444
+3591:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+ 6049              		.loc 1 3591 24 view .LVU2007
+ 6050 00ec 3546     		mov	r5, r6
+ 6051              	.LVL703:
+ARM GAS  /tmp/cc5lWXRL.s 			page 240
+
+
+ 6052              	.L444:
+3596:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 6053              		.loc 1 3596 3 is_stmt 1 view .LVU2008
+3596:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 6054              		.loc 1 3596 18 is_stmt 0 view .LVU2009
+ 6055 00ee 04F13001 		add	r1, r4, #48
+3596:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 6056              		.loc 1 3596 3 view .LVU2010
+ 6057 00f2 2A46     		mov	r2, r5
+ 6058 00f4 1944     		add	r1, r1, r3
+ 6059 00f6 3846     		mov	r0, r7
+ 6060 00f8 FFF7FEFF 		bl	mem_cpy
+ 6061              	.LVL704:
+ 6062              	.L440:
+3534:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {			/* On the sector boundary? */
+ 6063              		.loc 1 3534 3 is_stmt 1 view .LVU2011
+3534:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {			/* On the sector boundary? */
+ 6064              		.loc 1 3534 9 is_stmt 0 view .LVU2012
+ 6065 00fc 2F44     		add	r7, r7, r5
+ 6066              	.LVL705:
+3534:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {			/* On the sector boundary? */
+ 6067              		.loc 1 3534 27 view .LVU2013
+ 6068 00fe A369     		ldr	r3, [r4, #24]
+ 6069 0100 2B44     		add	r3, r3, r5
+ 6070 0102 A361     		str	r3, [r4, #24]
+3534:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {			/* On the sector boundary? */
+ 6071              		.loc 1 3534 40 view .LVU2014
+ 6072 0104 D8F80030 		ldr	r3, [r8]
+ 6073 0108 2B44     		add	r3, r3, r5
+ 6074 010a C8F80030 		str	r3, [r8]
+3534:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {			/* On the sector boundary? */
+ 6075              		.loc 1 3534 53 view .LVU2015
+ 6076 010e 761B     		subs	r6, r6, r5
+ 6077              	.LVL706:
+ 6078              	.L445:
+3533:Middlewares/Third_Party/FatFs/src/ff.c **** 		rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+ 6079              		.loc 1 3533 11 is_stmt 1 view .LVU2016
+3533:Middlewares/Third_Party/FatFs/src/ff.c **** 		rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+ 6080              		.loc 1 3533 2 is_stmt 0 view .LVU2017
+ 6081 0110 002E     		cmp	r6, #0
+ 6082 0112 3FD0     		beq	.L425
+3535:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+ 6083              		.loc 1 3535 3 is_stmt 1 view .LVU2018
+3535:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+ 6084              		.loc 1 3535 9 is_stmt 0 view .LVU2019
+ 6085 0114 A169     		ldr	r1, [r4, #24]
+3535:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+ 6086              		.loc 1 3535 18 view .LVU2020
+ 6087 0116 039A     		ldr	r2, [sp, #12]
+ 6088 0118 9589     		ldrh	r5, [r2, #12]
+3535:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+ 6089              		.loc 1 3535 16 view .LVU2021
+ 6090 011a B1FBF5F3 		udiv	r3, r1, r5
+ 6091 011e 05FB1313 		mls	r3, r5, r3, r1
+3535:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+ 6092              		.loc 1 3535 6 view .LVU2022
+ 6093 0122 002B     		cmp	r3, #0
+ARM GAS  /tmp/cc5lWXRL.s 			page 241
+
+
+ 6094 0124 D8D1     		bne	.L428
+3536:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (csect == 0) {					/* On the cluster boundary? */
+ 6095              		.loc 1 3536 4 is_stmt 1 view .LVU2023
+3536:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (csect == 0) {					/* On the cluster boundary? */
+ 6096              		.loc 1 3536 28 is_stmt 0 view .LVU2024
+ 6097 0126 B1FBF5F5 		udiv	r5, r1, r5
+3536:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (csect == 0) {					/* On the cluster boundary? */
+ 6098              		.loc 1 3536 42 view .LVU2025
+ 6099 012a 5389     		ldrh	r3, [r2, #10]
+3536:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (csect == 0) {					/* On the cluster boundary? */
+ 6100              		.loc 1 3536 50 view .LVU2026
+ 6101 012c 013B     		subs	r3, r3, #1
+ 6102              	.LVL707:
+3537:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr == 0) {			/* On the top of the file? */
+ 6103              		.loc 1 3537 4 is_stmt 1 view .LVU2027
+3537:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr == 0) {			/* On the top of the file? */
+ 6104              		.loc 1 3537 7 is_stmt 0 view .LVU2028
+ 6105 012e 1D40     		ands	r5, r5, r3
+ 6106              	.LVL708:
+3537:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr == 0) {			/* On the top of the file? */
+ 6107              		.loc 1 3537 7 view .LVU2029
+ 6108 0130 08D1     		bne	.L429
+3538:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = fp->obj.sclust;		/* Follow cluster chain from the origin */
+ 6109              		.loc 1 3538 5 is_stmt 1 view .LVU2030
+3538:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = fp->obj.sclust;		/* Follow cluster chain from the origin */
+ 6110              		.loc 1 3538 8 is_stmt 0 view .LVU2031
+ 6111 0132 0029     		cmp	r1, #0
+ 6112 0134 86D1     		bne	.L430
+3539:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {						/* Middle or end of the file */
+ 6113              		.loc 1 3539 6 is_stmt 1 view .LVU2032
+3539:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {						/* Middle or end of the file */
+ 6114              		.loc 1 3539 11 is_stmt 0 view .LVU2033
+ 6115 0136 A068     		ldr	r0, [r4, #8]
+ 6116              	.LVL709:
+ 6117              	.L431:
+3550:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 6118              		.loc 1 3550 5 is_stmt 1 view .LVU2034
+3550:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 6119              		.loc 1 3550 8 is_stmt 0 view .LVU2035
+ 6120 0138 0128     		cmp	r0, #1
+ 6121 013a 8ED9     		bls	.L454
+3550:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 6122              		.loc 1 3550 40 is_stmt 1 discriminator 2 view .LVU2036
+3551:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;				/* Update current cluster */
+ 6123              		.loc 1 3551 5 discriminator 2 view .LVU2037
+3551:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;				/* Update current cluster */
+ 6124              		.loc 1 3551 8 is_stmt 0 discriminator 2 view .LVU2038
+ 6125 013c B0F1FF3F 		cmp	r0, #-1
+ 6126 0140 92D0     		beq	.L455
+3551:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;				/* Update current cluster */
+ 6127              		.loc 1 3551 51 is_stmt 1 discriminator 2 view .LVU2039
+3552:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6128              		.loc 1 3552 5 discriminator 2 view .LVU2040
+3552:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6129              		.loc 1 3552 15 is_stmt 0 discriminator 2 view .LVU2041
+ 6130 0142 E061     		str	r0, [r4, #28]
+ 6131              	.LVL710:
+ARM GAS  /tmp/cc5lWXRL.s 			page 242
+
+
+ 6132              	.L429:
+3554:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!sect) ABORT(fs, FR_INT_ERR);
+ 6133              		.loc 1 3554 4 is_stmt 1 view .LVU2042
+3554:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!sect) ABORT(fs, FR_INT_ERR);
+ 6134              		.loc 1 3554 11 is_stmt 0 view .LVU2043
+ 6135 0144 DDF80CB0 		ldr	fp, [sp, #12]
+ 6136 0148 E169     		ldr	r1, [r4, #28]
+ 6137 014a 5846     		mov	r0, fp
+ 6138 014c FFF7FEFF 		bl	clust2sect
+ 6139              	.LVL711:
+3555:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 6140              		.loc 1 3555 4 is_stmt 1 view .LVU2044
+3555:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 6141              		.loc 1 3555 7 is_stmt 0 view .LVU2045
+ 6142 0150 8146     		mov	r9, r0
+ 6143 0152 0028     		cmp	r0, #0
+ 6144 0154 8FD0     		beq	.L456
+3555:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 6145              		.loc 1 3555 36 is_stmt 1 discriminator 2 view .LVU2046
+3556:Middlewares/Third_Party/FatFs/src/ff.c **** 			cc = btr / SS(fs);					/* When remaining bytes >= sector size, */
+ 6146              		.loc 1 3556 4 discriminator 2 view .LVU2047
+3556:Middlewares/Third_Party/FatFs/src/ff.c **** 			cc = btr / SS(fs);					/* When remaining bytes >= sector size, */
+ 6147              		.loc 1 3556 9 is_stmt 0 discriminator 2 view .LVU2048
+ 6148 0156 A944     		add	r9, r9, r5
+ 6149              	.LVL712:
+3557:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cc) {							/* Read maximum contiguous sectors directly */
+ 6150              		.loc 1 3557 4 is_stmt 1 discriminator 2 view .LVU2049
+3557:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cc) {							/* Read maximum contiguous sectors directly */
+ 6151              		.loc 1 3557 15 is_stmt 0 discriminator 2 view .LVU2050
+ 6152 0158 BBF80C30 		ldrh	r3, [fp, #12]
+3557:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cc) {							/* Read maximum contiguous sectors directly */
+ 6153              		.loc 1 3557 7 discriminator 2 view .LVU2051
+ 6154 015c B6FBF3FA 		udiv	r10, r6, r3
+ 6155              	.LVL713:
+3558:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+ 6156              		.loc 1 3558 4 is_stmt 1 discriminator 2 view .LVU2052
+3558:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+ 6157              		.loc 1 3558 7 is_stmt 0 discriminator 2 view .LVU2053
+ 6158 0160 B342     		cmp	r3, r6
+ 6159 0162 A6D8     		bhi	.L436
+3559:Middlewares/Third_Party/FatFs/src/ff.c **** 					cc = fs->csize - csect;
+ 6160              		.loc 1 3559 5 is_stmt 1 view .LVU2054
+3559:Middlewares/Third_Party/FatFs/src/ff.c **** 					cc = fs->csize - csect;
+ 6161              		.loc 1 3559 15 is_stmt 0 view .LVU2055
+ 6162 0164 05EB0A03 		add	r3, r5, r10
+3559:Middlewares/Third_Party/FatFs/src/ff.c **** 					cc = fs->csize - csect;
+ 6163              		.loc 1 3559 24 view .LVU2056
+ 6164 0168 BBF80A20 		ldrh	r2, [fp, #10]
+3559:Middlewares/Third_Party/FatFs/src/ff.c **** 					cc = fs->csize - csect;
+ 6165              		.loc 1 3559 8 view .LVU2057
+ 6166 016c 9342     		cmp	r3, r2
+ 6167 016e 01D9     		bls	.L437
+3560:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 6168              		.loc 1 3560 6 is_stmt 1 view .LVU2058
+3560:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 6169              		.loc 1 3560 9 is_stmt 0 view .LVU2059
+ 6170 0170 A2EB050A 		sub	r10, r2, r5
+ARM GAS  /tmp/cc5lWXRL.s 			page 243
+
+
+ 6171              	.LVL714:
+ 6172              	.L437:
+3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it 
+ 6173              		.loc 1 3562 5 is_stmt 1 view .LVU2060
+3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it 
+ 6174              		.loc 1 3562 9 is_stmt 0 view .LVU2061
+ 6175 0174 5346     		mov	r3, r10
+ 6176 0176 4A46     		mov	r2, r9
+ 6177 0178 3946     		mov	r1, r7
+ 6178 017a 9BF80100 		ldrb	r0, [fp, #1]	@ zero_extendqisi2
+ 6179 017e FFF7FEFF 		bl	disk_read
+ 6180              	.LVL715:
+3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it 
+ 6181              		.loc 1 3562 8 view .LVU2062
+ 6182 0182 0028     		cmp	r0, #0
+ 6183 0184 3FF47EAF 		beq	.L438
+3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it 
+ 6184              		.loc 1 3562 56 is_stmt 1 discriminator 1 view .LVU2063
+ 6185 0188 4FF0010A 		mov	r10, #1
+ 6186              	.LVL716:
+3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it 
+ 6187              		.loc 1 3562 56 is_stmt 0 discriminator 1 view .LVU2064
+ 6188 018c 84F815A0 		strb	r10, [r4, #21]
+3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it 
+ 6189              		.loc 1 3562 56 is_stmt 1 discriminator 1 view .LVU2065
+ 6190 0190 CDF804A0 		str	r10, [sp, #4]
+ 6191              	.LVL717:
+ 6192              	.L425:
+3601:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6193              		.loc 1 3601 1 is_stmt 0 view .LVU2066
+ 6194 0194 0198     		ldr	r0, [sp, #4]
+ 6195 0196 05B0     		add	sp, sp, #20
+ 6196              	.LCFI48:
+ 6197              		.cfi_remember_state
+ 6198              		.cfi_def_cfa_offset 36
+ 6199              		@ sp needed
+ 6200 0198 BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 6201              	.LVL718:
+ 6202              	.L452:
+ 6203              	.LCFI49:
+ 6204              		.cfi_restore_state
+3581:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+ 6205              		.loc 1 3581 6 is_stmt 1 view .LVU2067
+3581:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+ 6206              		.loc 1 3581 10 is_stmt 0 view .LVU2068
+ 6207 019c 0123     		movs	r3, #1
+ 6208 019e 04F13001 		add	r1, r4, #48
+ 6209 01a2 9BF80100 		ldrb	r0, [fp, #1]	@ zero_extendqisi2
+ 6210 01a6 FFF7FEFF 		bl	disk_write
+ 6211              	.LVL719:
+3581:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+ 6212              		.loc 1 3581 9 view .LVU2069
+ 6213 01aa 20B9     		cbnz	r0, .L457
+3581:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+ 6214              		.loc 1 3581 85 is_stmt 1 discriminator 2 view .LVU2070
+3582:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 6215              		.loc 1 3582 6 discriminator 2 view .LVU2071
+ARM GAS  /tmp/cc5lWXRL.s 			page 244
+
+
+3582:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 6216              		.loc 1 3582 15 is_stmt 0 discriminator 2 view .LVU2072
+ 6217 01ac 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 6218 01ae 03F07F03 		and	r3, r3, #127
+ 6219 01b2 2375     		strb	r3, [r4, #20]
+ 6220 01b4 84E7     		b	.L442
+ 6221              	.L457:
+3581:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+ 6222              		.loc 1 3581 63 is_stmt 1 discriminator 1 view .LVU2073
+ 6223 01b6 4FF0010A 		mov	r10, #1
+ 6224              	.LVL720:
+3581:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+ 6225              		.loc 1 3581 63 is_stmt 0 discriminator 1 view .LVU2074
+ 6226 01ba 84F815A0 		strb	r10, [r4, #21]
+3581:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+ 6227              		.loc 1 3581 63 is_stmt 1 discriminator 1 view .LVU2075
+ 6228 01be CDF804A0 		str	r10, [sp, #4]
+ 6229              	.LVL721:
+3581:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+ 6230              		.loc 1 3581 63 is_stmt 0 discriminator 1 view .LVU2076
+ 6231 01c2 E7E7     		b	.L425
+ 6232              	.LVL722:
+ 6233              	.L453:
+3585:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6234              		.loc 1 3585 57 is_stmt 1 discriminator 1 view .LVU2077
+ 6235 01c4 4FF0010A 		mov	r10, #1
+ 6236              	.LVL723:
+3585:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6237              		.loc 1 3585 57 is_stmt 0 discriminator 1 view .LVU2078
+ 6238 01c8 84F815A0 		strb	r10, [r4, #21]
+3585:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6239              		.loc 1 3585 57 is_stmt 1 discriminator 1 view .LVU2079
+ 6240 01cc CDF804A0 		str	r10, [sp, #4]
+ 6241              	.LVL724:
+3585:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6242              		.loc 1 3585 57 is_stmt 0 discriminator 1 view .LVU2080
+ 6243 01d0 E0E7     		b	.L425
+ 6244              	.LVL725:
+ 6245              	.L447:
+3529:Middlewares/Third_Party/FatFs/src/ff.c **** 	remain = fp->obj.objsize - fp->fptr;
+ 6246              		.loc 1 3529 29 view .LVU2081
+ 6247 01d2 0723     		movs	r3, #7
+ 6248 01d4 0193     		str	r3, [sp, #4]
+ 6249              	.LVL726:
+3529:Middlewares/Third_Party/FatFs/src/ff.c **** 	remain = fp->obj.objsize - fp->fptr;
+ 6250              		.loc 1 3529 29 view .LVU2082
+ 6251 01d6 DDE7     		b	.L425
+ 6252              		.cfi_endproc
+ 6253              	.LFE1223:
+ 6255              		.section	.text.f_write,"ax",%progbits
+ 6256              		.align	1
+ 6257              		.global	f_write
+ 6258              		.syntax unified
+ 6259              		.thumb
+ 6260              		.thumb_func
+ 6261              		.fpu fpv5-d16
+ 6263              	f_write:
+ARM GAS  /tmp/cc5lWXRL.s 			page 245
+
+
+ 6264              	.LVL727:
+ 6265              	.LFB1224:
+3617:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 6266              		.loc 1 3617 1 is_stmt 1 view -0
+ 6267              		.cfi_startproc
+ 6268              		@ args = 0, pretend = 0, frame = 16
+ 6269              		@ frame_needed = 0, uses_anonymous_args = 0
+3617:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 6270              		.loc 1 3617 1 is_stmt 0 view .LVU2084
+ 6271 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 6272              	.LCFI50:
+ 6273              		.cfi_def_cfa_offset 36
+ 6274              		.cfi_offset 4, -36
+ 6275              		.cfi_offset 5, -32
+ 6276              		.cfi_offset 6, -28
+ 6277              		.cfi_offset 7, -24
+ 6278              		.cfi_offset 8, -20
+ 6279              		.cfi_offset 9, -16
+ 6280              		.cfi_offset 10, -12
+ 6281              		.cfi_offset 11, -8
+ 6282              		.cfi_offset 14, -4
+ 6283 0004 85B0     		sub	sp, sp, #20
+ 6284              	.LCFI51:
+ 6285              		.cfi_def_cfa_offset 56
+ 6286 0006 0446     		mov	r4, r0
+ 6287 0008 0F46     		mov	r7, r1
+ 6288 000a 1546     		mov	r5, r2
+ 6289 000c 9846     		mov	r8, r3
+3618:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 6290              		.loc 1 3618 2 is_stmt 1 view .LVU2085
+3619:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst, sect;
+ 6291              		.loc 1 3619 2 view .LVU2086
+3620:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT wcnt, cc, csect;
+ 6292              		.loc 1 3620 2 view .LVU2087
+3621:Middlewares/Third_Party/FatFs/src/ff.c **** 	const BYTE *wbuff = (const BYTE*)buff;
+ 6293              		.loc 1 3621 2 view .LVU2088
+3622:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6294              		.loc 1 3622 2 view .LVU2089
+ 6295              	.LVL728:
+3625:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
+ 6296              		.loc 1 3625 2 view .LVU2090
+3625:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
+ 6297              		.loc 1 3625 6 is_stmt 0 view .LVU2091
+ 6298 000e 0023     		movs	r3, #0
+ 6299              	.LVL729:
+3625:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
+ 6300              		.loc 1 3625 6 view .LVU2092
+ 6301 0010 C8F80030 		str	r3, [r8]
+3626:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+ 6302              		.loc 1 3626 2 is_stmt 1 view .LVU2093
+3626:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+ 6303              		.loc 1 3626 8 is_stmt 0 view .LVU2094
+ 6304 0014 03A9     		add	r1, sp, #12
+ 6305              	.LVL730:
+3626:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+ 6306              		.loc 1 3626 8 view .LVU2095
+ 6307 0016 FFF7FEFF 		bl	validate
+ARM GAS  /tmp/cc5lWXRL.s 			page 246
+
+
+ 6308              	.LVL731:
+3627:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+ 6309              		.loc 1 3627 2 is_stmt 1 view .LVU2096
+3627:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+ 6310              		.loc 1 3627 5 is_stmt 0 view .LVU2097
+ 6311 001a 0190     		str	r0, [sp, #4]
+ 6312 001c 0028     		cmp	r0, #0
+ 6313 001e 4AD1     		bne	.L461
+3627:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+ 6314              		.loc 1 3627 27 discriminator 2 view .LVU2098
+ 6315 0020 637D     		ldrb	r3, [r4, #21]	@ zero_extendqisi2
+ 6316 0022 0193     		str	r3, [sp, #4]
+ 6317              	.LVL732:
+3627:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+ 6318              		.loc 1 3627 19 discriminator 2 view .LVU2099
+ 6319 0024 002B     		cmp	r3, #0
+ 6320 0026 46D1     		bne	.L461
+3628:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6321              		.loc 1 3628 2 is_stmt 1 view .LVU2100
+3628:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6322              		.loc 1 3628 10 is_stmt 0 view .LVU2101
+ 6323 0028 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 6324              	.LVL733:
+3628:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6325              		.loc 1 3628 5 view .LVU2102
+ 6326 002a 13F0020F 		tst	r3, #2
+ 6327 002e 00F0EC80 		beq	.L483
+3631:Middlewares/Third_Party/FatFs/src/ff.c **** 		btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
+ 6328              		.loc 1 3631 2 is_stmt 1 view .LVU2103
+3631:Middlewares/Third_Party/FatFs/src/ff.c **** 		btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
+ 6329              		.loc 1 3631 59 is_stmt 0 view .LVU2104
+ 6330 0032 A369     		ldr	r3, [r4, #24]
+3631:Middlewares/Third_Party/FatFs/src/ff.c **** 		btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
+ 6331              		.loc 1 3631 5 view .LVU2105
+ 6332 0034 EB42     		cmn	r3, r5
+ 6333 0036 C0F0B680 		bcc	.L481
+3632:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6334              		.loc 1 3632 3 is_stmt 1 view .LVU2106
+3632:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6335              		.loc 1 3632 7 is_stmt 0 view .LVU2107
+ 6336 003a DD43     		mvns	r5, r3
+ 6337              	.LVL734:
+3632:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6338              		.loc 1 3632 7 view .LVU2108
+ 6339 003c B3E0     		b	.L481
+ 6340              	.LVL735:
+ 6341              	.L465:
+3647:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+ 6342              		.loc 1 3647 6 is_stmt 1 view .LVU2109
+3647:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+ 6343              		.loc 1 3647 12 is_stmt 0 view .LVU2110
+ 6344 003e E36A     		ldr	r3, [r4, #44]
+3647:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+ 6345              		.loc 1 3647 9 view .LVU2111
+ 6346 0040 002B     		cmp	r3, #0
+ 6347 0042 3CD0     		beq	.L467
+3648:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else
+ARM GAS  /tmp/cc5lWXRL.s 			page 247
+
+
+ 6348              		.loc 1 3648 7 is_stmt 1 view .LVU2112
+3648:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else
+ 6349              		.loc 1 3648 14 is_stmt 0 view .LVU2113
+ 6350 0044 2046     		mov	r0, r4
+ 6351 0046 FFF7FEFF 		bl	clmt_clust
+ 6352              	.LVL736:
+ 6353              	.L466:
+3655:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 1) ABORT(fs, FR_INT_ERR);
+ 6354              		.loc 1 3655 5 is_stmt 1 view .LVU2114
+3655:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 1) ABORT(fs, FR_INT_ERR);
+ 6355              		.loc 1 3655 8 is_stmt 0 view .LVU2115
+ 6356 004a 0028     		cmp	r0, #0
+ 6357 004c 00F0D880 		beq	.L468
+3656:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 6358              		.loc 1 3656 5 is_stmt 1 view .LVU2116
+3656:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 6359              		.loc 1 3656 8 is_stmt 0 view .LVU2117
+ 6360 0050 0128     		cmp	r0, #1
+ 6361 0052 39D0     		beq	.L486
+3656:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 6362              		.loc 1 3656 41 is_stmt 1 discriminator 2 view .LVU2118
+3657:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;			/* Update current cluster */
+ 6363              		.loc 1 3657 5 discriminator 2 view .LVU2119
+3657:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;			/* Update current cluster */
+ 6364              		.loc 1 3657 8 is_stmt 0 discriminator 2 view .LVU2120
+ 6365 0054 B0F1FF3F 		cmp	r0, #-1
+ 6366 0058 3DD0     		beq	.L487
+3657:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;			/* Update current cluster */
+ 6367              		.loc 1 3657 51 is_stmt 1 discriminator 2 view .LVU2121
+3658:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->obj.sclust == 0) fp->obj.sclust = clst;	/* Set start cluster if the first write */
+ 6368              		.loc 1 3658 5 discriminator 2 view .LVU2122
+3658:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->obj.sclust == 0) fp->obj.sclust = clst;	/* Set start cluster if the first write */
+ 6369              		.loc 1 3658 15 is_stmt 0 discriminator 2 view .LVU2123
+ 6370 005a E061     		str	r0, [r4, #28]
+3659:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6371              		.loc 1 3659 5 is_stmt 1 discriminator 2 view .LVU2124
+3659:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6372              		.loc 1 3659 16 is_stmt 0 discriminator 2 view .LVU2125
+ 6373 005c A368     		ldr	r3, [r4, #8]
+3659:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6374              		.loc 1 3659 8 discriminator 2 view .LVU2126
+ 6375 005e 03B9     		cbnz	r3, .L464
+3659:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6376              		.loc 1 3659 30 is_stmt 1 discriminator 1 view .LVU2127
+3659:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6377              		.loc 1 3659 45 is_stmt 0 discriminator 1 view .LVU2128
+ 6378 0060 A060     		str	r0, [r4, #8]
+ 6379              	.LVL737:
+ 6380              	.L464:
+3664:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 6381              		.loc 1 3664 4 is_stmt 1 view .LVU2129
+3664:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 6382              		.loc 1 3664 8 is_stmt 0 view .LVU2130
+ 6383 0062 94F91430 		ldrsb	r3, [r4, #20]
+3664:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 6384              		.loc 1 3664 7 view .LVU2131
+ 6385 0066 002B     		cmp	r3, #0
+ARM GAS  /tmp/cc5lWXRL.s 			page 248
+
+
+ 6386 0068 3CDB     		blt	.L488
+ 6387              	.L471:
+3669:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!sect) ABORT(fs, FR_INT_ERR);
+ 6388              		.loc 1 3669 4 is_stmt 1 view .LVU2132
+3669:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!sect) ABORT(fs, FR_INT_ERR);
+ 6389              		.loc 1 3669 11 is_stmt 0 view .LVU2133
+ 6390 006a DDF80CB0 		ldr	fp, [sp, #12]
+ 6391 006e E169     		ldr	r1, [r4, #28]
+ 6392 0070 5846     		mov	r0, fp
+ 6393 0072 FFF7FEFF 		bl	clust2sect
+ 6394              	.LVL738:
+3670:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 6395              		.loc 1 3670 4 is_stmt 1 view .LVU2134
+3670:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 6396              		.loc 1 3670 7 is_stmt 0 view .LVU2135
+ 6397 0076 8146     		mov	r9, r0
+ 6398 0078 0028     		cmp	r0, #0
+ 6399 007a 48D0     		beq	.L489
+3670:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 6400              		.loc 1 3670 36 is_stmt 1 discriminator 2 view .LVU2136
+3671:Middlewares/Third_Party/FatFs/src/ff.c **** 			cc = btw / SS(fs);				/* When remaining bytes >= sector size, */
+ 6401              		.loc 1 3671 4 discriminator 2 view .LVU2137
+3671:Middlewares/Third_Party/FatFs/src/ff.c **** 			cc = btw / SS(fs);				/* When remaining bytes >= sector size, */
+ 6402              		.loc 1 3671 9 is_stmt 0 discriminator 2 view .LVU2138
+ 6403 007c B144     		add	r9, r9, r6
+ 6404              	.LVL739:
+3672:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cc) {						/* Write maximum contiguous sectors directly */
+ 6405              		.loc 1 3672 4 is_stmt 1 discriminator 2 view .LVU2139
+3672:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cc) {						/* Write maximum contiguous sectors directly */
+ 6406              		.loc 1 3672 15 is_stmt 0 discriminator 2 view .LVU2140
+ 6407 007e BBF80C30 		ldrh	r3, [fp, #12]
+3672:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cc) {						/* Write maximum contiguous sectors directly */
+ 6408              		.loc 1 3672 7 discriminator 2 view .LVU2141
+ 6409 0082 B5FBF3FA 		udiv	r10, r5, r3
+ 6410              	.LVL740:
+3673:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+ 6411              		.loc 1 3673 4 is_stmt 1 discriminator 2 view .LVU2142
+3673:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+ 6412              		.loc 1 3673 7 is_stmt 0 discriminator 2 view .LVU2143
+ 6413 0086 AB42     		cmp	r3, r5
+ 6414 0088 5FD8     		bhi	.L474
+3674:Middlewares/Third_Party/FatFs/src/ff.c **** 					cc = fs->csize - csect;
+ 6415              		.loc 1 3674 5 is_stmt 1 view .LVU2144
+3674:Middlewares/Third_Party/FatFs/src/ff.c **** 					cc = fs->csize - csect;
+ 6416              		.loc 1 3674 15 is_stmt 0 view .LVU2145
+ 6417 008a 06EB0A03 		add	r3, r6, r10
+3674:Middlewares/Third_Party/FatFs/src/ff.c **** 					cc = fs->csize - csect;
+ 6418              		.loc 1 3674 24 view .LVU2146
+ 6419 008e BBF80A20 		ldrh	r2, [fp, #10]
+3674:Middlewares/Third_Party/FatFs/src/ff.c **** 					cc = fs->csize - csect;
+ 6420              		.loc 1 3674 8 view .LVU2147
+ 6421 0092 9342     		cmp	r3, r2
+ 6422 0094 01D9     		bls	.L475
+3675:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 6423              		.loc 1 3675 6 is_stmt 1 view .LVU2148
+3675:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 6424              		.loc 1 3675 9 is_stmt 0 view .LVU2149
+ARM GAS  /tmp/cc5lWXRL.s 			page 249
+
+
+ 6425 0096 A2EB060A 		sub	r10, r2, r6
+ 6426              	.LVL741:
+ 6427              	.L475:
+3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2
+ 6428              		.loc 1 3677 5 is_stmt 1 view .LVU2150
+3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2
+ 6429              		.loc 1 3677 9 is_stmt 0 view .LVU2151
+ 6430 009a 5346     		mov	r3, r10
+ 6431 009c 4A46     		mov	r2, r9
+ 6432 009e 3946     		mov	r1, r7
+ 6433 00a0 9BF80100 		ldrb	r0, [fp, #1]	@ zero_extendqisi2
+ 6434 00a4 FFF7FEFF 		bl	disk_write
+ 6435              	.LVL742:
+3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2
+ 6436              		.loc 1 3677 8 view .LVU2152
+ 6437 00a8 C0B3     		cbz	r0, .L476
+3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2
+ 6438              		.loc 1 3677 57 is_stmt 1 discriminator 1 view .LVU2153
+ 6439 00aa 4FF0010A 		mov	r10, #1
+ 6440              	.LVL743:
+3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2
+ 6441              		.loc 1 3677 57 is_stmt 0 discriminator 1 view .LVU2154
+ 6442 00ae 84F815A0 		strb	r10, [r4, #21]
+3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2
+ 6443              		.loc 1 3677 57 is_stmt 1 discriminator 1 view .LVU2155
+ 6444 00b2 CDF804A0 		str	r10, [sp, #4]
+ 6445              	.LVL744:
+ 6446              	.L461:
+3723:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6447              		.loc 1 3723 1 is_stmt 0 view .LVU2156
+ 6448 00b6 0198     		ldr	r0, [sp, #4]
+ 6449 00b8 05B0     		add	sp, sp, #20
+ 6450              	.LCFI52:
+ 6451              		.cfi_remember_state
+ 6452              		.cfi_def_cfa_offset 36
+ 6453              		@ sp needed
+ 6454 00ba BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 6455              	.LVL745:
+ 6456              	.L467:
+ 6457              	.LCFI53:
+ 6458              		.cfi_restore_state
+3652:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 6459              		.loc 1 3652 7 is_stmt 1 view .LVU2157
+3652:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 6460              		.loc 1 3652 14 is_stmt 0 view .LVU2158
+ 6461 00be E169     		ldr	r1, [r4, #28]
+ 6462 00c0 2046     		mov	r0, r4
+ 6463 00c2 FFF7FEFF 		bl	create_chain
+ 6464              	.LVL746:
+3652:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 6465              		.loc 1 3652 14 view .LVU2159
+ 6466 00c6 C0E7     		b	.L466
+ 6467              	.L486:
+3656:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 6468              		.loc 1 3656 20 is_stmt 1 discriminator 1 view .LVU2160
+ 6469 00c8 4FF0020A 		mov	r10, #2
+ 6470 00cc 84F815A0 		strb	r10, [r4, #21]
+ARM GAS  /tmp/cc5lWXRL.s 			page 250
+
+
+3656:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 6471              		.loc 1 3656 20 discriminator 1 view .LVU2161
+ 6472 00d0 CDF804A0 		str	r10, [sp, #4]
+ 6473              	.LVL747:
+3656:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 6474              		.loc 1 3656 20 is_stmt 0 discriminator 1 view .LVU2162
+ 6475 00d4 EFE7     		b	.L461
+ 6476              	.LVL748:
+ 6477              	.L487:
+3657:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;			/* Update current cluster */
+ 6478              		.loc 1 3657 29 is_stmt 1 discriminator 1 view .LVU2163
+ 6479 00d6 4FF0010A 		mov	r10, #1
+ 6480 00da 84F815A0 		strb	r10, [r4, #21]
+3657:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;			/* Update current cluster */
+ 6481              		.loc 1 3657 29 discriminator 1 view .LVU2164
+ 6482 00de CDF804A0 		str	r10, [sp, #4]
+ 6483              	.LVL749:
+3657:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clst;			/* Update current cluster */
+ 6484              		.loc 1 3657 29 is_stmt 0 discriminator 1 view .LVU2165
+ 6485 00e2 E8E7     		b	.L461
+ 6486              	.LVL750:
+ 6487              	.L488:
+3665:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 6488              		.loc 1 3665 5 is_stmt 1 view .LVU2166
+3665:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 6489              		.loc 1 3665 9 is_stmt 0 view .LVU2167
+ 6490 00e4 0123     		movs	r3, #1
+ 6491 00e6 226A     		ldr	r2, [r4, #32]
+ 6492 00e8 04F13001 		add	r1, r4, #48
+ 6493 00ec 0398     		ldr	r0, [sp, #12]
+ 6494 00ee 4078     		ldrb	r0, [r0, #1]	@ zero_extendqisi2
+ 6495 00f0 FFF7FEFF 		bl	disk_write
+ 6496              	.LVL751:
+3665:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 6497              		.loc 1 3665 8 view .LVU2168
+ 6498 00f4 20B9     		cbnz	r0, .L490
+3665:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 6499              		.loc 1 3665 84 is_stmt 1 discriminator 2 view .LVU2169
+3666:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6500              		.loc 1 3666 5 discriminator 2 view .LVU2170
+3666:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6501              		.loc 1 3666 14 is_stmt 0 discriminator 2 view .LVU2171
+ 6502 00f6 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 6503 00f8 03F07F03 		and	r3, r3, #127
+ 6504 00fc 2375     		strb	r3, [r4, #20]
+ 6505 00fe B4E7     		b	.L471
+ 6506              	.L490:
+3665:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 6507              		.loc 1 3665 62 is_stmt 1 discriminator 1 view .LVU2172
+ 6508 0100 4FF0010A 		mov	r10, #1
+ 6509 0104 84F815A0 		strb	r10, [r4, #21]
+3665:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 6510              		.loc 1 3665 62 discriminator 1 view .LVU2173
+ 6511 0108 CDF804A0 		str	r10, [sp, #4]
+ 6512              	.LVL752:
+3665:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 6513              		.loc 1 3665 62 is_stmt 0 discriminator 1 view .LVU2174
+ARM GAS  /tmp/cc5lWXRL.s 			page 251
+
+
+ 6514 010c D3E7     		b	.L461
+ 6515              	.LVL753:
+ 6516              	.L489:
+3670:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 6517              		.loc 1 3670 15 is_stmt 1 discriminator 1 view .LVU2175
+ 6518 010e 4FF0020A 		mov	r10, #2
+ 6519 0112 84F815A0 		strb	r10, [r4, #21]
+3670:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 6520              		.loc 1 3670 15 discriminator 1 view .LVU2176
+ 6521 0116 CDF804A0 		str	r10, [sp, #4]
+ 6522              	.LVL754:
+3670:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += csect;
+ 6523              		.loc 1 3670 15 is_stmt 0 discriminator 1 view .LVU2177
+ 6524 011a CCE7     		b	.L461
+ 6525              	.LVL755:
+ 6526              	.L476:
+3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2
+ 6527              		.loc 1 3677 79 is_stmt 1 discriminator 2 view .LVU2178
+3685:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
+ 6528              		.loc 1 3685 5 discriminator 2 view .LVU2179
+3685:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
+ 6529              		.loc 1 3685 11 is_stmt 0 discriminator 2 view .LVU2180
+ 6530 011c 216A     		ldr	r1, [r4, #32]
+3685:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
+ 6531              		.loc 1 3685 18 discriminator 2 view .LVU2181
+ 6532 011e A1EB0901 		sub	r1, r1, r9
+3685:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
+ 6533              		.loc 1 3685 8 discriminator 2 view .LVU2182
+ 6534 0122 5145     		cmp	r1, r10
+ 6535 0124 04D3     		bcc	.L491
+ 6536              	.L477:
+3691:Middlewares/Third_Party/FatFs/src/ff.c **** 				continue;
+ 6537              		.loc 1 3691 5 is_stmt 1 view .LVU2183
+3691:Middlewares/Third_Party/FatFs/src/ff.c **** 				continue;
+ 6538              		.loc 1 3691 12 is_stmt 0 view .LVU2184
+ 6539 0126 039B     		ldr	r3, [sp, #12]
+ 6540 0128 9E89     		ldrh	r6, [r3, #12]
+ 6541              	.LVL756:
+3691:Middlewares/Third_Party/FatFs/src/ff.c **** 				continue;
+ 6542              		.loc 1 3691 10 view .LVU2185
+ 6543 012a 0AFB06F6 		mul	r6, r10, r6
+ 6544              	.LVL757:
+3692:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6545              		.loc 1 3692 5 is_stmt 1 view .LVU2186
+ 6546 012e 2BE0     		b	.L478
+ 6547              	.LVL758:
+ 6548              	.L491:
+3686:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+ 6549              		.loc 1 3686 6 view .LVU2187
+3686:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+ 6550              		.loc 1 3686 52 is_stmt 0 view .LVU2188
+ 6551 0130 039B     		ldr	r3, [sp, #12]
+ 6552 0132 9A89     		ldrh	r2, [r3, #12]
+3686:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_DIRTY;
+ 6553              		.loc 1 3686 6 view .LVU2189
+ 6554 0134 02FB0171 		mla	r1, r2, r1, r7
+ 6555 0138 04F13000 		add	r0, r4, #48
+ARM GAS  /tmp/cc5lWXRL.s 			page 252
+
+
+ 6556 013c FFF7FEFF 		bl	mem_cpy
+ 6557              	.LVL759:
+3687:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 6558              		.loc 1 3687 6 is_stmt 1 view .LVU2190
+3687:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 6559              		.loc 1 3687 15 is_stmt 0 view .LVU2191
+ 6560 0140 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 6561 0142 03F07F03 		and	r3, r3, #127
+ 6562 0146 2375     		strb	r3, [r4, #20]
+ 6563 0148 EDE7     		b	.L477
+ 6564              	.L474:
+3700:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr < fp->obj.objsize &&
+ 6565              		.loc 1 3700 4 is_stmt 1 view .LVU2192
+3700:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr < fp->obj.objsize &&
+ 6566              		.loc 1 3700 10 is_stmt 0 view .LVU2193
+ 6567 014a 236A     		ldr	r3, [r4, #32]
+3700:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr < fp->obj.objsize &&
+ 6568              		.loc 1 3700 7 view .LVU2194
+ 6569 014c 4B45     		cmp	r3, r9
+ 6570 014e 03D0     		beq	.L479
+3701:Middlewares/Third_Party/FatFs/src/ff.c **** 				disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) {
+ 6571              		.loc 1 3701 7 discriminator 1 view .LVU2195
+ 6572 0150 A269     		ldr	r2, [r4, #24]
+3701:Middlewares/Third_Party/FatFs/src/ff.c **** 				disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) {
+ 6573              		.loc 1 3701 23 discriminator 1 view .LVU2196
+ 6574 0152 E368     		ldr	r3, [r4, #12]
+3700:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr < fp->obj.objsize &&
+ 6575              		.loc 1 3700 25 discriminator 1 view .LVU2197
+ 6576 0154 9A42     		cmp	r2, r3
+ 6577 0156 42D3     		bcc	.L492
+ 6578              	.L479:
+3703:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6579              		.loc 1 3703 28 is_stmt 1 view .LVU2198
+3706:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 6580              		.loc 1 3706 4 view .LVU2199
+3706:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 6581              		.loc 1 3706 13 is_stmt 0 view .LVU2200
+ 6582 0158 C4F82090 		str	r9, [r4, #32]
+ 6583              	.LVL760:
+ 6584              	.L463:
+3708:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (wcnt > btw) wcnt = btw;					/* Clip it by btw if needed */
+ 6585              		.loc 1 3708 3 is_stmt 1 view .LVU2201
+3708:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (wcnt > btw) wcnt = btw;					/* Clip it by btw if needed */
+ 6586              		.loc 1 3708 10 is_stmt 0 view .LVU2202
+ 6587 015c 039B     		ldr	r3, [sp, #12]
+ 6588 015e 9E89     		ldrh	r6, [r3, #12]
+3708:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (wcnt > btw) wcnt = btw;					/* Clip it by btw if needed */
+ 6589              		.loc 1 3708 27 view .LVU2203
+ 6590 0160 A369     		ldr	r3, [r4, #24]
+3708:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (wcnt > btw) wcnt = btw;					/* Clip it by btw if needed */
+ 6591              		.loc 1 3708 34 view .LVU2204
+ 6592 0162 B3FBF6F0 		udiv	r0, r3, r6
+ 6593 0166 06FB1033 		mls	r3, r6, r0, r3
+3708:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (wcnt > btw) wcnt = btw;					/* Clip it by btw if needed */
+ 6594              		.loc 1 3708 8 view .LVU2205
+ 6595 016a F61A     		subs	r6, r6, r3
+ 6596              	.LVL761:
+ARM GAS  /tmp/cc5lWXRL.s 			page 253
+
+
+3709:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+ 6597              		.loc 1 3709 3 is_stmt 1 view .LVU2206
+3709:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+ 6598              		.loc 1 3709 6 is_stmt 0 view .LVU2207
+ 6599 016c B542     		cmp	r5, r6
+ 6600 016e 00D2     		bcs	.L480
+3709:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY
+ 6601              		.loc 1 3709 24 view .LVU2208
+ 6602 0170 2E46     		mov	r6, r5
+ 6603              	.LVL762:
+ 6604              	.L480:
+3715:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->flag |= FA_DIRTY;
+ 6605              		.loc 1 3715 3 is_stmt 1 view .LVU2209
+3715:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->flag |= FA_DIRTY;
+ 6606              		.loc 1 3715 11 is_stmt 0 view .LVU2210
+ 6607 0172 04F13000 		add	r0, r4, #48
+3715:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->flag |= FA_DIRTY;
+ 6608              		.loc 1 3715 3 view .LVU2211
+ 6609 0176 3246     		mov	r2, r6
+ 6610 0178 3946     		mov	r1, r7
+ 6611 017a 1844     		add	r0, r0, r3
+ 6612 017c FFF7FEFF 		bl	mem_cpy
+ 6613              	.LVL763:
+3716:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 6614              		.loc 1 3716 3 is_stmt 1 view .LVU2212
+3716:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 6615              		.loc 1 3716 12 is_stmt 0 view .LVU2213
+ 6616 0180 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 6617 0182 63F07F03 		orn	r3, r3, #127
+ 6618 0186 2375     		strb	r3, [r4, #20]
+ 6619              	.L478:
+3636:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+ 6620              		.loc 1 3636 3 is_stmt 1 view .LVU2214
+3636:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+ 6621              		.loc 1 3636 9 is_stmt 0 view .LVU2215
+ 6622 0188 3744     		add	r7, r7, r6
+ 6623              	.LVL764:
+3636:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+ 6624              		.loc 1 3636 27 view .LVU2216
+ 6625 018a A369     		ldr	r3, [r4, #24]
+ 6626 018c 3344     		add	r3, r3, r6
+ 6627 018e A361     		str	r3, [r4, #24]
+3636:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+ 6628              		.loc 1 3636 73 view .LVU2217
+ 6629 0190 E268     		ldr	r2, [r4, #12]
+3636:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+ 6630              		.loc 1 3636 94 view .LVU2218
+ 6631 0192 9342     		cmp	r3, r2
+ 6632 0194 38BF     		it	cc
+ 6633 0196 1346     		movcc	r3, r2
+3636:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+ 6634              		.loc 1 3636 52 view .LVU2219
+ 6635 0198 E360     		str	r3, [r4, #12]
+3636:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+ 6636              		.loc 1 3636 117 view .LVU2220
+ 6637 019a D8F80030 		ldr	r3, [r8]
+ 6638 019e 3344     		add	r3, r3, r6
+ARM GAS  /tmp/cc5lWXRL.s 			page 254
+
+
+ 6639 01a0 C8F80030 		str	r3, [r8]
+3636:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+ 6640              		.loc 1 3636 130 view .LVU2221
+ 6641 01a4 AD1B     		subs	r5, r5, r6
+ 6642              	.LVL765:
+ 6643              	.L481:
+3635:Middlewares/Third_Party/FatFs/src/ff.c **** 		wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->
+ 6644              		.loc 1 3635 11 is_stmt 1 view .LVU2222
+3635:Middlewares/Third_Party/FatFs/src/ff.c **** 		wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->
+ 6645              		.loc 1 3635 2 is_stmt 0 view .LVU2223
+ 6646 01a6 5DB3     		cbz	r5, .L468
+3637:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1);	/* Sector offset in the cluster */
+ 6647              		.loc 1 3637 3 is_stmt 1 view .LVU2224
+3637:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1);	/* Sector offset in the cluster */
+ 6648              		.loc 1 3637 9 is_stmt 0 view .LVU2225
+ 6649 01a8 A169     		ldr	r1, [r4, #24]
+3637:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1);	/* Sector offset in the cluster */
+ 6650              		.loc 1 3637 18 view .LVU2226
+ 6651 01aa 039A     		ldr	r2, [sp, #12]
+ 6652 01ac 9689     		ldrh	r6, [r2, #12]
+3637:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1);	/* Sector offset in the cluster */
+ 6653              		.loc 1 3637 16 view .LVU2227
+ 6654 01ae B1FBF6F3 		udiv	r3, r1, r6
+ 6655 01b2 06FB1313 		mls	r3, r6, r3, r1
+3637:Middlewares/Third_Party/FatFs/src/ff.c **** 			csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1);	/* Sector offset in the cluster */
+ 6656              		.loc 1 3637 6 view .LVU2228
+ 6657 01b6 002B     		cmp	r3, #0
+ 6658 01b8 D0D1     		bne	.L463
+3638:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (csect == 0) {				/* On the cluster boundary? */
+ 6659              		.loc 1 3638 4 is_stmt 1 view .LVU2229
+3638:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (csect == 0) {				/* On the cluster boundary? */
+ 6660              		.loc 1 3638 28 is_stmt 0 view .LVU2230
+ 6661 01ba B1FBF6F6 		udiv	r6, r1, r6
+3638:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (csect == 0) {				/* On the cluster boundary? */
+ 6662              		.loc 1 3638 43 view .LVU2231
+ 6663 01be 5389     		ldrh	r3, [r2, #10]
+3638:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (csect == 0) {				/* On the cluster boundary? */
+ 6664              		.loc 1 3638 51 view .LVU2232
+ 6665 01c0 013B     		subs	r3, r3, #1
+ 6666              	.LVL766:
+3639:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr == 0) {		/* On the top of the file? */
+ 6667              		.loc 1 3639 4 is_stmt 1 view .LVU2233
+3639:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr == 0) {		/* On the top of the file? */
+ 6668              		.loc 1 3639 7 is_stmt 0 view .LVU2234
+ 6669 01c2 1E40     		ands	r6, r6, r3
+ 6670              	.LVL767:
+3639:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr == 0) {		/* On the top of the file? */
+ 6671              		.loc 1 3639 7 view .LVU2235
+ 6672 01c4 7FF44DAF 		bne	.L464
+3640:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = fp->obj.sclust;	/* Follow from the origin */
+ 6673              		.loc 1 3640 5 is_stmt 1 view .LVU2236
+3640:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = fp->obj.sclust;	/* Follow from the origin */
+ 6674              		.loc 1 3640 8 is_stmt 0 view .LVU2237
+ 6675 01c8 0029     		cmp	r1, #0
+ 6676 01ca 7FF438AF 		bne	.L465
+3641:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0) {		/* If no cluster is allocated, */
+ 6677              		.loc 1 3641 6 is_stmt 1 view .LVU2238
+ARM GAS  /tmp/cc5lWXRL.s 			page 255
+
+
+3641:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0) {		/* If no cluster is allocated, */
+ 6678              		.loc 1 3641 11 is_stmt 0 view .LVU2239
+ 6679 01ce A068     		ldr	r0, [r4, #8]
+ 6680              	.LVL768:
+3642:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = create_chain(&fp->obj, 0);	/* create a new cluster chain */
+ 6681              		.loc 1 3642 6 is_stmt 1 view .LVU2240
+3642:Middlewares/Third_Party/FatFs/src/ff.c **** 						clst = create_chain(&fp->obj, 0);	/* create a new cluster chain */
+ 6682              		.loc 1 3642 9 is_stmt 0 view .LVU2241
+ 6683 01d0 0028     		cmp	r0, #0
+ 6684 01d2 7FF43AAF 		bne	.L466
+3643:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 6685              		.loc 1 3643 7 is_stmt 1 view .LVU2242
+3643:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 6686              		.loc 1 3643 14 is_stmt 0 view .LVU2243
+ 6687 01d6 2046     		mov	r0, r4
+ 6688              	.LVL769:
+3643:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 6689              		.loc 1 3643 14 view .LVU2244
+ 6690 01d8 FFF7FEFF 		bl	create_chain
+ 6691              	.LVL770:
+3643:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 6692              		.loc 1 3643 14 view .LVU2245
+ 6693 01dc 35E7     		b	.L466
+ 6694              	.LVL771:
+ 6695              	.L492:
+3702:Middlewares/Third_Party/FatFs/src/ff.c **** 					ABORT(fs, FR_DISK_ERR);
+ 6696              		.loc 1 3702 5 view .LVU2246
+ 6697 01de 0123     		movs	r3, #1
+ 6698 01e0 4A46     		mov	r2, r9
+ 6699 01e2 04F13001 		add	r1, r4, #48
+ 6700 01e6 9BF80100 		ldrb	r0, [fp, #1]	@ zero_extendqisi2
+ 6701 01ea FFF7FEFF 		bl	disk_read
+ 6702              	.LVL772:
+3701:Middlewares/Third_Party/FatFs/src/ff.c **** 				disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) {
+ 6703              		.loc 1 3701 32 view .LVU2247
+ 6704 01ee 0028     		cmp	r0, #0
+ 6705 01f0 B2D0     		beq	.L479
+3703:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6706              		.loc 1 3703 6 is_stmt 1 view .LVU2248
+ 6707 01f2 4FF0010A 		mov	r10, #1
+ 6708              	.LVL773:
+3703:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6709              		.loc 1 3703 6 is_stmt 0 view .LVU2249
+ 6710 01f6 84F815A0 		strb	r10, [r4, #21]
+3703:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6711              		.loc 1 3703 6 is_stmt 1 view .LVU2250
+ 6712 01fa CDF804A0 		str	r10, [sp, #4]
+ 6713              	.LVL774:
+3703:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 6714              		.loc 1 3703 6 is_stmt 0 view .LVU2251
+ 6715 01fe 5AE7     		b	.L461
+ 6716              	.LVL775:
+ 6717              	.L468:
+3720:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6718              		.loc 1 3720 2 is_stmt 1 view .LVU2252
+3720:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6719              		.loc 1 3720 11 is_stmt 0 view .LVU2253
+ARM GAS  /tmp/cc5lWXRL.s 			page 256
+
+
+ 6720 0200 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 6721 0202 43F04003 		orr	r3, r3, #64
+ 6722 0206 2375     		strb	r3, [r4, #20]
+3722:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 6723              		.loc 1 3722 2 is_stmt 1 view .LVU2254
+ 6724 0208 55E7     		b	.L461
+ 6725              	.LVL776:
+ 6726              	.L483:
+3628:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6727              		.loc 1 3628 30 is_stmt 0 view .LVU2255
+ 6728 020a 0723     		movs	r3, #7
+ 6729 020c 0193     		str	r3, [sp, #4]
+ 6730              	.LVL777:
+3628:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6731              		.loc 1 3628 30 view .LVU2256
+ 6732 020e 52E7     		b	.L461
+ 6733              		.cfi_endproc
+ 6734              	.LFE1224:
+ 6736              		.section	.text.putc_bfd,"ax",%progbits
+ 6737              		.align	1
+ 6738              		.syntax unified
+ 6739              		.thumb
+ 6740              		.thumb_func
+ 6741              		.fpu fpv5-d16
+ 6743              	putc_bfd:
+ 6744              	.LVL778:
+ 6745              	.LFB1239:
+5921:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT bw;
+ 6746              		.loc 1 5921 1 is_stmt 1 view -0
+ 6747              		.cfi_startproc
+ 6748              		@ args = 0, pretend = 0, frame = 8
+ 6749              		@ frame_needed = 0, uses_anonymous_args = 0
+5921:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT bw;
+ 6750              		.loc 1 5921 1 is_stmt 0 view .LVU2258
+ 6751 0000 70B5     		push	{r4, r5, r6, lr}
+ 6752              	.LCFI54:
+ 6753              		.cfi_def_cfa_offset 16
+ 6754              		.cfi_offset 4, -16
+ 6755              		.cfi_offset 5, -12
+ 6756              		.cfi_offset 6, -8
+ 6757              		.cfi_offset 14, -4
+ 6758 0002 82B0     		sub	sp, sp, #8
+ 6759              	.LCFI55:
+ 6760              		.cfi_def_cfa_offset 24
+ 6761 0004 0446     		mov	r4, r0
+ 6762 0006 0D46     		mov	r5, r1
+5922:Middlewares/Third_Party/FatFs/src/ff.c **** 	int i;
+ 6763              		.loc 1 5922 2 is_stmt 1 view .LVU2259
+5923:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6764              		.loc 1 5923 2 view .LVU2260
+5926:Middlewares/Third_Party/FatFs/src/ff.c **** 		putc_bfd(pb, '\r');
+ 6765              		.loc 1 5926 2 view .LVU2261
+5926:Middlewares/Third_Party/FatFs/src/ff.c **** 		putc_bfd(pb, '\r');
+ 6766              		.loc 1 5926 5 is_stmt 0 view .LVU2262
+ 6767 0008 0A29     		cmp	r1, #10
+ 6768 000a 0DD0     		beq	.L500
+ 6769              	.LVL779:
+ARM GAS  /tmp/cc5lWXRL.s 			page 257
+
+
+ 6770              	.L494:
+5930:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (i < 0) return;
+ 6771              		.loc 1 5930 2 is_stmt 1 view .LVU2263
+5930:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (i < 0) return;
+ 6772              		.loc 1 5930 4 is_stmt 0 view .LVU2264
+ 6773 000c 6368     		ldr	r3, [r4, #4]
+ 6774              	.LVL780:
+5931:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6775              		.loc 1 5931 2 is_stmt 1 view .LVU2265
+5931:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6776              		.loc 1 5931 5 is_stmt 0 view .LVU2266
+ 6777 000e 002B     		cmp	r3, #0
+ 6778 0010 08DB     		blt	.L493
+5960:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 6779              		.loc 1 5960 2 is_stmt 1 view .LVU2267
+5960:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 6780              		.loc 1 5960 11 is_stmt 0 view .LVU2268
+ 6781 0012 5E1C     		adds	r6, r3, #1
+ 6782              	.LVL781:
+5960:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 6783              		.loc 1 5960 15 view .LVU2269
+ 6784 0014 2344     		add	r3, r3, r4
+ 6785 0016 1D73     		strb	r5, [r3, #12]
+5963:Middlewares/Third_Party/FatFs/src/ff.c **** 		f_write(pb->fp, pb->buf, (UINT)i, &bw);
+ 6786              		.loc 1 5963 2 is_stmt 1 view .LVU2270
+5963:Middlewares/Third_Party/FatFs/src/ff.c **** 		f_write(pb->fp, pb->buf, (UINT)i, &bw);
+ 6787              		.loc 1 5963 5 is_stmt 0 view .LVU2271
+ 6788 0018 3C2E     		cmp	r6, #60
+ 6789 001a 09DC     		bgt	.L501
+ 6790              	.LVL782:
+ 6791              	.L497:
+5967:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->nchr++;
+ 6792              		.loc 1 5967 2 is_stmt 1 view .LVU2272
+5967:Middlewares/Third_Party/FatFs/src/ff.c **** 	pb->nchr++;
+ 6793              		.loc 1 5967 10 is_stmt 0 view .LVU2273
+ 6794 001c 6660     		str	r6, [r4, #4]
+5968:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 6795              		.loc 1 5968 2 is_stmt 1 view .LVU2274
+5968:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 6796              		.loc 1 5968 4 is_stmt 0 view .LVU2275
+ 6797 001e A368     		ldr	r3, [r4, #8]
+5968:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 6798              		.loc 1 5968 10 view .LVU2276
+ 6799 0020 0133     		adds	r3, r3, #1
+ 6800 0022 A360     		str	r3, [r4, #8]
+ 6801              	.LVL783:
+ 6802              	.L493:
+5969:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6803              		.loc 1 5969 1 view .LVU2277
+ 6804 0024 02B0     		add	sp, sp, #8
+ 6805              	.LCFI56:
+ 6806              		.cfi_remember_state
+ 6807              		.cfi_def_cfa_offset 16
+ 6808              		@ sp needed
+ 6809 0026 70BD     		pop	{r4, r5, r6, pc}
+ 6810              	.LVL784:
+ 6811              	.L500:
+ARM GAS  /tmp/cc5lWXRL.s 			page 258
+
+
+ 6812              	.LCFI57:
+ 6813              		.cfi_restore_state
+5927:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6814              		.loc 1 5927 3 is_stmt 1 view .LVU2278
+ 6815 0028 0D21     		movs	r1, #13
+ 6816              	.LVL785:
+5927:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6817              		.loc 1 5927 3 is_stmt 0 view .LVU2279
+ 6818 002a FFF7E9FF 		bl	putc_bfd
+ 6819              	.LVL786:
+5927:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6820              		.loc 1 5927 3 view .LVU2280
+ 6821 002e EDE7     		b	.L494
+ 6822              	.LVL787:
+ 6823              	.L501:
+5964:Middlewares/Third_Party/FatFs/src/ff.c **** 		i = (bw == (UINT)i) ? 0 : -1;
+ 6824              		.loc 1 5964 3 is_stmt 1 view .LVU2281
+5964:Middlewares/Third_Party/FatFs/src/ff.c **** 		i = (bw == (UINT)i) ? 0 : -1;
+ 6825              		.loc 1 5964 21 is_stmt 0 view .LVU2282
+ 6826 0030 2146     		mov	r1, r4
+5964:Middlewares/Third_Party/FatFs/src/ff.c **** 		i = (bw == (UINT)i) ? 0 : -1;
+ 6827              		.loc 1 5964 3 view .LVU2283
+ 6828 0032 51F80C0B 		ldr	r0, [r1], #12
+ 6829 0036 01AB     		add	r3, sp, #4
+ 6830 0038 3246     		mov	r2, r6
+ 6831 003a FFF7FEFF 		bl	f_write
+ 6832              	.LVL788:
+5965:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6833              		.loc 1 5965 3 is_stmt 1 view .LVU2284
+5965:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6834              		.loc 1 5965 11 is_stmt 0 view .LVU2285
+ 6835 003e 019B     		ldr	r3, [sp, #4]
+5965:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6836              		.loc 1 5965 27 view .LVU2286
+ 6837 0040 9E42     		cmp	r6, r3
+ 6838 0042 02D0     		beq	.L502
+ 6839 0044 4FF0FF36 		mov	r6, #-1
+ 6840              	.LVL789:
+5965:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6841              		.loc 1 5965 27 view .LVU2287
+ 6842 0048 E8E7     		b	.L497
+ 6843              	.LVL790:
+ 6844              	.L502:
+5965:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6845              		.loc 1 5965 27 view .LVU2288
+ 6846 004a 0026     		movs	r6, #0
+ 6847              	.LVL791:
+5965:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 6848              		.loc 1 5965 27 view .LVU2289
+ 6849 004c E6E7     		b	.L497
+ 6850              		.cfi_endproc
+ 6851              	.LFE1239:
+ 6853              		.section	.text.putc_flush,"ax",%progbits
+ 6854              		.align	1
+ 6855              		.syntax unified
+ 6856              		.thumb
+ 6857              		.thumb_func
+ARM GAS  /tmp/cc5lWXRL.s 			page 259
+
+
+ 6858              		.fpu fpv5-d16
+ 6860              	putc_flush:
+ 6861              	.LVL792:
+ 6862              	.LFB1240:
+5976:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT nw;
+ 6863              		.loc 1 5976 1 is_stmt 1 view -0
+ 6864              		.cfi_startproc
+ 6865              		@ args = 0, pretend = 0, frame = 8
+ 6866              		@ frame_needed = 0, uses_anonymous_args = 0
+5977:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6867              		.loc 1 5977 2 view .LVU2291
+5979:Middlewares/Third_Party/FatFs/src/ff.c **** 		&& f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
+ 6868              		.loc 1 5979 2 view .LVU2292
+5979:Middlewares/Third_Party/FatFs/src/ff.c **** 		&& f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
+ 6869              		.loc 1 5979 11 is_stmt 0 view .LVU2293
+ 6870 0000 4268     		ldr	r2, [r0, #4]
+5979:Middlewares/Third_Party/FatFs/src/ff.c **** 		&& f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
+ 6871              		.loc 1 5979 5 view .LVU2294
+ 6872 0002 002A     		cmp	r2, #0
+ 6873 0004 10DB     		blt	.L505
+5976:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT nw;
+ 6874              		.loc 1 5976 1 view .LVU2295
+ 6875 0006 10B5     		push	{r4, lr}
+ 6876              	.LCFI58:
+ 6877              		.cfi_def_cfa_offset 8
+ 6878              		.cfi_offset 4, -8
+ 6879              		.cfi_offset 14, -4
+ 6880 0008 82B0     		sub	sp, sp, #8
+ 6881              	.LCFI59:
+ 6882              		.cfi_def_cfa_offset 16
+ 6883 000a 0446     		mov	r4, r0
+5980:Middlewares/Third_Party/FatFs/src/ff.c **** 		&& (UINT)pb->idx == nw) return pb->nchr;
+ 6884              		.loc 1 5980 24 view .LVU2296
+ 6885 000c 0146     		mov	r1, r0
+5980:Middlewares/Third_Party/FatFs/src/ff.c **** 		&& (UINT)pb->idx == nw) return pb->nchr;
+ 6886              		.loc 1 5980 6 view .LVU2297
+ 6887 000e 51F80C0B 		ldr	r0, [r1], #12
+ 6888              	.LVL793:
+5980:Middlewares/Third_Party/FatFs/src/ff.c **** 		&& (UINT)pb->idx == nw) return pb->nchr;
+ 6889              		.loc 1 5980 6 view .LVU2298
+ 6890 0012 01AB     		add	r3, sp, #4
+ 6891 0014 FFF7FEFF 		bl	f_write
+ 6892              	.LVL794:
+5980:Middlewares/Third_Party/FatFs/src/ff.c **** 		&& (UINT)pb->idx == nw) return pb->nchr;
+ 6893              		.loc 1 5980 3 view .LVU2299
+ 6894 0018 48B9     		cbnz	r0, .L506
+5981:Middlewares/Third_Party/FatFs/src/ff.c **** 	return EOF;
+ 6895              		.loc 1 5981 14 view .LVU2300
+ 6896 001a 6268     		ldr	r2, [r4, #4]
+5981:Middlewares/Third_Party/FatFs/src/ff.c **** 	return EOF;
+ 6897              		.loc 1 5981 20 view .LVU2301
+ 6898 001c 019B     		ldr	r3, [sp, #4]
+5981:Middlewares/Third_Party/FatFs/src/ff.c **** 	return EOF;
+ 6899              		.loc 1 5981 3 view .LVU2302
+ 6900 001e 9A42     		cmp	r2, r3
+ 6901 0020 08D1     		bne	.L507
+5981:Middlewares/Third_Party/FatFs/src/ff.c **** 	return EOF;
+ARM GAS  /tmp/cc5lWXRL.s 			page 260
+
+
+ 6902              		.loc 1 5981 27 is_stmt 1 discriminator 1 view .LVU2303
+5981:Middlewares/Third_Party/FatFs/src/ff.c **** 	return EOF;
+ 6903              		.loc 1 5981 36 is_stmt 0 discriminator 1 view .LVU2304
+ 6904 0022 A068     		ldr	r0, [r4, #8]
+ 6905              	.L503:
+5983:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6906              		.loc 1 5983 1 view .LVU2305
+ 6907 0024 02B0     		add	sp, sp, #8
+ 6908              	.LCFI60:
+ 6909              		.cfi_def_cfa_offset 8
+ 6910              		@ sp needed
+ 6911 0026 10BD     		pop	{r4, pc}
+ 6912              	.LVL795:
+ 6913              	.L505:
+ 6914              	.LCFI61:
+ 6915              		.cfi_def_cfa_offset 0
+ 6916              		.cfi_restore 4
+ 6917              		.cfi_restore 14
+5982:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 6918              		.loc 1 5982 9 view .LVU2306
+ 6919 0028 4FF0FF30 		mov	r0, #-1
+ 6920              	.LVL796:
+5983:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 6921              		.loc 1 5983 1 view .LVU2307
+ 6922 002c 7047     		bx	lr
+ 6923              	.LVL797:
+ 6924              	.L506:
+ 6925              	.LCFI62:
+ 6926              		.cfi_def_cfa_offset 16
+ 6927              		.cfi_offset 4, -8
+ 6928              		.cfi_offset 14, -4
+5982:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 6929              		.loc 1 5982 9 view .LVU2308
+ 6930 002e 4FF0FF30 		mov	r0, #-1
+ 6931 0032 F7E7     		b	.L503
+ 6932              	.L507:
+ 6933 0034 4FF0FF30 		mov	r0, #-1
+ 6934 0038 F4E7     		b	.L503
+ 6935              		.cfi_endproc
+ 6936              	.LFE1240:
+ 6938              		.section	.text.f_sync,"ax",%progbits
+ 6939              		.align	1
+ 6940              		.global	f_sync
+ 6941              		.syntax unified
+ 6942              		.thumb
+ 6943              		.thumb_func
+ 6944              		.fpu fpv5-d16
+ 6946              	f_sync:
+ 6947              	.LVL798:
+ 6948              	.LFB1225:
+3735:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 6949              		.loc 1 3735 1 is_stmt 1 view -0
+ 6950              		.cfi_startproc
+ 6951              		@ args = 0, pretend = 0, frame = 8
+ 6952              		@ frame_needed = 0, uses_anonymous_args = 0
+3735:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 6953              		.loc 1 3735 1 is_stmt 0 view .LVU2310
+ARM GAS  /tmp/cc5lWXRL.s 			page 261
+
+
+ 6954 0000 70B5     		push	{r4, r5, r6, lr}
+ 6955              	.LCFI63:
+ 6956              		.cfi_def_cfa_offset 16
+ 6957              		.cfi_offset 4, -16
+ 6958              		.cfi_offset 5, -12
+ 6959              		.cfi_offset 6, -8
+ 6960              		.cfi_offset 14, -4
+ 6961 0002 82B0     		sub	sp, sp, #8
+ 6962              	.LCFI64:
+ 6963              		.cfi_def_cfa_offset 24
+ 6964 0004 0446     		mov	r4, r0
+3736:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 6965              		.loc 1 3736 2 is_stmt 1 view .LVU2311
+3737:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD tm;
+ 6966              		.loc 1 3737 2 view .LVU2312
+3738:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *dir;
+ 6967              		.loc 1 3738 2 view .LVU2313
+3739:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 6968              		.loc 1 3739 2 view .LVU2314
+3745:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 6969              		.loc 1 3745 2 view .LVU2315
+3745:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 6970              		.loc 1 3745 8 is_stmt 0 view .LVU2316
+ 6971 0006 01A9     		add	r1, sp, #4
+ 6972 0008 FFF7FEFF 		bl	validate
+ 6973              	.LVL799:
+3746:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->flag & FA_MODIFIED) {	/* Is there any change to the file? */
+ 6974              		.loc 1 3746 2 is_stmt 1 view .LVU2317
+3746:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->flag & FA_MODIFIED) {	/* Is there any change to the file? */
+ 6975              		.loc 1 3746 5 is_stmt 0 view .LVU2318
+ 6976 000c 70B9     		cbnz	r0, .L513
+3747:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 6977              		.loc 1 3747 3 is_stmt 1 view .LVU2319
+3747:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 6978              		.loc 1 3747 9 is_stmt 0 view .LVU2320
+ 6979 000e 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+3747:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 6980              		.loc 1 3747 6 view .LVU2321
+ 6981 0010 13F0400F 		tst	r3, #64
+ 6982 0014 0AD0     		beq	.L513
+3749:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR);
+ 6983              		.loc 1 3749 4 is_stmt 1 view .LVU2322
+3749:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR);
+ 6984              		.loc 1 3749 7 is_stmt 0 view .LVU2323
+ 6985 0016 13F0800F 		tst	r3, #128
+ 6986 001a 09D1     		bne	.L517
+ 6987              	.L514:
+3755:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 6988              		.loc 1 3755 4 is_stmt 1 view .LVU2324
+3755:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 6989              		.loc 1 3755 9 is_stmt 0 view .LVU2325
+ 6990 001c FFF7FEFF 		bl	get_fattime
+ 6991              	.LVL800:
+ 6992 0020 0546     		mov	r5, r0
+ 6993              	.LVL801:
+3785:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {
+ 6994              		.loc 1 3785 5 is_stmt 1 view .LVU2326
+ARM GAS  /tmp/cc5lWXRL.s 			page 262
+
+
+3785:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {
+ 6995              		.loc 1 3785 11 is_stmt 0 view .LVU2327
+ 6996 0022 616A     		ldr	r1, [r4, #36]
+ 6997 0024 0198     		ldr	r0, [sp, #4]
+ 6998              	.LVL802:
+3785:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {
+ 6999              		.loc 1 3785 11 view .LVU2328
+ 7000 0026 FFF7FEFF 		bl	move_window
+ 7001              	.LVL803:
+3786:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir = fp->dir_ptr;
+ 7002              		.loc 1 3786 5 is_stmt 1 view .LVU2329
+3786:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir = fp->dir_ptr;
+ 7003              		.loc 1 3786 8 is_stmt 0 view .LVU2330
+ 7004 002a 78B1     		cbz	r0, .L518
+ 7005              	.LVL804:
+ 7006              	.L513:
+3802:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7007              		.loc 1 3802 1 view .LVU2331
+ 7008 002c 02B0     		add	sp, sp, #8
+ 7009              	.LCFI65:
+ 7010              		.cfi_remember_state
+ 7011              		.cfi_def_cfa_offset 16
+ 7012              		@ sp needed
+ 7013 002e 70BD     		pop	{r4, r5, r6, pc}
+ 7014              	.LVL805:
+ 7015              	.L517:
+ 7016              	.LCFI66:
+ 7017              		.cfi_restore_state
+3750:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 7018              		.loc 1 3750 5 is_stmt 1 view .LVU2332
+3750:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 7019              		.loc 1 3750 9 is_stmt 0 view .LVU2333
+ 7020 0030 0123     		movs	r3, #1
+ 7021 0032 226A     		ldr	r2, [r4, #32]
+ 7022 0034 04F13001 		add	r1, r4, #48
+ 7023 0038 0198     		ldr	r0, [sp, #4]
+ 7024 003a 4078     		ldrb	r0, [r0, #1]	@ zero_extendqisi2
+ 7025 003c FFF7FEFF 		bl	disk_write
+ 7026              	.LVL806:
+3750:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 7027              		.loc 1 3750 8 view .LVU2334
+ 7028 0040 40BB     		cbnz	r0, .L515
+3751:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7029              		.loc 1 3751 5 is_stmt 1 view .LVU2335
+3751:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7030              		.loc 1 3751 14 is_stmt 0 view .LVU2336
+ 7031 0042 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 7032 0044 03F07F03 		and	r3, r3, #127
+ 7033 0048 2375     		strb	r3, [r4, #20]
+ 7034 004a E7E7     		b	.L514
+ 7035              	.LVL807:
+ 7036              	.L518:
+3787:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[DIR_Attr] |= AM_ARC;						/* Set archive bit */
+ 7037              		.loc 1 3787 6 is_stmt 1 view .LVU2337
+3787:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[DIR_Attr] |= AM_ARC;						/* Set archive bit */
+ 7038              		.loc 1 3787 10 is_stmt 0 view .LVU2338
+ 7039 004c A66A     		ldr	r6, [r4, #40]
+ARM GAS  /tmp/cc5lWXRL.s 			page 263
+
+
+ 7040              	.LVL808:
+3788:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fp->obj.fs, dir, fp->obj.sclust);		/* Update file allocation info  */
+ 7041              		.loc 1 3788 6 is_stmt 1 view .LVU2339
+3788:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fp->obj.fs, dir, fp->obj.sclust);		/* Update file allocation info  */
+ 7042              		.loc 1 3788 20 is_stmt 0 view .LVU2340
+ 7043 004e F37A     		ldrb	r3, [r6, #11]	@ zero_extendqisi2
+ 7044 0050 43F02003 		orr	r3, r3, #32
+ 7045 0054 F372     		strb	r3, [r6, #11]
+3789:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize);	/* Update file size */
+ 7046              		.loc 1 3789 6 is_stmt 1 view .LVU2341
+ 7047 0056 A268     		ldr	r2, [r4, #8]
+ 7048 0058 3146     		mov	r1, r6
+ 7049 005a 2068     		ldr	r0, [r4]
+ 7050              	.LVL809:
+3789:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize);	/* Update file size */
+ 7051              		.loc 1 3789 6 is_stmt 0 view .LVU2342
+ 7052 005c FFF7FEFF 		bl	st_clust
+ 7053              	.LVL810:
+3790:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dir + DIR_ModTime, tm);				/* Update modified time */
+ 7054              		.loc 1 3790 6 is_stmt 1 view .LVU2343
+ 7055 0060 E168     		ldr	r1, [r4, #12]
+ 7056 0062 06F11C00 		add	r0, r6, #28
+ 7057 0066 FFF7FEFF 		bl	st_dword
+ 7058              	.LVL811:
+3791:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_word(dir + DIR_LstAccDate, 0);
+ 7059              		.loc 1 3791 6 view .LVU2344
+ 7060 006a 2946     		mov	r1, r5
+ 7061 006c 06F11600 		add	r0, r6, #22
+ 7062 0070 FFF7FEFF 		bl	st_dword
+ 7063              	.LVL812:
+3792:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+ 7064              		.loc 1 3792 6 view .LVU2345
+ 7065 0074 0021     		movs	r1, #0
+ 7066 0076 06F11200 		add	r0, r6, #18
+ 7067 007a FFF7FEFF 		bl	st_word
+ 7068              	.LVL813:
+3793:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = sync_fs(fs);					/* Restore it to the directory */
+ 7069              		.loc 1 3793 6 view .LVU2346
+3793:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = sync_fs(fs);					/* Restore it to the directory */
+ 7070              		.loc 1 3793 16 is_stmt 0 view .LVU2347
+ 7071 007e 019B     		ldr	r3, [sp, #4]
+ 7072 0080 0122     		movs	r2, #1
+ 7073 0082 DA70     		strb	r2, [r3, #3]
+3794:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_MODIFIED;
+ 7074              		.loc 1 3794 6 is_stmt 1 view .LVU2348
+3794:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->flag &= (BYTE)~FA_MODIFIED;
+ 7075              		.loc 1 3794 12 is_stmt 0 view .LVU2349
+ 7076 0084 0198     		ldr	r0, [sp, #4]
+ 7077 0086 FFF7FEFF 		bl	sync_fs
+ 7078              	.LVL814:
+3795:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7079              		.loc 1 3795 6 is_stmt 1 view .LVU2350
+3795:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7080              		.loc 1 3795 15 is_stmt 0 view .LVU2351
+ 7081 008a 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 7082 008c 23F04003 		bic	r3, r3, #64
+ 7083 0090 2375     		strb	r3, [r4, #20]
+ARM GAS  /tmp/cc5lWXRL.s 			page 264
+
+
+ 7084 0092 CBE7     		b	.L513
+ 7085              	.LVL815:
+ 7086              	.L515:
+3750:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 7087              		.loc 1 3750 62 view .LVU2352
+ 7088 0094 0120     		movs	r0, #1
+ 7089 0096 C9E7     		b	.L513
+ 7090              		.cfi_endproc
+ 7091              	.LFE1225:
+ 7093              		.section	.text.f_close,"ax",%progbits
+ 7094              		.align	1
+ 7095              		.global	f_close
+ 7096              		.syntax unified
+ 7097              		.thumb
+ 7098              		.thumb_func
+ 7099              		.fpu fpv5-d16
+ 7101              	f_close:
+ 7102              	.LVL816:
+ 7103              	.LFB1226:
+3816:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 7104              		.loc 1 3816 1 is_stmt 1 view -0
+ 7105              		.cfi_startproc
+ 7106              		@ args = 0, pretend = 0, frame = 8
+ 7107              		@ frame_needed = 0, uses_anonymous_args = 0
+3816:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 7108              		.loc 1 3816 1 is_stmt 0 view .LVU2354
+ 7109 0000 10B5     		push	{r4, lr}
+ 7110              	.LCFI67:
+ 7111              		.cfi_def_cfa_offset 8
+ 7112              		.cfi_offset 4, -8
+ 7113              		.cfi_offset 14, -4
+ 7114 0002 82B0     		sub	sp, sp, #8
+ 7115              	.LCFI68:
+ 7116              		.cfi_def_cfa_offset 16
+ 7117 0004 0446     		mov	r4, r0
+3817:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 7118              		.loc 1 3817 2 is_stmt 1 view .LVU2355
+3818:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7119              		.loc 1 3818 2 view .LVU2356
+3821:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK)
+ 7120              		.loc 1 3821 2 view .LVU2357
+3821:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK)
+ 7121              		.loc 1 3821 8 is_stmt 0 view .LVU2358
+ 7122 0006 FFF7FEFF 		bl	f_sync
+ 7123              	.LVL817:
+3822:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7124              		.loc 1 3822 2 is_stmt 1 view .LVU2359
+3822:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7125              		.loc 1 3822 5 is_stmt 0 view .LVU2360
+ 7126 000a 08B1     		cbz	r0, .L522
+ 7127              	.L520:
+ 7128              	.LVL818:
+3839:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 7129              		.loc 1 3839 2 is_stmt 1 view .LVU2361
+3840:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7130              		.loc 1 3840 1 is_stmt 0 view .LVU2362
+ 7131 000c 02B0     		add	sp, sp, #8
+ARM GAS  /tmp/cc5lWXRL.s 			page 265
+
+
+ 7132              	.LCFI69:
+ 7133              		.cfi_remember_state
+ 7134              		.cfi_def_cfa_offset 8
+ 7135              		@ sp needed
+ 7136 000e 10BD     		pop	{r4, pc}
+ 7137              	.LVL819:
+ 7138              	.L522:
+ 7139              	.LCFI70:
+ 7140              		.cfi_restore_state
+3825:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+ 7141              		.loc 1 3825 3 is_stmt 1 view .LVU2363
+3825:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {
+ 7142              		.loc 1 3825 9 is_stmt 0 view .LVU2364
+ 7143 0010 01A9     		add	r1, sp, #4
+ 7144 0012 2046     		mov	r0, r4
+ 7145 0014 FFF7FEFF 		bl	validate
+ 7146              	.LVL820:
+3826:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 7147              		.loc 1 3826 3 is_stmt 1 view .LVU2365
+3826:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 7148              		.loc 1 3826 6 is_stmt 0 view .LVU2366
+ 7149 0018 0028     		cmp	r0, #0
+ 7150 001a F7D1     		bne	.L520
+3828:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK)
+ 7151              		.loc 1 3828 4 is_stmt 1 view .LVU2367
+3828:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK)
+ 7152              		.loc 1 3828 10 is_stmt 0 view .LVU2368
+ 7153 001c 2069     		ldr	r0, [r4, #16]
+ 7154              	.LVL821:
+3828:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK)
+ 7155              		.loc 1 3828 10 view .LVU2369
+ 7156 001e FFF7FEFF 		bl	dec_lock
+ 7157              	.LVL822:
+3829:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7158              		.loc 1 3829 4 is_stmt 1 view .LVU2370
+3829:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7159              		.loc 1 3829 7 is_stmt 0 view .LVU2371
+ 7160 0022 0028     		cmp	r0, #0
+ 7161 0024 F2D1     		bne	.L520
+3832:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7162              		.loc 1 3832 5 is_stmt 1 view .LVU2372
+3832:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7163              		.loc 1 3832 16 is_stmt 0 view .LVU2373
+ 7164 0026 2060     		str	r0, [r4]
+ 7165 0028 F0E7     		b	.L520
+ 7166              		.cfi_endproc
+ 7167              	.LFE1226:
+ 7169              		.section	.text.f_lseek,"ax",%progbits
+ 7170              		.align	1
+ 7171              		.global	f_lseek
+ 7172              		.syntax unified
+ 7173              		.thumb
+ 7174              		.thumb_func
+ 7175              		.fpu fpv5-d16
+ 7177              	f_lseek:
+ 7178              	.LVL823:
+ 7179              	.LFB1227:
+ARM GAS  /tmp/cc5lWXRL.s 			page 266
+
+
+4005:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 7180              		.loc 1 4005 1 is_stmt 1 view -0
+ 7181              		.cfi_startproc
+ 7182              		@ args = 0, pretend = 0, frame = 8
+ 7183              		@ frame_needed = 0, uses_anonymous_args = 0
+4005:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 7184              		.loc 1 4005 1 is_stmt 0 view .LVU2375
+ 7185 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 7186              	.LCFI71:
+ 7187              		.cfi_def_cfa_offset 36
+ 7188              		.cfi_offset 4, -36
+ 7189              		.cfi_offset 5, -32
+ 7190              		.cfi_offset 6, -28
+ 7191              		.cfi_offset 7, -24
+ 7192              		.cfi_offset 8, -20
+ 7193              		.cfi_offset 9, -16
+ 7194              		.cfi_offset 10, -12
+ 7195              		.cfi_offset 11, -8
+ 7196              		.cfi_offset 14, -4
+ 7197 0004 83B0     		sub	sp, sp, #12
+ 7198              	.LCFI72:
+ 7199              		.cfi_def_cfa_offset 48
+ 7200 0006 0446     		mov	r4, r0
+ 7201 0008 0E46     		mov	r6, r1
+4006:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 7202              		.loc 1 4006 2 is_stmt 1 view .LVU2376
+4007:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD clst, bcs, nsect;
+ 7203              		.loc 1 4007 2 view .LVU2377
+4008:Middlewares/Third_Party/FatFs/src/ff.c **** 	FSIZE_t ifptr;
+ 7204              		.loc 1 4008 2 view .LVU2378
+4009:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK
+ 7205              		.loc 1 4009 2 view .LVU2379
+4011:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7206              		.loc 1 4011 2 view .LVU2380
+4014:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) res = (FRESULT)fp->err;
+ 7207              		.loc 1 4014 2 view .LVU2381
+4014:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) res = (FRESULT)fp->err;
+ 7208              		.loc 1 4014 8 is_stmt 0 view .LVU2382
+ 7209 000a 01A9     		add	r1, sp, #4
+ 7210              	.LVL824:
+4014:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) res = (FRESULT)fp->err;
+ 7211              		.loc 1 4014 8 view .LVU2383
+ 7212 000c FFF7FEFF 		bl	validate
+ 7213              	.LVL825:
+4015:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY
+ 7214              		.loc 1 4015 2 is_stmt 1 view .LVU2384
+4015:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY
+ 7215              		.loc 1 4015 5 is_stmt 0 view .LVU2385
+ 7216 0010 0546     		mov	r5, r0
+ 7217 0012 00B9     		cbnz	r0, .L524
+4015:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY
+ 7218              		.loc 1 4015 20 is_stmt 1 discriminator 1 view .LVU2386
+4015:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY
+ 7219              		.loc 1 4015 24 is_stmt 0 discriminator 1 view .LVU2387
+ 7220 0014 657D     		ldrb	r5, [r4, #21]	@ zero_extendqisi2
+ 7221              	.LVL826:
+ 7222              	.L524:
+ARM GAS  /tmp/cc5lWXRL.s 			page 267
+
+
+4021:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7223              		.loc 1 4021 2 is_stmt 1 view .LVU2388
+4021:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7224              		.loc 1 4021 5 is_stmt 0 view .LVU2389
+ 7225 0016 6DB9     		cbnz	r5, .L525
+4024:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
+ 7226              		.loc 1 4024 2 is_stmt 1 view .LVU2390
+4024:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
+ 7227              		.loc 1 4024 8 is_stmt 0 view .LVU2391
+ 7228 0018 E36A     		ldr	r3, [r4, #44]
+4024:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
+ 7229              		.loc 1 4024 5 view .LVU2392
+ 7230 001a 002B     		cmp	r3, #0
+ 7231 001c 00F08E80 		beq	.L526
+4025:Middlewares/Third_Party/FatFs/src/ff.c **** 			tbl = fp->cltbl;
+ 7232              		.loc 1 4025 3 is_stmt 1 view .LVU2393
+4025:Middlewares/Third_Party/FatFs/src/ff.c **** 			tbl = fp->cltbl;
+ 7233              		.loc 1 4025 6 is_stmt 0 view .LVU2394
+ 7234 0020 B6F1FF3F 		cmp	r6, #-1
+ 7235 0024 0AD0     		beq	.L566
+4051:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->fptr = ofs;				/* Set file pointer */
+ 7236              		.loc 1 4051 4 is_stmt 1 view .LVU2395
+4051:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->fptr = ofs;				/* Set file pointer */
+ 7237              		.loc 1 4051 21 is_stmt 0 view .LVU2396
+ 7238 0026 E768     		ldr	r7, [r4, #12]
+4051:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->fptr = ofs;				/* Set file pointer */
+ 7239              		.loc 1 4051 7 view .LVU2397
+ 7240 0028 B742     		cmp	r7, r6
+ 7241 002a 00D3     		bcc	.L534
+ 7242 002c 3746     		mov	r7, r6
+ 7243              	.L534:
+ 7244              	.LVL827:
+4052:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ofs) {
+ 7245              		.loc 1 4052 4 is_stmt 1 view .LVU2398
+4052:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ofs) {
+ 7246              		.loc 1 4052 13 is_stmt 0 view .LVU2399
+ 7247 002e A761     		str	r7, [r4, #24]
+4053:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clmt_clust(fp, ofs - 1);
+ 7248              		.loc 1 4053 4 is_stmt 1 view .LVU2400
+4053:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->clust = clmt_clust(fp, ofs - 1);
+ 7249              		.loc 1 4053 7 is_stmt 0 view .LVU2401
+ 7250 0030 002F     		cmp	r7, #0
+ 7251 0032 3FD1     		bne	.L567
+ 7252              	.LVL828:
+ 7253              	.L525:
+4153:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7254              		.loc 1 4153 1 view .LVU2402
+ 7255 0034 2846     		mov	r0, r5
+ 7256 0036 03B0     		add	sp, sp, #12
+ 7257              	.LCFI73:
+ 7258              		.cfi_remember_state
+ 7259              		.cfi_def_cfa_offset 36
+ 7260              		@ sp needed
+ 7261 0038 BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 7262              	.LVL829:
+ 7263              	.L566:
+ 7264              	.LCFI74:
+ARM GAS  /tmp/cc5lWXRL.s 			page 268
+
+
+ 7265              		.cfi_restore_state
+4026:Middlewares/Third_Party/FatFs/src/ff.c **** 			tlen = *tbl++; ulen = 2;	/* Given table size and required table size */
+ 7266              		.loc 1 4026 4 is_stmt 1 view .LVU2403
+4027:Middlewares/Third_Party/FatFs/src/ff.c **** 			cl = fp->obj.sclust;		/* Origin of the chain */
+ 7267              		.loc 1 4027 4 view .LVU2404
+4027:Middlewares/Third_Party/FatFs/src/ff.c **** 			cl = fp->obj.sclust;		/* Origin of the chain */
+ 7268              		.loc 1 4027 15 is_stmt 0 view .LVU2405
+ 7269 003c 9846     		mov	r8, r3
+ 7270              	.LVL830:
+4027:Middlewares/Third_Party/FatFs/src/ff.c **** 			cl = fp->obj.sclust;		/* Origin of the chain */
+ 7271              		.loc 1 4027 9 view .LVU2406
+ 7272 003e 58F804BB 		ldr	fp, [r8], #4
+ 7273              	.LVL831:
+4027:Middlewares/Third_Party/FatFs/src/ff.c **** 			cl = fp->obj.sclust;		/* Origin of the chain */
+ 7274              		.loc 1 4027 19 is_stmt 1 view .LVU2407
+4028:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cl) {
+ 7275              		.loc 1 4028 4 view .LVU2408
+4028:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (cl) {
+ 7276              		.loc 1 4028 7 is_stmt 0 view .LVU2409
+ 7277 0042 D4F808A0 		ldr	r10, [r4, #8]
+ 7278              	.LVL832:
+4029:Middlewares/Third_Party/FatFs/src/ff.c **** 				do {
+ 7279              		.loc 1 4029 4 is_stmt 1 view .LVU2410
+4029:Middlewares/Third_Party/FatFs/src/ff.c **** 				do {
+ 7280              		.loc 1 4029 7 is_stmt 0 view .LVU2411
+ 7281 0046 BAF1000F 		cmp	r10, #0
+ 7282 004a 27D0     		beq	.L559
+4027:Middlewares/Third_Party/FatFs/src/ff.c **** 			cl = fp->obj.sclust;		/* Origin of the chain */
+ 7283              		.loc 1 4027 24 view .LVU2412
+ 7284 004c 4FF00209 		mov	r9, #2
+ 7285              	.LVL833:
+ 7286              	.L533:
+4030:Middlewares/Third_Party/FatFs/src/ff.c **** 					/* Get a fragment */
+ 7287              		.loc 1 4030 5 is_stmt 1 view .LVU2413
+4032:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+ 7288              		.loc 1 4032 6 view .LVU2414
+4032:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+ 7289              		.loc 1 4032 16 view .LVU2415
+4032:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+ 7290              		.loc 1 4032 25 view .LVU2416
+4032:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+ 7291              		.loc 1 4032 30 is_stmt 0 view .LVU2417
+ 7292 0050 09F10209 		add	r9, r9, #2
+ 7293              	.LVL834:
+4032:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+ 7294              		.loc 1 4032 30 view .LVU2418
+ 7295 0054 5146     		mov	r1, r10
+4032:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+ 7296              		.loc 1 4032 20 view .LVU2419
+ 7297 0056 0027     		movs	r7, #0
+ 7298              	.LVL835:
+ 7299              	.L531:
+4033:Middlewares/Third_Party/FatFs/src/ff.c **** 						pcl = cl; ncl++;
+ 7300              		.loc 1 4033 6 is_stmt 1 view .LVU2420
+4034:Middlewares/Third_Party/FatFs/src/ff.c **** 						cl = get_fat(&fp->obj, cl);
+ 7301              		.loc 1 4034 7 view .LVU2421
+4034:Middlewares/Third_Party/FatFs/src/ff.c **** 						cl = get_fat(&fp->obj, cl);
+ARM GAS  /tmp/cc5lWXRL.s 			page 269
+
+
+ 7302              		.loc 1 4034 17 view .LVU2422
+4034:Middlewares/Third_Party/FatFs/src/ff.c **** 						cl = get_fat(&fp->obj, cl);
+ 7303              		.loc 1 4034 20 is_stmt 0 view .LVU2423
+ 7304 0058 0137     		adds	r7, r7, #1
+ 7305              	.LVL836:
+4035:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl <= 1) ABORT(fs, FR_INT_ERR);
+ 7306              		.loc 1 4035 7 is_stmt 1 view .LVU2424
+ 7307 005a 0E46     		mov	r6, r1
+4035:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl <= 1) ABORT(fs, FR_INT_ERR);
+ 7308              		.loc 1 4035 12 is_stmt 0 view .LVU2425
+ 7309 005c 2046     		mov	r0, r4
+ 7310 005e FFF7FEFF 		bl	get_fat
+ 7311              	.LVL837:
+4035:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl <= 1) ABORT(fs, FR_INT_ERR);
+ 7312              		.loc 1 4035 12 view .LVU2426
+ 7313 0062 0146     		mov	r1, r0
+ 7314              	.LVL838:
+4036:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7315              		.loc 1 4036 7 is_stmt 1 view .LVU2427
+4036:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7316              		.loc 1 4036 10 is_stmt 0 view .LVU2428
+ 7317 0064 0128     		cmp	r0, #1
+ 7318 0066 13D9     		bls	.L568
+4036:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7319              		.loc 1 4036 41 is_stmt 1 discriminator 2 view .LVU2429
+4037:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (cl == pcl + 1);
+ 7320              		.loc 1 4037 7 discriminator 2 view .LVU2430
+4037:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (cl == pcl + 1);
+ 7321              		.loc 1 4037 10 is_stmt 0 discriminator 2 view .LVU2431
+ 7322 0068 B0F1FF3F 		cmp	r0, #-1
+ 7323 006c 13D0     		beq	.L569
+4037:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (cl == pcl + 1);
+ 7324              		.loc 1 4037 51 is_stmt 1 discriminator 2 view .LVU2432
+4038:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (ulen <= tlen) {		/* Store the length and top of the fragment */
+ 7325              		.loc 1 4038 14 discriminator 2 view .LVU2433
+4038:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (ulen <= tlen) {		/* Store the length and top of the fragment */
+ 7326              		.loc 1 4038 25 is_stmt 0 discriminator 2 view .LVU2434
+ 7327 006e 0136     		adds	r6, r6, #1
+ 7328              	.LVL839:
+4038:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (ulen <= tlen) {		/* Store the length and top of the fragment */
+ 7329              		.loc 1 4038 6 discriminator 2 view .LVU2435
+ 7330 0070 8642     		cmp	r6, r0
+ 7331 0072 F1D0     		beq	.L531
+4039:Middlewares/Third_Party/FatFs/src/ff.c **** 						*tbl++ = ncl; *tbl++ = tcl;
+ 7332              		.loc 1 4039 6 is_stmt 1 view .LVU2436
+4039:Middlewares/Third_Party/FatFs/src/ff.c **** 						*tbl++ = ncl; *tbl++ = tcl;
+ 7333              		.loc 1 4039 9 is_stmt 0 view .LVU2437
+ 7334 0074 CB45     		cmp	fp, r9
+ 7335 0076 05D3     		bcc	.L532
+4040:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 7336              		.loc 1 4040 7 is_stmt 1 view .LVU2438
+ 7337              	.LVL840:
+4040:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 7338              		.loc 1 4040 14 is_stmt 0 view .LVU2439
+ 7339 0078 4346     		mov	r3, r8
+ 7340 007a 43F8087B 		str	r7, [r3], #8
+4040:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ARM GAS  /tmp/cc5lWXRL.s 			page 270
+
+
+ 7341              		.loc 1 4040 21 is_stmt 1 view .LVU2440
+ 7342              	.LVL841:
+4040:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 7343              		.loc 1 4040 28 is_stmt 0 view .LVU2441
+ 7344 007e C8F804A0 		str	r10, [r8, #4]
+4040:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 7345              		.loc 1 4040 25 view .LVU2442
+ 7346 0082 9846     		mov	r8, r3
+ 7347              	.LVL842:
+ 7348              	.L532:
+4042:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7349              		.loc 1 4042 13 is_stmt 1 view .LVU2443
+4042:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7350              		.loc 1 4042 21 is_stmt 0 view .LVU2444
+ 7351 0084 019B     		ldr	r3, [sp, #4]
+ 7352 0086 9B69     		ldr	r3, [r3, #24]
+4042:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7353              		.loc 1 4042 5 view .LVU2445
+ 7354 0088 8B42     		cmp	r3, r1
+ 7355 008a 09D9     		bls	.L528
+4035:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl <= 1) ABORT(fs, FR_INT_ERR);
+ 7356              		.loc 1 4035 12 view .LVU2446
+ 7357 008c 8A46     		mov	r10, r1
+ 7358              	.LVL843:
+4035:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl <= 1) ABORT(fs, FR_INT_ERR);
+ 7359              		.loc 1 4035 12 view .LVU2447
+ 7360 008e DFE7     		b	.L533
+ 7361              	.LVL844:
+ 7362              	.L568:
+4036:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7363              		.loc 1 4036 20 is_stmt 1 discriminator 1 view .LVU2448
+ 7364 0090 0225     		movs	r5, #2
+ 7365              	.LVL845:
+4036:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7366              		.loc 1 4036 20 is_stmt 0 discriminator 1 view .LVU2449
+ 7367 0092 6575     		strb	r5, [r4, #21]
+4036:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7368              		.loc 1 4036 20 is_stmt 1 discriminator 1 view .LVU2450
+ 7369 0094 CEE7     		b	.L525
+ 7370              	.LVL846:
+ 7371              	.L569:
+4037:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (cl == pcl + 1);
+ 7372              		.loc 1 4037 29 discriminator 1 view .LVU2451
+ 7373 0096 0125     		movs	r5, #1
+ 7374              	.LVL847:
+4037:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (cl == pcl + 1);
+ 7375              		.loc 1 4037 29 is_stmt 0 discriminator 1 view .LVU2452
+ 7376 0098 6575     		strb	r5, [r4, #21]
+4037:Middlewares/Third_Party/FatFs/src/ff.c **** 					} while (cl == pcl + 1);
+ 7377              		.loc 1 4037 29 is_stmt 1 discriminator 1 view .LVU2453
+ 7378 009a CBE7     		b	.L525
+ 7379              	.LVL848:
+ 7380              	.L559:
+4027:Middlewares/Third_Party/FatFs/src/ff.c **** 			cl = fp->obj.sclust;		/* Origin of the chain */
+ 7381              		.loc 1 4027 24 is_stmt 0 view .LVU2454
+ 7382 009c 4FF00209 		mov	r9, #2
+ 7383              	.LVL849:
+ARM GAS  /tmp/cc5lWXRL.s 			page 271
+
+
+ 7384              	.L528:
+4044:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ulen <= tlen) {
+ 7385              		.loc 1 4044 4 is_stmt 1 view .LVU2455
+4044:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ulen <= tlen) {
+ 7386              		.loc 1 4044 7 is_stmt 0 view .LVU2456
+ 7387 00a0 E36A     		ldr	r3, [r4, #44]
+4044:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ulen <= tlen) {
+ 7388              		.loc 1 4044 15 view .LVU2457
+ 7389 00a2 C3F80090 		str	r9, [r3]
+4045:Middlewares/Third_Party/FatFs/src/ff.c **** 				*tbl = 0;		/* Terminate table */
+ 7390              		.loc 1 4045 4 is_stmt 1 view .LVU2458
+4045:Middlewares/Third_Party/FatFs/src/ff.c **** 				*tbl = 0;		/* Terminate table */
+ 7391              		.loc 1 4045 7 is_stmt 0 view .LVU2459
+ 7392 00a6 D945     		cmp	r9, fp
+ 7393 00a8 00F2FB80 		bhi	.L561
+4046:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 7394              		.loc 1 4046 5 is_stmt 1 view .LVU2460
+4046:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 7395              		.loc 1 4046 10 is_stmt 0 view .LVU2461
+ 7396 00ac 0023     		movs	r3, #0
+ 7397 00ae C8F80030 		str	r3, [r8]
+ 7398 00b2 BFE7     		b	.L525
+ 7399              	.LVL850:
+ 7400              	.L567:
+4054:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc = clust2sect(fs, fp->clust);
+ 7401              		.loc 1 4054 5 is_stmt 1 view .LVU2462
+4054:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc = clust2sect(fs, fp->clust);
+ 7402              		.loc 1 4054 17 is_stmt 0 view .LVU2463
+ 7403 00b4 7E1E     		subs	r6, r7, #1
+ 7404 00b6 3146     		mov	r1, r6
+ 7405 00b8 2046     		mov	r0, r4
+ 7406 00ba FFF7FEFF 		bl	clmt_clust
+ 7407              	.LVL851:
+ 7408 00be 0146     		mov	r1, r0
+4054:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc = clust2sect(fs, fp->clust);
+ 7409              		.loc 1 4054 15 view .LVU2464
+ 7410 00c0 E061     		str	r0, [r4, #28]
+4055:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!dsc) ABORT(fs, FR_INT_ERR);
+ 7411              		.loc 1 4055 5 is_stmt 1 view .LVU2465
+4055:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!dsc) ABORT(fs, FR_INT_ERR);
+ 7412              		.loc 1 4055 11 is_stmt 0 view .LVU2466
+ 7413 00c2 DDF80480 		ldr	r8, [sp, #4]
+ 7414 00c6 4046     		mov	r0, r8
+ 7415 00c8 FFF7FEFF 		bl	clust2sect
+ 7416              	.LVL852:
+4056:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+ 7417              		.loc 1 4056 5 is_stmt 1 view .LVU2467
+4056:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+ 7418              		.loc 1 4056 8 is_stmt 0 view .LVU2468
+ 7419 00cc 00B3     		cbz	r0, .L570
+4056:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+ 7420              		.loc 1 4056 36 is_stmt 1 discriminator 2 view .LVU2469
+4057:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+ 7421              		.loc 1 4057 5 discriminator 2 view .LVU2470
+4057:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+ 7422              		.loc 1 4057 32 is_stmt 0 discriminator 2 view .LVU2471
+ 7423 00ce B8F80C30 		ldrh	r3, [r8, #12]
+ARM GAS  /tmp/cc5lWXRL.s 			page 272
+
+
+4057:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+ 7424              		.loc 1 4057 12 discriminator 2 view .LVU2472
+ 7425 00d2 B6FBF3F6 		udiv	r6, r6, r3
+4057:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+ 7426              		.loc 1 4057 45 discriminator 2 view .LVU2473
+ 7427 00d6 B8F80A20 		ldrh	r2, [r8, #10]
+4057:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+ 7428              		.loc 1 4057 53 discriminator 2 view .LVU2474
+ 7429 00da 013A     		subs	r2, r2, #1
+4057:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+ 7430              		.loc 1 4057 40 discriminator 2 view .LVU2475
+ 7431 00dc 1640     		ands	r6, r6, r2
+4057:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+ 7432              		.loc 1 4057 9 discriminator 2 view .LVU2476
+ 7433 00de 0644     		add	r6, r6, r0
+ 7434              	.LVL853:
+4058:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 7435              		.loc 1 4058 5 is_stmt 1 discriminator 2 view .LVU2477
+4058:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 7436              		.loc 1 4058 18 is_stmt 0 discriminator 2 view .LVU2478
+ 7437 00e0 B7FBF3F2 		udiv	r2, r7, r3
+ 7438 00e4 03FB1277 		mls	r7, r3, r2, r7
+ 7439              	.LVL854:
+4058:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 7440              		.loc 1 4058 8 discriminator 2 view .LVU2479
+ 7441 00e8 002F     		cmp	r7, #0
+ 7442 00ea A3D0     		beq	.L525
+4058:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 7443              		.loc 1 4058 39 discriminator 1 view .LVU2480
+ 7444 00ec 226A     		ldr	r2, [r4, #32]
+4058:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 7445              		.loc 1 4058 27 discriminator 1 view .LVU2481
+ 7446 00ee B242     		cmp	r2, r6
+ 7447 00f0 A0D0     		beq	.L525
+4061:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 7448              		.loc 1 4061 6 is_stmt 1 view .LVU2482
+4061:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 7449              		.loc 1 4061 10 is_stmt 0 view .LVU2483
+ 7450 00f2 94F91430 		ldrsb	r3, [r4, #20]
+4061:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 7451              		.loc 1 4061 9 view .LVU2484
+ 7452 00f6 002B     		cmp	r3, #0
+ 7453 00f8 0DDB     		blt	.L571
+ 7454              	.L536:
+4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7455              		.loc 1 4066 6 is_stmt 1 view .LVU2485
+4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7456              		.loc 1 4066 10 is_stmt 0 view .LVU2486
+ 7457 00fa 0123     		movs	r3, #1
+ 7458 00fc 3246     		mov	r2, r6
+ 7459 00fe 04F13001 		add	r1, r4, #48
+ 7460 0102 0198     		ldr	r0, [sp, #4]
+ 7461 0104 4078     		ldrb	r0, [r0, #1]	@ zero_extendqisi2
+ 7462 0106 FFF7FEFF 		bl	disk_read
+ 7463              	.LVL855:
+4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7464              		.loc 1 4066 9 view .LVU2487
+ARM GAS  /tmp/cc5lWXRL.s 			page 273
+
+
+ 7465 010a A0B9     		cbnz	r0, .L572
+4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7466              		.loc 1 4066 79 is_stmt 1 discriminator 2 view .LVU2488
+4068:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7467              		.loc 1 4068 6 discriminator 2 view .LVU2489
+4068:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7468              		.loc 1 4068 15 is_stmt 0 discriminator 2 view .LVU2490
+ 7469 010c 2662     		str	r6, [r4, #32]
+ 7470 010e 91E7     		b	.L525
+ 7471              	.LVL856:
+ 7472              	.L570:
+4056:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+ 7473              		.loc 1 4056 15 is_stmt 1 discriminator 1 view .LVU2491
+ 7474 0110 0225     		movs	r5, #2
+ 7475              	.LVL857:
+4056:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+ 7476              		.loc 1 4056 15 is_stmt 0 discriminator 1 view .LVU2492
+ 7477 0112 6575     		strb	r5, [r4, #21]
+4056:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+ 7478              		.loc 1 4056 15 is_stmt 1 discriminator 1 view .LVU2493
+ 7479 0114 8EE7     		b	.L525
+ 7480              	.LVL858:
+ 7481              	.L571:
+4062:Middlewares/Third_Party/FatFs/src/ff.c **** 						fp->flag &= (BYTE)~FA_DIRTY;
+ 7482              		.loc 1 4062 7 view .LVU2494
+4062:Middlewares/Third_Party/FatFs/src/ff.c **** 						fp->flag &= (BYTE)~FA_DIRTY;
+ 7483              		.loc 1 4062 11 is_stmt 0 view .LVU2495
+ 7484 0116 0123     		movs	r3, #1
+ 7485 0118 04F13001 		add	r1, r4, #48
+ 7486 011c 98F80100 		ldrb	r0, [r8, #1]	@ zero_extendqisi2
+ 7487 0120 FFF7FEFF 		bl	disk_write
+ 7488              	.LVL859:
+4062:Middlewares/Third_Party/FatFs/src/ff.c **** 						fp->flag &= (BYTE)~FA_DIRTY;
+ 7489              		.loc 1 4062 10 view .LVU2496
+ 7490 0124 20B9     		cbnz	r0, .L573
+4062:Middlewares/Third_Party/FatFs/src/ff.c **** 						fp->flag &= (BYTE)~FA_DIRTY;
+ 7491              		.loc 1 4062 86 is_stmt 1 discriminator 2 view .LVU2497
+4063:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 7492              		.loc 1 4063 7 discriminator 2 view .LVU2498
+4063:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 7493              		.loc 1 4063 16 is_stmt 0 discriminator 2 view .LVU2499
+ 7494 0126 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 7495 0128 03F07F03 		and	r3, r3, #127
+ 7496 012c 2375     		strb	r3, [r4, #20]
+ 7497 012e E4E7     		b	.L536
+ 7498              	.L573:
+4062:Middlewares/Third_Party/FatFs/src/ff.c **** 						fp->flag &= (BYTE)~FA_DIRTY;
+ 7499              		.loc 1 4062 64 is_stmt 1 discriminator 1 view .LVU2500
+ 7500 0130 0125     		movs	r5, #1
+ 7501              	.LVL860:
+4062:Middlewares/Third_Party/FatFs/src/ff.c **** 						fp->flag &= (BYTE)~FA_DIRTY;
+ 7502              		.loc 1 4062 64 is_stmt 0 discriminator 1 view .LVU2501
+ 7503 0132 6575     		strb	r5, [r4, #21]
+4062:Middlewares/Third_Party/FatFs/src/ff.c **** 						fp->flag &= (BYTE)~FA_DIRTY;
+ 7504              		.loc 1 4062 64 is_stmt 1 discriminator 1 view .LVU2502
+ 7505 0134 7EE7     		b	.L525
+ 7506              	.LVL861:
+ARM GAS  /tmp/cc5lWXRL.s 			page 274
+
+
+ 7507              	.L572:
+4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7508              		.loc 1 4066 57 discriminator 1 view .LVU2503
+ 7509 0136 0125     		movs	r5, #1
+ 7510              	.LVL862:
+4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7511              		.loc 1 4066 57 is_stmt 0 discriminator 1 view .LVU2504
+ 7512 0138 6575     		strb	r5, [r4, #21]
+4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7513              		.loc 1 4066 57 is_stmt 1 discriminator 1 view .LVU2505
+ 7514 013a 7BE7     		b	.L525
+ 7515              	.LVL863:
+ 7516              	.L526:
+4080:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs = fp->obj.objsize;
+ 7517              		.loc 1 4080 3 view .LVU2506
+4080:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs = fp->obj.objsize;
+ 7518              		.loc 1 4080 20 is_stmt 0 view .LVU2507
+ 7519 013c E368     		ldr	r3, [r4, #12]
+4080:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs = fp->obj.objsize;
+ 7520              		.loc 1 4080 6 view .LVU2508
+ 7521 013e B342     		cmp	r3, r6
+ 7522 0140 04D2     		bcs	.L539
+4080:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs = fp->obj.objsize;
+ 7523              		.loc 1 4080 53 discriminator 1 view .LVU2509
+ 7524 0142 227D     		ldrb	r2, [r4, #20]	@ zero_extendqisi2
+4080:Middlewares/Third_Party/FatFs/src/ff.c **** 			ofs = fp->obj.objsize;
+ 7525              		.loc 1 4080 29 discriminator 1 view .LVU2510
+ 7526 0144 12F0020F 		tst	r2, #2
+ 7527 0148 00D1     		bne	.L539
+4081:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 7528              		.loc 1 4081 8 view .LVU2511
+ 7529 014a 1E46     		mov	r6, r3
+ 7530              	.LVL864:
+ 7531              	.L539:
+4083:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->fptr = nsect = 0;
+ 7532              		.loc 1 4083 3 is_stmt 1 view .LVU2512
+4083:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->fptr = nsect = 0;
+ 7533              		.loc 1 4083 9 is_stmt 0 view .LVU2513
+ 7534 014c A369     		ldr	r3, [r4, #24]
+ 7535              	.LVL865:
+4084:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs) {
+ 7536              		.loc 1 4084 3 is_stmt 1 view .LVU2514
+4084:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs) {
+ 7537              		.loc 1 4084 12 is_stmt 0 view .LVU2515
+ 7538 014e 0022     		movs	r2, #0
+ 7539 0150 A261     		str	r2, [r4, #24]
+4085:Middlewares/Third_Party/FatFs/src/ff.c **** 			bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size (byte) */
+ 7540              		.loc 1 4085 3 is_stmt 1 view .LVU2516
+4085:Middlewares/Third_Party/FatFs/src/ff.c **** 			bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size (byte) */
+ 7541              		.loc 1 4085 6 is_stmt 0 view .LVU2517
+ 7542 0152 E6B1     		cbz	r6, .L540
+4086:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ifptr > 0 &&
+ 7543              		.loc 1 4086 4 is_stmt 1 view .LVU2518
+4086:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ifptr > 0 &&
+ 7544              		.loc 1 4086 19 is_stmt 0 view .LVU2519
+ 7545 0154 019A     		ldr	r2, [sp, #4]
+ 7546 0156 B2F80A80 		ldrh	r8, [r2, #10]
+ARM GAS  /tmp/cc5lWXRL.s 			page 275
+
+
+4086:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ifptr > 0 &&
+ 7547              		.loc 1 4086 29 view .LVU2520
+ 7548 015a 9289     		ldrh	r2, [r2, #12]
+4086:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ifptr > 0 &&
+ 7549              		.loc 1 4086 8 view .LVU2521
+ 7550 015c 02FB08F8 		mul	r8, r2, r8
+ 7551              	.LVL866:
+4087:Middlewares/Third_Party/FatFs/src/ff.c **** 				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+ 7552              		.loc 1 4087 4 is_stmt 1 view .LVU2522
+4087:Middlewares/Third_Party/FatFs/src/ff.c **** 				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+ 7553              		.loc 1 4087 7 is_stmt 0 view .LVU2523
+ 7554 0160 73B1     		cbz	r3, .L541
+4088:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1);	/* start from the current cluster */
+ 7555              		.loc 1 4088 10 discriminator 1 view .LVU2524
+ 7556 0162 721E     		subs	r2, r6, #1
+4088:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1);	/* start from the current cluster */
+ 7557              		.loc 1 4088 15 discriminator 1 view .LVU2525
+ 7558 0164 B2FBF8F2 		udiv	r2, r2, r8
+4088:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1);	/* start from the current cluster */
+ 7559              		.loc 1 4088 31 discriminator 1 view .LVU2526
+ 7560 0168 013B     		subs	r3, r3, #1
+ 7561              	.LVL867:
+4088:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1);	/* start from the current cluster */
+ 7562              		.loc 1 4088 36 discriminator 1 view .LVU2527
+ 7563 016a B3FBF8F1 		udiv	r1, r3, r8
+4087:Middlewares/Third_Party/FatFs/src/ff.c **** 				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+ 7564              		.loc 1 4087 18 discriminator 1 view .LVU2528
+ 7565 016e 8A42     		cmp	r2, r1
+ 7566 0170 06D3     		bcc	.L541
+4089:Middlewares/Third_Party/FatFs/src/ff.c **** 				ofs -= fp->fptr;
+ 7567              		.loc 1 4089 5 is_stmt 1 view .LVU2529
+4089:Middlewares/Third_Party/FatFs/src/ff.c **** 				ofs -= fp->fptr;
+ 7568              		.loc 1 4089 30 is_stmt 0 view .LVU2530
+ 7569 0172 C8F10007 		rsb	r7, r8, #0
+4089:Middlewares/Third_Party/FatFs/src/ff.c **** 				ofs -= fp->fptr;
+ 7570              		.loc 1 4089 28 view .LVU2531
+ 7571 0176 1F40     		ands	r7, r7, r3
+4089:Middlewares/Third_Party/FatFs/src/ff.c **** 				ofs -= fp->fptr;
+ 7572              		.loc 1 4089 14 view .LVU2532
+ 7573 0178 A761     		str	r7, [r4, #24]
+4090:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = fp->clust;
+ 7574              		.loc 1 4090 5 is_stmt 1 view .LVU2533
+4090:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = fp->clust;
+ 7575              		.loc 1 4090 9 is_stmt 0 view .LVU2534
+ 7576 017a F71B     		subs	r7, r6, r7
+ 7577              	.LVL868:
+4091:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {									/* When seek to back cluster, */
+ 7578              		.loc 1 4091 5 is_stmt 1 view .LVU2535
+4091:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {									/* When seek to back cluster, */
+ 7579              		.loc 1 4091 10 is_stmt 0 view .LVU2536
+ 7580 017c E669     		ldr	r6, [r4, #28]
+ 7581              	.LVL869:
+4091:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {									/* When seek to back cluster, */
+ 7582              		.loc 1 4091 10 view .LVU2537
+ 7583 017e 04E0     		b	.L542
+ 7584              	.LVL870:
+ 7585              	.L541:
+ARM GAS  /tmp/cc5lWXRL.s 			page 276
+
+
+4093:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 7586              		.loc 1 4093 5 is_stmt 1 view .LVU2538
+4093:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 7587              		.loc 1 4093 10 is_stmt 0 view .LVU2539
+ 7588 0180 A068     		ldr	r0, [r4, #8]
+ 7589              	.LVL871:
+4095:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = create_chain(&fp->obj, 0);
+ 7590              		.loc 1 4095 5 is_stmt 1 view .LVU2540
+4095:Middlewares/Third_Party/FatFs/src/ff.c **** 					clst = create_chain(&fp->obj, 0);
+ 7591              		.loc 1 4095 8 is_stmt 0 view .LVU2541
+ 7592 0182 50B3     		cbz	r0, .L574
+ 7593              	.L543:
+4102:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7594              		.loc 1 4102 5 is_stmt 1 view .LVU2542
+4102:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7595              		.loc 1 4102 15 is_stmt 0 view .LVU2543
+ 7596 0184 E061     		str	r0, [r4, #28]
+ 7597 0186 3746     		mov	r7, r6
+ 7598 0188 0646     		mov	r6, r0
+ 7599              	.LVL872:
+ 7600              	.L542:
+4104:Middlewares/Third_Party/FatFs/src/ff.c **** 				while (ofs > bcs) {						/* Cluster following loop */
+ 7601              		.loc 1 4104 4 is_stmt 1 view .LVU2544
+4104:Middlewares/Third_Party/FatFs/src/ff.c **** 				while (ofs > bcs) {						/* Cluster following loop */
+ 7602              		.loc 1 4104 7 is_stmt 0 view .LVU2545
+ 7603 018a 002E     		cmp	r6, #0
+ 7604 018c 45D1     		bne	.L546
+ 7605              	.LVL873:
+ 7606              	.L540:
+4134:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.objsize = fp->fptr;
+ 7607              		.loc 1 4134 3 is_stmt 1 view .LVU2546
+4134:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.objsize = fp->fptr;
+ 7608              		.loc 1 4134 26 is_stmt 0 view .LVU2547
+ 7609 018e A369     		ldr	r3, [r4, #24]
+4134:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.objsize = fp->fptr;
+ 7610              		.loc 1 4134 42 view .LVU2548
+ 7611 0190 E268     		ldr	r2, [r4, #12]
+4134:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.objsize = fp->fptr;
+ 7612              		.loc 1 4134 6 view .LVU2549
+ 7613 0192 9342     		cmp	r3, r2
+ 7614 0194 04D9     		bls	.L555
+4135:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->flag |= FA_MODIFIED;
+ 7615              		.loc 1 4135 4 is_stmt 1 view .LVU2550
+4135:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->flag |= FA_MODIFIED;
+ 7616              		.loc 1 4135 20 is_stmt 0 view .LVU2551
+ 7617 0196 E360     		str	r3, [r4, #12]
+4136:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 7618              		.loc 1 4136 4 is_stmt 1 view .LVU2552
+4136:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 7619              		.loc 1 4136 13 is_stmt 0 view .LVU2553
+ 7620 0198 227D     		ldrb	r2, [r4, #20]	@ zero_extendqisi2
+ 7621 019a 42F04002 		orr	r2, r2, #64
+ 7622 019e 2275     		strb	r2, [r4, #20]
+ 7623              	.L555:
+4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 7624              		.loc 1 4138 3 is_stmt 1 view .LVU2554
+4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ARM GAS  /tmp/cc5lWXRL.s 			page 277
+
+
+ 7625              		.loc 1 4138 18 is_stmt 0 view .LVU2555
+ 7626 01a0 0198     		ldr	r0, [sp, #4]
+ 7627 01a2 8289     		ldrh	r2, [r0, #12]
+4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 7628              		.loc 1 4138 16 view .LVU2556
+ 7629 01a4 B3FBF2F1 		udiv	r1, r3, r2
+ 7630 01a8 02FB1133 		mls	r3, r2, r1, r3
+4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 7631              		.loc 1 4138 6 view .LVU2557
+ 7632 01ac 002B     		cmp	r3, #0
+ 7633 01ae 3FF441AF 		beq	.L525
+4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 7634              		.loc 1 4138 39 discriminator 1 view .LVU2558
+ 7635 01b2 226A     		ldr	r2, [r4, #32]
+4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 7636              		.loc 1 4138 25 discriminator 1 view .LVU2559
+ 7637 01b4 B242     		cmp	r2, r6
+ 7638 01b6 3FF43DAF 		beq	.L525
+4141:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 7639              		.loc 1 4141 4 is_stmt 1 view .LVU2560
+4141:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 7640              		.loc 1 4141 8 is_stmt 0 view .LVU2561
+ 7641 01ba 94F91430 		ldrsb	r3, [r4, #20]
+4141:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ 7642              		.loc 1 4141 7 view .LVU2562
+ 7643 01be 002B     		cmp	r3, #0
+ 7644 01c0 5DDB     		blt	.L575
+ 7645              	.L556:
+4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7646              		.loc 1 4146 4 is_stmt 1 view .LVU2563
+4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7647              		.loc 1 4146 8 is_stmt 0 view .LVU2564
+ 7648 01c2 0123     		movs	r3, #1
+ 7649 01c4 3246     		mov	r2, r6
+ 7650 01c6 04F13001 		add	r1, r4, #48
+ 7651 01ca 0198     		ldr	r0, [sp, #4]
+ 7652 01cc 4078     		ldrb	r0, [r0, #1]	@ zero_extendqisi2
+ 7653 01ce FFF7FEFF 		bl	disk_read
+ 7654              	.LVL874:
+4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7655              		.loc 1 4146 7 view .LVU2565
+ 7656 01d2 0028     		cmp	r0, #0
+ 7657 01d4 62D1     		bne	.L576
+4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7658              		.loc 1 4146 79 is_stmt 1 discriminator 2 view .LVU2566
+4148:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 7659              		.loc 1 4148 4 discriminator 2 view .LVU2567
+4148:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 7660              		.loc 1 4148 13 is_stmt 0 discriminator 2 view .LVU2568
+ 7661 01d6 2662     		str	r6, [r4, #32]
+ 7662 01d8 2CE7     		b	.L525
+ 7663              	.LVL875:
+ 7664              	.L574:
+4096:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 1) ABORT(fs, FR_INT_ERR);
+ 7665              		.loc 1 4096 6 is_stmt 1 view .LVU2569
+4096:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 1) ABORT(fs, FR_INT_ERR);
+ 7666              		.loc 1 4096 13 is_stmt 0 view .LVU2570
+ARM GAS  /tmp/cc5lWXRL.s 			page 278
+
+
+ 7667 01da 0021     		movs	r1, #0
+ 7668 01dc 2046     		mov	r0, r4
+ 7669              	.LVL876:
+4096:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 1) ABORT(fs, FR_INT_ERR);
+ 7670              		.loc 1 4096 13 view .LVU2571
+ 7671 01de FFF7FEFF 		bl	create_chain
+ 7672              	.LVL877:
+4097:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7673              		.loc 1 4097 6 is_stmt 1 view .LVU2572
+4097:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7674              		.loc 1 4097 9 is_stmt 0 view .LVU2573
+ 7675 01e2 0128     		cmp	r0, #1
+ 7676 01e4 04D0     		beq	.L577
+4097:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7677              		.loc 1 4097 42 is_stmt 1 discriminator 2 view .LVU2574
+4098:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.sclust = clst;
+ 7678              		.loc 1 4098 6 discriminator 2 view .LVU2575
+4098:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.sclust = clst;
+ 7679              		.loc 1 4098 9 is_stmt 0 discriminator 2 view .LVU2576
+ 7680 01e6 B0F1FF3F 		cmp	r0, #-1
+ 7681 01ea 04D0     		beq	.L578
+4098:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.sclust = clst;
+ 7682              		.loc 1 4098 52 is_stmt 1 discriminator 2 view .LVU2577
+4099:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7683              		.loc 1 4099 6 discriminator 2 view .LVU2578
+4099:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7684              		.loc 1 4099 21 is_stmt 0 discriminator 2 view .LVU2579
+ 7685 01ec A060     		str	r0, [r4, #8]
+ 7686 01ee C9E7     		b	.L543
+ 7687              	.L577:
+4097:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7688              		.loc 1 4097 21 is_stmt 1 discriminator 1 view .LVU2580
+ 7689 01f0 0225     		movs	r5, #2
+ 7690              	.LVL878:
+4097:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7691              		.loc 1 4097 21 is_stmt 0 discriminator 1 view .LVU2581
+ 7692 01f2 6575     		strb	r5, [r4, #21]
+4097:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ 7693              		.loc 1 4097 21 is_stmt 1 discriminator 1 view .LVU2582
+ 7694 01f4 1EE7     		b	.L525
+ 7695              	.LVL879:
+ 7696              	.L578:
+4098:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.sclust = clst;
+ 7697              		.loc 1 4098 30 discriminator 1 view .LVU2583
+ 7698 01f6 0125     		movs	r5, #1
+ 7699              	.LVL880:
+4098:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.sclust = clst;
+ 7700              		.loc 1 4098 30 is_stmt 0 discriminator 1 view .LVU2584
+ 7701 01f8 6575     		strb	r5, [r4, #21]
+4098:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->obj.sclust = clst;
+ 7702              		.loc 1 4098 30 is_stmt 1 discriminator 1 view .LVU2585
+ 7703 01fa 1BE7     		b	.L525
+ 7704              	.LVL881:
+ 7705              	.L547:
+4120:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 7706              		.loc 1 4120 7 view .LVU2586
+4120:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ARM GAS  /tmp/cc5lWXRL.s 			page 279
+
+
+ 7707              		.loc 1 4120 14 is_stmt 0 view .LVU2587
+ 7708 01fc 3146     		mov	r1, r6
+ 7709 01fe 2046     		mov	r0, r4
+ 7710 0200 FFF7FEFF 		bl	get_fat
+ 7711              	.LVL882:
+ 7712 0204 0646     		mov	r6, r0
+ 7713              	.LVL883:
+ 7714              	.L549:
+4122:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+ 7715              		.loc 1 4122 6 is_stmt 1 view .LVU2588
+4122:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+ 7716              		.loc 1 4122 9 is_stmt 0 view .LVU2589
+ 7717 0206 B6F1FF3F 		cmp	r6, #-1
+ 7718 020a 2DD0     		beq	.L579
+4122:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+ 7719              		.loc 1 4122 52 is_stmt 1 discriminator 2 view .LVU2590
+4123:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->clust = clst;
+ 7720              		.loc 1 4123 6 discriminator 2 view .LVU2591
+4123:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->clust = clst;
+ 7721              		.loc 1 4123 9 is_stmt 0 discriminator 2 view .LVU2592
+ 7722 020c 012E     		cmp	r6, #1
+ 7723 020e 2ED9     		bls	.L551
+4123:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->clust = clst;
+ 7724              		.loc 1 4123 33 discriminator 2 view .LVU2593
+ 7725 0210 019B     		ldr	r3, [sp, #4]
+ 7726 0212 9B69     		ldr	r3, [r3, #24]
+4123:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->clust = clst;
+ 7727              		.loc 1 4123 20 discriminator 2 view .LVU2594
+ 7728 0214 B342     		cmp	r3, r6
+ 7729 0216 2AD9     		bls	.L551
+4123:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->clust = clst;
+ 7730              		.loc 1 4123 66 is_stmt 1 discriminator 4 view .LVU2595
+4124:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7731              		.loc 1 4124 6 discriminator 4 view .LVU2596
+4124:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7732              		.loc 1 4124 16 is_stmt 0 discriminator 4 view .LVU2597
+ 7733 0218 E661     		str	r6, [r4, #28]
+ 7734              	.LVL884:
+ 7735              	.L546:
+4105:Middlewares/Third_Party/FatFs/src/ff.c **** 					ofs -= bcs; fp->fptr += bcs;
+ 7736              		.loc 1 4105 11 is_stmt 1 view .LVU2598
+ 7737 021a 4745     		cmp	r7, r8
+ 7738 021c 10D9     		bls	.L548
+4106:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 7739              		.loc 1 4106 6 view .LVU2599
+4106:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 7740              		.loc 1 4106 10 is_stmt 0 view .LVU2600
+ 7741 021e A7EB0807 		sub	r7, r7, r8
+ 7742              	.LVL885:
+4106:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 7743              		.loc 1 4106 18 is_stmt 1 view .LVU2601
+4106:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY
+ 7744              		.loc 1 4106 27 is_stmt 0 view .LVU2602
+ 7745 0222 A369     		ldr	r3, [r4, #24]
+ 7746 0224 4344     		add	r3, r3, r8
+ 7747 0226 A361     		str	r3, [r4, #24]
+4108:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (_FS_EXFAT && fp->fptr > fp->obj.objsize) {	/* No FAT chain object needs correct objsize t
+ARM GAS  /tmp/cc5lWXRL.s 			page 280
+
+
+ 7748              		.loc 1 4108 6 is_stmt 1 view .LVU2603
+4108:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (_FS_EXFAT && fp->fptr > fp->obj.objsize) {	/* No FAT chain object needs correct objsize t
+ 7749              		.loc 1 4108 12 is_stmt 0 view .LVU2604
+ 7750 0228 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+4108:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (_FS_EXFAT && fp->fptr > fp->obj.objsize) {	/* No FAT chain object needs correct objsize t
+ 7751              		.loc 1 4108 9 view .LVU2605
+ 7752 022a 13F0020F 		tst	r3, #2
+ 7753 022e E5D0     		beq	.L547
+4109:Middlewares/Third_Party/FatFs/src/ff.c **** 							fp->obj.objsize = fp->fptr;
+ 7754              		.loc 1 4109 7 is_stmt 1 view .LVU2606
+4113:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (clst == 0) {				/* Clip file size in case of disk full */
+ 7755              		.loc 1 4113 7 view .LVU2607
+4113:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (clst == 0) {				/* Clip file size in case of disk full */
+ 7756              		.loc 1 4113 14 is_stmt 0 view .LVU2608
+ 7757 0230 3146     		mov	r1, r6
+ 7758 0232 2046     		mov	r0, r4
+ 7759 0234 FFF7FEFF 		bl	create_chain
+ 7760              	.LVL886:
+4114:Middlewares/Third_Party/FatFs/src/ff.c **** 							ofs = 0; break;
+ 7761              		.loc 1 4114 7 is_stmt 1 view .LVU2609
+4114:Middlewares/Third_Party/FatFs/src/ff.c **** 							ofs = 0; break;
+ 7762              		.loc 1 4114 10 is_stmt 0 view .LVU2610
+ 7763 0238 0646     		mov	r6, r0
+ 7764 023a 0028     		cmp	r0, #0
+ 7765 023c E3D1     		bne	.L549
+4115:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 7766              		.loc 1 4115 12 view .LVU2611
+ 7767 023e 0746     		mov	r7, r0
+ 7768              	.LVL887:
+ 7769              	.L548:
+4126:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (ofs % SS(fs)) {
+ 7770              		.loc 1 4126 5 is_stmt 1 view .LVU2612
+4126:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (ofs % SS(fs)) {
+ 7771              		.loc 1 4126 14 is_stmt 0 view .LVU2613
+ 7772 0240 A369     		ldr	r3, [r4, #24]
+ 7773 0242 3B44     		add	r3, r3, r7
+ 7774 0244 A361     		str	r3, [r4, #24]
+4127:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect = clust2sect(fs, clst);	/* Current sector */
+ 7775              		.loc 1 4127 5 is_stmt 1 view .LVU2614
+4127:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect = clust2sect(fs, clst);	/* Current sector */
+ 7776              		.loc 1 4127 15 is_stmt 0 view .LVU2615
+ 7777 0246 0198     		ldr	r0, [sp, #4]
+ 7778 0248 B0F80C80 		ldrh	r8, [r0, #12]
+ 7779              	.LVL888:
+4127:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect = clust2sect(fs, clst);	/* Current sector */
+ 7780              		.loc 1 4127 13 view .LVU2616
+ 7781 024c B7FBF8F3 		udiv	r3, r7, r8
+ 7782 0250 08FB1373 		mls	r3, r8, r3, r7
+4127:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect = clust2sect(fs, clst);	/* Current sector */
+ 7783              		.loc 1 4127 8 view .LVU2617
+ 7784 0254 8BB1     		cbz	r3, .L564
+4128:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!nsect) ABORT(fs, FR_INT_ERR);
+ 7785              		.loc 1 4128 6 is_stmt 1 view .LVU2618
+4128:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!nsect) ABORT(fs, FR_INT_ERR);
+ 7786              		.loc 1 4128 14 is_stmt 0 view .LVU2619
+ 7787 0256 3146     		mov	r1, r6
+ 7788 0258 FFF7FEFF 		bl	clust2sect
+ARM GAS  /tmp/cc5lWXRL.s 			page 281
+
+
+ 7789              	.LVL889:
+4129:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect += (DWORD)(ofs / SS(fs));
+ 7790              		.loc 1 4129 6 is_stmt 1 view .LVU2620
+4129:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect += (DWORD)(ofs / SS(fs));
+ 7791              		.loc 1 4129 9 is_stmt 0 view .LVU2621
+ 7792 025c 0646     		mov	r6, r0
+ 7793              	.LVL890:
+4129:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect += (DWORD)(ofs / SS(fs));
+ 7794              		.loc 1 4129 9 view .LVU2622
+ 7795 025e 48B1     		cbz	r0, .L580
+4129:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect += (DWORD)(ofs / SS(fs));
+ 7796              		.loc 1 4129 39 is_stmt 1 discriminator 2 view .LVU2623
+4130:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7797              		.loc 1 4130 6 discriminator 2 view .LVU2624
+4130:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7798              		.loc 1 4130 15 is_stmt 0 discriminator 2 view .LVU2625
+ 7799 0260 B7FBF8F7 		udiv	r7, r7, r8
+ 7800              	.LVL891:
+4130:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7801              		.loc 1 4130 12 discriminator 2 view .LVU2626
+ 7802 0264 3E44     		add	r6, r6, r7
+ 7803              	.LVL892:
+4130:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 7804              		.loc 1 4130 12 discriminator 2 view .LVU2627
+ 7805 0266 92E7     		b	.L540
+ 7806              	.LVL893:
+ 7807              	.L579:
+4122:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+ 7808              		.loc 1 4122 30 is_stmt 1 discriminator 1 view .LVU2628
+ 7809 0268 0125     		movs	r5, #1
+ 7810              	.LVL894:
+4122:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+ 7811              		.loc 1 4122 30 is_stmt 0 discriminator 1 view .LVU2629
+ 7812 026a 6575     		strb	r5, [r4, #21]
+4122:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+ 7813              		.loc 1 4122 30 is_stmt 1 discriminator 1 view .LVU2630
+ 7814 026c E2E6     		b	.L525
+ 7815              	.LVL895:
+ 7816              	.L551:
+4123:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->clust = clst;
+ 7817              		.loc 1 4123 45 discriminator 3 view .LVU2631
+ 7818 026e 0225     		movs	r5, #2
+ 7819              	.LVL896:
+4123:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->clust = clst;
+ 7820              		.loc 1 4123 45 is_stmt 0 discriminator 3 view .LVU2632
+ 7821 0270 6575     		strb	r5, [r4, #21]
+4123:Middlewares/Third_Party/FatFs/src/ff.c **** 					fp->clust = clst;
+ 7822              		.loc 1 4123 45 is_stmt 1 discriminator 3 view .LVU2633
+ 7823 0272 DFE6     		b	.L525
+ 7824              	.LVL897:
+ 7825              	.L580:
+4129:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect += (DWORD)(ofs / SS(fs));
+ 7826              		.loc 1 4129 18 discriminator 1 view .LVU2634
+ 7827 0274 0225     		movs	r5, #2
+ 7828              	.LVL898:
+4129:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect += (DWORD)(ofs / SS(fs));
+ 7829              		.loc 1 4129 18 is_stmt 0 discriminator 1 view .LVU2635
+ARM GAS  /tmp/cc5lWXRL.s 			page 282
+
+
+ 7830 0276 6575     		strb	r5, [r4, #21]
+4129:Middlewares/Third_Party/FatFs/src/ff.c **** 					nsect += (DWORD)(ofs / SS(fs));
+ 7831              		.loc 1 4129 18 is_stmt 1 discriminator 1 view .LVU2636
+ 7832 0278 DCE6     		b	.L525
+ 7833              	.LVL899:
+ 7834              	.L564:
+4084:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs) {
+ 7835              		.loc 1 4084 20 is_stmt 0 view .LVU2637
+ 7836 027a 1E46     		mov	r6, r3
+ 7837              	.LVL900:
+4084:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (ofs) {
+ 7838              		.loc 1 4084 20 view .LVU2638
+ 7839 027c 87E7     		b	.L540
+ 7840              	.LVL901:
+ 7841              	.L575:
+4142:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 7842              		.loc 1 4142 5 is_stmt 1 view .LVU2639
+4142:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 7843              		.loc 1 4142 9 is_stmt 0 view .LVU2640
+ 7844 027e 0123     		movs	r3, #1
+ 7845 0280 04F13001 		add	r1, r4, #48
+ 7846 0284 4078     		ldrb	r0, [r0, #1]	@ zero_extendqisi2
+ 7847 0286 FFF7FEFF 		bl	disk_write
+ 7848              	.LVL902:
+4142:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 7849              		.loc 1 4142 8 view .LVU2641
+ 7850 028a 20B9     		cbnz	r0, .L581
+4142:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 7851              		.loc 1 4142 84 is_stmt 1 discriminator 2 view .LVU2642
+4143:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7852              		.loc 1 4143 5 discriminator 2 view .LVU2643
+4143:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7853              		.loc 1 4143 14 is_stmt 0 discriminator 2 view .LVU2644
+ 7854 028c 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 7855 028e 03F07F03 		and	r3, r3, #127
+ 7856 0292 2375     		strb	r3, [r4, #20]
+ 7857 0294 95E7     		b	.L556
+ 7858              	.L581:
+4142:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 7859              		.loc 1 4142 62 is_stmt 1 discriminator 1 view .LVU2645
+ 7860 0296 0125     		movs	r5, #1
+ 7861              	.LVL903:
+4142:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 7862              		.loc 1 4142 62 is_stmt 0 discriminator 1 view .LVU2646
+ 7863 0298 6575     		strb	r5, [r4, #21]
+4142:Middlewares/Third_Party/FatFs/src/ff.c **** 				fp->flag &= (BYTE)~FA_DIRTY;
+ 7864              		.loc 1 4142 62 is_stmt 1 discriminator 1 view .LVU2647
+ 7865 029a CBE6     		b	.L525
+ 7866              	.LVL904:
+ 7867              	.L576:
+4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7868              		.loc 1 4146 57 discriminator 1 view .LVU2648
+ 7869 029c 0125     		movs	r5, #1
+ 7870              	.LVL905:
+4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7871              		.loc 1 4146 57 is_stmt 0 discriminator 1 view .LVU2649
+ 7872 029e 6575     		strb	r5, [r4, #21]
+ARM GAS  /tmp/cc5lWXRL.s 			page 283
+
+
+4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 7873              		.loc 1 4146 57 is_stmt 1 discriminator 1 view .LVU2650
+ 7874 02a0 C8E6     		b	.L525
+ 7875              	.LVL906:
+ 7876              	.L561:
+4048:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7877              		.loc 1 4048 9 is_stmt 0 view .LVU2651
+ 7878 02a2 1125     		movs	r5, #17
+ 7879              	.LVL907:
+4048:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 7880              		.loc 1 4048 9 view .LVU2652
+ 7881 02a4 C6E6     		b	.L525
+ 7882              		.cfi_endproc
+ 7883              	.LFE1227:
+ 7885              		.section	.text.f_opendir,"ax",%progbits
+ 7886              		.align	1
+ 7887              		.global	f_opendir
+ 7888              		.syntax unified
+ 7889              		.thumb
+ 7890              		.thumb_func
+ 7891              		.fpu fpv5-d16
+ 7893              	f_opendir:
+ 7894              	.LVL908:
+ 7895              	.LFB1228:
+4166:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 7896              		.loc 1 4166 1 is_stmt 1 view -0
+ 7897              		.cfi_startproc
+ 7898              		@ args = 0, pretend = 0, frame = 16
+ 7899              		@ frame_needed = 0, uses_anonymous_args = 0
+4166:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 7900              		.loc 1 4166 1 is_stmt 0 view .LVU2654
+ 7901 0000 30B5     		push	{r4, r5, lr}
+ 7902              	.LCFI75:
+ 7903              		.cfi_def_cfa_offset 12
+ 7904              		.cfi_offset 4, -12
+ 7905              		.cfi_offset 5, -8
+ 7906              		.cfi_offset 14, -4
+ 7907 0002 85B0     		sub	sp, sp, #20
+ 7908              	.LCFI76:
+ 7909              		.cfi_def_cfa_offset 32
+ 7910 0004 0191     		str	r1, [sp, #4]
+4167:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 7911              		.loc 1 4167 2 is_stmt 1 view .LVU2655
+4168:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID *obj;
+ 7912              		.loc 1 4168 2 view .LVU2656
+4169:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+ 7913              		.loc 1 4169 2 view .LVU2657
+4173:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7914              		.loc 1 4173 2 view .LVU2658
+4173:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7915              		.loc 1 4173 5 is_stmt 0 view .LVU2659
+ 7916 0006 0028     		cmp	r0, #0
+ 7917 0008 3DD0     		beq	.L589
+ 7918 000a 0546     		mov	r5, r0
+4176:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path, &fs, 0);
+ 7919              		.loc 1 4176 2 is_stmt 1 view .LVU2660
+ 7920              	.LVL909:
+ARM GAS  /tmp/cc5lWXRL.s 			page 284
+
+
+4177:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 7921              		.loc 1 4177 2 view .LVU2661
+4177:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 7922              		.loc 1 4177 8 is_stmt 0 view .LVU2662
+ 7923 000c 0022     		movs	r2, #0
+ 7924 000e 03A9     		add	r1, sp, #12
+ 7925              	.LVL910:
+4177:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 7926              		.loc 1 4177 8 view .LVU2663
+ 7927 0010 01A8     		add	r0, sp, #4
+ 7928              	.LVL911:
+4177:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 7929              		.loc 1 4177 8 view .LVU2664
+ 7930 0012 FFF7FEFF 		bl	find_volume
+ 7931              	.LVL912:
+4178:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->fs = fs;
+ 7932              		.loc 1 4178 2 is_stmt 1 view .LVU2665
+4178:Middlewares/Third_Party/FatFs/src/ff.c **** 		obj->fs = fs;
+ 7933              		.loc 1 4178 5 is_stmt 0 view .LVU2666
+ 7934 0016 0446     		mov	r4, r0
+ 7935 0018 28B1     		cbz	r0, .L594
+ 7936              	.L584:
+4220:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7937              		.loc 1 4220 2 is_stmt 1 view .LVU2667
+4220:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7938              		.loc 1 4220 5 is_stmt 0 view .LVU2668
+ 7939 001a 0CB1     		cbz	r4, .L583
+ 7940              	.L588:
+4220:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7941              		.loc 1 4220 20 is_stmt 1 discriminator 1 view .LVU2669
+4220:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7942              		.loc 1 4220 28 is_stmt 0 discriminator 1 view .LVU2670
+ 7943 001c 0023     		movs	r3, #0
+ 7944 001e 2B60     		str	r3, [r5]
+ 7945              	.LVL913:
+ 7946              	.L583:
+4223:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 7947              		.loc 1 4223 1 view .LVU2671
+ 7948 0020 2046     		mov	r0, r4
+ 7949 0022 05B0     		add	sp, sp, #20
+ 7950              	.LCFI77:
+ 7951              		.cfi_remember_state
+ 7952              		.cfi_def_cfa_offset 12
+ 7953              		@ sp needed
+ 7954 0024 30BD     		pop	{r4, r5, pc}
+ 7955              	.LVL914:
+ 7956              	.L594:
+ 7957              	.LCFI78:
+ 7958              		.cfi_restore_state
+4179:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+ 7959              		.loc 1 4179 3 is_stmt 1 view .LVU2672
+4179:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+ 7960              		.loc 1 4179 11 is_stmt 0 view .LVU2673
+ 7961 0026 039B     		ldr	r3, [sp, #12]
+ 7962 0028 2B60     		str	r3, [r5]
+4180:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(dp, path);			/* Follow the path to the directory */
+ 7963              		.loc 1 4180 18 is_stmt 1 view .LVU2674
+ARM GAS  /tmp/cc5lWXRL.s 			page 285
+
+
+4181:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {						/* Follow completed */
+ 7964              		.loc 1 4181 3 view .LVU2675
+4181:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {						/* Follow completed */
+ 7965              		.loc 1 4181 9 is_stmt 0 view .LVU2676
+ 7966 002a 0199     		ldr	r1, [sp, #4]
+ 7967 002c 2846     		mov	r0, r5
+ 7968 002e FFF7FEFF 		bl	follow_path
+ 7969              	.LVL915:
+4182:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!(dp->fn[NSFLAG] & NS_NONAME)) {	/* It is not the origin directory itself */
+ 7970              		.loc 1 4182 3 is_stmt 1 view .LVU2677
+4182:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!(dp->fn[NSFLAG] & NS_NONAME)) {	/* It is not the origin directory itself */
+ 7971              		.loc 1 4182 6 is_stmt 0 view .LVU2678
+ 7972 0032 0446     		mov	r4, r0
+ 7973 0034 18BB     		cbnz	r0, .L585
+4183:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (obj->attr & AM_DIR) {		/* This object is a sub-directory */
+ 7974              		.loc 1 4183 4 is_stmt 1 view .LVU2679
+4183:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (obj->attr & AM_DIR) {		/* This object is a sub-directory */
+ 7975              		.loc 1 4183 8 is_stmt 0 view .LVU2680
+ 7976 0036 95F92F30 		ldrsb	r3, [r5, #47]
+4183:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (obj->attr & AM_DIR) {		/* This object is a sub-directory */
+ 7977              		.loc 1 4183 7 view .LVU2681
+ 7978 003a 002B     		cmp	r3, #0
+ 7979 003c 08DB     		blt	.L586
+4184:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 7980              		.loc 1 4184 5 is_stmt 1 view .LVU2682
+4184:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 7981              		.loc 1 4184 12 is_stmt 0 view .LVU2683
+ 7982 003e AB79     		ldrb	r3, [r5, #6]	@ zero_extendqisi2
+4184:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 7983              		.loc 1 4184 8 view .LVU2684
+ 7984 0040 13F0100F 		tst	r3, #16
+ 7985 0044 1AD0     		beq	.L590
+4196:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 7986              		.loc 1 4196 7 is_stmt 1 view .LVU2685
+4196:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 7987              		.loc 1 4196 21 is_stmt 0 view .LVU2686
+ 7988 0046 296A     		ldr	r1, [r5, #32]
+ 7989 0048 0398     		ldr	r0, [sp, #12]
+ 7990 004a FFF7FEFF 		bl	ld_clust
+ 7991              	.LVL916:
+4196:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 7992              		.loc 1 4196 19 view .LVU2687
+ 7993 004e A860     		str	r0, [r5, #8]
+ 7994              	.L586:
+4202:Middlewares/Third_Party/FatFs/src/ff.c **** 				obj->id = fs->id;
+ 7995              		.loc 1 4202 4 is_stmt 1 view .LVU2688
+4203:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_sdi(dp, 0);			/* Rewind directory */
+ 7996              		.loc 1 4203 5 view .LVU2689
+4203:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_sdi(dp, 0);			/* Rewind directory */
+ 7997              		.loc 1 4203 17 is_stmt 0 view .LVU2690
+ 7998 0050 039B     		ldr	r3, [sp, #12]
+ 7999 0052 DB88     		ldrh	r3, [r3, #6]
+4203:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_sdi(dp, 0);			/* Rewind directory */
+ 8000              		.loc 1 4203 13 view .LVU2691
+ 8001 0054 AB80     		strh	r3, [r5, #4]	@ movhi
+4204:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 8002              		.loc 1 4204 5 is_stmt 1 view .LVU2692
+ARM GAS  /tmp/cc5lWXRL.s 			page 286
+
+
+4204:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 8003              		.loc 1 4204 11 is_stmt 0 view .LVU2693
+ 8004 0056 0021     		movs	r1, #0
+ 8005 0058 2846     		mov	r0, r5
+ 8006 005a FFF7FEFF 		bl	dir_sdi
+ 8007              	.LVL917:
+4206:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (obj->sclust) {
+ 8008              		.loc 1 4206 5 is_stmt 1 view .LVU2694
+4206:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (obj->sclust) {
+ 8009              		.loc 1 4206 8 is_stmt 0 view .LVU2695
+ 8010 005e 0446     		mov	r4, r0
+ 8011 0060 68B9     		cbnz	r0, .L585
+4207:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->lockid = inc_lock(dp, 0);	/* Lock the sub directory */
+ 8012              		.loc 1 4207 6 is_stmt 1 view .LVU2696
+4207:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->lockid = inc_lock(dp, 0);	/* Lock the sub directory */
+ 8013              		.loc 1 4207 13 is_stmt 0 view .LVU2697
+ 8014 0062 AB68     		ldr	r3, [r5, #8]
+4207:Middlewares/Third_Party/FatFs/src/ff.c **** 						obj->lockid = inc_lock(dp, 0);	/* Lock the sub directory */
+ 8015              		.loc 1 4207 9 view .LVU2698
+ 8016 0064 13B9     		cbnz	r3, .L595
+4211:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 8017              		.loc 1 4211 7 is_stmt 1 view .LVU2699
+4211:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 8018              		.loc 1 4211 19 is_stmt 0 view .LVU2700
+ 8019 0066 0023     		movs	r3, #0
+ 8020 0068 2B61     		str	r3, [r5, #16]
+ 8021 006a 08E0     		b	.L585
+ 8022              	.L595:
+4208:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES;
+ 8023              		.loc 1 4208 7 is_stmt 1 view .LVU2701
+4208:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES;
+ 8024              		.loc 1 4208 21 is_stmt 0 view .LVU2702
+ 8025 006c 0021     		movs	r1, #0
+ 8026 006e 2846     		mov	r0, r5
+ 8027 0070 FFF7FEFF 		bl	inc_lock
+ 8028              	.LVL918:
+4208:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES;
+ 8029              		.loc 1 4208 19 view .LVU2703
+ 8030 0074 2861     		str	r0, [r5, #16]
+4209:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else {
+ 8031              		.loc 1 4209 7 is_stmt 1 view .LVU2704
+4209:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else {
+ 8032              		.loc 1 4209 10 is_stmt 0 view .LVU2705
+ 8033 0076 10B9     		cbnz	r0, .L585
+ 8034              	.LVL919:
+4209:Middlewares/Third_Party/FatFs/src/ff.c **** 					} else {
+ 8035              		.loc 1 4209 29 view .LVU2706
+ 8036 0078 1224     		movs	r4, #18
+ 8037 007a CEE7     		b	.L584
+ 8038              	.LVL920:
+ 8039              	.L590:
+4199:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 8040              		.loc 1 4199 10 view .LVU2707
+ 8041 007c 0524     		movs	r4, #5
+ 8042              	.LVL921:
+ 8043              	.L585:
+4217:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_NO_FILE) res = FR_NO_PATH;
+ARM GAS  /tmp/cc5lWXRL.s 			page 287
+
+
+ 8044              		.loc 1 4217 16 is_stmt 1 view .LVU2708
+4218:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 8045              		.loc 1 4218 3 view .LVU2709
+4218:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 8046              		.loc 1 4218 6 is_stmt 0 view .LVU2710
+ 8047 007e 042C     		cmp	r4, #4
+ 8048 0080 CBD1     		bne	.L584
+ 8049              	.LVL922:
+4218:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 8050              		.loc 1 4218 30 view .LVU2711
+ 8051 0082 0524     		movs	r4, #5
+ 8052 0084 CAE7     		b	.L588
+ 8053              	.LVL923:
+ 8054              	.L589:
+4173:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8055              		.loc 1 4173 18 view .LVU2712
+ 8056 0086 0924     		movs	r4, #9
+ 8057 0088 CAE7     		b	.L583
+ 8058              		.cfi_endproc
+ 8059              	.LFE1228:
+ 8061              		.section	.text.f_closedir,"ax",%progbits
+ 8062              		.align	1
+ 8063              		.global	f_closedir
+ 8064              		.syntax unified
+ 8065              		.thumb
+ 8066              		.thumb_func
+ 8067              		.fpu fpv5-d16
+ 8069              	f_closedir:
+ 8070              	.LVL924:
+ 8071              	.LFB1229:
+4235:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8072              		.loc 1 4235 1 is_stmt 1 view -0
+ 8073              		.cfi_startproc
+ 8074              		@ args = 0, pretend = 0, frame = 8
+ 8075              		@ frame_needed = 0, uses_anonymous_args = 0
+4235:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8076              		.loc 1 4235 1 is_stmt 0 view .LVU2714
+ 8077 0000 10B5     		push	{r4, lr}
+ 8078              	.LCFI79:
+ 8079              		.cfi_def_cfa_offset 8
+ 8080              		.cfi_offset 4, -8
+ 8081              		.cfi_offset 14, -4
+ 8082 0002 82B0     		sub	sp, sp, #8
+ 8083              	.LCFI80:
+ 8084              		.cfi_def_cfa_offset 16
+ 8085 0004 0446     		mov	r4, r0
+4236:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 8086              		.loc 1 4236 2 is_stmt 1 view .LVU2715
+4237:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8087              		.loc 1 4237 2 view .LVU2716
+4240:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8088              		.loc 1 4240 2 view .LVU2717
+4240:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8089              		.loc 1 4240 8 is_stmt 0 view .LVU2718
+ 8090 0006 01A9     		add	r1, sp, #4
+ 8091 0008 FFF7FEFF 		bl	validate
+ 8092              	.LVL925:
+ARM GAS  /tmp/cc5lWXRL.s 			page 288
+
+
+4241:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 8093              		.loc 1 4241 2 is_stmt 1 view .LVU2719
+4241:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 8094              		.loc 1 4241 5 is_stmt 0 view .LVU2720
+ 8095 000c 20B9     		cbnz	r0, .L597
+4243:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dec_lock(dp->obj.lockid);
+ 8096              		.loc 1 4243 3 is_stmt 1 view .LVU2721
+4243:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dec_lock(dp->obj.lockid);
+ 8097              		.loc 1 4243 14 is_stmt 0 view .LVU2722
+ 8098 000e 2369     		ldr	r3, [r4, #16]
+4243:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dec_lock(dp->obj.lockid);
+ 8099              		.loc 1 4243 6 view .LVU2723
+ 8100 0010 23B9     		cbnz	r3, .L600
+ 8101              	.L598:
+ 8102              	.LVL926:
+4246:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 8103              		.loc 1 4246 3 is_stmt 1 view .LVU2724
+4246:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 8104              		.loc 1 4246 6 is_stmt 0 view .LVU2725
+ 8105 0012 08B9     		cbnz	r0, .L597
+4249:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 8106              		.loc 1 4249 4 is_stmt 1 view .LVU2726
+4249:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 8107              		.loc 1 4249 15 is_stmt 0 view .LVU2727
+ 8108 0014 0023     		movs	r3, #0
+ 8109 0016 2360     		str	r3, [r4]
+ 8110              	.LVL927:
+ 8111              	.L597:
+4255:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 8112              		.loc 1 4255 2 is_stmt 1 view .LVU2728
+4256:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8113              		.loc 1 4256 1 is_stmt 0 view .LVU2729
+ 8114 0018 02B0     		add	sp, sp, #8
+ 8115              	.LCFI81:
+ 8116              		.cfi_remember_state
+ 8117              		.cfi_def_cfa_offset 8
+ 8118              		@ sp needed
+ 8119 001a 10BD     		pop	{r4, pc}
+ 8120              	.LVL928:
+ 8121              	.L600:
+ 8122              	.LCFI82:
+ 8123              		.cfi_restore_state
+4244:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 8124              		.loc 1 4244 4 is_stmt 1 view .LVU2730
+4244:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 8125              		.loc 1 4244 10 is_stmt 0 view .LVU2731
+ 8126 001c 1846     		mov	r0, r3
+ 8127 001e FFF7FEFF 		bl	dec_lock
+ 8128              	.LVL929:
+4244:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 8129              		.loc 1 4244 10 view .LVU2732
+ 8130 0022 F6E7     		b	.L598
+ 8131              		.cfi_endproc
+ 8132              	.LFE1229:
+ 8134              		.section	.text.f_readdir,"ax",%progbits
+ 8135              		.align	1
+ 8136              		.global	f_readdir
+ARM GAS  /tmp/cc5lWXRL.s 			page 289
+
+
+ 8137              		.syntax unified
+ 8138              		.thumb
+ 8139              		.thumb_func
+ 8140              		.fpu fpv5-d16
+ 8142              	f_readdir:
+ 8143              	.LVL930:
+ 8144              	.LFB1230:
+4269:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8145              		.loc 1 4269 1 is_stmt 1 view -0
+ 8146              		.cfi_startproc
+ 8147              		@ args = 0, pretend = 0, frame = 8
+ 8148              		@ frame_needed = 0, uses_anonymous_args = 0
+4269:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8149              		.loc 1 4269 1 is_stmt 0 view .LVU2734
+ 8150 0000 70B5     		push	{r4, r5, r6, lr}
+ 8151              	.LCFI83:
+ 8152              		.cfi_def_cfa_offset 16
+ 8153              		.cfi_offset 4, -16
+ 8154              		.cfi_offset 5, -12
+ 8155              		.cfi_offset 6, -8
+ 8156              		.cfi_offset 14, -4
+ 8157 0002 82B0     		sub	sp, sp, #8
+ 8158              	.LCFI84:
+ 8159              		.cfi_def_cfa_offset 24
+ 8160 0004 0446     		mov	r4, r0
+ 8161 0006 0D46     		mov	r5, r1
+4270:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 8162              		.loc 1 4270 2 is_stmt 1 view .LVU2735
+4271:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+ 8163              		.loc 1 4271 2 view .LVU2736
+4275:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8164              		.loc 1 4275 2 view .LVU2737
+4275:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8165              		.loc 1 4275 8 is_stmt 0 view .LVU2738
+ 8166 0008 01A9     		add	r1, sp, #4
+ 8167              	.LVL931:
+4275:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8168              		.loc 1 4275 8 view .LVU2739
+ 8169 000a FFF7FEFF 		bl	validate
+ 8170              	.LVL932:
+4276:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!fno) {
+ 8171              		.loc 1 4276 2 is_stmt 1 view .LVU2740
+4276:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!fno) {
+ 8172              		.loc 1 4276 5 is_stmt 0 view .LVU2741
+ 8173 000e 0646     		mov	r6, r0
+ 8174 0010 C0B9     		cbnz	r0, .L602
+4277:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dir_sdi(dp, 0);			/* Rewind the directory object */
+ 8175              		.loc 1 4277 3 is_stmt 1 view .LVU2742
+4277:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dir_sdi(dp, 0);			/* Rewind the directory object */
+ 8176              		.loc 1 4277 6 is_stmt 0 view .LVU2743
+ 8177 0012 95B1     		cbz	r5, .L607
+4280:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = dir_read(dp, 0);			/* Read an item */
+ 8178              		.loc 1 4280 19 is_stmt 1 view .LVU2744
+4281:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory */
+ 8179              		.loc 1 4281 4 view .LVU2745
+4281:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory */
+ 8180              		.loc 1 4281 10 is_stmt 0 view .LVU2746
+ARM GAS  /tmp/cc5lWXRL.s 			page 290
+
+
+ 8181 0014 0021     		movs	r1, #0
+ 8182 0016 2046     		mov	r0, r4
+ 8183              	.LVL933:
+4281:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory */
+ 8184              		.loc 1 4281 10 view .LVU2747
+ 8185 0018 FFF7FEFF 		bl	dir_read
+ 8186              	.LVL934:
+4282:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {				/* A valid entry is found */
+ 8187              		.loc 1 4282 4 is_stmt 1 view .LVU2748
+4282:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {				/* A valid entry is found */
+ 8188              		.loc 1 4282 7 is_stmt 0 view .LVU2749
+ 8189 001c 0428     		cmp	r0, #4
+ 8190 001e 00D0     		beq	.L604
+4283:Middlewares/Third_Party/FatFs/src/ff.c **** 				get_fileinfo(dp, fno);		/* Get the object information */
+ 8191              		.loc 1 4283 4 is_stmt 1 view .LVU2750
+4283:Middlewares/Third_Party/FatFs/src/ff.c **** 				get_fileinfo(dp, fno);		/* Get the object information */
+ 8192              		.loc 1 4283 7 is_stmt 0 view .LVU2751
+ 8193 0020 98B9     		cbnz	r0, .L605
+ 8194              	.L604:
+ 8195              	.LVL935:
+4284:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_next(dp, 0);		/* Increment index for next */
+ 8196              		.loc 1 4284 5 is_stmt 1 view .LVU2752
+ 8197 0022 2946     		mov	r1, r5
+ 8198 0024 2046     		mov	r0, r4
+ 8199 0026 FFF7FEFF 		bl	get_fileinfo
+ 8200              	.LVL936:
+4285:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory now */
+ 8201              		.loc 1 4285 5 view .LVU2753
+4285:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory now */
+ 8202              		.loc 1 4285 11 is_stmt 0 view .LVU2754
+ 8203 002a 0021     		movs	r1, #0
+ 8204 002c 2046     		mov	r0, r4
+ 8205 002e FFF7FEFF 		bl	dir_next
+ 8206              	.LVL937:
+4286:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8207              		.loc 1 4286 5 is_stmt 1 view .LVU2755
+4286:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8208              		.loc 1 4286 8 is_stmt 0 view .LVU2756
+ 8209 0032 0428     		cmp	r0, #4
+ 8210 0034 06D0     		beq	.L602
+4285:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory now */
+ 8211              		.loc 1 4285 11 view .LVU2757
+ 8212 0036 0646     		mov	r6, r0
+ 8213 0038 04E0     		b	.L602
+ 8214              	.L607:
+4278:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 8215              		.loc 1 4278 4 is_stmt 1 view .LVU2758
+4278:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 8216              		.loc 1 4278 10 is_stmt 0 view .LVU2759
+ 8217 003a 0021     		movs	r1, #0
+ 8218 003c 2046     		mov	r0, r4
+ 8219              	.LVL938:
+4278:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 8220              		.loc 1 4278 10 view .LVU2760
+ 8221 003e FFF7FEFF 		bl	dir_sdi
+ 8222              	.LVL939:
+ 8223 0042 0646     		mov	r6, r0
+ARM GAS  /tmp/cc5lWXRL.s 			page 291
+
+
+ 8224              	.LVL940:
+ 8225              	.L602:
+4288:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 8226              		.loc 1 4288 17 is_stmt 1 view .LVU2761
+4291:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 8227              		.loc 1 4291 2 view .LVU2762
+4292:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8228              		.loc 1 4292 1 is_stmt 0 view .LVU2763
+ 8229 0044 3046     		mov	r0, r6
+ 8230 0046 02B0     		add	sp, sp, #8
+ 8231              	.LCFI85:
+ 8232              		.cfi_remember_state
+ 8233              		.cfi_def_cfa_offset 16
+ 8234              		@ sp needed
+ 8235 0048 70BD     		pop	{r4, r5, r6, pc}
+ 8236              	.LVL941:
+ 8237              	.L605:
+ 8238              	.LCFI86:
+ 8239              		.cfi_restore_state
+4281:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory */
+ 8240              		.loc 1 4281 10 view .LVU2764
+ 8241 004a 0646     		mov	r6, r0
+ 8242 004c FAE7     		b	.L602
+ 8243              		.cfi_endproc
+ 8244              	.LFE1230:
+ 8246              		.section	.text.f_stat,"ax",%progbits
+ 8247              		.align	1
+ 8248              		.global	f_stat
+ 8249              		.syntax unified
+ 8250              		.thumb
+ 8251              		.thumb_func
+ 8252              		.fpu fpv5-d16
+ 8254              	f_stat:
+ 8255              	.LVL942:
+ 8256              	.LFB1231:
+4357:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8257              		.loc 1 4357 1 is_stmt 1 view -0
+ 8258              		.cfi_startproc
+ 8259              		@ args = 0, pretend = 0, frame = 56
+ 8260              		@ frame_needed = 0, uses_anonymous_args = 0
+4357:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8261              		.loc 1 4357 1 is_stmt 0 view .LVU2766
+ 8262 0000 30B5     		push	{r4, r5, lr}
+ 8263              	.LCFI87:
+ 8264              		.cfi_def_cfa_offset 12
+ 8265              		.cfi_offset 4, -12
+ 8266              		.cfi_offset 5, -8
+ 8267              		.cfi_offset 14, -4
+ 8268 0002 8FB0     		sub	sp, sp, #60
+ 8269              	.LCFI88:
+ 8270              		.cfi_def_cfa_offset 72
+ 8271 0004 0190     		str	r0, [sp, #4]
+ 8272 0006 0C46     		mov	r4, r1
+4358:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+ 8273              		.loc 1 4358 2 is_stmt 1 view .LVU2767
+4359:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+ 8274              		.loc 1 4359 2 view .LVU2768
+ARM GAS  /tmp/cc5lWXRL.s 			page 292
+
+
+4364:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8275              		.loc 1 4364 2 view .LVU2769
+4364:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8276              		.loc 1 4364 8 is_stmt 0 view .LVU2770
+ 8277 0008 0022     		movs	r2, #0
+ 8278 000a 02A9     		add	r1, sp, #8
+ 8279              	.LVL943:
+4364:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8280              		.loc 1 4364 8 view .LVU2771
+ 8281 000c 01A8     		add	r0, sp, #4
+ 8282              	.LVL944:
+4364:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8283              		.loc 1 4364 8 view .LVU2772
+ 8284 000e FFF7FEFF 		bl	find_volume
+ 8285              	.LVL945:
+4365:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(dj.obj.fs);
+ 8286              		.loc 1 4365 2 is_stmt 1 view .LVU2773
+4365:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(dj.obj.fs);
+ 8287              		.loc 1 4365 5 is_stmt 0 view .LVU2774
+ 8288 0012 0546     		mov	r5, r0
+ 8289 0014 10B1     		cbz	r0, .L612
+ 8290              	.LVL946:
+ 8291              	.L609:
+4375:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 8292              		.loc 1 4375 16 is_stmt 1 view .LVU2775
+4378:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 8293              		.loc 1 4378 2 view .LVU2776
+4379:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8294              		.loc 1 4379 1 is_stmt 0 view .LVU2777
+ 8295 0016 2846     		mov	r0, r5
+ 8296 0018 0FB0     		add	sp, sp, #60
+ 8297              	.LCFI89:
+ 8298              		.cfi_remember_state
+ 8299              		.cfi_def_cfa_offset 12
+ 8300              		@ sp needed
+ 8301 001a 30BD     		pop	{r4, r5, pc}
+ 8302              	.LVL947:
+ 8303              	.L612:
+ 8304              	.LCFI90:
+ 8305              		.cfi_restore_state
+4366:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&dj, path);	/* Follow the file path */
+ 8306              		.loc 1 4366 25 is_stmt 1 view .LVU2778
+4367:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {				/* Follow completed */
+ 8307              		.loc 1 4367 3 view .LVU2779
+4367:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {				/* Follow completed */
+ 8308              		.loc 1 4367 9 is_stmt 0 view .LVU2780
+ 8309 001c 0199     		ldr	r1, [sp, #4]
+ 8310 001e 02A8     		add	r0, sp, #8
+ 8311              	.LVL948:
+4367:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) {				/* Follow completed */
+ 8312              		.loc 1 4367 9 view .LVU2781
+ 8313 0020 FFF7FEFF 		bl	follow_path
+ 8314              	.LVL949:
+4368:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dj.fn[NSFLAG] & NS_NONAME) {	/* It is origin directory */
+ 8315              		.loc 1 4368 3 is_stmt 1 view .LVU2782
+4368:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dj.fn[NSFLAG] & NS_NONAME) {	/* It is origin directory */
+ 8316              		.loc 1 4368 6 is_stmt 0 view .LVU2783
+ARM GAS  /tmp/cc5lWXRL.s 			page 293
+
+
+ 8317 0024 0546     		mov	r5, r0
+ 8318 0026 0028     		cmp	r0, #0
+ 8319 0028 F5D1     		bne	.L609
+4369:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;
+ 8320              		.loc 1 4369 4 is_stmt 1 view .LVU2784
+4369:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;
+ 8321              		.loc 1 4369 8 is_stmt 0 view .LVU2785
+ 8322 002a 9DF93730 		ldrsb	r3, [sp, #55]
+4369:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;
+ 8323              		.loc 1 4369 7 view .LVU2786
+ 8324 002e 002B     		cmp	r3, #0
+ 8325 0030 06DB     		blt	.L610
+4372:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8326              		.loc 1 4372 5 is_stmt 1 view .LVU2787
+4372:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8327              		.loc 1 4372 8 is_stmt 0 view .LVU2788
+ 8328 0032 002C     		cmp	r4, #0
+ 8329 0034 EFD0     		beq	.L609
+4372:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8330              		.loc 1 4372 14 is_stmt 1 discriminator 1 view .LVU2789
+ 8331 0036 2146     		mov	r1, r4
+ 8332 0038 02A8     		add	r0, sp, #8
+ 8333              	.LVL950:
+4372:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8334              		.loc 1 4372 14 is_stmt 0 discriminator 1 view .LVU2790
+ 8335 003a FFF7FEFF 		bl	get_fileinfo
+ 8336              	.LVL951:
+ 8337 003e EAE7     		b	.L609
+ 8338              	.LVL952:
+ 8339              	.L610:
+4370:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {							/* Found an object */
+ 8340              		.loc 1 4370 9 view .LVU2791
+ 8341 0040 0625     		movs	r5, #6
+ 8342 0042 E8E7     		b	.L609
+ 8343              		.cfi_endproc
+ 8344              	.LFE1231:
+ 8346              		.section	.text.f_getfree,"ax",%progbits
+ 8347              		.align	1
+ 8348              		.global	f_getfree
+ 8349              		.syntax unified
+ 8350              		.thumb
+ 8351              		.thumb_func
+ 8352              		.fpu fpv5-d16
+ 8354              	f_getfree:
+ 8355              	.LVL953:
+ 8356              	.LFB1232:
+4393:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8357              		.loc 1 4393 1 is_stmt 1 view -0
+ 8358              		.cfi_startproc
+ 8359              		@ args = 0, pretend = 0, frame = 32
+ 8360              		@ frame_needed = 0, uses_anonymous_args = 0
+4393:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8361              		.loc 1 4393 1 is_stmt 0 view .LVU2793
+ 8362 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 8363              	.LCFI91:
+ 8364              		.cfi_def_cfa_offset 36
+ 8365              		.cfi_offset 4, -36
+ARM GAS  /tmp/cc5lWXRL.s 			page 294
+
+
+ 8366              		.cfi_offset 5, -32
+ 8367              		.cfi_offset 6, -28
+ 8368              		.cfi_offset 7, -24
+ 8369              		.cfi_offset 8, -20
+ 8370              		.cfi_offset 9, -16
+ 8371              		.cfi_offset 10, -12
+ 8372              		.cfi_offset 11, -8
+ 8373              		.cfi_offset 14, -4
+ 8374 0004 89B0     		sub	sp, sp, #36
+ 8375              	.LCFI92:
+ 8376              		.cfi_def_cfa_offset 72
+ 8377 0006 0190     		str	r0, [sp, #4]
+ 8378 0008 8846     		mov	r8, r1
+ 8379 000a 1446     		mov	r4, r2
+4394:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 8380              		.loc 1 4394 2 is_stmt 1 view .LVU2794
+4395:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD nfree, clst, sect, stat;
+ 8381              		.loc 1 4395 2 view .LVU2795
+4396:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+ 8382              		.loc 1 4396 2 view .LVU2796
+4397:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *p;
+ 8383              		.loc 1 4397 2 view .LVU2797
+4398:Middlewares/Third_Party/FatFs/src/ff.c **** 	_FDID obj;
+ 8384              		.loc 1 4398 2 view .LVU2798
+4399:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8385              		.loc 1 4399 2 view .LVU2799
+4403:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8386              		.loc 1 4403 2 view .LVU2800
+4403:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8387              		.loc 1 4403 8 is_stmt 0 view .LVU2801
+ 8388 000c 0022     		movs	r2, #0
+ 8389              	.LVL954:
+4403:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8390              		.loc 1 4403 8 view .LVU2802
+ 8391 000e 07A9     		add	r1, sp, #28
+ 8392              	.LVL955:
+4403:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8393              		.loc 1 4403 8 view .LVU2803
+ 8394 0010 01A8     		add	r0, sp, #4
+ 8395              	.LVL956:
+4403:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8396              		.loc 1 4403 8 view .LVU2804
+ 8397 0012 FFF7FEFF 		bl	find_volume
+ 8398              	.LVL957:
+4404:Middlewares/Third_Party/FatFs/src/ff.c **** 		*fatfs = fs;				/* Return ptr to the fs object */
+ 8399              		.loc 1 4404 2 is_stmt 1 view .LVU2805
+4404:Middlewares/Third_Party/FatFs/src/ff.c **** 		*fatfs = fs;				/* Return ptr to the fs object */
+ 8400              		.loc 1 4404 5 is_stmt 0 view .LVU2806
+ 8401 0016 8146     		mov	r9, r0
+ 8402 0018 0028     		cmp	r0, #0
+ 8403 001a 59D1     		bne	.L614
+4405:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* If free_clst is valid, return it without full cluster scan */
+ 8404              		.loc 1 4405 3 is_stmt 1 view .LVU2807
+4405:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* If free_clst is valid, return it without full cluster scan */
+ 8405              		.loc 1 4405 10 is_stmt 0 view .LVU2808
+ 8406 001c 079B     		ldr	r3, [sp, #28]
+ 8407 001e 2360     		str	r3, [r4]
+ARM GAS  /tmp/cc5lWXRL.s 			page 295
+
+
+4407:Middlewares/Third_Party/FatFs/src/ff.c **** 			*nclst = fs->free_clst;
+ 8408              		.loc 1 4407 3 is_stmt 1 view .LVU2809
+4407:Middlewares/Third_Party/FatFs/src/ff.c **** 			*nclst = fs->free_clst;
+ 8409              		.loc 1 4407 9 is_stmt 0 view .LVU2810
+ 8410 0020 5A69     		ldr	r2, [r3, #20]
+4407:Middlewares/Third_Party/FatFs/src/ff.c **** 			*nclst = fs->free_clst;
+ 8411              		.loc 1 4407 26 view .LVU2811
+ 8412 0022 9D69     		ldr	r5, [r3, #24]
+4407:Middlewares/Third_Party/FatFs/src/ff.c **** 			*nclst = fs->free_clst;
+ 8413              		.loc 1 4407 37 view .LVU2812
+ 8414 0024 A91E     		subs	r1, r5, #2
+4407:Middlewares/Third_Party/FatFs/src/ff.c **** 			*nclst = fs->free_clst;
+ 8415              		.loc 1 4407 6 view .LVU2813
+ 8416 0026 8A42     		cmp	r2, r1
+ 8417 0028 02D8     		bhi	.L615
+4408:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 8418              		.loc 1 4408 4 is_stmt 1 view .LVU2814
+4408:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 8419              		.loc 1 4408 11 is_stmt 0 view .LVU2815
+ 8420 002a C8F80020 		str	r2, [r8]
+ 8421 002e 4FE0     		b	.L614
+ 8422              	.L615:
+4411:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->fs_type == FS_FAT12) {	/* FAT12: Sector unalighed FAT entries */
+ 8423              		.loc 1 4411 4 is_stmt 1 view .LVU2816
+ 8424              	.LVL958:
+4412:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = 2; obj.fs = fs;
+ 8425              		.loc 1 4412 4 view .LVU2817
+4412:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = 2; obj.fs = fs;
+ 8426              		.loc 1 4412 10 is_stmt 0 view .LVU2818
+ 8427 0030 1E78     		ldrb	r6, [r3]	@ zero_extendqisi2
+4412:Middlewares/Third_Party/FatFs/src/ff.c **** 				clst = 2; obj.fs = fs;
+ 8428              		.loc 1 4412 7 view .LVU2819
+ 8429 0032 012E     		cmp	r6, #1
+ 8430 0034 05D0     		beq	.L629
+4440:Middlewares/Third_Party/FatFs/src/ff.c **** 					i = 0; p = 0;
+ 8431              		.loc 1 4440 6 is_stmt 1 view .LVU2820
+ 8432              	.LVL959:
+4440:Middlewares/Third_Party/FatFs/src/ff.c **** 					i = 0; p = 0;
+ 8433              		.loc 1 4440 27 view .LVU2821
+4440:Middlewares/Third_Party/FatFs/src/ff.c **** 					i = 0; p = 0;
+ 8434              		.loc 1 4440 32 is_stmt 0 view .LVU2822
+ 8435 0036 D3F824A0 		ldr	r10, [r3, #36]
+ 8436              	.LVL960:
+4441:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+ 8437              		.loc 1 4441 6 is_stmt 1 view .LVU2823
+4441:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+ 8438              		.loc 1 4441 13 view .LVU2824
+4441:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+ 8439              		.loc 1 4441 15 is_stmt 0 view .LVU2825
+ 8440 003a 0024     		movs	r4, #0
+ 8441              	.LVL961:
+4441:Middlewares/Third_Party/FatFs/src/ff.c **** 					do {
+ 8442              		.loc 1 4441 8 view .LVU2826
+ 8443 003c 2646     		mov	r6, r4
+4411:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->fs_type == FS_FAT12) {	/* FAT12: Sector unalighed FAT entries */
+ 8444              		.loc 1 4411 10 view .LVU2827
+ 8445 003e 2746     		mov	r7, r4
+ARM GAS  /tmp/cc5lWXRL.s 			page 296
+
+
+ 8446 0040 2FE0     		b	.L625
+ 8447              	.LVL962:
+ 8448              	.L629:
+4413:Middlewares/Third_Party/FatFs/src/ff.c **** 				do {
+ 8449              		.loc 1 4413 5 is_stmt 1 view .LVU2828
+4413:Middlewares/Third_Party/FatFs/src/ff.c **** 				do {
+ 8450              		.loc 1 4413 15 view .LVU2829
+4413:Middlewares/Third_Party/FatFs/src/ff.c **** 				do {
+ 8451              		.loc 1 4413 22 is_stmt 0 view .LVU2830
+ 8452 0042 0293     		str	r3, [sp, #8]
+4413:Middlewares/Third_Party/FatFs/src/ff.c **** 				do {
+ 8453              		.loc 1 4413 10 view .LVU2831
+ 8454 0044 0224     		movs	r4, #2
+ 8455              	.LVL963:
+4411:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fs->fs_type == FS_FAT12) {	/* FAT12: Sector unalighed FAT entries */
+ 8456              		.loc 1 4411 10 view .LVU2832
+ 8457 0046 0027     		movs	r7, #0
+ 8458 0048 04E0     		b	.L619
+ 8459              	.LVL964:
+ 8460              	.L618:
+4419:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 8461              		.loc 1 4419 13 is_stmt 1 view .LVU2833
+4419:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 8462              		.loc 1 4419 5 is_stmt 0 view .LVU2834
+ 8463 004a 0134     		adds	r4, r4, #1
+ 8464              	.LVL965:
+4419:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 8465              		.loc 1 4419 25 view .LVU2835
+ 8466 004c 079B     		ldr	r3, [sp, #28]
+ 8467 004e 9B69     		ldr	r3, [r3, #24]
+4419:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 8468              		.loc 1 4419 5 view .LVU2836
+ 8469 0050 A342     		cmp	r3, r4
+ 8470 0052 35D9     		bls	.L617
+ 8471              	.LVL966:
+ 8472              	.L619:
+4414:Middlewares/Third_Party/FatFs/src/ff.c **** 					stat = get_fat(&obj, clst);
+ 8473              		.loc 1 4414 5 is_stmt 1 view .LVU2837
+4415:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+ 8474              		.loc 1 4415 6 view .LVU2838
+4415:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+ 8475              		.loc 1 4415 13 is_stmt 0 view .LVU2839
+ 8476 0054 2146     		mov	r1, r4
+ 8477 0056 02A8     		add	r0, sp, #8
+ 8478 0058 FFF7FEFF 		bl	get_fat
+ 8479              	.LVL967:
+4416:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (stat == 1) { res = FR_INT_ERR; break; }
+ 8480              		.loc 1 4416 6 is_stmt 1 view .LVU2840
+4416:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (stat == 1) { res = FR_INT_ERR; break; }
+ 8481              		.loc 1 4416 9 is_stmt 0 view .LVU2841
+ 8482 005c B0F1FF3F 		cmp	r0, #-1
+ 8483 0060 2DD0     		beq	.L626
+4417:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (stat == 0) nfree++;
+ 8484              		.loc 1 4417 6 is_stmt 1 view .LVU2842
+4417:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (stat == 0) nfree++;
+ 8485              		.loc 1 4417 9 is_stmt 0 view .LVU2843
+ 8486 0062 0128     		cmp	r0, #1
+ARM GAS  /tmp/cc5lWXRL.s 			page 297
+
+
+ 8487 0064 38D0     		beq	.L627
+4418:Middlewares/Third_Party/FatFs/src/ff.c **** 				} while (++clst < fs->n_fatent);
+ 8488              		.loc 1 4418 6 is_stmt 1 view .LVU2844
+4418:Middlewares/Third_Party/FatFs/src/ff.c **** 				} while (++clst < fs->n_fatent);
+ 8489              		.loc 1 4418 9 is_stmt 0 view .LVU2845
+ 8490 0066 0028     		cmp	r0, #0
+ 8491 0068 EFD1     		bne	.L618
+4418:Middlewares/Third_Party/FatFs/src/ff.c **** 				} while (++clst < fs->n_fatent);
+ 8492              		.loc 1 4418 21 is_stmt 1 discriminator 1 view .LVU2846
+4418:Middlewares/Third_Party/FatFs/src/ff.c **** 				} while (++clst < fs->n_fatent);
+ 8493              		.loc 1 4418 26 is_stmt 0 discriminator 1 view .LVU2847
+ 8494 006a 0137     		adds	r7, r7, #1
+ 8495              	.LVL968:
+4418:Middlewares/Third_Party/FatFs/src/ff.c **** 				} while (++clst < fs->n_fatent);
+ 8496              		.loc 1 4418 26 discriminator 1 view .LVU2848
+ 8497 006c EDE7     		b	.L618
+ 8498              	.LVL969:
+ 8499              	.L630:
+4444:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res != FR_OK) break;
+ 8500              		.loc 1 4444 8 is_stmt 1 view .LVU2849
+4444:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res != FR_OK) break;
+ 8501              		.loc 1 4444 14 is_stmt 0 view .LVU2850
+ 8502 006e 0AF1010B 		add	fp, r10, #1
+ 8503              	.LVL970:
+4444:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res != FR_OK) break;
+ 8504              		.loc 1 4444 14 view .LVU2851
+ 8505 0072 5146     		mov	r1, r10
+ 8506 0074 0798     		ldr	r0, [sp, #28]
+ 8507 0076 FFF7FEFF 		bl	move_window
+ 8508              	.LVL971:
+4445:Middlewares/Third_Party/FatFs/src/ff.c **** 							p = fs->win;
+ 8509              		.loc 1 4445 8 is_stmt 1 view .LVU2852
+4445:Middlewares/Third_Party/FatFs/src/ff.c **** 							p = fs->win;
+ 8510              		.loc 1 4445 11 is_stmt 0 view .LVU2853
+ 8511 007a 8146     		mov	r9, r0
+ 8512 007c 00BB     		cbnz	r0, .L617
+4446:Middlewares/Third_Party/FatFs/src/ff.c **** 							i = SS(fs);
+ 8513              		.loc 1 4446 8 is_stmt 1 view .LVU2854
+4446:Middlewares/Third_Party/FatFs/src/ff.c **** 							i = SS(fs);
+ 8514              		.loc 1 4446 14 is_stmt 0 view .LVU2855
+ 8515 007e 079B     		ldr	r3, [sp, #28]
+4446:Middlewares/Third_Party/FatFs/src/ff.c **** 							i = SS(fs);
+ 8516              		.loc 1 4446 10 view .LVU2856
+ 8517 0080 03F13404 		add	r4, r3, #52
+ 8518              	.LVL972:
+4447:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 8519              		.loc 1 4447 8 is_stmt 1 view .LVU2857
+4447:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 8520              		.loc 1 4447 12 is_stmt 0 view .LVU2858
+ 8521 0084 9E89     		ldrh	r6, [r3, #12]
+ 8522              	.LVL973:
+4444:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res != FR_OK) break;
+ 8523              		.loc 1 4444 14 view .LVU2859
+ 8524 0086 DA46     		mov	r10, fp
+ 8525 0088 0DE0     		b	.L620
+ 8526              	.LVL974:
+ 8527              	.L631:
+ARM GAS  /tmp/cc5lWXRL.s 			page 298
+
+
+4450:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 2; i -= 2;
+ 8528              		.loc 1 4450 8 is_stmt 1 view .LVU2860
+4450:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 2; i -= 2;
+ 8529              		.loc 1 4450 12 is_stmt 0 view .LVU2861
+ 8530 008a 2046     		mov	r0, r4
+ 8531 008c FFF7FEFF 		bl	ld_word
+ 8532              	.LVL975:
+4450:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 2; i -= 2;
+ 8533              		.loc 1 4450 11 view .LVU2862
+ 8534 0090 00B9     		cbnz	r0, .L622
+4450:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 2; i -= 2;
+ 8535              		.loc 1 4450 29 is_stmt 1 discriminator 1 view .LVU2863
+4450:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 2; i -= 2;
+ 8536              		.loc 1 4450 34 is_stmt 0 discriminator 1 view .LVU2864
+ 8537 0092 0137     		adds	r7, r7, #1
+ 8538              	.LVL976:
+ 8539              	.L622:
+4451:Middlewares/Third_Party/FatFs/src/ff.c **** 						} else {
+ 8540              		.loc 1 4451 8 is_stmt 1 view .LVU2865
+4451:Middlewares/Third_Party/FatFs/src/ff.c **** 						} else {
+ 8541              		.loc 1 4451 10 is_stmt 0 view .LVU2866
+ 8542 0094 0234     		adds	r4, r4, #2
+ 8543              	.LVL977:
+4451:Middlewares/Third_Party/FatFs/src/ff.c **** 						} else {
+ 8544              		.loc 1 4451 16 is_stmt 1 view .LVU2867
+4451:Middlewares/Third_Party/FatFs/src/ff.c **** 						} else {
+ 8545              		.loc 1 4451 18 is_stmt 0 view .LVU2868
+ 8546 0096 023E     		subs	r6, r6, #2
+ 8547              	.LVL978:
+4451:Middlewares/Third_Party/FatFs/src/ff.c **** 						} else {
+ 8548              		.loc 1 4451 18 view .LVU2869
+ 8549 0098 01E0     		b	.L623
+ 8550              	.L624:
+4454:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 8551              		.loc 1 4454 8 is_stmt 1 view .LVU2870
+4454:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 8552              		.loc 1 4454 10 is_stmt 0 view .LVU2871
+ 8553 009a 0434     		adds	r4, r4, #4
+ 8554              	.LVL979:
+4454:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 8555              		.loc 1 4454 16 is_stmt 1 view .LVU2872
+4454:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 8556              		.loc 1 4454 18 is_stmt 0 view .LVU2873
+ 8557 009c 043E     		subs	r6, r6, #4
+ 8558              	.LVL980:
+ 8559              	.L623:
+4456:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 8560              		.loc 1 4456 14 is_stmt 1 view .LVU2874
+4456:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 8561              		.loc 1 4456 6 is_stmt 0 view .LVU2875
+ 8562 009e 013D     		subs	r5, r5, #1
+ 8563              	.LVL981:
+4456:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 8564              		.loc 1 4456 6 view .LVU2876
+ 8565 00a0 0ED0     		beq	.L617
+ 8566              	.LVL982:
+ 8567              	.L625:
+ARM GAS  /tmp/cc5lWXRL.s 			page 299
+
+
+4442:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (i == 0) {
+ 8568              		.loc 1 4442 6 is_stmt 1 view .LVU2877
+4443:Middlewares/Third_Party/FatFs/src/ff.c **** 							res = move_window(fs, sect++);
+ 8569              		.loc 1 4443 7 view .LVU2878
+4443:Middlewares/Third_Party/FatFs/src/ff.c **** 							res = move_window(fs, sect++);
+ 8570              		.loc 1 4443 10 is_stmt 0 view .LVU2879
+ 8571 00a2 002E     		cmp	r6, #0
+ 8572 00a4 E3D0     		beq	.L630
+ 8573              	.LVL983:
+ 8574              	.L620:
+4449:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (ld_word(p) == 0) nfree++;
+ 8575              		.loc 1 4449 7 is_stmt 1 view .LVU2880
+4449:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (ld_word(p) == 0) nfree++;
+ 8576              		.loc 1 4449 13 is_stmt 0 view .LVU2881
+ 8577 00a6 079B     		ldr	r3, [sp, #28]
+ 8578 00a8 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+4449:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (ld_word(p) == 0) nfree++;
+ 8579              		.loc 1 4449 10 view .LVU2882
+ 8580 00aa 022B     		cmp	r3, #2
+ 8581 00ac EDD0     		beq	.L631
+4453:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 4; i -= 4;
+ 8582              		.loc 1 4453 8 is_stmt 1 view .LVU2883
+4453:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 4; i -= 4;
+ 8583              		.loc 1 4453 13 is_stmt 0 view .LVU2884
+ 8584 00ae 2046     		mov	r0, r4
+ 8585 00b0 FFF7FEFF 		bl	ld_dword
+ 8586              	.LVL984:
+4453:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 4; i -= 4;
+ 8587              		.loc 1 4453 11 view .LVU2885
+ 8588 00b4 30F07043 		bics	r3, r0, #-268435456
+ 8589 00b8 EFD1     		bne	.L624
+4453:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 4; i -= 4;
+ 8590              		.loc 1 4453 45 is_stmt 1 discriminator 1 view .LVU2886
+4453:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 4; i -= 4;
+ 8591              		.loc 1 4453 50 is_stmt 0 discriminator 1 view .LVU2887
+ 8592 00ba 0137     		adds	r7, r7, #1
+ 8593              	.LVL985:
+4453:Middlewares/Third_Party/FatFs/src/ff.c **** 							p += 4; i -= 4;
+ 8594              		.loc 1 4453 50 discriminator 1 view .LVU2888
+ 8595 00bc EDE7     		b	.L624
+ 8596              	.LVL986:
+ 8597              	.L626:
+4416:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (stat == 1) { res = FR_INT_ERR; break; }
+ 8598              		.loc 1 4416 36 view .LVU2889
+ 8599 00be B146     		mov	r9, r6
+ 8600              	.LVL987:
+ 8601              	.L617:
+4459:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->free_clst = nfree;	/* Now free_clst is valid */
+ 8602              		.loc 1 4459 4 is_stmt 1 view .LVU2890
+4459:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->free_clst = nfree;	/* Now free_clst is valid */
+ 8603              		.loc 1 4459 11 is_stmt 0 view .LVU2891
+ 8604 00c0 C8F80070 		str	r7, [r8]
+4460:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->fsi_flag |= 1;		/* FSInfo is to be updated */
+ 8605              		.loc 1 4460 4 is_stmt 1 view .LVU2892
+4460:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->fsi_flag |= 1;		/* FSInfo is to be updated */
+ 8606              		.loc 1 4460 6 is_stmt 0 view .LVU2893
+ 8607 00c4 079B     		ldr	r3, [sp, #28]
+ARM GAS  /tmp/cc5lWXRL.s 			page 300
+
+
+4460:Middlewares/Third_Party/FatFs/src/ff.c **** 			fs->fsi_flag |= 1;		/* FSInfo is to be updated */
+ 8608              		.loc 1 4460 18 view .LVU2894
+ 8609 00c6 5F61     		str	r7, [r3, #20]
+4461:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 8610              		.loc 1 4461 4 is_stmt 1 view .LVU2895
+4461:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 8611              		.loc 1 4461 17 is_stmt 0 view .LVU2896
+ 8612 00c8 1A79     		ldrb	r2, [r3, #4]	@ zero_extendqisi2
+ 8613 00ca 42F00102 		orr	r2, r2, #1
+ 8614 00ce 1A71     		strb	r2, [r3, #4]
+ 8615              	.LVL988:
+ 8616              	.L614:
+4465:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 8617              		.loc 1 4465 2 is_stmt 1 view .LVU2897
+4466:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8618              		.loc 1 4466 1 is_stmt 0 view .LVU2898
+ 8619 00d0 4846     		mov	r0, r9
+ 8620 00d2 09B0     		add	sp, sp, #36
+ 8621              	.LCFI93:
+ 8622              		.cfi_remember_state
+ 8623              		.cfi_def_cfa_offset 36
+ 8624              		@ sp needed
+ 8625 00d4 BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 8626              	.LVL989:
+ 8627              	.L627:
+ 8628              	.LCFI94:
+ 8629              		.cfi_restore_state
+4417:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (stat == 0) nfree++;
+ 8630              		.loc 1 4417 27 view .LVU2899
+ 8631 00d8 4FF00209 		mov	r9, #2
+ 8632 00dc F0E7     		b	.L617
+ 8633              		.cfi_endproc
+ 8634              	.LFE1232:
+ 8636              		.section	.text.f_truncate,"ax",%progbits
+ 8637              		.align	1
+ 8638              		.global	f_truncate
+ 8639              		.syntax unified
+ 8640              		.thumb
+ 8641              		.thumb_func
+ 8642              		.fpu fpv5-d16
+ 8644              	f_truncate:
+ 8645              	.LVL990:
+ 8646              	.LFB1233:
+4478:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8647              		.loc 1 4478 1 is_stmt 1 view -0
+ 8648              		.cfi_startproc
+ 8649              		@ args = 0, pretend = 0, frame = 8
+ 8650              		@ frame_needed = 0, uses_anonymous_args = 0
+4478:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8651              		.loc 1 4478 1 is_stmt 0 view .LVU2901
+ 8652 0000 30B5     		push	{r4, r5, lr}
+ 8653              	.LCFI95:
+ 8654              		.cfi_def_cfa_offset 12
+ 8655              		.cfi_offset 4, -12
+ 8656              		.cfi_offset 5, -8
+ 8657              		.cfi_offset 14, -4
+ 8658 0002 83B0     		sub	sp, sp, #12
+ARM GAS  /tmp/cc5lWXRL.s 			page 301
+
+
+ 8659              	.LCFI96:
+ 8660              		.cfi_def_cfa_offset 24
+ 8661 0004 0446     		mov	r4, r0
+4479:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 8662              		.loc 1 4479 2 is_stmt 1 view .LVU2902
+4480:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD ncl;
+ 8663              		.loc 1 4480 2 view .LVU2903
+4481:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8664              		.loc 1 4481 2 view .LVU2904
+4484:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+ 8665              		.loc 1 4484 2 view .LVU2905
+4484:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+ 8666              		.loc 1 4484 8 is_stmt 0 view .LVU2906
+ 8667 0006 01A9     		add	r1, sp, #4
+ 8668 0008 FFF7FEFF 		bl	validate
+ 8669              	.LVL991:
+4485:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+ 8670              		.loc 1 4485 2 is_stmt 1 view .LVU2907
+4485:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+ 8671              		.loc 1 4485 5 is_stmt 0 view .LVU2908
+ 8672 000c 0546     		mov	r5, r0
+ 8673 000e E8B9     		cbnz	r0, .L635
+4485:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+ 8674              		.loc 1 4485 27 discriminator 2 view .LVU2909
+ 8675 0010 657D     		ldrb	r5, [r4, #21]	@ zero_extendqisi2
+ 8676              	.LVL992:
+4485:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+ 8677              		.loc 1 4485 19 discriminator 2 view .LVU2910
+ 8678 0012 DDB9     		cbnz	r5, .L635
+4486:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8679              		.loc 1 4486 2 is_stmt 1 view .LVU2911
+4486:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8680              		.loc 1 4486 10 is_stmt 0 view .LVU2912
+ 8681 0014 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+4486:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8682              		.loc 1 4486 5 view .LVU2913
+ 8683 0016 13F0020F 		tst	r3, #2
+ 8684 001a 45D0     		beq	.L641
+4488:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+ 8685              		.loc 1 4488 2 is_stmt 1 view .LVU2914
+4488:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+ 8686              		.loc 1 4488 8 is_stmt 0 view .LVU2915
+ 8687 001c A369     		ldr	r3, [r4, #24]
+4488:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+ 8688              		.loc 1 4488 24 view .LVU2916
+ 8689 001e E268     		ldr	r2, [r4, #12]
+4488:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+ 8690              		.loc 1 4488 5 view .LVU2917
+ 8691 0020 9342     		cmp	r3, r2
+ 8692 0022 13D2     		bcs	.L635
+4489:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+ 8693              		.loc 1 4489 3 is_stmt 1 view .LVU2918
+4489:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+ 8694              		.loc 1 4489 6 is_stmt 0 view .LVU2919
+ 8695 0024 ABB9     		cbnz	r3, .L636
+4490:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.sclust = 0;
+ 8696              		.loc 1 4490 4 is_stmt 1 view .LVU2920
+ARM GAS  /tmp/cc5lWXRL.s 			page 302
+
+
+4490:Middlewares/Third_Party/FatFs/src/ff.c **** 			fp->obj.sclust = 0;
+ 8697              		.loc 1 4490 10 is_stmt 0 view .LVU2921
+ 8698 0026 0022     		movs	r2, #0
+ 8699 0028 A168     		ldr	r1, [r4, #8]
+ 8700 002a 2046     		mov	r0, r4
+ 8701 002c FFF7FEFF 		bl	remove_chain
+ 8702              	.LVL993:
+ 8703 0030 0546     		mov	r5, r0
+ 8704              	.LVL994:
+4491:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {				/* When truncate a part of the file, remove remaining clusters */
+ 8705              		.loc 1 4491 4 is_stmt 1 view .LVU2922
+4491:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {				/* When truncate a part of the file, remove remaining clusters */
+ 8706              		.loc 1 4491 19 is_stmt 0 view .LVU2923
+ 8707 0032 0023     		movs	r3, #0
+ 8708 0034 A360     		str	r3, [r4, #8]
+ 8709              	.LVL995:
+ 8710              	.L637:
+4501:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->flag |= FA_MODIFIED;
+ 8711              		.loc 1 4501 3 is_stmt 1 view .LVU2924
+4501:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->flag |= FA_MODIFIED;
+ 8712              		.loc 1 4501 23 is_stmt 0 view .LVU2925
+ 8713 0036 A369     		ldr	r3, [r4, #24]
+4501:Middlewares/Third_Party/FatFs/src/ff.c **** 		fp->flag |= FA_MODIFIED;
+ 8714              		.loc 1 4501 19 view .LVU2926
+ 8715 0038 E360     		str	r3, [r4, #12]
+4502:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 8716              		.loc 1 4502 3 is_stmt 1 view .LVU2927
+4502:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY
+ 8717              		.loc 1 4502 12 is_stmt 0 view .LVU2928
+ 8718 003a 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 8719 003c 43F04003 		orr	r3, r3, #64
+ 8720 0040 2375     		strb	r3, [r4, #20]
+4504:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) {
+ 8721              		.loc 1 4504 3 is_stmt 1 view .LVU2929
+4504:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) {
+ 8722              		.loc 1 4504 6 is_stmt 0 view .LVU2930
+ 8723 0042 15B9     		cbnz	r5, .L639
+4504:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) {
+ 8724              		.loc 1 4504 20 discriminator 1 view .LVU2931
+ 8725 0044 13F0800F 		tst	r3, #128
+ 8726 0048 1DD1     		bne	.L646
+ 8727              	.L639:
+4512:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 8728              		.loc 1 4512 3 is_stmt 1 view .LVU2932
+4512:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 8729              		.loc 1 4512 6 is_stmt 0 view .LVU2933
+ 8730 004a 5DBB     		cbnz	r5, .L640
+ 8731              	.LVL996:
+ 8732              	.L635:
+4516:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8733              		.loc 1 4516 1 view .LVU2934
+ 8734 004c 2846     		mov	r0, r5
+ 8735 004e 03B0     		add	sp, sp, #12
+ 8736              	.LCFI97:
+ 8737              		.cfi_remember_state
+ 8738              		.cfi_def_cfa_offset 12
+ 8739              		@ sp needed
+ARM GAS  /tmp/cc5lWXRL.s 			page 303
+
+
+ 8740 0050 30BD     		pop	{r4, r5, pc}
+ 8741              	.LVL997:
+ 8742              	.L636:
+ 8743              	.LCFI98:
+ 8744              		.cfi_restore_state
+4493:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+ 8745              		.loc 1 4493 4 is_stmt 1 view .LVU2935
+4493:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+ 8746              		.loc 1 4493 10 is_stmt 0 view .LVU2936
+ 8747 0052 E169     		ldr	r1, [r4, #28]
+ 8748 0054 2046     		mov	r0, r4
+ 8749 0056 FFF7FEFF 		bl	get_fat
+ 8750              	.LVL998:
+4494:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ 8751              		.loc 1 4494 4 is_stmt 1 view .LVU2937
+4495:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl == 1) res = FR_INT_ERR;
+ 8752              		.loc 1 4495 4 view .LVU2938
+4495:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl == 1) res = FR_INT_ERR;
+ 8753              		.loc 1 4495 7 is_stmt 0 view .LVU2939
+ 8754 005a B0F1FF3F 		cmp	r0, #-1
+ 8755 005e 0ED0     		beq	.L647
+ 8756              	.L638:
+ 8757              	.LVL999:
+4496:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK && ncl < fs->n_fatent) {
+ 8758              		.loc 1 4496 4 is_stmt 1 view .LVU2940
+4496:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK && ncl < fs->n_fatent) {
+ 8759              		.loc 1 4496 7 is_stmt 0 view .LVU2941
+ 8760 0060 0128     		cmp	r0, #1
+ 8761 0062 0ED0     		beq	.L643
+4497:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = remove_chain(&fp->obj, ncl, fp->clust);
+ 8762              		.loc 1 4497 4 is_stmt 1 view .LVU2942
+4497:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = remove_chain(&fp->obj, ncl, fp->clust);
+ 8763              		.loc 1 4497 7 is_stmt 0 view .LVU2943
+ 8764 0064 002D     		cmp	r5, #0
+ 8765 0066 E6D1     		bne	.L637
+4497:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = remove_chain(&fp->obj, ncl, fp->clust);
+ 8766              		.loc 1 4497 32 discriminator 1 view .LVU2944
+ 8767 0068 019B     		ldr	r3, [sp, #4]
+ 8768 006a 9B69     		ldr	r3, [r3, #24]
+4497:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = remove_chain(&fp->obj, ncl, fp->clust);
+ 8769              		.loc 1 4497 21 discriminator 1 view .LVU2945
+ 8770 006c 8342     		cmp	r3, r0
+ 8771 006e E2D9     		bls	.L637
+4498:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8772              		.loc 1 4498 5 is_stmt 1 view .LVU2946
+4498:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8773              		.loc 1 4498 11 is_stmt 0 view .LVU2947
+ 8774 0070 E269     		ldr	r2, [r4, #28]
+ 8775 0072 0146     		mov	r1, r0
+ 8776 0074 2046     		mov	r0, r4
+ 8777              	.LVL1000:
+4498:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8778              		.loc 1 4498 11 view .LVU2948
+ 8779 0076 FFF7FEFF 		bl	remove_chain
+ 8780              	.LVL1001:
+4498:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8781              		.loc 1 4498 11 view .LVU2949
+ARM GAS  /tmp/cc5lWXRL.s 			page 304
+
+
+ 8782 007a 0546     		mov	r5, r0
+ 8783              	.LVL1002:
+4498:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8784              		.loc 1 4498 11 view .LVU2950
+ 8785 007c DBE7     		b	.L637
+ 8786              	.LVL1003:
+ 8787              	.L647:
+4495:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (ncl == 1) res = FR_INT_ERR;
+ 8788              		.loc 1 4495 31 view .LVU2951
+ 8789 007e 0125     		movs	r5, #1
+ 8790 0080 EEE7     		b	.L638
+ 8791              	.LVL1004:
+ 8792              	.L643:
+4496:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK && ncl < fs->n_fatent) {
+ 8793              		.loc 1 4496 22 view .LVU2952
+ 8794 0082 0225     		movs	r5, #2
+ 8795              	.LVL1005:
+4496:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK && ncl < fs->n_fatent) {
+ 8796              		.loc 1 4496 22 view .LVU2953
+ 8797 0084 D7E7     		b	.L637
+ 8798              	.LVL1006:
+ 8799              	.L646:
+4505:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_DISK_ERR;
+ 8800              		.loc 1 4505 4 is_stmt 1 view .LVU2954
+4505:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_DISK_ERR;
+ 8801              		.loc 1 4505 8 is_stmt 0 view .LVU2955
+ 8802 0086 0123     		movs	r3, #1
+ 8803 0088 226A     		ldr	r2, [r4, #32]
+ 8804 008a 04F13001 		add	r1, r4, #48
+ 8805 008e 0198     		ldr	r0, [sp, #4]
+ 8806 0090 4078     		ldrb	r0, [r0, #1]	@ zero_extendqisi2
+ 8807 0092 FFF7FEFF 		bl	disk_write
+ 8808              	.LVL1007:
+4505:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_DISK_ERR;
+ 8809              		.loc 1 4505 7 view .LVU2956
+ 8810 0096 20B9     		cbnz	r0, .L644
+4508:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8811              		.loc 1 4508 5 is_stmt 1 view .LVU2957
+4508:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 8812              		.loc 1 4508 14 is_stmt 0 view .LVU2958
+ 8813 0098 237D     		ldrb	r3, [r4, #20]	@ zero_extendqisi2
+ 8814 009a 03F07F03 		and	r3, r3, #127
+ 8815 009e 2375     		strb	r3, [r4, #20]
+ 8816 00a0 D3E7     		b	.L639
+ 8817              	.L644:
+4506:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 8818              		.loc 1 4506 9 view .LVU2959
+ 8819 00a2 0125     		movs	r5, #1
+ 8820              	.LVL1008:
+ 8821              	.L640:
+4512:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 8822              		.loc 1 4512 21 is_stmt 1 discriminator 1 view .LVU2960
+ 8823 00a4 6575     		strb	r5, [r4, #21]
+4512:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 8824              		.loc 1 4512 21 discriminator 1 view .LVU2961
+ 8825 00a6 D1E7     		b	.L635
+ 8826              	.LVL1009:
+ARM GAS  /tmp/cc5lWXRL.s 			page 305
+
+
+ 8827              	.L641:
+4486:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8828              		.loc 1 4486 30 is_stmt 0 view .LVU2962
+ 8829 00a8 0725     		movs	r5, #7
+ 8830              	.LVL1010:
+4486:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8831              		.loc 1 4486 30 view .LVU2963
+ 8832 00aa CFE7     		b	.L635
+ 8833              		.cfi_endproc
+ 8834              	.LFE1233:
+ 8836              		.section	.text.f_unlink,"ax",%progbits
+ 8837              		.align	1
+ 8838              		.global	f_unlink
+ 8839              		.syntax unified
+ 8840              		.thumb
+ 8841              		.thumb_func
+ 8842              		.fpu fpv5-d16
+ 8844              	f_unlink:
+ 8845              	.LVL1011:
+ 8846              	.LFB1234:
+4528:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8847              		.loc 1 4528 1 is_stmt 1 view -0
+ 8848              		.cfi_startproc
+ 8849              		@ args = 0, pretend = 0, frame = 112
+ 8850              		@ frame_needed = 0, uses_anonymous_args = 0
+4528:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 8851              		.loc 1 4528 1 is_stmt 0 view .LVU2965
+ 8852 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 8853              	.LCFI99:
+ 8854              		.cfi_def_cfa_offset 20
+ 8855              		.cfi_offset 4, -20
+ 8856              		.cfi_offset 5, -16
+ 8857              		.cfi_offset 6, -12
+ 8858              		.cfi_offset 7, -8
+ 8859              		.cfi_offset 14, -4
+ 8860 0002 9DB0     		sub	sp, sp, #116
+ 8861              	.LCFI100:
+ 8862              		.cfi_def_cfa_offset 136
+ 8863 0004 0190     		str	r0, [sp, #4]
+4529:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj, sdj;
+ 8864              		.loc 1 4529 2 is_stmt 1 view .LVU2966
+4530:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD dclst = 0;
+ 8865              		.loc 1 4530 2 view .LVU2967
+4531:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 8866              		.loc 1 4531 2 view .LVU2968
+ 8867              	.LVL1012:
+4532:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 8868              		.loc 1 4532 2 view .LVU2969
+4540:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.fs = fs;
+ 8869              		.loc 1 4540 2 view .LVU2970
+4540:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.fs = fs;
+ 8870              		.loc 1 4540 8 is_stmt 0 view .LVU2971
+ 8871 0006 0222     		movs	r2, #2
+ 8872 0008 03A9     		add	r1, sp, #12
+ 8873 000a 01A8     		add	r0, sp, #4
+ 8874              	.LVL1013:
+4540:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.fs = fs;
+ARM GAS  /tmp/cc5lWXRL.s 			page 306
+
+
+ 8875              		.loc 1 4540 8 view .LVU2972
+ 8876 000c FFF7FEFF 		bl	find_volume
+ 8877              	.LVL1014:
+4541:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8878              		.loc 1 4541 2 is_stmt 1 view .LVU2973
+4541:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 8879              		.loc 1 4541 12 is_stmt 0 view .LVU2974
+ 8880 0010 039B     		ldr	r3, [sp, #12]
+ 8881 0012 1093     		str	r3, [sp, #64]
+4542:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+ 8882              		.loc 1 4542 2 is_stmt 1 view .LVU2975
+4542:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+ 8883              		.loc 1 4542 5 is_stmt 0 view .LVU2976
+ 8884 0014 0446     		mov	r4, r0
+ 8885 0016 10B1     		cbz	r0, .L658
+ 8886              	.LVL1015:
+ 8887              	.L649:
+4607:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 8888              		.loc 1 4607 16 is_stmt 1 view .LVU2977
+4610:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 8889              		.loc 1 4610 2 view .LVU2978
+4611:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 8890              		.loc 1 4611 1 is_stmt 0 view .LVU2979
+ 8891 0018 2046     		mov	r0, r4
+ 8892 001a 1DB0     		add	sp, sp, #116
+ 8893              	.LCFI101:
+ 8894              		.cfi_remember_state
+ 8895              		.cfi_def_cfa_offset 20
+ 8896              		@ sp needed
+ 8897 001c F0BD     		pop	{r4, r5, r6, r7, pc}
+ 8898              	.LVL1016:
+ 8899              	.L658:
+ 8900              	.LCFI102:
+ 8901              		.cfi_restore_state
+4543:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&dj, path);		/* Follow the file path */
+ 8902              		.loc 1 4543 18 is_stmt 1 view .LVU2980
+4544:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) {
+ 8903              		.loc 1 4544 3 view .LVU2981
+4544:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) {
+ 8904              		.loc 1 4544 9 is_stmt 0 view .LVU2982
+ 8905 001e 0199     		ldr	r1, [sp, #4]
+ 8906 0020 10A8     		add	r0, sp, #64
+ 8907              	.LVL1017:
+4544:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) {
+ 8908              		.loc 1 4544 9 view .LVU2983
+ 8909 0022 FFF7FEFF 		bl	follow_path
+ 8910              	.LVL1018:
+4545:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_INVALID_NAME;			/* Cannot remove dot entry */
+ 8911              		.loc 1 4545 3 is_stmt 1 view .LVU2984
+4549:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 8912              		.loc 1 4549 3 view .LVU2985
+4549:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 8913              		.loc 1 4549 6 is_stmt 0 view .LVU2986
+ 8914 0026 0446     		mov	r4, r0
+ 8915 0028 20B9     		cbnz	r0, .L650
+4549:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 8916              		.loc 1 4549 21 is_stmt 1 discriminator 1 view .LVU2987
+ARM GAS  /tmp/cc5lWXRL.s 			page 307
+
+
+4549:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 8917              		.loc 1 4549 27 is_stmt 0 discriminator 1 view .LVU2988
+ 8918 002a 0221     		movs	r1, #2
+ 8919 002c 10A8     		add	r0, sp, #64
+ 8920              	.LVL1019:
+4549:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 8921              		.loc 1 4549 27 discriminator 1 view .LVU2989
+ 8922 002e FFF7FEFF 		bl	chk_lock
+ 8923              	.LVL1020:
+ 8924 0032 0446     		mov	r4, r0
+ 8925              	.LVL1021:
+ 8926              	.L650:
+4551:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dj.fn[NSFLAG] & NS_NONAME) {
+ 8927              		.loc 1 4551 3 is_stmt 1 view .LVU2990
+4551:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dj.fn[NSFLAG] & NS_NONAME) {
+ 8928              		.loc 1 4551 6 is_stmt 0 view .LVU2991
+ 8929 0034 002C     		cmp	r4, #0
+ 8930 0036 EFD1     		bne	.L649
+4552:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;		/* Cannot remove the origin directory */
+ 8931              		.loc 1 4552 4 is_stmt 1 view .LVU2992
+4552:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;		/* Cannot remove the origin directory */
+ 8932              		.loc 1 4552 8 is_stmt 0 view .LVU2993
+ 8933 0038 9DF96F30 		ldrsb	r3, [sp, #111]
+4552:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = FR_INVALID_NAME;		/* Cannot remove the origin directory */
+ 8934              		.loc 1 4552 7 view .LVU2994
+ 8935 003c 002B     		cmp	r3, #0
+ 8936 003e 1EDB     		blt	.L654
+4555:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_DENIED;		/* Cannot remove R/O object */
+ 8937              		.loc 1 4555 5 is_stmt 1 view .LVU2995
+4555:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_DENIED;		/* Cannot remove R/O object */
+ 8938              		.loc 1 4555 15 is_stmt 0 view .LVU2996
+ 8939 0040 9DF84660 		ldrb	r6, [sp, #70]	@ zero_extendqisi2
+4555:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = FR_DENIED;		/* Cannot remove R/O object */
+ 8940              		.loc 1 4555 8 view .LVU2997
+ 8941 0044 16F0010F 		tst	r6, #1
+ 8942 0048 2FD1     		bne	.L655
+4559:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 8943              		.loc 1 4559 4 is_stmt 1 view .LVU2998
+4569:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 8944              		.loc 1 4569 6 view .LVU2999
+4569:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 8945              		.loc 1 4569 14 is_stmt 0 view .LVU3000
+ 8946 004a 039F     		ldr	r7, [sp, #12]
+ 8947 004c 1899     		ldr	r1, [sp, #96]
+ 8948 004e 3846     		mov	r0, r7
+ 8949 0050 FFF7FEFF 		bl	ld_clust
+ 8950              	.LVL1022:
+ 8951 0054 0546     		mov	r5, r0
+ 8952              	.LVL1023:
+4571:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0
+ 8953              		.loc 1 4571 5 is_stmt 1 view .LVU3001
+4571:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0
+ 8954              		.loc 1 4571 8 is_stmt 0 view .LVU3002
+ 8955 0056 16F0100F 		tst	r6, #16
+ 8956 005a 12D0     		beq	.L651
+4578:Middlewares/Third_Party/FatFs/src/ff.c **** 						sdj.obj.sclust = dclst;
+ 8957              		.loc 1 4578 7 is_stmt 1 view .LVU3003
+ARM GAS  /tmp/cc5lWXRL.s 			page 308
+
+
+4578:Middlewares/Third_Party/FatFs/src/ff.c **** 						sdj.obj.sclust = dclst;
+ 8958              		.loc 1 4578 18 is_stmt 0 view .LVU3004
+ 8959 005c 0497     		str	r7, [sp, #16]
+4579:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 8960              		.loc 1 4579 7 is_stmt 1 view .LVU3005
+4579:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 8961              		.loc 1 4579 22 is_stmt 0 view .LVU3006
+ 8962 005e 0690     		str	r0, [sp, #24]
+4586:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (res == FR_OK) {
+ 8963              		.loc 1 4586 7 is_stmt 1 view .LVU3007
+4586:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (res == FR_OK) {
+ 8964              		.loc 1 4586 13 is_stmt 0 view .LVU3008
+ 8965 0060 0021     		movs	r1, #0
+ 8966 0062 04A8     		add	r0, sp, #16
+ 8967              	.LVL1024:
+4586:Middlewares/Third_Party/FatFs/src/ff.c **** 						if (res == FR_OK) {
+ 8968              		.loc 1 4586 13 view .LVU3009
+ 8969 0064 FFF7FEFF 		bl	dir_sdi
+ 8970              	.LVL1025:
+4587:Middlewares/Third_Party/FatFs/src/ff.c **** 							res = dir_read(&sdj, 0);			/* Read an item */
+ 8971              		.loc 1 4587 7 is_stmt 1 view .LVU3010
+4587:Middlewares/Third_Party/FatFs/src/ff.c **** 							res = dir_read(&sdj, 0);			/* Read an item */
+ 8972              		.loc 1 4587 10 is_stmt 0 view .LVU3011
+ 8973 0068 0446     		mov	r4, r0
+ 8974 006a 50B9     		cbnz	r0, .L651
+4588:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res == FR_OK) res = FR_DENIED;	/* Not empty? */
+ 8975              		.loc 1 4588 8 is_stmt 1 view .LVU3012
+4588:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res == FR_OK) res = FR_DENIED;	/* Not empty? */
+ 8976              		.loc 1 4588 14 is_stmt 0 view .LVU3013
+ 8977 006c 0021     		movs	r1, #0
+ 8978 006e 04A8     		add	r0, sp, #16
+ 8979              	.LVL1026:
+4588:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res == FR_OK) res = FR_DENIED;	/* Not empty? */
+ 8980              		.loc 1 4588 14 view .LVU3014
+ 8981 0070 FFF7FEFF 		bl	dir_read
+ 8982              	.LVL1027:
+4589:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res == FR_NO_FILE) res = FR_OK;	/* Empty? */
+ 8983              		.loc 1 4589 8 is_stmt 1 view .LVU3015
+4589:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res == FR_NO_FILE) res = FR_OK;	/* Empty? */
+ 8984              		.loc 1 4589 11 is_stmt 0 view .LVU3016
+ 8985 0074 0446     		mov	r4, r0
+ 8986 0076 D8B1     		cbz	r0, .L656
+4590:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 8987              		.loc 1 4590 8 is_stmt 1 view .LVU3017
+4590:Middlewares/Third_Party/FatFs/src/ff.c **** 						}
+ 8988              		.loc 1 4590 11 is_stmt 0 view .LVU3018
+ 8989 0078 0428     		cmp	r0, #4
+ 8990 007a 02D1     		bne	.L651
+ 8991 007c 03E0     		b	.L652
+ 8992              	.LVL1028:
+ 8993              	.L654:
+4531:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 8994              		.loc 1 4531 8 view .LVU3019
+ 8995 007e 0025     		movs	r5, #0
+4553:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 8996              		.loc 1 4553 9 view .LVU3020
+ 8997 0080 0624     		movs	r4, #6
+ARM GAS  /tmp/cc5lWXRL.s 			page 309
+
+
+ 8998              	.LVL1029:
+ 8999              	.L651:
+4595:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_remove(&dj);			/* Remove the directory entry */
+ 9000              		.loc 1 4595 4 is_stmt 1 view .LVU3021
+4595:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_remove(&dj);			/* Remove the directory entry */
+ 9001              		.loc 1 4595 7 is_stmt 0 view .LVU3022
+ 9002 0082 002C     		cmp	r4, #0
+ 9003 0084 C8D1     		bne	.L649
+ 9004              	.LVL1030:
+ 9005              	.L652:
+4596:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK && dclst) {	/* Remove the cluster chain if exist */
+ 9006              		.loc 1 4596 5 is_stmt 1 view .LVU3023
+4596:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK && dclst) {	/* Remove the cluster chain if exist */
+ 9007              		.loc 1 4596 11 is_stmt 0 view .LVU3024
+ 9008 0086 10A8     		add	r0, sp, #64
+ 9009 0088 FFF7FEFF 		bl	dir_remove
+ 9010              	.LVL1031:
+4597:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 9011              		.loc 1 4597 5 is_stmt 1 view .LVU3025
+4597:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 9012              		.loc 1 4597 13 is_stmt 0 view .LVU3026
+ 9013 008c 0446     		mov	r4, r0
+4597:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 9014              		.loc 1 4597 22 view .LVU3027
+ 9015 008e B0FA80F0 		clz	r0, r0
+ 9016              	.LVL1032:
+4597:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 9017              		.loc 1 4597 22 view .LVU3028
+ 9018 0092 4009     		lsrs	r0, r0, #5
+ 9019 0094 002D     		cmp	r5, #0
+ 9020 0096 08BF     		it	eq
+ 9021 0098 0020     		moveq	r0, #0
+4597:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 9022              		.loc 1 4597 8 view .LVU3029
+ 9023 009a 58B9     		cbnz	r0, .L659
+ 9024              	.L653:
+ 9025              	.LVL1033:
+4604:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 9026              		.loc 1 4604 5 is_stmt 1 view .LVU3030
+4604:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 9027              		.loc 1 4604 8 is_stmt 0 view .LVU3031
+ 9028 009c 002C     		cmp	r4, #0
+ 9029 009e BBD1     		bne	.L649
+4604:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 9030              		.loc 1 4604 23 is_stmt 1 discriminator 1 view .LVU3032
+4604:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 9031              		.loc 1 4604 29 is_stmt 0 discriminator 1 view .LVU3033
+ 9032 00a0 0398     		ldr	r0, [sp, #12]
+ 9033 00a2 FFF7FEFF 		bl	sync_fs
+ 9034              	.LVL1034:
+ 9035 00a6 0446     		mov	r4, r0
+ 9036              	.LVL1035:
+4604:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 9037              		.loc 1 4604 29 discriminator 1 view .LVU3034
+ 9038 00a8 B6E7     		b	.L649
+ 9039              	.LVL1036:
+ 9040              	.L655:
+ARM GAS  /tmp/cc5lWXRL.s 			page 310
+
+
+4531:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 9041              		.loc 1 4531 8 view .LVU3035
+ 9042 00aa 0025     		movs	r5, #0
+4556:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9043              		.loc 1 4556 10 view .LVU3036
+ 9044 00ac 0724     		movs	r4, #7
+ 9045              	.LVL1037:
+4556:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9046              		.loc 1 4556 10 view .LVU3037
+ 9047 00ae E8E7     		b	.L651
+ 9048              	.LVL1038:
+ 9049              	.L656:
+4589:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (res == FR_NO_FILE) res = FR_OK;	/* Empty? */
+ 9050              		.loc 1 4589 30 view .LVU3038
+ 9051 00b0 0724     		movs	r4, #7
+ 9052 00b2 E6E7     		b	.L651
+ 9053              	.LVL1039:
+ 9054              	.L659:
+4601:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 9055              		.loc 1 4601 6 is_stmt 1 view .LVU3039
+4601:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 9056              		.loc 1 4601 12 is_stmt 0 view .LVU3040
+ 9057 00b4 0022     		movs	r2, #0
+ 9058 00b6 2946     		mov	r1, r5
+ 9059 00b8 10A8     		add	r0, sp, #64
+ 9060 00ba FFF7FEFF 		bl	remove_chain
+ 9061              	.LVL1040:
+ 9062 00be 0446     		mov	r4, r0
+ 9063              	.LVL1041:
+4601:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 9064              		.loc 1 4601 12 view .LVU3041
+ 9065 00c0 ECE7     		b	.L653
+ 9066              		.cfi_endproc
+ 9067              	.LFE1234:
+ 9069              		.section	.text.f_mkdir,"ax",%progbits
+ 9070              		.align	1
+ 9071              		.global	f_mkdir
+ 9072              		.syntax unified
+ 9073              		.thumb
+ 9074              		.thumb_func
+ 9075              		.fpu fpv5-d16
+ 9077              	f_mkdir:
+ 9078              	.LVL1042:
+ 9079              	.LFB1235:
+4623:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 9080              		.loc 1 4623 1 is_stmt 1 view -0
+ 9081              		.cfi_startproc
+ 9082              		@ args = 0, pretend = 0, frame = 64
+ 9083              		@ frame_needed = 0, uses_anonymous_args = 0
+4623:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 9084              		.loc 1 4623 1 is_stmt 0 view .LVU3043
+ 9085 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 9086              	.LCFI103:
+ 9087              		.cfi_def_cfa_offset 36
+ 9088              		.cfi_offset 4, -36
+ 9089              		.cfi_offset 5, -32
+ 9090              		.cfi_offset 6, -28
+ARM GAS  /tmp/cc5lWXRL.s 			page 311
+
+
+ 9091              		.cfi_offset 7, -24
+ 9092              		.cfi_offset 8, -20
+ 9093              		.cfi_offset 9, -16
+ 9094              		.cfi_offset 10, -12
+ 9095              		.cfi_offset 11, -8
+ 9096              		.cfi_offset 14, -4
+ 9097 0004 91B0     		sub	sp, sp, #68
+ 9098              	.LCFI104:
+ 9099              		.cfi_def_cfa_offset 104
+ 9100 0006 0190     		str	r0, [sp, #4]
+4624:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR dj;
+ 9101              		.loc 1 4624 2 is_stmt 1 view .LVU3044
+4625:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 9102              		.loc 1 4625 2 view .LVU3045
+4626:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE *dir;
+ 9103              		.loc 1 4626 2 view .LVU3046
+4627:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT n;
+ 9104              		.loc 1 4627 2 view .LVU3047
+4628:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD dsc, dcl, pcl, tm;
+ 9105              		.loc 1 4628 2 view .LVU3048
+4629:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+ 9106              		.loc 1 4629 2 view .LVU3049
+4634:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.fs = fs;
+ 9107              		.loc 1 4634 2 view .LVU3050
+4634:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.fs = fs;
+ 9108              		.loc 1 4634 8 is_stmt 0 view .LVU3051
+ 9109 0008 0222     		movs	r2, #2
+ 9110 000a 03A9     		add	r1, sp, #12
+ 9111 000c 01A8     		add	r0, sp, #4
+ 9112              	.LVL1043:
+4634:Middlewares/Third_Party/FatFs/src/ff.c **** 	dj.obj.fs = fs;
+ 9113              		.loc 1 4634 8 view .LVU3052
+ 9114 000e FFF7FEFF 		bl	find_volume
+ 9115              	.LVL1044:
+4635:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 9116              		.loc 1 4635 2 is_stmt 1 view .LVU3053
+4635:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 9117              		.loc 1 4635 12 is_stmt 0 view .LVU3054
+ 9118 0012 039B     		ldr	r3, [sp, #12]
+ 9119 0014 0493     		str	r3, [sp, #16]
+4636:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+ 9120              		.loc 1 4636 2 is_stmt 1 view .LVU3055
+4636:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+ 9121              		.loc 1 4636 5 is_stmt 0 view .LVU3056
+ 9122 0016 0446     		mov	r4, r0
+ 9123 0018 18B1     		cbz	r0, .L678
+ 9124              	.LVL1045:
+ 9125              	.L661:
+4704:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 9126              		.loc 1 4704 16 is_stmt 1 view .LVU3057
+4707:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 9127              		.loc 1 4707 2 view .LVU3058
+4708:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 9128              		.loc 1 4708 1 is_stmt 0 view .LVU3059
+ 9129 001a 2046     		mov	r0, r4
+ 9130 001c 11B0     		add	sp, sp, #68
+ 9131              	.LCFI105:
+ARM GAS  /tmp/cc5lWXRL.s 			page 312
+
+
+ 9132              		.cfi_remember_state
+ 9133              		.cfi_def_cfa_offset 36
+ 9134              		@ sp needed
+ 9135 001e BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 9136              	.LVL1046:
+ 9137              	.L678:
+ 9138              	.LCFI106:
+ 9139              		.cfi_restore_state
+4637:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&dj, path);			/* Follow the file path */
+ 9140              		.loc 1 4637 18 is_stmt 1 view .LVU3060
+4638:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
+ 9141              		.loc 1 4638 3 view .LVU3061
+4638:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
+ 9142              		.loc 1 4638 9 is_stmt 0 view .LVU3062
+ 9143 0022 0199     		ldr	r1, [sp, #4]
+ 9144 0024 04A8     		add	r0, sp, #16
+ 9145              	.LVL1047:
+4638:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
+ 9146              		.loc 1 4638 9 view .LVU3063
+ 9147 0026 FFF7FEFF 		bl	follow_path
+ 9148              	.LVL1048:
+4639:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) {
+ 9149              		.loc 1 4639 3 is_stmt 1 view .LVU3064
+4639:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) {
+ 9150              		.loc 1 4639 6 is_stmt 0 view .LVU3065
+ 9151 002a 0028     		cmp	r0, #0
+ 9152 002c 00F09A80 		beq	.L671
+4640:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_INVALID_NAME;
+ 9153              		.loc 1 4640 3 is_stmt 1 view .LVU3066
+4643:Middlewares/Third_Party/FatFs/src/ff.c **** 			dcl = create_chain(&dj.obj, 0);		/* Allocate a cluster for the new directory table */
+ 9154              		.loc 1 4643 3 view .LVU3067
+4643:Middlewares/Third_Party/FatFs/src/ff.c **** 			dcl = create_chain(&dj.obj, 0);		/* Allocate a cluster for the new directory table */
+ 9155              		.loc 1 4643 6 is_stmt 0 view .LVU3068
+ 9156 0030 0428     		cmp	r0, #4
+ 9157 0032 01D0     		beq	.L679
+4638:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
+ 9158              		.loc 1 4638 9 view .LVU3069
+ 9159 0034 0446     		mov	r4, r0
+ 9160 0036 F0E7     		b	.L661
+ 9161              	.L679:
+4644:Middlewares/Third_Party/FatFs/src/ff.c **** 			dj.obj.objsize = (DWORD)fs->csize * SS(fs);
+ 9162              		.loc 1 4644 4 is_stmt 1 view .LVU3070
+4644:Middlewares/Third_Party/FatFs/src/ff.c **** 			dj.obj.objsize = (DWORD)fs->csize * SS(fs);
+ 9163              		.loc 1 4644 10 is_stmt 0 view .LVU3071
+ 9164 0038 0021     		movs	r1, #0
+ 9165 003a 04A8     		add	r0, sp, #16
+ 9166              	.LVL1049:
+4644:Middlewares/Third_Party/FatFs/src/ff.c **** 			dj.obj.objsize = (DWORD)fs->csize * SS(fs);
+ 9167              		.loc 1 4644 10 view .LVU3072
+ 9168 003c FFF7FEFF 		bl	create_chain
+ 9169              	.LVL1050:
+4645:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+ 9170              		.loc 1 4645 4 is_stmt 1 view .LVU3073
+4645:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+ 9171              		.loc 1 4645 30 is_stmt 0 view .LVU3074
+ 9172 0040 039A     		ldr	r2, [sp, #12]
+ 9173 0042 5389     		ldrh	r3, [r2, #10]
+ARM GAS  /tmp/cc5lWXRL.s 			page 313
+
+
+4645:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+ 9174              		.loc 1 4645 40 view .LVU3075
+ 9175 0044 9189     		ldrh	r1, [r2, #12]
+4645:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+ 9176              		.loc 1 4645 38 view .LVU3076
+ 9177 0046 01FB03F3 		mul	r3, r1, r3
+4645:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = FR_OK;
+ 9178              		.loc 1 4645 19 view .LVU3077
+ 9179 004a 0793     		str	r3, [sp, #28]
+4646:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dcl == 0) res = FR_DENIED;		/* No space to allocate a new cluster */
+ 9180              		.loc 1 4646 4 is_stmt 1 view .LVU3078
+ 9181              	.LVL1051:
+4647:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dcl == 1) res = FR_INT_ERR;
+ 9182              		.loc 1 4647 4 view .LVU3079
+4647:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dcl == 1) res = FR_INT_ERR;
+ 9183              		.loc 1 4647 7 is_stmt 0 view .LVU3080
+ 9184 004c 8046     		mov	r8, r0
+ 9185 004e 00B9     		cbnz	r0, .L662
+4647:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dcl == 1) res = FR_INT_ERR;
+ 9186              		.loc 1 4647 22 view .LVU3081
+ 9187 0050 0724     		movs	r4, #7
+ 9188              	.L662:
+ 9189              	.LVL1052:
+4648:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ 9190              		.loc 1 4648 4 is_stmt 1 view .LVU3082
+4648:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ 9191              		.loc 1 4648 7 is_stmt 0 view .LVU3083
+ 9192 0052 B8F1010F 		cmp	r8, #1
+ 9193 0056 20D0     		beq	.L680
+ 9194              	.LVL1053:
+ 9195              	.L663:
+4649:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) res = sync_window(fs);	/* Flush FAT */
+ 9196              		.loc 1 4649 4 is_stmt 1 view .LVU3084
+4649:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) res = sync_window(fs);	/* Flush FAT */
+ 9197              		.loc 1 4649 7 is_stmt 0 view .LVU3085
+ 9198 0058 B8F1FF3F 		cmp	r8, #-1
+ 9199 005c 24D0     		beq	.L675
+4650:Middlewares/Third_Party/FatFs/src/ff.c **** 			tm = GET_FATTIME();
+ 9200              		.loc 1 4650 4 is_stmt 1 view .LVU3086
+4650:Middlewares/Third_Party/FatFs/src/ff.c **** 			tm = GET_FATTIME();
+ 9201              		.loc 1 4650 7 is_stmt 0 view .LVU3087
+ 9202 005e F4B1     		cbz	r4, .L681
+ 9203              	.LVL1054:
+ 9204              	.L664:
+4651:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {					/* Initialize the new directory table */
+ 9205              		.loc 1 4651 4 is_stmt 1 view .LVU3088
+4651:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) {					/* Initialize the new directory table */
+ 9206              		.loc 1 4651 9 is_stmt 0 view .LVU3089
+ 9207 0060 FFF7FEFF 		bl	get_fattime
+ 9208              	.LVL1055:
+ 9209 0064 8246     		mov	r10, r0
+ 9210              	.LVL1056:
+4652:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc = clust2sect(fs, dcl);
+ 9211              		.loc 1 4652 4 is_stmt 1 view .LVU3090
+4652:Middlewares/Third_Party/FatFs/src/ff.c **** 				dsc = clust2sect(fs, dcl);
+ 9212              		.loc 1 4652 7 is_stmt 0 view .LVU3091
+ 9213 0066 0CB3     		cbz	r4, .L682
+ARM GAS  /tmp/cc5lWXRL.s 			page 314
+
+
+ 9214              	.LVL1057:
+ 9215              	.L665:
+4675:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_register(&dj);	/* Register the object to the directoy */
+ 9216              		.loc 1 4675 4 is_stmt 1 view .LVU3092
+4675:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_register(&dj);	/* Register the object to the directoy */
+ 9217              		.loc 1 4675 7 is_stmt 0 view .LVU3093
+ 9218 0068 002C     		cmp	r4, #0
+ 9219 006a 70D0     		beq	.L683
+ 9220              	.L669:
+4678:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 9221              		.loc 1 4678 4 is_stmt 1 view .LVU3094
+4678:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 9222              		.loc 1 4678 7 is_stmt 0 view .LVU3095
+ 9223 006c 002C     		cmp	r4, #0
+ 9224 006e 73D1     		bne	.L670
+4691:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dir + DIR_ModTime, tm);	/* Created time */
+ 9225              		.loc 1 4691 6 is_stmt 1 view .LVU3096
+4691:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dir + DIR_ModTime, tm);	/* Created time */
+ 9226              		.loc 1 4691 10 is_stmt 0 view .LVU3097
+ 9227 0070 0C9C     		ldr	r4, [sp, #48]
+ 9228              	.LVL1058:
+4692:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir, dcl);				/* Table start cluster */
+ 9229              		.loc 1 4692 6 is_stmt 1 view .LVU3098
+ 9230 0072 5146     		mov	r1, r10
+ 9231 0074 04F11600 		add	r0, r4, #22
+ 9232 0078 FFF7FEFF 		bl	st_dword
+ 9233              	.LVL1059:
+4693:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[DIR_Attr] = AM_DIR;				/* Attribute */
+ 9234              		.loc 1 4693 6 view .LVU3099
+ 9235 007c 4246     		mov	r2, r8
+ 9236 007e 2146     		mov	r1, r4
+ 9237 0080 0398     		ldr	r0, [sp, #12]
+ 9238 0082 FFF7FEFF 		bl	st_clust
+ 9239              	.LVL1060:
+4694:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+ 9240              		.loc 1 4694 6 view .LVU3100
+4694:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+ 9241              		.loc 1 4694 20 is_stmt 0 view .LVU3101
+ 9242 0086 1023     		movs	r3, #16
+ 9243 0088 E372     		strb	r3, [r4, #11]
+4695:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9244              		.loc 1 4695 6 is_stmt 1 view .LVU3102
+4695:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9245              		.loc 1 4695 16 is_stmt 0 view .LVU3103
+ 9246 008a 039B     		ldr	r3, [sp, #12]
+ 9247 008c 0122     		movs	r2, #1
+ 9248 008e DA70     		strb	r2, [r3, #3]
+4697:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = sync_fs(fs);
+ 9249              		.loc 1 4697 5 is_stmt 1 view .LVU3104
+4698:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9250              		.loc 1 4698 6 view .LVU3105
+4698:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9251              		.loc 1 4698 12 is_stmt 0 view .LVU3106
+ 9252 0090 0398     		ldr	r0, [sp, #12]
+ 9253 0092 FFF7FEFF 		bl	sync_fs
+ 9254              	.LVL1061:
+ 9255 0096 0446     		mov	r4, r0
+ARM GAS  /tmp/cc5lWXRL.s 			page 315
+
+
+ 9256              	.LVL1062:
+4698:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9257              		.loc 1 4698 12 view .LVU3107
+ 9258 0098 BFE7     		b	.L661
+ 9259              	.LVL1063:
+ 9260              	.L680:
+4648:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ 9261              		.loc 1 4648 22 view .LVU3108
+ 9262 009a 0224     		movs	r4, #2
+ 9263              	.LVL1064:
+4648:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ 9264              		.loc 1 4648 22 view .LVU3109
+ 9265 009c DCE7     		b	.L663
+ 9266              	.LVL1065:
+ 9267              	.L681:
+4650:Middlewares/Third_Party/FatFs/src/ff.c **** 			tm = GET_FATTIME();
+ 9268              		.loc 1 4650 22 is_stmt 1 discriminator 1 view .LVU3110
+4650:Middlewares/Third_Party/FatFs/src/ff.c **** 			tm = GET_FATTIME();
+ 9269              		.loc 1 4650 28 is_stmt 0 discriminator 1 view .LVU3111
+ 9270 009e 1046     		mov	r0, r2
+ 9271              	.LVL1066:
+4650:Middlewares/Third_Party/FatFs/src/ff.c **** 			tm = GET_FATTIME();
+ 9272              		.loc 1 4650 28 discriminator 1 view .LVU3112
+ 9273 00a0 FFF7FEFF 		bl	sync_window
+ 9274              	.LVL1067:
+ 9275 00a4 0446     		mov	r4, r0
+ 9276              	.LVL1068:
+4650:Middlewares/Third_Party/FatFs/src/ff.c **** 			tm = GET_FATTIME();
+ 9277              		.loc 1 4650 28 discriminator 1 view .LVU3113
+ 9278 00a6 DBE7     		b	.L664
+ 9279              	.LVL1069:
+ 9280              	.L675:
+4649:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) res = sync_window(fs);	/* Flush FAT */
+ 9281              		.loc 1 4649 31 view .LVU3114
+ 9282 00a8 0124     		movs	r4, #1
+ 9283              	.LVL1070:
+4649:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (res == FR_OK) res = sync_window(fs);	/* Flush FAT */
+ 9284              		.loc 1 4649 31 view .LVU3115
+ 9285 00aa D9E7     		b	.L664
+ 9286              	.LVL1071:
+ 9287              	.L682:
+4653:Middlewares/Third_Party/FatFs/src/ff.c **** 				dir = fs->win;
+ 9288              		.loc 1 4653 5 is_stmt 1 view .LVU3116
+4653:Middlewares/Third_Party/FatFs/src/ff.c **** 				dir = fs->win;
+ 9289              		.loc 1 4653 11 is_stmt 0 view .LVU3117
+ 9290 00ac 039E     		ldr	r6, [sp, #12]
+ 9291 00ae 4146     		mov	r1, r8
+ 9292 00b0 3046     		mov	r0, r6
+ 9293              	.LVL1072:
+4653:Middlewares/Third_Party/FatFs/src/ff.c **** 				dir = fs->win;
+ 9294              		.loc 1 4653 11 view .LVU3118
+ 9295 00b2 FFF7FEFF 		bl	clust2sect
+ 9296              	.LVL1073:
+ 9297 00b6 0546     		mov	r5, r0
+ 9298              	.LVL1074:
+4654:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_set(dir, 0, SS(fs));
+ 9299              		.loc 1 4654 5 is_stmt 1 view .LVU3119
+ARM GAS  /tmp/cc5lWXRL.s 			page 316
+
+
+4654:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_set(dir, 0, SS(fs));
+ 9300              		.loc 1 4654 9 is_stmt 0 view .LVU3120
+ 9301 00b8 06F13409 		add	r9, r6, #52
+ 9302              	.LVL1075:
+4655:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+ 9303              		.loc 1 4655 5 is_stmt 1 view .LVU3121
+ 9304 00bc B289     		ldrh	r2, [r6, #12]
+ 9305 00be 0021     		movs	r1, #0
+ 9306 00c0 4846     		mov	r0, r9
+ 9307              	.LVL1076:
+4655:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+ 9308              		.loc 1 4655 5 is_stmt 0 view .LVU3122
+ 9309 00c2 FFF7FEFF 		bl	mem_set
+ 9310              	.LVL1077:
+4656:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_set(dir + DIR_Name, ' ', 11);	/* Create "." entry */
+ 9311              		.loc 1 4656 5 is_stmt 1 view .LVU3123
+4657:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[DIR_Name] = '.';
+ 9312              		.loc 1 4657 6 view .LVU3124
+ 9313 00c6 0B22     		movs	r2, #11
+ 9314 00c8 2021     		movs	r1, #32
+ 9315 00ca 4846     		mov	r0, r9
+ 9316 00cc FFF7FEFF 		bl	mem_set
+ 9317              	.LVL1078:
+4658:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[DIR_Attr] = AM_DIR;
+ 9318              		.loc 1 4658 6 view .LVU3125
+4658:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[DIR_Attr] = AM_DIR;
+ 9319              		.loc 1 4658 20 is_stmt 0 view .LVU3126
+ 9320 00d0 4FF02E0B 		mov	fp, #46
+ 9321 00d4 86F834B0 		strb	fp, [r6, #52]
+4659:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dir + DIR_ModTime, tm);
+ 9322              		.loc 1 4659 6 is_stmt 1 view .LVU3127
+4659:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_dword(dir + DIR_ModTime, tm);
+ 9323              		.loc 1 4659 20 is_stmt 0 view .LVU3128
+ 9324 00d8 1023     		movs	r3, #16
+ 9325 00da 86F83F30 		strb	r3, [r6, #63]
+4660:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir, dcl);
+ 9326              		.loc 1 4660 6 is_stmt 1 view .LVU3129
+ 9327 00de 5146     		mov	r1, r10
+ 9328 00e0 06F14A00 		add	r0, r6, #74
+ 9329 00e4 FFF7FEFF 		bl	st_dword
+ 9330              	.LVL1079:
+4661:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_cpy(dir + SZDIRE, dir, SZDIRE); 	/* Create ".." entry */
+ 9331              		.loc 1 4661 6 view .LVU3130
+ 9332 00e8 4246     		mov	r2, r8
+ 9333 00ea 4946     		mov	r1, r9
+ 9334 00ec 0398     		ldr	r0, [sp, #12]
+ 9335 00ee FFF7FEFF 		bl	st_clust
+ 9336              	.LVL1080:
+4662:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust;
+ 9337              		.loc 1 4662 6 view .LVU3131
+4662:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust;
+ 9338              		.loc 1 4662 18 is_stmt 0 view .LVU3132
+ 9339 00f2 06F15407 		add	r7, r6, #84
+4662:Middlewares/Third_Party/FatFs/src/ff.c **** 					dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust;
+ 9340              		.loc 1 4662 6 view .LVU3133
+ 9341 00f6 2022     		movs	r2, #32
+ 9342 00f8 4946     		mov	r1, r9
+ARM GAS  /tmp/cc5lWXRL.s 			page 317
+
+
+ 9343 00fa 3846     		mov	r0, r7
+ 9344 00fc FFF7FEFF 		bl	mem_cpy
+ 9345              	.LVL1081:
+4663:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0;
+ 9346              		.loc 1 4663 6 is_stmt 1 view .LVU3134
+4663:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0;
+ 9347              		.loc 1 4663 22 is_stmt 0 view .LVU3135
+ 9348 0100 86F855B0 		strb	fp, [r6, #85]
+4663:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0;
+ 9349              		.loc 1 4663 29 is_stmt 1 view .LVU3136
+4663:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0;
+ 9350              		.loc 1 4663 33 is_stmt 0 view .LVU3137
+ 9351 0104 069A     		ldr	r2, [sp, #24]
+ 9352              	.LVL1082:
+4664:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir + SZDIRE, pcl);
+ 9353              		.loc 1 4664 6 is_stmt 1 view .LVU3138
+4664:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir + SZDIRE, pcl);
+ 9354              		.loc 1 4664 12 is_stmt 0 view .LVU3139
+ 9355 0106 0398     		ldr	r0, [sp, #12]
+ 9356 0108 0378     		ldrb	r3, [r0]	@ zero_extendqisi2
+4664:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir + SZDIRE, pcl);
+ 9357              		.loc 1 4664 9 view .LVU3140
+ 9358 010a 032B     		cmp	r3, #3
+ 9359 010c 1AD0     		beq	.L684
+ 9360              	.LVL1083:
+ 9361              	.L666:
+4665:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9362              		.loc 1 4665 6 is_stmt 1 view .LVU3141
+ 9363 010e 3946     		mov	r1, r7
+ 9364 0110 FFF7FEFF 		bl	st_clust
+ 9365              	.LVL1084:
+4667:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->winsect = dsc++;
+ 9366              		.loc 1 4667 5 view .LVU3142
+4667:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->winsect = dsc++;
+ 9367              		.loc 1 4667 16 is_stmt 0 view .LVU3143
+ 9368 0114 039B     		ldr	r3, [sp, #12]
+ 9369 0116 5E89     		ldrh	r6, [r3, #10]
+ 9370              	.LVL1085:
+ 9371              	.L667:
+4667:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->winsect = dsc++;
+ 9372              		.loc 1 4667 25 is_stmt 1 discriminator 1 view .LVU3144
+4667:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->winsect = dsc++;
+ 9373              		.loc 1 4667 5 is_stmt 0 discriminator 1 view .LVU3145
+ 9374 0118 002E     		cmp	r6, #0
+ 9375 011a A5D0     		beq	.L665
+4668:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+ 9376              		.loc 1 4668 6 is_stmt 1 view .LVU3146
+4668:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+ 9377              		.loc 1 4668 23 is_stmt 0 view .LVU3147
+ 9378 011c 6F1C     		adds	r7, r5, #1
+ 9379              	.LVL1086:
+4668:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+ 9380              		.loc 1 4668 8 view .LVU3148
+ 9381 011e 039B     		ldr	r3, [sp, #12]
+4668:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+ 9382              		.loc 1 4668 18 view .LVU3149
+ 9383 0120 1D63     		str	r5, [r3, #48]
+ARM GAS  /tmp/cc5lWXRL.s 			page 318
+
+
+4669:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = sync_window(fs);
+ 9384              		.loc 1 4669 6 is_stmt 1 view .LVU3150
+4669:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = sync_window(fs);
+ 9385              		.loc 1 4669 16 is_stmt 0 view .LVU3151
+ 9386 0122 0122     		movs	r2, #1
+ 9387 0124 DA70     		strb	r2, [r3, #3]
+4670:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res != FR_OK) break;
+ 9388              		.loc 1 4670 6 is_stmt 1 view .LVU3152
+4670:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res != FR_OK) break;
+ 9389              		.loc 1 4670 12 is_stmt 0 view .LVU3153
+ 9390 0126 0398     		ldr	r0, [sp, #12]
+ 9391 0128 FFF7FEFF 		bl	sync_window
+ 9392              	.LVL1087:
+4671:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_set(dir, 0, SS(fs));
+ 9393              		.loc 1 4671 6 is_stmt 1 view .LVU3154
+4671:Middlewares/Third_Party/FatFs/src/ff.c **** 					mem_set(dir, 0, SS(fs));
+ 9394              		.loc 1 4671 9 is_stmt 0 view .LVU3155
+ 9395 012c 0446     		mov	r4, r0
+ 9396 012e 0028     		cmp	r0, #0
+ 9397 0130 9AD1     		bne	.L665
+4672:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9398              		.loc 1 4672 6 is_stmt 1 discriminator 2 view .LVU3156
+ 9399 0132 039B     		ldr	r3, [sp, #12]
+ 9400 0134 9A89     		ldrh	r2, [r3, #12]
+ 9401 0136 0021     		movs	r1, #0
+ 9402 0138 4846     		mov	r0, r9
+ 9403              	.LVL1088:
+4672:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9404              		.loc 1 4672 6 is_stmt 0 discriminator 2 view .LVU3157
+ 9405 013a FFF7FEFF 		bl	mem_set
+ 9406              	.LVL1089:
+4667:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->winsect = dsc++;
+ 9407              		.loc 1 4667 28 is_stmt 1 discriminator 2 view .LVU3158
+4667:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->winsect = dsc++;
+ 9408              		.loc 1 4667 29 is_stmt 0 discriminator 2 view .LVU3159
+ 9409 013e 013E     		subs	r6, r6, #1
+ 9410              	.LVL1090:
+4668:Middlewares/Third_Party/FatFs/src/ff.c **** 					fs->wflag = 1;
+ 9411              		.loc 1 4668 23 discriminator 2 view .LVU3160
+ 9412 0140 3D46     		mov	r5, r7
+ 9413 0142 E9E7     		b	.L667
+ 9414              	.LVL1091:
+ 9415              	.L684:
+4664:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir + SZDIRE, pcl);
+ 9416              		.loc 1 4664 46 discriminator 1 view .LVU3161
+ 9417 0144 836A     		ldr	r3, [r0, #40]
+4664:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir + SZDIRE, pcl);
+ 9418              		.loc 1 4664 34 discriminator 1 view .LVU3162
+ 9419 0146 9342     		cmp	r3, r2
+ 9420 0148 E1D1     		bne	.L666
+4664:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir + SZDIRE, pcl);
+ 9421              		.loc 1 4664 61 view .LVU3163
+ 9422 014a 0022     		movs	r2, #0
+ 9423              	.LVL1092:
+4664:Middlewares/Third_Party/FatFs/src/ff.c **** 					st_clust(fs, dir + SZDIRE, pcl);
+ 9424              		.loc 1 4664 61 view .LVU3164
+ 9425 014c DFE7     		b	.L666
+ARM GAS  /tmp/cc5lWXRL.s 			page 319
+
+
+ 9426              	.LVL1093:
+ 9427              	.L683:
+4676:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 9428              		.loc 1 4676 5 is_stmt 1 view .LVU3165
+4676:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 9429              		.loc 1 4676 11 is_stmt 0 view .LVU3166
+ 9430 014e 04A8     		add	r0, sp, #16
+ 9431 0150 FFF7FEFF 		bl	dir_register
+ 9432              	.LVL1094:
+ 9433 0154 0446     		mov	r4, r0
+ 9434              	.LVL1095:
+4676:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 9435              		.loc 1 4676 11 view .LVU3167
+ 9436 0156 89E7     		b	.L669
+ 9437              	.L670:
+4701:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 9438              		.loc 1 4701 5 is_stmt 1 view .LVU3168
+ 9439 0158 0022     		movs	r2, #0
+ 9440 015a 4146     		mov	r1, r8
+ 9441 015c 04A8     		add	r0, sp, #16
+ 9442 015e FFF7FEFF 		bl	remove_chain
+ 9443              	.LVL1096:
+ 9444 0162 5AE7     		b	.L661
+ 9445              	.LVL1097:
+ 9446              	.L671:
+4639:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) {
+ 9447              		.loc 1 4639 25 is_stmt 0 view .LVU3169
+ 9448 0164 0824     		movs	r4, #8
+ 9449 0166 58E7     		b	.L661
+ 9450              		.cfi_endproc
+ 9451              	.LFE1235:
+ 9453              		.section	.text.f_rename,"ax",%progbits
+ 9454              		.align	1
+ 9455              		.global	f_rename
+ 9456              		.syntax unified
+ 9457              		.thumb
+ 9458              		.thumb_func
+ 9459              		.fpu fpv5-d16
+ 9461              	f_rename:
+ 9462              	.LVL1098:
+ 9463              	.LFB1236:
+4721:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 9464              		.loc 1 4721 1 is_stmt 1 view -0
+ 9465              		.cfi_startproc
+ 9466              		@ args = 0, pretend = 0, frame = 136
+ 9467              		@ frame_needed = 0, uses_anonymous_args = 0
+4721:Middlewares/Third_Party/FatFs/src/ff.c **** 	FRESULT res;
+ 9468              		.loc 1 4721 1 is_stmt 0 view .LVU3171
+ 9469 0000 30B5     		push	{r4, r5, lr}
+ 9470              	.LCFI107:
+ 9471              		.cfi_def_cfa_offset 12
+ 9472              		.cfi_offset 4, -12
+ 9473              		.cfi_offset 5, -8
+ 9474              		.cfi_offset 14, -4
+ 9475 0002 A3B0     		sub	sp, sp, #140
+ 9476              	.LCFI108:
+ 9477              		.cfi_def_cfa_offset 152
+ARM GAS  /tmp/cc5lWXRL.s 			page 320
+
+
+ 9478 0004 0190     		str	r0, [sp, #4]
+ 9479 0006 0091     		str	r1, [sp]
+4722:Middlewares/Third_Party/FatFs/src/ff.c **** 	DIR djo, djn;
+ 9480              		.loc 1 4722 2 is_stmt 1 view .LVU3172
+4723:Middlewares/Third_Party/FatFs/src/ff.c **** 	FATFS *fs;
+ 9481              		.loc 1 4723 2 view .LVU3173
+4724:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE buf[_FS_EXFAT ? SZDIRE * 2 : 24], *dir;
+ 9482              		.loc 1 4724 2 view .LVU3174
+4725:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD dw;
+ 9483              		.loc 1 4725 2 view .LVU3175
+4726:Middlewares/Third_Party/FatFs/src/ff.c **** 	DEF_NAMBUF
+ 9484              		.loc 1 4726 2 view .LVU3176
+4730:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path_old, &fs, FA_WRITE);	/* Get logical drive of the old object */
+ 9485              		.loc 1 4730 2 view .LVU3177
+ 9486 0008 6846     		mov	r0, sp
+ 9487              	.LVL1099:
+4730:Middlewares/Third_Party/FatFs/src/ff.c **** 	res = find_volume(&path_old, &fs, FA_WRITE);	/* Get logical drive of the old object */
+ 9488              		.loc 1 4730 2 is_stmt 0 view .LVU3178
+ 9489 000a FFF7FEFF 		bl	get_ldnumber
+ 9490              	.LVL1100:
+4731:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 9491              		.loc 1 4731 2 is_stmt 1 view .LVU3179
+4731:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (res == FR_OK) {
+ 9492              		.loc 1 4731 8 is_stmt 0 view .LVU3180
+ 9493 000e 0222     		movs	r2, #2
+ 9494 0010 09A9     		add	r1, sp, #36
+ 9495 0012 01A8     		add	r0, sp, #4
+ 9496 0014 FFF7FEFF 		bl	find_volume
+ 9497              	.LVL1101:
+4732:Middlewares/Third_Party/FatFs/src/ff.c **** 		djo.obj.fs = fs;
+ 9498              		.loc 1 4732 2 is_stmt 1 view .LVU3181
+4732:Middlewares/Third_Party/FatFs/src/ff.c **** 		djo.obj.fs = fs;
+ 9499              		.loc 1 4732 5 is_stmt 0 view .LVU3182
+ 9500 0018 0446     		mov	r4, r0
+ 9501 001a 10B1     		cbz	r0, .L696
+ 9502              	.LVL1102:
+ 9503              	.L686:
+4807:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 9504              		.loc 1 4807 16 is_stmt 1 view .LVU3183
+4810:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 9505              		.loc 1 4810 2 view .LVU3184
+4811:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 9506              		.loc 1 4811 1 is_stmt 0 view .LVU3185
+ 9507 001c 2046     		mov	r0, r4
+ 9508 001e 23B0     		add	sp, sp, #140
+ 9509              	.LCFI109:
+ 9510              		.cfi_remember_state
+ 9511              		.cfi_def_cfa_offset 12
+ 9512              		@ sp needed
+ 9513 0020 30BD     		pop	{r4, r5, pc}
+ 9514              	.LVL1103:
+ 9515              	.L696:
+ 9516              	.LCFI110:
+ 9517              		.cfi_restore_state
+4733:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+ 9518              		.loc 1 4733 3 is_stmt 1 view .LVU3186
+4733:Middlewares/Third_Party/FatFs/src/ff.c **** 		INIT_NAMBUF(fs);
+ARM GAS  /tmp/cc5lWXRL.s 			page 321
+
+
+ 9519              		.loc 1 4733 14 is_stmt 0 view .LVU3187
+ 9520 0022 099B     		ldr	r3, [sp, #36]
+ 9521 0024 1693     		str	r3, [sp, #88]
+4734:Middlewares/Third_Party/FatFs/src/ff.c **** 		res = follow_path(&djo, path_old);		/* Check old object */
+ 9522              		.loc 1 4734 18 is_stmt 1 view .LVU3188
+4735:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check vali
+ 9523              		.loc 1 4735 3 view .LVU3189
+4735:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check vali
+ 9524              		.loc 1 4735 9 is_stmt 0 view .LVU3190
+ 9525 0026 0199     		ldr	r1, [sp, #4]
+ 9526 0028 16A8     		add	r0, sp, #88
+ 9527              	.LVL1104:
+4735:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check vali
+ 9528              		.loc 1 4735 9 view .LVU3191
+ 9529 002a FFF7FEFF 		bl	follow_path
+ 9530              	.LVL1105:
+4736:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 9531              		.loc 1 4736 3 is_stmt 1 view .LVU3192
+4736:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 9532              		.loc 1 4736 6 is_stmt 0 view .LVU3193
+ 9533 002e 0446     		mov	r4, r0
+ 9534 0030 20B9     		cbnz	r0, .L687
+4736:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 9535              		.loc 1 4736 30 discriminator 1 view .LVU3194
+ 9536 0032 9DF88730 		ldrb	r3, [sp, #135]	@ zero_extendqisi2
+4736:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 9537              		.loc 1 4736 20 discriminator 1 view .LVU3195
+ 9538 0036 13F0A00F 		tst	r3, #160
+ 9539 003a 1ED1     		bne	.L692
+ 9540              	.L687:
+ 9541              	.LVL1106:
+4738:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = chk_lock(&djo, 2);
+ 9542              		.loc 1 4738 3 is_stmt 1 view .LVU3196
+4738:Middlewares/Third_Party/FatFs/src/ff.c **** 			res = chk_lock(&djo, 2);
+ 9543              		.loc 1 4738 6 is_stmt 0 view .LVU3197
+ 9544 003c 24B9     		cbnz	r4, .L688
+4739:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 9545              		.loc 1 4739 4 is_stmt 1 view .LVU3198
+4739:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 9546              		.loc 1 4739 10 is_stmt 0 view .LVU3199
+ 9547 003e 0221     		movs	r1, #2
+ 9548 0040 16A8     		add	r0, sp, #88
+ 9549 0042 FFF7FEFF 		bl	chk_lock
+ 9550              	.LVL1107:
+ 9551 0046 0446     		mov	r4, r0
+ 9552              	.LVL1108:
+ 9553              	.L688:
+4742:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 9554              		.loc 1 4742 3 is_stmt 1 view .LVU3200
+4742:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT
+ 9555              		.loc 1 4742 6 is_stmt 0 view .LVU3201
+ 9556 0048 002C     		cmp	r4, #0
+ 9557 004a E7D1     		bne	.L686
+4769:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_cpy(&djn, &djo, sizeof (DIR));		/* Duplicate the directory object */
+ 9558              		.loc 1 4769 5 is_stmt 1 view .LVU3202
+ 9559 004c 1522     		movs	r2, #21
+ 9560 004e 1E99     		ldr	r1, [sp, #120]
+ARM GAS  /tmp/cc5lWXRL.s 			page 322
+
+
+ 9561 0050 0B31     		adds	r1, r1, #11
+ 9562 0052 03A8     		add	r0, sp, #12
+ 9563 0054 FFF7FEFF 		bl	mem_cpy
+ 9564              	.LVL1109:
+4770:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+ 9565              		.loc 1 4770 5 view .LVU3203
+ 9566 0058 3022     		movs	r2, #48
+ 9567 005a 16A9     		add	r1, sp, #88
+ 9568 005c 0AA8     		add	r0, sp, #40
+ 9569 005e FFF7FEFF 		bl	mem_cpy
+ 9570              	.LVL1110:
+4771:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+ 9571              		.loc 1 4771 5 view .LVU3204
+4771:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+ 9572              		.loc 1 4771 11 is_stmt 0 view .LVU3205
+ 9573 0062 0099     		ldr	r1, [sp]
+ 9574 0064 0AA8     		add	r0, sp, #40
+ 9575 0066 FFF7FEFF 		bl	follow_path
+ 9576              	.LVL1111:
+4772:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+ 9577              		.loc 1 4772 5 is_stmt 1 view .LVU3206
+4772:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+ 9578              		.loc 1 4772 8 is_stmt 0 view .LVU3207
+ 9579 006a 0446     		mov	r4, r0
+ 9580 006c 68B9     		cbnz	r0, .L689
+4773:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9581              		.loc 1 4773 6 is_stmt 1 view .LVU3208
+4773:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9582              		.loc 1 4773 84 is_stmt 0 view .LVU3209
+ 9583 006e 0C9A     		ldr	r2, [sp, #48]
+ 9584 0070 189B     		ldr	r3, [sp, #96]
+ 9585 0072 9A42     		cmp	r2, r3
+ 9586 0074 03D0     		beq	.L697
+ 9587 0076 0824     		movs	r4, #8
+ 9588 0078 09E0     		b	.L690
+ 9589              	.L692:
+4736:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0
+ 9590              		.loc 1 4736 68 view .LVU3210
+ 9591 007a 0624     		movs	r4, #6
+ 9592 007c E4E7     		b	.L688
+ 9593              	.L697:
+4773:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9594              		.loc 1 4773 46 discriminator 1 view .LVU3211
+ 9595 007e 0F9A     		ldr	r2, [sp, #60]
+ 9596 0080 1B9B     		ldr	r3, [sp, #108]
+ 9597 0082 9A42     		cmp	r2, r3
+ 9598 0084 10D0     		beq	.L691
+4773:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9599              		.loc 1 4773 84 view .LVU3212
+ 9600 0086 0824     		movs	r4, #8
+ 9601 0088 01E0     		b	.L690
+ 9602              	.L689:
+4775:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = dir_register(&djn);			/* Register the new entry */
+ 9603              		.loc 1 4775 5 is_stmt 1 view .LVU3213
+4775:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = dir_register(&djn);			/* Register the new entry */
+ 9604              		.loc 1 4775 8 is_stmt 0 view .LVU3214
+ 9605 008a 0428     		cmp	r0, #4
+ARM GAS  /tmp/cc5lWXRL.s 			page 323
+
+
+ 9606 008c 0CD0     		beq	.L691
+ 9607              	.LVL1112:
+ 9608              	.L690:
+4799:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_remove(&djo);		/* Remove old entry */
+ 9609              		.loc 1 4799 4 is_stmt 1 view .LVU3215
+4799:Middlewares/Third_Party/FatFs/src/ff.c **** 				res = dir_remove(&djo);		/* Remove old entry */
+ 9610              		.loc 1 4799 7 is_stmt 0 view .LVU3216
+ 9611 008e 002C     		cmp	r4, #0
+ 9612 0090 C4D1     		bne	.L686
+4800:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {
+ 9613              		.loc 1 4800 5 is_stmt 1 view .LVU3217
+4800:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (res == FR_OK) {
+ 9614              		.loc 1 4800 11 is_stmt 0 view .LVU3218
+ 9615 0092 16A8     		add	r0, sp, #88
+ 9616 0094 FFF7FEFF 		bl	dir_remove
+ 9617              	.LVL1113:
+4801:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = sync_fs(fs);
+ 9618              		.loc 1 4801 5 is_stmt 1 view .LVU3219
+4801:Middlewares/Third_Party/FatFs/src/ff.c **** 					res = sync_fs(fs);
+ 9619              		.loc 1 4801 8 is_stmt 0 view .LVU3220
+ 9620 0098 0446     		mov	r4, r0
+ 9621 009a 0028     		cmp	r0, #0
+ 9622 009c BED1     		bne	.L686
+4802:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9623              		.loc 1 4802 6 is_stmt 1 view .LVU3221
+4802:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9624              		.loc 1 4802 12 is_stmt 0 view .LVU3222
+ 9625 009e 0998     		ldr	r0, [sp, #36]
+ 9626              	.LVL1114:
+4802:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9627              		.loc 1 4802 12 view .LVU3223
+ 9628 00a0 FFF7FEFF 		bl	sync_fs
+ 9629              	.LVL1115:
+ 9630 00a4 0446     		mov	r4, r0
+ 9631              	.LVL1116:
+4802:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 9632              		.loc 1 4802 12 view .LVU3224
+ 9633 00a6 B9E7     		b	.L686
+ 9634              	.LVL1117:
+ 9635              	.L691:
+4776:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res == FR_OK) {
+ 9636              		.loc 1 4776 6 is_stmt 1 view .LVU3225
+4776:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (res == FR_OK) {
+ 9637              		.loc 1 4776 12 is_stmt 0 view .LVU3226
+ 9638 00a8 0AA8     		add	r0, sp, #40
+ 9639 00aa FFF7FEFF 		bl	dir_register
+ 9640              	.LVL1118:
+4777:Middlewares/Third_Party/FatFs/src/ff.c **** 						dir = djn.dir;					/* Copy information about object except name */
+ 9641              		.loc 1 4777 6 is_stmt 1 view .LVU3227
+4777:Middlewares/Third_Party/FatFs/src/ff.c **** 						dir = djn.dir;					/* Copy information about object except name */
+ 9642              		.loc 1 4777 9 is_stmt 0 view .LVU3228
+ 9643 00ae 0446     		mov	r4, r0
+ 9644 00b0 0028     		cmp	r0, #0
+ 9645 00b2 ECD1     		bne	.L690
+4778:Middlewares/Third_Party/FatFs/src/ff.c **** 						mem_cpy(dir + 13, buf + 2, 19);
+ 9646              		.loc 1 4778 7 is_stmt 1 view .LVU3229
+4778:Middlewares/Third_Party/FatFs/src/ff.c **** 						mem_cpy(dir + 13, buf + 2, 19);
+ARM GAS  /tmp/cc5lWXRL.s 			page 324
+
+
+ 9647              		.loc 1 4778 11 is_stmt 0 view .LVU3230
+ 9648 00b4 129D     		ldr	r5, [sp, #72]
+ 9649              	.LVL1119:
+4779:Middlewares/Third_Party/FatFs/src/ff.c **** 						dir[DIR_Attr] = buf[0] | AM_ARC;
+ 9650              		.loc 1 4779 7 is_stmt 1 view .LVU3231
+ 9651 00b6 1322     		movs	r2, #19
+ 9652 00b8 0DF10E01 		add	r1, sp, #14
+ 9653 00bc 05F10D00 		add	r0, r5, #13
+ 9654              	.LVL1120:
+4779:Middlewares/Third_Party/FatFs/src/ff.c **** 						dir[DIR_Attr] = buf[0] | AM_ARC;
+ 9655              		.loc 1 4779 7 is_stmt 0 view .LVU3232
+ 9656 00c0 FFF7FEFF 		bl	mem_cpy
+ 9657              	.LVL1121:
+4780:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 9658              		.loc 1 4780 7 is_stmt 1 view .LVU3233
+4780:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 9659              		.loc 1 4780 26 is_stmt 0 view .LVU3234
+ 9660 00c4 9DF80C30 		ldrb	r3, [sp, #12]	@ zero_extendqisi2
+4780:Middlewares/Third_Party/FatFs/src/ff.c **** 						fs->wflag = 1;
+ 9661              		.loc 1 4780 21 view .LVU3235
+ 9662 00c8 43F02003 		orr	r3, r3, #32
+ 9663 00cc EB72     		strb	r3, [r5, #11]
+4781:Middlewares/Third_Party/FatFs/src/ff.c **** 						if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) {	/* Update .. entry in the
+ 9664              		.loc 1 4781 7 is_stmt 1 view .LVU3236
+4781:Middlewares/Third_Party/FatFs/src/ff.c **** 						if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) {	/* Update .. entry in the
+ 9665              		.loc 1 4781 17 is_stmt 0 view .LVU3237
+ 9666 00ce 099B     		ldr	r3, [sp, #36]
+ 9667 00d0 0122     		movs	r2, #1
+ 9668 00d2 DA70     		strb	r2, [r3, #3]
+4782:Middlewares/Third_Party/FatFs/src/ff.c **** 							dw = clust2sect(fs, ld_clust(fs, dir));
+ 9669              		.loc 1 4782 7 is_stmt 1 view .LVU3238
+4782:Middlewares/Third_Party/FatFs/src/ff.c **** 							dw = clust2sect(fs, ld_clust(fs, dir));
+ 9670              		.loc 1 4782 15 is_stmt 0 view .LVU3239
+ 9671 00d4 EB7A     		ldrb	r3, [r5, #11]	@ zero_extendqisi2
+4782:Middlewares/Third_Party/FatFs/src/ff.c **** 							dw = clust2sect(fs, ld_clust(fs, dir));
+ 9672              		.loc 1 4782 10 view .LVU3240
+ 9673 00d6 13F0100F 		tst	r3, #16
+ 9674 00da D8D0     		beq	.L690
+4782:Middlewares/Third_Party/FatFs/src/ff.c **** 							dw = clust2sect(fs, ld_clust(fs, dir));
+ 9675              		.loc 1 4782 36 discriminator 1 view .LVU3241
+ 9676 00dc 189A     		ldr	r2, [sp, #96]
+ 9677 00de 0C9B     		ldr	r3, [sp, #48]
+ 9678 00e0 9A42     		cmp	r2, r3
+ 9679 00e2 D4D0     		beq	.L690
+4783:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (!dw) {
+ 9680              		.loc 1 4783 8 is_stmt 1 view .LVU3242
+4783:Middlewares/Third_Party/FatFs/src/ff.c **** 							if (!dw) {
+ 9681              		.loc 1 4783 13 is_stmt 0 view .LVU3243
+ 9682 00e4 099C     		ldr	r4, [sp, #36]
+ 9683 00e6 2946     		mov	r1, r5
+ 9684 00e8 2046     		mov	r0, r4
+ 9685 00ea FFF7FEFF 		bl	ld_clust
+ 9686              	.LVL1122:
+ 9687 00ee 0146     		mov	r1, r0
+ 9688 00f0 2046     		mov	r0, r4
+ 9689 00f2 FFF7FEFF 		bl	clust2sect
+ 9690              	.LVL1123:
+ARM GAS  /tmp/cc5lWXRL.s 			page 325
+
+
+4784:Middlewares/Third_Party/FatFs/src/ff.c **** 								res = FR_INT_ERR;
+ 9691              		.loc 1 4784 8 is_stmt 1 view .LVU3244
+4784:Middlewares/Third_Party/FatFs/src/ff.c **** 								res = FR_INT_ERR;
+ 9692              		.loc 1 4784 11 is_stmt 0 view .LVU3245
+ 9693 00f6 0146     		mov	r1, r0
+ 9694 00f8 08B9     		cbnz	r0, .L698
+4785:Middlewares/Third_Party/FatFs/src/ff.c **** 							} else {
+ 9695              		.loc 1 4785 13 view .LVU3246
+ 9696 00fa 0224     		movs	r4, #2
+ 9697 00fc 8EE7     		b	.L686
+ 9698              	.L698:
+4788:Middlewares/Third_Party/FatFs/src/ff.c **** 								dir = fs->win + SZDIRE * 1;	/* Ptr to .. entry */
+ 9699              		.loc 1 4788 9 is_stmt 1 view .LVU3247
+4788:Middlewares/Third_Party/FatFs/src/ff.c **** 								dir = fs->win + SZDIRE * 1;	/* Ptr to .. entry */
+ 9700              		.loc 1 4788 15 is_stmt 0 view .LVU3248
+ 9701 00fe 2046     		mov	r0, r4
+ 9702              	.LVL1124:
+4788:Middlewares/Third_Party/FatFs/src/ff.c **** 								dir = fs->win + SZDIRE * 1;	/* Ptr to .. entry */
+ 9703              		.loc 1 4788 15 view .LVU3249
+ 9704 0100 FFF7FEFF 		bl	move_window
+ 9705              	.LVL1125:
+4789:Middlewares/Third_Party/FatFs/src/ff.c **** 								if (res == FR_OK && dir[1] == '.') {
+ 9706              		.loc 1 4789 9 is_stmt 1 view .LVU3250
+4789:Middlewares/Third_Party/FatFs/src/ff.c **** 								if (res == FR_OK && dir[1] == '.') {
+ 9707              		.loc 1 4789 17 is_stmt 0 view .LVU3251
+ 9708 0104 099B     		ldr	r3, [sp, #36]
+4789:Middlewares/Third_Party/FatFs/src/ff.c **** 								if (res == FR_OK && dir[1] == '.') {
+ 9709              		.loc 1 4789 13 view .LVU3252
+ 9710 0106 03F15401 		add	r1, r3, #84
+ 9711              	.LVL1126:
+4790:Middlewares/Third_Party/FatFs/src/ff.c **** 									st_clust(fs, dir, djn.obj.sclust);
+ 9712              		.loc 1 4790 9 is_stmt 1 view .LVU3253
+4790:Middlewares/Third_Party/FatFs/src/ff.c **** 									st_clust(fs, dir, djn.obj.sclust);
+ 9713              		.loc 1 4790 12 is_stmt 0 view .LVU3254
+ 9714 010a 0446     		mov	r4, r0
+ 9715 010c 0028     		cmp	r0, #0
+ 9716 010e BED1     		bne	.L690
+4790:Middlewares/Third_Party/FatFs/src/ff.c **** 									st_clust(fs, dir, djn.obj.sclust);
+ 9717              		.loc 1 4790 32 discriminator 1 view .LVU3255
+ 9718 0110 93F85520 		ldrb	r2, [r3, #85]	@ zero_extendqisi2
+4790:Middlewares/Third_Party/FatFs/src/ff.c **** 									st_clust(fs, dir, djn.obj.sclust);
+ 9719              		.loc 1 4790 26 discriminator 1 view .LVU3256
+ 9720 0114 2E2A     		cmp	r2, #46
+ 9721 0116 BAD1     		bne	.L690
+4791:Middlewares/Third_Party/FatFs/src/ff.c **** 									fs->wflag = 1;
+ 9722              		.loc 1 4791 10 is_stmt 1 view .LVU3257
+ 9723 0118 0C9A     		ldr	r2, [sp, #48]
+ 9724 011a 1846     		mov	r0, r3
+ 9725              	.LVL1127:
+4791:Middlewares/Third_Party/FatFs/src/ff.c **** 									fs->wflag = 1;
+ 9726              		.loc 1 4791 10 is_stmt 0 view .LVU3258
+ 9727 011c FFF7FEFF 		bl	st_clust
+ 9728              	.LVL1128:
+4792:Middlewares/Third_Party/FatFs/src/ff.c **** 								}
+ 9729              		.loc 1 4792 10 is_stmt 1 view .LVU3259
+4792:Middlewares/Third_Party/FatFs/src/ff.c **** 								}
+ 9730              		.loc 1 4792 20 is_stmt 0 view .LVU3260
+ARM GAS  /tmp/cc5lWXRL.s 			page 326
+
+
+ 9731 0120 099B     		ldr	r3, [sp, #36]
+ 9732 0122 0122     		movs	r2, #1
+ 9733 0124 DA70     		strb	r2, [r3, #3]
+ 9734 0126 B2E7     		b	.L690
+ 9735              		.cfi_endproc
+ 9736              	.LFE1236:
+ 9738              		.section	.rodata.f_mkfs.str1.4,"aMS",%progbits,1
+ 9739              		.align	2
+ 9740              	.LC1:
+ 9741 0000 EBFE904D 		.ascii	"\353\376\220MSDOS5.0\000"
+ 9741      53444F53 
+ 9741      352E3000 
+ 9742              		.align	2
+ 9743              	.LC2:
+ 9744 000c 4E4F204E 		.ascii	"NO NAME    FAT32   \000"
+ 9744      414D4520 
+ 9744      20202046 
+ 9744      41543332 
+ 9744      20202000 
+ 9745              		.align	2
+ 9746              	.LC3:
+ 9747 0020 4E4F204E 		.ascii	"NO NAME    FAT     \000"
+ 9747      414D4520 
+ 9747      20202046 
+ 9747      41542020 
+ 9747      20202000 
+ 9748              		.section	.text.f_mkfs,"ax",%progbits
+ 9749              		.align	1
+ 9750              		.global	f_mkfs
+ 9751              		.syntax unified
+ 9752              		.thumb
+ 9753              		.thumb_func
+ 9754              		.fpu fpv5-d16
+ 9756              	f_mkfs:
+ 9757              	.LVL1129:
+ 9758              	.LFB1237:
+5308:Middlewares/Third_Party/FatFs/src/ff.c **** 	const UINT n_fats = 1;		/* Number of FATs for FAT12/16/32 volume (1 or 2) */
+ 9759              		.loc 1 5308 1 is_stmt 1 view -0
+ 9760              		.cfi_startproc
+ 9761              		@ args = 4, pretend = 0, frame = 48
+ 9762              		@ frame_needed = 0, uses_anonymous_args = 0
+5308:Middlewares/Third_Party/FatFs/src/ff.c **** 	const UINT n_fats = 1;		/* Number of FATs for FAT12/16/32 volume (1 or 2) */
+ 9763              		.loc 1 5308 1 is_stmt 0 view .LVU3262
+ 9764 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 9765              	.LCFI111:
+ 9766              		.cfi_def_cfa_offset 36
+ 9767              		.cfi_offset 4, -36
+ 9768              		.cfi_offset 5, -32
+ 9769              		.cfi_offset 6, -28
+ 9770              		.cfi_offset 7, -24
+ 9771              		.cfi_offset 8, -20
+ 9772              		.cfi_offset 9, -16
+ 9773              		.cfi_offset 10, -12
+ 9774              		.cfi_offset 11, -8
+ 9775              		.cfi_offset 14, -4
+ 9776 0004 8DB0     		sub	sp, sp, #52
+ 9777              	.LCFI112:
+ARM GAS  /tmp/cc5lWXRL.s 			page 327
+
+
+ 9778              		.cfi_def_cfa_offset 88
+ 9779 0006 0790     		str	r0, [sp, #28]
+ 9780 0008 8846     		mov	r8, r1
+ 9781 000a 1546     		mov	r5, r2
+ 9782 000c 1E46     		mov	r6, r3
+5309:Middlewares/Third_Party/FatFs/src/ff.c **** 	const UINT n_rootdir = 512;	/* Number of root directory entries for FAT12/16 volume */
+ 9783              		.loc 1 5309 2 is_stmt 1 view .LVU3263
+ 9784              	.LVL1130:
+5310:Middlewares/Third_Party/FatFs/src/ff.c **** 	static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0};	/* Cluster size boundary for FAT12/16 volum
+ 9785              		.loc 1 5310 2 view .LVU3264
+5311:Middlewares/Third_Party/FatFs/src/ff.c **** 	static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0};	/* Cluster size boundary for FAT32 volume (12
+ 9786              		.loc 1 5311 2 view .LVU3265
+5312:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE fmt, sys, *buf, *pte, pdrv, part;
+ 9787              		.loc 1 5312 2 view .LVU3266
+5313:Middlewares/Third_Party/FatFs/src/ff.c **** 	WORD ss;
+ 9788              		.loc 1 5313 2 view .LVU3267
+5314:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n;
+ 9789              		.loc 1 5314 2 view .LVU3268
+5315:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD b_vol, b_fat, b_data;				/* Base LBA for volume, fat, data */
+ 9790              		.loc 1 5315 2 view .LVU3269
+5316:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD sz_vol, sz_rsv, sz_fat, sz_dir;	/* Size for volume, fat, dir, data */
+ 9791              		.loc 1 5316 2 view .LVU3270
+5317:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i;
+ 9792              		.loc 1 5317 2 view .LVU3271
+5318:Middlewares/Third_Party/FatFs/src/ff.c **** 	int vol;
+ 9793              		.loc 1 5318 2 view .LVU3272
+5319:Middlewares/Third_Party/FatFs/src/ff.c **** 	DSTATUS stat;
+ 9794              		.loc 1 5319 2 view .LVU3273
+5320:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM || _FS_EXFAT
+ 9795              		.loc 1 5320 2 view .LVU3274
+5327:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+ 9796              		.loc 1 5327 2 view .LVU3275
+5327:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+ 9797              		.loc 1 5327 8 is_stmt 0 view .LVU3276
+ 9798 000e 07A8     		add	r0, sp, #28
+ 9799              	.LVL1131:
+5327:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (vol < 0) return FR_INVALID_DRIVE;
+ 9800              		.loc 1 5327 8 view .LVU3277
+ 9801 0010 FFF7FEFF 		bl	get_ldnumber
+ 9802              	.LVL1132:
+5328:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (FatFs[vol]) FatFs[vol]->fs_type = 0;	/* Clear the volume */
+ 9803              		.loc 1 5328 2 is_stmt 1 view .LVU3278
+5328:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (FatFs[vol]) FatFs[vol]->fs_type = 0;	/* Clear the volume */
+ 9804              		.loc 1 5328 5 is_stmt 0 view .LVU3279
+ 9805 0014 0028     		cmp	r0, #0
+5328:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (FatFs[vol]) FatFs[vol]->fs_type = 0;	/* Clear the volume */
+ 9806              		.loc 1 5328 5 view .LVU3280
+ 9807 0016 C0F2F982 		blt	.L743
+5329:Middlewares/Third_Party/FatFs/src/ff.c **** 	pdrv = LD2PD(vol);	/* Physical drive */
+ 9808              		.loc 1 5329 2 is_stmt 1 view .LVU3281
+5329:Middlewares/Third_Party/FatFs/src/ff.c **** 	pdrv = LD2PD(vol);	/* Physical drive */
+ 9809              		.loc 1 5329 11 is_stmt 0 view .LVU3282
+ 9810 001a A74B     		ldr	r3, .L796
+ 9811 001c 53F82030 		ldr	r3, [r3, r0, lsl #2]
+5329:Middlewares/Third_Party/FatFs/src/ff.c **** 	pdrv = LD2PD(vol);	/* Physical drive */
+ 9812              		.loc 1 5329 5 view .LVU3283
+ 9813 0020 0BB1     		cbz	r3, .L701
+ARM GAS  /tmp/cc5lWXRL.s 			page 328
+
+
+5329:Middlewares/Third_Party/FatFs/src/ff.c **** 	pdrv = LD2PD(vol);	/* Physical drive */
+ 9814              		.loc 1 5329 18 is_stmt 1 discriminator 1 view .LVU3284
+5329:Middlewares/Third_Party/FatFs/src/ff.c **** 	pdrv = LD2PD(vol);	/* Physical drive */
+ 9815              		.loc 1 5329 38 is_stmt 0 discriminator 1 view .LVU3285
+ 9816 0022 0022     		movs	r2, #0
+ 9817 0024 1A70     		strb	r2, [r3]
+ 9818              	.L701:
+5330:Middlewares/Third_Party/FatFs/src/ff.c **** 	part = LD2PT(vol);	/* Partition (0:create as new, 1-4:get from partition table) */
+ 9819              		.loc 1 5330 2 is_stmt 1 view .LVU3286
+5330:Middlewares/Third_Party/FatFs/src/ff.c **** 	part = LD2PT(vol);	/* Partition (0:create as new, 1-4:get from partition table) */
+ 9820              		.loc 1 5330 7 is_stmt 0 view .LVU3287
+ 9821 0026 C4B2     		uxtb	r4, r0
+ 9822              	.LVL1133:
+5331:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 9823              		.loc 1 5331 2 is_stmt 1 view .LVU3288
+5334:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_NOINIT) return FR_NOT_READY;
+ 9824              		.loc 1 5334 2 view .LVU3289
+5334:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_NOINIT) return FR_NOT_READY;
+ 9825              		.loc 1 5334 9 is_stmt 0 view .LVU3290
+ 9826 0028 2046     		mov	r0, r4
+ 9827              	.LVL1134:
+5334:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_NOINIT) return FR_NOT_READY;
+ 9828              		.loc 1 5334 9 view .LVU3291
+ 9829 002a FFF7FEFF 		bl	disk_initialize
+ 9830              	.LVL1135:
+5335:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+ 9831              		.loc 1 5335 2 is_stmt 1 view .LVU3292
+5335:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+ 9832              		.loc 1 5335 5 is_stmt 0 view .LVU3293
+ 9833 002e 10F0010F 		tst	r0, #1
+ 9834 0032 40F0ED82 		bne	.L744
+5336:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & 
+ 9835              		.loc 1 5336 2 is_stmt 1 view .LVU3294
+5336:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & 
+ 9836              		.loc 1 5336 5 is_stmt 0 view .LVU3295
+ 9837 0036 10F0040F 		tst	r0, #4
+ 9838 003a 40F0EB82 		bne	.L745
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+ 9839              		.loc 1 5337 2 is_stmt 1 view .LVU3296
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+ 9840              		.loc 1 5337 6 is_stmt 0 view .LVU3297
+ 9841 003e 0AAA     		add	r2, sp, #40
+ 9842 0040 0321     		movs	r1, #3
+ 9843 0042 2046     		mov	r0, r4
+ 9844              	.LVL1136:
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+ 9845              		.loc 1 5337 6 view .LVU3298
+ 9846 0044 FFF7FEFF 		bl	disk_ioctl
+ 9847              	.LVL1137:
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+ 9848              		.loc 1 5337 5 view .LVU3299
+ 9849 0048 38B9     		cbnz	r0, .L702
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+ 9850              		.loc 1 5337 61 discriminator 2 view .LVU3300
+ 9851 004a 0A9B     		ldr	r3, [sp, #40]
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+ 9852              		.loc 1 5337 58 discriminator 2 view .LVU3301
+ARM GAS  /tmp/cc5lWXRL.s 			page 329
+
+
+ 9853 004c 2BB1     		cbz	r3, .L702
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+ 9854              		.loc 1 5337 69 discriminator 4 view .LVU3302
+ 9855 004e B3F5004F 		cmp	r3, #32768
+ 9856 0052 02D8     		bhi	.L702
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+ 9857              		.loc 1 5337 108 discriminator 6 view .LVU3303
+ 9858 0054 5A1E     		subs	r2, r3, #1
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+ 9859              		.loc 1 5337 87 discriminator 6 view .LVU3304
+ 9860 0056 1342     		tst	r3, r2
+ 9861 0058 01D0     		beq	.L703
+ 9862              	.L702:
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+ 9863              		.loc 1 5337 115 is_stmt 1 discriminator 7 view .LVU3305
+5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+ 9864              		.loc 1 5337 122 is_stmt 0 discriminator 7 view .LVU3306
+ 9865 005a 0123     		movs	r3, #1
+ 9866 005c 0A93     		str	r3, [sp, #40]
+ 9867              	.L703:
+5339:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+ 9868              		.loc 1 5339 2 is_stmt 1 view .LVU3307
+5339:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+ 9869              		.loc 1 5339 6 is_stmt 0 view .LVU3308
+ 9870 005e 0DF12E02 		add	r2, sp, #46
+ 9871 0062 0221     		movs	r1, #2
+ 9872 0064 2046     		mov	r0, r4
+ 9873 0066 FFF7FEFF 		bl	disk_ioctl
+ 9874              	.LVL1138:
+5339:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+ 9875              		.loc 1 5339 5 view .LVU3309
+ 9876 006a 0028     		cmp	r0, #0
+ 9877 006c 40F0D682 		bne	.L746
+5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 9878              		.loc 1 5340 2 is_stmt 1 view .LVU3310
+5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 9879              		.loc 1 5340 19 is_stmt 0 view .LVU3311
+ 9880 0070 BDF82E70 		ldrh	r7, [sp, #46]
+ 9881 0074 A7F50073 		sub	r3, r7, #512
+ 9882 0078 9BB2     		uxth	r3, r3
+5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 9883              		.loc 1 5340 5 view .LVU3312
+ 9884 007a B3F5606F 		cmp	r3, #3584
+ 9885 007e 00F2CF82 		bhi	.L747
+5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 9886              		.loc 1 5340 48 discriminator 2 view .LVU3313
+ 9887 0082 7B1E     		subs	r3, r7, #1
+5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 9888              		.loc 1 5340 35 discriminator 2 view .LVU3314
+ 9889 0084 1F42     		tst	r7, r3
+ 9890 0086 40F0CD82 		bne	.L748
+5344:Middlewares/Third_Party/FatFs/src/ff.c **** 	au /= ss;	/* Cluster size in unit of sector */
+ 9891              		.loc 1 5344 2 is_stmt 1 view .LVU3315
+5344:Middlewares/Third_Party/FatFs/src/ff.c **** 	au /= ss;	/* Cluster size in unit of sector */
+ 9892              		.loc 1 5344 5 is_stmt 0 view .LVU3316
+ 9893 008a 15B1     		cbz	r5, .L704
+5344:Middlewares/Third_Party/FatFs/src/ff.c **** 	au /= ss;	/* Cluster size in unit of sector */
+ARM GAS  /tmp/cc5lWXRL.s 			page 330
+
+
+ 9894              		.loc 1 5344 15 discriminator 1 view .LVU3317
+ 9895 008c AF42     		cmp	r7, r5
+ 9896 008e 00F2CB82 		bhi	.L749
+ 9897              	.L704:
+5344:Middlewares/Third_Party/FatFs/src/ff.c **** 	au /= ss;	/* Cluster size in unit of sector */
+ 9898              		.loc 1 5344 27 discriminator 4 view .LVU3318
+ 9899 0092 B5F1807F 		cmp	r5, #16777216
+ 9900 0096 00F2C982 		bhi	.L750
+5344:Middlewares/Third_Party/FatFs/src/ff.c **** 	au /= ss;	/* Cluster size in unit of sector */
+ 9901              		.loc 1 5344 58 discriminator 6 view .LVU3319
+ 9902 009a 6B1E     		subs	r3, r5, #1
+5344:Middlewares/Third_Party/FatFs/src/ff.c **** 	au /= ss;	/* Cluster size in unit of sector */
+ 9903              		.loc 1 5344 45 discriminator 6 view .LVU3320
+ 9904 009c 2B40     		ands	r3, r3, r5
+ 9905 009e 0193     		str	r3, [sp, #4]
+ 9906 00a0 40F0C682 		bne	.L751
+5345:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 9907              		.loc 1 5345 2 is_stmt 1 view .LVU3321
+5345:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 9908              		.loc 1 5345 5 is_stmt 0 view .LVU3322
+ 9909 00a4 B5FBF7F5 		udiv	r5, r5, r7
+ 9910              	.LVL1139:
+5348:Middlewares/Third_Party/FatFs/src/ff.c **** 	sz_buf = len / ss;		/* Size of working buffer (sector) */
+ 9911              		.loc 1 5348 2 is_stmt 1 view .LVU3323
+5349:Middlewares/Third_Party/FatFs/src/ff.c **** 	szb_buf = sz_buf * ss;	/* Size of working buffer (byte) */
+ 9912              		.loc 1 5349 2 view .LVU3324
+5349:Middlewares/Third_Party/FatFs/src/ff.c **** 	szb_buf = sz_buf * ss;	/* Size of working buffer (byte) */
+ 9913              		.loc 1 5349 9 is_stmt 0 view .LVU3325
+ 9914 00a8 169B     		ldr	r3, [sp, #88]
+ 9915 00aa B3FBF7F9 		udiv	r9, r3, r7
+ 9916              	.LVL1140:
+5350:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!szb_buf) return FR_MKFS_ABORTED;
+ 9917              		.loc 1 5350 2 is_stmt 1 view .LVU3326
+5350:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (!szb_buf) return FR_MKFS_ABORTED;
+ 9918              		.loc 1 5350 10 is_stmt 0 view .LVU3327
+ 9919 00ae 09FB07F7 		mul	r7, r9, r7
+ 9920              	.LVL1141:
+5351:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 9921              		.loc 1 5351 2 is_stmt 1 view .LVU3328
+5351:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 9922              		.loc 1 5351 5 is_stmt 0 view .LVU3329
+ 9923 00b2 002F     		cmp	r7, #0
+ 9924 00b4 00F0BE82 		beq	.L752
+5354:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Get partition information from partition table in the MBR */
+ 9925              		.loc 1 5354 2 is_stmt 1 view .LVU3330
+5364:Middlewares/Third_Party/FatFs/src/ff.c **** 		b_vol = (opt & FM_SFD) ? 0 : 63;		/* Volume start sector */
+ 9926              		.loc 1 5364 3 view .LVU3331
+5364:Middlewares/Third_Party/FatFs/src/ff.c **** 		b_vol = (opt & FM_SFD) ? 0 : 63;		/* Volume start sector */
+ 9927              		.loc 1 5364 7 is_stmt 0 view .LVU3332
+ 9928 00b8 09AA     		add	r2, sp, #36
+ 9929 00ba 0121     		movs	r1, #1
+ 9930 00bc 2046     		mov	r0, r4
+ 9931 00be FFF7FEFF 		bl	disk_ioctl
+ 9932              	.LVL1142:
+5364:Middlewares/Third_Party/FatFs/src/ff.c **** 		b_vol = (opt & FM_SFD) ? 0 : 63;		/* Volume start sector */
+ 9933              		.loc 1 5364 6 view .LVU3333
+ 9934 00c2 0028     		cmp	r0, #0
+ARM GAS  /tmp/cc5lWXRL.s 			page 331
+
+
+ 9935 00c4 40F0B882 		bne	.L753
+5365:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (sz_vol < b_vol) return FR_MKFS_ABORTED;
+ 9936              		.loc 1 5365 3 is_stmt 1 view .LVU3334
+5365:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (sz_vol < b_vol) return FR_MKFS_ABORTED;
+ 9937              		.loc 1 5365 30 is_stmt 0 view .LVU3335
+ 9938 00c8 18F00802 		ands	r2, r8, #8
+ 9939 00cc 0292     		str	r2, [sp, #8]
+ 9940 00ce 7AD0     		beq	.L754
+ 9941 00d0 019B     		ldr	r3, [sp, #4]
+ 9942 00d2 0093     		str	r3, [sp]
+ 9943              	.L705:
+ 9944              	.LVL1143:
+5366:Middlewares/Third_Party/FatFs/src/ff.c **** 		sz_vol -= b_vol;						/* Volume size */
+ 9945              		.loc 1 5366 3 is_stmt 1 discriminator 4 view .LVU3336
+5366:Middlewares/Third_Party/FatFs/src/ff.c **** 		sz_vol -= b_vol;						/* Volume size */
+ 9946              		.loc 1 5366 14 is_stmt 0 discriminator 4 view .LVU3337
+ 9947 00d4 099A     		ldr	r2, [sp, #36]
+5366:Middlewares/Third_Party/FatFs/src/ff.c **** 		sz_vol -= b_vol;						/* Volume size */
+ 9948              		.loc 1 5366 6 discriminator 4 view .LVU3338
+ 9949 00d6 009B     		ldr	r3, [sp]
+ 9950 00d8 9A42     		cmp	r2, r3
+ 9951 00da C0F0AF82 		bcc	.L755
+5367:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 9952              		.loc 1 5367 3 is_stmt 1 view .LVU3339
+5367:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 9953              		.loc 1 5367 10 is_stmt 0 view .LVU3340
+ 9954 00de D21A     		subs	r2, r2, r3
+ 9955 00e0 0992     		str	r2, [sp, #36]
+5369:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 9956              		.loc 1 5369 2 is_stmt 1 view .LVU3341
+5369:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 9957              		.loc 1 5369 5 is_stmt 0 view .LVU3342
+ 9958 00e2 7F2A     		cmp	r2, #127
+ 9959 00e4 40F2AC82 		bls	.L756
+5372:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (_FS_EXFAT && (opt & FM_EXFAT)) {	/* exFAT possible? */
+ 9960              		.loc 1 5372 2 is_stmt 1 view .LVU3343
+5373:Middlewares/Third_Party/FatFs/src/ff.c **** 			if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) {	/* exFAT only, vol >= 64Ms 
+ 9961              		.loc 1 5373 3 view .LVU3344
+5378:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (opt & FM_FAT32) {	/* FAT32 possible? */
+ 9962              		.loc 1 5378 3 view .LVU3345
+5378:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (opt & FM_FAT32) {	/* FAT32 possible? */
+ 9963              		.loc 1 5378 6 is_stmt 0 view .LVU3346
+ 9964 00e8 802D     		cmp	r5, #128
+ 9965 00ea 00F2AB82 		bhi	.L757
+5379:Middlewares/Third_Party/FatFs/src/ff.c **** 			if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) {	/* FAT32 only or no-FAT? */
+ 9966              		.loc 1 5379 3 is_stmt 1 view .LVU3347
+5379:Middlewares/Third_Party/FatFs/src/ff.c **** 			if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) {	/* FAT32 only or no-FAT? */
+ 9967              		.loc 1 5379 6 is_stmt 0 view .LVU3348
+ 9968 00ee 18F00201 		ands	r1, r8, #2
+ 9969 00f2 06D0     		beq	.L706
+5380:Middlewares/Third_Party/FatFs/src/ff.c **** 				fmt = FS_FAT32; break;
+ 9970              		.loc 1 5380 4 is_stmt 1 view .LVU3349
+5380:Middlewares/Third_Party/FatFs/src/ff.c **** 				fmt = FS_FAT32; break;
+ 9971              		.loc 1 5380 7 is_stmt 0 view .LVU3350
+ 9972 00f4 08F00703 		and	r3, r8, #7
+ 9973 00f8 022B     		cmp	r3, #2
+ 9974 00fa 67D0     		beq	.L758
+ARM GAS  /tmp/cc5lWXRL.s 			page 332
+
+
+5380:Middlewares/Third_Party/FatFs/src/ff.c **** 				fmt = FS_FAT32; break;
+ 9975              		.loc 1 5380 35 discriminator 1 view .LVU3351
+ 9976 00fc 18F0010F 		tst	r8, #1
+ 9977 0100 6AD0     		beq	.L759
+ 9978              	.L706:
+5384:Middlewares/Third_Party/FatFs/src/ff.c **** 		fmt = FS_FAT16;
+ 9979              		.loc 1 5384 3 is_stmt 1 view .LVU3352
+5384:Middlewares/Third_Party/FatFs/src/ff.c **** 		fmt = FS_FAT16;
+ 9980              		.loc 1 5384 6 is_stmt 0 view .LVU3353
+ 9981 0102 18F0010F 		tst	r8, #1
+ 9982 0106 00F09F82 		beq	.L760
+5385:Middlewares/Third_Party/FatFs/src/ff.c **** 	} while (0);
+ 9983              		.loc 1 5385 7 view .LVU3354
+ 9984 010a 4FF0020B 		mov	fp, #2
+ 9985 010e 0394     		str	r4, [sp, #12]
+ 9986 0110 CDF81090 		str	r9, [sp, #16]
+ 9987              	.LVL1144:
+ 9988              	.L708:
+5386:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 9989              		.loc 1 5386 10 is_stmt 1 view .LVU3355
+5552:Middlewares/Third_Party/FatFs/src/ff.c **** 			pau = au;
+ 9990              		.loc 1 5552 3 view .LVU3356
+5553:Middlewares/Third_Party/FatFs/src/ff.c **** 			/* Pre-determine number of clusters and FAT sub-type */
+ 9991              		.loc 1 5553 4 view .LVU3357
+5555:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!pau) {	/* au auto-selection */
+ 9992              		.loc 1 5555 4 view .LVU3358
+5555:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (!pau) {	/* au auto-selection */
+ 9993              		.loc 1 5555 7 is_stmt 0 view .LVU3359
+ 9994 0114 BBF1030F 		cmp	fp, #3
+ 9995 0118 68D0     		beq	.L726
+5566:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = sz_vol / 0x1000;	/* Volume size in unit of 4KS */
+ 9996              		.loc 1 5566 5 is_stmt 1 view .LVU3360
+5566:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = sz_vol / 0x1000;	/* Volume size in unit of 4KS */
+ 9997              		.loc 1 5566 8 is_stmt 0 view .LVU3361
+ 9998 011a 002D     		cmp	r5, #0
+ 9999 011c 00F08F80 		beq	.L785
+ 10000 0120 AA46     		mov	r10, r5
+ 10001              	.LVL1145:
+ 10002              	.L714:
+5570:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst > MAX_FAT12) {
+ 10003              		.loc 1 5570 5 is_stmt 1 view .LVU3362
+5570:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst > MAX_FAT12) {
+ 10004              		.loc 1 5570 12 is_stmt 0 view .LVU3363
+ 10005 0122 B2FBFAF3 		udiv	r3, r2, r10
+ 10006              	.LVL1146:
+5571:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = n_clst * 2 + 4;		/* FAT size [byte] */
+ 10007              		.loc 1 5571 5 is_stmt 1 view .LVU3364
+5571:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = n_clst * 2 + 4;		/* FAT size [byte] */
+ 10008              		.loc 1 5571 8 is_stmt 0 view .LVU3365
+ 10009 0126 40F6F570 		movw	r0, #4085
+ 10010 012a 8342     		cmp	r3, r0
+ 10011 012c 40F29880 		bls	.L717
+5572:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+ 10012              		.loc 1 5572 6 is_stmt 1 view .LVU3366
+5572:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+ 10013              		.loc 1 5572 21 is_stmt 0 view .LVU3367
+ 10014 0130 03F10208 		add	r8, r3, #2
+ARM GAS  /tmp/cc5lWXRL.s 			page 333
+
+
+5572:Middlewares/Third_Party/FatFs/src/ff.c **** 				} else {
+ 10015              		.loc 1 5572 8 view .LVU3368
+ 10016 0134 4FEA4808 		lsl	r8, r8, #1
+ 10017              	.LVL1147:
+ 10018              	.L718:
+5577:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv = 1;						/* Number of reserved sectors */
+ 10019              		.loc 1 5577 5 is_stmt 1 view .LVU3369
+5577:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv = 1;						/* Number of reserved sectors */
+ 10020              		.loc 1 5577 17 is_stmt 0 view .LVU3370
+ 10021 0138 BDF82E30 		ldrh	r3, [sp, #46]
+ 10022 013c 9844     		add	r8, r8, r3
+ 10023              	.LVL1148:
+5577:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv = 1;						/* Number of reserved sectors */
+ 10024              		.loc 1 5577 22 view .LVU3371
+ 10025 013e 08F1FF38 		add	r8, r8, #-1
+5577:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv = 1;						/* Number of reserved sectors */
+ 10026              		.loc 1 5577 12 view .LVU3372
+ 10027 0142 B8FBF3F8 		udiv	r8, r8, r3
+ 10028              	.LVL1149:
+5578:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_dir = (DWORD)n_rootdir * SZDIRE / ss;	/* Rootdir size [sector] */
+ 10029              		.loc 1 5578 5 is_stmt 1 view .LVU3373
+5579:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10030              		.loc 1 5579 5 view .LVU3374
+5579:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10031              		.loc 1 5579 12 is_stmt 0 view .LVU3375
+ 10032 0146 4FF4804C 		mov	ip, #16384
+ 10033 014a BCFBF3FC 		udiv	ip, ip, r3
+ 10034              	.LVL1150:
+5578:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_dir = (DWORD)n_rootdir * SZDIRE / ss;	/* Rootdir size [sector] */
+ 10035              		.loc 1 5578 12 view .LVU3376
+ 10036 014e 4FF0010E 		mov	lr, #1
+ 10037              	.LVL1151:
+ 10038              	.L713:
+5581:Middlewares/Third_Party/FatFs/src/ff.c **** 			b_data = b_fat + sz_fat * n_fats + sz_dir;	/* Data base */
+ 10039              		.loc 1 5581 4 is_stmt 1 view .LVU3377
+5581:Middlewares/Third_Party/FatFs/src/ff.c **** 			b_data = b_fat + sz_fat * n_fats + sz_dir;	/* Data base */
+ 10040              		.loc 1 5581 10 is_stmt 0 view .LVU3378
+ 10041 0152 009B     		ldr	r3, [sp]
+ 10042 0154 0EEB0309 		add	r9, lr, r3
+ 10043              	.LVL1152:
+5582:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10044              		.loc 1 5582 4 is_stmt 1 view .LVU3379
+5582:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10045              		.loc 1 5582 19 is_stmt 0 view .LVU3380
+ 10046 0158 08EB0903 		add	r3, r8, r9
+5582:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10047              		.loc 1 5582 11 view .LVU3381
+ 10048 015c 6344     		add	r3, r3, ip
+ 10049              	.LVL1153:
+5585:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
+ 10050              		.loc 1 5585 4 is_stmt 1 view .LVU3382
+5585:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
+ 10051              		.loc 1 5585 17 is_stmt 0 view .LVU3383
+ 10052 015e 0A9C     		ldr	r4, [sp, #40]
+ 10053 0160 E018     		adds	r0, r4, r3
+5585:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
+ 10054              		.loc 1 5585 26 view .LVU3384
+ARM GAS  /tmp/cc5lWXRL.s 			page 334
+
+
+ 10055 0162 0138     		subs	r0, r0, #1
+5585:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
+ 10056              		.loc 1 5585 33 view .LVU3385
+ 10057 0164 6442     		rsbs	r4, r4, #0
+5585:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
+ 10058              		.loc 1 5585 31 view .LVU3386
+ 10059 0166 0440     		ands	r4, r4, r0
+5585:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
+ 10060              		.loc 1 5585 6 view .LVU3387
+ 10061 0168 E41A     		subs	r4, r4, r3
+ 10062              	.LVL1154:
+5586:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv += n; b_fat += n;
+ 10063              		.loc 1 5586 4 is_stmt 1 view .LVU3388
+5586:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv += n; b_fat += n;
+ 10064              		.loc 1 5586 7 is_stmt 0 view .LVU3389
+ 10065 016a BBF1030F 		cmp	fp, #3
+ 10066 016e 00F08280 		beq	.L786
+5589:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10067              		.loc 1 5589 5 is_stmt 1 view .LVU3390
+5589:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10068              		.loc 1 5589 12 is_stmt 0 view .LVU3391
+ 10069 0172 A044     		add	r8, r8, r4
+ 10070              	.LVL1155:
+ 10071              	.L720:
+5593:Middlewares/Third_Party/FatFs/src/ff.c **** 			n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau;
+ 10072              		.loc 1 5593 4 is_stmt 1 view .LVU3392
+5593:Middlewares/Third_Party/FatFs/src/ff.c **** 			n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau;
+ 10073              		.loc 1 5593 24 is_stmt 0 view .LVU3393
+ 10074 0174 03EB0A13 		add	r3, r3, r10, lsl #4
+ 10075              	.LVL1156:
+5593:Middlewares/Third_Party/FatFs/src/ff.c **** 			n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau;
+ 10076              		.loc 1 5593 35 view .LVU3394
+ 10077 0178 0098     		ldr	r0, [sp]
+ 10078 017a 1B1A     		subs	r3, r3, r0
+5593:Middlewares/Third_Party/FatFs/src/ff.c **** 			n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau;
+ 10079              		.loc 1 5593 7 view .LVU3395
+ 10080 017c 9A42     		cmp	r2, r3
+ 10081 017e C0F07382 		bcc	.L764
+5594:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10082              		.loc 1 5594 4 is_stmt 1 view .LVU3396
+5594:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10083              		.loc 1 5594 21 is_stmt 0 view .LVU3397
+ 10084 0182 A2EB0E03 		sub	r3, r2, lr
+5594:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10085              		.loc 1 5594 30 view .LVU3398
+ 10086 0186 A3EB0803 		sub	r3, r3, r8
+5594:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10087              		.loc 1 5594 48 view .LVU3399
+ 10088 018a A3EB0C03 		sub	r3, r3, ip
+5594:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10089              		.loc 1 5594 11 view .LVU3400
+ 10090 018e B3FBFAF3 		udiv	r3, r3, r10
+ 10091              	.LVL1157:
+5595:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst <= MAX_FAT16) {	/* Too few clusters for FAT32 */
+ 10092              		.loc 1 5595 4 is_stmt 1 view .LVU3401
+5595:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst <= MAX_FAT16) {	/* Too few clusters for FAT32 */
+ 10093              		.loc 1 5595 7 is_stmt 0 view .LVU3402
+ARM GAS  /tmp/cc5lWXRL.s 			page 335
+
+
+ 10094 0192 BBF1030F 		cmp	fp, #3
+ 10095 0196 71D0     		beq	.L787
+ 10096              	.L721:
+5601:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst > MAX_FAT16) {	/* Too many clusters for FAT16 */
+ 10097              		.loc 1 5601 4 is_stmt 1 view .LVU3403
+5601:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst > MAX_FAT16) {	/* Too many clusters for FAT16 */
+ 10098              		.loc 1 5601 7 is_stmt 0 view .LVU3404
+ 10099 0198 BBF1020F 		cmp	fp, #2
+ 10100 019c 40F09680 		bne	.L723
+5602:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!au && (pau * 2) <= 64) {
+ 10101              		.loc 1 5602 5 is_stmt 1 view .LVU3405
+5602:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!au && (pau * 2) <= 64) {
+ 10102              		.loc 1 5602 8 is_stmt 0 view .LVU3406
+ 10103 01a0 4FF6F570 		movw	r0, #65525
+ 10104 01a4 8342     		cmp	r3, r0
+ 10105 01a6 78D9     		bls	.L724
+5603:Middlewares/Third_Party/FatFs/src/ff.c **** 						au = pau * 2; continue;		/* Adjust cluster size and retry */
+ 10106              		.loc 1 5603 6 is_stmt 1 view .LVU3407
+5603:Middlewares/Third_Party/FatFs/src/ff.c **** 						au = pau * 2; continue;		/* Adjust cluster size and retry */
+ 10107              		.loc 1 5603 9 is_stmt 0 view .LVU3408
+ 10108 01a8 1DB9     		cbnz	r5, .L725
+5603:Middlewares/Third_Party/FatFs/src/ff.c **** 						au = pau * 2; continue;		/* Adjust cluster size and retry */
+ 10109              		.loc 1 5603 22 discriminator 1 view .LVU3409
+ 10110 01aa 4FEA4A03 		lsl	r3, r10, #1
+ 10111              	.LVL1158:
+5603:Middlewares/Third_Party/FatFs/src/ff.c **** 						au = pau * 2; continue;		/* Adjust cluster size and retry */
+ 10112              		.loc 1 5603 14 discriminator 1 view .LVU3410
+ 10113 01ae 402B     		cmp	r3, #64
+ 10114 01b0 18D9     		bls	.L766
+ 10115              	.L725:
+5606:Middlewares/Third_Party/FatFs/src/ff.c **** 						fmt = FS_FAT32; continue;	/* Switch type to FAT32 and retry */
+ 10116              		.loc 1 5606 6 is_stmt 1 view .LVU3411
+5606:Middlewares/Third_Party/FatFs/src/ff.c **** 						fmt = FS_FAT32; continue;	/* Switch type to FAT32 and retry */
+ 10117              		.loc 1 5606 9 is_stmt 0 view .LVU3412
+ 10118 01b2 C9B9     		cbnz	r1, .L767
+5609:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10119              		.loc 1 5609 6 is_stmt 1 view .LVU3413
+5609:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10120              		.loc 1 5609 9 is_stmt 0 view .LVU3414
+ 10121 01b4 002D     		cmp	r5, #0
+ 10122 01b6 40F05B82 		bne	.L768
+5609:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10123              		.loc 1 5609 21 discriminator 1 view .LVU3415
+ 10124 01ba 4FEA4A05 		lsl	r5, r10, #1
+ 10125              	.LVL1159:
+5609:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10126              		.loc 1 5609 14 discriminator 1 view .LVU3416
+ 10127 01be 802D     		cmp	r5, #128
+ 10128 01c0 A8D9     		bls	.L708
+5610:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10129              		.loc 1 5610 13 view .LVU3417
+ 10130 01c2 0E20     		movs	r0, #14
+ 10131 01c4 27E2     		b	.L700
+ 10132              	.LVL1160:
+ 10133              	.L754:
+5365:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (sz_vol < b_vol) return FR_MKFS_ABORTED;
+ 10134              		.loc 1 5365 30 view .LVU3418
+ARM GAS  /tmp/cc5lWXRL.s 			page 336
+
+
+ 10135 01c6 3F23     		movs	r3, #63
+ 10136 01c8 0093     		str	r3, [sp]
+ 10137 01ca 83E7     		b	.L705
+ 10138              	.LVL1161:
+ 10139              	.L758:
+5381:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10140              		.loc 1 5381 9 view .LVU3419
+ 10141 01cc 4FF0030B 		mov	fp, #3
+ 10142 01d0 0394     		str	r4, [sp, #12]
+ 10143 01d2 CDF81090 		str	r9, [sp, #16]
+ 10144 01d6 9DE7     		b	.L708
+ 10145              	.L759:
+5381:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10146              		.loc 1 5381 9 view .LVU3420
+ 10147 01d8 4FF0030B 		mov	fp, #3
+ 10148 01dc 0394     		str	r4, [sp, #12]
+ 10149 01de CDF81090 		str	r9, [sp, #16]
+ 10150 01e2 97E7     		b	.L708
+ 10151              	.LVL1162:
+ 10152              	.L766:
+5604:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 10153              		.loc 1 5604 10 view .LVU3421
+ 10154 01e4 1D46     		mov	r5, r3
+ 10155 01e6 95E7     		b	.L708
+ 10156              	.L767:
+5607:Middlewares/Third_Party/FatFs/src/ff.c **** 					}
+ 10157              		.loc 1 5607 11 view .LVU3422
+ 10158 01e8 4FF0030B 		mov	fp, #3
+ 10159              	.LVL1163:
+ 10160              	.L726:
+5556:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = sz_vol / 0x20000;	/* Volume size in unit of 128KS */
+ 10161              		.loc 1 5556 5 is_stmt 1 view .LVU3423
+5556:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = sz_vol / 0x20000;	/* Volume size in unit of 128KS */
+ 10162              		.loc 1 5556 8 is_stmt 0 view .LVU3424
+ 10163 01ec BDB1     		cbz	r5, .L788
+ 10164 01ee AA46     		mov	r10, r5
+ 10165              	.L710:
+ 10166              	.LVL1164:
+5560:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_fat = (n_clst * 4 + 8 + ss - 1) / ss;	/* FAT size [sector] */
+ 10167              		.loc 1 5560 5 is_stmt 1 view .LVU3425
+5560:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_fat = (n_clst * 4 + 8 + ss - 1) / ss;	/* FAT size [sector] */
+ 10168              		.loc 1 5560 12 is_stmt 0 view .LVU3426
+ 10169 01f0 B2FBFAF3 		udiv	r3, r2, r10
+ 10170              	.LVL1165:
+5561:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv = 32;	/* Number of reserved sectors */
+ 10171              		.loc 1 5561 5 is_stmt 1 view .LVU3427
+5561:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv = 32;	/* Number of reserved sectors */
+ 10172              		.loc 1 5561 26 is_stmt 0 view .LVU3428
+ 10173 01f4 03F10208 		add	r8, r3, #2
+5561:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv = 32;	/* Number of reserved sectors */
+ 10174              		.loc 1 5561 30 view .LVU3429
+ 10175 01f8 BDF82E00 		ldrh	r0, [sp, #46]
+ 10176 01fc 00EB8808 		add	r8, r0, r8, lsl #2
+5561:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv = 32;	/* Number of reserved sectors */
+ 10177              		.loc 1 5561 35 view .LVU3430
+ 10178 0200 08F1FF38 		add	r8, r8, #-1
+5561:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_rsv = 32;	/* Number of reserved sectors */
+ARM GAS  /tmp/cc5lWXRL.s 			page 337
+
+
+ 10179              		.loc 1 5561 12 view .LVU3431
+ 10180 0204 B8FBF0F8 		udiv	r8, r8, r0
+ 10181              	.LVL1166:
+5562:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_dir = 0;		/* No static directory */
+ 10182              		.loc 1 5562 5 is_stmt 1 view .LVU3432
+5563:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) return FR_MKFS_ABORTED;
+ 10183              		.loc 1 5563 5 view .LVU3433
+5564:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {				/* FAT12/16 volume */
+ 10184              		.loc 1 5564 5 view .LVU3434
+5564:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {				/* FAT12/16 volume */
+ 10185              		.loc 1 5564 29 is_stmt 0 view .LVU3435
+ 10186 0208 2C48     		ldr	r0, .L796+4
+ 10187 020a 1844     		add	r0, r0, r3
+5564:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {				/* FAT12/16 volume */
+ 10188              		.loc 1 5564 8 view .LVU3436
+ 10189 020c 2C4B     		ldr	r3, .L796+8
+ 10190              	.LVL1167:
+5564:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {				/* FAT12/16 volume */
+ 10191              		.loc 1 5564 8 view .LVU3437
+ 10192 020e 9842     		cmp	r0, r3
+ 10193 0210 00F22882 		bhi	.L762
+5563:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) return FR_MKFS_ABORTED;
+ 10194              		.loc 1 5563 12 view .LVU3438
+ 10195 0214 DDF804C0 		ldr	ip, [sp, #4]
+5562:Middlewares/Third_Party/FatFs/src/ff.c **** 				sz_dir = 0;		/* No static directory */
+ 10196              		.loc 1 5562 12 view .LVU3439
+ 10197 0218 4FF0200E 		mov	lr, #32
+ 10198 021c 99E7     		b	.L713
+ 10199              	.LVL1168:
+ 10200              	.L788:
+5557:Middlewares/Third_Party/FatFs/src/ff.c **** 					for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+ 10201              		.loc 1 5557 6 is_stmt 1 view .LVU3440
+5557:Middlewares/Third_Party/FatFs/src/ff.c **** 					for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+ 10202              		.loc 1 5557 8 is_stmt 0 view .LVU3441
+ 10203 021e 540C     		lsrs	r4, r2, #17
+ 10204              	.LVL1169:
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10205              		.loc 1 5558 6 is_stmt 1 view .LVU3442
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10206              		.loc 1 5558 13 is_stmt 0 view .LVU3443
+ 10207 0220 2846     		mov	r0, r5
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10208              		.loc 1 5558 22 view .LVU3444
+ 10209 0222 4FF0010A 		mov	r10, #1
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10210              		.loc 1 5558 6 view .LVU3445
+ 10211 0226 02E0     		b	.L711
+ 10212              	.LVL1170:
+ 10213              	.L712:
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10214              		.loc 1 5558 70 is_stmt 1 discriminator 4 view .LVU3446
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10215              		.loc 1 5558 54 discriminator 4 view .LVU3447
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10216              		.loc 1 5558 55 is_stmt 0 discriminator 4 view .LVU3448
+ 10217 0228 0130     		adds	r0, r0, #1
+ 10218              	.LVL1171:
+ARM GAS  /tmp/cc5lWXRL.s 			page 338
+
+
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10219              		.loc 1 5558 63 discriminator 4 view .LVU3449
+ 10220 022a 4FEA4A0A 		lsl	r10, r10, #1
+ 10221              	.LVL1172:
+ 10222              	.L711:
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10223              		.loc 1 5558 27 is_stmt 1 discriminator 1 view .LVU3450
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10224              		.loc 1 5558 32 is_stmt 0 discriminator 1 view .LVU3451
+ 10225 022e 254B     		ldr	r3, .L796+12
+ 10226 0230 33F81030 		ldrh	r3, [r3, r0, lsl #1]
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10227              		.loc 1 5558 6 discriminator 1 view .LVU3452
+ 10228 0234 002B     		cmp	r3, #0
+ 10229 0236 DBD0     		beq	.L710
+5558:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10230              		.loc 1 5558 36 discriminator 3 view .LVU3453
+ 10231 0238 A342     		cmp	r3, r4
+ 10232 023a F5D9     		bls	.L712
+ 10233 023c D8E7     		b	.L710
+ 10234              	.LVL1173:
+ 10235              	.L785:
+5567:Middlewares/Third_Party/FatFs/src/ff.c **** 					for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+ 10236              		.loc 1 5567 6 is_stmt 1 view .LVU3454
+5567:Middlewares/Third_Party/FatFs/src/ff.c **** 					for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+ 10237              		.loc 1 5567 8 is_stmt 0 view .LVU3455
+ 10238 023e 140B     		lsrs	r4, r2, #12
+ 10239              	.LVL1174:
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10240              		.loc 1 5568 6 is_stmt 1 view .LVU3456
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10241              		.loc 1 5568 13 is_stmt 0 view .LVU3457
+ 10242 0240 2846     		mov	r0, r5
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10243              		.loc 1 5568 22 view .LVU3458
+ 10244 0242 4FF0010A 		mov	r10, #1
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10245              		.loc 1 5568 6 view .LVU3459
+ 10246 0246 02E0     		b	.L715
+ 10247              	.LVL1175:
+ 10248              	.L716:
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10249              		.loc 1 5568 66 is_stmt 1 discriminator 4 view .LVU3460
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10250              		.loc 1 5568 50 discriminator 4 view .LVU3461
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10251              		.loc 1 5568 51 is_stmt 0 discriminator 4 view .LVU3462
+ 10252 0248 0130     		adds	r0, r0, #1
+ 10253              	.LVL1176:
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10254              		.loc 1 5568 59 discriminator 4 view .LVU3463
+ 10255 024a 4FEA4A0A 		lsl	r10, r10, #1
+ 10256              	.LVL1177:
+ 10257              	.L715:
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10258              		.loc 1 5568 27 is_stmt 1 discriminator 1 view .LVU3464
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ARM GAS  /tmp/cc5lWXRL.s 			page 339
+
+
+ 10259              		.loc 1 5568 30 is_stmt 0 discriminator 1 view .LVU3465
+ 10260 024e 1E4B     		ldr	r3, .L796+16
+ 10261 0250 33F81030 		ldrh	r3, [r3, r0, lsl #1]
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10262              		.loc 1 5568 6 discriminator 1 view .LVU3466
+ 10263 0254 002B     		cmp	r3, #0
+ 10264 0256 3FF464AF 		beq	.L714
+5568:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10265              		.loc 1 5568 34 discriminator 3 view .LVU3467
+ 10266 025a A342     		cmp	r3, r4
+ 10267 025c F4D9     		bls	.L716
+ 10268 025e 60E7     		b	.L714
+ 10269              	.LVL1178:
+ 10270              	.L717:
+5574:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = (n_clst * 3 + 1) / 2 + 3;	/* FAT size [byte] */
+ 10271              		.loc 1 5574 6 is_stmt 1 view .LVU3468
+5575:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10272              		.loc 1 5575 6 view .LVU3469
+5575:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10273              		.loc 1 5575 18 is_stmt 0 view .LVU3470
+ 10274 0260 03EB4303 		add	r3, r3, r3, lsl #1
+ 10275              	.LVL1179:
+5575:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10276              		.loc 1 5575 22 view .LVU3471
+ 10277 0264 03F10108 		add	r8, r3, #1
+5575:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10278              		.loc 1 5575 27 view .LVU3472
+ 10279 0268 4FEA5808 		lsr	r8, r8, #1
+5575:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10280              		.loc 1 5575 8 view .LVU3473
+ 10281 026c 08F10308 		add	r8, r8, #3
+ 10282              	.LVL1180:
+5574:Middlewares/Third_Party/FatFs/src/ff.c **** 					n = (n_clst * 3 + 1) / 2 + 3;	/* FAT size [byte] */
+ 10283              		.loc 1 5574 10 view .LVU3474
+ 10284 0270 4FF0010B 		mov	fp, #1
+ 10285 0274 60E7     		b	.L718
+ 10286              	.LVL1181:
+ 10287              	.L786:
+5587:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {					/* FAT12/16: Expand FAT size */
+ 10288              		.loc 1 5587 5 is_stmt 1 view .LVU3475
+5587:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {					/* FAT12/16: Expand FAT size */
+ 10289              		.loc 1 5587 12 is_stmt 0 view .LVU3476
+ 10290 0276 A644     		add	lr, lr, r4
+ 10291              	.LVL1182:
+5587:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {					/* FAT12/16: Expand FAT size */
+ 10292              		.loc 1 5587 18 is_stmt 1 view .LVU3477
+5587:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {					/* FAT12/16: Expand FAT size */
+ 10293              		.loc 1 5587 24 is_stmt 0 view .LVU3478
+ 10294 0278 A144     		add	r9, r9, r4
+ 10295              	.LVL1183:
+5587:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {					/* FAT12/16: Expand FAT size */
+ 10296              		.loc 1 5587 24 view .LVU3479
+ 10297 027a 7BE7     		b	.L720
+ 10298              	.LVL1184:
+ 10299              	.L787:
+5596:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!au && (au = pau / 2) != 0) continue;	/* Adjust cluster size and retry */
+ 10300              		.loc 1 5596 5 is_stmt 1 view .LVU3480
+ARM GAS  /tmp/cc5lWXRL.s 			page 340
+
+
+5596:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!au && (au = pau / 2) != 0) continue;	/* Adjust cluster size and retry */
+ 10301              		.loc 1 5596 8 is_stmt 0 view .LVU3481
+ 10302 027c 4FF6F570 		movw	r0, #65525
+ 10303 0280 8342     		cmp	r3, r0
+ 10304 0282 89D8     		bhi	.L721
+5597:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10305              		.loc 1 5597 6 is_stmt 1 view .LVU3482
+5597:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10306              		.loc 1 5597 9 is_stmt 0 view .LVU3483
+ 10307 0284 002D     		cmp	r5, #0
+ 10308 0286 40F0F181 		bne	.L765
+5597:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10309              		.loc 1 5597 21 discriminator 1 view .LVU3484
+ 10310 028a 4FEA5A05 		lsr	r5, r10, #1
+ 10311              	.LVL1185:
+5597:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10312              		.loc 1 5597 14 discriminator 1 view .LVU3485
+ 10313 028e BAF1010F 		cmp	r10, #1
+ 10314 0292 3FF63FAF 		bhi	.L708
+5598:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10315              		.loc 1 5598 13 view .LVU3486
+ 10316 0296 0E20     		movs	r0, #14
+ 10317 0298 BDE1     		b	.L700
+ 10318              	.LVL1186:
+ 10319              	.L724:
+5612:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!au && (au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+ 10320              		.loc 1 5612 5 is_stmt 1 view .LVU3487
+5612:Middlewares/Third_Party/FatFs/src/ff.c **** 					if (!au && (au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+ 10321              		.loc 1 5612 9 is_stmt 0 view .LVU3488
+ 10322 029a 40F6F570 		movw	r0, #4085
+ 10323 029e 8342     		cmp	r3, r0
+ 10324 02a0 14D8     		bhi	.L723
+5613:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10325              		.loc 1 5613 6 is_stmt 1 view .LVU3489
+5613:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10326              		.loc 1 5613 9 is_stmt 0 view .LVU3490
+ 10327 02a2 002D     		cmp	r5, #0
+ 10328 02a4 40F0E681 		bne	.L769
+5613:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10329              		.loc 1 5613 21 discriminator 1 view .LVU3491
+ 10330 02a8 4FEA4A05 		lsl	r5, r10, #1
+ 10331              	.LVL1187:
+5613:Middlewares/Third_Party/FatFs/src/ff.c **** 					return FR_MKFS_ABORTED;
+ 10332              		.loc 1 5613 14 discriminator 1 view .LVU3492
+ 10333 02ac 802D     		cmp	r5, #128
+ 10334 02ae 7FF631AF 		bls	.L708
+5614:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 10335              		.loc 1 5614 13 view .LVU3493
+ 10336 02b2 0E20     		movs	r0, #14
+ 10337 02b4 AFE1     		b	.L700
+ 10338              	.L797:
+ 10339 02b6 00BF     		.align	2
+ 10340              	.L796:
+ 10341 02b8 00000000 		.word	.LANCHOR2
+ 10342 02bc 0A00FFFF 		.word	-65526
+ 10343 02c0 FFFFFE0F 		.word	268369919
+ 10344 02c4 00000000 		.word	.LANCHOR4
+ARM GAS  /tmp/cc5lWXRL.s 			page 341
+
+
+ 10345 02c8 00000000 		.word	.LANCHOR5
+ 10346              	.LVL1188:
+ 10347              	.L723:
+5617:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10348              		.loc 1 5617 24 view .LVU3494
+ 10349 02cc CDF818C0 		str	ip, [sp, #24]
+ 10350 02d0 7546     		mov	r5, lr
+ 10351 02d2 CDF81490 		str	r9, [sp, #20]
+ 10352 02d6 039C     		ldr	r4, [sp, #12]
+ 10353              	.LVL1189:
+5617:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10354              		.loc 1 5617 24 view .LVU3495
+ 10355 02d8 DDF81090 		ldr	r9, [sp, #16]
+ 10356              	.LVL1190:
+5617:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10357              		.loc 1 5617 24 view .LVU3496
+ 10358 02dc 0493     		str	r3, [sp, #16]
+ 10359              	.LVL1191:
+5617:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10360              		.loc 1 5617 4 is_stmt 1 view .LVU3497
+5617:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10361              		.loc 1 5617 24 is_stmt 0 view .LVU3498
+ 10362 02de 40F6F572 		movw	r2, #4085
+ 10363 02e2 1946     		mov	r1, r3
+ 10364 02e4 BBF1010F 		cmp	fp, #1
+ 10365 02e8 14BF     		ite	ne
+ 10366 02ea 0023     		movne	r3, #0
+ 10367              	.LVL1192:
+5617:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10368              		.loc 1 5617 24 view .LVU3499
+ 10369 02ec 0123     		moveq	r3, #1
+ 10370 02ee 9142     		cmp	r1, r2
+ 10371 02f0 98BF     		it	ls
+ 10372 02f2 0023     		movls	r3, #0
+5617:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10373              		.loc 1 5617 7 view .LVU3500
+ 10374 02f4 002B     		cmp	r3, #0
+ 10375 02f6 40F0BF81 		bne	.L770
+ 10376              	.LVL1193:
+5620:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (1);
+ 10377              		.loc 1 5620 4 is_stmt 1 view .LVU3501
+5628:Middlewares/Third_Party/FatFs/src/ff.c **** 		mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */
+ 10378              		.loc 1 5628 3 view .LVU3502
+ 10379 02fa BDF82E20 		ldrh	r2, [sp, #46]
+ 10380 02fe 0021     		movs	r1, #0
+ 10381              	.LVL1194:
+5628:Middlewares/Third_Party/FatFs/src/ff.c **** 		mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */
+ 10382              		.loc 1 5628 3 is_stmt 0 view .LVU3503
+ 10383 0300 3046     		mov	r0, r6
+ 10384 0302 FFF7FEFF 		bl	mem_set
+ 10385              	.LVL1195:
+5629:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_BytsPerSec, ss);				/* Sector size [byte] */
+ 10386              		.loc 1 5629 3 is_stmt 1 view .LVU3504
+ 10387 0306 0B22     		movs	r2, #11
+ 10388 0308 D049     		ldr	r1, .L798
+ 10389 030a 3046     		mov	r0, r6
+ 10390 030c FFF7FEFF 		bl	mem_cpy
+ARM GAS  /tmp/cc5lWXRL.s 			page 342
+
+
+ 10391              	.LVL1196:
+5630:Middlewares/Third_Party/FatFs/src/ff.c **** 		buf[BPB_SecPerClus] = (BYTE)pau;				/* Cluster size [sector] */
+ 10392              		.loc 1 5630 3 view .LVU3505
+ 10393 0310 BDF82E10 		ldrh	r1, [sp, #46]
+ 10394 0314 06F10B00 		add	r0, r6, #11
+ 10395 0318 FFF7FEFF 		bl	st_word
+ 10396              	.LVL1197:
+5631:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv);	/* Size of reserved area */
+ 10397              		.loc 1 5631 3 view .LVU3506
+5631:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv);	/* Size of reserved area */
+ 10398              		.loc 1 5631 23 is_stmt 0 view .LVU3507
+ 10399 031c 86F80DA0 		strb	r10, [r6, #13]
+5632:Middlewares/Third_Party/FatFs/src/ff.c **** 		buf[BPB_NumFATs] = (BYTE)n_fats;				/* Number of FATs */
+ 10400              		.loc 1 5632 3 is_stmt 1 view .LVU3508
+ 10401 0320 A9B2     		uxth	r1, r5
+ 10402 0322 06F10E00 		add	r0, r6, #14
+ 10403 0326 FFF7FEFF 		bl	st_word
+ 10404              	.LVL1198:
+5633:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir));	/* Number of root direc
+ 10405              		.loc 1 5633 3 view .LVU3509
+5633:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir));	/* Number of root direc
+ 10406              		.loc 1 5633 20 is_stmt 0 view .LVU3510
+ 10407 032a 0123     		movs	r3, #1
+ 10408 032c 3374     		strb	r3, [r6, #16]
+5634:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (sz_vol < 0x10000) {
+ 10409              		.loc 1 5634 3 is_stmt 1 view .LVU3511
+ 10410 032e 06F11100 		add	r0, r6, #17
+ 10411 0332 BBF1030F 		cmp	fp, #3
+ 10412 0336 7DD0     		beq	.L789
+ 10413 0338 4FF40071 		mov	r1, #512
+ 10414              	.L727:
+5634:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (sz_vol < 0x10000) {
+ 10415              		.loc 1 5634 3 is_stmt 0 discriminator 4 view .LVU3512
+ 10416 033c FFF7FEFF 		bl	st_word
+ 10417              	.LVL1199:
+5635:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BPB_TotSec16, (WORD)sz_vol);	/* Volume size in 16-bit LBA */
+ 10418              		.loc 1 5635 3 is_stmt 1 discriminator 4 view .LVU3513
+5635:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BPB_TotSec16, (WORD)sz_vol);	/* Volume size in 16-bit LBA */
+ 10419              		.loc 1 5635 14 is_stmt 0 discriminator 4 view .LVU3514
+ 10420 0340 0999     		ldr	r1, [sp, #36]
+5635:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BPB_TotSec16, (WORD)sz_vol);	/* Volume size in 16-bit LBA */
+ 10421              		.loc 1 5635 6 discriminator 4 view .LVU3515
+ 10422 0342 B1F5803F 		cmp	r1, #65536
+ 10423 0346 77D2     		bcs	.L728
+5636:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 10424              		.loc 1 5636 4 is_stmt 1 view .LVU3516
+ 10425 0348 89B2     		uxth	r1, r1
+ 10426 034a 06F11300 		add	r0, r6, #19
+ 10427 034e FFF7FEFF 		bl	st_word
+ 10428              	.LVL1200:
+ 10429              	.L729:
+5640:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_SecPerTrk, 63);				/* Number of sectors per track (for int13) */
+ 10430              		.loc 1 5640 3 view .LVU3517
+5640:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_SecPerTrk, 63);				/* Number of sectors per track (for int13) */
+ 10431              		.loc 1 5640 18 is_stmt 0 view .LVU3518
+ 10432 0352 F823     		movs	r3, #248
+ 10433 0354 7375     		strb	r3, [r6, #21]
+ARM GAS  /tmp/cc5lWXRL.s 			page 343
+
+
+5641:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_word(buf + BPB_NumHeads, 255);				/* Number of heads (for int13) */
+ 10434              		.loc 1 5641 3 is_stmt 1 view .LVU3519
+ 10435 0356 3F21     		movs	r1, #63
+ 10436 0358 06F11800 		add	r0, r6, #24
+ 10437 035c FFF7FEFF 		bl	st_word
+ 10438              	.LVL1201:
+5642:Middlewares/Third_Party/FatFs/src/ff.c **** 		st_dword(buf + BPB_HiddSec, b_vol);				/* Volume offset in the physical drive [sector] */
+ 10439              		.loc 1 5642 3 view .LVU3520
+ 10440 0360 FF21     		movs	r1, #255
+ 10441 0362 06F11A00 		add	r0, r6, #26
+ 10442 0366 FFF7FEFF 		bl	st_word
+ 10443              	.LVL1202:
+5643:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (fmt == FS_FAT32) {
+ 10444              		.loc 1 5643 3 view .LVU3521
+ 10445 036a 0099     		ldr	r1, [sp]
+ 10446 036c 06F11C00 		add	r0, r6, #28
+ 10447 0370 FFF7FEFF 		bl	st_dword
+ 10448              	.LVL1203:
+5644:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BS_VolID32, GET_FATTIME());	/* VSN */
+ 10449              		.loc 1 5644 3 view .LVU3522
+5644:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BS_VolID32, GET_FATTIME());	/* VSN */
+ 10450              		.loc 1 5644 6 is_stmt 0 view .LVU3523
+ 10451 0374 BBF1030F 		cmp	fp, #3
+ 10452 0378 63D0     		beq	.L790
+5654:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BPB_FATSz16, (WORD)sz_fat);	/* FAT size [sector] */
+ 10453              		.loc 1 5654 4 is_stmt 1 view .LVU3524
+ 10454 037a FFF7FEFF 		bl	get_fattime
+ 10455              	.LVL1204:
+ 10456 037e 0146     		mov	r1, r0
+ 10457 0380 06F12700 		add	r0, r6, #39
+ 10458 0384 FFF7FEFF 		bl	st_dword
+ 10459              	.LVL1205:
+5655:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BS_DrvNum] = 0x80;						/* Drive number (for int13) */
+ 10460              		.loc 1 5655 4 view .LVU3525
+ 10461 0388 1FFA88F1 		uxth	r1, r8
+ 10462 038c 06F11600 		add	r0, r6, #22
+ 10463 0390 FFF7FEFF 		bl	st_word
+ 10464              	.LVL1206:
+5656:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BS_BootSig] = 0x29;						/* Extended boot signature */
+ 10465              		.loc 1 5656 4 view .LVU3526
+5656:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BS_BootSig] = 0x29;						/* Extended boot signature */
+ 10466              		.loc 1 5656 19 is_stmt 0 view .LVU3527
+ 10467 0394 8023     		movs	r3, #128
+ 10468 0396 86F82430 		strb	r3, [r6, #36]
+5657:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_cpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+ 10469              		.loc 1 5657 4 is_stmt 1 view .LVU3528
+5657:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_cpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+ 10470              		.loc 1 5657 20 is_stmt 0 view .LVU3529
+ 10471 039a 2923     		movs	r3, #41
+ 10472 039c 86F82630 		strb	r3, [r6, #38]
+5658:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 10473              		.loc 1 5658 4 is_stmt 1 view .LVU3530
+ 10474 03a0 1322     		movs	r2, #19
+ 10475 03a2 AB49     		ldr	r1, .L798+4
+ 10476 03a4 06F12B00 		add	r0, r6, #43
+ 10477 03a8 FFF7FEFF 		bl	mem_cpy
+ 10478              	.LVL1207:
+ARM GAS  /tmp/cc5lWXRL.s 			page 344
+
+
+ 10479              	.L731:
+5660:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the VBR sector 
+ 10480              		.loc 1 5660 3 view .LVU3531
+ 10481 03ac 06F5FF73 		add	r3, r6, #510
+ 10482 03b0 0393     		str	r3, [sp, #12]
+ 10483              	.LVL1208:
+5660:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the VBR sector 
+ 10484              		.loc 1 5660 3 is_stmt 0 view .LVU3532
+ 10485 03b2 4AF65521 		movw	r1, #43605
+ 10486 03b6 1846     		mov	r0, r3
+ 10487 03b8 FFF7FEFF 		bl	st_word
+ 10488              	.LVL1209:
+5661:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10489              		.loc 1 5661 3 is_stmt 1 view .LVU3533
+5661:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10490              		.loc 1 5661 7 is_stmt 0 view .LVU3534
+ 10491 03bc 0123     		movs	r3, #1
+ 10492 03be 009A     		ldr	r2, [sp]
+ 10493 03c0 3146     		mov	r1, r6
+ 10494 03c2 2046     		mov	r0, r4
+ 10495 03c4 FFF7FEFF 		bl	disk_write
+ 10496              	.LVL1210:
+5661:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10497              		.loc 1 5661 6 view .LVU3535
+ 10498 03c8 0028     		cmp	r0, #0
+ 10499 03ca 40F05781 		bne	.L772
+5664:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(pdrv, buf, b_vol + 6, 1);		/* Write backup VBR (VBR + 6) */
+ 10500              		.loc 1 5664 3 is_stmt 1 view .LVU3536
+5664:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(pdrv, buf, b_vol + 6, 1);		/* Write backup VBR (VBR + 6) */
+ 10501              		.loc 1 5664 6 is_stmt 0 view .LVU3537
+ 10502 03ce BBF1030F 		cmp	fp, #3
+ 10503 03d2 5ED0     		beq	.L791
+ 10504              	.LVL1211:
+ 10505              	.L732:
+5677:Middlewares/Third_Party/FatFs/src/ff.c **** 		sect = b_fat;		/* FAT start sector */
+ 10506              		.loc 1 5677 3 is_stmt 1 view .LVU3538
+ 10507 03d4 3A46     		mov	r2, r7
+ 10508 03d6 0021     		movs	r1, #0
+ 10509 03d8 3046     		mov	r0, r6
+ 10510 03da FFF7FEFF 		bl	mem_set
+ 10511              	.LVL1212:
+5678:Middlewares/Third_Party/FatFs/src/ff.c **** 		for (i = 0; i < n_fats; i++) {			/* Initialize FATs each */
+ 10512              		.loc 1 5678 3 view .LVU3539
+5679:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10513              		.loc 1 5679 3 view .LVU3540
+ 10514              	.L733:
+5679:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10515              		.loc 1 5679 15 discriminator 1 view .LVU3541
+5679:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10516              		.loc 1 5679 3 is_stmt 0 discriminator 1 view .LVU3542
+ 10517 03de 019B     		ldr	r3, [sp, #4]
+ 10518 03e0 002B     		cmp	r3, #0
+ 10519 03e2 00F08980 		beq	.L738
+5697:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+ 10520              		.loc 1 5697 3 is_stmt 1 view .LVU3543
+5697:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+ 10521              		.loc 1 5697 35 is_stmt 0 view .LVU3544
+ARM GAS  /tmp/cc5lWXRL.s 			page 345
+
+
+ 10522 03e6 BBF1030F 		cmp	fp, #3
+ 10523 03ea 00F0C080 		beq	.L792
+ 10524 03ee 069F     		ldr	r7, [sp, #24]
+ 10525 03f0 DDF81480 		ldr	r8, [sp, #20]
+ 10526              	.LVL1213:
+ 10527              	.L740:
+5698:Middlewares/Third_Party/FatFs/src/ff.c **** 			n = (nsect > sz_buf) ? sz_buf : nsect;
+ 10528              		.loc 1 5698 3 is_stmt 1 view .LVU3545
+5699:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+ 10529              		.loc 1 5699 4 view .LVU3546
+5699:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+ 10530              		.loc 1 5699 6 is_stmt 0 view .LVU3547
+ 10531 03f4 3D46     		mov	r5, r7
+ 10532 03f6 4F45     		cmp	r7, r9
+ 10533 03f8 28BF     		it	cs
+ 10534 03fa 4D46     		movcs	r5, r9
+ 10535              	.LVL1214:
+5700:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += n; nsect -= n;
+ 10536              		.loc 1 5700 4 is_stmt 1 view .LVU3548
+5700:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += n; nsect -= n;
+ 10537              		.loc 1 5700 8 is_stmt 0 view .LVU3549
+ 10538 03fc 2B46     		mov	r3, r5
+ 10539 03fe 4246     		mov	r2, r8
+ 10540 0400 3146     		mov	r1, r6
+ 10541 0402 2046     		mov	r0, r4
+ 10542 0404 FFF7FEFF 		bl	disk_write
+ 10543              	.LVL1215:
+5700:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += n; nsect -= n;
+ 10544              		.loc 1 5700 7 view .LVU3550
+ 10545 0408 0028     		cmp	r0, #0
+ 10546 040a 40F03B81 		bne	.L775
+5701:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (nsect);
+ 10547              		.loc 1 5701 4 is_stmt 1 view .LVU3551
+5701:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (nsect);
+ 10548              		.loc 1 5701 9 is_stmt 0 view .LVU3552
+ 10549 040e A844     		add	r8, r8, r5
+ 10550              	.LVL1216:
+5701:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (nsect);
+ 10551              		.loc 1 5701 15 is_stmt 1 view .LVU3553
+5702:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 10552              		.loc 1 5702 11 view .LVU3554
+5702:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 10553              		.loc 1 5702 3 is_stmt 0 view .LVU3555
+ 10554 0410 7F1B     		subs	r7, r7, r5
+ 10555              	.LVL1217:
+5702:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 10556              		.loc 1 5702 3 view .LVU3556
+ 10557 0412 EFD1     		bne	.L740
+5706:Middlewares/Third_Party/FatFs/src/ff.c **** 		sys = 0x07;			/* HPFS/NTFS/exFAT */
+ 10558              		.loc 1 5706 2 is_stmt 1 view .LVU3557
+5709:Middlewares/Third_Party/FatFs/src/ff.c **** 			sys = 0x0C;		/* FAT32X */
+ 10559              		.loc 1 5709 3 view .LVU3558
+5709:Middlewares/Third_Party/FatFs/src/ff.c **** 			sys = 0x0C;		/* FAT32X */
+ 10560              		.loc 1 5709 6 is_stmt 0 view .LVU3559
+ 10561 0414 BBF1030F 		cmp	fp, #3
+ 10562 0418 00F0B080 		beq	.L776
+5712:Middlewares/Third_Party/FatFs/src/ff.c **** 				sys = 0x06;	/* FAT12/16 (>=64KS) */
+ARM GAS  /tmp/cc5lWXRL.s 			page 346
+
+
+ 10563              		.loc 1 5712 4 is_stmt 1 view .LVU3560
+5712:Middlewares/Third_Party/FatFs/src/ff.c **** 				sys = 0x06;	/* FAT12/16 (>=64KS) */
+ 10564              		.loc 1 5712 15 is_stmt 0 view .LVU3561
+ 10565 041c 099B     		ldr	r3, [sp, #36]
+5712:Middlewares/Third_Party/FatFs/src/ff.c **** 				sys = 0x06;	/* FAT12/16 (>=64KS) */
+ 10566              		.loc 1 5712 7 view .LVU3562
+ 10567 041e B3F5803F 		cmp	r3, #65536
+ 10568 0422 80F0F080 		bcs	.L777
+5715:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10569              		.loc 1 5715 5 is_stmt 1 view .LVU3563
+5715:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10570              		.loc 1 5715 9 is_stmt 0 view .LVU3564
+ 10571 0426 BBF1020F 		cmp	fp, #2
+ 10572 042a 00F0A480 		beq	.L793
+ 10573 042e 4FF00108 		mov	r8, #1
+ 10574              	.LVL1218:
+5715:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10575              		.loc 1 5715 9 view .LVU3565
+ 10576 0432 A5E0     		b	.L741
+ 10577              	.LVL1219:
+ 10578              	.L789:
+5634:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (sz_vol < 0x10000) {
+ 10579              		.loc 1 5634 3 view .LVU3566
+ 10580 0434 0021     		movs	r1, #0
+ 10581 0436 81E7     		b	.L727
+ 10582              	.L728:
+5638:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 10583              		.loc 1 5638 4 is_stmt 1 view .LVU3567
+ 10584 0438 06F12000 		add	r0, r6, #32
+ 10585 043c FFF7FEFF 		bl	st_dword
+ 10586              	.LVL1220:
+ 10587 0440 87E7     		b	.L729
+ 10588              	.L790:
+5645:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_FATSz32, sz_fat);		/* FAT size [sector] */
+ 10589              		.loc 1 5645 4 view .LVU3568
+ 10590 0442 FFF7FEFF 		bl	get_fattime
+ 10591              	.LVL1221:
+ 10592 0446 0146     		mov	r1, r0
+ 10593 0448 06F14300 		add	r0, r6, #67
+ 10594 044c FFF7FEFF 		bl	st_dword
+ 10595              	.LVL1222:
+5646:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + BPB_RootClus32, 2);			/* Root directory cluster # (2) */
+ 10596              		.loc 1 5646 4 view .LVU3569
+ 10597 0450 4146     		mov	r1, r8
+ 10598 0452 06F12400 		add	r0, r6, #36
+ 10599 0456 FFF7FEFF 		bl	st_dword
+ 10600              	.LVL1223:
+5647:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BPB_FSInfo32, 1);				/* Offset of FSINFO sector (VBR + 1) */
+ 10601              		.loc 1 5647 4 view .LVU3570
+ 10602 045a 0221     		movs	r1, #2
+ 10603 045c 06F12C00 		add	r0, r6, #44
+ 10604 0460 FFF7FEFF 		bl	st_dword
+ 10605              	.LVL1224:
+5648:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BPB_BkBootSec32, 6);			/* Offset of backup VBR (VBR + 6) */
+ 10606              		.loc 1 5648 4 view .LVU3571
+ 10607 0464 0121     		movs	r1, #1
+ 10608 0466 06F13000 		add	r0, r6, #48
+ARM GAS  /tmp/cc5lWXRL.s 			page 347
+
+
+ 10609 046a FFF7FEFF 		bl	st_word
+ 10610              	.LVL1225:
+5649:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BS_DrvNum32] = 0x80;					/* Drive number (for int13) */
+ 10611              		.loc 1 5649 4 view .LVU3572
+ 10612 046e 0621     		movs	r1, #6
+ 10613 0470 06F13200 		add	r0, r6, #50
+ 10614 0474 FFF7FEFF 		bl	st_word
+ 10615              	.LVL1226:
+5650:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BS_BootSig32] = 0x29;					/* Extended boot signature */
+ 10616              		.loc 1 5650 4 view .LVU3573
+5650:Middlewares/Third_Party/FatFs/src/ff.c **** 			buf[BS_BootSig32] = 0x29;					/* Extended boot signature */
+ 10617              		.loc 1 5650 21 is_stmt 0 view .LVU3574
+ 10618 0478 8023     		movs	r3, #128
+ 10619 047a 86F84030 		strb	r3, [r6, #64]
+5651:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_cpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+ 10620              		.loc 1 5651 4 is_stmt 1 view .LVU3575
+5651:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_cpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+ 10621              		.loc 1 5651 22 is_stmt 0 view .LVU3576
+ 10622 047e 2923     		movs	r3, #41
+ 10623 0480 86F84230 		strb	r3, [r6, #66]
+5652:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 10624              		.loc 1 5652 4 is_stmt 1 view .LVU3577
+ 10625 0484 1322     		movs	r2, #19
+ 10626 0486 7349     		ldr	r1, .L798+8
+ 10627 0488 06F14700 		add	r0, r6, #71
+ 10628 048c FFF7FEFF 		bl	mem_cpy
+ 10629              	.LVL1227:
+ 10630 0490 8CE7     		b	.L731
+ 10631              	.LVL1228:
+ 10632              	.L791:
+5665:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, ss);
+ 10633              		.loc 1 5665 4 view .LVU3578
+ 10634 0492 0123     		movs	r3, #1
+ 10635 0494 009D     		ldr	r5, [sp]
+ 10636              	.LVL1229:
+5665:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, ss);
+ 10637              		.loc 1 5665 4 is_stmt 0 view .LVU3579
+ 10638 0496 AA1D     		adds	r2, r5, #6
+ 10639 0498 3146     		mov	r1, r6
+ 10640 049a 2046     		mov	r0, r4
+ 10641 049c FFF7FEFF 		bl	disk_write
+ 10642              	.LVL1230:
+5666:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + FSI_LeadSig, 0x41615252);
+ 10643              		.loc 1 5666 4 is_stmt 1 view .LVU3580
+ 10644 04a0 BDF82E20 		ldrh	r2, [sp, #46]
+ 10645 04a4 0021     		movs	r1, #0
+ 10646 04a6 3046     		mov	r0, r6
+ 10647 04a8 FFF7FEFF 		bl	mem_set
+ 10648              	.LVL1231:
+5667:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + FSI_StrucSig, 0x61417272);
+ 10649              		.loc 1 5667 4 view .LVU3581
+ 10650 04ac 6A49     		ldr	r1, .L798+12
+ 10651 04ae 3046     		mov	r0, r6
+ 10652 04b0 FFF7FEFF 		bl	st_dword
+ 10653              	.LVL1232:
+5668:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
+ 10654              		.loc 1 5668 4 view .LVU3582
+ARM GAS  /tmp/cc5lWXRL.s 			page 348
+
+
+ 10655 04b4 6949     		ldr	r1, .L798+16
+ 10656 04b6 06F5F270 		add	r0, r6, #484
+ 10657 04ba FFF7FEFF 		bl	st_dword
+ 10658              	.LVL1233:
+5669:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(buf + FSI_Nxt_Free, 2);			/* Last allocated cluster# */
+ 10659              		.loc 1 5669 4 view .LVU3583
+ 10660 04be 049B     		ldr	r3, [sp, #16]
+ 10661 04c0 591E     		subs	r1, r3, #1
+ 10662 04c2 06F5F470 		add	r0, r6, #488
+ 10663 04c6 FFF7FEFF 		bl	st_dword
+ 10664              	.LVL1234:
+5670:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BS_55AA, 0xAA55);
+ 10665              		.loc 1 5670 4 view .LVU3584
+ 10666 04ca 0221     		movs	r1, #2
+ 10667 04cc 06F5F670 		add	r0, r6, #492
+ 10668 04d0 FFF7FEFF 		bl	st_dword
+ 10669              	.LVL1235:
+5671:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(pdrv, buf, b_vol + 7, 1);		/* Write backup FSINFO (VBR + 7) */
+ 10670              		.loc 1 5671 4 view .LVU3585
+ 10671 04d4 4AF65521 		movw	r1, #43605
+ 10672 04d8 0398     		ldr	r0, [sp, #12]
+ 10673 04da FFF7FEFF 		bl	st_word
+ 10674              	.LVL1236:
+5672:Middlewares/Third_Party/FatFs/src/ff.c **** 			disk_write(pdrv, buf, b_vol + 1, 1);		/* Write original FSINFO (VBR + 1) */
+ 10675              		.loc 1 5672 4 view .LVU3586
+ 10676 04de 0123     		movs	r3, #1
+ 10677 04e0 EA1D     		adds	r2, r5, #7
+ 10678 04e2 3146     		mov	r1, r6
+ 10679 04e4 2046     		mov	r0, r4
+ 10680 04e6 FFF7FEFF 		bl	disk_write
+ 10681              	.LVL1237:
+5673:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 10682              		.loc 1 5673 4 view .LVU3587
+ 10683 04ea 0123     		movs	r3, #1
+ 10684 04ec EA18     		adds	r2, r5, r3
+ 10685 04ee 3146     		mov	r1, r6
+ 10686 04f0 2046     		mov	r0, r4
+ 10687 04f2 FFF7FEFF 		bl	disk_write
+ 10688              	.LVL1238:
+ 10689 04f6 6DE7     		b	.L732
+ 10690              	.LVL1239:
+ 10691              	.L738:
+5680:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(buf + 0, 0xFFFFFFF8);	/* Entry 0 */
+ 10692              		.loc 1 5680 4 view .LVU3588
+5680:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(buf + 0, 0xFFFFFFF8);	/* Entry 0 */
+ 10693              		.loc 1 5680 7 is_stmt 0 view .LVU3589
+ 10694 04f8 BBF1030F 		cmp	fp, #3
+ 10695 04fc 24D0     		beq	.L794
+5685:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10696              		.loc 1 5685 5 is_stmt 1 view .LVU3590
+ 10697 04fe BBF1010F 		cmp	fp, #1
+ 10698 0502 32D0     		beq	.L795
+ 10699 0504 6FF00701 		mvn	r1, #7
+ 10700              	.L736:
+5685:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10701              		.loc 1 5685 5 is_stmt 0 discriminator 4 view .LVU3591
+ 10702 0508 3046     		mov	r0, r6
+ARM GAS  /tmp/cc5lWXRL.s 			page 349
+
+
+ 10703 050a FFF7FEFF 		bl	st_dword
+ 10704              	.LVL1240:
+ 10705              	.L735:
+5685:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10706              		.loc 1 5685 5 view .LVU3592
+ 10707 050e 4546     		mov	r5, r8
+ 10708              	.L737:
+ 10709              	.LVL1241:
+5688:Middlewares/Third_Party/FatFs/src/ff.c **** 				n = (nsect > sz_buf) ? sz_buf : nsect;
+ 10710              		.loc 1 5688 4 is_stmt 1 view .LVU3593
+5689:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+ 10711              		.loc 1 5689 5 view .LVU3594
+5689:Middlewares/Third_Party/FatFs/src/ff.c **** 				if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+ 10712              		.loc 1 5689 7 is_stmt 0 view .LVU3595
+ 10713 0510 2F46     		mov	r7, r5
+ 10714 0512 4D45     		cmp	r5, r9
+ 10715 0514 28BF     		it	cs
+ 10716 0516 4F46     		movcs	r7, r9
+ 10717              	.LVL1242:
+5690:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_set(buf, 0, ss);
+ 10718              		.loc 1 5690 5 is_stmt 1 view .LVU3596
+5690:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_set(buf, 0, ss);
+ 10719              		.loc 1 5690 9 is_stmt 0 view .LVU3597
+ 10720 0518 3B46     		mov	r3, r7
+ 10721 051a 059A     		ldr	r2, [sp, #20]
+ 10722 051c 3146     		mov	r1, r6
+ 10723 051e 2046     		mov	r0, r4
+ 10724 0520 FFF7FEFF 		bl	disk_write
+ 10725              	.LVL1243:
+5690:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_set(buf, 0, ss);
+ 10726              		.loc 1 5690 8 view .LVU3598
+ 10727 0524 0028     		cmp	r0, #0
+ 10728 0526 40F0AB80 		bne	.L774
+5691:Middlewares/Third_Party/FatFs/src/ff.c **** 				sect += n; nsect -= n;
+ 10729              		.loc 1 5691 5 is_stmt 1 view .LVU3599
+ 10730 052a BDF82E20 		ldrh	r2, [sp, #46]
+ 10731 052e 0021     		movs	r1, #0
+ 10732 0530 3046     		mov	r0, r6
+ 10733 0532 FFF7FEFF 		bl	mem_set
+ 10734              	.LVL1244:
+5692:Middlewares/Third_Party/FatFs/src/ff.c **** 			} while (nsect);
+ 10735              		.loc 1 5692 5 view .LVU3600
+5692:Middlewares/Third_Party/FatFs/src/ff.c **** 			} while (nsect);
+ 10736              		.loc 1 5692 10 is_stmt 0 view .LVU3601
+ 10737 0536 059B     		ldr	r3, [sp, #20]
+ 10738 0538 3B44     		add	r3, r3, r7
+ 10739 053a 0593     		str	r3, [sp, #20]
+ 10740              	.LVL1245:
+5692:Middlewares/Third_Party/FatFs/src/ff.c **** 			} while (nsect);
+ 10741              		.loc 1 5692 16 is_stmt 1 view .LVU3602
+5693:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 10742              		.loc 1 5693 12 view .LVU3603
+5693:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 10743              		.loc 1 5693 4 is_stmt 0 view .LVU3604
+ 10744 053c ED1B     		subs	r5, r5, r7
+ 10745              	.LVL1246:
+5693:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ARM GAS  /tmp/cc5lWXRL.s 			page 350
+
+
+ 10746              		.loc 1 5693 4 view .LVU3605
+ 10747 053e E7D1     		bne	.L737
+5679:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10748              		.loc 1 5679 27 is_stmt 1 discriminator 2 view .LVU3606
+5679:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10749              		.loc 1 5679 28 is_stmt 0 discriminator 2 view .LVU3607
+ 10750 0540 019B     		ldr	r3, [sp, #4]
+ 10751              	.LVL1247:
+5679:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10752              		.loc 1 5679 28 discriminator 2 view .LVU3608
+ 10753 0542 0133     		adds	r3, r3, #1
+ 10754 0544 0193     		str	r3, [sp, #4]
+ 10755              	.LVL1248:
+5679:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (fmt == FS_FAT32) {
+ 10756              		.loc 1 5679 28 discriminator 2 view .LVU3609
+ 10757 0546 4AE7     		b	.L733
+ 10758              	.LVL1249:
+ 10759              	.L794:
+5681:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(buf + 4, 0xFFFFFFFF);	/* Entry 1 */
+ 10760              		.loc 1 5681 5 is_stmt 1 view .LVU3610
+ 10761 0548 6FF00701 		mvn	r1, #7
+ 10762 054c 3046     		mov	r0, r6
+ 10763 054e FFF7FEFF 		bl	st_dword
+ 10764              	.LVL1250:
+5682:Middlewares/Third_Party/FatFs/src/ff.c **** 				st_dword(buf + 8, 0x0FFFFFFF);	/* Entry 2 (root directory) */
+ 10765              		.loc 1 5682 5 view .LVU3611
+ 10766 0552 4FF0FF31 		mov	r1, #-1
+ 10767 0556 301D     		adds	r0, r6, #4
+ 10768 0558 FFF7FEFF 		bl	st_dword
+ 10769              	.LVL1251:
+5683:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 10770              		.loc 1 5683 5 view .LVU3612
+ 10771 055c 6FF07041 		mvn	r1, #-268435456
+ 10772 0560 06F10800 		add	r0, r6, #8
+ 10773 0564 FFF7FEFF 		bl	st_dword
+ 10774              	.LVL1252:
+ 10775 0568 D1E7     		b	.L735
+ 10776              	.LVL1253:
+ 10777              	.L795:
+5685:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10778              		.loc 1 5685 5 is_stmt 0 view .LVU3613
+ 10779 056a 3D49     		ldr	r1, .L798+20
+ 10780 056c CCE7     		b	.L736
+ 10781              	.L792:
+5697:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+ 10782              		.loc 1 5697 35 view .LVU3614
+ 10783 056e 5746     		mov	r7, r10
+ 10784 0570 DDF81480 		ldr	r8, [sp, #20]
+ 10785              	.LVL1254:
+5697:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+ 10786              		.loc 1 5697 35 view .LVU3615
+ 10787 0574 3EE7     		b	.L740
+ 10788              	.LVL1255:
+ 10789              	.L793:
+5715:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10790              		.loc 1 5715 9 view .LVU3616
+ 10791 0576 4FF00408 		mov	r8, #4
+ARM GAS  /tmp/cc5lWXRL.s 			page 351
+
+
+ 10792              	.LVL1256:
+5715:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+ 10793              		.loc 1 5715 9 view .LVU3617
+ 10794 057a 01E0     		b	.L741
+ 10795              	.LVL1257:
+ 10796              	.L776:
+5710:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+ 10797              		.loc 1 5710 8 view .LVU3618
+ 10798 057c 4FF00C08 		mov	r8, #12
+ 10799              	.LVL1258:
+ 10800              	.L741:
+5721:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Update system ID in the partition table */
+ 10801              		.loc 1 5721 2 is_stmt 1 view .LVU3619
+5727:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, ss);
+ 10802              		.loc 1 5727 3 view .LVU3620
+5727:Middlewares/Third_Party/FatFs/src/ff.c **** 			mem_set(buf, 0, ss);
+ 10803              		.loc 1 5727 6 is_stmt 0 view .LVU3621
+ 10804 0580 029B     		ldr	r3, [sp, #8]
+ 10805 0582 C3BB     		cbnz	r3, .L742
+5728:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_word(buf + BS_55AA, 0xAA55);		/* MBR signature */
+ 10806              		.loc 1 5728 4 is_stmt 1 view .LVU3622
+ 10807 0584 BDF82E20 		ldrh	r2, [sp, #46]
+ 10808 0588 0021     		movs	r1, #0
+ 10809 058a 3046     		mov	r0, r6
+ 10810 058c FFF7FEFF 		bl	mem_set
+ 10811              	.LVL1259:
+5729:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte = buf + MBR_Table;				/* Create partition table for single partition in the drive */
+ 10812              		.loc 1 5729 4 view .LVU3623
+ 10813 0590 4AF65521 		movw	r1, #43605
+ 10814 0594 0398     		ldr	r0, [sp, #12]
+ 10815 0596 FFF7FEFF 		bl	st_word
+ 10816              	.LVL1260:
+5730:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_Boot] = 0;					/* Boot indicator */
+ 10817              		.loc 1 5730 4 view .LVU3624
+5731:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_StHead] = 1;				/* Start head */
+ 10818              		.loc 1 5731 4 view .LVU3625
+5731:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_StHead] = 1;				/* Start head */
+ 10819              		.loc 1 5731 18 is_stmt 0 view .LVU3626
+ 10820 059a 0025     		movs	r5, #0
+ 10821              	.LVL1261:
+5731:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_StHead] = 1;				/* Start head */
+ 10822              		.loc 1 5731 18 view .LVU3627
+ 10823 059c 86F8BE51 		strb	r5, [r6, #446]
+5732:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_StSec] = 1;					/* Start sector */
+ 10824              		.loc 1 5732 4 is_stmt 1 view .LVU3628
+5732:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_StSec] = 1;					/* Start sector */
+ 10825              		.loc 1 5732 20 is_stmt 0 view .LVU3629
+ 10826 05a0 0127     		movs	r7, #1
+ 10827              	.LVL1262:
+5732:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_StSec] = 1;					/* Start sector */
+ 10828              		.loc 1 5732 20 view .LVU3630
+ 10829 05a2 86F8BF71 		strb	r7, [r6, #447]
+5733:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_StCyl] = 0;					/* Start cylinder */
+ 10830              		.loc 1 5733 4 is_stmt 1 view .LVU3631
+5733:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_StCyl] = 0;					/* Start cylinder */
+ 10831              		.loc 1 5733 19 is_stmt 0 view .LVU3632
+ 10832 05a6 86F8C071 		strb	r7, [r6, #448]
+ARM GAS  /tmp/cc5lWXRL.s 			page 352
+
+
+5734:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_System] = sys;				/* System type */
+ 10833              		.loc 1 5734 4 is_stmt 1 view .LVU3633
+5734:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_System] = sys;				/* System type */
+ 10834              		.loc 1 5734 19 is_stmt 0 view .LVU3634
+ 10835 05aa 86F8C151 		strb	r5, [r6, #449]
+5735:Middlewares/Third_Party/FatFs/src/ff.c **** 			n = (b_vol + sz_vol) / (63 * 255);	/* (End CHS may be invalid) */
+ 10836              		.loc 1 5735 4 is_stmt 1 view .LVU3635
+5735:Middlewares/Third_Party/FatFs/src/ff.c **** 			n = (b_vol + sz_vol) / (63 * 255);	/* (End CHS may be invalid) */
+ 10837              		.loc 1 5735 20 is_stmt 0 view .LVU3636
+ 10838 05ae 86F8C281 		strb	r8, [r6, #450]
+5736:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdHead] = 254;				/* End head */
+ 10839              		.loc 1 5736 4 is_stmt 1 view .LVU3637
+5736:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdHead] = 254;				/* End head */
+ 10840              		.loc 1 5736 15 is_stmt 0 view .LVU3638
+ 10841 05b2 099B     		ldr	r3, [sp, #36]
+ 10842 05b4 0099     		ldr	r1, [sp]
+ 10843 05b6 0B44     		add	r3, r3, r1
+5736:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdHead] = 254;				/* End head */
+ 10844              		.loc 1 5736 6 view .LVU3639
+ 10845 05b8 43F6C162 		movw	r2, #16065
+ 10846 05bc B3FBF2F3 		udiv	r3, r3, r2
+ 10847              	.LVL1263:
+5737:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdSec] = (BYTE)(n >> 2 | 63);	/* End sector */
+ 10848              		.loc 1 5737 4 is_stmt 1 view .LVU3640
+5737:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdSec] = (BYTE)(n >> 2 | 63);	/* End sector */
+ 10849              		.loc 1 5737 20 is_stmt 0 view .LVU3641
+ 10850 05c0 FE22     		movs	r2, #254
+ 10851 05c2 86F8C321 		strb	r2, [r6, #451]
+5738:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdCyl] = (BYTE)n;			/* End cylinder */
+ 10852              		.loc 1 5738 4 is_stmt 1 view .LVU3642
+5738:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdCyl] = (BYTE)n;			/* End cylinder */
+ 10853              		.loc 1 5738 30 is_stmt 0 view .LVU3643
+ 10854 05c6 9A08     		lsrs	r2, r3, #2
+5738:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdCyl] = (BYTE)n;			/* End cylinder */
+ 10855              		.loc 1 5738 21 view .LVU3644
+ 10856 05c8 42F03F02 		orr	r2, r2, #63
+5738:Middlewares/Third_Party/FatFs/src/ff.c **** 			pte[PTE_EdCyl] = (BYTE)n;			/* End cylinder */
+ 10857              		.loc 1 5738 19 view .LVU3645
+ 10858 05cc 86F8C421 		strb	r2, [r6, #452]
+5739:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(pte + PTE_StLba, b_vol);	/* Start offset in LBA */
+ 10859              		.loc 1 5739 4 is_stmt 1 view .LVU3646
+5739:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(pte + PTE_StLba, b_vol);	/* Start offset in LBA */
+ 10860              		.loc 1 5739 19 is_stmt 0 view .LVU3647
+ 10861 05d0 86F8C531 		strb	r3, [r6, #453]
+5740:Middlewares/Third_Party/FatFs/src/ff.c **** 			st_dword(pte + PTE_SizLba, sz_vol);	/* Size in sectors */
+ 10862              		.loc 1 5740 4 is_stmt 1 view .LVU3648
+ 10863 05d4 06F5E370 		add	r0, r6, #454
+ 10864 05d8 FFF7FEFF 		bl	st_dword
+ 10865              	.LVL1264:
+5741:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the MBR */
+ 10866              		.loc 1 5741 4 view .LVU3649
+ 10867 05dc 0999     		ldr	r1, [sp, #36]
+ 10868 05de 06F5E570 		add	r0, r6, #458
+ 10869 05e2 FFF7FEFF 		bl	st_dword
+ 10870              	.LVL1265:
+5742:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 10871              		.loc 1 5742 4 view .LVU3650
+ARM GAS  /tmp/cc5lWXRL.s 			page 353
+
+
+5742:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 10872              		.loc 1 5742 8 is_stmt 0 view .LVU3651
+ 10873 05e6 3B46     		mov	r3, r7
+ 10874 05e8 2A46     		mov	r2, r5
+ 10875 05ea 3146     		mov	r1, r6
+ 10876 05ec 2046     		mov	r0, r4
+ 10877 05ee FFF7FEFF 		bl	disk_write
+ 10878              	.LVL1266:
+5742:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 10879              		.loc 1 5742 7 view .LVU3652
+ 10880 05f2 0028     		cmp	r0, #0
+ 10881 05f4 48D1     		bne	.L779
+ 10882              	.LVL1267:
+ 10883              	.L742:
+5746:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10884              		.loc 1 5746 2 is_stmt 1 view .LVU3653
+5746:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10885              		.loc 1 5746 6 is_stmt 0 view .LVU3654
+ 10886 05f6 0022     		movs	r2, #0
+ 10887 05f8 1146     		mov	r1, r2
+ 10888 05fa 2046     		mov	r0, r4
+ 10889 05fc FFF7FEFF 		bl	disk_ioctl
+ 10890              	.LVL1268:
+5746:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10891              		.loc 1 5746 5 view .LVU3655
+ 10892 0600 48B1     		cbz	r0, .L700
+5746:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10893              		.loc 1 5746 55 view .LVU3656
+ 10894 0602 0120     		movs	r0, #1
+ 10895 0604 07E0     		b	.L700
+ 10896              	.LVL1269:
+ 10897              	.L777:
+5713:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 10898              		.loc 1 5713 9 view .LVU3657
+ 10899 0606 4FF00608 		mov	r8, #6
+ 10900              	.LVL1270:
+5713:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {
+ 10901              		.loc 1 5713 9 view .LVU3658
+ 10902 060a B9E7     		b	.L741
+ 10903              	.LVL1271:
+ 10904              	.L743:
+5328:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (FatFs[vol]) FatFs[vol]->fs_type = 0;	/* Clear the volume */
+ 10905              		.loc 1 5328 22 view .LVU3659
+ 10906 060c 0B20     		movs	r0, #11
+ 10907              	.LVL1272:
+5328:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (FatFs[vol]) FatFs[vol]->fs_type = 0;	/* Clear the volume */
+ 10908              		.loc 1 5328 22 view .LVU3660
+ 10909 060e 02E0     		b	.L700
+ 10910              	.LVL1273:
+ 10911              	.L744:
+5335:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+ 10912              		.loc 1 5335 32 view .LVU3661
+ 10913 0610 0320     		movs	r0, #3
+ 10914              	.LVL1274:
+5335:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+ 10915              		.loc 1 5335 32 view .LVU3662
+ 10916 0612 00E0     		b	.L700
+ARM GAS  /tmp/cc5lWXRL.s 			page 354
+
+
+ 10917              	.LVL1275:
+ 10918              	.L745:
+5336:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & 
+ 10919              		.loc 1 5336 33 view .LVU3663
+ 10920 0614 0A20     		movs	r0, #10
+ 10921              	.LVL1276:
+ 10922              	.L700:
+5749:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10923              		.loc 1 5749 1 view .LVU3664
+ 10924 0616 0DB0     		add	sp, sp, #52
+ 10925              	.LCFI113:
+ 10926              		.cfi_remember_state
+ 10927              		.cfi_def_cfa_offset 36
+ 10928              		@ sp needed
+ 10929 0618 BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 10930              	.LVL1277:
+ 10931              	.L746:
+ 10932              	.LCFI114:
+ 10933              		.cfi_restore_state
+5339:Middlewares/Third_Party/FatFs/src/ff.c **** 	if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+ 10934              		.loc 1 5339 63 view .LVU3665
+ 10935 061c 0120     		movs	r0, #1
+ 10936 061e FAE7     		b	.L700
+ 10937              	.L747:
+5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else
+ 10938              		.loc 1 5340 62 view .LVU3666
+ 10939 0620 0120     		movs	r0, #1
+ 10940 0622 F8E7     		b	.L700
+ 10941              	.L748:
+ 10942 0624 0120     		movs	r0, #1
+ 10943 0626 F6E7     		b	.L700
+ 10944              	.L749:
+5344:Middlewares/Third_Party/FatFs/src/ff.c **** 	au /= ss;	/* Cluster size in unit of sector */
+ 10945              		.loc 1 5344 72 view .LVU3667
+ 10946 0628 1320     		movs	r0, #19
+ 10947 062a F4E7     		b	.L700
+ 10948              	.L750:
+5344:Middlewares/Third_Party/FatFs/src/ff.c **** 	au /= ss;	/* Cluster size in unit of sector */
+ 10949              		.loc 1 5344 72 view .LVU3668
+ 10950 062c 1320     		movs	r0, #19
+ 10951 062e F2E7     		b	.L700
+ 10952              	.L751:
+ 10953 0630 1320     		movs	r0, #19
+ 10954 0632 F0E7     		b	.L700
+ 10955              	.LVL1278:
+ 10956              	.L752:
+5351:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10957              		.loc 1 5351 23 view .LVU3669
+ 10958 0634 0E20     		movs	r0, #14
+ 10959 0636 EEE7     		b	.L700
+ 10960              	.L753:
+5364:Middlewares/Third_Party/FatFs/src/ff.c **** 		b_vol = (opt & FM_SFD) ? 0 : 63;		/* Volume start sector */
+ 10961              		.loc 1 5364 69 view .LVU3670
+ 10962 0638 0120     		movs	r0, #1
+ 10963 063a ECE7     		b	.L700
+ 10964              	.LVL1279:
+ 10965              	.L755:
+ARM GAS  /tmp/cc5lWXRL.s 			page 355
+
+
+5366:Middlewares/Third_Party/FatFs/src/ff.c **** 		sz_vol -= b_vol;						/* Volume size */
+ 10966              		.loc 1 5366 30 view .LVU3671
+ 10967 063c 0E20     		movs	r0, #14
+ 10968 063e EAE7     		b	.L700
+ 10969              	.L756:
+5369:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 10970              		.loc 1 5369 27 view .LVU3672
+ 10971 0640 0E20     		movs	r0, #14
+ 10972 0642 E8E7     		b	.L700
+ 10973              	.L757:
+5378:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (opt & FM_FAT32) {	/* FAT32 possible? */
+ 10974              		.loc 1 5378 24 view .LVU3673
+ 10975 0644 1320     		movs	r0, #19
+ 10976 0646 E6E7     		b	.L700
+ 10977              	.LVL1280:
+ 10978              	.L760:
+5384:Middlewares/Third_Party/FatFs/src/ff.c **** 		fmt = FS_FAT16;
+ 10979              		.loc 1 5384 31 view .LVU3674
+ 10980 0648 1320     		movs	r0, #19
+ 10981 064a E4E7     		b	.L700
+ 10982              	.L799:
+ 10983              		.align	2
+ 10984              	.L798:
+ 10985 064c 00000000 		.word	.LC1
+ 10986 0650 20000000 		.word	.LC3
+ 10987 0654 0C000000 		.word	.LC2
+ 10988 0658 52526141 		.word	1096897106
+ 10989 065c 72724161 		.word	1631679090
+ 10990 0660 F8FFFF00 		.word	16777208
+ 10991              	.LVL1281:
+ 10992              	.L762:
+5564:Middlewares/Third_Party/FatFs/src/ff.c **** 			} else {				/* FAT12/16 volume */
+ 10993              		.loc 1 5564 59 view .LVU3675
+ 10994 0664 0E20     		movs	r0, #14
+ 10995 0666 D6E7     		b	.L700
+ 10996              	.LVL1282:
+ 10997              	.L764:
+5593:Middlewares/Third_Party/FatFs/src/ff.c **** 			n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau;
+ 10998              		.loc 1 5593 51 view .LVU3676
+ 10999 0668 0E20     		movs	r0, #14
+ 11000 066a D4E7     		b	.L700
+ 11001              	.LVL1283:
+ 11002              	.L765:
+5598:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 11003              		.loc 1 5598 13 view .LVU3677
+ 11004 066c 0E20     		movs	r0, #14
+ 11005 066e D2E7     		b	.L700
+ 11006              	.LVL1284:
+ 11007              	.L768:
+5610:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 11008              		.loc 1 5610 13 view .LVU3678
+ 11009 0670 0E20     		movs	r0, #14
+ 11010 0672 D0E7     		b	.L700
+ 11011              	.LVL1285:
+ 11012              	.L769:
+5614:Middlewares/Third_Party/FatFs/src/ff.c **** 				}
+ 11013              		.loc 1 5614 13 view .LVU3679
+ARM GAS  /tmp/cc5lWXRL.s 			page 356
+
+
+ 11014 0674 0E20     		movs	r0, #14
+ 11015 0676 CEE7     		b	.L700
+ 11016              	.LVL1286:
+ 11017              	.L770:
+5617:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 11018              		.loc 1 5617 54 view .LVU3680
+ 11019 0678 0E20     		movs	r0, #14
+ 11020 067a CCE7     		b	.L700
+ 11021              	.LVL1287:
+ 11022              	.L772:
+5661:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 11023              		.loc 1 5661 57 view .LVU3681
+ 11024 067c 0120     		movs	r0, #1
+ 11025 067e CAE7     		b	.L700
+ 11026              	.LVL1288:
+ 11027              	.L774:
+5690:Middlewares/Third_Party/FatFs/src/ff.c **** 				mem_set(buf, 0, ss);
+ 11028              		.loc 1 5690 64 view .LVU3682
+ 11029 0680 0120     		movs	r0, #1
+ 11030 0682 C8E7     		b	.L700
+ 11031              	.LVL1289:
+ 11032              	.L775:
+5700:Middlewares/Third_Party/FatFs/src/ff.c **** 			sect += n; nsect -= n;
+ 11033              		.loc 1 5700 63 view .LVU3683
+ 11034 0684 0120     		movs	r0, #1
+ 11035 0686 C6E7     		b	.L700
+ 11036              	.LVL1290:
+ 11037              	.L779:
+5742:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 11038              		.loc 1 5742 54 view .LVU3684
+ 11039 0688 0120     		movs	r0, #1
+ 11040 068a C4E7     		b	.L700
+ 11041              		.cfi_endproc
+ 11042              	.LFE1237:
+ 11044              		.section	.text.f_gets,"ax",%progbits
+ 11045              		.align	1
+ 11046              		.global	f_gets
+ 11047              		.syntax unified
+ 11048              		.thumb
+ 11049              		.thumb_func
+ 11050              		.fpu fpv5-d16
+ 11052              	f_gets:
+ 11053              	.LVL1291:
+ 11054              	.LFB1238:
+5835:Middlewares/Third_Party/FatFs/src/ff.c **** 	int n = 0;
+ 11055              		.loc 1 5835 1 is_stmt 1 view -0
+ 11056              		.cfi_startproc
+ 11057              		@ args = 0, pretend = 0, frame = 8
+ 11058              		@ frame_needed = 0, uses_anonymous_args = 0
+5835:Middlewares/Third_Party/FatFs/src/ff.c **** 	int n = 0;
+ 11059              		.loc 1 5835 1 is_stmt 0 view .LVU3686
+ 11060 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 11061              	.LCFI115:
+ 11062              		.cfi_def_cfa_offset 24
+ 11063              		.cfi_offset 4, -24
+ 11064              		.cfi_offset 5, -20
+ 11065              		.cfi_offset 6, -16
+ARM GAS  /tmp/cc5lWXRL.s 			page 357
+
+
+ 11066              		.cfi_offset 7, -12
+ 11067              		.cfi_offset 8, -8
+ 11068              		.cfi_offset 14, -4
+ 11069 0004 82B0     		sub	sp, sp, #8
+ 11070              	.LCFI116:
+ 11071              		.cfi_def_cfa_offset 32
+ 11072 0006 8046     		mov	r8, r0
+ 11073 0008 0E46     		mov	r6, r1
+ 11074 000a 1746     		mov	r7, r2
+5836:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR c, *p = buff;
+ 11075              		.loc 1 5836 2 is_stmt 1 view .LVU3687
+ 11076              	.LVL1292:
+5837:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE s[2];
+ 11077              		.loc 1 5837 2 view .LVU3688
+5838:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT rc;
+ 11078              		.loc 1 5838 2 view .LVU3689
+5839:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 11079              		.loc 1 5839 2 view .LVU3690
+5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+ 11080              		.loc 1 5842 2 view .LVU3691
+5837:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE s[2];
+ 11081              		.loc 1 5837 12 is_stmt 0 view .LVU3692
+ 11082 000c 0446     		mov	r4, r0
+5836:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR c, *p = buff;
+ 11083              		.loc 1 5836 6 view .LVU3693
+ 11084 000e 0025     		movs	r5, #0
+5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+ 11085              		.loc 1 5842 8 view .LVU3694
+ 11086 0010 01E0     		b	.L801
+ 11087              	.LVL1293:
+ 11088              	.L806:
+5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+ 11089              		.loc 1 5842 8 view .LVU3695
+ 11090 0012 A446     		mov	ip, r4
+ 11091              	.LVL1294:
+ 11092              	.L803:
+5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+ 11093              		.loc 1 5842 8 view .LVU3696
+ 11094 0014 6446     		mov	r4, ip
+ 11095              	.LVL1295:
+ 11096              	.L801:
+5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+ 11097              		.loc 1 5842 8 is_stmt 1 view .LVU3697
+5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+ 11098              		.loc 1 5842 17 is_stmt 0 view .LVU3698
+ 11099 0016 731E     		subs	r3, r6, #1
+5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE
+ 11100              		.loc 1 5842 8 view .LVU3699
+ 11101 0018 AB42     		cmp	r3, r5
+ 11102 001a 13DD     		ble	.L802
+5887:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (rc != 1) break;
+ 11103              		.loc 1 5887 3 is_stmt 1 view .LVU3700
+ 11104 001c 6B46     		mov	r3, sp
+ 11105 001e 0122     		movs	r2, #1
+ 11106 0020 01A9     		add	r1, sp, #4
+ 11107 0022 3846     		mov	r0, r7
+ 11108 0024 FFF7FEFF 		bl	f_read
+ARM GAS  /tmp/cc5lWXRL.s 			page 358
+
+
+ 11109              	.LVL1296:
+5888:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = s[0];
+ 11110              		.loc 1 5888 3 view .LVU3701
+5888:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = s[0];
+ 11111              		.loc 1 5888 10 is_stmt 0 view .LVU3702
+ 11112 0028 009B     		ldr	r3, [sp]
+5888:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = s[0];
+ 11113              		.loc 1 5888 6 view .LVU3703
+ 11114 002a 012B     		cmp	r3, #1
+ 11115 002c 0AD1     		bne	.L802
+5889:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 11116              		.loc 1 5889 3 is_stmt 1 view .LVU3704
+5889:Middlewares/Third_Party/FatFs/src/ff.c **** #endif
+ 11117              		.loc 1 5889 5 is_stmt 0 view .LVU3705
+ 11118 002e 9DF80430 		ldrb	r3, [sp, #4]	@ zero_extendqisi2
+ 11119              	.LVL1297:
+5891:Middlewares/Third_Party/FatFs/src/ff.c **** 		*p++ = c;
+ 11120              		.loc 1 5891 3 is_stmt 1 view .LVU3706
+5891:Middlewares/Third_Party/FatFs/src/ff.c **** 		*p++ = c;
+ 11121              		.loc 1 5891 6 is_stmt 0 view .LVU3707
+ 11122 0032 0D2B     		cmp	r3, #13
+ 11123 0034 EDD0     		beq	.L806
+5892:Middlewares/Third_Party/FatFs/src/ff.c **** 		n++;
+ 11124              		.loc 1 5892 3 is_stmt 1 view .LVU3708
+5892:Middlewares/Third_Party/FatFs/src/ff.c **** 		n++;
+ 11125              		.loc 1 5892 5 is_stmt 0 view .LVU3709
+ 11126 0036 A446     		mov	ip, r4
+ 11127              	.LVL1298:
+5892:Middlewares/Third_Party/FatFs/src/ff.c **** 		n++;
+ 11128              		.loc 1 5892 8 view .LVU3710
+ 11129 0038 0CF8013B 		strb	r3, [ip], #1
+ 11130              	.LVL1299:
+5893:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == '\n') break;		/* Break on EOL */
+ 11131              		.loc 1 5893 3 is_stmt 1 view .LVU3711
+5893:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == '\n') break;		/* Break on EOL */
+ 11132              		.loc 1 5893 4 is_stmt 0 view .LVU3712
+ 11133 003c 0135     		adds	r5, r5, #1
+ 11134              	.LVL1300:
+5894:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 11135              		.loc 1 5894 3 is_stmt 1 view .LVU3713
+5894:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+ 11136              		.loc 1 5894 6 is_stmt 0 view .LVU3714
+ 11137 003e 0A2B     		cmp	r3, #10
+ 11138 0040 E8D1     		bne	.L803
+5892:Middlewares/Third_Party/FatFs/src/ff.c **** 		n++;
+ 11139              		.loc 1 5892 5 view .LVU3715
+ 11140 0042 6446     		mov	r4, ip
+ 11141              	.LVL1301:
+ 11142              	.L802:
+5896:Middlewares/Third_Party/FatFs/src/ff.c **** 	return n ? buff : 0;			/* When no data read (eof or error), return with error. */
+ 11143              		.loc 1 5896 2 is_stmt 1 view .LVU3716
+5896:Middlewares/Third_Party/FatFs/src/ff.c **** 	return n ? buff : 0;			/* When no data read (eof or error), return with error. */
+ 11144              		.loc 1 5896 5 is_stmt 0 view .LVU3717
+ 11145 0044 0023     		movs	r3, #0
+ 11146 0046 2370     		strb	r3, [r4]
+5897:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 11147              		.loc 1 5897 2 is_stmt 1 view .LVU3718
+ARM GAS  /tmp/cc5lWXRL.s 			page 359
+
+
+5897:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 11148              		.loc 1 5897 18 is_stmt 0 view .LVU3719
+ 11149 0048 1DB1     		cbz	r5, .L808
+5897:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 11150              		.loc 1 5897 18 view .LVU3720
+ 11151 004a 4046     		mov	r0, r8
+ 11152              	.L800:
+5898:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 11153              		.loc 1 5898 1 view .LVU3721
+ 11154 004c 02B0     		add	sp, sp, #8
+ 11155              	.LCFI117:
+ 11156              		.cfi_remember_state
+ 11157              		.cfi_def_cfa_offset 24
+ 11158              		@ sp needed
+ 11159 004e BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 11160              	.LVL1302:
+ 11161              	.L808:
+ 11162              	.LCFI118:
+ 11163              		.cfi_restore_state
+5897:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 11164              		.loc 1 5897 18 view .LVU3722
+ 11165 0052 0020     		movs	r0, #0
+ 11166 0054 FAE7     		b	.L800
+ 11167              		.cfi_endproc
+ 11168              	.LFE1238:
+ 11170              		.section	.text.f_putc,"ax",%progbits
+ 11171              		.align	1
+ 11172              		.global	f_putc
+ 11173              		.syntax unified
+ 11174              		.thumb
+ 11175              		.thumb_func
+ 11176              		.fpu fpv5-d16
+ 11178              	f_putc:
+ 11179              	.LVL1303:
+ 11180              	.LFB1242:
+5995:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5996:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5997:Middlewares/Third_Party/FatFs/src/ff.c **** 
+5998:Middlewares/Third_Party/FatFs/src/ff.c **** int f_putc (
+5999:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR c,	/* A character to be output */
+6000:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp		/* Pointer to the file object */
+6001:Middlewares/Third_Party/FatFs/src/ff.c **** )
+6002:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 11181              		.loc 1 6002 1 is_stmt 1 view -0
+ 11182              		.cfi_startproc
+ 11183              		@ args = 0, pretend = 0, frame = 80
+ 11184              		@ frame_needed = 0, uses_anonymous_args = 0
+ 11185              		.loc 1 6002 1 is_stmt 0 view .LVU3724
+ 11186 0000 10B5     		push	{r4, lr}
+ 11187              	.LCFI119:
+ 11188              		.cfi_def_cfa_offset 8
+ 11189              		.cfi_offset 4, -8
+ 11190              		.cfi_offset 14, -4
+ 11191 0002 94B0     		sub	sp, sp, #80
+ 11192              	.LCFI120:
+ 11193              		.cfi_def_cfa_offset 88
+ 11194 0004 0446     		mov	r4, r0
+ARM GAS  /tmp/cc5lWXRL.s 			page 360
+
+
+6003:Middlewares/Third_Party/FatFs/src/ff.c **** 	putbuff pb;
+ 11195              		.loc 1 6003 2 is_stmt 1 view .LVU3725
+6004:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6005:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6006:Middlewares/Third_Party/FatFs/src/ff.c **** 	putc_init(&pb, fp);
+ 11196              		.loc 1 6006 2 view .LVU3726
+ 11197 0006 01A8     		add	r0, sp, #4
+ 11198              	.LVL1304:
+ 11199              		.loc 1 6006 2 is_stmt 0 view .LVU3727
+ 11200 0008 FFF7FEFF 		bl	putc_init
+ 11201              	.LVL1305:
+6007:Middlewares/Third_Party/FatFs/src/ff.c **** 	putc_bfd(&pb, c);	/* Put the character */
+ 11202              		.loc 1 6007 2 is_stmt 1 view .LVU3728
+ 11203 000c 2146     		mov	r1, r4
+ 11204 000e 01A8     		add	r0, sp, #4
+ 11205 0010 FFF7FEFF 		bl	putc_bfd
+ 11206              	.LVL1306:
+6008:Middlewares/Third_Party/FatFs/src/ff.c **** 	return putc_flush(&pb);
+ 11207              		.loc 1 6008 2 view .LVU3729
+ 11208              		.loc 1 6008 9 is_stmt 0 view .LVU3730
+ 11209 0014 01A8     		add	r0, sp, #4
+ 11210 0016 FFF7FEFF 		bl	putc_flush
+ 11211              	.LVL1307:
+6009:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 11212              		.loc 1 6009 1 view .LVU3731
+ 11213 001a 14B0     		add	sp, sp, #80
+ 11214              	.LCFI121:
+ 11215              		.cfi_def_cfa_offset 8
+ 11216              		@ sp needed
+ 11217 001c 10BD     		pop	{r4, pc}
+ 11218              		.cfi_endproc
+ 11219              	.LFE1242:
+ 11221              		.section	.text.f_puts,"ax",%progbits
+ 11222              		.align	1
+ 11223              		.global	f_puts
+ 11224              		.syntax unified
+ 11225              		.thumb
+ 11226              		.thumb_func
+ 11227              		.fpu fpv5-d16
+ 11229              	f_puts:
+ 11230              	.LVL1308:
+ 11231              	.LFB1243:
+6010:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6011:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6012:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6013:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6014:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+6015:Middlewares/Third_Party/FatFs/src/ff.c **** /* Put a string to the file                                              */
+6016:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+6017:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6018:Middlewares/Third_Party/FatFs/src/ff.c **** int f_puts (
+6019:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* str,	/* Pointer to the string to be output */
+6020:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp				/* Pointer to the file object */
+6021:Middlewares/Third_Party/FatFs/src/ff.c **** )
+6022:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 11232              		.loc 1 6022 1 is_stmt 1 view -0
+ 11233              		.cfi_startproc
+ARM GAS  /tmp/cc5lWXRL.s 			page 361
+
+
+ 11234              		@ args = 0, pretend = 0, frame = 80
+ 11235              		@ frame_needed = 0, uses_anonymous_args = 0
+ 11236              		.loc 1 6022 1 is_stmt 0 view .LVU3733
+ 11237 0000 10B5     		push	{r4, lr}
+ 11238              	.LCFI122:
+ 11239              		.cfi_def_cfa_offset 8
+ 11240              		.cfi_offset 4, -8
+ 11241              		.cfi_offset 14, -4
+ 11242 0002 94B0     		sub	sp, sp, #80
+ 11243              	.LCFI123:
+ 11244              		.cfi_def_cfa_offset 88
+ 11245 0004 0446     		mov	r4, r0
+6023:Middlewares/Third_Party/FatFs/src/ff.c **** 	putbuff pb;
+ 11246              		.loc 1 6023 2 is_stmt 1 view .LVU3734
+6024:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6025:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6026:Middlewares/Third_Party/FatFs/src/ff.c **** 	putc_init(&pb, fp);
+ 11247              		.loc 1 6026 2 view .LVU3735
+ 11248 0006 01A8     		add	r0, sp, #4
+ 11249              	.LVL1309:
+ 11250              		.loc 1 6026 2 is_stmt 0 view .LVU3736
+ 11251 0008 FFF7FEFF 		bl	putc_init
+ 11252              	.LVL1310:
+6027:Middlewares/Third_Party/FatFs/src/ff.c **** 	while (*str) putc_bfd(&pb, *str++);		/* Put the string */
+ 11253              		.loc 1 6027 2 is_stmt 1 view .LVU3737
+ 11254              		.loc 1 6027 8 is_stmt 0 view .LVU3738
+ 11255 000c 03E0     		b	.L813
+ 11256              	.L814:
+ 11257              		.loc 1 6027 15 is_stmt 1 discriminator 2 view .LVU3739
+ 11258              		.loc 1 6027 33 is_stmt 0 discriminator 2 view .LVU3740
+ 11259 000e 0134     		adds	r4, r4, #1
+ 11260              	.LVL1311:
+ 11261              		.loc 1 6027 15 discriminator 2 view .LVU3741
+ 11262 0010 01A8     		add	r0, sp, #4
+ 11263 0012 FFF7FEFF 		bl	putc_bfd
+ 11264              	.LVL1312:
+ 11265              	.L813:
+ 11266              		.loc 1 6027 8 is_stmt 1 discriminator 1 view .LVU3742
+ 11267              		.loc 1 6027 9 is_stmt 0 discriminator 1 view .LVU3743
+ 11268 0016 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 11269              		.loc 1 6027 8 discriminator 1 view .LVU3744
+ 11270 0018 0029     		cmp	r1, #0
+ 11271 001a F8D1     		bne	.L814
+6028:Middlewares/Third_Party/FatFs/src/ff.c **** 	return putc_flush(&pb);
+ 11272              		.loc 1 6028 2 is_stmt 1 view .LVU3745
+ 11273              		.loc 1 6028 9 is_stmt 0 view .LVU3746
+ 11274 001c 01A8     		add	r0, sp, #4
+ 11275 001e FFF7FEFF 		bl	putc_flush
+ 11276              	.LVL1313:
+6029:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 11277              		.loc 1 6029 1 view .LVU3747
+ 11278 0022 14B0     		add	sp, sp, #80
+ 11279              	.LCFI124:
+ 11280              		.cfi_def_cfa_offset 8
+ 11281              		@ sp needed
+ 11282 0024 10BD     		pop	{r4, pc}
+ 11283              		.loc 1 6029 1 view .LVU3748
+ARM GAS  /tmp/cc5lWXRL.s 			page 362
+
+
+ 11284              		.cfi_endproc
+ 11285              	.LFE1243:
+ 11287              		.section	.text.f_printf,"ax",%progbits
+ 11288              		.align	1
+ 11289              		.global	f_printf
+ 11290              		.syntax unified
+ 11291              		.thumb
+ 11292              		.thumb_func
+ 11293              		.fpu fpv5-d16
+ 11295              	f_printf:
+ 11296              	.LVL1314:
+ 11297              	.LFB1244:
+6030:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6031:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6032:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6033:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6034:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+6035:Middlewares/Third_Party/FatFs/src/ff.c **** /* Put a formatted string to the file                                    */
+6036:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/
+6037:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6038:Middlewares/Third_Party/FatFs/src/ff.c **** int f_printf (
+6039:Middlewares/Third_Party/FatFs/src/ff.c **** 	FIL* fp,			/* Pointer to the file object */
+6040:Middlewares/Third_Party/FatFs/src/ff.c **** 	const TCHAR* fmt,	/* Pointer to the format string */
+6041:Middlewares/Third_Party/FatFs/src/ff.c **** 	...					/* Optional arguments... */
+6042:Middlewares/Third_Party/FatFs/src/ff.c **** )
+6043:Middlewares/Third_Party/FatFs/src/ff.c **** {
+ 11298              		.loc 1 6043 1 is_stmt 1 view -0
+ 11299              		.cfi_startproc
+ 11300              		@ args = 4, pretend = 12, frame = 112
+ 11301              		@ frame_needed = 0, uses_anonymous_args = 1
+ 11302              		.loc 1 6043 1 is_stmt 0 view .LVU3750
+ 11303 0000 0EB4     		push	{r1, r2, r3}
+ 11304              	.LCFI125:
+ 11305              		.cfi_def_cfa_offset 12
+ 11306              		.cfi_offset 1, -12
+ 11307              		.cfi_offset 2, -8
+ 11308              		.cfi_offset 3, -4
+ 11309 0002 2DE9F047 		push	{r4, r5, r6, r7, r8, r9, r10, lr}
+ 11310              	.LCFI126:
+ 11311              		.cfi_def_cfa_offset 44
+ 11312              		.cfi_offset 4, -44
+ 11313              		.cfi_offset 5, -40
+ 11314              		.cfi_offset 6, -36
+ 11315              		.cfi_offset 7, -32
+ 11316              		.cfi_offset 8, -28
+ 11317              		.cfi_offset 9, -24
+ 11318              		.cfi_offset 10, -20
+ 11319              		.cfi_offset 14, -16
+ 11320 0006 9DB0     		sub	sp, sp, #116
+ 11321              	.LCFI127:
+ 11322              		.cfi_def_cfa_offset 160
+ 11323 0008 0146     		mov	r1, r0
+ 11324 000a 25AC     		add	r4, sp, #148
+ 11325 000c 54F8045B 		ldr	r5, [r4], #4
+6044:Middlewares/Third_Party/FatFs/src/ff.c **** 	va_list arp;
+ 11326              		.loc 1 6044 2 is_stmt 1 view .LVU3751
+6045:Middlewares/Third_Party/FatFs/src/ff.c **** 	putbuff pb;
+ARM GAS  /tmp/cc5lWXRL.s 			page 363
+
+
+ 11327              		.loc 1 6045 2 view .LVU3752
+6046:Middlewares/Third_Party/FatFs/src/ff.c **** 	BYTE f, r;
+ 11328              		.loc 1 6046 2 view .LVU3753
+6047:Middlewares/Third_Party/FatFs/src/ff.c **** 	UINT i, j, w;
+ 11329              		.loc 1 6047 2 view .LVU3754
+6048:Middlewares/Third_Party/FatFs/src/ff.c **** 	DWORD v;
+ 11330              		.loc 1 6048 2 view .LVU3755
+6049:Middlewares/Third_Party/FatFs/src/ff.c **** 	TCHAR c, d, str[32], *p;
+ 11331              		.loc 1 6049 2 view .LVU3756
+6050:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6051:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6052:Middlewares/Third_Party/FatFs/src/ff.c **** 	putc_init(&pb, fp);
+ 11332              		.loc 1 6052 2 view .LVU3757
+ 11333 0010 08A8     		add	r0, sp, #32
+ 11334 0012 FFF7FEFF 		bl	putc_init
+ 11335              	.LVL1315:
+6053:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6054:Middlewares/Third_Party/FatFs/src/ff.c **** 	va_start(arp, fmt);
+ 11336              		.loc 1 6054 2 view .LVU3758
+ 11337 0016 1B94     		str	r4, [sp, #108]
+ 11338              	.LVL1316:
+ 11339              	.L817:
+6055:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6056:Middlewares/Third_Party/FatFs/src/ff.c **** 	for (;;) {
+ 11340              		.loc 1 6056 2 view .LVU3759
+6057:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = *fmt++;
+ 11341              		.loc 1 6057 3 view .LVU3760
+ 11342              		.loc 1 6057 11 is_stmt 0 view .LVU3761
+ 11343 0018 2C46     		mov	r4, r5
+ 11344              	.LVL1317:
+ 11345              		.loc 1 6057 5 view .LVU3762
+ 11346 001a 14F8011B 		ldrb	r1, [r4], #1	@ zero_extendqisi2
+ 11347              	.LVL1318:
+6058:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == 0) break;			/* End of string */
+ 11348              		.loc 1 6058 3 is_stmt 1 view .LVU3763
+ 11349              		.loc 1 6058 6 is_stmt 0 view .LVU3764
+ 11350 001e 0029     		cmp	r1, #0
+ 11351 0020 00F00481 		beq	.L818
+6059:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c != '%') {				/* Non escape character */
+ 11352              		.loc 1 6059 3 is_stmt 1 view .LVU3765
+ 11353              		.loc 1 6059 6 is_stmt 0 view .LVU3766
+ 11354 0024 2529     		cmp	r1, #37
+ 11355 0026 04D0     		beq	.L819
+6060:Middlewares/Third_Party/FatFs/src/ff.c **** 			putc_bfd(&pb, c);
+ 11356              		.loc 1 6060 4 is_stmt 1 view .LVU3767
+ 11357 0028 08A8     		add	r0, sp, #32
+ 11358 002a FFF7FEFF 		bl	putc_bfd
+ 11359              	.LVL1319:
+6061:Middlewares/Third_Party/FatFs/src/ff.c **** 			continue;
+ 11360              		.loc 1 6061 4 view .LVU3768
+6057:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == 0) break;			/* End of string */
+ 11361              		.loc 1 6057 11 is_stmt 0 view .LVU3769
+ 11362 002e 2546     		mov	r5, r4
+ 11363              		.loc 1 6061 4 view .LVU3770
+ 11364 0030 F2E7     		b	.L817
+ 11365              	.LVL1320:
+ 11366              	.L819:
+ARM GAS  /tmp/cc5lWXRL.s 			page 364
+
+
+6062:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+6063:Middlewares/Third_Party/FatFs/src/ff.c **** 		w = f = 0;
+ 11367              		.loc 1 6063 3 is_stmt 1 view .LVU3771
+6064:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = *fmt++;
+ 11368              		.loc 1 6064 3 view .LVU3772
+ 11369              		.loc 1 6064 11 is_stmt 0 view .LVU3773
+ 11370 0032 0235     		adds	r5, r5, #2
+ 11371              	.LVL1321:
+ 11372              		.loc 1 6064 5 view .LVU3774
+ 11373 0034 2178     		ldrb	r1, [r4]	@ zero_extendqisi2
+ 11374              	.LVL1322:
+6065:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == '0') {				/* Flag: '0' padding */
+ 11375              		.loc 1 6065 3 is_stmt 1 view .LVU3775
+ 11376              		.loc 1 6065 6 is_stmt 0 view .LVU3776
+ 11377 0036 3029     		cmp	r1, #48
+ 11378 0038 04D0     		beq	.L866
+6066:Middlewares/Third_Party/FatFs/src/ff.c **** 			f = 1; c = *fmt++;
+6067:Middlewares/Third_Party/FatFs/src/ff.c **** 		} else {
+6068:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (c == '-') {			/* Flag: left justified */
+ 11379              		.loc 1 6068 4 is_stmt 1 view .LVU3777
+ 11380              		.loc 1 6068 7 is_stmt 0 view .LVU3778
+ 11381 003a 2D29     		cmp	r1, #45
+ 11382 003c 06D0     		beq	.L867
+6063:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = *fmt++;
+ 11383              		.loc 1 6063 9 view .LVU3779
+ 11384 003e 0026     		movs	r6, #0
+ 11385              	.LVL1323:
+ 11386              	.L822:
+6063:Middlewares/Third_Party/FatFs/src/ff.c **** 		c = *fmt++;
+ 11387              		.loc 1 6063 9 view .LVU3780
+ 11388 0040 0024     		movs	r4, #0
+ 11389 0042 0EE0     		b	.L823
+ 11390              	.LVL1324:
+ 11391              	.L866:
+6066:Middlewares/Third_Party/FatFs/src/ff.c **** 			f = 1; c = *fmt++;
+ 11392              		.loc 1 6066 4 is_stmt 1 view .LVU3781
+6066:Middlewares/Third_Party/FatFs/src/ff.c **** 			f = 1; c = *fmt++;
+ 11393              		.loc 1 6066 11 view .LVU3782
+6066:Middlewares/Third_Party/FatFs/src/ff.c **** 			f = 1; c = *fmt++;
+ 11394              		.loc 1 6066 19 is_stmt 0 view .LVU3783
+ 11395 0044 A51C     		adds	r5, r4, #2
+ 11396              	.LVL1325:
+6066:Middlewares/Third_Party/FatFs/src/ff.c **** 			f = 1; c = *fmt++;
+ 11397              		.loc 1 6066 13 view .LVU3784
+ 11398 0046 6178     		ldrb	r1, [r4, #1]	@ zero_extendqisi2
+ 11399              	.LVL1326:
+6066:Middlewares/Third_Party/FatFs/src/ff.c **** 			f = 1; c = *fmt++;
+ 11400              		.loc 1 6066 6 view .LVU3785
+ 11401 0048 0126     		movs	r6, #1
+ 11402 004a F9E7     		b	.L822
+ 11403              	.LVL1327:
+ 11404              	.L867:
+6069:Middlewares/Third_Party/FatFs/src/ff.c **** 				f = 2; c = *fmt++;
+ 11405              		.loc 1 6069 5 is_stmt 1 view .LVU3786
+ 11406              		.loc 1 6069 12 view .LVU3787
+ 11407              		.loc 1 6069 20 is_stmt 0 view .LVU3788
+ 11408 004c A51C     		adds	r5, r4, #2
+ARM GAS  /tmp/cc5lWXRL.s 			page 365
+
+
+ 11409              	.LVL1328:
+ 11410              		.loc 1 6069 14 view .LVU3789
+ 11411 004e 6178     		ldrb	r1, [r4, #1]	@ zero_extendqisi2
+ 11412              	.LVL1329:
+ 11413              		.loc 1 6069 7 view .LVU3790
+ 11414 0050 0226     		movs	r6, #2
+ 11415 0052 F5E7     		b	.L822
+ 11416              	.LVL1330:
+ 11417              	.L824:
+6070:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+6071:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+6072:Middlewares/Third_Party/FatFs/src/ff.c **** 		while (IsDigit(c)) {		/* Precision */
+6073:Middlewares/Third_Party/FatFs/src/ff.c **** 			w = w * 10 + c - '0';
+ 11418              		.loc 1 6073 4 is_stmt 1 view .LVU3791
+ 11419              		.loc 1 6073 10 is_stmt 0 view .LVU3792
+ 11420 0054 04EB8404 		add	r4, r4, r4, lsl #2
+ 11421              	.LVL1331:
+ 11422              		.loc 1 6073 15 view .LVU3793
+ 11423 0058 01EB4404 		add	r4, r1, r4, lsl #1
+ 11424              		.loc 1 6073 6 view .LVU3794
+ 11425 005c 303C     		subs	r4, r4, #48
+ 11426              	.LVL1332:
+6074:Middlewares/Third_Party/FatFs/src/ff.c **** 			c = *fmt++;
+ 11427              		.loc 1 6074 4 is_stmt 1 view .LVU3795
+ 11428              		.loc 1 6074 6 is_stmt 0 view .LVU3796
+ 11429 005e 15F8011B 		ldrb	r1, [r5], #1	@ zero_extendqisi2
+ 11430              	.LVL1333:
+ 11431              	.L823:
+6072:Middlewares/Third_Party/FatFs/src/ff.c **** 			w = w * 10 + c - '0';
+ 11432              		.loc 1 6072 9 is_stmt 1 view .LVU3797
+6072:Middlewares/Third_Party/FatFs/src/ff.c **** 			w = w * 10 + c - '0';
+ 11433              		.loc 1 6072 10 is_stmt 0 view .LVU3798
+ 11434 0062 A1F13003 		sub	r3, r1, #48
+ 11435 0066 DBB2     		uxtb	r3, r3
+6072:Middlewares/Third_Party/FatFs/src/ff.c **** 			w = w * 10 + c - '0';
+ 11436              		.loc 1 6072 9 view .LVU3799
+ 11437 0068 092B     		cmp	r3, #9
+ 11438 006a F3D9     		bls	.L824
+6075:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+6076:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (c == 'l' || c == 'L') {	/* Prefix: Size is long int */
+ 11439              		.loc 1 6076 3 is_stmt 1 view .LVU3800
+ 11440              		.loc 1 6076 6 is_stmt 0 view .LVU3801
+ 11441 006c 4C29     		cmp	r1, #76
+ 11442 006e 18BF     		it	ne
+ 11443 0070 6C29     		cmpne	r1, #108
+ 11444 0072 03D1     		bne	.L825
+6077:Middlewares/Third_Party/FatFs/src/ff.c **** 			f |= 4; c = *fmt++;
+ 11445              		.loc 1 6077 4 is_stmt 1 view .LVU3802
+ 11446              		.loc 1 6077 6 is_stmt 0 view .LVU3803
+ 11447 0074 46F00406 		orr	r6, r6, #4
+ 11448              	.LVL1334:
+ 11449              		.loc 1 6077 12 is_stmt 1 view .LVU3804
+ 11450              		.loc 1 6077 14 is_stmt 0 view .LVU3805
+ 11451 0078 15F8011B 		ldrb	r1, [r5], #1	@ zero_extendqisi2
+ 11452              	.LVL1335:
+ 11453              	.L825:
+6078:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ARM GAS  /tmp/cc5lWXRL.s 			page 366
+
+
+6079:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (!c) break;
+ 11454              		.loc 1 6079 3 is_stmt 1 view .LVU3806
+ 11455              		.loc 1 6079 6 is_stmt 0 view .LVU3807
+ 11456 007c 0029     		cmp	r1, #0
+ 11457 007e 00F0D580 		beq	.L818
+6080:Middlewares/Third_Party/FatFs/src/ff.c **** 		d = c;
+ 11458              		.loc 1 6080 3 is_stmt 1 view .LVU3808
+ 11459              	.LVL1336:
+6081:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (IsLower(d)) d -= 0x20;
+ 11460              		.loc 1 6081 3 view .LVU3809
+ 11461              		.loc 1 6081 7 is_stmt 0 view .LVU3810
+ 11462 0082 A1F16103 		sub	r3, r1, #97
+ 11463 0086 DBB2     		uxtb	r3, r3
+ 11464              		.loc 1 6081 6 view .LVU3811
+ 11465 0088 192B     		cmp	r3, #25
+ 11466 008a 14D8     		bhi	.L860
+ 11467              		.loc 1 6081 19 is_stmt 1 discriminator 1 view .LVU3812
+ 11468              		.loc 1 6081 21 is_stmt 0 discriminator 1 view .LVU3813
+ 11469 008c A1F12003 		sub	r3, r1, #32
+ 11470 0090 DBB2     		uxtb	r3, r3
+ 11471              	.LVL1337:
+ 11472              	.L826:
+6082:Middlewares/Third_Party/FatFs/src/ff.c **** 		switch (d) {				/* Type is... */
+ 11473              		.loc 1 6082 3 is_stmt 1 view .LVU3814
+ 11474 0092 A3F14202 		sub	r2, r3, #66
+ 11475 0096 162A     		cmp	r2, #22
+ 11476 0098 5DD8     		bhi	.L827
+ 11477 009a DFE802F0 		tbb	[pc, r2]
+ 11478              	.L829:
+ 11479 009e 60       		.byte	(.L834-.L829)/2
+ 11480 009f 3D       		.byte	(.L833-.L829)/2
+ 11481 00a0 45       		.byte	(.L830-.L829)/2
+ 11482 00a1 5C       		.byte	(.L827-.L829)/2
+ 11483 00a2 5C       		.byte	(.L827-.L829)/2
+ 11484 00a3 5C       		.byte	(.L827-.L829)/2
+ 11485 00a4 5C       		.byte	(.L827-.L829)/2
+ 11486 00a5 5C       		.byte	(.L827-.L829)/2
+ 11487 00a6 5C       		.byte	(.L827-.L829)/2
+ 11488 00a7 5C       		.byte	(.L827-.L829)/2
+ 11489 00a8 5C       		.byte	(.L827-.L829)/2
+ 11490 00a9 5C       		.byte	(.L827-.L829)/2
+ 11491 00aa 5C       		.byte	(.L827-.L829)/2
+ 11492 00ab 62       		.byte	(.L861-.L829)/2
+ 11493 00ac 5C       		.byte	(.L827-.L829)/2
+ 11494 00ad 5C       		.byte	(.L827-.L829)/2
+ 11495 00ae 5C       		.byte	(.L827-.L829)/2
+ 11496 00af 0E       		.byte	(.L831-.L829)/2
+ 11497 00b0 5C       		.byte	(.L827-.L829)/2
+ 11498 00b1 45       		.byte	(.L830-.L829)/2
+ 11499 00b2 5C       		.byte	(.L827-.L829)/2
+ 11500 00b3 5C       		.byte	(.L827-.L829)/2
+ 11501 00b4 5A       		.byte	(.L828-.L829)/2
+ 11502              	.LVL1338:
+ 11503 00b5 00       		.p2align 1
+ 11504              	.L860:
+6080:Middlewares/Third_Party/FatFs/src/ff.c **** 		d = c;
+ 11505              		.loc 1 6080 5 is_stmt 0 view .LVU3815
+ARM GAS  /tmp/cc5lWXRL.s 			page 367
+
+
+ 11506 00b6 0B46     		mov	r3, r1
+ 11507 00b8 EBE7     		b	.L826
+ 11508              	.LVL1339:
+ 11509              	.L831:
+6083:Middlewares/Third_Party/FatFs/src/ff.c **** 		case 'S' :					/* String */
+6084:Middlewares/Third_Party/FatFs/src/ff.c **** 			p = va_arg(arp, TCHAR*);
+ 11510              		.loc 1 6084 4 is_stmt 1 view .LVU3816
+ 11511              		.loc 1 6084 6 is_stmt 0 view .LVU3817
+ 11512 00ba 1B9B     		ldr	r3, [sp, #108]
+ 11513              	.LVL1340:
+ 11514              		.loc 1 6084 6 view .LVU3818
+ 11515 00bc 1A1D     		adds	r2, r3, #4
+ 11516 00be 1B92     		str	r2, [sp, #108]
+ 11517 00c0 D3F80080 		ldr	r8, [r3]
+6085:Middlewares/Third_Party/FatFs/src/ff.c **** 			for (j = 0; p[j]; j++) ;
+ 11518              		.loc 1 6085 4 is_stmt 1 view .LVU3819
+ 11519              	.LVL1341:
+ 11520              		.loc 1 6085 11 is_stmt 0 view .LVU3820
+ 11521 00c4 0027     		movs	r7, #0
+ 11522              		.loc 1 6085 4 view .LVU3821
+ 11523 00c6 00E0     		b	.L835
+ 11524              	.LVL1342:
+ 11525              	.L836:
+ 11526              		.loc 1 6085 27 is_stmt 1 discriminator 3 view .LVU3822
+ 11527              		.loc 1 6085 22 discriminator 3 view .LVU3823
+ 11528              		.loc 1 6085 23 is_stmt 0 discriminator 3 view .LVU3824
+ 11529 00c8 0137     		adds	r7, r7, #1
+ 11530              	.LVL1343:
+ 11531              	.L835:
+ 11532              		.loc 1 6085 16 is_stmt 1 discriminator 1 view .LVU3825
+ 11533              		.loc 1 6085 17 is_stmt 0 discriminator 1 view .LVU3826
+ 11534 00ca 18F80730 		ldrb	r3, [r8, r7]	@ zero_extendqisi2
+ 11535              		.loc 1 6085 4 discriminator 1 view .LVU3827
+ 11536 00ce 002B     		cmp	r3, #0
+ 11537 00d0 FAD1     		bne	.L836
+6086:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (!(f & 2)) {
+ 11538              		.loc 1 6086 4 is_stmt 1 view .LVU3828
+ 11539              		.loc 1 6086 7 is_stmt 0 view .LVU3829
+ 11540 00d2 16F0020F 		tst	r6, #2
+ 11541 00d6 10D1     		bne	.L840
+ 11542 00d8 05E0     		b	.L837
+ 11543              	.LVL1344:
+ 11544              	.L839:
+6087:Middlewares/Third_Party/FatFs/src/ff.c **** 				while (j++ < w) putc_bfd(&pb, ' ');
+ 11545              		.loc 1 6087 21 is_stmt 1 discriminator 2 view .LVU3830
+ 11546 00da 2021     		movs	r1, #32
+ 11547 00dc 0DEB0100 		add	r0, sp, r1
+ 11548 00e0 FFF7FEFF 		bl	putc_bfd
+ 11549              	.LVL1345:
+ 11550              		.loc 1 6087 13 is_stmt 0 discriminator 2 view .LVU3831
+ 11551 00e4 3746     		mov	r7, r6
+ 11552              	.LVL1346:
+ 11553              	.L837:
+ 11554              		.loc 1 6087 11 is_stmt 1 discriminator 1 view .LVU3832
+ 11555              		.loc 1 6087 13 is_stmt 0 discriminator 1 view .LVU3833
+ 11556 00e6 7E1C     		adds	r6, r7, #1
+ 11557              	.LVL1347:
+ARM GAS  /tmp/cc5lWXRL.s 			page 368
+
+
+ 11558              		.loc 1 6087 11 discriminator 1 view .LVU3834
+ 11559 00e8 A742     		cmp	r7, r4
+ 11560 00ea F6D3     		bcc	.L839
+ 11561              		.loc 1 6087 13 view .LVU3835
+ 11562 00ec 3746     		mov	r7, r6
+ 11563 00ee 04E0     		b	.L840
+ 11564              	.LVL1348:
+ 11565              	.L841:
+6088:Middlewares/Third_Party/FatFs/src/ff.c **** 			}
+6089:Middlewares/Third_Party/FatFs/src/ff.c **** 			while (*p) putc_bfd(&pb, *p++);
+ 11566              		.loc 1 6089 15 is_stmt 1 discriminator 2 view .LVU3836
+ 11567              		.loc 1 6089 31 is_stmt 0 discriminator 2 view .LVU3837
+ 11568 00f0 08F10108 		add	r8, r8, #1
+ 11569              	.LVL1349:
+ 11570              		.loc 1 6089 15 discriminator 2 view .LVU3838
+ 11571 00f4 08A8     		add	r0, sp, #32
+ 11572 00f6 FFF7FEFF 		bl	putc_bfd
+ 11573              	.LVL1350:
+ 11574              	.L840:
+ 11575              		.loc 1 6089 10 is_stmt 1 discriminator 1 view .LVU3839
+ 11576              		.loc 1 6089 11 is_stmt 0 discriminator 1 view .LVU3840
+ 11577 00fa 98F80010 		ldrb	r1, [r8]	@ zero_extendqisi2
+ 11578              		.loc 1 6089 10 discriminator 1 view .LVU3841
+ 11579 00fe 0029     		cmp	r1, #0
+ 11580 0100 F6D1     		bne	.L841
+ 11581              		.loc 1 6089 10 discriminator 1 view .LVU3842
+ 11582 0102 05E0     		b	.L842
+ 11583              	.LVL1351:
+ 11584              	.L843:
+6090:Middlewares/Third_Party/FatFs/src/ff.c **** 			while (j++ < w) putc_bfd(&pb, ' ');
+ 11585              		.loc 1 6090 20 is_stmt 1 discriminator 2 view .LVU3843
+ 11586 0104 2021     		movs	r1, #32
+ 11587 0106 0DEB0100 		add	r0, sp, r1
+ 11588 010a FFF7FEFF 		bl	putc_bfd
+ 11589              	.LVL1352:
+ 11590              		.loc 1 6090 12 is_stmt 0 discriminator 2 view .LVU3844
+ 11591 010e 3746     		mov	r7, r6
+ 11592              	.LVL1353:
+ 11593              	.L842:
+ 11594              		.loc 1 6090 10 is_stmt 1 discriminator 1 view .LVU3845
+ 11595              		.loc 1 6090 12 is_stmt 0 discriminator 1 view .LVU3846
+ 11596 0110 7E1C     		adds	r6, r7, #1
+ 11597              	.LVL1354:
+ 11598              		.loc 1 6090 10 discriminator 1 view .LVU3847
+ 11599 0112 A742     		cmp	r7, r4
+ 11600 0114 F6D3     		bcc	.L843
+ 11601 0116 7FE7     		b	.L817
+ 11602              	.LVL1355:
+ 11603              	.L833:
+6091:Middlewares/Third_Party/FatFs/src/ff.c **** 			continue;
+6092:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6093:Middlewares/Third_Party/FatFs/src/ff.c **** 		case 'C' :					/* Character */
+6094:Middlewares/Third_Party/FatFs/src/ff.c **** 			putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue;
+ 11604              		.loc 1 6094 4 is_stmt 1 view .LVU3848
+ 11605              		.loc 1 6094 25 is_stmt 0 view .LVU3849
+ 11606 0118 1B9B     		ldr	r3, [sp, #108]
+ 11607              	.LVL1356:
+ARM GAS  /tmp/cc5lWXRL.s 			page 369
+
+
+ 11608              		.loc 1 6094 25 view .LVU3850
+ 11609 011a 1A1D     		adds	r2, r3, #4
+ 11610 011c 1B92     		str	r2, [sp, #108]
+ 11611              		.loc 1 6094 4 view .LVU3851
+ 11612 011e 1978     		ldrb	r1, [r3]	@ zero_extendqisi2
+ 11613              	.LVL1357:
+ 11614              		.loc 1 6094 4 view .LVU3852
+ 11615 0120 08A8     		add	r0, sp, #32
+ 11616 0122 FFF7FEFF 		bl	putc_bfd
+ 11617              	.LVL1358:
+ 11618              		.loc 1 6094 44 is_stmt 1 view .LVU3853
+ 11619              		.loc 1 6094 4 is_stmt 0 view .LVU3854
+ 11620 0126 77E7     		b	.L817
+ 11621              	.LVL1359:
+ 11622              	.L830:
+6095:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6096:Middlewares/Third_Party/FatFs/src/ff.c **** 		case 'B' :					/* Binary */
+6097:Middlewares/Third_Party/FatFs/src/ff.c **** 			r = 2; break;
+6098:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6099:Middlewares/Third_Party/FatFs/src/ff.c **** 		case 'O' :					/* Octal */
+6100:Middlewares/Third_Party/FatFs/src/ff.c **** 			r = 8; break;
+6101:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6102:Middlewares/Third_Party/FatFs/src/ff.c **** 		case 'D' :					/* Signed decimal */
+6103:Middlewares/Third_Party/FatFs/src/ff.c **** 		case 'U' :					/* Unsigned decimal */
+6104:Middlewares/Third_Party/FatFs/src/ff.c **** 			r = 10; break;
+ 11623              		.loc 1 6104 4 is_stmt 1 view .LVU3855
+ 11624              		.loc 1 6104 12 view .LVU3856
+ 11625              		.loc 1 6104 6 is_stmt 0 view .LVU3857
+ 11626 0128 0A20     		movs	r0, #10
+ 11627              	.LVL1360:
+ 11628              	.L832:
+6105:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6106:Middlewares/Third_Party/FatFs/src/ff.c **** 		case 'X' :					/* Hexdecimal */
+6107:Middlewares/Third_Party/FatFs/src/ff.c **** 			r = 16; break;
+6108:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6109:Middlewares/Third_Party/FatFs/src/ff.c **** 		default:					/* Unknown type (pass-through) */
+6110:Middlewares/Third_Party/FatFs/src/ff.c **** 			putc_bfd(&pb, c); continue;
+6111:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+6112:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6113:Middlewares/Third_Party/FatFs/src/ff.c **** 		/* Get an argument and put it in numeral */
+6114:Middlewares/Third_Party/FatFs/src/ff.c **** 		v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_
+ 11629              		.loc 1 6114 3 is_stmt 1 view .LVU3858
+ 11630              		.loc 1 6114 42 is_stmt 0 view .LVU3859
+ 11631 012a 16F0040F 		tst	r6, #4
+ 11632 012e 1AD0     		beq	.L844
+ 11633              		.loc 1 6114 24 view .LVU3860
+ 11634 0130 1B9A     		ldr	r2, [sp, #108]
+ 11635 0132 171D     		adds	r7, r2, #4
+ 11636 0134 1B97     		str	r7, [sp, #108]
+ 11637 0136 1268     		ldr	r2, [r2]
+ 11638              	.L845:
+ 11639              	.LVL1361:
+6115:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (d == 'D' && (v & 0x80000000)) {
+ 11640              		.loc 1 6115 3 is_stmt 1 discriminator 8 view .LVU3861
+ 11641              		.loc 1 6115 16 is_stmt 0 discriminator 8 view .LVU3862
+ 11642 0138 D70F     		lsrs	r7, r2, #31
+ 11643 013a 442B     		cmp	r3, #68
+ARM GAS  /tmp/cc5lWXRL.s 			page 370
+
+
+ 11644 013c 14BF     		ite	ne
+ 11645 013e 0027     		movne	r7, #0
+ 11646 0140 07F00107 		andeq	r7, r7, #1
+ 11647              		.loc 1 6115 6 discriminator 8 view .LVU3863
+ 11648 0144 17B1     		cbz	r7, .L847
+6116:Middlewares/Third_Party/FatFs/src/ff.c **** 			v = 0 - v;
+ 11649              		.loc 1 6116 4 is_stmt 1 view .LVU3864
+ 11650              		.loc 1 6116 6 is_stmt 0 view .LVU3865
+ 11651 0146 5242     		rsbs	r2, r2, #0
+ 11652              	.LVL1362:
+6117:Middlewares/Third_Party/FatFs/src/ff.c **** 			f |= 8;
+ 11653              		.loc 1 6117 4 is_stmt 1 view .LVU3866
+ 11654              		.loc 1 6117 6 is_stmt 0 view .LVU3867
+ 11655 0148 46F00806 		orr	r6, r6, #8
+ 11656              	.LVL1363:
+ 11657              	.L847:
+6118:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+6119:Middlewares/Third_Party/FatFs/src/ff.c **** 		i = 0;
+ 11658              		.loc 1 6119 3 is_stmt 1 view .LVU3868
+ 11659              		.loc 1 6119 5 is_stmt 0 view .LVU3869
+ 11660 014c 4FF0000C 		mov	ip, #0
+ 11661 0150 25E0     		b	.L850
+ 11662              	.LVL1364:
+ 11663              	.L828:
+6107:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 11664              		.loc 1 6107 4 is_stmt 1 view .LVU3870
+6107:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 11665              		.loc 1 6107 12 view .LVU3871
+6107:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 11666              		.loc 1 6107 6 is_stmt 0 view .LVU3872
+ 11667 0152 1020     		movs	r0, #16
+6107:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 11668              		.loc 1 6107 4 view .LVU3873
+ 11669 0154 E9E7     		b	.L832
+ 11670              	.LVL1365:
+ 11671              	.L827:
+6110:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 11672              		.loc 1 6110 4 is_stmt 1 view .LVU3874
+ 11673 0156 08A8     		add	r0, sp, #32
+ 11674 0158 FFF7FEFF 		bl	putc_bfd
+ 11675              	.LVL1366:
+6110:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 11676              		.loc 1 6110 22 view .LVU3875
+6110:Middlewares/Third_Party/FatFs/src/ff.c **** 		}
+ 11677              		.loc 1 6110 4 is_stmt 0 view .LVU3876
+ 11678 015c 5CE7     		b	.L817
+ 11679              	.LVL1367:
+ 11680              	.L834:
+6082:Middlewares/Third_Party/FatFs/src/ff.c **** 		case 'S' :					/* String */
+ 11681              		.loc 1 6082 3 view .LVU3877
+ 11682 015e 0220     		movs	r0, #2
+ 11683 0160 E3E7     		b	.L832
+ 11684              	.L861:
+6100:Middlewares/Third_Party/FatFs/src/ff.c **** 
+ 11685              		.loc 1 6100 6 view .LVU3878
+ 11686 0162 0820     		movs	r0, #8
+ 11687 0164 E1E7     		b	.L832
+ARM GAS  /tmp/cc5lWXRL.s 			page 371
+
+
+ 11688              	.LVL1368:
+ 11689              	.L844:
+6114:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (d == 'D' && (v & 0x80000000)) {
+ 11690              		.loc 1 6114 88 discriminator 2 view .LVU3879
+ 11691 0166 442B     		cmp	r3, #68
+ 11692 0168 04D0     		beq	.L868
+6114:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (d == 'D' && (v & 0x80000000)) {
+ 11693              		.loc 1 6114 88 view .LVU3880
+ 11694 016a 1B9A     		ldr	r2, [sp, #108]
+ 11695 016c 171D     		adds	r7, r2, #4
+ 11696 016e 1B97     		str	r7, [sp, #108]
+ 11697 0170 1268     		ldr	r2, [r2]
+ 11698 0172 E1E7     		b	.L845
+ 11699              	.L868:
+6114:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (d == 'D' && (v & 0x80000000)) {
+ 11700              		.loc 1 6114 71 view .LVU3881
+ 11701 0174 1B9A     		ldr	r2, [sp, #108]
+ 11702 0176 171D     		adds	r7, r2, #4
+ 11703 0178 1B97     		str	r7, [sp, #108]
+ 11704 017a 1268     		ldr	r2, [r2]
+ 11705 017c DCE7     		b	.L845
+ 11706              	.LVL1369:
+ 11707              	.L870:
+6120:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+6121:Middlewares/Third_Party/FatFs/src/ff.c **** 			d = (TCHAR)(v % r); v /= r;
+6122:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+ 11708              		.loc 1 6122 17 view .LVU3882
+ 11709 017e 2727     		movs	r7, #39
+ 11710              	.L849:
+ 11711              		.loc 1 6122 17 discriminator 5 view .LVU3883
+ 11712 0180 3B44     		add	r3, r3, r7
+ 11713              	.LVL1370:
+ 11714              		.loc 1 6122 17 discriminator 5 view .LVU3884
+ 11715 0182 DBB2     		uxtb	r3, r3
+ 11716              	.LVL1371:
+ 11717              	.L848:
+6123:Middlewares/Third_Party/FatFs/src/ff.c **** 			str[i++] = d + '0';
+ 11718              		.loc 1 6123 4 is_stmt 1 view .LVU3885
+ 11719              		.loc 1 6123 9 is_stmt 0 view .LVU3886
+ 11720 0184 0CF10107 		add	r7, ip, #1
+ 11721              	.LVL1372:
+ 11722              		.loc 1 6123 17 view .LVU3887
+ 11723 0188 3033     		adds	r3, r3, #48
+ 11724              	.LVL1373:
+ 11725              		.loc 1 6123 13 view .LVU3888
+ 11726 018a 0CF17009 		add	r9, ip, #112
+ 11727 018e E944     		add	r9, sp, r9
+ 11728 0190 09F8703C 		strb	r3, [r9, #-112]
+6124:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (v && i < sizeof str / sizeof str[0]);
+ 11729              		.loc 1 6124 11 is_stmt 1 view .LVU3889
+ 11730              		.loc 1 6124 3 is_stmt 0 view .LVU3890
+ 11731 0194 C645     		cmp	lr, r8
+ 11732 0196 98BF     		it	ls
+ 11733 0198 1F2F     		cmpls	r7, #31
+ 11734 019a 0ED8     		bhi	.L869
+6123:Middlewares/Third_Party/FatFs/src/ff.c **** 			str[i++] = d + '0';
+ 11735              		.loc 1 6123 9 view .LVU3891
+ARM GAS  /tmp/cc5lWXRL.s 			page 372
+
+
+ 11736 019c BC46     		mov	ip, r7
+ 11737              	.LVL1374:
+ 11738              	.L850:
+6120:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+ 11739              		.loc 1 6120 3 is_stmt 1 view .LVU3892
+6121:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+ 11740              		.loc 1 6121 4 view .LVU3893
+6121:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+ 11741              		.loc 1 6121 18 is_stmt 0 view .LVU3894
+ 11742 019e 8646     		mov	lr, r0
+ 11743 01a0 B2FBF0F7 		udiv	r7, r2, r0
+ 11744 01a4 00FB1723 		mls	r3, r0, r7, r2
+6121:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+ 11745              		.loc 1 6121 6 view .LVU3895
+ 11746 01a8 DBB2     		uxtb	r3, r3
+ 11747              	.LVL1375:
+6121:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+ 11748              		.loc 1 6121 24 is_stmt 1 view .LVU3896
+ 11749 01aa 9046     		mov	r8, r2
+6121:Middlewares/Third_Party/FatFs/src/ff.c **** 			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+ 11750              		.loc 1 6121 26 is_stmt 0 view .LVU3897
+ 11751 01ac 3A46     		mov	r2, r7
+ 11752              	.LVL1376:
+6122:Middlewares/Third_Party/FatFs/src/ff.c **** 			str[i++] = d + '0';
+ 11753              		.loc 1 6122 4 is_stmt 1 view .LVU3898
+6122:Middlewares/Third_Party/FatFs/src/ff.c **** 			str[i++] = d + '0';
+ 11754              		.loc 1 6122 7 is_stmt 0 view .LVU3899
+ 11755 01ae 092B     		cmp	r3, #9
+ 11756 01b0 E8D9     		bls	.L848
+6122:Middlewares/Third_Party/FatFs/src/ff.c **** 			str[i++] = d + '0';
+ 11757              		.loc 1 6122 15 is_stmt 1 discriminator 1 view .LVU3900
+6122:Middlewares/Third_Party/FatFs/src/ff.c **** 			str[i++] = d + '0';
+ 11758              		.loc 1 6122 17 is_stmt 0 discriminator 1 view .LVU3901
+ 11759 01b2 7829     		cmp	r1, #120
+ 11760 01b4 E3D0     		beq	.L870
+6122:Middlewares/Third_Party/FatFs/src/ff.c **** 			str[i++] = d + '0';
+ 11761              		.loc 1 6122 17 view .LVU3902
+ 11762 01b6 0727     		movs	r7, #7
+ 11763 01b8 E2E7     		b	.L849
+ 11764              	.LVL1377:
+ 11765              	.L869:
+6125:Middlewares/Third_Party/FatFs/src/ff.c **** 		if (f & 8) str[i++] = '-';
+ 11766              		.loc 1 6125 3 is_stmt 1 view .LVU3903
+ 11767              		.loc 1 6125 6 is_stmt 0 view .LVU3904
+ 11768 01ba 16F0080F 		tst	r6, #8
+ 11769 01be 08D0     		beq	.L851
+ 11770              		.loc 1 6125 14 is_stmt 1 discriminator 1 view .LVU3905
+ 11771              	.LVL1378:
+ 11772              		.loc 1 6125 23 is_stmt 0 discriminator 1 view .LVU3906
+ 11773 01c0 07F17003 		add	r3, r7, #112
+ 11774 01c4 0DEB0307 		add	r7, sp, r3
+ 11775 01c8 2D23     		movs	r3, #45
+ 11776 01ca 07F8703C 		strb	r3, [r7, #-112]
+ 11777              		.loc 1 6125 19 discriminator 1 view .LVU3907
+ 11778 01ce 0CF10207 		add	r7, ip, #2
+ 11779              	.LVL1379:
+ 11780              	.L851:
+ARM GAS  /tmp/cc5lWXRL.s 			page 373
+
+
+6126:Middlewares/Third_Party/FatFs/src/ff.c **** 		j = i; d = (f & 1) ? '0' : ' ';
+ 11781              		.loc 1 6126 3 is_stmt 1 view .LVU3908
+ 11782              		.loc 1 6126 10 view .LVU3909
+ 11783              		.loc 1 6126 12 is_stmt 0 view .LVU3910
+ 11784 01d2 16F0010F 		tst	r6, #1
+ 11785 01d6 03D0     		beq	.L864
+ 11786              		.loc 1 6126 12 view .LVU3911
+ 11787 01d8 4FF0300A 		mov	r10, #48
+ 11788              	.L852:
+ 11789              	.LVL1380:
+6127:Middlewares/Third_Party/FatFs/src/ff.c **** 		while (!(f & 2) && j++ < w) putc_bfd(&pb, d);
+ 11790              		.loc 1 6127 3 is_stmt 1 discriminator 4 view .LVU3912
+6126:Middlewares/Third_Party/FatFs/src/ff.c **** 		j = i; d = (f & 1) ? '0' : ' ';
+ 11791              		.loc 1 6126 5 is_stmt 0 discriminator 4 view .LVU3913
+ 11792 01dc B846     		mov	r8, r7
+ 11793              		.loc 1 6127 9 discriminator 4 view .LVU3914
+ 11794 01de 07E0     		b	.L853
+ 11795              	.LVL1381:
+ 11796              	.L864:
+6126:Middlewares/Third_Party/FatFs/src/ff.c **** 		j = i; d = (f & 1) ? '0' : ' ';
+ 11797              		.loc 1 6126 12 view .LVU3915
+ 11798 01e0 4FF0200A 		mov	r10, #32
+ 11799 01e4 FAE7     		b	.L852
+ 11800              	.LVL1382:
+ 11801              	.L855:
+ 11802              		.loc 1 6127 31 is_stmt 1 discriminator 3 view .LVU3916
+ 11803 01e6 5146     		mov	r1, r10
+ 11804 01e8 08A8     		add	r0, sp, #32
+ 11805 01ea FFF7FEFF 		bl	putc_bfd
+ 11806              	.LVL1383:
+ 11807              		.loc 1 6127 23 is_stmt 0 discriminator 3 view .LVU3917
+ 11808 01ee C846     		mov	r8, r9
+ 11809              	.LVL1384:
+ 11810              	.L853:
+ 11811              		.loc 1 6127 9 is_stmt 1 discriminator 1 view .LVU3918
+ 11812 01f0 16F0020F 		tst	r6, #2
+ 11813 01f4 04D1     		bne	.L856
+ 11814              		.loc 1 6127 23 is_stmt 0 discriminator 2 view .LVU3919
+ 11815 01f6 08F10109 		add	r9, r8, #1
+ 11816              	.LVL1385:
+ 11817              		.loc 1 6127 19 discriminator 2 view .LVU3920
+ 11818 01fa A045     		cmp	r8, r4
+ 11819 01fc F3D3     		bcc	.L855
+ 11820              		.loc 1 6127 23 view .LVU3921
+ 11821 01fe C846     		mov	r8, r9
+ 11822              	.LVL1386:
+ 11823              	.L856:
+6128:Middlewares/Third_Party/FatFs/src/ff.c **** 		do {
+ 11824              		.loc 1 6128 3 is_stmt 1 discriminator 1 view .LVU3922
+6129:Middlewares/Third_Party/FatFs/src/ff.c **** 			putc_bfd(&pb, str[--i]);
+ 11825              		.loc 1 6129 4 discriminator 1 view .LVU3923
+ 11826 0200 013F     		subs	r7, r7, #1
+ 11827              	.LVL1387:
+ 11828              		.loc 1 6129 4 is_stmt 0 discriminator 1 view .LVU3924
+ 11829 0202 07F17003 		add	r3, r7, #112
+ 11830 0206 6B44     		add	r3, sp, r3
+ 11831 0208 13F8701C 		ldrb	r1, [r3, #-112]	@ zero_extendqisi2
+ARM GAS  /tmp/cc5lWXRL.s 			page 374
+
+
+ 11832 020c 08A8     		add	r0, sp, #32
+ 11833 020e FFF7FEFF 		bl	putc_bfd
+ 11834              	.LVL1388:
+6130:Middlewares/Third_Party/FatFs/src/ff.c **** 		} while (i);
+ 11835              		.loc 1 6130 11 is_stmt 1 discriminator 1 view .LVU3925
+ 11836              		.loc 1 6130 3 is_stmt 0 discriminator 1 view .LVU3926
+ 11837 0212 002F     		cmp	r7, #0
+ 11838 0214 F4D1     		bne	.L856
+ 11839              	.LVL1389:
+ 11840              	.L857:
+6131:Middlewares/Third_Party/FatFs/src/ff.c **** 		while (j++ < w) putc_bfd(&pb, d);
+ 11841              		.loc 1 6131 9 is_stmt 1 discriminator 1 view .LVU3927
+ 11842              		.loc 1 6131 11 is_stmt 0 discriminator 1 view .LVU3928
+ 11843 0216 08F10106 		add	r6, r8, #1
+ 11844              	.LVL1390:
+ 11845              		.loc 1 6131 9 discriminator 1 view .LVU3929
+ 11846 021a A045     		cmp	r8, r4
+ 11847 021c BFF4FCAE 		bcs	.L817
+ 11848              		.loc 1 6131 19 is_stmt 1 discriminator 2 view .LVU3930
+ 11849 0220 5146     		mov	r1, r10
+ 11850 0222 08A8     		add	r0, sp, #32
+ 11851 0224 FFF7FEFF 		bl	putc_bfd
+ 11852              	.LVL1391:
+ 11853              		.loc 1 6131 11 is_stmt 0 discriminator 2 view .LVU3931
+ 11854 0228 B046     		mov	r8, r6
+ 11855 022a F4E7     		b	.L857
+ 11856              	.LVL1392:
+ 11857              	.L818:
+6132:Middlewares/Third_Party/FatFs/src/ff.c **** 	}
+6133:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6134:Middlewares/Third_Party/FatFs/src/ff.c **** 	va_end(arp);
+ 11858              		.loc 1 6134 2 is_stmt 1 view .LVU3932
+6135:Middlewares/Third_Party/FatFs/src/ff.c **** 
+6136:Middlewares/Third_Party/FatFs/src/ff.c **** 	return putc_flush(&pb);
+ 11859              		.loc 1 6136 2 view .LVU3933
+ 11860              		.loc 1 6136 9 is_stmt 0 view .LVU3934
+ 11861 022c 08A8     		add	r0, sp, #32
+ 11862 022e FFF7FEFF 		bl	putc_flush
+ 11863              	.LVL1393:
+6137:Middlewares/Third_Party/FatFs/src/ff.c **** }
+ 11864              		.loc 1 6137 1 view .LVU3935
+ 11865 0232 1DB0     		add	sp, sp, #116
+ 11866              	.LCFI128:
+ 11867              		.cfi_def_cfa_offset 44
+ 11868              		@ sp needed
+ 11869 0234 BDE8F047 		pop	{r4, r5, r6, r7, r8, r9, r10, lr}
+ 11870              	.LCFI129:
+ 11871              		.cfi_restore 14
+ 11872              		.cfi_restore 10
+ 11873              		.cfi_restore 9
+ 11874              		.cfi_restore 8
+ 11875              		.cfi_restore 7
+ 11876              		.cfi_restore 6
+ 11877              		.cfi_restore 5
+ 11878              		.cfi_restore 4
+ 11879              		.cfi_def_cfa_offset 12
+ 11880 0238 03B0     		add	sp, sp, #12
+ARM GAS  /tmp/cc5lWXRL.s 			page 375
+
+
+ 11881              	.LCFI130:
+ 11882              		.cfi_restore 3
+ 11883              		.cfi_restore 2
+ 11884              		.cfi_restore 1
+ 11885              		.cfi_def_cfa_offset 0
+ 11886 023a 7047     		bx	lr
+ 11887              		.cfi_endproc
+ 11888              	.LFE1244:
+ 11890              		.section	.bss.FatFs,"aw",%nobits
+ 11891              		.align	2
+ 11892              		.set	.LANCHOR2,. + 0
+ 11895              	FatFs:
+ 11896 0000 00000000 		.space	4
+ 11897              		.section	.bss.Files,"aw",%nobits
+ 11898              		.align	2
+ 11899              		.set	.LANCHOR0,. + 0
+ 11902              	Files:
+ 11903 0000 00000000 		.space	32
+ 11903      00000000 
+ 11903      00000000 
+ 11903      00000000 
+ 11903      00000000 
+ 11904              		.section	.bss.Fsid,"aw",%nobits
+ 11905              		.align	1
+ 11906              		.set	.LANCHOR3,. + 0
+ 11909              	Fsid:
+ 11910 0000 0000     		.space	2
+ 11911              		.section	.rodata.ExCvt,"a"
+ 11912              		.align	2
+ 11913              		.set	.LANCHOR1,. + 0
+ 11916              	ExCvt:
+ 11917 0000 43554541 		.ascii	"CUEAAAACEEEIIIAAE\222\222OOOUUYOUO\234O\236\237AIOU"
+ 11917      41414143 
+ 11917      45454549 
+ 11917      49494141 
+ 11917      4592924F 
+ 11918 0024 A5A5A6A7 		.ascii	"\245\245\246\247\250\251\252\253\254\255\256\257\260"
+ 11918      A8A9AAAB 
+ 11918      ACADAEAF 
+ 11918      B0
+ 11919 0031 B1B2B3B4 		.ascii	"\261\262\263\264AAA\270\271\272\273\274\275\276\277"
+ 11919      414141B8 
+ 11919      B9BABBBC 
+ 11919      BDBEBF
+ 11920 0040 C0C1C2C3 		.ascii	"\300\301\302\303\304\305AA\310\311\312\313\314\315\316"
+ 11920      C4C54141 
+ 11920      C8C9CACB 
+ 11920      CCCDCE
+ 11921 004f CFD1D145 		.ascii	"\317\321\321EEEIIII\331\332\333\334\335I\337O\341OO"
+ 11921      45454949 
+ 11921      4949D9DA 
+ 11921      DBDCDD49 
+ 11921      DF4FE14F 
+ 11922 0064 4F4FE6E8 		.ascii	"OO\346\350\350UUUYY\356\357\360\361\362\363\364\365"
+ 11922      E8555555 
+ 11922      5959EEEF 
+ 11922      F0F1F2F3 
+ARM GAS  /tmp/cc5lWXRL.s 			page 376
+
+
+ 11922      F4F5
+ 11923 0076 F6F7F8F9 		.ascii	"\366\367\370\371\372\373\374\375\376\377"
+ 11923      FAFBFCFD 
+ 11923      FEFF
+ 11924              		.section	.rodata.cst.0,"a"
+ 11925              		.align	2
+ 11926              		.set	.LANCHOR5,. + 0
+ 11929              	cst.0:
+ 11930 0000 0100     		.short	1
+ 11931 0002 0400     		.short	4
+ 11932 0004 1000     		.short	16
+ 11933 0006 4000     		.short	64
+ 11934 0008 0001     		.short	256
+ 11935 000a 0002     		.short	512
+ 11936 000c 0000     		.short	0
+ 11937              		.section	.rodata.cst32.1,"a"
+ 11938              		.align	2
+ 11939              		.set	.LANCHOR4,. + 0
+ 11942              	cst32.1:
+ 11943 0000 0100     		.short	1
+ 11944 0002 0200     		.short	2
+ 11945 0004 0400     		.short	4
+ 11946 0006 0800     		.short	8
+ 11947 0008 1000     		.short	16
+ 11948 000a 2000     		.short	32
+ 11949 000c 0000     		.short	0
+ 11950              		.text
+ 11951              	.Letext0:
+ 11952              		.file 2 "Middlewares/Third_Party/FatFs/src/integer.h"
+ 11953              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 11954              		.file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h"
+ 11955              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h"
+ 11956              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+ 11957              		.file 7 "Middlewares/Third_Party/FatFs/src/ff.h"
+ 11958              		.file 8 "Middlewares/Third_Party/FatFs/src/diskio.h"
+ 11959              		.file 9 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdarg.h"
+ 11960              		.file 10 ""
+ARM GAS  /tmp/cc5lWXRL.s 			page 377
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 ff.c
+     /tmp/cc5lWXRL.s:17     .text.ld_word:0000000000000000 $t
+     /tmp/cc5lWXRL.s:24     .text.ld_word:0000000000000000 ld_word
+     /tmp/cc5lWXRL.s:52     .text.ld_dword:0000000000000000 $t
+     /tmp/cc5lWXRL.s:58     .text.ld_dword:0000000000000000 ld_dword
+     /tmp/cc5lWXRL.s:97     .text.st_word:0000000000000000 $t
+     /tmp/cc5lWXRL.s:103    .text.st_word:0000000000000000 st_word
+     /tmp/cc5lWXRL.s:128    .text.st_dword:0000000000000000 $t
+     /tmp/cc5lWXRL.s:134    .text.st_dword:0000000000000000 st_dword
+     /tmp/cc5lWXRL.s:173    .text.mem_cpy:0000000000000000 $t
+     /tmp/cc5lWXRL.s:179    .text.mem_cpy:0000000000000000 mem_cpy
+     /tmp/cc5lWXRL.s:219    .text.mem_set:0000000000000000 $t
+     /tmp/cc5lWXRL.s:225    .text.mem_set:0000000000000000 mem_set
+     /tmp/cc5lWXRL.s:252    .text.mem_cmp:0000000000000000 $t
+     /tmp/cc5lWXRL.s:258    .text.mem_cmp:0000000000000000 mem_cmp
+     /tmp/cc5lWXRL.s:301    .text.chk_chr:0000000000000000 $t
+     /tmp/cc5lWXRL.s:307    .text.chk_chr:0000000000000000 chk_chr
+     /tmp/cc5lWXRL.s:343    .text.chk_lock:0000000000000000 $t
+     /tmp/cc5lWXRL.s:349    .text.chk_lock:0000000000000000 chk_lock
+     /tmp/cc5lWXRL.s:487    .text.chk_lock:0000000000000078 $d
+     /tmp/cc5lWXRL.s:492    .text.enq_lock:0000000000000000 $t
+     /tmp/cc5lWXRL.s:498    .text.enq_lock:0000000000000000 enq_lock
+     /tmp/cc5lWXRL.s:545    .text.enq_lock:000000000000001c $d
+     /tmp/cc5lWXRL.s:550    .text.inc_lock:0000000000000000 $t
+     /tmp/cc5lWXRL.s:556    .text.inc_lock:0000000000000000 inc_lock
+     /tmp/cc5lWXRL.s:735    .text.inc_lock:00000000000000a0 $d
+     /tmp/cc5lWXRL.s:740    .text.dec_lock:0000000000000000 $t
+     /tmp/cc5lWXRL.s:746    .text.dec_lock:0000000000000000 dec_lock
+     /tmp/cc5lWXRL.s:829    .text.dec_lock:000000000000003c $d
+     /tmp/cc5lWXRL.s:834    .text.clear_lock:0000000000000000 $t
+     /tmp/cc5lWXRL.s:840    .text.clear_lock:0000000000000000 clear_lock
+     /tmp/cc5lWXRL.s:921    .text.clear_lock:0000000000000038 $d
+     /tmp/cc5lWXRL.s:926    .text.clust2sect:0000000000000000 $t
+     /tmp/cc5lWXRL.s:932    .text.clust2sect:0000000000000000 clust2sect
+     /tmp/cc5lWXRL.s:972    .text.clmt_clust:0000000000000000 $t
+     /tmp/cc5lWXRL.s:978    .text.clmt_clust:0000000000000000 clmt_clust
+     /tmp/cc5lWXRL.s:1049   .text.ld_clust:0000000000000000 $t
+     /tmp/cc5lWXRL.s:1055   .text.ld_clust:0000000000000000 ld_clust
+     /tmp/cc5lWXRL.s:1111   .text.st_clust:0000000000000000 $t
+     /tmp/cc5lWXRL.s:1117   .text.st_clust:0000000000000000 st_clust
+     /tmp/cc5lWXRL.s:1166   .text.get_fileinfo:0000000000000000 $t
+     /tmp/cc5lWXRL.s:1172   .text.get_fileinfo:0000000000000000 get_fileinfo
+     /tmp/cc5lWXRL.s:1312   .rodata.create_name.str1.4:0000000000000000 $d
+     /tmp/cc5lWXRL.s:1316   .text.create_name:0000000000000000 $t
+     /tmp/cc5lWXRL.s:1322   .text.create_name:0000000000000000 create_name
+     /tmp/cc5lWXRL.s:1552   .text.create_name:00000000000000c8 $d
+     /tmp/cc5lWXRL.s:1558   .text.get_ldnumber:0000000000000000 $t
+     /tmp/cc5lWXRL.s:1564   .text.get_ldnumber:0000000000000000 get_ldnumber
+     /tmp/cc5lWXRL.s:1666   .text.putc_init:0000000000000000 $t
+     /tmp/cc5lWXRL.s:1672   .text.putc_init:0000000000000000 putc_init
+     /tmp/cc5lWXRL.s:1695   .text.validate:0000000000000000 $t
+     /tmp/cc5lWXRL.s:1701   .text.validate:0000000000000000 validate
+     /tmp/cc5lWXRL.s:1810   .text.sync_window:0000000000000000 $t
+     /tmp/cc5lWXRL.s:1816   .text.sync_window:0000000000000000 sync_window
+     /tmp/cc5lWXRL.s:1925   .text.move_window:0000000000000000 $t
+     /tmp/cc5lWXRL.s:1931   .text.move_window:0000000000000000 move_window
+ARM GAS  /tmp/cc5lWXRL.s 			page 378
+
+
+     /tmp/cc5lWXRL.s:2002   .text.check_fs:0000000000000000 $t
+     /tmp/cc5lWXRL.s:2008   .text.check_fs:0000000000000000 check_fs
+     /tmp/cc5lWXRL.s:2104   .text.check_fs:000000000000006c $d
+     /tmp/cc5lWXRL.s:2111   .text.find_volume:0000000000000000 $t
+     /tmp/cc5lWXRL.s:2117   .text.find_volume:0000000000000000 find_volume
+     /tmp/cc5lWXRL.s:2796   .text.find_volume:0000000000000318 $d
+     /tmp/cc5lWXRL.s:2803   .text.find_volume:0000000000000328 $t
+     /tmp/cc5lWXRL.s:2847   .text.put_fat:0000000000000000 $t
+     /tmp/cc5lWXRL.s:2853   .text.put_fat:0000000000000000 put_fat
+     /tmp/cc5lWXRL.s:3141   .text.get_fat:0000000000000000 $t
+     /tmp/cc5lWXRL.s:3147   .text.get_fat:0000000000000000 get_fat
+     /tmp/cc5lWXRL.s:3395   .text.dir_sdi:0000000000000000 $t
+     /tmp/cc5lWXRL.s:3401   .text.dir_sdi:0000000000000000 dir_sdi
+     /tmp/cc5lWXRL.s:3608   .text.create_chain:0000000000000000 $t
+     /tmp/cc5lWXRL.s:3614   .text.create_chain:0000000000000000 create_chain
+     /tmp/cc5lWXRL.s:3847   .text.remove_chain:0000000000000000 $t
+     /tmp/cc5lWXRL.s:3853   .text.remove_chain:0000000000000000 remove_chain
+     /tmp/cc5lWXRL.s:4014   .text.dir_remove:0000000000000000 $t
+     /tmp/cc5lWXRL.s:4020   .text.dir_remove:0000000000000000 dir_remove
+     /tmp/cc5lWXRL.s:4071   .text.dir_next:0000000000000000 $t
+     /tmp/cc5lWXRL.s:4077   .text.dir_next:0000000000000000 dir_next
+     /tmp/cc5lWXRL.s:4386   .text.dir_find:0000000000000000 $t
+     /tmp/cc5lWXRL.s:4392   .text.dir_find:0000000000000000 dir_find
+     /tmp/cc5lWXRL.s:4499   .text.follow_path:0000000000000000 $t
+     /tmp/cc5lWXRL.s:4505   .text.follow_path:0000000000000000 follow_path
+     /tmp/cc5lWXRL.s:4673   .text.dir_alloc:0000000000000000 $t
+     /tmp/cc5lWXRL.s:4679   .text.dir_alloc:0000000000000000 dir_alloc
+     /tmp/cc5lWXRL.s:4791   .text.dir_register:0000000000000000 $t
+     /tmp/cc5lWXRL.s:4797   .text.dir_register:0000000000000000 dir_register
+     /tmp/cc5lWXRL.s:4871   .text.dir_read:0000000000000000 $t
+     /tmp/cc5lWXRL.s:4877   .text.dir_read:0000000000000000 dir_read
+     /tmp/cc5lWXRL.s:4999   .text.sync_fs:0000000000000000 $t
+     /tmp/cc5lWXRL.s:5005   .text.sync_fs:0000000000000000 sync_fs
+     /tmp/cc5lWXRL.s:5119   .text.sync_fs:0000000000000080 $d
+     /tmp/cc5lWXRL.s:5125   .text.f_mount:0000000000000000 $t
+     /tmp/cc5lWXRL.s:5132   .text.f_mount:0000000000000000 f_mount
+     /tmp/cc5lWXRL.s:5248   .text.f_mount:000000000000005c $d
+     /tmp/cc5lWXRL.s:5253   .text.f_open:0000000000000000 $t
+     /tmp/cc5lWXRL.s:5260   .text.f_open:0000000000000000 f_open
+     /tmp/cc5lWXRL.s:5819   .text.f_read:0000000000000000 $t
+     /tmp/cc5lWXRL.s:5826   .text.f_read:0000000000000000 f_read
+     /tmp/cc5lWXRL.s:6256   .text.f_write:0000000000000000 $t
+     /tmp/cc5lWXRL.s:6263   .text.f_write:0000000000000000 f_write
+     /tmp/cc5lWXRL.s:6737   .text.putc_bfd:0000000000000000 $t
+     /tmp/cc5lWXRL.s:6743   .text.putc_bfd:0000000000000000 putc_bfd
+     /tmp/cc5lWXRL.s:6854   .text.putc_flush:0000000000000000 $t
+     /tmp/cc5lWXRL.s:6860   .text.putc_flush:0000000000000000 putc_flush
+     /tmp/cc5lWXRL.s:6939   .text.f_sync:0000000000000000 $t
+     /tmp/cc5lWXRL.s:6946   .text.f_sync:0000000000000000 f_sync
+     /tmp/cc5lWXRL.s:7094   .text.f_close:0000000000000000 $t
+     /tmp/cc5lWXRL.s:7101   .text.f_close:0000000000000000 f_close
+     /tmp/cc5lWXRL.s:7170   .text.f_lseek:0000000000000000 $t
+     /tmp/cc5lWXRL.s:7177   .text.f_lseek:0000000000000000 f_lseek
+     /tmp/cc5lWXRL.s:7886   .text.f_opendir:0000000000000000 $t
+     /tmp/cc5lWXRL.s:7893   .text.f_opendir:0000000000000000 f_opendir
+     /tmp/cc5lWXRL.s:8062   .text.f_closedir:0000000000000000 $t
+     /tmp/cc5lWXRL.s:8069   .text.f_closedir:0000000000000000 f_closedir
+ARM GAS  /tmp/cc5lWXRL.s 			page 379
+
+
+     /tmp/cc5lWXRL.s:8135   .text.f_readdir:0000000000000000 $t
+     /tmp/cc5lWXRL.s:8142   .text.f_readdir:0000000000000000 f_readdir
+     /tmp/cc5lWXRL.s:8247   .text.f_stat:0000000000000000 $t
+     /tmp/cc5lWXRL.s:8254   .text.f_stat:0000000000000000 f_stat
+     /tmp/cc5lWXRL.s:8347   .text.f_getfree:0000000000000000 $t
+     /tmp/cc5lWXRL.s:8354   .text.f_getfree:0000000000000000 f_getfree
+     /tmp/cc5lWXRL.s:8637   .text.f_truncate:0000000000000000 $t
+     /tmp/cc5lWXRL.s:8644   .text.f_truncate:0000000000000000 f_truncate
+     /tmp/cc5lWXRL.s:8837   .text.f_unlink:0000000000000000 $t
+     /tmp/cc5lWXRL.s:8844   .text.f_unlink:0000000000000000 f_unlink
+     /tmp/cc5lWXRL.s:9070   .text.f_mkdir:0000000000000000 $t
+     /tmp/cc5lWXRL.s:9077   .text.f_mkdir:0000000000000000 f_mkdir
+     /tmp/cc5lWXRL.s:9454   .text.f_rename:0000000000000000 $t
+     /tmp/cc5lWXRL.s:9461   .text.f_rename:0000000000000000 f_rename
+     /tmp/cc5lWXRL.s:9739   .rodata.f_mkfs.str1.4:0000000000000000 $d
+     /tmp/cc5lWXRL.s:9749   .text.f_mkfs:0000000000000000 $t
+     /tmp/cc5lWXRL.s:9756   .text.f_mkfs:0000000000000000 f_mkfs
+     /tmp/cc5lWXRL.s:10341  .text.f_mkfs:00000000000002b8 $d
+     /tmp/cc5lWXRL.s:10349  .text.f_mkfs:00000000000002cc $t
+     /tmp/cc5lWXRL.s:10985  .text.f_mkfs:000000000000064c $d
+     /tmp/cc5lWXRL.s:10994  .text.f_mkfs:0000000000000664 $t
+     /tmp/cc5lWXRL.s:11045  .text.f_gets:0000000000000000 $t
+     /tmp/cc5lWXRL.s:11052  .text.f_gets:0000000000000000 f_gets
+     /tmp/cc5lWXRL.s:11171  .text.f_putc:0000000000000000 $t
+     /tmp/cc5lWXRL.s:11178  .text.f_putc:0000000000000000 f_putc
+     /tmp/cc5lWXRL.s:11222  .text.f_puts:0000000000000000 $t
+     /tmp/cc5lWXRL.s:11229  .text.f_puts:0000000000000000 f_puts
+     /tmp/cc5lWXRL.s:11288  .text.f_printf:0000000000000000 $t
+     /tmp/cc5lWXRL.s:11295  .text.f_printf:0000000000000000 f_printf
+     /tmp/cc5lWXRL.s:11479  .text.f_printf:000000000000009e $d
+     /tmp/cc5lWXRL.s:11891  .bss.FatFs:0000000000000000 $d
+     /tmp/cc5lWXRL.s:11895  .bss.FatFs:0000000000000000 FatFs
+     /tmp/cc5lWXRL.s:11898  .bss.Files:0000000000000000 $d
+     /tmp/cc5lWXRL.s:11902  .bss.Files:0000000000000000 Files
+     /tmp/cc5lWXRL.s:11905  .bss.Fsid:0000000000000000 $d
+     /tmp/cc5lWXRL.s:11909  .bss.Fsid:0000000000000000 Fsid
+     /tmp/cc5lWXRL.s:11912  .rodata.ExCvt:0000000000000000 $d
+     /tmp/cc5lWXRL.s:11916  .rodata.ExCvt:0000000000000000 ExCvt
+     /tmp/cc5lWXRL.s:11925  .rodata.cst.0:0000000000000000 $d
+     /tmp/cc5lWXRL.s:11929  .rodata.cst.0:0000000000000000 cst.0
+     /tmp/cc5lWXRL.s:11938  .rodata.cst32.1:0000000000000000 $d
+     /tmp/cc5lWXRL.s:11942  .rodata.cst32.1:0000000000000000 cst32.1
+     /tmp/cc5lWXRL.s:11503  .text.f_printf:00000000000000b5 $d
+     /tmp/cc5lWXRL.s:11503  .text.f_printf:00000000000000b6 $t
+
+UNDEFINED SYMBOLS
+disk_status
+disk_write
+disk_read
+disk_initialize
+disk_ioctl
+get_fattime
diff --git a/build/ff.o b/build/ff.o
new file mode 100644
index 0000000..a412f01
Binary files /dev/null and b/build/ff.o differ
diff --git a/build/ff_gen_drv.d b/build/ff_gen_drv.d
new file mode 100644
index 0000000..27db340
--- /dev/null
+++ b/build/ff_gen_drv.d
@@ -0,0 +1,100 @@
+build/ff_gen_drv.o: Middlewares/Third_Party/FatFs/src/ff_gen_drv.c \
+ Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \
+ Middlewares/Third_Party/FatFs/src/diskio.h \
+ Middlewares/Third_Party/FatFs/src/integer.h \
+ Middlewares/Third_Party/FatFs/src/ff.h Inc/ffconf.h Inc/main.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/bsp_driver_sd.h \
+ Inc/fatfs_platform.h
+Middlewares/Third_Party/FatFs/src/ff_gen_drv.h:
+Middlewares/Third_Party/FatFs/src/diskio.h:
+Middlewares/Third_Party/FatFs/src/integer.h:
+Middlewares/Third_Party/FatFs/src/ff.h:
+Inc/ffconf.h:
+Inc/main.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h:
+Inc/bsp_driver_sd.h:
+Inc/fatfs_platform.h:
diff --git a/build/ff_gen_drv.lst b/build/ff_gen_drv.lst
new file mode 100644
index 0000000..ea66daf
--- /dev/null
+++ b/build/ff_gen_drv.lst
@@ -0,0 +1,476 @@
+ARM GAS  /tmp/cczj2lnx.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"ff_gen_drv.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.FATFS_LinkDriverEx,"ax",%progbits
+  17              		.align	1
+  18              		.global	FATFS_LinkDriverEx
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	FATFS_LinkDriverEx:
+  26              	.LVL0:
+  27              	.LFB1183:
+  28              		.file 1 "Middlewares/Third_Party/FatFs/src/ff_gen_drv.c"
+   1:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /**
+   2:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   ******************************************************************************
+   3:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @file    ff_gen_drv.c
+   4:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @author  MCD Application Team
+   5:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @brief   FatFs generic low level driver.
+   6:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   *****************************************************************************
+   7:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @attention
+   8:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   *
+   9:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+  10:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   *
+  11:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * This software component is licensed by ST under BSD 3-Clause license,
+  12:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * the "License"; You may not use this file except in compliance with the
+  13:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * License. You may obtain a copy of the License at:
+  14:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   *                       opensource.org/licenses/BSD-3-Clause
+  15:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   *
+  16:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   ******************************************************************************
+  17:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** **/
+  18:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /* Includes ------------------------------------------------------------------*/
+  19:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** #include "ff_gen_drv.h"
+  20:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+  21:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /* Private typedef -----------------------------------------------------------*/
+  22:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /* Private define ------------------------------------------------------------*/
+  23:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /* Private variables ---------------------------------------------------------*/
+  24:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** Disk_drvTypeDef disk = {{0},{0},{0},0};
+  25:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+  26:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /* Private function prototypes -----------------------------------------------*/
+  27:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /* Private functions ---------------------------------------------------------*/
+  28:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+  29:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /**
+  30:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @brief  Links a compatible diskio driver/lun id and increments the number of active
+ARM GAS  /tmp/cczj2lnx.s 			page 2
+
+
+  31:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   *         linked drivers.
+  32:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @note   The number of linked drivers (volumes) is up to 10 due to FatFs limits.
+  33:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @param  drv: pointer to the disk IO Driver structure
+  34:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @param  path: pointer to the logical drive path
+  35:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @param  lun : only used for USB Key Disk to add multi-lun management
+  36:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****             else the parameter must be equal to 0
+  37:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @retval Returns 0 in case of success, otherwise 1.
+  38:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   */
+  39:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, uint8_t lun)
+  40:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** {
+  29              		.loc 1 40 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  41:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   uint8_t ret = 1;
+  33              		.loc 1 41 3 view .LVU1
+  42:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   uint8_t DiskNum = 0;
+  34              		.loc 1 42 3 view .LVU2
+  43:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+  44:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   if(disk.nbr < _VOLUMES)
+  35              		.loc 1 44 3 view .LVU3
+  36              		.loc 1 44 10 is_stmt 0 view .LVU4
+  37 0000 134B     		ldr	r3, .L8
+  38 0002 5B7A     		ldrb	r3, [r3, #9]	@ zero_extendqisi2
+  39              		.loc 1 44 5 view .LVU5
+  40 0004 13BB     		cbnz	r3, .L3
+  40:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   uint8_t ret = 1;
+  41              		.loc 1 40 1 view .LVU6
+  42 0006 10B5     		push	{r4, lr}
+  43              	.LCFI0:
+  44              		.cfi_def_cfa_offset 8
+  45              		.cfi_offset 4, -8
+  46              		.cfi_offset 14, -4
+  47 0008 0446     		mov	r4, r0
+  48 000a 03F0FF00 		and	r0, r3, #255
+  49              	.LVL1:
+  45:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   {
+  46:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     disk.is_initialized[disk.nbr] = 0;
+  50              		.loc 1 46 5 is_stmt 1 view .LVU7
+  51              		.loc 1 46 29 is_stmt 0 view .LVU8
+  52 000e 104B     		ldr	r3, .L8
+  53 0010 93F809C0 		ldrb	ip, [r3, #9]	@ zero_extendqisi2
+  54 0014 5FFA8CFC 		uxtb	ip, ip
+  55              		.loc 1 46 35 view .LVU9
+  56 0018 4FF0000E 		mov	lr, #0
+  57 001c 03F80CE0 		strb	lr, [r3, ip]
+  47:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     disk.drv[disk.nbr] = drv;
+  58              		.loc 1 47 5 is_stmt 1 view .LVU10
+  59              		.loc 1 47 18 is_stmt 0 view .LVU11
+  60 0020 93F809C0 		ldrb	ip, [r3, #9]	@ zero_extendqisi2
+  61              		.loc 1 47 24 view .LVU12
+  62 0024 03EB8C0C 		add	ip, r3, ip, lsl #2
+  63 0028 CCF80440 		str	r4, [ip, #4]
+  48:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     disk.lun[disk.nbr] = lun;
+  64              		.loc 1 48 5 is_stmt 1 view .LVU13
+  65              		.loc 1 48 18 is_stmt 0 view .LVU14
+  66 002c 5C7A     		ldrb	r4, [r3, #9]	@ zero_extendqisi2
+ARM GAS  /tmp/cczj2lnx.s 			page 3
+
+
+  67              	.LVL2:
+  68              		.loc 1 48 24 view .LVU15
+  69 002e 1C44     		add	r4, r4, r3
+  70 0030 2272     		strb	r2, [r4, #8]
+  49:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     DiskNum = disk.nbr++;
+  71              		.loc 1 49 5 is_stmt 1 view .LVU16
+  72              		.loc 1 49 19 is_stmt 0 view .LVU17
+  73 0032 5A7A     		ldrb	r2, [r3, #9]	@ zero_extendqisi2
+  74              	.LVL3:
+  75              		.loc 1 49 23 view .LVU18
+  76 0034 541C     		adds	r4, r2, #1
+  77              	.LVL4:
+  78              		.loc 1 49 23 view .LVU19
+  79 0036 E4B2     		uxtb	r4, r4
+  80 0038 5C72     		strb	r4, [r3, #9]
+  81              	.LVL5:
+  50:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     path[0] = DiskNum + '0';
+  82              		.loc 1 50 5 is_stmt 1 view .LVU20
+  83              		.loc 1 50 23 is_stmt 0 view .LVU21
+  84 003a 3032     		adds	r2, r2, #48
+  85              	.LVL6:
+  86              		.loc 1 50 13 view .LVU22
+  87 003c 0A70     		strb	r2, [r1]
+  88              	.LVL7:
+  51:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     path[1] = ':';
+  89              		.loc 1 51 5 is_stmt 1 view .LVU23
+  90              		.loc 1 51 13 is_stmt 0 view .LVU24
+  91 003e 3A23     		movs	r3, #58
+  92 0040 4B70     		strb	r3, [r1, #1]
+  52:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     path[2] = '/';
+  93              		.loc 1 52 5 is_stmt 1 view .LVU25
+  94              		.loc 1 52 13 is_stmt 0 view .LVU26
+  95 0042 2F23     		movs	r3, #47
+  96 0044 8B70     		strb	r3, [r1, #2]
+  53:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     path[3] = 0;
+  97              		.loc 1 53 5 is_stmt 1 view .LVU27
+  98              		.loc 1 53 13 is_stmt 0 view .LVU28
+  99 0046 81F803E0 		strb	lr, [r1, #3]
+  54:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     ret = 0;
+ 100              		.loc 1 54 5 is_stmt 1 view .LVU29
+ 101              	.LVL8:
+  55:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   }
+  56:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+  57:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   return ret;
+ 102              		.loc 1 57 3 view .LVU30
+  58:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** }
+ 103              		.loc 1 58 1 is_stmt 0 view .LVU31
+ 104 004a 10BD     		pop	{r4, pc}
+ 105              	.LVL9:
+ 106              	.L3:
+ 107              	.LCFI1:
+ 108              		.cfi_def_cfa_offset 0
+ 109              		.cfi_restore 4
+ 110              		.cfi_restore 14
+  41:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   uint8_t DiskNum = 0;
+ 111              		.loc 1 41 11 view .LVU32
+ 112 004c 0120     		movs	r0, #1
+ARM GAS  /tmp/cczj2lnx.s 			page 4
+
+
+ 113              	.LVL10:
+  57:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** }
+ 114              		.loc 1 57 3 is_stmt 1 view .LVU33
+ 115              		.loc 1 58 1 is_stmt 0 view .LVU34
+ 116 004e 7047     		bx	lr
+ 117              	.L9:
+ 118              		.align	2
+ 119              	.L8:
+ 120 0050 00000000 		.word	.LANCHOR0
+ 121              		.cfi_endproc
+ 122              	.LFE1183:
+ 124              		.section	.text.FATFS_LinkDriver,"ax",%progbits
+ 125              		.align	1
+ 126              		.global	FATFS_LinkDriver
+ 127              		.syntax unified
+ 128              		.thumb
+ 129              		.thumb_func
+ 130              		.fpu fpv5-d16
+ 132              	FATFS_LinkDriver:
+ 133              	.LVL11:
+ 134              	.LFB1184:
+  59:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+  60:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /**
+  61:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @brief  Links a compatible diskio driver and increments the number of active
+  62:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   *         linked drivers.
+  63:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @note   The number of linked drivers (volumes) is up to 10 due to FatFs limits
+  64:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @param  drv: pointer to the disk IO Driver structure
+  65:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @param  path: pointer to the logical drive path
+  66:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @retval Returns 0 in case of success, otherwise 1.
+  67:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   */
+  68:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path)
+  69:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** {
+ 135              		.loc 1 69 1 is_stmt 1 view -0
+ 136              		.cfi_startproc
+ 137              		@ args = 0, pretend = 0, frame = 0
+ 138              		@ frame_needed = 0, uses_anonymous_args = 0
+ 139              		.loc 1 69 1 is_stmt 0 view .LVU36
+ 140 0000 08B5     		push	{r3, lr}
+ 141              	.LCFI2:
+ 142              		.cfi_def_cfa_offset 8
+ 143              		.cfi_offset 3, -8
+ 144              		.cfi_offset 14, -4
+  70:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   return FATFS_LinkDriverEx(drv, path, 0);
+ 145              		.loc 1 70 3 is_stmt 1 view .LVU37
+ 146              		.loc 1 70 10 is_stmt 0 view .LVU38
+ 147 0002 0022     		movs	r2, #0
+ 148 0004 FFF7FEFF 		bl	FATFS_LinkDriverEx
+ 149              	.LVL12:
+  71:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** }
+ 150              		.loc 1 71 1 view .LVU39
+ 151 0008 08BD     		pop	{r3, pc}
+ 152              		.cfi_endproc
+ 153              	.LFE1184:
+ 155              		.section	.text.FATFS_UnLinkDriverEx,"ax",%progbits
+ 156              		.align	1
+ 157              		.global	FATFS_UnLinkDriverEx
+ 158              		.syntax unified
+ARM GAS  /tmp/cczj2lnx.s 			page 5
+
+
+ 159              		.thumb
+ 160              		.thumb_func
+ 161              		.fpu fpv5-d16
+ 163              	FATFS_UnLinkDriverEx:
+ 164              	.LVL13:
+ 165              	.LFB1185:
+  72:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+  73:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /**
+  74:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @brief  Unlinks a diskio driver and decrements the number of active linked
+  75:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   *         drivers.
+  76:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @param  path: pointer to the logical drive path
+  77:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @param  lun : not used
+  78:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @retval Returns 0 in case of success, otherwise 1.
+  79:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   */
+  80:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** uint8_t FATFS_UnLinkDriverEx(char *path, uint8_t lun)
+  81:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** {
+ 166              		.loc 1 81 1 is_stmt 1 view -0
+ 167              		.cfi_startproc
+ 168              		@ args = 0, pretend = 0, frame = 0
+ 169              		@ frame_needed = 0, uses_anonymous_args = 0
+ 170              		@ link register save eliminated.
+  82:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   uint8_t DiskNum = 0;
+ 171              		.loc 1 82 3 view .LVU41
+  83:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   uint8_t ret = 1;
+ 172              		.loc 1 83 3 view .LVU42
+  84:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+  85:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   if(disk.nbr >= 1)
+ 173              		.loc 1 85 3 view .LVU43
+ 174              		.loc 1 85 10 is_stmt 0 view .LVU44
+ 175 0000 0D4B     		ldr	r3, .L16
+ 176 0002 5B7A     		ldrb	r3, [r3, #9]	@ zero_extendqisi2
+ 177              		.loc 1 85 5 view .LVU45
+ 178 0004 9BB1     		cbz	r3, .L14
+  86:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   {
+  87:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     DiskNum = path[0] - '0';
+ 179              		.loc 1 87 5 is_stmt 1 view .LVU46
+ 180              		.loc 1 87 19 is_stmt 0 view .LVU47
+ 181 0006 0378     		ldrb	r3, [r0]	@ zero_extendqisi2
+ 182              		.loc 1 87 13 view .LVU48
+ 183 0008 303B     		subs	r3, r3, #48
+ 184 000a DBB2     		uxtb	r3, r3
+ 185              	.LVL14:
+  88:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     if(disk.drv[DiskNum] != 0)
+ 186              		.loc 1 88 5 is_stmt 1 view .LVU49
+ 187              		.loc 1 88 16 is_stmt 0 view .LVU50
+ 188 000c 0A4A     		ldr	r2, .L16
+ 189 000e 02EB8302 		add	r2, r2, r3, lsl #2
+ 190 0012 5268     		ldr	r2, [r2, #4]
+ 191              		.loc 1 88 7 view .LVU51
+ 192 0014 6AB1     		cbz	r2, .L15
+  89:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     {
+  90:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****       disk.drv[DiskNum] = 0;
+ 193              		.loc 1 90 7 is_stmt 1 view .LVU52
+ 194              		.loc 1 90 25 is_stmt 0 view .LVU53
+ 195 0016 084A     		ldr	r2, .L16
+ 196 0018 02EB8301 		add	r1, r2, r3, lsl #2
+ 197              	.LVL15:
+ARM GAS  /tmp/cczj2lnx.s 			page 6
+
+
+ 198              		.loc 1 90 25 view .LVU54
+ 199 001c 0020     		movs	r0, #0
+ 200              	.LVL16:
+ 201              		.loc 1 90 25 view .LVU55
+ 202 001e 4860     		str	r0, [r1, #4]
+  91:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****       disk.lun[DiskNum] = 0;
+ 203              		.loc 1 91 7 is_stmt 1 view .LVU56
+ 204              		.loc 1 91 25 is_stmt 0 view .LVU57
+ 205 0020 1344     		add	r3, r3, r2
+ 206 0022 1872     		strb	r0, [r3, #8]
+  92:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****       disk.nbr--;
+ 207              		.loc 1 92 7 is_stmt 1 view .LVU58
+ 208              		.loc 1 92 11 is_stmt 0 view .LVU59
+ 209 0024 537A     		ldrb	r3, [r2, #9]	@ zero_extendqisi2
+ 210              		.loc 1 92 15 view .LVU60
+ 211 0026 013B     		subs	r3, r3, #1
+ 212 0028 DBB2     		uxtb	r3, r3
+ 213 002a 5372     		strb	r3, [r2, #9]
+  93:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****       ret = 0;
+ 214              		.loc 1 93 7 is_stmt 1 view .LVU61
+ 215              	.LVL17:
+ 216              		.loc 1 93 7 is_stmt 0 view .LVU62
+ 217 002c 7047     		bx	lr
+ 218              	.LVL18:
+ 219              	.L14:
+  83:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+ 220              		.loc 1 83 11 view .LVU63
+ 221 002e 0120     		movs	r0, #1
+ 222              	.LVL19:
+  83:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+ 223              		.loc 1 83 11 view .LVU64
+ 224 0030 7047     		bx	lr
+ 225              	.LVL20:
+ 226              	.L15:
+  83:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+ 227              		.loc 1 83 11 view .LVU65
+ 228 0032 0120     		movs	r0, #1
+ 229              	.LVL21:
+  94:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****     }
+  95:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   }
+  96:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+  97:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   return ret;
+ 230              		.loc 1 97 3 is_stmt 1 view .LVU66
+  98:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** }
+ 231              		.loc 1 98 1 is_stmt 0 view .LVU67
+ 232 0034 7047     		bx	lr
+ 233              	.L17:
+ 234 0036 00BF     		.align	2
+ 235              	.L16:
+ 236 0038 00000000 		.word	.LANCHOR0
+ 237              		.cfi_endproc
+ 238              	.LFE1185:
+ 240              		.section	.text.FATFS_UnLinkDriver,"ax",%progbits
+ 241              		.align	1
+ 242              		.global	FATFS_UnLinkDriver
+ 243              		.syntax unified
+ 244              		.thumb
+ARM GAS  /tmp/cczj2lnx.s 			page 7
+
+
+ 245              		.thumb_func
+ 246              		.fpu fpv5-d16
+ 248              	FATFS_UnLinkDriver:
+ 249              	.LVL22:
+ 250              	.LFB1186:
+  99:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+ 100:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /**
+ 101:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @brief  Unlinks a diskio driver and decrements the number of active linked
+ 102:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   *         drivers.
+ 103:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @param  path: pointer to the logical drive path
+ 104:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @retval Returns 0 in case of success, otherwise 1.
+ 105:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   */
+ 106:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** uint8_t FATFS_UnLinkDriver(char *path)
+ 107:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** {
+ 251              		.loc 1 107 1 is_stmt 1 view -0
+ 252              		.cfi_startproc
+ 253              		@ args = 0, pretend = 0, frame = 0
+ 254              		@ frame_needed = 0, uses_anonymous_args = 0
+ 255              		.loc 1 107 1 is_stmt 0 view .LVU69
+ 256 0000 08B5     		push	{r3, lr}
+ 257              	.LCFI3:
+ 258              		.cfi_def_cfa_offset 8
+ 259              		.cfi_offset 3, -8
+ 260              		.cfi_offset 14, -4
+ 108:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   return FATFS_UnLinkDriverEx(path, 0);
+ 261              		.loc 1 108 3 is_stmt 1 view .LVU70
+ 262              		.loc 1 108 10 is_stmt 0 view .LVU71
+ 263 0002 0021     		movs	r1, #0
+ 264 0004 FFF7FEFF 		bl	FATFS_UnLinkDriverEx
+ 265              	.LVL23:
+ 109:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** }
+ 266              		.loc 1 109 1 view .LVU72
+ 267 0008 08BD     		pop	{r3, pc}
+ 268              		.cfi_endproc
+ 269              	.LFE1186:
+ 271              		.section	.text.FATFS_GetAttachedDriversNbr,"ax",%progbits
+ 272              		.align	1
+ 273              		.global	FATFS_GetAttachedDriversNbr
+ 274              		.syntax unified
+ 275              		.thumb
+ 276              		.thumb_func
+ 277              		.fpu fpv5-d16
+ 279              	FATFS_GetAttachedDriversNbr:
+ 280              	.LFB1187:
+ 110:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** 
+ 111:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /**
+ 112:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @brief  Gets number of linked drivers to the FatFs module.
+ 113:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @param  None
+ 114:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   * @retval Number of attached drivers.
+ 115:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   */
+ 116:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** uint8_t FATFS_GetAttachedDriversNbr(void)
+ 117:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** {
+ 281              		.loc 1 117 1 is_stmt 1 view -0
+ 282              		.cfi_startproc
+ 283              		@ args = 0, pretend = 0, frame = 0
+ 284              		@ frame_needed = 0, uses_anonymous_args = 0
+ 285              		@ link register save eliminated.
+ARM GAS  /tmp/cczj2lnx.s 			page 8
+
+
+ 118:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c ****   return disk.nbr;
+ 286              		.loc 1 118 3 view .LVU74
+ 287              		.loc 1 118 14 is_stmt 0 view .LVU75
+ 288 0000 014B     		ldr	r3, .L21
+ 289 0002 587A     		ldrb	r0, [r3, #9]	@ zero_extendqisi2
+ 119:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** }
+ 290              		.loc 1 119 1 view .LVU76
+ 291 0004 7047     		bx	lr
+ 292              	.L22:
+ 293 0006 00BF     		.align	2
+ 294              	.L21:
+ 295 0008 00000000 		.word	.LANCHOR0
+ 296              		.cfi_endproc
+ 297              	.LFE1187:
+ 299              		.global	disk
+ 300              		.section	.bss.disk,"aw",%nobits
+ 301              		.align	2
+ 302              		.set	.LANCHOR0,. + 0
+ 305              	disk:
+ 306 0000 00000000 		.space	12
+ 306      00000000 
+ 306      00000000 
+ 307              		.text
+ 308              	.Letext0:
+ 309              		.file 2 "Middlewares/Third_Party/FatFs/src/integer.h"
+ 310              		.file 3 "Middlewares/Third_Party/FatFs/src/diskio.h"
+ 311              		.file 4 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 312              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h"
+ 313              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h"
+ 314              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+ 315              		.file 8 "Middlewares/Third_Party/FatFs/src/ff_gen_drv.h"
+ARM GAS  /tmp/cczj2lnx.s 			page 9
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 ff_gen_drv.c
+     /tmp/cczj2lnx.s:17     .text.FATFS_LinkDriverEx:0000000000000000 $t
+     /tmp/cczj2lnx.s:25     .text.FATFS_LinkDriverEx:0000000000000000 FATFS_LinkDriverEx
+     /tmp/cczj2lnx.s:120    .text.FATFS_LinkDriverEx:0000000000000050 $d
+     /tmp/cczj2lnx.s:125    .text.FATFS_LinkDriver:0000000000000000 $t
+     /tmp/cczj2lnx.s:132    .text.FATFS_LinkDriver:0000000000000000 FATFS_LinkDriver
+     /tmp/cczj2lnx.s:156    .text.FATFS_UnLinkDriverEx:0000000000000000 $t
+     /tmp/cczj2lnx.s:163    .text.FATFS_UnLinkDriverEx:0000000000000000 FATFS_UnLinkDriverEx
+     /tmp/cczj2lnx.s:236    .text.FATFS_UnLinkDriverEx:0000000000000038 $d
+     /tmp/cczj2lnx.s:241    .text.FATFS_UnLinkDriver:0000000000000000 $t
+     /tmp/cczj2lnx.s:248    .text.FATFS_UnLinkDriver:0000000000000000 FATFS_UnLinkDriver
+     /tmp/cczj2lnx.s:272    .text.FATFS_GetAttachedDriversNbr:0000000000000000 $t
+     /tmp/cczj2lnx.s:279    .text.FATFS_GetAttachedDriversNbr:0000000000000000 FATFS_GetAttachedDriversNbr
+     /tmp/cczj2lnx.s:295    .text.FATFS_GetAttachedDriversNbr:0000000000000008 $d
+     /tmp/cczj2lnx.s:305    .bss.disk:0000000000000000 disk
+     /tmp/cczj2lnx.s:301    .bss.disk:0000000000000000 $d
+
+NO UNDEFINED SYMBOLS
diff --git a/build/ff_gen_drv.o b/build/ff_gen_drv.o
new file mode 100644
index 0000000..9624276
Binary files /dev/null and b/build/ff_gen_drv.o differ
diff --git a/build/main.d b/build/main.d
new file mode 100644
index 0000000..95e55c9
--- /dev/null
+++ b/build/main.d
@@ -0,0 +1,108 @@
+build/main.o: Src/main.c Inc/main.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/fatfs.h \
+ Middlewares/Third_Party/FatFs/src/ff.h \
+ Middlewares/Third_Party/FatFs/src/integer.h Inc/ffconf.h Inc/main.h \
+ Inc/bsp_driver_sd.h Inc/fatfs_platform.h \
+ Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \
+ Middlewares/Third_Party/FatFs/src/diskio.h \
+ Middlewares/Third_Party/FatFs/src/ff.h Inc/sd_diskio.h \
+ Inc/File_Handling.h Inc/fatfs.h
+Inc/main.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h:
+Inc/fatfs.h:
+Middlewares/Third_Party/FatFs/src/ff.h:
+Middlewares/Third_Party/FatFs/src/integer.h:
+Inc/ffconf.h:
+Inc/main.h:
+Inc/bsp_driver_sd.h:
+Inc/fatfs_platform.h:
+Middlewares/Third_Party/FatFs/src/ff_gen_drv.h:
+Middlewares/Third_Party/FatFs/src/diskio.h:
+Middlewares/Third_Party/FatFs/src/ff.h:
+Inc/sd_diskio.h:
+Inc/File_Handling.h:
+Inc/fatfs.h:
diff --git a/build/main.lst b/build/main.lst
new file mode 100644
index 0000000..3d3986c
--- /dev/null
+++ b/build/main.lst
@@ -0,0 +1,32056 @@
+ARM GAS  /tmp/ccdsDELB.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"main.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.NVIC_EncodePriority,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	NVIC_EncodePriority:
+  25              	.LVL0:
+  26              	.LFB113:
+  27              		.file 1 "Drivers/CMSIS/Include/core_cm7.h"
+   1:Drivers/CMSIS/Include/core_cm7.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/core_cm7.h ****  * @file     core_cm7.h
+   3:Drivers/CMSIS/Include/core_cm7.h ****  * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+   4:Drivers/CMSIS/Include/core_cm7.h ****  * @version  V5.0.8
+   5:Drivers/CMSIS/Include/core_cm7.h ****  * @date     04. June 2018
+   6:Drivers/CMSIS/Include/core_cm7.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/core_cm7.h **** /*
+   8:Drivers/CMSIS/Include/core_cm7.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/core_cm7.h ****  *
+  10:Drivers/CMSIS/Include/core_cm7.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/core_cm7.h ****  *
+  12:Drivers/CMSIS/Include/core_cm7.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/core_cm7.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/core_cm7.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/core_cm7.h ****  *
+  16:Drivers/CMSIS/Include/core_cm7.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/core_cm7.h ****  *
+  18:Drivers/CMSIS/Include/core_cm7.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/core_cm7.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/core_cm7.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/core_cm7.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/core_cm7.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/core_cm7.h ****  */
+  24:Drivers/CMSIS/Include/core_cm7.h **** 
+  25:Drivers/CMSIS/Include/core_cm7.h **** #if   defined ( __ICCARM__ )
+  26:Drivers/CMSIS/Include/core_cm7.h ****   #pragma system_include         /* treat file as system include file for MISRA check */
+  27:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__clang__)
+  28:Drivers/CMSIS/Include/core_cm7.h ****   #pragma clang system_header   /* treat file as system include file */
+  29:Drivers/CMSIS/Include/core_cm7.h **** #endif
+  30:Drivers/CMSIS/Include/core_cm7.h **** 
+  31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC
+ARM GAS  /tmp/ccdsDELB.s 			page 2
+
+
+  32:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_GENERIC
+  33:Drivers/CMSIS/Include/core_cm7.h **** 
+  34:Drivers/CMSIS/Include/core_cm7.h **** #include 
+  35:Drivers/CMSIS/Include/core_cm7.h **** 
+  36:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
+  37:Drivers/CMSIS/Include/core_cm7.h ****  extern "C" {
+  38:Drivers/CMSIS/Include/core_cm7.h **** #endif
+  39:Drivers/CMSIS/Include/core_cm7.h **** 
+  40:Drivers/CMSIS/Include/core_cm7.h **** /**
+  41:Drivers/CMSIS/Include/core_cm7.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  42:Drivers/CMSIS/Include/core_cm7.h ****   CMSIS violates the following MISRA-C:2004 rules:
+  43:Drivers/CMSIS/Include/core_cm7.h **** 
+  44:Drivers/CMSIS/Include/core_cm7.h ****    \li Required Rule 8.5, object/function definition in header file.

+  45:Drivers/CMSIS/Include/core_cm7.h ****      Function definitions in header files are used to allow 'inlining'.
+  46:Drivers/CMSIS/Include/core_cm7.h **** 
+  47:Drivers/CMSIS/Include/core_cm7.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+  48:Drivers/CMSIS/Include/core_cm7.h ****      Unions are used for effective representation of core registers.
+  49:Drivers/CMSIS/Include/core_cm7.h **** 
+  50:Drivers/CMSIS/Include/core_cm7.h ****    \li Advisory Rule 19.7, Function-like macro defined.

+  51:Drivers/CMSIS/Include/core_cm7.h ****      Function-like macros are used to allow more efficient code.
+  52:Drivers/CMSIS/Include/core_cm7.h ****  */
+  53:Drivers/CMSIS/Include/core_cm7.h **** 
+  54:Drivers/CMSIS/Include/core_cm7.h **** 
+  55:Drivers/CMSIS/Include/core_cm7.h **** /*******************************************************************************
+  56:Drivers/CMSIS/Include/core_cm7.h ****  *                 CMSIS definitions
+  57:Drivers/CMSIS/Include/core_cm7.h ****  ******************************************************************************/
+  58:Drivers/CMSIS/Include/core_cm7.h **** /**
+  59:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup Cortex_M7
+  60:Drivers/CMSIS/Include/core_cm7.h ****   @{
+  61:Drivers/CMSIS/Include/core_cm7.h ****  */
+  62:Drivers/CMSIS/Include/core_cm7.h **** 
+  63:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_version.h"
+  64:Drivers/CMSIS/Include/core_cm7.h **** 
+  65:Drivers/CMSIS/Include/core_cm7.h **** /* CMSIS CM7 definitions */
+  66:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:1
+  67:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0
+  68:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+  69:Drivers/CMSIS/Include/core_cm7.h ****                                     __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS
+  70:Drivers/CMSIS/Include/core_cm7.h **** 
+  71:Drivers/CMSIS/Include/core_cm7.h **** #define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+  72:Drivers/CMSIS/Include/core_cm7.h **** 
+  73:Drivers/CMSIS/Include/core_cm7.h **** /** __FPU_USED indicates whether an FPU is used or not.
+  74:Drivers/CMSIS/Include/core_cm7.h ****     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
+  75:Drivers/CMSIS/Include/core_cm7.h **** */
+  76:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM )
+  77:Drivers/CMSIS/Include/core_cm7.h ****   #if defined __TARGET_FPU_VFP
+  78:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+  79:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+  80:Drivers/CMSIS/Include/core_cm7.h ****     #else
+  81:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+  82:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+  83:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+  84:Drivers/CMSIS/Include/core_cm7.h ****   #else
+  85:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+  86:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+  87:Drivers/CMSIS/Include/core_cm7.h **** 
+  88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ARM GAS  /tmp/ccdsDELB.s 			page 3
+
+
+  89:Drivers/CMSIS/Include/core_cm7.h ****   #if defined __ARM_PCS_VFP
+  90:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+  91:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+  92:Drivers/CMSIS/Include/core_cm7.h ****     #else
+  93:Drivers/CMSIS/Include/core_cm7.h ****       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
+  94:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+  95:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+  96:Drivers/CMSIS/Include/core_cm7.h ****   #else
+  97:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+  98:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+  99:Drivers/CMSIS/Include/core_cm7.h **** 
+ 100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ )
+ 101:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ 102:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 103:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+ 104:Drivers/CMSIS/Include/core_cm7.h ****     #else
+ 105:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 106:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+ 107:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+ 108:Drivers/CMSIS/Include/core_cm7.h ****   #else
+ 109:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+ 110:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 111:Drivers/CMSIS/Include/core_cm7.h **** 
+ 112:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __ICCARM__ )
+ 113:Drivers/CMSIS/Include/core_cm7.h ****   #if defined __ARMVFP__
+ 114:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 115:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+ 116:Drivers/CMSIS/Include/core_cm7.h ****     #else
+ 117:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 118:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+ 119:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+ 120:Drivers/CMSIS/Include/core_cm7.h ****   #else
+ 121:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+ 122:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 123:Drivers/CMSIS/Include/core_cm7.h **** 
+ 124:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TI_ARM__ )
+ 125:Drivers/CMSIS/Include/core_cm7.h ****   #if defined __TI_VFP_SUPPORT__
+ 126:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 127:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+ 128:Drivers/CMSIS/Include/core_cm7.h ****     #else
+ 129:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 130:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+ 131:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+ 132:Drivers/CMSIS/Include/core_cm7.h ****   #else
+ 133:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+ 134:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 135:Drivers/CMSIS/Include/core_cm7.h **** 
+ 136:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TASKING__ )
+ 137:Drivers/CMSIS/Include/core_cm7.h ****   #if defined __FPU_VFP__
+ 138:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 139:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+ 140:Drivers/CMSIS/Include/core_cm7.h ****     #else
+ 141:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 142:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+ 143:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+ 144:Drivers/CMSIS/Include/core_cm7.h ****   #else
+ 145:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+ARM GAS  /tmp/ccdsDELB.s 			page 4
+
+
+ 146:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 147:Drivers/CMSIS/Include/core_cm7.h **** 
+ 148:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __CSMC__ )
+ 149:Drivers/CMSIS/Include/core_cm7.h ****   #if ( __CSMC__ & 0x400U)
+ 150:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 151:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+ 152:Drivers/CMSIS/Include/core_cm7.h ****     #else
+ 153:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 154:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+ 155:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+ 156:Drivers/CMSIS/Include/core_cm7.h ****   #else
+ 157:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+ 158:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 159:Drivers/CMSIS/Include/core_cm7.h **** 
+ 160:Drivers/CMSIS/Include/core_cm7.h **** #endif
+ 161:Drivers/CMSIS/Include/core_cm7.h **** 
+ 162:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+ 163:Drivers/CMSIS/Include/core_cm7.h **** 
+ 164:Drivers/CMSIS/Include/core_cm7.h **** 
+ 165:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
+ 166:Drivers/CMSIS/Include/core_cm7.h **** }
+ 167:Drivers/CMSIS/Include/core_cm7.h **** #endif
+ 168:Drivers/CMSIS/Include/core_cm7.h **** 
+ 169:Drivers/CMSIS/Include/core_cm7.h **** #endif /* __CORE_CM7_H_GENERIC */
+ 170:Drivers/CMSIS/Include/core_cm7.h **** 
+ 171:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CMSIS_GENERIC
+ 172:Drivers/CMSIS/Include/core_cm7.h **** 
+ 173:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_DEPENDANT
+ 174:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_DEPENDANT
+ 175:Drivers/CMSIS/Include/core_cm7.h **** 
+ 176:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
+ 177:Drivers/CMSIS/Include/core_cm7.h ****  extern "C" {
+ 178:Drivers/CMSIS/Include/core_cm7.h **** #endif
+ 179:Drivers/CMSIS/Include/core_cm7.h **** 
+ 180:Drivers/CMSIS/Include/core_cm7.h **** /* check device defines and use defaults */
+ 181:Drivers/CMSIS/Include/core_cm7.h **** #if defined __CHECK_DEVICE_DEFINES
+ 182:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __CM7_REV
+ 183:Drivers/CMSIS/Include/core_cm7.h ****     #define __CM7_REV               0x0000U
+ 184:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__CM7_REV not defined in device header file; using default!"
+ 185:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 186:Drivers/CMSIS/Include/core_cm7.h **** 
+ 187:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __FPU_PRESENT
+ 188:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_PRESENT             0U
+ 189:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__FPU_PRESENT not defined in device header file; using default!"
+ 190:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 191:Drivers/CMSIS/Include/core_cm7.h **** 
+ 192:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __MPU_PRESENT
+ 193:Drivers/CMSIS/Include/core_cm7.h ****     #define __MPU_PRESENT             0U
+ 194:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__MPU_PRESENT not defined in device header file; using default!"
+ 195:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 196:Drivers/CMSIS/Include/core_cm7.h **** 
+ 197:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __ICACHE_PRESENT
+ 198:Drivers/CMSIS/Include/core_cm7.h ****     #define __ICACHE_PRESENT          0U
+ 199:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ 200:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 201:Drivers/CMSIS/Include/core_cm7.h **** 
+ 202:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __DCACHE_PRESENT
+ARM GAS  /tmp/ccdsDELB.s 			page 5
+
+
+ 203:Drivers/CMSIS/Include/core_cm7.h ****     #define __DCACHE_PRESENT          0U
+ 204:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ 205:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 206:Drivers/CMSIS/Include/core_cm7.h **** 
+ 207:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __DTCM_PRESENT
+ 208:Drivers/CMSIS/Include/core_cm7.h ****     #define __DTCM_PRESENT            0U
+ 209:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+ 210:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 211:Drivers/CMSIS/Include/core_cm7.h **** 
+ 212:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __NVIC_PRIO_BITS
+ 213:Drivers/CMSIS/Include/core_cm7.h ****     #define __NVIC_PRIO_BITS          3U
+ 214:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ 215:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 216:Drivers/CMSIS/Include/core_cm7.h **** 
+ 217:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __Vendor_SysTickConfig
+ 218:Drivers/CMSIS/Include/core_cm7.h ****     #define __Vendor_SysTickConfig    0U
+ 219:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ 220:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 221:Drivers/CMSIS/Include/core_cm7.h **** #endif
+ 222:Drivers/CMSIS/Include/core_cm7.h **** 
+ 223:Drivers/CMSIS/Include/core_cm7.h **** /* IO definitions (access restrictions to peripheral registers) */
+ 224:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 225:Drivers/CMSIS/Include/core_cm7.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
+ 226:Drivers/CMSIS/Include/core_cm7.h **** 
+ 227:Drivers/CMSIS/Include/core_cm7.h ****     IO Type Qualifiers are used
+ 228:Drivers/CMSIS/Include/core_cm7.h ****     \li to specify the access to peripheral variables.
+ 229:Drivers/CMSIS/Include/core_cm7.h ****     \li for automatic generation of peripheral register debug information.
+ 230:Drivers/CMSIS/Include/core_cm7.h **** */
+ 231:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
+ 232:Drivers/CMSIS/Include/core_cm7.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
+ 233:Drivers/CMSIS/Include/core_cm7.h **** #else
+ 234:Drivers/CMSIS/Include/core_cm7.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
+ 235:Drivers/CMSIS/Include/core_cm7.h **** #endif
+ 236:Drivers/CMSIS/Include/core_cm7.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
+ 237:Drivers/CMSIS/Include/core_cm7.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
+ 238:Drivers/CMSIS/Include/core_cm7.h **** 
+ 239:Drivers/CMSIS/Include/core_cm7.h **** /* following defines should be used for structure members */
+ 240:Drivers/CMSIS/Include/core_cm7.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+ 241:Drivers/CMSIS/Include/core_cm7.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+ 242:Drivers/CMSIS/Include/core_cm7.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+ 243:Drivers/CMSIS/Include/core_cm7.h **** 
+ 244:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group Cortex_M7 */
+ 245:Drivers/CMSIS/Include/core_cm7.h **** 
+ 246:Drivers/CMSIS/Include/core_cm7.h **** 
+ 247:Drivers/CMSIS/Include/core_cm7.h **** 
+ 248:Drivers/CMSIS/Include/core_cm7.h **** /*******************************************************************************
+ 249:Drivers/CMSIS/Include/core_cm7.h ****  *                 Register Abstraction
+ 250:Drivers/CMSIS/Include/core_cm7.h ****   Core Register contain:
+ 251:Drivers/CMSIS/Include/core_cm7.h ****   - Core Register
+ 252:Drivers/CMSIS/Include/core_cm7.h ****   - Core NVIC Register
+ 253:Drivers/CMSIS/Include/core_cm7.h ****   - Core SCB Register
+ 254:Drivers/CMSIS/Include/core_cm7.h ****   - Core SysTick Register
+ 255:Drivers/CMSIS/Include/core_cm7.h ****   - Core Debug Register
+ 256:Drivers/CMSIS/Include/core_cm7.h ****   - Core MPU Register
+ 257:Drivers/CMSIS/Include/core_cm7.h ****   - Core FPU Register
+ 258:Drivers/CMSIS/Include/core_cm7.h ****  ******************************************************************************/
+ 259:Drivers/CMSIS/Include/core_cm7.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 6
+
+
+ 260:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
+ 261:Drivers/CMSIS/Include/core_cm7.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
+ 262:Drivers/CMSIS/Include/core_cm7.h **** */
+ 263:Drivers/CMSIS/Include/core_cm7.h **** 
+ 264:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 265:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup    CMSIS_core_register
+ 266:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
+ 267:Drivers/CMSIS/Include/core_cm7.h ****   \brief      Core Register type definitions.
+ 268:Drivers/CMSIS/Include/core_cm7.h ****   @{
+ 269:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 270:Drivers/CMSIS/Include/core_cm7.h **** 
+ 271:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 272:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Union type to access the Application Program Status Register (APSR).
+ 273:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 274:Drivers/CMSIS/Include/core_cm7.h **** typedef union
+ 275:Drivers/CMSIS/Include/core_cm7.h **** {
+ 276:Drivers/CMSIS/Include/core_cm7.h ****   struct
+ 277:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 278:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+ 279:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+ 280:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+ 281:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+ 282:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+ 283:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+ 284:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+ 285:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+ 286:Drivers/CMSIS/Include/core_cm7.h ****   } b;                                   /*!< Structure used for bit  access */
+ 287:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 288:Drivers/CMSIS/Include/core_cm7.h **** } APSR_Type;
+ 289:Drivers/CMSIS/Include/core_cm7.h **** 
+ 290:Drivers/CMSIS/Include/core_cm7.h **** /* APSR Register Definitions */
+ 291:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
+ 292:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
+ 293:Drivers/CMSIS/Include/core_cm7.h **** 
+ 294:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
+ 295:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
+ 296:Drivers/CMSIS/Include/core_cm7.h **** 
+ 297:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
+ 298:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
+ 299:Drivers/CMSIS/Include/core_cm7.h **** 
+ 300:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
+ 301:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
+ 302:Drivers/CMSIS/Include/core_cm7.h **** 
+ 303:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Pos                         27U                                            /*!< APSR
+ 304:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR
+ 305:Drivers/CMSIS/Include/core_cm7.h **** 
+ 306:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Pos                        16U                                            /*!< APSR
+ 307:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR
+ 308:Drivers/CMSIS/Include/core_cm7.h **** 
+ 309:Drivers/CMSIS/Include/core_cm7.h **** 
+ 310:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 311:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ 312:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 313:Drivers/CMSIS/Include/core_cm7.h **** typedef union
+ 314:Drivers/CMSIS/Include/core_cm7.h **** {
+ 315:Drivers/CMSIS/Include/core_cm7.h ****   struct
+ 316:Drivers/CMSIS/Include/core_cm7.h ****   {
+ARM GAS  /tmp/ccdsDELB.s 			page 7
+
+
+ 317:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+ 318:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+ 319:Drivers/CMSIS/Include/core_cm7.h ****   } b;                                   /*!< Structure used for bit  access */
+ 320:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 321:Drivers/CMSIS/Include/core_cm7.h **** } IPSR_Type;
+ 322:Drivers/CMSIS/Include/core_cm7.h **** 
+ 323:Drivers/CMSIS/Include/core_cm7.h **** /* IPSR Register Definitions */
+ 324:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
+ 325:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
+ 326:Drivers/CMSIS/Include/core_cm7.h **** 
+ 327:Drivers/CMSIS/Include/core_cm7.h **** 
+ 328:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 329:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ 330:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 331:Drivers/CMSIS/Include/core_cm7.h **** typedef union
+ 332:Drivers/CMSIS/Include/core_cm7.h **** {
+ 333:Drivers/CMSIS/Include/core_cm7.h ****   struct
+ 334:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 335:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+ 336:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+ 337:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+ 338:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+ 339:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+ 340:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+ 341:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+ 342:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+ 343:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+ 344:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+ 345:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+ 346:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+ 347:Drivers/CMSIS/Include/core_cm7.h ****   } b;                                   /*!< Structure used for bit  access */
+ 348:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 349:Drivers/CMSIS/Include/core_cm7.h **** } xPSR_Type;
+ 350:Drivers/CMSIS/Include/core_cm7.h **** 
+ 351:Drivers/CMSIS/Include/core_cm7.h **** /* xPSR Register Definitions */
+ 352:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
+ 353:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
+ 354:Drivers/CMSIS/Include/core_cm7.h **** 
+ 355:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
+ 356:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
+ 357:Drivers/CMSIS/Include/core_cm7.h **** 
+ 358:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
+ 359:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
+ 360:Drivers/CMSIS/Include/core_cm7.h **** 
+ 361:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
+ 362:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
+ 363:Drivers/CMSIS/Include/core_cm7.h **** 
+ 364:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Pos                         27U                                            /*!< xPSR
+ 365:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR
+ 366:Drivers/CMSIS/Include/core_cm7.h **** 
+ 367:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR
+ 368:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR
+ 369:Drivers/CMSIS/Include/core_cm7.h **** 
+ 370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
+ 371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
+ 372:Drivers/CMSIS/Include/core_cm7.h **** 
+ 373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos                        16U                                            /*!< xPSR
+ARM GAS  /tmp/ccdsDELB.s 			page 8
+
+
+ 374:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR
+ 375:Drivers/CMSIS/Include/core_cm7.h **** 
+ 376:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR
+ 377:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR
+ 378:Drivers/CMSIS/Include/core_cm7.h **** 
+ 379:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
+ 380:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
+ 381:Drivers/CMSIS/Include/core_cm7.h **** 
+ 382:Drivers/CMSIS/Include/core_cm7.h **** 
+ 383:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 384:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Union type to access the Control Registers (CONTROL).
+ 385:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 386:Drivers/CMSIS/Include/core_cm7.h **** typedef union
+ 387:Drivers/CMSIS/Include/core_cm7.h **** {
+ 388:Drivers/CMSIS/Include/core_cm7.h ****   struct
+ 389:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 390:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+ 391:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+ 392:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+ 393:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+ 394:Drivers/CMSIS/Include/core_cm7.h ****   } b;                                   /*!< Structure used for bit  access */
+ 395:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 396:Drivers/CMSIS/Include/core_cm7.h **** } CONTROL_Type;
+ 397:Drivers/CMSIS/Include/core_cm7.h **** 
+ 398:Drivers/CMSIS/Include/core_cm7.h **** /* CONTROL Register Definitions */
+ 399:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Pos                    2U                                            /*!< CONT
+ 400:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONT
+ 401:Drivers/CMSIS/Include/core_cm7.h **** 
+ 402:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
+ 403:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
+ 404:Drivers/CMSIS/Include/core_cm7.h **** 
+ 405:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONT
+ 406:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONT
+ 407:Drivers/CMSIS/Include/core_cm7.h **** 
+ 408:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CORE */
+ 409:Drivers/CMSIS/Include/core_cm7.h **** 
+ 410:Drivers/CMSIS/Include/core_cm7.h **** 
+ 411:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 412:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup    CMSIS_core_register
+ 413:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+ 414:Drivers/CMSIS/Include/core_cm7.h ****   \brief      Type definitions for the NVIC Registers
+ 415:Drivers/CMSIS/Include/core_cm7.h ****   @{
+ 416:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 417:Drivers/CMSIS/Include/core_cm7.h **** 
+ 418:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 419:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ 420:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 421:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+ 422:Drivers/CMSIS/Include/core_cm7.h **** {
+ 423:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+ 424:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[24U];
+ 425:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
+ 426:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RSERVED1[24U];
+ 427:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
+ 428:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED2[24U];
+ 429:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
+ 430:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED3[24U];
+ARM GAS  /tmp/ccdsDELB.s 			page 9
+
+
+ 431:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+ 432:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED4[56U];
+ 433:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bi
+ 434:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED5[644U];
+ 435:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Regis
+ 436:Drivers/CMSIS/Include/core_cm7.h **** }  NVIC_Type;
+ 437:Drivers/CMSIS/Include/core_cm7.h **** 
+ 438:Drivers/CMSIS/Include/core_cm7.h **** /* Software Triggered Interrupt Register Definitions */
+ 439:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: I
+ 440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: I
+ 441:Drivers/CMSIS/Include/core_cm7.h **** 
+ 442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */
+ 443:Drivers/CMSIS/Include/core_cm7.h **** 
+ 444:Drivers/CMSIS/Include/core_cm7.h **** 
+ 445:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 446:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+ 447:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
+ 448:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the System Control Block Registers
+ 449:Drivers/CMSIS/Include/core_cm7.h ****   @{
+ 450:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 451:Drivers/CMSIS/Include/core_cm7.h **** 
+ 452:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 453:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the System Control Block (SCB).
+ 454:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 455:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+ 456:Drivers/CMSIS/Include/core_cm7.h **** {
+ 457:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+ 458:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
+ 459:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+ 460:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
+ 461:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+ 462:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
+ 463:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registe
+ 464:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
+ 465:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Regist
+ 466:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+ 467:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+ 468:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register
+ 469:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+ 470:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register 
+ 471:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+ 472:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+ 473:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+ 474:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+ 475:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Regis
+ 476:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[1U];
+ 477:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+ 478:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+ 479:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+ 480:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+ 481:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Regis
+ 482:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED3[93U];
+ 483:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Reg
+ 484:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED4[15U];
+ 485:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0
+ 486:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1
+ 487:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2
+ARM GAS  /tmp/ccdsDELB.s 			page 10
+
+
+ 488:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED5[1U];
+ 489:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+ 490:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED6[1U];
+ 491:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU
+ 492:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC
+ 493:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+ 494:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+ 495:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+ 496:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+ 497:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by 
+ 498:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by 
+ 499:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED7[6U];
+ 500:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memo
+ 501:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Cont
+ 502:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+ 503:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+ 504:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+ 505:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED8[1U];
+ 506:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Regis
+ 507:Drivers/CMSIS/Include/core_cm7.h **** } SCB_Type;
+ 508:Drivers/CMSIS/Include/core_cm7.h **** 
+ 509:Drivers/CMSIS/Include/core_cm7.h **** /* SCB CPUID Register Definitions */
+ 510:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
+ 511:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
+ 512:Drivers/CMSIS/Include/core_cm7.h **** 
+ 513:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
+ 514:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
+ 515:Drivers/CMSIS/Include/core_cm7.h **** 
+ 516:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
+ 517:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
+ 518:Drivers/CMSIS/Include/core_cm7.h **** 
+ 519:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
+ 520:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
+ 521:Drivers/CMSIS/Include/core_cm7.h **** 
+ 522:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
+ 523:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
+ 524:Drivers/CMSIS/Include/core_cm7.h **** 
+ 525:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Interrupt Control State Register Definitions */
+ 526:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
+ 527:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
+ 528:Drivers/CMSIS/Include/core_cm7.h **** 
+ 529:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
+ 530:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
+ 531:Drivers/CMSIS/Include/core_cm7.h **** 
+ 532:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
+ 533:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
+ 534:Drivers/CMSIS/Include/core_cm7.h **** 
+ 535:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
+ 536:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
+ 537:Drivers/CMSIS/Include/core_cm7.h **** 
+ 538:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
+ 539:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
+ 540:Drivers/CMSIS/Include/core_cm7.h **** 
+ 541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
+ 542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
+ 543:Drivers/CMSIS/Include/core_cm7.h **** 
+ 544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
+ARM GAS  /tmp/ccdsDELB.s 			page 11
+
+
+ 545:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
+ 546:Drivers/CMSIS/Include/core_cm7.h **** 
+ 547:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
+ 548:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
+ 549:Drivers/CMSIS/Include/core_cm7.h **** 
+ 550:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB 
+ 551:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB 
+ 552:Drivers/CMSIS/Include/core_cm7.h **** 
+ 553:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
+ 554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
+ 555:Drivers/CMSIS/Include/core_cm7.h **** 
+ 556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */
+ 557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB 
+ 558:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB 
+ 559:Drivers/CMSIS/Include/core_cm7.h **** 
+ 560:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
+ 561:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
+ 562:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
+ 563:Drivers/CMSIS/Include/core_cm7.h **** 
+ 564:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
+ 565:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
+ 566:Drivers/CMSIS/Include/core_cm7.h **** 
+ 567:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
+ 568:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
+ 569:Drivers/CMSIS/Include/core_cm7.h **** 
+ 570:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB 
+ 571:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB 
+ 572:Drivers/CMSIS/Include/core_cm7.h **** 
+ 573:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
+ 574:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
+ 575:Drivers/CMSIS/Include/core_cm7.h **** 
+ 576:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
+ 577:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
+ 578:Drivers/CMSIS/Include/core_cm7.h **** 
+ 579:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB 
+ 580:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB 
+ 581:Drivers/CMSIS/Include/core_cm7.h **** 
+ 582:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Control Register Definitions */
+ 583:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
+ 584:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
+ 585:Drivers/CMSIS/Include/core_cm7.h **** 
+ 586:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
+ 587:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
+ 588:Drivers/CMSIS/Include/core_cm7.h **** 
+ 589:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
+ 590:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
+ 591:Drivers/CMSIS/Include/core_cm7.h **** 
+ 592:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configuration Control Register Definitions */
+ 593:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Pos                      18U                                           /*!< SCB 
+ 594:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB 
+ 595:Drivers/CMSIS/Include/core_cm7.h **** 
+ 596:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Pos                      17U                                           /*!< SCB 
+ 597:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB 
+ 598:Drivers/CMSIS/Include/core_cm7.h **** 
+ 599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos                      16U                                           /*!< SCB 
+ 600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB 
+ 601:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 12
+
+
+ 602:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
+ 603:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
+ 604:Drivers/CMSIS/Include/core_cm7.h **** 
+ 605:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB 
+ 606:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB 
+ 607:Drivers/CMSIS/Include/core_cm7.h **** 
+ 608:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB 
+ 609:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB 
+ 610:Drivers/CMSIS/Include/core_cm7.h **** 
+ 611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
+ 612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
+ 613:Drivers/CMSIS/Include/core_cm7.h **** 
+ 614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB 
+ 615:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB 
+ 616:Drivers/CMSIS/Include/core_cm7.h **** 
+ 617:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB 
+ 618:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB 
+ 619:Drivers/CMSIS/Include/core_cm7.h **** 
+ 620:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Handler Control and State Register Definitions */
+ 621:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB 
+ 622:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB 
+ 623:Drivers/CMSIS/Include/core_cm7.h **** 
+ 624:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB 
+ 625:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB 
+ 626:Drivers/CMSIS/Include/core_cm7.h **** 
+ 627:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB 
+ 628:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB 
+ 629:Drivers/CMSIS/Include/core_cm7.h **** 
+ 630:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
+ 631:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
+ 632:Drivers/CMSIS/Include/core_cm7.h **** 
+ 633:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB 
+ 634:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB 
+ 635:Drivers/CMSIS/Include/core_cm7.h **** 
+ 636:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB 
+ 637:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB 
+ 638:Drivers/CMSIS/Include/core_cm7.h **** 
+ 639:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB 
+ 640:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB 
+ 641:Drivers/CMSIS/Include/core_cm7.h **** 
+ 642:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB 
+ 643:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB 
+ 644:Drivers/CMSIS/Include/core_cm7.h **** 
+ 645:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB 
+ 646:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB 
+ 647:Drivers/CMSIS/Include/core_cm7.h **** 
+ 648:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB 
+ 649:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB 
+ 650:Drivers/CMSIS/Include/core_cm7.h **** 
+ 651:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB 
+ 652:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB 
+ 653:Drivers/CMSIS/Include/core_cm7.h **** 
+ 654:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB 
+ 655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB 
+ 656:Drivers/CMSIS/Include/core_cm7.h **** 
+ 657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB 
+ 658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB 
+ARM GAS  /tmp/ccdsDELB.s 			page 13
+
+
+ 659:Drivers/CMSIS/Include/core_cm7.h **** 
+ 660:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB 
+ 661:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB 
+ 662:Drivers/CMSIS/Include/core_cm7.h **** 
+ 663:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configurable Fault Status Register Definitions */
+ 664:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB 
+ 665:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB 
+ 666:Drivers/CMSIS/Include/core_cm7.h **** 
+ 667:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB 
+ 668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB 
+ 669:Drivers/CMSIS/Include/core_cm7.h **** 
+ 670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB 
+ 671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB 
+ 672:Drivers/CMSIS/Include/core_cm7.h **** 
+ 673:Drivers/CMSIS/Include/core_cm7.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+ 674:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB 
+ 675:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB 
+ 676:Drivers/CMSIS/Include/core_cm7.h **** 
+ 677:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB 
+ 678:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB 
+ 679:Drivers/CMSIS/Include/core_cm7.h **** 
+ 680:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB 
+ 681:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB 
+ 682:Drivers/CMSIS/Include/core_cm7.h **** 
+ 683:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB 
+ 684:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB 
+ 685:Drivers/CMSIS/Include/core_cm7.h **** 
+ 686:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB 
+ 687:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB 
+ 688:Drivers/CMSIS/Include/core_cm7.h **** 
+ 689:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB 
+ 690:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB 
+ 691:Drivers/CMSIS/Include/core_cm7.h **** 
+ 692:Drivers/CMSIS/Include/core_cm7.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+ 693:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB 
+ 694:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB 
+ 695:Drivers/CMSIS/Include/core_cm7.h **** 
+ 696:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB 
+ 697:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB 
+ 698:Drivers/CMSIS/Include/core_cm7.h **** 
+ 699:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB 
+ 700:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB 
+ 701:Drivers/CMSIS/Include/core_cm7.h **** 
+ 702:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB 
+ 703:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB 
+ 704:Drivers/CMSIS/Include/core_cm7.h **** 
+ 705:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB 
+ 706:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB 
+ 707:Drivers/CMSIS/Include/core_cm7.h **** 
+ 708:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB 
+ 709:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB 
+ 710:Drivers/CMSIS/Include/core_cm7.h **** 
+ 711:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB 
+ 712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB 
+ 713:Drivers/CMSIS/Include/core_cm7.h **** 
+ 714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+ 715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB 
+ARM GAS  /tmp/ccdsDELB.s 			page 14
+
+
+ 716:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB 
+ 717:Drivers/CMSIS/Include/core_cm7.h **** 
+ 718:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB 
+ 719:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB 
+ 720:Drivers/CMSIS/Include/core_cm7.h **** 
+ 721:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB 
+ 722:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB 
+ 723:Drivers/CMSIS/Include/core_cm7.h **** 
+ 724:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB 
+ 725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB 
+ 726:Drivers/CMSIS/Include/core_cm7.h **** 
+ 727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB 
+ 728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB 
+ 729:Drivers/CMSIS/Include/core_cm7.h **** 
+ 730:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB 
+ 731:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB 
+ 732:Drivers/CMSIS/Include/core_cm7.h **** 
+ 733:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Hard Fault Status Register Definitions */
+ 734:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB 
+ 735:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB 
+ 736:Drivers/CMSIS/Include/core_cm7.h **** 
+ 737:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB 
+ 738:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB 
+ 739:Drivers/CMSIS/Include/core_cm7.h **** 
+ 740:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB 
+ 741:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB 
+ 742:Drivers/CMSIS/Include/core_cm7.h **** 
+ 743:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Debug Fault Status Register Definitions */
+ 744:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB 
+ 745:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB 
+ 746:Drivers/CMSIS/Include/core_cm7.h **** 
+ 747:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB 
+ 748:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB 
+ 749:Drivers/CMSIS/Include/core_cm7.h **** 
+ 750:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB 
+ 751:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB 
+ 752:Drivers/CMSIS/Include/core_cm7.h **** 
+ 753:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB 
+ 754:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB 
+ 755:Drivers/CMSIS/Include/core_cm7.h **** 
+ 756:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB 
+ 757:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB 
+ 758:Drivers/CMSIS/Include/core_cm7.h **** 
+ 759:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Level ID Register Definitions */
+ 760:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB 
+ 761:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB 
+ 762:Drivers/CMSIS/Include/core_cm7.h **** 
+ 763:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB 
+ 764:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB 
+ 765:Drivers/CMSIS/Include/core_cm7.h **** 
+ 766:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Type Register Definitions */
+ 767:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB 
+ 768:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB 
+ 769:Drivers/CMSIS/Include/core_cm7.h **** 
+ 770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB 
+ 771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB 
+ 772:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 15
+
+
+ 773:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB 
+ 774:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB 
+ 775:Drivers/CMSIS/Include/core_cm7.h **** 
+ 776:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB 
+ 777:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB 
+ 778:Drivers/CMSIS/Include/core_cm7.h **** 
+ 779:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB 
+ 780:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB 
+ 781:Drivers/CMSIS/Include/core_cm7.h **** 
+ 782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */
+ 783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB 
+ 784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB 
+ 785:Drivers/CMSIS/Include/core_cm7.h **** 
+ 786:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB 
+ 787:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB 
+ 788:Drivers/CMSIS/Include/core_cm7.h **** 
+ 789:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB 
+ 790:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB 
+ 791:Drivers/CMSIS/Include/core_cm7.h **** 
+ 792:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB 
+ 793:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB 
+ 794:Drivers/CMSIS/Include/core_cm7.h **** 
+ 795:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB 
+ 796:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB 
+ 797:Drivers/CMSIS/Include/core_cm7.h **** 
+ 798:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB 
+ 799:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB 
+ 800:Drivers/CMSIS/Include/core_cm7.h **** 
+ 801:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB 
+ 802:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB 
+ 803:Drivers/CMSIS/Include/core_cm7.h **** 
+ 804:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size Selection Register Definitions */
+ 805:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB 
+ 806:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB 
+ 807:Drivers/CMSIS/Include/core_cm7.h **** 
+ 808:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB 
+ 809:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB 
+ 810:Drivers/CMSIS/Include/core_cm7.h **** 
+ 811:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Software Triggered Interrupt Register Definitions */
+ 812:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB 
+ 813:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB 
+ 814:Drivers/CMSIS/Include/core_cm7.h **** 
+ 815:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Invalidate by Set-way Register Definitions */
+ 816:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB 
+ 817:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB 
+ 818:Drivers/CMSIS/Include/core_cm7.h **** 
+ 819:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB 
+ 820:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB 
+ 821:Drivers/CMSIS/Include/core_cm7.h **** 
+ 822:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean by Set-way Register Definitions */
+ 823:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB 
+ 824:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB 
+ 825:Drivers/CMSIS/Include/core_cm7.h **** 
+ 826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB 
+ 827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB 
+ 828:Drivers/CMSIS/Include/core_cm7.h **** 
+ 829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+ARM GAS  /tmp/ccdsDELB.s 			page 16
+
+
+ 830:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB 
+ 831:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB 
+ 832:Drivers/CMSIS/Include/core_cm7.h **** 
+ 833:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB 
+ 834:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB 
+ 835:Drivers/CMSIS/Include/core_cm7.h **** 
+ 836:Drivers/CMSIS/Include/core_cm7.h **** /* Instruction Tightly-Coupled Memory Control Register Definitions */
+ 837:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB 
+ 838:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB 
+ 839:Drivers/CMSIS/Include/core_cm7.h **** 
+ 840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB 
+ 841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB 
+ 842:Drivers/CMSIS/Include/core_cm7.h **** 
+ 843:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB 
+ 844:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB 
+ 845:Drivers/CMSIS/Include/core_cm7.h **** 
+ 846:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB 
+ 847:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB 
+ 848:Drivers/CMSIS/Include/core_cm7.h **** 
+ 849:Drivers/CMSIS/Include/core_cm7.h **** /* Data Tightly-Coupled Memory Control Register Definitions */
+ 850:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB 
+ 851:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB 
+ 852:Drivers/CMSIS/Include/core_cm7.h **** 
+ 853:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB 
+ 854:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB
+ 855:Drivers/CMSIS/Include/core_cm7.h **** 
+ 856:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB 
+ 857:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB 
+ 858:Drivers/CMSIS/Include/core_cm7.h **** 
+ 859:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB 
+ 860:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB 
+ 861:Drivers/CMSIS/Include/core_cm7.h **** 
+ 862:Drivers/CMSIS/Include/core_cm7.h **** /* AHBP Control Register Definitions */
+ 863:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB 
+ 864:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB 
+ 865:Drivers/CMSIS/Include/core_cm7.h **** 
+ 866:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB 
+ 867:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB 
+ 868:Drivers/CMSIS/Include/core_cm7.h **** 
+ 869:Drivers/CMSIS/Include/core_cm7.h **** /* L1 Cache Control Register Definitions */
+ 870:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB 
+ 871:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB 
+ 872:Drivers/CMSIS/Include/core_cm7.h **** 
+ 873:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB 
+ 874:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB 
+ 875:Drivers/CMSIS/Include/core_cm7.h **** 
+ 876:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB 
+ 877:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB 
+ 878:Drivers/CMSIS/Include/core_cm7.h **** 
+ 879:Drivers/CMSIS/Include/core_cm7.h **** /* AHBS Control Register Definitions */
+ 880:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB 
+ 881:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB 
+ 882:Drivers/CMSIS/Include/core_cm7.h **** 
+ 883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB 
+ 884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB 
+ 885:Drivers/CMSIS/Include/core_cm7.h **** 
+ 886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB 
+ARM GAS  /tmp/ccdsDELB.s 			page 17
+
+
+ 887:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB 
+ 888:Drivers/CMSIS/Include/core_cm7.h **** 
+ 889:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Bus Fault Status Register Definitions */
+ 890:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB 
+ 891:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB 
+ 892:Drivers/CMSIS/Include/core_cm7.h **** 
+ 893:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB 
+ 894:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB 
+ 895:Drivers/CMSIS/Include/core_cm7.h **** 
+ 896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB 
+ 897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB 
+ 898:Drivers/CMSIS/Include/core_cm7.h **** 
+ 899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB 
+ 900:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB 
+ 901:Drivers/CMSIS/Include/core_cm7.h **** 
+ 902:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB 
+ 903:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB 
+ 904:Drivers/CMSIS/Include/core_cm7.h **** 
+ 905:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB 
+ 906:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB 
+ 907:Drivers/CMSIS/Include/core_cm7.h **** 
+ 908:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCB */
+ 909:Drivers/CMSIS/Include/core_cm7.h **** 
+ 910:Drivers/CMSIS/Include/core_cm7.h **** 
+ 911:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 912:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+ 913:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ 914:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the System Control and ID Register not in the SCB
+ 915:Drivers/CMSIS/Include/core_cm7.h ****   @{
+ 916:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 917:Drivers/CMSIS/Include/core_cm7.h **** 
+ 918:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 919:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the System Control and ID Register not in the SCB.
+ 920:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 921:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+ 922:Drivers/CMSIS/Include/core_cm7.h **** {
+ 923:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[1U];
+ 924:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Regist
+ 925:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+ 926:Drivers/CMSIS/Include/core_cm7.h **** } SCnSCB_Type;
+ 927:Drivers/CMSIS/Include/core_cm7.h **** 
+ 928:Drivers/CMSIS/Include/core_cm7.h **** /* Interrupt Controller Type Register Definitions */
+ 929:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: I
+ 930:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: I
+ 931:Drivers/CMSIS/Include/core_cm7.h **** 
+ 932:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Control Register Definitions */
+ 933:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: 
+ 934:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: 
+ 935:Drivers/CMSIS/Include/core_cm7.h **** 
+ 936:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: 
+ 937:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: 
+ 938:Drivers/CMSIS/Include/core_cm7.h **** 
+ 939:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: 
+ 940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: 
+ 941:Drivers/CMSIS/Include/core_cm7.h **** 
+ 942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: 
+ 943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: 
+ARM GAS  /tmp/ccdsDELB.s 			page 18
+
+
+ 944:Drivers/CMSIS/Include/core_cm7.h **** 
+ 945:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: 
+ 946:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: 
+ 947:Drivers/CMSIS/Include/core_cm7.h **** 
+ 948:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCnotSCB */
+ 949:Drivers/CMSIS/Include/core_cm7.h **** 
+ 950:Drivers/CMSIS/Include/core_cm7.h **** 
+ 951:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 952:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+ 953:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+ 954:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the System Timer Registers.
+ 955:Drivers/CMSIS/Include/core_cm7.h ****   @{
+ 956:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 957:Drivers/CMSIS/Include/core_cm7.h **** 
+ 958:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 959:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the System Timer (SysTick).
+ 960:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 961:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+ 962:Drivers/CMSIS/Include/core_cm7.h **** {
+ 963:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
+ 964:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+ 965:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
+ 966:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+ 967:Drivers/CMSIS/Include/core_cm7.h **** } SysTick_Type;
+ 968:Drivers/CMSIS/Include/core_cm7.h **** 
+ 969:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Control / Status Register Definitions */
+ 970:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
+ 971:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
+ 972:Drivers/CMSIS/Include/core_cm7.h **** 
+ 973:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
+ 974:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
+ 975:Drivers/CMSIS/Include/core_cm7.h **** 
+ 976:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
+ 977:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
+ 978:Drivers/CMSIS/Include/core_cm7.h **** 
+ 979:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
+ 980:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
+ 981:Drivers/CMSIS/Include/core_cm7.h **** 
+ 982:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Reload Register Definitions */
+ 983:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
+ 984:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
+ 985:Drivers/CMSIS/Include/core_cm7.h **** 
+ 986:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Current Register Definitions */
+ 987:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
+ 988:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
+ 989:Drivers/CMSIS/Include/core_cm7.h **** 
+ 990:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Calibration Register Definitions */
+ 991:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
+ 992:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
+ 993:Drivers/CMSIS/Include/core_cm7.h **** 
+ 994:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
+ 995:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
+ 996:Drivers/CMSIS/Include/core_cm7.h **** 
+ 997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
+ 998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
+ 999:Drivers/CMSIS/Include/core_cm7.h **** 
+1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */
+ARM GAS  /tmp/ccdsDELB.s 			page 19
+
+
+1001:Drivers/CMSIS/Include/core_cm7.h **** 
+1002:Drivers/CMSIS/Include/core_cm7.h **** 
+1003:Drivers/CMSIS/Include/core_cm7.h **** /**
+1004:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1005:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+1006:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+1007:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1008:Drivers/CMSIS/Include/core_cm7.h ****  */
+1009:Drivers/CMSIS/Include/core_cm7.h **** 
+1010:Drivers/CMSIS/Include/core_cm7.h **** /**
+1011:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+1012:Drivers/CMSIS/Include/core_cm7.h ****  */
+1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1014:Drivers/CMSIS/Include/core_cm7.h **** {
+1015:Drivers/CMSIS/Include/core_cm7.h ****   __OM  union
+1016:Drivers/CMSIS/Include/core_cm7.h ****   {
+1017:Drivers/CMSIS/Include/core_cm7.h ****     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+1018:Drivers/CMSIS/Include/core_cm7.h ****     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+1019:Drivers/CMSIS/Include/core_cm7.h ****     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+1020:Drivers/CMSIS/Include/core_cm7.h ****   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+1021:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[864U];
+1022:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+1023:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED1[15U];
+1024:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+1025:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED2[15U];
+1026:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+1027:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED3[29U];
+1028:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register *
+1029:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+1030:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Reg
+1031:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED4[43U];
+1032:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+1033:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+1034:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED5[6U];
+1035:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Re
+1036:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Re
+1037:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Re
+1038:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Re
+1039:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Re
+1040:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Re
+1041:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Re
+1042:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Re
+1043:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Re
+1044:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Re
+1045:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Re
+1046:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Re
+1047:Drivers/CMSIS/Include/core_cm7.h **** } ITM_Type;
+1048:Drivers/CMSIS/Include/core_cm7.h **** 
+1049:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Privilege Register Definitions */
+1050:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM 
+1051:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM 
+1052:Drivers/CMSIS/Include/core_cm7.h **** 
+1053:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Control Register Definitions */
+1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM 
+1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM 
+1056:Drivers/CMSIS/Include/core_cm7.h **** 
+1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM 
+ARM GAS  /tmp/ccdsDELB.s 			page 20
+
+
+1058:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM 
+1059:Drivers/CMSIS/Include/core_cm7.h **** 
+1060:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM 
+1061:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM 
+1062:Drivers/CMSIS/Include/core_cm7.h **** 
+1063:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM 
+1064:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM 
+1065:Drivers/CMSIS/Include/core_cm7.h **** 
+1066:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM 
+1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM 
+1068:Drivers/CMSIS/Include/core_cm7.h **** 
+1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM 
+1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM 
+1071:Drivers/CMSIS/Include/core_cm7.h **** 
+1072:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM 
+1073:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM 
+1074:Drivers/CMSIS/Include/core_cm7.h **** 
+1075:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM 
+1076:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM 
+1077:Drivers/CMSIS/Include/core_cm7.h **** 
+1078:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM 
+1079:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM 
+1080:Drivers/CMSIS/Include/core_cm7.h **** 
+1081:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Write Register Definitions */
+1082:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM 
+1083:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM 
+1084:Drivers/CMSIS/Include/core_cm7.h **** 
+1085:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Read Register Definitions */
+1086:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM 
+1087:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM 
+1088:Drivers/CMSIS/Include/core_cm7.h **** 
+1089:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Mode Control Register Definitions */
+1090:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM 
+1091:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM 
+1092:Drivers/CMSIS/Include/core_cm7.h **** 
+1093:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Lock Status Register Definitions */
+1094:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM 
+1095:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM 
+1096:Drivers/CMSIS/Include/core_cm7.h **** 
+1097:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM 
+1098:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM 
+1099:Drivers/CMSIS/Include/core_cm7.h **** 
+1100:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM 
+1101:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM 
+1102:Drivers/CMSIS/Include/core_cm7.h **** 
+1103:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_ITM */
+1104:Drivers/CMSIS/Include/core_cm7.h **** 
+1105:Drivers/CMSIS/Include/core_cm7.h **** 
+1106:Drivers/CMSIS/Include/core_cm7.h **** /**
+1107:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1108:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+1109:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+1110:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1111:Drivers/CMSIS/Include/core_cm7.h ****  */
+1112:Drivers/CMSIS/Include/core_cm7.h **** 
+1113:Drivers/CMSIS/Include/core_cm7.h **** /**
+1114:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ARM GAS  /tmp/ccdsDELB.s 			page 21
+
+
+1115:Drivers/CMSIS/Include/core_cm7.h ****  */
+1116:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1117:Drivers/CMSIS/Include/core_cm7.h **** {
+1118:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+1119:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+1120:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+1121:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Registe
+1122:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+1123:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+1124:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Registe
+1125:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register 
+1126:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+1127:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+1128:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+1129:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[1U];
+1130:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+1131:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+1132:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+1133:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED1[1U];
+1134:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+1135:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+1136:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+1137:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED2[1U];
+1138:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+1139:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+1140:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+1141:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED3[981U];
+1142:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+1143:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+1144:Drivers/CMSIS/Include/core_cm7.h **** } DWT_Type;
+1145:Drivers/CMSIS/Include/core_cm7.h **** 
+1146:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Control Register Definitions */
+1147:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTR
+1148:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTR
+1149:Drivers/CMSIS/Include/core_cm7.h **** 
+1150:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTR
+1151:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTR
+1152:Drivers/CMSIS/Include/core_cm7.h **** 
+1153:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTR
+1154:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTR
+1155:Drivers/CMSIS/Include/core_cm7.h **** 
+1156:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTR
+1157:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTR
+1158:Drivers/CMSIS/Include/core_cm7.h **** 
+1159:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTR
+1160:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTR
+1161:Drivers/CMSIS/Include/core_cm7.h **** 
+1162:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTR
+1163:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTR
+1164:Drivers/CMSIS/Include/core_cm7.h **** 
+1165:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTR
+1166:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTR
+1167:Drivers/CMSIS/Include/core_cm7.h **** 
+1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTR
+1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTR
+1170:Drivers/CMSIS/Include/core_cm7.h **** 
+1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTR
+ARM GAS  /tmp/ccdsDELB.s 			page 22
+
+
+1172:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTR
+1173:Drivers/CMSIS/Include/core_cm7.h **** 
+1174:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTR
+1175:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTR
+1176:Drivers/CMSIS/Include/core_cm7.h **** 
+1177:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTR
+1178:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTR
+1179:Drivers/CMSIS/Include/core_cm7.h **** 
+1180:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTR
+1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTR
+1182:Drivers/CMSIS/Include/core_cm7.h **** 
+1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTR
+1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTR
+1185:Drivers/CMSIS/Include/core_cm7.h **** 
+1186:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTR
+1187:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTR
+1188:Drivers/CMSIS/Include/core_cm7.h **** 
+1189:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTR
+1190:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTR
+1191:Drivers/CMSIS/Include/core_cm7.h **** 
+1192:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTR
+1193:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTR
+1194:Drivers/CMSIS/Include/core_cm7.h **** 
+1195:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTR
+1196:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTR
+1197:Drivers/CMSIS/Include/core_cm7.h **** 
+1198:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTR
+1199:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTR
+1200:Drivers/CMSIS/Include/core_cm7.h **** 
+1201:Drivers/CMSIS/Include/core_cm7.h **** /* DWT CPI Count Register Definitions */
+1202:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPI
+1203:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPI
+1204:Drivers/CMSIS/Include/core_cm7.h **** 
+1205:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Exception Overhead Count Register Definitions */
+1206:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXC
+1207:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXC
+1208:Drivers/CMSIS/Include/core_cm7.h **** 
+1209:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Sleep Count Register Definitions */
+1210:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLE
+1211:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLE
+1212:Drivers/CMSIS/Include/core_cm7.h **** 
+1213:Drivers/CMSIS/Include/core_cm7.h **** /* DWT LSU Count Register Definitions */
+1214:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSU
+1215:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSU
+1216:Drivers/CMSIS/Include/core_cm7.h **** 
+1217:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Folded-instruction Count Register Definitions */
+1218:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOL
+1219:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOL
+1220:Drivers/CMSIS/Include/core_cm7.h **** 
+1221:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Mask Register Definitions */
+1222:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MAS
+1223:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MAS
+1224:Drivers/CMSIS/Include/core_cm7.h **** 
+1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */
+1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUN
+1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUN
+1228:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 23
+
+
+1229:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUN
+1230:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUN
+1231:Drivers/CMSIS/Include/core_cm7.h **** 
+1232:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUN
+1233:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUN
+1234:Drivers/CMSIS/Include/core_cm7.h **** 
+1235:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUN
+1236:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUN
+1237:Drivers/CMSIS/Include/core_cm7.h **** 
+1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUN
+1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUN
+1240:Drivers/CMSIS/Include/core_cm7.h **** 
+1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUN
+1242:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUN
+1243:Drivers/CMSIS/Include/core_cm7.h **** 
+1244:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUN
+1245:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUN
+1246:Drivers/CMSIS/Include/core_cm7.h **** 
+1247:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUN
+1248:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUN
+1249:Drivers/CMSIS/Include/core_cm7.h **** 
+1250:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUN
+1251:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUN
+1252:Drivers/CMSIS/Include/core_cm7.h **** 
+1253:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_DWT */
+1254:Drivers/CMSIS/Include/core_cm7.h **** 
+1255:Drivers/CMSIS/Include/core_cm7.h **** 
+1256:Drivers/CMSIS/Include/core_cm7.h **** /**
+1257:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1258:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+1259:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Trace Port Interface (TPI)
+1260:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1261:Drivers/CMSIS/Include/core_cm7.h ****  */
+1262:Drivers/CMSIS/Include/core_cm7.h **** 
+1263:Drivers/CMSIS/Include/core_cm7.h **** /**
+1264:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Trace Port Interface Register (TPI).
+1265:Drivers/CMSIS/Include/core_cm7.h ****  */
+1266:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1267:Drivers/CMSIS/Include/core_cm7.h **** {
+1268:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Reg
+1269:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Regis
+1270:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[2U];
+1271:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Reg
+1272:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED1[55U];
+1273:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register *
+1274:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED2[131U];
+1275:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Regis
+1276:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Regi
+1277:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counte
+1278:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED3[759U];
+1279:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+1280:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+1281:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+1282:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED4[1U];
+1283:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+1284:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+1285:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+ARM GAS  /tmp/ccdsDELB.s 			page 24
+
+
+1286:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED5[39U];
+1287:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+1288:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+1289:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED7[8U];
+1290:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+1291:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+1292:Drivers/CMSIS/Include/core_cm7.h **** } TPI_Type;
+1293:Drivers/CMSIS/Include/core_cm7.h **** 
+1294:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
+1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACP
+1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACP
+1297:Drivers/CMSIS/Include/core_cm7.h **** 
+1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */
+1299:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPP
+1300:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPP
+1301:Drivers/CMSIS/Include/core_cm7.h **** 
+1302:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Status Register Definitions */
+1303:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFS
+1304:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFS
+1305:Drivers/CMSIS/Include/core_cm7.h **** 
+1306:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFS
+1307:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFS
+1308:Drivers/CMSIS/Include/core_cm7.h **** 
+1309:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFS
+1310:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFS
+1311:Drivers/CMSIS/Include/core_cm7.h **** 
+1312:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFS
+1313:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFS
+1314:Drivers/CMSIS/Include/core_cm7.h **** 
+1315:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Control Register Definitions */
+1316:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFC
+1317:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFC
+1318:Drivers/CMSIS/Include/core_cm7.h **** 
+1319:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFC
+1320:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFC
+1321:Drivers/CMSIS/Include/core_cm7.h **** 
+1322:Drivers/CMSIS/Include/core_cm7.h **** /* TPI TRIGGER Register Definitions */
+1323:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRI
+1324:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRI
+1325:Drivers/CMSIS/Include/core_cm7.h **** 
+1326:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
+1327:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
+1328:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIF
+1329:Drivers/CMSIS/Include/core_cm7.h **** 
+1330:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
+1331:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIF
+1332:Drivers/CMSIS/Include/core_cm7.h **** 
+1333:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
+1334:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIF
+1335:Drivers/CMSIS/Include/core_cm7.h **** 
+1336:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
+1337:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIF
+1338:Drivers/CMSIS/Include/core_cm7.h **** 
+1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIF
+1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIF
+1341:Drivers/CMSIS/Include/core_cm7.h **** 
+1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIF
+ARM GAS  /tmp/ccdsDELB.s 			page 25
+
+
+1343:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIF
+1344:Drivers/CMSIS/Include/core_cm7.h **** 
+1345:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIF
+1346:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIF
+1347:Drivers/CMSIS/Include/core_cm7.h **** 
+1348:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR2 Register Definitions */
+1349:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITA
+1350:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITA
+1351:Drivers/CMSIS/Include/core_cm7.h **** 
+1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITA
+1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITA
+1354:Drivers/CMSIS/Include/core_cm7.h **** 
+1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
+1356:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
+1357:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIF
+1358:Drivers/CMSIS/Include/core_cm7.h **** 
+1359:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
+1360:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIF
+1361:Drivers/CMSIS/Include/core_cm7.h **** 
+1362:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
+1363:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIF
+1364:Drivers/CMSIS/Include/core_cm7.h **** 
+1365:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
+1366:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIF
+1367:Drivers/CMSIS/Include/core_cm7.h **** 
+1368:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIF
+1369:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIF
+1370:Drivers/CMSIS/Include/core_cm7.h **** 
+1371:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIF
+1372:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIF
+1373:Drivers/CMSIS/Include/core_cm7.h **** 
+1374:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIF
+1375:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIF
+1376:Drivers/CMSIS/Include/core_cm7.h **** 
+1377:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR0 Register Definitions */
+1378:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITA
+1379:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITA
+1380:Drivers/CMSIS/Include/core_cm7.h **** 
+1381:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITA
+1382:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITA
+1383:Drivers/CMSIS/Include/core_cm7.h **** 
+1384:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration Mode Control Register Definitions */
+1385:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITC
+1386:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITC
+1387:Drivers/CMSIS/Include/core_cm7.h **** 
+1388:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVID Register Definitions */
+1389:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEV
+1390:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEV
+1391:Drivers/CMSIS/Include/core_cm7.h **** 
+1392:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEV
+1393:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEV
+1394:Drivers/CMSIS/Include/core_cm7.h **** 
+1395:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEV
+1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEV
+1397:Drivers/CMSIS/Include/core_cm7.h **** 
+1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEV
+1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEV
+ARM GAS  /tmp/ccdsDELB.s 			page 26
+
+
+1400:Drivers/CMSIS/Include/core_cm7.h **** 
+1401:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEV
+1402:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEV
+1403:Drivers/CMSIS/Include/core_cm7.h **** 
+1404:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEV
+1405:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEV
+1406:Drivers/CMSIS/Include/core_cm7.h **** 
+1407:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVTYPE Register Definitions */
+1408:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEV
+1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEV
+1410:Drivers/CMSIS/Include/core_cm7.h **** 
+1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEV
+1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEV
+1413:Drivers/CMSIS/Include/core_cm7.h **** 
+1414:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_TPI */
+1415:Drivers/CMSIS/Include/core_cm7.h **** 
+1416:Drivers/CMSIS/Include/core_cm7.h **** 
+1417:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+1418:Drivers/CMSIS/Include/core_cm7.h **** /**
+1419:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1420:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+1421:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Memory Protection Unit (MPU)
+1422:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1423:Drivers/CMSIS/Include/core_cm7.h ****  */
+1424:Drivers/CMSIS/Include/core_cm7.h **** 
+1425:Drivers/CMSIS/Include/core_cm7.h **** /**
+1426:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Memory Protection Unit (MPU).
+1427:Drivers/CMSIS/Include/core_cm7.h ****  */
+1428:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1429:Drivers/CMSIS/Include/core_cm7.h **** {
+1430:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+1431:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+1432:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+1433:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register
+1434:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Re
+1435:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address 
+1436:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and
+1437:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address 
+1438:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and
+1439:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address 
+1440:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and
+1441:Drivers/CMSIS/Include/core_cm7.h **** } MPU_Type;
+1442:Drivers/CMSIS/Include/core_cm7.h **** 
+1443:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_RALIASES                  4U
+1444:Drivers/CMSIS/Include/core_cm7.h **** 
+1445:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Type Register Definitions */
+1446:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU 
+1447:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU 
+1448:Drivers/CMSIS/Include/core_cm7.h **** 
+1449:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU 
+1450:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU 
+1451:Drivers/CMSIS/Include/core_cm7.h **** 
+1452:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU 
+1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU 
+1454:Drivers/CMSIS/Include/core_cm7.h **** 
+1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */
+1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU 
+ARM GAS  /tmp/ccdsDELB.s 			page 27
+
+
+1457:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU 
+1458:Drivers/CMSIS/Include/core_cm7.h **** 
+1459:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU 
+1460:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU 
+1461:Drivers/CMSIS/Include/core_cm7.h **** 
+1462:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU 
+1463:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU 
+1464:Drivers/CMSIS/Include/core_cm7.h **** 
+1465:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Number Register Definitions */
+1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU 
+1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU 
+1468:Drivers/CMSIS/Include/core_cm7.h **** 
+1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */
+1470:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU 
+1471:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU 
+1472:Drivers/CMSIS/Include/core_cm7.h **** 
+1473:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU 
+1474:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU 
+1475:Drivers/CMSIS/Include/core_cm7.h **** 
+1476:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU 
+1477:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU 
+1478:Drivers/CMSIS/Include/core_cm7.h **** 
+1479:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Attribute and Size Register Definitions */
+1480:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU 
+1481:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU 
+1482:Drivers/CMSIS/Include/core_cm7.h **** 
+1483:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU 
+1484:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU 
+1485:Drivers/CMSIS/Include/core_cm7.h **** 
+1486:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU 
+1487:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU 
+1488:Drivers/CMSIS/Include/core_cm7.h **** 
+1489:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU 
+1490:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU 
+1491:Drivers/CMSIS/Include/core_cm7.h **** 
+1492:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Pos                     18U                                            /*!< MPU 
+1493:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU 
+1494:Drivers/CMSIS/Include/core_cm7.h **** 
+1495:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Pos                     17U                                            /*!< MPU 
+1496:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU 
+1497:Drivers/CMSIS/Include/core_cm7.h **** 
+1498:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Pos                     16U                                            /*!< MPU 
+1499:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU 
+1500:Drivers/CMSIS/Include/core_cm7.h **** 
+1501:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU 
+1502:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU 
+1503:Drivers/CMSIS/Include/core_cm7.h **** 
+1504:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU 
+1505:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU 
+1506:Drivers/CMSIS/Include/core_cm7.h **** 
+1507:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU 
+1508:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU 
+1509:Drivers/CMSIS/Include/core_cm7.h **** 
+1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */
+1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+1512:Drivers/CMSIS/Include/core_cm7.h **** 
+1513:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 28
+
+
+1514:Drivers/CMSIS/Include/core_cm7.h **** /**
+1515:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1516:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+1517:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Floating Point Unit (FPU)
+1518:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1519:Drivers/CMSIS/Include/core_cm7.h ****  */
+1520:Drivers/CMSIS/Include/core_cm7.h **** 
+1521:Drivers/CMSIS/Include/core_cm7.h **** /**
+1522:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Floating Point Unit (FPU).
+1523:Drivers/CMSIS/Include/core_cm7.h ****  */
+1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1525:Drivers/CMSIS/Include/core_cm7.h **** {
+1526:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[1U];
+1527:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control R
+1528:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address R
+1529:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Co
+1530:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 
+1531:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 
+1532:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 
+1533:Drivers/CMSIS/Include/core_cm7.h **** } FPU_Type;
+1534:Drivers/CMSIS/Include/core_cm7.h **** 
+1535:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Control Register Definitions */
+1536:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCC
+1537:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCC
+1538:Drivers/CMSIS/Include/core_cm7.h **** 
+1539:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCC
+1540:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCC
+1541:Drivers/CMSIS/Include/core_cm7.h **** 
+1542:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCC
+1543:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCC
+1544:Drivers/CMSIS/Include/core_cm7.h **** 
+1545:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCC
+1546:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCC
+1547:Drivers/CMSIS/Include/core_cm7.h **** 
+1548:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCC
+1549:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCC
+1550:Drivers/CMSIS/Include/core_cm7.h **** 
+1551:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCC
+1552:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCC
+1553:Drivers/CMSIS/Include/core_cm7.h **** 
+1554:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCC
+1555:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCC
+1556:Drivers/CMSIS/Include/core_cm7.h **** 
+1557:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCC
+1558:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCC
+1559:Drivers/CMSIS/Include/core_cm7.h **** 
+1560:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCC
+1561:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCC
+1562:Drivers/CMSIS/Include/core_cm7.h **** 
+1563:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Address Register Definitions */
+1564:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCA
+1565:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCA
+1566:Drivers/CMSIS/Include/core_cm7.h **** 
+1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */
+1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDS
+1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDS
+1570:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 29
+
+
+1571:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDS
+1572:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDS
+1573:Drivers/CMSIS/Include/core_cm7.h **** 
+1574:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDS
+1575:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDS
+1576:Drivers/CMSIS/Include/core_cm7.h **** 
+1577:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDS
+1578:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDS
+1579:Drivers/CMSIS/Include/core_cm7.h **** 
+1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */
+1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR
+1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR
+1583:Drivers/CMSIS/Include/core_cm7.h **** 
+1584:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR
+1585:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR
+1586:Drivers/CMSIS/Include/core_cm7.h **** 
+1587:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR
+1588:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR
+1589:Drivers/CMSIS/Include/core_cm7.h **** 
+1590:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR
+1591:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR
+1592:Drivers/CMSIS/Include/core_cm7.h **** 
+1593:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR
+1594:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR
+1595:Drivers/CMSIS/Include/core_cm7.h **** 
+1596:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR
+1597:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR
+1598:Drivers/CMSIS/Include/core_cm7.h **** 
+1599:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR
+1600:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR
+1601:Drivers/CMSIS/Include/core_cm7.h **** 
+1602:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR
+1603:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR
+1604:Drivers/CMSIS/Include/core_cm7.h **** 
+1605:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 1 Definitions */
+1606:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR
+1607:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR
+1608:Drivers/CMSIS/Include/core_cm7.h **** 
+1609:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR
+1610:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR
+1611:Drivers/CMSIS/Include/core_cm7.h **** 
+1612:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR
+1613:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR
+1614:Drivers/CMSIS/Include/core_cm7.h **** 
+1615:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR
+1616:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR
+1617:Drivers/CMSIS/Include/core_cm7.h **** 
+1618:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 2 Definitions */
+1619:Drivers/CMSIS/Include/core_cm7.h **** 
+1620:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_FPU */
+1621:Drivers/CMSIS/Include/core_cm7.h **** 
+1622:Drivers/CMSIS/Include/core_cm7.h **** 
+1623:Drivers/CMSIS/Include/core_cm7.h **** /**
+1624:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1625:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+1626:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Core Debug Registers
+1627:Drivers/CMSIS/Include/core_cm7.h ****   @{
+ARM GAS  /tmp/ccdsDELB.s 			page 30
+
+
+1628:Drivers/CMSIS/Include/core_cm7.h ****  */
+1629:Drivers/CMSIS/Include/core_cm7.h **** 
+1630:Drivers/CMSIS/Include/core_cm7.h **** /**
+1631:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Core Debug Register (CoreDebug).
+1632:Drivers/CMSIS/Include/core_cm7.h ****  */
+1633:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1634:Drivers/CMSIS/Include/core_cm7.h **** {
+1635:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status
+1636:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Reg
+1637:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Registe
+1638:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Cont
+1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type;
+1640:Drivers/CMSIS/Include/core_cm7.h **** 
+1641:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Halting Control and Status Register Definitions */
+1642:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< Core
+1643:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< Core
+1644:Drivers/CMSIS/Include/core_cm7.h **** 
+1645:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< Core
+1646:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< Core
+1647:Drivers/CMSIS/Include/core_cm7.h **** 
+1648:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< Core
+1649:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< Core
+1650:Drivers/CMSIS/Include/core_cm7.h **** 
+1651:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< Core
+1652:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< Core
+1653:Drivers/CMSIS/Include/core_cm7.h **** 
+1654:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< Core
+1655:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< Core
+1656:Drivers/CMSIS/Include/core_cm7.h **** 
+1657:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< Core
+1658:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< Core
+1659:Drivers/CMSIS/Include/core_cm7.h **** 
+1660:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< Core
+1661:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< Core
+1662:Drivers/CMSIS/Include/core_cm7.h **** 
+1663:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< Core
+1664:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< Core
+1665:Drivers/CMSIS/Include/core_cm7.h **** 
+1666:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< Core
+1667:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< Core
+1668:Drivers/CMSIS/Include/core_cm7.h **** 
+1669:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< Core
+1670:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< Core
+1671:Drivers/CMSIS/Include/core_cm7.h **** 
+1672:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< Core
+1673:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< Core
+1674:Drivers/CMSIS/Include/core_cm7.h **** 
+1675:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< Core
+1676:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< Core
+1677:Drivers/CMSIS/Include/core_cm7.h **** 
+1678:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Core Register Selector Register Definitions */
+1679:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< Core
+1680:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< Core
+1681:Drivers/CMSIS/Include/core_cm7.h **** 
+1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< Core
+1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< Core
+1684:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 31
+
+
+1685:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Exception and Monitor Control Register Definitions */
+1686:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< Core
+1687:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< Core
+1688:Drivers/CMSIS/Include/core_cm7.h **** 
+1689:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< Core
+1690:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< Core
+1691:Drivers/CMSIS/Include/core_cm7.h **** 
+1692:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< Core
+1693:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< Core
+1694:Drivers/CMSIS/Include/core_cm7.h **** 
+1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< Core
+1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< Core
+1697:Drivers/CMSIS/Include/core_cm7.h **** 
+1698:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< Core
+1699:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< Core
+1700:Drivers/CMSIS/Include/core_cm7.h **** 
+1701:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< Core
+1702:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< Core
+1703:Drivers/CMSIS/Include/core_cm7.h **** 
+1704:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< Core
+1705:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< Core
+1706:Drivers/CMSIS/Include/core_cm7.h **** 
+1707:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< Core
+1708:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< Core
+1709:Drivers/CMSIS/Include/core_cm7.h **** 
+1710:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< Core
+1711:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< Core
+1712:Drivers/CMSIS/Include/core_cm7.h **** 
+1713:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< Core
+1714:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< Core
+1715:Drivers/CMSIS/Include/core_cm7.h **** 
+1716:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< Core
+1717:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< Core
+1718:Drivers/CMSIS/Include/core_cm7.h **** 
+1719:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< Core
+1720:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< Core
+1721:Drivers/CMSIS/Include/core_cm7.h **** 
+1722:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< Core
+1723:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< Core
+1724:Drivers/CMSIS/Include/core_cm7.h **** 
+1725:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CoreDebug */
+1726:Drivers/CMSIS/Include/core_cm7.h **** 
+1727:Drivers/CMSIS/Include/core_cm7.h **** 
+1728:Drivers/CMSIS/Include/core_cm7.h **** /**
+1729:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup    CMSIS_core_register
+1730:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
+1731:Drivers/CMSIS/Include/core_cm7.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+1732:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1733:Drivers/CMSIS/Include/core_cm7.h ****  */
+1734:Drivers/CMSIS/Include/core_cm7.h **** 
+1735:Drivers/CMSIS/Include/core_cm7.h **** /**
+1736:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
+1737:Drivers/CMSIS/Include/core_cm7.h ****   \param[in] field  Name of the register bit field.
+1738:Drivers/CMSIS/Include/core_cm7.h ****   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+1739:Drivers/CMSIS/Include/core_cm7.h ****   \return           Masked and shifted value.
+1740:Drivers/CMSIS/Include/core_cm7.h **** */
+1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+ARM GAS  /tmp/ccdsDELB.s 			page 32
+
+
+1742:Drivers/CMSIS/Include/core_cm7.h **** 
+1743:Drivers/CMSIS/Include/core_cm7.h **** /**
+1744:Drivers/CMSIS/Include/core_cm7.h ****   \brief     Mask and shift a register value to extract a bit filed value.
+1745:Drivers/CMSIS/Include/core_cm7.h ****   \param[in] field  Name of the register bit field.
+1746:Drivers/CMSIS/Include/core_cm7.h ****   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+1747:Drivers/CMSIS/Include/core_cm7.h ****   \return           Masked and shifted bit field value.
+1748:Drivers/CMSIS/Include/core_cm7.h **** */
+1749:Drivers/CMSIS/Include/core_cm7.h **** #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+1750:Drivers/CMSIS/Include/core_cm7.h **** 
+1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */
+1752:Drivers/CMSIS/Include/core_cm7.h **** 
+1753:Drivers/CMSIS/Include/core_cm7.h **** 
+1754:Drivers/CMSIS/Include/core_cm7.h **** /**
+1755:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup    CMSIS_core_register
+1756:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup   CMSIS_core_base     Core Definitions
+1757:Drivers/CMSIS/Include/core_cm7.h ****   \brief      Definitions for base addresses, unions, and structures.
+1758:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1759:Drivers/CMSIS/Include/core_cm7.h ****  */
+1760:Drivers/CMSIS/Include/core_cm7.h **** 
+1761:Drivers/CMSIS/Include/core_cm7.h **** /* Memory mapping of Core Hardware */
+1762:Drivers/CMSIS/Include/core_cm7.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
+1763:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+1764:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+1765:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+1766:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address 
+1767:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+1768:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+1769:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
+1770:Drivers/CMSIS/Include/core_cm7.h **** 
+1771:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register 
+1772:Drivers/CMSIS/Include/core_cm7.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
+1773:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
+1774:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
+1775:Drivers/CMSIS/Include/core_cm7.h **** #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct
+1776:Drivers/CMSIS/Include/core_cm7.h **** #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct
+1777:Drivers/CMSIS/Include/core_cm7.h **** #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct
+1778:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration
+1779:Drivers/CMSIS/Include/core_cm7.h **** 
+1780:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+1781:Drivers/CMSIS/Include/core_cm7.h ****   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit *
+1782:Drivers/CMSIS/Include/core_cm7.h ****   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit *
+1783:Drivers/CMSIS/Include/core_cm7.h **** #endif
+1784:Drivers/CMSIS/Include/core_cm7.h **** 
+1785:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+1786:Drivers/CMSIS/Include/core_cm7.h **** #define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+1787:Drivers/CMSIS/Include/core_cm7.h **** 
+1788:Drivers/CMSIS/Include/core_cm7.h **** /*@} */
+1789:Drivers/CMSIS/Include/core_cm7.h **** 
+1790:Drivers/CMSIS/Include/core_cm7.h **** 
+1791:Drivers/CMSIS/Include/core_cm7.h **** 
+1792:Drivers/CMSIS/Include/core_cm7.h **** /*******************************************************************************
+1793:Drivers/CMSIS/Include/core_cm7.h ****  *                Hardware Abstraction Layer
+1794:Drivers/CMSIS/Include/core_cm7.h ****   Core Function Interface contains:
+1795:Drivers/CMSIS/Include/core_cm7.h ****   - Core NVIC Functions
+1796:Drivers/CMSIS/Include/core_cm7.h ****   - Core SysTick Functions
+1797:Drivers/CMSIS/Include/core_cm7.h ****   - Core Debug Functions
+1798:Drivers/CMSIS/Include/core_cm7.h ****   - Core Register Access Functions
+ARM GAS  /tmp/ccdsDELB.s 			page 33
+
+
+1799:Drivers/CMSIS/Include/core_cm7.h ****  ******************************************************************************/
+1800:Drivers/CMSIS/Include/core_cm7.h **** /**
+1801:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+1802:Drivers/CMSIS/Include/core_cm7.h **** */
+1803:Drivers/CMSIS/Include/core_cm7.h **** 
+1804:Drivers/CMSIS/Include/core_cm7.h **** 
+1805:Drivers/CMSIS/Include/core_cm7.h **** 
+1806:Drivers/CMSIS/Include/core_cm7.h **** /* ##########################   NVIC functions  #################################### */
+1807:Drivers/CMSIS/Include/core_cm7.h **** /**
+1808:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_Core_FunctionInterface
+1809:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+1810:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
+1811:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1812:Drivers/CMSIS/Include/core_cm7.h ****  */
+1813:Drivers/CMSIS/Include/core_cm7.h **** 
+1814:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_NVIC_VIRTUAL
+1815:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+1816:Drivers/CMSIS/Include/core_cm7.h ****     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+1817:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+1818:Drivers/CMSIS/Include/core_cm7.h ****   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+1819:Drivers/CMSIS/Include/core_cm7.h **** #else
+1820:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+1821:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+1822:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+1823:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+1824:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+1825:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+1826:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+1827:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+1828:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetActive              __NVIC_GetActive
+1829:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_SetPriority            __NVIC_SetPriority
+1830:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetPriority            __NVIC_GetPriority
+1831:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_SystemReset            __NVIC_SystemReset
+1832:Drivers/CMSIS/Include/core_cm7.h **** #endif /* CMSIS_NVIC_VIRTUAL */
+1833:Drivers/CMSIS/Include/core_cm7.h **** 
+1834:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_VECTAB_VIRTUAL
+1835:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+1836:Drivers/CMSIS/Include/core_cm7.h ****     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+1837:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+1838:Drivers/CMSIS/Include/core_cm7.h ****   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+1839:Drivers/CMSIS/Include/core_cm7.h **** #else
+1840:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_SetVector              __NVIC_SetVector
+1841:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetVector              __NVIC_GetVector
+1842:Drivers/CMSIS/Include/core_cm7.h **** #endif  /* (CMSIS_VECTAB_VIRTUAL) */
+1843:Drivers/CMSIS/Include/core_cm7.h **** 
+1844:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_USER_IRQ_OFFSET          16
+1845:Drivers/CMSIS/Include/core_cm7.h **** 
+1846:Drivers/CMSIS/Include/core_cm7.h **** 
+1847:Drivers/CMSIS/Include/core_cm7.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
+1848:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after ret
+1849:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after retu
+1850:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after retu
+1851:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after ret
+1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after retu
+1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after retu
+1854:Drivers/CMSIS/Include/core_cm7.h **** 
+1855:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 34
+
+
+1856:Drivers/CMSIS/Include/core_cm7.h **** /**
+1857:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Set Priority Grouping
+1858:Drivers/CMSIS/Include/core_cm7.h ****   \details Sets the priority grouping field using the required unlock sequence.
+1859:Drivers/CMSIS/Include/core_cm7.h ****            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+1860:Drivers/CMSIS/Include/core_cm7.h ****            Only values from 0..7 are used.
+1861:Drivers/CMSIS/Include/core_cm7.h ****            In case of a conflict between priority grouping and available
+1862:Drivers/CMSIS/Include/core_cm7.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+1863:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      PriorityGroup  Priority grouping field.
+1864:Drivers/CMSIS/Include/core_cm7.h ****  */
+1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+1866:Drivers/CMSIS/Include/core_cm7.h **** {
+1867:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t reg_value;
+1868:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
+1869:Drivers/CMSIS/Include/core_cm7.h **** 
+1870:Drivers/CMSIS/Include/core_cm7.h ****   reg_value  =  SCB->AIRCR;                                                   /* read old register 
+1871:Drivers/CMSIS/Include/core_cm7.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
+1872:Drivers/CMSIS/Include/core_cm7.h ****   reg_value  =  (reg_value                                   |
+1873:Drivers/CMSIS/Include/core_cm7.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+1874:Drivers/CMSIS/Include/core_cm7.h ****                 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key a
+1875:Drivers/CMSIS/Include/core_cm7.h ****   SCB->AIRCR =  reg_value;
+1876:Drivers/CMSIS/Include/core_cm7.h **** }
+1877:Drivers/CMSIS/Include/core_cm7.h **** 
+1878:Drivers/CMSIS/Include/core_cm7.h **** 
+1879:Drivers/CMSIS/Include/core_cm7.h **** /**
+1880:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Get Priority Grouping
+1881:Drivers/CMSIS/Include/core_cm7.h ****   \details Reads the priority grouping field from the NVIC Interrupt Controller.
+1882:Drivers/CMSIS/Include/core_cm7.h ****   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+1883:Drivers/CMSIS/Include/core_cm7.h ****  */
+1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+1885:Drivers/CMSIS/Include/core_cm7.h **** {
+1886:Drivers/CMSIS/Include/core_cm7.h ****   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+1887:Drivers/CMSIS/Include/core_cm7.h **** }
+1888:Drivers/CMSIS/Include/core_cm7.h **** 
+1889:Drivers/CMSIS/Include/core_cm7.h **** 
+1890:Drivers/CMSIS/Include/core_cm7.h **** /**
+1891:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Enable Interrupt
+1892:Drivers/CMSIS/Include/core_cm7.h ****   \details Enables a device specific interrupt in the NVIC interrupt controller.
+1893:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1894:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1895:Drivers/CMSIS/Include/core_cm7.h ****  */
+1896:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+1897:Drivers/CMSIS/Include/core_cm7.h **** {
+1898:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1899:Drivers/CMSIS/Include/core_cm7.h ****   {
+1900:Drivers/CMSIS/Include/core_cm7.h ****     NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+1901:Drivers/CMSIS/Include/core_cm7.h ****   }
+1902:Drivers/CMSIS/Include/core_cm7.h **** }
+1903:Drivers/CMSIS/Include/core_cm7.h **** 
+1904:Drivers/CMSIS/Include/core_cm7.h **** 
+1905:Drivers/CMSIS/Include/core_cm7.h **** /**
+1906:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Get Interrupt Enable status
+1907:Drivers/CMSIS/Include/core_cm7.h ****   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+1908:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1909:Drivers/CMSIS/Include/core_cm7.h ****   \return             0  Interrupt is not enabled.
+1910:Drivers/CMSIS/Include/core_cm7.h ****   \return             1  Interrupt is enabled.
+1911:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1912:Drivers/CMSIS/Include/core_cm7.h ****  */
+ARM GAS  /tmp/ccdsDELB.s 			page 35
+
+
+1913:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+1914:Drivers/CMSIS/Include/core_cm7.h **** {
+1915:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1916:Drivers/CMSIS/Include/core_cm7.h ****   {
+1917:Drivers/CMSIS/Include/core_cm7.h ****     return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
+1918:Drivers/CMSIS/Include/core_cm7.h ****   }
+1919:Drivers/CMSIS/Include/core_cm7.h ****   else
+1920:Drivers/CMSIS/Include/core_cm7.h ****   {
+1921:Drivers/CMSIS/Include/core_cm7.h ****     return(0U);
+1922:Drivers/CMSIS/Include/core_cm7.h ****   }
+1923:Drivers/CMSIS/Include/core_cm7.h **** }
+1924:Drivers/CMSIS/Include/core_cm7.h **** 
+1925:Drivers/CMSIS/Include/core_cm7.h **** 
+1926:Drivers/CMSIS/Include/core_cm7.h **** /**
+1927:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Disable Interrupt
+1928:Drivers/CMSIS/Include/core_cm7.h ****   \details Disables a device specific interrupt in the NVIC interrupt controller.
+1929:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1930:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1931:Drivers/CMSIS/Include/core_cm7.h ****  */
+1932:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+1933:Drivers/CMSIS/Include/core_cm7.h **** {
+1934:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1935:Drivers/CMSIS/Include/core_cm7.h ****   {
+1936:Drivers/CMSIS/Include/core_cm7.h ****     NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+1937:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+1938:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+1939:Drivers/CMSIS/Include/core_cm7.h ****   }
+1940:Drivers/CMSIS/Include/core_cm7.h **** }
+1941:Drivers/CMSIS/Include/core_cm7.h **** 
+1942:Drivers/CMSIS/Include/core_cm7.h **** 
+1943:Drivers/CMSIS/Include/core_cm7.h **** /**
+1944:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Get Pending Interrupt
+1945:Drivers/CMSIS/Include/core_cm7.h ****   \details Reads the NVIC pending register and returns the pending bit for the specified device spe
+1946:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1947:Drivers/CMSIS/Include/core_cm7.h ****   \return             0  Interrupt status is not pending.
+1948:Drivers/CMSIS/Include/core_cm7.h ****   \return             1  Interrupt status is pending.
+1949:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1950:Drivers/CMSIS/Include/core_cm7.h ****  */
+1951:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+1952:Drivers/CMSIS/Include/core_cm7.h **** {
+1953:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1954:Drivers/CMSIS/Include/core_cm7.h ****   {
+1955:Drivers/CMSIS/Include/core_cm7.h ****     return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
+1956:Drivers/CMSIS/Include/core_cm7.h ****   }
+1957:Drivers/CMSIS/Include/core_cm7.h ****   else
+1958:Drivers/CMSIS/Include/core_cm7.h ****   {
+1959:Drivers/CMSIS/Include/core_cm7.h ****     return(0U);
+1960:Drivers/CMSIS/Include/core_cm7.h ****   }
+1961:Drivers/CMSIS/Include/core_cm7.h **** }
+1962:Drivers/CMSIS/Include/core_cm7.h **** 
+1963:Drivers/CMSIS/Include/core_cm7.h **** 
+1964:Drivers/CMSIS/Include/core_cm7.h **** /**
+1965:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Set Pending Interrupt
+1966:Drivers/CMSIS/Include/core_cm7.h ****   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+1967:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1968:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1969:Drivers/CMSIS/Include/core_cm7.h ****  */
+ARM GAS  /tmp/ccdsDELB.s 			page 36
+
+
+1970:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+1971:Drivers/CMSIS/Include/core_cm7.h **** {
+1972:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1973:Drivers/CMSIS/Include/core_cm7.h ****   {
+1974:Drivers/CMSIS/Include/core_cm7.h ****     NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+1975:Drivers/CMSIS/Include/core_cm7.h ****   }
+1976:Drivers/CMSIS/Include/core_cm7.h **** }
+1977:Drivers/CMSIS/Include/core_cm7.h **** 
+1978:Drivers/CMSIS/Include/core_cm7.h **** 
+1979:Drivers/CMSIS/Include/core_cm7.h **** /**
+1980:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Clear Pending Interrupt
+1981:Drivers/CMSIS/Include/core_cm7.h ****   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+1982:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1983:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1984:Drivers/CMSIS/Include/core_cm7.h ****  */
+1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+1986:Drivers/CMSIS/Include/core_cm7.h **** {
+1987:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1988:Drivers/CMSIS/Include/core_cm7.h ****   {
+1989:Drivers/CMSIS/Include/core_cm7.h ****     NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+1990:Drivers/CMSIS/Include/core_cm7.h ****   }
+1991:Drivers/CMSIS/Include/core_cm7.h **** }
+1992:Drivers/CMSIS/Include/core_cm7.h **** 
+1993:Drivers/CMSIS/Include/core_cm7.h **** 
+1994:Drivers/CMSIS/Include/core_cm7.h **** /**
+1995:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Get Active Interrupt
+1996:Drivers/CMSIS/Include/core_cm7.h ****   \details Reads the active register in the NVIC and returns the active bit for the device specific
+1997:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1998:Drivers/CMSIS/Include/core_cm7.h ****   \return             0  Interrupt status is not active.
+1999:Drivers/CMSIS/Include/core_cm7.h ****   \return             1  Interrupt status is active.
+2000:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+2001:Drivers/CMSIS/Include/core_cm7.h ****  */
+2002:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+2003:Drivers/CMSIS/Include/core_cm7.h **** {
+2004:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+2005:Drivers/CMSIS/Include/core_cm7.h ****   {
+2006:Drivers/CMSIS/Include/core_cm7.h ****     return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
+2007:Drivers/CMSIS/Include/core_cm7.h ****   }
+2008:Drivers/CMSIS/Include/core_cm7.h ****   else
+2009:Drivers/CMSIS/Include/core_cm7.h ****   {
+2010:Drivers/CMSIS/Include/core_cm7.h ****     return(0U);
+2011:Drivers/CMSIS/Include/core_cm7.h ****   }
+2012:Drivers/CMSIS/Include/core_cm7.h **** }
+2013:Drivers/CMSIS/Include/core_cm7.h **** 
+2014:Drivers/CMSIS/Include/core_cm7.h **** 
+2015:Drivers/CMSIS/Include/core_cm7.h **** /**
+2016:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Set Interrupt Priority
+2017:Drivers/CMSIS/Include/core_cm7.h ****   \details Sets the priority of a device specific interrupt or a processor exception.
+2018:Drivers/CMSIS/Include/core_cm7.h ****            The interrupt number can be positive to specify a device specific interrupt,
+2019:Drivers/CMSIS/Include/core_cm7.h ****            or negative to specify a processor exception.
+2020:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Interrupt number.
+2021:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]  priority  Priority to set.
+2022:Drivers/CMSIS/Include/core_cm7.h ****   \note    The priority cannot be set for every processor exception.
+2023:Drivers/CMSIS/Include/core_cm7.h ****  */
+2024:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+2025:Drivers/CMSIS/Include/core_cm7.h **** {
+2026:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+ARM GAS  /tmp/ccdsDELB.s 			page 37
+
+
+2027:Drivers/CMSIS/Include/core_cm7.h ****   {
+2028:Drivers/CMSIS/Include/core_cm7.h ****     NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (
+2029:Drivers/CMSIS/Include/core_cm7.h ****   }
+2030:Drivers/CMSIS/Include/core_cm7.h ****   else
+2031:Drivers/CMSIS/Include/core_cm7.h ****   {
+2032:Drivers/CMSIS/Include/core_cm7.h ****     SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (
+2033:Drivers/CMSIS/Include/core_cm7.h ****   }
+2034:Drivers/CMSIS/Include/core_cm7.h **** }
+2035:Drivers/CMSIS/Include/core_cm7.h **** 
+2036:Drivers/CMSIS/Include/core_cm7.h **** 
+2037:Drivers/CMSIS/Include/core_cm7.h **** /**
+2038:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Get Interrupt Priority
+2039:Drivers/CMSIS/Include/core_cm7.h ****   \details Reads the priority of a device specific interrupt or a processor exception.
+2040:Drivers/CMSIS/Include/core_cm7.h ****            The interrupt number can be positive to specify a device specific interrupt,
+2041:Drivers/CMSIS/Include/core_cm7.h ****            or negative to specify a processor exception.
+2042:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]   IRQn  Interrupt number.
+2043:Drivers/CMSIS/Include/core_cm7.h ****   \return             Interrupt Priority.
+2044:Drivers/CMSIS/Include/core_cm7.h ****                       Value is aligned automatically to the implemented priority bits of the microc
+2045:Drivers/CMSIS/Include/core_cm7.h ****  */
+2046:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+2047:Drivers/CMSIS/Include/core_cm7.h **** {
+2048:Drivers/CMSIS/Include/core_cm7.h **** 
+2049:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+2050:Drivers/CMSIS/Include/core_cm7.h ****   {
+2051:Drivers/CMSIS/Include/core_cm7.h ****     return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+2052:Drivers/CMSIS/Include/core_cm7.h ****   }
+2053:Drivers/CMSIS/Include/core_cm7.h ****   else
+2054:Drivers/CMSIS/Include/core_cm7.h ****   {
+2055:Drivers/CMSIS/Include/core_cm7.h ****     return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+2056:Drivers/CMSIS/Include/core_cm7.h ****   }
+2057:Drivers/CMSIS/Include/core_cm7.h **** }
+2058:Drivers/CMSIS/Include/core_cm7.h **** 
+2059:Drivers/CMSIS/Include/core_cm7.h **** 
+2060:Drivers/CMSIS/Include/core_cm7.h **** /**
+2061:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Encode Priority
+2062:Drivers/CMSIS/Include/core_cm7.h ****   \details Encodes the priority for an interrupt with the given priority group,
+2063:Drivers/CMSIS/Include/core_cm7.h ****            preemptive priority value, and subpriority value.
+2064:Drivers/CMSIS/Include/core_cm7.h ****            In case of a conflict between priority grouping and available
+2065:Drivers/CMSIS/Include/core_cm7.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+2066:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]     PriorityGroup  Used priority group.
+2067:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+2068:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]       SubPriority  Subpriority value (starting from 0).
+2069:Drivers/CMSIS/Include/core_cm7.h ****   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetP
+2070:Drivers/CMSIS/Include/core_cm7.h ****  */
+2071:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
+2072:Drivers/CMSIS/Include/core_cm7.h **** {
+  28              		.loc 1 2072 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+2073:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
+  33              		.loc 1 2073 3 view .LVU1
+  34              		.loc 1 2073 12 is_stmt 0 view .LVU2
+  35 0000 00F00700 		and	r0, r0, #7
+  36              	.LVL1:
+2074:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t PreemptPriorityBits;
+ARM GAS  /tmp/ccdsDELB.s 			page 38
+
+
+  37              		.loc 1 2074 3 is_stmt 1 view .LVU3
+2075:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t SubPriorityBits;
+  38              		.loc 1 2075 3 view .LVU4
+2076:Drivers/CMSIS/Include/core_cm7.h **** 
+2077:Drivers/CMSIS/Include/core_cm7.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
+  39              		.loc 1 2077 3 view .LVU5
+  40              		.loc 1 2077 31 is_stmt 0 view .LVU6
+  41 0004 C0F1070C 		rsb	ip, r0, #7
+  42              		.loc 1 2077 23 view .LVU7
+  43 0008 BCF1040F 		cmp	ip, #4
+  44 000c 28BF     		it	cs
+  45 000e 4FF0040C 		movcs	ip, #4
+  46              	.LVL2:
+2078:Drivers/CMSIS/Include/core_cm7.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+  47              		.loc 1 2078 3 is_stmt 1 view .LVU8
+  48              		.loc 1 2078 44 is_stmt 0 view .LVU9
+  49 0012 031D     		adds	r3, r0, #4
+  50              		.loc 1 2078 109 view .LVU10
+  51 0014 062B     		cmp	r3, #6
+  52 0016 0CD9     		bls	.L3
+  53              		.loc 1 2078 109 discriminator 1 view .LVU11
+  54 0018 C31E     		subs	r3, r0, #3
+  55              	.L2:
+  56              	.LVL3:
+2079:Drivers/CMSIS/Include/core_cm7.h **** 
+2080:Drivers/CMSIS/Include/core_cm7.h ****   return (
+  57              		.loc 1 2080 3 is_stmt 1 discriminator 4 view .LVU12
+2081:Drivers/CMSIS/Include/core_cm7.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
+  58              		.loc 1 2081 30 is_stmt 0 discriminator 4 view .LVU13
+  59 001a 4FF0FF30 		mov	r0, #-1
+  60              	.LVL4:
+  61              		.loc 1 2081 30 discriminator 4 view .LVU14
+  62 001e 00FA0CFC 		lsl	ip, r0, ip
+  63              	.LVL5:
+  64              		.loc 1 2081 30 discriminator 4 view .LVU15
+  65 0022 21EA0C01 		bic	r1, r1, ip
+  66              	.LVL6:
+  67              		.loc 1 2081 82 discriminator 4 view .LVU16
+  68 0026 9940     		lsls	r1, r1, r3
+2082:Drivers/CMSIS/Include/core_cm7.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+  69              		.loc 1 2082 30 discriminator 4 view .LVU17
+  70 0028 9840     		lsls	r0, r0, r3
+  71 002a 22EA0000 		bic	r0, r2, r0
+2083:Drivers/CMSIS/Include/core_cm7.h ****          );
+2084:Drivers/CMSIS/Include/core_cm7.h **** }
+  72              		.loc 1 2084 1 discriminator 4 view .LVU18
+  73 002e 0843     		orrs	r0, r0, r1
+  74 0030 7047     		bx	lr
+  75              	.LVL7:
+  76              	.L3:
+2078:Drivers/CMSIS/Include/core_cm7.h **** 
+  77              		.loc 1 2078 109 view .LVU19
+  78 0032 0023     		movs	r3, #0
+  79 0034 F1E7     		b	.L2
+  80              		.cfi_endproc
+  81              	.LFE113:
+  83              		.section	.text.MX_SDMMC1_SD_Init,"ax",%progbits
+ARM GAS  /tmp/ccdsDELB.s 			page 39
+
+
+  84              		.align	1
+  85              		.syntax unified
+  86              		.thumb
+  87              		.thumb_func
+  88              		.fpu fpv5-d16
+  90              	MX_SDMMC1_SD_Init:
+  91              	.LFB1190:
+  92              		.file 2 "Src/main.c"
+   1:Src/main.c    **** /* USER CODE BEGIN Header */
+   2:Src/main.c    **** /**
+   3:Src/main.c    ****   ******************************************************************************
+   4:Src/main.c    ****   * @file           : main.c
+   5:Src/main.c    ****   * @brief          : Main program body
+   6:Src/main.c    ****   ******************************************************************************
+   7:Src/main.c    ****   * @attention
+   8:Src/main.c    ****   *
+   9:Src/main.c    ****   * Copyright (c) 2023 STMicroelectronics.
+  10:Src/main.c    ****   * All rights reserved.
+  11:Src/main.c    ****   *
+  12:Src/main.c    ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Src/main.c    ****   * in the root directory of this software component.
+  14:Src/main.c    ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Src/main.c    ****   *
+  16:Src/main.c    ****   ******************************************************************************
+  17:Src/main.c    ****   */
+  18:Src/main.c    **** /* USER CODE END Header */
+  19:Src/main.c    **** /* Includes ------------------------------------------------------------------*/
+  20:Src/main.c    **** #include "main.h"
+  21:Src/main.c    **** #include "fatfs.h"
+  22:Src/main.c    **** 
+  23:Src/main.c    **** /* Private includes ----------------------------------------------------------*/
+  24:Src/main.c    **** /* USER CODE BEGIN Includes */
+  25:Src/main.c    **** //	#include "math.h"
+  26:Src/main.c    **** 	#include "File_Handling.h"
+  27:Src/main.c    **** 	#include 
+  28:Src/main.c    **** /* USER CODE END Includes */
+  29:Src/main.c    **** 
+  30:Src/main.c    **** /* Private typedef -----------------------------------------------------------*/
+  31:Src/main.c    **** /* USER CODE BEGIN PTD */
+  32:Src/main.c    **** 
+  33:Src/main.c    **** /* USER CODE END PTD */
+  34:Src/main.c    **** 
+  35:Src/main.c    **** /* Private define ------------------------------------------------------------*/
+  36:Src/main.c    **** /* USER CODE BEGIN PD */
+  37:Src/main.c    **** /* USER CODE END PD */
+  38:Src/main.c    **** 
+  39:Src/main.c    **** /* Private macro -------------------------------------------------------------*/
+  40:Src/main.c    **** /* USER CODE BEGIN PM */
+  41:Src/main.c    **** 
+  42:Src/main.c    **** /* USER CODE END PM */
+  43:Src/main.c    **** 
+  44:Src/main.c    **** /* Private variables ---------------------------------------------------------*/
+  45:Src/main.c    **** ADC_HandleTypeDef hadc1;
+  46:Src/main.c    **** ADC_HandleTypeDef hadc3;
+  47:Src/main.c    **** 
+  48:Src/main.c    **** SD_HandleTypeDef hsd1;
+  49:Src/main.c    **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 40
+
+
+  50:Src/main.c    **** TIM_HandleTypeDef htim10;
+  51:Src/main.c    **** 
+  52:Src/main.c    **** /* USER CODE BEGIN PV */
+  53:Src/main.c    **** uint32_t TO6, TO6_before, TO6_stop, TO6_uart, SD_SEEK, SD_SLIDE, temp32, TO7, TO7_before, TO7_PID, 
+  54:Src/main.c    **** uint8_t uart_buf, CPU_state, CPU_state_old, UART_transmission_request, State_Data[2], UART_DATA[DL_
+  55:Src/main.c    **** uint16_t UART_rec_incr, UART_header, CS_result, temp16, Long_Data[DL_16], COMMAND[CL_16];//, SD_mat
+  56:Src/main.c    **** FRESULT fresult;  // result
+  57:Src/main.c    **** int test;
+  58:Src/main.c    **** unsigned long fgoto, sizeoffile;//file pointer of the file object & size of file FPGA_RECEIVE_DATA_
+  59:Src/main.c    **** 
+  60:Src/main.c    **** LDx_SetupTypeDef LD1_curr_setup, LD2_curr_setup, LD1_def_setup, LD2_def_setup;
+  61:Src/main.c    **** Work_SetupTypeDef Curr_setup, Def_setup;
+  62:Src/main.c    **** LDx_ParamTypeDef LD1_param, LD2_param;
+  63:Src/main.c    **** 
+  64:Src/main.c    **** task_t task;
+  65:Src/main.c    **** 
+  66:Src/main.c    **** /* USER CODE END PV */
+  67:Src/main.c    **** 
+  68:Src/main.c    **** /* Private function prototypes -----------------------------------------------*/
+  69:Src/main.c    **** void SystemClock_Config(void);
+  70:Src/main.c    **** static void MX_GPIO_Init(void);
+  71:Src/main.c    **** static void MX_DMA_Init(void);
+  72:Src/main.c    **** static void MX_SPI4_Init(void);
+  73:Src/main.c    **** static void MX_TIM2_Init(void);
+  74:Src/main.c    **** static void MX_TIM5_Init(void);
+  75:Src/main.c    **** static void MX_ADC1_Init(void);
+  76:Src/main.c    **** static void MX_ADC3_Init(void);
+  77:Src/main.c    **** static void MX_SPI2_Init(void);
+  78:Src/main.c    **** static void MX_SPI5_Init(void);
+  79:Src/main.c    **** static void MX_SPI6_Init(void);
+  80:Src/main.c    **** static void MX_USART1_UART_Init(void);
+  81:Src/main.c    **** static void MX_SDMMC1_SD_Init(void);
+  82:Src/main.c    **** static void MX_TIM7_Init(void);
+  83:Src/main.c    **** static void MX_TIM6_Init(void);
+  84:Src/main.c    **** static void MX_TIM10_Init(void);
+  85:Src/main.c    **** /* USER CODE BEGIN PFP */
+  86:Src/main.c    **** static void Init_params(void);
+  87:Src/main.c    **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_
+  88:Src/main.c    **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_
+  89:Src/main.c    **** static void Set_LTEC(uint8_t num, uint16_t DATA);
+  90:Src/main.c    **** static uint16_t MPhD_T(uint8_t num);
+  91:Src/main.c    **** static uint16_t Get_ADC(uint8_t num);
+  92:Src/main.c    **** static uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_resul
+  93:Src/main.c    **** uint8_t CheckChecksum(uint16_t *pbuff);
+  94:Src/main.c    **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len);
+  95:Src/main.c    **** //int SD_Init(void);
+  96:Src/main.c    **** int SD_SAVE(uint16_t *pbuff);
+  97:Src/main.c    **** //uint32_t Get_Length(void);
+  98:Src/main.c    **** int SD_READ(uint16_t *pbuff);
+  99:Src/main.c    **** int SD_REMOVE(void);
+ 100:Src/main.c    **** void USART_TX (uint8_t* dt, uint16_t sz);
+ 101:Src/main.c    **** void USART_TX_DMA (uint16_t sz);
+ 102:Src/main.c    **** static void Stop_TIM10();
+ 103:Src/main.c    **** /* USER CODE END PFP */
+ 104:Src/main.c    **** 
+ 105:Src/main.c    **** /* Private user code ---------------------------------------------------------*/
+ 106:Src/main.c    **** /* USER CODE BEGIN 0 */
+ARM GAS  /tmp/ccdsDELB.s 			page 41
+
+
+ 107:Src/main.c    **** 
+ 108:Src/main.c    **** /* USER CODE END 0 */
+ 109:Src/main.c    **** 
+ 110:Src/main.c    **** /**
+ 111:Src/main.c    ****   * @brief  The application entry point.
+ 112:Src/main.c    ****   * @retval int
+ 113:Src/main.c    ****   */
+ 114:Src/main.c    **** int main(void)
+ 115:Src/main.c    **** {
+ 116:Src/main.c    ****   /* USER CODE BEGIN 1 */
+ 117:Src/main.c    **** 	HAL_StatusTypeDef st;
+ 118:Src/main.c    ****   /* USER CODE END 1 */
+ 119:Src/main.c    **** 
+ 120:Src/main.c    ****   /* MCU Configuration--------------------------------------------------------*/
+ 121:Src/main.c    **** 
+ 122:Src/main.c    ****   /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ 123:Src/main.c    ****   HAL_Init();
+ 124:Src/main.c    **** 
+ 125:Src/main.c    ****   /* USER CODE BEGIN Init */
+ 126:Src/main.c    **** 	/*I hope you don't forget that first - MX_DMA_Init(); and than - MX_USART1_UART_Init();*/
+ 127:Src/main.c    ****   /* USER CODE END Init */
+ 128:Src/main.c    **** 
+ 129:Src/main.c    ****   /* Configure the system clock */
+ 130:Src/main.c    ****   SystemClock_Config();
+ 131:Src/main.c    **** 
+ 132:Src/main.c    ****   /* USER CODE BEGIN SysInit */
+ 133:Src/main.c    **** 	
+ 134:Src/main.c    ****   /* USER CODE END SysInit */
+ 135:Src/main.c    **** 
+ 136:Src/main.c    ****   /* Initialize all configured peripherals */
+ 137:Src/main.c    ****   MX_GPIO_Init();
+ 138:Src/main.c    ****   MX_DMA_Init();
+ 139:Src/main.c    ****   MX_SPI4_Init();
+ 140:Src/main.c    ****   MX_FATFS_Init();
+ 141:Src/main.c    ****   MX_TIM2_Init();
+ 142:Src/main.c    ****   MX_TIM5_Init();
+ 143:Src/main.c    ****   MX_ADC1_Init();
+ 144:Src/main.c    ****   MX_ADC3_Init();
+ 145:Src/main.c    ****   MX_SPI2_Init();
+ 146:Src/main.c    ****   MX_SPI5_Init();
+ 147:Src/main.c    ****   MX_SPI6_Init();
+ 148:Src/main.c    ****   MX_USART1_UART_Init();
+ 149:Src/main.c    ****   MX_SDMMC1_SD_Init();
+ 150:Src/main.c    ****   MX_TIM7_Init();
+ 151:Src/main.c    ****   MX_TIM6_Init();
+ 152:Src/main.c    ****   MX_TIM10_Init();
+ 153:Src/main.c    ****   /* USER CODE BEGIN 2 */
+ 154:Src/main.c    **** 	Init_params();
+ 155:Src/main.c    ****   /* USER CODE END 2 */
+ 156:Src/main.c    **** 
+ 157:Src/main.c    ****   /* Infinite loop */
+ 158:Src/main.c    ****   /* USER CODE BEGIN WHILE */
+ 159:Src/main.c    ****   while (1)
+ 160:Src/main.c    ****   {
+ 161:Src/main.c    **** 		if ((HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin)==GPIO_PIN_SET)&&(u_rx_flg == 0))
+ 162:Src/main.c    **** 		{
+ 163:Src/main.c    **** 			//NVIC_DisableIRQ(USART1_IRQn);
+ARM GAS  /tmp/ccdsDELB.s 			page 42
+
+
+ 164:Src/main.c    **** 			LL_USART_EnableIT_PE(USART1);
+ 165:Src/main.c    **** 			LL_USART_EnableIT_RXNE(USART1);
+ 166:Src/main.c    **** 			LL_USART_EnableIT_ERROR(USART1);
+ 167:Src/main.c    **** 			NVIC_SetPriority(USART1_IRQn, 0);
+ 168:Src/main.c    **** 			NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag...
+ 169:Src/main.c    **** 			u_rx_flg = 1;
+ 170:Src/main.c    **** 		}
+ 171:Src/main.c    **** //		else
+ 172:Src/main.c    **** //		{
+ 173:Src/main.c    **** //			//NVIC_DisableIRQ(USART1_IRQn);
+ 174:Src/main.c    **** //			u_rx_flg = 0;
+ 175:Src/main.c    **** //		}
+ 176:Src/main.c    **** 			switch (CPU_state)
+ 177:Src/main.c    **** 			{
+ 178:Src/main.c    **** 				case HALT://0 - Default state
+ 179:Src/main.c    **** 					CPU_state_old = HALT;//Save main current cycle
+ 180:Src/main.c    **** 					task.current_param = task.min_param;
+ 181:Src/main.c    **** 					Stop_TIM10();
+ 182:Src/main.c    **** 				break;
+ 183:Src/main.c    **** 				case DECODE_ENABLE://1 - Decode rec. message
+ 184:Src/main.c    **** 					CS_result = CalculateChecksum(COMMAND, CL_16-2);
+ 185:Src/main.c    **** 					if (CheckChecksum(COMMAND))
+ 186:Src/main.c    **** 					{
+ 187:Src/main.c    **** 						LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC & TEC1
+ 188:Src/main.c    **** 						LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2
+ 189:Src/main.c    **** 						Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup);
+ 190:Src/main.c    **** 						TO6_before = TO6;
+ 191:Src/main.c    **** 						//LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP;
+ 192:Src/main.c    **** 						//LD2_param.LD_TEMP_Before = LD2_param.LD_TEMP;
+ 193:Src/main.c    **** 						CPU_state = WORK_ENABLE;
+ 194:Src/main.c    **** 						CPU_state_old = WORK_ENABLE;//Save main current cycle
+ 195:Src/main.c    **** 					}
+ 196:Src/main.c    **** 					else
+ 197:Src/main.c    **** 					{
+ 198:Src/main.c    **** 						State_Data[0] |= UART_DECODE_ERR;
+ 199:Src/main.c    **** 						CPU_state = DEFAULT_ENABLE;
+ 200:Src/main.c    **** 						CPU_state_old = HALT;//Save main current cycle
+ 201:Src/main.c    **** 					}
+ 202:Src/main.c    **** 					UART_transmission_request = MESS_01;
+ 203:Src/main.c    **** 				break;
+ 204:Src/main.c    **** 				case DEFAULT_ENABLE://2 - Go to HALT
+ 205:Src/main.c    **** 					//Set current setup to default
+ 206:Src/main.c    **** 					task.current_param = task.min_param;
+ 207:Src/main.c    **** 					Stop_TIM10();
+ 208:Src/main.c    **** 					Init_params();
+ 209:Src/main.c    **** 					LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1
+ 210:Src/main.c    **** 					LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2
+ 211:Src/main.c    **** 					CPU_state = HALT;
+ 212:Src/main.c    **** 					CPU_state_old = HALT;//Save main current cycle
+ 213:Src/main.c    **** 					UART_transmission_request = MESS_01;
+ 214:Src/main.c    **** 				break;
+ 215:Src/main.c    **** 				case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting!
+ 216:Src/main.c    **** 					temp16 = SD_READ(&Long_Data[0]);
+ 217:Src/main.c    **** 					State_Data[0]|=temp16&0xff;
+ 218:Src/main.c    **** 					if (temp16==0)
+ 219:Src/main.c    **** 					{	
+ 220:Src/main.c    **** 						UART_transmission_request = MESS_03;
+ARM GAS  /tmp/ccdsDELB.s 			page 43
+
+
+ 221:Src/main.c    **** 					}
+ 222:Src/main.c    **** 					else
+ 223:Src/main.c    **** 					{
+ 224:Src/main.c    **** 						UART_transmission_request = MESS_01;
+ 225:Src/main.c    **** 					}
+ 226:Src/main.c    **** 					CPU_state_old = HALT;
+ 227:Src/main.c    **** 					CPU_state = CPU_state_old;//Return to main current cycle
+ 228:Src/main.c    **** 				break;
+ 229:Src/main.c    **** 				case TRANS_ENABLE://4 - Transmith current packet
+ 230:Src/main.c    **** 					UART_transmission_request = MESS_02;
+ 231:Src/main.c    **** 					CPU_state = CPU_state_old;//Return to main current cycle
+ 232:Src/main.c    **** 				break;
+ 233:Src/main.c    **** 				case REMOVE_FILE://5 - Remove file from SD
+ 234:Src/main.c    **** 					State_Data[0]|=SD_REMOVE()&0xff;
+ 235:Src/main.c    **** 					UART_transmission_request = MESS_01;
+ 236:Src/main.c    **** 					CPU_state = CPU_state_old;
+ 237:Src/main.c    **** 				break;
+ 238:Src/main.c    **** 				case STATE://6 - Transmith state message
+ 239:Src/main.c    **** 					UART_transmission_request = MESS_01;
+ 240:Src/main.c    **** 					CPU_state = CPU_state_old;//Return to main current cycle
+ 241:Src/main.c    **** 				break;
+ 242:Src/main.c    **** 				case WORK_ENABLE://7 - Main work cycle
+ 243:Src/main.c    **** 					task.current_param = task.min_param;
+ 244:Src/main.c    **** 					Stop_TIM10();
+ 245:Src/main.c    **** 					if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz)
+ 246:Src/main.c    **** 					{
+ 247:Src/main.c    **** 						TO7_before = TO7;
+ 248:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 249:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 250:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 251:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 252:Src/main.c    **** 						
+ 253:Src/main.c    **** 						//Correct temperature in all pulses
+ 254:Src/main.c    **** 						(void) MPhD_T(3);
+ 255:Src/main.c    **** 						LD1_param.LD_CURR_TEMP = MPhD_T(3);
+ 256:Src/main.c    **** 						(void) MPhD_T(4);
+ 257:Src/main.c    **** 						LD2_param.LD_CURR_TEMP = MPhD_T(4);
+ 258:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 259:Src/main.c    **** 						Set_LTEC(3, temp16);//Drive Laser TEC 1
+ 260:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2);
+ 261:Src/main.c    **** 						Set_LTEC(4, temp16);//Drive Laser TEC 2
+ 262:Src/main.c    **** 						
+ 263:Src/main.c    **** 						Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data
+ 264:Src/main.c    **** 						Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data
+ 265:Src/main.c    **** 
+ 266:Src/main.c    **** 						Set_LTEC(1,LD1_curr_setup.CURRENT);//Drive Laser diode 1
+ 267:Src/main.c    **** 						Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2
+ 268:Src/main.c    **** 
+ 269:Src/main.c    **** 						//Prepare DATA of internals ADCs
+ 270:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 271:Src/main.c    **** 						temp16 = Get_ADC(0);
+ 272:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 273:Src/main.c    **** 						Long_Data[7] = temp16;
+ 274:Src/main.c    **** 						
+ 275:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 276:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 277:Src/main.c    **** 						Long_Data[8] = temp16;
+ARM GAS  /tmp/ccdsDELB.s 			page 44
+
+
+ 278:Src/main.c    **** 						
+ 279:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 280:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 281:Src/main.c    **** 						Long_Data[9] = temp16;
+ 282:Src/main.c    **** 						
+ 283:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 284:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 285:Src/main.c    **** 						Long_Data[10] = temp16;
+ 286:Src/main.c    **** 						
+ 287:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 288:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 289:Src/main.c    **** 						Long_Data[11] = temp16;
+ 290:Src/main.c    **** 						temp16 = Get_ADC(2);
+ 291:Src/main.c    **** 						
+ 292:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 293:Src/main.c    **** 						temp16 = Get_ADC(3);
+ 294:Src/main.c    **** 						temp16 = Get_ADC(4);
+ 295:Src/main.c    **** 						Long_Data[12] = temp16;
+ 296:Src/main.c    **** 						temp16 = Get_ADC(5);
+ 297:Src/main.c    **** 													
+ 298:Src/main.c    **** 						//Put the timer tick to Long_Data:
+ 299:Src/main.c    **** 						TO6_stop = TO6;
+ 300:Src/main.c    **** 						Long_Data[3] = (TO6_stop)&0xffff;
+ 301:Src/main.c    **** 						Long_Data[4] = (TO6_stop>>16)&0xffff;
+ 302:Src/main.c    **** 						
+ 303:Src/main.c    **** 						//Put the average temperature of LD1 to Long_Data:
+ 304:Src/main.c    **** 						Long_Data[5] = LD1_param.LD_CURR_TEMP;
+ 305:Src/main.c    **** 						
+ 306:Src/main.c    **** 						//Put the average temperature of LD2 to Long_Data:
+ 307:Src/main.c    **** 						Long_Data[6] = LD2_param.LD_CURR_TEMP;
+ 308:Src/main.c    **** 
+ 309:Src/main.c    **** 						if (Curr_setup.SD_EN==1)
+ 310:Src/main.c    **** 						{
+ 311:Src/main.c    **** 							CS_result = CalculateChecksum(&Long_Data[1], DL_16-2);
+ 312:Src/main.c    **** 							Long_Data[DL_16-1] = CS_result;
+ 313:Src/main.c    **** 							temp16 = SD_SAVE(&Long_Data[0]);
+ 314:Src/main.c    **** 							State_Data[0]|=temp16&0xff;
+ 315:Src/main.c    **** 						}
+ 316:Src/main.c    **** 						CPU_state_old = WORK_ENABLE;//Save main current cycle
+ 317:Src/main.c    **** 					}
+ 318:Src/main.c    **** 				break;
+ 319:Src/main.c    **** 				case DECODE_TASK:
+ 320:Src/main.c    **** 					if (CheckChecksum(COMMAND))
+ 321:Src/main.c    **** 					{
+ 322:Src/main.c    **** 						Decode_task(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup);
+ 323:Src/main.c    **** 						TO6_before = TO6;
+ 324:Src/main.c    **** 						CPU_state = RUN_TASK;
+ 325:Src/main.c    **** 						CPU_state_old = RUN_TASK;//Save main current cycle
+ 326:Src/main.c    **** 					}
+ 327:Src/main.c    **** 					else
+ 328:Src/main.c    **** 					{
+ 329:Src/main.c    **** 						State_Data[0] |= UART_DECODE_ERR;
+ 330:Src/main.c    **** 						CPU_state = DEFAULT_ENABLE;
+ 331:Src/main.c    **** 						CPU_state_old = HALT;//Save main current cycle
+ 332:Src/main.c    **** 					}
+ 333:Src/main.c    **** 					UART_transmission_request = MESS_01;
+ 334:Src/main.c    **** 				break;
+ARM GAS  /tmp/ccdsDELB.s 			page 45
+
+
+ 335:Src/main.c    **** 				case RUN_TASK:
+ 336:Src/main.c    **** 					switch (task.task_type)
+ 337:Src/main.c    **** 					{
+ 338:Src/main.c    **** 					case TT_CHANGE_CURR_1:
+ 339:Src/main.c    **** 						Set_LTEC(TT_CHANGE_CURR_2, task.curr);
+ 340:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_1);
+ 341:Src/main.c    **** 						LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1);
+ 342:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_2);
+ 343:Src/main.c    **** 						LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2);
+ 344:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 345:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1
+ 346:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2);
+ 347:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2
+ 348:Src/main.c    **** 
+ 349:Src/main.c    **** 						// Toggle pin for oscilloscope
+ 350:Src/main.c    **** 						HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET);
+ 351:Src/main.c    **** 						HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET);
+ 352:Src/main.c    **** 		
+ 353:Src/main.c    **** 						st = HAL_TIM_Base_Start_IT(&htim10);
+ 354:Src/main.c    **** 						if (st != HAL_OK)
+ 355:Src/main.c    **** 							while(1);
+ 356:Src/main.c    **** 						while (task.current_param < task.max_param)
+ 357:Src/main.c    **** 						{
+ 358:Src/main.c    **** 							if (TIM10_coflag)
+ 359:Src/main.c    **** 							{
+ 360:Src/main.c    **** 								Set_LTEC(TT_CHANGE_CURR_1, task.current_param);
+ 361:Src/main.c    **** 								task.current_param += task.delta_param;
+ 362:Src/main.c    **** 								TO10 = 0;
+ 363:Src/main.c    **** 								TIM10_coflag = 0;
+ 364:Src/main.c    **** 							}
+ 365:Src/main.c    **** 						}
+ 366:Src/main.c    **** 						Stop_TIM10();
+ 367:Src/main.c    **** 						task.current_param = task.min_param;
+ 368:Src/main.c    **** 						Set_LTEC(TT_CHANGE_CURR_1, task.current_param);
+ 369:Src/main.c    **** 						if (task.tau > 3)
+ 370:Src/main.c    **** 						{
+ 371:Src/main.c    **** 							TIM10_period = htim10.Init.Period;
+ 372:Src/main.c    **** 							htim10.Init.Period = 9999;
+ 373:Src/main.c    **** 							TO10_counter = (task.tau - 1) * 100;
+ 374:Src/main.c    **** 						}
+ 375:Src/main.c    **** 						HAL_TIM_Base_Start_IT(&htim10);
+ 376:Src/main.c    **** 					break;
+ 377:Src/main.c    **** 					case TT_CHANGE_CURR_2:
+ 378:Src/main.c    **** 						Set_LTEC(TT_CHANGE_CURR_1, task.curr);
+ 379:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_1);
+ 380:Src/main.c    **** 						LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1);
+ 381:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_2);
+ 382:Src/main.c    **** 						LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2);
+ 383:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 384:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1
+ 385:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2);
+ 386:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2
+ 387:Src/main.c    **** 
+ 388:Src/main.c    **** 						// Toggle pin for oscilloscope
+ 389:Src/main.c    **** 						HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET);
+ 390:Src/main.c    **** 						HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET);
+ 391:Src/main.c    **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 46
+
+
+ 392:Src/main.c    **** 						st = HAL_TIM_Base_Start_IT(&htim10);
+ 393:Src/main.c    **** 						if (st != HAL_OK)
+ 394:Src/main.c    **** 							while(1);
+ 395:Src/main.c    **** 						while (task.current_param < task.max_param)
+ 396:Src/main.c    **** 						{
+ 397:Src/main.c    **** 							if (TIM10_coflag)
+ 398:Src/main.c    **** 							{
+ 399:Src/main.c    **** 								Set_LTEC(TT_CHANGE_CURR_2, task.current_param);
+ 400:Src/main.c    **** 								task.current_param += task.delta_param;
+ 401:Src/main.c    **** 								TO10 = 0;
+ 402:Src/main.c    **** 								TIM10_coflag = 0;
+ 403:Src/main.c    **** 							}
+ 404:Src/main.c    **** 						}
+ 405:Src/main.c    **** 						Stop_TIM10();
+ 406:Src/main.c    **** 						task.current_param = task.min_param;
+ 407:Src/main.c    **** 						Set_LTEC(TT_CHANGE_CURR_2, task.current_param);
+ 408:Src/main.c    **** 						if (task.tau > 3)
+ 409:Src/main.c    **** 						{
+ 410:Src/main.c    **** 							TIM10_period = htim10.Init.Period;
+ 411:Src/main.c    **** 							htim10.Init.Period = 9999;
+ 412:Src/main.c    **** 							TO10_counter = (task.tau - 1) * 100;
+ 413:Src/main.c    **** 						}
+ 414:Src/main.c    **** 						HAL_TIM_Base_Start_IT(&htim10);
+ 415:Src/main.c    **** 					break;
+ 416:Src/main.c    **** 					case TT_CHANGE_TEMP_1:
+ 417:Src/main.c    **** 						// isn't implemented
+ 418:Src/main.c    **** 					break;
+ 419:Src/main.c    **** 					case TT_CHANGE_TEMP_2:
+ 420:Src/main.c    **** 						// isn't implemented
+ 421:Src/main.c    **** 					break;
+ 422:Src/main.c    **** 					}
+ 423:Src/main.c    **** 	
+ 424:Src/main.c    **** 					if (TO7>TO7_before)
+ 425:Src/main.c    **** 					{
+ 426:Src/main.c    **** 						TO7_before = TO7;
+ 427:Src/main.c    **** 						
+ 428:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 429:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 430:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 431:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 432:Src/main.c    **** 						
+ 433:Src/main.c    **** 						Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data
+ 434:Src/main.c    **** 						Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data
+ 435:Src/main.c    **** 	
+ 436:Src/main.c    **** 						//Prepare DATA of internals ADCs
+ 437:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 438:Src/main.c    **** 						temp16 = Get_ADC(0);
+ 439:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 440:Src/main.c    **** 						Long_Data[7] = temp16;
+ 441:Src/main.c    **** 						
+ 442:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 443:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 444:Src/main.c    **** 						Long_Data[8] = temp16;
+ 445:Src/main.c    **** 						
+ 446:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 447:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 448:Src/main.c    **** 						Long_Data[9] = temp16;
+ARM GAS  /tmp/ccdsDELB.s 			page 47
+
+
+ 449:Src/main.c    **** 						
+ 450:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 451:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 452:Src/main.c    **** 						Long_Data[10] = temp16;
+ 453:Src/main.c    **** 						
+ 454:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 455:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 456:Src/main.c    **** 						Long_Data[11] = temp16;
+ 457:Src/main.c    **** 						temp16 = Get_ADC(2);
+ 458:Src/main.c    **** 						
+ 459:Src/main.c    **** 						//Put the temperature of LD2 to Long_Data:
+ 460:Src/main.c    **** 						temp16 = Get_ADC(3);
+ 461:Src/main.c    **** 						temp16 = Get_ADC(4);
+ 462:Src/main.c    **** 						Long_Data[12] = temp16;
+ 463:Src/main.c    **** 						temp16 = Get_ADC(5);
+ 464:Src/main.c    **** 													
+ 465:Src/main.c    **** 						//Put the timer tick to Long_Data:
+ 466:Src/main.c    **** 						TO6_stop = TO6;
+ 467:Src/main.c    **** 						Long_Data[3] = (TO6_stop)&0xffff;
+ 468:Src/main.c    **** 						Long_Data[4] = (TO6_stop>>16)&0xffff;
+ 469:Src/main.c    **** 						
+ 470:Src/main.c    **** 						//Put the average temperature of LD1 to Long_Data:
+ 471:Src/main.c    **** 						Long_Data[5] = LD1_param.LD_CURR_TEMP;
+ 472:Src/main.c    **** 						
+ 473:Src/main.c    **** 						//Put the average temperature of LD2 to Long_Data:
+ 474:Src/main.c    **** 						Long_Data[6] = LD2_param.LD_CURR_TEMP;
+ 475:Src/main.c    **** 					}
+ 476:Src/main.c    **** 					while (!TIM10_coflag);
+ 477:Src/main.c    **** 					
+ 478:Src/main.c    **** 					Stop_TIM10();
+ 479:Src/main.c    **** 					
+ 480:Src/main.c    **** 					if (task.tau > 3)
+ 481:Src/main.c    **** 					{
+ 482:Src/main.c    **** 						htim10.Init.Period = TIM10_period;
+ 483:Src/main.c    **** 						TO10_counter = task.dt / 10 - 1;
+ 484:Src/main.c    **** 					}
+ 485:Src/main.c    **** 					
+ 486:Src/main.c    **** 					CPU_state_old = RUN_TASK;
+ 487:Src/main.c    ****         break;
+ 488:Src/main.c    **** 			}
+ 489:Src/main.c    **** 			
+ 490:Src/main.c    **** 		switch (UART_transmission_request)
+ 491:Src/main.c    **** 		{
+ 492:Src/main.c    **** 			case MESS_01://Default state
+ 493:Src/main.c    **** 				USART_TX(State_Data,2);
+ 494:Src/main.c    **** 				//HAL_UART_Transmit(&huart1, State_Data, 2, 10);
+ 495:Src/main.c    **** 				State_Data[0]=0;
+ 496:Src/main.c    **** 				State_Data[1]=0;//All OK!
+ 497:Src/main.c    **** 				UART_transmission_request = NO_MESS;
+ 498:Src/main.c    **** 			break;
+ 499:Src/main.c    **** 			case MESS_02://Transmith packet
+ 500:Src/main.c    **** 				
+ 501:Src/main.c    **** 				//Find CS and put to Long_Data:
+ 502:Src/main.c    **** 				CS_result = CalculateChecksum(&Long_Data[1], DL_16-2);
+ 503:Src/main.c    **** 				Long_Data[DL_16-1] = CS_result;
+ 504:Src/main.c    **** 				
+ 505:Src/main.c    **** 				for (uint16_t i = 0; i < DL_16; i++)
+ARM GAS  /tmp/ccdsDELB.s 			page 48
+
+
+ 506:Src/main.c    **** 				{
+ 507:Src/main.c    **** 					UART_DATA[i*2] = (Long_Data[i])&0xff;
+ 508:Src/main.c    **** 					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+ 509:Src/main.c    **** 				}
+ 510:Src/main.c    **** 				//HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0);
+ 511:Src/main.c    **** 				//HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
+ 512:Src/main.c    **** 				//HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8);
+ 513:Src/main.c    **** 				//huart1.gState = HAL_UART_STATE_READY;
+ 514:Src/main.c    **** 				//hdma_usart1_tx.State=HAL_DMA_STATE_BUSY;
+ 515:Src/main.c    **** 				USART_TX_DMA (DL_8);//Send data by USART using DMA
+ 516:Src/main.c    **** 				UART_transmission_request = NO_MESS;
+ 517:Src/main.c    **** 			break;
+ 518:Src/main.c    **** 			case MESS_03://Transmith saved packet
+ 519:Src/main.c    **** 				for (uint16_t i = 0; i < DL_16; i++)
+ 520:Src/main.c    **** 				{
+ 521:Src/main.c    **** 					UART_DATA[i*2] = (Long_Data[i])&0xff;
+ 522:Src/main.c    **** 					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+ 523:Src/main.c    **** 				}
+ 524:Src/main.c    **** 				//HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
+ 525:Src/main.c    **** 				//HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8);
+ 526:Src/main.c    **** 				//huart1.gState = HAL_UART_STATE_READY;
+ 527:Src/main.c    **** 				//hdma_usart1_tx.State=HAL_DMA_STATE_BUSY;
+ 528:Src/main.c    **** 				USART_TX_DMA (DL_8);//Send data by USART using DMA
+ 529:Src/main.c    **** 				UART_transmission_request = NO_MESS;
+ 530:Src/main.c    **** 			break;			
+ 531:Src/main.c    **** 		}
+ 532:Src/main.c    ****     if ((flg_tmt==1)&&((TO6-TO6_uart)>100))//Uart timeout handle. if timeout beetween zero byte of 
+ 533:Src/main.c    **** 		{
+ 534:Src/main.c    **** 			UART_rec_incr = 0;//Reset uart command counter
+ 535:Src/main.c    **** 			State_Data[0] |= UART_ERR;//timeout error!
+ 536:Src/main.c    **** 			UART_transmission_request = MESS_01;//Send status
+ 537:Src/main.c    **** 			flg_tmt = 0;//Reset timeout flag
+ 538:Src/main.c    **** 		}
+ 539:Src/main.c    ****     /* USER CODE END WHILE */
+ 540:Src/main.c    **** 
+ 541:Src/main.c    ****     /* USER CODE BEGIN 3 */
+ 542:Src/main.c    ****   }
+ 543:Src/main.c    ****   /* USER CODE END 3 */
+ 544:Src/main.c    **** }
+ 545:Src/main.c    **** 
+ 546:Src/main.c    **** /**
+ 547:Src/main.c    ****   * @brief System Clock Configuration
+ 548:Src/main.c    ****   * @retval None
+ 549:Src/main.c    ****   */
+ 550:Src/main.c    **** void SystemClock_Config(void)
+ 551:Src/main.c    **** {
+ 552:Src/main.c    ****   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 553:Src/main.c    ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 554:Src/main.c    **** 
+ 555:Src/main.c    ****   /** Configure the main internal regulator output voltage
+ 556:Src/main.c    ****   */
+ 557:Src/main.c    ****   __HAL_RCC_PWR_CLK_ENABLE();
+ 558:Src/main.c    ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ 559:Src/main.c    **** 
+ 560:Src/main.c    ****   /** Initializes the RCC Oscillators according to the specified parameters
+ 561:Src/main.c    ****   * in the RCC_OscInitTypeDef structure.
+ 562:Src/main.c    ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 49
+
+
+ 563:Src/main.c    ****   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ 564:Src/main.c    ****   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ 565:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 566:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ 567:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLM = 25;
+ 568:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLN = 368;
+ 569:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ 570:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLQ = 8;
+ 571:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLR = 2;
+ 572:Src/main.c    ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 573:Src/main.c    ****   {
+ 574:Src/main.c    ****     Error_Handler();
+ 575:Src/main.c    ****   }
+ 576:Src/main.c    **** 
+ 577:Src/main.c    ****   /** Activate the Over-Drive mode
+ 578:Src/main.c    ****   */
+ 579:Src/main.c    ****   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
+ 580:Src/main.c    ****   {
+ 581:Src/main.c    ****     Error_Handler();
+ 582:Src/main.c    ****   }
+ 583:Src/main.c    **** 
+ 584:Src/main.c    ****   /** Initializes the CPU, AHB and APB buses clocks
+ 585:Src/main.c    ****   */
+ 586:Src/main.c    ****   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 587:Src/main.c    ****                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ 588:Src/main.c    ****   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ 589:Src/main.c    ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 590:Src/main.c    ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ 591:Src/main.c    ****   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+ 592:Src/main.c    **** 
+ 593:Src/main.c    ****   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK)
+ 594:Src/main.c    ****   {
+ 595:Src/main.c    ****     Error_Handler();
+ 596:Src/main.c    ****   }
+ 597:Src/main.c    **** }
+ 598:Src/main.c    **** 
+ 599:Src/main.c    **** /**
+ 600:Src/main.c    ****   * @brief ADC1 Initialization Function
+ 601:Src/main.c    ****   * @param None
+ 602:Src/main.c    ****   * @retval None
+ 603:Src/main.c    ****   */
+ 604:Src/main.c    **** static void MX_ADC1_Init(void)
+ 605:Src/main.c    **** {
+ 606:Src/main.c    **** 
+ 607:Src/main.c    ****   /* USER CODE BEGIN ADC1_Init 0 */
+ 608:Src/main.c    **** 
+ 609:Src/main.c    ****   /* USER CODE END ADC1_Init 0 */
+ 610:Src/main.c    **** 
+ 611:Src/main.c    ****   ADC_ChannelConfTypeDef sConfig = {0};
+ 612:Src/main.c    **** 
+ 613:Src/main.c    ****   /* USER CODE BEGIN ADC1_Init 1 */
+ 614:Src/main.c    **** 
+ 615:Src/main.c    ****   /* USER CODE END ADC1_Init 1 */
+ 616:Src/main.c    **** 
+ 617:Src/main.c    ****   /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con
+ 618:Src/main.c    ****   */
+ 619:Src/main.c    ****   hadc1.Instance = ADC1;
+ARM GAS  /tmp/ccdsDELB.s 			page 50
+
+
+ 620:Src/main.c    ****   hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8;
+ 621:Src/main.c    ****   hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+ 622:Src/main.c    ****   hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
+ 623:Src/main.c    ****   hadc1.Init.ContinuousConvMode = DISABLE;
+ 624:Src/main.c    ****   hadc1.Init.DiscontinuousConvMode = DISABLE;
+ 625:Src/main.c    ****   hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 626:Src/main.c    ****   hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 627:Src/main.c    ****   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 628:Src/main.c    ****   hadc1.Init.NbrOfConversion = 5;
+ 629:Src/main.c    ****   hadc1.Init.DMAContinuousRequests = DISABLE;
+ 630:Src/main.c    ****   hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 631:Src/main.c    ****   if (HAL_ADC_Init(&hadc1) != HAL_OK)
+ 632:Src/main.c    ****   {
+ 633:Src/main.c    ****     Error_Handler();
+ 634:Src/main.c    ****   }
+ 635:Src/main.c    **** 
+ 636:Src/main.c    ****   /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it
+ 637:Src/main.c    ****   */
+ 638:Src/main.c    ****   sConfig.Channel = ADC_CHANNEL_9;
+ 639:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 640:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
+ 641:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 642:Src/main.c    ****   {
+ 643:Src/main.c    ****     Error_Handler();
+ 644:Src/main.c    ****   }
+ 645:Src/main.c    **** 
+ 646:Src/main.c    ****   /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it
+ 647:Src/main.c    ****   */
+ 648:Src/main.c    ****   sConfig.Channel = ADC_CHANNEL_8;
+ 649:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_2;
+ 650:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 651:Src/main.c    ****   {
+ 652:Src/main.c    ****     Error_Handler();
+ 653:Src/main.c    ****   }
+ 654:Src/main.c    **** 
+ 655:Src/main.c    ****   /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it
+ 656:Src/main.c    ****   */
+ 657:Src/main.c    ****   sConfig.Channel = ADC_CHANNEL_2;
+ 658:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_3;
+ 659:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 660:Src/main.c    ****   {
+ 661:Src/main.c    ****     Error_Handler();
+ 662:Src/main.c    ****   }
+ 663:Src/main.c    **** 
+ 664:Src/main.c    ****   /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it
+ 665:Src/main.c    ****   */
+ 666:Src/main.c    ****   sConfig.Channel = ADC_CHANNEL_10;
+ 667:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_4;
+ 668:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 669:Src/main.c    ****   {
+ 670:Src/main.c    ****     Error_Handler();
+ 671:Src/main.c    ****   }
+ 672:Src/main.c    **** 
+ 673:Src/main.c    ****   /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it
+ 674:Src/main.c    ****   */
+ 675:Src/main.c    ****   sConfig.Channel = ADC_CHANNEL_11;
+ 676:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_5;
+ARM GAS  /tmp/ccdsDELB.s 			page 51
+
+
+ 677:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 678:Src/main.c    ****   {
+ 679:Src/main.c    ****     Error_Handler();
+ 680:Src/main.c    ****   }
+ 681:Src/main.c    ****   /* USER CODE BEGIN ADC1_Init 2 */
+ 682:Src/main.c    **** 
+ 683:Src/main.c    ****   /* USER CODE END ADC1_Init 2 */
+ 684:Src/main.c    **** 
+ 685:Src/main.c    **** }
+ 686:Src/main.c    **** 
+ 687:Src/main.c    **** /**
+ 688:Src/main.c    ****   * @brief ADC3 Initialization Function
+ 689:Src/main.c    ****   * @param None
+ 690:Src/main.c    ****   * @retval None
+ 691:Src/main.c    ****   */
+ 692:Src/main.c    **** static void MX_ADC3_Init(void)
+ 693:Src/main.c    **** {
+ 694:Src/main.c    **** 
+ 695:Src/main.c    ****   /* USER CODE BEGIN ADC3_Init 0 */
+ 696:Src/main.c    **** 
+ 697:Src/main.c    ****   /* USER CODE END ADC3_Init 0 */
+ 698:Src/main.c    **** 
+ 699:Src/main.c    ****   ADC_ChannelConfTypeDef sConfig = {0};
+ 700:Src/main.c    **** 
+ 701:Src/main.c    ****   /* USER CODE BEGIN ADC3_Init 1 */
+ 702:Src/main.c    **** 
+ 703:Src/main.c    ****   /* USER CODE END ADC3_Init 1 */
+ 704:Src/main.c    **** 
+ 705:Src/main.c    ****   /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con
+ 706:Src/main.c    ****   */
+ 707:Src/main.c    ****   hadc3.Instance = ADC3;
+ 708:Src/main.c    ****   hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8;
+ 709:Src/main.c    ****   hadc3.Init.Resolution = ADC_RESOLUTION_12B;
+ 710:Src/main.c    ****   hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
+ 711:Src/main.c    ****   hadc3.Init.ContinuousConvMode = DISABLE;
+ 712:Src/main.c    ****   hadc3.Init.DiscontinuousConvMode = DISABLE;
+ 713:Src/main.c    ****   hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 714:Src/main.c    ****   hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 715:Src/main.c    ****   hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 716:Src/main.c    ****   hadc3.Init.NbrOfConversion = 1;
+ 717:Src/main.c    ****   hadc3.Init.DMAContinuousRequests = DISABLE;
+ 718:Src/main.c    ****   hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 719:Src/main.c    ****   if (HAL_ADC_Init(&hadc3) != HAL_OK)
+ 720:Src/main.c    ****   {
+ 721:Src/main.c    ****     Error_Handler();
+ 722:Src/main.c    ****   }
+ 723:Src/main.c    **** 
+ 724:Src/main.c    ****   /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it
+ 725:Src/main.c    ****   */
+ 726:Src/main.c    ****   sConfig.Channel = ADC_CHANNEL_15;
+ 727:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 728:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
+ 729:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
+ 730:Src/main.c    ****   {
+ 731:Src/main.c    ****     Error_Handler();
+ 732:Src/main.c    ****   }
+ 733:Src/main.c    ****   /* USER CODE BEGIN ADC3_Init 2 */
+ARM GAS  /tmp/ccdsDELB.s 			page 52
+
+
+ 734:Src/main.c    **** 
+ 735:Src/main.c    ****   /* USER CODE END ADC3_Init 2 */
+ 736:Src/main.c    **** 
+ 737:Src/main.c    **** }
+ 738:Src/main.c    **** 
+ 739:Src/main.c    **** /**
+ 740:Src/main.c    ****   * @brief SDMMC1 Initialization Function
+ 741:Src/main.c    ****   * @param None
+ 742:Src/main.c    ****   * @retval None
+ 743:Src/main.c    ****   */
+ 744:Src/main.c    **** static void MX_SDMMC1_SD_Init(void)
+ 745:Src/main.c    **** {
+  93              		.loc 2 745 1 is_stmt 1 view -0
+  94              		.cfi_startproc
+  95              		@ args = 0, pretend = 0, frame = 0
+  96              		@ frame_needed = 0, uses_anonymous_args = 0
+  97              		@ link register save eliminated.
+ 746:Src/main.c    **** 
+ 747:Src/main.c    ****   /* USER CODE BEGIN SDMMC1_Init 0 */
+ 748:Src/main.c    **** 
+ 749:Src/main.c    ****   /* USER CODE END SDMMC1_Init 0 */
+ 750:Src/main.c    **** 
+ 751:Src/main.c    ****   /* USER CODE BEGIN SDMMC1_Init 1 */
+ 752:Src/main.c    **** 
+ 753:Src/main.c    ****   /* USER CODE END SDMMC1_Init 1 */
+ 754:Src/main.c    ****   hsd1.Instance = SDMMC1;
+  98              		.loc 2 754 3 view .LVU21
+  99              		.loc 2 754 17 is_stmt 0 view .LVU22
+ 100 0000 064B     		ldr	r3, .L5
+ 101 0002 074A     		ldr	r2, .L5+4
+ 102 0004 1A60     		str	r2, [r3]
+ 755:Src/main.c    ****   hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
+ 103              		.loc 2 755 3 is_stmt 1 view .LVU23
+ 104              		.loc 2 755 23 is_stmt 0 view .LVU24
+ 105 0006 0022     		movs	r2, #0
+ 106 0008 5A60     		str	r2, [r3, #4]
+ 756:Src/main.c    ****   hsd1.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE;
+ 107              		.loc 2 756 3 is_stmt 1 view .LVU25
+ 108              		.loc 2 756 25 is_stmt 0 view .LVU26
+ 109 000a 9A60     		str	r2, [r3, #8]
+ 757:Src/main.c    ****   hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+ 110              		.loc 2 757 3 is_stmt 1 view .LVU27
+ 111              		.loc 2 757 28 is_stmt 0 view .LVU28
+ 112 000c DA60     		str	r2, [r3, #12]
+ 758:Src/main.c    ****   hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B;
+ 113              		.loc 2 758 3 is_stmt 1 view .LVU29
+ 114              		.loc 2 758 21 is_stmt 0 view .LVU30
+ 115 000e 4FF40061 		mov	r1, #2048
+ 116 0012 1961     		str	r1, [r3, #16]
+ 759:Src/main.c    ****   hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+ 117              		.loc 2 759 3 is_stmt 1 view .LVU31
+ 118              		.loc 2 759 33 is_stmt 0 view .LVU32
+ 119 0014 5A61     		str	r2, [r3, #20]
+ 760:Src/main.c    ****   hsd1.Init.ClockDiv = 20;
+ 120              		.loc 2 760 3 is_stmt 1 view .LVU33
+ 121              		.loc 2 760 22 is_stmt 0 view .LVU34
+ 122 0016 1422     		movs	r2, #20
+ARM GAS  /tmp/ccdsDELB.s 			page 53
+
+
+ 123 0018 9A61     		str	r2, [r3, #24]
+ 761:Src/main.c    ****   /* USER CODE BEGIN SDMMC1_Init 2 */
+ 762:Src/main.c    **** 
+ 763:Src/main.c    ****   /* USER CODE END SDMMC1_Init 2 */
+ 764:Src/main.c    **** 
+ 765:Src/main.c    **** }
+ 124              		.loc 2 765 1 view .LVU35
+ 125 001a 7047     		bx	lr
+ 126              	.L6:
+ 127              		.align	2
+ 128              	.L5:
+ 129 001c 00000000 		.word	.LANCHOR0
+ 130 0020 002C0140 		.word	1073818624
+ 131              		.cfi_endproc
+ 132              	.LFE1190:
+ 134              		.section	.text.MX_DMA_Init,"ax",%progbits
+ 135              		.align	1
+ 136              		.syntax unified
+ 137              		.thumb
+ 138              		.thumb_func
+ 139              		.fpu fpv5-d16
+ 141              	MX_DMA_Init:
+ 142              	.LFB1201:
+ 766:Src/main.c    **** 
+ 767:Src/main.c    **** /**
+ 768:Src/main.c    ****   * @brief SPI2 Initialization Function
+ 769:Src/main.c    ****   * @param None
+ 770:Src/main.c    ****   * @retval None
+ 771:Src/main.c    ****   */
+ 772:Src/main.c    **** static void MX_SPI2_Init(void)
+ 773:Src/main.c    **** {
+ 774:Src/main.c    **** 
+ 775:Src/main.c    ****   /* USER CODE BEGIN SPI2_Init 0 */
+ 776:Src/main.c    **** 
+ 777:Src/main.c    ****   /* USER CODE END SPI2_Init 0 */
+ 778:Src/main.c    **** 
+ 779:Src/main.c    ****   LL_SPI_InitTypeDef SPI_InitStruct = {0};
+ 780:Src/main.c    **** 
+ 781:Src/main.c    ****   LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 782:Src/main.c    **** 
+ 783:Src/main.c    ****   /* Peripheral clock enable */
+ 784:Src/main.c    ****   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2);
+ 785:Src/main.c    **** 
+ 786:Src/main.c    ****   LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB);
+ 787:Src/main.c    ****   /**SPI2 GPIO Configuration
+ 788:Src/main.c    ****   PB13   ------> SPI2_SCK
+ 789:Src/main.c    ****   PB15   ------> SPI2_MOSI
+ 790:Src/main.c    ****   */
+ 791:Src/main.c    ****   GPIO_InitStruct.Pin = LL_GPIO_PIN_13;
+ 792:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 793:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 794:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 795:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 796:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 797:Src/main.c    ****   LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 798:Src/main.c    **** 
+ 799:Src/main.c    ****   GPIO_InitStruct.Pin = LL_GPIO_PIN_15;
+ARM GAS  /tmp/ccdsDELB.s 			page 54
+
+
+ 800:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 801:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 802:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 803:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 804:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 805:Src/main.c    ****   LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 806:Src/main.c    **** 
+ 807:Src/main.c    ****   /* USER CODE BEGIN SPI2_Init 1 */
+ 808:Src/main.c    **** 
+ 809:Src/main.c    ****   /* USER CODE END SPI2_Init 1 */
+ 810:Src/main.c    ****   /* SPI2 parameter configuration*/
+ 811:Src/main.c    ****   SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX;
+ 812:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ 813:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+ 814:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+ 815:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE;
+ 816:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ 817:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8;
+ 818:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ 819:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ 820:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+ 821:Src/main.c    ****   LL_SPI_Init(SPI2, &SPI_InitStruct);
+ 822:Src/main.c    ****   LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA);
+ 823:Src/main.c    ****   LL_SPI_DisableNSSPulseMgt(SPI2);
+ 824:Src/main.c    ****   /* USER CODE BEGIN SPI2_Init 2 */
+ 825:Src/main.c    **** 
+ 826:Src/main.c    ****   /* USER CODE END SPI2_Init 2 */
+ 827:Src/main.c    **** 
+ 828:Src/main.c    **** }
+ 829:Src/main.c    **** 
+ 830:Src/main.c    **** /**
+ 831:Src/main.c    ****   * @brief SPI4 Initialization Function
+ 832:Src/main.c    ****   * @param None
+ 833:Src/main.c    ****   * @retval None
+ 834:Src/main.c    ****   */
+ 835:Src/main.c    **** static void MX_SPI4_Init(void)
+ 836:Src/main.c    **** {
+ 837:Src/main.c    **** 
+ 838:Src/main.c    ****   /* USER CODE BEGIN SPI4_Init 0 */
+ 839:Src/main.c    **** 
+ 840:Src/main.c    ****   /* USER CODE END SPI4_Init 0 */
+ 841:Src/main.c    **** 
+ 842:Src/main.c    ****   LL_SPI_InitTypeDef SPI_InitStruct = {0};
+ 843:Src/main.c    **** 
+ 844:Src/main.c    ****   LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 845:Src/main.c    **** 
+ 846:Src/main.c    ****   /* Peripheral clock enable */
+ 847:Src/main.c    ****   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI4);
+ 848:Src/main.c    **** 
+ 849:Src/main.c    ****   LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOE);
+ 850:Src/main.c    ****   /**SPI4 GPIO Configuration
+ 851:Src/main.c    ****   PE12   ------> SPI4_SCK
+ 852:Src/main.c    ****   PE13   ------> SPI4_MISO
+ 853:Src/main.c    ****   */
+ 854:Src/main.c    ****   GPIO_InitStruct.Pin = LL_GPIO_PIN_12;
+ 855:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 856:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ARM GAS  /tmp/ccdsDELB.s 			page 55
+
+
+ 857:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 858:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 859:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 860:Src/main.c    ****   LL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 861:Src/main.c    **** 
+ 862:Src/main.c    ****   GPIO_InitStruct.Pin = LL_GPIO_PIN_13;
+ 863:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 864:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 865:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 866:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 867:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 868:Src/main.c    ****   LL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 869:Src/main.c    **** 
+ 870:Src/main.c    ****   /* USER CODE BEGIN SPI4_Init 1 */
+ 871:Src/main.c    **** 
+ 872:Src/main.c    ****   /* USER CODE END SPI4_Init 1 */
+ 873:Src/main.c    ****   /* SPI4 parameter configuration*/
+ 874:Src/main.c    ****   SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX;
+ 875:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ 876:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+ 877:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+ 878:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
+ 879:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ 880:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+ 881:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ 882:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ 883:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+ 884:Src/main.c    ****   LL_SPI_Init(SPI4, &SPI_InitStruct);
+ 885:Src/main.c    ****   LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA);
+ 886:Src/main.c    ****   LL_SPI_DisableNSSPulseMgt(SPI4);
+ 887:Src/main.c    ****   /* USER CODE BEGIN SPI4_Init 2 */
+ 888:Src/main.c    **** 
+ 889:Src/main.c    ****   /* USER CODE END SPI4_Init 2 */
+ 890:Src/main.c    **** 
+ 891:Src/main.c    **** }
+ 892:Src/main.c    **** 
+ 893:Src/main.c    **** /**
+ 894:Src/main.c    ****   * @brief SPI5 Initialization Function
+ 895:Src/main.c    ****   * @param None
+ 896:Src/main.c    ****   * @retval None
+ 897:Src/main.c    ****   */
+ 898:Src/main.c    **** static void MX_SPI5_Init(void)
+ 899:Src/main.c    **** {
+ 900:Src/main.c    **** 
+ 901:Src/main.c    ****   /* USER CODE BEGIN SPI5_Init 0 */
+ 902:Src/main.c    **** 
+ 903:Src/main.c    ****   /* USER CODE END SPI5_Init 0 */
+ 904:Src/main.c    **** 
+ 905:Src/main.c    ****   LL_SPI_InitTypeDef SPI_InitStruct = {0};
+ 906:Src/main.c    **** 
+ 907:Src/main.c    ****   LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 908:Src/main.c    **** 
+ 909:Src/main.c    ****   /* Peripheral clock enable */
+ 910:Src/main.c    ****   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI5);
+ 911:Src/main.c    **** 
+ 912:Src/main.c    ****   LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF);
+ 913:Src/main.c    ****   /**SPI5 GPIO Configuration
+ARM GAS  /tmp/ccdsDELB.s 			page 56
+
+
+ 914:Src/main.c    ****   PF7   ------> SPI5_SCK
+ 915:Src/main.c    ****   PF8   ------> SPI5_MISO
+ 916:Src/main.c    ****   */
+ 917:Src/main.c    ****   GPIO_InitStruct.Pin = LL_GPIO_PIN_7;
+ 918:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 919:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 920:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 921:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 922:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 923:Src/main.c    ****   LL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 924:Src/main.c    **** 
+ 925:Src/main.c    ****   GPIO_InitStruct.Pin = LL_GPIO_PIN_8;
+ 926:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 927:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 928:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 929:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 930:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 931:Src/main.c    ****   LL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 932:Src/main.c    **** 
+ 933:Src/main.c    ****   /* USER CODE BEGIN SPI5_Init 1 */
+ 934:Src/main.c    **** 
+ 935:Src/main.c    ****   /* USER CODE END SPI5_Init 1 */
+ 936:Src/main.c    ****   /* SPI5 parameter configuration*/
+ 937:Src/main.c    ****   SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX;
+ 938:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ 939:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+ 940:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+ 941:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
+ 942:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ 943:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+ 944:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ 945:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ 946:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+ 947:Src/main.c    ****   LL_SPI_Init(SPI5, &SPI_InitStruct);
+ 948:Src/main.c    ****   LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA);
+ 949:Src/main.c    ****   LL_SPI_DisableNSSPulseMgt(SPI5);
+ 950:Src/main.c    ****   /* USER CODE BEGIN SPI5_Init 2 */
+ 951:Src/main.c    **** 
+ 952:Src/main.c    ****   /* USER CODE END SPI5_Init 2 */
+ 953:Src/main.c    **** 
+ 954:Src/main.c    **** }
+ 955:Src/main.c    **** 
+ 956:Src/main.c    **** /**
+ 957:Src/main.c    ****   * @brief SPI6 Initialization Function
+ 958:Src/main.c    ****   * @param None
+ 959:Src/main.c    ****   * @retval None
+ 960:Src/main.c    ****   */
+ 961:Src/main.c    **** static void MX_SPI6_Init(void)
+ 962:Src/main.c    **** {
+ 963:Src/main.c    **** 
+ 964:Src/main.c    ****   /* USER CODE BEGIN SPI6_Init 0 */
+ 965:Src/main.c    **** 
+ 966:Src/main.c    ****   /* USER CODE END SPI6_Init 0 */
+ 967:Src/main.c    **** 
+ 968:Src/main.c    ****   LL_SPI_InitTypeDef SPI_InitStruct = {0};
+ 969:Src/main.c    **** 
+ 970:Src/main.c    ****   LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+ARM GAS  /tmp/ccdsDELB.s 			page 57
+
+
+ 971:Src/main.c    **** 
+ 972:Src/main.c    ****   /* Peripheral clock enable */
+ 973:Src/main.c    ****   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI6);
+ 974:Src/main.c    **** 
+ 975:Src/main.c    ****   LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);
+ 976:Src/main.c    ****   /**SPI6 GPIO Configuration
+ 977:Src/main.c    ****   PA5   ------> SPI6_SCK
+ 978:Src/main.c    ****   PA7   ------> SPI6_MOSI
+ 979:Src/main.c    ****   */
+ 980:Src/main.c    ****   GPIO_InitStruct.Pin = LL_GPIO_PIN_5;
+ 981:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 982:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 983:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 984:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 985:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_8;
+ 986:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 987:Src/main.c    **** 
+ 988:Src/main.c    ****   GPIO_InitStruct.Pin = LL_GPIO_PIN_7;
+ 989:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 990:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 991:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 992:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 993:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_8;
+ 994:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 995:Src/main.c    **** 
+ 996:Src/main.c    ****   /* USER CODE BEGIN SPI6_Init 1 */
+ 997:Src/main.c    **** 
+ 998:Src/main.c    ****   /* USER CODE END SPI6_Init 1 */
+ 999:Src/main.c    ****   /* SPI6 parameter configuration*/
+1000:Src/main.c    ****   SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX;
+1001:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+1002:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+1003:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+1004:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE;
+1005:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+1006:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+1007:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+1008:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+1009:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+1010:Src/main.c    ****   LL_SPI_Init(SPI6, &SPI_InitStruct);
+1011:Src/main.c    ****   LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA);
+1012:Src/main.c    ****   LL_SPI_DisableNSSPulseMgt(SPI6);
+1013:Src/main.c    ****   /* USER CODE BEGIN SPI6_Init 2 */
+1014:Src/main.c    **** 
+1015:Src/main.c    ****   /* USER CODE END SPI6_Init 2 */
+1016:Src/main.c    **** 
+1017:Src/main.c    **** }
+1018:Src/main.c    **** 
+1019:Src/main.c    **** /**
+1020:Src/main.c    ****   * @brief TIM2 Initialization Function
+1021:Src/main.c    ****   * @param None
+1022:Src/main.c    ****   * @retval None
+1023:Src/main.c    ****   */
+1024:Src/main.c    **** static void MX_TIM2_Init(void)
+1025:Src/main.c    **** {
+1026:Src/main.c    **** 
+1027:Src/main.c    ****   /* USER CODE BEGIN TIM2_Init 0 */
+ARM GAS  /tmp/ccdsDELB.s 			page 58
+
+
+1028:Src/main.c    **** 
+1029:Src/main.c    ****   /* USER CODE END TIM2_Init 0 */
+1030:Src/main.c    **** 
+1031:Src/main.c    ****   LL_TIM_InitTypeDef TIM_InitStruct = {0};
+1032:Src/main.c    **** 
+1033:Src/main.c    ****   /* Peripheral clock enable */
+1034:Src/main.c    ****   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
+1035:Src/main.c    **** 
+1036:Src/main.c    ****   /* TIM2 interrupt Init */
+1037:Src/main.c    ****   NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+1038:Src/main.c    ****   NVIC_EnableIRQ(TIM2_IRQn);
+1039:Src/main.c    **** 
+1040:Src/main.c    ****   /* USER CODE BEGIN TIM2_Init 1 */
+1041:Src/main.c    **** 
+1042:Src/main.c    ****   /* USER CODE END TIM2_Init 1 */
+1043:Src/main.c    ****   TIM_InitStruct.Prescaler = 1000;
+1044:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+1045:Src/main.c    ****   TIM_InitStruct.Autoreload = 840000;
+1046:Src/main.c    ****   TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+1047:Src/main.c    ****   LL_TIM_Init(TIM2, &TIM_InitStruct);
+1048:Src/main.c    ****   LL_TIM_DisableARRPreload(TIM2);
+1049:Src/main.c    ****   LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
+1050:Src/main.c    ****   LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET);
+1051:Src/main.c    ****   LL_TIM_DisableMasterSlaveMode(TIM2);
+1052:Src/main.c    ****   /* USER CODE BEGIN TIM2_Init 2 */
+1053:Src/main.c    **** 
+1054:Src/main.c    ****   /* USER CODE END TIM2_Init 2 */
+1055:Src/main.c    **** 
+1056:Src/main.c    **** }
+1057:Src/main.c    **** 
+1058:Src/main.c    **** /**
+1059:Src/main.c    ****   * @brief TIM5 Initialization Function
+1060:Src/main.c    ****   * @param None
+1061:Src/main.c    ****   * @retval None
+1062:Src/main.c    ****   */
+1063:Src/main.c    **** static void MX_TIM5_Init(void)
+1064:Src/main.c    **** {
+1065:Src/main.c    **** 
+1066:Src/main.c    ****   /* USER CODE BEGIN TIM5_Init 0 */
+1067:Src/main.c    **** 
+1068:Src/main.c    ****   /* USER CODE END TIM5_Init 0 */
+1069:Src/main.c    **** 
+1070:Src/main.c    ****   LL_TIM_InitTypeDef TIM_InitStruct = {0};
+1071:Src/main.c    **** 
+1072:Src/main.c    ****   /* Peripheral clock enable */
+1073:Src/main.c    ****   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5);
+1074:Src/main.c    **** 
+1075:Src/main.c    ****   /* TIM5 interrupt Init */
+1076:Src/main.c    ****   NVIC_SetPriority(TIM5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+1077:Src/main.c    ****   NVIC_EnableIRQ(TIM5_IRQn);
+1078:Src/main.c    **** 
+1079:Src/main.c    ****   /* USER CODE BEGIN TIM5_Init 1 */
+1080:Src/main.c    **** 
+1081:Src/main.c    ****   /* USER CODE END TIM5_Init 1 */
+1082:Src/main.c    ****   TIM_InitStruct.Prescaler = 10000;
+1083:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+1084:Src/main.c    ****   TIM_InitStruct.Autoreload = 560;
+ARM GAS  /tmp/ccdsDELB.s 			page 59
+
+
+1085:Src/main.c    ****   TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+1086:Src/main.c    ****   LL_TIM_Init(TIM5, &TIM_InitStruct);
+1087:Src/main.c    ****   LL_TIM_DisableARRPreload(TIM5);
+1088:Src/main.c    ****   LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL);
+1089:Src/main.c    ****   LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET);
+1090:Src/main.c    ****   LL_TIM_DisableMasterSlaveMode(TIM5);
+1091:Src/main.c    ****   /* USER CODE BEGIN TIM5_Init 2 */
+1092:Src/main.c    **** 
+1093:Src/main.c    ****   /* USER CODE END TIM5_Init 2 */
+1094:Src/main.c    **** 
+1095:Src/main.c    **** }
+1096:Src/main.c    **** 
+1097:Src/main.c    **** /**
+1098:Src/main.c    ****   * @brief TIM6 Initialization Function
+1099:Src/main.c    ****   * @param None
+1100:Src/main.c    ****   * @retval None
+1101:Src/main.c    ****   */
+1102:Src/main.c    **** static void MX_TIM6_Init(void)
+1103:Src/main.c    **** {
+1104:Src/main.c    **** 
+1105:Src/main.c    ****   /* USER CODE BEGIN TIM6_Init 0 */
+1106:Src/main.c    **** 
+1107:Src/main.c    ****   /* USER CODE END TIM6_Init 0 */
+1108:Src/main.c    **** 
+1109:Src/main.c    ****   LL_TIM_InitTypeDef TIM_InitStruct = {0};
+1110:Src/main.c    **** 
+1111:Src/main.c    ****   /* Peripheral clock enable */
+1112:Src/main.c    ****   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6);
+1113:Src/main.c    **** 
+1114:Src/main.c    ****   /* TIM6 interrupt Init */
+1115:Src/main.c    ****   NVIC_SetPriority(TIM6_DAC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+1116:Src/main.c    ****   NVIC_EnableIRQ(TIM6_DAC_IRQn);
+1117:Src/main.c    **** 
+1118:Src/main.c    ****   /* USER CODE BEGIN TIM6_Init 1 */
+1119:Src/main.c    **** 
+1120:Src/main.c    ****   /* USER CODE END TIM6_Init 1 */
+1121:Src/main.c    ****   TIM_InitStruct.Prescaler = 45999;
+1122:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+1123:Src/main.c    ****   TIM_InitStruct.Autoreload = 19;
+1124:Src/main.c    ****   LL_TIM_Init(TIM6, &TIM_InitStruct);
+1125:Src/main.c    ****   LL_TIM_DisableARRPreload(TIM6);
+1126:Src/main.c    ****   LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE);
+1127:Src/main.c    ****   LL_TIM_DisableMasterSlaveMode(TIM6);
+1128:Src/main.c    ****   /* USER CODE BEGIN TIM6_Init 2 */
+1129:Src/main.c    **** 
+1130:Src/main.c    ****   /* USER CODE END TIM6_Init 2 */
+1131:Src/main.c    **** 
+1132:Src/main.c    **** }
+1133:Src/main.c    **** 
+1134:Src/main.c    **** /**
+1135:Src/main.c    ****   * @brief TIM7 Initialization Function
+1136:Src/main.c    ****   * @param None
+1137:Src/main.c    ****   * @retval None
+1138:Src/main.c    ****   */
+1139:Src/main.c    **** static void MX_TIM7_Init(void)
+1140:Src/main.c    **** {
+1141:Src/main.c    **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 60
+
+
+1142:Src/main.c    ****   /* USER CODE BEGIN TIM7_Init 0 */
+1143:Src/main.c    **** 
+1144:Src/main.c    ****   /* USER CODE END TIM7_Init 0 */
+1145:Src/main.c    **** 
+1146:Src/main.c    ****   LL_TIM_InitTypeDef TIM_InitStruct = {0};
+1147:Src/main.c    **** 
+1148:Src/main.c    ****   /* Peripheral clock enable */
+1149:Src/main.c    ****   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7);
+1150:Src/main.c    **** 
+1151:Src/main.c    ****   /* TIM7 interrupt Init */
+1152:Src/main.c    ****   NVIC_SetPriority(TIM7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+1153:Src/main.c    ****   NVIC_EnableIRQ(TIM7_IRQn);
+1154:Src/main.c    **** 
+1155:Src/main.c    ****   /* USER CODE BEGIN TIM7_Init 1 */
+1156:Src/main.c    **** 
+1157:Src/main.c    ****   /* USER CODE END TIM7_Init 1 */
+1158:Src/main.c    ****   TIM_InitStruct.Prescaler = 919;
+1159:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+1160:Src/main.c    ****   TIM_InitStruct.Autoreload = 99;
+1161:Src/main.c    ****   LL_TIM_Init(TIM7, &TIM_InitStruct);
+1162:Src/main.c    ****   LL_TIM_DisableARRPreload(TIM7);
+1163:Src/main.c    ****   LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE);
+1164:Src/main.c    ****   LL_TIM_DisableMasterSlaveMode(TIM7);
+1165:Src/main.c    ****   /* USER CODE BEGIN TIM7_Init 2 */
+1166:Src/main.c    **** 
+1167:Src/main.c    ****   /* USER CODE END TIM7_Init 2 */
+1168:Src/main.c    **** 
+1169:Src/main.c    **** }
+1170:Src/main.c    **** 
+1171:Src/main.c    **** /**
+1172:Src/main.c    ****   * @brief TIM10 Initialization Function
+1173:Src/main.c    ****   * @param None
+1174:Src/main.c    ****   * @retval None
+1175:Src/main.c    ****   */
+1176:Src/main.c    **** static void MX_TIM10_Init(void)
+1177:Src/main.c    **** {
+1178:Src/main.c    **** 
+1179:Src/main.c    ****   /* USER CODE BEGIN TIM10_Init 0 */
+1180:Src/main.c    **** 
+1181:Src/main.c    ****   /* USER CODE END TIM10_Init 0 */
+1182:Src/main.c    **** 
+1183:Src/main.c    ****   /* USER CODE BEGIN TIM10_Init 1 */
+1184:Src/main.c    **** 
+1185:Src/main.c    ****   /* USER CODE END TIM10_Init 1 */
+1186:Src/main.c    ****   htim10.Instance = TIM10;
+1187:Src/main.c    ****   htim10.Init.Prescaler = 183;
+1188:Src/main.c    ****   htim10.Init.CounterMode = TIM_COUNTERMODE_UP;
+1189:Src/main.c    ****   htim10.Init.Period = 9;
+1190:Src/main.c    ****   htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+1191:Src/main.c    ****   htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+1192:Src/main.c    ****   if (HAL_TIM_Base_Init(&htim10) != HAL_OK)
+1193:Src/main.c    ****   {
+1194:Src/main.c    ****     Error_Handler();
+1195:Src/main.c    ****   }
+1196:Src/main.c    ****   /* USER CODE BEGIN TIM10_Init 2 */
+1197:Src/main.c    **** 
+1198:Src/main.c    ****   /* USER CODE END TIM10_Init 2 */
+ARM GAS  /tmp/ccdsDELB.s 			page 61
+
+
+1199:Src/main.c    **** 
+1200:Src/main.c    **** }
+1201:Src/main.c    **** 
+1202:Src/main.c    **** /**
+1203:Src/main.c    ****   * @brief USART1 Initialization Function
+1204:Src/main.c    ****   * @param None
+1205:Src/main.c    ****   * @retval None
+1206:Src/main.c    ****   */
+1207:Src/main.c    **** static void MX_USART1_UART_Init(void)
+1208:Src/main.c    **** {
+1209:Src/main.c    **** 
+1210:Src/main.c    ****   /* USER CODE BEGIN USART1_Init 0 */
+1211:Src/main.c    **** 
+1212:Src/main.c    ****   /* USER CODE END USART1_Init 0 */
+1213:Src/main.c    **** 
+1214:Src/main.c    ****   LL_USART_InitTypeDef USART_InitStruct = {0};
+1215:Src/main.c    **** 
+1216:Src/main.c    ****   LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+1217:Src/main.c    ****   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+1218:Src/main.c    **** 
+1219:Src/main.c    ****   /** Initializes the peripherals clock
+1220:Src/main.c    ****   */
+1221:Src/main.c    ****   PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+1222:Src/main.c    ****   PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+1223:Src/main.c    ****   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+1224:Src/main.c    ****   {
+1225:Src/main.c    ****     Error_Handler();
+1226:Src/main.c    ****   }
+1227:Src/main.c    **** 
+1228:Src/main.c    ****   /* Peripheral clock enable */
+1229:Src/main.c    ****   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
+1230:Src/main.c    **** 
+1231:Src/main.c    ****   LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);
+1232:Src/main.c    ****   /**USART1 GPIO Configuration
+1233:Src/main.c    ****   PA9   ------> USART1_TX
+1234:Src/main.c    ****   PA10   ------> USART1_RX
+1235:Src/main.c    ****   */
+1236:Src/main.c    ****   GPIO_InitStruct.Pin = LL_GPIO_PIN_9;
+1237:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+1238:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+1239:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+1240:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+1241:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+1242:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+1243:Src/main.c    **** 
+1244:Src/main.c    ****   GPIO_InitStruct.Pin = LL_GPIO_PIN_10;
+1245:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+1246:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+1247:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+1248:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+1249:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+1250:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+1251:Src/main.c    **** 
+1252:Src/main.c    ****   /* USART1 DMA Init */
+1253:Src/main.c    **** 
+1254:Src/main.c    ****   /* USART1_TX Init */
+1255:Src/main.c    ****   LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_7, LL_DMA_CHANNEL_4);
+ARM GAS  /tmp/ccdsDELB.s 			page 62
+
+
+1256:Src/main.c    **** 
+1257:Src/main.c    ****   LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_7, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+1258:Src/main.c    **** 
+1259:Src/main.c    ****   LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_7, LL_DMA_PRIORITY_VERYHIGH);
+1260:Src/main.c    **** 
+1261:Src/main.c    ****   LL_DMA_SetMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MODE_NORMAL);
+1262:Src/main.c    **** 
+1263:Src/main.c    ****   LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_PERIPH_NOINCREMENT);
+1264:Src/main.c    **** 
+1265:Src/main.c    ****   LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MEMORY_INCREMENT);
+1266:Src/main.c    **** 
+1267:Src/main.c    ****   LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_7, LL_DMA_PDATAALIGN_BYTE);
+1268:Src/main.c    **** 
+1269:Src/main.c    ****   LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_7, LL_DMA_MDATAALIGN_BYTE);
+1270:Src/main.c    **** 
+1271:Src/main.c    ****   LL_DMA_DisableFifoMode(DMA2, LL_DMA_STREAM_7);
+1272:Src/main.c    **** 
+1273:Src/main.c    ****   /* USART1 interrupt Init */
+1274:Src/main.c    ****   NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+1275:Src/main.c    ****   NVIC_EnableIRQ(USART1_IRQn);
+1276:Src/main.c    **** 
+1277:Src/main.c    ****   /* USER CODE BEGIN USART1_Init 1 */
+1278:Src/main.c    **** 
+1279:Src/main.c    ****   /* USER CODE END USART1_Init 1 */
+1280:Src/main.c    ****   USART_InitStruct.BaudRate = 115200;
+1281:Src/main.c    ****   USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
+1282:Src/main.c    ****   USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
+1283:Src/main.c    ****   USART_InitStruct.Parity = LL_USART_PARITY_NONE;
+1284:Src/main.c    ****   USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
+1285:Src/main.c    ****   USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+1286:Src/main.c    ****   USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
+1287:Src/main.c    ****   LL_USART_Init(USART1, &USART_InitStruct);
+1288:Src/main.c    ****   LL_USART_ConfigAsyncMode(USART1);
+1289:Src/main.c    ****   LL_USART_Enable(USART1);
+1290:Src/main.c    ****   /* USER CODE BEGIN USART1_Init 2 */
+1291:Src/main.c    **** 
+1292:Src/main.c    ****   /* USER CODE END USART1_Init 2 */
+1293:Src/main.c    **** 
+1294:Src/main.c    **** }
+1295:Src/main.c    **** 
+1296:Src/main.c    **** /**
+1297:Src/main.c    ****   * Enable DMA controller clock
+1298:Src/main.c    ****   */
+1299:Src/main.c    **** static void MX_DMA_Init(void)
+1300:Src/main.c    **** {
+ 143              		.loc 2 1300 1 is_stmt 1 view -0
+ 144              		.cfi_startproc
+ 145              		@ args = 0, pretend = 0, frame = 8
+ 146              		@ frame_needed = 0, uses_anonymous_args = 0
+ 147 0000 00B5     		push	{lr}
+ 148              	.LCFI0:
+ 149              		.cfi_def_cfa_offset 4
+ 150              		.cfi_offset 14, -4
+ 151 0002 83B0     		sub	sp, sp, #12
+ 152              	.LCFI1:
+ 153              		.cfi_def_cfa_offset 16
+1301:Src/main.c    **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 63
+
+
+1302:Src/main.c    ****   /* Init with LL driver */
+1303:Src/main.c    ****   /* DMA controller clock enable */
+1304:Src/main.c    ****   LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2);
+ 154              		.loc 2 1304 3 view .LVU37
+ 155              	.LVL8:
+ 156              	.LBB293:
+ 157              	.LBI293:
+ 158              		.file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @file    stm32f7xx_ll_bus.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief   Header file of BUS LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @verbatim
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****                       ##### RCC Limitations #####
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ==============================================================================
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       A delay between an RCC peripheral clock enable and the effective peripheral 
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       enabling should be taken into account in order to manage the peripheral read/write 
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       from/to registers.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (+) This delay depends on the peripheral mapping.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****         (++) AHB & APB peripherals, 1 dummy read is necessary
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       Workarounds:
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @endverbatim
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @attention
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * Copyright (c) 2017 STMicroelectronics.
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * All rights reserved.
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * This software is licensed under terms that can be found in the LICENSE file in
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * the root directory of this software component.
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" {
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h"
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 64
+
+
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC)
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ)
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK)
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM         RCC_AHB1ENR_DTCMRAMEN
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D)
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH)
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI             RCC_AHB1LPENR_AXILPEN
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ARM GAS  /tmp/ccdsDELB.s 			page 65
+
+
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI)
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG)
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG           RCC_AHB2ENR_JPEGEN
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) 
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES)
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH)
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX)
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */
+ARM GAS  /tmp/ccdsDELB.s 			page 66
+
+
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4)
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4           RCC_APB1ENR_I2C4EN
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2)
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3)
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC)
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN)
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCEN
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1       RCC_APB2ENR_SDMMC1EN
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2)
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2       RCC_APB2ENR_SDMMC2EN
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6)
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN
+ARM GAS  /tmp/ccdsDELB.s 			page 67
+
+
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC)
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI)
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0)
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS)
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO         RCC_APB2ENR_MDIOEN
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC)
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC      RCC_APB2ENR_OTGPHYCEN
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB1 peripherals clock.
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\n
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\n
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\n
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\n
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\n
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\n
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\n
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\n
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\n
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\n
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\n
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\n
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\n
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\n
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\n
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\n
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\n
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\n
+ARM GAS  /tmp/ccdsDELB.s 			page 68
+
+
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\n
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\n
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+ 159              		.loc 3 309 22 view .LVU38
+ 160              	.LBB294:
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 161              		.loc 3 311 3 view .LVU39
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1ENR, Periphs);
+ 162              		.loc 3 312 3 view .LVU40
+ 163 0004 0D4B     		ldr	r3, .L9
+ 164 0006 1A6B     		ldr	r2, [r3, #48]
+ 165 0008 42F48002 		orr	r2, r2, #4194304
+ 166 000c 1A63     		str	r2, [r3, #48]
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+ 167              		.loc 3 314 3 view .LVU41
+ 168              		.loc 3 314 12 is_stmt 0 view .LVU42
+ 169 000e 1B6B     		ldr	r3, [r3, #48]
+ 170 0010 03F48003 		and	r3, r3, #4194304
+ 171              		.loc 3 314 10 view .LVU43
+ 172 0014 0193     		str	r3, [sp, #4]
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 173              		.loc 3 315 3 is_stmt 1 view .LVU44
+ 174 0016 019B     		ldr	r3, [sp, #4]
+ 175              	.LVL9:
+ 176              		.loc 3 315 3 is_stmt 0 view .LVU45
+ 177              	.LBE294:
+ARM GAS  /tmp/ccdsDELB.s 			page 69
+
+
+ 178              	.LBE293:
+1305:Src/main.c    **** 
+1306:Src/main.c    ****   /* DMA interrupt init */
+1307:Src/main.c    ****   /* DMA2_Stream7_IRQn interrupt configuration */
+1308:Src/main.c    ****   NVIC_SetPriority(DMA2_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+ 179              		.loc 2 1308 3 is_stmt 1 view .LVU46
+ 180              	.LBB295:
+ 181              	.LBI295:
+1884:Drivers/CMSIS/Include/core_cm7.h **** {
+ 182              		.loc 1 1884 26 view .LVU47
+ 183              	.LBB296:
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 184              		.loc 1 1886 3 view .LVU48
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 185              		.loc 1 1886 26 is_stmt 0 view .LVU49
+ 186 0018 094B     		ldr	r3, .L9+4
+ 187 001a D868     		ldr	r0, [r3, #12]
+ 188              	.LBE296:
+ 189              	.LBE295:
+ 190              		.loc 2 1308 3 view .LVU50
+ 191 001c 0022     		movs	r2, #0
+ 192 001e 1146     		mov	r1, r2
+ 193 0020 C0F30220 		ubfx	r0, r0, #8, #3
+ 194 0024 FFF7FEFF 		bl	NVIC_EncodePriority
+ 195              	.LVL10:
+ 196              	.LBB297:
+ 197              	.LBI297:
+2024:Drivers/CMSIS/Include/core_cm7.h **** {
+ 198              		.loc 1 2024 22 is_stmt 1 view .LVU51
+ 199              	.LBB298:
+2026:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 200              		.loc 1 2026 3 view .LVU52
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 201              		.loc 1 2028 5 view .LVU53
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 202              		.loc 1 2028 49 is_stmt 0 view .LVU54
+ 203 0028 0001     		lsls	r0, r0, #4
+ 204              	.LVL11:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 205              		.loc 1 2028 49 view .LVU55
+ 206 002a C0B2     		uxtb	r0, r0
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 207              		.loc 1 2028 47 view .LVU56
+ 208 002c 054B     		ldr	r3, .L9+8
+ 209 002e 83F84603 		strb	r0, [r3, #838]
+ 210              	.LVL12:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 211              		.loc 1 2028 47 view .LVU57
+ 212              	.LBE298:
+ 213              	.LBE297:
+1309:Src/main.c    ****   NVIC_EnableIRQ(DMA2_Stream7_IRQn);
+ 214              		.loc 2 1309 3 is_stmt 1 view .LVU58
+ 215              	.LBB299:
+ 216              	.LBI299:
+1896:Drivers/CMSIS/Include/core_cm7.h **** {
+ 217              		.loc 1 1896 22 view .LVU59
+ 218              	.LBB300:
+ARM GAS  /tmp/ccdsDELB.s 			page 70
+
+
+1898:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 219              		.loc 1 1898 3 view .LVU60
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 220              		.loc 1 1900 5 view .LVU61
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 221              		.loc 1 1900 43 is_stmt 0 view .LVU62
+ 222 0032 4022     		movs	r2, #64
+ 223 0034 9A60     		str	r2, [r3, #8]
+ 224              	.LVL13:
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 225              		.loc 1 1900 43 view .LVU63
+ 226              	.LBE300:
+ 227              	.LBE299:
+1310:Src/main.c    **** 
+1311:Src/main.c    **** }
+ 228              		.loc 2 1311 1 view .LVU64
+ 229 0036 03B0     		add	sp, sp, #12
+ 230              	.LCFI2:
+ 231              		.cfi_def_cfa_offset 4
+ 232              		@ sp needed
+ 233 0038 5DF804FB 		ldr	pc, [sp], #4
+ 234              	.L10:
+ 235              		.align	2
+ 236              	.L9:
+ 237 003c 00380240 		.word	1073887232
+ 238 0040 00ED00E0 		.word	-536810240
+ 239 0044 00E100E0 		.word	-536813312
+ 240              		.cfi_endproc
+ 241              	.LFE1201:
+ 243              		.section	.text.Decode_task,"ax",%progbits
+ 244              		.align	1
+ 245              		.syntax unified
+ 246              		.thumb
+ 247              		.thumb_func
+ 248              		.fpu fpv5-d16
+ 250              	Decode_task:
+ 251              	.LVL14:
+ 252              	.LFB1205:
+1312:Src/main.c    **** 
+1313:Src/main.c    **** /**
+1314:Src/main.c    ****   * @brief GPIO Initialization Function
+1315:Src/main.c    ****   * @param None
+1316:Src/main.c    ****   * @retval None
+1317:Src/main.c    ****   */
+1318:Src/main.c    **** static void MX_GPIO_Init(void)
+1319:Src/main.c    **** {
+1320:Src/main.c    ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
+1321:Src/main.c    **** /* USER CODE BEGIN MX_GPIO_Init_1 */
+1322:Src/main.c    **** /* USER CODE END MX_GPIO_Init_1 */
+1323:Src/main.c    **** 
+1324:Src/main.c    ****   /* GPIO Ports Clock Enable */
+1325:Src/main.c    ****   __HAL_RCC_GPIOF_CLK_ENABLE();
+1326:Src/main.c    ****   __HAL_RCC_GPIOH_CLK_ENABLE();
+1327:Src/main.c    ****   __HAL_RCC_GPIOC_CLK_ENABLE();
+1328:Src/main.c    ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+1329:Src/main.c    ****   __HAL_RCC_GPIOB_CLK_ENABLE();
+1330:Src/main.c    ****   __HAL_RCC_GPIOE_CLK_ENABLE();
+ARM GAS  /tmp/ccdsDELB.s 			page 71
+
+
+1331:Src/main.c    ****   __HAL_RCC_GPIOD_CLK_ENABLE();
+1332:Src/main.c    **** 
+1333:Src/main.c    ****   /*Configure GPIO pin Output Level */
+1334:Src/main.c    ****   HAL_GPIO_WritePin(GPIOF, ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET);
+1335:Src/main.c    **** 
+1336:Src/main.c    ****   /*Configure GPIO pin Output Level */
+1337:Src/main.c    ****   HAL_GPIO_WritePin(GPIOC, EN_5V2_Pin|EN_5V1_Pin|LD2_EN_Pin|TEC2_PD_Pin, GPIO_PIN_RESET);
+1338:Src/main.c    **** 
+1339:Src/main.c    ****   /*Configure GPIO pin Output Level */
+1340:Src/main.c    ****   HAL_GPIO_WritePin(GPIOA, TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_LD2_CS_Pin, GPIO_PIN_RESET);
+1341:Src/main.c    **** 
+1342:Src/main.c    ****   /*Configure GPIO pin Output Level */
+1343:Src/main.c    ****   HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);
+1344:Src/main.c    **** 
+1345:Src/main.c    ****   /*Configure GPIO pin Output Level */
+1346:Src/main.c    ****   HAL_GPIO_WritePin(GPIOE, ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET);
+1347:Src/main.c    **** 
+1348:Src/main.c    ****   /*Configure GPIO pin Output Level */
+1349:Src/main.c    ****   HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);
+1350:Src/main.c    **** 
+1351:Src/main.c    ****   /*Configure GPIO pin Output Level */
+1352:Src/main.c    ****   HAL_GPIO_WritePin(GPIOB, REF0_EN_Pin|TEC1_PD_Pin|DAC_LD1_CS_Pin, GPIO_PIN_RESET);
+1353:Src/main.c    **** 
+1354:Src/main.c    ****   /*Configure GPIO pin Output Level */
+1355:Src/main.c    ****   HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);
+1356:Src/main.c    **** 
+1357:Src/main.c    ****   /*Configure GPIO pin Output Level */
+1358:Src/main.c    ****   HAL_GPIO_WritePin(GPIOD, LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7, GPIO_PIN_RESET);
+1359:Src/main.c    **** 
+1360:Src/main.c    ****   /*Configure GPIO pins : ADC_MPD2_CS_Pin SPI5_CNV_Pin ADC_ThrLD2_CS_Pin */
+1361:Src/main.c    ****   GPIO_InitStruct.Pin = ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin;
+1362:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+1363:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1364:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+1365:Src/main.c    ****   HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+1366:Src/main.c    **** 
+1367:Src/main.c    ****   /*Configure GPIO pins : EN_5V2_Pin LD2_EN_Pin TEC2_PD_Pin */
+1368:Src/main.c    ****   GPIO_InitStruct.Pin = EN_5V2_Pin|LD2_EN_Pin|TEC2_PD_Pin;
+1369:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+1370:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1371:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+1372:Src/main.c    ****   HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+1373:Src/main.c    **** 
+1374:Src/main.c    ****   /*Configure GPIO pin : EN_5V1_Pin */
+1375:Src/main.c    ****   GPIO_InitStruct.Pin = EN_5V1_Pin;
+1376:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+1377:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1378:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+1379:Src/main.c    ****   HAL_GPIO_Init(EN_5V1_GPIO_Port, &GPIO_InitStruct);
+1380:Src/main.c    **** 
+1381:Src/main.c    ****   /*Configure GPIO pins : TECEN1_Pin TECEN2_Pin REF2_ON_Pin DAC_TEC2_CS_Pin
+1382:Src/main.c    ****                            DAC_LD2_CS_Pin */
+1383:Src/main.c    ****   GPIO_InitStruct.Pin = TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_TEC2_CS_Pin
+1384:Src/main.c    ****                           |DAC_LD2_CS_Pin;
+1385:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+1386:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1387:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ARM GAS  /tmp/ccdsDELB.s 			page 72
+
+
+1388:Src/main.c    ****   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+1389:Src/main.c    **** 
+1390:Src/main.c    ****   /*Configure GPIO pins : TEC2_FLAG1_Pin TEC2_FLAG2_Pin TEC1_FLAG1_Pin TEC1_FLAG2_Pin */
+1391:Src/main.c    ****   GPIO_InitStruct.Pin = TEC2_FLAG1_Pin|TEC2_FLAG2_Pin|TEC1_FLAG1_Pin|TEC1_FLAG2_Pin;
+1392:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+1393:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1394:Src/main.c    ****   HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+1395:Src/main.c    **** 
+1396:Src/main.c    ****   /*Configure GPIO pins : ADC_MPD1_CS_Pin ADC_ThrLD1_CS_Pin */
+1397:Src/main.c    ****   GPIO_InitStruct.Pin = ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin;
+1398:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+1399:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1400:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+1401:Src/main.c    ****   HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+1402:Src/main.c    **** 
+1403:Src/main.c    ****   /*Configure GPIO pin : SPI4_CNV_Pin */
+1404:Src/main.c    ****   GPIO_InitStruct.Pin = SPI4_CNV_Pin;
+1405:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+1406:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1407:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+1408:Src/main.c    ****   HAL_GPIO_Init(SPI4_CNV_GPIO_Port, &GPIO_InitStruct);
+1409:Src/main.c    **** 
+1410:Src/main.c    ****   /*Configure GPIO pins : REF0_EN_Pin TEC1_PD_Pin DAC_TEC1_CS_Pin DAC_LD1_CS_Pin */
+1411:Src/main.c    ****   GPIO_InitStruct.Pin = REF0_EN_Pin|TEC1_PD_Pin|DAC_TEC1_CS_Pin|DAC_LD1_CS_Pin;
+1412:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+1413:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1414:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+1415:Src/main.c    ****   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+1416:Src/main.c    **** 
+1417:Src/main.c    ****   /*Configure GPIO pins : LD1_EN_Pin TEST_01_Pin PD7 */
+1418:Src/main.c    ****   GPIO_InitStruct.Pin = LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7;
+1419:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+1420:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1421:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+1422:Src/main.c    ****   HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+1423:Src/main.c    **** 
+1424:Src/main.c    ****   /*Configure GPIO pin : USB_FLAG_Pin */
+1425:Src/main.c    ****   GPIO_InitStruct.Pin = USB_FLAG_Pin;
+1426:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+1427:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1428:Src/main.c    ****   HAL_GPIO_Init(USB_FLAG_GPIO_Port, &GPIO_InitStruct);
+1429:Src/main.c    **** 
+1430:Src/main.c    ****   /*Configure GPIO pin : SDMMC1_EN_Pin */
+1431:Src/main.c    ****   GPIO_InitStruct.Pin = SDMMC1_EN_Pin;
+1432:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+1433:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1434:Src/main.c    ****   HAL_GPIO_Init(SDMMC1_EN_GPIO_Port, &GPIO_InitStruct);
+1435:Src/main.c    **** 
+1436:Src/main.c    ****   /*Configure GPIO pin : FPGA_CONF_DONE_Pin */
+1437:Src/main.c    ****   GPIO_InitStruct.Pin = FPGA_CONF_DONE_Pin;
+1438:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+1439:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+1440:Src/main.c    ****   HAL_GPIO_Init(FPGA_CONF_DONE_GPIO_Port, &GPIO_InitStruct);
+1441:Src/main.c    **** 
+1442:Src/main.c    **** /* USER CODE BEGIN MX_GPIO_Init_2 */
+1443:Src/main.c    **** /* USER CODE END MX_GPIO_Init_2 */
+1444:Src/main.c    **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 73
+
+
+1445:Src/main.c    **** 
+1446:Src/main.c    **** /* USER CODE BEGIN 4 */
+1447:Src/main.c    **** 
+1448:Src/main.c    **** //void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
+1449:Src/main.c    **** 
+1450:Src/main.c    **** //	UART_transmission_request = NO_MESS;
+1451:Src/main.c    **** 
+1452:Src/main.c    **** //}
+1453:Src/main.c    **** 
+1454:Src/main.c    **** static void Init_params(void)
+1455:Src/main.c    **** {
+1456:Src/main.c    **** 	TO6 = 0;
+1457:Src/main.c    **** 	TO7 = 0;
+1458:Src/main.c    **** 	TO7_before = 0;
+1459:Src/main.c    **** 	TO6_before = 0;
+1460:Src/main.c    **** 	TO6_uart = 0;
+1461:Src/main.c    **** 	flg_tmt = 0;
+1462:Src/main.c    **** 	UART_rec_incr = 0;
+1463:Src/main.c    **** 	fgoto = 0;
+1464:Src/main.c    **** 	sizeoffile = 0;
+1465:Src/main.c    **** 	u_tx_flg = 0;
+1466:Src/main.c    **** 	u_rx_flg = 0;
+1467:Src/main.c    **** 	//State_Data[0]=0;
+1468:Src/main.c    **** 	//State_Data[1]=0;//All OK!
+1469:Src/main.c    **** 	for (uint16_t i=0; iWORK_EN = ((uint8_t)((*temp2)>>0))&0x01;
+1621:Src/main.c    **** 	Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01;
+1622:Src/main.c    **** 	Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01;
+1623:Src/main.c    **** 	Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01;
+1624:Src/main.c    **** 	Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01;
+1625:Src/main.c    **** 	Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01;
+1626:Src/main.c    **** 	Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01;
+1627:Src/main.c    **** 	Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01;
+1628:Src/main.c    **** 	Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01;
+1629:Src/main.c    **** 	Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01;
+1630:Src/main.c    **** 	Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01;
+1631:Src/main.c    **** 	Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01;
+1632:Src/main.c    **** 	Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01;
+1633:Src/main.c    **** 	Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01;
+1634:Src/main.c    **** 	
+1635:Src/main.c    **** 	temp2++;
+1636:Src/main.c    **** 	LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2);
+1637:Src/main.c    **** 	temp2++;
+1638:Src/main.c    **** 	LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2);
+1639:Src/main.c    **** 	temp2++;
+1640:Src/main.c    **** 	temp2++;
+1641:Src/main.c    **** 	temp2++;
+1642:Src/main.c    **** 	Curr_setup->AVERAGES = (uint16_t)(*temp2);
+1643:Src/main.c    **** 	temp2++;
+1644:Src/main.c    **** 	LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint
+1645:Src/main.c    **** 	temp2++;
+1646:Src/main.c    **** 	LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint
+1647:Src/main.c    **** 	temp2++;
+1648:Src/main.c    **** 	LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint
+1649:Src/main.c    **** 	temp2++;
+1650:Src/main.c    **** 	LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint
+1651:Src/main.c    **** 	temp2++;
+1652:Src/main.c    **** 	Long_Data[13] = (uint16_t)(*temp2);//Message ID
+1653:Src/main.c    **** 	temp2++;
+1654:Src/main.c    **** 	LD1_curr_setup->CURRENT = (uint16_t)(*temp2);
+1655:Src/main.c    **** 	temp2++;
+1656:Src/main.c    **** 	LD2_curr_setup->CURRENT = (uint16_t)(*temp2);
+1657:Src/main.c    **** 	temp2++;
+1658:Src/main.c    **** 	
+1659:Src/main.c    **** 	if (Curr_setup->U5V1_EN)
+1660:Src/main.c    **** 	{
+1661:Src/main.c    **** 		HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_SET);
+1662:Src/main.c    **** 	}
+1663:Src/main.c    **** 	else
+1664:Src/main.c    **** 	{
+1665:Src/main.c    **** 		HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_RESET);
+1666:Src/main.c    **** 	}
+1667:Src/main.c    **** 	
+1668:Src/main.c    **** 	if (Curr_setup->U5V2_EN)
+1669:Src/main.c    **** 	{
+1670:Src/main.c    **** 		HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_SET);
+1671:Src/main.c    **** 	}
+1672:Src/main.c    **** 	else
+ARM GAS  /tmp/ccdsDELB.s 			page 77
+
+
+1673:Src/main.c    **** 	{
+1674:Src/main.c    **** 		HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET);
+1675:Src/main.c    **** 	}
+1676:Src/main.c    **** 	
+1677:Src/main.c    **** 	if (Curr_setup->LD1_EN)
+1678:Src/main.c    **** 	{
+1679:Src/main.c    **** 		HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_SET);
+1680:Src/main.c    **** 		//LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC
+1681:Src/main.c    **** 	}
+1682:Src/main.c    **** 	else
+1683:Src/main.c    **** 	{
+1684:Src/main.c    **** 		HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET);
+1685:Src/main.c    **** 		//LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC
+1686:Src/main.c    **** 	}
+1687:Src/main.c    **** 	
+1688:Src/main.c    **** 	if (Curr_setup->LD2_EN)
+1689:Src/main.c    **** 	{
+1690:Src/main.c    **** 		HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_SET);
+1691:Src/main.c    **** 		//LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC
+1692:Src/main.c    **** 	}
+1693:Src/main.c    **** 	else
+1694:Src/main.c    **** 	{
+1695:Src/main.c    **** 		HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET);
+1696:Src/main.c    **** 		//LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC
+1697:Src/main.c    **** 	}
+1698:Src/main.c    **** 	
+1699:Src/main.c    **** 	if (Curr_setup->REF1_EN)
+1700:Src/main.c    **** 	{
+1701:Src/main.c    **** 		HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_SET);
+1702:Src/main.c    **** 	}
+1703:Src/main.c    **** 	else
+1704:Src/main.c    **** 	{
+1705:Src/main.c    **** 		HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET);
+1706:Src/main.c    **** 	}
+1707:Src/main.c    **** 	
+1708:Src/main.c    **** 	if (Curr_setup->REF2_EN)
+1709:Src/main.c    **** 	{
+1710:Src/main.c    **** 		HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_SET);
+1711:Src/main.c    **** 	}
+1712:Src/main.c    **** 	else
+1713:Src/main.c    **** 	{
+1714:Src/main.c    **** 		HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET);
+1715:Src/main.c    **** 	}
+1716:Src/main.c    **** 	
+1717:Src/main.c    **** 	if ((Curr_setup->TS1_EN)&&(Curr_setup->TEC1_EN))
+1718:Src/main.c    **** 	{
+1719:Src/main.c    **** 		Set_LTEC(3,32767);
+1720:Src/main.c    **** 		Set_LTEC(3,32767);
+1721:Src/main.c    **** 		HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET);
+1722:Src/main.c    **** 		HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET);
+1723:Src/main.c    **** 	}
+1724:Src/main.c    **** 	else
+1725:Src/main.c    **** 	{
+1726:Src/main.c    **** 		HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET);
+1727:Src/main.c    **** 		HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET);		
+1728:Src/main.c    **** 	}
+1729:Src/main.c    **** 	
+ARM GAS  /tmp/ccdsDELB.s 			page 78
+
+
+1730:Src/main.c    **** 	if ((Curr_setup->TS2_EN)&&(Curr_setup->TEC2_EN))
+1731:Src/main.c    **** 	{
+1732:Src/main.c    **** 		Set_LTEC(4,32767);
+1733:Src/main.c    **** 		Set_LTEC(4,32767);
+1734:Src/main.c    **** 		HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET);
+1735:Src/main.c    **** 		HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET);
+1736:Src/main.c    **** 	}
+1737:Src/main.c    **** 	else
+1738:Src/main.c    **** 	{
+1739:Src/main.c    **** 		HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET);
+1740:Src/main.c    **** 		HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET);		
+1741:Src/main.c    **** 	}
+1742:Src/main.c    **** 	
+1743:Src/main.c    **** 	if (Curr_setup->PI1_RD==0)
+1744:Src/main.c    **** 	{
+1745:Src/main.c    **** 		LD1_curr_setup->P_coef_temp = 10;
+1746:Src/main.c    **** 		LD1_curr_setup->I_coef_temp = 0.01;
+1747:Src/main.c    **** 	}
+1748:Src/main.c    **** 	
+1749:Src/main.c    **** 	if (Curr_setup->PI2_RD==0)
+1750:Src/main.c    **** 	{
+1751:Src/main.c    **** 		LD2_curr_setup->P_coef_temp = 10;
+1752:Src/main.c    **** 		LD2_curr_setup->I_coef_temp = 0.01;
+1753:Src/main.c    **** 	}
+1754:Src/main.c    **** }
+1755:Src/main.c    **** 
+1756:Src/main.c    **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_
+1757:Src/main.c    **** {
+ 253              		.loc 2 1757 1 is_stmt 1 view -0
+ 254              		.cfi_startproc
+ 255              		@ args = 0, pretend = 0, frame = 8
+ 256              		@ frame_needed = 0, uses_anonymous_args = 0
+ 257              		@ link register save eliminated.
+ 258              		.loc 2 1757 1 is_stmt 0 view .LVU66
+ 259 0000 82B0     		sub	sp, sp, #8
+ 260              	.LCFI3:
+ 261              		.cfi_def_cfa_offset 8
+1758:Src/main.c    **** 	uint16_t *temp2;
+ 262              		.loc 2 1758 2 is_stmt 1 view .LVU67
+1759:Src/main.c    **** 
+1760:Src/main.c    **** 	temp2 = (uint16_t *)Command;
+ 263              		.loc 2 1760 2 view .LVU68
+ 264              	.LVL15:
+1761:Src/main.c    **** 	Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01;
+ 265              		.loc 2 1761 2 view .LVU69
+ 266              		.loc 2 1761 36 is_stmt 0 view .LVU70
+ 267 0002 0288     		ldrh	r2, [r0]
+ 268              	.LVL16:
+ 269              		.loc 2 1761 48 view .LVU71
+ 270 0004 02F00102 		and	r2, r2, #1
+ 271              		.loc 2 1761 22 view .LVU72
+ 272 0008 1A70     		strb	r2, [r3]
+1762:Src/main.c    **** 	Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01;
+ 273              		.loc 2 1762 2 is_stmt 1 view .LVU73
+ 274              		.loc 2 1762 36 is_stmt 0 view .LVU74
+ 275 000a 0288     		ldrh	r2, [r0]
+ 276              		.loc 2 1762 48 view .LVU75
+ARM GAS  /tmp/ccdsDELB.s 			page 79
+
+
+ 277 000c C2F34002 		ubfx	r2, r2, #1, #1
+ 278              		.loc 2 1762 22 view .LVU76
+ 279 0010 5A70     		strb	r2, [r3, #1]
+1763:Src/main.c    **** 	Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01;
+ 280              		.loc 2 1763 2 is_stmt 1 view .LVU77
+ 281              		.loc 2 1763 36 is_stmt 0 view .LVU78
+ 282 0012 0288     		ldrh	r2, [r0]
+ 283              		.loc 2 1763 48 view .LVU79
+ 284 0014 C2F38002 		ubfx	r2, r2, #2, #1
+ 285              		.loc 2 1763 22 view .LVU80
+ 286 0018 9A70     		strb	r2, [r3, #2]
+1764:Src/main.c    **** 	Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01;
+ 287              		.loc 2 1764 2 is_stmt 1 view .LVU81
+ 288              		.loc 2 1764 35 is_stmt 0 view .LVU82
+ 289 001a 0288     		ldrh	r2, [r0]
+ 290              		.loc 2 1764 47 view .LVU83
+ 291 001c C2F3C002 		ubfx	r2, r2, #3, #1
+ 292              		.loc 2 1764 21 view .LVU84
+ 293 0020 DA70     		strb	r2, [r3, #3]
+1765:Src/main.c    **** 	Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01;
+ 294              		.loc 2 1765 2 is_stmt 1 view .LVU85
+ 295              		.loc 2 1765 35 is_stmt 0 view .LVU86
+ 296 0022 0288     		ldrh	r2, [r0]
+ 297              		.loc 2 1765 47 view .LVU87
+ 298 0024 C2F30012 		ubfx	r2, r2, #4, #1
+ 299              		.loc 2 1765 21 view .LVU88
+ 300 0028 1A71     		strb	r2, [r3, #4]
+1766:Src/main.c    **** 	Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01;
+ 301              		.loc 2 1766 2 is_stmt 1 view .LVU89
+ 302              		.loc 2 1766 36 is_stmt 0 view .LVU90
+ 303 002a 0288     		ldrh	r2, [r0]
+ 304              		.loc 2 1766 48 view .LVU91
+ 305 002c C2F34012 		ubfx	r2, r2, #5, #1
+ 306              		.loc 2 1766 22 view .LVU92
+ 307 0030 5A71     		strb	r2, [r3, #5]
+1767:Src/main.c    **** 	Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01;
+ 308              		.loc 2 1767 2 is_stmt 1 view .LVU93
+ 309              		.loc 2 1767 36 is_stmt 0 view .LVU94
+ 310 0032 0288     		ldrh	r2, [r0]
+ 311              		.loc 2 1767 48 view .LVU95
+ 312 0034 C2F38012 		ubfx	r2, r2, #6, #1
+ 313              		.loc 2 1767 22 view .LVU96
+ 314 0038 9A71     		strb	r2, [r3, #6]
+1768:Src/main.c    **** 	Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01;
+ 315              		.loc 2 1768 2 is_stmt 1 view .LVU97
+ 316              		.loc 2 1768 36 is_stmt 0 view .LVU98
+ 317 003a 0288     		ldrh	r2, [r0]
+ 318              		.loc 2 1768 48 view .LVU99
+ 319 003c C2F3C012 		ubfx	r2, r2, #7, #1
+ 320              		.loc 2 1768 22 view .LVU100
+ 321 0040 DA71     		strb	r2, [r3, #7]
+1769:Src/main.c    **** 	Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01;
+ 322              		.loc 2 1769 2 is_stmt 1 view .LVU101
+ 323              		.loc 2 1769 36 is_stmt 0 view .LVU102
+ 324 0042 0288     		ldrh	r2, [r0]
+ 325              		.loc 2 1769 48 view .LVU103
+ 326 0044 C2F30022 		ubfx	r2, r2, #8, #1
+ARM GAS  /tmp/ccdsDELB.s 			page 80
+
+
+ 327              		.loc 2 1769 22 view .LVU104
+ 328 0048 1A72     		strb	r2, [r3, #8]
+1770:Src/main.c    **** 	Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01;
+ 329              		.loc 2 1770 2 is_stmt 1 view .LVU105
+ 330              		.loc 2 1770 35 is_stmt 0 view .LVU106
+ 331 004a 0288     		ldrh	r2, [r0]
+ 332              		.loc 2 1770 47 view .LVU107
+ 333 004c C2F34022 		ubfx	r2, r2, #9, #1
+ 334              		.loc 2 1770 21 view .LVU108
+ 335 0050 5A72     		strb	r2, [r3, #9]
+1771:Src/main.c    **** 	Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01;
+ 336              		.loc 2 1771 2 is_stmt 1 view .LVU109
+ 337              		.loc 2 1771 35 is_stmt 0 view .LVU110
+ 338 0052 0288     		ldrh	r2, [r0]
+ 339              		.loc 2 1771 48 view .LVU111
+ 340 0054 C2F38022 		ubfx	r2, r2, #10, #1
+ 341              		.loc 2 1771 21 view .LVU112
+ 342 0058 9A72     		strb	r2, [r3, #10]
+1772:Src/main.c    **** 	Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01;
+ 343              		.loc 2 1772 2 is_stmt 1 view .LVU113
+ 344              		.loc 2 1772 34 is_stmt 0 view .LVU114
+ 345 005a 0288     		ldrh	r2, [r0]
+ 346              		.loc 2 1772 47 view .LVU115
+ 347 005c C2F3C022 		ubfx	r2, r2, #11, #1
+ 348              		.loc 2 1772 20 view .LVU116
+ 349 0060 DA72     		strb	r2, [r3, #11]
+1773:Src/main.c    **** 	Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01;
+ 350              		.loc 2 1773 2 is_stmt 1 view .LVU117
+ 351              		.loc 2 1773 35 is_stmt 0 view .LVU118
+ 352 0062 0288     		ldrh	r2, [r0]
+ 353              		.loc 2 1773 48 view .LVU119
+ 354 0064 C2F30032 		ubfx	r2, r2, #12, #1
+ 355              		.loc 2 1773 21 view .LVU120
+ 356 0068 1A73     		strb	r2, [r3, #12]
+1774:Src/main.c    **** 	Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01;
+ 357              		.loc 2 1774 2 is_stmt 1 view .LVU121
+ 358              		.loc 2 1774 35 is_stmt 0 view .LVU122
+ 359 006a 0288     		ldrh	r2, [r0]
+ 360              		.loc 2 1774 48 view .LVU123
+ 361 006c C2F34032 		ubfx	r2, r2, #13, #1
+ 362              		.loc 2 1774 21 view .LVU124
+ 363 0070 5A73     		strb	r2, [r3, #13]
+1775:Src/main.c    **** 
+1776:Src/main.c    **** 	temp2++;
+ 364              		.loc 2 1776 2 is_stmt 1 view .LVU125
+ 365              	.LVL17:
+1777:Src/main.c    **** 	task.task_type   = (uint8_t)(*temp2); temp2++;
+ 366              		.loc 2 1777 2 view .LVU126
+ 367              		.loc 2 1777 21 is_stmt 0 view .LVU127
+ 368 0072 8278     		ldrb	r2, [r0, #2]	@ zero_extendqisi2
+ 369              		.loc 2 1777 19 view .LVU128
+ 370 0074 384B     		ldr	r3, .L13+8
+ 371              	.LVL18:
+ 372              		.loc 2 1777 19 view .LVU129
+ 373 0076 1A70     		strb	r2, [r3]
+ 374              		.loc 2 1777 40 is_stmt 1 view .LVU130
+ 375              	.LVL19:
+ARM GAS  /tmp/ccdsDELB.s 			page 81
+
+
+1778:Src/main.c    **** 	task.min_param   = (float)(*temp2); temp2++;
+ 376              		.loc 2 1778 2 view .LVU131
+ 377              		.loc 2 1778 29 is_stmt 0 view .LVU132
+ 378 0078 8288     		ldrh	r2, [r0, #4]
+ 379 007a 07EE902A 		vmov	s15, r2	@ int
+ 380              		.loc 2 1778 21 view .LVU133
+ 381 007e F8EE677A 		vcvt.f32.u32	s15, s15
+ 382              		.loc 2 1778 19 view .LVU134
+ 383 0082 C3ED017A 		vstr.32	s15, [r3, #4]
+ 384              		.loc 2 1778 38 is_stmt 1 view .LVU135
+ 385              	.LVL20:
+1779:Src/main.c    **** 	task.max_param   = (float)(*temp2); temp2++;
+ 386              		.loc 2 1779 2 view .LVU136
+ 387              		.loc 2 1779 29 is_stmt 0 view .LVU137
+ 388 0086 C288     		ldrh	r2, [r0, #6]
+ 389 0088 07EE902A 		vmov	s15, r2	@ int
+ 390              		.loc 2 1779 21 view .LVU138
+ 391 008c F8EE677A 		vcvt.f32.u32	s15, s15
+ 392              		.loc 2 1779 19 view .LVU139
+ 393 0090 C3ED027A 		vstr.32	s15, [r3, #8]
+ 394              		.loc 2 1779 38 is_stmt 1 view .LVU140
+ 395              	.LVL21:
+1780:Src/main.c    **** 	task.delta_param = (float)(*temp2); temp2++;
+ 396              		.loc 2 1780 2 view .LVU141
+ 397              		.loc 2 1780 29 is_stmt 0 view .LVU142
+ 398 0094 0289     		ldrh	r2, [r0, #8]
+ 399 0096 07EE902A 		vmov	s15, r2	@ int
+ 400              		.loc 2 1780 21 view .LVU143
+ 401 009a F8EE677A 		vcvt.f32.u32	s15, s15
+ 402              		.loc 2 1780 19 view .LVU144
+ 403 009e C3ED037A 		vstr.32	s15, [r3, #12]
+ 404              		.loc 2 1780 38 is_stmt 1 view .LVU145
+ 405              	.LVL22:
+1781:Src/main.c    **** 	task.dt          = (float)(*temp2) / 100.0; temp2++;
+ 406              		.loc 2 1781 2 view .LVU146
+ 407              		.loc 2 1781 29 is_stmt 0 view .LVU147
+ 408 00a2 4289     		ldrh	r2, [r0, #10]
+ 409 00a4 07EE102A 		vmov	s14, r2	@ int
+ 410              		.loc 2 1781 21 view .LVU148
+ 411 00a8 B8EE477B 		vcvt.f64.u32	d7, s14
+ 412              		.loc 2 1781 37 view .LVU149
+ 413 00ac 9FED285B 		vldr.64	d5, .L13
+ 414 00b0 87EE056B 		vdiv.f64	d6, d7, d5
+ 415              		.loc 2 1781 19 view .LVU150
+ 416 00b4 FCEEC67B 		vcvt.u32.f64	s15, d6
+ 417 00b8 CDED017A 		vstr.32	s15, [sp, #4]	@ int
+ 418 00bc 9DF80420 		ldrb	r2, [sp, #4]	@ zero_extendqisi2
+ 419 00c0 1A75     		strb	r2, [r3, #20]
+ 420              		.loc 2 1781 46 is_stmt 1 view .LVU151
+ 421              	.LVL23:
+1782:Src/main.c    **** 	task.sec_param   = (float)(*temp2); temp2++;
+ 422              		.loc 2 1782 2 view .LVU152
+ 423              		.loc 2 1782 29 is_stmt 0 view .LVU153
+ 424 00c2 8189     		ldrh	r1, [r0, #12]
+ 425              	.LVL24:
+ 426              		.loc 2 1782 29 view .LVU154
+ 427 00c4 07EE901A 		vmov	s15, r1	@ int
+ARM GAS  /tmp/ccdsDELB.s 			page 82
+
+
+ 428              		.loc 2 1782 21 view .LVU155
+ 429 00c8 F8EE677A 		vcvt.f32.u32	s15, s15
+ 430              		.loc 2 1782 19 view .LVU156
+ 431 00cc C3ED067A 		vstr.32	s15, [r3, #24]
+ 432              		.loc 2 1782 38 is_stmt 1 view .LVU157
+ 433              	.LVL25:
+1783:Src/main.c    **** 	task.curr        = (float)(*temp2); temp2++;
+ 434              		.loc 2 1783 2 view .LVU158
+ 435              		.loc 2 1783 29 is_stmt 0 view .LVU159
+ 436 00d0 C189     		ldrh	r1, [r0, #14]
+ 437 00d2 07EE901A 		vmov	s15, r1	@ int
+ 438              		.loc 2 1783 21 view .LVU160
+ 439 00d6 F8EE677A 		vcvt.f32.u32	s15, s15
+ 440              		.loc 2 1783 19 view .LVU161
+ 441 00da C3ED077A 		vstr.32	s15, [r3, #28]
+ 442              		.loc 2 1783 38 is_stmt 1 view .LVU162
+ 443              	.LVL26:
+1784:Src/main.c    **** 	task.temp        = (float)(*temp2); temp2++;
+ 444              		.loc 2 1784 2 view .LVU163
+ 445              		.loc 2 1784 29 is_stmt 0 view .LVU164
+ 446 00de 018A     		ldrh	r1, [r0, #16]
+ 447 00e0 07EE901A 		vmov	s15, r1	@ int
+ 448              		.loc 2 1784 21 view .LVU165
+ 449 00e4 F8EE677A 		vcvt.f32.u32	s15, s15
+ 450              		.loc 2 1784 19 view .LVU166
+ 451 00e8 C3ED087A 		vstr.32	s15, [r3, #32]
+ 452              		.loc 2 1784 38 is_stmt 1 view .LVU167
+ 453              	.LVL27:
+1785:Src/main.c    **** 	task.tau         = (float)(*temp2); temp2++;
+ 454              		.loc 2 1785 2 view .LVU168
+ 455              		.loc 2 1785 29 is_stmt 0 view .LVU169
+ 456 00ec 418A     		ldrh	r1, [r0, #18]
+ 457              		.loc 2 1785 19 view .LVU170
+ 458 00ee D982     		strh	r1, [r3, #22]	@ movhi
+ 459              		.loc 2 1785 38 is_stmt 1 view .LVU171
+ 460              	.LVL28:
+1786:Src/main.c    **** 	task.p_coef_1    = (float)(*temp2) * 256.0; temp2++;
+ 461              		.loc 2 1786 2 view .LVU172
+ 462              		.loc 2 1786 29 is_stmt 0 view .LVU173
+ 463 00f0 818A     		ldrh	r1, [r0, #20]
+ 464 00f2 07EE101A 		vmov	s14, r1	@ int
+ 465              		.loc 2 1786 21 view .LVU174
+ 466 00f6 B8EE477A 		vcvt.f32.u32	s14, s14
+ 467              		.loc 2 1786 37 view .LVU175
+ 468 00fa DFED186A 		vldr.32	s13, .L13+12
+ 469 00fe 27EE267A 		vmul.f32	s14, s14, s13
+ 470              		.loc 2 1786 19 view .LVU176
+ 471 0102 83ED0A7A 		vstr.32	s14, [r3, #40]
+ 472              		.loc 2 1786 46 is_stmt 1 view .LVU177
+ 473              	.LVL29:
+1787:Src/main.c    **** 	task.i_coef_1    = (float)(*temp2) * 256.0; temp2++;
+ 474              		.loc 2 1787 2 view .LVU178
+ 475              		.loc 2 1787 29 is_stmt 0 view .LVU179
+ 476 0106 C18A     		ldrh	r1, [r0, #22]
+ 477 0108 07EE101A 		vmov	s14, r1	@ int
+ 478              		.loc 2 1787 21 view .LVU180
+ 479 010c B8EE477A 		vcvt.f32.u32	s14, s14
+ARM GAS  /tmp/ccdsDELB.s 			page 83
+
+
+ 480              		.loc 2 1787 37 view .LVU181
+ 481 0110 27EE267A 		vmul.f32	s14, s14, s13
+ 482              		.loc 2 1787 19 view .LVU182
+ 483 0114 83ED097A 		vstr.32	s14, [r3, #36]
+ 484              		.loc 2 1787 46 is_stmt 1 view .LVU183
+ 485              	.LVL30:
+1788:Src/main.c    **** 	task.p_coef_2    = (float)(*temp2) * 256.0; temp2++;
+ 486              		.loc 2 1788 2 view .LVU184
+ 487              		.loc 2 1788 29 is_stmt 0 view .LVU185
+ 488 0118 018B     		ldrh	r1, [r0, #24]
+ 489 011a 07EE101A 		vmov	s14, r1	@ int
+ 490              		.loc 2 1788 21 view .LVU186
+ 491 011e B8EE477A 		vcvt.f32.u32	s14, s14
+ 492              		.loc 2 1788 37 view .LVU187
+ 493 0122 27EE267A 		vmul.f32	s14, s14, s13
+ 494              		.loc 2 1788 19 view .LVU188
+ 495 0126 83ED0C7A 		vstr.32	s14, [r3, #48]
+ 496              		.loc 2 1788 46 is_stmt 1 view .LVU189
+ 497              	.LVL31:
+1789:Src/main.c    **** 	task.i_coef_2    = (float)(*temp2) * 256.0; temp2++;
+ 498              		.loc 2 1789 2 view .LVU190
+ 499              		.loc 2 1789 29 is_stmt 0 view .LVU191
+ 500 012a 418B     		ldrh	r1, [r0, #26]
+ 501 012c 07EE901A 		vmov	s15, r1	@ int
+ 502              		.loc 2 1789 21 view .LVU192
+ 503 0130 F8EE677A 		vcvt.f32.u32	s15, s15
+ 504              		.loc 2 1789 37 view .LVU193
+ 505 0134 67EEA67A 		vmul.f32	s15, s15, s13
+ 506              		.loc 2 1789 19 view .LVU194
+ 507 0138 C3ED0B7A 		vstr.32	s15, [r3, #44]
+ 508              		.loc 2 1789 46 is_stmt 1 view .LVU195
+ 509              	.LVL32:
+1790:Src/main.c    **** 	
+1791:Src/main.c    **** 	TO10_counter = task.dt / 10 - 1;
+ 510              		.loc 2 1791 2 view .LVU196
+ 511              		.loc 2 1791 25 is_stmt 0 view .LVU197
+ 512 013c 084B     		ldr	r3, .L13+16
+ 513 013e A3FB0232 		umull	r3, r2, r3, r2
+ 514 0142 D208     		lsrs	r2, r2, #3
+ 515              		.loc 2 1791 30 view .LVU198
+ 516 0144 013A     		subs	r2, r2, #1
+ 517              		.loc 2 1791 15 view .LVU199
+ 518 0146 074B     		ldr	r3, .L13+20
+ 519 0148 1A60     		str	r2, [r3]
+1792:Src/main.c    **** }
+ 520              		.loc 2 1792 1 view .LVU200
+ 521 014a 02B0     		add	sp, sp, #8
+ 522              	.LCFI4:
+ 523              		.cfi_def_cfa_offset 0
+ 524              		@ sp needed
+ 525 014c 7047     		bx	lr
+ 526              	.L14:
+ 527 014e 00BF     		.align	3
+ 528              	.L13:
+ 529 0150 00000000 		.word	0
+ 530 0154 00005940 		.word	1079574528
+ 531 0158 00000000 		.word	.LANCHOR1
+ARM GAS  /tmp/ccdsDELB.s 			page 84
+
+
+ 532 015c 00008043 		.word	1132462080
+ 533 0160 CDCCCCCC 		.word	-858993459
+ 534 0164 00000000 		.word	.LANCHOR2
+ 535              		.cfi_endproc
+ 536              	.LFE1205:
+ 538              		.section	.text.PID_Controller_Temp,"ax",%progbits
+ 539              		.align	1
+ 540              		.syntax unified
+ 541              		.thumb
+ 542              		.thumb_func
+ 543              		.fpu fpv5-d16
+ 545              	PID_Controller_Temp:
+ 546              	.LVL33:
+ 547              	.LFB1209:
+1793:Src/main.c    **** 
+1794:Src/main.c    **** void Set_LTEC(uint8_t num, uint16_t DATA)
+1795:Src/main.c    **** {
+1796:Src/main.c    **** 	uint32_t tmp32;
+1797:Src/main.c    **** 	switch (num)
+1798:Src/main.c    **** 	{
+1799:Src/main.c    **** 		case 1:
+1800:Src/main.c    **** 			HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_RESET);//Start operation with L
+1801:Src/main.c    **** 			//tmp32=0;
+1802:Src/main.c    **** 			//while(tmp32<500){tmp32++;}
+1803:Src/main.c    **** 			tmp32 = 0;
+1804:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+1805:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+1806:Src/main.c    **** 			tmp32 = 0;
+1807:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+1808:Src/main.c    **** 			(void) SPI2->DR;
+1809:Src/main.c    **** 		break;
+1810:Src/main.c    **** 		case 2:
+1811:Src/main.c    **** 			HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_RESET);//Start operation with L
+1812:Src/main.c    **** 			//tmp32=0;
+1813:Src/main.c    **** 			//while(tmp32<500){tmp32++;}
+1814:Src/main.c    **** 			tmp32 = 0;
+1815:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+1816:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+1817:Src/main.c    **** 			tmp32 = 0;
+1818:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+1819:Src/main.c    **** 			(void) SPI6->DR;
+1820:Src/main.c    **** 		break;
+1821:Src/main.c    **** 		case 3:
+1822:Src/main.c    **** 			HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_RESET);//Start operation with
+1823:Src/main.c    **** 			//tmp32=0;
+1824:Src/main.c    **** 			//while(tmp32<500){tmp32++;}
+1825:Src/main.c    **** 			tmp32 = 0;
+1826:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+1827:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+1828:Src/main.c    **** 			tmp32 = 0;
+1829:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+1830:Src/main.c    **** 			(void) SPI2->DR;
+1831:Src/main.c    **** 		break;
+1832:Src/main.c    **** 		case 4:
+1833:Src/main.c    **** 			HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_RESET);//Start operation with
+1834:Src/main.c    **** 			//tmp32=0;
+1835:Src/main.c    **** 			//while(tmp32<500){tmp32++;}
+ARM GAS  /tmp/ccdsDELB.s 			page 85
+
+
+1836:Src/main.c    **** 			tmp32 = 0;
+1837:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+1838:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+1839:Src/main.c    **** 			tmp32 = 0;
+1840:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+1841:Src/main.c    **** 			(void) SPI6->DR;
+1842:Src/main.c    **** 		break;
+1843:Src/main.c    **** 	}
+1844:Src/main.c    **** 	HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1
+1845:Src/main.c    **** 	HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2
+1846:Src/main.c    **** 	HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1
+1847:Src/main.c    **** 	HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2
+1848:Src/main.c    **** }
+1849:Src/main.c    **** static uint16_t MPhD_T(uint8_t num)
+1850:Src/main.c    **** {
+1851:Src/main.c    **** 	uint16_t P;
+1852:Src/main.c    **** 	uint32_t tmp32;
+1853:Src/main.c    **** 	HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion
+1854:Src/main.c    **** 	HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion
+1855:Src/main.c    **** 	tmp32=0;
+1856:Src/main.c    **** 	while(tmp32<500){tmp32++;}
+1857:Src/main.c    **** 	HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver
+1858:Src/main.c    **** 	HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver
+1859:Src/main.c    **** 	tmp32=0;
+1860:Src/main.c    **** 	while(tmp32<500){tmp32++;}
+1861:Src/main.c    **** 	if (num==1)//MPD1
+1862:Src/main.c    **** 	{
+1863:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET);
+1864:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET);
+1865:Src/main.c    **** 		tmp32=0;
+1866:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+1867:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+1868:Src/main.c    **** 		LL_SPI_Enable(SPI4);//Enable SPI for MPhD1 ADC
+1869:Src/main.c    **** 		tmp32 = 0;
+1870:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+1871:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC
+1872:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+1873:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+1874:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET);
+1875:Src/main.c    **** 		P = LL_SPI_ReceiveData16(SPI4);
+1876:Src/main.c    **** 	}
+1877:Src/main.c    **** 	else if (num==2)//MPD2
+1878:Src/main.c    **** 	{
+1879:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET);
+1880:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET);
+1881:Src/main.c    **** 		tmp32=0;
+1882:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+1883:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+1884:Src/main.c    **** 		LL_SPI_Enable(SPI5);//Enable SPI for MPhD2 ADC
+1885:Src/main.c    **** 		tmp32 = 0;
+1886:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+1887:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC
+1888:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+1889:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+1890:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET);
+1891:Src/main.c    **** 		P = LL_SPI_ReceiveData16(SPI5);
+1892:Src/main.c    **** 	}
+ARM GAS  /tmp/ccdsDELB.s 			page 86
+
+
+1893:Src/main.c    **** 	else if (num==3)//ThrLD1
+1894:Src/main.c    **** 	{
+1895:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET);
+1896:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET);
+1897:Src/main.c    **** 		tmp32=0;
+1898:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+1899:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+1900:Src/main.c    **** 		LL_SPI_Enable(SPI4);//Enable SPI for ThrLD1 ADC
+1901:Src/main.c    **** 		tmp32 = 0;
+1902:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+1903:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC
+1904:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+1905:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+1906:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET);
+1907:Src/main.c    **** 		P = LL_SPI_ReceiveData16(SPI4);
+1908:Src/main.c    **** 	}
+1909:Src/main.c    **** 	else if (num==4)//ThrLD2
+1910:Src/main.c    **** 	{
+1911:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET);
+1912:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET);
+1913:Src/main.c    **** 		tmp32=0;
+1914:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+1915:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+1916:Src/main.c    **** 		LL_SPI_Enable(SPI5);//Enable SPI for ThrLD2 ADC
+1917:Src/main.c    **** 		tmp32 = 0;
+1918:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+1919:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC
+1920:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+1921:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+1922:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET);
+1923:Src/main.c    **** 		P = LL_SPI_ReceiveData16(SPI5);
+1924:Src/main.c    **** 	}
+1925:Src/main.c    **** 	/*float I_LD, Ith, I0m, T0m, Inorm, Tnorm1, Tnorm2, P, T_C, A, Pnorm;
+1926:Src/main.c    **** 	
+1927:Src/main.c    **** 	Inorm = (float) (65535) / (float) (100);
+1928:Src/main.c    **** 	Tnorm1 = (float) (65535) / (float) (50);
+1929:Src/main.c    **** 	Tnorm2 = 4;
+1930:Src/main.c    **** 	Pnorm = (float)(65535) / (float)(20);
+1931:Src/main.c    **** 	I0m = 8.1568;//@4 C - lowest temperature of system
+1932:Src/main.c    **** 	T0m = 48.6282;
+1933:Src/main.c    **** 	T_C = (float) (T_LD) / Tnorm1 + Tnorm2;
+1934:Src/main.c    **** 	
+1935:Src/main.c    **** 	Ith = I0m * expf(T_C/T0m);
+1936:Src/main.c    **** 	I_LD = (float) (C_LD) / Inorm;
+1937:Src/main.c    **** 	
+1938:Src/main.c    **** 	if (I_LD > Ith)
+1939:Src/main.c    **** 	{
+1940:Src/main.c    **** 		A = (float) (2.24276128270098e-07) * T_C * T_C * T_C  - (float) (4.73392579025590e-05) * T_C * T_
+1941:Src/main.c    **** 		P = A * (I_LD - Ith) * Pnorm;
+1942:Src/main.c    **** 	}
+1943:Src/main.c    **** 	else
+1944:Src/main.c    **** 	{
+1945:Src/main.c    **** 		P = 0;
+1946:Src/main.c    **** 	}	*/
+1947:Src/main.c    **** 	return P;
+1948:Src/main.c    **** }
+1949:Src/main.c    **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time
+ARM GAS  /tmp/ccdsDELB.s 			page 87
+
+
+1950:Src/main.c    **** {
+1951:Src/main.c    **** 	uint16_t Result;
+1952:Src/main.c    **** //	uint8_t randf;
+1953:Src/main.c    **** 	
+1954:Src/main.c    **** 	randf = 0;
+1955:Src/main.c    **** 	for (uint8_t i = 0; i < 32; i++)
+1956:Src/main.c    **** 	{
+1957:Src/main.c    **** 		randf = ((Timer>>i)&0x0001)^randf;
+1958:Src/main.c    **** 	}
+1959:Src/main.c    **** 	
+1960:Src/main.c    **** 	Result = ((float)(T_LD - T_LD_before))*((float)(1-expf(((float)(Timer_before)-(float)(Timer))/((fl
+1961:Src/main.c    **** 	
+1962:Src/main.c    **** 	return (uint16_t)(Result);
+1963:Src/main.c    **** }*/
+1964:Src/main.c    **** static uint16_t Get_ADC(uint8_t num)
+1965:Src/main.c    **** {
+1966:Src/main.c    **** 	uint16_t OUT;
+1967:Src/main.c    **** 	switch (num)
+1968:Src/main.c    **** 		{
+1969:Src/main.c    **** 			case 0:
+1970:Src/main.c    **** 				HAL_ADC_Start(&hadc1); // Power on
+1971:Src/main.c    **** 			break;
+1972:Src/main.c    **** 			case 1:
+1973:Src/main.c    **** 				HAL_ADC_PollForConversion(&hadc1, 100); // Waiting for conversion
+1974:Src/main.c    ****         OUT = HAL_ADC_GetValue(&hadc1); // Get value adc
+1975:Src/main.c    **** 			break;
+1976:Src/main.c    **** 			case 2:
+1977:Src/main.c    **** 				HAL_ADC_Stop(&hadc1); // Power off
+1978:Src/main.c    **** 			break;
+1979:Src/main.c    **** 			case 3:
+1980:Src/main.c    **** 				HAL_ADC_Start(&hadc3); // Power on
+1981:Src/main.c    **** 			break;
+1982:Src/main.c    **** 			case 4:
+1983:Src/main.c    **** 				HAL_ADC_PollForConversion(&hadc3, 100); // Waiting for conversion
+1984:Src/main.c    ****         OUT = HAL_ADC_GetValue(&hadc3); // Get value adc
+1985:Src/main.c    **** 			break;
+1986:Src/main.c    **** 			case 5:
+1987:Src/main.c    ****         HAL_ADC_Stop(&hadc3); // Power off
+1988:Src/main.c    **** 			break;
+1989:Src/main.c    **** 		}
+1990:Src/main.c    **** 	return OUT;
+1991:Src/main.c    **** }
+1992:Src/main.c    **** uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results, uin
+1993:Src/main.c    **** {			
+ 548              		.loc 2 1993 1 is_stmt 1 view -0
+ 549              		.cfi_startproc
+ 550              		@ args = 0, pretend = 0, frame = 0
+ 551              		@ frame_needed = 0, uses_anonymous_args = 0
+ 552              		@ link register save eliminated.
+ 553              		.loc 2 1993 1 is_stmt 0 view .LVU202
+ 554 0000 30B4     		push	{r4, r5}
+ 555              	.LCFI5:
+ 556              		.cfi_def_cfa_offset 8
+ 557              		.cfi_offset 4, -8
+ 558              		.cfi_offset 5, -4
+1994:Src/main.c    **** 	int e_pid;
+ 559              		.loc 2 1994 2 is_stmt 1 view .LVU203
+ARM GAS  /tmp/ccdsDELB.s 			page 88
+
+
+1995:Src/main.c    **** 	float P_coef_current;//, I_coef_current;
+ 560              		.loc 2 1995 2 view .LVU204
+1996:Src/main.c    **** 	float e_integral;
+ 561              		.loc 2 1996 2 view .LVU205
+1997:Src/main.c    **** 	int x_output;
+ 562              		.loc 2 1997 2 view .LVU206
+1998:Src/main.c    **** 	
+1999:Src/main.c    **** 	e_pid =  (int) LDx_results->LD_CURR_TEMP - (int) LDx_curr_setup->LD_TEMP;
+ 563              		.loc 2 1999 2 view .LVU207
+ 564              		.loc 2 1999 28 is_stmt 0 view .LVU208
+ 565 0002 0B88     		ldrh	r3, [r1]
+ 566              		.loc 2 1999 65 view .LVU209
+ 567 0004 0488     		ldrh	r4, [r0]
+ 568              		.loc 2 1999 8 view .LVU210
+ 569 0006 1B1B     		subs	r3, r3, r4
+ 570              	.LVL34:
+2000:Src/main.c    **** 
+2001:Src/main.c    **** 	e_integral = LDx_results->e_integral;
+ 571              		.loc 2 2001 2 is_stmt 1 view .LVU211
+ 572              		.loc 2 2001 13 is_stmt 0 view .LVU212
+ 573 0008 D1ED017A 		vldr.32	s15, [r1, #4]
+ 574              	.LVL35:
+2002:Src/main.c    **** 	
+2003:Src/main.c    **** 	if((e_pid < 3000) && (e_pid > - 3000)){
+ 575              		.loc 2 2003 2 is_stmt 1 view .LVU213
+ 576              		.loc 2 2003 20 is_stmt 0 view .LVU214
+ 577 000c 03F6B73C 		addw	ip, r3, #2999
+ 578              		.loc 2 2003 4 view .LVU215
+ 579 0010 41F26E74 		movw	r4, #5998
+ 580 0014 A445     		cmp	ip, r4
+ 581 0016 18D8     		bhi	.L16
+2004:Src/main.c    **** 		e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100
+ 582              		.loc 2 2004 3 is_stmt 1 view .LVU216
+ 583              		.loc 2 2004 31 is_stmt 0 view .LVU217
+ 584 0018 90ED027A 		vldr.32	s14, [r0, #8]
+ 585              		.loc 2 2004 47 view .LVU218
+ 586 001c 06EE903A 		vmov	s13, r3	@ int
+ 587 0020 F8EEE66A 		vcvt.f32.s32	s13, s13
+ 588              		.loc 2 2004 45 view .LVU219
+ 589 0024 67EE266A 		vmul.f32	s13, s14, s13
+ 590              		.loc 2 2004 76 view .LVU220
+ 591 0028 284C     		ldr	r4, .L26
+ 592 002a 2468     		ldr	r4, [r4]
+ 593 002c 284D     		ldr	r5, .L26+4
+ 594 002e 2D68     		ldr	r5, [r5]
+ 595 0030 641B     		subs	r4, r4, r5
+ 596 0032 07EE104A 		vmov	s14, r4	@ int
+ 597              		.loc 2 2004 64 view .LVU221
+ 598 0036 B8EE477A 		vcvt.f32.u32	s14, s14
+ 599              		.loc 2 2004 62 view .LVU222
+ 600 003a 26EE877A 		vmul.f32	s14, s13, s14
+ 601              		.loc 2 2004 87 view .LVU223
+ 602 003e 9FED256A 		vldr.32	s12, .L26+8
+ 603 0042 C7EE066A 		vdiv.f32	s13, s14, s12
+ 604              		.loc 2 2004 14 view .LVU224
+ 605 0046 77EEA67A 		vadd.f32	s15, s15, s13
+ 606              	.LVL36:
+ARM GAS  /tmp/ccdsDELB.s 			page 89
+
+
+ 607              	.L16:
+2005:Src/main.c    **** 	}
+2006:Src/main.c    **** 	P_coef_current = LDx_curr_setup->P_coef_temp;
+ 608              		.loc 2 2006 2 is_stmt 1 view .LVU225
+ 609              		.loc 2 2006 17 is_stmt 0 view .LVU226
+ 610 004a D0ED016A 		vldr.32	s13, [r0, #4]
+ 611              	.LVL37:
+2007:Src/main.c    **** 	
+2008:Src/main.c    **** 	if (e_integral > 32000){
+ 612              		.loc 2 2008 2 is_stmt 1 view .LVU227
+ 613              		.loc 2 2008 5 is_stmt 0 view .LVU228
+ 614 004e 9FED227A 		vldr.32	s14, .L26+12
+ 615 0052 F4EEC77A 		vcmpe.f32	s15, s14
+ 616 0056 F1EE10FA 		vmrs	APSR_nzcv, FPSCR
+ 617 005a 09DC     		bgt	.L20
+2009:Src/main.c    **** 			e_integral = 32000;
+2010:Src/main.c    **** 	}
+2011:Src/main.c    **** 	else if (e_integral < - 32000){
+ 618              		.loc 2 2011 7 is_stmt 1 view .LVU229
+ 619              		.loc 2 2011 10 is_stmt 0 view .LVU230
+ 620 005c 9FED1F7A 		vldr.32	s14, .L26+16
+ 621 0060 F4EEC77A 		vcmpe.f32	s15, s14
+ 622 0064 F1EE10FA 		vmrs	APSR_nzcv, FPSCR
+ 623 0068 04D5     		bpl	.L17
+2012:Src/main.c    **** 			e_integral = -32000;
+ 624              		.loc 2 2012 15 view .LVU231
+ 625 006a DFED1C7A 		vldr.32	s15, .L26+16
+ 626              	.LVL38:
+ 627              		.loc 2 2012 15 view .LVU232
+ 628 006e 01E0     		b	.L17
+ 629              	.LVL39:
+ 630              	.L20:
+2009:Src/main.c    **** 			e_integral = 32000;
+ 631              		.loc 2 2009 15 view .LVU233
+ 632 0070 DFED197A 		vldr.32	s15, .L26+12
+ 633              	.LVL40:
+ 634              	.L17:
+2013:Src/main.c    **** 	}
+2014:Src/main.c    **** 	LDx_results->e_integral = e_integral;
+ 635              		.loc 2 2014 2 is_stmt 1 view .LVU234
+ 636              		.loc 2 2014 26 is_stmt 0 view .LVU235
+ 637 0074 C1ED017A 		vstr.32	s15, [r1, #4]
+2015:Src/main.c    **** 	
+2016:Src/main.c    **** 	x_output = 32768 + P_coef_current * e_pid + (int)e_integral;//32768 - P_coef_current * e_pid - (in
+ 638              		.loc 2 2016 2 is_stmt 1 view .LVU236
+ 639              		.loc 2 2016 36 is_stmt 0 view .LVU237
+ 640 0078 07EE103A 		vmov	s14, r3	@ int
+ 641 007c B8EEC77A 		vcvt.f32.s32	s14, s14
+ 642 0080 27EE267A 		vmul.f32	s14, s14, s13
+ 643              		.loc 2 2016 19 view .LVU238
+ 644 0084 DFED166A 		vldr.32	s13, .L26+20
+ 645              	.LVL41:
+ 646              		.loc 2 2016 19 view .LVU239
+ 647 0088 37EE267A 		vadd.f32	s14, s14, s13
+ 648              		.loc 2 2016 46 view .LVU240
+ 649 008c FDEEE77A 		vcvt.s32.f32	s15, s15
+ 650              	.LVL42:
+ARM GAS  /tmp/ccdsDELB.s 			page 90
+
+
+ 651              		.loc 2 2016 44 view .LVU241
+ 652 0090 F8EEE77A 		vcvt.f32.s32	s15, s15
+ 653 0094 77EE877A 		vadd.f32	s15, s15, s14
+ 654              		.loc 2 2016 11 view .LVU242
+ 655 0098 FDEEE77A 		vcvt.s32.f32	s15, s15
+ 656 009c 17EE900A 		vmov	r0, s15	@ int
+ 657              	.LVL43:
+2017:Src/main.c    **** 	
+2018:Src/main.c    **** 	if(x_output < 1000){
+ 658              		.loc 2 2018 2 is_stmt 1 view .LVU243
+ 659              		.loc 2 2018 4 is_stmt 0 view .LVU244
+ 660 00a0 B0F57A7F 		cmp	r0, #1000
+ 661 00a4 06DB     		blt	.L22
+2019:Src/main.c    **** 		x_output = 8800;
+2020:Src/main.c    **** 	}
+2021:Src/main.c    **** 	else if(x_output > 56800){
+ 662              		.loc 2 2021 7 is_stmt 1 view .LVU245
+ 663              		.loc 2 2021 9 is_stmt 0 view .LVU246
+ 664 00a6 4DF6E053 		movw	r3, #56800
+ 665              	.LVL44:
+ 666              		.loc 2 2021 9 view .LVU247
+ 667 00aa 9842     		cmp	r0, r3
+ 668 00ac 04DD     		ble	.L18
+2022:Src/main.c    **** 		x_output = 56800;
+ 669              		.loc 2 2022 12 view .LVU248
+ 670 00ae 4DF6E050 		movw	r0, #56800
+ 671              	.LVL45:
+ 672              		.loc 2 2022 12 view .LVU249
+ 673 00b2 01E0     		b	.L18
+ 674              	.LVL46:
+ 675              	.L22:
+2019:Src/main.c    **** 		x_output = 8800;
+ 676              		.loc 2 2019 12 view .LVU250
+ 677 00b4 42F26020 		movw	r0, #8800
+ 678              	.LVL47:
+ 679              	.L18:
+2023:Src/main.c    **** 	}
+2024:Src/main.c    **** 	
+2025:Src/main.c    **** 	if (num==2)
+ 680              		.loc 2 2025 2 is_stmt 1 view .LVU251
+ 681              		.loc 2 2025 5 is_stmt 0 view .LVU252
+ 682 00b8 022A     		cmp	r2, #2
+ 683 00ba 02D0     		beq	.L25
+ 684              	.LVL48:
+ 685              	.L19:
+2026:Src/main.c    **** 		TO7_PID = TO7;//Save current time only on 2nd laser
+2027:Src/main.c    **** 	
+2028:Src/main.c    **** 	return (uint16_t)x_output;
+ 686              		.loc 2 2028 2 is_stmt 1 view .LVU253
+2029:Src/main.c    **** }
+ 687              		.loc 2 2029 1 is_stmt 0 view .LVU254
+ 688 00bc 80B2     		uxth	r0, r0
+ 689              	.LVL49:
+ 690              		.loc 2 2029 1 view .LVU255
+ 691 00be 30BC     		pop	{r4, r5}
+ 692              	.LCFI6:
+ 693              		.cfi_remember_state
+ARM GAS  /tmp/ccdsDELB.s 			page 91
+
+
+ 694              		.cfi_restore 5
+ 695              		.cfi_restore 4
+ 696              		.cfi_def_cfa_offset 0
+ 697 00c0 7047     		bx	lr
+ 698              	.LVL50:
+ 699              	.L25:
+ 700              	.LCFI7:
+ 701              		.cfi_restore_state
+2026:Src/main.c    **** 		TO7_PID = TO7;//Save current time only on 2nd laser
+ 702              		.loc 2 2026 3 is_stmt 1 view .LVU256
+2026:Src/main.c    **** 		TO7_PID = TO7;//Save current time only on 2nd laser
+ 703              		.loc 2 2026 11 is_stmt 0 view .LVU257
+ 704 00c2 024B     		ldr	r3, .L26
+ 705 00c4 1A68     		ldr	r2, [r3]
+ 706              	.LVL51:
+2026:Src/main.c    **** 		TO7_PID = TO7;//Save current time only on 2nd laser
+ 707              		.loc 2 2026 11 view .LVU258
+ 708 00c6 024B     		ldr	r3, .L26+4
+ 709 00c8 1A60     		str	r2, [r3]
+ 710 00ca F7E7     		b	.L19
+ 711              	.L27:
+ 712              		.align	2
+ 713              	.L26:
+ 714 00cc 00000000 		.word	.LANCHOR3
+ 715 00d0 00000000 		.word	.LANCHOR4
+ 716 00d4 0000C842 		.word	1120403456
+ 717 00d8 0000FA46 		.word	1190789120
+ 718 00dc 0000FAC6 		.word	-956694528
+ 719 00e0 00000047 		.word	1191182336
+ 720              		.cfi_endproc
+ 721              	.LFE1209:
+ 723              		.section	.text.Set_LTEC,"ax",%progbits
+ 724              		.align	1
+ 725              		.syntax unified
+ 726              		.thumb
+ 727              		.thumb_func
+ 728              		.fpu fpv5-d16
+ 730              	Set_LTEC:
+ 731              	.LVL52:
+ 732              	.LFB1206:
+1795:Src/main.c    **** 	uint32_t tmp32;
+ 733              		.loc 2 1795 1 is_stmt 1 view -0
+ 734              		.cfi_startproc
+ 735              		@ args = 0, pretend = 0, frame = 0
+ 736              		@ frame_needed = 0, uses_anonymous_args = 0
+1795:Src/main.c    **** 	uint32_t tmp32;
+ 737              		.loc 2 1795 1 is_stmt 0 view .LVU260
+ 738 0000 38B5     		push	{r3, r4, r5, lr}
+ 739              	.LCFI8:
+ 740              		.cfi_def_cfa_offset 16
+ 741              		.cfi_offset 3, -16
+ 742              		.cfi_offset 4, -12
+ 743              		.cfi_offset 5, -8
+ 744              		.cfi_offset 14, -4
+ 745 0002 0C46     		mov	r4, r1
+1796:Src/main.c    **** 	switch (num)
+ 746              		.loc 2 1796 2 is_stmt 1 view .LVU261
+ARM GAS  /tmp/ccdsDELB.s 			page 92
+
+
+1797:Src/main.c    **** 	{
+ 747              		.loc 2 1797 2 view .LVU262
+ 748 0004 0138     		subs	r0, r0, #1
+ 749              	.LVL53:
+1797:Src/main.c    **** 	{
+ 750              		.loc 2 1797 2 is_stmt 0 view .LVU263
+ 751 0006 0328     		cmp	r0, #3
+ 752 0008 23D8     		bhi	.L29
+ 753 000a DFE800F0 		tbb	[pc, r0]
+ 754              	.L31:
+ 755 000e 02       		.byte	(.L34-.L31)/2
+ 756 000f 3B       		.byte	(.L33-.L31)/2
+ 757 0010 5B       		.byte	(.L32-.L31)/2
+ 758 0011 7C       		.byte	(.L30-.L31)/2
+ 759              		.p2align 1
+ 760              	.L34:
+1800:Src/main.c    **** 			//tmp32=0;
+ 761              		.loc 2 1800 4 is_stmt 1 view .LVU264
+ 762 0012 0022     		movs	r2, #0
+ 763 0014 4FF48041 		mov	r1, #16384
+ 764              	.LVL54:
+1800:Src/main.c    **** 			//tmp32=0;
+ 765              		.loc 2 1800 4 is_stmt 0 view .LVU265
+ 766 0018 4B48     		ldr	r0, .L60
+ 767 001a FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 768              	.LVL55:
+1803:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+ 769              		.loc 2 1803 4 is_stmt 1 view .LVU266
+1804:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 770              		.loc 2 1804 4 view .LVU267
+1803:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+ 771              		.loc 2 1803 10 is_stmt 0 view .LVU268
+ 772 001e 0022     		movs	r2, #0
+ 773              	.LVL56:
+ 774              	.L35:
+1804:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 775              		.loc 2 1804 9 is_stmt 1 discriminator 1 view .LVU269
+ 776              	.LBB301:
+ 777              	.LBI301:
+ 778              		.file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @file    stm32f7xx_ll_spi.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief   Header file of SPI LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 93
+
+
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifndef STM32F7xx_LL_SPI_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define STM32F7xx_LL_SPI_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defin
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL SPI
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER)
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  SPI Init structures definition
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** typedef struct
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mod
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_M
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t DataWidth;               /*!< Specifies the SPI data width.
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 94
+
+
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (N
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used 
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPR
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          @note The communication clock is derived from the master c
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCUL
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter must be a number between Min_Data = 0x00 an
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } LL_SPI_InitTypeDef;
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag 
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag     
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag           
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag          
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag             
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format erro
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 95
+
+
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty inter
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable   
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_MODE Operation Mode
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuratio
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as de
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                  
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PHASE Clock Phase
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition i
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< Baud
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< Baud
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< Baud
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< Baud
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< Baud
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< Baud
+ARM GAS  /tmp/ccdsDELB.s 			page 96
+
+
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< Baud
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< Baud
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/recei
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/recei
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mo
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mod
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed inter
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in I
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in O
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                           
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                          
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                           
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                           
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)            
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                          
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                           
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                           
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)            
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                           
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)            
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)            
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER)
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 97
+
+
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled 
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated i
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated i
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception em
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception fu
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 98
+
+
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Write a value in SPI register
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __INSTANCE__ SPI Instance
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __REG__ Register to be written
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __VALUE__ Value to be written in the register
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Read a value in SPI register
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __INSTANCE__ SPI Instance
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __REG__ Register to be read
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Register value
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Configuration Configuration
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable SPI peripheral
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          SPE           LL_SPI_Enable
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 99
+
+
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable SPI peripheral
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          SPE           LL_SPI_Disable
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if SPI peripheral is enabled
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set SPI operation mode to Master or Slave
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing.
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          SSI           LL_SPI_SetMode
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  Mode This parameter can be one of the following values:
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MODE_MASTER
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MODE_SLAVE
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get SPI operation mode (Master or Slave)
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          SSI           LL_SPI_GetMode
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MODE_MASTER
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MODE_SLAVE
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 100
+
+
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set serial protocol used
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          FRF           LL_SPI_SetStandard
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  Standard This parameter can be one of the following values:
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PROTOCOL_TI
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get serial protocol used
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          FRF           LL_SPI_GetStandard
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PROTOCOL_TI
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set clock phase
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing.
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         This bit is not used in SPI TI mode.
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  ClockPhase This parameter can be one of the following values:
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PHASE_1EDGE
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PHASE_2EDGE
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get clock phase
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PHASE_1EDGE
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PHASE_2EDGE
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 101
+
+
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set clock polarity
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing.
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         This bit is not used in SPI TI mode.
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  ClockPolarity This parameter can be one of the following values:
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_POLARITY_LOW
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_POLARITY_HIGH
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get clock polarity
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_POLARITY_LOW
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_POLARITY_HIGH
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set baud rate prescaler
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Pr
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  BaudRate This parameter can be one of the following values:
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get baud rate prescaler
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ARM GAS  /tmp/ccdsDELB.s 			page 102
+
+
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set transfer bit order
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing. This bit is not used in S
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  BitOrder This parameter can be one of the following values:
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_LSB_FIRST
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MSB_FIRST
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get transfer bit order
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_LSB_FIRST
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MSB_FIRST
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set transfer direction mode
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   For Half-Duplex mode, Rx Direction is set by default.
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-D
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          BIDIOE        LL_SPI_SetTransferDirection
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  TransferDirection This parameter can be one of the following values:
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_FULL_DUPLEX
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_SIMPLEX_RX
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+ARM GAS  /tmp/ccdsDELB.s 			page 103
+
+
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get transfer direction mode
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          BIDIOE        LL_SPI_GetTransferDirection
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_FULL_DUPLEX
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_SIMPLEX_RX
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set frame data width
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          DS            LL_SPI_SetDataWidth
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  DataWidth This parameter can be one of the following values:
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get frame data width
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          DS            LL_SPI_GetDataWidth
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+ARM GAS  /tmp/ccdsDELB.s 			page 104
+
+
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set threshold of RXFIFO that triggers an RXNE event
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  Threshold This parameter can be one of the following values:
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get threshold of RXFIFO that triggers an RXNE event
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_CRC_Management CRC Management
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable CRC
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 105
+
+
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable CRC
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if CRC is enabled
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set CRC Length
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  CRCLength This parameter can be one of the following values:
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_CRC_8BIT
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_CRC_16BIT
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get CRC Length
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_CRC_8BIT
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_CRC_16BIT
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set CRCNext to transfer CRC on the line
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
+ARM GAS  /tmp/ccdsDELB.s 			page 106
+
+
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set polynomial for CRC calculation
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get polynomial for CRC calculation
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_REG(SPIx->CRCPR));
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get Rx CRC
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_REG(SPIx->RXCRCR));
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get Tx CRC
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_REG(SPIx->TXCRCR));
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 107
+
+
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set NSS mode
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  NSS This parameter can be one of the following values:
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_SOFT
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_HARD_INPUT
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get NSS mode
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_SOFT
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_HARD_INPUT
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (Ssm | Ssoe);
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable NSS pulse management
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing. This bit is not used in S
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable NSS pulse management
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing. This bit is not used in S
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ARM GAS  /tmp/ccdsDELB.s 			page 108
+
+
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if NSS pulse is enabled
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing. This bit is not used in S
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if Rx buffer is not empty
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if Tx buffer is empty
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+ 779              		.loc 4 916 26 discriminator 1 view .LVU270
+ 780              	.LBB302:
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
+ 781              		.loc 4 918 3 discriminator 1 view .LVU271
+ 782              		.loc 4 918 12 is_stmt 0 discriminator 1 view .LVU272
+ 783 0020 4A4B     		ldr	r3, .L60+4
+ 784 0022 9B68     		ldr	r3, [r3, #8]
+ 785              		.loc 4 918 66 discriminator 1 view .LVU273
+ 786 0024 13F0020F 		tst	r3, #2
+ 787 0028 04D1     		bne	.L36
+ 788              	.LVL57:
+ 789              		.loc 4 918 66 discriminator 1 view .LVU274
+ARM GAS  /tmp/ccdsDELB.s 			page 109
+
+
+ 790              	.LBE302:
+ 791              	.LBE301:
+1804:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 792              		.loc 2 1804 42 view .LVU275
+ 793 002a B2F5FA7F 		cmp	r2, #500
+ 794 002e 01D8     		bhi	.L36
+1804:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 795              		.loc 2 1804 59 is_stmt 1 discriminator 3 view .LVU276
+1804:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 796              		.loc 2 1804 64 is_stmt 0 discriminator 3 view .LVU277
+ 797 0030 0132     		adds	r2, r2, #1
+ 798              	.LVL58:
+1804:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 799              		.loc 2 1804 64 discriminator 3 view .LVU278
+ 800 0032 F5E7     		b	.L35
+ 801              	.L36:
+1805:Src/main.c    **** 			tmp32 = 0;
+ 802              		.loc 2 1805 4 is_stmt 1 view .LVU279
+ 803              	.LVL59:
+ 804              	.LBB303:
+ 805              	.LBI303:
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get CRC error flag
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get mode fault error flag
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get overrun error flag
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 110
+
+
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get busy flag
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   The BSY flag is cleared under any one of the following conditions:
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * -When the SPI is correctly disabled
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * -When a fault is detected in Master mode (MODF bit set to 1)
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * -In Master mode, when it finishes a data transmission and no new data is ready to be
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * sent
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * each data transfer.
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get frame format error flag
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get FIFO reception Level
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_EMPTY
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_FULL
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get FIFO Transmission Level
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_TX_FIFO_EMPTY
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_TX_FIFO_FULL
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 111
+
+
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Clear CRC error flag
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Clear mode fault error flag
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   Clearing this flag is done by a read access to the SPIx_SR
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         register followed by a write access to the SPIx_CR1 register
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   __IO uint32_t tmpreg_sr;
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   tmpreg_sr = SPIx->SR;
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   (void) tmpreg_sr;
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Clear overrun error flag
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   Clearing this flag is done by a read access to the SPIx_DR
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         register followed by a read access to the SPIx_SR register
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   __IO uint32_t tmpreg;
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   tmpreg = SPIx->DR;
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   (void) tmpreg;
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   tmpreg = SPIx->SR;
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   (void) tmpreg;
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Clear frame format error flag
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   Clearing this flag is done by reading SPIx_SR register
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   __IO uint32_t tmpreg;
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   tmpreg = SPIx->SR;
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   (void) tmpreg;
+ARM GAS  /tmp/ccdsDELB.s 			page 112
+
+
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable error interrupt
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable Rx buffer not empty interrupt
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable Tx buffer empty interrupt
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable error interrupt
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 113
+
+
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable Rx buffer not empty interrupt
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable Tx buffer empty interrupt
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if error interrupt is enabled
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if Rx buffer not empty interrupt is enabled
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if Tx buffer empty interrupt
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 114
+
+
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DMA_Management DMA Management
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable DMA Rx
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable DMA Rx
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if DMA Rx is enabled
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable DMA Tx
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable DMA Tx
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 115
+
+
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if DMA Tx is enabled
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set parity of  Last DMA reception
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  Parity This parameter can be one of the following values:
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_ODD
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get parity configuration for  Last DMA reception
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_ODD
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set parity of  Last DMA transmission
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  Parity This parameter can be one of the following values:
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_ODD
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get parity configuration for Last DMA transmission
+ARM GAS  /tmp/ccdsDELB.s 			page 116
+
+
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_ODD
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get the data register address used for DMA transfer
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Address of data register
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t) &(SPIx->DR);
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DATA_Management DATA Management
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Read 8-Bits in the data register
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll DR           DR            LL_SPI_ReceiveData8
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (*((__IO uint8_t *)&SPIx->DR));
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Read 16-Bits in the data register
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll DR           DR            LL_SPI_ReceiveData16
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint16_t)(READ_REG(SPIx->DR));
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Write 8-Bits in the data register
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll DR           DR            LL_SPI_TransmitData8
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
+ARM GAS  /tmp/ccdsDELB.s 			page 117
+
+
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__)
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *spidr = TxData;
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #else
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *((__IO uint8_t *)&SPIx->DR) = TxData;
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* __GNUC__ */
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Write 16-Bits in the data register
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll DR           DR            LL_SPI_TransmitData16
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+ 806              		.loc 4 1373 22 view .LVU280
+ 807              	.LBB304:
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__)
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+ 808              		.loc 4 1376 3 view .LVU281
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *spidr = TxData;
+ 809              		.loc 4 1377 3 view .LVU282
+ 810              		.loc 4 1377 10 is_stmt 0 view .LVU283
+ 811 0034 454B     		ldr	r3, .L60+4
+ 812 0036 9C81     		strh	r4, [r3, #12]	@ movhi
+ 813              	.LVL60:
+ 814              		.loc 4 1377 10 view .LVU284
+ 815              	.LBE304:
+ 816              	.LBE303:
+1806:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+ 817              		.loc 2 1806 4 is_stmt 1 view .LVU285
+1807:Src/main.c    **** 			(void) SPI2->DR;
+ 818              		.loc 2 1807 4 view .LVU286
+1806:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+ 819              		.loc 2 1806 10 is_stmt 0 view .LVU287
+ 820 0038 0022     		movs	r2, #0
+ 821              	.LVL61:
+ 822              	.L38:
+1807:Src/main.c    **** 			(void) SPI2->DR;
+ 823              		.loc 2 1807 9 is_stmt 1 discriminator 1 view .LVU288
+ 824              	.LBB305:
+ 825              	.LBI305:
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 826              		.loc 4 905 26 discriminator 1 view .LVU289
+ 827              	.LBB306:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 828              		.loc 4 907 3 discriminator 1 view .LVU290
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 829              		.loc 4 907 12 is_stmt 0 discriminator 1 view .LVU291
+ 830 003a 444B     		ldr	r3, .L60+4
+ 831 003c 9B68     		ldr	r3, [r3, #8]
+ARM GAS  /tmp/ccdsDELB.s 			page 118
+
+
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 832              		.loc 4 907 68 discriminator 1 view .LVU292
+ 833 003e 13F0010F 		tst	r3, #1
+ 834 0042 04D1     		bne	.L39
+ 835              	.LVL62:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 836              		.loc 4 907 68 discriminator 1 view .LVU293
+ 837              	.LBE306:
+ 838              	.LBE305:
+1807:Src/main.c    **** 			(void) SPI2->DR;
+ 839              		.loc 2 1807 43 view .LVU294
+ 840 0044 B2F5FA7F 		cmp	r2, #500
+ 841 0048 01D8     		bhi	.L39
+1807:Src/main.c    **** 			(void) SPI2->DR;
+ 842              		.loc 2 1807 60 is_stmt 1 discriminator 3 view .LVU295
+1807:Src/main.c    **** 			(void) SPI2->DR;
+ 843              		.loc 2 1807 65 is_stmt 0 discriminator 3 view .LVU296
+ 844 004a 0132     		adds	r2, r2, #1
+ 845              	.LVL63:
+1807:Src/main.c    **** 			(void) SPI2->DR;
+ 846              		.loc 2 1807 65 discriminator 3 view .LVU297
+ 847 004c F5E7     		b	.L38
+ 848              	.L39:
+1808:Src/main.c    **** 		break;
+ 849              		.loc 2 1808 4 is_stmt 1 view .LVU298
+ 850 004e 3F4B     		ldr	r3, .L60+4
+ 851 0050 DB68     		ldr	r3, [r3, #12]
+1809:Src/main.c    **** 		case 2:
+ 852              		.loc 2 1809 3 view .LVU299
+ 853              	.LVL64:
+ 854              	.L29:
+1844:Src/main.c    **** 	HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2
+ 855              		.loc 2 1844 2 view .LVU300
+ 856 0052 3D4D     		ldr	r5, .L60
+ 857 0054 0122     		movs	r2, #1
+ 858 0056 4FF48041 		mov	r1, #16384
+ 859 005a 2846     		mov	r0, r5
+ 860 005c FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 861              	.LVL65:
+1845:Src/main.c    **** 	HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1
+ 862              		.loc 2 1845 2 view .LVU301
+ 863 0060 3B4C     		ldr	r4, .L60+8
+ 864 0062 0122     		movs	r2, #1
+ 865 0064 4021     		movs	r1, #64
+ 866 0066 2046     		mov	r0, r4
+ 867 0068 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 868              	.LVL66:
+1846:Src/main.c    **** 	HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2
+ 869              		.loc 2 1846 2 view .LVU302
+ 870 006c 0122     		movs	r2, #1
+ 871 006e 4FF48051 		mov	r1, #4096
+ 872 0072 2846     		mov	r0, r5
+ 873 0074 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 874              	.LVL67:
+1847:Src/main.c    **** }
+ 875              		.loc 2 1847 2 view .LVU303
+ 876 0078 0122     		movs	r2, #1
+ARM GAS  /tmp/ccdsDELB.s 			page 119
+
+
+ 877 007a 1021     		movs	r1, #16
+ 878 007c 2046     		mov	r0, r4
+ 879 007e FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 880              	.LVL68:
+1848:Src/main.c    **** static uint16_t MPhD_T(uint8_t num)
+ 881              		.loc 2 1848 1 is_stmt 0 view .LVU304
+ 882 0082 38BD     		pop	{r3, r4, r5, pc}
+ 883              	.LVL69:
+ 884              	.L33:
+1811:Src/main.c    **** 			//tmp32=0;
+ 885              		.loc 2 1811 4 is_stmt 1 view .LVU305
+ 886 0084 0022     		movs	r2, #0
+ 887 0086 4021     		movs	r1, #64
+ 888              	.LVL70:
+1811:Src/main.c    **** 			//tmp32=0;
+ 889              		.loc 2 1811 4 is_stmt 0 view .LVU306
+ 890 0088 3148     		ldr	r0, .L60+8
+ 891 008a FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 892              	.LVL71:
+1814:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+ 893              		.loc 2 1814 4 is_stmt 1 view .LVU307
+1815:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ 894              		.loc 2 1815 4 view .LVU308
+1814:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+ 895              		.loc 2 1814 10 is_stmt 0 view .LVU309
+ 896 008e 0022     		movs	r2, #0
+ 897              	.LVL72:
+ 898              	.L41:
+1815:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ 899              		.loc 2 1815 9 is_stmt 1 discriminator 1 view .LVU310
+ 900              	.LBB307:
+ 901              	.LBI307:
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 902              		.loc 4 916 26 discriminator 1 view .LVU311
+ 903              	.LBB308:
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 904              		.loc 4 918 3 discriminator 1 view .LVU312
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 905              		.loc 4 918 12 is_stmt 0 discriminator 1 view .LVU313
+ 906 0090 304B     		ldr	r3, .L60+12
+ 907 0092 9B68     		ldr	r3, [r3, #8]
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 908              		.loc 4 918 66 discriminator 1 view .LVU314
+ 909 0094 13F0020F 		tst	r3, #2
+ 910 0098 04D1     		bne	.L42
+ 911              	.LVL73:
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 912              		.loc 4 918 66 discriminator 1 view .LVU315
+ 913              	.LBE308:
+ 914              	.LBE307:
+1815:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ 915              		.loc 2 1815 42 view .LVU316
+ 916 009a B2F5FA7F 		cmp	r2, #500
+ 917 009e 01D8     		bhi	.L42
+1815:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ 918              		.loc 2 1815 59 is_stmt 1 discriminator 3 view .LVU317
+1815:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ARM GAS  /tmp/ccdsDELB.s 			page 120
+
+
+ 919              		.loc 2 1815 64 is_stmt 0 discriminator 3 view .LVU318
+ 920 00a0 0132     		adds	r2, r2, #1
+ 921              	.LVL74:
+1815:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ 922              		.loc 2 1815 64 discriminator 3 view .LVU319
+ 923 00a2 F5E7     		b	.L41
+ 924              	.L42:
+1816:Src/main.c    **** 			tmp32 = 0;
+ 925              		.loc 2 1816 4 is_stmt 1 view .LVU320
+ 926              	.LVL75:
+ 927              	.LBB309:
+ 928              	.LBI309:
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 929              		.loc 4 1373 22 view .LVU321
+ 930              	.LBB310:
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *spidr = TxData;
+ 931              		.loc 4 1376 3 view .LVU322
+ 932              		.loc 4 1377 3 view .LVU323
+ 933              		.loc 4 1377 10 is_stmt 0 view .LVU324
+ 934 00a4 2B4B     		ldr	r3, .L60+12
+ 935 00a6 9C81     		strh	r4, [r3, #12]	@ movhi
+ 936              	.LVL76:
+ 937              		.loc 4 1377 10 view .LVU325
+ 938              	.LBE310:
+ 939              	.LBE309:
+1817:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+ 940              		.loc 2 1817 4 is_stmt 1 view .LVU326
+1818:Src/main.c    **** 			(void) SPI6->DR;
+ 941              		.loc 2 1818 4 view .LVU327
+1817:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+ 942              		.loc 2 1817 10 is_stmt 0 view .LVU328
+ 943 00a8 0022     		movs	r2, #0
+ 944              	.LVL77:
+ 945              	.L44:
+1818:Src/main.c    **** 			(void) SPI6->DR;
+ 946              		.loc 2 1818 9 is_stmt 1 discriminator 1 view .LVU329
+ 947              	.LBB311:
+ 948              	.LBI311:
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 949              		.loc 4 905 26 discriminator 1 view .LVU330
+ 950              	.LBB312:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 951              		.loc 4 907 3 discriminator 1 view .LVU331
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 952              		.loc 4 907 12 is_stmt 0 discriminator 1 view .LVU332
+ 953 00aa 2A4B     		ldr	r3, .L60+12
+ 954 00ac 9B68     		ldr	r3, [r3, #8]
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 955              		.loc 4 907 68 discriminator 1 view .LVU333
+ 956 00ae 13F0010F 		tst	r3, #1
+ 957 00b2 04D1     		bne	.L45
+ 958              	.LVL78:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 959              		.loc 4 907 68 discriminator 1 view .LVU334
+ 960              	.LBE312:
+ 961              	.LBE311:
+1818:Src/main.c    **** 			(void) SPI6->DR;
+ARM GAS  /tmp/ccdsDELB.s 			page 121
+
+
+ 962              		.loc 2 1818 43 view .LVU335
+ 963 00b4 B2F5FA7F 		cmp	r2, #500
+ 964 00b8 01D8     		bhi	.L45
+1818:Src/main.c    **** 			(void) SPI6->DR;
+ 965              		.loc 2 1818 60 is_stmt 1 discriminator 3 view .LVU336
+1818:Src/main.c    **** 			(void) SPI6->DR;
+ 966              		.loc 2 1818 65 is_stmt 0 discriminator 3 view .LVU337
+ 967 00ba 0132     		adds	r2, r2, #1
+ 968              	.LVL79:
+1818:Src/main.c    **** 			(void) SPI6->DR;
+ 969              		.loc 2 1818 65 discriminator 3 view .LVU338
+ 970 00bc F5E7     		b	.L44
+ 971              	.L45:
+1819:Src/main.c    **** 		break;
+ 972              		.loc 2 1819 4 is_stmt 1 view .LVU339
+ 973 00be 254B     		ldr	r3, .L60+12
+ 974 00c0 DB68     		ldr	r3, [r3, #12]
+1820:Src/main.c    **** 		case 3:
+ 975              		.loc 2 1820 3 view .LVU340
+ 976 00c2 C6E7     		b	.L29
+ 977              	.LVL80:
+ 978              	.L32:
+1822:Src/main.c    **** 			//tmp32=0;
+ 979              		.loc 2 1822 4 view .LVU341
+ 980 00c4 0022     		movs	r2, #0
+ 981 00c6 4FF48051 		mov	r1, #4096
+ 982              	.LVL81:
+1822:Src/main.c    **** 			//tmp32=0;
+ 983              		.loc 2 1822 4 is_stmt 0 view .LVU342
+ 984 00ca 1F48     		ldr	r0, .L60
+ 985 00cc FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 986              	.LVL82:
+1825:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+ 987              		.loc 2 1825 4 is_stmt 1 view .LVU343
+1826:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 988              		.loc 2 1826 4 view .LVU344
+1825:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+ 989              		.loc 2 1825 10 is_stmt 0 view .LVU345
+ 990 00d0 0022     		movs	r2, #0
+ 991              	.LVL83:
+ 992              	.L47:
+1826:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 993              		.loc 2 1826 9 is_stmt 1 discriminator 1 view .LVU346
+ 994              	.LBB313:
+ 995              	.LBI313:
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 996              		.loc 4 916 26 discriminator 1 view .LVU347
+ 997              	.LBB314:
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 998              		.loc 4 918 3 discriminator 1 view .LVU348
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 999              		.loc 4 918 12 is_stmt 0 discriminator 1 view .LVU349
+ 1000 00d2 1E4B     		ldr	r3, .L60+4
+ 1001 00d4 9B68     		ldr	r3, [r3, #8]
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1002              		.loc 4 918 66 discriminator 1 view .LVU350
+ 1003 00d6 13F0020F 		tst	r3, #2
+ARM GAS  /tmp/ccdsDELB.s 			page 122
+
+
+ 1004 00da 04D1     		bne	.L48
+ 1005              	.LVL84:
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1006              		.loc 4 918 66 discriminator 1 view .LVU351
+ 1007              	.LBE314:
+ 1008              	.LBE313:
+1826:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 1009              		.loc 2 1826 42 view .LVU352
+ 1010 00dc B2F5FA7F 		cmp	r2, #500
+ 1011 00e0 01D8     		bhi	.L48
+1826:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 1012              		.loc 2 1826 59 is_stmt 1 discriminator 3 view .LVU353
+1826:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 1013              		.loc 2 1826 64 is_stmt 0 discriminator 3 view .LVU354
+ 1014 00e2 0132     		adds	r2, r2, #1
+ 1015              	.LVL85:
+1826:Src/main.c    **** 			LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC
+ 1016              		.loc 2 1826 64 discriminator 3 view .LVU355
+ 1017 00e4 F5E7     		b	.L47
+ 1018              	.L48:
+1827:Src/main.c    **** 			tmp32 = 0;
+ 1019              		.loc 2 1827 4 is_stmt 1 view .LVU356
+ 1020              	.LVL86:
+ 1021              	.LBB315:
+ 1022              	.LBI315:
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1023              		.loc 4 1373 22 view .LVU357
+ 1024              	.LBB316:
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *spidr = TxData;
+ 1025              		.loc 4 1376 3 view .LVU358
+ 1026              		.loc 4 1377 3 view .LVU359
+ 1027              		.loc 4 1377 10 is_stmt 0 view .LVU360
+ 1028 00e6 194B     		ldr	r3, .L60+4
+ 1029 00e8 9C81     		strh	r4, [r3, #12]	@ movhi
+ 1030              	.LVL87:
+ 1031              		.loc 4 1377 10 view .LVU361
+ 1032              	.LBE316:
+ 1033              	.LBE315:
+1828:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+ 1034              		.loc 2 1828 4 is_stmt 1 view .LVU362
+1829:Src/main.c    **** 			(void) SPI2->DR;
+ 1035              		.loc 2 1829 4 view .LVU363
+1828:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+ 1036              		.loc 2 1828 10 is_stmt 0 view .LVU364
+ 1037 00ea 0022     		movs	r2, #0
+ 1038              	.LVL88:
+ 1039              	.L50:
+1829:Src/main.c    **** 			(void) SPI2->DR;
+ 1040              		.loc 2 1829 9 is_stmt 1 discriminator 1 view .LVU365
+ 1041              	.LBB317:
+ 1042              	.LBI317:
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1043              		.loc 4 905 26 discriminator 1 view .LVU366
+ 1044              	.LBB318:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1045              		.loc 4 907 3 discriminator 1 view .LVU367
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 123
+
+
+ 1046              		.loc 4 907 12 is_stmt 0 discriminator 1 view .LVU368
+ 1047 00ec 174B     		ldr	r3, .L60+4
+ 1048 00ee 9B68     		ldr	r3, [r3, #8]
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1049              		.loc 4 907 68 discriminator 1 view .LVU369
+ 1050 00f0 13F0010F 		tst	r3, #1
+ 1051 00f4 04D1     		bne	.L51
+ 1052              	.LVL89:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1053              		.loc 4 907 68 discriminator 1 view .LVU370
+ 1054              	.LBE318:
+ 1055              	.LBE317:
+1829:Src/main.c    **** 			(void) SPI2->DR;
+ 1056              		.loc 2 1829 43 view .LVU371
+ 1057 00f6 B2F5FA7F 		cmp	r2, #500
+ 1058 00fa 01D8     		bhi	.L51
+1829:Src/main.c    **** 			(void) SPI2->DR;
+ 1059              		.loc 2 1829 60 is_stmt 1 discriminator 3 view .LVU372
+1829:Src/main.c    **** 			(void) SPI2->DR;
+ 1060              		.loc 2 1829 65 is_stmt 0 discriminator 3 view .LVU373
+ 1061 00fc 0132     		adds	r2, r2, #1
+ 1062              	.LVL90:
+1829:Src/main.c    **** 			(void) SPI2->DR;
+ 1063              		.loc 2 1829 65 discriminator 3 view .LVU374
+ 1064 00fe F5E7     		b	.L50
+ 1065              	.L51:
+1830:Src/main.c    **** 		break;
+ 1066              		.loc 2 1830 4 is_stmt 1 view .LVU375
+ 1067 0100 124B     		ldr	r3, .L60+4
+ 1068 0102 DB68     		ldr	r3, [r3, #12]
+1831:Src/main.c    **** 		case 4:
+ 1069              		.loc 2 1831 3 view .LVU376
+ 1070 0104 A5E7     		b	.L29
+ 1071              	.LVL91:
+ 1072              	.L30:
+1833:Src/main.c    **** 			//tmp32=0;
+ 1073              		.loc 2 1833 4 view .LVU377
+ 1074 0106 0022     		movs	r2, #0
+ 1075 0108 1021     		movs	r1, #16
+ 1076              	.LVL92:
+1833:Src/main.c    **** 			//tmp32=0;
+ 1077              		.loc 2 1833 4 is_stmt 0 view .LVU378
+ 1078 010a 1148     		ldr	r0, .L60+8
+ 1079 010c FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1080              	.LVL93:
+1836:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+ 1081              		.loc 2 1836 4 is_stmt 1 view .LVU379
+1837:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ 1082              		.loc 2 1837 4 view .LVU380
+1836:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi
+ 1083              		.loc 2 1836 10 is_stmt 0 view .LVU381
+ 1084 0110 0022     		movs	r2, #0
+ 1085              	.LVL94:
+ 1086              	.L53:
+1837:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ 1087              		.loc 2 1837 9 is_stmt 1 discriminator 1 view .LVU382
+ 1088              	.LBB319:
+ARM GAS  /tmp/ccdsDELB.s 			page 124
+
+
+ 1089              	.LBI319:
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1090              		.loc 4 916 26 discriminator 1 view .LVU383
+ 1091              	.LBB320:
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1092              		.loc 4 918 3 discriminator 1 view .LVU384
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1093              		.loc 4 918 12 is_stmt 0 discriminator 1 view .LVU385
+ 1094 0112 104B     		ldr	r3, .L60+12
+ 1095 0114 9B68     		ldr	r3, [r3, #8]
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1096              		.loc 4 918 66 discriminator 1 view .LVU386
+ 1097 0116 13F0020F 		tst	r3, #2
+ 1098 011a 04D1     		bne	.L54
+ 1099              	.LVL95:
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1100              		.loc 4 918 66 discriminator 1 view .LVU387
+ 1101              	.LBE320:
+ 1102              	.LBE319:
+1837:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ 1103              		.loc 2 1837 42 view .LVU388
+ 1104 011c B2F5FA7F 		cmp	r2, #500
+ 1105 0120 01D8     		bhi	.L54
+1837:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ 1106              		.loc 2 1837 59 is_stmt 1 discriminator 3 view .LVU389
+1837:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ 1107              		.loc 2 1837 64 is_stmt 0 discriminator 3 view .LVU390
+ 1108 0122 0132     		adds	r2, r2, #1
+ 1109              	.LVL96:
+1837:Src/main.c    **** 			LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC
+ 1110              		.loc 2 1837 64 discriminator 3 view .LVU391
+ 1111 0124 F5E7     		b	.L53
+ 1112              	.L54:
+1838:Src/main.c    **** 			tmp32 = 0;
+ 1113              		.loc 2 1838 4 is_stmt 1 view .LVU392
+ 1114              	.LVL97:
+ 1115              	.LBB321:
+ 1116              	.LBI321:
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1117              		.loc 4 1373 22 view .LVU393
+ 1118              	.LBB322:
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *spidr = TxData;
+ 1119              		.loc 4 1376 3 view .LVU394
+ 1120              		.loc 4 1377 3 view .LVU395
+ 1121              		.loc 4 1377 10 is_stmt 0 view .LVU396
+ 1122 0126 0B4B     		ldr	r3, .L60+12
+ 1123 0128 9C81     		strh	r4, [r3, #12]	@ movhi
+ 1124              	.LVL98:
+ 1125              		.loc 4 1377 10 view .LVU397
+ 1126              	.LBE322:
+ 1127              	.LBE321:
+1839:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+ 1128              		.loc 2 1839 4 is_stmt 1 view .LVU398
+1840:Src/main.c    **** 			(void) SPI6->DR;
+ 1129              		.loc 2 1840 4 view .LVU399
+1839:Src/main.c    **** 			while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w
+ 1130              		.loc 2 1839 10 is_stmt 0 view .LVU400
+ARM GAS  /tmp/ccdsDELB.s 			page 125
+
+
+ 1131 012a 0022     		movs	r2, #0
+ 1132              	.LVL99:
+ 1133              	.L56:
+1840:Src/main.c    **** 			(void) SPI6->DR;
+ 1134              		.loc 2 1840 9 is_stmt 1 discriminator 1 view .LVU401
+ 1135              	.LBB323:
+ 1136              	.LBI323:
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1137              		.loc 4 905 26 discriminator 1 view .LVU402
+ 1138              	.LBB324:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1139              		.loc 4 907 3 discriminator 1 view .LVU403
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1140              		.loc 4 907 12 is_stmt 0 discriminator 1 view .LVU404
+ 1141 012c 094B     		ldr	r3, .L60+12
+ 1142 012e 9B68     		ldr	r3, [r3, #8]
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1143              		.loc 4 907 68 discriminator 1 view .LVU405
+ 1144 0130 13F0010F 		tst	r3, #1
+ 1145 0134 04D1     		bne	.L57
+ 1146              	.LVL100:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1147              		.loc 4 907 68 discriminator 1 view .LVU406
+ 1148              	.LBE324:
+ 1149              	.LBE323:
+1840:Src/main.c    **** 			(void) SPI6->DR;
+ 1150              		.loc 2 1840 43 view .LVU407
+ 1151 0136 B2F5FA7F 		cmp	r2, #500
+ 1152 013a 01D8     		bhi	.L57
+1840:Src/main.c    **** 			(void) SPI6->DR;
+ 1153              		.loc 2 1840 60 is_stmt 1 discriminator 3 view .LVU408
+1840:Src/main.c    **** 			(void) SPI6->DR;
+ 1154              		.loc 2 1840 65 is_stmt 0 discriminator 3 view .LVU409
+ 1155 013c 0132     		adds	r2, r2, #1
+ 1156              	.LVL101:
+1840:Src/main.c    **** 			(void) SPI6->DR;
+ 1157              		.loc 2 1840 65 discriminator 3 view .LVU410
+ 1158 013e F5E7     		b	.L56
+ 1159              	.L57:
+1841:Src/main.c    **** 		break;
+ 1160              		.loc 2 1841 4 is_stmt 1 view .LVU411
+ 1161 0140 044B     		ldr	r3, .L60+12
+ 1162 0142 DB68     		ldr	r3, [r3, #12]
+1842:Src/main.c    **** 	}
+ 1163              		.loc 2 1842 3 view .LVU412
+ 1164 0144 85E7     		b	.L29
+ 1165              	.L61:
+ 1166 0146 00BF     		.align	2
+ 1167              	.L60:
+ 1168 0148 00040240 		.word	1073873920
+ 1169 014c 00380040 		.word	1073756160
+ 1170 0150 00000240 		.word	1073872896
+ 1171 0154 00540140 		.word	1073828864
+ 1172              		.cfi_endproc
+ 1173              	.LFE1206:
+ 1175              		.section	.text.MPhD_T,"ax",%progbits
+ 1176              		.align	1
+ARM GAS  /tmp/ccdsDELB.s 			page 126
+
+
+ 1177              		.syntax unified
+ 1178              		.thumb
+ 1179              		.thumb_func
+ 1180              		.fpu fpv5-d16
+ 1182              	MPhD_T:
+ 1183              	.LVL102:
+ 1184              	.LFB1207:
+1850:Src/main.c    **** 	uint16_t P;
+ 1185              		.loc 2 1850 1 view -0
+ 1186              		.cfi_startproc
+ 1187              		@ args = 0, pretend = 0, frame = 0
+ 1188              		@ frame_needed = 0, uses_anonymous_args = 0
+1850:Src/main.c    **** 	uint16_t P;
+ 1189              		.loc 2 1850 1 is_stmt 0 view .LVU414
+ 1190 0000 38B5     		push	{r3, r4, r5, lr}
+ 1191              	.LCFI9:
+ 1192              		.cfi_def_cfa_offset 16
+ 1193              		.cfi_offset 3, -16
+ 1194              		.cfi_offset 4, -12
+ 1195              		.cfi_offset 5, -8
+ 1196              		.cfi_offset 14, -4
+ 1197 0002 0446     		mov	r4, r0
+1851:Src/main.c    **** 	uint32_t tmp32;
+ 1198              		.loc 2 1851 2 is_stmt 1 view .LVU415
+1852:Src/main.c    **** 	HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion
+ 1199              		.loc 2 1852 2 view .LVU416
+1853:Src/main.c    **** 	HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion
+ 1200              		.loc 2 1853 2 view .LVU417
+ 1201 0004 0022     		movs	r2, #0
+ 1202 0006 4FF48041 		mov	r1, #16384
+ 1203 000a 8248     		ldr	r0, .L106
+ 1204              	.LVL103:
+1853:Src/main.c    **** 	HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion
+ 1205              		.loc 2 1853 2 is_stmt 0 view .LVU418
+ 1206 000c FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1207              	.LVL104:
+1854:Src/main.c    **** 	tmp32=0;
+ 1208              		.loc 2 1854 2 is_stmt 1 view .LVU419
+ 1209 0010 0022     		movs	r2, #0
+ 1210 0012 4FF40071 		mov	r1, #512
+ 1211 0016 8048     		ldr	r0, .L106+4
+ 1212 0018 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1213              	.LVL105:
+1855:Src/main.c    **** 	while(tmp32<500){tmp32++;}
+ 1214              		.loc 2 1855 2 view .LVU420
+1856:Src/main.c    **** 	HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver
+ 1215              		.loc 2 1856 2 view .LVU421
+1855:Src/main.c    **** 	while(tmp32<500){tmp32++;}
+ 1216              		.loc 2 1855 7 is_stmt 0 view .LVU422
+ 1217 001c 0023     		movs	r3, #0
+1856:Src/main.c    **** 	HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver
+ 1218              		.loc 2 1856 7 view .LVU423
+ 1219 001e 00E0     		b	.L63
+ 1220              	.LVL106:
+ 1221              	.L64:
+1856:Src/main.c    **** 	HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver
+ 1222              		.loc 2 1856 19 is_stmt 1 discriminator 2 view .LVU424
+ARM GAS  /tmp/ccdsDELB.s 			page 127
+
+
+1856:Src/main.c    **** 	HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver
+ 1223              		.loc 2 1856 24 is_stmt 0 discriminator 2 view .LVU425
+ 1224 0020 0133     		adds	r3, r3, #1
+ 1225              	.LVL107:
+ 1226              	.L63:
+1856:Src/main.c    **** 	HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver
+ 1227              		.loc 2 1856 7 is_stmt 1 discriminator 1 view .LVU426
+ 1228 0022 B3F5FA7F 		cmp	r3, #500
+ 1229 0026 FBD3     		bcc	.L64
+1857:Src/main.c    **** 	HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver
+ 1230              		.loc 2 1857 2 view .LVU427
+ 1231 0028 0122     		movs	r2, #1
+ 1232 002a 4FF48041 		mov	r1, #16384
+ 1233 002e 7948     		ldr	r0, .L106
+ 1234 0030 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1235              	.LVL108:
+1858:Src/main.c    **** 	tmp32=0;
+ 1236              		.loc 2 1858 2 view .LVU428
+ 1237 0034 0122     		movs	r2, #1
+ 1238 0036 4FF40071 		mov	r1, #512
+ 1239 003a 7748     		ldr	r0, .L106+4
+ 1240 003c FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1241              	.LVL109:
+1859:Src/main.c    **** 	while(tmp32<500){tmp32++;}
+ 1242              		.loc 2 1859 2 view .LVU429
+1860:Src/main.c    **** 	if (num==1)//MPD1
+ 1243              		.loc 2 1860 2 view .LVU430
+1859:Src/main.c    **** 	while(tmp32<500){tmp32++;}
+ 1244              		.loc 2 1859 7 is_stmt 0 view .LVU431
+ 1245 0040 0023     		movs	r3, #0
+1860:Src/main.c    **** 	if (num==1)//MPD1
+ 1246              		.loc 2 1860 7 view .LVU432
+ 1247 0042 00E0     		b	.L65
+ 1248              	.LVL110:
+ 1249              	.L66:
+1860:Src/main.c    **** 	if (num==1)//MPD1
+ 1250              		.loc 2 1860 19 is_stmt 1 discriminator 2 view .LVU433
+1860:Src/main.c    **** 	if (num==1)//MPD1
+ 1251              		.loc 2 1860 24 is_stmt 0 discriminator 2 view .LVU434
+ 1252 0044 0133     		adds	r3, r3, #1
+ 1253              	.LVL111:
+ 1254              	.L65:
+1860:Src/main.c    **** 	if (num==1)//MPD1
+ 1255              		.loc 2 1860 7 is_stmt 1 discriminator 1 view .LVU435
+ 1256 0046 B3F5FA7F 		cmp	r3, #500
+ 1257 004a FBD3     		bcc	.L66
+1861:Src/main.c    **** 	{
+ 1258              		.loc 2 1861 2 view .LVU436
+1861:Src/main.c    **** 	{
+ 1259              		.loc 2 1861 5 is_stmt 0 view .LVU437
+ 1260 004c 012C     		cmp	r4, #1
+ 1261 004e 08D0     		beq	.L100
+1877:Src/main.c    **** 	{
+ 1262              		.loc 2 1877 7 is_stmt 1 view .LVU438
+1877:Src/main.c    **** 	{
+ 1263              		.loc 2 1877 10 is_stmt 0 view .LVU439
+ 1264 0050 022C     		cmp	r4, #2
+ARM GAS  /tmp/ccdsDELB.s 			page 128
+
+
+ 1265 0052 3DD0     		beq	.L101
+1893:Src/main.c    **** 	{
+ 1266              		.loc 2 1893 7 is_stmt 1 view .LVU440
+1893:Src/main.c    **** 	{
+ 1267              		.loc 2 1893 10 is_stmt 0 view .LVU441
+ 1268 0054 032C     		cmp	r4, #3
+ 1269 0056 70D0     		beq	.L102
+1909:Src/main.c    **** 	{
+ 1270              		.loc 2 1909 7 is_stmt 1 view .LVU442
+1909:Src/main.c    **** 	{
+ 1271              		.loc 2 1909 10 is_stmt 0 view .LVU443
+ 1272 0058 042C     		cmp	r4, #4
+ 1273 005a 00F0A580 		beq	.L103
+ 1274              	.LVL112:
+ 1275              	.L75:
+1947:Src/main.c    **** }
+ 1276              		.loc 2 1947 2 is_stmt 1 view .LVU444
+1948:Src/main.c    **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time
+ 1277              		.loc 2 1948 1 is_stmt 0 view .LVU445
+ 1278 005e 2846     		mov	r0, r5
+ 1279 0060 38BD     		pop	{r3, r4, r5, pc}
+ 1280              	.LVL113:
+ 1281              	.L100:
+1863:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET);
+ 1282              		.loc 2 1863 3 is_stmt 1 view .LVU446
+ 1283 0062 6C4C     		ldr	r4, .L106
+ 1284 0064 0122     		movs	r2, #1
+ 1285 0066 4FF40061 		mov	r1, #2048
+ 1286 006a 2046     		mov	r0, r4
+ 1287 006c FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1288              	.LVL114:
+1864:Src/main.c    **** 		tmp32=0;
+ 1289              		.loc 2 1864 3 view .LVU447
+ 1290 0070 0022     		movs	r2, #0
+ 1291 0072 4FF48061 		mov	r1, #1024
+ 1292 0076 2046     		mov	r0, r4
+ 1293 0078 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1294              	.LVL115:
+1865:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1295              		.loc 2 1865 3 view .LVU448
+1866:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1296              		.loc 2 1866 3 view .LVU449
+1865:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1297              		.loc 2 1865 8 is_stmt 0 view .LVU450
+ 1298 007c 0023     		movs	r3, #0
+1866:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1299              		.loc 2 1866 8 view .LVU451
+ 1300 007e 00E0     		b	.L68
+ 1301              	.LVL116:
+ 1302              	.L69:
+1866:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1303              		.loc 2 1866 20 is_stmt 1 discriminator 2 view .LVU452
+1866:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1304              		.loc 2 1866 25 is_stmt 0 discriminator 2 view .LVU453
+ 1305 0080 0133     		adds	r3, r3, #1
+ 1306              	.LVL117:
+ 1307              	.L68:
+ARM GAS  /tmp/ccdsDELB.s 			page 129
+
+
+1866:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1308              		.loc 2 1866 8 is_stmt 1 discriminator 1 view .LVU454
+ 1309 0082 B3F5FA7F 		cmp	r3, #500
+ 1310 0086 FBD3     		bcc	.L69
+1868:Src/main.c    **** 		tmp32 = 0;
+ 1311              		.loc 2 1868 3 view .LVU455
+ 1312              	.LVL118:
+ 1313              	.LBB325:
+ 1314              	.LBI325:
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1315              		.loc 4 358 22 view .LVU456
+ 1316              	.LBB326:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1317              		.loc 4 360 3 view .LVU457
+ 1318 0088 644A     		ldr	r2, .L106+8
+ 1319 008a 1368     		ldr	r3, [r2]
+ 1320              	.LVL119:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1321              		.loc 4 360 3 is_stmt 0 view .LVU458
+ 1322 008c 43F04003 		orr	r3, r3, #64
+ 1323 0090 1360     		str	r3, [r2]
+ 1324              	.LVL120:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1325              		.loc 4 360 3 view .LVU459
+ 1326              	.LBE326:
+ 1327              	.LBE325:
+1869:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+ 1328              		.loc 2 1869 3 is_stmt 1 view .LVU460
+1870:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC
+ 1329              		.loc 2 1870 3 view .LVU461
+1869:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+ 1330              		.loc 2 1869 9 is_stmt 0 view .LVU462
+ 1331 0092 0023     		movs	r3, #0
+ 1332              	.LVL121:
+ 1333              	.L70:
+1870:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC
+ 1334              		.loc 2 1870 8 is_stmt 1 discriminator 1 view .LVU463
+ 1335              	.LBB327:
+ 1336              	.LBI327:
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1337              		.loc 4 905 26 discriminator 1 view .LVU464
+ 1338              	.LBB328:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1339              		.loc 4 907 3 discriminator 1 view .LVU465
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1340              		.loc 4 907 12 is_stmt 0 discriminator 1 view .LVU466
+ 1341 0094 614A     		ldr	r2, .L106+8
+ 1342 0096 9268     		ldr	r2, [r2, #8]
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1343              		.loc 4 907 68 discriminator 1 view .LVU467
+ 1344 0098 12F0010F 		tst	r2, #1
+ 1345 009c 04D1     		bne	.L71
+ 1346              	.LVL122:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1347              		.loc 4 907 68 discriminator 1 view .LVU468
+ 1348              	.LBE328:
+ 1349              	.LBE327:
+ARM GAS  /tmp/ccdsDELB.s 			page 130
+
+
+1870:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC
+ 1350              		.loc 2 1870 43 view .LVU469
+ 1351 009e B3F57A7F 		cmp	r3, #1000
+ 1352 00a2 01D8     		bhi	.L71
+1870:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC
+ 1353              		.loc 2 1870 62 is_stmt 1 discriminator 3 view .LVU470
+1870:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC
+ 1354              		.loc 2 1870 67 is_stmt 0 discriminator 3 view .LVU471
+ 1355 00a4 0133     		adds	r3, r3, #1
+ 1356              	.LVL123:
+1870:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC
+ 1357              		.loc 2 1870 67 discriminator 3 view .LVU472
+ 1358 00a6 F5E7     		b	.L70
+ 1359              	.L71:
+1871:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1360              		.loc 2 1871 3 is_stmt 1 view .LVU473
+ 1361              	.LVL124:
+ 1362              	.LBB329:
+ 1363              	.LBI329:
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1364              		.loc 4 370 22 view .LVU474
+ 1365              	.LBB330:
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1366              		.loc 4 372 3 view .LVU475
+ 1367 00a8 5C49     		ldr	r1, .L106+8
+ 1368 00aa 0A68     		ldr	r2, [r1]
+ 1369 00ac 22F04002 		bic	r2, r2, #64
+ 1370 00b0 0A60     		str	r2, [r1]
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 1371              		.loc 4 373 1 is_stmt 0 view .LVU476
+ 1372 00b2 00E0     		b	.L73
+ 1373              	.LVL125:
+ 1374              	.L74:
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 1375              		.loc 4 373 1 view .LVU477
+ 1376              	.LBE330:
+ 1377              	.LBE329:
+1872:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1378              		.loc 2 1872 20 is_stmt 1 discriminator 2 view .LVU478
+1872:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1379              		.loc 2 1872 25 is_stmt 0 discriminator 2 view .LVU479
+ 1380 00b4 0133     		adds	r3, r3, #1
+ 1381              	.LVL126:
+ 1382              	.L73:
+1872:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1383              		.loc 2 1872 8 is_stmt 1 discriminator 1 view .LVU480
+ 1384 00b6 B3F5FA7F 		cmp	r3, #500
+ 1385 00ba FBD3     		bcc	.L74
+1874:Src/main.c    **** 		P = LL_SPI_ReceiveData16(SPI4);
+ 1386              		.loc 2 1874 3 view .LVU481
+ 1387 00bc 0122     		movs	r2, #1
+ 1388 00be 4FF48061 		mov	r1, #1024
+ 1389 00c2 5448     		ldr	r0, .L106
+ 1390 00c4 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1391              	.LVL127:
+1875:Src/main.c    **** 	}
+ 1392              		.loc 2 1875 3 view .LVU482
+ARM GAS  /tmp/ccdsDELB.s 			page 131
+
+
+ 1393              	.LBB331:
+ 1394              	.LBI331:
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1395              		.loc 4 1344 26 view .LVU483
+ 1396              	.LBB332:
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1397              		.loc 4 1346 3 view .LVU484
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1398              		.loc 4 1346 21 is_stmt 0 view .LVU485
+ 1399 00c8 544B     		ldr	r3, .L106+8
+ 1400 00ca DD68     		ldr	r5, [r3, #12]
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1401              		.loc 4 1346 10 view .LVU486
+ 1402 00cc ADB2     		uxth	r5, r5
+ 1403              	.LVL128:
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1404              		.loc 4 1346 10 view .LVU487
+ 1405              	.LBE332:
+ 1406              	.LBE331:
+ 1407 00ce C6E7     		b	.L75
+ 1408              	.LVL129:
+ 1409              	.L101:
+1879:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET);
+ 1410              		.loc 2 1879 3 is_stmt 1 view .LVU488
+ 1411 00d0 514C     		ldr	r4, .L106+4
+ 1412 00d2 0122     		movs	r2, #1
+ 1413 00d4 4FF48061 		mov	r1, #1024
+ 1414 00d8 2046     		mov	r0, r4
+ 1415 00da FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1416              	.LVL130:
+1880:Src/main.c    **** 		tmp32=0;
+ 1417              		.loc 2 1880 3 view .LVU489
+ 1418 00de 0022     		movs	r2, #0
+ 1419 00e0 4021     		movs	r1, #64
+ 1420 00e2 2046     		mov	r0, r4
+ 1421 00e4 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1422              	.LVL131:
+1881:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1423              		.loc 2 1881 3 view .LVU490
+1882:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1424              		.loc 2 1882 3 view .LVU491
+1881:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1425              		.loc 2 1881 8 is_stmt 0 view .LVU492
+ 1426 00e8 0023     		movs	r3, #0
+1882:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1427              		.loc 2 1882 8 view .LVU493
+ 1428 00ea 00E0     		b	.L77
+ 1429              	.LVL132:
+ 1430              	.L78:
+1882:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1431              		.loc 2 1882 20 is_stmt 1 discriminator 2 view .LVU494
+1882:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1432              		.loc 2 1882 25 is_stmt 0 discriminator 2 view .LVU495
+ 1433 00ec 0133     		adds	r3, r3, #1
+ 1434              	.LVL133:
+ 1435              	.L77:
+1882:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ARM GAS  /tmp/ccdsDELB.s 			page 132
+
+
+ 1436              		.loc 2 1882 8 is_stmt 1 discriminator 1 view .LVU496
+ 1437 00ee B3F5FA7F 		cmp	r3, #500
+ 1438 00f2 FBD3     		bcc	.L78
+1884:Src/main.c    **** 		tmp32 = 0;
+ 1439              		.loc 2 1884 3 view .LVU497
+ 1440              	.LVL134:
+ 1441              	.LBB333:
+ 1442              	.LBI333:
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1443              		.loc 4 358 22 view .LVU498
+ 1444              	.LBB334:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1445              		.loc 4 360 3 view .LVU499
+ 1446 00f4 4A4A     		ldr	r2, .L106+12
+ 1447 00f6 1368     		ldr	r3, [r2]
+ 1448              	.LVL135:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1449              		.loc 4 360 3 is_stmt 0 view .LVU500
+ 1450 00f8 43F04003 		orr	r3, r3, #64
+ 1451 00fc 1360     		str	r3, [r2]
+ 1452              	.LVL136:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1453              		.loc 4 360 3 view .LVU501
+ 1454              	.LBE334:
+ 1455              	.LBE333:
+1885:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+ 1456              		.loc 2 1885 3 is_stmt 1 view .LVU502
+1886:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC
+ 1457              		.loc 2 1886 3 view .LVU503
+1885:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+ 1458              		.loc 2 1885 9 is_stmt 0 view .LVU504
+ 1459 00fe 0023     		movs	r3, #0
+ 1460              	.LVL137:
+ 1461              	.L79:
+1886:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC
+ 1462              		.loc 2 1886 8 is_stmt 1 discriminator 1 view .LVU505
+ 1463              	.LBB335:
+ 1464              	.LBI335:
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1465              		.loc 4 905 26 discriminator 1 view .LVU506
+ 1466              	.LBB336:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1467              		.loc 4 907 3 discriminator 1 view .LVU507
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1468              		.loc 4 907 12 is_stmt 0 discriminator 1 view .LVU508
+ 1469 0100 474A     		ldr	r2, .L106+12
+ 1470 0102 9268     		ldr	r2, [r2, #8]
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1471              		.loc 4 907 68 discriminator 1 view .LVU509
+ 1472 0104 12F0010F 		tst	r2, #1
+ 1473 0108 04D1     		bne	.L80
+ 1474              	.LVL138:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1475              		.loc 4 907 68 discriminator 1 view .LVU510
+ 1476              	.LBE336:
+ 1477              	.LBE335:
+1886:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC
+ARM GAS  /tmp/ccdsDELB.s 			page 133
+
+
+ 1478              		.loc 2 1886 43 view .LVU511
+ 1479 010a B3F57A7F 		cmp	r3, #1000
+ 1480 010e 01D8     		bhi	.L80
+1886:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC
+ 1481              		.loc 2 1886 62 is_stmt 1 discriminator 3 view .LVU512
+1886:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC
+ 1482              		.loc 2 1886 67 is_stmt 0 discriminator 3 view .LVU513
+ 1483 0110 0133     		adds	r3, r3, #1
+ 1484              	.LVL139:
+1886:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC
+ 1485              		.loc 2 1886 67 discriminator 3 view .LVU514
+ 1486 0112 F5E7     		b	.L79
+ 1487              	.L80:
+1887:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1488              		.loc 2 1887 3 is_stmt 1 view .LVU515
+ 1489              	.LVL140:
+ 1490              	.LBB337:
+ 1491              	.LBI337:
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1492              		.loc 4 370 22 view .LVU516
+ 1493              	.LBB338:
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1494              		.loc 4 372 3 view .LVU517
+ 1495 0114 4249     		ldr	r1, .L106+12
+ 1496 0116 0A68     		ldr	r2, [r1]
+ 1497 0118 22F04002 		bic	r2, r2, #64
+ 1498 011c 0A60     		str	r2, [r1]
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 1499              		.loc 4 373 1 is_stmt 0 view .LVU518
+ 1500 011e 00E0     		b	.L82
+ 1501              	.LVL141:
+ 1502              	.L83:
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 1503              		.loc 4 373 1 view .LVU519
+ 1504              	.LBE338:
+ 1505              	.LBE337:
+1888:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1506              		.loc 2 1888 20 is_stmt 1 discriminator 2 view .LVU520
+1888:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1507              		.loc 2 1888 25 is_stmt 0 discriminator 2 view .LVU521
+ 1508 0120 0133     		adds	r3, r3, #1
+ 1509              	.LVL142:
+ 1510              	.L82:
+1888:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1511              		.loc 2 1888 8 is_stmt 1 discriminator 1 view .LVU522
+ 1512 0122 B3F5FA7F 		cmp	r3, #500
+ 1513 0126 FBD3     		bcc	.L83
+1890:Src/main.c    **** 		P = LL_SPI_ReceiveData16(SPI5);
+ 1514              		.loc 2 1890 3 view .LVU523
+ 1515 0128 0122     		movs	r2, #1
+ 1516 012a 4021     		movs	r1, #64
+ 1517 012c 3A48     		ldr	r0, .L106+4
+ 1518 012e FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1519              	.LVL143:
+1891:Src/main.c    **** 	}
+ 1520              		.loc 2 1891 3 view .LVU524
+ 1521              	.LBB339:
+ARM GAS  /tmp/ccdsDELB.s 			page 134
+
+
+ 1522              	.LBI339:
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1523              		.loc 4 1344 26 view .LVU525
+ 1524              	.LBB340:
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1525              		.loc 4 1346 3 view .LVU526
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1526              		.loc 4 1346 21 is_stmt 0 view .LVU527
+ 1527 0132 3B4B     		ldr	r3, .L106+12
+ 1528 0134 DD68     		ldr	r5, [r3, #12]
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1529              		.loc 4 1346 10 view .LVU528
+ 1530 0136 ADB2     		uxth	r5, r5
+ 1531              	.LVL144:
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1532              		.loc 4 1346 10 view .LVU529
+ 1533              	.LBE340:
+ 1534              	.LBE339:
+ 1535 0138 91E7     		b	.L75
+ 1536              	.LVL145:
+ 1537              	.L102:
+1895:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET);
+ 1538              		.loc 2 1895 3 is_stmt 1 view .LVU530
+ 1539 013a 364C     		ldr	r4, .L106
+ 1540 013c 0122     		movs	r2, #1
+ 1541 013e 4FF48061 		mov	r1, #1024
+ 1542 0142 2046     		mov	r0, r4
+ 1543 0144 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1544              	.LVL146:
+1896:Src/main.c    **** 		tmp32=0;
+ 1545              		.loc 2 1896 3 view .LVU531
+ 1546 0148 0022     		movs	r2, #0
+ 1547 014a 4FF40061 		mov	r1, #2048
+ 1548 014e 2046     		mov	r0, r4
+ 1549 0150 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1550              	.LVL147:
+1897:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1551              		.loc 2 1897 3 view .LVU532
+1898:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1552              		.loc 2 1898 3 view .LVU533
+1897:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1553              		.loc 2 1897 8 is_stmt 0 view .LVU534
+ 1554 0154 0023     		movs	r3, #0
+1898:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1555              		.loc 2 1898 8 view .LVU535
+ 1556 0156 00E0     		b	.L85
+ 1557              	.LVL148:
+ 1558              	.L86:
+1898:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1559              		.loc 2 1898 20 is_stmt 1 discriminator 2 view .LVU536
+1898:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1560              		.loc 2 1898 25 is_stmt 0 discriminator 2 view .LVU537
+ 1561 0158 0133     		adds	r3, r3, #1
+ 1562              	.LVL149:
+ 1563              	.L85:
+1898:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1564              		.loc 2 1898 8 is_stmt 1 discriminator 1 view .LVU538
+ARM GAS  /tmp/ccdsDELB.s 			page 135
+
+
+ 1565 015a B3F5FA7F 		cmp	r3, #500
+ 1566 015e FBD3     		bcc	.L86
+1900:Src/main.c    **** 		tmp32 = 0;
+ 1567              		.loc 2 1900 3 view .LVU539
+ 1568              	.LVL150:
+ 1569              	.LBB341:
+ 1570              	.LBI341:
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1571              		.loc 4 358 22 view .LVU540
+ 1572              	.LBB342:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1573              		.loc 4 360 3 view .LVU541
+ 1574 0160 2E4A     		ldr	r2, .L106+8
+ 1575 0162 1368     		ldr	r3, [r2]
+ 1576              	.LVL151:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1577              		.loc 4 360 3 is_stmt 0 view .LVU542
+ 1578 0164 43F04003 		orr	r3, r3, #64
+ 1579 0168 1360     		str	r3, [r2]
+ 1580              	.LVL152:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1581              		.loc 4 360 3 view .LVU543
+ 1582              	.LBE342:
+ 1583              	.LBE341:
+1901:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+ 1584              		.loc 2 1901 3 is_stmt 1 view .LVU544
+1902:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC
+ 1585              		.loc 2 1902 3 view .LVU545
+1901:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+ 1586              		.loc 2 1901 9 is_stmt 0 view .LVU546
+ 1587 016a 0023     		movs	r3, #0
+ 1588              	.LVL153:
+ 1589              	.L87:
+1902:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC
+ 1590              		.loc 2 1902 8 is_stmt 1 discriminator 1 view .LVU547
+ 1591              	.LBB343:
+ 1592              	.LBI343:
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1593              		.loc 4 905 26 discriminator 1 view .LVU548
+ 1594              	.LBB344:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1595              		.loc 4 907 3 discriminator 1 view .LVU549
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1596              		.loc 4 907 12 is_stmt 0 discriminator 1 view .LVU550
+ 1597 016c 2B4A     		ldr	r2, .L106+8
+ 1598 016e 9268     		ldr	r2, [r2, #8]
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1599              		.loc 4 907 68 discriminator 1 view .LVU551
+ 1600 0170 12F0010F 		tst	r2, #1
+ 1601 0174 04D1     		bne	.L88
+ 1602              	.LVL154:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1603              		.loc 4 907 68 discriminator 1 view .LVU552
+ 1604              	.LBE344:
+ 1605              	.LBE343:
+1902:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC
+ 1606              		.loc 2 1902 43 view .LVU553
+ARM GAS  /tmp/ccdsDELB.s 			page 136
+
+
+ 1607 0176 B3F57A7F 		cmp	r3, #1000
+ 1608 017a 01D8     		bhi	.L88
+1902:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC
+ 1609              		.loc 2 1902 62 is_stmt 1 discriminator 3 view .LVU554
+1902:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC
+ 1610              		.loc 2 1902 67 is_stmt 0 discriminator 3 view .LVU555
+ 1611 017c 0133     		adds	r3, r3, #1
+ 1612              	.LVL155:
+1902:Src/main.c    **** 		LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC
+ 1613              		.loc 2 1902 67 discriminator 3 view .LVU556
+ 1614 017e F5E7     		b	.L87
+ 1615              	.L88:
+1903:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1616              		.loc 2 1903 3 is_stmt 1 view .LVU557
+ 1617              	.LVL156:
+ 1618              	.LBB345:
+ 1619              	.LBI345:
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1620              		.loc 4 370 22 view .LVU558
+ 1621              	.LBB346:
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1622              		.loc 4 372 3 view .LVU559
+ 1623 0180 2649     		ldr	r1, .L106+8
+ 1624 0182 0A68     		ldr	r2, [r1]
+ 1625 0184 22F04002 		bic	r2, r2, #64
+ 1626 0188 0A60     		str	r2, [r1]
+ 1627              	.LVL157:
+ 1628              	.L90:
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1629              		.loc 4 372 3 is_stmt 0 view .LVU560
+ 1630              	.LBE346:
+ 1631              	.LBE345:
+1904:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1632              		.loc 2 1904 8 is_stmt 1 discriminator 1 view .LVU561
+ 1633 018a B3F5FA7F 		cmp	r3, #500
+ 1634 018e 01D2     		bcs	.L104
+1904:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1635              		.loc 2 1904 20 discriminator 2 view .LVU562
+1904:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1636              		.loc 2 1904 25 is_stmt 0 discriminator 2 view .LVU563
+ 1637 0190 0133     		adds	r3, r3, #1
+ 1638              	.LVL158:
+1904:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1639              		.loc 2 1904 25 discriminator 2 view .LVU564
+ 1640 0192 FAE7     		b	.L90
+ 1641              	.L104:
+1906:Src/main.c    **** 		P = LL_SPI_ReceiveData16(SPI4);
+ 1642              		.loc 2 1906 3 is_stmt 1 view .LVU565
+ 1643 0194 0122     		movs	r2, #1
+ 1644 0196 4FF40061 		mov	r1, #2048
+ 1645 019a 1E48     		ldr	r0, .L106
+ 1646 019c FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1647              	.LVL159:
+1907:Src/main.c    **** 	}
+ 1648              		.loc 2 1907 3 view .LVU566
+ 1649              	.LBB347:
+ 1650              	.LBI347:
+ARM GAS  /tmp/ccdsDELB.s 			page 137
+
+
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1651              		.loc 4 1344 26 view .LVU567
+ 1652              	.LBB348:
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1653              		.loc 4 1346 3 view .LVU568
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1654              		.loc 4 1346 21 is_stmt 0 view .LVU569
+ 1655 01a0 1E4B     		ldr	r3, .L106+8
+ 1656 01a2 DD68     		ldr	r5, [r3, #12]
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1657              		.loc 4 1346 10 view .LVU570
+ 1658 01a4 ADB2     		uxth	r5, r5
+ 1659              	.LVL160:
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1660              		.loc 4 1346 10 view .LVU571
+ 1661              	.LBE348:
+ 1662              	.LBE347:
+ 1663 01a6 5AE7     		b	.L75
+ 1664              	.LVL161:
+ 1665              	.L103:
+1911:Src/main.c    **** 		HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET);
+ 1666              		.loc 2 1911 3 is_stmt 1 view .LVU572
+ 1667 01a8 1B4C     		ldr	r4, .L106+4
+ 1668 01aa 0122     		movs	r2, #1
+ 1669 01ac 4021     		movs	r1, #64
+ 1670 01ae 2046     		mov	r0, r4
+ 1671 01b0 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1672              	.LVL162:
+1912:Src/main.c    **** 		tmp32=0;
+ 1673              		.loc 2 1912 3 view .LVU573
+ 1674 01b4 0022     		movs	r2, #0
+ 1675 01b6 4FF48061 		mov	r1, #1024
+ 1676 01ba 2046     		mov	r0, r4
+ 1677 01bc FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1678              	.LVL163:
+1913:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1679              		.loc 2 1913 3 view .LVU574
+1914:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1680              		.loc 2 1914 3 view .LVU575
+1913:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1681              		.loc 2 1913 8 is_stmt 0 view .LVU576
+ 1682 01c0 0023     		movs	r3, #0
+ 1683              	.LVL164:
+ 1684              	.L92:
+1914:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1685              		.loc 2 1914 8 is_stmt 1 discriminator 1 view .LVU577
+ 1686 01c2 B3F5FA7F 		cmp	r3, #500
+ 1687 01c6 01D2     		bcs	.L105
+1914:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1688              		.loc 2 1914 20 discriminator 2 view .LVU578
+1914:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1689              		.loc 2 1914 25 is_stmt 0 discriminator 2 view .LVU579
+ 1690 01c8 0133     		adds	r3, r3, #1
+ 1691              	.LVL165:
+1914:Src/main.c    **** 		//LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c
+ 1692              		.loc 2 1914 25 discriminator 2 view .LVU580
+ 1693 01ca FAE7     		b	.L92
+ARM GAS  /tmp/ccdsDELB.s 			page 138
+
+
+ 1694              	.L105:
+1916:Src/main.c    **** 		tmp32 = 0;
+ 1695              		.loc 2 1916 3 is_stmt 1 view .LVU581
+ 1696              	.LVL166:
+ 1697              	.LBB349:
+ 1698              	.LBI349:
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1699              		.loc 4 358 22 view .LVU582
+ 1700              	.LBB350:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1701              		.loc 4 360 3 view .LVU583
+ 1702 01cc 144A     		ldr	r2, .L106+12
+ 1703 01ce 1368     		ldr	r3, [r2]
+ 1704              	.LVL167:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1705              		.loc 4 360 3 is_stmt 0 view .LVU584
+ 1706 01d0 43F04003 		orr	r3, r3, #64
+ 1707 01d4 1360     		str	r3, [r2]
+ 1708              	.LVL168:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1709              		.loc 4 360 3 view .LVU585
+ 1710              	.LBE350:
+ 1711              	.LBE349:
+1917:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+ 1712              		.loc 2 1917 3 is_stmt 1 view .LVU586
+1918:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC
+ 1713              		.loc 2 1918 3 view .LVU587
+1917:Src/main.c    **** 		while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w
+ 1714              		.loc 2 1917 9 is_stmt 0 view .LVU588
+ 1715 01d6 0023     		movs	r3, #0
+ 1716              	.LVL169:
+ 1717              	.L94:
+1918:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC
+ 1718              		.loc 2 1918 8 is_stmt 1 discriminator 1 view .LVU589
+ 1719              	.LBB351:
+ 1720              	.LBI351:
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1721              		.loc 4 905 26 discriminator 1 view .LVU590
+ 1722              	.LBB352:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1723              		.loc 4 907 3 discriminator 1 view .LVU591
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1724              		.loc 4 907 12 is_stmt 0 discriminator 1 view .LVU592
+ 1725 01d8 114A     		ldr	r2, .L106+12
+ 1726 01da 9268     		ldr	r2, [r2, #8]
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1727              		.loc 4 907 68 discriminator 1 view .LVU593
+ 1728 01dc 12F0010F 		tst	r2, #1
+ 1729 01e0 04D1     		bne	.L95
+ 1730              	.LVL170:
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1731              		.loc 4 907 68 discriminator 1 view .LVU594
+ 1732              	.LBE352:
+ 1733              	.LBE351:
+1918:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC
+ 1734              		.loc 2 1918 43 view .LVU595
+ 1735 01e2 B3F57A7F 		cmp	r3, #1000
+ARM GAS  /tmp/ccdsDELB.s 			page 139
+
+
+ 1736 01e6 01D8     		bhi	.L95
+1918:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC
+ 1737              		.loc 2 1918 62 is_stmt 1 discriminator 3 view .LVU596
+1918:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC
+ 1738              		.loc 2 1918 67 is_stmt 0 discriminator 3 view .LVU597
+ 1739 01e8 0133     		adds	r3, r3, #1
+ 1740              	.LVL171:
+1918:Src/main.c    **** 		LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC
+ 1741              		.loc 2 1918 67 discriminator 3 view .LVU598
+ 1742 01ea F5E7     		b	.L94
+ 1743              	.L95:
+1919:Src/main.c    **** 		while(tmp32<500){tmp32++;}
+ 1744              		.loc 2 1919 3 is_stmt 1 view .LVU599
+ 1745              	.LVL172:
+ 1746              	.LBB353:
+ 1747              	.LBI353:
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 1748              		.loc 4 370 22 view .LVU600
+ 1749              	.LBB354:
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1750              		.loc 4 372 3 view .LVU601
+ 1751 01ec 0C49     		ldr	r1, .L106+12
+ 1752 01ee 0A68     		ldr	r2, [r1]
+ 1753 01f0 22F04002 		bic	r2, r2, #64
+ 1754 01f4 0A60     		str	r2, [r1]
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 1755              		.loc 4 373 1 is_stmt 0 view .LVU602
+ 1756 01f6 00E0     		b	.L97
+ 1757              	.LVL173:
+ 1758              	.L98:
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 1759              		.loc 4 373 1 view .LVU603
+ 1760              	.LBE354:
+ 1761              	.LBE353:
+1920:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1762              		.loc 2 1920 20 is_stmt 1 discriminator 2 view .LVU604
+1920:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1763              		.loc 2 1920 25 is_stmt 0 discriminator 2 view .LVU605
+ 1764 01f8 0133     		adds	r3, r3, #1
+ 1765              	.LVL174:
+ 1766              	.L97:
+1920:Src/main.c    **** 		//HAL_SPI_Receive(&hspi4, &P[0], 1, 100);
+ 1767              		.loc 2 1920 8 is_stmt 1 discriminator 1 view .LVU606
+ 1768 01fa B3F5FA7F 		cmp	r3, #500
+ 1769 01fe FBD3     		bcc	.L98
+1922:Src/main.c    **** 		P = LL_SPI_ReceiveData16(SPI5);
+ 1770              		.loc 2 1922 3 view .LVU607
+ 1771 0200 0122     		movs	r2, #1
+ 1772 0202 4FF48061 		mov	r1, #1024
+ 1773 0206 0448     		ldr	r0, .L106+4
+ 1774 0208 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1775              	.LVL175:
+1923:Src/main.c    **** 	}
+ 1776              		.loc 2 1923 3 view .LVU608
+ 1777              	.LBB355:
+ 1778              	.LBI355:
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 140
+
+
+ 1779              		.loc 4 1344 26 view .LVU609
+ 1780              	.LBB356:
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1781              		.loc 4 1346 3 view .LVU610
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1782              		.loc 4 1346 21 is_stmt 0 view .LVU611
+ 1783 020c 044B     		ldr	r3, .L106+12
+ 1784 020e DD68     		ldr	r5, [r3, #12]
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1785              		.loc 4 1346 10 view .LVU612
+ 1786 0210 ADB2     		uxth	r5, r5
+ 1787              	.LVL176:
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 1788              		.loc 4 1346 10 view .LVU613
+ 1789 0212 24E7     		b	.L75
+ 1790              	.L107:
+ 1791              		.align	2
+ 1792              	.L106:
+ 1793 0214 00100240 		.word	1073876992
+ 1794 0218 00140240 		.word	1073878016
+ 1795 021c 00340140 		.word	1073820672
+ 1796 0220 00500140 		.word	1073827840
+ 1797              	.LBE356:
+ 1798              	.LBE355:
+ 1799              		.cfi_endproc
+ 1800              	.LFE1207:
+ 1802              		.section	.text.MX_GPIO_Init,"ax",%progbits
+ 1803              		.align	1
+ 1804              		.syntax unified
+ 1805              		.thumb
+ 1806              		.thumb_func
+ 1807              		.fpu fpv5-d16
+ 1809              	MX_GPIO_Init:
+ 1810              	.LFB1202:
+1319:Src/main.c    ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 1811              		.loc 2 1319 1 is_stmt 1 view -0
+ 1812              		.cfi_startproc
+ 1813              		@ args = 0, pretend = 0, frame = 48
+ 1814              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1815 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 1816              	.LCFI10:
+ 1817              		.cfi_def_cfa_offset 36
+ 1818              		.cfi_offset 4, -36
+ 1819              		.cfi_offset 5, -32
+ 1820              		.cfi_offset 6, -28
+ 1821              		.cfi_offset 7, -24
+ 1822              		.cfi_offset 8, -20
+ 1823              		.cfi_offset 9, -16
+ 1824              		.cfi_offset 10, -12
+ 1825              		.cfi_offset 11, -8
+ 1826              		.cfi_offset 14, -4
+ 1827 0004 8DB0     		sub	sp, sp, #52
+ 1828              	.LCFI11:
+ 1829              		.cfi_def_cfa_offset 88
+1320:Src/main.c    **** /* USER CODE BEGIN MX_GPIO_Init_1 */
+ 1830              		.loc 2 1320 3 view .LVU615
+1320:Src/main.c    **** /* USER CODE BEGIN MX_GPIO_Init_1 */
+ARM GAS  /tmp/ccdsDELB.s 			page 141
+
+
+ 1831              		.loc 2 1320 20 is_stmt 0 view .LVU616
+ 1832 0006 0024     		movs	r4, #0
+ 1833 0008 0794     		str	r4, [sp, #28]
+ 1834 000a 0894     		str	r4, [sp, #32]
+ 1835 000c 0994     		str	r4, [sp, #36]
+ 1836 000e 0A94     		str	r4, [sp, #40]
+ 1837 0010 0B94     		str	r4, [sp, #44]
+1325:Src/main.c    ****   __HAL_RCC_GPIOH_CLK_ENABLE();
+ 1838              		.loc 2 1325 3 is_stmt 1 view .LVU617
+ 1839              	.LBB357:
+1325:Src/main.c    ****   __HAL_RCC_GPIOH_CLK_ENABLE();
+ 1840              		.loc 2 1325 3 view .LVU618
+1325:Src/main.c    ****   __HAL_RCC_GPIOH_CLK_ENABLE();
+ 1841              		.loc 2 1325 3 view .LVU619
+ 1842 0012 784B     		ldr	r3, .L110
+ 1843 0014 1A6B     		ldr	r2, [r3, #48]
+ 1844 0016 42F02002 		orr	r2, r2, #32
+ 1845 001a 1A63     		str	r2, [r3, #48]
+1325:Src/main.c    ****   __HAL_RCC_GPIOH_CLK_ENABLE();
+ 1846              		.loc 2 1325 3 view .LVU620
+ 1847 001c 1A6B     		ldr	r2, [r3, #48]
+ 1848 001e 02F02002 		and	r2, r2, #32
+ 1849 0022 0092     		str	r2, [sp]
+1325:Src/main.c    ****   __HAL_RCC_GPIOH_CLK_ENABLE();
+ 1850              		.loc 2 1325 3 view .LVU621
+ 1851 0024 009A     		ldr	r2, [sp]
+ 1852              	.LBE357:
+1325:Src/main.c    ****   __HAL_RCC_GPIOH_CLK_ENABLE();
+ 1853              		.loc 2 1325 3 view .LVU622
+1326:Src/main.c    ****   __HAL_RCC_GPIOC_CLK_ENABLE();
+ 1854              		.loc 2 1326 3 view .LVU623
+ 1855              	.LBB358:
+1326:Src/main.c    ****   __HAL_RCC_GPIOC_CLK_ENABLE();
+ 1856              		.loc 2 1326 3 view .LVU624
+1326:Src/main.c    ****   __HAL_RCC_GPIOC_CLK_ENABLE();
+ 1857              		.loc 2 1326 3 view .LVU625
+ 1858 0026 1A6B     		ldr	r2, [r3, #48]
+ 1859 0028 42F08002 		orr	r2, r2, #128
+ 1860 002c 1A63     		str	r2, [r3, #48]
+1326:Src/main.c    ****   __HAL_RCC_GPIOC_CLK_ENABLE();
+ 1861              		.loc 2 1326 3 view .LVU626
+ 1862 002e 1A6B     		ldr	r2, [r3, #48]
+ 1863 0030 02F08002 		and	r2, r2, #128
+ 1864 0034 0192     		str	r2, [sp, #4]
+1326:Src/main.c    ****   __HAL_RCC_GPIOC_CLK_ENABLE();
+ 1865              		.loc 2 1326 3 view .LVU627
+ 1866 0036 019A     		ldr	r2, [sp, #4]
+ 1867              	.LBE358:
+1326:Src/main.c    ****   __HAL_RCC_GPIOC_CLK_ENABLE();
+ 1868              		.loc 2 1326 3 view .LVU628
+1327:Src/main.c    ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 1869              		.loc 2 1327 3 view .LVU629
+ 1870              	.LBB359:
+1327:Src/main.c    ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 1871              		.loc 2 1327 3 view .LVU630
+1327:Src/main.c    ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 1872              		.loc 2 1327 3 view .LVU631
+ARM GAS  /tmp/ccdsDELB.s 			page 142
+
+
+ 1873 0038 1A6B     		ldr	r2, [r3, #48]
+ 1874 003a 42F00402 		orr	r2, r2, #4
+ 1875 003e 1A63     		str	r2, [r3, #48]
+1327:Src/main.c    ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 1876              		.loc 2 1327 3 view .LVU632
+ 1877 0040 1A6B     		ldr	r2, [r3, #48]
+ 1878 0042 02F00402 		and	r2, r2, #4
+ 1879 0046 0292     		str	r2, [sp, #8]
+1327:Src/main.c    ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 1880              		.loc 2 1327 3 view .LVU633
+ 1881 0048 029A     		ldr	r2, [sp, #8]
+ 1882              	.LBE359:
+1327:Src/main.c    ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 1883              		.loc 2 1327 3 view .LVU634
+1328:Src/main.c    ****   __HAL_RCC_GPIOB_CLK_ENABLE();
+ 1884              		.loc 2 1328 3 view .LVU635
+ 1885              	.LBB360:
+1328:Src/main.c    ****   __HAL_RCC_GPIOB_CLK_ENABLE();
+ 1886              		.loc 2 1328 3 view .LVU636
+1328:Src/main.c    ****   __HAL_RCC_GPIOB_CLK_ENABLE();
+ 1887              		.loc 2 1328 3 view .LVU637
+ 1888 004a 1A6B     		ldr	r2, [r3, #48]
+ 1889 004c 42F00102 		orr	r2, r2, #1
+ 1890 0050 1A63     		str	r2, [r3, #48]
+1328:Src/main.c    ****   __HAL_RCC_GPIOB_CLK_ENABLE();
+ 1891              		.loc 2 1328 3 view .LVU638
+ 1892 0052 1A6B     		ldr	r2, [r3, #48]
+ 1893 0054 02F00102 		and	r2, r2, #1
+ 1894 0058 0392     		str	r2, [sp, #12]
+1328:Src/main.c    ****   __HAL_RCC_GPIOB_CLK_ENABLE();
+ 1895              		.loc 2 1328 3 view .LVU639
+ 1896 005a 039A     		ldr	r2, [sp, #12]
+ 1897              	.LBE360:
+1328:Src/main.c    ****   __HAL_RCC_GPIOB_CLK_ENABLE();
+ 1898              		.loc 2 1328 3 view .LVU640
+1329:Src/main.c    ****   __HAL_RCC_GPIOE_CLK_ENABLE();
+ 1899              		.loc 2 1329 3 view .LVU641
+ 1900              	.LBB361:
+1329:Src/main.c    ****   __HAL_RCC_GPIOE_CLK_ENABLE();
+ 1901              		.loc 2 1329 3 view .LVU642
+1329:Src/main.c    ****   __HAL_RCC_GPIOE_CLK_ENABLE();
+ 1902              		.loc 2 1329 3 view .LVU643
+ 1903 005c 1A6B     		ldr	r2, [r3, #48]
+ 1904 005e 42F00202 		orr	r2, r2, #2
+ 1905 0062 1A63     		str	r2, [r3, #48]
+1329:Src/main.c    ****   __HAL_RCC_GPIOE_CLK_ENABLE();
+ 1906              		.loc 2 1329 3 view .LVU644
+ 1907 0064 1A6B     		ldr	r2, [r3, #48]
+ 1908 0066 02F00202 		and	r2, r2, #2
+ 1909 006a 0492     		str	r2, [sp, #16]
+1329:Src/main.c    ****   __HAL_RCC_GPIOE_CLK_ENABLE();
+ 1910              		.loc 2 1329 3 view .LVU645
+ 1911 006c 049A     		ldr	r2, [sp, #16]
+ 1912              	.LBE361:
+1329:Src/main.c    ****   __HAL_RCC_GPIOE_CLK_ENABLE();
+ 1913              		.loc 2 1329 3 view .LVU646
+1330:Src/main.c    ****   __HAL_RCC_GPIOD_CLK_ENABLE();
+ARM GAS  /tmp/ccdsDELB.s 			page 143
+
+
+ 1914              		.loc 2 1330 3 view .LVU647
+ 1915              	.LBB362:
+1330:Src/main.c    ****   __HAL_RCC_GPIOD_CLK_ENABLE();
+ 1916              		.loc 2 1330 3 view .LVU648
+1330:Src/main.c    ****   __HAL_RCC_GPIOD_CLK_ENABLE();
+ 1917              		.loc 2 1330 3 view .LVU649
+ 1918 006e 1A6B     		ldr	r2, [r3, #48]
+ 1919 0070 42F01002 		orr	r2, r2, #16
+ 1920 0074 1A63     		str	r2, [r3, #48]
+1330:Src/main.c    ****   __HAL_RCC_GPIOD_CLK_ENABLE();
+ 1921              		.loc 2 1330 3 view .LVU650
+ 1922 0076 1A6B     		ldr	r2, [r3, #48]
+ 1923 0078 02F01002 		and	r2, r2, #16
+ 1924 007c 0592     		str	r2, [sp, #20]
+1330:Src/main.c    ****   __HAL_RCC_GPIOD_CLK_ENABLE();
+ 1925              		.loc 2 1330 3 view .LVU651
+ 1926 007e 059A     		ldr	r2, [sp, #20]
+ 1927              	.LBE362:
+1330:Src/main.c    ****   __HAL_RCC_GPIOD_CLK_ENABLE();
+ 1928              		.loc 2 1330 3 view .LVU652
+1331:Src/main.c    **** 
+ 1929              		.loc 2 1331 3 view .LVU653
+ 1930              	.LBB363:
+1331:Src/main.c    **** 
+ 1931              		.loc 2 1331 3 view .LVU654
+1331:Src/main.c    **** 
+ 1932              		.loc 2 1331 3 view .LVU655
+ 1933 0080 1A6B     		ldr	r2, [r3, #48]
+ 1934 0082 42F00802 		orr	r2, r2, #8
+ 1935 0086 1A63     		str	r2, [r3, #48]
+1331:Src/main.c    **** 
+ 1936              		.loc 2 1331 3 view .LVU656
+ 1937 0088 1B6B     		ldr	r3, [r3, #48]
+ 1938 008a 03F00803 		and	r3, r3, #8
+ 1939 008e 0693     		str	r3, [sp, #24]
+1331:Src/main.c    **** 
+ 1940              		.loc 2 1331 3 view .LVU657
+ 1941 0090 069B     		ldr	r3, [sp, #24]
+ 1942              	.LBE363:
+1331:Src/main.c    **** 
+ 1943              		.loc 2 1331 3 view .LVU658
+1334:Src/main.c    **** 
+ 1944              		.loc 2 1334 3 view .LVU659
+ 1945 0092 DFF86CA1 		ldr	r10, .L110+12
+ 1946 0096 2246     		mov	r2, r4
+ 1947 0098 4FF4C861 		mov	r1, #1600
+ 1948 009c 5046     		mov	r0, r10
+ 1949 009e FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1950              	.LVL177:
+1337:Src/main.c    **** 
+ 1951              		.loc 2 1337 3 view .LVU660
+ 1952 00a2 DFF860B1 		ldr	fp, .L110+16
+ 1953 00a6 2246     		mov	r2, r4
+ 1954 00a8 3C21     		movs	r1, #60
+ 1955 00aa 5846     		mov	r0, fp
+ 1956 00ac FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1957              	.LVL178:
+ARM GAS  /tmp/ccdsDELB.s 			page 144
+
+
+1340:Src/main.c    **** 
+ 1958              		.loc 2 1340 3 view .LVU661
+ 1959 00b0 514F     		ldr	r7, .L110+4
+ 1960 00b2 2246     		mov	r2, r4
+ 1961 00b4 4B21     		movs	r1, #75
+ 1962 00b6 3846     		mov	r0, r7
+ 1963 00b8 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1964              	.LVL179:
+1343:Src/main.c    **** 
+ 1965              		.loc 2 1343 3 view .LVU662
+ 1966 00bc 0122     		movs	r2, #1
+ 1967 00be 1021     		movs	r1, #16
+ 1968 00c0 3846     		mov	r0, r7
+ 1969 00c2 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1970              	.LVL180:
+1346:Src/main.c    **** 
+ 1971              		.loc 2 1346 3 view .LVU663
+ 1972 00c6 4D4E     		ldr	r6, .L110+8
+ 1973 00c8 2246     		mov	r2, r4
+ 1974 00ca 4FF44061 		mov	r1, #3072
+ 1975 00ce 3046     		mov	r0, r6
+ 1976 00d0 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1977              	.LVL181:
+1349:Src/main.c    **** 
+ 1978              		.loc 2 1349 3 view .LVU664
+ 1979 00d4 0122     		movs	r2, #1
+ 1980 00d6 4FF48041 		mov	r1, #16384
+ 1981 00da 3046     		mov	r0, r6
+ 1982 00dc FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1983              	.LVL182:
+1352:Src/main.c    **** 
+ 1984              		.loc 2 1352 3 view .LVU665
+ 1985 00e0 DFF82491 		ldr	r9, .L110+20
+ 1986 00e4 2246     		mov	r2, r4
+ 1987 00e6 4FF49841 		mov	r1, #19456
+ 1988 00ea 4846     		mov	r0, r9
+ 1989 00ec FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1990              	.LVL183:
+1355:Src/main.c    **** 
+ 1991              		.loc 2 1355 3 view .LVU666
+ 1992 00f0 0122     		movs	r2, #1
+ 1993 00f2 4FF48051 		mov	r1, #4096
+ 1994 00f6 4846     		mov	r0, r9
+ 1995 00f8 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 1996              	.LVL184:
+1358:Src/main.c    **** 
+ 1997              		.loc 2 1358 3 view .LVU667
+ 1998 00fc DFF80C81 		ldr	r8, .L110+24
+ 1999 0100 2246     		mov	r2, r4
+ 2000 0102 4FF4C171 		mov	r1, #386
+ 2001 0106 4046     		mov	r0, r8
+ 2002 0108 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 2003              	.LVL185:
+1361:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2004              		.loc 2 1361 3 view .LVU668
+1361:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2005              		.loc 2 1361 23 is_stmt 0 view .LVU669
+ARM GAS  /tmp/ccdsDELB.s 			page 145
+
+
+ 2006 010c 4FF4C863 		mov	r3, #1600
+ 2007 0110 0793     		str	r3, [sp, #28]
+1362:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2008              		.loc 2 1362 3 is_stmt 1 view .LVU670
+1362:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2009              		.loc 2 1362 24 is_stmt 0 view .LVU671
+ 2010 0112 0125     		movs	r5, #1
+ 2011 0114 0895     		str	r5, [sp, #32]
+1363:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2012              		.loc 2 1363 3 is_stmt 1 view .LVU672
+1363:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2013              		.loc 2 1363 24 is_stmt 0 view .LVU673
+ 2014 0116 0994     		str	r4, [sp, #36]
+1364:Src/main.c    ****   HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 2015              		.loc 2 1364 3 is_stmt 1 view .LVU674
+1364:Src/main.c    ****   HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 2016              		.loc 2 1364 25 is_stmt 0 view .LVU675
+ 2017 0118 0A94     		str	r4, [sp, #40]
+1365:Src/main.c    **** 
+ 2018              		.loc 2 1365 3 is_stmt 1 view .LVU676
+ 2019 011a 07A9     		add	r1, sp, #28
+ 2020 011c 5046     		mov	r0, r10
+ 2021 011e FFF7FEFF 		bl	HAL_GPIO_Init
+ 2022              	.LVL186:
+1368:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2023              		.loc 2 1368 3 view .LVU677
+1368:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2024              		.loc 2 1368 23 is_stmt 0 view .LVU678
+ 2025 0122 3423     		movs	r3, #52
+ 2026 0124 0793     		str	r3, [sp, #28]
+1369:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2027              		.loc 2 1369 3 is_stmt 1 view .LVU679
+1369:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2028              		.loc 2 1369 24 is_stmt 0 view .LVU680
+ 2029 0126 0895     		str	r5, [sp, #32]
+1370:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2030              		.loc 2 1370 3 is_stmt 1 view .LVU681
+1370:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2031              		.loc 2 1370 24 is_stmt 0 view .LVU682
+ 2032 0128 0994     		str	r4, [sp, #36]
+1371:Src/main.c    ****   HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 2033              		.loc 2 1371 3 is_stmt 1 view .LVU683
+1371:Src/main.c    ****   HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 2034              		.loc 2 1371 25 is_stmt 0 view .LVU684
+ 2035 012a 0A94     		str	r4, [sp, #40]
+1372:Src/main.c    **** 
+ 2036              		.loc 2 1372 3 is_stmt 1 view .LVU685
+ 2037 012c 07A9     		add	r1, sp, #28
+ 2038 012e 5846     		mov	r0, fp
+ 2039 0130 FFF7FEFF 		bl	HAL_GPIO_Init
+ 2040              	.LVL187:
+1375:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2041              		.loc 2 1375 3 view .LVU686
+1375:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2042              		.loc 2 1375 23 is_stmt 0 view .LVU687
+ 2043 0134 0823     		movs	r3, #8
+ 2044 0136 0793     		str	r3, [sp, #28]
+ARM GAS  /tmp/ccdsDELB.s 			page 146
+
+
+1376:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2045              		.loc 2 1376 3 is_stmt 1 view .LVU688
+1376:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2046              		.loc 2 1376 24 is_stmt 0 view .LVU689
+ 2047 0138 0895     		str	r5, [sp, #32]
+1377:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 2048              		.loc 2 1377 3 is_stmt 1 view .LVU690
+1377:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 2049              		.loc 2 1377 24 is_stmt 0 view .LVU691
+ 2050 013a 0994     		str	r4, [sp, #36]
+1378:Src/main.c    ****   HAL_GPIO_Init(EN_5V1_GPIO_Port, &GPIO_InitStruct);
+ 2051              		.loc 2 1378 3 is_stmt 1 view .LVU692
+1378:Src/main.c    ****   HAL_GPIO_Init(EN_5V1_GPIO_Port, &GPIO_InitStruct);
+ 2052              		.loc 2 1378 25 is_stmt 0 view .LVU693
+ 2053 013c 0323     		movs	r3, #3
+ 2054 013e 0A93     		str	r3, [sp, #40]
+1379:Src/main.c    **** 
+ 2055              		.loc 2 1379 3 is_stmt 1 view .LVU694
+ 2056 0140 07A9     		add	r1, sp, #28
+ 2057 0142 5846     		mov	r0, fp
+ 2058 0144 FFF7FEFF 		bl	HAL_GPIO_Init
+ 2059              	.LVL188:
+1383:Src/main.c    ****                           |DAC_LD2_CS_Pin;
+ 2060              		.loc 2 1383 3 view .LVU695
+1383:Src/main.c    ****                           |DAC_LD2_CS_Pin;
+ 2061              		.loc 2 1383 23 is_stmt 0 view .LVU696
+ 2062 0148 5B23     		movs	r3, #91
+ 2063 014a 0793     		str	r3, [sp, #28]
+1385:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2064              		.loc 2 1385 3 is_stmt 1 view .LVU697
+1385:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2065              		.loc 2 1385 24 is_stmt 0 view .LVU698
+ 2066 014c 0895     		str	r5, [sp, #32]
+1386:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2067              		.loc 2 1386 3 is_stmt 1 view .LVU699
+1386:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2068              		.loc 2 1386 24 is_stmt 0 view .LVU700
+ 2069 014e 0994     		str	r4, [sp, #36]
+1387:Src/main.c    ****   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 2070              		.loc 2 1387 3 is_stmt 1 view .LVU701
+1387:Src/main.c    ****   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 2071              		.loc 2 1387 25 is_stmt 0 view .LVU702
+ 2072 0150 0A94     		str	r4, [sp, #40]
+1388:Src/main.c    **** 
+ 2073              		.loc 2 1388 3 is_stmt 1 view .LVU703
+ 2074 0152 07A9     		add	r1, sp, #28
+ 2075 0154 3846     		mov	r0, r7
+ 2076 0156 FFF7FEFF 		bl	HAL_GPIO_Init
+ 2077              	.LVL189:
+1391:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 2078              		.loc 2 1391 3 view .LVU704
+1391:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 2079              		.loc 2 1391 23 is_stmt 0 view .LVU705
+ 2080 015a 4FF4F043 		mov	r3, #30720
+ 2081 015e 0793     		str	r3, [sp, #28]
+1392:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2082              		.loc 2 1392 3 is_stmt 1 view .LVU706
+ARM GAS  /tmp/ccdsDELB.s 			page 147
+
+
+1392:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2083              		.loc 2 1392 24 is_stmt 0 view .LVU707
+ 2084 0160 0894     		str	r4, [sp, #32]
+1393:Src/main.c    ****   HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 2085              		.loc 2 1393 3 is_stmt 1 view .LVU708
+1393:Src/main.c    ****   HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 2086              		.loc 2 1393 24 is_stmt 0 view .LVU709
+ 2087 0162 0994     		str	r4, [sp, #36]
+1394:Src/main.c    **** 
+ 2088              		.loc 2 1394 3 is_stmt 1 view .LVU710
+ 2089 0164 07A9     		add	r1, sp, #28
+ 2090 0166 5046     		mov	r0, r10
+ 2091 0168 FFF7FEFF 		bl	HAL_GPIO_Init
+ 2092              	.LVL190:
+1397:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2093              		.loc 2 1397 3 view .LVU711
+1397:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2094              		.loc 2 1397 23 is_stmt 0 view .LVU712
+ 2095 016c 4FF44063 		mov	r3, #3072
+ 2096 0170 0793     		str	r3, [sp, #28]
+1398:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2097              		.loc 2 1398 3 is_stmt 1 view .LVU713
+1398:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2098              		.loc 2 1398 24 is_stmt 0 view .LVU714
+ 2099 0172 0895     		str	r5, [sp, #32]
+1399:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2100              		.loc 2 1399 3 is_stmt 1 view .LVU715
+1399:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2101              		.loc 2 1399 24 is_stmt 0 view .LVU716
+ 2102 0174 0994     		str	r4, [sp, #36]
+1400:Src/main.c    ****   HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 2103              		.loc 2 1400 3 is_stmt 1 view .LVU717
+1400:Src/main.c    ****   HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 2104              		.loc 2 1400 25 is_stmt 0 view .LVU718
+ 2105 0176 0A94     		str	r4, [sp, #40]
+1401:Src/main.c    **** 
+ 2106              		.loc 2 1401 3 is_stmt 1 view .LVU719
+ 2107 0178 07A9     		add	r1, sp, #28
+ 2108 017a 3046     		mov	r0, r6
+ 2109 017c FFF7FEFF 		bl	HAL_GPIO_Init
+ 2110              	.LVL191:
+1404:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2111              		.loc 2 1404 3 view .LVU720
+1404:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2112              		.loc 2 1404 23 is_stmt 0 view .LVU721
+ 2113 0180 4FF48043 		mov	r3, #16384
+ 2114 0184 0793     		str	r3, [sp, #28]
+1405:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2115              		.loc 2 1405 3 is_stmt 1 view .LVU722
+1405:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2116              		.loc 2 1405 24 is_stmt 0 view .LVU723
+ 2117 0186 0895     		str	r5, [sp, #32]
+1406:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 2118              		.loc 2 1406 3 is_stmt 1 view .LVU724
+1406:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 2119              		.loc 2 1406 24 is_stmt 0 view .LVU725
+ 2120 0188 0994     		str	r4, [sp, #36]
+ARM GAS  /tmp/ccdsDELB.s 			page 148
+
+
+1407:Src/main.c    ****   HAL_GPIO_Init(SPI4_CNV_GPIO_Port, &GPIO_InitStruct);
+ 2121              		.loc 2 1407 3 is_stmt 1 view .LVU726
+1407:Src/main.c    ****   HAL_GPIO_Init(SPI4_CNV_GPIO_Port, &GPIO_InitStruct);
+ 2122              		.loc 2 1407 25 is_stmt 0 view .LVU727
+ 2123 018a 0323     		movs	r3, #3
+ 2124 018c 0A93     		str	r3, [sp, #40]
+1408:Src/main.c    **** 
+ 2125              		.loc 2 1408 3 is_stmt 1 view .LVU728
+ 2126 018e 07A9     		add	r1, sp, #28
+ 2127 0190 3046     		mov	r0, r6
+ 2128 0192 FFF7FEFF 		bl	HAL_GPIO_Init
+ 2129              	.LVL192:
+1411:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2130              		.loc 2 1411 3 view .LVU729
+1411:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2131              		.loc 2 1411 23 is_stmt 0 view .LVU730
+ 2132 0196 4FF4B843 		mov	r3, #23552
+ 2133 019a 0793     		str	r3, [sp, #28]
+1412:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2134              		.loc 2 1412 3 is_stmt 1 view .LVU731
+1412:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2135              		.loc 2 1412 24 is_stmt 0 view .LVU732
+ 2136 019c 0895     		str	r5, [sp, #32]
+1413:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2137              		.loc 2 1413 3 is_stmt 1 view .LVU733
+1413:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2138              		.loc 2 1413 24 is_stmt 0 view .LVU734
+ 2139 019e 0994     		str	r4, [sp, #36]
+1414:Src/main.c    ****   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 2140              		.loc 2 1414 3 is_stmt 1 view .LVU735
+1414:Src/main.c    ****   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 2141              		.loc 2 1414 25 is_stmt 0 view .LVU736
+ 2142 01a0 0A94     		str	r4, [sp, #40]
+1415:Src/main.c    **** 
+ 2143              		.loc 2 1415 3 is_stmt 1 view .LVU737
+ 2144 01a2 07A9     		add	r1, sp, #28
+ 2145 01a4 4846     		mov	r0, r9
+ 2146 01a6 FFF7FEFF 		bl	HAL_GPIO_Init
+ 2147              	.LVL193:
+1418:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2148              		.loc 2 1418 3 view .LVU738
+1418:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 2149              		.loc 2 1418 23 is_stmt 0 view .LVU739
+ 2150 01aa 4FF4C173 		mov	r3, #386
+ 2151 01ae 0793     		str	r3, [sp, #28]
+1419:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2152              		.loc 2 1419 3 is_stmt 1 view .LVU740
+1419:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2153              		.loc 2 1419 24 is_stmt 0 view .LVU741
+ 2154 01b0 0895     		str	r5, [sp, #32]
+1420:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2155              		.loc 2 1420 3 is_stmt 1 view .LVU742
+1420:Src/main.c    ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 2156              		.loc 2 1420 24 is_stmt 0 view .LVU743
+ 2157 01b2 0994     		str	r4, [sp, #36]
+1421:Src/main.c    ****   HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 2158              		.loc 2 1421 3 is_stmt 1 view .LVU744
+ARM GAS  /tmp/ccdsDELB.s 			page 149
+
+
+1421:Src/main.c    ****   HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 2159              		.loc 2 1421 25 is_stmt 0 view .LVU745
+ 2160 01b4 0A94     		str	r4, [sp, #40]
+1422:Src/main.c    **** 
+ 2161              		.loc 2 1422 3 is_stmt 1 view .LVU746
+ 2162 01b6 07A9     		add	r1, sp, #28
+ 2163 01b8 4046     		mov	r0, r8
+ 2164 01ba FFF7FEFF 		bl	HAL_GPIO_Init
+ 2165              	.LVL194:
+1425:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 2166              		.loc 2 1425 3 view .LVU747
+1425:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 2167              		.loc 2 1425 23 is_stmt 0 view .LVU748
+ 2168 01be 4FF48073 		mov	r3, #256
+ 2169 01c2 0793     		str	r3, [sp, #28]
+1426:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2170              		.loc 2 1426 3 is_stmt 1 view .LVU749
+1426:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2171              		.loc 2 1426 24 is_stmt 0 view .LVU750
+ 2172 01c4 0894     		str	r4, [sp, #32]
+1427:Src/main.c    ****   HAL_GPIO_Init(USB_FLAG_GPIO_Port, &GPIO_InitStruct);
+ 2173              		.loc 2 1427 3 is_stmt 1 view .LVU751
+1427:Src/main.c    ****   HAL_GPIO_Init(USB_FLAG_GPIO_Port, &GPIO_InitStruct);
+ 2174              		.loc 2 1427 24 is_stmt 0 view .LVU752
+ 2175 01c6 0994     		str	r4, [sp, #36]
+1428:Src/main.c    **** 
+ 2176              		.loc 2 1428 3 is_stmt 1 view .LVU753
+ 2177 01c8 07A9     		add	r1, sp, #28
+ 2178 01ca 3846     		mov	r0, r7
+ 2179 01cc FFF7FEFF 		bl	HAL_GPIO_Init
+ 2180              	.LVL195:
+1431:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 2181              		.loc 2 1431 3 view .LVU754
+1431:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 2182              		.loc 2 1431 23 is_stmt 0 view .LVU755
+ 2183 01d0 0795     		str	r5, [sp, #28]
+1432:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2184              		.loc 2 1432 3 is_stmt 1 view .LVU756
+1432:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2185              		.loc 2 1432 24 is_stmt 0 view .LVU757
+ 2186 01d2 0894     		str	r4, [sp, #32]
+1433:Src/main.c    ****   HAL_GPIO_Init(SDMMC1_EN_GPIO_Port, &GPIO_InitStruct);
+ 2187              		.loc 2 1433 3 is_stmt 1 view .LVU758
+1433:Src/main.c    ****   HAL_GPIO_Init(SDMMC1_EN_GPIO_Port, &GPIO_InitStruct);
+ 2188              		.loc 2 1433 24 is_stmt 0 view .LVU759
+ 2189 01d4 0994     		str	r4, [sp, #36]
+1434:Src/main.c    **** 
+ 2190              		.loc 2 1434 3 is_stmt 1 view .LVU760
+ 2191 01d6 07A9     		add	r1, sp, #28
+ 2192 01d8 4046     		mov	r0, r8
+ 2193 01da FFF7FEFF 		bl	HAL_GPIO_Init
+ 2194              	.LVL196:
+1437:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 2195              		.loc 2 1437 3 view .LVU761
+1437:Src/main.c    ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 2196              		.loc 2 1437 23 is_stmt 0 view .LVU762
+ 2197 01de 0223     		movs	r3, #2
+ARM GAS  /tmp/ccdsDELB.s 			page 150
+
+
+ 2198 01e0 0793     		str	r3, [sp, #28]
+1438:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2199              		.loc 2 1438 3 is_stmt 1 view .LVU763
+1438:Src/main.c    ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 2200              		.loc 2 1438 24 is_stmt 0 view .LVU764
+ 2201 01e2 0894     		str	r4, [sp, #32]
+1439:Src/main.c    ****   HAL_GPIO_Init(FPGA_CONF_DONE_GPIO_Port, &GPIO_InitStruct);
+ 2202              		.loc 2 1439 3 is_stmt 1 view .LVU765
+1439:Src/main.c    ****   HAL_GPIO_Init(FPGA_CONF_DONE_GPIO_Port, &GPIO_InitStruct);
+ 2203              		.loc 2 1439 24 is_stmt 0 view .LVU766
+ 2204 01e4 0994     		str	r4, [sp, #36]
+1440:Src/main.c    **** 
+ 2205              		.loc 2 1440 3 is_stmt 1 view .LVU767
+ 2206 01e6 07A9     		add	r1, sp, #28
+ 2207 01e8 3046     		mov	r0, r6
+ 2208 01ea FFF7FEFF 		bl	HAL_GPIO_Init
+ 2209              	.LVL197:
+1444:Src/main.c    **** 
+ 2210              		.loc 2 1444 1 is_stmt 0 view .LVU768
+ 2211 01ee 0DB0     		add	sp, sp, #52
+ 2212              	.LCFI12:
+ 2213              		.cfi_def_cfa_offset 36
+ 2214              		@ sp needed
+ 2215 01f0 BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 2216              	.L111:
+ 2217              		.align	2
+ 2218              	.L110:
+ 2219 01f4 00380240 		.word	1073887232
+ 2220 01f8 00000240 		.word	1073872896
+ 2221 01fc 00100240 		.word	1073876992
+ 2222 0200 00140240 		.word	1073878016
+ 2223 0204 00080240 		.word	1073874944
+ 2224 0208 00040240 		.word	1073873920
+ 2225 020c 000C0240 		.word	1073875968
+ 2226              		.cfi_endproc
+ 2227              	.LFE1202:
+ 2229              		.section	.text.MX_SPI4_Init,"ax",%progbits
+ 2230              		.align	1
+ 2231              		.syntax unified
+ 2232              		.thumb
+ 2233              		.thumb_func
+ 2234              		.fpu fpv5-d16
+ 2236              	MX_SPI4_Init:
+ 2237              	.LFB1192:
+ 836:Src/main.c    **** 
+ 2238              		.loc 2 836 1 is_stmt 1 view -0
+ 2239              		.cfi_startproc
+ 2240              		@ args = 0, pretend = 0, frame = 72
+ 2241              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2242 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 2243              	.LCFI13:
+ 2244              		.cfi_def_cfa_offset 24
+ 2245              		.cfi_offset 4, -24
+ 2246              		.cfi_offset 5, -20
+ 2247              		.cfi_offset 6, -16
+ 2248              		.cfi_offset 7, -12
+ 2249              		.cfi_offset 8, -8
+ARM GAS  /tmp/ccdsDELB.s 			page 151
+
+
+ 2250              		.cfi_offset 14, -4
+ 2251 0004 92B0     		sub	sp, sp, #72
+ 2252              	.LCFI14:
+ 2253              		.cfi_def_cfa_offset 96
+ 842:Src/main.c    **** 
+ 2254              		.loc 2 842 3 view .LVU770
+ 842:Src/main.c    **** 
+ 2255              		.loc 2 842 22 is_stmt 0 view .LVU771
+ 2256 0006 2822     		movs	r2, #40
+ 2257 0008 0021     		movs	r1, #0
+ 2258 000a 08A8     		add	r0, sp, #32
+ 2259 000c FFF7FEFF 		bl	memset
+ 2260              	.LVL198:
+ 844:Src/main.c    **** 
+ 2261              		.loc 2 844 3 is_stmt 1 view .LVU772
+ 844:Src/main.c    **** 
+ 2262              		.loc 2 844 23 is_stmt 0 view .LVU773
+ 2263 0010 0024     		movs	r4, #0
+ 2264 0012 0294     		str	r4, [sp, #8]
+ 2265 0014 0394     		str	r4, [sp, #12]
+ 2266 0016 0494     		str	r4, [sp, #16]
+ 2267 0018 0594     		str	r4, [sp, #20]
+ 2268 001a 0694     		str	r4, [sp, #24]
+ 2269 001c 0794     		str	r4, [sp, #28]
+ 847:Src/main.c    **** 
+ 2270              		.loc 2 847 3 is_stmt 1 view .LVU774
+ 2271              	.LVL199:
+ 2272              	.LBB364:
+ 2273              	.LBI364:
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB1 peripheral clock is enabled or not
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\n
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\n
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\n
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_IsEnabledClock
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ARM GAS  /tmp/ccdsDELB.s 			page 152
+
+
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB1 peripherals clock.
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\n
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\n
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\n
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\n
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\n
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\n
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\n
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\n
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\n
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\n
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\n
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\n
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\n
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\n
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\n
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\n
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\n
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\n
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\n
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\n
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_DisableClock
+ARM GAS  /tmp/ccdsDELB.s 			page 153
+
+
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1ENR, Periphs);
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB1 peripherals reset.
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\n
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\n
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\n
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\n
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\n
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\n
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\n
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\n
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\n
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\n
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\n
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\n
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\n
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ARM GAS  /tmp/ccdsDELB.s 			page 154
+
+
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1RSTR, Periphs);
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB1 peripherals reset.
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\n
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\n
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\n
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\n
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\n
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ARM GAS  /tmp/ccdsDELB.s 			page 155
+
+
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB1 peripheral clocks in low-power mode
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    AXILPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DTCMRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_EnableClockLowPower\n
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_EnableClockLowPower\n
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockLowPower
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_AXI
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+ARM GAS  /tmp/ccdsDELB.s 			page 156
+
+
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1LPENR, Periphs);
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB1 peripheral clocks in low-power mode
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    AXILPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DTCMRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_DisableClockLowPower\n
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_DisableClockLowPower\n
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockLowPower
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ARM GAS  /tmp/ccdsDELB.s 			page 157
+
+
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_AXI
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1LPENR, Periphs);
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB2 peripherals clock.
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_EnableClock\n
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_EnableClock\n
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_EnableClock\n
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_EnableClock\n
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_EnableClock\n
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_EnableClock\n
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_EnableClock
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ARM GAS  /tmp/ccdsDELB.s 			page 158
+
+
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2ENR, Periphs);
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB2 peripheral clock is enabled or not
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_IsEnabledClock\n
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_IsEnabledClock\n
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_IsEnabledClock
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB2 peripherals clock.
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_DisableClock\n
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_DisableClock\n
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_DisableClock\n
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_DisableClock\n
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_DisableClock\n
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_DisableClock\n
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_DisableClock
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ARM GAS  /tmp/ccdsDELB.s 			page 159
+
+
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2ENR, Periphs);
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB2 peripherals reset.
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ForceReset\n
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     JPEGRST      LL_AHB2_GRP1_ForceReset\n
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ForceReset\n
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ForceReset\n
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ForceReset\n
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ForceReset\n
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ForceReset
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2RSTR, Periphs);
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB2 peripherals reset.
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ReleaseReset\n
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     JPEGRST      LL_AHB2_GRP1_ReleaseReset\n
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ReleaseReset\n
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ReleaseReset\n
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ReleaseReset\n
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ReleaseReset\n
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ReleaseReset
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ARM GAS  /tmp/ccdsDELB.s 			page 160
+
+
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB2 peripheral clocks in low-power mode
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    JPEGLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_EnableClockLowPower
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2LPENR, Periphs);
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB2 peripheral clocks in low-power mode
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    JPEGLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_DisableClockLowPower
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ARM GAS  /tmp/ccdsDELB.s 			page 161
+
+
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2LPENR, Periphs);
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB3 peripherals clock.
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3ENR, Periphs);
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB3 peripheral clock is enabled or not
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB3 peripherals clock.
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ARM GAS  /tmp/ccdsDELB.s 			page 162
+
+
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3ENR, Periphs);
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB3 peripherals reset.
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3RSTR, Periphs);
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB3 peripherals reset.
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB3 peripheral clocks in low-power mode
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockLowPower\n
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockLowPower
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 163
+
+
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3LPENR, Periphs);
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB3 peripheral clocks in low-power mode
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockLowPower\n
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockLowPower
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3LPENR, Periphs);
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB1 peripherals clock.
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\n
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\n
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_EnableClock\n
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_EnableClock\n
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_EnableClock\n
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_EnableClock\n
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_EnableClock\n
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_EnableClock\n
+ARM GAS  /tmp/ccdsDELB.s 			page 164
+
+
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_EnableClock\n
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_EnableClock\n
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\n
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\n
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_EnableClock\n
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_EnableClock\n
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_EnableClock
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1ENR, Periphs);
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if APB1 peripheral clock is enabled or not
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+ARM GAS  /tmp/ccdsDELB.s 			page 165
+
+
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_IsEnabledClock\n
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_IsEnabledClock\n
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_IsEnabledClock\n
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_IsEnabledClock\n
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\n
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\n
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_IsEnabledClock\n
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_IsEnabledClock
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ARM GAS  /tmp/ccdsDELB.s 			page 166
+
+
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable APB1 peripherals clock.
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\n
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\n
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_DisableClock\n
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_DisableClock\n
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_DisableClock\n
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_DisableClock\n
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_DisableClock\n
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_DisableClock\n
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_DisableClock\n
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_DisableClock\n
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\n
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\n
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_DisableClock\n
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_DisableClock\n
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_DisableClock
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ARM GAS  /tmp/ccdsDELB.s 			page 167
+
+
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1ENR, Periphs);
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force APB1 peripherals reset.
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\n
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\n
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ForceReset\n
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ForceReset\n
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\n
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\n
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ForceReset\n
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ForceReset\n
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ForceReset\n
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset\n
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\n
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\n
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ForceReset\n
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ForceReset\n
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\n
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART3RST      LL_APB1_GRP1_ForceReset\n
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART4RST       LL_APB1_GRP1_ForceReset\n
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART5RST       LL_APB1_GRP1_ForceReset\n
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\n
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\n
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\n
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C4RST        LL_APB1_GRP1_ForceReset\n
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ForceReset\n
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ForceReset\n
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ForceReset\n
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CECRST         LL_APB1_GRP1_ForceReset\n
+ARM GAS  /tmp/ccdsDELB.s 			page 168
+
+
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\n
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\n
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART7RST       LL_APB1_GRP1_ForceReset\n
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART8RST       LL_APB1_GRP1_ForceReset
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1RSTR, Periphs);
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release APB1 peripherals reset.
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ReleaseReset\n
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ReleaseReset\n
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ReleaseReset\n
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ReleaseReset\n
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ReleaseReset\n
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset\n
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\n
+ARM GAS  /tmp/ccdsDELB.s 			page 169
+
+
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ReleaseReset\n
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ReleaseReset\n
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\n
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART3RST      LL_APB1_GRP1_ReleaseReset\n
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART4RST       LL_APB1_GRP1_ReleaseReset\n
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART5RST       LL_APB1_GRP1_ReleaseReset\n
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C4RST        LL_APB1_GRP1_ReleaseReset\n
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ReleaseReset\n
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ReleaseReset\n
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ReleaseReset\n
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CECRST         LL_APB1_GRP1_ReleaseReset\n
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\n
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\n
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART7RST       LL_APB1_GRP1_ReleaseReset\n
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART8RST       LL_APB1_GRP1_ReleaseReset
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1RSTR, Periphs);
+ARM GAS  /tmp/ccdsDELB.s 			page 170
+
+
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB1 peripheral clocks in low-power mode
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_EnableClockLowPower\n
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CECLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     DACLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     RTCLPEN         LL_APB1_GRP1_EnableClockLowPower
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ARM GAS  /tmp/ccdsDELB.s 			page 171
+
+
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1LPENR, Periphs);
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable APB1 peripheral clocks in low-power mode
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_DisableClockLowPower\n
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CECLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     DACLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     RTCLPEN         LL_APB1_GRP1_DisableClockLowPower
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ARM GAS  /tmp/ccdsDELB.s 			page 172
+
+
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1LPENR, Periphs);
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB2 peripherals clock.
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_EnableClock\n
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM8EN        LL_APB2_GRP1_EnableClock\n
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART1EN      LL_APB2_GRP1_EnableClock\n
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART6EN      LL_APB2_GRP1_EnableClock\n
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC1EN        LL_APB2_GRP1_EnableClock\n
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC2EN        LL_APB2_GRP1_EnableClock\n
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC3EN        LL_APB2_GRP1_EnableClock\n
+ARM GAS  /tmp/ccdsDELB.s 			page 173
+
+
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_EnableClock\n
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_EnableClock\n
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI1EN        LL_APB2_GRP1_EnableClock\n
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI4EN        LL_APB2_GRP1_EnableClock\n
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_EnableClock\n
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM9EN        LL_APB2_GRP1_EnableClock\n
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM10EN       LL_APB2_GRP1_EnableClock\n
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM11EN       LL_APB2_GRP1_EnableClock\n
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI5EN        LL_APB2_GRP1_EnableClock\n
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI6EN        LL_APB2_GRP1_EnableClock\n
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI1EN        LL_APB2_GRP1_EnableClock\n
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI2EN        LL_APB2_GRP1_EnableClock\n
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     LTDCEN        LL_APB2_GRP1_EnableClock\n
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DSIEN         LL_APB2_GRP1_EnableClock\n
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_EnableClock\n
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     MDIOEN        LL_APB2_GRP1_EnableClock\n
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_EnableClock
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+ 2274              		.loc 3 1587 22 view .LVU775
+ 2275              	.LBB365:
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 2276              		.loc 3 1589 3 view .LVU776
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB2ENR, Periphs);
+ 2277              		.loc 3 1590 3 view .LVU777
+ 2278 001e 2A4B     		ldr	r3, .L114
+ 2279 0020 5A6C     		ldr	r2, [r3, #68]
+ 2280 0022 42F40052 		orr	r2, r2, #8192
+ARM GAS  /tmp/ccdsDELB.s 			page 174
+
+
+ 2281 0026 5A64     		str	r2, [r3, #68]
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+ 2282              		.loc 3 1592 3 view .LVU778
+ 2283              		.loc 3 1592 12 is_stmt 0 view .LVU779
+ 2284 0028 5A6C     		ldr	r2, [r3, #68]
+ 2285 002a 02F40052 		and	r2, r2, #8192
+ 2286              		.loc 3 1592 10 view .LVU780
+ 2287 002e 0192     		str	r2, [sp, #4]
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2288              		.loc 3 1593 3 is_stmt 1 view .LVU781
+ 2289 0030 019A     		ldr	r2, [sp, #4]
+ 2290              	.LVL200:
+ 2291              		.loc 3 1593 3 is_stmt 0 view .LVU782
+ 2292              	.LBE365:
+ 2293              	.LBE364:
+ 849:Src/main.c    ****   /**SPI4 GPIO Configuration
+ 2294              		.loc 2 849 3 is_stmt 1 view .LVU783
+ 2295              	.LBB366:
+ 2296              	.LBI366:
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 2297              		.loc 3 309 22 view .LVU784
+ 2298              	.LBB367:
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1ENR, Periphs);
+ 2299              		.loc 3 311 3 view .LVU785
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 2300              		.loc 3 312 3 view .LVU786
+ 2301 0032 1A6B     		ldr	r2, [r3, #48]
+ 2302 0034 42F01002 		orr	r2, r2, #16
+ 2303 0038 1A63     		str	r2, [r3, #48]
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2304              		.loc 3 314 3 view .LVU787
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2305              		.loc 3 314 12 is_stmt 0 view .LVU788
+ 2306 003a 1B6B     		ldr	r3, [r3, #48]
+ 2307 003c 03F01003 		and	r3, r3, #16
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2308              		.loc 3 314 10 view .LVU789
+ 2309 0040 0093     		str	r3, [sp]
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 2310              		.loc 3 315 3 is_stmt 1 view .LVU790
+ 2311 0042 009B     		ldr	r3, [sp]
+ 2312              	.LVL201:
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 2313              		.loc 3 315 3 is_stmt 0 view .LVU791
+ 2314              	.LBE367:
+ 2315              	.LBE366:
+ 854:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2316              		.loc 2 854 3 is_stmt 1 view .LVU792
+ 854:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2317              		.loc 2 854 23 is_stmt 0 view .LVU793
+ 2318 0044 4FF48053 		mov	r3, #4096
+ 2319 0048 0293     		str	r3, [sp, #8]
+ 855:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2320              		.loc 2 855 3 is_stmt 1 view .LVU794
+ 855:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2321              		.loc 2 855 24 is_stmt 0 view .LVU795
+ARM GAS  /tmp/ccdsDELB.s 			page 175
+
+
+ 2322 004a 0225     		movs	r5, #2
+ 2323 004c 0395     		str	r5, [sp, #12]
+ 856:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2324              		.loc 2 856 3 is_stmt 1 view .LVU796
+ 856:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2325              		.loc 2 856 25 is_stmt 0 view .LVU797
+ 2326 004e 4FF00308 		mov	r8, #3
+ 2327 0052 CDF81080 		str	r8, [sp, #16]
+ 857:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 2328              		.loc 2 857 3 is_stmt 1 view .LVU798
+ 858:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 2329              		.loc 2 858 3 view .LVU799
+ 859:Src/main.c    ****   LL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 2330              		.loc 2 859 3 view .LVU800
+ 859:Src/main.c    ****   LL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 2331              		.loc 2 859 29 is_stmt 0 view .LVU801
+ 2332 0056 0527     		movs	r7, #5
+ 2333 0058 0797     		str	r7, [sp, #28]
+ 860:Src/main.c    **** 
+ 2334              		.loc 2 860 3 is_stmt 1 view .LVU802
+ 2335 005a 1C4E     		ldr	r6, .L114+4
+ 2336 005c 02A9     		add	r1, sp, #8
+ 2337 005e 3046     		mov	r0, r6
+ 2338 0060 FFF7FEFF 		bl	LL_GPIO_Init
+ 2339              	.LVL202:
+ 862:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2340              		.loc 2 862 3 view .LVU803
+ 862:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2341              		.loc 2 862 23 is_stmt 0 view .LVU804
+ 2342 0064 4FF40053 		mov	r3, #8192
+ 2343 0068 0293     		str	r3, [sp, #8]
+ 863:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2344              		.loc 2 863 3 is_stmt 1 view .LVU805
+ 863:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2345              		.loc 2 863 24 is_stmt 0 view .LVU806
+ 2346 006a 0395     		str	r5, [sp, #12]
+ 864:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2347              		.loc 2 864 3 is_stmt 1 view .LVU807
+ 864:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2348              		.loc 2 864 25 is_stmt 0 view .LVU808
+ 2349 006c CDF81080 		str	r8, [sp, #16]
+ 865:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 2350              		.loc 2 865 3 is_stmt 1 view .LVU809
+ 865:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 2351              		.loc 2 865 30 is_stmt 0 view .LVU810
+ 2352 0070 0594     		str	r4, [sp, #20]
+ 866:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 2353              		.loc 2 866 3 is_stmt 1 view .LVU811
+ 866:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 2354              		.loc 2 866 24 is_stmt 0 view .LVU812
+ 2355 0072 0694     		str	r4, [sp, #24]
+ 867:Src/main.c    ****   LL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 2356              		.loc 2 867 3 is_stmt 1 view .LVU813
+ 867:Src/main.c    ****   LL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 2357              		.loc 2 867 29 is_stmt 0 view .LVU814
+ 2358 0074 0797     		str	r7, [sp, #28]
+ 868:Src/main.c    **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 176
+
+
+ 2359              		.loc 2 868 3 is_stmt 1 view .LVU815
+ 2360 0076 02A9     		add	r1, sp, #8
+ 2361 0078 3046     		mov	r0, r6
+ 2362 007a FFF7FEFF 		bl	LL_GPIO_Init
+ 2363              	.LVL203:
+ 874:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ 2364              		.loc 2 874 3 view .LVU816
+ 874:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ 2365              		.loc 2 874 36 is_stmt 0 view .LVU817
+ 2366 007e 4FF48063 		mov	r3, #1024
+ 2367 0082 0893     		str	r3, [sp, #32]
+ 875:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+ 2368              		.loc 2 875 3 is_stmt 1 view .LVU818
+ 875:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+ 2369              		.loc 2 875 23 is_stmt 0 view .LVU819
+ 2370 0084 4FF48273 		mov	r3, #260
+ 2371 0088 0993     		str	r3, [sp, #36]
+ 876:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+ 2372              		.loc 2 876 3 is_stmt 1 view .LVU820
+ 876:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+ 2373              		.loc 2 876 28 is_stmt 0 view .LVU821
+ 2374 008a 4FF47063 		mov	r3, #3840
+ 2375 008e 0A93     		str	r3, [sp, #40]
+ 877:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
+ 2376              		.loc 2 877 3 is_stmt 1 view .LVU822
+ 877:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
+ 2377              		.loc 2 877 32 is_stmt 0 view .LVU823
+ 2378 0090 0B95     		str	r5, [sp, #44]
+ 878:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ 2379              		.loc 2 878 3 is_stmt 1 view .LVU824
+ 878:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ 2380              		.loc 2 878 29 is_stmt 0 view .LVU825
+ 2381 0092 0C94     		str	r4, [sp, #48]
+ 879:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+ 2382              		.loc 2 879 3 is_stmt 1 view .LVU826
+ 879:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+ 2383              		.loc 2 879 22 is_stmt 0 view .LVU827
+ 2384 0094 4FF40073 		mov	r3, #512
+ 2385 0098 0D93     		str	r3, [sp, #52]
+ 880:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ 2386              		.loc 2 880 3 is_stmt 1 view .LVU828
+ 880:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ 2387              		.loc 2 880 27 is_stmt 0 view .LVU829
+ 2388 009a 1823     		movs	r3, #24
+ 2389 009c 0E93     		str	r3, [sp, #56]
+ 881:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ 2390              		.loc 2 881 3 is_stmt 1 view .LVU830
+ 881:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ 2391              		.loc 2 881 27 is_stmt 0 view .LVU831
+ 2392 009e 0F94     		str	r4, [sp, #60]
+ 882:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+ 2393              		.loc 2 882 3 is_stmt 1 view .LVU832
+ 882:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+ 2394              		.loc 2 882 33 is_stmt 0 view .LVU833
+ 2395 00a0 1094     		str	r4, [sp, #64]
+ 883:Src/main.c    ****   LL_SPI_Init(SPI4, &SPI_InitStruct);
+ 2396              		.loc 2 883 3 is_stmt 1 view .LVU834
+ARM GAS  /tmp/ccdsDELB.s 			page 177
+
+
+ 883:Src/main.c    ****   LL_SPI_Init(SPI4, &SPI_InitStruct);
+ 2397              		.loc 2 883 26 is_stmt 0 view .LVU835
+ 2398 00a2 0723     		movs	r3, #7
+ 2399 00a4 1193     		str	r3, [sp, #68]
+ 884:Src/main.c    ****   LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA);
+ 2400              		.loc 2 884 3 is_stmt 1 view .LVU836
+ 2401 00a6 0A4C     		ldr	r4, .L114+8
+ 2402 00a8 08A9     		add	r1, sp, #32
+ 2403 00aa 2046     		mov	r0, r4
+ 2404 00ac FFF7FEFF 		bl	LL_SPI_Init
+ 2405              	.LVL204:
+ 885:Src/main.c    ****   LL_SPI_DisableNSSPulseMgt(SPI4);
+ 2406              		.loc 2 885 3 view .LVU837
+ 2407              	.LBB368:
+ 2408              	.LBI368:
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 2409              		.loc 4 426 22 view .LVU838
+ 2410              	.LBB369:
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2411              		.loc 4 428 3 view .LVU839
+ 2412 00b0 6368     		ldr	r3, [r4, #4]
+ 2413 00b2 23F01003 		bic	r3, r3, #16
+ 2414 00b6 6360     		str	r3, [r4, #4]
+ 2415              	.LVL205:
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2416              		.loc 4 428 3 is_stmt 0 view .LVU840
+ 2417              	.LBE369:
+ 2418              	.LBE368:
+ 886:Src/main.c    ****   /* USER CODE BEGIN SPI4_Init 2 */
+ 2419              		.loc 2 886 3 is_stmt 1 view .LVU841
+ 2420              	.LBB370:
+ 2421              	.LBI370:
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 2422              		.loc 4 874 22 view .LVU842
+ 2423              	.LBB371:
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2424              		.loc 4 876 3 view .LVU843
+ 2425 00b8 6368     		ldr	r3, [r4, #4]
+ 2426 00ba 23F00803 		bic	r3, r3, #8
+ 2427 00be 6360     		str	r3, [r4, #4]
+ 2428              	.LVL206:
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2429              		.loc 4 876 3 is_stmt 0 view .LVU844
+ 2430              	.LBE371:
+ 2431              	.LBE370:
+ 891:Src/main.c    **** 
+ 2432              		.loc 2 891 1 view .LVU845
+ 2433 00c0 12B0     		add	sp, sp, #72
+ 2434              	.LCFI15:
+ 2435              		.cfi_def_cfa_offset 24
+ 2436              		@ sp needed
+ 2437 00c2 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 2438              	.L115:
+ 2439 00c6 00BF     		.align	2
+ 2440              	.L114:
+ 2441 00c8 00380240 		.word	1073887232
+ 2442 00cc 00100240 		.word	1073876992
+ARM GAS  /tmp/ccdsDELB.s 			page 178
+
+
+ 2443 00d0 00340140 		.word	1073820672
+ 2444              		.cfi_endproc
+ 2445              	.LFE1192:
+ 2447              		.section	.text.MX_SPI2_Init,"ax",%progbits
+ 2448              		.align	1
+ 2449              		.syntax unified
+ 2450              		.thumb
+ 2451              		.thumb_func
+ 2452              		.fpu fpv5-d16
+ 2454              	MX_SPI2_Init:
+ 2455              	.LFB1191:
+ 773:Src/main.c    **** 
+ 2456              		.loc 2 773 1 is_stmt 1 view -0
+ 2457              		.cfi_startproc
+ 2458              		@ args = 0, pretend = 0, frame = 72
+ 2459              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2460 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 2461              	.LCFI16:
+ 2462              		.cfi_def_cfa_offset 24
+ 2463              		.cfi_offset 4, -24
+ 2464              		.cfi_offset 5, -20
+ 2465              		.cfi_offset 6, -16
+ 2466              		.cfi_offset 7, -12
+ 2467              		.cfi_offset 8, -8
+ 2468              		.cfi_offset 14, -4
+ 2469 0004 92B0     		sub	sp, sp, #72
+ 2470              	.LCFI17:
+ 2471              		.cfi_def_cfa_offset 96
+ 779:Src/main.c    **** 
+ 2472              		.loc 2 779 3 view .LVU847
+ 779:Src/main.c    **** 
+ 2473              		.loc 2 779 22 is_stmt 0 view .LVU848
+ 2474 0006 2822     		movs	r2, #40
+ 2475 0008 0021     		movs	r1, #0
+ 2476 000a 08A8     		add	r0, sp, #32
+ 2477 000c FFF7FEFF 		bl	memset
+ 2478              	.LVL207:
+ 781:Src/main.c    **** 
+ 2479              		.loc 2 781 3 is_stmt 1 view .LVU849
+ 781:Src/main.c    **** 
+ 2480              		.loc 2 781 23 is_stmt 0 view .LVU850
+ 2481 0010 0024     		movs	r4, #0
+ 2482 0012 0294     		str	r4, [sp, #8]
+ 2483 0014 0394     		str	r4, [sp, #12]
+ 2484 0016 0494     		str	r4, [sp, #16]
+ 2485 0018 0594     		str	r4, [sp, #20]
+ 2486 001a 0694     		str	r4, [sp, #24]
+ 2487 001c 0794     		str	r4, [sp, #28]
+ 784:Src/main.c    **** 
+ 2488              		.loc 2 784 3 is_stmt 1 view .LVU851
+ 2489              	.LVL208:
+ 2490              	.LBB372:
+ 2491              	.LBI372:
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 2492              		.loc 3 1071 22 view .LVU852
+ 2493              	.LBB373:
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1ENR, Periphs);
+ARM GAS  /tmp/ccdsDELB.s 			page 179
+
+
+ 2494              		.loc 3 1073 3 view .LVU853
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 2495              		.loc 3 1074 3 view .LVU854
+ 2496 001e 294B     		ldr	r3, .L118
+ 2497 0020 1A6C     		ldr	r2, [r3, #64]
+ 2498 0022 42F48042 		orr	r2, r2, #16384
+ 2499 0026 1A64     		str	r2, [r3, #64]
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2500              		.loc 3 1076 3 view .LVU855
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2501              		.loc 3 1076 12 is_stmt 0 view .LVU856
+ 2502 0028 1A6C     		ldr	r2, [r3, #64]
+ 2503 002a 02F48042 		and	r2, r2, #16384
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2504              		.loc 3 1076 10 view .LVU857
+ 2505 002e 0192     		str	r2, [sp, #4]
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 2506              		.loc 3 1077 3 is_stmt 1 view .LVU858
+ 2507 0030 019A     		ldr	r2, [sp, #4]
+ 2508              	.LVL209:
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 2509              		.loc 3 1077 3 is_stmt 0 view .LVU859
+ 2510              	.LBE373:
+ 2511              	.LBE372:
+ 786:Src/main.c    ****   /**SPI2 GPIO Configuration
+ 2512              		.loc 2 786 3 is_stmt 1 view .LVU860
+ 2513              	.LBB374:
+ 2514              	.LBI374:
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 2515              		.loc 3 309 22 view .LVU861
+ 2516              	.LBB375:
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1ENR, Periphs);
+ 2517              		.loc 3 311 3 view .LVU862
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 2518              		.loc 3 312 3 view .LVU863
+ 2519 0032 1A6B     		ldr	r2, [r3, #48]
+ 2520 0034 42F00202 		orr	r2, r2, #2
+ 2521 0038 1A63     		str	r2, [r3, #48]
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2522              		.loc 3 314 3 view .LVU864
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2523              		.loc 3 314 12 is_stmt 0 view .LVU865
+ 2524 003a 1B6B     		ldr	r3, [r3, #48]
+ 2525 003c 03F00203 		and	r3, r3, #2
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2526              		.loc 3 314 10 view .LVU866
+ 2527 0040 0093     		str	r3, [sp]
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 2528              		.loc 3 315 3 is_stmt 1 view .LVU867
+ 2529 0042 009B     		ldr	r3, [sp]
+ 2530              	.LVL210:
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 2531              		.loc 3 315 3 is_stmt 0 view .LVU868
+ 2532              	.LBE375:
+ 2533              	.LBE374:
+ 791:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2534              		.loc 2 791 3 is_stmt 1 view .LVU869
+ARM GAS  /tmp/ccdsDELB.s 			page 180
+
+
+ 791:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2535              		.loc 2 791 23 is_stmt 0 view .LVU870
+ 2536 0044 4FF40053 		mov	r3, #8192
+ 2537 0048 0293     		str	r3, [sp, #8]
+ 792:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2538              		.loc 2 792 3 is_stmt 1 view .LVU871
+ 792:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2539              		.loc 2 792 24 is_stmt 0 view .LVU872
+ 2540 004a 0225     		movs	r5, #2
+ 2541 004c 0395     		str	r5, [sp, #12]
+ 793:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2542              		.loc 2 793 3 is_stmt 1 view .LVU873
+ 793:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2543              		.loc 2 793 25 is_stmt 0 view .LVU874
+ 2544 004e 4FF00308 		mov	r8, #3
+ 2545 0052 CDF81080 		str	r8, [sp, #16]
+ 794:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 2546              		.loc 2 794 3 is_stmt 1 view .LVU875
+ 795:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 2547              		.loc 2 795 3 view .LVU876
+ 796:Src/main.c    ****   LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 2548              		.loc 2 796 3 view .LVU877
+ 796:Src/main.c    ****   LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 2549              		.loc 2 796 29 is_stmt 0 view .LVU878
+ 2550 0056 0527     		movs	r7, #5
+ 2551 0058 0797     		str	r7, [sp, #28]
+ 797:Src/main.c    **** 
+ 2552              		.loc 2 797 3 is_stmt 1 view .LVU879
+ 2553 005a 1B4E     		ldr	r6, .L118+4
+ 2554 005c 02A9     		add	r1, sp, #8
+ 2555 005e 3046     		mov	r0, r6
+ 2556 0060 FFF7FEFF 		bl	LL_GPIO_Init
+ 2557              	.LVL211:
+ 799:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2558              		.loc 2 799 3 view .LVU880
+ 799:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2559              		.loc 2 799 23 is_stmt 0 view .LVU881
+ 2560 0064 4FF40043 		mov	r3, #32768
+ 2561 0068 0293     		str	r3, [sp, #8]
+ 800:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2562              		.loc 2 800 3 is_stmt 1 view .LVU882
+ 800:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2563              		.loc 2 800 24 is_stmt 0 view .LVU883
+ 2564 006a 0395     		str	r5, [sp, #12]
+ 801:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2565              		.loc 2 801 3 is_stmt 1 view .LVU884
+ 801:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2566              		.loc 2 801 25 is_stmt 0 view .LVU885
+ 2567 006c CDF81080 		str	r8, [sp, #16]
+ 802:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 2568              		.loc 2 802 3 is_stmt 1 view .LVU886
+ 802:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 2569              		.loc 2 802 30 is_stmt 0 view .LVU887
+ 2570 0070 0594     		str	r4, [sp, #20]
+ 803:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 2571              		.loc 2 803 3 is_stmt 1 view .LVU888
+ 803:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ARM GAS  /tmp/ccdsDELB.s 			page 181
+
+
+ 2572              		.loc 2 803 24 is_stmt 0 view .LVU889
+ 2573 0072 0694     		str	r4, [sp, #24]
+ 804:Src/main.c    ****   LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 2574              		.loc 2 804 3 is_stmt 1 view .LVU890
+ 804:Src/main.c    ****   LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 2575              		.loc 2 804 29 is_stmt 0 view .LVU891
+ 2576 0074 0797     		str	r7, [sp, #28]
+ 805:Src/main.c    **** 
+ 2577              		.loc 2 805 3 is_stmt 1 view .LVU892
+ 2578 0076 02A9     		add	r1, sp, #8
+ 2579 0078 3046     		mov	r0, r6
+ 2580 007a FFF7FEFF 		bl	LL_GPIO_Init
+ 2581              	.LVL212:
+ 811:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ 2582              		.loc 2 811 3 view .LVU893
+ 811:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ 2583              		.loc 2 811 36 is_stmt 0 view .LVU894
+ 2584 007e 0894     		str	r4, [sp, #32]
+ 812:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+ 2585              		.loc 2 812 3 is_stmt 1 view .LVU895
+ 812:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+ 2586              		.loc 2 812 23 is_stmt 0 view .LVU896
+ 2587 0080 4FF48273 		mov	r3, #260
+ 2588 0084 0993     		str	r3, [sp, #36]
+ 813:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+ 2589              		.loc 2 813 3 is_stmt 1 view .LVU897
+ 813:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+ 2590              		.loc 2 813 28 is_stmt 0 view .LVU898
+ 2591 0086 4FF47063 		mov	r3, #3840
+ 2592 008a 0A93     		str	r3, [sp, #40]
+ 814:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE;
+ 2593              		.loc 2 814 3 is_stmt 1 view .LVU899
+ 814:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE;
+ 2594              		.loc 2 814 32 is_stmt 0 view .LVU900
+ 2595 008c 0B95     		str	r5, [sp, #44]
+ 815:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ 2596              		.loc 2 815 3 is_stmt 1 view .LVU901
+ 815:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ 2597              		.loc 2 815 29 is_stmt 0 view .LVU902
+ 2598 008e 0123     		movs	r3, #1
+ 2599 0090 0C93     		str	r3, [sp, #48]
+ 816:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8;
+ 2600              		.loc 2 816 3 is_stmt 1 view .LVU903
+ 816:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8;
+ 2601              		.loc 2 816 22 is_stmt 0 view .LVU904
+ 2602 0092 4FF40073 		mov	r3, #512
+ 2603 0096 0D93     		str	r3, [sp, #52]
+ 817:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ 2604              		.loc 2 817 3 is_stmt 1 view .LVU905
+ 817:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ 2605              		.loc 2 817 27 is_stmt 0 view .LVU906
+ 2606 0098 1023     		movs	r3, #16
+ 2607 009a 0E93     		str	r3, [sp, #56]
+ 818:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ 2608              		.loc 2 818 3 is_stmt 1 view .LVU907
+ 818:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ 2609              		.loc 2 818 27 is_stmt 0 view .LVU908
+ARM GAS  /tmp/ccdsDELB.s 			page 182
+
+
+ 2610 009c 0F94     		str	r4, [sp, #60]
+ 819:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+ 2611              		.loc 2 819 3 is_stmt 1 view .LVU909
+ 819:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+ 2612              		.loc 2 819 33 is_stmt 0 view .LVU910
+ 2613 009e 1094     		str	r4, [sp, #64]
+ 820:Src/main.c    ****   LL_SPI_Init(SPI2, &SPI_InitStruct);
+ 2614              		.loc 2 820 3 is_stmt 1 view .LVU911
+ 820:Src/main.c    ****   LL_SPI_Init(SPI2, &SPI_InitStruct);
+ 2615              		.loc 2 820 26 is_stmt 0 view .LVU912
+ 2616 00a0 0723     		movs	r3, #7
+ 2617 00a2 1193     		str	r3, [sp, #68]
+ 821:Src/main.c    ****   LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA);
+ 2618              		.loc 2 821 3 is_stmt 1 view .LVU913
+ 2619 00a4 094C     		ldr	r4, .L118+8
+ 2620 00a6 08A9     		add	r1, sp, #32
+ 2621 00a8 2046     		mov	r0, r4
+ 2622 00aa FFF7FEFF 		bl	LL_SPI_Init
+ 2623              	.LVL213:
+ 822:Src/main.c    ****   LL_SPI_DisableNSSPulseMgt(SPI2);
+ 2624              		.loc 2 822 3 view .LVU914
+ 2625              	.LBB376:
+ 2626              	.LBI376:
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 2627              		.loc 4 426 22 view .LVU915
+ 2628              	.LBB377:
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2629              		.loc 4 428 3 view .LVU916
+ 2630 00ae 6368     		ldr	r3, [r4, #4]
+ 2631 00b0 23F01003 		bic	r3, r3, #16
+ 2632 00b4 6360     		str	r3, [r4, #4]
+ 2633              	.LVL214:
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2634              		.loc 4 428 3 is_stmt 0 view .LVU917
+ 2635              	.LBE377:
+ 2636              	.LBE376:
+ 823:Src/main.c    ****   /* USER CODE BEGIN SPI2_Init 2 */
+ 2637              		.loc 2 823 3 is_stmt 1 view .LVU918
+ 2638              	.LBB378:
+ 2639              	.LBI378:
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 2640              		.loc 4 874 22 view .LVU919
+ 2641              	.LBB379:
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2642              		.loc 4 876 3 view .LVU920
+ 2643 00b6 6368     		ldr	r3, [r4, #4]
+ 2644 00b8 23F00803 		bic	r3, r3, #8
+ 2645 00bc 6360     		str	r3, [r4, #4]
+ 2646              	.LVL215:
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2647              		.loc 4 876 3 is_stmt 0 view .LVU921
+ 2648              	.LBE379:
+ 2649              	.LBE378:
+ 828:Src/main.c    **** 
+ 2650              		.loc 2 828 1 view .LVU922
+ 2651 00be 12B0     		add	sp, sp, #72
+ 2652              	.LCFI18:
+ARM GAS  /tmp/ccdsDELB.s 			page 183
+
+
+ 2653              		.cfi_def_cfa_offset 24
+ 2654              		@ sp needed
+ 2655 00c0 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 2656              	.L119:
+ 2657              		.align	2
+ 2658              	.L118:
+ 2659 00c4 00380240 		.word	1073887232
+ 2660 00c8 00040240 		.word	1073873920
+ 2661 00cc 00380040 		.word	1073756160
+ 2662              		.cfi_endproc
+ 2663              	.LFE1191:
+ 2665              		.section	.text.MX_SPI5_Init,"ax",%progbits
+ 2666              		.align	1
+ 2667              		.syntax unified
+ 2668              		.thumb
+ 2669              		.thumb_func
+ 2670              		.fpu fpv5-d16
+ 2672              	MX_SPI5_Init:
+ 2673              	.LFB1193:
+ 899:Src/main.c    **** 
+ 2674              		.loc 2 899 1 is_stmt 1 view -0
+ 2675              		.cfi_startproc
+ 2676              		@ args = 0, pretend = 0, frame = 72
+ 2677              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2678 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 2679              	.LCFI19:
+ 2680              		.cfi_def_cfa_offset 24
+ 2681              		.cfi_offset 4, -24
+ 2682              		.cfi_offset 5, -20
+ 2683              		.cfi_offset 6, -16
+ 2684              		.cfi_offset 7, -12
+ 2685              		.cfi_offset 8, -8
+ 2686              		.cfi_offset 14, -4
+ 2687 0004 92B0     		sub	sp, sp, #72
+ 2688              	.LCFI20:
+ 2689              		.cfi_def_cfa_offset 96
+ 905:Src/main.c    **** 
+ 2690              		.loc 2 905 3 view .LVU924
+ 905:Src/main.c    **** 
+ 2691              		.loc 2 905 22 is_stmt 0 view .LVU925
+ 2692 0006 2822     		movs	r2, #40
+ 2693 0008 0021     		movs	r1, #0
+ 2694 000a 08A8     		add	r0, sp, #32
+ 2695 000c FFF7FEFF 		bl	memset
+ 2696              	.LVL216:
+ 907:Src/main.c    **** 
+ 2697              		.loc 2 907 3 is_stmt 1 view .LVU926
+ 907:Src/main.c    **** 
+ 2698              		.loc 2 907 23 is_stmt 0 view .LVU927
+ 2699 0010 0024     		movs	r4, #0
+ 2700 0012 0294     		str	r4, [sp, #8]
+ 2701 0014 0394     		str	r4, [sp, #12]
+ 2702 0016 0494     		str	r4, [sp, #16]
+ 2703 0018 0594     		str	r4, [sp, #20]
+ 2704 001a 0694     		str	r4, [sp, #24]
+ 2705 001c 0794     		str	r4, [sp, #28]
+ 910:Src/main.c    **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 184
+
+
+ 2706              		.loc 2 910 3 is_stmt 1 view .LVU928
+ 2707              	.LVL217:
+ 2708              	.LBB380:
+ 2709              	.LBI380:
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 2710              		.loc 3 1587 22 view .LVU929
+ 2711              	.LBB381:
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB2ENR, Periphs);
+ 2712              		.loc 3 1589 3 view .LVU930
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 2713              		.loc 3 1590 3 view .LVU931
+ 2714 001e 294B     		ldr	r3, .L122
+ 2715 0020 5A6C     		ldr	r2, [r3, #68]
+ 2716 0022 42F48012 		orr	r2, r2, #1048576
+ 2717 0026 5A64     		str	r2, [r3, #68]
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2718              		.loc 3 1592 3 view .LVU932
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2719              		.loc 3 1592 12 is_stmt 0 view .LVU933
+ 2720 0028 5A6C     		ldr	r2, [r3, #68]
+ 2721 002a 02F48012 		and	r2, r2, #1048576
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2722              		.loc 3 1592 10 view .LVU934
+ 2723 002e 0192     		str	r2, [sp, #4]
+ 2724              		.loc 3 1593 3 is_stmt 1 view .LVU935
+ 2725 0030 019A     		ldr	r2, [sp, #4]
+ 2726              	.LVL218:
+ 2727              		.loc 3 1593 3 is_stmt 0 view .LVU936
+ 2728              	.LBE381:
+ 2729              	.LBE380:
+ 912:Src/main.c    ****   /**SPI5 GPIO Configuration
+ 2730              		.loc 2 912 3 is_stmt 1 view .LVU937
+ 2731              	.LBB382:
+ 2732              	.LBI382:
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 2733              		.loc 3 309 22 view .LVU938
+ 2734              	.LBB383:
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1ENR, Periphs);
+ 2735              		.loc 3 311 3 view .LVU939
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 2736              		.loc 3 312 3 view .LVU940
+ 2737 0032 1A6B     		ldr	r2, [r3, #48]
+ 2738 0034 42F02002 		orr	r2, r2, #32
+ 2739 0038 1A63     		str	r2, [r3, #48]
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2740              		.loc 3 314 3 view .LVU941
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2741              		.loc 3 314 12 is_stmt 0 view .LVU942
+ 2742 003a 1B6B     		ldr	r3, [r3, #48]
+ 2743 003c 03F02003 		and	r3, r3, #32
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2744              		.loc 3 314 10 view .LVU943
+ 2745 0040 0093     		str	r3, [sp]
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 2746              		.loc 3 315 3 is_stmt 1 view .LVU944
+ 2747 0042 009B     		ldr	r3, [sp]
+ 2748              	.LVL219:
+ARM GAS  /tmp/ccdsDELB.s 			page 185
+
+
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 2749              		.loc 3 315 3 is_stmt 0 view .LVU945
+ 2750              	.LBE383:
+ 2751              	.LBE382:
+ 917:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2752              		.loc 2 917 3 is_stmt 1 view .LVU946
+ 917:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2753              		.loc 2 917 23 is_stmt 0 view .LVU947
+ 2754 0044 8023     		movs	r3, #128
+ 2755 0046 0293     		str	r3, [sp, #8]
+ 918:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2756              		.loc 2 918 3 is_stmt 1 view .LVU948
+ 918:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2757              		.loc 2 918 24 is_stmt 0 view .LVU949
+ 2758 0048 0225     		movs	r5, #2
+ 2759 004a 0395     		str	r5, [sp, #12]
+ 919:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2760              		.loc 2 919 3 is_stmt 1 view .LVU950
+ 919:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2761              		.loc 2 919 25 is_stmt 0 view .LVU951
+ 2762 004c 4FF00308 		mov	r8, #3
+ 2763 0050 CDF81080 		str	r8, [sp, #16]
+ 920:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 2764              		.loc 2 920 3 is_stmt 1 view .LVU952
+ 921:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 2765              		.loc 2 921 3 view .LVU953
+ 922:Src/main.c    ****   LL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 2766              		.loc 2 922 3 view .LVU954
+ 922:Src/main.c    ****   LL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 2767              		.loc 2 922 29 is_stmt 0 view .LVU955
+ 2768 0054 0527     		movs	r7, #5
+ 2769 0056 0797     		str	r7, [sp, #28]
+ 923:Src/main.c    **** 
+ 2770              		.loc 2 923 3 is_stmt 1 view .LVU956
+ 2771 0058 1B4E     		ldr	r6, .L122+4
+ 2772 005a 02A9     		add	r1, sp, #8
+ 2773 005c 3046     		mov	r0, r6
+ 2774 005e FFF7FEFF 		bl	LL_GPIO_Init
+ 2775              	.LVL220:
+ 925:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2776              		.loc 2 925 3 view .LVU957
+ 925:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2777              		.loc 2 925 23 is_stmt 0 view .LVU958
+ 2778 0062 4FF48073 		mov	r3, #256
+ 2779 0066 0293     		str	r3, [sp, #8]
+ 926:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2780              		.loc 2 926 3 is_stmt 1 view .LVU959
+ 926:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2781              		.loc 2 926 24 is_stmt 0 view .LVU960
+ 2782 0068 0395     		str	r5, [sp, #12]
+ 927:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2783              		.loc 2 927 3 is_stmt 1 view .LVU961
+ 927:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2784              		.loc 2 927 25 is_stmt 0 view .LVU962
+ 2785 006a CDF81080 		str	r8, [sp, #16]
+ 928:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 2786              		.loc 2 928 3 is_stmt 1 view .LVU963
+ARM GAS  /tmp/ccdsDELB.s 			page 186
+
+
+ 928:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 2787              		.loc 2 928 30 is_stmt 0 view .LVU964
+ 2788 006e 0594     		str	r4, [sp, #20]
+ 929:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 2789              		.loc 2 929 3 is_stmt 1 view .LVU965
+ 929:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ 2790              		.loc 2 929 24 is_stmt 0 view .LVU966
+ 2791 0070 0694     		str	r4, [sp, #24]
+ 930:Src/main.c    ****   LL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 2792              		.loc 2 930 3 is_stmt 1 view .LVU967
+ 930:Src/main.c    ****   LL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 2793              		.loc 2 930 29 is_stmt 0 view .LVU968
+ 2794 0072 0797     		str	r7, [sp, #28]
+ 931:Src/main.c    **** 
+ 2795              		.loc 2 931 3 is_stmt 1 view .LVU969
+ 2796 0074 02A9     		add	r1, sp, #8
+ 2797 0076 3046     		mov	r0, r6
+ 2798 0078 FFF7FEFF 		bl	LL_GPIO_Init
+ 2799              	.LVL221:
+ 937:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ 2800              		.loc 2 937 3 view .LVU970
+ 937:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ 2801              		.loc 2 937 36 is_stmt 0 view .LVU971
+ 2802 007c 4FF48063 		mov	r3, #1024
+ 2803 0080 0893     		str	r3, [sp, #32]
+ 938:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+ 2804              		.loc 2 938 3 is_stmt 1 view .LVU972
+ 938:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+ 2805              		.loc 2 938 23 is_stmt 0 view .LVU973
+ 2806 0082 4FF48273 		mov	r3, #260
+ 2807 0086 0993     		str	r3, [sp, #36]
+ 939:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+ 2808              		.loc 2 939 3 is_stmt 1 view .LVU974
+ 939:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+ 2809              		.loc 2 939 28 is_stmt 0 view .LVU975
+ 2810 0088 4FF47063 		mov	r3, #3840
+ 2811 008c 0A93     		str	r3, [sp, #40]
+ 940:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
+ 2812              		.loc 2 940 3 is_stmt 1 view .LVU976
+ 940:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
+ 2813              		.loc 2 940 32 is_stmt 0 view .LVU977
+ 2814 008e 0B95     		str	r5, [sp, #44]
+ 941:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ 2815              		.loc 2 941 3 is_stmt 1 view .LVU978
+ 941:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ 2816              		.loc 2 941 29 is_stmt 0 view .LVU979
+ 2817 0090 0C94     		str	r4, [sp, #48]
+ 942:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+ 2818              		.loc 2 942 3 is_stmt 1 view .LVU980
+ 942:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+ 2819              		.loc 2 942 22 is_stmt 0 view .LVU981
+ 2820 0092 4FF40073 		mov	r3, #512
+ 2821 0096 0D93     		str	r3, [sp, #52]
+ 943:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ 2822              		.loc 2 943 3 is_stmt 1 view .LVU982
+ 943:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ 2823              		.loc 2 943 27 is_stmt 0 view .LVU983
+ARM GAS  /tmp/ccdsDELB.s 			page 187
+
+
+ 2824 0098 1823     		movs	r3, #24
+ 2825 009a 0E93     		str	r3, [sp, #56]
+ 944:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ 2826              		.loc 2 944 3 is_stmt 1 view .LVU984
+ 944:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ 2827              		.loc 2 944 27 is_stmt 0 view .LVU985
+ 2828 009c 0F94     		str	r4, [sp, #60]
+ 945:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+ 2829              		.loc 2 945 3 is_stmt 1 view .LVU986
+ 945:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+ 2830              		.loc 2 945 33 is_stmt 0 view .LVU987
+ 2831 009e 1094     		str	r4, [sp, #64]
+ 946:Src/main.c    ****   LL_SPI_Init(SPI5, &SPI_InitStruct);
+ 2832              		.loc 2 946 3 is_stmt 1 view .LVU988
+ 946:Src/main.c    ****   LL_SPI_Init(SPI5, &SPI_InitStruct);
+ 2833              		.loc 2 946 26 is_stmt 0 view .LVU989
+ 2834 00a0 0723     		movs	r3, #7
+ 2835 00a2 1193     		str	r3, [sp, #68]
+ 947:Src/main.c    ****   LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA);
+ 2836              		.loc 2 947 3 is_stmt 1 view .LVU990
+ 2837 00a4 094C     		ldr	r4, .L122+8
+ 2838 00a6 08A9     		add	r1, sp, #32
+ 2839 00a8 2046     		mov	r0, r4
+ 2840 00aa FFF7FEFF 		bl	LL_SPI_Init
+ 2841              	.LVL222:
+ 948:Src/main.c    ****   LL_SPI_DisableNSSPulseMgt(SPI5);
+ 2842              		.loc 2 948 3 view .LVU991
+ 2843              	.LBB384:
+ 2844              	.LBI384:
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 2845              		.loc 4 426 22 view .LVU992
+ 2846              	.LBB385:
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2847              		.loc 4 428 3 view .LVU993
+ 2848 00ae 6368     		ldr	r3, [r4, #4]
+ 2849 00b0 23F01003 		bic	r3, r3, #16
+ 2850 00b4 6360     		str	r3, [r4, #4]
+ 2851              	.LVL223:
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2852              		.loc 4 428 3 is_stmt 0 view .LVU994
+ 2853              	.LBE385:
+ 2854              	.LBE384:
+ 949:Src/main.c    ****   /* USER CODE BEGIN SPI5_Init 2 */
+ 2855              		.loc 2 949 3 is_stmt 1 view .LVU995
+ 2856              	.LBB386:
+ 2857              	.LBI386:
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 2858              		.loc 4 874 22 view .LVU996
+ 2859              	.LBB387:
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2860              		.loc 4 876 3 view .LVU997
+ 2861 00b6 6368     		ldr	r3, [r4, #4]
+ 2862 00b8 23F00803 		bic	r3, r3, #8
+ 2863 00bc 6360     		str	r3, [r4, #4]
+ 2864              	.LVL224:
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 2865              		.loc 4 876 3 is_stmt 0 view .LVU998
+ARM GAS  /tmp/ccdsDELB.s 			page 188
+
+
+ 2866              	.LBE387:
+ 2867              	.LBE386:
+ 954:Src/main.c    **** 
+ 2868              		.loc 2 954 1 view .LVU999
+ 2869 00be 12B0     		add	sp, sp, #72
+ 2870              	.LCFI21:
+ 2871              		.cfi_def_cfa_offset 24
+ 2872              		@ sp needed
+ 2873 00c0 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 2874              	.L123:
+ 2875              		.align	2
+ 2876              	.L122:
+ 2877 00c4 00380240 		.word	1073887232
+ 2878 00c8 00140240 		.word	1073878016
+ 2879 00cc 00500140 		.word	1073827840
+ 2880              		.cfi_endproc
+ 2881              	.LFE1193:
+ 2883              		.section	.text.MX_SPI6_Init,"ax",%progbits
+ 2884              		.align	1
+ 2885              		.syntax unified
+ 2886              		.thumb
+ 2887              		.thumb_func
+ 2888              		.fpu fpv5-d16
+ 2890              	MX_SPI6_Init:
+ 2891              	.LFB1194:
+ 962:Src/main.c    **** 
+ 2892              		.loc 2 962 1 is_stmt 1 view -0
+ 2893              		.cfi_startproc
+ 2894              		@ args = 0, pretend = 0, frame = 72
+ 2895              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2896 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 2897              	.LCFI22:
+ 2898              		.cfi_def_cfa_offset 24
+ 2899              		.cfi_offset 4, -24
+ 2900              		.cfi_offset 5, -20
+ 2901              		.cfi_offset 6, -16
+ 2902              		.cfi_offset 7, -12
+ 2903              		.cfi_offset 8, -8
+ 2904              		.cfi_offset 14, -4
+ 2905 0004 92B0     		sub	sp, sp, #72
+ 2906              	.LCFI23:
+ 2907              		.cfi_def_cfa_offset 96
+ 968:Src/main.c    **** 
+ 2908              		.loc 2 968 3 view .LVU1001
+ 968:Src/main.c    **** 
+ 2909              		.loc 2 968 22 is_stmt 0 view .LVU1002
+ 2910 0006 2822     		movs	r2, #40
+ 2911 0008 0021     		movs	r1, #0
+ 2912 000a 08A8     		add	r0, sp, #32
+ 2913 000c FFF7FEFF 		bl	memset
+ 2914              	.LVL225:
+ 970:Src/main.c    **** 
+ 2915              		.loc 2 970 3 is_stmt 1 view .LVU1003
+ 970:Src/main.c    **** 
+ 2916              		.loc 2 970 23 is_stmt 0 view .LVU1004
+ 2917 0010 0024     		movs	r4, #0
+ 2918 0012 0294     		str	r4, [sp, #8]
+ARM GAS  /tmp/ccdsDELB.s 			page 189
+
+
+ 2919 0014 0394     		str	r4, [sp, #12]
+ 2920 0016 0494     		str	r4, [sp, #16]
+ 2921 0018 0594     		str	r4, [sp, #20]
+ 2922 001a 0694     		str	r4, [sp, #24]
+ 2923 001c 0794     		str	r4, [sp, #28]
+ 973:Src/main.c    **** 
+ 2924              		.loc 2 973 3 is_stmt 1 view .LVU1005
+ 2925              	.LVL226:
+ 2926              	.LBB388:
+ 2927              	.LBI388:
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 2928              		.loc 3 1587 22 view .LVU1006
+ 2929              	.LBB389:
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB2ENR, Periphs);
+ 2930              		.loc 3 1589 3 view .LVU1007
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 2931              		.loc 3 1590 3 view .LVU1008
+ 2932 001e 294B     		ldr	r3, .L126
+ 2933 0020 5A6C     		ldr	r2, [r3, #68]
+ 2934 0022 42F40012 		orr	r2, r2, #2097152
+ 2935 0026 5A64     		str	r2, [r3, #68]
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2936              		.loc 3 1592 3 view .LVU1009
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2937              		.loc 3 1592 12 is_stmt 0 view .LVU1010
+ 2938 0028 5A6C     		ldr	r2, [r3, #68]
+ 2939 002a 02F40012 		and	r2, r2, #2097152
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2940              		.loc 3 1592 10 view .LVU1011
+ 2941 002e 0192     		str	r2, [sp, #4]
+ 2942              		.loc 3 1593 3 is_stmt 1 view .LVU1012
+ 2943 0030 019A     		ldr	r2, [sp, #4]
+ 2944              	.LVL227:
+ 2945              		.loc 3 1593 3 is_stmt 0 view .LVU1013
+ 2946              	.LBE389:
+ 2947              	.LBE388:
+ 975:Src/main.c    ****   /**SPI6 GPIO Configuration
+ 2948              		.loc 2 975 3 is_stmt 1 view .LVU1014
+ 2949              	.LBB390:
+ 2950              	.LBI390:
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 2951              		.loc 3 309 22 view .LVU1015
+ 2952              	.LBB391:
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1ENR, Periphs);
+ 2953              		.loc 3 311 3 view .LVU1016
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 2954              		.loc 3 312 3 view .LVU1017
+ 2955 0032 1A6B     		ldr	r2, [r3, #48]
+ 2956 0034 42F00102 		orr	r2, r2, #1
+ 2957 0038 1A63     		str	r2, [r3, #48]
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2958              		.loc 3 314 3 view .LVU1018
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 2959              		.loc 3 314 12 is_stmt 0 view .LVU1019
+ 2960 003a 1B6B     		ldr	r3, [r3, #48]
+ 2961 003c 03F00103 		and	r3, r3, #1
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ARM GAS  /tmp/ccdsDELB.s 			page 190
+
+
+ 2962              		.loc 3 314 10 view .LVU1020
+ 2963 0040 0093     		str	r3, [sp]
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 2964              		.loc 3 315 3 is_stmt 1 view .LVU1021
+ 2965 0042 009B     		ldr	r3, [sp]
+ 2966              	.LVL228:
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 2967              		.loc 3 315 3 is_stmt 0 view .LVU1022
+ 2968              	.LBE391:
+ 2969              	.LBE390:
+ 980:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2970              		.loc 2 980 3 is_stmt 1 view .LVU1023
+ 980:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2971              		.loc 2 980 23 is_stmt 0 view .LVU1024
+ 2972 0044 2023     		movs	r3, #32
+ 2973 0046 0293     		str	r3, [sp, #8]
+ 981:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2974              		.loc 2 981 3 is_stmt 1 view .LVU1025
+ 981:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2975              		.loc 2 981 24 is_stmt 0 view .LVU1026
+ 2976 0048 0225     		movs	r5, #2
+ 2977 004a 0395     		str	r5, [sp, #12]
+ 982:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2978              		.loc 2 982 3 is_stmt 1 view .LVU1027
+ 982:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 2979              		.loc 2 982 25 is_stmt 0 view .LVU1028
+ 2980 004c 4FF00308 		mov	r8, #3
+ 2981 0050 CDF81080 		str	r8, [sp, #16]
+ 983:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 2982              		.loc 2 983 3 is_stmt 1 view .LVU1029
+ 984:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_8;
+ 2983              		.loc 2 984 3 view .LVU1030
+ 985:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 2984              		.loc 2 985 3 view .LVU1031
+ 985:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 2985              		.loc 2 985 29 is_stmt 0 view .LVU1032
+ 2986 0054 0827     		movs	r7, #8
+ 2987 0056 0797     		str	r7, [sp, #28]
+ 986:Src/main.c    **** 
+ 2988              		.loc 2 986 3 is_stmt 1 view .LVU1033
+ 2989 0058 1B4E     		ldr	r6, .L126+4
+ 2990 005a 0DEB0701 		add	r1, sp, r7
+ 2991 005e 3046     		mov	r0, r6
+ 2992 0060 FFF7FEFF 		bl	LL_GPIO_Init
+ 2993              	.LVL229:
+ 988:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2994              		.loc 2 988 3 view .LVU1034
+ 988:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 2995              		.loc 2 988 23 is_stmt 0 view .LVU1035
+ 2996 0064 8023     		movs	r3, #128
+ 2997 0066 0293     		str	r3, [sp, #8]
+ 989:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2998              		.loc 2 989 3 is_stmt 1 view .LVU1036
+ 989:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 2999              		.loc 2 989 24 is_stmt 0 view .LVU1037
+ 3000 0068 0395     		str	r5, [sp, #12]
+ 990:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ARM GAS  /tmp/ccdsDELB.s 			page 191
+
+
+ 3001              		.loc 2 990 3 is_stmt 1 view .LVU1038
+ 990:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 3002              		.loc 2 990 25 is_stmt 0 view .LVU1039
+ 3003 006a CDF81080 		str	r8, [sp, #16]
+ 991:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 3004              		.loc 2 991 3 is_stmt 1 view .LVU1040
+ 991:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 3005              		.loc 2 991 30 is_stmt 0 view .LVU1041
+ 3006 006e 0594     		str	r4, [sp, #20]
+ 992:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_8;
+ 3007              		.loc 2 992 3 is_stmt 1 view .LVU1042
+ 992:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_8;
+ 3008              		.loc 2 992 24 is_stmt 0 view .LVU1043
+ 3009 0070 0694     		str	r4, [sp, #24]
+ 993:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 3010              		.loc 2 993 3 is_stmt 1 view .LVU1044
+ 993:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 3011              		.loc 2 993 29 is_stmt 0 view .LVU1045
+ 3012 0072 0797     		str	r7, [sp, #28]
+ 994:Src/main.c    **** 
+ 3013              		.loc 2 994 3 is_stmt 1 view .LVU1046
+ 3014 0074 0DEB0701 		add	r1, sp, r7
+ 3015 0078 3046     		mov	r0, r6
+ 3016 007a FFF7FEFF 		bl	LL_GPIO_Init
+ 3017              	.LVL230:
+1000:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ 3018              		.loc 2 1000 3 view .LVU1047
+1000:Src/main.c    ****   SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ 3019              		.loc 2 1000 36 is_stmt 0 view .LVU1048
+ 3020 007e 0894     		str	r4, [sp, #32]
+1001:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+ 3021              		.loc 2 1001 3 is_stmt 1 view .LVU1049
+1001:Src/main.c    ****   SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
+ 3022              		.loc 2 1001 23 is_stmt 0 view .LVU1050
+ 3023 0080 4FF48273 		mov	r3, #260
+ 3024 0084 0993     		str	r3, [sp, #36]
+1002:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+ 3025              		.loc 2 1002 3 is_stmt 1 view .LVU1051
+1002:Src/main.c    ****   SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH;
+ 3026              		.loc 2 1002 28 is_stmt 0 view .LVU1052
+ 3027 0086 4FF47063 		mov	r3, #3840
+ 3028 008a 0A93     		str	r3, [sp, #40]
+1003:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE;
+ 3029              		.loc 2 1003 3 is_stmt 1 view .LVU1053
+1003:Src/main.c    ****   SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE;
+ 3030              		.loc 2 1003 32 is_stmt 0 view .LVU1054
+ 3031 008c 0B95     		str	r5, [sp, #44]
+1004:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ 3032              		.loc 2 1004 3 is_stmt 1 view .LVU1055
+1004:Src/main.c    ****   SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ 3033              		.loc 2 1004 29 is_stmt 0 view .LVU1056
+ 3034 008e 0123     		movs	r3, #1
+ 3035 0090 0C93     		str	r3, [sp, #48]
+1005:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+ 3036              		.loc 2 1005 3 is_stmt 1 view .LVU1057
+1005:Src/main.c    ****   SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16;
+ 3037              		.loc 2 1005 22 is_stmt 0 view .LVU1058
+ARM GAS  /tmp/ccdsDELB.s 			page 192
+
+
+ 3038 0092 4FF40073 		mov	r3, #512
+ 3039 0096 0D93     		str	r3, [sp, #52]
+1006:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ 3040              		.loc 2 1006 3 is_stmt 1 view .LVU1059
+1006:Src/main.c    ****   SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ 3041              		.loc 2 1006 27 is_stmt 0 view .LVU1060
+ 3042 0098 1823     		movs	r3, #24
+ 3043 009a 0E93     		str	r3, [sp, #56]
+1007:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ 3044              		.loc 2 1007 3 is_stmt 1 view .LVU1061
+1007:Src/main.c    ****   SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ 3045              		.loc 2 1007 27 is_stmt 0 view .LVU1062
+ 3046 009c 0F94     		str	r4, [sp, #60]
+1008:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+ 3047              		.loc 2 1008 3 is_stmt 1 view .LVU1063
+1008:Src/main.c    ****   SPI_InitStruct.CRCPoly = 7;
+ 3048              		.loc 2 1008 33 is_stmt 0 view .LVU1064
+ 3049 009e 1094     		str	r4, [sp, #64]
+1009:Src/main.c    ****   LL_SPI_Init(SPI6, &SPI_InitStruct);
+ 3050              		.loc 2 1009 3 is_stmt 1 view .LVU1065
+1009:Src/main.c    ****   LL_SPI_Init(SPI6, &SPI_InitStruct);
+ 3051              		.loc 2 1009 26 is_stmt 0 view .LVU1066
+ 3052 00a0 0723     		movs	r3, #7
+ 3053 00a2 1193     		str	r3, [sp, #68]
+1010:Src/main.c    ****   LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA);
+ 3054              		.loc 2 1010 3 is_stmt 1 view .LVU1067
+ 3055 00a4 094C     		ldr	r4, .L126+8
+ 3056 00a6 08A9     		add	r1, sp, #32
+ 3057 00a8 2046     		mov	r0, r4
+ 3058 00aa FFF7FEFF 		bl	LL_SPI_Init
+ 3059              	.LVL231:
+1011:Src/main.c    ****   LL_SPI_DisableNSSPulseMgt(SPI6);
+ 3060              		.loc 2 1011 3 view .LVU1068
+ 3061              	.LBB392:
+ 3062              	.LBI392:
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 3063              		.loc 4 426 22 view .LVU1069
+ 3064              	.LBB393:
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 3065              		.loc 4 428 3 view .LVU1070
+ 3066 00ae 6368     		ldr	r3, [r4, #4]
+ 3067 00b0 23F01003 		bic	r3, r3, #16
+ 3068 00b4 6360     		str	r3, [r4, #4]
+ 3069              	.LVL232:
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 3070              		.loc 4 428 3 is_stmt 0 view .LVU1071
+ 3071              	.LBE393:
+ 3072              	.LBE392:
+1012:Src/main.c    ****   /* USER CODE BEGIN SPI6_Init 2 */
+ 3073              		.loc 2 1012 3 is_stmt 1 view .LVU1072
+ 3074              	.LBB394:
+ 3075              	.LBI394:
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 3076              		.loc 4 874 22 view .LVU1073
+ 3077              	.LBB395:
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 3078              		.loc 4 876 3 view .LVU1074
+ARM GAS  /tmp/ccdsDELB.s 			page 193
+
+
+ 3079 00b6 6368     		ldr	r3, [r4, #4]
+ 3080 00b8 23F00803 		bic	r3, r3, #8
+ 3081 00bc 6360     		str	r3, [r4, #4]
+ 3082              	.LVL233:
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 3083              		.loc 4 876 3 is_stmt 0 view .LVU1075
+ 3084              	.LBE395:
+ 3085              	.LBE394:
+1017:Src/main.c    **** 
+ 3086              		.loc 2 1017 1 view .LVU1076
+ 3087 00be 12B0     		add	sp, sp, #72
+ 3088              	.LCFI24:
+ 3089              		.cfi_def_cfa_offset 24
+ 3090              		@ sp needed
+ 3091 00c0 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 3092              	.L127:
+ 3093              		.align	2
+ 3094              	.L126:
+ 3095 00c4 00380240 		.word	1073887232
+ 3096 00c8 00000240 		.word	1073872896
+ 3097 00cc 00540140 		.word	1073828864
+ 3098              		.cfi_endproc
+ 3099              	.LFE1194:
+ 3101              		.section	.text.MX_TIM2_Init,"ax",%progbits
+ 3102              		.align	1
+ 3103              		.syntax unified
+ 3104              		.thumb
+ 3105              		.thumb_func
+ 3106              		.fpu fpv5-d16
+ 3108              	MX_TIM2_Init:
+ 3109              	.LFB1195:
+1025:Src/main.c    **** 
+ 3110              		.loc 2 1025 1 is_stmt 1 view -0
+ 3111              		.cfi_startproc
+ 3112              		@ args = 0, pretend = 0, frame = 24
+ 3113              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3114 0000 10B5     		push	{r4, lr}
+ 3115              	.LCFI25:
+ 3116              		.cfi_def_cfa_offset 8
+ 3117              		.cfi_offset 4, -8
+ 3118              		.cfi_offset 14, -4
+ 3119 0002 86B0     		sub	sp, sp, #24
+ 3120              	.LCFI26:
+ 3121              		.cfi_def_cfa_offset 32
+1031:Src/main.c    **** 
+ 3122              		.loc 2 1031 3 view .LVU1078
+1031:Src/main.c    **** 
+ 3123              		.loc 2 1031 22 is_stmt 0 view .LVU1079
+ 3124 0004 0024     		movs	r4, #0
+ 3125 0006 0194     		str	r4, [sp, #4]
+ 3126 0008 0294     		str	r4, [sp, #8]
+ 3127 000a 0394     		str	r4, [sp, #12]
+ 3128 000c 0494     		str	r4, [sp, #16]
+ 3129 000e 0594     		str	r4, [sp, #20]
+1034:Src/main.c    **** 
+ 3130              		.loc 2 1034 3 is_stmt 1 view .LVU1080
+ 3131              	.LVL234:
+ARM GAS  /tmp/ccdsDELB.s 			page 194
+
+
+ 3132              	.LBB396:
+ 3133              	.LBI396:
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 3134              		.loc 3 1071 22 view .LVU1081
+ 3135              	.LBB397:
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1ENR, Periphs);
+ 3136              		.loc 3 1073 3 view .LVU1082
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 3137              		.loc 3 1074 3 view .LVU1083
+ 3138 0010 1D4B     		ldr	r3, .L130
+ 3139 0012 1A6C     		ldr	r2, [r3, #64]
+ 3140 0014 42F00102 		orr	r2, r2, #1
+ 3141 0018 1A64     		str	r2, [r3, #64]
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3142              		.loc 3 1076 3 view .LVU1084
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3143              		.loc 3 1076 12 is_stmt 0 view .LVU1085
+ 3144 001a 1B6C     		ldr	r3, [r3, #64]
+ 3145 001c 03F00103 		and	r3, r3, #1
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3146              		.loc 3 1076 10 view .LVU1086
+ 3147 0020 0093     		str	r3, [sp]
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 3148              		.loc 3 1077 3 is_stmt 1 view .LVU1087
+ 3149 0022 009B     		ldr	r3, [sp]
+ 3150              	.LVL235:
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 3151              		.loc 3 1077 3 is_stmt 0 view .LVU1088
+ 3152              	.LBE397:
+ 3153              	.LBE396:
+1037:Src/main.c    ****   NVIC_EnableIRQ(TIM2_IRQn);
+ 3154              		.loc 2 1037 3 is_stmt 1 view .LVU1089
+ 3155              	.LBB398:
+ 3156              	.LBI398:
+1884:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3157              		.loc 1 1884 26 view .LVU1090
+ 3158              	.LBB399:
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 3159              		.loc 1 1886 3 view .LVU1091
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 3160              		.loc 1 1886 26 is_stmt 0 view .LVU1092
+ 3161 0024 194B     		ldr	r3, .L130+4
+ 3162 0026 D868     		ldr	r0, [r3, #12]
+ 3163              	.LBE399:
+ 3164              	.LBE398:
+1037:Src/main.c    ****   NVIC_EnableIRQ(TIM2_IRQn);
+ 3165              		.loc 2 1037 3 view .LVU1093
+ 3166 0028 2246     		mov	r2, r4
+ 3167 002a 2146     		mov	r1, r4
+ 3168 002c C0F30220 		ubfx	r0, r0, #8, #3
+ 3169 0030 FFF7FEFF 		bl	NVIC_EncodePriority
+ 3170              	.LVL236:
+ 3171              	.LBB400:
+ 3172              	.LBI400:
+2024:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3173              		.loc 1 2024 22 is_stmt 1 view .LVU1094
+ 3174              	.LBB401:
+ARM GAS  /tmp/ccdsDELB.s 			page 195
+
+
+2026:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 3175              		.loc 1 2026 3 view .LVU1095
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3176              		.loc 1 2028 5 view .LVU1096
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3177              		.loc 1 2028 49 is_stmt 0 view .LVU1097
+ 3178 0034 0001     		lsls	r0, r0, #4
+ 3179              	.LVL237:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3180              		.loc 1 2028 49 view .LVU1098
+ 3181 0036 C0B2     		uxtb	r0, r0
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3182              		.loc 1 2028 47 view .LVU1099
+ 3183 0038 154B     		ldr	r3, .L130+8
+ 3184 003a 83F81C03 		strb	r0, [r3, #796]
+ 3185              	.LVL238:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3186              		.loc 1 2028 47 view .LVU1100
+ 3187              	.LBE401:
+ 3188              	.LBE400:
+1038:Src/main.c    **** 
+ 3189              		.loc 2 1038 3 is_stmt 1 view .LVU1101
+ 3190              	.LBB402:
+ 3191              	.LBI402:
+1896:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3192              		.loc 1 1896 22 view .LVU1102
+ 3193              	.LBB403:
+1898:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 3194              		.loc 1 1898 3 view .LVU1103
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3195              		.loc 1 1900 5 view .LVU1104
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3196              		.loc 1 1900 43 is_stmt 0 view .LVU1105
+ 3197 003e 4FF08052 		mov	r2, #268435456
+ 3198 0042 1A60     		str	r2, [r3]
+ 3199              	.LVL239:
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3200              		.loc 1 1900 43 view .LVU1106
+ 3201              	.LBE403:
+ 3202              	.LBE402:
+1043:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+ 3203              		.loc 2 1043 3 is_stmt 1 view .LVU1107
+1043:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+ 3204              		.loc 2 1043 28 is_stmt 0 view .LVU1108
+ 3205 0044 4FF47A73 		mov	r3, #1000
+ 3206 0048 ADF80430 		strh	r3, [sp, #4]	@ movhi
+1044:Src/main.c    ****   TIM_InitStruct.Autoreload = 840000;
+ 3207              		.loc 2 1044 3 is_stmt 1 view .LVU1109
+1044:Src/main.c    ****   TIM_InitStruct.Autoreload = 840000;
+ 3208              		.loc 2 1044 30 is_stmt 0 view .LVU1110
+ 3209 004c 0294     		str	r4, [sp, #8]
+1045:Src/main.c    ****   TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ 3210              		.loc 2 1045 3 is_stmt 1 view .LVU1111
+1045:Src/main.c    ****   TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ 3211              		.loc 2 1045 29 is_stmt 0 view .LVU1112
+ 3212 004e 114B     		ldr	r3, .L130+12
+ 3213 0050 0393     		str	r3, [sp, #12]
+ARM GAS  /tmp/ccdsDELB.s 			page 196
+
+
+1046:Src/main.c    ****   LL_TIM_Init(TIM2, &TIM_InitStruct);
+ 3214              		.loc 2 1046 3 is_stmt 1 view .LVU1113
+1046:Src/main.c    ****   LL_TIM_Init(TIM2, &TIM_InitStruct);
+ 3215              		.loc 2 1046 32 is_stmt 0 view .LVU1114
+ 3216 0052 0494     		str	r4, [sp, #16]
+1047:Src/main.c    ****   LL_TIM_DisableARRPreload(TIM2);
+ 3217              		.loc 2 1047 3 is_stmt 1 view .LVU1115
+ 3218 0054 01A9     		add	r1, sp, #4
+ 3219 0056 4FF08040 		mov	r0, #1073741824
+ 3220 005a FFF7FEFF 		bl	LL_TIM_Init
+ 3221              	.LVL240:
+1048:Src/main.c    ****   LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
+ 3222              		.loc 2 1048 3 view .LVU1116
+ 3223              	.LBB404:
+ 3224              	.LBI404:
+ 3225              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @file    stm32f7xx_ll_tim.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief   Header file of TIM LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifndef __STM32F7xx_LL_TIM_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __STM32F7xx_LL_TIM_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defi
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL TIM
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/
+ARM GAS  /tmp/ccdsDELB.s 			page 197
+
+
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] =
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 0: TIMx_CH1  */
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 1: TIMx_CH1N */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 2: TIMx_CH2  */
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 3: TIMx_CH2N */
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x04U,   /* 4: TIMx_CH3  */
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x04U,   /* 5: TIMx_CH3N */
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x04U,   /* 6: TIMx_CH4  */
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x3CU,   /* 7: TIMx_CH5  */
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x3CU    /* 8: TIMx_CH6  */
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] =
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: OC1M, OC1FE, OC1PE */
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 1: - NA */
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 2: OC2M, OC2FE, OC2PE */
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 3: - NA */
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 4: OC3M, OC3FE, OC3PE */
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 5: - NA */
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 6: OC4M, OC4FE, OC4PE */
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 7: OC5M, OC5FE, OC5PE */
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U             /* 8: OC6M, OC6FE, OC6PE */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] =
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: CC1S, IC1PSC, IC1F */
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 1: - NA */
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 2: CC2S, IC2PSC, IC2F */
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 3: - NA */
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 4: CC3S, IC3PSC, IC3F */
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 5: - NA */
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 6: CC4S, IC4PSC, IC4F */
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 7: - NA */
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U             /* 8: - NA */
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] =
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: CC1P */
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   2U,            /* 1: CC1NP */
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   4U,            /* 2: CC2P */
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   6U,            /* 3: CC2NP */
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 4: CC3P */
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   10U,           /* 5: CC3NP */
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   12U,           /* 6: CC4P */
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   16U,           /* 7: CC5P */
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   20U            /* 8: CC6P */
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OISx[] =
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 198
+
+
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: OIS1 */
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   1U,            /* 1: OIS1N */
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   2U,            /* 2: OIS2 */
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   3U,            /* 3: OIS2N */
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   4U,            /* 4: OIS3 */
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   5U,            /* 5: OIS3N */
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   6U,            /* 6: OIS4 */
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 7: OIS5 */
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   10U            /* 8: OIS6 */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if   defined(TIM_BREAK_INPUT_SUPPORT)
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Defines used for the bit position in the register and perform offsets */
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_POSITION_BRK_SOURCE           (POSITION_VAL(Source) & 0x1FUL)
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Generic bit definitions for TIMx_AF1 register */
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_AF1_BKINP        TIM1_AF1_BKINP       /*!< BRK BKIN input polarity */
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Remap mask definitions */
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_SHIFT  16U
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_MASK   0x0000FFFFU
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM2_OR_RMP_MASK   (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM5_OR_RMP_MASK   (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM11_OR_RMP_MASK  (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_1 ((uint8_t)0x7F)
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_2 ((uint8_t)0x3F)
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_3 ((uint8_t)0x1F)
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_4 ((uint8_t)0x1F)
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_1 ((uint8_t)0x00)
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_2 ((uint8_t)0x80)
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_3 ((uint8_t)0xC0)
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_4 ((uint8_t)0xE0)
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief  Convert channel id into channel index.
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+ARM GAS  /tmp/ccdsDELB.s 			page 199
+
+
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval none
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief  Calculate the deadtime sampling period(in ps).
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz).
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CKD__ This parameter can be one of the following values:
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval none
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Time Base configuration structure definition.
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter can be a number between Min_Data=0x0000 and Max_D
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetPrescaler().*/
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t CounterMode;       /*!< Specifies the counter mode.
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+ARM GAS  /tmp/ccdsDELB.s 			page 200
+
+
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetCounterMode().*/
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Auto-Reload Register at the next update event.
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter must be a number between Min_Data=0x0000 and Max_
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Some timer instances may support 32 bits counters. In that case 
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    be a number between 0x0000 and 0xFFFFFFFF.
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetAutoReload().*/
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ClockDivision;     /*!< Specifies the clock division.
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetClockDivision().*/
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downc
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    reaches zero, an update event is generated and counting restarts
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    from the RCR value (N).
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This means in PWM mode that (N+1) corresponds to:
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       - the number of PWM periods in edge-aligned mode
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       - the number of half PWM period in center-aligned mode
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    GP timers: this parameter must be a number between Min_Data = 0x
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Max_Data = 0xFF.
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Advanced timers: this parameter must be a number between Min_Dat
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Max_Data = 0xFFFF.
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetRepetitionCounter().*/
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_InitTypeDef;
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Output Compare configuration structure definition.
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCMode;        /*!< Specifies the output mode.
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetMode().*/
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary functions
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary functions
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 201
+
+
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Re
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a number between Min_Data=0x0000 and Max_Data=
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                LL_TIM_OC_SetCompareCHx (x=1..6).*/
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCPolarity;    /*!< Specifies the output polarity.
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetPolarity().*/
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetPolarity().*/
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetIdleState().*/
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetIdleState().*/
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef;
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Input Capture configuration structure definition.
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetPolarity().*/
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICActiveInput; /*!< Specifies the input.
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetActiveInput().*/
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetPrescaler().*/
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 202
+
+
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICFilter;      /*!< Specifies the input capture filter.
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetFilter().*/
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef;
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Encoder interface configuration structure definition.
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_SetEncoderMode().*/
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPolarity().*/
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetActiveInput().*/
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPrescaler().*/
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetFilter().*/
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPolarity().*/
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetActiveInput().*/
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ARM GAS  /tmp/ccdsDELB.s 			page 203
+
+
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPrescaler().*/
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetFilter().*/
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef;
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Hall sensor interface configuration structure definition.
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_IC_SetPolarity().*/
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     Prescaler must be set to get a maximum counter period longer th
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     time interval between 2 consecutive changes on the Hall inputs.
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_IC_SetPrescaler().*/
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a value of
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref TIM_LL_EC_IC_FILTER.
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_IC_SetFilter().*/
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compa
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     A positive pulse (TRGO event) is generated with a programmable 
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     a change occurs on the Hall inputs.
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a number between Min_Data = 0x0000 and Ma
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_OC_SetCompareCH2().*/
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_HALLSENSOR_InitTypeDef;
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  BDTR (Break and Dead Time) structure definition
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ARM GAS  /tmp/ccdsDELB.s 			page 204
+
+
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_SetOffStates()
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field cannot be modified as long as LOCK level
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                        programmed. */
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_SetOffStates()
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field cannot be modified as long as LOCK level
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note The LOCK bits can be written only once after the reset.
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       register has been written, their content is frozen until the 
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       switching-on of the outputs.
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a number between Min_Data = 0x00 and Ma
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_OC_SetDeadTime()
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                        programmed. */
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARIT
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK()
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK()
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 205
+
+
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARI
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK2()
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK2()
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTP
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAut
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_BDTR_InitTypeDef;
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrup
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrup
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrup
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrup
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrup
+ARM GAS  /tmp/ccdsDELB.s 			page 206
+
+
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrup
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt fla
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapt
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapt
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapt
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapt
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt fla
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by 
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by softw
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrup
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrup
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrup
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrup
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable *
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ARM GAS  /tmp/ccdsDELB.s 			page 207
+
+
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/unde
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at 
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at 
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!< Counter used as upcounter 
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounte
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and 
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!< The counter counts up and 
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and 
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down 
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bi
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bi
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 208
+
+
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when 
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CHANNEL Channel
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output ch
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output ch
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output ch
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** Legacy definitions for compatibility purpose
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @cond 0
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @endcond
+ARM GAS  /tmp/ccdsDELB.s 			page 209
+
+
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FROZEN                   0x00000000U                                         
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                    
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                    
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)               
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                    
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)               
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)               
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                    
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)               
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)               
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                 
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!__REG__, (__VAL
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Read a value in TIM register.
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __INSTANCE__ TIM Instance
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __REG__ Register to be read
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Register value
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        to TIMx_CNT register bit 31)
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CNT__ Counter value
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval UIF status bit
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested de
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CKD__ This parameter can be one of the following values:
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __DT__ deadtime duration (in ns)
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval DTG[0:7]
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__C
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                  (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) 
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__C
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                  (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) 
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                  (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) 
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     0U)
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock freq
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CNTCLK__ counter clock frequency (in Hz)
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+ARM GAS  /tmp/ccdsDELB.s 			page 218
+
+
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal fr
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PSC__ prescaler
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __FREQ__ output signal frequency (in Hz)
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the compare value required to achieve the required timer outpu
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         active/inactive delay.
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PSC__ prescaler
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __DELAY__ timer output compare active/inactive delay (in us)
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (when the timer operates in one pulse mode).
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PSC__ prescaler
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __DELAY__ timer output compare active/inactive delay (in us)
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PULSE__ pulse duration (in us)
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****               + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __ICPSC__ This parameter can be one of the following values:
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV2
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV4
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV8
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 219
+
+
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable timer counter.
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable timer counter.
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the timer counter is enabled.
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable update event generation.
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable update event generation.
+ARM GAS  /tmp/ccdsDELB.s 			page 220
+
+
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether update event generation is enabled.
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Inverted state of bit (0 or 1).
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set update event source
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       generate an update interrupt or DMA request if enabled:
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        - Counter overflow/underflow
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        - Setting the UG bit
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        - Update generation through the slave mode controller
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       overflow/underflow generates an update interrupt or DMA request if enabled.
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  UpdateSource This parameter can be one of the following values:
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual event update source
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set one pulse mode (one shot v.s. repetitive).
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+ARM GAS  /tmp/ccdsDELB.s 			page 221
+
+
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  OnePulseMode This parameter can be one of the following values:
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual one pulse mode.
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the timer counter counting mode.
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       check whether or not the counter mode selection feature is supported
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       by a timer instance.
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       requires a timer reset to avoid unexpected direction
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       due to DIR bit readonly in center aligned mode.
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR1          CMS           LL_TIM_SetCounterMode
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CounterMode This parameter can be one of the following values:
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_UP
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual counter mode.
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       check whether or not the counter mode selection feature is supported
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       by a timer instance.
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR1          CMS           LL_TIM_GetCounterMode
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+ARM GAS  /tmp/ccdsDELB.s 			page 222
+
+
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_UP
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t counter_mode;
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   if (counter_mode == 0U)
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   {
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   }
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return counter_mode;
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable auto-reload (ARR) preload.
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable auto-reload (ARR) preload.
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+ 3226              		.loc 5 1504 22 view .LVU1117
+ 3227              	.LBB405:
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+ 3228              		.loc 5 1506 3 view .LVU1118
+ 3229 005e 4FF08043 		mov	r3, #1073741824
+ 3230 0062 1A68     		ldr	r2, [r3]
+ 3231 0064 22F08002 		bic	r2, r2, #128
+ 3232 0068 1A60     		str	r2, [r3]
+ 3233              	.LVL241:
+ 3234              		.loc 5 1506 3 is_stmt 0 view .LVU1119
+ 3235              	.LBE405:
+ 3236              	.LBE404:
+1049:Src/main.c    ****   LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET);
+ 3237              		.loc 2 1049 3 is_stmt 1 view .LVU1120
+ 3238              	.LBB406:
+ 3239              	.LBI406:
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 223
+
+
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (when supported) and the digital filters.
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not the clock division feature is supported by the timer
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       instance.
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ClockDivision This parameter can be one of the following values:
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by t
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         generators (when supported) and the digital filters.
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not the clock division feature is supported by the timer
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       instance.
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the counter value.
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CNT          CNT           LL_TIM_SetCounter
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 224
+
+
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CNT, Counter);
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the counter value.
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CNT          CNT           LL_TIM_GetCounter
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CNT));
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current direction of the counter
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          DIR           LL_TIM_GetDirection
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the prescaler value.
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The prescaler can be changed on the fly as this control register is buffered. The new
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       prescaler ratio is taken into account at the next update event.
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Prescaler between Min_Data=0 and Max_Data=65535
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->PSC, Prescaler);
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the prescaler value.
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->PSC));
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 225
+
+
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the auto-reload value.
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The counter is blocked while the auto-reload value is null.
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  AutoReload between Min_Data=0 and Max_Data=65535
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->ARR, AutoReload);
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the auto-reload value.
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Auto-reload value
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->ARR));
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the repetition counter value.
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note For advanced timer instances RepetitionCounter can be up to 65535.
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a repetition counter.
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->RCR, RepetitionCounter);
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the repetition counter value.
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a repetition counter.
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Repetition counter value
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->RCR));
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 226
+
+
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter regis
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This allows both the counter value and a potential roll-over condition signalled by the U
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       in an atomic way.
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable update interrupt flag (UIF) remapping.
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether update interrupt flag (UIF) copy is set.
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Counter Counter value
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       they are updated only when a commutation event (COM) occurs.
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Only on channels that have a complementary output.
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance is able to generate a commutation event.
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 227
+
+
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance is able to generate a commutation event.
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is en
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCPC          LL_TIM_CC_IsEnabledPreload
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance is able to generate a commutation event.
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CCUpdateSource This parameter can be one of the following values:
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the trigger of the capture/compare DMA request.
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DMAReqTrigger This parameter can be one of the following values:
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual trigger of the capture/compare DMA request.
+ARM GAS  /tmp/ccdsDELB.s 			page 228
+
+
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the lock level to freeze the
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         configuration of several capture/compare parameters.
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       the lock mechanism is supported by a timer instance.
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  LockLevel This parameter can be one of the following values:
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_1
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_2
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_3
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable capture/compare channels.
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
+1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
+1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6E          LL_TIM_CC_EnableChannel
+1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channels This parameter can be a combination of the following values:
+1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CCER, Channels);
+ARM GAS  /tmp/ccdsDELB.s 			page 229
+
+
+1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable capture/compare channels.
+1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
+1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
+1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6E          LL_TIM_CC_DisableChannel
+1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channels This parameter can be a combination of the following values:
+1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CCER, Channels);
+1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether channel(s) is(are) enabled.
+1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
+1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
+1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
+1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channels This parameter can be a combination of the following values:
+1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
+1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 230
+
+
+1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure an output channel.
+1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
+1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
+1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
+1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
+1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
+1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
+1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS6          LL_TIM_OC_ConfigOutput
+1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Configuration This parameter must be a combination of all the following values:
+1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura
+1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Define the behavior of the output reference signal OCxREF from which
+1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         OCx and OCxN (when relevant) are derived.
+ARM GAS  /tmp/ccdsDELB.s 			page 231
+
+
+1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
+1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
+1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6M          LL_TIM_OC_SetMode
+1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Mode This parameter can be one of the following values:
+1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FROZEN
+1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ACTIVE
+1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_INACTIVE
+1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_TOGGLE
+1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM1
+1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM2
+1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT
+2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the output compare mode of an output channel.
+2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
+2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
+2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6M          LL_TIM_OC_GetMode
+2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FROZEN
+2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ACTIVE
+ARM GAS  /tmp/ccdsDELB.s 			page 232
+
+
+2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_INACTIVE
+2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_TOGGLE
+2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM1
+2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM2
+2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
+2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT
+2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the polarity of an output channel.
+2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
+2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
+2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6P          LL_TIM_OC_SetPolarity
+2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Polarity This parameter can be one of the following values:
+2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_LOW
+2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[i
+2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the polarity of an output channel.
+2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+ARM GAS  /tmp/ccdsDELB.s 			page 233
+
+
+2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
+2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
+2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6P          LL_TIM_OC_GetPolarity
+2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_LOW
+2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan
+2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the IDLE state of an output channel
+2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function is significant only for the timer instances
+2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       can be used to check whether or not a timer instance provides
+2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a break input.
+2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
+2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
+2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS6          LL_TIM_OC_SetIdleState
+2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  IdleState This parameter can be one of the following values:
+2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ARM GAS  /tmp/ccdsDELB.s 			page 234
+
+
+2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState
+2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iC
+2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the IDLE state of an output channel
+2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
+2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS6          LL_TIM_OC_GetIdleState
+2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
+2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChanne
+2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable fast mode for the output channel.
+2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
+2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
+2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
+2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+ARM GAS  /tmp/ccdsDELB.s 			page 235
+
+
+2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable fast mode for the output channel.
+2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
+2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
+2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
+2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether fast mode is enabled for the output channel.
+2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
+2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
+2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
+2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ARM GAS  /tmp/ccdsDELB.s 			page 236
+
+
+2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
+2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
+2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
+2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
+2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
+2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
+2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe
+ARM GAS  /tmp/ccdsDELB.s 			page 237
+
+
+2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
+2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
+2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
+2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable clearing the output channel on an external event.
+2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function can only be used in Output compare and PWM modes. It does not work in Force
+2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance can clear the OCxREF signal on an external event.
+2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
+2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
+2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
+2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable clearing the output channel on an external event.
+2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance can clear the OCxREF signal on an external event.
+2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+ARM GAS  /tmp/ccdsDELB.s 			page 238
+
+
+2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
+2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
+2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
+2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates clearing the output channel on an external event is enabled for the output ch
+2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function enables clearing the output channel on an external event.
+2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function can only be used in Output compare and PWM modes. It does not work in Force
+2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance can clear the OCxREF signal on an external event.
+2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
+2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
+2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
+2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal an
+2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         the Ocx and OCxN signals).
+2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       dead-time insertion feature is supported by a timer instance.
+ARM GAS  /tmp/ccdsDELB.s 			page 239
+
+
+2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DeadTime between Min_Data=0 and Max_Data=255
+2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 1 is supported by a timer instance.
+2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR1, CompareValue);
+2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 2 is supported by a timer instance.
+2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR2, CompareValue);
+2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel is supported by a timer instance.
+2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 240
+
+
+2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR3, CompareValue);
+2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 4 is supported by a timer instance.
+2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR4, CompareValue);
+2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 5 (TIMx_CCR5).
+2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 5 is supported by a timer instance.
+2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
+2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 6 (TIMx_CCR6).
+2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 6 is supported by a timer instance.
+2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
+2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR6, CompareValue);
+2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 1 is supported by a timer instance.
+ARM GAS  /tmp/ccdsDELB.s 			page 241
+
+
+2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
+2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR1));
+2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 2 is supported by a timer instance.
+2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
+2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR2));
+2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 3 is supported by a timer instance.
+2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
+2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR3));
+2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 4 is supported by a timer instance.
+2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
+2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR4));
+2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 242
+
+
+2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
+2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 5 is supported by a timer instance.
+2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
+2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
+2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
+2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 6 is supported by a timer instance.
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
+2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
+2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR6));
+2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Select on which reference signal the OC5REF is combined to.
+2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports the combined 3-phase PWM mode.
+2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
+2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
+2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
+2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  GroupCH5 This parameter can be a combination of the following values:
+2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_NONE
+2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
+2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
+2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
+2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
+2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure input channel.
+2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+ARM GAS  /tmp/ccdsDELB.s 			page 243
+
+
+2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC1F          LL_TIM_IC_Config\n
+2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_IC_Config\n
+2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2F          LL_TIM_IC_Config\n
+2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_IC_Config\n
+2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3F          LL_TIM_IC_Config\n
+2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_IC_Config\n
+2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4F          LL_TIM_IC_Config\n
+2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1P          LL_TIM_IC_Config\n
+2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_IC_Config\n
+2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_IC_Config\n
+2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_IC_Config\n
+2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_IC_Config\n
+2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_IC_Config\n
+2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_IC_Config\n
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4NP         LL_TIM_IC_Config
+2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Configuration This parameter must be a combination of all the following values:
+2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_
+2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_I
+2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne
+2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))       
+2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              << SHIFT_TAB_ICxx[iChannel]);
+2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the active input.
+2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICActiveInput This parameter can be one of the following values:
+2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ARM GAS  /tmp/ccdsDELB.s 			page 244
+
+
+2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv
+2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT
+2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current active input.
+2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
+2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann
+2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the prescaler of input channel.
+2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICPrescaler This parameter can be one of the following values:
+2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1
+2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV2
+2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV4
+2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV8
+2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal
+2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+ARM GAS  /tmp/ccdsDELB.s 			page 245
+
+
+2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT
+2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current prescaler value acting on an  input channel.
+2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1
+2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV2
+2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV4
+2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV8
+2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
+2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha
+2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the input filter duration.
+2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICFilter This parameter can be one of the following values:
+2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ARM GAS  /tmp/ccdsDELB.s 			page 246
+
+
+2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_
+2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the input filter duration.
+2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
+2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann
+2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the input channel polarity.
+2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+ARM GAS  /tmp/ccdsDELB.s 			page 247
+
+
+2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICPolarity This parameter can be one of the following values:
+2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_RISING
+2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity
+2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current input channel polarity.
+2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_RISING
+2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****           SHIFT_TAB_CCxP[iChannel]);
+2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides an XOR input.
+2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+ARM GAS  /tmp/ccdsDELB.s 			page 248
+
+
+2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides an XOR input.
+2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * a timer instance provides an XOR input.
+2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
+2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 1.
+2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 1 is supported by a timer instance.
+2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
+2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR1));
+2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 2.
+2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 2 is supported by a timer instance.
+2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
+2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 249
+
+
+2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR2));
+2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 3.
+2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 3 is supported by a timer instance.
+3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
+3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR3));
+3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 4.
+3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 4 is supported by a timer instance.
+3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
+3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR4));
+3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable external clock mode 2.
+3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET
+3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 250
+
+
+3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable external clock mode 2.
+3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether external clock mode 2 is enabled.
+3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
+3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the clock source of the counter clock.
+3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note when selected clock source is external clock mode 1, the timer input
+3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       function. This timer input must be configured by calling
+3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       the @ref LL_TIM_IC_Config() function.
+3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode1.
+3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         SMCR         ECE           LL_TIM_SetClockSource
+3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ClockSource This parameter can be one of the following values:
+3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+ 3240              		.loc 5 3092 22 view .LVU1121
+ 3241              	.LBB407:
+3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+ 3242              		.loc 5 3094 3 view .LVU1122
+ 3243 006a 9968     		ldr	r1, [r3, #8]
+ 3244 006c 0A4A     		ldr	r2, .L130+16
+ 3245 006e 0A40     		ands	r2, r2, r1
+ 3246 0070 9A60     		str	r2, [r3, #8]
+ 3247              	.LVL242:
+ 3248              		.loc 5 3094 3 is_stmt 0 view .LVU1123
+ 3249              	.LBE407:
+ARM GAS  /tmp/ccdsDELB.s 			page 251
+
+
+ 3250              	.LBE406:
+1050:Src/main.c    ****   LL_TIM_DisableMasterSlaveMode(TIM2);
+ 3251              		.loc 2 1050 3 is_stmt 1 view .LVU1124
+ 3252              	.LBB408:
+ 3253              	.LBI408:
+3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the encoder interface mode.
+3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports the encoder mode.
+3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  EncoderMode This parameter can be one of the following values:
+3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the trigger output (TRGO) used for timer synchronization .
+3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance can operate as a master timer.
+3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TimerSynchronization This parameter can be one of the following values:
+3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_RESET
+3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_ENABLE
+3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_UPDATE
+3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_CC1IF
+3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC1REF
+3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC2REF
+3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC3REF
+3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC4REF
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+ 3254              		.loc 5 3138 22 view .LVU1125
+ 3255              	.LBB409:
+3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+ 3256              		.loc 5 3140 3 view .LVU1126
+ 3257 0072 5A68     		ldr	r2, [r3, #4]
+ 3258 0074 22F07002 		bic	r2, r2, #112
+ 3259 0078 5A60     		str	r2, [r3, #4]
+ARM GAS  /tmp/ccdsDELB.s 			page 252
+
+
+ 3260              	.LVL243:
+ 3261              		.loc 5 3140 3 is_stmt 0 view .LVU1127
+ 3262              	.LBE409:
+ 3263              	.LBE408:
+1051:Src/main.c    ****   /* USER CODE BEGIN TIM2_Init 2 */
+ 3264              		.loc 2 1051 3 is_stmt 1 view .LVU1128
+ 3265              	.LBB410:
+ 3266              	.LBI410:
+3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
+3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance can be used for ADC synchronization.
+3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
+3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer Instance
+3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ADCSynchronization This parameter can be one of the following values:
+3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_RESET
+3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_ENABLE
+3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_UPDATE
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_CC1F
+3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC1
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC2
+3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC3
+3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4
+3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC5
+3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC6
+3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the synchronization mode of a slave timer.
+3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  SlaveMode This parameter can be one of the following values:
+3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_RESET
+3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_GATED
+3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+ARM GAS  /tmp/ccdsDELB.s 			page 253
+
+
+3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the selects the trigger input to be used to synchronize the counter.
+3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TriggerInput This parameter can be one of the following values:
+3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR0
+3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR1
+3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR2
+3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR3
+3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_TI1F_ED
+3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_TI1FP1
+3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_TI2FP2
+3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ETRF
+3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the Master/Slave mode.
+3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the Master/Slave mode.
+3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+ 3267              		.loc 5 3235 22 view .LVU1129
+ 3268              	.LBB411:
+3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+ 3269              		.loc 5 3237 3 view .LVU1130
+ 3270 007a 9A68     		ldr	r2, [r3, #8]
+ 3271 007c 22F08002 		bic	r2, r2, #128
+ 3272 0080 9A60     		str	r2, [r3, #8]
+ 3273              	.LVL244:
+ 3274              		.loc 5 3237 3 is_stmt 0 view .LVU1131
+ 3275              	.LBE411:
+ARM GAS  /tmp/ccdsDELB.s 			page 254
+
+
+ 3276              	.LBE410:
+1056:Src/main.c    **** 
+ 3277              		.loc 2 1056 1 view .LVU1132
+ 3278 0082 06B0     		add	sp, sp, #24
+ 3279              	.LCFI27:
+ 3280              		.cfi_def_cfa_offset 8
+ 3281              		@ sp needed
+ 3282 0084 10BD     		pop	{r4, pc}
+ 3283              	.L131:
+ 3284 0086 00BF     		.align	2
+ 3285              	.L130:
+ 3286 0088 00380240 		.word	1073887232
+ 3287 008c 00ED00E0 		.word	-536810240
+ 3288 0090 00E100E0 		.word	-536813312
+ 3289 0094 40D10C00 		.word	840000
+ 3290 0098 F8BFFEFF 		.word	-81928
+ 3291              		.cfi_endproc
+ 3292              	.LFE1195:
+ 3294              		.section	.text.MX_TIM5_Init,"ax",%progbits
+ 3295              		.align	1
+ 3296              		.syntax unified
+ 3297              		.thumb
+ 3298              		.thumb_func
+ 3299              		.fpu fpv5-d16
+ 3301              	MX_TIM5_Init:
+ 3302              	.LFB1196:
+1064:Src/main.c    **** 
+ 3303              		.loc 2 1064 1 is_stmt 1 view -0
+ 3304              		.cfi_startproc
+ 3305              		@ args = 0, pretend = 0, frame = 24
+ 3306              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3307 0000 10B5     		push	{r4, lr}
+ 3308              	.LCFI28:
+ 3309              		.cfi_def_cfa_offset 8
+ 3310              		.cfi_offset 4, -8
+ 3311              		.cfi_offset 14, -4
+ 3312 0002 86B0     		sub	sp, sp, #24
+ 3313              	.LCFI29:
+ 3314              		.cfi_def_cfa_offset 32
+1070:Src/main.c    **** 
+ 3315              		.loc 2 1070 3 view .LVU1134
+1070:Src/main.c    **** 
+ 3316              		.loc 2 1070 22 is_stmt 0 view .LVU1135
+ 3317 0004 0024     		movs	r4, #0
+ 3318 0006 0194     		str	r4, [sp, #4]
+ 3319 0008 0294     		str	r4, [sp, #8]
+ 3320 000a 0394     		str	r4, [sp, #12]
+ 3321 000c 0494     		str	r4, [sp, #16]
+ 3322 000e 0594     		str	r4, [sp, #20]
+1073:Src/main.c    **** 
+ 3323              		.loc 2 1073 3 is_stmt 1 view .LVU1136
+ 3324              	.LVL245:
+ 3325              	.LBB412:
+ 3326              	.LBI412:
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 3327              		.loc 3 1071 22 view .LVU1137
+ 3328              	.LBB413:
+ARM GAS  /tmp/ccdsDELB.s 			page 255
+
+
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1ENR, Periphs);
+ 3329              		.loc 3 1073 3 view .LVU1138
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 3330              		.loc 3 1074 3 view .LVU1139
+ 3331 0010 1C4B     		ldr	r3, .L134
+ 3332 0012 1A6C     		ldr	r2, [r3, #64]
+ 3333 0014 42F00802 		orr	r2, r2, #8
+ 3334 0018 1A64     		str	r2, [r3, #64]
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3335              		.loc 3 1076 3 view .LVU1140
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3336              		.loc 3 1076 12 is_stmt 0 view .LVU1141
+ 3337 001a 1B6C     		ldr	r3, [r3, #64]
+ 3338 001c 03F00803 		and	r3, r3, #8
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3339              		.loc 3 1076 10 view .LVU1142
+ 3340 0020 0093     		str	r3, [sp]
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 3341              		.loc 3 1077 3 is_stmt 1 view .LVU1143
+ 3342 0022 009B     		ldr	r3, [sp]
+ 3343              	.LVL246:
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 3344              		.loc 3 1077 3 is_stmt 0 view .LVU1144
+ 3345              	.LBE413:
+ 3346              	.LBE412:
+1076:Src/main.c    ****   NVIC_EnableIRQ(TIM5_IRQn);
+ 3347              		.loc 2 1076 3 is_stmt 1 view .LVU1145
+ 3348              	.LBB414:
+ 3349              	.LBI414:
+1884:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3350              		.loc 1 1884 26 view .LVU1146
+ 3351              	.LBB415:
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 3352              		.loc 1 1886 3 view .LVU1147
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 3353              		.loc 1 1886 26 is_stmt 0 view .LVU1148
+ 3354 0024 184B     		ldr	r3, .L134+4
+ 3355 0026 D868     		ldr	r0, [r3, #12]
+ 3356              	.LBE415:
+ 3357              	.LBE414:
+1076:Src/main.c    ****   NVIC_EnableIRQ(TIM5_IRQn);
+ 3358              		.loc 2 1076 3 view .LVU1149
+ 3359 0028 2246     		mov	r2, r4
+ 3360 002a 2146     		mov	r1, r4
+ 3361 002c C0F30220 		ubfx	r0, r0, #8, #3
+ 3362 0030 FFF7FEFF 		bl	NVIC_EncodePriority
+ 3363              	.LVL247:
+ 3364              	.LBB416:
+ 3365              	.LBI416:
+2024:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3366              		.loc 1 2024 22 is_stmt 1 view .LVU1150
+ 3367              	.LBB417:
+2026:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 3368              		.loc 1 2026 3 view .LVU1151
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3369              		.loc 1 2028 5 view .LVU1152
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ARM GAS  /tmp/ccdsDELB.s 			page 256
+
+
+ 3370              		.loc 1 2028 49 is_stmt 0 view .LVU1153
+ 3371 0034 0001     		lsls	r0, r0, #4
+ 3372              	.LVL248:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3373              		.loc 1 2028 49 view .LVU1154
+ 3374 0036 C0B2     		uxtb	r0, r0
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3375              		.loc 1 2028 47 view .LVU1155
+ 3376 0038 144B     		ldr	r3, .L134+8
+ 3377 003a 83F83203 		strb	r0, [r3, #818]
+ 3378              	.LVL249:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3379              		.loc 1 2028 47 view .LVU1156
+ 3380              	.LBE417:
+ 3381              	.LBE416:
+1077:Src/main.c    **** 
+ 3382              		.loc 2 1077 3 is_stmt 1 view .LVU1157
+ 3383              	.LBB418:
+ 3384              	.LBI418:
+1896:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3385              		.loc 1 1896 22 view .LVU1158
+ 3386              	.LBB419:
+1898:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 3387              		.loc 1 1898 3 view .LVU1159
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3388              		.loc 1 1900 5 view .LVU1160
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3389              		.loc 1 1900 43 is_stmt 0 view .LVU1161
+ 3390 003e 4FF48022 		mov	r2, #262144
+ 3391 0042 5A60     		str	r2, [r3, #4]
+ 3392              	.LVL250:
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3393              		.loc 1 1900 43 view .LVU1162
+ 3394              	.LBE419:
+ 3395              	.LBE418:
+1082:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+ 3396              		.loc 2 1082 3 is_stmt 1 view .LVU1163
+1082:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+ 3397              		.loc 2 1082 28 is_stmt 0 view .LVU1164
+ 3398 0044 42F21073 		movw	r3, #10000
+ 3399 0048 ADF80430 		strh	r3, [sp, #4]	@ movhi
+1083:Src/main.c    ****   TIM_InitStruct.Autoreload = 560;
+ 3400              		.loc 2 1083 3 is_stmt 1 view .LVU1165
+1083:Src/main.c    ****   TIM_InitStruct.Autoreload = 560;
+ 3401              		.loc 2 1083 30 is_stmt 0 view .LVU1166
+ 3402 004c 0294     		str	r4, [sp, #8]
+1084:Src/main.c    ****   TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ 3403              		.loc 2 1084 3 is_stmt 1 view .LVU1167
+1084:Src/main.c    ****   TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ 3404              		.loc 2 1084 29 is_stmt 0 view .LVU1168
+ 3405 004e 4FF40C73 		mov	r3, #560
+ 3406 0052 0393     		str	r3, [sp, #12]
+1085:Src/main.c    ****   LL_TIM_Init(TIM5, &TIM_InitStruct);
+ 3407              		.loc 2 1085 3 is_stmt 1 view .LVU1169
+1085:Src/main.c    ****   LL_TIM_Init(TIM5, &TIM_InitStruct);
+ 3408              		.loc 2 1085 32 is_stmt 0 view .LVU1170
+ 3409 0054 0494     		str	r4, [sp, #16]
+ARM GAS  /tmp/ccdsDELB.s 			page 257
+
+
+1086:Src/main.c    ****   LL_TIM_DisableARRPreload(TIM5);
+ 3410              		.loc 2 1086 3 is_stmt 1 view .LVU1171
+ 3411 0056 0E4C     		ldr	r4, .L134+12
+ 3412 0058 01A9     		add	r1, sp, #4
+ 3413 005a 2046     		mov	r0, r4
+ 3414 005c FFF7FEFF 		bl	LL_TIM_Init
+ 3415              	.LVL251:
+1087:Src/main.c    ****   LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL);
+ 3416              		.loc 2 1087 3 view .LVU1172
+ 3417              	.LBB420:
+ 3418              	.LBI420:
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 3419              		.loc 5 1504 22 view .LVU1173
+ 3420              	.LBB421:
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3421              		.loc 5 1506 3 view .LVU1174
+ 3422 0060 2368     		ldr	r3, [r4]
+ 3423 0062 23F08003 		bic	r3, r3, #128
+ 3424 0066 2360     		str	r3, [r4]
+ 3425              	.LVL252:
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3426              		.loc 5 1506 3 is_stmt 0 view .LVU1175
+ 3427              	.LBE421:
+ 3428              	.LBE420:
+1088:Src/main.c    ****   LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET);
+ 3429              		.loc 2 1088 3 is_stmt 1 view .LVU1176
+ 3430              	.LBB422:
+ 3431              	.LBI422:
+3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 3432              		.loc 5 3092 22 view .LVU1177
+ 3433              	.LBB423:
+3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3434              		.loc 5 3094 3 view .LVU1178
+ 3435 0068 A268     		ldr	r2, [r4, #8]
+ 3436 006a 0A4B     		ldr	r3, .L134+16
+ 3437 006c 1340     		ands	r3, r3, r2
+ 3438 006e A360     		str	r3, [r4, #8]
+ 3439              	.LVL253:
+3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3440              		.loc 5 3094 3 is_stmt 0 view .LVU1179
+ 3441              	.LBE423:
+ 3442              	.LBE422:
+1089:Src/main.c    ****   LL_TIM_DisableMasterSlaveMode(TIM5);
+ 3443              		.loc 2 1089 3 is_stmt 1 view .LVU1180
+ 3444              	.LBB424:
+ 3445              	.LBI424:
+3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 3446              		.loc 5 3138 22 view .LVU1181
+ 3447              	.LBB425:
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3448              		.loc 5 3140 3 view .LVU1182
+ 3449 0070 6368     		ldr	r3, [r4, #4]
+ 3450 0072 23F07003 		bic	r3, r3, #112
+ 3451 0076 6360     		str	r3, [r4, #4]
+ 3452              	.LVL254:
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3453              		.loc 5 3140 3 is_stmt 0 view .LVU1183
+ARM GAS  /tmp/ccdsDELB.s 			page 258
+
+
+ 3454              	.LBE425:
+ 3455              	.LBE424:
+1090:Src/main.c    ****   /* USER CODE BEGIN TIM5_Init 2 */
+ 3456              		.loc 2 1090 3 is_stmt 1 view .LVU1184
+ 3457              	.LBB426:
+ 3458              	.LBI426:
+3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 3459              		.loc 5 3235 22 view .LVU1185
+ 3460              	.LBB427:
+ 3461              		.loc 5 3237 3 view .LVU1186
+ 3462 0078 A368     		ldr	r3, [r4, #8]
+ 3463 007a 23F08003 		bic	r3, r3, #128
+ 3464 007e A360     		str	r3, [r4, #8]
+ 3465              	.LVL255:
+ 3466              		.loc 5 3237 3 is_stmt 0 view .LVU1187
+ 3467              	.LBE427:
+ 3468              	.LBE426:
+1095:Src/main.c    **** 
+ 3469              		.loc 2 1095 1 view .LVU1188
+ 3470 0080 06B0     		add	sp, sp, #24
+ 3471              	.LCFI30:
+ 3472              		.cfi_def_cfa_offset 8
+ 3473              		@ sp needed
+ 3474 0082 10BD     		pop	{r4, pc}
+ 3475              	.L135:
+ 3476              		.align	2
+ 3477              	.L134:
+ 3478 0084 00380240 		.word	1073887232
+ 3479 0088 00ED00E0 		.word	-536810240
+ 3480 008c 00E100E0 		.word	-536813312
+ 3481 0090 000C0040 		.word	1073744896
+ 3482 0094 F8BFFEFF 		.word	-81928
+ 3483              		.cfi_endproc
+ 3484              	.LFE1196:
+ 3486              		.section	.text.MX_TIM7_Init,"ax",%progbits
+ 3487              		.align	1
+ 3488              		.syntax unified
+ 3489              		.thumb
+ 3490              		.thumb_func
+ 3491              		.fpu fpv5-d16
+ 3493              	MX_TIM7_Init:
+ 3494              	.LFB1198:
+1140:Src/main.c    **** 
+ 3495              		.loc 2 1140 1 is_stmt 1 view -0
+ 3496              		.cfi_startproc
+ 3497              		@ args = 0, pretend = 0, frame = 24
+ 3498              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3499 0000 10B5     		push	{r4, lr}
+ 3500              	.LCFI31:
+ 3501              		.cfi_def_cfa_offset 8
+ 3502              		.cfi_offset 4, -8
+ 3503              		.cfi_offset 14, -4
+ 3504 0002 86B0     		sub	sp, sp, #24
+ 3505              	.LCFI32:
+ 3506              		.cfi_def_cfa_offset 32
+1146:Src/main.c    **** 
+ 3507              		.loc 2 1146 3 view .LVU1190
+ARM GAS  /tmp/ccdsDELB.s 			page 259
+
+
+1146:Src/main.c    **** 
+ 3508              		.loc 2 1146 22 is_stmt 0 view .LVU1191
+ 3509 0004 0024     		movs	r4, #0
+ 3510 0006 0194     		str	r4, [sp, #4]
+ 3511 0008 0294     		str	r4, [sp, #8]
+ 3512 000a 0394     		str	r4, [sp, #12]
+ 3513 000c 0494     		str	r4, [sp, #16]
+ 3514 000e 0594     		str	r4, [sp, #20]
+1149:Src/main.c    **** 
+ 3515              		.loc 2 1149 3 is_stmt 1 view .LVU1192
+ 3516              	.LVL256:
+ 3517              	.LBB428:
+ 3518              	.LBI428:
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 3519              		.loc 3 1071 22 view .LVU1193
+ 3520              	.LBB429:
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1ENR, Periphs);
+ 3521              		.loc 3 1073 3 view .LVU1194
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 3522              		.loc 3 1074 3 view .LVU1195
+ 3523 0010 1A4B     		ldr	r3, .L138
+ 3524 0012 1A6C     		ldr	r2, [r3, #64]
+ 3525 0014 42F02002 		orr	r2, r2, #32
+ 3526 0018 1A64     		str	r2, [r3, #64]
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3527              		.loc 3 1076 3 view .LVU1196
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3528              		.loc 3 1076 12 is_stmt 0 view .LVU1197
+ 3529 001a 1B6C     		ldr	r3, [r3, #64]
+ 3530 001c 03F02003 		and	r3, r3, #32
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3531              		.loc 3 1076 10 view .LVU1198
+ 3532 0020 0093     		str	r3, [sp]
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 3533              		.loc 3 1077 3 is_stmt 1 view .LVU1199
+ 3534 0022 009B     		ldr	r3, [sp]
+ 3535              	.LVL257:
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 3536              		.loc 3 1077 3 is_stmt 0 view .LVU1200
+ 3537              	.LBE429:
+ 3538              	.LBE428:
+1152:Src/main.c    ****   NVIC_EnableIRQ(TIM7_IRQn);
+ 3539              		.loc 2 1152 3 is_stmt 1 view .LVU1201
+ 3540              	.LBB430:
+ 3541              	.LBI430:
+1884:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3542              		.loc 1 1884 26 view .LVU1202
+ 3543              	.LBB431:
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 3544              		.loc 1 1886 3 view .LVU1203
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 3545              		.loc 1 1886 26 is_stmt 0 view .LVU1204
+ 3546 0024 164B     		ldr	r3, .L138+4
+ 3547 0026 D868     		ldr	r0, [r3, #12]
+ 3548              	.LBE431:
+ 3549              	.LBE430:
+1152:Src/main.c    ****   NVIC_EnableIRQ(TIM7_IRQn);
+ARM GAS  /tmp/ccdsDELB.s 			page 260
+
+
+ 3550              		.loc 2 1152 3 view .LVU1205
+ 3551 0028 2246     		mov	r2, r4
+ 3552 002a 2146     		mov	r1, r4
+ 3553 002c C0F30220 		ubfx	r0, r0, #8, #3
+ 3554 0030 FFF7FEFF 		bl	NVIC_EncodePriority
+ 3555              	.LVL258:
+ 3556              	.LBB432:
+ 3557              	.LBI432:
+2024:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3558              		.loc 1 2024 22 is_stmt 1 view .LVU1206
+ 3559              	.LBB433:
+2026:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 3560              		.loc 1 2026 3 view .LVU1207
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3561              		.loc 1 2028 5 view .LVU1208
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3562              		.loc 1 2028 49 is_stmt 0 view .LVU1209
+ 3563 0034 0001     		lsls	r0, r0, #4
+ 3564              	.LVL259:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3565              		.loc 1 2028 49 view .LVU1210
+ 3566 0036 C0B2     		uxtb	r0, r0
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3567              		.loc 1 2028 47 view .LVU1211
+ 3568 0038 124B     		ldr	r3, .L138+8
+ 3569 003a 83F83703 		strb	r0, [r3, #823]
+ 3570              	.LVL260:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3571              		.loc 1 2028 47 view .LVU1212
+ 3572              	.LBE433:
+ 3573              	.LBE432:
+1153:Src/main.c    **** 
+ 3574              		.loc 2 1153 3 is_stmt 1 view .LVU1213
+ 3575              	.LBB434:
+ 3576              	.LBI434:
+1896:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3577              		.loc 1 1896 22 view .LVU1214
+ 3578              	.LBB435:
+1898:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 3579              		.loc 1 1898 3 view .LVU1215
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3580              		.loc 1 1900 5 view .LVU1216
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3581              		.loc 1 1900 43 is_stmt 0 view .LVU1217
+ 3582 003e 4FF40002 		mov	r2, #8388608
+ 3583 0042 5A60     		str	r2, [r3, #4]
+ 3584              	.LVL261:
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3585              		.loc 1 1900 43 view .LVU1218
+ 3586              	.LBE435:
+ 3587              	.LBE434:
+1158:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+ 3588              		.loc 2 1158 3 is_stmt 1 view .LVU1219
+1158:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+ 3589              		.loc 2 1158 28 is_stmt 0 view .LVU1220
+ 3590 0044 40F29733 		movw	r3, #919
+ 3591 0048 ADF80430 		strh	r3, [sp, #4]	@ movhi
+ARM GAS  /tmp/ccdsDELB.s 			page 261
+
+
+1159:Src/main.c    ****   TIM_InitStruct.Autoreload = 99;
+ 3592              		.loc 2 1159 3 is_stmt 1 view .LVU1221
+1159:Src/main.c    ****   TIM_InitStruct.Autoreload = 99;
+ 3593              		.loc 2 1159 30 is_stmt 0 view .LVU1222
+ 3594 004c 0294     		str	r4, [sp, #8]
+1160:Src/main.c    ****   LL_TIM_Init(TIM7, &TIM_InitStruct);
+ 3595              		.loc 2 1160 3 is_stmt 1 view .LVU1223
+1160:Src/main.c    ****   LL_TIM_Init(TIM7, &TIM_InitStruct);
+ 3596              		.loc 2 1160 29 is_stmt 0 view .LVU1224
+ 3597 004e 6323     		movs	r3, #99
+ 3598 0050 0393     		str	r3, [sp, #12]
+1161:Src/main.c    ****   LL_TIM_DisableARRPreload(TIM7);
+ 3599              		.loc 2 1161 3 is_stmt 1 view .LVU1225
+ 3600 0052 0D4C     		ldr	r4, .L138+12
+ 3601 0054 01A9     		add	r1, sp, #4
+ 3602 0056 2046     		mov	r0, r4
+ 3603 0058 FFF7FEFF 		bl	LL_TIM_Init
+ 3604              	.LVL262:
+1162:Src/main.c    ****   LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE);
+ 3605              		.loc 2 1162 3 view .LVU1226
+ 3606              	.LBB436:
+ 3607              	.LBI436:
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 3608              		.loc 5 1504 22 view .LVU1227
+ 3609              	.LBB437:
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3610              		.loc 5 1506 3 view .LVU1228
+ 3611 005c 2368     		ldr	r3, [r4]
+ 3612 005e 23F08003 		bic	r3, r3, #128
+ 3613 0062 2360     		str	r3, [r4]
+ 3614              	.LVL263:
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3615              		.loc 5 1506 3 is_stmt 0 view .LVU1229
+ 3616              	.LBE437:
+ 3617              	.LBE436:
+1163:Src/main.c    ****   LL_TIM_DisableMasterSlaveMode(TIM7);
+ 3618              		.loc 2 1163 3 is_stmt 1 view .LVU1230
+ 3619              	.LBB438:
+ 3620              	.LBI438:
+3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 3621              		.loc 5 3138 22 view .LVU1231
+ 3622              	.LBB439:
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3623              		.loc 5 3140 3 view .LVU1232
+ 3624 0064 6368     		ldr	r3, [r4, #4]
+ 3625 0066 23F07003 		bic	r3, r3, #112
+ 3626 006a 43F01003 		orr	r3, r3, #16
+ 3627 006e 6360     		str	r3, [r4, #4]
+ 3628              	.LVL264:
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3629              		.loc 5 3140 3 is_stmt 0 view .LVU1233
+ 3630              	.LBE439:
+ 3631              	.LBE438:
+1164:Src/main.c    ****   /* USER CODE BEGIN TIM7_Init 2 */
+ 3632              		.loc 2 1164 3 is_stmt 1 view .LVU1234
+ 3633              	.LBB440:
+ 3634              	.LBI440:
+ARM GAS  /tmp/ccdsDELB.s 			page 262
+
+
+3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 3635              		.loc 5 3235 22 view .LVU1235
+ 3636              	.LBB441:
+ 3637              		.loc 5 3237 3 view .LVU1236
+ 3638 0070 A368     		ldr	r3, [r4, #8]
+ 3639 0072 23F08003 		bic	r3, r3, #128
+ 3640 0076 A360     		str	r3, [r4, #8]
+ 3641              	.LVL265:
+ 3642              		.loc 5 3237 3 is_stmt 0 view .LVU1237
+ 3643              	.LBE441:
+ 3644              	.LBE440:
+1169:Src/main.c    **** 
+ 3645              		.loc 2 1169 1 view .LVU1238
+ 3646 0078 06B0     		add	sp, sp, #24
+ 3647              	.LCFI33:
+ 3648              		.cfi_def_cfa_offset 8
+ 3649              		@ sp needed
+ 3650 007a 10BD     		pop	{r4, pc}
+ 3651              	.L139:
+ 3652              		.align	2
+ 3653              	.L138:
+ 3654 007c 00380240 		.word	1073887232
+ 3655 0080 00ED00E0 		.word	-536810240
+ 3656 0084 00E100E0 		.word	-536813312
+ 3657 0088 00140040 		.word	1073746944
+ 3658              		.cfi_endproc
+ 3659              	.LFE1198:
+ 3661              		.section	.text.MX_TIM6_Init,"ax",%progbits
+ 3662              		.align	1
+ 3663              		.syntax unified
+ 3664              		.thumb
+ 3665              		.thumb_func
+ 3666              		.fpu fpv5-d16
+ 3668              	MX_TIM6_Init:
+ 3669              	.LFB1197:
+1103:Src/main.c    **** 
+ 3670              		.loc 2 1103 1 is_stmt 1 view -0
+ 3671              		.cfi_startproc
+ 3672              		@ args = 0, pretend = 0, frame = 24
+ 3673              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3674 0000 10B5     		push	{r4, lr}
+ 3675              	.LCFI34:
+ 3676              		.cfi_def_cfa_offset 8
+ 3677              		.cfi_offset 4, -8
+ 3678              		.cfi_offset 14, -4
+ 3679 0002 86B0     		sub	sp, sp, #24
+ 3680              	.LCFI35:
+ 3681              		.cfi_def_cfa_offset 32
+1109:Src/main.c    **** 
+ 3682              		.loc 2 1109 3 view .LVU1240
+1109:Src/main.c    **** 
+ 3683              		.loc 2 1109 22 is_stmt 0 view .LVU1241
+ 3684 0004 0024     		movs	r4, #0
+ 3685 0006 0194     		str	r4, [sp, #4]
+ 3686 0008 0294     		str	r4, [sp, #8]
+ 3687 000a 0394     		str	r4, [sp, #12]
+ 3688 000c 0494     		str	r4, [sp, #16]
+ARM GAS  /tmp/ccdsDELB.s 			page 263
+
+
+ 3689 000e 0594     		str	r4, [sp, #20]
+1112:Src/main.c    **** 
+ 3690              		.loc 2 1112 3 is_stmt 1 view .LVU1242
+ 3691              	.LVL266:
+ 3692              	.LBB442:
+ 3693              	.LBI442:
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 3694              		.loc 3 1071 22 view .LVU1243
+ 3695              	.LBB443:
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1ENR, Periphs);
+ 3696              		.loc 3 1073 3 view .LVU1244
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 3697              		.loc 3 1074 3 view .LVU1245
+ 3698 0010 1A4B     		ldr	r3, .L142
+ 3699 0012 1A6C     		ldr	r2, [r3, #64]
+ 3700 0014 42F01002 		orr	r2, r2, #16
+ 3701 0018 1A64     		str	r2, [r3, #64]
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3702              		.loc 3 1076 3 view .LVU1246
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3703              		.loc 3 1076 12 is_stmt 0 view .LVU1247
+ 3704 001a 1B6C     		ldr	r3, [r3, #64]
+ 3705 001c 03F01003 		and	r3, r3, #16
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 3706              		.loc 3 1076 10 view .LVU1248
+ 3707 0020 0093     		str	r3, [sp]
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 3708              		.loc 3 1077 3 is_stmt 1 view .LVU1249
+ 3709 0022 009B     		ldr	r3, [sp]
+ 3710              	.LVL267:
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 3711              		.loc 3 1077 3 is_stmt 0 view .LVU1250
+ 3712              	.LBE443:
+ 3713              	.LBE442:
+1115:Src/main.c    ****   NVIC_EnableIRQ(TIM6_DAC_IRQn);
+ 3714              		.loc 2 1115 3 is_stmt 1 view .LVU1251
+ 3715              	.LBB444:
+ 3716              	.LBI444:
+1884:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3717              		.loc 1 1884 26 view .LVU1252
+ 3718              	.LBB445:
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 3719              		.loc 1 1886 3 view .LVU1253
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 3720              		.loc 1 1886 26 is_stmt 0 view .LVU1254
+ 3721 0024 164B     		ldr	r3, .L142+4
+ 3722 0026 D868     		ldr	r0, [r3, #12]
+ 3723              	.LBE445:
+ 3724              	.LBE444:
+1115:Src/main.c    ****   NVIC_EnableIRQ(TIM6_DAC_IRQn);
+ 3725              		.loc 2 1115 3 view .LVU1255
+ 3726 0028 2246     		mov	r2, r4
+ 3727 002a 2146     		mov	r1, r4
+ 3728 002c C0F30220 		ubfx	r0, r0, #8, #3
+ 3729 0030 FFF7FEFF 		bl	NVIC_EncodePriority
+ 3730              	.LVL268:
+ 3731              	.LBB446:
+ARM GAS  /tmp/ccdsDELB.s 			page 264
+
+
+ 3732              	.LBI446:
+2024:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3733              		.loc 1 2024 22 is_stmt 1 view .LVU1256
+ 3734              	.LBB447:
+2026:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 3735              		.loc 1 2026 3 view .LVU1257
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3736              		.loc 1 2028 5 view .LVU1258
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3737              		.loc 1 2028 49 is_stmt 0 view .LVU1259
+ 3738 0034 0001     		lsls	r0, r0, #4
+ 3739              	.LVL269:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3740              		.loc 1 2028 49 view .LVU1260
+ 3741 0036 C0B2     		uxtb	r0, r0
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3742              		.loc 1 2028 47 view .LVU1261
+ 3743 0038 124B     		ldr	r3, .L142+8
+ 3744 003a 83F83603 		strb	r0, [r3, #822]
+ 3745              	.LVL270:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3746              		.loc 1 2028 47 view .LVU1262
+ 3747              	.LBE447:
+ 3748              	.LBE446:
+1116:Src/main.c    **** 
+ 3749              		.loc 2 1116 3 is_stmt 1 view .LVU1263
+ 3750              	.LBB448:
+ 3751              	.LBI448:
+1896:Drivers/CMSIS/Include/core_cm7.h **** {
+ 3752              		.loc 1 1896 22 view .LVU1264
+ 3753              	.LBB449:
+1898:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 3754              		.loc 1 1898 3 view .LVU1265
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3755              		.loc 1 1900 5 view .LVU1266
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3756              		.loc 1 1900 43 is_stmt 0 view .LVU1267
+ 3757 003e 4FF48002 		mov	r2, #4194304
+ 3758 0042 5A60     		str	r2, [r3, #4]
+ 3759              	.LVL271:
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 3760              		.loc 1 1900 43 view .LVU1268
+ 3761              	.LBE449:
+ 3762              	.LBE448:
+1121:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+ 3763              		.loc 2 1121 3 is_stmt 1 view .LVU1269
+1121:Src/main.c    ****   TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+ 3764              		.loc 2 1121 28 is_stmt 0 view .LVU1270
+ 3765 0044 4BF2AF33 		movw	r3, #45999
+ 3766 0048 ADF80430 		strh	r3, [sp, #4]	@ movhi
+1122:Src/main.c    ****   TIM_InitStruct.Autoreload = 19;
+ 3767              		.loc 2 1122 3 is_stmt 1 view .LVU1271
+1122:Src/main.c    ****   TIM_InitStruct.Autoreload = 19;
+ 3768              		.loc 2 1122 30 is_stmt 0 view .LVU1272
+ 3769 004c 0294     		str	r4, [sp, #8]
+1123:Src/main.c    ****   LL_TIM_Init(TIM6, &TIM_InitStruct);
+ 3770              		.loc 2 1123 3 is_stmt 1 view .LVU1273
+ARM GAS  /tmp/ccdsDELB.s 			page 265
+
+
+1123:Src/main.c    ****   LL_TIM_Init(TIM6, &TIM_InitStruct);
+ 3771              		.loc 2 1123 29 is_stmt 0 view .LVU1274
+ 3772 004e 1323     		movs	r3, #19
+ 3773 0050 0393     		str	r3, [sp, #12]
+1124:Src/main.c    ****   LL_TIM_DisableARRPreload(TIM6);
+ 3774              		.loc 2 1124 3 is_stmt 1 view .LVU1275
+ 3775 0052 0D4C     		ldr	r4, .L142+12
+ 3776 0054 01A9     		add	r1, sp, #4
+ 3777 0056 2046     		mov	r0, r4
+ 3778 0058 FFF7FEFF 		bl	LL_TIM_Init
+ 3779              	.LVL272:
+1125:Src/main.c    ****   LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE);
+ 3780              		.loc 2 1125 3 view .LVU1276
+ 3781              	.LBB450:
+ 3782              	.LBI450:
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 3783              		.loc 5 1504 22 view .LVU1277
+ 3784              	.LBB451:
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3785              		.loc 5 1506 3 view .LVU1278
+ 3786 005c 2368     		ldr	r3, [r4]
+ 3787 005e 23F08003 		bic	r3, r3, #128
+ 3788 0062 2360     		str	r3, [r4]
+ 3789              	.LVL273:
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3790              		.loc 5 1506 3 is_stmt 0 view .LVU1279
+ 3791              	.LBE451:
+ 3792              	.LBE450:
+1126:Src/main.c    ****   LL_TIM_DisableMasterSlaveMode(TIM6);
+ 3793              		.loc 2 1126 3 is_stmt 1 view .LVU1280
+ 3794              	.LBB452:
+ 3795              	.LBI452:
+3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 3796              		.loc 5 3138 22 view .LVU1281
+ 3797              	.LBB453:
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3798              		.loc 5 3140 3 view .LVU1282
+ 3799 0064 6368     		ldr	r3, [r4, #4]
+ 3800 0066 23F07003 		bic	r3, r3, #112
+ 3801 006a 43F01003 		orr	r3, r3, #16
+ 3802 006e 6360     		str	r3, [r4, #4]
+ 3803              	.LVL274:
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 3804              		.loc 5 3140 3 is_stmt 0 view .LVU1283
+ 3805              	.LBE453:
+ 3806              	.LBE452:
+1127:Src/main.c    ****   /* USER CODE BEGIN TIM6_Init 2 */
+ 3807              		.loc 2 1127 3 is_stmt 1 view .LVU1284
+ 3808              	.LBB454:
+ 3809              	.LBI454:
+3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 3810              		.loc 5 3235 22 view .LVU1285
+ 3811              	.LBB455:
+ 3812              		.loc 5 3237 3 view .LVU1286
+ 3813 0070 A368     		ldr	r3, [r4, #8]
+ 3814 0072 23F08003 		bic	r3, r3, #128
+ 3815 0076 A360     		str	r3, [r4, #8]
+ARM GAS  /tmp/ccdsDELB.s 			page 266
+
+
+ 3816              	.LVL275:
+ 3817              		.loc 5 3237 3 is_stmt 0 view .LVU1287
+ 3818              	.LBE455:
+ 3819              	.LBE454:
+1132:Src/main.c    **** 
+ 3820              		.loc 2 1132 1 view .LVU1288
+ 3821 0078 06B0     		add	sp, sp, #24
+ 3822              	.LCFI36:
+ 3823              		.cfi_def_cfa_offset 8
+ 3824              		@ sp needed
+ 3825 007a 10BD     		pop	{r4, pc}
+ 3826              	.L143:
+ 3827              		.align	2
+ 3828              	.L142:
+ 3829 007c 00380240 		.word	1073887232
+ 3830 0080 00ED00E0 		.word	-536810240
+ 3831 0084 00E100E0 		.word	-536813312
+ 3832 0088 00100040 		.word	1073745920
+ 3833              		.cfi_endproc
+ 3834              	.LFE1197:
+ 3836              		.section	.rodata.Decode_uart.str1.4,"aMS",%progbits,1
+ 3837              		.align	2
+ 3838              	.LC0:
+ 3839 0000 2F00     		.ascii	"/\000"
+ 3840 0002 0000     		.align	2
+ 3841              	.LC1:
+ 3842 0004 434F4D4D 		.ascii	"COMMAND.TXT\000"
+ 3842      414E442E 
+ 3842      54585400 
+ 3843              		.section	.text.Decode_uart,"ax",%progbits
+ 3844              		.align	1
+ 3845              		.syntax unified
+ 3846              		.thumb
+ 3847              		.thumb_func
+ 3848              		.fpu fpv5-d16
+ 3850              	Decode_uart:
+ 3851              	.LVL276:
+ 3852              	.LFB1204:
+1596:Src/main.c    **** //	uint8_t *temp1;
+ 3853              		.loc 2 1596 1 is_stmt 1 view -0
+ 3854              		.cfi_startproc
+ 3855              		@ args = 0, pretend = 0, frame = 0
+ 3856              		@ frame_needed = 0, uses_anonymous_args = 0
+1596:Src/main.c    **** //	uint8_t *temp1;
+ 3857              		.loc 2 1596 1 is_stmt 0 view .LVU1290
+ 3858 0000 2DE9F843 		push	{r3, r4, r5, r6, r7, r8, r9, lr}
+ 3859              	.LCFI37:
+ 3860              		.cfi_def_cfa_offset 32
+ 3861              		.cfi_offset 3, -32
+ 3862              		.cfi_offset 4, -28
+ 3863              		.cfi_offset 5, -24
+ 3864              		.cfi_offset 6, -20
+ 3865              		.cfi_offset 7, -16
+ 3866              		.cfi_offset 8, -12
+ 3867              		.cfi_offset 9, -8
+ 3868              		.cfi_offset 14, -4
+ 3869 0004 0546     		mov	r5, r0
+ARM GAS  /tmp/ccdsDELB.s 			page 267
+
+
+ 3870 0006 0F46     		mov	r7, r1
+ 3871 0008 1646     		mov	r6, r2
+ 3872 000a 1C46     		mov	r4, r3
+1598:Src/main.c    **** 	
+ 3873              		.loc 2 1598 2 is_stmt 1 view .LVU1291
+1603:Src/main.c    **** 	if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&&
+ 3874              		.loc 2 1603 2 view .LVU1292
+1603:Src/main.c    **** 	if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&&
+ 3875              		.loc 2 1603 6 is_stmt 0 view .LVU1293
+ 3876 000c AF4B     		ldr	r3, .L168
+ 3877              	.LVL277:
+1603:Src/main.c    **** 	if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&&
+ 3878              		.loc 2 1603 6 view .LVU1294
+ 3879 000e 0022     		movs	r2, #0
+ 3880              	.LVL278:
+1603:Src/main.c    **** 	if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&&
+ 3881              		.loc 2 1603 6 view .LVU1295
+ 3882 0010 1A60     		str	r2, [r3]
+1604:Src/main.c    **** 		  (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u
+ 3883              		.loc 2 1604 2 is_stmt 1 view .LVU1296
+1604:Src/main.c    **** 		  (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u
+ 3884              		.loc 2 1604 7 is_stmt 0 view .LVU1297
+ 3885 0012 0121     		movs	r1, #1
+ 3886              	.LVL279:
+1604:Src/main.c    **** 		  (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u
+ 3887              		.loc 2 1604 7 view .LVU1298
+ 3888 0014 AE48     		ldr	r0, .L168+4
+ 3889              	.LVL280:
+1604:Src/main.c    **** 		  (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u
+ 3890              		.loc 2 1604 7 view .LVU1299
+ 3891 0016 FFF7FEFF 		bl	HAL_GPIO_ReadPin
+ 3892              	.LVL281:
+1604:Src/main.c    **** 		  (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u
+ 3893              		.loc 2 1604 5 view .LVU1300
+ 3894 001a 0028     		cmp	r0, #0
+ 3895 001c 00F0D280 		beq	.L165
+ 3896              	.L145:
+1619:Src/main.c    **** 	Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01;
+ 3897              		.loc 2 1619 2 is_stmt 1 view .LVU1301
+ 3898              	.LVL282:
+1620:Src/main.c    **** 	Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01;
+ 3899              		.loc 2 1620 2 view .LVU1302
+1620:Src/main.c    **** 	Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01;
+ 3900              		.loc 2 1620 36 is_stmt 0 view .LVU1303
+ 3901 0020 2B88     		ldrh	r3, [r5]
+1620:Src/main.c    **** 	Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01;
+ 3902              		.loc 2 1620 48 view .LVU1304
+ 3903 0022 03F00103 		and	r3, r3, #1
+1620:Src/main.c    **** 	Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01;
+ 3904              		.loc 2 1620 22 view .LVU1305
+ 3905 0026 2370     		strb	r3, [r4]
+1621:Src/main.c    **** 	Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01;
+ 3906              		.loc 2 1621 2 is_stmt 1 view .LVU1306
+1621:Src/main.c    **** 	Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01;
+ 3907              		.loc 2 1621 36 is_stmt 0 view .LVU1307
+ 3908 0028 2B88     		ldrh	r3, [r5]
+1621:Src/main.c    **** 	Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01;
+ARM GAS  /tmp/ccdsDELB.s 			page 268
+
+
+ 3909              		.loc 2 1621 48 view .LVU1308
+ 3910 002a C3F34003 		ubfx	r3, r3, #1, #1
+1621:Src/main.c    **** 	Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01;
+ 3911              		.loc 2 1621 22 view .LVU1309
+ 3912 002e 6370     		strb	r3, [r4, #1]
+1622:Src/main.c    **** 	Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01;
+ 3913              		.loc 2 1622 2 is_stmt 1 view .LVU1310
+1622:Src/main.c    **** 	Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01;
+ 3914              		.loc 2 1622 36 is_stmt 0 view .LVU1311
+ 3915 0030 2B88     		ldrh	r3, [r5]
+1622:Src/main.c    **** 	Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01;
+ 3916              		.loc 2 1622 48 view .LVU1312
+ 3917 0032 C3F38003 		ubfx	r3, r3, #2, #1
+1622:Src/main.c    **** 	Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01;
+ 3918              		.loc 2 1622 22 view .LVU1313
+ 3919 0036 A370     		strb	r3, [r4, #2]
+1623:Src/main.c    **** 	Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01;
+ 3920              		.loc 2 1623 2 is_stmt 1 view .LVU1314
+1623:Src/main.c    **** 	Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01;
+ 3921              		.loc 2 1623 35 is_stmt 0 view .LVU1315
+ 3922 0038 2B88     		ldrh	r3, [r5]
+1623:Src/main.c    **** 	Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01;
+ 3923              		.loc 2 1623 47 view .LVU1316
+ 3924 003a C3F3C003 		ubfx	r3, r3, #3, #1
+1623:Src/main.c    **** 	Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01;
+ 3925              		.loc 2 1623 21 view .LVU1317
+ 3926 003e E370     		strb	r3, [r4, #3]
+1624:Src/main.c    **** 	Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01;
+ 3927              		.loc 2 1624 2 is_stmt 1 view .LVU1318
+1624:Src/main.c    **** 	Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01;
+ 3928              		.loc 2 1624 35 is_stmt 0 view .LVU1319
+ 3929 0040 2B88     		ldrh	r3, [r5]
+1624:Src/main.c    **** 	Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01;
+ 3930              		.loc 2 1624 47 view .LVU1320
+ 3931 0042 C3F30013 		ubfx	r3, r3, #4, #1
+1624:Src/main.c    **** 	Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01;
+ 3932              		.loc 2 1624 21 view .LVU1321
+ 3933 0046 2371     		strb	r3, [r4, #4]
+1625:Src/main.c    **** 	Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01;
+ 3934              		.loc 2 1625 2 is_stmt 1 view .LVU1322
+1625:Src/main.c    **** 	Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01;
+ 3935              		.loc 2 1625 36 is_stmt 0 view .LVU1323
+ 3936 0048 2B88     		ldrh	r3, [r5]
+1625:Src/main.c    **** 	Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01;
+ 3937              		.loc 2 1625 48 view .LVU1324
+ 3938 004a C3F34013 		ubfx	r3, r3, #5, #1
+1625:Src/main.c    **** 	Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01;
+ 3939              		.loc 2 1625 22 view .LVU1325
+ 3940 004e 6371     		strb	r3, [r4, #5]
+1626:Src/main.c    **** 	Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01;
+ 3941              		.loc 2 1626 2 is_stmt 1 view .LVU1326
+1626:Src/main.c    **** 	Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01;
+ 3942              		.loc 2 1626 36 is_stmt 0 view .LVU1327
+ 3943 0050 2B88     		ldrh	r3, [r5]
+1626:Src/main.c    **** 	Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01;
+ 3944              		.loc 2 1626 48 view .LVU1328
+ 3945 0052 C3F38013 		ubfx	r3, r3, #6, #1
+ARM GAS  /tmp/ccdsDELB.s 			page 269
+
+
+1626:Src/main.c    **** 	Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01;
+ 3946              		.loc 2 1626 22 view .LVU1329
+ 3947 0056 A371     		strb	r3, [r4, #6]
+1627:Src/main.c    **** 	Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01;
+ 3948              		.loc 2 1627 2 is_stmt 1 view .LVU1330
+1627:Src/main.c    **** 	Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01;
+ 3949              		.loc 2 1627 36 is_stmt 0 view .LVU1331
+ 3950 0058 2B88     		ldrh	r3, [r5]
+1627:Src/main.c    **** 	Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01;
+ 3951              		.loc 2 1627 48 view .LVU1332
+ 3952 005a C3F3C013 		ubfx	r3, r3, #7, #1
+1627:Src/main.c    **** 	Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01;
+ 3953              		.loc 2 1627 22 view .LVU1333
+ 3954 005e E371     		strb	r3, [r4, #7]
+1628:Src/main.c    **** 	Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01;
+ 3955              		.loc 2 1628 2 is_stmt 1 view .LVU1334
+1628:Src/main.c    **** 	Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01;
+ 3956              		.loc 2 1628 36 is_stmt 0 view .LVU1335
+ 3957 0060 2B88     		ldrh	r3, [r5]
+1628:Src/main.c    **** 	Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01;
+ 3958              		.loc 2 1628 48 view .LVU1336
+ 3959 0062 C3F30023 		ubfx	r3, r3, #8, #1
+1628:Src/main.c    **** 	Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01;
+ 3960              		.loc 2 1628 22 view .LVU1337
+ 3961 0066 2372     		strb	r3, [r4, #8]
+1629:Src/main.c    **** 	Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01;
+ 3962              		.loc 2 1629 2 is_stmt 1 view .LVU1338
+1629:Src/main.c    **** 	Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01;
+ 3963              		.loc 2 1629 35 is_stmt 0 view .LVU1339
+ 3964 0068 2B88     		ldrh	r3, [r5]
+1629:Src/main.c    **** 	Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01;
+ 3965              		.loc 2 1629 47 view .LVU1340
+ 3966 006a C3F34023 		ubfx	r3, r3, #9, #1
+1629:Src/main.c    **** 	Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01;
+ 3967              		.loc 2 1629 21 view .LVU1341
+ 3968 006e 6372     		strb	r3, [r4, #9]
+1630:Src/main.c    **** 	Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01;
+ 3969              		.loc 2 1630 2 is_stmt 1 view .LVU1342
+1630:Src/main.c    **** 	Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01;
+ 3970              		.loc 2 1630 35 is_stmt 0 view .LVU1343
+ 3971 0070 2B88     		ldrh	r3, [r5]
+1630:Src/main.c    **** 	Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01;
+ 3972              		.loc 2 1630 48 view .LVU1344
+ 3973 0072 C3F38023 		ubfx	r3, r3, #10, #1
+1630:Src/main.c    **** 	Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01;
+ 3974              		.loc 2 1630 21 view .LVU1345
+ 3975 0076 A372     		strb	r3, [r4, #10]
+1631:Src/main.c    **** 	Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01;
+ 3976              		.loc 2 1631 2 is_stmt 1 view .LVU1346
+1631:Src/main.c    **** 	Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01;
+ 3977              		.loc 2 1631 34 is_stmt 0 view .LVU1347
+ 3978 0078 2B88     		ldrh	r3, [r5]
+1631:Src/main.c    **** 	Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01;
+ 3979              		.loc 2 1631 47 view .LVU1348
+ 3980 007a C3F3C023 		ubfx	r3, r3, #11, #1
+1631:Src/main.c    **** 	Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01;
+ 3981              		.loc 2 1631 20 view .LVU1349
+ARM GAS  /tmp/ccdsDELB.s 			page 270
+
+
+ 3982 007e E372     		strb	r3, [r4, #11]
+1632:Src/main.c    **** 	Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01;
+ 3983              		.loc 2 1632 2 is_stmt 1 view .LVU1350
+1632:Src/main.c    **** 	Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01;
+ 3984              		.loc 2 1632 35 is_stmt 0 view .LVU1351
+ 3985 0080 2B88     		ldrh	r3, [r5]
+1632:Src/main.c    **** 	Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01;
+ 3986              		.loc 2 1632 48 view .LVU1352
+ 3987 0082 C3F30033 		ubfx	r3, r3, #12, #1
+1632:Src/main.c    **** 	Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01;
+ 3988              		.loc 2 1632 21 view .LVU1353
+ 3989 0086 2373     		strb	r3, [r4, #12]
+1633:Src/main.c    **** 	
+ 3990              		.loc 2 1633 2 is_stmt 1 view .LVU1354
+1633:Src/main.c    **** 	
+ 3991              		.loc 2 1633 35 is_stmt 0 view .LVU1355
+ 3992 0088 2B88     		ldrh	r3, [r5]
+1633:Src/main.c    **** 	
+ 3993              		.loc 2 1633 48 view .LVU1356
+ 3994 008a C3F34033 		ubfx	r3, r3, #13, #1
+1633:Src/main.c    **** 	
+ 3995              		.loc 2 1633 21 view .LVU1357
+ 3996 008e 6373     		strb	r3, [r4, #13]
+1635:Src/main.c    **** 	LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2);
+ 3997              		.loc 2 1635 2 is_stmt 1 view .LVU1358
+ 3998              	.LVL283:
+1636:Src/main.c    **** 	temp2++;
+ 3999              		.loc 2 1636 2 view .LVU1359
+1636:Src/main.c    **** 	temp2++;
+ 4000              		.loc 2 1636 28 is_stmt 0 view .LVU1360
+ 4001 0090 6B88     		ldrh	r3, [r5, #2]
+1636:Src/main.c    **** 	temp2++;
+ 4002              		.loc 2 1636 26 view .LVU1361
+ 4003 0092 3B80     		strh	r3, [r7]	@ movhi
+1637:Src/main.c    **** 	LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2);
+ 4004              		.loc 2 1637 2 is_stmt 1 view .LVU1362
+ 4005              	.LVL284:
+1638:Src/main.c    **** 	temp2++;
+ 4006              		.loc 2 1638 2 view .LVU1363
+1638:Src/main.c    **** 	temp2++;
+ 4007              		.loc 2 1638 28 is_stmt 0 view .LVU1364
+ 4008 0094 AB88     		ldrh	r3, [r5, #4]
+1638:Src/main.c    **** 	temp2++;
+ 4009              		.loc 2 1638 26 view .LVU1365
+ 4010 0096 3380     		strh	r3, [r6]	@ movhi
+1639:Src/main.c    **** 	temp2++;
+ 4011              		.loc 2 1639 2 is_stmt 1 view .LVU1366
+ 4012              	.LVL285:
+1640:Src/main.c    **** 	temp2++;
+ 4013              		.loc 2 1640 2 view .LVU1367
+1641:Src/main.c    **** 	Curr_setup->AVERAGES = (uint16_t)(*temp2);
+ 4014              		.loc 2 1641 2 view .LVU1368
+1642:Src/main.c    **** 	temp2++;
+ 4015              		.loc 2 1642 2 view .LVU1369
+1642:Src/main.c    **** 	temp2++;
+ 4016              		.loc 2 1642 25 is_stmt 0 view .LVU1370
+ 4017 0098 6B89     		ldrh	r3, [r5, #10]
+ARM GAS  /tmp/ccdsDELB.s 			page 271
+
+
+1642:Src/main.c    **** 	temp2++;
+ 4018              		.loc 2 1642 23 view .LVU1371
+ 4019 009a E381     		strh	r3, [r4, #14]	@ movhi
+1643:Src/main.c    **** 	LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint
+ 4020              		.loc 2 1643 2 is_stmt 1 view .LVU1372
+ 4021              	.LVL286:
+1644:Src/main.c    **** 	temp2++;
+ 4022              		.loc 2 1644 2 view .LVU1373
+1644:Src/main.c    **** 	temp2++;
+ 4023              		.loc 2 1644 51 is_stmt 0 view .LVU1374
+ 4024 009c AB89     		ldrh	r3, [r5, #12]
+ 4025 009e 07EE103A 		vmov	s14, r3	@ int
+1644:Src/main.c    **** 	temp2++;
+ 4026              		.loc 2 1644 32 view .LVU1375
+ 4027 00a2 B8EE477A 		vcvt.f32.u32	s14, s14
+1644:Src/main.c    **** 	temp2++;
+ 4028              		.loc 2 1644 59 view .LVU1376
+ 4029 00a6 DFED8B6A 		vldr.32	s13, .L168+8
+ 4030 00aa 27EE267A 		vmul.f32	s14, s14, s13
+1644:Src/main.c    **** 	temp2++;
+ 4031              		.loc 2 1644 30 view .LVU1377
+ 4032 00ae 87ED017A 		vstr.32	s14, [r7, #4]
+1645:Src/main.c    **** 	LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint
+ 4033              		.loc 2 1645 2 is_stmt 1 view .LVU1378
+ 4034              	.LVL287:
+1646:Src/main.c    **** 	temp2++;
+ 4035              		.loc 2 1646 2 view .LVU1379
+1646:Src/main.c    **** 	temp2++;
+ 4036              		.loc 2 1646 51 is_stmt 0 view .LVU1380
+ 4037 00b2 EB89     		ldrh	r3, [r5, #14]
+ 4038 00b4 07EE103A 		vmov	s14, r3	@ int
+1646:Src/main.c    **** 	temp2++;
+ 4039              		.loc 2 1646 32 view .LVU1381
+ 4040 00b8 B8EE477A 		vcvt.f32.u32	s14, s14
+1646:Src/main.c    **** 	temp2++;
+ 4041              		.loc 2 1646 59 view .LVU1382
+ 4042 00bc 27EE267A 		vmul.f32	s14, s14, s13
+1646:Src/main.c    **** 	temp2++;
+ 4043              		.loc 2 1646 30 view .LVU1383
+ 4044 00c0 87ED027A 		vstr.32	s14, [r7, #8]
+1647:Src/main.c    **** 	LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint
+ 4045              		.loc 2 1647 2 is_stmt 1 view .LVU1384
+ 4046              	.LVL288:
+1648:Src/main.c    **** 	temp2++;
+ 4047              		.loc 2 1648 2 view .LVU1385
+1648:Src/main.c    **** 	temp2++;
+ 4048              		.loc 2 1648 51 is_stmt 0 view .LVU1386
+ 4049 00c4 2B8A     		ldrh	r3, [r5, #16]
+ 4050 00c6 07EE103A 		vmov	s14, r3	@ int
+1648:Src/main.c    **** 	temp2++;
+ 4051              		.loc 2 1648 32 view .LVU1387
+ 4052 00ca B8EE477A 		vcvt.f32.u32	s14, s14
+1648:Src/main.c    **** 	temp2++;
+ 4053              		.loc 2 1648 59 view .LVU1388
+ 4054 00ce 27EE267A 		vmul.f32	s14, s14, s13
+1648:Src/main.c    **** 	temp2++;
+ 4055              		.loc 2 1648 30 view .LVU1389
+ARM GAS  /tmp/ccdsDELB.s 			page 272
+
+
+ 4056 00d2 86ED017A 		vstr.32	s14, [r6, #4]
+1649:Src/main.c    **** 	LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint
+ 4057              		.loc 2 1649 2 is_stmt 1 view .LVU1390
+ 4058              	.LVL289:
+1650:Src/main.c    **** 	temp2++;
+ 4059              		.loc 2 1650 2 view .LVU1391
+1650:Src/main.c    **** 	temp2++;
+ 4060              		.loc 2 1650 51 is_stmt 0 view .LVU1392
+ 4061 00d6 6B8A     		ldrh	r3, [r5, #18]
+ 4062 00d8 07EE903A 		vmov	s15, r3	@ int
+1650:Src/main.c    **** 	temp2++;
+ 4063              		.loc 2 1650 32 view .LVU1393
+ 4064 00dc F8EE677A 		vcvt.f32.u32	s15, s15
+1650:Src/main.c    **** 	temp2++;
+ 4065              		.loc 2 1650 59 view .LVU1394
+ 4066 00e0 67EEA67A 		vmul.f32	s15, s15, s13
+1650:Src/main.c    **** 	temp2++;
+ 4067              		.loc 2 1650 30 view .LVU1395
+ 4068 00e4 C6ED027A 		vstr.32	s15, [r6, #8]
+1651:Src/main.c    **** 	Long_Data[13] = (uint16_t)(*temp2);//Message ID
+ 4069              		.loc 2 1651 2 is_stmt 1 view .LVU1396
+ 4070              	.LVL290:
+1652:Src/main.c    **** 	temp2++;
+ 4071              		.loc 2 1652 2 view .LVU1397
+1652:Src/main.c    **** 	temp2++;
+ 4072              		.loc 2 1652 18 is_stmt 0 view .LVU1398
+ 4073 00e8 AA8A     		ldrh	r2, [r5, #20]
+1652:Src/main.c    **** 	temp2++;
+ 4074              		.loc 2 1652 16 view .LVU1399
+ 4075 00ea 7B4B     		ldr	r3, .L168+12
+ 4076 00ec 5A83     		strh	r2, [r3, #26]	@ movhi
+1653:Src/main.c    **** 	LD1_curr_setup->CURRENT = (uint16_t)(*temp2);
+ 4077              		.loc 2 1653 2 is_stmt 1 view .LVU1400
+ 4078              	.LVL291:
+1654:Src/main.c    **** 	temp2++;
+ 4079              		.loc 2 1654 2 view .LVU1401
+1654:Src/main.c    **** 	temp2++;
+ 4080              		.loc 2 1654 28 is_stmt 0 view .LVU1402
+ 4081 00ee EB8A     		ldrh	r3, [r5, #22]
+1654:Src/main.c    **** 	temp2++;
+ 4082              		.loc 2 1654 26 view .LVU1403
+ 4083 00f0 BB81     		strh	r3, [r7, #12]	@ movhi
+1655:Src/main.c    **** 	LD2_curr_setup->CURRENT = (uint16_t)(*temp2);
+ 4084              		.loc 2 1655 2 is_stmt 1 view .LVU1404
+ 4085              	.LVL292:
+1656:Src/main.c    **** 	temp2++;
+ 4086              		.loc 2 1656 2 view .LVU1405
+1656:Src/main.c    **** 	temp2++;
+ 4087              		.loc 2 1656 28 is_stmt 0 view .LVU1406
+ 4088 00f2 2B8B     		ldrh	r3, [r5, #24]
+1656:Src/main.c    **** 	temp2++;
+ 4089              		.loc 2 1656 26 view .LVU1407
+ 4090 00f4 B381     		strh	r3, [r6, #12]	@ movhi
+1657:Src/main.c    **** 	
+ 4091              		.loc 2 1657 2 is_stmt 1 view .LVU1408
+ 4092              	.LVL293:
+1659:Src/main.c    **** 	{
+ARM GAS  /tmp/ccdsDELB.s 			page 273
+
+
+ 4093              		.loc 2 1659 2 view .LVU1409
+1659:Src/main.c    **** 	{
+ 4094              		.loc 2 1659 16 is_stmt 0 view .LVU1410
+ 4095 00f6 6378     		ldrb	r3, [r4, #1]	@ zero_extendqisi2
+1659:Src/main.c    **** 	{
+ 4096              		.loc 2 1659 5 view .LVU1411
+ 4097 00f8 002B     		cmp	r3, #0
+ 4098 00fa 00F09580 		beq	.L146
+1661:Src/main.c    **** 	}
+ 4099              		.loc 2 1661 3 is_stmt 1 view .LVU1412
+ 4100 00fe 0122     		movs	r2, #1
+ 4101 0100 0821     		movs	r1, #8
+ 4102 0102 7648     		ldr	r0, .L168+16
+ 4103 0104 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4104              	.LVL294:
+ 4105              	.L147:
+1668:Src/main.c    **** 	{
+ 4106              		.loc 2 1668 2 view .LVU1413
+1668:Src/main.c    **** 	{
+ 4107              		.loc 2 1668 16 is_stmt 0 view .LVU1414
+ 4108 0108 A378     		ldrb	r3, [r4, #2]	@ zero_extendqisi2
+1668:Src/main.c    **** 	{
+ 4109              		.loc 2 1668 5 view .LVU1415
+ 4110 010a 002B     		cmp	r3, #0
+ 4111 010c 00F09280 		beq	.L148
+1670:Src/main.c    **** 	}
+ 4112              		.loc 2 1670 3 is_stmt 1 view .LVU1416
+ 4113 0110 0122     		movs	r2, #1
+ 4114 0112 0421     		movs	r1, #4
+ 4115 0114 7148     		ldr	r0, .L168+16
+ 4116 0116 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4117              	.LVL295:
+ 4118              	.L149:
+1677:Src/main.c    **** 	{
+ 4119              		.loc 2 1677 2 view .LVU1417
+1677:Src/main.c    **** 	{
+ 4120              		.loc 2 1677 16 is_stmt 0 view .LVU1418
+ 4121 011a E378     		ldrb	r3, [r4, #3]	@ zero_extendqisi2
+1677:Src/main.c    **** 	{
+ 4122              		.loc 2 1677 5 view .LVU1419
+ 4123 011c 002B     		cmp	r3, #0
+ 4124 011e 00F08F80 		beq	.L150
+1679:Src/main.c    **** 		//LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC
+ 4125              		.loc 2 1679 3 is_stmt 1 view .LVU1420
+ 4126 0122 0122     		movs	r2, #1
+ 4127 0124 4FF48071 		mov	r1, #256
+ 4128 0128 6948     		ldr	r0, .L168+4
+ 4129 012a FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4130              	.LVL296:
+ 4131              	.L151:
+1688:Src/main.c    **** 	{
+ 4132              		.loc 2 1688 2 view .LVU1421
+1688:Src/main.c    **** 	{
+ 4133              		.loc 2 1688 16 is_stmt 0 view .LVU1422
+ 4134 012e 2379     		ldrb	r3, [r4, #4]	@ zero_extendqisi2
+1688:Src/main.c    **** 	{
+ 4135              		.loc 2 1688 5 view .LVU1423
+ARM GAS  /tmp/ccdsDELB.s 			page 274
+
+
+ 4136 0130 002B     		cmp	r3, #0
+ 4137 0132 00F08C80 		beq	.L152
+1690:Src/main.c    **** 		//LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC
+ 4138              		.loc 2 1690 3 is_stmt 1 view .LVU1424
+ 4139 0136 0122     		movs	r2, #1
+ 4140 0138 1021     		movs	r1, #16
+ 4141 013a 6848     		ldr	r0, .L168+16
+ 4142 013c FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4143              	.LVL297:
+ 4144              	.L153:
+1699:Src/main.c    **** 	{
+ 4145              		.loc 2 1699 2 view .LVU1425
+1699:Src/main.c    **** 	{
+ 4146              		.loc 2 1699 16 is_stmt 0 view .LVU1426
+ 4147 0140 6379     		ldrb	r3, [r4, #5]	@ zero_extendqisi2
+1699:Src/main.c    **** 	{
+ 4148              		.loc 2 1699 5 view .LVU1427
+ 4149 0142 002B     		cmp	r3, #0
+ 4150 0144 00F08980 		beq	.L154
+1701:Src/main.c    **** 	}
+ 4151              		.loc 2 1701 3 is_stmt 1 view .LVU1428
+ 4152 0148 0122     		movs	r2, #1
+ 4153 014a 4FF48061 		mov	r1, #1024
+ 4154 014e 6448     		ldr	r0, .L168+20
+ 4155 0150 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4156              	.LVL298:
+ 4157              	.L155:
+1708:Src/main.c    **** 	{
+ 4158              		.loc 2 1708 2 view .LVU1429
+1708:Src/main.c    **** 	{
+ 4159              		.loc 2 1708 16 is_stmt 0 view .LVU1430
+ 4160 0154 A379     		ldrb	r3, [r4, #6]	@ zero_extendqisi2
+1708:Src/main.c    **** 	{
+ 4161              		.loc 2 1708 5 view .LVU1431
+ 4162 0156 002B     		cmp	r3, #0
+ 4163 0158 00F08680 		beq	.L156
+1710:Src/main.c    **** 	}
+ 4164              		.loc 2 1710 3 is_stmt 1 view .LVU1432
+ 4165 015c 0122     		movs	r2, #1
+ 4166 015e 0821     		movs	r1, #8
+ 4167 0160 6048     		ldr	r0, .L168+24
+ 4168 0162 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4169              	.LVL299:
+ 4170              	.L157:
+1717:Src/main.c    **** 	{
+ 4171              		.loc 2 1717 2 view .LVU1433
+1717:Src/main.c    **** 	{
+ 4172              		.loc 2 1717 17 is_stmt 0 view .LVU1434
+ 4173 0166 637A     		ldrb	r3, [r4, #9]	@ zero_extendqisi2
+1717:Src/main.c    **** 	{
+ 4174              		.loc 2 1717 5 view .LVU1435
+ 4175 0168 1BB1     		cbz	r3, .L158
+1717:Src/main.c    **** 	{
+ 4176              		.loc 2 1717 39 discriminator 1 view .LVU1436
+ 4177 016a E379     		ldrb	r3, [r4, #7]	@ zero_extendqisi2
+1717:Src/main.c    **** 	{
+ 4178              		.loc 2 1717 26 discriminator 1 view .LVU1437
+ARM GAS  /tmp/ccdsDELB.s 			page 275
+
+
+ 4179 016c 002B     		cmp	r3, #0
+ 4180 016e 40F08180 		bne	.L166
+ 4181              	.L158:
+1726:Src/main.c    **** 		HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET);		
+ 4182              		.loc 2 1726 3 is_stmt 1 view .LVU1438
+ 4183 0172 0022     		movs	r2, #0
+ 4184 0174 0121     		movs	r1, #1
+ 4185 0176 5B48     		ldr	r0, .L168+24
+ 4186 0178 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4187              	.LVL300:
+1727:Src/main.c    **** 	}
+ 4188              		.loc 2 1727 3 view .LVU1439
+ 4189 017c 0022     		movs	r2, #0
+ 4190 017e 4FF40061 		mov	r1, #2048
+ 4191 0182 5748     		ldr	r0, .L168+20
+ 4192 0184 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4193              	.LVL301:
+ 4194              	.L159:
+1730:Src/main.c    **** 	{
+ 4195              		.loc 2 1730 2 view .LVU1440
+1730:Src/main.c    **** 	{
+ 4196              		.loc 2 1730 17 is_stmt 0 view .LVU1441
+ 4197 0188 A37A     		ldrb	r3, [r4, #10]	@ zero_extendqisi2
+1730:Src/main.c    **** 	{
+ 4198              		.loc 2 1730 5 view .LVU1442
+ 4199 018a 1BB1     		cbz	r3, .L160
+1730:Src/main.c    **** 	{
+ 4200              		.loc 2 1730 39 discriminator 1 view .LVU1443
+ 4201 018c 237A     		ldrb	r3, [r4, #8]	@ zero_extendqisi2
+1730:Src/main.c    **** 	{
+ 4202              		.loc 2 1730 26 discriminator 1 view .LVU1444
+ 4203 018e 002B     		cmp	r3, #0
+ 4204 0190 40F08680 		bne	.L167
+ 4205              	.L160:
+1739:Src/main.c    **** 		HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET);		
+ 4206              		.loc 2 1739 3 is_stmt 1 view .LVU1445
+ 4207 0194 0022     		movs	r2, #0
+ 4208 0196 0221     		movs	r1, #2
+ 4209 0198 5248     		ldr	r0, .L168+24
+ 4210 019a FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4211              	.LVL302:
+1740:Src/main.c    **** 	}
+ 4212              		.loc 2 1740 3 view .LVU1446
+ 4213 019e 0022     		movs	r2, #0
+ 4214 01a0 2021     		movs	r1, #32
+ 4215 01a2 4E48     		ldr	r0, .L168+16
+ 4216 01a4 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4217              	.LVL303:
+ 4218              	.L161:
+1743:Src/main.c    **** 	{
+ 4219              		.loc 2 1743 2 view .LVU1447
+1743:Src/main.c    **** 	{
+ 4220              		.loc 2 1743 16 is_stmt 0 view .LVU1448
+ 4221 01a8 237B     		ldrb	r3, [r4, #12]	@ zero_extendqisi2
+1743:Src/main.c    **** 	{
+ 4222              		.loc 2 1743 5 view .LVU1449
+ 4223 01aa 1BB9     		cbnz	r3, .L162
+ARM GAS  /tmp/ccdsDELB.s 			page 276
+
+
+1745:Src/main.c    **** 		LD1_curr_setup->I_coef_temp = 0.01;
+ 4224              		.loc 2 1745 3 is_stmt 1 view .LVU1450
+1745:Src/main.c    **** 		LD1_curr_setup->I_coef_temp = 0.01;
+ 4225              		.loc 2 1745 31 is_stmt 0 view .LVU1451
+ 4226 01ac 4E4B     		ldr	r3, .L168+28
+ 4227 01ae 7B60     		str	r3, [r7, #4]	@ float
+1746:Src/main.c    **** 	}
+ 4228              		.loc 2 1746 3 is_stmt 1 view .LVU1452
+1746:Src/main.c    **** 	}
+ 4229              		.loc 2 1746 31 is_stmt 0 view .LVU1453
+ 4230 01b0 4E4B     		ldr	r3, .L168+32
+ 4231 01b2 BB60     		str	r3, [r7, #8]	@ float
+ 4232              	.L162:
+1749:Src/main.c    **** 	{
+ 4233              		.loc 2 1749 2 is_stmt 1 view .LVU1454
+1749:Src/main.c    **** 	{
+ 4234              		.loc 2 1749 16 is_stmt 0 view .LVU1455
+ 4235 01b4 637B     		ldrb	r3, [r4, #13]	@ zero_extendqisi2
+1749:Src/main.c    **** 	{
+ 4236              		.loc 2 1749 5 view .LVU1456
+ 4237 01b6 1BB9     		cbnz	r3, .L144
+1751:Src/main.c    **** 		LD2_curr_setup->I_coef_temp = 0.01;
+ 4238              		.loc 2 1751 3 is_stmt 1 view .LVU1457
+1751:Src/main.c    **** 		LD2_curr_setup->I_coef_temp = 0.01;
+ 4239              		.loc 2 1751 31 is_stmt 0 view .LVU1458
+ 4240 01b8 4B4B     		ldr	r3, .L168+28
+ 4241 01ba 7360     		str	r3, [r6, #4]	@ float
+1752:Src/main.c    **** 	}
+ 4242              		.loc 2 1752 3 is_stmt 1 view .LVU1459
+1752:Src/main.c    **** 	}
+ 4243              		.loc 2 1752 31 is_stmt 0 view .LVU1460
+ 4244 01bc 4B4B     		ldr	r3, .L168+32
+ 4245 01be B360     		str	r3, [r6, #8]	@ float
+ 4246              	.L144:
+1754:Src/main.c    **** 
+ 4247              		.loc 2 1754 1 view .LVU1461
+ 4248 01c0 BDE8F883 		pop	{r3, r4, r5, r6, r7, r8, r9, pc}
+ 4249              	.LVL304:
+ 4250              	.L165:
+1605:Src/main.c    **** 	{
+ 4251              		.loc 2 1605 6 discriminator 1 view .LVU1462
+ 4252 01c4 4FF48071 		mov	r1, #256
+ 4253 01c8 4648     		ldr	r0, .L168+24
+ 4254 01ca FFF7FEFF 		bl	HAL_GPIO_ReadPin
+ 4255              	.LVL305:
+1604:Src/main.c    **** 		  (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u
+ 4256              		.loc 2 1604 78 discriminator 1 view .LVU1463
+ 4257 01ce 0128     		cmp	r0, #1
+ 4258 01d0 7FF426AF 		bne	.L145
+1607:Src/main.c    **** 		if (test == 0) //0 - suc
+ 4259              		.loc 2 1607 3 is_stmt 1 view .LVU1464
+1607:Src/main.c    **** 		if (test == 0) //0 - suc
+ 4260              		.loc 2 1607 10 is_stmt 0 view .LVU1465
+ 4261 01d4 4648     		ldr	r0, .L168+36
+ 4262 01d6 FFF7FEFF 		bl	Mount_SD
+ 4263              	.LVL306:
+1607:Src/main.c    **** 		if (test == 0) //0 - suc
+ARM GAS  /tmp/ccdsDELB.s 			page 277
+
+
+ 4264              		.loc 2 1607 8 view .LVU1466
+ 4265 01da 3C4B     		ldr	r3, .L168
+ 4266 01dc 1860     		str	r0, [r3]
+1608:Src/main.c    **** 		{
+ 4267              		.loc 2 1608 3 is_stmt 1 view .LVU1467
+1608:Src/main.c    **** 		{
+ 4268              		.loc 2 1608 6 is_stmt 0 view .LVU1468
+ 4269 01de 0028     		cmp	r0, #0
+ 4270 01e0 7FF41EAF 		bne	.L145
+1611:Src/main.c    **** 			test = Create_File("COMMAND.TXT"); // 0 -succ
+ 4271              		.loc 2 1611 4 is_stmt 1 view .LVU1469
+1611:Src/main.c    **** 			test = Create_File("COMMAND.TXT"); // 0 -succ
+ 4272              		.loc 2 1611 11 is_stmt 0 view .LVU1470
+ 4273 01e4 DFF80C91 		ldr	r9, .L168+40
+ 4274 01e8 4846     		mov	r0, r9
+ 4275 01ea FFF7FEFF 		bl	Remove_File
+ 4276              	.LVL307:
+1611:Src/main.c    **** 			test = Create_File("COMMAND.TXT"); // 0 -succ
+ 4277              		.loc 2 1611 9 view .LVU1471
+ 4278 01ee DFF8DC80 		ldr	r8, .L168
+ 4279 01f2 C8F80000 		str	r0, [r8]
+1612:Src/main.c    **** 			test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8);
+ 4280              		.loc 2 1612 4 is_stmt 1 view .LVU1472
+1612:Src/main.c    **** 			test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8);
+ 4281              		.loc 2 1612 11 is_stmt 0 view .LVU1473
+ 4282 01f6 4846     		mov	r0, r9
+ 4283 01f8 FFF7FEFF 		bl	Create_File
+ 4284              	.LVL308:
+1612:Src/main.c    **** 			test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8);
+ 4285              		.loc 2 1612 9 view .LVU1474
+ 4286 01fc C8F80000 		str	r0, [r8]
+1613:Src/main.c    **** 			test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8);
+ 4287              		.loc 2 1613 4 is_stmt 1 view .LVU1475
+1613:Src/main.c    **** 			test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8);
+ 4288              		.loc 2 1613 11 is_stmt 0 view .LVU1476
+ 4289 0200 1E22     		movs	r2, #30
+ 4290 0202 2946     		mov	r1, r5
+ 4291 0204 4846     		mov	r0, r9
+ 4292 0206 FFF7FEFF 		bl	Write_File_byte
+ 4293              	.LVL309:
+1613:Src/main.c    **** 			test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8);
+ 4294              		.loc 2 1613 9 view .LVU1477
+ 4295 020a C8F80000 		str	r0, [r8]
+1614:Src/main.c    **** 			test = Unmount_SD("/"); // 0 - succ
+ 4296              		.loc 2 1614 4 is_stmt 1 view .LVU1478
+1614:Src/main.c    **** 			test = Unmount_SD("/"); // 0 - succ
+ 4297              		.loc 2 1614 11 is_stmt 0 view .LVU1479
+ 4298 020e 1E22     		movs	r2, #30
+ 4299 0210 2946     		mov	r1, r5
+ 4300 0212 4846     		mov	r0, r9
+ 4301 0214 FFF7FEFF 		bl	Update_File_byte
+ 4302              	.LVL310:
+1614:Src/main.c    **** 			test = Unmount_SD("/"); // 0 - succ
+ 4303              		.loc 2 1614 9 view .LVU1480
+ 4304 0218 C8F80000 		str	r0, [r8]
+1615:Src/main.c    **** 		}
+ 4305              		.loc 2 1615 4 is_stmt 1 view .LVU1481
+ARM GAS  /tmp/ccdsDELB.s 			page 278
+
+
+1615:Src/main.c    **** 		}
+ 4306              		.loc 2 1615 11 is_stmt 0 view .LVU1482
+ 4307 021c 3448     		ldr	r0, .L168+36
+ 4308 021e FFF7FEFF 		bl	Unmount_SD
+ 4309              	.LVL311:
+1615:Src/main.c    **** 		}
+ 4310              		.loc 2 1615 9 view .LVU1483
+ 4311 0222 C8F80000 		str	r0, [r8]
+ 4312 0226 FBE6     		b	.L145
+ 4313              	.LVL312:
+ 4314              	.L146:
+1665:Src/main.c    **** 	}
+ 4315              		.loc 2 1665 3 is_stmt 1 view .LVU1484
+ 4316 0228 0022     		movs	r2, #0
+ 4317 022a 0821     		movs	r1, #8
+ 4318 022c 2B48     		ldr	r0, .L168+16
+ 4319 022e FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4320              	.LVL313:
+ 4321 0232 69E7     		b	.L147
+ 4322              	.L148:
+1674:Src/main.c    **** 	}
+ 4323              		.loc 2 1674 3 view .LVU1485
+ 4324 0234 0022     		movs	r2, #0
+ 4325 0236 0421     		movs	r1, #4
+ 4326 0238 2848     		ldr	r0, .L168+16
+ 4327 023a FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4328              	.LVL314:
+ 4329 023e 6CE7     		b	.L149
+ 4330              	.L150:
+1684:Src/main.c    **** 		//LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC
+ 4331              		.loc 2 1684 3 view .LVU1486
+ 4332 0240 0022     		movs	r2, #0
+ 4333 0242 4FF48071 		mov	r1, #256
+ 4334 0246 2248     		ldr	r0, .L168+4
+ 4335 0248 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4336              	.LVL315:
+ 4337 024c 6FE7     		b	.L151
+ 4338              	.L152:
+1695:Src/main.c    **** 		//LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC
+ 4339              		.loc 2 1695 3 view .LVU1487
+ 4340 024e 0022     		movs	r2, #0
+ 4341 0250 1021     		movs	r1, #16
+ 4342 0252 2248     		ldr	r0, .L168+16
+ 4343 0254 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4344              	.LVL316:
+ 4345 0258 72E7     		b	.L153
+ 4346              	.L154:
+1705:Src/main.c    **** 	}
+ 4347              		.loc 2 1705 3 view .LVU1488
+ 4348 025a 0022     		movs	r2, #0
+ 4349 025c 4FF48061 		mov	r1, #1024
+ 4350 0260 1F48     		ldr	r0, .L168+20
+ 4351 0262 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4352              	.LVL317:
+ 4353 0266 75E7     		b	.L155
+ 4354              	.L156:
+1714:Src/main.c    **** 	}
+ARM GAS  /tmp/ccdsDELB.s 			page 279
+
+
+ 4355              		.loc 2 1714 3 view .LVU1489
+ 4356 0268 0022     		movs	r2, #0
+ 4357 026a 0821     		movs	r1, #8
+ 4358 026c 1D48     		ldr	r0, .L168+24
+ 4359 026e FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4360              	.LVL318:
+ 4361 0272 78E7     		b	.L157
+ 4362              	.L166:
+1719:Src/main.c    **** 		Set_LTEC(3,32767);
+ 4363              		.loc 2 1719 3 view .LVU1490
+ 4364 0274 47F6FF71 		movw	r1, #32767
+ 4365 0278 0320     		movs	r0, #3
+ 4366 027a FFF7FEFF 		bl	Set_LTEC
+ 4367              	.LVL319:
+1720:Src/main.c    **** 		HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET);
+ 4368              		.loc 2 1720 3 view .LVU1491
+ 4369 027e 47F6FF71 		movw	r1, #32767
+ 4370 0282 0320     		movs	r0, #3
+ 4371 0284 FFF7FEFF 		bl	Set_LTEC
+ 4372              	.LVL320:
+1721:Src/main.c    **** 		HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET);
+ 4373              		.loc 2 1721 3 view .LVU1492
+ 4374 0288 0122     		movs	r2, #1
+ 4375 028a 4FF40061 		mov	r1, #2048
+ 4376 028e 1448     		ldr	r0, .L168+20
+ 4377 0290 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4378              	.LVL321:
+1722:Src/main.c    **** 	}
+ 4379              		.loc 2 1722 3 view .LVU1493
+ 4380 0294 0122     		movs	r2, #1
+ 4381 0296 1146     		mov	r1, r2
+ 4382 0298 1248     		ldr	r0, .L168+24
+ 4383 029a FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4384              	.LVL322:
+ 4385 029e 73E7     		b	.L159
+ 4386              	.L167:
+1732:Src/main.c    **** 		Set_LTEC(4,32767);
+ 4387              		.loc 2 1732 3 view .LVU1494
+ 4388 02a0 47F6FF71 		movw	r1, #32767
+ 4389 02a4 0420     		movs	r0, #4
+ 4390 02a6 FFF7FEFF 		bl	Set_LTEC
+ 4391              	.LVL323:
+1733:Src/main.c    **** 		HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET);
+ 4392              		.loc 2 1733 3 view .LVU1495
+ 4393 02aa 47F6FF71 		movw	r1, #32767
+ 4394 02ae 0420     		movs	r0, #4
+ 4395 02b0 FFF7FEFF 		bl	Set_LTEC
+ 4396              	.LVL324:
+1734:Src/main.c    **** 		HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET);
+ 4397              		.loc 2 1734 3 view .LVU1496
+ 4398 02b4 0122     		movs	r2, #1
+ 4399 02b6 2021     		movs	r1, #32
+ 4400 02b8 0848     		ldr	r0, .L168+16
+ 4401 02ba FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4402              	.LVL325:
+1735:Src/main.c    **** 	}
+ 4403              		.loc 2 1735 3 view .LVU1497
+ARM GAS  /tmp/ccdsDELB.s 			page 280
+
+
+ 4404 02be 0122     		movs	r2, #1
+ 4405 02c0 0221     		movs	r1, #2
+ 4406 02c2 0848     		ldr	r0, .L168+24
+ 4407 02c4 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4408              	.LVL326:
+ 4409 02c8 6EE7     		b	.L161
+ 4410              	.L169:
+ 4411 02ca 00BF     		.align	2
+ 4412              	.L168:
+ 4413 02cc 00000000 		.word	.LANCHOR5
+ 4414 02d0 000C0240 		.word	1073875968
+ 4415 02d4 0000803B 		.word	998244352
+ 4416 02d8 00000000 		.word	.LANCHOR6
+ 4417 02dc 00080240 		.word	1073874944
+ 4418 02e0 00040240 		.word	1073873920
+ 4419 02e4 00000240 		.word	1073872896
+ 4420 02e8 00002041 		.word	1092616192
+ 4421 02ec 0AD7233C 		.word	1008981770
+ 4422 02f0 00000000 		.word	.LC0
+ 4423 02f4 04000000 		.word	.LC1
+ 4424              		.cfi_endproc
+ 4425              	.LFE1204:
+ 4427              		.section	.text.Init_params,"ax",%progbits
+ 4428              		.align	1
+ 4429              		.syntax unified
+ 4430              		.thumb
+ 4431              		.thumb_func
+ 4432              		.fpu fpv5-d16
+ 4434              	Init_params:
+ 4435              	.LFB1203:
+1455:Src/main.c    **** 	TO6 = 0;
+ 4436              		.loc 2 1455 1 view -0
+ 4437              		.cfi_startproc
+ 4438              		@ args = 0, pretend = 0, frame = 0
+ 4439              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4440 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 4441              	.LCFI38:
+ 4442              		.cfi_def_cfa_offset 24
+ 4443              		.cfi_offset 4, -24
+ 4444              		.cfi_offset 5, -20
+ 4445              		.cfi_offset 6, -16
+ 4446              		.cfi_offset 7, -12
+ 4447              		.cfi_offset 8, -8
+ 4448              		.cfi_offset 14, -4
+1456:Src/main.c    **** 	TO7 = 0;
+ 4449              		.loc 2 1456 2 view .LVU1499
+1456:Src/main.c    **** 	TO7 = 0;
+ 4450              		.loc 2 1456 6 is_stmt 0 view .LVU1500
+ 4451 0004 0023     		movs	r3, #0
+ 4452 0006 9C4A     		ldr	r2, .L182
+ 4453 0008 1360     		str	r3, [r2]
+1457:Src/main.c    **** 	TO7_before = 0;
+ 4454              		.loc 2 1457 2 is_stmt 1 view .LVU1501
+1457:Src/main.c    **** 	TO7_before = 0;
+ 4455              		.loc 2 1457 6 is_stmt 0 view .LVU1502
+ 4456 000a 9C4A     		ldr	r2, .L182+4
+ 4457 000c 1360     		str	r3, [r2]
+ARM GAS  /tmp/ccdsDELB.s 			page 281
+
+
+1458:Src/main.c    **** 	TO6_before = 0;
+ 4458              		.loc 2 1458 2 is_stmt 1 view .LVU1503
+1458:Src/main.c    **** 	TO6_before = 0;
+ 4459              		.loc 2 1458 13 is_stmt 0 view .LVU1504
+ 4460 000e 9C4A     		ldr	r2, .L182+8
+ 4461 0010 1360     		str	r3, [r2]
+1459:Src/main.c    **** 	TO6_uart = 0;
+ 4462              		.loc 2 1459 2 is_stmt 1 view .LVU1505
+1459:Src/main.c    **** 	TO6_uart = 0;
+ 4463              		.loc 2 1459 13 is_stmt 0 view .LVU1506
+ 4464 0012 9C4A     		ldr	r2, .L182+12
+ 4465 0014 1360     		str	r3, [r2]
+1460:Src/main.c    **** 	flg_tmt = 0;
+ 4466              		.loc 2 1460 2 is_stmt 1 view .LVU1507
+1460:Src/main.c    **** 	flg_tmt = 0;
+ 4467              		.loc 2 1460 11 is_stmt 0 view .LVU1508
+ 4468 0016 9C4A     		ldr	r2, .L182+16
+ 4469 0018 1360     		str	r3, [r2]
+1461:Src/main.c    **** 	UART_rec_incr = 0;
+ 4470              		.loc 2 1461 2 is_stmt 1 view .LVU1509
+1461:Src/main.c    **** 	UART_rec_incr = 0;
+ 4471              		.loc 2 1461 10 is_stmt 0 view .LVU1510
+ 4472 001a 9C4A     		ldr	r2, .L182+20
+ 4473 001c 1370     		strb	r3, [r2]
+1462:Src/main.c    **** 	fgoto = 0;
+ 4474              		.loc 2 1462 2 is_stmt 1 view .LVU1511
+1462:Src/main.c    **** 	fgoto = 0;
+ 4475              		.loc 2 1462 16 is_stmt 0 view .LVU1512
+ 4476 001e 9C4A     		ldr	r2, .L182+24
+ 4477 0020 1380     		strh	r3, [r2]	@ movhi
+1463:Src/main.c    **** 	sizeoffile = 0;
+ 4478              		.loc 2 1463 2 is_stmt 1 view .LVU1513
+1463:Src/main.c    **** 	sizeoffile = 0;
+ 4479              		.loc 2 1463 8 is_stmt 0 view .LVU1514
+ 4480 0022 9C4A     		ldr	r2, .L182+28
+ 4481 0024 1360     		str	r3, [r2]
+1464:Src/main.c    **** 	u_tx_flg = 0;
+ 4482              		.loc 2 1464 2 is_stmt 1 view .LVU1515
+1464:Src/main.c    **** 	u_tx_flg = 0;
+ 4483              		.loc 2 1464 13 is_stmt 0 view .LVU1516
+ 4484 0026 9C4A     		ldr	r2, .L182+32
+ 4485 0028 1360     		str	r3, [r2]
+1465:Src/main.c    **** 	u_rx_flg = 0;
+ 4486              		.loc 2 1465 2 is_stmt 1 view .LVU1517
+1465:Src/main.c    **** 	u_rx_flg = 0;
+ 4487              		.loc 2 1465 11 is_stmt 0 view .LVU1518
+ 4488 002a 9C4A     		ldr	r2, .L182+36
+ 4489 002c 1370     		strb	r3, [r2]
+1466:Src/main.c    **** 	//State_Data[0]=0;
+ 4490              		.loc 2 1466 2 is_stmt 1 view .LVU1519
+1466:Src/main.c    **** 	//State_Data[0]=0;
+ 4491              		.loc 2 1466 11 is_stmt 0 view .LVU1520
+ 4492 002e 9C4A     		ldr	r2, .L182+40
+ 4493 0030 1370     		strb	r3, [r2]
+1469:Src/main.c    **** 	{
+ 4494              		.loc 2 1469 2 is_stmt 1 view .LVU1521
+ 4495              	.LBB456:
+ARM GAS  /tmp/ccdsDELB.s 			page 282
+
+
+1469:Src/main.c    **** 	{
+ 4496              		.loc 2 1469 7 view .LVU1522
+ 4497              	.LVL327:
+1469:Src/main.c    **** 	{
+ 4498              		.loc 2 1469 2 is_stmt 0 view .LVU1523
+ 4499 0032 05E0     		b	.L171
+ 4500              	.LVL328:
+ 4501              	.L172:
+1471:Src/main.c    **** 	}
+ 4502              		.loc 2 1471 3 is_stmt 1 discriminator 3 view .LVU1524
+1471:Src/main.c    **** 	}
+ 4503              		.loc 2 1471 16 is_stmt 0 discriminator 3 view .LVU1525
+ 4504 0034 9B4A     		ldr	r2, .L182+44
+ 4505 0036 0021     		movs	r1, #0
+ 4506 0038 22F81310 		strh	r1, [r2, r3, lsl #1]	@ movhi
+1469:Src/main.c    **** 	{
+ 4507              		.loc 2 1469 30 is_stmt 1 discriminator 3 view .LVU1526
+1469:Src/main.c    **** 	{
+ 4508              		.loc 2 1469 31 is_stmt 0 discriminator 3 view .LVU1527
+ 4509 003c 0133     		adds	r3, r3, #1
+ 4510              	.LVL329:
+1469:Src/main.c    **** 	{
+ 4511              		.loc 2 1469 31 discriminator 3 view .LVU1528
+ 4512 003e 9BB2     		uxth	r3, r3
+ 4513              	.LVL330:
+ 4514              	.L171:
+1469:Src/main.c    **** 	{
+ 4515              		.loc 2 1469 21 is_stmt 1 discriminator 1 view .LVU1529
+1469:Src/main.c    **** 	{
+ 4516              		.loc 2 1469 2 is_stmt 0 discriminator 1 view .LVU1530
+ 4517 0040 0E2B     		cmp	r3, #14
+ 4518 0042 F7D9     		bls	.L172
+ 4519              	.LBE456:
+1473:Src/main.c    **** 	
+ 4520              		.loc 2 1473 2 is_stmt 1 view .LVU1531
+1473:Src/main.c    **** 	
+ 4521              		.loc 2 1473 14 is_stmt 0 view .LVU1532
+ 4522 0044 974B     		ldr	r3, .L182+44
+ 4523              	.LVL331:
+1473:Src/main.c    **** 	
+ 4524              		.loc 2 1473 14 view .LVU1533
+ 4525 0046 41F21112 		movw	r2, #4369
+ 4526 004a 1A80     		strh	r2, [r3]	@ movhi
+1476:Src/main.c    **** 	Def_setup.LD1_EN = 0;
+ 4527              		.loc 2 1476 2 is_stmt 1 view .LVU1534
+1476:Src/main.c    **** 	Def_setup.LD1_EN = 0;
+ 4528              		.loc 2 1476 21 is_stmt 0 view .LVU1535
+ 4529 004c 964B     		ldr	r3, .L182+48
+ 4530 004e 0022     		movs	r2, #0
+ 4531 0050 DA81     		strh	r2, [r3, #14]	@ movhi
+1477:Src/main.c    **** 	Def_setup.LD2_EN = 0;
+ 4532              		.loc 2 1477 2 is_stmt 1 view .LVU1536
+1477:Src/main.c    **** 	Def_setup.LD2_EN = 0;
+ 4533              		.loc 2 1477 19 is_stmt 0 view .LVU1537
+ 4534 0052 DA70     		strb	r2, [r3, #3]
+1478:Src/main.c    **** 	Def_setup.MES_ID = 0;
+ 4535              		.loc 2 1478 2 is_stmt 1 view .LVU1538
+ARM GAS  /tmp/ccdsDELB.s 			page 283
+
+
+1478:Src/main.c    **** 	Def_setup.MES_ID = 0;
+ 4536              		.loc 2 1478 19 is_stmt 0 view .LVU1539
+ 4537 0054 1A71     		strb	r2, [r3, #4]
+1479:Src/main.c    **** 	Def_setup.PI1_RD = 0;
+ 4538              		.loc 2 1479 2 is_stmt 1 view .LVU1540
+1479:Src/main.c    **** 	Def_setup.PI1_RD = 0;
+ 4539              		.loc 2 1479 19 is_stmt 0 view .LVU1541
+ 4540 0056 1A82     		strh	r2, [r3, #16]	@ movhi
+1480:Src/main.c    **** 	Def_setup.PI2_RD = 0;
+ 4541              		.loc 2 1480 2 is_stmt 1 view .LVU1542
+1480:Src/main.c    **** 	Def_setup.PI2_RD = 0;
+ 4542              		.loc 2 1480 19 is_stmt 0 view .LVU1543
+ 4543 0058 1A73     		strb	r2, [r3, #12]
+1481:Src/main.c    **** 	Def_setup.REF1_EN = 0;
+ 4544              		.loc 2 1481 2 is_stmt 1 view .LVU1544
+1481:Src/main.c    **** 	Def_setup.REF1_EN = 0;
+ 4545              		.loc 2 1481 19 is_stmt 0 view .LVU1545
+ 4546 005a 5A73     		strb	r2, [r3, #13]
+1482:Src/main.c    **** 	Def_setup.REF2_EN = 0;
+ 4547              		.loc 2 1482 2 is_stmt 1 view .LVU1546
+1482:Src/main.c    **** 	Def_setup.REF2_EN = 0;
+ 4548              		.loc 2 1482 20 is_stmt 0 view .LVU1547
+ 4549 005c 5A71     		strb	r2, [r3, #5]
+1483:Src/main.c    **** 	Def_setup.SD_EN = 0;
+ 4550              		.loc 2 1483 2 is_stmt 1 view .LVU1548
+1483:Src/main.c    **** 	Def_setup.SD_EN = 0;
+ 4551              		.loc 2 1483 20 is_stmt 0 view .LVU1549
+ 4552 005e 9A71     		strb	r2, [r3, #6]
+1484:Src/main.c    **** 	Def_setup.TEC1_EN = 0;
+ 4553              		.loc 2 1484 2 is_stmt 1 view .LVU1550
+1484:Src/main.c    **** 	Def_setup.TEC1_EN = 0;
+ 4554              		.loc 2 1484 18 is_stmt 0 view .LVU1551
+ 4555 0060 DA72     		strb	r2, [r3, #11]
+1485:Src/main.c    **** 	Def_setup.TEC2_EN = 0;
+ 4556              		.loc 2 1485 2 is_stmt 1 view .LVU1552
+1485:Src/main.c    **** 	Def_setup.TEC2_EN = 0;
+ 4557              		.loc 2 1485 20 is_stmt 0 view .LVU1553
+ 4558 0062 DA71     		strb	r2, [r3, #7]
+1486:Src/main.c    **** 	Def_setup.TS1_EN = 0;
+ 4559              		.loc 2 1486 2 is_stmt 1 view .LVU1554
+1486:Src/main.c    **** 	Def_setup.TS1_EN = 0;
+ 4560              		.loc 2 1486 20 is_stmt 0 view .LVU1555
+ 4561 0064 1A72     		strb	r2, [r3, #8]
+1487:Src/main.c    **** 	Def_setup.TS2_EN = 0;
+ 4562              		.loc 2 1487 2 is_stmt 1 view .LVU1556
+1487:Src/main.c    **** 	Def_setup.TS2_EN = 0;
+ 4563              		.loc 2 1487 19 is_stmt 0 view .LVU1557
+ 4564 0066 5A72     		strb	r2, [r3, #9]
+1488:Src/main.c    **** 	Def_setup.U5V1_EN = 0;
+ 4565              		.loc 2 1488 2 is_stmt 1 view .LVU1558
+1488:Src/main.c    **** 	Def_setup.U5V1_EN = 0;
+ 4566              		.loc 2 1488 19 is_stmt 0 view .LVU1559
+ 4567 0068 9A72     		strb	r2, [r3, #10]
+1489:Src/main.c    **** 	Def_setup.U5V2_EN = 0;
+ 4568              		.loc 2 1489 2 is_stmt 1 view .LVU1560
+1489:Src/main.c    **** 	Def_setup.U5V2_EN = 0;
+ 4569              		.loc 2 1489 20 is_stmt 0 view .LVU1561
+ARM GAS  /tmp/ccdsDELB.s 			page 284
+
+
+ 4570 006a 5A70     		strb	r2, [r3, #1]
+1490:Src/main.c    **** 	Def_setup.WORK_EN = 0;
+ 4571              		.loc 2 1490 2 is_stmt 1 view .LVU1562
+1490:Src/main.c    **** 	Def_setup.WORK_EN = 0;
+ 4572              		.loc 2 1490 20 is_stmt 0 view .LVU1563
+ 4573 006c 9A70     		strb	r2, [r3, #2]
+1491:Src/main.c    **** 	
+ 4574              		.loc 2 1491 2 is_stmt 1 view .LVU1564
+1491:Src/main.c    **** 	
+ 4575              		.loc 2 1491 20 is_stmt 0 view .LVU1565
+ 4576 006e 1A70     		strb	r2, [r3]
+1493:Src/main.c    **** 	LD2_def_setup.LD_TEMP = 0;
+ 4577              		.loc 2 1493 2 is_stmt 1 view .LVU1566
+1493:Src/main.c    **** 	LD2_def_setup.LD_TEMP = 0;
+ 4578              		.loc 2 1493 24 is_stmt 0 view .LVU1567
+ 4579 0070 8E4D     		ldr	r5, .L182+52
+ 4580 0072 2A80     		strh	r2, [r5]	@ movhi
+1494:Src/main.c    **** 	LD1_def_setup.P_coef_temp = 0;
+ 4581              		.loc 2 1494 2 is_stmt 1 view .LVU1568
+1494:Src/main.c    **** 	LD1_def_setup.P_coef_temp = 0;
+ 4582              		.loc 2 1494 24 is_stmt 0 view .LVU1569
+ 4583 0074 8E4C     		ldr	r4, .L182+56
+ 4584 0076 2280     		strh	r2, [r4]	@ movhi
+1495:Src/main.c    **** 	LD2_def_setup.P_coef_temp = 0;
+ 4585              		.loc 2 1495 2 is_stmt 1 view .LVU1570
+1495:Src/main.c    **** 	LD2_def_setup.P_coef_temp = 0;
+ 4586              		.loc 2 1495 28 is_stmt 0 view .LVU1571
+ 4587 0078 0022     		movs	r2, #0
+ 4588 007a 6A60     		str	r2, [r5, #4]	@ float
+1496:Src/main.c    **** 	LD1_def_setup.I_coef_temp = 0;
+ 4589              		.loc 2 1496 2 is_stmt 1 view .LVU1572
+1496:Src/main.c    **** 	LD1_def_setup.I_coef_temp = 0;
+ 4590              		.loc 2 1496 28 is_stmt 0 view .LVU1573
+ 4591 007c 6260     		str	r2, [r4, #4]	@ float
+1497:Src/main.c    **** 	LD2_def_setup.I_coef_temp = 0;
+ 4592              		.loc 2 1497 2 is_stmt 1 view .LVU1574
+1497:Src/main.c    **** 	LD2_def_setup.I_coef_temp = 0;
+ 4593              		.loc 2 1497 28 is_stmt 0 view .LVU1575
+ 4594 007e AA60     		str	r2, [r5, #8]	@ float
+1498:Src/main.c    **** 	
+ 4595              		.loc 2 1498 2 is_stmt 1 view .LVU1576
+1498:Src/main.c    **** 	
+ 4596              		.loc 2 1498 28 is_stmt 0 view .LVU1577
+ 4597 0080 A260     		str	r2, [r4, #8]	@ float
+1501:Src/main.c    **** 	LD1_curr_setup = LD1_def_setup;
+ 4598              		.loc 2 1501 2 is_stmt 1 view .LVU1578
+1501:Src/main.c    **** 	LD1_curr_setup = LD1_def_setup;
+ 4599              		.loc 2 1501 13 is_stmt 0 view .LVU1579
+ 4600 0082 8C4E     		ldr	r6, .L182+60
+ 4601 0084 9C46     		mov	ip, r3
+ 4602 0086 BCE80F00 		ldmia	ip!, {r0, r1, r2, r3}
+ 4603 008a 0FC6     		stmia	r6!, {r0, r1, r2, r3}
+ 4604 008c DCF80030 		ldr	r3, [ip]
+ 4605 0090 3380     		strh	r3, [r6]	@ movhi
+1502:Src/main.c    **** 	LD2_curr_setup = LD2_def_setup;
+ 4606              		.loc 2 1502 2 is_stmt 1 view .LVU1580
+1502:Src/main.c    **** 	LD2_curr_setup = LD2_def_setup;
+ARM GAS  /tmp/ccdsDELB.s 			page 285
+
+
+ 4607              		.loc 2 1502 17 is_stmt 0 view .LVU1581
+ 4608 0092 894E     		ldr	r6, .L182+64
+ 4609 0094 95E80F00 		ldm	r5, {r0, r1, r2, r3}
+ 4610 0098 86E80F00 		stm	r6, {r0, r1, r2, r3}
+1503:Src/main.c    **** 	
+ 4611              		.loc 2 1503 2 is_stmt 1 view .LVU1582
+1503:Src/main.c    **** 	
+ 4612              		.loc 2 1503 17 is_stmt 0 view .LVU1583
+ 4613 009c 874D     		ldr	r5, .L182+68
+ 4614 009e 94E80F00 		ldm	r4, {r0, r1, r2, r3}
+ 4615 00a2 85E80F00 		stm	r5, {r0, r1, r2, r3}
+1508:Src/main.c    **** 	LL_TIM_EnableCounter(TIM6);
+ 4616              		.loc 2 1508 2 is_stmt 1 view .LVU1584
+ 4617              	.LVL332:
+ 4618              	.LBB457:
+ 4619              	.LBI457:
+3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief Indicates whether the Master/Slave mode is enabled.
+3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * a timer instance can operate as a slave timer.
+3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
+3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure the external trigger (ETR) input.
+3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides an external trigger input.
+3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         SMCR         ETPS          LL_TIM_ConfigETR\n
+3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         SMCR         ETF           LL_TIM_ConfigETR
+3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ETRPolarity This parameter can be one of the following values:
+3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ETRPrescaler This parameter can be one of the following values:
+3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ETRFilter This parameter can be one of the following values:
+3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+ARM GAS  /tmp/ccdsDELB.s 			page 286
+
+
+3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale
+3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       uint32_t ETRFilter)
+3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | 
+3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Break_Function Break function configuration
+3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the break function.
+3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the break function.
+3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure the break input.
+3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         BDTR         BKF           LL_TIM_ConfigBRK
+3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakPolarity This parameter can be one of the following values:
+3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+ARM GAS  /tmp/ccdsDELB.s 			page 287
+
+
+3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakFilter This parameter can be one of the following values:
+3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
+3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       uint32_t BreakFilter)
+3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
+3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the break 2 function.
+3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a second break input.
+3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
+3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the break  2 function.
+3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a second break input.
+3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
+3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure the break 2 input.
+3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a second break input.
+3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+ARM GAS  /tmp/ccdsDELB.s 			page 288
+
+
+3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         BDTR         BK2F          LL_TIM_ConfigBRK2
+3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Break2Polarity This parameter can be one of the following values:
+3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Break2Filter This parameter can be one of the following values:
+3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2F
+3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
+3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         BDTR         OSSR          LL_TIM_SetOffStates
+3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  OffStateIdle This parameter can be one of the following values:
+3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSI_DISABLE
+3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSI_ENABLE
+3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  OffStateRun This parameter can be one of the following values:
+3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSR_DISABLE
+3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSR_ENABLE
+3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat
+3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input
+3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 289
+
+
+3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable automatic output (MOE can be set only by software).
+3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether automatic output is enabled.
+3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
+3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       software and is reset in case of break or break2 event
+3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       software and is reset in case of break or break2 event.
+3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+ARM GAS  /tmp/ccdsDELB.s 			page 290
+
+
+3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether outputs are enabled.
+3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
+3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT)
+3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the signals connected to the designated timer break input.
+3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance allows for break input selection.
+3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll AF1          BKINE          LL_TIM_EnableBreakInputSource\n
+3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF1          BKDFBKE        LL_TIM_EnableBreakInputSource\n
+3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2INE         LL_TIM_EnableBreakInputSource\n
+3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2DFBKE       LL_TIM_EnableBreakInputSource
+3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakInput This parameter can be one of the following values:
+3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Source This parameter can be one of the following values:
+3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t
+3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, Source);
+3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the signals connected to the designated timer break input.
+3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance allows for break input selection.
+3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll AF1          BKINE          LL_TIM_DisableBreakInputSource\n
+3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF1          BKDFBKE        LL_TIM_DisableBreakInputSource\n
+3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2INE         LL_TIM_DisableBreakInputSource\n
+3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2DFBKE       LL_TIM_DisableBreakInputSource
+3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakInput This parameter can be one of the following values:
+3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Source This parameter can be one of the following values:
+3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+ARM GAS  /tmp/ccdsDELB.s 			page 291
+
+
+3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_
+3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, Source);
+3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the polarity of the break signal for the timer break input.
+3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance allows for break input selection.
+3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll AF1          BKINP          LL_TIM_SetBreakInputSourcePolarity\n
+3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF1          BKDFBKP        LL_TIM_SetBreakInputSourcePolarity\n
+3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2INP         LL_TIM_SetBreakInputSourcePolarity\n
+3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2DFBKP       LL_TIM_SetBreakInputSourcePolarity
+3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakInput This parameter can be one of the following values:
+3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Source This parameter can be one of the following values:
+3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Polarity This parameter can be one of the following values:
+3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
+3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uin
+3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                         uint32_t Polarity)
+3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOUR
+3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */
+3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configures the timer DMA burst feature.
+3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       not a timer instance supports the DMA burst mode.
+3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         DCR          DBA           LL_TIM_ConfigDMABurst
+3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DMABurstBaseAddress This parameter can be one of the following values:
+3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+ARM GAS  /tmp/ccdsDELB.s 			page 292
+
+
+3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR
+3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1  (*)
+3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2  (*)
+3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (*) value not defined in all devices
+3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DMABurstLength This parameter can be one of the following values:
+3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_
+3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
+3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Remap TIM inputs (input channel, internal/external triggers).
+3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a some timer inputs can be remapped.
+3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll TIM2_OR     ITR1_RMP          LL_TIM_SetRemap\n
+3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM5_OR     TI4_RMP           LL_TIM_SetRemap\n
+3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM11_OR    TI1_RMP           LL_TIM_SetRemap
+ARM GAS  /tmp/ccdsDELB.s 			page 293
+
+
+3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Remap Remap param depends on the TIMx. Description available only
+3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         in CHM version of the User Manual (not in .pdf).
+3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         Otherwise see Reference Manual description of OR registers.
+3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         Below description summarizes "Timer Instance" and "Remap" param combinations:
+3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM2: one of the following values
+3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            ITR1_RMP can be one of the following values
+3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
+3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP
+3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
+3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
+3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM5: one of the following values
+3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
+3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
+3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
+3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
+3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM11: one of the following values
+3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
+3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX
+3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_HSE
+3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1
+3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the update interrupt flag (UIF).
+3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+ARM GAS  /tmp/ccdsDELB.s 			page 294
+
+
+3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
+3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 inte
+3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
+3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 inte
+3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
+3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+ARM GAS  /tmp/ccdsDELB.s 			page 295
+
+
+3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 inte
+3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
+3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 inte
+3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
+3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
+3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
+3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 inte
+3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
+3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
+ARM GAS  /tmp/ccdsDELB.s 			page 296
+
+
+3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
+3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
+3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
+3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 inte
+3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
+3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
+3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
+3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the commutation interrupt flag (COMIF).
+3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
+3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pe
+3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
+3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
+3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the trigger interrupt flag (TIF).
+3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+ARM GAS  /tmp/ccdsDELB.s 			page 297
+
+
+3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
+3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the break interrupt flag (BIF).
+3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
+3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
+3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
+3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the break 2 interrupt flag (B2IF).
+3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
+3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
+3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
+3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
+3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 298
+
+
+3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (Capture/Compare 1 interrupt is pending).
+3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
+3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (Capture/Compare 2 over-capture interrupt is pending).
+4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
+4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 299
+
+
+4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (Capture/Compare 3 over-capture interrupt is pending).
+4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
+4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (Capture/Compare 4 over-capture interrupt is pending).
+4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
+4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the system break interrupt flag (SBIF).
+4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
+4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
+4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is p
+4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
+4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
+4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
+4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 300
+
+
+4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_IT_Management IT-Management
+4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable update interrupt (UIE).
+4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+ 4620              		.loc 5 4090 22 view .LVU1585
+ 4621              	.LBB458:
+4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+ 4622              		.loc 5 4092 3 view .LVU1586
+ 4623 00a6 864B     		ldr	r3, .L182+72
+ 4624 00a8 DA68     		ldr	r2, [r3, #12]
+ 4625 00aa 42F00102 		orr	r2, r2, #1
+ 4626 00ae DA60     		str	r2, [r3, #12]
+ 4627              	.LVL333:
+ 4628              		.loc 5 4092 3 is_stmt 0 view .LVU1587
+ 4629              	.LBE458:
+ 4630              	.LBE457:
+1509:Src/main.c    **** 	LL_TIM_EnableIT_UPDATE(TIM7);
+ 4631              		.loc 2 1509 2 is_stmt 1 view .LVU1588
+ 4632              	.LBB459:
+ 4633              	.LBI459:
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 4634              		.loc 5 1313 22 view .LVU1589
+ 4635              	.LBB460:
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 4636              		.loc 5 1315 3 view .LVU1590
+ 4637 00b0 1A68     		ldr	r2, [r3]
+ 4638 00b2 42F00102 		orr	r2, r2, #1
+ 4639 00b6 1A60     		str	r2, [r3]
+ 4640              	.LVL334:
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 4641              		.loc 5 1315 3 is_stmt 0 view .LVU1591
+ 4642              	.LBE460:
+ 4643              	.LBE459:
+1510:Src/main.c    **** 	LL_TIM_EnableCounter(TIM7);
+ 4644              		.loc 2 1510 2 is_stmt 1 view .LVU1592
+ 4645              	.LBB461:
+ 4646              	.LBI461:
+4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 4647              		.loc 5 4090 22 view .LVU1593
+ 4648              	.LBB462:
+ 4649              		.loc 5 4092 3 view .LVU1594
+ 4650 00b8 03F58063 		add	r3, r3, #1024
+ 4651 00bc DA68     		ldr	r2, [r3, #12]
+ 4652 00be 42F00102 		orr	r2, r2, #1
+ 4653 00c2 DA60     		str	r2, [r3, #12]
+ 4654              	.LVL335:
+ARM GAS  /tmp/ccdsDELB.s 			page 301
+
+
+ 4655              		.loc 5 4092 3 is_stmt 0 view .LVU1595
+ 4656              	.LBE462:
+ 4657              	.LBE461:
+1511:Src/main.c    **** 	//HAL_TIM_Base_Start_IT(&htim6);
+ 4658              		.loc 2 1511 2 is_stmt 1 view .LVU1596
+ 4659              	.LBB463:
+ 4660              	.LBI463:
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 4661              		.loc 5 1313 22 view .LVU1597
+ 4662              	.LBB464:
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 4663              		.loc 5 1315 3 view .LVU1598
+ 4664 00c4 1A68     		ldr	r2, [r3]
+ 4665 00c6 42F00102 		orr	r2, r2, #1
+ 4666 00ca 1A60     		str	r2, [r3]
+ 4667              	.LVL336:
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 4668              		.loc 5 1315 3 is_stmt 0 view .LVU1599
+ 4669              	.LBE464:
+ 4670              	.LBE463:
+1518:Src/main.c    ****   LL_DMA_ClearFlag_TC7(DMA2);
+ 4671              		.loc 2 1518 3 is_stmt 1 view .LVU1600
+ 4672              	.LBB465:
+ 4673              	.LBI465:
+ 4674              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @file    stm32f7xx_ll_dma.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief   Header file of DMA LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * This software is licensed under terms that can be found in the LICENSE file in
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifndef __STM32F7xx_LL_DMA_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __STM32F7xx_LL_DMA_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 302
+
+
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined (DMA1) || defined (DMA2)
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL DMA
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** static const uint8_t STREAM_OFFSET_TAB[] =
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** };
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Constants DMA Private Constants
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_SxCR_CHSEL_3)
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define DMA_CHANNEL_SELECTION_8_15
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_SxCR_CHSEL_3 */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER)
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** typedef struct
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         or as Source base address in case of memory to memory trans
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter must be a value between Min_Data = 0 and Max
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         or as Destination base address in case of memory to memory 
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 303
+
+
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter must be a value between Min_Data = 0 and Max
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to pe
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         from memory to memory or from peripheral to memory.
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MODE
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The circular buffer mode cannot be used if the memory
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                               data transfer direction is configured on the selected
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address 
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         is incremented or not.
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PERIPH
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         is incremented or not.
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MEMORY
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         in case of memory to memory transfer direction.
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         in case of memory to memory transfer direction.
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         The data unit is equal to the source buffer configuration s
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         or MemorySize parameters depending in the transfer directio
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter must be a value between Min_Data = 0 and Max
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Channel;                /*!< Specifies the peripheral channel.
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_CHANNEL
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Priority;               /*!< Specifies the channel priority level.
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for 
+ARM GAS  /tmp/ccdsDELB.s 			page 304
+
+
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_FIFOMODE
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The Direct mode (FIFO mode disabled) cannot be used i
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         memory-to-memory data transfer is configured on the selecte
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHO
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory t
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         It specifies the amount of data to be transferred in a sing
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         transaction.
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MBURST 
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The burst mode is possible only if the address Increm
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripher
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         It specifies the amount of data to be transferred in a sing
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         transaction. 
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PBURST
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The burst mode is possible only if the address Increm
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } LL_DMA_InitTypeDef;
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_STREAM STREAM
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_0                   0x00000000U
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_1                   0x00000001U
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_2                   0x00000002U
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_3                   0x00000003U
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_4                   0x00000004U
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_5                   0x00000005U
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_6                   0x00000006U
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_7                   0x00000007U
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_ALL                 0xFFFF0000U
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direc
+ARM GAS  /tmp/ccdsDELB.s 			page 305
+
+
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direc
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE MODE
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode               
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode             
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mo
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering m
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mo
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH PERIPH
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode 
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode 
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY MEMORY
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disa
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enab
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment 
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment 
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment 
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : By
+ARM GAS  /tmp/ccdsDELB.s 			page 306
+
+
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : Ha
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Wo
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offse
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offse
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low      
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium   
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High     
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_0                  0x00000000U                                              
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_1                  DMA_SxCR_CHSEL_0                                         
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_2                  DMA_SxCR_CHSEL_1                                         
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_3                  (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1)                    
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_4                  DMA_SxCR_CHSEL_2                                         
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_5                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)                    
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_6                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)                    
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_7                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_CHANNEL_SELECTION_8_15)
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_8                  DMA_SxCR_CHSEL_3                                         
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_9                  (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0)                    
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_10                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1)                    
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_11                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_12                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2)                    
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_13                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) 
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_14                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) 
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_15                 DMA_SxCR_CHSEL                                           
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_CHANNEL_SELECTION_8_15 */
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MBURST MBURST
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst
+ARM GAS  /tmp/ccdsDELB.s 			page 307
+
+
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PBURST PBURST
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral b
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral b
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral b
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral b
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode di
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode en
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */  
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_lev
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_l
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_l
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_l
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empt
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO thresho
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO thresho
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO thresho
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO thresho
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentT
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentT
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 308
+
+
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Write a value in DMA register
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __INSTANCE__ DMA Instance
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __REG__ Register to be written
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __VALUE__ Value to be written in the register
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Read a value in DMA register
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __INSTANCE__ DMA Instance
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __REG__ Register to be read
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Register value
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Convert DMAx_Streamy into DMAx
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __STREAM_INSTANCE__ DMAx_Streamy
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval DMAx
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __STREAM_INSTANCE__ DMAx_Streamy
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval LL_DMA_CHANNEL_y
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
+ARM GAS  /tmp/ccdsDELB.s 			page 309
+
+
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  LL_DMA_STREAM_7)
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __DMA_INSTANCE__ DMAx
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __STREAM__ LL_DMA_STREAM_y
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval DMAx_Streamy
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  DMA2_Stream7)
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable DMA stream.
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          EN            LL_DMA_EnableStream
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ARM GAS  /tmp/ccdsDELB.s 			page 310
+
+
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Disable DMA stream.
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          EN            LL_DMA_DisableStream
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+ 4675              		.loc 6 517 22 view .LVU1601
+ 4676              	.LBB466:
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 4677              		.loc 6 519 3 view .LVU1602
+ 4678 00cc 03F51433 		add	r3, r3, #151552
+ 4679 00d0 D3F8B820 		ldr	r2, [r3, #184]
+ 4680 00d4 22F00102 		bic	r2, r2, #1
+ 4681 00d8 C3F8B820 		str	r2, [r3, #184]
+ 4682              	.LVL337:
+ 4683              		.loc 6 519 3 is_stmt 0 view .LVU1603
+ 4684              	.LBE466:
+ 4685              	.LBE465:
+1519:Src/main.c    ****   LL_DMA_ClearFlag_TE7(DMA2);
+ 4686              		.loc 2 1519 3 is_stmt 1 view .LVU1604
+ 4687              	.LBB467:
+ 4688              	.LBI467:
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Check if DMA stream is enabled or disabled.
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          EN            LL_DMA_IsEnabledStream
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ARM GAS  /tmp/ccdsDELB.s 			page 311
+
+
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Configure all parameters linked to DMA transfer.
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          CIRC          LL_DMA_ConfigTransfer\n
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PINC          LL_DMA_ConfigTransfer\n
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          MINC          LL_DMA_ConfigTransfer\n
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PSIZE         LL_DMA_ConfigTransfer\n
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          MSIZE         LL_DMA_ConfigTransfer\n
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PL            LL_DMA_ConfigTransfer\n
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PFCTRL        LL_DMA_ConfigTransfer
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Configuration This parameter must be a combination of all the following values:
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *@retval None
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configurati
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****              DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****              Configuration);
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Data transfer direction (read from peripheral or from memory).
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ARM GAS  /tmp/ccdsDELB.s 			page 312
+
+
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Direction This parameter can be one of the following values:
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Data transfer direction (read from peripheral or from memory).
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set DMA mode normal, circular or peripheral flow control.
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CIRC           LL_DMA_SetMode\n
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PFCTRL         LL_DMA_SetMode
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Mode This parameter can be one of the following values:
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_NORMAL
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_CIRCULAR
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_PFCTRL
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ARM GAS  /tmp/ccdsDELB.s 			page 313
+
+
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get DMA mode normal, circular or peripheral flow control.
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CIRC           LL_DMA_GetMode\n
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PFCTRL         LL_DMA_GetMode
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_NORMAL
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_CIRCULAR
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_PFCTRL
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Peripheral increment mode.
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  IncrementMode This parameter can be one of the following values:
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_INCREMENT
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral increment mode.
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ARM GAS  /tmp/ccdsDELB.s 			page 314
+
+
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_INCREMENT
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Memory increment mode.
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  IncrementMode This parameter can be one of the following values:
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_INCREMENT
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Memory increment mode.
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_INCREMENT
+ARM GAS  /tmp/ccdsDELB.s 			page 315
+
+
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Peripheral size.
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Size This parameter can be one of the following values:
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_WORD
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral size.
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_WORD
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Memory size.
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ARM GAS  /tmp/ccdsDELB.s 			page 316
+
+
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Size This parameter can be one of the following values:
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_WORD
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Memory size.
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_WORD
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Peripheral increment offset size.
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  OffsetSize This parameter can be one of the following values:
+ARM GAS  /tmp/ccdsDELB.s 			page 317
+
+
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSiz
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral increment offset size.
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Stream priority level.
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Priority This parameter can be one of the following values:
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_LOW
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_HIGH
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Pr
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 318
+
+
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream priority level.
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_LOW
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_HIGH
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Number of data to transfer.
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This action has no effect if
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         stream is enabled.
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  NbData Between 0 to 0xFFFFFFFF
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR,
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Number of data to transfer.
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Once the stream is enabled, the return value indicate the
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         remaining bytes to be transmitted.
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ARM GAS  /tmp/ccdsDELB.s 			page 319
+
+
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Select Channel number associated to the Stream.
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CHSEL           LL_DMA_SetChannelSelection
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Channel This parameter can be one of the following values:
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_0
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_1
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_2
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_3
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_4
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_5
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_6
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_7
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_8 (*)
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_9 (*)
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_10 (*)
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_11 (*)
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_12 (*)
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_13 (*)
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_14 (*)
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_15 (*)
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         (*) value not defined in all devices.
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channe
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get the Channel number associated to the Stream.
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CHSEL           LL_DMA_GetChannelSelection
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ARM GAS  /tmp/ccdsDELB.s 			page 320
+
+
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_0
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_1
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_2
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_3
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_4
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_5
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_6
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_7
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_8 (*)
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_9 (*)
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_10 (*)
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_11 (*)
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_12 (*)
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_13 (*)
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_14 (*)
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_15 (*)
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         (*) value not defined in all devices.
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Memory burst transfer configuration.
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Mburst This parameter can be one of the following values:
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_SINGLE
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC4
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC8
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC16
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 321
+
+
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Memory burst transfer configuration.
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_SINGLE
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC4
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC8
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC16
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set  Peripheral burst transfer configuration.
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Pburst This parameter can be one of the following values:
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_SINGLE
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC4
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC8
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC16
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral burst transfer configuration.
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ARM GAS  /tmp/ccdsDELB.s 			page 322
+
+
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_SINGLE
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC4
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC8
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC16
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem 
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param CurrentMemory This parameter can be one of the following values:
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Curren
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****    MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem 
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 323
+
+
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable the double buffer mode.
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Disable the double buffer mode.
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode 
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get FIFO status.
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ARM GAS  /tmp/ccdsDELB.s 			page 324
+
+
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_0_25
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_25_50
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_50_75
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_75_100
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_FULL
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Disable Fifo mode.
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable Fifo mode.
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode 
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DM
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Select FIFO threshold.
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ARM GAS  /tmp/ccdsDELB.s 			page 325
+
+
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Threshold This parameter can be one of the following values:
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get FIFO threshold.
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Configure the FIFO .
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         FCR         DMDIS        LL_DMA_ConfigFifo
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ARM GAS  /tmp/ccdsDELB.s 			page 326
+
+
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  FifoMode This parameter can be one of the following values:
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOMODE_ENABLE
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOMODE_DISABLE
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  FifoThreshold This parameter can be one of the following values:
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint3
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Configure the Source and Destination addresses.
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA stream is enabled.
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n 
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         PAR         PA          LL_DMA_ConfigAddresses
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  SrcAddress Between 0 to 0xFFFFFFFF
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DstAddress Between 0 to 0xFFFFFFFF
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Direction This parameter can be one of the following values:
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   /* Direction Memory to Periph */
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR,
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   /* Direction Periph to Memory and Memory to Memory */
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   else
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR,
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Set the Memory address.
+ARM GAS  /tmp/ccdsDELB.s 			page 327
+
+
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA channel is enabled.
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, 
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Set the Peripheral address.
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA channel is enabled.
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  PeriphAddress Between 0 to 0xFFFFFFFF
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAdd
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, P
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Get the Memory address.
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ARM GAS  /tmp/ccdsDELB.s 			page 328
+
+
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Get the Peripheral address.
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Set the Memory to Memory Source address.
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA channel is enabled.
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, M
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Set the Memory to Memory Destination address.
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA channel is enabled.
+ARM GAS  /tmp/ccdsDELB.s 			page 329
+
+
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Get the Memory to Memory Source address.
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****    return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream]))
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Get the Memory to Memory Destination address.
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 330
+
+
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Memory 1 address (used in case of Double buffer mode).
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Address Between 0 to 0xFFFFFFFF
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR,
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Memory 1 address (used in case of Double buffer mode).
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 0 half transfer flag.
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+ARM GAS  /tmp/ccdsDELB.s 			page 331
+
+
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 1 half transfer flag.
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 2 half transfer flag.
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 3 half transfer flag.
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 4 half transfer flag.
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 5 half transfer flag.
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+ARM GAS  /tmp/ccdsDELB.s 			page 332
+
+
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 6 half transfer flag.
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 7 half transfer flag.
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 0 transfer complete flag.
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 1 transfer complete flag.
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 2 transfer complete flag.
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
+ARM GAS  /tmp/ccdsDELB.s 			page 333
+
+
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 3 transfer complete flag.
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 4 transfer complete flag.
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 5 transfer complete flag.
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 6 transfer complete flag.
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
+1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 7 transfer complete flag.
+1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7
+1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
+1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 334
+
+
+1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 0 transfer error flag.
+1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0
+1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
+1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
+1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 1 transfer error flag.
+1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1
+1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
+1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 2 transfer error flag.
+1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2
+1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
+1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 3 transfer error flag.
+1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3
+1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
+1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 4 transfer error flag.
+1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4
+1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
+1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 5 transfer error flag.
+ARM GAS  /tmp/ccdsDELB.s 			page 335
+
+
+1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5
+1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
+1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 6 transfer error flag.
+1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6
+1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
+1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 7 transfer error flag.
+1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7
+1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
+1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 0 direct mode error flag.
+1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0
+1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
+1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
+1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 1 direct mode error flag.
+1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1
+1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
+1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
+1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 2 direct mode error flag.
+1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2
+1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ARM GAS  /tmp/ccdsDELB.s 			page 336
+
+
+1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
+1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
+1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 3 direct mode error flag.
+1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3
+1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
+1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
+1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 4 direct mode error flag.
+1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4
+1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
+1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
+1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 5 direct mode error flag.
+1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5
+1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 6 direct mode error flag.
+1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6
+1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
+2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
+2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 7 direct mode error flag.
+2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7
+2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 337
+
+
+2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
+2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
+2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 0 FIFO error flag.
+2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0
+2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
+2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
+2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 1 FIFO error flag.
+2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
+2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
+2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 2 FIFO error flag.
+2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2
+2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
+2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
+2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 3 FIFO error flag.
+2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3
+2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
+2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
+2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 4 FIFO error flag.
+2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4
+2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
+2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 338
+
+
+2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
+2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 5 FIFO error flag.
+2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5
+2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
+2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
+2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 6 FIFO error flag.
+2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6
+2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
+2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
+2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 7 FIFO error flag.
+2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7
+2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
+2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
+2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 0 half transfer flag.
+2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0
+2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
+2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
+2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 1 half transfer flag.
+2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1
+2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
+2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 339
+
+
+2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 2 half transfer flag.
+2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2
+2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
+2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 3 half transfer flag.
+2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3
+2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
+2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 4 half transfer flag.
+2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4
+2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
+2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 5 half transfer flag.
+2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5
+2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
+2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 6 half transfer flag.
+2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6
+2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
+2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 340
+
+
+2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 7 half transfer flag.
+2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7
+2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
+2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 0 transfer complete flag.
+2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0
+2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
+2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
+2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 1 transfer complete flag.
+2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1
+2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
+2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 2 transfer complete flag.
+2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2
+2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
+2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 3 transfer complete flag.
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3
+2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
+2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 4 transfer complete flag.
+2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4
+ARM GAS  /tmp/ccdsDELB.s 			page 341
+
+
+2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
+2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 5 transfer complete flag.
+2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5
+2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
+2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 6 transfer complete flag.
+2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6
+2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
+2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 7 transfer complete flag.
+2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7
+2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+ 4689              		.loc 6 2277 22 view .LVU1605
+ 4690              	.LBB468:
+2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
+ 4691              		.loc 6 2279 3 view .LVU1606
+ 4692 00dc 4FF00062 		mov	r2, #134217728
+ 4693 00e0 DA60     		str	r2, [r3, #12]
+ 4694              	.LVL338:
+ 4695              		.loc 6 2279 3 is_stmt 0 view .LVU1607
+ 4696              	.LBE468:
+ 4697              	.LBE467:
+1520:Src/main.c    ****   LL_USART_EnableDMAReq_TX(USART1);
+ 4698              		.loc 2 1520 3 is_stmt 1 view .LVU1608
+ 4699              	.LBB469:
+ 4700              	.LBI469:
+2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 0 transfer error flag.
+2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0
+ARM GAS  /tmp/ccdsDELB.s 			page 342
+
+
+2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
+2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
+2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 1 transfer error flag.
+2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1
+2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
+2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 2 transfer error flag.
+2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2
+2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
+2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 3 transfer error flag.
+2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3
+2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
+2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 4 transfer error flag.
+2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4
+2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
+2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 5 transfer error flag.
+2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5
+2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ARM GAS  /tmp/ccdsDELB.s 			page 343
+
+
+2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
+2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 6 transfer error flag.
+2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6
+2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
+2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 7 transfer error flag.
+2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7
+2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+ 4701              		.loc 6 2365 22 view .LVU1609
+ 4702              	.LBB470:
+2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
+ 4703              		.loc 6 2367 3 view .LVU1610
+ 4704 00e2 4FF00072 		mov	r2, #33554432
+ 4705 00e6 DA60     		str	r2, [r3, #12]
+ 4706              	.LVL339:
+ 4707              	.L173:
+ 4708              		.loc 6 2367 3 is_stmt 0 view .LVU1611
+ 4709              	.LBE470:
+ 4710              	.LBE469:
+ 4711              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @file    stm32f7xx_ll_usart.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief   Header file of USART LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifndef STM32F7xx_LL_USART_H
+ARM GAS  /tmp/ccdsDELB.s 			page 344
+
+
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define STM32F7xx_LL_USART_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****  || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8)
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL USART
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private types -------------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private variables ---------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private constants ---------------------------------------------------------*/
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Constants USART Private Constants
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private macros ------------------------------------------------------------*/
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER)
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Macros USART Private Macros
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported types ------------------------------------------------------------*/
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER)
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief LL USART Init Structure definition
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rat
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetBaudRate().*/
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 345
+
+
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or receive
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_DATAWI
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetDataWidth().*/
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_STOPBI
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetStopBitsLength().*/
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t Parity;                    /*!< Specifies the parity mode.
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_PARITY
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetParity().*/
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is en
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_DIRECT
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetTransferDirection().*/
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enab
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_HWCONT
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetHWFlowCtrl().*/
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_OVERSA
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetOverSampling().*/
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_InitTypeDef;
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief LL USART Clock Init Structure definition
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_CLOCK.
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_Disabl
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_POLARI
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            functions @ref LL_USART_SetClockPolarity().
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 346
+
+
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture 
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_PHASE.
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            functions @ref LL_USART_SetClockPhase().
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the l
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            data bit (MSB) has to be output on the SCLK pin in synch
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_LASTCL
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            functions @ref LL_USART_SetLastClkPulseOutput().
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_ClockInitTypeDef;
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USE_FULL_LL_DRIVER */
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported constants --------------------------------------------------------*/
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Constants USART Exported Constants
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief    Flags defines which can be used with LL_USART_WriteReg function
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error cle
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error cl
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_NCF                        USART_ICR_NCF                 /*!< Noise error dete
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error cl
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detect
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission com
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission com
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detect
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag *
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block cle
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match 
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief    Flags defines which can be used with LL_USART_ReadReg function
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ARM GAS  /tmp/ccdsDELB.s 			page 347
+
+
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error fla
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error fl
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected f
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error fl
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detect
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RXNE                       USART_ISR_RXNE                /*!< Read data regist
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission com
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TXE                        USART_ISR_TXE                 /*!< Transmit data re
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detect
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt fl
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block fla
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate e
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate f
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match 
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag 
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup 
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable 
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK)
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable a
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission com
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IT IT Defines
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt e
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data regist
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission com
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data re
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match 
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block int
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detect
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt 
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt en
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+ARM GAS  /tmp/ccdsDELB.s 			page 348
+
+
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission com
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DIRECTION Communication Direction
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PARITY Parity Control
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity co
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity co
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity co
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP Wakeup
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : S
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : S
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : S
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER)
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLOCK Clock Signal
+ARM GAS  /tmp/ccdsDELB.s 			page 349
+
+
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provid
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided *
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the l
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the l
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PHASE Clock Phase
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transiti
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transit
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_POLARITY Clock Polarity
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCL
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_STOPBITS Stop Bits
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 s
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 s
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as d
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 350
+
+
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works usin
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works usin
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the da
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the da
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BITORDER Bit Order
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/rece
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/rece
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Me
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Fa
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection 
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection 
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+ARM GAS  /tmp/ccdsDELB.s 			page 351
+
+
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and R
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS outpu
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode 
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and R
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS)
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake u
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake u
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake u
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode *
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection m
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection m
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low 
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data regis
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data regis
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 352
+
+
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported macro ------------------------------------------------------------*/
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Macros USART Exported Macros
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Write a value in USART register
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __INSTANCE__ USART Instance
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __REG__ Register to be written
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __VALUE__ Value to be written in the register
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Read a value in USART register
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __INSTANCE__ USART Instance
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __REG__ Register to be read
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Register value
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Compute USARTDIV value according to Peripheral Clock and
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __BAUDRATE__ Baud rate value to achieve
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                                                 + ((__BAUDRATE__)/2U))/(__BAUDRATE_
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Compute USARTDIV value according to Peripheral Clock and
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __BAUDRATE__ Baud rate value to achieve
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 353
+
+
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported functions --------------------------------------------------------*/
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Functions USART Exported Functions
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration Configuration functions
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART Enable
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UE            LL_USART_Enable
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR1, USART_CR1_UE);
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART Disable (all USART prescalers and outputs are disabled)
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         and current operations are discarded. The configuration of the USART is kept, but all t
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         flags, in the USARTx_ISR are set to their default values.
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UE            LL_USART_Disable
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if USART is enabled
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UE            LL_USART_IsEnabled
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ARM GAS  /tmp/ccdsDELB.s 			page 354
+
+
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART enabled in STOP Mode.
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provide
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         USART clock selection is HSI or LSE in RCC.
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART disabled in STOP Mode.
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_UCESM)
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART Clock enabled in STOP Mode
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is called, USART Clock is enabled while in STOP mode
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          UCESM         LL_USART_EnableClockInStopMode
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx)
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM);
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART clock disabled in STOP Mode
+ARM GAS  /tmp/ccdsDELB.s 			page 355
+
+
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is called, USART Clock is disabled while in STOP mode
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          UCESM         LL_USART_DisableClockInStopMode
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx)
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM);
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if USART clock is enabled in STOP Mode
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          UCESM         LL_USART_IsClockEnabledInStopMode
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx)
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM));
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_UCESM */
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM*/
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Receiver Disable
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Transmitter Enable
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 356
+
+
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Transmitter Disable
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure simultaneously enabled/disabled states
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         of Transmitter and Receiver
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          TE            LL_USART_SetTransferDirection
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  TransferDirection This parameter can be one of the following values:
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_NONE
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_RX
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX_RX
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirectio
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return enabled/disabled states of Transmitter and Receiver
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          TE            LL_USART_GetTransferDirection
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_NONE
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_RX
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX_RX
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   This function selects if hardware parity control (generation and detection) is enabled 
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at th
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PS            LL_USART_SetParity\n
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          PCE           LL_USART_SetParity
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Parity This parameter can be one of the following values:
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_NONE
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_EVEN
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_ODD
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ARM GAS  /tmp/ccdsDELB.s 			page 357
+
+
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PS            LL_USART_GetParity\n
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          PCE           LL_USART_GetParity
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_NONE
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_EVEN
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_ODD
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Receiver Wake Up method from Mute mode.
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Method This parameter can be one of the following values:
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_IDLELINE
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Receiver Wake Up method from Mute mode
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_IDLELINE
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M1            LL_USART_SetDataWidth
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  DataWidth This parameter can be one of the following values:
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_7B
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_8B
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_9B
+ARM GAS  /tmp/ccdsDELB.s 			page 358
+
+
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M1            LL_USART_GetDataWidth
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_7B
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_8B
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_9B
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Allow switch between Mute Mode and Active mode
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Oversampling to 8-bit or 16-bit mode
+ARM GAS  /tmp/ccdsDELB.s 			page 359
+
+
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  OverSampling This parameter can be one of the following values:
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_16
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_8
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Oversampling mode
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_16
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_8
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  LastBitClockPulse This parameter can be one of the following values:
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPul
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve Clock pulse of the last data bit output configuration
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (Last bit Clock pulse output to the SCLK pin or not)
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 360
+
+
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  ClockPhase This parameter can be one of the following values:
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_1EDGE
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_2EDGE
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_1EDGE
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_2EDGE
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  ClockPolarity This parameter can be one of the following values:
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_LOW
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_HIGH
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_LOW
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_HIGH
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 361
+
+
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutpu
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CPOL          LL_USART_ConfigClock\n
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          LBCL          LL_USART_ConfigClock
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Phase This parameter can be one of the following values:
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_1EDGE
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_2EDGE
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Polarity This parameter can be one of the following values:
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_LOW
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_HIGH
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  LBCPOutput This parameter can be one of the following values:
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity,
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCP
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Clock output on SCLK pin
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Clock output on SCLK pin
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+ARM GAS  /tmp/ccdsDELB.s 			page 362
+
+
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Clock output on SCLK pin is enabled
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set the length of the stop bits
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  StopBits This parameter can be one of the following values:
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_0_5
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1_5
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_2
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve the length of the stop bits
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_0_5
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1_5
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_2
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          PCE           LL_USART_ConfigCharacter\n
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M0            LL_USART_ConfigCharacter\n
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M1            LL_USART_ConfigCharacter\n
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          STOP          LL_USART_ConfigCharacter
+ARM GAS  /tmp/ccdsDELB.s 			page 363
+
+
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  DataWidth This parameter can be one of the following values:
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_7B
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_8B
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_9B
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Parity This parameter can be one of the following values:
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_NONE
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_EVEN
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_ODD
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  StopBits This parameter can be one of the following values:
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_0_5
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1_5
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_2
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t P
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                               uint32_t StopBits)
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure TX/RX pins swapping setting.
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  SwapConfig This parameter can be one of the following values:
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_STANDARD
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_SWAPPED
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve TX/RX pins swapping configuration.
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_STANDARD
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_SWAPPED
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure RX pin active level logic
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PinInvMethod This parameter can be one of the following values:
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+ARM GAS  /tmp/ccdsDELB.s 			page 364
+
+
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve RX pin active level logic configuration
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure TX pin active level logic
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PinInvMethod This parameter can be one of the following values:
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve TX pin active level logic configuration
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Binary data logic.
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Allow to define how Logical data from the data register are send/received :
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  DataLogic This parameter can be one of the following values:
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ARM GAS  /tmp/ccdsDELB.s 			page 365
+
+
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve Binary data configuration
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   MSB First means data is transmitted/received with the MSB first, following the start bi
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LSB First means data is transmitted/received with data bit 0 first, following the start
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  BitOrder This parameter can be one of the following values:
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_LSBFIRST
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_MSBFIRST
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   MSB First means data is transmitted/received with the MSB first, following the start bi
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LSB First means data is transmitted/received with data bit 0 first, following the start
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_LSBFIRST
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_MSBFIRST
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Auto Baud-Rate Detection
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ARM GAS  /tmp/ccdsDELB.s 			page 366
+
+
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Auto Baud-Rate Detection
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Auto Baud-Rate mode bits
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  AutoBaudRateMode This parameter can be one of the following values:
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Auto Baud-Rate mode
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ARM GAS  /tmp/ccdsDELB.s 			page 367
+
+
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Receiver Timeout
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Receiver Timeout
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Receiver Timeout feature is enabled
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Address of the USART node.
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         for wake up with address mark detection.
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (b7-b4 should be set to 0)
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         for wake up with 7-bit address mark detection.
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         The MSB of the character sent by the transmitter should be equal to 1.
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         It may also be used for character detection during normal reception,
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         value and CMF flag is set on match)
+ARM GAS  /tmp/ccdsDELB.s 			page 368
+
+
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  AddressLen This parameter can be one of the following values:
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  NodeAddress 4 or 7 bit Address of the USART node.
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   If 4-bit Address Detection is selected in ADDM7,
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         If 7-bit Address Detection is selected in ADDM7,
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable RTS HW Flow Control
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 369
+
+
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable RTS HW Flow Control
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable CTS HW Flow Control
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable CTS HW Flow Control
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure HW Flow Control mode (both CTS and RTS)
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  HardwareFlowControl This parameter can be one of the following values:
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_NONE
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_CTS
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 370
+
+
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return HW Flow Control configuration (both CTS and RTS)
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_NONE
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_CTS
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable One bit sampling method
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable One bit sampling method
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if One bit sampling method is enabled
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Overrun detection
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 371
+
+
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Overrun detection
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Overrun detection is enabled
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS)
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Type This parameter can be one of the following values:
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 372
+
+
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (Baud rate value != 0)
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PeriphClk Peripheral Clock
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  OverSampling This parameter can be one of the following values:
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_16
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_8
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  BaudRate Baud Rate
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverS
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                           uint32_t BaudRate)
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t usartdiv;
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t brrtemp;
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   if (OverSampling == LL_USART_OVERSAMPLING_8)
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp = usartdiv & 0xFFF0U;
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     USARTx->BRR = brrtemp;
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   else
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be ret
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PeriphClk Peripheral Clock
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  OverSampling This parameter can be one of the following values:
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_16
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_8
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Baud Rate
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 373
+
+
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t usartdiv;
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t brrresult = 0x0U;
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   usartdiv = USARTx->BRR;
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   if (usartdiv == 0U)
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     /* Do not perform a division by 0 */
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   else if (OverSampling == LL_USART_OVERSAMPLING_8)
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     if (usartdiv != 0U)
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     {
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****       brrresult = (PeriphClk * 2U) / usartdiv;
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     }
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   else
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     if ((usartdiv & 0xFFFFU) != 0U)
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     {
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****       brrresult = PeriphClk / usartdiv;
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     }
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (brrresult);
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Block Length value in reception
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 374
+
+
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Get Block Length value in reception
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable IrDA mode
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          IREN          LL_USART_EnableIrda
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_IREN);
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable IrDA mode
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          IREN          LL_USART_DisableIrda
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if IrDA mode is enabled
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ARM GAS  /tmp/ccdsDELB.s 			page 375
+
+
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure IrDA Power Mode (Normal or Low Power)
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PowerMode This parameter can be one of the following values:
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_IRDA_POWER_LOW
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_2EDGE
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Irda prescaler value, used for dividing the USART clock source
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         to achieve the Irda Low Power frequency (8 bits value)
+1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Irda prescaler value, used for dividing the USART clock source
+1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         to achieve the Irda Low Power frequency (8 bits value)
+1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+ARM GAS  /tmp/ccdsDELB.s 			page 376
+
+
+1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
+1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feat
+1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Smartcard NACK transmission
+1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_NACK);
+1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Smartcard NACK transmission
+1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Smartcard NACK transmission is enabled
+1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
+1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 377
+
+
+1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Smartcard mode
+1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Smartcard mode
+1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Smartcard mode is enabled
+1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
+1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mo
+1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         In transmission mode, it specifies the number of automatic retransmission retries, befo
+1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         generating a transmission error (FE bit set).
+1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         In reception mode, it specifies the number or erroneous reception trials, before genera
+1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         reception error (RXNE and PE bits set)
+1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryC
+1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 378
+
+
+1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
+1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         source to provide the SMARTCARD Clock (5 bits value)
+1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         source to provide the SMARTCARD Clock (5 bits value)
+1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
+1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (GT[7:0] bits : Guard time value)
+2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 379
+
+
+2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (GT[7:0] bits : Guard time value)
+2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
+2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex f
+2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Single Wire Half-Duplex mode
+2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Half-Duplex mode is supported by the USARTx instance.
+2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Single Wire Half-Duplex mode
+2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Half-Duplex mode is supported by the USARTx instance.
+2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Half-Duplex mode is supported by the USARTx instance.
+2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
+ARM GAS  /tmp/ccdsDELB.s 			page 380
+
+
+2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set LIN Break Detection Length
+2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  LINBDLength This parameter can be one of the following values:
+2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return LIN Break Detection Length
+2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
+2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable LIN mode
+2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 381
+
+
+2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable LIN mode
+2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if LIN mode is enabled
+2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
+2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits)
+2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Time Value between Min_Data=0 and Max_Data=31
+2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return DEDT (Driver Enable De-Assertion Time)
+2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
+2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 382
+
+
+2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Time Value between Min_Data=0 and Max_Data=31
+2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return DEAT (Driver Enable Assertion Time)
+2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
+2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Driver Enable (DE) Mode
+2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_DEM);
+2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Driver Enable (DE) Mode
+2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 383
+
+
+2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Driver Enable (DE) Mode is enabled
+2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
+2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Select Driver Enable Polarity
+2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Polarity This parameter can be one of the following values:
+2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DE_POLARITY_HIGH
+2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DE_POLARITY_LOW
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Driver Enable Polarity
+2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DE_POLARITY_HIGH
+2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DE_POLARITY_LOW
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
+2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In UART mode, the following bits must be kept cleared:
+2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - CLKEN bit in the USART_CR2 register,
+2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+ARM GAS  /tmp/ccdsDELB.s 			page 384
+
+
+2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Asynchronous Mode
+2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, Parity, ...) should be set using
+2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In Asynchronous mode, the following bits must be kept cleared:
+2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN, CLKEN bits in the USART_CR2 register,
+2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In Synchronous mode, the following bits must be kept cleared:
+2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         This function also sets the USART in Synchronous mode.
+2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Synchronous Mode
+2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigSyncMode\n
+2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigSyncMode
+2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+ARM GAS  /tmp/ccdsDELB.s 			page 385
+
+
+2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In Synchronous mode, the following bits must be kept cleared:
+2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN bit in the USART_CR2 register,
+2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* set the UART/USART in Synchronous mode */
+2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In LIN mode, the following bits must be kept cleared:
+2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - STOP and CLKEN bits in the USART_CR2 register,
+2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         This function also set the UART/USART in LIN mode.
+2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to LIN Mode
+2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          STOP          LL_USART_ConfigLINMode\n
+2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          LINEN         LL_USART_ConfigLINMode\n
+2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigLINMode\n
+2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigLINMode\n
+2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigLINMode
+2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In LIN mode, the following bits must be kept cleared:
+2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - STOP and CLKEN bits in the USART_CR2 register,
+2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* Set the UART/USART in LIN mode */
+2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In Half Duplex mode, the following bits must be kept cleared:
+2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - CLKEN bit in the USART_CR2 register,
+ARM GAS  /tmp/ccdsDELB.s 			page 386
+
+
+2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         This function also sets the UART/USART in Half Duplex mode.
+2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Half-Duplex mode is supported by the USARTx instance.
+2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Half Duplex Mode
+2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, Parity, ...) should be set using
+2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In Half Duplex mode, the following bits must be kept cleared:
+2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN and CLKEN bits in the USART_CR2 register,
+2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - SCEN and IREN bits in the USART_CR3 register.
+2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* set the UART/USART in Half Duplex mode */
+2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In Smartcard mode, the following bits must be kept cleared:
+2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         This function also configures Stop bits to 1.5 bits and
+2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         sets the USART in Smartcard mode (SCEN bit).
+2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Clock Output is also enabled (CLKEN).
+2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Smartcard Mode
+2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, Parity, ...) should be set using
+2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+ARM GAS  /tmp/ccdsDELB.s 			page 387
+
+
+2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In Smartcard mode, the following bits must be kept cleared:
+2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN bit in the USART_CR2 register,
+2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - IREN and HDSEL bits in the USART_CR3 register.
+2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* Configure Stop bits to 1.5 bits */
+2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* Synchronous mode is activated by default */
+2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* set the UART/USART in Smartcard mode */
+2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In IRDA mode, the following bits must be kept cleared:
+2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - STOP and CLKEN bits in the USART_CR2 register,
+2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         This function also sets the UART/USART in IRDA mode (IREN bit).
+2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Irda Mode
+2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, Power mode, ...) should be set using
+2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigIrdaMode
+2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In IRDA mode, the following bits must be kept cleared:
+2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - SCEN and HDSEL bits in the USART_CR3 register.
+2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ARM GAS  /tmp/ccdsDELB.s 			page 388
+
+
+2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* set the UART/USART in IRDA mode */
+2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_IREN);
+2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (several USARTs connected in a network, one of the USARTs can be the master,
+2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         its TX output connected to the RX inputs of the other slaves USARTs).
+2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In MultiProcessor mode, the following bits must be kept cleared:
+2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - CLKEN bit in the USART_CR2 register,
+2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Multi processor Mode
+2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In Multi Processor mode, the following bits must be kept cleared:
+2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN and CLKEN bits in the USART_CR2 register,
+2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Parity Error Flag is set or not
+2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
+ARM GAS  /tmp/ccdsDELB.s 			page 389
+
+
+2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Framing Error Flag is set or not
+2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
+2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Noise error detected Flag is set or not
+2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
+2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
+2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART OverRun Error Flag is set or not
+2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
+2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART IDLE line detected Flag is set or not
+2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
+2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
+2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          RXNE          LL_USART_IsActiveFlag_RXNE
+2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx)
+2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
+ARM GAS  /tmp/ccdsDELB.s 			page 390
+
+
+2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Transmission Complete Flag is set or not
+2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
+2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
+2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          TXE           LL_USART_IsActiveFlag_TXE
+2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx)
+2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
+2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART LIN Break Detection Flag is set or not
+2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
+2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART CTS interrupt Flag is set or not
+2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
+2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART CTS Flag is set or not
+2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ARM GAS  /tmp/ccdsDELB.s 			page 391
+
+
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
+2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Receiver Time Out Flag is set or not
+2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
+2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART End Of Block Flag is set or not
+2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
+2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
+2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
+2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 392
+
+
+2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Busy Flag is set or not
+2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
+2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Character Match Flag is set or not
+2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
+2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Send Break Flag is set or not
+2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
+2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
+2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
+2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 393
+
+
+2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
+2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK)
+2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
+2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */
+2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */
+2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx)
+2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Parity Error Flag
+2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Framing Error Flag
+2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ARM GAS  /tmp/ccdsDELB.s 			page 394
+
+
+2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Noise Error detected Flag
+2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          NCF           LL_USART_ClearFlag_NE
+2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_NCF);
+2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear OverRun Error Flag
+2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear IDLE line detected Flag
+2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Transmission Complete Flag
+2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */
+2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ARM GAS  /tmp/ccdsDELB.s 			page 395
+
+
+2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear LIN Break Detection Flag
+2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear CTS Interrupt Flag
+2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Receiver Time Out Flag
+2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear End Of Block Flag
+2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 396
+
+
+2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Character Match Flag
+2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Wake Up from stop mode Flag
+3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_IT_Management IT_Management
+3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable IDLE Interrupt
+3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable RX Not Empty Interrupt
+3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
+3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 397
+
+
+3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Transmission Complete Interrupt
+3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable TX Empty Interrupt
+3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
+3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Parity Error Interrupt
+3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Character Match Interrupt
+3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Receiver Timeout Interrupt
+3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 398
+
+
+3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable End Of Block Interrupt
+3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable LIN Break Detection Interrupt
+3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Error Interrupt
+3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram
+3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           0: Interrupt is inhibited
+3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable CTS Interrupt
+3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Wake Up from Stop Mode Interrupt
+ARM GAS  /tmp/ccdsDELB.s 			page 399
+
+
+3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */
+3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable IDLE Interrupt
+3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable RX Not Empty Interrupt
+3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
+3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Transmission Complete Interrupt
+3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 400
+
+
+3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable TX Empty Interrupt
+3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
+3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Parity Error Interrupt
+3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Character Match Interrupt
+3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Receiver Timeout Interrupt
+3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable End Of Block Interrupt
+3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/ccdsDELB.s 			page 401
+
+
+3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable LIN Break Detection Interrupt
+3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Error Interrupt
+3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram
+3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           0: Interrupt is inhibited
+3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable CTS Interrupt
+3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Wake Up from Stop Mode Interrupt
+3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+ARM GAS  /tmp/ccdsDELB.s 			page 402
+
+
+3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */
+3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
+3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
+3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
+3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx)
+3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U);
+3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
+3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
+ARM GAS  /tmp/ccdsDELB.s 			page 403
+
+
+3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
+3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx)
+3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U);
+3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
+3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
+3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
+3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
+3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+ARM GAS  /tmp/ccdsDELB.s 			page 404
+
+
+3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
+3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Error Interrupt is enabled or disabled.
+3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
+3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
+3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
+3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */
+3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or 
+3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ARM GAS  /tmp/ccdsDELB.s 			page 405
+
+
+3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx)
+3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_DMA_Management DMA_Management
+3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable DMA Mode for reception
+3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable DMA Mode for reception
+3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if DMA Mode is enabled for reception
+3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
+3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable DMA Mode for transmission
+3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ARM GAS  /tmp/ccdsDELB.s 			page 406
+
+
+3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+ 4712              		.loc 7 3558 3 is_stmt 1 view .LVU1612
+ 4713              	.LBB471:
+ 4714              	.LBB472:
+ 4715              		.loc 7 3558 3 view .LVU1613
+ 4716              		.loc 7 3558 3 view .LVU1614
+ 4717              		.loc 7 3558 3 view .LVU1615
+ 4718 00e8 764A     		ldr	r2, .L182+76
+ 4719              	.LVL340:
+ 4720              	.LBB473:
+ 4721              	.LBI473:
+ 4722              		.file 8 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.0.4
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     09. April 2018
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccdsDELB.s 			page 407
+
+
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ARM GAS  /tmp/ccdsDELB.s 			page 408
+
+
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ARM GAS  /tmp/ccdsDELB.s 			page 409
+
+
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 410
+
+
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 411
+
+
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ARM GAS  /tmp/ccdsDELB.s 			page 412
+
+
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ARM GAS  /tmp/ccdsDELB.s 			page 413
+
+
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ARM GAS  /tmp/ccdsDELB.s 			page 414
+
+
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/ccdsDELB.s 			page 415
+
+
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ARM GAS  /tmp/ccdsDELB.s 			page 416
+
+
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ARM GAS  /tmp/ccdsDELB.s 			page 417
+
+
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 418
+
+
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 419
+
+
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccdsDELB.s 			page 420
+
+
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ARM GAS  /tmp/ccdsDELB.s 			page 421
+
+
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 891:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 892:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 895:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
+ 896:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
+ 897:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ARM GAS  /tmp/ccdsDELB.s 			page 422
+
+
+ 898:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 899:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+ 901:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ 903:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_bswap32(value);
+ 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 905:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 906:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 908:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 910:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 912:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 915:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
+ 916:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 917:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 918:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+ 920:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 922:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 923:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 924:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 925:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 930:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
+ 931:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 932:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ 937:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
+ 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 939:Drivers/CMSIS/Include/cmsis_gcc.h ****   int16_t result;
+ 940:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 942:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 945:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 946:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 948:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
+ 949:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
+ 950:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
+ 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
+ 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
+ 953:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+ARM GAS  /tmp/ccdsDELB.s 			page 423
+
+
+ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 956:Drivers/CMSIS/Include/cmsis_gcc.h ****   op2 %= 32U;
+ 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (op2 == 0U)
+ 958:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 959:Drivers/CMSIS/Include/cmsis_gcc.h ****     return op1;
+ 960:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 961:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
+ 962:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 963:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 964:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 966:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
+ 967:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
+ 968:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
+ 969:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
+ 970:Drivers/CMSIS/Include/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
+ 971:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+ 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 974:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 976:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse bit order of value
+ 977:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
+ 978:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 979:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 980:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+ 982:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 984:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 986:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 987:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 990:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+ 991:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 992:Drivers/CMSIS/Include/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
+ 993:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
+ 994:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 995:Drivers/CMSIS/Include/cmsis_gcc.h ****     result <<= 1U;
+ 996:Drivers/CMSIS/Include/cmsis_gcc.h ****     result |= value & 1U;
+ 997:Drivers/CMSIS/Include/cmsis_gcc.h ****     s--;
+ 998:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 999:Drivers/CMSIS/Include/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
+1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1001:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+1002:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1003:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1004:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1005:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1006:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Count leading zeros
+1007:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
+1008:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
+1009:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             number of leading zeros in value
+1010:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1011:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CLZ             (uint8_t)__builtin_clz
+ARM GAS  /tmp/ccdsDELB.s 			page 424
+
+
+1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1014:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+1015:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+1016:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+1017:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+1018:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1019:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (8 bit)
+1020:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 8 bit value.
+1021:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1022:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
+1023:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1024:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+1025:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1026:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+1027:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1028:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1029:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+1030:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1031:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+1032:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
+1033:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
+1034:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+1035:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1036:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
+1037:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1038:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1039:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1040:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1041:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (16 bit)
+1042:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 16 bit values.
+1043:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1044:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
+1045:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1046:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+1047:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1048:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+1049:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1051:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1053:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+1054:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
+1055:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
+1056:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+1057:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1058:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
+1059:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1060:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1061:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1062:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1063:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (32 bit)
+1064:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 32 bit values.
+1065:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1066:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
+1067:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+ARM GAS  /tmp/ccdsDELB.s 			page 425
+
+
+ 4723              		.loc 8 1068 31 view .LVU1616
+ 4724              	.LBB474:
+1069:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1070:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+ 4725              		.loc 8 1070 5 view .LVU1617
+1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1072:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 4726              		.loc 8 1072 4 view .LVU1618
+ 4727              		.syntax unified
+ 4728              	@ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4729 00ea 52E8003F 		ldrex r3, [r2]
+ 4730              	@ 0 "" 2
+ 4731              	.LVL341:
+1073:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4732              		.loc 8 1073 4 view .LVU1619
+ 4733              		.loc 8 1073 4 is_stmt 0 view .LVU1620
+ 4734              		.thumb
+ 4735              		.syntax unified
+ 4736              	.LBE474:
+ 4737              	.LBE473:
+ 4738              		.loc 7 3558 3 view .LVU1621
+ 4739 00ee 43F08003 		orr	r3, r3, #128
+ 4740              	.LVL342:
+ 4741              		.loc 7 3558 3 is_stmt 1 view .LVU1622
+ 4742              	.LBB475:
+ 4743              	.LBI475:
+1074:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1075:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1076:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1077:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1078:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (8 bit)
+1079:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 8 bit values.
+1080:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1081:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1082:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1083:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1084:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1085:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+1086:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1087:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+1088:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+1090:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+1091:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1092:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1093:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1094:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1095:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (16 bit)
+1096:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 16 bit values.
+1097:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1098:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1099:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1100:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1101:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1102:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+1103:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1104:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+ARM GAS  /tmp/ccdsDELB.s 			page 426
+
+
+1105:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1106:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+1107:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+1108:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1109:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1110:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1111:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1112:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (32 bit)
+1113:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 32 bit values.
+1114:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1115:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1116:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1117:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1118:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1119:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+ 4744              		.loc 8 1119 31 view .LVU1623
+ 4745              	.LBB476:
+1120:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1121:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+ 4746              		.loc 8 1121 4 view .LVU1624
+1122:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1123:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 4747              		.loc 8 1123 4 view .LVU1625
+ 4748              		.syntax unified
+ 4749              	@ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 4750 00f2 42E80031 		strex r1, r3, [r2]
+ 4751              	@ 0 "" 2
+ 4752              	.LVL343:
+1124:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 4753              		.loc 8 1124 4 view .LVU1626
+ 4754              		.loc 8 1124 4 is_stmt 0 view .LVU1627
+ 4755              		.thumb
+ 4756              		.syntax unified
+ 4757              	.LBE476:
+ 4758              	.LBE475:
+ 4759              		.loc 7 3558 3 view .LVU1628
+ 4760 00f6 0029     		cmp	r1, #0
+ 4761 00f8 F6D1     		bne	.L173
+ 4762              	.LBE472:
+ 4763              	.LBE471:
+ 4764              		.loc 7 3558 3 is_stmt 1 view .LVU1629
+ 4765              	.LVL344:
+1522:Src/main.c    ****   LL_DMA_EnableIT_TE(DMA2, LL_DMA_STREAM_7);
+ 4766              		.loc 2 1522 3 view .LVU1630
+ 4767              	.LBB477:
+ 4768              	.LBI477:
+2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 0 direct mode error flag.
+2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0
+2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
+2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
+ARM GAS  /tmp/ccdsDELB.s 			page 427
+
+
+2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 1 direct mode error flag.
+2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1
+2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
+2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
+2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 2 direct mode error flag.
+2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2
+2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
+2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
+2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 3 direct mode error flag.
+2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3
+2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
+2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
+2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 4 direct mode error flag.
+2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4
+2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
+2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
+2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 5 direct mode error flag.
+2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5
+2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
+2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
+2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 428
+
+
+2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 6 direct mode error flag.
+2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6
+2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
+2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
+2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 7 direct mode error flag.
+2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7
+2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
+2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
+2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 0 FIFO error flag.
+2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0
+2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
+2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
+2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 1 FIFO error flag.
+2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1
+2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
+2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
+2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 2 FIFO error flag.
+2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2
+2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
+2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
+2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 3 FIFO error flag.
+ARM GAS  /tmp/ccdsDELB.s 			page 429
+
+
+2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3
+2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
+2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
+2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 4 FIFO error flag.
+2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4
+2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
+2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
+2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 5 FIFO error flag.
+2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5
+2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
+2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
+2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 6 FIFO error flag.
+2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6
+2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
+2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
+2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 7 FIFO error flag.
+2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7
+2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
+2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
+2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 430
+
+
+2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_IT_Management IT_Management
+2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable Half transfer interrupt.
+2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT
+2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA
+2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable Transfer error interrupt.
+2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE
+2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA
+2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable Transfer complete interrupt.
+2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC
+2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ARM GAS  /tmp/ccdsDELB.s 			page 431
+
+
+2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+ 4769              		.loc 6 2609 22 view .LVU1631
+ 4770              	.LBB478:
+2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA
+ 4771              		.loc 6 2611 3 view .LVU1632
+ 4772 00fa 734B     		ldr	r3, .L182+80
+ 4773 00fc D3F8B820 		ldr	r2, [r3, #184]
+ 4774 0100 42F01002 		orr	r2, r2, #16
+ 4775 0104 C3F8B820 		str	r2, [r3, #184]
+ 4776              	.LVL345:
+ 4777              		.loc 6 2611 3 is_stmt 0 view .LVU1633
+ 4778              	.LBE478:
+ 4779              	.LBE477:
+1523:Src/main.c    ****   LL_DMA_ClearFlag_TC7(DMA2);
+ 4780              		.loc 2 1523 3 is_stmt 1 view .LVU1634
+ 4781              	.LBB479:
+ 4782              	.LBI479:
+2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 4783              		.loc 6 2589 22 view .LVU1635
+ 4784              	.LBB480:
+2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 4785              		.loc 6 2591 3 view .LVU1636
+ 4786 0108 D3F8B820 		ldr	r2, [r3, #184]
+ 4787 010c 42F00402 		orr	r2, r2, #4
+ 4788 0110 C3F8B820 		str	r2, [r3, #184]
+ 4789              	.LVL346:
+2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 4790              		.loc 6 2591 3 is_stmt 0 view .LVU1637
+ 4791              	.LBE480:
+ 4792              	.LBE479:
+1524:Src/main.c    ****   LL_DMA_ClearFlag_TE7(DMA2);
+ 4793              		.loc 2 1524 3 is_stmt 1 view .LVU1638
+ 4794              	.LBB481:
+ 4795              	.LBI481:
+2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 4796              		.loc 6 2277 22 view .LVU1639
+ 4797              	.LBB482:
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 4798              		.loc 6 2279 3 view .LVU1640
+ 4799 0114 4FF00062 		mov	r2, #134217728
+ 4800 0118 DA60     		str	r2, [r3, #12]
+ 4801              	.LVL347:
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 4802              		.loc 6 2279 3 is_stmt 0 view .LVU1641
+ 4803              	.LBE482:
+ 4804              	.LBE481:
+1525:Src/main.c    ****   LL_DMA_ConfigAddresses(DMA2, LL_DMA_STREAM_7, (uint32_t)&UART_DATA, LL_USART_DMA_GetRegAddr(USART
+ 4805              		.loc 2 1525 3 is_stmt 1 view .LVU1642
+ 4806              	.LBB483:
+ 4807              	.LBI483:
+2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 4808              		.loc 6 2365 22 view .LVU1643
+ 4809              	.LBB484:
+2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 432
+
+
+ 4810              		.loc 6 2367 3 view .LVU1644
+ 4811 011a 4FF00072 		mov	r2, #33554432
+ 4812 011e DA60     		str	r2, [r3, #12]
+ 4813              	.LVL348:
+2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 4814              		.loc 6 2367 3 is_stmt 0 view .LVU1645
+ 4815              	.LBE484:
+ 4816              	.LBE483:
+1526:Src/main.c    **** 	
+ 4817              		.loc 2 1526 3 is_stmt 1 view .LVU1646
+ 4818 0120 6A49     		ldr	r1, .L182+84
+ 4819              	.LVL349:
+ 4820              	.LBB485:
+ 4821              	.LBI485:
+3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable DMA Mode for transmission
+3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if DMA Mode is enabled for transmission
+3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
+3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable DMA Disabling on Reception Error
+3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable DMA Disabling on Reception Error
+3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 433
+
+
+3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if DMA Disabling on Reception Error is disabled
+3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
+3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Get the data register address used for DMA transfer
+3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Direction This parameter can be one of the following values:
+3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Address of data register
+3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
+ 4822              		.loc 7 3626 26 view .LVU1647
+ 4823              	.LBB486:
+3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t data_reg_addr;
+ 4824              		.loc 7 3628 3 view .LVU1648
+3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+ 4825              		.loc 7 3630 3 view .LVU1649
+3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     /* return address of TDR register */
+3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     data_reg_addr = (uint32_t) &(USARTx->TDR);
+ 4826              		.loc 7 3633 5 view .LVU1650
+ 4827              		.loc 7 3633 32 is_stmt 0 view .LVU1651
+ 4828 0122 6B4A     		ldr	r2, .L182+88
+ 4829              	.LVL350:
+3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   else
+3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     /* return address of RDR register */
+3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     data_reg_addr = (uint32_t) &(USARTx->RDR);
+3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return data_reg_addr;
+ 4830              		.loc 7 3641 3 is_stmt 1 view .LVU1652
+ 4831              		.loc 7 3641 3 is_stmt 0 view .LVU1653
+ 4832              	.LBE486:
+ 4833              	.LBE485:
+ 4834              	.LBB487:
+ 4835              	.LBI487:
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 4836              		.loc 6 621 26 is_stmt 1 view .LVU1654
+ 4837              	.LBB488:
+ARM GAS  /tmp/ccdsDELB.s 			page 434
+
+
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 4838              		.loc 6 623 3 view .LVU1655
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 4839              		.loc 6 623 11 is_stmt 0 view .LVU1656
+ 4840 0124 D3F8B830 		ldr	r3, [r3, #184]
+ 4841 0128 03F0C003 		and	r3, r3, #192
+ 4842              	.LVL351:
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 4843              		.loc 6 623 11 view .LVU1657
+ 4844              	.LBE488:
+ 4845              	.LBE487:
+ 4846              	.LBB489:
+ 4847              	.LBI489:
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 4848              		.loc 6 1425 22 is_stmt 1 view .LVU1658
+ 4849              	.LBB490:
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+ 4850              		.loc 6 1428 3 view .LVU1659
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+ 4851              		.loc 6 1428 6 is_stmt 0 view .LVU1660
+ 4852 012c 402B     		cmp	r3, #64
+ 4853 012e 7AD0     		beq	.L179
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR
+ 4854              		.loc 6 1436 5 is_stmt 1 view .LVU1661
+ 4855 0130 654B     		ldr	r3, .L182+80
+ 4856              	.LVL352:
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR
+ 4857              		.loc 6 1436 5 is_stmt 0 view .LVU1662
+ 4858 0132 C3F8C010 		str	r1, [r3, #192]
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+ 4859              		.loc 6 1437 5 is_stmt 1 view .LVU1663
+ 4860 0136 C3F8C420 		str	r2, [r3, #196]
+ 4861              	.L175:
+ 4862              	.LVL353:
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+ 4863              		.loc 6 1437 5 is_stmt 0 view .LVU1664
+ 4864              	.LBE490:
+ 4865              	.LBE489:
+1531:Src/main.c    **** 	SD_SLIDE = 0;
+ 4866              		.loc 2 1531 2 is_stmt 1 view .LVU1665
+1531:Src/main.c    **** 	SD_SLIDE = 0;
+ 4867              		.loc 2 1531 10 is_stmt 0 view .LVU1666
+ 4868 013a 0024     		movs	r4, #0
+ 4869 013c 654B     		ldr	r3, .L182+92
+ 4870 013e 1C60     		str	r4, [r3]
+1532:Src/main.c    **** 	//Reset all periphery
+ 4871              		.loc 2 1532 2 is_stmt 1 view .LVU1667
+1532:Src/main.c    **** 	//Reset all periphery
+ 4872              		.loc 2 1532 11 is_stmt 0 view .LVU1668
+ 4873 0140 654B     		ldr	r3, .L182+96
+ 4874 0142 1C60     		str	r4, [r3]
+1534:Src/main.c    **** 	HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET);
+ 4875              		.loc 2 1534 2 is_stmt 1 view .LVU1669
+ 4876 0144 654F     		ldr	r7, .L182+100
+ 4877 0146 2246     		mov	r2, r4
+ 4878 0148 0821     		movs	r1, #8
+ 4879 014a 3846     		mov	r0, r7
+ARM GAS  /tmp/ccdsDELB.s 			page 435
+
+
+ 4880 014c FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4881              	.LVL354:
+1535:Src/main.c    **** 	HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET);
+ 4882              		.loc 2 1535 2 view .LVU1670
+ 4883 0150 2246     		mov	r2, r4
+ 4884 0152 0421     		movs	r1, #4
+ 4885 0154 3846     		mov	r0, r7
+ 4886 0156 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4887              	.LVL355:
+1536:Src/main.c    **** 	HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET);
+ 4888              		.loc 2 1536 2 view .LVU1671
+ 4889 015a DFF8A481 		ldr	r8, .L182+136
+ 4890 015e 2246     		mov	r2, r4
+ 4891 0160 4FF48071 		mov	r1, #256
+ 4892 0164 4046     		mov	r0, r8
+ 4893 0166 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4894              	.LVL356:
+1537:Src/main.c    **** 	HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET);
+ 4895              		.loc 2 1537 2 view .LVU1672
+ 4896 016a 2246     		mov	r2, r4
+ 4897 016c 1021     		movs	r1, #16
+ 4898 016e 3846     		mov	r0, r7
+ 4899 0170 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4900              	.LVL357:
+1538:Src/main.c    **** 	HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET);
+ 4901              		.loc 2 1538 2 view .LVU1673
+ 4902 0174 5A4E     		ldr	r6, .L182+104
+ 4903 0176 2246     		mov	r2, r4
+ 4904 0178 4FF48061 		mov	r1, #1024
+ 4905 017c 3046     		mov	r0, r6
+ 4906 017e FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4907              	.LVL358:
+1539:Src/main.c    **** 	HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET);
+ 4908              		.loc 2 1539 2 view .LVU1674
+ 4909 0182 584D     		ldr	r5, .L182+108
+ 4910 0184 2246     		mov	r2, r4
+ 4911 0186 0821     		movs	r1, #8
+ 4912 0188 2846     		mov	r0, r5
+ 4913 018a FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4914              	.LVL359:
+1540:Src/main.c    **** 	HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET);
+ 4915              		.loc 2 1540 2 view .LVU1675
+ 4916 018e 2246     		mov	r2, r4
+ 4917 0190 0121     		movs	r1, #1
+ 4918 0192 2846     		mov	r0, r5
+ 4919 0194 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4920              	.LVL360:
+1541:Src/main.c    **** 	HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET);
+ 4921              		.loc 2 1541 2 view .LVU1676
+ 4922 0198 2246     		mov	r2, r4
+ 4923 019a 0221     		movs	r1, #2
+ 4924 019c 2846     		mov	r0, r5
+ 4925 019e FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4926              	.LVL361:
+1542:Src/main.c    **** 	HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET);
+ 4927              		.loc 2 1542 2 view .LVU1677
+ 4928 01a2 2246     		mov	r2, r4
+ARM GAS  /tmp/ccdsDELB.s 			page 436
+
+
+ 4929 01a4 4FF40061 		mov	r1, #2048
+ 4930 01a8 3046     		mov	r0, r6
+ 4931 01aa FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4932              	.LVL362:
+1543:Src/main.c    **** //	for (uint16_t i = 0; i < SD_Length; i++)
+ 4933              		.loc 2 1543 2 view .LVU1678
+ 4934 01ae 2246     		mov	r2, r4
+ 4935 01b0 2021     		movs	r1, #32
+ 4936 01b2 3846     		mov	r0, r7
+ 4937 01b4 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4938              	.LVL363:
+1553:Src/main.c    **** 	HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET);//Enable SPI for MPhD2 ADC
+ 4939              		.loc 2 1553 2 view .LVU1679
+ 4940 01b8 07F50067 		add	r7, r7, #2048
+ 4941 01bc 0122     		movs	r2, #1
+ 4942 01be 4FF48061 		mov	r1, #1024
+ 4943 01c2 3846     		mov	r0, r7
+ 4944 01c4 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4945              	.LVL364:
+1554:Src/main.c    **** 	HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);
+ 4946              		.loc 2 1554 2 view .LVU1680
+ 4947 01c8 474C     		ldr	r4, .L182+112
+ 4948 01ca 0122     		movs	r2, #1
+ 4949 01cc 4021     		movs	r1, #64
+ 4950 01ce 2046     		mov	r0, r4
+ 4951 01d0 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4952              	.LVL365:
+1555:Src/main.c    **** 	HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);
+ 4953              		.loc 2 1555 2 view .LVU1681
+ 4954 01d4 0122     		movs	r2, #1
+ 4955 01d6 4FF48041 		mov	r1, #16384
+ 4956 01da 3846     		mov	r0, r7
+ 4957 01dc FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4958              	.LVL366:
+1556:Src/main.c    **** 	HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1
+ 4959              		.loc 2 1556 2 view .LVU1682
+ 4960 01e0 0122     		movs	r2, #1
+ 4961 01e2 4FF48041 		mov	r1, #16384
+ 4962 01e6 2046     		mov	r0, r4
+ 4963 01e8 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4964              	.LVL367:
+1557:Src/main.c    **** 	HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2
+ 4965              		.loc 2 1557 2 view .LVU1683
+ 4966 01ec 0122     		movs	r2, #1
+ 4967 01ee 4FF48041 		mov	r1, #16384
+ 4968 01f2 3046     		mov	r0, r6
+ 4969 01f4 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4970              	.LVL368:
+1558:Src/main.c    **** 	HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 
+ 4971              		.loc 2 1558 2 view .LVU1684
+ 4972 01f8 0122     		movs	r2, #1
+ 4973 01fa 4021     		movs	r1, #64
+ 4974 01fc 2846     		mov	r0, r5
+ 4975 01fe FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4976              	.LVL369:
+1559:Src/main.c    **** 	HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 
+ 4977              		.loc 2 1559 2 view .LVU1685
+ARM GAS  /tmp/ccdsDELB.s 			page 437
+
+
+ 4978 0202 0122     		movs	r2, #1
+ 4979 0204 4FF48051 		mov	r1, #4096
+ 4980 0208 3046     		mov	r0, r6
+ 4981 020a FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4982              	.LVL370:
+1560:Src/main.c    **** 	
+ 4983              		.loc 2 1560 2 view .LVU1686
+ 4984 020e 0122     		movs	r2, #1
+ 4985 0210 1021     		movs	r1, #16
+ 4986 0212 2846     		mov	r0, r5
+ 4987 0214 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 4988              	.LVL371:
+1564:Src/main.c    **** 	{
+ 4989              		.loc 2 1564 2 view .LVU1687
+1564:Src/main.c    **** 	{
+ 4990              		.loc 2 1564 6 is_stmt 0 view .LVU1688
+ 4991 0218 0121     		movs	r1, #1
+ 4992 021a 4046     		mov	r0, r8
+ 4993 021c FFF7FEFF 		bl	HAL_GPIO_ReadPin
+ 4994              	.LVL372:
+1564:Src/main.c    **** 	{
+ 4995              		.loc 2 1564 5 view .LVU1689
+ 4996 0220 38B1     		cbz	r0, .L180
+ 4997              	.L170:
+1594:Src/main.c    **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_
+ 4998              		.loc 2 1594 1 view .LVU1690
+ 4999 0222 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 5000              	.LVL373:
+ 5001              	.L179:
+ 5002              	.LBB492:
+ 5003              	.LBB491:
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR,
+ 5004              		.loc 6 1430 5 is_stmt 1 view .LVU1691
+ 5005 0226 284B     		ldr	r3, .L182+80
+ 5006              	.LVL374:
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR,
+ 5007              		.loc 6 1430 5 is_stmt 0 view .LVU1692
+ 5008 0228 C3F8C410 		str	r1, [r3, #196]
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+ 5009              		.loc 6 1431 5 is_stmt 1 view .LVU1693
+ 5010 022c C3F8C020 		str	r2, [r3, #192]
+ 5011 0230 83E7     		b	.L175
+ 5012              	.LVL375:
+ 5013              	.L180:
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+ 5014              		.loc 6 1431 5 is_stmt 0 view .LVU1694
+ 5015              	.LBE491:
+ 5016              	.LBE492:
+1567:Src/main.c    **** 		{
+ 5017              		.loc 2 1567 3 is_stmt 1 view .LVU1695
+1567:Src/main.c    **** 		{
+ 5018              		.loc 2 1567 7 is_stmt 0 view .LVU1696
+ 5019 0232 4FF48071 		mov	r1, #256
+ 5020 0236 2846     		mov	r0, r5
+ 5021 0238 FFF7FEFF 		bl	HAL_GPIO_ReadPin
+ 5022              	.LVL376:
+1567:Src/main.c    **** 		{
+ARM GAS  /tmp/ccdsDELB.s 			page 438
+
+
+ 5023              		.loc 2 1567 6 view .LVU1697
+ 5024 023c 0028     		cmp	r0, #0
+ 5025 023e F0D1     		bne	.L170
+1570:Src/main.c    **** 			if (test == 0) //0 - suc
+ 5026              		.loc 2 1570 4 is_stmt 1 view .LVU1698
+1570:Src/main.c    **** 			if (test == 0) //0 - suc
+ 5027              		.loc 2 1570 11 is_stmt 0 view .LVU1699
+ 5028 0240 2A48     		ldr	r0, .L182+116
+ 5029 0242 FFF7FEFF 		bl	Mount_SD
+ 5030              	.LVL377:
+1570:Src/main.c    **** 			if (test == 0) //0 - suc
+ 5031              		.loc 2 1570 9 view .LVU1700
+ 5032 0246 2A4B     		ldr	r3, .L182+120
+ 5033 0248 1860     		str	r0, [r3]
+1571:Src/main.c    **** 			{
+ 5034              		.loc 2 1571 4 is_stmt 1 view .LVU1701
+1571:Src/main.c    **** 			{
+ 5035              		.loc 2 1571 7 is_stmt 0 view .LVU1702
+ 5036 024a 18B1     		cbz	r0, .L181
+ 5037              	.L177:
+1583:Src/main.c    **** 		}
+ 5038              		.loc 2 1583 4 is_stmt 1 view .LVU1703
+1583:Src/main.c    **** 		}
+ 5039              		.loc 2 1583 14 is_stmt 0 view .LVU1704
+ 5040 024c 294B     		ldr	r3, .L182+124
+ 5041 024e 0122     		movs	r2, #1
+ 5042 0250 1A70     		strb	r2, [r3]
+1594:Src/main.c    **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_
+ 5043              		.loc 2 1594 1 view .LVU1705
+ 5044 0252 E6E7     		b	.L170
+ 5045              	.L181:
+1574:Src/main.c    **** 				test = Unmount_SD("/"); // 0 - succ
+ 5046              		.loc 2 1574 5 is_stmt 1 view .LVU1706
+1574:Src/main.c    **** 				test = Unmount_SD("/"); // 0 - succ
+ 5047              		.loc 2 1574 12 is_stmt 0 view .LVU1707
+ 5048 0254 1E23     		movs	r3, #30
+ 5049 0256 1A46     		mov	r2, r3
+ 5050 0258 2749     		ldr	r1, .L182+128
+ 5051 025a 2848     		ldr	r0, .L182+132
+ 5052 025c FFF7FEFF 		bl	Seek_Read_File
+ 5053              	.LVL378:
+1574:Src/main.c    **** 				test = Unmount_SD("/"); // 0 - succ
+ 5054              		.loc 2 1574 10 view .LVU1708
+ 5055 0260 234C     		ldr	r4, .L182+120
+ 5056 0262 2060     		str	r0, [r4]
+1575:Src/main.c    **** 				UART_rec_incr = 0;
+ 5057              		.loc 2 1575 5 is_stmt 1 view .LVU1709
+1575:Src/main.c    **** 				UART_rec_incr = 0;
+ 5058              		.loc 2 1575 12 is_stmt 0 view .LVU1710
+ 5059 0264 2148     		ldr	r0, .L182+116
+ 5060 0266 FFF7FEFF 		bl	Unmount_SD
+ 5061              	.LVL379:
+1575:Src/main.c    **** 				UART_rec_incr = 0;
+ 5062              		.loc 2 1575 10 view .LVU1711
+ 5063 026a 2060     		str	r0, [r4]
+1576:Src/main.c    **** 				flg_tmt = 0;//Reset the timeout flag
+ 5064              		.loc 2 1576 5 is_stmt 1 view .LVU1712
+ARM GAS  /tmp/ccdsDELB.s 			page 439
+
+
+1576:Src/main.c    **** 				flg_tmt = 0;//Reset the timeout flag
+ 5065              		.loc 2 1576 19 is_stmt 0 view .LVU1713
+ 5066 026c 0023     		movs	r3, #0
+ 5067 026e 084A     		ldr	r2, .L182+24
+ 5068 0270 1380     		strh	r3, [r2]	@ movhi
+1577:Src/main.c    **** 			}
+ 5069              		.loc 2 1577 5 is_stmt 1 view .LVU1714
+1577:Src/main.c    **** 			}
+ 5070              		.loc 2 1577 13 is_stmt 0 view .LVU1715
+ 5071 0272 064A     		ldr	r2, .L182+20
+ 5072 0274 1370     		strb	r3, [r2]
+ 5073 0276 E9E7     		b	.L177
+ 5074              	.L183:
+ 5075              		.align	2
+ 5076              	.L182:
+ 5077 0278 00000000 		.word	.LANCHOR7
+ 5078 027c 00000000 		.word	.LANCHOR3
+ 5079 0280 00000000 		.word	.LANCHOR8
+ 5080 0284 00000000 		.word	.LANCHOR9
+ 5081 0288 00000000 		.word	.LANCHOR10
+ 5082 028c 00000000 		.word	.LANCHOR11
+ 5083 0290 00000000 		.word	.LANCHOR12
+ 5084 0294 00000000 		.word	.LANCHOR13
+ 5085 0298 00000000 		.word	.LANCHOR14
+ 5086 029c 00000000 		.word	.LANCHOR15
+ 5087 02a0 00000000 		.word	.LANCHOR16
+ 5088 02a4 00000000 		.word	.LANCHOR6
+ 5089 02a8 00000000 		.word	.LANCHOR17
+ 5090 02ac 00000000 		.word	.LANCHOR18
+ 5091 02b0 00000000 		.word	.LANCHOR19
+ 5092 02b4 00000000 		.word	.LANCHOR20
+ 5093 02b8 00000000 		.word	.LANCHOR21
+ 5094 02bc 00000000 		.word	.LANCHOR22
+ 5095 02c0 00100040 		.word	1073745920
+ 5096 02c4 08100140 		.word	1073811464
+ 5097 02c8 00640240 		.word	1073898496
+ 5098 02cc 00000000 		.word	.LANCHOR23
+ 5099 02d0 28100140 		.word	1073811496
+ 5100 02d4 00000000 		.word	.LANCHOR24
+ 5101 02d8 00000000 		.word	.LANCHOR25
+ 5102 02dc 00080240 		.word	1073874944
+ 5103 02e0 00040240 		.word	1073873920
+ 5104 02e4 00000240 		.word	1073872896
+ 5105 02e8 00140240 		.word	1073878016
+ 5106 02ec 00000000 		.word	.LC0
+ 5107 02f0 00000000 		.word	.LANCHOR5
+ 5108 02f4 00000000 		.word	.LANCHOR27
+ 5109 02f8 00000000 		.word	.LANCHOR26
+ 5110 02fc 04000000 		.word	.LC1
+ 5111 0300 000C0240 		.word	1073875968
+ 5112              		.cfi_endproc
+ 5113              	.LFE1203:
+ 5115              		.section	.text.Get_ADC,"ax",%progbits
+ 5116              		.align	1
+ 5117              		.syntax unified
+ 5118              		.thumb
+ 5119              		.thumb_func
+ARM GAS  /tmp/ccdsDELB.s 			page 440
+
+
+ 5120              		.fpu fpv5-d16
+ 5122              	Get_ADC:
+ 5123              	.LVL380:
+ 5124              	.LFB1208:
+1965:Src/main.c    **** 	uint16_t OUT;
+ 5125              		.loc 2 1965 1 is_stmt 1 view -0
+ 5126              		.cfi_startproc
+ 5127              		@ args = 0, pretend = 0, frame = 0
+ 5128              		@ frame_needed = 0, uses_anonymous_args = 0
+1965:Src/main.c    **** 	uint16_t OUT;
+ 5129              		.loc 2 1965 1 is_stmt 0 view .LVU1717
+ 5130 0000 10B5     		push	{r4, lr}
+ 5131              	.LCFI39:
+ 5132              		.cfi_def_cfa_offset 8
+ 5133              		.cfi_offset 4, -8
+ 5134              		.cfi_offset 14, -4
+ 5135 0002 0024     		movs	r4, #0
+1966:Src/main.c    **** 	switch (num)
+ 5136              		.loc 2 1966 2 is_stmt 1 view .LVU1718
+1967:Src/main.c    **** 		{
+ 5137              		.loc 2 1967 2 view .LVU1719
+ 5138 0004 0528     		cmp	r0, #5
+ 5139 0006 2CD8     		bhi	.L193
+ 5140 0008 DFE800F0 		tbb	[pc, r0]
+ 5141              	.L187:
+ 5142 000c 03       		.byte	(.L192-.L187)/2
+ 5143 000d 08       		.byte	(.L191-.L187)/2
+ 5144 000e 12       		.byte	(.L190-.L187)/2
+ 5145 000f 17       		.byte	(.L189-.L187)/2
+ 5146 0010 1C       		.byte	(.L188-.L187)/2
+ 5147 0011 26       		.byte	(.L186-.L187)/2
+ 5148              		.p2align 1
+ 5149              	.L192:
+1970:Src/main.c    **** 			break;
+ 5150              		.loc 2 1970 5 view .LVU1720
+ 5151 0012 1548     		ldr	r0, .L195
+ 5152              	.LVL381:
+1970:Src/main.c    **** 			break;
+ 5153              		.loc 2 1970 5 is_stmt 0 view .LVU1721
+ 5154 0014 FFF7FEFF 		bl	HAL_ADC_Start
+ 5155              	.LVL382:
+1971:Src/main.c    **** 			case 1:
+ 5156              		.loc 2 1971 4 is_stmt 1 view .LVU1722
+ 5157 0018 2046     		mov	r0, r4
+ 5158              	.L185:
+ 5159              	.LVL383:
+1990:Src/main.c    **** }
+ 5160              		.loc 2 1990 2 view .LVU1723
+1991:Src/main.c    **** uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results, uin
+ 5161              		.loc 2 1991 1 is_stmt 0 view .LVU1724
+ 5162 001a 10BD     		pop	{r4, pc}
+ 5163              	.LVL384:
+ 5164              	.L191:
+1973:Src/main.c    ****         OUT = HAL_ADC_GetValue(&hadc1); // Get value adc
+ 5165              		.loc 2 1973 5 is_stmt 1 view .LVU1725
+ 5166 001c 124C     		ldr	r4, .L195
+ 5167 001e 6421     		movs	r1, #100
+ARM GAS  /tmp/ccdsDELB.s 			page 441
+
+
+ 5168 0020 2046     		mov	r0, r4
+ 5169              	.LVL385:
+1973:Src/main.c    ****         OUT = HAL_ADC_GetValue(&hadc1); // Get value adc
+ 5170              		.loc 2 1973 5 is_stmt 0 view .LVU1726
+ 5171 0022 FFF7FEFF 		bl	HAL_ADC_PollForConversion
+ 5172              	.LVL386:
+1974:Src/main.c    **** 			break;
+ 5173              		.loc 2 1974 9 is_stmt 1 view .LVU1727
+1974:Src/main.c    **** 			break;
+ 5174              		.loc 2 1974 15 is_stmt 0 view .LVU1728
+ 5175 0026 2046     		mov	r0, r4
+ 5176 0028 FFF7FEFF 		bl	HAL_ADC_GetValue
+ 5177              	.LVL387:
+1974:Src/main.c    **** 			break;
+ 5178              		.loc 2 1974 13 view .LVU1729
+ 5179 002c 80B2     		uxth	r0, r0
+ 5180              	.LVL388:
+1975:Src/main.c    **** 			case 2:
+ 5181              		.loc 2 1975 4 is_stmt 1 view .LVU1730
+ 5182 002e F4E7     		b	.L185
+ 5183              	.LVL389:
+ 5184              	.L190:
+1977:Src/main.c    **** 			break;
+ 5185              		.loc 2 1977 5 view .LVU1731
+ 5186 0030 0D48     		ldr	r0, .L195
+ 5187              	.LVL390:
+1977:Src/main.c    **** 			break;
+ 5188              		.loc 2 1977 5 is_stmt 0 view .LVU1732
+ 5189 0032 FFF7FEFF 		bl	HAL_ADC_Stop
+ 5190              	.LVL391:
+1978:Src/main.c    **** 			case 3:
+ 5191              		.loc 2 1978 4 is_stmt 1 view .LVU1733
+ 5192 0036 2046     		mov	r0, r4
+ 5193 0038 EFE7     		b	.L185
+ 5194              	.LVL392:
+ 5195              	.L189:
+1980:Src/main.c    **** 			break;
+ 5196              		.loc 2 1980 5 view .LVU1734
+ 5197 003a 0C48     		ldr	r0, .L195+4
+ 5198              	.LVL393:
+1980:Src/main.c    **** 			break;
+ 5199              		.loc 2 1980 5 is_stmt 0 view .LVU1735
+ 5200 003c FFF7FEFF 		bl	HAL_ADC_Start
+ 5201              	.LVL394:
+1981:Src/main.c    **** 			case 4:
+ 5202              		.loc 2 1981 4 is_stmt 1 view .LVU1736
+ 5203 0040 2046     		mov	r0, r4
+ 5204 0042 EAE7     		b	.L185
+ 5205              	.LVL395:
+ 5206              	.L188:
+1983:Src/main.c    ****         OUT = HAL_ADC_GetValue(&hadc3); // Get value adc
+ 5207              		.loc 2 1983 5 view .LVU1737
+ 5208 0044 094C     		ldr	r4, .L195+4
+ 5209 0046 6421     		movs	r1, #100
+ 5210 0048 2046     		mov	r0, r4
+ 5211              	.LVL396:
+1983:Src/main.c    ****         OUT = HAL_ADC_GetValue(&hadc3); // Get value adc
+ARM GAS  /tmp/ccdsDELB.s 			page 442
+
+
+ 5212              		.loc 2 1983 5 is_stmt 0 view .LVU1738
+ 5213 004a FFF7FEFF 		bl	HAL_ADC_PollForConversion
+ 5214              	.LVL397:
+1984:Src/main.c    **** 			break;
+ 5215              		.loc 2 1984 9 is_stmt 1 view .LVU1739
+1984:Src/main.c    **** 			break;
+ 5216              		.loc 2 1984 15 is_stmt 0 view .LVU1740
+ 5217 004e 2046     		mov	r0, r4
+ 5218 0050 FFF7FEFF 		bl	HAL_ADC_GetValue
+ 5219              	.LVL398:
+1984:Src/main.c    **** 			break;
+ 5220              		.loc 2 1984 13 view .LVU1741
+ 5221 0054 80B2     		uxth	r0, r0
+ 5222              	.LVL399:
+1985:Src/main.c    **** 			case 5:
+ 5223              		.loc 2 1985 4 is_stmt 1 view .LVU1742
+ 5224 0056 E0E7     		b	.L185
+ 5225              	.LVL400:
+ 5226              	.L186:
+1987:Src/main.c    **** 			break;
+ 5227              		.loc 2 1987 9 view .LVU1743
+ 5228 0058 0448     		ldr	r0, .L195+4
+ 5229              	.LVL401:
+1987:Src/main.c    **** 			break;
+ 5230              		.loc 2 1987 9 is_stmt 0 view .LVU1744
+ 5231 005a FFF7FEFF 		bl	HAL_ADC_Stop
+ 5232              	.LVL402:
+1988:Src/main.c    **** 		}
+ 5233              		.loc 2 1988 4 is_stmt 1 view .LVU1745
+ 5234 005e 2046     		mov	r0, r4
+ 5235 0060 DBE7     		b	.L185
+ 5236              	.LVL403:
+ 5237              	.L193:
+1967:Src/main.c    **** 		{
+ 5238              		.loc 2 1967 2 is_stmt 0 view .LVU1746
+ 5239 0062 2046     		mov	r0, r4
+ 5240              	.LVL404:
+1967:Src/main.c    **** 		{
+ 5241              		.loc 2 1967 2 view .LVU1747
+ 5242 0064 D9E7     		b	.L185
+ 5243              	.L196:
+ 5244 0066 00BF     		.align	2
+ 5245              	.L195:
+ 5246 0068 00000000 		.word	.LANCHOR28
+ 5247 006c 00000000 		.word	.LANCHOR29
+ 5248              		.cfi_endproc
+ 5249              	.LFE1208:
+ 5251              		.section	.text.Stop_TIM10,"ax",%progbits
+ 5252              		.align	1
+ 5253              		.syntax unified
+ 5254              		.thumb
+ 5255              		.thumb_func
+ 5256              		.fpu fpv5-d16
+ 5258              	Stop_TIM10:
+ 5259              	.LFB1217:
+2030:Src/main.c    **** uint8_t CheckChecksum(uint16_t *pbuff)
+2031:Src/main.c    **** {
+ARM GAS  /tmp/ccdsDELB.s 			page 443
+
+
+2032:Src/main.c    ****   uint16_t cl_ind;
+2033:Src/main.c    **** 
+2034:Src/main.c    ****   switch (UART_header)
+2035:Src/main.c    ****   {
+2036:Src/main.c    ****     case 0x7777:
+2037:Src/main.c    ****       cl_ind = TSK_16 - 2;
+2038:Src/main.c    ****     break;
+2039:Src/main.c    ****     case 0x1111:
+2040:Src/main.c    ****       cl_ind = CL_16 - 2;
+2041:Src/main.c    ****     break;
+2042:Src/main.c    ****     default:
+2043:Src/main.c    ****       return 0;
+2044:Src/main.c    ****     break;
+2045:Src/main.c    ****   }
+2046:Src/main.c    **** 
+2047:Src/main.c    ****   CS_result = CalculateChecksum(pbuff, cl_ind);
+2048:Src/main.c    **** 
+2049:Src/main.c    ****   return ((CS_result == COMMAND[cl_ind]) ? 1 : 0);
+2050:Src/main.c    **** }
+2051:Src/main.c    **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len)
+2052:Src/main.c    **** {
+2053:Src/main.c    **** 	short  i;
+2054:Src/main.c    **** 	uint16_t cs = *pbuff;
+2055:Src/main.c    ****   
+2056:Src/main.c    ****  	for(i = 1; i < len; i++)
+2057:Src/main.c    **** 	{
+2058:Src/main.c    **** 		cs ^= *(pbuff+i);
+2059:Src/main.c    **** 	}
+2060:Src/main.c    **** 	return cs;
+2061:Src/main.c    **** }
+2062:Src/main.c    **** 
+2063:Src/main.c    **** /*int SD_Init(void)
+2064:Src/main.c    **** {
+2065:Src/main.c    **** 	int test=0;
+2066:Src/main.c    **** 	if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET)
+2067:Src/main.c    **** 	{
+2068:Src/main.c    **** 		test = Mount_SD("/");
+2069:Src/main.c    **** 		if (test == 0) //0 - suc
+2070:Src/main.c    **** 		{
+2071:Src/main.c    **** 			//Format_SD();
+2072:Src/main.c    **** 			test = Create_File("FILE1.TXT"); // 0 -suc
+2073:Src/main.c    **** 			//Create_File("FILE2.TXT");
+2074:Src/main.c    **** 			Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Viktor. Part 
+2075:Src/main.c    **** 			test = Unmount_SD("/"); // 0 - succ
+2076:Src/main.c    **** 			return test;
+2077:Src/main.c    **** 		}
+2078:Src/main.c    **** 		else
+2079:Src/main.c    **** 		{
+2080:Src/main.c    **** 			return 1;
+2081:Src/main.c    **** 		}
+2082:Src/main.c    **** 	}
+2083:Src/main.c    **** 	else
+2084:Src/main.c    **** 	{
+2085:Src/main.c    **** 		return 1;
+2086:Src/main.c    **** 	}
+2087:Src/main.c    **** }*/
+2088:Src/main.c    **** 
+ARM GAS  /tmp/ccdsDELB.s 			page 444
+
+
+2089:Src/main.c    **** int SD_SAVE(uint16_t *pbuff)
+2090:Src/main.c    **** {
+2091:Src/main.c    **** 	int test=0;
+2092:Src/main.c    **** 	if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET)
+2093:Src/main.c    **** 	{
+2094:Src/main.c    **** 		test = Mount_SD("/");
+2095:Src/main.c    **** 		if (test == 0) //0 - suc
+2096:Src/main.c    **** 		{
+2097:Src/main.c    **** 			//Format_SD();
+2098:Src/main.c    **** 			test = Update_File_byte("FILE1.TXT", (uint8_t *)pbuff, DL_8);
+2099:Src/main.c    **** 			test = Unmount_SD("/"); // 0 - succ
+2100:Src/main.c    **** 			return test;
+2101:Src/main.c    **** 		}
+2102:Src/main.c    **** 		else
+2103:Src/main.c    **** 		{
+2104:Src/main.c    **** 			return 1;
+2105:Src/main.c    **** 		}
+2106:Src/main.c    **** 	}
+2107:Src/main.c    **** 	else
+2108:Src/main.c    **** 	{
+2109:Src/main.c    **** 		return 1;
+2110:Src/main.c    **** 	}
+2111:Src/main.c    **** }
+2112:Src/main.c    **** 
+2113:Src/main.c    **** 
+2114:Src/main.c    **** 
+2115:Src/main.c    **** //uint32_t Get_Length(void)
+2116:Src/main.c    **** //{
+2117:Src/main.c    **** //	return SD_matr[0][0] + ((uint32_t) (SD_matr[0][1])<<16);
+2118:Src/main.c    **** //}
+2119:Src/main.c    **** 
+2120:Src/main.c    **** int SD_READ(uint16_t *pbuff)
+2121:Src/main.c    **** {
+2122:Src/main.c    **** 	int test=0;
+2123:Src/main.c    **** 	if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET)
+2124:Src/main.c    **** 	{
+2125:Src/main.c    **** 		test = Mount_SD("/");
+2126:Src/main.c    **** 		if (test == 0) //0 - suc
+2127:Src/main.c    **** 		{
+2128:Src/main.c    **** 			//Format_SD();
+2129:Src/main.c    **** 			test = Seek_Read_File ("FILE1.TXT", (uint8_t *)pbuff, DL_8, fgoto);//Read next 246 bytes
+2130:Src/main.c    **** 			fgoto+=DL_8;
+2131:Src/main.c    **** 			test = Unmount_SD("/"); // 0 - succ
+2132:Src/main.c    **** 			return test;
+2133:Src/main.c    **** 		}
+2134:Src/main.c    **** 		else
+2135:Src/main.c    **** 		{
+2136:Src/main.c    **** 			return 1;
+2137:Src/main.c    **** 		}
+2138:Src/main.c    **** 	}
+2139:Src/main.c    **** 	else
+2140:Src/main.c    **** 	{
+2141:Src/main.c    **** 		return 1;
+2142:Src/main.c    **** 	}
+2143:Src/main.c    **** 	
+2144:Src/main.c    **** /*	for (uint16_t j = 0; j < DL_16; j++)
+2145:Src/main.c    **** 	{
+ARM GAS  /tmp/ccdsDELB.s 			page 445
+
+
+2146:Src/main.c    **** 		*(pbuff+j) = SD_matr[SD_SLIDE][j];
+2147:Src/main.c    **** 	}
+2148:Src/main.c    **** 	if (SD_SLIDERDR, USART_RDR_RDR) & 0xFFU);
+3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RDR          RDR           LL_USART_ReceiveData9
+3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
+3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll TDR          TDR           LL_USART_TransmitData8
+3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ARM GAS  /tmp/ccdsDELB.s 			page 457
+
+
+3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+ 5738              		.loc 7 3681 22 view .LVU1870
+ 5739              	.LBB496:
+3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   USARTx->TDR = Value;
+ 5740              		.loc 7 3683 3 view .LVU1871
+ 5741              		.loc 7 3683 15 is_stmt 0 view .LVU1872
+ 5742 0014 044A     		ldr	r2, .L246
+ 5743 0016 9462     		str	r4, [r2, #40]
+ 5744              	.LVL458:
+ 5745              		.loc 7 3683 15 view .LVU1873
+ 5746              	.LBE496:
+ 5747              	.LBE495:
+2192:Src/main.c    ****   }
+ 5748              		.loc 2 2192 5 is_stmt 1 view .LVU1874
+2192:Src/main.c    ****   }
+ 5749              		.loc 2 2192 8 is_stmt 0 view .LVU1875
+ 5750 0018 0133     		adds	r3, r3, #1
+ 5751              	.LVL459:
+2192:Src/main.c    ****   }
+ 5752              		.loc 2 2192 8 view .LVU1876
+ 5753 001a 9BB2     		uxth	r3, r3
+ 5754              	.LVL460:
+2188:Src/main.c    ****   {
+ 5755              		.loc 2 2188 9 is_stmt 1 view .LVU1877
+ 5756 001c 8B42     		cmp	r3, r1
+ 5757 001e F3D3     		bcc	.L241
+2194:Src/main.c    **** 
+ 5758              		.loc 2 2194 1 is_stmt 0 view .LVU1878
+ 5759 0020 5DF8044B 		ldr	r4, [sp], #4
+ 5760              	.LCFI46:
+ 5761              		.cfi_restore 4
+ 5762              		.cfi_def_cfa_offset 0
+ 5763 0024 7047     		bx	lr
+ 5764              	.L245:
+2194:Src/main.c    **** 
+ 5765              		.loc 2 2194 1 view .LVU1879
+ 5766 0026 7047     		bx	lr
+ 5767              	.L247:
+ 5768              		.align	2
+ 5769              	.L246:
+ 5770 0028 00100140 		.word	1073811456
+ 5771              		.cfi_endproc
+ 5772              	.LFE1215:
+ 5774              		.section	.text.USART_TX_DMA,"ax",%progbits
+ 5775              		.align	1
+ 5776              		.global	USART_TX_DMA
+ 5777              		.syntax unified
+ 5778              		.thumb
+ 5779              		.thumb_func
+ 5780              		.fpu fpv5-d16
+ 5782              	USART_TX_DMA:
+ 5783              	.LFB1216:
+2197:Src/main.c    **** 	while (u_tx_flg) {}//Wait until previous transfer not complete. u_tx_flg is resetting in DMA inter
+ARM GAS  /tmp/ccdsDELB.s 			page 458
+
+
+ 5784              		.loc 2 2197 1 is_stmt 1 view -0
+ 5785              		.cfi_startproc
+ 5786              		@ args = 0, pretend = 0, frame = 0
+ 5787              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5788              		@ link register save eliminated.
+ 5789              	.LVL461:
+ 5790              	.L249:
+2198:Src/main.c    **** 	LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7);
+ 5791              		.loc 2 2198 20 discriminator 1 view .LVU1881
+2198:Src/main.c    **** 	LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7);
+ 5792              		.loc 2 2198 8 discriminator 1 view .LVU1882
+2198:Src/main.c    **** 	LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7);
+ 5793              		.loc 2 2198 9 is_stmt 0 discriminator 1 view .LVU1883
+ 5794 0000 0D4B     		ldr	r3, .L250
+ 5795 0002 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+2198:Src/main.c    **** 	LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7);
+ 5796              		.loc 2 2198 8 discriminator 1 view .LVU1884
+ 5797 0004 002B     		cmp	r3, #0
+ 5798 0006 FBD1     		bne	.L249
+2199:Src/main.c    ****   LL_DMA_SetDataLength(DMA2, LL_DMA_STREAM_7, sz);
+ 5799              		.loc 2 2199 2 is_stmt 1 view .LVU1885
+ 5800              	.LVL462:
+ 5801              	.LBB497:
+ 5802              	.LBI497:
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 5803              		.loc 6 517 22 view .LVU1886
+ 5804              	.LBB498:
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 5805              		.loc 6 519 3 view .LVU1887
+ 5806 0008 0C4B     		ldr	r3, .L250+4
+ 5807 000a D3F8B820 		ldr	r2, [r3, #184]
+ 5808 000e 22F00102 		bic	r2, r2, #1
+ 5809 0012 C3F8B820 		str	r2, [r3, #184]
+ 5810              	.LVL463:
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 5811              		.loc 6 519 3 is_stmt 0 view .LVU1888
+ 5812              	.LBE498:
+ 5813              	.LBE497:
+2200:Src/main.c    ****   LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_7);
+ 5814              		.loc 2 2200 3 is_stmt 1 view .LVU1889
+ 5815              	.LBB499:
+ 5816              	.LBI499:
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 5817              		.loc 6 971 22 view .LVU1890
+ 5818              	.LBB500:
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 5819              		.loc 6 973 3 view .LVU1891
+ 5820 0016 D3F8BC10 		ldr	r1, [r3, #188]
+ 5821 001a 094A     		ldr	r2, .L250+8
+ 5822 001c 0A40     		ands	r2, r2, r1
+ 5823 001e 1043     		orrs	r0, r0, r2
+ 5824              	.LVL464:
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 5825              		.loc 6 973 3 is_stmt 0 view .LVU1892
+ 5826 0020 C3F8BC00 		str	r0, [r3, #188]
+ 5827              	.LVL465:
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ARM GAS  /tmp/ccdsDELB.s 			page 459
+
+
+ 5828              		.loc 6 973 3 view .LVU1893
+ 5829              	.LBE500:
+ 5830              	.LBE499:
+2201:Src/main.c    **** 	u_tx_flg = 1;//indicate that transfer begin
+ 5831              		.loc 2 2201 3 is_stmt 1 view .LVU1894
+ 5832              	.LBB501:
+ 5833              	.LBI501:
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 5834              		.loc 6 497 22 view .LVU1895
+ 5835              	.LBB502:
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 5836              		.loc 6 499 3 view .LVU1896
+ 5837 0024 D3F8B820 		ldr	r2, [r3, #184]
+ 5838 0028 42F00102 		orr	r2, r2, #1
+ 5839 002c C3F8B820 		str	r2, [r3, #184]
+ 5840              	.LVL466:
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 5841              		.loc 6 499 3 is_stmt 0 view .LVU1897
+ 5842              	.LBE502:
+ 5843              	.LBE501:
+2202:Src/main.c    **** }
+ 5844              		.loc 2 2202 2 is_stmt 1 view .LVU1898
+2202:Src/main.c    **** }
+ 5845              		.loc 2 2202 11 is_stmt 0 view .LVU1899
+ 5846 0030 014B     		ldr	r3, .L250
+ 5847 0032 0122     		movs	r2, #1
+ 5848 0034 1A70     		strb	r2, [r3]
+2203:Src/main.c    **** 
+ 5849              		.loc 2 2203 1 view .LVU1900
+ 5850 0036 7047     		bx	lr
+ 5851              	.L251:
+ 5852              		.align	2
+ 5853              	.L250:
+ 5854 0038 00000000 		.word	.LANCHOR15
+ 5855 003c 00640240 		.word	1073898496
+ 5856 0040 0000FFFF 		.word	-65536
+ 5857              		.cfi_endproc
+ 5858              	.LFE1216:
+ 5860              		.section	.text.Error_Handler,"ax",%progbits
+ 5861              		.align	1
+ 5862              		.global	Error_Handler
+ 5863              		.syntax unified
+ 5864              		.thumb
+ 5865              		.thumb_func
+ 5866              		.fpu fpv5-d16
+ 5868              	Error_Handler:
+ 5869              	.LFB1218:
+2211:Src/main.c    **** //-------------------------------------------------------
+2212:Src/main.c    **** /* USER CODE END 4 */
+2213:Src/main.c    **** 
+2214:Src/main.c    **** /**
+2215:Src/main.c    ****   * @brief  This function is executed in case of error occurrence.
+2216:Src/main.c    ****   * @retval None
+2217:Src/main.c    ****   */
+2218:Src/main.c    **** void Error_Handler(void)
+2219:Src/main.c    **** {
+ 5870              		.loc 2 2219 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccdsDELB.s 			page 460
+
+
+ 5871              		.cfi_startproc
+ 5872              		@ Volatile: function does not return.
+ 5873              		@ args = 0, pretend = 0, frame = 0
+ 5874              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5875              		@ link register save eliminated.
+2220:Src/main.c    ****   /* USER CODE BEGIN Error_Handler_Debug */
+2221:Src/main.c    ****   /* User can add his own implementation to report the HAL error return state */
+2222:Src/main.c    ****   __disable_irq();
+ 5876              		.loc 2 2222 3 view .LVU1902
+ 5877              	.LBB503:
+ 5878              	.LBI503:
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 5879              		.loc 8 140 27 view .LVU1903
+ 5880              	.LBB504:
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 5881              		.loc 8 142 3 view .LVU1904
+ 5882              		.syntax unified
+ 5883              	@ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 5884 0000 72B6     		cpsid i
+ 5885              	@ 0 "" 2
+ 5886              		.thumb
+ 5887              		.syntax unified
+ 5888              	.L253:
+ 5889              	.LBE504:
+ 5890              	.LBE503:
+2223:Src/main.c    ****   while (1)
+ 5891              		.loc 2 2223 3 discriminator 1 view .LVU1905
+2224:Src/main.c    ****   {
+2225:Src/main.c    ****   }
+ 5892              		.loc 2 2225 3 discriminator 1 view .LVU1906
+2223:Src/main.c    ****   while (1)
+ 5893              		.loc 2 2223 9 discriminator 1 view .LVU1907
+ 5894 0002 FEE7     		b	.L253
+ 5895              		.cfi_endproc
+ 5896              	.LFE1218:
+ 5898              		.section	.text.MX_ADC1_Init,"ax",%progbits
+ 5899              		.align	1
+ 5900              		.syntax unified
+ 5901              		.thumb
+ 5902              		.thumb_func
+ 5903              		.fpu fpv5-d16
+ 5905              	MX_ADC1_Init:
+ 5906              	.LFB1188:
+ 605:Src/main.c    **** 
+ 5907              		.loc 2 605 1 view -0
+ 5908              		.cfi_startproc
+ 5909              		@ args = 0, pretend = 0, frame = 16
+ 5910              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5911 0000 00B5     		push	{lr}
+ 5912              	.LCFI47:
+ 5913              		.cfi_def_cfa_offset 4
+ 5914              		.cfi_offset 14, -4
+ 5915 0002 85B0     		sub	sp, sp, #20
+ 5916              	.LCFI48:
+ 5917              		.cfi_def_cfa_offset 24
+ 611:Src/main.c    **** 
+ 5918              		.loc 2 611 3 view .LVU1909
+ARM GAS  /tmp/ccdsDELB.s 			page 461
+
+
+ 611:Src/main.c    **** 
+ 5919              		.loc 2 611 26 is_stmt 0 view .LVU1910
+ 5920 0004 0023     		movs	r3, #0
+ 5921 0006 0093     		str	r3, [sp]
+ 5922 0008 0193     		str	r3, [sp, #4]
+ 5923 000a 0293     		str	r3, [sp, #8]
+ 5924 000c 0393     		str	r3, [sp, #12]
+ 619:Src/main.c    ****   hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8;
+ 5925              		.loc 2 619 3 is_stmt 1 view .LVU1911
+ 619:Src/main.c    ****   hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8;
+ 5926              		.loc 2 619 18 is_stmt 0 view .LVU1912
+ 5927 000e 2B48     		ldr	r0, .L268
+ 5928 0010 2B4A     		ldr	r2, .L268+4
+ 5929 0012 0260     		str	r2, [r0]
+ 620:Src/main.c    ****   hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+ 5930              		.loc 2 620 3 is_stmt 1 view .LVU1913
+ 620:Src/main.c    ****   hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+ 5931              		.loc 2 620 29 is_stmt 0 view .LVU1914
+ 5932 0014 4FF44032 		mov	r2, #196608
+ 5933 0018 4260     		str	r2, [r0, #4]
+ 621:Src/main.c    ****   hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
+ 5934              		.loc 2 621 3 is_stmt 1 view .LVU1915
+ 621:Src/main.c    ****   hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
+ 5935              		.loc 2 621 25 is_stmt 0 view .LVU1916
+ 5936 001a 8360     		str	r3, [r0, #8]
+ 622:Src/main.c    ****   hadc1.Init.ContinuousConvMode = DISABLE;
+ 5937              		.loc 2 622 3 is_stmt 1 view .LVU1917
+ 622:Src/main.c    ****   hadc1.Init.ContinuousConvMode = DISABLE;
+ 5938              		.loc 2 622 27 is_stmt 0 view .LVU1918
+ 5939 001c 0122     		movs	r2, #1
+ 5940 001e 0261     		str	r2, [r0, #16]
+ 623:Src/main.c    ****   hadc1.Init.DiscontinuousConvMode = DISABLE;
+ 5941              		.loc 2 623 3 is_stmt 1 view .LVU1919
+ 623:Src/main.c    ****   hadc1.Init.DiscontinuousConvMode = DISABLE;
+ 5942              		.loc 2 623 33 is_stmt 0 view .LVU1920
+ 5943 0020 8361     		str	r3, [r0, #24]
+ 624:Src/main.c    ****   hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 5944              		.loc 2 624 3 is_stmt 1 view .LVU1921
+ 624:Src/main.c    ****   hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 5945              		.loc 2 624 36 is_stmt 0 view .LVU1922
+ 5946 0022 80F82030 		strb	r3, [r0, #32]
+ 625:Src/main.c    ****   hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 5947              		.loc 2 625 3 is_stmt 1 view .LVU1923
+ 625:Src/main.c    ****   hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 5948              		.loc 2 625 35 is_stmt 0 view .LVU1924
+ 5949 0026 C362     		str	r3, [r0, #44]
+ 626:Src/main.c    ****   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 5950              		.loc 2 626 3 is_stmt 1 view .LVU1925
+ 626:Src/main.c    ****   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 5951              		.loc 2 626 31 is_stmt 0 view .LVU1926
+ 5952 0028 2649     		ldr	r1, .L268+8
+ 5953 002a 8162     		str	r1, [r0, #40]
+ 627:Src/main.c    ****   hadc1.Init.NbrOfConversion = 5;
+ 5954              		.loc 2 627 3 is_stmt 1 view .LVU1927
+ 627:Src/main.c    ****   hadc1.Init.NbrOfConversion = 5;
+ 5955              		.loc 2 627 24 is_stmt 0 view .LVU1928
+ 5956 002c C360     		str	r3, [r0, #12]
+ARM GAS  /tmp/ccdsDELB.s 			page 462
+
+
+ 628:Src/main.c    ****   hadc1.Init.DMAContinuousRequests = DISABLE;
+ 5957              		.loc 2 628 3 is_stmt 1 view .LVU1929
+ 628:Src/main.c    ****   hadc1.Init.DMAContinuousRequests = DISABLE;
+ 5958              		.loc 2 628 30 is_stmt 0 view .LVU1930
+ 5959 002e 0521     		movs	r1, #5
+ 5960 0030 C161     		str	r1, [r0, #28]
+ 629:Src/main.c    ****   hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 5961              		.loc 2 629 3 is_stmt 1 view .LVU1931
+ 629:Src/main.c    ****   hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 5962              		.loc 2 629 36 is_stmt 0 view .LVU1932
+ 5963 0032 80F83030 		strb	r3, [r0, #48]
+ 630:Src/main.c    ****   if (HAL_ADC_Init(&hadc1) != HAL_OK)
+ 5964              		.loc 2 630 3 is_stmt 1 view .LVU1933
+ 630:Src/main.c    ****   if (HAL_ADC_Init(&hadc1) != HAL_OK)
+ 5965              		.loc 2 630 27 is_stmt 0 view .LVU1934
+ 5966 0036 4261     		str	r2, [r0, #20]
+ 631:Src/main.c    ****   {
+ 5967              		.loc 2 631 3 is_stmt 1 view .LVU1935
+ 631:Src/main.c    ****   {
+ 5968              		.loc 2 631 7 is_stmt 0 view .LVU1936
+ 5969 0038 FFF7FEFF 		bl	HAL_ADC_Init
+ 5970              	.LVL467:
+ 631:Src/main.c    ****   {
+ 5971              		.loc 2 631 6 view .LVU1937
+ 5972 003c 0028     		cmp	r0, #0
+ 5973 003e 31D1     		bne	.L262
+ 638:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 5974              		.loc 2 638 3 is_stmt 1 view .LVU1938
+ 638:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 5975              		.loc 2 638 19 is_stmt 0 view .LVU1939
+ 5976 0040 0923     		movs	r3, #9
+ 5977 0042 0093     		str	r3, [sp]
+ 639:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
+ 5978              		.loc 2 639 3 is_stmt 1 view .LVU1940
+ 639:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
+ 5979              		.loc 2 639 16 is_stmt 0 view .LVU1941
+ 5980 0044 0123     		movs	r3, #1
+ 5981 0046 0193     		str	r3, [sp, #4]
+ 640:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 5982              		.loc 2 640 3 is_stmt 1 view .LVU1942
+ 640:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 5983              		.loc 2 640 24 is_stmt 0 view .LVU1943
+ 5984 0048 0723     		movs	r3, #7
+ 5985 004a 0293     		str	r3, [sp, #8]
+ 641:Src/main.c    ****   {
+ 5986              		.loc 2 641 3 is_stmt 1 view .LVU1944
+ 641:Src/main.c    ****   {
+ 5987              		.loc 2 641 7 is_stmt 0 view .LVU1945
+ 5988 004c 6946     		mov	r1, sp
+ 5989 004e 1B48     		ldr	r0, .L268
+ 5990 0050 FFF7FEFF 		bl	HAL_ADC_ConfigChannel
+ 5991              	.LVL468:
+ 641:Src/main.c    ****   {
+ 5992              		.loc 2 641 6 view .LVU1946
+ 5993 0054 40BB     		cbnz	r0, .L263
+ 648:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_2;
+ 5994              		.loc 2 648 3 is_stmt 1 view .LVU1947
+ARM GAS  /tmp/ccdsDELB.s 			page 463
+
+
+ 648:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_2;
+ 5995              		.loc 2 648 19 is_stmt 0 view .LVU1948
+ 5996 0056 0823     		movs	r3, #8
+ 5997 0058 0093     		str	r3, [sp]
+ 649:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 5998              		.loc 2 649 3 is_stmt 1 view .LVU1949
+ 649:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 5999              		.loc 2 649 16 is_stmt 0 view .LVU1950
+ 6000 005a 0223     		movs	r3, #2
+ 6001 005c 0193     		str	r3, [sp, #4]
+ 650:Src/main.c    ****   {
+ 6002              		.loc 2 650 3 is_stmt 1 view .LVU1951
+ 650:Src/main.c    ****   {
+ 6003              		.loc 2 650 7 is_stmt 0 view .LVU1952
+ 6004 005e 6946     		mov	r1, sp
+ 6005 0060 1648     		ldr	r0, .L268
+ 6006 0062 FFF7FEFF 		bl	HAL_ADC_ConfigChannel
+ 6007              	.LVL469:
+ 650:Src/main.c    ****   {
+ 6008              		.loc 2 650 6 view .LVU1953
+ 6009 0066 08BB     		cbnz	r0, .L264
+ 657:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_3;
+ 6010              		.loc 2 657 3 is_stmt 1 view .LVU1954
+ 657:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_3;
+ 6011              		.loc 2 657 19 is_stmt 0 view .LVU1955
+ 6012 0068 0223     		movs	r3, #2
+ 6013 006a 0093     		str	r3, [sp]
+ 658:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 6014              		.loc 2 658 3 is_stmt 1 view .LVU1956
+ 658:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 6015              		.loc 2 658 16 is_stmt 0 view .LVU1957
+ 6016 006c 0323     		movs	r3, #3
+ 6017 006e 0193     		str	r3, [sp, #4]
+ 659:Src/main.c    ****   {
+ 6018              		.loc 2 659 3 is_stmt 1 view .LVU1958
+ 659:Src/main.c    ****   {
+ 6019              		.loc 2 659 7 is_stmt 0 view .LVU1959
+ 6020 0070 6946     		mov	r1, sp
+ 6021 0072 1248     		ldr	r0, .L268
+ 6022 0074 FFF7FEFF 		bl	HAL_ADC_ConfigChannel
+ 6023              	.LVL470:
+ 659:Src/main.c    ****   {
+ 6024              		.loc 2 659 6 view .LVU1960
+ 6025 0078 D0B9     		cbnz	r0, .L265
+ 666:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_4;
+ 6026              		.loc 2 666 3 is_stmt 1 view .LVU1961
+ 666:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_4;
+ 6027              		.loc 2 666 19 is_stmt 0 view .LVU1962
+ 6028 007a 0A23     		movs	r3, #10
+ 6029 007c 0093     		str	r3, [sp]
+ 667:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 6030              		.loc 2 667 3 is_stmt 1 view .LVU1963
+ 667:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 6031              		.loc 2 667 16 is_stmt 0 view .LVU1964
+ 6032 007e 0423     		movs	r3, #4
+ 6033 0080 0193     		str	r3, [sp, #4]
+ 668:Src/main.c    ****   {
+ARM GAS  /tmp/ccdsDELB.s 			page 464
+
+
+ 6034              		.loc 2 668 3 is_stmt 1 view .LVU1965
+ 668:Src/main.c    ****   {
+ 6035              		.loc 2 668 7 is_stmt 0 view .LVU1966
+ 6036 0082 6946     		mov	r1, sp
+ 6037 0084 0D48     		ldr	r0, .L268
+ 6038 0086 FFF7FEFF 		bl	HAL_ADC_ConfigChannel
+ 6039              	.LVL471:
+ 668:Src/main.c    ****   {
+ 6040              		.loc 2 668 6 view .LVU1967
+ 6041 008a 98B9     		cbnz	r0, .L266
+ 675:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_5;
+ 6042              		.loc 2 675 3 is_stmt 1 view .LVU1968
+ 675:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_5;
+ 6043              		.loc 2 675 19 is_stmt 0 view .LVU1969
+ 6044 008c 0B23     		movs	r3, #11
+ 6045 008e 0093     		str	r3, [sp]
+ 676:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 6046              		.loc 2 676 3 is_stmt 1 view .LVU1970
+ 676:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 6047              		.loc 2 676 16 is_stmt 0 view .LVU1971
+ 6048 0090 0523     		movs	r3, #5
+ 6049 0092 0193     		str	r3, [sp, #4]
+ 677:Src/main.c    ****   {
+ 6050              		.loc 2 677 3 is_stmt 1 view .LVU1972
+ 677:Src/main.c    ****   {
+ 6051              		.loc 2 677 7 is_stmt 0 view .LVU1973
+ 6052 0094 6946     		mov	r1, sp
+ 6053 0096 0948     		ldr	r0, .L268
+ 6054 0098 FFF7FEFF 		bl	HAL_ADC_ConfigChannel
+ 6055              	.LVL472:
+ 677:Src/main.c    ****   {
+ 6056              		.loc 2 677 6 view .LVU1974
+ 6057 009c 60B9     		cbnz	r0, .L267
+ 685:Src/main.c    **** 
+ 6058              		.loc 2 685 1 view .LVU1975
+ 6059 009e 05B0     		add	sp, sp, #20
+ 6060              	.LCFI49:
+ 6061              		.cfi_remember_state
+ 6062              		.cfi_def_cfa_offset 4
+ 6063              		@ sp needed
+ 6064 00a0 5DF804FB 		ldr	pc, [sp], #4
+ 6065              	.L262:
+ 6066              	.LCFI50:
+ 6067              		.cfi_restore_state
+ 633:Src/main.c    ****   }
+ 6068              		.loc 2 633 5 is_stmt 1 view .LVU1976
+ 6069 00a4 FFF7FEFF 		bl	Error_Handler
+ 6070              	.LVL473:
+ 6071              	.L263:
+ 643:Src/main.c    ****   }
+ 6072              		.loc 2 643 5 view .LVU1977
+ 6073 00a8 FFF7FEFF 		bl	Error_Handler
+ 6074              	.LVL474:
+ 6075              	.L264:
+ 652:Src/main.c    ****   }
+ 6076              		.loc 2 652 5 view .LVU1978
+ 6077 00ac FFF7FEFF 		bl	Error_Handler
+ARM GAS  /tmp/ccdsDELB.s 			page 465
+
+
+ 6078              	.LVL475:
+ 6079              	.L265:
+ 661:Src/main.c    ****   }
+ 6080              		.loc 2 661 5 view .LVU1979
+ 6081 00b0 FFF7FEFF 		bl	Error_Handler
+ 6082              	.LVL476:
+ 6083              	.L266:
+ 670:Src/main.c    ****   }
+ 6084              		.loc 2 670 5 view .LVU1980
+ 6085 00b4 FFF7FEFF 		bl	Error_Handler
+ 6086              	.LVL477:
+ 6087              	.L267:
+ 679:Src/main.c    ****   }
+ 6088              		.loc 2 679 5 view .LVU1981
+ 6089 00b8 FFF7FEFF 		bl	Error_Handler
+ 6090              	.LVL478:
+ 6091              	.L269:
+ 6092              		.align	2
+ 6093              	.L268:
+ 6094 00bc 00000000 		.word	.LANCHOR28
+ 6095 00c0 00200140 		.word	1073815552
+ 6096 00c4 0100000F 		.word	251658241
+ 6097              		.cfi_endproc
+ 6098              	.LFE1188:
+ 6100              		.section	.text.MX_ADC3_Init,"ax",%progbits
+ 6101              		.align	1
+ 6102              		.syntax unified
+ 6103              		.thumb
+ 6104              		.thumb_func
+ 6105              		.fpu fpv5-d16
+ 6107              	MX_ADC3_Init:
+ 6108              	.LFB1189:
+ 693:Src/main.c    **** 
+ 6109              		.loc 2 693 1 view -0
+ 6110              		.cfi_startproc
+ 6111              		@ args = 0, pretend = 0, frame = 16
+ 6112              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6113 0000 00B5     		push	{lr}
+ 6114              	.LCFI51:
+ 6115              		.cfi_def_cfa_offset 4
+ 6116              		.cfi_offset 14, -4
+ 6117 0002 85B0     		sub	sp, sp, #20
+ 6118              	.LCFI52:
+ 6119              		.cfi_def_cfa_offset 24
+ 699:Src/main.c    **** 
+ 6120              		.loc 2 699 3 view .LVU1983
+ 699:Src/main.c    **** 
+ 6121              		.loc 2 699 26 is_stmt 0 view .LVU1984
+ 6122 0004 0023     		movs	r3, #0
+ 6123 0006 0093     		str	r3, [sp]
+ 6124 0008 0193     		str	r3, [sp, #4]
+ 6125 000a 0293     		str	r3, [sp, #8]
+ 6126 000c 0393     		str	r3, [sp, #12]
+ 707:Src/main.c    ****   hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8;
+ 6127              		.loc 2 707 3 is_stmt 1 view .LVU1985
+ 707:Src/main.c    ****   hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8;
+ 6128              		.loc 2 707 18 is_stmt 0 view .LVU1986
+ARM GAS  /tmp/ccdsDELB.s 			page 466
+
+
+ 6129 000e 1448     		ldr	r0, .L276
+ 6130 0010 144A     		ldr	r2, .L276+4
+ 6131 0012 0260     		str	r2, [r0]
+ 708:Src/main.c    ****   hadc3.Init.Resolution = ADC_RESOLUTION_12B;
+ 6132              		.loc 2 708 3 is_stmt 1 view .LVU1987
+ 708:Src/main.c    ****   hadc3.Init.Resolution = ADC_RESOLUTION_12B;
+ 6133              		.loc 2 708 29 is_stmt 0 view .LVU1988
+ 6134 0014 4FF44032 		mov	r2, #196608
+ 6135 0018 4260     		str	r2, [r0, #4]
+ 709:Src/main.c    ****   hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
+ 6136              		.loc 2 709 3 is_stmt 1 view .LVU1989
+ 709:Src/main.c    ****   hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
+ 6137              		.loc 2 709 25 is_stmt 0 view .LVU1990
+ 6138 001a 8360     		str	r3, [r0, #8]
+ 710:Src/main.c    ****   hadc3.Init.ContinuousConvMode = DISABLE;
+ 6139              		.loc 2 710 3 is_stmt 1 view .LVU1991
+ 710:Src/main.c    ****   hadc3.Init.ContinuousConvMode = DISABLE;
+ 6140              		.loc 2 710 27 is_stmt 0 view .LVU1992
+ 6141 001c 0361     		str	r3, [r0, #16]
+ 711:Src/main.c    ****   hadc3.Init.DiscontinuousConvMode = DISABLE;
+ 6142              		.loc 2 711 3 is_stmt 1 view .LVU1993
+ 711:Src/main.c    ****   hadc3.Init.DiscontinuousConvMode = DISABLE;
+ 6143              		.loc 2 711 33 is_stmt 0 view .LVU1994
+ 6144 001e 8361     		str	r3, [r0, #24]
+ 712:Src/main.c    ****   hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 6145              		.loc 2 712 3 is_stmt 1 view .LVU1995
+ 712:Src/main.c    ****   hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 6146              		.loc 2 712 36 is_stmt 0 view .LVU1996
+ 6147 0020 80F82030 		strb	r3, [r0, #32]
+ 713:Src/main.c    ****   hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 6148              		.loc 2 713 3 is_stmt 1 view .LVU1997
+ 713:Src/main.c    ****   hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 6149              		.loc 2 713 35 is_stmt 0 view .LVU1998
+ 6150 0024 C362     		str	r3, [r0, #44]
+ 714:Src/main.c    ****   hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 6151              		.loc 2 714 3 is_stmt 1 view .LVU1999
+ 714:Src/main.c    ****   hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 6152              		.loc 2 714 31 is_stmt 0 view .LVU2000
+ 6153 0026 104A     		ldr	r2, .L276+8
+ 6154 0028 8262     		str	r2, [r0, #40]
+ 715:Src/main.c    ****   hadc3.Init.NbrOfConversion = 1;
+ 6155              		.loc 2 715 3 is_stmt 1 view .LVU2001
+ 715:Src/main.c    ****   hadc3.Init.NbrOfConversion = 1;
+ 6156              		.loc 2 715 24 is_stmt 0 view .LVU2002
+ 6157 002a C360     		str	r3, [r0, #12]
+ 716:Src/main.c    ****   hadc3.Init.DMAContinuousRequests = DISABLE;
+ 6158              		.loc 2 716 3 is_stmt 1 view .LVU2003
+ 716:Src/main.c    ****   hadc3.Init.DMAContinuousRequests = DISABLE;
+ 6159              		.loc 2 716 30 is_stmt 0 view .LVU2004
+ 6160 002c 0122     		movs	r2, #1
+ 6161 002e C261     		str	r2, [r0, #28]
+ 717:Src/main.c    ****   hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 6162              		.loc 2 717 3 is_stmt 1 view .LVU2005
+ 717:Src/main.c    ****   hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 6163              		.loc 2 717 36 is_stmt 0 view .LVU2006
+ 6164 0030 80F83030 		strb	r3, [r0, #48]
+ 718:Src/main.c    ****   if (HAL_ADC_Init(&hadc3) != HAL_OK)
+ARM GAS  /tmp/ccdsDELB.s 			page 467
+
+
+ 6165              		.loc 2 718 3 is_stmt 1 view .LVU2007
+ 718:Src/main.c    ****   if (HAL_ADC_Init(&hadc3) != HAL_OK)
+ 6166              		.loc 2 718 27 is_stmt 0 view .LVU2008
+ 6167 0034 4261     		str	r2, [r0, #20]
+ 719:Src/main.c    ****   {
+ 6168              		.loc 2 719 3 is_stmt 1 view .LVU2009
+ 719:Src/main.c    ****   {
+ 6169              		.loc 2 719 7 is_stmt 0 view .LVU2010
+ 6170 0036 FFF7FEFF 		bl	HAL_ADC_Init
+ 6171              	.LVL479:
+ 719:Src/main.c    ****   {
+ 6172              		.loc 2 719 6 view .LVU2011
+ 6173 003a 68B9     		cbnz	r0, .L274
+ 726:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 6174              		.loc 2 726 3 is_stmt 1 view .LVU2012
+ 726:Src/main.c    ****   sConfig.Rank = ADC_REGULAR_RANK_1;
+ 6175              		.loc 2 726 19 is_stmt 0 view .LVU2013
+ 6176 003c 0F23     		movs	r3, #15
+ 6177 003e 0093     		str	r3, [sp]
+ 727:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
+ 6178              		.loc 2 727 3 is_stmt 1 view .LVU2014
+ 727:Src/main.c    ****   sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
+ 6179              		.loc 2 727 16 is_stmt 0 view .LVU2015
+ 6180 0040 0123     		movs	r3, #1
+ 6181 0042 0193     		str	r3, [sp, #4]
+ 728:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
+ 6182              		.loc 2 728 3 is_stmt 1 view .LVU2016
+ 728:Src/main.c    ****   if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
+ 6183              		.loc 2 728 24 is_stmt 0 view .LVU2017
+ 6184 0044 0723     		movs	r3, #7
+ 6185 0046 0293     		str	r3, [sp, #8]
+ 729:Src/main.c    ****   {
+ 6186              		.loc 2 729 3 is_stmt 1 view .LVU2018
+ 729:Src/main.c    ****   {
+ 6187              		.loc 2 729 7 is_stmt 0 view .LVU2019
+ 6188 0048 6946     		mov	r1, sp
+ 6189 004a 0548     		ldr	r0, .L276
+ 6190 004c FFF7FEFF 		bl	HAL_ADC_ConfigChannel
+ 6191              	.LVL480:
+ 729:Src/main.c    ****   {
+ 6192              		.loc 2 729 6 view .LVU2020
+ 6193 0050 20B9     		cbnz	r0, .L275
+ 737:Src/main.c    **** 
+ 6194              		.loc 2 737 1 view .LVU2021
+ 6195 0052 05B0     		add	sp, sp, #20
+ 6196              	.LCFI53:
+ 6197              		.cfi_remember_state
+ 6198              		.cfi_def_cfa_offset 4
+ 6199              		@ sp needed
+ 6200 0054 5DF804FB 		ldr	pc, [sp], #4
+ 6201              	.L274:
+ 6202              	.LCFI54:
+ 6203              		.cfi_restore_state
+ 721:Src/main.c    ****   }
+ 6204              		.loc 2 721 5 is_stmt 1 view .LVU2022
+ 6205 0058 FFF7FEFF 		bl	Error_Handler
+ 6206              	.LVL481:
+ARM GAS  /tmp/ccdsDELB.s 			page 468
+
+
+ 6207              	.L275:
+ 731:Src/main.c    ****   }
+ 6208              		.loc 2 731 5 view .LVU2023
+ 6209 005c FFF7FEFF 		bl	Error_Handler
+ 6210              	.LVL482:
+ 6211              	.L277:
+ 6212              		.align	2
+ 6213              	.L276:
+ 6214 0060 00000000 		.word	.LANCHOR29
+ 6215 0064 00220140 		.word	1073816064
+ 6216 0068 0100000F 		.word	251658241
+ 6217              		.cfi_endproc
+ 6218              	.LFE1189:
+ 6220              		.section	.text.MX_USART1_UART_Init,"ax",%progbits
+ 6221              		.align	1
+ 6222              		.syntax unified
+ 6223              		.thumb
+ 6224              		.thumb_func
+ 6225              		.fpu fpv5-d16
+ 6227              	MX_USART1_UART_Init:
+ 6228              	.LFB1200:
+1208:Src/main.c    **** 
+ 6229              		.loc 2 1208 1 view -0
+ 6230              		.cfi_startproc
+ 6231              		@ args = 0, pretend = 0, frame = 208
+ 6232              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6233 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 6234              	.LCFI55:
+ 6235              		.cfi_def_cfa_offset 24
+ 6236              		.cfi_offset 4, -24
+ 6237              		.cfi_offset 5, -20
+ 6238              		.cfi_offset 6, -16
+ 6239              		.cfi_offset 7, -12
+ 6240              		.cfi_offset 8, -8
+ 6241              		.cfi_offset 14, -4
+ 6242 0004 B4B0     		sub	sp, sp, #208
+ 6243              	.LCFI56:
+ 6244              		.cfi_def_cfa_offset 232
+1214:Src/main.c    **** 
+ 6245              		.loc 2 1214 3 view .LVU2025
+1214:Src/main.c    **** 
+ 6246              		.loc 2 1214 24 is_stmt 0 view .LVU2026
+ 6247 0006 0021     		movs	r1, #0
+ 6248 0008 2D91     		str	r1, [sp, #180]
+ 6249 000a 2E91     		str	r1, [sp, #184]
+ 6250 000c 2F91     		str	r1, [sp, #188]
+ 6251 000e 3091     		str	r1, [sp, #192]
+ 6252 0010 3191     		str	r1, [sp, #196]
+ 6253 0012 3291     		str	r1, [sp, #200]
+ 6254 0014 3391     		str	r1, [sp, #204]
+1216:Src/main.c    ****   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 6255              		.loc 2 1216 3 is_stmt 1 view .LVU2027
+1216:Src/main.c    ****   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 6256              		.loc 2 1216 23 is_stmt 0 view .LVU2028
+ 6257 0016 2791     		str	r1, [sp, #156]
+ 6258 0018 2891     		str	r1, [sp, #160]
+ 6259 001a 2991     		str	r1, [sp, #164]
+ARM GAS  /tmp/ccdsDELB.s 			page 469
+
+
+ 6260 001c 2A91     		str	r1, [sp, #168]
+ 6261 001e 2B91     		str	r1, [sp, #172]
+ 6262 0020 2C91     		str	r1, [sp, #176]
+1217:Src/main.c    **** 
+ 6263              		.loc 2 1217 3 is_stmt 1 view .LVU2029
+1217:Src/main.c    **** 
+ 6264              		.loc 2 1217 28 is_stmt 0 view .LVU2030
+ 6265 0022 9022     		movs	r2, #144
+ 6266 0024 03A8     		add	r0, sp, #12
+ 6267 0026 FFF7FEFF 		bl	memset
+ 6268              	.LVL483:
+1221:Src/main.c    ****   PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+ 6269              		.loc 2 1221 3 is_stmt 1 view .LVU2031
+1221:Src/main.c    ****   PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+ 6270              		.loc 2 1221 44 is_stmt 0 view .LVU2032
+ 6271 002a 4023     		movs	r3, #64
+ 6272 002c 0393     		str	r3, [sp, #12]
+1222:Src/main.c    ****   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 6273              		.loc 2 1222 3 is_stmt 1 view .LVU2033
+1223:Src/main.c    ****   {
+ 6274              		.loc 2 1223 3 view .LVU2034
+1223:Src/main.c    ****   {
+ 6275              		.loc 2 1223 7 is_stmt 0 view .LVU2035
+ 6276 002e 03A8     		add	r0, sp, #12
+ 6277 0030 FFF7FEFF 		bl	HAL_RCCEx_PeriphCLKConfig
+ 6278              	.LVL484:
+1223:Src/main.c    ****   {
+ 6279              		.loc 2 1223 6 view .LVU2036
+ 6280 0034 0028     		cmp	r0, #0
+ 6281 0036 40F09E80 		bne	.L281
+1229:Src/main.c    **** 
+ 6282              		.loc 2 1229 3 is_stmt 1 view .LVU2037
+ 6283              	.LVL485:
+ 6284              	.LBB505:
+ 6285              	.LBI505:
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 6286              		.loc 3 1587 22 view .LVU2038
+ 6287              	.LBB506:
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB2ENR, Periphs);
+ 6288              		.loc 3 1589 3 view .LVU2039
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 6289              		.loc 3 1590 3 view .LVU2040
+ 6290 003a 504B     		ldr	r3, .L282
+ 6291 003c 5A6C     		ldr	r2, [r3, #68]
+ 6292 003e 42F01002 		orr	r2, r2, #16
+ 6293 0042 5A64     		str	r2, [r3, #68]
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 6294              		.loc 3 1592 3 view .LVU2041
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 6295              		.loc 3 1592 12 is_stmt 0 view .LVU2042
+ 6296 0044 5A6C     		ldr	r2, [r3, #68]
+ 6297 0046 02F01002 		and	r2, r2, #16
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 6298              		.loc 3 1592 10 view .LVU2043
+ 6299 004a 0292     		str	r2, [sp, #8]
+ 6300              		.loc 3 1593 3 is_stmt 1 view .LVU2044
+ 6301 004c 029A     		ldr	r2, [sp, #8]
+ARM GAS  /tmp/ccdsDELB.s 			page 470
+
+
+ 6302              	.LVL486:
+ 6303              		.loc 3 1593 3 is_stmt 0 view .LVU2045
+ 6304              	.LBE506:
+ 6305              	.LBE505:
+1231:Src/main.c    ****   /**USART1 GPIO Configuration
+ 6306              		.loc 2 1231 3 is_stmt 1 view .LVU2046
+ 6307              	.LBB507:
+ 6308              	.LBI507:
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 6309              		.loc 3 309 22 view .LVU2047
+ 6310              	.LBB508:
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1ENR, Periphs);
+ 6311              		.loc 3 311 3 view .LVU2048
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 6312              		.loc 3 312 3 view .LVU2049
+ 6313 004e 1A6B     		ldr	r2, [r3, #48]
+ 6314 0050 42F00102 		orr	r2, r2, #1
+ 6315 0054 1A63     		str	r2, [r3, #48]
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 6316              		.loc 3 314 3 view .LVU2050
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 6317              		.loc 3 314 12 is_stmt 0 view .LVU2051
+ 6318 0056 1B6B     		ldr	r3, [r3, #48]
+ 6319 0058 03F00103 		and	r3, r3, #1
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 6320              		.loc 3 314 10 view .LVU2052
+ 6321 005c 0193     		str	r3, [sp, #4]
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 6322              		.loc 3 315 3 is_stmt 1 view .LVU2053
+ 6323 005e 019B     		ldr	r3, [sp, #4]
+ 6324              	.LVL487:
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 6325              		.loc 3 315 3 is_stmt 0 view .LVU2054
+ 6326              	.LBE508:
+ 6327              	.LBE507:
+1236:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 6328              		.loc 2 1236 3 is_stmt 1 view .LVU2055
+1236:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 6329              		.loc 2 1236 23 is_stmt 0 view .LVU2056
+ 6330 0060 4FF40073 		mov	r3, #512
+ 6331 0064 2793     		str	r3, [sp, #156]
+1237:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 6332              		.loc 2 1237 3 is_stmt 1 view .LVU2057
+1237:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 6333              		.loc 2 1237 24 is_stmt 0 view .LVU2058
+ 6334 0066 4FF00208 		mov	r8, #2
+ 6335 006a CDF8A080 		str	r8, [sp, #160]
+1238:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 6336              		.loc 2 1238 3 is_stmt 1 view .LVU2059
+1238:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 6337              		.loc 2 1238 25 is_stmt 0 view .LVU2060
+ 6338 006e 0327     		movs	r7, #3
+ 6339 0070 2997     		str	r7, [sp, #164]
+1239:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 6340              		.loc 2 1239 3 is_stmt 1 view .LVU2061
+1239:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 6341              		.loc 2 1239 30 is_stmt 0 view .LVU2062
+ARM GAS  /tmp/ccdsDELB.s 			page 471
+
+
+ 6342 0072 0024     		movs	r4, #0
+ 6343 0074 2A94     		str	r4, [sp, #168]
+1240:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+ 6344              		.loc 2 1240 3 is_stmt 1 view .LVU2063
+1240:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+ 6345              		.loc 2 1240 24 is_stmt 0 view .LVU2064
+ 6346 0076 2B94     		str	r4, [sp, #172]
+1241:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 6347              		.loc 2 1241 3 is_stmt 1 view .LVU2065
+1241:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 6348              		.loc 2 1241 29 is_stmt 0 view .LVU2066
+ 6349 0078 0726     		movs	r6, #7
+ 6350 007a 2C96     		str	r6, [sp, #176]
+1242:Src/main.c    **** 
+ 6351              		.loc 2 1242 3 is_stmt 1 view .LVU2067
+ 6352 007c 404D     		ldr	r5, .L282+4
+ 6353 007e 27A9     		add	r1, sp, #156
+ 6354 0080 2846     		mov	r0, r5
+ 6355 0082 FFF7FEFF 		bl	LL_GPIO_Init
+ 6356              	.LVL488:
+1244:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 6357              		.loc 2 1244 3 view .LVU2068
+1244:Src/main.c    ****   GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 6358              		.loc 2 1244 23 is_stmt 0 view .LVU2069
+ 6359 0086 4FF48063 		mov	r3, #1024
+ 6360 008a 2793     		str	r3, [sp, #156]
+1245:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 6361              		.loc 2 1245 3 is_stmt 1 view .LVU2070
+1245:Src/main.c    ****   GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 6362              		.loc 2 1245 24 is_stmt 0 view .LVU2071
+ 6363 008c CDF8A080 		str	r8, [sp, #160]
+1246:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 6364              		.loc 2 1246 3 is_stmt 1 view .LVU2072
+1246:Src/main.c    ****   GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 6365              		.loc 2 1246 25 is_stmt 0 view .LVU2073
+ 6366 0090 2997     		str	r7, [sp, #164]
+1247:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 6367              		.loc 2 1247 3 is_stmt 1 view .LVU2074
+1247:Src/main.c    ****   GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 6368              		.loc 2 1247 30 is_stmt 0 view .LVU2075
+ 6369 0092 2A94     		str	r4, [sp, #168]
+1248:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+ 6370              		.loc 2 1248 3 is_stmt 1 view .LVU2076
+1248:Src/main.c    ****   GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+ 6371              		.loc 2 1248 24 is_stmt 0 view .LVU2077
+ 6372 0094 2B94     		str	r4, [sp, #172]
+1249:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 6373              		.loc 2 1249 3 is_stmt 1 view .LVU2078
+1249:Src/main.c    ****   LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 6374              		.loc 2 1249 29 is_stmt 0 view .LVU2079
+ 6375 0096 2C96     		str	r6, [sp, #176]
+1250:Src/main.c    **** 
+ 6376              		.loc 2 1250 3 is_stmt 1 view .LVU2080
+ 6377 0098 27A9     		add	r1, sp, #156
+ 6378 009a 2846     		mov	r0, r5
+ 6379 009c FFF7FEFF 		bl	LL_GPIO_Init
+ 6380              	.LVL489:
+ARM GAS  /tmp/ccdsDELB.s 			page 472
+
+
+1255:Src/main.c    **** 
+ 6381              		.loc 2 1255 3 view .LVU2081
+ 6382              	.LBB509:
+ 6383              	.LBI509:
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 6384              		.loc 6 1032 22 view .LVU2082
+ 6385              	.LBB510:
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6386              		.loc 6 1034 3 view .LVU2083
+ 6387 00a0 384B     		ldr	r3, .L282+8
+ 6388 00a2 D3F8B820 		ldr	r2, [r3, #184]
+ 6389 00a6 22F0F052 		bic	r2, r2, #503316480
+ 6390 00aa 42F00062 		orr	r2, r2, #134217728
+ 6391 00ae C3F8B820 		str	r2, [r3, #184]
+ 6392              	.LVL490:
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6393              		.loc 6 1034 3 is_stmt 0 view .LVU2084
+ 6394              	.LBE510:
+ 6395              	.LBE509:
+1257:Src/main.c    **** 
+ 6396              		.loc 2 1257 3 is_stmt 1 view .LVU2085
+ 6397              	.LBB511:
+ 6398              	.LBI511:
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 6399              		.loc 6 598 22 view .LVU2086
+ 6400              	.LBB512:
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6401              		.loc 6 600 3 view .LVU2087
+ 6402 00b2 D3F8B820 		ldr	r2, [r3, #184]
+ 6403 00b6 22F0C002 		bic	r2, r2, #192
+ 6404 00ba 42F04002 		orr	r2, r2, #64
+ 6405 00be C3F8B820 		str	r2, [r3, #184]
+ 6406              	.LVL491:
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6407              		.loc 6 600 3 is_stmt 0 view .LVU2088
+ 6408              	.LBE512:
+ 6409              	.LBE511:
+1259:Src/main.c    **** 
+ 6410              		.loc 2 1259 3 is_stmt 1 view .LVU2089
+ 6411              	.LBB513:
+ 6412              	.LBI513:
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 6413              		.loc 6 924 22 view .LVU2090
+ 6414              	.LBB514:
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6415              		.loc 6 926 3 view .LVU2091
+ 6416 00c2 D3F8B820 		ldr	r2, [r3, #184]
+ 6417 00c6 42F44032 		orr	r2, r2, #196608
+ 6418 00ca C3F8B820 		str	r2, [r3, #184]
+ 6419              	.LVL492:
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6420              		.loc 6 926 3 is_stmt 0 view .LVU2092
+ 6421              	.LBE514:
+ 6422              	.LBE513:
+1261:Src/main.c    **** 
+ 6423              		.loc 2 1261 3 is_stmt 1 view .LVU2093
+ 6424              	.LBB515:
+ARM GAS  /tmp/ccdsDELB.s 			page 473
+
+
+ 6425              	.LBI515:
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 6426              		.loc 6 646 22 view .LVU2094
+ 6427              	.LBB516:
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6428              		.loc 6 648 3 view .LVU2095
+ 6429 00ce D3F8B820 		ldr	r2, [r3, #184]
+ 6430 00d2 22F49072 		bic	r2, r2, #288
+ 6431 00d6 C3F8B820 		str	r2, [r3, #184]
+ 6432              	.LVL493:
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6433              		.loc 6 648 3 is_stmt 0 view .LVU2096
+ 6434              	.LBE516:
+ 6435              	.LBE515:
+1263:Src/main.c    **** 
+ 6436              		.loc 2 1263 3 is_stmt 1 view .LVU2097
+ 6437              	.LBB517:
+ 6438              	.LBI517:
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 6439              		.loc 6 693 22 view .LVU2098
+ 6440              	.LBB518:
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6441              		.loc 6 695 3 view .LVU2099
+ 6442 00da D3F8B820 		ldr	r2, [r3, #184]
+ 6443 00de 22F40072 		bic	r2, r2, #512
+ 6444 00e2 C3F8B820 		str	r2, [r3, #184]
+ 6445              	.LVL494:
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6446              		.loc 6 695 3 is_stmt 0 view .LVU2100
+ 6447              	.LBE518:
+ 6448              	.LBE517:
+1265:Src/main.c    **** 
+ 6449              		.loc 2 1265 3 is_stmt 1 view .LVU2101
+ 6450              	.LBB519:
+ 6451              	.LBI519:
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 6452              		.loc 6 738 22 view .LVU2102
+ 6453              	.LBB520:
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6454              		.loc 6 740 3 view .LVU2103
+ 6455 00e6 D3F8B820 		ldr	r2, [r3, #184]
+ 6456 00ea 42F48062 		orr	r2, r2, #1024
+ 6457 00ee C3F8B820 		str	r2, [r3, #184]
+ 6458              	.LVL495:
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6459              		.loc 6 740 3 is_stmt 0 view .LVU2104
+ 6460              	.LBE520:
+ 6461              	.LBE519:
+1267:Src/main.c    **** 
+ 6462              		.loc 2 1267 3 is_stmt 1 view .LVU2105
+ 6463              	.LBB521:
+ 6464              	.LBI521:
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 6465              		.loc 6 784 22 view .LVU2106
+ 6466              	.LBB522:
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6467              		.loc 6 786 3 view .LVU2107
+ARM GAS  /tmp/ccdsDELB.s 			page 474
+
+
+ 6468 00f2 D3F8B820 		ldr	r2, [r3, #184]
+ 6469 00f6 22F4C052 		bic	r2, r2, #6144
+ 6470 00fa C3F8B820 		str	r2, [r3, #184]
+ 6471              	.LVL496:
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6472              		.loc 6 786 3 is_stmt 0 view .LVU2108
+ 6473              	.LBE522:
+ 6474              	.LBE521:
+1269:Src/main.c    **** 
+ 6475              		.loc 2 1269 3 is_stmt 1 view .LVU2109
+ 6476              	.LBB523:
+ 6477              	.LBI523:
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 6478              		.loc 6 831 22 view .LVU2110
+ 6479              	.LBB524:
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6480              		.loc 6 833 3 view .LVU2111
+ 6481 00fe D3F8B820 		ldr	r2, [r3, #184]
+ 6482 0102 22F4C042 		bic	r2, r2, #24576
+ 6483 0106 C3F8B820 		str	r2, [r3, #184]
+ 6484              	.LVL497:
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6485              		.loc 6 833 3 is_stmt 0 view .LVU2112
+ 6486              	.LBE524:
+ 6487              	.LBE523:
+1271:Src/main.c    **** 
+ 6488              		.loc 2 1271 3 is_stmt 1 view .LVU2113
+ 6489              	.LBB525:
+ 6490              	.LBI525:
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 6491              		.loc 6 1299 22 view .LVU2114
+ 6492              	.LBB526:
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6493              		.loc 6 1301 3 view .LVU2115
+ 6494 010a D3F8CC20 		ldr	r2, [r3, #204]
+ 6495 010e 22F00402 		bic	r2, r2, #4
+ 6496 0112 C3F8CC20 		str	r2, [r3, #204]
+ 6497              	.LVL498:
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 6498              		.loc 6 1301 3 is_stmt 0 view .LVU2116
+ 6499              	.LBE526:
+ 6500              	.LBE525:
+1274:Src/main.c    ****   NVIC_EnableIRQ(USART1_IRQn);
+ 6501              		.loc 2 1274 3 is_stmt 1 view .LVU2117
+ 6502              	.LBB527:
+ 6503              	.LBI527:
+1884:Drivers/CMSIS/Include/core_cm7.h **** {
+ 6504              		.loc 1 1884 26 view .LVU2118
+ 6505              	.LBB528:
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 6506              		.loc 1 1886 3 view .LVU2119
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 6507              		.loc 1 1886 26 is_stmt 0 view .LVU2120
+ 6508 0116 1C4B     		ldr	r3, .L282+12
+ 6509 0118 D868     		ldr	r0, [r3, #12]
+ 6510              	.LBE528:
+ 6511              	.LBE527:
+ARM GAS  /tmp/ccdsDELB.s 			page 475
+
+
+1274:Src/main.c    ****   NVIC_EnableIRQ(USART1_IRQn);
+ 6512              		.loc 2 1274 3 view .LVU2121
+ 6513 011a 2246     		mov	r2, r4
+ 6514 011c 2146     		mov	r1, r4
+ 6515 011e C0F30220 		ubfx	r0, r0, #8, #3
+ 6516 0122 FFF7FEFF 		bl	NVIC_EncodePriority
+ 6517              	.LVL499:
+ 6518              	.LBB529:
+ 6519              	.LBI529:
+2024:Drivers/CMSIS/Include/core_cm7.h **** {
+ 6520              		.loc 1 2024 22 is_stmt 1 view .LVU2122
+ 6521              	.LBB530:
+2026:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 6522              		.loc 1 2026 3 view .LVU2123
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 6523              		.loc 1 2028 5 view .LVU2124
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 6524              		.loc 1 2028 49 is_stmt 0 view .LVU2125
+ 6525 0126 0001     		lsls	r0, r0, #4
+ 6526              	.LVL500:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 6527              		.loc 1 2028 49 view .LVU2126
+ 6528 0128 C0B2     		uxtb	r0, r0
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 6529              		.loc 1 2028 47 view .LVU2127
+ 6530 012a 184B     		ldr	r3, .L282+16
+ 6531 012c 83F82503 		strb	r0, [r3, #805]
+ 6532              	.LVL501:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 6533              		.loc 1 2028 47 view .LVU2128
+ 6534              	.LBE530:
+ 6535              	.LBE529:
+1275:Src/main.c    **** 
+ 6536              		.loc 2 1275 3 is_stmt 1 view .LVU2129
+ 6537              	.LBB531:
+ 6538              	.LBI531:
+1896:Drivers/CMSIS/Include/core_cm7.h **** {
+ 6539              		.loc 1 1896 22 view .LVU2130
+ 6540              	.LBB532:
+1898:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 6541              		.loc 1 1898 3 view .LVU2131
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 6542              		.loc 1 1900 5 view .LVU2132
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 6543              		.loc 1 1900 43 is_stmt 0 view .LVU2133
+ 6544 0130 2022     		movs	r2, #32
+ 6545 0132 5A60     		str	r2, [r3, #4]
+ 6546              	.LVL502:
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 6547              		.loc 1 1900 43 view .LVU2134
+ 6548              	.LBE532:
+ 6549              	.LBE531:
+1280:Src/main.c    ****   USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
+ 6550              		.loc 2 1280 3 is_stmt 1 view .LVU2135
+1280:Src/main.c    ****   USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
+ 6551              		.loc 2 1280 29 is_stmt 0 view .LVU2136
+ 6552 0134 4FF4E133 		mov	r3, #115200
+ARM GAS  /tmp/ccdsDELB.s 			page 476
+
+
+ 6553 0138 2D93     		str	r3, [sp, #180]
+1281:Src/main.c    ****   USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
+ 6554              		.loc 2 1281 3 is_stmt 1 view .LVU2137
+1281:Src/main.c    ****   USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
+ 6555              		.loc 2 1281 30 is_stmt 0 view .LVU2138
+ 6556 013a 2E94     		str	r4, [sp, #184]
+1282:Src/main.c    ****   USART_InitStruct.Parity = LL_USART_PARITY_NONE;
+ 6557              		.loc 2 1282 3 is_stmt 1 view .LVU2139
+1282:Src/main.c    ****   USART_InitStruct.Parity = LL_USART_PARITY_NONE;
+ 6558              		.loc 2 1282 29 is_stmt 0 view .LVU2140
+ 6559 013c 2F94     		str	r4, [sp, #188]
+1283:Src/main.c    ****   USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
+ 6560              		.loc 2 1283 3 is_stmt 1 view .LVU2141
+1283:Src/main.c    ****   USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
+ 6561              		.loc 2 1283 27 is_stmt 0 view .LVU2142
+ 6562 013e 3094     		str	r4, [sp, #192]
+1284:Src/main.c    ****   USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+ 6563              		.loc 2 1284 3 is_stmt 1 view .LVU2143
+1284:Src/main.c    ****   USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+ 6564              		.loc 2 1284 38 is_stmt 0 view .LVU2144
+ 6565 0140 0C23     		movs	r3, #12
+ 6566 0142 3193     		str	r3, [sp, #196]
+1285:Src/main.c    ****   USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
+ 6567              		.loc 2 1285 3 is_stmt 1 view .LVU2145
+1285:Src/main.c    ****   USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
+ 6568              		.loc 2 1285 40 is_stmt 0 view .LVU2146
+ 6569 0144 3294     		str	r4, [sp, #200]
+1286:Src/main.c    ****   LL_USART_Init(USART1, &USART_InitStruct);
+ 6570              		.loc 2 1286 3 is_stmt 1 view .LVU2147
+1286:Src/main.c    ****   LL_USART_Init(USART1, &USART_InitStruct);
+ 6571              		.loc 2 1286 33 is_stmt 0 view .LVU2148
+ 6572 0146 3394     		str	r4, [sp, #204]
+1287:Src/main.c    ****   LL_USART_ConfigAsyncMode(USART1);
+ 6573              		.loc 2 1287 3 is_stmt 1 view .LVU2149
+ 6574 0148 04F18044 		add	r4, r4, #1073741824
+ 6575 014c 04F58834 		add	r4, r4, #69632
+ 6576 0150 2DA9     		add	r1, sp, #180
+ 6577 0152 2046     		mov	r0, r4
+ 6578 0154 FFF7FEFF 		bl	LL_USART_Init
+ 6579              	.LVL503:
+1288:Src/main.c    ****   LL_USART_Enable(USART1);
+ 6580              		.loc 2 1288 3 view .LVU2150
+ 6581              	.LBB533:
+ 6582              	.LBI533:
+2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 6583              		.loc 7 2320 22 view .LVU2151
+ 6584              	.LBB534:
+2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+ 6585              		.loc 7 2326 3 view .LVU2152
+ 6586 0158 6368     		ldr	r3, [r4, #4]
+ 6587 015a 23F49043 		bic	r3, r3, #18432
+ 6588 015e 6360     		str	r3, [r4, #4]
+2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 6589              		.loc 7 2327 3 view .LVU2153
+ 6590 0160 A368     		ldr	r3, [r4, #8]
+ 6591 0162 23F02A03 		bic	r3, r3, #42
+ 6592 0166 A360     		str	r3, [r4, #8]
+ARM GAS  /tmp/ccdsDELB.s 			page 477
+
+
+ 6593              	.LVL504:
+2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 6594              		.loc 7 2327 3 is_stmt 0 view .LVU2154
+ 6595              	.LBE534:
+ 6596              	.LBE533:
+1289:Src/main.c    ****   /* USER CODE BEGIN USART1_Init 2 */
+ 6597              		.loc 2 1289 3 is_stmt 1 view .LVU2155
+ 6598              	.LBB535:
+ 6599              	.LBI535:
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 6600              		.loc 7 560 22 view .LVU2156
+ 6601              	.LBB536:
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 6602              		.loc 7 562 3 view .LVU2157
+ 6603 0168 2368     		ldr	r3, [r4]
+ 6604 016a 43F00103 		orr	r3, r3, #1
+ 6605 016e 2360     		str	r3, [r4]
+ 6606              	.LVL505:
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 6607              		.loc 7 562 3 is_stmt 0 view .LVU2158
+ 6608              	.LBE536:
+ 6609              	.LBE535:
+1294:Src/main.c    **** 
+ 6610              		.loc 2 1294 1 view .LVU2159
+ 6611 0170 34B0     		add	sp, sp, #208
+ 6612              	.LCFI57:
+ 6613              		.cfi_remember_state
+ 6614              		.cfi_def_cfa_offset 24
+ 6615              		@ sp needed
+ 6616 0172 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 6617              	.L281:
+ 6618              	.LCFI58:
+ 6619              		.cfi_restore_state
+1225:Src/main.c    ****   }
+ 6620              		.loc 2 1225 5 is_stmt 1 view .LVU2160
+ 6621 0176 FFF7FEFF 		bl	Error_Handler
+ 6622              	.LVL506:
+ 6623              	.L283:
+ 6624 017a 00BF     		.align	2
+ 6625              	.L282:
+ 6626 017c 00380240 		.word	1073887232
+ 6627 0180 00000240 		.word	1073872896
+ 6628 0184 00640240 		.word	1073898496
+ 6629 0188 00ED00E0 		.word	-536810240
+ 6630 018c 00E100E0 		.word	-536813312
+ 6631              		.cfi_endproc
+ 6632              	.LFE1200:
+ 6634              		.section	.text.MX_TIM10_Init,"ax",%progbits
+ 6635              		.align	1
+ 6636              		.syntax unified
+ 6637              		.thumb
+ 6638              		.thumb_func
+ 6639              		.fpu fpv5-d16
+ 6641              	MX_TIM10_Init:
+ 6642              	.LFB1199:
+1177:Src/main.c    **** 
+ 6643              		.loc 2 1177 1 view -0
+ARM GAS  /tmp/ccdsDELB.s 			page 478
+
+
+ 6644              		.cfi_startproc
+ 6645              		@ args = 0, pretend = 0, frame = 0
+ 6646              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6647 0000 08B5     		push	{r3, lr}
+ 6648              	.LCFI59:
+ 6649              		.cfi_def_cfa_offset 8
+ 6650              		.cfi_offset 3, -8
+ 6651              		.cfi_offset 14, -4
+1186:Src/main.c    ****   htim10.Init.Prescaler = 183;
+ 6652              		.loc 2 1186 3 view .LVU2162
+1186:Src/main.c    ****   htim10.Init.Prescaler = 183;
+ 6653              		.loc 2 1186 19 is_stmt 0 view .LVU2163
+ 6654 0002 0848     		ldr	r0, .L288
+ 6655 0004 084B     		ldr	r3, .L288+4
+ 6656 0006 0360     		str	r3, [r0]
+1187:Src/main.c    ****   htim10.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 6657              		.loc 2 1187 3 is_stmt 1 view .LVU2164
+1187:Src/main.c    ****   htim10.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 6658              		.loc 2 1187 25 is_stmt 0 view .LVU2165
+ 6659 0008 B723     		movs	r3, #183
+ 6660 000a 4360     		str	r3, [r0, #4]
+1188:Src/main.c    ****   htim10.Init.Period = 9;
+ 6661              		.loc 2 1188 3 is_stmt 1 view .LVU2166
+1188:Src/main.c    ****   htim10.Init.Period = 9;
+ 6662              		.loc 2 1188 27 is_stmt 0 view .LVU2167
+ 6663 000c 0023     		movs	r3, #0
+ 6664 000e 8360     		str	r3, [r0, #8]
+1189:Src/main.c    ****   htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 6665              		.loc 2 1189 3 is_stmt 1 view .LVU2168
+1189:Src/main.c    ****   htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 6666              		.loc 2 1189 22 is_stmt 0 view .LVU2169
+ 6667 0010 0922     		movs	r2, #9
+ 6668 0012 C260     		str	r2, [r0, #12]
+1190:Src/main.c    ****   htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 6669              		.loc 2 1190 3 is_stmt 1 view .LVU2170
+1190:Src/main.c    ****   htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 6670              		.loc 2 1190 29 is_stmt 0 view .LVU2171
+ 6671 0014 0361     		str	r3, [r0, #16]
+1191:Src/main.c    ****   if (HAL_TIM_Base_Init(&htim10) != HAL_OK)
+ 6672              		.loc 2 1191 3 is_stmt 1 view .LVU2172
+1191:Src/main.c    ****   if (HAL_TIM_Base_Init(&htim10) != HAL_OK)
+ 6673              		.loc 2 1191 33 is_stmt 0 view .LVU2173
+ 6674 0016 8361     		str	r3, [r0, #24]
+1192:Src/main.c    ****   {
+ 6675              		.loc 2 1192 3 is_stmt 1 view .LVU2174
+1192:Src/main.c    ****   {
+ 6676              		.loc 2 1192 7 is_stmt 0 view .LVU2175
+ 6677 0018 FFF7FEFF 		bl	HAL_TIM_Base_Init
+ 6678              	.LVL507:
+1192:Src/main.c    ****   {
+ 6679              		.loc 2 1192 6 view .LVU2176
+ 6680 001c 00B9     		cbnz	r0, .L287
+1200:Src/main.c    **** 
+ 6681              		.loc 2 1200 1 view .LVU2177
+ 6682 001e 08BD     		pop	{r3, pc}
+ 6683              	.L287:
+1194:Src/main.c    ****   }
+ARM GAS  /tmp/ccdsDELB.s 			page 479
+
+
+ 6684              		.loc 2 1194 5 is_stmt 1 view .LVU2178
+ 6685 0020 FFF7FEFF 		bl	Error_Handler
+ 6686              	.LVL508:
+ 6687              	.L289:
+ 6688              		.align	2
+ 6689              	.L288:
+ 6690 0024 00000000 		.word	.LANCHOR30
+ 6691 0028 00440140 		.word	1073824768
+ 6692              		.cfi_endproc
+ 6693              	.LFE1199:
+ 6695              		.section	.text.SystemClock_Config,"ax",%progbits
+ 6696              		.align	1
+ 6697              		.global	SystemClock_Config
+ 6698              		.syntax unified
+ 6699              		.thumb
+ 6700              		.thumb_func
+ 6701              		.fpu fpv5-d16
+ 6703              	SystemClock_Config:
+ 6704              	.LFB1187:
+ 551:Src/main.c    ****   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 6705              		.loc 2 551 1 view -0
+ 6706              		.cfi_startproc
+ 6707              		@ args = 0, pretend = 0, frame = 80
+ 6708              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6709 0000 00B5     		push	{lr}
+ 6710              	.LCFI60:
+ 6711              		.cfi_def_cfa_offset 4
+ 6712              		.cfi_offset 14, -4
+ 6713 0002 95B0     		sub	sp, sp, #84
+ 6714              	.LCFI61:
+ 6715              		.cfi_def_cfa_offset 88
+ 552:Src/main.c    ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 6716              		.loc 2 552 3 view .LVU2180
+ 552:Src/main.c    ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 6717              		.loc 2 552 22 is_stmt 0 view .LVU2181
+ 6718 0004 3422     		movs	r2, #52
+ 6719 0006 0021     		movs	r1, #0
+ 6720 0008 07A8     		add	r0, sp, #28
+ 6721 000a FFF7FEFF 		bl	memset
+ 6722              	.LVL509:
+ 553:Src/main.c    **** 
+ 6723              		.loc 2 553 3 is_stmt 1 view .LVU2182
+ 553:Src/main.c    **** 
+ 6724              		.loc 2 553 22 is_stmt 0 view .LVU2183
+ 6725 000e 0023     		movs	r3, #0
+ 6726 0010 0293     		str	r3, [sp, #8]
+ 6727 0012 0393     		str	r3, [sp, #12]
+ 6728 0014 0493     		str	r3, [sp, #16]
+ 6729 0016 0593     		str	r3, [sp, #20]
+ 6730 0018 0693     		str	r3, [sp, #24]
+ 557:Src/main.c    ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ 6731              		.loc 2 557 3 is_stmt 1 view .LVU2184
+ 6732              	.LBB537:
+ 557:Src/main.c    ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ 6733              		.loc 2 557 3 view .LVU2185
+ 557:Src/main.c    ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ 6734              		.loc 2 557 3 view .LVU2186
+ARM GAS  /tmp/ccdsDELB.s 			page 480
+
+
+ 6735 001a 244B     		ldr	r3, .L298
+ 6736 001c 1A6C     		ldr	r2, [r3, #64]
+ 6737 001e 42F08052 		orr	r2, r2, #268435456
+ 6738 0022 1A64     		str	r2, [r3, #64]
+ 557:Src/main.c    ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ 6739              		.loc 2 557 3 view .LVU2187
+ 6740 0024 1B6C     		ldr	r3, [r3, #64]
+ 6741 0026 03F08053 		and	r3, r3, #268435456
+ 6742 002a 0093     		str	r3, [sp]
+ 557:Src/main.c    ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ 6743              		.loc 2 557 3 view .LVU2188
+ 6744 002c 009B     		ldr	r3, [sp]
+ 6745              	.LBE537:
+ 557:Src/main.c    ****   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ 6746              		.loc 2 557 3 view .LVU2189
+ 558:Src/main.c    **** 
+ 6747              		.loc 2 558 3 view .LVU2190
+ 6748              	.LBB538:
+ 558:Src/main.c    **** 
+ 6749              		.loc 2 558 3 view .LVU2191
+ 558:Src/main.c    **** 
+ 6750              		.loc 2 558 3 view .LVU2192
+ 6751 002e 204B     		ldr	r3, .L298+4
+ 6752 0030 1A68     		ldr	r2, [r3]
+ 6753 0032 42F44042 		orr	r2, r2, #49152
+ 6754 0036 1A60     		str	r2, [r3]
+ 558:Src/main.c    **** 
+ 6755              		.loc 2 558 3 view .LVU2193
+ 6756 0038 1B68     		ldr	r3, [r3]
+ 6757 003a 03F44043 		and	r3, r3, #49152
+ 6758 003e 0193     		str	r3, [sp, #4]
+ 558:Src/main.c    **** 
+ 6759              		.loc 2 558 3 view .LVU2194
+ 6760 0040 019B     		ldr	r3, [sp, #4]
+ 6761              	.LBE538:
+ 558:Src/main.c    **** 
+ 6762              		.loc 2 558 3 view .LVU2195
+ 563:Src/main.c    ****   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ 6763              		.loc 2 563 3 view .LVU2196
+ 563:Src/main.c    ****   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ 6764              		.loc 2 563 36 is_stmt 0 view .LVU2197
+ 6765 0042 0123     		movs	r3, #1
+ 6766 0044 0793     		str	r3, [sp, #28]
+ 564:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 6767              		.loc 2 564 3 is_stmt 1 view .LVU2198
+ 564:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 6768              		.loc 2 564 30 is_stmt 0 view .LVU2199
+ 6769 0046 4FF48033 		mov	r3, #65536
+ 6770 004a 0893     		str	r3, [sp, #32]
+ 565:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ 6771              		.loc 2 565 3 is_stmt 1 view .LVU2200
+ 565:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ 6772              		.loc 2 565 34 is_stmt 0 view .LVU2201
+ 6773 004c 0223     		movs	r3, #2
+ 6774 004e 0D93     		str	r3, [sp, #52]
+ 566:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLM = 25;
+ 6775              		.loc 2 566 3 is_stmt 1 view .LVU2202
+ARM GAS  /tmp/ccdsDELB.s 			page 481
+
+
+ 566:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLM = 25;
+ 6776              		.loc 2 566 35 is_stmt 0 view .LVU2203
+ 6777 0050 4FF48002 		mov	r2, #4194304
+ 6778 0054 0E92     		str	r2, [sp, #56]
+ 567:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLN = 368;
+ 6779              		.loc 2 567 3 is_stmt 1 view .LVU2204
+ 567:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLN = 368;
+ 6780              		.loc 2 567 30 is_stmt 0 view .LVU2205
+ 6781 0056 1922     		movs	r2, #25
+ 6782 0058 0F92     		str	r2, [sp, #60]
+ 568:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ 6783              		.loc 2 568 3 is_stmt 1 view .LVU2206
+ 568:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ 6784              		.loc 2 568 30 is_stmt 0 view .LVU2207
+ 6785 005a 4FF4B872 		mov	r2, #368
+ 6786 005e 1092     		str	r2, [sp, #64]
+ 569:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLQ = 8;
+ 6787              		.loc 2 569 3 is_stmt 1 view .LVU2208
+ 569:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLQ = 8;
+ 6788              		.loc 2 569 30 is_stmt 0 view .LVU2209
+ 6789 0060 1193     		str	r3, [sp, #68]
+ 570:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLR = 2;
+ 6790              		.loc 2 570 3 is_stmt 1 view .LVU2210
+ 570:Src/main.c    ****   RCC_OscInitStruct.PLL.PLLR = 2;
+ 6791              		.loc 2 570 30 is_stmt 0 view .LVU2211
+ 6792 0062 0822     		movs	r2, #8
+ 6793 0064 1292     		str	r2, [sp, #72]
+ 571:Src/main.c    ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 6794              		.loc 2 571 3 is_stmt 1 view .LVU2212
+ 571:Src/main.c    ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 6795              		.loc 2 571 30 is_stmt 0 view .LVU2213
+ 6796 0066 1393     		str	r3, [sp, #76]
+ 572:Src/main.c    ****   {
+ 6797              		.loc 2 572 3 is_stmt 1 view .LVU2214
+ 572:Src/main.c    ****   {
+ 6798              		.loc 2 572 7 is_stmt 0 view .LVU2215
+ 6799 0068 07A8     		add	r0, sp, #28
+ 6800 006a FFF7FEFF 		bl	HAL_RCC_OscConfig
+ 6801              	.LVL510:
+ 572:Src/main.c    ****   {
+ 6802              		.loc 2 572 6 view .LVU2216
+ 6803 006e B0B9     		cbnz	r0, .L295
+ 579:Src/main.c    ****   {
+ 6804              		.loc 2 579 3 is_stmt 1 view .LVU2217
+ 579:Src/main.c    ****   {
+ 6805              		.loc 2 579 7 is_stmt 0 view .LVU2218
+ 6806 0070 FFF7FEFF 		bl	HAL_PWREx_EnableOverDrive
+ 6807              	.LVL511:
+ 579:Src/main.c    ****   {
+ 6808              		.loc 2 579 6 view .LVU2219
+ 6809 0074 A8B9     		cbnz	r0, .L296
+ 586:Src/main.c    ****                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ 6810              		.loc 2 586 3 is_stmt 1 view .LVU2220
+ 586:Src/main.c    ****                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ 6811              		.loc 2 586 31 is_stmt 0 view .LVU2221
+ 6812 0076 0F23     		movs	r3, #15
+ 6813 0078 0293     		str	r3, [sp, #8]
+ARM GAS  /tmp/ccdsDELB.s 			page 482
+
+
+ 588:Src/main.c    ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 6814              		.loc 2 588 3 is_stmt 1 view .LVU2222
+ 588:Src/main.c    ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 6815              		.loc 2 588 34 is_stmt 0 view .LVU2223
+ 6816 007a 0223     		movs	r3, #2
+ 6817 007c 0393     		str	r3, [sp, #12]
+ 589:Src/main.c    ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ 6818              		.loc 2 589 3 is_stmt 1 view .LVU2224
+ 589:Src/main.c    ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ 6819              		.loc 2 589 35 is_stmt 0 view .LVU2225
+ 6820 007e 0023     		movs	r3, #0
+ 6821 0080 0493     		str	r3, [sp, #16]
+ 590:Src/main.c    ****   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+ 6822              		.loc 2 590 3 is_stmt 1 view .LVU2226
+ 590:Src/main.c    ****   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+ 6823              		.loc 2 590 36 is_stmt 0 view .LVU2227
+ 6824 0082 4FF4A053 		mov	r3, #5120
+ 6825 0086 0593     		str	r3, [sp, #20]
+ 591:Src/main.c    **** 
+ 6826              		.loc 2 591 3 is_stmt 1 view .LVU2228
+ 591:Src/main.c    **** 
+ 6827              		.loc 2 591 36 is_stmt 0 view .LVU2229
+ 6828 0088 4FF48053 		mov	r3, #4096
+ 6829 008c 0693     		str	r3, [sp, #24]
+ 593:Src/main.c    ****   {
+ 6830              		.loc 2 593 3 is_stmt 1 view .LVU2230
+ 593:Src/main.c    ****   {
+ 6831              		.loc 2 593 7 is_stmt 0 view .LVU2231
+ 6832 008e 0621     		movs	r1, #6
+ 6833 0090 02A8     		add	r0, sp, #8
+ 6834 0092 FFF7FEFF 		bl	HAL_RCC_ClockConfig
+ 6835              	.LVL512:
+ 593:Src/main.c    ****   {
+ 6836              		.loc 2 593 6 view .LVU2232
+ 6837 0096 30B9     		cbnz	r0, .L297
+ 597:Src/main.c    **** 
+ 6838              		.loc 2 597 1 view .LVU2233
+ 6839 0098 15B0     		add	sp, sp, #84
+ 6840              	.LCFI62:
+ 6841              		.cfi_remember_state
+ 6842              		.cfi_def_cfa_offset 4
+ 6843              		@ sp needed
+ 6844 009a 5DF804FB 		ldr	pc, [sp], #4
+ 6845              	.L295:
+ 6846              	.LCFI63:
+ 6847              		.cfi_restore_state
+ 574:Src/main.c    ****   }
+ 6848              		.loc 2 574 5 is_stmt 1 view .LVU2234
+ 6849 009e FFF7FEFF 		bl	Error_Handler
+ 6850              	.LVL513:
+ 6851              	.L296:
+ 581:Src/main.c    ****   }
+ 6852              		.loc 2 581 5 view .LVU2235
+ 6853 00a2 FFF7FEFF 		bl	Error_Handler
+ 6854              	.LVL514:
+ 6855              	.L297:
+ 595:Src/main.c    ****   }
+ARM GAS  /tmp/ccdsDELB.s 			page 483
+
+
+ 6856              		.loc 2 595 5 view .LVU2236
+ 6857 00a6 FFF7FEFF 		bl	Error_Handler
+ 6858              	.LVL515:
+ 6859              	.L299:
+ 6860 00aa 00BF     		.align	2
+ 6861              	.L298:
+ 6862 00ac 00380240 		.word	1073887232
+ 6863 00b0 00700040 		.word	1073770496
+ 6864              		.cfi_endproc
+ 6865              	.LFE1187:
+ 6867              		.section	.text.main,"ax",%progbits
+ 6868              		.align	1
+ 6869              		.global	main
+ 6870              		.syntax unified
+ 6871              		.thumb
+ 6872              		.thumb_func
+ 6873              		.fpu fpv5-d16
+ 6875              	main:
+ 6876              	.LFB1186:
+ 115:Src/main.c    ****   /* USER CODE BEGIN 1 */
+ 6877              		.loc 2 115 1 view -0
+ 6878              		.cfi_startproc
+ 6879              		@ args = 0, pretend = 0, frame = 0
+ 6880              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6881 0000 2DE9F843 		push	{r3, r4, r5, r6, r7, r8, r9, lr}
+ 6882              	.LCFI64:
+ 6883              		.cfi_def_cfa_offset 32
+ 6884              		.cfi_offset 3, -32
+ 6885              		.cfi_offset 4, -28
+ 6886              		.cfi_offset 5, -24
+ 6887              		.cfi_offset 6, -20
+ 6888              		.cfi_offset 7, -16
+ 6889              		.cfi_offset 8, -12
+ 6890              		.cfi_offset 9, -8
+ 6891              		.cfi_offset 14, -4
+ 117:Src/main.c    ****   /* USER CODE END 1 */
+ 6892              		.loc 2 117 2 view .LVU2238
+ 123:Src/main.c    **** 
+ 6893              		.loc 2 123 3 view .LVU2239
+ 6894 0004 FFF7FEFF 		bl	HAL_Init
+ 6895              	.LVL516:
+ 130:Src/main.c    **** 
+ 6896              		.loc 2 130 3 view .LVU2240
+ 6897 0008 FFF7FEFF 		bl	SystemClock_Config
+ 6898              	.LVL517:
+ 137:Src/main.c    ****   MX_DMA_Init();
+ 6899              		.loc 2 137 3 view .LVU2241
+ 6900 000c FFF7FEFF 		bl	MX_GPIO_Init
+ 6901              	.LVL518:
+ 138:Src/main.c    ****   MX_SPI4_Init();
+ 6902              		.loc 2 138 3 view .LVU2242
+ 6903 0010 FFF7FEFF 		bl	MX_DMA_Init
+ 6904              	.LVL519:
+ 139:Src/main.c    ****   MX_FATFS_Init();
+ 6905              		.loc 2 139 3 view .LVU2243
+ 6906 0014 FFF7FEFF 		bl	MX_SPI4_Init
+ 6907              	.LVL520:
+ARM GAS  /tmp/ccdsDELB.s 			page 484
+
+
+ 140:Src/main.c    ****   MX_TIM2_Init();
+ 6908              		.loc 2 140 3 view .LVU2244
+ 6909 0018 FFF7FEFF 		bl	MX_FATFS_Init
+ 6910              	.LVL521:
+ 141:Src/main.c    ****   MX_TIM5_Init();
+ 6911              		.loc 2 141 3 view .LVU2245
+ 6912 001c FFF7FEFF 		bl	MX_TIM2_Init
+ 6913              	.LVL522:
+ 142:Src/main.c    ****   MX_ADC1_Init();
+ 6914              		.loc 2 142 3 view .LVU2246
+ 6915 0020 FFF7FEFF 		bl	MX_TIM5_Init
+ 6916              	.LVL523:
+ 143:Src/main.c    ****   MX_ADC3_Init();
+ 6917              		.loc 2 143 3 view .LVU2247
+ 6918 0024 FFF7FEFF 		bl	MX_ADC1_Init
+ 6919              	.LVL524:
+ 144:Src/main.c    ****   MX_SPI2_Init();
+ 6920              		.loc 2 144 3 view .LVU2248
+ 6921 0028 FFF7FEFF 		bl	MX_ADC3_Init
+ 6922              	.LVL525:
+ 145:Src/main.c    ****   MX_SPI5_Init();
+ 6923              		.loc 2 145 3 view .LVU2249
+ 6924 002c FFF7FEFF 		bl	MX_SPI2_Init
+ 6925              	.LVL526:
+ 146:Src/main.c    ****   MX_SPI6_Init();
+ 6926              		.loc 2 146 3 view .LVU2250
+ 6927 0030 FFF7FEFF 		bl	MX_SPI5_Init
+ 6928              	.LVL527:
+ 147:Src/main.c    ****   MX_USART1_UART_Init();
+ 6929              		.loc 2 147 3 view .LVU2251
+ 6930 0034 FFF7FEFF 		bl	MX_SPI6_Init
+ 6931              	.LVL528:
+ 148:Src/main.c    ****   MX_SDMMC1_SD_Init();
+ 6932              		.loc 2 148 3 view .LVU2252
+ 6933 0038 FFF7FEFF 		bl	MX_USART1_UART_Init
+ 6934              	.LVL529:
+ 149:Src/main.c    ****   MX_TIM7_Init();
+ 6935              		.loc 2 149 3 view .LVU2253
+ 6936 003c FFF7FEFF 		bl	MX_SDMMC1_SD_Init
+ 6937              	.LVL530:
+ 150:Src/main.c    ****   MX_TIM6_Init();
+ 6938              		.loc 2 150 3 view .LVU2254
+ 6939 0040 FFF7FEFF 		bl	MX_TIM7_Init
+ 6940              	.LVL531:
+ 151:Src/main.c    ****   MX_TIM10_Init();
+ 6941              		.loc 2 151 3 view .LVU2255
+ 6942 0044 FFF7FEFF 		bl	MX_TIM6_Init
+ 6943              	.LVL532:
+ 152:Src/main.c    ****   /* USER CODE BEGIN 2 */
+ 6944              		.loc 2 152 3 view .LVU2256
+ 6945 0048 FFF7FEFF 		bl	MX_TIM10_Init
+ 6946              	.LVL533:
+ 154:Src/main.c    ****   /* USER CODE END 2 */
+ 6947              		.loc 2 154 2 view .LVU2257
+ 6948 004c FFF7FEFF 		bl	Init_params
+ 6949              	.LVL534:
+ 6950 0050 3FE0     		b	.L301
+ARM GAS  /tmp/ccdsDELB.s 			page 485
+
+
+ 6951              	.L352:
+ 161:Src/main.c    **** 		{
+ 6952              		.loc 2 161 85 is_stmt 0 discriminator 1 view .LVU2258
+ 6953 0052 744B     		ldr	r3, .L359
+ 6954 0054 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 161:Src/main.c    **** 		{
+ 6955              		.loc 2 161 73 discriminator 1 view .LVU2259
+ 6956 0056 002B     		cmp	r3, #0
+ 6957 0058 42D1     		bne	.L302
+ 6958              	.L303:
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 6959              		.loc 7 3073 3 is_stmt 1 view .LVU2260
+ 6960              	.LBB539:
+ 6961              	.LBB540:
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 6962              		.loc 7 3073 3 view .LVU2261
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 6963              		.loc 7 3073 3 view .LVU2262
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 6964              		.loc 7 3073 3 view .LVU2263
+ 6965 005a 734B     		ldr	r3, .L359+4
+ 6966              	.LVL535:
+ 6967              	.LBB541:
+ 6968              	.LBI541:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6969              		.loc 8 1068 31 view .LVU2264
+ 6970              	.LBB542:
+1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6971              		.loc 8 1070 5 view .LVU2265
+1072:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6972              		.loc 8 1072 4 view .LVU2266
+ 6973              		.syntax unified
+ 6974              	@ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6975 005c 53E8002F 		ldrex r2, [r3]
+ 6976              	@ 0 "" 2
+ 6977              	.LVL536:
+1073:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6978              		.loc 8 1073 4 view .LVU2267
+1073:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 6979              		.loc 8 1073 4 is_stmt 0 view .LVU2268
+ 6980              		.thumb
+ 6981              		.syntax unified
+ 6982              	.LBE542:
+ 6983              	.LBE541:
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 6984              		.loc 7 3073 3 view .LVU2269
+ 6985 0060 42F48072 		orr	r2, r2, #256
+ 6986              	.LVL537:
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 6987              		.loc 7 3073 3 is_stmt 1 view .LVU2270
+ 6988              	.LBB543:
+ 6989              	.LBI543:
+1119:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 6990              		.loc 8 1119 31 view .LVU2271
+ 6991              	.LBB544:
+1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 6992              		.loc 8 1121 4 view .LVU2272
+ARM GAS  /tmp/ccdsDELB.s 			page 486
+
+
+1123:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 6993              		.loc 8 1123 4 view .LVU2273
+ 6994              		.syntax unified
+ 6995              	@ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 6996 0064 43E80021 		strex r1, r2, [r3]
+ 6997              	@ 0 "" 2
+ 6998              	.LVL538:
+ 6999              		.loc 8 1124 4 view .LVU2274
+ 7000              		.loc 8 1124 4 is_stmt 0 view .LVU2275
+ 7001              		.thumb
+ 7002              		.syntax unified
+ 7003              	.LBE544:
+ 7004              	.LBE543:
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7005              		.loc 7 3073 3 view .LVU2276
+ 7006 0068 0029     		cmp	r1, #0
+ 7007 006a F6D1     		bne	.L303
+ 7008              	.LVL539:
+ 7009              	.L304:
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7010              		.loc 7 3073 3 view .LVU2277
+ 7011              	.LBE540:
+ 7012              	.LBE539:
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7013              		.loc 7 3040 3 is_stmt 1 view .LVU2278
+ 7014              	.LBB545:
+ 7015              	.LBB546:
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7016              		.loc 7 3040 3 view .LVU2279
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7017              		.loc 7 3040 3 view .LVU2280
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7018              		.loc 7 3040 3 view .LVU2281
+ 7019              	.LBB547:
+ 7020              	.LBI547:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7021              		.loc 8 1068 31 view .LVU2282
+ 7022              	.LBB548:
+1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7023              		.loc 8 1070 5 view .LVU2283
+1072:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7024              		.loc 8 1072 4 view .LVU2284
+ 7025              		.syntax unified
+ 7026              	@ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7027 006c 53E8002F 		ldrex r2, [r3]
+ 7028              	@ 0 "" 2
+ 7029              	.LVL540:
+1073:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7030              		.loc 8 1073 4 view .LVU2285
+1073:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7031              		.loc 8 1073 4 is_stmt 0 view .LVU2286
+ 7032              		.thumb
+ 7033              		.syntax unified
+ 7034              	.LBE548:
+ 7035              	.LBE547:
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7036              		.loc 7 3040 3 view .LVU2287
+ARM GAS  /tmp/ccdsDELB.s 			page 487
+
+
+ 7037 0070 42F02002 		orr	r2, r2, #32
+ 7038              	.LVL541:
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7039              		.loc 7 3040 3 is_stmt 1 view .LVU2288
+ 7040              	.LBB549:
+ 7041              	.LBI549:
+1119:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7042              		.loc 8 1119 31 view .LVU2289
+ 7043              	.LBB550:
+1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7044              		.loc 8 1121 4 view .LVU2290
+1123:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7045              		.loc 8 1123 4 view .LVU2291
+ 7046              		.syntax unified
+ 7047              	@ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7048 0074 43E80021 		strex r1, r2, [r3]
+ 7049              	@ 0 "" 2
+ 7050              	.LVL542:
+ 7051              		.loc 8 1124 4 view .LVU2292
+ 7052              		.loc 8 1124 4 is_stmt 0 view .LVU2293
+ 7053              		.thumb
+ 7054              		.syntax unified
+ 7055              	.LBE550:
+ 7056              	.LBE549:
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7057              		.loc 7 3040 3 view .LVU2294
+ 7058 0078 0029     		cmp	r1, #0
+ 7059 007a F7D1     		bne	.L304
+ 7060              	.LVL543:
+ 7061              	.L305:
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7062              		.loc 7 3040 3 view .LVU2295
+ 7063              	.LBE546:
+ 7064              	.LBE545:
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7065              		.loc 7 3136 3 is_stmt 1 view .LVU2296
+ 7066              	.LBB551:
+ 7067              	.LBB552:
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7068              		.loc 7 3136 3 view .LVU2297
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7069              		.loc 7 3136 3 view .LVU2298
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7070              		.loc 7 3136 3 view .LVU2299
+ 7071 007c 6B4A     		ldr	r2, .L359+8
+ 7072              	.LVL544:
+ 7073              	.LBB553:
+ 7074              	.LBI553:
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7075              		.loc 8 1068 31 view .LVU2300
+ 7076              	.LBB554:
+1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7077              		.loc 8 1070 5 view .LVU2301
+1072:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7078              		.loc 8 1072 4 view .LVU2302
+ 7079              		.syntax unified
+ 7080              	@ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ARM GAS  /tmp/ccdsDELB.s 			page 488
+
+
+ 7081 007e 52E8003F 		ldrex r3, [r2]
+ 7082              	@ 0 "" 2
+ 7083              	.LVL545:
+1073:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7084              		.loc 8 1073 4 view .LVU2303
+1073:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 7085              		.loc 8 1073 4 is_stmt 0 view .LVU2304
+ 7086              		.thumb
+ 7087              		.syntax unified
+ 7088              	.LBE554:
+ 7089              	.LBE553:
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7090              		.loc 7 3136 3 view .LVU2305
+ 7091 0082 43F00103 		orr	r3, r3, #1
+ 7092              	.LVL546:
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7093              		.loc 7 3136 3 is_stmt 1 view .LVU2306
+ 7094              	.LBB555:
+ 7095              	.LBI555:
+1119:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 7096              		.loc 8 1119 31 view .LVU2307
+ 7097              	.LBB556:
+1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 7098              		.loc 8 1121 4 view .LVU2308
+1123:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 7099              		.loc 8 1123 4 view .LVU2309
+ 7100              		.syntax unified
+ 7101              	@ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 7102 0086 42E80031 		strex r1, r3, [r2]
+ 7103              	@ 0 "" 2
+ 7104              	.LVL547:
+ 7105              		.loc 8 1124 4 view .LVU2310
+ 7106              		.loc 8 1124 4 is_stmt 0 view .LVU2311
+ 7107              		.thumb
+ 7108              		.syntax unified
+ 7109              	.LBE556:
+ 7110              	.LBE555:
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7111              		.loc 7 3136 3 view .LVU2312
+ 7112 008a 0029     		cmp	r1, #0
+ 7113 008c F6D1     		bne	.L305
+ 7114              	.LBE552:
+ 7115              	.LBE551:
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 7116              		.loc 7 3136 3 is_stmt 1 view .LVU2313
+ 7117              	.LVL548:
+ 167:Src/main.c    **** 			NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag...
+ 7118              		.loc 2 167 4 view .LVU2314
+ 7119              	.LBB557:
+ 7120              	.LBI557:
+2024:Drivers/CMSIS/Include/core_cm7.h **** {
+ 7121              		.loc 1 2024 22 view .LVU2315
+ 7122              	.LBB558:
+2026:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 7123              		.loc 1 2026 3 view .LVU2316
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 7124              		.loc 1 2028 5 view .LVU2317
+ARM GAS  /tmp/ccdsDELB.s 			page 489
+
+
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 7125              		.loc 1 2028 47 is_stmt 0 view .LVU2318
+ 7126 008e 684B     		ldr	r3, .L359+12
+ 7127 0090 0022     		movs	r2, #0
+ 7128 0092 83F82523 		strb	r2, [r3, #805]
+ 7129              	.LVL549:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 7130              		.loc 1 2028 47 view .LVU2319
+ 7131              	.LBE558:
+ 7132              	.LBE557:
+ 168:Src/main.c    **** 			u_rx_flg = 1;
+ 7133              		.loc 2 168 4 is_stmt 1 view .LVU2320
+ 7134              	.LBB559:
+ 7135              	.LBI559:
+1896:Drivers/CMSIS/Include/core_cm7.h **** {
+ 7136              		.loc 1 1896 22 view .LVU2321
+ 7137              	.LBB560:
+1898:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 7138              		.loc 1 1898 3 view .LVU2322
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 7139              		.loc 1 1900 5 view .LVU2323
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 7140              		.loc 1 1900 43 is_stmt 0 view .LVU2324
+ 7141 0096 2022     		movs	r2, #32
+ 7142 0098 5A60     		str	r2, [r3, #4]
+ 7143              	.LVL550:
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 7144              		.loc 1 1900 43 view .LVU2325
+ 7145              	.LBE560:
+ 7146              	.LBE559:
+ 169:Src/main.c    **** 		}
+ 7147              		.loc 2 169 4 is_stmt 1 view .LVU2326
+ 169:Src/main.c    **** 		}
+ 7148              		.loc 2 169 13 is_stmt 0 view .LVU2327
+ 7149 009a 624B     		ldr	r3, .L359
+ 7150 009c 0122     		movs	r2, #1
+ 7151 009e 1A70     		strb	r2, [r3]
+ 7152 00a0 1EE0     		b	.L302
+ 7153              	.L317:
+ 179:Src/main.c    **** 					task.current_param = task.min_param;
+ 7154              		.loc 2 179 6 is_stmt 1 view .LVU2328
+ 179:Src/main.c    **** 					task.current_param = task.min_param;
+ 7155              		.loc 2 179 20 is_stmt 0 view .LVU2329
+ 7156 00a2 644B     		ldr	r3, .L359+16
+ 7157 00a4 0022     		movs	r2, #0
+ 7158 00a6 1A70     		strb	r2, [r3]
+ 180:Src/main.c    **** 					Stop_TIM10();
+ 7159              		.loc 2 180 6 is_stmt 1 view .LVU2330
+ 180:Src/main.c    **** 					Stop_TIM10();
+ 7160              		.loc 2 180 31 is_stmt 0 view .LVU2331
+ 7161 00a8 634B     		ldr	r3, .L359+20
+ 7162 00aa 5A68     		ldr	r2, [r3, #4]	@ float
+ 180:Src/main.c    **** 					Stop_TIM10();
+ 7163              		.loc 2 180 25 view .LVU2332
+ 7164 00ac 1A61     		str	r2, [r3, #16]	@ float
+ 181:Src/main.c    **** 				break;
+ 7165              		.loc 2 181 6 is_stmt 1 view .LVU2333
+ARM GAS  /tmp/ccdsDELB.s 			page 490
+
+
+ 7166 00ae FFF7FEFF 		bl	Stop_TIM10
+ 7167              	.LVL551:
+ 182:Src/main.c    **** 				case DECODE_ENABLE://1 - Decode rec. message
+ 7168              		.loc 2 182 5 view .LVU2334
+ 7169              	.L306:
+ 490:Src/main.c    **** 		{
+ 7170              		.loc 2 490 3 view .LVU2335
+ 7171 00b2 624B     		ldr	r3, .L359+24
+ 7172 00b4 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 7173 00b6 022B     		cmp	r3, #2
+ 7174 00b8 00F07583 		beq	.L341
+ 7175 00bc 032B     		cmp	r3, #3
+ 7176 00be 00F0A683 		beq	.L348
+ 7177 00c2 012B     		cmp	r3, #1
+ 7178 00c4 00F06483 		beq	.L350
+ 7179              	.L343:
+ 532:Src/main.c    **** 		{
+ 7180              		.loc 2 532 5 view .LVU2336
+ 532:Src/main.c    **** 		{
+ 7181              		.loc 2 532 17 is_stmt 0 view .LVU2337
+ 7182 00c8 5D4B     		ldr	r3, .L359+28
+ 7183 00ca 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 532:Src/main.c    **** 		{
+ 7184              		.loc 2 532 8 view .LVU2338
+ 7185 00cc 012B     		cmp	r3, #1
+ 7186 00ce 00F0A083 		beq	.L351
+ 7187              	.L301:
+ 159:Src/main.c    ****   {
+ 7188              		.loc 2 159 3 is_stmt 1 view .LVU2339
+ 161:Src/main.c    **** 		{
+ 7189              		.loc 2 161 3 view .LVU2340
+ 161:Src/main.c    **** 		{
+ 7190              		.loc 2 161 8 is_stmt 0 view .LVU2341
+ 7191 00d2 4FF48071 		mov	r1, #256
+ 7192 00d6 5B48     		ldr	r0, .L359+32
+ 7193 00d8 FFF7FEFF 		bl	HAL_GPIO_ReadPin
+ 7194              	.LVL552:
+ 161:Src/main.c    **** 		{
+ 7195              		.loc 2 161 6 view .LVU2342
+ 7196 00dc 0128     		cmp	r0, #1
+ 7197 00de B8D0     		beq	.L352
+ 7198              	.L302:
+ 176:Src/main.c    **** 			{
+ 7199              		.loc 2 176 4 is_stmt 1 view .LVU2343
+ 7200 00e0 594B     		ldr	r3, .L359+36
+ 7201 00e2 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 7202 00e4 092B     		cmp	r3, #9
+ 7203 00e6 E4D8     		bhi	.L306
+ 7204 00e8 01A2     		adr	r2, .L308
+ 7205 00ea 52F823F0 		ldr	pc, [r2, r3, lsl #2]
+ 7206 00ee 00BF     		.p2align 2
+ 7207              	.L308:
+ 7208 00f0 A3000000 		.word	.L317+1
+ 7209 00f4 19010000 		.word	.L316+1
+ 7210 00f8 83010000 		.word	.L315+1
+ 7211 00fc B9010000 		.word	.L314+1
+ 7212 0100 E9010000 		.word	.L313+1
+ARM GAS  /tmp/ccdsDELB.s 			page 491
+
+
+ 7213 0104 F9010000 		.word	.L312+1
+ 7214 0108 15020000 		.word	.L311+1
+ 7215 010c 79020000 		.word	.L310+1
+ 7216 0110 C9030000 		.word	.L309+1
+ 7217 0114 0F040000 		.word	.L307+1
+ 7218              		.p2align 1
+ 7219              	.L316:
+ 184:Src/main.c    **** 					if (CheckChecksum(COMMAND))
+ 7220              		.loc 2 184 6 view .LVU2344
+ 184:Src/main.c    **** 					if (CheckChecksum(COMMAND))
+ 7221              		.loc 2 184 18 is_stmt 0 view .LVU2345
+ 7222 0118 4C4C     		ldr	r4, .L359+40
+ 7223 011a 0D21     		movs	r1, #13
+ 7224 011c 2046     		mov	r0, r4
+ 7225 011e FFF7FEFF 		bl	CalculateChecksum
+ 7226              	.LVL553:
+ 184:Src/main.c    **** 					if (CheckChecksum(COMMAND))
+ 7227              		.loc 2 184 16 view .LVU2346
+ 7228 0122 4B4B     		ldr	r3, .L359+44
+ 7229 0124 1880     		strh	r0, [r3]	@ movhi
+ 185:Src/main.c    **** 					{
+ 7230              		.loc 2 185 6 is_stmt 1 view .LVU2347
+ 185:Src/main.c    **** 					{
+ 7231              		.loc 2 185 10 is_stmt 0 view .LVU2348
+ 7232 0126 2046     		mov	r0, r4
+ 7233 0128 FFF7FEFF 		bl	CheckChecksum
+ 7234              	.LVL554:
+ 185:Src/main.c    **** 					{
+ 7235              		.loc 2 185 9 view .LVU2349
+ 7236 012c 70B9     		cbnz	r0, .L353
+ 198:Src/main.c    **** 						CPU_state = DEFAULT_ENABLE;
+ 7237              		.loc 2 198 7 is_stmt 1 view .LVU2350
+ 198:Src/main.c    **** 						CPU_state = DEFAULT_ENABLE;
+ 7238              		.loc 2 198 21 is_stmt 0 view .LVU2351
+ 7239 012e 494A     		ldr	r2, .L359+48
+ 7240 0130 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
+ 7241 0132 43F00403 		orr	r3, r3, #4
+ 7242 0136 1370     		strb	r3, [r2]
+ 199:Src/main.c    **** 						CPU_state_old = HALT;//Save main current cycle
+ 7243              		.loc 2 199 7 is_stmt 1 view .LVU2352
+ 199:Src/main.c    **** 						CPU_state_old = HALT;//Save main current cycle
+ 7244              		.loc 2 199 17 is_stmt 0 view .LVU2353
+ 7245 0138 434B     		ldr	r3, .L359+36
+ 7246 013a 0222     		movs	r2, #2
+ 7247 013c 1A70     		strb	r2, [r3]
+ 200:Src/main.c    **** 					}
+ 7248              		.loc 2 200 7 is_stmt 1 view .LVU2354
+ 200:Src/main.c    **** 					}
+ 7249              		.loc 2 200 21 is_stmt 0 view .LVU2355
+ 7250 013e 3D4B     		ldr	r3, .L359+16
+ 7251 0140 0022     		movs	r2, #0
+ 7252 0142 1A70     		strb	r2, [r3]
+ 7253              	.L319:
+ 202:Src/main.c    **** 				break;
+ 7254              		.loc 2 202 6 is_stmt 1 view .LVU2356
+ 202:Src/main.c    **** 				break;
+ 7255              		.loc 2 202 32 is_stmt 0 view .LVU2357
+ARM GAS  /tmp/ccdsDELB.s 			page 492
+
+
+ 7256 0144 3D4B     		ldr	r3, .L359+24
+ 7257 0146 0122     		movs	r2, #1
+ 7258 0148 1A70     		strb	r2, [r3]
+ 203:Src/main.c    **** 				case DEFAULT_ENABLE://2 - Go to HALT
+ 7259              		.loc 2 203 5 is_stmt 1 view .LVU2358
+ 7260 014a B2E7     		b	.L306
+ 7261              	.L353:
+ 187:Src/main.c    **** 						LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2
+ 7262              		.loc 2 187 7 view .LVU2359
+ 7263              	.LVL555:
+ 7264              	.LBB561:
+ 7265              	.LBI561:
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 7266              		.loc 4 358 22 view .LVU2360
+ 7267              	.LBB562:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 7268              		.loc 4 360 3 view .LVU2361
+ 7269 014c 424A     		ldr	r2, .L359+52
+ 7270 014e 1368     		ldr	r3, [r2]
+ 7271 0150 43F04003 		orr	r3, r3, #64
+ 7272 0154 1360     		str	r3, [r2]
+ 7273              	.LVL556:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 7274              		.loc 4 360 3 is_stmt 0 view .LVU2362
+ 7275              	.LBE562:
+ 7276              	.LBE561:
+ 188:Src/main.c    **** 						Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup);
+ 7277              		.loc 2 188 7 is_stmt 1 view .LVU2363
+ 7278              	.LBB563:
+ 7279              	.LBI563:
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 7280              		.loc 4 358 22 view .LVU2364
+ 7281              	.LBB564:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 7282              		.loc 4 360 3 view .LVU2365
+ 7283 0156 02F58E32 		add	r2, r2, #72704
+ 7284 015a 1368     		ldr	r3, [r2]
+ 7285 015c 43F04003 		orr	r3, r3, #64
+ 7286 0160 1360     		str	r3, [r2]
+ 7287              	.LVL557:
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 7288              		.loc 4 360 3 is_stmt 0 view .LVU2366
+ 7289              	.LBE564:
+ 7290              	.LBE563:
+ 189:Src/main.c    **** 						TO6_before = TO6;
+ 7291              		.loc 2 189 7 is_stmt 1 view .LVU2367
+ 7292 0162 3E4B     		ldr	r3, .L359+56
+ 7293 0164 3E4A     		ldr	r2, .L359+60
+ 7294 0166 3F49     		ldr	r1, .L359+64
+ 7295 0168 2046     		mov	r0, r4
+ 7296 016a FFF7FEFF 		bl	Decode_uart
+ 7297              	.LVL558:
+ 190:Src/main.c    **** 						//LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP;
+ 7298              		.loc 2 190 7 view .LVU2368
+ 190:Src/main.c    **** 						//LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP;
+ 7299              		.loc 2 190 18 is_stmt 0 view .LVU2369
+ 7300 016e 3E4B     		ldr	r3, .L359+68
+ARM GAS  /tmp/ccdsDELB.s 			page 493
+
+
+ 7301 0170 1A68     		ldr	r2, [r3]
+ 7302 0172 3E4B     		ldr	r3, .L359+72
+ 7303 0174 1A60     		str	r2, [r3]
+ 193:Src/main.c    **** 						CPU_state_old = WORK_ENABLE;//Save main current cycle
+ 7304              		.loc 2 193 7 is_stmt 1 view .LVU2370
+ 193:Src/main.c    **** 						CPU_state_old = WORK_ENABLE;//Save main current cycle
+ 7305              		.loc 2 193 17 is_stmt 0 view .LVU2371
+ 7306 0176 0723     		movs	r3, #7
+ 7307 0178 334A     		ldr	r2, .L359+36
+ 7308 017a 1370     		strb	r3, [r2]
+ 194:Src/main.c    **** 					}
+ 7309              		.loc 2 194 7 is_stmt 1 view .LVU2372
+ 194:Src/main.c    **** 					}
+ 7310              		.loc 2 194 21 is_stmt 0 view .LVU2373
+ 7311 017c 2D4A     		ldr	r2, .L359+16
+ 7312 017e 1370     		strb	r3, [r2]
+ 7313 0180 E0E7     		b	.L319
+ 7314              	.L315:
+ 206:Src/main.c    **** 					Stop_TIM10();
+ 7315              		.loc 2 206 6 is_stmt 1 view .LVU2374
+ 206:Src/main.c    **** 					Stop_TIM10();
+ 7316              		.loc 2 206 31 is_stmt 0 view .LVU2375
+ 7317 0182 2D4B     		ldr	r3, .L359+20
+ 7318 0184 5A68     		ldr	r2, [r3, #4]	@ float
+ 206:Src/main.c    **** 					Stop_TIM10();
+ 7319              		.loc 2 206 25 view .LVU2376
+ 7320 0186 1A61     		str	r2, [r3, #16]	@ float
+ 207:Src/main.c    **** 					Init_params();
+ 7321              		.loc 2 207 6 is_stmt 1 view .LVU2377
+ 7322 0188 FFF7FEFF 		bl	Stop_TIM10
+ 7323              	.LVL559:
+ 208:Src/main.c    **** 					LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1
+ 7324              		.loc 2 208 6 view .LVU2378
+ 7325 018c FFF7FEFF 		bl	Init_params
+ 7326              	.LVL560:
+ 209:Src/main.c    **** 					LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2
+ 7327              		.loc 2 209 6 view .LVU2379
+ 7328              	.LBB565:
+ 7329              	.LBI565:
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 7330              		.loc 4 370 22 view .LVU2380
+ 7331              	.LBB566:
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 7332              		.loc 4 372 3 view .LVU2381
+ 7333 0190 314A     		ldr	r2, .L359+52
+ 7334 0192 1368     		ldr	r3, [r2]
+ 7335 0194 23F04003 		bic	r3, r3, #64
+ 7336 0198 1360     		str	r3, [r2]
+ 7337              	.LVL561:
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 7338              		.loc 4 372 3 is_stmt 0 view .LVU2382
+ 7339              	.LBE566:
+ 7340              	.LBE565:
+ 210:Src/main.c    **** 					CPU_state = HALT;
+ 7341              		.loc 2 210 6 is_stmt 1 view .LVU2383
+ 7342              	.LBB567:
+ 7343              	.LBI567:
+ARM GAS  /tmp/ccdsDELB.s 			page 494
+
+
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 7344              		.loc 4 370 22 view .LVU2384
+ 7345              	.LBB568:
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 7346              		.loc 4 372 3 view .LVU2385
+ 7347 019a 02F58E32 		add	r2, r2, #72704
+ 7348 019e 1368     		ldr	r3, [r2]
+ 7349 01a0 23F04003 		bic	r3, r3, #64
+ 7350 01a4 1360     		str	r3, [r2]
+ 7351              	.LVL562:
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 7352              		.loc 4 372 3 is_stmt 0 view .LVU2386
+ 7353              	.LBE568:
+ 7354              	.LBE567:
+ 211:Src/main.c    **** 					CPU_state_old = HALT;//Save main current cycle
+ 7355              		.loc 2 211 6 is_stmt 1 view .LVU2387
+ 211:Src/main.c    **** 					CPU_state_old = HALT;//Save main current cycle
+ 7356              		.loc 2 211 16 is_stmt 0 view .LVU2388
+ 7357 01a6 0023     		movs	r3, #0
+ 7358 01a8 274A     		ldr	r2, .L359+36
+ 7359 01aa 1370     		strb	r3, [r2]
+ 212:Src/main.c    **** 					UART_transmission_request = MESS_01;
+ 7360              		.loc 2 212 6 is_stmt 1 view .LVU2389
+ 212:Src/main.c    **** 					UART_transmission_request = MESS_01;
+ 7361              		.loc 2 212 20 is_stmt 0 view .LVU2390
+ 7362 01ac 214A     		ldr	r2, .L359+16
+ 7363 01ae 1370     		strb	r3, [r2]
+ 213:Src/main.c    **** 				break;
+ 7364              		.loc 2 213 6 is_stmt 1 view .LVU2391
+ 213:Src/main.c    **** 				break;
+ 7365              		.loc 2 213 32 is_stmt 0 view .LVU2392
+ 7366 01b0 224B     		ldr	r3, .L359+24
+ 7367 01b2 0122     		movs	r2, #1
+ 7368 01b4 1A70     		strb	r2, [r3]
+ 214:Src/main.c    **** 				case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting!
+ 7369              		.loc 2 214 5 is_stmt 1 view .LVU2393
+ 7370 01b6 7CE7     		b	.L306
+ 7371              	.L314:
+ 216:Src/main.c    **** 					State_Data[0]|=temp16&0xff;
+ 7372              		.loc 2 216 6 view .LVU2394
+ 216:Src/main.c    **** 					State_Data[0]|=temp16&0xff;
+ 7373              		.loc 2 216 15 is_stmt 0 view .LVU2395
+ 7374 01b8 2D48     		ldr	r0, .L359+76
+ 7375 01ba FFF7FEFF 		bl	SD_READ
+ 7376              	.LVL563:
+ 216:Src/main.c    **** 					State_Data[0]|=temp16&0xff;
+ 7377              		.loc 2 216 13 view .LVU2396
+ 7378 01be 80B2     		uxth	r0, r0
+ 7379 01c0 2C4B     		ldr	r3, .L359+80
+ 7380 01c2 1880     		strh	r0, [r3]	@ movhi
+ 217:Src/main.c    **** 					if (temp16==0)
+ 7381              		.loc 2 217 6 is_stmt 1 view .LVU2397
+ 217:Src/main.c    **** 					if (temp16==0)
+ 7382              		.loc 2 217 19 is_stmt 0 view .LVU2398
+ 7383 01c4 234A     		ldr	r2, .L359+48
+ 7384 01c6 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
+ 7385 01c8 0343     		orrs	r3, r3, r0
+ARM GAS  /tmp/ccdsDELB.s 			page 495
+
+
+ 7386 01ca 1370     		strb	r3, [r2]
+ 218:Src/main.c    **** 					{	
+ 7387              		.loc 2 218 6 is_stmt 1 view .LVU2399
+ 218:Src/main.c    **** 					{	
+ 7388              		.loc 2 218 9 is_stmt 0 view .LVU2400
+ 7389 01cc 40B9     		cbnz	r0, .L320
+ 220:Src/main.c    **** 					}
+ 7390              		.loc 2 220 7 is_stmt 1 view .LVU2401
+ 220:Src/main.c    **** 					}
+ 7391              		.loc 2 220 33 is_stmt 0 view .LVU2402
+ 7392 01ce 1B4B     		ldr	r3, .L359+24
+ 7393 01d0 0322     		movs	r2, #3
+ 7394 01d2 1A70     		strb	r2, [r3]
+ 7395              	.L321:
+ 226:Src/main.c    **** 					CPU_state = CPU_state_old;//Return to main current cycle
+ 7396              		.loc 2 226 6 is_stmt 1 view .LVU2403
+ 226:Src/main.c    **** 					CPU_state = CPU_state_old;//Return to main current cycle
+ 7397              		.loc 2 226 20 is_stmt 0 view .LVU2404
+ 7398 01d4 0023     		movs	r3, #0
+ 7399 01d6 174A     		ldr	r2, .L359+16
+ 7400 01d8 1370     		strb	r3, [r2]
+ 227:Src/main.c    **** 				break;
+ 7401              		.loc 2 227 6 is_stmt 1 view .LVU2405
+ 227:Src/main.c    **** 				break;
+ 7402              		.loc 2 227 16 is_stmt 0 view .LVU2406
+ 7403 01da 1B4A     		ldr	r2, .L359+36
+ 7404 01dc 1370     		strb	r3, [r2]
+ 228:Src/main.c    **** 				case TRANS_ENABLE://4 - Transmith current packet
+ 7405              		.loc 2 228 5 is_stmt 1 view .LVU2407
+ 7406 01de 68E7     		b	.L306
+ 7407              	.L320:
+ 224:Src/main.c    **** 					}
+ 7408              		.loc 2 224 7 view .LVU2408
+ 224:Src/main.c    **** 					}
+ 7409              		.loc 2 224 33 is_stmt 0 view .LVU2409
+ 7410 01e0 164B     		ldr	r3, .L359+24
+ 7411 01e2 0122     		movs	r2, #1
+ 7412 01e4 1A70     		strb	r2, [r3]
+ 7413 01e6 F5E7     		b	.L321
+ 7414              	.L313:
+ 230:Src/main.c    **** 					CPU_state = CPU_state_old;//Return to main current cycle
+ 7415              		.loc 2 230 6 is_stmt 1 view .LVU2410
+ 230:Src/main.c    **** 					CPU_state = CPU_state_old;//Return to main current cycle
+ 7416              		.loc 2 230 32 is_stmt 0 view .LVU2411
+ 7417 01e8 144B     		ldr	r3, .L359+24
+ 7418 01ea 0222     		movs	r2, #2
+ 7419 01ec 1A70     		strb	r2, [r3]
+ 231:Src/main.c    **** 				break;
+ 7420              		.loc 2 231 6 is_stmt 1 view .LVU2412
+ 231:Src/main.c    **** 				break;
+ 7421              		.loc 2 231 16 is_stmt 0 view .LVU2413
+ 7422 01ee 114B     		ldr	r3, .L359+16
+ 7423 01f0 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
+ 7424 01f2 154B     		ldr	r3, .L359+36
+ 7425 01f4 1A70     		strb	r2, [r3]
+ 232:Src/main.c    **** 				case REMOVE_FILE://5 - Remove file from SD
+ 7426              		.loc 2 232 5 is_stmt 1 view .LVU2414
+ARM GAS  /tmp/ccdsDELB.s 			page 496
+
+
+ 7427 01f6 5CE7     		b	.L306
+ 7428              	.L312:
+ 234:Src/main.c    **** 					UART_transmission_request = MESS_01;
+ 7429              		.loc 2 234 6 view .LVU2415
+ 234:Src/main.c    **** 					UART_transmission_request = MESS_01;
+ 7430              		.loc 2 234 21 is_stmt 0 view .LVU2416
+ 7431 01f8 FFF7FEFF 		bl	SD_REMOVE
+ 7432              	.LVL564:
+ 234:Src/main.c    **** 					UART_transmission_request = MESS_01;
+ 7433              		.loc 2 234 19 view .LVU2417
+ 7434 01fc 154A     		ldr	r2, .L359+48
+ 7435 01fe 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
+ 7436 0200 0343     		orrs	r3, r3, r0
+ 7437 0202 1370     		strb	r3, [r2]
+ 235:Src/main.c    **** 					CPU_state = CPU_state_old;
+ 7438              		.loc 2 235 6 is_stmt 1 view .LVU2418
+ 235:Src/main.c    **** 					CPU_state = CPU_state_old;
+ 7439              		.loc 2 235 32 is_stmt 0 view .LVU2419
+ 7440 0204 0D4B     		ldr	r3, .L359+24
+ 7441 0206 0122     		movs	r2, #1
+ 7442 0208 1A70     		strb	r2, [r3]
+ 236:Src/main.c    **** 				break;
+ 7443              		.loc 2 236 6 is_stmt 1 view .LVU2420
+ 236:Src/main.c    **** 				break;
+ 7444              		.loc 2 236 16 is_stmt 0 view .LVU2421
+ 7445 020a 0A4B     		ldr	r3, .L359+16
+ 7446 020c 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
+ 7447 020e 0E4B     		ldr	r3, .L359+36
+ 7448 0210 1A70     		strb	r2, [r3]
+ 237:Src/main.c    **** 				case STATE://6 - Transmith state message
+ 7449              		.loc 2 237 5 is_stmt 1 view .LVU2422
+ 7450 0212 4EE7     		b	.L306
+ 7451              	.L311:
+ 239:Src/main.c    **** 					CPU_state = CPU_state_old;//Return to main current cycle
+ 7452              		.loc 2 239 6 view .LVU2423
+ 239:Src/main.c    **** 					CPU_state = CPU_state_old;//Return to main current cycle
+ 7453              		.loc 2 239 32 is_stmt 0 view .LVU2424
+ 7454 0214 094B     		ldr	r3, .L359+24
+ 7455 0216 0122     		movs	r2, #1
+ 7456 0218 1A70     		strb	r2, [r3]
+ 240:Src/main.c    **** 				break;
+ 7457              		.loc 2 240 6 is_stmt 1 view .LVU2425
+ 240:Src/main.c    **** 				break;
+ 7458              		.loc 2 240 16 is_stmt 0 view .LVU2426
+ 7459 021a 064B     		ldr	r3, .L359+16
+ 7460 021c 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
+ 7461 021e 0A4B     		ldr	r3, .L359+36
+ 7462 0220 1A70     		strb	r2, [r3]
+ 241:Src/main.c    **** 				case WORK_ENABLE://7 - Main work cycle
+ 7463              		.loc 2 241 5 is_stmt 1 view .LVU2427
+ 7464 0222 46E7     		b	.L306
+ 7465              	.L360:
+ 7466              		.align	2
+ 7467              	.L359:
+ 7468 0224 00000000 		.word	.LANCHOR16
+ 7469 0228 00100140 		.word	1073811456
+ 7470 022c 08100140 		.word	1073811464
+ARM GAS  /tmp/ccdsDELB.s 			page 497
+
+
+ 7471 0230 00E100E0 		.word	-536813312
+ 7472 0234 00000000 		.word	.LANCHOR35
+ 7473 0238 00000000 		.word	.LANCHOR1
+ 7474 023c 00000000 		.word	.LANCHOR37
+ 7475 0240 00000000 		.word	.LANCHOR11
+ 7476 0244 00000240 		.word	1073872896
+ 7477 0248 00000000 		.word	.LANCHOR27
+ 7478 024c 00000000 		.word	.LANCHOR26
+ 7479 0250 00000000 		.word	.LANCHOR34
+ 7480 0254 00000000 		.word	.LANCHOR36
+ 7481 0258 00380040 		.word	1073756160
+ 7482 025c 00000000 		.word	.LANCHOR20
+ 7483 0260 00000000 		.word	.LANCHOR22
+ 7484 0264 00000000 		.word	.LANCHOR21
+ 7485 0268 00000000 		.word	.LANCHOR7
+ 7486 026c 00000000 		.word	.LANCHOR9
+ 7487 0270 00000000 		.word	.LANCHOR6
+ 7488 0274 00000000 		.word	.LANCHOR38
+ 7489              	.L310:
+ 243:Src/main.c    **** 					Stop_TIM10();
+ 7490              		.loc 2 243 6 view .LVU2428
+ 243:Src/main.c    **** 					Stop_TIM10();
+ 7491              		.loc 2 243 31 is_stmt 0 view .LVU2429
+ 7492 0278 AC4B     		ldr	r3, .L361
+ 7493 027a 5A68     		ldr	r2, [r3, #4]	@ float
+ 243:Src/main.c    **** 					Stop_TIM10();
+ 7494              		.loc 2 243 25 view .LVU2430
+ 7495 027c 1A61     		str	r2, [r3, #16]	@ float
+ 244:Src/main.c    **** 					if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz)
+ 7496              		.loc 2 244 6 is_stmt 1 view .LVU2431
+ 7497 027e FFF7FEFF 		bl	Stop_TIM10
+ 7498              	.LVL565:
+ 245:Src/main.c    **** 					{
+ 7499              		.loc 2 245 6 view .LVU2432
+ 245:Src/main.c    **** 					{
+ 7500              		.loc 2 245 13 is_stmt 0 view .LVU2433
+ 7501 0282 AB4B     		ldr	r3, .L361+4
+ 7502 0284 1B68     		ldr	r3, [r3]
+ 7503 0286 AB4A     		ldr	r2, .L361+8
+ 7504 0288 1268     		ldr	r2, [r2]
+ 245:Src/main.c    **** 					{
+ 7505              		.loc 2 245 9 view .LVU2434
+ 7506 028a 9342     		cmp	r3, r2
+ 7507 028c 7FF611AF 		bls	.L306
+ 247:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 7508              		.loc 2 247 7 is_stmt 1 view .LVU2435
+ 247:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 7509              		.loc 2 247 18 is_stmt 0 view .LVU2436
+ 7510 0290 A84A     		ldr	r2, .L361+8
+ 7511 0292 1360     		str	r3, [r2]
+ 248:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 7512              		.loc 2 248 7 is_stmt 1 view .LVU2437
+ 248:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 7513              		.loc 2 248 25 is_stmt 0 view .LVU2438
+ 7514 0294 0120     		movs	r0, #1
+ 7515 0296 FFF7FEFF 		bl	MPhD_T
+ 7516              	.LVL566:
+ARM GAS  /tmp/ccdsDELB.s 			page 498
+
+
+ 248:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 7517              		.loc 2 248 23 view .LVU2439
+ 7518 029a A74F     		ldr	r7, .L361+12
+ 7519 029c 3881     		strh	r0, [r7, #8]	@ movhi
+ 249:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 7520              		.loc 2 249 7 is_stmt 1 view .LVU2440
+ 249:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 7521              		.loc 2 249 25 is_stmt 0 view .LVU2441
+ 7522 029e 0120     		movs	r0, #1
+ 7523 02a0 FFF7FEFF 		bl	MPhD_T
+ 7524              	.LVL567:
+ 249:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 7525              		.loc 2 249 23 view .LVU2442
+ 7526 02a4 3881     		strh	r0, [r7, #8]	@ movhi
+ 250:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 7527              		.loc 2 250 7 is_stmt 1 view .LVU2443
+ 250:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 7528              		.loc 2 250 25 is_stmt 0 view .LVU2444
+ 7529 02a6 0220     		movs	r0, #2
+ 7530 02a8 FFF7FEFF 		bl	MPhD_T
+ 7531              	.LVL568:
+ 250:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 7532              		.loc 2 250 23 view .LVU2445
+ 7533 02ac A34E     		ldr	r6, .L361+16
+ 7534 02ae 3081     		strh	r0, [r6, #8]	@ movhi
+ 251:Src/main.c    **** 						
+ 7535              		.loc 2 251 7 is_stmt 1 view .LVU2446
+ 251:Src/main.c    **** 						
+ 7536              		.loc 2 251 25 is_stmt 0 view .LVU2447
+ 7537 02b0 0220     		movs	r0, #2
+ 7538 02b2 FFF7FEFF 		bl	MPhD_T
+ 7539              	.LVL569:
+ 251:Src/main.c    **** 						
+ 7540              		.loc 2 251 23 view .LVU2448
+ 7541 02b6 3081     		strh	r0, [r6, #8]	@ movhi
+ 254:Src/main.c    **** 						LD1_param.LD_CURR_TEMP = MPhD_T(3);
+ 7542              		.loc 2 254 7 is_stmt 1 view .LVU2449
+ 254:Src/main.c    **** 						LD1_param.LD_CURR_TEMP = MPhD_T(3);
+ 7543              		.loc 2 254 14 is_stmt 0 view .LVU2450
+ 7544 02b8 0320     		movs	r0, #3
+ 7545 02ba FFF7FEFF 		bl	MPhD_T
+ 7546              	.LVL570:
+ 255:Src/main.c    **** 						(void) MPhD_T(4);
+ 7547              		.loc 2 255 7 is_stmt 1 view .LVU2451
+ 255:Src/main.c    **** 						(void) MPhD_T(4);
+ 7548              		.loc 2 255 32 is_stmt 0 view .LVU2452
+ 7549 02be 0320     		movs	r0, #3
+ 7550 02c0 FFF7FEFF 		bl	MPhD_T
+ 7551              	.LVL571:
+ 255:Src/main.c    **** 						(void) MPhD_T(4);
+ 7552              		.loc 2 255 30 view .LVU2453
+ 7553 02c4 3880     		strh	r0, [r7]	@ movhi
+ 256:Src/main.c    **** 						LD2_param.LD_CURR_TEMP = MPhD_T(4);
+ 7554              		.loc 2 256 7 is_stmt 1 view .LVU2454
+ 256:Src/main.c    **** 						LD2_param.LD_CURR_TEMP = MPhD_T(4);
+ 7555              		.loc 2 256 14 is_stmt 0 view .LVU2455
+ 7556 02c6 0420     		movs	r0, #4
+ARM GAS  /tmp/ccdsDELB.s 			page 499
+
+
+ 7557 02c8 FFF7FEFF 		bl	MPhD_T
+ 7558              	.LVL572:
+ 257:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 7559              		.loc 2 257 7 is_stmt 1 view .LVU2456
+ 257:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 7560              		.loc 2 257 32 is_stmt 0 view .LVU2457
+ 7561 02cc 0420     		movs	r0, #4
+ 7562 02ce FFF7FEFF 		bl	MPhD_T
+ 7563              	.LVL573:
+ 257:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 7564              		.loc 2 257 30 view .LVU2458
+ 7565 02d2 3080     		strh	r0, [r6]	@ movhi
+ 258:Src/main.c    **** 						Set_LTEC(3, temp16);//Drive Laser TEC 1
+ 7566              		.loc 2 258 7 is_stmt 1 view .LVU2459
+ 258:Src/main.c    **** 						Set_LTEC(3, temp16);//Drive Laser TEC 1
+ 7567              		.loc 2 258 14 is_stmt 0 view .LVU2460
+ 7568 02d4 DFF89882 		ldr	r8, .L361+68
+ 7569 02d8 0122     		movs	r2, #1
+ 7570 02da 3946     		mov	r1, r7
+ 7571 02dc 4046     		mov	r0, r8
+ 7572 02de FFF7FEFF 		bl	PID_Controller_Temp
+ 7573              	.LVL574:
+ 7574 02e2 0146     		mov	r1, r0
+ 258:Src/main.c    **** 						Set_LTEC(3, temp16);//Drive Laser TEC 1
+ 7575              		.loc 2 258 13 view .LVU2461
+ 7576 02e4 964D     		ldr	r5, .L361+20
+ 7577 02e6 2880     		strh	r0, [r5]	@ movhi
+ 259:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2);
+ 7578              		.loc 2 259 7 is_stmt 1 view .LVU2462
+ 7579 02e8 0320     		movs	r0, #3
+ 7580 02ea FFF7FEFF 		bl	Set_LTEC
+ 7581              	.LVL575:
+ 260:Src/main.c    **** 						Set_LTEC(4, temp16);//Drive Laser TEC 2
+ 7582              		.loc 2 260 7 view .LVU2463
+ 260:Src/main.c    **** 						Set_LTEC(4, temp16);//Drive Laser TEC 2
+ 7583              		.loc 2 260 14 is_stmt 0 view .LVU2464
+ 7584 02ee DFF87C92 		ldr	r9, .L361+64
+ 7585 02f2 0222     		movs	r2, #2
+ 7586 02f4 3146     		mov	r1, r6
+ 7587 02f6 4846     		mov	r0, r9
+ 7588 02f8 FFF7FEFF 		bl	PID_Controller_Temp
+ 7589              	.LVL576:
+ 7590 02fc 0146     		mov	r1, r0
+ 260:Src/main.c    **** 						Set_LTEC(4, temp16);//Drive Laser TEC 2
+ 7591              		.loc 2 260 13 view .LVU2465
+ 7592 02fe 2880     		strh	r0, [r5]	@ movhi
+ 261:Src/main.c    **** 						
+ 7593              		.loc 2 261 7 is_stmt 1 view .LVU2466
+ 7594 0300 0420     		movs	r0, #4
+ 7595 0302 FFF7FEFF 		bl	Set_LTEC
+ 7596              	.LVL577:
+ 263:Src/main.c    **** 						Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data
+ 7597              		.loc 2 263 7 view .LVU2467
+ 263:Src/main.c    **** 						Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data
+ 7598              		.loc 2 263 31 is_stmt 0 view .LVU2468
+ 7599 0306 3B89     		ldrh	r3, [r7, #8]
+ 263:Src/main.c    **** 						Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data
+ARM GAS  /tmp/ccdsDELB.s 			page 500
+
+
+ 7600              		.loc 2 263 20 view .LVU2469
+ 7601 0308 8E4C     		ldr	r4, .L361+24
+ 7602 030a 6380     		strh	r3, [r4, #2]	@ movhi
+ 264:Src/main.c    **** 
+ 7603              		.loc 2 264 7 is_stmt 1 view .LVU2470
+ 264:Src/main.c    **** 
+ 7604              		.loc 2 264 31 is_stmt 0 view .LVU2471
+ 7605 030c 3389     		ldrh	r3, [r6, #8]
+ 264:Src/main.c    **** 
+ 7606              		.loc 2 264 20 view .LVU2472
+ 7607 030e A380     		strh	r3, [r4, #4]	@ movhi
+ 266:Src/main.c    **** 						Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2
+ 7608              		.loc 2 266 7 is_stmt 1 view .LVU2473
+ 7609 0310 B8F80C10 		ldrh	r1, [r8, #12]
+ 7610 0314 0120     		movs	r0, #1
+ 7611 0316 FFF7FEFF 		bl	Set_LTEC
+ 7612              	.LVL578:
+ 267:Src/main.c    **** 
+ 7613              		.loc 2 267 7 view .LVU2474
+ 7614 031a B9F80C10 		ldrh	r1, [r9, #12]
+ 7615 031e 0220     		movs	r0, #2
+ 7616 0320 FFF7FEFF 		bl	Set_LTEC
+ 7617              	.LVL579:
+ 271:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 7618              		.loc 2 271 7 view .LVU2475
+ 271:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 7619              		.loc 2 271 16 is_stmt 0 view .LVU2476
+ 7620 0324 0020     		movs	r0, #0
+ 7621 0326 FFF7FEFF 		bl	Get_ADC
+ 7622              	.LVL580:
+ 271:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 7623              		.loc 2 271 14 view .LVU2477
+ 7624 032a 2880     		strh	r0, [r5]	@ movhi
+ 272:Src/main.c    **** 						Long_Data[7] = temp16;
+ 7625              		.loc 2 272 7 is_stmt 1 view .LVU2478
+ 272:Src/main.c    **** 						Long_Data[7] = temp16;
+ 7626              		.loc 2 272 16 is_stmt 0 view .LVU2479
+ 7627 032c 0120     		movs	r0, #1
+ 7628 032e FFF7FEFF 		bl	Get_ADC
+ 7629              	.LVL581:
+ 272:Src/main.c    **** 						Long_Data[7] = temp16;
+ 7630              		.loc 2 272 14 view .LVU2480
+ 7631 0332 2880     		strh	r0, [r5]	@ movhi
+ 273:Src/main.c    **** 						
+ 7632              		.loc 2 273 7 is_stmt 1 view .LVU2481
+ 273:Src/main.c    **** 						
+ 7633              		.loc 2 273 20 is_stmt 0 view .LVU2482
+ 7634 0334 E081     		strh	r0, [r4, #14]	@ movhi
+ 276:Src/main.c    **** 						Long_Data[8] = temp16;
+ 7635              		.loc 2 276 7 is_stmt 1 view .LVU2483
+ 276:Src/main.c    **** 						Long_Data[8] = temp16;
+ 7636              		.loc 2 276 16 is_stmt 0 view .LVU2484
+ 7637 0336 0120     		movs	r0, #1
+ 7638 0338 FFF7FEFF 		bl	Get_ADC
+ 7639              	.LVL582:
+ 276:Src/main.c    **** 						Long_Data[8] = temp16;
+ 7640              		.loc 2 276 14 view .LVU2485
+ARM GAS  /tmp/ccdsDELB.s 			page 501
+
+
+ 7641 033c 2880     		strh	r0, [r5]	@ movhi
+ 277:Src/main.c    **** 						
+ 7642              		.loc 2 277 7 is_stmt 1 view .LVU2486
+ 277:Src/main.c    **** 						
+ 7643              		.loc 2 277 20 is_stmt 0 view .LVU2487
+ 7644 033e 2082     		strh	r0, [r4, #16]	@ movhi
+ 280:Src/main.c    **** 						Long_Data[9] = temp16;
+ 7645              		.loc 2 280 7 is_stmt 1 view .LVU2488
+ 280:Src/main.c    **** 						Long_Data[9] = temp16;
+ 7646              		.loc 2 280 16 is_stmt 0 view .LVU2489
+ 7647 0340 0120     		movs	r0, #1
+ 7648 0342 FFF7FEFF 		bl	Get_ADC
+ 7649              	.LVL583:
+ 280:Src/main.c    **** 						Long_Data[9] = temp16;
+ 7650              		.loc 2 280 14 view .LVU2490
+ 7651 0346 2880     		strh	r0, [r5]	@ movhi
+ 281:Src/main.c    **** 						
+ 7652              		.loc 2 281 7 is_stmt 1 view .LVU2491
+ 281:Src/main.c    **** 						
+ 7653              		.loc 2 281 20 is_stmt 0 view .LVU2492
+ 7654 0348 6082     		strh	r0, [r4, #18]	@ movhi
+ 284:Src/main.c    **** 						Long_Data[10] = temp16;
+ 7655              		.loc 2 284 7 is_stmt 1 view .LVU2493
+ 284:Src/main.c    **** 						Long_Data[10] = temp16;
+ 7656              		.loc 2 284 16 is_stmt 0 view .LVU2494
+ 7657 034a 0120     		movs	r0, #1
+ 7658 034c FFF7FEFF 		bl	Get_ADC
+ 7659              	.LVL584:
+ 284:Src/main.c    **** 						Long_Data[10] = temp16;
+ 7660              		.loc 2 284 14 view .LVU2495
+ 7661 0350 2880     		strh	r0, [r5]	@ movhi
+ 285:Src/main.c    **** 						
+ 7662              		.loc 2 285 7 is_stmt 1 view .LVU2496
+ 285:Src/main.c    **** 						
+ 7663              		.loc 2 285 21 is_stmt 0 view .LVU2497
+ 7664 0352 A082     		strh	r0, [r4, #20]	@ movhi
+ 288:Src/main.c    **** 						Long_Data[11] = temp16;
+ 7665              		.loc 2 288 7 is_stmt 1 view .LVU2498
+ 288:Src/main.c    **** 						Long_Data[11] = temp16;
+ 7666              		.loc 2 288 16 is_stmt 0 view .LVU2499
+ 7667 0354 0120     		movs	r0, #1
+ 7668 0356 FFF7FEFF 		bl	Get_ADC
+ 7669              	.LVL585:
+ 288:Src/main.c    **** 						Long_Data[11] = temp16;
+ 7670              		.loc 2 288 14 view .LVU2500
+ 7671 035a 2880     		strh	r0, [r5]	@ movhi
+ 289:Src/main.c    **** 						temp16 = Get_ADC(2);
+ 7672              		.loc 2 289 7 is_stmt 1 view .LVU2501
+ 289:Src/main.c    **** 						temp16 = Get_ADC(2);
+ 7673              		.loc 2 289 21 is_stmt 0 view .LVU2502
+ 7674 035c E082     		strh	r0, [r4, #22]	@ movhi
+ 290:Src/main.c    **** 						
+ 7675              		.loc 2 290 7 is_stmt 1 view .LVU2503
+ 290:Src/main.c    **** 						
+ 7676              		.loc 2 290 16 is_stmt 0 view .LVU2504
+ 7677 035e 0220     		movs	r0, #2
+ 7678 0360 FFF7FEFF 		bl	Get_ADC
+ARM GAS  /tmp/ccdsDELB.s 			page 502
+
+
+ 7679              	.LVL586:
+ 290:Src/main.c    **** 						
+ 7680              		.loc 2 290 14 view .LVU2505
+ 7681 0364 2880     		strh	r0, [r5]	@ movhi
+ 293:Src/main.c    **** 						temp16 = Get_ADC(4);
+ 7682              		.loc 2 293 7 is_stmt 1 view .LVU2506
+ 293:Src/main.c    **** 						temp16 = Get_ADC(4);
+ 7683              		.loc 2 293 16 is_stmt 0 view .LVU2507
+ 7684 0366 0320     		movs	r0, #3
+ 7685 0368 FFF7FEFF 		bl	Get_ADC
+ 7686              	.LVL587:
+ 293:Src/main.c    **** 						temp16 = Get_ADC(4);
+ 7687              		.loc 2 293 14 view .LVU2508
+ 7688 036c 2880     		strh	r0, [r5]	@ movhi
+ 294:Src/main.c    **** 						Long_Data[12] = temp16;
+ 7689              		.loc 2 294 7 is_stmt 1 view .LVU2509
+ 294:Src/main.c    **** 						Long_Data[12] = temp16;
+ 7690              		.loc 2 294 16 is_stmt 0 view .LVU2510
+ 7691 036e 0420     		movs	r0, #4
+ 7692 0370 FFF7FEFF 		bl	Get_ADC
+ 7693              	.LVL588:
+ 294:Src/main.c    **** 						Long_Data[12] = temp16;
+ 7694              		.loc 2 294 14 view .LVU2511
+ 7695 0374 2880     		strh	r0, [r5]	@ movhi
+ 295:Src/main.c    **** 						temp16 = Get_ADC(5);
+ 7696              		.loc 2 295 7 is_stmt 1 view .LVU2512
+ 295:Src/main.c    **** 						temp16 = Get_ADC(5);
+ 7697              		.loc 2 295 21 is_stmt 0 view .LVU2513
+ 7698 0376 2083     		strh	r0, [r4, #24]	@ movhi
+ 296:Src/main.c    **** 													
+ 7699              		.loc 2 296 7 is_stmt 1 view .LVU2514
+ 296:Src/main.c    **** 													
+ 7700              		.loc 2 296 16 is_stmt 0 view .LVU2515
+ 7701 0378 0520     		movs	r0, #5
+ 7702 037a FFF7FEFF 		bl	Get_ADC
+ 7703              	.LVL589:
+ 296:Src/main.c    **** 													
+ 7704              		.loc 2 296 14 view .LVU2516
+ 7705 037e 2880     		strh	r0, [r5]	@ movhi
+ 299:Src/main.c    **** 						Long_Data[3] = (TO6_stop)&0xffff;
+ 7706              		.loc 2 299 7 is_stmt 1 view .LVU2517
+ 299:Src/main.c    **** 						Long_Data[3] = (TO6_stop)&0xffff;
+ 7707              		.loc 2 299 16 is_stmt 0 view .LVU2518
+ 7708 0380 714B     		ldr	r3, .L361+28
+ 7709 0382 1B68     		ldr	r3, [r3]
+ 7710 0384 714A     		ldr	r2, .L361+32
+ 7711 0386 1360     		str	r3, [r2]
+ 300:Src/main.c    **** 						Long_Data[4] = (TO6_stop>>16)&0xffff;
+ 7712              		.loc 2 300 7 is_stmt 1 view .LVU2519
+ 300:Src/main.c    **** 						Long_Data[4] = (TO6_stop>>16)&0xffff;
+ 7713              		.loc 2 300 20 is_stmt 0 view .LVU2520
+ 7714 0388 E380     		strh	r3, [r4, #6]	@ movhi
+ 301:Src/main.c    **** 						
+ 7715              		.loc 2 301 7 is_stmt 1 view .LVU2521
+ 301:Src/main.c    **** 						
+ 7716              		.loc 2 301 31 is_stmt 0 view .LVU2522
+ 7717 038a 1B0C     		lsrs	r3, r3, #16
+ARM GAS  /tmp/ccdsDELB.s 			page 503
+
+
+ 301:Src/main.c    **** 						
+ 7718              		.loc 2 301 20 view .LVU2523
+ 7719 038c 2381     		strh	r3, [r4, #8]	@ movhi
+ 304:Src/main.c    **** 						
+ 7720              		.loc 2 304 7 is_stmt 1 view .LVU2524
+ 304:Src/main.c    **** 						
+ 7721              		.loc 2 304 31 is_stmt 0 view .LVU2525
+ 7722 038e 3B88     		ldrh	r3, [r7]
+ 304:Src/main.c    **** 						
+ 7723              		.loc 2 304 20 view .LVU2526
+ 7724 0390 6381     		strh	r3, [r4, #10]	@ movhi
+ 307:Src/main.c    **** 
+ 7725              		.loc 2 307 7 is_stmt 1 view .LVU2527
+ 307:Src/main.c    **** 
+ 7726              		.loc 2 307 31 is_stmt 0 view .LVU2528
+ 7727 0392 3388     		ldrh	r3, [r6]
+ 307:Src/main.c    **** 
+ 7728              		.loc 2 307 20 view .LVU2529
+ 7729 0394 A381     		strh	r3, [r4, #12]	@ movhi
+ 309:Src/main.c    **** 						{
+ 7730              		.loc 2 309 7 is_stmt 1 view .LVU2530
+ 309:Src/main.c    **** 						{
+ 7731              		.loc 2 309 21 is_stmt 0 view .LVU2531
+ 7732 0396 6E4B     		ldr	r3, .L361+36
+ 7733 0398 DB7A     		ldrb	r3, [r3, #11]	@ zero_extendqisi2
+ 309:Src/main.c    **** 						{
+ 7734              		.loc 2 309 10 view .LVU2532
+ 7735 039a 012B     		cmp	r3, #1
+ 7736 039c 03D0     		beq	.L354
+ 7737              	.L322:
+ 316:Src/main.c    **** 					}
+ 7738              		.loc 2 316 7 is_stmt 1 view .LVU2533
+ 316:Src/main.c    **** 					}
+ 7739              		.loc 2 316 21 is_stmt 0 view .LVU2534
+ 7740 039e 6D4B     		ldr	r3, .L361+40
+ 7741 03a0 0722     		movs	r2, #7
+ 7742 03a2 1A70     		strb	r2, [r3]
+ 7743 03a4 85E6     		b	.L306
+ 7744              	.L354:
+ 311:Src/main.c    **** 							Long_Data[DL_16-1] = CS_result;
+ 7745              		.loc 2 311 8 is_stmt 1 view .LVU2535
+ 311:Src/main.c    **** 							Long_Data[DL_16-1] = CS_result;
+ 7746              		.loc 2 311 20 is_stmt 0 view .LVU2536
+ 7747 03a6 0D21     		movs	r1, #13
+ 7748 03a8 A01C     		adds	r0, r4, #2
+ 7749 03aa FFF7FEFF 		bl	CalculateChecksum
+ 7750              	.LVL590:
+ 311:Src/main.c    **** 							Long_Data[DL_16-1] = CS_result;
+ 7751              		.loc 2 311 18 view .LVU2537
+ 7752 03ae 6A4A     		ldr	r2, .L361+44
+ 7753 03b0 1080     		strh	r0, [r2]	@ movhi
+ 312:Src/main.c    **** 							temp16 = SD_SAVE(&Long_Data[0]);
+ 7754              		.loc 2 312 8 is_stmt 1 view .LVU2538
+ 312:Src/main.c    **** 							temp16 = SD_SAVE(&Long_Data[0]);
+ 7755              		.loc 2 312 27 is_stmt 0 view .LVU2539
+ 7756 03b2 A083     		strh	r0, [r4, #28]	@ movhi
+ 313:Src/main.c    **** 							State_Data[0]|=temp16&0xff;
+ARM GAS  /tmp/ccdsDELB.s 			page 504
+
+
+ 7757              		.loc 2 313 8 is_stmt 1 view .LVU2540
+ 313:Src/main.c    **** 							State_Data[0]|=temp16&0xff;
+ 7758              		.loc 2 313 17 is_stmt 0 view .LVU2541
+ 7759 03b4 2046     		mov	r0, r4
+ 7760 03b6 FFF7FEFF 		bl	SD_SAVE
+ 7761              	.LVL591:
+ 313:Src/main.c    **** 							State_Data[0]|=temp16&0xff;
+ 7762              		.loc 2 313 15 view .LVU2542
+ 7763 03ba 83B2     		uxth	r3, r0
+ 7764 03bc 2B80     		strh	r3, [r5]	@ movhi
+ 314:Src/main.c    **** 						}
+ 7765              		.loc 2 314 8 is_stmt 1 view .LVU2543
+ 314:Src/main.c    **** 						}
+ 7766              		.loc 2 314 21 is_stmt 0 view .LVU2544
+ 7767 03be 6749     		ldr	r1, .L361+48
+ 7768 03c0 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 7769 03c2 1343     		orrs	r3, r3, r2
+ 7770 03c4 0B70     		strb	r3, [r1]
+ 7771 03c6 EAE7     		b	.L322
+ 7772              	.L309:
+ 320:Src/main.c    **** 					{
+ 7773              		.loc 2 320 6 is_stmt 1 view .LVU2545
+ 320:Src/main.c    **** 					{
+ 7774              		.loc 2 320 10 is_stmt 0 view .LVU2546
+ 7775 03c8 6548     		ldr	r0, .L361+52
+ 7776 03ca FFF7FEFF 		bl	CheckChecksum
+ 7777              	.LVL592:
+ 320:Src/main.c    **** 					{
+ 7778              		.loc 2 320 9 view .LVU2547
+ 7779 03ce 70B9     		cbnz	r0, .L355
+ 329:Src/main.c    **** 						CPU_state = DEFAULT_ENABLE;
+ 7780              		.loc 2 329 7 is_stmt 1 view .LVU2548
+ 329:Src/main.c    **** 						CPU_state = DEFAULT_ENABLE;
+ 7781              		.loc 2 329 21 is_stmt 0 view .LVU2549
+ 7782 03d0 624A     		ldr	r2, .L361+48
+ 7783 03d2 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
+ 7784 03d4 43F00403 		orr	r3, r3, #4
+ 7785 03d8 1370     		strb	r3, [r2]
+ 330:Src/main.c    **** 						CPU_state_old = HALT;//Save main current cycle
+ 7786              		.loc 2 330 7 is_stmt 1 view .LVU2550
+ 330:Src/main.c    **** 						CPU_state_old = HALT;//Save main current cycle
+ 7787              		.loc 2 330 17 is_stmt 0 view .LVU2551
+ 7788 03da 624B     		ldr	r3, .L361+56
+ 7789 03dc 0222     		movs	r2, #2
+ 7790 03de 1A70     		strb	r2, [r3]
+ 331:Src/main.c    **** 					}
+ 7791              		.loc 2 331 7 is_stmt 1 view .LVU2552
+ 331:Src/main.c    **** 					}
+ 7792              		.loc 2 331 21 is_stmt 0 view .LVU2553
+ 7793 03e0 5C4B     		ldr	r3, .L361+40
+ 7794 03e2 0022     		movs	r2, #0
+ 7795 03e4 1A70     		strb	r2, [r3]
+ 7796              	.L324:
+ 333:Src/main.c    **** 				break;
+ 7797              		.loc 2 333 6 is_stmt 1 view .LVU2554
+ 333:Src/main.c    **** 				break;
+ 7798              		.loc 2 333 32 is_stmt 0 view .LVU2555
+ARM GAS  /tmp/ccdsDELB.s 			page 505
+
+
+ 7799 03e6 604B     		ldr	r3, .L361+60
+ 7800 03e8 0122     		movs	r2, #1
+ 7801 03ea 1A70     		strb	r2, [r3]
+ 334:Src/main.c    **** 				case RUN_TASK:
+ 7802              		.loc 2 334 5 is_stmt 1 view .LVU2556
+ 7803 03ec 61E6     		b	.L306
+ 7804              	.L355:
+ 322:Src/main.c    **** 						TO6_before = TO6;
+ 7805              		.loc 2 322 7 view .LVU2557
+ 7806 03ee 584B     		ldr	r3, .L361+36
+ 7807 03f0 5E4A     		ldr	r2, .L361+64
+ 7808 03f2 5F49     		ldr	r1, .L361+68
+ 7809 03f4 5A48     		ldr	r0, .L361+52
+ 7810 03f6 FFF7FEFF 		bl	Decode_task
+ 7811              	.LVL593:
+ 323:Src/main.c    **** 						CPU_state = RUN_TASK;
+ 7812              		.loc 2 323 7 view .LVU2558
+ 323:Src/main.c    **** 						CPU_state = RUN_TASK;
+ 7813              		.loc 2 323 18 is_stmt 0 view .LVU2559
+ 7814 03fa 534B     		ldr	r3, .L361+28
+ 7815 03fc 1A68     		ldr	r2, [r3]
+ 7816 03fe 5D4B     		ldr	r3, .L361+72
+ 7817 0400 1A60     		str	r2, [r3]
+ 324:Src/main.c    **** 						CPU_state_old = RUN_TASK;//Save main current cycle
+ 7818              		.loc 2 324 7 is_stmt 1 view .LVU2560
+ 324:Src/main.c    **** 						CPU_state_old = RUN_TASK;//Save main current cycle
+ 7819              		.loc 2 324 17 is_stmt 0 view .LVU2561
+ 7820 0402 0923     		movs	r3, #9
+ 7821 0404 574A     		ldr	r2, .L361+56
+ 7822 0406 1370     		strb	r3, [r2]
+ 325:Src/main.c    **** 					}
+ 7823              		.loc 2 325 7 is_stmt 1 view .LVU2562
+ 325:Src/main.c    **** 					}
+ 7824              		.loc 2 325 21 is_stmt 0 view .LVU2563
+ 7825 0408 524A     		ldr	r2, .L361+40
+ 7826 040a 1370     		strb	r3, [r2]
+ 7827 040c EBE7     		b	.L324
+ 7828              	.L307:
+ 336:Src/main.c    **** 					{
+ 7829              		.loc 2 336 6 is_stmt 1 view .LVU2564
+ 336:Src/main.c    **** 					{
+ 7830              		.loc 2 336 18 is_stmt 0 view .LVU2565
+ 7831 040e 474B     		ldr	r3, .L361
+ 7832 0410 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 7833 0412 012B     		cmp	r3, #1
+ 7834 0414 24D0     		beq	.L325
+ 7835 0416 022B     		cmp	r3, #2
+ 7836 0418 00F0DF80 		beq	.L326
+ 7837              	.L327:
+ 424:Src/main.c    **** 					{
+ 7838              		.loc 2 424 6 is_stmt 1 view .LVU2566
+ 424:Src/main.c    **** 					{
+ 7839              		.loc 2 424 13 is_stmt 0 view .LVU2567
+ 7840 041c 444B     		ldr	r3, .L361+4
+ 7841 041e 1B68     		ldr	r3, [r3]
+ 7842 0420 444A     		ldr	r2, .L361+8
+ 7843 0422 1268     		ldr	r2, [r2]
+ARM GAS  /tmp/ccdsDELB.s 			page 506
+
+
+ 424:Src/main.c    **** 					{
+ 7844              		.loc 2 424 9 view .LVU2568
+ 7845 0424 9342     		cmp	r3, r2
+ 7846 0426 00F26081 		bhi	.L356
+ 7847              	.L339:
+ 476:Src/main.c    **** 					
+ 7848              		.loc 2 476 27 is_stmt 1 discriminator 1 view .LVU2569
+ 476:Src/main.c    **** 					
+ 7849              		.loc 2 476 12 discriminator 1 view .LVU2570
+ 476:Src/main.c    **** 					
+ 7850              		.loc 2 476 13 is_stmt 0 discriminator 1 view .LVU2571
+ 7851 042a 534B     		ldr	r3, .L361+76
+ 7852 042c 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 476:Src/main.c    **** 					
+ 7853              		.loc 2 476 12 discriminator 1 view .LVU2572
+ 7854 042e 002B     		cmp	r3, #0
+ 7855 0430 FBD0     		beq	.L339
+ 478:Src/main.c    **** 					
+ 7856              		.loc 2 478 6 is_stmt 1 view .LVU2573
+ 7857 0432 FFF7FEFF 		bl	Stop_TIM10
+ 7858              	.LVL594:
+ 480:Src/main.c    **** 					{
+ 7859              		.loc 2 480 6 view .LVU2574
+ 480:Src/main.c    **** 					{
+ 7860              		.loc 2 480 14 is_stmt 0 view .LVU2575
+ 7861 0436 3D4B     		ldr	r3, .L361
+ 7862 0438 DB8A     		ldrh	r3, [r3, #22]
+ 480:Src/main.c    **** 					{
+ 7863              		.loc 2 480 9 view .LVU2576
+ 7864 043a 032B     		cmp	r3, #3
+ 7865 043c 0CD9     		bls	.L340
+ 482:Src/main.c    **** 						TO10_counter = task.dt / 10 - 1;
+ 7866              		.loc 2 482 7 is_stmt 1 view .LVU2577
+ 482:Src/main.c    **** 						TO10_counter = task.dt / 10 - 1;
+ 7867              		.loc 2 482 26 is_stmt 0 view .LVU2578
+ 7868 043e 4F4B     		ldr	r3, .L361+80
+ 7869 0440 1A68     		ldr	r2, [r3]
+ 7870 0442 4F4B     		ldr	r3, .L361+84
+ 7871 0444 DA60     		str	r2, [r3, #12]
+ 483:Src/main.c    **** 					}
+ 7872              		.loc 2 483 7 is_stmt 1 view .LVU2579
+ 483:Src/main.c    **** 					}
+ 7873              		.loc 2 483 26 is_stmt 0 view .LVU2580
+ 7874 0446 394B     		ldr	r3, .L361
+ 7875 0448 1B7D     		ldrb	r3, [r3, #20]	@ zero_extendqisi2
+ 483:Src/main.c    **** 					}
+ 7876              		.loc 2 483 30 view .LVU2581
+ 7877 044a 4E4A     		ldr	r2, .L361+88
+ 7878 044c A2FB0323 		umull	r2, r3, r2, r3
+ 7879 0450 DB08     		lsrs	r3, r3, #3
+ 483:Src/main.c    **** 					}
+ 7880              		.loc 2 483 35 view .LVU2582
+ 7881 0452 013B     		subs	r3, r3, #1
+ 483:Src/main.c    **** 					}
+ 7882              		.loc 2 483 20 view .LVU2583
+ 7883 0454 4C4A     		ldr	r2, .L361+92
+ 7884 0456 1360     		str	r3, [r2]
+ARM GAS  /tmp/ccdsDELB.s 			page 507
+
+
+ 7885              	.L340:
+ 486:Src/main.c    ****         break;
+ 7886              		.loc 2 486 6 is_stmt 1 view .LVU2584
+ 486:Src/main.c    ****         break;
+ 7887              		.loc 2 486 20 is_stmt 0 view .LVU2585
+ 7888 0458 3E4B     		ldr	r3, .L361+40
+ 7889 045a 0922     		movs	r2, #9
+ 7890 045c 1A70     		strb	r2, [r3]
+ 487:Src/main.c    **** 			}
+ 7891              		.loc 2 487 9 is_stmt 1 view .LVU2586
+ 7892 045e 28E6     		b	.L306
+ 7893              	.L325:
+ 339:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_1);
+ 7894              		.loc 2 339 7 view .LVU2587
+ 339:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_1);
+ 7895              		.loc 2 339 38 is_stmt 0 view .LVU2588
+ 7896 0460 324B     		ldr	r3, .L361
+ 7897 0462 D3ED077A 		vldr.32	s15, [r3, #28]
+ 339:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_1);
+ 7898              		.loc 2 339 7 view .LVU2589
+ 7899 0466 FCEEE77A 		vcvt.u32.f32	s15, s15
+ 7900 046a 17EE903A 		vmov	r3, s15	@ int
+ 7901 046e 99B2     		uxth	r1, r3
+ 7902 0470 0220     		movs	r0, #2
+ 7903 0472 FFF7FEFF 		bl	Set_LTEC
+ 7904              	.LVL595:
+ 340:Src/main.c    **** 						LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1);
+ 7905              		.loc 2 340 7 is_stmt 1 view .LVU2590
+ 340:Src/main.c    **** 						LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1);
+ 7906              		.loc 2 340 14 is_stmt 0 view .LVU2591
+ 7907 0476 0320     		movs	r0, #3
+ 7908 0478 FFF7FEFF 		bl	MPhD_T
+ 7909              	.LVL596:
+ 341:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_2);
+ 7910              		.loc 2 341 7 is_stmt 1 view .LVU2592
+ 341:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_2);
+ 7911              		.loc 2 341 32 is_stmt 0 view .LVU2593
+ 7912 047c 0320     		movs	r0, #3
+ 7913 047e FFF7FEFF 		bl	MPhD_T
+ 7914              	.LVL597:
+ 341:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_2);
+ 7915              		.loc 2 341 30 view .LVU2594
+ 7916 0482 2D4C     		ldr	r4, .L361+12
+ 7917 0484 2080     		strh	r0, [r4]	@ movhi
+ 342:Src/main.c    **** 						LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2);
+ 7918              		.loc 2 342 7 is_stmt 1 view .LVU2595
+ 342:Src/main.c    **** 						LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2);
+ 7919              		.loc 2 342 14 is_stmt 0 view .LVU2596
+ 7920 0486 0420     		movs	r0, #4
+ 7921 0488 FFF7FEFF 		bl	MPhD_T
+ 7922              	.LVL598:
+ 343:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 7923              		.loc 2 343 7 is_stmt 1 view .LVU2597
+ 343:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 7924              		.loc 2 343 32 is_stmt 0 view .LVU2598
+ 7925 048c 0420     		movs	r0, #4
+ 7926 048e FFF7FEFF 		bl	MPhD_T
+ARM GAS  /tmp/ccdsDELB.s 			page 508
+
+
+ 7927              	.LVL599:
+ 343:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 7928              		.loc 2 343 30 view .LVU2599
+ 7929 0492 2A4D     		ldr	r5, .L361+16
+ 7930 0494 2880     		strh	r0, [r5]	@ movhi
+ 344:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1
+ 7931              		.loc 2 344 7 is_stmt 1 view .LVU2600
+ 344:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1
+ 7932              		.loc 2 344 14 is_stmt 0 view .LVU2601
+ 7933 0496 0122     		movs	r2, #1
+ 7934 0498 2146     		mov	r1, r4
+ 7935 049a 3548     		ldr	r0, .L361+68
+ 7936 049c FFF7FEFF 		bl	PID_Controller_Temp
+ 7937              	.LVL600:
+ 7938 04a0 0146     		mov	r1, r0
+ 344:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1
+ 7939              		.loc 2 344 13 view .LVU2602
+ 7940 04a2 274C     		ldr	r4, .L361+20
+ 7941 04a4 2080     		strh	r0, [r4]	@ movhi
+ 345:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2);
+ 7942              		.loc 2 345 7 is_stmt 1 view .LVU2603
+ 7943 04a6 0320     		movs	r0, #3
+ 7944 04a8 FFF7FEFF 		bl	Set_LTEC
+ 7945              	.LVL601:
+ 346:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2
+ 7946              		.loc 2 346 7 view .LVU2604
+ 346:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2
+ 7947              		.loc 2 346 14 is_stmt 0 view .LVU2605
+ 7948 04ac 0222     		movs	r2, #2
+ 7949 04ae 2946     		mov	r1, r5
+ 7950 04b0 2E48     		ldr	r0, .L361+64
+ 7951 04b2 FFF7FEFF 		bl	PID_Controller_Temp
+ 7952              	.LVL602:
+ 7953 04b6 0146     		mov	r1, r0
+ 346:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2
+ 7954              		.loc 2 346 13 view .LVU2606
+ 7955 04b8 2080     		strh	r0, [r4]	@ movhi
+ 347:Src/main.c    **** 
+ 7956              		.loc 2 347 7 is_stmt 1 view .LVU2607
+ 7957 04ba 0420     		movs	r0, #4
+ 7958 04bc FFF7FEFF 		bl	Set_LTEC
+ 7959              	.LVL603:
+ 350:Src/main.c    **** 						HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET);
+ 7960              		.loc 2 350 7 view .LVU2608
+ 7961 04c0 324C     		ldr	r4, .L361+96
+ 7962 04c2 0122     		movs	r2, #1
+ 7963 04c4 8021     		movs	r1, #128
+ 7964 04c6 2046     		mov	r0, r4
+ 7965 04c8 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 7966              	.LVL604:
+ 351:Src/main.c    **** 		
+ 7967              		.loc 2 351 7 view .LVU2609
+ 7968 04cc 0022     		movs	r2, #0
+ 7969 04ce 8021     		movs	r1, #128
+ 7970 04d0 2046     		mov	r0, r4
+ 7971 04d2 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 7972              	.LVL605:
+ARM GAS  /tmp/ccdsDELB.s 			page 509
+
+
+ 353:Src/main.c    **** 						if (st != HAL_OK)
+ 7973              		.loc 2 353 7 view .LVU2610
+ 353:Src/main.c    **** 						if (st != HAL_OK)
+ 7974              		.loc 2 353 12 is_stmt 0 view .LVU2611
+ 7975 04d6 2A48     		ldr	r0, .L361+84
+ 7976 04d8 FFF7FEFF 		bl	HAL_TIM_Base_Start_IT
+ 7977              	.LVL606:
+ 354:Src/main.c    **** 							while(1);
+ 7978              		.loc 2 354 7 is_stmt 1 view .LVU2612
+ 354:Src/main.c    **** 							while(1);
+ 7979              		.loc 2 354 10 is_stmt 0 view .LVU2613
+ 7980 04dc 20BB     		cbnz	r0, .L329
+ 7981              	.LVL607:
+ 7982              	.L330:
+ 356:Src/main.c    **** 						{
+ 7983              		.loc 2 356 13 is_stmt 1 view .LVU2614
+ 356:Src/main.c    **** 						{
+ 7984              		.loc 2 356 18 is_stmt 0 view .LVU2615
+ 7985 04de 134B     		ldr	r3, .L361
+ 7986 04e0 D3ED047A 		vldr.32	s15, [r3, #16]
+ 356:Src/main.c    **** 						{
+ 7987              		.loc 2 356 39 view .LVU2616
+ 7988 04e4 93ED027A 		vldr.32	s14, [r3, #8]
+ 356:Src/main.c    **** 						{
+ 7989              		.loc 2 356 13 view .LVU2617
+ 7990 04e8 F4EEC77A 		vcmpe.f32	s15, s14
+ 7991 04ec F1EE10FA 		vmrs	APSR_nzcv, FPSCR
+ 7992 04f0 50D5     		bpl	.L357
+ 358:Src/main.c    **** 							{
+ 7993              		.loc 2 358 8 is_stmt 1 view .LVU2618
+ 358:Src/main.c    **** 							{
+ 7994              		.loc 2 358 12 is_stmt 0 view .LVU2619
+ 7995 04f2 214B     		ldr	r3, .L361+76
+ 7996 04f4 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 358:Src/main.c    **** 							{
+ 7997              		.loc 2 358 11 view .LVU2620
+ 7998 04f6 002B     		cmp	r3, #0
+ 7999 04f8 F1D0     		beq	.L330
+ 360:Src/main.c    **** 								task.current_param += task.delta_param;
+ 8000              		.loc 2 360 9 is_stmt 1 view .LVU2621
+ 8001 04fa FCEEE77A 		vcvt.u32.f32	s15, s15
+ 8002 04fe 17EE903A 		vmov	r3, s15	@ int
+ 8003 0502 99B2     		uxth	r1, r3
+ 8004 0504 0120     		movs	r0, #1
+ 8005 0506 FFF7FEFF 		bl	Set_LTEC
+ 8006              	.LVL608:
+ 361:Src/main.c    **** 								TO10 = 0;
+ 8007              		.loc 2 361 9 view .LVU2622
+ 361:Src/main.c    **** 								TO10 = 0;
+ 8008              		.loc 2 361 35 is_stmt 0 view .LVU2623
+ 8009 050a 084B     		ldr	r3, .L361
+ 8010 050c 93ED037A 		vldr.32	s14, [r3, #12]
+ 361:Src/main.c    **** 								TO10 = 0;
+ 8011              		.loc 2 361 28 view .LVU2624
+ 8012 0510 D3ED047A 		vldr.32	s15, [r3, #16]
+ 8013 0514 77EE877A 		vadd.f32	s15, s15, s14
+ 8014 0518 C3ED047A 		vstr.32	s15, [r3, #16]
+ARM GAS  /tmp/ccdsDELB.s 			page 510
+
+
+ 362:Src/main.c    **** 								TIM10_coflag = 0;
+ 8015              		.loc 2 362 9 is_stmt 1 view .LVU2625
+ 362:Src/main.c    **** 								TIM10_coflag = 0;
+ 8016              		.loc 2 362 14 is_stmt 0 view .LVU2626
+ 8017 051c 0023     		movs	r3, #0
+ 8018 051e 1C4A     		ldr	r2, .L361+100
+ 8019 0520 1360     		str	r3, [r2]
+ 363:Src/main.c    **** 							}
+ 8020              		.loc 2 363 9 is_stmt 1 view .LVU2627
+ 363:Src/main.c    **** 							}
+ 8021              		.loc 2 363 22 is_stmt 0 view .LVU2628
+ 8022 0522 154A     		ldr	r2, .L361+76
+ 8023 0524 1370     		strb	r3, [r2]
+ 8024 0526 DAE7     		b	.L330
+ 8025              	.LVL609:
+ 8026              	.L329:
+ 355:Src/main.c    **** 						while (task.current_param < task.max_param)
+ 8027              		.loc 2 355 8 is_stmt 1 discriminator 1 view .LVU2629
+ 355:Src/main.c    **** 						while (task.current_param < task.max_param)
+ 8028              		.loc 2 355 16 discriminator 1 view .LVU2630
+ 355:Src/main.c    **** 						while (task.current_param < task.max_param)
+ 8029              		.loc 2 355 13 discriminator 1 view .LVU2631
+ 8030 0528 FEE7     		b	.L329
+ 8031              	.L362:
+ 8032 052a 00BF     		.align	2
+ 8033              	.L361:
+ 8034 052c 00000000 		.word	.LANCHOR1
+ 8035 0530 00000000 		.word	.LANCHOR3
+ 8036 0534 00000000 		.word	.LANCHOR8
+ 8037 0538 00000000 		.word	.LANCHOR39
+ 8038 053c 00000000 		.word	.LANCHOR40
+ 8039 0540 00000000 		.word	.LANCHOR38
+ 8040 0544 00000000 		.word	.LANCHOR6
+ 8041 0548 00000000 		.word	.LANCHOR7
+ 8042 054c 00000000 		.word	.LANCHOR41
+ 8043 0550 00000000 		.word	.LANCHOR20
+ 8044 0554 00000000 		.word	.LANCHOR35
+ 8045 0558 00000000 		.word	.LANCHOR34
+ 8046 055c 00000000 		.word	.LANCHOR36
+ 8047 0560 00000000 		.word	.LANCHOR26
+ 8048 0564 00000000 		.word	.LANCHOR27
+ 8049 0568 00000000 		.word	.LANCHOR37
+ 8050 056c 00000000 		.word	.LANCHOR22
+ 8051 0570 00000000 		.word	.LANCHOR21
+ 8052 0574 00000000 		.word	.LANCHOR9
+ 8053 0578 00000000 		.word	.LANCHOR31
+ 8054 057c 00000000 		.word	.LANCHOR42
+ 8055 0580 00000000 		.word	.LANCHOR30
+ 8056 0584 CDCCCCCC 		.word	-858993459
+ 8057 0588 00000000 		.word	.LANCHOR2
+ 8058 058c 000C0240 		.word	1073875968
+ 8059 0590 00000000 		.word	.LANCHOR32
+ 8060              	.LVL610:
+ 8061              	.L357:
+ 366:Src/main.c    **** 						task.current_param = task.min_param;
+ 8062              		.loc 2 366 7 view .LVU2632
+ 8063 0594 FFF7FEFF 		bl	Stop_TIM10
+ARM GAS  /tmp/ccdsDELB.s 			page 511
+
+
+ 8064              	.LVL611:
+ 367:Src/main.c    **** 						Set_LTEC(TT_CHANGE_CURR_1, task.current_param);
+ 8065              		.loc 2 367 7 view .LVU2633
+ 367:Src/main.c    **** 						Set_LTEC(TT_CHANGE_CURR_1, task.current_param);
+ 8066              		.loc 2 367 32 is_stmt 0 view .LVU2634
+ 8067 0598 A94C     		ldr	r4, .L363
+ 8068 059a D4ED017A 		vldr.32	s15, [r4, #4]
+ 367:Src/main.c    **** 						Set_LTEC(TT_CHANGE_CURR_1, task.current_param);
+ 8069              		.loc 2 367 26 view .LVU2635
+ 8070 059e C4ED047A 		vstr.32	s15, [r4, #16]
+ 368:Src/main.c    **** 						if (task.tau > 3)
+ 8071              		.loc 2 368 7 is_stmt 1 view .LVU2636
+ 8072 05a2 FCEEE77A 		vcvt.u32.f32	s15, s15
+ 8073 05a6 17EE903A 		vmov	r3, s15	@ int
+ 8074 05aa 99B2     		uxth	r1, r3
+ 8075 05ac 0120     		movs	r0, #1
+ 8076 05ae FFF7FEFF 		bl	Set_LTEC
+ 8077              	.LVL612:
+ 369:Src/main.c    **** 						{
+ 8078              		.loc 2 369 7 view .LVU2637
+ 369:Src/main.c    **** 						{
+ 8079              		.loc 2 369 15 is_stmt 0 view .LVU2638
+ 8080 05b2 E38A     		ldrh	r3, [r4, #22]
+ 369:Src/main.c    **** 						{
+ 8081              		.loc 2 369 10 view .LVU2639
+ 8082 05b4 032B     		cmp	r3, #3
+ 8083 05b6 0CD9     		bls	.L332
+ 371:Src/main.c    **** 							htim10.Init.Period = 9999;
+ 8084              		.loc 2 371 8 is_stmt 1 view .LVU2640
+ 371:Src/main.c    **** 							htim10.Init.Period = 9999;
+ 8085              		.loc 2 371 34 is_stmt 0 view .LVU2641
+ 8086 05b8 A24A     		ldr	r2, .L363+4
+ 8087 05ba D068     		ldr	r0, [r2, #12]
+ 371:Src/main.c    **** 							htim10.Init.Period = 9999;
+ 8088              		.loc 2 371 21 view .LVU2642
+ 8089 05bc A249     		ldr	r1, .L363+8
+ 8090 05be 0860     		str	r0, [r1]
+ 372:Src/main.c    **** 							TO10_counter = (task.tau - 1) * 100;
+ 8091              		.loc 2 372 8 is_stmt 1 view .LVU2643
+ 372:Src/main.c    **** 							TO10_counter = (task.tau - 1) * 100;
+ 8092              		.loc 2 372 27 is_stmt 0 view .LVU2644
+ 8093 05c0 42F20F71 		movw	r1, #9999
+ 8094 05c4 D160     		str	r1, [r2, #12]
+ 373:Src/main.c    **** 						}
+ 8095              		.loc 2 373 8 is_stmt 1 view .LVU2645
+ 373:Src/main.c    **** 						}
+ 8096              		.loc 2 373 33 is_stmt 0 view .LVU2646
+ 8097 05c6 013B     		subs	r3, r3, #1
+ 373:Src/main.c    **** 						}
+ 8098              		.loc 2 373 38 view .LVU2647
+ 8099 05c8 6422     		movs	r2, #100
+ 8100 05ca 02FB03F3 		mul	r3, r2, r3
+ 373:Src/main.c    **** 						}
+ 8101              		.loc 2 373 21 view .LVU2648
+ 8102 05ce 9F4A     		ldr	r2, .L363+12
+ 8103 05d0 1360     		str	r3, [r2]
+ 8104              	.L332:
+ARM GAS  /tmp/ccdsDELB.s 			page 512
+
+
+ 375:Src/main.c    **** 					break;
+ 8105              		.loc 2 375 7 is_stmt 1 view .LVU2649
+ 8106 05d2 9C48     		ldr	r0, .L363+4
+ 8107 05d4 FFF7FEFF 		bl	HAL_TIM_Base_Start_IT
+ 8108              	.LVL613:
+ 376:Src/main.c    **** 					case TT_CHANGE_CURR_2:
+ 8109              		.loc 2 376 6 view .LVU2650
+ 8110 05d8 20E7     		b	.L327
+ 8111              	.L326:
+ 378:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_1);
+ 8112              		.loc 2 378 7 view .LVU2651
+ 378:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_1);
+ 8113              		.loc 2 378 38 is_stmt 0 view .LVU2652
+ 8114 05da 994B     		ldr	r3, .L363
+ 8115 05dc D3ED077A 		vldr.32	s15, [r3, #28]
+ 378:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_1);
+ 8116              		.loc 2 378 7 view .LVU2653
+ 8117 05e0 FCEEE77A 		vcvt.u32.f32	s15, s15
+ 8118 05e4 17EE903A 		vmov	r3, s15	@ int
+ 8119 05e8 99B2     		uxth	r1, r3
+ 8120 05ea 0120     		movs	r0, #1
+ 8121 05ec FFF7FEFF 		bl	Set_LTEC
+ 8122              	.LVL614:
+ 379:Src/main.c    **** 						LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1);
+ 8123              		.loc 2 379 7 is_stmt 1 view .LVU2654
+ 379:Src/main.c    **** 						LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1);
+ 8124              		.loc 2 379 14 is_stmt 0 view .LVU2655
+ 8125 05f0 0320     		movs	r0, #3
+ 8126 05f2 FFF7FEFF 		bl	MPhD_T
+ 8127              	.LVL615:
+ 380:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_2);
+ 8128              		.loc 2 380 7 is_stmt 1 view .LVU2656
+ 380:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_2);
+ 8129              		.loc 2 380 32 is_stmt 0 view .LVU2657
+ 8130 05f6 0320     		movs	r0, #3
+ 8131 05f8 FFF7FEFF 		bl	MPhD_T
+ 8132              	.LVL616:
+ 380:Src/main.c    **** 						(void) MPhD_T(TT_CHANGE_TEMP_2);
+ 8133              		.loc 2 380 30 view .LVU2658
+ 8134 05fc 944C     		ldr	r4, .L363+16
+ 8135 05fe 2080     		strh	r0, [r4]	@ movhi
+ 381:Src/main.c    **** 						LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2);
+ 8136              		.loc 2 381 7 is_stmt 1 view .LVU2659
+ 381:Src/main.c    **** 						LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2);
+ 8137              		.loc 2 381 14 is_stmt 0 view .LVU2660
+ 8138 0600 0420     		movs	r0, #4
+ 8139 0602 FFF7FEFF 		bl	MPhD_T
+ 8140              	.LVL617:
+ 382:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 8141              		.loc 2 382 7 is_stmt 1 view .LVU2661
+ 382:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 8142              		.loc 2 382 32 is_stmt 0 view .LVU2662
+ 8143 0606 0420     		movs	r0, #4
+ 8144 0608 FFF7FEFF 		bl	MPhD_T
+ 8145              	.LVL618:
+ 382:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1);
+ 8146              		.loc 2 382 30 view .LVU2663
+ARM GAS  /tmp/ccdsDELB.s 			page 513
+
+
+ 8147 060c 914D     		ldr	r5, .L363+20
+ 8148 060e 2880     		strh	r0, [r5]	@ movhi
+ 383:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1
+ 8149              		.loc 2 383 7 is_stmt 1 view .LVU2664
+ 383:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1
+ 8150              		.loc 2 383 14 is_stmt 0 view .LVU2665
+ 8151 0610 0122     		movs	r2, #1
+ 8152 0612 2146     		mov	r1, r4
+ 8153 0614 9048     		ldr	r0, .L363+24
+ 8154 0616 FFF7FEFF 		bl	PID_Controller_Temp
+ 8155              	.LVL619:
+ 8156 061a 0146     		mov	r1, r0
+ 383:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1
+ 8157              		.loc 2 383 13 view .LVU2666
+ 8158 061c 8F4C     		ldr	r4, .L363+28
+ 8159 061e 2080     		strh	r0, [r4]	@ movhi
+ 384:Src/main.c    **** 						temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2);
+ 8160              		.loc 2 384 7 is_stmt 1 view .LVU2667
+ 8161 0620 0320     		movs	r0, #3
+ 8162 0622 FFF7FEFF 		bl	Set_LTEC
+ 8163              	.LVL620:
+ 385:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2
+ 8164              		.loc 2 385 7 view .LVU2668
+ 385:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2
+ 8165              		.loc 2 385 14 is_stmt 0 view .LVU2669
+ 8166 0626 0222     		movs	r2, #2
+ 8167 0628 2946     		mov	r1, r5
+ 8168 062a 8D48     		ldr	r0, .L363+32
+ 8169 062c FFF7FEFF 		bl	PID_Controller_Temp
+ 8170              	.LVL621:
+ 8171 0630 0146     		mov	r1, r0
+ 385:Src/main.c    **** 						Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2
+ 8172              		.loc 2 385 13 view .LVU2670
+ 8173 0632 2080     		strh	r0, [r4]	@ movhi
+ 386:Src/main.c    **** 
+ 8174              		.loc 2 386 7 is_stmt 1 view .LVU2671
+ 8175 0634 0420     		movs	r0, #4
+ 8176 0636 FFF7FEFF 		bl	Set_LTEC
+ 8177              	.LVL622:
+ 389:Src/main.c    **** 						HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET);
+ 8178              		.loc 2 389 7 view .LVU2672
+ 8179 063a 8A4C     		ldr	r4, .L363+36
+ 8180 063c 0122     		movs	r2, #1
+ 8181 063e 8021     		movs	r1, #128
+ 8182 0640 2046     		mov	r0, r4
+ 8183 0642 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 8184              	.LVL623:
+ 390:Src/main.c    **** 
+ 8185              		.loc 2 390 7 view .LVU2673
+ 8186 0646 0022     		movs	r2, #0
+ 8187 0648 8021     		movs	r1, #128
+ 8188 064a 2046     		mov	r0, r4
+ 8189 064c FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 8190              	.LVL624:
+ 392:Src/main.c    **** 						if (st != HAL_OK)
+ 8191              		.loc 2 392 7 view .LVU2674
+ 392:Src/main.c    **** 						if (st != HAL_OK)
+ARM GAS  /tmp/ccdsDELB.s 			page 514
+
+
+ 8192              		.loc 2 392 12 is_stmt 0 view .LVU2675
+ 8193 0650 7C48     		ldr	r0, .L363+4
+ 8194 0652 FFF7FEFF 		bl	HAL_TIM_Base_Start_IT
+ 8195              	.LVL625:
+ 393:Src/main.c    **** 							while(1);
+ 8196              		.loc 2 393 7 is_stmt 1 view .LVU2676
+ 393:Src/main.c    **** 							while(1);
+ 8197              		.loc 2 393 10 is_stmt 0 view .LVU2677
+ 8198 0656 20BB     		cbnz	r0, .L334
+ 8199              	.LVL626:
+ 8200              	.L335:
+ 395:Src/main.c    **** 						{
+ 8201              		.loc 2 395 13 is_stmt 1 view .LVU2678
+ 395:Src/main.c    **** 						{
+ 8202              		.loc 2 395 18 is_stmt 0 view .LVU2679
+ 8203 0658 794B     		ldr	r3, .L363
+ 8204 065a D3ED047A 		vldr.32	s15, [r3, #16]
+ 395:Src/main.c    **** 						{
+ 8205              		.loc 2 395 39 view .LVU2680
+ 8206 065e 93ED027A 		vldr.32	s14, [r3, #8]
+ 395:Src/main.c    **** 						{
+ 8207              		.loc 2 395 13 view .LVU2681
+ 8208 0662 F4EEC77A 		vcmpe.f32	s15, s14
+ 8209 0666 F1EE10FA 		vmrs	APSR_nzcv, FPSCR
+ 8210 066a 1BD5     		bpl	.L358
+ 397:Src/main.c    **** 							{
+ 8211              		.loc 2 397 8 is_stmt 1 view .LVU2682
+ 397:Src/main.c    **** 							{
+ 8212              		.loc 2 397 12 is_stmt 0 view .LVU2683
+ 8213 066c 7E4B     		ldr	r3, .L363+40
+ 8214 066e 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 397:Src/main.c    **** 							{
+ 8215              		.loc 2 397 11 view .LVU2684
+ 8216 0670 002B     		cmp	r3, #0
+ 8217 0672 F1D0     		beq	.L335
+ 399:Src/main.c    **** 								task.current_param += task.delta_param;
+ 8218              		.loc 2 399 9 is_stmt 1 view .LVU2685
+ 8219 0674 FCEEE77A 		vcvt.u32.f32	s15, s15
+ 8220 0678 17EE903A 		vmov	r3, s15	@ int
+ 8221 067c 99B2     		uxth	r1, r3
+ 8222 067e 0220     		movs	r0, #2
+ 8223 0680 FFF7FEFF 		bl	Set_LTEC
+ 8224              	.LVL627:
+ 400:Src/main.c    **** 								TO10 = 0;
+ 8225              		.loc 2 400 9 view .LVU2686
+ 400:Src/main.c    **** 								TO10 = 0;
+ 8226              		.loc 2 400 35 is_stmt 0 view .LVU2687
+ 8227 0684 6E4B     		ldr	r3, .L363
+ 8228 0686 93ED037A 		vldr.32	s14, [r3, #12]
+ 400:Src/main.c    **** 								TO10 = 0;
+ 8229              		.loc 2 400 28 view .LVU2688
+ 8230 068a D3ED047A 		vldr.32	s15, [r3, #16]
+ 8231 068e 77EE877A 		vadd.f32	s15, s15, s14
+ 8232 0692 C3ED047A 		vstr.32	s15, [r3, #16]
+ 401:Src/main.c    **** 								TIM10_coflag = 0;
+ 8233              		.loc 2 401 9 is_stmt 1 view .LVU2689
+ 401:Src/main.c    **** 								TIM10_coflag = 0;
+ARM GAS  /tmp/ccdsDELB.s 			page 515
+
+
+ 8234              		.loc 2 401 14 is_stmt 0 view .LVU2690
+ 8235 0696 0023     		movs	r3, #0
+ 8236 0698 744A     		ldr	r2, .L363+44
+ 8237 069a 1360     		str	r3, [r2]
+ 402:Src/main.c    **** 							}
+ 8238              		.loc 2 402 9 is_stmt 1 view .LVU2691
+ 402:Src/main.c    **** 							}
+ 8239              		.loc 2 402 22 is_stmt 0 view .LVU2692
+ 8240 069c 724A     		ldr	r2, .L363+40
+ 8241 069e 1370     		strb	r3, [r2]
+ 8242 06a0 DAE7     		b	.L335
+ 8243              	.LVL628:
+ 8244              	.L334:
+ 394:Src/main.c    **** 						while (task.current_param < task.max_param)
+ 8245              		.loc 2 394 8 is_stmt 1 discriminator 2 view .LVU2693
+ 394:Src/main.c    **** 						while (task.current_param < task.max_param)
+ 8246              		.loc 2 394 16 discriminator 2 view .LVU2694
+ 394:Src/main.c    **** 						while (task.current_param < task.max_param)
+ 8247              		.loc 2 394 13 discriminator 2 view .LVU2695
+ 8248 06a2 FEE7     		b	.L334
+ 8249              	.LVL629:
+ 8250              	.L358:
+ 405:Src/main.c    **** 						task.current_param = task.min_param;
+ 8251              		.loc 2 405 7 view .LVU2696
+ 8252 06a4 FFF7FEFF 		bl	Stop_TIM10
+ 8253              	.LVL630:
+ 406:Src/main.c    **** 						Set_LTEC(TT_CHANGE_CURR_2, task.current_param);
+ 8254              		.loc 2 406 7 view .LVU2697
+ 406:Src/main.c    **** 						Set_LTEC(TT_CHANGE_CURR_2, task.current_param);
+ 8255              		.loc 2 406 32 is_stmt 0 view .LVU2698
+ 8256 06a8 654C     		ldr	r4, .L363
+ 8257 06aa D4ED017A 		vldr.32	s15, [r4, #4]
+ 406:Src/main.c    **** 						Set_LTEC(TT_CHANGE_CURR_2, task.current_param);
+ 8258              		.loc 2 406 26 view .LVU2699
+ 8259 06ae C4ED047A 		vstr.32	s15, [r4, #16]
+ 407:Src/main.c    **** 						if (task.tau > 3)
+ 8260              		.loc 2 407 7 is_stmt 1 view .LVU2700
+ 8261 06b2 FCEEE77A 		vcvt.u32.f32	s15, s15
+ 8262 06b6 17EE903A 		vmov	r3, s15	@ int
+ 8263 06ba 99B2     		uxth	r1, r3
+ 8264 06bc 0220     		movs	r0, #2
+ 8265 06be FFF7FEFF 		bl	Set_LTEC
+ 8266              	.LVL631:
+ 408:Src/main.c    **** 						{
+ 8267              		.loc 2 408 7 view .LVU2701
+ 408:Src/main.c    **** 						{
+ 8268              		.loc 2 408 15 is_stmt 0 view .LVU2702
+ 8269 06c2 E38A     		ldrh	r3, [r4, #22]
+ 408:Src/main.c    **** 						{
+ 8270              		.loc 2 408 10 view .LVU2703
+ 8271 06c4 032B     		cmp	r3, #3
+ 8272 06c6 0CD9     		bls	.L337
+ 410:Src/main.c    **** 							htim10.Init.Period = 9999;
+ 8273              		.loc 2 410 8 is_stmt 1 view .LVU2704
+ 410:Src/main.c    **** 							htim10.Init.Period = 9999;
+ 8274              		.loc 2 410 34 is_stmt 0 view .LVU2705
+ 8275 06c8 5E4A     		ldr	r2, .L363+4
+ARM GAS  /tmp/ccdsDELB.s 			page 516
+
+
+ 8276 06ca D068     		ldr	r0, [r2, #12]
+ 410:Src/main.c    **** 							htim10.Init.Period = 9999;
+ 8277              		.loc 2 410 21 view .LVU2706
+ 8278 06cc 5E49     		ldr	r1, .L363+8
+ 8279 06ce 0860     		str	r0, [r1]
+ 411:Src/main.c    **** 							TO10_counter = (task.tau - 1) * 100;
+ 8280              		.loc 2 411 8 is_stmt 1 view .LVU2707
+ 411:Src/main.c    **** 							TO10_counter = (task.tau - 1) * 100;
+ 8281              		.loc 2 411 27 is_stmt 0 view .LVU2708
+ 8282 06d0 42F20F71 		movw	r1, #9999
+ 8283 06d4 D160     		str	r1, [r2, #12]
+ 412:Src/main.c    **** 						}
+ 8284              		.loc 2 412 8 is_stmt 1 view .LVU2709
+ 412:Src/main.c    **** 						}
+ 8285              		.loc 2 412 33 is_stmt 0 view .LVU2710
+ 8286 06d6 013B     		subs	r3, r3, #1
+ 412:Src/main.c    **** 						}
+ 8287              		.loc 2 412 38 view .LVU2711
+ 8288 06d8 6422     		movs	r2, #100
+ 8289 06da 02FB03F3 		mul	r3, r2, r3
+ 412:Src/main.c    **** 						}
+ 8290              		.loc 2 412 21 view .LVU2712
+ 8291 06de 5B4A     		ldr	r2, .L363+12
+ 8292 06e0 1360     		str	r3, [r2]
+ 8293              	.L337:
+ 414:Src/main.c    **** 					break;
+ 8294              		.loc 2 414 7 is_stmt 1 view .LVU2713
+ 8295 06e2 5848     		ldr	r0, .L363+4
+ 8296 06e4 FFF7FEFF 		bl	HAL_TIM_Base_Start_IT
+ 8297              	.LVL632:
+ 415:Src/main.c    **** 					case TT_CHANGE_TEMP_1:
+ 8298              		.loc 2 415 6 view .LVU2714
+ 8299 06e8 98E6     		b	.L327
+ 8300              	.L356:
+ 426:Src/main.c    **** 						
+ 8301              		.loc 2 426 7 view .LVU2715
+ 426:Src/main.c    **** 						
+ 8302              		.loc 2 426 18 is_stmt 0 view .LVU2716
+ 8303 06ea 614A     		ldr	r2, .L363+48
+ 8304 06ec 1360     		str	r3, [r2]
+ 428:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 8305              		.loc 2 428 7 is_stmt 1 view .LVU2717
+ 428:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 8306              		.loc 2 428 25 is_stmt 0 view .LVU2718
+ 8307 06ee 0120     		movs	r0, #1
+ 8308 06f0 FFF7FEFF 		bl	MPhD_T
+ 8309              	.LVL633:
+ 428:Src/main.c    **** 						LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1
+ 8310              		.loc 2 428 23 view .LVU2719
+ 8311 06f4 564E     		ldr	r6, .L363+16
+ 8312 06f6 3081     		strh	r0, [r6, #8]	@ movhi
+ 429:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 8313              		.loc 2 429 7 is_stmt 1 view .LVU2720
+ 429:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 8314              		.loc 2 429 25 is_stmt 0 view .LVU2721
+ 8315 06f8 0120     		movs	r0, #1
+ 8316 06fa FFF7FEFF 		bl	MPhD_T
+ARM GAS  /tmp/ccdsDELB.s 			page 517
+
+
+ 8317              	.LVL634:
+ 429:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 8318              		.loc 2 429 23 view .LVU2722
+ 8319 06fe 3081     		strh	r0, [r6, #8]	@ movhi
+ 430:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 8320              		.loc 2 430 7 is_stmt 1 view .LVU2723
+ 430:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 8321              		.loc 2 430 25 is_stmt 0 view .LVU2724
+ 8322 0700 0220     		movs	r0, #2
+ 8323 0702 FFF7FEFF 		bl	MPhD_T
+ 8324              	.LVL635:
+ 430:Src/main.c    **** 						LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2
+ 8325              		.loc 2 430 23 view .LVU2725
+ 8326 0706 534F     		ldr	r7, .L363+20
+ 8327 0708 3881     		strh	r0, [r7, #8]	@ movhi
+ 431:Src/main.c    **** 						
+ 8328              		.loc 2 431 7 is_stmt 1 view .LVU2726
+ 431:Src/main.c    **** 						
+ 8329              		.loc 2 431 25 is_stmt 0 view .LVU2727
+ 8330 070a 0220     		movs	r0, #2
+ 8331 070c FFF7FEFF 		bl	MPhD_T
+ 8332              	.LVL636:
+ 431:Src/main.c    **** 						
+ 8333              		.loc 2 431 23 view .LVU2728
+ 8334 0710 3881     		strh	r0, [r7, #8]	@ movhi
+ 433:Src/main.c    **** 						Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data
+ 8335              		.loc 2 433 7 is_stmt 1 view .LVU2729
+ 433:Src/main.c    **** 						Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data
+ 8336              		.loc 2 433 31 is_stmt 0 view .LVU2730
+ 8337 0712 3389     		ldrh	r3, [r6, #8]
+ 433:Src/main.c    **** 						Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data
+ 8338              		.loc 2 433 20 view .LVU2731
+ 8339 0714 574C     		ldr	r4, .L363+52
+ 8340 0716 6380     		strh	r3, [r4, #2]	@ movhi
+ 434:Src/main.c    **** 	
+ 8341              		.loc 2 434 7 is_stmt 1 view .LVU2732
+ 434:Src/main.c    **** 	
+ 8342              		.loc 2 434 20 is_stmt 0 view .LVU2733
+ 8343 0718 A080     		strh	r0, [r4, #4]	@ movhi
+ 438:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 8344              		.loc 2 438 7 is_stmt 1 view .LVU2734
+ 438:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 8345              		.loc 2 438 16 is_stmt 0 view .LVU2735
+ 8346 071a 0020     		movs	r0, #0
+ 8347 071c FFF7FEFF 		bl	Get_ADC
+ 8348              	.LVL637:
+ 438:Src/main.c    **** 						temp16 = Get_ADC(1);
+ 8349              		.loc 2 438 14 view .LVU2736
+ 8350 0720 4E4D     		ldr	r5, .L363+28
+ 8351 0722 2880     		strh	r0, [r5]	@ movhi
+ 439:Src/main.c    **** 						Long_Data[7] = temp16;
+ 8352              		.loc 2 439 7 is_stmt 1 view .LVU2737
+ 439:Src/main.c    **** 						Long_Data[7] = temp16;
+ 8353              		.loc 2 439 16 is_stmt 0 view .LVU2738
+ 8354 0724 0120     		movs	r0, #1
+ 8355 0726 FFF7FEFF 		bl	Get_ADC
+ 8356              	.LVL638:
+ARM GAS  /tmp/ccdsDELB.s 			page 518
+
+
+ 439:Src/main.c    **** 						Long_Data[7] = temp16;
+ 8357              		.loc 2 439 14 view .LVU2739
+ 8358 072a 2880     		strh	r0, [r5]	@ movhi
+ 440:Src/main.c    **** 						
+ 8359              		.loc 2 440 7 is_stmt 1 view .LVU2740
+ 440:Src/main.c    **** 						
+ 8360              		.loc 2 440 20 is_stmt 0 view .LVU2741
+ 8361 072c E081     		strh	r0, [r4, #14]	@ movhi
+ 443:Src/main.c    **** 						Long_Data[8] = temp16;
+ 8362              		.loc 2 443 7 is_stmt 1 view .LVU2742
+ 443:Src/main.c    **** 						Long_Data[8] = temp16;
+ 8363              		.loc 2 443 16 is_stmt 0 view .LVU2743
+ 8364 072e 0120     		movs	r0, #1
+ 8365 0730 FFF7FEFF 		bl	Get_ADC
+ 8366              	.LVL639:
+ 443:Src/main.c    **** 						Long_Data[8] = temp16;
+ 8367              		.loc 2 443 14 view .LVU2744
+ 8368 0734 2880     		strh	r0, [r5]	@ movhi
+ 444:Src/main.c    **** 						
+ 8369              		.loc 2 444 7 is_stmt 1 view .LVU2745
+ 444:Src/main.c    **** 						
+ 8370              		.loc 2 444 20 is_stmt 0 view .LVU2746
+ 8371 0736 2082     		strh	r0, [r4, #16]	@ movhi
+ 447:Src/main.c    **** 						Long_Data[9] = temp16;
+ 8372              		.loc 2 447 7 is_stmt 1 view .LVU2747
+ 447:Src/main.c    **** 						Long_Data[9] = temp16;
+ 8373              		.loc 2 447 16 is_stmt 0 view .LVU2748
+ 8374 0738 0120     		movs	r0, #1
+ 8375 073a FFF7FEFF 		bl	Get_ADC
+ 8376              	.LVL640:
+ 447:Src/main.c    **** 						Long_Data[9] = temp16;
+ 8377              		.loc 2 447 14 view .LVU2749
+ 8378 073e 2880     		strh	r0, [r5]	@ movhi
+ 448:Src/main.c    **** 						
+ 8379              		.loc 2 448 7 is_stmt 1 view .LVU2750
+ 448:Src/main.c    **** 						
+ 8380              		.loc 2 448 20 is_stmt 0 view .LVU2751
+ 8381 0740 6082     		strh	r0, [r4, #18]	@ movhi
+ 451:Src/main.c    **** 						Long_Data[10] = temp16;
+ 8382              		.loc 2 451 7 is_stmt 1 view .LVU2752
+ 451:Src/main.c    **** 						Long_Data[10] = temp16;
+ 8383              		.loc 2 451 16 is_stmt 0 view .LVU2753
+ 8384 0742 0120     		movs	r0, #1
+ 8385 0744 FFF7FEFF 		bl	Get_ADC
+ 8386              	.LVL641:
+ 451:Src/main.c    **** 						Long_Data[10] = temp16;
+ 8387              		.loc 2 451 14 view .LVU2754
+ 8388 0748 2880     		strh	r0, [r5]	@ movhi
+ 452:Src/main.c    **** 						
+ 8389              		.loc 2 452 7 is_stmt 1 view .LVU2755
+ 452:Src/main.c    **** 						
+ 8390              		.loc 2 452 21 is_stmt 0 view .LVU2756
+ 8391 074a A082     		strh	r0, [r4, #20]	@ movhi
+ 455:Src/main.c    **** 						Long_Data[11] = temp16;
+ 8392              		.loc 2 455 7 is_stmt 1 view .LVU2757
+ 455:Src/main.c    **** 						Long_Data[11] = temp16;
+ 8393              		.loc 2 455 16 is_stmt 0 view .LVU2758
+ARM GAS  /tmp/ccdsDELB.s 			page 519
+
+
+ 8394 074c 0120     		movs	r0, #1
+ 8395 074e FFF7FEFF 		bl	Get_ADC
+ 8396              	.LVL642:
+ 455:Src/main.c    **** 						Long_Data[11] = temp16;
+ 8397              		.loc 2 455 14 view .LVU2759
+ 8398 0752 2880     		strh	r0, [r5]	@ movhi
+ 456:Src/main.c    **** 						temp16 = Get_ADC(2);
+ 8399              		.loc 2 456 7 is_stmt 1 view .LVU2760
+ 456:Src/main.c    **** 						temp16 = Get_ADC(2);
+ 8400              		.loc 2 456 21 is_stmt 0 view .LVU2761
+ 8401 0754 E082     		strh	r0, [r4, #22]	@ movhi
+ 457:Src/main.c    **** 						
+ 8402              		.loc 2 457 7 is_stmt 1 view .LVU2762
+ 457:Src/main.c    **** 						
+ 8403              		.loc 2 457 16 is_stmt 0 view .LVU2763
+ 8404 0756 0220     		movs	r0, #2
+ 8405 0758 FFF7FEFF 		bl	Get_ADC
+ 8406              	.LVL643:
+ 457:Src/main.c    **** 						
+ 8407              		.loc 2 457 14 view .LVU2764
+ 8408 075c 2880     		strh	r0, [r5]	@ movhi
+ 460:Src/main.c    **** 						temp16 = Get_ADC(4);
+ 8409              		.loc 2 460 7 is_stmt 1 view .LVU2765
+ 460:Src/main.c    **** 						temp16 = Get_ADC(4);
+ 8410              		.loc 2 460 16 is_stmt 0 view .LVU2766
+ 8411 075e 0320     		movs	r0, #3
+ 8412 0760 FFF7FEFF 		bl	Get_ADC
+ 8413              	.LVL644:
+ 460:Src/main.c    **** 						temp16 = Get_ADC(4);
+ 8414              		.loc 2 460 14 view .LVU2767
+ 8415 0764 2880     		strh	r0, [r5]	@ movhi
+ 461:Src/main.c    **** 						Long_Data[12] = temp16;
+ 8416              		.loc 2 461 7 is_stmt 1 view .LVU2768
+ 461:Src/main.c    **** 						Long_Data[12] = temp16;
+ 8417              		.loc 2 461 16 is_stmt 0 view .LVU2769
+ 8418 0766 0420     		movs	r0, #4
+ 8419 0768 FFF7FEFF 		bl	Get_ADC
+ 8420              	.LVL645:
+ 461:Src/main.c    **** 						Long_Data[12] = temp16;
+ 8421              		.loc 2 461 14 view .LVU2770
+ 8422 076c 2880     		strh	r0, [r5]	@ movhi
+ 462:Src/main.c    **** 						temp16 = Get_ADC(5);
+ 8423              		.loc 2 462 7 is_stmt 1 view .LVU2771
+ 462:Src/main.c    **** 						temp16 = Get_ADC(5);
+ 8424              		.loc 2 462 21 is_stmt 0 view .LVU2772
+ 8425 076e 2083     		strh	r0, [r4, #24]	@ movhi
+ 463:Src/main.c    **** 													
+ 8426              		.loc 2 463 7 is_stmt 1 view .LVU2773
+ 463:Src/main.c    **** 													
+ 8427              		.loc 2 463 16 is_stmt 0 view .LVU2774
+ 8428 0770 0520     		movs	r0, #5
+ 8429 0772 FFF7FEFF 		bl	Get_ADC
+ 8430              	.LVL646:
+ 463:Src/main.c    **** 													
+ 8431              		.loc 2 463 14 view .LVU2775
+ 8432 0776 2880     		strh	r0, [r5]	@ movhi
+ 466:Src/main.c    **** 						Long_Data[3] = (TO6_stop)&0xffff;
+ARM GAS  /tmp/ccdsDELB.s 			page 520
+
+
+ 8433              		.loc 2 466 7 is_stmt 1 view .LVU2776
+ 466:Src/main.c    **** 						Long_Data[3] = (TO6_stop)&0xffff;
+ 8434              		.loc 2 466 16 is_stmt 0 view .LVU2777
+ 8435 0778 3F4B     		ldr	r3, .L363+56
+ 8436 077a 1B68     		ldr	r3, [r3]
+ 8437 077c 3F4A     		ldr	r2, .L363+60
+ 8438 077e 1360     		str	r3, [r2]
+ 467:Src/main.c    **** 						Long_Data[4] = (TO6_stop>>16)&0xffff;
+ 8439              		.loc 2 467 7 is_stmt 1 view .LVU2778
+ 467:Src/main.c    **** 						Long_Data[4] = (TO6_stop>>16)&0xffff;
+ 8440              		.loc 2 467 20 is_stmt 0 view .LVU2779
+ 8441 0780 E380     		strh	r3, [r4, #6]	@ movhi
+ 468:Src/main.c    **** 						
+ 8442              		.loc 2 468 7 is_stmt 1 view .LVU2780
+ 468:Src/main.c    **** 						
+ 8443              		.loc 2 468 31 is_stmt 0 view .LVU2781
+ 8444 0782 1B0C     		lsrs	r3, r3, #16
+ 468:Src/main.c    **** 						
+ 8445              		.loc 2 468 20 view .LVU2782
+ 8446 0784 2381     		strh	r3, [r4, #8]	@ movhi
+ 471:Src/main.c    **** 						
+ 8447              		.loc 2 471 7 is_stmt 1 view .LVU2783
+ 471:Src/main.c    **** 						
+ 8448              		.loc 2 471 31 is_stmt 0 view .LVU2784
+ 8449 0786 3388     		ldrh	r3, [r6]
+ 471:Src/main.c    **** 						
+ 8450              		.loc 2 471 20 view .LVU2785
+ 8451 0788 6381     		strh	r3, [r4, #10]	@ movhi
+ 474:Src/main.c    **** 					}
+ 8452              		.loc 2 474 7 is_stmt 1 view .LVU2786
+ 474:Src/main.c    **** 					}
+ 8453              		.loc 2 474 31 is_stmt 0 view .LVU2787
+ 8454 078a 3B88     		ldrh	r3, [r7]
+ 474:Src/main.c    **** 					}
+ 8455              		.loc 2 474 20 view .LVU2788
+ 8456 078c A381     		strh	r3, [r4, #12]	@ movhi
+ 8457 078e 4CE6     		b	.L339
+ 8458              	.L350:
+ 493:Src/main.c    **** 				//HAL_UART_Transmit(&huart1, State_Data, 2, 10);
+ 8459              		.loc 2 493 5 is_stmt 1 view .LVU2789
+ 8460 0790 3B4C     		ldr	r4, .L363+64
+ 8461 0792 0221     		movs	r1, #2
+ 8462 0794 2046     		mov	r0, r4
+ 8463 0796 FFF7FEFF 		bl	USART_TX
+ 8464              	.LVL647:
+ 495:Src/main.c    **** 				State_Data[1]=0;//All OK!
+ 8465              		.loc 2 495 5 view .LVU2790
+ 495:Src/main.c    **** 				State_Data[1]=0;//All OK!
+ 8466              		.loc 2 495 18 is_stmt 0 view .LVU2791
+ 8467 079a 0023     		movs	r3, #0
+ 8468 079c 2370     		strb	r3, [r4]
+ 496:Src/main.c    **** 				UART_transmission_request = NO_MESS;
+ 8469              		.loc 2 496 5 is_stmt 1 view .LVU2792
+ 496:Src/main.c    **** 				UART_transmission_request = NO_MESS;
+ 8470              		.loc 2 496 18 is_stmt 0 view .LVU2793
+ 8471 079e 6370     		strb	r3, [r4, #1]
+ 497:Src/main.c    **** 			break;
+ARM GAS  /tmp/ccdsDELB.s 			page 521
+
+
+ 8472              		.loc 2 497 5 is_stmt 1 view .LVU2794
+ 497:Src/main.c    **** 			break;
+ 8473              		.loc 2 497 31 is_stmt 0 view .LVU2795
+ 8474 07a0 384A     		ldr	r2, .L363+68
+ 8475 07a2 1370     		strb	r3, [r2]
+ 498:Src/main.c    **** 			case MESS_02://Transmith packet
+ 8476              		.loc 2 498 4 is_stmt 1 view .LVU2796
+ 8477 07a4 90E4     		b	.L343
+ 8478              	.L341:
+ 502:Src/main.c    **** 				Long_Data[DL_16-1] = CS_result;
+ 8479              		.loc 2 502 5 view .LVU2797
+ 502:Src/main.c    **** 				Long_Data[DL_16-1] = CS_result;
+ 8480              		.loc 2 502 17 is_stmt 0 view .LVU2798
+ 8481 07a6 334C     		ldr	r4, .L363+52
+ 8482 07a8 0D21     		movs	r1, #13
+ 8483 07aa A01C     		adds	r0, r4, #2
+ 8484 07ac FFF7FEFF 		bl	CalculateChecksum
+ 8485              	.LVL648:
+ 502:Src/main.c    **** 				Long_Data[DL_16-1] = CS_result;
+ 8486              		.loc 2 502 15 view .LVU2799
+ 8487 07b0 354B     		ldr	r3, .L363+72
+ 8488 07b2 1880     		strh	r0, [r3]	@ movhi
+ 503:Src/main.c    **** 				
+ 8489              		.loc 2 503 5 is_stmt 1 view .LVU2800
+ 503:Src/main.c    **** 				
+ 8490              		.loc 2 503 24 is_stmt 0 view .LVU2801
+ 8491 07b4 A083     		strh	r0, [r4, #28]	@ movhi
+ 505:Src/main.c    **** 				{
+ 8492              		.loc 2 505 5 is_stmt 1 view .LVU2802
+ 8493              	.LBB569:
+ 505:Src/main.c    **** 				{
+ 8494              		.loc 2 505 10 view .LVU2803
+ 8495              	.LVL649:
+ 505:Src/main.c    **** 				{
+ 8496              		.loc 2 505 19 is_stmt 0 view .LVU2804
+ 8497 07b6 0023     		movs	r3, #0
+ 505:Src/main.c    **** 				{
+ 8498              		.loc 2 505 5 view .LVU2805
+ 8499 07b8 0BE0     		b	.L344
+ 8500              	.LVL650:
+ 8501              	.L345:
+ 507:Src/main.c    **** 					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+ 8502              		.loc 2 507 6 is_stmt 1 discriminator 3 view .LVU2806
+ 507:Src/main.c    **** 					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+ 8503              		.loc 2 507 33 is_stmt 0 discriminator 3 view .LVU2807
+ 8504 07ba 2E4A     		ldr	r2, .L363+52
+ 8505 07bc 32F81320 		ldrh	r2, [r2, r3, lsl #1]
+ 507:Src/main.c    **** 					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+ 8506              		.loc 2 507 17 discriminator 3 view .LVU2808
+ 8507 07c0 5900     		lsls	r1, r3, #1
+ 507:Src/main.c    **** 					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+ 8508              		.loc 2 507 21 discriminator 3 view .LVU2809
+ 8509 07c2 3248     		ldr	r0, .L363+76
+ 8510 07c4 00F81320 		strb	r2, [r0, r3, lsl #1]
+ 508:Src/main.c    **** 				}
+ 8511              		.loc 2 508 6 is_stmt 1 discriminator 3 view .LVU2810
+ 508:Src/main.c    **** 				}
+ARM GAS  /tmp/ccdsDELB.s 			page 522
+
+
+ 8512              		.loc 2 508 19 is_stmt 0 discriminator 3 view .LVU2811
+ 8513 07c8 0131     		adds	r1, r1, #1
+ 508:Src/main.c    **** 				}
+ 8514              		.loc 2 508 23 discriminator 3 view .LVU2812
+ 8515 07ca 120A     		lsrs	r2, r2, #8
+ 8516 07cc 4254     		strb	r2, [r0, r1]
+ 505:Src/main.c    **** 				{
+ 8517              		.loc 2 505 37 is_stmt 1 discriminator 3 view .LVU2813
+ 505:Src/main.c    **** 				{
+ 8518              		.loc 2 505 38 is_stmt 0 discriminator 3 view .LVU2814
+ 8519 07ce 0133     		adds	r3, r3, #1
+ 8520              	.LVL651:
+ 505:Src/main.c    **** 				{
+ 8521              		.loc 2 505 38 discriminator 3 view .LVU2815
+ 8522 07d0 9BB2     		uxth	r3, r3
+ 8523              	.LVL652:
+ 8524              	.L344:
+ 505:Src/main.c    **** 				{
+ 8525              		.loc 2 505 26 is_stmt 1 discriminator 1 view .LVU2816
+ 505:Src/main.c    **** 				{
+ 8526              		.loc 2 505 5 is_stmt 0 discriminator 1 view .LVU2817
+ 8527 07d2 0E2B     		cmp	r3, #14
+ 8528 07d4 F1D9     		bls	.L345
+ 8529              	.LBE569:
+ 515:Src/main.c    **** 				UART_transmission_request = NO_MESS;
+ 8530              		.loc 2 515 5 is_stmt 1 view .LVU2818
+ 8531 07d6 1E20     		movs	r0, #30
+ 8532 07d8 FFF7FEFF 		bl	USART_TX_DMA
+ 8533              	.LVL653:
+ 516:Src/main.c    **** 			break;
+ 8534              		.loc 2 516 5 view .LVU2819
+ 516:Src/main.c    **** 			break;
+ 8535              		.loc 2 516 31 is_stmt 0 view .LVU2820
+ 8536 07dc 294B     		ldr	r3, .L363+68
+ 8537 07de 0022     		movs	r2, #0
+ 8538 07e0 1A70     		strb	r2, [r3]
+ 517:Src/main.c    **** 			case MESS_03://Transmith saved packet
+ 8539              		.loc 2 517 4 is_stmt 1 view .LVU2821
+ 8540 07e2 71E4     		b	.L343
+ 8541              	.LVL654:
+ 8542              	.L346:
+ 8543              	.LBB570:
+ 521:Src/main.c    **** 					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+ 8544              		.loc 2 521 6 discriminator 3 view .LVU2822
+ 521:Src/main.c    **** 					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+ 8545              		.loc 2 521 33 is_stmt 0 discriminator 3 view .LVU2823
+ 8546 07e4 234A     		ldr	r2, .L363+52
+ 8547 07e6 32F81320 		ldrh	r2, [r2, r3, lsl #1]
+ 521:Src/main.c    **** 					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+ 8548              		.loc 2 521 17 discriminator 3 view .LVU2824
+ 8549 07ea 5900     		lsls	r1, r3, #1
+ 521:Src/main.c    **** 					UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff;
+ 8550              		.loc 2 521 21 discriminator 3 view .LVU2825
+ 8551 07ec 2748     		ldr	r0, .L363+76
+ 8552 07ee 00F81320 		strb	r2, [r0, r3, lsl #1]
+ 522:Src/main.c    **** 				}
+ 8553              		.loc 2 522 6 is_stmt 1 discriminator 3 view .LVU2826
+ARM GAS  /tmp/ccdsDELB.s 			page 523
+
+
+ 522:Src/main.c    **** 				}
+ 8554              		.loc 2 522 19 is_stmt 0 discriminator 3 view .LVU2827
+ 8555 07f2 0131     		adds	r1, r1, #1
+ 522:Src/main.c    **** 				}
+ 8556              		.loc 2 522 23 discriminator 3 view .LVU2828
+ 8557 07f4 120A     		lsrs	r2, r2, #8
+ 8558 07f6 4254     		strb	r2, [r0, r1]
+ 519:Src/main.c    **** 				{
+ 8559              		.loc 2 519 37 is_stmt 1 discriminator 3 view .LVU2829
+ 519:Src/main.c    **** 				{
+ 8560              		.loc 2 519 38 is_stmt 0 discriminator 3 view .LVU2830
+ 8561 07f8 0133     		adds	r3, r3, #1
+ 8562              	.LVL655:
+ 519:Src/main.c    **** 				{
+ 8563              		.loc 2 519 38 discriminator 3 view .LVU2831
+ 8564 07fa 9BB2     		uxth	r3, r3
+ 8565              	.LVL656:
+ 8566              	.L342:
+ 519:Src/main.c    **** 				{
+ 8567              		.loc 2 519 26 is_stmt 1 discriminator 1 view .LVU2832
+ 519:Src/main.c    **** 				{
+ 8568              		.loc 2 519 5 is_stmt 0 discriminator 1 view .LVU2833
+ 8569 07fc 0E2B     		cmp	r3, #14
+ 8570 07fe F1D9     		bls	.L346
+ 8571              	.LBE570:
+ 528:Src/main.c    **** 				UART_transmission_request = NO_MESS;
+ 8572              		.loc 2 528 5 is_stmt 1 view .LVU2834
+ 8573 0800 1E20     		movs	r0, #30
+ 8574 0802 FFF7FEFF 		bl	USART_TX_DMA
+ 8575              	.LVL657:
+ 529:Src/main.c    **** 			break;			
+ 8576              		.loc 2 529 5 view .LVU2835
+ 529:Src/main.c    **** 			break;			
+ 8577              		.loc 2 529 31 is_stmt 0 view .LVU2836
+ 8578 0806 1F4B     		ldr	r3, .L363+68
+ 8579 0808 0022     		movs	r2, #0
+ 8580 080a 1A70     		strb	r2, [r3]
+ 530:Src/main.c    **** 		}
+ 8581              		.loc 2 530 4 is_stmt 1 view .LVU2837
+ 8582 080c 5CE4     		b	.L343
+ 8583              	.L348:
+ 490:Src/main.c    **** 		{
+ 8584              		.loc 2 490 3 is_stmt 0 view .LVU2838
+ 8585 080e 0023     		movs	r3, #0
+ 8586 0810 F4E7     		b	.L342
+ 8587              	.L351:
+ 532:Src/main.c    **** 		{
+ 8588              		.loc 2 532 28 discriminator 1 view .LVU2839
+ 8589 0812 194B     		ldr	r3, .L363+56
+ 8590 0814 1B68     		ldr	r3, [r3]
+ 8591 0816 1E4A     		ldr	r2, .L363+80
+ 8592 0818 1268     		ldr	r2, [r2]
+ 8593 081a 9B1A     		subs	r3, r3, r2
+ 532:Src/main.c    **** 		{
+ 8594              		.loc 2 532 21 discriminator 1 view .LVU2840
+ 8595 081c 642B     		cmp	r3, #100
+ 8596 081e 7FF658AC 		bls	.L301
+ARM GAS  /tmp/ccdsDELB.s 			page 524
+
+
+ 534:Src/main.c    **** 			State_Data[0] |= UART_ERR;//timeout error!
+ 8597              		.loc 2 534 4 is_stmt 1 view .LVU2841
+ 534:Src/main.c    **** 			State_Data[0] |= UART_ERR;//timeout error!
+ 8598              		.loc 2 534 18 is_stmt 0 view .LVU2842
+ 8599 0822 0022     		movs	r2, #0
+ 8600 0824 1B4B     		ldr	r3, .L363+84
+ 8601 0826 1A80     		strh	r2, [r3]	@ movhi
+ 535:Src/main.c    **** 			UART_transmission_request = MESS_01;//Send status
+ 8602              		.loc 2 535 4 is_stmt 1 view .LVU2843
+ 535:Src/main.c    **** 			UART_transmission_request = MESS_01;//Send status
+ 8603              		.loc 2 535 18 is_stmt 0 view .LVU2844
+ 8604 0828 1549     		ldr	r1, .L363+64
+ 8605 082a 0B78     		ldrb	r3, [r1]	@ zero_extendqisi2
+ 8606 082c 43F00203 		orr	r3, r3, #2
+ 8607 0830 0B70     		strb	r3, [r1]
+ 536:Src/main.c    **** 			flg_tmt = 0;//Reset timeout flag
+ 8608              		.loc 2 536 4 is_stmt 1 view .LVU2845
+ 536:Src/main.c    **** 			flg_tmt = 0;//Reset timeout flag
+ 8609              		.loc 2 536 30 is_stmt 0 view .LVU2846
+ 8610 0832 144B     		ldr	r3, .L363+68
+ 8611 0834 0121     		movs	r1, #1
+ 8612 0836 1970     		strb	r1, [r3]
+ 537:Src/main.c    **** 		}
+ 8613              		.loc 2 537 4 is_stmt 1 view .LVU2847
+ 537:Src/main.c    **** 		}
+ 8614              		.loc 2 537 12 is_stmt 0 view .LVU2848
+ 8615 0838 174B     		ldr	r3, .L363+88
+ 8616 083a 1A70     		strb	r2, [r3]
+ 8617 083c 49E4     		b	.L301
+ 8618              	.L364:
+ 8619 083e 00BF     		.align	2
+ 8620              	.L363:
+ 8621 0840 00000000 		.word	.LANCHOR1
+ 8622 0844 00000000 		.word	.LANCHOR30
+ 8623 0848 00000000 		.word	.LANCHOR42
+ 8624 084c 00000000 		.word	.LANCHOR2
+ 8625 0850 00000000 		.word	.LANCHOR39
+ 8626 0854 00000000 		.word	.LANCHOR40
+ 8627 0858 00000000 		.word	.LANCHOR21
+ 8628 085c 00000000 		.word	.LANCHOR38
+ 8629 0860 00000000 		.word	.LANCHOR22
+ 8630 0864 000C0240 		.word	1073875968
+ 8631 0868 00000000 		.word	.LANCHOR31
+ 8632 086c 00000000 		.word	.LANCHOR32
+ 8633 0870 00000000 		.word	.LANCHOR8
+ 8634 0874 00000000 		.word	.LANCHOR6
+ 8635 0878 00000000 		.word	.LANCHOR7
+ 8636 087c 00000000 		.word	.LANCHOR41
+ 8637 0880 00000000 		.word	.LANCHOR36
+ 8638 0884 00000000 		.word	.LANCHOR37
+ 8639 0888 00000000 		.word	.LANCHOR34
+ 8640 088c 00000000 		.word	.LANCHOR23
+ 8641 0890 00000000 		.word	.LANCHOR10
+ 8642 0894 00000000 		.word	.LANCHOR12
+ 8643 0898 00000000 		.word	.LANCHOR11
+ 8644              		.cfi_endproc
+ 8645              	.LFE1186:
+ARM GAS  /tmp/ccdsDELB.s 			page 525
+
+
+ 8647              		.global	task
+ 8648              		.global	LD2_param
+ 8649              		.global	LD1_param
+ 8650              		.global	Def_setup
+ 8651              		.global	Curr_setup
+ 8652              		.global	LD2_def_setup
+ 8653              		.global	LD1_def_setup
+ 8654              		.global	LD2_curr_setup
+ 8655              		.global	LD1_curr_setup
+ 8656              		.global	sizeoffile
+ 8657              		.global	fgoto
+ 8658              		.global	test
+ 8659              		.global	fresult
+ 8660              		.global	COMMAND
+ 8661              		.global	Long_Data
+ 8662              		.global	temp16
+ 8663              		.global	CS_result
+ 8664              		.global	UART_header
+ 8665              		.global	UART_rec_incr
+ 8666              		.global	TIM10_coflag
+ 8667              		.global	u_rx_flg
+ 8668              		.global	u_tx_flg
+ 8669              		.global	flg_tmt
+ 8670              		.global	UART_DATA
+ 8671              		.global	State_Data
+ 8672              		.global	UART_transmission_request
+ 8673              		.global	CPU_state_old
+ 8674              		.global	CPU_state
+ 8675              		.global	uart_buf
+ 8676              		.global	TIM10_period
+ 8677              		.global	TO10_counter
+ 8678              		.global	TO10
+ 8679              		.global	TO7_PID
+ 8680              		.global	TO7_before
+ 8681              		.global	TO7
+ 8682              		.global	temp32
+ 8683              		.global	SD_SLIDE
+ 8684              		.global	SD_SEEK
+ 8685              		.global	TO6_uart
+ 8686              		.global	TO6_stop
+ 8687              		.global	TO6_before
+ 8688              		.global	TO6
+ 8689              		.global	htim10
+ 8690              		.global	hsd1
+ 8691              		.global	hadc3
+ 8692              		.global	hadc1
+ 8693              		.section	.bss.COMMAND,"aw",%nobits
+ 8694              		.align	2
+ 8695              		.set	.LANCHOR26,. + 0
+ 8698              	COMMAND:
+ 8699 0000 00000000 		.space	30
+ 8699      00000000 
+ 8699      00000000 
+ 8699      00000000 
+ 8699      00000000 
+ 8700              		.section	.bss.CPU_state,"aw",%nobits
+ 8701              		.set	.LANCHOR27,. + 0
+ARM GAS  /tmp/ccdsDELB.s 			page 526
+
+
+ 8704              	CPU_state:
+ 8705 0000 00       		.space	1
+ 8706              		.section	.bss.CPU_state_old,"aw",%nobits
+ 8707              		.set	.LANCHOR35,. + 0
+ 8710              	CPU_state_old:
+ 8711 0000 00       		.space	1
+ 8712              		.section	.bss.CS_result,"aw",%nobits
+ 8713              		.align	1
+ 8714              		.set	.LANCHOR34,. + 0
+ 8717              	CS_result:
+ 8718 0000 0000     		.space	2
+ 8719              		.section	.bss.Curr_setup,"aw",%nobits
+ 8720              		.align	2
+ 8721              		.set	.LANCHOR20,. + 0
+ 8724              	Curr_setup:
+ 8725 0000 00000000 		.space	18
+ 8725      00000000 
+ 8725      00000000 
+ 8725      00000000 
+ 8725      0000
+ 8726              		.section	.bss.Def_setup,"aw",%nobits
+ 8727              		.align	2
+ 8728              		.set	.LANCHOR17,. + 0
+ 8731              	Def_setup:
+ 8732 0000 00000000 		.space	18
+ 8732      00000000 
+ 8732      00000000 
+ 8732      00000000 
+ 8732      0000
+ 8733              		.section	.bss.LD1_curr_setup,"aw",%nobits
+ 8734              		.align	2
+ 8735              		.set	.LANCHOR21,. + 0
+ 8738              	LD1_curr_setup:
+ 8739 0000 00000000 		.space	16
+ 8739      00000000 
+ 8739      00000000 
+ 8739      00000000 
+ 8740              		.section	.bss.LD1_def_setup,"aw",%nobits
+ 8741              		.align	2
+ 8742              		.set	.LANCHOR18,. + 0
+ 8745              	LD1_def_setup:
+ 8746 0000 00000000 		.space	16
+ 8746      00000000 
+ 8746      00000000 
+ 8746      00000000 
+ 8747              		.section	.bss.LD1_param,"aw",%nobits
+ 8748              		.align	2
+ 8749              		.set	.LANCHOR39,. + 0
+ 8752              	LD1_param:
+ 8753 0000 00000000 		.space	12
+ 8753      00000000 
+ 8753      00000000 
+ 8754              		.section	.bss.LD2_curr_setup,"aw",%nobits
+ 8755              		.align	2
+ 8756              		.set	.LANCHOR22,. + 0
+ 8759              	LD2_curr_setup:
+ 8760 0000 00000000 		.space	16
+ARM GAS  /tmp/ccdsDELB.s 			page 527
+
+
+ 8760      00000000 
+ 8760      00000000 
+ 8760      00000000 
+ 8761              		.section	.bss.LD2_def_setup,"aw",%nobits
+ 8762              		.align	2
+ 8763              		.set	.LANCHOR19,. + 0
+ 8766              	LD2_def_setup:
+ 8767 0000 00000000 		.space	16
+ 8767      00000000 
+ 8767      00000000 
+ 8767      00000000 
+ 8768              		.section	.bss.LD2_param,"aw",%nobits
+ 8769              		.align	2
+ 8770              		.set	.LANCHOR40,. + 0
+ 8773              	LD2_param:
+ 8774 0000 00000000 		.space	12
+ 8774      00000000 
+ 8774      00000000 
+ 8775              		.section	.bss.Long_Data,"aw",%nobits
+ 8776              		.align	2
+ 8777              		.set	.LANCHOR6,. + 0
+ 8780              	Long_Data:
+ 8781 0000 00000000 		.space	30
+ 8781      00000000 
+ 8781      00000000 
+ 8781      00000000 
+ 8781      00000000 
+ 8782              		.section	.bss.SD_SEEK,"aw",%nobits
+ 8783              		.align	2
+ 8784              		.set	.LANCHOR24,. + 0
+ 8787              	SD_SEEK:
+ 8788 0000 00000000 		.space	4
+ 8789              		.section	.bss.SD_SLIDE,"aw",%nobits
+ 8790              		.align	2
+ 8791              		.set	.LANCHOR25,. + 0
+ 8794              	SD_SLIDE:
+ 8795 0000 00000000 		.space	4
+ 8796              		.section	.bss.State_Data,"aw",%nobits
+ 8797              		.align	2
+ 8798              		.set	.LANCHOR36,. + 0
+ 8801              	State_Data:
+ 8802 0000 0000     		.space	2
+ 8803              		.section	.bss.TIM10_coflag,"aw",%nobits
+ 8804              		.set	.LANCHOR31,. + 0
+ 8807              	TIM10_coflag:
+ 8808 0000 00       		.space	1
+ 8809              		.section	.bss.TIM10_period,"aw",%nobits
+ 8810              		.align	2
+ 8811              		.set	.LANCHOR42,. + 0
+ 8814              	TIM10_period:
+ 8815 0000 00000000 		.space	4
+ 8816              		.section	.bss.TO10,"aw",%nobits
+ 8817              		.align	2
+ 8818              		.set	.LANCHOR32,. + 0
+ 8821              	TO10:
+ 8822 0000 00000000 		.space	4
+ 8823              		.section	.bss.TO10_counter,"aw",%nobits
+ARM GAS  /tmp/ccdsDELB.s 			page 528
+
+
+ 8824              		.align	2
+ 8825              		.set	.LANCHOR2,. + 0
+ 8828              	TO10_counter:
+ 8829 0000 00000000 		.space	4
+ 8830              		.section	.bss.TO6,"aw",%nobits
+ 8831              		.align	2
+ 8832              		.set	.LANCHOR7,. + 0
+ 8835              	TO6:
+ 8836 0000 00000000 		.space	4
+ 8837              		.section	.bss.TO6_before,"aw",%nobits
+ 8838              		.align	2
+ 8839              		.set	.LANCHOR9,. + 0
+ 8842              	TO6_before:
+ 8843 0000 00000000 		.space	4
+ 8844              		.section	.bss.TO6_stop,"aw",%nobits
+ 8845              		.align	2
+ 8846              		.set	.LANCHOR41,. + 0
+ 8849              	TO6_stop:
+ 8850 0000 00000000 		.space	4
+ 8851              		.section	.bss.TO6_uart,"aw",%nobits
+ 8852              		.align	2
+ 8853              		.set	.LANCHOR10,. + 0
+ 8856              	TO6_uart:
+ 8857 0000 00000000 		.space	4
+ 8858              		.section	.bss.TO7,"aw",%nobits
+ 8859              		.align	2
+ 8860              		.set	.LANCHOR3,. + 0
+ 8863              	TO7:
+ 8864 0000 00000000 		.space	4
+ 8865              		.section	.bss.TO7_PID,"aw",%nobits
+ 8866              		.align	2
+ 8867              		.set	.LANCHOR4,. + 0
+ 8870              	TO7_PID:
+ 8871 0000 00000000 		.space	4
+ 8872              		.section	.bss.TO7_before,"aw",%nobits
+ 8873              		.align	2
+ 8874              		.set	.LANCHOR8,. + 0
+ 8877              	TO7_before:
+ 8878 0000 00000000 		.space	4
+ 8879              		.section	.bss.UART_DATA,"aw",%nobits
+ 8880              		.align	2
+ 8881              		.set	.LANCHOR23,. + 0
+ 8884              	UART_DATA:
+ 8885 0000 00000000 		.space	30
+ 8885      00000000 
+ 8885      00000000 
+ 8885      00000000 
+ 8885      00000000 
+ 8886              		.section	.bss.UART_header,"aw",%nobits
+ 8887              		.align	1
+ 8888              		.set	.LANCHOR33,. + 0
+ 8891              	UART_header:
+ 8892 0000 0000     		.space	2
+ 8893              		.section	.bss.UART_rec_incr,"aw",%nobits
+ 8894              		.align	1
+ 8895              		.set	.LANCHOR12,. + 0
+ 8898              	UART_rec_incr:
+ARM GAS  /tmp/ccdsDELB.s 			page 529
+
+
+ 8899 0000 0000     		.space	2
+ 8900              		.section	.bss.UART_transmission_request,"aw",%nobits
+ 8901              		.set	.LANCHOR37,. + 0
+ 8904              	UART_transmission_request:
+ 8905 0000 00       		.space	1
+ 8906              		.section	.bss.fgoto,"aw",%nobits
+ 8907              		.align	2
+ 8908              		.set	.LANCHOR13,. + 0
+ 8911              	fgoto:
+ 8912 0000 00000000 		.space	4
+ 8913              		.section	.bss.flg_tmt,"aw",%nobits
+ 8914              		.set	.LANCHOR11,. + 0
+ 8917              	flg_tmt:
+ 8918 0000 00       		.space	1
+ 8919              		.section	.bss.fresult,"aw",%nobits
+ 8922              	fresult:
+ 8923 0000 00       		.space	1
+ 8924              		.section	.bss.hadc1,"aw",%nobits
+ 8925              		.align	2
+ 8926              		.set	.LANCHOR28,. + 0
+ 8929              	hadc1:
+ 8930 0000 00000000 		.space	72
+ 8930      00000000 
+ 8930      00000000 
+ 8930      00000000 
+ 8930      00000000 
+ 8931              		.section	.bss.hadc3,"aw",%nobits
+ 8932              		.align	2
+ 8933              		.set	.LANCHOR29,. + 0
+ 8936              	hadc3:
+ 8937 0000 00000000 		.space	72
+ 8937      00000000 
+ 8937      00000000 
+ 8937      00000000 
+ 8937      00000000 
+ 8938              		.section	.bss.hsd1,"aw",%nobits
+ 8939              		.align	2
+ 8940              		.set	.LANCHOR0,. + 0
+ 8943              	hsd1:
+ 8944 0000 00000000 		.space	132
+ 8944      00000000 
+ 8944      00000000 
+ 8944      00000000 
+ 8944      00000000 
+ 8945              		.section	.bss.htim10,"aw",%nobits
+ 8946              		.align	2
+ 8947              		.set	.LANCHOR30,. + 0
+ 8950              	htim10:
+ 8951 0000 00000000 		.space	76
+ 8951      00000000 
+ 8951      00000000 
+ 8951      00000000 
+ 8951      00000000 
+ 8952              		.section	.bss.sizeoffile,"aw",%nobits
+ 8953              		.align	2
+ 8954              		.set	.LANCHOR14,. + 0
+ 8957              	sizeoffile:
+ARM GAS  /tmp/ccdsDELB.s 			page 530
+
+
+ 8958 0000 00000000 		.space	4
+ 8959              		.section	.bss.task,"aw",%nobits
+ 8960              		.align	2
+ 8961              		.set	.LANCHOR1,. + 0
+ 8964              	task:
+ 8965 0000 00000000 		.space	52
+ 8965      00000000 
+ 8965      00000000 
+ 8965      00000000 
+ 8965      00000000 
+ 8966              		.section	.bss.temp16,"aw",%nobits
+ 8967              		.align	1
+ 8968              		.set	.LANCHOR38,. + 0
+ 8971              	temp16:
+ 8972 0000 0000     		.space	2
+ 8973              		.section	.bss.temp32,"aw",%nobits
+ 8974              		.align	2
+ 8977              	temp32:
+ 8978 0000 00000000 		.space	4
+ 8979              		.section	.bss.test,"aw",%nobits
+ 8980              		.align	2
+ 8981              		.set	.LANCHOR5,. + 0
+ 8984              	test:
+ 8985 0000 00000000 		.space	4
+ 8986              		.section	.bss.u_rx_flg,"aw",%nobits
+ 8987              		.set	.LANCHOR16,. + 0
+ 8990              	u_rx_flg:
+ 8991 0000 00       		.space	1
+ 8992              		.section	.bss.u_tx_flg,"aw",%nobits
+ 8993              		.set	.LANCHOR15,. + 0
+ 8996              	u_tx_flg:
+ 8997 0000 00       		.space	1
+ 8998              		.section	.bss.uart_buf,"aw",%nobits
+ 9001              	uart_buf:
+ 9002 0000 00       		.space	1
+ 9003              		.text
+ 9004              	.Letext0:
+ 9005              		.file 9 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 9006              		.file 10 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 9007              		.file 11 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 9008              		.file 12 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 9009              		.file 13 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h"
+ 9010              		.file 14 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h"
+ 9011              		.file 15 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h"
+ 9012              		.file 16 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 9013              		.file 17 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h"
+ 9014              		.file 18 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h"
+ 9015              		.file 19 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h"
+ 9016              		.file 20 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h"
+ 9017              		.file 21 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+ 9018              		.file 22 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h"
+ 9019              		.file 23 "Inc/main.h"
+ 9020              		.file 24 "Middlewares/Third_Party/FatFs/src/ff.h"
+ 9021              		.file 25 "Inc/File_Handling.h"
+ 9022              		.file 26 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h"
+ 9023              		.file 27 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ 9024              		.file 28 "Inc/fatfs.h"
+ARM GAS  /tmp/ccdsDELB.s 			page 531
+
+
+ 9025              		.file 29 ""
+ARM GAS  /tmp/ccdsDELB.s 			page 532
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 main.c
+     /tmp/ccdsDELB.s:17     .text.NVIC_EncodePriority:0000000000000000 $t
+     /tmp/ccdsDELB.s:24     .text.NVIC_EncodePriority:0000000000000000 NVIC_EncodePriority
+     /tmp/ccdsDELB.s:84     .text.MX_SDMMC1_SD_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:90     .text.MX_SDMMC1_SD_Init:0000000000000000 MX_SDMMC1_SD_Init
+     /tmp/ccdsDELB.s:129    .text.MX_SDMMC1_SD_Init:000000000000001c $d
+     /tmp/ccdsDELB.s:135    .text.MX_DMA_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:141    .text.MX_DMA_Init:0000000000000000 MX_DMA_Init
+     /tmp/ccdsDELB.s:237    .text.MX_DMA_Init:000000000000003c $d
+     /tmp/ccdsDELB.s:244    .text.Decode_task:0000000000000000 $t
+     /tmp/ccdsDELB.s:250    .text.Decode_task:0000000000000000 Decode_task
+     /tmp/ccdsDELB.s:529    .text.Decode_task:0000000000000150 $d
+     /tmp/ccdsDELB.s:539    .text.PID_Controller_Temp:0000000000000000 $t
+     /tmp/ccdsDELB.s:545    .text.PID_Controller_Temp:0000000000000000 PID_Controller_Temp
+     /tmp/ccdsDELB.s:714    .text.PID_Controller_Temp:00000000000000cc $d
+     /tmp/ccdsDELB.s:724    .text.Set_LTEC:0000000000000000 $t
+     /tmp/ccdsDELB.s:730    .text.Set_LTEC:0000000000000000 Set_LTEC
+     /tmp/ccdsDELB.s:755    .text.Set_LTEC:000000000000000e $d
+     /tmp/ccdsDELB.s:759    .text.Set_LTEC:0000000000000012 $t
+     /tmp/ccdsDELB.s:1168   .text.Set_LTEC:0000000000000148 $d
+     /tmp/ccdsDELB.s:1176   .text.MPhD_T:0000000000000000 $t
+     /tmp/ccdsDELB.s:1182   .text.MPhD_T:0000000000000000 MPhD_T
+     /tmp/ccdsDELB.s:1793   .text.MPhD_T:0000000000000214 $d
+     /tmp/ccdsDELB.s:1803   .text.MX_GPIO_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:1809   .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init
+     /tmp/ccdsDELB.s:2219   .text.MX_GPIO_Init:00000000000001f4 $d
+     /tmp/ccdsDELB.s:2230   .text.MX_SPI4_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:2236   .text.MX_SPI4_Init:0000000000000000 MX_SPI4_Init
+     /tmp/ccdsDELB.s:2441   .text.MX_SPI4_Init:00000000000000c8 $d
+     /tmp/ccdsDELB.s:2448   .text.MX_SPI2_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:2454   .text.MX_SPI2_Init:0000000000000000 MX_SPI2_Init
+     /tmp/ccdsDELB.s:2659   .text.MX_SPI2_Init:00000000000000c4 $d
+     /tmp/ccdsDELB.s:2666   .text.MX_SPI5_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:2672   .text.MX_SPI5_Init:0000000000000000 MX_SPI5_Init
+     /tmp/ccdsDELB.s:2877   .text.MX_SPI5_Init:00000000000000c4 $d
+     /tmp/ccdsDELB.s:2884   .text.MX_SPI6_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:2890   .text.MX_SPI6_Init:0000000000000000 MX_SPI6_Init
+     /tmp/ccdsDELB.s:3095   .text.MX_SPI6_Init:00000000000000c4 $d
+     /tmp/ccdsDELB.s:3102   .text.MX_TIM2_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:3108   .text.MX_TIM2_Init:0000000000000000 MX_TIM2_Init
+     /tmp/ccdsDELB.s:3286   .text.MX_TIM2_Init:0000000000000088 $d
+     /tmp/ccdsDELB.s:3295   .text.MX_TIM5_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:3301   .text.MX_TIM5_Init:0000000000000000 MX_TIM5_Init
+     /tmp/ccdsDELB.s:3478   .text.MX_TIM5_Init:0000000000000084 $d
+     /tmp/ccdsDELB.s:3487   .text.MX_TIM7_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:3493   .text.MX_TIM7_Init:0000000000000000 MX_TIM7_Init
+     /tmp/ccdsDELB.s:3654   .text.MX_TIM7_Init:000000000000007c $d
+     /tmp/ccdsDELB.s:3662   .text.MX_TIM6_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:3668   .text.MX_TIM6_Init:0000000000000000 MX_TIM6_Init
+     /tmp/ccdsDELB.s:3829   .text.MX_TIM6_Init:000000000000007c $d
+     /tmp/ccdsDELB.s:3837   .rodata.Decode_uart.str1.4:0000000000000000 $d
+     /tmp/ccdsDELB.s:3844   .text.Decode_uart:0000000000000000 $t
+     /tmp/ccdsDELB.s:3850   .text.Decode_uart:0000000000000000 Decode_uart
+     /tmp/ccdsDELB.s:4413   .text.Decode_uart:00000000000002cc $d
+     /tmp/ccdsDELB.s:4428   .text.Init_params:0000000000000000 $t
+     /tmp/ccdsDELB.s:4434   .text.Init_params:0000000000000000 Init_params
+ARM GAS  /tmp/ccdsDELB.s 			page 533
+
+
+     /tmp/ccdsDELB.s:5077   .text.Init_params:0000000000000278 $d
+     /tmp/ccdsDELB.s:5116   .text.Get_ADC:0000000000000000 $t
+     /tmp/ccdsDELB.s:5122   .text.Get_ADC:0000000000000000 Get_ADC
+     /tmp/ccdsDELB.s:5142   .text.Get_ADC:000000000000000c $d
+     /tmp/ccdsDELB.s:5148   .text.Get_ADC:0000000000000012 $t
+     /tmp/ccdsDELB.s:5246   .text.Get_ADC:0000000000000068 $d
+     /tmp/ccdsDELB.s:5252   .text.Stop_TIM10:0000000000000000 $t
+     /tmp/ccdsDELB.s:5258   .text.Stop_TIM10:0000000000000000 Stop_TIM10
+     /tmp/ccdsDELB.s:5287   .text.Stop_TIM10:0000000000000014 $d
+     /tmp/ccdsDELB.s:5294   .text.CalculateChecksum:0000000000000000 $t
+     /tmp/ccdsDELB.s:5301   .text.CalculateChecksum:0000000000000000 CalculateChecksum
+     /tmp/ccdsDELB.s:5348   .text.CheckChecksum:0000000000000000 $t
+     /tmp/ccdsDELB.s:5355   .text.CheckChecksum:0000000000000000 CheckChecksum
+     /tmp/ccdsDELB.s:5417   .text.CheckChecksum:000000000000003c $d
+     /tmp/ccdsDELB.s:5424   .rodata.SD_SAVE.str1.4:0000000000000000 $d
+     /tmp/ccdsDELB.s:5428   .text.SD_SAVE:0000000000000000 $t
+     /tmp/ccdsDELB.s:5435   .text.SD_SAVE:0000000000000000 SD_SAVE
+     /tmp/ccdsDELB.s:5504   .text.SD_SAVE:0000000000000030 $d
+     /tmp/ccdsDELB.s:5511   .text.SD_READ:0000000000000000 $t
+     /tmp/ccdsDELB.s:5518   .text.SD_READ:0000000000000000 SD_READ
+     /tmp/ccdsDELB.s:5596   .text.SD_READ:000000000000003c $d
+     /tmp/ccdsDELB.s:5604   .text.SD_REMOVE:0000000000000000 $t
+     /tmp/ccdsDELB.s:5611   .text.SD_REMOVE:0000000000000000 SD_REMOVE
+     /tmp/ccdsDELB.s:5679   .text.SD_REMOVE:0000000000000034 $d
+     /tmp/ccdsDELB.s:5686   .text.USART_TX:0000000000000000 $t
+     /tmp/ccdsDELB.s:5693   .text.USART_TX:0000000000000000 USART_TX
+     /tmp/ccdsDELB.s:5770   .text.USART_TX:0000000000000028 $d
+     /tmp/ccdsDELB.s:5775   .text.USART_TX_DMA:0000000000000000 $t
+     /tmp/ccdsDELB.s:5782   .text.USART_TX_DMA:0000000000000000 USART_TX_DMA
+     /tmp/ccdsDELB.s:5854   .text.USART_TX_DMA:0000000000000038 $d
+     /tmp/ccdsDELB.s:5861   .text.Error_Handler:0000000000000000 $t
+     /tmp/ccdsDELB.s:5868   .text.Error_Handler:0000000000000000 Error_Handler
+     /tmp/ccdsDELB.s:5899   .text.MX_ADC1_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:5905   .text.MX_ADC1_Init:0000000000000000 MX_ADC1_Init
+     /tmp/ccdsDELB.s:6094   .text.MX_ADC1_Init:00000000000000bc $d
+     /tmp/ccdsDELB.s:6101   .text.MX_ADC3_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:6107   .text.MX_ADC3_Init:0000000000000000 MX_ADC3_Init
+     /tmp/ccdsDELB.s:6214   .text.MX_ADC3_Init:0000000000000060 $d
+     /tmp/ccdsDELB.s:6221   .text.MX_USART1_UART_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:6227   .text.MX_USART1_UART_Init:0000000000000000 MX_USART1_UART_Init
+     /tmp/ccdsDELB.s:6626   .text.MX_USART1_UART_Init:000000000000017c $d
+     /tmp/ccdsDELB.s:6635   .text.MX_TIM10_Init:0000000000000000 $t
+     /tmp/ccdsDELB.s:6641   .text.MX_TIM10_Init:0000000000000000 MX_TIM10_Init
+     /tmp/ccdsDELB.s:6690   .text.MX_TIM10_Init:0000000000000024 $d
+     /tmp/ccdsDELB.s:6696   .text.SystemClock_Config:0000000000000000 $t
+     /tmp/ccdsDELB.s:6703   .text.SystemClock_Config:0000000000000000 SystemClock_Config
+     /tmp/ccdsDELB.s:6862   .text.SystemClock_Config:00000000000000ac $d
+     /tmp/ccdsDELB.s:6868   .text.main:0000000000000000 $t
+     /tmp/ccdsDELB.s:6875   .text.main:0000000000000000 main
+     /tmp/ccdsDELB.s:7208   .text.main:00000000000000f0 $d
+     /tmp/ccdsDELB.s:7218   .text.main:0000000000000118 $t
+     /tmp/ccdsDELB.s:7468   .text.main:0000000000000224 $d
+     /tmp/ccdsDELB.s:7492   .text.main:0000000000000278 $t
+     /tmp/ccdsDELB.s:8034   .text.main:000000000000052c $d
+     /tmp/ccdsDELB.s:8063   .text.main:0000000000000594 $t
+     /tmp/ccdsDELB.s:8621   .text.main:0000000000000840 $d
+     /tmp/ccdsDELB.s:8964   .bss.task:0000000000000000 task
+ARM GAS  /tmp/ccdsDELB.s 			page 534
+
+
+     /tmp/ccdsDELB.s:8773   .bss.LD2_param:0000000000000000 LD2_param
+     /tmp/ccdsDELB.s:8752   .bss.LD1_param:0000000000000000 LD1_param
+     /tmp/ccdsDELB.s:8731   .bss.Def_setup:0000000000000000 Def_setup
+     /tmp/ccdsDELB.s:8724   .bss.Curr_setup:0000000000000000 Curr_setup
+     /tmp/ccdsDELB.s:8766   .bss.LD2_def_setup:0000000000000000 LD2_def_setup
+     /tmp/ccdsDELB.s:8745   .bss.LD1_def_setup:0000000000000000 LD1_def_setup
+     /tmp/ccdsDELB.s:8759   .bss.LD2_curr_setup:0000000000000000 LD2_curr_setup
+     /tmp/ccdsDELB.s:8738   .bss.LD1_curr_setup:0000000000000000 LD1_curr_setup
+     /tmp/ccdsDELB.s:8957   .bss.sizeoffile:0000000000000000 sizeoffile
+     /tmp/ccdsDELB.s:8911   .bss.fgoto:0000000000000000 fgoto
+     /tmp/ccdsDELB.s:8984   .bss.test:0000000000000000 test
+     /tmp/ccdsDELB.s:8922   .bss.fresult:0000000000000000 fresult
+     /tmp/ccdsDELB.s:8698   .bss.COMMAND:0000000000000000 COMMAND
+     /tmp/ccdsDELB.s:8780   .bss.Long_Data:0000000000000000 Long_Data
+     /tmp/ccdsDELB.s:8971   .bss.temp16:0000000000000000 temp16
+     /tmp/ccdsDELB.s:8717   .bss.CS_result:0000000000000000 CS_result
+     /tmp/ccdsDELB.s:8891   .bss.UART_header:0000000000000000 UART_header
+     /tmp/ccdsDELB.s:8898   .bss.UART_rec_incr:0000000000000000 UART_rec_incr
+     /tmp/ccdsDELB.s:8807   .bss.TIM10_coflag:0000000000000000 TIM10_coflag
+     /tmp/ccdsDELB.s:8990   .bss.u_rx_flg:0000000000000000 u_rx_flg
+     /tmp/ccdsDELB.s:8996   .bss.u_tx_flg:0000000000000000 u_tx_flg
+     /tmp/ccdsDELB.s:8917   .bss.flg_tmt:0000000000000000 flg_tmt
+     /tmp/ccdsDELB.s:8884   .bss.UART_DATA:0000000000000000 UART_DATA
+     /tmp/ccdsDELB.s:8801   .bss.State_Data:0000000000000000 State_Data
+     /tmp/ccdsDELB.s:8904   .bss.UART_transmission_request:0000000000000000 UART_transmission_request
+     /tmp/ccdsDELB.s:8710   .bss.CPU_state_old:0000000000000000 CPU_state_old
+     /tmp/ccdsDELB.s:8704   .bss.CPU_state:0000000000000000 CPU_state
+     /tmp/ccdsDELB.s:9001   .bss.uart_buf:0000000000000000 uart_buf
+     /tmp/ccdsDELB.s:8814   .bss.TIM10_period:0000000000000000 TIM10_period
+     /tmp/ccdsDELB.s:8828   .bss.TO10_counter:0000000000000000 TO10_counter
+     /tmp/ccdsDELB.s:8821   .bss.TO10:0000000000000000 TO10
+     /tmp/ccdsDELB.s:8870   .bss.TO7_PID:0000000000000000 TO7_PID
+     /tmp/ccdsDELB.s:8877   .bss.TO7_before:0000000000000000 TO7_before
+     /tmp/ccdsDELB.s:8863   .bss.TO7:0000000000000000 TO7
+     /tmp/ccdsDELB.s:8977   .bss.temp32:0000000000000000 temp32
+     /tmp/ccdsDELB.s:8794   .bss.SD_SLIDE:0000000000000000 SD_SLIDE
+     /tmp/ccdsDELB.s:8787   .bss.SD_SEEK:0000000000000000 SD_SEEK
+     /tmp/ccdsDELB.s:8856   .bss.TO6_uart:0000000000000000 TO6_uart
+     /tmp/ccdsDELB.s:8849   .bss.TO6_stop:0000000000000000 TO6_stop
+     /tmp/ccdsDELB.s:8842   .bss.TO6_before:0000000000000000 TO6_before
+     /tmp/ccdsDELB.s:8835   .bss.TO6:0000000000000000 TO6
+     /tmp/ccdsDELB.s:8950   .bss.htim10:0000000000000000 htim10
+     /tmp/ccdsDELB.s:8943   .bss.hsd1:0000000000000000 hsd1
+     /tmp/ccdsDELB.s:8936   .bss.hadc3:0000000000000000 hadc3
+     /tmp/ccdsDELB.s:8929   .bss.hadc1:0000000000000000 hadc1
+     /tmp/ccdsDELB.s:8694   .bss.COMMAND:0000000000000000 $d
+     /tmp/ccdsDELB.s:8705   .bss.CPU_state:0000000000000000 $d
+     /tmp/ccdsDELB.s:8711   .bss.CPU_state_old:0000000000000000 $d
+     /tmp/ccdsDELB.s:8713   .bss.CS_result:0000000000000000 $d
+     /tmp/ccdsDELB.s:8720   .bss.Curr_setup:0000000000000000 $d
+     /tmp/ccdsDELB.s:8727   .bss.Def_setup:0000000000000000 $d
+     /tmp/ccdsDELB.s:8734   .bss.LD1_curr_setup:0000000000000000 $d
+     /tmp/ccdsDELB.s:8741   .bss.LD1_def_setup:0000000000000000 $d
+     /tmp/ccdsDELB.s:8748   .bss.LD1_param:0000000000000000 $d
+     /tmp/ccdsDELB.s:8755   .bss.LD2_curr_setup:0000000000000000 $d
+     /tmp/ccdsDELB.s:8762   .bss.LD2_def_setup:0000000000000000 $d
+     /tmp/ccdsDELB.s:8769   .bss.LD2_param:0000000000000000 $d
+ARM GAS  /tmp/ccdsDELB.s 			page 535
+
+
+     /tmp/ccdsDELB.s:8776   .bss.Long_Data:0000000000000000 $d
+     /tmp/ccdsDELB.s:8783   .bss.SD_SEEK:0000000000000000 $d
+     /tmp/ccdsDELB.s:8790   .bss.SD_SLIDE:0000000000000000 $d
+     /tmp/ccdsDELB.s:8797   .bss.State_Data:0000000000000000 $d
+     /tmp/ccdsDELB.s:8808   .bss.TIM10_coflag:0000000000000000 $d
+     /tmp/ccdsDELB.s:8810   .bss.TIM10_period:0000000000000000 $d
+     /tmp/ccdsDELB.s:8817   .bss.TO10:0000000000000000 $d
+     /tmp/ccdsDELB.s:8824   .bss.TO10_counter:0000000000000000 $d
+     /tmp/ccdsDELB.s:8831   .bss.TO6:0000000000000000 $d
+     /tmp/ccdsDELB.s:8838   .bss.TO6_before:0000000000000000 $d
+     /tmp/ccdsDELB.s:8845   .bss.TO6_stop:0000000000000000 $d
+     /tmp/ccdsDELB.s:8852   .bss.TO6_uart:0000000000000000 $d
+     /tmp/ccdsDELB.s:8859   .bss.TO7:0000000000000000 $d
+     /tmp/ccdsDELB.s:8866   .bss.TO7_PID:0000000000000000 $d
+     /tmp/ccdsDELB.s:8873   .bss.TO7_before:0000000000000000 $d
+     /tmp/ccdsDELB.s:8880   .bss.UART_DATA:0000000000000000 $d
+     /tmp/ccdsDELB.s:8887   .bss.UART_header:0000000000000000 $d
+     /tmp/ccdsDELB.s:8894   .bss.UART_rec_incr:0000000000000000 $d
+     /tmp/ccdsDELB.s:8905   .bss.UART_transmission_request:0000000000000000 $d
+     /tmp/ccdsDELB.s:8907   .bss.fgoto:0000000000000000 $d
+     /tmp/ccdsDELB.s:8918   .bss.flg_tmt:0000000000000000 $d
+     /tmp/ccdsDELB.s:8923   .bss.fresult:0000000000000000 $d
+     /tmp/ccdsDELB.s:8925   .bss.hadc1:0000000000000000 $d
+     /tmp/ccdsDELB.s:8932   .bss.hadc3:0000000000000000 $d
+     /tmp/ccdsDELB.s:8939   .bss.hsd1:0000000000000000 $d
+     /tmp/ccdsDELB.s:8946   .bss.htim10:0000000000000000 $d
+     /tmp/ccdsDELB.s:8953   .bss.sizeoffile:0000000000000000 $d
+     /tmp/ccdsDELB.s:8960   .bss.task:0000000000000000 $d
+     /tmp/ccdsDELB.s:8967   .bss.temp16:0000000000000000 $d
+     /tmp/ccdsDELB.s:8974   .bss.temp32:0000000000000000 $d
+     /tmp/ccdsDELB.s:8980   .bss.test:0000000000000000 $d
+     /tmp/ccdsDELB.s:8991   .bss.u_rx_flg:0000000000000000 $d
+     /tmp/ccdsDELB.s:8997   .bss.u_tx_flg:0000000000000000 $d
+     /tmp/ccdsDELB.s:9002   .bss.uart_buf:0000000000000000 $d
+
+UNDEFINED SYMBOLS
+HAL_GPIO_WritePin
+HAL_GPIO_Init
+memset
+LL_GPIO_Init
+LL_SPI_Init
+LL_TIM_Init
+HAL_GPIO_ReadPin
+Mount_SD
+Remove_File
+Create_File
+Write_File_byte
+Update_File_byte
+Unmount_SD
+Seek_Read_File
+HAL_ADC_Start
+HAL_ADC_PollForConversion
+HAL_ADC_GetValue
+HAL_ADC_Stop
+HAL_TIM_Base_Stop_IT
+HAL_ADC_Init
+HAL_ADC_ConfigChannel
+ARM GAS  /tmp/ccdsDELB.s 			page 536
+
+
+HAL_RCCEx_PeriphCLKConfig
+LL_USART_Init
+HAL_TIM_Base_Init
+HAL_RCC_OscConfig
+HAL_PWREx_EnableOverDrive
+HAL_RCC_ClockConfig
+HAL_Init
+MX_FATFS_Init
+HAL_TIM_Base_Start_IT
diff --git a/build/main.o b/build/main.o
new file mode 100644
index 0000000..2e4ba8c
Binary files /dev/null and b/build/main.o differ
diff --git a/build/sd_diskio.d b/build/sd_diskio.d
new file mode 100644
index 0000000..01c7bd7
--- /dev/null
+++ b/build/sd_diskio.d
@@ -0,0 +1,101 @@
+build/sd_diskio.o: Src/sd_diskio.c \
+ Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \
+ Middlewares/Third_Party/FatFs/src/diskio.h \
+ Middlewares/Third_Party/FatFs/src/integer.h \
+ Middlewares/Third_Party/FatFs/src/ff.h Inc/ffconf.h Inc/main.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/bsp_driver_sd.h \
+ Inc/fatfs_platform.h Inc/sd_diskio.h
+Middlewares/Third_Party/FatFs/src/ff_gen_drv.h:
+Middlewares/Third_Party/FatFs/src/diskio.h:
+Middlewares/Third_Party/FatFs/src/integer.h:
+Middlewares/Third_Party/FatFs/src/ff.h:
+Inc/ffconf.h:
+Inc/main.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h:
+Inc/bsp_driver_sd.h:
+Inc/fatfs_platform.h:
+Inc/sd_diskio.h:
diff --git a/build/sd_diskio.lst b/build/sd_diskio.lst
new file mode 100644
index 0000000..d3e0a6a
--- /dev/null
+++ b/build/sd_diskio.lst
@@ -0,0 +1,747 @@
+ARM GAS  /tmp/ccixANLj.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"sd_diskio.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.SD_CheckStatus,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	SD_CheckStatus:
+  25              	.LVL0:
+  26              	.LFB1183:
+  27              		.file 1 "Src/sd_diskio.c"
+   1:Src/sd_diskio.c **** /* USER CODE BEGIN Header */
+   2:Src/sd_diskio.c **** /**
+   3:Src/sd_diskio.c ****   ******************************************************************************
+   4:Src/sd_diskio.c ****   * @file    sd_diskio.c
+   5:Src/sd_diskio.c ****   * @brief   SD Disk I/O driver
+   6:Src/sd_diskio.c ****   ******************************************************************************
+   7:Src/sd_diskio.c ****   * @attention
+   8:Src/sd_diskio.c ****   *
+   9:Src/sd_diskio.c ****   * Copyright (c) 2023 STMicroelectronics.
+  10:Src/sd_diskio.c ****   * All rights reserved.
+  11:Src/sd_diskio.c ****   *
+  12:Src/sd_diskio.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Src/sd_diskio.c ****   * in the root directory of this software component.
+  14:Src/sd_diskio.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Src/sd_diskio.c ****   *
+  16:Src/sd_diskio.c ****   ******************************************************************************
+  17:Src/sd_diskio.c ****   */
+  18:Src/sd_diskio.c **** /* USER CODE END Header */
+  19:Src/sd_diskio.c **** 
+  20:Src/sd_diskio.c **** /* Note: code generation based on sd_diskio_template_bspv1.c v2.1.4
+  21:Src/sd_diskio.c ****    as "Use dma template" is disabled. */
+  22:Src/sd_diskio.c **** 
+  23:Src/sd_diskio.c **** /* USER CODE BEGIN firstSection */
+  24:Src/sd_diskio.c **** /* can be used to modify / undefine following code or add new definitions */
+  25:Src/sd_diskio.c **** /* USER CODE END firstSection*/
+  26:Src/sd_diskio.c **** 
+  27:Src/sd_diskio.c **** /* Includes ------------------------------------------------------------------*/
+  28:Src/sd_diskio.c **** #include "ff_gen_drv.h"
+  29:Src/sd_diskio.c **** #include "sd_diskio.h"
+  30:Src/sd_diskio.c **** 
+  31:Src/sd_diskio.c **** /* Private typedef -----------------------------------------------------------*/
+ARM GAS  /tmp/ccixANLj.s 			page 2
+
+
+  32:Src/sd_diskio.c **** /* Private define ------------------------------------------------------------*/
+  33:Src/sd_diskio.c **** /* use the default SD timout as defined in the platform BSP driver*/
+  34:Src/sd_diskio.c **** #if defined(SDMMC_DATATIMEOUT)
+  35:Src/sd_diskio.c **** #define SD_TIMEOUT SDMMC_DATATIMEOUT
+  36:Src/sd_diskio.c **** #elif defined(SD_DATATIMEOUT)
+  37:Src/sd_diskio.c **** #define SD_TIMEOUT SD_DATATIMEOUT
+  38:Src/sd_diskio.c **** #else
+  39:Src/sd_diskio.c **** #define SD_TIMEOUT 30 * 1000
+  40:Src/sd_diskio.c **** #endif
+  41:Src/sd_diskio.c **** 
+  42:Src/sd_diskio.c **** #define SD_DEFAULT_BLOCK_SIZE 512
+  43:Src/sd_diskio.c **** 
+  44:Src/sd_diskio.c **** /*
+  45:Src/sd_diskio.c ****  * Depending on the use case, the SD card initialization could be done at the
+  46:Src/sd_diskio.c ****  * application level: if it is the case define the flag below to disable
+  47:Src/sd_diskio.c ****  * the BSP_SD_Init() call in the SD_Initialize() and add a call to
+  48:Src/sd_diskio.c ****  * BSP_SD_Init() elsewhere in the application.
+  49:Src/sd_diskio.c ****  */
+  50:Src/sd_diskio.c **** /* USER CODE BEGIN disableSDInit */
+  51:Src/sd_diskio.c **** /* #define DISABLE_SD_INIT */
+  52:Src/sd_diskio.c **** /* USER CODE END disableSDInit */
+  53:Src/sd_diskio.c **** 
+  54:Src/sd_diskio.c **** /* Private variables ---------------------------------------------------------*/
+  55:Src/sd_diskio.c **** /* Disk status */
+  56:Src/sd_diskio.c **** static volatile DSTATUS Stat = STA_NOINIT;
+  57:Src/sd_diskio.c **** 
+  58:Src/sd_diskio.c **** /* Private function prototypes -----------------------------------------------*/
+  59:Src/sd_diskio.c **** static DSTATUS SD_CheckStatus(BYTE lun);
+  60:Src/sd_diskio.c **** DSTATUS SD_initialize (BYTE);
+  61:Src/sd_diskio.c **** DSTATUS SD_status (BYTE);
+  62:Src/sd_diskio.c **** DRESULT SD_read (BYTE, BYTE*, DWORD, UINT);
+  63:Src/sd_diskio.c **** #if _USE_WRITE == 1
+  64:Src/sd_diskio.c **** DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT);
+  65:Src/sd_diskio.c **** #endif /* _USE_WRITE == 1 */
+  66:Src/sd_diskio.c **** #if _USE_IOCTL == 1
+  67:Src/sd_diskio.c **** DRESULT SD_ioctl (BYTE, BYTE, void*);
+  68:Src/sd_diskio.c **** #endif  /* _USE_IOCTL == 1 */
+  69:Src/sd_diskio.c **** 
+  70:Src/sd_diskio.c **** const Diskio_drvTypeDef  SD_Driver =
+  71:Src/sd_diskio.c **** {
+  72:Src/sd_diskio.c ****   SD_initialize,
+  73:Src/sd_diskio.c ****   SD_status,
+  74:Src/sd_diskio.c ****   SD_read,
+  75:Src/sd_diskio.c **** #if  _USE_WRITE == 1
+  76:Src/sd_diskio.c ****   SD_write,
+  77:Src/sd_diskio.c **** #endif /* _USE_WRITE == 1 */
+  78:Src/sd_diskio.c **** 
+  79:Src/sd_diskio.c **** #if  _USE_IOCTL == 1
+  80:Src/sd_diskio.c ****   SD_ioctl,
+  81:Src/sd_diskio.c **** #endif /* _USE_IOCTL == 1 */
+  82:Src/sd_diskio.c **** };
+  83:Src/sd_diskio.c **** 
+  84:Src/sd_diskio.c **** /* USER CODE BEGIN beforeFunctionSection */
+  85:Src/sd_diskio.c **** /* can be used to modify / undefine following code or add new code */
+  86:Src/sd_diskio.c **** /* USER CODE END beforeFunctionSection */
+  87:Src/sd_diskio.c **** 
+  88:Src/sd_diskio.c **** /* Private functions ---------------------------------------------------------*/
+ARM GAS  /tmp/ccixANLj.s 			page 3
+
+
+  89:Src/sd_diskio.c **** 
+  90:Src/sd_diskio.c **** static DSTATUS SD_CheckStatus(BYTE lun)
+  91:Src/sd_diskio.c **** {
+  28              		.loc 1 91 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		.loc 1 91 1 is_stmt 0 view .LVU1
+  33 0000 08B5     		push	{r3, lr}
+  34              	.LCFI0:
+  35              		.cfi_def_cfa_offset 8
+  36              		.cfi_offset 3, -8
+  37              		.cfi_offset 14, -4
+  92:Src/sd_diskio.c ****   Stat = STA_NOINIT;
+  38              		.loc 1 92 3 is_stmt 1 view .LVU2
+  39              		.loc 1 92 8 is_stmt 0 view .LVU3
+  40 0002 074B     		ldr	r3, .L4
+  41 0004 0122     		movs	r2, #1
+  42 0006 1A70     		strb	r2, [r3]
+  93:Src/sd_diskio.c **** 
+  94:Src/sd_diskio.c ****   if(BSP_SD_GetCardState() == MSD_OK)
+  43              		.loc 1 94 3 is_stmt 1 view .LVU4
+  44              		.loc 1 94 6 is_stmt 0 view .LVU5
+  45 0008 FFF7FEFF 		bl	BSP_SD_GetCardState
+  46              	.LVL1:
+  47              		.loc 1 94 5 view .LVU6
+  48 000c 20B9     		cbnz	r0, .L2
+  95:Src/sd_diskio.c ****   {
+  96:Src/sd_diskio.c ****     Stat &= ~STA_NOINIT;
+  49              		.loc 1 96 5 is_stmt 1 view .LVU7
+  50              		.loc 1 96 10 is_stmt 0 view .LVU8
+  51 000e 044A     		ldr	r2, .L4
+  52 0010 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
+  53 0012 03F0FE03 		and	r3, r3, #254
+  54 0016 1370     		strb	r3, [r2]
+  55              	.L2:
+  97:Src/sd_diskio.c ****   }
+  98:Src/sd_diskio.c **** 
+  99:Src/sd_diskio.c ****   return Stat;
+  56              		.loc 1 99 3 is_stmt 1 view .LVU9
+  57              		.loc 1 99 10 is_stmt 0 view .LVU10
+  58 0018 014B     		ldr	r3, .L4
+  59 001a 1878     		ldrb	r0, [r3]	@ zero_extendqisi2
+ 100:Src/sd_diskio.c **** }
+  60              		.loc 1 100 1 view .LVU11
+  61 001c 08BD     		pop	{r3, pc}
+  62              	.L5:
+  63 001e 00BF     		.align	2
+  64              	.L4:
+  65 0020 00000000 		.word	.LANCHOR0
+  66              		.cfi_endproc
+  67              	.LFE1183:
+  69              		.section	.text.SD_initialize,"ax",%progbits
+  70              		.align	1
+  71              		.global	SD_initialize
+  72              		.syntax unified
+  73              		.thumb
+ARM GAS  /tmp/ccixANLj.s 			page 4
+
+
+  74              		.thumb_func
+  75              		.fpu fpv5-d16
+  77              	SD_initialize:
+  78              	.LVL2:
+  79              	.LFB1184:
+ 101:Src/sd_diskio.c **** 
+ 102:Src/sd_diskio.c **** /**
+ 103:Src/sd_diskio.c ****   * @brief  Initializes a Drive
+ 104:Src/sd_diskio.c ****   * @param  lun : not used
+ 105:Src/sd_diskio.c ****   * @retval DSTATUS: Operation status
+ 106:Src/sd_diskio.c ****   */
+ 107:Src/sd_diskio.c **** DSTATUS SD_initialize(BYTE lun)
+ 108:Src/sd_diskio.c **** {
+  80              		.loc 1 108 1 is_stmt 1 view -0
+  81              		.cfi_startproc
+  82              		@ args = 0, pretend = 0, frame = 0
+  83              		@ frame_needed = 0, uses_anonymous_args = 0
+  84              		.loc 1 108 1 is_stmt 0 view .LVU13
+  85 0000 10B5     		push	{r4, lr}
+  86              	.LCFI1:
+  87              		.cfi_def_cfa_offset 8
+  88              		.cfi_offset 4, -8
+  89              		.cfi_offset 14, -4
+  90 0002 0446     		mov	r4, r0
+ 109:Src/sd_diskio.c **** Stat = STA_NOINIT;
+  91              		.loc 1 109 1 is_stmt 1 view .LVU14
+  92              		.loc 1 109 6 is_stmt 0 view .LVU15
+  93 0004 074B     		ldr	r3, .L10
+  94 0006 0122     		movs	r2, #1
+  95 0008 1A70     		strb	r2, [r3]
+ 110:Src/sd_diskio.c **** 
+ 111:Src/sd_diskio.c **** #if !defined(DISABLE_SD_INIT)
+ 112:Src/sd_diskio.c **** 
+ 113:Src/sd_diskio.c ****   if(BSP_SD_Init() == MSD_OK)
+  96              		.loc 1 113 3 is_stmt 1 view .LVU16
+  97              		.loc 1 113 6 is_stmt 0 view .LVU17
+  98 000a FFF7FEFF 		bl	BSP_SD_Init
+  99              	.LVL3:
+ 100              		.loc 1 113 5 view .LVU18
+ 101 000e 10B1     		cbz	r0, .L9
+ 102              	.L7:
+ 114:Src/sd_diskio.c ****   {
+ 115:Src/sd_diskio.c ****     Stat = SD_CheckStatus(lun);
+ 116:Src/sd_diskio.c ****   }
+ 117:Src/sd_diskio.c **** 
+ 118:Src/sd_diskio.c **** #else
+ 119:Src/sd_diskio.c ****   Stat = SD_CheckStatus(lun);
+ 120:Src/sd_diskio.c **** #endif
+ 121:Src/sd_diskio.c **** 
+ 122:Src/sd_diskio.c ****   return Stat;
+ 103              		.loc 1 122 3 is_stmt 1 view .LVU19
+ 104              		.loc 1 122 10 is_stmt 0 view .LVU20
+ 105 0010 044B     		ldr	r3, .L10
+ 106 0012 1878     		ldrb	r0, [r3]	@ zero_extendqisi2
+ 123:Src/sd_diskio.c **** }
+ 107              		.loc 1 123 1 view .LVU21
+ 108 0014 10BD     		pop	{r4, pc}
+ARM GAS  /tmp/ccixANLj.s 			page 5
+
+
+ 109              	.L9:
+ 115:Src/sd_diskio.c ****   }
+ 110              		.loc 1 115 5 is_stmt 1 view .LVU22
+ 115:Src/sd_diskio.c ****   }
+ 111              		.loc 1 115 12 is_stmt 0 view .LVU23
+ 112 0016 2046     		mov	r0, r4
+ 113 0018 FFF7FEFF 		bl	SD_CheckStatus
+ 114              	.LVL4:
+ 115:Src/sd_diskio.c ****   }
+ 115              		.loc 1 115 10 view .LVU24
+ 116 001c 014B     		ldr	r3, .L10
+ 117 001e 1870     		strb	r0, [r3]
+ 118 0020 F6E7     		b	.L7
+ 119              	.L11:
+ 120 0022 00BF     		.align	2
+ 121              	.L10:
+ 122 0024 00000000 		.word	.LANCHOR0
+ 123              		.cfi_endproc
+ 124              	.LFE1184:
+ 126              		.section	.text.SD_status,"ax",%progbits
+ 127              		.align	1
+ 128              		.global	SD_status
+ 129              		.syntax unified
+ 130              		.thumb
+ 131              		.thumb_func
+ 132              		.fpu fpv5-d16
+ 134              	SD_status:
+ 135              	.LVL5:
+ 136              	.LFB1185:
+ 124:Src/sd_diskio.c **** 
+ 125:Src/sd_diskio.c **** /**
+ 126:Src/sd_diskio.c ****   * @brief  Gets Disk Status
+ 127:Src/sd_diskio.c ****   * @param  lun : not used
+ 128:Src/sd_diskio.c ****   * @retval DSTATUS: Operation status
+ 129:Src/sd_diskio.c ****   */
+ 130:Src/sd_diskio.c **** DSTATUS SD_status(BYTE lun)
+ 131:Src/sd_diskio.c **** {
+ 137              		.loc 1 131 1 is_stmt 1 view -0
+ 138              		.cfi_startproc
+ 139              		@ args = 0, pretend = 0, frame = 0
+ 140              		@ frame_needed = 0, uses_anonymous_args = 0
+ 141              		.loc 1 131 1 is_stmt 0 view .LVU26
+ 142 0000 08B5     		push	{r3, lr}
+ 143              	.LCFI2:
+ 144              		.cfi_def_cfa_offset 8
+ 145              		.cfi_offset 3, -8
+ 146              		.cfi_offset 14, -4
+ 132:Src/sd_diskio.c ****   return SD_CheckStatus(lun);
+ 147              		.loc 1 132 3 is_stmt 1 view .LVU27
+ 148              		.loc 1 132 10 is_stmt 0 view .LVU28
+ 149 0002 FFF7FEFF 		bl	SD_CheckStatus
+ 150              	.LVL6:
+ 133:Src/sd_diskio.c **** }
+ 151              		.loc 1 133 1 view .LVU29
+ 152 0006 08BD     		pop	{r3, pc}
+ 153              		.cfi_endproc
+ 154              	.LFE1185:
+ARM GAS  /tmp/ccixANLj.s 			page 6
+
+
+ 156              		.section	.text.SD_read,"ax",%progbits
+ 157              		.align	1
+ 158              		.global	SD_read
+ 159              		.syntax unified
+ 160              		.thumb
+ 161              		.thumb_func
+ 162              		.fpu fpv5-d16
+ 164              	SD_read:
+ 165              	.LVL7:
+ 166              	.LFB1186:
+ 134:Src/sd_diskio.c **** 
+ 135:Src/sd_diskio.c **** /* USER CODE BEGIN beforeReadSection */
+ 136:Src/sd_diskio.c **** /* can be used to modify previous code / undefine following code / add new code */
+ 137:Src/sd_diskio.c **** /* USER CODE END beforeReadSection */
+ 138:Src/sd_diskio.c **** /**
+ 139:Src/sd_diskio.c ****   * @brief  Reads Sector(s)
+ 140:Src/sd_diskio.c ****   * @param  lun : not used
+ 141:Src/sd_diskio.c ****   * @param  *buff: Data buffer to store read data
+ 142:Src/sd_diskio.c ****   * @param  sector: Sector address (LBA)
+ 143:Src/sd_diskio.c ****   * @param  count: Number of sectors to read (1..128)
+ 144:Src/sd_diskio.c ****   * @retval DRESULT: Operation result
+ 145:Src/sd_diskio.c ****   */
+ 146:Src/sd_diskio.c **** 
+ 147:Src/sd_diskio.c **** DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
+ 148:Src/sd_diskio.c **** {
+ 167              		.loc 1 148 1 is_stmt 1 view -0
+ 168              		.cfi_startproc
+ 169              		@ args = 0, pretend = 0, frame = 0
+ 170              		@ frame_needed = 0, uses_anonymous_args = 0
+ 171              		.loc 1 148 1 is_stmt 0 view .LVU31
+ 172 0000 08B5     		push	{r3, lr}
+ 173              	.LCFI3:
+ 174              		.cfi_def_cfa_offset 8
+ 175              		.cfi_offset 3, -8
+ 176              		.cfi_offset 14, -4
+ 177 0002 0846     		mov	r0, r1
+ 178              	.LVL8:
+ 179              		.loc 1 148 1 view .LVU32
+ 180 0004 1146     		mov	r1, r2
+ 181              	.LVL9:
+ 182              		.loc 1 148 1 view .LVU33
+ 183 0006 1A46     		mov	r2, r3
+ 184              	.LVL10:
+ 149:Src/sd_diskio.c ****   DRESULT res = RES_ERROR;
+ 185              		.loc 1 149 3 is_stmt 1 view .LVU34
+ 150:Src/sd_diskio.c **** 
+ 151:Src/sd_diskio.c ****   if(BSP_SD_ReadBlocks((uint32_t*)buff,
+ 186              		.loc 1 151 3 view .LVU35
+ 187              		.loc 1 151 6 is_stmt 0 view .LVU36
+ 188 0008 4FF0FF33 		mov	r3, #-1
+ 189              	.LVL11:
+ 190              		.loc 1 151 6 view .LVU37
+ 191 000c FFF7FEFF 		bl	BSP_SD_ReadBlocks
+ 192              	.LVL12:
+ 193              		.loc 1 151 5 view .LVU38
+ 194 0010 30B9     		cbnz	r0, .L17
+ 195              	.L16:
+ARM GAS  /tmp/ccixANLj.s 			page 7
+
+
+ 152:Src/sd_diskio.c ****                        (uint32_t) (sector),
+ 153:Src/sd_diskio.c ****                        count, SD_TIMEOUT) == MSD_OK)
+ 154:Src/sd_diskio.c ****   {
+ 155:Src/sd_diskio.c ****     /* wait until the read operation is finished */
+ 156:Src/sd_diskio.c ****     while(BSP_SD_GetCardState()!= MSD_OK)
+ 157:Src/sd_diskio.c ****     {
+ 158:Src/sd_diskio.c ****     }
+ 196              		.loc 1 158 5 is_stmt 1 discriminator 1 view .LVU39
+ 156:Src/sd_diskio.c ****     {
+ 197              		.loc 1 156 10 discriminator 1 view .LVU40
+ 156:Src/sd_diskio.c ****     {
+ 198              		.loc 1 156 11 is_stmt 0 discriminator 1 view .LVU41
+ 199 0012 FFF7FEFF 		bl	BSP_SD_GetCardState
+ 200              	.LVL13:
+ 156:Src/sd_diskio.c ****     {
+ 201              		.loc 1 156 10 discriminator 1 view .LVU42
+ 202 0016 0346     		mov	r3, r0
+ 203 0018 0028     		cmp	r0, #0
+ 204 001a FAD1     		bne	.L16
+ 205              	.L15:
+ 206              	.LVL14:
+ 159:Src/sd_diskio.c ****     res = RES_OK;
+ 160:Src/sd_diskio.c ****   }
+ 161:Src/sd_diskio.c **** 
+ 162:Src/sd_diskio.c ****   return res;
+ 207              		.loc 1 162 3 is_stmt 1 view .LVU43
+ 163:Src/sd_diskio.c **** }
+ 208              		.loc 1 163 1 is_stmt 0 view .LVU44
+ 209 001c 1846     		mov	r0, r3
+ 210 001e 08BD     		pop	{r3, pc}
+ 211              	.LVL15:
+ 212              	.L17:
+ 149:Src/sd_diskio.c **** 
+ 213              		.loc 1 149 11 view .LVU45
+ 214 0020 0123     		movs	r3, #1
+ 215 0022 FBE7     		b	.L15
+ 216              		.cfi_endproc
+ 217              	.LFE1186:
+ 219              		.section	.text.SD_write,"ax",%progbits
+ 220              		.align	1
+ 221              		.global	SD_write
+ 222              		.syntax unified
+ 223              		.thumb
+ 224              		.thumb_func
+ 225              		.fpu fpv5-d16
+ 227              	SD_write:
+ 228              	.LVL16:
+ 229              	.LFB1187:
+ 164:Src/sd_diskio.c **** 
+ 165:Src/sd_diskio.c **** /* USER CODE BEGIN beforeWriteSection */
+ 166:Src/sd_diskio.c **** /* can be used to modify previous code / undefine following code / add new code */
+ 167:Src/sd_diskio.c **** /* USER CODE END beforeWriteSection */
+ 168:Src/sd_diskio.c **** /**
+ 169:Src/sd_diskio.c ****   * @brief  Writes Sector(s)
+ 170:Src/sd_diskio.c ****   * @param  lun : not used
+ 171:Src/sd_diskio.c ****   * @param  *buff: Data to be written
+ 172:Src/sd_diskio.c ****   * @param  sector: Sector address (LBA)
+ARM GAS  /tmp/ccixANLj.s 			page 8
+
+
+ 173:Src/sd_diskio.c ****   * @param  count: Number of sectors to write (1..128)
+ 174:Src/sd_diskio.c ****   * @retval DRESULT: Operation result
+ 175:Src/sd_diskio.c ****   */
+ 176:Src/sd_diskio.c **** #if _USE_WRITE == 1
+ 177:Src/sd_diskio.c **** 
+ 178:Src/sd_diskio.c **** DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count)
+ 179:Src/sd_diskio.c **** {
+ 230              		.loc 1 179 1 is_stmt 1 view -0
+ 231              		.cfi_startproc
+ 232              		@ args = 0, pretend = 0, frame = 0
+ 233              		@ frame_needed = 0, uses_anonymous_args = 0
+ 234              		.loc 1 179 1 is_stmt 0 view .LVU47
+ 235 0000 08B5     		push	{r3, lr}
+ 236              	.LCFI4:
+ 237              		.cfi_def_cfa_offset 8
+ 238              		.cfi_offset 3, -8
+ 239              		.cfi_offset 14, -4
+ 240 0002 0846     		mov	r0, r1
+ 241              	.LVL17:
+ 242              		.loc 1 179 1 view .LVU48
+ 243 0004 1146     		mov	r1, r2
+ 244              	.LVL18:
+ 245              		.loc 1 179 1 view .LVU49
+ 246 0006 1A46     		mov	r2, r3
+ 247              	.LVL19:
+ 180:Src/sd_diskio.c ****   DRESULT res = RES_ERROR;
+ 248              		.loc 1 180 3 is_stmt 1 view .LVU50
+ 181:Src/sd_diskio.c **** 
+ 182:Src/sd_diskio.c ****   if(BSP_SD_WriteBlocks((uint32_t*)buff,
+ 249              		.loc 1 182 3 view .LVU51
+ 250              		.loc 1 182 6 is_stmt 0 view .LVU52
+ 251 0008 4FF0FF33 		mov	r3, #-1
+ 252              	.LVL20:
+ 253              		.loc 1 182 6 view .LVU53
+ 254 000c FFF7FEFF 		bl	BSP_SD_WriteBlocks
+ 255              	.LVL21:
+ 256              		.loc 1 182 5 view .LVU54
+ 257 0010 30B9     		cbnz	r0, .L22
+ 258              	.L21:
+ 183:Src/sd_diskio.c ****                         (uint32_t)(sector),
+ 184:Src/sd_diskio.c ****                         count, SD_TIMEOUT) == MSD_OK)
+ 185:Src/sd_diskio.c ****   {
+ 186:Src/sd_diskio.c **** 	/* wait until the Write operation is finished */
+ 187:Src/sd_diskio.c ****     while(BSP_SD_GetCardState() != MSD_OK)
+ 188:Src/sd_diskio.c ****     {
+ 189:Src/sd_diskio.c ****     }
+ 259              		.loc 1 189 5 is_stmt 1 discriminator 1 view .LVU55
+ 187:Src/sd_diskio.c ****     {
+ 260              		.loc 1 187 10 discriminator 1 view .LVU56
+ 187:Src/sd_diskio.c ****     {
+ 261              		.loc 1 187 11 is_stmt 0 discriminator 1 view .LVU57
+ 262 0012 FFF7FEFF 		bl	BSP_SD_GetCardState
+ 263              	.LVL22:
+ 187:Src/sd_diskio.c ****     {
+ 264              		.loc 1 187 10 discriminator 1 view .LVU58
+ 265 0016 0346     		mov	r3, r0
+ 266 0018 0028     		cmp	r0, #0
+ARM GAS  /tmp/ccixANLj.s 			page 9
+
+
+ 267 001a FAD1     		bne	.L21
+ 268              	.L20:
+ 269              	.LVL23:
+ 190:Src/sd_diskio.c ****     res = RES_OK;
+ 191:Src/sd_diskio.c ****   }
+ 192:Src/sd_diskio.c **** 
+ 193:Src/sd_diskio.c ****   return res;
+ 270              		.loc 1 193 3 is_stmt 1 view .LVU59
+ 194:Src/sd_diskio.c **** }
+ 271              		.loc 1 194 1 is_stmt 0 view .LVU60
+ 272 001c 1846     		mov	r0, r3
+ 273 001e 08BD     		pop	{r3, pc}
+ 274              	.LVL24:
+ 275              	.L22:
+ 180:Src/sd_diskio.c **** 
+ 276              		.loc 1 180 11 view .LVU61
+ 277 0020 0123     		movs	r3, #1
+ 278 0022 FBE7     		b	.L20
+ 279              		.cfi_endproc
+ 280              	.LFE1187:
+ 282              		.section	.text.SD_ioctl,"ax",%progbits
+ 283              		.align	1
+ 284              		.global	SD_ioctl
+ 285              		.syntax unified
+ 286              		.thumb
+ 287              		.thumb_func
+ 288              		.fpu fpv5-d16
+ 290              	SD_ioctl:
+ 291              	.LVL25:
+ 292              	.LFB1188:
+ 195:Src/sd_diskio.c **** #endif /* _USE_WRITE == 1 */
+ 196:Src/sd_diskio.c **** 
+ 197:Src/sd_diskio.c **** /* USER CODE BEGIN beforeIoctlSection */
+ 198:Src/sd_diskio.c **** /* can be used to modify previous code / undefine following code / add new code */
+ 199:Src/sd_diskio.c **** /* USER CODE END beforeIoctlSection */
+ 200:Src/sd_diskio.c **** /**
+ 201:Src/sd_diskio.c ****   * @brief  I/O control operation
+ 202:Src/sd_diskio.c ****   * @param  lun : not used
+ 203:Src/sd_diskio.c ****   * @param  cmd: Control code
+ 204:Src/sd_diskio.c ****   * @param  *buff: Buffer to send/receive control data
+ 205:Src/sd_diskio.c ****   * @retval DRESULT: Operation result
+ 206:Src/sd_diskio.c ****   */
+ 207:Src/sd_diskio.c **** #if _USE_IOCTL == 1
+ 208:Src/sd_diskio.c **** DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff)
+ 209:Src/sd_diskio.c **** {
+ 293              		.loc 1 209 1 is_stmt 1 view -0
+ 294              		.cfi_startproc
+ 295              		@ args = 0, pretend = 0, frame = 32
+ 296              		@ frame_needed = 0, uses_anonymous_args = 0
+ 297              		.loc 1 209 1 is_stmt 0 view .LVU63
+ 298 0000 30B5     		push	{r4, r5, lr}
+ 299              	.LCFI5:
+ 300              		.cfi_def_cfa_offset 12
+ 301              		.cfi_offset 4, -12
+ 302              		.cfi_offset 5, -8
+ 303              		.cfi_offset 14, -4
+ 304 0002 89B0     		sub	sp, sp, #36
+ARM GAS  /tmp/ccixANLj.s 			page 10
+
+
+ 305              	.LCFI6:
+ 306              		.cfi_def_cfa_offset 48
+ 210:Src/sd_diskio.c ****   DRESULT res = RES_ERROR;
+ 307              		.loc 1 210 3 is_stmt 1 view .LVU64
+ 308              	.LVL26:
+ 211:Src/sd_diskio.c ****   BSP_SD_CardInfo CardInfo;
+ 309              		.loc 1 211 3 view .LVU65
+ 212:Src/sd_diskio.c **** 
+ 213:Src/sd_diskio.c ****   if (Stat & STA_NOINIT) return RES_NOTRDY;
+ 310              		.loc 1 213 3 view .LVU66
+ 311              		.loc 1 213 12 is_stmt 0 view .LVU67
+ 312 0004 134B     		ldr	r3, .L34
+ 313 0006 1878     		ldrb	r0, [r3]	@ zero_extendqisi2
+ 314              	.LVL27:
+ 315              		.loc 1 213 6 view .LVU68
+ 316 0008 10F00104 		ands	r4, r0, #1
+ 317 000c 1BD1     		bne	.L31
+ 318 000e 1546     		mov	r5, r2
+ 214:Src/sd_diskio.c **** 
+ 215:Src/sd_diskio.c ****   switch (cmd)
+ 319              		.loc 1 215 3 is_stmt 1 view .LVU69
+ 320 0010 0329     		cmp	r1, #3
+ 321 0012 1CD8     		bhi	.L32
+ 322 0014 DFE801F0 		tbb	[pc, r1]
+ 323              	.L27:
+ 324 0018 02       		.byte	(.L30-.L27)/2
+ 325 0019 04       		.byte	(.L29-.L27)/2
+ 326 001a 0A       		.byte	(.L28-.L27)/2
+ 327 001b 10       		.byte	(.L26-.L27)/2
+ 328              		.p2align 1
+ 329              	.L30:
+ 330 001c 0C46     		mov	r4, r1
+ 331 001e 13E0     		b	.L25
+ 332              	.L29:
+ 216:Src/sd_diskio.c ****   {
+ 217:Src/sd_diskio.c ****   /* Make sure that no pending write process */
+ 218:Src/sd_diskio.c ****   case CTRL_SYNC :
+ 219:Src/sd_diskio.c ****     res = RES_OK;
+ 220:Src/sd_diskio.c ****     break;
+ 221:Src/sd_diskio.c **** 
+ 222:Src/sd_diskio.c ****   /* Get number of sectors on the disk (DWORD) */
+ 223:Src/sd_diskio.c ****   case GET_SECTOR_COUNT :
+ 224:Src/sd_diskio.c ****     BSP_SD_GetCardInfo(&CardInfo);
+ 333              		.loc 1 224 5 view .LVU70
+ 334 0020 6846     		mov	r0, sp
+ 335 0022 FFF7FEFF 		bl	BSP_SD_GetCardInfo
+ 336              	.LVL28:
+ 225:Src/sd_diskio.c ****     *(DWORD*)buff = CardInfo.LogBlockNbr;
+ 337              		.loc 1 225 5 view .LVU71
+ 338              		.loc 1 225 29 is_stmt 0 view .LVU72
+ 339 0026 069B     		ldr	r3, [sp, #24]
+ 340              		.loc 1 225 19 view .LVU73
+ 341 0028 2B60     		str	r3, [r5]
+ 226:Src/sd_diskio.c ****     res = RES_OK;
+ 342              		.loc 1 226 5 is_stmt 1 view .LVU74
+ 343              	.LVL29:
+ 227:Src/sd_diskio.c ****     break;
+ARM GAS  /tmp/ccixANLj.s 			page 11
+
+
+ 344              		.loc 1 227 5 view .LVU75
+ 345 002a 0DE0     		b	.L25
+ 346              	.LVL30:
+ 347              	.L28:
+ 228:Src/sd_diskio.c **** 
+ 229:Src/sd_diskio.c ****   /* Get R/W sector size (WORD) */
+ 230:Src/sd_diskio.c ****   case GET_SECTOR_SIZE :
+ 231:Src/sd_diskio.c ****     BSP_SD_GetCardInfo(&CardInfo);
+ 348              		.loc 1 231 5 view .LVU76
+ 349 002c 6846     		mov	r0, sp
+ 350 002e FFF7FEFF 		bl	BSP_SD_GetCardInfo
+ 351              	.LVL31:
+ 232:Src/sd_diskio.c ****     *(WORD*)buff = CardInfo.LogBlockSize;
+ 352              		.loc 1 232 5 view .LVU77
+ 353              		.loc 1 232 28 is_stmt 0 view .LVU78
+ 354 0032 079B     		ldr	r3, [sp, #28]
+ 355              		.loc 1 232 18 view .LVU79
+ 356 0034 2B80     		strh	r3, [r5]	@ movhi
+ 233:Src/sd_diskio.c ****     res = RES_OK;
+ 357              		.loc 1 233 5 is_stmt 1 view .LVU80
+ 358              	.LVL32:
+ 234:Src/sd_diskio.c ****     break;
+ 359              		.loc 1 234 5 view .LVU81
+ 360 0036 07E0     		b	.L25
+ 361              	.LVL33:
+ 362              	.L26:
+ 235:Src/sd_diskio.c **** 
+ 236:Src/sd_diskio.c ****   /* Get erase block size in unit of sector (DWORD) */
+ 237:Src/sd_diskio.c ****   case GET_BLOCK_SIZE :
+ 238:Src/sd_diskio.c ****     BSP_SD_GetCardInfo(&CardInfo);
+ 363              		.loc 1 238 5 view .LVU82
+ 364 0038 6846     		mov	r0, sp
+ 365 003a FFF7FEFF 		bl	BSP_SD_GetCardInfo
+ 366              	.LVL34:
+ 239:Src/sd_diskio.c ****     *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE;
+ 367              		.loc 1 239 5 view .LVU83
+ 368              		.loc 1 239 29 is_stmt 0 view .LVU84
+ 369 003e 079B     		ldr	r3, [sp, #28]
+ 370              		.loc 1 239 43 view .LVU85
+ 371 0040 5B0A     		lsrs	r3, r3, #9
+ 372              		.loc 1 239 19 view .LVU86
+ 373 0042 2B60     		str	r3, [r5]
+ 240:Src/sd_diskio.c ****     res = RES_OK;
+ 374              		.loc 1 240 5 is_stmt 1 view .LVU87
+ 375              	.LVL35:
+ 241:Src/sd_diskio.c ****     break;
+ 376              		.loc 1 241 5 view .LVU88
+ 377 0044 00E0     		b	.L25
+ 378              	.LVL36:
+ 379              	.L31:
+ 213:Src/sd_diskio.c **** 
+ 380              		.loc 1 213 33 is_stmt 0 view .LVU89
+ 381 0046 0324     		movs	r4, #3
+ 382              	.LVL37:
+ 383              	.L25:
+ 242:Src/sd_diskio.c **** 
+ 243:Src/sd_diskio.c ****   default:
+ARM GAS  /tmp/ccixANLj.s 			page 12
+
+
+ 244:Src/sd_diskio.c ****     res = RES_PARERR;
+ 245:Src/sd_diskio.c ****   }
+ 246:Src/sd_diskio.c **** 
+ 247:Src/sd_diskio.c ****   return res;
+ 248:Src/sd_diskio.c **** }
+ 384              		.loc 1 248 1 view .LVU90
+ 385 0048 2046     		mov	r0, r4
+ 386 004a 09B0     		add	sp, sp, #36
+ 387              	.LCFI7:
+ 388              		.cfi_remember_state
+ 389              		.cfi_def_cfa_offset 12
+ 390              		@ sp needed
+ 391 004c 30BD     		pop	{r4, r5, pc}
+ 392              	.LVL38:
+ 393              	.L32:
+ 394              	.LCFI8:
+ 395              		.cfi_restore_state
+ 244:Src/sd_diskio.c ****   }
+ 396              		.loc 1 244 9 view .LVU91
+ 397 004e 0424     		movs	r4, #4
+ 398 0050 FAE7     		b	.L25
+ 399              	.L35:
+ 400 0052 00BF     		.align	2
+ 401              	.L34:
+ 402 0054 00000000 		.word	.LANCHOR0
+ 403              		.cfi_endproc
+ 404              	.LFE1188:
+ 406              		.global	SD_Driver
+ 407              		.section	.data.Stat,"aw"
+ 408              		.set	.LANCHOR0,. + 0
+ 411              	Stat:
+ 412 0000 01       		.byte	1
+ 413              		.section	.rodata.SD_Driver,"a"
+ 414              		.align	2
+ 417              	SD_Driver:
+ 418 0000 00000000 		.word	SD_initialize
+ 419 0004 00000000 		.word	SD_status
+ 420 0008 00000000 		.word	SD_read
+ 421 000c 00000000 		.word	SD_write
+ 422 0010 00000000 		.word	SD_ioctl
+ 423              		.text
+ 424              	.Letext0:
+ 425              		.file 2 "Middlewares/Third_Party/FatFs/src/integer.h"
+ 426              		.file 3 "Middlewares/Third_Party/FatFs/src/diskio.h"
+ 427              		.file 4 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 428              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h"
+ 429              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h"
+ 430              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h"
+ 431              		.file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+ 432              		.file 9 "Middlewares/Third_Party/FatFs/src/ff_gen_drv.h"
+ 433              		.file 10 "Inc/bsp_driver_sd.h"
+ 434              		.file 11 "Inc/sd_diskio.h"
+ARM GAS  /tmp/ccixANLj.s 			page 13
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 sd_diskio.c
+     /tmp/ccixANLj.s:17     .text.SD_CheckStatus:0000000000000000 $t
+     /tmp/ccixANLj.s:24     .text.SD_CheckStatus:0000000000000000 SD_CheckStatus
+     /tmp/ccixANLj.s:65     .text.SD_CheckStatus:0000000000000020 $d
+     /tmp/ccixANLj.s:70     .text.SD_initialize:0000000000000000 $t
+     /tmp/ccixANLj.s:77     .text.SD_initialize:0000000000000000 SD_initialize
+     /tmp/ccixANLj.s:122    .text.SD_initialize:0000000000000024 $d
+     /tmp/ccixANLj.s:127    .text.SD_status:0000000000000000 $t
+     /tmp/ccixANLj.s:134    .text.SD_status:0000000000000000 SD_status
+     /tmp/ccixANLj.s:157    .text.SD_read:0000000000000000 $t
+     /tmp/ccixANLj.s:164    .text.SD_read:0000000000000000 SD_read
+     /tmp/ccixANLj.s:220    .text.SD_write:0000000000000000 $t
+     /tmp/ccixANLj.s:227    .text.SD_write:0000000000000000 SD_write
+     /tmp/ccixANLj.s:283    .text.SD_ioctl:0000000000000000 $t
+     /tmp/ccixANLj.s:290    .text.SD_ioctl:0000000000000000 SD_ioctl
+     /tmp/ccixANLj.s:324    .text.SD_ioctl:0000000000000018 $d
+     /tmp/ccixANLj.s:328    .text.SD_ioctl:000000000000001c $t
+     /tmp/ccixANLj.s:402    .text.SD_ioctl:0000000000000054 $d
+     /tmp/ccixANLj.s:417    .rodata.SD_Driver:0000000000000000 SD_Driver
+     /tmp/ccixANLj.s:411    .data.Stat:0000000000000000 Stat
+     /tmp/ccixANLj.s:414    .rodata.SD_Driver:0000000000000000 $d
+
+UNDEFINED SYMBOLS
+BSP_SD_GetCardState
+BSP_SD_Init
+BSP_SD_ReadBlocks
+BSP_SD_WriteBlocks
+BSP_SD_GetCardInfo
diff --git a/build/sd_diskio.o b/build/sd_diskio.o
new file mode 100644
index 0000000..26ca4d2
Binary files /dev/null and b/build/sd_diskio.o differ
diff --git a/build/startup_stm32f767xx.d b/build/startup_stm32f767xx.d
new file mode 100644
index 0000000..0be54eb
--- /dev/null
+++ b/build/startup_stm32f767xx.d
@@ -0,0 +1 @@
+build/startup_stm32f767xx.o: startup_stm32f767xx.s
diff --git a/build/startup_stm32f767xx.o b/build/startup_stm32f767xx.o
new file mode 100644
index 0000000..699122c
Binary files /dev/null and b/build/startup_stm32f767xx.o differ
diff --git a/build/stm32f7xx_hal.d b/build/stm32f7xx_hal.d
new file mode 100644
index 0000000..75bd47e
--- /dev/null
+++ b/build/stm32f7xx_hal.d
@@ -0,0 +1,63 @@
+build/stm32f7xx_hal.o: Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal.lst b/build/stm32f7xx_hal.lst
new file mode 100644
index 0000000..8615bf3
--- /dev/null
+++ b/build/stm32f7xx_hal.lst
@@ -0,0 +1,1844 @@
+ARM GAS  /tmp/cceuBEQV.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.HAL_MspInit,"ax",%progbits
+  17              		.align	1
+  18              		.weak	HAL_MspInit
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	HAL_MspInit:
+  26              	.LFB143:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @file    stm32f7xx_hal.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief   HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *          This is the common part of the HAL initialization
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   ******************************************************************************
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @attention
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * Copyright (c) 2017 STMicroelectronics.
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * All rights reserved.
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * in the root directory of this software component.
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   ******************************************************************************
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   @verbatim
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   ==============================================================================
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****                      ##### How to use this driver #####
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   ==============================================================================
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     [..]
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     The common HAL driver contains a set of generic and common APIs that can be
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     used by the PPP peripheral drivers and the user to start using the HAL. 
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     [..]
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     The HAL contains two APIs' categories: 
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****          (+) Common HAL APIs
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****          (+) Services HAL APIs
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   @endverbatim
+ARM GAS  /tmp/cceuBEQV.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   ******************************************************************************
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */ 
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Includes ------------------------------------------------------------------*/
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #include "stm32f7xx_hal.h"
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @{
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** @defgroup HAL HAL
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief HAL module driver.
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @{
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Private typedef -----------------------------------------------------------*/
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Private define ------------------------------------------------------------*/
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** @addtogroup HAL_Private_Constants
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @{
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****  * @brief STM32F7xx HAL Driver version number V1.3.1
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****    */
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #define __STM32F7xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #define __STM32F7xx_HAL_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #define __STM32F7xx_HAL_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #define __STM32F7xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #define __STM32F7xx_HAL_VERSION         ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****                                         |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****                                         |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****                                         |(__STM32F7xx_HAL_VERSION_RC))
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****                                         
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @}
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Private macro -------------------------------------------------------------*/
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Exported variables ---------------------------------------------------------*/
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** @addtogroup HAL_Exported_Variables
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @{
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __IO uint32_t uwTick;
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @}
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Private function prototypes -----------------------------------------------*/
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Private functions ---------------------------------------------------------*/
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** @defgroup HAL_Exported_Functions HAL Exported Functions
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @{
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions 
+ARM GAS  /tmp/cceuBEQV.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****  *  @brief    Initialization and de-initialization functions
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****  *
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** @verbatim    
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****  ===============================================================================
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****               ##### Initialization and Configuration functions #####
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****  ===============================================================================
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     [..]  This section provides functions allowing to:
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Initializes the Flash interface the NVIC allocation and initial clock 
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****           configuration. It initializes the systick also when timeout is needed 
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****           and the backup domain when enabled.
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) De-Initializes common part of the HAL.
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Configure the time base source to have 1ms time base with a dedicated 
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****           Tick interrupt priority. 
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****         (++) SysTick timer is used by default as source of time base, but user
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****              can eventually implement his proper time base source (a general purpose 
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****              timer for example or other time source), keeping in mind that Time base 
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****              handled in milliseconds basis.
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****         (++) Time base configuration function (HAL_InitTick ()) is called automatically 
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****              at the beginning of the program after reset by HAL_Init() or at any time 
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****              when clock is configured, by HAL_RCC_ClockConfig(). 
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****         (++) Source of time base is configured  to generate interrupts at regular 
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****              time intervals. Care must be taken if HAL_Delay() is called from a 
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****              peripheral ISR process, the Tick interrupt line must have higher priority 
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****             (numerically lower) than the peripheral interrupt. Otherwise the caller 
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****             ISR process will be blocked. 
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****        (++) functions affecting time base configurations are declared as __weak  
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****              to make  override possible  in case of other  implementations in user file.
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** @endverbatim
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @{
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  This function is used to initialize the HAL Library; it must be the first 
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *         instruction to be executed in the main program (before to call any other
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *         HAL function), it performs the following:
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *           Configure the Flash prefetch, and instruction cache through ART accelerator.
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *           Configures the SysTick to generate an interrupt each 1 millisecond,
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *           which is clocked by the HSI (at this stage, the clock is not yet
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *           configured and thus the system is running from the internal HSI at 16 MHz).
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *           Set NVIC Group Priority to 4.
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *           Calls the HAL_MspInit() callback function defined in user file 
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *           "stm32f7xx_hal_msp.c" to do the global low level hardware initialization 
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *            
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note   SysTick is used as time base for the HAL_Delay() function, the application
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *         need to ensure that the SysTick time base is always set to 1 millisecond
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *         to have correct HAL operation.
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval HAL status
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** HAL_StatusTypeDef HAL_Init(void)
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Configure Instruction cache through ART accelerator */ 
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #if (ART_ACCELERATOR_ENABLE != 0)
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_FLASH_ART_ENABLE();
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #endif /* ART_ACCELERATOR_ENABLE */
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Configure Flash prefetch */
+ARM GAS  /tmp/cceuBEQV.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #if (PREFETCH_ENABLE != 0U)
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #endif /* PREFETCH_ENABLE */
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Set Interrupt Group Priority */
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   HAL_InitTick(TICK_INT_PRIORITY);
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Init the low level hardware */
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   HAL_MspInit();
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Return function status */
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   return HAL_OK;
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  This function de-Initializes common part of the HAL and stops the systick.
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *         This function is optional.   
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval HAL status
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** HAL_StatusTypeDef HAL_DeInit(void)
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Reset of all peripherals */
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_APB1_FORCE_RESET();
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_APB1_RELEASE_RESET();
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_APB2_FORCE_RESET();
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_APB2_RELEASE_RESET();
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_AHB1_FORCE_RESET();
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_AHB1_RELEASE_RESET();
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_AHB2_FORCE_RESET();
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_AHB2_RELEASE_RESET();
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_AHB3_FORCE_RESET();
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_AHB3_RELEASE_RESET();
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* De-Init the low level hardware */
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   HAL_MspDeInit();
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Return function status */
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   return HAL_OK;
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Initialize the MSP.
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak void HAL_MspInit(void)
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+  28              		.loc 1 198 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cceuBEQV.s 			page 5
+
+
+  32              		@ link register save eliminated.
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****             the HAL_MspInit could be implemented in the user file
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****    */
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+  33              		.loc 1 202 1 view .LVU1
+  34 0000 7047     		bx	lr
+  35              		.cfi_endproc
+  36              	.LFE143:
+  38              		.section	.text.HAL_MspDeInit,"ax",%progbits
+  39              		.align	1
+  40              		.weak	HAL_MspDeInit
+  41              		.syntax unified
+  42              		.thumb
+  43              		.thumb_func
+  44              		.fpu fpv5-d16
+  46              	HAL_MspDeInit:
+  47              	.LFB144:
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  DeInitializes the MSP.
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak void HAL_MspDeInit(void)
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+  48              		.loc 1 209 1 view -0
+  49              		.cfi_startproc
+  50              		@ args = 0, pretend = 0, frame = 0
+  51              		@ frame_needed = 0, uses_anonymous_args = 0
+  52              		@ link register save eliminated.
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****             the HAL_MspDeInit could be implemented in the user file
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****    */ 
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+  53              		.loc 1 213 1 view .LVU3
+  54 0000 7047     		bx	lr
+  55              		.cfi_endproc
+  56              	.LFE144:
+  58              		.section	.text.HAL_DeInit,"ax",%progbits
+  59              		.align	1
+  60              		.global	HAL_DeInit
+  61              		.syntax unified
+  62              		.thumb
+  63              		.thumb_func
+  64              		.fpu fpv5-d16
+  66              	HAL_DeInit:
+  67              	.LFB142:
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Reset of all peripherals */
+  68              		.loc 1 169 1 view -0
+  69              		.cfi_startproc
+  70              		@ args = 0, pretend = 0, frame = 0
+  71              		@ frame_needed = 0, uses_anonymous_args = 0
+  72 0000 10B5     		push	{r4, lr}
+  73              	.LCFI0:
+  74              		.cfi_def_cfa_offset 8
+  75              		.cfi_offset 4, -8
+  76              		.cfi_offset 14, -4
+ARM GAS  /tmp/cceuBEQV.s 			page 6
+
+
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_APB1_RELEASE_RESET();
+  77              		.loc 1 171 3 view .LVU5
+  78 0002 094B     		ldr	r3, .L5
+  79 0004 4FF0FF32 		mov	r2, #-1
+  80 0008 1A62     		str	r2, [r3, #32]
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  81              		.loc 1 172 3 view .LVU6
+  82 000a 0024     		movs	r4, #0
+  83 000c 1C62     		str	r4, [r3, #32]
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_APB2_RELEASE_RESET();
+  84              		.loc 1 174 3 view .LVU7
+  85 000e 5A62     		str	r2, [r3, #36]
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  86              		.loc 1 175 3 view .LVU8
+  87 0010 5C62     		str	r4, [r3, #36]
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_AHB1_RELEASE_RESET();
+  88              		.loc 1 177 3 view .LVU9
+  89 0012 1A61     		str	r2, [r3, #16]
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  90              		.loc 1 178 3 view .LVU10
+  91 0014 1C61     		str	r4, [r3, #16]
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_AHB2_RELEASE_RESET();
+  92              		.loc 1 180 3 view .LVU11
+  93 0016 5A61     		str	r2, [r3, #20]
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  94              		.loc 1 181 3 view .LVU12
+  95 0018 5C61     		str	r4, [r3, #20]
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   __HAL_RCC_AHB3_RELEASE_RESET();
+  96              		.loc 1 183 3 view .LVU13
+  97 001a 9A61     		str	r2, [r3, #24]
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+  98              		.loc 1 184 3 view .LVU14
+  99 001c 9C61     		str	r4, [r3, #24]
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 100              		.loc 1 187 3 view .LVU15
+ 101 001e FFF7FEFF 		bl	HAL_MspDeInit
+ 102              	.LVL0:
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 103              		.loc 1 190 3 view .LVU16
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 104              		.loc 1 191 1 is_stmt 0 view .LVU17
+ 105 0022 2046     		mov	r0, r4
+ 106 0024 10BD     		pop	{r4, pc}
+ 107              	.L6:
+ 108 0026 00BF     		.align	2
+ 109              	.L5:
+ 110 0028 00380240 		.word	1073887232
+ 111              		.cfi_endproc
+ 112              	.LFE142:
+ 114              		.section	.text.HAL_InitTick,"ax",%progbits
+ 115              		.align	1
+ 116              		.weak	HAL_InitTick
+ 117              		.syntax unified
+ 118              		.thumb
+ 119              		.thumb_func
+ 120              		.fpu fpv5-d16
+ 122              	HAL_InitTick:
+ARM GAS  /tmp/cceuBEQV.s 			page 7
+
+
+ 123              	.LVL1:
+ 124              	.LFB145:
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief This function configures the source of the time base.
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *        The time source is configured  to have 1ms time base with a dedicated 
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *        Tick interrupt priority.
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note This function is called  automatically at the beginning of program after
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note In the default implementation, SysTick timer is the source of time base. 
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       It is used to generate interrupts at regular time intervals. 
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, 
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       The SysTick interrupt must have higher priority (numerically lower)
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       The function is declared as __weak  to be overwritten  in case of other
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       implementation  in user file.
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @param TickPriority Tick interrupt priority.
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval HAL status
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 125              		.loc 1 232 1 is_stmt 1 view -0
+ 126              		.cfi_startproc
+ 127              		@ args = 0, pretend = 0, frame = 0
+ 128              		@ frame_needed = 0, uses_anonymous_args = 0
+ 129              		.loc 1 232 1 is_stmt 0 view .LVU19
+ 130 0000 10B5     		push	{r4, lr}
+ 131              	.LCFI1:
+ 132              		.cfi_def_cfa_offset 8
+ 133              		.cfi_offset 4, -8
+ 134              		.cfi_offset 14, -4
+ 135 0002 0446     		mov	r4, r0
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Configure the SysTick to have interrupt in 1ms time basis*/
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ 136              		.loc 1 234 3 is_stmt 1 view .LVU20
+ 137              		.loc 1 234 51 is_stmt 0 view .LVU21
+ 138 0004 0E4B     		ldr	r3, .L13
+ 139 0006 1878     		ldrb	r0, [r3]	@ zero_extendqisi2
+ 140              	.LVL2:
+ 141              		.loc 1 234 51 view .LVU22
+ 142 0008 4FF47A73 		mov	r3, #1000
+ 143 000c B3FBF0F3 		udiv	r3, r3, r0
+ 144              		.loc 1 234 7 view .LVU23
+ 145 0010 0C4A     		ldr	r2, .L13+4
+ 146 0012 1068     		ldr	r0, [r2]
+ 147 0014 B0FBF3F0 		udiv	r0, r0, r3
+ 148 0018 FFF7FEFF 		bl	HAL_SYSTICK_Config
+ 149              	.LVL3:
+ 150              		.loc 1 234 6 view .LVU24
+ 151 001c 68B9     		cbnz	r0, .L9
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   {
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     return HAL_ERROR;
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   }
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Configure the SysTick IRQ priority */
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 152              		.loc 1 240 3 is_stmt 1 view .LVU25
+ARM GAS  /tmp/cceuBEQV.s 			page 8
+
+
+ 153              		.loc 1 240 6 is_stmt 0 view .LVU26
+ 154 001e 0F2C     		cmp	r4, #15
+ 155 0020 01D9     		bls	.L12
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   {
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     uwTickPrio = TickPriority;
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   }
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   else
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   {
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     return HAL_ERROR;
+ 156              		.loc 1 247 12 view .LVU27
+ 157 0022 0120     		movs	r0, #1
+ 158 0024 0AE0     		b	.L8
+ 159              	.L12:
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     uwTickPrio = TickPriority;
+ 160              		.loc 1 242 5 is_stmt 1 view .LVU28
+ 161 0026 0022     		movs	r2, #0
+ 162 0028 2146     		mov	r1, r4
+ 163 002a 4FF0FF30 		mov	r0, #-1
+ 164 002e FFF7FEFF 		bl	HAL_NVIC_SetPriority
+ 165              	.LVL4:
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   }
+ 166              		.loc 1 243 5 view .LVU29
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   }
+ 167              		.loc 1 243 16 is_stmt 0 view .LVU30
+ 168 0032 054B     		ldr	r3, .L13+8
+ 169 0034 1C60     		str	r4, [r3]
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   }
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Return function status */
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   return HAL_OK;
+ 170              		.loc 1 251 3 is_stmt 1 view .LVU31
+ 171              		.loc 1 251 10 is_stmt 0 view .LVU32
+ 172 0036 0020     		movs	r0, #0
+ 173 0038 00E0     		b	.L8
+ 174              	.L9:
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   }
+ 175              		.loc 1 236 12 view .LVU33
+ 176 003a 0120     		movs	r0, #1
+ 177              	.L8:
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 178              		.loc 1 252 1 view .LVU34
+ 179 003c 10BD     		pop	{r4, pc}
+ 180              	.LVL5:
+ 181              	.L14:
+ 182              		.loc 1 252 1 view .LVU35
+ 183 003e 00BF     		.align	2
+ 184              	.L13:
+ 185 0040 00000000 		.word	.LANCHOR0
+ 186 0044 00000000 		.word	SystemCoreClock
+ 187 0048 00000000 		.word	.LANCHOR1
+ 188              		.cfi_endproc
+ 189              	.LFE145:
+ 191              		.section	.text.HAL_Init,"ax",%progbits
+ 192              		.align	1
+ 193              		.global	HAL_Init
+ 194              		.syntax unified
+ARM GAS  /tmp/cceuBEQV.s 			page 9
+
+
+ 195              		.thumb
+ 196              		.thumb_func
+ 197              		.fpu fpv5-d16
+ 199              	HAL_Init:
+ 200              	.LFB141:
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Configure Instruction cache through ART accelerator */ 
+ 201              		.loc 1 139 1 is_stmt 1 view -0
+ 202              		.cfi_startproc
+ 203              		@ args = 0, pretend = 0, frame = 0
+ 204              		@ frame_needed = 0, uses_anonymous_args = 0
+ 205 0000 08B5     		push	{r3, lr}
+ 206              	.LCFI2:
+ 207              		.cfi_def_cfa_offset 8
+ 208              		.cfi_offset 3, -8
+ 209              		.cfi_offset 14, -4
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 210              		.loc 1 151 3 view .LVU37
+ 211 0002 0320     		movs	r0, #3
+ 212 0004 FFF7FEFF 		bl	HAL_NVIC_SetPriorityGrouping
+ 213              	.LVL6:
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 214              		.loc 1 154 3 view .LVU38
+ 215 0008 0020     		movs	r0, #0
+ 216 000a FFF7FEFF 		bl	HAL_InitTick
+ 217              	.LVL7:
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 218              		.loc 1 157 3 view .LVU39
+ 219 000e FFF7FEFF 		bl	HAL_MspInit
+ 220              	.LVL8:
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 221              		.loc 1 160 3 view .LVU40
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 222              		.loc 1 161 1 is_stmt 0 view .LVU41
+ 223 0012 0020     		movs	r0, #0
+ 224 0014 08BD     		pop	{r3, pc}
+ 225              		.cfi_endproc
+ 226              	.LFE141:
+ 228              		.section	.text.HAL_IncTick,"ax",%progbits
+ 229              		.align	1
+ 230              		.weak	HAL_IncTick
+ 231              		.syntax unified
+ 232              		.thumb
+ 233              		.thumb_func
+ 234              		.fpu fpv5-d16
+ 236              	HAL_IncTick:
+ 237              	.LFB146:
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @}
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****  *  @brief    HAL Control functions
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****  *
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** @verbatim
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****  ===============================================================================
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****                       ##### HAL Control functions #####
+ARM GAS  /tmp/cceuBEQV.s 			page 10
+
+
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****  ===============================================================================
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     [..]  This section provides functions allowing to:
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Provide a tick value in millisecond
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Provide a blocking delay in millisecond
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Suspend the time base source interrupt
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Resume the time base source interrupt
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Get the HAL API driver version
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Get the device identifier
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Get the device revision identifier
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Enable/Disable Debug module during SLEEP mode
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Enable/Disable Debug module during STOP mode
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       (+) Enable/Disable Debug module during STANDBY mode
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** @endverbatim
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @{
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief This function is called to increment  a global variable "uwTick"
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *        used as application time base.
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note In the default implementation, this variable is incremented each 1ms
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       in SysTick ISR.
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****  * @note This function is declared as __weak to be overwritten in case of other 
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *      implementations in user file.
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak void HAL_IncTick(void)
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 238              		.loc 1 291 1 is_stmt 1 view -0
+ 239              		.cfi_startproc
+ 240              		@ args = 0, pretend = 0, frame = 0
+ 241              		@ frame_needed = 0, uses_anonymous_args = 0
+ 242              		@ link register save eliminated.
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   uwTick += uwTickFreq;
+ 243              		.loc 1 292 3 view .LVU43
+ 244              		.loc 1 292 10 is_stmt 0 view .LVU44
+ 245 0000 034A     		ldr	r2, .L18
+ 246 0002 1168     		ldr	r1, [r2]
+ 247 0004 034B     		ldr	r3, .L18+4
+ 248 0006 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 249 0008 0B44     		add	r3, r3, r1
+ 250 000a 1360     		str	r3, [r2]
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 251              		.loc 1 293 1 view .LVU45
+ 252 000c 7047     		bx	lr
+ 253              	.L19:
+ 254 000e 00BF     		.align	2
+ 255              	.L18:
+ 256 0010 00000000 		.word	.LANCHOR2
+ 257 0014 00000000 		.word	.LANCHOR0
+ 258              		.cfi_endproc
+ 259              	.LFE146:
+ 261              		.section	.text.HAL_GetTick,"ax",%progbits
+ 262              		.align	1
+ 263              		.weak	HAL_GetTick
+ 264              		.syntax unified
+ 265              		.thumb
+ARM GAS  /tmp/cceuBEQV.s 			page 11
+
+
+ 266              		.thumb_func
+ 267              		.fpu fpv5-d16
+ 269              	HAL_GetTick:
+ 270              	.LFB147:
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief Provides a tick value in millisecond.
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note This function is declared as __weak to be overwritten in case of other 
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       implementations in user file.
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval tick value
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak uint32_t HAL_GetTick(void)
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 271              		.loc 1 302 1 is_stmt 1 view -0
+ 272              		.cfi_startproc
+ 273              		@ args = 0, pretend = 0, frame = 0
+ 274              		@ frame_needed = 0, uses_anonymous_args = 0
+ 275              		@ link register save eliminated.
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   return uwTick;
+ 276              		.loc 1 303 3 view .LVU47
+ 277              		.loc 1 303 10 is_stmt 0 view .LVU48
+ 278 0000 014B     		ldr	r3, .L21
+ 279 0002 1868     		ldr	r0, [r3]
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 280              		.loc 1 304 1 view .LVU49
+ 281 0004 7047     		bx	lr
+ 282              	.L22:
+ 283 0006 00BF     		.align	2
+ 284              	.L21:
+ 285 0008 00000000 		.word	.LANCHOR2
+ 286              		.cfi_endproc
+ 287              	.LFE147:
+ 289              		.section	.text.HAL_GetTickPrio,"ax",%progbits
+ 290              		.align	1
+ 291              		.global	HAL_GetTickPrio
+ 292              		.syntax unified
+ 293              		.thumb
+ 294              		.thumb_func
+ 295              		.fpu fpv5-d16
+ 297              	HAL_GetTickPrio:
+ 298              	.LFB148:
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief This function returns a tick priority.
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval tick priority
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetTickPrio(void)
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 299              		.loc 1 311 1 is_stmt 1 view -0
+ 300              		.cfi_startproc
+ 301              		@ args = 0, pretend = 0, frame = 0
+ 302              		@ frame_needed = 0, uses_anonymous_args = 0
+ 303              		@ link register save eliminated.
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   return uwTickPrio;
+ 304              		.loc 1 312 3 view .LVU51
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 305              		.loc 1 313 1 is_stmt 0 view .LVU52
+ARM GAS  /tmp/cceuBEQV.s 			page 12
+
+
+ 306 0000 014B     		ldr	r3, .L24
+ 307 0002 1868     		ldr	r0, [r3]
+ 308 0004 7047     		bx	lr
+ 309              	.L25:
+ 310 0006 00BF     		.align	2
+ 311              	.L24:
+ 312 0008 00000000 		.word	.LANCHOR1
+ 313              		.cfi_endproc
+ 314              	.LFE148:
+ 316              		.section	.text.HAL_SetTickFreq,"ax",%progbits
+ 317              		.align	1
+ 318              		.global	HAL_SetTickFreq
+ 319              		.syntax unified
+ 320              		.thumb
+ 321              		.thumb_func
+ 322              		.fpu fpv5-d16
+ 324              	HAL_SetTickFreq:
+ 325              	.LVL9:
+ 326              	.LFB149:
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief Set new tick Freq.
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval Status
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 327              		.loc 1 320 1 is_stmt 1 view -0
+ 328              		.cfi_startproc
+ 329              		@ args = 0, pretend = 0, frame = 0
+ 330              		@ frame_needed = 0, uses_anonymous_args = 0
+ 331              		.loc 1 320 1 is_stmt 0 view .LVU54
+ 332 0000 10B5     		push	{r4, lr}
+ 333              	.LCFI3:
+ 334              		.cfi_def_cfa_offset 8
+ 335              		.cfi_offset 4, -8
+ 336              		.cfi_offset 14, -4
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   HAL_StatusTypeDef status  = HAL_OK;
+ 337              		.loc 1 321 3 is_stmt 1 view .LVU55
+ 338              	.LVL10:
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   HAL_TickFreqTypeDef prevTickFreq;
+ 339              		.loc 1 322 3 view .LVU56
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   assert_param(IS_TICKFREQ(Freq));
+ 340              		.loc 1 324 3 view .LVU57
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   if (uwTickFreq != Freq)
+ 341              		.loc 1 326 3 view .LVU58
+ 342              		.loc 1 326 18 is_stmt 0 view .LVU59
+ 343 0002 084B     		ldr	r3, .L31
+ 344 0004 1C78     		ldrb	r4, [r3]	@ zero_extendqisi2
+ 345              		.loc 1 326 6 view .LVU60
+ 346 0006 8442     		cmp	r4, r0
+ 347 0008 01D1     		bne	.L30
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   HAL_TickFreqTypeDef prevTickFreq;
+ 348              		.loc 1 321 21 view .LVU61
+ 349 000a 0020     		movs	r0, #0
+ 350              	.LVL11:
+ARM GAS  /tmp/cceuBEQV.s 			page 13
+
+
+ 351              	.L27:
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   {
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     /* Back up uwTickFreq frequency */
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     prevTickFreq = uwTickFreq;
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     /* Update uwTickFreq global variable used by HAL_InitTick() */
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     uwTickFreq = Freq;
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     /* Apply the new tick Freq  */
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     status = HAL_InitTick(uwTickPrio);
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     if (status != HAL_OK)
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     {
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       /* Restore previous tick frequency */
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****       uwTickFreq = prevTickFreq;
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     }
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   }
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   return status;
+ 352              		.loc 1 344 3 is_stmt 1 view .LVU62
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 353              		.loc 1 345 1 is_stmt 0 view .LVU63
+ 354 000c 10BD     		pop	{r4, pc}
+ 355              	.LVL12:
+ 356              	.L30:
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 357              		.loc 1 329 5 is_stmt 1 view .LVU64
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 358              		.loc 1 332 5 view .LVU65
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 359              		.loc 1 332 16 is_stmt 0 view .LVU66
+ 360 000e 1870     		strb	r0, [r3]
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 361              		.loc 1 335 5 is_stmt 1 view .LVU67
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 362              		.loc 1 335 14 is_stmt 0 view .LVU68
+ 363 0010 054B     		ldr	r3, .L31+4
+ 364 0012 1868     		ldr	r0, [r3]
+ 365              	.LVL13:
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 366              		.loc 1 335 14 view .LVU69
+ 367 0014 FFF7FEFF 		bl	HAL_InitTick
+ 368              	.LVL14:
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     {
+ 369              		.loc 1 337 5 is_stmt 1 view .LVU70
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     {
+ 370              		.loc 1 337 8 is_stmt 0 view .LVU71
+ 371 0018 0028     		cmp	r0, #0
+ 372 001a F7D0     		beq	.L27
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     }
+ 373              		.loc 1 340 7 is_stmt 1 view .LVU72
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     }
+ 374              		.loc 1 340 18 is_stmt 0 view .LVU73
+ 375 001c 014B     		ldr	r3, .L31
+ 376 001e 1C70     		strb	r4, [r3]
+ 377 0020 F4E7     		b	.L27
+ 378              	.L32:
+ARM GAS  /tmp/cceuBEQV.s 			page 14
+
+
+ 379 0022 00BF     		.align	2
+ 380              	.L31:
+ 381 0024 00000000 		.word	.LANCHOR0
+ 382 0028 00000000 		.word	.LANCHOR1
+ 383              		.cfi_endproc
+ 384              	.LFE149:
+ 386              		.section	.text.HAL_GetTickFreq,"ax",%progbits
+ 387              		.align	1
+ 388              		.global	HAL_GetTickFreq
+ 389              		.syntax unified
+ 390              		.thumb
+ 391              		.thumb_func
+ 392              		.fpu fpv5-d16
+ 394              	HAL_GetTickFreq:
+ 395              	.LFB150:
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief Return tick frequency.
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval Tick frequency.
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *         Value of @ref HAL_TickFreqTypeDef.
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 396              		.loc 1 353 1 is_stmt 1 view -0
+ 397              		.cfi_startproc
+ 398              		@ args = 0, pretend = 0, frame = 0
+ 399              		@ frame_needed = 0, uses_anonymous_args = 0
+ 400              		@ link register save eliminated.
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   return uwTickFreq;
+ 401              		.loc 1 354 3 view .LVU75
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 402              		.loc 1 355 1 is_stmt 0 view .LVU76
+ 403 0000 014B     		ldr	r3, .L34
+ 404 0002 1878     		ldrb	r0, [r3]	@ zero_extendqisi2
+ 405 0004 7047     		bx	lr
+ 406              	.L35:
+ 407 0006 00BF     		.align	2
+ 408              	.L34:
+ 409 0008 00000000 		.word	.LANCHOR0
+ 410              		.cfi_endproc
+ 411              	.LFE150:
+ 413              		.section	.text.HAL_Delay,"ax",%progbits
+ 414              		.align	1
+ 415              		.weak	HAL_Delay
+ 416              		.syntax unified
+ 417              		.thumb
+ 418              		.thumb_func
+ 419              		.fpu fpv5-d16
+ 421              	HAL_Delay:
+ 422              	.LVL15:
+ 423              	.LFB151:
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief This function provides minimum delay (in milliseconds) based
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *        on variable incremented.
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note In the default implementation , SysTick timer is the source of time base.
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       It is used to generate interrupts at regular time intervals where uwTick
+ARM GAS  /tmp/cceuBEQV.s 			page 15
+
+
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       is incremented.
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note This function is declared as __weak to be overwritten in case of other
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       implementations in user file.
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @param Delay  specifies the delay time length, in milliseconds.
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak void HAL_Delay(uint32_t Delay)
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 424              		.loc 1 369 1 is_stmt 1 view -0
+ 425              		.cfi_startproc
+ 426              		@ args = 0, pretend = 0, frame = 0
+ 427              		@ frame_needed = 0, uses_anonymous_args = 0
+ 428              		.loc 1 369 1 is_stmt 0 view .LVU78
+ 429 0000 38B5     		push	{r3, r4, r5, lr}
+ 430              	.LCFI4:
+ 431              		.cfi_def_cfa_offset 16
+ 432              		.cfi_offset 3, -16
+ 433              		.cfi_offset 4, -12
+ 434              		.cfi_offset 5, -8
+ 435              		.cfi_offset 14, -4
+ 436 0002 0446     		mov	r4, r0
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   uint32_t tickstart = HAL_GetTick();
+ 437              		.loc 1 370 3 is_stmt 1 view .LVU79
+ 438              		.loc 1 370 24 is_stmt 0 view .LVU80
+ 439 0004 FFF7FEFF 		bl	HAL_GetTick
+ 440              	.LVL16:
+ 441              		.loc 1 370 24 view .LVU81
+ 442 0008 0546     		mov	r5, r0
+ 443              	.LVL17:
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   uint32_t wait = Delay;
+ 444              		.loc 1 371 3 is_stmt 1 view .LVU82
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Add a freq to guarantee minimum wait */
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   if (wait < HAL_MAX_DELAY)
+ 445              		.loc 1 374 3 view .LVU83
+ 446              		.loc 1 374 6 is_stmt 0 view .LVU84
+ 447 000a B4F1FF3F 		cmp	r4, #-1
+ 448 000e 02D0     		beq	.L38
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   {
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****     wait += (uint32_t)(uwTickFreq);
+ 449              		.loc 1 376 5 is_stmt 1 view .LVU85
+ 450              		.loc 1 376 13 is_stmt 0 view .LVU86
+ 451 0010 044B     		ldr	r3, .L40
+ 452 0012 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 453              		.loc 1 376 10 view .LVU87
+ 454 0014 1C44     		add	r4, r4, r3
+ 455              	.LVL18:
+ 456              	.L38:
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   }
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   while ((HAL_GetTick() - tickstart) < wait)
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   {
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   }
+ 457              		.loc 1 381 3 is_stmt 1 discriminator 1 view .LVU88
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   {
+ 458              		.loc 1 379 9 discriminator 1 view .LVU89
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   {
+ARM GAS  /tmp/cceuBEQV.s 			page 16
+
+
+ 459              		.loc 1 379 11 is_stmt 0 discriminator 1 view .LVU90
+ 460 0016 FFF7FEFF 		bl	HAL_GetTick
+ 461              	.LVL19:
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   {
+ 462              		.loc 1 379 25 discriminator 1 view .LVU91
+ 463 001a 401B     		subs	r0, r0, r5
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   {
+ 464              		.loc 1 379 9 discriminator 1 view .LVU92
+ 465 001c A042     		cmp	r0, r4
+ 466 001e FAD3     		bcc	.L38
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 467              		.loc 1 382 1 view .LVU93
+ 468 0020 38BD     		pop	{r3, r4, r5, pc}
+ 469              	.LVL20:
+ 470              	.L41:
+ 471              		.loc 1 382 1 view .LVU94
+ 472 0022 00BF     		.align	2
+ 473              	.L40:
+ 474 0024 00000000 		.word	.LANCHOR0
+ 475              		.cfi_endproc
+ 476              	.LFE151:
+ 478              		.section	.text.HAL_SuspendTick,"ax",%progbits
+ 479              		.align	1
+ 480              		.weak	HAL_SuspendTick
+ 481              		.syntax unified
+ 482              		.thumb
+ 483              		.thumb_func
+ 484              		.fpu fpv5-d16
+ 486              	HAL_SuspendTick:
+ 487              	.LFB152:
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief Suspend Tick increment.
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note In the default implementation , SysTick timer is the source of time base. It is
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       is called, the SysTick interrupt will be disabled and so Tick increment 
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       is suspended.
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note This function is declared as __weak to be overwritten in case of other
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       implementations in user file.
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak void HAL_SuspendTick(void)
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 488              		.loc 1 395 1 is_stmt 1 view -0
+ 489              		.cfi_startproc
+ 490              		@ args = 0, pretend = 0, frame = 0
+ 491              		@ frame_needed = 0, uses_anonymous_args = 0
+ 492              		@ link register save eliminated.
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Disable SysTick Interrupt */
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+ 493              		.loc 1 397 3 view .LVU96
+ 494              		.loc 1 397 17 is_stmt 0 view .LVU97
+ 495 0000 4FF0E022 		mov	r2, #-536813568
+ 496 0004 1369     		ldr	r3, [r2, #16]
+ 497 0006 23F00203 		bic	r3, r3, #2
+ 498 000a 1361     		str	r3, [r2, #16]
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ARM GAS  /tmp/cceuBEQV.s 			page 17
+
+
+ 499              		.loc 1 398 1 view .LVU98
+ 500 000c 7047     		bx	lr
+ 501              		.cfi_endproc
+ 502              	.LFE152:
+ 504              		.section	.text.HAL_ResumeTick,"ax",%progbits
+ 505              		.align	1
+ 506              		.weak	HAL_ResumeTick
+ 507              		.syntax unified
+ 508              		.thumb
+ 509              		.thumb_func
+ 510              		.fpu fpv5-d16
+ 512              	HAL_ResumeTick:
+ 513              	.LFB153:
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief Resume Tick increment.
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note In the default implementation , SysTick timer is the source of time base. It is
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       is called, the SysTick interrupt will be enabled and so Tick increment 
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       is resumed.
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note This function is declared as __weak to be overwritten in case of other
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *       implementations in user file.
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak void HAL_ResumeTick(void)
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 514              		.loc 1 411 1 is_stmt 1 view -0
+ 515              		.cfi_startproc
+ 516              		@ args = 0, pretend = 0, frame = 0
+ 517              		@ frame_needed = 0, uses_anonymous_args = 0
+ 518              		@ link register save eliminated.
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   /* Enable SysTick Interrupt */
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+ 519              		.loc 1 413 3 view .LVU100
+ 520              		.loc 1 413 18 is_stmt 0 view .LVU101
+ 521 0000 4FF0E022 		mov	r2, #-536813568
+ 522 0004 1369     		ldr	r3, [r2, #16]
+ 523 0006 43F00203 		orr	r3, r3, #2
+ 524 000a 1361     		str	r3, [r2, #16]
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 525              		.loc 1 414 1 view .LVU102
+ 526 000c 7047     		bx	lr
+ 527              		.cfi_endproc
+ 528              	.LFE153:
+ 530              		.section	.text.HAL_GetHalVersion,"ax",%progbits
+ 531              		.align	1
+ 532              		.global	HAL_GetHalVersion
+ 533              		.syntax unified
+ 534              		.thumb
+ 535              		.thumb_func
+ 536              		.fpu fpv5-d16
+ 538              	HAL_GetHalVersion:
+ 539              	.LFB154:
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Returns the HAL revision
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+ARM GAS  /tmp/cceuBEQV.s 			page 18
+
+
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetHalVersion(void)
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 540              		.loc 1 421 1 is_stmt 1 view -0
+ 541              		.cfi_startproc
+ 542              		@ args = 0, pretend = 0, frame = 0
+ 543              		@ frame_needed = 0, uses_anonymous_args = 0
+ 544              		@ link register save eliminated.
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   return __STM32F7xx_HAL_VERSION;
+ 545              		.loc 1 422 3 view .LVU104
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 546              		.loc 1 423 1 is_stmt 0 view .LVU105
+ 547 0000 0048     		ldr	r0, .L45
+ 548 0002 7047     		bx	lr
+ 549              	.L46:
+ 550              		.align	2
+ 551              	.L45:
+ 552 0004 00010301 		.word	16974080
+ 553              		.cfi_endproc
+ 554              	.LFE154:
+ 556              		.section	.text.HAL_GetREVID,"ax",%progbits
+ 557              		.align	1
+ 558              		.global	HAL_GetREVID
+ 559              		.syntax unified
+ 560              		.thumb
+ 561              		.thumb_func
+ 562              		.fpu fpv5-d16
+ 564              	HAL_GetREVID:
+ 565              	.LFB155:
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Returns the device revision identifier.
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval Device revision identifier
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetREVID(void)
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 566              		.loc 1 430 1 is_stmt 1 view -0
+ 567              		.cfi_startproc
+ 568              		@ args = 0, pretend = 0, frame = 0
+ 569              		@ frame_needed = 0, uses_anonymous_args = 0
+ 570              		@ link register save eliminated.
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****    return((DBGMCU->IDCODE) >> 16U);
+ 571              		.loc 1 431 4 view .LVU107
+ 572              		.loc 1 431 18 is_stmt 0 view .LVU108
+ 573 0000 014B     		ldr	r3, .L48
+ 574 0002 1868     		ldr	r0, [r3]
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 575              		.loc 1 432 1 view .LVU109
+ 576 0004 000C     		lsrs	r0, r0, #16
+ 577 0006 7047     		bx	lr
+ 578              	.L49:
+ 579              		.align	2
+ 580              	.L48:
+ 581 0008 002004E0 		.word	-536600576
+ 582              		.cfi_endproc
+ 583              	.LFE155:
+ 585              		.section	.text.HAL_GetDEVID,"ax",%progbits
+ARM GAS  /tmp/cceuBEQV.s 			page 19
+
+
+ 586              		.align	1
+ 587              		.global	HAL_GetDEVID
+ 588              		.syntax unified
+ 589              		.thumb
+ 590              		.thumb_func
+ 591              		.fpu fpv5-d16
+ 593              	HAL_GetDEVID:
+ 594              	.LFB156:
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Returns the device identifier.
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval Device identifier
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetDEVID(void)
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 595              		.loc 1 439 1 is_stmt 1 view -0
+ 596              		.cfi_startproc
+ 597              		@ args = 0, pretend = 0, frame = 0
+ 598              		@ frame_needed = 0, uses_anonymous_args = 0
+ 599              		@ link register save eliminated.
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****    return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+ 600              		.loc 1 440 4 view .LVU111
+ 601              		.loc 1 440 18 is_stmt 0 view .LVU112
+ 602 0000 024B     		ldr	r3, .L51
+ 603 0002 1868     		ldr	r0, [r3]
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 604              		.loc 1 441 1 view .LVU113
+ 605 0004 C0F30B00 		ubfx	r0, r0, #0, #12
+ 606 0008 7047     		bx	lr
+ 607              	.L52:
+ 608 000a 00BF     		.align	2
+ 609              	.L51:
+ 610 000c 002004E0 		.word	-536600576
+ 611              		.cfi_endproc
+ 612              	.LFE156:
+ 614              		.section	.text.HAL_GetUIDw0,"ax",%progbits
+ 615              		.align	1
+ 616              		.global	HAL_GetUIDw0
+ 617              		.syntax unified
+ 618              		.thumb
+ 619              		.thumb_func
+ 620              		.fpu fpv5-d16
+ 622              	HAL_GetUIDw0:
+ 623              	.LFB157:
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval Device identifier
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetUIDw0(void)
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 624              		.loc 1 448 1 is_stmt 1 view -0
+ 625              		.cfi_startproc
+ 626              		@ args = 0, pretend = 0, frame = 0
+ 627              		@ frame_needed = 0, uses_anonymous_args = 0
+ 628              		@ link register save eliminated.
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   return(READ_REG(*((uint32_t *)UID_BASE)));
+ARM GAS  /tmp/cceuBEQV.s 			page 20
+
+
+ 629              		.loc 1 449 3 view .LVU115
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 630              		.loc 1 450 1 is_stmt 0 view .LVU116
+ 631 0000 014B     		ldr	r3, .L54
+ 632 0002 D3F82004 		ldr	r0, [r3, #1056]
+ 633 0006 7047     		bx	lr
+ 634              	.L55:
+ 635              		.align	2
+ 636              	.L54:
+ 637 0008 00F0F01F 		.word	535883776
+ 638              		.cfi_endproc
+ 639              	.LFE157:
+ 641              		.section	.text.HAL_GetUIDw1,"ax",%progbits
+ 642              		.align	1
+ 643              		.global	HAL_GetUIDw1
+ 644              		.syntax unified
+ 645              		.thumb
+ 646              		.thumb_func
+ 647              		.fpu fpv5-d16
+ 649              	HAL_GetUIDw1:
+ 650              	.LFB158:
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval Device identifier
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetUIDw1(void)
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 651              		.loc 1 457 1 is_stmt 1 view -0
+ 652              		.cfi_startproc
+ 653              		@ args = 0, pretend = 0, frame = 0
+ 654              		@ frame_needed = 0, uses_anonymous_args = 0
+ 655              		@ link register save eliminated.
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+ 656              		.loc 1 458 3 view .LVU118
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 657              		.loc 1 459 1 is_stmt 0 view .LVU119
+ 658 0000 014B     		ldr	r3, .L57
+ 659 0002 D3F82404 		ldr	r0, [r3, #1060]
+ 660 0006 7047     		bx	lr
+ 661              	.L58:
+ 662              		.align	2
+ 663              	.L57:
+ 664 0008 00F0F01F 		.word	535883776
+ 665              		.cfi_endproc
+ 666              	.LFE158:
+ 668              		.section	.text.HAL_GetUIDw2,"ax",%progbits
+ 669              		.align	1
+ 670              		.global	HAL_GetUIDw2
+ 671              		.syntax unified
+ 672              		.thumb
+ 673              		.thumb_func
+ 674              		.fpu fpv5-d16
+ 676              	HAL_GetUIDw2:
+ 677              	.LFB159:
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ARM GAS  /tmp/cceuBEQV.s 			page 21
+
+
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval Device identifier
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetUIDw2(void)
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 678              		.loc 1 466 1 is_stmt 1 view -0
+ 679              		.cfi_startproc
+ 680              		@ args = 0, pretend = 0, frame = 0
+ 681              		@ frame_needed = 0, uses_anonymous_args = 0
+ 682              		@ link register save eliminated.
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+ 683              		.loc 1 467 3 view .LVU121
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 684              		.loc 1 468 1 is_stmt 0 view .LVU122
+ 685 0000 014B     		ldr	r3, .L60
+ 686 0002 D3F82804 		ldr	r0, [r3, #1064]
+ 687 0006 7047     		bx	lr
+ 688              	.L61:
+ 689              		.align	2
+ 690              	.L60:
+ 691 0008 00F0F01F 		.word	535883776
+ 692              		.cfi_endproc
+ 693              	.LFE159:
+ 695              		.section	.text.HAL_DBGMCU_EnableDBGSleepMode,"ax",%progbits
+ 696              		.align	1
+ 697              		.global	HAL_DBGMCU_EnableDBGSleepMode
+ 698              		.syntax unified
+ 699              		.thumb
+ 700              		.thumb_func
+ 701              		.fpu fpv5-d16
+ 703              	HAL_DBGMCU_EnableDBGSleepMode:
+ 704              	.LFB160:
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Enable the Debug Module during SLEEP mode
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_EnableDBGSleepMode(void)
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 705              		.loc 1 475 1 is_stmt 1 view -0
+ 706              		.cfi_startproc
+ 707              		@ args = 0, pretend = 0, frame = 0
+ 708              		@ frame_needed = 0, uses_anonymous_args = 0
+ 709              		@ link register save eliminated.
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+ 710              		.loc 1 476 3 view .LVU124
+ 711 0000 024A     		ldr	r2, .L63
+ 712 0002 5368     		ldr	r3, [r2, #4]
+ 713 0004 43F00103 		orr	r3, r3, #1
+ 714 0008 5360     		str	r3, [r2, #4]
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 715              		.loc 1 477 1 is_stmt 0 view .LVU125
+ 716 000a 7047     		bx	lr
+ 717              	.L64:
+ 718              		.align	2
+ 719              	.L63:
+ 720 000c 002004E0 		.word	-536600576
+ARM GAS  /tmp/cceuBEQV.s 			page 22
+
+
+ 721              		.cfi_endproc
+ 722              	.LFE160:
+ 724              		.section	.text.HAL_DBGMCU_DisableDBGSleepMode,"ax",%progbits
+ 725              		.align	1
+ 726              		.global	HAL_DBGMCU_DisableDBGSleepMode
+ 727              		.syntax unified
+ 728              		.thumb
+ 729              		.thumb_func
+ 730              		.fpu fpv5-d16
+ 732              	HAL_DBGMCU_DisableDBGSleepMode:
+ 733              	.LFB161:
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Disable the Debug Module during SLEEP mode
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_DisableDBGSleepMode(void)
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 734              		.loc 1 484 1 is_stmt 1 view -0
+ 735              		.cfi_startproc
+ 736              		@ args = 0, pretend = 0, frame = 0
+ 737              		@ frame_needed = 0, uses_anonymous_args = 0
+ 738              		@ link register save eliminated.
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+ 739              		.loc 1 485 3 view .LVU127
+ 740 0000 024A     		ldr	r2, .L66
+ 741 0002 5368     		ldr	r3, [r2, #4]
+ 742 0004 23F00103 		bic	r3, r3, #1
+ 743 0008 5360     		str	r3, [r2, #4]
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 744              		.loc 1 486 1 is_stmt 0 view .LVU128
+ 745 000a 7047     		bx	lr
+ 746              	.L67:
+ 747              		.align	2
+ 748              	.L66:
+ 749 000c 002004E0 		.word	-536600576
+ 750              		.cfi_endproc
+ 751              	.LFE161:
+ 753              		.section	.text.HAL_DBGMCU_EnableDBGStopMode,"ax",%progbits
+ 754              		.align	1
+ 755              		.global	HAL_DBGMCU_EnableDBGStopMode
+ 756              		.syntax unified
+ 757              		.thumb
+ 758              		.thumb_func
+ 759              		.fpu fpv5-d16
+ 761              	HAL_DBGMCU_EnableDBGStopMode:
+ 762              	.LFB162:
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Enable the Debug Module during STOP mode
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_EnableDBGStopMode(void)
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 763              		.loc 1 493 1 is_stmt 1 view -0
+ 764              		.cfi_startproc
+ 765              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/cceuBEQV.s 			page 23
+
+
+ 766              		@ frame_needed = 0, uses_anonymous_args = 0
+ 767              		@ link register save eliminated.
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+ 768              		.loc 1 494 3 view .LVU130
+ 769 0000 024A     		ldr	r2, .L69
+ 770 0002 5368     		ldr	r3, [r2, #4]
+ 771 0004 43F00203 		orr	r3, r3, #2
+ 772 0008 5360     		str	r3, [r2, #4]
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 773              		.loc 1 495 1 is_stmt 0 view .LVU131
+ 774 000a 7047     		bx	lr
+ 775              	.L70:
+ 776              		.align	2
+ 777              	.L69:
+ 778 000c 002004E0 		.word	-536600576
+ 779              		.cfi_endproc
+ 780              	.LFE162:
+ 782              		.section	.text.HAL_DBGMCU_DisableDBGStopMode,"ax",%progbits
+ 783              		.align	1
+ 784              		.global	HAL_DBGMCU_DisableDBGStopMode
+ 785              		.syntax unified
+ 786              		.thumb
+ 787              		.thumb_func
+ 788              		.fpu fpv5-d16
+ 790              	HAL_DBGMCU_DisableDBGStopMode:
+ 791              	.LFB163:
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Disable the Debug Module during STOP mode
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_DisableDBGStopMode(void)
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 792              		.loc 1 502 1 is_stmt 1 view -0
+ 793              		.cfi_startproc
+ 794              		@ args = 0, pretend = 0, frame = 0
+ 795              		@ frame_needed = 0, uses_anonymous_args = 0
+ 796              		@ link register save eliminated.
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+ 797              		.loc 1 503 3 view .LVU133
+ 798 0000 024A     		ldr	r2, .L72
+ 799 0002 5368     		ldr	r3, [r2, #4]
+ 800 0004 23F00203 		bic	r3, r3, #2
+ 801 0008 5360     		str	r3, [r2, #4]
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 802              		.loc 1 504 1 is_stmt 0 view .LVU134
+ 803 000a 7047     		bx	lr
+ 804              	.L73:
+ 805              		.align	2
+ 806              	.L72:
+ 807 000c 002004E0 		.word	-536600576
+ 808              		.cfi_endproc
+ 809              	.LFE163:
+ 811              		.section	.text.HAL_DBGMCU_EnableDBGStandbyMode,"ax",%progbits
+ 812              		.align	1
+ 813              		.global	HAL_DBGMCU_EnableDBGStandbyMode
+ 814              		.syntax unified
+ARM GAS  /tmp/cceuBEQV.s 			page 24
+
+
+ 815              		.thumb
+ 816              		.thumb_func
+ 817              		.fpu fpv5-d16
+ 819              	HAL_DBGMCU_EnableDBGStandbyMode:
+ 820              	.LFB164:
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Enable the Debug Module during STANDBY mode
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_EnableDBGStandbyMode(void)
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 821              		.loc 1 511 1 is_stmt 1 view -0
+ 822              		.cfi_startproc
+ 823              		@ args = 0, pretend = 0, frame = 0
+ 824              		@ frame_needed = 0, uses_anonymous_args = 0
+ 825              		@ link register save eliminated.
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+ 826              		.loc 1 512 3 view .LVU136
+ 827 0000 024A     		ldr	r2, .L75
+ 828 0002 5368     		ldr	r3, [r2, #4]
+ 829 0004 43F00403 		orr	r3, r3, #4
+ 830 0008 5360     		str	r3, [r2, #4]
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 831              		.loc 1 513 1 is_stmt 0 view .LVU137
+ 832 000a 7047     		bx	lr
+ 833              	.L76:
+ 834              		.align	2
+ 835              	.L75:
+ 836 000c 002004E0 		.word	-536600576
+ 837              		.cfi_endproc
+ 838              	.LFE164:
+ 840              		.section	.text.HAL_DBGMCU_DisableDBGStandbyMode,"ax",%progbits
+ 841              		.align	1
+ 842              		.global	HAL_DBGMCU_DisableDBGStandbyMode
+ 843              		.syntax unified
+ 844              		.thumb
+ 845              		.thumb_func
+ 846              		.fpu fpv5-d16
+ 848              	HAL_DBGMCU_DisableDBGStandbyMode:
+ 849              	.LFB165:
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Disable the Debug Module during STANDBY mode
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_DisableDBGStandbyMode(void)
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 850              		.loc 1 520 1 is_stmt 1 view -0
+ 851              		.cfi_startproc
+ 852              		@ args = 0, pretend = 0, frame = 0
+ 853              		@ frame_needed = 0, uses_anonymous_args = 0
+ 854              		@ link register save eliminated.
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+ 855              		.loc 1 521 3 view .LVU139
+ 856 0000 024A     		ldr	r2, .L78
+ 857 0002 5368     		ldr	r3, [r2, #4]
+ARM GAS  /tmp/cceuBEQV.s 			page 25
+
+
+ 858 0004 23F00403 		bic	r3, r3, #4
+ 859 0008 5360     		str	r3, [r2, #4]
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 860              		.loc 1 522 1 is_stmt 0 view .LVU140
+ 861 000a 7047     		bx	lr
+ 862              	.L79:
+ 863              		.align	2
+ 864              	.L78:
+ 865 000c 002004E0 		.word	-536600576
+ 866              		.cfi_endproc
+ 867              	.LFE165:
+ 869              		.section	.text.HAL_EnableCompensationCell,"ax",%progbits
+ 870              		.align	1
+ 871              		.global	HAL_EnableCompensationCell
+ 872              		.syntax unified
+ 873              		.thumb
+ 874              		.thumb_func
+ 875              		.fpu fpv5-d16
+ 877              	HAL_EnableCompensationCell:
+ 878              	.LFB166:
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Enables the I/O Compensation Cell.
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note   The I/O compensation cell can be used only when the device supply
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *         voltage ranges from 2.4 to 3.6 V.  
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_EnableCompensationCell(void)
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 879              		.loc 1 531 1 is_stmt 1 view -0
+ 880              		.cfi_startproc
+ 881              		@ args = 0, pretend = 0, frame = 0
+ 882              		@ frame_needed = 0, uses_anonymous_args = 0
+ 883              		@ link register save eliminated.
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;
+ 884              		.loc 1 532 3 view .LVU142
+ 885              		.loc 1 532 17 is_stmt 0 view .LVU143
+ 886 0000 024A     		ldr	r2, .L81
+ 887 0002 136A     		ldr	r3, [r2, #32]
+ 888 0004 43F00103 		orr	r3, r3, #1
+ 889 0008 1362     		str	r3, [r2, #32]
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 890              		.loc 1 533 1 view .LVU144
+ 891 000a 7047     		bx	lr
+ 892              	.L82:
+ 893              		.align	2
+ 894              	.L81:
+ 895 000c 00380140 		.word	1073821696
+ 896              		.cfi_endproc
+ 897              	.LFE166:
+ 899              		.section	.text.HAL_DisableCompensationCell,"ax",%progbits
+ 900              		.align	1
+ 901              		.global	HAL_DisableCompensationCell
+ 902              		.syntax unified
+ 903              		.thumb
+ 904              		.thumb_func
+ 905              		.fpu fpv5-d16
+ARM GAS  /tmp/cceuBEQV.s 			page 26
+
+
+ 907              	HAL_DisableCompensationCell:
+ 908              	.LFB167:
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Power-down the I/O Compensation Cell.
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note   The I/O compensation cell can be used only when the device supply
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *         voltage ranges from 2.4 to 3.6 V.  
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DisableCompensationCell(void)
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 909              		.loc 1 542 1 is_stmt 1 view -0
+ 910              		.cfi_startproc
+ 911              		@ args = 0, pretend = 0, frame = 0
+ 912              		@ frame_needed = 0, uses_anonymous_args = 0
+ 913              		@ link register save eliminated.
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);
+ 914              		.loc 1 543 3 view .LVU146
+ 915              		.loc 1 543 17 is_stmt 0 view .LVU147
+ 916 0000 024A     		ldr	r2, .L84
+ 917 0002 136A     		ldr	r3, [r2, #32]
+ 918 0004 23F00103 		bic	r3, r3, #1
+ 919 0008 1362     		str	r3, [r2, #32]
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 920              		.loc 1 544 1 view .LVU148
+ 921 000a 7047     		bx	lr
+ 922              	.L85:
+ 923              		.align	2
+ 924              	.L84:
+ 925 000c 00380140 		.word	1073821696
+ 926              		.cfi_endproc
+ 927              	.LFE167:
+ 929              		.section	.text.HAL_EnableFMCMemorySwapping,"ax",%progbits
+ 930              		.align	1
+ 931              		.global	HAL_EnableFMCMemorySwapping
+ 932              		.syntax unified
+ 933              		.thumb
+ 934              		.thumb_func
+ 935              		.fpu fpv5-d16
+ 937              	HAL_EnableFMCMemorySwapping:
+ 938              	.LFB168:
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Enables the FMC Memory Mapping Swapping.
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *   
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note   SDRAM is accessible at 0x60000000 
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *         and NOR/RAM is accessible at 0xC0000000   
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_EnableFMCMemorySwapping(void)
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 939              		.loc 1 555 1 is_stmt 1 view -0
+ 940              		.cfi_startproc
+ 941              		@ args = 0, pretend = 0, frame = 0
+ 942              		@ frame_needed = 0, uses_anonymous_args = 0
+ 943              		@ link register save eliminated.
+ARM GAS  /tmp/cceuBEQV.s 			page 27
+
+
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;
+ 944              		.loc 1 556 3 view .LVU150
+ 945              		.loc 1 556 18 is_stmt 0 view .LVU151
+ 946 0000 024A     		ldr	r2, .L87
+ 947 0002 1368     		ldr	r3, [r2]
+ 948 0004 43F48063 		orr	r3, r3, #1024
+ 949 0008 1360     		str	r3, [r2]
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 950              		.loc 1 557 1 view .LVU152
+ 951 000a 7047     		bx	lr
+ 952              	.L88:
+ 953              		.align	2
+ 954              	.L87:
+ 955 000c 00380140 		.word	1073821696
+ 956              		.cfi_endproc
+ 957              	.LFE168:
+ 959              		.section	.text.HAL_DisableFMCMemorySwapping,"ax",%progbits
+ 960              		.align	1
+ 961              		.global	HAL_DisableFMCMemorySwapping
+ 962              		.syntax unified
+ 963              		.thumb
+ 964              		.thumb_func
+ 965              		.fpu fpv5-d16
+ 967              	HAL_DisableFMCMemorySwapping:
+ 968              	.LFB169:
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @brief  Disables the FMC Memory Mapping Swapping
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *   
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @note   SDRAM is accessible at 0xC0000000 (default mapping)  
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *         and NOR/RAM is accessible at 0x60000000 (default mapping)    
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   *           
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   * @retval None
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   */
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DisableFMCMemorySwapping(void)
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 969              		.loc 1 568 1 is_stmt 1 view -0
+ 970              		.cfi_startproc
+ 971              		@ args = 0, pretend = 0, frame = 0
+ 972              		@ frame_needed = 0, uses_anonymous_args = 0
+ 973              		@ link register save eliminated.
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);
+ 974              		.loc 1 569 3 view .LVU154
+ 975              		.loc 1 569 18 is_stmt 0 view .LVU155
+ 976 0000 024A     		ldr	r2, .L90
+ 977 0002 1368     		ldr	r3, [r2]
+ 978 0004 23F44063 		bic	r3, r3, #3072
+ 979 0008 1360     		str	r3, [r2]
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 980              		.loc 1 570 1 view .LVU156
+ 981 000a 7047     		bx	lr
+ 982              	.L91:
+ 983              		.align	2
+ 984              	.L90:
+ 985 000c 00380140 		.word	1073821696
+ 986              		.cfi_endproc
+ 987              	.LFE169:
+ARM GAS  /tmp/cceuBEQV.s 			page 28
+
+
+ 989              		.section	.text.HAL_EnableMemorySwappingBank,"ax",%progbits
+ 990              		.align	1
+ 991              		.global	HAL_EnableMemorySwappingBank
+ 992              		.syntax unified
+ 993              		.thumb
+ 994              		.thumb_func
+ 995              		.fpu fpv5-d16
+ 997              	HAL_EnableMemorySwappingBank:
+ 998              	.LFB170:
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief  Enable the Internal FLASH Bank Swapping.
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** *   
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note   This function can be used only for STM32F77xx/STM32F76xx devices. 
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** *
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note   Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) 
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** *         and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM))   
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** *
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_EnableMemorySwappingBank(void)
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 999              		.loc 1 584 1 is_stmt 1 view -0
+ 1000              		.cfi_startproc
+ 1001              		@ args = 0, pretend = 0, frame = 0
+ 1002              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1003              		@ link register save eliminated.
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
+ 1004              		.loc 1 585 3 view .LVU158
+ 1005 0000 024A     		ldr	r2, .L93
+ 1006 0002 1368     		ldr	r3, [r2]
+ 1007 0004 43F48073 		orr	r3, r3, #256
+ 1008 0008 1360     		str	r3, [r2]
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 1009              		.loc 1 586 1 is_stmt 0 view .LVU159
+ 1010 000a 7047     		bx	lr
+ 1011              	.L94:
+ 1012              		.align	2
+ 1013              	.L93:
+ 1014 000c 00380140 		.word	1073821696
+ 1015              		.cfi_endproc
+ 1016              	.LFE170:
+ 1018              		.section	.text.HAL_DisableMemorySwappingBank,"ax",%progbits
+ 1019              		.align	1
+ 1020              		.global	HAL_DisableMemorySwappingBank
+ 1021              		.syntax unified
+ 1022              		.thumb
+ 1023              		.thumb_func
+ 1024              		.fpu fpv5-d16
+ 1026              	HAL_DisableMemorySwappingBank:
+ 1027              	.LFB171:
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** 
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /**
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief  Disable the Internal FLASH Bank Swapping.
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** *   
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note   This function can be used only for STM32F77xx/STM32F76xx devices. 
+ARM GAS  /tmp/cceuBEQV.s 			page 29
+
+
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** *
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note   The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) 
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** *         and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) 
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** *           
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DisableMemorySwappingBank(void)
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** {
+ 1028              		.loc 1 599 1 is_stmt 1 view -0
+ 1029              		.cfi_startproc
+ 1030              		@ args = 0, pretend = 0, frame = 0
+ 1031              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1032              		@ link register save eliminated.
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c ****   CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
+ 1033              		.loc 1 600 3 view .LVU161
+ 1034 0000 024A     		ldr	r2, .L96
+ 1035 0002 1368     		ldr	r3, [r2]
+ 1036 0004 23F48073 		bic	r3, r3, #256
+ 1037 0008 1360     		str	r3, [r2]
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** }
+ 1038              		.loc 1 601 1 is_stmt 0 view .LVU162
+ 1039 000a 7047     		bx	lr
+ 1040              	.L97:
+ 1041              		.align	2
+ 1042              	.L96:
+ 1043 000c 00380140 		.word	1073821696
+ 1044              		.cfi_endproc
+ 1045              	.LFE171:
+ 1047              		.global	uwTickFreq
+ 1048              		.global	uwTickPrio
+ 1049              		.global	uwTick
+ 1050              		.section	.bss.uwTick,"aw",%nobits
+ 1051              		.align	2
+ 1052              		.set	.LANCHOR2,. + 0
+ 1055              	uwTick:
+ 1056 0000 00000000 		.space	4
+ 1057              		.section	.data.uwTickFreq,"aw"
+ 1058              		.set	.LANCHOR0,. + 0
+ 1061              	uwTickFreq:
+ 1062 0000 01       		.byte	1
+ 1063              		.section	.data.uwTickPrio,"aw"
+ 1064              		.align	2
+ 1065              		.set	.LANCHOR1,. + 0
+ 1068              	uwTickPrio:
+ 1069 0000 10000000 		.word	16
+ 1070              		.text
+ 1071              	.Letext0:
+ 1072              		.file 2 "Drivers/CMSIS/Include/core_cm7.h"
+ 1073              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 1074              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 1075              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 1076              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ 1077              		.file 7 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h"
+ 1078              		.file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h"
+ARM GAS  /tmp/cceuBEQV.s 			page 30
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal.c
+     /tmp/cceuBEQV.s:17     .text.HAL_MspInit:0000000000000000 $t
+     /tmp/cceuBEQV.s:25     .text.HAL_MspInit:0000000000000000 HAL_MspInit
+     /tmp/cceuBEQV.s:39     .text.HAL_MspDeInit:0000000000000000 $t
+     /tmp/cceuBEQV.s:46     .text.HAL_MspDeInit:0000000000000000 HAL_MspDeInit
+     /tmp/cceuBEQV.s:59     .text.HAL_DeInit:0000000000000000 $t
+     /tmp/cceuBEQV.s:66     .text.HAL_DeInit:0000000000000000 HAL_DeInit
+     /tmp/cceuBEQV.s:110    .text.HAL_DeInit:0000000000000028 $d
+     /tmp/cceuBEQV.s:115    .text.HAL_InitTick:0000000000000000 $t
+     /tmp/cceuBEQV.s:122    .text.HAL_InitTick:0000000000000000 HAL_InitTick
+     /tmp/cceuBEQV.s:185    .text.HAL_InitTick:0000000000000040 $d
+     /tmp/cceuBEQV.s:192    .text.HAL_Init:0000000000000000 $t
+     /tmp/cceuBEQV.s:199    .text.HAL_Init:0000000000000000 HAL_Init
+     /tmp/cceuBEQV.s:229    .text.HAL_IncTick:0000000000000000 $t
+     /tmp/cceuBEQV.s:236    .text.HAL_IncTick:0000000000000000 HAL_IncTick
+     /tmp/cceuBEQV.s:256    .text.HAL_IncTick:0000000000000010 $d
+     /tmp/cceuBEQV.s:262    .text.HAL_GetTick:0000000000000000 $t
+     /tmp/cceuBEQV.s:269    .text.HAL_GetTick:0000000000000000 HAL_GetTick
+     /tmp/cceuBEQV.s:285    .text.HAL_GetTick:0000000000000008 $d
+     /tmp/cceuBEQV.s:290    .text.HAL_GetTickPrio:0000000000000000 $t
+     /tmp/cceuBEQV.s:297    .text.HAL_GetTickPrio:0000000000000000 HAL_GetTickPrio
+     /tmp/cceuBEQV.s:312    .text.HAL_GetTickPrio:0000000000000008 $d
+     /tmp/cceuBEQV.s:317    .text.HAL_SetTickFreq:0000000000000000 $t
+     /tmp/cceuBEQV.s:324    .text.HAL_SetTickFreq:0000000000000000 HAL_SetTickFreq
+     /tmp/cceuBEQV.s:381    .text.HAL_SetTickFreq:0000000000000024 $d
+     /tmp/cceuBEQV.s:387    .text.HAL_GetTickFreq:0000000000000000 $t
+     /tmp/cceuBEQV.s:394    .text.HAL_GetTickFreq:0000000000000000 HAL_GetTickFreq
+     /tmp/cceuBEQV.s:409    .text.HAL_GetTickFreq:0000000000000008 $d
+     /tmp/cceuBEQV.s:414    .text.HAL_Delay:0000000000000000 $t
+     /tmp/cceuBEQV.s:421    .text.HAL_Delay:0000000000000000 HAL_Delay
+     /tmp/cceuBEQV.s:474    .text.HAL_Delay:0000000000000024 $d
+     /tmp/cceuBEQV.s:479    .text.HAL_SuspendTick:0000000000000000 $t
+     /tmp/cceuBEQV.s:486    .text.HAL_SuspendTick:0000000000000000 HAL_SuspendTick
+     /tmp/cceuBEQV.s:505    .text.HAL_ResumeTick:0000000000000000 $t
+     /tmp/cceuBEQV.s:512    .text.HAL_ResumeTick:0000000000000000 HAL_ResumeTick
+     /tmp/cceuBEQV.s:531    .text.HAL_GetHalVersion:0000000000000000 $t
+     /tmp/cceuBEQV.s:538    .text.HAL_GetHalVersion:0000000000000000 HAL_GetHalVersion
+     /tmp/cceuBEQV.s:552    .text.HAL_GetHalVersion:0000000000000004 $d
+     /tmp/cceuBEQV.s:557    .text.HAL_GetREVID:0000000000000000 $t
+     /tmp/cceuBEQV.s:564    .text.HAL_GetREVID:0000000000000000 HAL_GetREVID
+     /tmp/cceuBEQV.s:581    .text.HAL_GetREVID:0000000000000008 $d
+     /tmp/cceuBEQV.s:586    .text.HAL_GetDEVID:0000000000000000 $t
+     /tmp/cceuBEQV.s:593    .text.HAL_GetDEVID:0000000000000000 HAL_GetDEVID
+     /tmp/cceuBEQV.s:610    .text.HAL_GetDEVID:000000000000000c $d
+     /tmp/cceuBEQV.s:615    .text.HAL_GetUIDw0:0000000000000000 $t
+     /tmp/cceuBEQV.s:622    .text.HAL_GetUIDw0:0000000000000000 HAL_GetUIDw0
+     /tmp/cceuBEQV.s:637    .text.HAL_GetUIDw0:0000000000000008 $d
+     /tmp/cceuBEQV.s:642    .text.HAL_GetUIDw1:0000000000000000 $t
+     /tmp/cceuBEQV.s:649    .text.HAL_GetUIDw1:0000000000000000 HAL_GetUIDw1
+     /tmp/cceuBEQV.s:664    .text.HAL_GetUIDw1:0000000000000008 $d
+     /tmp/cceuBEQV.s:669    .text.HAL_GetUIDw2:0000000000000000 $t
+     /tmp/cceuBEQV.s:676    .text.HAL_GetUIDw2:0000000000000000 HAL_GetUIDw2
+     /tmp/cceuBEQV.s:691    .text.HAL_GetUIDw2:0000000000000008 $d
+     /tmp/cceuBEQV.s:696    .text.HAL_DBGMCU_EnableDBGSleepMode:0000000000000000 $t
+     /tmp/cceuBEQV.s:703    .text.HAL_DBGMCU_EnableDBGSleepMode:0000000000000000 HAL_DBGMCU_EnableDBGSleepMode
+     /tmp/cceuBEQV.s:720    .text.HAL_DBGMCU_EnableDBGSleepMode:000000000000000c $d
+ARM GAS  /tmp/cceuBEQV.s 			page 31
+
+
+     /tmp/cceuBEQV.s:725    .text.HAL_DBGMCU_DisableDBGSleepMode:0000000000000000 $t
+     /tmp/cceuBEQV.s:732    .text.HAL_DBGMCU_DisableDBGSleepMode:0000000000000000 HAL_DBGMCU_DisableDBGSleepMode
+     /tmp/cceuBEQV.s:749    .text.HAL_DBGMCU_DisableDBGSleepMode:000000000000000c $d
+     /tmp/cceuBEQV.s:754    .text.HAL_DBGMCU_EnableDBGStopMode:0000000000000000 $t
+     /tmp/cceuBEQV.s:761    .text.HAL_DBGMCU_EnableDBGStopMode:0000000000000000 HAL_DBGMCU_EnableDBGStopMode
+     /tmp/cceuBEQV.s:778    .text.HAL_DBGMCU_EnableDBGStopMode:000000000000000c $d
+     /tmp/cceuBEQV.s:783    .text.HAL_DBGMCU_DisableDBGStopMode:0000000000000000 $t
+     /tmp/cceuBEQV.s:790    .text.HAL_DBGMCU_DisableDBGStopMode:0000000000000000 HAL_DBGMCU_DisableDBGStopMode
+     /tmp/cceuBEQV.s:807    .text.HAL_DBGMCU_DisableDBGStopMode:000000000000000c $d
+     /tmp/cceuBEQV.s:812    .text.HAL_DBGMCU_EnableDBGStandbyMode:0000000000000000 $t
+     /tmp/cceuBEQV.s:819    .text.HAL_DBGMCU_EnableDBGStandbyMode:0000000000000000 HAL_DBGMCU_EnableDBGStandbyMode
+     /tmp/cceuBEQV.s:836    .text.HAL_DBGMCU_EnableDBGStandbyMode:000000000000000c $d
+     /tmp/cceuBEQV.s:841    .text.HAL_DBGMCU_DisableDBGStandbyMode:0000000000000000 $t
+     /tmp/cceuBEQV.s:848    .text.HAL_DBGMCU_DisableDBGStandbyMode:0000000000000000 HAL_DBGMCU_DisableDBGStandbyMode
+     /tmp/cceuBEQV.s:865    .text.HAL_DBGMCU_DisableDBGStandbyMode:000000000000000c $d
+     /tmp/cceuBEQV.s:870    .text.HAL_EnableCompensationCell:0000000000000000 $t
+     /tmp/cceuBEQV.s:877    .text.HAL_EnableCompensationCell:0000000000000000 HAL_EnableCompensationCell
+     /tmp/cceuBEQV.s:895    .text.HAL_EnableCompensationCell:000000000000000c $d
+     /tmp/cceuBEQV.s:900    .text.HAL_DisableCompensationCell:0000000000000000 $t
+     /tmp/cceuBEQV.s:907    .text.HAL_DisableCompensationCell:0000000000000000 HAL_DisableCompensationCell
+     /tmp/cceuBEQV.s:925    .text.HAL_DisableCompensationCell:000000000000000c $d
+     /tmp/cceuBEQV.s:930    .text.HAL_EnableFMCMemorySwapping:0000000000000000 $t
+     /tmp/cceuBEQV.s:937    .text.HAL_EnableFMCMemorySwapping:0000000000000000 HAL_EnableFMCMemorySwapping
+     /tmp/cceuBEQV.s:955    .text.HAL_EnableFMCMemorySwapping:000000000000000c $d
+     /tmp/cceuBEQV.s:960    .text.HAL_DisableFMCMemorySwapping:0000000000000000 $t
+     /tmp/cceuBEQV.s:967    .text.HAL_DisableFMCMemorySwapping:0000000000000000 HAL_DisableFMCMemorySwapping
+     /tmp/cceuBEQV.s:985    .text.HAL_DisableFMCMemorySwapping:000000000000000c $d
+     /tmp/cceuBEQV.s:990    .text.HAL_EnableMemorySwappingBank:0000000000000000 $t
+     /tmp/cceuBEQV.s:997    .text.HAL_EnableMemorySwappingBank:0000000000000000 HAL_EnableMemorySwappingBank
+     /tmp/cceuBEQV.s:1014   .text.HAL_EnableMemorySwappingBank:000000000000000c $d
+     /tmp/cceuBEQV.s:1019   .text.HAL_DisableMemorySwappingBank:0000000000000000 $t
+     /tmp/cceuBEQV.s:1026   .text.HAL_DisableMemorySwappingBank:0000000000000000 HAL_DisableMemorySwappingBank
+     /tmp/cceuBEQV.s:1043   .text.HAL_DisableMemorySwappingBank:000000000000000c $d
+     /tmp/cceuBEQV.s:1061   .data.uwTickFreq:0000000000000000 uwTickFreq
+     /tmp/cceuBEQV.s:1068   .data.uwTickPrio:0000000000000000 uwTickPrio
+     /tmp/cceuBEQV.s:1055   .bss.uwTick:0000000000000000 uwTick
+     /tmp/cceuBEQV.s:1051   .bss.uwTick:0000000000000000 $d
+     /tmp/cceuBEQV.s:1064   .data.uwTickPrio:0000000000000000 $d
+
+UNDEFINED SYMBOLS
+HAL_SYSTICK_Config
+HAL_NVIC_SetPriority
+SystemCoreClock
+HAL_NVIC_SetPriorityGrouping
diff --git a/build/stm32f7xx_hal.o b/build/stm32f7xx_hal.o
new file mode 100644
index 0000000..5c059d3
Binary files /dev/null and b/build/stm32f7xx_hal.o differ
diff --git a/build/stm32f7xx_hal_adc.d b/build/stm32f7xx_hal_adc.d
new file mode 100644
index 0000000..b579621
--- /dev/null
+++ b/build/stm32f7xx_hal_adc.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_adc.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_adc.lst b/build/stm32f7xx_hal_adc.lst
new file mode 100644
index 0000000..8c9dc94
--- /dev/null
+++ b/build/stm32f7xx_hal_adc.lst
@@ -0,0 +1,6352 @@
+ARM GAS  /tmp/ccHbw826.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_adc.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.ADC_Init,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	ADC_Init:
+  25              	.LVL0:
+  26              	.LFB163:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @file    stm32f7xx_hal_adc.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief   This file provides firmware functions to manage the following 
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          functionalities of the Analog to Digital Converter (ADC) peripheral:
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *           + Initialization and de-initialization functions
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *           + Peripheral Control functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *           + Peripheral State functions
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ******************************************************************************
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @attention
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * Copyright (c) 2017 STMicroelectronics.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * All rights reserved.
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * in the root directory of this software component.
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ******************************************************************************
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   @verbatim
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ==============================================================================
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                     ##### ADC Peripheral features #####
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ==============================================================================
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   [..] 
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Interrupt generation at the end of conversion, end of injected conversion,  
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       and in case of analog watchdog or overrun events
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Single and continuous conversion modes.
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Scan mode for automatic conversion of channel 0 to channel x.
+ARM GAS  /tmp/ccHbw826.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Data alignment with in-built data coherency.
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Channel-wise programmable sampling time.
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) External trigger option with configurable polarity for both regular and 
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       injected conversion.
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Dual/Triple mode (on devices with 2 ADCs or more).
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Configurable DMA data storage in Dual/Triple ADC mode. 
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Configurable delay between conversions in Dual/Triple interleaved mode.
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) ADC conversion type (refer to the datasheets).
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at 
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       slower speed.
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) ADC input range: VREF(minus) = VIN = VREF(plus).
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) DMA request generation during regular channel conversion.
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                      ##### How to use this driver #####
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ==============================================================================
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   [..]
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (##) ADC pins configuration
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****              (+++) Enable the clock for the ADC GPIOs using the following function:
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                    __HAL_RCC_GPIOx_CLK_ENABLE()  
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****              (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() 
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****              (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****              (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****              (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****              (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****              (+++) Configure and enable two DMA streams stream for managing data
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                  transfer from peripheral to memory (output stream)
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****              (+++) Associate the initialized DMA handle to the CRYP DMA handle
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                  using  __HAL_LINKDMA()
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****              (+++) Configure the priority and enable the NVIC for the transfer complete
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                  interrupt on the two DMA Streams. The output stream should have higher
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                  priority than the input stream.
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                        
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     *** Configuration of ADC, groups regular/injected, channels parameters ***
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ==============================================================================
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   [..]
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Configure the ADC parameters (resolution, data alignment, ...)
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       and regular group parameters (conversion trigger, sequencer, ...)
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       using function HAL_ADC_Init().
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Configure the channels for regular group parameters (channel number, 
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       channel rank into sequencer, ..., into regular group)
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       using function HAL_ADC_ConfigChannel().
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Optionally, configure the injected group parameters (conversion trigger, 
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       sequencer, ..., of injected group)
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       and the channels for injected group parameters (channel number, 
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       channel rank into sequencer, ..., into injected group)
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       using function HAL_ADCEx_InjectedConfigChannel().
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Optionally, configure the analog watchdog parameters (channels
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ARM GAS  /tmp/ccHbw826.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Optionally, for devices with several ADC instances: configure the 
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                        *** Execution of ADC conversions ***
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ==============================================================================
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   [..]  
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) ADC driver can be used among three modes: polling, interruption,
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       transfer by DMA.    
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      *** Polling mode IO operation ***
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      =================================
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      [..]    
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) Start the ADC peripheral using HAL_ADC_Start() 
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****            user can specify the value of timeout according to his end application      
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) Stop the ADC peripheral using HAL_ADC_Stop()
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      *** Interrupt mode IO operation ***    
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      ===================================
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      [..]    
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) Start the ADC peripheral using HAL_ADC_Start_IT() 
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can 
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****            add his own code by customization of function pointer HAL_ADC_ConvCpltCallback 
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can 
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****            add his own code by customization of function pointer HAL_ADC_ErrorCallback
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()     
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      *** DMA mode IO operation ***    
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      ==============================
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      [..]    
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the l
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****            of data to be transferred at each end of conversion 
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user 
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****            add his own code by customization of function pointer HAL_ADC_ConvCpltCallback 
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can 
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****            add his own code by customization of function pointer HAL_ADC_ErrorCallback
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                     
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      *** ADC HAL driver macros list ***
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      ============================================= 
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      [..]
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        Below the list of most used macros in ADC HAL driver.
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabl
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register 
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      *** Callback functions ***
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      ==============================
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      [..]
+ARM GAS  /tmp/ccHbw826.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (@) Callback functions must be implemented in user program:
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+@) HAL_ADC_ErrorCallback()
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+@) HAL_ADC_ConvCpltCallback()
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+@) HAL_ADC_ConvHalfCpltCallback
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (@) You can refer to the ADC HAL driver header file for more useful macros 
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       *** Deinitialization of ADC ***
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ==============================================================================
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   [..]
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Disable the ADC interface
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (++) ADC clock can be hard reset and disabled at RCC top level.
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (++) Hard reset of ADC peripherals
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (++) ADC clock disable using the equivalent macro/functions as configuration step.
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                (+++) Example:
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                    Into HAL_ADC_MspDeInit() (recommended code location) or with
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                    other device clock parameters configuration:
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) ADC pins configuration
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Optionally, in case of usage of ADC with interruptions:
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   (#) Optionally, in case of usage of DMA:
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         (++) Deinitialize the DMA using function HAL_DMA_DeInit().
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)   
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       *** Callback registration ***
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ==============================================================================
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     [..]
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      allows the user to configure dynamically the driver callbacks.
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      Use Functions HAL_ADC_RegisterCallback()
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      to register an interrupt callback.
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     [..]
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      Function HAL_ADC_RegisterCallback() allows to register following callbacks:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) ConvCpltCallback               : ADC conversion complete callback
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) ErrorCallback                  : ADC error callback
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) EndOfSamplingCallback          : ADC end of sampling callback
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) MspInitCallback                : ADC Msp Init callback
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) MspDeInitCallback              : ADC Msp DeInit callback
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      This function takes as parameters the HAL peripheral handle, the Callback ID
+ARM GAS  /tmp/ccHbw826.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      and a pointer to the user callback function.
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     [..]
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      weak function.
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     [..]
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      and the Callback ID.
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      This function allows to reset following callbacks:
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) ConvCpltCallback               : ADC conversion complete callback
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) ErrorCallback                  : ADC error callback
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) EndOfSamplingCallback          : ADC end of sampling callback
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) MspInitCallback                : ADC Msp Init callback
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (+) MspDeInitCallback              : ADC Msp DeInit callback
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      [..]
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      all callbacks are set to the corresponding weak functions:
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      Exception done for MspInit and MspDeInit functions that are
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      these callbacks are null (not registered beforehand).
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     [..]
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      [..]
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     [..]
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      Then, the user first registers the MspInit/MspDeInit user callbacks
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      or HAL_ADC_Init() function.
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      [..]
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      not defined, the callback registration feature is not available and all callbacks
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      are set to the corresponding weak functions.
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     @endverbatim
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ******************************************************************************
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */ 
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Includes ------------------------------------------------------------------*/
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #include "stm32f7xx_hal.h"
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ARM GAS  /tmp/ccHbw826.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @addtogroup STM32F7xx_HAL_Driver
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @{
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC ADC
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief ADC driver modules
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @{
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */ 
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #ifdef HAL_ADC_MODULE_ENABLED
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private typedef -----------------------------------------------------------*/
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private define ------------------------------------------------------------*/
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private macro -------------------------------------------------------------*/
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private variables ---------------------------------------------------------*/
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @addtogroup ADC_Private_Functions
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @{
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private function prototypes -----------------------------------------------*/
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_Init(ADC_HandleTypeDef* hadc);
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAError(DMA_HandleTypeDef *hdma);
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @}
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Exported functions --------------------------------------------------------*/
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions ADC Exported Functions
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @{
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions 
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  *  @brief    Initialization and Configuration functions 
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  *
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @verbatim    
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  ===============================================================================
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****               ##### Initialization and de-initialization functions #####
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  ===============================================================================
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     [..]  This section provides functions allowing to:
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Initialize and configure the ADC. 
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) De-initialize the ADC. 
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****          
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @endverbatim
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @{
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Initializes the ADCx peripheral according to the specified parameters 
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         in the ADC_InitStruct and initializes the ADC MSP.
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *           
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @note   This function is used to configure the global features of the ADC ( 
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the rest of the configuration parameters are specific to the regular
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         channels group (scan mode activation, continuous mode activation,
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         External trigger source and edge, DMA continuous request after the  
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         last transfer and End of conversion selection).
+ARM GAS  /tmp/ccHbw826.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *             
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.  
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check ADC handle */
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(hadc == NULL)
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     return HAL_ERROR;
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(hadc->State == HAL_ADC_STATE_RESET)
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Init the ADC Callback settings */
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak 
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak 
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak 
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak 
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak 
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (hadc->MspInitCallback == NULL)
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Init the low level hardware */
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->MspInitCallback(hadc);
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Init the low level hardware */
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     HAL_ADC_MspInit(hadc);
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Initialize ADC error code */
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_CLEAR_ERRORCODE(hadc);
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ARM GAS  /tmp/ccHbw826.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Allocate lock resource and initialize it */
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Lock = HAL_UNLOCKED;
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Configuration of ADC parameters if previous preliminary actions are      */ 
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* correctly completed.                                                     */
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC state */
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_BUSY_INTERNAL);
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC parameters */
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_Init(hadc);
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC error code to none */
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_CLEAR_ERRORCODE(hadc);
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set the ADC state */
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_BUSY_INTERNAL,
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_READY);
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     tmp_hal_status = HAL_ERROR;
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Release Lock */
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return function status */
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return tmp_hal_status;
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Deinitializes the ADCx peripheral registers to their default reset values. 
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.  
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check ADC handle */
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(hadc == NULL)
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     return HAL_ERROR;
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set ADC state */
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+ARM GAS  /tmp/ccHbw826.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Stop potential conversion on going, on regular and injected groups */
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Disable ADC peripheral */
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_ADC_DISABLE(hadc);
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Configuration of ADC parameters if previous preliminary actions are      */ 
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* correctly completed.                                                     */
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if (hadc->MspDeInitCallback == NULL)
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* DeInit the low level hardware: RCC clock, NVIC */
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->MspDeInitCallback(hadc);
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* DeInit the low level hardware: RCC clock, NVIC */
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_ADC_MspDeInit(hadc);
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC error code to none */
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_CLEAR_ERRORCODE(hadc);
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC state */
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->State = HAL_ADC_STATE_RESET;
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process unlocked */
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return function status */
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return tmp_hal_status;
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Initializes the ADC MSP.
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.  
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval None
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   UNUSED(hadc);
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****             the HAL_ADC_MspInit could be implemented in the user file
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****    */ 
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  DeInitializes the ADC MSP.
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.  
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval None
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ARM GAS  /tmp/ccHbw826.s 			page 10
+
+
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   UNUSED(hadc);
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****             the HAL_ADC_MspDeInit could be implemented in the user file
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****    */ 
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Register a User ADC Callback
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         To be used instead of the weak predefined callback
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *                the configuration information for the specified ADC.
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  CallbackID ID of the callback to be registered
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         This parameter can be one of the following values:
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer call
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complet
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue over
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  pCallback pointer to the Callback function
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef Callb
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if (pCallback == NULL)
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Update the error code */
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     return HAL_ERROR;
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     switch (CallbackID)
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->ConvCpltCallback = pCallback;
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_CONVERSION_HALF_CB_ID :
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->ConvHalfCpltCallback = pCallback;
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->LevelOutOfWindowCallback = pCallback;
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_ERROR_CB_ID :
+ARM GAS  /tmp/ccHbw826.s 			page 11
+
+
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->ErrorCallback = pCallback;
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->InjectedConvCpltCallback = pCallback;
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_MSPINIT_CB_ID :
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->MspInitCallback = pCallback;
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_MSPDEINIT_CB_ID :
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->MspDeInitCallback = pCallback;
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       default :
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Update the error code */
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Return error status */
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         status = HAL_ERROR;
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else if (HAL_ADC_STATE_RESET == hadc->State)
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     switch (CallbackID)
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_MSPINIT_CB_ID :
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->MspInitCallback = pCallback;
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_MSPDEINIT_CB_ID :
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->MspDeInitCallback = pCallback;
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       default :
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Update the error code */
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Return error status */
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         status = HAL_ERROR;
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Update the error code */
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Return error status */
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     status =  HAL_ERROR;
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return status;
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ARM GAS  /tmp/ccHbw826.s 			page 12
+
+
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Unregister a ADC Callback
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         ADC callback is redirected to the weak predefined callback
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *                the configuration information for the specified ADC.
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  CallbackID ID of the callback to be unregistered
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         This parameter can be one of the following values:
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer call
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complet
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue over
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef Cal
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     switch (CallbackID)
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_CONVERSION_HALF_CB_ID :
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_ERROR_CB_ID :
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_MSPINIT_CB_ID :
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_MSPDEINIT_CB_ID :
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       default :
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Update the error code */
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ARM GAS  /tmp/ccHbw826.s 			page 13
+
+
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Return error status */
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         status =  HAL_ERROR;
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else if (HAL_ADC_STATE_RESET == hadc->State)
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     switch (CallbackID)
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_MSPINIT_CB_ID :
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit          
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       case HAL_ADC_MSPDEINIT_CB_ID :
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit        
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       default :
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Update the error code */
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Return error status */
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         status =  HAL_ERROR;
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         break;
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Update the error code */
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Return error status */
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     status =  HAL_ERROR;
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return status;
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @}
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  *  @brief    IO operation functions 
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  *
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @verbatim   
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  ===============================================================================
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****              ##### IO operation functions #####
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  ===============================================================================  
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     [..]  This section provides functions allowing to:
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Start conversion of regular channel.
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Stop conversion of regular channel.
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Start conversion of regular channel and enable interrupt.
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Stop conversion of regular channel and disable interrupt.
+ARM GAS  /tmp/ccHbw826.s 			page 14
+
+
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Start conversion of regular channel and enable DMA transfer.
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Stop conversion of regular channel and disable DMA transfer.
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Handle ADC interrupt request. 
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @endverbatim
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @{
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Enables ADC and starts conversion of the regular channels.
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process locked */
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_LOCK(hadc);
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Enable the ADC peripheral */
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check if ADC peripheral is disabled in order to enable it and wait during 
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   Tstab time the ADC's stabilization */
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Enable the Peripheral */
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_ENABLE(hadc);
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Delay for ADC stabilization time */
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Compute number of CPU cycles to wait for */
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       counter--;
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Start conversion if ADC is effectively enabled */
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC state                                                          */
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* - Clear state bitfield related to regular group conversion results     */
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* - Set state bitfield related to regular group operation                */
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY);
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* If conversions on group regular are also triggering group injected,    */
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* update ADC state.                                                      */
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+ARM GAS  /tmp/ccHbw826.s 			page 15
+
+
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* State machine update: Check if an injected conversion is ongoing */
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Reset ADC error code fields related to conversions on group regular */
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     else
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Reset ADC all error code fields */
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       ADC_CLEAR_ERRORCODE(hadc);
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Process unlocked */
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Unlock before starting ADC conversions: in case of potential           */
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* interruption, to let the process to ADC IRQ Handler.                   */
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_UNLOCK(hadc);
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear regular group conversion flag and overrun flag */
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* (To ensure of no unknown state from potential previous ADC operations) */
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Check if Multimode enabled */
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* if no external trigger present enable software conversion of regular channels */
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Enable the selected ADC software conversion for regular group */
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     else
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* if instance of handle correspond to ADC1 and  no external trigger present enable software 
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Enable the selected ADC software conversion for regular group */
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* if dual mode is selected, ADC3 works independently. */
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* check if the mode selected is not triple */
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* if instance of handle correspond to ADC3 and no external trigger present enable software
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           /* Enable the selected ADC software conversion for regular group */
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ARM GAS  /tmp/ccHbw826.s 			page 16
+
+
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Update ADC state machine to error */
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC error code to ADC IP internal error */
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return function status */
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return HAL_OK;
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Disables ADC and stop conversion of regular channels.
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * 
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @note   Caution: This function will stop also injected channels.  
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status.
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process locked */
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_LOCK(hadc);
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Stop potential conversion on going, on regular and injected groups */
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Disable ADC peripheral */
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_ADC_DISABLE(hadc);
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check if ADC is effectively disabled */
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC state */
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_READY);
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process unlocked */
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return function status */
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return HAL_OK;
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Poll for regular conversion complete
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         conversion) are cleared by this function.
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @note   This function cannot be used in a particular setup: ADC configured 
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         in DMA mode and polling for end of each conversion (ADC init
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         In this case, DMA resets the flag EOC and polling cannot be
+ARM GAS  /tmp/ccHbw826.s 			page 17
+
+
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         performed on each conversion. Nevertheless, polling can still 
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         be performed on the complete sequence.
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  Timeout Timeout value in millisecond.  
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tickstart = 0;
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Verification that ADC configuration is compliant with polling for      */
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* each conversion:                                                       */
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* several ranks and polling for end of each conversion.                  */
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* For code simplicity sake, this particular case is generalized to       */
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* ADC configured in DMA mode and polling for end of each conversion.     */
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Update ADC state machine to error */
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Process unlocked */
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_UNLOCK(hadc);
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     return HAL_ERROR;
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Get tick */ 
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tickstart = HAL_GetTick();
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check End of conversion flag */
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Check if timeout is disabled (set to infinite wait) */
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if(Timeout != HAL_MAX_DELAY)
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* New check to avoid false timeout detection in case of preemption */
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           /* Update ADC state machine to timeout */
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           /* Process unlocked */
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           __HAL_UNLOCK(hadc);
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           return HAL_TIMEOUT;
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Clear regular group conversion flag */
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+ARM GAS  /tmp/ccHbw826.s 			page 18
+
+
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Update ADC state machine */
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Determine whether any further conversion upcoming on group regular       */
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* by external trigger, continuous mode or scan sequence on going.          */
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Note: On STM32F7, there is no independent flag of end of sequence.       */
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /*       The test of scan sequence on going is done either with scan        */
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /*       sequence disabled or with end of conversion flag set to            */
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /*       of end of sequence.                                                */
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC state */
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     { 
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return ADC state */
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return HAL_OK;
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Poll for conversion event
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  EventType the ADC event type.
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *          This parameter can be one of the following values:
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *            @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *            @arg ADC_OVR_EVENT: ADC Overrun event.
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  Timeout Timeout value in millisecond.   
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeou
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tickstart = 0;
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EVENT_TYPE(EventType));
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Get tick */
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tickstart = HAL_GetTick();
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check selected event flag */
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Check for the Timeout */
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if(Timeout != HAL_MAX_DELAY)
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ARM GAS  /tmp/ccHbw826.s 			page 19
+
+
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* New check to avoid false timeout detection in case of preemption */
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         if(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           /* Update ADC state machine to timeout */
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           /* Process unlocked */
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           __HAL_UNLOCK(hadc);
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           return HAL_TIMEOUT;
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Analog watchdog (level out of window) event */
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(EventType == ADC_AWD_EVENT)
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC state */
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear ADC analog watchdog flag */
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Overrun event */
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC state */
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC error code to overrun */
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear ADC overrun flag */
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return ADC state */
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return HAL_OK;
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Enables the interrupt and starts ADC conversion of regular channels.
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status.
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process locked */
+ARM GAS  /tmp/ccHbw826.s 			page 20
+
+
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_LOCK(hadc);
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Enable the ADC peripheral */
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check if ADC peripheral is disabled in order to enable it and wait during 
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      Tstab time the ADC's stabilization */
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Enable the Peripheral */
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_ENABLE(hadc);
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Delay for ADC stabilization time */
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Compute number of CPU cycles to wait for */
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       counter--;
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Start conversion if ADC is effectively enabled */
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC state                                                          */
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* - Clear state bitfield related to regular group conversion results     */
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* - Set state bitfield related to regular group operation                */
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_STATE_CLR_SET(hadc->State,
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY);
+1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* If conversions on group regular are also triggering group injected,    */
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* update ADC state.                                                      */
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* State machine update: Check if an injected conversion is ongoing */
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Reset ADC error code fields related to conversions on group regular */
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     else
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Reset ADC all error code fields */
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       ADC_CLEAR_ERRORCODE(hadc);
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Process unlocked */
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Unlock before starting ADC conversions: in case of potential           */
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* interruption, to let the process to ADC IRQ Handler.                   */
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_UNLOCK(hadc);
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear regular group conversion flag and overrun flag */
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* (To ensure of no unknown state from potential previous ADC operations) */
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ARM GAS  /tmp/ccHbw826.s 			page 21
+
+
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Enable end of conversion interrupt for regular group */
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Check if Multimode enabled */
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* if no external trigger present enable software conversion of regular channels */
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Enable the selected ADC software conversion for regular group */
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     else
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* if instance of handle correspond to ADC1 and  no external trigger present enable software 
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Enable the selected ADC software conversion for regular group */
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* if dual mode is selected, ADC3 works independently. */
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* check if the mode selected is not triple */
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* if instance of handle correspond to ADC3 and  no external trigger present enable softwar
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           /* Enable the selected ADC software conversion for regular group */
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       } 
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Update ADC state machine to error */
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC error code to ADC IP internal error */
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return function status */
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return HAL_OK;
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Disables the interrupt and stop ADC conversion of regular channels.
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * 
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @note   Caution: This function will stop also injected channels.  
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status.
+1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ARM GAS  /tmp/ccHbw826.s 			page 22
+
+
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process locked */
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_LOCK(hadc);
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Stop potential conversion on going, on regular and injected groups */
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Disable ADC peripheral */
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_ADC_DISABLE(hadc);
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check if ADC is effectively disabled */
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   	/* Disable ADC end of conversion interrupt for regular group */
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC state */
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_STATE_CLR_SET(hadc->State,
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_READY);
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process unlocked */
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return function status */
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return HAL_OK;
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Handles ADC interrupt request  
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval None
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tmp1 = 0, tmp2 = 0;
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tmp_sr = hadc->Instance->SR;
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tmp_cr1 = hadc->Instance->CR1;
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp1 = tmp_sr & ADC_FLAG_EOC;
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp2 = tmp_cr1 & ADC_IT_EOC;
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check End of conversion flag for regular channels */
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(tmp1 && tmp2)
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Update state machine on conversion status if not in error state */
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ARM GAS  /tmp/ccHbw826.s 			page 23
+
+
+1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Set ADC state */
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Determine whether any further conversion upcoming on group regular   */
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* by external trigger, continuous mode or scan sequence on going.      */
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Note: On STM32F7, there is no independent flag of end of sequence.   */
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /*       The test of scan sequence on going is done either with scan    */
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /*       sequence disabled or with end of conversion flag set to        */
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /*       of end of sequence.                                            */
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Disable ADC end of single conversion interrupt on group regular */
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* by overrun IRQ process below.                                      */
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Set ADC state */
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Conversion complete callback */ 
+1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->ConvCpltCallback(hadc);
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     HAL_ADC_ConvCpltCallback(hadc);
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear regular group conversion flag */
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp1 = tmp_sr & ADC_FLAG_JEOC;
+1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp2 = tmp_cr1 & ADC_IT_JEOC;
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check End of conversion flag for injected channels */
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(tmp1 && tmp2)
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Update state machine on conversion status if not in error state */
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Set ADC state */
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Determine whether any further conversion upcoming on group injected  */
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* by external trigger, scan sequence on going or by automatic injected */
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* conversion from group regular (same conditions as group regular      */
+ARM GAS  /tmp/ccHbw826.s 			page 24
+
+
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* interruption disabling above).                                       */
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE))))
+1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Disable ADC end of single conversion interrupt on group injected */
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Set ADC state */
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
+1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       { 
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Conversion complete callback */ 
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       hadc->InjectedConvCpltCallback(hadc);
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_ADCEx_InjectedConvCpltCallback(hadc);
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear injected group conversion flag */
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
+1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp1 = tmp_sr & ADC_FLAG_AWD;
+1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp2 = tmp_cr1 & ADC_IT_AWD;
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check Analog watchdog flag */
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(tmp1 && tmp2)
+1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
+1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Set ADC state */
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Level out of window callback */ 
+1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       hadc->LevelOutOfWindowCallback(hadc);
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_ADC_LevelOutOfWindowCallback(hadc);
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Clear the ADC analog watchdog flag */
+1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp1 = tmp_sr & ADC_FLAG_OVR;
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp2 = tmp_cr1 & ADC_IT_OVR;
+1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check Overrun flag */
+ARM GAS  /tmp/ccHbw826.s 			page 25
+
+
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(tmp1 && tmp2)
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Note: On STM32F7, ADC overrun can be set through other parameters    */
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /*       refer to description of parameter "EOCSelection" for more      */
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /*       details.                                                       */
+1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC error code to overrun */
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear ADC overrun flag */
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Error callback */ 
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       hadc->ErrorCallback(hadc);
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_ADC_ErrorCallback(hadc);
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear the Overrun flag */
+1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC periphera
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  pData The destination Buffer address.
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  Length The length of data to be transferred from ADC peripheral to memory.
+1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status
+1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
+1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process locked */
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_LOCK(hadc);
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Enable the ADC peripheral */
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check if ADC peripheral is disabled in order to enable it and wait during 
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      Tstab time the ADC's stabilization */
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Enable the Peripheral */
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_ENABLE(hadc);
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Delay for ADC stabilization time */
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Compute number of CPU cycles to wait for */
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       counter--;
+ARM GAS  /tmp/ccHbw826.s 			page 26
+
+
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Start conversion if ADC is effectively enabled */
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC state                                                          */
+1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* - Clear state bitfield related to regular group conversion results     */
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* - Set state bitfield related to regular group operation                */
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_STATE_CLR_SET(hadc->State,
+1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY);
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* If conversions on group regular are also triggering group injected,    */
+1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* update ADC state.                                                      */
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* State machine update: Check if an injected conversion is ongoing */
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Reset ADC error code fields related to conversions on group regular */
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     else
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Reset ADC all error code fields */
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       ADC_CLEAR_ERRORCODE(hadc);
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Process unlocked */
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Unlock before starting ADC conversions: in case of potential           */
+1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* interruption, to let the process to ADC IRQ Handler.                   */
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_UNLOCK(hadc);   
+1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set the DMA transfer complete callback */
+1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set the DMA half transfer complete callback */
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set the DMA error callback */
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* start (in case of SW start):                                           */
+1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear regular group conversion flag and overrun flag */
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* (To ensure of no unknown state from potential previous ADC operations) */
+1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Enable ADC overrun interrupt */
+1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ARM GAS  /tmp/ccHbw826.s 			page 27
+
+
+1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Enable ADC DMA mode */
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR2 |= ADC_CR2_DMA;
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Start the DMA channel */
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Check if Multimode enabled */
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* if no external trigger present enable software conversion of regular channels */
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Enable the selected ADC software conversion for regular group */
+1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     else
+1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* if instance of handle correspond to ADC1 and  no external trigger present enable software 
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Enable the selected ADC software conversion for regular group */
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* if dual mode is selected, ADC3 works independently. */
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* check if the mode selected is not triple */
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
+1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* if instance of handle correspond to ADC3 and  no external trigger present enable softwar
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           /* Enable the selected ADC software conversion for regular group */
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else
+1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Update ADC state machine to error */
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC error code to ADC IP internal error */
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return function status */
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return HAL_OK;
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral    
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+ARM GAS  /tmp/ccHbw826.s 			page 28
+
+
+1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process locked */
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_LOCK(hadc);
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Stop potential conversion on going, on regular and injected groups */
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Disable ADC peripheral */
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_ADC_DISABLE(hadc);
+1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check if ADC is effectively disabled */
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Disable the selected ADC DMA mode */
+1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR2 &= ~ADC_CR2_DMA;
+1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* DMA transfer is on going)                                              */
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Check if DMA channel effectively disabled */
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if (tmp_hal_status != HAL_OK)
+1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         /* Update ADC state machine to error */
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Disable ADC overrun interrupt */
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC state */
+1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC_STATE_CLR_SET(hadc->State,
+1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_READY);
+1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process unlocked */
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return function status */
+1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return tmp_hal_status;
+1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Gets the converted value from data register of regular channel.
+1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval Converted value
+1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {       
+ARM GAS  /tmp/ccHbw826.s 			page 29
+
+
+1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return the selected ADC converted value */ 
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return hadc->Instance->DR;
+1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Regular conversion complete callback in non blocking mode 
+1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval None
+1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   UNUSED(hadc);
+1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****             the HAL_ADC_ConvCpltCallback could be implemented in the user file
+1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****    */
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Regular conversion half DMA transfer callback in non blocking mode 
+1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval None
+1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   UNUSED(hadc);
+1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****             the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
+1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****    */
+1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Analog watchdog callback in non blocking mode 
+1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval None
+1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   UNUSED(hadc);
+1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****             the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
+1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****    */
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Error ADC callback.
+1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @note   In case of error due to overrun when using ADC with DMA transfer 
+1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         - If needed, restart a new ADC conversion using function
+1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *           "HAL_ADC_Start_DMA()"
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *           (this function is also clearing overrun flag)
+ARM GAS  /tmp/ccHbw826.s 			page 30
+
+
+1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval None
+1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   UNUSED(hadc);
+1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****             the HAL_ADC_ErrorCallback could be implemented in the user file
+1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****    */
+1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @}
+1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  *  @brief   	Peripheral Control functions 
+1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  *
+1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @verbatim   
+1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  ===============================================================================
+1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****              ##### Peripheral Control functions #####
+1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  ===============================================================================  
+1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     [..]  This section provides functions allowing to:
+1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Configure regular channels. 
+1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Configure injected channels.
+1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Configure multimode.
+1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Configure the analog watch dog.
+1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @endverbatim
+1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @{
+1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /**
+1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Configures for the selected ADC regular channel its corresponding
+1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         rank in the sequencer and its sample time.
+1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  sConfig ADC configuration structure. 
+1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status
+1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process locked */
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_LOCK(hadc);
+1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE))
+1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ARM GAS  /tmp/ccHbw826.s 			page 31
+
+
+1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear the old sample time */
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
+1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Set the new sample time */
+1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     else
+1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Set the new sample time */
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else /* ADC_Channel include in ADC_Channel_[0..9] */
+1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear the old sample time */
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
+1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set the new sample time */
+1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
+1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* For Rank 1 to 6 */
+1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if (sConfig->Rank < 7)
+1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear the old SQx bits for the selected rank */
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
+1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set the SQx bits for the selected rank */
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* For Rank 7 to 12 */
+1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else if (sConfig->Rank < 13)
+1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear the old SQx bits for the selected rank */
+1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set the SQx bits for the selected rank */
+1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
+1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* For Rank 13 to 16 */
+1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else
+1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Clear the old SQx bits for the selected rank */
+1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
+1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set the SQx bits for the selected rank */
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* if no internal channel selected */
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE))
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Disable the VBAT & TSVREFE channel*/
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
+1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ARM GAS  /tmp/ccHbw826.s 			page 32
+
+
+1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* if ADC1 Channel_18 is selected enable VBAT Channel */
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
+1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Disable the TEMPSENSOR channel as it is multiplixed with the VBAT channel */
+1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC->CCR &= ~ADC_CCR_TSVREFE;
+1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Enable the VBAT channel*/
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC->CCR |= ADC_CCR_VBATE;
+1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VRE
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channe
+1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Disable the VBAT channel as it is multiplixed with TEMPSENSOR channel */
+1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC->CCR &= ~ADC_CCR_VBATE;
+1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Enable the TSVREFE channel*/
+1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     ADC->CCR |= ADC_CCR_TSVREFE;
+1761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+1764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Delay for temperature sensor stabilization time */
+1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Compute number of CPU cycles to wait for */
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       while(counter != 0)
+1768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         counter--;
+1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+1772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process unlocked */
+1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+1776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return function status */
+1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return HAL_OK;
+1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Configures the analog watchdog.
+1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @note   Analog watchdog thresholds can be modified while ADC conversion
+1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         is on going.
+1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         In this case, some constraints must be taken into account:
+1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the programmed threshold values are effective from the next
+1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         ADC EOC (end of unitary conversion).
+1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         Considering that registers write delay may happen due to
+1789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         bus activity, this might cause an uncertainty on the
+1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         effective timing of the new programmed threshold values.
+1791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  AnalogWDGConfig  pointer to an ADC_AnalogWDGConfTypeDef structure 
+1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         that contains the configuration information of ADC analog watchdog.
+1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL status	  
+1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* Analog
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ARM GAS  /tmp/ccHbw826.s 			page 33
+
+
+1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #ifdef USE_FULL_ASSERT  
+1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tmp = 0;
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_FULL_ASSERT  */  
+1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
+1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #ifdef USE_FULL_ASSERT  
+1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp = ADC_GET_RESOLUTION(hadc);
+1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
+1811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
+1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_FULL_ASSERT  */
+1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process locked */
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_LOCK(hadc);
+1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(AnalogWDGConfig->ITMode == ENABLE)
+1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Enable the ADC Analog watchdog interrupt */
+1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Disable the ADC Analog watchdog interrupt */
+1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
+1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Clear AWDEN, JAWDEN and AWDSGL bits */
+1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR1 &=  ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
+1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set the analog watchdog enable mode */
+1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
+1833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set the high threshold */
+1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
+1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set the low threshold */
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
+1839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Clear the Analog watchdog channel select bits */
+1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
+1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set the Analog watchdog channel */
+1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
+1845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Process unlocked */
+1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __HAL_UNLOCK(hadc);
+1848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return function status */
+1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return HAL_OK;
+1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @}
+1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+ARM GAS  /tmp/ccHbw826.s 			page 34
+
+
+1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  *  @brief   ADC Peripheral State functions 
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  *
+1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @verbatim   
+1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  ===============================================================================
+1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****             ##### Peripheral State and errors functions #####
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****  ===============================================================================  
+1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     [..]
+1865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     This subsection provides functions allowing to
+1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Check the ADC state
+1867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       (+) Check the ADC Error
+1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****          
+1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @endverbatim
+1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @{
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  return the ADC state
+1875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval HAL state
+1878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return ADC state */
+1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return hadc->State;
+1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Return the ADC error code
+1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.
+1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval ADC Error Code
+1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return hadc->ErrorCode;
+1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+1895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @}
+1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @}
+1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private functions ---------------------------------------------------------*/
+1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Private_Functions ADC Private Functions
+1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @{
+1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  Initializes the ADCx peripheral according to the specified parameters 
+1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         in the ADC_InitStruct without initializing the ADC MSP.       
+ARM GAS  /tmp/ccHbw826.s 			page 35
+
+
+1913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *         the configuration information for the specified ADC.  
+1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval None
+1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_Init(ADC_HandleTypeDef* hadc)
+1918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+  28              		.loc 1 1918 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set ADC parameters */
+1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set the ADC clock prescaler */
+1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ADC->CCR &= ~(ADC_CCR_ADCPRE);
+  33              		.loc 1 1921 3 view .LVU1
+  34              		.loc 1 1921 12 is_stmt 0 view .LVU2
+  35 0000 4A4B     		ldr	r3, .L6
+  36 0002 5A68     		ldr	r2, [r3, #4]
+  37 0004 22F44032 		bic	r2, r2, #196608
+  38 0008 5A60     		str	r2, [r3, #4]
+1922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ADC->CCR |=  hadc->Init.ClockPrescaler;
+  39              		.loc 1 1922 3 is_stmt 1 view .LVU3
+  40              		.loc 1 1922 12 is_stmt 0 view .LVU4
+  41 000a 5A68     		ldr	r2, [r3, #4]
+  42              		.loc 1 1922 26 view .LVU5
+  43 000c 4168     		ldr	r1, [r0, #4]
+  44              		.loc 1 1922 12 view .LVU6
+  45 000e 0A43     		orrs	r2, r2, r1
+  46 0010 5A60     		str	r2, [r3, #4]
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set ADC scan mode */
+1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
+  47              		.loc 1 1925 3 is_stmt 1 view .LVU7
+  48              		.loc 1 1925 7 is_stmt 0 view .LVU8
+  49 0012 0268     		ldr	r2, [r0]
+  50              		.loc 1 1925 23 view .LVU9
+  51 0014 5368     		ldr	r3, [r2, #4]
+  52 0016 23F48073 		bic	r3, r3, #256
+  53 001a 5360     		str	r3, [r2, #4]
+1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR1 |=  ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
+  54              		.loc 1 1926 3 is_stmt 1 view .LVU10
+  55              		.loc 1 1926 7 is_stmt 0 view .LVU11
+  56 001c 0268     		ldr	r2, [r0]
+  57              		.loc 1 1926 23 view .LVU12
+  58 001e 5368     		ldr	r3, [r2, #4]
+  59              		.loc 1 1926 27 view .LVU13
+  60 0020 0169     		ldr	r1, [r0, #16]
+  61              		.loc 1 1926 23 view .LVU14
+  62 0022 43EA0123 		orr	r3, r3, r1, lsl #8
+  63 0026 5360     		str	r3, [r2, #4]
+1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set ADC resolution */
+1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR1 &= ~(ADC_CR1_RES);
+  64              		.loc 1 1929 3 is_stmt 1 view .LVU15
+  65              		.loc 1 1929 7 is_stmt 0 view .LVU16
+  66 0028 0268     		ldr	r2, [r0]
+  67              		.loc 1 1929 23 view .LVU17
+ARM GAS  /tmp/ccHbw826.s 			page 36
+
+
+  68 002a 5368     		ldr	r3, [r2, #4]
+  69 002c 23F04073 		bic	r3, r3, #50331648
+  70 0030 5360     		str	r3, [r2, #4]
+1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR1 |=  hadc->Init.Resolution;
+  71              		.loc 1 1930 3 is_stmt 1 view .LVU18
+  72              		.loc 1 1930 7 is_stmt 0 view .LVU19
+  73 0032 0268     		ldr	r2, [r0]
+  74              		.loc 1 1930 23 view .LVU20
+  75 0034 5368     		ldr	r3, [r2, #4]
+  76              		.loc 1 1930 37 view .LVU21
+  77 0036 8168     		ldr	r1, [r0, #8]
+  78              		.loc 1 1930 23 view .LVU22
+  79 0038 0B43     		orrs	r3, r3, r1
+  80 003a 5360     		str	r3, [r2, #4]
+1931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set ADC data alignment */
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
+  81              		.loc 1 1933 3 is_stmt 1 view .LVU23
+  82              		.loc 1 1933 7 is_stmt 0 view .LVU24
+  83 003c 0268     		ldr	r2, [r0]
+  84              		.loc 1 1933 23 view .LVU25
+  85 003e 9368     		ldr	r3, [r2, #8]
+  86 0040 23F40063 		bic	r3, r3, #2048
+  87 0044 9360     		str	r3, [r2, #8]
+1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR2 |= hadc->Init.DataAlign;
+  88              		.loc 1 1934 3 is_stmt 1 view .LVU26
+  89              		.loc 1 1934 7 is_stmt 0 view .LVU27
+  90 0046 0268     		ldr	r2, [r0]
+  91              		.loc 1 1934 23 view .LVU28
+  92 0048 9368     		ldr	r3, [r2, #8]
+  93              		.loc 1 1934 36 view .LVU29
+  94 004a C168     		ldr	r1, [r0, #12]
+  95              		.loc 1 1934 23 view .LVU30
+  96 004c 0B43     		orrs	r3, r3, r1
+  97 004e 9360     		str	r3, [r2, #8]
+1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Enable external trigger if trigger selection is different of software  */
+1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* start.                                                                 */
+1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Note: This configuration keeps the hardware feature of parameter       */
+1939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /*       software start.                                                  */
+1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+  98              		.loc 1 1941 3 is_stmt 1 view .LVU31
+  99              		.loc 1 1941 16 is_stmt 0 view .LVU32
+ 100 0050 826A     		ldr	r2, [r0, #40]
+ 101              		.loc 1 1941 5 view .LVU33
+ 102 0052 374B     		ldr	r3, .L6+4
+ 103 0054 9A42     		cmp	r2, r3
+ 104 0056 57D0     		beq	.L2
+1942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Select external trigger to start conversion */
+1944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+ 105              		.loc 1 1944 5 is_stmt 1 view .LVU34
+ 106              		.loc 1 1944 9 is_stmt 0 view .LVU35
+ 107 0058 0268     		ldr	r2, [r0]
+ 108              		.loc 1 1944 25 view .LVU36
+ 109 005a 9368     		ldr	r3, [r2, #8]
+ARM GAS  /tmp/ccHbw826.s 			page 37
+
+
+ 110 005c 23F07063 		bic	r3, r3, #251658240
+ 111 0060 9360     		str	r3, [r2, #8]
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
+ 112              		.loc 1 1945 5 is_stmt 1 view .LVU37
+ 113              		.loc 1 1945 9 is_stmt 0 view .LVU38
+ 114 0062 0268     		ldr	r2, [r0]
+ 115              		.loc 1 1945 25 view .LVU39
+ 116 0064 9368     		ldr	r3, [r2, #8]
+ 117              		.loc 1 1945 38 view .LVU40
+ 118 0066 816A     		ldr	r1, [r0, #40]
+ 119              		.loc 1 1945 25 view .LVU41
+ 120 0068 0B43     		orrs	r3, r3, r1
+ 121 006a 9360     		str	r3, [r2, #8]
+1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Select external trigger polarity */
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ 122              		.loc 1 1948 5 is_stmt 1 view .LVU42
+ 123              		.loc 1 1948 9 is_stmt 0 view .LVU43
+ 124 006c 0268     		ldr	r2, [r0]
+ 125              		.loc 1 1948 25 view .LVU44
+ 126 006e 9368     		ldr	r3, [r2, #8]
+ 127 0070 23F04053 		bic	r3, r3, #805306368
+ 128 0074 9360     		str	r3, [r2, #8]
+1949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
+ 129              		.loc 1 1949 5 is_stmt 1 view .LVU45
+ 130              		.loc 1 1949 9 is_stmt 0 view .LVU46
+ 131 0076 0268     		ldr	r2, [r0]
+ 132              		.loc 1 1949 25 view .LVU47
+ 133 0078 9368     		ldr	r3, [r2, #8]
+ 134              		.loc 1 1949 38 view .LVU48
+ 135 007a C16A     		ldr	r1, [r0, #44]
+ 136              		.loc 1 1949 25 view .LVU49
+ 137 007c 0B43     		orrs	r3, r3, r1
+ 138 007e 9360     		str	r3, [r2, #8]
+ 139              	.L3:
+1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else
+1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Reset the external trigger */
+1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Enable or disable ADC continuous conversion mode */
+1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
+ 140              		.loc 1 1959 3 is_stmt 1 view .LVU50
+ 141              		.loc 1 1959 7 is_stmt 0 view .LVU51
+ 142 0080 0268     		ldr	r2, [r0]
+ 143              		.loc 1 1959 23 view .LVU52
+ 144 0082 9368     		ldr	r3, [r2, #8]
+ 145 0084 23F00203 		bic	r3, r3, #2
+ 146 0088 9360     		str	r3, [r2, #8]
+1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
+ 147              		.loc 1 1960 3 is_stmt 1 view .LVU53
+ 148              		.loc 1 1960 7 is_stmt 0 view .LVU54
+ 149 008a 0268     		ldr	r2, [r0]
+ 150              		.loc 1 1960 23 view .LVU55
+ARM GAS  /tmp/ccHbw826.s 			page 38
+
+
+ 151 008c 9368     		ldr	r3, [r2, #8]
+ 152              		.loc 1 1960 26 view .LVU56
+ 153 008e 8169     		ldr	r1, [r0, #24]
+ 154              		.loc 1 1960 23 view .LVU57
+ 155 0090 43EA4103 		orr	r3, r3, r1, lsl #1
+ 156 0094 9360     		str	r3, [r2, #8]
+1961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if(hadc->Init.DiscontinuousConvMode != DISABLE)
+ 157              		.loc 1 1962 3 is_stmt 1 view .LVU58
+ 158              		.loc 1 1962 16 is_stmt 0 view .LVU59
+ 159 0096 90F82030 		ldrb	r3, [r0, #32]	@ zero_extendqisi2
+ 160              		.loc 1 1962 5 view .LVU60
+ 161 009a 002B     		cmp	r3, #0
+ 162 009c 3FD0     		beq	.L4
+1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
+ 163              		.loc 1 1964 5 is_stmt 1 view .LVU61
+1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Enable the selected ADC regular discontinuous mode */
+1967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
+ 164              		.loc 1 1967 5 view .LVU62
+ 165              		.loc 1 1967 9 is_stmt 0 view .LVU63
+ 166 009e 0268     		ldr	r2, [r0]
+ 167              		.loc 1 1967 25 view .LVU64
+ 168 00a0 5368     		ldr	r3, [r2, #4]
+ 169 00a2 43F40063 		orr	r3, r3, #2048
+ 170 00a6 5360     		str	r3, [r2, #4]
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set the number of channels to be converted in discontinuous mode */
+1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
+ 171              		.loc 1 1970 5 is_stmt 1 view .LVU65
+ 172              		.loc 1 1970 9 is_stmt 0 view .LVU66
+ 173 00a8 0268     		ldr	r2, [r0]
+ 174              		.loc 1 1970 25 view .LVU67
+ 175 00aa 5368     		ldr	r3, [r2, #4]
+ 176 00ac 23F46043 		bic	r3, r3, #57344
+ 177 00b0 5360     		str	r3, [r2, #4]
+1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR1 |=  ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
+ 178              		.loc 1 1971 5 is_stmt 1 view .LVU68
+ 179              		.loc 1 1971 9 is_stmt 0 view .LVU69
+ 180 00b2 0168     		ldr	r1, [r0]
+ 181              		.loc 1 1971 25 view .LVU70
+ 182 00b4 4B68     		ldr	r3, [r1, #4]
+ 183              		.loc 1 1971 29 view .LVU71
+ 184 00b6 426A     		ldr	r2, [r0, #36]
+ 185 00b8 013A     		subs	r2, r2, #1
+ 186              		.loc 1 1971 25 view .LVU72
+ 187 00ba 43EA4233 		orr	r3, r3, r2, lsl #13
+ 188 00be 4B60     		str	r3, [r1, #4]
+ 189              	.L5:
+1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else
+1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Disable the selected ADC regular discontinuous mode */
+1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
+1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ARM GAS  /tmp/ccHbw826.s 			page 39
+
+
+1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set ADC number of conversion */
+1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
+ 190              		.loc 1 1980 3 is_stmt 1 view .LVU73
+ 191              		.loc 1 1980 7 is_stmt 0 view .LVU74
+ 192 00c0 0268     		ldr	r2, [r0]
+ 193              		.loc 1 1980 24 view .LVU75
+ 194 00c2 D36A     		ldr	r3, [r2, #44]
+ 195 00c4 23F47003 		bic	r3, r3, #15728640
+ 196 00c8 D362     		str	r3, [r2, #44]
+1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->SQR1 |=  ADC_SQR1(hadc->Init.NbrOfConversion);
+ 197              		.loc 1 1981 3 is_stmt 1 view .LVU76
+ 198              		.loc 1 1981 7 is_stmt 0 view .LVU77
+ 199 00ca 0168     		ldr	r1, [r0]
+ 200              		.loc 1 1981 24 view .LVU78
+ 201 00cc CB6A     		ldr	r3, [r1, #44]
+ 202              		.loc 1 1981 28 view .LVU79
+ 203 00ce C269     		ldr	r2, [r0, #28]
+ 204 00d0 013A     		subs	r2, r2, #1
+ 205              		.loc 1 1981 24 view .LVU80
+ 206 00d2 43EA0253 		orr	r3, r3, r2, lsl #20
+ 207 00d6 CB62     		str	r3, [r1, #44]
+1982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Enable or disable ADC DMA continuous request */
+1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
+ 208              		.loc 1 1984 3 is_stmt 1 view .LVU81
+ 209              		.loc 1 1984 7 is_stmt 0 view .LVU82
+ 210 00d8 0268     		ldr	r2, [r0]
+ 211              		.loc 1 1984 23 view .LVU83
+ 212 00da 9368     		ldr	r3, [r2, #8]
+ 213 00dc 23F40073 		bic	r3, r3, #512
+ 214 00e0 9360     		str	r3, [r2, #8]
+1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
+ 215              		.loc 1 1985 3 is_stmt 1 view .LVU84
+ 216              		.loc 1 1985 7 is_stmt 0 view .LVU85
+ 217 00e2 0268     		ldr	r2, [r0]
+ 218              		.loc 1 1985 23 view .LVU86
+ 219 00e4 9368     		ldr	r3, [r2, #8]
+ 220              		.loc 1 1985 26 view .LVU87
+ 221 00e6 90F83010 		ldrb	r1, [r0, #48]	@ zero_extendqisi2
+ 222              		.loc 1 1985 23 view .LVU88
+ 223 00ea 43EA4123 		orr	r3, r3, r1, lsl #9
+ 224 00ee 9360     		str	r3, [r2, #8]
+1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Enable or disable ADC end of conversion selection */
+1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
+ 225              		.loc 1 1988 3 is_stmt 1 view .LVU89
+ 226              		.loc 1 1988 7 is_stmt 0 view .LVU90
+ 227 00f0 0268     		ldr	r2, [r0]
+ 228              		.loc 1 1988 23 view .LVU91
+ 229 00f2 9368     		ldr	r3, [r2, #8]
+ 230 00f4 23F48063 		bic	r3, r3, #1024
+ 231 00f8 9360     		str	r3, [r2, #8]
+1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
+ 232              		.loc 1 1989 3 is_stmt 1 view .LVU92
+ 233              		.loc 1 1989 7 is_stmt 0 view .LVU93
+ 234 00fa 0268     		ldr	r2, [r0]
+ 235              		.loc 1 1989 23 view .LVU94
+ARM GAS  /tmp/ccHbw826.s 			page 40
+
+
+ 236 00fc 9368     		ldr	r3, [r2, #8]
+ 237              		.loc 1 1989 26 view .LVU95
+ 238 00fe 4169     		ldr	r1, [r0, #20]
+ 239              		.loc 1 1989 23 view .LVU96
+ 240 0100 43EA8123 		orr	r3, r3, r1, lsl #10
+ 241 0104 9360     		str	r3, [r2, #8]
+1990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 242              		.loc 1 1990 1 view .LVU97
+ 243 0106 7047     		bx	lr
+ 244              	.L2:
+1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ 245              		.loc 1 1954 5 is_stmt 1 view .LVU98
+1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ 246              		.loc 1 1954 9 is_stmt 0 view .LVU99
+ 247 0108 0268     		ldr	r2, [r0]
+1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+ 248              		.loc 1 1954 25 view .LVU100
+ 249 010a 9368     		ldr	r3, [r2, #8]
+ 250 010c 23F07063 		bic	r3, r3, #251658240
+ 251 0110 9360     		str	r3, [r2, #8]
+1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 252              		.loc 1 1955 5 is_stmt 1 view .LVU101
+1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 253              		.loc 1 1955 9 is_stmt 0 view .LVU102
+ 254 0112 0268     		ldr	r2, [r0]
+1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 255              		.loc 1 1955 25 view .LVU103
+ 256 0114 9368     		ldr	r3, [r2, #8]
+ 257 0116 23F04053 		bic	r3, r3, #805306368
+ 258 011a 9360     		str	r3, [r2, #8]
+ 259 011c B0E7     		b	.L3
+ 260              	.L4:
+1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 261              		.loc 1 1976 5 is_stmt 1 view .LVU104
+1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 262              		.loc 1 1976 9 is_stmt 0 view .LVU105
+ 263 011e 0268     		ldr	r2, [r0]
+1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 264              		.loc 1 1976 25 view .LVU106
+ 265 0120 5368     		ldr	r3, [r2, #4]
+ 266 0122 23F40063 		bic	r3, r3, #2048
+ 267 0126 5360     		str	r3, [r2, #4]
+ 268 0128 CAE7     		b	.L5
+ 269              	.L7:
+ 270 012a 00BF     		.align	2
+ 271              	.L6:
+ 272 012c 00230140 		.word	1073816320
+ 273 0130 0100000F 		.word	251658241
+ 274              		.cfi_endproc
+ 275              	.LFE163:
+ 277              		.section	.text.HAL_ADC_MspInit,"ax",%progbits
+ 278              		.align	1
+ 279              		.weak	HAL_ADC_MspInit
+ 280              		.syntax unified
+ 281              		.thumb
+ 282              		.thumb_func
+ 283              		.fpu fpv5-d16
+ARM GAS  /tmp/ccHbw826.s 			page 41
+
+
+ 285              	HAL_ADC_MspInit:
+ 286              	.LVL1:
+ 287              	.LFB143:
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 288              		.loc 1 474 1 is_stmt 1 view -0
+ 289              		.cfi_startproc
+ 290              		@ args = 0, pretend = 0, frame = 0
+ 291              		@ frame_needed = 0, uses_anonymous_args = 0
+ 292              		@ link register save eliminated.
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 293              		.loc 1 476 3 view .LVU108
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 294              		.loc 1 480 1 is_stmt 0 view .LVU109
+ 295 0000 7047     		bx	lr
+ 296              		.cfi_endproc
+ 297              	.LFE143:
+ 299              		.section	.text.HAL_ADC_Init,"ax",%progbits
+ 300              		.align	1
+ 301              		.global	HAL_ADC_Init
+ 302              		.syntax unified
+ 303              		.thumb
+ 304              		.thumb_func
+ 305              		.fpu fpv5-d16
+ 307              	HAL_ADC_Init:
+ 308              	.LVL2:
+ 309              	.LFB141:
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 310              		.loc 1 323 1 is_stmt 1 view -0
+ 311              		.cfi_startproc
+ 312              		@ args = 0, pretend = 0, frame = 0
+ 313              		@ frame_needed = 0, uses_anonymous_args = 0
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 314              		.loc 1 324 3 view .LVU111
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 315              		.loc 1 327 3 view .LVU112
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 316              		.loc 1 327 5 is_stmt 0 view .LVU113
+ 317 0000 28B3     		cbz	r0, .L13
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 318              		.loc 1 323 1 view .LVU114
+ 319 0002 10B5     		push	{r4, lr}
+ 320              	.LCFI0:
+ 321              		.cfi_def_cfa_offset 8
+ 322              		.cfi_offset 4, -8
+ 323              		.cfi_offset 14, -4
+ 324 0004 0446     		mov	r4, r0
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ 325              		.loc 1 333 3 is_stmt 1 view .LVU115
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ 326              		.loc 1 334 3 view .LVU116
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ 327              		.loc 1 335 3 view .LVU117
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ 328              		.loc 1 336 3 view .LVU118
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
+ 329              		.loc 1 337 3 view .LVU119
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ARM GAS  /tmp/ccHbw826.s 			page 42
+
+
+ 330              		.loc 1 338 3 view .LVU120
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
+ 331              		.loc 1 339 3 view .LVU121
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ 332              		.loc 1 340 3 view .LVU122
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
+ 333              		.loc 1 341 3 view .LVU123
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+ 334              		.loc 1 342 3 view .LVU124
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 335              		.loc 1 343 3 view .LVU125
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 336              		.loc 1 345 3 view .LVU126
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 337              		.loc 1 347 5 view .LVU127
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 338              		.loc 1 350 3 view .LVU128
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 339              		.loc 1 350 10 is_stmt 0 view .LVU129
+ 340 0006 036C     		ldr	r3, [r0, #64]
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 341              		.loc 1 350 5 view .LVU130
+ 342 0008 43B1     		cbz	r3, .L19
+ 343              	.LVL3:
+ 344              	.L11:
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 345              		.loc 1 380 3 is_stmt 1 view .LVU131
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 346              		.loc 1 380 7 is_stmt 0 view .LVU132
+ 347 000a 236C     		ldr	r3, [r4, #64]
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 348              		.loc 1 380 6 view .LVU133
+ 349 000c 13F0100F 		tst	r3, #16
+ 350 0010 0BD0     		beq	.L20
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 351              		.loc 1 400 20 view .LVU134
+ 352 0012 0120     		movs	r0, #1
+ 353              	.L12:
+ 354              	.LVL4:
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 355              		.loc 1 404 3 is_stmt 1 view .LVU135
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 356              		.loc 1 404 3 view .LVU136
+ 357 0014 0023     		movs	r3, #0
+ 358 0016 84F83C30 		strb	r3, [r4, #60]
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 359              		.loc 1 404 3 view .LVU137
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 360              		.loc 1 407 3 view .LVU138
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 361              		.loc 1 408 1 is_stmt 0 view .LVU139
+ 362 001a 10BD     		pop	{r4, pc}
+ 363              	.LVL5:
+ 364              	.L19:
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 365              		.loc 1 368 5 is_stmt 1 view .LVU140
+ 366 001c FFF7FEFF 		bl	HAL_ADC_MspInit
+ARM GAS  /tmp/ccHbw826.s 			page 43
+
+
+ 367              	.LVL6:
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 368              		.loc 1 372 5 view .LVU141
+ 369 0020 0023     		movs	r3, #0
+ 370 0022 6364     		str	r3, [r4, #68]
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 371              		.loc 1 375 5 view .LVU142
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 372              		.loc 1 375 16 is_stmt 0 view .LVU143
+ 373 0024 84F83C30 		strb	r3, [r4, #60]
+ 374 0028 EFE7     		b	.L11
+ 375              	.L20:
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 376              		.loc 1 383 5 is_stmt 1 view .LVU144
+ 377 002a 226C     		ldr	r2, [r4, #64]
+ 378 002c 094B     		ldr	r3, .L21
+ 379 002e 1340     		ands	r3, r3, r2
+ 380 0030 43F00203 		orr	r3, r3, #2
+ 381 0034 2364     		str	r3, [r4, #64]
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 382              		.loc 1 388 5 view .LVU145
+ 383 0036 2046     		mov	r0, r4
+ 384 0038 FFF7FEFF 		bl	ADC_Init
+ 385              	.LVL7:
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 386              		.loc 1 391 5 view .LVU146
+ 387 003c 0020     		movs	r0, #0
+ 388 003e 6064     		str	r0, [r4, #68]
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_BUSY_INTERNAL,
+ 389              		.loc 1 394 5 view .LVU147
+ 390 0040 236C     		ldr	r3, [r4, #64]
+ 391 0042 23F00303 		bic	r3, r3, #3
+ 392 0046 43F00103 		orr	r3, r3, #1
+ 393 004a 2364     		str	r3, [r4, #64]
+ 394 004c E2E7     		b	.L12
+ 395              	.LVL8:
+ 396              	.L13:
+ 397              	.LCFI1:
+ 398              		.cfi_def_cfa_offset 0
+ 399              		.cfi_restore 4
+ 400              		.cfi_restore 14
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 401              		.loc 1 329 12 is_stmt 0 view .LVU148
+ 402 004e 0120     		movs	r0, #1
+ 403              	.LVL9:
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 404              		.loc 1 408 1 view .LVU149
+ 405 0050 7047     		bx	lr
+ 406              	.L22:
+ 407 0052 00BF     		.align	2
+ 408              	.L21:
+ 409 0054 FDEEFFFF 		.word	-4355
+ 410              		.cfi_endproc
+ 411              	.LFE141:
+ 413              		.section	.text.HAL_ADC_MspDeInit,"ax",%progbits
+ 414              		.align	1
+ 415              		.weak	HAL_ADC_MspDeInit
+ARM GAS  /tmp/ccHbw826.s 			page 44
+
+
+ 416              		.syntax unified
+ 417              		.thumb
+ 418              		.thumb_func
+ 419              		.fpu fpv5-d16
+ 421              	HAL_ADC_MspDeInit:
+ 422              	.LVL10:
+ 423              	.LFB144:
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 424              		.loc 1 489 1 is_stmt 1 view -0
+ 425              		.cfi_startproc
+ 426              		@ args = 0, pretend = 0, frame = 0
+ 427              		@ frame_needed = 0, uses_anonymous_args = 0
+ 428              		@ link register save eliminated.
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 429              		.loc 1 491 3 view .LVU151
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 430              		.loc 1 495 1 is_stmt 0 view .LVU152
+ 431 0000 7047     		bx	lr
+ 432              		.cfi_endproc
+ 433              	.LFE144:
+ 435              		.section	.text.HAL_ADC_DeInit,"ax",%progbits
+ 436              		.align	1
+ 437              		.global	HAL_ADC_DeInit
+ 438              		.syntax unified
+ 439              		.thumb
+ 440              		.thumb_func
+ 441              		.fpu fpv5-d16
+ 443              	HAL_ADC_DeInit:
+ 444              	.LVL11:
+ 445              	.LFB142:
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 446              		.loc 1 417 1 is_stmt 1 view -0
+ 447              		.cfi_startproc
+ 448              		@ args = 0, pretend = 0, frame = 0
+ 449              		@ frame_needed = 0, uses_anonymous_args = 0
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 450              		.loc 1 418 3 view .LVU154
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 451              		.loc 1 421 3 view .LVU155
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 452              		.loc 1 421 5 is_stmt 0 view .LVU156
+ 453 0000 C8B1     		cbz	r0, .L27
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 454              		.loc 1 417 1 view .LVU157
+ 455 0002 10B5     		push	{r4, lr}
+ 456              	.LCFI2:
+ 457              		.cfi_def_cfa_offset 8
+ 458              		.cfi_offset 4, -8
+ 459              		.cfi_offset 14, -4
+ 460 0004 0446     		mov	r4, r0
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 461              		.loc 1 427 3 is_stmt 1 view .LVU158
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 462              		.loc 1 430 3 view .LVU159
+ 463 0006 036C     		ldr	r3, [r0, #64]
+ 464 0008 43F00203 		orr	r3, r3, #2
+ 465 000c 0364     		str	r3, [r0, #64]
+ARM GAS  /tmp/ccHbw826.s 			page 45
+
+
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 466              		.loc 1 434 3 view .LVU160
+ 467 000e 0268     		ldr	r2, [r0]
+ 468 0010 9368     		ldr	r3, [r2, #8]
+ 469 0012 23F00103 		bic	r3, r3, #1
+ 470 0016 9360     		str	r3, [r2, #8]
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 471              		.loc 1 438 3 view .LVU161
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 472              		.loc 1 438 6 is_stmt 0 view .LVU162
+ 473 0018 0368     		ldr	r3, [r0]
+ 474 001a 9B68     		ldr	r3, [r3, #8]
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 475              		.loc 1 438 5 view .LVU163
+ 476 001c 13F0010F 		tst	r3, #1
+ 477 0020 03D0     		beq	.L32
+ 478              	.LVL12:
+ 479              	.L26:
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 480              		.loc 1 461 3 is_stmt 1 view .LVU164
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 481              		.loc 1 461 3 view .LVU165
+ 482 0022 0020     		movs	r0, #0
+ 483 0024 84F83C00 		strb	r0, [r4, #60]
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 484              		.loc 1 461 3 view .LVU166
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 485              		.loc 1 464 3 view .LVU167
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 486              		.loc 1 465 1 is_stmt 0 view .LVU168
+ 487 0028 10BD     		pop	{r4, pc}
+ 488              	.LVL13:
+ 489              	.L32:
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 490              		.loc 1 450 3 is_stmt 1 view .LVU169
+ 491 002a FFF7FEFF 		bl	HAL_ADC_MspDeInit
+ 492              	.LVL14:
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 493              		.loc 1 454 5 view .LVU170
+ 494 002e 0023     		movs	r3, #0
+ 495 0030 6364     		str	r3, [r4, #68]
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 496              		.loc 1 457 5 view .LVU171
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 497              		.loc 1 457 17 is_stmt 0 view .LVU172
+ 498 0032 2364     		str	r3, [r4, #64]
+ 499 0034 F5E7     		b	.L26
+ 500              	.LVL15:
+ 501              	.L27:
+ 502              	.LCFI3:
+ 503              		.cfi_def_cfa_offset 0
+ 504              		.cfi_restore 4
+ 505              		.cfi_restore 14
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 506              		.loc 1 423 12 view .LVU173
+ 507 0036 0120     		movs	r0, #1
+ 508              	.LVL16:
+ARM GAS  /tmp/ccHbw826.s 			page 46
+
+
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 509              		.loc 1 465 1 view .LVU174
+ 510 0038 7047     		bx	lr
+ 511              		.cfi_endproc
+ 512              	.LFE142:
+ 514              		.section	.text.HAL_ADC_Start,"ax",%progbits
+ 515              		.align	1
+ 516              		.global	HAL_ADC_Start
+ 517              		.syntax unified
+ 518              		.thumb
+ 519              		.thumb_func
+ 520              		.fpu fpv5-d16
+ 522              	HAL_ADC_Start:
+ 523              	.LVL17:
+ 524              	.LFB145:
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+ 525              		.loc 1 731 1 is_stmt 1 view -0
+ 526              		.cfi_startproc
+ 527              		@ args = 0, pretend = 0, frame = 8
+ 528              		@ frame_needed = 0, uses_anonymous_args = 0
+ 529              		@ link register save eliminated.
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+ 530              		.loc 1 731 1 is_stmt 0 view .LVU176
+ 531 0000 82B0     		sub	sp, sp, #8
+ 532              	.LCFI4:
+ 533              		.cfi_def_cfa_offset 8
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 534              		.loc 1 732 3 is_stmt 1 view .LVU177
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 535              		.loc 1 732 17 is_stmt 0 view .LVU178
+ 536 0002 0023     		movs	r3, #0
+ 537 0004 0193     		str	r3, [sp, #4]
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
+ 538              		.loc 1 735 3 is_stmt 1 view .LVU179
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 539              		.loc 1 736 3 view .LVU180
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 540              		.loc 1 739 3 view .LVU181
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 541              		.loc 1 739 3 view .LVU182
+ 542 0006 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 543 000a 012B     		cmp	r3, #1
+ 544 000c 7ED0     		beq	.L44
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 545              		.loc 1 739 3 discriminator 2 view .LVU183
+ 546 000e 0123     		movs	r3, #1
+ 547 0010 80F83C30 		strb	r3, [r0, #60]
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 548              		.loc 1 739 3 discriminator 2 view .LVU184
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 549              		.loc 1 744 3 discriminator 2 view .LVU185
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 550              		.loc 1 744 11 is_stmt 0 discriminator 2 view .LVU186
+ 551 0014 0368     		ldr	r3, [r0]
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 552              		.loc 1 744 21 discriminator 2 view .LVU187
+ 553 0016 9A68     		ldr	r2, [r3, #8]
+ARM GAS  /tmp/ccHbw826.s 			page 47
+
+
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 554              		.loc 1 744 5 discriminator 2 view .LVU188
+ 555 0018 12F0010F 		tst	r2, #1
+ 556 001c 13D1     		bne	.L35
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 557              		.loc 1 747 5 is_stmt 1 view .LVU189
+ 558 001e 9A68     		ldr	r2, [r3, #8]
+ 559 0020 42F00102 		orr	r2, r2, #1
+ 560 0024 9A60     		str	r2, [r3, #8]
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 561              		.loc 1 751 5 view .LVU190
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 562              		.loc 1 751 53 is_stmt 0 view .LVU191
+ 563 0026 3D4B     		ldr	r3, .L52
+ 564 0028 1B68     		ldr	r3, [r3]
+ 565 002a 3D4A     		ldr	r2, .L52+4
+ 566 002c A2FB0323 		umull	r2, r3, r2, r3
+ 567 0030 9B0C     		lsrs	r3, r3, #18
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 568              		.loc 1 751 34 view .LVU192
+ 569 0032 03EB4303 		add	r3, r3, r3, lsl #1
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 570              		.loc 1 751 13 view .LVU193
+ 571 0036 0193     		str	r3, [sp, #4]
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 572              		.loc 1 752 5 is_stmt 1 view .LVU194
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 573              		.loc 1 752 10 is_stmt 0 view .LVU195
+ 574 0038 02E0     		b	.L36
+ 575              	.L37:
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 576              		.loc 1 754 7 is_stmt 1 view .LVU196
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 577              		.loc 1 754 14 is_stmt 0 view .LVU197
+ 578 003a 019B     		ldr	r3, [sp, #4]
+ 579 003c 013B     		subs	r3, r3, #1
+ 580 003e 0193     		str	r3, [sp, #4]
+ 581              	.L36:
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 582              		.loc 1 752 10 is_stmt 1 view .LVU198
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 583              		.loc 1 752 19 is_stmt 0 view .LVU199
+ 584 0040 019B     		ldr	r3, [sp, #4]
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 585              		.loc 1 752 10 view .LVU200
+ 586 0042 002B     		cmp	r3, #0
+ 587 0044 F9D1     		bne	.L37
+ 588              	.L35:
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 589              		.loc 1 759 3 is_stmt 1 view .LVU201
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 590              		.loc 1 759 6 is_stmt 0 view .LVU202
+ 591 0046 0368     		ldr	r3, [r0]
+ 592 0048 9A68     		ldr	r2, [r3, #8]
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 593              		.loc 1 759 5 view .LVU203
+ 594 004a 12F0010F 		tst	r2, #1
+ARM GAS  /tmp/ccHbw826.s 			page 48
+
+
+ 595 004e 52D0     		beq	.L38
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ 596              		.loc 1 764 5 is_stmt 1 view .LVU204
+ 597 0050 016C     		ldr	r1, [r0, #64]
+ 598 0052 344A     		ldr	r2, .L52+8
+ 599 0054 0A40     		ands	r2, r2, r1
+ 600 0056 42F48072 		orr	r2, r2, #256
+ 601 005a 0264     		str	r2, [r0, #64]
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 602              		.loc 1 770 5 view .LVU205
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 603              		.loc 1 770 9 is_stmt 0 view .LVU206
+ 604 005c 5A68     		ldr	r2, [r3, #4]
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 605              		.loc 1 770 8 view .LVU207
+ 606 005e 12F4806F 		tst	r2, #1024
+ 607 0062 05D0     		beq	.L39
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 608              		.loc 1 772 7 is_stmt 1 view .LVU208
+ 609 0064 026C     		ldr	r2, [r0, #64]
+ 610 0066 22F44052 		bic	r2, r2, #12288
+ 611 006a 42F48052 		orr	r2, r2, #4096
+ 612 006e 0264     		str	r2, [r0, #64]
+ 613              	.L39:
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 614              		.loc 1 776 5 view .LVU209
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 615              		.loc 1 776 9 is_stmt 0 view .LVU210
+ 616 0070 026C     		ldr	r2, [r0, #64]
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 617              		.loc 1 776 8 view .LVU211
+ 618 0072 12F4805F 		tst	r2, #4096
+ 619 0076 19D0     		beq	.L40
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 620              		.loc 1 779 7 is_stmt 1 view .LVU212
+ 621 0078 426C     		ldr	r2, [r0, #68]
+ 622 007a 22F00602 		bic	r2, r2, #6
+ 623 007e 4264     		str	r2, [r0, #68]
+ 624              	.L41:
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 625              		.loc 1 790 5 view .LVU213
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 626              		.loc 1 790 5 view .LVU214
+ 627 0080 0022     		movs	r2, #0
+ 628 0082 80F83C20 		strb	r2, [r0, #60]
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 629              		.loc 1 790 5 view .LVU215
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 630              		.loc 1 794 5 view .LVU216
+ 631 0086 6FF02202 		mvn	r2, #34
+ 632 008a 1A60     		str	r2, [r3]
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 633              		.loc 1 797 5 view .LVU217
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 634              		.loc 1 797 8 is_stmt 0 view .LVU218
+ 635 008c 264B     		ldr	r3, .L52+12
+ 636 008e 5B68     		ldr	r3, [r3, #4]
+ARM GAS  /tmp/ccHbw826.s 			page 49
+
+
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 637              		.loc 1 797 7 view .LVU219
+ 638 0090 13F01F0F 		tst	r3, #31
+ 639 0094 0DD1     		bne	.L42
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 640              		.loc 1 800 7 is_stmt 1 view .LVU220
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 641              		.loc 1 800 15 is_stmt 0 view .LVU221
+ 642 0096 0368     		ldr	r3, [r0]
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 643              		.loc 1 800 25 view .LVU222
+ 644 0098 9A68     		ldr	r2, [r3, #8]
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 645              		.loc 1 800 9 view .LVU223
+ 646 009a 12F0405F 		tst	r2, #805306368
+ 647 009e 37D1     		bne	.L45
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 648              		.loc 1 803 9 is_stmt 1 view .LVU224
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 649              		.loc 1 803 29 is_stmt 0 view .LVU225
+ 650 00a0 9A68     		ldr	r2, [r3, #8]
+ 651 00a2 42F08042 		orr	r2, r2, #1073741824
+ 652 00a6 9A60     		str	r2, [r3, #8]
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 653              		.loc 1 838 10 view .LVU226
+ 654 00a8 0020     		movs	r0, #0
+ 655              	.LVL18:
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 656              		.loc 1 838 10 view .LVU227
+ 657 00aa 2DE0     		b	.L34
+ 658              	.LVL19:
+ 659              	.L40:
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 660              		.loc 1 784 7 is_stmt 1 view .LVU228
+ 661 00ac 0022     		movs	r2, #0
+ 662 00ae 4264     		str	r2, [r0, #68]
+ 663 00b0 E6E7     		b	.L41
+ 664              	.L42:
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 665              		.loc 1 809 7 view .LVU229
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 666              		.loc 1 809 15 is_stmt 0 view .LVU230
+ 667 00b2 0368     		ldr	r3, [r0]
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 668              		.loc 1 809 9 view .LVU231
+ 669 00b4 1D4A     		ldr	r2, .L52+16
+ 670 00b6 9342     		cmp	r3, r2
+ 671 00b8 0AD0     		beq	.L50
+ 672              	.L43:
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 673              		.loc 1 817 7 is_stmt 1 view .LVU232
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 674              		.loc 1 817 11 is_stmt 0 view .LVU233
+ 675 00ba 1B4B     		ldr	r3, .L52+12
+ 676 00bc 5B68     		ldr	r3, [r3, #4]
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 677              		.loc 1 817 9 view .LVU234
+ARM GAS  /tmp/ccHbw826.s 			page 50
+
+
+ 678 00be 13F0100F 		tst	r3, #16
+ 679 00c2 27D1     		bne	.L46
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 680              		.loc 1 820 9 is_stmt 1 view .LVU235
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 681              		.loc 1 820 17 is_stmt 0 view .LVU236
+ 682 00c4 0368     		ldr	r3, [r0]
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 683              		.loc 1 820 11 view .LVU237
+ 684 00c6 1A4A     		ldr	r2, .L52+20
+ 685 00c8 9342     		cmp	r3, r2
+ 686 00ca 0AD0     		beq	.L51
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 687              		.loc 1 838 10 view .LVU238
+ 688 00cc 0020     		movs	r0, #0
+ 689              	.LVL20:
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 690              		.loc 1 838 10 view .LVU239
+ 691 00ce 1BE0     		b	.L34
+ 692              	.LVL21:
+ 693              	.L50:
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 694              		.loc 1 809 54 discriminator 1 view .LVU240
+ 695 00d0 9A68     		ldr	r2, [r3, #8]
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 696              		.loc 1 809 35 discriminator 1 view .LVU241
+ 697 00d2 12F0405F 		tst	r2, #805306368
+ 698 00d6 F0D1     		bne	.L43
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 699              		.loc 1 812 11 is_stmt 1 view .LVU242
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 700              		.loc 1 812 31 is_stmt 0 view .LVU243
+ 701 00d8 9A68     		ldr	r2, [r3, #8]
+ 702 00da 42F08042 		orr	r2, r2, #1073741824
+ 703 00de 9A60     		str	r2, [r3, #8]
+ 704 00e0 EBE7     		b	.L43
+ 705              	.L51:
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 706              		.loc 1 820 56 discriminator 1 view .LVU244
+ 707 00e2 9A68     		ldr	r2, [r3, #8]
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 708              		.loc 1 820 37 discriminator 1 view .LVU245
+ 709 00e4 12F0405F 		tst	r2, #805306368
+ 710 00e8 16D1     		bne	.L48
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 711              		.loc 1 823 11 is_stmt 1 view .LVU246
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 712              		.loc 1 823 31 is_stmt 0 view .LVU247
+ 713 00ea 9A68     		ldr	r2, [r3, #8]
+ 714 00ec 42F08042 		orr	r2, r2, #1073741824
+ 715 00f0 9A60     		str	r2, [r3, #8]
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 716              		.loc 1 838 10 view .LVU248
+ 717 00f2 0020     		movs	r0, #0
+ 718              	.LVL22:
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 719              		.loc 1 838 10 view .LVU249
+ARM GAS  /tmp/ccHbw826.s 			page 51
+
+
+ 720 00f4 08E0     		b	.L34
+ 721              	.LVL23:
+ 722              	.L38:
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 723              		.loc 1 831 5 is_stmt 1 view .LVU250
+ 724 00f6 036C     		ldr	r3, [r0, #64]
+ 725 00f8 43F01003 		orr	r3, r3, #16
+ 726 00fc 0364     		str	r3, [r0, #64]
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 727              		.loc 1 834 5 view .LVU251
+ 728 00fe 436C     		ldr	r3, [r0, #68]
+ 729 0100 43F00103 		orr	r3, r3, #1
+ 730 0104 4364     		str	r3, [r0, #68]
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 731              		.loc 1 838 10 is_stmt 0 view .LVU252
+ 732 0106 0020     		movs	r0, #0
+ 733              	.LVL24:
+ 734              	.L34:
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 735              		.loc 1 839 1 view .LVU253
+ 736 0108 02B0     		add	sp, sp, #8
+ 737              	.LCFI5:
+ 738              		.cfi_remember_state
+ 739              		.cfi_def_cfa_offset 0
+ 740              		@ sp needed
+ 741 010a 7047     		bx	lr
+ 742              	.LVL25:
+ 743              	.L44:
+ 744              	.LCFI6:
+ 745              		.cfi_restore_state
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 746              		.loc 1 739 3 view .LVU254
+ 747 010c 0220     		movs	r0, #2
+ 748              	.LVL26:
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 749              		.loc 1 739 3 view .LVU255
+ 750 010e FBE7     		b	.L34
+ 751              	.LVL27:
+ 752              	.L45:
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 753              		.loc 1 838 10 view .LVU256
+ 754 0110 0020     		movs	r0, #0
+ 755              	.LVL28:
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 756              		.loc 1 838 10 view .LVU257
+ 757 0112 F9E7     		b	.L34
+ 758              	.LVL29:
+ 759              	.L46:
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 760              		.loc 1 838 10 view .LVU258
+ 761 0114 0020     		movs	r0, #0
+ 762              	.LVL30:
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 763              		.loc 1 838 10 view .LVU259
+ 764 0116 F7E7     		b	.L34
+ 765              	.LVL31:
+ 766              	.L48:
+ARM GAS  /tmp/ccHbw826.s 			page 52
+
+
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 767              		.loc 1 838 10 view .LVU260
+ 768 0118 0020     		movs	r0, #0
+ 769              	.LVL32:
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 770              		.loc 1 838 10 view .LVU261
+ 771 011a F5E7     		b	.L34
+ 772              	.L53:
+ 773              		.align	2
+ 774              	.L52:
+ 775 011c 00000000 		.word	SystemCoreClock
+ 776 0120 83DE1B43 		.word	1125899907
+ 777 0124 FEF8FFFF 		.word	-1794
+ 778 0128 00230140 		.word	1073816320
+ 779 012c 00200140 		.word	1073815552
+ 780 0130 00220140 		.word	1073816064
+ 781              		.cfi_endproc
+ 782              	.LFE145:
+ 784              		.section	.text.HAL_ADC_Stop,"ax",%progbits
+ 785              		.align	1
+ 786              		.global	HAL_ADC_Stop
+ 787              		.syntax unified
+ 788              		.thumb
+ 789              		.thumb_func
+ 790              		.fpu fpv5-d16
+ 792              	HAL_ADC_Stop:
+ 793              	.LVL33:
+ 794              	.LFB146:
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+ 795              		.loc 1 852 1 is_stmt 1 view -0
+ 796              		.cfi_startproc
+ 797              		@ args = 0, pretend = 0, frame = 0
+ 798              		@ frame_needed = 0, uses_anonymous_args = 0
+ 799              		@ link register save eliminated.
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 800              		.loc 1 854 3 view .LVU263
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 801              		.loc 1 857 3 view .LVU264
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 802              		.loc 1 857 3 view .LVU265
+ 803 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 804 0004 012B     		cmp	r3, #1
+ 805 0006 17D0     		beq	.L57
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 806              		.loc 1 857 3 discriminator 2 view .LVU266
+ 807 0008 0123     		movs	r3, #1
+ 808 000a 80F83C30 		strb	r3, [r0, #60]
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 809              		.loc 1 857 3 discriminator 2 view .LVU267
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 810              		.loc 1 861 3 discriminator 2 view .LVU268
+ 811 000e 0268     		ldr	r2, [r0]
+ 812 0010 9368     		ldr	r3, [r2, #8]
+ 813 0012 23F00103 		bic	r3, r3, #1
+ 814 0016 9360     		str	r3, [r2, #8]
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 815              		.loc 1 864 3 discriminator 2 view .LVU269
+ARM GAS  /tmp/ccHbw826.s 			page 53
+
+
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 816              		.loc 1 864 6 is_stmt 0 discriminator 2 view .LVU270
+ 817 0018 0368     		ldr	r3, [r0]
+ 818 001a 9B68     		ldr	r3, [r3, #8]
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 819              		.loc 1 864 5 discriminator 2 view .LVU271
+ 820 001c 13F0010F 		tst	r3, #1
+ 821 0020 05D1     		bne	.L56
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 822              		.loc 1 867 5 is_stmt 1 view .LVU272
+ 823 0022 026C     		ldr	r2, [r0, #64]
+ 824 0024 054B     		ldr	r3, .L58
+ 825 0026 1340     		ands	r3, r3, r2
+ 826 0028 43F00103 		orr	r3, r3, #1
+ 827 002c 0364     		str	r3, [r0, #64]
+ 828              	.L56:
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 829              		.loc 1 873 3 view .LVU273
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 830              		.loc 1 873 3 view .LVU274
+ 831 002e 0023     		movs	r3, #0
+ 832 0030 80F83C30 		strb	r3, [r0, #60]
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 833              		.loc 1 873 3 view .LVU275
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 834              		.loc 1 876 3 view .LVU276
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 835              		.loc 1 876 10 is_stmt 0 view .LVU277
+ 836 0034 1846     		mov	r0, r3
+ 837              	.LVL34:
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 838              		.loc 1 876 10 view .LVU278
+ 839 0036 7047     		bx	lr
+ 840              	.LVL35:
+ 841              	.L57:
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 842              		.loc 1 857 3 view .LVU279
+ 843 0038 0220     		movs	r0, #2
+ 844              	.LVL36:
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 845              		.loc 1 877 1 view .LVU280
+ 846 003a 7047     		bx	lr
+ 847              	.L59:
+ 848              		.align	2
+ 849              	.L58:
+ 850 003c FEEEFFFF 		.word	-4354
+ 851              		.cfi_endproc
+ 852              	.LFE146:
+ 854              		.section	.text.HAL_ADC_PollForConversion,"ax",%progbits
+ 855              		.align	1
+ 856              		.global	HAL_ADC_PollForConversion
+ 857              		.syntax unified
+ 858              		.thumb
+ 859              		.thumb_func
+ 860              		.fpu fpv5-d16
+ 862              	HAL_ADC_PollForConversion:
+ 863              	.LVL37:
+ARM GAS  /tmp/ccHbw826.s 			page 54
+
+
+ 864              	.LFB147:
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tickstart = 0;
+ 865              		.loc 1 895 1 is_stmt 1 view -0
+ 866              		.cfi_startproc
+ 867              		@ args = 0, pretend = 0, frame = 0
+ 868              		@ frame_needed = 0, uses_anonymous_args = 0
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tickstart = 0;
+ 869              		.loc 1 895 1 is_stmt 0 view .LVU282
+ 870 0000 70B5     		push	{r4, r5, r6, lr}
+ 871              	.LCFI7:
+ 872              		.cfi_def_cfa_offset 16
+ 873              		.cfi_offset 4, -16
+ 874              		.cfi_offset 5, -12
+ 875              		.cfi_offset 6, -8
+ 876              		.cfi_offset 14, -4
+ 877 0002 0446     		mov	r4, r0
+ 878 0004 0D46     		mov	r5, r1
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 879              		.loc 1 896 3 is_stmt 1 view .LVU283
+ 880              	.LVL38:
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
+ 881              		.loc 1 904 3 view .LVU284
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
+ 882              		.loc 1 904 7 is_stmt 0 view .LVU285
+ 883 0006 0368     		ldr	r3, [r0]
+ 884 0008 9A68     		ldr	r2, [r3, #8]
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
+ 885              		.loc 1 904 6 view .LVU286
+ 886 000a 12F4806F 		tst	r2, #1024
+ 887 000e 03D0     		beq	.L61
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 888              		.loc 1 905 7 discriminator 1 view .LVU287
+ 889 0010 9B68     		ldr	r3, [r3, #8]
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
+ 890              		.loc 1 904 57 discriminator 1 view .LVU288
+ 891 0012 13F4807F 		tst	r3, #256
+ 892 0016 19D1     		bne	.L74
+ 893              	.L61:
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 894              		.loc 1 917 3 is_stmt 1 view .LVU289
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 895              		.loc 1 917 15 is_stmt 0 view .LVU290
+ 896 0018 FFF7FEFF 		bl	HAL_GetTick
+ 897              	.LVL39:
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 898              		.loc 1 917 15 view .LVU291
+ 899 001c 0646     		mov	r6, r0
+ 900              	.LVL40:
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 901              		.loc 1 920 3 is_stmt 1 view .LVU292
+ 902              	.L64:
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 903              		.loc 1 920 8 view .LVU293
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 904              		.loc 1 920 11 is_stmt 0 view .LVU294
+ 905 001e 2368     		ldr	r3, [r4]
+ 906 0020 1A68     		ldr	r2, [r3]
+ARM GAS  /tmp/ccHbw826.s 			page 55
+
+
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 907              		.loc 1 920 8 view .LVU295
+ 908 0022 12F0020F 		tst	r2, #2
+ 909 0026 20D1     		bne	.L75
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 910              		.loc 1 923 5 is_stmt 1 view .LVU296
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 911              		.loc 1 923 7 is_stmt 0 view .LVU297
+ 912 0028 B5F1FF3F 		cmp	r5, #-1
+ 913 002c F7D0     		beq	.L64
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 914              		.loc 1 925 7 is_stmt 1 view .LVU298
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 915              		.loc 1 925 9 is_stmt 0 view .LVU299
+ 916 002e B5B9     		cbnz	r5, .L76
+ 917              	.L65:
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 918              		.loc 1 928 9 is_stmt 1 view .LVU300
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 919              		.loc 1 928 14 is_stmt 0 view .LVU301
+ 920 0030 2368     		ldr	r3, [r4]
+ 921 0032 1B68     		ldr	r3, [r3]
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 922              		.loc 1 928 11 view .LVU302
+ 923 0034 13F0020F 		tst	r3, #2
+ 924 0038 F1D1     		bne	.L64
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+ 925              		.loc 1 931 11 is_stmt 1 view .LVU303
+ 926 003a 236C     		ldr	r3, [r4, #64]
+ 927 003c 43F00403 		orr	r3, r3, #4
+ 928 0040 2364     		str	r3, [r4, #64]
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+ 929              		.loc 1 934 11 view .LVU304
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+ 930              		.loc 1 934 11 view .LVU305
+ 931 0042 0023     		movs	r3, #0
+ 932 0044 84F83C30 		strb	r3, [r4, #60]
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+ 933              		.loc 1 934 11 view .LVU306
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 934              		.loc 1 936 11 view .LVU307
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 935              		.loc 1 936 18 is_stmt 0 view .LVU308
+ 936 0048 0320     		movs	r0, #3
+ 937 004a 33E0     		b	.L62
+ 938              	.LVL41:
+ 939              	.L74:
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 940              		.loc 1 908 5 is_stmt 1 view .LVU309
+ 941 004c 036C     		ldr	r3, [r0, #64]
+ 942 004e 43F02003 		orr	r3, r3, #32
+ 943 0052 0364     		str	r3, [r0, #64]
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 944              		.loc 1 911 5 view .LVU310
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 945              		.loc 1 911 5 view .LVU311
+ 946 0054 0023     		movs	r3, #0
+ARM GAS  /tmp/ccHbw826.s 			page 56
+
+
+ 947 0056 80F83C30 		strb	r3, [r0, #60]
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 948              		.loc 1 911 5 view .LVU312
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 949              		.loc 1 913 5 view .LVU313
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 950              		.loc 1 913 12 is_stmt 0 view .LVU314
+ 951 005a 0120     		movs	r0, #1
+ 952              	.LVL42:
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 953              		.loc 1 913 12 view .LVU315
+ 954 005c 2AE0     		b	.L62
+ 955              	.LVL43:
+ 956              	.L76:
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 957              		.loc 1 925 30 discriminator 1 view .LVU316
+ 958 005e FFF7FEFF 		bl	HAL_GetTick
+ 959              	.LVL44:
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 960              		.loc 1 925 44 discriminator 1 view .LVU317
+ 961 0062 801B     		subs	r0, r0, r6
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 962              		.loc 1 925 25 discriminator 1 view .LVU318
+ 963 0064 A842     		cmp	r0, r5
+ 964 0066 DAD9     		bls	.L64
+ 965 0068 E2E7     		b	.L65
+ 966              	.L75:
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 967              		.loc 1 943 3 is_stmt 1 view .LVU319
+ 968 006a 6FF01202 		mvn	r2, #18
+ 969 006e 1A60     		str	r2, [r3]
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 970              		.loc 1 946 3 view .LVU320
+ 971 0070 236C     		ldr	r3, [r4, #64]
+ 972 0072 43F40073 		orr	r3, r3, #512
+ 973 0076 2364     		str	r3, [r4, #64]
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 974              		.loc 1 954 3 view .LVU321
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 975              		.loc 1 954 6 is_stmt 0 view .LVU322
+ 976 0078 2368     		ldr	r3, [r4]
+ 977 007a 9A68     		ldr	r2, [r3, #8]
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 978              		.loc 1 954 5 view .LVU323
+ 979 007c 12F0405F 		tst	r2, #805306368
+ 980 0080 17D1     		bne	.L69
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ 981              		.loc 1 955 17 discriminator 1 view .LVU324
+ 982 0082 A269     		ldr	r2, [r4, #24]
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 983              		.loc 1 954 60 discriminator 1 view .LVU325
+ 984 0084 BAB9     		cbnz	r2, .L70
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+ 985              		.loc 1 956 7 view .LVU326
+ 986 0086 DA6A     		ldr	r2, [r3, #44]
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****      (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ 987              		.loc 1 955 60 view .LVU327
+ARM GAS  /tmp/ccHbw826.s 			page 57
+
+
+ 988 0088 12F4700F 		tst	r2, #15728640
+ 989 008c 03D0     		beq	.L68
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 990              		.loc 1 957 7 view .LVU328
+ 991 008e 9B68     		ldr	r3, [r3, #8]
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+ 992              		.loc 1 956 56 view .LVU329
+ 993 0090 13F4806F 		tst	r3, #1024
+ 994 0094 11D1     		bne	.L71
+ 995              	.L68:
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 996              		.loc 1 960 5 is_stmt 1 view .LVU330
+ 997 0096 236C     		ldr	r3, [r4, #64]
+ 998 0098 23F48073 		bic	r3, r3, #256
+ 999 009c 2364     		str	r3, [r4, #64]
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     { 
+ 1000              		.loc 1 962 5 view .LVU331
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     { 
+ 1001              		.loc 1 962 9 is_stmt 0 view .LVU332
+ 1002 009e 236C     		ldr	r3, [r4, #64]
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     { 
+ 1003              		.loc 1 962 8 view .LVU333
+ 1004 00a0 13F4805F 		tst	r3, #4096
+ 1005 00a4 0BD1     		bne	.L72
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 1006              		.loc 1 964 7 is_stmt 1 view .LVU334
+ 1007 00a6 236C     		ldr	r3, [r4, #64]
+ 1008 00a8 43F00103 		orr	r3, r3, #1
+ 1009 00ac 2364     		str	r3, [r4, #64]
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1010              		.loc 1 969 10 is_stmt 0 view .LVU335
+ 1011 00ae 0020     		movs	r0, #0
+ 1012 00b0 00E0     		b	.L62
+ 1013              	.L69:
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1014              		.loc 1 969 10 view .LVU336
+ 1015 00b2 0020     		movs	r0, #0
+ 1016              	.LVL45:
+ 1017              	.L62:
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1018              		.loc 1 970 1 view .LVU337
+ 1019 00b4 70BD     		pop	{r4, r5, r6, pc}
+ 1020              	.LVL46:
+ 1021              	.L70:
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1022              		.loc 1 969 10 view .LVU338
+ 1023 00b6 0020     		movs	r0, #0
+ 1024 00b8 FCE7     		b	.L62
+ 1025              	.L71:
+ 1026 00ba 0020     		movs	r0, #0
+ 1027 00bc FAE7     		b	.L62
+ 1028              	.L72:
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1029              		.loc 1 969 10 view .LVU339
+ 1030 00be 0020     		movs	r0, #0
+ 1031 00c0 F8E7     		b	.L62
+ 1032              		.cfi_endproc
+ARM GAS  /tmp/ccHbw826.s 			page 58
+
+
+ 1033              	.LFE147:
+ 1035              		.section	.text.HAL_ADC_PollForEvent,"ax",%progbits
+ 1036              		.align	1
+ 1037              		.global	HAL_ADC_PollForEvent
+ 1038              		.syntax unified
+ 1039              		.thumb
+ 1040              		.thumb_func
+ 1041              		.fpu fpv5-d16
+ 1043              	HAL_ADC_PollForEvent:
+ 1044              	.LVL47:
+ 1045              	.LFB148:
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tickstart = 0;
+ 1046              		.loc 1 984 1 is_stmt 1 view -0
+ 1047              		.cfi_startproc
+ 1048              		@ args = 0, pretend = 0, frame = 0
+ 1049              		@ frame_needed = 0, uses_anonymous_args = 0
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tickstart = 0;
+ 1050              		.loc 1 984 1 is_stmt 0 view .LVU341
+ 1051 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 1052              	.LCFI8:
+ 1053              		.cfi_def_cfa_offset 24
+ 1054              		.cfi_offset 4, -24
+ 1055              		.cfi_offset 5, -20
+ 1056              		.cfi_offset 6, -16
+ 1057              		.cfi_offset 7, -12
+ 1058              		.cfi_offset 8, -8
+ 1059              		.cfi_offset 14, -4
+ 1060 0004 0546     		mov	r5, r0
+ 1061 0006 0E46     		mov	r6, r1
+ 1062 0008 1746     		mov	r7, r2
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1063              		.loc 1 985 3 is_stmt 1 view .LVU342
+ 1064              	.LVL48:
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EVENT_TYPE(EventType));
+ 1065              		.loc 1 988 3 view .LVU343
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1066              		.loc 1 989 3 view .LVU344
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1067              		.loc 1 992 3 view .LVU345
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1068              		.loc 1 992 15 is_stmt 0 view .LVU346
+ 1069 000a FFF7FEFF 		bl	HAL_GetTick
+ 1070              	.LVL49:
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1071              		.loc 1 992 15 view .LVU347
+ 1072 000e 8046     		mov	r8, r0
+ 1073              	.LVL50:
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1074              		.loc 1 995 3 is_stmt 1 view .LVU348
+ 1075              	.L79:
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1076              		.loc 1 995 8 view .LVU349
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1077              		.loc 1 995 11 is_stmt 0 view .LVU350
+ 1078 0010 2B68     		ldr	r3, [r5]
+ 1079 0012 1C68     		ldr	r4, [r3]
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ARM GAS  /tmp/ccHbw826.s 			page 59
+
+
+ 1080              		.loc 1 995 8 view .LVU351
+ 1081 0014 36EA0402 		bics	r2, r6, r4
+ 1082 0018 18D0     		beq	.L86
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1083              		.loc 1 998 5 is_stmt 1 view .LVU352
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1084              		.loc 1 998 7 is_stmt 0 view .LVU353
+ 1085 001a B7F1FF3F 		cmp	r7, #-1
+ 1086 001e F7D0     		beq	.L79
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1087              		.loc 1 1000 7 is_stmt 1 view .LVU354
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1088              		.loc 1 1000 9 is_stmt 0 view .LVU355
+ 1089 0020 6FB9     		cbnz	r7, .L87
+ 1090              	.L80:
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1091              		.loc 1 1003 9 is_stmt 1 view .LVU356
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1092              		.loc 1 1003 14 is_stmt 0 view .LVU357
+ 1093 0022 2B68     		ldr	r3, [r5]
+ 1094 0024 1B68     		ldr	r3, [r3]
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1095              		.loc 1 1003 11 view .LVU358
+ 1096 0026 36EA0303 		bics	r3, r6, r3
+ 1097 002a F1D0     		beq	.L79
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+ 1098              		.loc 1 1006 11 is_stmt 1 view .LVU359
+ 1099 002c 2B6C     		ldr	r3, [r5, #64]
+ 1100 002e 43F00403 		orr	r3, r3, #4
+ 1101 0032 2B64     		str	r3, [r5, #64]
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+ 1102              		.loc 1 1009 11 view .LVU360
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+ 1103              		.loc 1 1009 11 view .LVU361
+ 1104 0034 0023     		movs	r3, #0
+ 1105 0036 85F83C30 		strb	r3, [r5, #60]
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****           
+ 1106              		.loc 1 1009 11 view .LVU362
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 1107              		.loc 1 1011 11 view .LVU363
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 1108              		.loc 1 1011 18 is_stmt 0 view .LVU364
+ 1109 003a 0320     		movs	r0, #3
+ 1110 003c 14E0     		b	.L82
+ 1111              	.L87:
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1112              		.loc 1 1000 30 discriminator 1 view .LVU365
+ 1113 003e FFF7FEFF 		bl	HAL_GetTick
+ 1114              	.LVL51:
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1115              		.loc 1 1000 44 discriminator 1 view .LVU366
+ 1116 0042 A0EB0800 		sub	r0, r0, r8
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1117              		.loc 1 1000 25 discriminator 1 view .LVU367
+ 1118 0046 B842     		cmp	r0, r7
+ 1119 0048 E2D9     		bls	.L79
+ 1120 004a EAE7     		b	.L80
+ARM GAS  /tmp/ccHbw826.s 			page 60
+
+
+ 1121              	.L86:
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1122              		.loc 1 1018 3 is_stmt 1 view .LVU368
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1123              		.loc 1 1018 5 is_stmt 0 view .LVU369
+ 1124 004c 012E     		cmp	r6, #1
+ 1125 004e 0DD0     		beq	.L88
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Set ADC error code to overrun */
+ 1126              		.loc 1 1030 5 is_stmt 1 view .LVU370
+ 1127 0050 2A6C     		ldr	r2, [r5, #64]
+ 1128 0052 42F48062 		orr	r2, r2, #1024
+ 1129 0056 2A64     		str	r2, [r5, #64]
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1130              		.loc 1 1032 5 view .LVU371
+ 1131 0058 6A6C     		ldr	r2, [r5, #68]
+ 1132 005a 42F00202 		orr	r2, r2, #2
+ 1133 005e 6A64     		str	r2, [r5, #68]
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 1134              		.loc 1 1035 5 view .LVU372
+ 1135 0060 6FF02002 		mvn	r2, #32
+ 1136 0064 1A60     		str	r2, [r3]
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1137              		.loc 1 1039 10 is_stmt 0 view .LVU373
+ 1138 0066 0020     		movs	r0, #0
+ 1139              	.L82:
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1140              		.loc 1 1040 1 view .LVU374
+ 1141 0068 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 1142              	.LVL52:
+ 1143              	.L88:
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+ 1144              		.loc 1 1021 5 is_stmt 1 view .LVU375
+ 1145 006c 2A6C     		ldr	r2, [r5, #64]
+ 1146 006e 42F48032 		orr	r2, r2, #65536
+ 1147 0072 2A64     		str	r2, [r5, #64]
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 1148              		.loc 1 1024 5 view .LVU376
+ 1149 0074 6FF00102 		mvn	r2, #1
+ 1150 0078 1A60     		str	r2, [r3]
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1151              		.loc 1 1039 10 is_stmt 0 view .LVU377
+ 1152 007a 0020     		movs	r0, #0
+ 1153 007c F4E7     		b	.L82
+ 1154              		.cfi_endproc
+ 1155              	.LFE148:
+ 1157              		.section	.text.HAL_ADC_Start_IT,"ax",%progbits
+ 1158              		.align	1
+ 1159              		.global	HAL_ADC_Start_IT
+ 1160              		.syntax unified
+ 1161              		.thumb
+ 1162              		.thumb_func
+ 1163              		.fpu fpv5-d16
+ 1165              	HAL_ADC_Start_IT:
+ 1166              	.LVL53:
+ 1167              	.LFB149:
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+ 1168              		.loc 1 1050 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccHbw826.s 			page 61
+
+
+ 1169              		.cfi_startproc
+ 1170              		@ args = 0, pretend = 0, frame = 8
+ 1171              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1172              		@ link register save eliminated.
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+ 1173              		.loc 1 1050 1 is_stmt 0 view .LVU379
+ 1174 0000 82B0     		sub	sp, sp, #8
+ 1175              	.LCFI9:
+ 1176              		.cfi_def_cfa_offset 8
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1177              		.loc 1 1051 3 is_stmt 1 view .LVU380
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1178              		.loc 1 1051 17 is_stmt 0 view .LVU381
+ 1179 0002 0023     		movs	r3, #0
+ 1180 0004 0193     		str	r3, [sp, #4]
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
+ 1181              		.loc 1 1054 3 is_stmt 1 view .LVU382
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1182              		.loc 1 1055 3 view .LVU383
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1183              		.loc 1 1058 3 view .LVU384
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1184              		.loc 1 1058 3 view .LVU385
+ 1185 0006 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 1186 000a 012B     		cmp	r3, #1
+ 1187 000c 00F08480 		beq	.L100
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1188              		.loc 1 1058 3 discriminator 2 view .LVU386
+ 1189 0010 0123     		movs	r3, #1
+ 1190 0012 80F83C30 		strb	r3, [r0, #60]
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1191              		.loc 1 1058 3 discriminator 2 view .LVU387
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 1192              		.loc 1 1063 3 discriminator 2 view .LVU388
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 1193              		.loc 1 1063 11 is_stmt 0 discriminator 2 view .LVU389
+ 1194 0016 0368     		ldr	r3, [r0]
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 1195              		.loc 1 1063 21 discriminator 2 view .LVU390
+ 1196 0018 9A68     		ldr	r2, [r3, #8]
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 1197              		.loc 1 1063 5 discriminator 2 view .LVU391
+ 1198 001a 12F0010F 		tst	r2, #1
+ 1199 001e 13D1     		bne	.L91
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1200              		.loc 1 1066 5 is_stmt 1 view .LVU392
+ 1201 0020 9A68     		ldr	r2, [r3, #8]
+ 1202 0022 42F00102 		orr	r2, r2, #1
+ 1203 0026 9A60     		str	r2, [r3, #8]
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 1204              		.loc 1 1070 5 view .LVU393
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 1205              		.loc 1 1070 53 is_stmt 0 view .LVU394
+ 1206 0028 3F4B     		ldr	r3, .L108
+ 1207 002a 1B68     		ldr	r3, [r3]
+ 1208 002c 3F4A     		ldr	r2, .L108+4
+ 1209 002e A2FB0323 		umull	r2, r3, r2, r3
+ARM GAS  /tmp/ccHbw826.s 			page 62
+
+
+ 1210 0032 9B0C     		lsrs	r3, r3, #18
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 1211              		.loc 1 1070 34 view .LVU395
+ 1212 0034 03EB4303 		add	r3, r3, r3, lsl #1
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 1213              		.loc 1 1070 13 view .LVU396
+ 1214 0038 0193     		str	r3, [sp, #4]
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1215              		.loc 1 1071 5 is_stmt 1 view .LVU397
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1216              		.loc 1 1071 10 is_stmt 0 view .LVU398
+ 1217 003a 02E0     		b	.L92
+ 1218              	.L93:
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 1219              		.loc 1 1073 7 is_stmt 1 view .LVU399
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 1220              		.loc 1 1073 14 is_stmt 0 view .LVU400
+ 1221 003c 019B     		ldr	r3, [sp, #4]
+ 1222 003e 013B     		subs	r3, r3, #1
+ 1223 0040 0193     		str	r3, [sp, #4]
+ 1224              	.L92:
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1225              		.loc 1 1071 10 is_stmt 1 view .LVU401
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1226              		.loc 1 1071 19 is_stmt 0 view .LVU402
+ 1227 0042 019B     		ldr	r3, [sp, #4]
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1228              		.loc 1 1071 10 view .LVU403
+ 1229 0044 002B     		cmp	r3, #0
+ 1230 0046 F9D1     		bne	.L93
+ 1231              	.L91:
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1232              		.loc 1 1078 3 is_stmt 1 view .LVU404
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1233              		.loc 1 1078 6 is_stmt 0 view .LVU405
+ 1234 0048 0368     		ldr	r3, [r0]
+ 1235 004a 9A68     		ldr	r2, [r3, #8]
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1236              		.loc 1 1078 5 view .LVU406
+ 1237 004c 12F0010F 		tst	r2, #1
+ 1238 0050 57D0     		beq	.L94
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ 1239              		.loc 1 1083 5 is_stmt 1 view .LVU407
+ 1240 0052 016C     		ldr	r1, [r0, #64]
+ 1241 0054 364A     		ldr	r2, .L108+8
+ 1242 0056 0A40     		ands	r2, r2, r1
+ 1243 0058 42F48072 		orr	r2, r2, #256
+ 1244 005c 0264     		str	r2, [r0, #64]
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1245              		.loc 1 1089 5 view .LVU408
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1246              		.loc 1 1089 9 is_stmt 0 view .LVU409
+ 1247 005e 5A68     		ldr	r2, [r3, #4]
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1248              		.loc 1 1089 8 view .LVU410
+ 1249 0060 12F4806F 		tst	r2, #1024
+ 1250 0064 05D0     		beq	.L95
+ARM GAS  /tmp/ccHbw826.s 			page 63
+
+
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 1251              		.loc 1 1091 7 is_stmt 1 view .LVU411
+ 1252 0066 026C     		ldr	r2, [r0, #64]
+ 1253 0068 22F44052 		bic	r2, r2, #12288
+ 1254 006c 42F48052 		orr	r2, r2, #4096
+ 1255 0070 0264     		str	r2, [r0, #64]
+ 1256              	.L95:
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1257              		.loc 1 1095 5 view .LVU412
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1258              		.loc 1 1095 9 is_stmt 0 view .LVU413
+ 1259 0072 026C     		ldr	r2, [r0, #64]
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1260              		.loc 1 1095 8 view .LVU414
+ 1261 0074 12F4805F 		tst	r2, #4096
+ 1262 0078 1ED0     		beq	.L96
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 1263              		.loc 1 1098 7 is_stmt 1 view .LVU415
+ 1264 007a 426C     		ldr	r2, [r0, #68]
+ 1265 007c 22F00602 		bic	r2, r2, #6
+ 1266 0080 4264     		str	r2, [r0, #68]
+ 1267              	.L97:
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1268              		.loc 1 1109 5 view .LVU416
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1269              		.loc 1 1109 5 view .LVU417
+ 1270 0082 0022     		movs	r2, #0
+ 1271 0084 80F83C20 		strb	r2, [r0, #60]
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1272              		.loc 1 1109 5 view .LVU418
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1273              		.loc 1 1113 5 view .LVU419
+ 1274 0088 6FF02202 		mvn	r2, #34
+ 1275 008c 1A60     		str	r2, [r3]
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1276              		.loc 1 1116 5 view .LVU420
+ 1277 008e 0268     		ldr	r2, [r0]
+ 1278 0090 5168     		ldr	r1, [r2, #4]
+ 1279 0092 284B     		ldr	r3, .L108+12
+ 1280 0094 0B43     		orrs	r3, r3, r1
+ 1281 0096 5360     		str	r3, [r2, #4]
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1282              		.loc 1 1119 5 view .LVU421
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1283              		.loc 1 1119 8 is_stmt 0 view .LVU422
+ 1284 0098 274B     		ldr	r3, .L108+16
+ 1285 009a 5B68     		ldr	r3, [r3, #4]
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1286              		.loc 1 1119 7 view .LVU423
+ 1287 009c 13F01F0F 		tst	r3, #31
+ 1288 00a0 0DD1     		bne	.L98
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1289              		.loc 1 1122 7 is_stmt 1 view .LVU424
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1290              		.loc 1 1122 15 is_stmt 0 view .LVU425
+ 1291 00a2 0368     		ldr	r3, [r0]
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ARM GAS  /tmp/ccHbw826.s 			page 64
+
+
+ 1292              		.loc 1 1122 25 view .LVU426
+ 1293 00a4 9A68     		ldr	r2, [r3, #8]
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1294              		.loc 1 1122 9 view .LVU427
+ 1295 00a6 12F0405F 		tst	r2, #805306368
+ 1296 00aa 37D1     		bne	.L101
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 1297              		.loc 1 1125 9 is_stmt 1 view .LVU428
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 1298              		.loc 1 1125 29 is_stmt 0 view .LVU429
+ 1299 00ac 9A68     		ldr	r2, [r3, #8]
+ 1300 00ae 42F08042 		orr	r2, r2, #1073741824
+ 1301 00b2 9A60     		str	r2, [r3, #8]
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1302              		.loc 1 1160 10 view .LVU430
+ 1303 00b4 0020     		movs	r0, #0
+ 1304              	.LVL54:
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1305              		.loc 1 1160 10 view .LVU431
+ 1306 00b6 2DE0     		b	.L90
+ 1307              	.LVL55:
+ 1308              	.L96:
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 1309              		.loc 1 1103 7 is_stmt 1 view .LVU432
+ 1310 00b8 0022     		movs	r2, #0
+ 1311 00ba 4264     		str	r2, [r0, #68]
+ 1312 00bc E1E7     		b	.L97
+ 1313              	.L98:
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1314              		.loc 1 1131 7 view .LVU433
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1315              		.loc 1 1131 15 is_stmt 0 view .LVU434
+ 1316 00be 0368     		ldr	r3, [r0]
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1317              		.loc 1 1131 9 view .LVU435
+ 1318 00c0 1E4A     		ldr	r2, .L108+20
+ 1319 00c2 9342     		cmp	r3, r2
+ 1320 00c4 0AD0     		beq	.L106
+ 1321              	.L99:
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1322              		.loc 1 1139 7 is_stmt 1 view .LVU436
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1323              		.loc 1 1139 11 is_stmt 0 view .LVU437
+ 1324 00c6 1C4B     		ldr	r3, .L108+16
+ 1325 00c8 5B68     		ldr	r3, [r3, #4]
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1326              		.loc 1 1139 9 view .LVU438
+ 1327 00ca 13F0100F 		tst	r3, #16
+ 1328 00ce 27D1     		bne	.L102
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1329              		.loc 1 1142 9 is_stmt 1 view .LVU439
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1330              		.loc 1 1142 17 is_stmt 0 view .LVU440
+ 1331 00d0 0368     		ldr	r3, [r0]
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1332              		.loc 1 1142 11 view .LVU441
+ 1333 00d2 1B4A     		ldr	r2, .L108+24
+ARM GAS  /tmp/ccHbw826.s 			page 65
+
+
+ 1334 00d4 9342     		cmp	r3, r2
+ 1335 00d6 0AD0     		beq	.L107
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1336              		.loc 1 1160 10 view .LVU442
+ 1337 00d8 0020     		movs	r0, #0
+ 1338              	.LVL56:
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1339              		.loc 1 1160 10 view .LVU443
+ 1340 00da 1BE0     		b	.L90
+ 1341              	.LVL57:
+ 1342              	.L106:
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1343              		.loc 1 1131 54 discriminator 1 view .LVU444
+ 1344 00dc 9A68     		ldr	r2, [r3, #8]
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1345              		.loc 1 1131 35 discriminator 1 view .LVU445
+ 1346 00de 12F0405F 		tst	r2, #805306368
+ 1347 00e2 F0D1     		bne	.L99
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 1348              		.loc 1 1134 11 is_stmt 1 view .LVU446
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 1349              		.loc 1 1134 31 is_stmt 0 view .LVU447
+ 1350 00e4 9A68     		ldr	r2, [r3, #8]
+ 1351 00e6 42F08042 		orr	r2, r2, #1073741824
+ 1352 00ea 9A60     		str	r2, [r3, #8]
+ 1353 00ec EBE7     		b	.L99
+ 1354              	.L107:
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1355              		.loc 1 1142 56 discriminator 1 view .LVU448
+ 1356 00ee 9A68     		ldr	r2, [r3, #8]
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1357              		.loc 1 1142 37 discriminator 1 view .LVU449
+ 1358 00f0 12F0405F 		tst	r2, #805306368
+ 1359 00f4 16D1     		bne	.L104
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 1360              		.loc 1 1145 11 is_stmt 1 view .LVU450
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 1361              		.loc 1 1145 31 is_stmt 0 view .LVU451
+ 1362 00f6 9A68     		ldr	r2, [r3, #8]
+ 1363 00f8 42F08042 		orr	r2, r2, #1073741824
+ 1364 00fc 9A60     		str	r2, [r3, #8]
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1365              		.loc 1 1160 10 view .LVU452
+ 1366 00fe 0020     		movs	r0, #0
+ 1367              	.LVL58:
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1368              		.loc 1 1160 10 view .LVU453
+ 1369 0100 08E0     		b	.L90
+ 1370              	.LVL59:
+ 1371              	.L94:
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1372              		.loc 1 1153 5 is_stmt 1 view .LVU454
+ 1373 0102 036C     		ldr	r3, [r0, #64]
+ 1374 0104 43F01003 		orr	r3, r3, #16
+ 1375 0108 0364     		str	r3, [r0, #64]
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 1376              		.loc 1 1156 5 view .LVU455
+ARM GAS  /tmp/ccHbw826.s 			page 66
+
+
+ 1377 010a 436C     		ldr	r3, [r0, #68]
+ 1378 010c 43F00103 		orr	r3, r3, #1
+ 1379 0110 4364     		str	r3, [r0, #68]
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1380              		.loc 1 1160 10 is_stmt 0 view .LVU456
+ 1381 0112 0020     		movs	r0, #0
+ 1382              	.LVL60:
+ 1383              	.L90:
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1384              		.loc 1 1161 1 view .LVU457
+ 1385 0114 02B0     		add	sp, sp, #8
+ 1386              	.LCFI10:
+ 1387              		.cfi_remember_state
+ 1388              		.cfi_def_cfa_offset 0
+ 1389              		@ sp needed
+ 1390 0116 7047     		bx	lr
+ 1391              	.LVL61:
+ 1392              	.L100:
+ 1393              	.LCFI11:
+ 1394              		.cfi_restore_state
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1395              		.loc 1 1058 3 view .LVU458
+ 1396 0118 0220     		movs	r0, #2
+ 1397              	.LVL62:
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1398              		.loc 1 1058 3 view .LVU459
+ 1399 011a FBE7     		b	.L90
+ 1400              	.LVL63:
+ 1401              	.L101:
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1402              		.loc 1 1160 10 view .LVU460
+ 1403 011c 0020     		movs	r0, #0
+ 1404              	.LVL64:
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1405              		.loc 1 1160 10 view .LVU461
+ 1406 011e F9E7     		b	.L90
+ 1407              	.LVL65:
+ 1408              	.L102:
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1409              		.loc 1 1160 10 view .LVU462
+ 1410 0120 0020     		movs	r0, #0
+ 1411              	.LVL66:
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1412              		.loc 1 1160 10 view .LVU463
+ 1413 0122 F7E7     		b	.L90
+ 1414              	.LVL67:
+ 1415              	.L104:
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1416              		.loc 1 1160 10 view .LVU464
+ 1417 0124 0020     		movs	r0, #0
+ 1418              	.LVL68:
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1419              		.loc 1 1160 10 view .LVU465
+ 1420 0126 F5E7     		b	.L90
+ 1421              	.L109:
+ 1422              		.align	2
+ 1423              	.L108:
+ARM GAS  /tmp/ccHbw826.s 			page 67
+
+
+ 1424 0128 00000000 		.word	SystemCoreClock
+ 1425 012c 83DE1B43 		.word	1125899907
+ 1426 0130 FEF8FFFF 		.word	-1794
+ 1427 0134 20000004 		.word	67108896
+ 1428 0138 00230140 		.word	1073816320
+ 1429 013c 00200140 		.word	1073815552
+ 1430 0140 00220140 		.word	1073816064
+ 1431              		.cfi_endproc
+ 1432              	.LFE149:
+ 1434              		.section	.text.HAL_ADC_Stop_IT,"ax",%progbits
+ 1435              		.align	1
+ 1436              		.global	HAL_ADC_Stop_IT
+ 1437              		.syntax unified
+ 1438              		.thumb
+ 1439              		.thumb_func
+ 1440              		.fpu fpv5-d16
+ 1442              	HAL_ADC_Stop_IT:
+ 1443              	.LVL69:
+ 1444              	.LFB150:
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check the parameters */
+ 1445              		.loc 1 1173 1 is_stmt 1 view -0
+ 1446              		.cfi_startproc
+ 1447              		@ args = 0, pretend = 0, frame = 0
+ 1448              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1449              		@ link register save eliminated.
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1450              		.loc 1 1175 3 view .LVU467
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1451              		.loc 1 1178 3 view .LVU468
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1452              		.loc 1 1178 3 view .LVU469
+ 1453 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 1454 0004 012B     		cmp	r3, #1
+ 1455 0006 1BD0     		beq	.L113
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1456              		.loc 1 1178 3 discriminator 2 view .LVU470
+ 1457 0008 0123     		movs	r3, #1
+ 1458 000a 80F83C30 		strb	r3, [r0, #60]
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1459              		.loc 1 1178 3 discriminator 2 view .LVU471
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1460              		.loc 1 1182 3 discriminator 2 view .LVU472
+ 1461 000e 0268     		ldr	r2, [r0]
+ 1462 0010 9368     		ldr	r3, [r2, #8]
+ 1463 0012 23F00103 		bic	r3, r3, #1
+ 1464 0016 9360     		str	r3, [r2, #8]
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1465              		.loc 1 1185 3 discriminator 2 view .LVU473
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1466              		.loc 1 1185 6 is_stmt 0 discriminator 2 view .LVU474
+ 1467 0018 0368     		ldr	r3, [r0]
+ 1468 001a 9A68     		ldr	r2, [r3, #8]
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1469              		.loc 1 1185 5 discriminator 2 view .LVU475
+ 1470 001c 12F0010F 		tst	r2, #1
+ 1471 0020 09D1     		bne	.L112
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ARM GAS  /tmp/ccHbw826.s 			page 68
+
+
+ 1472              		.loc 1 1188 5 is_stmt 1 view .LVU476
+ 1473 0022 5968     		ldr	r1, [r3, #4]
+ 1474 0024 074A     		ldr	r2, .L114
+ 1475 0026 0A40     		ands	r2, r2, r1
+ 1476 0028 5A60     		str	r2, [r3, #4]
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 1477              		.loc 1 1191 5 view .LVU477
+ 1478 002a 026C     		ldr	r2, [r0, #64]
+ 1479 002c 064B     		ldr	r3, .L114+4
+ 1480 002e 1340     		ands	r3, r3, r2
+ 1481 0030 43F00103 		orr	r3, r3, #1
+ 1482 0034 0364     		str	r3, [r0, #64]
+ 1483              	.L112:
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1484              		.loc 1 1197 3 view .LVU478
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1485              		.loc 1 1197 3 view .LVU479
+ 1486 0036 0023     		movs	r3, #0
+ 1487 0038 80F83C30 		strb	r3, [r0, #60]
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1488              		.loc 1 1197 3 view .LVU480
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1489              		.loc 1 1200 3 view .LVU481
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1490              		.loc 1 1200 10 is_stmt 0 view .LVU482
+ 1491 003c 1846     		mov	r0, r3
+ 1492              	.LVL70:
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1493              		.loc 1 1200 10 view .LVU483
+ 1494 003e 7047     		bx	lr
+ 1495              	.LVL71:
+ 1496              	.L113:
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1497              		.loc 1 1178 3 view .LVU484
+ 1498 0040 0220     		movs	r0, #2
+ 1499              	.LVL72:
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1500              		.loc 1 1201 1 view .LVU485
+ 1501 0042 7047     		bx	lr
+ 1502              	.L115:
+ 1503              		.align	2
+ 1504              	.L114:
+ 1505 0044 DFFFFFFB 		.word	-67108897
+ 1506 0048 FEEEFFFF 		.word	-4354
+ 1507              		.cfi_endproc
+ 1508              	.LFE150:
+ 1510              		.section	.text.HAL_ADC_Start_DMA,"ax",%progbits
+ 1511              		.align	1
+ 1512              		.global	HAL_ADC_Start_DMA
+ 1513              		.syntax unified
+ 1514              		.thumb
+ 1515              		.thumb_func
+ 1516              		.fpu fpv5-d16
+ 1518              	HAL_ADC_Start_DMA:
+ 1519              	.LVL73:
+ 1520              	.LFB152:
+1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+ARM GAS  /tmp/ccHbw826.s 			page 69
+
+
+ 1521              		.loc 1 1376 1 is_stmt 1 view -0
+ 1522              		.cfi_startproc
+ 1523              		@ args = 0, pretend = 0, frame = 8
+ 1524              		@ frame_needed = 0, uses_anonymous_args = 0
+1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+ 1525              		.loc 1 1376 1 is_stmt 0 view .LVU487
+ 1526 0000 30B5     		push	{r4, r5, lr}
+ 1527              	.LCFI12:
+ 1528              		.cfi_def_cfa_offset 12
+ 1529              		.cfi_offset 4, -12
+ 1530              		.cfi_offset 5, -8
+ 1531              		.cfi_offset 14, -4
+ 1532 0002 83B0     		sub	sp, sp, #12
+ 1533              	.LCFI13:
+ 1534              		.cfi_def_cfa_offset 24
+ 1535 0004 1346     		mov	r3, r2
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1536              		.loc 1 1377 3 is_stmt 1 view .LVU488
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1537              		.loc 1 1377 17 is_stmt 0 view .LVU489
+ 1538 0006 0022     		movs	r2, #0
+ 1539              	.LVL74:
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1540              		.loc 1 1377 17 view .LVU490
+ 1541 0008 0192     		str	r2, [sp, #4]
+1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
+ 1542              		.loc 1 1380 3 is_stmt 1 view .LVU491
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1543              		.loc 1 1381 3 view .LVU492
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1544              		.loc 1 1384 3 view .LVU493
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1545              		.loc 1 1384 3 view .LVU494
+ 1546 000a 90F83C20 		ldrb	r2, [r0, #60]	@ zero_extendqisi2
+ 1547 000e 012A     		cmp	r2, #1
+ 1548 0010 00F09B80 		beq	.L127
+ 1549 0014 0446     		mov	r4, r0
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1550              		.loc 1 1384 3 discriminator 2 view .LVU495
+ 1551 0016 0122     		movs	r2, #1
+ 1552 0018 80F83C20 		strb	r2, [r0, #60]
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1553              		.loc 1 1384 3 discriminator 2 view .LVU496
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 1554              		.loc 1 1389 3 discriminator 2 view .LVU497
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 1555              		.loc 1 1389 11 is_stmt 0 discriminator 2 view .LVU498
+ 1556 001c 0268     		ldr	r2, [r0]
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 1557              		.loc 1 1389 21 discriminator 2 view .LVU499
+ 1558 001e 9068     		ldr	r0, [r2, #8]
+ 1559              	.LVL75:
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {  
+ 1560              		.loc 1 1389 5 discriminator 2 view .LVU500
+ 1561 0020 10F0010F 		tst	r0, #1
+ 1562 0024 13D1     		bne	.L118
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ARM GAS  /tmp/ccHbw826.s 			page 70
+
+
+ 1563              		.loc 1 1392 5 is_stmt 1 view .LVU501
+ 1564 0026 9068     		ldr	r0, [r2, #8]
+ 1565 0028 40F00100 		orr	r0, r0, #1
+ 1566 002c 9060     		str	r0, [r2, #8]
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 1567              		.loc 1 1396 5 view .LVU502
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 1568              		.loc 1 1396 53 is_stmt 0 view .LVU503
+ 1569 002e 4B4A     		ldr	r2, .L135
+ 1570 0030 1068     		ldr	r0, [r2]
+ 1571 0032 4B4A     		ldr	r2, .L135+4
+ 1572 0034 A2FB0020 		umull	r2, r0, r2, r0
+ 1573 0038 800C     		lsrs	r0, r0, #18
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 1574              		.loc 1 1396 34 view .LVU504
+ 1575 003a 00EB4000 		add	r0, r0, r0, lsl #1
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     while(counter != 0)
+ 1576              		.loc 1 1396 13 view .LVU505
+ 1577 003e 0190     		str	r0, [sp, #4]
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1578              		.loc 1 1397 5 is_stmt 1 view .LVU506
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1579              		.loc 1 1397 10 is_stmt 0 view .LVU507
+ 1580 0040 02E0     		b	.L119
+ 1581              	.L120:
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 1582              		.loc 1 1399 7 is_stmt 1 view .LVU508
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 1583              		.loc 1 1399 14 is_stmt 0 view .LVU509
+ 1584 0042 0198     		ldr	r0, [sp, #4]
+ 1585 0044 0138     		subs	r0, r0, #1
+ 1586 0046 0190     		str	r0, [sp, #4]
+ 1587              	.L119:
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1588              		.loc 1 1397 10 is_stmt 1 view .LVU510
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1589              		.loc 1 1397 19 is_stmt 0 view .LVU511
+ 1590 0048 0198     		ldr	r0, [sp, #4]
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1591              		.loc 1 1397 10 view .LVU512
+ 1592 004a 0028     		cmp	r0, #0
+ 1593 004c F9D1     		bne	.L120
+ 1594              	.L118:
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1595              		.loc 1 1404 3 is_stmt 1 view .LVU513
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1596              		.loc 1 1404 6 is_stmt 0 view .LVU514
+ 1597 004e 2068     		ldr	r0, [r4]
+ 1598 0050 8268     		ldr	r2, [r0, #8]
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1599              		.loc 1 1404 5 view .LVU515
+ 1600 0052 12F0010F 		tst	r2, #1
+ 1601 0056 6DD0     		beq	.L121
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ 1602              		.loc 1 1409 5 is_stmt 1 view .LVU516
+ 1603 0058 256C     		ldr	r5, [r4, #64]
+ 1604 005a 424A     		ldr	r2, .L135+8
+ARM GAS  /tmp/ccHbw826.s 			page 71
+
+
+ 1605 005c 2A40     		ands	r2, r2, r5
+ 1606 005e 42F48072 		orr	r2, r2, #256
+ 1607 0062 2264     		str	r2, [r4, #64]
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1608              		.loc 1 1415 5 view .LVU517
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1609              		.loc 1 1415 9 is_stmt 0 view .LVU518
+ 1610 0064 4268     		ldr	r2, [r0, #4]
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1611              		.loc 1 1415 8 view .LVU519
+ 1612 0066 12F4806F 		tst	r2, #1024
+ 1613 006a 05D0     		beq	.L122
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 1614              		.loc 1 1417 7 is_stmt 1 view .LVU520
+ 1615 006c 226C     		ldr	r2, [r4, #64]
+ 1616 006e 22F44052 		bic	r2, r2, #12288
+ 1617 0072 42F48052 		orr	r2, r2, #4096
+ 1618 0076 2264     		str	r2, [r4, #64]
+ 1619              	.L122:
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1620              		.loc 1 1421 5 view .LVU521
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1621              		.loc 1 1421 9 is_stmt 0 view .LVU522
+ 1622 0078 226C     		ldr	r2, [r4, #64]
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1623              		.loc 1 1421 8 view .LVU523
+ 1624 007a 12F4805F 		tst	r2, #4096
+ 1625 007e 34D0     		beq	.L123
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 1626              		.loc 1 1424 7 is_stmt 1 view .LVU524
+ 1627 0080 626C     		ldr	r2, [r4, #68]
+ 1628 0082 22F00602 		bic	r2, r2, #6
+ 1629 0086 6264     		str	r2, [r4, #68]
+ 1630              	.L124:
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1631              		.loc 1 1435 5 view .LVU525
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1632              		.loc 1 1435 5 view .LVU526
+ 1633 0088 0022     		movs	r2, #0
+ 1634 008a 84F83C20 		strb	r2, [r4, #60]
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1635              		.loc 1 1435 5 view .LVU527
+1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1636              		.loc 1 1438 5 view .LVU528
+1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1637              		.loc 1 1438 9 is_stmt 0 view .LVU529
+ 1638 008e A26B     		ldr	r2, [r4, #56]
+1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1639              		.loc 1 1438 40 view .LVU530
+ 1640 0090 3548     		ldr	r0, .L135+12
+ 1641 0092 D063     		str	r0, [r2, #60]
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1642              		.loc 1 1441 5 is_stmt 1 view .LVU531
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1643              		.loc 1 1441 9 is_stmt 0 view .LVU532
+ 1644 0094 A26B     		ldr	r2, [r4, #56]
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ARM GAS  /tmp/ccHbw826.s 			page 72
+
+
+ 1645              		.loc 1 1441 44 view .LVU533
+ 1646 0096 3548     		ldr	r0, .L135+16
+ 1647 0098 1064     		str	r0, [r2, #64]
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1648              		.loc 1 1444 5 is_stmt 1 view .LVU534
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1649              		.loc 1 1444 9 is_stmt 0 view .LVU535
+ 1650 009a A26B     		ldr	r2, [r4, #56]
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1651              		.loc 1 1444 41 view .LVU536
+ 1652 009c 3448     		ldr	r0, .L135+20
+ 1653 009e D064     		str	r0, [r2, #76]
+1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1654              		.loc 1 1452 5 is_stmt 1 view .LVU537
+ 1655 00a0 2268     		ldr	r2, [r4]
+ 1656 00a2 6FF02200 		mvn	r0, #34
+ 1657 00a6 1060     		str	r0, [r2]
+1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1658              		.loc 1 1455 5 view .LVU538
+ 1659 00a8 2068     		ldr	r0, [r4]
+ 1660 00aa 4268     		ldr	r2, [r0, #4]
+ 1661 00ac 42F08062 		orr	r2, r2, #67108864
+ 1662 00b0 4260     		str	r2, [r0, #4]
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1663              		.loc 1 1458 5 view .LVU539
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1664              		.loc 1 1458 9 is_stmt 0 view .LVU540
+ 1665 00b2 2068     		ldr	r0, [r4]
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1666              		.loc 1 1458 25 view .LVU541
+ 1667 00b4 8268     		ldr	r2, [r0, #8]
+ 1668 00b6 42F48072 		orr	r2, r2, #256
+ 1669 00ba 8260     		str	r2, [r0, #8]
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1670              		.loc 1 1461 5 is_stmt 1 view .LVU542
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1671              		.loc 1 1461 55 is_stmt 0 view .LVU543
+ 1672 00bc 2068     		ldr	r0, [r4]
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1673              		.loc 1 1461 5 view .LVU544
+ 1674 00be 0A46     		mov	r2, r1
+ 1675 00c0 00F14C01 		add	r1, r0, #76
+ 1676              	.LVL76:
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1677              		.loc 1 1461 5 view .LVU545
+ 1678 00c4 A06B     		ldr	r0, [r4, #56]
+ 1679 00c6 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 1680              	.LVL77:
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1681              		.loc 1 1464 5 is_stmt 1 view .LVU546
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1682              		.loc 1 1464 8 is_stmt 0 view .LVU547
+ 1683 00ca 2A4B     		ldr	r3, .L135+24
+ 1684 00cc 5B68     		ldr	r3, [r3, #4]
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1685              		.loc 1 1464 7 view .LVU548
+ 1686 00ce 13F01F0F 		tst	r3, #31
+ARM GAS  /tmp/ccHbw826.s 			page 73
+
+
+ 1687 00d2 0DD1     		bne	.L125
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1688              		.loc 1 1467 7 is_stmt 1 view .LVU549
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1689              		.loc 1 1467 15 is_stmt 0 view .LVU550
+ 1690 00d4 2368     		ldr	r3, [r4]
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1691              		.loc 1 1467 25 view .LVU551
+ 1692 00d6 9A68     		ldr	r2, [r3, #8]
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1693              		.loc 1 1467 9 view .LVU552
+ 1694 00d8 12F0405F 		tst	r2, #805306368
+ 1695 00dc 37D1     		bne	.L128
+1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 1696              		.loc 1 1470 9 is_stmt 1 view .LVU553
+1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 1697              		.loc 1 1470 29 is_stmt 0 view .LVU554
+ 1698 00de 9A68     		ldr	r2, [r3, #8]
+ 1699 00e0 42F08042 		orr	r2, r2, #1073741824
+ 1700 00e4 9A60     		str	r2, [r3, #8]
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1701              		.loc 1 1504 10 view .LVU555
+ 1702 00e6 0020     		movs	r0, #0
+ 1703 00e8 2DE0     		b	.L117
+ 1704              	.LVL78:
+ 1705              	.L123:
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 1706              		.loc 1 1429 7 is_stmt 1 view .LVU556
+ 1707 00ea 0022     		movs	r2, #0
+ 1708 00ec 6264     		str	r2, [r4, #68]
+ 1709 00ee CBE7     		b	.L124
+ 1710              	.LVL79:
+ 1711              	.L125:
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1712              		.loc 1 1476 7 view .LVU557
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1713              		.loc 1 1476 15 is_stmt 0 view .LVU558
+ 1714 00f0 2368     		ldr	r3, [r4]
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1715              		.loc 1 1476 9 view .LVU559
+ 1716 00f2 214A     		ldr	r2, .L135+28
+ 1717 00f4 9342     		cmp	r3, r2
+ 1718 00f6 0AD0     		beq	.L133
+ 1719              	.L126:
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1720              		.loc 1 1483 7 is_stmt 1 view .LVU560
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1721              		.loc 1 1483 11 is_stmt 0 view .LVU561
+ 1722 00f8 1E4B     		ldr	r3, .L135+24
+ 1723 00fa 5B68     		ldr	r3, [r3, #4]
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1724              		.loc 1 1483 9 view .LVU562
+ 1725 00fc 13F0100F 		tst	r3, #16
+ 1726 0100 27D1     		bne	.L129
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1727              		.loc 1 1486 9 is_stmt 1 view .LVU563
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ARM GAS  /tmp/ccHbw826.s 			page 74
+
+
+ 1728              		.loc 1 1486 17 is_stmt 0 view .LVU564
+ 1729 0102 2368     		ldr	r3, [r4]
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1730              		.loc 1 1486 11 view .LVU565
+ 1731 0104 1D4A     		ldr	r2, .L135+32
+ 1732 0106 9342     		cmp	r3, r2
+ 1733 0108 0AD0     		beq	.L134
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1734              		.loc 1 1504 10 view .LVU566
+ 1735 010a 0020     		movs	r0, #0
+ 1736 010c 1BE0     		b	.L117
+ 1737              	.L133:
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1738              		.loc 1 1476 54 discriminator 1 view .LVU567
+ 1739 010e 9A68     		ldr	r2, [r3, #8]
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1740              		.loc 1 1476 35 discriminator 1 view .LVU568
+ 1741 0110 12F0405F 		tst	r2, #805306368
+ 1742 0114 F0D1     		bne	.L126
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 1743              		.loc 1 1479 11 is_stmt 1 view .LVU569
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 1744              		.loc 1 1479 31 is_stmt 0 view .LVU570
+ 1745 0116 9A68     		ldr	r2, [r3, #8]
+ 1746 0118 42F08042 		orr	r2, r2, #1073741824
+ 1747 011c 9A60     		str	r2, [r3, #8]
+ 1748 011e EBE7     		b	.L126
+ 1749              	.L134:
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1750              		.loc 1 1486 56 discriminator 1 view .LVU571
+ 1751 0120 9A68     		ldr	r2, [r3, #8]
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         {
+ 1752              		.loc 1 1486 37 discriminator 1 view .LVU572
+ 1753 0122 12F0405F 		tst	r2, #805306368
+ 1754 0126 16D1     		bne	.L131
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 1755              		.loc 1 1489 11 is_stmt 1 view .LVU573
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         }
+ 1756              		.loc 1 1489 31 is_stmt 0 view .LVU574
+ 1757 0128 9A68     		ldr	r2, [r3, #8]
+ 1758 012a 42F08042 		orr	r2, r2, #1073741824
+ 1759 012e 9A60     		str	r2, [r3, #8]
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1760              		.loc 1 1504 10 view .LVU575
+ 1761 0130 0020     		movs	r0, #0
+ 1762 0132 08E0     		b	.L117
+ 1763              	.LVL80:
+ 1764              	.L121:
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1765              		.loc 1 1497 5 is_stmt 1 view .LVU576
+ 1766 0134 236C     		ldr	r3, [r4, #64]
+ 1767              	.LVL81:
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1768              		.loc 1 1497 5 is_stmt 0 view .LVU577
+ 1769 0136 43F01003 		orr	r3, r3, #16
+ 1770 013a 2364     		str	r3, [r4, #64]
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ARM GAS  /tmp/ccHbw826.s 			page 75
+
+
+ 1771              		.loc 1 1500 5 is_stmt 1 view .LVU578
+ 1772 013c 636C     		ldr	r3, [r4, #68]
+ 1773 013e 43F00103 		orr	r3, r3, #1
+ 1774 0142 6364     		str	r3, [r4, #68]
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1775              		.loc 1 1504 10 is_stmt 0 view .LVU579
+ 1776 0144 0020     		movs	r0, #0
+ 1777              	.LVL82:
+ 1778              	.L117:
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1779              		.loc 1 1505 1 view .LVU580
+ 1780 0146 03B0     		add	sp, sp, #12
+ 1781              	.LCFI14:
+ 1782              		.cfi_remember_state
+ 1783              		.cfi_def_cfa_offset 12
+ 1784              		@ sp needed
+ 1785 0148 30BD     		pop	{r4, r5, pc}
+ 1786              	.LVL83:
+ 1787              	.L127:
+ 1788              	.LCFI15:
+ 1789              		.cfi_restore_state
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1790              		.loc 1 1384 3 view .LVU581
+ 1791 014a 0220     		movs	r0, #2
+ 1792              	.LVL84:
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1793              		.loc 1 1384 3 view .LVU582
+ 1794 014c FBE7     		b	.L117
+ 1795              	.LVL85:
+ 1796              	.L128:
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1797              		.loc 1 1504 10 view .LVU583
+ 1798 014e 0020     		movs	r0, #0
+ 1799 0150 F9E7     		b	.L117
+ 1800              	.L129:
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1801              		.loc 1 1504 10 view .LVU584
+ 1802 0152 0020     		movs	r0, #0
+ 1803 0154 F7E7     		b	.L117
+ 1804              	.L131:
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1805              		.loc 1 1504 10 view .LVU585
+ 1806 0156 0020     		movs	r0, #0
+ 1807 0158 F5E7     		b	.L117
+ 1808              	.L136:
+ 1809 015a 00BF     		.align	2
+ 1810              	.L135:
+ 1811 015c 00000000 		.word	SystemCoreClock
+ 1812 0160 83DE1B43 		.word	1125899907
+ 1813 0164 FEF8FFFF 		.word	-1794
+ 1814 0168 00000000 		.word	ADC_DMAConvCplt
+ 1815 016c 00000000 		.word	ADC_DMAHalfConvCplt
+ 1816 0170 00000000 		.word	ADC_DMAError
+ 1817 0174 00230140 		.word	1073816320
+ 1818 0178 00200140 		.word	1073815552
+ 1819 017c 00220140 		.word	1073816064
+ 1820              		.cfi_endproc
+ARM GAS  /tmp/ccHbw826.s 			page 76
+
+
+ 1821              	.LFE152:
+ 1823              		.section	.text.HAL_ADC_Stop_DMA,"ax",%progbits
+ 1824              		.align	1
+ 1825              		.global	HAL_ADC_Stop_DMA
+ 1826              		.syntax unified
+ 1827              		.thumb
+ 1828              		.thumb_func
+ 1829              		.fpu fpv5-d16
+ 1831              	HAL_ADC_Stop_DMA:
+ 1832              	.LVL86:
+ 1833              	.LFB153:
+1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 1834              		.loc 1 1514 1 is_stmt 1 view -0
+ 1835              		.cfi_startproc
+ 1836              		@ args = 0, pretend = 0, frame = 0
+ 1837              		@ frame_needed = 0, uses_anonymous_args = 0
+1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1838              		.loc 1 1515 3 view .LVU587
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1839              		.loc 1 1518 3 view .LVU588
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1840              		.loc 1 1521 3 view .LVU589
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1841              		.loc 1 1521 3 view .LVU590
+ 1842 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 1843 0004 012B     		cmp	r3, #1
+ 1844 0006 33D0     		beq	.L141
+1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 1845              		.loc 1 1514 1 is_stmt 0 discriminator 2 view .LVU591
+ 1846 0008 10B5     		push	{r4, lr}
+ 1847              	.LCFI16:
+ 1848              		.cfi_def_cfa_offset 8
+ 1849              		.cfi_offset 4, -8
+ 1850              		.cfi_offset 14, -4
+ 1851 000a 0446     		mov	r4, r0
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1852              		.loc 1 1521 3 is_stmt 1 discriminator 2 view .LVU592
+ 1853 000c 0123     		movs	r3, #1
+ 1854 000e 80F83C30 		strb	r3, [r0, #60]
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1855              		.loc 1 1521 3 discriminator 2 view .LVU593
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1856              		.loc 1 1525 3 discriminator 2 view .LVU594
+ 1857 0012 0268     		ldr	r2, [r0]
+ 1858 0014 9368     		ldr	r3, [r2, #8]
+ 1859 0016 23F00103 		bic	r3, r3, #1
+ 1860 001a 9360     		str	r3, [r2, #8]
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1861              		.loc 1 1528 3 discriminator 2 view .LVU595
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1862              		.loc 1 1528 6 is_stmt 0 discriminator 2 view .LVU596
+ 1863 001c 0368     		ldr	r3, [r0]
+ 1864 001e 9A68     		ldr	r2, [r3, #8]
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 1865              		.loc 1 1528 5 discriminator 2 view .LVU597
+ 1866 0020 12F0010F 		tst	r2, #1
+ 1867 0024 1FD1     		bne	.L142
+ARM GAS  /tmp/ccHbw826.s 			page 77
+
+
+1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1868              		.loc 1 1531 5 is_stmt 1 view .LVU598
+1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1869              		.loc 1 1531 25 is_stmt 0 view .LVU599
+ 1870 0026 9A68     		ldr	r2, [r3, #8]
+ 1871 0028 22F48072 		bic	r2, r2, #256
+ 1872 002c 9A60     		str	r2, [r3, #8]
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1873              		.loc 1 1535 5 is_stmt 1 view .LVU600
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1874              		.loc 1 1535 13 is_stmt 0 view .LVU601
+ 1875 002e 806B     		ldr	r0, [r0, #56]
+ 1876              	.LVL87:
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1877              		.loc 1 1535 25 view .LVU602
+ 1878 0030 90F83530 		ldrb	r3, [r0, #53]	@ zero_extendqisi2
+ 1879 0034 DBB2     		uxtb	r3, r3
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 1880              		.loc 1 1535 8 view .LVU603
+ 1881 0036 022B     		cmp	r3, #2
+ 1882 0038 0CD0     		beq	.L148
+1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1883              		.loc 1 1515 21 view .LVU604
+ 1884 003a 0020     		movs	r0, #0
+ 1885              	.LVL88:
+ 1886              	.L140:
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 1887              		.loc 1 1548 5 is_stmt 1 view .LVU605
+ 1888 003c 2268     		ldr	r2, [r4]
+ 1889 003e 5368     		ldr	r3, [r2, #4]
+ 1890 0040 23F08063 		bic	r3, r3, #67108864
+ 1891 0044 5360     		str	r3, [r2, #4]
+1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 1892              		.loc 1 1551 5 view .LVU606
+ 1893 0046 226C     		ldr	r2, [r4, #64]
+ 1894 0048 0A4B     		ldr	r3, .L149
+ 1895 004a 1340     		ands	r3, r3, r2
+ 1896 004c 43F00103 		orr	r3, r3, #1
+ 1897 0050 2364     		str	r3, [r4, #64]
+ 1898 0052 09E0     		b	.L139
+ 1899              	.LVL89:
+ 1900              	.L148:
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+ 1901              		.loc 1 1537 7 view .LVU607
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+ 1902              		.loc 1 1537 24 is_stmt 0 view .LVU608
+ 1903 0054 FFF7FEFF 		bl	HAL_DMA_Abort
+ 1904              	.LVL90:
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1905              		.loc 1 1540 7 is_stmt 1 view .LVU609
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 1906              		.loc 1 1540 10 is_stmt 0 view .LVU610
+ 1907 0058 0028     		cmp	r0, #0
+ 1908 005a EFD0     		beq	.L140
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 1909              		.loc 1 1543 9 is_stmt 1 view .LVU611
+ 1910 005c 236C     		ldr	r3, [r4, #64]
+ARM GAS  /tmp/ccHbw826.s 			page 78
+
+
+ 1911 005e 43F04003 		orr	r3, r3, #64
+ 1912 0062 2364     		str	r3, [r4, #64]
+ 1913 0064 EAE7     		b	.L140
+ 1914              	.LVL91:
+ 1915              	.L142:
+1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1916              		.loc 1 1515 21 is_stmt 0 view .LVU612
+ 1917 0066 0020     		movs	r0, #0
+ 1918              	.LVL92:
+ 1919              	.L139:
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1920              		.loc 1 1557 3 is_stmt 1 view .LVU613
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1921              		.loc 1 1557 3 view .LVU614
+ 1922 0068 0023     		movs	r3, #0
+ 1923 006a 84F83C30 		strb	r3, [r4, #60]
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1924              		.loc 1 1557 3 view .LVU615
+1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1925              		.loc 1 1560 3 view .LVU616
+1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1926              		.loc 1 1561 1 is_stmt 0 view .LVU617
+ 1927 006e 10BD     		pop	{r4, pc}
+ 1928              	.LVL93:
+ 1929              	.L141:
+ 1930              	.LCFI17:
+ 1931              		.cfi_def_cfa_offset 0
+ 1932              		.cfi_restore 4
+ 1933              		.cfi_restore 14
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 1934              		.loc 1 1521 3 view .LVU618
+ 1935 0070 0220     		movs	r0, #2
+ 1936              	.LVL94:
+1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1937              		.loc 1 1561 1 view .LVU619
+ 1938 0072 7047     		bx	lr
+ 1939              	.L150:
+ 1940              		.align	2
+ 1941              	.L149:
+ 1942 0074 FEEEFFFF 		.word	-4354
+ 1943              		.cfi_endproc
+ 1944              	.LFE153:
+ 1946              		.section	.text.HAL_ADC_GetValue,"ax",%progbits
+ 1947              		.align	1
+ 1948              		.global	HAL_ADC_GetValue
+ 1949              		.syntax unified
+ 1950              		.thumb
+ 1951              		.thumb_func
+ 1952              		.fpu fpv5-d16
+ 1954              	HAL_ADC_GetValue:
+ 1955              	.LVL95:
+ 1956              	.LFB154:
+1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return the selected ADC converted value */ 
+ 1957              		.loc 1 1570 1 is_stmt 1 view -0
+ 1958              		.cfi_startproc
+ 1959              		@ args = 0, pretend = 0, frame = 0
+ 1960              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccHbw826.s 			page 79
+
+
+ 1961              		@ link register save eliminated.
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1962              		.loc 1 1572 3 view .LVU621
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1963              		.loc 1 1572 14 is_stmt 0 view .LVU622
+ 1964 0000 0368     		ldr	r3, [r0]
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 1965              		.loc 1 1572 24 view .LVU623
+ 1966 0002 D86C     		ldr	r0, [r3, #76]
+ 1967              	.LVL96:
+1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1968              		.loc 1 1573 1 view .LVU624
+ 1969 0004 7047     		bx	lr
+ 1970              		.cfi_endproc
+ 1971              	.LFE154:
+ 1973              		.section	.text.HAL_ADC_ConvCpltCallback,"ax",%progbits
+ 1974              		.align	1
+ 1975              		.weak	HAL_ADC_ConvCpltCallback
+ 1976              		.syntax unified
+ 1977              		.thumb
+ 1978              		.thumb_func
+ 1979              		.fpu fpv5-d16
+ 1981              	HAL_ADC_ConvCpltCallback:
+ 1982              	.LVL97:
+ 1983              	.LFB155:
+1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 1984              		.loc 1 1582 1 is_stmt 1 view -0
+ 1985              		.cfi_startproc
+ 1986              		@ args = 0, pretend = 0, frame = 0
+ 1987              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1988              		@ link register save eliminated.
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 1989              		.loc 1 1584 3 view .LVU626
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 1990              		.loc 1 1588 1 is_stmt 0 view .LVU627
+ 1991 0000 7047     		bx	lr
+ 1992              		.cfi_endproc
+ 1993              	.LFE155:
+ 1995              		.section	.text.HAL_ADC_ConvHalfCpltCallback,"ax",%progbits
+ 1996              		.align	1
+ 1997              		.weak	HAL_ADC_ConvHalfCpltCallback
+ 1998              		.syntax unified
+ 1999              		.thumb
+ 2000              		.thumb_func
+ 2001              		.fpu fpv5-d16
+ 2003              	HAL_ADC_ConvHalfCpltCallback:
+ 2004              	.LVL98:
+ 2005              	.LFB156:
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 2006              		.loc 1 1597 1 is_stmt 1 view -0
+ 2007              		.cfi_startproc
+ 2008              		@ args = 0, pretend = 0, frame = 0
+ 2009              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2010              		@ link register save eliminated.
+1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 2011              		.loc 1 1599 3 view .LVU629
+1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ARM GAS  /tmp/ccHbw826.s 			page 80
+
+
+ 2012              		.loc 1 1603 1 is_stmt 0 view .LVU630
+ 2013 0000 7047     		bx	lr
+ 2014              		.cfi_endproc
+ 2015              	.LFE156:
+ 2017              		.section	.text.ADC_DMAHalfConvCplt,"ax",%progbits
+ 2018              		.align	1
+ 2019              		.syntax unified
+ 2020              		.thumb
+ 2021              		.thumb_func
+ 2022              		.fpu fpv5-d16
+ 2024              	ADC_DMAHalfConvCplt:
+ 2025              	.LVL99:
+ 2026              	.LFB165:
+1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  DMA transfer complete callback. 
+1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *                the configuration information for the specified DMA module.
+1996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval None
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+1998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)   
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Retrieve ADC handle corresponding to current DMA handle */
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Update state machine on conversion status if not in error state */
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Update ADC state machine */
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Determine whether any further conversion upcoming on group regular   */
+2010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* by external trigger, continuous mode or scan sequence on going.      */
+2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Note: On STM32F7, there is no independent flag of end of sequence.   */
+2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /*       The test of scan sequence on going is done either with scan    */
+2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /*       sequence disabled or with end of conversion flag set to        */
+2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /*       of end of sequence.                                            */
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+2020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Disable ADC end of single conversion interrupt on group regular */
+2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
+2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* by overrun IRQ process below.                                      */
+2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+2026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Set ADC state */
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
+2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ARM GAS  /tmp/ccHbw826.s 			page 81
+
+
+2035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     /* Conversion complete callback */
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     hadc->ConvCpltCallback(hadc);
+2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     HAL_ADC_ConvCpltCallback(hadc);
+2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   else /* DMA and-or internal error occurred */
+2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+2045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+2046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Call HAL ADC Error Callback function */
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       hadc->ErrorCallback(hadc);
+2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       HAL_ADC_ErrorCallback(hadc);
+2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     else
+2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       /* Call DMA error callback */
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       hadc->DMA_Handle->XferErrorCallback(hdma);
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  DMA half transfer complete callback. 
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *                the configuration information for the specified DMA module.
+2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval None
+2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
+2068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 2027              		.loc 1 2068 1 is_stmt 1 view -0
+ 2028              		.cfi_startproc
+ 2029              		@ args = 0, pretend = 0, frame = 0
+ 2030              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2031              		.loc 1 2068 1 is_stmt 0 view .LVU632
+ 2032 0000 08B5     		push	{r3, lr}
+ 2033              	.LCFI18:
+ 2034              		.cfi_def_cfa_offset 8
+ 2035              		.cfi_offset 3, -8
+ 2036              		.cfi_offset 14, -4
+2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ 2037              		.loc 1 2069 3 is_stmt 1 view .LVU633
+ 2038              	.LVL100:
+2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****    /* Half conversion callback */
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->ConvHalfCpltCallback(hadc);
+2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else
+2074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_ADC_ConvHalfCpltCallback(hadc);
+ 2039              		.loc 1 2074 3 view .LVU634
+ 2040 0002 806B     		ldr	r0, [r0, #56]
+ 2041              	.LVL101:
+ 2042              		.loc 1 2074 3 is_stmt 0 view .LVU635
+ 2043 0004 FFF7FEFF 		bl	HAL_ADC_ConvHalfCpltCallback
+ARM GAS  /tmp/ccHbw826.s 			page 82
+
+
+ 2044              	.LVL102:
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 2045              		.loc 1 2076 1 view .LVU636
+ 2046 0008 08BD     		pop	{r3, pc}
+ 2047              		.cfi_endproc
+ 2048              	.LFE165:
+ 2050              		.section	.text.HAL_ADC_LevelOutOfWindowCallback,"ax",%progbits
+ 2051              		.align	1
+ 2052              		.weak	HAL_ADC_LevelOutOfWindowCallback
+ 2053              		.syntax unified
+ 2054              		.thumb
+ 2055              		.thumb_func
+ 2056              		.fpu fpv5-d16
+ 2058              	HAL_ADC_LevelOutOfWindowCallback:
+ 2059              	.LVL103:
+ 2060              	.LFB157:
+1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 2061              		.loc 1 1612 1 is_stmt 1 view -0
+ 2062              		.cfi_startproc
+ 2063              		@ args = 0, pretend = 0, frame = 0
+ 2064              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2065              		@ link register save eliminated.
+1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 2066              		.loc 1 1614 3 view .LVU638
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2067              		.loc 1 1618 1 is_stmt 0 view .LVU639
+ 2068 0000 7047     		bx	lr
+ 2069              		.cfi_endproc
+ 2070              	.LFE157:
+ 2072              		.section	.text.HAL_ADC_ErrorCallback,"ax",%progbits
+ 2073              		.align	1
+ 2074              		.weak	HAL_ADC_ErrorCallback
+ 2075              		.syntax unified
+ 2076              		.thumb
+ 2077              		.thumb_func
+ 2078              		.fpu fpv5-d16
+ 2080              	HAL_ADC_ErrorCallback:
+ 2081              	.LVL104:
+ 2082              	.LFB158:
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Prevent unused argument(s) compilation warning */
+ 2083              		.loc 1 1633 1 is_stmt 1 view -0
+ 2084              		.cfi_startproc
+ 2085              		@ args = 0, pretend = 0, frame = 0
+ 2086              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2087              		@ link register save eliminated.
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 2088              		.loc 1 1635 3 view .LVU641
+1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2089              		.loc 1 1639 1 is_stmt 0 view .LVU642
+ 2090 0000 7047     		bx	lr
+ 2091              		.cfi_endproc
+ 2092              	.LFE158:
+ 2094              		.section	.text.HAL_ADC_IRQHandler,"ax",%progbits
+ 2095              		.align	1
+ 2096              		.global	HAL_ADC_IRQHandler
+ 2097              		.syntax unified
+ARM GAS  /tmp/ccHbw826.s 			page 83
+
+
+ 2098              		.thumb
+ 2099              		.thumb_func
+ 2100              		.fpu fpv5-d16
+ 2102              	HAL_ADC_IRQHandler:
+ 2103              	.LVL105:
+ 2104              	.LFB151:
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tmp1 = 0, tmp2 = 0;
+ 2105              		.loc 1 1210 1 is_stmt 1 view -0
+ 2106              		.cfi_startproc
+ 2107              		@ args = 0, pretend = 0, frame = 0
+ 2108              		@ frame_needed = 0, uses_anonymous_args = 0
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tmp1 = 0, tmp2 = 0;
+ 2109              		.loc 1 1210 1 is_stmt 0 view .LVU644
+ 2110 0000 70B5     		push	{r4, r5, r6, lr}
+ 2111              	.LCFI19:
+ 2112              		.cfi_def_cfa_offset 16
+ 2113              		.cfi_offset 4, -16
+ 2114              		.cfi_offset 5, -12
+ 2115              		.cfi_offset 6, -8
+ 2116              		.cfi_offset 14, -4
+ 2117 0002 0446     		mov	r4, r0
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2118              		.loc 1 1211 3 is_stmt 1 view .LVU645
+ 2119              	.LVL106:
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tmp_cr1 = hadc->Instance->CR1;
+ 2120              		.loc 1 1213 3 view .LVU646
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tmp_cr1 = hadc->Instance->CR1;
+ 2121              		.loc 1 1213 25 is_stmt 0 view .LVU647
+ 2122 0004 0368     		ldr	r3, [r0]
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   uint32_t tmp_cr1 = hadc->Instance->CR1;
+ 2123              		.loc 1 1213 12 view .LVU648
+ 2124 0006 1E68     		ldr	r6, [r3]
+ 2125              	.LVL107:
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2126              		.loc 1 1214 3 is_stmt 1 view .LVU649
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2127              		.loc 1 1214 12 is_stmt 0 view .LVU650
+ 2128 0008 5D68     		ldr	r5, [r3, #4]
+ 2129              	.LVL108:
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
+ 2130              		.loc 1 1217 3 is_stmt 1 view .LVU651
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
+ 2131              		.loc 1 1218 3 view .LVU652
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2132              		.loc 1 1219 3 view .LVU653
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp2 = tmp_cr1 & ADC_IT_EOC;
+ 2133              		.loc 1 1221 3 view .LVU654
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2134              		.loc 1 1222 3 view .LVU655
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2135              		.loc 1 1225 3 view .LVU656
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2136              		.loc 1 1225 11 is_stmt 0 view .LVU657
+ 2137 000a C5F34012 		ubfx	r2, r5, #5, #1
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2138              		.loc 1 1225 5 view .LVU658
+ 2139 000e 12EA5602 		ands	r2, r2, r6, lsr #1
+ARM GAS  /tmp/ccHbw826.s 			page 84
+
+
+ 2140 0012 2CD0     		beq	.L159
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2141              		.loc 1 1228 5 is_stmt 1 view .LVU659
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2142              		.loc 1 1228 9 is_stmt 0 view .LVU660
+ 2143 0014 026C     		ldr	r2, [r0, #64]
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2144              		.loc 1 1228 8 view .LVU661
+ 2145 0016 12F0100F 		tst	r2, #16
+ 2146 001a 03D1     		bne	.L160
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2147              		.loc 1 1231 7 is_stmt 1 view .LVU662
+ 2148 001c 026C     		ldr	r2, [r0, #64]
+ 2149 001e 42F40072 		orr	r2, r2, #512
+ 2150 0022 0264     		str	r2, [r0, #64]
+ 2151              	.L160:
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 2152              		.loc 1 1240 5 view .LVU663
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 2153              		.loc 1 1240 8 is_stmt 0 view .LVU664
+ 2154 0024 9A68     		ldr	r2, [r3, #8]
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 2155              		.loc 1 1240 7 view .LVU665
+ 2156 0026 12F0405F 		tst	r2, #805306368
+ 2157 002a 19D1     		bne	.L161
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+ 2158              		.loc 1 1241 19 discriminator 1 view .LVU666
+ 2159 002c A269     		ldr	r2, [r4, #24]
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 2160              		.loc 1 1240 62 discriminator 1 view .LVU667
+ 2161 002e BAB9     		cbnz	r2, .L161
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+ 2162              		.loc 1 1242 9 view .LVU668
+ 2163 0030 DA6A     		ldr	r2, [r3, #44]
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+ 2164              		.loc 1 1241 62 view .LVU669
+ 2165 0032 12F4700F 		tst	r2, #15728640
+ 2166 0036 03D0     		beq	.L162
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2167              		.loc 1 1243 9 view .LVU670
+ 2168 0038 9A68     		ldr	r2, [r3, #8]
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+ 2169              		.loc 1 1242 58 view .LVU671
+ 2170 003a 12F4806F 		tst	r2, #1024
+ 2171 003e 0FD1     		bne	.L161
+ 2172              	.L162:
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+ 2173              		.loc 1 1249 7 is_stmt 1 view .LVU672
+ 2174 0040 5A68     		ldr	r2, [r3, #4]
+ 2175 0042 22F02002 		bic	r2, r2, #32
+ 2176 0046 5A60     		str	r2, [r3, #4]
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+ 2177              		.loc 1 1252 7 view .LVU673
+ 2178 0048 236C     		ldr	r3, [r4, #64]
+ 2179 004a 23F48073 		bic	r3, r3, #256
+ 2180 004e 2364     		str	r3, [r4, #64]
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ARM GAS  /tmp/ccHbw826.s 			page 85
+
+
+ 2181              		.loc 1 1254 7 view .LVU674
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 2182              		.loc 1 1254 11 is_stmt 0 view .LVU675
+ 2183 0050 236C     		ldr	r3, [r4, #64]
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 2184              		.loc 1 1254 10 view .LVU676
+ 2185 0052 13F4805F 		tst	r3, #4096
+ 2186 0056 03D1     		bne	.L161
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 2187              		.loc 1 1256 9 is_stmt 1 view .LVU677
+ 2188 0058 236C     		ldr	r3, [r4, #64]
+ 2189 005a 43F00103 		orr	r3, r3, #1
+ 2190 005e 2364     		str	r3, [r4, #64]
+ 2191              	.L161:
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2192              		.loc 1 1264 5 view .LVU678
+ 2193 0060 2046     		mov	r0, r4
+ 2194              	.LVL109:
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2195              		.loc 1 1264 5 is_stmt 0 view .LVU679
+ 2196 0062 FFF7FEFF 		bl	HAL_ADC_ConvCpltCallback
+ 2197              	.LVL110:
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2198              		.loc 1 1268 5 is_stmt 1 view .LVU680
+ 2199 0066 2368     		ldr	r3, [r4]
+ 2200 0068 6FF01202 		mvn	r2, #18
+ 2201 006c 1A60     		str	r2, [r3]
+ 2202              	.L159:
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp2 = tmp_cr1 & ADC_IT_JEOC;
+ 2203              		.loc 1 1271 3 view .LVU681
+ 2204              	.LVL111:
+1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check End of conversion flag for injected channels */
+ 2205              		.loc 1 1272 3 view .LVU682
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2206              		.loc 1 1274 3 view .LVU683
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2207              		.loc 1 1274 11 is_stmt 0 view .LVU684
+ 2208 006e C5F3C013 		ubfx	r3, r5, #7, #1
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2209              		.loc 1 1274 5 view .LVU685
+ 2210 0072 13EA9603 		ands	r3, r3, r6, lsr #2
+ 2211 0076 35D0     		beq	.L163
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2212              		.loc 1 1277 5 is_stmt 1 view .LVU686
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2213              		.loc 1 1277 9 is_stmt 0 view .LVU687
+ 2214 0078 236C     		ldr	r3, [r4, #64]
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2215              		.loc 1 1277 8 view .LVU688
+ 2216 007a 13F0100F 		tst	r3, #16
+ 2217 007e 03D1     		bne	.L164
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2218              		.loc 1 1280 7 is_stmt 1 view .LVU689
+ 2219 0080 236C     		ldr	r3, [r4, #64]
+ 2220 0082 43F40053 		orr	r3, r3, #8192
+ 2221 0086 2364     		str	r3, [r4, #64]
+ 2222              	.L164:
+ARM GAS  /tmp/ccHbw826.s 			page 86
+
+
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+ 2223              		.loc 1 1287 5 view .LVU690
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+ 2224              		.loc 1 1287 8 is_stmt 0 view .LVU691
+ 2225 0088 2368     		ldr	r3, [r4]
+ 2226 008a 9A68     		ldr	r2, [r3, #8]
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+ 2227              		.loc 1 1287 7 view .LVU692
+ 2228 008c 12F4401F 		tst	r2, #3145728
+ 2229 0090 21D1     		bne	.L165
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
+ 2230              		.loc 1 1288 9 discriminator 1 view .LVU693
+ 2231 0092 9A6B     		ldr	r2, [r3, #56]
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+ 2232              		.loc 1 1287 64 discriminator 1 view .LVU694
+ 2233 0094 12F4401F 		tst	r2, #3145728
+ 2234 0098 03D0     		beq	.L166
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ 2235              		.loc 1 1289 9 view .LVU695
+ 2236 009a 9A68     		ldr	r2, [r3, #8]
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
+ 2237              		.loc 1 1288 59 view .LVU696
+ 2238 009c 12F4806F 		tst	r2, #1024
+ 2239 00a0 19D1     		bne	.L165
+ 2240              	.L166:
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ 2241              		.loc 1 1290 9 view .LVU697
+ 2242 00a2 5A68     		ldr	r2, [r3, #4]
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ 2243              		.loc 1 1289 60 view .LVU698
+ 2244 00a4 12F4806F 		tst	r2, #1024
+ 2245 00a8 15D1     		bne	.L165
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE))))
+ 2246              		.loc 1 1291 9 view .LVU699
+ 2247 00aa 9A68     		ldr	r2, [r3, #8]
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ 2248              		.loc 1 1290 60 view .LVU700
+ 2249 00ac 12F0405F 		tst	r2, #805306368
+ 2250 00b0 11D1     		bne	.L165
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2251              		.loc 1 1292 19 view .LVU701
+ 2252 00b2 A269     		ldr	r2, [r4, #24]
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE))))
+ 2253              		.loc 1 1291 45 view .LVU702
+ 2254 00b4 7AB9     		cbnz	r2, .L165
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+ 2255              		.loc 1 1295 7 is_stmt 1 view .LVU703
+ 2256 00b6 5A68     		ldr	r2, [r3, #4]
+ 2257 00b8 22F08002 		bic	r2, r2, #128
+ 2258 00bc 5A60     		str	r2, [r3, #4]
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2259              		.loc 1 1298 7 view .LVU704
+ 2260 00be 236C     		ldr	r3, [r4, #64]
+ 2261 00c0 23F48053 		bic	r3, r3, #4096
+ 2262 00c4 2364     		str	r3, [r4, #64]
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       { 
+ 2263              		.loc 1 1300 7 view .LVU705
+ARM GAS  /tmp/ccHbw826.s 			page 87
+
+
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       { 
+ 2264              		.loc 1 1300 11 is_stmt 0 view .LVU706
+ 2265 00c6 236C     		ldr	r3, [r4, #64]
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       { 
+ 2266              		.loc 1 1300 10 view .LVU707
+ 2267 00c8 13F4807F 		tst	r3, #256
+ 2268 00cc 03D1     		bne	.L165
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 2269              		.loc 1 1302 9 is_stmt 1 view .LVU708
+ 2270 00ce 236C     		ldr	r3, [r4, #64]
+ 2271 00d0 43F00103 		orr	r3, r3, #1
+ 2272 00d4 2364     		str	r3, [r4, #64]
+ 2273              	.L165:
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2274              		.loc 1 1310 7 view .LVU709
+ 2275 00d6 2046     		mov	r0, r4
+ 2276 00d8 FFF7FEFF 		bl	HAL_ADCEx_InjectedConvCpltCallback
+ 2277              	.LVL112:
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2278              		.loc 1 1314 5 view .LVU710
+ 2279 00dc 2368     		ldr	r3, [r4]
+ 2280 00de 6FF00C02 		mvn	r2, #12
+ 2281 00e2 1A60     		str	r2, [r3]
+ 2282              	.L163:
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp2 = tmp_cr1 & ADC_IT_AWD;
+ 2283              		.loc 1 1317 3 view .LVU711
+ 2284              	.LVL113:
+1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check Analog watchdog flag */
+ 2285              		.loc 1 1318 3 view .LVU712
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2286              		.loc 1 1320 3 view .LVU713
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2287              		.loc 1 1320 11 is_stmt 0 view .LVU714
+ 2288 00e4 C5F38013 		ubfx	r3, r5, #6, #1
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2289              		.loc 1 1320 5 view .LVU715
+ 2290 00e8 1E42     		tst	r6, r3
+ 2291 00ea 04D0     		beq	.L167
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2292              		.loc 1 1322 5 is_stmt 1 view .LVU716
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2293              		.loc 1 1322 8 is_stmt 0 view .LVU717
+ 2294 00ec 2368     		ldr	r3, [r4]
+ 2295 00ee 1B68     		ldr	r3, [r3]
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2296              		.loc 1 1322 7 view .LVU718
+ 2297 00f0 13F0010F 		tst	r3, #1
+ 2298 00f4 05D1     		bne	.L170
+ 2299              	.L167:
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   tmp2 = tmp_cr1 & ADC_IT_OVR;
+ 2300              		.loc 1 1340 3 is_stmt 1 view .LVU719
+ 2301              	.LVL114:
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Check Overrun flag */
+ 2302              		.loc 1 1341 3 view .LVU720
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2303              		.loc 1 1343 3 view .LVU721
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ARM GAS  /tmp/ccHbw826.s 			page 88
+
+
+ 2304              		.loc 1 1343 11 is_stmt 0 view .LVU722
+ 2305 00f6 C5F38065 		ubfx	r5, r5, #26, #1
+ 2306              	.LVL115:
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2307              		.loc 1 1343 5 view .LVU723
+ 2308 00fa 15EA5613 		ands	r3, r5, r6, lsr #5
+ 2309 00fe 0CD1     		bne	.L171
+ 2310              	.L158:
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2311              		.loc 1 1365 1 view .LVU724
+ 2312 0100 70BD     		pop	{r4, r5, r6, pc}
+ 2313              	.LVL116:
+ 2314              	.L170:
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+ 2315              		.loc 1 1325 7 is_stmt 1 view .LVU725
+ 2316 0102 236C     		ldr	r3, [r4, #64]
+ 2317 0104 43F48033 		orr	r3, r3, #65536
+ 2318 0108 2364     		str	r3, [r4, #64]
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2319              		.loc 1 1331 7 view .LVU726
+ 2320 010a 2046     		mov	r0, r4
+ 2321 010c FFF7FEFF 		bl	HAL_ADC_LevelOutOfWindowCallback
+ 2322              	.LVL117:
+1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2323              		.loc 1 1336 7 view .LVU727
+ 2324 0110 2368     		ldr	r3, [r4]
+ 2325 0112 6FF00102 		mvn	r2, #1
+ 2326 0116 1A60     		str	r2, [r3]
+ 2327 0118 EDE7     		b	.L167
+ 2328              	.LVL118:
+ 2329              	.L171:
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2330              		.loc 1 1350 5 view .LVU728
+ 2331 011a 636C     		ldr	r3, [r4, #68]
+ 2332 011c 43F00203 		orr	r3, r3, #2
+ 2333 0120 6364     		str	r3, [r4, #68]
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2334              		.loc 1 1353 5 view .LVU729
+ 2335 0122 2368     		ldr	r3, [r4]
+ 2336 0124 6FF02005 		mvn	r5, #32
+ 2337 0128 1D60     		str	r5, [r3]
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2338              		.loc 1 1359 7 view .LVU730
+ 2339 012a 2046     		mov	r0, r4
+ 2340 012c FFF7FEFF 		bl	HAL_ADC_ErrorCallback
+ 2341              	.LVL119:
+1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2342              		.loc 1 1363 5 view .LVU731
+ 2343 0130 2368     		ldr	r3, [r4]
+ 2344 0132 1D60     		str	r5, [r3]
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2345              		.loc 1 1365 1 is_stmt 0 view .LVU732
+ 2346 0134 E4E7     		b	.L158
+ 2347              		.cfi_endproc
+ 2348              	.LFE151:
+ 2350              		.section	.text.ADC_DMAError,"ax",%progbits
+ 2351              		.align	1
+ARM GAS  /tmp/ccHbw826.s 			page 89
+
+
+ 2352              		.syntax unified
+ 2353              		.thumb
+ 2354              		.thumb_func
+ 2355              		.fpu fpv5-d16
+ 2357              	ADC_DMAError:
+ 2358              	.LVL120:
+ 2359              	.LFB166:
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /**
+2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @brief  DMA error callback 
+2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   *                the configuration information for the specified DMA module.
+2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   * @retval None
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   */
+2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAError(DMA_HandleTypeDef *hdma)   
+2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** {
+ 2360              		.loc 1 2085 1 is_stmt 1 view -0
+ 2361              		.cfi_startproc
+ 2362              		@ args = 0, pretend = 0, frame = 0
+ 2363              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2364              		.loc 1 2085 1 is_stmt 0 view .LVU734
+ 2365 0000 08B5     		push	{r3, lr}
+ 2366              	.LCFI20:
+ 2367              		.cfi_def_cfa_offset 8
+ 2368              		.cfi_offset 3, -8
+ 2369              		.cfi_offset 14, -4
+2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ 2370              		.loc 1 2086 3 is_stmt 1 view .LVU735
+ 2371              		.loc 1 2086 22 is_stmt 0 view .LVU736
+ 2372 0002 806B     		ldr	r0, [r0, #56]
+ 2373              	.LVL121:
+2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->State= HAL_ADC_STATE_ERROR_DMA;
+ 2374              		.loc 1 2087 3 is_stmt 1 view .LVU737
+ 2375              		.loc 1 2087 14 is_stmt 0 view .LVU738
+ 2376 0004 4023     		movs	r3, #64
+ 2377 0006 0364     		str	r3, [r0, #64]
+2088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Set ADC error code to DMA error */
+2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+ 2378              		.loc 1 2089 3 is_stmt 1 view .LVU739
+ 2379              		.loc 1 2089 19 is_stmt 0 view .LVU740
+ 2380 0008 436C     		ldr	r3, [r0, #68]
+ 2381 000a 43F00403 		orr	r3, r3, #4
+ 2382 000e 4364     		str	r3, [r0, #68]
+2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Error callback */
+2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+2092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   hadc->ErrorCallback(hadc);
+2093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else
+2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   HAL_ADC_ErrorCallback(hadc);
+ 2383              		.loc 1 2094 3 is_stmt 1 view .LVU741
+ 2384 0010 FFF7FEFF 		bl	HAL_ADC_ErrorCallback
+ 2385              	.LVL122:
+2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 2386              		.loc 1 2096 1 is_stmt 0 view .LVU742
+ 2387 0014 08BD     		pop	{r3, pc}
+ 2388              		.cfi_endproc
+ 2389              	.LFE166:
+ARM GAS  /tmp/ccHbw826.s 			page 90
+
+
+ 2391              		.section	.text.ADC_DMAConvCplt,"ax",%progbits
+ 2392              		.align	1
+ 2393              		.syntax unified
+ 2394              		.thumb
+ 2395              		.thumb_func
+ 2396              		.fpu fpv5-d16
+ 2398              	ADC_DMAConvCplt:
+ 2399              	.LVL123:
+ 2400              	.LFB164:
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Retrieve ADC handle corresponding to current DMA handle */
+ 2401              		.loc 1 1999 1 is_stmt 1 view -0
+ 2402              		.cfi_startproc
+ 2403              		@ args = 0, pretend = 0, frame = 0
+ 2404              		@ frame_needed = 0, uses_anonymous_args = 0
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Retrieve ADC handle corresponding to current DMA handle */
+ 2405              		.loc 1 1999 1 is_stmt 0 view .LVU744
+ 2406 0000 08B5     		push	{r3, lr}
+ 2407              	.LCFI21:
+ 2408              		.cfi_def_cfa_offset 8
+ 2409              		.cfi_offset 3, -8
+ 2410              		.cfi_offset 14, -4
+ 2411 0002 0346     		mov	r3, r0
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2412              		.loc 1 2001 3 is_stmt 1 view .LVU745
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2413              		.loc 1 2001 22 is_stmt 0 view .LVU746
+ 2414 0004 806B     		ldr	r0, [r0, #56]
+ 2415              	.LVL124:
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2416              		.loc 1 2004 3 is_stmt 1 view .LVU747
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2417              		.loc 1 2004 7 is_stmt 0 view .LVU748
+ 2418 0006 026C     		ldr	r2, [r0, #64]
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2419              		.loc 1 2004 6 view .LVU749
+ 2420 0008 12F0500F 		tst	r2, #80
+ 2421 000c 25D1     		bne	.L175
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2422              		.loc 1 2007 5 is_stmt 1 view .LVU750
+ 2423 000e 036C     		ldr	r3, [r0, #64]
+ 2424              	.LVL125:
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2425              		.loc 1 2007 5 is_stmt 0 view .LVU751
+ 2426 0010 43F40073 		orr	r3, r3, #512
+ 2427 0014 0364     		str	r3, [r0, #64]
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 2428              		.loc 1 2015 5 is_stmt 1 view .LVU752
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 2429              		.loc 1 2015 8 is_stmt 0 view .LVU753
+ 2430 0016 0368     		ldr	r3, [r0]
+ 2431 0018 9A68     		ldr	r2, [r3, #8]
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 2432              		.loc 1 2015 7 view .LVU754
+ 2433 001a 12F0405F 		tst	r2, #805306368
+ 2434 001e 19D1     		bne	.L176
+2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+ 2435              		.loc 1 2016 19 discriminator 1 view .LVU755
+ARM GAS  /tmp/ccHbw826.s 			page 91
+
+
+ 2436 0020 8269     		ldr	r2, [r0, #24]
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 2437              		.loc 1 2015 62 discriminator 1 view .LVU756
+ 2438 0022 BAB9     		cbnz	r2, .L176
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+ 2439              		.loc 1 2017 9 view .LVU757
+ 2440 0024 DA6A     		ldr	r2, [r3, #44]
+2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+ 2441              		.loc 1 2016 62 view .LVU758
+ 2442 0026 12F4700F 		tst	r2, #15728640
+ 2443 002a 03D0     		beq	.L177
+2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2444              		.loc 1 2018 9 view .LVU759
+ 2445 002c 9A68     		ldr	r2, [r3, #8]
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+ 2446              		.loc 1 2017 58 view .LVU760
+ 2447 002e 12F4806F 		tst	r2, #1024
+ 2448 0032 0FD1     		bne	.L176
+ 2449              	.L177:
+2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+ 2450              		.loc 1 2024 7 is_stmt 1 view .LVU761
+ 2451 0034 5A68     		ldr	r2, [r3, #4]
+ 2452 0036 22F02002 		bic	r2, r2, #32
+ 2453 003a 5A60     		str	r2, [r3, #4]
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       
+ 2454              		.loc 1 2027 7 view .LVU762
+ 2455 003c 036C     		ldr	r3, [r0, #64]
+ 2456 003e 23F48073 		bic	r3, r3, #256
+ 2457 0042 0364     		str	r3, [r0, #64]
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 2458              		.loc 1 2029 7 view .LVU763
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 2459              		.loc 1 2029 11 is_stmt 0 view .LVU764
+ 2460 0044 036C     		ldr	r3, [r0, #64]
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 2461              		.loc 1 2029 10 view .LVU765
+ 2462 0046 13F4805F 		tst	r3, #4096
+ 2463 004a 03D1     		bne	.L176
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 2464              		.loc 1 2031 9 is_stmt 1 view .LVU766
+ 2465 004c 036C     		ldr	r3, [r0, #64]
+ 2466 004e 43F00103 		orr	r3, r3, #1
+ 2467 0052 0364     		str	r3, [r0, #64]
+ 2468              	.L176:
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2469              		.loc 1 2039 5 view .LVU767
+ 2470 0054 FFF7FEFF 		bl	HAL_ADC_ConvCpltCallback
+ 2471              	.LVL126:
+ 2472              	.L174:
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2473              		.loc 1 2059 1 is_stmt 0 view .LVU768
+ 2474 0058 08BD     		pop	{r3, pc}
+ 2475              	.LVL127:
+ 2476              	.L175:
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2477              		.loc 1 2044 5 is_stmt 1 view .LVU769
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ARM GAS  /tmp/ccHbw826.s 			page 92
+
+
+ 2478              		.loc 1 2044 14 is_stmt 0 view .LVU770
+ 2479 005a 026C     		ldr	r2, [r0, #64]
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2480              		.loc 1 2044 8 view .LVU771
+ 2481 005c 12F0100F 		tst	r2, #16
+ 2482 0060 04D1     		bne	.L181
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2483              		.loc 1 2056 7 is_stmt 1 view .LVU772
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2484              		.loc 1 2056 11 is_stmt 0 view .LVU773
+ 2485 0062 826B     		ldr	r2, [r0, #56]
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2486              		.loc 1 2056 23 view .LVU774
+ 2487 0064 D26C     		ldr	r2, [r2, #76]
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2488              		.loc 1 2056 7 view .LVU775
+ 2489 0066 1846     		mov	r0, r3
+ 2490              	.LVL128:
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2491              		.loc 1 2056 7 view .LVU776
+ 2492 0068 9047     		blx	r2
+ 2493              	.LVL129:
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2494              		.loc 1 2059 1 view .LVU777
+ 2495 006a F5E7     		b	.L174
+ 2496              	.LVL130:
+ 2497              	.L181:
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2498              		.loc 1 2050 7 is_stmt 1 view .LVU778
+ 2499 006c FFF7FEFF 		bl	HAL_ADC_ErrorCallback
+ 2500              	.LVL131:
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ 2501              		.loc 1 2050 7 is_stmt 0 view .LVU779
+ 2502 0070 F2E7     		b	.L174
+ 2503              		.cfi_endproc
+ 2504              	.LFE164:
+ 2506              		.section	.text.HAL_ADC_ConfigChannel,"ax",%progbits
+ 2507              		.align	1
+ 2508              		.global	HAL_ADC_ConfigChannel
+ 2509              		.syntax unified
+ 2510              		.thumb
+ 2511              		.thumb_func
+ 2512              		.fpu fpv5-d16
+ 2514              	HAL_ADC_ConfigChannel:
+ 2515              	.LVL132:
+ 2516              	.LFB159:
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+ 2517              		.loc 1 1671 1 is_stmt 1 view -0
+ 2518              		.cfi_startproc
+ 2519              		@ args = 0, pretend = 0, frame = 8
+ 2520              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2521              		@ link register save eliminated.
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   __IO uint32_t counter = 0;
+ 2522              		.loc 1 1671 1 is_stmt 0 view .LVU781
+ 2523 0000 30B4     		push	{r4, r5}
+ 2524              	.LCFI22:
+ 2525              		.cfi_def_cfa_offset 8
+ARM GAS  /tmp/ccHbw826.s 			page 93
+
+
+ 2526              		.cfi_offset 4, -8
+ 2527              		.cfi_offset 5, -4
+ 2528 0002 82B0     		sub	sp, sp, #8
+ 2529              	.LCFI23:
+ 2530              		.cfi_def_cfa_offset 16
+1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2531              		.loc 1 1672 3 is_stmt 1 view .LVU782
+1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2532              		.loc 1 1672 17 is_stmt 0 view .LVU783
+ 2533 0004 0023     		movs	r3, #0
+ 2534 0006 0193     		str	r3, [sp, #4]
+1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ 2535              		.loc 1 1675 3 is_stmt 1 view .LVU784
+1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+ 2536              		.loc 1 1676 3 view .LVU785
+1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2537              		.loc 1 1677 3 view .LVU786
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2538              		.loc 1 1680 3 view .LVU787
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2539              		.loc 1 1680 3 view .LVU788
+ 2540 0008 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 2541 000c 012B     		cmp	r3, #1
+ 2542 000e 00F0DD80 		beq	.L195
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2543              		.loc 1 1680 3 discriminator 2 view .LVU789
+ 2544 0012 0123     		movs	r3, #1
+ 2545 0014 80F83C30 		strb	r3, [r0, #60]
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2546              		.loc 1 1680 3 discriminator 2 view .LVU790
+1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2547              		.loc 1 1683 3 discriminator 2 view .LVU791
+1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2548              		.loc 1 1683 15 is_stmt 0 discriminator 2 view .LVU792
+ 2549 0018 0B68     		ldr	r3, [r1]
+1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2550              		.loc 1 1683 6 discriminator 2 view .LVU793
+ 2551 001a B3F1004F 		cmp	r3, #-2147483648
+ 2552 001e 18BF     		it	ne
+ 2553 0020 092B     		cmpne	r3, #9
+ 2554 0022 23D9     		bls	.L184
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2555              		.loc 1 1686 5 is_stmt 1 view .LVU794
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2556              		.loc 1 1686 9 is_stmt 0 view .LVU795
+ 2557 0024 0468     		ldr	r4, [r0]
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2558              		.loc 1 1686 27 view .LVU796
+ 2559 0026 E268     		ldr	r2, [r4, #12]
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2560              		.loc 1 1686 31 view .LVU797
+ 2561 0028 9BB2     		uxth	r3, r3
+ 2562 002a 03EB4303 		add	r3, r3, r3, lsl #1
+ 2563 002e 1E3B     		subs	r3, r3, #30
+ 2564 0030 4FF0070C 		mov	ip, #7
+ 2565 0034 0CFA03F3 		lsl	r3, ip, r3
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ARM GAS  /tmp/ccHbw826.s 			page 94
+
+
+ 2566              		.loc 1 1686 27 view .LVU798
+ 2567 0038 22EA0303 		bic	r3, r2, r3
+ 2568 003c E360     		str	r3, [r4, #12]
+1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2569              		.loc 1 1688 5 is_stmt 1 view .LVU799
+1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2570              		.loc 1 1688 16 is_stmt 0 view .LVU800
+ 2571 003e 0B68     		ldr	r3, [r1]
+1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2572              		.loc 1 1688 8 view .LVU801
+ 2573 0040 634A     		ldr	r2, .L201
+ 2574 0042 9342     		cmp	r3, r2
+ 2575 0044 0BD0     		beq	.L197
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2576              		.loc 1 1696 7 is_stmt 1 view .LVU802
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2577              		.loc 1 1696 11 is_stmt 0 view .LVU803
+ 2578 0046 0568     		ldr	r5, [r0]
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2579              		.loc 1 1696 29 view .LVU804
+ 2580 0048 EA68     		ldr	r2, [r5, #12]
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2581              		.loc 1 1696 32 view .LVU805
+ 2582 004a 8C68     		ldr	r4, [r1, #8]
+ 2583 004c 9BB2     		uxth	r3, r3
+ 2584 004e 03EB4303 		add	r3, r3, r3, lsl #1
+ 2585 0052 1E3B     		subs	r3, r3, #30
+ 2586 0054 04FA03F3 		lsl	r3, r4, r3
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2587              		.loc 1 1696 29 view .LVU806
+ 2588 0058 1343     		orrs	r3, r3, r2
+ 2589 005a EB60     		str	r3, [r5, #12]
+ 2590 005c 1CE0     		b	.L186
+ 2591              	.L197:
+1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2592              		.loc 1 1691 7 is_stmt 1 view .LVU807
+1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2593              		.loc 1 1691 11 is_stmt 0 view .LVU808
+ 2594 005e 0268     		ldr	r2, [r0]
+1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2595              		.loc 1 1691 29 view .LVU809
+ 2596 0060 D368     		ldr	r3, [r2, #12]
+1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2597              		.loc 1 1691 32 view .LVU810
+ 2598 0062 8C68     		ldr	r4, [r1, #8]
+1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     }
+ 2599              		.loc 1 1691 29 view .LVU811
+ 2600 0064 43EA0463 		orr	r3, r3, r4, lsl #24
+ 2601 0068 D360     		str	r3, [r2, #12]
+ 2602 006a 15E0     		b	.L186
+ 2603              	.L184:
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2604              		.loc 1 1702 5 is_stmt 1 view .LVU812
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2605              		.loc 1 1702 9 is_stmt 0 view .LVU813
+ 2606 006c 0468     		ldr	r4, [r0]
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ARM GAS  /tmp/ccHbw826.s 			page 95
+
+
+ 2607              		.loc 1 1702 27 view .LVU814
+ 2608 006e 2269     		ldr	r2, [r4, #16]
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2609              		.loc 1 1702 31 view .LVU815
+ 2610 0070 9BB2     		uxth	r3, r3
+ 2611 0072 03EB4303 		add	r3, r3, r3, lsl #1
+ 2612 0076 4FF0070C 		mov	ip, #7
+ 2613 007a 0CFA03F3 		lsl	r3, ip, r3
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2614              		.loc 1 1702 27 view .LVU816
+ 2615 007e 22EA0303 		bic	r3, r2, r3
+ 2616 0082 2361     		str	r3, [r4, #16]
+1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2617              		.loc 1 1705 5 is_stmt 1 view .LVU817
+1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2618              		.loc 1 1705 9 is_stmt 0 view .LVU818
+ 2619 0084 0468     		ldr	r4, [r0]
+1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2620              		.loc 1 1705 27 view .LVU819
+ 2621 0086 2269     		ldr	r2, [r4, #16]
+1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2622              		.loc 1 1705 30 view .LVU820
+ 2623 0088 0B88     		ldrh	r3, [r1]
+ 2624 008a 03EB4303 		add	r3, r3, r3, lsl #1
+ 2625 008e 8D68     		ldr	r5, [r1, #8]
+ 2626 0090 05FA03F3 		lsl	r3, r5, r3
+1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2627              		.loc 1 1705 27 view .LVU821
+ 2628 0094 1343     		orrs	r3, r3, r2
+ 2629 0096 2361     		str	r3, [r4, #16]
+ 2630              	.L186:
+1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2631              		.loc 1 1709 3 is_stmt 1 view .LVU822
+1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2632              		.loc 1 1709 14 is_stmt 0 view .LVU823
+ 2633 0098 4B68     		ldr	r3, [r1, #4]
+1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2634              		.loc 1 1709 6 view .LVU824
+ 2635 009a 062B     		cmp	r3, #6
+ 2636 009c 2AD8     		bhi	.L187
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2637              		.loc 1 1712 5 is_stmt 1 view .LVU825
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2638              		.loc 1 1712 9 is_stmt 0 view .LVU826
+ 2639 009e 0468     		ldr	r4, [r0]
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2640              		.loc 1 1712 26 view .LVU827
+ 2641 00a0 626B     		ldr	r2, [r4, #52]
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2642              		.loc 1 1712 30 view .LVU828
+ 2643 00a2 03EB8303 		add	r3, r3, r3, lsl #2
+ 2644 00a6 053B     		subs	r3, r3, #5
+ 2645 00a8 4FF01F0C 		mov	ip, #31
+ 2646 00ac 0CFA03F3 		lsl	r3, ip, r3
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2647              		.loc 1 1712 26 view .LVU829
+ 2648 00b0 22EA0303 		bic	r3, r2, r3
+ARM GAS  /tmp/ccHbw826.s 			page 96
+
+
+ 2649 00b4 6363     		str	r3, [r4, #52]
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2650              		.loc 1 1715 5 is_stmt 1 view .LVU830
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2651              		.loc 1 1715 9 is_stmt 0 view .LVU831
+ 2652 00b6 0468     		ldr	r4, [r0]
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2653              		.loc 1 1715 26 view .LVU832
+ 2654 00b8 626B     		ldr	r2, [r4, #52]
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2655              		.loc 1 1715 29 view .LVU833
+ 2656 00ba 4B68     		ldr	r3, [r1, #4]
+ 2657 00bc 03EB8303 		add	r3, r3, r3, lsl #2
+ 2658 00c0 053B     		subs	r3, r3, #5
+ 2659 00c2 B1F800C0 		ldrh	ip, [r1]
+ 2660 00c6 0CFA03F3 		lsl	r3, ip, r3
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2661              		.loc 1 1715 26 view .LVU834
+ 2662 00ca 1343     		orrs	r3, r3, r2
+ 2663 00cc 6363     		str	r3, [r4, #52]
+ 2664              	.L188:
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2665              		.loc 1 1737 3 is_stmt 1 view .LVU835
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2666              		.loc 1 1737 12 is_stmt 0 view .LVU836
+ 2667 00ce 0268     		ldr	r2, [r0]
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2668              		.loc 1 1737 6 view .LVU837
+ 2669 00d0 404B     		ldr	r3, .L201+4
+ 2670 00d2 9A42     		cmp	r2, r3
+ 2671 00d4 3ED0     		beq	.L198
+ 2672              	.L190:
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2673              		.loc 1 1744 3 is_stmt 1 view .LVU838
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2674              		.loc 1 1744 12 is_stmt 0 view .LVU839
+ 2675 00d6 0268     		ldr	r2, [r0]
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2676              		.loc 1 1744 6 view .LVU840
+ 2677 00d8 3E4B     		ldr	r3, .L201+4
+ 2678 00da 9A42     		cmp	r2, r3
+ 2679 00dc 44D0     		beq	.L199
+ 2680              	.L191:
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2681              		.loc 1 1754 3 is_stmt 1 view .LVU841
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2682              		.loc 1 1754 12 is_stmt 0 view .LVU842
+ 2683 00de 0268     		ldr	r2, [r0]
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2684              		.loc 1 1754 6 view .LVU843
+ 2685 00e0 3C4B     		ldr	r3, .L201+4
+ 2686 00e2 9A42     		cmp	r2, r3
+ 2687 00e4 4DD0     		beq	.L200
+ 2688              	.L192:
+1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2689              		.loc 1 1775 3 is_stmt 1 view .LVU844
+1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ARM GAS  /tmp/ccHbw826.s 			page 97
+
+
+ 2690              		.loc 1 1775 3 view .LVU845
+ 2691 00e6 0023     		movs	r3, #0
+ 2692 00e8 80F83C30 		strb	r3, [r0, #60]
+1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2693              		.loc 1 1775 3 view .LVU846
+1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 2694              		.loc 1 1778 3 view .LVU847
+1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 2695              		.loc 1 1778 10 is_stmt 0 view .LVU848
+ 2696 00ec 1846     		mov	r0, r3
+ 2697              	.LVL133:
+ 2698              	.L183:
+1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2699              		.loc 1 1779 1 view .LVU849
+ 2700 00ee 02B0     		add	sp, sp, #8
+ 2701              	.LCFI24:
+ 2702              		.cfi_remember_state
+ 2703              		.cfi_def_cfa_offset 8
+ 2704              		@ sp needed
+ 2705 00f0 30BC     		pop	{r4, r5}
+ 2706              	.LCFI25:
+ 2707              		.cfi_restore 5
+ 2708              		.cfi_restore 4
+ 2709              		.cfi_def_cfa_offset 0
+ 2710 00f2 7047     		bx	lr
+ 2711              	.LVL134:
+ 2712              	.L187:
+ 2713              	.LCFI26:
+ 2714              		.cfi_restore_state
+1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2715              		.loc 1 1718 8 is_stmt 1 view .LVU850
+1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2716              		.loc 1 1718 11 is_stmt 0 view .LVU851
+ 2717 00f4 0C2B     		cmp	r3, #12
+ 2718 00f6 16D8     		bhi	.L189
+1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2719              		.loc 1 1721 5 is_stmt 1 view .LVU852
+1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2720              		.loc 1 1721 9 is_stmt 0 view .LVU853
+ 2721 00f8 0568     		ldr	r5, [r0]
+1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2722              		.loc 1 1721 26 view .LVU854
+ 2723 00fa 2A6B     		ldr	r2, [r5, #48]
+1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2724              		.loc 1 1721 30 view .LVU855
+ 2725 00fc 03EB8303 		add	r3, r3, r3, lsl #2
+ 2726 0100 233B     		subs	r3, r3, #35
+ 2727 0102 1F24     		movs	r4, #31
+ 2728 0104 04FA03F3 		lsl	r3, r4, r3
+1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2729              		.loc 1 1721 26 view .LVU856
+ 2730 0108 22EA0303 		bic	r3, r2, r3
+ 2731 010c 2B63     		str	r3, [r5, #48]
+1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2732              		.loc 1 1724 5 is_stmt 1 view .LVU857
+1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2733              		.loc 1 1724 9 is_stmt 0 view .LVU858
+ARM GAS  /tmp/ccHbw826.s 			page 98
+
+
+ 2734 010e 0568     		ldr	r5, [r0]
+1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2735              		.loc 1 1724 26 view .LVU859
+ 2736 0110 2A6B     		ldr	r2, [r5, #48]
+1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2737              		.loc 1 1724 29 view .LVU860
+ 2738 0112 4B68     		ldr	r3, [r1, #4]
+ 2739 0114 03EB8303 		add	r3, r3, r3, lsl #2
+ 2740 0118 233B     		subs	r3, r3, #35
+ 2741 011a 0C88     		ldrh	r4, [r1]
+ 2742 011c 04FA03F3 		lsl	r3, r4, r3
+1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2743              		.loc 1 1724 26 view .LVU861
+ 2744 0120 1343     		orrs	r3, r3, r2
+ 2745 0122 2B63     		str	r3, [r5, #48]
+ 2746 0124 D3E7     		b	.L188
+ 2747              	.L189:
+1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2748              		.loc 1 1730 5 is_stmt 1 view .LVU862
+1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2749              		.loc 1 1730 9 is_stmt 0 view .LVU863
+ 2750 0126 0568     		ldr	r5, [r0]
+1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2751              		.loc 1 1730 26 view .LVU864
+ 2752 0128 EA6A     		ldr	r2, [r5, #44]
+1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2753              		.loc 1 1730 30 view .LVU865
+ 2754 012a 03EB8303 		add	r3, r3, r3, lsl #2
+ 2755 012e 413B     		subs	r3, r3, #65
+ 2756 0130 1F24     		movs	r4, #31
+ 2757 0132 04FA03F3 		lsl	r3, r4, r3
+1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     
+ 2758              		.loc 1 1730 26 view .LVU866
+ 2759 0136 22EA0303 		bic	r3, r2, r3
+ 2760 013a EB62     		str	r3, [r5, #44]
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2761              		.loc 1 1733 5 is_stmt 1 view .LVU867
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2762              		.loc 1 1733 9 is_stmt 0 view .LVU868
+ 2763 013c 0568     		ldr	r5, [r0]
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2764              		.loc 1 1733 26 view .LVU869
+ 2765 013e EA6A     		ldr	r2, [r5, #44]
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2766              		.loc 1 1733 29 view .LVU870
+ 2767 0140 4B68     		ldr	r3, [r1, #4]
+ 2768 0142 03EB8303 		add	r3, r3, r3, lsl #2
+ 2769 0146 413B     		subs	r3, r3, #65
+ 2770 0148 0C88     		ldrh	r4, [r1]
+ 2771 014a 04FA03F3 		lsl	r3, r4, r3
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2772              		.loc 1 1733 26 view .LVU871
+ 2773 014e 1343     		orrs	r3, r3, r2
+ 2774 0150 EB62     		str	r3, [r5, #44]
+ 2775 0152 BCE7     		b	.L188
+ 2776              	.L198:
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ARM GAS  /tmp/ccHbw826.s 			page 99
+
+
+ 2777              		.loc 1 1737 43 discriminator 1 view .LVU872
+ 2778 0154 0B68     		ldr	r3, [r1]
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2779              		.loc 1 1737 32 discriminator 1 view .LVU873
+ 2780 0156 B3F1004F 		cmp	r3, #-2147483648
+ 2781 015a BCD1     		bne	.L190
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2782              		.loc 1 1740 5 is_stmt 1 view .LVU874
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2783              		.loc 1 1740 14 is_stmt 0 view .LVU875
+ 2784 015c 1E4A     		ldr	r2, .L201+8
+ 2785 015e 5368     		ldr	r3, [r2, #4]
+ 2786 0160 23F44003 		bic	r3, r3, #12582912
+ 2787 0164 5360     		str	r3, [r2, #4]
+ 2788 0166 B6E7     		b	.L190
+ 2789              	.L199:
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2790              		.loc 1 1744 43 discriminator 1 view .LVU876
+ 2791 0168 0B68     		ldr	r3, [r1]
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2792              		.loc 1 1744 32 discriminator 1 view .LVU877
+ 2793 016a 122B     		cmp	r3, #18
+ 2794 016c B7D1     		bne	.L191
+1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2795              		.loc 1 1747 5 is_stmt 1 view .LVU878
+1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2796              		.loc 1 1747 14 is_stmt 0 view .LVU879
+ 2797 016e 1A4B     		ldr	r3, .L201+8
+ 2798 0170 5A68     		ldr	r2, [r3, #4]
+ 2799 0172 22F40002 		bic	r2, r2, #8388608
+ 2800 0176 5A60     		str	r2, [r3, #4]
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2801              		.loc 1 1750 5 is_stmt 1 view .LVU880
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2802              		.loc 1 1750 14 is_stmt 0 view .LVU881
+ 2803 0178 5A68     		ldr	r2, [r3, #4]
+ 2804 017a 42F48002 		orr	r2, r2, #4194304
+ 2805 017e 5A60     		str	r2, [r3, #4]
+ 2806 0180 ADE7     		b	.L191
+ 2807              	.L200:
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2808              		.loc 1 1754 44 discriminator 1 view .LVU882
+ 2809 0182 0B68     		ldr	r3, [r1]
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2810              		.loc 1 1754 32 discriminator 1 view .LVU883
+ 2811 0184 124A     		ldr	r2, .L201
+ 2812 0186 112B     		cmp	r3, #17
+ 2813 0188 18BF     		it	ne
+ 2814 018a 9342     		cmpne	r3, r2
+ 2815 018c ABD1     		bne	.L192
+1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2816              		.loc 1 1757 5 is_stmt 1 view .LVU884
+1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2817              		.loc 1 1757 14 is_stmt 0 view .LVU885
+ 2818 018e 124B     		ldr	r3, .L201+8
+ 2819 0190 5A68     		ldr	r2, [r3, #4]
+ 2820 0192 22F48002 		bic	r2, r2, #4194304
+ARM GAS  /tmp/ccHbw826.s 			page 100
+
+
+ 2821 0196 5A60     		str	r2, [r3, #4]
+1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2822              		.loc 1 1760 5 is_stmt 1 view .LVU886
+1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2823              		.loc 1 1760 14 is_stmt 0 view .LVU887
+ 2824 0198 5A68     		ldr	r2, [r3, #4]
+ 2825 019a 42F40002 		orr	r2, r2, #8388608
+ 2826 019e 5A60     		str	r2, [r3, #4]
+1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2827              		.loc 1 1762 5 is_stmt 1 view .LVU888
+1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2828              		.loc 1 1762 15 is_stmt 0 view .LVU889
+ 2829 01a0 0A68     		ldr	r2, [r1]
+1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****     {
+ 2830              		.loc 1 1762 7 view .LVU890
+ 2831 01a2 0B4B     		ldr	r3, .L201
+ 2832 01a4 9A42     		cmp	r2, r3
+ 2833 01a6 9ED1     		bne	.L192
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       while(counter != 0)
+ 2834              		.loc 1 1766 7 is_stmt 1 view .LVU891
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       while(counter != 0)
+ 2835              		.loc 1 1766 61 is_stmt 0 view .LVU892
+ 2836 01a8 0C4B     		ldr	r3, .L201+12
+ 2837 01aa 1B68     		ldr	r3, [r3]
+ 2838 01ac 0C4A     		ldr	r2, .L201+16
+ 2839 01ae A2FB0323 		umull	r2, r3, r2, r3
+ 2840 01b2 9B0C     		lsrs	r3, r3, #18
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       while(counter != 0)
+ 2841              		.loc 1 1766 42 view .LVU893
+ 2842 01b4 03EB8303 		add	r3, r3, r3, lsl #2
+ 2843 01b8 5B00     		lsls	r3, r3, #1
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       while(counter != 0)
+ 2844              		.loc 1 1766 15 view .LVU894
+ 2845 01ba 0193     		str	r3, [sp, #4]
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 2846              		.loc 1 1767 7 is_stmt 1 view .LVU895
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 2847              		.loc 1 1767 12 is_stmt 0 view .LVU896
+ 2848 01bc 02E0     		b	.L193
+ 2849              	.L194:
+1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 2850              		.loc 1 1769 9 is_stmt 1 view .LVU897
+1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       }
+ 2851              		.loc 1 1769 16 is_stmt 0 view .LVU898
+ 2852 01be 019B     		ldr	r3, [sp, #4]
+ 2853 01c0 013B     		subs	r3, r3, #1
+ 2854 01c2 0193     		str	r3, [sp, #4]
+ 2855              	.L193:
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 2856              		.loc 1 1767 12 is_stmt 1 view .LVU899
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 2857              		.loc 1 1767 21 is_stmt 0 view .LVU900
+ 2858 01c4 019B     		ldr	r3, [sp, #4]
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****       {
+ 2859              		.loc 1 1767 12 view .LVU901
+ 2860 01c6 002B     		cmp	r3, #0
+ 2861 01c8 F9D1     		bne	.L194
+ARM GAS  /tmp/ccHbw826.s 			page 101
+
+
+ 2862 01ca 8CE7     		b	.L192
+ 2863              	.L195:
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2864              		.loc 1 1680 3 view .LVU902
+ 2865 01cc 0220     		movs	r0, #2
+ 2866              	.LVL135:
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2867              		.loc 1 1680 3 view .LVU903
+ 2868 01ce 8EE7     		b	.L183
+ 2869              	.L202:
+ 2870              		.align	2
+ 2871              	.L201:
+ 2872 01d0 12000010 		.word	268435474
+ 2873 01d4 00200140 		.word	1073815552
+ 2874 01d8 00230140 		.word	1073816320
+ 2875 01dc 00000000 		.word	SystemCoreClock
+ 2876 01e0 83DE1B43 		.word	1125899907
+ 2877              		.cfi_endproc
+ 2878              	.LFE159:
+ 2880              		.section	.text.HAL_ADC_AnalogWDGConfig,"ax",%progbits
+ 2881              		.align	1
+ 2882              		.global	HAL_ADC_AnalogWDGConfig
+ 2883              		.syntax unified
+ 2884              		.thumb
+ 2885              		.thumb_func
+ 2886              		.fpu fpv5-d16
+ 2888              	HAL_ADC_AnalogWDGConfig:
+ 2889              	.LVL136:
+ 2890              	.LFB160:
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #ifdef USE_FULL_ASSERT  
+ 2891              		.loc 1 1798 1 is_stmt 1 view -0
+ 2892              		.cfi_startproc
+ 2893              		@ args = 0, pretend = 0, frame = 0
+ 2894              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2895              		@ link register save eliminated.
+1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+ 2896              		.loc 1 1804 3 view .LVU905
+1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+ 2897              		.loc 1 1805 3 view .LVU906
+1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2898              		.loc 1 1806 3 view .LVU907
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2899              		.loc 1 1815 3 view .LVU908
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2900              		.loc 1 1815 3 view .LVU909
+ 2901 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 2902 0004 012B     		cmp	r3, #1
+ 2903 0006 32D0     		beq	.L207
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #ifdef USE_FULL_ASSERT  
+ 2904              		.loc 1 1798 1 is_stmt 0 discriminator 2 view .LVU910
+ 2905 0008 10B4     		push	{r4}
+ 2906              	.LCFI27:
+ 2907              		.cfi_def_cfa_offset 4
+ 2908              		.cfi_offset 4, -4
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2909              		.loc 1 1815 3 is_stmt 1 discriminator 2 view .LVU911
+ 2910 000a 0123     		movs	r3, #1
+ARM GAS  /tmp/ccHbw826.s 			page 102
+
+
+ 2911 000c 80F83C30 		strb	r3, [r0, #60]
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2912              		.loc 1 1815 3 discriminator 2 view .LVU912
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2913              		.loc 1 1817 3 discriminator 2 view .LVU913
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2914              		.loc 1 1817 21 is_stmt 0 discriminator 2 view .LVU914
+ 2915 0010 0B7C     		ldrb	r3, [r1, #16]	@ zero_extendqisi2
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   {
+ 2916              		.loc 1 1817 5 discriminator 2 view .LVU915
+ 2917 0012 012B     		cmp	r3, #1
+ 2918 0014 25D0     		beq	.L212
+1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2919              		.loc 1 1825 5 is_stmt 1 view .LVU916
+ 2920 0016 0268     		ldr	r2, [r0]
+ 2921 0018 5368     		ldr	r3, [r2, #4]
+ 2922 001a 23F04003 		bic	r3, r3, #64
+ 2923 001e 5360     		str	r3, [r2, #4]
+ 2924              	.L206:
+1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2925              		.loc 1 1829 3 view .LVU917
+1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2926              		.loc 1 1829 7 is_stmt 0 view .LVU918
+ 2927 0020 0268     		ldr	r2, [r0]
+1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2928              		.loc 1 1829 23 view .LVU919
+ 2929 0022 5468     		ldr	r4, [r2, #4]
+ 2930 0024 134B     		ldr	r3, .L213
+ 2931 0026 2340     		ands	r3, r3, r4
+ 2932 0028 5360     		str	r3, [r2, #4]
+1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2933              		.loc 1 1832 3 is_stmt 1 view .LVU920
+1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2934              		.loc 1 1832 7 is_stmt 0 view .LVU921
+ 2935 002a 0268     		ldr	r2, [r0]
+1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2936              		.loc 1 1832 23 view .LVU922
+ 2937 002c 5368     		ldr	r3, [r2, #4]
+1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2938              		.loc 1 1832 41 view .LVU923
+ 2939 002e 0C68     		ldr	r4, [r1]
+1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2940              		.loc 1 1832 23 view .LVU924
+ 2941 0030 2343     		orrs	r3, r3, r4
+ 2942 0032 5360     		str	r3, [r2, #4]
+1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2943              		.loc 1 1835 3 is_stmt 1 view .LVU925
+1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2944              		.loc 1 1835 7 is_stmt 0 view .LVU926
+ 2945 0034 0368     		ldr	r3, [r0]
+1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2946              		.loc 1 1835 40 view .LVU927
+ 2947 0036 4A68     		ldr	r2, [r1, #4]
+1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2948              		.loc 1 1835 23 view .LVU928
+ 2949 0038 5A62     		str	r2, [r3, #36]
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ARM GAS  /tmp/ccHbw826.s 			page 103
+
+
+ 2950              		.loc 1 1838 3 is_stmt 1 view .LVU929
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2951              		.loc 1 1838 7 is_stmt 0 view .LVU930
+ 2952 003a 0368     		ldr	r3, [r0]
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2953              		.loc 1 1838 40 view .LVU931
+ 2954 003c 8A68     		ldr	r2, [r1, #8]
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2955              		.loc 1 1838 23 view .LVU932
+ 2956 003e 9A62     		str	r2, [r3, #40]
+1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2957              		.loc 1 1841 3 is_stmt 1 view .LVU933
+1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2958              		.loc 1 1841 7 is_stmt 0 view .LVU934
+ 2959 0040 0268     		ldr	r2, [r0]
+1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2960              		.loc 1 1841 23 view .LVU935
+ 2961 0042 5368     		ldr	r3, [r2, #4]
+ 2962 0044 23F01F03 		bic	r3, r3, #31
+ 2963 0048 5360     		str	r3, [r2, #4]
+1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2964              		.loc 1 1844 3 is_stmt 1 view .LVU936
+1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2965              		.loc 1 1844 7 is_stmt 0 view .LVU937
+ 2966 004a 0268     		ldr	r2, [r0]
+1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2967              		.loc 1 1844 23 view .LVU938
+ 2968 004c 5468     		ldr	r4, [r2, #4]
+ 2969 004e 8B89     		ldrh	r3, [r1, #12]
+ 2970 0050 2343     		orrs	r3, r3, r4
+ 2971 0052 5360     		str	r3, [r2, #4]
+1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2972              		.loc 1 1847 3 is_stmt 1 view .LVU939
+1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2973              		.loc 1 1847 3 view .LVU940
+ 2974 0054 0023     		movs	r3, #0
+ 2975 0056 80F83C30 		strb	r3, [r0, #60]
+1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 2976              		.loc 1 1847 3 view .LVU941
+1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 2977              		.loc 1 1850 3 view .LVU942
+1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 2978              		.loc 1 1850 10 is_stmt 0 view .LVU943
+ 2979 005a 1846     		mov	r0, r3
+ 2980              	.LVL137:
+1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 2981              		.loc 1 1851 1 view .LVU944
+ 2982 005c 5DF8044B 		ldr	r4, [sp], #4
+ 2983              	.LCFI28:
+ 2984              		.cfi_remember_state
+ 2985              		.cfi_restore 4
+ 2986              		.cfi_def_cfa_offset 0
+ 2987 0060 7047     		bx	lr
+ 2988              	.LVL138:
+ 2989              	.L212:
+ 2990              	.LCFI29:
+ 2991              		.cfi_restore_state
+ARM GAS  /tmp/ccHbw826.s 			page 104
+
+
+1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   }
+ 2992              		.loc 1 1820 5 is_stmt 1 view .LVU945
+ 2993 0062 0268     		ldr	r2, [r0]
+ 2994 0064 5368     		ldr	r3, [r2, #4]
+ 2995 0066 43F04003 		orr	r3, r3, #64
+ 2996 006a 5360     		str	r3, [r2, #4]
+ 2997 006c D8E7     		b	.L206
+ 2998              	.L207:
+ 2999              	.LCFI30:
+ 3000              		.cfi_def_cfa_offset 0
+ 3001              		.cfi_restore 4
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   
+ 3002              		.loc 1 1815 3 is_stmt 0 view .LVU946
+ 3003 006e 0220     		movs	r0, #2
+ 3004              	.LVL139:
+1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 3005              		.loc 1 1851 1 view .LVU947
+ 3006 0070 7047     		bx	lr
+ 3007              	.L214:
+ 3008 0072 00BF     		.align	2
+ 3009              	.L213:
+ 3010 0074 FFFD3FFF 		.word	-12583425
+ 3011              		.cfi_endproc
+ 3012              	.LFE160:
+ 3014              		.section	.text.HAL_ADC_GetState,"ax",%progbits
+ 3015              		.align	1
+ 3016              		.global	HAL_ADC_GetState
+ 3017              		.syntax unified
+ 3018              		.thumb
+ 3019              		.thumb_func
+ 3020              		.fpu fpv5-d16
+ 3022              	HAL_ADC_GetState:
+ 3023              	.LVL140:
+ 3024              	.LFB161:
+1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   /* Return ADC state */
+ 3025              		.loc 1 1880 1 is_stmt 1 view -0
+ 3026              		.cfi_startproc
+ 3027              		@ args = 0, pretend = 0, frame = 0
+ 3028              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3029              		@ link register save eliminated.
+1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 3030              		.loc 1 1882 3 view .LVU949
+1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 3031              		.loc 1 1882 14 is_stmt 0 view .LVU950
+ 3032 0000 006C     		ldr	r0, [r0, #64]
+ 3033              	.LVL141:
+1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 3034              		.loc 1 1883 1 view .LVU951
+ 3035 0002 7047     		bx	lr
+ 3036              		.cfi_endproc
+ 3037              	.LFE161:
+ 3039              		.section	.text.HAL_ADC_GetError,"ax",%progbits
+ 3040              		.align	1
+ 3041              		.global	HAL_ADC_GetError
+ 3042              		.syntax unified
+ 3043              		.thumb
+ 3044              		.thumb_func
+ARM GAS  /tmp/ccHbw826.s 			page 105
+
+
+ 3045              		.fpu fpv5-d16
+ 3047              	HAL_ADC_GetError:
+ 3048              	.LVL142:
+ 3049              	.LFB162:
+1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c ****   return hadc->ErrorCode;
+ 3050              		.loc 1 1892 1 is_stmt 1 view -0
+ 3051              		.cfi_startproc
+ 3052              		@ args = 0, pretend = 0, frame = 0
+ 3053              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3054              		@ link register save eliminated.
+1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 3055              		.loc 1 1893 3 view .LVU953
+1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** }
+ 3056              		.loc 1 1893 14 is_stmt 0 view .LVU954
+ 3057 0000 406C     		ldr	r0, [r0, #68]
+ 3058              	.LVL143:
+1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** 
+ 3059              		.loc 1 1894 1 view .LVU955
+ 3060 0002 7047     		bx	lr
+ 3061              		.cfi_endproc
+ 3062              	.LFE162:
+ 3064              		.text
+ 3065              	.Letext0:
+ 3066              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 3067              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 3068              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 3069              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 3070              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 3071              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h"
+ 3072              		.file 8 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h"
+ 3073              		.file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h"
+ 3074              		.file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ARM GAS  /tmp/ccHbw826.s 			page 106
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_adc.c
+     /tmp/ccHbw826.s:17     .text.ADC_Init:0000000000000000 $t
+     /tmp/ccHbw826.s:24     .text.ADC_Init:0000000000000000 ADC_Init
+     /tmp/ccHbw826.s:272    .text.ADC_Init:000000000000012c $d
+     /tmp/ccHbw826.s:278    .text.HAL_ADC_MspInit:0000000000000000 $t
+     /tmp/ccHbw826.s:285    .text.HAL_ADC_MspInit:0000000000000000 HAL_ADC_MspInit
+     /tmp/ccHbw826.s:300    .text.HAL_ADC_Init:0000000000000000 $t
+     /tmp/ccHbw826.s:307    .text.HAL_ADC_Init:0000000000000000 HAL_ADC_Init
+     /tmp/ccHbw826.s:409    .text.HAL_ADC_Init:0000000000000054 $d
+     /tmp/ccHbw826.s:414    .text.HAL_ADC_MspDeInit:0000000000000000 $t
+     /tmp/ccHbw826.s:421    .text.HAL_ADC_MspDeInit:0000000000000000 HAL_ADC_MspDeInit
+     /tmp/ccHbw826.s:436    .text.HAL_ADC_DeInit:0000000000000000 $t
+     /tmp/ccHbw826.s:443    .text.HAL_ADC_DeInit:0000000000000000 HAL_ADC_DeInit
+     /tmp/ccHbw826.s:515    .text.HAL_ADC_Start:0000000000000000 $t
+     /tmp/ccHbw826.s:522    .text.HAL_ADC_Start:0000000000000000 HAL_ADC_Start
+     /tmp/ccHbw826.s:775    .text.HAL_ADC_Start:000000000000011c $d
+     /tmp/ccHbw826.s:785    .text.HAL_ADC_Stop:0000000000000000 $t
+     /tmp/ccHbw826.s:792    .text.HAL_ADC_Stop:0000000000000000 HAL_ADC_Stop
+     /tmp/ccHbw826.s:850    .text.HAL_ADC_Stop:000000000000003c $d
+     /tmp/ccHbw826.s:855    .text.HAL_ADC_PollForConversion:0000000000000000 $t
+     /tmp/ccHbw826.s:862    .text.HAL_ADC_PollForConversion:0000000000000000 HAL_ADC_PollForConversion
+     /tmp/ccHbw826.s:1036   .text.HAL_ADC_PollForEvent:0000000000000000 $t
+     /tmp/ccHbw826.s:1043   .text.HAL_ADC_PollForEvent:0000000000000000 HAL_ADC_PollForEvent
+     /tmp/ccHbw826.s:1158   .text.HAL_ADC_Start_IT:0000000000000000 $t
+     /tmp/ccHbw826.s:1165   .text.HAL_ADC_Start_IT:0000000000000000 HAL_ADC_Start_IT
+     /tmp/ccHbw826.s:1424   .text.HAL_ADC_Start_IT:0000000000000128 $d
+     /tmp/ccHbw826.s:1435   .text.HAL_ADC_Stop_IT:0000000000000000 $t
+     /tmp/ccHbw826.s:1442   .text.HAL_ADC_Stop_IT:0000000000000000 HAL_ADC_Stop_IT
+     /tmp/ccHbw826.s:1505   .text.HAL_ADC_Stop_IT:0000000000000044 $d
+     /tmp/ccHbw826.s:1511   .text.HAL_ADC_Start_DMA:0000000000000000 $t
+     /tmp/ccHbw826.s:1518   .text.HAL_ADC_Start_DMA:0000000000000000 HAL_ADC_Start_DMA
+     /tmp/ccHbw826.s:1811   .text.HAL_ADC_Start_DMA:000000000000015c $d
+     /tmp/ccHbw826.s:2398   .text.ADC_DMAConvCplt:0000000000000000 ADC_DMAConvCplt
+     /tmp/ccHbw826.s:2024   .text.ADC_DMAHalfConvCplt:0000000000000000 ADC_DMAHalfConvCplt
+     /tmp/ccHbw826.s:2357   .text.ADC_DMAError:0000000000000000 ADC_DMAError
+     /tmp/ccHbw826.s:1824   .text.HAL_ADC_Stop_DMA:0000000000000000 $t
+     /tmp/ccHbw826.s:1831   .text.HAL_ADC_Stop_DMA:0000000000000000 HAL_ADC_Stop_DMA
+     /tmp/ccHbw826.s:1942   .text.HAL_ADC_Stop_DMA:0000000000000074 $d
+     /tmp/ccHbw826.s:1947   .text.HAL_ADC_GetValue:0000000000000000 $t
+     /tmp/ccHbw826.s:1954   .text.HAL_ADC_GetValue:0000000000000000 HAL_ADC_GetValue
+     /tmp/ccHbw826.s:1974   .text.HAL_ADC_ConvCpltCallback:0000000000000000 $t
+     /tmp/ccHbw826.s:1981   .text.HAL_ADC_ConvCpltCallback:0000000000000000 HAL_ADC_ConvCpltCallback
+     /tmp/ccHbw826.s:1996   .text.HAL_ADC_ConvHalfCpltCallback:0000000000000000 $t
+     /tmp/ccHbw826.s:2003   .text.HAL_ADC_ConvHalfCpltCallback:0000000000000000 HAL_ADC_ConvHalfCpltCallback
+     /tmp/ccHbw826.s:2018   .text.ADC_DMAHalfConvCplt:0000000000000000 $t
+     /tmp/ccHbw826.s:2051   .text.HAL_ADC_LevelOutOfWindowCallback:0000000000000000 $t
+     /tmp/ccHbw826.s:2058   .text.HAL_ADC_LevelOutOfWindowCallback:0000000000000000 HAL_ADC_LevelOutOfWindowCallback
+     /tmp/ccHbw826.s:2073   .text.HAL_ADC_ErrorCallback:0000000000000000 $t
+     /tmp/ccHbw826.s:2080   .text.HAL_ADC_ErrorCallback:0000000000000000 HAL_ADC_ErrorCallback
+     /tmp/ccHbw826.s:2095   .text.HAL_ADC_IRQHandler:0000000000000000 $t
+     /tmp/ccHbw826.s:2102   .text.HAL_ADC_IRQHandler:0000000000000000 HAL_ADC_IRQHandler
+     /tmp/ccHbw826.s:2351   .text.ADC_DMAError:0000000000000000 $t
+     /tmp/ccHbw826.s:2392   .text.ADC_DMAConvCplt:0000000000000000 $t
+     /tmp/ccHbw826.s:2507   .text.HAL_ADC_ConfigChannel:0000000000000000 $t
+     /tmp/ccHbw826.s:2514   .text.HAL_ADC_ConfigChannel:0000000000000000 HAL_ADC_ConfigChannel
+     /tmp/ccHbw826.s:2872   .text.HAL_ADC_ConfigChannel:00000000000001d0 $d
+ARM GAS  /tmp/ccHbw826.s 			page 107
+
+
+     /tmp/ccHbw826.s:2881   .text.HAL_ADC_AnalogWDGConfig:0000000000000000 $t
+     /tmp/ccHbw826.s:2888   .text.HAL_ADC_AnalogWDGConfig:0000000000000000 HAL_ADC_AnalogWDGConfig
+     /tmp/ccHbw826.s:3010   .text.HAL_ADC_AnalogWDGConfig:0000000000000074 $d
+     /tmp/ccHbw826.s:3015   .text.HAL_ADC_GetState:0000000000000000 $t
+     /tmp/ccHbw826.s:3022   .text.HAL_ADC_GetState:0000000000000000 HAL_ADC_GetState
+     /tmp/ccHbw826.s:3040   .text.HAL_ADC_GetError:0000000000000000 $t
+     /tmp/ccHbw826.s:3047   .text.HAL_ADC_GetError:0000000000000000 HAL_ADC_GetError
+
+UNDEFINED SYMBOLS
+SystemCoreClock
+HAL_GetTick
+HAL_DMA_Start_IT
+HAL_DMA_Abort
+HAL_ADCEx_InjectedConvCpltCallback
diff --git a/build/stm32f7xx_hal_adc.o b/build/stm32f7xx_hal_adc.o
new file mode 100644
index 0000000..4895630
Binary files /dev/null and b/build/stm32f7xx_hal_adc.o differ
diff --git a/build/stm32f7xx_hal_adc_ex.d b/build/stm32f7xx_hal_adc_ex.d
new file mode 100644
index 0000000..87cbf07
--- /dev/null
+++ b/build/stm32f7xx_hal_adc_ex.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_adc_ex.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_adc_ex.lst b/build/stm32f7xx_hal_adc_ex.lst
new file mode 100644
index 0000000..7feb701
--- /dev/null
+++ b/build/stm32f7xx_hal_adc_ex.lst
@@ -0,0 +1,4009 @@
+ARM GAS  /tmp/ccfOJcl9.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_adc_ex.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.ADC_MultiModeDMAError,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	ADC_MultiModeDMAError:
+  25              	.LVL0:
+  26              	.LFB155:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @file    stm32f7xx_hal_adc_ex.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief   This file provides firmware functions to manage the following 
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *          functionalities of the ADC extension peripheral:
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *           + Extended features functions
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ******************************************************************************
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @attention
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * Copyright (c) 2017 STMicroelectronics.
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * All rights reserved.
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * in the root directory of this software component.
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ******************************************************************************
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   @verbatim
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ==============================================================================
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                     ##### How to use this driver #####
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ==============================================================================
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     [..]
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (##) ADC pins configuration
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****              (+++) Enable the clock for the ADC GPIOs using the following function:
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                    __HAL_RCC_GPIOx_CLK_ENABLE()
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****              (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
+ARM GAS  /tmp/ccfOJcl9.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****              (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****              (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****              (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****              (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****              (+++) Configure and enable two DMA streams stream for managing data
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                  transfer from peripheral to memory (output stream)
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****              (+++) Associate the initialized DMA handle to the ADC DMA handle
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                  using  __HAL_LINKDMA()
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****              (+++) Configure the priority and enable the NVIC for the transfer complete
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                  interrupt on the two DMA Streams. The output stream should have higher
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                  priority than the input stream.
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      (#) Configure the ADC Prescaler, conversion resolution and data alignment
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****          using the HAL_ADC_Init() function.
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****          and HAL_ADC_ConfigChannel() functions.
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      (#) Three operation modes are available within this driver :
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      *** Polling mode IO operation ***
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      =================================
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      [..]
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) Wait for end of conversion using HAL_ADCEx_InjectedPollForConversion(), at this stage
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****            user can specify the value of timeout according to his end application
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      *** Interrupt mode IO operation ***
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      ===================================
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      [..]
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and u
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****             add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallbac
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user ca
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****             add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      *** Multi mode ADCs Regular channels configuration ***
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      ======================================================
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      [..]
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) Select the Multi mode ADC regular channels features (dual or triple mode)
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****           and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user sp
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****            of data to be transferred at each end of conversion
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     @endverbatim
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ******************************************************************************
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Includes ------------------------------------------------------------------*/
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** #include "stm32f7xx_hal.h"
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ARM GAS  /tmp/ccfOJcl9.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @{
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** @defgroup ADCEx ADCEx
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief ADC Extended driver modules
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @{
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */ 
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** #ifdef HAL_ADC_MODULE_ENABLED
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Private typedef -----------------------------------------------------------*/
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Private define ------------------------------------------------------------*/ 
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Private macro -------------------------------------------------------------*/
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Private variables ---------------------------------------------------------*/
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** @addtogroup ADCEx_Private_Functions
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @{
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Private function prototypes -----------------------------------------------*/
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); 
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @}
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Exported functions --------------------------------------------------------*/
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** @defgroup ADCEx_Exported_Functions ADC Exported Functions
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @{
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** @defgroup ADCEx_Exported_Functions_Group1  Extended features functions 
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *  @brief    Extended features functions  
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** @verbatim   
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****  ===============================================================================
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                  ##### Extended features functions #####
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****  ===============================================================================  
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     [..]  This section provides functions allowing to:
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (+) Start conversion of injected channel.
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (+) Stop conversion of injected channel.
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (+) Start multimode and enable DMA transfer.
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (+) Stop multimode and disable DMA transfer.
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (+) Get result of injected channel conversion.
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (+) Get result of multimode conversion.
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (+) Configure injected channels.
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (+) Configure multimode.
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** @endverbatim
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @{
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Enables the selected ADC software start conversion of the injected channels.
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         the configuration information for the specified ADC.
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval HAL status
+ARM GAS  /tmp/ccfOJcl9.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t counter = 0;
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   uint32_t tmp1 = 0, tmp2 = 0;
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process locked */
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Enable the ADC peripheral */
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check if ADC peripheral is disabled in order to enable it and wait during 
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      Tstab time the ADC's stabilization */
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Enable the Peripheral */
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_ADC_ENABLE(hadc);
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Delay for ADC stabilization time */
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Compute number of CPU cycles to wait for */
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       counter--;
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Start conversion if ADC is effectively enabled */
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set ADC state                                                          */
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* - Clear state bitfield related to injected group conversion results    */
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* - Set state bitfield related to injected operation                     */
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_INJ_BUSY);
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Check if a regular conversion is ongoing */
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Note: On this device, there is no ADC error code fields related to     */
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /*       conversions on group injected only. In case of conversion on     */
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /*       going on group regular, no error code is reset.                  */
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Reset ADC all error code fields */
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       ADC_CLEAR_ERRORCODE(hadc);
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Process unlocked */
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Unlock before starting ADC conversions: in case of potential           */
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* interruption, to let the process to ADC IRQ Handler.                   */
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_UNLOCK(hadc);
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Clear injected group conversion flag */
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* (To ensure of no unknown state from potential previous ADC operations) */
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Check if Multimode enabled */
+ARM GAS  /tmp/ccfOJcl9.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if(tmp1 && tmp2)
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         /* Enable the selected ADC software conversion for injected group */
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     else
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         /* Enable the selected ADC software conversion for injected group */
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   else
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Update ADC state machine to error */
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set ADC error code to ADC IP internal error */
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Return function status */
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   return HAL_OK;
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Enables the interrupt and starts ADC conversion of injected channels.
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         the configuration information for the specified ADC.
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval HAL status.
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t counter = 0;
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   uint32_t tmp1 = 0, tmp2 = 0;
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process locked */
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Enable the ADC peripheral */
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check if ADC peripheral is disabled in order to enable it and wait during 
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      Tstab time the ADC's stabilization */
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Enable the Peripheral */
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_ADC_ENABLE(hadc);
+ARM GAS  /tmp/ccfOJcl9.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Delay for ADC stabilization time */
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Compute number of CPU cycles to wait for */
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       counter--;
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Start conversion if ADC is effectively enabled */
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set ADC state                                                          */
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* - Clear state bitfield related to injected group conversion results    */
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* - Set state bitfield related to injected operation                     */
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_INJ_BUSY);
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Check if a regular conversion is ongoing */
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Note: On this device, there is no ADC error code fields related to     */
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /*       conversions on group injected only. In case of conversion on     */
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /*       going on group regular, no error code is reset.                  */
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Reset ADC all error code fields */
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       ADC_CLEAR_ERRORCODE(hadc);
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Process unlocked */
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Unlock before starting ADC conversions: in case of potential           */
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* interruption, to let the process to ADC IRQ Handler.                   */
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_UNLOCK(hadc);
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Clear injected group conversion flag */
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* (To ensure of no unknown state from potential previous ADC operations) */
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Enable end of conversion interrupt for injected channels */
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Check if Multimode enabled */
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if(tmp1 && tmp2)
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         /* Enable the selected ADC software conversion for injected group */
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     else
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ARM GAS  /tmp/ccfOJcl9.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         /* Enable the selected ADC software conversion for injected group */
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   else
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Update ADC state machine to error */
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set ADC error code to ADC IP internal error */
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Return function status */
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   return HAL_OK;
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Stop conversion of injected channels. Disable ADC peripheral if
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         no regular conversion is on going.
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @note   If ADC must be disabled and if conversion is on going on 
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         regular group, function HAL_ADC_Stop must be used to stop both
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         injected and regular groups, and disable the ADC.
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @note   If injected group mode auto-injection is enabled,
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         function HAL_ADC_Stop must be used.
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc ADC handle
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval None
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check the parameters */
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process locked */
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Stop potential conversion and disable ADC peripheral                     */
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Conditioned to:                                                          */
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* - No conversion on the other group (regular group) is intended to        */
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /*   continue (injected and regular groups stop conversion and ADC disable  */
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /*   are common)                                                            */
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Stop potential conversion on going, on regular and injected groups */
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Disable ADC peripheral */
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_ADC_DISABLE(hadc);
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Check if ADC is effectively disabled */
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ARM GAS  /tmp/ccfOJcl9.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Set ADC state */
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       ADC_STATE_CLR_SET(hadc->State,
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                         HAL_ADC_STATE_READY);
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   else
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Update ADC state machine to error */
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     tmp_hal_status = HAL_ERROR;
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process unlocked */
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Return function status */
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Poll for injected conversion complete
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         the configuration information for the specified ADC.
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  Timeout Timeout value in millisecond.  
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval HAL status
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   uint32_t tickstart = 0;
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Get tick */ 
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   tickstart = HAL_GetTick();
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check End of conversion flag */
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Check for the Timeout */
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if(Timeout != HAL_MAX_DELAY)
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         /* New check to avoid false timeout detection in case of preemption */
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         {
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****           hadc->State= HAL_ADC_STATE_TIMEOUT;
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****           /* Process unlocked */
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****           __HAL_UNLOCK(hadc);
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****           return HAL_TIMEOUT;
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         }
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Clear injected group conversion flag */
+ARM GAS  /tmp/ccfOJcl9.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Update ADC state machine */
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Determine whether any further conversion upcoming on group injected      */
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* by external trigger, continuous mode or scan sequence on going.          */
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Note: On STM32F7, there is no independent flag of end of sequence.       */
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /*       The test of scan sequence on going is done either with scan        */
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /*       sequence disabled or with end of conversion flag set to            */
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /*       of end of sequence.                                                */
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set ADC state */
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     { 
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Return ADC state */
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   return HAL_OK;
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }      
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Stop conversion of injected channels, disable interruption of 
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         end-of-conversion. Disable ADC peripheral if no regular conversion
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         is on going.
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @note   If ADC must be disabled and if conversion is on going on 
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         regular group, function HAL_ADC_Stop must be used to stop both
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         injected and regular groups, and disable the ADC.
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @note   If injected group mode auto-injection is enabled,
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         function HAL_ADC_Stop must be used.
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc ADC handle
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval None
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check the parameters */
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process locked */
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Stop potential conversion and disable ADC peripheral                     */
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Conditioned to:                                                          */
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* - No conversion on the other group (regular group) is intended to        */
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /*   continue (injected and regular groups stop conversion and ADC disable  */
+ARM GAS  /tmp/ccfOJcl9.s 			page 10
+
+
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /*   are common)                                                            */
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */ 
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Stop potential conversion on going, on regular and injected groups */
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Disable ADC peripheral */
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_ADC_DISABLE(hadc);
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Check if ADC is effectively disabled */
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Disable ADC end of conversion interrupt for injected channels */
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Set ADC state */
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       ADC_STATE_CLR_SET(hadc->State,
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                         HAL_ADC_STATE_READY);
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   else
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Update ADC state machine to error */
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     tmp_hal_status = HAL_ERROR;
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process unlocked */
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Return function status */
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Gets the converted value from data register of injected channel.
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         the configuration information for the specified ADC.
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  InjectedRank the ADC injected rank.
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *          This parameter can be one of the following values:
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval None
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t tmp = 0;
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check the parameters */
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Clear injected group conversion flag to have similar behaviour as        */
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* regular group: reading data register also clears end of conversion flag. */
+ARM GAS  /tmp/ccfOJcl9.s 			page 11
+
+
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Return the selected ADC converted value */ 
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   switch(InjectedRank)
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_4:
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp =  hadc->Instance->JDR4;
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }  
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     break;
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_3: 
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {  
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp =  hadc->Instance->JDR3;
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }  
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     break;
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_2: 
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {  
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp =  hadc->Instance->JDR2;
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     break;
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_1:
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp =  hadc->Instance->JDR1;
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     break;
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     default:
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     break;  
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   return tmp;
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * 
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @note   Caution: This function must be used only with the ADC master.  
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         the configuration information for the specified ADC.
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  pData   Pointer to buffer in which transferred from ADC peripheral to memory will be st
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  Length  The length of data to be transferred from ADC peripheral to memory.  
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval HAL status
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t L
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t counter = 0;
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check the parameters */
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process locked */
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check if ADC peripheral is disabled in order to enable it and wait during 
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      Tstab time the ADC's stabilization */
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+ARM GAS  /tmp/ccfOJcl9.s 			page 12
+
+
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Enable the Peripheral */
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_ADC_ENABLE(hadc);
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Delay for temperature sensor stabilization time */
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Compute number of CPU cycles to wait for */
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       counter--;
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Start conversion if ADC is effectively enabled */
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set ADC state                                                          */
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* - Clear state bitfield related to regular group conversion results     */
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* - Set state bitfield related to regular group operation                */
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_REG_BUSY);
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* If conversions on group regular are also triggering group injected,    */
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* update ADC state.                                                      */
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* State machine update: Check if an injected conversion is ongoing */
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Reset ADC error code fields related to conversions on group regular */
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     else
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Reset ADC all error code fields */
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       ADC_CLEAR_ERRORCODE(hadc);
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Process unlocked */
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Unlock before starting ADC conversions: in case of potential           */
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* interruption, to let the process to ADC IRQ Handler.                   */
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_UNLOCK(hadc);
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set the DMA transfer complete callback */
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set the DMA half transfer complete callback */
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set the DMA error callback */
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
+ARM GAS  /tmp/ccfOJcl9.s 			page 13
+
+
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* start (in case of SW start):                                           */
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Clear regular group conversion flag and overrun flag */
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* (To ensure of no unknown state from potential previous ADC operations) */
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Enable ADC overrun interrupt */
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if (hadc->Init.DMAContinuousRequests != DISABLE)
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Enable the selected ADC DMA request after last transfer */
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       ADC->CCR |= ADC_CCR_DDS;
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     else
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Disable the selected ADC EOC rising on each regular channel conversion */
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       ADC->CCR &= ~ADC_CCR_DDS;
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Enable the DMA Stream */
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* if no external trigger present enable software conversion of regular channels */
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Enable the selected ADC software conversion for regular group */
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   else
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Update ADC state machine to error */
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set ADC error code to ADC IP internal error */
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Return function status */
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   return HAL_OK;
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral    
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         the configuration information for the specified ADC.
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval HAL status
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check the parameters */
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process locked */
+ARM GAS  /tmp/ccfOJcl9.s 			page 14
+
+
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Stop potential conversion on going, on regular and injected groups */
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Disable ADC peripheral */
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_ADC_DISABLE(hadc);
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check if ADC is effectively disabled */
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Disable the selected ADC DMA mode for multimode */
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     ADC->CCR &= ~ADC_CCR_DDS;
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* DMA transfer is on going)                                              */
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Disable ADC overrun interrupt */
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set ADC state */
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     ADC_STATE_CLR_SET(hadc->State,
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_READY);
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process unlocked */
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Return function status */
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   return tmp_hal_status;
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results 
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         data in the selected multi mode.
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         the configuration information for the specified ADC.
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval The converted data value.
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   UNUSED(hadc);
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Return the multi mode conversion value */
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   return ADC->CDR;
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Injected conversion complete callback in non blocking mode 
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         the configuration information for the specified ADC.
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval None
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ARM GAS  /tmp/ccfOJcl9.s 			page 15
+
+
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   UNUSED(hadc);
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****             the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****    */
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Configures for the selected ADC injected channel its corresponding
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         rank in the sequencer and its sample time.
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *         the configuration information for the specified ADC.
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  sConfigInjected ADC configuration structure for injected channel. 
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval None
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** #ifdef USE_FULL_ASSERT  
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   uint32_t tmp = 0;
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** #endif /* USE_FULL_ASSERT  */
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check the parameters */
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** #ifdef USE_FULL_ASSERT
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   tmp = ADC_GET_RESOLUTION(hadc);
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** #endif /* USE_FULL_ASSERT  */
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process locked */
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Clear the old sample time */
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set the new sample time */
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->Inje
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   else /* ADC_Channel include in ADC_Channel_[0..9] */
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Clear the old sample time */
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ARM GAS  /tmp/ccfOJcl9.s 			page 16
+
+
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set the new sample time */
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->Inje
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /*---------------------------- ADCx JSQR Configuration -----------------*/
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Rank configuration */
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Clear the old SQx bits for the selected rank */
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->I
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****    
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Set the SQx bits for the selected rank */
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Enable external trigger if trigger selection is different of software  */
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* start.                                                                 */
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Note: This configuration keeps the hardware feature of parameter       */
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /*       software start.                                                  */ 
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Select external trigger to start conversion */
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Select external trigger polarity */
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   else
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Reset the external trigger */
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);  
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if (sConfigInjected->AutoInjectedConv != DISABLE)
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Enable the selected ADC automatic injected group conversion */
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR1 |= ADC_CR1_JAUTO;
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   else
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Disable the selected ADC automatic injected group conversion */
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Enable the selected ADC injected discontinuous mode */
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   else
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Disable the selected ADC injected discontinuous mode */
+ARM GAS  /tmp/ccfOJcl9.s 			page 17
+
+
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   switch(sConfigInjected->InjectedRank)
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case 1:
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Set injected channel 1 offset */
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case 2:
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Set injected channel 2 offset */
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case 3:
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Set injected channel 3 offset */
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     default:
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Set injected channel 4 offset */
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* if ADC1 Channel_18 is selected enable VBAT Channel */
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Enable the VBAT channel*/
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     ADC->CCR |= ADC_CCR_VBATE;
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VRE
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || 
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Enable the TSVREFE channel*/
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     ADC->CCR |= ADC_CCR_TSVREFE;
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process unlocked */
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Return function status */
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   return HAL_OK;
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  Configures the ADC multi-mode 
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hadc       pointer to a ADC_HandleTypeDef structure that contains
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *                     the configuration information for the specified ADC.  
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  multimode  pointer to an ADC_MultiModeTypeDef structure that contains 
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *                     the configuration information for  multimode.
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval HAL status
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* m
+ARM GAS  /tmp/ccfOJcl9.s 			page 18
+
+
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check the parameters */
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_MODE(multimode->Mode));
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process locked */
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_LOCK(hadc);
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Set ADC mode */
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR &= ~(ADC_CCR_MULTI);
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR |= multimode->Mode;
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Set the ADC DMA access mode */
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR &= ~(ADC_CCR_DMA);
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR |= multimode->DMAAccessMode;
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Set delay between two sampling phases */
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR &= ~(ADC_CCR_DELAY);
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR |= multimode->TwoSamplingDelay;
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Process unlocked */
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __HAL_UNLOCK(hadc);
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Return function status */
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   return HAL_OK;
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @}
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /**
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  DMA transfer complete callback. 
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *                the configuration information for the specified DMA module.
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval None
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)   
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Retrieve ADC handle corresponding to current DMA handle */
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Update state machine on conversion status if not in error state */
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Update ADC state machine */
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Determine whether any further conversion upcoming on group regular   */
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* by external trigger, continuous mode or scan sequence on going.      */
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Note: On STM32F7, there is no independent flag of end of sequence.   */
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /*       The test of scan sequence on going is done either with scan    */
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /*       sequence disabled or with end of conversion flag set to        */
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /*       of end of sequence.                                            */
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ARM GAS  /tmp/ccfOJcl9.s 			page 19
+
+
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Disable ADC end of single conversion interrupt on group regular */
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* by overrun IRQ process below.                                      */
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       /* Set ADC state */
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Conversion complete callback */
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     HAL_ADC_ConvCpltCallback(hadc);
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   else
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Call DMA error callback */
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->DMA_Handle->XferErrorCallback(hdma);
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  DMA half transfer complete callback. 
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *                the configuration information for the specified DMA module.
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval None
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Conversion complete callback */
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     HAL_ADC_ConvHalfCpltCallback(hadc); 
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /**
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @brief  DMA error callback 
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   *                the configuration information for the specified DMA module.
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   * @retval None
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   */
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)   
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** {
+  28              		.loc 1 1049 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		.loc 1 1049 1 is_stmt 0 view .LVU1
+  33 0000 08B5     		push	{r3, lr}
+  34              	.LCFI0:
+  35              		.cfi_def_cfa_offset 8
+ARM GAS  /tmp/ccfOJcl9.s 			page 20
+
+
+  36              		.cfi_offset 3, -8
+  37              		.cfi_offset 14, -4
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  38              		.loc 1 1050 5 is_stmt 1 view .LVU2
+  39              		.loc 1 1050 24 is_stmt 0 view .LVU3
+  40 0002 806B     		ldr	r0, [r0, #56]
+  41              	.LVL1:
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->State= HAL_ADC_STATE_ERROR_DMA;
+  42              		.loc 1 1051 5 is_stmt 1 view .LVU4
+  43              		.loc 1 1051 16 is_stmt 0 view .LVU5
+  44 0004 4023     		movs	r3, #64
+  45 0006 0364     		str	r3, [r0, #64]
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Set ADC error code to DMA error */
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+  46              		.loc 1 1053 5 is_stmt 1 view .LVU6
+  47              		.loc 1 1053 21 is_stmt 0 view .LVU7
+  48 0008 436C     		ldr	r3, [r0, #68]
+  49 000a 43F00403 		orr	r3, r3, #4
+  50 000e 4364     		str	r3, [r0, #68]
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     HAL_ADC_ErrorCallback(hadc); 
+  51              		.loc 1 1054 5 is_stmt 1 view .LVU8
+  52 0010 FFF7FEFF 		bl	HAL_ADC_ErrorCallback
+  53              	.LVL2:
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+  54              		.loc 1 1055 1 is_stmt 0 view .LVU9
+  55 0014 08BD     		pop	{r3, pc}
+  56              		.cfi_endproc
+  57              	.LFE155:
+  59              		.section	.text.ADC_MultiModeDMAHalfConvCplt,"ax",%progbits
+  60              		.align	1
+  61              		.syntax unified
+  62              		.thumb
+  63              		.thumb_func
+  64              		.fpu fpv5-d16
+  66              	ADC_MultiModeDMAHalfConvCplt:
+  67              	.LVL3:
+  68              	.LFB154:
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  69              		.loc 1 1036 1 is_stmt 1 view -0
+  70              		.cfi_startproc
+  71              		@ args = 0, pretend = 0, frame = 0
+  72              		@ frame_needed = 0, uses_anonymous_args = 0
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  73              		.loc 1 1036 1 is_stmt 0 view .LVU11
+  74 0000 08B5     		push	{r3, lr}
+  75              	.LCFI1:
+  76              		.cfi_def_cfa_offset 8
+  77              		.cfi_offset 3, -8
+  78              		.cfi_offset 14, -4
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     /* Conversion complete callback */
+  79              		.loc 1 1037 5 is_stmt 1 view .LVU12
+  80              	.LVL4:
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+  81              		.loc 1 1039 5 view .LVU13
+  82 0002 806B     		ldr	r0, [r0, #56]
+  83              	.LVL5:
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ARM GAS  /tmp/ccfOJcl9.s 			page 21
+
+
+  84              		.loc 1 1039 5 is_stmt 0 view .LVU14
+  85 0004 FFF7FEFF 		bl	HAL_ADC_ConvHalfCpltCallback
+  86              	.LVL6:
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+  87              		.loc 1 1040 1 view .LVU15
+  88 0008 08BD     		pop	{r3, pc}
+  89              		.cfi_endproc
+  90              	.LFE154:
+  92              		.section	.text.ADC_MultiModeDMAConvCplt,"ax",%progbits
+  93              		.align	1
+  94              		.syntax unified
+  95              		.thumb
+  96              		.thumb_func
+  97              		.fpu fpv5-d16
+  99              	ADC_MultiModeDMAConvCplt:
+ 100              	.LVL7:
+ 101              	.LFB153:
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Retrieve ADC handle corresponding to current DMA handle */
+ 102              		.loc 1 983 1 is_stmt 1 view -0
+ 103              		.cfi_startproc
+ 104              		@ args = 0, pretend = 0, frame = 0
+ 105              		@ frame_needed = 0, uses_anonymous_args = 0
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Retrieve ADC handle corresponding to current DMA handle */
+ 106              		.loc 1 983 1 is_stmt 0 view .LVU17
+ 107 0000 08B5     		push	{r3, lr}
+ 108              	.LCFI2:
+ 109              		.cfi_def_cfa_offset 8
+ 110              		.cfi_offset 3, -8
+ 111              		.cfi_offset 14, -4
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 112              		.loc 1 985 3 is_stmt 1 view .LVU18
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 113              		.loc 1 985 22 is_stmt 0 view .LVU19
+ 114 0002 836B     		ldr	r3, [r0, #56]
+ 115              	.LVL8:
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 116              		.loc 1 988 3 is_stmt 1 view .LVU20
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 117              		.loc 1 988 7 is_stmt 0 view .LVU21
+ 118 0004 1A6C     		ldr	r2, [r3, #64]
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 119              		.loc 1 988 6 view .LVU22
+ 120 0006 12F0500F 		tst	r2, #80
+ 121 000a 26D1     		bne	.L6
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 122              		.loc 1 991 5 is_stmt 1 view .LVU23
+ 123 000c 1A6C     		ldr	r2, [r3, #64]
+ 124 000e 42F40072 		orr	r2, r2, #512
+ 125 0012 1A64     		str	r2, [r3, #64]
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 126              		.loc 1 999 5 view .LVU24
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 127              		.loc 1 999 8 is_stmt 0 view .LVU25
+ 128 0014 1A68     		ldr	r2, [r3]
+ 129 0016 9168     		ldr	r1, [r2, #8]
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 130              		.loc 1 999 7 view .LVU26
+ARM GAS  /tmp/ccfOJcl9.s 			page 22
+
+
+ 131 0018 11F0405F 		tst	r1, #805306368
+ 132 001c 19D1     		bne	.L7
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+ 133              		.loc 1 1000 19 discriminator 1 view .LVU27
+ 134 001e 9969     		ldr	r1, [r3, #24]
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (hadc->Init.ContinuousConvMode == DISABLE)            &&
+ 135              		.loc 1 999 62 discriminator 1 view .LVU28
+ 136 0020 B9B9     		cbnz	r1, .L7
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+ 137              		.loc 1 1001 9 view .LVU29
+ 138 0022 D16A     		ldr	r1, [r2, #44]
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
+ 139              		.loc 1 1000 62 view .LVU30
+ 140 0024 11F4700F 		tst	r1, #15728640
+ 141 0028 03D0     		beq	.L8
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 142              		.loc 1 1002 9 view .LVU31
+ 143 002a 9168     		ldr	r1, [r2, #8]
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
+ 144              		.loc 1 1001 58 view .LVU32
+ 145 002c 11F4806F 		tst	r1, #1024
+ 146 0030 0FD1     		bne	.L7
+ 147              	.L8:
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       
+ 148              		.loc 1 1008 7 is_stmt 1 view .LVU33
+ 149 0032 5168     		ldr	r1, [r2, #4]
+ 150 0034 21F02001 		bic	r1, r1, #32
+ 151 0038 5160     		str	r1, [r2, #4]
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       
+ 152              		.loc 1 1011 7 view .LVU34
+ 153 003a 1A6C     		ldr	r2, [r3, #64]
+ 154 003c 22F48072 		bic	r2, r2, #256
+ 155 0040 1A64     		str	r2, [r3, #64]
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 156              		.loc 1 1013 7 view .LVU35
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 157              		.loc 1 1013 11 is_stmt 0 view .LVU36
+ 158 0042 1A6C     		ldr	r2, [r3, #64]
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 159              		.loc 1 1013 10 view .LVU37
+ 160 0044 12F4805F 		tst	r2, #4096
+ 161 0048 03D1     		bne	.L7
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 162              		.loc 1 1015 9 is_stmt 1 view .LVU38
+ 163 004a 1A6C     		ldr	r2, [r3, #64]
+ 164 004c 42F00102 		orr	r2, r2, #1
+ 165 0050 1A64     		str	r2, [r3, #64]
+ 166              	.L7:
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 167              		.loc 1 1020 5 view .LVU39
+ 168 0052 1846     		mov	r0, r3
+ 169              	.LVL9:
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 170              		.loc 1 1020 5 is_stmt 0 view .LVU40
+ 171 0054 FFF7FEFF 		bl	HAL_ADC_ConvCpltCallback
+ 172              	.LVL10:
+ 173              	.L5:
+ARM GAS  /tmp/ccfOJcl9.s 			page 23
+
+
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 174              		.loc 1 1027 1 view .LVU41
+ 175 0058 08BD     		pop	{r3, pc}
+ 176              	.LVL11:
+ 177              	.L6:
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 178              		.loc 1 1025 5 is_stmt 1 view .LVU42
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 179              		.loc 1 1025 9 is_stmt 0 view .LVU43
+ 180 005a 9B6B     		ldr	r3, [r3, #56]
+ 181              	.LVL12:
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 182              		.loc 1 1025 21 view .LVU44
+ 183 005c DB6C     		ldr	r3, [r3, #76]
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 184              		.loc 1 1025 5 view .LVU45
+ 185 005e 9847     		blx	r3
+ 186              	.LVL13:
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 187              		.loc 1 1027 1 view .LVU46
+ 188 0060 FAE7     		b	.L5
+ 189              		.cfi_endproc
+ 190              	.LFE153:
+ 192              		.section	.text.HAL_ADCEx_InjectedStart,"ax",%progbits
+ 193              		.align	1
+ 194              		.global	HAL_ADCEx_InjectedStart
+ 195              		.syntax unified
+ 196              		.thumb
+ 197              		.thumb_func
+ 198              		.fpu fpv5-d16
+ 200              	HAL_ADCEx_InjectedStart:
+ 201              	.LVL14:
+ 202              	.LFB141:
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t counter = 0;
+ 203              		.loc 1 148 1 is_stmt 1 view -0
+ 204              		.cfi_startproc
+ 205              		@ args = 0, pretend = 0, frame = 8
+ 206              		@ frame_needed = 0, uses_anonymous_args = 0
+ 207              		@ link register save eliminated.
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t counter = 0;
+ 208              		.loc 1 148 1 is_stmt 0 view .LVU48
+ 209 0000 82B0     		sub	sp, sp, #8
+ 210              	.LCFI3:
+ 211              		.cfi_def_cfa_offset 8
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   uint32_t tmp1 = 0, tmp2 = 0;
+ 212              		.loc 1 149 3 is_stmt 1 view .LVU49
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   uint32_t tmp1 = 0, tmp2 = 0;
+ 213              		.loc 1 149 17 is_stmt 0 view .LVU50
+ 214 0002 0023     		movs	r3, #0
+ 215 0004 0193     		str	r3, [sp, #4]
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 216              		.loc 1 150 3 is_stmt 1 view .LVU51
+ 217              	.LVL15:
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 218              		.loc 1 153 3 view .LVU52
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 219              		.loc 1 153 3 view .LVU53
+ARM GAS  /tmp/ccfOJcl9.s 			page 24
+
+
+ 220 0006 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 221 000a 012B     		cmp	r3, #1
+ 222 000c 65D0     		beq	.L19
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 223              		.loc 1 153 3 discriminator 2 view .LVU54
+ 224 000e 0123     		movs	r3, #1
+ 225 0010 80F83C30 		strb	r3, [r0, #60]
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 226              		.loc 1 153 3 discriminator 2 view .LVU55
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 227              		.loc 1 159 3 discriminator 2 view .LVU56
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 228              		.loc 1 159 11 is_stmt 0 discriminator 2 view .LVU57
+ 229 0014 0368     		ldr	r3, [r0]
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 230              		.loc 1 159 21 discriminator 2 view .LVU58
+ 231 0016 9A68     		ldr	r2, [r3, #8]
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 232              		.loc 1 159 5 discriminator 2 view .LVU59
+ 233 0018 12F0010F 		tst	r2, #1
+ 234 001c 13D1     		bne	.L13
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 235              		.loc 1 162 5 is_stmt 1 view .LVU60
+ 236 001e 9A68     		ldr	r2, [r3, #8]
+ 237 0020 42F00102 		orr	r2, r2, #1
+ 238 0024 9A60     		str	r2, [r3, #8]
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 239              		.loc 1 166 5 view .LVU61
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 240              		.loc 1 166 53 is_stmt 0 view .LVU62
+ 241 0026 304B     		ldr	r3, .L25
+ 242 0028 1B68     		ldr	r3, [r3]
+ 243 002a 304A     		ldr	r2, .L25+4
+ 244 002c A2FB0323 		umull	r2, r3, r2, r3
+ 245 0030 9B0C     		lsrs	r3, r3, #18
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 246              		.loc 1 166 34 view .LVU63
+ 247 0032 03EB4303 		add	r3, r3, r3, lsl #1
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 248              		.loc 1 166 13 view .LVU64
+ 249 0036 0193     		str	r3, [sp, #4]
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 250              		.loc 1 167 5 is_stmt 1 view .LVU65
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 251              		.loc 1 167 10 is_stmt 0 view .LVU66
+ 252 0038 02E0     		b	.L14
+ 253              	.L15:
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 254              		.loc 1 169 7 is_stmt 1 view .LVU67
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 255              		.loc 1 169 14 is_stmt 0 view .LVU68
+ 256 003a 019B     		ldr	r3, [sp, #4]
+ 257 003c 013B     		subs	r3, r3, #1
+ 258 003e 0193     		str	r3, [sp, #4]
+ 259              	.L14:
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 260              		.loc 1 167 10 is_stmt 1 view .LVU69
+ARM GAS  /tmp/ccfOJcl9.s 			page 25
+
+
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 261              		.loc 1 167 19 is_stmt 0 view .LVU70
+ 262 0040 019B     		ldr	r3, [sp, #4]
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 263              		.loc 1 167 10 view .LVU71
+ 264 0042 002B     		cmp	r3, #0
+ 265 0044 F9D1     		bne	.L15
+ 266              	.L13:
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 267              		.loc 1 174 3 is_stmt 1 view .LVU72
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 268              		.loc 1 174 6 is_stmt 0 view .LVU73
+ 269 0046 0268     		ldr	r2, [r0]
+ 270 0048 9368     		ldr	r3, [r2, #8]
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 271              		.loc 1 174 5 view .LVU74
+ 272 004a 13F0010F 		tst	r3, #1
+ 273 004e 39D0     		beq	.L16
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ 274              		.loc 1 179 5 is_stmt 1 view .LVU75
+ 275 0050 016C     		ldr	r1, [r0, #64]
+ 276 0052 274B     		ldr	r3, .L25+8
+ 277 0054 0B40     		ands	r3, r3, r1
+ 278 0056 43F48053 		orr	r3, r3, #4096
+ 279 005a 0364     		str	r3, [r0, #64]
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 280              		.loc 1 187 5 view .LVU76
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 281              		.loc 1 187 9 is_stmt 0 view .LVU77
+ 282 005c 036C     		ldr	r3, [r0, #64]
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 283              		.loc 1 187 8 view .LVU78
+ 284 005e 13F4807F 		tst	r3, #256
+ 285 0062 01D1     		bne	.L17
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 286              		.loc 1 190 7 is_stmt 1 view .LVU79
+ 287 0064 0023     		movs	r3, #0
+ 288 0066 4364     		str	r3, [r0, #68]
+ 289              	.L17:
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 290              		.loc 1 196 5 view .LVU80
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 291              		.loc 1 196 5 view .LVU81
+ 292 0068 0023     		movs	r3, #0
+ 293 006a 80F83C30 		strb	r3, [r0, #60]
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 294              		.loc 1 196 5 view .LVU82
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 295              		.loc 1 200 5 view .LVU83
+ 296 006e 6FF00403 		mvn	r3, #4
+ 297 0072 1360     		str	r3, [r2]
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 298              		.loc 1 203 5 view .LVU84
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 299              		.loc 1 203 8 is_stmt 0 view .LVU85
+ 300 0074 1F4B     		ldr	r3, .L25+12
+ 301 0076 5B68     		ldr	r3, [r3, #4]
+ARM GAS  /tmp/ccfOJcl9.s 			page 26
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 302              		.loc 1 203 7 view .LVU86
+ 303 0078 13F01F0F 		tst	r3, #31
+ 304 007c 0ED1     		bne	.L18
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ 305              		.loc 1 205 7 is_stmt 1 view .LVU87
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ 306              		.loc 1 205 14 is_stmt 0 view .LVU88
+ 307 007e 0168     		ldr	r1, [r0]
+ 308 0080 8A68     		ldr	r2, [r1, #8]
+ 309 0082 02F44012 		and	r2, r2, #3145728
+ 310              	.LVL16:
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if(tmp1 && tmp2)
+ 311              		.loc 1 206 7 is_stmt 1 view .LVU89
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if(tmp1 && tmp2)
+ 312              		.loc 1 206 14 is_stmt 0 view .LVU90
+ 313 0086 4B68     		ldr	r3, [r1, #4]
+ 314 0088 03F48063 		and	r3, r3, #1024
+ 315              	.LVL17:
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 316              		.loc 1 207 7 is_stmt 1 view .LVU91
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 317              		.loc 1 207 9 is_stmt 0 view .LVU92
+ 318 008c 1343     		orrs	r3, r2, r3
+ 319              	.LVL18:
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 320              		.loc 1 207 9 view .LVU93
+ 321 008e 26D1     		bne	.L20
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 322              		.loc 1 210 9 is_stmt 1 view .LVU94
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 323              		.loc 1 210 29 is_stmt 0 view .LVU95
+ 324 0090 8B68     		ldr	r3, [r1, #8]
+ 325 0092 43F48003 		orr	r3, r3, #4194304
+ 326 0096 8B60     		str	r3, [r1, #8]
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 327              		.loc 1 234 10 view .LVU96
+ 328 0098 0020     		movs	r0, #0
+ 329              	.LVL19:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 330              		.loc 1 234 10 view .LVU97
+ 331 009a 1CE0     		b	.L12
+ 332              	.LVL20:
+ 333              	.L18:
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ 334              		.loc 1 215 7 is_stmt 1 view .LVU98
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ 335              		.loc 1 215 14 is_stmt 0 view .LVU99
+ 336 009c 0368     		ldr	r3, [r0]
+ 337 009e 9968     		ldr	r1, [r3, #8]
+ 338 00a0 01F44011 		and	r1, r1, #3145728
+ 339              	.LVL21:
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+ 340              		.loc 1 216 7 is_stmt 1 view .LVU100
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+ 341              		.loc 1 216 14 is_stmt 0 view .LVU101
+ 342 00a4 5A68     		ldr	r2, [r3, #4]
+ARM GAS  /tmp/ccfOJcl9.s 			page 27
+
+
+ 343 00a6 02F48062 		and	r2, r2, #1024
+ 344              	.LVL22:
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 345              		.loc 1 217 7 is_stmt 1 view .LVU102
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 346              		.loc 1 217 9 is_stmt 0 view .LVU103
+ 347 00aa 1348     		ldr	r0, .L25+16
+ 348              	.LVL23:
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 349              		.loc 1 217 9 view .LVU104
+ 350 00ac 8342     		cmp	r3, r0
+ 351 00ae 01D0     		beq	.L24
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 352              		.loc 1 234 10 view .LVU105
+ 353 00b0 0020     		movs	r0, #0
+ 354 00b2 10E0     		b	.L12
+ 355              	.L24:
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 356              		.loc 1 217 43 discriminator 1 view .LVU106
+ 357 00b4 0A43     		orrs	r2, r1, r2
+ 358              	.LVL24:
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 359              		.loc 1 217 43 discriminator 1 view .LVU107
+ 360 00b6 14D1     		bne	.L22
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 361              		.loc 1 220 9 is_stmt 1 view .LVU108
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 362              		.loc 1 220 29 is_stmt 0 view .LVU109
+ 363 00b8 9A68     		ldr	r2, [r3, #8]
+ 364 00ba 42F48002 		orr	r2, r2, #4194304
+ 365 00be 9A60     		str	r2, [r3, #8]
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 366              		.loc 1 234 10 view .LVU110
+ 367 00c0 0020     		movs	r0, #0
+ 368 00c2 08E0     		b	.L12
+ 369              	.LVL25:
+ 370              	.L16:
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 371              		.loc 1 227 5 is_stmt 1 view .LVU111
+ 372 00c4 036C     		ldr	r3, [r0, #64]
+ 373 00c6 43F01003 		orr	r3, r3, #16
+ 374 00ca 0364     		str	r3, [r0, #64]
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 375              		.loc 1 230 5 view .LVU112
+ 376 00cc 436C     		ldr	r3, [r0, #68]
+ 377 00ce 43F00103 		orr	r3, r3, #1
+ 378 00d2 4364     		str	r3, [r0, #68]
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 379              		.loc 1 234 10 is_stmt 0 view .LVU113
+ 380 00d4 0020     		movs	r0, #0
+ 381              	.LVL26:
+ 382              	.L12:
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 383              		.loc 1 235 1 view .LVU114
+ 384 00d6 02B0     		add	sp, sp, #8
+ 385              	.LCFI4:
+ 386              		.cfi_remember_state
+ARM GAS  /tmp/ccfOJcl9.s 			page 28
+
+
+ 387              		.cfi_def_cfa_offset 0
+ 388              		@ sp needed
+ 389 00d8 7047     		bx	lr
+ 390              	.LVL27:
+ 391              	.L19:
+ 392              	.LCFI5:
+ 393              		.cfi_restore_state
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 394              		.loc 1 153 3 view .LVU115
+ 395 00da 0220     		movs	r0, #2
+ 396              	.LVL28:
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 397              		.loc 1 153 3 view .LVU116
+ 398 00dc FBE7     		b	.L12
+ 399              	.LVL29:
+ 400              	.L20:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 401              		.loc 1 234 10 view .LVU117
+ 402 00de 0020     		movs	r0, #0
+ 403              	.LVL30:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 404              		.loc 1 234 10 view .LVU118
+ 405 00e0 F9E7     		b	.L12
+ 406              	.LVL31:
+ 407              	.L22:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 408              		.loc 1 234 10 view .LVU119
+ 409 00e2 0020     		movs	r0, #0
+ 410 00e4 F7E7     		b	.L12
+ 411              	.L26:
+ 412 00e6 00BF     		.align	2
+ 413              	.L25:
+ 414 00e8 00000000 		.word	SystemCoreClock
+ 415 00ec 83DE1B43 		.word	1125899907
+ 416 00f0 FECFFFFF 		.word	-12290
+ 417 00f4 00230140 		.word	1073816320
+ 418 00f8 00200140 		.word	1073815552
+ 419              		.cfi_endproc
+ 420              	.LFE141:
+ 422              		.section	.text.HAL_ADCEx_InjectedStart_IT,"ax",%progbits
+ 423              		.align	1
+ 424              		.global	HAL_ADCEx_InjectedStart_IT
+ 425              		.syntax unified
+ 426              		.thumb
+ 427              		.thumb_func
+ 428              		.fpu fpv5-d16
+ 430              	HAL_ADCEx_InjectedStart_IT:
+ 431              	.LVL32:
+ 432              	.LFB142:
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t counter = 0;
+ 433              		.loc 1 245 1 is_stmt 1 view -0
+ 434              		.cfi_startproc
+ 435              		@ args = 0, pretend = 0, frame = 8
+ 436              		@ frame_needed = 0, uses_anonymous_args = 0
+ 437              		@ link register save eliminated.
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t counter = 0;
+ 438              		.loc 1 245 1 is_stmt 0 view .LVU121
+ARM GAS  /tmp/ccfOJcl9.s 			page 29
+
+
+ 439 0000 82B0     		sub	sp, sp, #8
+ 440              	.LCFI6:
+ 441              		.cfi_def_cfa_offset 8
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   uint32_t tmp1 = 0, tmp2 = 0;
+ 442              		.loc 1 246 3 is_stmt 1 view .LVU122
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   uint32_t tmp1 = 0, tmp2 = 0;
+ 443              		.loc 1 246 17 is_stmt 0 view .LVU123
+ 444 0002 0023     		movs	r3, #0
+ 445 0004 0193     		str	r3, [sp, #4]
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 446              		.loc 1 247 3 is_stmt 1 view .LVU124
+ 447              	.LVL33:
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 448              		.loc 1 250 3 view .LVU125
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 449              		.loc 1 250 3 view .LVU126
+ 450 0006 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 451 000a 012B     		cmp	r3, #1
+ 452 000c 6AD0     		beq	.L35
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 453              		.loc 1 250 3 discriminator 2 view .LVU127
+ 454 000e 0123     		movs	r3, #1
+ 455 0010 80F83C30 		strb	r3, [r0, #60]
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 456              		.loc 1 250 3 discriminator 2 view .LVU128
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 457              		.loc 1 256 3 discriminator 2 view .LVU129
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 458              		.loc 1 256 11 is_stmt 0 discriminator 2 view .LVU130
+ 459 0014 0368     		ldr	r3, [r0]
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 460              		.loc 1 256 21 discriminator 2 view .LVU131
+ 461 0016 9A68     		ldr	r2, [r3, #8]
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 462              		.loc 1 256 5 discriminator 2 view .LVU132
+ 463 0018 12F0010F 		tst	r2, #1
+ 464 001c 13D1     		bne	.L29
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 465              		.loc 1 259 5 is_stmt 1 view .LVU133
+ 466 001e 9A68     		ldr	r2, [r3, #8]
+ 467 0020 42F00102 		orr	r2, r2, #1
+ 468 0024 9A60     		str	r2, [r3, #8]
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 469              		.loc 1 263 5 view .LVU134
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 470              		.loc 1 263 53 is_stmt 0 view .LVU135
+ 471 0026 324B     		ldr	r3, .L41
+ 472 0028 1B68     		ldr	r3, [r3]
+ 473 002a 324A     		ldr	r2, .L41+4
+ 474 002c A2FB0323 		umull	r2, r3, r2, r3
+ 475 0030 9B0C     		lsrs	r3, r3, #18
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 476              		.loc 1 263 34 view .LVU136
+ 477 0032 03EB4303 		add	r3, r3, r3, lsl #1
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 478              		.loc 1 263 13 view .LVU137
+ 479 0036 0193     		str	r3, [sp, #4]
+ARM GAS  /tmp/ccfOJcl9.s 			page 30
+
+
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 480              		.loc 1 264 5 is_stmt 1 view .LVU138
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 481              		.loc 1 264 10 is_stmt 0 view .LVU139
+ 482 0038 02E0     		b	.L30
+ 483              	.L31:
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 484              		.loc 1 266 7 is_stmt 1 view .LVU140
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 485              		.loc 1 266 14 is_stmt 0 view .LVU141
+ 486 003a 019B     		ldr	r3, [sp, #4]
+ 487 003c 013B     		subs	r3, r3, #1
+ 488 003e 0193     		str	r3, [sp, #4]
+ 489              	.L30:
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 490              		.loc 1 264 10 is_stmt 1 view .LVU142
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 491              		.loc 1 264 19 is_stmt 0 view .LVU143
+ 492 0040 019B     		ldr	r3, [sp, #4]
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 493              		.loc 1 264 10 view .LVU144
+ 494 0042 002B     		cmp	r3, #0
+ 495 0044 F9D1     		bne	.L31
+ 496              	.L29:
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 497              		.loc 1 271 3 is_stmt 1 view .LVU145
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 498              		.loc 1 271 6 is_stmt 0 view .LVU146
+ 499 0046 0268     		ldr	r2, [r0]
+ 500 0048 9368     		ldr	r3, [r2, #8]
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 501              		.loc 1 271 5 view .LVU147
+ 502 004a 13F0010F 		tst	r3, #1
+ 503 004e 3ED0     		beq	.L32
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ 504              		.loc 1 276 5 is_stmt 1 view .LVU148
+ 505 0050 016C     		ldr	r1, [r0, #64]
+ 506 0052 294B     		ldr	r3, .L41+8
+ 507 0054 0B40     		ands	r3, r3, r1
+ 508 0056 43F48053 		orr	r3, r3, #4096
+ 509 005a 0364     		str	r3, [r0, #64]
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 510              		.loc 1 284 5 view .LVU149
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 511              		.loc 1 284 9 is_stmt 0 view .LVU150
+ 512 005c 036C     		ldr	r3, [r0, #64]
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 513              		.loc 1 284 8 view .LVU151
+ 514 005e 13F4807F 		tst	r3, #256
+ 515 0062 01D1     		bne	.L33
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 516              		.loc 1 287 7 is_stmt 1 view .LVU152
+ 517 0064 0023     		movs	r3, #0
+ 518 0066 4364     		str	r3, [r0, #68]
+ 519              	.L33:
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 520              		.loc 1 293 5 view .LVU153
+ARM GAS  /tmp/ccfOJcl9.s 			page 31
+
+
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 521              		.loc 1 293 5 view .LVU154
+ 522 0068 0023     		movs	r3, #0
+ 523 006a 80F83C30 		strb	r3, [r0, #60]
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 524              		.loc 1 293 5 view .LVU155
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 525              		.loc 1 297 5 view .LVU156
+ 526 006e 6FF00403 		mvn	r3, #4
+ 527 0072 1360     		str	r3, [r2]
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 528              		.loc 1 300 5 view .LVU157
+ 529 0074 0268     		ldr	r2, [r0]
+ 530 0076 5368     		ldr	r3, [r2, #4]
+ 531 0078 43F08003 		orr	r3, r3, #128
+ 532 007c 5360     		str	r3, [r2, #4]
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 533              		.loc 1 303 5 view .LVU158
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 534              		.loc 1 303 8 is_stmt 0 view .LVU159
+ 535 007e 1F4B     		ldr	r3, .L41+12
+ 536 0080 5B68     		ldr	r3, [r3, #4]
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 537              		.loc 1 303 7 view .LVU160
+ 538 0082 13F01F0F 		tst	r3, #31
+ 539 0086 0ED1     		bne	.L34
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ 540              		.loc 1 305 7 is_stmt 1 view .LVU161
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ 541              		.loc 1 305 14 is_stmt 0 view .LVU162
+ 542 0088 0168     		ldr	r1, [r0]
+ 543 008a 8A68     		ldr	r2, [r1, #8]
+ 544 008c 02F44012 		and	r2, r2, #3145728
+ 545              	.LVL34:
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if(tmp1 && tmp2)
+ 546              		.loc 1 306 7 is_stmt 1 view .LVU163
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if(tmp1 && tmp2)
+ 547              		.loc 1 306 14 is_stmt 0 view .LVU164
+ 548 0090 4B68     		ldr	r3, [r1, #4]
+ 549 0092 03F48063 		and	r3, r3, #1024
+ 550              	.LVL35:
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 551              		.loc 1 307 7 is_stmt 1 view .LVU165
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 552              		.loc 1 307 9 is_stmt 0 view .LVU166
+ 553 0096 1343     		orrs	r3, r2, r3
+ 554              	.LVL36:
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 555              		.loc 1 307 9 view .LVU167
+ 556 0098 26D1     		bne	.L36
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 557              		.loc 1 310 9 is_stmt 1 view .LVU168
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 558              		.loc 1 310 29 is_stmt 0 view .LVU169
+ 559 009a 8B68     		ldr	r3, [r1, #8]
+ 560 009c 43F48003 		orr	r3, r3, #4194304
+ 561 00a0 8B60     		str	r3, [r1, #8]
+ARM GAS  /tmp/ccfOJcl9.s 			page 32
+
+
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 562              		.loc 1 334 10 view .LVU170
+ 563 00a2 0020     		movs	r0, #0
+ 564              	.LVL37:
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 565              		.loc 1 334 10 view .LVU171
+ 566 00a4 1CE0     		b	.L28
+ 567              	.LVL38:
+ 568              	.L34:
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ 569              		.loc 1 315 7 is_stmt 1 view .LVU172
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ 570              		.loc 1 315 14 is_stmt 0 view .LVU173
+ 571 00a6 0368     		ldr	r3, [r0]
+ 572 00a8 9968     		ldr	r1, [r3, #8]
+ 573 00aa 01F44011 		and	r1, r1, #3145728
+ 574              	.LVL39:
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+ 575              		.loc 1 316 7 is_stmt 1 view .LVU174
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+ 576              		.loc 1 316 14 is_stmt 0 view .LVU175
+ 577 00ae 5A68     		ldr	r2, [r3, #4]
+ 578 00b0 02F48062 		and	r2, r2, #1024
+ 579              	.LVL40:
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 580              		.loc 1 317 7 is_stmt 1 view .LVU176
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 581              		.loc 1 317 9 is_stmt 0 view .LVU177
+ 582 00b4 1248     		ldr	r0, .L41+16
+ 583              	.LVL41:
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 584              		.loc 1 317 9 view .LVU178
+ 585 00b6 8342     		cmp	r3, r0
+ 586 00b8 01D0     		beq	.L40
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 587              		.loc 1 334 10 view .LVU179
+ 588 00ba 0020     		movs	r0, #0
+ 589 00bc 10E0     		b	.L28
+ 590              	.L40:
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 591              		.loc 1 317 43 discriminator 1 view .LVU180
+ 592 00be 0A43     		orrs	r2, r1, r2
+ 593              	.LVL42:
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 594              		.loc 1 317 43 discriminator 1 view .LVU181
+ 595 00c0 14D1     		bne	.L38
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 596              		.loc 1 320 9 is_stmt 1 view .LVU182
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       }
+ 597              		.loc 1 320 29 is_stmt 0 view .LVU183
+ 598 00c2 9A68     		ldr	r2, [r3, #8]
+ 599 00c4 42F48002 		orr	r2, r2, #4194304
+ 600 00c8 9A60     		str	r2, [r3, #8]
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 601              		.loc 1 334 10 view .LVU184
+ 602 00ca 0020     		movs	r0, #0
+ 603 00cc 08E0     		b	.L28
+ARM GAS  /tmp/ccfOJcl9.s 			page 33
+
+
+ 604              	.LVL43:
+ 605              	.L32:
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 606              		.loc 1 327 5 is_stmt 1 view .LVU185
+ 607 00ce 036C     		ldr	r3, [r0, #64]
+ 608 00d0 43F01003 		orr	r3, r3, #16
+ 609 00d4 0364     		str	r3, [r0, #64]
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 610              		.loc 1 330 5 view .LVU186
+ 611 00d6 436C     		ldr	r3, [r0, #68]
+ 612 00d8 43F00103 		orr	r3, r3, #1
+ 613 00dc 4364     		str	r3, [r0, #68]
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 614              		.loc 1 334 10 is_stmt 0 view .LVU187
+ 615 00de 0020     		movs	r0, #0
+ 616              	.LVL44:
+ 617              	.L28:
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 618              		.loc 1 335 1 view .LVU188
+ 619 00e0 02B0     		add	sp, sp, #8
+ 620              	.LCFI7:
+ 621              		.cfi_remember_state
+ 622              		.cfi_def_cfa_offset 0
+ 623              		@ sp needed
+ 624 00e2 7047     		bx	lr
+ 625              	.LVL45:
+ 626              	.L35:
+ 627              	.LCFI8:
+ 628              		.cfi_restore_state
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 629              		.loc 1 250 3 view .LVU189
+ 630 00e4 0220     		movs	r0, #2
+ 631              	.LVL46:
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 632              		.loc 1 250 3 view .LVU190
+ 633 00e6 FBE7     		b	.L28
+ 634              	.LVL47:
+ 635              	.L36:
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 636              		.loc 1 334 10 view .LVU191
+ 637 00e8 0020     		movs	r0, #0
+ 638              	.LVL48:
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 639              		.loc 1 334 10 view .LVU192
+ 640 00ea F9E7     		b	.L28
+ 641              	.LVL49:
+ 642              	.L38:
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 643              		.loc 1 334 10 view .LVU193
+ 644 00ec 0020     		movs	r0, #0
+ 645 00ee F7E7     		b	.L28
+ 646              	.L42:
+ 647              		.align	2
+ 648              	.L41:
+ 649 00f0 00000000 		.word	SystemCoreClock
+ 650 00f4 83DE1B43 		.word	1125899907
+ 651 00f8 FECFFFFF 		.word	-12290
+ARM GAS  /tmp/ccfOJcl9.s 			page 34
+
+
+ 652 00fc 00230140 		.word	1073816320
+ 653 0100 00200140 		.word	1073815552
+ 654              		.cfi_endproc
+ 655              	.LFE142:
+ 657              		.section	.text.HAL_ADCEx_InjectedStop,"ax",%progbits
+ 658              		.align	1
+ 659              		.global	HAL_ADCEx_InjectedStop
+ 660              		.syntax unified
+ 661              		.thumb
+ 662              		.thumb_func
+ 663              		.fpu fpv5-d16
+ 665              	HAL_ADCEx_InjectedStop:
+ 666              	.LVL50:
+ 667              	.LFB143:
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 668              		.loc 1 350 1 is_stmt 1 view -0
+ 669              		.cfi_startproc
+ 670              		@ args = 0, pretend = 0, frame = 0
+ 671              		@ frame_needed = 0, uses_anonymous_args = 0
+ 672              		@ link register save eliminated.
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 673              		.loc 1 350 1 is_stmt 0 view .LVU195
+ 674 0000 0346     		mov	r3, r0
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 675              		.loc 1 351 3 is_stmt 1 view .LVU196
+ 676              	.LVL51:
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 677              		.loc 1 354 3 view .LVU197
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 678              		.loc 1 357 3 view .LVU198
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 679              		.loc 1 357 3 view .LVU199
+ 680 0002 90F83C20 		ldrb	r2, [r0, #60]	@ zero_extendqisi2
+ 681 0006 012A     		cmp	r2, #1
+ 682 0008 27D0     		beq	.L47
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 683              		.loc 1 357 3 discriminator 2 view .LVU200
+ 684 000a 0122     		movs	r2, #1
+ 685 000c 80F83C20 		strb	r2, [r0, #60]
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 686              		.loc 1 357 3 discriminator 2 view .LVU201
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+ 687              		.loc 1 365 3 discriminator 2 view .LVU202
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+ 688              		.loc 1 365 12 is_stmt 0 discriminator 2 view .LVU203
+ 689 0010 026C     		ldr	r2, [r0, #64]
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+ 690              		.loc 1 365 5 discriminator 2 view .LVU204
+ 691 0012 12F4807F 		tst	r2, #256
+ 692 0016 15D1     		bne	.L45
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 693              		.loc 1 366 6 discriminator 1 view .LVU205
+ 694 0018 0268     		ldr	r2, [r0]
+ 695 001a 5168     		ldr	r1, [r2, #4]
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+ 696              		.loc 1 365 57 discriminator 1 view .LVU206
+ 697 001c 11F4806F 		tst	r1, #1024
+ARM GAS  /tmp/ccfOJcl9.s 			page 35
+
+
+ 698 0020 10D1     		bne	.L45
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 699              		.loc 1 370 5 is_stmt 1 view .LVU207
+ 700 0022 9168     		ldr	r1, [r2, #8]
+ 701 0024 21F00101 		bic	r1, r1, #1
+ 702 0028 9160     		str	r1, [r2, #8]
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 703              		.loc 1 373 5 view .LVU208
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 704              		.loc 1 373 8 is_stmt 0 view .LVU209
+ 705 002a 0268     		ldr	r2, [r0]
+ 706 002c 9268     		ldr	r2, [r2, #8]
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 707              		.loc 1 373 7 view .LVU210
+ 708 002e 12F0010F 		tst	r2, #1
+ 709 0032 10D1     		bne	.L48
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 710              		.loc 1 376 7 is_stmt 1 view .LVU211
+ 711 0034 016C     		ldr	r1, [r0, #64]
+ 712 0036 0A4A     		ldr	r2, .L49
+ 713 0038 0A40     		ands	r2, r2, r1
+ 714 003a 42F00102 		orr	r2, r2, #1
+ 715 003e 0264     		str	r2, [r0, #64]
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 716              		.loc 1 351 21 is_stmt 0 view .LVU212
+ 717 0040 0020     		movs	r0, #0
+ 718              	.LVL52:
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 719              		.loc 1 351 21 view .LVU213
+ 720 0042 04E0     		b	.L46
+ 721              	.LVL53:
+ 722              	.L45:
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       
+ 723              		.loc 1 384 5 is_stmt 1 view .LVU214
+ 724 0044 1A6C     		ldr	r2, [r3, #64]
+ 725 0046 42F02002 		orr	r2, r2, #32
+ 726 004a 1A64     		str	r2, [r3, #64]
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 727              		.loc 1 386 5 view .LVU215
+ 728              	.LVL54:
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 729              		.loc 1 386 20 is_stmt 0 view .LVU216
+ 730 004c 0120     		movs	r0, #1
+ 731              	.LVL55:
+ 732              	.L46:
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 733              		.loc 1 390 3 is_stmt 1 view .LVU217
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 734              		.loc 1 390 3 view .LVU218
+ 735 004e 0022     		movs	r2, #0
+ 736 0050 83F83C20 		strb	r2, [r3, #60]
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 737              		.loc 1 390 3 view .LVU219
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 738              		.loc 1 393 3 view .LVU220
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 739              		.loc 1 393 10 is_stmt 0 view .LVU221
+ARM GAS  /tmp/ccfOJcl9.s 			page 36
+
+
+ 740 0054 7047     		bx	lr
+ 741              	.LVL56:
+ 742              	.L48:
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 743              		.loc 1 351 21 view .LVU222
+ 744 0056 0020     		movs	r0, #0
+ 745              	.LVL57:
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 746              		.loc 1 351 21 view .LVU223
+ 747 0058 F9E7     		b	.L46
+ 748              	.LVL58:
+ 749              	.L47:
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 750              		.loc 1 357 3 view .LVU224
+ 751 005a 0220     		movs	r0, #2
+ 752              	.LVL59:
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 753              		.loc 1 394 1 view .LVU225
+ 754 005c 7047     		bx	lr
+ 755              	.L50:
+ 756 005e 00BF     		.align	2
+ 757              	.L49:
+ 758 0060 FEEEFFFF 		.word	-4354
+ 759              		.cfi_endproc
+ 760              	.LFE143:
+ 762              		.section	.text.HAL_ADCEx_InjectedPollForConversion,"ax",%progbits
+ 763              		.align	1
+ 764              		.global	HAL_ADCEx_InjectedPollForConversion
+ 765              		.syntax unified
+ 766              		.thumb
+ 767              		.thumb_func
+ 768              		.fpu fpv5-d16
+ 770              	HAL_ADCEx_InjectedPollForConversion:
+ 771              	.LVL60:
+ 772              	.LFB144:
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   uint32_t tickstart = 0;
+ 773              		.loc 1 404 1 is_stmt 1 view -0
+ 774              		.cfi_startproc
+ 775              		@ args = 0, pretend = 0, frame = 0
+ 776              		@ frame_needed = 0, uses_anonymous_args = 0
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   uint32_t tickstart = 0;
+ 777              		.loc 1 404 1 is_stmt 0 view .LVU227
+ 778 0000 70B5     		push	{r4, r5, r6, lr}
+ 779              	.LCFI9:
+ 780              		.cfi_def_cfa_offset 16
+ 781              		.cfi_offset 4, -16
+ 782              		.cfi_offset 5, -12
+ 783              		.cfi_offset 6, -8
+ 784              		.cfi_offset 14, -4
+ 785 0002 0446     		mov	r4, r0
+ 786 0004 0D46     		mov	r5, r1
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 787              		.loc 1 405 3 is_stmt 1 view .LVU228
+ 788              	.LVL61:
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 789              		.loc 1 408 3 view .LVU229
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ARM GAS  /tmp/ccfOJcl9.s 			page 37
+
+
+ 790              		.loc 1 408 15 is_stmt 0 view .LVU230
+ 791 0006 FFF7FEFF 		bl	HAL_GetTick
+ 792              	.LVL62:
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 793              		.loc 1 408 15 view .LVU231
+ 794 000a 0646     		mov	r6, r0
+ 795              	.LVL63:
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 796              		.loc 1 411 3 is_stmt 1 view .LVU232
+ 797              	.L53:
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 798              		.loc 1 411 8 view .LVU233
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 799              		.loc 1 411 11 is_stmt 0 view .LVU234
+ 800 000c 2368     		ldr	r3, [r4]
+ 801 000e 1A68     		ldr	r2, [r3]
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 802              		.loc 1 411 8 view .LVU235
+ 803 0010 12F0040F 		tst	r2, #4
+ 804 0014 15D1     		bne	.L66
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 805              		.loc 1 414 5 is_stmt 1 view .LVU236
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 806              		.loc 1 414 7 is_stmt 0 view .LVU237
+ 807 0016 B5F1FF3F 		cmp	r5, #-1
+ 808 001a F7D0     		beq	.L53
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 809              		.loc 1 416 7 is_stmt 1 view .LVU238
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 810              		.loc 1 416 9 is_stmt 0 view .LVU239
+ 811 001c 5DB9     		cbnz	r5, .L67
+ 812              	.L54:
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         {
+ 813              		.loc 1 419 9 is_stmt 1 view .LVU240
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         {
+ 814              		.loc 1 419 14 is_stmt 0 view .LVU241
+ 815 001e 2368     		ldr	r3, [r4]
+ 816 0020 1B68     		ldr	r3, [r3]
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         {
+ 817              		.loc 1 419 11 view .LVU242
+ 818 0022 13F0040F 		tst	r3, #4
+ 819 0026 F1D1     		bne	.L53
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****           /* Process unlocked */
+ 820              		.loc 1 421 11 is_stmt 1 view .LVU243
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****           /* Process unlocked */
+ 821              		.loc 1 421 22 is_stmt 0 view .LVU244
+ 822 0028 0423     		movs	r3, #4
+ 823 002a 2364     		str	r3, [r4, #64]
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****           return HAL_TIMEOUT;
+ 824              		.loc 1 423 11 is_stmt 1 view .LVU245
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****           return HAL_TIMEOUT;
+ 825              		.loc 1 423 11 view .LVU246
+ 826 002c 0023     		movs	r3, #0
+ 827 002e 84F83C30 		strb	r3, [r4, #60]
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****           return HAL_TIMEOUT;
+ 828              		.loc 1 423 11 view .LVU247
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         }
+ARM GAS  /tmp/ccfOJcl9.s 			page 38
+
+
+ 829              		.loc 1 424 11 view .LVU248
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****         }
+ 830              		.loc 1 424 18 is_stmt 0 view .LVU249
+ 831 0032 0320     		movs	r0, #3
+ 832 0034 32E0     		b	.L56
+ 833              	.L67:
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 834              		.loc 1 416 28 discriminator 1 view .LVU250
+ 835 0036 FFF7FEFF 		bl	HAL_GetTick
+ 836              	.LVL64:
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 837              		.loc 1 416 42 discriminator 1 view .LVU251
+ 838 003a 801B     		subs	r0, r0, r6
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       {
+ 839              		.loc 1 416 24 discriminator 1 view .LVU252
+ 840 003c A842     		cmp	r0, r5
+ 841 003e E5D9     		bls	.L53
+ 842 0040 EDE7     		b	.L54
+ 843              	.L66:
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 844              		.loc 1 431 3 is_stmt 1 view .LVU253
+ 845 0042 6FF00C02 		mvn	r2, #12
+ 846 0046 1A60     		str	r2, [r3]
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 847              		.loc 1 434 3 view .LVU254
+ 848 0048 236C     		ldr	r3, [r4, #64]
+ 849 004a 43F40053 		orr	r3, r3, #8192
+ 850 004e 2364     		str	r3, [r4, #64]
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
+ 851              		.loc 1 442 3 view .LVU255
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
+ 852              		.loc 1 442 6 is_stmt 0 view .LVU256
+ 853 0050 2368     		ldr	r3, [r4]
+ 854 0052 9A68     		ldr	r2, [r3, #8]
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
+ 855              		.loc 1 442 5 view .LVU257
+ 856 0054 12F4401F 		tst	r2, #3145728
+ 857 0058 1FD1     		bne	.L59
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
+ 858              		.loc 1 443 7 discriminator 1 view .LVU258
+ 859 005a 9A6B     		ldr	r2, [r3, #56]
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
+ 860              		.loc 1 442 62 discriminator 1 view .LVU259
+ 861 005c 12F4401F 		tst	r2, #3145728
+ 862 0060 03D0     		beq	.L58
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ 863              		.loc 1 444 7 view .LVU260
+ 864 0062 9A68     		ldr	r2, [r3, #8]
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
+ 865              		.loc 1 443 58 view .LVU261
+ 866 0064 12F4806F 		tst	r2, #1024
+ 867 0068 19D1     		bne	.L60
+ 868              	.L58:
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
+ 869              		.loc 1 445 7 view .LVU262
+ 870 006a 5A68     		ldr	r2, [r3, #4]
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ARM GAS  /tmp/ccfOJcl9.s 			page 39
+
+
+ 871              		.loc 1 444 62 view .LVU263
+ 872 006c 12F4806F 		tst	r2, #1024
+ 873 0070 17D1     		bne	.L61
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
+ 874              		.loc 1 446 8 view .LVU264
+ 875 0072 9B68     		ldr	r3, [r3, #8]
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
+ 876              		.loc 1 445 58 view .LVU265
+ 877 0074 13F0405F 		tst	r3, #805306368
+ 878 0078 15D1     		bne	.L62
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 879              		.loc 1 447 18 view .LVU266
+ 880 007a A369     		ldr	r3, [r4, #24]
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
+ 881              		.loc 1 446 50 view .LVU267
+ 882 007c ABB9     		cbnz	r3, .L63
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 883              		.loc 1 450 5 is_stmt 1 view .LVU268
+ 884 007e 236C     		ldr	r3, [r4, #64]
+ 885 0080 23F48053 		bic	r3, r3, #4096
+ 886 0084 2364     		str	r3, [r4, #64]
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     { 
+ 887              		.loc 1 452 5 view .LVU269
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     { 
+ 888              		.loc 1 452 9 is_stmt 0 view .LVU270
+ 889 0086 236C     		ldr	r3, [r4, #64]
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     { 
+ 890              		.loc 1 452 8 view .LVU271
+ 891 0088 13F4807F 		tst	r3, #256
+ 892 008c 0FD1     		bne	.L64
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 893              		.loc 1 454 7 is_stmt 1 view .LVU272
+ 894 008e 236C     		ldr	r3, [r4, #64]
+ 895 0090 43F00103 		orr	r3, r3, #1
+ 896 0094 2364     		str	r3, [r4, #64]
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }      
+ 897              		.loc 1 459 10 is_stmt 0 view .LVU273
+ 898 0096 0020     		movs	r0, #0
+ 899 0098 00E0     		b	.L56
+ 900              	.L59:
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }      
+ 901              		.loc 1 459 10 view .LVU274
+ 902 009a 0020     		movs	r0, #0
+ 903              	.L56:
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 904              		.loc 1 460 1 view .LVU275
+ 905 009c 70BD     		pop	{r4, r5, r6, pc}
+ 906              	.LVL65:
+ 907              	.L60:
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }      
+ 908              		.loc 1 459 10 view .LVU276
+ 909 009e 0020     		movs	r0, #0
+ 910 00a0 FCE7     		b	.L56
+ 911              	.L61:
+ 912 00a2 0020     		movs	r0, #0
+ 913 00a4 FAE7     		b	.L56
+ 914              	.L62:
+ARM GAS  /tmp/ccfOJcl9.s 			page 40
+
+
+ 915 00a6 0020     		movs	r0, #0
+ 916 00a8 F8E7     		b	.L56
+ 917              	.L63:
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }      
+ 918              		.loc 1 459 10 view .LVU277
+ 919 00aa 0020     		movs	r0, #0
+ 920 00ac F6E7     		b	.L56
+ 921              	.L64:
+ 922 00ae 0020     		movs	r0, #0
+ 923 00b0 F4E7     		b	.L56
+ 924              		.cfi_endproc
+ 925              	.LFE144:
+ 927              		.section	.text.HAL_ADCEx_InjectedStop_IT,"ax",%progbits
+ 928              		.align	1
+ 929              		.global	HAL_ADCEx_InjectedStop_IT
+ 930              		.syntax unified
+ 931              		.thumb
+ 932              		.thumb_func
+ 933              		.fpu fpv5-d16
+ 935              	HAL_ADCEx_InjectedStop_IT:
+ 936              	.LVL66:
+ 937              	.LFB145:
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 938              		.loc 1 475 1 is_stmt 1 view -0
+ 939              		.cfi_startproc
+ 940              		@ args = 0, pretend = 0, frame = 0
+ 941              		@ frame_needed = 0, uses_anonymous_args = 0
+ 942              		@ link register save eliminated.
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 943              		.loc 1 475 1 is_stmt 0 view .LVU279
+ 944 0000 0346     		mov	r3, r0
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 945              		.loc 1 476 3 is_stmt 1 view .LVU280
+ 946              	.LVL67:
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 947              		.loc 1 479 3 view .LVU281
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 948              		.loc 1 482 3 view .LVU282
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 949              		.loc 1 482 3 view .LVU283
+ 950 0002 90F83C20 		ldrb	r2, [r0, #60]	@ zero_extendqisi2
+ 951 0006 012A     		cmp	r2, #1
+ 952 0008 2BD0     		beq	.L72
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 953              		.loc 1 482 3 discriminator 2 view .LVU284
+ 954 000a 0122     		movs	r2, #1
+ 955 000c 80F83C20 		strb	r2, [r0, #60]
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 956              		.loc 1 482 3 discriminator 2 view .LVU285
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+ 957              		.loc 1 490 3 discriminator 2 view .LVU286
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+ 958              		.loc 1 490 12 is_stmt 0 discriminator 2 view .LVU287
+ 959 0010 026C     		ldr	r2, [r0, #64]
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+ 960              		.loc 1 490 5 discriminator 2 view .LVU288
+ 961 0012 12F4807F 		tst	r2, #256
+ARM GAS  /tmp/ccfOJcl9.s 			page 41
+
+
+ 962 0016 19D1     		bne	.L70
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 963              		.loc 1 491 6 discriminator 1 view .LVU289
+ 964 0018 0268     		ldr	r2, [r0]
+ 965 001a 5168     		ldr	r1, [r2, #4]
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
+ 966              		.loc 1 490 57 discriminator 1 view .LVU290
+ 967 001c 11F4806F 		tst	r1, #1024
+ 968 0020 14D1     		bne	.L70
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 969              		.loc 1 495 5 is_stmt 1 view .LVU291
+ 970 0022 9168     		ldr	r1, [r2, #8]
+ 971 0024 21F00101 		bic	r1, r1, #1
+ 972 0028 9160     		str	r1, [r2, #8]
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 973              		.loc 1 498 5 view .LVU292
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 974              		.loc 1 498 8 is_stmt 0 view .LVU293
+ 975 002a 0268     		ldr	r2, [r0]
+ 976 002c 9168     		ldr	r1, [r2, #8]
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 977              		.loc 1 498 7 view .LVU294
+ 978 002e 11F0010F 		tst	r1, #1
+ 979 0032 14D1     		bne	.L73
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       
+ 980              		.loc 1 501 7 is_stmt 1 view .LVU295
+ 981 0034 5168     		ldr	r1, [r2, #4]
+ 982 0036 21F08001 		bic	r1, r1, #128
+ 983 003a 5160     		str	r1, [r2, #4]
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 984              		.loc 1 504 7 view .LVU296
+ 985 003c 016C     		ldr	r1, [r0, #64]
+ 986 003e 0A4A     		ldr	r2, .L74
+ 987 0040 0A40     		ands	r2, r2, r1
+ 988 0042 42F00102 		orr	r2, r2, #1
+ 989 0046 0264     		str	r2, [r0, #64]
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 990              		.loc 1 476 21 is_stmt 0 view .LVU297
+ 991 0048 0020     		movs	r0, #0
+ 992              	.LVL68:
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 993              		.loc 1 476 21 view .LVU298
+ 994 004a 04E0     		b	.L71
+ 995              	.LVL69:
+ 996              	.L70:
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       
+ 997              		.loc 1 512 5 is_stmt 1 view .LVU299
+ 998 004c 1A6C     		ldr	r2, [r3, #64]
+ 999 004e 42F02002 		orr	r2, r2, #32
+ 1000 0052 1A64     		str	r2, [r3, #64]
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1001              		.loc 1 514 5 view .LVU300
+ 1002              	.LVL70:
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1003              		.loc 1 514 20 is_stmt 0 view .LVU301
+ 1004 0054 0120     		movs	r0, #1
+ 1005              	.LVL71:
+ARM GAS  /tmp/ccfOJcl9.s 			page 42
+
+
+ 1006              	.L71:
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1007              		.loc 1 518 3 is_stmt 1 view .LVU302
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1008              		.loc 1 518 3 view .LVU303
+ 1009 0056 0022     		movs	r2, #0
+ 1010 0058 83F83C20 		strb	r2, [r3, #60]
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1011              		.loc 1 518 3 view .LVU304
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1012              		.loc 1 521 3 view .LVU305
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1013              		.loc 1 521 10 is_stmt 0 view .LVU306
+ 1014 005c 7047     		bx	lr
+ 1015              	.LVL72:
+ 1016              	.L73:
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1017              		.loc 1 476 21 view .LVU307
+ 1018 005e 0020     		movs	r0, #0
+ 1019              	.LVL73:
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1020              		.loc 1 476 21 view .LVU308
+ 1021 0060 F9E7     		b	.L71
+ 1022              	.LVL74:
+ 1023              	.L72:
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1024              		.loc 1 482 3 view .LVU309
+ 1025 0062 0220     		movs	r0, #2
+ 1026              	.LVL75:
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1027              		.loc 1 522 1 view .LVU310
+ 1028 0064 7047     		bx	lr
+ 1029              	.L75:
+ 1030 0066 00BF     		.align	2
+ 1031              	.L74:
+ 1032 0068 FEEEFFFF 		.word	-4354
+ 1033              		.cfi_endproc
+ 1034              	.LFE145:
+ 1036              		.section	.text.HAL_ADCEx_InjectedGetValue,"ax",%progbits
+ 1037              		.align	1
+ 1038              		.global	HAL_ADCEx_InjectedGetValue
+ 1039              		.syntax unified
+ 1040              		.thumb
+ 1041              		.thumb_func
+ 1042              		.fpu fpv5-d16
+ 1044              	HAL_ADCEx_InjectedGetValue:
+ 1045              	.LVL76:
+ 1046              	.LFB146:
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t tmp = 0;
+ 1047              		.loc 1 537 1 is_stmt 1 view -0
+ 1048              		.cfi_startproc
+ 1049              		@ args = 0, pretend = 0, frame = 8
+ 1050              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1051              		@ link register save eliminated.
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t tmp = 0;
+ 1052              		.loc 1 537 1 is_stmt 0 view .LVU312
+ 1053 0000 82B0     		sub	sp, sp, #8
+ARM GAS  /tmp/ccfOJcl9.s 			page 43
+
+
+ 1054              	.LCFI10:
+ 1055              		.cfi_def_cfa_offset 8
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1056              		.loc 1 538 3 is_stmt 1 view .LVU313
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1057              		.loc 1 538 17 is_stmt 0 view .LVU314
+ 1058 0002 0023     		movs	r3, #0
+ 1059 0004 0193     		str	r3, [sp, #4]
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1060              		.loc 1 541 3 is_stmt 1 view .LVU315
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1061              		.loc 1 545 3 view .LVU316
+ 1062 0006 0368     		ldr	r3, [r0]
+ 1063 0008 6FF00402 		mvn	r2, #4
+ 1064 000c 1A60     		str	r2, [r3]
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 1065              		.loc 1 548 3 view .LVU317
+ 1066 000e 0139     		subs	r1, r1, #1
+ 1067              	.LVL77:
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 1068              		.loc 1 548 3 is_stmt 0 view .LVU318
+ 1069 0010 0329     		cmp	r1, #3
+ 1070 0012 06D8     		bhi	.L77
+ 1071 0014 DFE801F0 		tbb	[pc, r1]
+ 1072              	.L79:
+ 1073 0018 10       		.byte	(.L82-.L79)/2
+ 1074 0019 0C       		.byte	(.L81-.L79)/2
+ 1075 001a 08       		.byte	(.L80-.L79)/2
+ 1076 001b 02       		.byte	(.L78-.L79)/2
+ 1077              		.p2align 1
+ 1078              	.L78:
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }  
+ 1079              		.loc 1 552 7 is_stmt 1 view .LVU319
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }  
+ 1080              		.loc 1 552 18 is_stmt 0 view .LVU320
+ 1081 001c 0368     		ldr	r3, [r0]
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }  
+ 1082              		.loc 1 552 28 view .LVU321
+ 1083 001e 9B6C     		ldr	r3, [r3, #72]
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }  
+ 1084              		.loc 1 552 11 view .LVU322
+ 1085 0020 0193     		str	r3, [sp, #4]
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_3: 
+ 1086              		.loc 1 554 5 is_stmt 1 view .LVU323
+ 1087              	.L77:
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1088              		.loc 1 573 3 view .LVU324
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1089              		.loc 1 573 10 is_stmt 0 view .LVU325
+ 1090 0022 0198     		ldr	r0, [sp, #4]
+ 1091              	.LVL78:
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1092              		.loc 1 574 1 view .LVU326
+ 1093 0024 02B0     		add	sp, sp, #8
+ 1094              	.LCFI11:
+ 1095              		.cfi_remember_state
+ 1096              		.cfi_def_cfa_offset 0
+ARM GAS  /tmp/ccfOJcl9.s 			page 44
+
+
+ 1097              		@ sp needed
+ 1098 0026 7047     		bx	lr
+ 1099              	.LVL79:
+ 1100              	.L80:
+ 1101              	.LCFI12:
+ 1102              		.cfi_restore_state
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }  
+ 1103              		.loc 1 557 7 is_stmt 1 view .LVU327
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }  
+ 1104              		.loc 1 557 18 is_stmt 0 view .LVU328
+ 1105 0028 0368     		ldr	r3, [r0]
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }  
+ 1106              		.loc 1 557 28 view .LVU329
+ 1107 002a 5B6C     		ldr	r3, [r3, #68]
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }  
+ 1108              		.loc 1 557 11 view .LVU330
+ 1109 002c 0193     		str	r3, [sp, #4]
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_2: 
+ 1110              		.loc 1 559 5 is_stmt 1 view .LVU331
+ 1111 002e F8E7     		b	.L77
+ 1112              	.L81:
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1113              		.loc 1 562 7 view .LVU332
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1114              		.loc 1 562 18 is_stmt 0 view .LVU333
+ 1115 0030 0368     		ldr	r3, [r0]
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1116              		.loc 1 562 28 view .LVU334
+ 1117 0032 1B6C     		ldr	r3, [r3, #64]
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1118              		.loc 1 562 11 view .LVU335
+ 1119 0034 0193     		str	r3, [sp, #4]
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case ADC_INJECTED_RANK_1:
+ 1120              		.loc 1 564 5 is_stmt 1 view .LVU336
+ 1121 0036 F4E7     		b	.L77
+ 1122              	.L82:
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1123              		.loc 1 567 7 view .LVU337
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1124              		.loc 1 567 18 is_stmt 0 view .LVU338
+ 1125 0038 0368     		ldr	r3, [r0]
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1126              		.loc 1 567 28 view .LVU339
+ 1127 003a DB6B     		ldr	r3, [r3, #60]
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1128              		.loc 1 567 11 view .LVU340
+ 1129 003c 0193     		str	r3, [sp, #4]
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     default:
+ 1130              		.loc 1 569 5 is_stmt 1 view .LVU341
+ 1131 003e F0E7     		b	.L77
+ 1132              		.cfi_endproc
+ 1133              	.LFE146:
+ 1135              		.section	.text.HAL_ADCEx_MultiModeStart_DMA,"ax",%progbits
+ 1136              		.align	1
+ 1137              		.global	HAL_ADCEx_MultiModeStart_DMA
+ 1138              		.syntax unified
+ 1139              		.thumb
+ARM GAS  /tmp/ccfOJcl9.s 			page 45
+
+
+ 1140              		.thumb_func
+ 1141              		.fpu fpv5-d16
+ 1143              	HAL_ADCEx_MultiModeStart_DMA:
+ 1144              	.LVL80:
+ 1145              	.LFB147:
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t counter = 0;
+ 1146              		.loc 1 588 1 view -0
+ 1147              		.cfi_startproc
+ 1148              		@ args = 0, pretend = 0, frame = 8
+ 1149              		@ frame_needed = 0, uses_anonymous_args = 0
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   __IO uint32_t counter = 0;
+ 1150              		.loc 1 588 1 is_stmt 0 view .LVU343
+ 1151 0000 30B5     		push	{r4, r5, lr}
+ 1152              	.LCFI13:
+ 1153              		.cfi_def_cfa_offset 12
+ 1154              		.cfi_offset 4, -12
+ 1155              		.cfi_offset 5, -8
+ 1156              		.cfi_offset 14, -4
+ 1157 0002 83B0     		sub	sp, sp, #12
+ 1158              	.LCFI14:
+ 1159              		.cfi_def_cfa_offset 24
+ 1160 0004 1346     		mov	r3, r2
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1161              		.loc 1 589 3 is_stmt 1 view .LVU344
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1162              		.loc 1 589 17 is_stmt 0 view .LVU345
+ 1163 0006 0022     		movs	r2, #0
+ 1164              	.LVL81:
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1165              		.loc 1 589 17 view .LVU346
+ 1166 0008 0192     		str	r2, [sp, #4]
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ 1167              		.loc 1 592 3 is_stmt 1 view .LVU347
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ 1168              		.loc 1 593 3 view .LVU348
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1169              		.loc 1 594 3 view .LVU349
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1170              		.loc 1 597 3 view .LVU350
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1171              		.loc 1 597 3 view .LVU351
+ 1172 000a 90F83C20 		ldrb	r2, [r0, #60]	@ zero_extendqisi2
+ 1173 000e 012A     		cmp	r2, #1
+ 1174 0010 7AD0     		beq	.L95
+ 1175 0012 0446     		mov	r4, r0
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1176              		.loc 1 597 3 discriminator 2 view .LVU352
+ 1177 0014 0122     		movs	r2, #1
+ 1178 0016 80F83C20 		strb	r2, [r0, #60]
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1179              		.loc 1 597 3 discriminator 2 view .LVU353
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 1180              		.loc 1 601 3 discriminator 2 view .LVU354
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 1181              		.loc 1 601 11 is_stmt 0 discriminator 2 view .LVU355
+ 1182 001a 0268     		ldr	r2, [r0]
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ARM GAS  /tmp/ccfOJcl9.s 			page 46
+
+
+ 1183              		.loc 1 601 21 discriminator 2 view .LVU356
+ 1184 001c 9068     		ldr	r0, [r2, #8]
+ 1185              	.LVL82:
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 1186              		.loc 1 601 5 discriminator 2 view .LVU357
+ 1187 001e 10F0010F 		tst	r0, #1
+ 1188 0022 13D1     		bne	.L86
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1189              		.loc 1 604 5 is_stmt 1 view .LVU358
+ 1190 0024 9068     		ldr	r0, [r2, #8]
+ 1191 0026 40F00100 		orr	r0, r0, #1
+ 1192 002a 9060     		str	r0, [r2, #8]
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 1193              		.loc 1 608 5 view .LVU359
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 1194              		.loc 1 608 53 is_stmt 0 view .LVU360
+ 1195 002c 384A     		ldr	r2, .L98
+ 1196 002e 1068     		ldr	r0, [r2]
+ 1197 0030 384A     		ldr	r2, .L98+4
+ 1198 0032 A2FB0020 		umull	r2, r0, r2, r0
+ 1199 0036 800C     		lsrs	r0, r0, #18
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 1200              		.loc 1 608 34 view .LVU361
+ 1201 0038 00EB4000 		add	r0, r0, r0, lsl #1
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     while(counter != 0)
+ 1202              		.loc 1 608 13 view .LVU362
+ 1203 003c 0190     		str	r0, [sp, #4]
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1204              		.loc 1 609 5 is_stmt 1 view .LVU363
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1205              		.loc 1 609 10 is_stmt 0 view .LVU364
+ 1206 003e 02E0     		b	.L87
+ 1207              	.L88:
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1208              		.loc 1 611 7 is_stmt 1 view .LVU365
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1209              		.loc 1 611 14 is_stmt 0 view .LVU366
+ 1210 0040 0198     		ldr	r0, [sp, #4]
+ 1211 0042 0138     		subs	r0, r0, #1
+ 1212 0044 0190     		str	r0, [sp, #4]
+ 1213              	.L87:
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1214              		.loc 1 609 10 is_stmt 1 view .LVU367
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1215              		.loc 1 609 19 is_stmt 0 view .LVU368
+ 1216 0046 0198     		ldr	r0, [sp, #4]
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1217              		.loc 1 609 10 view .LVU369
+ 1218 0048 0028     		cmp	r0, #0
+ 1219 004a F9D1     		bne	.L88
+ 1220              	.L86:
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1221              		.loc 1 616 3 is_stmt 1 view .LVU370
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1222              		.loc 1 616 6 is_stmt 0 view .LVU371
+ 1223 004c 2068     		ldr	r0, [r4]
+ 1224 004e 8268     		ldr	r2, [r0, #8]
+ARM GAS  /tmp/ccfOJcl9.s 			page 47
+
+
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1225              		.loc 1 616 5 view .LVU372
+ 1226 0050 12F0010F 		tst	r2, #1
+ 1227 0054 4DD0     		beq	.L89
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ 1228              		.loc 1 621 5 is_stmt 1 view .LVU373
+ 1229 0056 256C     		ldr	r5, [r4, #64]
+ 1230 0058 2F4A     		ldr	r2, .L98+8
+ 1231 005a 2A40     		ands	r2, r2, r5
+ 1232 005c 42F48072 		orr	r2, r2, #256
+ 1233 0060 2264     		str	r2, [r4, #64]
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1234              		.loc 1 627 5 view .LVU374
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1235              		.loc 1 627 9 is_stmt 0 view .LVU375
+ 1236 0062 4268     		ldr	r2, [r0, #4]
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1237              		.loc 1 627 8 view .LVU376
+ 1238 0064 12F4806F 		tst	r2, #1024
+ 1239 0068 05D0     		beq	.L90
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1240              		.loc 1 629 7 is_stmt 1 view .LVU377
+ 1241 006a 226C     		ldr	r2, [r4, #64]
+ 1242 006c 22F44052 		bic	r2, r2, #12288
+ 1243 0070 42F48052 		orr	r2, r2, #4096
+ 1244 0074 2264     		str	r2, [r4, #64]
+ 1245              	.L90:
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1246              		.loc 1 633 5 view .LVU378
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1247              		.loc 1 633 9 is_stmt 0 view .LVU379
+ 1248 0076 226C     		ldr	r2, [r4, #64]
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1249              		.loc 1 633 8 view .LVU380
+ 1250 0078 12F4805F 		tst	r2, #4096
+ 1251 007c 30D0     		beq	.L91
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1252              		.loc 1 636 7 is_stmt 1 view .LVU381
+ 1253 007e 626C     		ldr	r2, [r4, #68]
+ 1254 0080 22F00602 		bic	r2, r2, #6
+ 1255 0084 6264     		str	r2, [r4, #68]
+ 1256              	.L92:
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1257              		.loc 1 647 5 view .LVU382
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1258              		.loc 1 647 5 view .LVU383
+ 1259 0086 0022     		movs	r2, #0
+ 1260 0088 84F83C20 		strb	r2, [r4, #60]
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1261              		.loc 1 647 5 view .LVU384
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1262              		.loc 1 650 5 view .LVU385
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1263              		.loc 1 650 9 is_stmt 0 view .LVU386
+ 1264 008c A26B     		ldr	r2, [r4, #56]
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1265              		.loc 1 650 40 view .LVU387
+ARM GAS  /tmp/ccfOJcl9.s 			page 48
+
+
+ 1266 008e 2348     		ldr	r0, .L98+12
+ 1267 0090 D063     		str	r0, [r2, #60]
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1268              		.loc 1 653 5 is_stmt 1 view .LVU388
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1269              		.loc 1 653 9 is_stmt 0 view .LVU389
+ 1270 0092 A26B     		ldr	r2, [r4, #56]
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1271              		.loc 1 653 44 view .LVU390
+ 1272 0094 2248     		ldr	r0, .L98+16
+ 1273 0096 1064     		str	r0, [r2, #64]
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1274              		.loc 1 656 5 is_stmt 1 view .LVU391
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1275              		.loc 1 656 9 is_stmt 0 view .LVU392
+ 1276 0098 A26B     		ldr	r2, [r4, #56]
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1277              		.loc 1 656 41 view .LVU393
+ 1278 009a 2248     		ldr	r0, .L98+20
+ 1279 009c D064     		str	r0, [r2, #76]
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1280              		.loc 1 663 5 is_stmt 1 view .LVU394
+ 1281 009e 2268     		ldr	r2, [r4]
+ 1282 00a0 6FF00200 		mvn	r0, #2
+ 1283 00a4 1060     		str	r0, [r2]
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1284              		.loc 1 666 5 view .LVU395
+ 1285 00a6 2068     		ldr	r0, [r4]
+ 1286 00a8 4268     		ldr	r2, [r0, #4]
+ 1287 00aa 42F08062 		orr	r2, r2, #67108864
+ 1288 00ae 4260     		str	r2, [r0, #4]
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1289              		.loc 1 668 5 view .LVU396
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1290              		.loc 1 668 19 is_stmt 0 view .LVU397
+ 1291 00b0 94F83020 		ldrb	r2, [r4, #48]	@ zero_extendqisi2
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1292              		.loc 1 668 8 view .LVU398
+ 1293 00b4 BAB1     		cbz	r2, .L93
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1294              		.loc 1 671 7 is_stmt 1 view .LVU399
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1295              		.loc 1 671 16 is_stmt 0 view .LVU400
+ 1296 00b6 1C48     		ldr	r0, .L98+24
+ 1297 00b8 4268     		ldr	r2, [r0, #4]
+ 1298 00ba 42F40052 		orr	r2, r2, #8192
+ 1299 00be 4260     		str	r2, [r0, #4]
+ 1300              	.L94:
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1301              		.loc 1 680 5 is_stmt 1 view .LVU401
+ 1302 00c0 0A46     		mov	r2, r1
+ 1303 00c2 1A49     		ldr	r1, .L98+28
+ 1304              	.LVL83:
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1305              		.loc 1 680 5 is_stmt 0 view .LVU402
+ 1306 00c4 A06B     		ldr	r0, [r4, #56]
+ 1307 00c6 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ARM GAS  /tmp/ccfOJcl9.s 			page 49
+
+
+ 1308              	.LVL84:
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1309              		.loc 1 683 5 is_stmt 1 view .LVU403
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1310              		.loc 1 683 13 is_stmt 0 view .LVU404
+ 1311 00ca 2368     		ldr	r3, [r4]
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1312              		.loc 1 683 23 view .LVU405
+ 1313 00cc 9A68     		ldr	r2, [r3, #8]
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     {
+ 1314              		.loc 1 683 7 view .LVU406
+ 1315 00ce 12F0405F 		tst	r2, #805306368
+ 1316 00d2 1BD1     		bne	.L96
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1317              		.loc 1 686 7 is_stmt 1 view .LVU407
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1318              		.loc 1 686 27 is_stmt 0 view .LVU408
+ 1319 00d4 9A68     		ldr	r2, [r3, #8]
+ 1320 00d6 42F08042 		orr	r2, r2, #1073741824
+ 1321 00da 9A60     		str	r2, [r3, #8]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1322              		.loc 1 699 10 view .LVU409
+ 1323 00dc 0020     		movs	r0, #0
+ 1324 00de 11E0     		b	.L85
+ 1325              	.LVL85:
+ 1326              	.L91:
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1327              		.loc 1 641 7 is_stmt 1 view .LVU410
+ 1328 00e0 0022     		movs	r2, #0
+ 1329 00e2 6264     		str	r2, [r4, #68]
+ 1330 00e4 CFE7     		b	.L92
+ 1331              	.L93:
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1332              		.loc 1 676 7 view .LVU411
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     }
+ 1333              		.loc 1 676 16 is_stmt 0 view .LVU412
+ 1334 00e6 1048     		ldr	r0, .L98+24
+ 1335 00e8 4268     		ldr	r2, [r0, #4]
+ 1336 00ea 22F40052 		bic	r2, r2, #8192
+ 1337 00ee 4260     		str	r2, [r0, #4]
+ 1338 00f0 E6E7     		b	.L94
+ 1339              	.L89:
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1340              		.loc 1 692 5 is_stmt 1 view .LVU413
+ 1341 00f2 236C     		ldr	r3, [r4, #64]
+ 1342              	.LVL86:
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1343              		.loc 1 692 5 is_stmt 0 view .LVU414
+ 1344 00f4 43F01003 		orr	r3, r3, #16
+ 1345 00f8 2364     		str	r3, [r4, #64]
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1346              		.loc 1 695 5 is_stmt 1 view .LVU415
+ 1347 00fa 636C     		ldr	r3, [r4, #68]
+ 1348 00fc 43F00103 		orr	r3, r3, #1
+ 1349 0100 6364     		str	r3, [r4, #68]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1350              		.loc 1 699 10 is_stmt 0 view .LVU416
+ARM GAS  /tmp/ccfOJcl9.s 			page 50
+
+
+ 1351 0102 0020     		movs	r0, #0
+ 1352              	.LVL87:
+ 1353              	.L85:
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1354              		.loc 1 700 1 view .LVU417
+ 1355 0104 03B0     		add	sp, sp, #12
+ 1356              	.LCFI15:
+ 1357              		.cfi_remember_state
+ 1358              		.cfi_def_cfa_offset 12
+ 1359              		@ sp needed
+ 1360 0106 30BD     		pop	{r4, r5, pc}
+ 1361              	.LVL88:
+ 1362              	.L95:
+ 1363              	.LCFI16:
+ 1364              		.cfi_restore_state
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1365              		.loc 1 597 3 view .LVU418
+ 1366 0108 0220     		movs	r0, #2
+ 1367              	.LVL89:
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1368              		.loc 1 597 3 view .LVU419
+ 1369 010a FBE7     		b	.L85
+ 1370              	.LVL90:
+ 1371              	.L96:
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1372              		.loc 1 699 10 view .LVU420
+ 1373 010c 0020     		movs	r0, #0
+ 1374 010e F9E7     		b	.L85
+ 1375              	.L99:
+ 1376              		.align	2
+ 1377              	.L98:
+ 1378 0110 00000000 		.word	SystemCoreClock
+ 1379 0114 83DE1B43 		.word	1125899907
+ 1380 0118 FEF8FFFF 		.word	-1794
+ 1381 011c 00000000 		.word	ADC_MultiModeDMAConvCplt
+ 1382 0120 00000000 		.word	ADC_MultiModeDMAHalfConvCplt
+ 1383 0124 00000000 		.word	ADC_MultiModeDMAError
+ 1384 0128 00230140 		.word	1073816320
+ 1385 012c 08230140 		.word	1073816328
+ 1386              		.cfi_endproc
+ 1387              	.LFE147:
+ 1389              		.section	.text.HAL_ADCEx_MultiModeStop_DMA,"ax",%progbits
+ 1390              		.align	1
+ 1391              		.global	HAL_ADCEx_MultiModeStop_DMA
+ 1392              		.syntax unified
+ 1393              		.thumb
+ 1394              		.thumb_func
+ 1395              		.fpu fpv5-d16
+ 1397              	HAL_ADCEx_MultiModeStop_DMA:
+ 1398              	.LVL91:
+ 1399              	.LFB148:
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 1400              		.loc 1 709 1 is_stmt 1 view -0
+ 1401              		.cfi_startproc
+ 1402              		@ args = 0, pretend = 0, frame = 0
+ 1403              		@ frame_needed = 0, uses_anonymous_args = 0
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ARM GAS  /tmp/ccfOJcl9.s 			page 51
+
+
+ 1404              		.loc 1 710 3 view .LVU422
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1405              		.loc 1 713 3 view .LVU423
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1406              		.loc 1 716 3 view .LVU424
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1407              		.loc 1 716 3 view .LVU425
+ 1408 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 1409 0004 012B     		cmp	r3, #1
+ 1410 0006 27D0     		beq	.L103
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 1411              		.loc 1 709 1 is_stmt 0 discriminator 2 view .LVU426
+ 1412 0008 10B5     		push	{r4, lr}
+ 1413              	.LCFI17:
+ 1414              		.cfi_def_cfa_offset 8
+ 1415              		.cfi_offset 4, -8
+ 1416              		.cfi_offset 14, -4
+ 1417 000a 0446     		mov	r4, r0
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1418              		.loc 1 716 3 is_stmt 1 discriminator 2 view .LVU427
+ 1419 000c 0123     		movs	r3, #1
+ 1420 000e 80F83C30 		strb	r3, [r0, #60]
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1421              		.loc 1 716 3 discriminator 2 view .LVU428
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1422              		.loc 1 720 3 discriminator 2 view .LVU429
+ 1423 0012 0268     		ldr	r2, [r0]
+ 1424 0014 9368     		ldr	r3, [r2, #8]
+ 1425 0016 23F00103 		bic	r3, r3, #1
+ 1426 001a 9360     		str	r3, [r2, #8]
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1427              		.loc 1 723 3 discriminator 2 view .LVU430
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1428              		.loc 1 723 6 is_stmt 0 discriminator 2 view .LVU431
+ 1429 001c 0368     		ldr	r3, [r0]
+ 1430 001e 9B68     		ldr	r3, [r3, #8]
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1431              		.loc 1 723 5 discriminator 2 view .LVU432
+ 1432 0020 13F0010F 		tst	r3, #1
+ 1433 0024 04D0     		beq	.L109
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1434              		.loc 1 710 21 view .LVU433
+ 1435 0026 0020     		movs	r0, #0
+ 1436              	.LVL92:
+ 1437              	.L102:
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1438              		.loc 1 742 3 is_stmt 1 view .LVU434
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1439              		.loc 1 742 3 view .LVU435
+ 1440 0028 0023     		movs	r3, #0
+ 1441 002a 84F83C30 		strb	r3, [r4, #60]
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1442              		.loc 1 742 3 view .LVU436
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1443              		.loc 1 745 3 view .LVU437
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1444              		.loc 1 746 1 is_stmt 0 view .LVU438
+ARM GAS  /tmp/ccfOJcl9.s 			page 52
+
+
+ 1445 002e 10BD     		pop	{r4, pc}
+ 1446              	.LVL93:
+ 1447              	.L109:
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1448              		.loc 1 726 5 is_stmt 1 view .LVU439
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1449              		.loc 1 726 14 is_stmt 0 view .LVU440
+ 1450 0030 0A4A     		ldr	r2, .L110
+ 1451 0032 5368     		ldr	r3, [r2, #4]
+ 1452 0034 23F40053 		bic	r3, r3, #8192
+ 1453 0038 5360     		str	r3, [r2, #4]
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1454              		.loc 1 730 5 is_stmt 1 view .LVU441
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1455              		.loc 1 730 22 is_stmt 0 view .LVU442
+ 1456 003a 806B     		ldr	r0, [r0, #56]
+ 1457              	.LVL94:
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1458              		.loc 1 730 22 view .LVU443
+ 1459 003c FFF7FEFF 		bl	HAL_DMA_Abort
+ 1460              	.LVL95:
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1461              		.loc 1 733 5 is_stmt 1 view .LVU444
+ 1462 0040 2268     		ldr	r2, [r4]
+ 1463 0042 5368     		ldr	r3, [r2, #4]
+ 1464 0044 23F08063 		bic	r3, r3, #67108864
+ 1465 0048 5360     		str	r3, [r2, #4]
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ 1466              		.loc 1 736 5 view .LVU445
+ 1467 004a 226C     		ldr	r2, [r4, #64]
+ 1468 004c 044B     		ldr	r3, .L110+4
+ 1469 004e 1340     		ands	r3, r3, r2
+ 1470 0050 43F00103 		orr	r3, r3, #1
+ 1471 0054 2364     		str	r3, [r4, #64]
+ 1472 0056 E7E7     		b	.L102
+ 1473              	.LVL96:
+ 1474              	.L103:
+ 1475              	.LCFI18:
+ 1476              		.cfi_def_cfa_offset 0
+ 1477              		.cfi_restore 4
+ 1478              		.cfi_restore 14
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1479              		.loc 1 716 3 is_stmt 0 view .LVU446
+ 1480 0058 0220     		movs	r0, #2
+ 1481              	.LVL97:
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1482              		.loc 1 746 1 view .LVU447
+ 1483 005a 7047     		bx	lr
+ 1484              	.L111:
+ 1485              		.align	2
+ 1486              	.L110:
+ 1487 005c 00230140 		.word	1073816320
+ 1488 0060 FEEEFFFF 		.word	-4354
+ 1489              		.cfi_endproc
+ 1490              	.LFE148:
+ 1492              		.section	.text.HAL_ADCEx_MultiModeGetValue,"ax",%progbits
+ 1493              		.align	1
+ARM GAS  /tmp/ccfOJcl9.s 			page 53
+
+
+ 1494              		.global	HAL_ADCEx_MultiModeGetValue
+ 1495              		.syntax unified
+ 1496              		.thumb
+ 1497              		.thumb_func
+ 1498              		.fpu fpv5-d16
+ 1500              	HAL_ADCEx_MultiModeGetValue:
+ 1501              	.LVL98:
+ 1502              	.LFB149:
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 1503              		.loc 1 756 1 is_stmt 1 view -0
+ 1504              		.cfi_startproc
+ 1505              		@ args = 0, pretend = 0, frame = 0
+ 1506              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1507              		@ link register save eliminated.
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1508              		.loc 1 758 3 view .LVU449
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1509              		.loc 1 761 3 view .LVU450
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1510              		.loc 1 761 13 is_stmt 0 view .LVU451
+ 1511 0000 014B     		ldr	r3, .L113
+ 1512 0002 9868     		ldr	r0, [r3, #8]
+ 1513              	.LVL99:
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1514              		.loc 1 762 1 view .LVU452
+ 1515 0004 7047     		bx	lr
+ 1516              	.L114:
+ 1517 0006 00BF     		.align	2
+ 1518              	.L113:
+ 1519 0008 00230140 		.word	1073816320
+ 1520              		.cfi_endproc
+ 1521              	.LFE149:
+ 1523              		.section	.text.HAL_ADCEx_InjectedConvCpltCallback,"ax",%progbits
+ 1524              		.align	1
+ 1525              		.weak	HAL_ADCEx_InjectedConvCpltCallback
+ 1526              		.syntax unified
+ 1527              		.thumb
+ 1528              		.thumb_func
+ 1529              		.fpu fpv5-d16
+ 1531              	HAL_ADCEx_InjectedConvCpltCallback:
+ 1532              	.LVL100:
+ 1533              	.LFB150:
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 1534              		.loc 1 771 1 is_stmt 1 view -0
+ 1535              		.cfi_startproc
+ 1536              		@ args = 0, pretend = 0, frame = 0
+ 1537              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1538              		@ link register save eliminated.
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 1539              		.loc 1 773 3 view .LVU454
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1540              		.loc 1 777 1 is_stmt 0 view .LVU455
+ 1541 0000 7047     		bx	lr
+ 1542              		.cfi_endproc
+ 1543              	.LFE150:
+ 1545              		.section	.text.HAL_ADCEx_InjectedConfigChannel,"ax",%progbits
+ 1546              		.align	1
+ARM GAS  /tmp/ccfOJcl9.s 			page 54
+
+
+ 1547              		.global	HAL_ADCEx_InjectedConfigChannel
+ 1548              		.syntax unified
+ 1549              		.thumb
+ 1550              		.thumb_func
+ 1551              		.fpu fpv5-d16
+ 1553              	HAL_ADCEx_InjectedConfigChannel:
+ 1554              	.LVL101:
+ 1555              	.LFB151:
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1556              		.loc 1 788 1 is_stmt 1 view -0
+ 1557              		.cfi_startproc
+ 1558              		@ args = 0, pretend = 0, frame = 0
+ 1559              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1560              		@ link register save eliminated.
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+ 1561              		.loc 1 795 3 view .LVU457
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+ 1562              		.loc 1 796 3 view .LVU458
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
+ 1563              		.loc 1 797 3 view .LVU459
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
+ 1564              		.loc 1 798 3 view .LVU460
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+ 1565              		.loc 1 799 3 view .LVU461
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+ 1566              		.loc 1 800 3 view .LVU462
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1567              		.loc 1 801 3 view .LVU463
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1568              		.loc 1 808 3 view .LVU464
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1569              		.loc 1 810 5 view .LVU465
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1570              		.loc 1 814 3 view .LVU466
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1571              		.loc 1 814 3 view .LVU467
+ 1572 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 1573 0004 012B     		cmp	r3, #1
+ 1574 0006 00F0F580 		beq	.L132
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1575              		.loc 1 788 1 is_stmt 0 discriminator 2 view .LVU468
+ 1576 000a 30B4     		push	{r4, r5}
+ 1577              	.LCFI19:
+ 1578              		.cfi_def_cfa_offset 8
+ 1579              		.cfi_offset 4, -8
+ 1580              		.cfi_offset 5, -4
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1581              		.loc 1 814 3 is_stmt 1 discriminator 2 view .LVU469
+ 1582 000c 0123     		movs	r3, #1
+ 1583 000e 80F83C30 		strb	r3, [r0, #60]
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1584              		.loc 1 814 3 discriminator 2 view .LVU470
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1585              		.loc 1 817 3 discriminator 2 view .LVU471
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1586              		.loc 1 817 22 is_stmt 0 discriminator 2 view .LVU472
+ 1587 0012 0B68     		ldr	r3, [r1]
+ARM GAS  /tmp/ccfOJcl9.s 			page 55
+
+
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1588              		.loc 1 817 6 discriminator 2 view .LVU473
+ 1589 0014 092B     		cmp	r3, #9
+ 1590 0016 7DD9     		bls	.L118
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1591              		.loc 1 820 5 is_stmt 1 view .LVU474
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1592              		.loc 1 820 9 is_stmt 0 view .LVU475
+ 1593 0018 0568     		ldr	r5, [r0]
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1594              		.loc 1 820 27 view .LVU476
+ 1595 001a EA68     		ldr	r2, [r5, #12]
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1596              		.loc 1 820 31 view .LVU477
+ 1597 001c 9BB2     		uxth	r3, r3
+ 1598 001e 03EB4303 		add	r3, r3, r3, lsl #1
+ 1599 0022 1E3B     		subs	r3, r3, #30
+ 1600 0024 0724     		movs	r4, #7
+ 1601 0026 04FA03F3 		lsl	r3, r4, r3
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1602              		.loc 1 820 27 view .LVU478
+ 1603 002a 22EA0303 		bic	r3, r2, r3
+ 1604 002e EB60     		str	r3, [r5, #12]
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1605              		.loc 1 823 5 is_stmt 1 view .LVU479
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1606              		.loc 1 823 9 is_stmt 0 view .LVU480
+ 1607 0030 0568     		ldr	r5, [r0]
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1608              		.loc 1 823 27 view .LVU481
+ 1609 0032 EA68     		ldr	r2, [r5, #12]
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1610              		.loc 1 823 30 view .LVU482
+ 1611 0034 8C68     		ldr	r4, [r1, #8]
+ 1612 0036 0B88     		ldrh	r3, [r1]
+ 1613 0038 03EB4303 		add	r3, r3, r3, lsl #1
+ 1614 003c 1E3B     		subs	r3, r3, #30
+ 1615 003e 04FA03F3 		lsl	r3, r4, r3
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1616              		.loc 1 823 27 view .LVU483
+ 1617 0042 1343     		orrs	r3, r3, r2
+ 1618 0044 EB60     		str	r3, [r5, #12]
+ 1619              	.L119:
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
+ 1620              		.loc 1 835 3 is_stmt 1 view .LVU484
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
+ 1621              		.loc 1 835 7 is_stmt 0 view .LVU485
+ 1622 0046 0268     		ldr	r2, [r0]
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
+ 1623              		.loc 1 835 24 view .LVU486
+ 1624 0048 936B     		ldr	r3, [r2, #56]
+ 1625 004a 23F44013 		bic	r3, r3, #3145728
+ 1626 004e 9363     		str	r3, [r2, #56]
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1627              		.loc 1 836 3 is_stmt 1 view .LVU487
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1628              		.loc 1 836 7 is_stmt 0 view .LVU488
+ARM GAS  /tmp/ccfOJcl9.s 			page 56
+
+
+ 1629 0050 0468     		ldr	r4, [r0]
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1630              		.loc 1 836 24 view .LVU489
+ 1631 0052 A36B     		ldr	r3, [r4, #56]
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1632              		.loc 1 836 28 view .LVU490
+ 1633 0054 0A69     		ldr	r2, [r1, #16]
+ 1634 0056 013A     		subs	r2, r2, #1
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1635              		.loc 1 836 24 view .LVU491
+ 1636 0058 43EA0253 		orr	r3, r3, r2, lsl #20
+ 1637 005c A363     		str	r3, [r4, #56]
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****    
+ 1638              		.loc 1 841 3 is_stmt 1 view .LVU492
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****    
+ 1639              		.loc 1 841 7 is_stmt 0 view .LVU493
+ 1640 005e 0468     		ldr	r4, [r0]
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****    
+ 1641              		.loc 1 841 24 view .LVU494
+ 1642 0060 A26B     		ldr	r2, [r4, #56]
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****    
+ 1643              		.loc 1 841 28 view .LVU495
+ 1644 0062 4B68     		ldr	r3, [r1, #4]
+ 1645 0064 0D69     		ldr	r5, [r1, #16]
+ 1646 0066 5B1B     		subs	r3, r3, r5
+ 1647 0068 DBB2     		uxtb	r3, r3
+ 1648 006a 0333     		adds	r3, r3, #3
+ 1649 006c DBB2     		uxtb	r3, r3
+ 1650 006e 03EB8303 		add	r3, r3, r3, lsl #2
+ 1651 0072 4FF01F0C 		mov	ip, #31
+ 1652 0076 0CFA03F3 		lsl	r3, ip, r3
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****    
+ 1653              		.loc 1 841 24 view .LVU496
+ 1654 007a 22EA0303 		bic	r3, r2, r3
+ 1655 007e A363     		str	r3, [r4, #56]
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1656              		.loc 1 844 3 is_stmt 1 view .LVU497
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1657              		.loc 1 844 7 is_stmt 0 view .LVU498
+ 1658 0080 0468     		ldr	r4, [r0]
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1659              		.loc 1 844 24 view .LVU499
+ 1660 0082 A26B     		ldr	r2, [r4, #56]
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1661              		.loc 1 844 27 view .LVU500
+ 1662 0084 4B68     		ldr	r3, [r1, #4]
+ 1663 0086 0D69     		ldr	r5, [r1, #16]
+ 1664 0088 5B1B     		subs	r3, r3, r5
+ 1665 008a DBB2     		uxtb	r3, r3
+ 1666 008c 0333     		adds	r3, r3, #3
+ 1667 008e DBB2     		uxtb	r3, r3
+ 1668 0090 03EB8303 		add	r3, r3, r3, lsl #2
+ 1669 0094 B1F800C0 		ldrh	ip, [r1]
+ 1670 0098 0CFA03F3 		lsl	r3, ip, r3
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1671              		.loc 1 844 24 view .LVU501
+ 1672 009c 1343     		orrs	r3, r3, r2
+ARM GAS  /tmp/ccfOJcl9.s 			page 57
+
+
+ 1673 009e A363     		str	r3, [r4, #56]
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 1674              		.loc 1 851 3 is_stmt 1 view .LVU502
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 1675              		.loc 1 851 21 is_stmt 0 view .LVU503
+ 1676 00a0 8A69     		ldr	r2, [r1, #24]
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {  
+ 1677              		.loc 1 851 5 view .LVU504
+ 1678 00a2 554B     		ldr	r3, .L140
+ 1679 00a4 9A42     		cmp	r2, r3
+ 1680 00a6 4BD0     		beq	.L120
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
+ 1681              		.loc 1 854 5 is_stmt 1 view .LVU505
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
+ 1682              		.loc 1 854 9 is_stmt 0 view .LVU506
+ 1683 00a8 0268     		ldr	r2, [r0]
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
+ 1684              		.loc 1 854 25 view .LVU507
+ 1685 00aa 9368     		ldr	r3, [r2, #8]
+ 1686 00ac 23F47023 		bic	r3, r3, #983040
+ 1687 00b0 9360     		str	r3, [r2, #8]
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1688              		.loc 1 855 5 is_stmt 1 view .LVU508
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1689              		.loc 1 855 9 is_stmt 0 view .LVU509
+ 1690 00b2 0268     		ldr	r2, [r0]
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1691              		.loc 1 855 25 view .LVU510
+ 1692 00b4 9368     		ldr	r3, [r2, #8]
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1693              		.loc 1 855 44 view .LVU511
+ 1694 00b6 8C69     		ldr	r4, [r1, #24]
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1695              		.loc 1 855 25 view .LVU512
+ 1696 00b8 2343     		orrs	r3, r3, r4
+ 1697 00ba 9360     		str	r3, [r2, #8]
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+ 1698              		.loc 1 858 5 is_stmt 1 view .LVU513
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+ 1699              		.loc 1 858 9 is_stmt 0 view .LVU514
+ 1700 00bc 0268     		ldr	r2, [r0]
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+ 1701              		.loc 1 858 25 view .LVU515
+ 1702 00be 9368     		ldr	r3, [r2, #8]
+ 1703 00c0 23F44013 		bic	r3, r3, #3145728
+ 1704 00c4 9360     		str	r3, [r2, #8]
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1705              		.loc 1 859 5 is_stmt 1 view .LVU516
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1706              		.loc 1 859 9 is_stmt 0 view .LVU517
+ 1707 00c6 0268     		ldr	r2, [r0]
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1708              		.loc 1 859 25 view .LVU518
+ 1709 00c8 9368     		ldr	r3, [r2, #8]
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1710              		.loc 1 859 43 view .LVU519
+ 1711 00ca CC69     		ldr	r4, [r1, #28]
+ARM GAS  /tmp/ccfOJcl9.s 			page 58
+
+
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1712              		.loc 1 859 25 view .LVU520
+ 1713 00cc 2343     		orrs	r3, r3, r4
+ 1714 00ce 9360     		str	r3, [r2, #8]
+ 1715              	.L121:
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1716              		.loc 1 868 3 is_stmt 1 view .LVU521
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1717              		.loc 1 868 22 is_stmt 0 view .LVU522
+ 1718 00d0 4B7D     		ldrb	r3, [r1, #21]	@ zero_extendqisi2
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1719              		.loc 1 868 6 view .LVU523
+ 1720 00d2 002B     		cmp	r3, #0
+ 1721 00d4 3FD0     		beq	.L122
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1722              		.loc 1 871 5 is_stmt 1 view .LVU524
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1723              		.loc 1 871 9 is_stmt 0 view .LVU525
+ 1724 00d6 0268     		ldr	r2, [r0]
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1725              		.loc 1 871 25 view .LVU526
+ 1726 00d8 5368     		ldr	r3, [r2, #4]
+ 1727 00da 43F48063 		orr	r3, r3, #1024
+ 1728 00de 5360     		str	r3, [r2, #4]
+ 1729              	.L123:
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1730              		.loc 1 879 3 is_stmt 1 view .LVU527
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1731              		.loc 1 879 22 is_stmt 0 view .LVU528
+ 1732 00e0 0B7D     		ldrb	r3, [r1, #20]	@ zero_extendqisi2
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1733              		.loc 1 879 6 view .LVU529
+ 1734 00e2 002B     		cmp	r3, #0
+ 1735 00e4 3DD0     		beq	.L124
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1736              		.loc 1 882 5 is_stmt 1 view .LVU530
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1737              		.loc 1 882 9 is_stmt 0 view .LVU531
+ 1738 00e6 0268     		ldr	r2, [r0]
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1739              		.loc 1 882 25 view .LVU532
+ 1740 00e8 5368     		ldr	r3, [r2, #4]
+ 1741 00ea 43F48053 		orr	r3, r3, #4096
+ 1742 00ee 5360     		str	r3, [r2, #4]
+ 1743              	.L125:
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1744              		.loc 1 890 3 is_stmt 1 view .LVU533
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1745              		.loc 1 890 25 is_stmt 0 view .LVU534
+ 1746 00f0 4B68     		ldr	r3, [r1, #4]
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1747              		.loc 1 890 3 view .LVU535
+ 1748 00f2 022B     		cmp	r3, #2
+ 1749 00f4 53D0     		beq	.L126
+ 1750 00f6 032B     		cmp	r3, #3
+ 1751 00f8 5CD0     		beq	.L127
+ 1752 00fa 012B     		cmp	r3, #1
+ARM GAS  /tmp/ccfOJcl9.s 			page 59
+
+
+ 1753 00fc 37D0     		beq	.L137
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
+ 1754              		.loc 1 909 7 is_stmt 1 view .LVU536
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
+ 1755              		.loc 1 909 11 is_stmt 0 view .LVU537
+ 1756 00fe 0268     		ldr	r2, [r0]
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
+ 1757              		.loc 1 909 29 view .LVU538
+ 1758 0100 146A     		ldr	r4, [r2, #32]
+ 1759 0102 3E4B     		ldr	r3, .L140+4
+ 1760 0104 2340     		ands	r3, r3, r4
+ 1761 0106 1362     		str	r3, [r2, #32]
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1762              		.loc 1 910 7 is_stmt 1 view .LVU539
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1763              		.loc 1 910 11 is_stmt 0 view .LVU540
+ 1764 0108 0268     		ldr	r2, [r0]
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1765              		.loc 1 910 29 view .LVU541
+ 1766 010a 136A     		ldr	r3, [r2, #32]
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1767              		.loc 1 910 47 view .LVU542
+ 1768 010c CC68     		ldr	r4, [r1, #12]
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1769              		.loc 1 910 29 view .LVU543
+ 1770 010e 2343     		orrs	r3, r3, r4
+ 1771 0110 1362     		str	r3, [r2, #32]
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1772              		.loc 1 911 7 is_stmt 1 view .LVU544
+ 1773 0112 36E0     		b	.L129
+ 1774              	.L118:
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1775              		.loc 1 828 5 view .LVU545
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1776              		.loc 1 828 9 is_stmt 0 view .LVU546
+ 1777 0114 0568     		ldr	r5, [r0]
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1778              		.loc 1 828 27 view .LVU547
+ 1779 0116 2A69     		ldr	r2, [r5, #16]
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1780              		.loc 1 828 31 view .LVU548
+ 1781 0118 9BB2     		uxth	r3, r3
+ 1782 011a 03EB4303 		add	r3, r3, r3, lsl #1
+ 1783 011e 0724     		movs	r4, #7
+ 1784 0120 04FA03F3 		lsl	r3, r4, r3
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     
+ 1785              		.loc 1 828 27 view .LVU549
+ 1786 0124 22EA0303 		bic	r3, r2, r3
+ 1787 0128 2B61     		str	r3, [r5, #16]
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1788              		.loc 1 831 5 is_stmt 1 view .LVU550
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1789              		.loc 1 831 9 is_stmt 0 view .LVU551
+ 1790 012a 0568     		ldr	r5, [r0]
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1791              		.loc 1 831 27 view .LVU552
+ 1792 012c 2A69     		ldr	r2, [r5, #16]
+ARM GAS  /tmp/ccfOJcl9.s 			page 60
+
+
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1793              		.loc 1 831 30 view .LVU553
+ 1794 012e 8C68     		ldr	r4, [r1, #8]
+ 1795 0130 0B88     		ldrh	r3, [r1]
+ 1796 0132 03EB4303 		add	r3, r3, r3, lsl #1
+ 1797 0136 04FA03F3 		lsl	r3, r4, r3
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1798              		.loc 1 831 27 view .LVU554
+ 1799 013a 1343     		orrs	r3, r3, r2
+ 1800 013c 2B61     		str	r3, [r5, #16]
+ 1801 013e 82E7     		b	.L119
+ 1802              	.L120:
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);  
+ 1803              		.loc 1 864 5 is_stmt 1 view .LVU555
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);  
+ 1804              		.loc 1 864 9 is_stmt 0 view .LVU556
+ 1805 0140 0268     		ldr	r2, [r0]
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);  
+ 1806              		.loc 1 864 25 view .LVU557
+ 1807 0142 9368     		ldr	r3, [r2, #8]
+ 1808 0144 23F47023 		bic	r3, r3, #983040
+ 1809 0148 9360     		str	r3, [r2, #8]
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1810              		.loc 1 865 5 is_stmt 1 view .LVU558
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1811              		.loc 1 865 9 is_stmt 0 view .LVU559
+ 1812 014a 0268     		ldr	r2, [r0]
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1813              		.loc 1 865 25 view .LVU560
+ 1814 014c 9368     		ldr	r3, [r2, #8]
+ 1815 014e 23F44013 		bic	r3, r3, #3145728
+ 1816 0152 9360     		str	r3, [r2, #8]
+ 1817 0154 BCE7     		b	.L121
+ 1818              	.L122:
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1819              		.loc 1 876 5 is_stmt 1 view .LVU561
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1820              		.loc 1 876 9 is_stmt 0 view .LVU562
+ 1821 0156 0268     		ldr	r2, [r0]
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1822              		.loc 1 876 25 view .LVU563
+ 1823 0158 5368     		ldr	r3, [r2, #4]
+ 1824 015a 23F48063 		bic	r3, r3, #1024
+ 1825 015e 5360     		str	r3, [r2, #4]
+ 1826 0160 BEE7     		b	.L123
+ 1827              	.L124:
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1828              		.loc 1 887 5 is_stmt 1 view .LVU564
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1829              		.loc 1 887 9 is_stmt 0 view .LVU565
+ 1830 0162 0268     		ldr	r2, [r0]
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1831              		.loc 1 887 25 view .LVU566
+ 1832 0164 5368     		ldr	r3, [r2, #4]
+ 1833 0166 23F48053 		bic	r3, r3, #4096
+ 1834 016a 5360     		str	r3, [r2, #4]
+ 1835 016c C0E7     		b	.L125
+ARM GAS  /tmp/ccfOJcl9.s 			page 61
+
+
+ 1836              	.L137:
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
+ 1837              		.loc 1 894 7 is_stmt 1 view .LVU567
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
+ 1838              		.loc 1 894 11 is_stmt 0 view .LVU568
+ 1839 016e 0268     		ldr	r2, [r0]
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
+ 1840              		.loc 1 894 29 view .LVU569
+ 1841 0170 5469     		ldr	r4, [r2, #20]
+ 1842 0172 224B     		ldr	r3, .L140+4
+ 1843 0174 2340     		ands	r3, r3, r4
+ 1844 0176 5361     		str	r3, [r2, #20]
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1845              		.loc 1 895 7 is_stmt 1 view .LVU570
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1846              		.loc 1 895 11 is_stmt 0 view .LVU571
+ 1847 0178 0268     		ldr	r2, [r0]
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1848              		.loc 1 895 29 view .LVU572
+ 1849 017a 5369     		ldr	r3, [r2, #20]
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1850              		.loc 1 895 47 view .LVU573
+ 1851 017c CC68     		ldr	r4, [r1, #12]
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1852              		.loc 1 895 29 view .LVU574
+ 1853 017e 2343     		orrs	r3, r3, r4
+ 1854 0180 5361     		str	r3, [r2, #20]
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case 2:
+ 1855              		.loc 1 896 7 is_stmt 1 view .LVU575
+ 1856              	.L129:
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1857              		.loc 1 915 3 view .LVU576
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1858              		.loc 1 915 12 is_stmt 0 view .LVU577
+ 1859 0182 0268     		ldr	r2, [r0]
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1860              		.loc 1 915 6 view .LVU578
+ 1861 0184 1E4B     		ldr	r3, .L140+8
+ 1862 0186 9A42     		cmp	r2, r3
+ 1863 0188 1FD0     		beq	.L138
+ 1864              	.L130:
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1865              		.loc 1 922 3 is_stmt 1 view .LVU579
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1866              		.loc 1 922 12 is_stmt 0 view .LVU580
+ 1867 018a 0268     		ldr	r2, [r0]
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1868              		.loc 1 922 6 view .LVU581
+ 1869 018c 1C4B     		ldr	r3, .L140+8
+ 1870 018e 9A42     		cmp	r2, r3
+ 1871 0190 24D0     		beq	.L139
+ 1872              	.L131:
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1873              		.loc 1 929 3 is_stmt 1 view .LVU582
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1874              		.loc 1 929 3 view .LVU583
+ 1875 0192 0023     		movs	r3, #0
+ARM GAS  /tmp/ccfOJcl9.s 			page 62
+
+
+ 1876 0194 80F83C30 		strb	r3, [r0, #60]
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1877              		.loc 1 929 3 view .LVU584
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1878              		.loc 1 932 3 view .LVU585
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 1879              		.loc 1 932 10 is_stmt 0 view .LVU586
+ 1880 0198 1846     		mov	r0, r3
+ 1881              	.LVL102:
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1882              		.loc 1 933 1 view .LVU587
+ 1883 019a 30BC     		pop	{r4, r5}
+ 1884              	.LCFI20:
+ 1885              		.cfi_remember_state
+ 1886              		.cfi_restore 5
+ 1887              		.cfi_restore 4
+ 1888              		.cfi_def_cfa_offset 0
+ 1889 019c 7047     		bx	lr
+ 1890              	.LVL103:
+ 1891              	.L126:
+ 1892              	.LCFI21:
+ 1893              		.cfi_restore_state
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
+ 1894              		.loc 1 899 7 is_stmt 1 view .LVU588
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
+ 1895              		.loc 1 899 11 is_stmt 0 view .LVU589
+ 1896 019e 0268     		ldr	r2, [r0]
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
+ 1897              		.loc 1 899 29 view .LVU590
+ 1898 01a0 9469     		ldr	r4, [r2, #24]
+ 1899 01a2 164B     		ldr	r3, .L140+4
+ 1900 01a4 2340     		ands	r3, r3, r4
+ 1901 01a6 9361     		str	r3, [r2, #24]
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1902              		.loc 1 900 7 is_stmt 1 view .LVU591
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1903              		.loc 1 900 11 is_stmt 0 view .LVU592
+ 1904 01a8 0268     		ldr	r2, [r0]
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1905              		.loc 1 900 29 view .LVU593
+ 1906 01aa 9369     		ldr	r3, [r2, #24]
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1907              		.loc 1 900 47 view .LVU594
+ 1908 01ac CC68     		ldr	r4, [r1, #12]
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1909              		.loc 1 900 29 view .LVU595
+ 1910 01ae 2343     		orrs	r3, r3, r4
+ 1911 01b0 9361     		str	r3, [r2, #24]
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     case 3:
+ 1912              		.loc 1 901 7 is_stmt 1 view .LVU596
+ 1913 01b2 E6E7     		b	.L129
+ 1914              	.L127:
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
+ 1915              		.loc 1 904 7 view .LVU597
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
+ 1916              		.loc 1 904 11 is_stmt 0 view .LVU598
+ 1917 01b4 0268     		ldr	r2, [r0]
+ARM GAS  /tmp/ccfOJcl9.s 			page 63
+
+
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
+ 1918              		.loc 1 904 29 view .LVU599
+ 1919 01b6 D469     		ldr	r4, [r2, #28]
+ 1920 01b8 104B     		ldr	r3, .L140+4
+ 1921 01ba 2340     		ands	r3, r3, r4
+ 1922 01bc D361     		str	r3, [r2, #28]
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1923              		.loc 1 905 7 is_stmt 1 view .LVU600
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1924              		.loc 1 905 11 is_stmt 0 view .LVU601
+ 1925 01be 0268     		ldr	r2, [r0]
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1926              		.loc 1 905 29 view .LVU602
+ 1927 01c0 D369     		ldr	r3, [r2, #28]
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1928              		.loc 1 905 47 view .LVU603
+ 1929 01c2 CC68     		ldr	r4, [r1, #12]
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****       break;
+ 1930              		.loc 1 905 29 view .LVU604
+ 1931 01c4 2343     		orrs	r3, r3, r4
+ 1932 01c6 D361     		str	r3, [r2, #28]
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****     default:
+ 1933              		.loc 1 906 7 is_stmt 1 view .LVU605
+ 1934 01c8 DBE7     		b	.L129
+ 1935              	.L138:
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1936              		.loc 1 915 51 is_stmt 0 discriminator 1 view .LVU606
+ 1937 01ca 0B68     		ldr	r3, [r1]
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1938              		.loc 1 915 32 discriminator 1 view .LVU607
+ 1939 01cc 122B     		cmp	r3, #18
+ 1940 01ce DCD1     		bne	.L130
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1941              		.loc 1 918 5 is_stmt 1 view .LVU608
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1942              		.loc 1 918 14 is_stmt 0 view .LVU609
+ 1943 01d0 0C4A     		ldr	r2, .L140+12
+ 1944 01d2 5368     		ldr	r3, [r2, #4]
+ 1945 01d4 43F48003 		orr	r3, r3, #4194304
+ 1946 01d8 5360     		str	r3, [r2, #4]
+ 1947 01da D6E7     		b	.L130
+ 1948              	.L139:
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1949              		.loc 1 922 52 discriminator 1 view .LVU610
+ 1950 01dc 0B68     		ldr	r3, [r1]
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   {
+ 1951              		.loc 1 922 32 discriminator 1 view .LVU611
+ 1952 01de 0A4A     		ldr	r2, .L140+16
+ 1953 01e0 112B     		cmp	r3, #17
+ 1954 01e2 18BF     		it	ne
+ 1955 01e4 9342     		cmpne	r3, r2
+ 1956 01e6 D4D1     		bne	.L131
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1957              		.loc 1 925 5 is_stmt 1 view .LVU612
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   }
+ 1958              		.loc 1 925 14 is_stmt 0 view .LVU613
+ 1959 01e8 064A     		ldr	r2, .L140+12
+ARM GAS  /tmp/ccfOJcl9.s 			page 64
+
+
+ 1960 01ea 5368     		ldr	r3, [r2, #4]
+ 1961 01ec 43F40003 		orr	r3, r3, #8388608
+ 1962 01f0 5360     		str	r3, [r2, #4]
+ 1963 01f2 CEE7     		b	.L131
+ 1964              	.L132:
+ 1965              	.LCFI22:
+ 1966              		.cfi_def_cfa_offset 0
+ 1967              		.cfi_restore 4
+ 1968              		.cfi_restore 5
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 1969              		.loc 1 814 3 view .LVU614
+ 1970 01f4 0220     		movs	r0, #2
+ 1971              	.LVL104:
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 1972              		.loc 1 933 1 view .LVU615
+ 1973 01f6 7047     		bx	lr
+ 1974              	.L141:
+ 1975              		.align	2
+ 1976              	.L140:
+ 1977 01f8 01000F00 		.word	983041
+ 1978 01fc 00F0FFFF 		.word	-4096
+ 1979 0200 00200140 		.word	1073815552
+ 1980 0204 00230140 		.word	1073816320
+ 1981 0208 12000010 		.word	268435474
+ 1982              		.cfi_endproc
+ 1983              	.LFE151:
+ 1985              		.section	.text.HAL_ADCEx_MultiModeConfigChannel,"ax",%progbits
+ 1986              		.align	1
+ 1987              		.global	HAL_ADCEx_MultiModeConfigChannel
+ 1988              		.syntax unified
+ 1989              		.thumb
+ 1990              		.thumb_func
+ 1991              		.fpu fpv5-d16
+ 1993              	HAL_ADCEx_MultiModeConfigChannel:
+ 1994              	.LVL105:
+ 1995              	.LFB152:
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check the parameters */
+ 1996              		.loc 1 944 1 is_stmt 1 view -0
+ 1997              		.cfi_startproc
+ 1998              		@ args = 0, pretend = 0, frame = 0
+ 1999              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2000              		@ link register save eliminated.
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
+ 2001              		.loc 1 946 3 view .LVU617
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
+ 2002              		.loc 1 947 3 view .LVU618
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2003              		.loc 1 948 3 view .LVU619
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2004              		.loc 1 951 3 view .LVU620
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2005              		.loc 1 951 3 view .LVU621
+ 2006 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 2007 0004 012B     		cmp	r3, #1
+ 2008 0006 23D0     		beq	.L144
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   /* Check the parameters */
+ 2009              		.loc 1 944 1 is_stmt 0 discriminator 2 view .LVU622
+ARM GAS  /tmp/ccfOJcl9.s 			page 65
+
+
+ 2010 0008 10B4     		push	{r4}
+ 2011              	.LCFI23:
+ 2012              		.cfi_def_cfa_offset 4
+ 2013              		.cfi_offset 4, -4
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2014              		.loc 1 951 3 is_stmt 1 discriminator 2 view .LVU623
+ 2015 000a 0123     		movs	r3, #1
+ 2016 000c 80F83C30 		strb	r3, [r0, #60]
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2017              		.loc 1 951 3 discriminator 2 view .LVU624
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR |= multimode->Mode;
+ 2018              		.loc 1 954 3 discriminator 2 view .LVU625
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR |= multimode->Mode;
+ 2019              		.loc 1 954 12 is_stmt 0 discriminator 2 view .LVU626
+ 2020 0010 104B     		ldr	r3, .L149
+ 2021 0012 5A68     		ldr	r2, [r3, #4]
+ 2022 0014 22F01F02 		bic	r2, r2, #31
+ 2023 0018 5A60     		str	r2, [r3, #4]
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2024              		.loc 1 955 3 is_stmt 1 discriminator 2 view .LVU627
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2025              		.loc 1 955 12 is_stmt 0 discriminator 2 view .LVU628
+ 2026 001a 5A68     		ldr	r2, [r3, #4]
+ 2027 001c 0C68     		ldr	r4, [r1]
+ 2028 001e 2243     		orrs	r2, r2, r4
+ 2029 0020 5A60     		str	r2, [r3, #4]
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR |= multimode->DMAAccessMode;
+ 2030              		.loc 1 958 3 is_stmt 1 discriminator 2 view .LVU629
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR |= multimode->DMAAccessMode;
+ 2031              		.loc 1 958 12 is_stmt 0 discriminator 2 view .LVU630
+ 2032 0022 5A68     		ldr	r2, [r3, #4]
+ 2033 0024 22F44042 		bic	r2, r2, #49152
+ 2034 0028 5A60     		str	r2, [r3, #4]
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2035              		.loc 1 959 3 is_stmt 1 discriminator 2 view .LVU631
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2036              		.loc 1 959 12 is_stmt 0 discriminator 2 view .LVU632
+ 2037 002a 5A68     		ldr	r2, [r3, #4]
+ 2038 002c 4C68     		ldr	r4, [r1, #4]
+ 2039 002e 2243     		orrs	r2, r2, r4
+ 2040 0030 5A60     		str	r2, [r3, #4]
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR |= multimode->TwoSamplingDelay;
+ 2041              		.loc 1 962 3 is_stmt 1 discriminator 2 view .LVU633
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   ADC->CCR |= multimode->TwoSamplingDelay;
+ 2042              		.loc 1 962 12 is_stmt 0 discriminator 2 view .LVU634
+ 2043 0032 5A68     		ldr	r2, [r3, #4]
+ 2044 0034 22F47062 		bic	r2, r2, #3840
+ 2045 0038 5A60     		str	r2, [r3, #4]
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2046              		.loc 1 963 3 is_stmt 1 discriminator 2 view .LVU635
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2047              		.loc 1 963 12 is_stmt 0 discriminator 2 view .LVU636
+ 2048 003a 5A68     		ldr	r2, [r3, #4]
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2049              		.loc 1 963 24 discriminator 2 view .LVU637
+ 2050 003c 8968     		ldr	r1, [r1, #8]
+ 2051              	.LVL106:
+ARM GAS  /tmp/ccfOJcl9.s 			page 66
+
+
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2052              		.loc 1 963 12 discriminator 2 view .LVU638
+ 2053 003e 0A43     		orrs	r2, r2, r1
+ 2054 0040 5A60     		str	r2, [r3, #4]
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2055              		.loc 1 966 3 is_stmt 1 discriminator 2 view .LVU639
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2056              		.loc 1 966 3 discriminator 2 view .LVU640
+ 2057 0042 0023     		movs	r3, #0
+ 2058 0044 80F83C30 		strb	r3, [r0, #60]
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2059              		.loc 1 966 3 discriminator 2 view .LVU641
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 2060              		.loc 1 969 3 discriminator 2 view .LVU642
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** }
+ 2061              		.loc 1 969 10 is_stmt 0 discriminator 2 view .LVU643
+ 2062 0048 1846     		mov	r0, r3
+ 2063              	.LVL107:
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 2064              		.loc 1 970 1 discriminator 2 view .LVU644
+ 2065 004a 5DF8044B 		ldr	r4, [sp], #4
+ 2066              	.LCFI24:
+ 2067              		.cfi_restore 4
+ 2068              		.cfi_def_cfa_offset 0
+ 2069 004e 7047     		bx	lr
+ 2070              	.LVL108:
+ 2071              	.L144:
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c ****   
+ 2072              		.loc 1 951 3 view .LVU645
+ 2073 0050 0220     		movs	r0, #2
+ 2074              	.LVL109:
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** 
+ 2075              		.loc 1 970 1 view .LVU646
+ 2076 0052 7047     		bx	lr
+ 2077              	.L150:
+ 2078              		.align	2
+ 2079              	.L149:
+ 2080 0054 00230140 		.word	1073816320
+ 2081              		.cfi_endproc
+ 2082              	.LFE152:
+ 2084              		.text
+ 2085              	.Letext0:
+ 2086              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 2087              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 2088              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 2089              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 2090              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 2091              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h"
+ 2092              		.file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h"
+ 2093              		.file 9 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h"
+ 2094              		.file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ARM GAS  /tmp/ccfOJcl9.s 			page 67
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_adc_ex.c
+     /tmp/ccfOJcl9.s:17     .text.ADC_MultiModeDMAError:0000000000000000 $t
+     /tmp/ccfOJcl9.s:24     .text.ADC_MultiModeDMAError:0000000000000000 ADC_MultiModeDMAError
+     /tmp/ccfOJcl9.s:60     .text.ADC_MultiModeDMAHalfConvCplt:0000000000000000 $t
+     /tmp/ccfOJcl9.s:66     .text.ADC_MultiModeDMAHalfConvCplt:0000000000000000 ADC_MultiModeDMAHalfConvCplt
+     /tmp/ccfOJcl9.s:93     .text.ADC_MultiModeDMAConvCplt:0000000000000000 $t
+     /tmp/ccfOJcl9.s:99     .text.ADC_MultiModeDMAConvCplt:0000000000000000 ADC_MultiModeDMAConvCplt
+     /tmp/ccfOJcl9.s:193    .text.HAL_ADCEx_InjectedStart:0000000000000000 $t
+     /tmp/ccfOJcl9.s:200    .text.HAL_ADCEx_InjectedStart:0000000000000000 HAL_ADCEx_InjectedStart
+     /tmp/ccfOJcl9.s:414    .text.HAL_ADCEx_InjectedStart:00000000000000e8 $d
+     /tmp/ccfOJcl9.s:423    .text.HAL_ADCEx_InjectedStart_IT:0000000000000000 $t
+     /tmp/ccfOJcl9.s:430    .text.HAL_ADCEx_InjectedStart_IT:0000000000000000 HAL_ADCEx_InjectedStart_IT
+     /tmp/ccfOJcl9.s:649    .text.HAL_ADCEx_InjectedStart_IT:00000000000000f0 $d
+     /tmp/ccfOJcl9.s:658    .text.HAL_ADCEx_InjectedStop:0000000000000000 $t
+     /tmp/ccfOJcl9.s:665    .text.HAL_ADCEx_InjectedStop:0000000000000000 HAL_ADCEx_InjectedStop
+     /tmp/ccfOJcl9.s:758    .text.HAL_ADCEx_InjectedStop:0000000000000060 $d
+     /tmp/ccfOJcl9.s:763    .text.HAL_ADCEx_InjectedPollForConversion:0000000000000000 $t
+     /tmp/ccfOJcl9.s:770    .text.HAL_ADCEx_InjectedPollForConversion:0000000000000000 HAL_ADCEx_InjectedPollForConversion
+     /tmp/ccfOJcl9.s:928    .text.HAL_ADCEx_InjectedStop_IT:0000000000000000 $t
+     /tmp/ccfOJcl9.s:935    .text.HAL_ADCEx_InjectedStop_IT:0000000000000000 HAL_ADCEx_InjectedStop_IT
+     /tmp/ccfOJcl9.s:1032   .text.HAL_ADCEx_InjectedStop_IT:0000000000000068 $d
+     /tmp/ccfOJcl9.s:1037   .text.HAL_ADCEx_InjectedGetValue:0000000000000000 $t
+     /tmp/ccfOJcl9.s:1044   .text.HAL_ADCEx_InjectedGetValue:0000000000000000 HAL_ADCEx_InjectedGetValue
+     /tmp/ccfOJcl9.s:1073   .text.HAL_ADCEx_InjectedGetValue:0000000000000018 $d
+     /tmp/ccfOJcl9.s:1077   .text.HAL_ADCEx_InjectedGetValue:000000000000001c $t
+     /tmp/ccfOJcl9.s:1136   .text.HAL_ADCEx_MultiModeStart_DMA:0000000000000000 $t
+     /tmp/ccfOJcl9.s:1143   .text.HAL_ADCEx_MultiModeStart_DMA:0000000000000000 HAL_ADCEx_MultiModeStart_DMA
+     /tmp/ccfOJcl9.s:1378   .text.HAL_ADCEx_MultiModeStart_DMA:0000000000000110 $d
+     /tmp/ccfOJcl9.s:1390   .text.HAL_ADCEx_MultiModeStop_DMA:0000000000000000 $t
+     /tmp/ccfOJcl9.s:1397   .text.HAL_ADCEx_MultiModeStop_DMA:0000000000000000 HAL_ADCEx_MultiModeStop_DMA
+     /tmp/ccfOJcl9.s:1487   .text.HAL_ADCEx_MultiModeStop_DMA:000000000000005c $d
+     /tmp/ccfOJcl9.s:1493   .text.HAL_ADCEx_MultiModeGetValue:0000000000000000 $t
+     /tmp/ccfOJcl9.s:1500   .text.HAL_ADCEx_MultiModeGetValue:0000000000000000 HAL_ADCEx_MultiModeGetValue
+     /tmp/ccfOJcl9.s:1519   .text.HAL_ADCEx_MultiModeGetValue:0000000000000008 $d
+     /tmp/ccfOJcl9.s:1524   .text.HAL_ADCEx_InjectedConvCpltCallback:0000000000000000 $t
+     /tmp/ccfOJcl9.s:1531   .text.HAL_ADCEx_InjectedConvCpltCallback:0000000000000000 HAL_ADCEx_InjectedConvCpltCallback
+     /tmp/ccfOJcl9.s:1546   .text.HAL_ADCEx_InjectedConfigChannel:0000000000000000 $t
+     /tmp/ccfOJcl9.s:1553   .text.HAL_ADCEx_InjectedConfigChannel:0000000000000000 HAL_ADCEx_InjectedConfigChannel
+     /tmp/ccfOJcl9.s:1977   .text.HAL_ADCEx_InjectedConfigChannel:00000000000001f8 $d
+     /tmp/ccfOJcl9.s:1986   .text.HAL_ADCEx_MultiModeConfigChannel:0000000000000000 $t
+     /tmp/ccfOJcl9.s:1993   .text.HAL_ADCEx_MultiModeConfigChannel:0000000000000000 HAL_ADCEx_MultiModeConfigChannel
+     /tmp/ccfOJcl9.s:2080   .text.HAL_ADCEx_MultiModeConfigChannel:0000000000000054 $d
+
+UNDEFINED SYMBOLS
+HAL_ADC_ErrorCallback
+HAL_ADC_ConvHalfCpltCallback
+HAL_ADC_ConvCpltCallback
+SystemCoreClock
+HAL_GetTick
+HAL_DMA_Start_IT
+HAL_DMA_Abort
diff --git a/build/stm32f7xx_hal_adc_ex.o b/build/stm32f7xx_hal_adc_ex.o
new file mode 100644
index 0000000..c769a92
Binary files /dev/null and b/build/stm32f7xx_hal_adc_ex.o differ
diff --git a/build/stm32f7xx_hal_cortex.d b/build/stm32f7xx_hal_cortex.d
new file mode 100644
index 0000000..a06a763
--- /dev/null
+++ b/build/stm32f7xx_hal_cortex.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_cortex.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_cortex.lst b/build/stm32f7xx_hal_cortex.lst
new file mode 100644
index 0000000..ee4e504
--- /dev/null
+++ b/build/stm32f7xx_hal_cortex.lst
@@ -0,0 +1,5737 @@
+ARM GAS  /tmp/ccs1e2mJ.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_cortex.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits
+  17              		.align	1
+  18              		.global	HAL_NVIC_SetPriorityGrouping
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	HAL_NVIC_SetPriorityGrouping:
+  26              	.LVL0:
+  27              	.LFB141:
+  28              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @file    stm32f7xx_hal_cortex.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief   CORTEX HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *          This file provides firmware functions to manage the following 
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *          functionalities of the CORTEX:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *           + Peripheral Control functions 
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   @verbatim  
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   ==============================================================================
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****                         ##### How to use this driver #####
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   ==============================================================================
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     [..]  
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     *** How to configure Interrupts using CORTEX HAL driver ***
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     ===========================================================
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     [..]     
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     This section provides functions allowing to configure the NVIC interrupts (IRQ).
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     The Cortex-M4 exceptions are managed by CMSIS functions.
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****    
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****         function according to the following table.
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     (#) please refer to programming manual for details in how to configure priority. 
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****       
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****          The pending IRQ priority will be managed only by the sub priority.
+ARM GAS  /tmp/ccs1e2mJ.s 			page 2
+
+
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****    
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****      -@- IRQ priority order (sorted by highest to lowest priority):
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****         (+@) Lowest preemption priority
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****         (+@) Lowest sub priority
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****         (+@) Lowest hardware priority (IRQ number)
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****  
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     [..]  
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     *** How to configure Systick using CORTEX HAL driver ***
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     ========================================================
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     [..]
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     Setup SysTick Timer for time base.
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****            
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****        is a CMSIS function that:
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****         (++) Configures the SysTick Reload register with value passed as function parameter.
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****         (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****         (++) Resets the SysTick Counter register.
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****         (++) Enables the SysTick Interrupt.
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****         (++) Starts the SysTick Counter.
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****        inside the stm32f7xx_hal_cortex.h file.
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****    (+) You can change the SysTick IRQ priority by calling the
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****    (+) To adjust the SysTick time base, use the following formula:
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****                             
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****        (++) Reload Value should not exceed 0xFFFFFF
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****    
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   @endverbatim
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   ******************************************************************************
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @attention
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * Copyright (c) 2017 STMicroelectronics.
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * All rights reserved.
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * the root directory of this software component.
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   ******************************************************************************
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** #include "stm32f7xx_hal.h"
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @{
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 3
+
+
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief CORTEX HAL module driver
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @{
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @{
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****  *  @brief    Initialization and Configuration functions 
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****  *
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** @verbatim    
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   ==============================================================================
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ##### Initialization and de-initialization functions #####
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   ==============================================================================
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     [..]
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****       Systick functionalities 
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** @endverbatim
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @{
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Sets the priority grouping field (preemption priority and subpriority)
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         using the required unlock sequence.
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  PriorityGroup The priority grouping bits length. 
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         This parameter can be one of the following values:
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                                    4 bits for subpriority
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                                    3 bits for subpriority
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                                    2 bits for subpriority
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                                    1 bits for subpriority
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                                    0 bits for subpriority
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         The pending IRQ priority will be managed only by the subpriority. 
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+  29              		.loc 1 143 1 view -0
+ARM GAS  /tmp/ccs1e2mJ.s 			page 4
+
+
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+  34              		.loc 1 145 3 view .LVU1
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   NVIC_SetPriorityGrouping(PriorityGroup);
+  35              		.loc 1 148 3 view .LVU2
+  36              	.LBB38:
+  37              	.LBI38:
+  38              		.file 2 "Drivers/CMSIS/Include/core_cm7.h"
+   1:Drivers/CMSIS/Include/core_cm7.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/core_cm7.h ****  * @file     core_cm7.h
+   3:Drivers/CMSIS/Include/core_cm7.h ****  * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+   4:Drivers/CMSIS/Include/core_cm7.h ****  * @version  V5.0.8
+   5:Drivers/CMSIS/Include/core_cm7.h ****  * @date     04. June 2018
+   6:Drivers/CMSIS/Include/core_cm7.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/core_cm7.h **** /*
+   8:Drivers/CMSIS/Include/core_cm7.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/core_cm7.h ****  *
+  10:Drivers/CMSIS/Include/core_cm7.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/core_cm7.h ****  *
+  12:Drivers/CMSIS/Include/core_cm7.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/core_cm7.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/core_cm7.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/core_cm7.h ****  *
+  16:Drivers/CMSIS/Include/core_cm7.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/core_cm7.h ****  *
+  18:Drivers/CMSIS/Include/core_cm7.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/core_cm7.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/core_cm7.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/core_cm7.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/core_cm7.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/core_cm7.h ****  */
+  24:Drivers/CMSIS/Include/core_cm7.h **** 
+  25:Drivers/CMSIS/Include/core_cm7.h **** #if   defined ( __ICCARM__ )
+  26:Drivers/CMSIS/Include/core_cm7.h ****   #pragma system_include         /* treat file as system include file for MISRA check */
+  27:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__clang__)
+  28:Drivers/CMSIS/Include/core_cm7.h ****   #pragma clang system_header   /* treat file as system include file */
+  29:Drivers/CMSIS/Include/core_cm7.h **** #endif
+  30:Drivers/CMSIS/Include/core_cm7.h **** 
+  31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC
+  32:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_GENERIC
+  33:Drivers/CMSIS/Include/core_cm7.h **** 
+  34:Drivers/CMSIS/Include/core_cm7.h **** #include 
+  35:Drivers/CMSIS/Include/core_cm7.h **** 
+  36:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
+  37:Drivers/CMSIS/Include/core_cm7.h ****  extern "C" {
+  38:Drivers/CMSIS/Include/core_cm7.h **** #endif
+  39:Drivers/CMSIS/Include/core_cm7.h **** 
+  40:Drivers/CMSIS/Include/core_cm7.h **** /**
+  41:Drivers/CMSIS/Include/core_cm7.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  42:Drivers/CMSIS/Include/core_cm7.h ****   CMSIS violates the following MISRA-C:2004 rules:
+  43:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 5
+
+
+  44:Drivers/CMSIS/Include/core_cm7.h ****    \li Required Rule 8.5, object/function definition in header file.

+  45:Drivers/CMSIS/Include/core_cm7.h ****      Function definitions in header files are used to allow 'inlining'.
+  46:Drivers/CMSIS/Include/core_cm7.h **** 
+  47:Drivers/CMSIS/Include/core_cm7.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+  48:Drivers/CMSIS/Include/core_cm7.h ****      Unions are used for effective representation of core registers.
+  49:Drivers/CMSIS/Include/core_cm7.h **** 
+  50:Drivers/CMSIS/Include/core_cm7.h ****    \li Advisory Rule 19.7, Function-like macro defined.

+  51:Drivers/CMSIS/Include/core_cm7.h ****      Function-like macros are used to allow more efficient code.
+  52:Drivers/CMSIS/Include/core_cm7.h ****  */
+  53:Drivers/CMSIS/Include/core_cm7.h **** 
+  54:Drivers/CMSIS/Include/core_cm7.h **** 
+  55:Drivers/CMSIS/Include/core_cm7.h **** /*******************************************************************************
+  56:Drivers/CMSIS/Include/core_cm7.h ****  *                 CMSIS definitions
+  57:Drivers/CMSIS/Include/core_cm7.h ****  ******************************************************************************/
+  58:Drivers/CMSIS/Include/core_cm7.h **** /**
+  59:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup Cortex_M7
+  60:Drivers/CMSIS/Include/core_cm7.h ****   @{
+  61:Drivers/CMSIS/Include/core_cm7.h ****  */
+  62:Drivers/CMSIS/Include/core_cm7.h **** 
+  63:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_version.h"
+  64:Drivers/CMSIS/Include/core_cm7.h **** 
+  65:Drivers/CMSIS/Include/core_cm7.h **** /* CMSIS CM7 definitions */
+  66:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:1
+  67:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0
+  68:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+  69:Drivers/CMSIS/Include/core_cm7.h ****                                     __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS
+  70:Drivers/CMSIS/Include/core_cm7.h **** 
+  71:Drivers/CMSIS/Include/core_cm7.h **** #define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+  72:Drivers/CMSIS/Include/core_cm7.h **** 
+  73:Drivers/CMSIS/Include/core_cm7.h **** /** __FPU_USED indicates whether an FPU is used or not.
+  74:Drivers/CMSIS/Include/core_cm7.h ****     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
+  75:Drivers/CMSIS/Include/core_cm7.h **** */
+  76:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM )
+  77:Drivers/CMSIS/Include/core_cm7.h ****   #if defined __TARGET_FPU_VFP
+  78:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+  79:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+  80:Drivers/CMSIS/Include/core_cm7.h ****     #else
+  81:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+  82:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+  83:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+  84:Drivers/CMSIS/Include/core_cm7.h ****   #else
+  85:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+  86:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+  87:Drivers/CMSIS/Include/core_cm7.h **** 
+  88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  89:Drivers/CMSIS/Include/core_cm7.h ****   #if defined __ARM_PCS_VFP
+  90:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+  91:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+  92:Drivers/CMSIS/Include/core_cm7.h ****     #else
+  93:Drivers/CMSIS/Include/core_cm7.h ****       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
+  94:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+  95:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+  96:Drivers/CMSIS/Include/core_cm7.h ****   #else
+  97:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+  98:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+  99:Drivers/CMSIS/Include/core_cm7.h **** 
+ 100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ )
+ARM GAS  /tmp/ccs1e2mJ.s 			page 6
+
+
+ 101:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ 102:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 103:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+ 104:Drivers/CMSIS/Include/core_cm7.h ****     #else
+ 105:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 106:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+ 107:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+ 108:Drivers/CMSIS/Include/core_cm7.h ****   #else
+ 109:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+ 110:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 111:Drivers/CMSIS/Include/core_cm7.h **** 
+ 112:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __ICCARM__ )
+ 113:Drivers/CMSIS/Include/core_cm7.h ****   #if defined __ARMVFP__
+ 114:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 115:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+ 116:Drivers/CMSIS/Include/core_cm7.h ****     #else
+ 117:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 118:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+ 119:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+ 120:Drivers/CMSIS/Include/core_cm7.h ****   #else
+ 121:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+ 122:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 123:Drivers/CMSIS/Include/core_cm7.h **** 
+ 124:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TI_ARM__ )
+ 125:Drivers/CMSIS/Include/core_cm7.h ****   #if defined __TI_VFP_SUPPORT__
+ 126:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 127:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+ 128:Drivers/CMSIS/Include/core_cm7.h ****     #else
+ 129:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 130:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+ 131:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+ 132:Drivers/CMSIS/Include/core_cm7.h ****   #else
+ 133:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+ 134:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 135:Drivers/CMSIS/Include/core_cm7.h **** 
+ 136:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TASKING__ )
+ 137:Drivers/CMSIS/Include/core_cm7.h ****   #if defined __FPU_VFP__
+ 138:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 139:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+ 140:Drivers/CMSIS/Include/core_cm7.h ****     #else
+ 141:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 142:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+ 143:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+ 144:Drivers/CMSIS/Include/core_cm7.h ****   #else
+ 145:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+ 146:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 147:Drivers/CMSIS/Include/core_cm7.h **** 
+ 148:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __CSMC__ )
+ 149:Drivers/CMSIS/Include/core_cm7.h ****   #if ( __CSMC__ & 0x400U)
+ 150:Drivers/CMSIS/Include/core_cm7.h ****     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ 151:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       1U
+ 152:Drivers/CMSIS/Include/core_cm7.h ****     #else
+ 153:Drivers/CMSIS/Include/core_cm7.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 154:Drivers/CMSIS/Include/core_cm7.h ****       #define __FPU_USED       0U
+ 155:Drivers/CMSIS/Include/core_cm7.h ****     #endif
+ 156:Drivers/CMSIS/Include/core_cm7.h ****   #else
+ 157:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_USED         0U
+ARM GAS  /tmp/ccs1e2mJ.s 			page 7
+
+
+ 158:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 159:Drivers/CMSIS/Include/core_cm7.h **** 
+ 160:Drivers/CMSIS/Include/core_cm7.h **** #endif
+ 161:Drivers/CMSIS/Include/core_cm7.h **** 
+ 162:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+ 163:Drivers/CMSIS/Include/core_cm7.h **** 
+ 164:Drivers/CMSIS/Include/core_cm7.h **** 
+ 165:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
+ 166:Drivers/CMSIS/Include/core_cm7.h **** }
+ 167:Drivers/CMSIS/Include/core_cm7.h **** #endif
+ 168:Drivers/CMSIS/Include/core_cm7.h **** 
+ 169:Drivers/CMSIS/Include/core_cm7.h **** #endif /* __CORE_CM7_H_GENERIC */
+ 170:Drivers/CMSIS/Include/core_cm7.h **** 
+ 171:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CMSIS_GENERIC
+ 172:Drivers/CMSIS/Include/core_cm7.h **** 
+ 173:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_DEPENDANT
+ 174:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_DEPENDANT
+ 175:Drivers/CMSIS/Include/core_cm7.h **** 
+ 176:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
+ 177:Drivers/CMSIS/Include/core_cm7.h ****  extern "C" {
+ 178:Drivers/CMSIS/Include/core_cm7.h **** #endif
+ 179:Drivers/CMSIS/Include/core_cm7.h **** 
+ 180:Drivers/CMSIS/Include/core_cm7.h **** /* check device defines and use defaults */
+ 181:Drivers/CMSIS/Include/core_cm7.h **** #if defined __CHECK_DEVICE_DEFINES
+ 182:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __CM7_REV
+ 183:Drivers/CMSIS/Include/core_cm7.h ****     #define __CM7_REV               0x0000U
+ 184:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__CM7_REV not defined in device header file; using default!"
+ 185:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 186:Drivers/CMSIS/Include/core_cm7.h **** 
+ 187:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __FPU_PRESENT
+ 188:Drivers/CMSIS/Include/core_cm7.h ****     #define __FPU_PRESENT             0U
+ 189:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__FPU_PRESENT not defined in device header file; using default!"
+ 190:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 191:Drivers/CMSIS/Include/core_cm7.h **** 
+ 192:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __MPU_PRESENT
+ 193:Drivers/CMSIS/Include/core_cm7.h ****     #define __MPU_PRESENT             0U
+ 194:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__MPU_PRESENT not defined in device header file; using default!"
+ 195:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 196:Drivers/CMSIS/Include/core_cm7.h **** 
+ 197:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __ICACHE_PRESENT
+ 198:Drivers/CMSIS/Include/core_cm7.h ****     #define __ICACHE_PRESENT          0U
+ 199:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ 200:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 201:Drivers/CMSIS/Include/core_cm7.h **** 
+ 202:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __DCACHE_PRESENT
+ 203:Drivers/CMSIS/Include/core_cm7.h ****     #define __DCACHE_PRESENT          0U
+ 204:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ 205:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 206:Drivers/CMSIS/Include/core_cm7.h **** 
+ 207:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __DTCM_PRESENT
+ 208:Drivers/CMSIS/Include/core_cm7.h ****     #define __DTCM_PRESENT            0U
+ 209:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+ 210:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 211:Drivers/CMSIS/Include/core_cm7.h **** 
+ 212:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __NVIC_PRIO_BITS
+ 213:Drivers/CMSIS/Include/core_cm7.h ****     #define __NVIC_PRIO_BITS          3U
+ 214:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ARM GAS  /tmp/ccs1e2mJ.s 			page 8
+
+
+ 215:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 216:Drivers/CMSIS/Include/core_cm7.h **** 
+ 217:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef __Vendor_SysTickConfig
+ 218:Drivers/CMSIS/Include/core_cm7.h ****     #define __Vendor_SysTickConfig    0U
+ 219:Drivers/CMSIS/Include/core_cm7.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ 220:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ 221:Drivers/CMSIS/Include/core_cm7.h **** #endif
+ 222:Drivers/CMSIS/Include/core_cm7.h **** 
+ 223:Drivers/CMSIS/Include/core_cm7.h **** /* IO definitions (access restrictions to peripheral registers) */
+ 224:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 225:Drivers/CMSIS/Include/core_cm7.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
+ 226:Drivers/CMSIS/Include/core_cm7.h **** 
+ 227:Drivers/CMSIS/Include/core_cm7.h ****     IO Type Qualifiers are used
+ 228:Drivers/CMSIS/Include/core_cm7.h ****     \li to specify the access to peripheral variables.
+ 229:Drivers/CMSIS/Include/core_cm7.h ****     \li for automatic generation of peripheral register debug information.
+ 230:Drivers/CMSIS/Include/core_cm7.h **** */
+ 231:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus
+ 232:Drivers/CMSIS/Include/core_cm7.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
+ 233:Drivers/CMSIS/Include/core_cm7.h **** #else
+ 234:Drivers/CMSIS/Include/core_cm7.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
+ 235:Drivers/CMSIS/Include/core_cm7.h **** #endif
+ 236:Drivers/CMSIS/Include/core_cm7.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
+ 237:Drivers/CMSIS/Include/core_cm7.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
+ 238:Drivers/CMSIS/Include/core_cm7.h **** 
+ 239:Drivers/CMSIS/Include/core_cm7.h **** /* following defines should be used for structure members */
+ 240:Drivers/CMSIS/Include/core_cm7.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+ 241:Drivers/CMSIS/Include/core_cm7.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+ 242:Drivers/CMSIS/Include/core_cm7.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+ 243:Drivers/CMSIS/Include/core_cm7.h **** 
+ 244:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group Cortex_M7 */
+ 245:Drivers/CMSIS/Include/core_cm7.h **** 
+ 246:Drivers/CMSIS/Include/core_cm7.h **** 
+ 247:Drivers/CMSIS/Include/core_cm7.h **** 
+ 248:Drivers/CMSIS/Include/core_cm7.h **** /*******************************************************************************
+ 249:Drivers/CMSIS/Include/core_cm7.h ****  *                 Register Abstraction
+ 250:Drivers/CMSIS/Include/core_cm7.h ****   Core Register contain:
+ 251:Drivers/CMSIS/Include/core_cm7.h ****   - Core Register
+ 252:Drivers/CMSIS/Include/core_cm7.h ****   - Core NVIC Register
+ 253:Drivers/CMSIS/Include/core_cm7.h ****   - Core SCB Register
+ 254:Drivers/CMSIS/Include/core_cm7.h ****   - Core SysTick Register
+ 255:Drivers/CMSIS/Include/core_cm7.h ****   - Core Debug Register
+ 256:Drivers/CMSIS/Include/core_cm7.h ****   - Core MPU Register
+ 257:Drivers/CMSIS/Include/core_cm7.h ****   - Core FPU Register
+ 258:Drivers/CMSIS/Include/core_cm7.h ****  ******************************************************************************/
+ 259:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 260:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
+ 261:Drivers/CMSIS/Include/core_cm7.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
+ 262:Drivers/CMSIS/Include/core_cm7.h **** */
+ 263:Drivers/CMSIS/Include/core_cm7.h **** 
+ 264:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 265:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup    CMSIS_core_register
+ 266:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
+ 267:Drivers/CMSIS/Include/core_cm7.h ****   \brief      Core Register type definitions.
+ 268:Drivers/CMSIS/Include/core_cm7.h ****   @{
+ 269:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 270:Drivers/CMSIS/Include/core_cm7.h **** 
+ 271:Drivers/CMSIS/Include/core_cm7.h **** /**
+ARM GAS  /tmp/ccs1e2mJ.s 			page 9
+
+
+ 272:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Union type to access the Application Program Status Register (APSR).
+ 273:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 274:Drivers/CMSIS/Include/core_cm7.h **** typedef union
+ 275:Drivers/CMSIS/Include/core_cm7.h **** {
+ 276:Drivers/CMSIS/Include/core_cm7.h ****   struct
+ 277:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 278:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+ 279:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+ 280:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+ 281:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+ 282:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+ 283:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+ 284:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+ 285:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+ 286:Drivers/CMSIS/Include/core_cm7.h ****   } b;                                   /*!< Structure used for bit  access */
+ 287:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 288:Drivers/CMSIS/Include/core_cm7.h **** } APSR_Type;
+ 289:Drivers/CMSIS/Include/core_cm7.h **** 
+ 290:Drivers/CMSIS/Include/core_cm7.h **** /* APSR Register Definitions */
+ 291:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
+ 292:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
+ 293:Drivers/CMSIS/Include/core_cm7.h **** 
+ 294:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
+ 295:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
+ 296:Drivers/CMSIS/Include/core_cm7.h **** 
+ 297:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
+ 298:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
+ 299:Drivers/CMSIS/Include/core_cm7.h **** 
+ 300:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
+ 301:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
+ 302:Drivers/CMSIS/Include/core_cm7.h **** 
+ 303:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Pos                         27U                                            /*!< APSR
+ 304:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR
+ 305:Drivers/CMSIS/Include/core_cm7.h **** 
+ 306:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Pos                        16U                                            /*!< APSR
+ 307:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR
+ 308:Drivers/CMSIS/Include/core_cm7.h **** 
+ 309:Drivers/CMSIS/Include/core_cm7.h **** 
+ 310:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 311:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ 312:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 313:Drivers/CMSIS/Include/core_cm7.h **** typedef union
+ 314:Drivers/CMSIS/Include/core_cm7.h **** {
+ 315:Drivers/CMSIS/Include/core_cm7.h ****   struct
+ 316:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 317:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+ 318:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+ 319:Drivers/CMSIS/Include/core_cm7.h ****   } b;                                   /*!< Structure used for bit  access */
+ 320:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 321:Drivers/CMSIS/Include/core_cm7.h **** } IPSR_Type;
+ 322:Drivers/CMSIS/Include/core_cm7.h **** 
+ 323:Drivers/CMSIS/Include/core_cm7.h **** /* IPSR Register Definitions */
+ 324:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
+ 325:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
+ 326:Drivers/CMSIS/Include/core_cm7.h **** 
+ 327:Drivers/CMSIS/Include/core_cm7.h **** 
+ 328:Drivers/CMSIS/Include/core_cm7.h **** /**
+ARM GAS  /tmp/ccs1e2mJ.s 			page 10
+
+
+ 329:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ 330:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 331:Drivers/CMSIS/Include/core_cm7.h **** typedef union
+ 332:Drivers/CMSIS/Include/core_cm7.h **** {
+ 333:Drivers/CMSIS/Include/core_cm7.h ****   struct
+ 334:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 335:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+ 336:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+ 337:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+ 338:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+ 339:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+ 340:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+ 341:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+ 342:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+ 343:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+ 344:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+ 345:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+ 346:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+ 347:Drivers/CMSIS/Include/core_cm7.h ****   } b;                                   /*!< Structure used for bit  access */
+ 348:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 349:Drivers/CMSIS/Include/core_cm7.h **** } xPSR_Type;
+ 350:Drivers/CMSIS/Include/core_cm7.h **** 
+ 351:Drivers/CMSIS/Include/core_cm7.h **** /* xPSR Register Definitions */
+ 352:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
+ 353:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
+ 354:Drivers/CMSIS/Include/core_cm7.h **** 
+ 355:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
+ 356:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
+ 357:Drivers/CMSIS/Include/core_cm7.h **** 
+ 358:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
+ 359:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
+ 360:Drivers/CMSIS/Include/core_cm7.h **** 
+ 361:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
+ 362:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
+ 363:Drivers/CMSIS/Include/core_cm7.h **** 
+ 364:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Pos                         27U                                            /*!< xPSR
+ 365:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR
+ 366:Drivers/CMSIS/Include/core_cm7.h **** 
+ 367:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR
+ 368:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR
+ 369:Drivers/CMSIS/Include/core_cm7.h **** 
+ 370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
+ 371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
+ 372:Drivers/CMSIS/Include/core_cm7.h **** 
+ 373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos                        16U                                            /*!< xPSR
+ 374:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR
+ 375:Drivers/CMSIS/Include/core_cm7.h **** 
+ 376:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR
+ 377:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR
+ 378:Drivers/CMSIS/Include/core_cm7.h **** 
+ 379:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
+ 380:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
+ 381:Drivers/CMSIS/Include/core_cm7.h **** 
+ 382:Drivers/CMSIS/Include/core_cm7.h **** 
+ 383:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 384:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Union type to access the Control Registers (CONTROL).
+ 385:Drivers/CMSIS/Include/core_cm7.h ****  */
+ARM GAS  /tmp/ccs1e2mJ.s 			page 11
+
+
+ 386:Drivers/CMSIS/Include/core_cm7.h **** typedef union
+ 387:Drivers/CMSIS/Include/core_cm7.h **** {
+ 388:Drivers/CMSIS/Include/core_cm7.h ****   struct
+ 389:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 390:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+ 391:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+ 392:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+ 393:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+ 394:Drivers/CMSIS/Include/core_cm7.h ****   } b;                                   /*!< Structure used for bit  access */
+ 395:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 396:Drivers/CMSIS/Include/core_cm7.h **** } CONTROL_Type;
+ 397:Drivers/CMSIS/Include/core_cm7.h **** 
+ 398:Drivers/CMSIS/Include/core_cm7.h **** /* CONTROL Register Definitions */
+ 399:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Pos                    2U                                            /*!< CONT
+ 400:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONT
+ 401:Drivers/CMSIS/Include/core_cm7.h **** 
+ 402:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
+ 403:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
+ 404:Drivers/CMSIS/Include/core_cm7.h **** 
+ 405:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONT
+ 406:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONT
+ 407:Drivers/CMSIS/Include/core_cm7.h **** 
+ 408:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CORE */
+ 409:Drivers/CMSIS/Include/core_cm7.h **** 
+ 410:Drivers/CMSIS/Include/core_cm7.h **** 
+ 411:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 412:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup    CMSIS_core_register
+ 413:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+ 414:Drivers/CMSIS/Include/core_cm7.h ****   \brief      Type definitions for the NVIC Registers
+ 415:Drivers/CMSIS/Include/core_cm7.h ****   @{
+ 416:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 417:Drivers/CMSIS/Include/core_cm7.h **** 
+ 418:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 419:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ 420:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 421:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+ 422:Drivers/CMSIS/Include/core_cm7.h **** {
+ 423:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+ 424:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[24U];
+ 425:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
+ 426:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RSERVED1[24U];
+ 427:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
+ 428:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED2[24U];
+ 429:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
+ 430:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED3[24U];
+ 431:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+ 432:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED4[56U];
+ 433:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bi
+ 434:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED5[644U];
+ 435:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Regis
+ 436:Drivers/CMSIS/Include/core_cm7.h **** }  NVIC_Type;
+ 437:Drivers/CMSIS/Include/core_cm7.h **** 
+ 438:Drivers/CMSIS/Include/core_cm7.h **** /* Software Triggered Interrupt Register Definitions */
+ 439:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: I
+ 440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: I
+ 441:Drivers/CMSIS/Include/core_cm7.h **** 
+ 442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */
+ARM GAS  /tmp/ccs1e2mJ.s 			page 12
+
+
+ 443:Drivers/CMSIS/Include/core_cm7.h **** 
+ 444:Drivers/CMSIS/Include/core_cm7.h **** 
+ 445:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 446:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+ 447:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
+ 448:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the System Control Block Registers
+ 449:Drivers/CMSIS/Include/core_cm7.h ****   @{
+ 450:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 451:Drivers/CMSIS/Include/core_cm7.h **** 
+ 452:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 453:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the System Control Block (SCB).
+ 454:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 455:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+ 456:Drivers/CMSIS/Include/core_cm7.h **** {
+ 457:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+ 458:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
+ 459:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+ 460:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
+ 461:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+ 462:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
+ 463:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registe
+ 464:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
+ 465:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Regist
+ 466:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+ 467:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+ 468:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register
+ 469:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+ 470:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register 
+ 471:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+ 472:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+ 473:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+ 474:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+ 475:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Regis
+ 476:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[1U];
+ 477:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+ 478:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+ 479:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+ 480:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+ 481:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Regis
+ 482:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED3[93U];
+ 483:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Reg
+ 484:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED4[15U];
+ 485:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0
+ 486:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1
+ 487:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2
+ 488:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED5[1U];
+ 489:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+ 490:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED6[1U];
+ 491:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU
+ 492:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC
+ 493:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+ 494:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+ 495:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+ 496:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+ 497:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by 
+ 498:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by 
+ 499:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED7[6U];
+ARM GAS  /tmp/ccs1e2mJ.s 			page 13
+
+
+ 500:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memo
+ 501:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Cont
+ 502:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+ 503:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+ 504:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+ 505:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED8[1U];
+ 506:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Regis
+ 507:Drivers/CMSIS/Include/core_cm7.h **** } SCB_Type;
+ 508:Drivers/CMSIS/Include/core_cm7.h **** 
+ 509:Drivers/CMSIS/Include/core_cm7.h **** /* SCB CPUID Register Definitions */
+ 510:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
+ 511:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
+ 512:Drivers/CMSIS/Include/core_cm7.h **** 
+ 513:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
+ 514:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
+ 515:Drivers/CMSIS/Include/core_cm7.h **** 
+ 516:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
+ 517:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
+ 518:Drivers/CMSIS/Include/core_cm7.h **** 
+ 519:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
+ 520:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
+ 521:Drivers/CMSIS/Include/core_cm7.h **** 
+ 522:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
+ 523:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
+ 524:Drivers/CMSIS/Include/core_cm7.h **** 
+ 525:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Interrupt Control State Register Definitions */
+ 526:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
+ 527:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
+ 528:Drivers/CMSIS/Include/core_cm7.h **** 
+ 529:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
+ 530:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
+ 531:Drivers/CMSIS/Include/core_cm7.h **** 
+ 532:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
+ 533:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
+ 534:Drivers/CMSIS/Include/core_cm7.h **** 
+ 535:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
+ 536:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
+ 537:Drivers/CMSIS/Include/core_cm7.h **** 
+ 538:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
+ 539:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
+ 540:Drivers/CMSIS/Include/core_cm7.h **** 
+ 541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
+ 542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
+ 543:Drivers/CMSIS/Include/core_cm7.h **** 
+ 544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
+ 545:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
+ 546:Drivers/CMSIS/Include/core_cm7.h **** 
+ 547:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
+ 548:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
+ 549:Drivers/CMSIS/Include/core_cm7.h **** 
+ 550:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB 
+ 551:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB 
+ 552:Drivers/CMSIS/Include/core_cm7.h **** 
+ 553:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
+ 554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
+ 555:Drivers/CMSIS/Include/core_cm7.h **** 
+ 556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */
+ARM GAS  /tmp/ccs1e2mJ.s 			page 14
+
+
+ 557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB 
+ 558:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB 
+ 559:Drivers/CMSIS/Include/core_cm7.h **** 
+ 560:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
+ 561:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
+ 562:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
+ 563:Drivers/CMSIS/Include/core_cm7.h **** 
+ 564:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
+ 565:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
+ 566:Drivers/CMSIS/Include/core_cm7.h **** 
+ 567:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
+ 568:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
+ 569:Drivers/CMSIS/Include/core_cm7.h **** 
+ 570:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB 
+ 571:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB 
+ 572:Drivers/CMSIS/Include/core_cm7.h **** 
+ 573:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
+ 574:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
+ 575:Drivers/CMSIS/Include/core_cm7.h **** 
+ 576:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
+ 577:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
+ 578:Drivers/CMSIS/Include/core_cm7.h **** 
+ 579:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB 
+ 580:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB 
+ 581:Drivers/CMSIS/Include/core_cm7.h **** 
+ 582:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Control Register Definitions */
+ 583:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
+ 584:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
+ 585:Drivers/CMSIS/Include/core_cm7.h **** 
+ 586:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
+ 587:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
+ 588:Drivers/CMSIS/Include/core_cm7.h **** 
+ 589:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
+ 590:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
+ 591:Drivers/CMSIS/Include/core_cm7.h **** 
+ 592:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configuration Control Register Definitions */
+ 593:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Pos                      18U                                           /*!< SCB 
+ 594:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB 
+ 595:Drivers/CMSIS/Include/core_cm7.h **** 
+ 596:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Pos                      17U                                           /*!< SCB 
+ 597:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB 
+ 598:Drivers/CMSIS/Include/core_cm7.h **** 
+ 599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos                      16U                                           /*!< SCB 
+ 600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB 
+ 601:Drivers/CMSIS/Include/core_cm7.h **** 
+ 602:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
+ 603:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
+ 604:Drivers/CMSIS/Include/core_cm7.h **** 
+ 605:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB 
+ 606:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB 
+ 607:Drivers/CMSIS/Include/core_cm7.h **** 
+ 608:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB 
+ 609:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB 
+ 610:Drivers/CMSIS/Include/core_cm7.h **** 
+ 611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
+ 612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
+ 613:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 15
+
+
+ 614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB 
+ 615:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB 
+ 616:Drivers/CMSIS/Include/core_cm7.h **** 
+ 617:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB 
+ 618:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB 
+ 619:Drivers/CMSIS/Include/core_cm7.h **** 
+ 620:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Handler Control and State Register Definitions */
+ 621:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB 
+ 622:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB 
+ 623:Drivers/CMSIS/Include/core_cm7.h **** 
+ 624:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB 
+ 625:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB 
+ 626:Drivers/CMSIS/Include/core_cm7.h **** 
+ 627:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB 
+ 628:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB 
+ 629:Drivers/CMSIS/Include/core_cm7.h **** 
+ 630:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
+ 631:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
+ 632:Drivers/CMSIS/Include/core_cm7.h **** 
+ 633:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB 
+ 634:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB 
+ 635:Drivers/CMSIS/Include/core_cm7.h **** 
+ 636:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB 
+ 637:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB 
+ 638:Drivers/CMSIS/Include/core_cm7.h **** 
+ 639:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB 
+ 640:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB 
+ 641:Drivers/CMSIS/Include/core_cm7.h **** 
+ 642:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB 
+ 643:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB 
+ 644:Drivers/CMSIS/Include/core_cm7.h **** 
+ 645:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB 
+ 646:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB 
+ 647:Drivers/CMSIS/Include/core_cm7.h **** 
+ 648:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB 
+ 649:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB 
+ 650:Drivers/CMSIS/Include/core_cm7.h **** 
+ 651:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB 
+ 652:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB 
+ 653:Drivers/CMSIS/Include/core_cm7.h **** 
+ 654:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB 
+ 655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB 
+ 656:Drivers/CMSIS/Include/core_cm7.h **** 
+ 657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB 
+ 658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB 
+ 659:Drivers/CMSIS/Include/core_cm7.h **** 
+ 660:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB 
+ 661:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB 
+ 662:Drivers/CMSIS/Include/core_cm7.h **** 
+ 663:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configurable Fault Status Register Definitions */
+ 664:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB 
+ 665:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB 
+ 666:Drivers/CMSIS/Include/core_cm7.h **** 
+ 667:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB 
+ 668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB 
+ 669:Drivers/CMSIS/Include/core_cm7.h **** 
+ 670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 16
+
+
+ 671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB 
+ 672:Drivers/CMSIS/Include/core_cm7.h **** 
+ 673:Drivers/CMSIS/Include/core_cm7.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+ 674:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB 
+ 675:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB 
+ 676:Drivers/CMSIS/Include/core_cm7.h **** 
+ 677:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB 
+ 678:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB 
+ 679:Drivers/CMSIS/Include/core_cm7.h **** 
+ 680:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB 
+ 681:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB 
+ 682:Drivers/CMSIS/Include/core_cm7.h **** 
+ 683:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB 
+ 684:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB 
+ 685:Drivers/CMSIS/Include/core_cm7.h **** 
+ 686:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB 
+ 687:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB 
+ 688:Drivers/CMSIS/Include/core_cm7.h **** 
+ 689:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB 
+ 690:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB 
+ 691:Drivers/CMSIS/Include/core_cm7.h **** 
+ 692:Drivers/CMSIS/Include/core_cm7.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+ 693:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB 
+ 694:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB 
+ 695:Drivers/CMSIS/Include/core_cm7.h **** 
+ 696:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB 
+ 697:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB 
+ 698:Drivers/CMSIS/Include/core_cm7.h **** 
+ 699:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB 
+ 700:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB 
+ 701:Drivers/CMSIS/Include/core_cm7.h **** 
+ 702:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB 
+ 703:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB 
+ 704:Drivers/CMSIS/Include/core_cm7.h **** 
+ 705:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB 
+ 706:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB 
+ 707:Drivers/CMSIS/Include/core_cm7.h **** 
+ 708:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB 
+ 709:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB 
+ 710:Drivers/CMSIS/Include/core_cm7.h **** 
+ 711:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB 
+ 712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB 
+ 713:Drivers/CMSIS/Include/core_cm7.h **** 
+ 714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+ 715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB 
+ 716:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB 
+ 717:Drivers/CMSIS/Include/core_cm7.h **** 
+ 718:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB 
+ 719:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB 
+ 720:Drivers/CMSIS/Include/core_cm7.h **** 
+ 721:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB 
+ 722:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB 
+ 723:Drivers/CMSIS/Include/core_cm7.h **** 
+ 724:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB 
+ 725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB 
+ 726:Drivers/CMSIS/Include/core_cm7.h **** 
+ 727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 17
+
+
+ 728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB 
+ 729:Drivers/CMSIS/Include/core_cm7.h **** 
+ 730:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB 
+ 731:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB 
+ 732:Drivers/CMSIS/Include/core_cm7.h **** 
+ 733:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Hard Fault Status Register Definitions */
+ 734:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB 
+ 735:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB 
+ 736:Drivers/CMSIS/Include/core_cm7.h **** 
+ 737:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB 
+ 738:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB 
+ 739:Drivers/CMSIS/Include/core_cm7.h **** 
+ 740:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB 
+ 741:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB 
+ 742:Drivers/CMSIS/Include/core_cm7.h **** 
+ 743:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Debug Fault Status Register Definitions */
+ 744:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB 
+ 745:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB 
+ 746:Drivers/CMSIS/Include/core_cm7.h **** 
+ 747:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB 
+ 748:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB 
+ 749:Drivers/CMSIS/Include/core_cm7.h **** 
+ 750:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB 
+ 751:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB 
+ 752:Drivers/CMSIS/Include/core_cm7.h **** 
+ 753:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB 
+ 754:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB 
+ 755:Drivers/CMSIS/Include/core_cm7.h **** 
+ 756:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB 
+ 757:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB 
+ 758:Drivers/CMSIS/Include/core_cm7.h **** 
+ 759:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Level ID Register Definitions */
+ 760:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB 
+ 761:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB 
+ 762:Drivers/CMSIS/Include/core_cm7.h **** 
+ 763:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB 
+ 764:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB 
+ 765:Drivers/CMSIS/Include/core_cm7.h **** 
+ 766:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Type Register Definitions */
+ 767:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB 
+ 768:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB 
+ 769:Drivers/CMSIS/Include/core_cm7.h **** 
+ 770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB 
+ 771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB 
+ 772:Drivers/CMSIS/Include/core_cm7.h **** 
+ 773:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB 
+ 774:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB 
+ 775:Drivers/CMSIS/Include/core_cm7.h **** 
+ 776:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB 
+ 777:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB 
+ 778:Drivers/CMSIS/Include/core_cm7.h **** 
+ 779:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB 
+ 780:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB 
+ 781:Drivers/CMSIS/Include/core_cm7.h **** 
+ 782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */
+ 783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB 
+ 784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 18
+
+
+ 785:Drivers/CMSIS/Include/core_cm7.h **** 
+ 786:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB 
+ 787:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB 
+ 788:Drivers/CMSIS/Include/core_cm7.h **** 
+ 789:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB 
+ 790:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB 
+ 791:Drivers/CMSIS/Include/core_cm7.h **** 
+ 792:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB 
+ 793:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB 
+ 794:Drivers/CMSIS/Include/core_cm7.h **** 
+ 795:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB 
+ 796:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB 
+ 797:Drivers/CMSIS/Include/core_cm7.h **** 
+ 798:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB 
+ 799:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB 
+ 800:Drivers/CMSIS/Include/core_cm7.h **** 
+ 801:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB 
+ 802:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB 
+ 803:Drivers/CMSIS/Include/core_cm7.h **** 
+ 804:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size Selection Register Definitions */
+ 805:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB 
+ 806:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB 
+ 807:Drivers/CMSIS/Include/core_cm7.h **** 
+ 808:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB 
+ 809:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB 
+ 810:Drivers/CMSIS/Include/core_cm7.h **** 
+ 811:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Software Triggered Interrupt Register Definitions */
+ 812:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB 
+ 813:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB 
+ 814:Drivers/CMSIS/Include/core_cm7.h **** 
+ 815:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Invalidate by Set-way Register Definitions */
+ 816:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB 
+ 817:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB 
+ 818:Drivers/CMSIS/Include/core_cm7.h **** 
+ 819:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB 
+ 820:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB 
+ 821:Drivers/CMSIS/Include/core_cm7.h **** 
+ 822:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean by Set-way Register Definitions */
+ 823:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB 
+ 824:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB 
+ 825:Drivers/CMSIS/Include/core_cm7.h **** 
+ 826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB 
+ 827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB 
+ 828:Drivers/CMSIS/Include/core_cm7.h **** 
+ 829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+ 830:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB 
+ 831:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB 
+ 832:Drivers/CMSIS/Include/core_cm7.h **** 
+ 833:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB 
+ 834:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB 
+ 835:Drivers/CMSIS/Include/core_cm7.h **** 
+ 836:Drivers/CMSIS/Include/core_cm7.h **** /* Instruction Tightly-Coupled Memory Control Register Definitions */
+ 837:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB 
+ 838:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB 
+ 839:Drivers/CMSIS/Include/core_cm7.h **** 
+ 840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB 
+ 841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 19
+
+
+ 842:Drivers/CMSIS/Include/core_cm7.h **** 
+ 843:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB 
+ 844:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB 
+ 845:Drivers/CMSIS/Include/core_cm7.h **** 
+ 846:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB 
+ 847:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB 
+ 848:Drivers/CMSIS/Include/core_cm7.h **** 
+ 849:Drivers/CMSIS/Include/core_cm7.h **** /* Data Tightly-Coupled Memory Control Register Definitions */
+ 850:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB 
+ 851:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB 
+ 852:Drivers/CMSIS/Include/core_cm7.h **** 
+ 853:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB 
+ 854:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB
+ 855:Drivers/CMSIS/Include/core_cm7.h **** 
+ 856:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB 
+ 857:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB 
+ 858:Drivers/CMSIS/Include/core_cm7.h **** 
+ 859:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB 
+ 860:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB 
+ 861:Drivers/CMSIS/Include/core_cm7.h **** 
+ 862:Drivers/CMSIS/Include/core_cm7.h **** /* AHBP Control Register Definitions */
+ 863:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB 
+ 864:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB 
+ 865:Drivers/CMSIS/Include/core_cm7.h **** 
+ 866:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB 
+ 867:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB 
+ 868:Drivers/CMSIS/Include/core_cm7.h **** 
+ 869:Drivers/CMSIS/Include/core_cm7.h **** /* L1 Cache Control Register Definitions */
+ 870:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB 
+ 871:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB 
+ 872:Drivers/CMSIS/Include/core_cm7.h **** 
+ 873:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB 
+ 874:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB 
+ 875:Drivers/CMSIS/Include/core_cm7.h **** 
+ 876:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB 
+ 877:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB 
+ 878:Drivers/CMSIS/Include/core_cm7.h **** 
+ 879:Drivers/CMSIS/Include/core_cm7.h **** /* AHBS Control Register Definitions */
+ 880:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB 
+ 881:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB 
+ 882:Drivers/CMSIS/Include/core_cm7.h **** 
+ 883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB 
+ 884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB 
+ 885:Drivers/CMSIS/Include/core_cm7.h **** 
+ 886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB 
+ 887:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB 
+ 888:Drivers/CMSIS/Include/core_cm7.h **** 
+ 889:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Bus Fault Status Register Definitions */
+ 890:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB 
+ 891:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB 
+ 892:Drivers/CMSIS/Include/core_cm7.h **** 
+ 893:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB 
+ 894:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB 
+ 895:Drivers/CMSIS/Include/core_cm7.h **** 
+ 896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB 
+ 897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB 
+ 898:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 20
+
+
+ 899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB 
+ 900:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB 
+ 901:Drivers/CMSIS/Include/core_cm7.h **** 
+ 902:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB 
+ 903:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB 
+ 904:Drivers/CMSIS/Include/core_cm7.h **** 
+ 905:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB 
+ 906:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB 
+ 907:Drivers/CMSIS/Include/core_cm7.h **** 
+ 908:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCB */
+ 909:Drivers/CMSIS/Include/core_cm7.h **** 
+ 910:Drivers/CMSIS/Include/core_cm7.h **** 
+ 911:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 912:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+ 913:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ 914:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the System Control and ID Register not in the SCB
+ 915:Drivers/CMSIS/Include/core_cm7.h ****   @{
+ 916:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 917:Drivers/CMSIS/Include/core_cm7.h **** 
+ 918:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 919:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the System Control and ID Register not in the SCB.
+ 920:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 921:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+ 922:Drivers/CMSIS/Include/core_cm7.h **** {
+ 923:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[1U];
+ 924:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Regist
+ 925:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+ 926:Drivers/CMSIS/Include/core_cm7.h **** } SCnSCB_Type;
+ 927:Drivers/CMSIS/Include/core_cm7.h **** 
+ 928:Drivers/CMSIS/Include/core_cm7.h **** /* Interrupt Controller Type Register Definitions */
+ 929:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: I
+ 930:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: I
+ 931:Drivers/CMSIS/Include/core_cm7.h **** 
+ 932:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Control Register Definitions */
+ 933:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: 
+ 934:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: 
+ 935:Drivers/CMSIS/Include/core_cm7.h **** 
+ 936:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: 
+ 937:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: 
+ 938:Drivers/CMSIS/Include/core_cm7.h **** 
+ 939:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: 
+ 940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: 
+ 941:Drivers/CMSIS/Include/core_cm7.h **** 
+ 942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: 
+ 943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: 
+ 944:Drivers/CMSIS/Include/core_cm7.h **** 
+ 945:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: 
+ 946:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: 
+ 947:Drivers/CMSIS/Include/core_cm7.h **** 
+ 948:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCnotSCB */
+ 949:Drivers/CMSIS/Include/core_cm7.h **** 
+ 950:Drivers/CMSIS/Include/core_cm7.h **** 
+ 951:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 952:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+ 953:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+ 954:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the System Timer Registers.
+ 955:Drivers/CMSIS/Include/core_cm7.h ****   @{
+ARM GAS  /tmp/ccs1e2mJ.s 			page 21
+
+
+ 956:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 957:Drivers/CMSIS/Include/core_cm7.h **** 
+ 958:Drivers/CMSIS/Include/core_cm7.h **** /**
+ 959:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the System Timer (SysTick).
+ 960:Drivers/CMSIS/Include/core_cm7.h ****  */
+ 961:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+ 962:Drivers/CMSIS/Include/core_cm7.h **** {
+ 963:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
+ 964:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+ 965:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
+ 966:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+ 967:Drivers/CMSIS/Include/core_cm7.h **** } SysTick_Type;
+ 968:Drivers/CMSIS/Include/core_cm7.h **** 
+ 969:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Control / Status Register Definitions */
+ 970:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
+ 971:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
+ 972:Drivers/CMSIS/Include/core_cm7.h **** 
+ 973:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
+ 974:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
+ 975:Drivers/CMSIS/Include/core_cm7.h **** 
+ 976:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
+ 977:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
+ 978:Drivers/CMSIS/Include/core_cm7.h **** 
+ 979:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
+ 980:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
+ 981:Drivers/CMSIS/Include/core_cm7.h **** 
+ 982:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Reload Register Definitions */
+ 983:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
+ 984:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
+ 985:Drivers/CMSIS/Include/core_cm7.h **** 
+ 986:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Current Register Definitions */
+ 987:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
+ 988:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
+ 989:Drivers/CMSIS/Include/core_cm7.h **** 
+ 990:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Calibration Register Definitions */
+ 991:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
+ 992:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
+ 993:Drivers/CMSIS/Include/core_cm7.h **** 
+ 994:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
+ 995:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
+ 996:Drivers/CMSIS/Include/core_cm7.h **** 
+ 997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
+ 998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
+ 999:Drivers/CMSIS/Include/core_cm7.h **** 
+1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */
+1001:Drivers/CMSIS/Include/core_cm7.h **** 
+1002:Drivers/CMSIS/Include/core_cm7.h **** 
+1003:Drivers/CMSIS/Include/core_cm7.h **** /**
+1004:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1005:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+1006:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+1007:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1008:Drivers/CMSIS/Include/core_cm7.h ****  */
+1009:Drivers/CMSIS/Include/core_cm7.h **** 
+1010:Drivers/CMSIS/Include/core_cm7.h **** /**
+1011:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+1012:Drivers/CMSIS/Include/core_cm7.h ****  */
+ARM GAS  /tmp/ccs1e2mJ.s 			page 22
+
+
+1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1014:Drivers/CMSIS/Include/core_cm7.h **** {
+1015:Drivers/CMSIS/Include/core_cm7.h ****   __OM  union
+1016:Drivers/CMSIS/Include/core_cm7.h ****   {
+1017:Drivers/CMSIS/Include/core_cm7.h ****     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+1018:Drivers/CMSIS/Include/core_cm7.h ****     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+1019:Drivers/CMSIS/Include/core_cm7.h ****     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+1020:Drivers/CMSIS/Include/core_cm7.h ****   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+1021:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[864U];
+1022:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+1023:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED1[15U];
+1024:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+1025:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED2[15U];
+1026:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+1027:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED3[29U];
+1028:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register *
+1029:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+1030:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Reg
+1031:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED4[43U];
+1032:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+1033:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+1034:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED5[6U];
+1035:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Re
+1036:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Re
+1037:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Re
+1038:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Re
+1039:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Re
+1040:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Re
+1041:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Re
+1042:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Re
+1043:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Re
+1044:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Re
+1045:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Re
+1046:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Re
+1047:Drivers/CMSIS/Include/core_cm7.h **** } ITM_Type;
+1048:Drivers/CMSIS/Include/core_cm7.h **** 
+1049:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Privilege Register Definitions */
+1050:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM 
+1051:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM 
+1052:Drivers/CMSIS/Include/core_cm7.h **** 
+1053:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Control Register Definitions */
+1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM 
+1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM 
+1056:Drivers/CMSIS/Include/core_cm7.h **** 
+1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM 
+1058:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM 
+1059:Drivers/CMSIS/Include/core_cm7.h **** 
+1060:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM 
+1061:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM 
+1062:Drivers/CMSIS/Include/core_cm7.h **** 
+1063:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM 
+1064:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM 
+1065:Drivers/CMSIS/Include/core_cm7.h **** 
+1066:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM 
+1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM 
+1068:Drivers/CMSIS/Include/core_cm7.h **** 
+1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 23
+
+
+1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM 
+1071:Drivers/CMSIS/Include/core_cm7.h **** 
+1072:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM 
+1073:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM 
+1074:Drivers/CMSIS/Include/core_cm7.h **** 
+1075:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM 
+1076:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM 
+1077:Drivers/CMSIS/Include/core_cm7.h **** 
+1078:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM 
+1079:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM 
+1080:Drivers/CMSIS/Include/core_cm7.h **** 
+1081:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Write Register Definitions */
+1082:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM 
+1083:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM 
+1084:Drivers/CMSIS/Include/core_cm7.h **** 
+1085:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Read Register Definitions */
+1086:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM 
+1087:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM 
+1088:Drivers/CMSIS/Include/core_cm7.h **** 
+1089:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Mode Control Register Definitions */
+1090:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM 
+1091:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM 
+1092:Drivers/CMSIS/Include/core_cm7.h **** 
+1093:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Lock Status Register Definitions */
+1094:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM 
+1095:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM 
+1096:Drivers/CMSIS/Include/core_cm7.h **** 
+1097:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM 
+1098:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM 
+1099:Drivers/CMSIS/Include/core_cm7.h **** 
+1100:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM 
+1101:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM 
+1102:Drivers/CMSIS/Include/core_cm7.h **** 
+1103:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_ITM */
+1104:Drivers/CMSIS/Include/core_cm7.h **** 
+1105:Drivers/CMSIS/Include/core_cm7.h **** 
+1106:Drivers/CMSIS/Include/core_cm7.h **** /**
+1107:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1108:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+1109:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+1110:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1111:Drivers/CMSIS/Include/core_cm7.h ****  */
+1112:Drivers/CMSIS/Include/core_cm7.h **** 
+1113:Drivers/CMSIS/Include/core_cm7.h **** /**
+1114:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+1115:Drivers/CMSIS/Include/core_cm7.h ****  */
+1116:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1117:Drivers/CMSIS/Include/core_cm7.h **** {
+1118:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+1119:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+1120:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+1121:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Registe
+1122:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+1123:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+1124:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Registe
+1125:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register 
+1126:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+ARM GAS  /tmp/ccs1e2mJ.s 			page 24
+
+
+1127:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+1128:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+1129:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[1U];
+1130:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+1131:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+1132:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+1133:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED1[1U];
+1134:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+1135:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+1136:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+1137:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED2[1U];
+1138:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+1139:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+1140:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+1141:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED3[981U];
+1142:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+1143:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+1144:Drivers/CMSIS/Include/core_cm7.h **** } DWT_Type;
+1145:Drivers/CMSIS/Include/core_cm7.h **** 
+1146:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Control Register Definitions */
+1147:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTR
+1148:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTR
+1149:Drivers/CMSIS/Include/core_cm7.h **** 
+1150:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTR
+1151:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTR
+1152:Drivers/CMSIS/Include/core_cm7.h **** 
+1153:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTR
+1154:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTR
+1155:Drivers/CMSIS/Include/core_cm7.h **** 
+1156:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTR
+1157:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTR
+1158:Drivers/CMSIS/Include/core_cm7.h **** 
+1159:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTR
+1160:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTR
+1161:Drivers/CMSIS/Include/core_cm7.h **** 
+1162:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTR
+1163:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTR
+1164:Drivers/CMSIS/Include/core_cm7.h **** 
+1165:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTR
+1166:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTR
+1167:Drivers/CMSIS/Include/core_cm7.h **** 
+1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTR
+1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTR
+1170:Drivers/CMSIS/Include/core_cm7.h **** 
+1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTR
+1172:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTR
+1173:Drivers/CMSIS/Include/core_cm7.h **** 
+1174:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTR
+1175:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTR
+1176:Drivers/CMSIS/Include/core_cm7.h **** 
+1177:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTR
+1178:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTR
+1179:Drivers/CMSIS/Include/core_cm7.h **** 
+1180:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTR
+1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTR
+1182:Drivers/CMSIS/Include/core_cm7.h **** 
+1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTR
+ARM GAS  /tmp/ccs1e2mJ.s 			page 25
+
+
+1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTR
+1185:Drivers/CMSIS/Include/core_cm7.h **** 
+1186:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTR
+1187:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTR
+1188:Drivers/CMSIS/Include/core_cm7.h **** 
+1189:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTR
+1190:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTR
+1191:Drivers/CMSIS/Include/core_cm7.h **** 
+1192:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTR
+1193:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTR
+1194:Drivers/CMSIS/Include/core_cm7.h **** 
+1195:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTR
+1196:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTR
+1197:Drivers/CMSIS/Include/core_cm7.h **** 
+1198:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTR
+1199:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTR
+1200:Drivers/CMSIS/Include/core_cm7.h **** 
+1201:Drivers/CMSIS/Include/core_cm7.h **** /* DWT CPI Count Register Definitions */
+1202:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPI
+1203:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPI
+1204:Drivers/CMSIS/Include/core_cm7.h **** 
+1205:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Exception Overhead Count Register Definitions */
+1206:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXC
+1207:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXC
+1208:Drivers/CMSIS/Include/core_cm7.h **** 
+1209:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Sleep Count Register Definitions */
+1210:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLE
+1211:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLE
+1212:Drivers/CMSIS/Include/core_cm7.h **** 
+1213:Drivers/CMSIS/Include/core_cm7.h **** /* DWT LSU Count Register Definitions */
+1214:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSU
+1215:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSU
+1216:Drivers/CMSIS/Include/core_cm7.h **** 
+1217:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Folded-instruction Count Register Definitions */
+1218:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOL
+1219:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOL
+1220:Drivers/CMSIS/Include/core_cm7.h **** 
+1221:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Mask Register Definitions */
+1222:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MAS
+1223:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MAS
+1224:Drivers/CMSIS/Include/core_cm7.h **** 
+1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */
+1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUN
+1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUN
+1228:Drivers/CMSIS/Include/core_cm7.h **** 
+1229:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUN
+1230:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUN
+1231:Drivers/CMSIS/Include/core_cm7.h **** 
+1232:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUN
+1233:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUN
+1234:Drivers/CMSIS/Include/core_cm7.h **** 
+1235:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUN
+1236:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUN
+1237:Drivers/CMSIS/Include/core_cm7.h **** 
+1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUN
+1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUN
+1240:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 26
+
+
+1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUN
+1242:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUN
+1243:Drivers/CMSIS/Include/core_cm7.h **** 
+1244:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUN
+1245:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUN
+1246:Drivers/CMSIS/Include/core_cm7.h **** 
+1247:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUN
+1248:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUN
+1249:Drivers/CMSIS/Include/core_cm7.h **** 
+1250:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUN
+1251:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUN
+1252:Drivers/CMSIS/Include/core_cm7.h **** 
+1253:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_DWT */
+1254:Drivers/CMSIS/Include/core_cm7.h **** 
+1255:Drivers/CMSIS/Include/core_cm7.h **** 
+1256:Drivers/CMSIS/Include/core_cm7.h **** /**
+1257:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1258:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+1259:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Trace Port Interface (TPI)
+1260:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1261:Drivers/CMSIS/Include/core_cm7.h ****  */
+1262:Drivers/CMSIS/Include/core_cm7.h **** 
+1263:Drivers/CMSIS/Include/core_cm7.h **** /**
+1264:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Trace Port Interface Register (TPI).
+1265:Drivers/CMSIS/Include/core_cm7.h ****  */
+1266:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1267:Drivers/CMSIS/Include/core_cm7.h **** {
+1268:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Reg
+1269:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Regis
+1270:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[2U];
+1271:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Reg
+1272:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED1[55U];
+1273:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register *
+1274:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED2[131U];
+1275:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Regis
+1276:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Regi
+1277:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counte
+1278:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED3[759U];
+1279:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+1280:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+1281:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+1282:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED4[1U];
+1283:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+1284:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+1285:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+1286:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED5[39U];
+1287:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+1288:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+1289:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED7[8U];
+1290:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+1291:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+1292:Drivers/CMSIS/Include/core_cm7.h **** } TPI_Type;
+1293:Drivers/CMSIS/Include/core_cm7.h **** 
+1294:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
+1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACP
+1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACP
+1297:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 27
+
+
+1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */
+1299:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPP
+1300:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPP
+1301:Drivers/CMSIS/Include/core_cm7.h **** 
+1302:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Status Register Definitions */
+1303:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFS
+1304:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFS
+1305:Drivers/CMSIS/Include/core_cm7.h **** 
+1306:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFS
+1307:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFS
+1308:Drivers/CMSIS/Include/core_cm7.h **** 
+1309:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFS
+1310:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFS
+1311:Drivers/CMSIS/Include/core_cm7.h **** 
+1312:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFS
+1313:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFS
+1314:Drivers/CMSIS/Include/core_cm7.h **** 
+1315:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Control Register Definitions */
+1316:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFC
+1317:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFC
+1318:Drivers/CMSIS/Include/core_cm7.h **** 
+1319:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFC
+1320:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFC
+1321:Drivers/CMSIS/Include/core_cm7.h **** 
+1322:Drivers/CMSIS/Include/core_cm7.h **** /* TPI TRIGGER Register Definitions */
+1323:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRI
+1324:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRI
+1325:Drivers/CMSIS/Include/core_cm7.h **** 
+1326:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
+1327:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
+1328:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIF
+1329:Drivers/CMSIS/Include/core_cm7.h **** 
+1330:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
+1331:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIF
+1332:Drivers/CMSIS/Include/core_cm7.h **** 
+1333:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
+1334:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIF
+1335:Drivers/CMSIS/Include/core_cm7.h **** 
+1336:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
+1337:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIF
+1338:Drivers/CMSIS/Include/core_cm7.h **** 
+1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIF
+1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIF
+1341:Drivers/CMSIS/Include/core_cm7.h **** 
+1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIF
+1343:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIF
+1344:Drivers/CMSIS/Include/core_cm7.h **** 
+1345:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIF
+1346:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIF
+1347:Drivers/CMSIS/Include/core_cm7.h **** 
+1348:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR2 Register Definitions */
+1349:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITA
+1350:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITA
+1351:Drivers/CMSIS/Include/core_cm7.h **** 
+1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITA
+1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITA
+1354:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 28
+
+
+1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
+1356:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
+1357:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIF
+1358:Drivers/CMSIS/Include/core_cm7.h **** 
+1359:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
+1360:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIF
+1361:Drivers/CMSIS/Include/core_cm7.h **** 
+1362:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
+1363:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIF
+1364:Drivers/CMSIS/Include/core_cm7.h **** 
+1365:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
+1366:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIF
+1367:Drivers/CMSIS/Include/core_cm7.h **** 
+1368:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIF
+1369:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIF
+1370:Drivers/CMSIS/Include/core_cm7.h **** 
+1371:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIF
+1372:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIF
+1373:Drivers/CMSIS/Include/core_cm7.h **** 
+1374:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIF
+1375:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIF
+1376:Drivers/CMSIS/Include/core_cm7.h **** 
+1377:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR0 Register Definitions */
+1378:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITA
+1379:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITA
+1380:Drivers/CMSIS/Include/core_cm7.h **** 
+1381:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITA
+1382:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITA
+1383:Drivers/CMSIS/Include/core_cm7.h **** 
+1384:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration Mode Control Register Definitions */
+1385:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITC
+1386:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITC
+1387:Drivers/CMSIS/Include/core_cm7.h **** 
+1388:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVID Register Definitions */
+1389:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEV
+1390:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEV
+1391:Drivers/CMSIS/Include/core_cm7.h **** 
+1392:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEV
+1393:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEV
+1394:Drivers/CMSIS/Include/core_cm7.h **** 
+1395:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEV
+1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEV
+1397:Drivers/CMSIS/Include/core_cm7.h **** 
+1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEV
+1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEV
+1400:Drivers/CMSIS/Include/core_cm7.h **** 
+1401:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEV
+1402:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEV
+1403:Drivers/CMSIS/Include/core_cm7.h **** 
+1404:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEV
+1405:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEV
+1406:Drivers/CMSIS/Include/core_cm7.h **** 
+1407:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVTYPE Register Definitions */
+1408:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEV
+1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEV
+1410:Drivers/CMSIS/Include/core_cm7.h **** 
+1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEV
+ARM GAS  /tmp/ccs1e2mJ.s 			page 29
+
+
+1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEV
+1413:Drivers/CMSIS/Include/core_cm7.h **** 
+1414:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_TPI */
+1415:Drivers/CMSIS/Include/core_cm7.h **** 
+1416:Drivers/CMSIS/Include/core_cm7.h **** 
+1417:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+1418:Drivers/CMSIS/Include/core_cm7.h **** /**
+1419:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1420:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+1421:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Memory Protection Unit (MPU)
+1422:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1423:Drivers/CMSIS/Include/core_cm7.h ****  */
+1424:Drivers/CMSIS/Include/core_cm7.h **** 
+1425:Drivers/CMSIS/Include/core_cm7.h **** /**
+1426:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Memory Protection Unit (MPU).
+1427:Drivers/CMSIS/Include/core_cm7.h ****  */
+1428:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1429:Drivers/CMSIS/Include/core_cm7.h **** {
+1430:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+1431:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+1432:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+1433:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register
+1434:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Re
+1435:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address 
+1436:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and
+1437:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address 
+1438:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and
+1439:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address 
+1440:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and
+1441:Drivers/CMSIS/Include/core_cm7.h **** } MPU_Type;
+1442:Drivers/CMSIS/Include/core_cm7.h **** 
+1443:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_RALIASES                  4U
+1444:Drivers/CMSIS/Include/core_cm7.h **** 
+1445:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Type Register Definitions */
+1446:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU 
+1447:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU 
+1448:Drivers/CMSIS/Include/core_cm7.h **** 
+1449:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU 
+1450:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU 
+1451:Drivers/CMSIS/Include/core_cm7.h **** 
+1452:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU 
+1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU 
+1454:Drivers/CMSIS/Include/core_cm7.h **** 
+1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */
+1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU 
+1457:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU 
+1458:Drivers/CMSIS/Include/core_cm7.h **** 
+1459:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU 
+1460:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU 
+1461:Drivers/CMSIS/Include/core_cm7.h **** 
+1462:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU 
+1463:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU 
+1464:Drivers/CMSIS/Include/core_cm7.h **** 
+1465:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Number Register Definitions */
+1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU 
+1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU 
+1468:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 30
+
+
+1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */
+1470:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU 
+1471:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU 
+1472:Drivers/CMSIS/Include/core_cm7.h **** 
+1473:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU 
+1474:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU 
+1475:Drivers/CMSIS/Include/core_cm7.h **** 
+1476:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU 
+1477:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU 
+1478:Drivers/CMSIS/Include/core_cm7.h **** 
+1479:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Attribute and Size Register Definitions */
+1480:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU 
+1481:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU 
+1482:Drivers/CMSIS/Include/core_cm7.h **** 
+1483:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU 
+1484:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU 
+1485:Drivers/CMSIS/Include/core_cm7.h **** 
+1486:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU 
+1487:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU 
+1488:Drivers/CMSIS/Include/core_cm7.h **** 
+1489:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU 
+1490:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU 
+1491:Drivers/CMSIS/Include/core_cm7.h **** 
+1492:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Pos                     18U                                            /*!< MPU 
+1493:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU 
+1494:Drivers/CMSIS/Include/core_cm7.h **** 
+1495:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Pos                     17U                                            /*!< MPU 
+1496:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU 
+1497:Drivers/CMSIS/Include/core_cm7.h **** 
+1498:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Pos                     16U                                            /*!< MPU 
+1499:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU 
+1500:Drivers/CMSIS/Include/core_cm7.h **** 
+1501:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU 
+1502:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU 
+1503:Drivers/CMSIS/Include/core_cm7.h **** 
+1504:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU 
+1505:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU 
+1506:Drivers/CMSIS/Include/core_cm7.h **** 
+1507:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU 
+1508:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU 
+1509:Drivers/CMSIS/Include/core_cm7.h **** 
+1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */
+1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+1512:Drivers/CMSIS/Include/core_cm7.h **** 
+1513:Drivers/CMSIS/Include/core_cm7.h **** 
+1514:Drivers/CMSIS/Include/core_cm7.h **** /**
+1515:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1516:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+1517:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Floating Point Unit (FPU)
+1518:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1519:Drivers/CMSIS/Include/core_cm7.h ****  */
+1520:Drivers/CMSIS/Include/core_cm7.h **** 
+1521:Drivers/CMSIS/Include/core_cm7.h **** /**
+1522:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Floating Point Unit (FPU).
+1523:Drivers/CMSIS/Include/core_cm7.h ****  */
+1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1525:Drivers/CMSIS/Include/core_cm7.h **** {
+ARM GAS  /tmp/ccs1e2mJ.s 			page 31
+
+
+1526:Drivers/CMSIS/Include/core_cm7.h ****         uint32_t RESERVED0[1U];
+1527:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control R
+1528:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address R
+1529:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Co
+1530:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 
+1531:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 
+1532:Drivers/CMSIS/Include/core_cm7.h ****   __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 
+1533:Drivers/CMSIS/Include/core_cm7.h **** } FPU_Type;
+1534:Drivers/CMSIS/Include/core_cm7.h **** 
+1535:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Control Register Definitions */
+1536:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCC
+1537:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCC
+1538:Drivers/CMSIS/Include/core_cm7.h **** 
+1539:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCC
+1540:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCC
+1541:Drivers/CMSIS/Include/core_cm7.h **** 
+1542:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCC
+1543:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCC
+1544:Drivers/CMSIS/Include/core_cm7.h **** 
+1545:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCC
+1546:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCC
+1547:Drivers/CMSIS/Include/core_cm7.h **** 
+1548:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCC
+1549:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCC
+1550:Drivers/CMSIS/Include/core_cm7.h **** 
+1551:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCC
+1552:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCC
+1553:Drivers/CMSIS/Include/core_cm7.h **** 
+1554:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCC
+1555:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCC
+1556:Drivers/CMSIS/Include/core_cm7.h **** 
+1557:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCC
+1558:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCC
+1559:Drivers/CMSIS/Include/core_cm7.h **** 
+1560:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCC
+1561:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCC
+1562:Drivers/CMSIS/Include/core_cm7.h **** 
+1563:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Address Register Definitions */
+1564:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCA
+1565:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCA
+1566:Drivers/CMSIS/Include/core_cm7.h **** 
+1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */
+1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDS
+1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDS
+1570:Drivers/CMSIS/Include/core_cm7.h **** 
+1571:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDS
+1572:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDS
+1573:Drivers/CMSIS/Include/core_cm7.h **** 
+1574:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDS
+1575:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDS
+1576:Drivers/CMSIS/Include/core_cm7.h **** 
+1577:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDS
+1578:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDS
+1579:Drivers/CMSIS/Include/core_cm7.h **** 
+1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */
+1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR
+1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR
+ARM GAS  /tmp/ccs1e2mJ.s 			page 32
+
+
+1583:Drivers/CMSIS/Include/core_cm7.h **** 
+1584:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR
+1585:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR
+1586:Drivers/CMSIS/Include/core_cm7.h **** 
+1587:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR
+1588:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR
+1589:Drivers/CMSIS/Include/core_cm7.h **** 
+1590:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR
+1591:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR
+1592:Drivers/CMSIS/Include/core_cm7.h **** 
+1593:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR
+1594:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR
+1595:Drivers/CMSIS/Include/core_cm7.h **** 
+1596:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR
+1597:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR
+1598:Drivers/CMSIS/Include/core_cm7.h **** 
+1599:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR
+1600:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR
+1601:Drivers/CMSIS/Include/core_cm7.h **** 
+1602:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR
+1603:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR
+1604:Drivers/CMSIS/Include/core_cm7.h **** 
+1605:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 1 Definitions */
+1606:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR
+1607:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR
+1608:Drivers/CMSIS/Include/core_cm7.h **** 
+1609:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR
+1610:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR
+1611:Drivers/CMSIS/Include/core_cm7.h **** 
+1612:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR
+1613:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR
+1614:Drivers/CMSIS/Include/core_cm7.h **** 
+1615:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR
+1616:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR
+1617:Drivers/CMSIS/Include/core_cm7.h **** 
+1618:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 2 Definitions */
+1619:Drivers/CMSIS/Include/core_cm7.h **** 
+1620:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_FPU */
+1621:Drivers/CMSIS/Include/core_cm7.h **** 
+1622:Drivers/CMSIS/Include/core_cm7.h **** 
+1623:Drivers/CMSIS/Include/core_cm7.h **** /**
+1624:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_core_register
+1625:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+1626:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Type definitions for the Core Debug Registers
+1627:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1628:Drivers/CMSIS/Include/core_cm7.h ****  */
+1629:Drivers/CMSIS/Include/core_cm7.h **** 
+1630:Drivers/CMSIS/Include/core_cm7.h **** /**
+1631:Drivers/CMSIS/Include/core_cm7.h ****   \brief  Structure type to access the Core Debug Register (CoreDebug).
+1632:Drivers/CMSIS/Include/core_cm7.h ****  */
+1633:Drivers/CMSIS/Include/core_cm7.h **** typedef struct
+1634:Drivers/CMSIS/Include/core_cm7.h **** {
+1635:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status
+1636:Drivers/CMSIS/Include/core_cm7.h ****   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Reg
+1637:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Registe
+1638:Drivers/CMSIS/Include/core_cm7.h ****   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Cont
+1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type;
+ARM GAS  /tmp/ccs1e2mJ.s 			page 33
+
+
+1640:Drivers/CMSIS/Include/core_cm7.h **** 
+1641:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Halting Control and Status Register Definitions */
+1642:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< Core
+1643:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< Core
+1644:Drivers/CMSIS/Include/core_cm7.h **** 
+1645:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< Core
+1646:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< Core
+1647:Drivers/CMSIS/Include/core_cm7.h **** 
+1648:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< Core
+1649:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< Core
+1650:Drivers/CMSIS/Include/core_cm7.h **** 
+1651:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< Core
+1652:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< Core
+1653:Drivers/CMSIS/Include/core_cm7.h **** 
+1654:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< Core
+1655:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< Core
+1656:Drivers/CMSIS/Include/core_cm7.h **** 
+1657:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< Core
+1658:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< Core
+1659:Drivers/CMSIS/Include/core_cm7.h **** 
+1660:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< Core
+1661:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< Core
+1662:Drivers/CMSIS/Include/core_cm7.h **** 
+1663:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< Core
+1664:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< Core
+1665:Drivers/CMSIS/Include/core_cm7.h **** 
+1666:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< Core
+1667:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< Core
+1668:Drivers/CMSIS/Include/core_cm7.h **** 
+1669:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< Core
+1670:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< Core
+1671:Drivers/CMSIS/Include/core_cm7.h **** 
+1672:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< Core
+1673:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< Core
+1674:Drivers/CMSIS/Include/core_cm7.h **** 
+1675:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< Core
+1676:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< Core
+1677:Drivers/CMSIS/Include/core_cm7.h **** 
+1678:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Core Register Selector Register Definitions */
+1679:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< Core
+1680:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< Core
+1681:Drivers/CMSIS/Include/core_cm7.h **** 
+1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< Core
+1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< Core
+1684:Drivers/CMSIS/Include/core_cm7.h **** 
+1685:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Exception and Monitor Control Register Definitions */
+1686:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< Core
+1687:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< Core
+1688:Drivers/CMSIS/Include/core_cm7.h **** 
+1689:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< Core
+1690:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< Core
+1691:Drivers/CMSIS/Include/core_cm7.h **** 
+1692:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< Core
+1693:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< Core
+1694:Drivers/CMSIS/Include/core_cm7.h **** 
+1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< Core
+1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< Core
+ARM GAS  /tmp/ccs1e2mJ.s 			page 34
+
+
+1697:Drivers/CMSIS/Include/core_cm7.h **** 
+1698:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< Core
+1699:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< Core
+1700:Drivers/CMSIS/Include/core_cm7.h **** 
+1701:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< Core
+1702:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< Core
+1703:Drivers/CMSIS/Include/core_cm7.h **** 
+1704:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< Core
+1705:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< Core
+1706:Drivers/CMSIS/Include/core_cm7.h **** 
+1707:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< Core
+1708:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< Core
+1709:Drivers/CMSIS/Include/core_cm7.h **** 
+1710:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< Core
+1711:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< Core
+1712:Drivers/CMSIS/Include/core_cm7.h **** 
+1713:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< Core
+1714:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< Core
+1715:Drivers/CMSIS/Include/core_cm7.h **** 
+1716:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< Core
+1717:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< Core
+1718:Drivers/CMSIS/Include/core_cm7.h **** 
+1719:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< Core
+1720:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< Core
+1721:Drivers/CMSIS/Include/core_cm7.h **** 
+1722:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< Core
+1723:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< Core
+1724:Drivers/CMSIS/Include/core_cm7.h **** 
+1725:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CoreDebug */
+1726:Drivers/CMSIS/Include/core_cm7.h **** 
+1727:Drivers/CMSIS/Include/core_cm7.h **** 
+1728:Drivers/CMSIS/Include/core_cm7.h **** /**
+1729:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup    CMSIS_core_register
+1730:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
+1731:Drivers/CMSIS/Include/core_cm7.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+1732:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1733:Drivers/CMSIS/Include/core_cm7.h ****  */
+1734:Drivers/CMSIS/Include/core_cm7.h **** 
+1735:Drivers/CMSIS/Include/core_cm7.h **** /**
+1736:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
+1737:Drivers/CMSIS/Include/core_cm7.h ****   \param[in] field  Name of the register bit field.
+1738:Drivers/CMSIS/Include/core_cm7.h ****   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+1739:Drivers/CMSIS/Include/core_cm7.h ****   \return           Masked and shifted value.
+1740:Drivers/CMSIS/Include/core_cm7.h **** */
+1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+1742:Drivers/CMSIS/Include/core_cm7.h **** 
+1743:Drivers/CMSIS/Include/core_cm7.h **** /**
+1744:Drivers/CMSIS/Include/core_cm7.h ****   \brief     Mask and shift a register value to extract a bit filed value.
+1745:Drivers/CMSIS/Include/core_cm7.h ****   \param[in] field  Name of the register bit field.
+1746:Drivers/CMSIS/Include/core_cm7.h ****   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+1747:Drivers/CMSIS/Include/core_cm7.h ****   \return           Masked and shifted bit field value.
+1748:Drivers/CMSIS/Include/core_cm7.h **** */
+1749:Drivers/CMSIS/Include/core_cm7.h **** #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+1750:Drivers/CMSIS/Include/core_cm7.h **** 
+1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */
+1752:Drivers/CMSIS/Include/core_cm7.h **** 
+1753:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 35
+
+
+1754:Drivers/CMSIS/Include/core_cm7.h **** /**
+1755:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup    CMSIS_core_register
+1756:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup   CMSIS_core_base     Core Definitions
+1757:Drivers/CMSIS/Include/core_cm7.h ****   \brief      Definitions for base addresses, unions, and structures.
+1758:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1759:Drivers/CMSIS/Include/core_cm7.h ****  */
+1760:Drivers/CMSIS/Include/core_cm7.h **** 
+1761:Drivers/CMSIS/Include/core_cm7.h **** /* Memory mapping of Core Hardware */
+1762:Drivers/CMSIS/Include/core_cm7.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
+1763:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+1764:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+1765:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+1766:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address 
+1767:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+1768:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+1769:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
+1770:Drivers/CMSIS/Include/core_cm7.h **** 
+1771:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register 
+1772:Drivers/CMSIS/Include/core_cm7.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
+1773:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
+1774:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
+1775:Drivers/CMSIS/Include/core_cm7.h **** #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct
+1776:Drivers/CMSIS/Include/core_cm7.h **** #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct
+1777:Drivers/CMSIS/Include/core_cm7.h **** #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct
+1778:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration
+1779:Drivers/CMSIS/Include/core_cm7.h **** 
+1780:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+1781:Drivers/CMSIS/Include/core_cm7.h ****   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit *
+1782:Drivers/CMSIS/Include/core_cm7.h ****   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit *
+1783:Drivers/CMSIS/Include/core_cm7.h **** #endif
+1784:Drivers/CMSIS/Include/core_cm7.h **** 
+1785:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+1786:Drivers/CMSIS/Include/core_cm7.h **** #define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+1787:Drivers/CMSIS/Include/core_cm7.h **** 
+1788:Drivers/CMSIS/Include/core_cm7.h **** /*@} */
+1789:Drivers/CMSIS/Include/core_cm7.h **** 
+1790:Drivers/CMSIS/Include/core_cm7.h **** 
+1791:Drivers/CMSIS/Include/core_cm7.h **** 
+1792:Drivers/CMSIS/Include/core_cm7.h **** /*******************************************************************************
+1793:Drivers/CMSIS/Include/core_cm7.h ****  *                Hardware Abstraction Layer
+1794:Drivers/CMSIS/Include/core_cm7.h ****   Core Function Interface contains:
+1795:Drivers/CMSIS/Include/core_cm7.h ****   - Core NVIC Functions
+1796:Drivers/CMSIS/Include/core_cm7.h ****   - Core SysTick Functions
+1797:Drivers/CMSIS/Include/core_cm7.h ****   - Core Debug Functions
+1798:Drivers/CMSIS/Include/core_cm7.h ****   - Core Register Access Functions
+1799:Drivers/CMSIS/Include/core_cm7.h ****  ******************************************************************************/
+1800:Drivers/CMSIS/Include/core_cm7.h **** /**
+1801:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+1802:Drivers/CMSIS/Include/core_cm7.h **** */
+1803:Drivers/CMSIS/Include/core_cm7.h **** 
+1804:Drivers/CMSIS/Include/core_cm7.h **** 
+1805:Drivers/CMSIS/Include/core_cm7.h **** 
+1806:Drivers/CMSIS/Include/core_cm7.h **** /* ##########################   NVIC functions  #################################### */
+1807:Drivers/CMSIS/Include/core_cm7.h **** /**
+1808:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_Core_FunctionInterface
+1809:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+1810:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
+ARM GAS  /tmp/ccs1e2mJ.s 			page 36
+
+
+1811:Drivers/CMSIS/Include/core_cm7.h ****   @{
+1812:Drivers/CMSIS/Include/core_cm7.h ****  */
+1813:Drivers/CMSIS/Include/core_cm7.h **** 
+1814:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_NVIC_VIRTUAL
+1815:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+1816:Drivers/CMSIS/Include/core_cm7.h ****     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+1817:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+1818:Drivers/CMSIS/Include/core_cm7.h ****   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+1819:Drivers/CMSIS/Include/core_cm7.h **** #else
+1820:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+1821:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+1822:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+1823:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+1824:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+1825:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+1826:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+1827:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+1828:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetActive              __NVIC_GetActive
+1829:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_SetPriority            __NVIC_SetPriority
+1830:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetPriority            __NVIC_GetPriority
+1831:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_SystemReset            __NVIC_SystemReset
+1832:Drivers/CMSIS/Include/core_cm7.h **** #endif /* CMSIS_NVIC_VIRTUAL */
+1833:Drivers/CMSIS/Include/core_cm7.h **** 
+1834:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_VECTAB_VIRTUAL
+1835:Drivers/CMSIS/Include/core_cm7.h ****   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+1836:Drivers/CMSIS/Include/core_cm7.h ****     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+1837:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+1838:Drivers/CMSIS/Include/core_cm7.h ****   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+1839:Drivers/CMSIS/Include/core_cm7.h **** #else
+1840:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_SetVector              __NVIC_SetVector
+1841:Drivers/CMSIS/Include/core_cm7.h ****   #define NVIC_GetVector              __NVIC_GetVector
+1842:Drivers/CMSIS/Include/core_cm7.h **** #endif  /* (CMSIS_VECTAB_VIRTUAL) */
+1843:Drivers/CMSIS/Include/core_cm7.h **** 
+1844:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_USER_IRQ_OFFSET          16
+1845:Drivers/CMSIS/Include/core_cm7.h **** 
+1846:Drivers/CMSIS/Include/core_cm7.h **** 
+1847:Drivers/CMSIS/Include/core_cm7.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
+1848:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after ret
+1849:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after retu
+1850:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after retu
+1851:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after ret
+1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after retu
+1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after retu
+1854:Drivers/CMSIS/Include/core_cm7.h **** 
+1855:Drivers/CMSIS/Include/core_cm7.h **** 
+1856:Drivers/CMSIS/Include/core_cm7.h **** /**
+1857:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Set Priority Grouping
+1858:Drivers/CMSIS/Include/core_cm7.h ****   \details Sets the priority grouping field using the required unlock sequence.
+1859:Drivers/CMSIS/Include/core_cm7.h ****            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+1860:Drivers/CMSIS/Include/core_cm7.h ****            Only values from 0..7 are used.
+1861:Drivers/CMSIS/Include/core_cm7.h ****            In case of a conflict between priority grouping and available
+1862:Drivers/CMSIS/Include/core_cm7.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+1863:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      PriorityGroup  Priority grouping field.
+1864:Drivers/CMSIS/Include/core_cm7.h ****  */
+1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+  39              		.loc 2 1865 22 view .LVU3
+  40              	.LBB39:
+ARM GAS  /tmp/ccs1e2mJ.s 			page 37
+
+
+1866:Drivers/CMSIS/Include/core_cm7.h **** {
+1867:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t reg_value;
+  41              		.loc 2 1867 3 view .LVU4
+1868:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
+  42              		.loc 2 1868 3 view .LVU5
+1869:Drivers/CMSIS/Include/core_cm7.h **** 
+1870:Drivers/CMSIS/Include/core_cm7.h ****   reg_value  =  SCB->AIRCR;                                                   /* read old register 
+  43              		.loc 2 1870 3 view .LVU6
+  44              		.loc 2 1870 14 is_stmt 0 view .LVU7
+  45 0000 0649     		ldr	r1, .L2
+  46 0002 CB68     		ldr	r3, [r1, #12]
+  47              	.LVL1:
+1871:Drivers/CMSIS/Include/core_cm7.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
+  48              		.loc 2 1871 3 is_stmt 1 view .LVU8
+  49              		.loc 2 1871 13 is_stmt 0 view .LVU9
+  50 0004 23F4E063 		bic	r3, r3, #1792
+  51              	.LVL2:
+  52              		.loc 2 1871 13 view .LVU10
+  53 0008 1B04     		lsls	r3, r3, #16
+  54 000a 1B0C     		lsrs	r3, r3, #16
+  55              	.LVL3:
+1872:Drivers/CMSIS/Include/core_cm7.h ****   reg_value  =  (reg_value                                   |
+  56              		.loc 2 1872 3 is_stmt 1 view .LVU11
+1873:Drivers/CMSIS/Include/core_cm7.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+1874:Drivers/CMSIS/Include/core_cm7.h ****                 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key a
+  57              		.loc 2 1874 35 is_stmt 0 view .LVU12
+  58 000c 0002     		lsls	r0, r0, #8
+  59              	.LVL4:
+  60              		.loc 2 1874 35 view .LVU13
+  61 000e 00F4E060 		and	r0, r0, #1792
+1873:Drivers/CMSIS/Include/core_cm7.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+  62              		.loc 2 1873 62 view .LVU14
+  63 0012 0343     		orrs	r3, r3, r0
+  64              	.LVL5:
+1872:Drivers/CMSIS/Include/core_cm7.h ****   reg_value  =  (reg_value                                   |
+  65              		.loc 2 1872 14 view .LVU15
+  66 0014 024A     		ldr	r2, .L2+4
+  67 0016 1A43     		orrs	r2, r2, r3
+  68              	.LVL6:
+1875:Drivers/CMSIS/Include/core_cm7.h ****   SCB->AIRCR =  reg_value;
+  69              		.loc 2 1875 3 is_stmt 1 view .LVU16
+  70              		.loc 2 1875 14 is_stmt 0 view .LVU17
+  71 0018 CA60     		str	r2, [r1, #12]
+  72              	.LVL7:
+  73              		.loc 2 1875 14 view .LVU18
+  74              	.LBE39:
+  75              	.LBE38:
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+  76              		.loc 1 149 1 view .LVU19
+  77 001a 7047     		bx	lr
+  78              	.L3:
+  79              		.align	2
+  80              	.L2:
+  81 001c 00ED00E0 		.word	-536810240
+  82 0020 0000FA05 		.word	100270080
+  83              		.cfi_endproc
+  84              	.LFE141:
+ARM GAS  /tmp/ccs1e2mJ.s 			page 38
+
+
+  86              		.section	.text.HAL_NVIC_SetPriority,"ax",%progbits
+  87              		.align	1
+  88              		.global	HAL_NVIC_SetPriority
+  89              		.syntax unified
+  90              		.thumb
+  91              		.thumb_func
+  92              		.fpu fpv5-d16
+  94              	HAL_NVIC_SetPriority:
+  95              	.LVL8:
+  96              	.LFB142:
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Sets the priority of an interrupt.
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  PreemptPriority The preemption priority for the IRQn channel.
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         This parameter can be a value between 0 and 15
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         A lower priority value indicates a higher priority 
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  SubPriority the subpriority level for the IRQ channel.
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         This parameter can be a value between 0 and 15
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         A lower priority value indicates a higher priority.          
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { 
+  97              		.loc 1 165 1 is_stmt 1 view -0
+  98              		.cfi_startproc
+  99              		@ args = 0, pretend = 0, frame = 0
+ 100              		@ frame_needed = 0, uses_anonymous_args = 0
+ 101              		.loc 1 165 1 is_stmt 0 view .LVU21
+ 102 0000 00B5     		push	{lr}
+ 103              	.LCFI0:
+ 104              		.cfi_def_cfa_offset 4
+ 105              		.cfi_offset 14, -4
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   uint32_t prioritygroup = 0x00;
+ 106              		.loc 1 166 3 is_stmt 1 view .LVU22
+ 107              	.LVL9:
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ 108              		.loc 1 169 3 view .LVU23
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+ 109              		.loc 1 170 3 view .LVU24
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   prioritygroup = NVIC_GetPriorityGrouping();
+ 110              		.loc 1 172 3 view .LVU25
+ 111              	.LBB46:
+ 112              	.LBI46:
+1876:Drivers/CMSIS/Include/core_cm7.h **** }
+1877:Drivers/CMSIS/Include/core_cm7.h **** 
+1878:Drivers/CMSIS/Include/core_cm7.h **** 
+1879:Drivers/CMSIS/Include/core_cm7.h **** /**
+1880:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Get Priority Grouping
+1881:Drivers/CMSIS/Include/core_cm7.h ****   \details Reads the priority grouping field from the NVIC Interrupt Controller.
+1882:Drivers/CMSIS/Include/core_cm7.h ****   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+1883:Drivers/CMSIS/Include/core_cm7.h ****  */
+ARM GAS  /tmp/ccs1e2mJ.s 			page 39
+
+
+1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+ 113              		.loc 2 1884 26 view .LVU26
+ 114              	.LBB47:
+1885:Drivers/CMSIS/Include/core_cm7.h **** {
+1886:Drivers/CMSIS/Include/core_cm7.h ****   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+ 115              		.loc 2 1886 3 view .LVU27
+ 116              		.loc 2 1886 26 is_stmt 0 view .LVU28
+ 117 0002 174B     		ldr	r3, .L10
+ 118 0004 DB68     		ldr	r3, [r3, #12]
+ 119              		.loc 2 1886 11 view .LVU29
+ 120 0006 C3F30223 		ubfx	r3, r3, #8, #3
+ 121              	.LVL10:
+ 122              		.loc 2 1886 11 view .LVU30
+ 123              	.LBE47:
+ 124              	.LBE46:
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+ 125              		.loc 1 174 3 is_stmt 1 view .LVU31
+ 126              	.LBB48:
+ 127              	.LBI48:
+1887:Drivers/CMSIS/Include/core_cm7.h **** }
+1888:Drivers/CMSIS/Include/core_cm7.h **** 
+1889:Drivers/CMSIS/Include/core_cm7.h **** 
+1890:Drivers/CMSIS/Include/core_cm7.h **** /**
+1891:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Enable Interrupt
+1892:Drivers/CMSIS/Include/core_cm7.h ****   \details Enables a device specific interrupt in the NVIC interrupt controller.
+1893:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1894:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1895:Drivers/CMSIS/Include/core_cm7.h ****  */
+1896:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+1897:Drivers/CMSIS/Include/core_cm7.h **** {
+1898:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1899:Drivers/CMSIS/Include/core_cm7.h ****   {
+1900:Drivers/CMSIS/Include/core_cm7.h ****     NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+1901:Drivers/CMSIS/Include/core_cm7.h ****   }
+1902:Drivers/CMSIS/Include/core_cm7.h **** }
+1903:Drivers/CMSIS/Include/core_cm7.h **** 
+1904:Drivers/CMSIS/Include/core_cm7.h **** 
+1905:Drivers/CMSIS/Include/core_cm7.h **** /**
+1906:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Get Interrupt Enable status
+1907:Drivers/CMSIS/Include/core_cm7.h ****   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+1908:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1909:Drivers/CMSIS/Include/core_cm7.h ****   \return             0  Interrupt is not enabled.
+1910:Drivers/CMSIS/Include/core_cm7.h ****   \return             1  Interrupt is enabled.
+1911:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1912:Drivers/CMSIS/Include/core_cm7.h ****  */
+1913:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+1914:Drivers/CMSIS/Include/core_cm7.h **** {
+1915:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1916:Drivers/CMSIS/Include/core_cm7.h ****   {
+1917:Drivers/CMSIS/Include/core_cm7.h ****     return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
+1918:Drivers/CMSIS/Include/core_cm7.h ****   }
+1919:Drivers/CMSIS/Include/core_cm7.h ****   else
+1920:Drivers/CMSIS/Include/core_cm7.h ****   {
+1921:Drivers/CMSIS/Include/core_cm7.h ****     return(0U);
+1922:Drivers/CMSIS/Include/core_cm7.h ****   }
+1923:Drivers/CMSIS/Include/core_cm7.h **** }
+ARM GAS  /tmp/ccs1e2mJ.s 			page 40
+
+
+1924:Drivers/CMSIS/Include/core_cm7.h **** 
+1925:Drivers/CMSIS/Include/core_cm7.h **** 
+1926:Drivers/CMSIS/Include/core_cm7.h **** /**
+1927:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Disable Interrupt
+1928:Drivers/CMSIS/Include/core_cm7.h ****   \details Disables a device specific interrupt in the NVIC interrupt controller.
+1929:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1930:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1931:Drivers/CMSIS/Include/core_cm7.h ****  */
+1932:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+1933:Drivers/CMSIS/Include/core_cm7.h **** {
+1934:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1935:Drivers/CMSIS/Include/core_cm7.h ****   {
+1936:Drivers/CMSIS/Include/core_cm7.h ****     NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+1937:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+1938:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+1939:Drivers/CMSIS/Include/core_cm7.h ****   }
+1940:Drivers/CMSIS/Include/core_cm7.h **** }
+1941:Drivers/CMSIS/Include/core_cm7.h **** 
+1942:Drivers/CMSIS/Include/core_cm7.h **** 
+1943:Drivers/CMSIS/Include/core_cm7.h **** /**
+1944:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Get Pending Interrupt
+1945:Drivers/CMSIS/Include/core_cm7.h ****   \details Reads the NVIC pending register and returns the pending bit for the specified device spe
+1946:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1947:Drivers/CMSIS/Include/core_cm7.h ****   \return             0  Interrupt status is not pending.
+1948:Drivers/CMSIS/Include/core_cm7.h ****   \return             1  Interrupt status is pending.
+1949:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1950:Drivers/CMSIS/Include/core_cm7.h ****  */
+1951:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+1952:Drivers/CMSIS/Include/core_cm7.h **** {
+1953:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1954:Drivers/CMSIS/Include/core_cm7.h ****   {
+1955:Drivers/CMSIS/Include/core_cm7.h ****     return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
+1956:Drivers/CMSIS/Include/core_cm7.h ****   }
+1957:Drivers/CMSIS/Include/core_cm7.h ****   else
+1958:Drivers/CMSIS/Include/core_cm7.h ****   {
+1959:Drivers/CMSIS/Include/core_cm7.h ****     return(0U);
+1960:Drivers/CMSIS/Include/core_cm7.h ****   }
+1961:Drivers/CMSIS/Include/core_cm7.h **** }
+1962:Drivers/CMSIS/Include/core_cm7.h **** 
+1963:Drivers/CMSIS/Include/core_cm7.h **** 
+1964:Drivers/CMSIS/Include/core_cm7.h **** /**
+1965:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Set Pending Interrupt
+1966:Drivers/CMSIS/Include/core_cm7.h ****   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+1967:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1968:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1969:Drivers/CMSIS/Include/core_cm7.h ****  */
+1970:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+1971:Drivers/CMSIS/Include/core_cm7.h **** {
+1972:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1973:Drivers/CMSIS/Include/core_cm7.h ****   {
+1974:Drivers/CMSIS/Include/core_cm7.h ****     NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+1975:Drivers/CMSIS/Include/core_cm7.h ****   }
+1976:Drivers/CMSIS/Include/core_cm7.h **** }
+1977:Drivers/CMSIS/Include/core_cm7.h **** 
+1978:Drivers/CMSIS/Include/core_cm7.h **** 
+1979:Drivers/CMSIS/Include/core_cm7.h **** /**
+1980:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Clear Pending Interrupt
+ARM GAS  /tmp/ccs1e2mJ.s 			page 41
+
+
+1981:Drivers/CMSIS/Include/core_cm7.h ****   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+1982:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1983:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+1984:Drivers/CMSIS/Include/core_cm7.h ****  */
+1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+1986:Drivers/CMSIS/Include/core_cm7.h **** {
+1987:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+1988:Drivers/CMSIS/Include/core_cm7.h ****   {
+1989:Drivers/CMSIS/Include/core_cm7.h ****     NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+1990:Drivers/CMSIS/Include/core_cm7.h ****   }
+1991:Drivers/CMSIS/Include/core_cm7.h **** }
+1992:Drivers/CMSIS/Include/core_cm7.h **** 
+1993:Drivers/CMSIS/Include/core_cm7.h **** 
+1994:Drivers/CMSIS/Include/core_cm7.h **** /**
+1995:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Get Active Interrupt
+1996:Drivers/CMSIS/Include/core_cm7.h ****   \details Reads the active register in the NVIC and returns the active bit for the device specific
+1997:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Device specific interrupt number.
+1998:Drivers/CMSIS/Include/core_cm7.h ****   \return             0  Interrupt status is not active.
+1999:Drivers/CMSIS/Include/core_cm7.h ****   \return             1  Interrupt status is active.
+2000:Drivers/CMSIS/Include/core_cm7.h ****   \note    IRQn must not be negative.
+2001:Drivers/CMSIS/Include/core_cm7.h ****  */
+2002:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+2003:Drivers/CMSIS/Include/core_cm7.h **** {
+2004:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+2005:Drivers/CMSIS/Include/core_cm7.h ****   {
+2006:Drivers/CMSIS/Include/core_cm7.h ****     return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
+2007:Drivers/CMSIS/Include/core_cm7.h ****   }
+2008:Drivers/CMSIS/Include/core_cm7.h ****   else
+2009:Drivers/CMSIS/Include/core_cm7.h ****   {
+2010:Drivers/CMSIS/Include/core_cm7.h ****     return(0U);
+2011:Drivers/CMSIS/Include/core_cm7.h ****   }
+2012:Drivers/CMSIS/Include/core_cm7.h **** }
+2013:Drivers/CMSIS/Include/core_cm7.h **** 
+2014:Drivers/CMSIS/Include/core_cm7.h **** 
+2015:Drivers/CMSIS/Include/core_cm7.h **** /**
+2016:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Set Interrupt Priority
+2017:Drivers/CMSIS/Include/core_cm7.h ****   \details Sets the priority of a device specific interrupt or a processor exception.
+2018:Drivers/CMSIS/Include/core_cm7.h ****            The interrupt number can be positive to specify a device specific interrupt,
+2019:Drivers/CMSIS/Include/core_cm7.h ****            or negative to specify a processor exception.
+2020:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]      IRQn  Interrupt number.
+2021:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]  priority  Priority to set.
+2022:Drivers/CMSIS/Include/core_cm7.h ****   \note    The priority cannot be set for every processor exception.
+2023:Drivers/CMSIS/Include/core_cm7.h ****  */
+2024:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+2025:Drivers/CMSIS/Include/core_cm7.h **** {
+2026:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+2027:Drivers/CMSIS/Include/core_cm7.h ****   {
+2028:Drivers/CMSIS/Include/core_cm7.h ****     NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (
+2029:Drivers/CMSIS/Include/core_cm7.h ****   }
+2030:Drivers/CMSIS/Include/core_cm7.h ****   else
+2031:Drivers/CMSIS/Include/core_cm7.h ****   {
+2032:Drivers/CMSIS/Include/core_cm7.h ****     SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (
+2033:Drivers/CMSIS/Include/core_cm7.h ****   }
+2034:Drivers/CMSIS/Include/core_cm7.h **** }
+2035:Drivers/CMSIS/Include/core_cm7.h **** 
+2036:Drivers/CMSIS/Include/core_cm7.h **** 
+2037:Drivers/CMSIS/Include/core_cm7.h **** /**
+ARM GAS  /tmp/ccs1e2mJ.s 			page 42
+
+
+2038:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Get Interrupt Priority
+2039:Drivers/CMSIS/Include/core_cm7.h ****   \details Reads the priority of a device specific interrupt or a processor exception.
+2040:Drivers/CMSIS/Include/core_cm7.h ****            The interrupt number can be positive to specify a device specific interrupt,
+2041:Drivers/CMSIS/Include/core_cm7.h ****            or negative to specify a processor exception.
+2042:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]   IRQn  Interrupt number.
+2043:Drivers/CMSIS/Include/core_cm7.h ****   \return             Interrupt Priority.
+2044:Drivers/CMSIS/Include/core_cm7.h ****                       Value is aligned automatically to the implemented priority bits of the microc
+2045:Drivers/CMSIS/Include/core_cm7.h ****  */
+2046:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+2047:Drivers/CMSIS/Include/core_cm7.h **** {
+2048:Drivers/CMSIS/Include/core_cm7.h **** 
+2049:Drivers/CMSIS/Include/core_cm7.h ****   if ((int32_t)(IRQn) >= 0)
+2050:Drivers/CMSIS/Include/core_cm7.h ****   {
+2051:Drivers/CMSIS/Include/core_cm7.h ****     return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+2052:Drivers/CMSIS/Include/core_cm7.h ****   }
+2053:Drivers/CMSIS/Include/core_cm7.h ****   else
+2054:Drivers/CMSIS/Include/core_cm7.h ****   {
+2055:Drivers/CMSIS/Include/core_cm7.h ****     return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+2056:Drivers/CMSIS/Include/core_cm7.h ****   }
+2057:Drivers/CMSIS/Include/core_cm7.h **** }
+2058:Drivers/CMSIS/Include/core_cm7.h **** 
+2059:Drivers/CMSIS/Include/core_cm7.h **** 
+2060:Drivers/CMSIS/Include/core_cm7.h **** /**
+2061:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Encode Priority
+2062:Drivers/CMSIS/Include/core_cm7.h ****   \details Encodes the priority for an interrupt with the given priority group,
+2063:Drivers/CMSIS/Include/core_cm7.h ****            preemptive priority value, and subpriority value.
+2064:Drivers/CMSIS/Include/core_cm7.h ****            In case of a conflict between priority grouping and available
+2065:Drivers/CMSIS/Include/core_cm7.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+2066:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]     PriorityGroup  Used priority group.
+2067:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+2068:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]       SubPriority  Subpriority value (starting from 0).
+2069:Drivers/CMSIS/Include/core_cm7.h ****   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetP
+2070:Drivers/CMSIS/Include/core_cm7.h ****  */
+2071:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
+ 128              		.loc 2 2071 26 view .LVU32
+ 129              	.LBB49:
+2072:Drivers/CMSIS/Include/core_cm7.h **** {
+2073:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
+ 130              		.loc 2 2073 3 view .LVU33
+2074:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t PreemptPriorityBits;
+ 131              		.loc 2 2074 3 view .LVU34
+2075:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t SubPriorityBits;
+ 132              		.loc 2 2075 3 view .LVU35
+2076:Drivers/CMSIS/Include/core_cm7.h **** 
+2077:Drivers/CMSIS/Include/core_cm7.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
+ 133              		.loc 2 2077 3 view .LVU36
+ 134              		.loc 2 2077 31 is_stmt 0 view .LVU37
+ 135 000a C3F1070C 		rsb	ip, r3, #7
+ 136              		.loc 2 2077 23 view .LVU38
+ 137 000e BCF1040F 		cmp	ip, #4
+ 138 0012 28BF     		it	cs
+ 139 0014 4FF0040C 		movcs	ip, #4
+ 140              	.LVL11:
+2078:Drivers/CMSIS/Include/core_cm7.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+ 141              		.loc 2 2078 3 is_stmt 1 view .LVU39
+ 142              		.loc 2 2078 44 is_stmt 0 view .LVU40
+ 143 0018 03F1040E 		add	lr, r3, #4
+ARM GAS  /tmp/ccs1e2mJ.s 			page 43
+
+
+ 144              		.loc 2 2078 109 view .LVU41
+ 145 001c BEF1060F 		cmp	lr, #6
+ 146 0020 14D9     		bls	.L8
+ 147 0022 033B     		subs	r3, r3, #3
+ 148              	.LVL12:
+ 149              	.L5:
+2079:Drivers/CMSIS/Include/core_cm7.h **** 
+2080:Drivers/CMSIS/Include/core_cm7.h ****   return (
+ 150              		.loc 2 2080 3 is_stmt 1 view .LVU42
+2081:Drivers/CMSIS/Include/core_cm7.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
+ 151              		.loc 2 2081 30 is_stmt 0 view .LVU43
+ 152 0024 4FF0FF3E 		mov	lr, #-1
+ 153              	.LVL13:
+ 154              		.loc 2 2081 30 view .LVU44
+ 155 0028 0EFA0CFC 		lsl	ip, lr, ip
+ 156              	.LVL14:
+ 157              		.loc 2 2081 30 view .LVU45
+ 158 002c 21EA0C01 		bic	r1, r1, ip
+ 159              	.LVL15:
+ 160              		.loc 2 2081 82 view .LVU46
+ 161 0030 9940     		lsls	r1, r1, r3
+2082:Drivers/CMSIS/Include/core_cm7.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+ 162              		.loc 2 2082 30 view .LVU47
+ 163 0032 0EFA03F3 		lsl	r3, lr, r3
+ 164              	.LVL16:
+ 165              		.loc 2 2082 30 view .LVU48
+ 166 0036 22EA0303 		bic	r3, r2, r3
+2081:Drivers/CMSIS/Include/core_cm7.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
+ 167              		.loc 2 2081 102 view .LVU49
+ 168 003a 1943     		orrs	r1, r1, r3
+ 169              	.LVL17:
+2081:Drivers/CMSIS/Include/core_cm7.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
+ 170              		.loc 2 2081 102 view .LVU50
+ 171              	.LBE49:
+ 172              	.LBE48:
+ 173              	.LBB51:
+ 174              	.LBI51:
+2024:Drivers/CMSIS/Include/core_cm7.h **** {
+ 175              		.loc 2 2024 22 is_stmt 1 view .LVU51
+ 176              	.LBB52:
+2026:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 177              		.loc 2 2026 3 view .LVU52
+2026:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 178              		.loc 2 2026 6 is_stmt 0 view .LVU53
+ 179 003c 0028     		cmp	r0, #0
+ 180 003e 07DB     		blt	.L6
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 181              		.loc 2 2028 5 is_stmt 1 view .LVU54
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 182              		.loc 2 2028 49 is_stmt 0 view .LVU55
+ 183 0040 0901     		lsls	r1, r1, #4
+ 184              	.LVL18:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 185              		.loc 2 2028 49 view .LVU56
+ 186 0042 C9B2     		uxtb	r1, r1
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 187              		.loc 2 2028 47 view .LVU57
+ARM GAS  /tmp/ccs1e2mJ.s 			page 44
+
+
+ 188 0044 074B     		ldr	r3, .L10+4
+ 189 0046 1954     		strb	r1, [r3, r0]
+ 190              	.LVL19:
+ 191              	.L4:
+2028:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 192              		.loc 2 2028 47 view .LVU58
+ 193              	.LBE52:
+ 194              	.LBE51:
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 195              		.loc 1 175 1 view .LVU59
+ 196 0048 5DF804FB 		ldr	pc, [sp], #4
+ 197              	.LVL20:
+ 198              	.L8:
+ 199              	.LBB54:
+ 200              	.LBB50:
+2078:Drivers/CMSIS/Include/core_cm7.h **** 
+ 201              		.loc 2 2078 109 view .LVU60
+ 202 004c 0023     		movs	r3, #0
+ 203              	.LVL21:
+2078:Drivers/CMSIS/Include/core_cm7.h **** 
+ 204              		.loc 2 2078 109 view .LVU61
+ 205 004e E9E7     		b	.L5
+ 206              	.LVL22:
+ 207              	.L6:
+2078:Drivers/CMSIS/Include/core_cm7.h **** 
+ 208              		.loc 2 2078 109 view .LVU62
+ 209              	.LBE50:
+ 210              	.LBE54:
+ 211              	.LBB55:
+ 212              	.LBB53:
+2032:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 213              		.loc 2 2032 5 is_stmt 1 view .LVU63
+2032:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 214              		.loc 2 2032 33 is_stmt 0 view .LVU64
+ 215 0050 00F00F00 		and	r0, r0, #15
+ 216              	.LVL23:
+2032:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 217              		.loc 2 2032 49 view .LVU65
+ 218 0054 0901     		lsls	r1, r1, #4
+ 219              	.LVL24:
+2032:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 220              		.loc 2 2032 49 view .LVU66
+ 221 0056 C9B2     		uxtb	r1, r1
+2032:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 222              		.loc 2 2032 47 view .LVU67
+ 223 0058 034B     		ldr	r3, .L10+8
+ 224 005a 1954     		strb	r1, [r3, r0]
+ 225              	.LVL25:
+2032:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 226              		.loc 2 2032 47 view .LVU68
+ 227              	.LBE53:
+ 228              	.LBE55:
+ 229              		.loc 1 175 1 view .LVU69
+ 230 005c F4E7     		b	.L4
+ 231              	.L11:
+ 232 005e 00BF     		.align	2
+ 233              	.L10:
+ARM GAS  /tmp/ccs1e2mJ.s 			page 45
+
+
+ 234 0060 00ED00E0 		.word	-536810240
+ 235 0064 00E400E0 		.word	-536812544
+ 236 0068 14ED00E0 		.word	-536810220
+ 237              		.cfi_endproc
+ 238              	.LFE142:
+ 240              		.section	.text.HAL_NVIC_EnableIRQ,"ax",%progbits
+ 241              		.align	1
+ 242              		.global	HAL_NVIC_EnableIRQ
+ 243              		.syntax unified
+ 244              		.thumb
+ 245              		.thumb_func
+ 246              		.fpu fpv5-d16
+ 248              	HAL_NVIC_EnableIRQ:
+ 249              	.LVL26:
+ 250              	.LFB143:
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         function should be called before. 
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 251              		.loc 1 187 1 is_stmt 1 view -0
+ 252              		.cfi_startproc
+ 253              		@ args = 0, pretend = 0, frame = 0
+ 254              		@ frame_needed = 0, uses_anonymous_args = 0
+ 255              		@ link register save eliminated.
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+ 256              		.loc 1 189 3 view .LVU71
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Enable interrupt */
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   NVIC_EnableIRQ(IRQn);
+ 257              		.loc 1 192 3 view .LVU72
+ 258              	.LBB56:
+ 259              	.LBI56:
+1896:Drivers/CMSIS/Include/core_cm7.h **** {
+ 260              		.loc 2 1896 22 view .LVU73
+ 261              	.LBB57:
+1898:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 262              		.loc 2 1898 3 view .LVU74
+1898:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 263              		.loc 2 1898 6 is_stmt 0 view .LVU75
+ 264 0000 0028     		cmp	r0, #0
+ 265              	.LVL27:
+1898:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 266              		.loc 2 1898 6 view .LVU76
+ 267 0002 07DB     		blt	.L12
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 268              		.loc 2 1900 5 is_stmt 1 view .LVU77
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 269              		.loc 2 1900 81 is_stmt 0 view .LVU78
+ARM GAS  /tmp/ccs1e2mJ.s 			page 46
+
+
+ 270 0004 00F01F02 		and	r2, r0, #31
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 271              		.loc 2 1900 34 view .LVU79
+ 272 0008 4009     		lsrs	r0, r0, #5
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 273              		.loc 2 1900 45 view .LVU80
+ 274 000a 0123     		movs	r3, #1
+ 275 000c 9340     		lsls	r3, r3, r2
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 276              		.loc 2 1900 43 view .LVU81
+ 277 000e 024A     		ldr	r2, .L14
+ 278 0010 42F82030 		str	r3, [r2, r0, lsl #2]
+ 279              	.LVL28:
+ 280              	.L12:
+1900:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 281              		.loc 2 1900 43 view .LVU82
+ 282              	.LBE57:
+ 283              	.LBE56:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 284              		.loc 1 193 1 view .LVU83
+ 285 0014 7047     		bx	lr
+ 286              	.L15:
+ 287 0016 00BF     		.align	2
+ 288              	.L14:
+ 289 0018 00E100E0 		.word	-536813312
+ 290              		.cfi_endproc
+ 291              	.LFE143:
+ 293              		.section	.text.HAL_NVIC_DisableIRQ,"ax",%progbits
+ 294              		.align	1
+ 295              		.global	HAL_NVIC_DisableIRQ
+ 296              		.syntax unified
+ 297              		.thumb
+ 298              		.thumb_func
+ 299              		.fpu fpv5-d16
+ 301              	HAL_NVIC_DisableIRQ:
+ 302              	.LVL29:
+ 303              	.LFB144:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 304              		.loc 1 203 1 is_stmt 1 view -0
+ 305              		.cfi_startproc
+ 306              		@ args = 0, pretend = 0, frame = 0
+ 307              		@ frame_needed = 0, uses_anonymous_args = 0
+ 308              		@ link register save eliminated.
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+ 309              		.loc 1 205 3 view .LVU85
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Disable interrupt */
+ARM GAS  /tmp/ccs1e2mJ.s 			page 47
+
+
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   NVIC_DisableIRQ(IRQn);
+ 310              		.loc 1 208 3 view .LVU86
+ 311              	.LBB64:
+ 312              	.LBI64:
+1932:Drivers/CMSIS/Include/core_cm7.h **** {
+ 313              		.loc 2 1932 22 view .LVU87
+ 314              	.LBB65:
+1934:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 315              		.loc 2 1934 3 view .LVU88
+1934:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 316              		.loc 2 1934 6 is_stmt 0 view .LVU89
+ 317 0000 0028     		cmp	r0, #0
+ 318              	.LVL30:
+1934:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 319              		.loc 2 1934 6 view .LVU90
+ 320 0002 0CDB     		blt	.L16
+1936:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+ 321              		.loc 2 1936 5 is_stmt 1 view .LVU91
+1936:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+ 322              		.loc 2 1936 81 is_stmt 0 view .LVU92
+ 323 0004 00F01F02 		and	r2, r0, #31
+1936:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+ 324              		.loc 2 1936 34 view .LVU93
+ 325 0008 4009     		lsrs	r0, r0, #5
+1936:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+ 326              		.loc 2 1936 45 view .LVU94
+ 327 000a 0123     		movs	r3, #1
+ 328 000c 9340     		lsls	r3, r3, r2
+1936:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+ 329              		.loc 2 1936 43 view .LVU95
+ 330 000e 2030     		adds	r0, r0, #32
+ 331 0010 034A     		ldr	r2, .L18
+ 332 0012 42F82030 		str	r3, [r2, r0, lsl #2]
+1937:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+ 333              		.loc 2 1937 5 is_stmt 1 view .LVU96
+ 334              	.LBB66:
+ 335              	.LBI66:
+ 336              		.file 3 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.0.4
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     09. April 2018
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ARM GAS  /tmp/ccs1e2mJ.s 			page 48
+
+
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+ARM GAS  /tmp/ccs1e2mJ.s 			page 49
+
+
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 50
+
+
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ARM GAS  /tmp/ccs1e2mJ.s 			page 51
+
+
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ARM GAS  /tmp/ccs1e2mJ.s 			page 52
+
+
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 53
+
+
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ARM GAS  /tmp/ccs1e2mJ.s 			page 54
+
+
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ARM GAS  /tmp/ccs1e2mJ.s 			page 55
+
+
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/ccs1e2mJ.s 			page 56
+
+
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ARM GAS  /tmp/ccs1e2mJ.s 			page 57
+
+
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ARM GAS  /tmp/ccs1e2mJ.s 			page 58
+
+
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ARM GAS  /tmp/ccs1e2mJ.s 			page 59
+
+
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccs1e2mJ.s 			page 60
+
+
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 61
+
+
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ARM GAS  /tmp/ccs1e2mJ.s 			page 62
+
+
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ARM GAS  /tmp/ccs1e2mJ.s 			page 63
+
+
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 337              		.loc 3 877 27 view .LVU97
+ 338              	.LBB67:
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 339              		.loc 3 879 3 view .LVU98
+ 340              		.syntax unified
+ 341              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 342 0016 BFF34F8F 		dsb 0xF
+ 343              	@ 0 "" 2
+ 344              		.thumb
+ 345              		.syntax unified
+ 346              	.LBE67:
+ 347              	.LBE66:
+1938:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 348              		.loc 2 1938 5 view .LVU99
+ 349              	.LBB68:
+ 350              	.LBI68:
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 351              		.loc 3 866 27 view .LVU100
+ 352              	.LBB69:
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 353              		.loc 3 868 3 view .LVU101
+ 354              		.syntax unified
+ 355              	@ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 356 001a BFF36F8F 		isb 0xF
+ 357              	@ 0 "" 2
+ 358              	.LVL31:
+ 359              		.thumb
+ 360              		.syntax unified
+ 361              	.L16:
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 362              		.loc 3 868 3 is_stmt 0 view .LVU102
+ 363              	.LBE69:
+ 364              	.LBE68:
+ 365              	.LBE65:
+ 366              	.LBE64:
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 367              		.loc 1 209 1 view .LVU103
+ 368 001e 7047     		bx	lr
+ 369              	.L19:
+ 370              		.align	2
+ 371              	.L18:
+ 372 0020 00E100E0 		.word	-536813312
+ 373              		.cfi_endproc
+ 374              	.LFE144:
+ 376              		.section	.text.HAL_NVIC_SystemReset,"ax",%progbits
+ 377              		.align	1
+ 378              		.global	HAL_NVIC_SystemReset
+ 379              		.syntax unified
+ 380              		.thumb
+ 381              		.thumb_func
+ 382              		.fpu fpv5-d16
+ 384              	HAL_NVIC_SystemReset:
+ 385              	.LFB145:
+ARM GAS  /tmp/ccs1e2mJ.s 			page 64
+
+
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Initiates a system reset request to reset the MCU.
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void)
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 386              		.loc 1 216 1 is_stmt 1 view -0
+ 387              		.cfi_startproc
+ 388              		@ Volatile: function does not return.
+ 389              		@ args = 0, pretend = 0, frame = 0
+ 390              		@ frame_needed = 0, uses_anonymous_args = 0
+ 391              		@ link register save eliminated.
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* System Reset */
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   NVIC_SystemReset();
+ 392              		.loc 1 218 3 view .LVU105
+ 393              	.LBB76:
+ 394              	.LBI76:
+2083:Drivers/CMSIS/Include/core_cm7.h ****          );
+2084:Drivers/CMSIS/Include/core_cm7.h **** }
+2085:Drivers/CMSIS/Include/core_cm7.h **** 
+2086:Drivers/CMSIS/Include/core_cm7.h **** 
+2087:Drivers/CMSIS/Include/core_cm7.h **** /**
+2088:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Decode Priority
+2089:Drivers/CMSIS/Include/core_cm7.h ****   \details Decodes an interrupt priority value with a given priority group to
+2090:Drivers/CMSIS/Include/core_cm7.h ****            preemptive priority value and subpriority value.
+2091:Drivers/CMSIS/Include/core_cm7.h ****            In case of a conflict between priority grouping and available
+2092:Drivers/CMSIS/Include/core_cm7.h ****            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+2093:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC
+2094:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]     PriorityGroup  Used priority group.
+2095:Drivers/CMSIS/Include/core_cm7.h ****   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+2096:Drivers/CMSIS/Include/core_cm7.h ****   \param [out]     pSubPriority  Subpriority value (starting from 0).
+2097:Drivers/CMSIS/Include/core_cm7.h ****  */
+2098:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons
+2099:Drivers/CMSIS/Include/core_cm7.h **** {
+2100:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
+2101:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t PreemptPriorityBits;
+2102:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t SubPriorityBits;
+2103:Drivers/CMSIS/Include/core_cm7.h **** 
+2104:Drivers/CMSIS/Include/core_cm7.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
+2105:Drivers/CMSIS/Include/core_cm7.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+2106:Drivers/CMSIS/Include/core_cm7.h **** 
+2107:Drivers/CMSIS/Include/core_cm7.h ****   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1
+2108:Drivers/CMSIS/Include/core_cm7.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
+2109:Drivers/CMSIS/Include/core_cm7.h **** }
+2110:Drivers/CMSIS/Include/core_cm7.h **** 
+2111:Drivers/CMSIS/Include/core_cm7.h **** 
+2112:Drivers/CMSIS/Include/core_cm7.h **** /**
+2113:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Set Interrupt Vector
+2114:Drivers/CMSIS/Include/core_cm7.h ****   \details Sets an interrupt vector in SRAM based interrupt vector table.
+2115:Drivers/CMSIS/Include/core_cm7.h ****            The interrupt number can be positive to specify a device specific interrupt,
+2116:Drivers/CMSIS/Include/core_cm7.h ****            or negative to specify a processor exception.
+2117:Drivers/CMSIS/Include/core_cm7.h ****            VTOR must been relocated to SRAM before.
+2118:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]   IRQn      Interrupt number
+2119:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]   vector    Address of interrupt handler function
+2120:Drivers/CMSIS/Include/core_cm7.h ****  */
+2121:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+ARM GAS  /tmp/ccs1e2mJ.s 			page 65
+
+
+2122:Drivers/CMSIS/Include/core_cm7.h **** {
+2123:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t *vectors = (uint32_t *)SCB->VTOR;
+2124:Drivers/CMSIS/Include/core_cm7.h ****   vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+2125:Drivers/CMSIS/Include/core_cm7.h **** }
+2126:Drivers/CMSIS/Include/core_cm7.h **** 
+2127:Drivers/CMSIS/Include/core_cm7.h **** 
+2128:Drivers/CMSIS/Include/core_cm7.h **** /**
+2129:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Get Interrupt Vector
+2130:Drivers/CMSIS/Include/core_cm7.h ****   \details Reads an interrupt vector from interrupt vector table.
+2131:Drivers/CMSIS/Include/core_cm7.h ****            The interrupt number can be positive to specify a device specific interrupt,
+2132:Drivers/CMSIS/Include/core_cm7.h ****            or negative to specify a processor exception.
+2133:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]   IRQn      Interrupt number.
+2134:Drivers/CMSIS/Include/core_cm7.h ****   \return                 Address of interrupt handler function
+2135:Drivers/CMSIS/Include/core_cm7.h ****  */
+2136:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+2137:Drivers/CMSIS/Include/core_cm7.h **** {
+2138:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t *vectors = (uint32_t *)SCB->VTOR;
+2139:Drivers/CMSIS/Include/core_cm7.h ****   return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+2140:Drivers/CMSIS/Include/core_cm7.h **** }
+2141:Drivers/CMSIS/Include/core_cm7.h **** 
+2142:Drivers/CMSIS/Include/core_cm7.h **** 
+2143:Drivers/CMSIS/Include/core_cm7.h **** /**
+2144:Drivers/CMSIS/Include/core_cm7.h ****   \brief   System Reset
+2145:Drivers/CMSIS/Include/core_cm7.h ****   \details Initiates a system reset request to reset the MCU.
+2146:Drivers/CMSIS/Include/core_cm7.h ****  */
+2147:Drivers/CMSIS/Include/core_cm7.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+ 395              		.loc 2 2147 34 view .LVU106
+ 396              	.LBB77:
+2148:Drivers/CMSIS/Include/core_cm7.h **** {
+2149:Drivers/CMSIS/Include/core_cm7.h ****   __DSB();                                                          /* Ensure all outstanding memor
+ 397              		.loc 2 2149 3 view .LVU107
+ 398              	.LBB78:
+ 399              	.LBI78:
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 400              		.loc 3 877 27 view .LVU108
+ 401              	.LBB79:
+ 402              		.loc 3 879 3 view .LVU109
+ 403              		.syntax unified
+ 404              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 405 0000 BFF34F8F 		dsb 0xF
+ 406              	@ 0 "" 2
+ 407              		.thumb
+ 408              		.syntax unified
+ 409              	.LBE79:
+ 410              	.LBE78:
+2150:Drivers/CMSIS/Include/core_cm7.h ****                                                                        buffered write are completed
+2151:Drivers/CMSIS/Include/core_cm7.h ****   SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+ 411              		.loc 2 2151 3 view .LVU110
+2152:Drivers/CMSIS/Include/core_cm7.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ 412              		.loc 2 2152 32 is_stmt 0 view .LVU111
+ 413 0004 0549     		ldr	r1, .L22
+ 414 0006 CA68     		ldr	r2, [r1, #12]
+ 415              		.loc 2 2152 40 view .LVU112
+ 416 0008 02F4E062 		and	r2, r2, #1792
+2151:Drivers/CMSIS/Include/core_cm7.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ 417              		.loc 2 2151 17 view .LVU113
+ 418 000c 044B     		ldr	r3, .L22+4
+ARM GAS  /tmp/ccs1e2mJ.s 			page 66
+
+
+ 419 000e 1343     		orrs	r3, r3, r2
+2151:Drivers/CMSIS/Include/core_cm7.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ 420              		.loc 2 2151 15 view .LVU114
+ 421 0010 CB60     		str	r3, [r1, #12]
+2153:Drivers/CMSIS/Include/core_cm7.h ****                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchange
+2154:Drivers/CMSIS/Include/core_cm7.h ****   __DSB();                                                          /* Ensure completion of memory 
+ 422              		.loc 2 2154 3 is_stmt 1 view .LVU115
+ 423              	.LBB80:
+ 424              	.LBI80:
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 425              		.loc 3 877 27 view .LVU116
+ 426              	.LBB81:
+ 427              		.loc 3 879 3 view .LVU117
+ 428              		.syntax unified
+ 429              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 430 0012 BFF34F8F 		dsb 0xF
+ 431              	@ 0 "" 2
+ 432              		.thumb
+ 433              		.syntax unified
+ 434              	.L21:
+ 435              	.LBE81:
+ 436              	.LBE80:
+2155:Drivers/CMSIS/Include/core_cm7.h **** 
+2156:Drivers/CMSIS/Include/core_cm7.h ****   for(;;)                                                           /* wait until reset */
+ 437              		.loc 2 2156 3 view .LVU118
+2157:Drivers/CMSIS/Include/core_cm7.h ****   {
+2158:Drivers/CMSIS/Include/core_cm7.h ****     __NOP();
+ 438              		.loc 2 2158 5 view .LVU119
+ 439              		.syntax unified
+ 440              	@ 2158 "Drivers/CMSIS/Include/core_cm7.h" 1
+ 441 0016 00BF     		nop
+ 442              	@ 0 "" 2
+2156:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 443              		.loc 2 2156 8 view .LVU120
+ 444              		.thumb
+ 445              		.syntax unified
+ 446 0018 FDE7     		b	.L21
+ 447              	.L23:
+ 448 001a 00BF     		.align	2
+ 449              	.L22:
+ 450 001c 00ED00E0 		.word	-536810240
+ 451 0020 0400FA05 		.word	100270084
+ 452              	.LBE77:
+ 453              	.LBE76:
+ 454              		.cfi_endproc
+ 455              	.LFE145:
+ 457              		.section	.text.HAL_SYSTICK_Config,"ax",%progbits
+ 458              		.align	1
+ 459              		.global	HAL_SYSTICK_Config
+ 460              		.syntax unified
+ 461              		.thumb
+ 462              		.thumb_func
+ 463              		.fpu fpv5-d16
+ 465              	HAL_SYSTICK_Config:
+ 466              	.LVL32:
+ 467              	.LFB146:
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ARM GAS  /tmp/ccs1e2mJ.s 			page 67
+
+
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         Counter is in free running mode to generate periodic interrupts.
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval status:  - 0  Function succeeded.
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                  - 1  Function failed.
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 468              		.loc 1 229 1 view -0
+ 469              		.cfi_startproc
+ 470              		@ args = 0, pretend = 0, frame = 0
+ 471              		@ frame_needed = 0, uses_anonymous_args = 0
+ 472              		@ link register save eliminated.
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****    return SysTick_Config(TicksNumb);
+ 473              		.loc 1 230 4 view .LVU122
+ 474              	.LBB82:
+ 475              	.LBI82:
+2159:Drivers/CMSIS/Include/core_cm7.h ****   }
+2160:Drivers/CMSIS/Include/core_cm7.h **** }
+2161:Drivers/CMSIS/Include/core_cm7.h **** 
+2162:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_NVICFunctions */
+2163:Drivers/CMSIS/Include/core_cm7.h **** 
+2164:Drivers/CMSIS/Include/core_cm7.h **** /* ##########################  MPU functions  #################################### */
+2165:Drivers/CMSIS/Include/core_cm7.h **** 
+2166:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+2167:Drivers/CMSIS/Include/core_cm7.h **** 
+2168:Drivers/CMSIS/Include/core_cm7.h **** #include "mpu_armv7.h"
+2169:Drivers/CMSIS/Include/core_cm7.h **** 
+2170:Drivers/CMSIS/Include/core_cm7.h **** #endif
+2171:Drivers/CMSIS/Include/core_cm7.h **** 
+2172:Drivers/CMSIS/Include/core_cm7.h **** /* ##########################  FPU functions  #################################### */
+2173:Drivers/CMSIS/Include/core_cm7.h **** /**
+2174:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_Core_FunctionInterface
+2175:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_Core_FpuFunctions FPU Functions
+2176:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Function that provides FPU type.
+2177:Drivers/CMSIS/Include/core_cm7.h ****   @{
+2178:Drivers/CMSIS/Include/core_cm7.h ****  */
+2179:Drivers/CMSIS/Include/core_cm7.h **** 
+2180:Drivers/CMSIS/Include/core_cm7.h **** /**
+2181:Drivers/CMSIS/Include/core_cm7.h ****   \brief   get FPU type
+2182:Drivers/CMSIS/Include/core_cm7.h ****   \details returns the FPU type
+2183:Drivers/CMSIS/Include/core_cm7.h ****   \returns
+2184:Drivers/CMSIS/Include/core_cm7.h ****    - \b  0: No FPU
+2185:Drivers/CMSIS/Include/core_cm7.h ****    - \b  1: Single precision FPU
+2186:Drivers/CMSIS/Include/core_cm7.h ****    - \b  2: Double + Single precision FPU
+2187:Drivers/CMSIS/Include/core_cm7.h ****  */
+2188:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void)
+2189:Drivers/CMSIS/Include/core_cm7.h **** {
+2190:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t mvfr0;
+2191:Drivers/CMSIS/Include/core_cm7.h **** 
+2192:Drivers/CMSIS/Include/core_cm7.h ****   mvfr0 = SCB->MVFR0;
+2193:Drivers/CMSIS/Include/core_cm7.h ****   if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+2194:Drivers/CMSIS/Include/core_cm7.h ****   {
+2195:Drivers/CMSIS/Include/core_cm7.h ****     return 2U;           /* Double + Single precision FPU */
+2196:Drivers/CMSIS/Include/core_cm7.h ****   }
+ARM GAS  /tmp/ccs1e2mJ.s 			page 68
+
+
+2197:Drivers/CMSIS/Include/core_cm7.h ****   else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+2198:Drivers/CMSIS/Include/core_cm7.h ****   {
+2199:Drivers/CMSIS/Include/core_cm7.h ****     return 1U;           /* Single precision FPU */
+2200:Drivers/CMSIS/Include/core_cm7.h ****   }
+2201:Drivers/CMSIS/Include/core_cm7.h ****   else
+2202:Drivers/CMSIS/Include/core_cm7.h ****   {
+2203:Drivers/CMSIS/Include/core_cm7.h ****     return 0U;           /* No FPU */
+2204:Drivers/CMSIS/Include/core_cm7.h ****   }
+2205:Drivers/CMSIS/Include/core_cm7.h **** }
+2206:Drivers/CMSIS/Include/core_cm7.h **** 
+2207:Drivers/CMSIS/Include/core_cm7.h **** 
+2208:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_FpuFunctions */
+2209:Drivers/CMSIS/Include/core_cm7.h **** 
+2210:Drivers/CMSIS/Include/core_cm7.h **** 
+2211:Drivers/CMSIS/Include/core_cm7.h **** 
+2212:Drivers/CMSIS/Include/core_cm7.h **** /* ##########################  Cache functions  #################################### */
+2213:Drivers/CMSIS/Include/core_cm7.h **** /**
+2214:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_Core_FunctionInterface
+2215:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_Core_CacheFunctions Cache Functions
+2216:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Functions that configure Instruction and Data cache.
+2217:Drivers/CMSIS/Include/core_cm7.h ****   @{
+2218:Drivers/CMSIS/Include/core_cm7.h ****  */
+2219:Drivers/CMSIS/Include/core_cm7.h **** 
+2220:Drivers/CMSIS/Include/core_cm7.h **** /* Cache Size ID Register Macros */
+2221:Drivers/CMSIS/Include/core_cm7.h **** #define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Po
+2222:Drivers/CMSIS/Include/core_cm7.h **** #define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos     
+2223:Drivers/CMSIS/Include/core_cm7.h **** 
+2224:Drivers/CMSIS/Include/core_cm7.h **** 
+2225:Drivers/CMSIS/Include/core_cm7.h **** /**
+2226:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Enable I-Cache
+2227:Drivers/CMSIS/Include/core_cm7.h ****   \details Turns on I-Cache
+2228:Drivers/CMSIS/Include/core_cm7.h ****   */
+2229:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_EnableICache (void)
+2230:Drivers/CMSIS/Include/core_cm7.h **** {
+2231:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+2232:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2233:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2234:Drivers/CMSIS/Include/core_cm7.h ****     SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+2235:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2236:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2237:Drivers/CMSIS/Include/core_cm7.h ****     SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+2238:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2239:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2240:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+2241:Drivers/CMSIS/Include/core_cm7.h **** }
+2242:Drivers/CMSIS/Include/core_cm7.h **** 
+2243:Drivers/CMSIS/Include/core_cm7.h **** 
+2244:Drivers/CMSIS/Include/core_cm7.h **** /**
+2245:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Disable I-Cache
+2246:Drivers/CMSIS/Include/core_cm7.h ****   \details Turns off I-Cache
+2247:Drivers/CMSIS/Include/core_cm7.h ****   */
+2248:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_DisableICache (void)
+2249:Drivers/CMSIS/Include/core_cm7.h **** {
+2250:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+2251:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2252:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2253:Drivers/CMSIS/Include/core_cm7.h ****     SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+ARM GAS  /tmp/ccs1e2mJ.s 			page 69
+
+
+2254:Drivers/CMSIS/Include/core_cm7.h ****     SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+2255:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2256:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2257:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+2258:Drivers/CMSIS/Include/core_cm7.h **** }
+2259:Drivers/CMSIS/Include/core_cm7.h **** 
+2260:Drivers/CMSIS/Include/core_cm7.h **** 
+2261:Drivers/CMSIS/Include/core_cm7.h **** /**
+2262:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Invalidate I-Cache
+2263:Drivers/CMSIS/Include/core_cm7.h ****   \details Invalidates I-Cache
+2264:Drivers/CMSIS/Include/core_cm7.h ****   */
+2265:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateICache (void)
+2266:Drivers/CMSIS/Include/core_cm7.h **** {
+2267:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+2268:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2269:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2270:Drivers/CMSIS/Include/core_cm7.h ****     SCB->ICIALLU = 0UL;
+2271:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2272:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2273:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+2274:Drivers/CMSIS/Include/core_cm7.h **** }
+2275:Drivers/CMSIS/Include/core_cm7.h **** 
+2276:Drivers/CMSIS/Include/core_cm7.h **** 
+2277:Drivers/CMSIS/Include/core_cm7.h **** /**
+2278:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Enable D-Cache
+2279:Drivers/CMSIS/Include/core_cm7.h ****   \details Turns on D-Cache
+2280:Drivers/CMSIS/Include/core_cm7.h ****   */
+2281:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_EnableDCache (void)
+2282:Drivers/CMSIS/Include/core_cm7.h **** {
+2283:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+2284:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ccsidr;
+2285:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t sets;
+2286:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ways;
+2287:Drivers/CMSIS/Include/core_cm7.h **** 
+2288:Drivers/CMSIS/Include/core_cm7.h ****     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+2289:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2290:Drivers/CMSIS/Include/core_cm7.h **** 
+2291:Drivers/CMSIS/Include/core_cm7.h ****     ccsidr = SCB->CCSIDR;
+2292:Drivers/CMSIS/Include/core_cm7.h **** 
+2293:Drivers/CMSIS/Include/core_cm7.h ****                                             /* invalidate D-Cache */
+2294:Drivers/CMSIS/Include/core_cm7.h ****     sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+2295:Drivers/CMSIS/Include/core_cm7.h ****     do {
+2296:Drivers/CMSIS/Include/core_cm7.h ****       ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+2297:Drivers/CMSIS/Include/core_cm7.h ****       do {
+2298:Drivers/CMSIS/Include/core_cm7.h ****         SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+2299:Drivers/CMSIS/Include/core_cm7.h ****                       ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+2300:Drivers/CMSIS/Include/core_cm7.h ****         #if defined ( __CC_ARM )
+2301:Drivers/CMSIS/Include/core_cm7.h ****           __schedule_barrier();
+2302:Drivers/CMSIS/Include/core_cm7.h ****         #endif
+2303:Drivers/CMSIS/Include/core_cm7.h ****       } while (ways-- != 0U);
+2304:Drivers/CMSIS/Include/core_cm7.h ****     } while(sets-- != 0U);
+2305:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2306:Drivers/CMSIS/Include/core_cm7.h **** 
+2307:Drivers/CMSIS/Include/core_cm7.h ****     SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+2308:Drivers/CMSIS/Include/core_cm7.h **** 
+2309:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2310:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+ARM GAS  /tmp/ccs1e2mJ.s 			page 70
+
+
+2311:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+2312:Drivers/CMSIS/Include/core_cm7.h **** }
+2313:Drivers/CMSIS/Include/core_cm7.h **** 
+2314:Drivers/CMSIS/Include/core_cm7.h **** 
+2315:Drivers/CMSIS/Include/core_cm7.h **** /**
+2316:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Disable D-Cache
+2317:Drivers/CMSIS/Include/core_cm7.h ****   \details Turns off D-Cache
+2318:Drivers/CMSIS/Include/core_cm7.h ****   */
+2319:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_DisableDCache (void)
+2320:Drivers/CMSIS/Include/core_cm7.h **** {
+2321:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+2322:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ccsidr;
+2323:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t sets;
+2324:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ways;
+2325:Drivers/CMSIS/Include/core_cm7.h **** 
+2326:Drivers/CMSIS/Include/core_cm7.h ****     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+2327:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2328:Drivers/CMSIS/Include/core_cm7.h **** 
+2329:Drivers/CMSIS/Include/core_cm7.h ****     SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+2330:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2331:Drivers/CMSIS/Include/core_cm7.h **** 
+2332:Drivers/CMSIS/Include/core_cm7.h ****     ccsidr = SCB->CCSIDR;
+2333:Drivers/CMSIS/Include/core_cm7.h **** 
+2334:Drivers/CMSIS/Include/core_cm7.h ****                                             /* clean & invalidate D-Cache */
+2335:Drivers/CMSIS/Include/core_cm7.h ****     sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+2336:Drivers/CMSIS/Include/core_cm7.h ****     do {
+2337:Drivers/CMSIS/Include/core_cm7.h ****       ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+2338:Drivers/CMSIS/Include/core_cm7.h ****       do {
+2339:Drivers/CMSIS/Include/core_cm7.h ****         SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+2340:Drivers/CMSIS/Include/core_cm7.h ****                        ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+2341:Drivers/CMSIS/Include/core_cm7.h ****         #if defined ( __CC_ARM )
+2342:Drivers/CMSIS/Include/core_cm7.h ****           __schedule_barrier();
+2343:Drivers/CMSIS/Include/core_cm7.h ****         #endif
+2344:Drivers/CMSIS/Include/core_cm7.h ****       } while (ways-- != 0U);
+2345:Drivers/CMSIS/Include/core_cm7.h ****     } while(sets-- != 0U);
+2346:Drivers/CMSIS/Include/core_cm7.h **** 
+2347:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2348:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2349:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+2350:Drivers/CMSIS/Include/core_cm7.h **** }
+2351:Drivers/CMSIS/Include/core_cm7.h **** 
+2352:Drivers/CMSIS/Include/core_cm7.h **** 
+2353:Drivers/CMSIS/Include/core_cm7.h **** /**
+2354:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Invalidate D-Cache
+2355:Drivers/CMSIS/Include/core_cm7.h ****   \details Invalidates D-Cache
+2356:Drivers/CMSIS/Include/core_cm7.h ****   */
+2357:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateDCache (void)
+2358:Drivers/CMSIS/Include/core_cm7.h **** {
+2359:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+2360:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ccsidr;
+2361:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t sets;
+2362:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ways;
+2363:Drivers/CMSIS/Include/core_cm7.h **** 
+2364:Drivers/CMSIS/Include/core_cm7.h ****     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+2365:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2366:Drivers/CMSIS/Include/core_cm7.h **** 
+2367:Drivers/CMSIS/Include/core_cm7.h ****     ccsidr = SCB->CCSIDR;
+ARM GAS  /tmp/ccs1e2mJ.s 			page 71
+
+
+2368:Drivers/CMSIS/Include/core_cm7.h **** 
+2369:Drivers/CMSIS/Include/core_cm7.h ****                                             /* invalidate D-Cache */
+2370:Drivers/CMSIS/Include/core_cm7.h ****     sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+2371:Drivers/CMSIS/Include/core_cm7.h ****     do {
+2372:Drivers/CMSIS/Include/core_cm7.h ****       ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+2373:Drivers/CMSIS/Include/core_cm7.h ****       do {
+2374:Drivers/CMSIS/Include/core_cm7.h ****         SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+2375:Drivers/CMSIS/Include/core_cm7.h ****                       ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+2376:Drivers/CMSIS/Include/core_cm7.h ****         #if defined ( __CC_ARM )
+2377:Drivers/CMSIS/Include/core_cm7.h ****           __schedule_barrier();
+2378:Drivers/CMSIS/Include/core_cm7.h ****         #endif
+2379:Drivers/CMSIS/Include/core_cm7.h ****       } while (ways-- != 0U);
+2380:Drivers/CMSIS/Include/core_cm7.h ****     } while(sets-- != 0U);
+2381:Drivers/CMSIS/Include/core_cm7.h **** 
+2382:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2383:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2384:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+2385:Drivers/CMSIS/Include/core_cm7.h **** }
+2386:Drivers/CMSIS/Include/core_cm7.h **** 
+2387:Drivers/CMSIS/Include/core_cm7.h **** 
+2388:Drivers/CMSIS/Include/core_cm7.h **** /**
+2389:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Clean D-Cache
+2390:Drivers/CMSIS/Include/core_cm7.h ****   \details Cleans D-Cache
+2391:Drivers/CMSIS/Include/core_cm7.h ****   */
+2392:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanDCache (void)
+2393:Drivers/CMSIS/Include/core_cm7.h **** {
+2394:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+2395:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ccsidr;
+2396:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t sets;
+2397:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ways;
+2398:Drivers/CMSIS/Include/core_cm7.h **** 
+2399:Drivers/CMSIS/Include/core_cm7.h ****      SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+2400:Drivers/CMSIS/Include/core_cm7.h ****    __DSB();
+2401:Drivers/CMSIS/Include/core_cm7.h **** 
+2402:Drivers/CMSIS/Include/core_cm7.h ****     ccsidr = SCB->CCSIDR;
+2403:Drivers/CMSIS/Include/core_cm7.h **** 
+2404:Drivers/CMSIS/Include/core_cm7.h ****                                             /* clean D-Cache */
+2405:Drivers/CMSIS/Include/core_cm7.h ****     sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+2406:Drivers/CMSIS/Include/core_cm7.h ****     do {
+2407:Drivers/CMSIS/Include/core_cm7.h ****       ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+2408:Drivers/CMSIS/Include/core_cm7.h ****       do {
+2409:Drivers/CMSIS/Include/core_cm7.h ****         SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+2410:Drivers/CMSIS/Include/core_cm7.h ****                       ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+2411:Drivers/CMSIS/Include/core_cm7.h ****         #if defined ( __CC_ARM )
+2412:Drivers/CMSIS/Include/core_cm7.h ****           __schedule_barrier();
+2413:Drivers/CMSIS/Include/core_cm7.h ****         #endif
+2414:Drivers/CMSIS/Include/core_cm7.h ****       } while (ways-- != 0U);
+2415:Drivers/CMSIS/Include/core_cm7.h ****     } while(sets-- != 0U);
+2416:Drivers/CMSIS/Include/core_cm7.h **** 
+2417:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2418:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2419:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+2420:Drivers/CMSIS/Include/core_cm7.h **** }
+2421:Drivers/CMSIS/Include/core_cm7.h **** 
+2422:Drivers/CMSIS/Include/core_cm7.h **** 
+2423:Drivers/CMSIS/Include/core_cm7.h **** /**
+2424:Drivers/CMSIS/Include/core_cm7.h ****   \brief   Clean & Invalidate D-Cache
+ARM GAS  /tmp/ccs1e2mJ.s 			page 72
+
+
+2425:Drivers/CMSIS/Include/core_cm7.h ****   \details Cleans and Invalidates D-Cache
+2426:Drivers/CMSIS/Include/core_cm7.h ****   */
+2427:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+2428:Drivers/CMSIS/Include/core_cm7.h **** {
+2429:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+2430:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ccsidr;
+2431:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t sets;
+2432:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t ways;
+2433:Drivers/CMSIS/Include/core_cm7.h **** 
+2434:Drivers/CMSIS/Include/core_cm7.h ****     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+2435:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2436:Drivers/CMSIS/Include/core_cm7.h **** 
+2437:Drivers/CMSIS/Include/core_cm7.h ****     ccsidr = SCB->CCSIDR;
+2438:Drivers/CMSIS/Include/core_cm7.h **** 
+2439:Drivers/CMSIS/Include/core_cm7.h ****                                             /* clean & invalidate D-Cache */
+2440:Drivers/CMSIS/Include/core_cm7.h ****     sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+2441:Drivers/CMSIS/Include/core_cm7.h ****     do {
+2442:Drivers/CMSIS/Include/core_cm7.h ****       ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+2443:Drivers/CMSIS/Include/core_cm7.h ****       do {
+2444:Drivers/CMSIS/Include/core_cm7.h ****         SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+2445:Drivers/CMSIS/Include/core_cm7.h ****                        ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+2446:Drivers/CMSIS/Include/core_cm7.h ****         #if defined ( __CC_ARM )
+2447:Drivers/CMSIS/Include/core_cm7.h ****           __schedule_barrier();
+2448:Drivers/CMSIS/Include/core_cm7.h ****         #endif
+2449:Drivers/CMSIS/Include/core_cm7.h ****       } while (ways-- != 0U);
+2450:Drivers/CMSIS/Include/core_cm7.h ****     } while(sets-- != 0U);
+2451:Drivers/CMSIS/Include/core_cm7.h **** 
+2452:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2453:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2454:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+2455:Drivers/CMSIS/Include/core_cm7.h **** }
+2456:Drivers/CMSIS/Include/core_cm7.h **** 
+2457:Drivers/CMSIS/Include/core_cm7.h **** 
+2458:Drivers/CMSIS/Include/core_cm7.h **** /**
+2459:Drivers/CMSIS/Include/core_cm7.h ****   \brief   D-Cache Invalidate by address
+2460:Drivers/CMSIS/Include/core_cm7.h ****   \details Invalidates D-Cache for the given address
+2461:Drivers/CMSIS/Include/core_cm7.h ****   \param[in]   addr    address (aligned to 32-byte boundary)
+2462:Drivers/CMSIS/Include/core_cm7.h ****   \param[in]   dsize   size of memory block (in number of bytes)
+2463:Drivers/CMSIS/Include/core_cm7.h **** */
+2464:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+2465:Drivers/CMSIS/Include/core_cm7.h **** {
+2466:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+2467:Drivers/CMSIS/Include/core_cm7.h ****      int32_t op_size = dsize;
+2468:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t op_addr = (uint32_t)addr;
+2469:Drivers/CMSIS/Include/core_cm7.h ****      int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (
+2470:Drivers/CMSIS/Include/core_cm7.h **** 
+2471:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2472:Drivers/CMSIS/Include/core_cm7.h **** 
+2473:Drivers/CMSIS/Include/core_cm7.h ****     while (op_size > 0) {
+2474:Drivers/CMSIS/Include/core_cm7.h ****       SCB->DCIMVAC = op_addr;
+2475:Drivers/CMSIS/Include/core_cm7.h ****       op_addr += (uint32_t)linesize;
+2476:Drivers/CMSIS/Include/core_cm7.h ****       op_size -=           linesize;
+2477:Drivers/CMSIS/Include/core_cm7.h ****     }
+2478:Drivers/CMSIS/Include/core_cm7.h **** 
+2479:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2480:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2481:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+ARM GAS  /tmp/ccs1e2mJ.s 			page 73
+
+
+2482:Drivers/CMSIS/Include/core_cm7.h **** }
+2483:Drivers/CMSIS/Include/core_cm7.h **** 
+2484:Drivers/CMSIS/Include/core_cm7.h **** 
+2485:Drivers/CMSIS/Include/core_cm7.h **** /**
+2486:Drivers/CMSIS/Include/core_cm7.h ****   \brief   D-Cache Clean by address
+2487:Drivers/CMSIS/Include/core_cm7.h ****   \details Cleans D-Cache for the given address
+2488:Drivers/CMSIS/Include/core_cm7.h ****   \param[in]   addr    address (aligned to 32-byte boundary)
+2489:Drivers/CMSIS/Include/core_cm7.h ****   \param[in]   dsize   size of memory block (in number of bytes)
+2490:Drivers/CMSIS/Include/core_cm7.h **** */
+2491:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+2492:Drivers/CMSIS/Include/core_cm7.h **** {
+2493:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+2494:Drivers/CMSIS/Include/core_cm7.h ****      int32_t op_size = dsize;
+2495:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t op_addr = (uint32_t) addr;
+2496:Drivers/CMSIS/Include/core_cm7.h ****      int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (
+2497:Drivers/CMSIS/Include/core_cm7.h **** 
+2498:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2499:Drivers/CMSIS/Include/core_cm7.h **** 
+2500:Drivers/CMSIS/Include/core_cm7.h ****     while (op_size > 0) {
+2501:Drivers/CMSIS/Include/core_cm7.h ****       SCB->DCCMVAC = op_addr;
+2502:Drivers/CMSIS/Include/core_cm7.h ****       op_addr += (uint32_t)linesize;
+2503:Drivers/CMSIS/Include/core_cm7.h ****       op_size -=           linesize;
+2504:Drivers/CMSIS/Include/core_cm7.h ****     }
+2505:Drivers/CMSIS/Include/core_cm7.h **** 
+2506:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2507:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2508:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+2509:Drivers/CMSIS/Include/core_cm7.h **** }
+2510:Drivers/CMSIS/Include/core_cm7.h **** 
+2511:Drivers/CMSIS/Include/core_cm7.h **** 
+2512:Drivers/CMSIS/Include/core_cm7.h **** /**
+2513:Drivers/CMSIS/Include/core_cm7.h ****   \brief   D-Cache Clean and Invalidate by address
+2514:Drivers/CMSIS/Include/core_cm7.h ****   \details Cleans and invalidates D_Cache for the given address
+2515:Drivers/CMSIS/Include/core_cm7.h ****   \param[in]   addr    address (aligned to 32-byte boundary)
+2516:Drivers/CMSIS/Include/core_cm7.h ****   \param[in]   dsize   size of memory block (in number of bytes)
+2517:Drivers/CMSIS/Include/core_cm7.h **** */
+2518:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+2519:Drivers/CMSIS/Include/core_cm7.h **** {
+2520:Drivers/CMSIS/Include/core_cm7.h ****   #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+2521:Drivers/CMSIS/Include/core_cm7.h ****      int32_t op_size = dsize;
+2522:Drivers/CMSIS/Include/core_cm7.h ****     uint32_t op_addr = (uint32_t) addr;
+2523:Drivers/CMSIS/Include/core_cm7.h ****      int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (
+2524:Drivers/CMSIS/Include/core_cm7.h **** 
+2525:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2526:Drivers/CMSIS/Include/core_cm7.h **** 
+2527:Drivers/CMSIS/Include/core_cm7.h ****     while (op_size > 0) {
+2528:Drivers/CMSIS/Include/core_cm7.h ****       SCB->DCCIMVAC = op_addr;
+2529:Drivers/CMSIS/Include/core_cm7.h ****       op_addr += (uint32_t)linesize;
+2530:Drivers/CMSIS/Include/core_cm7.h ****       op_size -=           linesize;
+2531:Drivers/CMSIS/Include/core_cm7.h ****     }
+2532:Drivers/CMSIS/Include/core_cm7.h **** 
+2533:Drivers/CMSIS/Include/core_cm7.h ****     __DSB();
+2534:Drivers/CMSIS/Include/core_cm7.h ****     __ISB();
+2535:Drivers/CMSIS/Include/core_cm7.h ****   #endif
+2536:Drivers/CMSIS/Include/core_cm7.h **** }
+2537:Drivers/CMSIS/Include/core_cm7.h **** 
+2538:Drivers/CMSIS/Include/core_cm7.h **** 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 74
+
+
+2539:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_CacheFunctions */
+2540:Drivers/CMSIS/Include/core_cm7.h **** 
+2541:Drivers/CMSIS/Include/core_cm7.h **** 
+2542:Drivers/CMSIS/Include/core_cm7.h **** 
+2543:Drivers/CMSIS/Include/core_cm7.h **** /* ##################################    SysTick function  ########################################
+2544:Drivers/CMSIS/Include/core_cm7.h **** /**
+2545:Drivers/CMSIS/Include/core_cm7.h ****   \ingroup  CMSIS_Core_FunctionInterface
+2546:Drivers/CMSIS/Include/core_cm7.h ****   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+2547:Drivers/CMSIS/Include/core_cm7.h ****   \brief    Functions that configure the System.
+2548:Drivers/CMSIS/Include/core_cm7.h ****   @{
+2549:Drivers/CMSIS/Include/core_cm7.h ****  */
+2550:Drivers/CMSIS/Include/core_cm7.h **** 
+2551:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+2552:Drivers/CMSIS/Include/core_cm7.h **** 
+2553:Drivers/CMSIS/Include/core_cm7.h **** /**
+2554:Drivers/CMSIS/Include/core_cm7.h ****   \brief   System Tick Configuration
+2555:Drivers/CMSIS/Include/core_cm7.h ****   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+2556:Drivers/CMSIS/Include/core_cm7.h ****            Counter is in free running mode to generate periodic interrupts.
+2557:Drivers/CMSIS/Include/core_cm7.h ****   \param [in]  ticks  Number of ticks between two interrupts.
+2558:Drivers/CMSIS/Include/core_cm7.h ****   \return          0  Function succeeded.
+2559:Drivers/CMSIS/Include/core_cm7.h ****   \return          1  Function failed.
+2560:Drivers/CMSIS/Include/core_cm7.h ****   \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+2561:Drivers/CMSIS/Include/core_cm7.h ****            function SysTick_Config is not included. In this case, the file device.
+2562:Drivers/CMSIS/Include/core_cm7.h ****            must contain a vendor-specific implementation of this function.
+2563:Drivers/CMSIS/Include/core_cm7.h ****  */
+2564:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+ 476              		.loc 2 2564 26 view .LVU123
+ 477              	.LBB83:
+2565:Drivers/CMSIS/Include/core_cm7.h **** {
+2566:Drivers/CMSIS/Include/core_cm7.h ****   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 478              		.loc 2 2566 3 view .LVU124
+ 479              		.loc 2 2566 14 is_stmt 0 view .LVU125
+ 480 0000 0138     		subs	r0, r0, #1
+ 481              	.LVL33:
+ 482              		.loc 2 2566 6 view .LVU126
+ 483 0002 B0F1807F 		cmp	r0, #16777216
+ 484 0006 0BD2     		bcs	.L26
+2567:Drivers/CMSIS/Include/core_cm7.h ****   {
+2568:Drivers/CMSIS/Include/core_cm7.h ****     return (1UL);                                                   /* Reload value impossible */
+2569:Drivers/CMSIS/Include/core_cm7.h ****   }
+2570:Drivers/CMSIS/Include/core_cm7.h **** 
+2571:Drivers/CMSIS/Include/core_cm7.h ****   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+ 485              		.loc 2 2571 3 is_stmt 1 view .LVU127
+ 486              		.loc 2 2571 18 is_stmt 0 view .LVU128
+ 487 0008 4FF0E023 		mov	r3, #-536813568
+ 488 000c 5861     		str	r0, [r3, #20]
+2572:Drivers/CMSIS/Include/core_cm7.h ****   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int
+ 489              		.loc 2 2572 3 is_stmt 1 view .LVU129
+ 490              	.LVL34:
+ 491              	.LBB84:
+ 492              	.LBI84:
+2024:Drivers/CMSIS/Include/core_cm7.h **** {
+ 493              		.loc 2 2024 22 view .LVU130
+ 494              	.LBB85:
+2026:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 495              		.loc 2 2026 3 view .LVU131
+2032:Drivers/CMSIS/Include/core_cm7.h ****   }
+ARM GAS  /tmp/ccs1e2mJ.s 			page 75
+
+
+ 496              		.loc 2 2032 5 view .LVU132
+2032:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 497              		.loc 2 2032 47 is_stmt 0 view .LVU133
+ 498 000e 054A     		ldr	r2, .L27
+ 499 0010 F021     		movs	r1, #240
+ 500 0012 82F82310 		strb	r1, [r2, #35]
+ 501              	.LVL35:
+2032:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 502              		.loc 2 2032 47 view .LVU134
+ 503              	.LBE85:
+ 504              	.LBE84:
+2573:Drivers/CMSIS/Include/core_cm7.h ****   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Val
+ 505              		.loc 2 2573 3 is_stmt 1 view .LVU135
+ 506              		.loc 2 2573 18 is_stmt 0 view .LVU136
+ 507 0016 0020     		movs	r0, #0
+ 508              	.LVL36:
+ 509              		.loc 2 2573 18 view .LVU137
+ 510 0018 9861     		str	r0, [r3, #24]
+2574:Drivers/CMSIS/Include/core_cm7.h ****   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+ 511              		.loc 2 2574 3 is_stmt 1 view .LVU138
+ 512              		.loc 2 2574 18 is_stmt 0 view .LVU139
+ 513 001a 0722     		movs	r2, #7
+ 514 001c 1A61     		str	r2, [r3, #16]
+2575:Drivers/CMSIS/Include/core_cm7.h ****                    SysTick_CTRL_TICKINT_Msk   |
+2576:Drivers/CMSIS/Include/core_cm7.h ****                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTi
+2577:Drivers/CMSIS/Include/core_cm7.h ****   return (0UL);                                                     /* Function successful */
+ 515              		.loc 2 2577 3 is_stmt 1 view .LVU140
+ 516              		.loc 2 2577 10 is_stmt 0 view .LVU141
+ 517 001e 7047     		bx	lr
+ 518              	.L26:
+2568:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 519              		.loc 2 2568 12 view .LVU142
+ 520 0020 0120     		movs	r0, #1
+ 521              	.LVL37:
+2568:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 522              		.loc 2 2568 12 view .LVU143
+ 523              	.LBE83:
+ 524              	.LBE82:
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 525              		.loc 1 231 1 view .LVU144
+ 526 0022 7047     		bx	lr
+ 527              	.L28:
+ 528              		.align	2
+ 529              	.L27:
+ 530 0024 00ED00E0 		.word	-536810240
+ 531              		.cfi_endproc
+ 532              	.LFE146:
+ 534              		.section	.text.HAL_MPU_Disable,"ax",%progbits
+ 535              		.align	1
+ 536              		.global	HAL_MPU_Disable
+ 537              		.syntax unified
+ 538              		.thumb
+ 539              		.thumb_func
+ 540              		.fpu fpv5-d16
+ 542              	HAL_MPU_Disable:
+ 543              	.LFB147:
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ARM GAS  /tmp/ccs1e2mJ.s 			page 76
+
+
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @}
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****  *  @brief   Cortex control functions 
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****  *
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** @verbatim   
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   ==============================================================================
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****                       ##### Peripheral Control functions #####
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   ==============================================================================  
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     [..]
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****       This subsection provides a set of functions allowing to control the CORTEX
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****       (NVIC, SYSTICK, MPU) functionalities. 
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****  
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****       
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** @endverbatim
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @{
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** #if (__MPU_PRESENT == 1)
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Disables the MPU
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_MPU_Disable(void)
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 544              		.loc 1 258 1 is_stmt 1 view -0
+ 545              		.cfi_startproc
+ 546              		@ args = 0, pretend = 0, frame = 0
+ 547              		@ frame_needed = 0, uses_anonymous_args = 0
+ 548              		@ link register save eliminated.
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Make sure outstanding transfers are done */
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   __DMB();
+ 549              		.loc 1 260 3 view .LVU146
+ 550              	.LBB86:
+ 551              	.LBI86:
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
+ 552              		.loc 3 888 27 view .LVU147
+ 553              	.LBB87:
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 554              		.loc 3 890 3 view .LVU148
+ 555              		.syntax unified
+ 556              	@ 890 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 557 0000 BFF35F8F 		dmb 0xF
+ 558              	@ 0 "" 2
+ 559              		.thumb
+ 560              		.syntax unified
+ 561              	.LBE87:
+ARM GAS  /tmp/ccs1e2mJ.s 			page 77
+
+
+ 562              	.LBE86:
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Disable fault exceptions */
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+ 563              		.loc 1 263 3 view .LVU149
+ 564              		.loc 1 263 14 is_stmt 0 view .LVU150
+ 565 0004 044B     		ldr	r3, .L30
+ 566 0006 5A6A     		ldr	r2, [r3, #36]
+ 567 0008 22F48032 		bic	r2, r2, #65536
+ 568 000c 5A62     		str	r2, [r3, #36]
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Disable the MPU and clear the control register*/
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   MPU->CTRL = 0;
+ 569              		.loc 1 266 3 is_stmt 1 view .LVU151
+ 570              		.loc 1 266 13 is_stmt 0 view .LVU152
+ 571 000e 0022     		movs	r2, #0
+ 572 0010 C3F89420 		str	r2, [r3, #148]
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 573              		.loc 1 267 1 view .LVU153
+ 574 0014 7047     		bx	lr
+ 575              	.L31:
+ 576 0016 00BF     		.align	2
+ 577              	.L30:
+ 578 0018 00ED00E0 		.word	-536810240
+ 579              		.cfi_endproc
+ 580              	.LFE147:
+ 582              		.section	.text.HAL_MPU_Enable,"ax",%progbits
+ 583              		.align	1
+ 584              		.global	HAL_MPU_Enable
+ 585              		.syntax unified
+ 586              		.thumb
+ 587              		.thumb_func
+ 588              		.fpu fpv5-d16
+ 590              	HAL_MPU_Enable:
+ 591              	.LVL38:
+ 592              	.LFB148:
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Enables the MPU
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  MPU_Control Specifies the control mode of the MPU during hard fault, 
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *          NMI, FAULTMASK and privileged access to the default memory 
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *          This parameter can be one of the following values:
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *            @arg MPU_HFNMI_PRIVDEF_NONE
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *            @arg MPU_HARDFAULT_NMI
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *            @arg MPU_PRIVILEGED_DEFAULT
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *            @arg MPU_HFNMI_PRIVDEF
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control)
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 593              		.loc 1 281 1 is_stmt 1 view -0
+ 594              		.cfi_startproc
+ 595              		@ args = 0, pretend = 0, frame = 0
+ 596              		@ frame_needed = 0, uses_anonymous_args = 0
+ 597              		@ link register save eliminated.
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Enable the MPU */
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+ARM GAS  /tmp/ccs1e2mJ.s 			page 78
+
+
+ 598              		.loc 1 283 3 view .LVU155
+ 599              		.loc 1 283 27 is_stmt 0 view .LVU156
+ 600 0000 40F00100 		orr	r0, r0, #1
+ 601              	.LVL39:
+ 602              		.loc 1 283 13 view .LVU157
+ 603 0004 054B     		ldr	r3, .L33
+ 604 0006 C3F89400 		str	r0, [r3, #148]
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Enable fault exceptions */
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+ 605              		.loc 1 286 3 is_stmt 1 view .LVU158
+ 606              		.loc 1 286 14 is_stmt 0 view .LVU159
+ 607 000a 5A6A     		ldr	r2, [r3, #36]
+ 608 000c 42F48032 		orr	r2, r2, #65536
+ 609 0010 5A62     		str	r2, [r3, #36]
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Ensure MPU setting take effects */
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   __DSB();
+ 610              		.loc 1 289 3 is_stmt 1 view .LVU160
+ 611              	.LBB88:
+ 612              	.LBI88:
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 613              		.loc 3 877 27 view .LVU161
+ 614              	.LBB89:
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 615              		.loc 3 879 3 view .LVU162
+ 616              		.syntax unified
+ 617              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 618 0012 BFF34F8F 		dsb 0xF
+ 619              	@ 0 "" 2
+ 620              		.thumb
+ 621              		.syntax unified
+ 622              	.LBE89:
+ 623              	.LBE88:
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   __ISB();
+ 624              		.loc 1 290 3 view .LVU163
+ 625              	.LBB90:
+ 626              	.LBI90:
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 627              		.loc 3 866 27 view .LVU164
+ 628              	.LBB91:
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 629              		.loc 3 868 3 view .LVU165
+ 630              		.syntax unified
+ 631              	@ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 632 0016 BFF36F8F 		isb 0xF
+ 633              	@ 0 "" 2
+ 634              		.thumb
+ 635              		.syntax unified
+ 636              	.LBE91:
+ 637              	.LBE90:
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 638              		.loc 1 291 1 is_stmt 0 view .LVU166
+ 639 001a 7047     		bx	lr
+ 640              	.L34:
+ 641              		.align	2
+ 642              	.L33:
+ARM GAS  /tmp/ccs1e2mJ.s 			page 79
+
+
+ 643 001c 00ED00E0 		.word	-536810240
+ 644              		.cfi_endproc
+ 645              	.LFE148:
+ 647              		.section	.text.HAL_MPU_EnableRegion,"ax",%progbits
+ 648              		.align	1
+ 649              		.global	HAL_MPU_EnableRegion
+ 650              		.syntax unified
+ 651              		.thumb
+ 652              		.thumb_func
+ 653              		.fpu fpv5-d16
+ 655              	HAL_MPU_EnableRegion:
+ 656              	.LVL40:
+ 657              	.LFB149:
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Enables the MPU Region.
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 658              		.loc 1 298 1 is_stmt 1 view -0
+ 659              		.cfi_startproc
+ 660              		@ args = 0, pretend = 0, frame = 0
+ 661              		@ frame_needed = 0, uses_anonymous_args = 0
+ 662              		@ link register save eliminated.
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+ 663              		.loc 1 300 3 view .LVU168
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Set the Region number */
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   MPU->RNR = RegionNumber;
+ 664              		.loc 1 303 3 view .LVU169
+ 665              		.loc 1 303 12 is_stmt 0 view .LVU170
+ 666 0000 044B     		ldr	r3, .L36
+ 667 0002 C3F89800 		str	r0, [r3, #152]
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Enable the Region */
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+ 668              		.loc 1 306 3 is_stmt 1 view .LVU171
+ 669 0006 D3F8A020 		ldr	r2, [r3, #160]
+ 670 000a 42F00102 		orr	r2, r2, #1
+ 671 000e C3F8A020 		str	r2, [r3, #160]
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 672              		.loc 1 307 1 is_stmt 0 view .LVU172
+ 673 0012 7047     		bx	lr
+ 674              	.L37:
+ 675              		.align	2
+ 676              	.L36:
+ 677 0014 00ED00E0 		.word	-536810240
+ 678              		.cfi_endproc
+ 679              	.LFE149:
+ 681              		.section	.text.HAL_MPU_DisableRegion,"ax",%progbits
+ 682              		.align	1
+ 683              		.global	HAL_MPU_DisableRegion
+ 684              		.syntax unified
+ 685              		.thumb
+ 686              		.thumb_func
+ARM GAS  /tmp/ccs1e2mJ.s 			page 80
+
+
+ 687              		.fpu fpv5-d16
+ 689              	HAL_MPU_DisableRegion:
+ 690              	.LVL41:
+ 691              	.LFB150:
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Disables the MPU Region.
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 692              		.loc 1 314 1 is_stmt 1 view -0
+ 693              		.cfi_startproc
+ 694              		@ args = 0, pretend = 0, frame = 0
+ 695              		@ frame_needed = 0, uses_anonymous_args = 0
+ 696              		@ link register save eliminated.
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+ 697              		.loc 1 316 3 view .LVU174
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Set the Region number */
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   MPU->RNR = RegionNumber;
+ 698              		.loc 1 319 3 view .LVU175
+ 699              		.loc 1 319 12 is_stmt 0 view .LVU176
+ 700 0000 044B     		ldr	r3, .L39
+ 701 0002 C3F89800 		str	r0, [r3, #152]
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Disable the Region */
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+ 702              		.loc 1 322 3 is_stmt 1 view .LVU177
+ 703 0006 D3F8A020 		ldr	r2, [r3, #160]
+ 704 000a 22F00102 		bic	r2, r2, #1
+ 705 000e C3F8A020 		str	r2, [r3, #160]
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 706              		.loc 1 323 1 is_stmt 0 view .LVU178
+ 707 0012 7047     		bx	lr
+ 708              	.L40:
+ 709              		.align	2
+ 710              	.L39:
+ 711 0014 00ED00E0 		.word	-536810240
+ 712              		.cfi_endproc
+ 713              	.LFE150:
+ 715              		.section	.text.HAL_MPU_ConfigRegion,"ax",%progbits
+ 716              		.align	1
+ 717              		.global	HAL_MPU_ConfigRegion
+ 718              		.syntax unified
+ 719              		.thumb
+ 720              		.thumb_func
+ 721              		.fpu fpv5-d16
+ 723              	HAL_MPU_ConfigRegion:
+ 724              	.LVL42:
+ 725              	.LFB151:
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Initializes and configures the Region and the memory to be protected.
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                the initialization and configuration information.
+ARM GAS  /tmp/ccs1e2mJ.s 			page 81
+
+
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 726              		.loc 1 332 1 is_stmt 1 view -0
+ 727              		.cfi_startproc
+ 728              		@ args = 0, pretend = 0, frame = 0
+ 729              		@ frame_needed = 0, uses_anonymous_args = 0
+ 730              		@ link register save eliminated.
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ 731              		.loc 1 334 3 view .LVU180
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+ 732              		.loc 1 335 3 view .LVU181
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ 733              		.loc 1 336 3 view .LVU182
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ 734              		.loc 1 337 3 view .LVU183
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ 735              		.loc 1 338 3 view .LVU184
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ 736              		.loc 1 339 3 view .LVU185
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ 737              		.loc 1 340 3 view .LVU186
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ 738              		.loc 1 341 3 view .LVU187
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ 739              		.loc 1 342 3 view .LVU188
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+ 740              		.loc 1 343 3 view .LVU189
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Set the Region number */
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   MPU->RNR = MPU_Init->Number;
+ 741              		.loc 1 346 3 view .LVU190
+ 742              		.loc 1 346 22 is_stmt 0 view .LVU191
+ 743 0000 4378     		ldrb	r3, [r0, #1]	@ zero_extendqisi2
+ 744              		.loc 1 346 12 view .LVU192
+ 745 0002 144A     		ldr	r2, .L42
+ 746 0004 C2F89830 		str	r3, [r2, #152]
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Disable the Region */
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+ 747              		.loc 1 349 3 is_stmt 1 view .LVU193
+ 748 0008 D2F8A030 		ldr	r3, [r2, #160]
+ 749 000c 23F00103 		bic	r3, r3, #1
+ 750 0010 C2F8A030 		str	r3, [r2, #160]
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Apply configuration */
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   MPU->RBAR = MPU_Init->BaseAddress;
+ 751              		.loc 1 352 3 view .LVU194
+ 752              		.loc 1 352 23 is_stmt 0 view .LVU195
+ 753 0014 4368     		ldr	r3, [r0, #4]
+ 754              		.loc 1 352 13 view .LVU196
+ 755 0016 C2F89C30 		str	r3, [r2, #156]
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+ 756              		.loc 1 353 3 is_stmt 1 view .LVU197
+ 757              		.loc 1 353 34 is_stmt 0 view .LVU198
+ARM GAS  /tmp/ccs1e2mJ.s 			page 82
+
+
+ 758 001a 017B     		ldrb	r1, [r0, #12]	@ zero_extendqisi2
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+ 759              		.loc 1 354 34 view .LVU199
+ 760 001c C37A     		ldrb	r3, [r0, #11]	@ zero_extendqisi2
+ 761              		.loc 1 354 60 view .LVU200
+ 762 001e 1B06     		lsls	r3, r3, #24
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+ 763              		.loc 1 353 82 view .LVU201
+ 764 0020 43EA0173 		orr	r3, r3, r1, lsl #28
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+ 765              		.loc 1 355 34 view .LVU202
+ 766 0024 817A     		ldrb	r1, [r0, #10]	@ zero_extendqisi2
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+ 767              		.loc 1 354 82 view .LVU203
+ 768 0026 43EAC143 		orr	r3, r3, r1, lsl #19
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+ 769              		.loc 1 356 34 view .LVU204
+ 770 002a 417B     		ldrb	r1, [r0, #13]	@ zero_extendqisi2
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+ 771              		.loc 1 355 82 view .LVU205
+ 772 002c 43EA8143 		orr	r3, r3, r1, lsl #18
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+ 773              		.loc 1 357 34 view .LVU206
+ 774 0030 817B     		ldrb	r1, [r0, #14]	@ zero_extendqisi2
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+ 775              		.loc 1 356 82 view .LVU207
+ 776 0032 43EA4143 		orr	r3, r3, r1, lsl #17
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+ 777              		.loc 1 358 34 view .LVU208
+ 778 0036 C17B     		ldrb	r1, [r0, #15]	@ zero_extendqisi2
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+ 779              		.loc 1 357 82 view .LVU209
+ 780 0038 43EA0143 		orr	r3, r3, r1, lsl #16
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+ 781              		.loc 1 359 34 view .LVU210
+ 782 003c 417A     		ldrb	r1, [r0, #9]	@ zero_extendqisi2
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+ 783              		.loc 1 358 82 view .LVU211
+ 784 003e 43EA0123 		orr	r3, r3, r1, lsl #8
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+ 785              		.loc 1 360 34 view .LVU212
+ 786 0042 017A     		ldrb	r1, [r0, #8]	@ zero_extendqisi2
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+ 787              		.loc 1 359 82 view .LVU213
+ 788 0044 43EA4103 		orr	r3, r3, r1, lsl #1
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+ 789              		.loc 1 361 34 view .LVU214
+ 790 0048 0178     		ldrb	r1, [r0]	@ zero_extendqisi2
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+ 791              		.loc 1 360 82 view .LVU215
+ 792 004a 0B43     		orrs	r3, r3, r1
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****               ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+ 793              		.loc 1 353 13 view .LVU216
+ 794 004c C2F8A030 		str	r3, [r2, #160]
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 795              		.loc 1 362 1 view .LVU217
+ 796 0050 7047     		bx	lr
+ARM GAS  /tmp/ccs1e2mJ.s 			page 83
+
+
+ 797              	.L43:
+ 798 0052 00BF     		.align	2
+ 799              	.L42:
+ 800 0054 00ED00E0 		.word	-536810240
+ 801              		.cfi_endproc
+ 802              	.LFE151:
+ 804              		.section	.text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits
+ 805              		.align	1
+ 806              		.global	HAL_NVIC_GetPriorityGrouping
+ 807              		.syntax unified
+ 808              		.thumb
+ 809              		.thumb_func
+ 810              		.fpu fpv5-d16
+ 812              	HAL_NVIC_GetPriorityGrouping:
+ 813              	.LFB152:
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** #endif /* __MPU_PRESENT */
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void)
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 814              		.loc 1 370 1 is_stmt 1 view -0
+ 815              		.cfi_startproc
+ 816              		@ args = 0, pretend = 0, frame = 0
+ 817              		@ frame_needed = 0, uses_anonymous_args = 0
+ 818              		@ link register save eliminated.
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Get the PRIGROUP[10:8] field value */
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   return NVIC_GetPriorityGrouping();
+ 819              		.loc 1 372 3 view .LVU219
+ 820              	.LBB92:
+ 821              	.LBI92:
+1884:Drivers/CMSIS/Include/core_cm7.h **** {
+ 822              		.loc 2 1884 26 view .LVU220
+ 823              	.LBB93:
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 824              		.loc 2 1886 3 view .LVU221
+1886:Drivers/CMSIS/Include/core_cm7.h **** }
+ 825              		.loc 2 1886 26 is_stmt 0 view .LVU222
+ 826 0000 024B     		ldr	r3, .L45
+ 827 0002 D868     		ldr	r0, [r3, #12]
+ 828              	.LBE93:
+ 829              	.LBE92:
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 830              		.loc 1 373 1 view .LVU223
+ 831 0004 C0F30220 		ubfx	r0, r0, #8, #3
+ 832 0008 7047     		bx	lr
+ 833              	.L46:
+ 834 000a 00BF     		.align	2
+ 835              	.L45:
+ 836 000c 00ED00E0 		.word	-536810240
+ 837              		.cfi_endproc
+ 838              	.LFE152:
+ 840              		.section	.text.HAL_NVIC_GetPriority,"ax",%progbits
+ 841              		.align	1
+ 842              		.global	HAL_NVIC_GetPriority
+ARM GAS  /tmp/ccs1e2mJ.s 			page 84
+
+
+ 843              		.syntax unified
+ 844              		.thumb
+ 845              		.thumb_func
+ 846              		.fpu fpv5-d16
+ 848              	HAL_NVIC_GetPriority:
+ 849              	.LVL43:
+ 850              	.LFB153:
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Gets the priority of an interrupt.
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param   PriorityGroup the priority grouping bits length.
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         This parameter can be one of the following values:
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                                      4 bits for subpriority
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                                      3 bits for subpriority
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                                      2 bits for subpriority
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                                      1 bits for subpriority
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                                      0 bits for subpriority
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint3
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 851              		.loc 1 397 1 is_stmt 1 view -0
+ 852              		.cfi_startproc
+ 853              		@ args = 0, pretend = 0, frame = 0
+ 854              		@ frame_needed = 0, uses_anonymous_args = 0
+ 855              		.loc 1 397 1 is_stmt 0 view .LVU225
+ 856 0000 10B5     		push	{r4, lr}
+ 857              	.LCFI1:
+ 858              		.cfi_def_cfa_offset 8
+ 859              		.cfi_offset 4, -8
+ 860              		.cfi_offset 14, -4
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ 861              		.loc 1 399 3 is_stmt 1 view .LVU226
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****  /* Get priority for Cortex-M system or device specific interrupts */
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+ 862              		.loc 1 401 3 view .LVU227
+ 863              	.LVL44:
+ 864              	.LBB98:
+ 865              	.LBI98:
+2046:Drivers/CMSIS/Include/core_cm7.h **** {
+ 866              		.loc 2 2046 26 view .LVU228
+ 867              	.LBB99:
+2049:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 868              		.loc 2 2049 3 view .LVU229
+2049:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 869              		.loc 2 2049 6 is_stmt 0 view .LVU230
+ARM GAS  /tmp/ccs1e2mJ.s 			page 85
+
+
+ 870 0002 0028     		cmp	r0, #0
+ 871              	.LVL45:
+2049:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 872              		.loc 2 2049 6 view .LVU231
+ 873 0004 1EDB     		blt	.L48
+2051:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 874              		.loc 2 2051 5 is_stmt 1 view .LVU232
+2051:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 875              		.loc 2 2051 31 is_stmt 0 view .LVU233
+ 876 0006 134C     		ldr	r4, .L53
+ 877 0008 205C     		ldrb	r0, [r4, r0]	@ zero_extendqisi2
+2051:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 878              		.loc 2 2051 65 view .LVU234
+ 879 000a 0009     		lsrs	r0, r0, #4
+ 880              	.L49:
+ 881              	.LVL46:
+2051:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 882              		.loc 2 2051 65 view .LVU235
+ 883              	.LBE99:
+ 884              	.LBE98:
+ 885              	.LBB101:
+ 886              	.LBI101:
+2098:Drivers/CMSIS/Include/core_cm7.h **** {
+ 887              		.loc 2 2098 22 is_stmt 1 view .LVU236
+ 888              	.LBB102:
+2100:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t PreemptPriorityBits;
+ 889              		.loc 2 2100 3 view .LVU237
+2100:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t PreemptPriorityBits;
+ 890              		.loc 2 2100 12 is_stmt 0 view .LVU238
+ 891 000c 01F00701 		and	r1, r1, #7
+ 892              	.LVL47:
+2101:Drivers/CMSIS/Include/core_cm7.h ****   uint32_t SubPriorityBits;
+ 893              		.loc 2 2101 3 is_stmt 1 view .LVU239
+2102:Drivers/CMSIS/Include/core_cm7.h **** 
+ 894              		.loc 2 2102 3 view .LVU240
+2104:Drivers/CMSIS/Include/core_cm7.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+ 895              		.loc 2 2104 3 view .LVU241
+2104:Drivers/CMSIS/Include/core_cm7.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+ 896              		.loc 2 2104 31 is_stmt 0 view .LVU242
+ 897 0010 C1F1070C 		rsb	ip, r1, #7
+2104:Drivers/CMSIS/Include/core_cm7.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+ 898              		.loc 2 2104 23 view .LVU243
+ 899 0014 BCF1040F 		cmp	ip, #4
+ 900 0018 28BF     		it	cs
+ 901 001a 4FF0040C 		movcs	ip, #4
+ 902              	.LVL48:
+2105:Drivers/CMSIS/Include/core_cm7.h **** 
+ 903              		.loc 2 2105 3 is_stmt 1 view .LVU244
+2105:Drivers/CMSIS/Include/core_cm7.h **** 
+ 904              		.loc 2 2105 44 is_stmt 0 view .LVU245
+ 905 001e 0C1D     		adds	r4, r1, #4
+2105:Drivers/CMSIS/Include/core_cm7.h **** 
+ 906              		.loc 2 2105 109 view .LVU246
+ 907 0020 062C     		cmp	r4, #6
+ 908 0022 15D9     		bls	.L51
+ 909 0024 0339     		subs	r1, r1, #3
+ 910              	.LVL49:
+ARM GAS  /tmp/ccs1e2mJ.s 			page 86
+
+
+ 911              	.L50:
+2107:Drivers/CMSIS/Include/core_cm7.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
+ 912              		.loc 2 2107 3 is_stmt 1 view .LVU247
+2107:Drivers/CMSIS/Include/core_cm7.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
+ 913              		.loc 2 2107 33 is_stmt 0 view .LVU248
+ 914 0026 20FA01F4 		lsr	r4, r0, r1
+ 915              	.LVL50:
+2107:Drivers/CMSIS/Include/core_cm7.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
+ 916              		.loc 2 2107 53 view .LVU249
+ 917 002a 4FF0FF3E 		mov	lr, #-1
+ 918 002e 0EFA0CFC 		lsl	ip, lr, ip
+ 919              	.LVL51:
+2107:Drivers/CMSIS/Include/core_cm7.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
+ 920              		.loc 2 2107 53 view .LVU250
+ 921 0032 24EA0C04 		bic	r4, r4, ip
+2107:Drivers/CMSIS/Include/core_cm7.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
+ 922              		.loc 2 2107 21 view .LVU251
+ 923 0036 1460     		str	r4, [r2]
+2108:Drivers/CMSIS/Include/core_cm7.h **** }
+ 924              		.loc 2 2108 3 is_stmt 1 view .LVU252
+2108:Drivers/CMSIS/Include/core_cm7.h **** }
+ 925              		.loc 2 2108 53 is_stmt 0 view .LVU253
+ 926 0038 0EFA01F1 		lsl	r1, lr, r1
+ 927              	.LVL52:
+2108:Drivers/CMSIS/Include/core_cm7.h **** }
+ 928              		.loc 2 2108 53 view .LVU254
+ 929 003c 20EA0100 		bic	r0, r0, r1
+ 930              	.LVL53:
+2108:Drivers/CMSIS/Include/core_cm7.h **** }
+ 931              		.loc 2 2108 21 view .LVU255
+ 932 0040 1860     		str	r0, [r3]
+ 933              	.LVL54:
+2108:Drivers/CMSIS/Include/core_cm7.h **** }
+ 934              		.loc 2 2108 21 view .LVU256
+ 935              	.LBE102:
+ 936              	.LBE101:
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 937              		.loc 1 402 1 view .LVU257
+ 938 0042 10BD     		pop	{r4, pc}
+ 939              	.LVL55:
+ 940              	.L48:
+ 941              	.LBB104:
+ 942              	.LBB100:
+2055:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 943              		.loc 2 2055 5 is_stmt 1 view .LVU258
+2055:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 944              		.loc 2 2055 51 is_stmt 0 view .LVU259
+ 945 0044 00F00F00 		and	r0, r0, #15
+2055:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 946              		.loc 2 2055 32 view .LVU260
+ 947 0048 034C     		ldr	r4, .L53+4
+ 948 004a 205C     		ldrb	r0, [r4, r0]	@ zero_extendqisi2
+2055:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 949              		.loc 2 2055 65 view .LVU261
+ 950 004c 0009     		lsrs	r0, r0, #4
+ 951 004e DDE7     		b	.L49
+ 952              	.LVL56:
+ARM GAS  /tmp/ccs1e2mJ.s 			page 87
+
+
+ 953              	.L51:
+2055:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 954              		.loc 2 2055 65 view .LVU262
+ 955              	.LBE100:
+ 956              	.LBE104:
+ 957              	.LBB105:
+ 958              	.LBB103:
+2105:Drivers/CMSIS/Include/core_cm7.h **** 
+ 959              		.loc 2 2105 109 view .LVU263
+ 960 0050 0021     		movs	r1, #0
+ 961              	.LVL57:
+2105:Drivers/CMSIS/Include/core_cm7.h **** 
+ 962              		.loc 2 2105 109 view .LVU264
+ 963 0052 E8E7     		b	.L50
+ 964              	.L54:
+ 965              		.align	2
+ 966              	.L53:
+ 967 0054 00E400E0 		.word	-536812544
+ 968 0058 14ED00E0 		.word	-536810220
+ 969              	.LBE103:
+ 970              	.LBE105:
+ 971              		.cfi_endproc
+ 972              	.LFE153:
+ 974              		.section	.text.HAL_NVIC_SetPendingIRQ,"ax",%progbits
+ 975              		.align	1
+ 976              		.global	HAL_NVIC_SetPendingIRQ
+ 977              		.syntax unified
+ 978              		.thumb
+ 979              		.thumb_func
+ 980              		.fpu fpv5-d16
+ 982              	HAL_NVIC_SetPendingIRQ:
+ 983              	.LVL58:
+ 984              	.LFB154:
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Sets Pending bit of an external interrupt.
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  IRQn External interrupt number
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 985              		.loc 1 412 1 is_stmt 1 view -0
+ 986              		.cfi_startproc
+ 987              		@ args = 0, pretend = 0, frame = 0
+ 988              		@ frame_needed = 0, uses_anonymous_args = 0
+ 989              		@ link register save eliminated.
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+ 990              		.loc 1 414 3 view .LVU266
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Set interrupt pending */
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   NVIC_SetPendingIRQ(IRQn);
+ 991              		.loc 1 417 3 view .LVU267
+ 992              	.LBB106:
+ 993              	.LBI106:
+ARM GAS  /tmp/ccs1e2mJ.s 			page 88
+
+
+1970:Drivers/CMSIS/Include/core_cm7.h **** {
+ 994              		.loc 2 1970 22 view .LVU268
+ 995              	.LBB107:
+1972:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 996              		.loc 2 1972 3 view .LVU269
+1972:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 997              		.loc 2 1972 6 is_stmt 0 view .LVU270
+ 998 0000 0028     		cmp	r0, #0
+ 999              	.LVL59:
+1972:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 1000              		.loc 2 1972 6 view .LVU271
+ 1001 0002 08DB     		blt	.L55
+1974:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1002              		.loc 2 1974 5 is_stmt 1 view .LVU272
+1974:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1003              		.loc 2 1974 81 is_stmt 0 view .LVU273
+ 1004 0004 00F01F02 		and	r2, r0, #31
+1974:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1005              		.loc 2 1974 34 view .LVU274
+ 1006 0008 4009     		lsrs	r0, r0, #5
+1974:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1007              		.loc 2 1974 45 view .LVU275
+ 1008 000a 0123     		movs	r3, #1
+ 1009 000c 9340     		lsls	r3, r3, r2
+1974:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1010              		.loc 2 1974 43 view .LVU276
+ 1011 000e 4030     		adds	r0, r0, #64
+ 1012 0010 014A     		ldr	r2, .L57
+ 1013 0012 42F82030 		str	r3, [r2, r0, lsl #2]
+ 1014              	.LVL60:
+ 1015              	.L55:
+1974:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1016              		.loc 2 1974 43 view .LVU277
+ 1017              	.LBE107:
+ 1018              	.LBE106:
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 1019              		.loc 1 418 1 view .LVU278
+ 1020 0016 7047     		bx	lr
+ 1021              	.L58:
+ 1022              		.align	2
+ 1023              	.L57:
+ 1024 0018 00E100E0 		.word	-536813312
+ 1025              		.cfi_endproc
+ 1026              	.LFE154:
+ 1028              		.section	.text.HAL_NVIC_GetPendingIRQ,"ax",%progbits
+ 1029              		.align	1
+ 1030              		.global	HAL_NVIC_GetPendingIRQ
+ 1031              		.syntax unified
+ 1032              		.thumb
+ 1033              		.thumb_func
+ 1034              		.fpu fpv5-d16
+ 1036              	HAL_NVIC_GetPendingIRQ:
+ 1037              	.LVL61:
+ 1038              	.LFB155:
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Gets Pending Interrupt (reads the pending register in the NVIC 
+ARM GAS  /tmp/ccs1e2mJ.s 			page 89
+
+
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         and returns the pending bit for the specified interrupt).
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *          This parameter can be an enumerator of IRQn_Type enumeration
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval status: - 0  Interrupt status is not pending.
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                 - 1  Interrupt status is pending.
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 1039              		.loc 1 430 1 is_stmt 1 view -0
+ 1040              		.cfi_startproc
+ 1041              		@ args = 0, pretend = 0, frame = 0
+ 1042              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1043              		@ link register save eliminated.
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+ 1044              		.loc 1 432 3 view .LVU280
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Return 1 if pending else 0 */
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   return NVIC_GetPendingIRQ(IRQn);
+ 1045              		.loc 1 435 3 view .LVU281
+ 1046              	.LBB108:
+ 1047              	.LBI108:
+1951:Drivers/CMSIS/Include/core_cm7.h **** {
+ 1048              		.loc 2 1951 26 view .LVU282
+ 1049              	.LBB109:
+1953:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 1050              		.loc 2 1953 3 view .LVU283
+1953:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 1051              		.loc 2 1953 6 is_stmt 0 view .LVU284
+ 1052 0000 0028     		cmp	r0, #0
+ 1053              	.LVL62:
+1953:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 1054              		.loc 2 1953 6 view .LVU285
+ 1055 0002 0BDB     		blt	.L61
+1955:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1056              		.loc 2 1955 5 is_stmt 1 view .LVU286
+1955:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1057              		.loc 2 1955 54 is_stmt 0 view .LVU287
+ 1058 0004 4309     		lsrs	r3, r0, #5
+1955:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1059              		.loc 2 1955 35 view .LVU288
+ 1060 0006 4033     		adds	r3, r3, #64
+ 1061 0008 054A     		ldr	r2, .L62
+ 1062 000a 52F82330 		ldr	r3, [r2, r3, lsl #2]
+1955:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1063              		.loc 2 1955 91 view .LVU289
+ 1064 000e 00F01F00 		and	r0, r0, #31
+1955:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1065              		.loc 2 1955 103 view .LVU290
+ 1066 0012 23FA00F0 		lsr	r0, r3, r0
+1955:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1067              		.loc 2 1955 12 view .LVU291
+ 1068 0016 00F00100 		and	r0, r0, #1
+ 1069 001a 7047     		bx	lr
+ 1070              	.L61:
+1959:Drivers/CMSIS/Include/core_cm7.h ****   }
+ARM GAS  /tmp/ccs1e2mJ.s 			page 90
+
+
+ 1071              		.loc 2 1959 11 view .LVU292
+ 1072 001c 0020     		movs	r0, #0
+ 1073              	.LVL63:
+1959:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1074              		.loc 2 1959 11 view .LVU293
+ 1075              	.LBE109:
+ 1076              	.LBE108:
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 1077              		.loc 1 436 1 view .LVU294
+ 1078 001e 7047     		bx	lr
+ 1079              	.L63:
+ 1080              		.align	2
+ 1081              	.L62:
+ 1082 0020 00E100E0 		.word	-536813312
+ 1083              		.cfi_endproc
+ 1084              	.LFE155:
+ 1086              		.section	.text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits
+ 1087              		.align	1
+ 1088              		.global	HAL_NVIC_ClearPendingIRQ
+ 1089              		.syntax unified
+ 1090              		.thumb
+ 1091              		.thumb_func
+ 1092              		.fpu fpv5-d16
+ 1094              	HAL_NVIC_ClearPendingIRQ:
+ 1095              	.LVL64:
+ 1096              	.LFB156:
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Clears the pending bit of an external interrupt.
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 1097              		.loc 1 446 1 is_stmt 1 view -0
+ 1098              		.cfi_startproc
+ 1099              		@ args = 0, pretend = 0, frame = 0
+ 1100              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1101              		@ link register save eliminated.
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+ 1102              		.loc 1 448 3 view .LVU296
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Clear pending interrupt */
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   NVIC_ClearPendingIRQ(IRQn);
+ 1103              		.loc 1 451 3 view .LVU297
+ 1104              	.LBB110:
+ 1105              	.LBI110:
+1985:Drivers/CMSIS/Include/core_cm7.h **** {
+ 1106              		.loc 2 1985 22 view .LVU298
+ 1107              	.LBB111:
+1987:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 1108              		.loc 2 1987 3 view .LVU299
+1987:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 1109              		.loc 2 1987 6 is_stmt 0 view .LVU300
+ARM GAS  /tmp/ccs1e2mJ.s 			page 91
+
+
+ 1110 0000 0028     		cmp	r0, #0
+ 1111              	.LVL65:
+1987:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 1112              		.loc 2 1987 6 view .LVU301
+ 1113 0002 08DB     		blt	.L64
+1989:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1114              		.loc 2 1989 5 is_stmt 1 view .LVU302
+1989:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1115              		.loc 2 1989 81 is_stmt 0 view .LVU303
+ 1116 0004 00F01F02 		and	r2, r0, #31
+1989:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1117              		.loc 2 1989 34 view .LVU304
+ 1118 0008 4009     		lsrs	r0, r0, #5
+1989:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1119              		.loc 2 1989 45 view .LVU305
+ 1120 000a 0123     		movs	r3, #1
+ 1121 000c 9340     		lsls	r3, r3, r2
+1989:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1122              		.loc 2 1989 43 view .LVU306
+ 1123 000e 6030     		adds	r0, r0, #96
+ 1124 0010 014A     		ldr	r2, .L66
+ 1125 0012 42F82030 		str	r3, [r2, r0, lsl #2]
+ 1126              	.LVL66:
+ 1127              	.L64:
+1989:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1128              		.loc 2 1989 43 view .LVU307
+ 1129              	.LBE111:
+ 1130              	.LBE110:
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 1131              		.loc 1 452 1 view .LVU308
+ 1132 0016 7047     		bx	lr
+ 1133              	.L67:
+ 1134              		.align	2
+ 1135              	.L66:
+ 1136 0018 00E100E0 		.word	-536813312
+ 1137              		.cfi_endproc
+ 1138              	.LFE156:
+ 1140              		.section	.text.HAL_NVIC_GetActive,"ax",%progbits
+ 1141              		.align	1
+ 1142              		.global	HAL_NVIC_GetActive
+ 1143              		.syntax unified
+ 1144              		.thumb
+ 1145              		.thumb_func
+ 1146              		.fpu fpv5-d16
+ 1148              	HAL_NVIC_GetActive:
+ 1149              	.LVL67:
+ 1150              	.LFB157:
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param IRQn External interrupt number
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval status: - 0  Interrupt status is not pending.
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *                 - 1  Interrupt status is pending.
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+ARM GAS  /tmp/ccs1e2mJ.s 			page 92
+
+
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 1151              		.loc 1 463 1 is_stmt 1 view -0
+ 1152              		.cfi_startproc
+ 1153              		@ args = 0, pretend = 0, frame = 0
+ 1154              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1155              		@ link register save eliminated.
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+ 1156              		.loc 1 465 3 view .LVU310
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Return 1 if active else 0 */
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   return NVIC_GetActive(IRQn);
+ 1157              		.loc 1 468 3 view .LVU311
+ 1158              	.LBB112:
+ 1159              	.LBI112:
+2002:Drivers/CMSIS/Include/core_cm7.h **** {
+ 1160              		.loc 2 2002 26 view .LVU312
+ 1161              	.LBB113:
+2004:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 1162              		.loc 2 2004 3 view .LVU313
+2004:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 1163              		.loc 2 2004 6 is_stmt 0 view .LVU314
+ 1164 0000 0028     		cmp	r0, #0
+ 1165              	.LVL68:
+2004:Drivers/CMSIS/Include/core_cm7.h ****   {
+ 1166              		.loc 2 2004 6 view .LVU315
+ 1167 0002 0BDB     		blt	.L70
+2006:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1168              		.loc 2 2006 5 is_stmt 1 view .LVU316
+2006:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1169              		.loc 2 2006 54 is_stmt 0 view .LVU317
+ 1170 0004 4309     		lsrs	r3, r0, #5
+2006:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1171              		.loc 2 2006 35 view .LVU318
+ 1172 0006 8033     		adds	r3, r3, #128
+ 1173 0008 054A     		ldr	r2, .L71
+ 1174 000a 52F82330 		ldr	r3, [r2, r3, lsl #2]
+2006:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1175              		.loc 2 2006 91 view .LVU319
+ 1176 000e 00F01F00 		and	r0, r0, #31
+2006:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1177              		.loc 2 2006 103 view .LVU320
+ 1178 0012 23FA00F0 		lsr	r0, r3, r0
+2006:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1179              		.loc 2 2006 12 view .LVU321
+ 1180 0016 00F00100 		and	r0, r0, #1
+ 1181 001a 7047     		bx	lr
+ 1182              	.L70:
+2010:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1183              		.loc 2 2010 11 view .LVU322
+ 1184 001c 0020     		movs	r0, #0
+ 1185              	.LVL69:
+2010:Drivers/CMSIS/Include/core_cm7.h ****   }
+ 1186              		.loc 2 2010 11 view .LVU323
+ 1187              	.LBE113:
+ 1188              	.LBE112:
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ARM GAS  /tmp/ccs1e2mJ.s 			page 93
+
+
+ 1189              		.loc 1 469 1 view .LVU324
+ 1190 001e 7047     		bx	lr
+ 1191              	.L72:
+ 1192              		.align	2
+ 1193              	.L71:
+ 1194 0020 00E100E0 		.word	-536813312
+ 1195              		.cfi_endproc
+ 1196              	.LFE157:
+ 1198              		.section	.text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits
+ 1199              		.align	1
+ 1200              		.global	HAL_SYSTICK_CLKSourceConfig
+ 1201              		.syntax unified
+ 1202              		.thumb
+ 1203              		.thumb_func
+ 1204              		.fpu fpv5-d16
+ 1206              	HAL_SYSTICK_CLKSourceConfig:
+ 1207              	.LVL70:
+ 1208              	.LFB158:
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  Configures the SysTick clock source.
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @param  CLKSource specifies the SysTick clock source.
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *          This parameter can be one of the following values:
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock 
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 1209              		.loc 1 480 1 is_stmt 1 view -0
+ 1210              		.cfi_startproc
+ 1211              		@ args = 0, pretend = 0, frame = 0
+ 1212              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1213              		@ link register save eliminated.
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* Check the parameters */
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ 1214              		.loc 1 482 3 view .LVU326
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+ 1215              		.loc 1 483 3 view .LVU327
+ 1216              		.loc 1 483 6 is_stmt 0 view .LVU328
+ 1217 0000 0428     		cmp	r0, #4
+ 1218 0002 06D0     		beq	.L76
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   {
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   }
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   else
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   {
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ 1219              		.loc 1 489 5 is_stmt 1 view .LVU329
+ 1220              		.loc 1 489 19 is_stmt 0 view .LVU330
+ 1221 0004 4FF0E022 		mov	r2, #-536813568
+ 1222 0008 1369     		ldr	r3, [r2, #16]
+ 1223 000a 23F00403 		bic	r3, r3, #4
+ 1224 000e 1361     		str	r3, [r2, #16]
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   }
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 1225              		.loc 1 491 1 view .LVU331
+ARM GAS  /tmp/ccs1e2mJ.s 			page 94
+
+
+ 1226 0010 7047     		bx	lr
+ 1227              	.L76:
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   }
+ 1228              		.loc 1 485 5 is_stmt 1 view .LVU332
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   }
+ 1229              		.loc 1 485 19 is_stmt 0 view .LVU333
+ 1230 0012 4FF0E022 		mov	r2, #-536813568
+ 1231 0016 1369     		ldr	r3, [r2, #16]
+ 1232 0018 43F00403 		orr	r3, r3, #4
+ 1233 001c 1361     		str	r3, [r2, #16]
+ 1234 001e 7047     		bx	lr
+ 1235              		.cfi_endproc
+ 1236              	.LFE158:
+ 1238              		.section	.text.HAL_SYSTICK_Callback,"ax",%progbits
+ 1239              		.align	1
+ 1240              		.weak	HAL_SYSTICK_Callback
+ 1241              		.syntax unified
+ 1242              		.thumb
+ 1243              		.thumb_func
+ 1244              		.fpu fpv5-d16
+ 1246              	HAL_SYSTICK_Callback:
+ 1247              	.LFB160:
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  This function handles SYSTICK interrupt request.
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void)
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   HAL_SYSTICK_Callback();
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @brief  SYSTICK callback.
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   * @retval None
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   */
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void)
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
+ 1248              		.loc 1 507 1 is_stmt 1 view -0
+ 1249              		.cfi_startproc
+ 1250              		@ args = 0, pretend = 0, frame = 0
+ 1251              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1252              		@ link register save eliminated.
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****             the HAL_SYSTICK_Callback could be implemented in the user file
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****    */
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 1253              		.loc 1 511 1 view .LVU335
+ 1254 0000 7047     		bx	lr
+ 1255              		.cfi_endproc
+ 1256              	.LFE160:
+ 1258              		.section	.text.HAL_SYSTICK_IRQHandler,"ax",%progbits
+ 1259              		.align	1
+ 1260              		.global	HAL_SYSTICK_IRQHandler
+ 1261              		.syntax unified
+ 1262              		.thumb
+ 1263              		.thumb_func
+ARM GAS  /tmp/ccs1e2mJ.s 			page 95
+
+
+ 1264              		.fpu fpv5-d16
+ 1266              	HAL_SYSTICK_IRQHandler:
+ 1267              	.LFB159:
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****   HAL_SYSTICK_Callback();
+ 1268              		.loc 1 498 1 view -0
+ 1269              		.cfi_startproc
+ 1270              		@ args = 0, pretend = 0, frame = 0
+ 1271              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1272 0000 08B5     		push	{r3, lr}
+ 1273              	.LCFI2:
+ 1274              		.cfi_def_cfa_offset 8
+ 1275              		.cfi_offset 3, -8
+ 1276              		.cfi_offset 14, -4
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
+ 1277              		.loc 1 499 3 view .LVU337
+ 1278 0002 FFF7FEFF 		bl	HAL_SYSTICK_Callback
+ 1279              	.LVL71:
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** 
+ 1280              		.loc 1 500 1 is_stmt 0 view .LVU338
+ 1281 0006 08BD     		pop	{r3, pc}
+ 1282              		.cfi_endproc
+ 1283              	.LFE159:
+ 1285              		.text
+ 1286              	.Letext0:
+ 1287              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 1288              		.file 5 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 1289              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h"
+ARM GAS  /tmp/ccs1e2mJ.s 			page 96
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_cortex.c
+     /tmp/ccs1e2mJ.s:17     .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:25     .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 HAL_NVIC_SetPriorityGrouping
+     /tmp/ccs1e2mJ.s:81     .text.HAL_NVIC_SetPriorityGrouping:000000000000001c $d
+     /tmp/ccs1e2mJ.s:87     .text.HAL_NVIC_SetPriority:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:94     .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority
+     /tmp/ccs1e2mJ.s:234    .text.HAL_NVIC_SetPriority:0000000000000060 $d
+     /tmp/ccs1e2mJ.s:241    .text.HAL_NVIC_EnableIRQ:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:248    .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ
+     /tmp/ccs1e2mJ.s:289    .text.HAL_NVIC_EnableIRQ:0000000000000018 $d
+     /tmp/ccs1e2mJ.s:294    .text.HAL_NVIC_DisableIRQ:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:301    .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ
+     /tmp/ccs1e2mJ.s:372    .text.HAL_NVIC_DisableIRQ:0000000000000020 $d
+     /tmp/ccs1e2mJ.s:377    .text.HAL_NVIC_SystemReset:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:384    .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset
+     /tmp/ccs1e2mJ.s:450    .text.HAL_NVIC_SystemReset:000000000000001c $d
+     /tmp/ccs1e2mJ.s:458    .text.HAL_SYSTICK_Config:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:465    .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config
+     /tmp/ccs1e2mJ.s:530    .text.HAL_SYSTICK_Config:0000000000000024 $d
+     /tmp/ccs1e2mJ.s:535    .text.HAL_MPU_Disable:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:542    .text.HAL_MPU_Disable:0000000000000000 HAL_MPU_Disable
+     /tmp/ccs1e2mJ.s:578    .text.HAL_MPU_Disable:0000000000000018 $d
+     /tmp/ccs1e2mJ.s:583    .text.HAL_MPU_Enable:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:590    .text.HAL_MPU_Enable:0000000000000000 HAL_MPU_Enable
+     /tmp/ccs1e2mJ.s:643    .text.HAL_MPU_Enable:000000000000001c $d
+     /tmp/ccs1e2mJ.s:648    .text.HAL_MPU_EnableRegion:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:655    .text.HAL_MPU_EnableRegion:0000000000000000 HAL_MPU_EnableRegion
+     /tmp/ccs1e2mJ.s:677    .text.HAL_MPU_EnableRegion:0000000000000014 $d
+     /tmp/ccs1e2mJ.s:682    .text.HAL_MPU_DisableRegion:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:689    .text.HAL_MPU_DisableRegion:0000000000000000 HAL_MPU_DisableRegion
+     /tmp/ccs1e2mJ.s:711    .text.HAL_MPU_DisableRegion:0000000000000014 $d
+     /tmp/ccs1e2mJ.s:716    .text.HAL_MPU_ConfigRegion:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:723    .text.HAL_MPU_ConfigRegion:0000000000000000 HAL_MPU_ConfigRegion
+     /tmp/ccs1e2mJ.s:800    .text.HAL_MPU_ConfigRegion:0000000000000054 $d
+     /tmp/ccs1e2mJ.s:805    .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:812    .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 HAL_NVIC_GetPriorityGrouping
+     /tmp/ccs1e2mJ.s:836    .text.HAL_NVIC_GetPriorityGrouping:000000000000000c $d
+     /tmp/ccs1e2mJ.s:841    .text.HAL_NVIC_GetPriority:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:848    .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority
+     /tmp/ccs1e2mJ.s:967    .text.HAL_NVIC_GetPriority:0000000000000054 $d
+     /tmp/ccs1e2mJ.s:975    .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:982    .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ
+     /tmp/ccs1e2mJ.s:1024   .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d
+     /tmp/ccs1e2mJ.s:1029   .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:1036   .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ
+     /tmp/ccs1e2mJ.s:1082   .text.HAL_NVIC_GetPendingIRQ:0000000000000020 $d
+     /tmp/ccs1e2mJ.s:1087   .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:1094   .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ
+     /tmp/ccs1e2mJ.s:1136   .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d
+     /tmp/ccs1e2mJ.s:1141   .text.HAL_NVIC_GetActive:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:1148   .text.HAL_NVIC_GetActive:0000000000000000 HAL_NVIC_GetActive
+     /tmp/ccs1e2mJ.s:1194   .text.HAL_NVIC_GetActive:0000000000000020 $d
+     /tmp/ccs1e2mJ.s:1199   .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:1206   .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig
+     /tmp/ccs1e2mJ.s:1239   .text.HAL_SYSTICK_Callback:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:1246   .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback
+ARM GAS  /tmp/ccs1e2mJ.s 			page 97
+
+
+     /tmp/ccs1e2mJ.s:1259   .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t
+     /tmp/ccs1e2mJ.s:1266   .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler
+
+NO UNDEFINED SYMBOLS
diff --git a/build/stm32f7xx_hal_cortex.o b/build/stm32f7xx_hal_cortex.o
new file mode 100644
index 0000000..93eb222
Binary files /dev/null and b/build/stm32f7xx_hal_cortex.o differ
diff --git a/build/stm32f7xx_hal_dma.d b/build/stm32f7xx_hal_dma.d
new file mode 100644
index 0000000..4086f6c
--- /dev/null
+++ b/build/stm32f7xx_hal_dma.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_dma.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_dma.lst b/build/stm32f7xx_hal_dma.lst
new file mode 100644
index 0000000..0a9fbb7
--- /dev/null
+++ b/build/stm32f7xx_hal_dma.lst
@@ -0,0 +1,4627 @@
+ARM GAS  /tmp/ccRPwCnE.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_dma.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.DMA_SetConfig,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	DMA_SetConfig:
+  25              	.LVL0:
+  26              	.LFB153:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @file    stm32f7xx_hal_dma.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief   DMA HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *    
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *          This file provides firmware functions to manage the following 
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *          functionalities of the Direct Memory Access (DMA) peripheral:
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *           + Initialization and de-initialization functions
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *           + IO operation functions
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *           + Peripheral State and errors functions
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   @verbatim     
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   ==============================================================================
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                         ##### How to use this driver #####
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   ==============================================================================
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   [..]
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****    (#) Enable and configure the peripheral to be connected to the DMA Stream
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****        (except for internal SRAM/FLASH memories: no initialization is 
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****        necessary) please refer to Reference manual for connection between peripherals
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****        and DMA requests.
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****    (#) For a given Stream, program the required configuration through the following parameters:
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****        Transfer Direction, Source and Destination data formats, 
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****        Circular, Normal or peripheral flow control mode, Stream Priority level, 
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****        Source and Destination Increment mode, FIFO mode and its Threshold (if needed), 
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****        Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****    -@-   Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****          __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      *** Polling mode IO operation ***
+ARM GAS  /tmp/ccRPwCnE.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      =================================
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     [..]
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****               address and destination address and the Length of data to be transferred.
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****               case a fixed Timeout can be configured by User depending from his application.
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           (+) Use HAL_DMA_Abort() function to abort the current transfer.
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      *** Interrupt mode IO operation ***
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      ===================================
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     [..]
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           (+) Select Callbacks functions using HAL_DMA_RegisterCallback()
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****               Source address and destination address and the Length of data to be transferred. In t
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****               case the DMA interrupt is configured 
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****               add his own function by customization of function pointer XferCpltCallback and 
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****               XferErrorCallback (i.e a member of DMA handle structure).
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     [..]
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of 
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****          detection.
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****            possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****            Half-Word data size for the peripheral to access its data register and set Word data siz
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****            for the Memory to gain in access time. Each two half words will be packed and written in
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****            a single access to a Word in the Memory).
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****            and Destination. In this case the Peripheral Data Size will be applied to both Source
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****            and Destination.
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      *** DMA HAL driver macros list ***
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      =============================================
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      [..]
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****        Below the list of most used macros in DMA HAL driver.
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****        
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      [..]
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       (@) You can refer to the DMA HAL driver header file for more useful macros
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   @endverbatim
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   ******************************************************************************
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @attention
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * Copyright (c) 2017 STMicroelectronics.
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * All rights reserved.
+ARM GAS  /tmp/ccRPwCnE.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * the root directory of this software component.
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   ******************************************************************************
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */ 
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Includes ------------------------------------------------------------------*/
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** #include "stm32f7xx_hal.h"
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @addtogroup STM32F7xx_HAL_Driver
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @{
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @defgroup DMA DMA
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief DMA HAL module driver
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @{
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** #ifdef HAL_DMA_MODULE_ENABLED
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Private types -------------------------------------------------------------*/
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** typedef struct
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __IO uint32_t ISR;   /*!< DMA interrupt status register */
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __IO uint32_t Reserved0;
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } DMA_Base_Registers;
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Private variables ---------------------------------------------------------*/
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Private constants ---------------------------------------------------------*/
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @addtogroup DMA_Private_Constants
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****  * @{
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****  */
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****  #define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)5)  /* 5 ms */
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @}
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Private macros ------------------------------------------------------------*/
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Private functions ---------------------------------------------------------*/
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @addtogroup DMA_Private_Functions
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @{
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @}
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */  
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Exported functions ---------------------------------------------------------*/
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @{
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ARM GAS  /tmp/ccRPwCnE.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions_Group1
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** @verbatim
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****  ===============================================================================
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****              ##### Initialization and de-initialization functions  #####
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****  ===============================================================================
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     [..]
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     This section provides functions allowing to initialize the DMA Stream source
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     and destination addresses, incrementation and data sizes, transfer direction, 
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     [..]
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     reference manual.
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** @endverbatim
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @{
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Initialize the DMA according to the specified
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *         parameters in the DMA_InitTypeDef and create the associated handle.
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *               the configuration information for the specified DMA Stream.  
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL status
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = 0U;
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tickstart = HAL_GetTick();
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   DMA_Base_Registers *regs;
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Check the DMA peripheral state */
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma == NULL)
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Check the parameters */
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      when FIFO mode is enabled */
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ARM GAS  /tmp/ccRPwCnE.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Change DMA peripheral state */
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->State = HAL_DMA_STATE_BUSY;
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Allocate lock resource */
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __HAL_UNLOCK(hdma);
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Disable the peripheral */
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __HAL_DMA_DISABLE(hdma);
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Check if the DMA Stream is effectively disabled */
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Check for the Timeout */
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Update error code */
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Change the DMA state */
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->State = HAL_DMA_STATE_TIMEOUT;
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       return HAL_TIMEOUT;
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Get the CR register value */
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   tmp = hdma->Instance->CR;
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                       DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                       DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                       DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Prepare the DMA Stream configuration */
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.Mode                | hdma->Init.Priority;
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Get memory burst and peripheral burst */
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Write to DMA Stream CR register */
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->Instance->CR = tmp;  
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Get the FCR register value */
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   tmp = hdma->Instance->FCR;
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Clear Direct mode and FIFO threshold bits */
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ARM GAS  /tmp/ccRPwCnE.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Prepare the DMA Stream FIFO configuration */
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   tmp |= hdma->Init.FIFOMode;
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* The FIFO threshold is not used when the FIFO mode is disabled */
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Get the FIFO threshold */
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     tmp |= hdma->Init.FIFOThreshold;
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Check compatibility between FIFO threshold level and size of the memory burst */
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* for INCR4, INCR8, INCR16 bursts */
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       if (DMA_CheckFifoParam(hdma) != HAL_OK)
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Update error code */
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Change the DMA state */
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->State = HAL_DMA_STATE_RESET;
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         return HAL_ERROR; 
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Write to DMA Stream FCR */
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->Instance->FCR = tmp;
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****      DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Clear all interrupt flags */
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   regs->IFCR = 0x3FU << hdma->StreamIndex;
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Initialize the error code */
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                                                                                      
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Initialize the DMA state */
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->State = HAL_DMA_STATE_READY;
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return HAL_OK;
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  DeInitializes the DMA peripheral 
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *               the configuration information for the specified DMA Stream.  
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL status
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   DMA_Base_Registers *regs;
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Check the DMA peripheral state */
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma == NULL)
+ARM GAS  /tmp/ccRPwCnE.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Check the DMA peripheral state */
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma->State == HAL_DMA_STATE_BUSY)
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Return error status */
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_BUSY;
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Check the parameters */
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Disable the selected DMA Streamx */
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __HAL_DMA_DISABLE(hdma);
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Reset DMA Streamx control register */
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->Instance->CR   = 0U;
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Reset DMA Streamx number of data to transfer register */
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->Instance->NDTR = 0U;
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Reset DMA Streamx peripheral address register */
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->Instance->PAR  = 0U;
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Reset DMA Streamx memory 0 address register */
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->Instance->M0AR = 0U;
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Reset DMA Streamx memory 1 address register */
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->Instance->M1AR = 0U;
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Reset DMA Streamx FIFO control register */
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->Instance->FCR  = (uint32_t)0x00000021U;
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Get DMA steam Base Address */  
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Clear all interrupt flags at correct offset within the register */
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   regs->IFCR = 0x3FU << hdma->StreamIndex;
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Clean all callbacks */
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferCpltCallback = NULL;
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferHalfCpltCallback = NULL;
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferM1CpltCallback = NULL;
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferM1HalfCpltCallback = NULL;
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferErrorCallback = NULL;
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferAbortCallback = NULL;  
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Reset the error code */
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Reset the DMA state */
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->State = HAL_DMA_STATE_RESET;
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Release Lock */
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __HAL_UNLOCK(hdma);
+ARM GAS  /tmp/ccRPwCnE.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return HAL_OK;
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @}
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions_Group2
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** @verbatim   
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****  ===============================================================================
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                       #####  IO operation functions  #####
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****  ===============================================================================
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     [..]  This section provides functions allowing to:
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       (+) Configure the source, destination address and data length and Start DMA transfer
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       (+) Configure the source, destination address and data length and 
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           Start DMA transfer with interrupt
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       (+) Abort DMA transfer
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       (+) Poll for transfer complete
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       (+) Handle DMA interrupt request  
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** @endverbatim
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @{
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Starts the DMA Transfer.
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                     the configuration information for the specified DMA Stream.
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  SrcAddress The source memory Buffer address
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  DstAddress The destination memory Buffer address
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  DataLength The length of data to be transferred from source to destination
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL status
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, 
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Check the parameters */
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Process locked */
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __HAL_LOCK(hdma);
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(HAL_DMA_STATE_READY == hdma->State)
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Change DMA peripheral state */
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->State = HAL_DMA_STATE_BUSY;
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Initialize the error code */
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Configure the source, destination address and the data length */
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Enable the Peripheral */
+ARM GAS  /tmp/ccRPwCnE.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_DMA_ENABLE(hdma);
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Process unlocked */
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Return error status */
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     status = HAL_BUSY;
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   } 
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return status; 
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Start the DMA Transfer with interrupt enabled.
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                     the configuration information for the specified DMA Stream.  
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  SrcAddress The source memory Buffer address
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  DstAddress The destination memory Buffer address
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  DataLength The length of data to be transferred from source to destination
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL status
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* calculate DMA base and stream number */
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Check the parameters */
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****  
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Process locked */
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __HAL_LOCK(hdma);
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(HAL_DMA_STATE_READY == hdma->State)
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Change DMA peripheral state */
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->State = HAL_DMA_STATE_BUSY;
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Initialize the error code */
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Configure the source, destination address and the data length */
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Clear all interrupt flags at correct offset within the register */
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     regs->IFCR = 0x3FU << hdma->StreamIndex;
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Enable Common interrupts*/
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->FCR |= DMA_IT_FE;
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if(hdma->XferHalfCpltCallback != NULL)
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->Instance->CR  |= DMA_IT_HT;
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ARM GAS  /tmp/ccRPwCnE.s 			page 10
+
+
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Enable the Peripheral */
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_DMA_ENABLE(hdma);
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Process unlocked */
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_UNLOCK(hdma);	  
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Return error status */
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     status = HAL_BUSY;
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return status;
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Aborts the DMA Transfer.
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                 the configuration information for the specified DMA Stream.
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                   
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is 
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *        effectively disabled is added. If a Stream is disabled 
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *        while a data transfer is ongoing, the current data will be transferred
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *        and the Stream will be effectively disabled only after the transfer of
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *        this single data is finished.  
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL status
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* calculate DMA base and stream number */
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tickstart = HAL_GetTick();
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma->State != HAL_DMA_STATE_BUSY)
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Process Unlocked */
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Disable all the transfer interrupts */
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->FCR &= ~(DMA_IT_FE);
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->Instance->CR  &= ~(DMA_IT_HT);
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Disable the stream */
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_DMA_DISABLE(hdma);
+ARM GAS  /tmp/ccRPwCnE.s 			page 11
+
+
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Check if the DMA Stream is effectively disabled */
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Check for the Timeout */
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Update error code */
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Change the DMA state */
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->State = HAL_DMA_STATE_TIMEOUT;
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Process Unlocked */
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         __HAL_UNLOCK(hdma);
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         return HAL_TIMEOUT;
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Clear all interrupt flags at correct offset within the register */
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     regs->IFCR = 0x3FU << hdma->StreamIndex;
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Change the DMA state*/
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->State = HAL_DMA_STATE_READY;
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Process Unlocked */
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return HAL_OK;
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Aborts the DMA Transfer in Interrupt mode.
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                 the configuration information for the specified DMA Stream.
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL status
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma->State != HAL_DMA_STATE_BUSY)
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Set Abort State  */
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->State = HAL_DMA_STATE_ABORT;
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Disable the stream */
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_DMA_DISABLE(hdma);
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return HAL_OK;
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ARM GAS  /tmp/ccRPwCnE.s 			page 12
+
+
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Polling for transfer complete.
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma          pointer to a DMA_HandleTypeDef structure that contains
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                        the configuration information for the specified DMA Stream.
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  CompleteLevel Specifies the DMA level complete.
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @note   The polling mode is kept in this version for legacy. it is recommended to use the IT mo
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *         This model could be used for debug purpose.
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (a
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  Timeout       Timeout duration.
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL status
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK; 
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t mask_cpltlevel;
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tickstart = HAL_GetTick(); 
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmpisr;
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* calculate DMA base and stream number */
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   DMA_Base_Registers *regs;
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(HAL_DMA_STATE_BUSY != hdma->State)
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* No transfer ongoing */
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Polling mode not supported in circular mode and double buffering mode */
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Get the level transfer complete flag */
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Transfer Complete flag */
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Half Transfer Complete flag */
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   tmpisr = regs->ISR;
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Check for the Timeout (Not applicable in circular mode)*/
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if(Timeout != HAL_MAX_DELAY)
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ARM GAS  /tmp/ccRPwCnE.s 			page 13
+
+
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Update error code */
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Change the DMA state */
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->State = HAL_DMA_STATE_READY;
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Process Unlocked */
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         __HAL_UNLOCK(hdma);
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         return HAL_TIMEOUT;
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Get the ISR register value */
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     tmpisr = regs->ISR;
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Update error code */
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Clear the transfer error flag */
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Update error code */
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Clear the FIFO error flag */
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Update error code */
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Clear the Direct Mode error flag */
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       HAL_DMA_Abort(hdma);
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Clear the half transfer and transfer complete flags */
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Change the DMA state */
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->State= HAL_DMA_STATE_READY;
+ARM GAS  /tmp/ccRPwCnE.s 			page 14
+
+
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Process Unlocked */
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       __HAL_UNLOCK(hdma);
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       return HAL_ERROR;
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****    }
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Get the level transfer complete flag */
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Clear the half transfer and transfer complete flags */
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->State = HAL_DMA_STATE_READY;
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Process Unlocked */
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Clear the half transfer flag */
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return status;
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Handles DMA interrupt request.
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *               the configuration information for the specified DMA Stream.  
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval None
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmpisr;
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __IO uint32_t count = 0;
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t timeout = SystemCoreClock / 9600;
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* calculate DMA base and stream number */
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   tmpisr = regs->ISR;
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Transfer Error Interrupt management ***************************************/
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Disable the transfer error interrupt */
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->Instance->CR  &= ~(DMA_IT_TE);
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Clear the transfer error flag */
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ARM GAS  /tmp/ccRPwCnE.s 			page 15
+
+
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Update error code */
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* FIFO Error Interrupt management ******************************************/
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Clear the FIFO error flag */
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Update error code */
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Direct Mode Error Interrupt management ***********************************/
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Clear the direct mode error flag */
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Update error code */
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Half Transfer Complete Interrupt management ******************************/
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Clear the half transfer complete flag */
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Multi_Buffering mode enabled */
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Current memory buffer used is Memory 0 */
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           if(hdma->XferHalfCpltCallback != NULL)
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****             /* Half transfer callback */
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****             hdma->XferHalfCpltCallback(hdma);
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           }
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Current memory buffer used is Memory 1 */
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         else
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           if(hdma->XferM1HalfCpltCallback != NULL)
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****             /* Half transfer callback */
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****             hdma->XferM1HalfCpltCallback(hdma);
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           }
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ARM GAS  /tmp/ccRPwCnE.s 			page 16
+
+
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       else
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           /* Disable the half transfer interrupt */
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Instance->CR  &= ~(DMA_IT_HT);
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         if(hdma->XferHalfCpltCallback != NULL)
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           /* Half transfer callback */
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->XferHalfCpltCallback(hdma);
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Transfer Complete Interrupt management ***********************************/
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Clear the transfer complete flag */
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       if(HAL_DMA_STATE_ABORT == hdma->State)
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Disable all the transfer interrupts */
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->Instance->FCR &= ~(DMA_IT_FE);
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Instance->CR  &= ~(DMA_IT_HT);
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Clear all interrupt flags at correct offset within the register */
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         regs->IFCR = 0x3FU << hdma->StreamIndex;
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Change the DMA state */
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->State = HAL_DMA_STATE_READY;
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Process Unlocked */
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         __HAL_UNLOCK(hdma);
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         if(hdma->XferAbortCallback != NULL)
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->XferAbortCallback(hdma);
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         return;
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Current memory buffer used is Memory 0 */
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
+ARM GAS  /tmp/ccRPwCnE.s 			page 17
+
+
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           if(hdma->XferM1CpltCallback != NULL)
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****             /* Transfer complete Callback for memory1 */
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****             hdma->XferM1CpltCallback(hdma);
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           }
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         /* Current memory buffer used is Memory 1 */
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         else
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           if(hdma->XferCpltCallback != NULL)
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****             /* Transfer complete Callback for memory0 */
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****             hdma->XferCpltCallback(hdma);
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           }
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       else
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           /* Disable the transfer complete interrupt */
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Instance->CR  &= ~(DMA_IT_TC);
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           /* Change the DMA state */
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->State = HAL_DMA_STATE_READY;
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           /* Process Unlocked */
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           __HAL_UNLOCK(hdma);
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         if(hdma->XferCpltCallback != NULL)
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           /* Transfer complete callback */
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->XferCpltCallback(hdma);
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* manage error case */
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->State = HAL_DMA_STATE_ABORT;
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Disable the stream */
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       __HAL_DMA_DISABLE(hdma);
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       do
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         if (++count > timeout)
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           break;
+ARM GAS  /tmp/ccRPwCnE.s 			page 18
+
+
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Change the DMA state */
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->State = HAL_DMA_STATE_READY;
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Process Unlocked */
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       __HAL_UNLOCK(hdma);
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     if(hdma->XferErrorCallback != NULL)
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Transfer error callback */
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferErrorCallback(hdma);
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Register callbacks
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                               the configuration information for the specified DMA Stream.
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  CallbackID           User Callback identifier
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                               a DMA_HandleTypeDef structure as parameter.
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  pCallback            pointer to private callbacsk function which has pointer to 
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                               a DMA_HandleTypeDef structure as parameter.
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL status
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */                      
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Process locked */
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __HAL_LOCK(hdma);
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(HAL_DMA_STATE_READY == hdma->State)
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     switch (CallbackID)
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_CPLT_CB_ID:
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferCpltCallback = pCallback;
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferHalfCpltCallback = pCallback;
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_M1CPLT_CB_ID:
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferM1CpltCallback = pCallback;
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferM1HalfCpltCallback = pCallback;
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ARM GAS  /tmp/ccRPwCnE.s 			page 19
+
+
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_ERROR_CB_ID:
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferErrorCallback = pCallback;
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_ABORT_CB_ID:
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferAbortCallback = pCallback;
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     default:
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       /* Return error status */
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       status =  HAL_ERROR;
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Return error status */
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     status =  HAL_ERROR;
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Release Lock */
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __HAL_UNLOCK(hdma);
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return status;
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  UnRegister callbacks
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                               the configuration information for the specified DMA Stream.
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  CallbackID           User Callback identifier
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL status
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */              
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Process locked */
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __HAL_LOCK(hdma);
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(HAL_DMA_STATE_READY == hdma->State)
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     switch (CallbackID)
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_CPLT_CB_ID:
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferCpltCallback = NULL;
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferHalfCpltCallback = NULL;
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_M1CPLT_CB_ID:
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferM1CpltCallback = NULL;
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ARM GAS  /tmp/ccRPwCnE.s 			page 20
+
+
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferM1HalfCpltCallback = NULL;
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_ERROR_CB_ID:
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferErrorCallback = NULL;
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case  HAL_DMA_XFER_ABORT_CB_ID:
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferAbortCallback = NULL;
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break; 
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case   HAL_DMA_XFER_ALL_CB_ID:
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferCpltCallback = NULL;
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferHalfCpltCallback = NULL;
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferM1CpltCallback = NULL;
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferM1HalfCpltCallback = NULL;
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferErrorCallback = NULL;
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferAbortCallback = NULL;
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break; 
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     default:
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       status = HAL_ERROR;
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else
+1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     status = HAL_ERROR;
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Release Lock */
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __HAL_UNLOCK(hdma);
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return status;
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @}
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions_Group3
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** @verbatim
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****  ===============================================================================
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                     ##### State and Errors functions #####
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****  ===============================================================================
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     [..]
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     This subsection provides functions allowing to
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       (+) Check the DMA state
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       (+) Get error code
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** @endverbatim
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @{
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ARM GAS  /tmp/ccRPwCnE.s 			page 21
+
+
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Returns the DMA state.
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *               the configuration information for the specified DMA Stream.
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL state
+1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return hdma->State;
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Return the DMA error code
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma  pointer to a DMA_HandleTypeDef structure that contains
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *              the configuration information for the specified DMA Stream.
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval DMA Error Code
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return hdma->ErrorCode;
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @}
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @}
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @addtogroup DMA_Private_Functions
+1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @{
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Sets the DMA Transfer parameter.
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                     the configuration information for the specified DMA Stream.
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  SrcAddress The source memory Buffer address
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  DstAddress The destination memory Buffer address
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  DataLength The length of data to be transferred from source to destination
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL status
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+  28              		.loc 1 1159 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  33              		.loc 1 1159 1 is_stmt 0 view .LVU1
+  34 0000 30B4     		push	{r4, r5}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 8
+  37              		.cfi_offset 4, -8
+  38              		.cfi_offset 5, -4
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Clear DBM bit */
+ARM GAS  /tmp/ccRPwCnE.s 			page 22
+
+
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
+  39              		.loc 1 1161 3 is_stmt 1 view .LVU2
+  40              		.loc 1 1161 7 is_stmt 0 view .LVU3
+  41 0002 0568     		ldr	r5, [r0]
+  42              		.loc 1 1161 22 view .LVU4
+  43 0004 2C68     		ldr	r4, [r5]
+  44 0006 24F48024 		bic	r4, r4, #262144
+  45 000a 2C60     		str	r4, [r5]
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Configure DMA Stream data length */
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->Instance->NDTR = DataLength;
+  46              		.loc 1 1164 3 is_stmt 1 view .LVU5
+  47              		.loc 1 1164 7 is_stmt 0 view .LVU6
+  48 000c 0468     		ldr	r4, [r0]
+  49              		.loc 1 1164 24 view .LVU7
+  50 000e 6360     		str	r3, [r4, #4]
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Memory to Peripheral */
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  51              		.loc 1 1167 3 is_stmt 1 view .LVU8
+  52              		.loc 1 1167 17 is_stmt 0 view .LVU9
+  53 0010 8368     		ldr	r3, [r0, #8]
+  54              	.LVL1:
+  55              		.loc 1 1167 5 view .LVU10
+  56 0012 402B     		cmp	r3, #64
+  57 0014 05D0     		beq	.L5
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Configure DMA Stream destination address */
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->PAR = DstAddress;
+1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Configure DMA Stream source address */
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->M0AR = SrcAddress;
+1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Peripheral to Memory */
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Configure DMA Stream source address */
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->PAR = SrcAddress;
+  58              		.loc 1 1179 5 is_stmt 1 view .LVU11
+  59              		.loc 1 1179 9 is_stmt 0 view .LVU12
+  60 0016 0368     		ldr	r3, [r0]
+  61              		.loc 1 1179 25 view .LVU13
+  62 0018 9960     		str	r1, [r3, #8]
+  63              	.LVL2:
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* Configure DMA Stream destination address */
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->M0AR = DstAddress;
+  64              		.loc 1 1182 5 is_stmt 1 view .LVU14
+  65              		.loc 1 1182 9 is_stmt 0 view .LVU15
+  66 001a 0368     		ldr	r3, [r0]
+  67              		.loc 1 1182 26 view .LVU16
+  68 001c DA60     		str	r2, [r3, #12]
+  69              	.L1:
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+  70              		.loc 1 1184 1 view .LVU17
+  71 001e 30BC     		pop	{r4, r5}
+ARM GAS  /tmp/ccRPwCnE.s 			page 23
+
+
+  72              	.LCFI1:
+  73              		.cfi_remember_state
+  74              		.cfi_restore 5
+  75              		.cfi_restore 4
+  76              		.cfi_def_cfa_offset 0
+  77 0020 7047     		bx	lr
+  78              	.LVL3:
+  79              	.L5:
+  80              	.LCFI2:
+  81              		.cfi_restore_state
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  82              		.loc 1 1170 5 is_stmt 1 view .LVU18
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  83              		.loc 1 1170 9 is_stmt 0 view .LVU19
+  84 0022 0368     		ldr	r3, [r0]
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+  85              		.loc 1 1170 25 view .LVU20
+  86 0024 9A60     		str	r2, [r3, #8]
+  87              	.LVL4:
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+  88              		.loc 1 1173 5 is_stmt 1 view .LVU21
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+  89              		.loc 1 1173 9 is_stmt 0 view .LVU22
+  90 0026 0368     		ldr	r3, [r0]
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+  91              		.loc 1 1173 26 view .LVU23
+  92 0028 D960     		str	r1, [r3, #12]
+  93 002a F8E7     		b	.L1
+  94              		.cfi_endproc
+  95              	.LFE153:
+  97              		.section	.text.DMA_CalcBaseAndBitshift,"ax",%progbits
+  98              		.align	1
+  99              		.syntax unified
+ 100              		.thumb
+ 101              		.thumb_func
+ 102              		.fpu fpv5-d16
+ 104              	DMA_CalcBaseAndBitshift:
+ 105              	.LVL5:
+ 106              	.LFB154:
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Returns the DMA Stream base address depending on stream number
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                     the configuration information for the specified DMA Stream. 
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval Stream base address
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 107              		.loc 1 1193 1 is_stmt 1 view -0
+ 108              		.cfi_startproc
+ 109              		@ args = 0, pretend = 0, frame = 0
+ 110              		@ frame_needed = 0, uses_anonymous_args = 0
+ 111              		@ link register save eliminated.
+ 112              		.loc 1 1193 1 is_stmt 0 view .LVU25
+ 113 0000 10B4     		push	{r4}
+ 114              	.LCFI3:
+ 115              		.cfi_def_cfa_offset 4
+ARM GAS  /tmp/ccRPwCnE.s 			page 24
+
+
+ 116              		.cfi_offset 4, -4
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
+ 117              		.loc 1 1194 3 is_stmt 1 view .LVU26
+ 118              		.loc 1 1194 44 is_stmt 0 view .LVU27
+ 119 0002 0168     		ldr	r1, [r0]
+ 120              		.loc 1 1194 55 view .LVU28
+ 121 0004 CAB2     		uxtb	r2, r1
+ 122              		.loc 1 1194 64 view .LVU29
+ 123 0006 103A     		subs	r2, r2, #16
+ 124              		.loc 1 1194 12 view .LVU30
+ 125 0008 0A4B     		ldr	r3, .L10
+ 126 000a A3FB0243 		umull	r4, r3, r3, r2
+ 127 000e 1B09     		lsrs	r3, r3, #4
+ 128              	.LVL6:
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* lookup table for necessary bitshift of flags within status registers */
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+ 129              		.loc 1 1197 3 is_stmt 1 view .LVU31
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->StreamIndex = flagBitshiftOffset[stream_number];
+ 130              		.loc 1 1198 3 view .LVU32
+ 131              		.loc 1 1198 41 is_stmt 0 view .LVU33
+ 132 0010 094C     		ldr	r4, .L10+4
+ 133 0012 E35C     		ldrb	r3, [r4, r3]	@ zero_extendqisi2
+ 134              	.LVL7:
+ 135              		.loc 1 1198 21 view .LVU34
+ 136 0014 C365     		str	r3, [r0, #92]
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if (stream_number > 3U)
+ 137              		.loc 1 1200 3 is_stmt 1 view .LVU35
+ 138              		.loc 1 1200 6 is_stmt 0 view .LVU36
+ 139 0016 5F2A     		cmp	r2, #95
+ 140 0018 07D9     		bls	.L7
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* return pointer to HISR and HIFCR */
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
+ 141              		.loc 1 1203 5 is_stmt 1 view .LVU37
+ 142              		.loc 1 1203 58 is_stmt 0 view .LVU38
+ 143 001a 084B     		ldr	r3, .L10+8
+ 144 001c 0B40     		ands	r3, r3, r1
+ 145              		.loc 1 1203 81 view .LVU39
+ 146 001e 0433     		adds	r3, r3, #4
+ 147              		.loc 1 1203 29 view .LVU40
+ 148 0020 8365     		str	r3, [r0, #88]
+ 149              	.L8:
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     /* return pointer to LISR and LIFCR */
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return hdma->StreamBaseAddress;
+ 150              		.loc 1 1211 3 is_stmt 1 view .LVU41
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 151              		.loc 1 1212 1 is_stmt 0 view .LVU42
+ 152 0022 806D     		ldr	r0, [r0, #88]
+ 153              	.LVL8:
+ARM GAS  /tmp/ccRPwCnE.s 			page 25
+
+
+ 154              		.loc 1 1212 1 view .LVU43
+ 155 0024 5DF8044B 		ldr	r4, [sp], #4
+ 156              	.LCFI4:
+ 157              		.cfi_remember_state
+ 158              		.cfi_restore 4
+ 159              		.cfi_def_cfa_offset 0
+ 160 0028 7047     		bx	lr
+ 161              	.LVL9:
+ 162              	.L7:
+ 163              	.LCFI5:
+ 164              		.cfi_restore_state
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 165              		.loc 1 1208 5 is_stmt 1 view .LVU44
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 166              		.loc 1 1208 57 is_stmt 0 view .LVU45
+ 167 002a 044B     		ldr	r3, .L10+8
+ 168 002c 0B40     		ands	r3, r3, r1
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 169              		.loc 1 1208 29 view .LVU46
+ 170 002e 8365     		str	r3, [r0, #88]
+ 171 0030 F7E7     		b	.L8
+ 172              	.L11:
+ 173 0032 00BF     		.align	2
+ 174              	.L10:
+ 175 0034 ABAAAAAA 		.word	-1431655765
+ 176 0038 00000000 		.word	.LANCHOR0
+ 177 003c 00FCFFFF 		.word	-1024
+ 178              		.cfi_endproc
+ 179              	.LFE154:
+ 181              		.section	.text.DMA_CheckFifoParam,"ax",%progbits
+ 182              		.align	1
+ 183              		.syntax unified
+ 184              		.thumb
+ 185              		.thumb_func
+ 186              		.fpu fpv5-d16
+ 188              	DMA_CheckFifoParam:
+ 189              	.LVL10:
+ 190              	.LFB155:
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /**
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @brief  Check compatibility between FIFO threshold level and size of the memory burst
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   *                     the configuration information for the specified DMA Stream. 
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   * @retval HAL status
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   */
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** {
+ 191              		.loc 1 1221 1 is_stmt 1 view -0
+ 192              		.cfi_startproc
+ 193              		@ args = 0, pretend = 0, frame = 0
+ 194              		@ frame_needed = 0, uses_anonymous_args = 0
+ 195              		@ link register save eliminated.
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 196              		.loc 1 1222 3 view .LVU48
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = hdma->Init.FIFOThreshold;
+ 197              		.loc 1 1223 3 view .LVU49
+ 198              		.loc 1 1223 12 is_stmt 0 view .LVU50
+ARM GAS  /tmp/ccRPwCnE.s 			page 26
+
+
+ 199 0000 836A     		ldr	r3, [r0, #40]
+ 200              	.LVL11:
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Memory Data size equal to Byte */
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+ 201              		.loc 1 1226 3 is_stmt 1 view .LVU51
+ 202              		.loc 1 1226 16 is_stmt 0 view .LVU52
+ 203 0002 8269     		ldr	r2, [r0, #24]
+ 204              		.loc 1 1226 5 view .LVU53
+ 205 0004 92B9     		cbnz	r2, .L13
+1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     switch (tmp)
+ 206              		.loc 1 1228 5 is_stmt 1 view .LVU54
+ 207 0006 012B     		cmp	r3, #1
+ 208 0008 0AD0     		beq	.L14
+ 209 000a 022B     		cmp	r3, #2
+ 210 000c 02D0     		beq	.L15
+ 211 000e 0BB1     		cbz	r3, .L15
+ 212 0010 0020     		movs	r0, #0
+ 213              	.LVL12:
+ 214              		.loc 1 1228 5 is_stmt 0 view .LVU55
+ 215 0012 7047     		bx	lr
+ 216              	.LVL13:
+ 217              	.L15:
+1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ 218              		.loc 1 1232 7 is_stmt 1 view .LVU56
+ 219              		.loc 1 1232 22 is_stmt 0 view .LVU57
+ 220 0014 C36A     		ldr	r3, [r0, #44]
+ 221              	.LVL14:
+ 222              		.loc 1 1232 10 view .LVU58
+ 223 0016 13F0807F 		tst	r3, #16777216
+ 224 001a 28D1     		bne	.L23
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = hdma->Init.FIFOThreshold;
+ 225              		.loc 1 1222 21 view .LVU59
+ 226 001c 0020     		movs	r0, #0
+ 227              	.LVL15:
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = hdma->Init.FIFOThreshold;
+ 228              		.loc 1 1222 21 view .LVU60
+ 229 001e 7047     		bx	lr
+ 230              	.LVL16:
+ 231              	.L14:
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         status = HAL_ERROR;
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_HALFFULL:
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+ 232              		.loc 1 1238 7 is_stmt 1 view .LVU61
+ 233              		.loc 1 1238 21 is_stmt 0 view .LVU62
+ 234 0020 C36A     		ldr	r3, [r0, #44]
+ 235              	.LVL17:
+ 236              		.loc 1 1238 10 view .LVU63
+ 237 0022 B3F1C07F 		cmp	r3, #25165824
+ 238 0026 24D0     		beq	.L24
+ARM GAS  /tmp/ccRPwCnE.s 			page 27
+
+
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = hdma->Init.FIFOThreshold;
+ 239              		.loc 1 1222 21 view .LVU64
+ 240 0028 0020     		movs	r0, #0
+ 241              	.LVL18:
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = hdma->Init.FIFOThreshold;
+ 242              		.loc 1 1222 21 view .LVU65
+ 243 002a 7047     		bx	lr
+ 244              	.LVL19:
+ 245              	.L13:
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         status = HAL_ERROR;
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_FULL:
+1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     default:
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Memory Data size equal to Half-Word */
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ 246              		.loc 1 1251 8 is_stmt 1 view .LVU66
+ 247              		.loc 1 1251 11 is_stmt 0 view .LVU67
+ 248 002c B2F5005F 		cmp	r2, #8192
+ 249 0030 09D0     		beq	.L31
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     switch (tmp)
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       status = HAL_ERROR;
+1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_HALFFULL:
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         status = HAL_ERROR;
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_FULL:
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         status = HAL_ERROR;
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;   
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     default:
+1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Memory Data size equal to Word */
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   else
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     switch (tmp)
+ 250              		.loc 1 1279 5 is_stmt 1 view .LVU68
+ 251 0032 022B     		cmp	r3, #2
+ 252 0034 25D9     		bls	.L28
+ARM GAS  /tmp/ccRPwCnE.s 			page 28
+
+
+ 253 0036 032B     		cmp	r3, #3
+ 254 0038 25D1     		bne	.L29
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_HALFFULL:
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       status = HAL_ERROR;
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     case DMA_FIFO_THRESHOLD_FULL:
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ 255              		.loc 1 1287 7 view .LVU69
+ 256              		.loc 1 1287 22 is_stmt 0 view .LVU70
+ 257 003a C36A     		ldr	r3, [r0, #44]
+ 258              	.LVL20:
+ 259              		.loc 1 1287 10 view .LVU71
+ 260 003c 13F0807F 		tst	r3, #16777216
+ 261 0040 23D1     		bne	.L30
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = hdma->Init.FIFOThreshold;
+ 262              		.loc 1 1222 21 view .LVU72
+ 263 0042 0020     		movs	r0, #0
+ 264              	.LVL21:
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = hdma->Init.FIFOThreshold;
+ 265              		.loc 1 1222 21 view .LVU73
+ 266 0044 7047     		bx	lr
+ 267              	.LVL22:
+ 268              	.L31:
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 269              		.loc 1 1253 5 is_stmt 1 view .LVU74
+ 270 0046 032B     		cmp	r3, #3
+ 271 0048 03D8     		bhi	.L18
+ 272 004a DFE803F0 		tbb	[pc, r3]
+ 273              	.L20:
+ 274 004e 14       		.byte	(.L25-.L20)/2
+ 275 004f 04       		.byte	(.L21-.L20)/2
+ 276 0050 14       		.byte	(.L25-.L20)/2
+ 277 0051 0A       		.byte	(.L19-.L20)/2
+ 278              		.p2align 1
+ 279              	.L18:
+ 280 0052 0020     		movs	r0, #0
+ 281              	.LVL23:
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 282              		.loc 1 1253 5 is_stmt 0 view .LVU75
+ 283 0054 7047     		bx	lr
+ 284              	.LVL24:
+ 285              	.L21:
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 286              		.loc 1 1260 7 is_stmt 1 view .LVU76
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 287              		.loc 1 1260 22 is_stmt 0 view .LVU77
+ 288 0056 C36A     		ldr	r3, [r0, #44]
+ 289              	.LVL25:
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 290              		.loc 1 1260 10 view .LVU78
+ 291 0058 13F0807F 		tst	r3, #16777216
+ 292 005c 0DD1     		bne	.L26
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = hdma->Init.FIFOThreshold;
+ 293              		.loc 1 1222 21 view .LVU79
+ARM GAS  /tmp/ccRPwCnE.s 			page 29
+
+
+ 294 005e 0020     		movs	r0, #0
+ 295              	.LVL26:
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = hdma->Init.FIFOThreshold;
+ 296              		.loc 1 1222 21 view .LVU80
+ 297 0060 7047     		bx	lr
+ 298              	.LVL27:
+ 299              	.L19:
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 300              		.loc 1 1266 7 is_stmt 1 view .LVU81
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 301              		.loc 1 1266 21 is_stmt 0 view .LVU82
+ 302 0062 C36A     		ldr	r3, [r0, #44]
+ 303              	.LVL28:
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 304              		.loc 1 1266 10 view .LVU83
+ 305 0064 B3F1C07F 		cmp	r3, #25165824
+ 306 0068 09D0     		beq	.L27
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = hdma->Init.FIFOThreshold;
+ 307              		.loc 1 1222 21 view .LVU84
+ 308 006a 0020     		movs	r0, #0
+ 309              	.LVL29:
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = hdma->Init.FIFOThreshold;
+ 310              		.loc 1 1222 21 view .LVU85
+ 311 006c 7047     		bx	lr
+ 312              	.LVL30:
+ 313              	.L23:
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 314              		.loc 1 1234 16 view .LVU86
+ 315 006e 0120     		movs	r0, #1
+ 316              	.LVL31:
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 317              		.loc 1 1234 16 view .LVU87
+ 318 0070 7047     		bx	lr
+ 319              	.LVL32:
+ 320              	.L24:
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 321              		.loc 1 1240 16 view .LVU88
+ 322 0072 0120     		movs	r0, #1
+ 323              	.LVL33:
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 324              		.loc 1 1240 16 view .LVU89
+ 325 0074 7047     		bx	lr
+ 326              	.LVL34:
+ 327              	.L25:
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 328              		.loc 1 1257 14 view .LVU90
+ 329 0076 0120     		movs	r0, #1
+ 330              	.LVL35:
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 331              		.loc 1 1257 14 view .LVU91
+ 332 0078 7047     		bx	lr
+ 333              	.LVL36:
+ 334              	.L26:
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 335              		.loc 1 1262 16 view .LVU92
+ 336 007a 0120     		movs	r0, #1
+ 337              	.LVL37:
+ARM GAS  /tmp/ccRPwCnE.s 			page 30
+
+
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 338              		.loc 1 1262 16 view .LVU93
+ 339 007c 7047     		bx	lr
+ 340              	.LVL38:
+ 341              	.L27:
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 342              		.loc 1 1268 16 view .LVU94
+ 343 007e 0120     		movs	r0, #1
+ 344              	.LVL39:
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 345              		.loc 1 1268 16 view .LVU95
+ 346 0080 7047     		bx	lr
+ 347              	.LVL40:
+ 348              	.L28:
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 349              		.loc 1 1284 14 view .LVU96
+ 350 0082 0120     		movs	r0, #1
+ 351              	.LVL41:
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 352              		.loc 1 1284 14 view .LVU97
+ 353 0084 7047     		bx	lr
+ 354              	.LVL42:
+ 355              	.L29:
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 356              		.loc 1 1279 5 view .LVU98
+ 357 0086 0020     		movs	r0, #0
+ 358              	.LVL43:
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 359              		.loc 1 1279 5 view .LVU99
+ 360 0088 7047     		bx	lr
+ 361              	.LVL44:
+ 362              	.L30:
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         status = HAL_ERROR;
+ 363              		.loc 1 1289 16 view .LVU100
+ 364 008a 0120     		movs	r0, #1
+ 365              	.LVL45:
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     default:
+1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   } 
+1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return status; 
+ 366              		.loc 1 1297 3 is_stmt 1 view .LVU101
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 367              		.loc 1 1298 1 is_stmt 0 view .LVU102
+ 368 008c 7047     		bx	lr
+ 369              		.cfi_endproc
+ 370              	.LFE155:
+ 372              		.section	.text.HAL_DMA_Init,"ax",%progbits
+ 373              		.align	1
+ 374              		.global	HAL_DMA_Init
+ 375              		.syntax unified
+ 376              		.thumb
+ 377              		.thumb_func
+ARM GAS  /tmp/ccRPwCnE.s 			page 31
+
+
+ 378              		.fpu fpv5-d16
+ 380              	HAL_DMA_Init:
+ 381              	.LVL46:
+ 382              	.LFB141:
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = 0U;
+ 383              		.loc 1 172 1 is_stmt 1 view -0
+ 384              		.cfi_startproc
+ 385              		@ args = 0, pretend = 0, frame = 0
+ 386              		@ frame_needed = 0, uses_anonymous_args = 0
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmp = 0U;
+ 387              		.loc 1 172 1 is_stmt 0 view .LVU104
+ 388 0000 70B5     		push	{r4, r5, r6, lr}
+ 389              	.LCFI6:
+ 390              		.cfi_def_cfa_offset 16
+ 391              		.cfi_offset 4, -16
+ 392              		.cfi_offset 5, -12
+ 393              		.cfi_offset 6, -8
+ 394              		.cfi_offset 14, -4
+ 395 0002 0446     		mov	r4, r0
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tickstart = HAL_GetTick();
+ 396              		.loc 1 173 3 is_stmt 1 view .LVU105
+ 397              	.LVL47:
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   DMA_Base_Registers *regs;
+ 398              		.loc 1 174 3 view .LVU106
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   DMA_Base_Registers *regs;
+ 399              		.loc 1 174 24 is_stmt 0 view .LVU107
+ 400 0004 FFF7FEFF 		bl	HAL_GetTick
+ 401              	.LVL48:
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 402              		.loc 1 175 3 is_stmt 1 view .LVU108
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 403              		.loc 1 178 3 view .LVU109
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 404              		.loc 1 178 5 is_stmt 0 view .LVU110
+ 405 0008 002C     		cmp	r4, #0
+ 406 000a 5CD0     		beq	.L38
+ 407 000c 0546     		mov	r5, r0
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
+ 408              		.loc 1 184 3 is_stmt 1 view .LVU111
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ 409              		.loc 1 185 3 view .LVU112
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ 410              		.loc 1 186 3 view .LVU113
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ 411              		.loc 1 187 3 view .LVU114
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ 412              		.loc 1 188 3 view .LVU115
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ 413              		.loc 1 189 3 view .LVU116
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ 414              		.loc 1 190 3 view .LVU117
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+ 415              		.loc 1 191 3 view .LVU118
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+ 416              		.loc 1 192 3 view .LVU119
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+ 417              		.loc 1 193 3 view .LVU120
+ARM GAS  /tmp/ccRPwCnE.s 			page 32
+
+
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 418              		.loc 1 196 3 view .LVU121
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+ 419              		.loc 1 198 5 view .LVU122
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+ 420              		.loc 1 199 5 view .LVU123
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 421              		.loc 1 200 5 view .LVU124
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 422              		.loc 1 204 3 view .LVU125
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 423              		.loc 1 204 15 is_stmt 0 view .LVU126
+ 424 000e 0223     		movs	r3, #2
+ 425 0010 84F83530 		strb	r3, [r4, #53]
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 426              		.loc 1 207 3 is_stmt 1 view .LVU127
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 427              		.loc 1 207 3 view .LVU128
+ 428 0014 0023     		movs	r3, #0
+ 429 0016 84F83430 		strb	r3, [r4, #52]
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 430              		.loc 1 207 3 view .LVU129
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 431              		.loc 1 211 3 view .LVU130
+ 432 001a 2268     		ldr	r2, [r4]
+ 433 001c 1368     		ldr	r3, [r2]
+ 434 001e 23F00103 		bic	r3, r3, #1
+ 435 0022 1360     		str	r3, [r2]
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 436              		.loc 1 214 3 view .LVU131
+ 437              	.LVL49:
+ 438              	.L34:
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 439              		.loc 1 214 8 view .LVU132
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 440              		.loc 1 214 14 is_stmt 0 view .LVU133
+ 441 0024 2368     		ldr	r3, [r4]
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 442              		.loc 1 214 24 view .LVU134
+ 443 0026 1A68     		ldr	r2, [r3]
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 444              		.loc 1 214 8 view .LVU135
+ 445 0028 12F0010F 		tst	r2, #1
+ 446 002c 0AD0     		beq	.L40
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 447              		.loc 1 217 5 is_stmt 1 view .LVU136
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 448              		.loc 1 217 9 is_stmt 0 view .LVU137
+ 449 002e FFF7FEFF 		bl	HAL_GetTick
+ 450              	.LVL50:
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 451              		.loc 1 217 23 view .LVU138
+ 452 0032 431B     		subs	r3, r0, r5
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 453              		.loc 1 217 7 view .LVU139
+ 454 0034 052B     		cmp	r3, #5
+ 455 0036 F5D9     		bls	.L34
+ARM GAS  /tmp/ccRPwCnE.s 			page 33
+
+
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 456              		.loc 1 220 7 is_stmt 1 view .LVU140
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 457              		.loc 1 220 23 is_stmt 0 view .LVU141
+ 458 0038 2023     		movs	r3, #32
+ 459 003a 6365     		str	r3, [r4, #84]
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 460              		.loc 1 223 7 is_stmt 1 view .LVU142
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 461              		.loc 1 223 19 is_stmt 0 view .LVU143
+ 462 003c 0320     		movs	r0, #3
+ 463 003e 84F83500 		strb	r0, [r4, #53]
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 464              		.loc 1 225 7 is_stmt 1 view .LVU144
+ 465              	.LVL51:
+ 466              	.L33:
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 467              		.loc 1 303 1 is_stmt 0 view .LVU145
+ 468 0042 70BD     		pop	{r4, r5, r6, pc}
+ 469              	.LVL52:
+ 470              	.L40:
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 471              		.loc 1 230 3 is_stmt 1 view .LVU146
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 472              		.loc 1 230 7 is_stmt 0 view .LVU147
+ 473 0044 1A68     		ldr	r2, [r3]
+ 474              	.LVL53:
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                       DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+ 475              		.loc 1 233 3 is_stmt 1 view .LVU148
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                       DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+ 476              		.loc 1 233 7 is_stmt 0 view .LVU149
+ 477 0046 2148     		ldr	r0, .L43
+ 478 0048 1040     		ands	r0, r0, r2
+ 479              	.LVL54:
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 480              		.loc 1 239 3 is_stmt 1 view .LVU150
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 481              		.loc 1 239 21 is_stmt 0 view .LVU151
+ 482 004a 6168     		ldr	r1, [r4, #4]
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 483              		.loc 1 239 54 view .LVU152
+ 484 004c A268     		ldr	r2, [r4, #8]
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 485              		.loc 1 239 42 view .LVU153
+ 486 004e 0A43     		orrs	r2, r2, r1
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 487              		.loc 1 240 21 view .LVU154
+ 488 0050 E168     		ldr	r1, [r4, #12]
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 489              		.loc 1 239 72 view .LVU155
+ 490 0052 0A43     		orrs	r2, r2, r1
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 491              		.loc 1 240 54 view .LVU156
+ 492 0054 2169     		ldr	r1, [r4, #16]
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 493              		.loc 1 240 42 view .LVU157
+ 494 0056 0A43     		orrs	r2, r2, r1
+ARM GAS  /tmp/ccRPwCnE.s 			page 34
+
+
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.Mode                | hdma->Init.Priority;
+ 495              		.loc 1 241 21 view .LVU158
+ 496 0058 6169     		ldr	r1, [r4, #20]
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 497              		.loc 1 240 72 view .LVU159
+ 498 005a 0A43     		orrs	r2, r2, r1
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.Mode                | hdma->Init.Priority;
+ 499              		.loc 1 241 54 view .LVU160
+ 500 005c A169     		ldr	r1, [r4, #24]
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.Mode                | hdma->Init.Priority;
+ 501              		.loc 1 241 42 view .LVU161
+ 502 005e 0A43     		orrs	r2, r2, r1
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 503              		.loc 1 242 21 view .LVU162
+ 504 0060 E169     		ldr	r1, [r4, #28]
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.Mode                | hdma->Init.Priority;
+ 505              		.loc 1 241 72 view .LVU163
+ 506 0062 0A43     		orrs	r2, r2, r1
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 507              		.loc 1 242 54 view .LVU164
+ 508 0064 216A     		ldr	r1, [r4, #32]
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 509              		.loc 1 242 42 view .LVU165
+ 510 0066 0A43     		orrs	r2, r2, r1
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 511              		.loc 1 239 7 view .LVU166
+ 512 0068 0243     		orrs	r2, r2, r0
+ 513              	.LVL55:
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 514              		.loc 1 245 3 is_stmt 1 view .LVU167
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 515              		.loc 1 245 16 is_stmt 0 view .LVU168
+ 516 006a 616A     		ldr	r1, [r4, #36]
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 517              		.loc 1 245 5 view .LVU169
+ 518 006c 0429     		cmp	r1, #4
+ 519 006e 1ED0     		beq	.L41
+ 520              	.L36:
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 521              		.loc 1 252 3 is_stmt 1 view .LVU170
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 522              		.loc 1 252 22 is_stmt 0 view .LVU171
+ 523 0070 1A60     		str	r2, [r3]
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 524              		.loc 1 255 3 is_stmt 1 view .LVU172
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 525              		.loc 1 255 13 is_stmt 0 view .LVU173
+ 526 0072 2668     		ldr	r6, [r4]
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 527              		.loc 1 255 7 view .LVU174
+ 528 0074 7569     		ldr	r5, [r6, #20]
+ 529              	.LVL56:
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 530              		.loc 1 258 3 is_stmt 1 view .LVU175
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 531              		.loc 1 258 7 is_stmt 0 view .LVU176
+ 532 0076 25F00705 		bic	r5, r5, #7
+ARM GAS  /tmp/ccRPwCnE.s 			page 35
+
+
+ 533              	.LVL57:
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 534              		.loc 1 261 3 is_stmt 1 view .LVU177
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 535              		.loc 1 261 20 is_stmt 0 view .LVU178
+ 536 007a 636A     		ldr	r3, [r4, #36]
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 537              		.loc 1 261 7 view .LVU179
+ 538 007c 1D43     		orrs	r5, r5, r3
+ 539              	.LVL58:
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 540              		.loc 1 264 3 is_stmt 1 view .LVU180
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 541              		.loc 1 264 5 is_stmt 0 view .LVU181
+ 542 007e 042B     		cmp	r3, #4
+ 543 0080 07D1     		bne	.L37
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 544              		.loc 1 267 5 is_stmt 1 view .LVU182
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 545              		.loc 1 267 22 is_stmt 0 view .LVU183
+ 546 0082 A36A     		ldr	r3, [r4, #40]
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 547              		.loc 1 267 9 view .LVU184
+ 548 0084 1D43     		orrs	r5, r5, r3
+ 549              	.LVL59:
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 550              		.loc 1 271 5 is_stmt 1 view .LVU185
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 551              		.loc 1 271 19 is_stmt 0 view .LVU186
+ 552 0086 E36A     		ldr	r3, [r4, #44]
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 553              		.loc 1 271 8 view .LVU187
+ 554 0088 1BB1     		cbz	r3, .L37
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 555              		.loc 1 273 7 is_stmt 1 view .LVU188
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 556              		.loc 1 273 11 is_stmt 0 view .LVU189
+ 557 008a 2046     		mov	r0, r4
+ 558 008c FFF7FEFF 		bl	DMA_CheckFifoParam
+ 559              	.LVL60:
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 560              		.loc 1 273 10 view .LVU190
+ 561 0090 90B9     		cbnz	r0, .L42
+ 562              	.L37:
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 563              		.loc 1 287 3 is_stmt 1 view .LVU191
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 564              		.loc 1 287 23 is_stmt 0 view .LVU192
+ 565 0092 7561     		str	r5, [r6, #20]
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 566              		.loc 1 291 3 is_stmt 1 view .LVU193
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 567              		.loc 1 291 32 is_stmt 0 view .LVU194
+ 568 0094 2046     		mov	r0, r4
+ 569 0096 FFF7FEFF 		bl	DMA_CalcBaseAndBitshift
+ 570              	.LVL61:
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ARM GAS  /tmp/ccRPwCnE.s 			page 36
+
+
+ 571              		.loc 1 294 3 is_stmt 1 view .LVU195
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 572              		.loc 1 294 29 is_stmt 0 view .LVU196
+ 573 009a E26D     		ldr	r2, [r4, #92]
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 574              		.loc 1 294 22 view .LVU197
+ 575 009c 3F23     		movs	r3, #63
+ 576 009e 9340     		lsls	r3, r3, r2
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 577              		.loc 1 294 14 view .LVU198
+ 578 00a0 8360     		str	r3, [r0, #8]
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                                                                                      
+ 579              		.loc 1 297 3 is_stmt 1 view .LVU199
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                                                                                      
+ 580              		.loc 1 297 19 is_stmt 0 view .LVU200
+ 581 00a2 0020     		movs	r0, #0
+ 582              	.LVL62:
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****                                                                                      
+ 583              		.loc 1 297 19 view .LVU201
+ 584 00a4 6065     		str	r0, [r4, #84]
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 585              		.loc 1 300 3 is_stmt 1 view .LVU202
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 586              		.loc 1 300 15 is_stmt 0 view .LVU203
+ 587 00a6 0123     		movs	r3, #1
+ 588 00a8 84F83530 		strb	r3, [r4, #53]
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 589              		.loc 1 302 3 is_stmt 1 view .LVU204
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 590              		.loc 1 302 10 is_stmt 0 view .LVU205
+ 591 00ac C9E7     		b	.L33
+ 592              	.LVL63:
+ 593              	.L41:
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 594              		.loc 1 248 5 is_stmt 1 view .LVU206
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 595              		.loc 1 248 23 is_stmt 0 view .LVU207
+ 596 00ae E16A     		ldr	r1, [r4, #44]
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 597              		.loc 1 248 45 view .LVU208
+ 598 00b0 206B     		ldr	r0, [r4, #48]
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 599              		.loc 1 248 33 view .LVU209
+ 600 00b2 0143     		orrs	r1, r1, r0
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 601              		.loc 1 248 9 view .LVU210
+ 602 00b4 0A43     		orrs	r2, r2, r1
+ 603              	.LVL64:
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 604              		.loc 1 248 9 view .LVU211
+ 605 00b6 DBE7     		b	.L36
+ 606              	.LVL65:
+ 607              	.L42:
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 608              		.loc 1 276 9 is_stmt 1 view .LVU212
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 609              		.loc 1 276 25 is_stmt 0 view .LVU213
+ARM GAS  /tmp/ccRPwCnE.s 			page 37
+
+
+ 610 00b8 4023     		movs	r3, #64
+ 611 00ba 6365     		str	r3, [r4, #84]
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 612              		.loc 1 279 9 is_stmt 1 view .LVU214
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 613              		.loc 1 279 21 is_stmt 0 view .LVU215
+ 614 00bc 0023     		movs	r3, #0
+ 615 00be 84F83530 		strb	r3, [r4, #53]
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 616              		.loc 1 281 9 is_stmt 1 view .LVU216
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 617              		.loc 1 281 16 is_stmt 0 view .LVU217
+ 618 00c2 0120     		movs	r0, #1
+ 619 00c4 BDE7     		b	.L33
+ 620              	.LVL66:
+ 621              	.L38:
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 622              		.loc 1 180 12 view .LVU218
+ 623 00c6 0120     		movs	r0, #1
+ 624              	.LVL67:
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 625              		.loc 1 180 12 view .LVU219
+ 626 00c8 BBE7     		b	.L33
+ 627              	.L44:
+ 628 00ca 00BF     		.align	2
+ 629              	.L43:
+ 630 00cc 3F8010E0 		.word	-535789505
+ 631              		.cfi_endproc
+ 632              	.LFE141:
+ 634              		.section	.text.HAL_DMA_DeInit,"ax",%progbits
+ 635              		.align	1
+ 636              		.global	HAL_DMA_DeInit
+ 637              		.syntax unified
+ 638              		.thumb
+ 639              		.thumb_func
+ 640              		.fpu fpv5-d16
+ 642              	HAL_DMA_DeInit:
+ 643              	.LVL68:
+ 644              	.LFB142:
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   DMA_Base_Registers *regs;
+ 645              		.loc 1 312 1 is_stmt 1 view -0
+ 646              		.cfi_startproc
+ 647              		@ args = 0, pretend = 0, frame = 0
+ 648              		@ frame_needed = 0, uses_anonymous_args = 0
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 649              		.loc 1 313 3 view .LVU221
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 650              		.loc 1 316 3 view .LVU222
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 651              		.loc 1 316 5 is_stmt 0 view .LVU223
+ 652 0000 0028     		cmp	r0, #0
+ 653 0002 2DD0     		beq	.L47
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   DMA_Base_Registers *regs;
+ 654              		.loc 1 312 1 view .LVU224
+ 655 0004 38B5     		push	{r3, r4, r5, lr}
+ 656              	.LCFI7:
+ 657              		.cfi_def_cfa_offset 16
+ARM GAS  /tmp/ccRPwCnE.s 			page 38
+
+
+ 658              		.cfi_offset 3, -16
+ 659              		.cfi_offset 4, -12
+ 660              		.cfi_offset 5, -8
+ 661              		.cfi_offset 14, -4
+ 662 0006 0546     		mov	r5, r0
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 663              		.loc 1 322 3 is_stmt 1 view .LVU225
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 664              		.loc 1 322 10 is_stmt 0 view .LVU226
+ 665 0008 90F83500 		ldrb	r0, [r0, #53]	@ zero_extendqisi2
+ 666              	.LVL69:
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 667              		.loc 1 322 10 view .LVU227
+ 668 000c C0B2     		uxtb	r0, r0
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 669              		.loc 1 322 5 view .LVU228
+ 670 000e 0228     		cmp	r0, #2
+ 671 0010 25D0     		beq	.L46
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 672              		.loc 1 329 3 is_stmt 1 view .LVU229
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 673              		.loc 1 332 3 view .LVU230
+ 674 0012 2A68     		ldr	r2, [r5]
+ 675 0014 1368     		ldr	r3, [r2]
+ 676 0016 23F00103 		bic	r3, r3, #1
+ 677 001a 1360     		str	r3, [r2]
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 678              		.loc 1 335 3 view .LVU231
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 679              		.loc 1 335 7 is_stmt 0 view .LVU232
+ 680 001c 2B68     		ldr	r3, [r5]
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 681              		.loc 1 335 24 view .LVU233
+ 682 001e 0024     		movs	r4, #0
+ 683 0020 1C60     		str	r4, [r3]
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 684              		.loc 1 338 3 is_stmt 1 view .LVU234
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 685              		.loc 1 338 7 is_stmt 0 view .LVU235
+ 686 0022 2B68     		ldr	r3, [r5]
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 687              		.loc 1 338 24 view .LVU236
+ 688 0024 5C60     		str	r4, [r3, #4]
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 689              		.loc 1 341 3 is_stmt 1 view .LVU237
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 690              		.loc 1 341 7 is_stmt 0 view .LVU238
+ 691 0026 2B68     		ldr	r3, [r5]
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 692              		.loc 1 341 24 view .LVU239
+ 693 0028 9C60     		str	r4, [r3, #8]
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 694              		.loc 1 344 3 is_stmt 1 view .LVU240
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 695              		.loc 1 344 7 is_stmt 0 view .LVU241
+ 696 002a 2B68     		ldr	r3, [r5]
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ARM GAS  /tmp/ccRPwCnE.s 			page 39
+
+
+ 697              		.loc 1 344 24 view .LVU242
+ 698 002c DC60     		str	r4, [r3, #12]
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 699              		.loc 1 347 3 is_stmt 1 view .LVU243
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 700              		.loc 1 347 7 is_stmt 0 view .LVU244
+ 701 002e 2B68     		ldr	r3, [r5]
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 702              		.loc 1 347 24 view .LVU245
+ 703 0030 1C61     		str	r4, [r3, #16]
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 704              		.loc 1 350 3 is_stmt 1 view .LVU246
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 705              		.loc 1 350 7 is_stmt 0 view .LVU247
+ 706 0032 2B68     		ldr	r3, [r5]
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 707              		.loc 1 350 24 view .LVU248
+ 708 0034 2122     		movs	r2, #33
+ 709 0036 5A61     		str	r2, [r3, #20]
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 710              		.loc 1 353 3 is_stmt 1 view .LVU249
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 711              		.loc 1 353 32 is_stmt 0 view .LVU250
+ 712 0038 2846     		mov	r0, r5
+ 713 003a FFF7FEFF 		bl	DMA_CalcBaseAndBitshift
+ 714              	.LVL70:
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 715              		.loc 1 356 3 is_stmt 1 view .LVU251
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 716              		.loc 1 356 29 is_stmt 0 view .LVU252
+ 717 003e EA6D     		ldr	r2, [r5, #92]
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 718              		.loc 1 356 22 view .LVU253
+ 719 0040 3F23     		movs	r3, #63
+ 720 0042 9340     		lsls	r3, r3, r2
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 721              		.loc 1 356 14 view .LVU254
+ 722 0044 8360     		str	r3, [r0, #8]
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferHalfCpltCallback = NULL;
+ 723              		.loc 1 359 3 is_stmt 1 view .LVU255
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferHalfCpltCallback = NULL;
+ 724              		.loc 1 359 26 is_stmt 0 view .LVU256
+ 725 0046 EC63     		str	r4, [r5, #60]
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferM1CpltCallback = NULL;
+ 726              		.loc 1 360 3 is_stmt 1 view .LVU257
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferM1CpltCallback = NULL;
+ 727              		.loc 1 360 30 is_stmt 0 view .LVU258
+ 728 0048 2C64     		str	r4, [r5, #64]
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferM1HalfCpltCallback = NULL;
+ 729              		.loc 1 361 3 is_stmt 1 view .LVU259
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferM1HalfCpltCallback = NULL;
+ 730              		.loc 1 361 28 is_stmt 0 view .LVU260
+ 731 004a 6C64     		str	r4, [r5, #68]
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferErrorCallback = NULL;
+ 732              		.loc 1 362 3 is_stmt 1 view .LVU261
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferErrorCallback = NULL;
+ 733              		.loc 1 362 32 is_stmt 0 view .LVU262
+ARM GAS  /tmp/ccRPwCnE.s 			page 40
+
+
+ 734 004c AC64     		str	r4, [r5, #72]
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferAbortCallback = NULL;  
+ 735              		.loc 1 363 3 is_stmt 1 view .LVU263
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   hdma->XferAbortCallback = NULL;  
+ 736              		.loc 1 363 27 is_stmt 0 view .LVU264
+ 737 004e EC64     		str	r4, [r5, #76]
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 738              		.loc 1 364 3 is_stmt 1 view .LVU265
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 739              		.loc 1 364 27 is_stmt 0 view .LVU266
+ 740 0050 2C65     		str	r4, [r5, #80]
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 741              		.loc 1 367 3 is_stmt 1 view .LVU267
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 742              		.loc 1 367 19 is_stmt 0 view .LVU268
+ 743 0052 6C65     		str	r4, [r5, #84]
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 744              		.loc 1 370 3 is_stmt 1 view .LVU269
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 745              		.loc 1 370 15 is_stmt 0 view .LVU270
+ 746 0054 85F83540 		strb	r4, [r5, #53]
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 747              		.loc 1 373 3 is_stmt 1 view .LVU271
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 748              		.loc 1 373 3 view .LVU272
+ 749 0058 85F83440 		strb	r4, [r5, #52]
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 750              		.loc 1 373 3 view .LVU273
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 751              		.loc 1 375 3 view .LVU274
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 752              		.loc 1 375 10 is_stmt 0 view .LVU275
+ 753 005c 2046     		mov	r0, r4
+ 754              	.LVL71:
+ 755              	.L46:
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 756              		.loc 1 376 1 view .LVU276
+ 757 005e 38BD     		pop	{r3, r4, r5, pc}
+ 758              	.LVL72:
+ 759              	.L47:
+ 760              	.LCFI8:
+ 761              		.cfi_def_cfa_offset 0
+ 762              		.cfi_restore 3
+ 763              		.cfi_restore 4
+ 764              		.cfi_restore 5
+ 765              		.cfi_restore 14
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 766              		.loc 1 318 12 view .LVU277
+ 767 0060 0120     		movs	r0, #1
+ 768              	.LVL73:
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 769              		.loc 1 376 1 view .LVU278
+ 770 0062 7047     		bx	lr
+ 771              		.cfi_endproc
+ 772              	.LFE142:
+ 774              		.section	.text.HAL_DMA_Start,"ax",%progbits
+ 775              		.align	1
+ARM GAS  /tmp/ccRPwCnE.s 			page 41
+
+
+ 776              		.global	HAL_DMA_Start
+ 777              		.syntax unified
+ 778              		.thumb
+ 779              		.thumb_func
+ 780              		.fpu fpv5-d16
+ 782              	HAL_DMA_Start:
+ 783              	.LVL74:
+ 784              	.LFB143:
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 785              		.loc 1 410 1 is_stmt 1 view -0
+ 786              		.cfi_startproc
+ 787              		@ args = 0, pretend = 0, frame = 0
+ 788              		@ frame_needed = 0, uses_anonymous_args = 0
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 789              		.loc 1 410 1 is_stmt 0 view .LVU280
+ 790 0000 38B5     		push	{r3, r4, r5, lr}
+ 791              	.LCFI9:
+ 792              		.cfi_def_cfa_offset 16
+ 793              		.cfi_offset 3, -16
+ 794              		.cfi_offset 4, -12
+ 795              		.cfi_offset 5, -8
+ 796              		.cfi_offset 14, -4
+ 797 0002 0446     		mov	r4, r0
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 798              		.loc 1 411 3 is_stmt 1 view .LVU281
+ 799              	.LVL75:
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 800              		.loc 1 414 3 view .LVU282
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 801              		.loc 1 417 3 view .LVU283
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 802              		.loc 1 417 3 view .LVU284
+ 803 0004 90F83400 		ldrb	r0, [r0, #52]	@ zero_extendqisi2
+ 804              	.LVL76:
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 805              		.loc 1 417 3 is_stmt 0 view .LVU285
+ 806 0008 0128     		cmp	r0, #1
+ 807 000a 1BD0     		beq	.L55
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 808              		.loc 1 417 3 is_stmt 1 discriminator 2 view .LVU286
+ 809 000c 0120     		movs	r0, #1
+ 810 000e 84F83400 		strb	r0, [r4, #52]
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 811              		.loc 1 417 3 discriminator 2 view .LVU287
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 812              		.loc 1 419 3 discriminator 2 view .LVU288
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 813              		.loc 1 419 33 is_stmt 0 discriminator 2 view .LVU289
+ 814 0012 94F83500 		ldrb	r0, [r4, #53]	@ zero_extendqisi2
+ 815 0016 C0B2     		uxtb	r0, r0
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 816              		.loc 1 419 5 discriminator 2 view .LVU290
+ 817 0018 0128     		cmp	r0, #1
+ 818 001a 04D0     		beq	.L57
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 819              		.loc 1 436 5 is_stmt 1 view .LVU291
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ARM GAS  /tmp/ccRPwCnE.s 			page 42
+
+
+ 820              		.loc 1 436 5 view .LVU292
+ 821 001c 0023     		movs	r3, #0
+ 822              	.LVL77:
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 823              		.loc 1 436 5 is_stmt 0 view .LVU293
+ 824 001e 84F83430 		strb	r3, [r4, #52]
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 825              		.loc 1 436 5 is_stmt 1 view .LVU294
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   } 
+ 826              		.loc 1 439 5 view .LVU295
+ 827              	.LVL78:
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   } 
+ 828              		.loc 1 439 12 is_stmt 0 view .LVU296
+ 829 0022 0220     		movs	r0, #2
+ 830              	.LVL79:
+ 831              	.L53:
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 832              		.loc 1 442 1 view .LVU297
+ 833 0024 38BD     		pop	{r3, r4, r5, pc}
+ 834              	.LVL80:
+ 835              	.L57:
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 836              		.loc 1 422 5 is_stmt 1 view .LVU298
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 837              		.loc 1 422 17 is_stmt 0 view .LVU299
+ 838 0026 0220     		movs	r0, #2
+ 839 0028 84F83500 		strb	r0, [r4, #53]
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 840              		.loc 1 425 5 is_stmt 1 view .LVU300
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 841              		.loc 1 425 21 is_stmt 0 view .LVU301
+ 842 002c 0025     		movs	r5, #0
+ 843 002e 6565     		str	r5, [r4, #84]
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 844              		.loc 1 428 5 is_stmt 1 view .LVU302
+ 845 0030 2046     		mov	r0, r4
+ 846 0032 FFF7FEFF 		bl	DMA_SetConfig
+ 847              	.LVL81:
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 848              		.loc 1 431 5 view .LVU303
+ 849 0036 2268     		ldr	r2, [r4]
+ 850 0038 1368     		ldr	r3, [r2]
+ 851 003a 43F00103 		orr	r3, r3, #1
+ 852 003e 1360     		str	r3, [r2]
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 853              		.loc 1 411 21 is_stmt 0 view .LVU304
+ 854 0040 2846     		mov	r0, r5
+ 855 0042 EFE7     		b	.L53
+ 856              	.LVL82:
+ 857              	.L55:
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 858              		.loc 1 417 3 view .LVU305
+ 859 0044 0220     		movs	r0, #2
+ 860 0046 EDE7     		b	.L53
+ 861              		.cfi_endproc
+ 862              	.LFE143:
+ 864              		.section	.text.HAL_DMA_Start_IT,"ax",%progbits
+ARM GAS  /tmp/ccRPwCnE.s 			page 43
+
+
+ 865              		.align	1
+ 866              		.global	HAL_DMA_Start_IT
+ 867              		.syntax unified
+ 868              		.thumb
+ 869              		.thumb_func
+ 870              		.fpu fpv5-d16
+ 872              	HAL_DMA_Start_IT:
+ 873              	.LVL83:
+ 874              	.LFB144:
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 875              		.loc 1 454 1 is_stmt 1 view -0
+ 876              		.cfi_startproc
+ 877              		@ args = 0, pretend = 0, frame = 0
+ 878              		@ frame_needed = 0, uses_anonymous_args = 0
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 879              		.loc 1 454 1 is_stmt 0 view .LVU307
+ 880 0000 38B5     		push	{r3, r4, r5, lr}
+ 881              	.LCFI10:
+ 882              		.cfi_def_cfa_offset 16
+ 883              		.cfi_offset 3, -16
+ 884              		.cfi_offset 4, -12
+ 885              		.cfi_offset 5, -8
+ 886              		.cfi_offset 14, -4
+ 887 0002 0446     		mov	r4, r0
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 888              		.loc 1 455 3 is_stmt 1 view .LVU308
+ 889              	.LVL84:
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 890              		.loc 1 458 3 view .LVU309
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 891              		.loc 1 458 56 is_stmt 0 view .LVU310
+ 892 0004 856D     		ldr	r5, [r0, #88]
+ 893              	.LVL85:
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****  
+ 894              		.loc 1 461 3 is_stmt 1 view .LVU311
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 895              		.loc 1 464 3 view .LVU312
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 896              		.loc 1 464 3 view .LVU313
+ 897 0006 90F83400 		ldrb	r0, [r0, #52]	@ zero_extendqisi2
+ 898              	.LVL86:
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 899              		.loc 1 464 3 is_stmt 0 view .LVU314
+ 900 000a 0128     		cmp	r0, #1
+ 901 000c 30D0     		beq	.L62
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 902              		.loc 1 464 3 is_stmt 1 discriminator 2 view .LVU315
+ 903 000e 0120     		movs	r0, #1
+ 904 0010 84F83400 		strb	r0, [r4, #52]
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 905              		.loc 1 464 3 discriminator 2 view .LVU316
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 906              		.loc 1 466 3 discriminator 2 view .LVU317
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 907              		.loc 1 466 33 is_stmt 0 discriminator 2 view .LVU318
+ 908 0014 94F83500 		ldrb	r0, [r4, #53]	@ zero_extendqisi2
+ 909 0018 C0B2     		uxtb	r0, r0
+ARM GAS  /tmp/ccRPwCnE.s 			page 44
+
+
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 910              		.loc 1 466 5 discriminator 2 view .LVU319
+ 911 001a 0128     		cmp	r0, #1
+ 912 001c 04D0     		beq	.L64
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 913              		.loc 1 495 5 is_stmt 1 view .LVU320
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 914              		.loc 1 495 5 view .LVU321
+ 915 001e 0023     		movs	r3, #0
+ 916              	.LVL87:
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 917              		.loc 1 495 5 is_stmt 0 view .LVU322
+ 918 0020 84F83430 		strb	r3, [r4, #52]
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 919              		.loc 1 495 5 is_stmt 1 view .LVU323
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 920              		.loc 1 498 5 view .LVU324
+ 921              	.LVL88:
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 922              		.loc 1 498 12 is_stmt 0 view .LVU325
+ 923 0024 0220     		movs	r0, #2
+ 924              	.LVL89:
+ 925              	.L59:
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 926              		.loc 1 502 1 view .LVU326
+ 927 0026 38BD     		pop	{r3, r4, r5, pc}
+ 928              	.LVL90:
+ 929              	.L64:
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 930              		.loc 1 469 5 is_stmt 1 view .LVU327
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 931              		.loc 1 469 17 is_stmt 0 view .LVU328
+ 932 0028 0220     		movs	r0, #2
+ 933 002a 84F83500 		strb	r0, [r4, #53]
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 934              		.loc 1 472 5 is_stmt 1 view .LVU329
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 935              		.loc 1 472 21 is_stmt 0 view .LVU330
+ 936 002e 0020     		movs	r0, #0
+ 937 0030 6065     		str	r0, [r4, #84]
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 938              		.loc 1 475 5 is_stmt 1 view .LVU331
+ 939 0032 2046     		mov	r0, r4
+ 940 0034 FFF7FEFF 		bl	DMA_SetConfig
+ 941              	.LVL91:
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 942              		.loc 1 478 5 view .LVU332
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 943              		.loc 1 478 31 is_stmt 0 view .LVU333
+ 944 0038 E26D     		ldr	r2, [r4, #92]
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 945              		.loc 1 478 24 view .LVU334
+ 946 003a 3F23     		movs	r3, #63
+ 947 003c 9340     		lsls	r3, r3, r2
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 948              		.loc 1 478 16 view .LVU335
+ 949 003e AB60     		str	r3, [r5, #8]
+ARM GAS  /tmp/ccRPwCnE.s 			page 45
+
+
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->FCR |= DMA_IT_FE;
+ 950              		.loc 1 481 5 is_stmt 1 view .LVU336
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->FCR |= DMA_IT_FE;
+ 951              		.loc 1 481 9 is_stmt 0 view .LVU337
+ 952 0040 2268     		ldr	r2, [r4]
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->FCR |= DMA_IT_FE;
+ 953              		.loc 1 481 25 view .LVU338
+ 954 0042 1368     		ldr	r3, [r2]
+ 955 0044 43F01603 		orr	r3, r3, #22
+ 956 0048 1360     		str	r3, [r2]
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 957              		.loc 1 482 5 is_stmt 1 view .LVU339
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 958              		.loc 1 482 9 is_stmt 0 view .LVU340
+ 959 004a 2268     		ldr	r2, [r4]
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 960              		.loc 1 482 25 view .LVU341
+ 961 004c 5369     		ldr	r3, [r2, #20]
+ 962 004e 43F08003 		orr	r3, r3, #128
+ 963 0052 5361     		str	r3, [r2, #20]
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 964              		.loc 1 484 5 is_stmt 1 view .LVU342
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 965              		.loc 1 484 12 is_stmt 0 view .LVU343
+ 966 0054 236C     		ldr	r3, [r4, #64]
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 967              		.loc 1 484 7 view .LVU344
+ 968 0056 23B1     		cbz	r3, .L61
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 969              		.loc 1 486 7 is_stmt 1 view .LVU345
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 970              		.loc 1 486 11 is_stmt 0 view .LVU346
+ 971 0058 2268     		ldr	r2, [r4]
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 972              		.loc 1 486 27 view .LVU347
+ 973 005a 1368     		ldr	r3, [r2]
+ 974 005c 43F00803 		orr	r3, r3, #8
+ 975 0060 1360     		str	r3, [r2]
+ 976              	.L61:
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 977              		.loc 1 490 5 is_stmt 1 view .LVU348
+ 978 0062 2268     		ldr	r2, [r4]
+ 979 0064 1368     		ldr	r3, [r2]
+ 980 0066 43F00103 		orr	r3, r3, #1
+ 981 006a 1360     		str	r3, [r2]
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 982              		.loc 1 455 21 is_stmt 0 view .LVU349
+ 983 006c 0020     		movs	r0, #0
+ 984 006e DAE7     		b	.L59
+ 985              	.LVL92:
+ 986              	.L62:
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 987              		.loc 1 464 3 view .LVU350
+ 988 0070 0220     		movs	r0, #2
+ 989 0072 D8E7     		b	.L59
+ 990              		.cfi_endproc
+ 991              	.LFE144:
+ARM GAS  /tmp/ccRPwCnE.s 			page 46
+
+
+ 993              		.section	.text.HAL_DMA_Abort,"ax",%progbits
+ 994              		.align	1
+ 995              		.global	HAL_DMA_Abort
+ 996              		.syntax unified
+ 997              		.thumb
+ 998              		.thumb_func
+ 999              		.fpu fpv5-d16
+ 1001              	HAL_DMA_Abort:
+ 1002              	.LVL93:
+ 1003              	.LFB145:
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* calculate DMA base and stream number */
+ 1004              		.loc 1 517 1 is_stmt 1 view -0
+ 1005              		.cfi_startproc
+ 1006              		@ args = 0, pretend = 0, frame = 0
+ 1007              		@ frame_needed = 0, uses_anonymous_args = 0
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   /* calculate DMA base and stream number */
+ 1008              		.loc 1 517 1 is_stmt 0 view .LVU352
+ 1009 0000 70B5     		push	{r4, r5, r6, lr}
+ 1010              	.LCFI11:
+ 1011              		.cfi_def_cfa_offset 16
+ 1012              		.cfi_offset 4, -16
+ 1013              		.cfi_offset 5, -12
+ 1014              		.cfi_offset 6, -8
+ 1015              		.cfi_offset 14, -4
+ 1016 0002 0446     		mov	r4, r0
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 1017              		.loc 1 519 3 is_stmt 1 view .LVU353
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 1018              		.loc 1 519 56 is_stmt 0 view .LVU354
+ 1019 0004 866D     		ldr	r6, [r0, #88]
+ 1020              	.LVL94:
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 1021              		.loc 1 521 3 is_stmt 1 view .LVU355
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 1022              		.loc 1 521 24 is_stmt 0 view .LVU356
+ 1023 0006 FFF7FEFF 		bl	HAL_GetTick
+ 1024              	.LVL95:
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1025              		.loc 1 523 3 is_stmt 1 view .LVU357
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1026              		.loc 1 523 10 is_stmt 0 view .LVU358
+ 1027 000a 94F83530 		ldrb	r3, [r4, #53]	@ zero_extendqisi2
+ 1028 000e DBB2     		uxtb	r3, r3
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1029              		.loc 1 523 5 view .LVU359
+ 1030 0010 022B     		cmp	r3, #2
+ 1031 0012 06D0     		beq	.L66
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1032              		.loc 1 525 5 is_stmt 1 view .LVU360
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1033              		.loc 1 525 21 is_stmt 0 view .LVU361
+ 1034 0014 8023     		movs	r3, #128
+ 1035 0016 6365     		str	r3, [r4, #84]
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1036              		.loc 1 528 5 is_stmt 1 view .LVU362
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1037              		.loc 1 528 5 view .LVU363
+ARM GAS  /tmp/ccRPwCnE.s 			page 47
+
+
+ 1038 0018 0023     		movs	r3, #0
+ 1039 001a 84F83430 		strb	r3, [r4, #52]
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1040              		.loc 1 528 5 view .LVU364
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1041              		.loc 1 530 5 view .LVU365
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1042              		.loc 1 530 12 is_stmt 0 view .LVU366
+ 1043 001e 0120     		movs	r0, #1
+ 1044              	.LVL96:
+ 1045              	.L67:
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1046              		.loc 1 576 1 view .LVU367
+ 1047 0020 70BD     		pop	{r4, r5, r6, pc}
+ 1048              	.LVL97:
+ 1049              	.L66:
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1050              		.loc 1 576 1 view .LVU368
+ 1051 0022 0546     		mov	r5, r0
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->FCR &= ~(DMA_IT_FE);
+ 1052              		.loc 1 535 5 is_stmt 1 view .LVU369
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->FCR &= ~(DMA_IT_FE);
+ 1053              		.loc 1 535 9 is_stmt 0 view .LVU370
+ 1054 0024 2268     		ldr	r2, [r4]
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     hdma->Instance->FCR &= ~(DMA_IT_FE);
+ 1055              		.loc 1 535 25 view .LVU371
+ 1056 0026 1368     		ldr	r3, [r2]
+ 1057 0028 23F01603 		bic	r3, r3, #22
+ 1058 002c 1360     		str	r3, [r2]
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1059              		.loc 1 536 5 is_stmt 1 view .LVU372
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1060              		.loc 1 536 9 is_stmt 0 view .LVU373
+ 1061 002e 2268     		ldr	r2, [r4]
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1062              		.loc 1 536 25 view .LVU374
+ 1063 0030 5369     		ldr	r3, [r2, #20]
+ 1064 0032 23F08003 		bic	r3, r3, #128
+ 1065 0036 5361     		str	r3, [r2, #20]
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1066              		.loc 1 538 5 is_stmt 1 view .LVU375
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1067              		.loc 1 538 13 is_stmt 0 view .LVU376
+ 1068 0038 236C     		ldr	r3, [r4, #64]
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1069              		.loc 1 538 7 view .LVU377
+ 1070 003a E3B1     		cbz	r3, .L73
+ 1071              	.L68:
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1072              		.loc 1 540 7 is_stmt 1 view .LVU378
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1073              		.loc 1 540 11 is_stmt 0 view .LVU379
+ 1074 003c 2268     		ldr	r2, [r4]
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1075              		.loc 1 540 27 view .LVU380
+ 1076 003e 1368     		ldr	r3, [r2]
+ 1077 0040 23F00803 		bic	r3, r3, #8
+ARM GAS  /tmp/ccRPwCnE.s 			page 48
+
+
+ 1078 0044 1360     		str	r3, [r2]
+ 1079              	.L69:
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1080              		.loc 1 544 5 is_stmt 1 view .LVU381
+ 1081 0046 2268     		ldr	r2, [r4]
+ 1082 0048 1368     		ldr	r3, [r2]
+ 1083 004a 23F00103 		bic	r3, r3, #1
+ 1084 004e 1360     		str	r3, [r2]
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1085              		.loc 1 547 5 view .LVU382
+ 1086              	.LVL98:
+ 1087              	.L70:
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1088              		.loc 1 547 10 view .LVU383
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1089              		.loc 1 547 16 is_stmt 0 view .LVU384
+ 1090 0050 2368     		ldr	r3, [r4]
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1091              		.loc 1 547 26 view .LVU385
+ 1092 0052 1B68     		ldr	r3, [r3]
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1093              		.loc 1 547 10 view .LVU386
+ 1094 0054 13F0010F 		tst	r3, #1
+ 1095 0058 11D0     		beq	.L74
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1096              		.loc 1 550 7 is_stmt 1 view .LVU387
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1097              		.loc 1 550 11 is_stmt 0 view .LVU388
+ 1098 005a FFF7FEFF 		bl	HAL_GetTick
+ 1099              	.LVL99:
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1100              		.loc 1 550 25 view .LVU389
+ 1101 005e 431B     		subs	r3, r0, r5
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1102              		.loc 1 550 9 view .LVU390
+ 1103 0060 052B     		cmp	r3, #5
+ 1104 0062 F5D9     		bls	.L70
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 1105              		.loc 1 553 9 is_stmt 1 view .LVU391
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 1106              		.loc 1 553 25 is_stmt 0 view .LVU392
+ 1107 0064 2023     		movs	r3, #32
+ 1108 0066 6365     		str	r3, [r4, #84]
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 1109              		.loc 1 556 9 is_stmt 1 view .LVU393
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 1110              		.loc 1 556 21 is_stmt 0 view .LVU394
+ 1111 0068 0320     		movs	r0, #3
+ 1112 006a 84F83500 		strb	r0, [r4, #53]
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1113              		.loc 1 559 9 is_stmt 1 view .LVU395
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1114              		.loc 1 559 9 view .LVU396
+ 1115 006e 0023     		movs	r3, #0
+ 1116 0070 84F83430 		strb	r3, [r4, #52]
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1117              		.loc 1 559 9 view .LVU397
+ARM GAS  /tmp/ccRPwCnE.s 			page 49
+
+
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 1118              		.loc 1 561 9 view .LVU398
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 1119              		.loc 1 561 16 is_stmt 0 view .LVU399
+ 1120 0074 D4E7     		b	.L67
+ 1121              	.LVL100:
+ 1122              	.L73:
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1123              		.loc 1 538 53 discriminator 1 view .LVU400
+ 1124 0076 A36C     		ldr	r3, [r4, #72]
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1125              		.loc 1 538 45 discriminator 1 view .LVU401
+ 1126 0078 002B     		cmp	r3, #0
+ 1127 007a DFD1     		bne	.L68
+ 1128 007c E3E7     		b	.L69
+ 1129              	.LVL101:
+ 1130              	.L74:
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1131              		.loc 1 566 5 is_stmt 1 view .LVU402
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1132              		.loc 1 566 31 is_stmt 0 view .LVU403
+ 1133 007e E26D     		ldr	r2, [r4, #92]
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1134              		.loc 1 566 24 view .LVU404
+ 1135 0080 3F23     		movs	r3, #63
+ 1136 0082 9340     		lsls	r3, r3, r2
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1137              		.loc 1 566 16 view .LVU405
+ 1138 0084 B360     		str	r3, [r6, #8]
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1139              		.loc 1 569 5 is_stmt 1 view .LVU406
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1140              		.loc 1 569 17 is_stmt 0 view .LVU407
+ 1141 0086 0123     		movs	r3, #1
+ 1142 0088 84F83530 		strb	r3, [r4, #53]
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1143              		.loc 1 572 5 is_stmt 1 view .LVU408
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1144              		.loc 1 572 5 view .LVU409
+ 1145 008c 0020     		movs	r0, #0
+ 1146 008e 84F83400 		strb	r0, [r4, #52]
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1147              		.loc 1 572 5 view .LVU410
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 1148              		.loc 1 575 3 view .LVU411
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 1149              		.loc 1 575 10 is_stmt 0 view .LVU412
+ 1150 0092 C5E7     		b	.L67
+ 1151              		.cfi_endproc
+ 1152              	.LFE145:
+ 1154              		.section	.text.HAL_DMA_Abort_IT,"ax",%progbits
+ 1155              		.align	1
+ 1156              		.global	HAL_DMA_Abort_IT
+ 1157              		.syntax unified
+ 1158              		.thumb
+ 1159              		.thumb_func
+ 1160              		.fpu fpv5-d16
+ARM GAS  /tmp/ccRPwCnE.s 			page 50
+
+
+ 1162              	HAL_DMA_Abort_IT:
+ 1163              	.LVL102:
+ 1164              	.LFB146:
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   if(hdma->State != HAL_DMA_STATE_BUSY)
+ 1165              		.loc 1 585 1 is_stmt 1 view -0
+ 1166              		.cfi_startproc
+ 1167              		@ args = 0, pretend = 0, frame = 0
+ 1168              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1169              		@ link register save eliminated.
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1170              		.loc 1 586 3 view .LVU414
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1171              		.loc 1 586 10 is_stmt 0 view .LVU415
+ 1172 0000 90F83530 		ldrb	r3, [r0, #53]	@ zero_extendqisi2
+ 1173 0004 DBB2     		uxtb	r3, r3
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1174              		.loc 1 586 5 view .LVU416
+ 1175 0006 022B     		cmp	r3, #2
+ 1176 0008 03D0     		beq	.L76
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 1177              		.loc 1 588 5 is_stmt 1 view .LVU417
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 1178              		.loc 1 588 21 is_stmt 0 view .LVU418
+ 1179 000a 8023     		movs	r3, #128
+ 1180 000c 4365     		str	r3, [r0, #84]
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1181              		.loc 1 589 5 is_stmt 1 view .LVU419
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1182              		.loc 1 589 12 is_stmt 0 view .LVU420
+ 1183 000e 0120     		movs	r0, #1
+ 1184              	.LVL103:
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1185              		.loc 1 589 12 view .LVU421
+ 1186 0010 7047     		bx	lr
+ 1187              	.LVL104:
+ 1188              	.L76:
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1189              		.loc 1 594 5 is_stmt 1 view .LVU422
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1190              		.loc 1 594 17 is_stmt 0 view .LVU423
+ 1191 0012 0523     		movs	r3, #5
+ 1192 0014 80F83530 		strb	r3, [r0, #53]
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1193              		.loc 1 597 5 is_stmt 1 view .LVU424
+ 1194 0018 0268     		ldr	r2, [r0]
+ 1195 001a 1368     		ldr	r3, [r2]
+ 1196 001c 23F00103 		bic	r3, r3, #1
+ 1197 0020 1360     		str	r3, [r2]
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 1198              		.loc 1 600 3 view .LVU425
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 1199              		.loc 1 600 10 is_stmt 0 view .LVU426
+ 1200 0022 0020     		movs	r0, #0
+ 1201              	.LVL105:
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1202              		.loc 1 601 1 view .LVU427
+ 1203 0024 7047     		bx	lr
+ARM GAS  /tmp/ccRPwCnE.s 			page 51
+
+
+ 1204              		.cfi_endproc
+ 1205              	.LFE146:
+ 1207              		.section	.text.HAL_DMA_PollForTransfer,"ax",%progbits
+ 1208              		.align	1
+ 1209              		.global	HAL_DMA_PollForTransfer
+ 1210              		.syntax unified
+ 1211              		.thumb
+ 1212              		.thumb_func
+ 1213              		.fpu fpv5-d16
+ 1215              	HAL_DMA_PollForTransfer:
+ 1216              	.LVL106:
+ 1217              	.LFB147:
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK; 
+ 1218              		.loc 1 615 1 is_stmt 1 view -0
+ 1219              		.cfi_startproc
+ 1220              		@ args = 0, pretend = 0, frame = 0
+ 1221              		@ frame_needed = 0, uses_anonymous_args = 0
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK; 
+ 1222              		.loc 1 615 1 is_stmt 0 view .LVU429
+ 1223 0000 2DE9F047 		push	{r4, r5, r6, r7, r8, r9, r10, lr}
+ 1224              	.LCFI12:
+ 1225              		.cfi_def_cfa_offset 32
+ 1226              		.cfi_offset 4, -32
+ 1227              		.cfi_offset 5, -28
+ 1228              		.cfi_offset 6, -24
+ 1229              		.cfi_offset 7, -20
+ 1230              		.cfi_offset 8, -16
+ 1231              		.cfi_offset 9, -12
+ 1232              		.cfi_offset 10, -8
+ 1233              		.cfi_offset 14, -4
+ 1234 0004 0446     		mov	r4, r0
+ 1235 0006 8846     		mov	r8, r1
+ 1236 0008 1646     		mov	r6, r2
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t mask_cpltlevel;
+ 1237              		.loc 1 616 3 is_stmt 1 view .LVU430
+ 1238              	.LVL107:
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tickstart = HAL_GetTick(); 
+ 1239              		.loc 1 617 3 view .LVU431
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmpisr;
+ 1240              		.loc 1 618 3 view .LVU432
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmpisr;
+ 1241              		.loc 1 618 24 is_stmt 0 view .LVU433
+ 1242 000a FFF7FEFF 		bl	HAL_GetTick
+ 1243              	.LVL108:
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 1244              		.loc 1 619 3 is_stmt 1 view .LVU434
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1245              		.loc 1 622 3 view .LVU435
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1246              		.loc 1 624 3 view .LVU436
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1247              		.loc 1 624 32 is_stmt 0 view .LVU437
+ 1248 000e 94F83530 		ldrb	r3, [r4, #53]	@ zero_extendqisi2
+ 1249 0012 DBB2     		uxtb	r3, r3
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1250              		.loc 1 624 5 view .LVU438
+ 1251 0014 022B     		cmp	r3, #2
+ARM GAS  /tmp/ccRPwCnE.s 			page 52
+
+
+ 1252 0016 07D0     		beq	.L79
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 1253              		.loc 1 627 5 is_stmt 1 view .LVU439
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     __HAL_UNLOCK(hdma);
+ 1254              		.loc 1 627 21 is_stmt 0 view .LVU440
+ 1255 0018 8023     		movs	r3, #128
+ 1256 001a 6365     		str	r3, [r4, #84]
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 1257              		.loc 1 628 5 is_stmt 1 view .LVU441
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 1258              		.loc 1 628 5 view .LVU442
+ 1259 001c 0023     		movs	r3, #0
+ 1260 001e 84F83430 		strb	r3, [r4, #52]
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 1261              		.loc 1 628 5 view .LVU443
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1262              		.loc 1 629 5 view .LVU444
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1263              		.loc 1 629 12 is_stmt 0 view .LVU445
+ 1264 0022 0120     		movs	r0, #1
+ 1265              	.LVL109:
+ 1266              	.L80:
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1267              		.loc 1 743 1 view .LVU446
+ 1268 0024 BDE8F087 		pop	{r4, r5, r6, r7, r8, r9, r10, pc}
+ 1269              	.LVL110:
+ 1270              	.L79:
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1271              		.loc 1 743 1 view .LVU447
+ 1272 0028 8146     		mov	r9, r0
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1273              		.loc 1 633 3 is_stmt 1 view .LVU448
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1274              		.loc 1 633 12 is_stmt 0 view .LVU449
+ 1275 002a 2368     		ldr	r3, [r4]
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1276              		.loc 1 633 22 view .LVU450
+ 1277 002c 1B68     		ldr	r3, [r3]
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1278              		.loc 1 633 6 view .LVU451
+ 1279 002e 13F4807F 		tst	r3, #256
+ 1280 0032 3BD1     		bne	.L95
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1281              		.loc 1 640 3 is_stmt 1 view .LVU452
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1282              		.loc 1 640 5 is_stmt 0 view .LVU453
+ 1283 0034 B8F1000F 		cmp	r8, #0
+ 1284 0038 3DD1     		bne	.L82
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1285              		.loc 1 643 5 is_stmt 1 view .LVU454
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1286              		.loc 1 643 46 is_stmt 0 view .LVU455
+ 1287 003a E36D     		ldr	r3, [r4, #92]
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1288              		.loc 1 643 20 view .LVU456
+ 1289 003c 4FF0200A 		mov	r10, #32
+ 1290 0040 0AFA03FA 		lsl	r10, r10, r3
+ARM GAS  /tmp/ccRPwCnE.s 			page 53
+
+
+ 1291              	.LVL111:
+ 1292              	.L83:
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   tmpisr = regs->ISR;
+ 1293              		.loc 1 651 3 is_stmt 1 view .LVU457
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   tmpisr = regs->ISR;
+ 1294              		.loc 1 651 36 is_stmt 0 view .LVU458
+ 1295 0044 A76D     		ldr	r7, [r4, #88]
+ 1296              	.LVL112:
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 1297              		.loc 1 652 3 is_stmt 1 view .LVU459
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 1298              		.loc 1 652 10 is_stmt 0 view .LVU460
+ 1299 0046 3B68     		ldr	r3, [r7]
+ 1300              	.LVL113:
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1301              		.loc 1 654 3 is_stmt 1 view .LVU461
+ 1302              	.L84:
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1303              		.loc 1 654 8 view .LVU462
+ 1304 0048 1AEA030F 		tst	r10, r3
+ 1305 004c 43D1     		bne	.L90
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1306              		.loc 1 654 55 is_stmt 0 discriminator 1 view .LVU463
+ 1307 004e 636D     		ldr	r3, [r4, #84]
+ 1308              	.LVL114:
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1309              		.loc 1 654 46 discriminator 1 view .LVU464
+ 1310 0050 13F0010F 		tst	r3, #1
+ 1311 0054 3FD1     		bne	.L90
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1312              		.loc 1 657 5 is_stmt 1 view .LVU465
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1313              		.loc 1 657 7 is_stmt 0 view .LVU466
+ 1314 0056 B6F1FF3F 		cmp	r6, #-1
+ 1315 005a 07D0     		beq	.L85
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1316              		.loc 1 659 7 is_stmt 1 view .LVU467
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1317              		.loc 1 659 9 is_stmt 0 view .LVU468
+ 1318 005c 002E     		cmp	r6, #0
+ 1319 005e 30D0     		beq	.L86
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1320              		.loc 1 659 28 discriminator 1 view .LVU469
+ 1321 0060 FFF7FEFF 		bl	HAL_GetTick
+ 1322              	.LVL115:
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1323              		.loc 1 659 42 discriminator 1 view .LVU470
+ 1324 0064 A0EB0900 		sub	r0, r0, r9
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1325              		.loc 1 659 24 discriminator 1 view .LVU471
+ 1326 0068 B042     		cmp	r0, r6
+ 1327 006a 2AD8     		bhi	.L86
+ 1328              	.L85:
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1329              		.loc 1 675 5 is_stmt 1 view .LVU472
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1330              		.loc 1 675 12 is_stmt 0 view .LVU473
+ARM GAS  /tmp/ccRPwCnE.s 			page 54
+
+
+ 1331 006c 3B68     		ldr	r3, [r7]
+ 1332              	.LVL116:
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1333              		.loc 1 677 5 is_stmt 1 view .LVU474
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1334              		.loc 1 677 43 is_stmt 0 view .LVU475
+ 1335 006e E16D     		ldr	r1, [r4, #92]
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1336              		.loc 1 677 36 view .LVU476
+ 1337 0070 0822     		movs	r2, #8
+ 1338 0072 8A40     		lsls	r2, r2, r1
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1339              		.loc 1 677 7 view .LVU477
+ 1340 0074 1A42     		tst	r2, r3
+ 1341 0076 04D0     		beq	.L87
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1342              		.loc 1 680 7 is_stmt 1 view .LVU478
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1343              		.loc 1 680 23 is_stmt 0 view .LVU479
+ 1344 0078 616D     		ldr	r1, [r4, #84]
+ 1345 007a 41F00101 		orr	r1, r1, #1
+ 1346 007e 6165     		str	r1, [r4, #84]
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1347              		.loc 1 683 7 is_stmt 1 view .LVU480
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1348              		.loc 1 683 18 is_stmt 0 view .LVU481
+ 1349 0080 BA60     		str	r2, [r7, #8]
+ 1350              	.L87:
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1351              		.loc 1 686 5 is_stmt 1 view .LVU482
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1352              		.loc 1 686 43 is_stmt 0 view .LVU483
+ 1353 0082 E16D     		ldr	r1, [r4, #92]
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1354              		.loc 1 686 36 view .LVU484
+ 1355 0084 0122     		movs	r2, #1
+ 1356 0086 8A40     		lsls	r2, r2, r1
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1357              		.loc 1 686 7 view .LVU485
+ 1358 0088 1A42     		tst	r2, r3
+ 1359 008a 04D0     		beq	.L88
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1360              		.loc 1 689 7 is_stmt 1 view .LVU486
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1361              		.loc 1 689 23 is_stmt 0 view .LVU487
+ 1362 008c 616D     		ldr	r1, [r4, #84]
+ 1363 008e 41F00201 		orr	r1, r1, #2
+ 1364 0092 6165     		str	r1, [r4, #84]
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1365              		.loc 1 692 7 is_stmt 1 view .LVU488
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1366              		.loc 1 692 18 is_stmt 0 view .LVU489
+ 1367 0094 BA60     		str	r2, [r7, #8]
+ 1368              	.L88:
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1369              		.loc 1 695 5 is_stmt 1 view .LVU490
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ARM GAS  /tmp/ccRPwCnE.s 			page 55
+
+
+ 1370              		.loc 1 695 44 is_stmt 0 view .LVU491
+ 1371 0096 E26D     		ldr	r2, [r4, #92]
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1372              		.loc 1 695 37 view .LVU492
+ 1373 0098 0425     		movs	r5, #4
+ 1374 009a 9540     		lsls	r5, r5, r2
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1375              		.loc 1 695 7 view .LVU493
+ 1376 009c 1D42     		tst	r5, r3
+ 1377 009e D3D0     		beq	.L84
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1378              		.loc 1 698 7 is_stmt 1 view .LVU494
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1379              		.loc 1 698 23 is_stmt 0 view .LVU495
+ 1380 00a0 626D     		ldr	r2, [r4, #84]
+ 1381 00a2 42F00402 		orr	r2, r2, #4
+ 1382 00a6 6265     		str	r2, [r4, #84]
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1383              		.loc 1 701 7 is_stmt 1 view .LVU496
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1384              		.loc 1 701 18 is_stmt 0 view .LVU497
+ 1385 00a8 BD60     		str	r5, [r7, #8]
+ 1386 00aa CDE7     		b	.L84
+ 1387              	.LVL117:
+ 1388              	.L95:
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 1389              		.loc 1 635 5 is_stmt 1 view .LVU498
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     return HAL_ERROR;
+ 1390              		.loc 1 635 21 is_stmt 0 view .LVU499
+ 1391 00ac 4FF48073 		mov	r3, #256
+ 1392 00b0 6365     		str	r3, [r4, #84]
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1393              		.loc 1 636 5 is_stmt 1 view .LVU500
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1394              		.loc 1 636 12 is_stmt 0 view .LVU501
+ 1395 00b2 0120     		movs	r0, #1
+ 1396              	.LVL118:
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1397              		.loc 1 636 12 view .LVU502
+ 1398 00b4 B6E7     		b	.L80
+ 1399              	.LVL119:
+ 1400              	.L82:
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1401              		.loc 1 648 5 is_stmt 1 view .LVU503
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1402              		.loc 1 648 46 is_stmt 0 view .LVU504
+ 1403 00b6 E36D     		ldr	r3, [r4, #92]
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1404              		.loc 1 648 20 view .LVU505
+ 1405 00b8 4FF0100A 		mov	r10, #16
+ 1406 00bc 0AFA03FA 		lsl	r10, r10, r3
+ 1407              	.LVL120:
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1408              		.loc 1 648 20 view .LVU506
+ 1409 00c0 C0E7     		b	.L83
+ 1410              	.LVL121:
+ 1411              	.L86:
+ARM GAS  /tmp/ccRPwCnE.s 			page 56
+
+
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 1412              		.loc 1 662 9 is_stmt 1 view .LVU507
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 1413              		.loc 1 662 25 is_stmt 0 view .LVU508
+ 1414 00c2 2023     		movs	r3, #32
+ 1415 00c4 6365     		str	r3, [r4, #84]
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1416              		.loc 1 665 9 is_stmt 1 view .LVU509
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1417              		.loc 1 665 21 is_stmt 0 view .LVU510
+ 1418 00c6 0123     		movs	r3, #1
+ 1419 00c8 84F83530 		strb	r3, [r4, #53]
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1420              		.loc 1 668 9 is_stmt 1 view .LVU511
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1421              		.loc 1 668 9 view .LVU512
+ 1422 00cc 0023     		movs	r3, #0
+ 1423 00ce 84F83430 		strb	r3, [r4, #52]
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1424              		.loc 1 668 9 view .LVU513
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 1425              		.loc 1 670 9 view .LVU514
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 1426              		.loc 1 670 16 is_stmt 0 view .LVU515
+ 1427 00d2 0320     		movs	r0, #3
+ 1428 00d4 A6E7     		b	.L80
+ 1429              	.L90:
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1430              		.loc 1 705 3 is_stmt 1 view .LVU516
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1431              		.loc 1 705 10 is_stmt 0 view .LVU517
+ 1432 00d6 636D     		ldr	r3, [r4, #84]
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1433              		.loc 1 705 5 view .LVU518
+ 1434 00d8 1BB1     		cbz	r3, .L92
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1435              		.loc 1 707 5 is_stmt 1 view .LVU519
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1436              		.loc 1 707 13 is_stmt 0 view .LVU520
+ 1437 00da 636D     		ldr	r3, [r4, #84]
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1438              		.loc 1 707 7 view .LVU521
+ 1439 00dc 13F0010F 		tst	r3, #1
+ 1440 00e0 0ED1     		bne	.L96
+ 1441              	.L92:
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1442              		.loc 1 725 3 is_stmt 1 view .LVU522
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1443              		.loc 1 725 5 is_stmt 0 view .LVU523
+ 1444 00e2 B8F1000F 		cmp	r8, #0
+ 1445 00e6 19D1     		bne	.L93
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1446              		.loc 1 728 5 is_stmt 1 view .LVU524
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1447              		.loc 1 728 63 is_stmt 0 view .LVU525
+ 1448 00e8 E26D     		ldr	r2, [r4, #92]
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ARM GAS  /tmp/ccRPwCnE.s 			page 57
+
+
+ 1449              		.loc 1 728 56 view .LVU526
+ 1450 00ea 3023     		movs	r3, #48
+ 1451 00ec 9340     		lsls	r3, r3, r2
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1452              		.loc 1 728 16 view .LVU527
+ 1453 00ee BB60     		str	r3, [r7, #8]
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1454              		.loc 1 730 5 is_stmt 1 view .LVU528
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1455              		.loc 1 730 17 is_stmt 0 view .LVU529
+ 1456 00f0 0123     		movs	r3, #1
+ 1457 00f2 84F83530 		strb	r3, [r4, #53]
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1458              		.loc 1 733 5 is_stmt 1 view .LVU530
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1459              		.loc 1 733 5 view .LVU531
+ 1460 00f6 0023     		movs	r3, #0
+ 1461 00f8 84F83430 		strb	r3, [r4, #52]
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1462              		.loc 1 733 5 view .LVU532
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 1463              		.loc 1 742 10 is_stmt 0 view .LVU533
+ 1464 00fc 4046     		mov	r0, r8
+ 1465 00fe 91E7     		b	.L80
+ 1466              	.L96:
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1467              		.loc 1 709 7 is_stmt 1 view .LVU534
+ 1468 0100 2046     		mov	r0, r4
+ 1469 0102 FFF7FEFF 		bl	HAL_DMA_Abort
+ 1470              	.LVL122:
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1471              		.loc 1 712 7 view .LVU535
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1472              		.loc 1 712 65 is_stmt 0 view .LVU536
+ 1473 0106 E26D     		ldr	r2, [r4, #92]
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1474              		.loc 1 712 58 view .LVU537
+ 1475 0108 3023     		movs	r3, #48
+ 1476 010a 9340     		lsls	r3, r3, r2
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     
+ 1477              		.loc 1 712 18 view .LVU538
+ 1478 010c BB60     		str	r3, [r7, #8]
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1479              		.loc 1 715 7 is_stmt 1 view .LVU539
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1480              		.loc 1 715 18 is_stmt 0 view .LVU540
+ 1481 010e 0120     		movs	r0, #1
+ 1482 0110 84F83500 		strb	r0, [r4, #53]
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1483              		.loc 1 718 7 is_stmt 1 view .LVU541
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1484              		.loc 1 718 7 view .LVU542
+ 1485 0114 0023     		movs	r3, #0
+ 1486 0116 84F83430 		strb	r3, [r4, #52]
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1487              		.loc 1 718 7 view .LVU543
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****    }
+ARM GAS  /tmp/ccRPwCnE.s 			page 58
+
+
+ 1488              		.loc 1 720 7 view .LVU544
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****    }
+ 1489              		.loc 1 720 14 is_stmt 0 view .LVU545
+ 1490 011a 83E7     		b	.L80
+ 1491              	.L93:
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1492              		.loc 1 739 5 is_stmt 1 view .LVU546
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1493              		.loc 1 739 44 is_stmt 0 view .LVU547
+ 1494 011c E26D     		ldr	r2, [r4, #92]
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1495              		.loc 1 739 37 view .LVU548
+ 1496 011e 1023     		movs	r3, #16
+ 1497 0120 9340     		lsls	r3, r3, r2
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1498              		.loc 1 739 16 view .LVU549
+ 1499 0122 BB60     		str	r3, [r7, #8]
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 1500              		.loc 1 742 10 view .LVU550
+ 1501 0124 0020     		movs	r0, #0
+ 1502 0126 7DE7     		b	.L80
+ 1503              		.cfi_endproc
+ 1504              	.LFE147:
+ 1506              		.section	.text.HAL_DMA_IRQHandler,"ax",%progbits
+ 1507              		.align	1
+ 1508              		.global	HAL_DMA_IRQHandler
+ 1509              		.syntax unified
+ 1510              		.thumb
+ 1511              		.thumb_func
+ 1512              		.fpu fpv5-d16
+ 1514              	HAL_DMA_IRQHandler:
+ 1515              	.LVL123:
+ 1516              	.LFB148:
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmpisr;
+ 1517              		.loc 1 752 1 is_stmt 1 view -0
+ 1518              		.cfi_startproc
+ 1519              		@ args = 0, pretend = 0, frame = 8
+ 1520              		@ frame_needed = 0, uses_anonymous_args = 0
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t tmpisr;
+ 1521              		.loc 1 752 1 is_stmt 0 view .LVU552
+ 1522 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 1523              	.LCFI13:
+ 1524              		.cfi_def_cfa_offset 20
+ 1525              		.cfi_offset 4, -20
+ 1526              		.cfi_offset 5, -16
+ 1527              		.cfi_offset 6, -12
+ 1528              		.cfi_offset 7, -8
+ 1529              		.cfi_offset 14, -4
+ 1530 0002 83B0     		sub	sp, sp, #12
+ 1531              	.LCFI14:
+ 1532              		.cfi_def_cfa_offset 32
+ 1533 0004 0446     		mov	r4, r0
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   __IO uint32_t count = 0;
+ 1534              		.loc 1 753 3 is_stmt 1 view .LVU553
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t timeout = SystemCoreClock / 9600;
+ 1535              		.loc 1 754 3 view .LVU554
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   uint32_t timeout = SystemCoreClock / 9600;
+ARM GAS  /tmp/ccRPwCnE.s 			page 59
+
+
+ 1536              		.loc 1 754 17 is_stmt 0 view .LVU555
+ 1537 0006 0023     		movs	r3, #0
+ 1538 0008 0193     		str	r3, [sp, #4]
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1539              		.loc 1 755 3 is_stmt 1 view .LVU556
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1540              		.loc 1 755 38 is_stmt 0 view .LVU557
+ 1541 000a 724B     		ldr	r3, .L120
+ 1542 000c 1D68     		ldr	r5, [r3]
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1543              		.loc 1 755 12 view .LVU558
+ 1544 000e 724B     		ldr	r3, .L120+4
+ 1545 0010 A3FB0535 		umull	r3, r5, r3, r5
+ 1546 0014 AD0A     		lsrs	r5, r5, #10
+ 1547              	.LVL124:
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1548              		.loc 1 758 3 is_stmt 1 view .LVU559
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1549              		.loc 1 758 56 is_stmt 0 view .LVU560
+ 1550 0016 876D     		ldr	r7, [r0, #88]
+ 1551              	.LVL125:
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1552              		.loc 1 760 3 is_stmt 1 view .LVU561
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1553              		.loc 1 760 10 is_stmt 0 view .LVU562
+ 1554 0018 3E68     		ldr	r6, [r7]
+ 1555              	.LVL126:
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1556              		.loc 1 763 3 is_stmt 1 view .LVU563
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1557              		.loc 1 763 42 is_stmt 0 view .LVU564
+ 1558 001a C26D     		ldr	r2, [r0, #92]
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1559              		.loc 1 763 35 view .LVU565
+ 1560 001c 0823     		movs	r3, #8
+ 1561 001e 9340     		lsls	r3, r3, r2
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1562              		.loc 1 763 6 view .LVU566
+ 1563 0020 3342     		tst	r3, r6
+ 1564 0022 10D0     		beq	.L98
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1565              		.loc 1 765 5 is_stmt 1 view .LVU567
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1566              		.loc 1 765 8 is_stmt 0 view .LVU568
+ 1567 0024 0368     		ldr	r3, [r0]
+ 1568 0026 1A68     		ldr	r2, [r3]
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1569              		.loc 1 765 7 view .LVU569
+ 1570 0028 12F0040F 		tst	r2, #4
+ 1571 002c 0BD0     		beq	.L98
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1572              		.loc 1 768 7 is_stmt 1 view .LVU570
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1573              		.loc 1 768 27 is_stmt 0 view .LVU571
+ 1574 002e 1A68     		ldr	r2, [r3]
+ 1575 0030 22F00402 		bic	r2, r2, #4
+ 1576 0034 1A60     		str	r2, [r3]
+ARM GAS  /tmp/ccRPwCnE.s 			page 60
+
+
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1577              		.loc 1 771 7 is_stmt 1 view .LVU572
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1578              		.loc 1 771 44 is_stmt 0 view .LVU573
+ 1579 0036 C26D     		ldr	r2, [r0, #92]
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1580              		.loc 1 771 37 view .LVU574
+ 1581 0038 0823     		movs	r3, #8
+ 1582 003a 9340     		lsls	r3, r3, r2
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1583              		.loc 1 771 18 view .LVU575
+ 1584 003c BB60     		str	r3, [r7, #8]
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1585              		.loc 1 774 7 is_stmt 1 view .LVU576
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1586              		.loc 1 774 23 is_stmt 0 view .LVU577
+ 1587 003e 436D     		ldr	r3, [r0, #84]
+ 1588 0040 43F00103 		orr	r3, r3, #1
+ 1589 0044 4365     		str	r3, [r0, #84]
+ 1590              	.L98:
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1591              		.loc 1 778 3 is_stmt 1 view .LVU578
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1592              		.loc 1 778 42 is_stmt 0 view .LVU579
+ 1593 0046 E26D     		ldr	r2, [r4, #92]
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1594              		.loc 1 778 35 view .LVU580
+ 1595 0048 0123     		movs	r3, #1
+ 1596 004a 9340     		lsls	r3, r3, r2
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1597              		.loc 1 778 6 view .LVU581
+ 1598 004c 3342     		tst	r3, r6
+ 1599 004e 09D0     		beq	.L99
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1600              		.loc 1 780 5 is_stmt 1 view .LVU582
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1601              		.loc 1 780 8 is_stmt 0 view .LVU583
+ 1602 0050 2268     		ldr	r2, [r4]
+ 1603 0052 5269     		ldr	r2, [r2, #20]
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1604              		.loc 1 780 7 view .LVU584
+ 1605 0054 12F0800F 		tst	r2, #128
+ 1606 0058 04D0     		beq	.L99
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1607              		.loc 1 783 7 is_stmt 1 view .LVU585
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1608              		.loc 1 783 18 is_stmt 0 view .LVU586
+ 1609 005a BB60     		str	r3, [r7, #8]
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1610              		.loc 1 786 7 is_stmt 1 view .LVU587
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1611              		.loc 1 786 23 is_stmt 0 view .LVU588
+ 1612 005c 636D     		ldr	r3, [r4, #84]
+ 1613 005e 43F00203 		orr	r3, r3, #2
+ 1614 0062 6365     		str	r3, [r4, #84]
+ 1615              	.L99:
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ARM GAS  /tmp/ccRPwCnE.s 			page 61
+
+
+ 1616              		.loc 1 790 3 is_stmt 1 view .LVU589
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1617              		.loc 1 790 43 is_stmt 0 view .LVU590
+ 1618 0064 E26D     		ldr	r2, [r4, #92]
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1619              		.loc 1 790 36 view .LVU591
+ 1620 0066 0423     		movs	r3, #4
+ 1621 0068 9340     		lsls	r3, r3, r2
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1622              		.loc 1 790 6 view .LVU592
+ 1623 006a 3342     		tst	r3, r6
+ 1624 006c 09D0     		beq	.L100
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1625              		.loc 1 792 5 is_stmt 1 view .LVU593
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1626              		.loc 1 792 8 is_stmt 0 view .LVU594
+ 1627 006e 2268     		ldr	r2, [r4]
+ 1628 0070 1268     		ldr	r2, [r2]
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1629              		.loc 1 792 7 view .LVU595
+ 1630 0072 12F0020F 		tst	r2, #2
+ 1631 0076 04D0     		beq	.L100
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1632              		.loc 1 795 7 is_stmt 1 view .LVU596
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1633              		.loc 1 795 18 is_stmt 0 view .LVU597
+ 1634 0078 BB60     		str	r3, [r7, #8]
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1635              		.loc 1 798 7 is_stmt 1 view .LVU598
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1636              		.loc 1 798 23 is_stmt 0 view .LVU599
+ 1637 007a 636D     		ldr	r3, [r4, #84]
+ 1638 007c 43F00403 		orr	r3, r3, #4
+ 1639 0080 6365     		str	r3, [r4, #84]
+ 1640              	.L100:
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1641              		.loc 1 802 3 is_stmt 1 view .LVU600
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1642              		.loc 1 802 42 is_stmt 0 view .LVU601
+ 1643 0082 E26D     		ldr	r2, [r4, #92]
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1644              		.loc 1 802 35 view .LVU602
+ 1645 0084 1023     		movs	r3, #16
+ 1646 0086 9340     		lsls	r3, r3, r2
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1647              		.loc 1 802 6 view .LVU603
+ 1648 0088 3342     		tst	r3, r6
+ 1649 008a 24D0     		beq	.L101
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1650              		.loc 1 804 5 is_stmt 1 view .LVU604
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1651              		.loc 1 804 8 is_stmt 0 view .LVU605
+ 1652 008c 2268     		ldr	r2, [r4]
+ 1653 008e 1268     		ldr	r2, [r2]
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1654              		.loc 1 804 7 view .LVU606
+ 1655 0090 12F0080F 		tst	r2, #8
+ARM GAS  /tmp/ccRPwCnE.s 			page 62
+
+
+ 1656 0094 1FD0     		beq	.L101
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1657              		.loc 1 807 7 is_stmt 1 view .LVU607
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1658              		.loc 1 807 18 is_stmt 0 view .LVU608
+ 1659 0096 BB60     		str	r3, [r7, #8]
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1660              		.loc 1 810 7 is_stmt 1 view .LVU609
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1661              		.loc 1 810 16 is_stmt 0 view .LVU610
+ 1662 0098 2368     		ldr	r3, [r4]
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1663              		.loc 1 810 26 view .LVU611
+ 1664 009a 1A68     		ldr	r2, [r3]
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1665              		.loc 1 810 9 view .LVU612
+ 1666 009c 12F4802F 		tst	r2, #262144
+ 1667 00a0 0DD0     		beq	.L102
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1668              		.loc 1 813 9 is_stmt 1 view .LVU613
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1669              		.loc 1 813 27 is_stmt 0 view .LVU614
+ 1670 00a2 1B68     		ldr	r3, [r3]
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1671              		.loc 1 813 11 view .LVU615
+ 1672 00a4 13F4002F 		tst	r3, #524288
+ 1673 00a8 04D1     		bne	.L103
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1674              		.loc 1 815 11 is_stmt 1 view .LVU616
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1675              		.loc 1 815 18 is_stmt 0 view .LVU617
+ 1676 00aa 236C     		ldr	r3, [r4, #64]
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1677              		.loc 1 815 13 view .LVU618
+ 1678 00ac 9BB1     		cbz	r3, .L101
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           }
+ 1679              		.loc 1 818 13 is_stmt 1 view .LVU619
+ 1680 00ae 2046     		mov	r0, r4
+ 1681              	.LVL127:
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           }
+ 1682              		.loc 1 818 13 is_stmt 0 view .LVU620
+ 1683 00b0 9847     		blx	r3
+ 1684              	.LVL128:
+ 1685 00b2 10E0     		b	.L101
+ 1686              	.LVL129:
+ 1687              	.L103:
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1688              		.loc 1 824 11 is_stmt 1 view .LVU621
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1689              		.loc 1 824 18 is_stmt 0 view .LVU622
+ 1690 00b4 A36C     		ldr	r3, [r4, #72]
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1691              		.loc 1 824 13 view .LVU623
+ 1692 00b6 73B1     		cbz	r3, .L101
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           }
+ 1693              		.loc 1 827 13 is_stmt 1 view .LVU624
+ 1694 00b8 2046     		mov	r0, r4
+ARM GAS  /tmp/ccRPwCnE.s 			page 63
+
+
+ 1695              	.LVL130:
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           }
+ 1696              		.loc 1 827 13 is_stmt 0 view .LVU625
+ 1697 00ba 9847     		blx	r3
+ 1698              	.LVL131:
+ 1699 00bc 0BE0     		b	.L101
+ 1700              	.LVL132:
+ 1701              	.L102:
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1702              		.loc 1 834 9 is_stmt 1 view .LVU626
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1703              		.loc 1 834 27 is_stmt 0 view .LVU627
+ 1704 00be 1A68     		ldr	r2, [r3]
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1705              		.loc 1 834 11 view .LVU628
+ 1706 00c0 12F4807F 		tst	r2, #256
+ 1707 00c4 03D1     		bne	.L104
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 1708              		.loc 1 837 11 is_stmt 1 view .LVU629
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 1709              		.loc 1 837 31 is_stmt 0 view .LVU630
+ 1710 00c6 1A68     		ldr	r2, [r3]
+ 1711 00c8 22F00802 		bic	r2, r2, #8
+ 1712 00cc 1A60     		str	r2, [r3]
+ 1713              	.L104:
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1714              		.loc 1 840 9 is_stmt 1 view .LVU631
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1715              		.loc 1 840 16 is_stmt 0 view .LVU632
+ 1716 00ce 236C     		ldr	r3, [r4, #64]
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1717              		.loc 1 840 11 view .LVU633
+ 1718 00d0 0BB1     		cbz	r3, .L101
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 1719              		.loc 1 843 11 is_stmt 1 view .LVU634
+ 1720 00d2 2046     		mov	r0, r4
+ 1721              	.LVL133:
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 1722              		.loc 1 843 11 is_stmt 0 view .LVU635
+ 1723 00d4 9847     		blx	r3
+ 1724              	.LVL134:
+ 1725              	.L101:
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1726              		.loc 1 849 3 is_stmt 1 view .LVU636
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1727              		.loc 1 849 42 is_stmt 0 view .LVU637
+ 1728 00d6 E26D     		ldr	r2, [r4, #92]
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1729              		.loc 1 849 35 view .LVU638
+ 1730 00d8 2023     		movs	r3, #32
+ 1731 00da 9340     		lsls	r3, r3, r2
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1732              		.loc 1 849 6 view .LVU639
+ 1733 00dc 3342     		tst	r3, r6
+ 1734 00de 55D0     		beq	.L105
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1735              		.loc 1 851 5 is_stmt 1 view .LVU640
+ARM GAS  /tmp/ccRPwCnE.s 			page 64
+
+
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1736              		.loc 1 851 8 is_stmt 0 view .LVU641
+ 1737 00e0 2268     		ldr	r2, [r4]
+ 1738 00e2 1268     		ldr	r2, [r2]
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1739              		.loc 1 851 7 view .LVU642
+ 1740 00e4 12F0100F 		tst	r2, #16
+ 1741 00e8 50D0     		beq	.L105
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1742              		.loc 1 854 7 is_stmt 1 view .LVU643
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 1743              		.loc 1 854 18 is_stmt 0 view .LVU644
+ 1744 00ea BB60     		str	r3, [r7, #8]
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1745              		.loc 1 856 7 is_stmt 1 view .LVU645
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1746              		.loc 1 856 37 is_stmt 0 view .LVU646
+ 1747 00ec 94F83530 		ldrb	r3, [r4, #53]	@ zero_extendqisi2
+ 1748 00f0 DBB2     		uxtb	r3, r3
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1749              		.loc 1 856 9 view .LVU647
+ 1750 00f2 052B     		cmp	r3, #5
+ 1751 00f4 0ED0     		beq	.L118
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1752              		.loc 1 883 7 is_stmt 1 view .LVU648
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1753              		.loc 1 883 16 is_stmt 0 view .LVU649
+ 1754 00f6 2368     		ldr	r3, [r4]
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1755              		.loc 1 883 26 view .LVU650
+ 1756 00f8 1A68     		ldr	r2, [r3]
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1757              		.loc 1 883 9 view .LVU651
+ 1758 00fa 12F4802F 		tst	r2, #262144
+ 1759 00fe 33D0     		beq	.L111
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1760              		.loc 1 886 9 is_stmt 1 view .LVU652
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1761              		.loc 1 886 27 is_stmt 0 view .LVU653
+ 1762 0100 1B68     		ldr	r3, [r3]
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1763              		.loc 1 886 11 view .LVU654
+ 1764 0102 13F4002F 		tst	r3, #524288
+ 1765 0106 2AD1     		bne	.L112
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1766              		.loc 1 888 11 is_stmt 1 view .LVU655
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1767              		.loc 1 888 18 is_stmt 0 view .LVU656
+ 1768 0108 636C     		ldr	r3, [r4, #68]
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1769              		.loc 1 888 13 view .LVU657
+ 1770 010a 002B     		cmp	r3, #0
+ 1771 010c 3ED0     		beq	.L105
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           }
+ 1772              		.loc 1 891 13 is_stmt 1 view .LVU658
+ 1773 010e 2046     		mov	r0, r4
+ 1774 0110 9847     		blx	r3
+ARM GAS  /tmp/ccRPwCnE.s 			page 65
+
+
+ 1775              	.LVL135:
+ 1776 0112 3BE0     		b	.L105
+ 1777              	.L118:
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->Instance->FCR &= ~(DMA_IT_FE);
+ 1778              		.loc 1 859 9 view .LVU659
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->Instance->FCR &= ~(DMA_IT_FE);
+ 1779              		.loc 1 859 13 is_stmt 0 view .LVU660
+ 1780 0114 2268     		ldr	r2, [r4]
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         hdma->Instance->FCR &= ~(DMA_IT_FE);
+ 1781              		.loc 1 859 29 view .LVU661
+ 1782 0116 1368     		ldr	r3, [r2]
+ 1783 0118 23F01603 		bic	r3, r3, #22
+ 1784 011c 1360     		str	r3, [r2]
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 1785              		.loc 1 860 9 is_stmt 1 view .LVU662
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 1786              		.loc 1 860 13 is_stmt 0 view .LVU663
+ 1787 011e 2268     		ldr	r2, [r4]
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         
+ 1788              		.loc 1 860 29 view .LVU664
+ 1789 0120 5369     		ldr	r3, [r2, #20]
+ 1790 0122 23F08003 		bic	r3, r3, #128
+ 1791 0126 5361     		str	r3, [r2, #20]
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1792              		.loc 1 862 9 is_stmt 1 view .LVU665
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1793              		.loc 1 862 17 is_stmt 0 view .LVU666
+ 1794 0128 236C     		ldr	r3, [r4, #64]
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1795              		.loc 1 862 11 view .LVU667
+ 1796 012a A3B1     		cbz	r3, .L119
+ 1797              	.L107:
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 1798              		.loc 1 864 11 is_stmt 1 view .LVU668
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 1799              		.loc 1 864 15 is_stmt 0 view .LVU669
+ 1800 012c 2268     		ldr	r2, [r4]
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 1801              		.loc 1 864 31 view .LVU670
+ 1802 012e 1368     		ldr	r3, [r2]
+ 1803 0130 23F00803 		bic	r3, r3, #8
+ 1804 0134 1360     		str	r3, [r2]
+ 1805              	.L108:
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1806              		.loc 1 868 9 is_stmt 1 view .LVU671
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1807              		.loc 1 868 35 is_stmt 0 view .LVU672
+ 1808 0136 E26D     		ldr	r2, [r4, #92]
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1809              		.loc 1 868 28 view .LVU673
+ 1810 0138 3F23     		movs	r3, #63
+ 1811 013a 9340     		lsls	r3, r3, r2
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1812              		.loc 1 868 20 view .LVU674
+ 1813 013c BB60     		str	r3, [r7, #8]
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1814              		.loc 1 871 9 is_stmt 1 view .LVU675
+ARM GAS  /tmp/ccRPwCnE.s 			page 66
+
+
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1815              		.loc 1 871 21 is_stmt 0 view .LVU676
+ 1816 013e 0123     		movs	r3, #1
+ 1817 0140 84F83530 		strb	r3, [r4, #53]
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1818              		.loc 1 874 9 is_stmt 1 view .LVU677
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1819              		.loc 1 874 9 view .LVU678
+ 1820 0144 0023     		movs	r3, #0
+ 1821 0146 84F83430 		strb	r3, [r4, #52]
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1822              		.loc 1 874 9 view .LVU679
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1823              		.loc 1 876 9 view .LVU680
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1824              		.loc 1 876 16 is_stmt 0 view .LVU681
+ 1825 014a 236D     		ldr	r3, [r4, #80]
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1826              		.loc 1 876 11 view .LVU682
+ 1827 014c 002B     		cmp	r3, #0
+ 1828 014e 3FD0     		beq	.L97
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 1829              		.loc 1 878 11 is_stmt 1 view .LVU683
+ 1830 0150 2046     		mov	r0, r4
+ 1831 0152 9847     		blx	r3
+ 1832              	.LVL136:
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       }
+ 1833              		.loc 1 880 9 view .LVU684
+ 1834 0154 3CE0     		b	.L97
+ 1835              	.L119:
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1836              		.loc 1 862 57 is_stmt 0 discriminator 1 view .LVU685
+ 1837 0156 A36C     		ldr	r3, [r4, #72]
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1838              		.loc 1 862 49 discriminator 1 view .LVU686
+ 1839 0158 002B     		cmp	r3, #0
+ 1840 015a E7D1     		bne	.L107
+ 1841 015c EBE7     		b	.L108
+ 1842              	.L112:
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1843              		.loc 1 897 11 is_stmt 1 view .LVU687
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1844              		.loc 1 897 18 is_stmt 0 view .LVU688
+ 1845 015e E36B     		ldr	r3, [r4, #60]
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           {
+ 1846              		.loc 1 897 13 view .LVU689
+ 1847 0160 A3B1     		cbz	r3, .L105
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****           }
+ 1848              		.loc 1 900 13 is_stmt 1 view .LVU690
+ 1849 0162 2046     		mov	r0, r4
+ 1850 0164 9847     		blx	r3
+ 1851              	.LVL137:
+ 1852 0166 11E0     		b	.L105
+ 1853              	.L111:
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1854              		.loc 1 907 9 view .LVU691
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ARM GAS  /tmp/ccRPwCnE.s 			page 67
+
+
+ 1855              		.loc 1 907 27 is_stmt 0 view .LVU692
+ 1856 0168 1A68     		ldr	r2, [r3]
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1857              		.loc 1 907 11 view .LVU693
+ 1858 016a 12F4807F 		tst	r2, #256
+ 1859 016e 09D1     		bne	.L113
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1860              		.loc 1 910 11 is_stmt 1 view .LVU694
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1861              		.loc 1 910 31 is_stmt 0 view .LVU695
+ 1862 0170 1A68     		ldr	r2, [r3]
+ 1863 0172 22F01002 		bic	r2, r2, #16
+ 1864 0176 1A60     		str	r2, [r3]
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1865              		.loc 1 913 11 is_stmt 1 view .LVU696
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1866              		.loc 1 913 23 is_stmt 0 view .LVU697
+ 1867 0178 0123     		movs	r3, #1
+ 1868 017a 84F83530 		strb	r3, [r4, #53]
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1869              		.loc 1 916 11 is_stmt 1 view .LVU698
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1870              		.loc 1 916 11 view .LVU699
+ 1871 017e 0023     		movs	r3, #0
+ 1872 0180 84F83430 		strb	r3, [r4, #52]
+ 1873              	.L113:
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1874              		.loc 1 916 11 discriminator 1 view .LVU700
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1875              		.loc 1 920 9 discriminator 1 view .LVU701
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1876              		.loc 1 920 16 is_stmt 0 discriminator 1 view .LVU702
+ 1877 0184 E36B     		ldr	r3, [r4, #60]
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1878              		.loc 1 920 11 discriminator 1 view .LVU703
+ 1879 0186 0BB1     		cbz	r3, .L105
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         }
+ 1880              		.loc 1 923 11 is_stmt 1 view .LVU704
+ 1881 0188 2046     		mov	r0, r4
+ 1882 018a 9847     		blx	r3
+ 1883              	.LVL138:
+ 1884              	.L105:
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1885              		.loc 1 930 3 view .LVU705
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1886              		.loc 1 930 10 is_stmt 0 view .LVU706
+ 1887 018c 636D     		ldr	r3, [r4, #84]
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1888              		.loc 1 930 5 view .LVU707
+ 1889 018e FBB1     		cbz	r3, .L97
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1890              		.loc 1 932 5 is_stmt 1 view .LVU708
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1891              		.loc 1 932 13 is_stmt 0 view .LVU709
+ 1892 0190 636D     		ldr	r3, [r4, #84]
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1893              		.loc 1 932 7 view .LVU710
+ARM GAS  /tmp/ccRPwCnE.s 			page 68
+
+
+ 1894 0192 13F0010F 		tst	r3, #1
+ 1895 0196 17D0     		beq	.L114
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1896              		.loc 1 934 7 is_stmt 1 view .LVU711
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1897              		.loc 1 934 19 is_stmt 0 view .LVU712
+ 1898 0198 0523     		movs	r3, #5
+ 1899 019a 84F83530 		strb	r3, [r4, #53]
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1900              		.loc 1 937 7 is_stmt 1 view .LVU713
+ 1901 019e 2268     		ldr	r2, [r4]
+ 1902 01a0 1368     		ldr	r3, [r2]
+ 1903 01a2 23F00103 		bic	r3, r3, #1
+ 1904 01a6 1360     		str	r3, [r2]
+ 1905              	.L116:
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       {
+ 1906              		.loc 1 939 7 view .LVU714
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1907              		.loc 1 941 9 view .LVU715
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1908              		.loc 1 941 13 is_stmt 0 view .LVU716
+ 1909 01a8 019B     		ldr	r3, [sp, #4]
+ 1910 01aa 0133     		adds	r3, r3, #1
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****         {
+ 1911              		.loc 1 941 12 view .LVU717
+ 1912 01ac 0193     		str	r3, [sp, #4]
+ 1913 01ae AB42     		cmp	r3, r5
+ 1914 01b0 04D8     		bhi	.L115
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1915              		.loc 1 946 12 is_stmt 1 view .LVU718
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1916              		.loc 1 946 18 is_stmt 0 view .LVU719
+ 1917 01b2 2368     		ldr	r3, [r4]
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1918              		.loc 1 946 28 view .LVU720
+ 1919 01b4 1B68     		ldr	r3, [r3]
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1920              		.loc 1 946 7 view .LVU721
+ 1921 01b6 13F0010F 		tst	r3, #1
+ 1922 01ba F5D1     		bne	.L116
+ 1923              	.L115:
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1924              		.loc 1 949 7 is_stmt 1 view .LVU722
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1925              		.loc 1 949 19 is_stmt 0 view .LVU723
+ 1926 01bc 0123     		movs	r3, #1
+ 1927 01be 84F83530 		strb	r3, [r4, #53]
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1928              		.loc 1 952 7 is_stmt 1 view .LVU724
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1929              		.loc 1 952 7 view .LVU725
+ 1930 01c2 0023     		movs	r3, #0
+ 1931 01c4 84F83430 		strb	r3, [r4, #52]
+ 1932              	.L114:
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1933              		.loc 1 952 7 discriminator 1 view .LVU726
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ARM GAS  /tmp/ccRPwCnE.s 			page 69
+
+
+ 1934              		.loc 1 956 5 discriminator 1 view .LVU727
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1935              		.loc 1 956 12 is_stmt 0 discriminator 1 view .LVU728
+ 1936 01c8 E36C     		ldr	r3, [r4, #76]
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 1937              		.loc 1 956 7 discriminator 1 view .LVU729
+ 1938 01ca 0BB1     		cbz	r3, .L97
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     }
+ 1939              		.loc 1 959 7 is_stmt 1 view .LVU730
+ 1940 01cc 2046     		mov	r0, r4
+ 1941 01ce 9847     		blx	r3
+ 1942              	.LVL139:
+ 1943              	.L97:
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1944              		.loc 1 962 1 is_stmt 0 view .LVU731
+ 1945 01d0 03B0     		add	sp, sp, #12
+ 1946              	.LCFI15:
+ 1947              		.cfi_def_cfa_offset 20
+ 1948              		@ sp needed
+ 1949 01d2 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 1950              	.LVL140:
+ 1951              	.L121:
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1952              		.loc 1 962 1 view .LVU732
+ 1953              		.align	2
+ 1954              	.L120:
+ 1955 01d4 00000000 		.word	SystemCoreClock
+ 1956 01d8 B5814E1B 		.word	458129845
+ 1957              		.cfi_endproc
+ 1958              	.LFE148:
+ 1960              		.section	.text.HAL_DMA_RegisterCallback,"ax",%progbits
+ 1961              		.align	1
+ 1962              		.global	HAL_DMA_RegisterCallback
+ 1963              		.syntax unified
+ 1964              		.thumb
+ 1965              		.thumb_func
+ 1966              		.fpu fpv5-d16
+ 1968              	HAL_DMA_RegisterCallback:
+ 1969              	.LVL141:
+ 1970              	.LFB149:
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1971              		.loc 1 975 1 is_stmt 1 view -0
+ 1972              		.cfi_startproc
+ 1973              		@ args = 0, pretend = 0, frame = 0
+ 1974              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1975              		@ link register save eliminated.
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1976              		.loc 1 975 1 is_stmt 0 view .LVU734
+ 1977 0000 0346     		mov	r3, r0
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1978              		.loc 1 977 3 is_stmt 1 view .LVU735
+ 1979              	.LVL142:
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1980              		.loc 1 980 3 view .LVU736
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1981              		.loc 1 980 3 view .LVU737
+ 1982 0002 90F83400 		ldrb	r0, [r0, #52]	@ zero_extendqisi2
+ARM GAS  /tmp/ccRPwCnE.s 			page 70
+
+
+ 1983              	.LVL143:
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1984              		.loc 1 980 3 is_stmt 0 view .LVU738
+ 1985 0006 0128     		cmp	r0, #1
+ 1986 0008 25D0     		beq	.L132
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1987              		.loc 1 980 3 is_stmt 1 discriminator 2 view .LVU739
+ 1988 000a 0120     		movs	r0, #1
+ 1989 000c 83F83400 		strb	r0, [r3, #52]
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 1990              		.loc 1 980 3 discriminator 2 view .LVU740
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1991              		.loc 1 982 3 discriminator 2 view .LVU741
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1992              		.loc 1 982 33 is_stmt 0 discriminator 2 view .LVU742
+ 1993 0010 93F83500 		ldrb	r0, [r3, #53]	@ zero_extendqisi2
+ 1994 0014 C0B2     		uxtb	r0, r0
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 1995              		.loc 1 982 5 discriminator 2 view .LVU743
+ 1996 0016 0128     		cmp	r0, #1
+ 1997 0018 04D0     		beq	.L134
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 1998              		.loc 1 1019 12 view .LVU744
+ 1999 001a 0120     		movs	r0, #1
+ 2000              	.L124:
+ 2001              	.LVL144:
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2002              		.loc 1 1023 3 is_stmt 1 view .LVU745
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2003              		.loc 1 1023 3 view .LVU746
+ 2004 001c 0022     		movs	r2, #0
+ 2005              	.LVL145:
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2006              		.loc 1 1023 3 is_stmt 0 view .LVU747
+ 2007 001e 83F83420 		strb	r2, [r3, #52]
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2008              		.loc 1 1023 3 is_stmt 1 view .LVU748
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 2009              		.loc 1 1025 3 view .LVU749
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 2010              		.loc 1 1025 10 is_stmt 0 view .LVU750
+ 2011 0022 7047     		bx	lr
+ 2012              	.LVL146:
+ 2013              	.L134:
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 2014              		.loc 1 984 5 is_stmt 1 view .LVU751
+ 2015 0024 0529     		cmp	r1, #5
+ 2016 0026 F9D8     		bhi	.L124
+ 2017 0028 DFE801F0 		tbb	[pc, r1]
+ 2018              	.L126:
+ 2019 002c 03       		.byte	(.L131-.L126)/2
+ 2020 002d 06       		.byte	(.L130-.L126)/2
+ 2021 002e 09       		.byte	(.L129-.L126)/2
+ 2022 002f 0C       		.byte	(.L128-.L126)/2
+ 2023 0030 0F       		.byte	(.L127-.L126)/2
+ 2024 0031 12       		.byte	(.L125-.L126)/2
+ 2025              		.p2align 1
+ARM GAS  /tmp/ccRPwCnE.s 			page 71
+
+
+ 2026              	.L131:
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2027              		.loc 1 987 7 view .LVU752
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2028              		.loc 1 987 30 is_stmt 0 view .LVU753
+ 2029 0032 DA63     		str	r2, [r3, #60]
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2030              		.loc 1 988 7 is_stmt 1 view .LVU754
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2031              		.loc 1 977 21 is_stmt 0 view .LVU755
+ 2032 0034 0846     		mov	r0, r1
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2033              		.loc 1 988 7 view .LVU756
+ 2034 0036 F1E7     		b	.L124
+ 2035              	.L130:
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2036              		.loc 1 991 7 is_stmt 1 view .LVU757
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2037              		.loc 1 991 34 is_stmt 0 view .LVU758
+ 2038 0038 1A64     		str	r2, [r3, #64]
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2039              		.loc 1 992 7 is_stmt 1 view .LVU759
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2040              		.loc 1 977 21 is_stmt 0 view .LVU760
+ 2041 003a 0020     		movs	r0, #0
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2042              		.loc 1 992 7 view .LVU761
+ 2043 003c EEE7     		b	.L124
+ 2044              	.L129:
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2045              		.loc 1 995 7 is_stmt 1 view .LVU762
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2046              		.loc 1 995 32 is_stmt 0 view .LVU763
+ 2047 003e 5A64     		str	r2, [r3, #68]
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2048              		.loc 1 996 7 is_stmt 1 view .LVU764
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2049              		.loc 1 977 21 is_stmt 0 view .LVU765
+ 2050 0040 0020     		movs	r0, #0
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2051              		.loc 1 996 7 view .LVU766
+ 2052 0042 EBE7     		b	.L124
+ 2053              	.L128:
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2054              		.loc 1 999 7 is_stmt 1 view .LVU767
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2055              		.loc 1 999 36 is_stmt 0 view .LVU768
+ 2056 0044 9A64     		str	r2, [r3, #72]
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2057              		.loc 1 1000 7 is_stmt 1 view .LVU769
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2058              		.loc 1 977 21 is_stmt 0 view .LVU770
+ 2059 0046 0020     		movs	r0, #0
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2060              		.loc 1 1000 7 view .LVU771
+ 2061 0048 E8E7     		b	.L124
+ 2062              	.L127:
+ARM GAS  /tmp/ccRPwCnE.s 			page 72
+
+
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2063              		.loc 1 1003 7 is_stmt 1 view .LVU772
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2064              		.loc 1 1003 31 is_stmt 0 view .LVU773
+ 2065 004a DA64     		str	r2, [r3, #76]
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2066              		.loc 1 1004 7 is_stmt 1 view .LVU774
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2067              		.loc 1 977 21 is_stmt 0 view .LVU775
+ 2068 004c 0020     		movs	r0, #0
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2069              		.loc 1 1004 7 view .LVU776
+ 2070 004e E5E7     		b	.L124
+ 2071              	.L125:
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2072              		.loc 1 1007 7 is_stmt 1 view .LVU777
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2073              		.loc 1 1007 31 is_stmt 0 view .LVU778
+ 2074 0050 1A65     		str	r2, [r3, #80]
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2075              		.loc 1 1008 7 is_stmt 1 view .LVU779
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2076              		.loc 1 977 21 is_stmt 0 view .LVU780
+ 2077 0052 0020     		movs	r0, #0
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2078              		.loc 1 1008 7 view .LVU781
+ 2079 0054 E2E7     		b	.L124
+ 2080              	.L132:
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2081              		.loc 1 980 3 view .LVU782
+ 2082 0056 0220     		movs	r0, #2
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2083              		.loc 1 1026 1 view .LVU783
+ 2084 0058 7047     		bx	lr
+ 2085              		.cfi_endproc
+ 2086              	.LFE149:
+ 2088              		.section	.text.HAL_DMA_UnRegisterCallback,"ax",%progbits
+ 2089              		.align	1
+ 2090              		.global	HAL_DMA_UnRegisterCallback
+ 2091              		.syntax unified
+ 2092              		.thumb
+ 2093              		.thumb_func
+ 2094              		.fpu fpv5-d16
+ 2096              	HAL_DMA_UnRegisterCallback:
+ 2097              	.LVL147:
+ 2098              	.LFB150:
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2099              		.loc 1 1037 1 is_stmt 1 view -0
+ 2100              		.cfi_startproc
+ 2101              		@ args = 0, pretend = 0, frame = 0
+ 2102              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2103              		@ link register save eliminated.
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2104              		.loc 1 1037 1 is_stmt 0 view .LVU785
+ 2105 0000 0346     		mov	r3, r0
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2106              		.loc 1 1038 3 is_stmt 1 view .LVU786
+ARM GAS  /tmp/ccRPwCnE.s 			page 73
+
+
+ 2107              	.LVL148:
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2108              		.loc 1 1041 3 view .LVU787
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2109              		.loc 1 1041 3 view .LVU788
+ 2110 0002 90F83420 		ldrb	r2, [r0, #52]	@ zero_extendqisi2
+ 2111 0006 012A     		cmp	r2, #1
+ 2112 0008 2FD0     		beq	.L146
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2113              		.loc 1 1041 3 discriminator 2 view .LVU789
+ 2114 000a 0122     		movs	r2, #1
+ 2115 000c 80F83420 		strb	r2, [r0, #52]
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2116              		.loc 1 1041 3 discriminator 2 view .LVU790
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 2117              		.loc 1 1043 3 discriminator 2 view .LVU791
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 2118              		.loc 1 1043 33 is_stmt 0 discriminator 2 view .LVU792
+ 2119 0010 90F83500 		ldrb	r0, [r0, #53]	@ zero_extendqisi2
+ 2120              	.LVL149:
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 2121              		.loc 1 1043 33 discriminator 2 view .LVU793
+ 2122 0014 C0B2     		uxtb	r0, r0
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   {
+ 2123              		.loc 1 1043 5 discriminator 2 view .LVU794
+ 2124 0016 9042     		cmp	r0, r2
+ 2125 0018 04D0     		beq	.L148
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   }
+ 2126              		.loc 1 1087 12 view .LVU795
+ 2127 001a 0120     		movs	r0, #1
+ 2128              	.L137:
+ 2129              	.LVL150:
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2130              		.loc 1 1091 3 is_stmt 1 view .LVU796
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2131              		.loc 1 1091 3 view .LVU797
+ 2132 001c 0022     		movs	r2, #0
+ 2133 001e 83F83420 		strb	r2, [r3, #52]
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2134              		.loc 1 1091 3 view .LVU798
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 2135              		.loc 1 1093 3 view .LVU799
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 2136              		.loc 1 1093 10 is_stmt 0 view .LVU800
+ 2137 0022 7047     		bx	lr
+ 2138              	.LVL151:
+ 2139              	.L148:
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****     {
+ 2140              		.loc 1 1045 5 is_stmt 1 view .LVU801
+ 2141 0024 0629     		cmp	r1, #6
+ 2142 0026 F9D8     		bhi	.L137
+ 2143 0028 DFE801F0 		tbb	[pc, r1]
+ 2144              	.L139:
+ 2145 002c 04       		.byte	(.L145-.L139)/2
+ 2146 002d 08       		.byte	(.L144-.L139)/2
+ 2147 002e 0B       		.byte	(.L143-.L139)/2
+ 2148 002f 0E       		.byte	(.L142-.L139)/2
+ARM GAS  /tmp/ccRPwCnE.s 			page 74
+
+
+ 2149 0030 11       		.byte	(.L141-.L139)/2
+ 2150 0031 14       		.byte	(.L140-.L139)/2
+ 2151 0032 17       		.byte	(.L138-.L139)/2
+ 2152 0033 00       		.p2align 1
+ 2153              	.L145:
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2154              		.loc 1 1048 7 view .LVU802
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2155              		.loc 1 1048 30 is_stmt 0 view .LVU803
+ 2156 0034 0022     		movs	r2, #0
+ 2157 0036 DA63     		str	r2, [r3, #60]
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 2158              		.loc 1 1049 7 is_stmt 1 view .LVU804
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2159              		.loc 1 1038 21 is_stmt 0 view .LVU805
+ 2160 0038 0846     		mov	r0, r1
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 2161              		.loc 1 1049 7 view .LVU806
+ 2162 003a EFE7     		b	.L137
+ 2163              	.L144:
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2164              		.loc 1 1052 7 is_stmt 1 view .LVU807
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2165              		.loc 1 1052 34 is_stmt 0 view .LVU808
+ 2166 003c 0020     		movs	r0, #0
+ 2167 003e 1864     		str	r0, [r3, #64]
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 2168              		.loc 1 1053 7 is_stmt 1 view .LVU809
+ 2169 0040 ECE7     		b	.L137
+ 2170              	.L143:
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2171              		.loc 1 1056 7 view .LVU810
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2172              		.loc 1 1056 32 is_stmt 0 view .LVU811
+ 2173 0042 0020     		movs	r0, #0
+ 2174 0044 5864     		str	r0, [r3, #68]
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 2175              		.loc 1 1057 7 is_stmt 1 view .LVU812
+ 2176 0046 E9E7     		b	.L137
+ 2177              	.L142:
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2178              		.loc 1 1060 7 view .LVU813
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2179              		.loc 1 1060 36 is_stmt 0 view .LVU814
+ 2180 0048 0020     		movs	r0, #0
+ 2181 004a 9864     		str	r0, [r3, #72]
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 2182              		.loc 1 1061 7 is_stmt 1 view .LVU815
+ 2183 004c E6E7     		b	.L137
+ 2184              	.L141:
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2185              		.loc 1 1064 7 view .LVU816
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break;
+ 2186              		.loc 1 1064 31 is_stmt 0 view .LVU817
+ 2187 004e 0020     		movs	r0, #0
+ 2188 0050 D864     		str	r0, [r3, #76]
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ARM GAS  /tmp/ccRPwCnE.s 			page 75
+
+
+ 2189              		.loc 1 1065 7 is_stmt 1 view .LVU818
+ 2190 0052 E3E7     		b	.L137
+ 2191              	.L140:
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break; 
+ 2192              		.loc 1 1068 7 view .LVU819
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break; 
+ 2193              		.loc 1 1068 31 is_stmt 0 view .LVU820
+ 2194 0054 0020     		movs	r0, #0
+ 2195 0056 1865     		str	r0, [r3, #80]
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 2196              		.loc 1 1069 7 is_stmt 1 view .LVU821
+ 2197 0058 E0E7     		b	.L137
+ 2198              	.L138:
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferHalfCpltCallback = NULL;
+ 2199              		.loc 1 1072 7 view .LVU822
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferHalfCpltCallback = NULL;
+ 2200              		.loc 1 1072 30 is_stmt 0 view .LVU823
+ 2201 005a 0020     		movs	r0, #0
+ 2202 005c D863     		str	r0, [r3, #60]
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferM1CpltCallback = NULL;
+ 2203              		.loc 1 1073 7 is_stmt 1 view .LVU824
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferM1CpltCallback = NULL;
+ 2204              		.loc 1 1073 34 is_stmt 0 view .LVU825
+ 2205 005e 1864     		str	r0, [r3, #64]
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferM1HalfCpltCallback = NULL;
+ 2206              		.loc 1 1074 7 is_stmt 1 view .LVU826
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferM1HalfCpltCallback = NULL;
+ 2207              		.loc 1 1074 32 is_stmt 0 view .LVU827
+ 2208 0060 5864     		str	r0, [r3, #68]
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferErrorCallback = NULL;
+ 2209              		.loc 1 1075 7 is_stmt 1 view .LVU828
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferErrorCallback = NULL;
+ 2210              		.loc 1 1075 36 is_stmt 0 view .LVU829
+ 2211 0062 9864     		str	r0, [r3, #72]
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferAbortCallback = NULL;
+ 2212              		.loc 1 1076 7 is_stmt 1 view .LVU830
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       hdma->XferAbortCallback = NULL;
+ 2213              		.loc 1 1076 31 is_stmt 0 view .LVU831
+ 2214 0064 D864     		str	r0, [r3, #76]
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break; 
+ 2215              		.loc 1 1077 7 is_stmt 1 view .LVU832
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       break; 
+ 2216              		.loc 1 1077 31 is_stmt 0 view .LVU833
+ 2217 0066 1865     		str	r0, [r3, #80]
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****       
+ 2218              		.loc 1 1078 7 is_stmt 1 view .LVU834
+ 2219 0068 D8E7     		b	.L137
+ 2220              	.LVL152:
+ 2221              	.L146:
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   
+ 2222              		.loc 1 1041 3 is_stmt 0 view .LVU835
+ 2223 006a 0220     		movs	r0, #2
+ 2224              	.LVL153:
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2225              		.loc 1 1094 1 view .LVU836
+ 2226 006c 7047     		bx	lr
+ 2227              		.cfi_endproc
+ARM GAS  /tmp/ccRPwCnE.s 			page 76
+
+
+ 2228              	.LFE150:
+ 2230              		.section	.text.HAL_DMA_GetState,"ax",%progbits
+ 2231              		.align	1
+ 2232              		.global	HAL_DMA_GetState
+ 2233              		.syntax unified
+ 2234              		.thumb
+ 2235              		.thumb_func
+ 2236              		.fpu fpv5-d16
+ 2238              	HAL_DMA_GetState:
+ 2239              	.LVL154:
+ 2240              	.LFB151:
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return hdma->State;
+ 2241              		.loc 1 1122 1 is_stmt 1 view -0
+ 2242              		.cfi_startproc
+ 2243              		@ args = 0, pretend = 0, frame = 0
+ 2244              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2245              		@ link register save eliminated.
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 2246              		.loc 1 1123 3 view .LVU838
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 2247              		.loc 1 1123 14 is_stmt 0 view .LVU839
+ 2248 0000 90F83500 		ldrb	r0, [r0, #53]	@ zero_extendqisi2
+ 2249              	.LVL155:
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2250              		.loc 1 1124 1 view .LVU840
+ 2251 0004 7047     		bx	lr
+ 2252              		.cfi_endproc
+ 2253              	.LFE151:
+ 2255              		.section	.text.HAL_DMA_GetError,"ax",%progbits
+ 2256              		.align	1
+ 2257              		.global	HAL_DMA_GetError
+ 2258              		.syntax unified
+ 2259              		.thumb
+ 2260              		.thumb_func
+ 2261              		.fpu fpv5-d16
+ 2263              	HAL_DMA_GetError:
+ 2264              	.LVL156:
+ 2265              	.LFB152:
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c ****   return hdma->ErrorCode;
+ 2266              		.loc 1 1133 1 is_stmt 1 view -0
+ 2267              		.cfi_startproc
+ 2268              		@ args = 0, pretend = 0, frame = 0
+ 2269              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2270              		@ link register save eliminated.
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 2271              		.loc 1 1134 3 view .LVU842
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** }
+ 2272              		.loc 1 1134 14 is_stmt 0 view .LVU843
+ 2273 0000 406D     		ldr	r0, [r0, #84]
+ 2274              	.LVL157:
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** 
+ 2275              		.loc 1 1135 1 view .LVU844
+ 2276 0002 7047     		bx	lr
+ 2277              		.cfi_endproc
+ 2278              	.LFE152:
+ 2280              		.section	.rodata.flagBitshiftOffset.0,"a"
+ 2281              		.align	2
+ARM GAS  /tmp/ccRPwCnE.s 			page 77
+
+
+ 2282              		.set	.LANCHOR0,. + 0
+ 2285              	flagBitshiftOffset.0:
+ 2286 0000 00061016 		.ascii	"\000\006\020\026\000\006\020\026"
+ 2286      00061016 
+ 2287              		.text
+ 2288              	.Letext0:
+ 2289              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 2290              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 2291              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 2292              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 2293              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 2294              		.file 7 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h"
+ 2295              		.file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ARM GAS  /tmp/ccRPwCnE.s 			page 78
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_dma.c
+     /tmp/ccRPwCnE.s:17     .text.DMA_SetConfig:0000000000000000 $t
+     /tmp/ccRPwCnE.s:24     .text.DMA_SetConfig:0000000000000000 DMA_SetConfig
+     /tmp/ccRPwCnE.s:98     .text.DMA_CalcBaseAndBitshift:0000000000000000 $t
+     /tmp/ccRPwCnE.s:104    .text.DMA_CalcBaseAndBitshift:0000000000000000 DMA_CalcBaseAndBitshift
+     /tmp/ccRPwCnE.s:175    .text.DMA_CalcBaseAndBitshift:0000000000000034 $d
+     /tmp/ccRPwCnE.s:182    .text.DMA_CheckFifoParam:0000000000000000 $t
+     /tmp/ccRPwCnE.s:188    .text.DMA_CheckFifoParam:0000000000000000 DMA_CheckFifoParam
+     /tmp/ccRPwCnE.s:274    .text.DMA_CheckFifoParam:000000000000004e $d
+     /tmp/ccRPwCnE.s:278    .text.DMA_CheckFifoParam:0000000000000052 $t
+     /tmp/ccRPwCnE.s:373    .text.HAL_DMA_Init:0000000000000000 $t
+     /tmp/ccRPwCnE.s:380    .text.HAL_DMA_Init:0000000000000000 HAL_DMA_Init
+     /tmp/ccRPwCnE.s:630    .text.HAL_DMA_Init:00000000000000cc $d
+     /tmp/ccRPwCnE.s:635    .text.HAL_DMA_DeInit:0000000000000000 $t
+     /tmp/ccRPwCnE.s:642    .text.HAL_DMA_DeInit:0000000000000000 HAL_DMA_DeInit
+     /tmp/ccRPwCnE.s:775    .text.HAL_DMA_Start:0000000000000000 $t
+     /tmp/ccRPwCnE.s:782    .text.HAL_DMA_Start:0000000000000000 HAL_DMA_Start
+     /tmp/ccRPwCnE.s:865    .text.HAL_DMA_Start_IT:0000000000000000 $t
+     /tmp/ccRPwCnE.s:872    .text.HAL_DMA_Start_IT:0000000000000000 HAL_DMA_Start_IT
+     /tmp/ccRPwCnE.s:994    .text.HAL_DMA_Abort:0000000000000000 $t
+     /tmp/ccRPwCnE.s:1001   .text.HAL_DMA_Abort:0000000000000000 HAL_DMA_Abort
+     /tmp/ccRPwCnE.s:1155   .text.HAL_DMA_Abort_IT:0000000000000000 $t
+     /tmp/ccRPwCnE.s:1162   .text.HAL_DMA_Abort_IT:0000000000000000 HAL_DMA_Abort_IT
+     /tmp/ccRPwCnE.s:1208   .text.HAL_DMA_PollForTransfer:0000000000000000 $t
+     /tmp/ccRPwCnE.s:1215   .text.HAL_DMA_PollForTransfer:0000000000000000 HAL_DMA_PollForTransfer
+     /tmp/ccRPwCnE.s:1507   .text.HAL_DMA_IRQHandler:0000000000000000 $t
+     /tmp/ccRPwCnE.s:1514   .text.HAL_DMA_IRQHandler:0000000000000000 HAL_DMA_IRQHandler
+     /tmp/ccRPwCnE.s:1955   .text.HAL_DMA_IRQHandler:00000000000001d4 $d
+     /tmp/ccRPwCnE.s:1961   .text.HAL_DMA_RegisterCallback:0000000000000000 $t
+     /tmp/ccRPwCnE.s:1968   .text.HAL_DMA_RegisterCallback:0000000000000000 HAL_DMA_RegisterCallback
+     /tmp/ccRPwCnE.s:2019   .text.HAL_DMA_RegisterCallback:000000000000002c $d
+     /tmp/ccRPwCnE.s:2025   .text.HAL_DMA_RegisterCallback:0000000000000032 $t
+     /tmp/ccRPwCnE.s:2089   .text.HAL_DMA_UnRegisterCallback:0000000000000000 $t
+     /tmp/ccRPwCnE.s:2096   .text.HAL_DMA_UnRegisterCallback:0000000000000000 HAL_DMA_UnRegisterCallback
+     /tmp/ccRPwCnE.s:2145   .text.HAL_DMA_UnRegisterCallback:000000000000002c $d
+     /tmp/ccRPwCnE.s:2231   .text.HAL_DMA_GetState:0000000000000000 $t
+     /tmp/ccRPwCnE.s:2238   .text.HAL_DMA_GetState:0000000000000000 HAL_DMA_GetState
+     /tmp/ccRPwCnE.s:2256   .text.HAL_DMA_GetError:0000000000000000 $t
+     /tmp/ccRPwCnE.s:2263   .text.HAL_DMA_GetError:0000000000000000 HAL_DMA_GetError
+     /tmp/ccRPwCnE.s:2281   .rodata.flagBitshiftOffset.0:0000000000000000 $d
+     /tmp/ccRPwCnE.s:2285   .rodata.flagBitshiftOffset.0:0000000000000000 flagBitshiftOffset.0
+     /tmp/ccRPwCnE.s:2152   .text.HAL_DMA_UnRegisterCallback:0000000000000033 $d
+     /tmp/ccRPwCnE.s:2152   .text.HAL_DMA_UnRegisterCallback:0000000000000034 $t
+
+UNDEFINED SYMBOLS
+HAL_GetTick
+SystemCoreClock
diff --git a/build/stm32f7xx_hal_dma.o b/build/stm32f7xx_hal_dma.o
new file mode 100644
index 0000000..5982929
Binary files /dev/null and b/build/stm32f7xx_hal_dma.o differ
diff --git a/build/stm32f7xx_hal_dma_ex.d b/build/stm32f7xx_hal_dma_ex.d
new file mode 100644
index 0000000..f621e4a
--- /dev/null
+++ b/build/stm32f7xx_hal_dma_ex.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_dma_ex.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_dma_ex.lst b/build/stm32f7xx_hal_dma_ex.lst
new file mode 100644
index 0000000..6e10cea
--- /dev/null
+++ b/build/stm32f7xx_hal_dma_ex.lst
@@ -0,0 +1,3299 @@
+ARM GAS  /tmp/ccgvGc3k.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_dma_ex.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.DMA_MultiBufferSetConfig,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	DMA_MultiBufferSetConfig:
+  25              	.LVL0:
+  26              	.LFB144:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @file    stm32f7xx_hal_dma_ex.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @brief   DMA Extension HAL module driver
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *         This file provides firmware functions to manage the following 
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *         functionalities of the DMA Extension peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *           + Extended features functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   @verbatim
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   ==============================================================================
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****                         ##### How to use this driver #####
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   ==============================================================================
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   [..]
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   The DMA Extension HAL driver can be used as follows:
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****    (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****        for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****      -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****      -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****      -@-  In Multi (Double) buffer mode, it is possible to update the base address for 
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****           the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   @endverbatim
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   ******************************************************************************
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @attention
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * Copyright (c) 2017 STMicroelectronics.
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * All rights reserved.
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+ARM GAS  /tmp/ccgvGc3k.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * the root directory of this software component.
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   ******************************************************************************
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Includes ------------------------------------------------------------------*/
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** #include "stm32f7xx_hal.h"
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @{
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** @defgroup DMAEx DMAEx
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @brief DMA Extended HAL module driver
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @{
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** #ifdef HAL_DMA_MODULE_ENABLED
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Private types -------------------------------------------------------------*/
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Private variables ---------------------------------------------------------*/
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Private Constants ---------------------------------------------------------*/
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Private macros ------------------------------------------------------------*/
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Private functions ---------------------------------------------------------*/
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** @addtogroup DMAEx_Private_Functions
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @{
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddr
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /**
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @}
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Exported functions ---------------------------------------------------------*/
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** @addtogroup DMAEx_Exported_Functions
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @{
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** @addtogroup DMAEx_Exported_Functions_Group1
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** @verbatim
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****  ===============================================================================
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****                 #####  Extended features functions  #####
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****  ===============================================================================  
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     [..]  This section provides functions allowing to:
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       (+) Configure the source, destination address and data length and 
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****           Start MultiBuffer DMA transfer
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       (+) Configure the source, destination address and data length and 
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****           Start MultiBuffer DMA transfer with interrupt
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       (+) Change on the fly the memory0 or memory1 address.
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** @endverbatim
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @{
+ARM GAS  /tmp/ccgvGc3k.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /**
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @brief  Starts the multi_buffer DMA Transfer.
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *                     the configuration information for the specified DMA Stream.  
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  SrcAddress The source memory Buffer address
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  DstAddress The destination memory Buffer address
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  DataLength The length of data to be transferred from source to destination
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @retval HAL status
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** {
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   /* Check the parameters */
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   /* Memory-to-memory transfer not supported in double buffering mode */
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     status = HAL_ERROR;
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   else
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Process Locked */
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_LOCK(hdma);
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     if(HAL_DMA_STATE_READY == hdma->State)
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     {
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       /* Change DMA peripheral state */
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       hdma->State = HAL_DMA_STATE_BUSY; 
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       /* Enable the double buffer mode */
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       /* Configure DMA Stream destination address */
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       hdma->Instance->M1AR = SecondMemAddress;
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       /* Configure the source, destination address and the data length */
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       /* Enable the peripheral */
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       __HAL_DMA_ENABLE(hdma);
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     }
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     else
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     {
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       /* Return error status */
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       status = HAL_BUSY;
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     }
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   return status;
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** }
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+ARM GAS  /tmp/ccgvGc3k.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /**
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *                     the configuration information for the specified DMA Stream.  
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  SrcAddress The source memory Buffer address
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  DstAddress The destination memory Buffer address
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  DataLength The length of data to be transferred from source to destination
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @retval HAL status
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint3
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** {
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   /* Check the parameters */
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   /* Memory-to-memory transfer not supported in double buffering mode */
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     return HAL_ERROR;
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   /* Process locked */
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   __HAL_LOCK(hdma);
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   if(HAL_DMA_STATE_READY == hdma->State)
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Change DMA peripheral state */
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->State = HAL_DMA_STATE_BUSY;
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Initialize the error code */
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Enable the Double buffer mode */
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Configure DMA Stream destination address */
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->M1AR = SecondMemAddress;
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Configure the source, destination address and the data length */
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Clear all flags */
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Enable Common interrupts*/
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->FCR |= DMA_IT_FE;
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     {
+ARM GAS  /tmp/ccgvGc3k.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       hdma->Instance->CR  |= DMA_IT_HT;
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     }
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Enable the peripheral */
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_ENABLE(hdma); 
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   else
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {     
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Process unlocked */
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_UNLOCK(hdma);	  
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Return error status */
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     status = HAL_BUSY;
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }  
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   return status; 
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** }
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /**
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @brief  Change the memory0 or memory1 address on the fly.
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *                     the configuration information for the specified DMA Stream.  
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  Address    The new address
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  memory     the memory to be changed, This parameter can be one of 
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *                     the following values:
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *                      MEMORY0 /
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *                      MEMORY1
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @note   The MEMORY0 address can be changed only when the current transfer use
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *         MEMORY1 and the MEMORY1 address can be changed only when the current 
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *         transfer use MEMORY0.
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @retval HAL status
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryT
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** {
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   if(memory == MEMORY0)
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* change the memory0 address */
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->M0AR = Address;
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   else
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* change the memory1 address */
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->M1AR = Address;
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   return HAL_OK;
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** }
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /**
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @}
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /**
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @}
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** @addtogroup DMAEx_Private_Functions
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @{
+ARM GAS  /tmp/ccgvGc3k.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /**
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @brief  Set the DMA Transfer parameter.
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   *                     the configuration information for the specified DMA Stream.  
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  SrcAddress The source memory Buffer address
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  DstAddress The destination memory Buffer address
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @param  DataLength The length of data to be transferred from source to destination
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   * @retval HAL status
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   */
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddr
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** {
+  28              		.loc 1 272 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  33              		.loc 1 272 1 is_stmt 0 view .LVU1
+  34 0000 10B4     		push	{r4}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 4
+  37              		.cfi_offset 4, -4
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   /* Configure DMA Stream data length */
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   hdma->Instance->NDTR = DataLength;
+  38              		.loc 1 274 3 is_stmt 1 view .LVU2
+  39              		.loc 1 274 24 is_stmt 0 view .LVU3
+  40 0002 0468     		ldr	r4, [r0]
+  41 0004 6360     		str	r3, [r4, #4]
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   /* Peripheral to Memory */
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  42              		.loc 1 277 3 is_stmt 1 view .LVU4
+  43              		.loc 1 277 17 is_stmt 0 view .LVU5
+  44 0006 8368     		ldr	r3, [r0, #8]
+  45              	.LVL1:
+  46              		.loc 1 277 5 view .LVU6
+  47 0008 402B     		cmp	r3, #64
+  48 000a 06D0     		beq	.L5
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Configure DMA Stream destination address */
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->PAR = DstAddress;
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Configure DMA Stream source address */
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->M0AR = SrcAddress;
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   /* Memory to Peripheral */
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   else
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Configure DMA Stream source address */
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->PAR = SrcAddress;
+  49              		.loc 1 289 5 is_stmt 1 view .LVU7
+  50              		.loc 1 289 9 is_stmt 0 view .LVU8
+  51 000c 0368     		ldr	r3, [r0]
+  52              		.loc 1 289 25 view .LVU9
+  53 000e 9960     		str	r1, [r3, #8]
+  54              	.LVL2:
+ARM GAS  /tmp/ccgvGc3k.s 			page 7
+
+
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     /* Configure DMA Stream destination address */
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->M0AR = DstAddress;
+  55              		.loc 1 292 5 is_stmt 1 view .LVU10
+  56              		.loc 1 292 9 is_stmt 0 view .LVU11
+  57 0010 0368     		ldr	r3, [r0]
+  58              		.loc 1 292 26 view .LVU12
+  59 0012 DA60     		str	r2, [r3, #12]
+  60              	.L1:
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** }
+  61              		.loc 1 294 1 view .LVU13
+  62 0014 5DF8044B 		ldr	r4, [sp], #4
+  63              	.LCFI1:
+  64              		.cfi_remember_state
+  65              		.cfi_restore 4
+  66              		.cfi_def_cfa_offset 0
+  67 0018 7047     		bx	lr
+  68              	.LVL3:
+  69              	.L5:
+  70              	.LCFI2:
+  71              		.cfi_restore_state
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+  72              		.loc 1 280 5 is_stmt 1 view .LVU14
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+  73              		.loc 1 280 9 is_stmt 0 view .LVU15
+  74 001a 0368     		ldr	r3, [r0]
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+  75              		.loc 1 280 25 view .LVU16
+  76 001c 9A60     		str	r2, [r3, #8]
+  77              	.LVL4:
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+  78              		.loc 1 283 5 is_stmt 1 view .LVU17
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+  79              		.loc 1 283 9 is_stmt 0 view .LVU18
+  80 001e 0368     		ldr	r3, [r0]
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+  81              		.loc 1 283 26 view .LVU19
+  82 0020 D960     		str	r1, [r3, #12]
+  83 0022 F7E7     		b	.L1
+  84              		.cfi_endproc
+  85              	.LFE144:
+  87              		.section	.text.HAL_DMAEx_MultiBufferStart,"ax",%progbits
+  88              		.align	1
+  89              		.global	HAL_DMAEx_MultiBufferStart
+  90              		.syntax unified
+  91              		.thumb
+  92              		.thumb_func
+  93              		.fpu fpv5-d16
+  95              	HAL_DMAEx_MultiBufferStart:
+  96              	.LVL5:
+  97              	.LFB141:
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+  98              		.loc 1 103 1 is_stmt 1 view -0
+  99              		.cfi_startproc
+ 100              		@ args = 4, pretend = 0, frame = 0
+ 101              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccgvGc3k.s 			page 8
+
+
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 102              		.loc 1 103 1 is_stmt 0 view .LVU21
+ 103 0000 38B5     		push	{r3, r4, r5, lr}
+ 104              	.LCFI3:
+ 105              		.cfi_def_cfa_offset 16
+ 106              		.cfi_offset 3, -16
+ 107              		.cfi_offset 4, -12
+ 108              		.cfi_offset 5, -8
+ 109              		.cfi_offset 14, -4
+ 110 0002 0446     		mov	r4, r0
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 111              		.loc 1 104 3 is_stmt 1 view .LVU22
+ 112              	.LVL6:
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 113              		.loc 1 107 3 view .LVU23
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 114              		.loc 1 110 3 view .LVU24
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 115              		.loc 1 110 17 is_stmt 0 view .LVU25
+ 116 0004 8068     		ldr	r0, [r0, #8]
+ 117              	.LVL7:
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 118              		.loc 1 110 6 view .LVU26
+ 119 0006 8028     		cmp	r0, #128
+ 120 0008 0DD0     		beq	.L12
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 121              		.loc 1 118 5 is_stmt 1 view .LVU27
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 122              		.loc 1 118 5 view .LVU28
+ 123 000a 94F83400 		ldrb	r0, [r4, #52]	@ zero_extendqisi2
+ 124 000e 0128     		cmp	r0, #1
+ 125 0010 23D0     		beq	.L9
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 126              		.loc 1 118 5 discriminator 2 view .LVU29
+ 127 0012 0120     		movs	r0, #1
+ 128 0014 84F83400 		strb	r0, [r4, #52]
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 129              		.loc 1 118 5 discriminator 2 view .LVU30
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     {
+ 130              		.loc 1 120 5 discriminator 2 view .LVU31
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     {
+ 131              		.loc 1 120 35 is_stmt 0 discriminator 2 view .LVU32
+ 132 0018 94F83500 		ldrb	r0, [r4, #53]	@ zero_extendqisi2
+ 133 001c C0B2     		uxtb	r0, r0
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     {
+ 134              		.loc 1 120 7 discriminator 2 view .LVU33
+ 135 001e 0128     		cmp	r0, #1
+ 136 0020 06D0     		beq	.L13
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     }
+ 137              		.loc 1 140 14 view .LVU34
+ 138 0022 0220     		movs	r0, #2
+ 139              	.LVL8:
+ 140              	.L8:
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+ 141              		.loc 1 144 1 view .LVU35
+ 142 0024 38BD     		pop	{r3, r4, r5, pc}
+ 143              	.LVL9:
+ARM GAS  /tmp/ccgvGc3k.s 			page 9
+
+
+ 144              	.L12:
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     status = HAL_ERROR;
+ 145              		.loc 1 112 5 is_stmt 1 view .LVU36
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     status = HAL_ERROR;
+ 146              		.loc 1 112 21 is_stmt 0 view .LVU37
+ 147 0026 4FF48073 		mov	r3, #256
+ 148              	.LVL10:
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     status = HAL_ERROR;
+ 149              		.loc 1 112 21 view .LVU38
+ 150 002a 6365     		str	r3, [r4, #84]
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 151              		.loc 1 113 5 is_stmt 1 view .LVU39
+ 152              	.LVL11:
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 153              		.loc 1 113 12 is_stmt 0 view .LVU40
+ 154 002c 0120     		movs	r0, #1
+ 155 002e F9E7     		b	.L8
+ 156              	.LVL12:
+ 157              	.L13:
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 158              		.loc 1 123 7 is_stmt 1 view .LVU41
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 159              		.loc 1 123 19 is_stmt 0 view .LVU42
+ 160 0030 0220     		movs	r0, #2
+ 161 0032 84F83500 		strb	r0, [r4, #53]
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 162              		.loc 1 126 7 is_stmt 1 view .LVU43
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 163              		.loc 1 126 11 is_stmt 0 view .LVU44
+ 164 0036 2568     		ldr	r5, [r4]
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 165              		.loc 1 126 26 view .LVU45
+ 166 0038 2868     		ldr	r0, [r5]
+ 167 003a 40F48020 		orr	r0, r0, #262144
+ 168 003e 2860     		str	r0, [r5]
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 169              		.loc 1 129 7 is_stmt 1 view .LVU46
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 170              		.loc 1 129 11 is_stmt 0 view .LVU47
+ 171 0040 2068     		ldr	r0, [r4]
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 172              		.loc 1 129 28 view .LVU48
+ 173 0042 0361     		str	r3, [r0, #16]
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 174              		.loc 1 132 7 is_stmt 1 view .LVU49
+ 175 0044 049B     		ldr	r3, [sp, #16]
+ 176              	.LVL13:
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 177              		.loc 1 132 7 is_stmt 0 view .LVU50
+ 178 0046 2046     		mov	r0, r4
+ 179              	.LVL14:
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****       
+ 180              		.loc 1 132 7 view .LVU51
+ 181 0048 FFF7FEFF 		bl	DMA_MultiBufferSetConfig
+ 182              	.LVL15:
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     }
+ 183              		.loc 1 135 7 is_stmt 1 view .LVU52
+ARM GAS  /tmp/ccgvGc3k.s 			page 10
+
+
+ 184 004c 2268     		ldr	r2, [r4]
+ 185 004e 1368     		ldr	r3, [r2]
+ 186 0050 43F00103 		orr	r3, r3, #1
+ 187 0054 1360     		str	r3, [r2]
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 188              		.loc 1 104 21 is_stmt 0 view .LVU53
+ 189 0056 0020     		movs	r0, #0
+ 190 0058 E4E7     		b	.L8
+ 191              	.LVL16:
+ 192              	.L9:
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 193              		.loc 1 118 5 view .LVU54
+ 194 005a 0220     		movs	r0, #2
+ 195 005c E2E7     		b	.L8
+ 196              		.cfi_endproc
+ 197              	.LFE141:
+ 199              		.section	.text.HAL_DMAEx_MultiBufferStart_IT,"ax",%progbits
+ 200              		.align	1
+ 201              		.global	HAL_DMAEx_MultiBufferStart_IT
+ 202              		.syntax unified
+ 203              		.thumb
+ 204              		.thumb_func
+ 205              		.fpu fpv5-d16
+ 207              	HAL_DMAEx_MultiBufferStart_IT:
+ 208              	.LVL17:
+ 209              	.LFB142:
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 210              		.loc 1 157 1 is_stmt 1 view -0
+ 211              		.cfi_startproc
+ 212              		@ args = 4, pretend = 0, frame = 0
+ 213              		@ frame_needed = 0, uses_anonymous_args = 0
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 214              		.loc 1 157 1 is_stmt 0 view .LVU56
+ 215 0000 38B5     		push	{r3, r4, r5, lr}
+ 216              	.LCFI4:
+ 217              		.cfi_def_cfa_offset 16
+ 218              		.cfi_offset 3, -16
+ 219              		.cfi_offset 4, -12
+ 220              		.cfi_offset 5, -8
+ 221              		.cfi_offset 14, -4
+ 222 0002 0446     		mov	r4, r0
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 223              		.loc 1 158 3 is_stmt 1 view .LVU57
+ 224              	.LVL18:
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 225              		.loc 1 161 3 view .LVU58
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 226              		.loc 1 164 3 view .LVU59
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 227              		.loc 1 164 17 is_stmt 0 view .LVU60
+ 228 0004 8068     		ldr	r0, [r0, #8]
+ 229              	.LVL19:
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 230              		.loc 1 164 6 view .LVU61
+ 231 0006 8028     		cmp	r0, #128
+ 232 0008 11D0     		beq	.L302
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ARM GAS  /tmp/ccgvGc3k.s 			page 11
+
+
+ 233              		.loc 1 171 3 is_stmt 1 view .LVU62
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 234              		.loc 1 171 3 view .LVU63
+ 235 000a 94F83400 		ldrb	r0, [r4, #52]	@ zero_extendqisi2
+ 236 000e 0128     		cmp	r0, #1
+ 237 0010 00F06587 		beq	.L60
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 238              		.loc 1 171 3 discriminator 2 view .LVU64
+ 239 0014 0120     		movs	r0, #1
+ 240 0016 84F83400 		strb	r0, [r4, #52]
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 241              		.loc 1 171 3 discriminator 2 view .LVU65
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 242              		.loc 1 173 3 discriminator 2 view .LVU66
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 243              		.loc 1 173 33 is_stmt 0 discriminator 2 view .LVU67
+ 244 001a 94F83500 		ldrb	r0, [r4, #53]	@ zero_extendqisi2
+ 245 001e C0B2     		uxtb	r0, r0
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 246              		.loc 1 173 5 discriminator 2 view .LVU68
+ 247 0020 0128     		cmp	r0, #1
+ 248 0022 09D0     		beq	.L303
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 249              		.loc 1 212 5 is_stmt 1 view .LVU69
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 250              		.loc 1 212 5 view .LVU70
+ 251 0024 0023     		movs	r3, #0
+ 252              	.LVL20:
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 253              		.loc 1 212 5 is_stmt 0 view .LVU71
+ 254 0026 84F83430 		strb	r3, [r4, #52]
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 255              		.loc 1 212 5 is_stmt 1 view .LVU72
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }  
+ 256              		.loc 1 215 5 view .LVU73
+ 257              	.LVL21:
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }  
+ 258              		.loc 1 215 12 is_stmt 0 view .LVU74
+ 259 002a 0220     		movs	r0, #2
+ 260              	.LVL22:
+ 261              	.L16:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+ 262              		.loc 1 218 1 view .LVU75
+ 263 002c 38BD     		pop	{r3, r4, r5, pc}
+ 264              	.LVL23:
+ 265              	.L302:
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     return HAL_ERROR;
+ 266              		.loc 1 166 5 is_stmt 1 view .LVU76
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     return HAL_ERROR;
+ 267              		.loc 1 166 21 is_stmt 0 view .LVU77
+ 268 002e 4FF48073 		mov	r3, #256
+ 269              	.LVL24:
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     return HAL_ERROR;
+ 270              		.loc 1 166 21 view .LVU78
+ 271 0032 6365     		str	r3, [r4, #84]
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 272              		.loc 1 167 5 is_stmt 1 view .LVU79
+ARM GAS  /tmp/ccgvGc3k.s 			page 12
+
+
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 273              		.loc 1 167 12 is_stmt 0 view .LVU80
+ 274 0034 0120     		movs	r0, #1
+ 275 0036 F9E7     		b	.L16
+ 276              	.LVL25:
+ 277              	.L303:
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 278              		.loc 1 176 5 is_stmt 1 view .LVU81
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 279              		.loc 1 176 17 is_stmt 0 view .LVU82
+ 280 0038 0220     		movs	r0, #2
+ 281 003a 84F83500 		strb	r0, [r4, #53]
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 282              		.loc 1 179 5 is_stmt 1 view .LVU83
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 283              		.loc 1 179 21 is_stmt 0 view .LVU84
+ 284 003e 0020     		movs	r0, #0
+ 285 0040 6065     		str	r0, [r4, #84]
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 286              		.loc 1 182 5 is_stmt 1 view .LVU85
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 287              		.loc 1 182 9 is_stmt 0 view .LVU86
+ 288 0042 2568     		ldr	r5, [r4]
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 289              		.loc 1 182 24 view .LVU87
+ 290 0044 2868     		ldr	r0, [r5]
+ 291 0046 40F48020 		orr	r0, r0, #262144
+ 292 004a 2860     		str	r0, [r5]
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 293              		.loc 1 185 5 is_stmt 1 view .LVU88
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 294              		.loc 1 185 9 is_stmt 0 view .LVU89
+ 295 004c 2068     		ldr	r0, [r4]
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 296              		.loc 1 185 26 view .LVU90
+ 297 004e 0361     		str	r3, [r0, #16]
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 298              		.loc 1 188 5 is_stmt 1 view .LVU91
+ 299 0050 049B     		ldr	r3, [sp, #16]
+ 300              	.LVL26:
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 301              		.loc 1 188 5 is_stmt 0 view .LVU92
+ 302 0052 2046     		mov	r0, r4
+ 303              	.LVL27:
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 304              		.loc 1 188 5 view .LVU93
+ 305 0054 FFF7FEFF 		bl	DMA_MultiBufferSetConfig
+ 306              	.LVL28:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 307              		.loc 1 191 5 is_stmt 1 view .LVU94
+ 308 0058 2368     		ldr	r3, [r4]
+ 309 005a A54A     		ldr	r2, .L325
+ 310 005c 9342     		cmp	r3, r2
+ 311 005e 40F29880 		bls	.L18
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 312              		.loc 1 191 5 is_stmt 0 discriminator 1 view .LVU95
+ 313 0062 A2F58962 		sub	r2, r2, #1096
+ARM GAS  /tmp/ccgvGc3k.s 			page 13
+
+
+ 314 0066 9342     		cmp	r3, r2
+ 315 0068 31D0     		beq	.L61
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 316              		.loc 1 191 5 discriminator 3 view .LVU96
+ 317 006a 02F58062 		add	r2, r2, #1024
+ 318 006e 9342     		cmp	r3, r2
+ 319 0070 74D0     		beq	.L62
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 320              		.loc 1 191 5 discriminator 5 view .LVU97
+ 321 0072 A2F56872 		sub	r2, r2, #928
+ 322 0076 9342     		cmp	r3, r2
+ 323 0078 72D0     		beq	.L63
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 324              		.loc 1 191 5 discriminator 7 view .LVU98
+ 325 007a 02F58062 		add	r2, r2, #1024
+ 326 007e 9342     		cmp	r3, r2
+ 327 0080 70D0     		beq	.L64
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 328              		.loc 1 191 5 discriminator 9 view .LVU99
+ 329 0082 A2F58962 		sub	r2, r2, #1096
+ 330 0086 9342     		cmp	r3, r2
+ 331 0088 6ED0     		beq	.L65
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 332              		.loc 1 191 5 discriminator 11 view .LVU100
+ 333 008a 02F58062 		add	r2, r2, #1024
+ 334 008e 9342     		cmp	r3, r2
+ 335 0090 6DD0     		beq	.L66
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 336              		.loc 1 191 5 discriminator 13 view .LVU101
+ 337 0092 A2F56872 		sub	r2, r2, #928
+ 338 0096 9342     		cmp	r3, r2
+ 339 0098 6CD0     		beq	.L67
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 340              		.loc 1 191 5 discriminator 15 view .LVU102
+ 341 009a 02F58062 		add	r2, r2, #1024
+ 342 009e 9342     		cmp	r3, r2
+ 343 00a0 6BD0     		beq	.L68
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 344              		.loc 1 191 5 discriminator 17 view .LVU103
+ 345 00a2 A2F58962 		sub	r2, r2, #1096
+ 346 00a6 9342     		cmp	r3, r2
+ 347 00a8 6AD0     		beq	.L69
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 348              		.loc 1 191 5 discriminator 19 view .LVU104
+ 349 00aa 02F58062 		add	r2, r2, #1024
+ 350 00ae 9342     		cmp	r3, r2
+ 351 00b0 69D0     		beq	.L70
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 352              		.loc 1 191 5 discriminator 21 view .LVU105
+ 353 00b2 A2F56872 		sub	r2, r2, #928
+ 354 00b6 9342     		cmp	r3, r2
+ 355 00b8 68D0     		beq	.L71
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 356              		.loc 1 191 5 discriminator 23 view .LVU106
+ 357 00ba 02F58062 		add	r2, r2, #1024
+ 358 00be 9342     		cmp	r3, r2
+ 359 00c0 02D0     		beq	.L304
+ARM GAS  /tmp/ccgvGc3k.s 			page 14
+
+
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 360              		.loc 1 191 5 view .LVU107
+ 361 00c2 4FF00062 		mov	r2, #134217728
+ 362 00c6 03E0     		b	.L19
+ 363              	.L304:
+ 364 00c8 4FF40012 		mov	r2, #2097152
+ 365 00cc 00E0     		b	.L19
+ 366              	.L61:
+ 367 00ce 2022     		movs	r2, #32
+ 368              	.L19:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 369              		.loc 1 191 5 discriminator 50 view .LVU108
+ 370 00d0 884B     		ldr	r3, .L325+4
+ 371 00d2 DA60     		str	r2, [r3, #12]
+ 372              	.LVL29:
+ 373              	.L20:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 374              		.loc 1 192 5 is_stmt 1 view .LVU109
+ 375 00d4 2368     		ldr	r3, [r4]
+ 376 00d6 864A     		ldr	r2, .L325
+ 377 00d8 9342     		cmp	r3, r2
+ 378 00da 40F2CC81 		bls	.L26
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 379              		.loc 1 192 5 is_stmt 0 discriminator 1 view .LVU110
+ 380 00de A2F58962 		sub	r2, r2, #1096
+ 381 00e2 9342     		cmp	r3, r2
+ 382 00e4 00F06581 		beq	.L109
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 383              		.loc 1 192 5 discriminator 3 view .LVU111
+ 384 00e8 02F58062 		add	r2, r2, #1024
+ 385 00ec 9342     		cmp	r3, r2
+ 386 00ee 00F0A781 		beq	.L110
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 387              		.loc 1 192 5 discriminator 5 view .LVU112
+ 388 00f2 A2F56872 		sub	r2, r2, #928
+ 389 00f6 9342     		cmp	r3, r2
+ 390 00f8 00F0A481 		beq	.L111
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 391              		.loc 1 192 5 discriminator 7 view .LVU113
+ 392 00fc 02F58062 		add	r2, r2, #1024
+ 393 0100 9342     		cmp	r3, r2
+ 394 0102 00F0A181 		beq	.L112
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 395              		.loc 1 192 5 discriminator 9 view .LVU114
+ 396 0106 A2F58962 		sub	r2, r2, #1096
+ 397 010a 9342     		cmp	r3, r2
+ 398 010c 00F09E81 		beq	.L113
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 399              		.loc 1 192 5 discriminator 11 view .LVU115
+ 400 0110 02F58062 		add	r2, r2, #1024
+ 401 0114 9342     		cmp	r3, r2
+ 402 0116 00F09C81 		beq	.L114
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 403              		.loc 1 192 5 discriminator 13 view .LVU116
+ 404 011a A2F56872 		sub	r2, r2, #928
+ 405 011e 9342     		cmp	r3, r2
+ 406 0120 00F09A81 		beq	.L115
+ARM GAS  /tmp/ccgvGc3k.s 			page 15
+
+
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 407              		.loc 1 192 5 discriminator 15 view .LVU117
+ 408 0124 02F58062 		add	r2, r2, #1024
+ 409 0128 9342     		cmp	r3, r2
+ 410 012a 00F09881 		beq	.L116
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 411              		.loc 1 192 5 discriminator 17 view .LVU118
+ 412 012e A2F58962 		sub	r2, r2, #1096
+ 413 0132 9342     		cmp	r3, r2
+ 414 0134 00F09681 		beq	.L117
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 415              		.loc 1 192 5 discriminator 19 view .LVU119
+ 416 0138 02F58062 		add	r2, r2, #1024
+ 417 013c 9342     		cmp	r3, r2
+ 418 013e 00F09481 		beq	.L118
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 419              		.loc 1 192 5 discriminator 21 view .LVU120
+ 420 0142 A2F56872 		sub	r2, r2, #928
+ 421 0146 9342     		cmp	r3, r2
+ 422 0148 00F09281 		beq	.L119
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 423              		.loc 1 192 5 discriminator 23 view .LVU121
+ 424 014c 02F58062 		add	r2, r2, #1024
+ 425 0150 9342     		cmp	r3, r2
+ 426 0152 00F02B81 		beq	.L305
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 427              		.loc 1 192 5 view .LVU122
+ 428 0156 4FF08062 		mov	r2, #67108864
+ 429 015a 2BE1     		b	.L27
+ 430              	.LVL30:
+ 431              	.L62:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 432              		.loc 1 191 5 view .LVU123
+ 433 015c 2022     		movs	r2, #32
+ 434 015e B7E7     		b	.L19
+ 435              	.L63:
+ 436 0160 2022     		movs	r2, #32
+ 437 0162 B5E7     		b	.L19
+ 438              	.L64:
+ 439 0164 2022     		movs	r2, #32
+ 440 0166 B3E7     		b	.L19
+ 441              	.L65:
+ 442 0168 4FF40062 		mov	r2, #2048
+ 443 016c B0E7     		b	.L19
+ 444              	.L66:
+ 445 016e 4FF40062 		mov	r2, #2048
+ 446 0172 ADE7     		b	.L19
+ 447              	.L67:
+ 448 0174 4FF40062 		mov	r2, #2048
+ 449 0178 AAE7     		b	.L19
+ 450              	.L68:
+ 451 017a 4FF40062 		mov	r2, #2048
+ 452 017e A7E7     		b	.L19
+ 453              	.L69:
+ 454 0180 4FF40012 		mov	r2, #2097152
+ 455 0184 A4E7     		b	.L19
+ 456              	.L70:
+ARM GAS  /tmp/ccgvGc3k.s 			page 16
+
+
+ 457 0186 4FF40012 		mov	r2, #2097152
+ 458 018a A1E7     		b	.L19
+ 459              	.L71:
+ 460 018c 4FF40012 		mov	r2, #2097152
+ 461 0190 9EE7     		b	.L19
+ 462              	.L18:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 463              		.loc 1 191 5 discriminator 2 view .LVU124
+ 464 0192 594A     		ldr	r2, .L325+8
+ 465 0194 9342     		cmp	r3, r2
+ 466 0196 53D9     		bls	.L21
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 467              		.loc 1 191 5 discriminator 51 view .LVU125
+ 468 0198 A83A     		subs	r2, r2, #168
+ 469 019a 9342     		cmp	r3, r2
+ 470 019c 31D0     		beq	.L73
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 471              		.loc 1 191 5 discriminator 53 view .LVU126
+ 472 019e 02F58062 		add	r2, r2, #1024
+ 473 01a2 9342     		cmp	r3, r2
+ 474 01a4 31D0     		beq	.L74
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 475              		.loc 1 191 5 discriminator 55 view .LVU127
+ 476 01a6 A2F56872 		sub	r2, r2, #928
+ 477 01aa 9342     		cmp	r3, r2
+ 478 01ac 2FD0     		beq	.L75
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 479              		.loc 1 191 5 discriminator 57 view .LVU128
+ 480 01ae 02F58062 		add	r2, r2, #1024
+ 481 01b2 9342     		cmp	r3, r2
+ 482 01b4 2DD0     		beq	.L76
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 483              		.loc 1 191 5 discriminator 59 view .LVU129
+ 484 01b6 A2F58962 		sub	r2, r2, #1096
+ 485 01ba 9342     		cmp	r3, r2
+ 486 01bc 2BD0     		beq	.L77
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 487              		.loc 1 191 5 discriminator 61 view .LVU130
+ 488 01be 02F58062 		add	r2, r2, #1024
+ 489 01c2 9342     		cmp	r3, r2
+ 490 01c4 2AD0     		beq	.L78
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 491              		.loc 1 191 5 discriminator 63 view .LVU131
+ 492 01c6 A2F56872 		sub	r2, r2, #928
+ 493 01ca 9342     		cmp	r3, r2
+ 494 01cc 29D0     		beq	.L79
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 495              		.loc 1 191 5 discriminator 65 view .LVU132
+ 496 01ce 02F58062 		add	r2, r2, #1024
+ 497 01d2 9342     		cmp	r3, r2
+ 498 01d4 28D0     		beq	.L80
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 499              		.loc 1 191 5 discriminator 67 view .LVU133
+ 500 01d6 A2F58962 		sub	r2, r2, #1096
+ 501 01da 9342     		cmp	r3, r2
+ 502 01dc 27D0     		beq	.L81
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ARM GAS  /tmp/ccgvGc3k.s 			page 17
+
+
+ 503              		.loc 1 191 5 discriminator 69 view .LVU134
+ 504 01de 02F58062 		add	r2, r2, #1024
+ 505 01e2 9342     		cmp	r3, r2
+ 506 01e4 26D0     		beq	.L82
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 507              		.loc 1 191 5 discriminator 71 view .LVU135
+ 508 01e6 A2F56872 		sub	r2, r2, #928
+ 509 01ea 9342     		cmp	r3, r2
+ 510 01ec 25D0     		beq	.L83
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 511              		.loc 1 191 5 discriminator 73 view .LVU136
+ 512 01ee 02F58062 		add	r2, r2, #1024
+ 513 01f2 9342     		cmp	r3, r2
+ 514 01f4 02D0     		beq	.L306
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 515              		.loc 1 191 5 view .LVU137
+ 516 01f6 4FF00062 		mov	r2, #134217728
+ 517 01fa 03E0     		b	.L22
+ 518              	.L306:
+ 519 01fc 4FF40012 		mov	r2, #2097152
+ 520 0200 00E0     		b	.L22
+ 521              	.L73:
+ 522 0202 2022     		movs	r2, #32
+ 523              	.L22:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 524              		.loc 1 191 5 discriminator 100 view .LVU138
+ 525 0204 3B4B     		ldr	r3, .L325+4
+ 526 0206 9A60     		str	r2, [r3, #8]
+ 527              	.LVL31:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 528              		.loc 1 191 5 discriminator 100 view .LVU139
+ 529 0208 64E7     		b	.L20
+ 530              	.LVL32:
+ 531              	.L74:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 532              		.loc 1 191 5 view .LVU140
+ 533 020a 2022     		movs	r2, #32
+ 534 020c FAE7     		b	.L22
+ 535              	.L75:
+ 536 020e 2022     		movs	r2, #32
+ 537 0210 F8E7     		b	.L22
+ 538              	.L76:
+ 539 0212 2022     		movs	r2, #32
+ 540 0214 F6E7     		b	.L22
+ 541              	.L77:
+ 542 0216 4FF40062 		mov	r2, #2048
+ 543 021a F3E7     		b	.L22
+ 544              	.L78:
+ 545 021c 4FF40062 		mov	r2, #2048
+ 546 0220 F0E7     		b	.L22
+ 547              	.L79:
+ 548 0222 4FF40062 		mov	r2, #2048
+ 549 0226 EDE7     		b	.L22
+ 550              	.L80:
+ 551 0228 4FF40062 		mov	r2, #2048
+ 552 022c EAE7     		b	.L22
+ 553              	.L81:
+ARM GAS  /tmp/ccgvGc3k.s 			page 18
+
+
+ 554 022e 4FF40012 		mov	r2, #2097152
+ 555 0232 E7E7     		b	.L22
+ 556              	.L82:
+ 557 0234 4FF40012 		mov	r2, #2097152
+ 558 0238 E4E7     		b	.L22
+ 559              	.L83:
+ 560 023a 4FF40012 		mov	r2, #2097152
+ 561 023e E1E7     		b	.L22
+ 562              	.L21:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 563              		.loc 1 191 5 discriminator 52 view .LVU141
+ 564 0240 2E4A     		ldr	r2, .L325+12
+ 565 0242 9342     		cmp	r3, r2
+ 566 0244 5ED9     		bls	.L23
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 567              		.loc 1 191 5 discriminator 102 view .LVU142
+ 568 0246 483A     		subs	r2, r2, #72
+ 569 0248 9342     		cmp	r3, r2
+ 570 024a 31D0     		beq	.L85
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 571              		.loc 1 191 5 discriminator 104 view .LVU143
+ 572 024c 02F58062 		add	r2, r2, #1024
+ 573 0250 9342     		cmp	r3, r2
+ 574 0252 31D0     		beq	.L86
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 575              		.loc 1 191 5 discriminator 106 view .LVU144
+ 576 0254 A2F56872 		sub	r2, r2, #928
+ 577 0258 9342     		cmp	r3, r2
+ 578 025a 2FD0     		beq	.L87
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 579              		.loc 1 191 5 discriminator 108 view .LVU145
+ 580 025c 02F58062 		add	r2, r2, #1024
+ 581 0260 9342     		cmp	r3, r2
+ 582 0262 2DD0     		beq	.L88
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 583              		.loc 1 191 5 discriminator 110 view .LVU146
+ 584 0264 A2F58962 		sub	r2, r2, #1096
+ 585 0268 9342     		cmp	r3, r2
+ 586 026a 2BD0     		beq	.L89
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 587              		.loc 1 191 5 discriminator 112 view .LVU147
+ 588 026c 02F58062 		add	r2, r2, #1024
+ 589 0270 9342     		cmp	r3, r2
+ 590 0272 2AD0     		beq	.L90
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 591              		.loc 1 191 5 discriminator 114 view .LVU148
+ 592 0274 A2F56872 		sub	r2, r2, #928
+ 593 0278 9342     		cmp	r3, r2
+ 594 027a 29D0     		beq	.L91
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 595              		.loc 1 191 5 discriminator 116 view .LVU149
+ 596 027c 02F58062 		add	r2, r2, #1024
+ 597 0280 9342     		cmp	r3, r2
+ 598 0282 28D0     		beq	.L92
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 599              		.loc 1 191 5 discriminator 118 view .LVU150
+ 600 0284 A2F58962 		sub	r2, r2, #1096
+ARM GAS  /tmp/ccgvGc3k.s 			page 19
+
+
+ 601 0288 9342     		cmp	r3, r2
+ 602 028a 27D0     		beq	.L93
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 603              		.loc 1 191 5 discriminator 120 view .LVU151
+ 604 028c 02F58062 		add	r2, r2, #1024
+ 605 0290 9342     		cmp	r3, r2
+ 606 0292 26D0     		beq	.L94
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 607              		.loc 1 191 5 discriminator 122 view .LVU152
+ 608 0294 A2F56872 		sub	r2, r2, #928
+ 609 0298 9342     		cmp	r3, r2
+ 610 029a 25D0     		beq	.L95
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 611              		.loc 1 191 5 discriminator 124 view .LVU153
+ 612 029c 02F58062 		add	r2, r2, #1024
+ 613 02a0 9342     		cmp	r3, r2
+ 614 02a2 02D0     		beq	.L307
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 615              		.loc 1 191 5 view .LVU154
+ 616 02a4 4FF00063 		mov	r3, #134217728
+ 617 02a8 03E0     		b	.L24
+ 618              	.L307:
+ 619 02aa 4FF40013 		mov	r3, #2097152
+ 620 02ae 00E0     		b	.L24
+ 621              	.L85:
+ 622 02b0 2023     		movs	r3, #32
+ 623              	.L24:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 624              		.loc 1 191 5 discriminator 151 view .LVU155
+ 625 02b2 134A     		ldr	r2, .L325+16
+ 626 02b4 D360     		str	r3, [r2, #12]
+ 627              	.LVL33:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 628              		.loc 1 191 5 discriminator 151 view .LVU156
+ 629 02b6 0DE7     		b	.L20
+ 630              	.LVL34:
+ 631              	.L86:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 632              		.loc 1 191 5 view .LVU157
+ 633 02b8 2023     		movs	r3, #32
+ 634 02ba FAE7     		b	.L24
+ 635              	.L87:
+ 636 02bc 2023     		movs	r3, #32
+ 637 02be F8E7     		b	.L24
+ 638              	.L88:
+ 639 02c0 2023     		movs	r3, #32
+ 640 02c2 F6E7     		b	.L24
+ 641              	.L89:
+ 642 02c4 4FF40063 		mov	r3, #2048
+ 643 02c8 F3E7     		b	.L24
+ 644              	.L90:
+ 645 02ca 4FF40063 		mov	r3, #2048
+ 646 02ce F0E7     		b	.L24
+ 647              	.L91:
+ 648 02d0 4FF40063 		mov	r3, #2048
+ 649 02d4 EDE7     		b	.L24
+ 650              	.L92:
+ARM GAS  /tmp/ccgvGc3k.s 			page 20
+
+
+ 651 02d6 4FF40063 		mov	r3, #2048
+ 652 02da EAE7     		b	.L24
+ 653              	.L93:
+ 654 02dc 4FF40013 		mov	r3, #2097152
+ 655 02e0 E7E7     		b	.L24
+ 656              	.L94:
+ 657 02e2 4FF40013 		mov	r3, #2097152
+ 658 02e6 E4E7     		b	.L24
+ 659              	.L95:
+ 660 02e8 4FF40013 		mov	r3, #2097152
+ 661 02ec E1E7     		b	.L24
+ 662              	.L326:
+ 663 02ee 00BF     		.align	2
+ 664              	.L325:
+ 665 02f0 58640240 		.word	1073898584
+ 666 02f4 00640240 		.word	1073898496
+ 667 02f8 B8600240 		.word	1073897656
+ 668 02fc 58600240 		.word	1073897560
+ 669 0300 00600240 		.word	1073897472
+ 670              	.L23:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 671              		.loc 1 191 5 discriminator 103 view .LVU158
+ 672 0304 B14A     		ldr	r2, .L327
+ 673 0306 9342     		cmp	r3, r2
+ 674 0308 31D0     		beq	.L97
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 675              		.loc 1 191 5 discriminator 153 view .LVU159
+ 676 030a 02F58062 		add	r2, r2, #1024
+ 677 030e 9342     		cmp	r3, r2
+ 678 0310 31D0     		beq	.L98
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 679              		.loc 1 191 5 discriminator 155 view .LVU160
+ 680 0312 A2F56872 		sub	r2, r2, #928
+ 681 0316 9342     		cmp	r3, r2
+ 682 0318 2FD0     		beq	.L99
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 683              		.loc 1 191 5 discriminator 157 view .LVU161
+ 684 031a 02F58062 		add	r2, r2, #1024
+ 685 031e 9342     		cmp	r3, r2
+ 686 0320 2DD0     		beq	.L100
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 687              		.loc 1 191 5 discriminator 159 view .LVU162
+ 688 0322 A2F58962 		sub	r2, r2, #1096
+ 689 0326 9342     		cmp	r3, r2
+ 690 0328 2BD0     		beq	.L101
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 691              		.loc 1 191 5 discriminator 161 view .LVU163
+ 692 032a 02F58062 		add	r2, r2, #1024
+ 693 032e 9342     		cmp	r3, r2
+ 694 0330 2AD0     		beq	.L102
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 695              		.loc 1 191 5 discriminator 163 view .LVU164
+ 696 0332 A2F56872 		sub	r2, r2, #928
+ 697 0336 9342     		cmp	r3, r2
+ 698 0338 29D0     		beq	.L103
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 699              		.loc 1 191 5 discriminator 165 view .LVU165
+ARM GAS  /tmp/ccgvGc3k.s 			page 21
+
+
+ 700 033a 02F58062 		add	r2, r2, #1024
+ 701 033e 9342     		cmp	r3, r2
+ 702 0340 28D0     		beq	.L104
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 703              		.loc 1 191 5 discriminator 167 view .LVU166
+ 704 0342 A2F58962 		sub	r2, r2, #1096
+ 705 0346 9342     		cmp	r3, r2
+ 706 0348 27D0     		beq	.L105
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 707              		.loc 1 191 5 discriminator 169 view .LVU167
+ 708 034a 02F58062 		add	r2, r2, #1024
+ 709 034e 9342     		cmp	r3, r2
+ 710 0350 26D0     		beq	.L106
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 711              		.loc 1 191 5 discriminator 171 view .LVU168
+ 712 0352 A2F56872 		sub	r2, r2, #928
+ 713 0356 9342     		cmp	r3, r2
+ 714 0358 25D0     		beq	.L107
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 715              		.loc 1 191 5 discriminator 173 view .LVU169
+ 716 035a 02F58062 		add	r2, r2, #1024
+ 717 035e 9342     		cmp	r3, r2
+ 718 0360 02D0     		beq	.L308
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 719              		.loc 1 191 5 view .LVU170
+ 720 0362 4FF00063 		mov	r3, #134217728
+ 721 0366 03E0     		b	.L25
+ 722              	.L308:
+ 723 0368 4FF40013 		mov	r3, #2097152
+ 724 036c 00E0     		b	.L25
+ 725              	.L97:
+ 726 036e 2023     		movs	r3, #32
+ 727              	.L25:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 728              		.loc 1 191 5 discriminator 200 view .LVU171
+ 729 0370 974A     		ldr	r2, .L327+4
+ 730 0372 9360     		str	r3, [r2, #8]
+ 731              	.LVL35:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 732              		.loc 1 191 5 discriminator 200 view .LVU172
+ 733 0374 AEE6     		b	.L20
+ 734              	.LVL36:
+ 735              	.L98:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ 736              		.loc 1 191 5 view .LVU173
+ 737 0376 2023     		movs	r3, #32
+ 738 0378 FAE7     		b	.L25
+ 739              	.L99:
+ 740 037a 2023     		movs	r3, #32
+ 741 037c F8E7     		b	.L25
+ 742              	.L100:
+ 743 037e 2023     		movs	r3, #32
+ 744 0380 F6E7     		b	.L25
+ 745              	.L101:
+ 746 0382 4FF40063 		mov	r3, #2048
+ 747 0386 F3E7     		b	.L25
+ 748              	.L102:
+ARM GAS  /tmp/ccgvGc3k.s 			page 22
+
+
+ 749 0388 4FF40063 		mov	r3, #2048
+ 750 038c F0E7     		b	.L25
+ 751              	.L103:
+ 752 038e 4FF40063 		mov	r3, #2048
+ 753 0392 EDE7     		b	.L25
+ 754              	.L104:
+ 755 0394 4FF40063 		mov	r3, #2048
+ 756 0398 EAE7     		b	.L25
+ 757              	.L105:
+ 758 039a 4FF40013 		mov	r3, #2097152
+ 759 039e E7E7     		b	.L25
+ 760              	.L106:
+ 761 03a0 4FF40013 		mov	r3, #2097152
+ 762 03a4 E4E7     		b	.L25
+ 763              	.L107:
+ 764 03a6 4FF40013 		mov	r3, #2097152
+ 765 03aa E1E7     		b	.L25
+ 766              	.LVL37:
+ 767              	.L305:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 768              		.loc 1 192 5 view .LVU174
+ 769 03ac 4FF48012 		mov	r2, #1048576
+ 770 03b0 00E0     		b	.L27
+ 771              	.L109:
+ 772 03b2 1022     		movs	r2, #16
+ 773              	.L27:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 774              		.loc 1 192 5 discriminator 50 view .LVU175
+ 775 03b4 874B     		ldr	r3, .L327+8
+ 776 03b6 DA60     		str	r2, [r3, #12]
+ 777              	.L28:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 778              		.loc 1 193 5 is_stmt 1 view .LVU176
+ 779 03b8 2368     		ldr	r3, [r4]
+ 780 03ba 874A     		ldr	r2, .L327+12
+ 781 03bc 9342     		cmp	r3, r2
+ 782 03be 40F2CD81 		bls	.L34
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 783              		.loc 1 193 5 is_stmt 0 discriminator 1 view .LVU177
+ 784 03c2 A2F58962 		sub	r2, r2, #1096
+ 785 03c6 9342     		cmp	r3, r2
+ 786 03c8 00F06681 		beq	.L157
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 787              		.loc 1 193 5 discriminator 3 view .LVU178
+ 788 03cc 02F58062 		add	r2, r2, #1024
+ 789 03d0 9342     		cmp	r3, r2
+ 790 03d2 00F0A881 		beq	.L158
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 791              		.loc 1 193 5 discriminator 5 view .LVU179
+ 792 03d6 A2F56872 		sub	r2, r2, #928
+ 793 03da 9342     		cmp	r3, r2
+ 794 03dc 00F0A581 		beq	.L159
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 795              		.loc 1 193 5 discriminator 7 view .LVU180
+ 796 03e0 02F58062 		add	r2, r2, #1024
+ 797 03e4 9342     		cmp	r3, r2
+ 798 03e6 00F0A281 		beq	.L160
+ARM GAS  /tmp/ccgvGc3k.s 			page 23
+
+
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 799              		.loc 1 193 5 discriminator 9 view .LVU181
+ 800 03ea A2F58962 		sub	r2, r2, #1096
+ 801 03ee 9342     		cmp	r3, r2
+ 802 03f0 00F09F81 		beq	.L161
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 803              		.loc 1 193 5 discriminator 11 view .LVU182
+ 804 03f4 02F58062 		add	r2, r2, #1024
+ 805 03f8 9342     		cmp	r3, r2
+ 806 03fa 00F09D81 		beq	.L162
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 807              		.loc 1 193 5 discriminator 13 view .LVU183
+ 808 03fe A2F56872 		sub	r2, r2, #928
+ 809 0402 9342     		cmp	r3, r2
+ 810 0404 00F09B81 		beq	.L163
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 811              		.loc 1 193 5 discriminator 15 view .LVU184
+ 812 0408 02F58062 		add	r2, r2, #1024
+ 813 040c 9342     		cmp	r3, r2
+ 814 040e 00F09981 		beq	.L164
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 815              		.loc 1 193 5 discriminator 17 view .LVU185
+ 816 0412 A2F58962 		sub	r2, r2, #1096
+ 817 0416 9342     		cmp	r3, r2
+ 818 0418 00F09781 		beq	.L165
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 819              		.loc 1 193 5 discriminator 19 view .LVU186
+ 820 041c 02F58062 		add	r2, r2, #1024
+ 821 0420 9342     		cmp	r3, r2
+ 822 0422 00F09581 		beq	.L166
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 823              		.loc 1 193 5 discriminator 21 view .LVU187
+ 824 0426 A2F56872 		sub	r2, r2, #928
+ 825 042a 9342     		cmp	r3, r2
+ 826 042c 00F09381 		beq	.L167
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 827              		.loc 1 193 5 discriminator 23 view .LVU188
+ 828 0430 02F58062 		add	r2, r2, #1024
+ 829 0434 9342     		cmp	r3, r2
+ 830 0436 00F02C81 		beq	.L309
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 831              		.loc 1 193 5 view .LVU189
+ 832 043a 4FF00072 		mov	r2, #33554432
+ 833 043e 2CE1     		b	.L35
+ 834              	.L110:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 835              		.loc 1 192 5 view .LVU190
+ 836 0440 1022     		movs	r2, #16
+ 837 0442 B7E7     		b	.L27
+ 838              	.L111:
+ 839 0444 1022     		movs	r2, #16
+ 840 0446 B5E7     		b	.L27
+ 841              	.L112:
+ 842 0448 1022     		movs	r2, #16
+ 843 044a B3E7     		b	.L27
+ 844              	.L113:
+ 845 044c 4FF48062 		mov	r2, #1024
+ARM GAS  /tmp/ccgvGc3k.s 			page 24
+
+
+ 846 0450 B0E7     		b	.L27
+ 847              	.L114:
+ 848 0452 4FF48062 		mov	r2, #1024
+ 849 0456 ADE7     		b	.L27
+ 850              	.L115:
+ 851 0458 4FF48062 		mov	r2, #1024
+ 852 045c AAE7     		b	.L27
+ 853              	.L116:
+ 854 045e 4FF48062 		mov	r2, #1024
+ 855 0462 A7E7     		b	.L27
+ 856              	.L117:
+ 857 0464 4FF48012 		mov	r2, #1048576
+ 858 0468 A4E7     		b	.L27
+ 859              	.L118:
+ 860 046a 4FF48012 		mov	r2, #1048576
+ 861 046e A1E7     		b	.L27
+ 862              	.L119:
+ 863 0470 4FF48012 		mov	r2, #1048576
+ 864 0474 9EE7     		b	.L27
+ 865              	.L26:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 866              		.loc 1 192 5 discriminator 2 view .LVU191
+ 867 0476 594A     		ldr	r2, .L327+16
+ 868 0478 9342     		cmp	r3, r2
+ 869 047a 53D9     		bls	.L29
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 870              		.loc 1 192 5 discriminator 51 view .LVU192
+ 871 047c A83A     		subs	r2, r2, #168
+ 872 047e 9342     		cmp	r3, r2
+ 873 0480 31D0     		beq	.L121
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 874              		.loc 1 192 5 discriminator 53 view .LVU193
+ 875 0482 02F58062 		add	r2, r2, #1024
+ 876 0486 9342     		cmp	r3, r2
+ 877 0488 31D0     		beq	.L122
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 878              		.loc 1 192 5 discriminator 55 view .LVU194
+ 879 048a A2F56872 		sub	r2, r2, #928
+ 880 048e 9342     		cmp	r3, r2
+ 881 0490 2FD0     		beq	.L123
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 882              		.loc 1 192 5 discriminator 57 view .LVU195
+ 883 0492 02F58062 		add	r2, r2, #1024
+ 884 0496 9342     		cmp	r3, r2
+ 885 0498 2DD0     		beq	.L124
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 886              		.loc 1 192 5 discriminator 59 view .LVU196
+ 887 049a A2F58962 		sub	r2, r2, #1096
+ 888 049e 9342     		cmp	r3, r2
+ 889 04a0 2BD0     		beq	.L125
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 890              		.loc 1 192 5 discriminator 61 view .LVU197
+ 891 04a2 02F58062 		add	r2, r2, #1024
+ 892 04a6 9342     		cmp	r3, r2
+ 893 04a8 2AD0     		beq	.L126
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 894              		.loc 1 192 5 discriminator 63 view .LVU198
+ARM GAS  /tmp/ccgvGc3k.s 			page 25
+
+
+ 895 04aa A2F56872 		sub	r2, r2, #928
+ 896 04ae 9342     		cmp	r3, r2
+ 897 04b0 29D0     		beq	.L127
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 898              		.loc 1 192 5 discriminator 65 view .LVU199
+ 899 04b2 02F58062 		add	r2, r2, #1024
+ 900 04b6 9342     		cmp	r3, r2
+ 901 04b8 28D0     		beq	.L128
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 902              		.loc 1 192 5 discriminator 67 view .LVU200
+ 903 04ba A2F58962 		sub	r2, r2, #1096
+ 904 04be 9342     		cmp	r3, r2
+ 905 04c0 27D0     		beq	.L129
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 906              		.loc 1 192 5 discriminator 69 view .LVU201
+ 907 04c2 02F58062 		add	r2, r2, #1024
+ 908 04c6 9342     		cmp	r3, r2
+ 909 04c8 26D0     		beq	.L130
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 910              		.loc 1 192 5 discriminator 71 view .LVU202
+ 911 04ca A2F56872 		sub	r2, r2, #928
+ 912 04ce 9342     		cmp	r3, r2
+ 913 04d0 25D0     		beq	.L131
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 914              		.loc 1 192 5 discriminator 73 view .LVU203
+ 915 04d2 02F58062 		add	r2, r2, #1024
+ 916 04d6 9342     		cmp	r3, r2
+ 917 04d8 02D0     		beq	.L310
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 918              		.loc 1 192 5 view .LVU204
+ 919 04da 4FF08062 		mov	r2, #67108864
+ 920 04de 03E0     		b	.L30
+ 921              	.L310:
+ 922 04e0 4FF48012 		mov	r2, #1048576
+ 923 04e4 00E0     		b	.L30
+ 924              	.L121:
+ 925 04e6 1022     		movs	r2, #16
+ 926              	.L30:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 927              		.loc 1 192 5 discriminator 100 view .LVU205
+ 928 04e8 3A4B     		ldr	r3, .L327+8
+ 929 04ea 9A60     		str	r2, [r3, #8]
+ 930 04ec 64E7     		b	.L28
+ 931              	.L122:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 932              		.loc 1 192 5 view .LVU206
+ 933 04ee 1022     		movs	r2, #16
+ 934 04f0 FAE7     		b	.L30
+ 935              	.L123:
+ 936 04f2 1022     		movs	r2, #16
+ 937 04f4 F8E7     		b	.L30
+ 938              	.L124:
+ 939 04f6 1022     		movs	r2, #16
+ 940 04f8 F6E7     		b	.L30
+ 941              	.L125:
+ 942 04fa 4FF48062 		mov	r2, #1024
+ 943 04fe F3E7     		b	.L30
+ARM GAS  /tmp/ccgvGc3k.s 			page 26
+
+
+ 944              	.L126:
+ 945 0500 4FF48062 		mov	r2, #1024
+ 946 0504 F0E7     		b	.L30
+ 947              	.L127:
+ 948 0506 4FF48062 		mov	r2, #1024
+ 949 050a EDE7     		b	.L30
+ 950              	.L128:
+ 951 050c 4FF48062 		mov	r2, #1024
+ 952 0510 EAE7     		b	.L30
+ 953              	.L129:
+ 954 0512 4FF48012 		mov	r2, #1048576
+ 955 0516 E7E7     		b	.L30
+ 956              	.L130:
+ 957 0518 4FF48012 		mov	r2, #1048576
+ 958 051c E4E7     		b	.L30
+ 959              	.L131:
+ 960 051e 4FF48012 		mov	r2, #1048576
+ 961 0522 E1E7     		b	.L30
+ 962              	.L29:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 963              		.loc 1 192 5 discriminator 52 view .LVU207
+ 964 0524 2E4A     		ldr	r2, .L327+20
+ 965 0526 9342     		cmp	r3, r2
+ 966 0528 5FD9     		bls	.L31
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 967              		.loc 1 192 5 discriminator 102 view .LVU208
+ 968 052a 483A     		subs	r2, r2, #72
+ 969 052c 9342     		cmp	r3, r2
+ 970 052e 31D0     		beq	.L133
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 971              		.loc 1 192 5 discriminator 104 view .LVU209
+ 972 0530 02F58062 		add	r2, r2, #1024
+ 973 0534 9342     		cmp	r3, r2
+ 974 0536 31D0     		beq	.L134
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 975              		.loc 1 192 5 discriminator 106 view .LVU210
+ 976 0538 A2F56872 		sub	r2, r2, #928
+ 977 053c 9342     		cmp	r3, r2
+ 978 053e 2FD0     		beq	.L135
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 979              		.loc 1 192 5 discriminator 108 view .LVU211
+ 980 0540 02F58062 		add	r2, r2, #1024
+ 981 0544 9342     		cmp	r3, r2
+ 982 0546 2DD0     		beq	.L136
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 983              		.loc 1 192 5 discriminator 110 view .LVU212
+ 984 0548 A2F58962 		sub	r2, r2, #1096
+ 985 054c 9342     		cmp	r3, r2
+ 986 054e 2BD0     		beq	.L137
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 987              		.loc 1 192 5 discriminator 112 view .LVU213
+ 988 0550 02F58062 		add	r2, r2, #1024
+ 989 0554 9342     		cmp	r3, r2
+ 990 0556 2AD0     		beq	.L138
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 991              		.loc 1 192 5 discriminator 114 view .LVU214
+ 992 0558 A2F56872 		sub	r2, r2, #928
+ARM GAS  /tmp/ccgvGc3k.s 			page 27
+
+
+ 993 055c 9342     		cmp	r3, r2
+ 994 055e 29D0     		beq	.L139
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 995              		.loc 1 192 5 discriminator 116 view .LVU215
+ 996 0560 02F58062 		add	r2, r2, #1024
+ 997 0564 9342     		cmp	r3, r2
+ 998 0566 28D0     		beq	.L140
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 999              		.loc 1 192 5 discriminator 118 view .LVU216
+ 1000 0568 A2F58962 		sub	r2, r2, #1096
+ 1001 056c 9342     		cmp	r3, r2
+ 1002 056e 27D0     		beq	.L141
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1003              		.loc 1 192 5 discriminator 120 view .LVU217
+ 1004 0570 02F58062 		add	r2, r2, #1024
+ 1005 0574 9342     		cmp	r3, r2
+ 1006 0576 26D0     		beq	.L142
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1007              		.loc 1 192 5 discriminator 122 view .LVU218
+ 1008 0578 A2F56872 		sub	r2, r2, #928
+ 1009 057c 9342     		cmp	r3, r2
+ 1010 057e 31D0     		beq	.L143
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1011              		.loc 1 192 5 discriminator 124 view .LVU219
+ 1012 0580 02F58062 		add	r2, r2, #1024
+ 1013 0584 9342     		cmp	r3, r2
+ 1014 0586 02D0     		beq	.L311
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1015              		.loc 1 192 5 view .LVU220
+ 1016 0588 4FF08063 		mov	r3, #67108864
+ 1017 058c 03E0     		b	.L32
+ 1018              	.L311:
+ 1019 058e 4FF48013 		mov	r3, #1048576
+ 1020 0592 00E0     		b	.L32
+ 1021              	.L133:
+ 1022 0594 1023     		movs	r3, #16
+ 1023              	.L32:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1024              		.loc 1 192 5 discriminator 151 view .LVU221
+ 1025 0596 0E4A     		ldr	r2, .L327+4
+ 1026 0598 D360     		str	r3, [r2, #12]
+ 1027 059a 0DE7     		b	.L28
+ 1028              	.L134:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1029              		.loc 1 192 5 view .LVU222
+ 1030 059c 1023     		movs	r3, #16
+ 1031 059e FAE7     		b	.L32
+ 1032              	.L135:
+ 1033 05a0 1023     		movs	r3, #16
+ 1034 05a2 F8E7     		b	.L32
+ 1035              	.L136:
+ 1036 05a4 1023     		movs	r3, #16
+ 1037 05a6 F6E7     		b	.L32
+ 1038              	.L137:
+ 1039 05a8 4FF48063 		mov	r3, #1024
+ 1040 05ac F3E7     		b	.L32
+ 1041              	.L138:
+ARM GAS  /tmp/ccgvGc3k.s 			page 28
+
+
+ 1042 05ae 4FF48063 		mov	r3, #1024
+ 1043 05b2 F0E7     		b	.L32
+ 1044              	.L139:
+ 1045 05b4 4FF48063 		mov	r3, #1024
+ 1046 05b8 EDE7     		b	.L32
+ 1047              	.L140:
+ 1048 05ba 4FF48063 		mov	r3, #1024
+ 1049 05be EAE7     		b	.L32
+ 1050              	.L141:
+ 1051 05c0 4FF48013 		mov	r3, #1048576
+ 1052 05c4 E7E7     		b	.L32
+ 1053              	.L142:
+ 1054 05c6 4FF48013 		mov	r3, #1048576
+ 1055 05ca E4E7     		b	.L32
+ 1056              	.L328:
+ 1057              		.align	2
+ 1058              	.L327:
+ 1059 05cc 10600240 		.word	1073897488
+ 1060 05d0 00600240 		.word	1073897472
+ 1061 05d4 00640240 		.word	1073898496
+ 1062 05d8 58640240 		.word	1073898584
+ 1063 05dc B8600240 		.word	1073897656
+ 1064 05e0 58600240 		.word	1073897560
+ 1065              	.L143:
+ 1066 05e4 4FF48013 		mov	r3, #1048576
+ 1067 05e8 D5E7     		b	.L32
+ 1068              	.L31:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1069              		.loc 1 192 5 discriminator 103 view .LVU223
+ 1070 05ea B24A     		ldr	r2, .L329
+ 1071 05ec 9342     		cmp	r3, r2
+ 1072 05ee 31D0     		beq	.L145
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1073              		.loc 1 192 5 discriminator 153 view .LVU224
+ 1074 05f0 02F58062 		add	r2, r2, #1024
+ 1075 05f4 9342     		cmp	r3, r2
+ 1076 05f6 31D0     		beq	.L146
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1077              		.loc 1 192 5 discriminator 155 view .LVU225
+ 1078 05f8 A2F56872 		sub	r2, r2, #928
+ 1079 05fc 9342     		cmp	r3, r2
+ 1080 05fe 2FD0     		beq	.L147
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1081              		.loc 1 192 5 discriminator 157 view .LVU226
+ 1082 0600 02F58062 		add	r2, r2, #1024
+ 1083 0604 9342     		cmp	r3, r2
+ 1084 0606 2DD0     		beq	.L148
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1085              		.loc 1 192 5 discriminator 159 view .LVU227
+ 1086 0608 A2F58962 		sub	r2, r2, #1096
+ 1087 060c 9342     		cmp	r3, r2
+ 1088 060e 2BD0     		beq	.L149
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1089              		.loc 1 192 5 discriminator 161 view .LVU228
+ 1090 0610 02F58062 		add	r2, r2, #1024
+ 1091 0614 9342     		cmp	r3, r2
+ 1092 0616 2AD0     		beq	.L150
+ARM GAS  /tmp/ccgvGc3k.s 			page 29
+
+
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1093              		.loc 1 192 5 discriminator 163 view .LVU229
+ 1094 0618 A2F56872 		sub	r2, r2, #928
+ 1095 061c 9342     		cmp	r3, r2
+ 1096 061e 29D0     		beq	.L151
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1097              		.loc 1 192 5 discriminator 165 view .LVU230
+ 1098 0620 02F58062 		add	r2, r2, #1024
+ 1099 0624 9342     		cmp	r3, r2
+ 1100 0626 28D0     		beq	.L152
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1101              		.loc 1 192 5 discriminator 167 view .LVU231
+ 1102 0628 A2F58962 		sub	r2, r2, #1096
+ 1103 062c 9342     		cmp	r3, r2
+ 1104 062e 27D0     		beq	.L153
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1105              		.loc 1 192 5 discriminator 169 view .LVU232
+ 1106 0630 02F58062 		add	r2, r2, #1024
+ 1107 0634 9342     		cmp	r3, r2
+ 1108 0636 26D0     		beq	.L154
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1109              		.loc 1 192 5 discriminator 171 view .LVU233
+ 1110 0638 A2F56872 		sub	r2, r2, #928
+ 1111 063c 9342     		cmp	r3, r2
+ 1112 063e 25D0     		beq	.L155
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1113              		.loc 1 192 5 discriminator 173 view .LVU234
+ 1114 0640 02F58062 		add	r2, r2, #1024
+ 1115 0644 9342     		cmp	r3, r2
+ 1116 0646 02D0     		beq	.L312
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1117              		.loc 1 192 5 view .LVU235
+ 1118 0648 4FF08063 		mov	r3, #67108864
+ 1119 064c 03E0     		b	.L33
+ 1120              	.L312:
+ 1121 064e 4FF48013 		mov	r3, #1048576
+ 1122 0652 00E0     		b	.L33
+ 1123              	.L145:
+ 1124 0654 1023     		movs	r3, #16
+ 1125              	.L33:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1126              		.loc 1 192 5 discriminator 200 view .LVU236
+ 1127 0656 984A     		ldr	r2, .L329+4
+ 1128 0658 9360     		str	r3, [r2, #8]
+ 1129 065a ADE6     		b	.L28
+ 1130              	.L146:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ 1131              		.loc 1 192 5 view .LVU237
+ 1132 065c 1023     		movs	r3, #16
+ 1133 065e FAE7     		b	.L33
+ 1134              	.L147:
+ 1135 0660 1023     		movs	r3, #16
+ 1136 0662 F8E7     		b	.L33
+ 1137              	.L148:
+ 1138 0664 1023     		movs	r3, #16
+ 1139 0666 F6E7     		b	.L33
+ 1140              	.L149:
+ARM GAS  /tmp/ccgvGc3k.s 			page 30
+
+
+ 1141 0668 4FF48063 		mov	r3, #1024
+ 1142 066c F3E7     		b	.L33
+ 1143              	.L150:
+ 1144 066e 4FF48063 		mov	r3, #1024
+ 1145 0672 F0E7     		b	.L33
+ 1146              	.L151:
+ 1147 0674 4FF48063 		mov	r3, #1024
+ 1148 0678 EDE7     		b	.L33
+ 1149              	.L152:
+ 1150 067a 4FF48063 		mov	r3, #1024
+ 1151 067e EAE7     		b	.L33
+ 1152              	.L153:
+ 1153 0680 4FF48013 		mov	r3, #1048576
+ 1154 0684 E7E7     		b	.L33
+ 1155              	.L154:
+ 1156 0686 4FF48013 		mov	r3, #1048576
+ 1157 068a E4E7     		b	.L33
+ 1158              	.L155:
+ 1159 068c 4FF48013 		mov	r3, #1048576
+ 1160 0690 E1E7     		b	.L33
+ 1161              	.L309:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1162              		.loc 1 193 5 view .LVU238
+ 1163 0692 4FF40022 		mov	r2, #524288
+ 1164 0696 00E0     		b	.L35
+ 1165              	.L157:
+ 1166 0698 0822     		movs	r2, #8
+ 1167              	.L35:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1168              		.loc 1 193 5 discriminator 50 view .LVU239
+ 1169 069a 884B     		ldr	r3, .L329+8
+ 1170 069c DA60     		str	r2, [r3, #12]
+ 1171              	.L36:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1172              		.loc 1 194 5 is_stmt 1 view .LVU240
+ 1173 069e 2368     		ldr	r3, [r4]
+ 1174 06a0 874A     		ldr	r2, .L329+12
+ 1175 06a2 9342     		cmp	r3, r2
+ 1176 06a4 40F2CE81 		bls	.L42
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1177              		.loc 1 194 5 is_stmt 0 discriminator 1 view .LVU241
+ 1178 06a8 A2F58962 		sub	r2, r2, #1096
+ 1179 06ac 9342     		cmp	r3, r2
+ 1180 06ae 00F06781 		beq	.L205
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1181              		.loc 1 194 5 discriminator 3 view .LVU242
+ 1182 06b2 02F58062 		add	r2, r2, #1024
+ 1183 06b6 9342     		cmp	r3, r2
+ 1184 06b8 00F0A981 		beq	.L206
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1185              		.loc 1 194 5 discriminator 5 view .LVU243
+ 1186 06bc A2F56872 		sub	r2, r2, #928
+ 1187 06c0 9342     		cmp	r3, r2
+ 1188 06c2 00F0A681 		beq	.L207
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1189              		.loc 1 194 5 discriminator 7 view .LVU244
+ 1190 06c6 02F58062 		add	r2, r2, #1024
+ARM GAS  /tmp/ccgvGc3k.s 			page 31
+
+
+ 1191 06ca 9342     		cmp	r3, r2
+ 1192 06cc 00F0A381 		beq	.L208
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1193              		.loc 1 194 5 discriminator 9 view .LVU245
+ 1194 06d0 A2F58962 		sub	r2, r2, #1096
+ 1195 06d4 9342     		cmp	r3, r2
+ 1196 06d6 00F0A081 		beq	.L209
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1197              		.loc 1 194 5 discriminator 11 view .LVU246
+ 1198 06da 02F58062 		add	r2, r2, #1024
+ 1199 06de 9342     		cmp	r3, r2
+ 1200 06e0 00F09E81 		beq	.L210
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1201              		.loc 1 194 5 discriminator 13 view .LVU247
+ 1202 06e4 A2F56872 		sub	r2, r2, #928
+ 1203 06e8 9342     		cmp	r3, r2
+ 1204 06ea 00F09C81 		beq	.L211
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1205              		.loc 1 194 5 discriminator 15 view .LVU248
+ 1206 06ee 02F58062 		add	r2, r2, #1024
+ 1207 06f2 9342     		cmp	r3, r2
+ 1208 06f4 00F09A81 		beq	.L212
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1209              		.loc 1 194 5 discriminator 17 view .LVU249
+ 1210 06f8 A2F58962 		sub	r2, r2, #1096
+ 1211 06fc 9342     		cmp	r3, r2
+ 1212 06fe 00F09881 		beq	.L213
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1213              		.loc 1 194 5 discriminator 19 view .LVU250
+ 1214 0702 02F58062 		add	r2, r2, #1024
+ 1215 0706 9342     		cmp	r3, r2
+ 1216 0708 00F09681 		beq	.L214
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1217              		.loc 1 194 5 discriminator 21 view .LVU251
+ 1218 070c A2F56872 		sub	r2, r2, #928
+ 1219 0710 9342     		cmp	r3, r2
+ 1220 0712 00F09481 		beq	.L215
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1221              		.loc 1 194 5 discriminator 23 view .LVU252
+ 1222 0716 02F58062 		add	r2, r2, #1024
+ 1223 071a 9342     		cmp	r3, r2
+ 1224 071c 00F02D81 		beq	.L313
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1225              		.loc 1 194 5 view .LVU253
+ 1226 0720 4FF08072 		mov	r2, #16777216
+ 1227 0724 2DE1     		b	.L43
+ 1228              	.L158:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1229              		.loc 1 193 5 view .LVU254
+ 1230 0726 0822     		movs	r2, #8
+ 1231 0728 B7E7     		b	.L35
+ 1232              	.L159:
+ 1233 072a 0822     		movs	r2, #8
+ 1234 072c B5E7     		b	.L35
+ 1235              	.L160:
+ 1236 072e 0822     		movs	r2, #8
+ 1237 0730 B3E7     		b	.L35
+ARM GAS  /tmp/ccgvGc3k.s 			page 32
+
+
+ 1238              	.L161:
+ 1239 0732 4FF40072 		mov	r2, #512
+ 1240 0736 B0E7     		b	.L35
+ 1241              	.L162:
+ 1242 0738 4FF40072 		mov	r2, #512
+ 1243 073c ADE7     		b	.L35
+ 1244              	.L163:
+ 1245 073e 4FF40072 		mov	r2, #512
+ 1246 0742 AAE7     		b	.L35
+ 1247              	.L164:
+ 1248 0744 4FF40072 		mov	r2, #512
+ 1249 0748 A7E7     		b	.L35
+ 1250              	.L165:
+ 1251 074a 4FF40022 		mov	r2, #524288
+ 1252 074e A4E7     		b	.L35
+ 1253              	.L166:
+ 1254 0750 4FF40022 		mov	r2, #524288
+ 1255 0754 A1E7     		b	.L35
+ 1256              	.L167:
+ 1257 0756 4FF40022 		mov	r2, #524288
+ 1258 075a 9EE7     		b	.L35
+ 1259              	.L34:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1260              		.loc 1 193 5 discriminator 2 view .LVU255
+ 1261 075c 594A     		ldr	r2, .L329+16
+ 1262 075e 9342     		cmp	r3, r2
+ 1263 0760 53D9     		bls	.L37
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1264              		.loc 1 193 5 discriminator 51 view .LVU256
+ 1265 0762 A83A     		subs	r2, r2, #168
+ 1266 0764 9342     		cmp	r3, r2
+ 1267 0766 31D0     		beq	.L169
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1268              		.loc 1 193 5 discriminator 53 view .LVU257
+ 1269 0768 02F58062 		add	r2, r2, #1024
+ 1270 076c 9342     		cmp	r3, r2
+ 1271 076e 31D0     		beq	.L170
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1272              		.loc 1 193 5 discriminator 55 view .LVU258
+ 1273 0770 A2F56872 		sub	r2, r2, #928
+ 1274 0774 9342     		cmp	r3, r2
+ 1275 0776 2FD0     		beq	.L171
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1276              		.loc 1 193 5 discriminator 57 view .LVU259
+ 1277 0778 02F58062 		add	r2, r2, #1024
+ 1278 077c 9342     		cmp	r3, r2
+ 1279 077e 2DD0     		beq	.L172
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1280              		.loc 1 193 5 discriminator 59 view .LVU260
+ 1281 0780 A2F58962 		sub	r2, r2, #1096
+ 1282 0784 9342     		cmp	r3, r2
+ 1283 0786 2BD0     		beq	.L173
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1284              		.loc 1 193 5 discriminator 61 view .LVU261
+ 1285 0788 02F58062 		add	r2, r2, #1024
+ 1286 078c 9342     		cmp	r3, r2
+ 1287 078e 2AD0     		beq	.L174
+ARM GAS  /tmp/ccgvGc3k.s 			page 33
+
+
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1288              		.loc 1 193 5 discriminator 63 view .LVU262
+ 1289 0790 A2F56872 		sub	r2, r2, #928
+ 1290 0794 9342     		cmp	r3, r2
+ 1291 0796 29D0     		beq	.L175
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1292              		.loc 1 193 5 discriminator 65 view .LVU263
+ 1293 0798 02F58062 		add	r2, r2, #1024
+ 1294 079c 9342     		cmp	r3, r2
+ 1295 079e 28D0     		beq	.L176
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1296              		.loc 1 193 5 discriminator 67 view .LVU264
+ 1297 07a0 A2F58962 		sub	r2, r2, #1096
+ 1298 07a4 9342     		cmp	r3, r2
+ 1299 07a6 27D0     		beq	.L177
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1300              		.loc 1 193 5 discriminator 69 view .LVU265
+ 1301 07a8 02F58062 		add	r2, r2, #1024
+ 1302 07ac 9342     		cmp	r3, r2
+ 1303 07ae 26D0     		beq	.L178
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1304              		.loc 1 193 5 discriminator 71 view .LVU266
+ 1305 07b0 A2F56872 		sub	r2, r2, #928
+ 1306 07b4 9342     		cmp	r3, r2
+ 1307 07b6 25D0     		beq	.L179
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1308              		.loc 1 193 5 discriminator 73 view .LVU267
+ 1309 07b8 02F58062 		add	r2, r2, #1024
+ 1310 07bc 9342     		cmp	r3, r2
+ 1311 07be 02D0     		beq	.L314
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1312              		.loc 1 193 5 view .LVU268
+ 1313 07c0 4FF00072 		mov	r2, #33554432
+ 1314 07c4 03E0     		b	.L38
+ 1315              	.L314:
+ 1316 07c6 4FF40022 		mov	r2, #524288
+ 1317 07ca 00E0     		b	.L38
+ 1318              	.L169:
+ 1319 07cc 0822     		movs	r2, #8
+ 1320              	.L38:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1321              		.loc 1 193 5 discriminator 100 view .LVU269
+ 1322 07ce 3B4B     		ldr	r3, .L329+8
+ 1323 07d0 9A60     		str	r2, [r3, #8]
+ 1324 07d2 64E7     		b	.L36
+ 1325              	.L170:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1326              		.loc 1 193 5 view .LVU270
+ 1327 07d4 0822     		movs	r2, #8
+ 1328 07d6 FAE7     		b	.L38
+ 1329              	.L171:
+ 1330 07d8 0822     		movs	r2, #8
+ 1331 07da F8E7     		b	.L38
+ 1332              	.L172:
+ 1333 07dc 0822     		movs	r2, #8
+ 1334 07de F6E7     		b	.L38
+ 1335              	.L173:
+ARM GAS  /tmp/ccgvGc3k.s 			page 34
+
+
+ 1336 07e0 4FF40072 		mov	r2, #512
+ 1337 07e4 F3E7     		b	.L38
+ 1338              	.L174:
+ 1339 07e6 4FF40072 		mov	r2, #512
+ 1340 07ea F0E7     		b	.L38
+ 1341              	.L175:
+ 1342 07ec 4FF40072 		mov	r2, #512
+ 1343 07f0 EDE7     		b	.L38
+ 1344              	.L176:
+ 1345 07f2 4FF40072 		mov	r2, #512
+ 1346 07f6 EAE7     		b	.L38
+ 1347              	.L177:
+ 1348 07f8 4FF40022 		mov	r2, #524288
+ 1349 07fc E7E7     		b	.L38
+ 1350              	.L178:
+ 1351 07fe 4FF40022 		mov	r2, #524288
+ 1352 0802 E4E7     		b	.L38
+ 1353              	.L179:
+ 1354 0804 4FF40022 		mov	r2, #524288
+ 1355 0808 E1E7     		b	.L38
+ 1356              	.L37:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1357              		.loc 1 193 5 discriminator 52 view .LVU271
+ 1358 080a 2F4A     		ldr	r2, .L329+20
+ 1359 080c 9342     		cmp	r3, r2
+ 1360 080e 60D9     		bls	.L39
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1361              		.loc 1 193 5 discriminator 102 view .LVU272
+ 1362 0810 483A     		subs	r2, r2, #72
+ 1363 0812 9342     		cmp	r3, r2
+ 1364 0814 31D0     		beq	.L181
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1365              		.loc 1 193 5 discriminator 104 view .LVU273
+ 1366 0816 02F58062 		add	r2, r2, #1024
+ 1367 081a 9342     		cmp	r3, r2
+ 1368 081c 31D0     		beq	.L182
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1369              		.loc 1 193 5 discriminator 106 view .LVU274
+ 1370 081e A2F56872 		sub	r2, r2, #928
+ 1371 0822 9342     		cmp	r3, r2
+ 1372 0824 2FD0     		beq	.L183
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1373              		.loc 1 193 5 discriminator 108 view .LVU275
+ 1374 0826 02F58062 		add	r2, r2, #1024
+ 1375 082a 9342     		cmp	r3, r2
+ 1376 082c 2DD0     		beq	.L184
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1377              		.loc 1 193 5 discriminator 110 view .LVU276
+ 1378 082e A2F58962 		sub	r2, r2, #1096
+ 1379 0832 9342     		cmp	r3, r2
+ 1380 0834 2BD0     		beq	.L185
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1381              		.loc 1 193 5 discriminator 112 view .LVU277
+ 1382 0836 02F58062 		add	r2, r2, #1024
+ 1383 083a 9342     		cmp	r3, r2
+ 1384 083c 2AD0     		beq	.L186
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ARM GAS  /tmp/ccgvGc3k.s 			page 35
+
+
+ 1385              		.loc 1 193 5 discriminator 114 view .LVU278
+ 1386 083e A2F56872 		sub	r2, r2, #928
+ 1387 0842 9342     		cmp	r3, r2
+ 1388 0844 29D0     		beq	.L187
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1389              		.loc 1 193 5 discriminator 116 view .LVU279
+ 1390 0846 02F58062 		add	r2, r2, #1024
+ 1391 084a 9342     		cmp	r3, r2
+ 1392 084c 28D0     		beq	.L188
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1393              		.loc 1 193 5 discriminator 118 view .LVU280
+ 1394 084e A2F58962 		sub	r2, r2, #1096
+ 1395 0852 9342     		cmp	r3, r2
+ 1396 0854 27D0     		beq	.L189
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1397              		.loc 1 193 5 discriminator 120 view .LVU281
+ 1398 0856 02F58062 		add	r2, r2, #1024
+ 1399 085a 9342     		cmp	r3, r2
+ 1400 085c 26D0     		beq	.L190
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1401              		.loc 1 193 5 discriminator 122 view .LVU282
+ 1402 085e A2F56872 		sub	r2, r2, #928
+ 1403 0862 9342     		cmp	r3, r2
+ 1404 0864 32D0     		beq	.L191
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1405              		.loc 1 193 5 discriminator 124 view .LVU283
+ 1406 0866 02F58062 		add	r2, r2, #1024
+ 1407 086a 9342     		cmp	r3, r2
+ 1408 086c 02D0     		beq	.L315
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1409              		.loc 1 193 5 view .LVU284
+ 1410 086e 4FF00073 		mov	r3, #33554432
+ 1411 0872 03E0     		b	.L40
+ 1412              	.L315:
+ 1413 0874 4FF40023 		mov	r3, #524288
+ 1414 0878 00E0     		b	.L40
+ 1415              	.L181:
+ 1416 087a 0823     		movs	r3, #8
+ 1417              	.L40:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1418              		.loc 1 193 5 discriminator 151 view .LVU285
+ 1419 087c 0E4A     		ldr	r2, .L329+4
+ 1420 087e D360     		str	r3, [r2, #12]
+ 1421 0880 0DE7     		b	.L36
+ 1422              	.L182:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1423              		.loc 1 193 5 view .LVU286
+ 1424 0882 0823     		movs	r3, #8
+ 1425 0884 FAE7     		b	.L40
+ 1426              	.L183:
+ 1427 0886 0823     		movs	r3, #8
+ 1428 0888 F8E7     		b	.L40
+ 1429              	.L184:
+ 1430 088a 0823     		movs	r3, #8
+ 1431 088c F6E7     		b	.L40
+ 1432              	.L185:
+ 1433 088e 4FF40073 		mov	r3, #512
+ARM GAS  /tmp/ccgvGc3k.s 			page 36
+
+
+ 1434 0892 F3E7     		b	.L40
+ 1435              	.L186:
+ 1436 0894 4FF40073 		mov	r3, #512
+ 1437 0898 F0E7     		b	.L40
+ 1438              	.L187:
+ 1439 089a 4FF40073 		mov	r3, #512
+ 1440 089e EDE7     		b	.L40
+ 1441              	.L188:
+ 1442 08a0 4FF40073 		mov	r3, #512
+ 1443 08a4 EAE7     		b	.L40
+ 1444              	.L189:
+ 1445 08a6 4FF40023 		mov	r3, #524288
+ 1446 08aa E7E7     		b	.L40
+ 1447              	.L190:
+ 1448 08ac 4FF40023 		mov	r3, #524288
+ 1449 08b0 E4E7     		b	.L40
+ 1450              	.L330:
+ 1451 08b2 00BF     		.align	2
+ 1452              	.L329:
+ 1453 08b4 10600240 		.word	1073897488
+ 1454 08b8 00600240 		.word	1073897472
+ 1455 08bc 00640240 		.word	1073898496
+ 1456 08c0 58640240 		.word	1073898584
+ 1457 08c4 B8600240 		.word	1073897656
+ 1458 08c8 58600240 		.word	1073897560
+ 1459              	.L191:
+ 1460 08cc 4FF40023 		mov	r3, #524288
+ 1461 08d0 D4E7     		b	.L40
+ 1462              	.L39:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1463              		.loc 1 193 5 discriminator 103 view .LVU287
+ 1464 08d2 B24A     		ldr	r2, .L331
+ 1465 08d4 9342     		cmp	r3, r2
+ 1466 08d6 31D0     		beq	.L193
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1467              		.loc 1 193 5 discriminator 153 view .LVU288
+ 1468 08d8 02F58062 		add	r2, r2, #1024
+ 1469 08dc 9342     		cmp	r3, r2
+ 1470 08de 31D0     		beq	.L194
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1471              		.loc 1 193 5 discriminator 155 view .LVU289
+ 1472 08e0 A2F56872 		sub	r2, r2, #928
+ 1473 08e4 9342     		cmp	r3, r2
+ 1474 08e6 2FD0     		beq	.L195
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1475              		.loc 1 193 5 discriminator 157 view .LVU290
+ 1476 08e8 02F58062 		add	r2, r2, #1024
+ 1477 08ec 9342     		cmp	r3, r2
+ 1478 08ee 2DD0     		beq	.L196
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1479              		.loc 1 193 5 discriminator 159 view .LVU291
+ 1480 08f0 A2F58962 		sub	r2, r2, #1096
+ 1481 08f4 9342     		cmp	r3, r2
+ 1482 08f6 2BD0     		beq	.L197
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1483              		.loc 1 193 5 discriminator 161 view .LVU292
+ 1484 08f8 02F58062 		add	r2, r2, #1024
+ARM GAS  /tmp/ccgvGc3k.s 			page 37
+
+
+ 1485 08fc 9342     		cmp	r3, r2
+ 1486 08fe 2AD0     		beq	.L198
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1487              		.loc 1 193 5 discriminator 163 view .LVU293
+ 1488 0900 A2F56872 		sub	r2, r2, #928
+ 1489 0904 9342     		cmp	r3, r2
+ 1490 0906 29D0     		beq	.L199
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1491              		.loc 1 193 5 discriminator 165 view .LVU294
+ 1492 0908 02F58062 		add	r2, r2, #1024
+ 1493 090c 9342     		cmp	r3, r2
+ 1494 090e 28D0     		beq	.L200
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1495              		.loc 1 193 5 discriminator 167 view .LVU295
+ 1496 0910 A2F58962 		sub	r2, r2, #1096
+ 1497 0914 9342     		cmp	r3, r2
+ 1498 0916 27D0     		beq	.L201
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1499              		.loc 1 193 5 discriminator 169 view .LVU296
+ 1500 0918 02F58062 		add	r2, r2, #1024
+ 1501 091c 9342     		cmp	r3, r2
+ 1502 091e 26D0     		beq	.L202
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1503              		.loc 1 193 5 discriminator 171 view .LVU297
+ 1504 0920 A2F56872 		sub	r2, r2, #928
+ 1505 0924 9342     		cmp	r3, r2
+ 1506 0926 25D0     		beq	.L203
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1507              		.loc 1 193 5 discriminator 173 view .LVU298
+ 1508 0928 02F58062 		add	r2, r2, #1024
+ 1509 092c 9342     		cmp	r3, r2
+ 1510 092e 02D0     		beq	.L316
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1511              		.loc 1 193 5 view .LVU299
+ 1512 0930 4FF00073 		mov	r3, #33554432
+ 1513 0934 03E0     		b	.L41
+ 1514              	.L316:
+ 1515 0936 4FF40023 		mov	r3, #524288
+ 1516 093a 00E0     		b	.L41
+ 1517              	.L193:
+ 1518 093c 0823     		movs	r3, #8
+ 1519              	.L41:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1520              		.loc 1 193 5 discriminator 200 view .LVU300
+ 1521 093e 984A     		ldr	r2, .L331+4
+ 1522 0940 9360     		str	r3, [r2, #8]
+ 1523 0942 ACE6     		b	.L36
+ 1524              	.L194:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ 1525              		.loc 1 193 5 view .LVU301
+ 1526 0944 0823     		movs	r3, #8
+ 1527 0946 FAE7     		b	.L41
+ 1528              	.L195:
+ 1529 0948 0823     		movs	r3, #8
+ 1530 094a F8E7     		b	.L41
+ 1531              	.L196:
+ 1532 094c 0823     		movs	r3, #8
+ARM GAS  /tmp/ccgvGc3k.s 			page 38
+
+
+ 1533 094e F6E7     		b	.L41
+ 1534              	.L197:
+ 1535 0950 4FF40073 		mov	r3, #512
+ 1536 0954 F3E7     		b	.L41
+ 1537              	.L198:
+ 1538 0956 4FF40073 		mov	r3, #512
+ 1539 095a F0E7     		b	.L41
+ 1540              	.L199:
+ 1541 095c 4FF40073 		mov	r3, #512
+ 1542 0960 EDE7     		b	.L41
+ 1543              	.L200:
+ 1544 0962 4FF40073 		mov	r3, #512
+ 1545 0966 EAE7     		b	.L41
+ 1546              	.L201:
+ 1547 0968 4FF40023 		mov	r3, #524288
+ 1548 096c E7E7     		b	.L41
+ 1549              	.L202:
+ 1550 096e 4FF40023 		mov	r3, #524288
+ 1551 0972 E4E7     		b	.L41
+ 1552              	.L203:
+ 1553 0974 4FF40023 		mov	r3, #524288
+ 1554 0978 E1E7     		b	.L41
+ 1555              	.L313:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1556              		.loc 1 194 5 view .LVU302
+ 1557 097a 4FF48022 		mov	r2, #262144
+ 1558 097e 00E0     		b	.L43
+ 1559              	.L205:
+ 1560 0980 0422     		movs	r2, #4
+ 1561              	.L43:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1562              		.loc 1 194 5 discriminator 50 view .LVU303
+ 1563 0982 884B     		ldr	r3, .L331+8
+ 1564 0984 DA60     		str	r2, [r3, #12]
+ 1565              	.L44:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1566              		.loc 1 195 5 is_stmt 1 view .LVU304
+ 1567 0986 2368     		ldr	r3, [r4]
+ 1568 0988 874A     		ldr	r2, .L331+12
+ 1569 098a 9342     		cmp	r3, r2
+ 1570 098c 40F2A181 		bls	.L50
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1571              		.loc 1 195 5 is_stmt 0 discriminator 1 view .LVU305
+ 1572 0990 A2F58962 		sub	r2, r2, #1096
+ 1573 0994 9342     		cmp	r3, r2
+ 1574 0996 00F06781 		beq	.L253
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1575              		.loc 1 195 5 discriminator 3 view .LVU306
+ 1576 099a 02F58062 		add	r2, r2, #1024
+ 1577 099e 9342     		cmp	r3, r2
+ 1578 09a0 00F08081 		beq	.L254
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1579              		.loc 1 195 5 discriminator 5 view .LVU307
+ 1580 09a4 A2F56872 		sub	r2, r2, #928
+ 1581 09a8 9342     		cmp	r3, r2
+ 1582 09aa 00F07D81 		beq	.L255
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ARM GAS  /tmp/ccgvGc3k.s 			page 39
+
+
+ 1583              		.loc 1 195 5 discriminator 7 view .LVU308
+ 1584 09ae 02F58062 		add	r2, r2, #1024
+ 1585 09b2 9342     		cmp	r3, r2
+ 1586 09b4 00F07A81 		beq	.L256
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1587              		.loc 1 195 5 discriminator 9 view .LVU309
+ 1588 09b8 A2F58962 		sub	r2, r2, #1096
+ 1589 09bc 9342     		cmp	r3, r2
+ 1590 09be 00F07781 		beq	.L257
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1591              		.loc 1 195 5 discriminator 11 view .LVU310
+ 1592 09c2 02F58062 		add	r2, r2, #1024
+ 1593 09c6 9342     		cmp	r3, r2
+ 1594 09c8 00F07481 		beq	.L258
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1595              		.loc 1 195 5 discriminator 13 view .LVU311
+ 1596 09cc A2F56872 		sub	r2, r2, #928
+ 1597 09d0 9342     		cmp	r3, r2
+ 1598 09d2 00F07181 		beq	.L259
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1599              		.loc 1 195 5 discriminator 15 view .LVU312
+ 1600 09d6 02F58062 		add	r2, r2, #1024
+ 1601 09da 9342     		cmp	r3, r2
+ 1602 09dc 00F06E81 		beq	.L260
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1603              		.loc 1 195 5 discriminator 17 view .LVU313
+ 1604 09e0 A2F58962 		sub	r2, r2, #1096
+ 1605 09e4 9342     		cmp	r3, r2
+ 1606 09e6 00F06B81 		beq	.L261
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1607              		.loc 1 195 5 discriminator 19 view .LVU314
+ 1608 09ea 02F58062 		add	r2, r2, #1024
+ 1609 09ee 9342     		cmp	r3, r2
+ 1610 09f0 00F06981 		beq	.L262
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1611              		.loc 1 195 5 discriminator 21 view .LVU315
+ 1612 09f4 A2F56872 		sub	r2, r2, #928
+ 1613 09f8 9342     		cmp	r3, r2
+ 1614 09fa 00F06781 		beq	.L263
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1615              		.loc 1 195 5 discriminator 23 view .LVU316
+ 1616 09fe 02F58062 		add	r2, r2, #1024
+ 1617 0a02 9342     		cmp	r3, r2
+ 1618 0a04 00F02D81 		beq	.L317
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1619              		.loc 1 195 5 view .LVU317
+ 1620 0a08 4FF48002 		mov	r2, #4194304
+ 1621 0a0c 2DE1     		b	.L51
+ 1622              	.L206:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1623              		.loc 1 194 5 view .LVU318
+ 1624 0a0e 0422     		movs	r2, #4
+ 1625 0a10 B7E7     		b	.L43
+ 1626              	.L207:
+ 1627 0a12 0422     		movs	r2, #4
+ 1628 0a14 B5E7     		b	.L43
+ 1629              	.L208:
+ARM GAS  /tmp/ccgvGc3k.s 			page 40
+
+
+ 1630 0a16 0422     		movs	r2, #4
+ 1631 0a18 B3E7     		b	.L43
+ 1632              	.L209:
+ 1633 0a1a 4FF48072 		mov	r2, #256
+ 1634 0a1e B0E7     		b	.L43
+ 1635              	.L210:
+ 1636 0a20 4FF48072 		mov	r2, #256
+ 1637 0a24 ADE7     		b	.L43
+ 1638              	.L211:
+ 1639 0a26 4FF48072 		mov	r2, #256
+ 1640 0a2a AAE7     		b	.L43
+ 1641              	.L212:
+ 1642 0a2c 4FF48072 		mov	r2, #256
+ 1643 0a30 A7E7     		b	.L43
+ 1644              	.L213:
+ 1645 0a32 4FF48022 		mov	r2, #262144
+ 1646 0a36 A4E7     		b	.L43
+ 1647              	.L214:
+ 1648 0a38 4FF48022 		mov	r2, #262144
+ 1649 0a3c A1E7     		b	.L43
+ 1650              	.L215:
+ 1651 0a3e 4FF48022 		mov	r2, #262144
+ 1652 0a42 9EE7     		b	.L43
+ 1653              	.L42:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1654              		.loc 1 194 5 discriminator 2 view .LVU319
+ 1655 0a44 594A     		ldr	r2, .L331+16
+ 1656 0a46 9342     		cmp	r3, r2
+ 1657 0a48 53D9     		bls	.L45
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1658              		.loc 1 194 5 discriminator 51 view .LVU320
+ 1659 0a4a A83A     		subs	r2, r2, #168
+ 1660 0a4c 9342     		cmp	r3, r2
+ 1661 0a4e 31D0     		beq	.L217
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1662              		.loc 1 194 5 discriminator 53 view .LVU321
+ 1663 0a50 02F58062 		add	r2, r2, #1024
+ 1664 0a54 9342     		cmp	r3, r2
+ 1665 0a56 31D0     		beq	.L218
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1666              		.loc 1 194 5 discriminator 55 view .LVU322
+ 1667 0a58 A2F56872 		sub	r2, r2, #928
+ 1668 0a5c 9342     		cmp	r3, r2
+ 1669 0a5e 2FD0     		beq	.L219
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1670              		.loc 1 194 5 discriminator 57 view .LVU323
+ 1671 0a60 02F58062 		add	r2, r2, #1024
+ 1672 0a64 9342     		cmp	r3, r2
+ 1673 0a66 2DD0     		beq	.L220
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1674              		.loc 1 194 5 discriminator 59 view .LVU324
+ 1675 0a68 A2F58962 		sub	r2, r2, #1096
+ 1676 0a6c 9342     		cmp	r3, r2
+ 1677 0a6e 2BD0     		beq	.L221
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1678              		.loc 1 194 5 discriminator 61 view .LVU325
+ 1679 0a70 02F58062 		add	r2, r2, #1024
+ARM GAS  /tmp/ccgvGc3k.s 			page 41
+
+
+ 1680 0a74 9342     		cmp	r3, r2
+ 1681 0a76 2AD0     		beq	.L222
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1682              		.loc 1 194 5 discriminator 63 view .LVU326
+ 1683 0a78 A2F56872 		sub	r2, r2, #928
+ 1684 0a7c 9342     		cmp	r3, r2
+ 1685 0a7e 29D0     		beq	.L223
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1686              		.loc 1 194 5 discriminator 65 view .LVU327
+ 1687 0a80 02F58062 		add	r2, r2, #1024
+ 1688 0a84 9342     		cmp	r3, r2
+ 1689 0a86 28D0     		beq	.L224
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1690              		.loc 1 194 5 discriminator 67 view .LVU328
+ 1691 0a88 A2F58962 		sub	r2, r2, #1096
+ 1692 0a8c 9342     		cmp	r3, r2
+ 1693 0a8e 27D0     		beq	.L225
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1694              		.loc 1 194 5 discriminator 69 view .LVU329
+ 1695 0a90 02F58062 		add	r2, r2, #1024
+ 1696 0a94 9342     		cmp	r3, r2
+ 1697 0a96 26D0     		beq	.L226
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1698              		.loc 1 194 5 discriminator 71 view .LVU330
+ 1699 0a98 A2F56872 		sub	r2, r2, #928
+ 1700 0a9c 9342     		cmp	r3, r2
+ 1701 0a9e 25D0     		beq	.L227
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1702              		.loc 1 194 5 discriminator 73 view .LVU331
+ 1703 0aa0 02F58062 		add	r2, r2, #1024
+ 1704 0aa4 9342     		cmp	r3, r2
+ 1705 0aa6 02D0     		beq	.L318
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1706              		.loc 1 194 5 view .LVU332
+ 1707 0aa8 4FF08072 		mov	r2, #16777216
+ 1708 0aac 03E0     		b	.L46
+ 1709              	.L318:
+ 1710 0aae 4FF48022 		mov	r2, #262144
+ 1711 0ab2 00E0     		b	.L46
+ 1712              	.L217:
+ 1713 0ab4 0422     		movs	r2, #4
+ 1714              	.L46:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1715              		.loc 1 194 5 discriminator 100 view .LVU333
+ 1716 0ab6 3B4B     		ldr	r3, .L331+8
+ 1717 0ab8 9A60     		str	r2, [r3, #8]
+ 1718 0aba 64E7     		b	.L44
+ 1719              	.L218:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1720              		.loc 1 194 5 view .LVU334
+ 1721 0abc 0422     		movs	r2, #4
+ 1722 0abe FAE7     		b	.L46
+ 1723              	.L219:
+ 1724 0ac0 0422     		movs	r2, #4
+ 1725 0ac2 F8E7     		b	.L46
+ 1726              	.L220:
+ 1727 0ac4 0422     		movs	r2, #4
+ARM GAS  /tmp/ccgvGc3k.s 			page 42
+
+
+ 1728 0ac6 F6E7     		b	.L46
+ 1729              	.L221:
+ 1730 0ac8 4FF48072 		mov	r2, #256
+ 1731 0acc F3E7     		b	.L46
+ 1732              	.L222:
+ 1733 0ace 4FF48072 		mov	r2, #256
+ 1734 0ad2 F0E7     		b	.L46
+ 1735              	.L223:
+ 1736 0ad4 4FF48072 		mov	r2, #256
+ 1737 0ad8 EDE7     		b	.L46
+ 1738              	.L224:
+ 1739 0ada 4FF48072 		mov	r2, #256
+ 1740 0ade EAE7     		b	.L46
+ 1741              	.L225:
+ 1742 0ae0 4FF48022 		mov	r2, #262144
+ 1743 0ae4 E7E7     		b	.L46
+ 1744              	.L226:
+ 1745 0ae6 4FF48022 		mov	r2, #262144
+ 1746 0aea E4E7     		b	.L46
+ 1747              	.L227:
+ 1748 0aec 4FF48022 		mov	r2, #262144
+ 1749 0af0 E1E7     		b	.L46
+ 1750              	.L45:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1751              		.loc 1 194 5 discriminator 52 view .LVU335
+ 1752 0af2 2F4A     		ldr	r2, .L331+20
+ 1753 0af4 9342     		cmp	r3, r2
+ 1754 0af6 60D9     		bls	.L47
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1755              		.loc 1 194 5 discriminator 102 view .LVU336
+ 1756 0af8 483A     		subs	r2, r2, #72
+ 1757 0afa 9342     		cmp	r3, r2
+ 1758 0afc 31D0     		beq	.L229
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1759              		.loc 1 194 5 discriminator 104 view .LVU337
+ 1760 0afe 02F58062 		add	r2, r2, #1024
+ 1761 0b02 9342     		cmp	r3, r2
+ 1762 0b04 31D0     		beq	.L230
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1763              		.loc 1 194 5 discriminator 106 view .LVU338
+ 1764 0b06 A2F56872 		sub	r2, r2, #928
+ 1765 0b0a 9342     		cmp	r3, r2
+ 1766 0b0c 2FD0     		beq	.L231
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1767              		.loc 1 194 5 discriminator 108 view .LVU339
+ 1768 0b0e 02F58062 		add	r2, r2, #1024
+ 1769 0b12 9342     		cmp	r3, r2
+ 1770 0b14 2DD0     		beq	.L232
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1771              		.loc 1 194 5 discriminator 110 view .LVU340
+ 1772 0b16 A2F58962 		sub	r2, r2, #1096
+ 1773 0b1a 9342     		cmp	r3, r2
+ 1774 0b1c 2BD0     		beq	.L233
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1775              		.loc 1 194 5 discriminator 112 view .LVU341
+ 1776 0b1e 02F58062 		add	r2, r2, #1024
+ 1777 0b22 9342     		cmp	r3, r2
+ARM GAS  /tmp/ccgvGc3k.s 			page 43
+
+
+ 1778 0b24 2AD0     		beq	.L234
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1779              		.loc 1 194 5 discriminator 114 view .LVU342
+ 1780 0b26 A2F56872 		sub	r2, r2, #928
+ 1781 0b2a 9342     		cmp	r3, r2
+ 1782 0b2c 29D0     		beq	.L235
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1783              		.loc 1 194 5 discriminator 116 view .LVU343
+ 1784 0b2e 02F58062 		add	r2, r2, #1024
+ 1785 0b32 9342     		cmp	r3, r2
+ 1786 0b34 28D0     		beq	.L236
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1787              		.loc 1 194 5 discriminator 118 view .LVU344
+ 1788 0b36 A2F58962 		sub	r2, r2, #1096
+ 1789 0b3a 9342     		cmp	r3, r2
+ 1790 0b3c 27D0     		beq	.L237
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1791              		.loc 1 194 5 discriminator 120 view .LVU345
+ 1792 0b3e 02F58062 		add	r2, r2, #1024
+ 1793 0b42 9342     		cmp	r3, r2
+ 1794 0b44 26D0     		beq	.L238
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1795              		.loc 1 194 5 discriminator 122 view .LVU346
+ 1796 0b46 A2F56872 		sub	r2, r2, #928
+ 1797 0b4a 9342     		cmp	r3, r2
+ 1798 0b4c 32D0     		beq	.L239
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1799              		.loc 1 194 5 discriminator 124 view .LVU347
+ 1800 0b4e 02F58062 		add	r2, r2, #1024
+ 1801 0b52 9342     		cmp	r3, r2
+ 1802 0b54 02D0     		beq	.L319
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1803              		.loc 1 194 5 view .LVU348
+ 1804 0b56 4FF08073 		mov	r3, #16777216
+ 1805 0b5a 03E0     		b	.L48
+ 1806              	.L319:
+ 1807 0b5c 4FF48023 		mov	r3, #262144
+ 1808 0b60 00E0     		b	.L48
+ 1809              	.L229:
+ 1810 0b62 0423     		movs	r3, #4
+ 1811              	.L48:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1812              		.loc 1 194 5 discriminator 151 view .LVU349
+ 1813 0b64 0E4A     		ldr	r2, .L331+4
+ 1814 0b66 D360     		str	r3, [r2, #12]
+ 1815 0b68 0DE7     		b	.L44
+ 1816              	.L230:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1817              		.loc 1 194 5 view .LVU350
+ 1818 0b6a 0423     		movs	r3, #4
+ 1819 0b6c FAE7     		b	.L48
+ 1820              	.L231:
+ 1821 0b6e 0423     		movs	r3, #4
+ 1822 0b70 F8E7     		b	.L48
+ 1823              	.L232:
+ 1824 0b72 0423     		movs	r3, #4
+ 1825 0b74 F6E7     		b	.L48
+ARM GAS  /tmp/ccgvGc3k.s 			page 44
+
+
+ 1826              	.L233:
+ 1827 0b76 4FF48073 		mov	r3, #256
+ 1828 0b7a F3E7     		b	.L48
+ 1829              	.L234:
+ 1830 0b7c 4FF48073 		mov	r3, #256
+ 1831 0b80 F0E7     		b	.L48
+ 1832              	.L235:
+ 1833 0b82 4FF48073 		mov	r3, #256
+ 1834 0b86 EDE7     		b	.L48
+ 1835              	.L236:
+ 1836 0b88 4FF48073 		mov	r3, #256
+ 1837 0b8c EAE7     		b	.L48
+ 1838              	.L237:
+ 1839 0b8e 4FF48023 		mov	r3, #262144
+ 1840 0b92 E7E7     		b	.L48
+ 1841              	.L238:
+ 1842 0b94 4FF48023 		mov	r3, #262144
+ 1843 0b98 E4E7     		b	.L48
+ 1844              	.L332:
+ 1845 0b9a 00BF     		.align	2
+ 1846              	.L331:
+ 1847 0b9c 10600240 		.word	1073897488
+ 1848 0ba0 00600240 		.word	1073897472
+ 1849 0ba4 00640240 		.word	1073898496
+ 1850 0ba8 58640240 		.word	1073898584
+ 1851 0bac B8600240 		.word	1073897656
+ 1852 0bb0 58600240 		.word	1073897560
+ 1853              	.L239:
+ 1854 0bb4 4FF48023 		mov	r3, #262144
+ 1855 0bb8 D4E7     		b	.L48
+ 1856              	.L47:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1857              		.loc 1 194 5 discriminator 103 view .LVU351
+ 1858 0bba 994A     		ldr	r2, .L333
+ 1859 0bbc 9342     		cmp	r3, r2
+ 1860 0bbe 31D0     		beq	.L241
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1861              		.loc 1 194 5 discriminator 153 view .LVU352
+ 1862 0bc0 02F58062 		add	r2, r2, #1024
+ 1863 0bc4 9342     		cmp	r3, r2
+ 1864 0bc6 31D0     		beq	.L242
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1865              		.loc 1 194 5 discriminator 155 view .LVU353
+ 1866 0bc8 A2F56872 		sub	r2, r2, #928
+ 1867 0bcc 9342     		cmp	r3, r2
+ 1868 0bce 2FD0     		beq	.L243
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1869              		.loc 1 194 5 discriminator 157 view .LVU354
+ 1870 0bd0 02F58062 		add	r2, r2, #1024
+ 1871 0bd4 9342     		cmp	r3, r2
+ 1872 0bd6 2DD0     		beq	.L244
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1873              		.loc 1 194 5 discriminator 159 view .LVU355
+ 1874 0bd8 A2F58962 		sub	r2, r2, #1096
+ 1875 0bdc 9342     		cmp	r3, r2
+ 1876 0bde 2BD0     		beq	.L245
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ARM GAS  /tmp/ccgvGc3k.s 			page 45
+
+
+ 1877              		.loc 1 194 5 discriminator 161 view .LVU356
+ 1878 0be0 02F58062 		add	r2, r2, #1024
+ 1879 0be4 9342     		cmp	r3, r2
+ 1880 0be6 2AD0     		beq	.L246
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1881              		.loc 1 194 5 discriminator 163 view .LVU357
+ 1882 0be8 A2F56872 		sub	r2, r2, #928
+ 1883 0bec 9342     		cmp	r3, r2
+ 1884 0bee 29D0     		beq	.L247
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1885              		.loc 1 194 5 discriminator 165 view .LVU358
+ 1886 0bf0 02F58062 		add	r2, r2, #1024
+ 1887 0bf4 9342     		cmp	r3, r2
+ 1888 0bf6 28D0     		beq	.L248
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1889              		.loc 1 194 5 discriminator 167 view .LVU359
+ 1890 0bf8 A2F58962 		sub	r2, r2, #1096
+ 1891 0bfc 9342     		cmp	r3, r2
+ 1892 0bfe 27D0     		beq	.L249
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1893              		.loc 1 194 5 discriminator 169 view .LVU360
+ 1894 0c00 02F58062 		add	r2, r2, #1024
+ 1895 0c04 9342     		cmp	r3, r2
+ 1896 0c06 26D0     		beq	.L250
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1897              		.loc 1 194 5 discriminator 171 view .LVU361
+ 1898 0c08 A2F56872 		sub	r2, r2, #928
+ 1899 0c0c 9342     		cmp	r3, r2
+ 1900 0c0e 25D0     		beq	.L251
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1901              		.loc 1 194 5 discriminator 173 view .LVU362
+ 1902 0c10 02F58062 		add	r2, r2, #1024
+ 1903 0c14 9342     		cmp	r3, r2
+ 1904 0c16 02D0     		beq	.L320
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1905              		.loc 1 194 5 view .LVU363
+ 1906 0c18 4FF08073 		mov	r3, #16777216
+ 1907 0c1c 03E0     		b	.L49
+ 1908              	.L320:
+ 1909 0c1e 4FF48023 		mov	r3, #262144
+ 1910 0c22 00E0     		b	.L49
+ 1911              	.L241:
+ 1912 0c24 0423     		movs	r3, #4
+ 1913              	.L49:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1914              		.loc 1 194 5 discriminator 200 view .LVU364
+ 1915 0c26 7F4A     		ldr	r2, .L333+4
+ 1916 0c28 9360     		str	r3, [r2, #8]
+ 1917 0c2a ACE6     		b	.L44
+ 1918              	.L242:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ 1919              		.loc 1 194 5 view .LVU365
+ 1920 0c2c 0423     		movs	r3, #4
+ 1921 0c2e FAE7     		b	.L49
+ 1922              	.L243:
+ 1923 0c30 0423     		movs	r3, #4
+ 1924 0c32 F8E7     		b	.L49
+ARM GAS  /tmp/ccgvGc3k.s 			page 46
+
+
+ 1925              	.L244:
+ 1926 0c34 0423     		movs	r3, #4
+ 1927 0c36 F6E7     		b	.L49
+ 1928              	.L245:
+ 1929 0c38 4FF48073 		mov	r3, #256
+ 1930 0c3c F3E7     		b	.L49
+ 1931              	.L246:
+ 1932 0c3e 4FF48073 		mov	r3, #256
+ 1933 0c42 F0E7     		b	.L49
+ 1934              	.L247:
+ 1935 0c44 4FF48073 		mov	r3, #256
+ 1936 0c48 EDE7     		b	.L49
+ 1937              	.L248:
+ 1938 0c4a 4FF48073 		mov	r3, #256
+ 1939 0c4e EAE7     		b	.L49
+ 1940              	.L249:
+ 1941 0c50 4FF48023 		mov	r3, #262144
+ 1942 0c54 E7E7     		b	.L49
+ 1943              	.L250:
+ 1944 0c56 4FF48023 		mov	r3, #262144
+ 1945 0c5a E4E7     		b	.L49
+ 1946              	.L251:
+ 1947 0c5c 4FF48023 		mov	r3, #262144
+ 1948 0c60 E1E7     		b	.L49
+ 1949              	.L317:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1950              		.loc 1 195 5 view .LVU366
+ 1951 0c62 4FF48032 		mov	r2, #65536
+ 1952 0c66 00E0     		b	.L51
+ 1953              	.L253:
+ 1954 0c68 0122     		movs	r2, #1
+ 1955              	.L51:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1956              		.loc 1 195 5 discriminator 50 view .LVU367
+ 1957 0c6a 6F4B     		ldr	r3, .L333+8
+ 1958 0c6c DA60     		str	r2, [r3, #12]
+ 1959              	.L52:
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->FCR |= DMA_IT_FE;
+ 1960              		.loc 1 198 5 is_stmt 1 view .LVU368
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->FCR |= DMA_IT_FE;
+ 1961              		.loc 1 198 9 is_stmt 0 view .LVU369
+ 1962 0c6e 2268     		ldr	r2, [r4]
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     hdma->Instance->FCR |= DMA_IT_FE;
+ 1963              		.loc 1 198 25 view .LVU370
+ 1964 0c70 1368     		ldr	r3, [r2]
+ 1965 0c72 43F01603 		orr	r3, r3, #22
+ 1966 0c76 1360     		str	r3, [r2]
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1967              		.loc 1 199 5 is_stmt 1 view .LVU371
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1968              		.loc 1 199 9 is_stmt 0 view .LVU372
+ 1969 0c78 2268     		ldr	r2, [r4]
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1970              		.loc 1 199 25 view .LVU373
+ 1971 0c7a 5369     		ldr	r3, [r2, #20]
+ 1972 0c7c 43F08003 		orr	r3, r3, #128
+ 1973 0c80 5361     		str	r3, [r2, #20]
+ARM GAS  /tmp/ccgvGc3k.s 			page 47
+
+
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     {
+ 1974              		.loc 1 201 5 is_stmt 1 view .LVU374
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     {
+ 1975              		.loc 1 201 13 is_stmt 0 view .LVU375
+ 1976 0c82 236C     		ldr	r3, [r4, #64]
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     {
+ 1977              		.loc 1 201 7 view .LVU376
+ 1978 0c84 002B     		cmp	r3, #0
+ 1979 0c86 00F02581 		beq	.L321
+ 1980              	.L58:
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     }
+ 1981              		.loc 1 203 7 is_stmt 1 view .LVU377
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     }
+ 1982              		.loc 1 203 11 is_stmt 0 view .LVU378
+ 1983 0c8a 2268     		ldr	r2, [r4]
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     }
+ 1984              		.loc 1 203 27 view .LVU379
+ 1985 0c8c 1368     		ldr	r3, [r2]
+ 1986 0c8e 43F00803 		orr	r3, r3, #8
+ 1987 0c92 1360     		str	r3, [r2]
+ 1988              	.L59:
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 1989              		.loc 1 207 5 is_stmt 1 view .LVU380
+ 1990 0c94 2268     		ldr	r2, [r4]
+ 1991 0c96 1368     		ldr	r3, [r2]
+ 1992 0c98 43F00103 		orr	r3, r3, #1
+ 1993 0c9c 1360     		str	r3, [r2]
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 1994              		.loc 1 158 21 is_stmt 0 view .LVU381
+ 1995 0c9e 0020     		movs	r0, #0
+ 1996 0ca0 FFF7C4B9 		b	.L16
+ 1997              	.L254:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 1998              		.loc 1 195 5 view .LVU382
+ 1999 0ca4 0122     		movs	r2, #1
+ 2000 0ca6 E0E7     		b	.L51
+ 2001              	.L255:
+ 2002 0ca8 0122     		movs	r2, #1
+ 2003 0caa DEE7     		b	.L51
+ 2004              	.L256:
+ 2005 0cac 0122     		movs	r2, #1
+ 2006 0cae DCE7     		b	.L51
+ 2007              	.L257:
+ 2008 0cb0 4022     		movs	r2, #64
+ 2009 0cb2 DAE7     		b	.L51
+ 2010              	.L258:
+ 2011 0cb4 4022     		movs	r2, #64
+ 2012 0cb6 D8E7     		b	.L51
+ 2013              	.L259:
+ 2014 0cb8 4022     		movs	r2, #64
+ 2015 0cba D6E7     		b	.L51
+ 2016              	.L260:
+ 2017 0cbc 4022     		movs	r2, #64
+ 2018 0cbe D4E7     		b	.L51
+ 2019              	.L261:
+ 2020 0cc0 4FF48032 		mov	r2, #65536
+ 2021 0cc4 D1E7     		b	.L51
+ARM GAS  /tmp/ccgvGc3k.s 			page 48
+
+
+ 2022              	.L262:
+ 2023 0cc6 4FF48032 		mov	r2, #65536
+ 2024 0cca CEE7     		b	.L51
+ 2025              	.L263:
+ 2026 0ccc 4FF48032 		mov	r2, #65536
+ 2027 0cd0 CBE7     		b	.L51
+ 2028              	.L50:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2029              		.loc 1 195 5 discriminator 2 view .LVU383
+ 2030 0cd2 564A     		ldr	r2, .L333+12
+ 2031 0cd4 9342     		cmp	r3, r2
+ 2032 0cd6 4FD9     		bls	.L53
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2033              		.loc 1 195 5 discriminator 51 view .LVU384
+ 2034 0cd8 A83A     		subs	r2, r2, #168
+ 2035 0cda 9342     		cmp	r3, r2
+ 2036 0cdc 31D0     		beq	.L265
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2037              		.loc 1 195 5 discriminator 53 view .LVU385
+ 2038 0cde 02F58062 		add	r2, r2, #1024
+ 2039 0ce2 9342     		cmp	r3, r2
+ 2040 0ce4 31D0     		beq	.L266
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2041              		.loc 1 195 5 discriminator 55 view .LVU386
+ 2042 0ce6 A2F56872 		sub	r2, r2, #928
+ 2043 0cea 9342     		cmp	r3, r2
+ 2044 0cec 2FD0     		beq	.L267
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2045              		.loc 1 195 5 discriminator 57 view .LVU387
+ 2046 0cee 02F58062 		add	r2, r2, #1024
+ 2047 0cf2 9342     		cmp	r3, r2
+ 2048 0cf4 2DD0     		beq	.L268
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2049              		.loc 1 195 5 discriminator 59 view .LVU388
+ 2050 0cf6 A2F58962 		sub	r2, r2, #1096
+ 2051 0cfa 9342     		cmp	r3, r2
+ 2052 0cfc 2BD0     		beq	.L269
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2053              		.loc 1 195 5 discriminator 61 view .LVU389
+ 2054 0cfe 02F58062 		add	r2, r2, #1024
+ 2055 0d02 9342     		cmp	r3, r2
+ 2056 0d04 29D0     		beq	.L270
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2057              		.loc 1 195 5 discriminator 63 view .LVU390
+ 2058 0d06 A2F56872 		sub	r2, r2, #928
+ 2059 0d0a 9342     		cmp	r3, r2
+ 2060 0d0c 27D0     		beq	.L271
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2061              		.loc 1 195 5 discriminator 65 view .LVU391
+ 2062 0d0e 02F58062 		add	r2, r2, #1024
+ 2063 0d12 9342     		cmp	r3, r2
+ 2064 0d14 25D0     		beq	.L272
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2065              		.loc 1 195 5 discriminator 67 view .LVU392
+ 2066 0d16 A2F58962 		sub	r2, r2, #1096
+ 2067 0d1a 9342     		cmp	r3, r2
+ 2068 0d1c 23D0     		beq	.L273
+ARM GAS  /tmp/ccgvGc3k.s 			page 49
+
+
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2069              		.loc 1 195 5 discriminator 69 view .LVU393
+ 2070 0d1e 02F58062 		add	r2, r2, #1024
+ 2071 0d22 9342     		cmp	r3, r2
+ 2072 0d24 22D0     		beq	.L274
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2073              		.loc 1 195 5 discriminator 71 view .LVU394
+ 2074 0d26 A2F56872 		sub	r2, r2, #928
+ 2075 0d2a 9342     		cmp	r3, r2
+ 2076 0d2c 21D0     		beq	.L275
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2077              		.loc 1 195 5 discriminator 73 view .LVU395
+ 2078 0d2e 02F58062 		add	r2, r2, #1024
+ 2079 0d32 9342     		cmp	r3, r2
+ 2080 0d34 02D0     		beq	.L322
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2081              		.loc 1 195 5 view .LVU396
+ 2082 0d36 4FF48002 		mov	r2, #4194304
+ 2083 0d3a 03E0     		b	.L54
+ 2084              	.L322:
+ 2085 0d3c 4FF48032 		mov	r2, #65536
+ 2086 0d40 00E0     		b	.L54
+ 2087              	.L265:
+ 2088 0d42 0122     		movs	r2, #1
+ 2089              	.L54:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2090              		.loc 1 195 5 discriminator 100 view .LVU397
+ 2091 0d44 384B     		ldr	r3, .L333+8
+ 2092 0d46 9A60     		str	r2, [r3, #8]
+ 2093 0d48 91E7     		b	.L52
+ 2094              	.L266:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2095              		.loc 1 195 5 view .LVU398
+ 2096 0d4a 0122     		movs	r2, #1
+ 2097 0d4c FAE7     		b	.L54
+ 2098              	.L267:
+ 2099 0d4e 0122     		movs	r2, #1
+ 2100 0d50 F8E7     		b	.L54
+ 2101              	.L268:
+ 2102 0d52 0122     		movs	r2, #1
+ 2103 0d54 F6E7     		b	.L54
+ 2104              	.L269:
+ 2105 0d56 4022     		movs	r2, #64
+ 2106 0d58 F4E7     		b	.L54
+ 2107              	.L270:
+ 2108 0d5a 4022     		movs	r2, #64
+ 2109 0d5c F2E7     		b	.L54
+ 2110              	.L271:
+ 2111 0d5e 4022     		movs	r2, #64
+ 2112 0d60 F0E7     		b	.L54
+ 2113              	.L272:
+ 2114 0d62 4022     		movs	r2, #64
+ 2115 0d64 EEE7     		b	.L54
+ 2116              	.L273:
+ 2117 0d66 4FF48032 		mov	r2, #65536
+ 2118 0d6a EBE7     		b	.L54
+ 2119              	.L274:
+ARM GAS  /tmp/ccgvGc3k.s 			page 50
+
+
+ 2120 0d6c 4FF48032 		mov	r2, #65536
+ 2121 0d70 E8E7     		b	.L54
+ 2122              	.L275:
+ 2123 0d72 4FF48032 		mov	r2, #65536
+ 2124 0d76 E5E7     		b	.L54
+ 2125              	.L53:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2126              		.loc 1 195 5 discriminator 52 view .LVU399
+ 2127 0d78 2D4A     		ldr	r2, .L333+16
+ 2128 0d7a 9342     		cmp	r3, r2
+ 2129 0d7c 5AD9     		bls	.L55
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2130              		.loc 1 195 5 discriminator 102 view .LVU400
+ 2131 0d7e 483A     		subs	r2, r2, #72
+ 2132 0d80 9342     		cmp	r3, r2
+ 2133 0d82 31D0     		beq	.L277
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2134              		.loc 1 195 5 discriminator 104 view .LVU401
+ 2135 0d84 02F58062 		add	r2, r2, #1024
+ 2136 0d88 9342     		cmp	r3, r2
+ 2137 0d8a 31D0     		beq	.L278
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2138              		.loc 1 195 5 discriminator 106 view .LVU402
+ 2139 0d8c A2F56872 		sub	r2, r2, #928
+ 2140 0d90 9342     		cmp	r3, r2
+ 2141 0d92 2FD0     		beq	.L279
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2142              		.loc 1 195 5 discriminator 108 view .LVU403
+ 2143 0d94 02F58062 		add	r2, r2, #1024
+ 2144 0d98 9342     		cmp	r3, r2
+ 2145 0d9a 2DD0     		beq	.L280
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2146              		.loc 1 195 5 discriminator 110 view .LVU404
+ 2147 0d9c A2F58962 		sub	r2, r2, #1096
+ 2148 0da0 9342     		cmp	r3, r2
+ 2149 0da2 2BD0     		beq	.L281
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2150              		.loc 1 195 5 discriminator 112 view .LVU405
+ 2151 0da4 02F58062 		add	r2, r2, #1024
+ 2152 0da8 9342     		cmp	r3, r2
+ 2153 0daa 29D0     		beq	.L282
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2154              		.loc 1 195 5 discriminator 114 view .LVU406
+ 2155 0dac A2F56872 		sub	r2, r2, #928
+ 2156 0db0 9342     		cmp	r3, r2
+ 2157 0db2 27D0     		beq	.L283
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2158              		.loc 1 195 5 discriminator 116 view .LVU407
+ 2159 0db4 02F58062 		add	r2, r2, #1024
+ 2160 0db8 9342     		cmp	r3, r2
+ 2161 0dba 25D0     		beq	.L284
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2162              		.loc 1 195 5 discriminator 118 view .LVU408
+ 2163 0dbc A2F58962 		sub	r2, r2, #1096
+ 2164 0dc0 9342     		cmp	r3, r2
+ 2165 0dc2 23D0     		beq	.L285
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ARM GAS  /tmp/ccgvGc3k.s 			page 51
+
+
+ 2166              		.loc 1 195 5 discriminator 120 view .LVU409
+ 2167 0dc4 02F58062 		add	r2, r2, #1024
+ 2168 0dc8 9342     		cmp	r3, r2
+ 2169 0dca 22D0     		beq	.L286
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2170              		.loc 1 195 5 discriminator 122 view .LVU410
+ 2171 0dcc A2F56872 		sub	r2, r2, #928
+ 2172 0dd0 9342     		cmp	r3, r2
+ 2173 0dd2 21D0     		beq	.L287
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2174              		.loc 1 195 5 discriminator 124 view .LVU411
+ 2175 0dd4 02F58062 		add	r2, r2, #1024
+ 2176 0dd8 9342     		cmp	r3, r2
+ 2177 0dda 02D0     		beq	.L323
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2178              		.loc 1 195 5 view .LVU412
+ 2179 0ddc 4FF48003 		mov	r3, #4194304
+ 2180 0de0 03E0     		b	.L56
+ 2181              	.L323:
+ 2182 0de2 4FF48033 		mov	r3, #65536
+ 2183 0de6 00E0     		b	.L56
+ 2184              	.L277:
+ 2185 0de8 0123     		movs	r3, #1
+ 2186              	.L56:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2187              		.loc 1 195 5 discriminator 151 view .LVU413
+ 2188 0dea 0E4A     		ldr	r2, .L333+4
+ 2189 0dec D360     		str	r3, [r2, #12]
+ 2190 0dee 3EE7     		b	.L52
+ 2191              	.L278:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2192              		.loc 1 195 5 view .LVU414
+ 2193 0df0 0123     		movs	r3, #1
+ 2194 0df2 FAE7     		b	.L56
+ 2195              	.L279:
+ 2196 0df4 0123     		movs	r3, #1
+ 2197 0df6 F8E7     		b	.L56
+ 2198              	.L280:
+ 2199 0df8 0123     		movs	r3, #1
+ 2200 0dfa F6E7     		b	.L56
+ 2201              	.L281:
+ 2202 0dfc 4023     		movs	r3, #64
+ 2203 0dfe F4E7     		b	.L56
+ 2204              	.L282:
+ 2205 0e00 4023     		movs	r3, #64
+ 2206 0e02 F2E7     		b	.L56
+ 2207              	.L283:
+ 2208 0e04 4023     		movs	r3, #64
+ 2209 0e06 F0E7     		b	.L56
+ 2210              	.L284:
+ 2211 0e08 4023     		movs	r3, #64
+ 2212 0e0a EEE7     		b	.L56
+ 2213              	.L285:
+ 2214 0e0c 4FF48033 		mov	r3, #65536
+ 2215 0e10 EBE7     		b	.L56
+ 2216              	.L286:
+ 2217 0e12 4FF48033 		mov	r3, #65536
+ARM GAS  /tmp/ccgvGc3k.s 			page 52
+
+
+ 2218 0e16 E8E7     		b	.L56
+ 2219              	.L287:
+ 2220 0e18 4FF48033 		mov	r3, #65536
+ 2221 0e1c E5E7     		b	.L56
+ 2222              	.L334:
+ 2223 0e1e 00BF     		.align	2
+ 2224              	.L333:
+ 2225 0e20 10600240 		.word	1073897488
+ 2226 0e24 00600240 		.word	1073897472
+ 2227 0e28 00640240 		.word	1073898496
+ 2228 0e2c B8600240 		.word	1073897656
+ 2229 0e30 58600240 		.word	1073897560
+ 2230              	.L55:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2231              		.loc 1 195 5 discriminator 103 view .LVU415
+ 2232 0e34 2B4A     		ldr	r2, .L335
+ 2233 0e36 9342     		cmp	r3, r2
+ 2234 0e38 31D0     		beq	.L289
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2235              		.loc 1 195 5 discriminator 153 view .LVU416
+ 2236 0e3a 02F58062 		add	r2, r2, #1024
+ 2237 0e3e 9342     		cmp	r3, r2
+ 2238 0e40 31D0     		beq	.L290
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2239              		.loc 1 195 5 discriminator 155 view .LVU417
+ 2240 0e42 A2F56872 		sub	r2, r2, #928
+ 2241 0e46 9342     		cmp	r3, r2
+ 2242 0e48 2FD0     		beq	.L291
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2243              		.loc 1 195 5 discriminator 157 view .LVU418
+ 2244 0e4a 02F58062 		add	r2, r2, #1024
+ 2245 0e4e 9342     		cmp	r3, r2
+ 2246 0e50 2DD0     		beq	.L292
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2247              		.loc 1 195 5 discriminator 159 view .LVU419
+ 2248 0e52 A2F58962 		sub	r2, r2, #1096
+ 2249 0e56 9342     		cmp	r3, r2
+ 2250 0e58 2BD0     		beq	.L293
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2251              		.loc 1 195 5 discriminator 161 view .LVU420
+ 2252 0e5a 02F58062 		add	r2, r2, #1024
+ 2253 0e5e 9342     		cmp	r3, r2
+ 2254 0e60 29D0     		beq	.L294
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2255              		.loc 1 195 5 discriminator 163 view .LVU421
+ 2256 0e62 A2F56872 		sub	r2, r2, #928
+ 2257 0e66 9342     		cmp	r3, r2
+ 2258 0e68 27D0     		beq	.L295
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2259              		.loc 1 195 5 discriminator 165 view .LVU422
+ 2260 0e6a 02F58062 		add	r2, r2, #1024
+ 2261 0e6e 9342     		cmp	r3, r2
+ 2262 0e70 25D0     		beq	.L296
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2263              		.loc 1 195 5 discriminator 167 view .LVU423
+ 2264 0e72 A2F58962 		sub	r2, r2, #1096
+ 2265 0e76 9342     		cmp	r3, r2
+ARM GAS  /tmp/ccgvGc3k.s 			page 53
+
+
+ 2266 0e78 23D0     		beq	.L297
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2267              		.loc 1 195 5 discriminator 169 view .LVU424
+ 2268 0e7a 02F58062 		add	r2, r2, #1024
+ 2269 0e7e 9342     		cmp	r3, r2
+ 2270 0e80 22D0     		beq	.L298
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2271              		.loc 1 195 5 discriminator 171 view .LVU425
+ 2272 0e82 A2F56872 		sub	r2, r2, #928
+ 2273 0e86 9342     		cmp	r3, r2
+ 2274 0e88 21D0     		beq	.L299
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2275              		.loc 1 195 5 discriminator 173 view .LVU426
+ 2276 0e8a 02F58062 		add	r2, r2, #1024
+ 2277 0e8e 9342     		cmp	r3, r2
+ 2278 0e90 02D0     		beq	.L324
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2279              		.loc 1 195 5 view .LVU427
+ 2280 0e92 4FF48003 		mov	r3, #4194304
+ 2281 0e96 03E0     		b	.L57
+ 2282              	.L324:
+ 2283 0e98 4FF48033 		mov	r3, #65536
+ 2284 0e9c 00E0     		b	.L57
+ 2285              	.L289:
+ 2286 0e9e 0123     		movs	r3, #1
+ 2287              	.L57:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2288              		.loc 1 195 5 discriminator 200 view .LVU428
+ 2289 0ea0 114A     		ldr	r2, .L335+4
+ 2290 0ea2 9360     		str	r3, [r2, #8]
+ 2291 0ea4 E3E6     		b	.L52
+ 2292              	.L290:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     
+ 2293              		.loc 1 195 5 view .LVU429
+ 2294 0ea6 0123     		movs	r3, #1
+ 2295 0ea8 FAE7     		b	.L57
+ 2296              	.L291:
+ 2297 0eaa 0123     		movs	r3, #1
+ 2298 0eac F8E7     		b	.L57
+ 2299              	.L292:
+ 2300 0eae 0123     		movs	r3, #1
+ 2301 0eb0 F6E7     		b	.L57
+ 2302              	.L293:
+ 2303 0eb2 4023     		movs	r3, #64
+ 2304 0eb4 F4E7     		b	.L57
+ 2305              	.L294:
+ 2306 0eb6 4023     		movs	r3, #64
+ 2307 0eb8 F2E7     		b	.L57
+ 2308              	.L295:
+ 2309 0eba 4023     		movs	r3, #64
+ 2310 0ebc F0E7     		b	.L57
+ 2311              	.L296:
+ 2312 0ebe 4023     		movs	r3, #64
+ 2313 0ec0 EEE7     		b	.L57
+ 2314              	.L297:
+ 2315 0ec2 4FF48033 		mov	r3, #65536
+ 2316 0ec6 EBE7     		b	.L57
+ARM GAS  /tmp/ccgvGc3k.s 			page 54
+
+
+ 2317              	.L298:
+ 2318 0ec8 4FF48033 		mov	r3, #65536
+ 2319 0ecc E8E7     		b	.L57
+ 2320              	.L299:
+ 2321 0ece 4FF48033 		mov	r3, #65536
+ 2322 0ed2 E5E7     		b	.L57
+ 2323              	.L321:
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     {
+ 2324              		.loc 1 201 53 discriminator 1 view .LVU430
+ 2325 0ed4 A36C     		ldr	r3, [r4, #72]
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****     {
+ 2326              		.loc 1 201 45 discriminator 1 view .LVU431
+ 2327 0ed6 002B     		cmp	r3, #0
+ 2328 0ed8 7FF4D7AE 		bne	.L58
+ 2329 0edc DAE6     		b	.L59
+ 2330              	.LVL38:
+ 2331              	.L60:
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   
+ 2332              		.loc 1 171 3 view .LVU432
+ 2333 0ede 0220     		movs	r0, #2
+ 2334 0ee0 FFF7A4B8 		b	.L16
+ 2335              	.L336:
+ 2336              		.align	2
+ 2337              	.L335:
+ 2338 0ee4 10600240 		.word	1073897488
+ 2339 0ee8 00600240 		.word	1073897472
+ 2340              		.cfi_endproc
+ 2341              	.LFE142:
+ 2343              		.section	.text.HAL_DMAEx_ChangeMemory,"ax",%progbits
+ 2344              		.align	1
+ 2345              		.global	HAL_DMAEx_ChangeMemory
+ 2346              		.syntax unified
+ 2347              		.thumb
+ 2348              		.thumb_func
+ 2349              		.fpu fpv5-d16
+ 2351              	HAL_DMAEx_ChangeMemory:
+ 2352              	.LVL39:
+ 2353              	.LFB143:
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   if(memory == MEMORY0)
+ 2354              		.loc 1 235 1 is_stmt 1 view -0
+ 2355              		.cfi_startproc
+ 2356              		@ args = 0, pretend = 0, frame = 0
+ 2357              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2358              		@ link register save eliminated.
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 2359              		.loc 1 236 3 view .LVU434
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   {
+ 2360              		.loc 1 236 5 is_stmt 0 view .LVU435
+ 2361 0000 1AB9     		cbnz	r2, .L338
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 2362              		.loc 1 239 5 is_stmt 1 view .LVU436
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 2363              		.loc 1 239 9 is_stmt 0 view .LVU437
+ 2364 0002 0368     		ldr	r3, [r0]
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 2365              		.loc 1 239 26 view .LVU438
+ 2366 0004 D960     		str	r1, [r3, #12]
+ARM GAS  /tmp/ccgvGc3k.s 			page 55
+
+
+ 2367              	.L339:
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** }
+ 2368              		.loc 1 247 3 is_stmt 1 view .LVU439
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+ 2369              		.loc 1 248 1 is_stmt 0 view .LVU440
+ 2370 0006 0020     		movs	r0, #0
+ 2371              	.LVL40:
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** 
+ 2372              		.loc 1 248 1 view .LVU441
+ 2373 0008 7047     		bx	lr
+ 2374              	.LVL41:
+ 2375              	.L338:
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 2376              		.loc 1 244 5 is_stmt 1 view .LVU442
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 2377              		.loc 1 244 9 is_stmt 0 view .LVU443
+ 2378 000a 0368     		ldr	r3, [r0]
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c ****   }
+ 2379              		.loc 1 244 26 view .LVU444
+ 2380 000c 1961     		str	r1, [r3, #16]
+ 2381 000e FAE7     		b	.L339
+ 2382              		.cfi_endproc
+ 2383              	.LFE143:
+ 2385              		.text
+ 2386              	.Letext0:
+ 2387              		.file 2 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 2388              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 2389              		.file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 2390              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 2391              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h"
+ARM GAS  /tmp/ccgvGc3k.s 			page 56
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_dma_ex.c
+     /tmp/ccgvGc3k.s:17     .text.DMA_MultiBufferSetConfig:0000000000000000 $t
+     /tmp/ccgvGc3k.s:24     .text.DMA_MultiBufferSetConfig:0000000000000000 DMA_MultiBufferSetConfig
+     /tmp/ccgvGc3k.s:88     .text.HAL_DMAEx_MultiBufferStart:0000000000000000 $t
+     /tmp/ccgvGc3k.s:95     .text.HAL_DMAEx_MultiBufferStart:0000000000000000 HAL_DMAEx_MultiBufferStart
+     /tmp/ccgvGc3k.s:200    .text.HAL_DMAEx_MultiBufferStart_IT:0000000000000000 $t
+     /tmp/ccgvGc3k.s:207    .text.HAL_DMAEx_MultiBufferStart_IT:0000000000000000 HAL_DMAEx_MultiBufferStart_IT
+     /tmp/ccgvGc3k.s:665    .text.HAL_DMAEx_MultiBufferStart_IT:00000000000002f0 $d
+     /tmp/ccgvGc3k.s:672    .text.HAL_DMAEx_MultiBufferStart_IT:0000000000000304 $t
+     /tmp/ccgvGc3k.s:1059   .text.HAL_DMAEx_MultiBufferStart_IT:00000000000005cc $d
+     /tmp/ccgvGc3k.s:1066   .text.HAL_DMAEx_MultiBufferStart_IT:00000000000005e4 $t
+     /tmp/ccgvGc3k.s:1453   .text.HAL_DMAEx_MultiBufferStart_IT:00000000000008b4 $d
+     /tmp/ccgvGc3k.s:1460   .text.HAL_DMAEx_MultiBufferStart_IT:00000000000008cc $t
+     /tmp/ccgvGc3k.s:1847   .text.HAL_DMAEx_MultiBufferStart_IT:0000000000000b9c $d
+     /tmp/ccgvGc3k.s:1854   .text.HAL_DMAEx_MultiBufferStart_IT:0000000000000bb4 $t
+     /tmp/ccgvGc3k.s:2225   .text.HAL_DMAEx_MultiBufferStart_IT:0000000000000e20 $d
+     /tmp/ccgvGc3k.s:2232   .text.HAL_DMAEx_MultiBufferStart_IT:0000000000000e34 $t
+     /tmp/ccgvGc3k.s:2338   .text.HAL_DMAEx_MultiBufferStart_IT:0000000000000ee4 $d
+     /tmp/ccgvGc3k.s:2344   .text.HAL_DMAEx_ChangeMemory:0000000000000000 $t
+     /tmp/ccgvGc3k.s:2351   .text.HAL_DMAEx_ChangeMemory:0000000000000000 HAL_DMAEx_ChangeMemory
+
+NO UNDEFINED SYMBOLS
diff --git a/build/stm32f7xx_hal_dma_ex.o b/build/stm32f7xx_hal_dma_ex.o
new file mode 100644
index 0000000..da8112d
Binary files /dev/null and b/build/stm32f7xx_hal_dma_ex.o differ
diff --git a/build/stm32f7xx_hal_exti.d b/build/stm32f7xx_hal_exti.d
new file mode 100644
index 0000000..d425bfb
--- /dev/null
+++ b/build/stm32f7xx_hal_exti.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_exti.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_exti.lst b/build/stm32f7xx_hal_exti.lst
new file mode 100644
index 0000000..18bad11
--- /dev/null
+++ b/build/stm32f7xx_hal_exti.lst
@@ -0,0 +1,1555 @@
+ARM GAS  /tmp/ccsKoAYX.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_exti.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.HAL_EXTI_SetConfigLine,"ax",%progbits
+  17              		.align	1
+  18              		.global	HAL_EXTI_SetConfigLine
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	HAL_EXTI_SetConfigLine:
+  26              	.LVL0:
+  27              	.LFB141:
+  28              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @file    stm32F7xx_hal_exti.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @brief   EXTI HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *           + IO operation functions
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   ******************************************************************************
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @attention
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * Copyright (c) 2018 STMicroelectronics.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * All rights reserved.
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * in the root directory of this software component.
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   ******************************************************************************
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   @verbatim
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   ==============================================================================
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****                     ##### EXTI Peripheral features #####
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   ==============================================================================
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   [..]
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (+) Each Exti line can be configured within this driver.
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (+) Exti line can be configured in 3 different modes
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Interrupt
+ARM GAS  /tmp/ccsKoAYX.s 			page 2
+
+
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Event
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Both of them
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (+) Configurable Exti lines can be configured with 3 different triggers
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Rising
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Falling
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Both of them
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (+) When set in interrupt mode, configurable Exti lines have two different
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         interrupts pending registers which allow to distinguish which transition
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         occurs:
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Rising edge pending interrupt
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Falling
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         be selected through multiplexer.
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****                      ##### How to use this driver #####
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   ==============================================================================
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   [..]
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Choose the interrupt line number by setting "Line" member from
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****              EXTI_ConfigTypeDef structure.
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Configure the interrupt and/or event mode using "Mode" member from
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****              EXTI_ConfigTypeDef structure.
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) For configurable lines, configure rising and/or falling trigger
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****              "Trigger" member from EXTI_ConfigTypeDef structure.
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****              member from GPIO_InitTypeDef structure.
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (#) Get current Exti configuration of a dedicated line using
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         HAL_EXTI_GetConfigLine().
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Provide exiting handle as parameter.
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Provide exiting handle as parameter.
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Provide exiting handle as first parameter.
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Provide which callback will be registered using one value from
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****              EXTI_CallbackIDTypeDef.
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****         (++) Provide callback function pointer.
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   @endverbatim
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Includes ------------------------------------------------------------------*/
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** #include "stm32f7xx_hal.h"
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ARM GAS  /tmp/ccsKoAYX.s 			page 3
+
+
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @{
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** @addtogroup EXTI
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @{
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** MISRA C:2012 deviation rule has been granted for following rule:
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * of bounds [0,3] in following API :
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * HAL_EXTI_SetConfigLine
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * HAL_EXTI_GetConfigLine
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * HAL_EXTI_ClearConfigLine
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** #ifdef HAL_EXTI_MODULE_ENABLED
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Private typedef -----------------------------------------------------------*/
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Private defines -----------------------------------------------------------*/
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** @defgroup EXTI_Private_Constants EXTI Private Constants
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @{
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @}
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Private macros ------------------------------------------------------------*/
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Private variables ---------------------------------------------------------*/
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Private function prototypes -----------------------------------------------*/
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Exported functions --------------------------------------------------------*/
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @{
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group1
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *  @brief    Configuration functions
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** @verbatim
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****  ===============================================================================
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****               ##### Configuration functions #####
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****  ===============================================================================
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** @endverbatim
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @{
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @brief  Set configuration of a dedicated Exti line.
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  pExtiConfig Pointer on EXTI configuration to be set.
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @retval HAL Status.
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** {
+  29              		.loc 1 143 1 view -0
+ARM GAS  /tmp/ccsKoAYX.s 			page 4
+
+
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t regval;
+  34              		.loc 1 144 3 view .LVU1
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t linepos;
+  35              		.loc 1 145 3 view .LVU2
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t maskline;
+  36              		.loc 1 146 3 view .LVU3
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check null pointer */
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if ((hexti == NULL) || (pExtiConfig == NULL))
+  37              		.loc 1 149 3 view .LVU4
+  38              		.loc 1 149 6 is_stmt 0 view .LVU5
+  39 0000 0029     		cmp	r1, #0
+  40 0002 18BF     		it	ne
+  41 0004 0028     		cmpne	r0, #0
+  42 0006 5FD0     		beq	.L11
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t regval;
+  43              		.loc 1 143 1 view .LVU6
+  44 0008 70B4     		push	{r4, r5, r6}
+  45              	.LCFI0:
+  46              		.cfi_def_cfa_offset 12
+  47              		.cfi_offset 4, -12
+  48              		.cfi_offset 5, -8
+  49              		.cfi_offset 6, -4
+  50 000a 0B46     		mov	r3, r1
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     return HAL_ERROR;
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check parameters */
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  51              		.loc 1 155 3 is_stmt 1 view .LVU7
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+  52              		.loc 1 156 3 view .LVU8
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Assign line number to handle */
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   hexti->Line = pExtiConfig->Line;
+  53              		.loc 1 159 3 view .LVU9
+  54              		.loc 1 159 28 is_stmt 0 view .LVU10
+  55 000c 0968     		ldr	r1, [r1]
+  56              	.LVL1:
+  57              		.loc 1 159 15 view .LVU11
+  58 000e 0160     		str	r1, [r0]
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Compute line mask */
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  59              		.loc 1 162 3 is_stmt 1 view .LVU12
+  60              		.loc 1 162 11 is_stmt 0 view .LVU13
+  61 0010 01F01F00 		and	r0, r1, #31
+  62              	.LVL2:
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   maskline = (1uL << linepos);
+  63              		.loc 1 163 3 is_stmt 1 view .LVU14
+  64              		.loc 1 163 12 is_stmt 0 view .LVU15
+  65 0014 0122     		movs	r2, #1
+ARM GAS  /tmp/ccsKoAYX.s 			page 5
+
+
+  66 0016 8240     		lsls	r2, r2, r0
+  67              	.LVL3:
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Configure triggers for configurable lines */
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  68              		.loc 1 166 3 is_stmt 1 view .LVU16
+  69              		.loc 1 166 6 is_stmt 0 view .LVU17
+  70 0018 11F0007F 		tst	r1, #33554432
+  71 001c 15D0     		beq	.L3
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+  72              		.loc 1 168 5 is_stmt 1 view .LVU18
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Configure rising trigger */
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Mask or set line */
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
+  73              		.loc 1 172 5 view .LVU19
+  74              		.loc 1 172 21 is_stmt 0 view .LVU20
+  75 001e 9C68     		ldr	r4, [r3, #8]
+  76              		.loc 1 172 8 view .LVU21
+  77 0020 14F0010F 		tst	r4, #1
+  78 0024 24D0     		beq	.L4
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     {
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       EXTI->RTSR |= maskline;
+  79              		.loc 1 174 7 is_stmt 1 view .LVU22
+  80              		.loc 1 174 18 is_stmt 0 view .LVU23
+  81 0026 294D     		ldr	r5, .L17
+  82 0028 AC68     		ldr	r4, [r5, #8]
+  83 002a 1443     		orrs	r4, r4, r2
+  84 002c AC60     		str	r4, [r5, #8]
+  85              	.L5:
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     else
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     {
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       EXTI->RTSR &= ~maskline;
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Configure falling trigger */
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Mask or set line */
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
+  86              		.loc 1 183 5 is_stmt 1 view .LVU24
+  87              		.loc 1 183 21 is_stmt 0 view .LVU25
+  88 002e 9C68     		ldr	r4, [r3, #8]
+  89              		.loc 1 183 8 view .LVU26
+  90 0030 14F0020F 		tst	r4, #2
+  91 0034 22D0     		beq	.L6
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     {
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       EXTI->FTSR |= maskline;
+  92              		.loc 1 185 7 is_stmt 1 view .LVU27
+  93              		.loc 1 185 18 is_stmt 0 view .LVU28
+  94 0036 254D     		ldr	r5, .L17
+  95 0038 EC68     		ldr	r4, [r5, #12]
+  96 003a 1443     		orrs	r4, r4, r2
+  97 003c EC60     		str	r4, [r5, #12]
+  98              	.L7:
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     else
+ARM GAS  /tmp/ccsKoAYX.s 			page 6
+
+
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     {
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       EXTI->FTSR &= ~maskline;
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Configure gpio port selection in case of gpio exti line */
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+  99              		.loc 1 194 5 is_stmt 1 view .LVU29
+ 100              		.loc 1 194 28 is_stmt 0 view .LVU30
+ 101 003e 1C68     		ldr	r4, [r3]
+ 102 0040 04F0C06C 		and	ip, r4, #100663296
+ 103              		.loc 1 194 8 view .LVU31
+ 104 0044 BCF1C06F 		cmp	ip, #100663296
+ 105 0048 1ED0     		beq	.L16
+ 106              	.LVL4:
+ 107              	.L3:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     {
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       assert_param(IS_EXTI_GPIO_PIN(linepos));
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval = SYSCFG->EXTICR[linepos >> 2u];
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Configure interrupt mode : read current mode */
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Mask or set line */
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+ 108              		.loc 1 208 3 is_stmt 1 view .LVU32
+ 109              		.loc 1 208 19 is_stmt 0 view .LVU33
+ 110 004a 5968     		ldr	r1, [r3, #4]
+ 111              		.loc 1 208 6 view .LVU34
+ 112 004c 11F0010F 		tst	r1, #1
+ 113 0050 2DD0     		beq	.L8
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     EXTI->IMR |= maskline;
+ 114              		.loc 1 210 5 is_stmt 1 view .LVU35
+ 115              		.loc 1 210 15 is_stmt 0 view .LVU36
+ 116 0052 1E48     		ldr	r0, .L17
+ 117 0054 0168     		ldr	r1, [r0]
+ 118 0056 1143     		orrs	r1, r1, r2
+ 119 0058 0160     		str	r1, [r0]
+ 120              	.L9:
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   else
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     EXTI->IMR &= ~maskline;
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Configure event mode : read current mode */
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Mask or set line */
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+ 121              		.loc 1 219 3 is_stmt 1 view .LVU37
+ 122              		.loc 1 219 19 is_stmt 0 view .LVU38
+ 123 005a 5B68     		ldr	r3, [r3, #4]
+ARM GAS  /tmp/ccsKoAYX.s 			page 7
+
+
+ 124              	.LVL5:
+ 125              		.loc 1 219 6 view .LVU39
+ 126 005c 13F0020F 		tst	r3, #2
+ 127 0060 2BD0     		beq	.L10
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     EXTI->EMR |= maskline;
+ 128              		.loc 1 221 5 is_stmt 1 view .LVU40
+ 129              		.loc 1 221 15 is_stmt 0 view .LVU41
+ 130 0062 1A49     		ldr	r1, .L17
+ 131 0064 4B68     		ldr	r3, [r1, #4]
+ 132 0066 1A43     		orrs	r2, r2, r3
+ 133              	.LVL6:
+ 134              		.loc 1 221 15 view .LVU42
+ 135 0068 4A60     		str	r2, [r1, #4]
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   else
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     EXTI->EMR &= ~maskline;
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   return HAL_OK;
+ 136              		.loc 1 228 10 view .LVU43
+ 137 006a 0020     		movs	r0, #0
+ 138              	.L2:
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 139              		.loc 1 229 1 view .LVU44
+ 140 006c 70BC     		pop	{r4, r5, r6}
+ 141              	.LCFI1:
+ 142              		.cfi_remember_state
+ 143              		.cfi_restore 6
+ 144              		.cfi_restore 5
+ 145              		.cfi_restore 4
+ 146              		.cfi_def_cfa_offset 0
+ 147 006e 7047     		bx	lr
+ 148              	.LVL7:
+ 149              	.L4:
+ 150              	.LCFI2:
+ 151              		.cfi_restore_state
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 152              		.loc 1 178 7 is_stmt 1 view .LVU45
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 153              		.loc 1 178 18 is_stmt 0 view .LVU46
+ 154 0070 164D     		ldr	r5, .L17
+ 155 0072 AC68     		ldr	r4, [r5, #8]
+ 156 0074 24EA0204 		bic	r4, r4, r2
+ 157 0078 AC60     		str	r4, [r5, #8]
+ 158 007a D8E7     		b	.L5
+ 159              	.L6:
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 160              		.loc 1 189 7 is_stmt 1 view .LVU47
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 161              		.loc 1 189 18 is_stmt 0 view .LVU48
+ 162 007c 134D     		ldr	r5, .L17
+ 163 007e EC68     		ldr	r4, [r5, #12]
+ 164 0080 24EA0204 		bic	r4, r4, r2
+ 165 0084 EC60     		str	r4, [r5, #12]
+ 166 0086 DAE7     		b	.L7
+ARM GAS  /tmp/ccsKoAYX.s 			page 8
+
+
+ 167              	.L16:
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       assert_param(IS_EXTI_GPIO_PIN(linepos));
+ 168              		.loc 1 196 7 is_stmt 1 view .LVU49
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 169              		.loc 1 197 7 view .LVU50
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 170              		.loc 1 199 7 view .LVU51
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 171              		.loc 1 199 39 is_stmt 0 view .LVU52
+ 172 0088 8008     		lsrs	r0, r0, #2
+ 173              	.LVL8:
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 174              		.loc 1 199 14 view .LVU53
+ 175 008a 114E     		ldr	r6, .L17+4
+ 176 008c 0230     		adds	r0, r0, #2
+ 177 008e 56F82040 		ldr	r4, [r6, r0, lsl #2]
+ 178              	.LVL9:
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 179              		.loc 1 200 7 is_stmt 1 view .LVU54
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 180              		.loc 1 200 80 is_stmt 0 view .LVU55
+ 181 0092 01F00301 		and	r1, r1, #3
+ 182              	.LVL10:
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 183              		.loc 1 200 69 view .LVU56
+ 184 0096 8900     		lsls	r1, r1, #2
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 185              		.loc 1 200 40 view .LVU57
+ 186 0098 0F25     		movs	r5, #15
+ 187 009a 8D40     		lsls	r5, r5, r1
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 188              		.loc 1 200 14 view .LVU58
+ 189 009c 24EA0504 		bic	r4, r4, r5
+ 190              	.LVL11:
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 191              		.loc 1 201 7 is_stmt 1 view .LVU59
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 192              		.loc 1 201 39 is_stmt 0 view .LVU60
+ 193 00a0 DD68     		ldr	r5, [r3, #12]
+ 194 00a2 05FA01F1 		lsl	r1, r5, r1
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 195              		.loc 1 201 14 view .LVU61
+ 196 00a6 2143     		orrs	r1, r1, r4
+ 197              	.LVL12:
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 198              		.loc 1 202 7 is_stmt 1 view .LVU62
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 199              		.loc 1 202 37 is_stmt 0 view .LVU63
+ 200 00a8 46F82010 		str	r1, [r6, r0, lsl #2]
+ 201 00ac CDE7     		b	.L3
+ 202              	.LVL13:
+ 203              	.L8:
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 204              		.loc 1 214 5 is_stmt 1 view .LVU64
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 205              		.loc 1 214 15 is_stmt 0 view .LVU65
+ 206 00ae 0748     		ldr	r0, .L17
+ARM GAS  /tmp/ccsKoAYX.s 			page 9
+
+
+ 207 00b0 0168     		ldr	r1, [r0]
+ 208 00b2 21EA0201 		bic	r1, r1, r2
+ 209 00b6 0160     		str	r1, [r0]
+ 210 00b8 CFE7     		b	.L9
+ 211              	.LVL14:
+ 212              	.L10:
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 213              		.loc 1 225 5 is_stmt 1 view .LVU66
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 214              		.loc 1 225 15 is_stmt 0 view .LVU67
+ 215 00ba 0449     		ldr	r1, .L17
+ 216 00bc 4B68     		ldr	r3, [r1, #4]
+ 217 00be 23EA0202 		bic	r2, r3, r2
+ 218              	.LVL15:
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 219              		.loc 1 225 15 view .LVU68
+ 220 00c2 4A60     		str	r2, [r1, #4]
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 221              		.loc 1 228 10 view .LVU69
+ 222 00c4 0020     		movs	r0, #0
+ 223 00c6 D1E7     		b	.L2
+ 224              	.LVL16:
+ 225              	.L11:
+ 226              	.LCFI3:
+ 227              		.cfi_def_cfa_offset 0
+ 228              		.cfi_restore 4
+ 229              		.cfi_restore 5
+ 230              		.cfi_restore 6
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 231              		.loc 1 151 12 view .LVU70
+ 232 00c8 0120     		movs	r0, #1
+ 233              	.LVL17:
+ 234              		.loc 1 229 1 view .LVU71
+ 235 00ca 7047     		bx	lr
+ 236              	.L18:
+ 237              		.align	2
+ 238              	.L17:
+ 239 00cc 003C0140 		.word	1073822720
+ 240 00d0 00380140 		.word	1073821696
+ 241              		.cfi_endproc
+ 242              	.LFE141:
+ 244              		.section	.text.HAL_EXTI_GetConfigLine,"ax",%progbits
+ 245              		.align	1
+ 246              		.global	HAL_EXTI_GetConfigLine
+ 247              		.syntax unified
+ 248              		.thumb
+ 249              		.thumb_func
+ 250              		.fpu fpv5-d16
+ 252              	HAL_EXTI_GetConfigLine:
+ 253              	.LVL18:
+ 254              	.LFB142:
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @brief  Get configuration of a dedicated Exti line.
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  pExtiConfig Pointer on structure to store Exti configuration.
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @retval HAL Status.
+ARM GAS  /tmp/ccsKoAYX.s 			page 10
+
+
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** {
+ 255              		.loc 1 238 1 is_stmt 1 view -0
+ 256              		.cfi_startproc
+ 257              		@ args = 0, pretend = 0, frame = 0
+ 258              		@ frame_needed = 0, uses_anonymous_args = 0
+ 259              		@ link register save eliminated.
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t regval;
+ 260              		.loc 1 239 3 view .LVU73
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t linepos;
+ 261              		.loc 1 240 3 view .LVU74
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t maskline;
+ 262              		.loc 1 241 3 view .LVU75
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check null pointer */
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if ((hexti == NULL) || (pExtiConfig == NULL))
+ 263              		.loc 1 244 3 view .LVU76
+ 264              		.loc 1 244 6 is_stmt 0 view .LVU77
+ 265 0000 0029     		cmp	r1, #0
+ 266 0002 18BF     		it	ne
+ 267 0004 0028     		cmpne	r0, #0
+ 268 0006 44D0     		beq	.L26
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t regval;
+ 269              		.loc 1 238 1 view .LVU78
+ 270 0008 10B4     		push	{r4}
+ 271              	.LCFI4:
+ 272              		.cfi_def_cfa_offset 4
+ 273              		.cfi_offset 4, -4
+ 274 000a 0B46     		mov	r3, r1
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     return HAL_ERROR;
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check the parameter */
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(hexti->Line));
+ 275              		.loc 1 250 3 is_stmt 1 view .LVU79
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Store handle line number to configuration structure */
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   pExtiConfig->Line = hexti->Line;
+ 276              		.loc 1 253 3 view .LVU80
+ 277              		.loc 1 253 28 is_stmt 0 view .LVU81
+ 278 000c 0468     		ldr	r4, [r0]
+ 279              		.loc 1 253 21 view .LVU82
+ 280 000e 0C60     		str	r4, [r1]
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Compute line mask */
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ 281              		.loc 1 256 3 is_stmt 1 view .LVU83
+ 282              		.loc 1 256 11 is_stmt 0 view .LVU84
+ 283 0010 04F01F0C 		and	ip, r4, #31
+ 284              	.LVL19:
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   maskline = (1uL << linepos);
+ 285              		.loc 1 257 3 is_stmt 1 view .LVU85
+ 286              		.loc 1 257 12 is_stmt 0 view .LVU86
+ 287 0014 0122     		movs	r2, #1
+ 288 0016 02FA0CF2 		lsl	r2, r2, ip
+ARM GAS  /tmp/ccsKoAYX.s 			page 11
+
+
+ 289              	.LVL20:
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* 1] Get core mode : interrupt */
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check if selected line is enable */
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if ((EXTI->IMR & maskline) != 0x00u)
+ 290              		.loc 1 262 3 is_stmt 1 view .LVU87
+ 291              		.loc 1 262 12 is_stmt 0 view .LVU88
+ 292 001a 2148     		ldr	r0, .L34
+ 293              	.LVL21:
+ 294              		.loc 1 262 12 view .LVU89
+ 295 001c 0068     		ldr	r0, [r0]
+ 296              		.loc 1 262 6 view .LVU90
+ 297 001e 1042     		tst	r0, r2
+ 298 0020 24D0     		beq	.L21
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+ 299              		.loc 1 264 5 is_stmt 1 view .LVU91
+ 300              		.loc 1 264 23 is_stmt 0 view .LVU92
+ 301 0022 0121     		movs	r1, #1
+ 302              	.LVL22:
+ 303              		.loc 1 264 23 view .LVU93
+ 304 0024 5960     		str	r1, [r3, #4]
+ 305              	.L22:
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   else
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     pExtiConfig->Mode = EXTI_MODE_NONE;
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Get event mode */
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check if selected line is enable */
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if ((EXTI->EMR & maskline) != 0x00u)
+ 306              		.loc 1 273 3 is_stmt 1 view .LVU94
+ 307              		.loc 1 273 12 is_stmt 0 view .LVU95
+ 308 0026 1E48     		ldr	r0, .L34
+ 309 0028 4068     		ldr	r0, [r0, #4]
+ 310              		.loc 1 273 6 view .LVU96
+ 311 002a 1042     		tst	r0, r2
+ 312 002c 03D0     		beq	.L23
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     pExtiConfig->Mode |= EXTI_MODE_EVENT;
+ 313              		.loc 1 275 5 is_stmt 1 view .LVU97
+ 314              		.loc 1 275 23 is_stmt 0 view .LVU98
+ 315 002e 5868     		ldr	r0, [r3, #4]
+ 316 0030 40F00200 		orr	r0, r0, #2
+ 317 0034 5860     		str	r0, [r3, #4]
+ 318              	.L23:
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Get default Trigger and GPIOSel configuration */
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ 319              		.loc 1 279 3 is_stmt 1 view .LVU99
+ 320              		.loc 1 279 24 is_stmt 0 view .LVU100
+ 321 0036 0021     		movs	r1, #0
+ 322 0038 9960     		str	r1, [r3, #8]
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   pExtiConfig->GPIOSel = 0x00u;
+ARM GAS  /tmp/ccsKoAYX.s 			page 12
+
+
+ 323              		.loc 1 280 3 is_stmt 1 view .LVU101
+ 324              		.loc 1 280 24 is_stmt 0 view .LVU102
+ 325 003a D960     		str	r1, [r3, #12]
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* 2] Get trigger for configurable lines : rising */
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+ 326              		.loc 1 283 3 is_stmt 1 view .LVU103
+ 327              		.loc 1 283 6 is_stmt 0 view .LVU104
+ 328 003c 14F0007F 		tst	r4, #33554432
+ 329 0040 29D0     		beq	.L27
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Check if configuration of selected line is enable */
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     if ((EXTI->RTSR & maskline) != 0x00u)
+ 330              		.loc 1 286 5 is_stmt 1 view .LVU105
+ 331              		.loc 1 286 14 is_stmt 0 view .LVU106
+ 332 0042 1749     		ldr	r1, .L34
+ 333 0044 8968     		ldr	r1, [r1, #8]
+ 334              		.loc 1 286 8 view .LVU107
+ 335 0046 1142     		tst	r1, r2
+ 336 0048 01D0     		beq	.L24
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     {
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+ 337              		.loc 1 288 7 is_stmt 1 view .LVU108
+ 338              		.loc 1 288 28 is_stmt 0 view .LVU109
+ 339 004a 0121     		movs	r1, #1
+ 340 004c 9960     		str	r1, [r3, #8]
+ 341              	.L24:
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Get falling configuration */
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Check if configuration of selected line is enable */
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     if ((EXTI->FTSR & maskline) != 0x00u)
+ 342              		.loc 1 293 5 is_stmt 1 view .LVU110
+ 343              		.loc 1 293 14 is_stmt 0 view .LVU111
+ 344 004e 1449     		ldr	r1, .L34
+ 345 0050 C968     		ldr	r1, [r1, #12]
+ 346              		.loc 1 293 8 view .LVU112
+ 347 0052 1142     		tst	r1, r2
+ 348 0054 03D0     		beq	.L25
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     {
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+ 349              		.loc 1 295 7 is_stmt 1 view .LVU113
+ 350              		.loc 1 295 28 is_stmt 0 view .LVU114
+ 351 0056 9A68     		ldr	r2, [r3, #8]
+ 352              	.LVL23:
+ 353              		.loc 1 295 28 view .LVU115
+ 354 0058 42F00202 		orr	r2, r2, #2
+ 355 005c 9A60     		str	r2, [r3, #8]
+ 356              	.L25:
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Get Gpio port selection for gpio lines */
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ 357              		.loc 1 299 5 is_stmt 1 view .LVU116
+ 358              		.loc 1 299 28 is_stmt 0 view .LVU117
+ 359 005e 04F0C062 		and	r2, r4, #100663296
+ 360              		.loc 1 299 8 view .LVU118
+ARM GAS  /tmp/ccsKoAYX.s 			page 13
+
+
+ 361 0062 B2F1C06F 		cmp	r2, #100663296
+ 362 0066 04D0     		beq	.L33
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     {
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       assert_param(IS_EXTI_GPIO_PIN(linepos));
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval = SYSCFG->EXTICR[linepos >> 2u];
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EX
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   return HAL_OK;
+ 363              		.loc 1 308 10 view .LVU119
+ 364 0068 0020     		movs	r0, #0
+ 365 006a 15E0     		b	.L20
+ 366              	.LVL24:
+ 367              	.L21:
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 368              		.loc 1 268 5 is_stmt 1 view .LVU120
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 369              		.loc 1 268 23 is_stmt 0 view .LVU121
+ 370 006c 0021     		movs	r1, #0
+ 371              	.LVL25:
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 372              		.loc 1 268 23 view .LVU122
+ 373 006e 5960     		str	r1, [r3, #4]
+ 374 0070 D9E7     		b	.L22
+ 375              	.LVL26:
+ 376              	.L33:
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 377              		.loc 1 301 7 is_stmt 1 view .LVU123
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EX
+ 378              		.loc 1 303 7 view .LVU124
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EX
+ 379              		.loc 1 303 39 is_stmt 0 view .LVU125
+ 380 0072 4FEA9C01 		lsr	r1, ip, #2
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EX
+ 381              		.loc 1 303 14 view .LVU126
+ 382 0076 0231     		adds	r1, r1, #2
+ 383 0078 0A4A     		ldr	r2, .L34+4
+ 384 007a 52F82110 		ldr	r1, [r2, r1, lsl #2]
+ 385              	.LVL27:
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 386              		.loc 1 304 7 is_stmt 1 view .LVU127
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 387              		.loc 1 304 78 is_stmt 0 view .LVU128
+ 388 007e 04F00302 		and	r2, r4, #3
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 389              		.loc 1 304 67 view .LVU129
+ 390 0082 9200     		lsls	r2, r2, #2
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 391              		.loc 1 304 38 view .LVU130
+ 392 0084 21FA02F2 		lsr	r2, r1, r2
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 393              		.loc 1 304 89 view .LVU131
+ 394 0088 02F00F02 		and	r2, r2, #15
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 395              		.loc 1 304 28 view .LVU132
+ARM GAS  /tmp/ccsKoAYX.s 			page 14
+
+
+ 396 008c DA60     		str	r2, [r3, #12]
+ 397              		.loc 1 308 10 view .LVU133
+ 398 008e 0020     		movs	r0, #0
+ 399 0090 02E0     		b	.L20
+ 400              	.LVL28:
+ 401              	.L26:
+ 402              	.LCFI5:
+ 403              		.cfi_def_cfa_offset 0
+ 404              		.cfi_restore 4
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 405              		.loc 1 246 12 view .LVU134
+ 406 0092 0120     		movs	r0, #1
+ 407              	.LVL29:
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 408              		.loc 1 309 1 view .LVU135
+ 409 0094 7047     		bx	lr
+ 410              	.LVL30:
+ 411              	.L27:
+ 412              	.LCFI6:
+ 413              		.cfi_def_cfa_offset 4
+ 414              		.cfi_offset 4, -4
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 415              		.loc 1 308 10 view .LVU136
+ 416 0096 0020     		movs	r0, #0
+ 417              	.LVL31:
+ 418              	.L20:
+ 419              		.loc 1 309 1 view .LVU137
+ 420 0098 5DF8044B 		ldr	r4, [sp], #4
+ 421              	.LCFI7:
+ 422              		.cfi_restore 4
+ 423              		.cfi_def_cfa_offset 0
+ 424 009c 7047     		bx	lr
+ 425              	.L35:
+ 426 009e 00BF     		.align	2
+ 427              	.L34:
+ 428 00a0 003C0140 		.word	1073822720
+ 429 00a4 00380140 		.word	1073821696
+ 430              		.cfi_endproc
+ 431              	.LFE142:
+ 433              		.section	.text.HAL_EXTI_ClearConfigLine,"ax",%progbits
+ 434              		.align	1
+ 435              		.global	HAL_EXTI_ClearConfigLine
+ 436              		.syntax unified
+ 437              		.thumb
+ 438              		.thumb_func
+ 439              		.fpu fpv5-d16
+ 441              	HAL_EXTI_ClearConfigLine:
+ 442              	.LVL32:
+ 443              	.LFB143:
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @brief  Clear whole configuration of a dedicated Exti line.
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @retval HAL Status.
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** {
+ARM GAS  /tmp/ccsKoAYX.s 			page 15
+
+
+ 444              		.loc 1 317 1 is_stmt 1 view -0
+ 445              		.cfi_startproc
+ 446              		@ args = 0, pretend = 0, frame = 0
+ 447              		@ frame_needed = 0, uses_anonymous_args = 0
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t regval;
+ 448              		.loc 1 318 3 view .LVU139
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t linepos;
+ 449              		.loc 1 319 3 view .LVU140
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t maskline;
+ 450              		.loc 1 320 3 view .LVU141
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check null pointer */
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if (hexti == NULL)
+ 451              		.loc 1 323 3 view .LVU142
+ 452              		.loc 1 323 6 is_stmt 0 view .LVU143
+ 453 0000 0028     		cmp	r0, #0
+ 454 0002 38D0     		beq	.L38
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t regval;
+ 455              		.loc 1 317 1 view .LVU144
+ 456 0004 10B5     		push	{r4, lr}
+ 457              	.LCFI8:
+ 458              		.cfi_def_cfa_offset 8
+ 459              		.cfi_offset 4, -8
+ 460              		.cfi_offset 14, -4
+ 461 0006 8446     		mov	ip, r0
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     return HAL_ERROR;
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check the parameter */
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(hexti->Line));
+ 462              		.loc 1 329 3 is_stmt 1 view .LVU145
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* compute line mask */
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   linepos = (hexti->Line & EXTI_PIN_MASK);
+ 463              		.loc 1 332 3 view .LVU146
+ 464              		.loc 1 332 19 is_stmt 0 view .LVU147
+ 465 0008 0468     		ldr	r4, [r0]
+ 466              		.loc 1 332 11 view .LVU148
+ 467 000a 04F01F00 		and	r0, r4, #31
+ 468              	.LVL33:
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   maskline = (1uL << linepos);
+ 469              		.loc 1 333 3 is_stmt 1 view .LVU149
+ 470              		.loc 1 333 12 is_stmt 0 view .LVU150
+ 471 000e 0123     		movs	r3, #1
+ 472 0010 8340     		lsls	r3, r3, r0
+ 473              	.LVL34:
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* 1] Clear interrupt mode */
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   EXTI->IMR = (EXTI->IMR & ~maskline);
+ 474              		.loc 1 336 3 is_stmt 1 view .LVU151
+ 475              		.loc 1 336 20 is_stmt 0 view .LVU152
+ 476 0012 1B4A     		ldr	r2, .L46
+ 477 0014 1168     		ldr	r1, [r2]
+ 478              		.loc 1 336 28 view .LVU153
+ 479 0016 6FEA030E 		mvn	lr, r3
+ 480              		.loc 1 336 26 view .LVU154
+ARM GAS  /tmp/ccsKoAYX.s 			page 16
+
+
+ 481 001a 21EA0301 		bic	r1, r1, r3
+ 482              		.loc 1 336 13 view .LVU155
+ 483 001e 1160     		str	r1, [r2]
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* 2] Clear event mode */
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   EXTI->EMR = (EXTI->EMR & ~maskline);
+ 484              		.loc 1 339 3 is_stmt 1 view .LVU156
+ 485              		.loc 1 339 20 is_stmt 0 view .LVU157
+ 486 0020 5168     		ldr	r1, [r2, #4]
+ 487              		.loc 1 339 26 view .LVU158
+ 488 0022 21EA0303 		bic	r3, r1, r3
+ 489              	.LVL35:
+ 490              		.loc 1 339 13 view .LVU159
+ 491 0026 5360     		str	r3, [r2, #4]
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* 3] Clear triggers in case of configurable lines */
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if ((hexti->Line & EXTI_CONFIG) != 0x00u)
+ 492              		.loc 1 342 3 is_stmt 1 view .LVU160
+ 493              		.loc 1 342 13 is_stmt 0 view .LVU161
+ 494 0028 DCF80030 		ldr	r3, [ip]
+ 495              		.loc 1 342 6 view .LVU162
+ 496 002c 13F0007F 		tst	r3, #33554432
+ 497 0030 23D0     		beq	.L39
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     EXTI->RTSR = (EXTI->RTSR & ~maskline);
+ 498              		.loc 1 344 5 is_stmt 1 view .LVU163
+ 499              		.loc 1 344 23 is_stmt 0 view .LVU164
+ 500 0032 9368     		ldr	r3, [r2, #8]
+ 501              		.loc 1 344 30 view .LVU165
+ 502 0034 0EEA0303 		and	r3, lr, r3
+ 503              		.loc 1 344 16 view .LVU166
+ 504 0038 9360     		str	r3, [r2, #8]
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     EXTI->FTSR = (EXTI->FTSR & ~maskline);
+ 505              		.loc 1 345 5 is_stmt 1 view .LVU167
+ 506              		.loc 1 345 23 is_stmt 0 view .LVU168
+ 507 003a D368     		ldr	r3, [r2, #12]
+ 508              		.loc 1 345 30 view .LVU169
+ 509 003c 0EEA0303 		and	r3, lr, r3
+ 510              		.loc 1 345 16 view .LVU170
+ 511 0040 D360     		str	r3, [r2, #12]
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Get Gpio port selection for gpio lines */
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+ 512              		.loc 1 348 5 is_stmt 1 view .LVU171
+ 513              		.loc 1 348 15 is_stmt 0 view .LVU172
+ 514 0042 DCF80030 		ldr	r3, [ip]
+ 515              		.loc 1 348 22 view .LVU173
+ 516 0046 03F0C063 		and	r3, r3, #100663296
+ 517              		.loc 1 348 8 view .LVU174
+ 518 004a B3F1C06F 		cmp	r3, #100663296
+ 519 004e 01D0     		beq	.L45
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     {
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       assert_param(IS_EXTI_GPIO_PIN(linepos));
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval = SYSCFG->EXTICR[linepos >> 2u];
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ARM GAS  /tmp/ccsKoAYX.s 			page 17
+
+
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   return HAL_OK;
+ 520              		.loc 1 358 10 view .LVU175
+ 521 0050 0020     		movs	r0, #0
+ 522              	.LVL36:
+ 523              		.loc 1 358 10 view .LVU176
+ 524 0052 13E0     		b	.L37
+ 525              	.LVL37:
+ 526              	.L45:
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 527              		.loc 1 350 7 is_stmt 1 view .LVU177
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 528              		.loc 1 352 7 view .LVU178
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 529              		.loc 1 352 39 is_stmt 0 view .LVU179
+ 530 0054 8008     		lsrs	r0, r0, #2
+ 531              	.LVL38:
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ 532              		.loc 1 352 14 view .LVU180
+ 533 0056 0B49     		ldr	r1, .L46+4
+ 534 0058 0230     		adds	r0, r0, #2
+ 535 005a 51F82030 		ldr	r3, [r1, r0, lsl #2]
+ 536              	.LVL39:
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 537              		.loc 1 353 7 is_stmt 1 view .LVU181
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 538              		.loc 1 353 80 is_stmt 0 view .LVU182
+ 539 005e 04F00304 		and	r4, r4, #3
+ 540              	.LVL40:
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 541              		.loc 1 353 69 view .LVU183
+ 542 0062 A400     		lsls	r4, r4, #2
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 543              		.loc 1 353 40 view .LVU184
+ 544 0064 0F22     		movs	r2, #15
+ 545 0066 02FA04F4 		lsl	r4, r2, r4
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       SYSCFG->EXTICR[linepos >> 2u] = regval;
+ 546              		.loc 1 353 14 view .LVU185
+ 547 006a 23EA0404 		bic	r4, r3, r4
+ 548              	.LVL41:
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 549              		.loc 1 354 7 is_stmt 1 view .LVU186
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 550              		.loc 1 354 37 is_stmt 0 view .LVU187
+ 551 006e 41F82040 		str	r4, [r1, r0, lsl #2]
+ 552              		.loc 1 358 10 view .LVU188
+ 553 0072 0020     		movs	r0, #0
+ 554 0074 02E0     		b	.L37
+ 555              	.LVL42:
+ 556              	.L38:
+ 557              	.LCFI9:
+ 558              		.cfi_def_cfa_offset 0
+ 559              		.cfi_restore 4
+ 560              		.cfi_restore 14
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ARM GAS  /tmp/ccsKoAYX.s 			page 18
+
+
+ 561              		.loc 1 325 12 view .LVU189
+ 562 0076 0120     		movs	r0, #1
+ 563              	.LVL43:
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 564              		.loc 1 359 1 view .LVU190
+ 565 0078 7047     		bx	lr
+ 566              	.LVL44:
+ 567              	.L39:
+ 568              	.LCFI10:
+ 569              		.cfi_def_cfa_offset 8
+ 570              		.cfi_offset 4, -8
+ 571              		.cfi_offset 14, -4
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 572              		.loc 1 358 10 view .LVU191
+ 573 007a 0020     		movs	r0, #0
+ 574              	.LVL45:
+ 575              	.L37:
+ 576              		.loc 1 359 1 view .LVU192
+ 577 007c 10BD     		pop	{r4, pc}
+ 578              	.L47:
+ 579 007e 00BF     		.align	2
+ 580              	.L46:
+ 581 0080 003C0140 		.word	1073822720
+ 582 0084 00380140 		.word	1073821696
+ 583              		.cfi_endproc
+ 584              	.LFE143:
+ 586              		.section	.text.HAL_EXTI_RegisterCallback,"ax",%progbits
+ 587              		.align	1
+ 588              		.global	HAL_EXTI_RegisterCallback
+ 589              		.syntax unified
+ 590              		.thumb
+ 591              		.thumb_func
+ 592              		.fpu fpv5-d16
+ 594              	HAL_EXTI_RegisterCallback:
+ 595              	.LVL46:
+ 596              	.LFB144:
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @brief  Register callback for a dedicated Exti line.
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  CallbackID User callback identifier.
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  pPendingCbfn function pointer to be stored as callback.
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @retval HAL Status.
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef Callb
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** {
+ 597              		.loc 1 370 1 is_stmt 1 view -0
+ 598              		.cfi_startproc
+ 599              		@ args = 0, pretend = 0, frame = 0
+ 600              		@ frame_needed = 0, uses_anonymous_args = 0
+ 601              		@ link register save eliminated.
+ 602              		.loc 1 370 1 is_stmt 0 view .LVU194
+ 603 0000 0346     		mov	r3, r0
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 604              		.loc 1 371 3 is_stmt 1 view .LVU195
+ 605              	.LVL47:
+ARM GAS  /tmp/ccsKoAYX.s 			page 19
+
+
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   switch (CallbackID)
+ 606              		.loc 1 373 3 view .LVU196
+ 607 0002 0846     		mov	r0, r1
+ 608              	.LVL48:
+ 609              		.loc 1 373 3 is_stmt 0 view .LVU197
+ 610 0004 09B9     		cbnz	r1, .L50
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     case  HAL_EXTI_COMMON_CB_ID:
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       hexti->PendingCallback = pPendingCbfn;
+ 611              		.loc 1 376 7 is_stmt 1 view .LVU198
+ 612              		.loc 1 376 30 is_stmt 0 view .LVU199
+ 613 0006 5A60     		str	r2, [r3, #4]
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       break;
+ 614              		.loc 1 377 7 is_stmt 1 view .LVU200
+ 615 0008 7047     		bx	lr
+ 616              	.L50:
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     default:
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       status = HAL_ERROR;
+ 617              		.loc 1 380 14 is_stmt 0 view .LVU201
+ 618 000a 0120     		movs	r0, #1
+ 619              	.LVL49:
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       break;
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   return status;
+ 620              		.loc 1 384 3 is_stmt 1 view .LVU202
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 621              		.loc 1 385 1 is_stmt 0 view .LVU203
+ 622 000c 7047     		bx	lr
+ 623              		.cfi_endproc
+ 624              	.LFE144:
+ 626              		.section	.text.HAL_EXTI_GetHandle,"ax",%progbits
+ 627              		.align	1
+ 628              		.global	HAL_EXTI_GetHandle
+ 629              		.syntax unified
+ 630              		.thumb
+ 631              		.thumb_func
+ 632              		.fpu fpv5-d16
+ 634              	HAL_EXTI_GetHandle:
+ 635              	.LVL50:
+ 636              	.LFB145:
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @brief  Store line number as handle private field.
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  ExtiLine Exti line number.
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @retval HAL Status.
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** {
+ 637              		.loc 1 395 1 is_stmt 1 view -0
+ 638              		.cfi_startproc
+ 639              		@ args = 0, pretend = 0, frame = 0
+ 640              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccsKoAYX.s 			page 20
+
+
+ 641              		@ link register save eliminated.
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check the parameters */
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(ExtiLine));
+ 642              		.loc 1 397 3 view .LVU205
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check null pointer */
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if (hexti == NULL)
+ 643              		.loc 1 400 3 view .LVU206
+ 644              		.loc 1 400 6 is_stmt 0 view .LVU207
+ 645 0000 10B1     		cbz	r0, .L53
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     return HAL_ERROR;
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   else
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Store line number as handle private field */
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     hexti->Line = ExtiLine;
+ 646              		.loc 1 407 5 is_stmt 1 view .LVU208
+ 647              		.loc 1 407 17 is_stmt 0 view .LVU209
+ 648 0002 0160     		str	r1, [r0]
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     return HAL_OK;
+ 649              		.loc 1 409 5 is_stmt 1 view .LVU210
+ 650              		.loc 1 409 12 is_stmt 0 view .LVU211
+ 651 0004 0020     		movs	r0, #0
+ 652              	.LVL51:
+ 653              		.loc 1 409 12 view .LVU212
+ 654 0006 7047     		bx	lr
+ 655              	.LVL52:
+ 656              	.L53:
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 657              		.loc 1 402 12 view .LVU213
+ 658 0008 0120     		movs	r0, #1
+ 659              	.LVL53:
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 660              		.loc 1 411 1 view .LVU214
+ 661 000a 7047     		bx	lr
+ 662              		.cfi_endproc
+ 663              	.LFE145:
+ 665              		.section	.text.HAL_EXTI_IRQHandler,"ax",%progbits
+ 666              		.align	1
+ 667              		.global	HAL_EXTI_IRQHandler
+ 668              		.syntax unified
+ 669              		.thumb
+ 670              		.thumb_func
+ 671              		.fpu fpv5-d16
+ 673              	HAL_EXTI_IRQHandler:
+ 674              	.LVL54:
+ 675              	.LFB146:
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @}
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group2
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *  @brief EXTI IO functions.
+ARM GAS  /tmp/ccsKoAYX.s 			page 21
+
+
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** @verbatim
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****  ===============================================================================
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****                        ##### IO operation functions #####
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****  ===============================================================================
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** @endverbatim
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @{
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @brief  Handle EXTI interrupt request.
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @retval none.
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** {
+ 676              		.loc 1 435 1 is_stmt 1 view -0
+ 677              		.cfi_startproc
+ 678              		@ args = 0, pretend = 0, frame = 0
+ 679              		@ frame_needed = 0, uses_anonymous_args = 0
+ 680              		.loc 1 435 1 is_stmt 0 view .LVU216
+ 681 0000 08B5     		push	{r3, lr}
+ 682              	.LCFI11:
+ 683              		.cfi_def_cfa_offset 8
+ 684              		.cfi_offset 3, -8
+ 685              		.cfi_offset 14, -4
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t regval;
+ 686              		.loc 1 436 3 is_stmt 1 view .LVU217
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t maskline;
+ 687              		.loc 1 437 3 view .LVU218
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Compute line mask */
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+ 688              		.loc 1 440 3 view .LVU219
+ 689              		.loc 1 440 28 is_stmt 0 view .LVU220
+ 690 0002 0368     		ldr	r3, [r0]
+ 691              		.loc 1 440 35 view .LVU221
+ 692 0004 03F01F02 		and	r2, r3, #31
+ 693              		.loc 1 440 12 view .LVU222
+ 694 0008 0123     		movs	r3, #1
+ 695 000a 9340     		lsls	r3, r3, r2
+ 696              	.LVL55:
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Get pending bit  */
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   regval = (EXTI->PR & maskline);
+ 697              		.loc 1 443 3 is_stmt 1 view .LVU223
+ 698              		.loc 1 443 17 is_stmt 0 view .LVU224
+ 699 000c 044A     		ldr	r2, .L57
+ 700 000e 5269     		ldr	r2, [r2, #20]
+ 701              	.LVL56:
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   if (regval != 0x00u)
+ 702              		.loc 1 444 3 is_stmt 1 view .LVU225
+ 703              		.loc 1 444 6 is_stmt 0 view .LVU226
+ 704 0010 1A42     		tst	r2, r3
+ 705 0012 04D0     		beq	.L54
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   {
+ARM GAS  /tmp/ccsKoAYX.s 			page 22
+
+
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Clear pending bit */
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     EXTI->PR = maskline;
+ 706              		.loc 1 447 5 is_stmt 1 view .LVU227
+ 707              		.loc 1 447 14 is_stmt 0 view .LVU228
+ 708 0014 024A     		ldr	r2, .L57
+ 709              	.LVL57:
+ 710              		.loc 1 447 14 view .LVU229
+ 711 0016 5361     		str	r3, [r2, #20]
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     /* Call callback */
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     if (hexti->PendingCallback != NULL)
+ 712              		.loc 1 450 5 is_stmt 1 view .LVU230
+ 713              		.loc 1 450 14 is_stmt 0 view .LVU231
+ 714 0018 4368     		ldr	r3, [r0, #4]
+ 715              	.LVL58:
+ 716              		.loc 1 450 8 view .LVU232
+ 717 001a 03B1     		cbz	r3, .L54
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     {
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****       hexti->PendingCallback();
+ 718              		.loc 1 452 7 is_stmt 1 view .LVU233
+ 719 001c 9847     		blx	r3
+ 720              	.LVL59:
+ 721              	.L54:
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****     }
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   }
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 722              		.loc 1 455 1 is_stmt 0 view .LVU234
+ 723 001e 08BD     		pop	{r3, pc}
+ 724              	.L58:
+ 725              		.align	2
+ 726              	.L57:
+ 727 0020 003C0140 		.word	1073822720
+ 728              		.cfi_endproc
+ 729              	.LFE146:
+ 731              		.section	.text.HAL_EXTI_GetPending,"ax",%progbits
+ 732              		.align	1
+ 733              		.global	HAL_EXTI_GetPending
+ 734              		.syntax unified
+ 735              		.thumb
+ 736              		.thumb_func
+ 737              		.fpu fpv5-d16
+ 739              	HAL_EXTI_GetPending:
+ 740              	.LVL60:
+ 741              	.LFB147:
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @brief  Get interrupt pending bit of a dedicated line.
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  Edge Specify which pending edge as to be checked.
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *         This parameter can be one of the following values:
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *         This parameter is kept for compatibility with other series.
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @retval 1 if interrupt is pending else 0.
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** {
+ 742              		.loc 1 467 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccsKoAYX.s 			page 23
+
+
+ 743              		.cfi_startproc
+ 744              		@ args = 0, pretend = 0, frame = 0
+ 745              		@ frame_needed = 0, uses_anonymous_args = 0
+ 746              		@ link register save eliminated.
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t regval;
+ 747              		.loc 1 468 3 view .LVU236
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t linepos;
+ 748              		.loc 1 469 3 view .LVU237
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t maskline;
+ 749              		.loc 1 470 3 view .LVU238
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check parameters */
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(hexti->Line));
+ 750              		.loc 1 473 3 view .LVU239
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ 751              		.loc 1 474 3 view .LVU240
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_PENDING_EDGE(Edge));
+ 752              		.loc 1 475 3 view .LVU241
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Compute line mask */
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   linepos = (hexti->Line & EXTI_PIN_MASK);
+ 753              		.loc 1 478 3 view .LVU242
+ 754              		.loc 1 478 19 is_stmt 0 view .LVU243
+ 755 0000 0368     		ldr	r3, [r0]
+ 756              		.loc 1 478 11 view .LVU244
+ 757 0002 03F01F03 		and	r3, r3, #31
+ 758              	.LVL61:
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   maskline = (1uL << linepos);
+ 759              		.loc 1 479 3 is_stmt 1 view .LVU245
+ 760              		.loc 1 479 12 is_stmt 0 view .LVU246
+ 761 0006 0120     		movs	r0, #1
+ 762              	.LVL62:
+ 763              		.loc 1 479 12 view .LVU247
+ 764 0008 00FA03F2 		lsl	r2, r0, r3
+ 765              	.LVL63:
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* return 1 if bit is set else 0 */
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   regval = ((EXTI->PR & maskline) >> linepos);
+ 766              		.loc 1 482 3 is_stmt 1 view .LVU248
+ 767              		.loc 1 482 18 is_stmt 0 view .LVU249
+ 768 000c 0249     		ldr	r1, .L60
+ 769              	.LVL64:
+ 770              		.loc 1 482 18 view .LVU250
+ 771 000e 4869     		ldr	r0, [r1, #20]
+ 772              		.loc 1 482 23 view .LVU251
+ 773 0010 1040     		ands	r0, r0, r2
+ 774              	.LVL65:
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   return regval;
+ 775              		.loc 1 483 3 is_stmt 1 view .LVU252
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 776              		.loc 1 484 1 is_stmt 0 view .LVU253
+ 777 0012 D840     		lsrs	r0, r0, r3
+ 778              	.LVL66:
+ 779              		.loc 1 484 1 view .LVU254
+ 780 0014 7047     		bx	lr
+ 781              	.L61:
+ 782 0016 00BF     		.align	2
+ARM GAS  /tmp/ccsKoAYX.s 			page 24
+
+
+ 783              	.L60:
+ 784 0018 003C0140 		.word	1073822720
+ 785              		.cfi_endproc
+ 786              	.LFE147:
+ 788              		.section	.text.HAL_EXTI_ClearPending,"ax",%progbits
+ 789              		.align	1
+ 790              		.global	HAL_EXTI_ClearPending
+ 791              		.syntax unified
+ 792              		.thumb
+ 793              		.thumb_func
+ 794              		.fpu fpv5-d16
+ 796              	HAL_EXTI_ClearPending:
+ 797              	.LVL67:
+ 798              	.LFB148:
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @brief  Clear interrupt pending bit of a dedicated line.
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  Edge Specify which pending edge as to be clear.
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *         This parameter can be one of the following values:
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   *         This parameter is kept for compatibility with other series.
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @retval None.
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** {
+ 799              		.loc 1 496 1 is_stmt 1 view -0
+ 800              		.cfi_startproc
+ 801              		@ args = 0, pretend = 0, frame = 0
+ 802              		@ frame_needed = 0, uses_anonymous_args = 0
+ 803              		@ link register save eliminated.
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t maskline;
+ 804              		.loc 1 497 3 view .LVU256
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check parameters */
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(hexti->Line));
+ 805              		.loc 1 500 3 view .LVU257
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ 806              		.loc 1 501 3 view .LVU258
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_PENDING_EDGE(Edge));
+ 807              		.loc 1 502 3 view .LVU259
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Compute line mask */
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+ 808              		.loc 1 505 3 view .LVU260
+ 809              		.loc 1 505 28 is_stmt 0 view .LVU261
+ 810 0000 0268     		ldr	r2, [r0]
+ 811              		.loc 1 505 35 view .LVU262
+ 812 0002 02F01F02 		and	r2, r2, #31
+ 813              		.loc 1 505 12 view .LVU263
+ 814 0006 0123     		movs	r3, #1
+ 815 0008 9340     		lsls	r3, r3, r2
+ 816              	.LVL68:
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Clear Pending bit */
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   EXTI->PR =  maskline;
+ 817              		.loc 1 508 3 is_stmt 1 view .LVU264
+ARM GAS  /tmp/ccsKoAYX.s 			page 25
+
+
+ 818              		.loc 1 508 12 is_stmt 0 view .LVU265
+ 819 000a 014A     		ldr	r2, .L63
+ 820 000c 5361     		str	r3, [r2, #20]
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 821              		.loc 1 509 1 view .LVU266
+ 822 000e 7047     		bx	lr
+ 823              	.L64:
+ 824              		.align	2
+ 825              	.L63:
+ 826 0010 003C0140 		.word	1073822720
+ 827              		.cfi_endproc
+ 828              	.LFE148:
+ 830              		.section	.text.HAL_EXTI_GenerateSWI,"ax",%progbits
+ 831              		.align	1
+ 832              		.global	HAL_EXTI_GenerateSWI
+ 833              		.syntax unified
+ 834              		.thumb
+ 835              		.thumb_func
+ 836              		.fpu fpv5-d16
+ 838              	HAL_EXTI_GenerateSWI:
+ 839              	.LVL69:
+ 840              	.LFB149:
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /**
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @brief  Generate a software interrupt for a dedicated line.
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @param  hexti Exti handle.
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   * @retval None.
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   */
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** {
+ 841              		.loc 1 517 1 is_stmt 1 view -0
+ 842              		.cfi_startproc
+ 843              		@ args = 0, pretend = 0, frame = 0
+ 844              		@ frame_needed = 0, uses_anonymous_args = 0
+ 845              		@ link register save eliminated.
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   uint32_t maskline;
+ 846              		.loc 1 518 3 view .LVU268
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Check parameters */
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_LINE(hexti->Line));
+ 847              		.loc 1 521 3 view .LVU269
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ 848              		.loc 1 522 3 view .LVU270
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Compute line mask */
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+ 849              		.loc 1 525 3 view .LVU271
+ 850              		.loc 1 525 28 is_stmt 0 view .LVU272
+ 851 0000 0268     		ldr	r2, [r0]
+ 852              		.loc 1 525 35 view .LVU273
+ 853 0002 02F01F02 		and	r2, r2, #31
+ 854              		.loc 1 525 12 view .LVU274
+ 855 0006 0123     		movs	r3, #1
+ 856 0008 9340     		lsls	r3, r3, r2
+ 857              	.LVL70:
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** 
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   /* Generate Software interrupt */
+ARM GAS  /tmp/ccsKoAYX.s 			page 26
+
+
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c ****   EXTI->SWIER = maskline;
+ 858              		.loc 1 528 3 is_stmt 1 view .LVU275
+ 859              		.loc 1 528 15 is_stmt 0 view .LVU276
+ 860 000a 014A     		ldr	r2, .L66
+ 861 000c 1361     		str	r3, [r2, #16]
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** }
+ 862              		.loc 1 529 1 view .LVU277
+ 863 000e 7047     		bx	lr
+ 864              	.L67:
+ 865              		.align	2
+ 866              	.L66:
+ 867 0010 003C0140 		.word	1073822720
+ 868              		.cfi_endproc
+ 869              	.LFE149:
+ 871              		.text
+ 872              	.Letext0:
+ 873              		.file 2 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 874              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 875              		.file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 876              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h"
+ARM GAS  /tmp/ccsKoAYX.s 			page 27
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_exti.c
+     /tmp/ccsKoAYX.s:17     .text.HAL_EXTI_SetConfigLine:0000000000000000 $t
+     /tmp/ccsKoAYX.s:25     .text.HAL_EXTI_SetConfigLine:0000000000000000 HAL_EXTI_SetConfigLine
+     /tmp/ccsKoAYX.s:239    .text.HAL_EXTI_SetConfigLine:00000000000000cc $d
+     /tmp/ccsKoAYX.s:245    .text.HAL_EXTI_GetConfigLine:0000000000000000 $t
+     /tmp/ccsKoAYX.s:252    .text.HAL_EXTI_GetConfigLine:0000000000000000 HAL_EXTI_GetConfigLine
+     /tmp/ccsKoAYX.s:428    .text.HAL_EXTI_GetConfigLine:00000000000000a0 $d
+     /tmp/ccsKoAYX.s:434    .text.HAL_EXTI_ClearConfigLine:0000000000000000 $t
+     /tmp/ccsKoAYX.s:441    .text.HAL_EXTI_ClearConfigLine:0000000000000000 HAL_EXTI_ClearConfigLine
+     /tmp/ccsKoAYX.s:581    .text.HAL_EXTI_ClearConfigLine:0000000000000080 $d
+     /tmp/ccsKoAYX.s:587    .text.HAL_EXTI_RegisterCallback:0000000000000000 $t
+     /tmp/ccsKoAYX.s:594    .text.HAL_EXTI_RegisterCallback:0000000000000000 HAL_EXTI_RegisterCallback
+     /tmp/ccsKoAYX.s:627    .text.HAL_EXTI_GetHandle:0000000000000000 $t
+     /tmp/ccsKoAYX.s:634    .text.HAL_EXTI_GetHandle:0000000000000000 HAL_EXTI_GetHandle
+     /tmp/ccsKoAYX.s:666    .text.HAL_EXTI_IRQHandler:0000000000000000 $t
+     /tmp/ccsKoAYX.s:673    .text.HAL_EXTI_IRQHandler:0000000000000000 HAL_EXTI_IRQHandler
+     /tmp/ccsKoAYX.s:727    .text.HAL_EXTI_IRQHandler:0000000000000020 $d
+     /tmp/ccsKoAYX.s:732    .text.HAL_EXTI_GetPending:0000000000000000 $t
+     /tmp/ccsKoAYX.s:739    .text.HAL_EXTI_GetPending:0000000000000000 HAL_EXTI_GetPending
+     /tmp/ccsKoAYX.s:784    .text.HAL_EXTI_GetPending:0000000000000018 $d
+     /tmp/ccsKoAYX.s:789    .text.HAL_EXTI_ClearPending:0000000000000000 $t
+     /tmp/ccsKoAYX.s:796    .text.HAL_EXTI_ClearPending:0000000000000000 HAL_EXTI_ClearPending
+     /tmp/ccsKoAYX.s:826    .text.HAL_EXTI_ClearPending:0000000000000010 $d
+     /tmp/ccsKoAYX.s:831    .text.HAL_EXTI_GenerateSWI:0000000000000000 $t
+     /tmp/ccsKoAYX.s:838    .text.HAL_EXTI_GenerateSWI:0000000000000000 HAL_EXTI_GenerateSWI
+     /tmp/ccsKoAYX.s:867    .text.HAL_EXTI_GenerateSWI:0000000000000010 $d
+
+NO UNDEFINED SYMBOLS
diff --git a/build/stm32f7xx_hal_exti.o b/build/stm32f7xx_hal_exti.o
new file mode 100644
index 0000000..dba4ba7
Binary files /dev/null and b/build/stm32f7xx_hal_exti.o differ
diff --git a/build/stm32f7xx_hal_flash.d b/build/stm32f7xx_hal_flash.d
new file mode 100644
index 0000000..b314449
--- /dev/null
+++ b/build/stm32f7xx_hal_flash.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_flash.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_flash.lst b/build/stm32f7xx_hal_flash.lst
new file mode 100644
index 0000000..89f9714
--- /dev/null
+++ b/build/stm32f7xx_hal_flash.lst
@@ -0,0 +1,3444 @@
+ARM GAS  /tmp/ccSYetfS.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_flash.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.FLASH_Program_DoubleWord,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	FLASH_Program_DoubleWord:
+  25              	.LVL0:
+  26              	.LFB153:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @file    stm32f7xx_hal_flash.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief   FLASH HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *          This file provides firmware functions to manage the following 
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *          functionalities of the internal FLASH memory:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *           + Program operations functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *           + Memory Control functions 
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *           + Peripheral Errors functions
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *         
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   @verbatim
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   ==============================================================================
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****                         ##### FLASH peripheral features #####
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   ==============================================================================
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****            
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****        to the Flash memory. It implements the erase and program Flash memory operations 
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****        and the read and write protection mechanisms.
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   [..] The Flash memory interface accelerates code execution with a system of instruction
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****        prefetch and cache lines. 
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   [..] The FLASH main features are:
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       (+) Flash memory read operations
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       (+) Flash memory program/erase operations
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       (+) Read / write protections
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       (+) Prefetch on I-Code
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       (+) 64 cache lines of 128 bits on I-Code
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       (+) 8 cache lines of 128 bits on D-Code
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       
+ARM GAS  /tmp/ccSYetfS.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****                      ##### How to use this driver #####
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   ==============================================================================
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     [..]                             
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       This driver provides functions and macros to configure and program the FLASH 
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       memory of all STM32F7xx devices.
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       (#) FLASH Memory IO Programming functions: 
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****                 HAL_FLASH_Lock() functions
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****            (++) Program functions: byte, half word, word and double word
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****            (++) There Two modes of programming :
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****             (+++) Polling mode using HAL_FLASH_Program() function
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****             (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       (#) Interrupts and flags management functions : 
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****            (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****            (++) Wait for last FLASH operation according to its status
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****            (++) Get error flag status by calling HAL_SetErrorCode()          
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     [..] 
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       In addition to these functions, this driver includes a set of macros allowing
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       to handle the following operations:
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****        (+) Set the latency
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****        (+) Enable/Disable the prefetch buffer
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****        (+) Enable/Disable the Instruction cache and the Data cache
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****        (+) Reset the Instruction cache and the Data cache
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****        (+) Enable/Disable the FLASH interrupts
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****        (+) Monitor the FLASH flags status
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     [..]	   
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 	(@) For any Flash memory program operation (erase or program), the CPU clock frequency
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         (HCLK) must be at least 1MHz. 
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 	(@) The contents of the Flash memory are not guaranteed if a device reset occurs during 
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 	    a Flash memory operation.
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     (@) Any attempt to read the Flash memory while it is being written or erased, causes the 
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 	    bus to stall. Read operations are processed correctly once the program operation has 
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 		completed. This means that code or data fetches cannot be performed while a write/erase 
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 		operation is ongoing.
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   @endverbatim
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   ******************************************************************************
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @attention
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * Copyright (c) 2017 STMicroelectronics.
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * All rights reserved.
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * the root directory of this software component.
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   ******************************************************************************
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */ 
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Includes ------------------------------------------------------------------*/
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #include "stm32f7xx_hal.h"
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @{
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ARM GAS  /tmp/ccSYetfS.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @defgroup FLASH FLASH
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief FLASH HAL module driver
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @{
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #ifdef HAL_FLASH_MODULE_ENABLED
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Private typedef -----------------------------------------------------------*/
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Private define ------------------------------------------------------------*/
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @addtogroup FLASH_Private_Constants
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @{
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #define SECTOR_MASK               ((uint32_t)0xFFFFFF07U)
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #define FLASH_TIMEOUT_VALUE       ((uint32_t)50000U)/* 50 s */
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @}
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */         
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Private macro -------------------------------------------------------------*/
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Private variables ---------------------------------------------------------*/
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @addtogroup FLASH_Private_Variables
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @{
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Variable used for Erase sectors under interruption */
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_ProcessTypeDef pFlash;
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @}
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Private function prototypes -----------------------------------------------*/
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @addtogroup FLASH_Private_Functions
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @{
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Program operations */
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void   FLASH_Program_Word(uint32_t Address, uint32_t Data);
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void   FLASH_SetErrorCode(void);
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @}
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Exported functions --------------------------------------------------------*/
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @{
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  *  @brief   Programming operation functions 
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  *
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @verbatim   
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  ===============================================================================
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****                   ##### Programming operation functions #####
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  ===============================================================================  
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     [..]
+ARM GAS  /tmp/ccSYetfS.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     This subsection provides a set of functions allowing to manage the FLASH 
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     program operations.
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @endverbatim
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @{
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Program byte, halfword, word or double word at a specified address
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  TypeProgram  Indicate the way to program at a specified address.
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *                           This parameter can be a value of @ref FLASH_Type_Program
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Address  specifies the address to be programmed.
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Data specifies the data to be programmed
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * 
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval HAL_StatusTypeDef HAL Status
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Process Locked */
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __HAL_LOCK(&pFlash);
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Check the parameters */
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Wait for last operation to be completed */
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(status == HAL_OK)
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     switch(TypeProgram)
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       case FLASH_TYPEPROGRAM_BYTE :
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /*Program byte (8-bit) at a specified address.*/
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         FLASH_Program_Byte(Address, (uint8_t) Data);
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       case FLASH_TYPEPROGRAM_HALFWORD :
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /*Program halfword (16-bit) at a specified address.*/
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         FLASH_Program_HalfWord(Address, (uint16_t) Data);
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       case FLASH_TYPEPROGRAM_WORD :
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /*Program word (32-bit) at a specified address.*/
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         FLASH_Program_Word(Address, (uint32_t) Data);
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       case FLASH_TYPEPROGRAM_DOUBLEWORD :
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /*Program double word (64-bit) at a specified address.*/
+ARM GAS  /tmp/ccSYetfS.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         FLASH_Program_DoubleWord(Address, Data);
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       default :
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /* Wait for last operation to be completed */
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /* If the program operation is completed, disable the PG Bit */
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     FLASH->CR &= (~FLASH_CR_PG);
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Process Unlocked */
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __HAL_UNLOCK(&pFlash);
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   return status;
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief   Program byte, halfword, word or double word at a specified address  with interrupt ena
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  TypeProgram  Indicate the way to program at a specified address.
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *                           This parameter can be a value of @ref FLASH_Type_Program
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Address  specifies the address to be programmed.
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Data specifies the data to be programmed
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * 
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval HAL Status
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Process Locked */
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __HAL_LOCK(&pFlash);
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Check the parameters */
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Enable End of FLASH Operation interrupt */
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Enable Error source interrupt */
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Clear pending flags (if any) */  
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****                          FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);  
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   pFlash.Address = Address;
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   switch(TypeProgram)
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     case FLASH_TYPEPROGRAM_BYTE :
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       /*Program byte (8-bit) at a specified address.*/
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       FLASH_Program_Byte(Address, (uint8_t) Data);
+ARM GAS  /tmp/ccSYetfS.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       break;
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     case FLASH_TYPEPROGRAM_HALFWORD :
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       /*Program halfword (16-bit) at a specified address.*/
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       FLASH_Program_HalfWord(Address, (uint16_t) Data);
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       break;
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     case FLASH_TYPEPROGRAM_WORD :
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       /*Program word (32-bit) at a specified address.*/
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       FLASH_Program_Word(Address, (uint32_t) Data);
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       break;
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     case FLASH_TYPEPROGRAM_DOUBLEWORD :
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       /*Program double word (64-bit) at a specified address.*/
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       FLASH_Program_DoubleWord(Address, Data);
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       break;
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     default :
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       break;
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   return status;
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief This function handles FLASH interrupt request.
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval None
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** void HAL_FLASH_IRQHandler(void)
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   uint32_t temp = 0;
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* If the program operation is completed, disable the PG Bit */
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR &= (~FLASH_CR_PG);
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* If the erase operation is completed, disable the SER Bit */
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR &= (~FLASH_CR_SER);
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR &= SECTOR_MASK; 
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* if the erase operation is completed, disable the MER Bit */
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR &= (~FLASH_MER_BIT);
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Check FLASH End of Operation flag  */
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /* Clear FLASH End of Operation pending bit */
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     switch (pFlash.ProcedureOnGoing)
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       case FLASH_PROC_SECTERASE :
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ARM GAS  /tmp/ccSYetfS.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /* Nb of sector to erased can be decreased */
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         pFlash.NbSectorsToErase--;
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /* Check if there are still sectors to erase */
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         if(pFlash.NbSectorsToErase != 0)
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         {
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           temp = pFlash.Sector;
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           /* Indicate user which sector has been erased */
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           HAL_FLASH_EndOfOperationCallback(temp);
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           /* Increment sector number */
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           temp = ++pFlash.Sector;
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         }
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         else
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         {
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           /* No more sectors to Erase, user callback can be called.*/
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           /* Reset Sector and stop Erase sectors procedure */
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           pFlash.Sector = temp = 0xFFFFFFFFU;
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           /* FLASH EOP interrupt user callback */
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           HAL_FLASH_EndOfOperationCallback(temp);
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           /* Sector Erase procedure is completed */
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         }
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       case FLASH_PROC_MASSERASE :
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /* MassErase ended. Return the selected bank : in this product we don't have Banks */
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /* FLASH EOP interrupt user callback */
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         HAL_FLASH_EndOfOperationCallback(0);
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /* MAss Erase procedure is completed */
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       case FLASH_PROC_PROGRAM :
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /*Program ended. Return the selected address*/
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /* FLASH EOP interrupt user callback */
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /* Programming procedure is completed */
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       default :
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Check FLASH operation error flags */
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     switch (pFlash.ProcedureOnGoing)
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       case FLASH_PROC_SECTERASE :
+ARM GAS  /tmp/ccSYetfS.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /* return the faulty sector */
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         temp = pFlash.Sector;
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         pFlash.Sector = 0xFFFFFFFFU;
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       case FLASH_PROC_MASSERASE :
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /* No return in case of Mass Erase */
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         temp = 0;
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       case FLASH_PROC_PROGRAM :
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /*return the faulty address*/
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         temp = pFlash.Address;
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     default :
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       break;
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /*Save the Error code*/
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     FLASH_SetErrorCode();
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /* FLASH error interrupt user callback */
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     HAL_FLASH_OperationErrorCallback(temp);
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /*Stop the procedure ongoing */
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /* Disable End of FLASH Operation interrupt */
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /* Disable Error source interrupt */
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /* Process Unlocked */
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     __HAL_UNLOCK(&pFlash);
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  FLASH end of operation interrupt callback
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that 
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *                                  all the selected sectors have been erased)
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *                 - Program      : Address which was selected for data program
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *                 - Mass Erase   : No return value expected
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval None
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Prevent unused argument(s) compilation warning */
+ARM GAS  /tmp/ccSYetfS.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   UNUSED(ReturnValue);
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */ 
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  FLASH operation error interrupt callback
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that 
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *                                  all the selected sectors have been erased)
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *                 - Program      : Address which was selected for data program
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *                 - Mass Erase   : No return value expected
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval None
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Prevent unused argument(s) compilation warning */
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   UNUSED(ReturnValue);
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****    */ 
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @}
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  *  @brief   management functions 
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  *
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @verbatim   
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  ===============================================================================
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****                       ##### Peripheral Control functions #####
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  ===============================================================================  
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     [..]
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     This subsection provides a set of functions allowing to control the FLASH 
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     memory operations.
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @endverbatim
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @{
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Unlock the FLASH control register access
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval HAL Status
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /* Authorize the FLASH Registers access */
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ARM GAS  /tmp/ccSYetfS.s 			page 10
+
+
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /* Verify Flash is unlocked */
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       status = HAL_ERROR;
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   return status;
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Locks the FLASH control register access
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval HAL Status
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Lock(void)
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Set the LOCK Bit to lock the FLASH Registers access */
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR |= FLASH_CR_LOCK;
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   return HAL_OK;  
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Unlock the FLASH Option Control Registers access.
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval HAL Status
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /* Authorizes the Option Byte register programming */
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     FLASH->OPTKEYR = FLASH_OPT_KEY1;
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     FLASH->OPTKEYR = FLASH_OPT_KEY2;
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   else
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     return HAL_ERROR;
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }  
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   return HAL_OK;  
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Lock the FLASH Option Control Registers access.
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval HAL Status 
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   return HAL_OK;  
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Launch the option byte loading.
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval HAL Status
+ARM GAS  /tmp/ccSYetfS.s 			page 11
+
+
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Set the OPTSTRT bit in OPTCR register */
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Wait for last operation to be completed */
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); 
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @}
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions 
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  *  @brief   Peripheral Errors functions 
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  *
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @verbatim   
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  ===============================================================================
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****                 ##### Peripheral Errors functions #####
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****  ===============================================================================  
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     [..]
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     This subsection permits to get in run-time Errors of the FLASH peripheral.
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @endverbatim
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @{
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Get the specific FLASH error flag.
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval FLASH_ErrorCode: The returned value can be:
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *            @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag 
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *            @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *            @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *            @arg FLASH_ERROR_WRP: FLASH Write protected error flag
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *            @arg FLASH_ERROR_OPERATION: FLASH operation Error flag 
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** uint32_t HAL_FLASH_GetError(void)
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { 
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****    return pFlash.ErrorCode;
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }  
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @}
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */    
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Wait for a FLASH operation to complete.
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Timeout maximum flash operationtimeout
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval HAL Status
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { 
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   uint32_t tickstart = 0;
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Clear Error Code */
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+ARM GAS  /tmp/ccSYetfS.s 			page 12
+
+
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****      Even if the FLASH operation fails, the BUSY flag will be reset and an error
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****      flag will be set */
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Get tick */
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   tickstart = HAL_GetTick();
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) 
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   { 
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     if(Timeout != HAL_MAX_DELAY)
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         return HAL_TIMEOUT;
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     } 
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /*Save the error code*/
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     FLASH_SetErrorCode();
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     return HAL_ERROR;
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Check FLASH End of Operation flag  */
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     /* Clear FLASH End of Operation pending bit */
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* If there is an error flag set */
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   return HAL_OK;
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }  
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Program a double word (64-bit) at a specified address.
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @note   This function must be used when the device voltage range is from
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *         2.7V to 3.6V and an External Vpp is present.
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @note   If an erase and a program operations are requested simultaneously,    
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *         the erase operation is performed before the program one.
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *  
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Address specifies the address to be programmed.
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Data specifies the data to be programmed.
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval None
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+  28              		.loc 1 652 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  33              		.loc 1 652 1 is_stmt 0 view .LVU1
+ARM GAS  /tmp/ccSYetfS.s 			page 13
+
+
+  34 0000 10B4     		push	{r4}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 4
+  37              		.cfi_offset 4, -4
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Check the parameters */
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   assert_param(IS_FLASH_ADDRESS(Address));
+  38              		.loc 1 654 3 is_stmt 1 view .LVU2
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* If the previous operation is completed, proceed to program the new data */
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR &= CR_PSIZE_MASK;
+  39              		.loc 1 657 3 view .LVU3
+  40              		.loc 1 657 13 is_stmt 0 view .LVU4
+  41 0002 0B49     		ldr	r1, .L3
+  42 0004 0C69     		ldr	r4, [r1, #16]
+  43 0006 24F44074 		bic	r4, r4, #768
+  44 000a 0C61     		str	r4, [r1, #16]
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
+  45              		.loc 1 658 3 is_stmt 1 view .LVU5
+  46              		.loc 1 658 13 is_stmt 0 view .LVU6
+  47 000c 0C69     		ldr	r4, [r1, #16]
+  48 000e 44F44074 		orr	r4, r4, #768
+  49 0012 0C61     		str	r4, [r1, #16]
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR |= FLASH_CR_PG;
+  50              		.loc 1 659 3 is_stmt 1 view .LVU7
+  51              		.loc 1 659 13 is_stmt 0 view .LVU8
+  52 0014 0C69     		ldr	r4, [r1, #16]
+  53 0016 44F00104 		orr	r4, r4, #1
+  54 001a 0C61     		str	r4, [r1, #16]
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Program first word */
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *(__IO uint32_t*)Address = (uint32_t)Data;
+  55              		.loc 1 662 3 is_stmt 1 view .LVU9
+  56              		.loc 1 662 28 is_stmt 0 view .LVU10
+  57 001c 0260     		str	r2, [r0]
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Barrier to ensure programming is performed in 2 steps, in right order
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     (independently of compiler optimization behavior) */
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __ISB();
+  58              		.loc 1 665 3 is_stmt 1 view .LVU11
+  59              	.LBB12:
+  60              	.LBI12:
+  61              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.0.4
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     09. April 2018
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+ARM GAS  /tmp/ccSYetfS.s 			page 14
+
+
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ARM GAS  /tmp/ccSYetfS.s 			page 15
+
+
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccSYetfS.s 			page 16
+
+
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ARM GAS  /tmp/ccSYetfS.s 			page 17
+
+
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ARM GAS  /tmp/ccSYetfS.s 			page 18
+
+
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ARM GAS  /tmp/ccSYetfS.s 			page 19
+
+
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ARM GAS  /tmp/ccSYetfS.s 			page 20
+
+
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ARM GAS  /tmp/ccSYetfS.s 			page 21
+
+
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ARM GAS  /tmp/ccSYetfS.s 			page 22
+
+
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ARM GAS  /tmp/ccSYetfS.s 			page 23
+
+
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ARM GAS  /tmp/ccSYetfS.s 			page 24
+
+
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ARM GAS  /tmp/ccSYetfS.s 			page 25
+
+
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ARM GAS  /tmp/ccSYetfS.s 			page 26
+
+
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ARM GAS  /tmp/ccSYetfS.s 			page 27
+
+
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ARM GAS  /tmp/ccSYetfS.s 			page 28
+
+
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+  62              		.loc 2 866 27 view .LVU12
+  63              	.LBB13:
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+  64              		.loc 2 868 3 view .LVU13
+ARM GAS  /tmp/ccSYetfS.s 			page 29
+
+
+  65              		.syntax unified
+  66              	@ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+  67 001e BFF36F8F 		isb 0xF
+  68              	@ 0 "" 2
+  69              		.thumb
+  70              		.syntax unified
+  71              	.LBE13:
+  72              	.LBE12:
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Program second word */
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
+  73              		.loc 1 668 3 view .LVU14
+  74              		.loc 1 668 32 is_stmt 0 view .LVU15
+  75 0022 4360     		str	r3, [r0, #4]
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Data synchronous Barrier (DSB) Just after the write operation
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****      This will force the CPU to respect the sequence of instruction (no optimization).*/
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __DSB();
+  76              		.loc 1 672 3 is_stmt 1 view .LVU16
+  77              	.LBB14:
+  78              	.LBI14:
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+  79              		.loc 2 877 27 view .LVU17
+  80              	.LBB15:
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+  81              		.loc 2 879 3 view .LVU18
+  82              		.syntax unified
+  83              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+  84 0024 BFF34F8F 		dsb 0xF
+  85              	@ 0 "" 2
+  86              		.thumb
+  87              		.syntax unified
+  88              	.LBE15:
+  89              	.LBE14:
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+  90              		.loc 1 673 1 is_stmt 0 view .LVU19
+  91 0028 5DF8044B 		ldr	r4, [sp], #4
+  92              	.LCFI1:
+  93              		.cfi_restore 4
+  94              		.cfi_def_cfa_offset 0
+  95 002c 7047     		bx	lr
+  96              	.L4:
+  97 002e 00BF     		.align	2
+  98              	.L3:
+  99 0030 003C0240 		.word	1073888256
+ 100              		.cfi_endproc
+ 101              	.LFE153:
+ 103              		.section	.text.FLASH_Program_Word,"ax",%progbits
+ARM GAS  /tmp/ccSYetfS.s 			page 30
+
+
+ 104              		.align	1
+ 105              		.syntax unified
+ 106              		.thumb
+ 107              		.thumb_func
+ 108              		.fpu fpv5-d16
+ 110              	FLASH_Program_Word:
+ 111              	.LVL1:
+ 112              	.LFB154:
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Program word (32-bit) at a specified address.
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @note   This function must be used when the device voltage range is from
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *         2.7V to 3.3V.
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @note   If an erase and a program operations are requested simultaneously,    
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *         the erase operation is performed before the program one.
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *  
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Address specifies the address to be programmed.
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Data specifies the data to be programmed.
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval None
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 113              		.loc 1 689 1 is_stmt 1 view -0
+ 114              		.cfi_startproc
+ 115              		@ args = 0, pretend = 0, frame = 0
+ 116              		@ frame_needed = 0, uses_anonymous_args = 0
+ 117              		@ link register save eliminated.
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Check the parameters */
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   assert_param(IS_FLASH_ADDRESS(Address));
+ 118              		.loc 1 691 3 view .LVU21
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* If the previous operation is completed, proceed to program the new data */
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR &= CR_PSIZE_MASK;
+ 119              		.loc 1 694 3 view .LVU22
+ 120              		.loc 1 694 13 is_stmt 0 view .LVU23
+ 121 0000 084B     		ldr	r3, .L6
+ 122 0002 1A69     		ldr	r2, [r3, #16]
+ 123 0004 22F44072 		bic	r2, r2, #768
+ 124 0008 1A61     		str	r2, [r3, #16]
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR |= FLASH_PSIZE_WORD;
+ 125              		.loc 1 695 3 is_stmt 1 view .LVU24
+ 126              		.loc 1 695 13 is_stmt 0 view .LVU25
+ 127 000a 1A69     		ldr	r2, [r3, #16]
+ 128 000c 42F40072 		orr	r2, r2, #512
+ 129 0010 1A61     		str	r2, [r3, #16]
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR |= FLASH_CR_PG;
+ 130              		.loc 1 696 3 is_stmt 1 view .LVU26
+ 131              		.loc 1 696 13 is_stmt 0 view .LVU27
+ 132 0012 1A69     		ldr	r2, [r3, #16]
+ 133 0014 42F00102 		orr	r2, r2, #1
+ 134 0018 1A61     		str	r2, [r3, #16]
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *(__IO uint32_t*)Address = Data;
+ 135              		.loc 1 698 3 is_stmt 1 view .LVU28
+ 136              		.loc 1 698 28 is_stmt 0 view .LVU29
+ARM GAS  /tmp/ccSYetfS.s 			page 31
+
+
+ 137 001a 0160     		str	r1, [r0]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Data synchronous Barrier (DSB) Just after the write operation
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****      This will force the CPU to respect the sequence of instruction (no optimization).*/
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __DSB();
+ 138              		.loc 1 702 3 is_stmt 1 view .LVU30
+ 139              	.LBB16:
+ 140              	.LBI16:
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 141              		.loc 2 877 27 view .LVU31
+ 142              	.LBB17:
+ 143              		.loc 2 879 3 view .LVU32
+ 144              		.syntax unified
+ 145              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 146 001c BFF34F8F 		dsb 0xF
+ 147              	@ 0 "" 2
+ 148              		.thumb
+ 149              		.syntax unified
+ 150              	.LBE17:
+ 151              	.LBE16:
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 152              		.loc 1 703 1 is_stmt 0 view .LVU33
+ 153 0020 7047     		bx	lr
+ 154              	.L7:
+ 155 0022 00BF     		.align	2
+ 156              	.L6:
+ 157 0024 003C0240 		.word	1073888256
+ 158              		.cfi_endproc
+ 159              	.LFE154:
+ 161              		.section	.text.FLASH_Program_HalfWord,"ax",%progbits
+ 162              		.align	1
+ 163              		.syntax unified
+ 164              		.thumb
+ 165              		.thumb_func
+ 166              		.fpu fpv5-d16
+ 168              	FLASH_Program_HalfWord:
+ 169              	.LVL2:
+ 170              	.LFB155:
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Program a half-word (16-bit) at a specified address.
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @note   This function must be used when the device voltage range is from
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *         2.1V to 3.6V.
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @note   If an erase and a program operations are requested simultaneously,    
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *         the erase operation is performed before the program one.
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *  
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Address specifies the address to be programmed.
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Data specifies the data to be programmed.
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval None
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 171              		.loc 1 718 1 is_stmt 1 view -0
+ 172              		.cfi_startproc
+ 173              		@ args = 0, pretend = 0, frame = 0
+ 174              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccSYetfS.s 			page 32
+
+
+ 175              		@ link register save eliminated.
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Check the parameters */
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   assert_param(IS_FLASH_ADDRESS(Address));
+ 176              		.loc 1 720 3 view .LVU35
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* If the previous operation is completed, proceed to program the new data */
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR &= CR_PSIZE_MASK;
+ 177              		.loc 1 723 3 view .LVU36
+ 178              		.loc 1 723 13 is_stmt 0 view .LVU37
+ 179 0000 084B     		ldr	r3, .L9
+ 180 0002 1A69     		ldr	r2, [r3, #16]
+ 181 0004 22F44072 		bic	r2, r2, #768
+ 182 0008 1A61     		str	r2, [r3, #16]
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR |= FLASH_PSIZE_HALF_WORD;
+ 183              		.loc 1 724 3 is_stmt 1 view .LVU38
+ 184              		.loc 1 724 13 is_stmt 0 view .LVU39
+ 185 000a 1A69     		ldr	r2, [r3, #16]
+ 186 000c 42F48072 		orr	r2, r2, #256
+ 187 0010 1A61     		str	r2, [r3, #16]
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR |= FLASH_CR_PG;
+ 188              		.loc 1 725 3 is_stmt 1 view .LVU40
+ 189              		.loc 1 725 13 is_stmt 0 view .LVU41
+ 190 0012 1A69     		ldr	r2, [r3, #16]
+ 191 0014 42F00102 		orr	r2, r2, #1
+ 192 0018 1A61     		str	r2, [r3, #16]
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *(__IO uint16_t*)Address = Data;
+ 193              		.loc 1 727 3 is_stmt 1 view .LVU42
+ 194              		.loc 1 727 28 is_stmt 0 view .LVU43
+ 195 001a 0180     		strh	r1, [r0]	@ movhi
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Data synchronous Barrier (DSB) Just after the write operation
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****      This will force the CPU to respect the sequence of instruction (no optimization).*/
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __DSB();
+ 196              		.loc 1 731 3 is_stmt 1 view .LVU44
+ 197              	.LBB18:
+ 198              	.LBI18:
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 199              		.loc 2 877 27 view .LVU45
+ 200              	.LBB19:
+ 201              		.loc 2 879 3 view .LVU46
+ 202              		.syntax unified
+ 203              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 204 001c BFF34F8F 		dsb 0xF
+ 205              	@ 0 "" 2
+ 206              		.thumb
+ 207              		.syntax unified
+ 208              	.LBE19:
+ 209              	.LBE18:
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 210              		.loc 1 733 1 is_stmt 0 view .LVU47
+ 211 0020 7047     		bx	lr
+ 212              	.L10:
+ 213 0022 00BF     		.align	2
+ 214              	.L9:
+ 215 0024 003C0240 		.word	1073888256
+ARM GAS  /tmp/ccSYetfS.s 			page 33
+
+
+ 216              		.cfi_endproc
+ 217              	.LFE155:
+ 219              		.section	.text.FLASH_Program_Byte,"ax",%progbits
+ 220              		.align	1
+ 221              		.syntax unified
+ 222              		.thumb
+ 223              		.thumb_func
+ 224              		.fpu fpv5-d16
+ 226              	FLASH_Program_Byte:
+ 227              	.LVL3:
+ 228              	.LFB156:
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Program byte (8-bit) at a specified address.
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @note   This function must be used when the device voltage range is from
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *         1.7V to 3.6V.
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @note   If an erase and a program operations are requested simultaneously,    
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *         the erase operation is performed before the program one.
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *  
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Address specifies the address to be programmed.
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @param  Data specifies the data to be programmed.
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval None
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 229              		.loc 1 748 1 is_stmt 1 view -0
+ 230              		.cfi_startproc
+ 231              		@ args = 0, pretend = 0, frame = 0
+ 232              		@ frame_needed = 0, uses_anonymous_args = 0
+ 233              		@ link register save eliminated.
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Check the parameters */
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   assert_param(IS_FLASH_ADDRESS(Address));
+ 234              		.loc 1 750 3 view .LVU49
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* If the previous operation is completed, proceed to program the new data */
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR &= CR_PSIZE_MASK;
+ 235              		.loc 1 753 3 view .LVU50
+ 236              		.loc 1 753 13 is_stmt 0 view .LVU51
+ 237 0000 074B     		ldr	r3, .L12
+ 238 0002 1A69     		ldr	r2, [r3, #16]
+ 239 0004 22F44072 		bic	r2, r2, #768
+ 240 0008 1A61     		str	r2, [r3, #16]
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR |= FLASH_PSIZE_BYTE;
+ 241              		.loc 1 754 3 is_stmt 1 view .LVU52
+ 242              		.loc 1 754 13 is_stmt 0 view .LVU53
+ 243 000a 1A69     		ldr	r2, [r3, #16]
+ 244 000c 1A61     		str	r2, [r3, #16]
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR |= FLASH_CR_PG;
+ 245              		.loc 1 755 3 is_stmt 1 view .LVU54
+ 246              		.loc 1 755 13 is_stmt 0 view .LVU55
+ 247 000e 1A69     		ldr	r2, [r3, #16]
+ 248 0010 42F00102 		orr	r2, r2, #1
+ 249 0014 1A61     		str	r2, [r3, #16]
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   *(__IO uint8_t*)Address = Data;
+ 250              		.loc 1 757 3 is_stmt 1 view .LVU56
+ARM GAS  /tmp/ccSYetfS.s 			page 34
+
+
+ 251              		.loc 1 757 27 is_stmt 0 view .LVU57
+ 252 0016 0170     		strb	r1, [r0]
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Data synchronous Barrier (DSB) Just after the write operation
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****      This will force the CPU to respect the sequence of instruction (no optimization).*/
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __DSB();
+ 253              		.loc 1 761 3 is_stmt 1 view .LVU58
+ 254              	.LBB20:
+ 255              	.LBI20:
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 256              		.loc 2 877 27 view .LVU59
+ 257              	.LBB21:
+ 258              		.loc 2 879 3 view .LVU60
+ 259              		.syntax unified
+ 260              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 261 0018 BFF34F8F 		dsb 0xF
+ 262              	@ 0 "" 2
+ 263              		.thumb
+ 264              		.syntax unified
+ 265              	.LBE21:
+ 266              	.LBE20:
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 267              		.loc 1 762 1 is_stmt 0 view .LVU61
+ 268 001c 7047     		bx	lr
+ 269              	.L13:
+ 270 001e 00BF     		.align	2
+ 271              	.L12:
+ 272 0020 003C0240 		.word	1073888256
+ 273              		.cfi_endproc
+ 274              	.LFE156:
+ 276              		.section	.text.FLASH_SetErrorCode,"ax",%progbits
+ 277              		.align	1
+ 278              		.syntax unified
+ 279              		.thumb
+ 280              		.thumb_func
+ 281              		.fpu fpv5-d16
+ 283              	FLASH_SetErrorCode:
+ 284              	.LFB157:
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /**
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @brief  Set the specific FLASH error flag.
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   * @retval None
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   */
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_SetErrorCode(void)
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** {
+ 285              		.loc 1 769 1 is_stmt 1 view -0
+ 286              		.cfi_startproc
+ 287              		@ args = 0, pretend = 0, frame = 0
+ 288              		@ frame_needed = 0, uses_anonymous_args = 0
+ 289              		@ link register save eliminated.
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
+ 290              		.loc 1 770 3 view .LVU63
+ 291              		.loc 1 770 6 is_stmt 0 view .LVU64
+ 292 0000 1A4B     		ldr	r3, .L20
+ 293 0002 DB68     		ldr	r3, [r3, #12]
+ 294              		.loc 1 770 5 view .LVU65
+ 295 0004 13F0020F 		tst	r3, #2
+ARM GAS  /tmp/ccSYetfS.s 			page 35
+
+
+ 296 0008 04D0     		beq	.L15
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
+ 297              		.loc 1 772 5 is_stmt 1 view .LVU66
+ 298              		.loc 1 772 22 is_stmt 0 view .LVU67
+ 299 000a 194A     		ldr	r2, .L20+4
+ 300 000c 9369     		ldr	r3, [r2, #24]
+ 301 000e 43F02003 		orr	r3, r3, #32
+ 302 0012 9361     		str	r3, [r2, #24]
+ 303              	.L15:
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
+ 304              		.loc 1 775 3 is_stmt 1 view .LVU68
+ 305              		.loc 1 775 6 is_stmt 0 view .LVU69
+ 306 0014 154B     		ldr	r3, .L20
+ 307 0016 DB68     		ldr	r3, [r3, #12]
+ 308              		.loc 1 775 5 view .LVU70
+ 309 0018 13F0100F 		tst	r3, #16
+ 310 001c 04D0     		beq	.L16
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+ 311              		.loc 1 777 4 is_stmt 1 view .LVU71
+ 312              		.loc 1 777 21 is_stmt 0 view .LVU72
+ 313 001e 144A     		ldr	r2, .L20+4
+ 314 0020 9369     		ldr	r3, [r2, #24]
+ 315 0022 43F01003 		orr	r3, r3, #16
+ 316 0026 9361     		str	r3, [r2, #24]
+ 317              	.L16:
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
+ 318              		.loc 1 780 3 is_stmt 1 view .LVU73
+ 319              		.loc 1 780 6 is_stmt 0 view .LVU74
+ 320 0028 104B     		ldr	r3, .L20
+ 321 002a DB68     		ldr	r3, [r3, #12]
+ 322              		.loc 1 780 5 view .LVU75
+ 323 002c 13F0200F 		tst	r3, #32
+ 324 0030 04D0     		beq	.L17
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
+ 325              		.loc 1 782 4 is_stmt 1 view .LVU76
+ 326              		.loc 1 782 21 is_stmt 0 view .LVU77
+ 327 0032 0F4A     		ldr	r2, .L20+4
+ 328 0034 9369     		ldr	r3, [r2, #24]
+ 329 0036 43F00803 		orr	r3, r3, #8
+ 330 003a 9361     		str	r3, [r2, #24]
+ 331              	.L17:
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
+ 332              		.loc 1 785 3 is_stmt 1 view .LVU78
+ 333              		.loc 1 785 6 is_stmt 0 view .LVU79
+ 334 003c 0B4B     		ldr	r3, .L20
+ 335 003e DB68     		ldr	r3, [r3, #12]
+ 336              		.loc 1 785 5 view .LVU80
+ 337 0040 13F0400F 		tst	r3, #64
+ARM GAS  /tmp/ccSYetfS.s 			page 36
+
+
+ 338 0044 04D0     		beq	.L18
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
+ 339              		.loc 1 787 5 is_stmt 1 view .LVU81
+ 340              		.loc 1 787 22 is_stmt 0 view .LVU82
+ 341 0046 0A4A     		ldr	r2, .L20+4
+ 342 0048 9369     		ldr	r3, [r2, #24]
+ 343 004a 43F00403 		orr	r3, r3, #4
+ 344 004e 9361     		str	r3, [r2, #24]
+ 345              	.L18:
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET)
+ 346              		.loc 1 790 3 is_stmt 1 view .LVU83
+ 347              		.loc 1 790 6 is_stmt 0 view .LVU84
+ 348 0050 064B     		ldr	r3, .L20
+ 349 0052 DB68     		ldr	r3, [r3, #12]
+ 350              		.loc 1 790 5 view .LVU85
+ 351 0054 13F0800F 		tst	r3, #128
+ 352 0058 04D0     		beq	.L19
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;
+ 353              		.loc 1 792 5 is_stmt 1 view .LVU86
+ 354              		.loc 1 792 22 is_stmt 0 view .LVU87
+ 355 005a 054A     		ldr	r2, .L20+4
+ 356 005c 9369     		ldr	r3, [r2, #24]
+ 357 005e 43F00203 		orr	r3, r3, #2
+ 358 0062 9361     		str	r3, [r2, #24]
+ 359              	.L19:
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #if defined (FLASH_OPTCR2_PCROP)
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   { 
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****    pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }  
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #endif /* FLASH_OPTCR2_PCROP */
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Clear error programming flags */
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
+ 360              		.loc 1 803 3 is_stmt 1 view .LVU88
+ 361 0064 014B     		ldr	r3, .L20
+ 362 0066 F222     		movs	r2, #242
+ 363 0068 DA60     		str	r2, [r3, #12]
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 364              		.loc 1 804 1 is_stmt 0 view .LVU89
+ 365 006a 7047     		bx	lr
+ 366              	.L21:
+ 367              		.align	2
+ 368              	.L20:
+ 369 006c 003C0240 		.word	1073888256
+ 370 0070 00000000 		.word	.LANCHOR0
+ 371              		.cfi_endproc
+ 372              	.LFE157:
+ 374              		.section	.text.HAL_FLASH_Program_IT,"ax",%progbits
+ 375              		.align	1
+ 376              		.global	HAL_FLASH_Program_IT
+ARM GAS  /tmp/ccSYetfS.s 			page 37
+
+
+ 377              		.syntax unified
+ 378              		.thumb
+ 379              		.thumb_func
+ 380              		.fpu fpv5-d16
+ 382              	HAL_FLASH_Program_IT:
+ 383              	.LVL4:
+ 384              	.LFB142:
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 385              		.loc 1 232 1 is_stmt 1 view -0
+ 386              		.cfi_startproc
+ 387              		@ args = 0, pretend = 0, frame = 0
+ 388              		@ frame_needed = 0, uses_anonymous_args = 0
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 389              		.loc 1 232 1 is_stmt 0 view .LVU91
+ 390 0000 70B5     		push	{r4, r5, r6, lr}
+ 391              	.LCFI2:
+ 392              		.cfi_def_cfa_offset 16
+ 393              		.cfi_offset 4, -16
+ 394              		.cfi_offset 5, -12
+ 395              		.cfi_offset 6, -8
+ 396              		.cfi_offset 14, -4
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 397              		.loc 1 233 3 is_stmt 1 view .LVU92
+ 398              	.LVL5:
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 399              		.loc 1 236 3 view .LVU93
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 400              		.loc 1 236 3 view .LVU94
+ 401 0002 1A4C     		ldr	r4, .L32
+ 402 0004 247D     		ldrb	r4, [r4, #20]	@ zero_extendqisi2
+ 403 0006 012C     		cmp	r4, #1
+ 404 0008 2CD0     		beq	.L29
+ 405 000a 8446     		mov	ip, r0
+ 406 000c 0846     		mov	r0, r1
+ 407              	.LVL6:
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 408              		.loc 1 236 3 discriminator 2 view .LVU95
+ 409 000e 174D     		ldr	r5, .L32
+ 410 0010 0121     		movs	r1, #1
+ 411              	.LVL7:
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 412              		.loc 1 236 3 is_stmt 0 discriminator 2 view .LVU96
+ 413 0012 2975     		strb	r1, [r5, #20]
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 414              		.loc 1 236 3 is_stmt 1 discriminator 2 view .LVU97
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 415              		.loc 1 239 3 discriminator 2 view .LVU98
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 416              		.loc 1 242 3 discriminator 2 view .LVU99
+ 417 0014 164C     		ldr	r4, .L32+4
+ 418 0016 2669     		ldr	r6, [r4, #16]
+ 419 0018 46F08076 		orr	r6, r6, #16777216
+ 420 001c 2661     		str	r6, [r4, #16]
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 421              		.loc 1 245 3 discriminator 2 view .LVU100
+ 422 001e 2669     		ldr	r6, [r4, #16]
+ 423 0020 46F00076 		orr	r6, r6, #33554432
+ARM GAS  /tmp/ccSYetfS.s 			page 38
+
+
+ 424 0024 2661     		str	r6, [r4, #16]
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****                          FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);  
+ 425              		.loc 1 248 3 discriminator 2 view .LVU101
+ 426 0026 F321     		movs	r1, #243
+ 427 0028 E160     		str	r1, [r4, #12]
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   pFlash.Address = Address;
+ 428              		.loc 1 251 3 discriminator 2 view .LVU102
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   pFlash.Address = Address;
+ 429              		.loc 1 251 27 is_stmt 0 discriminator 2 view .LVU103
+ 430 002a 0321     		movs	r1, #3
+ 431 002c 2970     		strb	r1, [r5]
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 432              		.loc 1 252 3 is_stmt 1 discriminator 2 view .LVU104
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 433              		.loc 1 252 18 is_stmt 0 discriminator 2 view .LVU105
+ 434 002e 2861     		str	r0, [r5, #16]
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 435              		.loc 1 254 3 is_stmt 1 discriminator 2 view .LVU106
+ 436 0030 BCF1030F 		cmp	ip, #3
+ 437 0034 18D8     		bhi	.L30
+ 438 0036 DFE80CF0 		tbb	[pc, ip]
+ 439              	.L25:
+ 440 003a 02       		.byte	(.L28-.L25)/2
+ 441 003b 07       		.byte	(.L27-.L25)/2
+ 442 003c 0C       		.byte	(.L26-.L25)/2
+ 443 003d 11       		.byte	(.L24-.L25)/2
+ 444              		.p2align 1
+ 445              	.L28:
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       break;
+ 446              		.loc 1 259 7 view .LVU107
+ 447 003e D1B2     		uxtb	r1, r2
+ 448 0040 FFF7FEFF 		bl	FLASH_Program_Byte
+ 449              	.LVL8:
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 450              		.loc 1 260 7 view .LVU108
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 451              		.loc 1 286 10 is_stmt 0 view .LVU109
+ 452 0044 0020     		movs	r0, #0
+ 453              	.L23:
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 454              		.loc 1 287 1 view .LVU110
+ 455 0046 70BD     		pop	{r4, r5, r6, pc}
+ 456              	.LVL9:
+ 457              	.L27:
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       break;
+ 458              		.loc 1 266 7 is_stmt 1 view .LVU111
+ 459 0048 91B2     		uxth	r1, r2
+ 460 004a FFF7FEFF 		bl	FLASH_Program_HalfWord
+ 461              	.LVL10:
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 462              		.loc 1 267 7 view .LVU112
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 463              		.loc 1 286 10 is_stmt 0 view .LVU113
+ 464 004e 0020     		movs	r0, #0
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 465              		.loc 1 267 7 view .LVU114
+ 466 0050 F9E7     		b	.L23
+ARM GAS  /tmp/ccSYetfS.s 			page 39
+
+
+ 467              	.LVL11:
+ 468              	.L26:
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       break;
+ 469              		.loc 1 273 7 is_stmt 1 view .LVU115
+ 470 0052 1146     		mov	r1, r2
+ 471 0054 FFF7FEFF 		bl	FLASH_Program_Word
+ 472              	.LVL12:
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 473              		.loc 1 274 7 view .LVU116
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 474              		.loc 1 286 10 is_stmt 0 view .LVU117
+ 475 0058 0020     		movs	r0, #0
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 476              		.loc 1 274 7 view .LVU118
+ 477 005a F4E7     		b	.L23
+ 478              	.LVL13:
+ 479              	.L24:
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       break;
+ 480              		.loc 1 280 7 is_stmt 1 view .LVU119
+ 481 005c FFF7FEFF 		bl	FLASH_Program_DoubleWord
+ 482              	.LVL14:
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 483              		.loc 1 281 7 view .LVU120
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 484              		.loc 1 286 10 is_stmt 0 view .LVU121
+ 485 0060 0020     		movs	r0, #0
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 486              		.loc 1 281 7 view .LVU122
+ 487 0062 F0E7     		b	.L23
+ 488              	.LVL15:
+ 489              	.L29:
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 490              		.loc 1 236 3 view .LVU123
+ 491 0064 0220     		movs	r0, #2
+ 492              	.LVL16:
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 493              		.loc 1 236 3 view .LVU124
+ 494 0066 EEE7     		b	.L23
+ 495              	.LVL17:
+ 496              	.L30:
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 497              		.loc 1 254 3 view .LVU125
+ 498 0068 0020     		movs	r0, #0
+ 499              	.LVL18:
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 500              		.loc 1 254 3 view .LVU126
+ 501 006a ECE7     		b	.L23
+ 502              	.L33:
+ 503              		.align	2
+ 504              	.L32:
+ 505 006c 00000000 		.word	.LANCHOR0
+ 506 0070 003C0240 		.word	1073888256
+ 507              		.cfi_endproc
+ 508              	.LFE142:
+ 510              		.section	.text.HAL_FLASH_EndOfOperationCallback,"ax",%progbits
+ 511              		.align	1
+ 512              		.weak	HAL_FLASH_EndOfOperationCallback
+ARM GAS  /tmp/ccSYetfS.s 			page 40
+
+
+ 513              		.syntax unified
+ 514              		.thumb
+ 515              		.thumb_func
+ 516              		.fpu fpv5-d16
+ 518              	HAL_FLASH_EndOfOperationCallback:
+ 519              	.LVL19:
+ 520              	.LFB144:
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Prevent unused argument(s) compilation warning */
+ 521              		.loc 1 429 1 is_stmt 1 view -0
+ 522              		.cfi_startproc
+ 523              		@ args = 0, pretend = 0, frame = 0
+ 524              		@ frame_needed = 0, uses_anonymous_args = 0
+ 525              		@ link register save eliminated.
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 526              		.loc 1 431 3 view .LVU128
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 527              		.loc 1 435 1 is_stmt 0 view .LVU129
+ 528 0000 7047     		bx	lr
+ 529              		.cfi_endproc
+ 530              	.LFE144:
+ 532              		.section	.text.HAL_FLASH_OperationErrorCallback,"ax",%progbits
+ 533              		.align	1
+ 534              		.weak	HAL_FLASH_OperationErrorCallback
+ 535              		.syntax unified
+ 536              		.thumb
+ 537              		.thumb_func
+ 538              		.fpu fpv5-d16
+ 540              	HAL_FLASH_OperationErrorCallback:
+ 541              	.LVL20:
+ 542              	.LFB145:
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Prevent unused argument(s) compilation warning */
+ 543              		.loc 1 447 1 is_stmt 1 view -0
+ 544              		.cfi_startproc
+ 545              		@ args = 0, pretend = 0, frame = 0
+ 546              		@ frame_needed = 0, uses_anonymous_args = 0
+ 547              		@ link register save eliminated.
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 548              		.loc 1 449 3 view .LVU131
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 549              		.loc 1 453 1 is_stmt 0 view .LVU132
+ 550 0000 7047     		bx	lr
+ 551              		.cfi_endproc
+ 552              	.LFE145:
+ 554              		.section	.text.HAL_FLASH_IRQHandler,"ax",%progbits
+ 555              		.align	1
+ 556              		.global	HAL_FLASH_IRQHandler
+ 557              		.syntax unified
+ 558              		.thumb
+ 559              		.thumb_func
+ 560              		.fpu fpv5-d16
+ 562              	HAL_FLASH_IRQHandler:
+ 563              	.LFB143:
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   uint32_t temp = 0;
+ 564              		.loc 1 294 1 is_stmt 1 view -0
+ 565              		.cfi_startproc
+ 566              		@ args = 0, pretend = 0, frame = 0
+ 567              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccSYetfS.s 			page 41
+
+
+ 568 0000 38B5     		push	{r3, r4, r5, lr}
+ 569              	.LCFI3:
+ 570              		.cfi_def_cfa_offset 16
+ 571              		.cfi_offset 3, -16
+ 572              		.cfi_offset 4, -12
+ 573              		.cfi_offset 5, -8
+ 574              		.cfi_offset 14, -4
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 575              		.loc 1 295 3 view .LVU134
+ 576              	.LVL21:
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 577              		.loc 1 298 3 view .LVU135
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 578              		.loc 1 298 13 is_stmt 0 view .LVU136
+ 579 0002 3F4B     		ldr	r3, .L50
+ 580 0004 1A69     		ldr	r2, [r3, #16]
+ 581 0006 22F00102 		bic	r2, r2, #1
+ 582 000a 1A61     		str	r2, [r3, #16]
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR &= SECTOR_MASK; 
+ 583              		.loc 1 301 3 is_stmt 1 view .LVU137
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   FLASH->CR &= SECTOR_MASK; 
+ 584              		.loc 1 301 13 is_stmt 0 view .LVU138
+ 585 000c 1A69     		ldr	r2, [r3, #16]
+ 586 000e 22F00202 		bic	r2, r2, #2
+ 587 0012 1A61     		str	r2, [r3, #16]
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 588              		.loc 1 302 3 is_stmt 1 view .LVU139
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 589              		.loc 1 302 13 is_stmt 0 view .LVU140
+ 590 0014 1A69     		ldr	r2, [r3, #16]
+ 591 0016 22F0F802 		bic	r2, r2, #248
+ 592 001a 1A61     		str	r2, [r3, #16]
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 593              		.loc 1 305 3 is_stmt 1 view .LVU141
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 594              		.loc 1 305 13 is_stmt 0 view .LVU142
+ 595 001c 1969     		ldr	r1, [r3, #16]
+ 596 001e 394A     		ldr	r2, .L50+4
+ 597 0020 0A40     		ands	r2, r2, r1
+ 598 0022 1A61     		str	r2, [r3, #16]
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 599              		.loc 1 308 3 is_stmt 1 view .LVU143
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 600              		.loc 1 308 6 is_stmt 0 view .LVU144
+ 601 0024 DC68     		ldr	r4, [r3, #12]
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 602              		.loc 1 308 5 view .LVU145
+ 603 0026 14F00104 		ands	r4, r4, #1
+ 604 002a 0BD0     		beq	.L37
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     
+ 605              		.loc 1 311 5 is_stmt 1 view .LVU146
+ 606 002c 0122     		movs	r2, #1
+ 607 002e DA60     		str	r2, [r3, #12]
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 608              		.loc 1 313 5 view .LVU147
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 609              		.loc 1 313 19 is_stmt 0 view .LVU148
+ARM GAS  /tmp/ccSYetfS.s 			page 42
+
+
+ 610 0030 354B     		ldr	r3, .L50+8
+ 611 0032 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 612 0034 DBB2     		uxtb	r3, r3
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 613              		.loc 1 313 5 view .LVU149
+ 614 0036 022B     		cmp	r3, #2
+ 615 0038 46D0     		beq	.L38
+ 616 003a 032B     		cmp	r3, #3
+ 617 003c 4CD0     		beq	.L39
+ 618 003e 9342     		cmp	r3, r2
+ 619 0040 26D0     		beq	.L48
+ 620 0042 0024     		movs	r4, #0
+ 621              	.LVL22:
+ 622              	.L37:
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 623              		.loc 1 369 3 is_stmt 1 view .LVU150
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 624              		.loc 1 369 6 is_stmt 0 view .LVU151
+ 625 0044 2E4B     		ldr	r3, .L50
+ 626 0046 DB68     		ldr	r3, [r3, #12]
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 627              		.loc 1 369 5 view .LVU152
+ 628 0048 13F0F20F 		tst	r3, #242
+ 629 004c 10D0     		beq	.L41
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 630              		.loc 1 371 5 is_stmt 1 view .LVU153
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 631              		.loc 1 371 19 is_stmt 0 view .LVU154
+ 632 004e 2E4B     		ldr	r3, .L50+8
+ 633 0050 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 634 0052 DBB2     		uxtb	r3, r3
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 635              		.loc 1 371 5 view .LVU155
+ 636 0054 022B     		cmp	r3, #2
+ 637 0056 50D0     		beq	.L46
+ 638 0058 032B     		cmp	r3, #3
+ 639 005a 4BD0     		beq	.L43
+ 640 005c 012B     		cmp	r3, #1
+ 641 005e 43D0     		beq	.L49
+ 642              	.LVL23:
+ 643              	.L42:
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 644              		.loc 1 396 5 is_stmt 1 view .LVU156
+ 645 0060 FFF7FEFF 		bl	FLASH_SetErrorCode
+ 646              	.LVL24:
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 647              		.loc 1 399 5 view .LVU157
+ 648 0064 2046     		mov	r0, r4
+ 649 0066 FFF7FEFF 		bl	HAL_FLASH_OperationErrorCallback
+ 650              	.LVL25:
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 651              		.loc 1 402 5 view .LVU158
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 652              		.loc 1 402 29 is_stmt 0 view .LVU159
+ 653 006a 274B     		ldr	r3, .L50+8
+ 654 006c 0022     		movs	r2, #0
+ 655 006e 1A70     		strb	r2, [r3]
+ARM GAS  /tmp/ccSYetfS.s 			page 43
+
+
+ 656              	.L41:
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 657              		.loc 1 405 3 is_stmt 1 view .LVU160
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 658              		.loc 1 405 12 is_stmt 0 view .LVU161
+ 659 0070 254B     		ldr	r3, .L50+8
+ 660 0072 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 661              		.loc 1 405 5 view .LVU162
+ 662 0074 5BB9     		cbnz	r3, .L36
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 663              		.loc 1 408 5 is_stmt 1 view .LVU163
+ 664 0076 224B     		ldr	r3, .L50
+ 665 0078 1A69     		ldr	r2, [r3, #16]
+ 666 007a 22F08072 		bic	r2, r2, #16777216
+ 667 007e 1A61     		str	r2, [r3, #16]
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 668              		.loc 1 411 5 view .LVU164
+ 669 0080 1A69     		ldr	r2, [r3, #16]
+ 670 0082 22F00072 		bic	r2, r2, #33554432
+ 671 0086 1A61     		str	r2, [r3, #16]
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 672              		.loc 1 414 5 view .LVU165
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 673              		.loc 1 414 5 view .LVU166
+ 674 0088 1F4B     		ldr	r3, .L50+8
+ 675 008a 0022     		movs	r2, #0
+ 676 008c 1A75     		strb	r2, [r3, #20]
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 677              		.loc 1 414 5 view .LVU167
+ 678              	.L36:
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 679              		.loc 1 417 1 is_stmt 0 view .LVU168
+ 680 008e 38BD     		pop	{r3, r4, r5, pc}
+ 681              	.LVL26:
+ 682              	.L48:
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 683              		.loc 1 318 9 is_stmt 1 view .LVU169
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 684              		.loc 1 318 15 is_stmt 0 view .LVU170
+ 685 0090 1D4B     		ldr	r3, .L50+8
+ 686 0092 5A68     		ldr	r2, [r3, #4]
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 687              		.loc 1 318 32 view .LVU171
+ 688 0094 013A     		subs	r2, r2, #1
+ 689 0096 5A60     		str	r2, [r3, #4]
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         {
+ 690              		.loc 1 321 9 is_stmt 1 view .LVU172
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         {
+ 691              		.loc 1 321 18 is_stmt 0 view .LVU173
+ 692 0098 5B68     		ldr	r3, [r3, #4]
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         {
+ 693              		.loc 1 321 11 view .LVU174
+ 694 009a 5BB1     		cbz	r3, .L40
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           /* Indicate user which sector has been erased */
+ 695              		.loc 1 323 11 is_stmt 1 view .LVU175
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           /* Indicate user which sector has been erased */
+ARM GAS  /tmp/ccSYetfS.s 			page 44
+
+
+ 696              		.loc 1 323 16 is_stmt 0 view .LVU176
+ 697 009c 1A4D     		ldr	r5, .L50+8
+ 698 009e E868     		ldr	r0, [r5, #12]
+ 699              	.LVL27:
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 700              		.loc 1 325 11 is_stmt 1 view .LVU177
+ 701 00a0 FFF7FEFF 		bl	HAL_FLASH_EndOfOperationCallback
+ 702              	.LVL28:
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
+ 703              		.loc 1 328 11 view .LVU178
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
+ 704              		.loc 1 328 26 is_stmt 0 view .LVU179
+ 705 00a4 EC68     		ldr	r4, [r5, #12]
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
+ 706              		.loc 1 328 18 view .LVU180
+ 707 00a6 0134     		adds	r4, r4, #1
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
+ 708              		.loc 1 328 16 view .LVU181
+ 709 00a8 EC60     		str	r4, [r5, #12]
+ 710              	.LVL29:
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         }
+ 711              		.loc 1 329 11 is_stmt 1 view .LVU182
+ 712 00aa 297A     		ldrb	r1, [r5, #8]	@ zero_extendqisi2
+ 713 00ac 2046     		mov	r0, r4
+ 714 00ae FFF7FEFF 		bl	FLASH_Erase_Sector
+ 715              	.LVL30:
+ 716 00b2 C7E7     		b	.L37
+ 717              	.LVL31:
+ 718              	.L40:
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           /* FLASH EOP interrupt user callback */
+ 719              		.loc 1 335 11 view .LVU183
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           /* FLASH EOP interrupt user callback */
+ 720              		.loc 1 335 25 is_stmt 0 view .LVU184
+ 721 00b4 144D     		ldr	r5, .L50+8
+ 722 00b6 4FF0FF34 		mov	r4, #-1
+ 723 00ba EC60     		str	r4, [r5, #12]
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****           /* Sector Erase procedure is completed */
+ 724              		.loc 1 337 11 is_stmt 1 view .LVU185
+ 725 00bc 2046     		mov	r0, r4
+ 726 00be FFF7FEFF 		bl	HAL_FLASH_EndOfOperationCallback
+ 727              	.LVL32:
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         }
+ 728              		.loc 1 339 11 view .LVU186
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         }
+ 729              		.loc 1 339 35 is_stmt 0 view .LVU187
+ 730 00c2 0023     		movs	r3, #0
+ 731 00c4 2B70     		strb	r3, [r5]
+ 732 00c6 BDE7     		b	.L37
+ 733              	.LVL33:
+ 734              	.L38:
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /* MAss Erase procedure is completed */
+ 735              		.loc 1 348 9 is_stmt 1 view .LVU188
+ 736 00c8 0020     		movs	r0, #0
+ 737 00ca FFF7FEFF 		bl	HAL_FLASH_EndOfOperationCallback
+ 738              	.LVL34:
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 739              		.loc 1 350 9 view .LVU189
+ARM GAS  /tmp/ccSYetfS.s 			page 45
+
+
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 740              		.loc 1 350 33 is_stmt 0 view .LVU190
+ 741 00ce 0020     		movs	r0, #0
+ 742 00d0 0D4B     		ldr	r3, .L50+8
+ 743 00d2 1870     		strb	r0, [r3]
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 744              		.loc 1 351 9 is_stmt 1 view .LVU191
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 745              		.loc 1 295 12 is_stmt 0 view .LVU192
+ 746 00d4 0446     		mov	r4, r0
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 747              		.loc 1 351 9 view .LVU193
+ 748 00d6 B5E7     		b	.L37
+ 749              	.L39:
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         /* Programming procedure is completed */
+ 750              		.loc 1 358 9 is_stmt 1 view .LVU194
+ 751 00d8 0B4C     		ldr	r4, .L50+8
+ 752 00da 2069     		ldr	r0, [r4, #16]
+ 753 00dc FFF7FEFF 		bl	HAL_FLASH_EndOfOperationCallback
+ 754              	.LVL35:
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 755              		.loc 1 360 9 view .LVU195
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 756              		.loc 1 360 33 is_stmt 0 view .LVU196
+ 757 00e0 0020     		movs	r0, #0
+ 758 00e2 2070     		strb	r0, [r4]
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 759              		.loc 1 361 9 is_stmt 1 view .LVU197
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 760              		.loc 1 295 12 is_stmt 0 view .LVU198
+ 761 00e4 0446     		mov	r4, r0
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 762              		.loc 1 361 9 view .LVU199
+ 763 00e6 ADE7     		b	.L37
+ 764              	.LVL36:
+ 765              	.L49:
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         pFlash.Sector = 0xFFFFFFFFU;
+ 766              		.loc 1 376 9 is_stmt 1 view .LVU200
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         pFlash.Sector = 0xFFFFFFFFU;
+ 767              		.loc 1 376 14 is_stmt 0 view .LVU201
+ 768 00e8 074B     		ldr	r3, .L50+8
+ 769 00ea DC68     		ldr	r4, [r3, #12]
+ 770              	.LVL37:
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 771              		.loc 1 377 9 is_stmt 1 view .LVU202
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 772              		.loc 1 377 23 is_stmt 0 view .LVU203
+ 773 00ec 4FF0FF32 		mov	r2, #-1
+ 774 00f0 DA60     		str	r2, [r3, #12]
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 775              		.loc 1 378 9 is_stmt 1 view .LVU204
+ 776 00f2 B5E7     		b	.L42
+ 777              	.L43:
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 778              		.loc 1 389 9 view .LVU205
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 779              		.loc 1 389 14 is_stmt 0 view .LVU206
+ARM GAS  /tmp/ccSYetfS.s 			page 46
+
+
+ 780 00f4 044B     		ldr	r3, .L50+8
+ 781 00f6 1C69     		ldr	r4, [r3, #16]
+ 782              	.LVL38:
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 783              		.loc 1 390 9 is_stmt 1 view .LVU207
+ 784 00f8 B2E7     		b	.L42
+ 785              	.L46:
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 786              		.loc 1 383 14 is_stmt 0 view .LVU208
+ 787 00fa 0024     		movs	r4, #0
+ 788              	.LVL39:
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 789              		.loc 1 383 14 view .LVU209
+ 790 00fc B0E7     		b	.L42
+ 791              	.L51:
+ 792 00fe 00BF     		.align	2
+ 793              	.L50:
+ 794 0100 003C0240 		.word	1073888256
+ 795 0104 FB7FFFFF 		.word	-32773
+ 796 0108 00000000 		.word	.LANCHOR0
+ 797              		.cfi_endproc
+ 798              	.LFE143:
+ 800              		.section	.text.HAL_FLASH_Unlock,"ax",%progbits
+ 801              		.align	1
+ 802              		.global	HAL_FLASH_Unlock
+ 803              		.syntax unified
+ 804              		.thumb
+ 805              		.thumb_func
+ 806              		.fpu fpv5-d16
+ 808              	HAL_FLASH_Unlock:
+ 809              	.LFB146:
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 810              		.loc 1 479 1 is_stmt 1 view -0
+ 811              		.cfi_startproc
+ 812              		@ args = 0, pretend = 0, frame = 0
+ 813              		@ frame_needed = 0, uses_anonymous_args = 0
+ 814              		@ link register save eliminated.
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 815              		.loc 1 480 3 view .LVU211
+ 816              	.LVL40:
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 817              		.loc 1 482 3 view .LVU212
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 818              		.loc 1 482 6 is_stmt 0 view .LVU213
+ 819 0000 094B     		ldr	r3, .L57
+ 820 0002 1B69     		ldr	r3, [r3, #16]
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 821              		.loc 1 482 5 view .LVU214
+ 822 0004 002B     		cmp	r3, #0
+ 823 0006 01DB     		blt	.L56
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 824              		.loc 1 480 21 view .LVU215
+ 825 0008 0020     		movs	r0, #0
+ 826 000a 7047     		bx	lr
+ 827              	.L56:
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+ 828              		.loc 1 485 5 is_stmt 1 view .LVU216
+ARM GAS  /tmp/ccSYetfS.s 			page 47
+
+
+ 829 000c 064B     		ldr	r3, .L57
+ 830 000e 074A     		ldr	r2, .L57+4
+ 831 0010 5A60     		str	r2, [r3, #4]
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 832              		.loc 1 486 5 view .LVU217
+ 833 0012 02F18832 		add	r2, r2, #-2004318072
+ 834 0016 5A60     		str	r2, [r3, #4]
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 835              		.loc 1 489 5 view .LVU218
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 836              		.loc 1 489 8 is_stmt 0 view .LVU219
+ 837 0018 1B69     		ldr	r3, [r3, #16]
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 838              		.loc 1 489 7 view .LVU220
+ 839 001a 002B     		cmp	r3, #0
+ 840 001c 01DB     		blt	.L55
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 841              		.loc 1 480 21 view .LVU221
+ 842 001e 0020     		movs	r0, #0
+ 843 0020 7047     		bx	lr
+ 844              	.L55:
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     }
+ 845              		.loc 1 491 14 view .LVU222
+ 846 0022 0120     		movs	r0, #1
+ 847              	.LVL41:
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 848              		.loc 1 495 3 is_stmt 1 view .LVU223
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 849              		.loc 1 496 1 is_stmt 0 view .LVU224
+ 850 0024 7047     		bx	lr
+ 851              	.L58:
+ 852 0026 00BF     		.align	2
+ 853              	.L57:
+ 854 0028 003C0240 		.word	1073888256
+ 855 002c 23016745 		.word	1164378403
+ 856              		.cfi_endproc
+ 857              	.LFE146:
+ 859              		.section	.text.HAL_FLASH_Lock,"ax",%progbits
+ 860              		.align	1
+ 861              		.global	HAL_FLASH_Lock
+ 862              		.syntax unified
+ 863              		.thumb
+ 864              		.thumb_func
+ 865              		.fpu fpv5-d16
+ 867              	HAL_FLASH_Lock:
+ 868              	.LFB147:
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Set the LOCK Bit to lock the FLASH Registers access */
+ 869              		.loc 1 503 1 is_stmt 1 view -0
+ 870              		.cfi_startproc
+ 871              		@ args = 0, pretend = 0, frame = 0
+ 872              		@ frame_needed = 0, uses_anonymous_args = 0
+ 873              		@ link register save eliminated.
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 874              		.loc 1 505 3 view .LVU226
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 875              		.loc 1 505 13 is_stmt 0 view .LVU227
+ 876 0000 034A     		ldr	r2, .L60
+ARM GAS  /tmp/ccSYetfS.s 			page 48
+
+
+ 877 0002 1369     		ldr	r3, [r2, #16]
+ 878 0004 43F00043 		orr	r3, r3, #-2147483648
+ 879 0008 1361     		str	r3, [r2, #16]
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 880              		.loc 1 507 3 is_stmt 1 view .LVU228
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 881              		.loc 1 508 1 is_stmt 0 view .LVU229
+ 882 000a 0020     		movs	r0, #0
+ 883 000c 7047     		bx	lr
+ 884              	.L61:
+ 885 000e 00BF     		.align	2
+ 886              	.L60:
+ 887 0010 003C0240 		.word	1073888256
+ 888              		.cfi_endproc
+ 889              	.LFE147:
+ 891              		.section	.text.HAL_FLASH_OB_Unlock,"ax",%progbits
+ 892              		.align	1
+ 893              		.global	HAL_FLASH_OB_Unlock
+ 894              		.syntax unified
+ 895              		.thumb
+ 896              		.thumb_func
+ 897              		.fpu fpv5-d16
+ 899              	HAL_FLASH_OB_Unlock:
+ 900              	.LFB148:
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
+ 901              		.loc 1 515 1 is_stmt 1 view -0
+ 902              		.cfi_startproc
+ 903              		@ args = 0, pretend = 0, frame = 0
+ 904              		@ frame_needed = 0, uses_anonymous_args = 0
+ 905              		@ link register save eliminated.
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 906              		.loc 1 516 3 view .LVU231
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 907              		.loc 1 516 12 is_stmt 0 view .LVU232
+ 908 0000 074B     		ldr	r3, .L65
+ 909 0002 5B69     		ldr	r3, [r3, #20]
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 910              		.loc 1 516 5 view .LVU233
+ 911 0004 13F0010F 		tst	r3, #1
+ 912 0008 07D0     		beq	.L64
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     FLASH->OPTKEYR = FLASH_OPT_KEY2;
+ 913              		.loc 1 519 5 is_stmt 1 view .LVU234
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     FLASH->OPTKEYR = FLASH_OPT_KEY2;
+ 914              		.loc 1 519 20 is_stmt 0 view .LVU235
+ 915 000a 054B     		ldr	r3, .L65
+ 916 000c 054A     		ldr	r2, .L65+4
+ 917 000e 9A60     		str	r2, [r3, #8]
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 918              		.loc 1 520 5 is_stmt 1 view .LVU236
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 919              		.loc 1 520 20 is_stmt 0 view .LVU237
+ 920 0010 02F14432 		add	r2, r2, #1145324612
+ 921 0014 9A60     		str	r2, [r3, #8]
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 922              		.loc 1 527 3 is_stmt 1 view .LVU238
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 923              		.loc 1 527 10 is_stmt 0 view .LVU239
+ARM GAS  /tmp/ccSYetfS.s 			page 49
+
+
+ 924 0016 0020     		movs	r0, #0
+ 925 0018 7047     		bx	lr
+ 926              	.L64:
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }  
+ 927              		.loc 1 524 12 view .LVU240
+ 928 001a 0120     		movs	r0, #1
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 929              		.loc 1 528 1 view .LVU241
+ 930 001c 7047     		bx	lr
+ 931              	.L66:
+ 932 001e 00BF     		.align	2
+ 933              	.L65:
+ 934 0020 003C0240 		.word	1073888256
+ 935 0024 3B2A1908 		.word	135866939
+ 936              		.cfi_endproc
+ 937              	.LFE148:
+ 939              		.section	.text.HAL_FLASH_OB_Lock,"ax",%progbits
+ 940              		.align	1
+ 941              		.global	HAL_FLASH_OB_Lock
+ 942              		.syntax unified
+ 943              		.thumb
+ 944              		.thumb_func
+ 945              		.fpu fpv5-d16
+ 947              	HAL_FLASH_OB_Lock:
+ 948              	.LFB149:
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+ 949              		.loc 1 535 1 is_stmt 1 view -0
+ 950              		.cfi_startproc
+ 951              		@ args = 0, pretend = 0, frame = 0
+ 952              		@ frame_needed = 0, uses_anonymous_args = 0
+ 953              		@ link register save eliminated.
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 954              		.loc 1 537 3 view .LVU243
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 955              		.loc 1 537 16 is_stmt 0 view .LVU244
+ 956 0000 034A     		ldr	r2, .L68
+ 957 0002 5369     		ldr	r3, [r2, #20]
+ 958 0004 43F00103 		orr	r3, r3, #1
+ 959 0008 5361     		str	r3, [r2, #20]
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 960              		.loc 1 539 3 is_stmt 1 view .LVU245
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 961              		.loc 1 540 1 is_stmt 0 view .LVU246
+ 962 000a 0020     		movs	r0, #0
+ 963 000c 7047     		bx	lr
+ 964              	.L69:
+ 965 000e 00BF     		.align	2
+ 966              	.L68:
+ 967 0010 003C0240 		.word	1073888256
+ 968              		.cfi_endproc
+ 969              	.LFE149:
+ 971              		.section	.text.HAL_FLASH_GetError,"ax",%progbits
+ 972              		.align	1
+ 973              		.global	HAL_FLASH_GetError
+ 974              		.syntax unified
+ 975              		.thumb
+ 976              		.thumb_func
+ARM GAS  /tmp/ccSYetfS.s 			page 50
+
+
+ 977              		.fpu fpv5-d16
+ 979              	HAL_FLASH_GetError:
+ 980              	.LFB151:
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****    return pFlash.ErrorCode;
+ 981              		.loc 1 583 1 is_stmt 1 view -0
+ 982              		.cfi_startproc
+ 983              		@ args = 0, pretend = 0, frame = 0
+ 984              		@ frame_needed = 0, uses_anonymous_args = 0
+ 985              		@ link register save eliminated.
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }  
+ 986              		.loc 1 584 4 view .LVU248
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }  
+ 987              		.loc 1 584 17 is_stmt 0 view .LVU249
+ 988 0000 014B     		ldr	r3, .L71
+ 989 0002 9869     		ldr	r0, [r3, #24]
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 990              		.loc 1 585 1 view .LVU250
+ 991 0004 7047     		bx	lr
+ 992              	.L72:
+ 993 0006 00BF     		.align	2
+ 994              	.L71:
+ 995 0008 00000000 		.word	.LANCHOR0
+ 996              		.cfi_endproc
+ 997              	.LFE151:
+ 999              		.section	.text.FLASH_WaitForLastOperation,"ax",%progbits
+ 1000              		.align	1
+ 1001              		.global	FLASH_WaitForLastOperation
+ 1002              		.syntax unified
+ 1003              		.thumb
+ 1004              		.thumb_func
+ 1005              		.fpu fpv5-d16
+ 1007              	FLASH_WaitForLastOperation:
+ 1008              	.LVL42:
+ 1009              	.LFB152:
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   uint32_t tickstart = 0;
+ 1010              		.loc 1 597 1 is_stmt 1 view -0
+ 1011              		.cfi_startproc
+ 1012              		@ args = 0, pretend = 0, frame = 0
+ 1013              		@ frame_needed = 0, uses_anonymous_args = 0
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   uint32_t tickstart = 0;
+ 1014              		.loc 1 597 1 is_stmt 0 view .LVU252
+ 1015 0000 38B5     		push	{r3, r4, r5, lr}
+ 1016              	.LCFI4:
+ 1017              		.cfi_def_cfa_offset 16
+ 1018              		.cfi_offset 3, -16
+ 1019              		.cfi_offset 4, -12
+ 1020              		.cfi_offset 5, -8
+ 1021              		.cfi_offset 14, -4
+ 1022 0002 0446     		mov	r4, r0
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 1023              		.loc 1 598 3 is_stmt 1 view .LVU253
+ 1024              	.LVL43:
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 1025              		.loc 1 601 3 view .LVU254
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 1026              		.loc 1 601 20 is_stmt 0 view .LVU255
+ 1027 0004 154B     		ldr	r3, .L84
+ARM GAS  /tmp/ccSYetfS.s 			page 51
+
+
+ 1028 0006 0022     		movs	r2, #0
+ 1029 0008 9A61     		str	r2, [r3, #24]
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1030              		.loc 1 607 3 is_stmt 1 view .LVU256
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1031              		.loc 1 607 15 is_stmt 0 view .LVU257
+ 1032 000a FFF7FEFF 		bl	HAL_GetTick
+ 1033              	.LVL44:
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1034              		.loc 1 607 15 view .LVU258
+ 1035 000e 0546     		mov	r5, r0
+ 1036              	.LVL45:
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   { 
+ 1037              		.loc 1 609 3 is_stmt 1 view .LVU259
+ 1038              	.L75:
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   { 
+ 1039              		.loc 1 609 8 view .LVU260
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   { 
+ 1040              		.loc 1 609 9 is_stmt 0 view .LVU261
+ 1041 0010 134B     		ldr	r3, .L84+4
+ 1042 0012 DB68     		ldr	r3, [r3, #12]
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   { 
+ 1043              		.loc 1 609 8 view .LVU262
+ 1044 0014 13F4803F 		tst	r3, #65536
+ 1045 0018 0AD0     		beq	.L82
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 1046              		.loc 1 611 5 is_stmt 1 view .LVU263
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 1047              		.loc 1 611 7 is_stmt 0 view .LVU264
+ 1048 001a B4F1FF3F 		cmp	r4, #-1
+ 1049 001e F7D0     		beq	.L75
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 1050              		.loc 1 613 7 is_stmt 1 view .LVU265
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 1051              		.loc 1 613 9 is_stmt 0 view .LVU266
+ 1052 0020 24B1     		cbz	r4, .L76
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 1053              		.loc 1 613 28 discriminator 1 view .LVU267
+ 1054 0022 FFF7FEFF 		bl	HAL_GetTick
+ 1055              	.LVL46:
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 1056              		.loc 1 613 42 discriminator 1 view .LVU268
+ 1057 0026 401B     		subs	r0, r0, r5
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       {
+ 1058              		.loc 1 613 24 discriminator 1 view .LVU269
+ 1059 0028 A042     		cmp	r0, r4
+ 1060 002a F1D9     		bls	.L75
+ 1061              	.L76:
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 1062              		.loc 1 615 9 is_stmt 1 view .LVU270
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 1063              		.loc 1 615 16 is_stmt 0 view .LVU271
+ 1064 002c 0320     		movs	r0, #3
+ 1065 002e 0DE0     		b	.L77
+ 1066              	.L82:
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 1067              		.loc 1 620 3 is_stmt 1 view .LVU272
+ARM GAS  /tmp/ccSYetfS.s 			page 52
+
+
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 1068              		.loc 1 620 6 is_stmt 0 view .LVU273
+ 1069 0030 0B4B     		ldr	r3, .L84+4
+ 1070 0032 DB68     		ldr	r3, [r3, #12]
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 1071              		.loc 1 620 5 view .LVU274
+ 1072 0034 13F0F20F 		tst	r3, #242
+ 1073 0038 09D1     		bne	.L83
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 1074              		.loc 1 628 3 is_stmt 1 view .LVU275
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 1075              		.loc 1 628 7 is_stmt 0 view .LVU276
+ 1076 003a 094B     		ldr	r3, .L84+4
+ 1077 003c DB68     		ldr	r3, [r3, #12]
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 1078              		.loc 1 628 6 view .LVU277
+ 1079 003e 13F0010F 		tst	r3, #1
+ 1080 0042 08D0     		beq	.L80
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 1081              		.loc 1 631 5 is_stmt 1 view .LVU278
+ 1082 0044 064B     		ldr	r3, .L84+4
+ 1083 0046 0122     		movs	r2, #1
+ 1084 0048 DA60     		str	r2, [r3, #12]
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 1085              		.loc 1 635 10 is_stmt 0 view .LVU279
+ 1086 004a 0020     		movs	r0, #0
+ 1087              	.L77:
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1088              		.loc 1 637 1 view .LVU280
+ 1089 004c 38BD     		pop	{r3, r4, r5, pc}
+ 1090              	.LVL47:
+ 1091              	.L83:
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     return HAL_ERROR;
+ 1092              		.loc 1 623 5 is_stmt 1 view .LVU281
+ 1093 004e FFF7FEFF 		bl	FLASH_SetErrorCode
+ 1094              	.LVL48:
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 1095              		.loc 1 624 5 view .LVU282
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 1096              		.loc 1 624 12 is_stmt 0 view .LVU283
+ 1097 0052 0120     		movs	r0, #1
+ 1098 0054 FAE7     		b	.L77
+ 1099              	.L80:
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 1100              		.loc 1 635 10 view .LVU284
+ 1101 0056 0020     		movs	r0, #0
+ 1102 0058 F8E7     		b	.L77
+ 1103              	.L85:
+ 1104 005a 00BF     		.align	2
+ 1105              	.L84:
+ 1106 005c 00000000 		.word	.LANCHOR0
+ 1107 0060 003C0240 		.word	1073888256
+ 1108              		.cfi_endproc
+ 1109              	.LFE152:
+ 1111              		.section	.text.HAL_FLASH_Program,"ax",%progbits
+ 1112              		.align	1
+ 1113              		.global	HAL_FLASH_Program
+ARM GAS  /tmp/ccSYetfS.s 			page 53
+
+
+ 1114              		.syntax unified
+ 1115              		.thumb
+ 1116              		.thumb_func
+ 1117              		.fpu fpv5-d16
+ 1119              	HAL_FLASH_Program:
+ 1120              	.LVL49:
+ 1121              	.LFB141:
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 1122              		.loc 1 163 1 is_stmt 1 view -0
+ 1123              		.cfi_startproc
+ 1124              		@ args = 0, pretend = 0, frame = 0
+ 1125              		@ frame_needed = 0, uses_anonymous_args = 0
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 1126              		.loc 1 163 1 is_stmt 0 view .LVU286
+ 1127 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 1128              	.LCFI5:
+ 1129              		.cfi_def_cfa_offset 24
+ 1130              		.cfi_offset 3, -24
+ 1131              		.cfi_offset 4, -20
+ 1132              		.cfi_offset 5, -16
+ 1133              		.cfi_offset 6, -12
+ 1134              		.cfi_offset 7, -8
+ 1135              		.cfi_offset 14, -4
+ 1136 0002 1646     		mov	r6, r2
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 1137              		.loc 1 164 3 is_stmt 1 view .LVU287
+ 1138              	.LVL50:
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1139              		.loc 1 167 3 view .LVU288
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1140              		.loc 1 167 3 view .LVU289
+ 1141 0004 1B4A     		ldr	r2, .L97
+ 1142              	.LVL51:
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1143              		.loc 1 167 3 is_stmt 0 view .LVU290
+ 1144 0006 127D     		ldrb	r2, [r2, #20]	@ zero_extendqisi2
+ 1145 0008 012A     		cmp	r2, #1
+ 1146 000a 31D0     		beq	.L95
+ 1147 000c 0446     		mov	r4, r0
+ 1148 000e 0D46     		mov	r5, r1
+ 1149 0010 1F46     		mov	r7, r3
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1150              		.loc 1 167 3 is_stmt 1 discriminator 2 view .LVU291
+ 1151 0012 184B     		ldr	r3, .L97
+ 1152 0014 0122     		movs	r2, #1
+ 1153 0016 1A75     		strb	r2, [r3, #20]
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1154              		.loc 1 167 3 discriminator 2 view .LVU292
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1155              		.loc 1 170 3 discriminator 2 view .LVU293
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 1156              		.loc 1 173 3 discriminator 2 view .LVU294
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ 1157              		.loc 1 173 12 is_stmt 0 discriminator 2 view .LVU295
+ 1158 0018 4CF25030 		movw	r0, #50000
+ 1159              	.LVL52:
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   
+ARM GAS  /tmp/ccSYetfS.s 			page 54
+
+
+ 1160              		.loc 1 173 12 discriminator 2 view .LVU296
+ 1161 001c FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1162              	.LVL53:
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 1163              		.loc 1 175 3 is_stmt 1 discriminator 2 view .LVU297
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   {
+ 1164              		.loc 1 175 5 is_stmt 0 discriminator 2 view .LVU298
+ 1165 0020 90B9     		cbnz	r0, .L88
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     {
+ 1166              		.loc 1 177 5 is_stmt 1 view .LVU299
+ 1167 0022 032C     		cmp	r4, #3
+ 1168 0024 07D8     		bhi	.L89
+ 1169 0026 DFE804F0 		tbb	[pc, r4]
+ 1170              	.L91:
+ 1171 002a 02       		.byte	(.L94-.L91)/2
+ 1172 002b 13       		.byte	(.L93-.L91)/2
+ 1173 002c 18       		.byte	(.L92-.L91)/2
+ 1174 002d 1D       		.byte	(.L90-.L91)/2
+ 1175              		.p2align 1
+ 1176              	.L94:
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 1177              		.loc 1 182 9 view .LVU300
+ 1178 002e F1B2     		uxtb	r1, r6
+ 1179 0030 2846     		mov	r0, r5
+ 1180              	.LVL54:
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 1181              		.loc 1 182 9 is_stmt 0 view .LVU301
+ 1182 0032 FFF7FEFF 		bl	FLASH_Program_Byte
+ 1183              	.LVL55:
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 1184              		.loc 1 183 9 is_stmt 1 view .LVU302
+ 1185              	.L89:
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     
+ 1186              		.loc 1 210 5 view .LVU303
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****     
+ 1187              		.loc 1 210 14 is_stmt 0 view .LVU304
+ 1188 0036 4CF25030 		movw	r0, #50000
+ 1189 003a FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1190              	.LVL56:
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 1191              		.loc 1 213 5 is_stmt 1 view .LVU305
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   }
+ 1192              		.loc 1 213 15 is_stmt 0 view .LVU306
+ 1193 003e 0E4A     		ldr	r2, .L97+4
+ 1194 0040 1369     		ldr	r3, [r2, #16]
+ 1195 0042 23F00103 		bic	r3, r3, #1
+ 1196 0046 1361     		str	r3, [r2, #16]
+ 1197              	.L88:
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1198              		.loc 1 217 3 is_stmt 1 view .LVU307
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1199              		.loc 1 217 3 view .LVU308
+ 1200 0048 0A4B     		ldr	r3, .L97
+ 1201 004a 0022     		movs	r2, #0
+ 1202 004c 1A75     		strb	r2, [r3, #20]
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1203              		.loc 1 217 3 view .LVU309
+ARM GAS  /tmp/ccSYetfS.s 			page 55
+
+
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 1204              		.loc 1 219 3 view .LVU310
+ 1205              	.LVL57:
+ 1206              	.L87:
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1207              		.loc 1 220 1 is_stmt 0 view .LVU311
+ 1208 004e F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 1209              	.LVL58:
+ 1210              	.L93:
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 1211              		.loc 1 189 9 is_stmt 1 view .LVU312
+ 1212 0050 B1B2     		uxth	r1, r6
+ 1213 0052 2846     		mov	r0, r5
+ 1214              	.LVL59:
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 1215              		.loc 1 189 9 is_stmt 0 view .LVU313
+ 1216 0054 FFF7FEFF 		bl	FLASH_Program_HalfWord
+ 1217              	.LVL60:
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 1218              		.loc 1 190 9 is_stmt 1 view .LVU314
+ 1219 0058 EDE7     		b	.L89
+ 1220              	.LVL61:
+ 1221              	.L92:
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 1222              		.loc 1 196 9 view .LVU315
+ 1223 005a 3146     		mov	r1, r6
+ 1224 005c 2846     		mov	r0, r5
+ 1225              	.LVL62:
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 1226              		.loc 1 196 9 is_stmt 0 view .LVU316
+ 1227 005e FFF7FEFF 		bl	FLASH_Program_Word
+ 1228              	.LVL63:
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 1229              		.loc 1 197 9 is_stmt 1 view .LVU317
+ 1230 0062 E8E7     		b	.L89
+ 1231              	.LVL64:
+ 1232              	.L90:
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 1233              		.loc 1 203 9 view .LVU318
+ 1234 0064 3246     		mov	r2, r6
+ 1235 0066 3B46     		mov	r3, r7
+ 1236 0068 2846     		mov	r0, r5
+ 1237              	.LVL65:
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****         break;
+ 1238              		.loc 1 203 9 is_stmt 0 view .LVU319
+ 1239 006a FFF7FEFF 		bl	FLASH_Program_DoubleWord
+ 1240              	.LVL66:
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****       }
+ 1241              		.loc 1 204 9 is_stmt 1 view .LVU320
+ 1242 006e E2E7     		b	.L89
+ 1243              	.LVL67:
+ 1244              	.L95:
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1245              		.loc 1 167 3 is_stmt 0 view .LVU321
+ 1246 0070 0220     		movs	r0, #2
+ 1247              	.LVL68:
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ARM GAS  /tmp/ccSYetfS.s 			page 56
+
+
+ 1248              		.loc 1 167 3 view .LVU322
+ 1249 0072 ECE7     		b	.L87
+ 1250              	.L98:
+ 1251              		.align	2
+ 1252              	.L97:
+ 1253 0074 00000000 		.word	.LANCHOR0
+ 1254 0078 003C0240 		.word	1073888256
+ 1255              		.cfi_endproc
+ 1256              	.LFE141:
+ 1258              		.section	.text.HAL_FLASH_OB_Launch,"ax",%progbits
+ 1259              		.align	1
+ 1260              		.global	HAL_FLASH_OB_Launch
+ 1261              		.syntax unified
+ 1262              		.thumb
+ 1263              		.thumb_func
+ 1264              		.fpu fpv5-d16
+ 1266              	HAL_FLASH_OB_Launch:
+ 1267              	.LFB150:
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c ****   /* Set the OPTSTRT bit in OPTCR register */
+ 1268              		.loc 1 547 1 is_stmt 1 view -0
+ 1269              		.cfi_startproc
+ 1270              		@ args = 0, pretend = 0, frame = 0
+ 1271              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1272 0000 08B5     		push	{r3, lr}
+ 1273              	.LCFI6:
+ 1274              		.cfi_def_cfa_offset 8
+ 1275              		.cfi_offset 3, -8
+ 1276              		.cfi_offset 14, -4
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1277              		.loc 1 549 3 view .LVU324
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1278              		.loc 1 549 16 is_stmt 0 view .LVU325
+ 1279 0002 054A     		ldr	r2, .L101
+ 1280 0004 5369     		ldr	r3, [r2, #20]
+ 1281 0006 43F00203 		orr	r3, r3, #2
+ 1282 000a 5361     		str	r3, [r2, #20]
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 1283              		.loc 1 552 3 is_stmt 1 view .LVU326
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** }
+ 1284              		.loc 1 552 10 is_stmt 0 view .LVU327
+ 1285 000c 4CF25030 		movw	r0, #50000
+ 1286 0010 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1287              	.LVL69:
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** 
+ 1288              		.loc 1 553 1 view .LVU328
+ 1289 0014 08BD     		pop	{r3, pc}
+ 1290              	.L102:
+ 1291 0016 00BF     		.align	2
+ 1292              	.L101:
+ 1293 0018 003C0240 		.word	1073888256
+ 1294              		.cfi_endproc
+ 1295              	.LFE150:
+ 1297              		.global	pFlash
+ 1298              		.section	.bss.pFlash,"aw",%nobits
+ 1299              		.align	2
+ 1300              		.set	.LANCHOR0,. + 0
+ 1303              	pFlash:
+ARM GAS  /tmp/ccSYetfS.s 			page 57
+
+
+ 1304 0000 00000000 		.space	28
+ 1304      00000000 
+ 1304      00000000 
+ 1304      00000000 
+ 1304      00000000 
+ 1305              		.text
+ 1306              	.Letext0:
+ 1307              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 1308              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 1309              		.file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 1310              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 1311              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h"
+ 1312              		.file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ 1313              		.file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h"
+ARM GAS  /tmp/ccSYetfS.s 			page 58
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_flash.c
+     /tmp/ccSYetfS.s:17     .text.FLASH_Program_DoubleWord:0000000000000000 $t
+     /tmp/ccSYetfS.s:24     .text.FLASH_Program_DoubleWord:0000000000000000 FLASH_Program_DoubleWord
+     /tmp/ccSYetfS.s:99     .text.FLASH_Program_DoubleWord:0000000000000030 $d
+     /tmp/ccSYetfS.s:104    .text.FLASH_Program_Word:0000000000000000 $t
+     /tmp/ccSYetfS.s:110    .text.FLASH_Program_Word:0000000000000000 FLASH_Program_Word
+     /tmp/ccSYetfS.s:157    .text.FLASH_Program_Word:0000000000000024 $d
+     /tmp/ccSYetfS.s:162    .text.FLASH_Program_HalfWord:0000000000000000 $t
+     /tmp/ccSYetfS.s:168    .text.FLASH_Program_HalfWord:0000000000000000 FLASH_Program_HalfWord
+     /tmp/ccSYetfS.s:215    .text.FLASH_Program_HalfWord:0000000000000024 $d
+     /tmp/ccSYetfS.s:220    .text.FLASH_Program_Byte:0000000000000000 $t
+     /tmp/ccSYetfS.s:226    .text.FLASH_Program_Byte:0000000000000000 FLASH_Program_Byte
+     /tmp/ccSYetfS.s:272    .text.FLASH_Program_Byte:0000000000000020 $d
+     /tmp/ccSYetfS.s:277    .text.FLASH_SetErrorCode:0000000000000000 $t
+     /tmp/ccSYetfS.s:283    .text.FLASH_SetErrorCode:0000000000000000 FLASH_SetErrorCode
+     /tmp/ccSYetfS.s:369    .text.FLASH_SetErrorCode:000000000000006c $d
+     /tmp/ccSYetfS.s:375    .text.HAL_FLASH_Program_IT:0000000000000000 $t
+     /tmp/ccSYetfS.s:382    .text.HAL_FLASH_Program_IT:0000000000000000 HAL_FLASH_Program_IT
+     /tmp/ccSYetfS.s:440    .text.HAL_FLASH_Program_IT:000000000000003a $d
+     /tmp/ccSYetfS.s:444    .text.HAL_FLASH_Program_IT:000000000000003e $t
+     /tmp/ccSYetfS.s:505    .text.HAL_FLASH_Program_IT:000000000000006c $d
+     /tmp/ccSYetfS.s:511    .text.HAL_FLASH_EndOfOperationCallback:0000000000000000 $t
+     /tmp/ccSYetfS.s:518    .text.HAL_FLASH_EndOfOperationCallback:0000000000000000 HAL_FLASH_EndOfOperationCallback
+     /tmp/ccSYetfS.s:533    .text.HAL_FLASH_OperationErrorCallback:0000000000000000 $t
+     /tmp/ccSYetfS.s:540    .text.HAL_FLASH_OperationErrorCallback:0000000000000000 HAL_FLASH_OperationErrorCallback
+     /tmp/ccSYetfS.s:555    .text.HAL_FLASH_IRQHandler:0000000000000000 $t
+     /tmp/ccSYetfS.s:562    .text.HAL_FLASH_IRQHandler:0000000000000000 HAL_FLASH_IRQHandler
+     /tmp/ccSYetfS.s:794    .text.HAL_FLASH_IRQHandler:0000000000000100 $d
+     /tmp/ccSYetfS.s:801    .text.HAL_FLASH_Unlock:0000000000000000 $t
+     /tmp/ccSYetfS.s:808    .text.HAL_FLASH_Unlock:0000000000000000 HAL_FLASH_Unlock
+     /tmp/ccSYetfS.s:854    .text.HAL_FLASH_Unlock:0000000000000028 $d
+     /tmp/ccSYetfS.s:860    .text.HAL_FLASH_Lock:0000000000000000 $t
+     /tmp/ccSYetfS.s:867    .text.HAL_FLASH_Lock:0000000000000000 HAL_FLASH_Lock
+     /tmp/ccSYetfS.s:887    .text.HAL_FLASH_Lock:0000000000000010 $d
+     /tmp/ccSYetfS.s:892    .text.HAL_FLASH_OB_Unlock:0000000000000000 $t
+     /tmp/ccSYetfS.s:899    .text.HAL_FLASH_OB_Unlock:0000000000000000 HAL_FLASH_OB_Unlock
+     /tmp/ccSYetfS.s:934    .text.HAL_FLASH_OB_Unlock:0000000000000020 $d
+     /tmp/ccSYetfS.s:940    .text.HAL_FLASH_OB_Lock:0000000000000000 $t
+     /tmp/ccSYetfS.s:947    .text.HAL_FLASH_OB_Lock:0000000000000000 HAL_FLASH_OB_Lock
+     /tmp/ccSYetfS.s:967    .text.HAL_FLASH_OB_Lock:0000000000000010 $d
+     /tmp/ccSYetfS.s:972    .text.HAL_FLASH_GetError:0000000000000000 $t
+     /tmp/ccSYetfS.s:979    .text.HAL_FLASH_GetError:0000000000000000 HAL_FLASH_GetError
+     /tmp/ccSYetfS.s:995    .text.HAL_FLASH_GetError:0000000000000008 $d
+     /tmp/ccSYetfS.s:1000   .text.FLASH_WaitForLastOperation:0000000000000000 $t
+     /tmp/ccSYetfS.s:1007   .text.FLASH_WaitForLastOperation:0000000000000000 FLASH_WaitForLastOperation
+     /tmp/ccSYetfS.s:1106   .text.FLASH_WaitForLastOperation:000000000000005c $d
+     /tmp/ccSYetfS.s:1112   .text.HAL_FLASH_Program:0000000000000000 $t
+     /tmp/ccSYetfS.s:1119   .text.HAL_FLASH_Program:0000000000000000 HAL_FLASH_Program
+     /tmp/ccSYetfS.s:1171   .text.HAL_FLASH_Program:000000000000002a $d
+     /tmp/ccSYetfS.s:1175   .text.HAL_FLASH_Program:000000000000002e $t
+     /tmp/ccSYetfS.s:1253   .text.HAL_FLASH_Program:0000000000000074 $d
+     /tmp/ccSYetfS.s:1259   .text.HAL_FLASH_OB_Launch:0000000000000000 $t
+     /tmp/ccSYetfS.s:1266   .text.HAL_FLASH_OB_Launch:0000000000000000 HAL_FLASH_OB_Launch
+     /tmp/ccSYetfS.s:1293   .text.HAL_FLASH_OB_Launch:0000000000000018 $d
+     /tmp/ccSYetfS.s:1303   .bss.pFlash:0000000000000000 pFlash
+     /tmp/ccSYetfS.s:1299   .bss.pFlash:0000000000000000 $d
+ARM GAS  /tmp/ccSYetfS.s 			page 59
+
+
+
+UNDEFINED SYMBOLS
+FLASH_Erase_Sector
+HAL_GetTick
diff --git a/build/stm32f7xx_hal_flash.o b/build/stm32f7xx_hal_flash.o
new file mode 100644
index 0000000..7600b33
Binary files /dev/null and b/build/stm32f7xx_hal_flash.o differ
diff --git a/build/stm32f7xx_hal_flash_ex.d b/build/stm32f7xx_hal_flash_ex.d
new file mode 100644
index 0000000..7f140b7
--- /dev/null
+++ b/build/stm32f7xx_hal_flash_ex.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_flash_ex.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_flash_ex.lst b/build/stm32f7xx_hal_flash_ex.lst
new file mode 100644
index 0000000..c7146e5
--- /dev/null
+++ b/build/stm32f7xx_hal_flash_ex.lst
@@ -0,0 +1,3765 @@
+ARM GAS  /tmp/cctoWaKX.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_flash_ex.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.FLASH_MassErase,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	FLASH_MassErase:
+  25              	.LVL0:
+  26              	.LFB145:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @file    stm32f7xx_hal_flash_ex.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief   Extended FLASH HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This file provides firmware functions to manage the following 
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          functionalities of the FLASH extension peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *           + Extended programming operations functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *  
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   @verbatim
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   ==============================================================================
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                    ##### Flash Extension features #####
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   ==============================================================================
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****            
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx 
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****        devices contains the following additional features 
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****        
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****        (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****            capability (RWW)
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****        (+) Dual bank memory organization       
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****        (+) Dual boot mode
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****    
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                       ##### How to use this driver #####
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   ==============================================================================
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   [..] This driver provides functions to configure and program the FLASH memory 
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****        of all STM32F7xx devices. It includes
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       (#) FLASH Memory Erase functions: 
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                 HAL_FLASH_Lock() functions
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****            (++) Erase function: Erase sector, erase all sectors
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****            (++) There are two modes of erase :
+ARM GAS  /tmp/cctoWaKX.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****              (+++) Polling Mode using HAL_FLASHEx_Erase()
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****              (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****              
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****            (++) Set/Reset the write protection
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****            (++) Set the Read protection Level
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****            (++) Set the BOR level
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****            (++) Program the user Option Bytes
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   @endverbatim
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   ******************************************************************************
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @attention
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * Copyright (c) 2017 STMicroelectronics.
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * All rights reserved.
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * the root directory of this software component.
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   ******************************************************************************
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */ 
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Includes ------------------------------------------------------------------*/
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #include "stm32f7xx_hal.h"
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @{
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @defgroup FLASHEx FLASHEx
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief FLASH HAL Extension module driver
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @{
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #ifdef HAL_FLASH_MODULE_ENABLED
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Private define ------------------------------------------------------------*/
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Constants
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @{
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */    
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #define SECTOR_MASK               0xFFFFFF07U
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #define FLASH_TIMEOUT_VALUE       50000U/* 50 s */
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @}
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Private macro -------------------------------------------------------------*/
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Private variables ---------------------------------------------------------*/
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Variables
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @{
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */    
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** extern FLASH_ProcessTypeDef pFlash;
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @}
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ARM GAS  /tmp/cctoWaKX.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Private function prototypes -----------------------------------------------*/
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Functions
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @{
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Option bytes control */
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector);
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector);
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef  FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t           FLASH_OB_GetUser(void);
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t           FLASH_OB_GetWRP(void);
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint8_t            FLASH_OB_GetRDP(void);
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t           FLASH_OB_GetBOR(void);
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t           FLASH_OB_GetBootAddress(uint32_t BootOption);
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK)
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                               uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static void               FLASH_MassErase(uint8_t VoltageRange);
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR_nDBANK */
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR2_PCROP)
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef  FLASH_OB_PCROP_Config(uint32_t PCROPSector);
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef  FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp);
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t           FLASH_OB_GetPCROP(void);
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t           FLASH_OB_GetPCROPRDP(void);
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR2_PCROP */
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** extern HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @}
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Exported functions --------------------------------------------------------*/
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @{
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****  *  @brief   Extended IO operation functions 
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****  *
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** @verbatim   
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****  ===============================================================================
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                 ##### Extended programming operation functions #####
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****  ===============================================================================  
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     [..]
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     This subsection provides a set of functions allowing to manage the Extension FLASH 
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     programming operations Operations.
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** @endverbatim
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @{
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ARM GAS  /tmp/cctoWaKX.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Perform a mass erase or erase the specified FLASH memory sectors 
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         contains the configuration information for the erasing.
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * 
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param[out]  SectorError pointer to variable  that
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         contains the configuration information on faulty sector in case of error 
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         (0xFFFFFFFF means that all the sectors have been correctly erased)
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * 
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL Status
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t index = 0;
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Process Locked */
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __HAL_LOCK(&pFlash);
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(status == HAL_OK)
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /*Initialization of SectorError variable*/
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     *SectorError = 0xFFFFFFFFU;
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       /*Mass erase to be done*/
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK)      
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);      
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR_nDBANK */
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                       
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       /* Wait for last operation to be completed */
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       /* if the erase operation is completed, disable the MER Bit */
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       FLASH->CR &= (~FLASH_MER_BIT);
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     else
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       /* Check the parameters */
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       /* Erase by sector by sector to be done*/
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       {
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         /* Wait for last operation to be completed */
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ARM GAS  /tmp/cctoWaKX.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         /* If the erase operation is completed, disable the SER Bit and SNB Bits */
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); 
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         if(status != HAL_OK) 
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         {
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****           /* In case of error, stop erase procedure and return the faulty sector*/
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****           *SectorError = index;
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****           break;
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         }
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       }
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Process Unlocked */
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __HAL_UNLOCK(&pFlash);
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return status;
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enable
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         contains the configuration information for the erasing.
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * 
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL Status
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Process Locked */
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __HAL_LOCK(&pFlash);
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Enable End of FLASH Operation interrupt */
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Enable Error source interrupt */
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Clear pending flags (if any) */  
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                          FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);  
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /*Mass erase to be done*/
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK)    
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);      
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR_nDBANK */    
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else
+ARM GAS  /tmp/cctoWaKX.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /* Erase by sector to be done*/
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /* Check the parameters */
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.Sector = pEraseInit->Sector;
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /*Erase 1st sector and wait for IT*/
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return status;
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Program option bytes
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         contains the configuration information for the programming.
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * 
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL Status
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Process Locked */
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __HAL_LOCK(&pFlash);
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Write protection configuration */
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     assert_param(IS_WRPSTATE(pOBInit->WRPState));
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       /*Enable of Write protection on the selected Sector*/
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       status = FLASH_OB_EnableWRP(pOBInit->WRPSector);
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     else
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       /*Disable of Write protection on the selected Sector*/
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       status = FLASH_OB_DisableWRP(pOBInit->WRPSector);
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Read protection configuration */
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ARM GAS  /tmp/cctoWaKX.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* USER  configuration */
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK)
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, 
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_IWDG_SW,
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_STOP_NO_RST,
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_STDBY_NO_RST, 
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, 
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_IWDG_SW,
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_STOP_NO_RST,
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_STDBY_NO_RST, 
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);    
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR_nDBANK */
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* BOR Level  configuration */
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Boot 0 Address configuration */
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Boot 1 Address configuration */
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR2_PCROP)
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* PCROP configuration */
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector);
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* PCROP_RDP configuration */
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP)
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp);
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR2_PCROP */
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Process Unlocked */
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __HAL_UNLOCK(&pFlash);
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ARM GAS  /tmp/cctoWaKX.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return status;
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Get the Option byte configuration
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         contains the configuration information for the programming.
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * 
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval None
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 	                OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /*Get WRP*/
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   pOBInit->WRPSector = FLASH_OB_GetWRP();
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /*Get RDP Level*/
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   pOBInit->RDPLevel = FLASH_OB_GetRDP();
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /*Get USER*/
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   pOBInit->USERConfig = FLASH_OB_GetUser();
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /*Get BOR Level*/
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   pOBInit->BORLevel = FLASH_OB_GetBOR();
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /*Get Boot Address when Boot pin = 0 */
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /*Get Boot Address when Boot pin = 1 */
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR2_PCROP)
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /*Get PCROP Sectors */
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   pOBInit->PCROPSector = FLASH_OB_GetPCROP();
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /*Get PCROP_RDP Value */
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP();
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR2_PCROP */
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @}
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK)
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Full erase of FLASH memory sectors 
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  VoltageRange The device voltage range which defines the erase parallelism.  
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by byte (8-bit) 
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by half word (16-bit)
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by word (32-bit)
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+ARM GAS  /tmp/cctoWaKX.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by double word (64-bit)
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Banks Banks to be erased
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_1: Bank1 to be erased
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_2: Bank2 to be erased
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL Status
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+  28              		.loc 1 441 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_VOLTAGERANGE(VoltageRange));
+  33              		.loc 1 443 3 view .LVU1
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_FLASH_BANK(Banks));
+  34              		.loc 1 444 3 view .LVU2
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* if the previous operation is completed, proceed to erase all sectors */
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR &= CR_PSIZE_MASK;
+  35              		.loc 1 447 3 view .LVU3
+  36              		.loc 1 447 13 is_stmt 0 view .LVU4
+  37 0000 114A     		ldr	r2, .L7
+  38 0002 1369     		ldr	r3, [r2, #16]
+  39 0004 23F44073 		bic	r3, r3, #768
+  40 0008 1361     		str	r3, [r2, #16]
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(Banks == FLASH_BANK_BOTH)
+  41              		.loc 1 448 3 is_stmt 1 view .LVU5
+  42              		.loc 1 448 5 is_stmt 0 view .LVU6
+  43 000a 0329     		cmp	r1, #3
+  44 000c 10D0     		beq	.L5
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /* bank1 & bank2 will be erased*/
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     FLASH->CR |= FLASH_MER_BIT;
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else if(Banks == FLASH_BANK_2)
+  45              		.loc 1 453 8 is_stmt 1 view .LVU7
+  46              		.loc 1 453 10 is_stmt 0 view .LVU8
+  47 000e 0229     		cmp	r1, #2
+  48 0010 14D0     		beq	.L6
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /*Only bank2 will be erased*/
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     FLASH->CR |= FLASH_CR_MER2;
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /*Only bank1 will be erased*/
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     FLASH->CR |= FLASH_CR_MER1;    
+  49              		.loc 1 461 5 is_stmt 1 view .LVU9
+  50              		.loc 1 461 15 is_stmt 0 view .LVU10
+  51 0012 0D4A     		ldr	r2, .L7
+  52 0014 1369     		ldr	r3, [r2, #16]
+  53 0016 43F00403 		orr	r3, r3, #4
+ARM GAS  /tmp/cctoWaKX.s 			page 10
+
+
+  54 001a 1361     		str	r3, [r2, #16]
+  55              	.LVL1:
+  56              	.L3:
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
+  57              		.loc 1 463 3 is_stmt 1 view .LVU11
+  58              		.loc 1 463 13 is_stmt 0 view .LVU12
+  59 001c 0A4A     		ldr	r2, .L7
+  60 001e 1369     		ldr	r3, [r2, #16]
+  61 0020 43EA0020 		orr	r0, r3, r0, lsl #8
+  62              	.LVL2:
+  63              		.loc 1 463 13 view .LVU13
+  64 0024 40F48030 		orr	r0, r0, #65536
+  65 0028 1061     		str	r0, [r2, #16]
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Data synchronous Barrier (DSB) Just after the write operation
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****      This will force the CPU to respect the sequence of instruction (no optimization).*/
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __DSB();
+  66              		.loc 1 466 3 is_stmt 1 view .LVU14
+  67              	.LBB6:
+  68              	.LBI6:
+  69              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.0.4
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     09. April 2018
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+ARM GAS  /tmp/cctoWaKX.s 			page 11
+
+
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/cctoWaKX.s 			page 12
+
+
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/cctoWaKX.s 			page 13
+
+
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ARM GAS  /tmp/cctoWaKX.s 			page 14
+
+
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ARM GAS  /tmp/cctoWaKX.s 			page 15
+
+
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ARM GAS  /tmp/cctoWaKX.s 			page 16
+
+
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ARM GAS  /tmp/cctoWaKX.s 			page 17
+
+
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ARM GAS  /tmp/cctoWaKX.s 			page 18
+
+
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cctoWaKX.s 			page 19
+
+
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/cctoWaKX.s 			page 20
+
+
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/cctoWaKX.s 			page 21
+
+
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ARM GAS  /tmp/cctoWaKX.s 			page 22
+
+
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ARM GAS  /tmp/cctoWaKX.s 			page 23
+
+
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cctoWaKX.s 			page 24
+
+
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ARM GAS  /tmp/cctoWaKX.s 			page 25
+
+
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+  70              		.loc 2 877 27 view .LVU15
+  71              	.LBB7:
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+  72              		.loc 2 879 3 view .LVU16
+  73              		.syntax unified
+  74              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+  75 002a BFF34F8F 		dsb 0xF
+  76              	@ 0 "" 2
+  77              		.thumb
+  78              		.syntax unified
+  79              	.LBE7:
+  80              	.LBE6:
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ARM GAS  /tmp/cctoWaKX.s 			page 26
+
+
+  81              		.loc 1 467 1 is_stmt 0 view .LVU17
+  82 002e 7047     		bx	lr
+  83              	.LVL3:
+  84              	.L5:
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+  85              		.loc 1 451 5 is_stmt 1 view .LVU18
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+  86              		.loc 1 451 15 is_stmt 0 view .LVU19
+  87 0030 1169     		ldr	r1, [r2, #16]
+  88              	.LVL4:
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+  89              		.loc 1 451 15 view .LVU20
+  90 0032 48F20403 		movw	r3, #32772
+  91 0036 0B43     		orrs	r3, r3, r1
+  92 0038 1361     		str	r3, [r2, #16]
+  93 003a EFE7     		b	.L3
+  94              	.LVL5:
+  95              	.L6:
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+  96              		.loc 1 456 5 is_stmt 1 view .LVU21
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+  97              		.loc 1 456 15 is_stmt 0 view .LVU22
+  98 003c 024A     		ldr	r2, .L7
+  99 003e 1369     		ldr	r3, [r2, #16]
+ 100 0040 43F40043 		orr	r3, r3, #32768
+ 101 0044 1361     		str	r3, [r2, #16]
+ 102 0046 E9E7     		b	.L3
+ 103              	.L8:
+ 104              		.align	2
+ 105              	.L7:
+ 106 0048 003C0240 		.word	1073888256
+ 107              		.cfi_endproc
+ 108              	.LFE145:
+ 110              		.section	.text.FLASH_OB_GetWRP,"ax",%progbits
+ 111              		.align	1
+ 112              		.syntax unified
+ 113              		.thumb
+ 114              		.thumb_func
+ 115              		.fpu fpv5-d16
+ 117              	FLASH_OB_GetWRP:
+ 118              	.LFB147:
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Erase the specified FLASH memory sector
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Sector FLASH sector to erase
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         The value of this parameter depend on device used within the same series      
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  VoltageRange The device voltage range which defines the erase parallelism.  
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by byte (8-bit) 
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by half word (16-bit)
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by word (32-bit)
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by double word (64-bit)
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * 
+ARM GAS  /tmp/cctoWaKX.s 			page 27
+
+
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval None
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t tmp_psize = 0;
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_FLASH_SECTOR(Sector));
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_VOLTAGERANGE(VoltageRange));
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****      tmp_psize = FLASH_PSIZE_BYTE;
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     tmp_psize = FLASH_PSIZE_HALF_WORD;
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     tmp_psize = FLASH_PSIZE_WORD;
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(Sector > FLASH_SECTOR_11) 
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     Sector += 4;
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }  
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* If the previous operation is completed, proceed to erase the sector */
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR &= CR_PSIZE_MASK;
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= tmp_psize;
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= FLASH_CR_STRT;
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Data synchronous Barrier (DSB) Just after the write operation
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****      This will force the CPU to respect the sequence of instruction (no optimization).*/
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __DSB();
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Return the FLASH Write Protection Option Bytes value.
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval uint32_t FLASH Write Protection Option Bytes value
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP(void)
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 119              		.loc 1 534 1 is_stmt 1 view -0
+ 120              		.cfi_startproc
+ 121              		@ args = 0, pretend = 0, frame = 0
+ 122              		@ frame_needed = 0, uses_anonymous_args = 0
+ 123              		@ link register save eliminated.
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Return the FLASH write protection Register value */
+ARM GAS  /tmp/cctoWaKX.s 			page 28
+
+
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));
+ 124              		.loc 1 536 3 view .LVU24
+ 125              		.loc 1 536 27 is_stmt 0 view .LVU25
+ 126 0000 024B     		ldr	r3, .L10
+ 127 0002 5B69     		ldr	r3, [r3, #20]
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 128              		.loc 1 537 1 view .LVU26
+ 129 0004 0248     		ldr	r0, .L10+4
+ 130 0006 1840     		ands	r0, r0, r3
+ 131 0008 7047     		bx	lr
+ 132              	.L11:
+ 133 000a 00BF     		.align	2
+ 134              	.L10:
+ 135 000c 003C0240 		.word	1073888256
+ 136 0010 0000FF0F 		.word	268369920
+ 137              		.cfi_endproc
+ 138              	.LFE147:
+ 140              		.section	.text.FLASH_OB_GetUser,"ax",%progbits
+ 141              		.align	1
+ 142              		.syntax unified
+ 143              		.thumb
+ 144              		.thumb_func
+ 145              		.fpu fpv5-d16
+ 147              	FLASH_OB_GetUser:
+ 148              	.LFB149:
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Wwdg Selects the IWDG mode
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_WWDG_SW: Software WWDG selected
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_WWDG_HW: Hardware WWDG selected
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Iwdg Selects the WWDG mode
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_SW: Software IWDG selected
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_HW: Hardware IWDG selected
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Stop Reset event when entering STOP mode.
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter  can be one of the following values:
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_STOP_RST: Reset generated when entering in STOP
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Stdby Reset event when entering Standby mode.
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter  can be one of the following values:
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Iwdgstop Independent watchdog counter freeze in Stop mode.
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter  can be one of the following values:
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Iwdgstdby Independent watchdog counter freeze in standby mode.
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter  can be one of the following values:
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  NDBank Flash Single Bank mode enabled.
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter  can be one of the following values:
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mo
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  NDBoot Flash Dual boot mode disable.
+ARM GAS  /tmp/cctoWaKX.s 			page 29
+
+
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter  can be one of the following values:
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL Status
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t 
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                              uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t useroptionmask = 0x00;
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t useroptionvalue = 0x00;
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_WWDG_SOURCE(Wwdg));
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_IWDG_SOURCE(Iwdg));
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_STOP_SOURCE(Stop));
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_STDBY_SOURCE(Stdby));
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_NDBANK(NDBank));
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_NDBOOT(NDBoot));
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(status == HAL_OK)
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                       FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                       FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                       
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /* Update User Option Byte */               
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return status; 
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Return the FLASH User Option Byte value.
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetUser(void)
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 149              		.loc 1 618 1 is_stmt 1 view -0
+ 150              		.cfi_startproc
+ 151              		@ args = 0, pretend = 0, frame = 0
+ 152              		@ frame_needed = 0, uses_anonymous_args = 0
+ 153              		@ link register save eliminated.
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Return the User Option Byte */
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));
+ 154              		.loc 1 620 3 view .LVU28
+ARM GAS  /tmp/cctoWaKX.s 			page 30
+
+
+ 155              		.loc 1 620 27 is_stmt 0 view .LVU29
+ 156 0000 024B     		ldr	r3, .L13
+ 157 0002 5B69     		ldr	r3, [r3, #20]
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 158              		.loc 1 621 1 view .LVU30
+ 159 0004 0248     		ldr	r0, .L13+4
+ 160 0006 1840     		ands	r0, r0, r3
+ 161 0008 7047     		bx	lr
+ 162              	.L14:
+ 163 000a 00BF     		.align	2
+ 164              	.L13:
+ 165 000c 003C0240 		.word	1073888256
+ 166 0010 F00000F0 		.word	-268435216
+ 167              		.cfi_endproc
+ 168              	.LFE149:
+ 170              		.section	.text.FLASH_OB_BOR_LevelConfig,"ax",%progbits
+ 171              		.align	1
+ 172              		.syntax unified
+ 173              		.thumb
+ 174              		.thumb_func
+ 175              		.fpu fpv5-d16
+ 177              	FLASH_OB_BOR_LevelConfig:
+ 178              	.LVL6:
+ 179              	.LFB153:
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Full erase of FLASH memory sectors 
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  VoltageRange The device voltage range which defines the erase parallelism.  
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by byte (8-bit) 
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by half word (16-bit)
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by word (32-bit)
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by double word (64-bit)
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL Status
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static void FLASH_MassErase(uint8_t VoltageRange)
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_VOLTAGERANGE(VoltageRange));
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* if the previous operation is completed, proceed to erase all sectors */
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR &= CR_PSIZE_MASK;
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= FLASH_CR_MER;
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Data synchronous Barrier (DSB) Just after the write operation
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****      This will force the CPU to respect the sequence of instruction (no optimization).*/
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __DSB();
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Erase the specified FLASH memory sector
+ARM GAS  /tmp/cctoWaKX.s 			page 31
+
+
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Sector FLASH sector to erase
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         The value of this parameter depend on device used within the same series      
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  VoltageRange The device voltage range which defines the erase parallelism.  
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by byte (8-bit) 
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by half word (16-bit)
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by word (32-bit)
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *                                  the operation will be done by double word (64-bit)
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * 
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval None
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t tmp_psize = 0;
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_FLASH_SECTOR(Sector));
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_VOLTAGERANGE(VoltageRange));
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****      tmp_psize = FLASH_PSIZE_BYTE;
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     tmp_psize = FLASH_PSIZE_HALF_WORD;
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     tmp_psize = FLASH_PSIZE_WORD;
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* If the previous operation is completed, proceed to erase the sector */
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR &= CR_PSIZE_MASK;
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= tmp_psize;
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR &= SECTOR_MASK;
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= FLASH_CR_STRT;
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Data synchronous Barrier (DSB) Just after the write operation
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****      This will force the CPU to respect the sequence of instruction (no optimization).*/
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   __DSB();
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Return the FLASH Write Protection Option Bytes value.
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval uint32_t FLASH Write Protection Option Bytes value
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP(void)
+ARM GAS  /tmp/cctoWaKX.s 			page 32
+
+
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Return the FLASH write protection Register value */
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Wwdg Selects the IWDG mode
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_WWDG_SW: Software WWDG selected
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_WWDG_HW: Hardware WWDG selected
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Iwdg Selects the WWDG mode
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_SW: Software IWDG selected
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_HW: Hardware IWDG selected
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Stop Reset event when entering STOP mode.
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter  can be one of the following values:
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_STOP_RST: Reset generated when entering in STOP
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Stdby Reset event when entering Standby mode.
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter  can be one of the following values:
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Iwdgstop Independent watchdog counter freeze in Stop mode.
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter  can be one of the following values:
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Iwdgstdby Independent watchdog counter freeze in standby mode.
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter  can be one of the following values:
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY           
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL Status
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t 
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t useroptionmask = 0x00;
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t useroptionvalue = 0x00;
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_WWDG_SOURCE(Wwdg));
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_IWDG_SOURCE(Iwdg));
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_STOP_SOURCE(Stop));
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_STDBY_SOURCE(Stdby));
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(status == HAL_OK)
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                       FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                       
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);
+ARM GAS  /tmp/cctoWaKX.s 			page 33
+
+
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /* Update User Option Byte */               
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return status; 
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Return the FLASH User Option Byte value.
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetUser(void)
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Return the User Option Byte */
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U));
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR_nDBANK */
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Enable the write protection of the desired bank1 or bank2 sectors
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @note   When the memory read protection level is selected (RDP level = 1), 
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         it is not possible to program or erase the flash sector i if CortexM7  
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1    
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * 
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  WRPSector specifies the sector(s) to be write protected.
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *              or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for S
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *              or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode f
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_WRP_SECTOR_All
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL FLASH State   
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_WRP_SECTOR(WRPSector));
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(status == HAL_OK)
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /*Write protection enabled on sectors */
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     FLASH->OPTCR &= (~WRPSector);  
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return status;
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ARM GAS  /tmp/cctoWaKX.s 			page 34
+
+
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @note   When the memory read protection level is selected (RDP level = 1), 
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         it is not possible to program or erase the flash sector i if CortexM4  
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1  
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * 
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  WRPSector specifies the sector(s) to be write protected.
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *              or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for S
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *              or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode f
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_WRP_Sector_All
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL Status   
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_WRP_SECTOR(WRPSector));
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(status == HAL_OK)
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     /* Write protection disabled on sectors */
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     FLASH->OPTCR |= (WRPSector); 
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return status;
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Set the read protection level.
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Level specifies the read protection level.
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_0: No protection
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_2: Full chip protection
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *   
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *    
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL Status
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_RDP_LEVEL(Level));
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ARM GAS  /tmp/cctoWaKX.s 			page 35
+
+
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(status == HAL_OK)
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   { 
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return status;
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Set the BOR Level. 
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param  Level specifies the Option Bytes BOR Reset Level.
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL Status
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 180              		.loc 1 902 1 is_stmt 1 view -0
+ 181              		.cfi_startproc
+ 182              		@ args = 0, pretend = 0, frame = 0
+ 183              		@ frame_needed = 0, uses_anonymous_args = 0
+ 184              		@ link register save eliminated.
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_BOR_LEVEL(Level));
+ 185              		.loc 1 904 3 view .LVU32
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Set the BOR Level */
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);
+ 186              		.loc 1 907 3 view .LVU33
+ 187 0000 034A     		ldr	r2, .L16
+ 188 0002 5369     		ldr	r3, [r2, #20]
+ 189 0004 23F00C03 		bic	r3, r3, #12
+ 190 0008 1843     		orrs	r0, r0, r3
+ 191              	.LVL7:
+ 192              		.loc 1 907 3 is_stmt 0 view .LVU34
+ 193 000a 5061     		str	r0, [r2, #20]
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return HAL_OK;
+ 194              		.loc 1 909 3 is_stmt 1 view .LVU35
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 195              		.loc 1 911 1 is_stmt 0 view .LVU36
+ 196 000c 0020     		movs	r0, #0
+ 197 000e 7047     		bx	lr
+ 198              	.L17:
+ 199              		.align	2
+ 200              	.L16:
+ 201 0010 003C0240 		.word	1073888256
+ 202              		.cfi_endproc
+ 203              	.LFE153:
+ 205              		.section	.text.FLASH_OB_GetRDP,"ax",%progbits
+ 206              		.align	1
+ 207              		.syntax unified
+ 208              		.thumb
+ARM GAS  /tmp/cctoWaKX.s 			page 36
+
+
+ 209              		.thumb_func
+ 210              		.fpu fpv5-d16
+ 212              	FLASH_OB_GetRDP:
+ 213              	.LFB155:
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Configure Boot base address.
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * 
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param   BootOption  specifies Boot base address depending from Boot pin = 0 or pin = 1
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0                 
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1  
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param   Address specifies Boot base address
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)                 
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) 
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)  
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)  
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)                 
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)                    
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)              
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *    
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval HAL Status
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Check the parameters */
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_BOOT_ADDRESS(Address));
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Wait for last operation to be completed */
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(status == HAL_OK)
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     if(BootOption == OPTIONBYTE_BOOTADDR_0)
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {			
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     else
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return status;
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Returns the FLASH Read Protection level.
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval FlagStatus FLASH ReadOut Protection Status:
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *         This parameter can be one of the following values:
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_0: No protection
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OB_RDP_LEVEL_2: Full chip protection
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ARM GAS  /tmp/cctoWaKX.s 			page 37
+
+
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetRDP(void)
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 214              		.loc 1 966 1 is_stmt 1 view -0
+ 215              		.cfi_startproc
+ 216              		@ args = 0, pretend = 0, frame = 0
+ 217              		@ frame_needed = 0, uses_anonymous_args = 0
+ 218              		@ link register save eliminated.
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint8_t readstatus = OB_RDP_LEVEL_0;
+ 219              		.loc 1 967 3 view .LVU38
+ 220              	.LVL8:
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)
+ 221              		.loc 1 969 3 view .LVU39
+ 222              		.loc 1 969 8 is_stmt 0 view .LVU40
+ 223 0000 054B     		ldr	r3, .L21
+ 224 0002 587D     		ldrb	r0, [r3, #21]	@ zero_extendqisi2
+ 225 0004 C0B2     		uxtb	r0, r0
+ 226              		.loc 1 969 6 view .LVU41
+ 227 0006 AA28     		cmp	r0, #170
+ 228 0008 04D0     		beq	.L19
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     readstatus = OB_RDP_LEVEL_0;
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)
+ 229              		.loc 1 973 8 is_stmt 1 view .LVU42
+ 230              		.loc 1 973 13 is_stmt 0 view .LVU43
+ 231 000a 587D     		ldrb	r0, [r3, #21]	@ zero_extendqisi2
+ 232 000c C0B2     		uxtb	r0, r0
+ 233              		.loc 1 973 11 view .LVU44
+ 234 000e CC28     		cmp	r0, #204
+ 235 0010 00D0     		beq	.L19
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     readstatus = OB_RDP_LEVEL_2;
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else 
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     readstatus = OB_RDP_LEVEL_1;
+ 236              		.loc 1 979 16 view .LVU45
+ 237 0012 5520     		movs	r0, #85
+ 238              	.L19:
+ 239              	.LVL9:
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return readstatus;
+ 240              		.loc 1 982 3 is_stmt 1 view .LVU46
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 241              		.loc 1 983 1 is_stmt 0 view .LVU47
+ 242 0014 7047     		bx	lr
+ 243              	.L22:
+ 244 0016 00BF     		.align	2
+ 245              	.L21:
+ 246 0018 003C0240 		.word	1073888256
+ 247              		.cfi_endproc
+ 248              	.LFE155:
+ 250              		.section	.text.FLASH_OB_GetBOR,"ax",%progbits
+ 251              		.align	1
+ 252              		.syntax unified
+ARM GAS  /tmp/cctoWaKX.s 			page 38
+
+
+ 253              		.thumb
+ 254              		.thumb_func
+ 255              		.fpu fpv5-d16
+ 257              	FLASH_OB_GetBOR:
+ 258              	.LFB156:
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Returns the FLASH BOR level.
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval uint32_t The FLASH BOR level:
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V  
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetBOR(void)
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {
+ 259              		.loc 1 994 1 is_stmt 1 view -0
+ 260              		.cfi_startproc
+ 261              		@ args = 0, pretend = 0, frame = 0
+ 262              		@ frame_needed = 0, uses_anonymous_args = 0
+ 263              		@ link register save eliminated.
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   /* Return the FLASH BOR level */
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return ((uint32_t)(FLASH->OPTCR & 0x0C));
+ 264              		.loc 1 996 3 view .LVU49
+ 265              		.loc 1 996 27 is_stmt 0 view .LVU50
+ 266 0000 024B     		ldr	r3, .L24
+ 267 0002 5869     		ldr	r0, [r3, #20]
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 268              		.loc 1 997 1 view .LVU51
+ 269 0004 00F00C00 		and	r0, r0, #12
+ 270 0008 7047     		bx	lr
+ 271              	.L25:
+ 272 000a 00BF     		.align	2
+ 273              	.L24:
+ 274 000c 003C0240 		.word	1073888256
+ 275              		.cfi_endproc
+ 276              	.LFE156:
+ 278              		.section	.text.FLASH_OB_GetBootAddress,"ax",%progbits
+ 279              		.align	1
+ 280              		.syntax unified
+ 281              		.thumb
+ 282              		.thumb_func
+ 283              		.fpu fpv5-d16
+ 285              	FLASH_OB_GetBootAddress:
+ 286              	.LVL10:
+ 287              	.LFB157:
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @brief  Configure Boot base address.
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * 
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @param   BootOption  specifies Boot base address depending from Boot pin = 0 or pin = 1
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *          This parameter can be one of the following values:
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0                 
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1       
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *    
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   * @retval uint32_t Boot Base Address:
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)                 
+ARM GAS  /tmp/cctoWaKX.s 			page 39
+
+
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) 
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)  
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)  
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)                 
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)                    
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   *            - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) 
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   */
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** {  
+ 288              		.loc 1 1017 1 is_stmt 1 view -0
+ 289              		.cfi_startproc
+ 290              		@ args = 0, pretend = 0, frame = 0
+ 291              		@ frame_needed = 0, uses_anonymous_args = 0
+ 292              		@ link register save eliminated.
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t Address = 0;
+ 293              		.loc 1 1018 3 view .LVU53
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 	/* Return the Boot base Address */
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   if(BootOption == OPTIONBYTE_BOOTADDR_0)
+ 294              		.loc 1 1021 3 view .LVU54
+ 295              		.loc 1 1021 5 is_stmt 0 view .LVU55
+ 296 0000 1028     		cmp	r0, #16
+ 297 0002 03D0     		beq	.L29
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {			
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 	}
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   else
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 	{
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 		Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);
+ 298              		.loc 1 1027 3 is_stmt 1 view .LVU56
+ 299              		.loc 1 1027 20 is_stmt 0 view .LVU57
+ 300 0004 034B     		ldr	r3, .L30
+ 301 0006 9869     		ldr	r0, [r3, #24]
+ 302              	.LVL11:
+ 303              		.loc 1 1027 55 view .LVU58
+ 304 0008 000C     		lsrs	r0, r0, #16
+ 305              	.LVL12:
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 	}
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   return Address;
+ 306              		.loc 1 1030 3 is_stmt 1 view .LVU59
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 307              		.loc 1 1031 1 is_stmt 0 view .LVU60
+ 308 000a 7047     		bx	lr
+ 309              	.LVL13:
+ 310              	.L29:
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 	}
+ 311              		.loc 1 1023 5 is_stmt 1 view .LVU61
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 	}
+ 312              		.loc 1 1023 20 is_stmt 0 view .LVU62
+ 313 000c 014B     		ldr	r3, .L30
+ 314 000e 9869     		ldr	r0, [r3, #24]
+ 315              	.LVL14:
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 	}
+ 316              		.loc 1 1023 13 view .LVU63
+ 317 0010 80B2     		uxth	r0, r0
+ 318              	.LVL15:
+ARM GAS  /tmp/cctoWaKX.s 			page 40
+
+
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 	}
+ 319              		.loc 1 1023 13 view .LVU64
+ 320 0012 7047     		bx	lr
+ 321              	.L31:
+ 322              		.align	2
+ 323              	.L30:
+ 324 0014 003C0240 		.word	1073888256
+ 325              		.cfi_endproc
+ 326              	.LFE157:
+ 328              		.section	.text.FLASH_OB_EnableWRP,"ax",%progbits
+ 329              		.align	1
+ 330              		.syntax unified
+ 331              		.thumb
+ 332              		.thumb_func
+ 333              		.fpu fpv5-d16
+ 335              	FLASH_OB_EnableWRP:
+ 336              	.LVL16:
+ 337              	.LFB150:
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 338              		.loc 1 807 1 is_stmt 1 view -0
+ 339              		.cfi_startproc
+ 340              		@ args = 0, pretend = 0, frame = 0
+ 341              		@ frame_needed = 0, uses_anonymous_args = 0
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 342              		.loc 1 807 1 is_stmt 0 view .LVU66
+ 343 0000 10B5     		push	{r4, lr}
+ 344              	.LCFI0:
+ 345              		.cfi_def_cfa_offset 8
+ 346              		.cfi_offset 4, -8
+ 347              		.cfi_offset 14, -4
+ 348 0002 0446     		mov	r4, r0
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 349              		.loc 1 808 3 is_stmt 1 view .LVU67
+ 350              	.LVL17:
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+ 351              		.loc 1 811 3 view .LVU68
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 352              		.loc 1 814 3 view .LVU69
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 353              		.loc 1 814 12 is_stmt 0 view .LVU70
+ 354 0004 4CF25030 		movw	r0, #50000
+ 355              	.LVL18:
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 356              		.loc 1 814 12 view .LVU71
+ 357 0008 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 358              	.LVL19:
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 359              		.loc 1 816 3 is_stmt 1 view .LVU72
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 360              		.loc 1 816 5 is_stmt 0 view .LVU73
+ 361 000c 20B9     		cbnz	r0, .L33
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 362              		.loc 1 819 5 is_stmt 1 view .LVU74
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 363              		.loc 1 819 18 is_stmt 0 view .LVU75
+ 364 000e 034A     		ldr	r2, .L35
+ 365 0010 5369     		ldr	r3, [r2, #20]
+ARM GAS  /tmp/cctoWaKX.s 			page 41
+
+
+ 366 0012 23EA0404 		bic	r4, r3, r4
+ 367              	.LVL20:
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 368              		.loc 1 819 18 view .LVU76
+ 369 0016 5461     		str	r4, [r2, #20]
+ 370              	.L33:
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 371              		.loc 1 822 3 is_stmt 1 view .LVU77
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 372              		.loc 1 823 1 is_stmt 0 view .LVU78
+ 373 0018 10BD     		pop	{r4, pc}
+ 374              	.L36:
+ 375 001a 00BF     		.align	2
+ 376              	.L35:
+ 377 001c 003C0240 		.word	1073888256
+ 378              		.cfi_endproc
+ 379              	.LFE150:
+ 381              		.section	.text.FLASH_OB_DisableWRP,"ax",%progbits
+ 382              		.align	1
+ 383              		.syntax unified
+ 384              		.thumb
+ 385              		.thumb_func
+ 386              		.fpu fpv5-d16
+ 388              	FLASH_OB_DisableWRP:
+ 389              	.LVL21:
+ 390              	.LFB151:
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 391              		.loc 1 843 1 is_stmt 1 view -0
+ 392              		.cfi_startproc
+ 393              		@ args = 0, pretend = 0, frame = 0
+ 394              		@ frame_needed = 0, uses_anonymous_args = 0
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 395              		.loc 1 843 1 is_stmt 0 view .LVU80
+ 396 0000 10B5     		push	{r4, lr}
+ 397              	.LCFI1:
+ 398              		.cfi_def_cfa_offset 8
+ 399              		.cfi_offset 4, -8
+ 400              		.cfi_offset 14, -4
+ 401 0002 0446     		mov	r4, r0
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 402              		.loc 1 844 3 is_stmt 1 view .LVU81
+ 403              	.LVL22:
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+ 404              		.loc 1 847 3 view .LVU82
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 405              		.loc 1 850 3 view .LVU83
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 406              		.loc 1 850 12 is_stmt 0 view .LVU84
+ 407 0004 4CF25030 		movw	r0, #50000
+ 408              	.LVL23:
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 409              		.loc 1 850 12 view .LVU85
+ 410 0008 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 411              	.LVL24:
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 412              		.loc 1 852 3 is_stmt 1 view .LVU86
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ARM GAS  /tmp/cctoWaKX.s 			page 42
+
+
+ 413              		.loc 1 852 5 is_stmt 0 view .LVU87
+ 414 000c 18B9     		cbnz	r0, .L38
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 415              		.loc 1 855 5 is_stmt 1 view .LVU88
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 416              		.loc 1 855 18 is_stmt 0 view .LVU89
+ 417 000e 024A     		ldr	r2, .L40
+ 418 0010 5369     		ldr	r3, [r2, #20]
+ 419 0012 1C43     		orrs	r4, r4, r3
+ 420              	.LVL25:
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 421              		.loc 1 855 18 view .LVU90
+ 422 0014 5461     		str	r4, [r2, #20]
+ 423              	.L38:
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 424              		.loc 1 858 3 is_stmt 1 view .LVU91
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 425              		.loc 1 859 1 is_stmt 0 view .LVU92
+ 426 0016 10BD     		pop	{r4, pc}
+ 427              	.L41:
+ 428              		.align	2
+ 429              	.L40:
+ 430 0018 003C0240 		.word	1073888256
+ 431              		.cfi_endproc
+ 432              	.LFE151:
+ 434              		.section	.text.FLASH_OB_RDP_LevelConfig,"ax",%progbits
+ 435              		.align	1
+ 436              		.syntax unified
+ 437              		.thumb
+ 438              		.thumb_func
+ 439              		.fpu fpv5-d16
+ 441              	FLASH_OB_RDP_LevelConfig:
+ 442              	.LVL26:
+ 443              	.LFB152:
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 444              		.loc 1 874 1 is_stmt 1 view -0
+ 445              		.cfi_startproc
+ 446              		@ args = 0, pretend = 0, frame = 0
+ 447              		@ frame_needed = 0, uses_anonymous_args = 0
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 448              		.loc 1 874 1 is_stmt 0 view .LVU94
+ 449 0000 10B5     		push	{r4, lr}
+ 450              	.LCFI2:
+ 451              		.cfi_def_cfa_offset 8
+ 452              		.cfi_offset 4, -8
+ 453              		.cfi_offset 14, -4
+ 454 0002 0446     		mov	r4, r0
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 455              		.loc 1 875 3 is_stmt 1 view .LVU95
+ 456              	.LVL27:
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+ 457              		.loc 1 878 3 view .LVU96
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 458              		.loc 1 881 3 view .LVU97
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 459              		.loc 1 881 12 is_stmt 0 view .LVU98
+ 460 0004 4CF25030 		movw	r0, #50000
+ARM GAS  /tmp/cctoWaKX.s 			page 43
+
+
+ 461              	.LVL28:
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 462              		.loc 1 881 12 view .LVU99
+ 463 0008 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 464              	.LVL29:
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   { 
+ 465              		.loc 1 883 3 is_stmt 1 view .LVU100
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   { 
+ 466              		.loc 1 883 5 is_stmt 0 view .LVU101
+ 467 000c 08B9     		cbnz	r0, .L43
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 468              		.loc 1 885 5 is_stmt 1 view .LVU102
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 469              		.loc 1 885 41 is_stmt 0 view .LVU103
+ 470 000e 014B     		ldr	r3, .L45
+ 471 0010 5C75     		strb	r4, [r3, #21]
+ 472              	.L43:
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 473              		.loc 1 888 3 is_stmt 1 view .LVU104
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 474              		.loc 1 889 1 is_stmt 0 view .LVU105
+ 475 0012 10BD     		pop	{r4, pc}
+ 476              	.L46:
+ 477              		.align	2
+ 478              	.L45:
+ 479 0014 003C0240 		.word	1073888256
+ 480              		.cfi_endproc
+ 481              	.LFE152:
+ 483              		.section	.text.FLASH_OB_UserConfig,"ax",%progbits
+ 484              		.align	1
+ 485              		.syntax unified
+ 486              		.thumb
+ 487              		.thumb_func
+ 488              		.fpu fpv5-d16
+ 490              	FLASH_OB_UserConfig:
+ 491              	.LVL30:
+ 492              	.LFB148:
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t useroptionmask = 0x00;
+ 493              		.loc 1 578 1 is_stmt 1 view -0
+ 494              		.cfi_startproc
+ 495              		@ args = 16, pretend = 0, frame = 0
+ 496              		@ frame_needed = 0, uses_anonymous_args = 0
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t useroptionmask = 0x00;
+ 497              		.loc 1 578 1 is_stmt 0 view .LVU107
+ 498 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 499              	.LCFI3:
+ 500              		.cfi_def_cfa_offset 24
+ 501              		.cfi_offset 3, -24
+ 502              		.cfi_offset 4, -20
+ 503              		.cfi_offset 5, -16
+ 504              		.cfi_offset 6, -12
+ 505              		.cfi_offset 7, -8
+ 506              		.cfi_offset 14, -4
+ 507 0002 0746     		mov	r7, r0
+ 508 0004 0C46     		mov	r4, r1
+ 509 0006 1646     		mov	r6, r2
+ 510 0008 1D46     		mov	r5, r3
+ARM GAS  /tmp/cctoWaKX.s 			page 44
+
+
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t useroptionvalue = 0x00;
+ 511              		.loc 1 579 3 is_stmt 1 view .LVU108
+ 512              	.LVL31:
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 513              		.loc 1 580 3 view .LVU109
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 514              		.loc 1 582 3 view .LVU110
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_IWDG_SOURCE(Iwdg));
+ 515              		.loc 1 585 3 view .LVU111
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_STOP_SOURCE(Stop));
+ 516              		.loc 1 586 3 view .LVU112
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_STDBY_SOURCE(Stdby));
+ 517              		.loc 1 587 3 view .LVU113
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
+ 518              		.loc 1 588 3 view .LVU114
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
+ 519              		.loc 1 589 3 view .LVU115
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_NDBANK(NDBank));
+ 520              		.loc 1 590 3 view .LVU116
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_OB_NDBOOT(NDBoot));
+ 521              		.loc 1 591 3 view .LVU117
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 522              		.loc 1 592 3 view .LVU118
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 523              		.loc 1 595 3 view .LVU119
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 524              		.loc 1 595 12 is_stmt 0 view .LVU120
+ 525 000a 4CF25030 		movw	r0, #50000
+ 526              	.LVL32:
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 527              		.loc 1 595 12 view .LVU121
+ 528 000e FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 529              	.LVL33:
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 530              		.loc 1 597 3 is_stmt 1 view .LVU122
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 531              		.loc 1 597 5 is_stmt 0 view .LVU123
+ 532 0012 90B9     		cbnz	r0, .L48
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                       FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \
+ 533              		.loc 1 599 5 is_stmt 1 view .LVU124
+ 534              	.LVL34:
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 535              		.loc 1 603 5 view .LVU125
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 536              		.loc 1 603 29 is_stmt 0 view .LVU126
+ 537 0014 44EA0701 		orr	r1, r4, r7
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 538              		.loc 1 603 36 view .LVU127
+ 539 0018 3143     		orrs	r1, r1, r6
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 540              		.loc 1 603 43 view .LVU128
+ 541 001a 41EA0503 		orr	r3, r1, r5
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 542              		.loc 1 603 51 view .LVU129
+ 543 001e 069C     		ldr	r4, [sp, #24]
+ 544              	.LVL35:
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ARM GAS  /tmp/cctoWaKX.s 			page 45
+
+
+ 545              		.loc 1 603 51 view .LVU130
+ 546 0020 2343     		orrs	r3, r3, r4
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 547              		.loc 1 603 62 view .LVU131
+ 548 0022 079A     		ldr	r2, [sp, #28]
+ 549 0024 1343     		orrs	r3, r3, r2
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 550              		.loc 1 603 74 view .LVU132
+ 551 0026 099A     		ldr	r2, [sp, #36]
+ 552 0028 1343     		orrs	r3, r3, r2
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 553              		.loc 1 603 21 view .LVU133
+ 554 002a 089A     		ldr	r2, [sp, #32]
+ 555 002c 1343     		orrs	r3, r3, r2
+ 556              	.LVL36:
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 557              		.loc 1 606 5 is_stmt 1 view .LVU134
+ 558 002e 0349     		ldr	r1, .L50
+ 559 0030 4C69     		ldr	r4, [r1, #20]
+ 560 0032 034A     		ldr	r2, .L50+4
+ 561 0034 2240     		ands	r2, r2, r4
+ 562 0036 1343     		orrs	r3, r3, r2
+ 563              	.LVL37:
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 564              		.loc 1 606 5 is_stmt 0 view .LVU135
+ 565 0038 4B61     		str	r3, [r1, #20]
+ 566              	.LVL38:
+ 567              	.L48:
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 568              		.loc 1 609 3 is_stmt 1 view .LVU136
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 569              		.loc 1 610 1 is_stmt 0 view .LVU137
+ 570 003a F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 571              	.LVL39:
+ 572              	.L51:
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 573              		.loc 1 610 1 view .LVU138
+ 574              		.align	2
+ 575              	.L50:
+ 576 003c 003C0240 		.word	1073888256
+ 577 0040 0FFFFF0F 		.word	268435215
+ 578              		.cfi_endproc
+ 579              	.LFE148:
+ 581              		.section	.text.FLASH_OB_BootAddressConfig,"ax",%progbits
+ 582              		.align	1
+ 583              		.syntax unified
+ 584              		.thumb
+ 585              		.thumb_func
+ 586              		.fpu fpv5-d16
+ 588              	FLASH_OB_BootAddressConfig:
+ 589              	.LVL40:
+ 590              	.LFB154:
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 591              		.loc 1 933 1 is_stmt 1 view -0
+ 592              		.cfi_startproc
+ 593              		@ args = 0, pretend = 0, frame = 0
+ 594              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cctoWaKX.s 			page 46
+
+
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 595              		.loc 1 933 1 is_stmt 0 view .LVU140
+ 596 0000 38B5     		push	{r3, r4, r5, lr}
+ 597              	.LCFI4:
+ 598              		.cfi_def_cfa_offset 16
+ 599              		.cfi_offset 3, -16
+ 600              		.cfi_offset 4, -12
+ 601              		.cfi_offset 5, -8
+ 602              		.cfi_offset 14, -4
+ 603 0002 0446     		mov	r4, r0
+ 604 0004 0D46     		mov	r5, r1
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 605              		.loc 1 934 3 is_stmt 1 view .LVU141
+ 606              	.LVL41:
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+ 607              		.loc 1 937 3 view .LVU142
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 608              		.loc 1 940 3 view .LVU143
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 609              		.loc 1 940 12 is_stmt 0 view .LVU144
+ 610 0006 4CF25030 		movw	r0, #50000
+ 611              	.LVL42:
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 612              		.loc 1 940 12 view .LVU145
+ 613 000a FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 614              	.LVL43:
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 615              		.loc 1 942 3 is_stmt 1 view .LVU146
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 616              		.loc 1 942 5 is_stmt 0 view .LVU147
+ 617 000e 38B9     		cbnz	r0, .L53
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {			
+ 618              		.loc 1 944 5 is_stmt 1 view .LVU148
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {			
+ 619              		.loc 1 944 7 is_stmt 0 view .LVU149
+ 620 0010 102C     		cmp	r4, #16
+ 621 0012 06D0     		beq	.L56
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 622              		.loc 1 950 7 is_stmt 1 view .LVU150
+ 623 0014 064B     		ldr	r3, .L57
+ 624 0016 9969     		ldr	r1, [r3, #24]
+ 625 0018 89B2     		uxth	r1, r1
+ 626 001a 41EA0541 		orr	r1, r1, r5, lsl #16
+ 627 001e 9961     		str	r1, [r3, #24]
+ 628              	.L53:
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 629              		.loc 1 954 3 view .LVU151
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 630              		.loc 1 955 1 is_stmt 0 view .LVU152
+ 631 0020 38BD     		pop	{r3, r4, r5, pc}
+ 632              	.LVL44:
+ 633              	.L56:
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 634              		.loc 1 946 7 is_stmt 1 view .LVU153
+ 635 0022 034B     		ldr	r3, .L57
+ 636 0024 9A69     		ldr	r2, [r3, #24]
+ 637 0026 0349     		ldr	r1, .L57+4
+ARM GAS  /tmp/cctoWaKX.s 			page 47
+
+
+ 638 0028 1140     		ands	r1, r1, r2
+ 639 002a 2943     		orrs	r1, r1, r5
+ 640 002c 9961     		str	r1, [r3, #24]
+ 641 002e F7E7     		b	.L53
+ 642              	.L58:
+ 643              		.align	2
+ 644              	.L57:
+ 645 0030 003C0240 		.word	1073888256
+ 646 0034 0000FFFF 		.word	-65536
+ 647              		.cfi_endproc
+ 648              	.LFE154:
+ 650              		.section	.text.HAL_FLASHEx_OBProgram,"ax",%progbits
+ 651              		.align	1
+ 652              		.global	HAL_FLASHEx_OBProgram
+ 653              		.syntax unified
+ 654              		.thumb
+ 655              		.thumb_func
+ 656              		.fpu fpv5-d16
+ 658              	HAL_FLASHEx_OBProgram:
+ 659              	.LVL45:
+ 660              	.LFB143:
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 661              		.loc 1 286 1 view -0
+ 662              		.cfi_startproc
+ 663              		@ args = 0, pretend = 0, frame = 0
+ 664              		@ frame_needed = 0, uses_anonymous_args = 0
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 665              		.loc 1 287 3 view .LVU155
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 666              		.loc 1 290 3 view .LVU156
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 667              		.loc 1 290 3 view .LVU157
+ 668 0000 2F4B     		ldr	r3, .L80
+ 669 0002 1B7D     		ldrb	r3, [r3, #20]	@ zero_extendqisi2
+ 670 0004 012B     		cmp	r3, #1
+ 671 0006 58D0     		beq	.L68
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 672              		.loc 1 286 1 is_stmt 0 discriminator 2 view .LVU158
+ 673 0008 10B5     		push	{r4, lr}
+ 674              	.LCFI5:
+ 675              		.cfi_def_cfa_offset 8
+ 676              		.cfi_offset 4, -8
+ 677              		.cfi_offset 14, -4
+ 678 000a 84B0     		sub	sp, sp, #16
+ 679              	.LCFI6:
+ 680              		.cfi_def_cfa_offset 24
+ 681 000c 0446     		mov	r4, r0
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 682              		.loc 1 290 3 is_stmt 1 discriminator 2 view .LVU159
+ 683 000e 2C4B     		ldr	r3, .L80
+ 684 0010 0122     		movs	r2, #1
+ 685 0012 1A75     		strb	r2, [r3, #20]
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 686              		.loc 1 290 3 discriminator 2 view .LVU160
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 687              		.loc 1 293 3 discriminator 2 view .LVU161
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ARM GAS  /tmp/cctoWaKX.s 			page 48
+
+
+ 688              		.loc 1 296 3 discriminator 2 view .LVU162
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 689              		.loc 1 296 14 is_stmt 0 discriminator 2 view .LVU163
+ 690 0014 0368     		ldr	r3, [r0]
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 691              		.loc 1 296 5 discriminator 2 view .LVU164
+ 692 0016 13F0010F 		tst	r3, #1
+ 693 001a 0AD0     		beq	.L69
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+ 694              		.loc 1 298 5 is_stmt 1 view .LVU165
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {
+ 695              		.loc 1 299 5 view .LVU166
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {
+ 696              		.loc 1 299 15 is_stmt 0 view .LVU167
+ 697 001c 4368     		ldr	r3, [r0, #4]
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {
+ 698              		.loc 1 299 7 view .LVU168
+ 699 001e 9342     		cmp	r3, r2
+ 700 0020 03D0     		beq	.L74
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 701              		.loc 1 307 7 is_stmt 1 view .LVU169
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 702              		.loc 1 307 16 is_stmt 0 view .LVU170
+ 703 0022 8068     		ldr	r0, [r0, #8]
+ 704              	.LVL46:
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 705              		.loc 1 307 16 view .LVU171
+ 706 0024 FFF7FEFF 		bl	FLASH_OB_DisableWRP
+ 707              	.LVL47:
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 708              		.loc 1 307 16 view .LVU172
+ 709 0028 04E0     		b	.L61
+ 710              	.LVL48:
+ 711              	.L74:
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 712              		.loc 1 302 7 is_stmt 1 view .LVU173
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 713              		.loc 1 302 16 is_stmt 0 view .LVU174
+ 714 002a 8068     		ldr	r0, [r0, #8]
+ 715              	.LVL49:
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 716              		.loc 1 302 16 view .LVU175
+ 717 002c FFF7FEFF 		bl	FLASH_OB_EnableWRP
+ 718              	.LVL50:
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 719              		.loc 1 302 16 view .LVU176
+ 720 0030 00E0     		b	.L61
+ 721              	.LVL51:
+ 722              	.L69:
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 723              		.loc 1 287 21 view .LVU177
+ 724 0032 0120     		movs	r0, #1
+ 725              	.LVL52:
+ 726              	.L61:
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 727              		.loc 1 312 3 is_stmt 1 view .LVU178
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ARM GAS  /tmp/cctoWaKX.s 			page 49
+
+
+ 728              		.loc 1 312 14 is_stmt 0 view .LVU179
+ 729 0034 2368     		ldr	r3, [r4]
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 730              		.loc 1 312 5 view .LVU180
+ 731 0036 13F0020F 		tst	r3, #2
+ 732 003a 14D1     		bne	.L75
+ 733              	.L63:
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 734              		.loc 1 318 3 is_stmt 1 view .LVU181
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 735              		.loc 1 318 14 is_stmt 0 view .LVU182
+ 736 003c 2368     		ldr	r3, [r4]
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 737              		.loc 1 318 5 view .LVU183
+ 738 003e 13F0040F 		tst	r3, #4
+ 739 0042 14D1     		bne	.L76
+ 740              	.L64:
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 741              		.loc 1 340 3 is_stmt 1 view .LVU184
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 742              		.loc 1 340 14 is_stmt 0 view .LVU185
+ 743 0044 2368     		ldr	r3, [r4]
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 744              		.loc 1 340 5 view .LVU186
+ 745 0046 13F0080F 		tst	r3, #8
+ 746 004a 28D1     		bne	.L77
+ 747              	.L65:
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 748              		.loc 1 346 3 is_stmt 1 view .LVU187
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 749              		.loc 1 346 14 is_stmt 0 view .LVU188
+ 750 004c 2368     		ldr	r3, [r4]
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 751              		.loc 1 346 5 view .LVU189
+ 752 004e 13F0100F 		tst	r3, #16
+ 753 0052 28D1     		bne	.L78
+ 754              	.L66:
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 755              		.loc 1 352 3 is_stmt 1 view .LVU190
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 756              		.loc 1 352 14 is_stmt 0 view .LVU191
+ 757 0054 2368     		ldr	r3, [r4]
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 758              		.loc 1 352 5 view .LVU192
+ 759 0056 13F0200F 		tst	r3, #32
+ 760 005a 29D1     		bne	.L79
+ 761              	.L67:
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 762              		.loc 1 372 3 is_stmt 1 view .LVU193
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 763              		.loc 1 372 3 view .LVU194
+ 764 005c 184B     		ldr	r3, .L80
+ 765 005e 0022     		movs	r2, #0
+ 766 0060 1A75     		strb	r2, [r3, #20]
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 767              		.loc 1 372 3 view .LVU195
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ARM GAS  /tmp/cctoWaKX.s 			page 50
+
+
+ 768              		.loc 1 374 3 view .LVU196
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 769              		.loc 1 375 1 is_stmt 0 view .LVU197
+ 770 0062 04B0     		add	sp, sp, #16
+ 771              	.LCFI7:
+ 772              		.cfi_remember_state
+ 773              		.cfi_def_cfa_offset 8
+ 774              		@ sp needed
+ 775 0064 10BD     		pop	{r4, pc}
+ 776              	.LVL53:
+ 777              	.L75:
+ 778              	.LCFI8:
+ 779              		.cfi_restore_state
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 780              		.loc 1 314 5 is_stmt 1 view .LVU198
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 781              		.loc 1 314 14 is_stmt 0 view .LVU199
+ 782 0066 207B     		ldrb	r0, [r4, #12]	@ zero_extendqisi2
+ 783              	.LVL54:
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 784              		.loc 1 314 14 view .LVU200
+ 785 0068 FFF7FEFF 		bl	FLASH_OB_RDP_LevelConfig
+ 786              	.LVL55:
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 787              		.loc 1 314 14 view .LVU201
+ 788 006c E6E7     		b	.L63
+ 789              	.L76:
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_IWDG_SW,
+ 790              		.loc 1 321 5 is_stmt 1 view .LVU202
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_IWDG_SW,
+ 791              		.loc 1 321 41 is_stmt 0 view .LVU203
+ 792 006e 6069     		ldr	r0, [r4, #20]
+ 793              	.LVL56:
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_IWDG_SW,
+ 794              		.loc 1 321 14 view .LVU204
+ 795 0070 00F08053 		and	r3, r0, #268435456
+ 796 0074 0393     		str	r3, [sp, #12]
+ 797 0076 00F00053 		and	r3, r0, #536870912
+ 798 007a 0293     		str	r3, [sp, #8]
+ 799 007c 00F08043 		and	r3, r0, #1073741824
+ 800 0080 0193     		str	r3, [sp, #4]
+ 801 0082 00F00043 		and	r3, r0, #-2147483648
+ 802 0086 0093     		str	r3, [sp]
+ 803 0088 00F08003 		and	r3, r0, #128
+ 804 008c 00F04002 		and	r2, r0, #64
+ 805 0090 00F02001 		and	r1, r0, #32
+ 806 0094 00F01000 		and	r0, r0, #16
+ 807 0098 FFF7FEFF 		bl	FLASH_OB_UserConfig
+ 808              	.LVL57:
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                                  pOBInit->USERConfig & OB_IWDG_SW,
+ 809              		.loc 1 321 14 view .LVU205
+ 810 009c D2E7     		b	.L64
+ 811              	.L77:
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 812              		.loc 1 342 5 is_stmt 1 view .LVU206
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 813              		.loc 1 342 14 is_stmt 0 view .LVU207
+ARM GAS  /tmp/cctoWaKX.s 			page 51
+
+
+ 814 009e 207C     		ldrb	r0, [r4, #16]	@ zero_extendqisi2
+ 815              	.LVL58:
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 816              		.loc 1 342 14 view .LVU208
+ 817 00a0 FFF7FEFF 		bl	FLASH_OB_BOR_LevelConfig
+ 818              	.LVL59:
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 819              		.loc 1 342 14 view .LVU209
+ 820 00a4 D2E7     		b	.L65
+ 821              	.L78:
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 822              		.loc 1 348 5 is_stmt 1 view .LVU210
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 823              		.loc 1 348 14 is_stmt 0 view .LVU211
+ 824 00a6 A169     		ldr	r1, [r4, #24]
+ 825 00a8 1020     		movs	r0, #16
+ 826              	.LVL60:
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 827              		.loc 1 348 14 view .LVU212
+ 828 00aa FFF7FEFF 		bl	FLASH_OB_BootAddressConfig
+ 829              	.LVL61:
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 830              		.loc 1 348 14 view .LVU213
+ 831 00ae D1E7     		b	.L66
+ 832              	.L79:
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 833              		.loc 1 354 5 is_stmt 1 view .LVU214
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 834              		.loc 1 354 14 is_stmt 0 view .LVU215
+ 835 00b0 E169     		ldr	r1, [r4, #28]
+ 836 00b2 2020     		movs	r0, #32
+ 837              	.LVL62:
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 838              		.loc 1 354 14 view .LVU216
+ 839 00b4 FFF7FEFF 		bl	FLASH_OB_BootAddressConfig
+ 840              	.LVL63:
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 841              		.loc 1 354 14 view .LVU217
+ 842 00b8 D0E7     		b	.L67
+ 843              	.LVL64:
+ 844              	.L68:
+ 845              	.LCFI9:
+ 846              		.cfi_def_cfa_offset 0
+ 847              		.cfi_restore 4
+ 848              		.cfi_restore 14
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 849              		.loc 1 290 3 view .LVU218
+ 850 00ba 0220     		movs	r0, #2
+ 851              	.LVL65:
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 852              		.loc 1 375 1 view .LVU219
+ 853 00bc 7047     		bx	lr
+ 854              	.L81:
+ 855 00be 00BF     		.align	2
+ 856              	.L80:
+ 857 00c0 00000000 		.word	pFlash
+ 858              		.cfi_endproc
+ARM GAS  /tmp/cctoWaKX.s 			page 52
+
+
+ 859              	.LFE143:
+ 861              		.section	.text.HAL_FLASHEx_OBGetConfig,"ax",%progbits
+ 862              		.align	1
+ 863              		.global	HAL_FLASHEx_OBGetConfig
+ 864              		.syntax unified
+ 865              		.thumb
+ 866              		.thumb_func
+ 867              		.fpu fpv5-d16
+ 869              	HAL_FLASHEx_OBGetConfig:
+ 870              	.LVL66:
+ 871              	.LFB144:
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
+ 872              		.loc 1 385 1 is_stmt 1 view -0
+ 873              		.cfi_startproc
+ 874              		@ args = 0, pretend = 0, frame = 0
+ 875              		@ frame_needed = 0, uses_anonymous_args = 0
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
+ 876              		.loc 1 385 1 is_stmt 0 view .LVU221
+ 877 0000 10B5     		push	{r4, lr}
+ 878              	.LCFI10:
+ 879              		.cfi_def_cfa_offset 8
+ 880              		.cfi_offset 4, -8
+ 881              		.cfi_offset 14, -4
+ 882 0002 0446     		mov	r4, r0
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 	                OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
+ 883              		.loc 1 386 3 is_stmt 1 view .LVU222
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 	                OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
+ 884              		.loc 1 386 23 is_stmt 0 view .LVU223
+ 885 0004 3F23     		movs	r3, #63
+ 886 0006 0360     		str	r3, [r0]
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 887              		.loc 1 390 3 is_stmt 1 view .LVU224
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 888              		.loc 1 390 24 is_stmt 0 view .LVU225
+ 889 0008 FFF7FEFF 		bl	FLASH_OB_GetWRP
+ 890              	.LVL67:
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 891              		.loc 1 390 22 view .LVU226
+ 892 000c A060     		str	r0, [r4, #8]
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 893              		.loc 1 393 3 is_stmt 1 view .LVU227
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 894              		.loc 1 393 23 is_stmt 0 view .LVU228
+ 895 000e FFF7FEFF 		bl	FLASH_OB_GetRDP
+ 896              	.LVL68:
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 897              		.loc 1 393 21 view .LVU229
+ 898 0012 E060     		str	r0, [r4, #12]
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 899              		.loc 1 396 3 is_stmt 1 view .LVU230
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 900              		.loc 1 396 25 is_stmt 0 view .LVU231
+ 901 0014 FFF7FEFF 		bl	FLASH_OB_GetUser
+ 902              	.LVL69:
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 903              		.loc 1 396 23 view .LVU232
+ 904 0018 6061     		str	r0, [r4, #20]
+ARM GAS  /tmp/cctoWaKX.s 			page 53
+
+
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 905              		.loc 1 399 3 is_stmt 1 view .LVU233
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 906              		.loc 1 399 23 is_stmt 0 view .LVU234
+ 907 001a FFF7FEFF 		bl	FLASH_OB_GetBOR
+ 908              	.LVL70:
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 909              		.loc 1 399 21 view .LVU235
+ 910 001e 2061     		str	r0, [r4, #16]
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 911              		.loc 1 402 3 is_stmt 1 view .LVU236
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 912              		.loc 1 402 24 is_stmt 0 view .LVU237
+ 913 0020 1020     		movs	r0, #16
+ 914 0022 FFF7FEFF 		bl	FLASH_OB_GetBootAddress
+ 915              	.LVL71:
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 916              		.loc 1 402 22 view .LVU238
+ 917 0026 A061     		str	r0, [r4, #24]
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 918              		.loc 1 405 3 is_stmt 1 view .LVU239
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 919              		.loc 1 405 24 is_stmt 0 view .LVU240
+ 920 0028 2020     		movs	r0, #32
+ 921 002a FFF7FEFF 		bl	FLASH_OB_GetBootAddress
+ 922              	.LVL72:
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 923              		.loc 1 405 22 view .LVU241
+ 924 002e E061     		str	r0, [r4, #28]
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 925              		.loc 1 414 1 view .LVU242
+ 926 0030 10BD     		pop	{r4, pc}
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /**
+ 927              		.loc 1 414 1 view .LVU243
+ 928              		.cfi_endproc
+ 929              	.LFE144:
+ 931              		.section	.text.FLASH_Erase_Sector,"ax",%progbits
+ 932              		.align	1
+ 933              		.global	FLASH_Erase_Sector
+ 934              		.syntax unified
+ 935              		.thumb
+ 936              		.thumb_func
+ 937              		.fpu fpv5-d16
+ 939              	FLASH_Erase_Sector:
+ 940              	.LVL73:
+ 941              	.LFB146:
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t tmp_psize = 0;
+ 942              		.loc 1 487 1 is_stmt 1 view -0
+ 943              		.cfi_startproc
+ 944              		@ args = 0, pretend = 0, frame = 0
+ 945              		@ frame_needed = 0, uses_anonymous_args = 0
+ 946              		@ link register save eliminated.
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 947              		.loc 1 488 3 view .LVU245
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   assert_param(IS_VOLTAGERANGE(VoltageRange));
+ 948              		.loc 1 491 3 view .LVU246
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ARM GAS  /tmp/cctoWaKX.s 			page 54
+
+
+ 949              		.loc 1 492 3 view .LVU247
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 950              		.loc 1 494 3 view .LVU248
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 951              		.loc 1 494 5 is_stmt 0 view .LVU249
+ 952 0000 49B1     		cbz	r1, .L87
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 953              		.loc 1 498 8 is_stmt 1 view .LVU250
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 954              		.loc 1 498 10 is_stmt 0 view .LVU251
+ 955 0002 0129     		cmp	r1, #1
+ 956 0004 26D0     		beq	.L88
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 957              		.loc 1 502 8 is_stmt 1 view .LVU252
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 958              		.loc 1 502 10 is_stmt 0 view .LVU253
+ 959 0006 0229     		cmp	r1, #2
+ 960 0008 02D0     		beq	.L90
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 961              		.loc 1 508 15 view .LVU254
+ 962 000a 4FF4407C 		mov	ip, #768
+ 963 000e 04E0     		b	.L85
+ 964              	.L90:
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 965              		.loc 1 504 15 view .LVU255
+ 966 0010 4FF4007C 		mov	ip, #512
+ 967 0014 01E0     		b	.L85
+ 968              	.L87:
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 969              		.loc 1 496 16 view .LVU256
+ 970 0016 4FF0000C 		mov	ip, #0
+ 971              	.L85:
+ 972              	.LVL74:
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 973              		.loc 1 512 3 is_stmt 1 view .LVU257
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 974              		.loc 1 512 5 is_stmt 0 view .LVU258
+ 975 001a 0B28     		cmp	r0, #11
+ 976 001c 00D9     		bls	.L86
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }  
+ 977              		.loc 1 514 5 is_stmt 1 view .LVU259
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }  
+ 978              		.loc 1 514 12 is_stmt 0 view .LVU260
+ 979 001e 0430     		adds	r0, r0, #4
+ 980              	.LVL75:
+ 981              	.L86:
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= tmp_psize;
+ 982              		.loc 1 518 3 is_stmt 1 view .LVU261
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= tmp_psize;
+ 983              		.loc 1 518 13 is_stmt 0 view .LVU262
+ 984 0020 0E4B     		ldr	r3, .L91
+ 985 0022 1969     		ldr	r1, [r3, #16]
+ 986              	.LVL76:
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= tmp_psize;
+ 987              		.loc 1 518 13 view .LVU263
+ 988 0024 21F44071 		bic	r1, r1, #768
+ 989 0028 1961     		str	r1, [r3, #16]
+ARM GAS  /tmp/cctoWaKX.s 			page 55
+
+
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
+ 990              		.loc 1 519 3 is_stmt 1 view .LVU264
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
+ 991              		.loc 1 519 13 is_stmt 0 view .LVU265
+ 992 002a 1A69     		ldr	r2, [r3, #16]
+ 993 002c 42EA0C02 		orr	r2, r2, ip
+ 994 0030 1A61     		str	r2, [r3, #16]
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+ 995              		.loc 1 520 3 is_stmt 1 view .LVU266
+ 996 0032 1A69     		ldr	r2, [r3, #16]
+ 997 0034 22F0F802 		bic	r2, r2, #248
+ 998 0038 1A61     		str	r2, [r3, #16]
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= FLASH_CR_STRT;
+ 999              		.loc 1 521 3 view .LVU267
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= FLASH_CR_STRT;
+ 1000              		.loc 1 521 13 is_stmt 0 view .LVU268
+ 1001 003a 1A69     		ldr	r2, [r3, #16]
+ 1002 003c 42EAC000 		orr	r0, r2, r0, lsl #3
+ 1003              	.LVL77:
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   FLASH->CR |= FLASH_CR_STRT;
+ 1004              		.loc 1 521 13 view .LVU269
+ 1005 0040 40F00200 		orr	r0, r0, #2
+ 1006 0044 1861     		str	r0, [r3, #16]
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 1007              		.loc 1 522 3 is_stmt 1 view .LVU270
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 1008              		.loc 1 522 13 is_stmt 0 view .LVU271
+ 1009 0046 1A69     		ldr	r2, [r3, #16]
+ 1010 0048 42F48032 		orr	r2, r2, #65536
+ 1011 004c 1A61     		str	r2, [r3, #16]
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 1012              		.loc 1 526 3 is_stmt 1 view .LVU272
+ 1013              	.LBB8:
+ 1014              	.LBI8:
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 1015              		.loc 2 877 27 view .LVU273
+ 1016              	.LBB9:
+ 1017              		.loc 2 879 3 view .LVU274
+ 1018              		.syntax unified
+ 1019              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1020 004e BFF34F8F 		dsb 0xF
+ 1021              	@ 0 "" 2
+ 1022              		.thumb
+ 1023              		.syntax unified
+ 1024              	.LBE9:
+ 1025              	.LBE8:
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1026              		.loc 1 527 1 is_stmt 0 view .LVU275
+ 1027 0052 7047     		bx	lr
+ 1028              	.LVL78:
+ 1029              	.L88:
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 1030              		.loc 1 500 15 view .LVU276
+ 1031 0054 4FF4807C 		mov	ip, #256
+ 1032 0058 DFE7     		b	.L85
+ 1033              	.L92:
+ 1034 005a 00BF     		.align	2
+ARM GAS  /tmp/cctoWaKX.s 			page 56
+
+
+ 1035              	.L91:
+ 1036 005c 003C0240 		.word	1073888256
+ 1037              		.cfi_endproc
+ 1038              	.LFE146:
+ 1040              		.section	.text.HAL_FLASHEx_Erase,"ax",%progbits
+ 1041              		.align	1
+ 1042              		.global	HAL_FLASHEx_Erase
+ 1043              		.syntax unified
+ 1044              		.thumb
+ 1045              		.thumb_func
+ 1046              		.fpu fpv5-d16
+ 1048              	HAL_FLASHEx_Erase:
+ 1049              	.LVL79:
+ 1050              	.LFB141:
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 1051              		.loc 1 157 1 is_stmt 1 view -0
+ 1052              		.cfi_startproc
+ 1053              		@ args = 0, pretend = 0, frame = 0
+ 1054              		@ frame_needed = 0, uses_anonymous_args = 0
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   uint32_t index = 0;
+ 1055              		.loc 1 158 3 view .LVU278
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 1056              		.loc 1 159 3 view .LVU279
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1057              		.loc 1 162 3 view .LVU280
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1058              		.loc 1 162 3 view .LVU281
+ 1059 0000 224B     		ldr	r3, .L107
+ 1060 0002 1B7D     		ldrb	r3, [r3, #20]	@ zero_extendqisi2
+ 1061 0004 012B     		cmp	r3, #1
+ 1062 0006 3DD0     		beq	.L100
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_ERROR;
+ 1063              		.loc 1 157 1 is_stmt 0 discriminator 2 view .LVU282
+ 1064 0008 70B5     		push	{r4, r5, r6, lr}
+ 1065              	.LCFI11:
+ 1066              		.cfi_def_cfa_offset 16
+ 1067              		.cfi_offset 4, -16
+ 1068              		.cfi_offset 5, -12
+ 1069              		.cfi_offset 6, -8
+ 1070              		.cfi_offset 14, -4
+ 1071 000a 0446     		mov	r4, r0
+ 1072 000c 0E46     		mov	r6, r1
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1073              		.loc 1 162 3 is_stmt 1 discriminator 2 view .LVU283
+ 1074 000e 1F4B     		ldr	r3, .L107
+ 1075 0010 0122     		movs	r2, #1
+ 1076 0012 1A75     		strb	r2, [r3, #20]
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1077              		.loc 1 162 3 discriminator 2 view .LVU284
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1078              		.loc 1 165 3 discriminator 2 view .LVU285
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1079              		.loc 1 168 3 discriminator 2 view .LVU286
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1080              		.loc 1 168 12 is_stmt 0 discriminator 2 view .LVU287
+ 1081 0014 4CF25030 		movw	r0, #50000
+ 1082              	.LVL80:
+ARM GAS  /tmp/cctoWaKX.s 			page 57
+
+
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1083              		.loc 1 168 12 discriminator 2 view .LVU288
+ 1084 0018 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1085              	.LVL81:
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 1086              		.loc 1 170 3 is_stmt 1 discriminator 2 view .LVU289
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 1087              		.loc 1 170 5 is_stmt 0 discriminator 2 view .LVU290
+ 1088 001c 0146     		mov	r1, r0
+ 1089 001e 60BB     		cbnz	r0, .L95
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+ 1090              		.loc 1 173 5 is_stmt 1 view .LVU291
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     
+ 1091              		.loc 1 173 18 is_stmt 0 view .LVU292
+ 1092 0020 4FF0FF33 		mov	r3, #-1
+ 1093 0024 3360     		str	r3, [r6]
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {
+ 1094              		.loc 1 175 5 is_stmt 1 view .LVU293
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {
+ 1095              		.loc 1 175 18 is_stmt 0 view .LVU294
+ 1096 0026 2368     		ldr	r3, [r4]
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     {
+ 1097              		.loc 1 175 7 view .LVU295
+ 1098 0028 012B     		cmp	r3, #1
+ 1099 002a 16D0     		beq	.L105
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1100              		.loc 1 193 7 is_stmt 1 view .LVU296
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       {
+ 1101              		.loc 1 196 7 view .LVU297
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       {
+ 1102              		.loc 1 196 17 is_stmt 0 view .LVU298
+ 1103 002c A568     		ldr	r5, [r4, #8]
+ 1104              	.LVL82:
+ 1105              	.L97:
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       {
+ 1106              		.loc 1 196 39 is_stmt 1 discriminator 1 view .LVU299
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       {
+ 1107              		.loc 1 196 58 is_stmt 0 discriminator 1 view .LVU300
+ 1108 002e E368     		ldr	r3, [r4, #12]
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       {
+ 1109              		.loc 1 196 82 discriminator 1 view .LVU301
+ 1110 0030 A268     		ldr	r2, [r4, #8]
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       {
+ 1111              		.loc 1 196 70 discriminator 1 view .LVU302
+ 1112 0032 1344     		add	r3, r3, r2
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       {
+ 1113              		.loc 1 196 7 discriminator 1 view .LVU303
+ 1114 0034 AB42     		cmp	r3, r5
+ 1115 0036 20D9     		bls	.L95
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1116              		.loc 1 198 9 is_stmt 1 view .LVU304
+ 1117 0038 217C     		ldrb	r1, [r4, #16]	@ zero_extendqisi2
+ 1118              	.LVL83:
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1119              		.loc 1 198 9 is_stmt 0 view .LVU305
+ 1120 003a 2846     		mov	r0, r5
+ 1121 003c FFF7FEFF 		bl	FLASH_Erase_Sector
+ARM GAS  /tmp/cctoWaKX.s 			page 58
+
+
+ 1122              	.LVL84:
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 1123              		.loc 1 201 9 is_stmt 1 view .LVU306
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         
+ 1124              		.loc 1 201 18 is_stmt 0 view .LVU307
+ 1125 0040 4CF25030 		movw	r0, #50000
+ 1126 0044 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1127              	.LVL85:
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1128              		.loc 1 204 9 is_stmt 1 view .LVU308
+ 1129 0048 114A     		ldr	r2, .L107+4
+ 1130 004a 1369     		ldr	r3, [r2, #16]
+ 1131 004c 23F0FA03 		bic	r3, r3, #250
+ 1132 0050 1361     		str	r3, [r2, #16]
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         {
+ 1133              		.loc 1 206 9 view .LVU309
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         {
+ 1134              		.loc 1 206 11 is_stmt 0 view .LVU310
+ 1135 0052 0146     		mov	r1, r0
+ 1136 0054 80B9     		cbnz	r0, .L106
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       {
+ 1137              		.loc 1 196 93 is_stmt 1 discriminator 2 view .LVU311
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       {
+ 1138              		.loc 1 196 98 is_stmt 0 discriminator 2 view .LVU312
+ 1139 0056 0135     		adds	r5, r5, #1
+ 1140              	.LVL86:
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       {
+ 1141              		.loc 1 196 98 discriminator 2 view .LVU313
+ 1142 0058 E9E7     		b	.L97
+ 1143              	.LVL87:
+ 1144              	.L105:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else
+ 1145              		.loc 1 179 7 is_stmt 1 view .LVU314
+ 1146 005a 6168     		ldr	r1, [r4, #4]
+ 1147 005c 207C     		ldrb	r0, [r4, #16]	@ zero_extendqisi2
+ 1148              	.LVL88:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else
+ 1149              		.loc 1 179 7 is_stmt 0 view .LVU315
+ 1150 005e FFF7FEFF 		bl	FLASH_MassErase
+ 1151              	.LVL89:
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       
+ 1152              		.loc 1 185 7 is_stmt 1 view .LVU316
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****       
+ 1153              		.loc 1 185 16 is_stmt 0 view .LVU317
+ 1154 0062 4CF25030 		movw	r0, #50000
+ 1155 0066 FFF7FEFF 		bl	FLASH_WaitForLastOperation
+ 1156              	.LVL90:
+ 1157 006a 0146     		mov	r1, r0
+ 1158              	.LVL91:
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 1159              		.loc 1 188 7 is_stmt 1 view .LVU318
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     }
+ 1160              		.loc 1 188 17 is_stmt 0 view .LVU319
+ 1161 006c 084A     		ldr	r2, .L107+4
+ 1162 006e 1069     		ldr	r0, [r2, #16]
+ 1163 0070 084B     		ldr	r3, .L107+8
+ 1164 0072 0340     		ands	r3, r3, r0
+ARM GAS  /tmp/cctoWaKX.s 			page 59
+
+
+ 1165 0074 1361     		str	r3, [r2, #16]
+ 1166 0076 00E0     		b	.L95
+ 1167              	.LVL92:
+ 1168              	.L106:
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****           break;
+ 1169              		.loc 1 209 11 is_stmt 1 view .LVU320
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****           break;
+ 1170              		.loc 1 209 24 is_stmt 0 view .LVU321
+ 1171 0078 3560     		str	r5, [r6]
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****         }
+ 1172              		.loc 1 210 11 is_stmt 1 view .LVU322
+ 1173              	.LVL93:
+ 1174              	.L95:
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1175              		.loc 1 217 3 view .LVU323
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1176              		.loc 1 217 3 view .LVU324
+ 1177 007a 044B     		ldr	r3, .L107
+ 1178 007c 0022     		movs	r2, #0
+ 1179 007e 1A75     		strb	r2, [r3, #20]
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1180              		.loc 1 217 3 view .LVU325
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 1181              		.loc 1 219 3 view .LVU326
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1182              		.loc 1 220 1 is_stmt 0 view .LVU327
+ 1183 0080 0846     		mov	r0, r1
+ 1184 0082 70BD     		pop	{r4, r5, r6, pc}
+ 1185              	.LVL94:
+ 1186              	.L100:
+ 1187              	.LCFI12:
+ 1188              		.cfi_def_cfa_offset 0
+ 1189              		.cfi_restore 4
+ 1190              		.cfi_restore 5
+ 1191              		.cfi_restore 6
+ 1192              		.cfi_restore 14
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1193              		.loc 1 162 3 view .LVU328
+ 1194 0084 0221     		movs	r1, #2
+ 1195              	.LVL95:
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1196              		.loc 1 220 1 view .LVU329
+ 1197 0086 0846     		mov	r0, r1
+ 1198              	.LVL96:
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1199              		.loc 1 220 1 view .LVU330
+ 1200 0088 7047     		bx	lr
+ 1201              	.L108:
+ 1202 008a 00BF     		.align	2
+ 1203              	.L107:
+ 1204 008c 00000000 		.word	pFlash
+ 1205 0090 003C0240 		.word	1073888256
+ 1206 0094 FB7FFFFF 		.word	-32773
+ 1207              		.cfi_endproc
+ 1208              	.LFE141:
+ 1210              		.section	.text.HAL_FLASHEx_Erase_IT,"ax",%progbits
+ 1211              		.align	1
+ARM GAS  /tmp/cctoWaKX.s 			page 60
+
+
+ 1212              		.global	HAL_FLASHEx_Erase_IT
+ 1213              		.syntax unified
+ 1214              		.thumb
+ 1215              		.thumb_func
+ 1216              		.fpu fpv5-d16
+ 1218              	HAL_FLASHEx_Erase_IT:
+ 1219              	.LVL97:
+ 1220              	.LFB142:
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1221              		.loc 1 230 1 is_stmt 1 view -0
+ 1222              		.cfi_startproc
+ 1223              		@ args = 0, pretend = 0, frame = 0
+ 1224              		@ frame_needed = 0, uses_anonymous_args = 0
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1225              		.loc 1 230 1 is_stmt 0 view .LVU332
+ 1226 0000 08B5     		push	{r3, lr}
+ 1227              	.LCFI13:
+ 1228              		.cfi_def_cfa_offset 8
+ 1229              		.cfi_offset 3, -8
+ 1230              		.cfi_offset 14, -4
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1231              		.loc 1 231 3 is_stmt 1 view .LVU333
+ 1232              	.LVL98:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1233              		.loc 1 234 3 view .LVU334
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1234              		.loc 1 234 3 view .LVU335
+ 1235 0002 174B     		ldr	r3, .L115
+ 1236 0004 1B7D     		ldrb	r3, [r3, #20]	@ zero_extendqisi2
+ 1237 0006 012B     		cmp	r3, #1
+ 1238 0008 27D0     		beq	.L112
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1239              		.loc 1 234 3 discriminator 2 view .LVU336
+ 1240 000a 154B     		ldr	r3, .L115
+ 1241 000c 0122     		movs	r2, #1
+ 1242 000e 1A75     		strb	r2, [r3, #20]
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1243              		.loc 1 234 3 discriminator 2 view .LVU337
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1244              		.loc 1 237 3 discriminator 2 view .LVU338
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 1245              		.loc 1 240 3 discriminator 2 view .LVU339
+ 1246 0010 144B     		ldr	r3, .L115+4
+ 1247 0012 1A69     		ldr	r2, [r3, #16]
+ 1248 0014 42F08072 		orr	r2, r2, #16777216
+ 1249 0018 1A61     		str	r2, [r3, #16]
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   
+ 1250              		.loc 1 243 3 discriminator 2 view .LVU340
+ 1251 001a 1A69     		ldr	r2, [r3, #16]
+ 1252 001c 42F00072 		orr	r2, r2, #33554432
+ 1253 0020 1A61     		str	r2, [r3, #16]
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****                          FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);  
+ 1254              		.loc 1 246 3 discriminator 2 view .LVU341
+ 1255 0022 F322     		movs	r2, #243
+ 1256 0024 DA60     		str	r2, [r3, #12]
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 1257              		.loc 1 249 3 discriminator 2 view .LVU342
+ARM GAS  /tmp/cctoWaKX.s 			page 61
+
+
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 1258              		.loc 1 249 16 is_stmt 0 discriminator 2 view .LVU343
+ 1259 0026 0368     		ldr	r3, [r0]
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   {
+ 1260              		.loc 1 249 5 discriminator 2 view .LVU344
+ 1261 0028 012B     		cmp	r3, #1
+ 1262 002a 0DD0     		beq	.L114
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1263              		.loc 1 264 5 is_stmt 1 view .LVU345
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+ 1264              		.loc 1 266 5 view .LVU346
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+ 1265              		.loc 1 266 29 is_stmt 0 view .LVU347
+ 1266 002c 0C4B     		ldr	r3, .L115
+ 1267 002e 0122     		movs	r2, #1
+ 1268 0030 1A70     		strb	r2, [r3]
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.Sector = pEraseInit->Sector;
+ 1269              		.loc 1 267 5 is_stmt 1 view .LVU348
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.Sector = pEraseInit->Sector;
+ 1270              		.loc 1 267 41 is_stmt 0 view .LVU349
+ 1271 0032 C268     		ldr	r2, [r0, #12]
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.Sector = pEraseInit->Sector;
+ 1272              		.loc 1 267 29 view .LVU350
+ 1273 0034 5A60     		str	r2, [r3, #4]
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
+ 1274              		.loc 1 268 5 is_stmt 1 view .LVU351
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
+ 1275              		.loc 1 268 31 is_stmt 0 view .LVU352
+ 1276 0036 8268     		ldr	r2, [r0, #8]
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****     pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
+ 1277              		.loc 1 268 19 view .LVU353
+ 1278 0038 DA60     		str	r2, [r3, #12]
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1279              		.loc 1 269 5 is_stmt 1 view .LVU354
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1280              		.loc 1 269 30 is_stmt 0 view .LVU355
+ 1281 003a 017C     		ldrb	r1, [r0, #16]	@ zero_extendqisi2
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1282              		.loc 1 269 28 view .LVU356
+ 1283 003c 1972     		strb	r1, [r3, #8]
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 1284              		.loc 1 272 5 is_stmt 1 view .LVU357
+ 1285 003e 8068     		ldr	r0, [r0, #8]
+ 1286              	.LVL99:
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c ****   }
+ 1287              		.loc 1 272 5 is_stmt 0 view .LVU358
+ 1288 0040 FFF7FEFF 		bl	FLASH_Erase_Sector
+ 1289              	.LVL100:
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 1290              		.loc 1 275 10 view .LVU359
+ 1291 0044 0020     		movs	r0, #0
+ 1292              	.L110:
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1293              		.loc 1 276 1 view .LVU360
+ 1294 0046 08BD     		pop	{r3, pc}
+ 1295              	.LVL101:
+ 1296              	.L114:
+ARM GAS  /tmp/cctoWaKX.s 			page 62
+
+
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK)    
+ 1297              		.loc 1 252 5 is_stmt 1 view .LVU361
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK)    
+ 1298              		.loc 1 252 29 is_stmt 0 view .LVU362
+ 1299 0048 054B     		ldr	r3, .L115
+ 1300 004a 0222     		movs	r2, #2
+ 1301 004c 1A70     		strb	r2, [r3]
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else
+ 1302              		.loc 1 254 5 is_stmt 1 view .LVU363
+ 1303 004e 4168     		ldr	r1, [r0, #4]
+ 1304 0050 007C     		ldrb	r0, [r0, #16]	@ zero_extendqisi2
+ 1305              	.LVL102:
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else
+ 1306              		.loc 1 254 5 is_stmt 0 view .LVU364
+ 1307 0052 FFF7FEFF 		bl	FLASH_MassErase
+ 1308              	.LVL103:
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** }
+ 1309              		.loc 1 275 10 view .LVU365
+ 1310 0056 0020     		movs	r0, #0
+ 1311 0058 F5E7     		b	.L110
+ 1312              	.LVL104:
+ 1313              	.L112:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1314              		.loc 1 234 3 view .LVU366
+ 1315 005a 0220     		movs	r0, #2
+ 1316              	.LVL105:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** 
+ 1317              		.loc 1 234 3 view .LVU367
+ 1318 005c F3E7     		b	.L110
+ 1319              	.L116:
+ 1320 005e 00BF     		.align	2
+ 1321              	.L115:
+ 1322 0060 00000000 		.word	pFlash
+ 1323 0064 003C0240 		.word	1073888256
+ 1324              		.cfi_endproc
+ 1325              	.LFE142:
+ 1327              		.text
+ 1328              	.Letext0:
+ 1329              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 1330              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 1331              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 1332              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h"
+ 1333              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h"
+ARM GAS  /tmp/cctoWaKX.s 			page 63
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_flash_ex.c
+     /tmp/cctoWaKX.s:17     .text.FLASH_MassErase:0000000000000000 $t
+     /tmp/cctoWaKX.s:24     .text.FLASH_MassErase:0000000000000000 FLASH_MassErase
+     /tmp/cctoWaKX.s:106    .text.FLASH_MassErase:0000000000000048 $d
+     /tmp/cctoWaKX.s:111    .text.FLASH_OB_GetWRP:0000000000000000 $t
+     /tmp/cctoWaKX.s:117    .text.FLASH_OB_GetWRP:0000000000000000 FLASH_OB_GetWRP
+     /tmp/cctoWaKX.s:135    .text.FLASH_OB_GetWRP:000000000000000c $d
+     /tmp/cctoWaKX.s:141    .text.FLASH_OB_GetUser:0000000000000000 $t
+     /tmp/cctoWaKX.s:147    .text.FLASH_OB_GetUser:0000000000000000 FLASH_OB_GetUser
+     /tmp/cctoWaKX.s:165    .text.FLASH_OB_GetUser:000000000000000c $d
+     /tmp/cctoWaKX.s:171    .text.FLASH_OB_BOR_LevelConfig:0000000000000000 $t
+     /tmp/cctoWaKX.s:177    .text.FLASH_OB_BOR_LevelConfig:0000000000000000 FLASH_OB_BOR_LevelConfig
+     /tmp/cctoWaKX.s:201    .text.FLASH_OB_BOR_LevelConfig:0000000000000010 $d
+     /tmp/cctoWaKX.s:206    .text.FLASH_OB_GetRDP:0000000000000000 $t
+     /tmp/cctoWaKX.s:212    .text.FLASH_OB_GetRDP:0000000000000000 FLASH_OB_GetRDP
+     /tmp/cctoWaKX.s:246    .text.FLASH_OB_GetRDP:0000000000000018 $d
+     /tmp/cctoWaKX.s:251    .text.FLASH_OB_GetBOR:0000000000000000 $t
+     /tmp/cctoWaKX.s:257    .text.FLASH_OB_GetBOR:0000000000000000 FLASH_OB_GetBOR
+     /tmp/cctoWaKX.s:274    .text.FLASH_OB_GetBOR:000000000000000c $d
+     /tmp/cctoWaKX.s:279    .text.FLASH_OB_GetBootAddress:0000000000000000 $t
+     /tmp/cctoWaKX.s:285    .text.FLASH_OB_GetBootAddress:0000000000000000 FLASH_OB_GetBootAddress
+     /tmp/cctoWaKX.s:324    .text.FLASH_OB_GetBootAddress:0000000000000014 $d
+     /tmp/cctoWaKX.s:329    .text.FLASH_OB_EnableWRP:0000000000000000 $t
+     /tmp/cctoWaKX.s:335    .text.FLASH_OB_EnableWRP:0000000000000000 FLASH_OB_EnableWRP
+     /tmp/cctoWaKX.s:377    .text.FLASH_OB_EnableWRP:000000000000001c $d
+     /tmp/cctoWaKX.s:382    .text.FLASH_OB_DisableWRP:0000000000000000 $t
+     /tmp/cctoWaKX.s:388    .text.FLASH_OB_DisableWRP:0000000000000000 FLASH_OB_DisableWRP
+     /tmp/cctoWaKX.s:430    .text.FLASH_OB_DisableWRP:0000000000000018 $d
+     /tmp/cctoWaKX.s:435    .text.FLASH_OB_RDP_LevelConfig:0000000000000000 $t
+     /tmp/cctoWaKX.s:441    .text.FLASH_OB_RDP_LevelConfig:0000000000000000 FLASH_OB_RDP_LevelConfig
+     /tmp/cctoWaKX.s:479    .text.FLASH_OB_RDP_LevelConfig:0000000000000014 $d
+     /tmp/cctoWaKX.s:484    .text.FLASH_OB_UserConfig:0000000000000000 $t
+     /tmp/cctoWaKX.s:490    .text.FLASH_OB_UserConfig:0000000000000000 FLASH_OB_UserConfig
+     /tmp/cctoWaKX.s:576    .text.FLASH_OB_UserConfig:000000000000003c $d
+     /tmp/cctoWaKX.s:582    .text.FLASH_OB_BootAddressConfig:0000000000000000 $t
+     /tmp/cctoWaKX.s:588    .text.FLASH_OB_BootAddressConfig:0000000000000000 FLASH_OB_BootAddressConfig
+     /tmp/cctoWaKX.s:645    .text.FLASH_OB_BootAddressConfig:0000000000000030 $d
+     /tmp/cctoWaKX.s:651    .text.HAL_FLASHEx_OBProgram:0000000000000000 $t
+     /tmp/cctoWaKX.s:658    .text.HAL_FLASHEx_OBProgram:0000000000000000 HAL_FLASHEx_OBProgram
+     /tmp/cctoWaKX.s:857    .text.HAL_FLASHEx_OBProgram:00000000000000c0 $d
+     /tmp/cctoWaKX.s:862    .text.HAL_FLASHEx_OBGetConfig:0000000000000000 $t
+     /tmp/cctoWaKX.s:869    .text.HAL_FLASHEx_OBGetConfig:0000000000000000 HAL_FLASHEx_OBGetConfig
+     /tmp/cctoWaKX.s:932    .text.FLASH_Erase_Sector:0000000000000000 $t
+     /tmp/cctoWaKX.s:939    .text.FLASH_Erase_Sector:0000000000000000 FLASH_Erase_Sector
+     /tmp/cctoWaKX.s:1036   .text.FLASH_Erase_Sector:000000000000005c $d
+     /tmp/cctoWaKX.s:1041   .text.HAL_FLASHEx_Erase:0000000000000000 $t
+     /tmp/cctoWaKX.s:1048   .text.HAL_FLASHEx_Erase:0000000000000000 HAL_FLASHEx_Erase
+     /tmp/cctoWaKX.s:1204   .text.HAL_FLASHEx_Erase:000000000000008c $d
+     /tmp/cctoWaKX.s:1211   .text.HAL_FLASHEx_Erase_IT:0000000000000000 $t
+     /tmp/cctoWaKX.s:1218   .text.HAL_FLASHEx_Erase_IT:0000000000000000 HAL_FLASHEx_Erase_IT
+     /tmp/cctoWaKX.s:1322   .text.HAL_FLASHEx_Erase_IT:0000000000000060 $d
+
+UNDEFINED SYMBOLS
+FLASH_WaitForLastOperation
+pFlash
diff --git a/build/stm32f7xx_hal_flash_ex.o b/build/stm32f7xx_hal_flash_ex.o
new file mode 100644
index 0000000..db806f8
Binary files /dev/null and b/build/stm32f7xx_hal_flash_ex.o differ
diff --git a/build/stm32f7xx_hal_gpio.d b/build/stm32f7xx_hal_gpio.d
new file mode 100644
index 0000000..452faa4
--- /dev/null
+++ b/build/stm32f7xx_hal_gpio.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_gpio.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_gpio.lst b/build/stm32f7xx_hal_gpio.lst
new file mode 100644
index 0000000..9befbfb
--- /dev/null
+++ b/build/stm32f7xx_hal_gpio.lst
@@ -0,0 +1,1791 @@
+ARM GAS  /tmp/ccJPacwp.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_gpio.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.HAL_GPIO_Init,"ax",%progbits
+  17              		.align	1
+  18              		.global	HAL_GPIO_Init
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	HAL_GPIO_Init:
+  26              	.LVL0:
+  27              	.LFB141:
+  28              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @file    stm32f7xx_hal_gpio.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @brief   GPIO HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *           + IO operation functions
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   ******************************************************************************
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @attention
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * Copyright (c) 2017 STMicroelectronics.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * All rights reserved.
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * in the root directory of this software component.
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   ******************************************************************************
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   @verbatim
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   ==============================================================================
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****                     ##### GPIO Peripheral features #####
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   ==============================================================================
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   [..]
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   in several modes:
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   (+) Input mode
+ARM GAS  /tmp/ccJPacwp.s 			page 2
+
+
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   (+) Analog mode
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   (+) Output mode
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   (+) Alternate function mode
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   (+) External interrupt/event lines
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   [..]
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   During and just after reset, the alternate functions and external interrupt
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   lines are not active and the I/O ports are configured in input floating mode.
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   [..]
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   activated or not.
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   [..]
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   type and the IO speed can be selected depending on the VDD value.
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   [..]
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   All ports have external interrupt/event capability. To use external interrupt
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   lines, the port must be configured in input mode. All available GPIO pins are
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   [..]
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   The external interrupt/event controller consists of up to 23 edge detectors
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   (16 lines are connected to GPIO) for generating event/interrupt requests (each
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   input line can be independently configured to select the type (interrupt or event)
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   and the corresponding trigger event (rising or falling or both). Each line can
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   also be masked independently.
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****                      ##### How to use this driver #####
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   ==============================================================================
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   [..]
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****              structure.
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         (++) In case of Output or alternate function mode selection: the speed is
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****              configured through "Speed" member from GPIO_InitTypeDef structure.
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         (++) In alternate mode is selection, the alternate function connected to the IO
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****              is configured through "Alternate" member from GPIO_InitTypeDef structure.
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         (++) Analog mode is required when a pin is to be used as ADC channel
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****              or DAC output.
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         (++) In case of external interrupt/event selection the "Mode" member from
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****              GPIO_InitTypeDef structure select the type (interrupt or event) and
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****              the corresponding trigger event (rising or falling or both).
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         HAL_NVIC_EnableIRQ().
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     (#) To set/reset the level of a pin configured in output mode use
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ARM GAS  /tmp/ccJPacwp.s 			page 3
+
+
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     (#) During and just after reset, the alternate functions are not
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         active and the GPIO pins are configured in input floating mode (except JTAG
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         pins).
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         priority over the GPIO function.
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         The HSE has priority over the GPIO function.
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   @endverbatim
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   ******************************************************************************
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Includes ------------------------------------------------------------------*/
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** #include "stm32f7xx_hal.h"
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @addtogroup STM32F7xx_HAL_Driver
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @{
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @defgroup GPIO GPIO
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @brief GPIO HAL module driver
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @{
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** #ifdef HAL_GPIO_MODULE_ENABLED
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private typedef -----------------------------------------------------------*/
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private define ------------------------------------------------------------*/
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @addtogroup GPIO_Private_Constants GPIO Private Constants
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @{
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** #define GPIO_NUMBER           ((uint32_t)16U)
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /**
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @}
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private macro -------------------------------------------------------------*/
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private variables ---------------------------------------------------------*/
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private function prototypes -----------------------------------------------*/
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private functions ---------------------------------------------------------*/
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Exported functions --------------------------------------------------------*/
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @{
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****  *  @brief    Initialization and Configuration functions
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****  *
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** @verbatim
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****  ===============================================================================
+ARM GAS  /tmp/ccJPacwp.s 			page 4
+
+
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****               ##### Initialization and de-initialization functions #####
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****  ===============================================================================
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   [..]
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     This section provides functions allowing to initialize and de-initialize the GPIOs
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     to be ready for use.
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** @endverbatim
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @{
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /**
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *         the configuration information for the specified GPIO peripheral.
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @retval None
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** {
+  29              		.loc 1 163 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 8
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   uint32_t position = 0x00;
+  33              		.loc 1 164 3 view .LVU1
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   uint32_t ioposition = 0x00;
+  34              		.loc 1 165 3 view .LVU2
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   uint32_t iocurrent = 0x00;
+  35              		.loc 1 166 3 view .LVU3
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   uint32_t temp = 0x00;
+  36              		.loc 1 167 3 view .LVU4
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Check the parameters */
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  37              		.loc 1 170 3 view .LVU5
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  38              		.loc 1 171 3 view .LVU6
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+  39              		.loc 1 172 3 view .LVU7
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Configure the port pins */
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   for (position = 0; position < GPIO_NUMBER; position++)
+  40              		.loc 1 175 3 view .LVU8
+  41              		.loc 1 175 17 is_stmt 0 view .LVU9
+  42 0000 0023     		movs	r3, #0
+  43              	.LVL1:
+  44              		.loc 1 175 22 is_stmt 1 view .LVU10
+  45              		.loc 1 175 3 is_stmt 0 view .LVU11
+  46 0002 0F2B     		cmp	r3, #15
+  47 0004 00F2EF80 		bhi	.L26
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   uint32_t position = 0x00;
+  48              		.loc 1 163 1 view .LVU12
+  49 0008 70B5     		push	{r4, r5, r6, lr}
+  50              	.LCFI0:
+  51              		.cfi_def_cfa_offset 16
+  52              		.cfi_offset 4, -16
+  53              		.cfi_offset 5, -12
+ARM GAS  /tmp/ccJPacwp.s 			page 5
+
+
+  54              		.cfi_offset 6, -8
+  55              		.cfi_offset 14, -4
+  56 000a 82B0     		sub	sp, sp, #8
+  57              	.LCFI1:
+  58              		.cfi_def_cfa_offset 24
+  59 000c 61E0     		b	.L12
+  60              	.LVL2:
+  61              	.L28:
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     /* Get the IO position */
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     ioposition = ((uint32_t)0x01) << position;
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     /* Get the current IO position */
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     if (iocurrent == ioposition)
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     {
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /*--------------------- GPIO Mode Configuration ------------------------*/
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /* In case of Output or Alternate function mode selection */
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Check the Speed parameter */
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+  62              		.loc 1 189 9 is_stmt 1 view .LVU13
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Configure the IO Speed */
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp = GPIOx->OSPEEDR;
+  63              		.loc 1 191 9 view .LVU14
+  64              		.loc 1 191 14 is_stmt 0 view .LVU15
+  65 000e 8568     		ldr	r5, [r0, #8]
+  66              	.LVL3:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+  67              		.loc 1 192 9 is_stmt 1 view .LVU16
+  68              		.loc 1 192 55 is_stmt 0 view .LVU17
+  69 0010 5E00     		lsls	r6, r3, #1
+  70              		.loc 1 192 42 view .LVU18
+  71 0012 0324     		movs	r4, #3
+  72 0014 B440     		lsls	r4, r4, r6
+  73              		.loc 1 192 14 view .LVU19
+  74 0016 25EA0405 		bic	r5, r5, r4
+  75              	.LVL4:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= (GPIO_Init->Speed << (position * 2));
+  76              		.loc 1 193 9 is_stmt 1 view .LVU20
+  77              		.loc 1 193 27 is_stmt 0 view .LVU21
+  78 001a CC68     		ldr	r4, [r1, #12]
+  79              		.loc 1 193 35 view .LVU22
+  80 001c B440     		lsls	r4, r4, r6
+  81              		.loc 1 193 14 view .LVU23
+  82 001e 2C43     		orrs	r4, r4, r5
+  83              	.LVL5:
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         GPIOx->OSPEEDR = temp;
+  84              		.loc 1 194 9 is_stmt 1 view .LVU24
+  85              		.loc 1 194 24 is_stmt 0 view .LVU25
+  86 0020 8460     		str	r4, [r0, #8]
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Configure the IO Output Type */
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp = GPIOx->OTYPER;
+  87              		.loc 1 197 9 is_stmt 1 view .LVU26
+  88              		.loc 1 197 14 is_stmt 0 view .LVU27
+ARM GAS  /tmp/ccJPacwp.s 			page 6
+
+
+  89 0022 4568     		ldr	r5, [r0, #4]
+  90              	.LVL6:
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+  91              		.loc 1 198 9 is_stmt 1 view .LVU28
+  92              		.loc 1 198 14 is_stmt 0 view .LVU29
+  93 0024 25EA0205 		bic	r5, r5, r2
+  94              	.LVL7:
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+  95              		.loc 1 199 9 is_stmt 1 view .LVU30
+  96              		.loc 1 199 29 is_stmt 0 view .LVU31
+  97 0028 4C68     		ldr	r4, [r1, #4]
+  98              		.loc 1 199 51 view .LVU32
+  99 002a C4F30012 		ubfx	r2, r4, #4, #1
+ 100              	.LVL8:
+ 101              		.loc 1 199 71 view .LVU33
+ 102 002e 9A40     		lsls	r2, r2, r3
+ 103              		.loc 1 199 14 view .LVU34
+ 104 0030 2A43     		orrs	r2, r2, r5
+ 105              	.LVL9:
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         GPIOx->OTYPER = temp;
+ 106              		.loc 1 200 9 is_stmt 1 view .LVU35
+ 107              		.loc 1 200 23 is_stmt 0 view .LVU36
+ 108 0032 4260     		str	r2, [r0, #4]
+ 109 0034 5BE0     		b	.L4
+ 110              	.LVL10:
+ 111              	.L29:
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       }
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Check the Pull parameter */
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Activate the Pull-up or Pull down resistor for the current IO */
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp = GPIOx->PUPDR;
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((GPIO_Init->Pull) << (position * 2));
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         GPIOx->PUPDR = temp;
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       }
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /* In case of Alternate function mode selection */
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Check the Alternate function parameter */
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+ 112              		.loc 1 219 9 is_stmt 1 view .LVU37
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Configure Alternate function mapped with the current IO */
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp = GPIOx->AFR[position >> 3];
+ 113              		.loc 1 222 9 view .LVU38
+ 114              		.loc 1 222 36 is_stmt 0 view .LVU39
+ 115 0036 DC08     		lsrs	r4, r3, #3
+ 116              		.loc 1 222 14 view .LVU40
+ 117 0038 0834     		adds	r4, r4, #8
+ 118 003a 50F82460 		ldr	r6, [r0, r4, lsl #2]
+ 119              	.LVL11:
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ARM GAS  /tmp/ccJPacwp.s 			page 7
+
+
+ 120              		.loc 1 223 9 is_stmt 1 view .LVU41
+ 121              		.loc 1 223 37 is_stmt 0 view .LVU42
+ 122 003e 03F00702 		and	r2, r3, #7
+ 123              		.loc 1 223 75 view .LVU43
+ 124 0042 9500     		lsls	r5, r2, #2
+ 125              		.loc 1 223 33 view .LVU44
+ 126 0044 0F22     		movs	r2, #15
+ 127 0046 AA40     		lsls	r2, r2, r5
+ 128              		.loc 1 223 14 view .LVU45
+ 129 0048 26EA020E 		bic	lr, r6, r2
+ 130              	.LVL12:
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+ 131              		.loc 1 224 9 is_stmt 1 view .LVU46
+ 132              		.loc 1 224 38 is_stmt 0 view .LVU47
+ 133 004c 0A69     		ldr	r2, [r1, #16]
+ 134              		.loc 1 224 51 view .LVU48
+ 135 004e AA40     		lsls	r2, r2, r5
+ 136              		.loc 1 224 14 view .LVU49
+ 137 0050 42EA0E02 		orr	r2, r2, lr
+ 138              	.LVL13:
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         GPIOx->AFR[position >> 3] = temp;
+ 139              		.loc 1 225 9 is_stmt 1 view .LVU50
+ 140              		.loc 1 225 35 is_stmt 0 view .LVU51
+ 141 0054 40F82420 		str	r2, [r0, r4, lsl #2]
+ 142 0058 5DE0     		b	.L6
+ 143              	.LVL14:
+ 144              	.L30:
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       }
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       temp = GPIOx->MODER;
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /*--------------------- EXTI Mode Configuration ------------------------*/
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /* Configure the External Interrupt or event for the current IO */
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Enable SYSCFG Clock */
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp = SYSCFG->EXTICR[position >> 2];
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+ 145              		.loc 1 243 29 view .LVU52
+ 146 005a 0922     		movs	r2, #9
+ 147 005c 00E0     		b	.L7
+ 148              	.L13:
+ 149              		.loc 1 243 18 view .LVU53
+ 150 005e 0022     		movs	r2, #0
+ 151              	.L7:
+ 152              		.loc 1 243 52 discriminator 40 view .LVU54
+ 153 0060 02FA0EF2 		lsl	r2, r2, lr
+ 154              		.loc 1 243 14 discriminator 40 view .LVU55
+ 155 0064 2A43     		orrs	r2, r2, r5
+ 156              	.LVL15:
+ARM GAS  /tmp/ccJPacwp.s 			page 8
+
+
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 157              		.loc 1 244 9 is_stmt 1 discriminator 40 view .LVU56
+ 158              		.loc 1 244 39 is_stmt 0 discriminator 40 view .LVU57
+ 159 0066 0234     		adds	r4, r4, #2
+ 160 0068 5F4D     		ldr	r5, .L31
+ 161 006a 45F82420 		str	r2, [r5, r4, lsl #2]
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Clear Rising Falling edge configuration */
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp = EXTI->RTSR;
+ 162              		.loc 1 247 9 is_stmt 1 discriminator 40 view .LVU58
+ 163              		.loc 1 247 14 is_stmt 0 discriminator 40 view .LVU59
+ 164 006e 5F4A     		ldr	r2, .L31+4
+ 165              	.LVL16:
+ 166              		.loc 1 247 14 discriminator 40 view .LVU60
+ 167 0070 9468     		ldr	r4, [r2, #8]
+ 168              	.LVL17:
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~((uint32_t)iocurrent);
+ 169              		.loc 1 248 9 is_stmt 1 discriminator 40 view .LVU61
+ 170              		.loc 1 248 17 is_stmt 0 discriminator 40 view .LVU62
+ 171 0072 6FEA0C02 		mvn	r2, ip
+ 172              		.loc 1 248 14 discriminator 40 view .LVU63
+ 173 0076 24EA0C05 		bic	r5, r4, ip
+ 174              	.LVL18:
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
+ 175              		.loc 1 249 9 is_stmt 1 discriminator 40 view .LVU64
+ 176              		.loc 1 249 23 is_stmt 0 discriminator 40 view .LVU65
+ 177 007a 4E68     		ldr	r6, [r1, #4]
+ 178              		.loc 1 249 12 discriminator 40 view .LVU66
+ 179 007c 16F4801F 		tst	r6, #1048576
+ 180 0080 01D0     		beq	.L8
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         {
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****           temp |= iocurrent;
+ 181              		.loc 1 251 11 is_stmt 1 view .LVU67
+ 182              		.loc 1 251 16 is_stmt 0 view .LVU68
+ 183 0082 4CEA0405 		orr	r5, ip, r4
+ 184              	.LVL19:
+ 185              	.L8:
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         }
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->RTSR = temp;
+ 186              		.loc 1 253 9 is_stmt 1 view .LVU69
+ 187              		.loc 1 253 20 is_stmt 0 view .LVU70
+ 188 0086 594C     		ldr	r4, .L31+4
+ 189 0088 A560     		str	r5, [r4, #8]
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp = EXTI->FTSR;
+ 190              		.loc 1 255 9 is_stmt 1 view .LVU71
+ 191              		.loc 1 255 14 is_stmt 0 view .LVU72
+ 192 008a E468     		ldr	r4, [r4, #12]
+ 193              	.LVL20:
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~((uint32_t)iocurrent);
+ 194              		.loc 1 256 9 is_stmt 1 view .LVU73
+ 195              		.loc 1 256 14 is_stmt 0 view .LVU74
+ 196 008c 02EA0405 		and	r5, r2, r4
+ 197              	.LVL21:
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
+ 198              		.loc 1 257 9 is_stmt 1 view .LVU75
+ 199              		.loc 1 257 23 is_stmt 0 view .LVU76
+ARM GAS  /tmp/ccJPacwp.s 			page 9
+
+
+ 200 0090 4E68     		ldr	r6, [r1, #4]
+ 201              		.loc 1 257 12 view .LVU77
+ 202 0092 16F4001F 		tst	r6, #2097152
+ 203 0096 01D0     		beq	.L9
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         {
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****           temp |= iocurrent;
+ 204              		.loc 1 259 11 is_stmt 1 view .LVU78
+ 205              		.loc 1 259 16 is_stmt 0 view .LVU79
+ 206 0098 4CEA0405 		orr	r5, ip, r4
+ 207              	.LVL22:
+ 208              	.L9:
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         }
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->FTSR = temp;
+ 209              		.loc 1 261 9 is_stmt 1 view .LVU80
+ 210              		.loc 1 261 20 is_stmt 0 view .LVU81
+ 211 009c 534C     		ldr	r4, .L31+4
+ 212 009e E560     		str	r5, [r4, #12]
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp = EXTI->EMR;
+ 213              		.loc 1 263 9 is_stmt 1 view .LVU82
+ 214              		.loc 1 263 14 is_stmt 0 view .LVU83
+ 215 00a0 6468     		ldr	r4, [r4, #4]
+ 216              	.LVL23:
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~((uint32_t)iocurrent);
+ 217              		.loc 1 264 9 is_stmt 1 view .LVU84
+ 218              		.loc 1 264 14 is_stmt 0 view .LVU85
+ 219 00a2 02EA0405 		and	r5, r2, r4
+ 220              	.LVL24:
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
+ 221              		.loc 1 265 9 is_stmt 1 view .LVU86
+ 222              		.loc 1 265 23 is_stmt 0 view .LVU87
+ 223 00a6 4E68     		ldr	r6, [r1, #4]
+ 224              		.loc 1 265 12 view .LVU88
+ 225 00a8 16F4003F 		tst	r6, #131072
+ 226 00ac 01D0     		beq	.L10
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         {
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****           temp |= iocurrent;
+ 227              		.loc 1 267 11 is_stmt 1 view .LVU89
+ 228              		.loc 1 267 16 is_stmt 0 view .LVU90
+ 229 00ae 4CEA0405 		orr	r5, ip, r4
+ 230              	.LVL25:
+ 231              	.L10:
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         }
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->EMR = temp;
+ 232              		.loc 1 269 9 is_stmt 1 view .LVU91
+ 233              		.loc 1 269 19 is_stmt 0 view .LVU92
+ 234 00b2 4E4C     		ldr	r4, .L31+4
+ 235 00b4 6560     		str	r5, [r4, #4]
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Clear EXTI line configuration */
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp = EXTI->IMR;
+ 236              		.loc 1 272 9 is_stmt 1 view .LVU93
+ 237              		.loc 1 272 14 is_stmt 0 view .LVU94
+ 238 00b6 2468     		ldr	r4, [r4]
+ 239              	.LVL26:
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~((uint32_t)iocurrent);
+ 240              		.loc 1 273 9 is_stmt 1 view .LVU95
+ARM GAS  /tmp/ccJPacwp.s 			page 10
+
+
+ 241              		.loc 1 273 14 is_stmt 0 view .LVU96
+ 242 00b8 2240     		ands	r2, r2, r4
+ 243              	.LVL27:
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
+ 244              		.loc 1 274 9 is_stmt 1 view .LVU97
+ 245              		.loc 1 274 23 is_stmt 0 view .LVU98
+ 246 00ba 4D68     		ldr	r5, [r1, #4]
+ 247              		.loc 1 274 12 view .LVU99
+ 248 00bc 15F4803F 		tst	r5, #65536
+ 249 00c0 01D0     		beq	.L11
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         {
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****           temp |= iocurrent;
+ 250              		.loc 1 276 11 is_stmt 1 view .LVU100
+ 251              		.loc 1 276 16 is_stmt 0 view .LVU101
+ 252 00c2 4CEA0402 		orr	r2, ip, r4
+ 253              	.LVL28:
+ 254              	.L11:
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         }
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->IMR = temp;
+ 255              		.loc 1 278 9 is_stmt 1 view .LVU102
+ 256              		.loc 1 278 19 is_stmt 0 view .LVU103
+ 257 00c6 494C     		ldr	r4, .L31+4
+ 258 00c8 2260     		str	r2, [r4]
+ 259              	.LVL29:
+ 260              	.L3:
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 261              		.loc 1 175 46 is_stmt 1 discriminator 2 view .LVU104
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 262              		.loc 1 175 54 is_stmt 0 discriminator 2 view .LVU105
+ 263 00ca 0133     		adds	r3, r3, #1
+ 264              	.LVL30:
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 265              		.loc 1 175 22 is_stmt 1 discriminator 2 view .LVU106
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 266              		.loc 1 175 3 is_stmt 0 discriminator 2 view .LVU107
+ 267 00cc 0F2B     		cmp	r3, #15
+ 268 00ce 00F28880 		bhi	.L27
+ 269              	.LVL31:
+ 270              	.L12:
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     /* Get the current IO position */
+ 271              		.loc 1 178 5 is_stmt 1 view .LVU108
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     /* Get the current IO position */
+ 272              		.loc 1 178 16 is_stmt 0 view .LVU109
+ 273 00d2 0122     		movs	r2, #1
+ 274 00d4 9A40     		lsls	r2, r2, r3
+ 275              	.LVL32:
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 276              		.loc 1 180 5 is_stmt 1 view .LVU110
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 277              		.loc 1 180 37 is_stmt 0 view .LVU111
+ 278 00d6 0C68     		ldr	r4, [r1]
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 279              		.loc 1 180 15 view .LVU112
+ 280 00d8 04EA020C 		and	ip, r4, r2
+ 281              	.LVL33:
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     {
+ 282              		.loc 1 182 5 is_stmt 1 view .LVU113
+ARM GAS  /tmp/ccJPacwp.s 			page 11
+
+
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     {
+ 283              		.loc 1 182 8 is_stmt 0 view .LVU114
+ 284 00dc 32EA0404 		bics	r4, r2, r4
+ 285 00e0 F3D1     		bne	.L3
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 286              		.loc 1 186 7 is_stmt 1 view .LVU115
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 287              		.loc 1 186 22 is_stmt 0 view .LVU116
+ 288 00e2 4C68     		ldr	r4, [r1, #4]
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 289              		.loc 1 186 29 view .LVU117
+ 290 00e4 04F00304 		and	r4, r4, #3
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 291              		.loc 1 186 58 view .LVU118
+ 292 00e8 013C     		subs	r4, r4, #1
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 293              		.loc 1 186 10 view .LVU119
+ 294 00ea 012C     		cmp	r4, #1
+ 295 00ec 8FD9     		bls	.L28
+ 296              	.LVL34:
+ 297              	.L4:
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 298              		.loc 1 203 7 is_stmt 1 view .LVU120
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 299              		.loc 1 203 21 is_stmt 0 view .LVU121
+ 300 00ee 4A68     		ldr	r2, [r1, #4]
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 301              		.loc 1 203 28 view .LVU122
+ 302 00f0 02F00302 		and	r2, r2, #3
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 303              		.loc 1 203 10 view .LVU123
+ 304 00f4 032A     		cmp	r2, #3
+ 305 00f6 09D0     		beq	.L5
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 306              		.loc 1 206 9 is_stmt 1 view .LVU124
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ 307              		.loc 1 209 9 view .LVU125
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ 308              		.loc 1 209 14 is_stmt 0 view .LVU126
+ 309 00f8 C468     		ldr	r4, [r0, #12]
+ 310              	.LVL35:
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((GPIO_Init->Pull) << (position * 2));
+ 311              		.loc 1 210 9 is_stmt 1 view .LVU127
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((GPIO_Init->Pull) << (position * 2));
+ 312              		.loc 1 210 50 is_stmt 0 view .LVU128
+ 313 00fa 5D00     		lsls	r5, r3, #1
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((GPIO_Init->Pull) << (position * 2));
+ 314              		.loc 1 210 37 view .LVU129
+ 315 00fc 0322     		movs	r2, #3
+ 316 00fe AA40     		lsls	r2, r2, r5
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((GPIO_Init->Pull) << (position * 2));
+ 317              		.loc 1 210 14 view .LVU130
+ 318 0100 24EA0204 		bic	r4, r4, r2
+ 319              	.LVL36:
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         GPIOx->PUPDR = temp;
+ 320              		.loc 1 211 9 is_stmt 1 view .LVU131
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         GPIOx->PUPDR = temp;
+ARM GAS  /tmp/ccJPacwp.s 			page 12
+
+
+ 321              		.loc 1 211 28 is_stmt 0 view .LVU132
+ 322 0104 8A68     		ldr	r2, [r1, #8]
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         GPIOx->PUPDR = temp;
+ 323              		.loc 1 211 36 view .LVU133
+ 324 0106 AA40     		lsls	r2, r2, r5
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         GPIOx->PUPDR = temp;
+ 325              		.loc 1 211 14 view .LVU134
+ 326 0108 2243     		orrs	r2, r2, r4
+ 327              	.LVL37:
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       }
+ 328              		.loc 1 212 9 is_stmt 1 view .LVU135
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       }
+ 329              		.loc 1 212 22 is_stmt 0 view .LVU136
+ 330 010a C260     		str	r2, [r0, #12]
+ 331              	.LVL38:
+ 332              	.L5:
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 333              		.loc 1 216 7 is_stmt 1 view .LVU137
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 334              		.loc 1 216 21 is_stmt 0 view .LVU138
+ 335 010c 4A68     		ldr	r2, [r1, #4]
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 336              		.loc 1 216 28 view .LVU139
+ 337 010e 02F00302 		and	r2, r2, #3
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 338              		.loc 1 216 10 view .LVU140
+ 339 0112 022A     		cmp	r2, #2
+ 340 0114 8FD0     		beq	.L29
+ 341              	.L6:
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+ 342              		.loc 1 229 7 is_stmt 1 view .LVU141
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+ 343              		.loc 1 229 12 is_stmt 0 view .LVU142
+ 344 0116 0468     		ldr	r4, [r0]
+ 345              	.LVL39:
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ 346              		.loc 1 230 7 is_stmt 1 view .LVU143
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ 347              		.loc 1 230 48 is_stmt 0 view .LVU144
+ 348 0118 4FEA430E 		lsl	lr, r3, #1
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ 349              		.loc 1 230 35 view .LVU145
+ 350 011c 0322     		movs	r2, #3
+ 351 011e 02FA0EF2 		lsl	r2, r2, lr
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ 352              		.loc 1 230 12 view .LVU146
+ 353 0122 24EA0204 		bic	r4, r4, r2
+ 354              	.LVL40:
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ 355              		.loc 1 231 7 is_stmt 1 view .LVU147
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ 356              		.loc 1 231 26 is_stmt 0 view .LVU148
+ 357 0126 4A68     		ldr	r2, [r1, #4]
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ 358              		.loc 1 231 33 view .LVU149
+ 359 0128 02F00302 		and	r2, r2, #3
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ARM GAS  /tmp/ccJPacwp.s 			page 13
+
+
+ 360              		.loc 1 231 46 view .LVU150
+ 361 012c 02FA0EF2 		lsl	r2, r2, lr
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       GPIOx->MODER = temp;
+ 362              		.loc 1 231 12 view .LVU151
+ 363 0130 2243     		orrs	r2, r2, r4
+ 364              	.LVL41:
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 365              		.loc 1 232 7 is_stmt 1 view .LVU152
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 366              		.loc 1 232 20 is_stmt 0 view .LVU153
+ 367 0132 0260     		str	r2, [r0]
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 368              		.loc 1 236 7 is_stmt 1 view .LVU154
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 369              		.loc 1 236 21 is_stmt 0 view .LVU155
+ 370 0134 4A68     		ldr	r2, [r1, #4]
+ 371              	.LVL42:
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 372              		.loc 1 236 10 view .LVU156
+ 373 0136 12F4403F 		tst	r2, #196608
+ 374 013a C6D0     		beq	.L3
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 375              		.loc 1 239 9 is_stmt 1 view .LVU157
+ 376              	.LBB2:
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 377              		.loc 1 239 9 view .LVU158
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 378              		.loc 1 239 9 view .LVU159
+ 379 013c 2C4A     		ldr	r2, .L31+8
+ 380 013e 546C     		ldr	r4, [r2, #68]
+ 381 0140 44F48044 		orr	r4, r4, #16384
+ 382 0144 5464     		str	r4, [r2, #68]
+ 383              	.LVL43:
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 384              		.loc 1 239 9 view .LVU160
+ 385 0146 526C     		ldr	r2, [r2, #68]
+ 386 0148 02F48042 		and	r2, r2, #16384
+ 387 014c 0192     		str	r2, [sp, #4]
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 388              		.loc 1 239 9 view .LVU161
+ 389 014e 019A     		ldr	r2, [sp, #4]
+ 390              	.LBE2:
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 391              		.loc 1 239 9 view .LVU162
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+ 392              		.loc 1 241 9 view .LVU163
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+ 393              		.loc 1 241 40 is_stmt 0 view .LVU164
+ 394 0150 9C08     		lsrs	r4, r3, #2
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+ 395              		.loc 1 241 14 view .LVU165
+ 396 0152 A51C     		adds	r5, r4, #2
+ 397 0154 244A     		ldr	r2, .L31
+ 398 0156 52F82550 		ldr	r5, [r2, r5, lsl #2]
+ 399              	.LVL44:
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+ 400              		.loc 1 242 9 is_stmt 1 view .LVU166
+ARM GAS  /tmp/ccJPacwp.s 			page 14
+
+
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+ 401              		.loc 1 242 54 is_stmt 0 view .LVU167
+ 402 015a 03F00302 		and	r2, r3, #3
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+ 403              		.loc 1 242 42 view .LVU168
+ 404 015e 4FEA820E 		lsl	lr, r2, #2
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+ 405              		.loc 1 242 36 view .LVU169
+ 406 0162 0F22     		movs	r2, #15
+ 407 0164 02FA0EF2 		lsl	r2, r2, lr
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+ 408              		.loc 1 242 14 view .LVU170
+ 409 0168 25EA0205 		bic	r5, r5, r2
+ 410              	.LVL45:
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 411              		.loc 1 243 9 is_stmt 1 view .LVU171
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 412              		.loc 1 243 18 is_stmt 0 view .LVU172
+ 413 016c 214A     		ldr	r2, .L31+12
+ 414 016e 9042     		cmp	r0, r2
+ 415 0170 3FF475AF 		beq	.L13
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 416              		.loc 1 243 29 discriminator 1 view .LVU173
+ 417 0174 02F58062 		add	r2, r2, #1024
+ 418 0178 9042     		cmp	r0, r2
+ 419 017a 22D0     		beq	.L14
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 420              		.loc 1 243 29 discriminator 3 view .LVU174
+ 421 017c 02F58062 		add	r2, r2, #1024
+ 422 0180 9042     		cmp	r0, r2
+ 423 0182 20D0     		beq	.L15
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 424              		.loc 1 243 29 discriminator 5 view .LVU175
+ 425 0184 02F58062 		add	r2, r2, #1024
+ 426 0188 9042     		cmp	r0, r2
+ 427 018a 1ED0     		beq	.L16
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 428              		.loc 1 243 29 discriminator 7 view .LVU176
+ 429 018c 02F58062 		add	r2, r2, #1024
+ 430 0190 9042     		cmp	r0, r2
+ 431 0192 1CD0     		beq	.L17
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 432              		.loc 1 243 29 discriminator 9 view .LVU177
+ 433 0194 02F58062 		add	r2, r2, #1024
+ 434 0198 9042     		cmp	r0, r2
+ 435 019a 1AD0     		beq	.L18
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 436              		.loc 1 243 29 discriminator 11 view .LVU178
+ 437 019c 02F58062 		add	r2, r2, #1024
+ 438 01a0 9042     		cmp	r0, r2
+ 439 01a2 18D0     		beq	.L19
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 440              		.loc 1 243 29 discriminator 13 view .LVU179
+ 441 01a4 02F58062 		add	r2, r2, #1024
+ 442 01a8 9042     		cmp	r0, r2
+ 443 01aa 16D0     		beq	.L20
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ARM GAS  /tmp/ccJPacwp.s 			page 15
+
+
+ 444              		.loc 1 243 29 discriminator 15 view .LVU180
+ 445 01ac 02F58062 		add	r2, r2, #1024
+ 446 01b0 9042     		cmp	r0, r2
+ 447 01b2 14D0     		beq	.L21
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 448              		.loc 1 243 29 discriminator 17 view .LVU181
+ 449 01b4 02F58062 		add	r2, r2, #1024
+ 450 01b8 9042     		cmp	r0, r2
+ 451 01ba 3FF44EAF 		beq	.L30
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 452              		.loc 1 243 29 view .LVU182
+ 453 01be 0A22     		movs	r2, #10
+ 454 01c0 4EE7     		b	.L7
+ 455              	.L14:
+ 456 01c2 0122     		movs	r2, #1
+ 457              	.LVL46:
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 458              		.loc 1 243 29 view .LVU183
+ 459 01c4 4CE7     		b	.L7
+ 460              	.LVL47:
+ 461              	.L15:
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 462              		.loc 1 243 29 view .LVU184
+ 463 01c6 0222     		movs	r2, #2
+ 464 01c8 4AE7     		b	.L7
+ 465              	.L16:
+ 466 01ca 0322     		movs	r2, #3
+ 467 01cc 48E7     		b	.L7
+ 468              	.L17:
+ 469 01ce 0422     		movs	r2, #4
+ 470 01d0 46E7     		b	.L7
+ 471              	.L18:
+ 472 01d2 0522     		movs	r2, #5
+ 473 01d4 44E7     		b	.L7
+ 474              	.L19:
+ 475 01d6 0622     		movs	r2, #6
+ 476 01d8 42E7     		b	.L7
+ 477              	.L20:
+ 478 01da 0722     		movs	r2, #7
+ 479 01dc 40E7     		b	.L7
+ 480              	.L21:
+ 481 01de 0822     		movs	r2, #8
+ 482 01e0 3EE7     		b	.L7
+ 483              	.LVL48:
+ 484              	.L27:
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       }
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     }
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** }
+ 485              		.loc 1 282 1 view .LVU185
+ 486 01e2 02B0     		add	sp, sp, #8
+ 487              	.LCFI2:
+ 488              		.cfi_def_cfa_offset 16
+ 489              		@ sp needed
+ 490 01e4 70BD     		pop	{r4, r5, r6, pc}
+ 491              	.LVL49:
+ 492              	.L26:
+ARM GAS  /tmp/ccJPacwp.s 			page 16
+
+
+ 493              	.LCFI3:
+ 494              		.cfi_def_cfa_offset 0
+ 495              		.cfi_restore 4
+ 496              		.cfi_restore 5
+ 497              		.cfi_restore 6
+ 498              		.cfi_restore 14
+ 499              		.loc 1 282 1 view .LVU186
+ 500 01e6 7047     		bx	lr
+ 501              	.L32:
+ 502              		.align	2
+ 503              	.L31:
+ 504 01e8 00380140 		.word	1073821696
+ 505 01ec 003C0140 		.word	1073822720
+ 506 01f0 00380240 		.word	1073887232
+ 507 01f4 00000240 		.word	1073872896
+ 508              		.cfi_endproc
+ 509              	.LFE141:
+ 511              		.section	.text.HAL_GPIO_DeInit,"ax",%progbits
+ 512              		.align	1
+ 513              		.global	HAL_GPIO_DeInit
+ 514              		.syntax unified
+ 515              		.thumb
+ 516              		.thumb_func
+ 517              		.fpu fpv5-d16
+ 519              	HAL_GPIO_DeInit:
+ 520              	.LVL50:
+ 521              	.LFB142:
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /**
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIO_Pin specifies the port bit to be written.
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @retval None
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** {
+ 522              		.loc 1 292 1 is_stmt 1 view -0
+ 523              		.cfi_startproc
+ 524              		@ args = 0, pretend = 0, frame = 0
+ 525              		@ frame_needed = 0, uses_anonymous_args = 0
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   uint32_t position;
+ 526              		.loc 1 293 3 view .LVU188
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   uint32_t ioposition = 0x00;
+ 527              		.loc 1 294 3 view .LVU189
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   uint32_t iocurrent = 0x00;
+ 528              		.loc 1 295 3 view .LVU190
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   uint32_t tmp = 0x00;
+ 529              		.loc 1 296 3 view .LVU191
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Check the parameters */
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ 530              		.loc 1 299 3 view .LVU192
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Configure the port pins */
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   for (position = 0; position < GPIO_NUMBER; position++)
+ 531              		.loc 1 302 3 view .LVU193
+ARM GAS  /tmp/ccJPacwp.s 			page 17
+
+
+ 532              		.loc 1 302 17 is_stmt 0 view .LVU194
+ 533 0000 0023     		movs	r3, #0
+ 534              	.LVL51:
+ 535              		.loc 1 302 22 is_stmt 1 view .LVU195
+ 536              		.loc 1 302 3 is_stmt 0 view .LVU196
+ 537 0002 0F2B     		cmp	r3, #15
+ 538 0004 00F29B80 		bhi	.L52
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   uint32_t position;
+ 539              		.loc 1 292 1 view .LVU197
+ 540 0008 F0B5     		push	{r4, r5, r6, r7, lr}
+ 541              	.LCFI4:
+ 542              		.cfi_def_cfa_offset 20
+ 543              		.cfi_offset 4, -20
+ 544              		.cfi_offset 5, -16
+ 545              		.cfi_offset 6, -12
+ 546              		.cfi_offset 7, -8
+ 547              		.cfi_offset 14, -4
+ 548 000a 2DE0     		b	.L38
+ 549              	.LVL52:
+ 550              	.L55:
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     /* Get the IO position */
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     ioposition = ((uint32_t)0x01) << position;
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     /* Get the current IO position */
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     iocurrent = (GPIO_Pin) & ioposition;
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     if (iocurrent == ioposition)
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     {
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /*------------------------- EXTI Mode Configuration --------------------*/
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       tmp = SYSCFG->EXTICR[position >> 2];
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
+ 551              		.loc 1 314 30 view .LVU198
+ 552 000c 0925     		movs	r5, #9
+ 553 000e 00E0     		b	.L36
+ 554              	.L39:
+ 555              		.loc 1 314 19 view .LVU199
+ 556 0010 0025     		movs	r5, #0
+ 557              	.L36:
+ 558              		.loc 1 314 53 discriminator 40 view .LVU200
+ 559 0012 05FA0CFC 		lsl	ip, r5, ip
+ 560              		.loc 1 314 10 discriminator 40 view .LVU201
+ 561 0016 A445     		cmp	ip, r4
+ 562 0018 75D0     		beq	.L53
+ 563              	.LVL53:
+ 564              	.L37:
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Clear EXTI line configuration */
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->IMR &= ~((uint32_t)iocurrent);
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->EMR &= ~((uint32_t)iocurrent);
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Clear Rising Falling edge configuration */
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->FTSR &= ~((uint32_t)iocurrent);
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->RTSR &= ~((uint32_t)iocurrent);
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         /* Configure the External Interrupt or event for the current IO */
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+ARM GAS  /tmp/ccJPacwp.s 			page 18
+
+
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] &= ~tmp;
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       }
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /*------------------------- GPIO Mode Configuration --------------------*/
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /* Configure IO Direction in Input Floating Mode */
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
+ 565              		.loc 1 330 7 is_stmt 1 view .LVU202
+ 566              		.loc 1 330 20 is_stmt 0 view .LVU203
+ 567 001a 0468     		ldr	r4, [r0]
+ 568              		.loc 1 330 56 view .LVU204
+ 569 001c 5D00     		lsls	r5, r3, #1
+ 570              		.loc 1 330 43 view .LVU205
+ 571 001e 4FF0030C 		mov	ip, #3
+ 572 0022 0CFA05FC 		lsl	ip, ip, r5
+ 573              		.loc 1 330 20 view .LVU206
+ 574 0026 24EA0C04 		bic	r4, r4, ip
+ 575 002a 0460     		str	r4, [r0]
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /* Configure the default Alternate Function in current IO */
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) 
+ 576              		.loc 1 333 7 is_stmt 1 view .LVU207
+ 577              		.loc 1 333 33 is_stmt 0 view .LVU208
+ 578 002c 4FEAD30E 		lsr	lr, r3, #3
+ 579 0030 0EF1080E 		add	lr, lr, #8
+ 580 0034 50F82E40 		ldr	r4, [r0, lr, lsl #2]
+ 581              		.loc 1 333 56 view .LVU209
+ 582 0038 03F00705 		and	r5, r3, #7
+ 583              		.loc 1 333 94 view .LVU210
+ 584 003c AE00     		lsls	r6, r5, #2
+ 585              		.loc 1 333 52 view .LVU211
+ 586 003e 0F25     		movs	r5, #15
+ 587 0040 B540     		lsls	r5, r5, r6
+ 588              		.loc 1 333 33 view .LVU212
+ 589 0042 24EA0504 		bic	r4, r4, r5
+ 590 0046 40F82E40 		str	r4, [r0, lr, lsl #2]
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ 591              		.loc 1 336 7 is_stmt 1 view .LVU213
+ 592              		.loc 1 336 20 is_stmt 0 view .LVU214
+ 593 004a C468     		ldr	r4, [r0, #12]
+ 594 004c 24EA0C04 		bic	r4, r4, ip
+ 595 0050 C460     		str	r4, [r0, #12]
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /* Configure the default value IO Output Type */
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 596              		.loc 1 339 7 is_stmt 1 view .LVU215
+ 597              		.loc 1 339 22 is_stmt 0 view .LVU216
+ 598 0052 4468     		ldr	r4, [r0, #4]
+ 599 0054 24EA0202 		bic	r2, r4, r2
+ 600              	.LVL54:
+ 601              		.loc 1 339 22 view .LVU217
+ 602 0058 4260     		str	r2, [r0, #4]
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       /* Configure the default value for IO Speed */
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+ 603              		.loc 1 342 7 is_stmt 1 view .LVU218
+ 604              		.loc 1 342 22 is_stmt 0 view .LVU219
+ARM GAS  /tmp/ccJPacwp.s 			page 19
+
+
+ 605 005a 8268     		ldr	r2, [r0, #8]
+ 606 005c 22EA0C02 		bic	r2, r2, ip
+ 607 0060 8260     		str	r2, [r0, #8]
+ 608              	.L35:
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 609              		.loc 1 302 46 is_stmt 1 discriminator 2 view .LVU220
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 610              		.loc 1 302 54 is_stmt 0 discriminator 2 view .LVU221
+ 611 0062 0133     		adds	r3, r3, #1
+ 612              	.LVL55:
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 613              		.loc 1 302 22 is_stmt 1 discriminator 2 view .LVU222
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 614              		.loc 1 302 3 is_stmt 0 discriminator 2 view .LVU223
+ 615 0064 0F2B     		cmp	r3, #15
+ 616 0066 69D8     		bhi	.L54
+ 617              	.LVL56:
+ 618              	.L38:
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     /* Get the current IO position */
+ 619              		.loc 1 305 5 is_stmt 1 view .LVU224
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     /* Get the current IO position */
+ 620              		.loc 1 305 16 is_stmt 0 view .LVU225
+ 621 0068 0122     		movs	r2, #1
+ 622 006a 9A40     		lsls	r2, r2, r3
+ 623              	.LVL57:
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 624              		.loc 1 307 5 is_stmt 1 view .LVU226
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 625              		.loc 1 307 15 is_stmt 0 view .LVU227
+ 626 006c 02EA0106 		and	r6, r2, r1
+ 627              	.LVL58:
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     {
+ 628              		.loc 1 309 5 is_stmt 1 view .LVU228
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     {
+ 629              		.loc 1 309 8 is_stmt 0 view .LVU229
+ 630 0070 32EA0104 		bics	r4, r2, r1
+ 631 0074 F5D1     		bne	.L35
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ 632              		.loc 1 312 7 is_stmt 1 view .LVU230
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ 633              		.loc 1 312 37 is_stmt 0 view .LVU231
+ 634 0076 4FEA930E 		lsr	lr, r3, #2
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ 635              		.loc 1 312 11 view .LVU232
+ 636 007a 0EF10205 		add	r5, lr, #2
+ 637 007e 304C     		ldr	r4, .L56
+ 638 0080 54F82540 		ldr	r4, [r4, r5, lsl #2]
+ 639              	.LVL59:
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
+ 640              		.loc 1 313 7 is_stmt 1 view .LVU233
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
+ 641              		.loc 1 313 50 is_stmt 0 view .LVU234
+ 642 0084 03F0030C 		and	ip, r3, #3
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
+ 643              		.loc 1 313 38 view .LVU235
+ 644 0088 4FEA8C0C 		lsl	ip, ip, #2
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
+ARM GAS  /tmp/ccJPacwp.s 			page 20
+
+
+ 645              		.loc 1 313 32 view .LVU236
+ 646 008c 0F25     		movs	r5, #15
+ 647 008e 05FA0CF7 		lsl	r7, r5, ip
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
+ 648              		.loc 1 313 11 view .LVU237
+ 649 0092 3C40     		ands	r4, r4, r7
+ 650              	.LVL60:
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 651              		.loc 1 314 7 is_stmt 1 view .LVU238
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 652              		.loc 1 314 19 is_stmt 0 view .LVU239
+ 653 0094 2B4D     		ldr	r5, .L56+4
+ 654 0096 A842     		cmp	r0, r5
+ 655 0098 BAD0     		beq	.L39
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 656              		.loc 1 314 30 discriminator 1 view .LVU240
+ 657 009a 05F58065 		add	r5, r5, #1024
+ 658 009e A842     		cmp	r0, r5
+ 659 00a0 21D0     		beq	.L40
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 660              		.loc 1 314 30 discriminator 3 view .LVU241
+ 661 00a2 05F58065 		add	r5, r5, #1024
+ 662 00a6 A842     		cmp	r0, r5
+ 663 00a8 1FD0     		beq	.L41
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 664              		.loc 1 314 30 discriminator 5 view .LVU242
+ 665 00aa 05F58065 		add	r5, r5, #1024
+ 666 00ae A842     		cmp	r0, r5
+ 667 00b0 1DD0     		beq	.L42
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 668              		.loc 1 314 30 discriminator 7 view .LVU243
+ 669 00b2 05F58065 		add	r5, r5, #1024
+ 670 00b6 A842     		cmp	r0, r5
+ 671 00b8 1BD0     		beq	.L43
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 672              		.loc 1 314 30 discriminator 9 view .LVU244
+ 673 00ba 05F58065 		add	r5, r5, #1024
+ 674 00be A842     		cmp	r0, r5
+ 675 00c0 19D0     		beq	.L44
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 676              		.loc 1 314 30 discriminator 11 view .LVU245
+ 677 00c2 05F58065 		add	r5, r5, #1024
+ 678 00c6 A842     		cmp	r0, r5
+ 679 00c8 17D0     		beq	.L45
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 680              		.loc 1 314 30 discriminator 13 view .LVU246
+ 681 00ca 05F58065 		add	r5, r5, #1024
+ 682 00ce A842     		cmp	r0, r5
+ 683 00d0 15D0     		beq	.L46
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 684              		.loc 1 314 30 discriminator 15 view .LVU247
+ 685 00d2 05F58065 		add	r5, r5, #1024
+ 686 00d6 A842     		cmp	r0, r5
+ 687 00d8 13D0     		beq	.L47
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 688              		.loc 1 314 30 discriminator 17 view .LVU248
+ 689 00da 05F58065 		add	r5, r5, #1024
+ARM GAS  /tmp/ccJPacwp.s 			page 21
+
+
+ 690 00de A842     		cmp	r0, r5
+ 691 00e0 94D0     		beq	.L55
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       {
+ 692              		.loc 1 314 30 view .LVU249
+ 693 00e2 0A25     		movs	r5, #10
+ 694 00e4 95E7     		b	.L36
+ 695              	.L40:
+ 696 00e6 0125     		movs	r5, #1
+ 697 00e8 93E7     		b	.L36
+ 698              	.L41:
+ 699 00ea 0225     		movs	r5, #2
+ 700 00ec 91E7     		b	.L36
+ 701              	.L42:
+ 702 00ee 0325     		movs	r5, #3
+ 703 00f0 8FE7     		b	.L36
+ 704              	.L43:
+ 705 00f2 0425     		movs	r5, #4
+ 706 00f4 8DE7     		b	.L36
+ 707              	.L44:
+ 708 00f6 0525     		movs	r5, #5
+ 709 00f8 8BE7     		b	.L36
+ 710              	.L45:
+ 711 00fa 0625     		movs	r5, #6
+ 712 00fc 89E7     		b	.L36
+ 713              	.L46:
+ 714 00fe 0725     		movs	r5, #7
+ 715 0100 87E7     		b	.L36
+ 716              	.L47:
+ 717 0102 0825     		movs	r5, #8
+ 718 0104 85E7     		b	.L36
+ 719              	.L53:
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->EMR &= ~((uint32_t)iocurrent);
+ 720              		.loc 1 317 9 is_stmt 1 view .LVU250
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->EMR &= ~((uint32_t)iocurrent);
+ 721              		.loc 1 317 19 is_stmt 0 view .LVU251
+ 722 0106 104C     		ldr	r4, .L56+8
+ 723              	.LVL61:
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->EMR &= ~((uint32_t)iocurrent);
+ 724              		.loc 1 317 19 view .LVU252
+ 725 0108 2568     		ldr	r5, [r4]
+ 726 010a 25EA0605 		bic	r5, r5, r6
+ 727 010e 2560     		str	r5, [r4]
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 728              		.loc 1 318 9 is_stmt 1 view .LVU253
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 729              		.loc 1 318 19 is_stmt 0 view .LVU254
+ 730 0110 6568     		ldr	r5, [r4, #4]
+ 731 0112 25EA0605 		bic	r5, r5, r6
+ 732 0116 6560     		str	r5, [r4, #4]
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->RTSR &= ~((uint32_t)iocurrent);
+ 733              		.loc 1 321 9 is_stmt 1 view .LVU255
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         EXTI->RTSR &= ~((uint32_t)iocurrent);
+ 734              		.loc 1 321 20 is_stmt 0 view .LVU256
+ 735 0118 E568     		ldr	r5, [r4, #12]
+ 736 011a 25EA0605 		bic	r5, r5, r6
+ 737 011e E560     		str	r5, [r4, #12]
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ARM GAS  /tmp/ccJPacwp.s 			page 22
+
+
+ 738              		.loc 1 322 9 is_stmt 1 view .LVU257
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 739              		.loc 1 322 20 is_stmt 0 view .LVU258
+ 740 0120 A568     		ldr	r5, [r4, #8]
+ 741 0122 25EA0606 		bic	r6, r5, r6
+ 742              	.LVL62:
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 743              		.loc 1 322 20 view .LVU259
+ 744 0126 A660     		str	r6, [r4, #8]
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****         SYSCFG->EXTICR[position >> 2] &= ~tmp;
+ 745              		.loc 1 325 9 is_stmt 1 view .LVU260
+ 746              	.LVL63:
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       }
+ 747              		.loc 1 326 9 view .LVU261
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****       }
+ 748              		.loc 1 326 39 is_stmt 0 view .LVU262
+ 749 0128 054E     		ldr	r6, .L56
+ 750 012a 0EF10204 		add	r4, lr, #2
+ 751 012e 56F82450 		ldr	r5, [r6, r4, lsl #2]
+ 752 0132 25EA0705 		bic	r5, r5, r7
+ 753 0136 46F82450 		str	r5, [r6, r4, lsl #2]
+ 754 013a 6EE7     		b	.L37
+ 755              	.LVL64:
+ 756              	.L54:
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     }
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** }
+ 757              		.loc 1 345 1 view .LVU263
+ 758 013c F0BD     		pop	{r4, r5, r6, r7, pc}
+ 759              	.LVL65:
+ 760              	.L52:
+ 761              	.LCFI5:
+ 762              		.cfi_def_cfa_offset 0
+ 763              		.cfi_restore 4
+ 764              		.cfi_restore 5
+ 765              		.cfi_restore 6
+ 766              		.cfi_restore 7
+ 767              		.cfi_restore 14
+ 768              		.loc 1 345 1 view .LVU264
+ 769 013e 7047     		bx	lr
+ 770              	.L57:
+ 771              		.align	2
+ 772              	.L56:
+ 773 0140 00380140 		.word	1073821696
+ 774 0144 00000240 		.word	1073872896
+ 775 0148 003C0140 		.word	1073822720
+ 776              		.cfi_endproc
+ 777              	.LFE142:
+ 779              		.section	.text.HAL_GPIO_ReadPin,"ax",%progbits
+ 780              		.align	1
+ 781              		.global	HAL_GPIO_ReadPin
+ 782              		.syntax unified
+ 783              		.thumb
+ 784              		.thumb_func
+ 785              		.fpu fpv5-d16
+ 787              	HAL_GPIO_ReadPin:
+ 788              	.LVL66:
+ARM GAS  /tmp/ccJPacwp.s 			page 23
+
+
+ 789              	.LFB143:
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /**
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @}
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****  *  @brief   GPIO Read and Write
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****  *
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** @verbatim
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****  ===============================================================================
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****                        ##### IO operation functions #####
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****  ===============================================================================
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** @endverbatim
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @{
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /**
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @brief  Reads the specified input port pin.
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIO_Pin specifies the port bit to read.
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @retval The input port pin value.
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** {
+ 790              		.loc 1 371 1 is_stmt 1 view -0
+ 791              		.cfi_startproc
+ 792              		@ args = 0, pretend = 0, frame = 0
+ 793              		@ frame_needed = 0, uses_anonymous_args = 0
+ 794              		@ link register save eliminated.
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   GPIO_PinState bitstatus;
+ 795              		.loc 1 372 3 view .LVU266
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Check the parameters */
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
+ 796              		.loc 1 375 3 view .LVU267
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+ 797              		.loc 1 377 3 view .LVU268
+ 798              		.loc 1 377 13 is_stmt 0 view .LVU269
+ 799 0000 0369     		ldr	r3, [r0, #16]
+ 800              		.loc 1 377 6 view .LVU270
+ 801 0002 1942     		tst	r1, r3
+ 802 0004 01D0     		beq	.L60
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     bitstatus = GPIO_PIN_SET;
+ 803              		.loc 1 379 15 view .LVU271
+ 804 0006 0120     		movs	r0, #1
+ 805              	.LVL67:
+ 806              		.loc 1 379 15 view .LVU272
+ 807 0008 7047     		bx	lr
+ 808              	.LVL68:
+ 809              	.L60:
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   else
+ARM GAS  /tmp/ccJPacwp.s 			page 24
+
+
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     bitstatus = GPIO_PIN_RESET;
+ 810              		.loc 1 383 15 view .LVU273
+ 811 000a 0020     		movs	r0, #0
+ 812              	.LVL69:
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   return bitstatus;
+ 813              		.loc 1 385 3 is_stmt 1 view .LVU274
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** }
+ 814              		.loc 1 386 1 is_stmt 0 view .LVU275
+ 815 000c 7047     		bx	lr
+ 816              		.cfi_endproc
+ 817              	.LFE143:
+ 819              		.section	.text.HAL_GPIO_WritePin,"ax",%progbits
+ 820              		.align	1
+ 821              		.global	HAL_GPIO_WritePin
+ 822              		.syntax unified
+ 823              		.thumb
+ 824              		.thumb_func
+ 825              		.fpu fpv5-d16
+ 827              	HAL_GPIO_WritePin:
+ 828              	.LVL70:
+ 829              	.LFB144:
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /**
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @brief  Sets or clears the selected data port bit.
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *         accesses. In this way, there is no risk of an IRQ occurring between
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *         the read and the modify access.
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIO_Pin specifies the port bit to be written.
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  PinState specifies the value to be written to the selected bit.
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *          This parameter can be one of the GPIO_PinState enum values:
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *            @arg GPIO_PIN_RESET: to clear the port pin
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *            @arg GPIO_PIN_SET: to set the port pin
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @retval None
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** {
+ 830              		.loc 1 405 1 is_stmt 1 view -0
+ 831              		.cfi_startproc
+ 832              		@ args = 0, pretend = 0, frame = 0
+ 833              		@ frame_needed = 0, uses_anonymous_args = 0
+ 834              		@ link register save eliminated.
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Check the parameters */
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
+ 835              		.loc 1 407 3 view .LVU277
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN_ACTION(PinState));
+ 836              		.loc 1 408 3 view .LVU278
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   if (PinState != GPIO_PIN_RESET)
+ 837              		.loc 1 410 3 view .LVU279
+ 838              		.loc 1 410 6 is_stmt 0 view .LVU280
+ 839 0000 0AB1     		cbz	r2, .L62
+ARM GAS  /tmp/ccJPacwp.s 			page 25
+
+
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     GPIOx->BSRR = GPIO_Pin;
+ 840              		.loc 1 412 5 is_stmt 1 view .LVU281
+ 841              		.loc 1 412 17 is_stmt 0 view .LVU282
+ 842 0002 8161     		str	r1, [r0, #24]
+ 843 0004 7047     		bx	lr
+ 844              	.L62:
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   else
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
+ 845              		.loc 1 416 5 is_stmt 1 view .LVU283
+ 846              		.loc 1 416 38 is_stmt 0 view .LVU284
+ 847 0006 0904     		lsls	r1, r1, #16
+ 848              	.LVL71:
+ 849              		.loc 1 416 17 view .LVU285
+ 850 0008 8161     		str	r1, [r0, #24]
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** }
+ 851              		.loc 1 418 1 view .LVU286
+ 852 000a 7047     		bx	lr
+ 853              		.cfi_endproc
+ 854              	.LFE144:
+ 856              		.section	.text.HAL_GPIO_TogglePin,"ax",%progbits
+ 857              		.align	1
+ 858              		.global	HAL_GPIO_TogglePin
+ 859              		.syntax unified
+ 860              		.thumb
+ 861              		.thumb_func
+ 862              		.fpu fpv5-d16
+ 864              	HAL_GPIO_TogglePin:
+ 865              	.LVL72:
+ 866              	.LFB145:
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /**
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @brief  Toggles the specified GPIO pins.
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIOx Where x can be (A..I) to select the GPIO peripheral.
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIO_Pin Specifies the pins to be toggled.
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @retval None
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** {
+ 867              		.loc 1 428 1 is_stmt 1 view -0
+ 868              		.cfi_startproc
+ 869              		@ args = 0, pretend = 0, frame = 0
+ 870              		@ frame_needed = 0, uses_anonymous_args = 0
+ 871              		@ link register save eliminated.
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   uint32_t odr;
+ 872              		.loc 1 429 3 view .LVU288
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Check the parameters */
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
+ 873              		.loc 1 432 3 view .LVU289
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* get current Output Data Register value */
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   odr = GPIOx->ODR;
+ARM GAS  /tmp/ccJPacwp.s 			page 26
+
+
+ 874              		.loc 1 435 3 view .LVU290
+ 875              		.loc 1 435 7 is_stmt 0 view .LVU291
+ 876 0000 4369     		ldr	r3, [r0, #20]
+ 877              	.LVL73:
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Set selected pins that were at low level, and reset ones that were high */
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+ 878              		.loc 1 438 3 is_stmt 1 view .LVU292
+ 879              		.loc 1 438 23 is_stmt 0 view .LVU293
+ 880 0002 01EA0302 		and	r2, r1, r3
+ 881              		.loc 1 438 59 view .LVU294
+ 882 0006 21EA0301 		bic	r1, r1, r3
+ 883              	.LVL74:
+ 884              		.loc 1 438 51 view .LVU295
+ 885 000a 41EA0241 		orr	r1, r1, r2, lsl #16
+ 886              		.loc 1 438 15 view .LVU296
+ 887 000e 8161     		str	r1, [r0, #24]
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** }
+ 888              		.loc 1 439 1 view .LVU297
+ 889 0010 7047     		bx	lr
+ 890              		.cfi_endproc
+ 891              	.LFE145:
+ 893              		.section	.text.HAL_GPIO_LockPin,"ax",%progbits
+ 894              		.align	1
+ 895              		.global	HAL_GPIO_LockPin
+ 896              		.syntax unified
+ 897              		.thumb
+ 898              		.thumb_func
+ 899              		.fpu fpv5-d16
+ 901              	HAL_GPIO_LockPin:
+ 902              	.LVL75:
+ 903              	.LFB146:
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /**
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @brief  Locks GPIO Pins configuration registers.
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @note   The configuration of the locked GPIO pins can no longer be modified
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *         until the next reset.
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIO_Pin specifies the port bit to be locked.
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @retval None
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** {
+ 904              		.loc 1 453 1 is_stmt 1 view -0
+ 905              		.cfi_startproc
+ 906              		@ args = 0, pretend = 0, frame = 8
+ 907              		@ frame_needed = 0, uses_anonymous_args = 0
+ 908              		@ link register save eliminated.
+ 909              		.loc 1 453 1 is_stmt 0 view .LVU299
+ 910 0000 82B0     		sub	sp, sp, #8
+ 911              	.LCFI6:
+ 912              		.cfi_def_cfa_offset 8
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   __IO uint32_t tmp = GPIO_LCKR_LCKK;
+ 913              		.loc 1 454 3 is_stmt 1 view .LVU300
+ARM GAS  /tmp/ccJPacwp.s 			page 27
+
+
+ 914              		.loc 1 454 17 is_stmt 0 view .LVU301
+ 915 0002 4FF48033 		mov	r3, #65536
+ 916 0006 0193     		str	r3, [sp, #4]
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Check the parameters */
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
+ 917              		.loc 1 457 3 is_stmt 1 view .LVU302
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Apply lock key write sequence */
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   tmp |= GPIO_Pin;
+ 918              		.loc 1 460 3 view .LVU303
+ 919              		.loc 1 460 7 is_stmt 0 view .LVU304
+ 920 0008 019B     		ldr	r3, [sp, #4]
+ 921 000a 0B43     		orrs	r3, r3, r1
+ 922 000c 0193     		str	r3, [sp, #4]
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   GPIOx->LCKR = tmp;
+ 923              		.loc 1 462 3 is_stmt 1 view .LVU305
+ 924              		.loc 1 462 15 is_stmt 0 view .LVU306
+ 925 000e 019B     		ldr	r3, [sp, #4]
+ 926 0010 C361     		str	r3, [r0, #28]
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   GPIOx->LCKR = GPIO_Pin;
+ 927              		.loc 1 464 3 is_stmt 1 view .LVU307
+ 928              		.loc 1 464 15 is_stmt 0 view .LVU308
+ 929 0012 C161     		str	r1, [r0, #28]
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   GPIOx->LCKR = tmp;
+ 930              		.loc 1 466 3 is_stmt 1 view .LVU309
+ 931              		.loc 1 466 15 is_stmt 0 view .LVU310
+ 932 0014 019B     		ldr	r3, [sp, #4]
+ 933 0016 C361     		str	r3, [r0, #28]
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Read LCKR register. This read is mandatory to complete key lock sequence */
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   tmp = GPIOx->LCKR;
+ 934              		.loc 1 468 3 is_stmt 1 view .LVU311
+ 935              		.loc 1 468 14 is_stmt 0 view .LVU312
+ 936 0018 C369     		ldr	r3, [r0, #28]
+ 937              		.loc 1 468 7 view .LVU313
+ 938 001a 0193     		str	r3, [sp, #4]
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Read again in order to confirm lock is active */
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+ 939              		.loc 1 471 3 is_stmt 1 view .LVU314
+ 940              		.loc 1 471 13 is_stmt 0 view .LVU315
+ 941 001c C369     		ldr	r3, [r0, #28]
+ 942              		.loc 1 471 6 view .LVU316
+ 943 001e 13F4803F 		tst	r3, #65536
+ 944 0022 02D0     		beq	.L67
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     return HAL_OK;
+ 945              		.loc 1 473 12 view .LVU317
+ 946 0024 0020     		movs	r0, #0
+ 947              	.LVL76:
+ 948              	.L66:
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   else
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ARM GAS  /tmp/ccJPacwp.s 			page 28
+
+
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     return HAL_ERROR;
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** }
+ 949              		.loc 1 479 1 view .LVU318
+ 950 0026 02B0     		add	sp, sp, #8
+ 951              	.LCFI7:
+ 952              		.cfi_remember_state
+ 953              		.cfi_def_cfa_offset 0
+ 954              		@ sp needed
+ 955 0028 7047     		bx	lr
+ 956              	.LVL77:
+ 957              	.L67:
+ 958              	.LCFI8:
+ 959              		.cfi_restore_state
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 960              		.loc 1 477 12 view .LVU319
+ 961 002a 0120     		movs	r0, #1
+ 962              	.LVL78:
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 963              		.loc 1 477 12 view .LVU320
+ 964 002c FBE7     		b	.L66
+ 965              		.cfi_endproc
+ 966              	.LFE146:
+ 968              		.section	.text.HAL_GPIO_EXTI_Callback,"ax",%progbits
+ 969              		.align	1
+ 970              		.weak	HAL_GPIO_EXTI_Callback
+ 971              		.syntax unified
+ 972              		.thumb
+ 973              		.thumb_func
+ 974              		.fpu fpv5-d16
+ 976              	HAL_GPIO_EXTI_Callback:
+ 977              	.LVL79:
+ 978              	.LFB148:
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /**
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @brief  This function handles EXTI interrupt request.
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIO_Pin Specifies the pins connected EXTI line
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @retval None
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** {
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* EXTI line interrupt detected */
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** }
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /**
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @brief  EXTI line detection callbacks.
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @param  GPIO_Pin Specifies the pins connected EXTI line
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   * @retval None
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   */
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** {
+ 979              		.loc 1 502 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccJPacwp.s 			page 29
+
+
+ 980              		.cfi_startproc
+ 981              		@ args = 0, pretend = 0, frame = 0
+ 982              		@ frame_needed = 0, uses_anonymous_args = 0
+ 983              		@ link register save eliminated.
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* Prevent unused argument(s) compilation warning */
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   UNUSED(GPIO_Pin);
+ 984              		.loc 1 504 3 view .LVU322
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* NOTE: This function Should not be modified, when the callback is needed,
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****            the HAL_GPIO_EXTI_Callback could be implemented in the user file
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****    */
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** }
+ 985              		.loc 1 509 1 is_stmt 0 view .LVU323
+ 986 0000 7047     		bx	lr
+ 987              		.cfi_endproc
+ 988              	.LFE148:
+ 990              		.section	.text.HAL_GPIO_EXTI_IRQHandler,"ax",%progbits
+ 991              		.align	1
+ 992              		.global	HAL_GPIO_EXTI_IRQHandler
+ 993              		.syntax unified
+ 994              		.thumb
+ 995              		.thumb_func
+ 996              		.fpu fpv5-d16
+ 998              	HAL_GPIO_EXTI_IRQHandler:
+ 999              	.LVL80:
+ 1000              	.LFB147:
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* EXTI line interrupt detected */
+ 1001              		.loc 1 487 1 is_stmt 1 view -0
+ 1002              		.cfi_startproc
+ 1003              		@ args = 0, pretend = 0, frame = 0
+ 1004              		@ frame_needed = 0, uses_anonymous_args = 0
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   /* EXTI line interrupt detected */
+ 1005              		.loc 1 487 1 is_stmt 0 view .LVU325
+ 1006 0000 08B5     		push	{r3, lr}
+ 1007              	.LCFI9:
+ 1008              		.cfi_def_cfa_offset 8
+ 1009              		.cfi_offset 3, -8
+ 1010              		.cfi_offset 14, -4
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 1011              		.loc 1 489 3 is_stmt 1 view .LVU326
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 1012              		.loc 1 489 7 is_stmt 0 view .LVU327
+ 1013 0002 054B     		ldr	r3, .L74
+ 1014 0004 5B69     		ldr	r3, [r3, #20]
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   {
+ 1015              		.loc 1 489 6 view .LVU328
+ 1016 0006 0342     		tst	r3, r0
+ 1017 0008 00D1     		bne	.L73
+ 1018              	.LVL81:
+ 1019              	.L70:
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 1020              		.loc 1 494 1 view .LVU329
+ 1021 000a 08BD     		pop	{r3, pc}
+ 1022              	.LVL82:
+ 1023              	.L73:
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****     HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ 1024              		.loc 1 491 5 is_stmt 1 view .LVU330
+ARM GAS  /tmp/ccJPacwp.s 			page 30
+
+
+ 1025 000c 024B     		ldr	r3, .L74
+ 1026 000e 5861     		str	r0, [r3, #20]
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c ****   }
+ 1027              		.loc 1 492 5 view .LVU331
+ 1028 0010 FFF7FEFF 		bl	HAL_GPIO_EXTI_Callback
+ 1029              	.LVL83:
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** 
+ 1030              		.loc 1 494 1 is_stmt 0 view .LVU332
+ 1031 0014 F9E7     		b	.L70
+ 1032              	.L75:
+ 1033 0016 00BF     		.align	2
+ 1034              	.L74:
+ 1035 0018 003C0140 		.word	1073822720
+ 1036              		.cfi_endproc
+ 1037              	.LFE147:
+ 1039              		.text
+ 1040              	.Letext0:
+ 1041              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 1042              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 1043              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 1044              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 1045              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h"
+ARM GAS  /tmp/ccJPacwp.s 			page 31
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_gpio.c
+     /tmp/ccJPacwp.s:17     .text.HAL_GPIO_Init:0000000000000000 $t
+     /tmp/ccJPacwp.s:25     .text.HAL_GPIO_Init:0000000000000000 HAL_GPIO_Init
+     /tmp/ccJPacwp.s:504    .text.HAL_GPIO_Init:00000000000001e8 $d
+     /tmp/ccJPacwp.s:512    .text.HAL_GPIO_DeInit:0000000000000000 $t
+     /tmp/ccJPacwp.s:519    .text.HAL_GPIO_DeInit:0000000000000000 HAL_GPIO_DeInit
+     /tmp/ccJPacwp.s:773    .text.HAL_GPIO_DeInit:0000000000000140 $d
+     /tmp/ccJPacwp.s:780    .text.HAL_GPIO_ReadPin:0000000000000000 $t
+     /tmp/ccJPacwp.s:787    .text.HAL_GPIO_ReadPin:0000000000000000 HAL_GPIO_ReadPin
+     /tmp/ccJPacwp.s:820    .text.HAL_GPIO_WritePin:0000000000000000 $t
+     /tmp/ccJPacwp.s:827    .text.HAL_GPIO_WritePin:0000000000000000 HAL_GPIO_WritePin
+     /tmp/ccJPacwp.s:857    .text.HAL_GPIO_TogglePin:0000000000000000 $t
+     /tmp/ccJPacwp.s:864    .text.HAL_GPIO_TogglePin:0000000000000000 HAL_GPIO_TogglePin
+     /tmp/ccJPacwp.s:894    .text.HAL_GPIO_LockPin:0000000000000000 $t
+     /tmp/ccJPacwp.s:901    .text.HAL_GPIO_LockPin:0000000000000000 HAL_GPIO_LockPin
+     /tmp/ccJPacwp.s:969    .text.HAL_GPIO_EXTI_Callback:0000000000000000 $t
+     /tmp/ccJPacwp.s:976    .text.HAL_GPIO_EXTI_Callback:0000000000000000 HAL_GPIO_EXTI_Callback
+     /tmp/ccJPacwp.s:991    .text.HAL_GPIO_EXTI_IRQHandler:0000000000000000 $t
+     /tmp/ccJPacwp.s:998    .text.HAL_GPIO_EXTI_IRQHandler:0000000000000000 HAL_GPIO_EXTI_IRQHandler
+     /tmp/ccJPacwp.s:1035   .text.HAL_GPIO_EXTI_IRQHandler:0000000000000018 $d
+
+NO UNDEFINED SYMBOLS
diff --git a/build/stm32f7xx_hal_gpio.o b/build/stm32f7xx_hal_gpio.o
new file mode 100644
index 0000000..5c4402a
Binary files /dev/null and b/build/stm32f7xx_hal_gpio.o differ
diff --git a/build/stm32f7xx_hal_i2c.d b/build/stm32f7xx_hal_i2c.d
new file mode 100644
index 0000000..3751e1e
--- /dev/null
+++ b/build/stm32f7xx_hal_i2c.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_i2c.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_i2c.lst b/build/stm32f7xx_hal_i2c.lst
new file mode 100644
index 0000000..407cf2c
--- /dev/null
+++ b/build/stm32f7xx_hal_i2c.lst
@@ -0,0 +1,28608 @@
+ARM GAS  /tmp/ccVyGVF6.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_i2c.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.I2C_Flush_TXDR,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	I2C_Flush_TXDR:
+  25              	.LVL0:
+  26              	.LFB206:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @file    stm32f7xx_hal_i2c.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief   I2C HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *           + IO operation functions
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *           + Peripheral State and Errors functions
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   ******************************************************************************
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @attention
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * Copyright (c) 2017 STMicroelectronics.
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * All rights reserved.
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * in the root directory of this software component.
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   ******************************************************************************
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   @verbatim
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   ==============================================================================
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                         ##### How to use this driver #####
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   ==============================================================================
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     The I2C HAL driver can be used as follows:
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     (#) Declare a I2C_HandleTypeDef handle structure, for example:
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_HandleTypeDef  hi2c;
+ARM GAS  /tmp/ccVyGVF6.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (##) Enable the I2Cx interface clock
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (##) I2C pins configuration
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (+++) Enable the clock for the I2C GPIOs
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (+++) Configure I2C pins as alternate function open-drain
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (##) NVIC configuration if you need to use interrupt process
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (+++) Configure the I2Cx interrupt priority
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (+++) Enable the NVIC I2C IRQ Channel
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (##) DMA Configuration if you need to use DMA process
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (+++) Declare a DMA_HandleTypeDef handle structure for
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   the transmit or receive stream
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (+++) Enable the DMAx interface clock using
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (+++) Configure the DMA handle parameters
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (+++) Configure the DMA Tx or Rx stream
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   the DMA Tx or Rx stream
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addres
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level H
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceRead
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     *** Polling mode IO operation ***
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     =================================
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit(
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     *** Polling mode IO MEM operation ***
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     =====================================
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_W
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     *** Interrupt mode IO operation ***
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     ===================================
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Trans
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receiv
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmi
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_
+ARM GAS  /tmp/ccVyGVF6.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Ab
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            This action will inform Master to generate a Stop condition to discard the communication
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     *** Interrupt mode or DMA mode IO sequential operation ***
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     ==========================================================
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           when a direction change during transfer
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) A specific option field manage the different steps of a sequential transfer
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfac
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            no sequential mode
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start con
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             and data to transfer without a final stop condition
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a 
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             start condition, address and data to transfer without a final stop cond
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             an then permit a call the same master sequential interface several time
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_D
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart 
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             and with new data to transfer if the direction change or manage only th
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             transfer
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             if no direction change and without a final stop condition in both cases
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart 
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             and with new data to transfer if the direction change or manage only th
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             transfer
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             if no direction change and with a final stop condition in both cases
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a re
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             after several call of the same master sequential interface several time
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             (link with option I2C_FIRST_AND_NEXT_FRAME).
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             Usage can, transfer several bytes one by one using
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               HAL_I2C_Master_Seq_Transmit_IT
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Receive_IT
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Transmit_DMA
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Receive_DMA
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit 
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               Receive sequence permit to call the opposite interface Receive or Tra
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               without stopping the communication and so generate a restart conditio
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart c
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             each call of the same master sequential
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             interface.
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             Usage can, transfer several bytes one by one with a restart with slave 
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             each bytes using
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               HAL_I2C_Master_Seq_Transmit_IT
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Receive_IT
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Transmit_DMA
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               or HAL_I2C_Master_Seq_Receive_DMA
+ARM GAS  /tmp/ccVyGVF6.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                               with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                             generation of STOP condition.
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Different sequential I2C interfaces are listed below:
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is execut
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltC
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed 
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             HAL_I2C_DisableListen_IT()
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code to check the Address Match Code and the transmission direction reques
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (Write/Read).
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is execute
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCa
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed a
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            This action will inform Master to generate a Stop condition to discard the communication
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     *** Interrupt mode IO MEM operation ***
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     =======================================
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address 
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           HAL_I2C_Mem_Write_IT()
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           HAL_I2C_Mem_Read_IT()
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     *** DMA mode IO operation ***
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     ==============================
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           HAL_I2C_Master_Transmit_DMA()
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ARM GAS  /tmp/ccVyGVF6.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           HAL_I2C_Master_Receive_DMA()
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           HAL_I2C_Slave_Transmit_DMA()
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           HAL_I2C_Slave_Receive_DMA()
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Ab
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            This action will inform Master to generate a Stop condition to discard the communication
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     *** DMA mode IO MEM operation ***
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     =================================
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           HAL_I2C_Mem_Write_DMA()
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           HAL_I2C_Mem_Read_DMA()
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      *** I2C HAL driver macros list ***
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      ==================================
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      [..]
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        Below the list of most used macros in I2C HAL driver.
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      *** Callback registration ***
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      =============================================
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      allows the user to configure dynamically the driver callbacks.
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      to register an interrupt callback.
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      Function HAL_I2C_RegisterCallback() allows to register following callbacks:
+ARM GAS  /tmp/ccVyGVF6.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) ListenCpltCallback   : callback for end of listen mode.
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) ErrorCallback        : callback for error detection.
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) AbortCpltCallback    : callback for abort completion process.
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MspInitCallback      : callback for Msp Init.
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MspDeInitCallback    : callback for Msp DeInit.
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      This function takes as parameters the HAL peripheral handle, the Callback ID
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      and a pointer to the user callback function.
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCall
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      weak function.
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      and the Callback ID.
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      This function allows to reset following callbacks:
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) ListenCpltCallback   : callback for end of listen mode.
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) ErrorCallback        : callback for error detection.
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) AbortCpltCallback    : callback for abort completion process.
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MspInitCallback      : callback for Msp Init.
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (+) MspDeInitCallback    : callback for Msp DeInit.
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      all callbacks are set to the corresponding weak functions:
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      Exception done for MspInit and MspDeInit functions that are
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      these callbacks are null (not registered beforehand).
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      Then, the user first registers the MspInit/MspDeInit user callbacks
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      or HAL_I2C_Init() function.
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      not defined, the callback registration feature is not available and all callbacks
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      are set to the corresponding weak functions.
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****      [..]
+ARM GAS  /tmp/ccVyGVF6.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (@) You can refer to the I2C HAL driver header file for more useful macros
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   @endverbatim
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Includes ------------------------------------------------------------------*/
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #include "stm32f7xx_hal.h"
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @addtogroup STM32F7xx_HAL_Driver
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @{
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C I2C
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief I2C HAL module driver
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @{
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #ifdef HAL_I2C_MODULE_ENABLED
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private typedef -----------------------------------------------------------*/
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private define ------------------------------------------------------------*/
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Private_Define I2C Private Define
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @{
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define MAX_NBYTE_SIZE      255U
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define SLAVE_ADDR_SHIFT     7U
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define SLAVE_ADDR_MSK       0x06U
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private define for @ref PreviousState usage */
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                          (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                               (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Mask State define, keep only RX and TX bits */
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Default Value */
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_MASTER))
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_MASTER))
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_SLAVE))
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ARM GAS  /tmp/ccVyGVF6.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_SLAVE))
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_MEM))
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                               (uint32_t)HAL_I2C_MODE_MEM))
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private define to centralize the enable/disable of Interrupts */
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /*!< Bit field can be combinated with
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                          @ref I2C_XFER_LISTEN_IT */
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /*!< Bit field can be combinated with
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                          @ref I2C_XFER_LISTEN_IT */
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /*!< Bit field can be combinated with @ref I2
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                          and @ref I2C_XFER_RX_IT */
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /*!< Bit definition to manage addition of glo
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                          and NACK treatment */
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /*!< Bit definition to manage only STOP evene
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /*!< Bit definition to manage only Reload of 
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private define Sequential Transfer Options default/reset value */
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @}
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private macros ------------------------------------------------------------*/
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @addtogroup I2C_Private_Macro
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @{
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Macro to get remaining data to transfer on DMA side */
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)     __HAL_DMA_GET_COUNTER(__HANDLE__)
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @}
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private variables ---------------------------------------------------------*/
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private function prototypes -----------------------------------------------*/
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Private_Functions I2C Private Functions
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @{
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions to handle DMA transfer */
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions to handle IT transfer */
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+ARM GAS  /tmp/ccVyGVF6.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions to handle IT transfer */
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                 uint16_t MemAddress, uint16_t MemAddSize, uint32_t 
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                 uint32_t Tickstart);
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t T
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                uint32_t Tickstart);
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions for I2C transfer IRQ handler */
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                            uint32_t ITSources);
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                         uint32_t ITSources);
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                           uint32_t ITSources);
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                             uint32_t ITSources);
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          uint32_t ITSources);
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                            uint32_t ITSources);
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions to handle flags during polling transfer */
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                     uint32_t Timeout, uint32_t Tickstart);
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                         uint32_t Tickstart);
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                         uint32_t Tickstart);
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                         uint32_t Tickstart);
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                              uint32_t Tickstart);
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions to centralize the enable/disable of Interrupts */
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private function to treat different error callback */
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private function to flush TXDR register */
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private function to handle  start, restart or stop a transfer */
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                uint32_t Request);
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private function to Convert Specific options */
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ARM GAS  /tmp/ccVyGVF6.s 			page 10
+
+
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @}
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Exported functions --------------------------------------------------------*/
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions I2C Exported Functions
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @{
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *  @brief    Initialization and Configuration functions
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @verbatim
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****  ===============================================================================
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               ##### Initialization and de-initialization functions #####
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****  ===============================================================================
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]  This subsection provides a set of functions allowing to initialize and
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           deinitialize the I2Cx peripheral:
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) User must Implement HAL_I2C_MspInit() function in which he configures
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Call the function HAL_I2C_Init() to configure the selected device with
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           the selected configuration:
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) Clock Timing
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) Own Address 1
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) Addressing mode (Master, Slave)
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) Dual Addressing mode
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) Own Address 2
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) Own Address 2 Mask
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) General call mode
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) Nostretch mode
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           of the selected I2Cx peripheral.
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @endverbatim
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @{
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Initializes the I2C according to the specified parameters
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in the I2C_InitTypeDef and initialize the associated handle.
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c == NULL)
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ARM GAS  /tmp/ccVyGVF6.s 			page 11
+
+
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_RESET)
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Allocate lock resource and initialize it */
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Lock = HAL_UNLOCKED;
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Init the I2C Callback settings */
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback 
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback 
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->MspInitCallback == NULL)
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->MspInitCallback(hi2c);
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     HAL_I2C_MspInit(hi2c);
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_BUSY;
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable the selected I2C peripheral */
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_I2C_DISABLE(hi2c);
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Configure I2Cx: Frequency range */
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable Own Address1 before set the Own Address1 configuration */
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccVyGVF6.s 			page 12
+
+
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else /* I2C_ADDRESSINGMODE_10BIT */
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Configure I2Cx: Addressing Master mode */
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear the I2C ADD10 bit */
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable Own Address2 before set the Own Address2 configuration */
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Configure I2Cx: Dual mode and Own Address2 */
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Configure I2Cx: Generalcall and NoStretch mode */
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Enable the selected I2C peripheral */
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_I2C_ENABLE(hi2c);
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  DeInitialize the I2C peripheral.
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c == NULL)
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+ARM GAS  /tmp/ccVyGVF6.s 			page 13
+
+
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_BUSY;
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable the I2C Peripheral Clock */
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_I2C_DISABLE(hi2c);
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->MspDeInitCallback == NULL)
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->MspDeInitCallback(hi2c);
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_MspDeInit(hi2c);
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_RESET;
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Release Lock */
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief Initialize the I2C MSP.
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_MspInit could be implemented in the user file
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief DeInitialize the I2C MSP.
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+ARM GAS  /tmp/ccVyGVF6.s 			page 14
+
+
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_MspDeInit could be implemented in the user file
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Register a User I2C Callback
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         To be used instead of the weak predefined callback
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @note   The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RES
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  CallbackID ID of the callback to be registered
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         This parameter can be one of the following values:
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pCallback pointer to the Callback function
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Callb
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                            pI2C_CallbackTypeDef pCallback)
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (pCallback == NULL)
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Update the error code */
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (HAL_I2C_STATE_READY == hi2c->State)
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     switch (CallbackID)
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MasterTxCpltCallback = pCallback;
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MasterRxCpltCallback = pCallback;
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->SlaveTxCpltCallback = pCallback;
+ARM GAS  /tmp/ccVyGVF6.s 			page 15
+
+
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->SlaveRxCpltCallback = pCallback;
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ListenCpltCallback = pCallback;
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MemTxCpltCallback = pCallback;
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MemRxCpltCallback = pCallback;
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_ERROR_CB_ID :
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCallback = pCallback;
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_ABORT_CB_ID :
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->AbortCpltCallback = pCallback;
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MSPINIT_CB_ID :
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MspInitCallback = pCallback;
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MSPDEINIT_CB_ID :
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MspDeInitCallback = pCallback;
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       default :
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update the error code */
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Return error status */
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         status =  HAL_ERROR;
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (HAL_I2C_STATE_RESET == hi2c->State)
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     switch (CallbackID)
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MSPINIT_CB_ID :
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MspInitCallback = pCallback;
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MSPDEINIT_CB_ID :
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MspDeInitCallback = pCallback;
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       default :
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update the error code */
+ARM GAS  /tmp/ccVyGVF6.s 			page 16
+
+
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Return error status */
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         status =  HAL_ERROR;
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Update the error code */
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Return error status */
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     status =  HAL_ERROR;
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return status;
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Unregister an I2C Callback
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         I2C callback is redirected to the weak predefined callback
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @note   The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_R
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  CallbackID ID of the callback to be unregistered
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         This parameter can be one of the following values:
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         This parameter can be one of the following values:
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Cal
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (HAL_I2C_STATE_READY == hi2c->State)
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     switch (CallbackID)
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallb
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallb
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ARM GAS  /tmp/ccVyGVF6.s 			page 17
+
+
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallba
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallba
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallbac
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_ERROR_CB_ID :
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback    
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_ABORT_CB_ID :
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MSPINIT_CB_ID :
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit          
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MSPDEINIT_CB_ID :
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit        
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       default :
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update the error code */
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Return error status */
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         status =  HAL_ERROR;
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (HAL_I2C_STATE_RESET == hi2c->State)
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     switch (CallbackID)
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MSPINIT_CB_ID :
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit          
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       case HAL_I2C_MSPDEINIT_CB_ID :
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit        
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ARM GAS  /tmp/ccVyGVF6.s 			page 18
+
+
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       default :
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update the error code */
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Return error status */
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         status =  HAL_ERROR;
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         break;
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Update the error code */
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Return error status */
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     status =  HAL_ERROR;
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return status;
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Register the Slave Address Match I2C Callback
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pCallback pointer to the Address Match Callback function
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pC
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (pCallback == NULL)
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Update the error code */
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (HAL_I2C_STATE_READY == hi2c->State)
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->AddrCallback = pCallback;
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Update the error code */
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Return error status */
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     status =  HAL_ERROR;
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return status;
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ARM GAS  /tmp/ccVyGVF6.s 			page 19
+
+
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  UnRegister the Slave Address Match I2C Callback
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined cal
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (HAL_I2C_STATE_READY == hi2c->State)
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Update the error code */
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Return error status */
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     status =  HAL_ERROR;
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return status;
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @}
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *  @brief   Data transfers functions
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @verbatim
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****  ===============================================================================
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                       ##### IO operation functions #####
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****  ===============================================================================
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     This subsection provides a set of functions allowing to manage the I2C data
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     transfers.
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     (#) There are two modes of transfer:
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (++) Blocking mode : The communication is performed in the polling mode.
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             The status of all data processing is returned by the same function
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             after finishing transfer.
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        (++) No-Blocking mode : The communication is performed using Interrupts
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             or DMA. These functions return the status of the transfer startup.
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             The end of the data processing will be indicated through the
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             using DMA mode.
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     (#) Blocking mode functions are :
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Master_Transmit()
+ARM GAS  /tmp/ccVyGVF6.s 			page 20
+
+
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Master_Receive()
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Transmit()
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Receive()
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Write()
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Read()
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_IsDeviceReady()
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     (#) No-Blocking mode functions with Interrupt are :
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Master_Transmit_IT()
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Master_Receive_IT()
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Transmit_IT()
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Receive_IT()
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Write_IT()
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Read_IT()
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Master_Seq_Transmit_IT()
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Master_Seq_Receive_IT()
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Seq_Transmit_IT()
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Seq_Receive_IT()
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_EnableListen_IT()
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_DisableListen_IT()
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Master_Abort_IT()
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     (#) No-Blocking mode functions with DMA are :
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Master_Transmit_DMA()
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Master_Receive_DMA()
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Transmit_DMA()
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Receive_DMA()
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Write_DMA()
+1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Mem_Read_DMA()
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Master_Seq_Transmit_DMA()
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Master_Seq_Receive_DMA()
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_Slave_Seq_Receive_DMA()
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_MasterTxCpltCallback()
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_MasterRxCpltCallback()
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_SlaveTxCpltCallback()
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_SlaveRxCpltCallback()
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_MemTxCpltCallback()
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_MemRxCpltCallback()
+1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_AddrCallback()
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_ListenCpltCallback()
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_ErrorCallback()
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (++) HAL_I2C_AbortCpltCallback()
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @endverbatim
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @{
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Transmits in master mode an amount of data in blocking mode.
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+ARM GAS  /tmp/ccVyGVF6.s 			page 21
+
+
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pD
+1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                           uint16_t Size, uint32_t Timeout)
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferSize > 0U)
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Preload TX register */
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Send Slave Address */
+1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ARM GAS  /tmp/ccVyGVF6.s 			page 22
+
+
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Send Slave Address */
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     while (hi2c->XferCount > 0U)
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wait until TXIS flag is set */
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Wait until TCR flag is set */
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           return HAL_ERROR;
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = MAX_NBYTE_SIZE;
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = hi2c->XferCount;
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until STOPF flag is set */
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 23
+
+
+1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear STOP Flag */
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear Configuration Register 2 */
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_RESET_CR2(hi2c);
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Receives in master mode an amount of data in blocking mode.
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pDa
+1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          uint16_t Size, uint32_t Timeout)
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ARM GAS  /tmp/ccVyGVF6.s 			page 24
+
+
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Slave Address */
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = 1U;
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     while (hi2c->XferCount > 0U)
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wait until RXNE flag is set */
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Read data from RXDR */
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Wait until TCR flag is set */
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           return HAL_ERROR;
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = MAX_NBYTE_SIZE;
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = hi2c->XferCount;
+1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ARM GAS  /tmp/ccVyGVF6.s 			page 25
+
+
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until STOPF flag is set */
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear STOP Flag */
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear Configuration Register 2 */
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_RESET_CR2(hi2c);
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Transmits in slave mode an amount of data in blocking mode.
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          uint32_t Timeout)
+1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t tmpXferCount;
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef error;
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ARM GAS  /tmp/ccVyGVF6.s 			page 26
+
+
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Preload TX data if no stretch enable */
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Preload TX register */
+1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until ADDR flag is set */
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Flush TX register */
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Flush_TXDR(hi2c);
+1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear ADDR flag */
+1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If 10bit addressing mode is selected */
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wait until ADDR flag is set */
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Disable Address Acknowledge */
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Flush TX register */
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_Flush_TXDR(hi2c);
+1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Clear ADDR flag */
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 27
+
+
+1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until DIR flag is set Transmitter mode */
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Flush TX register */
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Flush_TXDR(hi2c);
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     while (hi2c->XferCount > 0U)
+1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wait until TXIS flag is set */
+1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Disable Address Acknowledge */
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until AF flag is set */
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (error != HAL_OK)
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Check that I2C transfer finished */
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Mean XferCount == 0 */
+1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpXferCount = hi2c->XferCount;
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Reset ErrorCode to NONE */
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Disable Address Acknowledge */
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Flush TX register */
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Flush_TXDR(hi2c);
+ARM GAS  /tmp/ccVyGVF6.s 			page 28
+
+
+1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Clear AF flag */
+1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wait until STOP flag is set */
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Disable Address Acknowledge */
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Clear STOP flag */
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until BUSY flag is reset */
+1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Address Acknowledge */
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Receive in slave mode an amount of data in blocking mode
+1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                         uint32_t Timeout)
+1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ARM GAS  /tmp/ccVyGVF6.s 			page 29
+
+
+1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize = hi2c->XferCount;
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until ADDR flag is set */
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear ADDR flag */
+1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until DIR flag is reset Receiver mode */
+1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     while (hi2c->XferCount > 0U)
+1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wait until RXNE flag is set */
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Disable Address Acknowledge */
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Store Last receive data if any */
+1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Read data from RXDR */
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+ARM GAS  /tmp/ccVyGVF6.s 			page 30
+
+
+1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Increment Buffer pointer */
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->pBuffPtr++;
+1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferCount--;
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize--;
+1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Read data from RXDR */
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until STOP flag is set */
+1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear STOP flag */
+1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until BUSY flag is reset */
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable Address Acknowledge */
+1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Address Acknowledge */
+1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR2 |= I2C_CR2_NACK;
+1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 31
+
+
+1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t 
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                              uint16_t Size)
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_BUSY;
+1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Slave Address */
+1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferSize > 0U)
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Preload TX register */
+1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 32
+
+
+1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
+1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               process unlock */
+1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* possible to enable all of these */
+1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+1764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+1768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+1772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+1776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *
+1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                             uint16_t Size)
+1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+1789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+1793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_BUSY;
+1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+ARM GAS  /tmp/ccVyGVF6.s 			page 33
+
+
+1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = 1U;
+1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+1819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Slave Address */
+1822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ
+1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               process unlock */
+1831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+1833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* possible to enable all of these */
+1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+1839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+1843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+1845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+1848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+1853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+ARM GAS  /tmp/ccVyGVF6.s 			page 34
+
+
+1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+1867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Preload TX data if no stretch enable */
+1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Preload TX register */
+1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+1884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               process unlock */
+1895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+1897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* possible to enable all of these */
+1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+1903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
+1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ARM GAS  /tmp/ccVyGVF6.s 			page 35
+
+
+1913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+1918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+1931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+1944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               process unlock */
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+1947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* possible to enable all of these */
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+1949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+1957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+1961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+1967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ARM GAS  /tmp/ccVyGVF6.s 			page 36
+
+
+1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t
+1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                               uint16_t Size)
+1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t sizetoxfer = 0U;
+1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_BUSY;
+1982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+1990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+1996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+1998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferSize > 0U)
+2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Preload TX register */
+2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       sizetoxfer = hi2c->XferSize;
+2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+2020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferSize > 0U)
+2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->hdmatx != NULL)
+2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the I2C DMA transfer complete callback */
+ARM GAS  /tmp/ccVyGVF6.s 			page 37
+
+
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the DMA error callback */
+2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the unused DMA callbacks to NULL */
+2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferHalfCpltCallback = NULL;
+2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+2035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable the DMA stream */
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C state */
+2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+2045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C error code */
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (dmaxferstatus == HAL_OK)
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Send Slave Address */
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART 
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
+2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            xfermode, I2C_GENERATE_START_WRITE);
+2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update XferCount value */
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferCount -= hi2c->XferSize;
+2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Note : The I2C interrupts must be enabled after unlocking current process
+2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   to avoid the risk of I2C interrupt handle execution before current
+2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   process unlock */
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable ERR and NACK interrupts */
+2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable DMA Request */
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C state */
+2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C error code */
+ARM GAS  /tmp/ccVyGVF6.s 			page 38
+
+
+2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+2093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update Transfer ISR function pointer */
+2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferISR = I2C_Master_ISR_IT;
+2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Send Slave Address */
+2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set NBYTES to write and generate START condition */
+2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
+2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 process unlock */
+2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* possible to enable all of these */
+2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+2113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+2124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t 
+2134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                              uint16_t Size)
+2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccVyGVF6.s 			page 39
+
+
+2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_BUSY;
+2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = 1U;
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferSize > 0U)
+2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->hdmarx != NULL)
+2173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the I2C DMA transfer complete callback */
+2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+2176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the DMA error callback */
+2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the unused DMA callbacks to NULL */
+2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferHalfCpltCallback = NULL;
+2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable the DMA stream */
+2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p
+2186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          hi2c->XferSize);
+2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C state */
+2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C error code */
+2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+ARM GAS  /tmp/ccVyGVF6.s 			page 40
+
+
+2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (dmaxferstatus == HAL_OK)
+2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Send Slave Address */
+2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART *
+2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_
+2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update XferCount value */
+2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferCount -= hi2c->XferSize;
+2211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Note : The I2C interrupts must be enabled after unlocking current process
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   to avoid the risk of I2C interrupt handle execution before current
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   process unlock */
+2218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable ERR and NACK interrupts */
+2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+2220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable DMA Request */
+2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+2225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C state */
+2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+2229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C error code */
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+2232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update Transfer ISR function pointer */
+2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferISR = I2C_Master_ISR_IT;
+2243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Send Slave Address */
+2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set NBYTES to read and generate START condition */
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+2248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+2253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+2254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 process unlock */
+ARM GAS  /tmp/ccVyGVF6.s 			page 41
+
+
+2255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* possible to enable all of these */
+2257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+2258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+2260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+2263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+2265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size
+2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+2288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+2302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Preload TX data if no stretch enable */
+2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Preload TX register */
+2307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+ARM GAS  /tmp/ccVyGVF6.s 			page 42
+
+
+2312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+2315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount != 0U)
+2318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->hdmatx != NULL)
+2320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the I2C DMA transfer complete callback */
+2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+2323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the DMA error callback */
+2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+2326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the unused DMA callbacks to NULL */
+2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferHalfCpltCallback = NULL;
+2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable the DMA stream */
+2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
+2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+2334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          hi2c->XferSize);
+2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+2337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C state */
+2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_LISTEN;
+2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+2341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C error code */
+2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+2344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+2349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (dmaxferstatus == HAL_OK)
+2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable Address Acknowledge */
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Note : The I2C interrupts must be enabled after unlocking current process
+2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   to avoid the risk of I2C interrupt handle execution before current
+2361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   process unlock */
+2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable ERR, STOP, NACK, ADDR interrupts */
+2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable DMA Request */
+2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+ARM GAS  /tmp/ccVyGVF6.s 			page 43
+
+
+2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C state */
+2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_LISTEN;
+2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C error code */
+2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable Address Acknowledge */
+2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+2387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+2392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       to avoid the risk of I2C interrupt handle execution before current
+2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       process unlock */
+2394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, STOP, NACK, ADDR interrupts */
+2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+2408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+2416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+2417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+2424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+ARM GAS  /tmp/ccVyGVF6.s 			page 44
+
+
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+2438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->hdmarx != NULL)
+2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the I2C DMA transfer complete callback */
+2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+2443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the DMA error callback */
+2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+2446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the unused DMA callbacks to NULL */
+2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferHalfCpltCallback = NULL;
+2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+2450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable the DMA stream */
+2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa
+2453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+2456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C state */
+2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+2460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C error code */
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+2463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (dmaxferstatus == HAL_OK)
+2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable Address Acknowledge */
+2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+2479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 process unlock */
+2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, STOP, NACK, ADDR interrupts */
+2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+ARM GAS  /tmp/ccVyGVF6.s 			page 45
+
+
+2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable DMA Request */
+2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+2488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C state */
+2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C error code */
+2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+2495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+2500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+2503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+2507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Write an amount of data in blocking mode to a specific memory address
+2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+2518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddre
+2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                     uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Ti
+2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+2530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+2537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+ARM GAS  /tmp/ccVyGVF6.s 			page 46
+
+
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+2544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK
+2546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+2553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+2558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Slave Address and Memory Address */
+2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL
+2561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+2565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST
+2572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS
+2577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     do
+2580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wait until TXIS flag is set */
+2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+2583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+2585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+2592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+2595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ARM GAS  /tmp/ccVyGVF6.s 			page 47
+
+
+2597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Wait until TCR flag is set */
+2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+2600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+2601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           return HAL_ERROR;
+2602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+2603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+2606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = MAX_NBYTE_SIZE;
+2607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+2608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+2609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+2610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+2611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = hi2c->XferCount;
+2613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+2614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+2615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+2616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     } while (hi2c->XferCount > 0U);
+2619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+2621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until STOPF flag is reset */
+2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+2623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+2625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear STOP Flag */
+2628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+2629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear Configuration Register 2 */
+2631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_RESET_CR2(hi2c);
+2632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+2635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+2646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Read an amount of data in blocking mode from a specific memory address
+2649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+ARM GAS  /tmp/ccVyGVF6.s 			page 48
+
+
+2654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+2659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+2660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddres
+2661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Tim
+2662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+2663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+2664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+2667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Init tickstart for timeout management*/
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tickstart = HAL_GetTick();
+2681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK
+2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+2685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+2688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+2690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr  = pData;
+2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+2695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Slave Address and Memory Address */
+2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_
+2698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Slave Address */
+2705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = 1U;
+2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+2710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ARM GAS  /tmp/ccVyGVF6.s 			page 49
+
+
+2711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+2713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+2715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     do
+2720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wait until RXNE flag is set */
+2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+2725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Read data from RXDR */
+2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+2729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+2732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+2735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+2738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Wait until TCR flag is set */
+2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+2741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           return HAL_ERROR;
+2742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferCount > MAX_NBYTE_SIZE)
+2745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = 1U;
+2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+2748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+2749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+2750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = hi2c->XferCount;
+2753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+2755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     } while (hi2c->XferCount > 0U);
+2758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+2760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until STOPF flag is reset */
+2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+2764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear STOP Flag */
+2767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ARM GAS  /tmp/ccVyGVF6.s 			page 50
+
+
+2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear Configuration Register 2 */
+2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_RESET_CR2(hi2c);
+2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+2779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+2785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+2786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory addres
+2787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+2792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+2796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd
+2798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+2800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+2801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+2809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+2812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_BUSY;
+2814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+2820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = 0U;
+ARM GAS  /tmp/ccVyGVF6.s 			page 51
+
+
+2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+2826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_IT;
+2829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If Memory address size is 8Bit */
+2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+2833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prefetch Memory Address */
+2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+2836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Reset Memaddress content */
+2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Memaddress = 0xFFFFFFFFU;
+2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If Memory address size is 16Bit */
+2841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+2842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prepare Memaddress buffer for LSB part */
+2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Slave Address and Memory Address */
+2850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_W
+2851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+2854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+2857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               process unlock */
+2858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* possible to enable all of these */
+2861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+2863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+2868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+2870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+2872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+2874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory addre
+2875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+2880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+ARM GAS  /tmp/ccVyGVF6.s 			page 52
+
+
+2882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+2884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAdd
+2886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+2888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+2897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+2900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_BUSY;
+2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+2915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_IT;
+2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+2917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If Memory address size is 8Bit */
+2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+2920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prefetch Memory Address */
+2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+2923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Reset Memaddress content */
+2925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Memaddress = 0xFFFFFFFFU;
+2926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If Memory address size is 16Bit */
+2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+2932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prepare Memaddress buffer for LSB part */
+2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Slave Address and Memory Address */
+2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_
+2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 53
+
+
+2939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+2941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+2943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+2944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               process unlock */
+2945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+2947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* possible to enable all of these */
+2948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+2951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+2953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+2955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+2958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+2959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+2961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+2962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+2963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+2964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+2965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+2968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+2969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+2971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+2972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemA
+2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                         uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+2975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+2976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+2978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+2979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+2981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+2986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+2989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+2990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_BUSY;
+2991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+2992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+2993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+2995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 54
+
+
+2996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+2999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_DMA;
+3005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+3006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+3008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+3010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+3014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If Memory address size is 8Bit */
+3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+3018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prefetch Memory Address */
+3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Reset Memaddress content */
+3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Memaddress = 0xFFFFFFFFU;
+3024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If Memory address size is 16Bit */
+3026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+3030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prepare Memaddress buffer for LSB part */
+3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+3033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->hdmatx != NULL)
+3036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the I2C DMA transfer complete callback */
+3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+3039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the DMA error callback */
+3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+3042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the unused DMA callbacks to NULL */
+3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferHalfCpltCallback = NULL;
+3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable the DMA stream */
+3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX
+3049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+3050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccVyGVF6.s 			page 55
+
+
+3053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C state */
+3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_READY;
+3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+3056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C error code */
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+3059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+3064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (dmaxferstatus == HAL_OK)
+3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Send Slave Address and Memory Address */
+3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START
+3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+3076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 process unlock */
+3077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+3078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* possible to enable all of these */
+3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+3080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+3082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C state */
+3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_READY;
+3087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+3088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C error code */
+3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+3096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+ARM GAS  /tmp/ccVyGVF6.s 			page 56
+
+
+3110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+3111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+3114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be read
+3116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+3117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+3118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd
+3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+3127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+3132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+3135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_BUSY;
+3137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+3144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+3145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_DMA;
+3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+3154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+3160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If Memory address size is 8Bit */
+3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prefetch Memory Address */
+3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ARM GAS  /tmp/ccVyGVF6.s 			page 57
+
+
+3167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Reset Memaddress content */
+3169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Memaddress = 0xFFFFFFFFU;
+3170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If Memory address size is 16Bit */
+3172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+3176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prepare Memaddress buffer for LSB part */
+3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+3179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->hdmarx != NULL)
+3182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the I2C DMA transfer complete callback */
+3184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+3185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the DMA error callback */
+3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the unused DMA callbacks to NULL */
+3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferHalfCpltCallback = NULL;
+3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+3192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable the DMA stream */
+3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa
+3195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C state */
+3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_READY;
+3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C error code */
+3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+3210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (dmaxferstatus == HAL_OK)
+3213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Send Slave Address and Memory Address */
+3215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_STAR
+3216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+3218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+3221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+3222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 process unlock */
+3223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ARM GAS  /tmp/ccVyGVF6.s 			page 58
+
+
+3224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* possible to enable all of these */
+3225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+3226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+3228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C state */
+3232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_READY;
+3233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+3234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C error code */
+3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+3237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+3242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+3245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+3247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+3249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+3251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+3253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Checks if target device is ready for communication.
+3254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @note   This function is used with Memory devices
+3255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+3258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+3259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Trials Number of trials
+3260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+3261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+3262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+3263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Tria
+3264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                         uint32_t Timeout)
+3265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+3267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __IO uint32_t I2C_Trials = 0UL;
+3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   FlagStatus tmp1;
+3271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   FlagStatus tmp2;
+3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+3274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+3276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_BUSY;
+3278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+ARM GAS  /tmp/ccVyGVF6.s 			page 59
+
+
+3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_BUSY;
+3284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     do
+3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Generate Start */
+3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+3290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+3292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wait until STOPF flag is set or a NACK flag is set*/
+3293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tickstart = HAL_GetTick();
+3294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+3296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+3297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       while ((tmp1 == RESET) && (tmp2 == RESET))
+3299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (Timeout != HAL_MAX_DELAY)
+3301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+3303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+3304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Update I2C state */
+3305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             hi2c->State = HAL_I2C_STATE_READY;
+3306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Update I2C error code */
+3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+3309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Process Unlocked */
+3311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             __HAL_UNLOCK(hi2c);
+3312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             return HAL_ERROR;
+3314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+3315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+3316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+3319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Check if the NACKF flag has not been set */
+3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+3323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Wait until STOPF flag is reset */
+3325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+3326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+3327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           return HAL_ERROR;
+3328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+3329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Clear STOP Flag */
+3331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+3332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Device is ready */
+3334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+3335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+ARM GAS  /tmp/ccVyGVF6.s 			page 60
+
+
+3338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_OK;
+3340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+3342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Wait until STOPF flag is reset */
+3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+3346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           return HAL_ERROR;
+3347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+3348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Clear NACK Flag */
+3350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+3351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Clear STOP Flag, auto generated with autoend*/
+3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Trials */
+3357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Trials++;
+3358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     } while (I2C_Trials < Trials);
+3359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Update I2C state */
+3361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+3362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Update I2C error code */
+3364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+3365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+3368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+3370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+3372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+3374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+3376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+3378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Inte
+3379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+3380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+3383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+3384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+3386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+3387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+3389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint
+3390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                  uint16_t Size, uint32_t XferOptions)
+3391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+3392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+3393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+3394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t sizetoxfer = 0U;
+ARM GAS  /tmp/ccVyGVF6.s 			page 61
+
+
+3395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+3397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+3398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+3400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+3406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+3413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+3415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+3424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+3427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+3428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Preload TX register */
+3430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+3432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+3434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+3435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       sizetoxfer = hi2c->XferSize;
+3437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+3438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+3439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If transfer direction not change and there is no request to start another frame,
+3442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        do not generate Restart Condition */
+3443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Mean Previous state is same as current state */
+3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+3445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+3446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xferrequest = I2C_NO_STARTSTOP;
+3448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Convert OTHER_xxx XferOptions if any */
+ARM GAS  /tmp/ccVyGVF6.s 			page 62
+
+
+3452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ConvertOtherXferOptions(hi2c);
+3453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update xfermode accordingly if no reload is necessary */
+3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+3456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         xfermode = hi2c->XferOptions;
+3458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Slave Address and set NBYTES to write */
+3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+3463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+3465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+3469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+3473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+3475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+3476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               process unlock */
+3477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+3478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* possible to enable all of these */
+3479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+3481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+3482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+3484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+3486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+3488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+3490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+3492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+3493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+3494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+3497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+3498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+3500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+3501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+3502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+3503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin
+3504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                   uint16_t Size, uint32_t XferOptions)
+3505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+3506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+3508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ARM GAS  /tmp/ccVyGVF6.s 			page 63
+
+
+3509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t sizetoxfer = 0U;
+3510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+3512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+3513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+3515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+3520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+3521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+3527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+3528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+3530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+3531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+3533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+3534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+3538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+3539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+3542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+3543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Preload TX register */
+3545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+3547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+3550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       sizetoxfer = hi2c->XferSize;
+3552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+3553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+3554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If transfer direction not change and there is no request to start another frame,
+3557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        do not generate Restart Condition */
+3558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Mean Previous state is same as current state */
+3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+3560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+3561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xferrequest = I2C_NO_STARTSTOP;
+3563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccVyGVF6.s 			page 64
+
+
+3566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Convert OTHER_xxx XferOptions if any */
+3567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ConvertOtherXferOptions(hi2c);
+3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update xfermode accordingly if no reload is necessary */
+3570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+3571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         xfermode = hi2c->XferOptions;
+3573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferSize > 0U)
+3577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->hdmatx != NULL)
+3579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the I2C DMA transfer complete callback */
+3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+3582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the DMA error callback */
+3584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+3585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the unused DMA callbacks to NULL */
+3587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferHalfCpltCallback = NULL;
+3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+3589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable the DMA stream */
+3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+3592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+3593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+3595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C state */
+3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+3599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C error code */
+3601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+3602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+3604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+3607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (dmaxferstatus == HAL_OK)
+3610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Send Slave Address and set NBYTES to write */
+3612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+3614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+3615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+3616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+3617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+3619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update XferCount value */
+3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferCount -= hi2c->XferSize;
+ARM GAS  /tmp/ccVyGVF6.s 			page 65
+
+
+3623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+3625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Note : The I2C interrupts must be enabled after unlocking current process
+3628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   to avoid the risk of I2C interrupt handle execution before current
+3629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   process unlock */
+3630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable ERR and NACK interrupts */
+3631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+3632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable DMA Request */
+3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+3635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+3637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C state */
+3639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+3640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+3641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C error code */
+3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+3644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+3649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update Transfer ISR function pointer */
+3654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferISR = I2C_Master_ISR_IT;
+3655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Send Slave Address */
+3657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set NBYTES to write and generate START condition */
+3658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+3659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+3661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+3663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+3665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+3668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+3672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 process unlock */
+3673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+3674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* possible to enable all of these */
+3675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+3676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+3678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 66
+
+
+3680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+3681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+3683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+3685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+3687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+3689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Inter
+3690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+3691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+3694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+3695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+3697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+3700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8
+3701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                 uint16_t Size, uint32_t XferOptions)
+3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+3703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+3704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_READ;
+3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+3707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+3708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+3710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+3715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+3716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+3723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+3726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+3728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+3729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+3734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If transfer direction not change and there is no request to start another frame,
+ARM GAS  /tmp/ccVyGVF6.s 			page 67
+
+
+3737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        do not generate Restart Condition */
+3738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Mean Previous state is same as current state */
+3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+3740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+3741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xferrequest = I2C_NO_STARTSTOP;
+3743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Convert OTHER_xxx XferOptions if any */
+3747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ConvertOtherXferOptions(hi2c);
+3748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update xfermode accordingly if no reload is necessary */
+3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+3751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         xfermode = hi2c->XferOptions;
+3753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Slave Address and set NBYTES to read */
+3757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+3758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+3761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+3763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+3764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               process unlock */
+3765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+3766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+3768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+3770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+3772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+3774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+3776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+3777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+3778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+3781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+3782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+3784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+3785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+3786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+3787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint
+3788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                  uint16_t Size, uint32_t XferOptions)
+3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+3791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_READ;
+3792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 68
+
+
+3794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+3795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+3796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+3803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+3804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+3805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+3807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+3808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+3809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+3811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+3813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+3814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+3816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+3817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+3822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If transfer direction not change and there is no request to start another frame,
+3825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        do not generate Restart Condition */
+3826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Mean Previous state is same as current state */
+3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+3828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+3829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xferrequest = I2C_NO_STARTSTOP;
+3831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Convert OTHER_xxx XferOptions if any */
+3835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ConvertOtherXferOptions(hi2c);
+3836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update xfermode accordingly if no reload is necessary */
+3838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+3839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         xfermode = hi2c->XferOptions;
+3841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferSize > 0U)
+3845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->hdmarx != NULL)
+3847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the I2C DMA transfer complete callback */
+3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+3850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 69
+
+
+3851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the DMA error callback */
+3852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+3853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set the unused DMA callbacks to NULL */
+3855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferHalfCpltCallback = NULL;
+3856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+3857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable the DMA stream */
+3859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p
+3860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          hi2c->XferSize);
+3861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+3863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C state */
+3865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+3866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+3867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C error code */
+3869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+3870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+3872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+3875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (dmaxferstatus == HAL_OK)
+3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Send Slave Address and set NBYTES to read */
+3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+3881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update XferCount value */
+3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferCount -= hi2c->XferSize;
+3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+3886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Note : The I2C interrupts must be enabled after unlocking current process
+3889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   to avoid the risk of I2C interrupt handle execution before current
+3890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                   process unlock */
+3891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable ERR and NACK interrupts */
+3892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+3893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Enable DMA Request */
+3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+3896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+3898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C state */
+3900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State     = HAL_I2C_STATE_READY;
+3901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Update I2C error code */
+3904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+3905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+ARM GAS  /tmp/ccVyGVF6.s 			page 70
+
+
+3908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+3911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update Transfer ISR function pointer */
+3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferISR = I2C_Master_ISR_IT;
+3916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Send Slave Address */
+3918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set NBYTES to read and generate START condition */
+3919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+3920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+3921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+3923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+3924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Note : The I2C interrupts must be enabled after unlocking current process
+3926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 to avoid the risk of I2C interrupt handle execution before current
+3927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                 process unlock */
+3928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+3929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* possible to enable all of these */
+3930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+3931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+3932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+3933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+3936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+3938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+3941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+3942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+3944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit
+3945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+3946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+3947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+3948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+3949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+3950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+3951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+3952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+3953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S
+3954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                 uint32_t XferOptions)
+3955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+3956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+3957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   FlagStatus tmp;
+3958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+3960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+3961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+3963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+3964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+ARM GAS  /tmp/ccVyGVF6.s 			page 71
+
+
+3965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+3968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+3969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+3972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+3975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* and then toggle the HAL slave RX state to TX state */
+3978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+3979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+3980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable associated Interrupts */
+3981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+3982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Abort DMA Xfer if any */
+3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+3985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+3987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->hdmarx != NULL)
+3989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+3990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+3991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+3993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+3994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Abort DMA RX */
+3995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+3996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+3997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+3999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+4000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+4001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+4002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+4006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+4007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+4010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+4012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+4013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+4014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+4015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+4017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
+4020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Clear ADDR flag after prepare the transfer parameters */
+ARM GAS  /tmp/ccVyGVF6.s 			page 72
+
+
+4022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* This action will generate an acknowledge to the Master */
+4023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+4024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+4028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+4030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     to avoid the risk of I2C interrupt handle execution before current
+4031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     process unlock */
+4032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* REnable ADDR interrupt */
+4033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+4034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+4036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+4038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+4040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit
+4045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+4046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+4049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+4050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+4051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+4052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t 
+4054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                  uint32_t XferOptions)
+4055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+4057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   FlagStatus tmp;
+4058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+4059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+4061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+4062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+4064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+4066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+4068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+4069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+4073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+4075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+4076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+4078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* and then toggle the HAL slave RX state to TX state */
+ARM GAS  /tmp/ccVyGVF6.s 			page 73
+
+
+4079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable associated Interrupts */
+4082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+4083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+4085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+4086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Abort DMA Xfer if any */
+4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->hdmarx != NULL)
+4088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+4089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+4090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+4092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+4093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+4094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Abort DMA RX */
+4096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+4097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+4098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+4100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+4101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+4102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+4103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+4105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+4107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+4108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+4109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Abort DMA Xfer if any */
+4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->hdmatx != NULL)
+4112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+4113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+4114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+4115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+4116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Abort DMA TX */
+4118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+4119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+4120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+4122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+4123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+4124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+4125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+4127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Nothing to do */
+4129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+4132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+4133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+4134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+ARM GAS  /tmp/ccVyGVF6.s 			page 74
+
+
+4136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+4137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+4139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+4142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+4143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+4144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->hdmatx != NULL)
+4146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the I2C DMA transfer complete callback */
+4148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+4149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the DMA error callback */
+4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+4152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the unused DMA callbacks to NULL */
+4154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferHalfCpltCallback = NULL;
+4155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+4156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable the DMA stream */
+4158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX
+4159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+4160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+4162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C state */
+4164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+4165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+4166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C error code */
+4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+4171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+4172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+4174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (dmaxferstatus == HAL_OK)
+4177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update XferCount value */
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount -= hi2c->XferSize;
+4180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Reset XferSize */
+4182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = 0;
+4183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+4185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C state */
+4187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+4188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+4189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C error code */
+4191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+4192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 75
+
+
+4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+4194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+4195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+4197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
+4201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Clear ADDR flag after prepare the transfer parameters */
+4203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* This action will generate an acknowledge to the Master */
+4204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+4205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+4208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable DMA Request */
+4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+4212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+4214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     to avoid the risk of I2C interrupt handle execution before current
+4215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     process unlock */
+4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable ERR, STOP, NACK, ADDR interrupts */
+4217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+4218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+4220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+4222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+4224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with
+4229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+4230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+4233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+4234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+4235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+4236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Si
+4238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                uint32_t XferOptions)
+4239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   FlagStatus tmp;
+4242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+4244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+4245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+4247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+4249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccVyGVF6.s 			page 76
+
+
+4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+4251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+4252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+4255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+4256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+4259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+4261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* and then toggle the HAL slave TX state to RX state */
+4262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+4263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable associated Interrupts */
+4265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+4266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+4268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+4269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+4270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Abort DMA Xfer if any */
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->hdmatx != NULL)
+4273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+4274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+4275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+4276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+4277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Abort DMA TX */
+4279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+4280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+4283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+4284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+4285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+4286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+4289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+4290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+4291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+4293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+4294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+4296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+4300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+4301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
+4304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Clear ADDR flag after prepare the transfer parameters */
+4306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* This action will generate an acknowledge to the Master */
+ARM GAS  /tmp/ccVyGVF6.s 			page 77
+
+
+4307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+4308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+4312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+4314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     to avoid the risk of I2C interrupt handle execution before current
+4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     process unlock */
+4316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* REnable ADDR interrupt */
+4317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+4318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+4320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+4322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+4324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with
+4329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @note   This interface allow to manage repeated start condition when a direction change during 
+4330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  pData Pointer to data buffer
+4333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Amount of data to be sent
+4334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+4335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+4336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S
+4338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                 uint32_t XferOptions)
+4339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+4341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   FlagStatus tmp;
+4342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+4343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+4346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+4348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((pData == NULL) || (Size == 0U))
+4350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+4352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+4353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+4356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+4357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+4360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+4362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* and then toggle the HAL slave TX state to RX state */
+4363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ARM GAS  /tmp/ccVyGVF6.s 			page 78
+
+
+4364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable associated Interrupts */
+4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+4367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+4369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+4370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Abort DMA Xfer if any */
+4371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->hdmatx != NULL)
+4372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+4373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+4374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+4376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+4377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+4378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Abort DMA TX */
+4380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+4381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+4382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+4384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+4385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+4386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+4387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+4389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+4391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+4393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Abort DMA Xfer if any */
+4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->hdmarx != NULL)
+4396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+4397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Set the I2C DMA Abort callback :
+4398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+4399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+4400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Abort DMA RX */
+4402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+4403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+4404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Call Directly XferAbortCallback function in case of error */
+4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+4406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+4407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+4408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+4409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+4411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Nothing to do */
+4413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+4416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+4417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+4418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable Address Acknowledge */
+4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+ARM GAS  /tmp/ccVyGVF6.s 			page 79
+
+
+4421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Prepare transfer parameters */
+4423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+4424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+4425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+4427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+4428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->hdmarx != NULL)
+4430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the I2C DMA transfer complete callback */
+4432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+4433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the DMA error callback */
+4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+4436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the unused DMA callbacks to NULL */
+4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferHalfCpltCallback = NULL;
+4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+4440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable the DMA stream */
+4442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
+4443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        (uint32_t)pData, hi2c->XferSize);
+4444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+4446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C state */
+4448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+4449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+4450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C error code */
+4452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+4453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+4456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+4458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (dmaxferstatus == HAL_OK)
+4461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update XferCount value */
+4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount -= hi2c->XferSize;
+4464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Reset XferSize */
+4466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = 0;
+4467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+4469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C state */
+4471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->State     = HAL_I2C_STATE_LISTEN;
+4472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+4473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update I2C error code */
+4475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+4476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+ARM GAS  /tmp/ccVyGVF6.s 			page 80
+
+
+4478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+4479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+4481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
+4485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Clear ADDR flag after prepare the transfer parameters */
+4487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* This action will generate an acknowledge to the Master */
+4488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+4489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+4493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable DMA Request */
+4495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+4496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+4498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     to avoid the risk of I2C interrupt handle execution before current
+4499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     process unlock */
+4500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* REnable ADDR interrupt */
+4501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+4502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+4504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+4506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+4508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Enable the Address listen mode with Interrupt.
+4513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+4516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+4518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+4520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_LISTEN;
+4522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR = I2C_Slave_ISR_IT;
+4523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable the Address Match interrupt */
+4525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+4526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+4528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+4530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+4532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 81
+
+
+4535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Disable the Address listen mode with Interrupt.
+4537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C
+4539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+4540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+4542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+4544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmp;
+4545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable Address listen mode only if a transfer is not ongoing */
+4547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_LISTEN)
+4548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+4551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+4552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+4553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR = NULL;
+4554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable the Address Match interrupt */
+4556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+4557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+4559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+4561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_BUSY;
+4563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Abort a master or memory I2C IT or DMA process communication with Interrupt.
+4568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+4571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+4572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+4573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+4575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
+4577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
+4579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Locked */
+4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_LOCK(hi2c);
+4582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupts and Store Previous state */
+4584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+4585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+4587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+4588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+4590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ARM GAS  /tmp/ccVyGVF6.s 			page 82
+
+
+4592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+4593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+4595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Do nothing */
+4597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set State at HAL_I2C_STATE_ABORT */
+4600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_ABORT;
+4601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+4603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfe
+4604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+4605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+4607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+4608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Note : The I2C interrupts must be enabled after unlocking current process
+4610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               to avoid the risk of I2C interrupt handle execution before current
+4611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               process unlock */
+4612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+4613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_OK;
+4615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+4617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wrong usage of abort function */
+4619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* This function should be used only in case of abort monitored by master device */
+4620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+4621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @}
+4626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+4629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @{
+4630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  This function handles I2C event interrupt request.
+4634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
+4639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Get current IT Flags and IT sources value */
+4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+4642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+4643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* I2C events treatment -------------------------------------*/
+4645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->XferISR != NULL)
+4646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR(hi2c, itflags, itsources);
+4648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccVyGVF6.s 			page 83
+
+
+4649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  This function handles I2C error interrupt request.
+4653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+4658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+4660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+4661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmperror;
+4662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* I2C Bus error interrupt occurred ------------------------------------*/
+4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
+4665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+4666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+4668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear BERR flag */
+4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+4671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+4674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
+4675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+4676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+4678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear OVR flag */
+4680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+4681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+4684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
+4685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+4686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+4688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear ARLO flag */
+4690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+4691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Store current volatile hi2c->ErrorCode, misra rule */
+4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   tmperror = hi2c->ErrorCode;
+4695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Call the Error Callback in case of Error detected */
+4697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_
+4698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITError(hi2c, tmperror);
+4700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Master Tx Transfer completed callback.
+4705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ARM GAS  /tmp/ccVyGVF6.s 			page 84
+
+
+4706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+4710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+4713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+4716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+4717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Master Rx Transfer completed callback.
+4721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+4726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+4729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+4732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+4733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @brief  Slave Tx Transfer completed callback.
+4736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+4744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+4747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Slave Rx Transfer completed callback.
+4752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+4757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+4760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+ARM GAS  /tmp/ccVyGVF6.s 			page 85
+
+
+4763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+4764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Slave Address Match callback.
+4768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFE
+4771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  AddrMatchCode Address Match Code
+4772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrM
+4775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(TransferDirection);
+4779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(AddrMatchCode);
+4780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_AddrCallback() could be implemented in the user file
+4783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Listen Complete callback.
+4788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+4793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+4796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+4799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Memory Tx Transfer completed callback.
+4804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+4809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+4812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+4815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+4816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Memory Rx Transfer completed callback.
+ARM GAS  /tmp/ccVyGVF6.s 			page 86
+
+
+4820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+4825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+4828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+4831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  I2C error callback.
+4836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+4841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+4844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_ErrorCallback could be implemented in the user file
+4847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+4848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  I2C abort callback.
+4852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+4855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+4859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(hi2c);
+4860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+4862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             the HAL_I2C_AbortCpltCallback could be implemented in the user file
+4863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****    */
+4864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @}
+4868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+4871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *  @brief   Peripheral State, Mode and Error functions
+4872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *
+4873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @verbatim
+4874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****  ===============================================================================
+4875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             ##### Peripheral State, Mode and Error functions #####
+4876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****  ===============================================================================
+ARM GAS  /tmp/ccVyGVF6.s 			page 87
+
+
+4877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     [..]
+4878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     This subsection permit to get in run-time the status of the peripheral
+4879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     and the data flow.
+4880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @endverbatim
+4882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @{
+4883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Return the I2C handle state.
+4887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL state
+4890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
+4892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Return I2C handle state */
+4894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return hi2c->State;
+4895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Returns the I2C Master, Slave, Memory or no mode.
+4899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         the configuration information for I2C module
+4901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL mode
+4902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
+4904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return hi2c->Mode;
+4906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Return the I2C error code.
+4910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+4911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *              the configuration information for the specified I2C.
+4912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval I2C Error Code
+4913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
+4915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return hi2c->ErrorCode;
+4917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+4918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @}
+4921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @}
+4925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @addtogroup I2C_Private_Functions
+4928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @{
+4929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+4932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+4933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ARM GAS  /tmp/ccVyGVF6.s 			page 88
+
+
+4934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+4935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+4936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITSources Interrupt sources enabled.
+4937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+4938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+4939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+4940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                            uint32_t ITSources)
+4941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+4942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t devaddress;
+4943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+4944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process Locked */
+4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+4947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+4949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+4950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear NACK Flag */
+4952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+4953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set corresponding Error Code */
+4955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* No need to generate STOP, it is automatically done */
+4956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Error callback will be send during stop flag treatment */
+4957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+4958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Flush TX register */
+4960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Flush_TXDR(hi2c);
+4961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+4963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+4964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Remove RXNE flag on temporary variable as read done */
+4966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmpITFlags &= ~I2C_FLAG_RXNE;
+4967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Read data from RXDR */
+4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+4970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Increment Buffer pointer */
+4972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr++;
+4973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize--;
+4975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount--;
+4976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
+4978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+4979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
+4980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Write data to TXDR */
+4982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount != 0U)
+4983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+4986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+4989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ARM GAS  /tmp/ccVyGVF6.s 			page 89
+
+
+4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+4992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+4993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+4995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+4996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+4998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->XferCount > MAX_NBYTE_SIZE)
+5002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Errata workaround 170323 */
+5004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+5005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = 1U;
+5007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+5009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = MAX_NBYTE_SIZE;
+5011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START
+5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferSize = hi2c->XferCount;
+5017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+5018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+5020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              hi2c->XferOptions, I2C_NO_STARTSTOP);
+5021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+5023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+5026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call TxCpltCallback() if no stop mode is set */
+5032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+5033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call I2C Master Sequential complete process */
+5035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_ITMasterSeqCplt(hi2c);
+5036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Wrong size Status regarding TCR flag event */
+5040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call the corresponding callback to inform upper layer of End of Transfer */
+5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+5042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+5046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+5047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccVyGVF6.s 			page 90
+
+
+5048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount == 0U)
+5049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+5051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Generate a stop condition in case of no transfer option */
+5053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+5054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Generate Stop */
+5056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->Instance->CR2 |= I2C_CR2_STOP;
+5057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+5059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Call I2C Master Sequential complete process */
+5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_ITMasterSeqCplt(hi2c);
+5062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wrong size Status regarding TC flag event */
+5068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+5070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+5073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Nothing to do */
+5075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+5078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call I2C Master complete process */
+5081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITMasterCplt(hi2c, tmpITFlags);
+5082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process Unlocked */
+5085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+5086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+5088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+5089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+5091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
+5092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+5093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+5094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITSources Interrupt sources enabled.
+5096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+5098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+5099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                         uint32_t ITSources)
+5100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+5101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t direction = I2C_GENERATE_START_WRITE;
+5102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+5103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process Locked */
+ARM GAS  /tmp/ccVyGVF6.s 			page 91
+
+
+5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+5106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+5108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+5109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear NACK Flag */
+5111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set corresponding Error Code */
+5114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* No need to generate STOP, it is automatically done */
+5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Error callback will be send during stop flag treatment */
+5116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+5117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Flush TX register */
+5119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Flush_TXDR(hi2c);
+5120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+5122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+5123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Remove RXNE flag on temporary variable as read done */
+5125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmpITFlags &= ~I2C_FLAG_RXNE;
+5126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Read data from RXDR */
+5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+5129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Increment Buffer pointer */
+5131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr++;
+5132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize--;
+5134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount--;
+5135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+5137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+5138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->Memaddress == 0xFFFFFFFFU)
+5140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+5143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+5145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+5146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+5148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write LSB part of Memory Address */
+5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = hi2c->Memaddress;
+5154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Reset Memaddress content */
+5156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Memaddress = 0xFFFFFFFFU;
+5157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+5160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+5161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccVyGVF6.s 			page 92
+
+
+5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+5163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->XferCount > MAX_NBYTE_SIZE)
+5165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Errata workaround 170323 */
+5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+5168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = 1U;
+5170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+5172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = MAX_NBYTE_SIZE;
+5174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+5176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+5177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferSize = hi2c->XferCount;
+5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+5182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+5183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wrong size Status regarding TCR flag event */
+5188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+5190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+5193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+5194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupt related to address step */
+5196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+5197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+5199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+5200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+5202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       direction = I2C_GENERATE_START_READ;
+5204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+5207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Errata workaround 170323 */
+5209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+5210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferSize = 1U;
+5212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferSize = MAX_NBYTE_SIZE;
+5216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ARM GAS  /tmp/ccVyGVF6.s 			page 93
+
+
+5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+5220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_RELOAD_MODE, direction);
+5221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+5225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set NBYTES to write and generate RESTART */
+5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+5228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+5229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+5232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Nothing to do */
+5234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+5237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+5238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call I2C Master complete process */
+5240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITMasterCplt(hi2c, tmpITFlags);
+5241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process Unlocked */
+5244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+5245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+5247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+5248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+5250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+5251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+5252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+5253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITSources Interrupt sources enabled.
+5255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+5257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+5258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                           uint32_t ITSources)
+5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+5260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+5261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+5262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process locked */
+5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+5265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check if STOPF is set */
+5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+5268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+5269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call I2C Slave complete process */
+5271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITSlaveCplt(hi2c, tmpITFlags);
+5272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+5274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+5275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccVyGVF6.s 			page 94
+
+
+5276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check that I2C transfer finished */
+5277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+5278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Mean XferCount == 0*/
+5279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* So clear Flag NACKF only */
+5280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount == 0U)
+5281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+5283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+5284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            Warning[Pa134]: left and right operands are identical */
+5285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call I2C Listen complete process */
+5287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_ITListenCplt(hi2c, tmpITFlags);
+5288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)
+5290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Clear NACK Flag */
+5292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Flush TX register */
+5295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_Flush_TXDR(hi2c);
+5296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Last Byte is Transmitted */
+5298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call I2C Slave Sequential complete process */
+5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_ITSlaveSeqCplt(hi2c);
+5300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Clear NACK Flag */
+5304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+5310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Clear NACK Flag */
+5311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set ErrorCode corresponding to a Non-Acknowledge */
+5314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+5315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+5317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call the corresponding callback to inform upper layer of End of Transfer */
+5319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_ITError(hi2c, hi2c->ErrorCode);
+5320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+5324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+5325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > 0U)
+5327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Read data from RXDR */
+5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+5330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+5332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+ARM GAS  /tmp/ccVyGVF6.s 			page 95
+
+
+5333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+5335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+5336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->XferCount == 0U) && \
+5339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (tmpoptions != I2C_NO_OPTION_FRAME))
+5340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call I2C Slave Sequential complete process */
+5342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ITSlaveSeqCplt(hi2c);
+5343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
+5346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+5347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITAddrCplt(hi2c, tmpITFlags);
+5349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+5351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+5352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Write data to TXDR only if XferCount not reach "0" */
+5354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* A TXIS flag can be set, during STOP treatment      */
+5355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check if all Data have already been sent */
+5356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+5357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > 0U)
+5358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Write data to TXDR */
+5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+5361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Increment Buffer pointer */
+5363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->pBuffPtr++;
+5364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+5366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+5367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+5371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Last Byte is Transmitted */
+5373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call I2C Slave Sequential complete process */
+5374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_ITSlaveSeqCplt(hi2c);
+5375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+5379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Nothing to do */
+5381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process Unlocked */
+5384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+5385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+5388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ARM GAS  /tmp/ccVyGVF6.s 			page 96
+
+
+5390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+5391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+5392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+5393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITSources Interrupt sources enabled.
+5395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+5396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+5397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+5398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                             uint32_t ITSources)
+5399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+5400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t devaddress;
+5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+5402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process Locked */
+5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+5405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+5407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+5408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear NACK Flag */
+5410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set corresponding Error Code */
+5413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+5414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* No need to generate STOP, it is automatically done */
+5416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* But enable STOP interrupt, to treat it */
+5417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Error callback will be send during stop flag treatment */
+5418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+5419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Flush TX register */
+5421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Flush_TXDR(hi2c);
+5422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+5424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+5425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable TC interrupt */
+5427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+5428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount != 0U)
+5430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Recover Slave address */
+5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+5433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prepare the new XferSize to transfer */
+5435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->XferCount > MAX_NBYTE_SIZE)
+5436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Errata workaround 170323 */
+5438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+5439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = 1U;
+5441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+5443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = MAX_NBYTE_SIZE;
+5445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         xfermode = I2C_RELOAD_MODE;
+ARM GAS  /tmp/ccVyGVF6.s 			page 97
+
+
+5447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferSize = hi2c->XferCount;
+5451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           xfermode = hi2c->XferOptions;
+5454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+5456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           xfermode = I2C_AUTOEND_MODE;
+5458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the new XferSize in Nbytes register */
+5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+5463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update XferCount value */
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount -= hi2c->XferSize;
+5466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable DMA Request */
+5468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+5469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+5471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+5475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call TxCpltCallback() if no stop mode is set */
+5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+5481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call I2C Master Sequential complete process */
+5483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_ITMasterSeqCplt(hi2c);
+5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Wrong size Status regarding TCR flag event */
+5488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call the corresponding callback to inform upper layer of End of Transfer */
+5489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+5490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+5494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+5495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount == 0U)
+5497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+5499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Generate a stop condition in case of no transfer option */
+5501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+5502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Generate Stop */
+ARM GAS  /tmp/ccVyGVF6.s 			page 98
+
+
+5504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->Instance->CR2 |= I2C_CR2_STOP;
+5505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+5507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Call I2C Master Sequential complete process */
+5509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_ITMasterSeqCplt(hi2c);
+5510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wrong size Status regarding TC flag event */
+5516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+5518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+5521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+5522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call I2C Master complete process */
+5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITMasterCplt(hi2c, ITFlags);
+5525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+5527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Nothing to do */
+5529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process Unlocked */
+5532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+5533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+5535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+5536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+5538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
+5539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+5540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+5541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITSources Interrupt sources enabled.
+5543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+5544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+5545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+5546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          uint32_t ITSources)
+5547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+5548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t direction = I2C_GENERATE_START_WRITE;
+5549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process Locked */
+5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+5552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+5554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+5555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear NACK Flag */
+5557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set corresponding Error Code */
+5560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ARM GAS  /tmp/ccVyGVF6.s 			page 99
+
+
+5561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* No need to generate STOP, it is automatically done */
+5563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* But enable STOP interrupt, to treat it */
+5564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Error callback will be send during stop flag treatment */
+5565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+5566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Flush TX register */
+5568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Flush_TXDR(hi2c);
+5569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
+5571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+5572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Write LSB part of Memory Address */
+5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->TXDR = hi2c->Memaddress;
+5575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Reset Memaddress content */
+5577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Memaddress = 0xFFFFFFFFU;
+5578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+5580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+5581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupt related to address step */
+5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+5584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable only Error interrupt */
+5586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+5587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount != 0U)
+5589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Prepare the new XferSize to transfer */
+5591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->XferCount > MAX_NBYTE_SIZE)
+5592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Errata workaround 170323 */
+5594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+5595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = 1U;
+5597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+5599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize = MAX_NBYTE_SIZE;
+5601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+5603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+5604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferSize = hi2c->XferCount;
+5608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+5609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+5610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Update XferCount value */
+5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount -= hi2c->XferSize;
+5614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable DMA Request */
+5616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+5617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ARM GAS  /tmp/ccVyGVF6.s 			page 100
+
+
+5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+5619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+5623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Wrong size Status regarding TCR flag event */
+5628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+5629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+5630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+5633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+5634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupt related to address step */
+5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+5637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable only Error and NACK interrupt for data transfer */
+5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+5640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+5642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       direction = I2C_GENERATE_START_READ;
+5644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+5647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Errata workaround 170323 */
+5649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+5650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferSize = 1U;
+5652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferSize = MAX_NBYTE_SIZE;
+5656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+5660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_RELOAD_MODE, direction);
+5661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+5665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set NBYTES to write and generate RESTART */
+5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+5668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+5669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Update XferCount value */
+5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount -= hi2c->XferSize;
+5673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable DMA Request */
+ARM GAS  /tmp/ccVyGVF6.s 			page 101
+
+
+5675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+5676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+5678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+5682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+5685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+5686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call I2C Master complete process */
+5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITMasterCplt(hi2c, ITFlags);
+5689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+5691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Nothing to do */
+5693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process Unlocked */
+5696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+5697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+5700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+5702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+5703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+5704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+5705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITSources Interrupt sources enabled.
+5707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+5708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+5709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+5710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                            uint32_t ITSources)
+5711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+5712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t treatdmanack = 0U;
+5714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate;
+5715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process locked */
+5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_LOCK(hi2c);
+5718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check if STOPF is set */
+5720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+5721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+5722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call I2C Slave complete process */
+5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITSlaveCplt(hi2c, ITFlags);
+5725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+5727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+5728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check that I2C transfer finished */
+5730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+5731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Mean XferCount == 0 */
+ARM GAS  /tmp/ccVyGVF6.s 			page 102
+
+
+5732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* So clear Flag NACKF only */
+5733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+5734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+5735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Split check of hdmarx, for MISRA compliance */
+5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->hdmarx != NULL)
+5738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+5740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
+5742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+5743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             treatdmanack = 1U;
+5744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+5745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Split check of hdmatx, for MISRA compliance  */
+5749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (hi2c->hdmatx != NULL)
+5750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+5752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
+5754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+5755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             treatdmanack = 1U;
+5756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+5757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (treatdmanack == 1U)
+5761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+5763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+5764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****              Warning[Pa134]: left and right operands are identical */
+5765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Call I2C Listen complete process */
+5767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_ITListenCplt(hi2c, ITFlags);
+5768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAM
+5770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Clear NACK Flag */
+5772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Flush TX register */
+5775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_Flush_TXDR(hi2c);
+5776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Last Byte is Transmitted */
+5778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Call I2C Slave Sequential complete process */
+5779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_ITSlaveSeqCplt(hi2c);
+5780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         else
+5782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Clear NACK Flag */
+5784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+5788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ARM GAS  /tmp/ccVyGVF6.s 			page 103
+
+
+5789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+5790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Clear NACK Flag */
+5791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Set ErrorCode corresponding to a Non-Acknowledge */
+5794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+5795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+5797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         tmpstate = hi2c->State;
+5798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+5800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+5802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+5803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+5804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+5805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN
+5806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+5808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+5809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           else
+5810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+5811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Do nothing */
+5812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+5813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Call the corresponding callback to inform upper layer of End of Transfer */
+5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_ITError(hi2c, hi2c->ErrorCode);
+5816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+5817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+5818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+5820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Only Clear NACK Flag, no DMA treatment is pending */
+5822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+5823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
+5826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+5827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITAddrCplt(hi2c, ITFlags);
+5829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+5831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Nothing to do */
+5833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process Unlocked */
+5836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+5837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+5839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+5840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+5842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Master sends target device address followed by internal memory address for write reques
+5843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+5844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+5845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+ARM GAS  /tmp/ccVyGVF6.s 			page 104
+
+
+5846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+5847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+5848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+5849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+5850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+5851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+5852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+5853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+5854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                 uint16_t MemAddress, uint16_t MemAddSize, uint32_t 
+5855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                 uint32_t Tickstart)
+5856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+5857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI
+5858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Wait until TXIS flag is set */
+5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+5861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+5863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* If Memory address size is 8Bit */
+5866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+5867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Memory Address */
+5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+5870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* If Memory address size is 16Bit */
+5872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+5873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send MSB of Memory Address */
+5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+5876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until TXIS flag is set */
+5878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+5879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+5881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send LSB of Memory Address */
+5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+5885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Wait until TCR flag is set */
+5888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+5889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+5891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+5894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+5895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+5897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Master sends target device address followed by internal memory address for read request
+5898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+5899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+5900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Target device address: The device 7 bits address value
+5901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *         in datasheet must be shifted to the left before calling the interface
+5902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddress Internal memory address
+ARM GAS  /tmp/ccVyGVF6.s 			page 105
+
+
+5903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  MemAddSize Size of internal memory address
+5904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+5905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+5906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+5907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+5908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+5909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t T
+5910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                uint32_t Tickstart)
+5911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR
+5913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Wait until TXIS flag is set */
+5915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+5916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+5918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* If Memory address size is 8Bit */
+5921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+5922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send Memory Address */
+5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+5925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* If Memory address size is 16Bit */
+5927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+5928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send MSB of Memory Address */
+5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+5931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until TXIS flag is set */
+5933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+5934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+5936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+5937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Send LSB of Memory Address */
+5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+5940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Wait until TC flag is set */
+5943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+5944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     return HAL_ERROR;
+5946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+5947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+5949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+5950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+5952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  I2C Address complete process callback.
+5953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+5954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+5955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+5956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+5957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+5958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+5959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint8_t transferdirection;
+ARM GAS  /tmp/ccVyGVF6.s 			page 106
+
+
+5960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t slaveaddrcode;
+5961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t ownadd1code;
+5962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t ownadd2code;
+5963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+5965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(ITFlags);
+5966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* In case of Listen state, need to inform upper layer of address match code event */
+5968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+5969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+5970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     transferdirection = I2C_GET_DIR(hi2c);
+5971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+5972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+5973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+5974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If 10bits addressing mode is selected */
+5976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+5977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+5978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
+5979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+5980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         slaveaddrcode = ownadd1code;
+5981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->AddrEventCount++;
+5982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->AddrEventCount == 2U)
+5983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+5984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Reset Address Event counter */
+5985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->AddrEventCount = 0U;
+5986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Clear ADDR flag */
+5988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+5989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Process Unlocked */
+5991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           __HAL_UNLOCK(hi2c);
+5992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+5993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Call Slave Addr callback */
+5994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+5995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+5996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+5997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+5998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+5999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+6000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+6001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+6002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+6003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         slaveaddrcode = ownadd2code;
+6004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Disable ADDR Interrupts */
+6006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+6007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+6009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+6010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call Slave Addr callback */
+6012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+6014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+6016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ARM GAS  /tmp/ccVyGVF6.s 			page 107
+
+
+6017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+6018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* else 7 bits addressing mode is selected */
+6020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+6021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable ADDR Interrupts */
+6023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+6024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+6026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+6027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call Slave Addr callback */
+6029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+6031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+6033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Else clear address flag only */
+6037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear ADDR flag */
+6040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+6041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+6043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  I2C Master sequential complete process.
+6049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
+6053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Reset I2C handle mode */
+6055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+6056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* No Generate Stop, to permit restart mode */
+6058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+6059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+6060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State         = HAL_I2C_STATE_READY;
+6062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+6063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+6064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupts */
+6066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+6067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+6069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->MasterTxCpltCallback(hi2c);
+ARM GAS  /tmp/ccVyGVF6.s 			page 108
+
+
+6074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     HAL_I2C_MasterTxCpltCallback(hi2c);
+6076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+6079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State         = HAL_I2C_STATE_READY;
+6082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+6083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+6084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupts */
+6086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+6087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+6089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->MasterRxCpltCallback(hi2c);
+6094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     HAL_I2C_MasterRxCpltCallback(hi2c);
+6096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  I2C Slave sequential complete process.
+6102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+6106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+6108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Reset I2C handle mode */
+6110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+6111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* If a DMA is ongoing, Update handle size context */
+6113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+6114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable DMA Request */
+6116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+6117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+6119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable DMA Request */
+6121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+6122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Do nothing */
+6126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+6129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+ARM GAS  /tmp/ccVyGVF6.s 			page 109
+
+
+6131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State         = HAL_I2C_STATE_LISTEN;
+6132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+6133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupts */
+6135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+6136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+6138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->SlaveTxCpltCallback(hi2c);
+6143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     HAL_I2C_SlaveTxCpltCallback(hi2c);
+6145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+6149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+6151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State         = HAL_I2C_STATE_LISTEN;
+6152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+6153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Interrupts */
+6155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+6156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+6158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->SlaveRxCpltCallback(hi2c);
+6163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     HAL_I2C_SlaveRxCpltCallback(hi2c);
+6165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Nothing to do */
+6170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  I2C Master complete process.
+6175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+6177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+6180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmperror;
+6182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+6183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __IO uint32_t tmpreg;
+6184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Clear STOP Flag */
+6186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+6187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 110
+
+
+6188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable Interrupts and Store Previous state */
+6189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+6190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+6192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+6193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+6195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+6197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+6198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Do nothing */
+6202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Clear Configuration Register 2 */
+6205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_RESET_CR2(hi2c);
+6206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Reset handle parameters */
+6208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferISR       = NULL;
+6209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+6210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
+6212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear NACK Flag */
+6214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+6215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set acknowledge error code */
+6217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+6218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Fetch Last receive data if any */
+6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+6222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Read data from RXDR */
+6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmpreg = (uint8_t)hi2c->Instance->RXDR;
+6225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     UNUSED(tmpreg);
+6226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Flush TX register */
+6229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_Flush_TXDR(hi2c);
+6230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Store current volatile hi2c->ErrorCode, misra rule */
+6232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   tmperror = hi2c->ErrorCode;
+6233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Call the corresponding callback to inform upper layer of End of Transfer */
+6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
+6236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITError(hi2c, hi2c->ErrorCode);
+6239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+6241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+6242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+6244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ARM GAS  /tmp/ccVyGVF6.s 			page 111
+
+
+6245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->Mode == HAL_I2C_MODE_MEM)
+6247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode = HAL_I2C_MODE_NONE;
+6249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+6251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+6252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+6254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->MemTxCpltCallback(hi2c);
+6256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       HAL_I2C_MemTxCpltCallback(hi2c);
+6258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+6261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode = HAL_I2C_MODE_NONE;
+6263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+6265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+6266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+6268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->MasterTxCpltCallback(hi2c);
+6270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       HAL_I2C_MasterTxCpltCallback(hi2c);
+6272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+6276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+6277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+6279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+6280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->Mode == HAL_I2C_MODE_MEM)
+6282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode = HAL_I2C_MODE_NONE;
+6284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+6286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+6287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+6289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->MemRxCpltCallback(hi2c);
+6291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       HAL_I2C_MemRxCpltCallback(hi2c);
+6293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+6296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode = HAL_I2C_MODE_NONE;
+6298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+6300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+6301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 112
+
+
+6302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+6303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->MasterRxCpltCallback(hi2c);
+6305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       HAL_I2C_MasterRxCpltCallback(hi2c);
+6307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Nothing to do */
+6313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  I2C Slave complete process.
+6318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+6320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+6323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+6325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+6326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+6327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+6328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Clear STOP Flag */
+6330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+6331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable Interrupts and Store Previous state */
+6333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+6334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+6336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+6337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+6339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+6341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+6342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (tmpstate == HAL_I2C_STATE_LISTEN)
+6344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+6346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+6347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Do nothing */
+6351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable Address Acknowledge */
+6354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Instance->CR2 |= I2C_CR2_NACK;
+6355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Clear Configuration Register 2 */
+6357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_RESET_CR2(hi2c);
+6358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 113
+
+
+6359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Flush TX register */
+6360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_Flush_TXDR(hi2c);
+6361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* If a DMA is ongoing, Update handle size context */
+6363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+6364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable DMA Request */
+6366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+6367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->hdmatx != NULL)
+6369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
+6371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+6374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable DMA Request */
+6376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+6377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->hdmarx != NULL)
+6379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
+6381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Do nothing */
+6386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Store Last receive data if any */
+6389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+6390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Remove RXNE flag on temporary variable as read done */
+6392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmpITFlags &= ~I2C_FLAG_RXNE;
+6393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Read data from RXDR */
+6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+6396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Increment Buffer pointer */
+6398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr++;
+6399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->XferSize > 0U))
+6401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+6403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+6404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* All data are not transferred, so set error code accordingly */
+6408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->XferCount != 0U)
+6409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set ErrorCode corresponding to a Non-Acknowledge */
+6411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+6412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+6415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
+ARM GAS  /tmp/ccVyGVF6.s 			page 114
+
+
+6416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check that I2C transfer finished */
+6418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+6419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Mean XferCount == 0*/
+6420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* So clear Flag NACKF only */
+6421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount == 0U)
+6422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+6424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+6425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            Warning[Pa134]: left and right operands are identical */
+6426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+6427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call I2C Listen complete process */
+6428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_ITListenCplt(hi2c, tmpITFlags);
+6429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)
+6431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+6432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Clear NACK Flag */
+6433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+6434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Flush TX register */
+6436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_Flush_TXDR(hi2c);
+6437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Last Byte is Transmitted */
+6439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call I2C Slave Sequential complete process */
+6440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_ITSlaveSeqCplt(hi2c);
+6441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+6442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+6443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+6444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Clear NACK Flag */
+6445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+6446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+6447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+6449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+6451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Clear NACK Flag */
+6452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+6453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set ErrorCode corresponding to a Non-Acknowledge */
+6455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+6456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+6458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+6459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call the corresponding callback to inform upper layer of End of Transfer */
+6460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_ITError(hi2c, hi2c->ErrorCode);
+6461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+6462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+6466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+6467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+6469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITError(hi2c, hi2c->ErrorCode);
+6472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 115
+
+
+6473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+6474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->State == HAL_I2C_STATE_LISTEN)
+6475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call I2C Listen complete process */
+6477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ITListenCplt(hi2c, tmpITFlags);
+6478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+6481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
+6483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITSlaveSeqCplt(hi2c);
+6484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+6486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+6487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+6488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+6490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+6493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ListenCpltCallback(hi2c);
+6495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     HAL_I2C_ListenCpltCallback(hi2c);
+6497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Call the corresponding callback to inform upper layer of End of Transfer */
+6500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+6501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+6503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+6504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+6506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->SlaveRxCpltCallback(hi2c);
+6511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     HAL_I2C_SlaveRxCpltCallback(hi2c);
+6513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+6518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+6519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+6521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->SlaveTxCpltCallback(hi2c);
+6526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     HAL_I2C_SlaveTxCpltCallback(hi2c);
+6528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccVyGVF6.s 			page 116
+
+
+6530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  I2C Listen complete process.
+6534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ITFlags Interrupt flags to handle.
+6536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+6539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Reset handle parameters */
+6541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+6542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+6543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+6545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+6546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Store Last receive data if any */
+6548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+6549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Read data from RXDR */
+6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+6552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Increment Buffer pointer */
+6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr++;
+6555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->XferSize > 0U))
+6557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+6559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+6560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set ErrorCode corresponding to a Non-Acknowledge */
+6562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+6563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable all Interrupts*/
+6567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+6568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Clear NACK Flag */
+6570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+6571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Process Unlocked */
+6573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_UNLOCK(hi2c);
+6574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+6576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->ListenCpltCallback(hi2c);
+6578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_ListenCpltCallback(hi2c);
+6580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  I2C interrupts error process.
+6585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  ErrorCode Error code to handle.
+ARM GAS  /tmp/ccVyGVF6.s 			page 117
+
+
+6587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+6590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+6592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmppreviousstate;
+6594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Reset handle parameters */
+6596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode          = HAL_I2C_MODE_NONE;
+6597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+6598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferCount     = 0U;
+6599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Set new error code */
+6601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->ErrorCode |= ErrorCode;
+6602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable Interrupts */
+6604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
+6605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+6606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+6607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable all interrupts, except interrupts related to LISTEN state */
+6609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+6610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* keep HAL_I2C_STATE_LISTEN if set */
+6612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State         = HAL_I2C_STATE_LISTEN;
+6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR       = I2C_Slave_ISR_IT;
+6614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable all interrupts */
+6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+6619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Flush TX register */
+6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Flush_TXDR(hi2c);
+6622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* If state is an abort treatment on going, don't change state */
+6624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* This change will be do later */
+6625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->State != HAL_I2C_STATE_ABORT)
+6626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set HAL_I2C_STATE_READY */
+6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->State         = HAL_I2C_STATE_READY;
+6629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Check if a STOPF is detected */
+6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+6632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+6634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+6635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+6636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+6637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+6638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Clear STOP Flag */
+6640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+6641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+6642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ARM GAS  /tmp/ccVyGVF6.s 			page 118
+
+
+6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+6645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Abort DMA TX transfer if any */
+6648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   tmppreviousstate = hi2c->PreviousState;
+6649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+6651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+6652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+6654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+6656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+6659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the I2C DMA Abort callback :
+6661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+6662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+6663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+6666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Abort DMA TX */
+6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+6669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+6670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call Directly XferAbortCallback function in case of error */
+6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+6672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+6673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+6675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TreatErrorCallback(hi2c);
+6677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Abort DMA RX transfer if any */
+6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
+6681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+6682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+6684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+6686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+6689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Set the I2C DMA Abort callback :
+6691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+6693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Process Unlocked */
+6695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_UNLOCK(hi2c);
+6696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Abort DMA RX */
+6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+6699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+6700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+ARM GAS  /tmp/ccVyGVF6.s 			page 119
+
+
+6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+6702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+6703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+6705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TreatErrorCallback(hi2c);
+6707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_TreatErrorCallback(hi2c);
+6712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  I2C Error callback treatment.
+6717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+6721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_ABORT)
+6723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+6725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+6726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->AbortCpltCallback(hi2c);
+6733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     HAL_I2C_AbortCpltCallback(hi2c);
+6735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+6740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+6743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+6746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCallback(hi2c);
+6747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else
+6748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     HAL_I2C_ErrorCallback(hi2c);
+6749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+6750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  I2C Tx data register flush process.
+6755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+6756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ARM GAS  /tmp/ccVyGVF6.s 			page 120
+
+
+6758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+6759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+  28              		.loc 1 6759 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+6760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* If a pending TXIS flag is set */
+6761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Write a dummy data in TXDR to clear it */
+6762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+  33              		.loc 1 6762 3 view .LVU1
+  34              		.loc 1 6762 7 is_stmt 0 view .LVU2
+  35 0000 0368     		ldr	r3, [r0]
+  36 0002 9A69     		ldr	r2, [r3, #24]
+  37              		.loc 1 6762 6 view .LVU3
+  38 0004 12F0020F 		tst	r2, #2
+  39 0008 01D0     		beq	.L2
+6763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->TXDR = 0x00U;
+  40              		.loc 1 6764 5 is_stmt 1 view .LVU4
+  41              		.loc 1 6764 26 is_stmt 0 view .LVU5
+  42 000a 0022     		movs	r2, #0
+  43 000c 9A62     		str	r2, [r3, #40]
+  44              	.L2:
+6765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Flush TX register if not empty */
+6768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  45              		.loc 1 6768 3 is_stmt 1 view .LVU6
+  46              		.loc 1 6768 7 is_stmt 0 view .LVU7
+  47 000e 0368     		ldr	r3, [r0]
+  48 0010 9A69     		ldr	r2, [r3, #24]
+  49              		.loc 1 6768 6 view .LVU8
+  50 0012 12F0010F 		tst	r2, #1
+  51 0016 03D1     		bne	.L1
+6769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+  52              		.loc 1 6770 5 is_stmt 1 view .LVU9
+  53 0018 9A69     		ldr	r2, [r3, #24]
+  54 001a 42F00102 		orr	r2, r2, #1
+  55 001e 9A61     		str	r2, [r3, #24]
+  56              	.L1:
+6771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+  57              		.loc 1 6772 1 is_stmt 0 view .LVU10
+  58 0020 7047     		bx	lr
+  59              		.cfi_endproc
+  60              	.LFE206:
+  62              		.section	.text.I2C_TransferConfig,"ax",%progbits
+  63              		.align	1
+  64              		.syntax unified
+  65              		.thumb
+  66              		.thumb_func
+  67              		.fpu fpv5-d16
+  69              	I2C_TransferConfig:
+  70              	.LVL1:
+  71              	.LFB218:
+ARM GAS  /tmp/ccVyGVF6.s 			page 121
+
+
+6773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  DMA I2C master transmit process complete callback.
+6776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hdma DMA handle
+6777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+6780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable DMA Request */
+6785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+6786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* If last transfer, enable STOP interrupt */
+6788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->XferCount == 0U)
+6789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable STOP interrupt */
+6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+6792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* else prepare a new DMA transfer and enable TCReload interrupt */
+6794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Update Buffer pointer */
+6797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr += hi2c->XferSize;
+6798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set the XferSize to transfer */
+6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+6801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = MAX_NBYTE_SIZE;
+6803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+6805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+6807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable the DMA stream */
+6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+6811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+6812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+6814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+6815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+6817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable TC interrupts */
+6819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+6820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  DMA I2C slave transmit process complete callback.
+6827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hdma DMA handle
+6828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+ARM GAS  /tmp/ccVyGVF6.s 			page 122
+
+
+6830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+6831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+6835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+6837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable DMA Request */
+6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+6840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Last Byte is Transmitted */
+6842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call I2C Slave Sequential complete process */
+6843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITSlaveSeqCplt(hi2c);
+6844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* No specific action, Master fully manage the generation of STOP condition */
+6848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Mean that this generation can arrive at any time, at the end or during DMA process */
+6849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* So STOP condition should be manage through Interrupt treatment */
+6850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief DMA I2C master receive process complete callback.
+6856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hdma DMA handle
+6857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+6860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable DMA Request */
+6865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+6866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* If last transfer, enable STOP interrupt */
+6868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->XferCount == 0U)
+6869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable STOP interrupt */
+6871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+6872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* else prepare a new DMA transfer and enable TCReload interrupt */
+6874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Update Buffer pointer */
+6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr += hi2c->XferSize;
+6878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Set the XferSize to transfer */
+6880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (hi2c->XferCount > MAX_NBYTE_SIZE)
+6881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Errata workaround 170323 */
+6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+6884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+6885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferSize = 1U;
+6886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ARM GAS  /tmp/ccVyGVF6.s 			page 123
+
+
+6887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+6888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+6889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->XferSize = MAX_NBYTE_SIZE;
+6890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+6891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+6893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize = hi2c->XferCount;
+6895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable the DMA stream */
+6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
+6899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+6900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Call the corresponding callback to inform upper layer of End of Transfer */
+6902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+6903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     else
+6905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable TC interrupts */
+6907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+6908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  DMA I2C slave receive process complete callback.
+6915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hdma DMA handle
+6916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+6919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+6923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
+6925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (tmpoptions != I2C_NO_OPTION_FRAME))
+6926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable DMA Request */
+6928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+6929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call I2C Slave Sequential complete process */
+6931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITSlaveSeqCplt(hi2c);
+6932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+6934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* No specific action, Master fully manage the generation of STOP condition */
+6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Mean that this generation can arrive at any time, at the end or during DMA process */
+6937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* So STOP condition should be manage through Interrupt treatment */
+6938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  DMA I2C communication error callback.
+ARM GAS  /tmp/ccVyGVF6.s 			page 124
+
+
+6944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param hdma DMA handle
+6945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+6948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t treatdmaerror = 0U;
+6950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->hdmatx != NULL)
+6954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
+6956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       treatdmaerror = 1U;
+6958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->hdmarx != NULL)
+6962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
+6964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+6965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       treatdmaerror = 1U;
+6966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+6967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform *
+6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
+6971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable Acknowledge */
+6973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Instance->CR2 |= I2C_CR2_NACK;
+6974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Call the corresponding callback to inform upper layer of End of Transfer */
+6976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+6977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+6979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+6982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief DMA I2C communication abort callback
+6983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *        (To be called at end of DMA Abort procedure).
+6984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param hdma DMA handle.
+6985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+6986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+6987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+6988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+6989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+6990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+6991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+6992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Reset AbortCpltCallback */
+6993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->hdmatx != NULL)
+6994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->hdmatx->XferAbortCallback = NULL;
+6996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+6997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->hdmarx != NULL)
+6998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+6999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->hdmarx->XferAbortCallback = NULL;
+7000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccVyGVF6.s 			page 125
+
+
+7001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_TreatErrorCallback(hi2c);
+7003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+7004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+7007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  This function handles I2C Communication Timeout. It waits
+7008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                until a flag is no longer in the specified status.
+7009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+7010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+7011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Flag Specifies the I2C flag to check.
+7012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Status The actual Flag status (SET or RESET).
+7013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+7014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+7015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+7016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+7017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta
+7018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                     uint32_t Timeout, uint32_t Tickstart)
+7019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+7021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check if an error is detected */
+7023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+7024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+7026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check for the Timeout */
+7029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (Timeout != HAL_MAX_DELAY)
+7030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+7032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+7033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
+7034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+7035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+7036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->State = HAL_I2C_STATE_READY;
+7037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->Mode = HAL_I2C_MODE_NONE;
+7038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Process Unlocked */
+7040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           __HAL_UNLOCK(hi2c);
+7041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           return HAL_ERROR;
+7042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+7043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+7044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+7047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+7048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+7050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
+7051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+7052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+7053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+7054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+7055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+7056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+7057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ARM GAS  /tmp/ccVyGVF6.s 			page 126
+
+
+7058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                         uint32_t Tickstart)
+7059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+7061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check if an error is detected */
+7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+7064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+7066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check for the Timeout */
+7069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (Timeout != HAL_MAX_DELAY)
+7070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+7072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+7073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
+7074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+7075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+7076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->State = HAL_I2C_STATE_READY;
+7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->Mode = HAL_I2C_MODE_NONE;
+7078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Process Unlocked */
+7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           __HAL_UNLOCK(hi2c);
+7081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           return HAL_ERROR;
+7083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+7084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+7085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+7088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+7089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+7091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+7092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+7093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+7094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+7095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+7096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+7097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+7098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+7099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                         uint32_t Tickstart)
+7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+7102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check if an error is detected */
+7104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+7105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+7107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check for the Timeout */
+7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+7111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
+7113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+7114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ARM GAS  /tmp/ccVyGVF6.s 			page 127
+
+
+7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+7116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+7117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+7120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+7122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+7123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return HAL_OK;
+7126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+7127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+7129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+7130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+7131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+7132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+7133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+7134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+7135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+7136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+7137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                                         uint32_t Tickstart)
+7138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+7139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+7140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
+7142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check if an error is detected */
+7144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+7145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       status = HAL_ERROR;
+7147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check if a STOPF is detected */
+7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
+7151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Check if an RXNE is pending */
+7153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Store Last receive data if any */
+7154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+7155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+7156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Return HAL_OK */
+7157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* The Reading of data from RXDR will be done in caller function */
+7158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         status = HAL_OK;
+7159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+7160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Check a no-acknowledge have been detected */
+7162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+7163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+7164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+7165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+7166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Clear STOP Flag */
+7168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+7169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Clear Configuration Register 2 */
+7171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_RESET_CR2(hi2c);
+ARM GAS  /tmp/ccVyGVF6.s 			page 128
+
+
+7172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+7174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+7175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+7177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+7178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         status = HAL_ERROR;
+7180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+7181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       else
+7182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+7183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+7184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+7185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Check for the Timeout */
+7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
+7189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
+7191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+7192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+7193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+7194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Process Unlocked */
+7196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         __HAL_UNLOCK(hi2c);
+7197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         status = HAL_ERROR;
+7199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+7200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return status;
+7203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+7204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+7206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  This function handles errors detection during an I2C Communication.
+7207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+7208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+7209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Timeout Timeout duration
+7210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Tickstart Tick start value
+7211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval HAL status
+7212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+7213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Ti
+7214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+7215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+7216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itflag   = hi2c->Instance->ISR;
+7217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t error_code = 0;
+7218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart = Tickstart;
+7219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmp1;
+7220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_ModeTypeDef tmp2;
+7221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
+7223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear NACKF Flag */
+7225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+7226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Wait until STOP Flag is set or timeout occurred */
+7228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* AutoEnd should be initiate after AF */
+ARM GAS  /tmp/ccVyGVF6.s 			page 129
+
+
+7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
+7230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Check for the Timeout */
+7232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if (Timeout != HAL_MAX_DELAY)
+7233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+7235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
+7237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           tmp2 = hi2c->Mode;
+7238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* In case of I2C still busy, try to regenerate a STOP manually */
+7240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
+7241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               (tmp1 != I2C_CR2_STOP) && \
+7242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               (tmp2 != HAL_I2C_MODE_SLAVE))
+7243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+7244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Generate Stop */
+7245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             hi2c->Instance->CR2 |= I2C_CR2_STOP;
+7246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Update Tick with new reference */
+7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             tickstart = HAL_GetTick();
+7249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+7250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+7252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+7253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             /* Check for the Timeout */
+7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
+7255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             {
+7256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               error_code |= HAL_I2C_ERROR_TIMEOUT;
+7257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               status = HAL_ERROR;
+7259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               break;
+7261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             }
+7262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+7263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+7264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+7265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* In case STOP Flag is detected, clear it */
+7268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (status == HAL_OK)
+7269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Clear STOP Flag */
+7271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+7272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     error_code |= HAL_I2C_ERROR_AF;
+7275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     status = HAL_ERROR;
+7277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Refresh Content of Status register */
+7280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   itflag = hi2c->Instance->ISR;
+7281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Then verify if an additional errors occurs */
+7283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check if a Bus error occurred */
+7284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
+7285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccVyGVF6.s 			page 130
+
+
+7286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     error_code |= HAL_I2C_ERROR_BERR;
+7287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear BERR flag */
+7289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+7290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     status = HAL_ERROR;
+7292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check if an Over-Run/Under-Run error occurred */
+7295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
+7296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     error_code |= HAL_I2C_ERROR_OVR;
+7298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear OVR flag */
+7300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+7301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     status = HAL_ERROR;
+7303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check if an Arbitration Loss error occurred */
+7306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
+7307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     error_code |= HAL_I2C_ERROR_ARLO;
+7309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear ARLO flag */
+7311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+7312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     status = HAL_ERROR;
+7314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (status != HAL_OK)
+7317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Flush TX register */
+7319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_Flush_TXDR(hi2c);
+7320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Clear Configuration Register 2 */
+7322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     I2C_RESET_CR2(hi2c);
+7323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode |= error_code;
+7325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+7326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+7327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Process Unlocked */
+7329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     __HAL_UNLOCK(hi2c);
+7330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return status;
+7333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+7334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+7336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag ar
+7337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+7338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  DevAddress Specifies the slave address to be programmed.
+7339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Size Specifies the number of bytes to be programmed.
+7340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *   This parameter must be a value between 0 and 255.
+7341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Mode New state of the I2C START condition generation.
+7342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *   This parameter can be one of the following values:
+ARM GAS  /tmp/ccVyGVF6.s 			page 131
+
+
+7343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+7344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+7345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+7346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  Request New state of the I2C START condition generation.
+7347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *   This parameter can be one of the following values:
+7348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+7349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+7350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+7351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+7352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+7353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+7354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t
+7355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                uint32_t Request)
+7356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+  72              		.loc 1 7356 1 is_stmt 1 view -0
+  73              		.cfi_startproc
+  74              		@ args = 4, pretend = 0, frame = 0
+  75              		@ frame_needed = 0, uses_anonymous_args = 0
+  76              		@ link register save eliminated.
+  77              		.loc 1 7356 1 is_stmt 0 view .LVU12
+  78 0000 10B4     		push	{r4}
+  79              	.LCFI0:
+  80              		.cfi_def_cfa_offset 4
+  81              		.cfi_offset 4, -4
+  82 0002 019C     		ldr	r4, [sp, #4]
+7357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+7358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  83              		.loc 1 7358 3 is_stmt 1 view .LVU13
+7359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_TRANSFER_MODE(Mode));
+  84              		.loc 1 7359 3 view .LVU14
+7360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_TRANSFER_REQUEST(Request));
+  85              		.loc 1 7360 3 view .LVU15
+7361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+7363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+  86              		.loc 1 7363 3 view .LVU16
+  87              		.loc 1 7363 52 is_stmt 0 view .LVU17
+  88 0004 C1F30901 		ubfx	r1, r1, #0, #10
+  89              	.LVL2:
+  90              		.loc 1 7363 68 view .LVU18
+  91 0008 41EA0241 		orr	r1, r1, r2, lsl #16
+7364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+  92              		.loc 1 7364 88 view .LVU19
+  93 000c 1943     		orrs	r1, r1, r3
+7363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+  94              		.loc 1 7363 19 view .LVU20
+  95 000e 2143     		orrs	r1, r1, r4
+7363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+  96              		.loc 1 7363 12 view .LVU21
+  97 0010 21F00041 		bic	r1, r1, #-2147483648
+  98              	.LVL3:
+7365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+7366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* update CR2 register */
+7368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   MODIFY_REG(hi2c->Instance->CR2, \
+  99              		.loc 1 7368 3 is_stmt 1 view .LVU22
+ 100 0014 0268     		ldr	r2, [r0]
+ARM GAS  /tmp/ccVyGVF6.s 			page 132
+
+
+ 101              	.LVL4:
+ 102              		.loc 1 7368 3 is_stmt 0 view .LVU23
+ 103 0016 5368     		ldr	r3, [r2, #4]
+ 104              	.LVL5:
+ 105              		.loc 1 7368 3 view .LVU24
+ 106 0018 640D     		lsrs	r4, r4, #21
+ 107 001a 04F48064 		and	r4, r4, #1024
+ 108 001e 44F07F74 		orr	r4, r4, #66846720
+ 109 0022 44F45834 		orr	r4, r4, #221184
+ 110 0026 44F47F74 		orr	r4, r4, #1020
+ 111 002a 44F00304 		orr	r4, r4, #3
+ 112 002e 23EA0404 		bic	r4, r3, r4
+ 113 0032 2143     		orrs	r1, r1, r4
+ 114              	.LVL6:
+ 115              		.loc 1 7368 3 view .LVU25
+ 116 0034 5160     		str	r1, [r2, #4]
+7369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****              ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+7370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
+7371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                I2C_CR2_START | I2C_CR2_STOP)), tmp);
+7372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 117              		.loc 1 7372 1 view .LVU26
+ 118 0036 5DF8044B 		ldr	r4, [sp], #4
+ 119              	.LCFI1:
+ 120              		.cfi_restore 4
+ 121              		.cfi_def_cfa_offset 0
+ 122              	.LVL7:
+ 123              		.loc 1 7372 1 view .LVU27
+ 124 003a 7047     		bx	lr
+ 125              		.cfi_endproc
+ 126              	.LFE218:
+ 128              		.section	.text.I2C_Enable_IRQ,"ax",%progbits
+ 129              		.align	1
+ 130              		.syntax unified
+ 131              		.thumb
+ 132              		.thumb_func
+ 133              		.fpu fpv5-d16
+ 135              	I2C_Enable_IRQ:
+ 136              	.LVL8:
+ 137              	.LFB219:
+7373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+7375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Manage the enabling of Interrupts.
+7376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+7377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+7378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+7379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+7380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+7381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+7382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+ 138              		.loc 1 7382 1 is_stmt 1 view -0
+ 139              		.cfi_startproc
+ 140              		@ args = 0, pretend = 0, frame = 0
+ 141              		@ frame_needed = 0, uses_anonymous_args = 0
+ 142              		@ link register save eliminated.
+7383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpisr = 0U;
+ 143              		.loc 1 7383 3 view .LVU29
+7384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 133
+
+
+7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
+ 144              		.loc 1 7385 3 view .LVU30
+ 145              		.loc 1 7385 12 is_stmt 0 view .LVU31
+ 146 0000 436B     		ldr	r3, [r0, #52]
+ 147              		.loc 1 7385 6 view .LVU32
+ 148 0002 234A     		ldr	r2, .L24
+ 149 0004 9342     		cmp	r3, r2
+ 150 0006 1FD0     		beq	.L7
+ 151              		.loc 1 7385 45 discriminator 1 view .LVU33
+ 152 0008 224A     		ldr	r2, .L24+4
+ 153 000a 9342     		cmp	r3, r2
+ 154 000c 1CD0     		beq	.L7
+7386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
+ 155              		.loc 1 7386 44 view .LVU34
+ 156 000e 224A     		ldr	r2, .L24+8
+ 157 0010 9342     		cmp	r3, r2
+ 158 0012 19D0     		beq	.L7
+7387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (hi2c->XferISR != I2C_Mem_ISR_DMA))
+7388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ 159              		.loc 1 7389 5 is_stmt 1 view .LVU35
+ 160              		.loc 1 7389 8 is_stmt 0 view .LVU36
+ 161 0014 11F4004F 		tst	r1, #32768
+ 162 0018 11D1     		bne	.L18
+7383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 163              		.loc 1 7383 12 view .LVU37
+ 164 001a 0023     		movs	r3, #0
+ 165              	.L8:
+ 166              	.LVL9:
+7390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, STOP, NACK and ADDR interrupts */
+7392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+7393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ 167              		.loc 1 7395 5 is_stmt 1 view .LVU38
+ 168              		.loc 1 7395 8 is_stmt 0 view .LVU39
+ 169 001c 11F0010F 		tst	r1, #1
+ 170 0020 01D0     		beq	.L9
+7396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+7398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ 171              		.loc 1 7398 7 is_stmt 1 view .LVU40
+ 172              		.loc 1 7398 14 is_stmt 0 view .LVU41
+ 173 0022 43F0F203 		orr	r3, r3, #242
+ 174              	.LVL10:
+ 175              	.L9:
+7399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ 176              		.loc 1 7401 5 is_stmt 1 view .LVU42
+ 177              		.loc 1 7401 8 is_stmt 0 view .LVU43
+ 178 0026 11F0020F 		tst	r1, #2
+ 179 002a 01D0     		beq	.L10
+7402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+7404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ARM GAS  /tmp/ccVyGVF6.s 			page 134
+
+
+ 180              		.loc 1 7404 7 is_stmt 1 view .LVU44
+ 181              		.loc 1 7404 14 is_stmt 0 view .LVU45
+ 182 002c 43F0F403 		orr	r3, r3, #244
+ 183              	.LVL11:
+ 184              	.L10:
+7405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (InterruptRequest == I2C_XFER_ERROR_IT)
+ 185              		.loc 1 7407 5 is_stmt 1 view .LVU46
+ 186              		.loc 1 7407 8 is_stmt 0 view .LVU47
+ 187 0030 1029     		cmp	r1, #16
+ 188 0032 06D0     		beq	.L20
+ 189              	.L11:
+7408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR and NACK interrupts */
+7410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+7411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (InterruptRequest == I2C_XFER_CPLT_IT)
+ 190              		.loc 1 7413 5 is_stmt 1 view .LVU48
+ 191              		.loc 1 7413 8 is_stmt 0 view .LVU49
+ 192 0034 2029     		cmp	r1, #32
+ 193 0036 1BD1     		bne	.L12
+7414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable STOP interrupts */
+7416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_STOPI;
+ 194              		.loc 1 7416 7 is_stmt 1 view .LVU50
+ 195              		.loc 1 7416 14 is_stmt 0 view .LVU51
+ 196 0038 43F02003 		orr	r3, r3, #32
+ 197              	.LVL12:
+ 198              		.loc 1 7416 14 view .LVU52
+ 199 003c 18E0     		b	.L12
+ 200              	.LVL13:
+ 201              	.L18:
+7392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 202              		.loc 1 7392 14 view .LVU53
+ 203 003e B823     		movs	r3, #184
+ 204 0040 ECE7     		b	.L8
+ 205              	.LVL14:
+ 206              	.L20:
+7410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 207              		.loc 1 7410 7 is_stmt 1 view .LVU54
+7410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 208              		.loc 1 7410 14 is_stmt 0 view .LVU55
+ 209 0042 43F09003 		orr	r3, r3, #144
+ 210              	.LVL15:
+7410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 211              		.loc 1 7410 14 view .LVU56
+ 212 0046 F5E7     		b	.L11
+ 213              	.LVL16:
+ 214              	.L7:
+7417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+7421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ARM GAS  /tmp/ccVyGVF6.s 			page 135
+
+
+ 215              		.loc 1 7422 5 is_stmt 1 view .LVU57
+ 216              		.loc 1 7422 8 is_stmt 0 view .LVU58
+ 217 0048 11F4004F 		tst	r1, #32768
+ 218 004c 15D1     		bne	.L19
+7383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 219              		.loc 1 7383 12 view .LVU59
+ 220 004e 0023     		movs	r3, #0
+ 221              	.L13:
+ 222              	.LVL17:
+7423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, STOP, NACK and ADDR interrupts */
+7425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+7426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ 223              		.loc 1 7428 5 is_stmt 1 view .LVU60
+ 224              		.loc 1 7428 8 is_stmt 0 view .LVU61
+ 225 0050 11F0010F 		tst	r1, #1
+ 226 0054 01D0     		beq	.L14
+7429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+7431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ 227              		.loc 1 7431 7 is_stmt 1 view .LVU62
+ 228              		.loc 1 7431 14 is_stmt 0 view .LVU63
+ 229 0056 43F0F203 		orr	r3, r3, #242
+ 230              	.LVL18:
+ 231              	.L14:
+7432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ 232              		.loc 1 7434 5 is_stmt 1 view .LVU64
+ 233              		.loc 1 7434 8 is_stmt 0 view .LVU65
+ 234 005a 11F0020F 		tst	r1, #2
+ 235 005e 01D0     		beq	.L15
+7435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+7437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ 236              		.loc 1 7437 7 is_stmt 1 view .LVU66
+ 237              		.loc 1 7437 14 is_stmt 0 view .LVU67
+ 238 0060 43F0F403 		orr	r3, r3, #244
+ 239              	.LVL19:
+ 240              	.L15:
+7438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (InterruptRequest == I2C_XFER_ERROR_IT)
+ 241              		.loc 1 7440 5 is_stmt 1 view .LVU68
+ 242              		.loc 1 7440 8 is_stmt 0 view .LVU69
+ 243 0064 1029     		cmp	r1, #16
+ 244 0066 0AD0     		beq	.L21
+ 245              	.L16:
+7441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable ERR and NACK interrupts */
+7443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+7444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (InterruptRequest == I2C_XFER_CPLT_IT)
+ 246              		.loc 1 7446 5 is_stmt 1 view .LVU70
+ARM GAS  /tmp/ccVyGVF6.s 			page 136
+
+
+ 247              		.loc 1 7446 8 is_stmt 0 view .LVU71
+ 248 0068 2029     		cmp	r1, #32
+ 249 006a 0BD0     		beq	.L22
+ 250              	.L17:
+7447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable STOP interrupts */
+7449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+7450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (InterruptRequest == I2C_XFER_RELOAD_IT)
+ 251              		.loc 1 7452 5 is_stmt 1 view .LVU72
+ 252              		.loc 1 7452 8 is_stmt 0 view .LVU73
+ 253 006c 4029     		cmp	r1, #64
+ 254 006e 0CD0     		beq	.L23
+ 255              	.L12:
+7453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Enable TC interrupts */
+7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_TCI;
+7456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Enable interrupts only at the end */
+7460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* to avoid the risk of I2C interrupt handle execution before */
+7461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* all interrupts requested done */
+7462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+ 256              		.loc 1 7462 3 is_stmt 1 view .LVU74
+ 257 0070 0168     		ldr	r1, [r0]
+ 258              	.LVL20:
+ 259              		.loc 1 7462 3 is_stmt 0 view .LVU75
+ 260 0072 0A68     		ldr	r2, [r1]
+ 261 0074 1343     		orrs	r3, r3, r2
+ 262              	.LVL21:
+ 263              		.loc 1 7462 3 view .LVU76
+ 264 0076 0B60     		str	r3, [r1]
+7463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 265              		.loc 1 7463 1 view .LVU77
+ 266 0078 7047     		bx	lr
+ 267              	.LVL22:
+ 268              	.L19:
+7425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 269              		.loc 1 7425 14 view .LVU78
+ 270 007a B823     		movs	r3, #184
+ 271 007c E8E7     		b	.L13
+ 272              	.LVL23:
+ 273              	.L21:
+7443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 274              		.loc 1 7443 7 is_stmt 1 view .LVU79
+7443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 275              		.loc 1 7443 14 is_stmt 0 view .LVU80
+ 276 007e 43F09003 		orr	r3, r3, #144
+ 277              	.LVL24:
+7443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 278              		.loc 1 7443 14 view .LVU81
+ 279 0082 F1E7     		b	.L16
+ 280              	.L22:
+7449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 281              		.loc 1 7449 7 is_stmt 1 view .LVU82
+ARM GAS  /tmp/ccVyGVF6.s 			page 137
+
+
+7449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 282              		.loc 1 7449 14 is_stmt 0 view .LVU83
+ 283 0084 43F06003 		orr	r3, r3, #96
+ 284              	.LVL25:
+7449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 285              		.loc 1 7449 14 view .LVU84
+ 286 0088 F0E7     		b	.L17
+ 287              	.L23:
+7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 288              		.loc 1 7455 7 is_stmt 1 view .LVU85
+7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 289              		.loc 1 7455 14 is_stmt 0 view .LVU86
+ 290 008a 43F04003 		orr	r3, r3, #64
+ 291              	.LVL26:
+7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 292              		.loc 1 7455 14 view .LVU87
+ 293 008e EFE7     		b	.L12
+ 294              	.L25:
+ 295              		.align	2
+ 296              	.L24:
+ 297 0090 00000000 		.word	I2C_Master_ISR_DMA
+ 298 0094 00000000 		.word	I2C_Slave_ISR_DMA
+ 299 0098 00000000 		.word	I2C_Mem_ISR_DMA
+ 300              		.cfi_endproc
+ 301              	.LFE219:
+ 303              		.section	.text.I2C_Disable_IRQ,"ax",%progbits
+ 304              		.align	1
+ 305              		.syntax unified
+ 306              		.thumb
+ 307              		.thumb_func
+ 308              		.fpu fpv5-d16
+ 310              	I2C_Disable_IRQ:
+ 311              	.LVL27:
+ 312              	.LFB220:
+7464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+7466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Manage the disabling of Interrupts.
+7467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+7468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   *                the configuration information for the specified I2C.
+7469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+7470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+7471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+7472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+7473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+ 313              		.loc 1 7473 1 is_stmt 1 view -0
+ 314              		.cfi_startproc
+ 315              		@ args = 0, pretend = 0, frame = 0
+ 316              		@ frame_needed = 0, uses_anonymous_args = 0
+ 317              		@ link register save eliminated.
+7474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpisr = 0U;
+ 318              		.loc 1 7474 3 view .LVU89
+7475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ 319              		.loc 1 7476 3 view .LVU90
+ 320              		.loc 1 7476 6 is_stmt 0 view .LVU91
+ 321 0000 11F0010F 		tst	r1, #1
+ 322 0004 09D0     		beq	.L33
+ARM GAS  /tmp/ccVyGVF6.s 			page 138
+
+
+7477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable TC and TXI interrupts */
+7479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+ 323              		.loc 1 7479 5 is_stmt 1 view .LVU92
+ 324              	.LVL28:
+7480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+ 325              		.loc 1 7481 5 view .LVU93
+ 326              		.loc 1 7481 24 is_stmt 0 view .LVU94
+ 327 0006 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 328              		.loc 1 7481 8 view .LVU95
+ 329 000a 03F02803 		and	r3, r3, #40
+ 330 000e 282B     		cmp	r3, #40
+ 331 0010 01D0     		beq	.L36
+7482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+7483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable NACK and STOP interrupts */
+7484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ 332              		.loc 1 7484 14 view .LVU96
+ 333 0012 F223     		movs	r3, #242
+ 334 0014 02E0     		b	.L27
+ 335              	.L36:
+7479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 336              		.loc 1 7479 12 view .LVU97
+ 337 0016 4223     		movs	r3, #66
+ 338 0018 00E0     		b	.L27
+ 339              	.LVL29:
+ 340              	.L33:
+7474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 341              		.loc 1 7474 12 view .LVU98
+ 342 001a 0023     		movs	r3, #0
+ 343              	.LVL30:
+ 344              	.L27:
+7485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ 345              		.loc 1 7488 3 is_stmt 1 view .LVU99
+ 346              		.loc 1 7488 6 is_stmt 0 view .LVU100
+ 347 001c 11F0020F 		tst	r1, #2
+ 348 0020 09D0     		beq	.L28
+7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable TC and RXI interrupts */
+7491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+ 349              		.loc 1 7491 5 is_stmt 1 view .LVU101
+ 350              		.loc 1 7491 12 is_stmt 0 view .LVU102
+ 351 0022 43F0440C 		orr	ip, r3, #68
+ 352              	.LVL31:
+7492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+ 353              		.loc 1 7493 5 is_stmt 1 view .LVU103
+ 354              		.loc 1 7493 24 is_stmt 0 view .LVU104
+ 355 0026 90F84120 		ldrb	r2, [r0, #65]	@ zero_extendqisi2
+ 356              		.loc 1 7493 8 view .LVU105
+ 357 002a 02F02802 		and	r2, r2, #40
+ 358 002e 282A     		cmp	r2, #40
+ 359 0030 10D0     		beq	.L35
+7494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccVyGVF6.s 			page 139
+
+
+7495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       /* Disable NACK and STOP interrupts */
+7496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ 360              		.loc 1 7496 7 is_stmt 1 view .LVU106
+ 361              		.loc 1 7496 14 is_stmt 0 view .LVU107
+ 362 0032 43F0F403 		orr	r3, r3, #244
+ 363              	.LVL32:
+ 364              	.L28:
+7497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+7498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ 365              		.loc 1 7500 3 is_stmt 1 view .LVU108
+ 366              		.loc 1 7500 6 is_stmt 0 view .LVU109
+ 367 0036 11F4004F 		tst	r1, #32768
+ 368 003a 0DD1     		bne	.L37
+ 369              	.L29:
+7501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Disable ADDR, NACK and STOP interrupts */
+7503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+7504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (InterruptRequest == I2C_XFER_ERROR_IT)
+ 370              		.loc 1 7506 3 is_stmt 1 view .LVU110
+ 371              		.loc 1 7506 6 is_stmt 0 view .LVU111
+ 372 003c 1029     		cmp	r1, #16
+ 373 003e 0ED0     		beq	.L38
+ 374              	.L30:
+7507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable ERR and NACK interrupts */
+7509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+7510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (InterruptRequest == I2C_XFER_CPLT_IT)
+ 375              		.loc 1 7512 3 is_stmt 1 view .LVU112
+ 376              		.loc 1 7512 6 is_stmt 0 view .LVU113
+ 377 0040 2029     		cmp	r1, #32
+ 378 0042 0FD0     		beq	.L39
+ 379              	.L31:
+7513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable STOP interrupts */
+7515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmpisr |= I2C_IT_STOPI;
+7516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (InterruptRequest == I2C_XFER_RELOAD_IT)
+ 380              		.loc 1 7518 3 is_stmt 1 view .LVU114
+ 381              		.loc 1 7518 6 is_stmt 0 view .LVU115
+ 382 0044 4029     		cmp	r1, #64
+ 383 0046 10D0     		beq	.L40
+ 384              	.L32:
+7519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Enable TC interrupts */
+7521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     tmpisr |= I2C_IT_TCI;
+7522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Disable interrupts only at the end */
+7525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* to avoid a breaking situation like at "t" time */
+7526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* all disable interrupts request are not done */
+ARM GAS  /tmp/ccVyGVF6.s 			page 140
+
+
+7527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+ 385              		.loc 1 7527 3 is_stmt 1 view .LVU116
+ 386 0048 0168     		ldr	r1, [r0]
+ 387              	.LVL33:
+ 388              		.loc 1 7527 3 is_stmt 0 view .LVU117
+ 389 004a 0A68     		ldr	r2, [r1]
+ 390 004c 22EA0303 		bic	r3, r2, r3
+ 391              	.LVL34:
+ 392              		.loc 1 7527 3 view .LVU118
+ 393 0050 0B60     		str	r3, [r1]
+7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 394              		.loc 1 7528 1 view .LVU119
+ 395 0052 7047     		bx	lr
+ 396              	.LVL35:
+ 397              	.L35:
+7491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 398              		.loc 1 7491 12 view .LVU120
+ 399 0054 6346     		mov	r3, ip
+ 400 0056 EEE7     		b	.L28
+ 401              	.LVL36:
+ 402              	.L37:
+7503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 403              		.loc 1 7503 5 is_stmt 1 view .LVU121
+7503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 404              		.loc 1 7503 12 is_stmt 0 view .LVU122
+ 405 0058 43F0B803 		orr	r3, r3, #184
+ 406              	.LVL37:
+7503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 407              		.loc 1 7503 12 view .LVU123
+ 408 005c EEE7     		b	.L29
+ 409              	.L38:
+7509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 410              		.loc 1 7509 5 is_stmt 1 view .LVU124
+7509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 411              		.loc 1 7509 12 is_stmt 0 view .LVU125
+ 412 005e 43F09003 		orr	r3, r3, #144
+ 413              	.LVL38:
+7509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 414              		.loc 1 7509 12 view .LVU126
+ 415 0062 EDE7     		b	.L30
+ 416              	.L39:
+7515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 417              		.loc 1 7515 5 is_stmt 1 view .LVU127
+7515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 418              		.loc 1 7515 12 is_stmt 0 view .LVU128
+ 419 0064 43F02003 		orr	r3, r3, #32
+ 420              	.LVL39:
+7515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 421              		.loc 1 7515 12 view .LVU129
+ 422 0068 ECE7     		b	.L31
+ 423              	.L40:
+7521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 424              		.loc 1 7521 5 is_stmt 1 view .LVU130
+7521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 425              		.loc 1 7521 12 is_stmt 0 view .LVU131
+ 426 006a 43F04003 		orr	r3, r3, #64
+ 427              	.LVL40:
+ARM GAS  /tmp/ccVyGVF6.s 			page 141
+
+
+7521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 428              		.loc 1 7521 12 view .LVU132
+ 429 006e EBE7     		b	.L32
+ 430              		.cfi_endproc
+ 431              	.LFE220:
+ 433              		.section	.text.I2C_ConvertOtherXferOptions,"ax",%progbits
+ 434              		.align	1
+ 435              		.syntax unified
+ 436              		.thumb
+ 437              		.thumb_func
+ 438              		.fpu fpv5-d16
+ 440              	I2C_ConvertOtherXferOptions:
+ 441              	.LVL41:
+ 442              	.LFB221:
+7529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+7530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+7531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
+7532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @param  hi2c I2C handle.
+7533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   * @retval None
+7534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   */
+7535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+7536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** {
+ 443              		.loc 1 7536 1 is_stmt 1 view -0
+ 444              		.cfi_startproc
+ 445              		@ args = 0, pretend = 0, frame = 0
+ 446              		@ frame_needed = 0, uses_anonymous_args = 0
+ 447              		@ link register save eliminated.
+7537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* if user set XferOptions to I2C_OTHER_FRAME            */
+7538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* it request implicitly to generate a restart condition */
+7539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* set XferOptions to I2C_FIRST_FRAME                    */
+7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->XferOptions == I2C_OTHER_FRAME)
+ 448              		.loc 1 7540 3 view .LVU134
+ 449              		.loc 1 7540 11 is_stmt 0 view .LVU135
+ 450 0000 C36A     		ldr	r3, [r0, #44]
+ 451              		.loc 1 7540 6 view .LVU136
+ 452 0002 AA2B     		cmp	r3, #170
+ 453 0004 04D0     		beq	.L44
+7541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_FIRST_FRAME;
+7543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+7545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* it request implicitly to generate a restart condition    */
+7546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* then generate a stop condition at the end of transfer    */
+7547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
+7548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+ 454              		.loc 1 7548 8 is_stmt 1 view .LVU137
+ 455              		.loc 1 7548 16 is_stmt 0 view .LVU138
+ 456 0006 C36A     		ldr	r3, [r0, #44]
+ 457              		.loc 1 7548 11 view .LVU139
+ 458 0008 B3F52A4F 		cmp	r3, #43520
+ 459 000c 03D0     		beq	.L45
+ 460              	.L41:
+7549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+7550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+7551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   else
+7553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccVyGVF6.s 			page 142
+
+
+7554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     /* Nothing to do */
+7555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+7556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 461              		.loc 1 7556 1 view .LVU140
+ 462 000e 7047     		bx	lr
+ 463              	.L44:
+7542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 464              		.loc 1 7542 5 is_stmt 1 view .LVU141
+7542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 465              		.loc 1 7542 23 is_stmt 0 view .LVU142
+ 466 0010 0023     		movs	r3, #0
+ 467 0012 C362     		str	r3, [r0, #44]
+ 468 0014 7047     		bx	lr
+ 469              	.L45:
+7550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 470              		.loc 1 7550 5 is_stmt 1 view .LVU143
+7550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 471              		.loc 1 7550 23 is_stmt 0 view .LVU144
+ 472 0016 4FF00073 		mov	r3, #33554432
+ 473 001a C362     		str	r3, [r0, #44]
+7555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 474              		.loc 1 7555 3 is_stmt 1 view .LVU145
+ 475              		.loc 1 7556 1 is_stmt 0 view .LVU146
+ 476 001c F7E7     		b	.L41
+ 477              		.cfi_endproc
+ 478              	.LFE221:
+ 480              		.section	.text.I2C_IsErrorOccurred,"ax",%progbits
+ 481              		.align	1
+ 482              		.syntax unified
+ 483              		.thumb
+ 484              		.thumb_func
+ 485              		.fpu fpv5-d16
+ 487              	I2C_IsErrorOccurred:
+ 488              	.LVL42:
+ 489              	.LFB217:
+7214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 490              		.loc 1 7214 1 is_stmt 1 view -0
+ 491              		.cfi_startproc
+ 492              		@ args = 0, pretend = 0, frame = 0
+ 493              		@ frame_needed = 0, uses_anonymous_args = 0
+7214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 494              		.loc 1 7214 1 is_stmt 0 view .LVU148
+ 495 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 496              	.LCFI2:
+ 497              		.cfi_def_cfa_offset 24
+ 498              		.cfi_offset 4, -24
+ 499              		.cfi_offset 5, -20
+ 500              		.cfi_offset 6, -16
+ 501              		.cfi_offset 7, -12
+ 502              		.cfi_offset 8, -8
+ 503              		.cfi_offset 14, -4
+ 504 0004 0446     		mov	r4, r0
+7215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itflag   = hi2c->Instance->ISR;
+ 505              		.loc 1 7215 3 is_stmt 1 view .LVU149
+ 506              	.LVL43:
+7216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t error_code = 0;
+ 507              		.loc 1 7216 3 view .LVU150
+ARM GAS  /tmp/ccVyGVF6.s 			page 143
+
+
+7216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t error_code = 0;
+ 508              		.loc 1 7216 27 is_stmt 0 view .LVU151
+ 509 0006 0368     		ldr	r3, [r0]
+7216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t error_code = 0;
+ 510              		.loc 1 7216 12 view .LVU152
+ 511 0008 9E69     		ldr	r6, [r3, #24]
+ 512              	.LVL44:
+7217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart = Tickstart;
+ 513              		.loc 1 7217 3 is_stmt 1 view .LVU153
+7218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmp1;
+ 514              		.loc 1 7218 3 view .LVU154
+7219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_ModeTypeDef tmp2;
+ 515              		.loc 1 7219 3 view .LVU155
+7220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 516              		.loc 1 7220 3 view .LVU156
+7222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 517              		.loc 1 7222 3 view .LVU157
+7222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 518              		.loc 1 7222 6 is_stmt 0 view .LVU158
+ 519 000a 16F01006 		ands	r6, r6, #16
+ 520              	.LVL45:
+7222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 521              		.loc 1 7222 6 view .LVU159
+ 522 000e 7ED0     		beq	.L63
+ 523 0010 0D46     		mov	r5, r1
+ 524 0012 9046     		mov	r8, r2
+7225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 525              		.loc 1 7225 5 is_stmt 1 view .LVU160
+ 526 0014 1022     		movs	r2, #16
+ 527              	.LVL46:
+7225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 528              		.loc 1 7225 5 is_stmt 0 view .LVU161
+ 529 0016 DA61     		str	r2, [r3, #28]
+7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 530              		.loc 1 7229 5 is_stmt 1 view .LVU162
+7217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart = Tickstart;
+ 531              		.loc 1 7217 12 is_stmt 0 view .LVU163
+ 532 0018 0026     		movs	r6, #0
+7215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itflag   = hi2c->Instance->ISR;
+ 533              		.loc 1 7215 21 view .LVU164
+ 534 001a 3746     		mov	r7, r6
+ 535              	.LVL47:
+ 536              	.L49:
+7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 537              		.loc 1 7229 11 is_stmt 1 view .LVU165
+7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 538              		.loc 1 7229 13 is_stmt 0 view .LVU166
+ 539 001c 2368     		ldr	r3, [r4]
+ 540 001e 9869     		ldr	r0, [r3, #24]
+7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 541              		.loc 1 7229 11 view .LVU167
+ 542 0020 10F0200F 		tst	r0, #32
+ 543 0024 32D1     		bne	.L55
+7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 544              		.loc 1 7229 64 discriminator 1 view .LVU168
+ 545 0026 8FBB     		cbnz	r7, .L55
+7232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ARM GAS  /tmp/ccVyGVF6.s 			page 144
+
+
+ 546              		.loc 1 7232 7 is_stmt 1 view .LVU169
+7232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 547              		.loc 1 7232 10 is_stmt 0 view .LVU170
+ 548 0028 B5F1FF3F 		cmp	r5, #-1
+ 549 002c F6D0     		beq	.L49
+7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 550              		.loc 1 7234 9 is_stmt 1 view .LVU171
+7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 551              		.loc 1 7234 15 is_stmt 0 view .LVU172
+ 552 002e FFF7FEFF 		bl	HAL_GetTick
+ 553              	.LVL48:
+7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 554              		.loc 1 7234 29 view .LVU173
+ 555 0032 A0EB0800 		sub	r0, r0, r8
+7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 556              		.loc 1 7234 12 view .LVU174
+ 557 0036 A842     		cmp	r0, r5
+ 558 0038 01D8     		bhi	.L50
+7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 559              		.loc 1 7234 53 discriminator 1 view .LVU175
+ 560 003a 002D     		cmp	r5, #0
+ 561 003c EED1     		bne	.L49
+ 562              	.L50:
+7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           tmp2 = hi2c->Mode;
+ 563              		.loc 1 7236 11 is_stmt 1 view .LVU176
+7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           tmp2 = hi2c->Mode;
+ 564              		.loc 1 7236 33 is_stmt 0 view .LVU177
+ 565 003e 2168     		ldr	r1, [r4]
+7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           tmp2 = hi2c->Mode;
+ 566              		.loc 1 7236 43 view .LVU178
+ 567 0040 4A68     		ldr	r2, [r1, #4]
+7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           tmp2 = hi2c->Mode;
+ 568              		.loc 1 7236 16 view .LVU179
+ 569 0042 02F48042 		and	r2, r2, #16384
+ 570              	.LVL49:
+7237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 571              		.loc 1 7237 11 is_stmt 1 view .LVU180
+7237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 572              		.loc 1 7237 16 is_stmt 0 view .LVU181
+ 573 0046 94F84230 		ldrb	r3, [r4, #66]	@ zero_extendqisi2
+ 574 004a DBB2     		uxtb	r3, r3
+ 575              	.LVL50:
+7240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               (tmp1 != I2C_CR2_STOP) && \
+ 576              		.loc 1 7240 11 is_stmt 1 view .LVU182
+7240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               (tmp1 != I2C_CR2_STOP) && \
+ 577              		.loc 1 7240 16 is_stmt 0 view .LVU183
+ 578 004c 8869     		ldr	r0, [r1, #24]
+7240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               (tmp1 != I2C_CR2_STOP) && \
+ 579              		.loc 1 7240 14 view .LVU184
+ 580 004e 10F4004F 		tst	r0, #32768
+ 581 0052 04D0     		beq	.L53
+7242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 582              		.loc 1 7242 21 view .LVU185
+ 583 0054 203B     		subs	r3, r3, #32
+ 584              	.LVL51:
+7242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 585              		.loc 1 7242 21 view .LVU186
+ARM GAS  /tmp/ccVyGVF6.s 			page 145
+
+
+ 586 0056 18BF     		it	ne
+ 587 0058 0123     		movne	r3, #1
+ 588              	.LVL52:
+7241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****               (tmp2 != HAL_I2C_MODE_SLAVE))
+ 589              		.loc 1 7241 38 view .LVU187
+ 590 005a 02B9     		cbnz	r2, .L53
+ 591 005c 73B9     		cbnz	r3, .L65
+ 592              	.LVL53:
+ 593              	.L53:
+7251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 594              		.loc 1 7251 17 is_stmt 1 view .LVU188
+7251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 595              		.loc 1 7251 18 is_stmt 0 view .LVU189
+ 596 005e 2368     		ldr	r3, [r4]
+ 597 0060 9B69     		ldr	r3, [r3, #24]
+7251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 598              		.loc 1 7251 17 view .LVU190
+ 599 0062 13F0200F 		tst	r3, #32
+ 600 0066 D9D1     		bne	.L49
+7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             {
+ 601              		.loc 1 7254 13 is_stmt 1 view .LVU191
+7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             {
+ 602              		.loc 1 7254 18 is_stmt 0 view .LVU192
+ 603 0068 FFF7FEFF 		bl	HAL_GetTick
+ 604              	.LVL54:
+7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             {
+ 605              		.loc 1 7254 32 view .LVU193
+ 606 006c A0EB0800 		sub	r0, r0, r8
+7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             {
+ 607              		.loc 1 7254 16 view .LVU194
+ 608 0070 1928     		cmp	r0, #25
+ 609 0072 F4D9     		bls	.L53
+7256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 610              		.loc 1 7256 15 is_stmt 1 view .LVU195
+7256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 611              		.loc 1 7256 26 is_stmt 0 view .LVU196
+ 612 0074 46F02006 		orr	r6, r6, #32
+ 613              	.LVL55:
+7258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 614              		.loc 1 7258 15 is_stmt 1 view .LVU197
+7260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             }
+ 615              		.loc 1 7260 15 view .LVU198
+7258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 616              		.loc 1 7258 22 is_stmt 0 view .LVU199
+ 617 0078 0127     		movs	r7, #1
+7260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             }
+ 618              		.loc 1 7260 15 view .LVU200
+ 619 007a CFE7     		b	.L49
+ 620              	.LVL56:
+ 621              	.L65:
+7245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 622              		.loc 1 7245 13 is_stmt 1 view .LVU201
+7245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 623              		.loc 1 7245 33 is_stmt 0 view .LVU202
+ 624 007c 4B68     		ldr	r3, [r1, #4]
+ 625 007e 43F48043 		orr	r3, r3, #16384
+ 626 0082 4B60     		str	r3, [r1, #4]
+ARM GAS  /tmp/ccVyGVF6.s 			page 146
+
+
+7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 627              		.loc 1 7248 13 is_stmt 1 view .LVU203
+7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 628              		.loc 1 7248 25 is_stmt 0 view .LVU204
+ 629 0084 FFF7FEFF 		bl	HAL_GetTick
+ 630              	.LVL57:
+7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 631              		.loc 1 7248 25 view .LVU205
+ 632 0088 8046     		mov	r8, r0
+ 633              	.LVL58:
+7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 634              		.loc 1 7248 25 view .LVU206
+ 635 008a E8E7     		b	.L53
+ 636              	.LVL59:
+ 637              	.L55:
+7268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 638              		.loc 1 7268 5 is_stmt 1 view .LVU207
+7268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 639              		.loc 1 7268 8 is_stmt 0 view .LVU208
+ 640 008c 0FB9     		cbnz	r7, .L57
+7271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 641              		.loc 1 7271 7 is_stmt 1 view .LVU209
+ 642 008e 2022     		movs	r2, #32
+ 643 0090 DA61     		str	r2, [r3, #28]
+ 644              	.L57:
+7274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 645              		.loc 1 7274 5 view .LVU210
+7274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 646              		.loc 1 7274 16 is_stmt 0 view .LVU211
+ 647 0092 46F00406 		orr	r6, r6, #4
+ 648              	.LVL60:
+7276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 649              		.loc 1 7276 5 is_stmt 1 view .LVU212
+7276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 650              		.loc 1 7276 12 is_stmt 0 view .LVU213
+ 651 0096 0125     		movs	r5, #1
+ 652              	.LVL61:
+ 653              	.L47:
+7280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 654              		.loc 1 7280 3 is_stmt 1 view .LVU214
+7280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 655              		.loc 1 7280 16 is_stmt 0 view .LVU215
+ 656 0098 2268     		ldr	r2, [r4]
+7280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 657              		.loc 1 7280 10 view .LVU216
+ 658 009a 9369     		ldr	r3, [r2, #24]
+ 659              	.LVL62:
+7284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 660              		.loc 1 7284 3 is_stmt 1 view .LVU217
+7284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 661              		.loc 1 7284 6 is_stmt 0 view .LVU218
+ 662 009c 13F4807F 		tst	r3, #256
+ 663 00a0 05D0     		beq	.L58
+7286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 664              		.loc 1 7286 5 is_stmt 1 view .LVU219
+7286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 665              		.loc 1 7286 16 is_stmt 0 view .LVU220
+ARM GAS  /tmp/ccVyGVF6.s 			page 147
+
+
+ 666 00a2 46F00106 		orr	r6, r6, #1
+ 667              	.LVL63:
+7289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 668              		.loc 1 7289 5 is_stmt 1 view .LVU221
+ 669 00a6 4FF48071 		mov	r1, #256
+ 670 00aa D161     		str	r1, [r2, #28]
+7291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 671              		.loc 1 7291 5 view .LVU222
+ 672              	.LVL64:
+7291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 673              		.loc 1 7291 12 is_stmt 0 view .LVU223
+ 674 00ac 0125     		movs	r5, #1
+ 675              	.LVL65:
+ 676              	.L58:
+7295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 677              		.loc 1 7295 3 is_stmt 1 view .LVU224
+7295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 678              		.loc 1 7295 6 is_stmt 0 view .LVU225
+ 679 00ae 13F4806F 		tst	r3, #1024
+ 680 00b2 06D0     		beq	.L59
+7297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 681              		.loc 1 7297 5 is_stmt 1 view .LVU226
+7297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 682              		.loc 1 7297 16 is_stmt 0 view .LVU227
+ 683 00b4 46F00806 		orr	r6, r6, #8
+ 684              	.LVL66:
+7300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 685              		.loc 1 7300 5 is_stmt 1 view .LVU228
+ 686 00b8 2268     		ldr	r2, [r4]
+ 687 00ba 4FF48061 		mov	r1, #1024
+ 688 00be D161     		str	r1, [r2, #28]
+7302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 689              		.loc 1 7302 5 view .LVU229
+ 690              	.LVL67:
+7302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 691              		.loc 1 7302 12 is_stmt 0 view .LVU230
+ 692 00c0 0125     		movs	r5, #1
+ 693              	.LVL68:
+ 694              	.L59:
+7306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 695              		.loc 1 7306 3 is_stmt 1 view .LVU231
+7306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 696              		.loc 1 7306 6 is_stmt 0 view .LVU232
+ 697 00c2 13F4007F 		tst	r3, #512
+ 698 00c6 24D0     		beq	.L60
+7308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 699              		.loc 1 7308 5 is_stmt 1 view .LVU233
+7308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 700              		.loc 1 7308 16 is_stmt 0 view .LVU234
+ 701 00c8 46F00206 		orr	r6, r6, #2
+ 702              	.LVL69:
+7311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 703              		.loc 1 7311 5 is_stmt 1 view .LVU235
+ 704 00cc 2368     		ldr	r3, [r4]
+ 705              	.LVL70:
+7311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 706              		.loc 1 7311 5 is_stmt 0 view .LVU236
+ARM GAS  /tmp/ccVyGVF6.s 			page 148
+
+
+ 707 00ce 4FF40072 		mov	r2, #512
+ 708 00d2 DA61     		str	r2, [r3, #28]
+7313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 709              		.loc 1 7313 5 is_stmt 1 view .LVU237
+ 710              	.LVL71:
+7316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 711              		.loc 1 7316 3 view .LVU238
+7313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 712              		.loc 1 7313 12 is_stmt 0 view .LVU239
+ 713 00d4 0125     		movs	r5, #1
+ 714              	.LVL72:
+ 715              	.L61:
+7319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 716              		.loc 1 7319 5 is_stmt 1 view .LVU240
+ 717 00d6 2046     		mov	r0, r4
+ 718 00d8 FFF7FEFF 		bl	I2C_Flush_TXDR
+ 719              	.LVL73:
+7322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 720              		.loc 1 7322 5 view .LVU241
+ 721 00dc 2268     		ldr	r2, [r4]
+ 722 00de 5368     		ldr	r3, [r2, #4]
+ 723 00e0 23F0FF73 		bic	r3, r3, #33423360
+ 724 00e4 23F48B33 		bic	r3, r3, #71168
+ 725 00e8 23F4FF73 		bic	r3, r3, #510
+ 726 00ec 23F00103 		bic	r3, r3, #1
+ 727 00f0 5360     		str	r3, [r2, #4]
+7324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 728              		.loc 1 7324 5 view .LVU242
+7324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 729              		.loc 1 7324 21 is_stmt 0 view .LVU243
+ 730 00f2 636C     		ldr	r3, [r4, #68]
+ 731 00f4 1E43     		orrs	r6, r6, r3
+ 732              	.LVL74:
+7324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 733              		.loc 1 7324 21 view .LVU244
+ 734 00f6 6664     		str	r6, [r4, #68]
+7325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+ 735              		.loc 1 7325 5 is_stmt 1 view .LVU245
+7325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+ 736              		.loc 1 7325 17 is_stmt 0 view .LVU246
+ 737 00f8 2023     		movs	r3, #32
+ 738 00fa 84F84130 		strb	r3, [r4, #65]
+7326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 739              		.loc 1 7326 5 is_stmt 1 view .LVU247
+7326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 740              		.loc 1 7326 16 is_stmt 0 view .LVU248
+ 741 00fe 0023     		movs	r3, #0
+ 742 0100 84F84230 		strb	r3, [r4, #66]
+7329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 743              		.loc 1 7329 5 is_stmt 1 view .LVU249
+7329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 744              		.loc 1 7329 5 view .LVU250
+ 745 0104 84F84030 		strb	r3, [r4, #64]
+ 746              	.L62:
+7329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 747              		.loc 1 7329 5 discriminator 1 view .LVU251
+7332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ARM GAS  /tmp/ccVyGVF6.s 			page 149
+
+
+ 748              		.loc 1 7332 3 discriminator 1 view .LVU252
+7333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 749              		.loc 1 7333 1 is_stmt 0 discriminator 1 view .LVU253
+ 750 0108 2846     		mov	r0, r5
+ 751 010a BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 752              	.LVL75:
+ 753              	.L63:
+7215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itflag   = hi2c->Instance->ISR;
+ 754              		.loc 1 7215 21 view .LVU254
+ 755 010e 0025     		movs	r5, #0
+ 756 0110 C2E7     		b	.L47
+ 757              	.LVL76:
+ 758              	.L60:
+7316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 759              		.loc 1 7316 3 is_stmt 1 view .LVU255
+7316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 760              		.loc 1 7316 6 is_stmt 0 view .LVU256
+ 761 0112 002D     		cmp	r5, #0
+ 762 0114 F8D0     		beq	.L62
+ 763 0116 DEE7     		b	.L61
+ 764              		.cfi_endproc
+ 765              	.LFE217:
+ 767              		.section	.text.I2C_WaitOnTXISFlagUntilTimeout,"ax",%progbits
+ 768              		.align	1
+ 769              		.syntax unified
+ 770              		.thumb
+ 771              		.thumb_func
+ 772              		.fpu fpv5-d16
+ 774              	I2C_WaitOnTXISFlagUntilTimeout:
+ 775              	.LVL77:
+ 776              	.LFB214:
+7059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+ 777              		.loc 1 7059 1 is_stmt 1 view -0
+ 778              		.cfi_startproc
+ 779              		@ args = 0, pretend = 0, frame = 0
+ 780              		@ frame_needed = 0, uses_anonymous_args = 0
+7059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+ 781              		.loc 1 7059 1 is_stmt 0 view .LVU258
+ 782 0000 70B5     		push	{r4, r5, r6, lr}
+ 783              	.LCFI3:
+ 784              		.cfi_def_cfa_offset 16
+ 785              		.cfi_offset 4, -16
+ 786              		.cfi_offset 5, -12
+ 787              		.cfi_offset 6, -8
+ 788              		.cfi_offset 14, -4
+ 789 0002 0446     		mov	r4, r0
+ 790 0004 0D46     		mov	r5, r1
+ 791 0006 1646     		mov	r6, r2
+7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 792              		.loc 1 7060 3 is_stmt 1 view .LVU259
+ 793              	.LVL78:
+ 794              	.L69:
+7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 795              		.loc 1 7060 9 view .LVU260
+7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 796              		.loc 1 7060 10 is_stmt 0 view .LVU261
+ 797 0008 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/ccVyGVF6.s 			page 150
+
+
+ 798 000a 9B69     		ldr	r3, [r3, #24]
+7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 799              		.loc 1 7060 9 view .LVU262
+ 800 000c 13F0020F 		tst	r3, #2
+ 801 0010 22D1     		bne	.L74
+7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 802              		.loc 1 7063 5 is_stmt 1 view .LVU263
+7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 803              		.loc 1 7063 9 is_stmt 0 view .LVU264
+ 804 0012 3246     		mov	r2, r6
+ 805 0014 2946     		mov	r1, r5
+ 806 0016 2046     		mov	r0, r4
+ 807 0018 FFF7FEFF 		bl	I2C_IsErrorOccurred
+ 808              	.LVL79:
+7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 809              		.loc 1 7063 8 view .LVU265
+ 810 001c F0B9     		cbnz	r0, .L72
+7069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 811              		.loc 1 7069 5 is_stmt 1 view .LVU266
+7069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 812              		.loc 1 7069 8 is_stmt 0 view .LVU267
+ 813 001e B5F1FF3F 		cmp	r5, #-1
+ 814 0022 F1D0     		beq	.L69
+7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 815              		.loc 1 7071 7 is_stmt 1 view .LVU268
+7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 816              		.loc 1 7071 13 is_stmt 0 view .LVU269
+ 817 0024 FFF7FEFF 		bl	HAL_GetTick
+ 818              	.LVL80:
+7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 819              		.loc 1 7071 27 view .LVU270
+ 820 0028 801B     		subs	r0, r0, r6
+7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 821              		.loc 1 7071 10 view .LVU271
+ 822 002a A842     		cmp	r0, r5
+ 823 002c 01D8     		bhi	.L70
+7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 824              		.loc 1 7071 51 discriminator 1 view .LVU272
+ 825 002e 002D     		cmp	r5, #0
+ 826 0030 EAD1     		bne	.L69
+ 827              	.L70:
+7073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 828              		.loc 1 7073 9 is_stmt 1 view .LVU273
+7073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 829              		.loc 1 7073 14 is_stmt 0 view .LVU274
+ 830 0032 2368     		ldr	r3, [r4]
+ 831 0034 9B69     		ldr	r3, [r3, #24]
+7073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 832              		.loc 1 7073 12 view .LVU275
+ 833 0036 13F0020F 		tst	r3, #2
+ 834 003a E5D1     		bne	.L69
+7075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->State = HAL_I2C_STATE_READY;
+ 835              		.loc 1 7075 11 is_stmt 1 view .LVU276
+7075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->State = HAL_I2C_STATE_READY;
+ 836              		.loc 1 7075 27 is_stmt 0 view .LVU277
+ 837 003c 636C     		ldr	r3, [r4, #68]
+ 838 003e 43F02003 		orr	r3, r3, #32
+ARM GAS  /tmp/ccVyGVF6.s 			page 151
+
+
+ 839 0042 6364     		str	r3, [r4, #68]
+7076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->Mode = HAL_I2C_MODE_NONE;
+ 840              		.loc 1 7076 11 is_stmt 1 view .LVU278
+7076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->Mode = HAL_I2C_MODE_NONE;
+ 841              		.loc 1 7076 23 is_stmt 0 view .LVU279
+ 842 0044 2023     		movs	r3, #32
+ 843 0046 84F84130 		strb	r3, [r4, #65]
+7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 844              		.loc 1 7077 11 is_stmt 1 view .LVU280
+7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 845              		.loc 1 7077 22 is_stmt 0 view .LVU281
+ 846 004a 0023     		movs	r3, #0
+ 847 004c 84F84230 		strb	r3, [r4, #66]
+7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 848              		.loc 1 7080 11 is_stmt 1 view .LVU282
+7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 849              		.loc 1 7080 11 view .LVU283
+ 850 0050 84F84030 		strb	r3, [r4, #64]
+7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 851              		.loc 1 7080 11 view .LVU284
+7082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 852              		.loc 1 7082 11 view .LVU285
+7082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 853              		.loc 1 7082 18 is_stmt 0 view .LVU286
+ 854 0054 0120     		movs	r0, #1
+ 855 0056 00E0     		b	.L68
+ 856              	.L74:
+7087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 857              		.loc 1 7087 10 view .LVU287
+ 858 0058 0020     		movs	r0, #0
+ 859              	.L68:
+7088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 860              		.loc 1 7088 1 view .LVU288
+ 861 005a 70BD     		pop	{r4, r5, r6, pc}
+ 862              	.LVL81:
+ 863              	.L72:
+7065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 864              		.loc 1 7065 14 view .LVU289
+ 865 005c 0120     		movs	r0, #1
+ 866 005e FCE7     		b	.L68
+ 867              		.cfi_endproc
+ 868              	.LFE214:
+ 870              		.section	.text.I2C_WaitOnFlagUntilTimeout,"ax",%progbits
+ 871              		.align	1
+ 872              		.syntax unified
+ 873              		.thumb
+ 874              		.thumb_func
+ 875              		.fpu fpv5-d16
+ 877              	I2C_WaitOnFlagUntilTimeout:
+ 878              	.LVL82:
+ 879              	.LFB213:
+7019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+ 880              		.loc 1 7019 1 is_stmt 1 view -0
+ 881              		.cfi_startproc
+ 882              		@ args = 4, pretend = 0, frame = 0
+ 883              		@ frame_needed = 0, uses_anonymous_args = 0
+7019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+ARM GAS  /tmp/ccVyGVF6.s 			page 152
+
+
+ 884              		.loc 1 7019 1 is_stmt 0 view .LVU291
+ 885 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 886              	.LCFI4:
+ 887              		.cfi_def_cfa_offset 24
+ 888              		.cfi_offset 4, -24
+ 889              		.cfi_offset 5, -20
+ 890              		.cfi_offset 6, -16
+ 891              		.cfi_offset 7, -12
+ 892              		.cfi_offset 8, -8
+ 893              		.cfi_offset 14, -4
+ 894 0004 0446     		mov	r4, r0
+ 895 0006 0F46     		mov	r7, r1
+ 896 0008 1646     		mov	r6, r2
+ 897 000a 1D46     		mov	r5, r3
+ 898 000c DDF81880 		ldr	r8, [sp, #24]
+7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 899              		.loc 1 7020 3 is_stmt 1 view .LVU292
+ 900              	.LVL83:
+ 901              	.L78:
+7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 902              		.loc 1 7020 9 view .LVU293
+7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 903              		.loc 1 7020 10 is_stmt 0 view .LVU294
+ 904 0010 2368     		ldr	r3, [r4]
+ 905 0012 9B69     		ldr	r3, [r3, #24]
+ 906 0014 37EA0303 		bics	r3, r7, r3
+ 907 0018 0CBF     		ite	eq
+ 908 001a 0123     		moveq	r3, #1
+ 909 001c 0023     		movne	r3, #0
+7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 910              		.loc 1 7020 9 view .LVU295
+ 911 001e B342     		cmp	r3, r6
+ 912 0020 27D1     		bne	.L83
+7023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 913              		.loc 1 7023 5 is_stmt 1 view .LVU296
+7023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 914              		.loc 1 7023 9 is_stmt 0 view .LVU297
+ 915 0022 4246     		mov	r2, r8
+ 916 0024 2946     		mov	r1, r5
+ 917 0026 2046     		mov	r0, r4
+ 918 0028 FFF7FEFF 		bl	I2C_IsErrorOccurred
+ 919              	.LVL84:
+7023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 920              		.loc 1 7023 8 view .LVU298
+ 921 002c 20BB     		cbnz	r0, .L81
+7029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 922              		.loc 1 7029 5 is_stmt 1 view .LVU299
+7029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 923              		.loc 1 7029 8 is_stmt 0 view .LVU300
+ 924 002e B5F1FF3F 		cmp	r5, #-1
+ 925 0032 EDD0     		beq	.L78
+7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 926              		.loc 1 7031 7 is_stmt 1 view .LVU301
+7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 927              		.loc 1 7031 13 is_stmt 0 view .LVU302
+ 928 0034 FFF7FEFF 		bl	HAL_GetTick
+ 929              	.LVL85:
+ARM GAS  /tmp/ccVyGVF6.s 			page 153
+
+
+7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 930              		.loc 1 7031 27 view .LVU303
+ 931 0038 A0EB0800 		sub	r0, r0, r8
+7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 932              		.loc 1 7031 10 view .LVU304
+ 933 003c A842     		cmp	r0, r5
+ 934 003e 01D8     		bhi	.L79
+7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 935              		.loc 1 7031 51 discriminator 1 view .LVU305
+ 936 0040 002D     		cmp	r5, #0
+ 937 0042 E5D1     		bne	.L78
+ 938              	.L79:
+7033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 939              		.loc 1 7033 9 is_stmt 1 view .LVU306
+7033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 940              		.loc 1 7033 14 is_stmt 0 view .LVU307
+ 941 0044 2368     		ldr	r3, [r4]
+ 942 0046 9B69     		ldr	r3, [r3, #24]
+ 943 0048 37EA0303 		bics	r3, r7, r3
+ 944 004c 0CBF     		ite	eq
+ 945 004e 0123     		moveq	r3, #1
+ 946 0050 0023     		movne	r3, #0
+7033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 947              		.loc 1 7033 12 view .LVU308
+ 948 0052 B342     		cmp	r3, r6
+ 949 0054 DCD1     		bne	.L78
+7035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->State = HAL_I2C_STATE_READY;
+ 950              		.loc 1 7035 11 is_stmt 1 view .LVU309
+7035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->State = HAL_I2C_STATE_READY;
+ 951              		.loc 1 7035 27 is_stmt 0 view .LVU310
+ 952 0056 636C     		ldr	r3, [r4, #68]
+ 953 0058 43F02003 		orr	r3, r3, #32
+ 954 005c 6364     		str	r3, [r4, #68]
+7036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->Mode = HAL_I2C_MODE_NONE;
+ 955              		.loc 1 7036 11 is_stmt 1 view .LVU311
+7036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->Mode = HAL_I2C_MODE_NONE;
+ 956              		.loc 1 7036 23 is_stmt 0 view .LVU312
+ 957 005e 2023     		movs	r3, #32
+ 958 0060 84F84130 		strb	r3, [r4, #65]
+7037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 959              		.loc 1 7037 11 is_stmt 1 view .LVU313
+7037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 960              		.loc 1 7037 22 is_stmt 0 view .LVU314
+ 961 0064 0023     		movs	r3, #0
+ 962 0066 84F84230 		strb	r3, [r4, #66]
+7040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           return HAL_ERROR;
+ 963              		.loc 1 7040 11 is_stmt 1 view .LVU315
+7040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           return HAL_ERROR;
+ 964              		.loc 1 7040 11 view .LVU316
+ 965 006a 84F84030 		strb	r3, [r4, #64]
+7040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           return HAL_ERROR;
+ 966              		.loc 1 7040 11 view .LVU317
+7041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 967              		.loc 1 7041 11 view .LVU318
+7041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 968              		.loc 1 7041 18 is_stmt 0 view .LVU319
+ 969 006e 0120     		movs	r0, #1
+ARM GAS  /tmp/ccVyGVF6.s 			page 154
+
+
+ 970 0070 00E0     		b	.L77
+ 971              	.L83:
+7046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 972              		.loc 1 7046 10 view .LVU320
+ 973 0072 0020     		movs	r0, #0
+ 974              	.L77:
+7047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 975              		.loc 1 7047 1 view .LVU321
+ 976 0074 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 977              	.LVL86:
+ 978              	.L81:
+7025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 979              		.loc 1 7025 14 view .LVU322
+ 980 0078 0120     		movs	r0, #1
+ 981 007a FBE7     		b	.L77
+ 982              		.cfi_endproc
+ 983              	.LFE213:
+ 985              		.section	.text.I2C_RequestMemoryWrite,"ax",%progbits
+ 986              		.align	1
+ 987              		.syntax unified
+ 988              		.thumb
+ 989              		.thumb_func
+ 990              		.fpu fpv5-d16
+ 992              	I2C_RequestMemoryWrite:
+ 993              	.LVL87:
+ 994              	.LFB196:
+5856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI
+ 995              		.loc 1 5856 1 is_stmt 1 view -0
+ 996              		.cfi_startproc
+ 997              		@ args = 8, pretend = 0, frame = 0
+ 998              		@ frame_needed = 0, uses_anonymous_args = 0
+5856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI
+ 999              		.loc 1 5856 1 is_stmt 0 view .LVU324
+ 1000 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 1001              	.LCFI5:
+ 1002              		.cfi_def_cfa_offset 24
+ 1003              		.cfi_offset 4, -24
+ 1004              		.cfi_offset 5, -20
+ 1005              		.cfi_offset 6, -16
+ 1006              		.cfi_offset 7, -12
+ 1007              		.cfi_offset 8, -8
+ 1008              		.cfi_offset 14, -4
+ 1009 0004 82B0     		sub	sp, sp, #8
+ 1010              	.LCFI6:
+ 1011              		.cfi_def_cfa_offset 32
+ 1012 0006 0446     		mov	r4, r0
+ 1013 0008 9046     		mov	r8, r2
+ 1014 000a 1D46     		mov	r5, r3
+ 1015 000c 089E     		ldr	r6, [sp, #32]
+ 1016 000e 099F     		ldr	r7, [sp, #36]
+5857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1017              		.loc 1 5857 3 is_stmt 1 view .LVU325
+ 1018 0010 194B     		ldr	r3, .L93
+ 1019              	.LVL88:
+5857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1020              		.loc 1 5857 3 is_stmt 0 view .LVU326
+ 1021 0012 0093     		str	r3, [sp]
+ARM GAS  /tmp/ccVyGVF6.s 			page 155
+
+
+ 1022 0014 4FF08073 		mov	r3, #16777216
+ 1023 0018 EAB2     		uxtb	r2, r5
+ 1024              	.LVL89:
+5857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1025              		.loc 1 5857 3 view .LVU327
+ 1026 001a FFF7FEFF 		bl	I2C_TransferConfig
+ 1027              	.LVL90:
+5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1028              		.loc 1 5860 3 is_stmt 1 view .LVU328
+5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1029              		.loc 1 5860 7 is_stmt 0 view .LVU329
+ 1030 001e 3A46     		mov	r2, r7
+ 1031 0020 3146     		mov	r1, r6
+ 1032 0022 2046     		mov	r0, r4
+ 1033 0024 FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 1034              	.LVL91:
+5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1035              		.loc 1 5860 6 view .LVU330
+ 1036 0028 F8B9     		cbnz	r0, .L88
+5866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1037              		.loc 1 5866 3 is_stmt 1 view .LVU331
+5866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1038              		.loc 1 5866 6 is_stmt 0 view .LVU332
+ 1039 002a 012D     		cmp	r5, #1
+ 1040 002c 0ED1     		bne	.L86
+5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1041              		.loc 1 5869 5 is_stmt 1 view .LVU333
+5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1042              		.loc 1 5869 9 is_stmt 0 view .LVU334
+ 1043 002e 2368     		ldr	r3, [r4]
+5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1044              		.loc 1 5869 28 view .LVU335
+ 1045 0030 5FFA88F2 		uxtb	r2, r8
+5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1046              		.loc 1 5869 26 view .LVU336
+ 1047 0034 9A62     		str	r2, [r3, #40]
+ 1048              	.L87:
+5888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1049              		.loc 1 5888 3 is_stmt 1 view .LVU337
+5888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1050              		.loc 1 5888 7 is_stmt 0 view .LVU338
+ 1051 0036 0097     		str	r7, [sp]
+ 1052 0038 3346     		mov	r3, r6
+ 1053 003a 0022     		movs	r2, #0
+ 1054 003c 8021     		movs	r1, #128
+ 1055 003e 2046     		mov	r0, r4
+ 1056 0040 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 1057              	.LVL92:
+5888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1058              		.loc 1 5888 6 view .LVU339
+ 1059 0044 A8B9     		cbnz	r0, .L92
+ 1060              	.L85:
+5894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1061              		.loc 1 5894 1 view .LVU340
+ 1062 0046 02B0     		add	sp, sp, #8
+ 1063              	.LCFI7:
+ 1064              		.cfi_remember_state
+ARM GAS  /tmp/ccVyGVF6.s 			page 156
+
+
+ 1065              		.cfi_def_cfa_offset 24
+ 1066              		@ sp needed
+ 1067 0048 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 1068              	.LVL93:
+ 1069              	.L86:
+ 1070              	.LCFI8:
+ 1071              		.cfi_restore_state
+5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1072              		.loc 1 5875 5 is_stmt 1 view .LVU341
+5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1073              		.loc 1 5875 9 is_stmt 0 view .LVU342
+ 1074 004c 2368     		ldr	r3, [r4]
+5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1075              		.loc 1 5875 28 view .LVU343
+ 1076 004e 4FEA1822 		lsr	r2, r8, #8
+5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1077              		.loc 1 5875 26 view .LVU344
+ 1078 0052 9A62     		str	r2, [r3, #40]
+5878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1079              		.loc 1 5878 5 is_stmt 1 view .LVU345
+5878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1080              		.loc 1 5878 9 is_stmt 0 view .LVU346
+ 1081 0054 3A46     		mov	r2, r7
+ 1082 0056 3146     		mov	r1, r6
+ 1083 0058 2046     		mov	r0, r4
+ 1084 005a FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 1085              	.LVL94:
+5878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1086              		.loc 1 5878 8 view .LVU347
+ 1087 005e 30B9     		cbnz	r0, .L89
+5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1088              		.loc 1 5884 5 is_stmt 1 view .LVU348
+5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1089              		.loc 1 5884 9 is_stmt 0 view .LVU349
+ 1090 0060 2368     		ldr	r3, [r4]
+5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1091              		.loc 1 5884 28 view .LVU350
+ 1092 0062 5FFA88F2 		uxtb	r2, r8
+5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1093              		.loc 1 5884 26 view .LVU351
+ 1094 0066 9A62     		str	r2, [r3, #40]
+ 1095 0068 E5E7     		b	.L87
+ 1096              	.L88:
+5862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1097              		.loc 1 5862 12 view .LVU352
+ 1098 006a 0120     		movs	r0, #1
+ 1099 006c EBE7     		b	.L85
+ 1100              	.L89:
+5880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 1101              		.loc 1 5880 14 view .LVU353
+ 1102 006e 0120     		movs	r0, #1
+ 1103 0070 E9E7     		b	.L85
+ 1104              	.L92:
+5890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1105              		.loc 1 5890 12 view .LVU354
+ 1106 0072 0120     		movs	r0, #1
+ 1107 0074 E7E7     		b	.L85
+ARM GAS  /tmp/ccVyGVF6.s 			page 157
+
+
+ 1108              	.L94:
+ 1109 0076 00BF     		.align	2
+ 1110              	.L93:
+ 1111 0078 00200080 		.word	-2147475456
+ 1112              		.cfi_endproc
+ 1113              	.LFE196:
+ 1115              		.section	.text.I2C_RequestMemoryRead,"ax",%progbits
+ 1116              		.align	1
+ 1117              		.syntax unified
+ 1118              		.thumb
+ 1119              		.thumb_func
+ 1120              		.fpu fpv5-d16
+ 1122              	I2C_RequestMemoryRead:
+ 1123              	.LVL95:
+ 1124              	.LFB197:
+5911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR
+ 1125              		.loc 1 5911 1 is_stmt 1 view -0
+ 1126              		.cfi_startproc
+ 1127              		@ args = 8, pretend = 0, frame = 0
+ 1128              		@ frame_needed = 0, uses_anonymous_args = 0
+5911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR
+ 1129              		.loc 1 5911 1 is_stmt 0 view .LVU356
+ 1130 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 1131              	.LCFI9:
+ 1132              		.cfi_def_cfa_offset 24
+ 1133              		.cfi_offset 4, -24
+ 1134              		.cfi_offset 5, -20
+ 1135              		.cfi_offset 6, -16
+ 1136              		.cfi_offset 7, -12
+ 1137              		.cfi_offset 8, -8
+ 1138              		.cfi_offset 14, -4
+ 1139 0004 82B0     		sub	sp, sp, #8
+ 1140              	.LCFI10:
+ 1141              		.cfi_def_cfa_offset 32
+ 1142 0006 0446     		mov	r4, r0
+ 1143 0008 9046     		mov	r8, r2
+ 1144 000a 1D46     		mov	r5, r3
+ 1145 000c 089E     		ldr	r6, [sp, #32]
+ 1146 000e 099F     		ldr	r7, [sp, #36]
+5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1147              		.loc 1 5912 3 is_stmt 1 view .LVU357
+ 1148 0010 184B     		ldr	r3, .L104
+ 1149              	.LVL96:
+5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1150              		.loc 1 5912 3 is_stmt 0 view .LVU358
+ 1151 0012 0093     		str	r3, [sp]
+ 1152 0014 0023     		movs	r3, #0
+ 1153 0016 EAB2     		uxtb	r2, r5
+ 1154              	.LVL97:
+5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1155              		.loc 1 5912 3 view .LVU359
+ 1156 0018 FFF7FEFF 		bl	I2C_TransferConfig
+ 1157              	.LVL98:
+5915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1158              		.loc 1 5915 3 is_stmt 1 view .LVU360
+5915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1159              		.loc 1 5915 7 is_stmt 0 view .LVU361
+ARM GAS  /tmp/ccVyGVF6.s 			page 158
+
+
+ 1160 001c 3A46     		mov	r2, r7
+ 1161 001e 3146     		mov	r1, r6
+ 1162 0020 2046     		mov	r0, r4
+ 1163 0022 FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 1164              	.LVL99:
+5915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1165              		.loc 1 5915 6 view .LVU362
+ 1166 0026 F8B9     		cbnz	r0, .L99
+5921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1167              		.loc 1 5921 3 is_stmt 1 view .LVU363
+5921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1168              		.loc 1 5921 6 is_stmt 0 view .LVU364
+ 1169 0028 012D     		cmp	r5, #1
+ 1170 002a 0ED1     		bne	.L97
+5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1171              		.loc 1 5924 5 is_stmt 1 view .LVU365
+5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1172              		.loc 1 5924 9 is_stmt 0 view .LVU366
+ 1173 002c 2368     		ldr	r3, [r4]
+5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1174              		.loc 1 5924 28 view .LVU367
+ 1175 002e 5FFA88F2 		uxtb	r2, r8
+5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1176              		.loc 1 5924 26 view .LVU368
+ 1177 0032 9A62     		str	r2, [r3, #40]
+ 1178              	.L98:
+5943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1179              		.loc 1 5943 3 is_stmt 1 view .LVU369
+5943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1180              		.loc 1 5943 7 is_stmt 0 view .LVU370
+ 1181 0034 0097     		str	r7, [sp]
+ 1182 0036 3346     		mov	r3, r6
+ 1183 0038 0022     		movs	r2, #0
+ 1184 003a 4021     		movs	r1, #64
+ 1185 003c 2046     		mov	r0, r4
+ 1186 003e FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 1187              	.LVL100:
+5943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1188              		.loc 1 5943 6 view .LVU371
+ 1189 0042 A8B9     		cbnz	r0, .L103
+ 1190              	.L96:
+5949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1191              		.loc 1 5949 1 view .LVU372
+ 1192 0044 02B0     		add	sp, sp, #8
+ 1193              	.LCFI11:
+ 1194              		.cfi_remember_state
+ 1195              		.cfi_def_cfa_offset 24
+ 1196              		@ sp needed
+ 1197 0046 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 1198              	.LVL101:
+ 1199              	.L97:
+ 1200              	.LCFI12:
+ 1201              		.cfi_restore_state
+5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1202              		.loc 1 5930 5 is_stmt 1 view .LVU373
+5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1203              		.loc 1 5930 9 is_stmt 0 view .LVU374
+ARM GAS  /tmp/ccVyGVF6.s 			page 159
+
+
+ 1204 004a 2368     		ldr	r3, [r4]
+5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1205              		.loc 1 5930 28 view .LVU375
+ 1206 004c 4FEA1822 		lsr	r2, r8, #8
+5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1207              		.loc 1 5930 26 view .LVU376
+ 1208 0050 9A62     		str	r2, [r3, #40]
+5933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1209              		.loc 1 5933 5 is_stmt 1 view .LVU377
+5933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1210              		.loc 1 5933 9 is_stmt 0 view .LVU378
+ 1211 0052 3A46     		mov	r2, r7
+ 1212 0054 3146     		mov	r1, r6
+ 1213 0056 2046     		mov	r0, r4
+ 1214 0058 FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 1215              	.LVL102:
+5933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1216              		.loc 1 5933 8 view .LVU379
+ 1217 005c 30B9     		cbnz	r0, .L100
+5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1218              		.loc 1 5939 5 is_stmt 1 view .LVU380
+5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1219              		.loc 1 5939 9 is_stmt 0 view .LVU381
+ 1220 005e 2368     		ldr	r3, [r4]
+5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1221              		.loc 1 5939 28 view .LVU382
+ 1222 0060 5FFA88F2 		uxtb	r2, r8
+5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1223              		.loc 1 5939 26 view .LVU383
+ 1224 0064 9A62     		str	r2, [r3, #40]
+ 1225 0066 E5E7     		b	.L98
+ 1226              	.L99:
+5917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1227              		.loc 1 5917 12 view .LVU384
+ 1228 0068 0120     		movs	r0, #1
+ 1229 006a EBE7     		b	.L96
+ 1230              	.L100:
+5935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 1231              		.loc 1 5935 14 view .LVU385
+ 1232 006c 0120     		movs	r0, #1
+ 1233 006e E9E7     		b	.L96
+ 1234              	.L103:
+5945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1235              		.loc 1 5945 12 view .LVU386
+ 1236 0070 0120     		movs	r0, #1
+ 1237 0072 E7E7     		b	.L96
+ 1238              	.L105:
+ 1239              		.align	2
+ 1240              	.L104:
+ 1241 0074 00200080 		.word	-2147475456
+ 1242              		.cfi_endproc
+ 1243              	.LFE197:
+ 1245              		.section	.text.I2C_WaitOnSTOPFlagUntilTimeout,"ax",%progbits
+ 1246              		.align	1
+ 1247              		.syntax unified
+ 1248              		.thumb
+ 1249              		.thumb_func
+ARM GAS  /tmp/ccVyGVF6.s 			page 160
+
+
+ 1250              		.fpu fpv5-d16
+ 1252              	I2C_WaitOnSTOPFlagUntilTimeout:
+ 1253              	.LVL103:
+ 1254              	.LFB215:
+7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ 1255              		.loc 1 7100 1 is_stmt 1 view -0
+ 1256              		.cfi_startproc
+ 1257              		@ args = 0, pretend = 0, frame = 0
+ 1258              		@ frame_needed = 0, uses_anonymous_args = 0
+7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ 1259              		.loc 1 7100 1 is_stmt 0 view .LVU388
+ 1260 0000 70B5     		push	{r4, r5, r6, lr}
+ 1261              	.LCFI13:
+ 1262              		.cfi_def_cfa_offset 16
+ 1263              		.cfi_offset 4, -16
+ 1264              		.cfi_offset 5, -12
+ 1265              		.cfi_offset 6, -8
+ 1266              		.cfi_offset 14, -4
+ 1267 0002 0446     		mov	r4, r0
+ 1268 0004 0D46     		mov	r5, r1
+ 1269 0006 1646     		mov	r6, r2
+7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1270              		.loc 1 7101 3 is_stmt 1 view .LVU389
+7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1271              		.loc 1 7101 9 is_stmt 0 view .LVU390
+ 1272 0008 04E0     		b	.L107
+ 1273              	.LVL104:
+ 1274              	.L109:
+7112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 1275              		.loc 1 7112 7 is_stmt 1 view .LVU391
+7112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 1276              		.loc 1 7112 12 is_stmt 0 view .LVU392
+ 1277 000a 2368     		ldr	r3, [r4]
+ 1278 000c 9B69     		ldr	r3, [r3, #24]
+7112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 1279              		.loc 1 7112 10 view .LVU393
+ 1280 000e 13F0200F 		tst	r3, #32
+ 1281 0012 12D0     		beq	.L113
+ 1282              	.L107:
+7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1283              		.loc 1 7101 9 is_stmt 1 view .LVU394
+7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1284              		.loc 1 7101 10 is_stmt 0 view .LVU395
+ 1285 0014 2368     		ldr	r3, [r4]
+ 1286 0016 9B69     		ldr	r3, [r3, #24]
+7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1287              		.loc 1 7101 9 view .LVU396
+ 1288 0018 13F0200F 		tst	r3, #32
+ 1289 001c 1BD1     		bne	.L114
+7104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1290              		.loc 1 7104 5 is_stmt 1 view .LVU397
+7104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1291              		.loc 1 7104 9 is_stmt 0 view .LVU398
+ 1292 001e 3246     		mov	r2, r6
+ 1293 0020 2946     		mov	r1, r5
+ 1294 0022 2046     		mov	r0, r4
+ 1295 0024 FFF7FEFF 		bl	I2C_IsErrorOccurred
+ARM GAS  /tmp/ccVyGVF6.s 			page 161
+
+
+ 1296              	.LVL105:
+7104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1297              		.loc 1 7104 8 view .LVU399
+ 1298 0028 B8B9     		cbnz	r0, .L111
+7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1299              		.loc 1 7110 5 is_stmt 1 view .LVU400
+7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1300              		.loc 1 7110 11 is_stmt 0 view .LVU401
+ 1301 002a FFF7FEFF 		bl	HAL_GetTick
+ 1302              	.LVL106:
+7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1303              		.loc 1 7110 25 view .LVU402
+ 1304 002e 801B     		subs	r0, r0, r6
+7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1305              		.loc 1 7110 8 view .LVU403
+ 1306 0030 A842     		cmp	r0, r5
+ 1307 0032 EAD8     		bhi	.L109
+7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1308              		.loc 1 7110 49 discriminator 1 view .LVU404
+ 1309 0034 002D     		cmp	r5, #0
+ 1310 0036 EDD1     		bne	.L107
+ 1311 0038 E7E7     		b	.L109
+ 1312              	.L113:
+7114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+ 1313              		.loc 1 7114 9 is_stmt 1 view .LVU405
+7114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+ 1314              		.loc 1 7114 25 is_stmt 0 view .LVU406
+ 1315 003a 636C     		ldr	r3, [r4, #68]
+ 1316 003c 43F02003 		orr	r3, r3, #32
+ 1317 0040 6364     		str	r3, [r4, #68]
+7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1318              		.loc 1 7115 9 is_stmt 1 view .LVU407
+7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1319              		.loc 1 7115 21 is_stmt 0 view .LVU408
+ 1320 0042 2023     		movs	r3, #32
+ 1321 0044 84F84130 		strb	r3, [r4, #65]
+7116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1322              		.loc 1 7116 9 is_stmt 1 view .LVU409
+7116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1323              		.loc 1 7116 20 is_stmt 0 view .LVU410
+ 1324 0048 0023     		movs	r3, #0
+ 1325 004a 84F84230 		strb	r3, [r4, #66]
+7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1326              		.loc 1 7119 9 is_stmt 1 view .LVU411
+7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1327              		.loc 1 7119 9 view .LVU412
+ 1328 004e 84F84030 		strb	r3, [r4, #64]
+7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1329              		.loc 1 7119 9 view .LVU413
+7121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 1330              		.loc 1 7121 9 view .LVU414
+7121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 1331              		.loc 1 7121 16 is_stmt 0 view .LVU415
+ 1332 0052 0120     		movs	r0, #1
+ 1333 0054 00E0     		b	.L108
+ 1334              	.L114:
+7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ARM GAS  /tmp/ccVyGVF6.s 			page 162
+
+
+ 1335              		.loc 1 7125 10 view .LVU416
+ 1336 0056 0020     		movs	r0, #0
+ 1337              	.L108:
+7126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1338              		.loc 1 7126 1 view .LVU417
+ 1339 0058 70BD     		pop	{r4, r5, r6, pc}
+ 1340              	.LVL107:
+ 1341              	.L111:
+7106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 1342              		.loc 1 7106 14 view .LVU418
+ 1343 005a 0120     		movs	r0, #1
+ 1344 005c FCE7     		b	.L108
+ 1345              		.cfi_endproc
+ 1346              	.LFE215:
+ 1348              		.section	.text.I2C_WaitOnRXNEFlagUntilTimeout,"ax",%progbits
+ 1349              		.align	1
+ 1350              		.syntax unified
+ 1351              		.thumb
+ 1352              		.thumb_func
+ 1353              		.fpu fpv5-d16
+ 1355              	I2C_WaitOnRXNEFlagUntilTimeout:
+ 1356              	.LVL108:
+ 1357              	.LFB216:
+7138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1358              		.loc 1 7138 1 is_stmt 1 view -0
+ 1359              		.cfi_startproc
+ 1360              		@ args = 0, pretend = 0, frame = 0
+ 1361              		@ frame_needed = 0, uses_anonymous_args = 0
+7138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1362              		.loc 1 7138 1 is_stmt 0 view .LVU420
+ 1363 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 1364              	.LCFI14:
+ 1365              		.cfi_def_cfa_offset 24
+ 1366              		.cfi_offset 3, -24
+ 1367              		.cfi_offset 4, -20
+ 1368              		.cfi_offset 5, -16
+ 1369              		.cfi_offset 6, -12
+ 1370              		.cfi_offset 7, -8
+ 1371              		.cfi_offset 14, -4
+ 1372 0002 0446     		mov	r4, r0
+ 1373 0004 0E46     		mov	r6, r1
+ 1374 0006 1746     		mov	r7, r2
+7139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1375              		.loc 1 7139 3 is_stmt 1 view .LVU421
+ 1376              	.LVL109:
+7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1377              		.loc 1 7141 3 view .LVU422
+7139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1378              		.loc 1 7139 21 is_stmt 0 view .LVU423
+ 1379 0008 0025     		movs	r5, #0
+7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1380              		.loc 1 7141 9 view .LVU424
+ 1381 000a 18E0     		b	.L116
+ 1382              	.LVL110:
+ 1383              	.L120:
+7183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 1384              		.loc 1 7183 9 is_stmt 1 view .LVU425
+ARM GAS  /tmp/ccVyGVF6.s 			page 163
+
+
+7183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 1385              		.loc 1 7183 25 is_stmt 0 view .LVU426
+ 1386 000c 0023     		movs	r3, #0
+ 1387 000e 6364     		str	r3, [r4, #68]
+ 1388              	.LVL111:
+ 1389              	.L118:
+7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1390              		.loc 1 7188 5 is_stmt 1 view .LVU427
+7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1391              		.loc 1 7188 12 is_stmt 0 view .LVU428
+ 1392 0010 FFF7FEFF 		bl	HAL_GetTick
+ 1393              	.LVL112:
+7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1394              		.loc 1 7188 26 view .LVU429
+ 1395 0014 C01B     		subs	r0, r0, r7
+7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1396              		.loc 1 7188 8 view .LVU430
+ 1397 0016 B042     		cmp	r0, r6
+ 1398 0018 00D8     		bhi	.L121
+7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1399              		.loc 1 7188 50 discriminator 2 view .LVU431
+ 1400 001a 86B9     		cbnz	r6, .L116
+ 1401              	.L121:
+7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1402              		.loc 1 7188 70 discriminator 3 view .LVU432
+ 1403 001c 7DB9     		cbnz	r5, .L116
+7190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 1404              		.loc 1 7190 7 is_stmt 1 view .LVU433
+7190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 1405              		.loc 1 7190 12 is_stmt 0 view .LVU434
+ 1406 001e 2368     		ldr	r3, [r4]
+ 1407 0020 9B69     		ldr	r3, [r3, #24]
+7190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 1408              		.loc 1 7190 10 view .LVU435
+ 1409 0022 13F0040F 		tst	r3, #4
+ 1410 0026 0AD1     		bne	.L116
+7192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+ 1411              		.loc 1 7192 9 is_stmt 1 view .LVU436
+7192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->State = HAL_I2C_STATE_READY;
+ 1412              		.loc 1 7192 25 is_stmt 0 view .LVU437
+ 1413 0028 636C     		ldr	r3, [r4, #68]
+ 1414 002a 43F02003 		orr	r3, r3, #32
+ 1415 002e 6364     		str	r3, [r4, #68]
+7193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1416              		.loc 1 7193 9 is_stmt 1 view .LVU438
+7193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1417              		.loc 1 7193 21 is_stmt 0 view .LVU439
+ 1418 0030 2023     		movs	r3, #32
+ 1419 0032 84F84130 		strb	r3, [r4, #65]
+7196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1420              		.loc 1 7196 9 is_stmt 1 view .LVU440
+7196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1421              		.loc 1 7196 9 view .LVU441
+ 1422 0036 0023     		movs	r3, #0
+ 1423 0038 84F84030 		strb	r3, [r4, #64]
+7196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1424              		.loc 1 7196 9 view .LVU442
+ARM GAS  /tmp/ccVyGVF6.s 			page 164
+
+
+7198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 1425              		.loc 1 7198 9 view .LVU443
+ 1426              	.LVL113:
+7198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 1427              		.loc 1 7198 16 is_stmt 0 view .LVU444
+ 1428 003c 0125     		movs	r5, #1
+ 1429              	.LVL114:
+ 1430              	.L116:
+7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1431              		.loc 1 7141 9 is_stmt 1 view .LVU445
+7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1432              		.loc 1 7141 11 is_stmt 0 view .LVU446
+ 1433 003e 2368     		ldr	r3, [r4]
+ 1434 0040 9B69     		ldr	r3, [r3, #24]
+7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1435              		.loc 1 7141 9 view .LVU447
+ 1436 0042 13F0040F 		tst	r3, #4
+ 1437 0046 2ED1     		bne	.L123
+7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1438              		.loc 1 7141 61 discriminator 1 view .LVU448
+ 1439 0048 6DBB     		cbnz	r5, .L123
+7144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1440              		.loc 1 7144 5 is_stmt 1 view .LVU449
+7144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1441              		.loc 1 7144 9 is_stmt 0 view .LVU450
+ 1442 004a 3A46     		mov	r2, r7
+ 1443 004c 3146     		mov	r1, r6
+ 1444 004e 2046     		mov	r0, r4
+ 1445 0050 FFF7FEFF 		bl	I2C_IsErrorOccurred
+ 1446              	.LVL115:
+7144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1447              		.loc 1 7144 8 view .LVU451
+ 1448 0054 00B1     		cbz	r0, .L117
+7146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 1449              		.loc 1 7146 14 view .LVU452
+ 1450 0056 0125     		movs	r5, #1
+ 1451              	.LVL116:
+ 1452              	.L117:
+7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1453              		.loc 1 7150 5 is_stmt 1 view .LVU453
+7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1454              		.loc 1 7150 10 is_stmt 0 view .LVU454
+ 1455 0058 2368     		ldr	r3, [r4]
+ 1456 005a 9A69     		ldr	r2, [r3, #24]
+7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1457              		.loc 1 7150 8 view .LVU455
+ 1458 005c 12F0200F 		tst	r2, #32
+ 1459 0060 D6D0     		beq	.L118
+7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1460              		.loc 1 7150 59 discriminator 1 view .LVU456
+ 1461 0062 002D     		cmp	r5, #0
+ 1462 0064 D4D1     		bne	.L118
+7154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 1463              		.loc 1 7154 7 is_stmt 1 view .LVU457
+7154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 1464              		.loc 1 7154 12 is_stmt 0 view .LVU458
+ 1465 0066 9A69     		ldr	r2, [r3, #24]
+ARM GAS  /tmp/ccVyGVF6.s 			page 165
+
+
+7162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 1466              		.loc 1 7162 7 is_stmt 1 view .LVU459
+7162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 1467              		.loc 1 7162 11 is_stmt 0 view .LVU460
+ 1468 0068 9A69     		ldr	r2, [r3, #24]
+7162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 1469              		.loc 1 7162 10 view .LVU461
+ 1470 006a 12F0100F 		tst	r2, #16
+ 1471 006e CDD0     		beq	.L120
+7164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ 1472              		.loc 1 7164 9 is_stmt 1 view .LVU462
+ 1473 0070 1022     		movs	r2, #16
+ 1474 0072 DA61     		str	r2, [r3, #28]
+7165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1475              		.loc 1 7165 9 view .LVU463
+7165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1476              		.loc 1 7165 25 is_stmt 0 view .LVU464
+ 1477 0074 0423     		movs	r3, #4
+ 1478 0076 6364     		str	r3, [r4, #68]
+7168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1479              		.loc 1 7168 9 is_stmt 1 view .LVU465
+ 1480 0078 2368     		ldr	r3, [r4]
+ 1481 007a 2022     		movs	r2, #32
+ 1482 007c DA61     		str	r2, [r3, #28]
+7171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1483              		.loc 1 7171 9 view .LVU466
+ 1484 007e 2168     		ldr	r1, [r4]
+ 1485 0080 4B68     		ldr	r3, [r1, #4]
+ 1486 0082 23F0FF73 		bic	r3, r3, #33423360
+ 1487 0086 23F48B33 		bic	r3, r3, #71168
+ 1488 008a 23F4FF73 		bic	r3, r3, #510
+ 1489 008e 23F00103 		bic	r3, r3, #1
+ 1490 0092 4B60     		str	r3, [r1, #4]
+7173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1491              		.loc 1 7173 9 view .LVU467
+7173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1492              		.loc 1 7173 21 is_stmt 0 view .LVU468
+ 1493 0094 84F84120 		strb	r2, [r4, #65]
+7174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1494              		.loc 1 7174 9 is_stmt 1 view .LVU469
+7174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1495              		.loc 1 7174 20 is_stmt 0 view .LVU470
+ 1496 0098 0023     		movs	r3, #0
+ 1497 009a 84F84230 		strb	r3, [r4, #66]
+7177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1498              		.loc 1 7177 9 is_stmt 1 view .LVU471
+7177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1499              		.loc 1 7177 9 view .LVU472
+ 1500 009e 84F84030 		strb	r3, [r4, #64]
+7177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1501              		.loc 1 7177 9 view .LVU473
+7179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 1502              		.loc 1 7179 9 view .LVU474
+ 1503              	.LVL117:
+7179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 1504              		.loc 1 7179 16 is_stmt 0 view .LVU475
+ 1505 00a2 0125     		movs	r5, #1
+ARM GAS  /tmp/ccVyGVF6.s 			page 166
+
+
+ 1506 00a4 B4E7     		b	.L118
+ 1507              	.LVL118:
+ 1508              	.L123:
+7202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 1509              		.loc 1 7202 3 is_stmt 1 view .LVU476
+7203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1510              		.loc 1 7203 1 is_stmt 0 view .LVU477
+ 1511 00a6 2846     		mov	r0, r5
+ 1512 00a8 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+7203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1513              		.loc 1 7203 1 view .LVU478
+ 1514              		.cfi_endproc
+ 1515              	.LFE216:
+ 1517              		.section	.text.HAL_I2C_MspInit,"ax",%progbits
+ 1518              		.align	1
+ 1519              		.weak	HAL_I2C_MspInit
+ 1520              		.syntax unified
+ 1521              		.thumb
+ 1522              		.thumb_func
+ 1523              		.fpu fpv5-d16
+ 1525              	HAL_I2C_MspInit:
+ 1526              	.LVL119:
+ 1527              	.LFB143:
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 1528              		.loc 1 697 1 is_stmt 1 view -0
+ 1529              		.cfi_startproc
+ 1530              		@ args = 0, pretend = 0, frame = 0
+ 1531              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1532              		@ link register save eliminated.
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1533              		.loc 1 699 3 view .LVU480
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1534              		.loc 1 704 1 is_stmt 0 view .LVU481
+ 1535 0000 7047     		bx	lr
+ 1536              		.cfi_endproc
+ 1537              	.LFE143:
+ 1539              		.section	.text.HAL_I2C_Init,"ax",%progbits
+ 1540              		.align	1
+ 1541              		.global	HAL_I2C_Init
+ 1542              		.syntax unified
+ 1543              		.thumb
+ 1544              		.thumb_func
+ 1545              		.fpu fpv5-d16
+ 1547              	HAL_I2C_Init:
+ 1548              	.LVL120:
+ 1549              	.LFB141:
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 1550              		.loc 1 536 1 is_stmt 1 view -0
+ 1551              		.cfi_startproc
+ 1552              		@ args = 0, pretend = 0, frame = 0
+ 1553              		@ frame_needed = 0, uses_anonymous_args = 0
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1554              		.loc 1 538 3 view .LVU483
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1555              		.loc 1 538 6 is_stmt 0 view .LVU484
+ 1556 0000 0028     		cmp	r0, #0
+ 1557 0002 5DD0     		beq	.L135
+ARM GAS  /tmp/ccVyGVF6.s 			page 167
+
+
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 1558              		.loc 1 536 1 view .LVU485
+ 1559 0004 10B5     		push	{r4, lr}
+ 1560              	.LCFI15:
+ 1561              		.cfi_def_cfa_offset 8
+ 1562              		.cfi_offset 4, -8
+ 1563              		.cfi_offset 14, -4
+ 1564 0006 0446     		mov	r4, r0
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+ 1565              		.loc 1 544 3 is_stmt 1 view .LVU486
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+ 1566              		.loc 1 545 3 view .LVU487
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+ 1567              		.loc 1 546 3 view .LVU488
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ 1568              		.loc 1 547 3 view .LVU489
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+ 1569              		.loc 1 548 3 view .LVU490
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ 1570              		.loc 1 549 3 view .LVU491
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+ 1571              		.loc 1 550 3 view .LVU492
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1572              		.loc 1 551 3 view .LVU493
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1573              		.loc 1 553 3 view .LVU494
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1574              		.loc 1 553 11 is_stmt 0 view .LVU495
+ 1575 0008 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1576              		.loc 1 553 6 view .LVU496
+ 1577 000c 002B     		cmp	r3, #0
+ 1578 000e 46D0     		beq	.L140
+ 1579              	.LVL121:
+ 1580              	.L130:
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1581              		.loc 1 584 3 is_stmt 1 view .LVU497
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1582              		.loc 1 584 15 is_stmt 0 view .LVU498
+ 1583 0010 2423     		movs	r3, #36
+ 1584 0012 84F84130 		strb	r3, [r4, #65]
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1585              		.loc 1 587 3 is_stmt 1 view .LVU499
+ 1586 0016 2268     		ldr	r2, [r4]
+ 1587 0018 1368     		ldr	r3, [r2]
+ 1588 001a 23F00103 		bic	r3, r3, #1
+ 1589 001e 1360     		str	r3, [r2]
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1590              		.loc 1 591 3 view .LVU500
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1591              		.loc 1 591 39 is_stmt 0 view .LVU501
+ 1592 0020 6368     		ldr	r3, [r4, #4]
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1593              		.loc 1 591 7 view .LVU502
+ 1594 0022 2268     		ldr	r2, [r4]
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1595              		.loc 1 591 47 view .LVU503
+ARM GAS  /tmp/ccVyGVF6.s 			page 168
+
+
+ 1596 0024 23F07063 		bic	r3, r3, #251658240
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1597              		.loc 1 591 27 view .LVU504
+ 1598 0028 1361     		str	r3, [r2, #16]
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1599              		.loc 1 595 3 is_stmt 1 view .LVU505
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1600              		.loc 1 595 7 is_stmt 0 view .LVU506
+ 1601 002a 2268     		ldr	r2, [r4]
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1602              		.loc 1 595 24 view .LVU507
+ 1603 002c 9368     		ldr	r3, [r2, #8]
+ 1604 002e 23F40043 		bic	r3, r3, #32768
+ 1605 0032 9360     		str	r3, [r2, #8]
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1606              		.loc 1 598 3 is_stmt 1 view .LVU508
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1607              		.loc 1 598 17 is_stmt 0 view .LVU509
+ 1608 0034 E368     		ldr	r3, [r4, #12]
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1609              		.loc 1 598 6 view .LVU510
+ 1610 0036 012B     		cmp	r3, #1
+ 1611 0038 36D0     		beq	.L141
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1612              		.loc 1 604 5 is_stmt 1 view .LVU511
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1613              		.loc 1 604 75 is_stmt 0 view .LVU512
+ 1614 003a A368     		ldr	r3, [r4, #8]
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1615              		.loc 1 604 9 view .LVU513
+ 1616 003c 2268     		ldr	r2, [r4]
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1617              		.loc 1 604 63 view .LVU514
+ 1618 003e 43F40443 		orr	r3, r3, #33792
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1619              		.loc 1 604 26 view .LVU515
+ 1620 0042 9360     		str	r3, [r2, #8]
+ 1621              	.L132:
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1622              		.loc 1 609 3 is_stmt 1 view .LVU516
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1623              		.loc 1 609 17 is_stmt 0 view .LVU517
+ 1624 0044 E368     		ldr	r3, [r4, #12]
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1625              		.loc 1 609 6 view .LVU518
+ 1626 0046 022B     		cmp	r3, #2
+ 1627 0048 34D0     		beq	.L142
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1628              		.loc 1 616 5 is_stmt 1 view .LVU519
+ 1629 004a 2268     		ldr	r2, [r4]
+ 1630 004c 5368     		ldr	r3, [r2, #4]
+ 1631 004e 23F40063 		bic	r3, r3, #2048
+ 1632 0052 5360     		str	r3, [r2, #4]
+ 1633              	.L134:
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1634              		.loc 1 619 3 view .LVU520
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 169
+
+
+ 1635              		.loc 1 619 7 is_stmt 0 view .LVU521
+ 1636 0054 2268     		ldr	r2, [r4]
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1637              		.loc 1 619 23 view .LVU522
+ 1638 0056 5168     		ldr	r1, [r2, #4]
+ 1639 0058 1A4B     		ldr	r3, .L143
+ 1640 005a 0B43     		orrs	r3, r3, r1
+ 1641 005c 5360     		str	r3, [r2, #4]
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1642              		.loc 1 623 3 is_stmt 1 view .LVU523
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1643              		.loc 1 623 7 is_stmt 0 view .LVU524
+ 1644 005e 2268     		ldr	r2, [r4]
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1645              		.loc 1 623 24 view .LVU525
+ 1646 0060 D368     		ldr	r3, [r2, #12]
+ 1647 0062 23F40043 		bic	r3, r3, #32768
+ 1648 0066 D360     		str	r3, [r2, #12]
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1649              		.loc 1 626 3 is_stmt 1 view .LVU526
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1650              		.loc 1 626 37 is_stmt 0 view .LVU527
+ 1651 0068 2369     		ldr	r3, [r4, #16]
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1652              		.loc 1 626 66 view .LVU528
+ 1653 006a 6269     		ldr	r2, [r4, #20]
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1654              		.loc 1 626 54 view .LVU529
+ 1655 006c 1343     		orrs	r3, r3, r2
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1656              		.loc 1 627 38 view .LVU530
+ 1657 006e A169     		ldr	r1, [r4, #24]
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1658              		.loc 1 626 7 view .LVU531
+ 1659 0070 2268     		ldr	r2, [r4]
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1660              		.loc 1 626 79 view .LVU532
+ 1661 0072 43EA0123 		orr	r3, r3, r1, lsl #8
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                           (hi2c->Init.OwnAddress2Masks << 8));
+ 1662              		.loc 1 626 24 view .LVU533
+ 1663 0076 D360     		str	r3, [r2, #12]
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1664              		.loc 1 631 3 is_stmt 1 view .LVU534
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1665              		.loc 1 631 36 is_stmt 0 view .LVU535
+ 1666 0078 E369     		ldr	r3, [r4, #28]
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1667              		.loc 1 631 65 view .LVU536
+ 1668 007a 216A     		ldr	r1, [r4, #32]
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1669              		.loc 1 631 7 view .LVU537
+ 1670 007c 2268     		ldr	r2, [r4]
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1671              		.loc 1 631 53 view .LVU538
+ 1672 007e 0B43     		orrs	r3, r3, r1
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1673              		.loc 1 631 23 view .LVU539
+ARM GAS  /tmp/ccVyGVF6.s 			page 170
+
+
+ 1674 0080 1360     		str	r3, [r2]
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1675              		.loc 1 634 3 is_stmt 1 view .LVU540
+ 1676 0082 2268     		ldr	r2, [r4]
+ 1677 0084 1368     		ldr	r3, [r2]
+ 1678 0086 43F00103 		orr	r3, r3, #1
+ 1679 008a 1360     		str	r3, [r2]
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+ 1680              		.loc 1 636 3 view .LVU541
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+ 1681              		.loc 1 636 19 is_stmt 0 view .LVU542
+ 1682 008c 0020     		movs	r0, #0
+ 1683 008e 6064     		str	r0, [r4, #68]
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 1684              		.loc 1 637 3 is_stmt 1 view .LVU543
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 1685              		.loc 1 637 15 is_stmt 0 view .LVU544
+ 1686 0090 2023     		movs	r3, #32
+ 1687 0092 84F84130 		strb	r3, [r4, #65]
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1688              		.loc 1 638 3 is_stmt 1 view .LVU545
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1689              		.loc 1 638 23 is_stmt 0 view .LVU546
+ 1690 0096 2063     		str	r0, [r4, #48]
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1691              		.loc 1 639 3 is_stmt 1 view .LVU547
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1692              		.loc 1 639 14 is_stmt 0 view .LVU548
+ 1693 0098 84F84200 		strb	r0, [r4, #66]
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 1694              		.loc 1 641 3 is_stmt 1 view .LVU549
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1695              		.loc 1 642 1 is_stmt 0 view .LVU550
+ 1696 009c 10BD     		pop	{r4, pc}
+ 1697              	.LVL122:
+ 1698              	.L140:
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1699              		.loc 1 556 5 is_stmt 1 view .LVU551
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1700              		.loc 1 556 16 is_stmt 0 view .LVU552
+ 1701 009e 80F84030 		strb	r3, [r0, #64]
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 1702              		.loc 1 580 5 is_stmt 1 view .LVU553
+ 1703 00a2 FFF7FEFF 		bl	HAL_I2C_MspInit
+ 1704              	.LVL123:
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 1705              		.loc 1 580 5 is_stmt 0 view .LVU554
+ 1706 00a6 B3E7     		b	.L130
+ 1707              	.L141:
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1708              		.loc 1 600 5 is_stmt 1 view .LVU555
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1709              		.loc 1 600 56 is_stmt 0 view .LVU556
+ 1710 00a8 A368     		ldr	r3, [r4, #8]
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1711              		.loc 1 600 9 view .LVU557
+ 1712 00aa 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/ccVyGVF6.s 			page 171
+
+
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1713              		.loc 1 600 44 view .LVU558
+ 1714 00ac 43F40043 		orr	r3, r3, #32768
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1715              		.loc 1 600 26 view .LVU559
+ 1716 00b0 9360     		str	r3, [r2, #8]
+ 1717 00b2 C7E7     		b	.L132
+ 1718              	.L142:
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1719              		.loc 1 611 5 is_stmt 1 view .LVU560
+ 1720 00b4 2268     		ldr	r2, [r4]
+ 1721 00b6 5368     		ldr	r3, [r2, #4]
+ 1722 00b8 43F40063 		orr	r3, r3, #2048
+ 1723 00bc 5360     		str	r3, [r2, #4]
+ 1724 00be C9E7     		b	.L134
+ 1725              	.LVL124:
+ 1726              	.L135:
+ 1727              	.LCFI16:
+ 1728              		.cfi_def_cfa_offset 0
+ 1729              		.cfi_restore 4
+ 1730              		.cfi_restore 14
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1731              		.loc 1 540 12 is_stmt 0 view .LVU561
+ 1732 00c0 0120     		movs	r0, #1
+ 1733              	.LVL125:
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1734              		.loc 1 642 1 view .LVU562
+ 1735 00c2 7047     		bx	lr
+ 1736              	.L144:
+ 1737              		.align	2
+ 1738              	.L143:
+ 1739 00c4 00800002 		.word	33587200
+ 1740              		.cfi_endproc
+ 1741              	.LFE141:
+ 1743              		.section	.text.HAL_I2C_MspDeInit,"ax",%progbits
+ 1744              		.align	1
+ 1745              		.weak	HAL_I2C_MspDeInit
+ 1746              		.syntax unified
+ 1747              		.thumb
+ 1748              		.thumb_func
+ 1749              		.fpu fpv5-d16
+ 1751              	HAL_I2C_MspDeInit:
+ 1752              	.LVL126:
+ 1753              	.LFB144:
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 1754              		.loc 1 713 1 is_stmt 1 view -0
+ 1755              		.cfi_startproc
+ 1756              		@ args = 0, pretend = 0, frame = 0
+ 1757              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1758              		@ link register save eliminated.
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1759              		.loc 1 715 3 view .LVU564
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1760              		.loc 1 720 1 is_stmt 0 view .LVU565
+ 1761 0000 7047     		bx	lr
+ 1762              		.cfi_endproc
+ 1763              	.LFE144:
+ARM GAS  /tmp/ccVyGVF6.s 			page 172
+
+
+ 1765              		.section	.text.HAL_I2C_DeInit,"ax",%progbits
+ 1766              		.align	1
+ 1767              		.global	HAL_I2C_DeInit
+ 1768              		.syntax unified
+ 1769              		.thumb
+ 1770              		.thumb_func
+ 1771              		.fpu fpv5-d16
+ 1773              	HAL_I2C_DeInit:
+ 1774              	.LVL127:
+ 1775              	.LFB142:
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 1776              		.loc 1 651 1 is_stmt 1 view -0
+ 1777              		.cfi_startproc
+ 1778              		@ args = 0, pretend = 0, frame = 0
+ 1779              		@ frame_needed = 0, uses_anonymous_args = 0
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1780              		.loc 1 653 3 view .LVU567
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1781              		.loc 1 653 6 is_stmt 0 view .LVU568
+ 1782 0000 A8B1     		cbz	r0, .L148
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the I2C handle allocation */
+ 1783              		.loc 1 651 1 view .LVU569
+ 1784 0002 10B5     		push	{r4, lr}
+ 1785              	.LCFI17:
+ 1786              		.cfi_def_cfa_offset 8
+ 1787              		.cfi_offset 4, -8
+ 1788              		.cfi_offset 14, -4
+ 1789 0004 0446     		mov	r4, r0
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1790              		.loc 1 659 3 is_stmt 1 view .LVU570
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1791              		.loc 1 661 3 view .LVU571
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1792              		.loc 1 661 15 is_stmt 0 view .LVU572
+ 1793 0006 2423     		movs	r3, #36
+ 1794 0008 80F84130 		strb	r3, [r0, #65]
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1795              		.loc 1 664 3 is_stmt 1 view .LVU573
+ 1796 000c 0268     		ldr	r2, [r0]
+ 1797 000e 1368     		ldr	r3, [r2]
+ 1798 0010 23F00103 		bic	r3, r3, #1
+ 1799 0014 1360     		str	r3, [r2]
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 1800              		.loc 1 676 3 view .LVU574
+ 1801 0016 FFF7FEFF 		bl	HAL_I2C_MspDeInit
+ 1802              	.LVL128:
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_RESET;
+ 1803              		.loc 1 679 3 view .LVU575
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_RESET;
+ 1804              		.loc 1 679 19 is_stmt 0 view .LVU576
+ 1805 001a 0020     		movs	r0, #0
+ 1806 001c 6064     		str	r0, [r4, #68]
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 1807              		.loc 1 680 3 is_stmt 1 view .LVU577
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 1808              		.loc 1 680 15 is_stmt 0 view .LVU578
+ 1809 001e 84F84100 		strb	r0, [r4, #65]
+ARM GAS  /tmp/ccVyGVF6.s 			page 173
+
+
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1810              		.loc 1 681 3 is_stmt 1 view .LVU579
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 1811              		.loc 1 681 23 is_stmt 0 view .LVU580
+ 1812 0022 2063     		str	r0, [r4, #48]
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1813              		.loc 1 682 3 is_stmt 1 view .LVU581
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1814              		.loc 1 682 14 is_stmt 0 view .LVU582
+ 1815 0024 84F84200 		strb	r0, [r4, #66]
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1816              		.loc 1 685 3 is_stmt 1 view .LVU583
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1817              		.loc 1 685 3 view .LVU584
+ 1818 0028 84F84000 		strb	r0, [r4, #64]
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1819              		.loc 1 685 3 view .LVU585
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 1820              		.loc 1 687 3 view .LVU586
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1821              		.loc 1 688 1 is_stmt 0 view .LVU587
+ 1822 002c 10BD     		pop	{r4, pc}
+ 1823              	.LVL129:
+ 1824              	.L148:
+ 1825              	.LCFI18:
+ 1826              		.cfi_def_cfa_offset 0
+ 1827              		.cfi_restore 4
+ 1828              		.cfi_restore 14
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 1829              		.loc 1 655 12 view .LVU588
+ 1830 002e 0120     		movs	r0, #1
+ 1831              	.LVL130:
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1832              		.loc 1 688 1 view .LVU589
+ 1833 0030 7047     		bx	lr
+ 1834              		.cfi_endproc
+ 1835              	.LFE142:
+ 1837              		.section	.text.HAL_I2C_Master_Transmit,"ax",%progbits
+ 1838              		.align	1
+ 1839              		.global	HAL_I2C_Master_Transmit
+ 1840              		.syntax unified
+ 1841              		.thumb
+ 1842              		.thumb_func
+ 1843              		.fpu fpv5-d16
+ 1845              	HAL_I2C_Master_Transmit:
+ 1846              	.LVL131:
+ 1847              	.LFB145:
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 1848              		.loc 1 1121 1 is_stmt 1 view -0
+ 1849              		.cfi_startproc
+ 1850              		@ args = 4, pretend = 0, frame = 0
+ 1851              		@ frame_needed = 0, uses_anonymous_args = 0
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 1852              		.loc 1 1121 1 is_stmt 0 view .LVU591
+ 1853 0000 2DE9F047 		push	{r4, r5, r6, r7, r8, r9, r10, lr}
+ 1854              	.LCFI19:
+ 1855              		.cfi_def_cfa_offset 32
+ARM GAS  /tmp/ccVyGVF6.s 			page 174
+
+
+ 1856              		.cfi_offset 4, -32
+ 1857              		.cfi_offset 5, -28
+ 1858              		.cfi_offset 6, -24
+ 1859              		.cfi_offset 7, -20
+ 1860              		.cfi_offset 8, -16
+ 1861              		.cfi_offset 9, -12
+ 1862              		.cfi_offset 10, -8
+ 1863              		.cfi_offset 14, -4
+ 1864 0004 82B0     		sub	sp, sp, #8
+ 1865              	.LCFI20:
+ 1866              		.cfi_def_cfa_offset 40
+ 1867 0006 0F46     		mov	r7, r1
+ 1868 0008 0A9E     		ldr	r6, [sp, #40]
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 1869              		.loc 1 1122 3 is_stmt 1 view .LVU592
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1870              		.loc 1 1123 3 view .LVU593
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1871              		.loc 1 1125 3 view .LVU594
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1872              		.loc 1 1125 11 is_stmt 0 view .LVU595
+ 1873 000a 90F84110 		ldrb	r1, [r0, #65]	@ zero_extendqisi2
+ 1874              	.LVL132:
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1875              		.loc 1 1125 11 view .LVU596
+ 1876 000e C9B2     		uxtb	r1, r1
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 1877              		.loc 1 1125 6 view .LVU597
+ 1878 0010 2029     		cmp	r1, #32
+ 1879 0012 40F0B780 		bne	.L163
+ 1880 0016 0446     		mov	r4, r0
+ 1881 0018 9046     		mov	r8, r2
+ 1882 001a 9946     		mov	r9, r3
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1883              		.loc 1 1128 5 is_stmt 1 view .LVU598
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1884              		.loc 1 1128 5 view .LVU599
+ 1885 001c 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 1886              	.LVL133:
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1887              		.loc 1 1128 5 is_stmt 0 view .LVU600
+ 1888 0020 012B     		cmp	r3, #1
+ 1889 0022 00F0B380 		beq	.L164
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1890              		.loc 1 1128 5 is_stmt 1 discriminator 2 view .LVU601
+ 1891 0026 4FF0010A 		mov	r10, #1
+ 1892 002a 80F840A0 		strb	r10, [r0, #64]
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1893              		.loc 1 1128 5 discriminator 2 view .LVU602
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1894              		.loc 1 1131 5 discriminator 2 view .LVU603
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1895              		.loc 1 1131 17 is_stmt 0 discriminator 2 view .LVU604
+ 1896 002e FFF7FEFF 		bl	HAL_GetTick
+ 1897              	.LVL134:
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1898              		.loc 1 1131 17 discriminator 2 view .LVU605
+ARM GAS  /tmp/ccVyGVF6.s 			page 175
+
+
+ 1899 0032 0546     		mov	r5, r0
+ 1900              	.LVL135:
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1901              		.loc 1 1133 5 is_stmt 1 discriminator 2 view .LVU606
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1902              		.loc 1 1133 9 is_stmt 0 discriminator 2 view .LVU607
+ 1903 0034 0090     		str	r0, [sp]
+ 1904 0036 1923     		movs	r3, #25
+ 1905 0038 5246     		mov	r2, r10
+ 1906 003a 4FF40041 		mov	r1, #32768
+ 1907 003e 2046     		mov	r0, r4
+ 1908              	.LVL136:
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1909              		.loc 1 1133 9 discriminator 2 view .LVU608
+ 1910 0040 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 1911              	.LVL137:
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1912              		.loc 1 1133 8 discriminator 2 view .LVU609
+ 1913 0044 0028     		cmp	r0, #0
+ 1914 0046 40F0A380 		bne	.L165
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 1915              		.loc 1 1138 5 is_stmt 1 view .LVU610
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 1916              		.loc 1 1138 21 is_stmt 0 view .LVU611
+ 1917 004a 2123     		movs	r3, #33
+ 1918 004c 84F84130 		strb	r3, [r4, #65]
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 1919              		.loc 1 1139 5 is_stmt 1 view .LVU612
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 1920              		.loc 1 1139 21 is_stmt 0 view .LVU613
+ 1921 0050 1023     		movs	r3, #16
+ 1922 0052 84F84230 		strb	r3, [r4, #66]
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1923              		.loc 1 1140 5 is_stmt 1 view .LVU614
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1924              		.loc 1 1140 21 is_stmt 0 view .LVU615
+ 1925 0056 0023     		movs	r3, #0
+ 1926 0058 6364     		str	r3, [r4, #68]
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 1927              		.loc 1 1143 5 is_stmt 1 view .LVU616
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 1928              		.loc 1 1143 21 is_stmt 0 view .LVU617
+ 1929 005a C4F82480 		str	r8, [r4, #36]
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 1930              		.loc 1 1144 5 is_stmt 1 view .LVU618
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 1931              		.loc 1 1144 21 is_stmt 0 view .LVU619
+ 1932 005e A4F82A90 		strh	r9, [r4, #42]	@ movhi
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1933              		.loc 1 1145 5 is_stmt 1 view .LVU620
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1934              		.loc 1 1145 21 is_stmt 0 view .LVU621
+ 1935 0062 6363     		str	r3, [r4, #52]
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1936              		.loc 1 1147 5 is_stmt 1 view .LVU622
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1937              		.loc 1 1147 13 is_stmt 0 view .LVU623
+ARM GAS  /tmp/ccVyGVF6.s 			page 176
+
+
+ 1938 0064 638D     		ldrh	r3, [r4, #42]
+ 1939 0066 9BB2     		uxth	r3, r3
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1940              		.loc 1 1147 8 view .LVU624
+ 1941 0068 FF2B     		cmp	r3, #255
+ 1942 006a 1ED9     		bls	.L155
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 1943              		.loc 1 1149 7 is_stmt 1 view .LVU625
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 1944              		.loc 1 1149 22 is_stmt 0 view .LVU626
+ 1945 006c FF23     		movs	r3, #255
+ 1946 006e 2385     		strh	r3, [r4, #40]	@ movhi
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 1947              		.loc 1 1150 7 is_stmt 1 view .LVU627
+ 1948              	.LVL138:
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 1949              		.loc 1 1150 16 is_stmt 0 view .LVU628
+ 1950 0070 4FF08073 		mov	r3, #16777216
+ 1951              	.LVL139:
+ 1952              	.L156:
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1953              		.loc 1 1158 5 is_stmt 1 view .LVU629
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1954              		.loc 1 1158 13 is_stmt 0 view .LVU630
+ 1955 0074 228D     		ldrh	r2, [r4, #40]
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 1956              		.loc 1 1158 8 view .LVU631
+ 1957 0076 EAB1     		cbz	r2, .L157
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1958              		.loc 1 1162 7 is_stmt 1 view .LVU632
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1959              		.loc 1 1162 11 is_stmt 0 view .LVU633
+ 1960 0078 2268     		ldr	r2, [r4]
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1961              		.loc 1 1162 30 view .LVU634
+ 1962 007a 98F80010 		ldrb	r1, [r8]	@ zero_extendqisi2
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1963              		.loc 1 1162 28 view .LVU635
+ 1964 007e 9162     		str	r1, [r2, #40]
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1965              		.loc 1 1165 7 is_stmt 1 view .LVU636
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1966              		.loc 1 1165 11 is_stmt 0 view .LVU637
+ 1967 0080 626A     		ldr	r2, [r4, #36]
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1968              		.loc 1 1165 21 view .LVU638
+ 1969 0082 0132     		adds	r2, r2, #1
+ 1970 0084 6262     		str	r2, [r4, #36]
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 1971              		.loc 1 1167 7 is_stmt 1 view .LVU639
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 1972              		.loc 1 1167 11 is_stmt 0 view .LVU640
+ 1973 0086 628D     		ldrh	r2, [r4, #42]
+ 1974 0088 92B2     		uxth	r2, r2
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 1975              		.loc 1 1167 22 view .LVU641
+ 1976 008a 013A     		subs	r2, r2, #1
+ARM GAS  /tmp/ccVyGVF6.s 			page 177
+
+
+ 1977 008c 92B2     		uxth	r2, r2
+ 1978 008e 6285     		strh	r2, [r4, #42]	@ movhi
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1979              		.loc 1 1168 7 is_stmt 1 view .LVU642
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1980              		.loc 1 1168 11 is_stmt 0 view .LVU643
+ 1981 0090 228D     		ldrh	r2, [r4, #40]
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 1982              		.loc 1 1168 21 view .LVU644
+ 1983 0092 013A     		subs	r2, r2, #1
+ 1984 0094 92B2     		uxth	r2, r2
+ 1985 0096 2285     		strh	r2, [r4, #40]	@ movhi
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 1986              		.loc 1 1172 7 is_stmt 1 view .LVU645
+ 1987 0098 0132     		adds	r2, r2, #1
+ 1988 009a 4149     		ldr	r1, .L171
+ 1989 009c 0091     		str	r1, [sp]
+ 1990 009e D2B2     		uxtb	r2, r2
+ 1991 00a0 3946     		mov	r1, r7
+ 1992 00a2 2046     		mov	r0, r4
+ 1993 00a4 FFF7FEFF 		bl	I2C_TransferConfig
+ 1994              	.LVL140:
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 1995              		.loc 1 1172 7 is_stmt 0 view .LVU646
+ 1996 00a8 18E0     		b	.L159
+ 1997              	.L155:
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 1998              		.loc 1 1154 7 is_stmt 1 view .LVU647
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 1999              		.loc 1 1154 28 is_stmt 0 view .LVU648
+ 2000 00aa 638D     		ldrh	r3, [r4, #42]
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 2001              		.loc 1 1154 22 view .LVU649
+ 2002 00ac 2385     		strh	r3, [r4, #40]	@ movhi
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2003              		.loc 1 1155 7 is_stmt 1 view .LVU650
+ 2004              	.LVL141:
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2005              		.loc 1 1155 16 is_stmt 0 view .LVU651
+ 2006 00ae 4FF00073 		mov	r3, #33554432
+ 2007 00b2 DFE7     		b	.L156
+ 2008              	.LVL142:
+ 2009              	.L157:
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 2010              		.loc 1 1179 7 is_stmt 1 view .LVU652
+ 2011 00b4 3A49     		ldr	r1, .L171
+ 2012 00b6 0091     		str	r1, [sp]
+ 2013 00b8 D2B2     		uxtb	r2, r2
+ 2014 00ba 3946     		mov	r1, r7
+ 2015 00bc 2046     		mov	r0, r4
+ 2016 00be FFF7FEFF 		bl	I2C_TransferConfig
+ 2017              	.LVL143:
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 2018              		.loc 1 1179 7 is_stmt 0 view .LVU653
+ 2019 00c2 0BE0     		b	.L159
+ 2020              	.L161:
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ARM GAS  /tmp/ccVyGVF6.s 			page 178
+
+
+ 2021              		.loc 1 1215 11 is_stmt 1 view .LVU654
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2022              		.loc 1 1215 32 is_stmt 0 view .LVU655
+ 2023 00c4 628D     		ldrh	r2, [r4, #42]
+ 2024 00c6 92B2     		uxth	r2, r2
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2025              		.loc 1 1215 26 view .LVU656
+ 2026 00c8 2285     		strh	r2, [r4, #40]	@ movhi
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 2027              		.loc 1 1216 11 is_stmt 1 view .LVU657
+ 2028 00ca 0023     		movs	r3, #0
+ 2029 00cc 0093     		str	r3, [sp]
+ 2030 00ce 4FF00073 		mov	r3, #33554432
+ 2031 00d2 D2B2     		uxtb	r2, r2
+ 2032 00d4 3946     		mov	r1, r7
+ 2033 00d6 2046     		mov	r0, r4
+ 2034 00d8 FFF7FEFF 		bl	I2C_TransferConfig
+ 2035              	.LVL144:
+ 2036              	.L159:
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2037              		.loc 1 1183 11 view .LVU658
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2038              		.loc 1 1183 16 is_stmt 0 view .LVU659
+ 2039 00dc 638D     		ldrh	r3, [r4, #42]
+ 2040 00de 9BB2     		uxth	r3, r3
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2041              		.loc 1 1183 11 view .LVU660
+ 2042 00e0 002B     		cmp	r3, #0
+ 2043 00e2 33D0     		beq	.L170
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2044              		.loc 1 1186 7 is_stmt 1 view .LVU661
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2045              		.loc 1 1186 11 is_stmt 0 view .LVU662
+ 2046 00e4 2A46     		mov	r2, r5
+ 2047 00e6 3146     		mov	r1, r6
+ 2048 00e8 2046     		mov	r0, r4
+ 2049 00ea FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 2050              	.LVL145:
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2051              		.loc 1 1186 10 view .LVU663
+ 2052 00ee 0028     		cmp	r0, #0
+ 2053 00f0 50D1     		bne	.L166
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2054              		.loc 1 1191 7 is_stmt 1 view .LVU664
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2055              		.loc 1 1191 35 is_stmt 0 view .LVU665
+ 2056 00f2 626A     		ldr	r2, [r4, #36]
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2057              		.loc 1 1191 11 view .LVU666
+ 2058 00f4 2368     		ldr	r3, [r4]
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2059              		.loc 1 1191 30 view .LVU667
+ 2060 00f6 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2061              		.loc 1 1191 28 view .LVU668
+ 2062 00f8 9A62     		str	r2, [r3, #40]
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 179
+
+
+ 2063              		.loc 1 1194 7 is_stmt 1 view .LVU669
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2064              		.loc 1 1194 11 is_stmt 0 view .LVU670
+ 2065 00fa 636A     		ldr	r3, [r4, #36]
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2066              		.loc 1 1194 21 view .LVU671
+ 2067 00fc 0133     		adds	r3, r3, #1
+ 2068 00fe 6362     		str	r3, [r4, #36]
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 2069              		.loc 1 1196 7 is_stmt 1 view .LVU672
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 2070              		.loc 1 1196 11 is_stmt 0 view .LVU673
+ 2071 0100 638D     		ldrh	r3, [r4, #42]
+ 2072 0102 9BB2     		uxth	r3, r3
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 2073              		.loc 1 1196 22 view .LVU674
+ 2074 0104 013B     		subs	r3, r3, #1
+ 2075 0106 9BB2     		uxth	r3, r3
+ 2076 0108 6385     		strh	r3, [r4, #42]	@ movhi
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2077              		.loc 1 1197 7 is_stmt 1 view .LVU675
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2078              		.loc 1 1197 11 is_stmt 0 view .LVU676
+ 2079 010a 238D     		ldrh	r3, [r4, #40]
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2080              		.loc 1 1197 21 view .LVU677
+ 2081 010c 013B     		subs	r3, r3, #1
+ 2082 010e 9BB2     		uxth	r3, r3
+ 2083 0110 2385     		strh	r3, [r4, #40]	@ movhi
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2084              		.loc 1 1199 7 is_stmt 1 view .LVU678
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2085              		.loc 1 1199 16 is_stmt 0 view .LVU679
+ 2086 0112 628D     		ldrh	r2, [r4, #42]
+ 2087 0114 92B2     		uxth	r2, r2
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2088              		.loc 1 1199 10 view .LVU680
+ 2089 0116 002A     		cmp	r2, #0
+ 2090 0118 E0D0     		beq	.L159
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2091              		.loc 1 1199 35 discriminator 1 view .LVU681
+ 2092 011a 002B     		cmp	r3, #0
+ 2093 011c DED1     		bne	.L159
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2094              		.loc 1 1202 9 is_stmt 1 view .LVU682
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2095              		.loc 1 1202 13 is_stmt 0 view .LVU683
+ 2096 011e 0095     		str	r5, [sp]
+ 2097 0120 3346     		mov	r3, r6
+ 2098 0122 0022     		movs	r2, #0
+ 2099 0124 8021     		movs	r1, #128
+ 2100 0126 2046     		mov	r0, r4
+ 2101 0128 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2102              	.LVL146:
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2103              		.loc 1 1202 12 view .LVU684
+ 2104 012c A0BB     		cbnz	r0, .L167
+ARM GAS  /tmp/ccVyGVF6.s 			page 180
+
+
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2105              		.loc 1 1207 9 is_stmt 1 view .LVU685
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2106              		.loc 1 1207 17 is_stmt 0 view .LVU686
+ 2107 012e 638D     		ldrh	r3, [r4, #42]
+ 2108 0130 9BB2     		uxth	r3, r3
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2109              		.loc 1 1207 12 view .LVU687
+ 2110 0132 FF2B     		cmp	r3, #255
+ 2111 0134 C6D9     		bls	.L161
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 2112              		.loc 1 1209 11 is_stmt 1 view .LVU688
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 2113              		.loc 1 1209 26 is_stmt 0 view .LVU689
+ 2114 0136 FF22     		movs	r2, #255
+ 2115 0138 2285     		strh	r2, [r4, #40]	@ movhi
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 2116              		.loc 1 1210 11 is_stmt 1 view .LVU690
+ 2117 013a 0023     		movs	r3, #0
+ 2118 013c 0093     		str	r3, [sp]
+ 2119 013e 4FF08073 		mov	r3, #16777216
+ 2120 0142 3946     		mov	r1, r7
+ 2121 0144 2046     		mov	r0, r4
+ 2122 0146 FFF7FEFF 		bl	I2C_TransferConfig
+ 2123              	.LVL147:
+ 2124 014a C7E7     		b	.L159
+ 2125              	.L170:
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2126              		.loc 1 1224 5 view .LVU691
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2127              		.loc 1 1224 9 is_stmt 0 view .LVU692
+ 2128 014c 2A46     		mov	r2, r5
+ 2129 014e 3146     		mov	r1, r6
+ 2130 0150 2046     		mov	r0, r4
+ 2131 0152 FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 2132              	.LVL148:
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2133              		.loc 1 1224 8 view .LVU693
+ 2134 0156 08BB     		cbnz	r0, .L168
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2135              		.loc 1 1230 5 is_stmt 1 view .LVU694
+ 2136 0158 2368     		ldr	r3, [r4]
+ 2137 015a 2022     		movs	r2, #32
+ 2138 015c DA61     		str	r2, [r3, #28]
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2139              		.loc 1 1233 5 view .LVU695
+ 2140 015e 2168     		ldr	r1, [r4]
+ 2141 0160 4B68     		ldr	r3, [r1, #4]
+ 2142 0162 23F0FF73 		bic	r3, r3, #33423360
+ 2143 0166 23F48B33 		bic	r3, r3, #71168
+ 2144 016a 23F4FF73 		bic	r3, r3, #510
+ 2145 016e 23F00103 		bic	r3, r3, #1
+ 2146 0172 4B60     		str	r3, [r1, #4]
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2147              		.loc 1 1235 5 view .LVU696
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2148              		.loc 1 1235 17 is_stmt 0 view .LVU697
+ARM GAS  /tmp/ccVyGVF6.s 			page 181
+
+
+ 2149 0174 84F84120 		strb	r2, [r4, #65]
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2150              		.loc 1 1236 5 is_stmt 1 view .LVU698
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2151              		.loc 1 1236 17 is_stmt 0 view .LVU699
+ 2152 0178 0023     		movs	r3, #0
+ 2153 017a 84F84230 		strb	r3, [r4, #66]
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2154              		.loc 1 1239 5 is_stmt 1 view .LVU700
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2155              		.loc 1 1239 5 view .LVU701
+ 2156 017e 84F84030 		strb	r3, [r4, #64]
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2157              		.loc 1 1239 5 view .LVU702
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 2158              		.loc 1 1241 5 view .LVU703
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 2159              		.loc 1 1241 12 is_stmt 0 view .LVU704
+ 2160 0182 00E0     		b	.L154
+ 2161              	.LVL149:
+ 2162              	.L163:
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 2163              		.loc 1 1245 12 view .LVU705
+ 2164 0184 0220     		movs	r0, #2
+ 2165              	.LVL150:
+ 2166              	.L154:
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2167              		.loc 1 1247 1 view .LVU706
+ 2168 0186 02B0     		add	sp, sp, #8
+ 2169              	.LCFI21:
+ 2170              		.cfi_remember_state
+ 2171              		.cfi_def_cfa_offset 32
+ 2172              		@ sp needed
+ 2173 0188 BDE8F087 		pop	{r4, r5, r6, r7, r8, r9, r10, pc}
+ 2174              	.LVL151:
+ 2175              	.L164:
+ 2176              	.LCFI22:
+ 2177              		.cfi_restore_state
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2178              		.loc 1 1128 5 view .LVU707
+ 2179 018c 0220     		movs	r0, #2
+ 2180              	.LVL152:
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2181              		.loc 1 1128 5 view .LVU708
+ 2182 018e FAE7     		b	.L154
+ 2183              	.LVL153:
+ 2184              	.L165:
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2185              		.loc 1 1135 14 view .LVU709
+ 2186 0190 0120     		movs	r0, #1
+ 2187 0192 F8E7     		b	.L154
+ 2188              	.L166:
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2189              		.loc 1 1188 16 view .LVU710
+ 2190 0194 0120     		movs	r0, #1
+ 2191 0196 F6E7     		b	.L154
+ 2192              	.L167:
+ARM GAS  /tmp/ccVyGVF6.s 			page 182
+
+
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 2193              		.loc 1 1204 18 view .LVU711
+ 2194 0198 0120     		movs	r0, #1
+ 2195 019a F4E7     		b	.L154
+ 2196              	.L168:
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2197              		.loc 1 1226 14 view .LVU712
+ 2198 019c 0120     		movs	r0, #1
+ 2199 019e F2E7     		b	.L154
+ 2200              	.L172:
+ 2201              		.align	2
+ 2202              	.L171:
+ 2203 01a0 00200080 		.word	-2147475456
+ 2204              		.cfi_endproc
+ 2205              	.LFE145:
+ 2207              		.section	.text.HAL_I2C_Master_Receive,"ax",%progbits
+ 2208              		.align	1
+ 2209              		.global	HAL_I2C_Master_Receive
+ 2210              		.syntax unified
+ 2211              		.thumb
+ 2212              		.thumb_func
+ 2213              		.fpu fpv5-d16
+ 2215              	HAL_I2C_Master_Receive:
+ 2216              	.LVL154:
+ 2217              	.LFB146:
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 2218              		.loc 1 1262 1 is_stmt 1 view -0
+ 2219              		.cfi_startproc
+ 2220              		@ args = 4, pretend = 0, frame = 0
+ 2221              		@ frame_needed = 0, uses_anonymous_args = 0
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 2222              		.loc 1 1262 1 is_stmt 0 view .LVU714
+ 2223 0000 2DE9F047 		push	{r4, r5, r6, r7, r8, r9, r10, lr}
+ 2224              	.LCFI23:
+ 2225              		.cfi_def_cfa_offset 32
+ 2226              		.cfi_offset 4, -32
+ 2227              		.cfi_offset 5, -28
+ 2228              		.cfi_offset 6, -24
+ 2229              		.cfi_offset 7, -20
+ 2230              		.cfi_offset 8, -16
+ 2231              		.cfi_offset 9, -12
+ 2232              		.cfi_offset 10, -8
+ 2233              		.cfi_offset 14, -4
+ 2234 0004 82B0     		sub	sp, sp, #8
+ 2235              	.LCFI24:
+ 2236              		.cfi_def_cfa_offset 40
+ 2237 0006 0F46     		mov	r7, r1
+ 2238 0008 0A9E     		ldr	r6, [sp, #40]
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2239              		.loc 1 1263 3 is_stmt 1 view .LVU715
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 2240              		.loc 1 1265 3 view .LVU716
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 2241              		.loc 1 1265 11 is_stmt 0 view .LVU717
+ 2242 000a 90F84110 		ldrb	r1, [r0, #65]	@ zero_extendqisi2
+ 2243              	.LVL155:
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccVyGVF6.s 			page 183
+
+
+ 2244              		.loc 1 1265 11 view .LVU718
+ 2245 000e C9B2     		uxtb	r1, r1
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 2246              		.loc 1 1265 6 view .LVU719
+ 2247 0010 2029     		cmp	r1, #32
+ 2248 0012 40F0A380 		bne	.L181
+ 2249 0016 0446     		mov	r4, r0
+ 2250 0018 9046     		mov	r8, r2
+ 2251 001a 9946     		mov	r9, r3
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2252              		.loc 1 1268 5 is_stmt 1 view .LVU720
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2253              		.loc 1 1268 5 view .LVU721
+ 2254 001c 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 2255              	.LVL156:
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2256              		.loc 1 1268 5 is_stmt 0 view .LVU722
+ 2257 0020 012B     		cmp	r3, #1
+ 2258 0022 00F09F80 		beq	.L182
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2259              		.loc 1 1268 5 is_stmt 1 discriminator 2 view .LVU723
+ 2260 0026 4FF0010A 		mov	r10, #1
+ 2261 002a 80F840A0 		strb	r10, [r0, #64]
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2262              		.loc 1 1268 5 discriminator 2 view .LVU724
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2263              		.loc 1 1271 5 discriminator 2 view .LVU725
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2264              		.loc 1 1271 17 is_stmt 0 discriminator 2 view .LVU726
+ 2265 002e FFF7FEFF 		bl	HAL_GetTick
+ 2266              	.LVL157:
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2267              		.loc 1 1271 17 discriminator 2 view .LVU727
+ 2268 0032 0546     		mov	r5, r0
+ 2269              	.LVL158:
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2270              		.loc 1 1273 5 is_stmt 1 discriminator 2 view .LVU728
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2271              		.loc 1 1273 9 is_stmt 0 discriminator 2 view .LVU729
+ 2272 0034 0090     		str	r0, [sp]
+ 2273 0036 1923     		movs	r3, #25
+ 2274 0038 5246     		mov	r2, r10
+ 2275 003a 4FF40041 		mov	r1, #32768
+ 2276 003e 2046     		mov	r0, r4
+ 2277              	.LVL159:
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2278              		.loc 1 1273 9 discriminator 2 view .LVU730
+ 2279 0040 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2280              	.LVL160:
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2281              		.loc 1 1273 8 discriminator 2 view .LVU731
+ 2282 0044 0028     		cmp	r0, #0
+ 2283 0046 40F08F80 		bne	.L183
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 2284              		.loc 1 1278 5 is_stmt 1 view .LVU732
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 2285              		.loc 1 1278 21 is_stmt 0 view .LVU733
+ARM GAS  /tmp/ccVyGVF6.s 			page 184
+
+
+ 2286 004a 2223     		movs	r3, #34
+ 2287 004c 84F84130 		strb	r3, [r4, #65]
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 2288              		.loc 1 1279 5 is_stmt 1 view .LVU734
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 2289              		.loc 1 1279 21 is_stmt 0 view .LVU735
+ 2290 0050 1023     		movs	r3, #16
+ 2291 0052 84F84230 		strb	r3, [r4, #66]
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2292              		.loc 1 1280 5 is_stmt 1 view .LVU736
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2293              		.loc 1 1280 21 is_stmt 0 view .LVU737
+ 2294 0056 0023     		movs	r3, #0
+ 2295 0058 6364     		str	r3, [r4, #68]
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 2296              		.loc 1 1283 5 is_stmt 1 view .LVU738
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 2297              		.loc 1 1283 21 is_stmt 0 view .LVU739
+ 2298 005a C4F82480 		str	r8, [r4, #36]
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 2299              		.loc 1 1284 5 is_stmt 1 view .LVU740
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 2300              		.loc 1 1284 21 is_stmt 0 view .LVU741
+ 2301 005e A4F82A90 		strh	r9, [r4, #42]	@ movhi
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2302              		.loc 1 1285 5 is_stmt 1 view .LVU742
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2303              		.loc 1 1285 21 is_stmt 0 view .LVU743
+ 2304 0062 6363     		str	r3, [r4, #52]
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2305              		.loc 1 1289 5 is_stmt 1 view .LVU744
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2306              		.loc 1 1289 13 is_stmt 0 view .LVU745
+ 2307 0064 638D     		ldrh	r3, [r4, #42]
+ 2308 0066 9BB2     		uxth	r3, r3
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2309              		.loc 1 1289 8 view .LVU746
+ 2310 0068 FF2B     		cmp	r3, #255
+ 2311 006a 0BD9     		bls	.L175
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 2312              		.loc 1 1291 7 is_stmt 1 view .LVU747
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 2313              		.loc 1 1291 22 is_stmt 0 view .LVU748
+ 2314 006c 5246     		mov	r2, r10
+ 2315 006e A4F828A0 		strh	r10, [r4, #40]	@ movhi
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 2316              		.loc 1 1292 7 is_stmt 1 view .LVU749
+ 2317 0072 414B     		ldr	r3, .L189
+ 2318 0074 0093     		str	r3, [sp]
+ 2319 0076 4FF08073 		mov	r3, #16777216
+ 2320 007a 3946     		mov	r1, r7
+ 2321 007c 2046     		mov	r0, r4
+ 2322 007e FFF7FEFF 		bl	I2C_TransferConfig
+ 2323              	.LVL161:
+ 2324 0082 18E0     		b	.L177
+ 2325              	.L175:
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ARM GAS  /tmp/ccVyGVF6.s 			page 185
+
+
+ 2326              		.loc 1 1297 7 view .LVU750
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2327              		.loc 1 1297 28 is_stmt 0 view .LVU751
+ 2328 0084 628D     		ldrh	r2, [r4, #42]
+ 2329 0086 92B2     		uxth	r2, r2
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2330              		.loc 1 1297 22 view .LVU752
+ 2331 0088 2285     		strh	r2, [r4, #40]	@ movhi
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 2332              		.loc 1 1298 7 is_stmt 1 view .LVU753
+ 2333 008a 3B4B     		ldr	r3, .L189
+ 2334 008c 0093     		str	r3, [sp]
+ 2335 008e 4FF00073 		mov	r3, #33554432
+ 2336 0092 D2B2     		uxtb	r2, r2
+ 2337 0094 3946     		mov	r1, r7
+ 2338 0096 2046     		mov	r0, r4
+ 2339 0098 FFF7FEFF 		bl	I2C_TransferConfig
+ 2340              	.LVL162:
+ 2341 009c 0BE0     		b	.L177
+ 2342              	.L179:
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2343              		.loc 1 1335 11 view .LVU754
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2344              		.loc 1 1335 32 is_stmt 0 view .LVU755
+ 2345 009e 628D     		ldrh	r2, [r4, #42]
+ 2346 00a0 92B2     		uxth	r2, r2
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 2347              		.loc 1 1335 26 view .LVU756
+ 2348 00a2 2285     		strh	r2, [r4, #40]	@ movhi
+1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 2349              		.loc 1 1336 11 is_stmt 1 view .LVU757
+ 2350 00a4 0023     		movs	r3, #0
+ 2351 00a6 0093     		str	r3, [sp]
+ 2352 00a8 4FF00073 		mov	r3, #33554432
+ 2353 00ac D2B2     		uxtb	r2, r2
+ 2354 00ae 3946     		mov	r1, r7
+ 2355 00b0 2046     		mov	r0, r4
+ 2356 00b2 FFF7FEFF 		bl	I2C_TransferConfig
+ 2357              	.LVL163:
+ 2358              	.L177:
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2359              		.loc 1 1302 11 view .LVU758
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2360              		.loc 1 1302 16 is_stmt 0 view .LVU759
+ 2361 00b6 638D     		ldrh	r3, [r4, #42]
+ 2362 00b8 9BB2     		uxth	r3, r3
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2363              		.loc 1 1302 11 view .LVU760
+ 2364 00ba 002B     		cmp	r3, #0
+ 2365 00bc 32D0     		beq	.L188
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2366              		.loc 1 1305 7 is_stmt 1 view .LVU761
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2367              		.loc 1 1305 11 is_stmt 0 view .LVU762
+ 2368 00be 2A46     		mov	r2, r5
+ 2369 00c0 3146     		mov	r1, r6
+ 2370 00c2 2046     		mov	r0, r4
+ARM GAS  /tmp/ccVyGVF6.s 			page 186
+
+
+ 2371 00c4 FFF7FEFF 		bl	I2C_WaitOnRXNEFlagUntilTimeout
+ 2372              	.LVL164:
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2373              		.loc 1 1305 10 view .LVU763
+ 2374 00c8 0028     		cmp	r0, #0
+ 2375 00ca 4FD1     		bne	.L184
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2376              		.loc 1 1311 7 is_stmt 1 view .LVU764
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2377              		.loc 1 1311 38 is_stmt 0 view .LVU765
+ 2378 00cc 2368     		ldr	r3, [r4]
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2379              		.loc 1 1311 48 view .LVU766
+ 2380 00ce 5A6A     		ldr	r2, [r3, #36]
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2381              		.loc 1 1311 12 view .LVU767
+ 2382 00d0 636A     		ldr	r3, [r4, #36]
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2383              		.loc 1 1311 23 view .LVU768
+ 2384 00d2 1A70     		strb	r2, [r3]
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2385              		.loc 1 1314 7 is_stmt 1 view .LVU769
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2386              		.loc 1 1314 11 is_stmt 0 view .LVU770
+ 2387 00d4 636A     		ldr	r3, [r4, #36]
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2388              		.loc 1 1314 21 view .LVU771
+ 2389 00d6 0133     		adds	r3, r3, #1
+ 2390 00d8 6362     		str	r3, [r4, #36]
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 2391              		.loc 1 1316 7 is_stmt 1 view .LVU772
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 2392              		.loc 1 1316 11 is_stmt 0 view .LVU773
+ 2393 00da 228D     		ldrh	r2, [r4, #40]
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 2394              		.loc 1 1316 21 view .LVU774
+ 2395 00dc 013A     		subs	r2, r2, #1
+ 2396 00de 92B2     		uxth	r2, r2
+ 2397 00e0 2285     		strh	r2, [r4, #40]	@ movhi
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2398              		.loc 1 1317 7 is_stmt 1 view .LVU775
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2399              		.loc 1 1317 11 is_stmt 0 view .LVU776
+ 2400 00e2 638D     		ldrh	r3, [r4, #42]
+ 2401 00e4 9BB2     		uxth	r3, r3
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2402              		.loc 1 1317 22 view .LVU777
+ 2403 00e6 013B     		subs	r3, r3, #1
+ 2404 00e8 9BB2     		uxth	r3, r3
+ 2405 00ea 6385     		strh	r3, [r4, #42]	@ movhi
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2406              		.loc 1 1319 7 is_stmt 1 view .LVU778
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2407              		.loc 1 1319 16 is_stmt 0 view .LVU779
+ 2408 00ec 638D     		ldrh	r3, [r4, #42]
+ 2409 00ee 9BB2     		uxth	r3, r3
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ARM GAS  /tmp/ccVyGVF6.s 			page 187
+
+
+ 2410              		.loc 1 1319 10 view .LVU780
+ 2411 00f0 002B     		cmp	r3, #0
+ 2412 00f2 E0D0     		beq	.L177
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2413              		.loc 1 1319 35 discriminator 1 view .LVU781
+ 2414 00f4 002A     		cmp	r2, #0
+ 2415 00f6 DED1     		bne	.L177
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2416              		.loc 1 1322 9 is_stmt 1 view .LVU782
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2417              		.loc 1 1322 13 is_stmt 0 view .LVU783
+ 2418 00f8 0095     		str	r5, [sp]
+ 2419 00fa 3346     		mov	r3, r6
+ 2420 00fc 8021     		movs	r1, #128
+ 2421 00fe 2046     		mov	r0, r4
+ 2422 0100 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2423              	.LVL165:
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2424              		.loc 1 1322 12 view .LVU784
+ 2425 0104 A0BB     		cbnz	r0, .L185
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2426              		.loc 1 1327 9 is_stmt 1 view .LVU785
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2427              		.loc 1 1327 17 is_stmt 0 view .LVU786
+ 2428 0106 638D     		ldrh	r3, [r4, #42]
+ 2429 0108 9BB2     		uxth	r3, r3
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 2430              		.loc 1 1327 12 view .LVU787
+ 2431 010a FF2B     		cmp	r3, #255
+ 2432 010c C7D9     		bls	.L179
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 2433              		.loc 1 1329 11 is_stmt 1 view .LVU788
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 2434              		.loc 1 1329 26 is_stmt 0 view .LVU789
+ 2435 010e FF22     		movs	r2, #255
+ 2436 0110 2285     		strh	r2, [r4, #40]	@ movhi
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 2437              		.loc 1 1330 11 is_stmt 1 view .LVU790
+ 2438 0112 0023     		movs	r3, #0
+ 2439 0114 0093     		str	r3, [sp]
+ 2440 0116 4FF08073 		mov	r3, #16777216
+ 2441 011a 3946     		mov	r1, r7
+ 2442 011c 2046     		mov	r0, r4
+ 2443 011e FFF7FEFF 		bl	I2C_TransferConfig
+ 2444              	.LVL166:
+ 2445 0122 C8E7     		b	.L177
+ 2446              	.L188:
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2447              		.loc 1 1344 5 view .LVU791
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2448              		.loc 1 1344 9 is_stmt 0 view .LVU792
+ 2449 0124 2A46     		mov	r2, r5
+ 2450 0126 3146     		mov	r1, r6
+ 2451 0128 2046     		mov	r0, r4
+ 2452 012a FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 2453              	.LVL167:
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccVyGVF6.s 			page 188
+
+
+ 2454              		.loc 1 1344 8 view .LVU793
+ 2455 012e 08BB     		cbnz	r0, .L186
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2456              		.loc 1 1350 5 is_stmt 1 view .LVU794
+ 2457 0130 2368     		ldr	r3, [r4]
+ 2458 0132 2022     		movs	r2, #32
+ 2459 0134 DA61     		str	r2, [r3, #28]
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2460              		.loc 1 1353 5 view .LVU795
+ 2461 0136 2168     		ldr	r1, [r4]
+ 2462 0138 4B68     		ldr	r3, [r1, #4]
+ 2463 013a 23F0FF73 		bic	r3, r3, #33423360
+ 2464 013e 23F48B33 		bic	r3, r3, #71168
+ 2465 0142 23F4FF73 		bic	r3, r3, #510
+ 2466 0146 23F00103 		bic	r3, r3, #1
+ 2467 014a 4B60     		str	r3, [r1, #4]
+1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2468              		.loc 1 1355 5 view .LVU796
+1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2469              		.loc 1 1355 17 is_stmt 0 view .LVU797
+ 2470 014c 84F84120 		strb	r2, [r4, #65]
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2471              		.loc 1 1356 5 is_stmt 1 view .LVU798
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2472              		.loc 1 1356 17 is_stmt 0 view .LVU799
+ 2473 0150 0023     		movs	r3, #0
+ 2474 0152 84F84230 		strb	r3, [r4, #66]
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2475              		.loc 1 1359 5 is_stmt 1 view .LVU800
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2476              		.loc 1 1359 5 view .LVU801
+ 2477 0156 84F84030 		strb	r3, [r4, #64]
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2478              		.loc 1 1359 5 view .LVU802
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 2479              		.loc 1 1361 5 view .LVU803
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 2480              		.loc 1 1361 12 is_stmt 0 view .LVU804
+ 2481 015a 00E0     		b	.L174
+ 2482              	.LVL168:
+ 2483              	.L181:
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 2484              		.loc 1 1365 12 view .LVU805
+ 2485 015c 0220     		movs	r0, #2
+ 2486              	.LVL169:
+ 2487              	.L174:
+1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2488              		.loc 1 1367 1 view .LVU806
+ 2489 015e 02B0     		add	sp, sp, #8
+ 2490              	.LCFI25:
+ 2491              		.cfi_remember_state
+ 2492              		.cfi_def_cfa_offset 32
+ 2493              		@ sp needed
+ 2494 0160 BDE8F087 		pop	{r4, r5, r6, r7, r8, r9, r10, pc}
+ 2495              	.LVL170:
+ 2496              	.L182:
+ 2497              	.LCFI26:
+ARM GAS  /tmp/ccVyGVF6.s 			page 189
+
+
+ 2498              		.cfi_restore_state
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2499              		.loc 1 1268 5 view .LVU807
+ 2500 0164 0220     		movs	r0, #2
+ 2501              	.LVL171:
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2502              		.loc 1 1268 5 view .LVU808
+ 2503 0166 FAE7     		b	.L174
+ 2504              	.LVL172:
+ 2505              	.L183:
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2506              		.loc 1 1275 14 view .LVU809
+ 2507 0168 0120     		movs	r0, #1
+ 2508 016a F8E7     		b	.L174
+ 2509              	.L184:
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2510              		.loc 1 1307 16 view .LVU810
+ 2511 016c 0120     		movs	r0, #1
+ 2512 016e F6E7     		b	.L174
+ 2513              	.L185:
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 2514              		.loc 1 1324 18 view .LVU811
+ 2515 0170 0120     		movs	r0, #1
+ 2516 0172 F4E7     		b	.L174
+ 2517              	.L186:
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2518              		.loc 1 1346 14 view .LVU812
+ 2519 0174 0120     		movs	r0, #1
+ 2520 0176 F2E7     		b	.L174
+ 2521              	.L190:
+ 2522              		.align	2
+ 2523              	.L189:
+ 2524 0178 00240080 		.word	-2147474432
+ 2525              		.cfi_endproc
+ 2526              	.LFE146:
+ 2528              		.section	.text.HAL_I2C_Slave_Transmit,"ax",%progbits
+ 2529              		.align	1
+ 2530              		.global	HAL_I2C_Slave_Transmit
+ 2531              		.syntax unified
+ 2532              		.thumb
+ 2533              		.thumb_func
+ 2534              		.fpu fpv5-d16
+ 2536              	HAL_I2C_Slave_Transmit:
+ 2537              	.LVL173:
+ 2538              	.LFB147:
+1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 2539              		.loc 1 1380 1 is_stmt 1 view -0
+ 2540              		.cfi_startproc
+ 2541              		@ args = 0, pretend = 0, frame = 0
+ 2542              		@ frame_needed = 0, uses_anonymous_args = 0
+1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 2543              		.loc 1 1380 1 is_stmt 0 view .LVU814
+ 2544 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 2545              	.LCFI27:
+ 2546              		.cfi_def_cfa_offset 24
+ 2547              		.cfi_offset 4, -24
+ 2548              		.cfi_offset 5, -20
+ARM GAS  /tmp/ccVyGVF6.s 			page 190
+
+
+ 2549              		.cfi_offset 6, -16
+ 2550              		.cfi_offset 7, -12
+ 2551              		.cfi_offset 8, -8
+ 2552              		.cfi_offset 14, -4
+ 2553 0004 82B0     		sub	sp, sp, #8
+ 2554              	.LCFI28:
+ 2555              		.cfi_def_cfa_offset 32
+ 2556 0006 1D46     		mov	r5, r3
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t tmpXferCount;
+ 2557              		.loc 1 1381 3 is_stmt 1 view .LVU815
+1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef error;
+ 2558              		.loc 1 1382 3 view .LVU816
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2559              		.loc 1 1383 3 view .LVU817
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 2560              		.loc 1 1385 3 view .LVU818
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 2561              		.loc 1 1385 11 is_stmt 0 view .LVU819
+ 2562 0008 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 2563              	.LVL174:
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 2564              		.loc 1 1385 11 view .LVU820
+ 2565 000c DBB2     		uxtb	r3, r3
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 2566              		.loc 1 1385 6 view .LVU821
+ 2567 000e 202B     		cmp	r3, #32
+ 2568 0010 40F0EA80 		bne	.L206
+ 2569 0014 0446     		mov	r4, r0
+ 2570 0016 0F46     		mov	r7, r1
+ 2571 0018 9046     		mov	r8, r2
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2572              		.loc 1 1387 5 is_stmt 1 view .LVU822
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2573              		.loc 1 1387 8 is_stmt 0 view .LVU823
+ 2574 001a 002A     		cmp	r2, #0
+ 2575 001c 18BF     		it	ne
+ 2576 001e 0029     		cmpne	r1, #0
+ 2577 0020 55D0     		beq	.L209
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2578              		.loc 1 1393 5 is_stmt 1 view .LVU824
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2579              		.loc 1 1393 5 view .LVU825
+ 2580 0022 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 2581 0026 012B     		cmp	r3, #1
+ 2582 0028 00F0E280 		beq	.L207
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2583              		.loc 1 1393 5 discriminator 2 view .LVU826
+ 2584 002c 0123     		movs	r3, #1
+ 2585 002e 80F84030 		strb	r3, [r0, #64]
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2586              		.loc 1 1393 5 discriminator 2 view .LVU827
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2587              		.loc 1 1396 5 discriminator 2 view .LVU828
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2588              		.loc 1 1396 17 is_stmt 0 discriminator 2 view .LVU829
+ 2589 0032 FFF7FEFF 		bl	HAL_GetTick
+ 2590              	.LVL175:
+ARM GAS  /tmp/ccVyGVF6.s 			page 191
+
+
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2591              		.loc 1 1396 17 discriminator 2 view .LVU830
+ 2592 0036 0646     		mov	r6, r0
+ 2593              	.LVL176:
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 2594              		.loc 1 1398 5 is_stmt 1 discriminator 2 view .LVU831
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 2595              		.loc 1 1398 21 is_stmt 0 discriminator 2 view .LVU832
+ 2596 0038 2123     		movs	r3, #33
+ 2597 003a 84F84130 		strb	r3, [r4, #65]
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 2598              		.loc 1 1399 5 is_stmt 1 discriminator 2 view .LVU833
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 2599              		.loc 1 1399 21 is_stmt 0 discriminator 2 view .LVU834
+ 2600 003e 2023     		movs	r3, #32
+ 2601 0040 84F84230 		strb	r3, [r4, #66]
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2602              		.loc 1 1400 5 is_stmt 1 discriminator 2 view .LVU835
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2603              		.loc 1 1400 21 is_stmt 0 discriminator 2 view .LVU836
+ 2604 0044 0023     		movs	r3, #0
+ 2605 0046 6364     		str	r3, [r4, #68]
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 2606              		.loc 1 1403 5 is_stmt 1 discriminator 2 view .LVU837
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 2607              		.loc 1 1403 21 is_stmt 0 discriminator 2 view .LVU838
+ 2608 0048 6762     		str	r7, [r4, #36]
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 2609              		.loc 1 1404 5 is_stmt 1 discriminator 2 view .LVU839
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 2610              		.loc 1 1404 21 is_stmt 0 discriminator 2 view .LVU840
+ 2611 004a A4F82A80 		strh	r8, [r4, #42]	@ movhi
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2612              		.loc 1 1405 5 is_stmt 1 discriminator 2 view .LVU841
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2613              		.loc 1 1405 21 is_stmt 0 discriminator 2 view .LVU842
+ 2614 004e 6363     		str	r3, [r4, #52]
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2615              		.loc 1 1408 5 is_stmt 1 discriminator 2 view .LVU843
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2616              		.loc 1 1408 9 is_stmt 0 discriminator 2 view .LVU844
+ 2617 0050 2268     		ldr	r2, [r4]
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2618              		.loc 1 1408 25 discriminator 2 view .LVU845
+ 2619 0052 5368     		ldr	r3, [r2, #4]
+ 2620 0054 23F40043 		bic	r3, r3, #32768
+ 2621 0058 5360     		str	r3, [r2, #4]
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2622              		.loc 1 1411 5 is_stmt 1 discriminator 2 view .LVU846
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2623              		.loc 1 1411 19 is_stmt 0 discriminator 2 view .LVU847
+ 2624 005a 236A     		ldr	r3, [r4, #32]
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2625              		.loc 1 1411 8 discriminator 2 view .LVU848
+ 2626 005c B3F5003F 		cmp	r3, #131072
+ 2627 0060 3AD0     		beq	.L210
+ 2628              	.L194:
+ARM GAS  /tmp/ccVyGVF6.s 			page 192
+
+
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2629              		.loc 1 1424 5 is_stmt 1 view .LVU849
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2630              		.loc 1 1424 9 is_stmt 0 view .LVU850
+ 2631 0062 0096     		str	r6, [sp]
+ 2632 0064 2B46     		mov	r3, r5
+ 2633 0066 0022     		movs	r2, #0
+ 2634 0068 0821     		movs	r1, #8
+ 2635 006a 2046     		mov	r0, r4
+ 2636              	.LVL177:
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2637              		.loc 1 1424 9 view .LVU851
+ 2638 006c FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2639              	.LVL178:
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2640              		.loc 1 1424 8 view .LVU852
+ 2641 0070 0028     		cmp	r0, #0
+ 2642 0072 3ED1     		bne	.L211
+1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2643              		.loc 1 1436 5 is_stmt 1 view .LVU853
+ 2644 0074 2368     		ldr	r3, [r4]
+ 2645 0076 0822     		movs	r2, #8
+ 2646 0078 DA61     		str	r2, [r3, #28]
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2647              		.loc 1 1439 5 view .LVU854
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2648              		.loc 1 1439 19 is_stmt 0 view .LVU855
+ 2649 007a E368     		ldr	r3, [r4, #12]
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2650              		.loc 1 1439 8 view .LVU856
+ 2651 007c 022B     		cmp	r3, #2
+ 2652 007e 42D0     		beq	.L212
+ 2653              	.L196:
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2654              		.loc 1 1458 5 is_stmt 1 view .LVU857
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2655              		.loc 1 1458 9 is_stmt 0 view .LVU858
+ 2656 0080 0096     		str	r6, [sp]
+ 2657 0082 2B46     		mov	r3, r5
+ 2658 0084 0022     		movs	r2, #0
+ 2659 0086 4FF48031 		mov	r1, #65536
+ 2660 008a 2046     		mov	r0, r4
+ 2661 008c FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2662              	.LVL179:
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2663              		.loc 1 1458 8 view .LVU859
+ 2664 0090 0028     		cmp	r0, #0
+ 2665 0092 4ED1     		bne	.L213
+ 2666              	.L198:
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2667              		.loc 1 1469 11 is_stmt 1 view .LVU860
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2668              		.loc 1 1469 16 is_stmt 0 view .LVU861
+ 2669 0094 628D     		ldrh	r2, [r4, #42]
+ 2670 0096 92B2     		uxth	r2, r2
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2671              		.loc 1 1469 11 view .LVU862
+ARM GAS  /tmp/ccVyGVF6.s 			page 193
+
+
+ 2672 0098 002A     		cmp	r2, #0
+ 2673 009a 5BD0     		beq	.L214
+1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2674              		.loc 1 1472 7 is_stmt 1 view .LVU863
+1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2675              		.loc 1 1472 11 is_stmt 0 view .LVU864
+ 2676 009c 3246     		mov	r2, r6
+ 2677 009e 2946     		mov	r1, r5
+ 2678 00a0 2046     		mov	r0, r4
+ 2679 00a2 FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 2680              	.LVL180:
+1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2681              		.loc 1 1472 10 view .LVU865
+ 2682 00a6 0028     		cmp	r0, #0
+ 2683 00a8 4DD1     		bne	.L215
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2684              		.loc 1 1480 7 is_stmt 1 view .LVU866
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2685              		.loc 1 1480 35 is_stmt 0 view .LVU867
+ 2686 00aa 626A     		ldr	r2, [r4, #36]
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2687              		.loc 1 1480 11 view .LVU868
+ 2688 00ac 2368     		ldr	r3, [r4]
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2689              		.loc 1 1480 30 view .LVU869
+ 2690 00ae 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2691              		.loc 1 1480 28 view .LVU870
+ 2692 00b0 9A62     		str	r2, [r3, #40]
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2693              		.loc 1 1483 7 is_stmt 1 view .LVU871
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2694              		.loc 1 1483 11 is_stmt 0 view .LVU872
+ 2695 00b2 636A     		ldr	r3, [r4, #36]
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2696              		.loc 1 1483 21 view .LVU873
+ 2697 00b4 0133     		adds	r3, r3, #1
+ 2698 00b6 6362     		str	r3, [r4, #36]
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2699              		.loc 1 1485 7 is_stmt 1 view .LVU874
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2700              		.loc 1 1485 11 is_stmt 0 view .LVU875
+ 2701 00b8 B4F82AC0 		ldrh	ip, [r4, #42]
+ 2702 00bc 1FFA8CFC 		uxth	ip, ip
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2703              		.loc 1 1485 22 view .LVU876
+ 2704 00c0 0CF1FF3C 		add	ip, ip, #-1
+ 2705 00c4 1FFA8CFC 		uxth	ip, ip
+ 2706 00c8 A4F82AC0 		strh	ip, [r4, #42]	@ movhi
+ 2707 00cc E2E7     		b	.L198
+ 2708              	.LVL181:
+ 2709              	.L209:
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 2710              		.loc 1 1389 7 is_stmt 1 view .LVU877
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 2711              		.loc 1 1389 23 is_stmt 0 view .LVU878
+ 2712 00ce 4FF40073 		mov	r3, #512
+ARM GAS  /tmp/ccVyGVF6.s 			page 194
+
+
+ 2713 00d2 4364     		str	r3, [r0, #68]
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2714              		.loc 1 1390 7 is_stmt 1 view .LVU879
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2715              		.loc 1 1390 15 is_stmt 0 view .LVU880
+ 2716 00d4 0120     		movs	r0, #1
+ 2717              	.LVL182:
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2718              		.loc 1 1390 15 view .LVU881
+ 2719 00d6 88E0     		b	.L192
+ 2720              	.LVL183:
+ 2721              	.L210:
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2722              		.loc 1 1415 7 is_stmt 1 view .LVU882
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2723              		.loc 1 1415 35 is_stmt 0 view .LVU883
+ 2724 00d8 626A     		ldr	r2, [r4, #36]
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2725              		.loc 1 1415 11 view .LVU884
+ 2726 00da 2368     		ldr	r3, [r4]
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2727              		.loc 1 1415 30 view .LVU885
+ 2728 00dc 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2729              		.loc 1 1415 28 view .LVU886
+ 2730 00de 9A62     		str	r2, [r3, #40]
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2731              		.loc 1 1418 7 is_stmt 1 view .LVU887
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2732              		.loc 1 1418 11 is_stmt 0 view .LVU888
+ 2733 00e0 636A     		ldr	r3, [r4, #36]
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2734              		.loc 1 1418 21 view .LVU889
+ 2735 00e2 0133     		adds	r3, r3, #1
+ 2736 00e4 6362     		str	r3, [r4, #36]
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2737              		.loc 1 1420 7 is_stmt 1 view .LVU890
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2738              		.loc 1 1420 11 is_stmt 0 view .LVU891
+ 2739 00e6 638D     		ldrh	r3, [r4, #42]
+ 2740 00e8 9BB2     		uxth	r3, r3
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2741              		.loc 1 1420 22 view .LVU892
+ 2742 00ea 013B     		subs	r3, r3, #1
+ 2743 00ec 9BB2     		uxth	r3, r3
+ 2744 00ee 6385     		strh	r3, [r4, #42]	@ movhi
+ 2745 00f0 B7E7     		b	.L194
+ 2746              	.LVL184:
+ 2747              	.L211:
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2748              		.loc 1 1427 7 is_stmt 1 view .LVU893
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2749              		.loc 1 1427 11 is_stmt 0 view .LVU894
+ 2750 00f2 2268     		ldr	r2, [r4]
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2751              		.loc 1 1427 27 view .LVU895
+ 2752 00f4 5368     		ldr	r3, [r2, #4]
+ARM GAS  /tmp/ccVyGVF6.s 			page 195
+
+
+ 2753 00f6 43F40043 		orr	r3, r3, #32768
+ 2754 00fa 5360     		str	r3, [r2, #4]
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2755              		.loc 1 1430 7 is_stmt 1 view .LVU896
+ 2756 00fc 2046     		mov	r0, r4
+ 2757 00fe FFF7FEFF 		bl	I2C_Flush_TXDR
+ 2758              	.LVL185:
+1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2759              		.loc 1 1432 7 view .LVU897
+1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2760              		.loc 1 1432 14 is_stmt 0 view .LVU898
+ 2761 0102 0120     		movs	r0, #1
+ 2762 0104 71E0     		b	.L192
+ 2763              	.L212:
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2764              		.loc 1 1442 7 is_stmt 1 view .LVU899
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2765              		.loc 1 1442 11 is_stmt 0 view .LVU900
+ 2766 0106 0096     		str	r6, [sp]
+ 2767 0108 2B46     		mov	r3, r5
+ 2768 010a 0022     		movs	r2, #0
+ 2769 010c 0821     		movs	r1, #8
+ 2770 010e 2046     		mov	r0, r4
+ 2771 0110 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2772              	.LVL186:
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2773              		.loc 1 1442 10 view .LVU901
+ 2774 0114 18B9     		cbnz	r0, .L216
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2775              		.loc 1 1454 7 is_stmt 1 view .LVU902
+ 2776 0116 2368     		ldr	r3, [r4]
+ 2777 0118 0822     		movs	r2, #8
+ 2778 011a DA61     		str	r2, [r3, #28]
+ 2779 011c B0E7     		b	.L196
+ 2780              	.L216:
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2781              		.loc 1 1445 9 view .LVU903
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2782              		.loc 1 1445 13 is_stmt 0 view .LVU904
+ 2783 011e 2268     		ldr	r2, [r4]
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2784              		.loc 1 1445 29 view .LVU905
+ 2785 0120 5368     		ldr	r3, [r2, #4]
+ 2786 0122 43F40043 		orr	r3, r3, #32768
+ 2787 0126 5360     		str	r3, [r2, #4]
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2788              		.loc 1 1448 9 is_stmt 1 view .LVU906
+ 2789 0128 2046     		mov	r0, r4
+ 2790 012a FFF7FEFF 		bl	I2C_Flush_TXDR
+ 2791              	.LVL187:
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2792              		.loc 1 1450 9 view .LVU907
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2793              		.loc 1 1450 16 is_stmt 0 view .LVU908
+ 2794 012e 0120     		movs	r0, #1
+ 2795 0130 5BE0     		b	.L192
+ 2796              	.L213:
+ARM GAS  /tmp/ccVyGVF6.s 			page 196
+
+
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2797              		.loc 1 1461 7 is_stmt 1 view .LVU909
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2798              		.loc 1 1461 11 is_stmt 0 view .LVU910
+ 2799 0132 2268     		ldr	r2, [r4]
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2800              		.loc 1 1461 27 view .LVU911
+ 2801 0134 5368     		ldr	r3, [r2, #4]
+ 2802 0136 43F40043 		orr	r3, r3, #32768
+ 2803 013a 5360     		str	r3, [r2, #4]
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2804              		.loc 1 1464 7 is_stmt 1 view .LVU912
+ 2805 013c 2046     		mov	r0, r4
+ 2806 013e FFF7FEFF 		bl	I2C_Flush_TXDR
+ 2807              	.LVL188:
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2808              		.loc 1 1466 7 view .LVU913
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2809              		.loc 1 1466 14 is_stmt 0 view .LVU914
+ 2810 0142 0120     		movs	r0, #1
+ 2811 0144 51E0     		b	.L192
+ 2812              	.L215:
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+ 2813              		.loc 1 1475 9 is_stmt 1 view .LVU915
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+ 2814              		.loc 1 1475 13 is_stmt 0 view .LVU916
+ 2815 0146 2268     		ldr	r2, [r4]
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+ 2816              		.loc 1 1475 29 view .LVU917
+ 2817 0148 5368     		ldr	r3, [r2, #4]
+ 2818 014a 43F40043 		orr	r3, r3, #32768
+ 2819 014e 5360     		str	r3, [r2, #4]
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2820              		.loc 1 1476 9 is_stmt 1 view .LVU918
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2821              		.loc 1 1476 16 is_stmt 0 view .LVU919
+ 2822 0150 0120     		movs	r0, #1
+ 2823 0152 4AE0     		b	.L192
+ 2824              	.L214:
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2825              		.loc 1 1489 5 is_stmt 1 view .LVU920
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2826              		.loc 1 1489 13 is_stmt 0 view .LVU921
+ 2827 0154 0096     		str	r6, [sp]
+ 2828 0156 2B46     		mov	r3, r5
+ 2829 0158 1021     		movs	r1, #16
+ 2830 015a 2046     		mov	r0, r4
+ 2831 015c FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2832              	.LVL189:
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2833              		.loc 1 1491 5 is_stmt 1 view .LVU922
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2834              		.loc 1 1491 8 is_stmt 0 view .LVU923
+ 2835 0160 E8B1     		cbz	r0, .L201
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
+ 2836              		.loc 1 1497 7 is_stmt 1 view .LVU924
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
+ARM GAS  /tmp/ccVyGVF6.s 			page 197
+
+
+ 2837              		.loc 1 1497 20 is_stmt 0 view .LVU925
+ 2838 0162 638D     		ldrh	r3, [r4, #42]
+ 2839 0164 9BB2     		uxth	r3, r3
+ 2840              	.LVL190:
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2841              		.loc 1 1498 7 is_stmt 1 view .LVU926
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2842              		.loc 1 1498 16 is_stmt 0 view .LVU927
+ 2843 0166 626C     		ldr	r2, [r4, #68]
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2844              		.loc 1 1498 10 view .LVU928
+ 2845 0168 042A     		cmp	r2, #4
+ 2846 016a 11D1     		bne	.L202
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2847              		.loc 1 1498 49 discriminator 1 view .LVU929
+ 2848 016c 83B9     		cbnz	r3, .L202
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2849              		.loc 1 1501 9 is_stmt 1 view .LVU930
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2850              		.loc 1 1501 25 is_stmt 0 view .LVU931
+ 2851 016e 6364     		str	r3, [r4, #68]
+ 2852              	.LVL191:
+ 2853              	.L203:
+1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2854              		.loc 1 1532 5 is_stmt 1 view .LVU932
+1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2855              		.loc 1 1532 9 is_stmt 0 view .LVU933
+ 2856 0170 0096     		str	r6, [sp]
+ 2857 0172 2B46     		mov	r3, r5
+ 2858 0174 0122     		movs	r2, #1
+ 2859 0176 4FF40041 		mov	r1, #32768
+ 2860 017a 2046     		mov	r0, r4
+ 2861 017c FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 2862              	.LVL192:
+1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 2863              		.loc 1 1532 8 view .LVU934
+ 2864 0180 20B3     		cbz	r0, .L205
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 2865              		.loc 1 1535 7 is_stmt 1 view .LVU935
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 2866              		.loc 1 1535 11 is_stmt 0 view .LVU936
+ 2867 0182 2268     		ldr	r2, [r4]
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 2868              		.loc 1 1535 27 view .LVU937
+ 2869 0184 5368     		ldr	r3, [r2, #4]
+ 2870 0186 43F40043 		orr	r3, r3, #32768
+ 2871 018a 5360     		str	r3, [r2, #4]
+1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2872              		.loc 1 1536 7 is_stmt 1 view .LVU938
+1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2873              		.loc 1 1536 14 is_stmt 0 view .LVU939
+ 2874 018c 0120     		movs	r0, #1
+ 2875 018e 2CE0     		b	.L192
+ 2876              	.LVL193:
+ 2877              	.L202:
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+ 2878              		.loc 1 1506 9 is_stmt 1 view .LVU940
+ARM GAS  /tmp/ccVyGVF6.s 			page 198
+
+
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+ 2879              		.loc 1 1506 13 is_stmt 0 view .LVU941
+ 2880 0190 2268     		ldr	r2, [r4]
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+ 2881              		.loc 1 1506 29 view .LVU942
+ 2882 0192 5368     		ldr	r3, [r2, #4]
+ 2883              	.LVL194:
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         return HAL_ERROR;
+ 2884              		.loc 1 1506 29 view .LVU943
+ 2885 0194 43F40043 		orr	r3, r3, #32768
+ 2886 0198 5360     		str	r3, [r2, #4]
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2887              		.loc 1 1507 9 is_stmt 1 view .LVU944
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2888              		.loc 1 1507 16 is_stmt 0 view .LVU945
+ 2889 019a 0120     		movs	r0, #1
+ 2890              	.LVL195:
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2891              		.loc 1 1507 16 view .LVU946
+ 2892 019c 25E0     		b	.L192
+ 2893              	.LVL196:
+ 2894              	.L201:
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2895              		.loc 1 1513 7 is_stmt 1 view .LVU947
+ 2896 019e 2046     		mov	r0, r4
+ 2897              	.LVL197:
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2898              		.loc 1 1513 7 is_stmt 0 view .LVU948
+ 2899 01a0 FFF7FEFF 		bl	I2C_Flush_TXDR
+ 2900              	.LVL198:
+1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2901              		.loc 1 1516 7 is_stmt 1 view .LVU949
+ 2902 01a4 2368     		ldr	r3, [r4]
+ 2903 01a6 1022     		movs	r2, #16
+ 2904 01a8 DA61     		str	r2, [r3, #28]
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2905              		.loc 1 1519 7 view .LVU950
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2906              		.loc 1 1519 11 is_stmt 0 view .LVU951
+ 2907 01aa 3246     		mov	r2, r6
+ 2908 01ac 2946     		mov	r1, r5
+ 2909 01ae 2046     		mov	r0, r4
+ 2910 01b0 FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 2911              	.LVL199:
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 2912              		.loc 1 1519 10 view .LVU952
+ 2913 01b4 18B9     		cbnz	r0, .L217
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 2914              		.loc 1 1528 7 is_stmt 1 view .LVU953
+ 2915 01b6 2368     		ldr	r3, [r4]
+ 2916 01b8 2022     		movs	r2, #32
+ 2917 01ba DA61     		str	r2, [r3, #28]
+ 2918 01bc D8E7     		b	.L203
+ 2919              	.L217:
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2920              		.loc 1 1522 9 view .LVU954
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 199
+
+
+ 2921              		.loc 1 1522 13 is_stmt 0 view .LVU955
+ 2922 01be 2268     		ldr	r2, [r4]
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2923              		.loc 1 1522 29 view .LVU956
+ 2924 01c0 5368     		ldr	r3, [r2, #4]
+ 2925 01c2 43F40043 		orr	r3, r3, #32768
+ 2926 01c6 5360     		str	r3, [r2, #4]
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2927              		.loc 1 1524 9 is_stmt 1 view .LVU957
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 2928              		.loc 1 1524 16 is_stmt 0 view .LVU958
+ 2929 01c8 0120     		movs	r0, #1
+ 2930 01ca 0EE0     		b	.L192
+ 2931              	.L205:
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2932              		.loc 1 1540 5 is_stmt 1 view .LVU959
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2933              		.loc 1 1540 9 is_stmt 0 view .LVU960
+ 2934 01cc 2268     		ldr	r2, [r4]
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2935              		.loc 1 1540 25 view .LVU961
+ 2936 01ce 5368     		ldr	r3, [r2, #4]
+ 2937 01d0 43F40043 		orr	r3, r3, #32768
+ 2938 01d4 5360     		str	r3, [r2, #4]
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2939              		.loc 1 1542 5 is_stmt 1 view .LVU962
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 2940              		.loc 1 1542 17 is_stmt 0 view .LVU963
+ 2941 01d6 2023     		movs	r3, #32
+ 2942 01d8 84F84130 		strb	r3, [r4, #65]
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2943              		.loc 1 1543 5 is_stmt 1 view .LVU964
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2944              		.loc 1 1543 17 is_stmt 0 view .LVU965
+ 2945 01dc 0023     		movs	r3, #0
+ 2946 01de 84F84230 		strb	r3, [r4, #66]
+1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2947              		.loc 1 1546 5 is_stmt 1 view .LVU966
+1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2948              		.loc 1 1546 5 view .LVU967
+ 2949 01e2 84F84030 		strb	r3, [r4, #64]
+1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2950              		.loc 1 1546 5 view .LVU968
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 2951              		.loc 1 1548 5 view .LVU969
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 2952              		.loc 1 1548 12 is_stmt 0 view .LVU970
+ 2953 01e6 00E0     		b	.L192
+ 2954              	.LVL200:
+ 2955              	.L206:
+1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 2956              		.loc 1 1552 12 view .LVU971
+ 2957 01e8 0220     		movs	r0, #2
+ 2958              	.LVL201:
+ 2959              	.L192:
+1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2960              		.loc 1 1554 1 view .LVU972
+ARM GAS  /tmp/ccVyGVF6.s 			page 200
+
+
+ 2961 01ea 02B0     		add	sp, sp, #8
+ 2962              	.LCFI29:
+ 2963              		.cfi_remember_state
+ 2964              		.cfi_def_cfa_offset 24
+ 2965              		@ sp needed
+ 2966 01ec BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 2967              	.LVL202:
+ 2968              	.L207:
+ 2969              	.LCFI30:
+ 2970              		.cfi_restore_state
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2971              		.loc 1 1393 5 view .LVU973
+ 2972 01f0 0220     		movs	r0, #2
+ 2973              	.LVL203:
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 2974              		.loc 1 1393 5 view .LVU974
+ 2975 01f2 FAE7     		b	.L192
+ 2976              		.cfi_endproc
+ 2977              	.LFE147:
+ 2979              		.section	.text.HAL_I2C_Slave_Receive,"ax",%progbits
+ 2980              		.align	1
+ 2981              		.global	HAL_I2C_Slave_Receive
+ 2982              		.syntax unified
+ 2983              		.thumb
+ 2984              		.thumb_func
+ 2985              		.fpu fpv5-d16
+ 2987              	HAL_I2C_Slave_Receive:
+ 2988              	.LVL204:
+ 2989              	.LFB148:
+1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 2990              		.loc 1 1567 1 is_stmt 1 view -0
+ 2991              		.cfi_startproc
+ 2992              		@ args = 0, pretend = 0, frame = 0
+ 2993              		@ frame_needed = 0, uses_anonymous_args = 0
+1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 2994              		.loc 1 1567 1 is_stmt 0 view .LVU976
+ 2995 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 2996              	.LCFI31:
+ 2997              		.cfi_def_cfa_offset 24
+ 2998              		.cfi_offset 4, -24
+ 2999              		.cfi_offset 5, -20
+ 3000              		.cfi_offset 6, -16
+ 3001              		.cfi_offset 7, -12
+ 3002              		.cfi_offset 8, -8
+ 3003              		.cfi_offset 14, -4
+ 3004 0004 82B0     		sub	sp, sp, #8
+ 3005              	.LCFI32:
+ 3006              		.cfi_def_cfa_offset 32
+ 3007 0006 1D46     		mov	r5, r3
+1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3008              		.loc 1 1568 3 is_stmt 1 view .LVU977
+1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3009              		.loc 1 1570 3 view .LVU978
+1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3010              		.loc 1 1570 11 is_stmt 0 view .LVU979
+ 3011 0008 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 3012              	.LVL205:
+ARM GAS  /tmp/ccVyGVF6.s 			page 201
+
+
+1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3013              		.loc 1 1570 11 view .LVU980
+ 3014 000c DBB2     		uxtb	r3, r3
+1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3015              		.loc 1 1570 6 view .LVU981
+ 3016 000e 202B     		cmp	r3, #32
+ 3017 0010 40F0B280 		bne	.L228
+ 3018 0014 0446     		mov	r4, r0
+ 3019 0016 0F46     		mov	r7, r1
+ 3020 0018 9046     		mov	r8, r2
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3021              		.loc 1 1572 5 is_stmt 1 view .LVU982
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3022              		.loc 1 1572 8 is_stmt 0 view .LVU983
+ 3023 001a 002A     		cmp	r2, #0
+ 3024 001c 18BF     		it	ne
+ 3025 001e 0029     		cmpne	r1, #0
+ 3026 0020 2BD0     		beq	.L231
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3027              		.loc 1 1578 5 is_stmt 1 view .LVU984
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3028              		.loc 1 1578 5 view .LVU985
+ 3029 0022 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 3030 0026 012B     		cmp	r3, #1
+ 3031 0028 00F0AA80 		beq	.L229
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3032              		.loc 1 1578 5 discriminator 2 view .LVU986
+ 3033 002c 0123     		movs	r3, #1
+ 3034 002e 80F84030 		strb	r3, [r0, #64]
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3035              		.loc 1 1578 5 discriminator 2 view .LVU987
+1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3036              		.loc 1 1581 5 discriminator 2 view .LVU988
+1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3037              		.loc 1 1581 17 is_stmt 0 discriminator 2 view .LVU989
+ 3038 0032 FFF7FEFF 		bl	HAL_GetTick
+ 3039              	.LVL206:
+1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3040              		.loc 1 1581 17 discriminator 2 view .LVU990
+ 3041 0036 0646     		mov	r6, r0
+ 3042              	.LVL207:
+1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 3043              		.loc 1 1583 5 is_stmt 1 discriminator 2 view .LVU991
+1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 3044              		.loc 1 1583 21 is_stmt 0 discriminator 2 view .LVU992
+ 3045 0038 2223     		movs	r3, #34
+ 3046 003a 84F84130 		strb	r3, [r4, #65]
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 3047              		.loc 1 1584 5 is_stmt 1 discriminator 2 view .LVU993
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 3048              		.loc 1 1584 21 is_stmt 0 discriminator 2 view .LVU994
+ 3049 003e 2023     		movs	r3, #32
+ 3050 0040 84F84230 		strb	r3, [r4, #66]
+1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3051              		.loc 1 1585 5 is_stmt 1 discriminator 2 view .LVU995
+1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3052              		.loc 1 1585 21 is_stmt 0 discriminator 2 view .LVU996
+ARM GAS  /tmp/ccVyGVF6.s 			page 202
+
+
+ 3053 0044 0022     		movs	r2, #0
+ 3054 0046 6264     		str	r2, [r4, #68]
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 3055              		.loc 1 1588 5 is_stmt 1 discriminator 2 view .LVU997
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 3056              		.loc 1 1588 21 is_stmt 0 discriminator 2 view .LVU998
+ 3057 0048 6762     		str	r7, [r4, #36]
+1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize = hi2c->XferCount;
+ 3058              		.loc 1 1589 5 is_stmt 1 discriminator 2 view .LVU999
+1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize = hi2c->XferCount;
+ 3059              		.loc 1 1589 21 is_stmt 0 discriminator 2 view .LVU1000
+ 3060 004a A4F82A80 		strh	r8, [r4, #42]	@ movhi
+1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 3061              		.loc 1 1590 5 is_stmt 1 discriminator 2 view .LVU1001
+1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 3062              		.loc 1 1590 26 is_stmt 0 discriminator 2 view .LVU1002
+ 3063 004e 638D     		ldrh	r3, [r4, #42]
+1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 3064              		.loc 1 1590 20 discriminator 2 view .LVU1003
+ 3065 0050 2385     		strh	r3, [r4, #40]	@ movhi
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3066              		.loc 1 1591 5 is_stmt 1 discriminator 2 view .LVU1004
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3067              		.loc 1 1591 21 is_stmt 0 discriminator 2 view .LVU1005
+ 3068 0052 6263     		str	r2, [r4, #52]
+1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3069              		.loc 1 1594 5 is_stmt 1 discriminator 2 view .LVU1006
+1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3070              		.loc 1 1594 9 is_stmt 0 discriminator 2 view .LVU1007
+ 3071 0054 2168     		ldr	r1, [r4]
+1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3072              		.loc 1 1594 25 discriminator 2 view .LVU1008
+ 3073 0056 4B68     		ldr	r3, [r1, #4]
+ 3074 0058 23F40043 		bic	r3, r3, #32768
+ 3075 005c 4B60     		str	r3, [r1, #4]
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3076              		.loc 1 1597 5 is_stmt 1 discriminator 2 view .LVU1009
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3077              		.loc 1 1597 9 is_stmt 0 discriminator 2 view .LVU1010
+ 3078 005e 0090     		str	r0, [sp]
+ 3079 0060 2B46     		mov	r3, r5
+ 3080 0062 0821     		movs	r1, #8
+ 3081 0064 2046     		mov	r0, r4
+ 3082              	.LVL208:
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3083              		.loc 1 1597 9 discriminator 2 view .LVU1011
+ 3084 0066 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 3085              	.LVL209:
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3086              		.loc 1 1597 8 discriminator 2 view .LVU1012
+ 3087 006a 58B1     		cbz	r0, .L221
+1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 3088              		.loc 1 1600 7 is_stmt 1 view .LVU1013
+1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 3089              		.loc 1 1600 11 is_stmt 0 view .LVU1014
+ 3090 006c 2268     		ldr	r2, [r4]
+1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ARM GAS  /tmp/ccVyGVF6.s 			page 203
+
+
+ 3091              		.loc 1 1600 27 view .LVU1015
+ 3092 006e 5368     		ldr	r3, [r2, #4]
+ 3093 0070 43F40043 		orr	r3, r3, #32768
+ 3094 0074 5360     		str	r3, [r2, #4]
+1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3095              		.loc 1 1601 7 is_stmt 1 view .LVU1016
+1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3096              		.loc 1 1601 14 is_stmt 0 view .LVU1017
+ 3097 0076 0120     		movs	r0, #1
+ 3098 0078 7FE0     		b	.L219
+ 3099              	.LVL210:
+ 3100              	.L231:
+1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 3101              		.loc 1 1574 7 is_stmt 1 view .LVU1018
+1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 3102              		.loc 1 1574 23 is_stmt 0 view .LVU1019
+ 3103 007a 4FF40073 		mov	r3, #512
+ 3104 007e 4364     		str	r3, [r0, #68]
+1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3105              		.loc 1 1575 7 is_stmt 1 view .LVU1020
+1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3106              		.loc 1 1575 15 is_stmt 0 view .LVU1021
+ 3107 0080 0120     		movs	r0, #1
+ 3108              	.LVL211:
+1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3109              		.loc 1 1575 15 view .LVU1022
+ 3110 0082 7AE0     		b	.L219
+ 3111              	.LVL212:
+ 3112              	.L221:
+1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3113              		.loc 1 1605 5 is_stmt 1 view .LVU1023
+ 3114 0084 2368     		ldr	r3, [r4]
+ 3115 0086 0822     		movs	r2, #8
+ 3116 0088 DA61     		str	r2, [r3, #28]
+1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3117              		.loc 1 1608 5 view .LVU1024
+1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3118              		.loc 1 1608 9 is_stmt 0 view .LVU1025
+ 3119 008a 0096     		str	r6, [sp]
+ 3120 008c 2B46     		mov	r3, r5
+ 3121 008e 0122     		movs	r2, #1
+ 3122 0090 4FF48031 		mov	r1, #65536
+ 3123 0094 2046     		mov	r0, r4
+ 3124 0096 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 3125              	.LVL213:
+1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3126              		.loc 1 1608 8 view .LVU1026
+ 3127 009a F0B9     		cbnz	r0, .L232
+ 3128              	.L222:
+1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3129              		.loc 1 1615 11 is_stmt 1 view .LVU1027
+1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3130              		.loc 1 1615 16 is_stmt 0 view .LVU1028
+ 3131 009c 638D     		ldrh	r3, [r4, #42]
+ 3132 009e 9BB2     		uxth	r3, r3
+1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3133              		.loc 1 1615 11 view .LVU1029
+ARM GAS  /tmp/ccVyGVF6.s 			page 204
+
+
+ 3134 00a0 002B     		cmp	r3, #0
+ 3135 00a2 3BD0     		beq	.L233
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 3136              		.loc 1 1618 7 is_stmt 1 view .LVU1030
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 3137              		.loc 1 1618 11 is_stmt 0 view .LVU1031
+ 3138 00a4 3246     		mov	r2, r6
+ 3139 00a6 2946     		mov	r1, r5
+ 3140 00a8 2046     		mov	r0, r4
+ 3141 00aa FFF7FEFF 		bl	I2C_WaitOnRXNEFlagUntilTimeout
+ 3142              	.LVL214:
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 3143              		.loc 1 1618 10 view .LVU1032
+ 3144 00ae D8B9     		cbnz	r0, .L234
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3145              		.loc 1 1640 7 is_stmt 1 view .LVU1033
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3146              		.loc 1 1640 38 is_stmt 0 view .LVU1034
+ 3147 00b0 2368     		ldr	r3, [r4]
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3148              		.loc 1 1640 48 view .LVU1035
+ 3149 00b2 5A6A     		ldr	r2, [r3, #36]
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3150              		.loc 1 1640 12 view .LVU1036
+ 3151 00b4 636A     		ldr	r3, [r4, #36]
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3152              		.loc 1 1640 23 view .LVU1037
+ 3153 00b6 1A70     		strb	r2, [r3]
+1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3154              		.loc 1 1643 7 is_stmt 1 view .LVU1038
+1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3155              		.loc 1 1643 11 is_stmt 0 view .LVU1039
+ 3156 00b8 636A     		ldr	r3, [r4, #36]
+1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3157              		.loc 1 1643 21 view .LVU1040
+ 3158 00ba 0133     		adds	r3, r3, #1
+ 3159 00bc 6362     		str	r3, [r4, #36]
+1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 3160              		.loc 1 1645 7 is_stmt 1 view .LVU1041
+1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 3161              		.loc 1 1645 11 is_stmt 0 view .LVU1042
+ 3162 00be B4F82AC0 		ldrh	ip, [r4, #42]
+ 3163 00c2 1FFA8CFC 		uxth	ip, ip
+1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 3164              		.loc 1 1645 22 view .LVU1043
+ 3165 00c6 0CF1FF3C 		add	ip, ip, #-1
+ 3166 00ca 1FFA8CFC 		uxth	ip, ip
+ 3167 00ce A4F82AC0 		strh	ip, [r4, #42]	@ movhi
+1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3168              		.loc 1 1646 7 is_stmt 1 view .LVU1044
+1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3169              		.loc 1 1646 11 is_stmt 0 view .LVU1045
+ 3170 00d2 238D     		ldrh	r3, [r4, #40]
+1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3171              		.loc 1 1646 21 view .LVU1046
+ 3172 00d4 013B     		subs	r3, r3, #1
+ 3173 00d6 2385     		strh	r3, [r4, #40]	@ movhi
+ARM GAS  /tmp/ccVyGVF6.s 			page 205
+
+
+ 3174 00d8 E0E7     		b	.L222
+ 3175              	.L232:
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 3176              		.loc 1 1611 7 is_stmt 1 view .LVU1047
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 3177              		.loc 1 1611 11 is_stmt 0 view .LVU1048
+ 3178 00da 2268     		ldr	r2, [r4]
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 3179              		.loc 1 1611 27 view .LVU1049
+ 3180 00dc 5368     		ldr	r3, [r2, #4]
+ 3181 00de 43F40043 		orr	r3, r3, #32768
+ 3182 00e2 5360     		str	r3, [r2, #4]
+1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3183              		.loc 1 1612 7 is_stmt 1 view .LVU1050
+1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3184              		.loc 1 1612 14 is_stmt 0 view .LVU1051
+ 3185 00e4 0120     		movs	r0, #1
+ 3186 00e6 48E0     		b	.L219
+ 3187              	.L234:
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3188              		.loc 1 1621 9 is_stmt 1 view .LVU1052
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3189              		.loc 1 1621 13 is_stmt 0 view .LVU1053
+ 3190 00e8 2268     		ldr	r2, [r4]
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3191              		.loc 1 1621 29 view .LVU1054
+ 3192 00ea 5368     		ldr	r3, [r2, #4]
+ 3193 00ec 43F40043 		orr	r3, r3, #32768
+ 3194 00f0 5360     		str	r3, [r2, #4]
+1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 3195              		.loc 1 1624 9 is_stmt 1 view .LVU1055
+1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 3196              		.loc 1 1624 13 is_stmt 0 view .LVU1056
+ 3197 00f2 2368     		ldr	r3, [r4]
+ 3198 00f4 9A69     		ldr	r2, [r3, #24]
+1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 3199              		.loc 1 1624 12 view .LVU1057
+ 3200 00f6 12F0040F 		tst	r2, #4
+ 3201 00fa 0DD0     		beq	.L224
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3202              		.loc 1 1627 11 is_stmt 1 view .LVU1058
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3203              		.loc 1 1627 52 is_stmt 0 view .LVU1059
+ 3204 00fc 5A6A     		ldr	r2, [r3, #36]
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3205              		.loc 1 1627 16 view .LVU1060
+ 3206 00fe 636A     		ldr	r3, [r4, #36]
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3207              		.loc 1 1627 27 view .LVU1061
+ 3208 0100 1A70     		strb	r2, [r3]
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3209              		.loc 1 1630 11 is_stmt 1 view .LVU1062
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3210              		.loc 1 1630 15 is_stmt 0 view .LVU1063
+ 3211 0102 636A     		ldr	r3, [r4, #36]
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3212              		.loc 1 1630 25 view .LVU1064
+ARM GAS  /tmp/ccVyGVF6.s 			page 206
+
+
+ 3213 0104 0133     		adds	r3, r3, #1
+ 3214 0106 6362     		str	r3, [r4, #36]
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize--;
+ 3215              		.loc 1 1632 11 is_stmt 1 view .LVU1065
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize--;
+ 3216              		.loc 1 1632 15 is_stmt 0 view .LVU1066
+ 3217 0108 638D     		ldrh	r3, [r4, #42]
+ 3218 010a 9BB2     		uxth	r3, r3
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->XferSize--;
+ 3219              		.loc 1 1632 26 view .LVU1067
+ 3220 010c 013B     		subs	r3, r3, #1
+ 3221 010e 9BB2     		uxth	r3, r3
+ 3222 0110 6385     		strh	r3, [r4, #42]	@ movhi
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 3223              		.loc 1 1633 11 is_stmt 1 view .LVU1068
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 3224              		.loc 1 1633 15 is_stmt 0 view .LVU1069
+ 3225 0112 238D     		ldrh	r3, [r4, #40]
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 3226              		.loc 1 1633 25 view .LVU1070
+ 3227 0114 013B     		subs	r3, r3, #1
+ 3228 0116 2385     		strh	r3, [r4, #40]	@ movhi
+ 3229              	.L224:
+1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 3230              		.loc 1 1636 9 is_stmt 1 view .LVU1071
+1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 3231              		.loc 1 1636 16 is_stmt 0 view .LVU1072
+ 3232 0118 0120     		movs	r0, #1
+ 3233 011a 2EE0     		b	.L219
+ 3234              	.L233:
+1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3235              		.loc 1 1650 5 is_stmt 1 view .LVU1073
+1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3236              		.loc 1 1650 9 is_stmt 0 view .LVU1074
+ 3237 011c 3246     		mov	r2, r6
+ 3238 011e 2946     		mov	r1, r5
+ 3239 0120 2046     		mov	r0, r4
+ 3240 0122 FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 3241              	.LVL215:
+1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3242              		.loc 1 1650 8 view .LVU1075
+ 3243 0126 30B1     		cbz	r0, .L226
+1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 3244              		.loc 1 1653 7 is_stmt 1 view .LVU1076
+1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 3245              		.loc 1 1653 11 is_stmt 0 view .LVU1077
+ 3246 0128 2268     		ldr	r2, [r4]
+1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 3247              		.loc 1 1653 27 view .LVU1078
+ 3248 012a 5368     		ldr	r3, [r2, #4]
+ 3249 012c 43F40043 		orr	r3, r3, #32768
+ 3250 0130 5360     		str	r3, [r2, #4]
+1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3251              		.loc 1 1654 7 is_stmt 1 view .LVU1079
+1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3252              		.loc 1 1654 14 is_stmt 0 view .LVU1080
+ 3253 0132 0120     		movs	r0, #1
+ARM GAS  /tmp/ccVyGVF6.s 			page 207
+
+
+ 3254 0134 21E0     		b	.L219
+ 3255              	.L226:
+1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3256              		.loc 1 1658 5 is_stmt 1 view .LVU1081
+ 3257 0136 2368     		ldr	r3, [r4]
+ 3258 0138 2022     		movs	r2, #32
+ 3259 013a DA61     		str	r2, [r3, #28]
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3260              		.loc 1 1661 5 view .LVU1082
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3261              		.loc 1 1661 9 is_stmt 0 view .LVU1083
+ 3262 013c 0096     		str	r6, [sp]
+ 3263 013e 2B46     		mov	r3, r5
+ 3264 0140 0122     		movs	r2, #1
+ 3265 0142 4FF40041 		mov	r1, #32768
+ 3266 0146 2046     		mov	r0, r4
+ 3267 0148 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 3268              	.LVL216:
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3269              		.loc 1 1661 8 view .LVU1084
+ 3270 014c 30B1     		cbz	r0, .L227
+1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 3271              		.loc 1 1664 7 is_stmt 1 view .LVU1085
+1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 3272              		.loc 1 1664 11 is_stmt 0 view .LVU1086
+ 3273 014e 2268     		ldr	r2, [r4]
+1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 3274              		.loc 1 1664 27 view .LVU1087
+ 3275 0150 5368     		ldr	r3, [r2, #4]
+ 3276 0152 43F40043 		orr	r3, r3, #32768
+ 3277 0156 5360     		str	r3, [r2, #4]
+1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3278              		.loc 1 1665 7 is_stmt 1 view .LVU1088
+1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3279              		.loc 1 1665 14 is_stmt 0 view .LVU1089
+ 3280 0158 0120     		movs	r0, #1
+ 3281 015a 0EE0     		b	.L219
+ 3282              	.L227:
+1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3283              		.loc 1 1669 5 is_stmt 1 view .LVU1090
+1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3284              		.loc 1 1669 9 is_stmt 0 view .LVU1091
+ 3285 015c 2268     		ldr	r2, [r4]
+1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3286              		.loc 1 1669 25 view .LVU1092
+ 3287 015e 5368     		ldr	r3, [r2, #4]
+ 3288 0160 43F40043 		orr	r3, r3, #32768
+ 3289 0164 5360     		str	r3, [r2, #4]
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 3290              		.loc 1 1671 5 is_stmt 1 view .LVU1093
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 3291              		.loc 1 1671 17 is_stmt 0 view .LVU1094
+ 3292 0166 2023     		movs	r3, #32
+ 3293 0168 84F84130 		strb	r3, [r4, #65]
+1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3294              		.loc 1 1672 5 is_stmt 1 view .LVU1095
+1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 208
+
+
+ 3295              		.loc 1 1672 17 is_stmt 0 view .LVU1096
+ 3296 016c 0023     		movs	r3, #0
+ 3297 016e 84F84230 		strb	r3, [r4, #66]
+1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3298              		.loc 1 1675 5 is_stmt 1 view .LVU1097
+1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3299              		.loc 1 1675 5 view .LVU1098
+ 3300 0172 84F84030 		strb	r3, [r4, #64]
+1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3301              		.loc 1 1675 5 view .LVU1099
+1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3302              		.loc 1 1677 5 view .LVU1100
+1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3303              		.loc 1 1677 12 is_stmt 0 view .LVU1101
+ 3304 0176 00E0     		b	.L219
+ 3305              	.LVL217:
+ 3306              	.L228:
+1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3307              		.loc 1 1681 12 view .LVU1102
+ 3308 0178 0220     		movs	r0, #2
+ 3309              	.LVL218:
+ 3310              	.L219:
+1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3311              		.loc 1 1683 1 view .LVU1103
+ 3312 017a 02B0     		add	sp, sp, #8
+ 3313              	.LCFI33:
+ 3314              		.cfi_remember_state
+ 3315              		.cfi_def_cfa_offset 24
+ 3316              		@ sp needed
+ 3317 017c BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 3318              	.LVL219:
+ 3319              	.L229:
+ 3320              	.LCFI34:
+ 3321              		.cfi_restore_state
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3322              		.loc 1 1578 5 view .LVU1104
+ 3323 0180 0220     		movs	r0, #2
+ 3324              	.LVL220:
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3325              		.loc 1 1578 5 view .LVU1105
+ 3326 0182 FAE7     		b	.L219
+ 3327              		.cfi_endproc
+ 3328              	.LFE148:
+ 3330              		.section	.text.HAL_I2C_Master_Transmit_IT,"ax",%progbits
+ 3331              		.align	1
+ 3332              		.global	HAL_I2C_Master_Transmit_IT
+ 3333              		.syntax unified
+ 3334              		.thumb
+ 3335              		.thumb_func
+ 3336              		.fpu fpv5-d16
+ 3338              	HAL_I2C_Master_Transmit_IT:
+ 3339              	.LVL221:
+ 3340              	.LFB149:
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 3341              		.loc 1 1697 1 is_stmt 1 view -0
+ 3342              		.cfi_startproc
+ 3343              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccVyGVF6.s 			page 209
+
+
+ 3344              		@ frame_needed = 0, uses_anonymous_args = 0
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 3345              		.loc 1 1697 1 is_stmt 0 view .LVU1107
+ 3346 0000 30B5     		push	{r4, r5, lr}
+ 3347              	.LCFI35:
+ 3348              		.cfi_def_cfa_offset 12
+ 3349              		.cfi_offset 4, -12
+ 3350              		.cfi_offset 5, -8
+ 3351              		.cfi_offset 14, -4
+ 3352 0002 83B0     		sub	sp, sp, #12
+ 3353              	.LCFI36:
+ 3354              		.cfi_def_cfa_offset 24
+ 3355 0004 0446     		mov	r4, r0
+1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3356              		.loc 1 1698 3 is_stmt 1 view .LVU1108
+1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3357              		.loc 1 1700 3 view .LVU1109
+1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3358              		.loc 1 1700 11 is_stmt 0 view .LVU1110
+ 3359 0006 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 3360              	.LVL222:
+1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3361              		.loc 1 1700 11 view .LVU1111
+ 3362 000a C0B2     		uxtb	r0, r0
+1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3363              		.loc 1 1700 6 view .LVU1112
+ 3364 000c 2028     		cmp	r0, #32
+ 3365 000e 4ED1     		bne	.L241
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3366              		.loc 1 1702 5 is_stmt 1 view .LVU1113
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3367              		.loc 1 1702 9 is_stmt 0 view .LVU1114
+ 3368 0010 2068     		ldr	r0, [r4]
+ 3369 0012 8569     		ldr	r5, [r0, #24]
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3370              		.loc 1 1702 8 view .LVU1115
+ 3371 0014 15F4004F 		tst	r5, #32768
+ 3372 0018 4BD1     		bne	.L242
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3373              		.loc 1 1708 5 is_stmt 1 view .LVU1116
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3374              		.loc 1 1708 5 view .LVU1117
+ 3375 001a 94F84050 		ldrb	r5, [r4, #64]	@ zero_extendqisi2
+ 3376 001e 012D     		cmp	r5, #1
+ 3377 0020 49D0     		beq	.L243
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3378              		.loc 1 1708 5 discriminator 2 view .LVU1118
+ 3379 0022 0125     		movs	r5, #1
+ 3380 0024 84F84050 		strb	r5, [r4, #64]
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3381              		.loc 1 1708 5 discriminator 2 view .LVU1119
+1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 3382              		.loc 1 1710 5 discriminator 2 view .LVU1120
+1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 3383              		.loc 1 1710 23 is_stmt 0 discriminator 2 view .LVU1121
+ 3384 0028 2125     		movs	r5, #33
+ 3385 002a 84F84150 		strb	r5, [r4, #65]
+ARM GAS  /tmp/ccVyGVF6.s 			page 210
+
+
+1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3386              		.loc 1 1711 5 is_stmt 1 discriminator 2 view .LVU1122
+1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3387              		.loc 1 1711 23 is_stmt 0 discriminator 2 view .LVU1123
+ 3388 002e 1025     		movs	r5, #16
+ 3389 0030 84F84250 		strb	r5, [r4, #66]
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3390              		.loc 1 1712 5 is_stmt 1 discriminator 2 view .LVU1124
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3391              		.loc 1 1712 23 is_stmt 0 discriminator 2 view .LVU1125
+ 3392 0034 0025     		movs	r5, #0
+ 3393 0036 6564     		str	r5, [r4, #68]
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3394              		.loc 1 1715 5 is_stmt 1 discriminator 2 view .LVU1126
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3395              		.loc 1 1715 23 is_stmt 0 discriminator 2 view .LVU1127
+ 3396 0038 6262     		str	r2, [r4, #36]
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3397              		.loc 1 1716 5 is_stmt 1 discriminator 2 view .LVU1128
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3398              		.loc 1 1716 23 is_stmt 0 discriminator 2 view .LVU1129
+ 3399 003a 6385     		strh	r3, [r4, #42]	@ movhi
+1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 3400              		.loc 1 1717 5 is_stmt 1 discriminator 2 view .LVU1130
+1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 3401              		.loc 1 1717 23 is_stmt 0 discriminator 2 view .LVU1131
+ 3402 003c 1F4B     		ldr	r3, .L245
+ 3403              	.LVL223:
+1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 3404              		.loc 1 1717 23 discriminator 2 view .LVU1132
+ 3405 003e E362     		str	r3, [r4, #44]
+ 3406              	.LVL224:
+1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3407              		.loc 1 1718 5 is_stmt 1 discriminator 2 view .LVU1133
+1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3408              		.loc 1 1718 23 is_stmt 0 discriminator 2 view .LVU1134
+ 3409 0040 1F4B     		ldr	r3, .L245+4
+ 3410 0042 6363     		str	r3, [r4, #52]
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3411              		.loc 1 1720 5 is_stmt 1 discriminator 2 view .LVU1135
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3412              		.loc 1 1720 13 is_stmt 0 discriminator 2 view .LVU1136
+ 3413 0044 638D     		ldrh	r3, [r4, #42]
+ 3414 0046 9BB2     		uxth	r3, r3
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3415              		.loc 1 1720 8 discriminator 2 view .LVU1137
+ 3416 0048 FF2B     		cmp	r3, #255
+ 3417 004a 24D9     		bls	.L237
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 3418              		.loc 1 1722 7 is_stmt 1 view .LVU1138
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 3419              		.loc 1 1722 22 is_stmt 0 view .LVU1139
+ 3420 004c FF23     		movs	r3, #255
+ 3421 004e 2385     		strh	r3, [r4, #40]	@ movhi
+1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3422              		.loc 1 1723 7 is_stmt 1 view .LVU1140
+ 3423              	.LVL225:
+ARM GAS  /tmp/ccVyGVF6.s 			page 211
+
+
+1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3424              		.loc 1 1723 16 is_stmt 0 view .LVU1141
+ 3425 0050 4FF08073 		mov	r3, #16777216
+ 3426              	.LVL226:
+ 3427              	.L238:
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3428              		.loc 1 1733 5 is_stmt 1 view .LVU1142
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3429              		.loc 1 1733 13 is_stmt 0 view .LVU1143
+ 3430 0054 258D     		ldrh	r5, [r4, #40]
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3431              		.loc 1 1733 8 view .LVU1144
+ 3432 0056 1DB3     		cbz	r5, .L239
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3433              		.loc 1 1737 7 is_stmt 1 view .LVU1145
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3434              		.loc 1 1737 30 is_stmt 0 view .LVU1146
+ 3435 0058 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+ 3436              	.LVL227:
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3437              		.loc 1 1737 28 view .LVU1147
+ 3438 005a 8262     		str	r2, [r0, #40]
+ 3439              	.LVL228:
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3440              		.loc 1 1740 7 is_stmt 1 view .LVU1148
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3441              		.loc 1 1740 11 is_stmt 0 view .LVU1149
+ 3442 005c 626A     		ldr	r2, [r4, #36]
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3443              		.loc 1 1740 21 view .LVU1150
+ 3444 005e 0132     		adds	r2, r2, #1
+ 3445 0060 6262     		str	r2, [r4, #36]
+1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 3446              		.loc 1 1742 7 is_stmt 1 view .LVU1151
+1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 3447              		.loc 1 1742 11 is_stmt 0 view .LVU1152
+ 3448 0062 628D     		ldrh	r2, [r4, #42]
+ 3449 0064 92B2     		uxth	r2, r2
+1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 3450              		.loc 1 1742 22 view .LVU1153
+ 3451 0066 013A     		subs	r2, r2, #1
+ 3452 0068 92B2     		uxth	r2, r2
+ 3453 006a 6285     		strh	r2, [r4, #42]	@ movhi
+1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3454              		.loc 1 1743 7 is_stmt 1 view .LVU1154
+1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3455              		.loc 1 1743 11 is_stmt 0 view .LVU1155
+ 3456 006c 228D     		ldrh	r2, [r4, #40]
+1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3457              		.loc 1 1743 21 view .LVU1156
+ 3458 006e 013A     		subs	r2, r2, #1
+ 3459 0070 92B2     		uxth	r2, r2
+ 3460 0072 2285     		strh	r2, [r4, #40]	@ movhi
+1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 3461              		.loc 1 1745 7 is_stmt 1 view .LVU1157
+ 3462 0074 0132     		adds	r2, r2, #1
+ 3463 0076 1348     		ldr	r0, .L245+8
+ARM GAS  /tmp/ccVyGVF6.s 			page 212
+
+
+ 3464 0078 0090     		str	r0, [sp]
+ 3465 007a D2B2     		uxtb	r2, r2
+ 3466 007c 2046     		mov	r0, r4
+ 3467 007e FFF7FEFF 		bl	I2C_TransferConfig
+ 3468              	.LVL229:
+ 3469              	.L240:
+1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3470              		.loc 1 1755 5 view .LVU1158
+1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3471              		.loc 1 1755 5 view .LVU1159
+ 3472 0082 0025     		movs	r5, #0
+ 3473 0084 84F84050 		strb	r5, [r4, #64]
+1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3474              		.loc 1 1755 5 view .LVU1160
+1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3475              		.loc 1 1765 5 view .LVU1161
+ 3476 0088 0121     		movs	r1, #1
+ 3477 008a 2046     		mov	r0, r4
+ 3478 008c FFF7FEFF 		bl	I2C_Enable_IRQ
+ 3479              	.LVL230:
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3480              		.loc 1 1767 5 view .LVU1162
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3481              		.loc 1 1767 12 is_stmt 0 view .LVU1163
+ 3482 0090 2846     		mov	r0, r5
+ 3483              	.L236:
+1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3484              		.loc 1 1773 1 view .LVU1164
+ 3485 0092 03B0     		add	sp, sp, #12
+ 3486              	.LCFI37:
+ 3487              		.cfi_remember_state
+ 3488              		.cfi_def_cfa_offset 12
+ 3489              		@ sp needed
+ 3490 0094 30BD     		pop	{r4, r5, pc}
+ 3491              	.LVL231:
+ 3492              	.L237:
+ 3493              	.LCFI38:
+ 3494              		.cfi_restore_state
+1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3495              		.loc 1 1727 7 is_stmt 1 view .LVU1165
+1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3496              		.loc 1 1727 28 is_stmt 0 view .LVU1166
+ 3497 0096 638D     		ldrh	r3, [r4, #42]
+1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3498              		.loc 1 1727 22 view .LVU1167
+ 3499 0098 2385     		strh	r3, [r4, #40]	@ movhi
+1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3500              		.loc 1 1728 7 is_stmt 1 view .LVU1168
+ 3501              	.LVL232:
+1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3502              		.loc 1 1728 16 is_stmt 0 view .LVU1169
+ 3503 009a 4FF00073 		mov	r3, #33554432
+ 3504 009e D9E7     		b	.L238
+ 3505              	.LVL233:
+ 3506              	.L239:
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 3507              		.loc 1 1750 7 is_stmt 1 view .LVU1170
+ARM GAS  /tmp/ccVyGVF6.s 			page 213
+
+
+ 3508 00a0 084A     		ldr	r2, .L245+8
+ 3509              	.LVL234:
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 3510              		.loc 1 1750 7 is_stmt 0 view .LVU1171
+ 3511 00a2 0092     		str	r2, [sp]
+ 3512              	.LVL235:
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 3513              		.loc 1 1750 7 view .LVU1172
+ 3514 00a4 EAB2     		uxtb	r2, r5
+ 3515 00a6 2046     		mov	r0, r4
+ 3516 00a8 FFF7FEFF 		bl	I2C_TransferConfig
+ 3517              	.LVL236:
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 3518              		.loc 1 1750 7 view .LVU1173
+ 3519 00ac E9E7     		b	.L240
+ 3520              	.LVL237:
+ 3521              	.L241:
+1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3522              		.loc 1 1771 12 view .LVU1174
+ 3523 00ae 0220     		movs	r0, #2
+ 3524 00b0 EFE7     		b	.L236
+ 3525              	.L242:
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3526              		.loc 1 1704 14 view .LVU1175
+ 3527 00b2 0220     		movs	r0, #2
+ 3528 00b4 EDE7     		b	.L236
+ 3529              	.L243:
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3530              		.loc 1 1708 5 view .LVU1176
+ 3531 00b6 0220     		movs	r0, #2
+ 3532 00b8 EBE7     		b	.L236
+ 3533              	.L246:
+ 3534 00ba 00BF     		.align	2
+ 3535              	.L245:
+ 3536 00bc 0000FFFF 		.word	-65536
+ 3537 00c0 00000000 		.word	I2C_Master_ISR_IT
+ 3538 00c4 00200080 		.word	-2147475456
+ 3539              		.cfi_endproc
+ 3540              	.LFE149:
+ 3542              		.section	.text.HAL_I2C_Master_Receive_IT,"ax",%progbits
+ 3543              		.align	1
+ 3544              		.global	HAL_I2C_Master_Receive_IT
+ 3545              		.syntax unified
+ 3546              		.thumb
+ 3547              		.thumb_func
+ 3548              		.fpu fpv5-d16
+ 3550              	HAL_I2C_Master_Receive_IT:
+ 3551              	.LVL238:
+ 3552              	.LFB150:
+1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 3553              		.loc 1 1787 1 is_stmt 1 view -0
+ 3554              		.cfi_startproc
+ 3555              		@ args = 0, pretend = 0, frame = 0
+ 3556              		@ frame_needed = 0, uses_anonymous_args = 0
+1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 3557              		.loc 1 1787 1 is_stmt 0 view .LVU1178
+ 3558 0000 30B5     		push	{r4, r5, lr}
+ARM GAS  /tmp/ccVyGVF6.s 			page 214
+
+
+ 3559              	.LCFI39:
+ 3560              		.cfi_def_cfa_offset 12
+ 3561              		.cfi_offset 4, -12
+ 3562              		.cfi_offset 5, -8
+ 3563              		.cfi_offset 14, -4
+ 3564 0002 83B0     		sub	sp, sp, #12
+ 3565              	.LCFI40:
+ 3566              		.cfi_def_cfa_offset 24
+ 3567 0004 0446     		mov	r4, r0
+1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3568              		.loc 1 1788 3 is_stmt 1 view .LVU1179
+1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3569              		.loc 1 1790 3 view .LVU1180
+1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3570              		.loc 1 1790 11 is_stmt 0 view .LVU1181
+ 3571 0006 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 3572              	.LVL239:
+1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3573              		.loc 1 1790 11 view .LVU1182
+ 3574 000a C0B2     		uxtb	r0, r0
+1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3575              		.loc 1 1790 6 view .LVU1183
+ 3576 000c 2028     		cmp	r0, #32
+ 3577 000e 37D1     		bne	.L251
+1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3578              		.loc 1 1792 5 is_stmt 1 view .LVU1184
+1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3579              		.loc 1 1792 9 is_stmt 0 view .LVU1185
+ 3580 0010 2068     		ldr	r0, [r4]
+ 3581 0012 8069     		ldr	r0, [r0, #24]
+1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3582              		.loc 1 1792 8 view .LVU1186
+ 3583 0014 10F4004F 		tst	r0, #32768
+ 3584 0018 34D1     		bne	.L252
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3585              		.loc 1 1798 5 is_stmt 1 view .LVU1187
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3586              		.loc 1 1798 5 view .LVU1188
+ 3587 001a 94F84000 		ldrb	r0, [r4, #64]	@ zero_extendqisi2
+ 3588 001e 0128     		cmp	r0, #1
+ 3589 0020 32D0     		beq	.L253
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3590              		.loc 1 1798 5 discriminator 2 view .LVU1189
+ 3591 0022 0120     		movs	r0, #1
+ 3592 0024 84F84000 		strb	r0, [r4, #64]
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3593              		.loc 1 1798 5 discriminator 2 view .LVU1190
+1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 3594              		.loc 1 1800 5 discriminator 2 view .LVU1191
+1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 3595              		.loc 1 1800 23 is_stmt 0 discriminator 2 view .LVU1192
+ 3596 0028 2220     		movs	r0, #34
+ 3597 002a 84F84100 		strb	r0, [r4, #65]
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3598              		.loc 1 1801 5 is_stmt 1 discriminator 2 view .LVU1193
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3599              		.loc 1 1801 23 is_stmt 0 discriminator 2 view .LVU1194
+ARM GAS  /tmp/ccVyGVF6.s 			page 215
+
+
+ 3600 002e 1020     		movs	r0, #16
+ 3601 0030 84F84200 		strb	r0, [r4, #66]
+1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3602              		.loc 1 1802 5 is_stmt 1 discriminator 2 view .LVU1195
+1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3603              		.loc 1 1802 23 is_stmt 0 discriminator 2 view .LVU1196
+ 3604 0034 0020     		movs	r0, #0
+ 3605 0036 6064     		str	r0, [r4, #68]
+1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3606              		.loc 1 1805 5 is_stmt 1 discriminator 2 view .LVU1197
+1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3607              		.loc 1 1805 23 is_stmt 0 discriminator 2 view .LVU1198
+ 3608 0038 6262     		str	r2, [r4, #36]
+1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3609              		.loc 1 1806 5 is_stmt 1 discriminator 2 view .LVU1199
+1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3610              		.loc 1 1806 23 is_stmt 0 discriminator 2 view .LVU1200
+ 3611 003a 6385     		strh	r3, [r4, #42]	@ movhi
+1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 3612              		.loc 1 1807 5 is_stmt 1 discriminator 2 view .LVU1201
+1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 3613              		.loc 1 1807 23 is_stmt 0 discriminator 2 view .LVU1202
+ 3614 003c 134B     		ldr	r3, .L255
+ 3615              	.LVL240:
+1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 3616              		.loc 1 1807 23 discriminator 2 view .LVU1203
+ 3617 003e E362     		str	r3, [r4, #44]
+ 3618              	.LVL241:
+1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3619              		.loc 1 1808 5 is_stmt 1 discriminator 2 view .LVU1204
+1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3620              		.loc 1 1808 23 is_stmt 0 discriminator 2 view .LVU1205
+ 3621 0040 134B     		ldr	r3, .L255+4
+ 3622 0042 6363     		str	r3, [r4, #52]
+1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3623              		.loc 1 1810 5 is_stmt 1 discriminator 2 view .LVU1206
+1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3624              		.loc 1 1810 13 is_stmt 0 discriminator 2 view .LVU1207
+ 3625 0044 638D     		ldrh	r3, [r4, #42]
+ 3626 0046 9BB2     		uxth	r3, r3
+1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3627              		.loc 1 1810 8 discriminator 2 view .LVU1208
+ 3628 0048 FF2B     		cmp	r3, #255
+ 3629 004a 14D9     		bls	.L249
+1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 3630              		.loc 1 1812 7 is_stmt 1 view .LVU1209
+1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 3631              		.loc 1 1812 22 is_stmt 0 view .LVU1210
+ 3632 004c 0123     		movs	r3, #1
+ 3633 004e 2385     		strh	r3, [r4, #40]	@ movhi
+1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3634              		.loc 1 1813 7 is_stmt 1 view .LVU1211
+ 3635              	.LVL242:
+1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3636              		.loc 1 1813 16 is_stmt 0 view .LVU1212
+ 3637 0050 4FF08073 		mov	r3, #16777216
+ 3638              	.LVL243:
+ARM GAS  /tmp/ccVyGVF6.s 			page 216
+
+
+ 3639              	.L250:
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3640              		.loc 1 1823 5 is_stmt 1 view .LVU1213
+ 3641 0054 0F4A     		ldr	r2, .L255+8
+ 3642              	.LVL244:
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3643              		.loc 1 1823 5 is_stmt 0 view .LVU1214
+ 3644 0056 0092     		str	r2, [sp]
+ 3645              	.LVL245:
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3646              		.loc 1 1823 5 view .LVU1215
+ 3647 0058 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 3648 005c 2046     		mov	r0, r4
+ 3649 005e FFF7FEFF 		bl	I2C_TransferConfig
+ 3650              	.LVL246:
+1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3651              		.loc 1 1826 5 is_stmt 1 view .LVU1216
+1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3652              		.loc 1 1826 5 view .LVU1217
+ 3653 0062 0025     		movs	r5, #0
+ 3654 0064 84F84050 		strb	r5, [r4, #64]
+1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3655              		.loc 1 1826 5 view .LVU1218
+1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3656              		.loc 1 1836 5 view .LVU1219
+ 3657 0068 0221     		movs	r1, #2
+ 3658 006a 2046     		mov	r0, r4
+ 3659 006c FFF7FEFF 		bl	I2C_Enable_IRQ
+ 3660              	.LVL247:
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3661              		.loc 1 1838 5 view .LVU1220
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3662              		.loc 1 1838 12 is_stmt 0 view .LVU1221
+ 3663 0070 2846     		mov	r0, r5
+ 3664              	.L248:
+1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3665              		.loc 1 1844 1 view .LVU1222
+ 3666 0072 03B0     		add	sp, sp, #12
+ 3667              	.LCFI41:
+ 3668              		.cfi_remember_state
+ 3669              		.cfi_def_cfa_offset 12
+ 3670              		@ sp needed
+ 3671 0074 30BD     		pop	{r4, r5, pc}
+ 3672              	.LVL248:
+ 3673              	.L249:
+ 3674              	.LCFI42:
+ 3675              		.cfi_restore_state
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3676              		.loc 1 1817 7 is_stmt 1 view .LVU1223
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3677              		.loc 1 1817 28 is_stmt 0 view .LVU1224
+ 3678 0076 638D     		ldrh	r3, [r4, #42]
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 3679              		.loc 1 1817 22 view .LVU1225
+ 3680 0078 2385     		strh	r3, [r4, #40]	@ movhi
+1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3681              		.loc 1 1818 7 is_stmt 1 view .LVU1226
+ARM GAS  /tmp/ccVyGVF6.s 			page 217
+
+
+ 3682              	.LVL249:
+1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3683              		.loc 1 1818 16 is_stmt 0 view .LVU1227
+ 3684 007a 4FF00073 		mov	r3, #33554432
+ 3685 007e E9E7     		b	.L250
+ 3686              	.LVL250:
+ 3687              	.L251:
+1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3688              		.loc 1 1842 12 view .LVU1228
+ 3689 0080 0220     		movs	r0, #2
+ 3690 0082 F6E7     		b	.L248
+ 3691              	.L252:
+1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3692              		.loc 1 1794 14 view .LVU1229
+ 3693 0084 0220     		movs	r0, #2
+ 3694 0086 F4E7     		b	.L248
+ 3695              	.L253:
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3696              		.loc 1 1798 5 view .LVU1230
+ 3697 0088 0220     		movs	r0, #2
+ 3698 008a F2E7     		b	.L248
+ 3699              	.L256:
+ 3700              		.align	2
+ 3701              	.L255:
+ 3702 008c 0000FFFF 		.word	-65536
+ 3703 0090 00000000 		.word	I2C_Master_ISR_IT
+ 3704 0094 00240080 		.word	-2147474432
+ 3705              		.cfi_endproc
+ 3706              	.LFE150:
+ 3708              		.section	.text.HAL_I2C_Slave_Transmit_IT,"ax",%progbits
+ 3709              		.align	1
+ 3710              		.global	HAL_I2C_Slave_Transmit_IT
+ 3711              		.syntax unified
+ 3712              		.thumb
+ 3713              		.thumb_func
+ 3714              		.fpu fpv5-d16
+ 3716              	HAL_I2C_Slave_Transmit_IT:
+ 3717              	.LVL251:
+ 3718              	.LFB151:
+1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 3719              		.loc 1 1855 1 is_stmt 1 view -0
+ 3720              		.cfi_startproc
+ 3721              		@ args = 0, pretend = 0, frame = 0
+ 3722              		@ frame_needed = 0, uses_anonymous_args = 0
+1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3723              		.loc 1 1856 3 view .LVU1232
+1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3724              		.loc 1 1856 11 is_stmt 0 view .LVU1233
+ 3725 0000 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 3726 0004 DBB2     		uxtb	r3, r3
+1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3727              		.loc 1 1856 6 view .LVU1234
+ 3728 0006 202B     		cmp	r3, #32
+ 3729 0008 38D1     		bne	.L260
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3730              		.loc 1 1859 5 is_stmt 1 view .LVU1235
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 218
+
+
+ 3731              		.loc 1 1859 5 view .LVU1236
+ 3732 000a 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 3733 000e 012B     		cmp	r3, #1
+ 3734 0010 36D0     		beq	.L261
+1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 3735              		.loc 1 1855 1 is_stmt 0 discriminator 2 view .LVU1237
+ 3736 0012 10B5     		push	{r4, lr}
+ 3737              	.LCFI43:
+ 3738              		.cfi_def_cfa_offset 8
+ 3739              		.cfi_offset 4, -8
+ 3740              		.cfi_offset 14, -4
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3741              		.loc 1 1859 5 is_stmt 1 discriminator 2 view .LVU1238
+ 3742 0014 0123     		movs	r3, #1
+ 3743 0016 80F84030 		strb	r3, [r0, #64]
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3744              		.loc 1 1859 5 discriminator 2 view .LVU1239
+1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 3745              		.loc 1 1861 5 discriminator 2 view .LVU1240
+1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 3746              		.loc 1 1861 23 is_stmt 0 discriminator 2 view .LVU1241
+ 3747 001a 2123     		movs	r3, #33
+ 3748 001c 80F84130 		strb	r3, [r0, #65]
+1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3749              		.loc 1 1862 5 is_stmt 1 discriminator 2 view .LVU1242
+1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3750              		.loc 1 1862 23 is_stmt 0 discriminator 2 view .LVU1243
+ 3751 0020 2023     		movs	r3, #32
+ 3752 0022 80F84230 		strb	r3, [r0, #66]
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3753              		.loc 1 1863 5 is_stmt 1 discriminator 2 view .LVU1244
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3754              		.loc 1 1863 23 is_stmt 0 discriminator 2 view .LVU1245
+ 3755 0026 0023     		movs	r3, #0
+ 3756 0028 4364     		str	r3, [r0, #68]
+1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3757              		.loc 1 1866 5 is_stmt 1 discriminator 2 view .LVU1246
+1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3758              		.loc 1 1866 9 is_stmt 0 discriminator 2 view .LVU1247
+ 3759 002a 0468     		ldr	r4, [r0]
+1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3760              		.loc 1 1866 25 discriminator 2 view .LVU1248
+ 3761 002c 6368     		ldr	r3, [r4, #4]
+ 3762 002e 23F40043 		bic	r3, r3, #32768
+ 3763 0032 6360     		str	r3, [r4, #4]
+1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3764              		.loc 1 1869 5 is_stmt 1 discriminator 2 view .LVU1249
+1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3765              		.loc 1 1869 23 is_stmt 0 discriminator 2 view .LVU1250
+ 3766 0034 4162     		str	r1, [r0, #36]
+1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 3767              		.loc 1 1870 5 is_stmt 1 discriminator 2 view .LVU1251
+1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 3768              		.loc 1 1870 23 is_stmt 0 discriminator 2 view .LVU1252
+ 3769 0036 4285     		strh	r2, [r0, #42]	@ movhi
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3770              		.loc 1 1871 5 is_stmt 1 discriminator 2 view .LVU1253
+ARM GAS  /tmp/ccVyGVF6.s 			page 219
+
+
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3771              		.loc 1 1871 29 is_stmt 0 discriminator 2 view .LVU1254
+ 3772 0038 438D     		ldrh	r3, [r0, #42]
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3773              		.loc 1 1871 23 discriminator 2 view .LVU1255
+ 3774 003a 0385     		strh	r3, [r0, #40]	@ movhi
+1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 3775              		.loc 1 1872 5 is_stmt 1 discriminator 2 view .LVU1256
+1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 3776              		.loc 1 1872 23 is_stmt 0 discriminator 2 view .LVU1257
+ 3777 003c 114B     		ldr	r3, .L267
+ 3778 003e C362     		str	r3, [r0, #44]
+1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3779              		.loc 1 1873 5 is_stmt 1 discriminator 2 view .LVU1258
+1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3780              		.loc 1 1873 23 is_stmt 0 discriminator 2 view .LVU1259
+ 3781 0040 114B     		ldr	r3, .L267+4
+ 3782 0042 4363     		str	r3, [r0, #52]
+1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3783              		.loc 1 1876 5 is_stmt 1 discriminator 2 view .LVU1260
+1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3784              		.loc 1 1876 19 is_stmt 0 discriminator 2 view .LVU1261
+ 3785 0044 036A     		ldr	r3, [r0, #32]
+1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 3786              		.loc 1 1876 8 discriminator 2 view .LVU1262
+ 3787 0046 B3F5003F 		cmp	r3, #131072
+ 3788 004a 08D0     		beq	.L266
+ 3789              	.LVL252:
+ 3790              	.L259:
+1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3791              		.loc 1 1890 5 is_stmt 1 view .LVU1263
+1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3792              		.loc 1 1890 5 view .LVU1264
+ 3793 004c 0024     		movs	r4, #0
+ 3794 004e 80F84040 		strb	r4, [r0, #64]
+1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3795              		.loc 1 1890 5 view .LVU1265
+1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3796              		.loc 1 1900 5 view .LVU1266
+ 3797 0052 48F20101 		movw	r1, #32769
+ 3798              	.LVL253:
+1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3799              		.loc 1 1900 5 is_stmt 0 view .LVU1267
+ 3800 0056 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 3801              	.LVL254:
+1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3802              		.loc 1 1902 5 is_stmt 1 view .LVU1268
+1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3803              		.loc 1 1902 12 is_stmt 0 view .LVU1269
+ 3804 005a 2046     		mov	r0, r4
+1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3805              		.loc 1 1908 1 view .LVU1270
+ 3806 005c 10BD     		pop	{r4, pc}
+ 3807              	.LVL255:
+ 3808              	.L266:
+1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3809              		.loc 1 1880 7 is_stmt 1 view .LVU1271
+ARM GAS  /tmp/ccVyGVF6.s 			page 220
+
+
+1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3810              		.loc 1 1880 11 is_stmt 0 view .LVU1272
+ 3811 005e 0368     		ldr	r3, [r0]
+1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3812              		.loc 1 1880 30 view .LVU1273
+ 3813 0060 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 3814              	.LVL256:
+1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3815              		.loc 1 1880 28 view .LVU1274
+ 3816 0062 9A62     		str	r2, [r3, #40]
+1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3817              		.loc 1 1883 7 is_stmt 1 view .LVU1275
+1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3818              		.loc 1 1883 11 is_stmt 0 view .LVU1276
+ 3819 0064 436A     		ldr	r3, [r0, #36]
+1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3820              		.loc 1 1883 21 view .LVU1277
+ 3821 0066 0133     		adds	r3, r3, #1
+ 3822 0068 4362     		str	r3, [r0, #36]
+1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 3823              		.loc 1 1885 7 is_stmt 1 view .LVU1278
+1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 3824              		.loc 1 1885 11 is_stmt 0 view .LVU1279
+ 3825 006a 438D     		ldrh	r3, [r0, #42]
+ 3826 006c 9BB2     		uxth	r3, r3
+1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 3827              		.loc 1 1885 22 view .LVU1280
+ 3828 006e 013B     		subs	r3, r3, #1
+ 3829 0070 9BB2     		uxth	r3, r3
+ 3830 0072 4385     		strh	r3, [r0, #42]	@ movhi
+1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3831              		.loc 1 1886 7 is_stmt 1 view .LVU1281
+1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3832              		.loc 1 1886 11 is_stmt 0 view .LVU1282
+ 3833 0074 038D     		ldrh	r3, [r0, #40]
+1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 3834              		.loc 1 1886 21 view .LVU1283
+ 3835 0076 013B     		subs	r3, r3, #1
+ 3836 0078 0385     		strh	r3, [r0, #40]	@ movhi
+ 3837 007a E7E7     		b	.L259
+ 3838              	.LVL257:
+ 3839              	.L260:
+ 3840              	.LCFI44:
+ 3841              		.cfi_def_cfa_offset 0
+ 3842              		.cfi_restore 4
+ 3843              		.cfi_restore 14
+1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3844              		.loc 1 1906 12 view .LVU1284
+ 3845 007c 0220     		movs	r0, #2
+ 3846              	.LVL258:
+1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3847              		.loc 1 1906 12 view .LVU1285
+ 3848 007e 7047     		bx	lr
+ 3849              	.LVL259:
+ 3850              	.L261:
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3851              		.loc 1 1859 5 view .LVU1286
+ARM GAS  /tmp/ccVyGVF6.s 			page 221
+
+
+ 3852 0080 0220     		movs	r0, #2
+ 3853              	.LVL260:
+1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3854              		.loc 1 1908 1 view .LVU1287
+ 3855 0082 7047     		bx	lr
+ 3856              	.L268:
+ 3857              		.align	2
+ 3858              	.L267:
+ 3859 0084 0000FFFF 		.word	-65536
+ 3860 0088 00000000 		.word	I2C_Slave_ISR_IT
+ 3861              		.cfi_endproc
+ 3862              	.LFE151:
+ 3864              		.section	.text.HAL_I2C_Slave_Receive_IT,"ax",%progbits
+ 3865              		.align	1
+ 3866              		.global	HAL_I2C_Slave_Receive_IT
+ 3867              		.syntax unified
+ 3868              		.thumb
+ 3869              		.thumb_func
+ 3870              		.fpu fpv5-d16
+ 3872              	HAL_I2C_Slave_Receive_IT:
+ 3873              	.LVL261:
+ 3874              	.LFB152:
+1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 3875              		.loc 1 1919 1 is_stmt 1 view -0
+ 3876              		.cfi_startproc
+ 3877              		@ args = 0, pretend = 0, frame = 0
+ 3878              		@ frame_needed = 0, uses_anonymous_args = 0
+1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 3879              		.loc 1 1919 1 is_stmt 0 view .LVU1289
+ 3880 0000 38B5     		push	{r3, r4, r5, lr}
+ 3881              	.LCFI45:
+ 3882              		.cfi_def_cfa_offset 16
+ 3883              		.cfi_offset 3, -16
+ 3884              		.cfi_offset 4, -12
+ 3885              		.cfi_offset 5, -8
+ 3886              		.cfi_offset 14, -4
+1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3887              		.loc 1 1920 3 is_stmt 1 view .LVU1290
+1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3888              		.loc 1 1920 11 is_stmt 0 view .LVU1291
+ 3889 0002 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 3890 0006 DBB2     		uxtb	r3, r3
+1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 3891              		.loc 1 1920 6 view .LVU1292
+ 3892 0008 202B     		cmp	r3, #32
+ 3893 000a 23D1     		bne	.L271
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3894              		.loc 1 1923 5 is_stmt 1 view .LVU1293
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3895              		.loc 1 1923 5 view .LVU1294
+ 3896 000c 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 3897 0010 012B     		cmp	r3, #1
+ 3898 0012 21D0     		beq	.L272
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3899              		.loc 1 1923 5 discriminator 2 view .LVU1295
+ 3900 0014 0123     		movs	r3, #1
+ 3901 0016 80F84030 		strb	r3, [r0, #64]
+ARM GAS  /tmp/ccVyGVF6.s 			page 222
+
+
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3902              		.loc 1 1923 5 discriminator 2 view .LVU1296
+1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 3903              		.loc 1 1925 5 discriminator 2 view .LVU1297
+1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 3904              		.loc 1 1925 23 is_stmt 0 discriminator 2 view .LVU1298
+ 3905 001a 2223     		movs	r3, #34
+ 3906 001c 80F84130 		strb	r3, [r0, #65]
+1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3907              		.loc 1 1926 5 is_stmt 1 discriminator 2 view .LVU1299
+1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 3908              		.loc 1 1926 23 is_stmt 0 discriminator 2 view .LVU1300
+ 3909 0020 2023     		movs	r3, #32
+ 3910 0022 80F84230 		strb	r3, [r0, #66]
+1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3911              		.loc 1 1927 5 is_stmt 1 discriminator 2 view .LVU1301
+1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3912              		.loc 1 1927 23 is_stmt 0 discriminator 2 view .LVU1302
+ 3913 0026 0024     		movs	r4, #0
+ 3914 0028 4464     		str	r4, [r0, #68]
+1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3915              		.loc 1 1930 5 is_stmt 1 discriminator 2 view .LVU1303
+1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3916              		.loc 1 1930 9 is_stmt 0 discriminator 2 view .LVU1304
+ 3917 002a 0568     		ldr	r5, [r0]
+1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3918              		.loc 1 1930 25 discriminator 2 view .LVU1305
+ 3919 002c 6B68     		ldr	r3, [r5, #4]
+ 3920 002e 23F40043 		bic	r3, r3, #32768
+ 3921 0032 6B60     		str	r3, [r5, #4]
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3922              		.loc 1 1933 5 is_stmt 1 discriminator 2 view .LVU1306
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 3923              		.loc 1 1933 23 is_stmt 0 discriminator 2 view .LVU1307
+ 3924 0034 4162     		str	r1, [r0, #36]
+1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 3925              		.loc 1 1934 5 is_stmt 1 discriminator 2 view .LVU1308
+1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 3926              		.loc 1 1934 23 is_stmt 0 discriminator 2 view .LVU1309
+ 3927 0036 4285     		strh	r2, [r0, #42]	@ movhi
+1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3928              		.loc 1 1935 5 is_stmt 1 discriminator 2 view .LVU1310
+1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3929              		.loc 1 1935 29 is_stmt 0 discriminator 2 view .LVU1311
+ 3930 0038 438D     		ldrh	r3, [r0, #42]
+1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 3931              		.loc 1 1935 23 discriminator 2 view .LVU1312
+ 3932 003a 0385     		strh	r3, [r0, #40]	@ movhi
+1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 3933              		.loc 1 1936 5 is_stmt 1 discriminator 2 view .LVU1313
+1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 3934              		.loc 1 1936 23 is_stmt 0 discriminator 2 view .LVU1314
+ 3935 003c 074B     		ldr	r3, .L274
+ 3936 003e C362     		str	r3, [r0, #44]
+1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3937              		.loc 1 1937 5 is_stmt 1 discriminator 2 view .LVU1315
+1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 223
+
+
+ 3938              		.loc 1 1937 23 is_stmt 0 discriminator 2 view .LVU1316
+ 3939 0040 074B     		ldr	r3, .L274+4
+ 3940 0042 4363     		str	r3, [r0, #52]
+1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3941              		.loc 1 1940 5 is_stmt 1 discriminator 2 view .LVU1317
+1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3942              		.loc 1 1940 5 discriminator 2 view .LVU1318
+ 3943 0044 80F84040 		strb	r4, [r0, #64]
+1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3944              		.loc 1 1940 5 discriminator 2 view .LVU1319
+1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3945              		.loc 1 1950 5 discriminator 2 view .LVU1320
+ 3946 0048 48F20201 		movw	r1, #32770
+ 3947              	.LVL262:
+1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3948              		.loc 1 1950 5 is_stmt 0 discriminator 2 view .LVU1321
+ 3949 004c FFF7FEFF 		bl	I2C_Enable_IRQ
+ 3950              	.LVL263:
+1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3951              		.loc 1 1952 5 is_stmt 1 discriminator 2 view .LVU1322
+1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3952              		.loc 1 1952 12 is_stmt 0 discriminator 2 view .LVU1323
+ 3953 0050 2046     		mov	r0, r4
+ 3954              	.L270:
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3955              		.loc 1 1958 1 view .LVU1324
+ 3956 0052 38BD     		pop	{r3, r4, r5, pc}
+ 3957              	.LVL264:
+ 3958              	.L271:
+1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3959              		.loc 1 1956 12 view .LVU1325
+ 3960 0054 0220     		movs	r0, #2
+ 3961              	.LVL265:
+1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 3962              		.loc 1 1956 12 view .LVU1326
+ 3963 0056 FCE7     		b	.L270
+ 3964              	.LVL266:
+ 3965              	.L272:
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3966              		.loc 1 1923 5 view .LVU1327
+ 3967 0058 0220     		movs	r0, #2
+ 3968              	.LVL267:
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 3969              		.loc 1 1923 5 view .LVU1328
+ 3970 005a FAE7     		b	.L270
+ 3971              	.L275:
+ 3972              		.align	2
+ 3973              	.L274:
+ 3974 005c 0000FFFF 		.word	-65536
+ 3975 0060 00000000 		.word	I2C_Slave_ISR_IT
+ 3976              		.cfi_endproc
+ 3977              	.LFE152:
+ 3979              		.section	.text.HAL_I2C_Master_Transmit_DMA,"ax",%progbits
+ 3980              		.align	1
+ 3981              		.global	HAL_I2C_Master_Transmit_DMA
+ 3982              		.syntax unified
+ 3983              		.thumb
+ARM GAS  /tmp/ccVyGVF6.s 			page 224
+
+
+ 3984              		.thumb_func
+ 3985              		.fpu fpv5-d16
+ 3987              	HAL_I2C_Master_Transmit_DMA:
+ 3988              	.LVL268:
+ 3989              	.LFB153:
+1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 3990              		.loc 1 1972 1 is_stmt 1 view -0
+ 3991              		.cfi_startproc
+ 3992              		@ args = 0, pretend = 0, frame = 0
+ 3993              		@ frame_needed = 0, uses_anonymous_args = 0
+1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 3994              		.loc 1 1972 1 is_stmt 0 view .LVU1330
+ 3995 0000 70B5     		push	{r4, r5, r6, lr}
+ 3996              	.LCFI46:
+ 3997              		.cfi_def_cfa_offset 16
+ 3998              		.cfi_offset 4, -16
+ 3999              		.cfi_offset 5, -12
+ 4000              		.cfi_offset 6, -8
+ 4001              		.cfi_offset 14, -4
+ 4002 0002 82B0     		sub	sp, sp, #8
+ 4003              	.LCFI47:
+ 4004              		.cfi_def_cfa_offset 24
+ 4005 0004 0446     		mov	r4, r0
+1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 4006              		.loc 1 1973 3 is_stmt 1 view .LVU1331
+1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t sizetoxfer = 0U;
+ 4007              		.loc 1 1974 3 view .LVU1332
+1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4008              		.loc 1 1975 3 view .LVU1333
+ 4009              	.LVL269:
+1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4010              		.loc 1 1977 3 view .LVU1334
+1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4011              		.loc 1 1977 11 is_stmt 0 view .LVU1335
+ 4012 0006 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 4013              	.LVL270:
+1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4014              		.loc 1 1977 11 view .LVU1336
+ 4015 000a C0B2     		uxtb	r0, r0
+1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4016              		.loc 1 1977 6 view .LVU1337
+ 4017 000c 2028     		cmp	r0, #32
+ 4018 000e 40F09D80 		bne	.L286
+ 4019 0012 0D46     		mov	r5, r1
+1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4020              		.loc 1 1979 5 is_stmt 1 view .LVU1338
+1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4021              		.loc 1 1979 9 is_stmt 0 view .LVU1339
+ 4022 0014 2068     		ldr	r0, [r4]
+ 4023 0016 8169     		ldr	r1, [r0, #24]
+ 4024              	.LVL271:
+1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4025              		.loc 1 1979 8 view .LVU1340
+ 4026 0018 11F40041 		ands	r1, r1, #32768
+ 4027 001c 40F09980 		bne	.L287
+1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4028              		.loc 1 1985 5 is_stmt 1 view .LVU1341
+ARM GAS  /tmp/ccVyGVF6.s 			page 225
+
+
+1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4029              		.loc 1 1985 5 view .LVU1342
+ 4030 0020 94F84060 		ldrb	r6, [r4, #64]	@ zero_extendqisi2
+ 4031 0024 012E     		cmp	r6, #1
+ 4032 0026 00F09680 		beq	.L288
+1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4033              		.loc 1 1985 5 discriminator 2 view .LVU1343
+ 4034 002a 0126     		movs	r6, #1
+ 4035 002c 84F84060 		strb	r6, [r4, #64]
+1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4036              		.loc 1 1985 5 discriminator 2 view .LVU1344
+1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 4037              		.loc 1 1987 5 discriminator 2 view .LVU1345
+1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 4038              		.loc 1 1987 23 is_stmt 0 discriminator 2 view .LVU1346
+ 4039 0030 2126     		movs	r6, #33
+ 4040 0032 84F84160 		strb	r6, [r4, #65]
+1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4041              		.loc 1 1988 5 is_stmt 1 discriminator 2 view .LVU1347
+1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4042              		.loc 1 1988 23 is_stmt 0 discriminator 2 view .LVU1348
+ 4043 0036 1026     		movs	r6, #16
+ 4044 0038 84F84260 		strb	r6, [r4, #66]
+1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4045              		.loc 1 1989 5 is_stmt 1 discriminator 2 view .LVU1349
+1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4046              		.loc 1 1989 23 is_stmt 0 discriminator 2 view .LVU1350
+ 4047 003c 0026     		movs	r6, #0
+ 4048 003e 6664     		str	r6, [r4, #68]
+1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4049              		.loc 1 1992 5 is_stmt 1 discriminator 2 view .LVU1351
+1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4050              		.loc 1 1992 23 is_stmt 0 discriminator 2 view .LVU1352
+ 4051 0040 6262     		str	r2, [r4, #36]
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4052              		.loc 1 1993 5 is_stmt 1 discriminator 2 view .LVU1353
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4053              		.loc 1 1993 23 is_stmt 0 discriminator 2 view .LVU1354
+ 4054 0042 6385     		strh	r3, [r4, #42]	@ movhi
+1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 4055              		.loc 1 1994 5 is_stmt 1 discriminator 2 view .LVU1355
+1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 4056              		.loc 1 1994 23 is_stmt 0 discriminator 2 view .LVU1356
+ 4057 0044 454B     		ldr	r3, .L292
+ 4058              	.LVL272:
+1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 4059              		.loc 1 1994 23 discriminator 2 view .LVU1357
+ 4060 0046 E362     		str	r3, [r4, #44]
+ 4061              	.LVL273:
+1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4062              		.loc 1 1995 5 is_stmt 1 discriminator 2 view .LVU1358
+1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4063              		.loc 1 1995 23 is_stmt 0 discriminator 2 view .LVU1359
+ 4064 0048 454B     		ldr	r3, .L292+4
+ 4065 004a 6363     		str	r3, [r4, #52]
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4066              		.loc 1 1997 5 is_stmt 1 discriminator 2 view .LVU1360
+ARM GAS  /tmp/ccVyGVF6.s 			page 226
+
+
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4067              		.loc 1 1997 13 is_stmt 0 discriminator 2 view .LVU1361
+ 4068 004c 638D     		ldrh	r3, [r4, #42]
+ 4069 004e 9BB2     		uxth	r3, r3
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4070              		.loc 1 1997 8 discriminator 2 view .LVU1362
+ 4071 0050 FF2B     		cmp	r3, #255
+ 4072 0052 37D9     		bls	.L278
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 4073              		.loc 1 1999 7 is_stmt 1 view .LVU1363
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 4074              		.loc 1 1999 22 is_stmt 0 view .LVU1364
+ 4075 0054 FF23     		movs	r3, #255
+ 4076 0056 2385     		strh	r3, [r4, #40]	@ movhi
+2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4077              		.loc 1 2000 7 is_stmt 1 view .LVU1365
+ 4078              	.LVL274:
+2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4079              		.loc 1 2000 16 is_stmt 0 view .LVU1366
+ 4080 0058 4FF08076 		mov	r6, #16777216
+ 4081              	.LVL275:
+ 4082              	.L279:
+2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4083              		.loc 1 2008 5 is_stmt 1 view .LVU1367
+2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4084              		.loc 1 2008 13 is_stmt 0 view .LVU1368
+ 4085 005c 238D     		ldrh	r3, [r4, #40]
+2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4086              		.loc 1 2008 8 view .LVU1369
+ 4087 005e 63B1     		cbz	r3, .L280
+2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4088              		.loc 1 2012 7 is_stmt 1 view .LVU1370
+2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4089              		.loc 1 2012 30 is_stmt 0 view .LVU1371
+ 4090 0060 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
+2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4091              		.loc 1 2012 28 view .LVU1372
+ 4092 0062 8362     		str	r3, [r0, #40]
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4093              		.loc 1 2015 7 is_stmt 1 view .LVU1373
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4094              		.loc 1 2015 11 is_stmt 0 view .LVU1374
+ 4095 0064 636A     		ldr	r3, [r4, #36]
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4096              		.loc 1 2015 21 view .LVU1375
+ 4097 0066 0133     		adds	r3, r3, #1
+ 4098 0068 6362     		str	r3, [r4, #36]
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 4099              		.loc 1 2017 7 is_stmt 1 view .LVU1376
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 4100              		.loc 1 2017 24 is_stmt 0 view .LVU1377
+ 4101 006a 218D     		ldrh	r1, [r4, #40]
+ 4102              	.LVL276:
+2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 4103              		.loc 1 2018 7 is_stmt 1 view .LVU1378
+2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 4104              		.loc 1 2018 11 is_stmt 0 view .LVU1379
+ARM GAS  /tmp/ccVyGVF6.s 			page 227
+
+
+ 4105 006c 638D     		ldrh	r3, [r4, #42]
+ 4106 006e 9BB2     		uxth	r3, r3
+2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 4107              		.loc 1 2018 22 view .LVU1380
+ 4108 0070 013B     		subs	r3, r3, #1
+ 4109 0072 9BB2     		uxth	r3, r3
+ 4110 0074 6385     		strh	r3, [r4, #42]	@ movhi
+2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4111              		.loc 1 2019 7 is_stmt 1 view .LVU1381
+2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4112              		.loc 1 2019 21 is_stmt 0 view .LVU1382
+ 4113 0076 4B1E     		subs	r3, r1, #1
+ 4114 0078 2385     		strh	r3, [r4, #40]	@ movhi
+ 4115              	.LVL277:
+ 4116              	.L280:
+2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4117              		.loc 1 2022 5 is_stmt 1 view .LVU1383
+2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4118              		.loc 1 2022 13 is_stmt 0 view .LVU1384
+ 4119 007a 238D     		ldrh	r3, [r4, #40]
+2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4120              		.loc 1 2022 8 view .LVU1385
+ 4121 007c 002B     		cmp	r3, #0
+ 4122 007e 51D0     		beq	.L281
+2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4123              		.loc 1 2024 7 is_stmt 1 view .LVU1386
+2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4124              		.loc 1 2024 15 is_stmt 0 view .LVU1387
+ 4125 0080 A36B     		ldr	r3, [r4, #56]
+2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4126              		.loc 1 2024 10 view .LVU1388
+ 4127 0082 23B3     		cbz	r3, .L282
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4128              		.loc 1 2027 9 is_stmt 1 view .LVU1389
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4129              		.loc 1 2027 40 is_stmt 0 view .LVU1390
+ 4130 0084 374A     		ldr	r2, .L292+8
+ 4131              	.LVL278:
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4132              		.loc 1 2027 40 view .LVU1391
+ 4133 0086 DA63     		str	r2, [r3, #60]
+2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4134              		.loc 1 2030 9 is_stmt 1 view .LVU1392
+2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4135              		.loc 1 2030 13 is_stmt 0 view .LVU1393
+ 4136 0088 A36B     		ldr	r3, [r4, #56]
+2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4137              		.loc 1 2030 41 view .LVU1394
+ 4138 008a 374A     		ldr	r2, .L292+12
+ 4139 008c DA64     		str	r2, [r3, #76]
+2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 4140              		.loc 1 2033 9 is_stmt 1 view .LVU1395
+2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 4141              		.loc 1 2033 13 is_stmt 0 view .LVU1396
+ 4142 008e A26B     		ldr	r2, [r4, #56]
+2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 4143              		.loc 1 2033 44 view .LVU1397
+ARM GAS  /tmp/ccVyGVF6.s 			page 228
+
+
+ 4144 0090 0023     		movs	r3, #0
+ 4145 0092 1364     		str	r3, [r2, #64]
+2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4146              		.loc 1 2034 9 is_stmt 1 view .LVU1398
+2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4147              		.loc 1 2034 13 is_stmt 0 view .LVU1399
+ 4148 0094 A26B     		ldr	r2, [r4, #56]
+2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4149              		.loc 1 2034 41 view .LVU1400
+ 4150 0096 1365     		str	r3, [r2, #80]
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ 4151              		.loc 1 2037 9 is_stmt 1 view .LVU1401
+2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4152              		.loc 1 2038 57 is_stmt 0 view .LVU1402
+ 4153 0098 2268     		ldr	r2, [r4]
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ 4154              		.loc 1 2037 25 view .LVU1403
+ 4155 009a 238D     		ldrh	r3, [r4, #40]
+ 4156 009c 2832     		adds	r2, r2, #40
+ 4157 009e 616A     		ldr	r1, [r4, #36]
+ 4158              	.LVL279:
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ 4159              		.loc 1 2037 25 view .LVU1404
+ 4160 00a0 A06B     		ldr	r0, [r4, #56]
+ 4161 00a2 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 4162              	.LVL280:
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4163              		.loc 1 2055 7 is_stmt 1 view .LVU1405
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4164              		.loc 1 2055 10 is_stmt 0 view .LVU1406
+ 4165 00a6 00B3     		cbz	r0, .L291
+2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4166              		.loc 1 2080 9 is_stmt 1 view .LVU1407
+2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4167              		.loc 1 2080 25 is_stmt 0 view .LVU1408
+ 4168 00a8 2023     		movs	r3, #32
+ 4169 00aa 84F84130 		strb	r3, [r4, #65]
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4170              		.loc 1 2081 9 is_stmt 1 view .LVU1409
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4171              		.loc 1 2081 25 is_stmt 0 view .LVU1410
+ 4172 00ae 0022     		movs	r2, #0
+ 4173 00b0 84F84220 		strb	r2, [r4, #66]
+2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4174              		.loc 1 2084 9 is_stmt 1 view .LVU1411
+2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4175              		.loc 1 2084 25 is_stmt 0 view .LVU1412
+ 4176 00b4 636C     		ldr	r3, [r4, #68]
+ 4177 00b6 43F01003 		orr	r3, r3, #16
+ 4178 00ba 6364     		str	r3, [r4, #68]
+2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4179              		.loc 1 2087 9 is_stmt 1 view .LVU1413
+2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4180              		.loc 1 2087 9 view .LVU1414
+ 4181 00bc 84F84020 		strb	r2, [r4, #64]
+2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4182              		.loc 1 2087 9 view .LVU1415
+ARM GAS  /tmp/ccVyGVF6.s 			page 229
+
+
+2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4183              		.loc 1 2089 9 view .LVU1416
+2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4184              		.loc 1 2089 16 is_stmt 0 view .LVU1417
+ 4185 00c0 0120     		movs	r0, #1
+ 4186              	.LVL281:
+2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4187              		.loc 1 2089 16 view .LVU1418
+ 4188 00c2 44E0     		b	.L277
+ 4189              	.LVL282:
+ 4190              	.L278:
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 4191              		.loc 1 2004 7 is_stmt 1 view .LVU1419
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 4192              		.loc 1 2004 28 is_stmt 0 view .LVU1420
+ 4193 00c4 638D     		ldrh	r3, [r4, #42]
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 4194              		.loc 1 2004 22 view .LVU1421
+ 4195 00c6 2385     		strh	r3, [r4, #40]	@ movhi
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4196              		.loc 1 2005 7 is_stmt 1 view .LVU1422
+ 4197              	.LVL283:
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4198              		.loc 1 2005 16 is_stmt 0 view .LVU1423
+ 4199 00c8 4FF00076 		mov	r6, #33554432
+ 4200 00cc C6E7     		b	.L279
+ 4201              	.LVL284:
+ 4202              	.L282:
+2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4203              		.loc 1 2043 9 is_stmt 1 view .LVU1424
+2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4204              		.loc 1 2043 25 is_stmt 0 view .LVU1425
+ 4205 00ce 2023     		movs	r3, #32
+ 4206 00d0 84F84130 		strb	r3, [r4, #65]
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4207              		.loc 1 2044 9 is_stmt 1 view .LVU1426
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4208              		.loc 1 2044 25 is_stmt 0 view .LVU1427
+ 4209 00d4 0022     		movs	r2, #0
+ 4210              	.LVL285:
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4211              		.loc 1 2044 25 view .LVU1428
+ 4212 00d6 84F84220 		strb	r2, [r4, #66]
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4213              		.loc 1 2047 9 is_stmt 1 view .LVU1429
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4214              		.loc 1 2047 25 is_stmt 0 view .LVU1430
+ 4215 00da 636C     		ldr	r3, [r4, #68]
+ 4216 00dc 43F08003 		orr	r3, r3, #128
+ 4217 00e0 6364     		str	r3, [r4, #68]
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4218              		.loc 1 2050 9 is_stmt 1 view .LVU1431
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4219              		.loc 1 2050 9 view .LVU1432
+ 4220 00e2 84F84020 		strb	r2, [r4, #64]
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4221              		.loc 1 2050 9 view .LVU1433
+ARM GAS  /tmp/ccVyGVF6.s 			page 230
+
+
+2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4222              		.loc 1 2052 9 view .LVU1434
+2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4223              		.loc 1 2052 16 is_stmt 0 view .LVU1435
+ 4224 00e6 0120     		movs	r0, #1
+ 4225 00e8 31E0     		b	.L277
+ 4226              	.LVL286:
+ 4227              	.L291:
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            xfermode, I2C_GENERATE_START_WRITE);
+ 4228              		.loc 1 2059 9 is_stmt 1 view .LVU1436
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            xfermode, I2C_GENERATE_START_WRITE);
+ 4229              		.loc 1 2059 60 is_stmt 0 view .LVU1437
+ 4230 00ea 228D     		ldrh	r2, [r4, #40]
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            xfermode, I2C_GENERATE_START_WRITE);
+ 4231              		.loc 1 2059 9 view .LVU1438
+ 4232 00ec 0132     		adds	r2, r2, #1
+ 4233 00ee 1F4B     		ldr	r3, .L292+16
+ 4234 00f0 0093     		str	r3, [sp]
+ 4235 00f2 3346     		mov	r3, r6
+ 4236 00f4 D2B2     		uxtb	r2, r2
+ 4237 00f6 2946     		mov	r1, r5
+ 4238 00f8 2046     		mov	r0, r4
+ 4239              	.LVL287:
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            xfermode, I2C_GENERATE_START_WRITE);
+ 4240              		.loc 1 2059 9 view .LVU1439
+ 4241 00fa FFF7FEFF 		bl	I2C_TransferConfig
+ 4242              	.LVL288:
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4243              		.loc 1 2063 9 is_stmt 1 view .LVU1440
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4244              		.loc 1 2063 25 is_stmt 0 view .LVU1441
+ 4245 00fe 638D     		ldrh	r3, [r4, #42]
+ 4246 0100 9BB2     		uxth	r3, r3
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4247              		.loc 1 2063 32 view .LVU1442
+ 4248 0102 228D     		ldrh	r2, [r4, #40]
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4249              		.loc 1 2063 25 view .LVU1443
+ 4250 0104 9B1A     		subs	r3, r3, r2
+ 4251 0106 9BB2     		uxth	r3, r3
+ 4252 0108 6385     		strh	r3, [r4, #42]	@ movhi
+2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4253              		.loc 1 2066 9 is_stmt 1 view .LVU1444
+2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4254              		.loc 1 2066 9 view .LVU1445
+ 4255 010a 0023     		movs	r3, #0
+ 4256 010c 84F84030 		strb	r3, [r4, #64]
+2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4257              		.loc 1 2066 9 view .LVU1446
+2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4258              		.loc 1 2072 9 view .LVU1447
+ 4259 0110 1021     		movs	r1, #16
+ 4260 0112 2046     		mov	r0, r4
+ 4261 0114 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 4262              	.LVL289:
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4263              		.loc 1 2075 9 view .LVU1448
+ARM GAS  /tmp/ccVyGVF6.s 			page 231
+
+
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4264              		.loc 1 2075 13 is_stmt 0 view .LVU1449
+ 4265 0118 2268     		ldr	r2, [r4]
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4266              		.loc 1 2075 29 view .LVU1450
+ 4267 011a 1368     		ldr	r3, [r2]
+ 4268 011c 43F48043 		orr	r3, r3, #16384
+ 4269 0120 1360     		str	r3, [r2]
+ 4270 0122 11E0     		b	.L285
+ 4271              	.LVL290:
+ 4272              	.L281:
+2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4273              		.loc 1 2095 7 is_stmt 1 view .LVU1451
+2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4274              		.loc 1 2095 21 is_stmt 0 view .LVU1452
+ 4275 0124 124B     		ldr	r3, .L292+20
+ 4276 0126 6363     		str	r3, [r4, #52]
+2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 4277              		.loc 1 2099 7 is_stmt 1 view .LVU1453
+ 4278 0128 104B     		ldr	r3, .L292+16
+ 4279 012a 0093     		str	r3, [sp]
+ 4280 012c 4FF00073 		mov	r3, #33554432
+ 4281 0130 CAB2     		uxtb	r2, r1
+ 4282              	.LVL291:
+2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 4283              		.loc 1 2099 7 is_stmt 0 view .LVU1454
+ 4284 0132 2946     		mov	r1, r5
+ 4285              	.LVL292:
+2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_WRITE);
+ 4286              		.loc 1 2099 7 view .LVU1455
+ 4287 0134 2046     		mov	r0, r4
+ 4288 0136 FFF7FEFF 		bl	I2C_TransferConfig
+ 4289              	.LVL293:
+2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4290              		.loc 1 2103 7 is_stmt 1 view .LVU1456
+2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4291              		.loc 1 2103 7 view .LVU1457
+ 4292 013a 0023     		movs	r3, #0
+ 4293 013c 84F84030 		strb	r3, [r4, #64]
+2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4294              		.loc 1 2103 7 view .LVU1458
+2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4295              		.loc 1 2112 7 view .LVU1459
+ 4296 0140 0121     		movs	r1, #1
+ 4297 0142 2046     		mov	r0, r4
+ 4298 0144 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 4299              	.LVL294:
+ 4300              	.L285:
+2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 4301              		.loc 1 2115 5 view .LVU1460
+2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 4302              		.loc 1 2115 12 is_stmt 0 view .LVU1461
+ 4303 0148 0020     		movs	r0, #0
+ 4304 014a 00E0     		b	.L277
+ 4305              	.LVL295:
+ 4306              	.L286:
+2119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccVyGVF6.s 			page 232
+
+
+ 4307              		.loc 1 2119 12 view .LVU1462
+ 4308 014c 0220     		movs	r0, #2
+ 4309              	.LVL296:
+ 4310              	.L277:
+2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4311              		.loc 1 2121 1 view .LVU1463
+ 4312 014e 02B0     		add	sp, sp, #8
+ 4313              	.LCFI48:
+ 4314              		.cfi_remember_state
+ 4315              		.cfi_def_cfa_offset 16
+ 4316              		@ sp needed
+ 4317 0150 70BD     		pop	{r4, r5, r6, pc}
+ 4318              	.LVL297:
+ 4319              	.L287:
+ 4320              	.LCFI49:
+ 4321              		.cfi_restore_state
+1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4322              		.loc 1 1981 14 view .LVU1464
+ 4323 0152 0220     		movs	r0, #2
+ 4324 0154 FBE7     		b	.L277
+ 4325              	.L288:
+1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4326              		.loc 1 1985 5 view .LVU1465
+ 4327 0156 0220     		movs	r0, #2
+ 4328 0158 F9E7     		b	.L277
+ 4329              	.L293:
+ 4330 015a 00BF     		.align	2
+ 4331              	.L292:
+ 4332 015c 0000FFFF 		.word	-65536
+ 4333 0160 00000000 		.word	I2C_Master_ISR_DMA
+ 4334 0164 00000000 		.word	I2C_DMAMasterTransmitCplt
+ 4335 0168 00000000 		.word	I2C_DMAError
+ 4336 016c 00200080 		.word	-2147475456
+ 4337 0170 00000000 		.word	I2C_Master_ISR_IT
+ 4338              		.cfi_endproc
+ 4339              	.LFE153:
+ 4341              		.section	.text.HAL_I2C_Master_Receive_DMA,"ax",%progbits
+ 4342              		.align	1
+ 4343              		.global	HAL_I2C_Master_Receive_DMA
+ 4344              		.syntax unified
+ 4345              		.thumb
+ 4346              		.thumb_func
+ 4347              		.fpu fpv5-d16
+ 4349              	HAL_I2C_Master_Receive_DMA:
+ 4350              	.LVL298:
+ 4351              	.LFB154:
+2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 4352              		.loc 1 2135 1 is_stmt 1 view -0
+ 4353              		.cfi_startproc
+ 4354              		@ args = 0, pretend = 0, frame = 0
+ 4355              		@ frame_needed = 0, uses_anonymous_args = 0
+2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 4356              		.loc 1 2135 1 is_stmt 0 view .LVU1467
+ 4357 0000 70B5     		push	{r4, r5, r6, lr}
+ 4358              	.LCFI50:
+ 4359              		.cfi_def_cfa_offset 16
+ 4360              		.cfi_offset 4, -16
+ARM GAS  /tmp/ccVyGVF6.s 			page 233
+
+
+ 4361              		.cfi_offset 5, -12
+ 4362              		.cfi_offset 6, -8
+ 4363              		.cfi_offset 14, -4
+ 4364 0002 82B0     		sub	sp, sp, #8
+ 4365              	.LCFI51:
+ 4366              		.cfi_def_cfa_offset 24
+ 4367 0004 0446     		mov	r4, r0
+2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 4368              		.loc 1 2136 3 is_stmt 1 view .LVU1468
+2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4369              		.loc 1 2137 3 view .LVU1469
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4370              		.loc 1 2139 3 view .LVU1470
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4371              		.loc 1 2139 11 is_stmt 0 view .LVU1471
+ 4372 0006 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 4373              	.LVL299:
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4374              		.loc 1 2139 11 view .LVU1472
+ 4375 000a C0B2     		uxtb	r0, r0
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4376              		.loc 1 2139 6 view .LVU1473
+ 4377 000c 2028     		cmp	r0, #32
+ 4378 000e 40F08C80 		bne	.L303
+ 4379 0012 0D46     		mov	r5, r1
+2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4380              		.loc 1 2141 5 is_stmt 1 view .LVU1474
+2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4381              		.loc 1 2141 9 is_stmt 0 view .LVU1475
+ 4382 0014 2168     		ldr	r1, [r4]
+ 4383              	.LVL300:
+2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4384              		.loc 1 2141 9 view .LVU1476
+ 4385 0016 8969     		ldr	r1, [r1, #24]
+2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4386              		.loc 1 2141 8 view .LVU1477
+ 4387 0018 11F4004F 		tst	r1, #32768
+ 4388 001c 40F08880 		bne	.L304
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4389              		.loc 1 2147 5 is_stmt 1 view .LVU1478
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4390              		.loc 1 2147 5 view .LVU1479
+ 4391 0020 94F84010 		ldrb	r1, [r4, #64]	@ zero_extendqisi2
+ 4392 0024 0129     		cmp	r1, #1
+ 4393 0026 00F08580 		beq	.L305
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4394              		.loc 1 2147 5 discriminator 2 view .LVU1480
+ 4395 002a 0121     		movs	r1, #1
+ 4396 002c 84F84010 		strb	r1, [r4, #64]
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4397              		.loc 1 2147 5 discriminator 2 view .LVU1481
+2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 4398              		.loc 1 2149 5 discriminator 2 view .LVU1482
+2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MASTER;
+ 4399              		.loc 1 2149 23 is_stmt 0 discriminator 2 view .LVU1483
+ 4400 0030 2221     		movs	r1, #34
+ 4401 0032 84F84110 		strb	r1, [r4, #65]
+ARM GAS  /tmp/ccVyGVF6.s 			page 234
+
+
+2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4402              		.loc 1 2150 5 is_stmt 1 discriminator 2 view .LVU1484
+2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4403              		.loc 1 2150 23 is_stmt 0 discriminator 2 view .LVU1485
+ 4404 0036 1021     		movs	r1, #16
+ 4405 0038 84F84210 		strb	r1, [r4, #66]
+2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4406              		.loc 1 2151 5 is_stmt 1 discriminator 2 view .LVU1486
+2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4407              		.loc 1 2151 23 is_stmt 0 discriminator 2 view .LVU1487
+ 4408 003c 0021     		movs	r1, #0
+ 4409 003e 6164     		str	r1, [r4, #68]
+2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4410              		.loc 1 2154 5 is_stmt 1 discriminator 2 view .LVU1488
+2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4411              		.loc 1 2154 23 is_stmt 0 discriminator 2 view .LVU1489
+ 4412 0040 6262     		str	r2, [r4, #36]
+2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4413              		.loc 1 2155 5 is_stmt 1 discriminator 2 view .LVU1490
+2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4414              		.loc 1 2155 23 is_stmt 0 discriminator 2 view .LVU1491
+ 4415 0042 6385     		strh	r3, [r4, #42]	@ movhi
+2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 4416              		.loc 1 2156 5 is_stmt 1 discriminator 2 view .LVU1492
+2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 4417              		.loc 1 2156 23 is_stmt 0 discriminator 2 view .LVU1493
+ 4418 0044 3C4B     		ldr	r3, .L309
+ 4419              	.LVL301:
+2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 4420              		.loc 1 2156 23 discriminator 2 view .LVU1494
+ 4421 0046 E362     		str	r3, [r4, #44]
+ 4422              	.LVL302:
+2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4423              		.loc 1 2157 5 is_stmt 1 discriminator 2 view .LVU1495
+2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4424              		.loc 1 2157 23 is_stmt 0 discriminator 2 view .LVU1496
+ 4425 0048 3C4B     		ldr	r3, .L309+4
+ 4426 004a 6363     		str	r3, [r4, #52]
+2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4427              		.loc 1 2159 5 is_stmt 1 discriminator 2 view .LVU1497
+2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4428              		.loc 1 2159 13 is_stmt 0 discriminator 2 view .LVU1498
+ 4429 004c 638D     		ldrh	r3, [r4, #42]
+ 4430 004e 9BB2     		uxth	r3, r3
+2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4431              		.loc 1 2159 8 discriminator 2 view .LVU1499
+ 4432 0050 FF2B     		cmp	r3, #255
+ 4433 0052 27D9     		bls	.L296
+2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 4434              		.loc 1 2161 7 is_stmt 1 view .LVU1500
+2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 4435              		.loc 1 2161 22 is_stmt 0 view .LVU1501
+ 4436 0054 0123     		movs	r3, #1
+ 4437 0056 2385     		strh	r3, [r4, #40]	@ movhi
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4438              		.loc 1 2162 7 is_stmt 1 view .LVU1502
+ 4439              	.LVL303:
+ARM GAS  /tmp/ccVyGVF6.s 			page 235
+
+
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4440              		.loc 1 2162 16 is_stmt 0 view .LVU1503
+ 4441 0058 4FF08076 		mov	r6, #16777216
+ 4442              	.LVL304:
+ 4443              	.L297:
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4444              		.loc 1 2170 5 is_stmt 1 view .LVU1504
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4445              		.loc 1 2170 13 is_stmt 0 view .LVU1505
+ 4446 005c 218D     		ldrh	r1, [r4, #40]
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4447              		.loc 1 2170 8 view .LVU1506
+ 4448 005e 0029     		cmp	r1, #0
+ 4449 0060 4FD0     		beq	.L298
+2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4450              		.loc 1 2172 7 is_stmt 1 view .LVU1507
+2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4451              		.loc 1 2172 15 is_stmt 0 view .LVU1508
+ 4452 0062 E36B     		ldr	r3, [r4, #60]
+2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4453              		.loc 1 2172 10 view .LVU1509
+ 4454 0064 1BB3     		cbz	r3, .L299
+2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4455              		.loc 1 2175 9 is_stmt 1 view .LVU1510
+2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4456              		.loc 1 2175 40 is_stmt 0 view .LVU1511
+ 4457 0066 3649     		ldr	r1, .L309+8
+ 4458 0068 D963     		str	r1, [r3, #60]
+2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4459              		.loc 1 2178 9 is_stmt 1 view .LVU1512
+2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4460              		.loc 1 2178 13 is_stmt 0 view .LVU1513
+ 4461 006a E36B     		ldr	r3, [r4, #60]
+2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4462              		.loc 1 2178 41 view .LVU1514
+ 4463 006c 3549     		ldr	r1, .L309+12
+ 4464 006e D964     		str	r1, [r3, #76]
+2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 4465              		.loc 1 2181 9 is_stmt 1 view .LVU1515
+2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 4466              		.loc 1 2181 13 is_stmt 0 view .LVU1516
+ 4467 0070 E16B     		ldr	r1, [r4, #60]
+2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 4468              		.loc 1 2181 44 view .LVU1517
+ 4469 0072 0023     		movs	r3, #0
+ 4470 0074 0B64     		str	r3, [r1, #64]
+2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4471              		.loc 1 2182 9 is_stmt 1 view .LVU1518
+2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4472              		.loc 1 2182 13 is_stmt 0 view .LVU1519
+ 4473 0076 E16B     		ldr	r1, [r4, #60]
+2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4474              		.loc 1 2182 41 view .LVU1520
+ 4475 0078 0B65     		str	r3, [r1, #80]
+2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 4476              		.loc 1 2185 9 is_stmt 1 view .LVU1521
+2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          hi2c->XferSize);
+ARM GAS  /tmp/ccVyGVF6.s 			page 236
+
+
+ 4477              		.loc 1 2185 71 is_stmt 0 view .LVU1522
+ 4478 007a 2168     		ldr	r1, [r4]
+2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 4479              		.loc 1 2185 25 view .LVU1523
+ 4480 007c 238D     		ldrh	r3, [r4, #40]
+ 4481 007e 2431     		adds	r1, r1, #36
+ 4482 0080 E06B     		ldr	r0, [r4, #60]
+ 4483 0082 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 4484              	.LVL305:
+2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4485              		.loc 1 2203 7 is_stmt 1 view .LVU1524
+2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4486              		.loc 1 2203 10 is_stmt 0 view .LVU1525
+ 4487 0086 00B3     		cbz	r0, .L308
+2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4488              		.loc 1 2227 9 is_stmt 1 view .LVU1526
+2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4489              		.loc 1 2227 25 is_stmt 0 view .LVU1527
+ 4490 0088 2023     		movs	r3, #32
+ 4491 008a 84F84130 		strb	r3, [r4, #65]
+2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4492              		.loc 1 2228 9 is_stmt 1 view .LVU1528
+2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4493              		.loc 1 2228 25 is_stmt 0 view .LVU1529
+ 4494 008e 0022     		movs	r2, #0
+ 4495 0090 84F84220 		strb	r2, [r4, #66]
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4496              		.loc 1 2231 9 is_stmt 1 view .LVU1530
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4497              		.loc 1 2231 25 is_stmt 0 view .LVU1531
+ 4498 0094 636C     		ldr	r3, [r4, #68]
+ 4499 0096 43F01003 		orr	r3, r3, #16
+ 4500 009a 6364     		str	r3, [r4, #68]
+2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4501              		.loc 1 2234 9 is_stmt 1 view .LVU1532
+2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4502              		.loc 1 2234 9 view .LVU1533
+ 4503 009c 84F84020 		strb	r2, [r4, #64]
+2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4504              		.loc 1 2234 9 view .LVU1534
+2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4505              		.loc 1 2236 9 view .LVU1535
+2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4506              		.loc 1 2236 16 is_stmt 0 view .LVU1536
+ 4507 00a0 0120     		movs	r0, #1
+ 4508              	.LVL306:
+2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4509              		.loc 1 2236 16 view .LVU1537
+ 4510 00a2 43E0     		b	.L295
+ 4511              	.LVL307:
+ 4512              	.L296:
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 4513              		.loc 1 2166 7 is_stmt 1 view .LVU1538
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ 4514              		.loc 1 2166 28 is_stmt 0 view .LVU1539
+ 4515 00a4 638D     		ldrh	r3, [r4, #42]
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_AUTOEND_MODE;
+ARM GAS  /tmp/ccVyGVF6.s 			page 237
+
+
+ 4516              		.loc 1 2166 22 view .LVU1540
+ 4517 00a6 2385     		strh	r3, [r4, #40]	@ movhi
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4518              		.loc 1 2167 7 is_stmt 1 view .LVU1541
+ 4519              	.LVL308:
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4520              		.loc 1 2167 16 is_stmt 0 view .LVU1542
+ 4521 00a8 4FF00076 		mov	r6, #33554432
+ 4522 00ac D6E7     		b	.L297
+ 4523              	.LVL309:
+ 4524              	.L299:
+2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4525              		.loc 1 2191 9 is_stmt 1 view .LVU1543
+2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4526              		.loc 1 2191 25 is_stmt 0 view .LVU1544
+ 4527 00ae 2023     		movs	r3, #32
+ 4528 00b0 84F84130 		strb	r3, [r4, #65]
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4529              		.loc 1 2192 9 is_stmt 1 view .LVU1545
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4530              		.loc 1 2192 25 is_stmt 0 view .LVU1546
+ 4531 00b4 0022     		movs	r2, #0
+ 4532              	.LVL310:
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4533              		.loc 1 2192 25 view .LVU1547
+ 4534 00b6 84F84220 		strb	r2, [r4, #66]
+2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4535              		.loc 1 2195 9 is_stmt 1 view .LVU1548
+2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4536              		.loc 1 2195 25 is_stmt 0 view .LVU1549
+ 4537 00ba 636C     		ldr	r3, [r4, #68]
+ 4538 00bc 43F08003 		orr	r3, r3, #128
+ 4539 00c0 6364     		str	r3, [r4, #68]
+2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4540              		.loc 1 2198 9 is_stmt 1 view .LVU1550
+2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4541              		.loc 1 2198 9 view .LVU1551
+ 4542 00c2 84F84020 		strb	r2, [r4, #64]
+2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4543              		.loc 1 2198 9 view .LVU1552
+2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4544              		.loc 1 2200 9 view .LVU1553
+2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4545              		.loc 1 2200 16 is_stmt 0 view .LVU1554
+ 4546 00c6 0120     		movs	r0, #1
+ 4547 00c8 30E0     		b	.L295
+ 4548              	.LVL311:
+ 4549              	.L308:
+2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4550              		.loc 1 2207 9 is_stmt 1 view .LVU1555
+ 4551 00ca 1F4B     		ldr	r3, .L309+16
+ 4552 00cc 0093     		str	r3, [sp]
+ 4553 00ce 3346     		mov	r3, r6
+ 4554 00d0 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 4555 00d4 2946     		mov	r1, r5
+ 4556 00d6 2046     		mov	r0, r4
+ 4557              	.LVL312:
+ARM GAS  /tmp/ccVyGVF6.s 			page 238
+
+
+2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4558              		.loc 1 2207 9 is_stmt 0 view .LVU1556
+ 4559 00d8 FFF7FEFF 		bl	I2C_TransferConfig
+ 4560              	.LVL313:
+2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4561              		.loc 1 2210 9 is_stmt 1 view .LVU1557
+2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4562              		.loc 1 2210 25 is_stmt 0 view .LVU1558
+ 4563 00dc 638D     		ldrh	r3, [r4, #42]
+ 4564 00de 9BB2     		uxth	r3, r3
+2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4565              		.loc 1 2210 32 view .LVU1559
+ 4566 00e0 228D     		ldrh	r2, [r4, #40]
+2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4567              		.loc 1 2210 25 view .LVU1560
+ 4568 00e2 9B1A     		subs	r3, r3, r2
+ 4569 00e4 9BB2     		uxth	r3, r3
+ 4570 00e6 6385     		strh	r3, [r4, #42]	@ movhi
+2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4571              		.loc 1 2213 9 is_stmt 1 view .LVU1561
+2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4572              		.loc 1 2213 9 view .LVU1562
+ 4573 00e8 0023     		movs	r3, #0
+ 4574 00ea 84F84030 		strb	r3, [r4, #64]
+2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4575              		.loc 1 2213 9 view .LVU1563
+2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4576              		.loc 1 2219 9 view .LVU1564
+ 4577 00ee 1021     		movs	r1, #16
+ 4578 00f0 2046     		mov	r0, r4
+ 4579 00f2 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 4580              	.LVL314:
+2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4581              		.loc 1 2222 9 view .LVU1565
+2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4582              		.loc 1 2222 13 is_stmt 0 view .LVU1566
+ 4583 00f6 2268     		ldr	r2, [r4]
+2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4584              		.loc 1 2222 29 view .LVU1567
+ 4585 00f8 1368     		ldr	r3, [r2]
+ 4586 00fa 43F40043 		orr	r3, r3, #32768
+ 4587 00fe 1360     		str	r3, [r2]
+ 4588 0100 11E0     		b	.L302
+ 4589              	.LVL315:
+ 4590              	.L298:
+2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4591              		.loc 1 2242 7 is_stmt 1 view .LVU1568
+2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4592              		.loc 1 2242 21 is_stmt 0 view .LVU1569
+ 4593 0102 124B     		ldr	r3, .L309+20
+ 4594 0104 6363     		str	r3, [r4, #52]
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 4595              		.loc 1 2246 7 is_stmt 1 view .LVU1570
+ 4596 0106 104B     		ldr	r3, .L309+16
+ 4597 0108 0093     		str	r3, [sp]
+ 4598 010a 4FF00073 		mov	r3, #33554432
+ 4599 010e CAB2     		uxtb	r2, r1
+ARM GAS  /tmp/ccVyGVF6.s 			page 239
+
+
+ 4600              	.LVL316:
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 4601              		.loc 1 2246 7 is_stmt 0 view .LVU1571
+ 4602 0110 2946     		mov	r1, r5
+ 4603 0112 2046     		mov	r0, r4
+ 4604 0114 FFF7FEFF 		bl	I2C_TransferConfig
+ 4605              	.LVL317:
+2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4606              		.loc 1 2250 7 is_stmt 1 view .LVU1572
+2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4607              		.loc 1 2250 7 view .LVU1573
+ 4608 0118 0023     		movs	r3, #0
+ 4609 011a 84F84030 		strb	r3, [r4, #64]
+2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4610              		.loc 1 2250 7 view .LVU1574
+2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4611              		.loc 1 2259 7 view .LVU1575
+ 4612 011e 0221     		movs	r1, #2
+ 4613 0120 2046     		mov	r0, r4
+ 4614 0122 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 4615              	.LVL318:
+ 4616              	.L302:
+2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 4617              		.loc 1 2262 5 view .LVU1576
+2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 4618              		.loc 1 2262 12 is_stmt 0 view .LVU1577
+ 4619 0126 0020     		movs	r0, #0
+ 4620 0128 00E0     		b	.L295
+ 4621              	.LVL319:
+ 4622              	.L303:
+2266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 4623              		.loc 1 2266 12 view .LVU1578
+ 4624 012a 0220     		movs	r0, #2
+ 4625              	.LVL320:
+ 4626              	.L295:
+2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4627              		.loc 1 2268 1 view .LVU1579
+ 4628 012c 02B0     		add	sp, sp, #8
+ 4629              	.LCFI52:
+ 4630              		.cfi_remember_state
+ 4631              		.cfi_def_cfa_offset 16
+ 4632              		@ sp needed
+ 4633 012e 70BD     		pop	{r4, r5, r6, pc}
+ 4634              	.LVL321:
+ 4635              	.L304:
+ 4636              	.LCFI53:
+ 4637              		.cfi_restore_state
+2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4638              		.loc 1 2143 14 view .LVU1580
+ 4639 0130 0220     		movs	r0, #2
+ 4640 0132 FBE7     		b	.L295
+ 4641              	.L305:
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4642              		.loc 1 2147 5 view .LVU1581
+ 4643 0134 0220     		movs	r0, #2
+ 4644 0136 F9E7     		b	.L295
+ 4645              	.L310:
+ARM GAS  /tmp/ccVyGVF6.s 			page 240
+
+
+ 4646              		.align	2
+ 4647              	.L309:
+ 4648 0138 0000FFFF 		.word	-65536
+ 4649 013c 00000000 		.word	I2C_Master_ISR_DMA
+ 4650 0140 00000000 		.word	I2C_DMAMasterReceiveCplt
+ 4651 0144 00000000 		.word	I2C_DMAError
+ 4652 0148 00240080 		.word	-2147474432
+ 4653 014c 00000000 		.word	I2C_Master_ISR_IT
+ 4654              		.cfi_endproc
+ 4655              	.LFE154:
+ 4657              		.section	.text.HAL_I2C_Slave_Transmit_DMA,"ax",%progbits
+ 4658              		.align	1
+ 4659              		.global	HAL_I2C_Slave_Transmit_DMA
+ 4660              		.syntax unified
+ 4661              		.thumb
+ 4662              		.thumb_func
+ 4663              		.fpu fpv5-d16
+ 4665              	HAL_I2C_Slave_Transmit_DMA:
+ 4666              	.LVL322:
+ 4667              	.LFB155:
+2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 4668              		.loc 1 2279 1 is_stmt 1 view -0
+ 4669              		.cfi_startproc
+ 4670              		@ args = 0, pretend = 0, frame = 0
+ 4671              		@ frame_needed = 0, uses_anonymous_args = 0
+2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4672              		.loc 1 2280 3 view .LVU1583
+2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4673              		.loc 1 2282 3 view .LVU1584
+2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4674              		.loc 1 2282 11 is_stmt 0 view .LVU1585
+ 4675 0000 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 4676 0004 DBB2     		uxtb	r3, r3
+2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4677              		.loc 1 2282 6 view .LVU1586
+ 4678 0006 202B     		cmp	r3, #32
+ 4679 0008 40F08D80 		bne	.L320
+2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 4680              		.loc 1 2279 1 view .LVU1587
+ 4681 000c 10B5     		push	{r4, lr}
+ 4682              	.LCFI54:
+ 4683              		.cfi_def_cfa_offset 8
+ 4684              		.cfi_offset 4, -8
+ 4685              		.cfi_offset 14, -4
+ 4686 000e 0446     		mov	r4, r0
+2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4687              		.loc 1 2284 5 is_stmt 1 view .LVU1588
+2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4688              		.loc 1 2284 8 is_stmt 0 view .LVU1589
+ 4689 0010 002A     		cmp	r2, #0
+ 4690 0012 18BF     		it	ne
+ 4691 0014 0029     		cmpne	r1, #0
+ 4692 0016 42D0     		beq	.L327
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4693              		.loc 1 2290 5 is_stmt 1 view .LVU1590
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4694              		.loc 1 2290 5 view .LVU1591
+ARM GAS  /tmp/ccVyGVF6.s 			page 241
+
+
+ 4695 0018 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 4696 001c 012B     		cmp	r3, #1
+ 4697 001e 00F08480 		beq	.L321
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4698              		.loc 1 2290 5 discriminator 2 view .LVU1592
+ 4699 0022 0123     		movs	r3, #1
+ 4700 0024 80F84030 		strb	r3, [r0, #64]
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4701              		.loc 1 2290 5 discriminator 2 view .LVU1593
+2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 4702              		.loc 1 2292 5 discriminator 2 view .LVU1594
+2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 4703              		.loc 1 2292 23 is_stmt 0 discriminator 2 view .LVU1595
+ 4704 0028 2123     		movs	r3, #33
+ 4705 002a 80F84130 		strb	r3, [r0, #65]
+2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4706              		.loc 1 2293 5 is_stmt 1 discriminator 2 view .LVU1596
+2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 4707              		.loc 1 2293 23 is_stmt 0 discriminator 2 view .LVU1597
+ 4708 002e 2023     		movs	r3, #32
+ 4709 0030 80F84230 		strb	r3, [r0, #66]
+2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4710              		.loc 1 2294 5 is_stmt 1 discriminator 2 view .LVU1598
+2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4711              		.loc 1 2294 23 is_stmt 0 discriminator 2 view .LVU1599
+ 4712 0034 0023     		movs	r3, #0
+ 4713 0036 4364     		str	r3, [r0, #68]
+2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4714              		.loc 1 2297 5 is_stmt 1 discriminator 2 view .LVU1600
+2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 4715              		.loc 1 2297 23 is_stmt 0 discriminator 2 view .LVU1601
+ 4716 0038 4162     		str	r1, [r0, #36]
+2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 4717              		.loc 1 2298 5 is_stmt 1 discriminator 2 view .LVU1602
+2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 4718              		.loc 1 2298 23 is_stmt 0 discriminator 2 view .LVU1603
+ 4719 003a 4285     		strh	r2, [r0, #42]	@ movhi
+2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4720              		.loc 1 2299 5 is_stmt 1 discriminator 2 view .LVU1604
+2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4721              		.loc 1 2299 29 is_stmt 0 discriminator 2 view .LVU1605
+ 4722 003c 438D     		ldrh	r3, [r0, #42]
+2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 4723              		.loc 1 2299 23 discriminator 2 view .LVU1606
+ 4724 003e 0385     		strh	r3, [r0, #40]	@ movhi
+2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 4725              		.loc 1 2300 5 is_stmt 1 discriminator 2 view .LVU1607
+2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 4726              		.loc 1 2300 23 is_stmt 0 discriminator 2 view .LVU1608
+ 4727 0040 3B4B     		ldr	r3, .L330
+ 4728 0042 C362     		str	r3, [r0, #44]
+2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4729              		.loc 1 2301 5 is_stmt 1 discriminator 2 view .LVU1609
+2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4730              		.loc 1 2301 23 is_stmt 0 discriminator 2 view .LVU1610
+ 4731 0044 3B4B     		ldr	r3, .L330+4
+ 4732 0046 4363     		str	r3, [r0, #52]
+ARM GAS  /tmp/ccVyGVF6.s 			page 242
+
+
+2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4733              		.loc 1 2304 5 is_stmt 1 discriminator 2 view .LVU1611
+2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4734              		.loc 1 2304 19 is_stmt 0 discriminator 2 view .LVU1612
+ 4735 0048 036A     		ldr	r3, [r0, #32]
+2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4736              		.loc 1 2304 8 discriminator 2 view .LVU1613
+ 4737 004a B3F5003F 		cmp	r3, #131072
+ 4738 004e 2BD0     		beq	.L328
+ 4739              	.LVL323:
+ 4740              	.L314:
+2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4741              		.loc 1 2317 5 is_stmt 1 view .LVU1614
+2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4742              		.loc 1 2317 13 is_stmt 0 view .LVU1615
+ 4743 0050 638D     		ldrh	r3, [r4, #42]
+ 4744 0052 9BB2     		uxth	r3, r3
+2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 4745              		.loc 1 2317 8 view .LVU1616
+ 4746 0054 002B     		cmp	r3, #0
+ 4747 0056 57D0     		beq	.L315
+2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4748              		.loc 1 2319 7 is_stmt 1 view .LVU1617
+2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4749              		.loc 1 2319 15 is_stmt 0 view .LVU1618
+ 4750 0058 A36B     		ldr	r3, [r4, #56]
+2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4751              		.loc 1 2319 10 view .LVU1619
+ 4752 005a 002B     		cmp	r3, #0
+ 4753 005c 33D0     		beq	.L316
+2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4754              		.loc 1 2322 9 is_stmt 1 view .LVU1620
+2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4755              		.loc 1 2322 40 is_stmt 0 view .LVU1621
+ 4756 005e 364A     		ldr	r2, .L330+8
+ 4757 0060 DA63     		str	r2, [r3, #60]
+2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4758              		.loc 1 2325 9 is_stmt 1 view .LVU1622
+2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4759              		.loc 1 2325 13 is_stmt 0 view .LVU1623
+ 4760 0062 A36B     		ldr	r3, [r4, #56]
+2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4761              		.loc 1 2325 41 view .LVU1624
+ 4762 0064 354A     		ldr	r2, .L330+12
+ 4763 0066 DA64     		str	r2, [r3, #76]
+2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 4764              		.loc 1 2328 9 is_stmt 1 view .LVU1625
+2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 4765              		.loc 1 2328 13 is_stmt 0 view .LVU1626
+ 4766 0068 A26B     		ldr	r2, [r4, #56]
+2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 4767              		.loc 1 2328 44 view .LVU1627
+ 4768 006a 0023     		movs	r3, #0
+ 4769 006c 1364     		str	r3, [r2, #64]
+2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4770              		.loc 1 2329 9 is_stmt 1 view .LVU1628
+2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 243
+
+
+ 4771              		.loc 1 2329 13 is_stmt 0 view .LVU1629
+ 4772 006e A26B     		ldr	r2, [r4, #56]
+2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4773              		.loc 1 2329 41 view .LVU1630
+ 4774 0070 1365     		str	r3, [r2, #80]
+2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+ 4775              		.loc 1 2332 9 is_stmt 1 view .LVU1631
+2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 4776              		.loc 1 2333 83 is_stmt 0 view .LVU1632
+ 4777 0072 2268     		ldr	r2, [r4]
+2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+ 4778              		.loc 1 2332 25 view .LVU1633
+ 4779 0074 238D     		ldrh	r3, [r4, #40]
+ 4780 0076 2832     		adds	r2, r2, #40
+ 4781 0078 616A     		ldr	r1, [r4, #36]
+ 4782              	.LVL324:
+2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+ 4783              		.loc 1 2332 25 view .LVU1634
+ 4784 007a A06B     		ldr	r0, [r4, #56]
+ 4785              	.LVL325:
+2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+ 4786              		.loc 1 2332 25 view .LVU1635
+ 4787 007c FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 4788              	.LVL326:
+2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4789              		.loc 1 2351 7 is_stmt 1 view .LVU1636
+2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 4790              		.loc 1 2351 10 is_stmt 0 view .LVU1637
+ 4791 0080 78B3     		cbz	r0, .L329
+2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4792              		.loc 1 2371 9 is_stmt 1 view .LVU1638
+2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4793              		.loc 1 2371 25 is_stmt 0 view .LVU1639
+ 4794 0082 2823     		movs	r3, #40
+ 4795 0084 84F84130 		strb	r3, [r4, #65]
+2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4796              		.loc 1 2372 9 is_stmt 1 view .LVU1640
+2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4797              		.loc 1 2372 25 is_stmt 0 view .LVU1641
+ 4798 0088 0022     		movs	r2, #0
+ 4799 008a 84F84220 		strb	r2, [r4, #66]
+2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4800              		.loc 1 2375 9 is_stmt 1 view .LVU1642
+2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4801              		.loc 1 2375 25 is_stmt 0 view .LVU1643
+ 4802 008e 636C     		ldr	r3, [r4, #68]
+ 4803 0090 43F01003 		orr	r3, r3, #16
+ 4804 0094 6364     		str	r3, [r4, #68]
+2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4805              		.loc 1 2378 9 is_stmt 1 view .LVU1644
+2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4806              		.loc 1 2378 9 view .LVU1645
+ 4807 0096 84F84020 		strb	r2, [r4, #64]
+2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4808              		.loc 1 2378 9 view .LVU1646
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4809              		.loc 1 2380 9 view .LVU1647
+ARM GAS  /tmp/ccVyGVF6.s 			page 244
+
+
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4810              		.loc 1 2380 16 is_stmt 0 view .LVU1648
+ 4811 009a 0120     		movs	r0, #1
+ 4812              	.LVL327:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4813              		.loc 1 2380 16 view .LVU1649
+ 4814 009c 03E0     		b	.L312
+ 4815              	.LVL328:
+ 4816              	.L327:
+2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 4817              		.loc 1 2286 7 is_stmt 1 view .LVU1650
+2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 4818              		.loc 1 2286 23 is_stmt 0 view .LVU1651
+ 4819 009e 4FF40073 		mov	r3, #512
+ 4820 00a2 4364     		str	r3, [r0, #68]
+2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4821              		.loc 1 2287 7 is_stmt 1 view .LVU1652
+2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4822              		.loc 1 2287 15 is_stmt 0 view .LVU1653
+ 4823 00a4 0120     		movs	r0, #1
+ 4824              	.LVL329:
+ 4825              	.L312:
+2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4826              		.loc 1 2404 1 view .LVU1654
+ 4827 00a6 10BD     		pop	{r4, pc}
+ 4828              	.LVL330:
+ 4829              	.L328:
+2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4830              		.loc 1 2308 7 is_stmt 1 view .LVU1655
+2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4831              		.loc 1 2308 11 is_stmt 0 view .LVU1656
+ 4832 00a8 0368     		ldr	r3, [r0]
+2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4833              		.loc 1 2308 30 view .LVU1657
+ 4834 00aa 0A78     		ldrb	r2, [r1]	@ zero_extendqisi2
+ 4835              	.LVL331:
+2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4836              		.loc 1 2308 28 view .LVU1658
+ 4837 00ac 9A62     		str	r2, [r3, #40]
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4838              		.loc 1 2311 7 is_stmt 1 view .LVU1659
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4839              		.loc 1 2311 11 is_stmt 0 view .LVU1660
+ 4840 00ae 436A     		ldr	r3, [r0, #36]
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4841              		.loc 1 2311 21 view .LVU1661
+ 4842 00b0 0133     		adds	r3, r3, #1
+ 4843 00b2 4362     		str	r3, [r0, #36]
+2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 4844              		.loc 1 2313 7 is_stmt 1 view .LVU1662
+2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 4845              		.loc 1 2313 11 is_stmt 0 view .LVU1663
+ 4846 00b4 438D     		ldrh	r3, [r0, #42]
+ 4847 00b6 9BB2     		uxth	r3, r3
+2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 4848              		.loc 1 2313 22 view .LVU1664
+ 4849 00b8 013B     		subs	r3, r3, #1
+ARM GAS  /tmp/ccVyGVF6.s 			page 245
+
+
+ 4850 00ba 9BB2     		uxth	r3, r3
+ 4851 00bc 4385     		strh	r3, [r0, #42]	@ movhi
+2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4852              		.loc 1 2314 7 is_stmt 1 view .LVU1665
+2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4853              		.loc 1 2314 11 is_stmt 0 view .LVU1666
+ 4854 00be 038D     		ldrh	r3, [r0, #40]
+2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4855              		.loc 1 2314 21 view .LVU1667
+ 4856 00c0 013B     		subs	r3, r3, #1
+ 4857 00c2 0385     		strh	r3, [r0, #40]	@ movhi
+ 4858 00c4 C4E7     		b	.L314
+ 4859              	.L316:
+2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4860              		.loc 1 2339 9 is_stmt 1 view .LVU1668
+2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 4861              		.loc 1 2339 25 is_stmt 0 view .LVU1669
+ 4862 00c6 2823     		movs	r3, #40
+ 4863 00c8 84F84130 		strb	r3, [r4, #65]
+2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4864              		.loc 1 2340 9 is_stmt 1 view .LVU1670
+2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4865              		.loc 1 2340 25 is_stmt 0 view .LVU1671
+ 4866 00cc 0022     		movs	r2, #0
+ 4867 00ce 84F84220 		strb	r2, [r4, #66]
+2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4868              		.loc 1 2343 9 is_stmt 1 view .LVU1672
+2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4869              		.loc 1 2343 25 is_stmt 0 view .LVU1673
+ 4870 00d2 636C     		ldr	r3, [r4, #68]
+ 4871 00d4 43F08003 		orr	r3, r3, #128
+ 4872 00d8 6364     		str	r3, [r4, #68]
+2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4873              		.loc 1 2346 9 is_stmt 1 view .LVU1674
+2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4874              		.loc 1 2346 9 view .LVU1675
+ 4875 00da 84F84020 		strb	r2, [r4, #64]
+2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4876              		.loc 1 2346 9 view .LVU1676
+2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4877              		.loc 1 2348 9 view .LVU1677
+2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4878              		.loc 1 2348 16 is_stmt 0 view .LVU1678
+ 4879 00de 0120     		movs	r0, #1
+ 4880              	.LVL332:
+2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4881              		.loc 1 2348 16 view .LVU1679
+ 4882 00e0 E1E7     		b	.L312
+ 4883              	.LVL333:
+ 4884              	.L329:
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4885              		.loc 1 2354 9 is_stmt 1 view .LVU1680
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4886              		.loc 1 2354 13 is_stmt 0 view .LVU1681
+ 4887 00e2 2268     		ldr	r2, [r4]
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4888              		.loc 1 2354 29 view .LVU1682
+ARM GAS  /tmp/ccVyGVF6.s 			page 246
+
+
+ 4889 00e4 5368     		ldr	r3, [r2, #4]
+ 4890 00e6 23F40043 		bic	r3, r3, #32768
+ 4891 00ea 5360     		str	r3, [r2, #4]
+2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4892              		.loc 1 2357 9 is_stmt 1 view .LVU1683
+2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4893              		.loc 1 2357 9 view .LVU1684
+ 4894 00ec 0023     		movs	r3, #0
+ 4895 00ee 84F84030 		strb	r3, [r4, #64]
+2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4896              		.loc 1 2357 9 view .LVU1685
+2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4897              		.loc 1 2363 9 view .LVU1686
+ 4898 00f2 4FF40041 		mov	r1, #32768
+ 4899 00f6 2046     		mov	r0, r4
+ 4900              	.LVL334:
+2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4901              		.loc 1 2363 9 is_stmt 0 view .LVU1687
+ 4902 00f8 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 4903              	.LVL335:
+2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4904              		.loc 1 2366 9 is_stmt 1 view .LVU1688
+2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4905              		.loc 1 2366 13 is_stmt 0 view .LVU1689
+ 4906 00fc 2268     		ldr	r2, [r4]
+2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 4907              		.loc 1 2366 29 view .LVU1690
+ 4908 00fe 1368     		ldr	r3, [r2]
+ 4909 0100 43F48043 		orr	r3, r3, #16384
+ 4910 0104 1360     		str	r3, [r2]
+ 4911 0106 0CE0     		b	.L319
+ 4912              	.LVL336:
+ 4913              	.L315:
+2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4914              		.loc 1 2386 7 is_stmt 1 view .LVU1691
+2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4915              		.loc 1 2386 11 is_stmt 0 view .LVU1692
+ 4916 0108 2268     		ldr	r2, [r4]
+2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4917              		.loc 1 2386 27 view .LVU1693
+ 4918 010a 5368     		ldr	r3, [r2, #4]
+ 4919 010c 23F40043 		bic	r3, r3, #32768
+ 4920 0110 5360     		str	r3, [r2, #4]
+2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4921              		.loc 1 2389 7 is_stmt 1 view .LVU1694
+2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4922              		.loc 1 2389 7 view .LVU1695
+ 4923 0112 0023     		movs	r3, #0
+ 4924 0114 84F84030 		strb	r3, [r4, #64]
+2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4925              		.loc 1 2389 7 view .LVU1696
+2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4926              		.loc 1 2395 7 view .LVU1697
+ 4927 0118 4FF40041 		mov	r1, #32768
+ 4928              	.LVL337:
+2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4929              		.loc 1 2395 7 is_stmt 0 view .LVU1698
+ARM GAS  /tmp/ccVyGVF6.s 			page 247
+
+
+ 4930 011c 2046     		mov	r0, r4
+ 4931              	.LVL338:
+2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 4932              		.loc 1 2395 7 view .LVU1699
+ 4933 011e FFF7FEFF 		bl	I2C_Enable_IRQ
+ 4934              	.LVL339:
+ 4935              	.L319:
+2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 4936              		.loc 1 2398 5 is_stmt 1 view .LVU1700
+2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 4937              		.loc 1 2398 12 is_stmt 0 view .LVU1701
+ 4938 0122 0020     		movs	r0, #0
+ 4939 0124 BFE7     		b	.L312
+ 4940              	.LVL340:
+ 4941              	.L320:
+ 4942              	.LCFI55:
+ 4943              		.cfi_def_cfa_offset 0
+ 4944              		.cfi_restore 4
+ 4945              		.cfi_restore 14
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 4946              		.loc 1 2402 12 view .LVU1702
+ 4947 0126 0220     		movs	r0, #2
+ 4948              	.LVL341:
+2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4949              		.loc 1 2404 1 view .LVU1703
+ 4950 0128 7047     		bx	lr
+ 4951              	.LVL342:
+ 4952              	.L321:
+ 4953              	.LCFI56:
+ 4954              		.cfi_def_cfa_offset 8
+ 4955              		.cfi_offset 4, -8
+ 4956              		.cfi_offset 14, -4
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4957              		.loc 1 2290 5 view .LVU1704
+ 4958 012a 0220     		movs	r0, #2
+ 4959              	.LVL343:
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4960              		.loc 1 2290 5 view .LVU1705
+ 4961 012c BBE7     		b	.L312
+ 4962              	.L331:
+ 4963 012e 00BF     		.align	2
+ 4964              	.L330:
+ 4965 0130 0000FFFF 		.word	-65536
+ 4966 0134 00000000 		.word	I2C_Slave_ISR_DMA
+ 4967 0138 00000000 		.word	I2C_DMASlaveTransmitCplt
+ 4968 013c 00000000 		.word	I2C_DMAError
+ 4969              		.cfi_endproc
+ 4970              	.LFE155:
+ 4972              		.section	.text.HAL_I2C_Slave_Receive_DMA,"ax",%progbits
+ 4973              		.align	1
+ 4974              		.global	HAL_I2C_Slave_Receive_DMA
+ 4975              		.syntax unified
+ 4976              		.thumb
+ 4977              		.thumb_func
+ 4978              		.fpu fpv5-d16
+ 4980              	HAL_I2C_Slave_Receive_DMA:
+ 4981              	.LVL344:
+ARM GAS  /tmp/ccVyGVF6.s 			page 248
+
+
+ 4982              	.LFB156:
+2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 4983              		.loc 1 2415 1 is_stmt 1 view -0
+ 4984              		.cfi_startproc
+ 4985              		@ args = 0, pretend = 0, frame = 0
+ 4986              		@ frame_needed = 0, uses_anonymous_args = 0
+2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 4987              		.loc 1 2415 1 is_stmt 0 view .LVU1707
+ 4988 0000 38B5     		push	{r3, r4, r5, lr}
+ 4989              	.LCFI57:
+ 4990              		.cfi_def_cfa_offset 16
+ 4991              		.cfi_offset 3, -16
+ 4992              		.cfi_offset 4, -12
+ 4993              		.cfi_offset 5, -8
+ 4994              		.cfi_offset 14, -4
+2416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 4995              		.loc 1 2416 3 is_stmt 1 view .LVU1708
+2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4996              		.loc 1 2418 3 view .LVU1709
+2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 4997              		.loc 1 2418 11 is_stmt 0 view .LVU1710
+ 4998 0002 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 4999 0006 DBB2     		uxtb	r3, r3
+2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5000              		.loc 1 2418 6 view .LVU1711
+ 5001 0008 202B     		cmp	r3, #32
+ 5002 000a 65D1     		bne	.L338
+ 5003 000c 0446     		mov	r4, r0
+2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5004              		.loc 1 2420 5 is_stmt 1 view .LVU1712
+2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5005              		.loc 1 2420 8 is_stmt 0 view .LVU1713
+ 5006 000e 002A     		cmp	r2, #0
+ 5007 0010 18BF     		it	ne
+ 5008 0012 0029     		cmpne	r1, #0
+ 5009 0014 3AD0     		beq	.L342
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5010              		.loc 1 2426 5 is_stmt 1 view .LVU1714
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5011              		.loc 1 2426 5 view .LVU1715
+ 5012 0016 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 5013 001a 012B     		cmp	r3, #1
+ 5014 001c 5FD0     		beq	.L339
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5015              		.loc 1 2426 5 discriminator 2 view .LVU1716
+ 5016 001e 0123     		movs	r3, #1
+ 5017 0020 80F84030 		strb	r3, [r0, #64]
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5018              		.loc 1 2426 5 discriminator 2 view .LVU1717
+2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 5019              		.loc 1 2428 5 discriminator 2 view .LVU1718
+2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+ 5020              		.loc 1 2428 23 is_stmt 0 discriminator 2 view .LVU1719
+ 5021 0024 2223     		movs	r3, #34
+ 5022 0026 80F84130 		strb	r3, [r0, #65]
+2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 5023              		.loc 1 2429 5 is_stmt 1 discriminator 2 view .LVU1720
+ARM GAS  /tmp/ccVyGVF6.s 			page 249
+
+
+2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 5024              		.loc 1 2429 23 is_stmt 0 discriminator 2 view .LVU1721
+ 5025 002a 2023     		movs	r3, #32
+ 5026 002c 80F84230 		strb	r3, [r0, #66]
+2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5027              		.loc 1 2430 5 is_stmt 1 discriminator 2 view .LVU1722
+2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5028              		.loc 1 2430 23 is_stmt 0 discriminator 2 view .LVU1723
+ 5029 0030 0023     		movs	r3, #0
+ 5030 0032 4364     		str	r3, [r0, #68]
+2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 5031              		.loc 1 2433 5 is_stmt 1 discriminator 2 view .LVU1724
+2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 5032              		.loc 1 2433 23 is_stmt 0 discriminator 2 view .LVU1725
+ 5033 0034 4162     		str	r1, [r0, #36]
+2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 5034              		.loc 1 2434 5 is_stmt 1 discriminator 2 view .LVU1726
+2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 5035              		.loc 1 2434 23 is_stmt 0 discriminator 2 view .LVU1727
+ 5036 0036 4285     		strh	r2, [r0, #42]	@ movhi
+2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 5037              		.loc 1 2435 5 is_stmt 1 discriminator 2 view .LVU1728
+2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 5038              		.loc 1 2435 29 is_stmt 0 discriminator 2 view .LVU1729
+ 5039 0038 438D     		ldrh	r3, [r0, #42]
+2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 5040              		.loc 1 2435 23 discriminator 2 view .LVU1730
+ 5041 003a 0385     		strh	r3, [r0, #40]	@ movhi
+2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 5042              		.loc 1 2436 5 is_stmt 1 discriminator 2 view .LVU1731
+2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 5043              		.loc 1 2436 23 is_stmt 0 discriminator 2 view .LVU1732
+ 5044 003c 294B     		ldr	r3, .L344
+ 5045 003e C362     		str	r3, [r0, #44]
+2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5046              		.loc 1 2437 5 is_stmt 1 discriminator 2 view .LVU1733
+2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5047              		.loc 1 2437 23 is_stmt 0 discriminator 2 view .LVU1734
+ 5048 0040 294B     		ldr	r3, .L344+4
+ 5049 0042 4363     		str	r3, [r0, #52]
+2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5050              		.loc 1 2439 5 is_stmt 1 discriminator 2 view .LVU1735
+2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5051              		.loc 1 2439 13 is_stmt 0 discriminator 2 view .LVU1736
+ 5052 0044 C36B     		ldr	r3, [r0, #60]
+2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5053              		.loc 1 2439 8 discriminator 2 view .LVU1737
+ 5054 0046 33B3     		cbz	r3, .L335
+2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5055              		.loc 1 2442 7 is_stmt 1 view .LVU1738
+2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5056              		.loc 1 2442 38 is_stmt 0 view .LVU1739
+ 5057 0048 284A     		ldr	r2, .L344+8
+ 5058              	.LVL345:
+2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5059              		.loc 1 2442 38 view .LVU1740
+ 5060 004a DA63     		str	r2, [r3, #60]
+ARM GAS  /tmp/ccVyGVF6.s 			page 250
+
+
+2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5061              		.loc 1 2445 7 is_stmt 1 view .LVU1741
+2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5062              		.loc 1 2445 11 is_stmt 0 view .LVU1742
+ 5063 004c C36B     		ldr	r3, [r0, #60]
+2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5064              		.loc 1 2445 39 view .LVU1743
+ 5065 004e 284A     		ldr	r2, .L344+12
+ 5066 0050 DA64     		str	r2, [r3, #76]
+2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 5067              		.loc 1 2448 7 is_stmt 1 view .LVU1744
+2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 5068              		.loc 1 2448 11 is_stmt 0 view .LVU1745
+ 5069 0052 C26B     		ldr	r2, [r0, #60]
+2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 5070              		.loc 1 2448 42 view .LVU1746
+ 5071 0054 0023     		movs	r3, #0
+ 5072 0056 1364     		str	r3, [r2, #64]
+2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5073              		.loc 1 2449 7 is_stmt 1 view .LVU1747
+2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5074              		.loc 1 2449 11 is_stmt 0 view .LVU1748
+ 5075 0058 C26B     		ldr	r2, [r0, #60]
+2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5076              		.loc 1 2449 39 view .LVU1749
+ 5077 005a 1365     		str	r3, [r2, #80]
+2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 5078              		.loc 1 2452 7 is_stmt 1 view .LVU1750
+2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 5079              		.loc 1 2452 69 is_stmt 0 view .LVU1751
+ 5080 005c 0068     		ldr	r0, [r0]
+ 5081              	.LVL346:
+2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 5082              		.loc 1 2452 23 view .LVU1752
+ 5083 005e 238D     		ldrh	r3, [r4, #40]
+ 5084 0060 0A46     		mov	r2, r1
+ 5085 0062 00F12401 		add	r1, r0, #36
+ 5086              	.LVL347:
+2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 5087              		.loc 1 2452 23 view .LVU1753
+ 5088 0066 E06B     		ldr	r0, [r4, #60]
+ 5089 0068 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 5090              	.LVL348:
+2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5091              		.loc 1 2470 5 is_stmt 1 view .LVU1754
+2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5092              		.loc 1 2470 8 is_stmt 0 view .LVU1755
+ 5093 006c 0546     		mov	r5, r0
+ 5094 006e 00B3     		cbz	r0, .L343
+2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 5095              		.loc 1 2490 7 is_stmt 1 view .LVU1756
+2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 5096              		.loc 1 2490 23 is_stmt 0 view .LVU1757
+ 5097 0070 2823     		movs	r3, #40
+ 5098 0072 84F84130 		strb	r3, [r4, #65]
+2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5099              		.loc 1 2491 7 is_stmt 1 view .LVU1758
+ARM GAS  /tmp/ccVyGVF6.s 			page 251
+
+
+2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5100              		.loc 1 2491 23 is_stmt 0 view .LVU1759
+ 5101 0076 0022     		movs	r2, #0
+ 5102 0078 84F84220 		strb	r2, [r4, #66]
+2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5103              		.loc 1 2494 7 is_stmt 1 view .LVU1760
+2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5104              		.loc 1 2494 23 is_stmt 0 view .LVU1761
+ 5105 007c 636C     		ldr	r3, [r4, #68]
+ 5106 007e 43F01003 		orr	r3, r3, #16
+ 5107 0082 6364     		str	r3, [r4, #68]
+2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5108              		.loc 1 2497 7 is_stmt 1 view .LVU1762
+2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5109              		.loc 1 2497 7 view .LVU1763
+ 5110 0084 84F84020 		strb	r2, [r4, #64]
+2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5111              		.loc 1 2497 7 view .LVU1764
+2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5112              		.loc 1 2499 7 view .LVU1765
+2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5113              		.loc 1 2499 14 is_stmt 0 view .LVU1766
+ 5114 0088 0125     		movs	r5, #1
+ 5115 008a 26E0     		b	.L333
+ 5116              	.LVL349:
+ 5117              	.L342:
+2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5118              		.loc 1 2422 7 is_stmt 1 view .LVU1767
+2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5119              		.loc 1 2422 23 is_stmt 0 view .LVU1768
+ 5120 008c 4FF40073 		mov	r3, #512
+ 5121 0090 4364     		str	r3, [r0, #68]
+2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5122              		.loc 1 2423 7 is_stmt 1 view .LVU1769
+2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5123              		.loc 1 2423 15 is_stmt 0 view .LVU1770
+ 5124 0092 0125     		movs	r5, #1
+ 5125 0094 21E0     		b	.L333
+ 5126              	.L335:
+2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 5127              		.loc 1 2458 7 is_stmt 1 view .LVU1771
+2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 5128              		.loc 1 2458 23 is_stmt 0 view .LVU1772
+ 5129 0096 2823     		movs	r3, #40
+ 5130 0098 80F84130 		strb	r3, [r0, #65]
+2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5131              		.loc 1 2459 7 is_stmt 1 view .LVU1773
+2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5132              		.loc 1 2459 23 is_stmt 0 view .LVU1774
+ 5133 009c 0022     		movs	r2, #0
+ 5134              	.LVL350:
+2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5135              		.loc 1 2459 23 view .LVU1775
+ 5136 009e 80F84220 		strb	r2, [r0, #66]
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5137              		.loc 1 2462 7 is_stmt 1 view .LVU1776
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 252
+
+
+ 5138              		.loc 1 2462 23 is_stmt 0 view .LVU1777
+ 5139 00a2 436C     		ldr	r3, [r0, #68]
+ 5140 00a4 43F08003 		orr	r3, r3, #128
+ 5141 00a8 4364     		str	r3, [r0, #68]
+2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5142              		.loc 1 2465 7 is_stmt 1 view .LVU1778
+2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5143              		.loc 1 2465 7 view .LVU1779
+ 5144 00aa 80F84020 		strb	r2, [r0, #64]
+2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5145              		.loc 1 2465 7 view .LVU1780
+2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5146              		.loc 1 2467 7 view .LVU1781
+2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5147              		.loc 1 2467 14 is_stmt 0 view .LVU1782
+ 5148 00ae 0125     		movs	r5, #1
+ 5149 00b0 13E0     		b	.L333
+ 5150              	.LVL351:
+ 5151              	.L343:
+2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5152              		.loc 1 2473 7 is_stmt 1 view .LVU1783
+2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5153              		.loc 1 2473 11 is_stmt 0 view .LVU1784
+ 5154 00b2 2268     		ldr	r2, [r4]
+2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5155              		.loc 1 2473 27 view .LVU1785
+ 5156 00b4 5368     		ldr	r3, [r2, #4]
+ 5157 00b6 23F40043 		bic	r3, r3, #32768
+ 5158 00ba 5360     		str	r3, [r2, #4]
+2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5159              		.loc 1 2476 7 is_stmt 1 view .LVU1786
+2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5160              		.loc 1 2476 7 view .LVU1787
+ 5161 00bc 0023     		movs	r3, #0
+ 5162 00be 84F84030 		strb	r3, [r4, #64]
+2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5163              		.loc 1 2476 7 view .LVU1788
+2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5164              		.loc 1 2482 7 view .LVU1789
+ 5165 00c2 4FF40041 		mov	r1, #32768
+ 5166 00c6 2046     		mov	r0, r4
+ 5167              	.LVL352:
+2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5168              		.loc 1 2482 7 is_stmt 0 view .LVU1790
+ 5169 00c8 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 5170              	.LVL353:
+2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5171              		.loc 1 2485 7 is_stmt 1 view .LVU1791
+2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5172              		.loc 1 2485 11 is_stmt 0 view .LVU1792
+ 5173 00cc 2268     		ldr	r2, [r4]
+2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5174              		.loc 1 2485 27 view .LVU1793
+ 5175 00ce 1368     		ldr	r3, [r2]
+ 5176 00d0 43F40043 		orr	r3, r3, #32768
+ 5177 00d4 1360     		str	r3, [r2]
+2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccVyGVF6.s 			page 253
+
+
+ 5178              		.loc 1 2502 5 is_stmt 1 view .LVU1794
+2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 5179              		.loc 1 2502 12 is_stmt 0 view .LVU1795
+ 5180 00d6 00E0     		b	.L333
+ 5181              	.LVL354:
+ 5182              	.L338:
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 5183              		.loc 1 2506 12 view .LVU1796
+ 5184 00d8 0225     		movs	r5, #2
+ 5185              	.LVL355:
+ 5186              	.L333:
+2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5187              		.loc 1 2508 1 view .LVU1797
+ 5188 00da 2846     		mov	r0, r5
+ 5189 00dc 38BD     		pop	{r3, r4, r5, pc}
+ 5190              	.LVL356:
+ 5191              	.L339:
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5192              		.loc 1 2426 5 view .LVU1798
+ 5193 00de 0225     		movs	r5, #2
+ 5194 00e0 FBE7     		b	.L333
+ 5195              	.L345:
+ 5196 00e2 00BF     		.align	2
+ 5197              	.L344:
+ 5198 00e4 0000FFFF 		.word	-65536
+ 5199 00e8 00000000 		.word	I2C_Slave_ISR_DMA
+ 5200 00ec 00000000 		.word	I2C_DMASlaveReceiveCplt
+ 5201 00f0 00000000 		.word	I2C_DMAError
+ 5202              		.cfi_endproc
+ 5203              	.LFE156:
+ 5205              		.section	.text.HAL_I2C_Mem_Write,"ax",%progbits
+ 5206              		.align	1
+ 5207              		.global	HAL_I2C_Mem_Write
+ 5208              		.syntax unified
+ 5209              		.thumb
+ 5210              		.thumb_func
+ 5211              		.fpu fpv5-d16
+ 5213              	HAL_I2C_Mem_Write:
+ 5214              	.LVL357:
+ 5215              	.LFB157:
+2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 5216              		.loc 1 2525 1 is_stmt 1 view -0
+ 5217              		.cfi_startproc
+ 5218              		@ args = 12, pretend = 0, frame = 0
+ 5219              		@ frame_needed = 0, uses_anonymous_args = 0
+2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 5220              		.loc 1 2525 1 is_stmt 0 view .LVU1800
+ 5221 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 5222              	.LCFI58:
+ 5223              		.cfi_def_cfa_offset 36
+ 5224              		.cfi_offset 4, -36
+ 5225              		.cfi_offset 5, -32
+ 5226              		.cfi_offset 6, -28
+ 5227              		.cfi_offset 7, -24
+ 5228              		.cfi_offset 8, -20
+ 5229              		.cfi_offset 9, -16
+ 5230              		.cfi_offset 10, -12
+ARM GAS  /tmp/ccVyGVF6.s 			page 254
+
+
+ 5231              		.cfi_offset 11, -8
+ 5232              		.cfi_offset 14, -4
+ 5233 0004 83B0     		sub	sp, sp, #12
+ 5234              	.LCFI59:
+ 5235              		.cfi_def_cfa_offset 48
+ 5236 0006 0D46     		mov	r5, r1
+ 5237 0008 BDF834A0 		ldrh	r10, [sp, #52]
+ 5238 000c 0E9F     		ldr	r7, [sp, #56]
+2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5239              		.loc 1 2526 3 is_stmt 1 view .LVU1801
+2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5240              		.loc 1 2529 3 view .LVU1802
+2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5241              		.loc 1 2531 3 view .LVU1803
+2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5242              		.loc 1 2531 11 is_stmt 0 view .LVU1804
+ 5243 000e 90F84110 		ldrb	r1, [r0, #65]	@ zero_extendqisi2
+ 5244              	.LVL358:
+2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5245              		.loc 1 2531 11 view .LVU1805
+ 5246 0012 C9B2     		uxtb	r1, r1
+2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5247              		.loc 1 2531 6 view .LVU1806
+ 5248 0014 2029     		cmp	r1, #32
+ 5249 0016 40F0BC80 		bne	.L355
+ 5250 001a 0446     		mov	r4, r0
+ 5251 001c 9046     		mov	r8, r2
+ 5252 001e 9946     		mov	r9, r3
+2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5253              		.loc 1 2533 5 is_stmt 1 view .LVU1807
+2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5254              		.loc 1 2533 8 is_stmt 0 view .LVU1808
+ 5255 0020 0C9B     		ldr	r3, [sp, #48]
+ 5256              	.LVL359:
+2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5257              		.loc 1 2533 8 view .LVU1809
+ 5258 0022 BAF1000F 		cmp	r10, #0
+ 5259 0026 18BF     		it	ne
+ 5260 0028 002B     		cmpne	r3, #0
+ 5261 002a 16D0     		beq	.L362
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5262              		.loc 1 2540 5 is_stmt 1 view .LVU1810
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5263              		.loc 1 2540 5 view .LVU1811
+ 5264 002c 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 5265 0030 012B     		cmp	r3, #1
+ 5266 0032 00F0B280 		beq	.L356
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5267              		.loc 1 2540 5 discriminator 2 view .LVU1812
+ 5268 0036 4FF0010B 		mov	fp, #1
+ 5269 003a 80F840B0 		strb	fp, [r0, #64]
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5270              		.loc 1 2540 5 discriminator 2 view .LVU1813
+2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5271              		.loc 1 2543 5 discriminator 2 view .LVU1814
+2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5272              		.loc 1 2543 17 is_stmt 0 discriminator 2 view .LVU1815
+ARM GAS  /tmp/ccVyGVF6.s 			page 255
+
+
+ 5273 003e FFF7FEFF 		bl	HAL_GetTick
+ 5274              	.LVL360:
+2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5275              		.loc 1 2543 17 discriminator 2 view .LVU1816
+ 5276 0042 0646     		mov	r6, r0
+ 5277              	.LVL361:
+2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5278              		.loc 1 2545 5 is_stmt 1 discriminator 2 view .LVU1817
+2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5279              		.loc 1 2545 9 is_stmt 0 discriminator 2 view .LVU1818
+ 5280 0044 0090     		str	r0, [sp]
+ 5281 0046 1923     		movs	r3, #25
+ 5282 0048 5A46     		mov	r2, fp
+ 5283 004a 4FF40041 		mov	r1, #32768
+ 5284 004e 2046     		mov	r0, r4
+ 5285              	.LVL362:
+2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5286              		.loc 1 2545 9 discriminator 2 view .LVU1819
+ 5287 0050 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 5288              	.LVL363:
+2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5289              		.loc 1 2545 8 discriminator 2 view .LVU1820
+ 5290 0054 30B1     		cbz	r0, .L363
+2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5291              		.loc 1 2547 14 view .LVU1821
+ 5292 0056 0120     		movs	r0, #1
+ 5293 0058 9CE0     		b	.L347
+ 5294              	.LVL364:
+ 5295              	.L362:
+2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5296              		.loc 1 2535 7 is_stmt 1 view .LVU1822
+2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5297              		.loc 1 2535 23 is_stmt 0 view .LVU1823
+ 5298 005a 4FF40073 		mov	r3, #512
+ 5299 005e 4364     		str	r3, [r0, #68]
+2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5300              		.loc 1 2536 7 is_stmt 1 view .LVU1824
+2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5301              		.loc 1 2536 15 is_stmt 0 view .LVU1825
+ 5302 0060 0120     		movs	r0, #1
+ 5303              	.LVL365:
+2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5304              		.loc 1 2536 15 view .LVU1826
+ 5305 0062 97E0     		b	.L347
+ 5306              	.LVL366:
+ 5307              	.L363:
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+ 5308              		.loc 1 2550 5 is_stmt 1 view .LVU1827
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+ 5309              		.loc 1 2550 21 is_stmt 0 view .LVU1828
+ 5310 0064 2123     		movs	r3, #33
+ 5311 0066 84F84130 		strb	r3, [r4, #65]
+2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 5312              		.loc 1 2551 5 is_stmt 1 view .LVU1829
+2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 5313              		.loc 1 2551 21 is_stmt 0 view .LVU1830
+ 5314 006a 4023     		movs	r3, #64
+ARM GAS  /tmp/ccVyGVF6.s 			page 256
+
+
+ 5315 006c 84F84230 		strb	r3, [r4, #66]
+2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5316              		.loc 1 2552 5 is_stmt 1 view .LVU1831
+2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5317              		.loc 1 2552 21 is_stmt 0 view .LVU1832
+ 5318 0070 0023     		movs	r3, #0
+ 5319 0072 6364     		str	r3, [r4, #68]
+2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 5320              		.loc 1 2555 5 is_stmt 1 view .LVU1833
+2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 5321              		.loc 1 2555 21 is_stmt 0 view .LVU1834
+ 5322 0074 0C9A     		ldr	r2, [sp, #48]
+ 5323 0076 6262     		str	r2, [r4, #36]
+2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 5324              		.loc 1 2556 5 is_stmt 1 view .LVU1835
+2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 5325              		.loc 1 2556 21 is_stmt 0 view .LVU1836
+ 5326 0078 A4F82AA0 		strh	r10, [r4, #42]	@ movhi
+2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5327              		.loc 1 2557 5 is_stmt 1 view .LVU1837
+2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5328              		.loc 1 2557 21 is_stmt 0 view .LVU1838
+ 5329 007c 6363     		str	r3, [r4, #52]
+2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5330              		.loc 1 2560 5 is_stmt 1 view .LVU1839
+2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5331              		.loc 1 2560 9 is_stmt 0 view .LVU1840
+ 5332 007e 0196     		str	r6, [sp, #4]
+ 5333 0080 0097     		str	r7, [sp]
+ 5334 0082 4B46     		mov	r3, r9
+ 5335 0084 4246     		mov	r2, r8
+ 5336 0086 2946     		mov	r1, r5
+ 5337 0088 2046     		mov	r0, r4
+ 5338 008a FFF7FEFF 		bl	I2C_RequestMemoryWrite
+ 5339              	.LVL367:
+2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5340              		.loc 1 2560 8 view .LVU1841
+ 5341 008e 70B9     		cbnz	r0, .L364
+2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5342              		.loc 1 2568 5 is_stmt 1 view .LVU1842
+2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5343              		.loc 1 2568 13 is_stmt 0 view .LVU1843
+ 5344 0090 638D     		ldrh	r3, [r4, #42]
+ 5345 0092 9BB2     		uxth	r3, r3
+2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5346              		.loc 1 2568 8 view .LVU1844
+ 5347 0094 FF2B     		cmp	r3, #255
+ 5348 0096 0FD9     		bls	.L350
+2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST
+ 5349              		.loc 1 2570 7 is_stmt 1 view .LVU1845
+2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST
+ 5350              		.loc 1 2570 22 is_stmt 0 view .LVU1846
+ 5351 0098 FF22     		movs	r2, #255
+ 5352 009a 2285     		strh	r2, [r4, #40]	@ movhi
+2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5353              		.loc 1 2571 7 is_stmt 1 view .LVU1847
+ 5354 009c 0023     		movs	r3, #0
+ARM GAS  /tmp/ccVyGVF6.s 			page 257
+
+
+ 5355 009e 0093     		str	r3, [sp]
+ 5356 00a0 4FF08073 		mov	r3, #16777216
+ 5357 00a4 2946     		mov	r1, r5
+ 5358 00a6 2046     		mov	r0, r4
+ 5359 00a8 FFF7FEFF 		bl	I2C_TransferConfig
+ 5360              	.LVL368:
+ 5361 00ac 21E0     		b	.L354
+ 5362              	.L364:
+2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 5363              		.loc 1 2563 7 view .LVU1848
+2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 5364              		.loc 1 2563 7 view .LVU1849
+ 5365 00ae 0023     		movs	r3, #0
+ 5366 00b0 84F84030 		strb	r3, [r4, #64]
+2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 5367              		.loc 1 2563 7 view .LVU1850
+2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5368              		.loc 1 2564 7 view .LVU1851
+2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5369              		.loc 1 2564 14 is_stmt 0 view .LVU1852
+ 5370 00b4 5846     		mov	r0, fp
+ 5371 00b6 6DE0     		b	.L347
+ 5372              	.L350:
+2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS
+ 5373              		.loc 1 2575 7 is_stmt 1 view .LVU1853
+2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS
+ 5374              		.loc 1 2575 28 is_stmt 0 view .LVU1854
+ 5375 00b8 628D     		ldrh	r2, [r4, #42]
+ 5376 00ba 92B2     		uxth	r2, r2
+2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS
+ 5377              		.loc 1 2575 22 view .LVU1855
+ 5378 00bc 2285     		strh	r2, [r4, #40]	@ movhi
+2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5379              		.loc 1 2576 7 is_stmt 1 view .LVU1856
+ 5380 00be 0023     		movs	r3, #0
+ 5381 00c0 0093     		str	r3, [sp]
+ 5382 00c2 4FF00073 		mov	r3, #33554432
+ 5383 00c6 D2B2     		uxtb	r2, r2
+ 5384 00c8 2946     		mov	r1, r5
+ 5385 00ca 2046     		mov	r0, r4
+ 5386 00cc FFF7FEFF 		bl	I2C_TransferConfig
+ 5387              	.LVL369:
+ 5388 00d0 0FE0     		b	.L354
+ 5389              	.L353:
+2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5390              		.loc 1 2612 11 view .LVU1857
+2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5391              		.loc 1 2612 32 is_stmt 0 view .LVU1858
+ 5392 00d2 628D     		ldrh	r2, [r4, #42]
+ 5393 00d4 92B2     		uxth	r2, r2
+2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5394              		.loc 1 2612 26 view .LVU1859
+ 5395 00d6 2285     		strh	r2, [r4, #40]	@ movhi
+2613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 5396              		.loc 1 2613 11 is_stmt 1 view .LVU1860
+ 5397 00d8 0023     		movs	r3, #0
+ 5398 00da 0093     		str	r3, [sp]
+ARM GAS  /tmp/ccVyGVF6.s 			page 258
+
+
+ 5399 00dc 4FF00073 		mov	r3, #33554432
+ 5400 00e0 D2B2     		uxtb	r2, r2
+ 5401 00e2 2946     		mov	r1, r5
+ 5402 00e4 2046     		mov	r0, r4
+ 5403 00e6 FFF7FEFF 		bl	I2C_TransferConfig
+ 5404              	.LVL370:
+ 5405              	.L352:
+2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5406              		.loc 1 2618 13 view .LVU1861
+2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5407              		.loc 1 2618 18 is_stmt 0 view .LVU1862
+ 5408 00ea 638D     		ldrh	r3, [r4, #42]
+ 5409 00ec 9BB2     		uxth	r3, r3
+2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5410              		.loc 1 2618 5 view .LVU1863
+ 5411 00ee 002B     		cmp	r3, #0
+ 5412 00f0 33D0     		beq	.L365
+ 5413              	.L354:
+2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5414              		.loc 1 2579 5 is_stmt 1 view .LVU1864
+2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5415              		.loc 1 2582 7 view .LVU1865
+2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5416              		.loc 1 2582 11 is_stmt 0 view .LVU1866
+ 5417 00f2 3246     		mov	r2, r6
+ 5418 00f4 3946     		mov	r1, r7
+ 5419 00f6 2046     		mov	r0, r4
+ 5420 00f8 FFF7FEFF 		bl	I2C_WaitOnTXISFlagUntilTimeout
+ 5421              	.LVL371:
+2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5422              		.loc 1 2582 10 view .LVU1867
+ 5423 00fc 0028     		cmp	r0, #0
+ 5424 00fe 4ED1     		bne	.L358
+2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5425              		.loc 1 2588 7 is_stmt 1 view .LVU1868
+2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5426              		.loc 1 2588 35 is_stmt 0 view .LVU1869
+ 5427 0100 626A     		ldr	r2, [r4, #36]
+2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5428              		.loc 1 2588 11 view .LVU1870
+ 5429 0102 2368     		ldr	r3, [r4]
+2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5430              		.loc 1 2588 30 view .LVU1871
+ 5431 0104 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5432              		.loc 1 2588 28 view .LVU1872
+ 5433 0106 9A62     		str	r2, [r3, #40]
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5434              		.loc 1 2591 7 is_stmt 1 view .LVU1873
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5435              		.loc 1 2591 11 is_stmt 0 view .LVU1874
+ 5436 0108 636A     		ldr	r3, [r4, #36]
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5437              		.loc 1 2591 21 view .LVU1875
+ 5438 010a 0133     		adds	r3, r3, #1
+ 5439 010c 6362     		str	r3, [r4, #36]
+2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ARM GAS  /tmp/ccVyGVF6.s 			page 259
+
+
+ 5440              		.loc 1 2593 7 is_stmt 1 view .LVU1876
+2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 5441              		.loc 1 2593 11 is_stmt 0 view .LVU1877
+ 5442 010e 638D     		ldrh	r3, [r4, #42]
+ 5443 0110 9BB2     		uxth	r3, r3
+2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 5444              		.loc 1 2593 22 view .LVU1878
+ 5445 0112 013B     		subs	r3, r3, #1
+ 5446 0114 9BB2     		uxth	r3, r3
+ 5447 0116 6385     		strh	r3, [r4, #42]	@ movhi
+2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5448              		.loc 1 2594 7 is_stmt 1 view .LVU1879
+2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5449              		.loc 1 2594 11 is_stmt 0 view .LVU1880
+ 5450 0118 238D     		ldrh	r3, [r4, #40]
+2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5451              		.loc 1 2594 21 view .LVU1881
+ 5452 011a 013B     		subs	r3, r3, #1
+ 5453 011c 9BB2     		uxth	r3, r3
+ 5454 011e 2385     		strh	r3, [r4, #40]	@ movhi
+2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5455              		.loc 1 2596 7 is_stmt 1 view .LVU1882
+2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5456              		.loc 1 2596 16 is_stmt 0 view .LVU1883
+ 5457 0120 628D     		ldrh	r2, [r4, #42]
+ 5458 0122 92B2     		uxth	r2, r2
+2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5459              		.loc 1 2596 10 view .LVU1884
+ 5460 0124 002A     		cmp	r2, #0
+ 5461 0126 E0D0     		beq	.L352
+2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5462              		.loc 1 2596 35 discriminator 1 view .LVU1885
+ 5463 0128 002B     		cmp	r3, #0
+ 5464 012a DED1     		bne	.L352
+2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5465              		.loc 1 2599 9 is_stmt 1 view .LVU1886
+2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5466              		.loc 1 2599 13 is_stmt 0 view .LVU1887
+ 5467 012c 0096     		str	r6, [sp]
+ 5468 012e 3B46     		mov	r3, r7
+ 5469 0130 0022     		movs	r2, #0
+ 5470 0132 8021     		movs	r1, #128
+ 5471 0134 2046     		mov	r0, r4
+ 5472 0136 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 5473              	.LVL372:
+2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5474              		.loc 1 2599 12 view .LVU1888
+ 5475 013a 90BB     		cbnz	r0, .L359
+2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5476              		.loc 1 2604 9 is_stmt 1 view .LVU1889
+2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5477              		.loc 1 2604 17 is_stmt 0 view .LVU1890
+ 5478 013c 638D     		ldrh	r3, [r4, #42]
+ 5479 013e 9BB2     		uxth	r3, r3
+2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5480              		.loc 1 2604 12 view .LVU1891
+ 5481 0140 FF2B     		cmp	r3, #255
+ARM GAS  /tmp/ccVyGVF6.s 			page 260
+
+
+ 5482 0142 C6D9     		bls	.L353
+2606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 5483              		.loc 1 2606 11 is_stmt 1 view .LVU1892
+2606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 5484              		.loc 1 2606 26 is_stmt 0 view .LVU1893
+ 5485 0144 FF22     		movs	r2, #255
+ 5486 0146 2285     		strh	r2, [r4, #40]	@ movhi
+2607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 5487              		.loc 1 2607 11 is_stmt 1 view .LVU1894
+ 5488 0148 0023     		movs	r3, #0
+ 5489 014a 0093     		str	r3, [sp]
+ 5490 014c 4FF08073 		mov	r3, #16777216
+ 5491 0150 2946     		mov	r1, r5
+ 5492 0152 2046     		mov	r0, r4
+ 5493 0154 FFF7FEFF 		bl	I2C_TransferConfig
+ 5494              	.LVL373:
+ 5495 0158 C7E7     		b	.L352
+ 5496              	.L365:
+2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5497              		.loc 1 2622 5 view .LVU1895
+2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5498              		.loc 1 2622 9 is_stmt 0 view .LVU1896
+ 5499 015a 3246     		mov	r2, r6
+ 5500 015c 3946     		mov	r1, r7
+ 5501 015e 2046     		mov	r0, r4
+ 5502 0160 FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 5503              	.LVL374:
+2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5504              		.loc 1 2622 8 view .LVU1897
+ 5505 0164 F8B9     		cbnz	r0, .L360
+2628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5506              		.loc 1 2628 5 is_stmt 1 view .LVU1898
+ 5507 0166 2368     		ldr	r3, [r4]
+ 5508 0168 2022     		movs	r2, #32
+ 5509 016a DA61     		str	r2, [r3, #28]
+2631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5510              		.loc 1 2631 5 view .LVU1899
+ 5511 016c 2168     		ldr	r1, [r4]
+ 5512 016e 4B68     		ldr	r3, [r1, #4]
+ 5513 0170 23F0FF73 		bic	r3, r3, #33423360
+ 5514 0174 23F48B33 		bic	r3, r3, #71168
+ 5515 0178 23F4FF73 		bic	r3, r3, #510
+ 5516 017c 23F00103 		bic	r3, r3, #1
+ 5517 0180 4B60     		str	r3, [r1, #4]
+2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 5518              		.loc 1 2633 5 view .LVU1900
+2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 5519              		.loc 1 2633 17 is_stmt 0 view .LVU1901
+ 5520 0182 84F84120 		strb	r2, [r4, #65]
+2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5521              		.loc 1 2634 5 is_stmt 1 view .LVU1902
+2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5522              		.loc 1 2634 17 is_stmt 0 view .LVU1903
+ 5523 0186 0023     		movs	r3, #0
+ 5524 0188 84F84230 		strb	r3, [r4, #66]
+2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5525              		.loc 1 2637 5 is_stmt 1 view .LVU1904
+ARM GAS  /tmp/ccVyGVF6.s 			page 261
+
+
+2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5526              		.loc 1 2637 5 view .LVU1905
+ 5527 018c 84F84030 		strb	r3, [r4, #64]
+2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5528              		.loc 1 2637 5 view .LVU1906
+2639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 5529              		.loc 1 2639 5 view .LVU1907
+2639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 5530              		.loc 1 2639 12 is_stmt 0 view .LVU1908
+ 5531 0190 00E0     		b	.L347
+ 5532              	.LVL375:
+ 5533              	.L355:
+2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 5534              		.loc 1 2643 12 view .LVU1909
+ 5535 0192 0220     		movs	r0, #2
+ 5536              	.LVL376:
+ 5537              	.L347:
+2645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5538              		.loc 1 2645 1 view .LVU1910
+ 5539 0194 03B0     		add	sp, sp, #12
+ 5540              	.LCFI60:
+ 5541              		.cfi_remember_state
+ 5542              		.cfi_def_cfa_offset 36
+ 5543              		@ sp needed
+ 5544 0196 BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 5545              	.LVL377:
+ 5546              	.L356:
+ 5547              	.LCFI61:
+ 5548              		.cfi_restore_state
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5549              		.loc 1 2540 5 view .LVU1911
+ 5550 019a 0220     		movs	r0, #2
+ 5551              	.LVL378:
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5552              		.loc 1 2540 5 view .LVU1912
+ 5553 019c FAE7     		b	.L347
+ 5554              	.LVL379:
+ 5555              	.L358:
+2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 5556              		.loc 1 2584 16 view .LVU1913
+ 5557 019e 0120     		movs	r0, #1
+ 5558 01a0 F8E7     		b	.L347
+ 5559              	.L359:
+2601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 5560              		.loc 1 2601 18 view .LVU1914
+ 5561 01a2 0120     		movs	r0, #1
+ 5562 01a4 F6E7     		b	.L347
+ 5563              	.L360:
+2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5564              		.loc 1 2624 14 view .LVU1915
+ 5565 01a6 0120     		movs	r0, #1
+ 5566 01a8 F4E7     		b	.L347
+ 5567              		.cfi_endproc
+ 5568              	.LFE157:
+ 5570              		.section	.text.HAL_I2C_Mem_Read,"ax",%progbits
+ 5571              		.align	1
+ 5572              		.global	HAL_I2C_Mem_Read
+ARM GAS  /tmp/ccVyGVF6.s 			page 262
+
+
+ 5573              		.syntax unified
+ 5574              		.thumb
+ 5575              		.thumb_func
+ 5576              		.fpu fpv5-d16
+ 5578              	HAL_I2C_Mem_Read:
+ 5579              	.LVL380:
+ 5580              	.LFB158:
+2662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 5581              		.loc 1 2662 1 is_stmt 1 view -0
+ 5582              		.cfi_startproc
+ 5583              		@ args = 12, pretend = 0, frame = 0
+ 5584              		@ frame_needed = 0, uses_anonymous_args = 0
+2662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 5585              		.loc 1 2662 1 is_stmt 0 view .LVU1917
+ 5586 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 5587              	.LCFI62:
+ 5588              		.cfi_def_cfa_offset 36
+ 5589              		.cfi_offset 4, -36
+ 5590              		.cfi_offset 5, -32
+ 5591              		.cfi_offset 6, -28
+ 5592              		.cfi_offset 7, -24
+ 5593              		.cfi_offset 8, -20
+ 5594              		.cfi_offset 9, -16
+ 5595              		.cfi_offset 10, -12
+ 5596              		.cfi_offset 11, -8
+ 5597              		.cfi_offset 14, -4
+ 5598 0004 83B0     		sub	sp, sp, #12
+ 5599              	.LCFI63:
+ 5600              		.cfi_def_cfa_offset 48
+ 5601 0006 0D46     		mov	r5, r1
+ 5602 0008 BDF834A0 		ldrh	r10, [sp, #52]
+ 5603 000c 0E9F     		ldr	r7, [sp, #56]
+2663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5604              		.loc 1 2663 3 is_stmt 1 view .LVU1918
+2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5605              		.loc 1 2666 3 view .LVU1919
+2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5606              		.loc 1 2668 3 view .LVU1920
+2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5607              		.loc 1 2668 11 is_stmt 0 view .LVU1921
+ 5608 000e 90F84110 		ldrb	r1, [r0, #65]	@ zero_extendqisi2
+ 5609              	.LVL381:
+2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5610              		.loc 1 2668 11 view .LVU1922
+ 5611 0012 C9B2     		uxtb	r1, r1
+2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5612              		.loc 1 2668 6 view .LVU1923
+ 5613 0014 2029     		cmp	r1, #32
+ 5614 0016 40F0BD80 		bne	.L375
+ 5615 001a 0446     		mov	r4, r0
+ 5616 001c 9046     		mov	r8, r2
+ 5617 001e 9946     		mov	r9, r3
+2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5618              		.loc 1 2670 5 is_stmt 1 view .LVU1924
+2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5619              		.loc 1 2670 8 is_stmt 0 view .LVU1925
+ 5620 0020 0C9B     		ldr	r3, [sp, #48]
+ARM GAS  /tmp/ccVyGVF6.s 			page 263
+
+
+ 5621              	.LVL382:
+2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5622              		.loc 1 2670 8 view .LVU1926
+ 5623 0022 BAF1000F 		cmp	r10, #0
+ 5624 0026 18BF     		it	ne
+ 5625 0028 002B     		cmpne	r3, #0
+ 5626 002a 16D0     		beq	.L382
+2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5627              		.loc 1 2677 5 is_stmt 1 view .LVU1927
+2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5628              		.loc 1 2677 5 view .LVU1928
+ 5629 002c 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 5630 0030 012B     		cmp	r3, #1
+ 5631 0032 00F0B380 		beq	.L376
+2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5632              		.loc 1 2677 5 discriminator 2 view .LVU1929
+ 5633 0036 4FF0010B 		mov	fp, #1
+ 5634 003a 80F840B0 		strb	fp, [r0, #64]
+2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5635              		.loc 1 2677 5 discriminator 2 view .LVU1930
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5636              		.loc 1 2680 5 discriminator 2 view .LVU1931
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5637              		.loc 1 2680 17 is_stmt 0 discriminator 2 view .LVU1932
+ 5638 003e FFF7FEFF 		bl	HAL_GetTick
+ 5639              	.LVL383:
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5640              		.loc 1 2680 17 discriminator 2 view .LVU1933
+ 5641 0042 0646     		mov	r6, r0
+ 5642              	.LVL384:
+2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5643              		.loc 1 2682 5 is_stmt 1 discriminator 2 view .LVU1934
+2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5644              		.loc 1 2682 9 is_stmt 0 discriminator 2 view .LVU1935
+ 5645 0044 0090     		str	r0, [sp]
+ 5646 0046 1923     		movs	r3, #25
+ 5647 0048 5A46     		mov	r2, fp
+ 5648 004a 4FF40041 		mov	r1, #32768
+ 5649 004e 2046     		mov	r0, r4
+ 5650              	.LVL385:
+2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5651              		.loc 1 2682 9 discriminator 2 view .LVU1936
+ 5652 0050 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 5653              	.LVL386:
+2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5654              		.loc 1 2682 8 discriminator 2 view .LVU1937
+ 5655 0054 30B1     		cbz	r0, .L383
+2684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5656              		.loc 1 2684 14 view .LVU1938
+ 5657 0056 0120     		movs	r0, #1
+ 5658 0058 9DE0     		b	.L367
+ 5659              	.LVL387:
+ 5660              	.L382:
+2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5661              		.loc 1 2672 7 is_stmt 1 view .LVU1939
+2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 5662              		.loc 1 2672 23 is_stmt 0 view .LVU1940
+ARM GAS  /tmp/ccVyGVF6.s 			page 264
+
+
+ 5663 005a 4FF40073 		mov	r3, #512
+ 5664 005e 4364     		str	r3, [r0, #68]
+2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5665              		.loc 1 2673 7 is_stmt 1 view .LVU1941
+2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5666              		.loc 1 2673 15 is_stmt 0 view .LVU1942
+ 5667 0060 0120     		movs	r0, #1
+ 5668              	.LVL388:
+2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5669              		.loc 1 2673 15 view .LVU1943
+ 5670 0062 98E0     		b	.L367
+ 5671              	.LVL389:
+ 5672              	.L383:
+2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+ 5673              		.loc 1 2687 5 is_stmt 1 view .LVU1944
+2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MEM;
+ 5674              		.loc 1 2687 21 is_stmt 0 view .LVU1945
+ 5675 0064 2223     		movs	r3, #34
+ 5676 0066 84F84130 		strb	r3, [r4, #65]
+2688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 5677              		.loc 1 2688 5 is_stmt 1 view .LVU1946
+2688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 5678              		.loc 1 2688 21 is_stmt 0 view .LVU1947
+ 5679 006a 4023     		movs	r3, #64
+ 5680 006c 84F84230 		strb	r3, [r4, #66]
+2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5681              		.loc 1 2689 5 is_stmt 1 view .LVU1948
+2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5682              		.loc 1 2689 21 is_stmt 0 view .LVU1949
+ 5683 0070 0023     		movs	r3, #0
+ 5684 0072 6364     		str	r3, [r4, #68]
+2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 5685              		.loc 1 2692 5 is_stmt 1 view .LVU1950
+2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount = Size;
+ 5686              		.loc 1 2692 21 is_stmt 0 view .LVU1951
+ 5687 0074 0C9A     		ldr	r2, [sp, #48]
+ 5688 0076 6262     		str	r2, [r4, #36]
+2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 5689              		.loc 1 2693 5 is_stmt 1 view .LVU1952
+2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR   = NULL;
+ 5690              		.loc 1 2693 21 is_stmt 0 view .LVU1953
+ 5691 0078 A4F82AA0 		strh	r10, [r4, #42]	@ movhi
+2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5692              		.loc 1 2694 5 is_stmt 1 view .LVU1954
+2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5693              		.loc 1 2694 21 is_stmt 0 view .LVU1955
+ 5694 007c 6363     		str	r3, [r4, #52]
+2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5695              		.loc 1 2697 5 is_stmt 1 view .LVU1956
+2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5696              		.loc 1 2697 9 is_stmt 0 view .LVU1957
+ 5697 007e 0196     		str	r6, [sp, #4]
+ 5698 0080 0097     		str	r7, [sp]
+ 5699 0082 4B46     		mov	r3, r9
+ 5700 0084 4246     		mov	r2, r8
+ 5701 0086 2946     		mov	r1, r5
+ 5702 0088 2046     		mov	r0, r4
+ARM GAS  /tmp/ccVyGVF6.s 			page 265
+
+
+ 5703 008a FFF7FEFF 		bl	I2C_RequestMemoryRead
+ 5704              	.LVL390:
+2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5705              		.loc 1 2697 8 view .LVU1958
+ 5706 008e 70B9     		cbnz	r0, .L384
+2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5707              		.loc 1 2706 5 is_stmt 1 view .LVU1959
+2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5708              		.loc 1 2706 13 is_stmt 0 view .LVU1960
+ 5709 0090 638D     		ldrh	r3, [r4, #42]
+ 5710 0092 9BB2     		uxth	r3, r3
+2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5711              		.loc 1 2706 8 view .LVU1961
+ 5712 0094 FF2B     		cmp	r3, #255
+ 5713 0096 0FD9     		bls	.L370
+2708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 5714              		.loc 1 2708 7 is_stmt 1 view .LVU1962
+2708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ 5715              		.loc 1 2708 22 is_stmt 0 view .LVU1963
+ 5716 0098 0122     		movs	r2, #1
+ 5717 009a 2285     		strh	r2, [r4, #40]	@ movhi
+2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 5718              		.loc 1 2709 7 is_stmt 1 view .LVU1964
+ 5719 009c 434B     		ldr	r3, .L386
+ 5720 009e 0093     		str	r3, [sp]
+ 5721 00a0 4FF08073 		mov	r3, #16777216
+ 5722 00a4 2946     		mov	r1, r5
+ 5723 00a6 2046     		mov	r0, r4
+ 5724 00a8 FFF7FEFF 		bl	I2C_TransferConfig
+ 5725              	.LVL391:
+ 5726 00ac 21E0     		b	.L374
+ 5727              	.L384:
+2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 5728              		.loc 1 2700 7 view .LVU1965
+2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 5729              		.loc 1 2700 7 view .LVU1966
+ 5730 00ae 0023     		movs	r3, #0
+ 5731 00b0 84F84030 		strb	r3, [r4, #64]
+2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return HAL_ERROR;
+ 5732              		.loc 1 2700 7 view .LVU1967
+2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5733              		.loc 1 2701 7 view .LVU1968
+2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5734              		.loc 1 2701 14 is_stmt 0 view .LVU1969
+ 5735 00b4 5846     		mov	r0, fp
+ 5736 00b6 6EE0     		b	.L367
+ 5737              	.L370:
+2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5738              		.loc 1 2714 7 is_stmt 1 view .LVU1970
+2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5739              		.loc 1 2714 28 is_stmt 0 view .LVU1971
+ 5740 00b8 628D     		ldrh	r2, [r4, #42]
+ 5741 00ba 92B2     		uxth	r2, r2
+2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5742              		.loc 1 2714 22 view .LVU1972
+ 5743 00bc 2285     		strh	r2, [r4, #40]	@ movhi
+2715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ARM GAS  /tmp/ccVyGVF6.s 			page 266
+
+
+ 5744              		.loc 1 2715 7 is_stmt 1 view .LVU1973
+ 5745 00be 3B4B     		ldr	r3, .L386
+ 5746 00c0 0093     		str	r3, [sp]
+ 5747 00c2 4FF00073 		mov	r3, #33554432
+ 5748 00c6 D2B2     		uxtb	r2, r2
+ 5749 00c8 2946     		mov	r1, r5
+ 5750 00ca 2046     		mov	r0, r4
+ 5751 00cc FFF7FEFF 		bl	I2C_TransferConfig
+ 5752              	.LVL392:
+ 5753 00d0 0FE0     		b	.L374
+ 5754              	.L373:
+2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5755              		.loc 1 2752 11 view .LVU1974
+2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5756              		.loc 1 2752 32 is_stmt 0 view .LVU1975
+ 5757 00d2 628D     		ldrh	r2, [r4, #42]
+ 5758 00d4 92B2     		uxth	r2, r2
+2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ 5759              		.loc 1 2752 26 view .LVU1976
+ 5760 00d6 2285     		strh	r2, [r4, #40]	@ movhi
+2753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 5761              		.loc 1 2753 11 is_stmt 1 view .LVU1977
+ 5762 00d8 0023     		movs	r3, #0
+ 5763 00da 0093     		str	r3, [sp]
+ 5764 00dc 4FF00073 		mov	r3, #33554432
+ 5765 00e0 D2B2     		uxtb	r2, r2
+ 5766 00e2 2946     		mov	r1, r5
+ 5767 00e4 2046     		mov	r0, r4
+ 5768 00e6 FFF7FEFF 		bl	I2C_TransferConfig
+ 5769              	.LVL393:
+ 5770              	.L372:
+2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5771              		.loc 1 2757 13 view .LVU1978
+2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5772              		.loc 1 2757 18 is_stmt 0 view .LVU1979
+ 5773 00ea 638D     		ldrh	r3, [r4, #42]
+ 5774 00ec 9BB2     		uxth	r3, r3
+2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5775              		.loc 1 2757 5 view .LVU1980
+ 5776 00ee 002B     		cmp	r3, #0
+ 5777 00f0 34D0     		beq	.L385
+ 5778              	.L374:
+2719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5779              		.loc 1 2719 5 is_stmt 1 view .LVU1981
+2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5780              		.loc 1 2722 7 view .LVU1982
+2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5781              		.loc 1 2722 11 is_stmt 0 view .LVU1983
+ 5782 00f2 0096     		str	r6, [sp]
+ 5783 00f4 3B46     		mov	r3, r7
+ 5784 00f6 0022     		movs	r2, #0
+ 5785 00f8 0421     		movs	r1, #4
+ 5786 00fa 2046     		mov	r0, r4
+ 5787 00fc FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 5788              	.LVL394:
+2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5789              		.loc 1 2722 10 view .LVU1984
+ARM GAS  /tmp/ccVyGVF6.s 			page 267
+
+
+ 5790 0100 0028     		cmp	r0, #0
+ 5791 0102 4DD1     		bne	.L378
+2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5792              		.loc 1 2728 7 is_stmt 1 view .LVU1985
+2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5793              		.loc 1 2728 38 is_stmt 0 view .LVU1986
+ 5794 0104 2368     		ldr	r3, [r4]
+2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5795              		.loc 1 2728 48 view .LVU1987
+ 5796 0106 5A6A     		ldr	r2, [r3, #36]
+2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5797              		.loc 1 2728 12 view .LVU1988
+ 5798 0108 636A     		ldr	r3, [r4, #36]
+2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5799              		.loc 1 2728 23 view .LVU1989
+ 5800 010a 1A70     		strb	r2, [r3]
+2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5801              		.loc 1 2731 7 is_stmt 1 view .LVU1990
+2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5802              		.loc 1 2731 11 is_stmt 0 view .LVU1991
+ 5803 010c 636A     		ldr	r3, [r4, #36]
+2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5804              		.loc 1 2731 21 view .LVU1992
+ 5805 010e 0133     		adds	r3, r3, #1
+ 5806 0110 6362     		str	r3, [r4, #36]
+2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 5807              		.loc 1 2733 7 is_stmt 1 view .LVU1993
+2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 5808              		.loc 1 2733 11 is_stmt 0 view .LVU1994
+ 5809 0112 228D     		ldrh	r2, [r4, #40]
+2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 5810              		.loc 1 2733 21 view .LVU1995
+ 5811 0114 013A     		subs	r2, r2, #1
+ 5812 0116 92B2     		uxth	r2, r2
+ 5813 0118 2285     		strh	r2, [r4, #40]	@ movhi
+2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5814              		.loc 1 2734 7 is_stmt 1 view .LVU1996
+2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5815              		.loc 1 2734 11 is_stmt 0 view .LVU1997
+ 5816 011a 638D     		ldrh	r3, [r4, #42]
+ 5817 011c 9BB2     		uxth	r3, r3
+2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5818              		.loc 1 2734 22 view .LVU1998
+ 5819 011e 013B     		subs	r3, r3, #1
+ 5820 0120 9BB2     		uxth	r3, r3
+ 5821 0122 6385     		strh	r3, [r4, #42]	@ movhi
+2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5822              		.loc 1 2736 7 is_stmt 1 view .LVU1999
+2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5823              		.loc 1 2736 16 is_stmt 0 view .LVU2000
+ 5824 0124 638D     		ldrh	r3, [r4, #42]
+ 5825 0126 9BB2     		uxth	r3, r3
+2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 5826              		.loc 1 2736 10 view .LVU2001
+ 5827 0128 002B     		cmp	r3, #0
+ 5828 012a DED0     		beq	.L372
+2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ARM GAS  /tmp/ccVyGVF6.s 			page 268
+
+
+ 5829              		.loc 1 2736 35 discriminator 1 view .LVU2002
+ 5830 012c 002A     		cmp	r2, #0
+ 5831 012e DCD1     		bne	.L372
+2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5832              		.loc 1 2739 9 is_stmt 1 view .LVU2003
+2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5833              		.loc 1 2739 13 is_stmt 0 view .LVU2004
+ 5834 0130 0096     		str	r6, [sp]
+ 5835 0132 3B46     		mov	r3, r7
+ 5836 0134 8021     		movs	r1, #128
+ 5837 0136 2046     		mov	r0, r4
+ 5838 0138 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 5839              	.LVL395:
+2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5840              		.loc 1 2739 12 view .LVU2005
+ 5841 013c 90BB     		cbnz	r0, .L379
+2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5842              		.loc 1 2744 9 is_stmt 1 view .LVU2006
+2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5843              		.loc 1 2744 17 is_stmt 0 view .LVU2007
+ 5844 013e 638D     		ldrh	r3, [r4, #42]
+ 5845 0140 9BB2     		uxth	r3, r3
+2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 5846              		.loc 1 2744 12 view .LVU2008
+ 5847 0142 FF2B     		cmp	r3, #255
+ 5848 0144 C5D9     		bls	.L373
+2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+ 5849              		.loc 1 2746 11 is_stmt 1 view .LVU2009
+2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+ 5850              		.loc 1 2746 26 is_stmt 0 view .LVU2010
+ 5851 0146 0122     		movs	r2, #1
+ 5852 0148 2285     		strh	r2, [r4, #40]	@ movhi
+2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_NO_STARTSTOP);
+ 5853              		.loc 1 2747 11 is_stmt 1 view .LVU2011
+ 5854 014a 0023     		movs	r3, #0
+ 5855 014c 0093     		str	r3, [sp]
+ 5856 014e 4FF08073 		mov	r3, #16777216
+ 5857 0152 2946     		mov	r1, r5
+ 5858 0154 2046     		mov	r0, r4
+ 5859 0156 FFF7FEFF 		bl	I2C_TransferConfig
+ 5860              	.LVL396:
+ 5861 015a C6E7     		b	.L372
+ 5862              	.L385:
+2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5863              		.loc 1 2761 5 view .LVU2012
+2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5864              		.loc 1 2761 9 is_stmt 0 view .LVU2013
+ 5865 015c 3246     		mov	r2, r6
+ 5866 015e 3946     		mov	r1, r7
+ 5867 0160 2046     		mov	r0, r4
+ 5868 0162 FFF7FEFF 		bl	I2C_WaitOnSTOPFlagUntilTimeout
+ 5869              	.LVL397:
+2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5870              		.loc 1 2761 8 view .LVU2014
+ 5871 0166 F8B9     		cbnz	r0, .L380
+2767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5872              		.loc 1 2767 5 is_stmt 1 view .LVU2015
+ARM GAS  /tmp/ccVyGVF6.s 			page 269
+
+
+ 5873 0168 2368     		ldr	r3, [r4]
+ 5874 016a 2022     		movs	r2, #32
+ 5875 016c DA61     		str	r2, [r3, #28]
+2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5876              		.loc 1 2770 5 view .LVU2016
+ 5877 016e 2168     		ldr	r1, [r4]
+ 5878 0170 4B68     		ldr	r3, [r1, #4]
+ 5879 0172 23F0FF73 		bic	r3, r3, #33423360
+ 5880 0176 23F48B33 		bic	r3, r3, #71168
+ 5881 017a 23F4FF73 		bic	r3, r3, #510
+ 5882 017e 23F00103 		bic	r3, r3, #1
+ 5883 0182 4B60     		str	r3, [r1, #4]
+2772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 5884              		.loc 1 2772 5 view .LVU2017
+2772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode  = HAL_I2C_MODE_NONE;
+ 5885              		.loc 1 2772 17 is_stmt 0 view .LVU2018
+ 5886 0184 84F84120 		strb	r2, [r4, #65]
+2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5887              		.loc 1 2773 5 is_stmt 1 view .LVU2019
+2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5888              		.loc 1 2773 17 is_stmt 0 view .LVU2020
+ 5889 0188 0023     		movs	r3, #0
+ 5890 018a 84F84230 		strb	r3, [r4, #66]
+2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5891              		.loc 1 2776 5 is_stmt 1 view .LVU2021
+2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5892              		.loc 1 2776 5 view .LVU2022
+ 5893 018e 84F84030 		strb	r3, [r4, #64]
+2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5894              		.loc 1 2776 5 view .LVU2023
+2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 5895              		.loc 1 2778 5 view .LVU2024
+2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 5896              		.loc 1 2778 12 is_stmt 0 view .LVU2025
+ 5897 0192 00E0     		b	.L367
+ 5898              	.LVL398:
+ 5899              	.L375:
+2782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 5900              		.loc 1 2782 12 view .LVU2026
+ 5901 0194 0220     		movs	r0, #2
+ 5902              	.LVL399:
+ 5903              	.L367:
+2784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /**
+ 5904              		.loc 1 2784 1 view .LVU2027
+ 5905 0196 03B0     		add	sp, sp, #12
+ 5906              	.LCFI64:
+ 5907              		.cfi_remember_state
+ 5908              		.cfi_def_cfa_offset 36
+ 5909              		@ sp needed
+ 5910 0198 BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 5911              	.LVL400:
+ 5912              	.L376:
+ 5913              	.LCFI65:
+ 5914              		.cfi_restore_state
+2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5915              		.loc 1 2677 5 view .LVU2028
+ 5916 019c 0220     		movs	r0, #2
+ARM GAS  /tmp/ccVyGVF6.s 			page 270
+
+
+ 5917              	.LVL401:
+2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5918              		.loc 1 2677 5 view .LVU2029
+ 5919 019e FAE7     		b	.L367
+ 5920              	.LVL402:
+ 5921              	.L378:
+2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 5922              		.loc 1 2724 16 view .LVU2030
+ 5923 01a0 0120     		movs	r0, #1
+ 5924 01a2 F8E7     		b	.L367
+ 5925              	.L379:
+2741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 5926              		.loc 1 2741 18 view .LVU2031
+ 5927 01a4 0120     		movs	r0, #1
+ 5928 01a6 F6E7     		b	.L367
+ 5929              	.L380:
+2763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 5930              		.loc 1 2763 14 view .LVU2032
+ 5931 01a8 0120     		movs	r0, #1
+ 5932 01aa F4E7     		b	.L367
+ 5933              	.L387:
+ 5934              		.align	2
+ 5935              	.L386:
+ 5936 01ac 00240080 		.word	-2147474432
+ 5937              		.cfi_endproc
+ 5938              	.LFE158:
+ 5940              		.section	.text.HAL_I2C_Mem_Write_IT,"ax",%progbits
+ 5941              		.align	1
+ 5942              		.global	HAL_I2C_Mem_Write_IT
+ 5943              		.syntax unified
+ 5944              		.thumb
+ 5945              		.thumb_func
+ 5946              		.fpu fpv5-d16
+ 5948              	HAL_I2C_Mem_Write_IT:
+ 5949              	.LVL403:
+ 5950              	.LFB159:
+2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+ 5951              		.loc 1 2799 1 is_stmt 1 view -0
+ 5952              		.cfi_startproc
+ 5953              		@ args = 8, pretend = 0, frame = 0
+ 5954              		@ frame_needed = 0, uses_anonymous_args = 0
+2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+ 5955              		.loc 1 2799 1 is_stmt 0 view .LVU2034
+ 5956 0000 70B5     		push	{r4, r5, r6, lr}
+ 5957              	.LCFI66:
+ 5958              		.cfi_def_cfa_offset 16
+ 5959              		.cfi_offset 4, -16
+ 5960              		.cfi_offset 5, -12
+ 5961              		.cfi_offset 6, -8
+ 5962              		.cfi_offset 14, -4
+ 5963 0002 82B0     		sub	sp, sp, #8
+ 5964              	.LCFI67:
+ 5965              		.cfi_def_cfa_offset 24
+ 5966 0004 0446     		mov	r4, r0
+ 5967 0006 1D46     		mov	r5, r3
+ 5968 0008 BDF81C30 		ldrh	r3, [sp, #28]
+ 5969              	.LVL404:
+ARM GAS  /tmp/ccVyGVF6.s 			page 271
+
+
+2801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5970              		.loc 1 2801 3 is_stmt 1 view .LVU2035
+2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5971              		.loc 1 2803 3 view .LVU2036
+2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5972              		.loc 1 2803 11 is_stmt 0 view .LVU2037
+ 5973 000c 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 5974              	.LVL405:
+2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5975              		.loc 1 2803 11 view .LVU2038
+ 5976 0010 C0B2     		uxtb	r0, r0
+2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 5977              		.loc 1 2803 6 view .LVU2039
+ 5978 0012 2028     		cmp	r0, #32
+ 5979 0014 43D1     		bne	.L393
+2805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5980              		.loc 1 2805 5 is_stmt 1 view .LVU2040
+2805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5981              		.loc 1 2805 8 is_stmt 0 view .LVU2041
+ 5982 0016 0698     		ldr	r0, [sp, #24]
+ 5983 0018 002B     		cmp	r3, #0
+ 5984 001a 18BF     		it	ne
+ 5985 001c 0028     		cmpne	r0, #0
+ 5986 001e 33D0     		beq	.L397
+2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5987              		.loc 1 2811 5 is_stmt 1 view .LVU2042
+2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5988              		.loc 1 2811 9 is_stmt 0 view .LVU2043
+ 5989 0020 2068     		ldr	r0, [r4]
+ 5990 0022 8669     		ldr	r6, [r0, #24]
+2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 5991              		.loc 1 2811 8 view .LVU2044
+ 5992 0024 16F4004F 		tst	r6, #32768
+ 5993 0028 3CD1     		bne	.L394
+2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5994              		.loc 1 2817 5 is_stmt 1 view .LVU2045
+2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5995              		.loc 1 2817 5 view .LVU2046
+ 5996 002a 94F84060 		ldrb	r6, [r4, #64]	@ zero_extendqisi2
+ 5997 002e 012E     		cmp	r6, #1
+ 5998 0030 3AD0     		beq	.L395
+2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 5999              		.loc 1 2817 5 discriminator 2 view .LVU2047
+ 6000 0032 0126     		movs	r6, #1
+ 6001 0034 84F84060 		strb	r6, [r4, #64]
+2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6002              		.loc 1 2817 5 discriminator 2 view .LVU2048
+2819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6003              		.loc 1 2819 5 discriminator 2 view .LVU2049
+2819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6004              		.loc 1 2819 23 is_stmt 0 discriminator 2 view .LVU2050
+ 6005 0038 2126     		movs	r6, #33
+ 6006 003a 84F84160 		strb	r6, [r4, #65]
+2820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6007              		.loc 1 2820 5 is_stmt 1 discriminator 2 view .LVU2051
+2820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6008              		.loc 1 2820 23 is_stmt 0 discriminator 2 view .LVU2052
+ARM GAS  /tmp/ccVyGVF6.s 			page 272
+
+
+ 6009 003e 4026     		movs	r6, #64
+ 6010 0040 84F84260 		strb	r6, [r4, #66]
+2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6011              		.loc 1 2821 5 is_stmt 1 discriminator 2 view .LVU2053
+2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6012              		.loc 1 2821 23 is_stmt 0 discriminator 2 view .LVU2054
+ 6013 0044 0026     		movs	r6, #0
+ 6014 0046 6664     		str	r6, [r4, #68]
+2824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+ 6015              		.loc 1 2824 5 is_stmt 1 discriminator 2 view .LVU2055
+2824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->pBuffPtr    = pData;
+ 6016              		.loc 1 2824 23 is_stmt 0 discriminator 2 view .LVU2056
+ 6017 0048 2685     		strh	r6, [r4, #40]	@ movhi
+2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6018              		.loc 1 2825 5 is_stmt 1 discriminator 2 view .LVU2057
+2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6019              		.loc 1 2825 23 is_stmt 0 discriminator 2 view .LVU2058
+ 6020 004a 069E     		ldr	r6, [sp, #24]
+ 6021 004c 6662     		str	r6, [r4, #36]
+2826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6022              		.loc 1 2826 5 is_stmt 1 discriminator 2 view .LVU2059
+2826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6023              		.loc 1 2826 23 is_stmt 0 discriminator 2 view .LVU2060
+ 6024 004e 6385     		strh	r3, [r4, #42]	@ movhi
+2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_IT;
+ 6025              		.loc 1 2827 5 is_stmt 1 discriminator 2 view .LVU2061
+2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_IT;
+ 6026              		.loc 1 2827 23 is_stmt 0 discriminator 2 view .LVU2062
+ 6027 0050 164B     		ldr	r3, .L399
+ 6028 0052 E362     		str	r3, [r4, #44]
+2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+ 6029              		.loc 1 2828 5 is_stmt 1 discriminator 2 view .LVU2063
+2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+ 6030              		.loc 1 2828 23 is_stmt 0 discriminator 2 view .LVU2064
+ 6031 0054 164B     		ldr	r3, .L399+4
+ 6032 0056 6363     		str	r3, [r4, #52]
+2829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6033              		.loc 1 2829 5 is_stmt 1 discriminator 2 view .LVU2065
+2829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6034              		.loc 1 2829 23 is_stmt 0 discriminator 2 view .LVU2066
+ 6035 0058 E164     		str	r1, [r4, #76]
+2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6036              		.loc 1 2832 5 is_stmt 1 discriminator 2 view .LVU2067
+2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6037              		.loc 1 2832 8 is_stmt 0 discriminator 2 view .LVU2068
+ 6038 005a 012D     		cmp	r5, #1
+ 6039 005c 19D0     		beq	.L398
+2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6040              		.loc 1 2844 7 is_stmt 1 view .LVU2069
+2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6041              		.loc 1 2844 30 is_stmt 0 view .LVU2070
+ 6042 005e 130A     		lsrs	r3, r2, #8
+2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6043              		.loc 1 2844 28 view .LVU2071
+ 6044 0060 8362     		str	r3, [r0, #40]
+2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6045              		.loc 1 2847 7 is_stmt 1 view .LVU2072
+ARM GAS  /tmp/ccVyGVF6.s 			page 273
+
+
+2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6046              		.loc 1 2847 26 is_stmt 0 view .LVU2073
+ 6047 0062 D2B2     		uxtb	r2, r2
+ 6048              	.LVL406:
+2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6049              		.loc 1 2847 24 view .LVU2074
+ 6050 0064 2265     		str	r2, [r4, #80]
+ 6051              	.L392:
+2850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6052              		.loc 1 2850 5 is_stmt 1 view .LVU2075
+ 6053 0066 134B     		ldr	r3, .L399+8
+ 6054 0068 0093     		str	r3, [sp]
+ 6055 006a 4FF08073 		mov	r3, #16777216
+ 6056 006e EAB2     		uxtb	r2, r5
+ 6057 0070 2046     		mov	r0, r4
+ 6058 0072 FFF7FEFF 		bl	I2C_TransferConfig
+ 6059              	.LVL407:
+2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6060              		.loc 1 2853 5 view .LVU2076
+2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6061              		.loc 1 2853 5 view .LVU2077
+ 6062 0076 0025     		movs	r5, #0
+ 6063 0078 84F84050 		strb	r5, [r4, #64]
+2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6064              		.loc 1 2853 5 view .LVU2078
+2863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6065              		.loc 1 2863 5 view .LVU2079
+ 6066 007c 0121     		movs	r1, #1
+ 6067 007e 2046     		mov	r0, r4
+ 6068 0080 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 6069              	.LVL408:
+2865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6070              		.loc 1 2865 5 view .LVU2080
+2865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6071              		.loc 1 2865 12 is_stmt 0 view .LVU2081
+ 6072 0084 2846     		mov	r0, r5
+ 6073 0086 0BE0     		b	.L389
+ 6074              	.LVL409:
+ 6075              	.L397:
+2807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6076              		.loc 1 2807 7 is_stmt 1 view .LVU2082
+2807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6077              		.loc 1 2807 23 is_stmt 0 view .LVU2083
+ 6078 0088 4FF40073 		mov	r3, #512
+ 6079 008c 6364     		str	r3, [r4, #68]
+2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6080              		.loc 1 2808 7 is_stmt 1 view .LVU2084
+2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6081              		.loc 1 2808 15 is_stmt 0 view .LVU2085
+ 6082 008e 0120     		movs	r0, #1
+ 6083 0090 06E0     		b	.L389
+ 6084              	.L398:
+2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6085              		.loc 1 2835 7 is_stmt 1 view .LVU2086
+2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6086              		.loc 1 2835 30 is_stmt 0 view .LVU2087
+ 6087 0092 D2B2     		uxtb	r2, r2
+ARM GAS  /tmp/ccVyGVF6.s 			page 274
+
+
+ 6088              	.LVL410:
+2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6089              		.loc 1 2835 28 view .LVU2088
+ 6090 0094 8262     		str	r2, [r0, #40]
+2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6091              		.loc 1 2838 7 is_stmt 1 view .LVU2089
+2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6092              		.loc 1 2838 24 is_stmt 0 view .LVU2090
+ 6093 0096 4FF0FF33 		mov	r3, #-1
+ 6094 009a 2365     		str	r3, [r4, #80]
+ 6095 009c E3E7     		b	.L392
+ 6096              	.LVL411:
+ 6097              	.L393:
+2869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6098              		.loc 1 2869 12 view .LVU2091
+ 6099 009e 0220     		movs	r0, #2
+ 6100              	.LVL412:
+ 6101              	.L389:
+2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6102              		.loc 1 2871 1 view .LVU2092
+ 6103 00a0 02B0     		add	sp, sp, #8
+ 6104              	.LCFI68:
+ 6105              		.cfi_remember_state
+ 6106              		.cfi_def_cfa_offset 16
+ 6107              		@ sp needed
+ 6108 00a2 70BD     		pop	{r4, r5, r6, pc}
+ 6109              	.LVL413:
+ 6110              	.L394:
+ 6111              	.LCFI69:
+ 6112              		.cfi_restore_state
+2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6113              		.loc 1 2813 14 view .LVU2093
+ 6114 00a4 0220     		movs	r0, #2
+ 6115 00a6 FBE7     		b	.L389
+ 6116              	.L395:
+2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6117              		.loc 1 2817 5 view .LVU2094
+ 6118 00a8 0220     		movs	r0, #2
+ 6119 00aa F9E7     		b	.L389
+ 6120              	.L400:
+ 6121              		.align	2
+ 6122              	.L399:
+ 6123 00ac 0000FFFF 		.word	-65536
+ 6124 00b0 00000000 		.word	I2C_Mem_ISR_IT
+ 6125 00b4 00200080 		.word	-2147475456
+ 6126              		.cfi_endproc
+ 6127              	.LFE159:
+ 6129              		.section	.text.HAL_I2C_Mem_Read_IT,"ax",%progbits
+ 6130              		.align	1
+ 6131              		.global	HAL_I2C_Mem_Read_IT
+ 6132              		.syntax unified
+ 6133              		.thumb
+ 6134              		.thumb_func
+ 6135              		.fpu fpv5-d16
+ 6137              	HAL_I2C_Mem_Read_IT:
+ 6138              	.LVL414:
+ 6139              	.LFB160:
+ARM GAS  /tmp/ccVyGVF6.s 			page 275
+
+
+2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+ 6140              		.loc 1 2887 1 is_stmt 1 view -0
+ 6141              		.cfi_startproc
+ 6142              		@ args = 8, pretend = 0, frame = 0
+ 6143              		@ frame_needed = 0, uses_anonymous_args = 0
+2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Check the parameters */
+ 6144              		.loc 1 2887 1 is_stmt 0 view .LVU2096
+ 6145 0000 70B5     		push	{r4, r5, r6, lr}
+ 6146              	.LCFI70:
+ 6147              		.cfi_def_cfa_offset 16
+ 6148              		.cfi_offset 4, -16
+ 6149              		.cfi_offset 5, -12
+ 6150              		.cfi_offset 6, -8
+ 6151              		.cfi_offset 14, -4
+ 6152 0002 82B0     		sub	sp, sp, #8
+ 6153              	.LCFI71:
+ 6154              		.cfi_def_cfa_offset 24
+ 6155 0004 0446     		mov	r4, r0
+ 6156 0006 1D46     		mov	r5, r3
+ 6157 0008 BDF81C30 		ldrh	r3, [sp, #28]
+ 6158              	.LVL415:
+2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6159              		.loc 1 2889 3 is_stmt 1 view .LVU2097
+2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6160              		.loc 1 2891 3 view .LVU2098
+2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6161              		.loc 1 2891 11 is_stmt 0 view .LVU2099
+ 6162 000c 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 6163              	.LVL416:
+2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6164              		.loc 1 2891 11 view .LVU2100
+ 6165 0010 C0B2     		uxtb	r0, r0
+2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6166              		.loc 1 2891 6 view .LVU2101
+ 6167 0012 2028     		cmp	r0, #32
+ 6168 0014 41D1     		bne	.L406
+2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6169              		.loc 1 2893 5 is_stmt 1 view .LVU2102
+2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6170              		.loc 1 2893 8 is_stmt 0 view .LVU2103
+ 6171 0016 0698     		ldr	r0, [sp, #24]
+ 6172 0018 002B     		cmp	r3, #0
+ 6173 001a 18BF     		it	ne
+ 6174 001c 0028     		cmpne	r0, #0
+ 6175 001e 31D0     		beq	.L410
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6176              		.loc 1 2899 5 is_stmt 1 view .LVU2104
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6177              		.loc 1 2899 9 is_stmt 0 view .LVU2105
+ 6178 0020 2068     		ldr	r0, [r4]
+ 6179 0022 8669     		ldr	r6, [r0, #24]
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6180              		.loc 1 2899 8 view .LVU2106
+ 6181 0024 16F4004F 		tst	r6, #32768
+ 6182 0028 3AD1     		bne	.L407
+2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6183              		.loc 1 2905 5 is_stmt 1 view .LVU2107
+ARM GAS  /tmp/ccVyGVF6.s 			page 276
+
+
+2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6184              		.loc 1 2905 5 view .LVU2108
+ 6185 002a 94F84060 		ldrb	r6, [r4, #64]	@ zero_extendqisi2
+ 6186 002e 012E     		cmp	r6, #1
+ 6187 0030 38D0     		beq	.L408
+2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6188              		.loc 1 2905 5 discriminator 2 view .LVU2109
+ 6189 0032 0126     		movs	r6, #1
+ 6190 0034 84F84060 		strb	r6, [r4, #64]
+2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6191              		.loc 1 2905 5 discriminator 2 view .LVU2110
+2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6192              		.loc 1 2907 5 discriminator 2 view .LVU2111
+2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6193              		.loc 1 2907 23 is_stmt 0 discriminator 2 view .LVU2112
+ 6194 0038 2226     		movs	r6, #34
+ 6195 003a 84F84160 		strb	r6, [r4, #65]
+2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6196              		.loc 1 2908 5 is_stmt 1 discriminator 2 view .LVU2113
+2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6197              		.loc 1 2908 23 is_stmt 0 discriminator 2 view .LVU2114
+ 6198 003e 4026     		movs	r6, #64
+ 6199 0040 84F84260 		strb	r6, [r4, #66]
+2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6200              		.loc 1 2909 5 is_stmt 1 discriminator 2 view .LVU2115
+2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6201              		.loc 1 2909 23 is_stmt 0 discriminator 2 view .LVU2116
+ 6202 0044 0026     		movs	r6, #0
+ 6203 0046 6664     		str	r6, [r4, #68]
+2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6204              		.loc 1 2912 5 is_stmt 1 discriminator 2 view .LVU2117
+2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6205              		.loc 1 2912 23 is_stmt 0 discriminator 2 view .LVU2118
+ 6206 0048 069E     		ldr	r6, [sp, #24]
+ 6207 004a 6662     		str	r6, [r4, #36]
+2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6208              		.loc 1 2913 5 is_stmt 1 discriminator 2 view .LVU2119
+2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6209              		.loc 1 2913 23 is_stmt 0 discriminator 2 view .LVU2120
+ 6210 004c 6385     		strh	r3, [r4, #42]	@ movhi
+2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_IT;
+ 6211              		.loc 1 2914 5 is_stmt 1 discriminator 2 view .LVU2121
+2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_IT;
+ 6212              		.loc 1 2914 23 is_stmt 0 discriminator 2 view .LVU2122
+ 6213 004e 164B     		ldr	r3, .L412
+ 6214 0050 E362     		str	r3, [r4, #44]
+2915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+ 6215              		.loc 1 2915 5 is_stmt 1 discriminator 2 view .LVU2123
+2915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+ 6216              		.loc 1 2915 23 is_stmt 0 discriminator 2 view .LVU2124
+ 6217 0052 164B     		ldr	r3, .L412+4
+ 6218 0054 6363     		str	r3, [r4, #52]
+2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6219              		.loc 1 2916 5 is_stmt 1 discriminator 2 view .LVU2125
+2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6220              		.loc 1 2916 23 is_stmt 0 discriminator 2 view .LVU2126
+ 6221 0056 E164     		str	r1, [r4, #76]
+ARM GAS  /tmp/ccVyGVF6.s 			page 277
+
+
+2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6222              		.loc 1 2919 5 is_stmt 1 discriminator 2 view .LVU2127
+2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6223              		.loc 1 2919 8 is_stmt 0 discriminator 2 view .LVU2128
+ 6224 0058 012D     		cmp	r5, #1
+ 6225 005a 18D0     		beq	.L411
+2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6226              		.loc 1 2931 7 is_stmt 1 view .LVU2129
+2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6227              		.loc 1 2931 30 is_stmt 0 view .LVU2130
+ 6228 005c 130A     		lsrs	r3, r2, #8
+2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6229              		.loc 1 2931 28 view .LVU2131
+ 6230 005e 8362     		str	r3, [r0, #40]
+2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6231              		.loc 1 2934 7 is_stmt 1 view .LVU2132
+2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6232              		.loc 1 2934 26 is_stmt 0 view .LVU2133
+ 6233 0060 D2B2     		uxtb	r2, r2
+ 6234              	.LVL417:
+2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6235              		.loc 1 2934 24 view .LVU2134
+ 6236 0062 2265     		str	r2, [r4, #80]
+ 6237              	.L405:
+2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6238              		.loc 1 2937 5 is_stmt 1 view .LVU2135
+ 6239 0064 124B     		ldr	r3, .L412+8
+ 6240 0066 0093     		str	r3, [sp]
+ 6241 0068 0023     		movs	r3, #0
+ 6242 006a EAB2     		uxtb	r2, r5
+ 6243 006c 2046     		mov	r0, r4
+ 6244 006e FFF7FEFF 		bl	I2C_TransferConfig
+ 6245              	.LVL418:
+2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6246              		.loc 1 2940 5 view .LVU2136
+2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6247              		.loc 1 2940 5 view .LVU2137
+ 6248 0072 0025     		movs	r5, #0
+ 6249 0074 84F84050 		strb	r5, [r4, #64]
+2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6250              		.loc 1 2940 5 view .LVU2138
+2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6251              		.loc 1 2950 5 view .LVU2139
+ 6252 0078 0121     		movs	r1, #1
+ 6253 007a 2046     		mov	r0, r4
+ 6254 007c FFF7FEFF 		bl	I2C_Enable_IRQ
+ 6255              	.LVL419:
+2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6256              		.loc 1 2952 5 view .LVU2140
+2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6257              		.loc 1 2952 12 is_stmt 0 view .LVU2141
+ 6258 0080 2846     		mov	r0, r5
+ 6259 0082 0BE0     		b	.L402
+ 6260              	.LVL420:
+ 6261              	.L410:
+2895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6262              		.loc 1 2895 7 is_stmt 1 view .LVU2142
+ARM GAS  /tmp/ccVyGVF6.s 			page 278
+
+
+2895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6263              		.loc 1 2895 23 is_stmt 0 view .LVU2143
+ 6264 0084 4FF40073 		mov	r3, #512
+ 6265 0088 6364     		str	r3, [r4, #68]
+2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6266              		.loc 1 2896 7 is_stmt 1 view .LVU2144
+2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6267              		.loc 1 2896 15 is_stmt 0 view .LVU2145
+ 6268 008a 0120     		movs	r0, #1
+ 6269 008c 06E0     		b	.L402
+ 6270              	.L411:
+2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6271              		.loc 1 2922 7 is_stmt 1 view .LVU2146
+2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6272              		.loc 1 2922 30 is_stmt 0 view .LVU2147
+ 6273 008e D2B2     		uxtb	r2, r2
+ 6274              	.LVL421:
+2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6275              		.loc 1 2922 28 view .LVU2148
+ 6276 0090 8262     		str	r2, [r0, #40]
+2925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6277              		.loc 1 2925 7 is_stmt 1 view .LVU2149
+2925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6278              		.loc 1 2925 24 is_stmt 0 view .LVU2150
+ 6279 0092 4FF0FF33 		mov	r3, #-1
+ 6280 0096 2365     		str	r3, [r4, #80]
+ 6281 0098 E4E7     		b	.L405
+ 6282              	.LVL422:
+ 6283              	.L406:
+2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6284              		.loc 1 2956 12 view .LVU2151
+ 6285 009a 0220     		movs	r0, #2
+ 6286              	.LVL423:
+ 6287              	.L402:
+2958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6288              		.loc 1 2958 1 view .LVU2152
+ 6289 009c 02B0     		add	sp, sp, #8
+ 6290              	.LCFI72:
+ 6291              		.cfi_remember_state
+ 6292              		.cfi_def_cfa_offset 16
+ 6293              		@ sp needed
+ 6294 009e 70BD     		pop	{r4, r5, r6, pc}
+ 6295              	.LVL424:
+ 6296              	.L407:
+ 6297              	.LCFI73:
+ 6298              		.cfi_restore_state
+2901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6299              		.loc 1 2901 14 view .LVU2153
+ 6300 00a0 0220     		movs	r0, #2
+ 6301 00a2 FBE7     		b	.L402
+ 6302              	.L408:
+2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6303              		.loc 1 2905 5 view .LVU2154
+ 6304 00a4 0220     		movs	r0, #2
+ 6305 00a6 F9E7     		b	.L402
+ 6306              	.L413:
+ 6307              		.align	2
+ARM GAS  /tmp/ccVyGVF6.s 			page 279
+
+
+ 6308              	.L412:
+ 6309 00a8 0000FFFF 		.word	-65536
+ 6310 00ac 00000000 		.word	I2C_Mem_ISR_IT
+ 6311 00b0 00200080 		.word	-2147475456
+ 6312              		.cfi_endproc
+ 6313              	.LFE160:
+ 6315              		.section	.text.HAL_I2C_Mem_Write_DMA,"ax",%progbits
+ 6316              		.align	1
+ 6317              		.global	HAL_I2C_Mem_Write_DMA
+ 6318              		.syntax unified
+ 6319              		.thumb
+ 6320              		.thumb_func
+ 6321              		.fpu fpv5-d16
+ 6323              	HAL_I2C_Mem_Write_DMA:
+ 6324              	.LVL425:
+ 6325              	.LFB161:
+2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 6326              		.loc 1 2974 1 is_stmt 1 view -0
+ 6327              		.cfi_startproc
+ 6328              		@ args = 8, pretend = 0, frame = 0
+ 6329              		@ frame_needed = 0, uses_anonymous_args = 0
+2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 6330              		.loc 1 2974 1 is_stmt 0 view .LVU2156
+ 6331 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 6332              	.LCFI74:
+ 6333              		.cfi_def_cfa_offset 20
+ 6334              		.cfi_offset 4, -20
+ 6335              		.cfi_offset 5, -16
+ 6336              		.cfi_offset 6, -12
+ 6337              		.cfi_offset 7, -8
+ 6338              		.cfi_offset 14, -4
+ 6339 0002 83B0     		sub	sp, sp, #12
+ 6340              	.LCFI75:
+ 6341              		.cfi_def_cfa_offset 32
+ 6342 0004 0446     		mov	r4, r0
+ 6343 0006 0E46     		mov	r6, r1
+ 6344 0008 1F46     		mov	r7, r3
+ 6345 000a 0899     		ldr	r1, [sp, #32]
+ 6346              	.LVL426:
+2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 6347              		.loc 1 2974 1 view .LVU2157
+ 6348 000c BDF82430 		ldrh	r3, [sp, #36]
+ 6349              	.LVL427:
+2975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6350              		.loc 1 2975 3 is_stmt 1 view .LVU2158
+2978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6351              		.loc 1 2978 3 view .LVU2159
+2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6352              		.loc 1 2980 3 view .LVU2160
+2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6353              		.loc 1 2980 11 is_stmt 0 view .LVU2161
+ 6354 0010 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 6355              	.LVL428:
+2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6356              		.loc 1 2980 11 view .LVU2162
+ 6357 0014 C0B2     		uxtb	r0, r0
+2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccVyGVF6.s 			page 280
+
+
+ 6358              		.loc 1 2980 6 view .LVU2163
+ 6359 0016 2028     		cmp	r0, #32
+ 6360 0018 7AD1     		bne	.L424
+2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6361              		.loc 1 2982 5 is_stmt 1 view .LVU2164
+2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6362              		.loc 1 2982 8 is_stmt 0 view .LVU2165
+ 6363 001a 002B     		cmp	r3, #0
+ 6364 001c 18BF     		it	ne
+ 6365 001e 0029     		cmpne	r1, #0
+ 6366 0020 49D0     		beq	.L429
+2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6367              		.loc 1 2988 5 is_stmt 1 view .LVU2166
+2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6368              		.loc 1 2988 9 is_stmt 0 view .LVU2167
+ 6369 0022 2068     		ldr	r0, [r4]
+ 6370 0024 8569     		ldr	r5, [r0, #24]
+2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6371              		.loc 1 2988 8 view .LVU2168
+ 6372 0026 15F4004F 		tst	r5, #32768
+ 6373 002a 75D1     		bne	.L425
+2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6374              		.loc 1 2994 5 is_stmt 1 view .LVU2169
+2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6375              		.loc 1 2994 5 view .LVU2170
+ 6376 002c 94F84050 		ldrb	r5, [r4, #64]	@ zero_extendqisi2
+ 6377 0030 012D     		cmp	r5, #1
+ 6378 0032 73D0     		beq	.L426
+2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6379              		.loc 1 2994 5 discriminator 2 view .LVU2171
+ 6380 0034 0125     		movs	r5, #1
+ 6381 0036 84F84050 		strb	r5, [r4, #64]
+2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6382              		.loc 1 2994 5 discriminator 2 view .LVU2172
+2996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6383              		.loc 1 2996 5 discriminator 2 view .LVU2173
+2996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6384              		.loc 1 2996 23 is_stmt 0 discriminator 2 view .LVU2174
+ 6385 003a 2125     		movs	r5, #33
+ 6386 003c 84F84150 		strb	r5, [r4, #65]
+2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6387              		.loc 1 2997 5 is_stmt 1 discriminator 2 view .LVU2175
+2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6388              		.loc 1 2997 23 is_stmt 0 discriminator 2 view .LVU2176
+ 6389 0040 4025     		movs	r5, #64
+ 6390 0042 84F84250 		strb	r5, [r4, #66]
+2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6391              		.loc 1 2998 5 is_stmt 1 discriminator 2 view .LVU2177
+2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6392              		.loc 1 2998 23 is_stmt 0 discriminator 2 view .LVU2178
+ 6393 0046 0025     		movs	r5, #0
+ 6394 0048 6564     		str	r5, [r4, #68]
+3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6395              		.loc 1 3001 5 is_stmt 1 discriminator 2 view .LVU2179
+3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6396              		.loc 1 3001 23 is_stmt 0 discriminator 2 view .LVU2180
+ 6397 004a 6162     		str	r1, [r4, #36]
+ARM GAS  /tmp/ccVyGVF6.s 			page 281
+
+
+3002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6398              		.loc 1 3002 5 is_stmt 1 discriminator 2 view .LVU2181
+3002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6399              		.loc 1 3002 23 is_stmt 0 discriminator 2 view .LVU2182
+ 6400 004c 6385     		strh	r3, [r4, #42]	@ movhi
+3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_DMA;
+ 6401              		.loc 1 3003 5 is_stmt 1 discriminator 2 view .LVU2183
+3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_DMA;
+ 6402              		.loc 1 3003 23 is_stmt 0 discriminator 2 view .LVU2184
+ 6403 004e 344B     		ldr	r3, .L432
+ 6404 0050 E362     		str	r3, [r4, #44]
+3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+ 6405              		.loc 1 3004 5 is_stmt 1 discriminator 2 view .LVU2185
+3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+ 6406              		.loc 1 3004 23 is_stmt 0 discriminator 2 view .LVU2186
+ 6407 0052 344B     		ldr	r3, .L432+4
+ 6408 0054 6363     		str	r3, [r4, #52]
+3005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6409              		.loc 1 3005 5 is_stmt 1 discriminator 2 view .LVU2187
+3005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6410              		.loc 1 3005 23 is_stmt 0 discriminator 2 view .LVU2188
+ 6411 0056 E664     		str	r6, [r4, #76]
+3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6412              		.loc 1 3007 5 is_stmt 1 discriminator 2 view .LVU2189
+3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6413              		.loc 1 3007 13 is_stmt 0 discriminator 2 view .LVU2190
+ 6414 0058 638D     		ldrh	r3, [r4, #42]
+ 6415 005a 9BB2     		uxth	r3, r3
+3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6416              		.loc 1 3007 8 discriminator 2 view .LVU2191
+ 6417 005c FF2B     		cmp	r3, #255
+ 6418 005e 2FD9     		bls	.L417
+3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6419              		.loc 1 3009 7 is_stmt 1 view .LVU2192
+3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6420              		.loc 1 3009 22 is_stmt 0 view .LVU2193
+ 6421 0060 FF23     		movs	r3, #255
+ 6422 0062 2385     		strh	r3, [r4, #40]	@ movhi
+ 6423              	.L418:
+3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6424              		.loc 1 3017 5 is_stmt 1 view .LVU2194
+3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6425              		.loc 1 3017 8 is_stmt 0 view .LVU2195
+ 6426 0064 012F     		cmp	r7, #1
+ 6427 0066 2ED0     		beq	.L430
+3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6428              		.loc 1 3029 7 is_stmt 1 view .LVU2196
+3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6429              		.loc 1 3029 30 is_stmt 0 view .LVU2197
+ 6430 0068 130A     		lsrs	r3, r2, #8
+3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6431              		.loc 1 3029 28 view .LVU2198
+ 6432 006a 8362     		str	r3, [r0, #40]
+3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6433              		.loc 1 3032 7 is_stmt 1 view .LVU2199
+3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6434              		.loc 1 3032 26 is_stmt 0 view .LVU2200
+ARM GAS  /tmp/ccVyGVF6.s 			page 282
+
+
+ 6435 006c D2B2     		uxtb	r2, r2
+ 6436              	.LVL429:
+3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6437              		.loc 1 3032 24 view .LVU2201
+ 6438 006e 2265     		str	r2, [r4, #80]
+ 6439              	.L420:
+3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6440              		.loc 1 3035 5 is_stmt 1 view .LVU2202
+3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6441              		.loc 1 3035 13 is_stmt 0 view .LVU2203
+ 6442 0070 A36B     		ldr	r3, [r4, #56]
+3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6443              		.loc 1 3035 8 view .LVU2204
+ 6444 0072 002B     		cmp	r3, #0
+ 6445 0074 2DD0     		beq	.L421
+3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6446              		.loc 1 3038 7 is_stmt 1 view .LVU2205
+3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6447              		.loc 1 3038 38 is_stmt 0 view .LVU2206
+ 6448 0076 2C4A     		ldr	r2, .L432+8
+ 6449 0078 DA63     		str	r2, [r3, #60]
+3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6450              		.loc 1 3041 7 is_stmt 1 view .LVU2207
+3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6451              		.loc 1 3041 11 is_stmt 0 view .LVU2208
+ 6452 007a A36B     		ldr	r3, [r4, #56]
+3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6453              		.loc 1 3041 39 view .LVU2209
+ 6454 007c 2B4A     		ldr	r2, .L432+12
+ 6455 007e DA64     		str	r2, [r3, #76]
+3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 6456              		.loc 1 3044 7 is_stmt 1 view .LVU2210
+3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 6457              		.loc 1 3044 11 is_stmt 0 view .LVU2211
+ 6458 0080 A26B     		ldr	r2, [r4, #56]
+3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 6459              		.loc 1 3044 42 view .LVU2212
+ 6460 0082 0023     		movs	r3, #0
+ 6461 0084 1364     		str	r3, [r2, #64]
+3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6462              		.loc 1 3045 7 is_stmt 1 view .LVU2213
+3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6463              		.loc 1 3045 11 is_stmt 0 view .LVU2214
+ 6464 0086 A26B     		ldr	r2, [r4, #56]
+3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6465              		.loc 1 3045 39 view .LVU2215
+ 6466 0088 1365     		str	r3, [r2, #80]
+3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6467              		.loc 1 3048 7 is_stmt 1 view .LVU2216
+3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6468              		.loc 1 3048 86 is_stmt 0 view .LVU2217
+ 6469 008a 2268     		ldr	r2, [r4]
+3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6470              		.loc 1 3048 23 view .LVU2218
+ 6471 008c 238D     		ldrh	r3, [r4, #40]
+ 6472 008e 2832     		adds	r2, r2, #40
+ 6473 0090 A06B     		ldr	r0, [r4, #56]
+ARM GAS  /tmp/ccVyGVF6.s 			page 283
+
+
+ 6474 0092 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 6475              	.LVL430:
+3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6476              		.loc 1 3066 5 is_stmt 1 view .LVU2219
+3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6477              		.loc 1 3066 8 is_stmt 0 view .LVU2220
+ 6478 0096 0546     		mov	r5, r0
+ 6479 0098 48B3     		cbz	r0, .L431
+3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6480              		.loc 1 3086 7 is_stmt 1 view .LVU2221
+3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6481              		.loc 1 3086 23 is_stmt 0 view .LVU2222
+ 6482 009a 2023     		movs	r3, #32
+ 6483 009c 84F84130 		strb	r3, [r4, #65]
+3087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6484              		.loc 1 3087 7 is_stmt 1 view .LVU2223
+3087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6485              		.loc 1 3087 23 is_stmt 0 view .LVU2224
+ 6486 00a0 0022     		movs	r2, #0
+ 6487 00a2 84F84220 		strb	r2, [r4, #66]
+3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6488              		.loc 1 3090 7 is_stmt 1 view .LVU2225
+3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6489              		.loc 1 3090 23 is_stmt 0 view .LVU2226
+ 6490 00a6 636C     		ldr	r3, [r4, #68]
+ 6491 00a8 43F01003 		orr	r3, r3, #16
+ 6492 00ac 6364     		str	r3, [r4, #68]
+3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6493              		.loc 1 3093 7 is_stmt 1 view .LVU2227
+3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6494              		.loc 1 3093 7 view .LVU2228
+ 6495 00ae 84F84020 		strb	r2, [r4, #64]
+3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6496              		.loc 1 3093 7 view .LVU2229
+3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6497              		.loc 1 3095 7 view .LVU2230
+3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6498              		.loc 1 3095 14 is_stmt 0 view .LVU2231
+ 6499 00b2 0125     		movs	r5, #1
+ 6500 00b4 2DE0     		b	.L415
+ 6501              	.LVL431:
+ 6502              	.L429:
+2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6503              		.loc 1 2984 7 is_stmt 1 view .LVU2232
+2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6504              		.loc 1 2984 23 is_stmt 0 view .LVU2233
+ 6505 00b6 4FF40073 		mov	r3, #512
+ 6506 00ba 6364     		str	r3, [r4, #68]
+2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6507              		.loc 1 2985 7 is_stmt 1 view .LVU2234
+2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6508              		.loc 1 2985 15 is_stmt 0 view .LVU2235
+ 6509 00bc 0125     		movs	r5, #1
+ 6510 00be 28E0     		b	.L415
+ 6511              	.L417:
+3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6512              		.loc 1 3013 7 is_stmt 1 view .LVU2236
+ARM GAS  /tmp/ccVyGVF6.s 			page 284
+
+
+3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6513              		.loc 1 3013 28 is_stmt 0 view .LVU2237
+ 6514 00c0 638D     		ldrh	r3, [r4, #42]
+3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6515              		.loc 1 3013 22 view .LVU2238
+ 6516 00c2 2385     		strh	r3, [r4, #40]	@ movhi
+ 6517 00c4 CEE7     		b	.L418
+ 6518              	.L430:
+3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6519              		.loc 1 3020 7 is_stmt 1 view .LVU2239
+3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6520              		.loc 1 3020 30 is_stmt 0 view .LVU2240
+ 6521 00c6 D2B2     		uxtb	r2, r2
+ 6522              	.LVL432:
+3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6523              		.loc 1 3020 28 view .LVU2241
+ 6524 00c8 8262     		str	r2, [r0, #40]
+3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6525              		.loc 1 3023 7 is_stmt 1 view .LVU2242
+3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6526              		.loc 1 3023 24 is_stmt 0 view .LVU2243
+ 6527 00ca 4FF0FF33 		mov	r3, #-1
+ 6528 00ce 2365     		str	r3, [r4, #80]
+ 6529 00d0 CEE7     		b	.L420
+ 6530              	.L421:
+3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6531              		.loc 1 3054 7 is_stmt 1 view .LVU2244
+3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6532              		.loc 1 3054 23 is_stmt 0 view .LVU2245
+ 6533 00d2 2023     		movs	r3, #32
+ 6534 00d4 84F84130 		strb	r3, [r4, #65]
+3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6535              		.loc 1 3055 7 is_stmt 1 view .LVU2246
+3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6536              		.loc 1 3055 23 is_stmt 0 view .LVU2247
+ 6537 00d8 0022     		movs	r2, #0
+ 6538 00da 84F84220 		strb	r2, [r4, #66]
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6539              		.loc 1 3058 7 is_stmt 1 view .LVU2248
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6540              		.loc 1 3058 23 is_stmt 0 view .LVU2249
+ 6541 00de 636C     		ldr	r3, [r4, #68]
+ 6542 00e0 43F08003 		orr	r3, r3, #128
+ 6543 00e4 6364     		str	r3, [r4, #68]
+3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6544              		.loc 1 3061 7 is_stmt 1 view .LVU2250
+3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6545              		.loc 1 3061 7 view .LVU2251
+ 6546 00e6 84F84020 		strb	r2, [r4, #64]
+3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6547              		.loc 1 3061 7 view .LVU2252
+3063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6548              		.loc 1 3063 7 view .LVU2253
+3063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6549              		.loc 1 3063 14 is_stmt 0 view .LVU2254
+ 6550 00ea 0125     		movs	r5, #1
+ 6551 00ec 11E0     		b	.L415
+ARM GAS  /tmp/ccVyGVF6.s 			page 285
+
+
+ 6552              	.LVL433:
+ 6553              	.L431:
+3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6554              		.loc 1 3069 7 is_stmt 1 view .LVU2255
+ 6555 00ee 104B     		ldr	r3, .L432+16
+ 6556 00f0 0093     		str	r3, [sp]
+ 6557 00f2 4FF08073 		mov	r3, #16777216
+ 6558 00f6 FAB2     		uxtb	r2, r7
+ 6559 00f8 3146     		mov	r1, r6
+ 6560 00fa 2046     		mov	r0, r4
+ 6561              	.LVL434:
+3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6562              		.loc 1 3069 7 is_stmt 0 view .LVU2256
+ 6563 00fc FFF7FEFF 		bl	I2C_TransferConfig
+ 6564              	.LVL435:
+3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6565              		.loc 1 3072 7 is_stmt 1 view .LVU2257
+3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6566              		.loc 1 3072 7 view .LVU2258
+ 6567 0100 0023     		movs	r3, #0
+ 6568 0102 84F84030 		strb	r3, [r4, #64]
+3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6569              		.loc 1 3072 7 view .LVU2259
+3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6570              		.loc 1 3081 7 view .LVU2260
+ 6571 0106 0121     		movs	r1, #1
+ 6572 0108 2046     		mov	r0, r4
+ 6573 010a FFF7FEFF 		bl	I2C_Enable_IRQ
+ 6574              	.LVL436:
+3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6575              		.loc 1 3098 5 view .LVU2261
+3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6576              		.loc 1 3098 12 is_stmt 0 view .LVU2262
+ 6577 010e 00E0     		b	.L415
+ 6578              	.LVL437:
+ 6579              	.L424:
+3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6580              		.loc 1 3102 12 view .LVU2263
+ 6581 0110 0225     		movs	r5, #2
+ 6582              	.LVL438:
+ 6583              	.L415:
+3104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6584              		.loc 1 3104 1 view .LVU2264
+ 6585 0112 2846     		mov	r0, r5
+ 6586 0114 03B0     		add	sp, sp, #12
+ 6587              	.LCFI76:
+ 6588              		.cfi_remember_state
+ 6589              		.cfi_def_cfa_offset 20
+ 6590              		@ sp needed
+ 6591 0116 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 6592              	.LVL439:
+ 6593              	.L425:
+ 6594              	.LCFI77:
+ 6595              		.cfi_restore_state
+2990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6596              		.loc 1 2990 14 view .LVU2265
+ 6597 0118 0225     		movs	r5, #2
+ARM GAS  /tmp/ccVyGVF6.s 			page 286
+
+
+ 6598 011a FAE7     		b	.L415
+ 6599              	.L426:
+2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6600              		.loc 1 2994 5 view .LVU2266
+ 6601 011c 0225     		movs	r5, #2
+ 6602 011e F8E7     		b	.L415
+ 6603              	.L433:
+ 6604              		.align	2
+ 6605              	.L432:
+ 6606 0120 0000FFFF 		.word	-65536
+ 6607 0124 00000000 		.word	I2C_Mem_ISR_DMA
+ 6608 0128 00000000 		.word	I2C_DMAMasterTransmitCplt
+ 6609 012c 00000000 		.word	I2C_DMAError
+ 6610 0130 00200080 		.word	-2147475456
+ 6611              		.cfi_endproc
+ 6612              	.LFE161:
+ 6614              		.section	.text.HAL_I2C_Mem_Read_DMA,"ax",%progbits
+ 6615              		.align	1
+ 6616              		.global	HAL_I2C_Mem_Read_DMA
+ 6617              		.syntax unified
+ 6618              		.thumb
+ 6619              		.thumb_func
+ 6620              		.fpu fpv5-d16
+ 6622              	HAL_I2C_Mem_Read_DMA:
+ 6623              	.LVL440:
+ 6624              	.LFB162:
+3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 6625              		.loc 1 3120 1 is_stmt 1 view -0
+ 6626              		.cfi_startproc
+ 6627              		@ args = 8, pretend = 0, frame = 0
+ 6628              		@ frame_needed = 0, uses_anonymous_args = 0
+3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 6629              		.loc 1 3120 1 is_stmt 0 view .LVU2268
+ 6630 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 6631              	.LCFI78:
+ 6632              		.cfi_def_cfa_offset 20
+ 6633              		.cfi_offset 4, -20
+ 6634              		.cfi_offset 5, -16
+ 6635              		.cfi_offset 6, -12
+ 6636              		.cfi_offset 7, -8
+ 6637              		.cfi_offset 14, -4
+ 6638 0002 83B0     		sub	sp, sp, #12
+ 6639              	.LCFI79:
+ 6640              		.cfi_def_cfa_offset 32
+ 6641 0004 0446     		mov	r4, r0
+ 6642 0006 1F46     		mov	r7, r3
+ 6643 0008 089D     		ldr	r5, [sp, #32]
+ 6644 000a BDF82430 		ldrh	r3, [sp, #36]
+ 6645              	.LVL441:
+3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6646              		.loc 1 3121 3 is_stmt 1 view .LVU2269
+3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6647              		.loc 1 3124 3 view .LVU2270
+3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6648              		.loc 1 3126 3 view .LVU2271
+3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6649              		.loc 1 3126 11 is_stmt 0 view .LVU2272
+ARM GAS  /tmp/ccVyGVF6.s 			page 287
+
+
+ 6650 000e 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 6651              	.LVL442:
+3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6652              		.loc 1 3126 11 view .LVU2273
+ 6653 0012 C0B2     		uxtb	r0, r0
+3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6654              		.loc 1 3126 6 view .LVU2274
+ 6655 0014 2028     		cmp	r0, #32
+ 6656 0016 7BD1     		bne	.L444
+ 6657 0018 0E46     		mov	r6, r1
+3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6658              		.loc 1 3128 5 is_stmt 1 view .LVU2275
+3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6659              		.loc 1 3128 8 is_stmt 0 view .LVU2276
+ 6660 001a 002B     		cmp	r3, #0
+ 6661 001c 18BF     		it	ne
+ 6662 001e 002D     		cmpne	r5, #0
+ 6663 0020 4AD0     		beq	.L449
+3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6664              		.loc 1 3134 5 is_stmt 1 view .LVU2277
+3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6665              		.loc 1 3134 9 is_stmt 0 view .LVU2278
+ 6666 0022 2168     		ldr	r1, [r4]
+ 6667              	.LVL443:
+3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6668              		.loc 1 3134 9 view .LVU2279
+ 6669 0024 8869     		ldr	r0, [r1, #24]
+3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6670              		.loc 1 3134 8 view .LVU2280
+ 6671 0026 10F4004F 		tst	r0, #32768
+ 6672 002a 75D1     		bne	.L445
+3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6673              		.loc 1 3140 5 is_stmt 1 view .LVU2281
+3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6674              		.loc 1 3140 5 view .LVU2282
+ 6675 002c 94F84000 		ldrb	r0, [r4, #64]	@ zero_extendqisi2
+ 6676 0030 0128     		cmp	r0, #1
+ 6677 0032 73D0     		beq	.L446
+3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6678              		.loc 1 3140 5 discriminator 2 view .LVU2283
+ 6679 0034 0120     		movs	r0, #1
+ 6680 0036 84F84000 		strb	r0, [r4, #64]
+3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6681              		.loc 1 3140 5 discriminator 2 view .LVU2284
+3142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6682              		.loc 1 3142 5 discriminator 2 view .LVU2285
+3142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode        = HAL_I2C_MODE_MEM;
+ 6683              		.loc 1 3142 23 is_stmt 0 discriminator 2 view .LVU2286
+ 6684 003a 2220     		movs	r0, #34
+ 6685 003c 84F84100 		strb	r0, [r4, #65]
+3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6686              		.loc 1 3143 5 is_stmt 1 discriminator 2 view .LVU2287
+3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+ 6687              		.loc 1 3143 23 is_stmt 0 discriminator 2 view .LVU2288
+ 6688 0040 4020     		movs	r0, #64
+ 6689 0042 84F84200 		strb	r0, [r4, #66]
+3144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 288
+
+
+ 6690              		.loc 1 3144 5 is_stmt 1 discriminator 2 view .LVU2289
+3144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6691              		.loc 1 3144 23 is_stmt 0 discriminator 2 view .LVU2290
+ 6692 0046 0020     		movs	r0, #0
+ 6693 0048 6064     		str	r0, [r4, #68]
+3147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6694              		.loc 1 3147 5 is_stmt 1 discriminator 2 view .LVU2291
+3147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 6695              		.loc 1 3147 23 is_stmt 0 discriminator 2 view .LVU2292
+ 6696 004a 6562     		str	r5, [r4, #36]
+3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6697              		.loc 1 3148 5 is_stmt 1 discriminator 2 view .LVU2293
+3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 6698              		.loc 1 3148 23 is_stmt 0 discriminator 2 view .LVU2294
+ 6699 004c 6385     		strh	r3, [r4, #42]	@ movhi
+3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_DMA;
+ 6700              		.loc 1 3149 5 is_stmt 1 discriminator 2 view .LVU2295
+3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Mem_ISR_DMA;
+ 6701              		.loc 1 3149 23 is_stmt 0 discriminator 2 view .LVU2296
+ 6702 004e 344B     		ldr	r3, .L452
+ 6703 0050 E362     		str	r3, [r4, #44]
+3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+ 6704              		.loc 1 3150 5 is_stmt 1 discriminator 2 view .LVU2297
+3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Devaddress  = DevAddress;
+ 6705              		.loc 1 3150 23 is_stmt 0 discriminator 2 view .LVU2298
+ 6706 0052 344B     		ldr	r3, .L452+4
+ 6707 0054 6363     		str	r3, [r4, #52]
+3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6708              		.loc 1 3151 5 is_stmt 1 discriminator 2 view .LVU2299
+3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6709              		.loc 1 3151 23 is_stmt 0 discriminator 2 view .LVU2300
+ 6710 0056 E664     		str	r6, [r4, #76]
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6711              		.loc 1 3153 5 is_stmt 1 discriminator 2 view .LVU2301
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6712              		.loc 1 3153 13 is_stmt 0 discriminator 2 view .LVU2302
+ 6713 0058 638D     		ldrh	r3, [r4, #42]
+ 6714 005a 9BB2     		uxth	r3, r3
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6715              		.loc 1 3153 8 discriminator 2 view .LVU2303
+ 6716 005c FF2B     		cmp	r3, #255
+ 6717 005e 30D9     		bls	.L437
+3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6718              		.loc 1 3155 7 is_stmt 1 view .LVU2304
+3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6719              		.loc 1 3155 22 is_stmt 0 view .LVU2305
+ 6720 0060 FF23     		movs	r3, #255
+ 6721 0062 2385     		strh	r3, [r4, #40]	@ movhi
+ 6722              	.L438:
+3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6723              		.loc 1 3163 5 is_stmt 1 view .LVU2306
+3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6724              		.loc 1 3163 8 is_stmt 0 view .LVU2307
+ 6725 0064 012F     		cmp	r7, #1
+ 6726 0066 2FD0     		beq	.L450
+3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6727              		.loc 1 3175 7 is_stmt 1 view .LVU2308
+ARM GAS  /tmp/ccVyGVF6.s 			page 289
+
+
+3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6728              		.loc 1 3175 30 is_stmt 0 view .LVU2309
+ 6729 0068 130A     		lsrs	r3, r2, #8
+3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6730              		.loc 1 3175 28 view .LVU2310
+ 6731 006a 8B62     		str	r3, [r1, #40]
+3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6732              		.loc 1 3178 7 is_stmt 1 view .LVU2311
+3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6733              		.loc 1 3178 26 is_stmt 0 view .LVU2312
+ 6734 006c D2B2     		uxtb	r2, r2
+ 6735              	.LVL444:
+3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6736              		.loc 1 3178 24 view .LVU2313
+ 6737 006e 2265     		str	r2, [r4, #80]
+ 6738              	.L440:
+3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6739              		.loc 1 3181 5 is_stmt 1 view .LVU2314
+3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6740              		.loc 1 3181 13 is_stmt 0 view .LVU2315
+ 6741 0070 E36B     		ldr	r3, [r4, #60]
+3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6742              		.loc 1 3181 8 view .LVU2316
+ 6743 0072 002B     		cmp	r3, #0
+ 6744 0074 2ED0     		beq	.L441
+3184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6745              		.loc 1 3184 7 is_stmt 1 view .LVU2317
+3184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6746              		.loc 1 3184 38 is_stmt 0 view .LVU2318
+ 6747 0076 2C4A     		ldr	r2, .L452+8
+ 6748 0078 DA63     		str	r2, [r3, #60]
+3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6749              		.loc 1 3187 7 is_stmt 1 view .LVU2319
+3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6750              		.loc 1 3187 11 is_stmt 0 view .LVU2320
+ 6751 007a E36B     		ldr	r3, [r4, #60]
+3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6752              		.loc 1 3187 39 view .LVU2321
+ 6753 007c 2B4A     		ldr	r2, .L452+12
+ 6754 007e DA64     		str	r2, [r3, #76]
+3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 6755              		.loc 1 3190 7 is_stmt 1 view .LVU2322
+3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 6756              		.loc 1 3190 11 is_stmt 0 view .LVU2323
+ 6757 0080 E26B     		ldr	r2, [r4, #60]
+3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 6758              		.loc 1 3190 42 view .LVU2324
+ 6759 0082 0023     		movs	r3, #0
+ 6760 0084 1364     		str	r3, [r2, #64]
+3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6761              		.loc 1 3191 7 is_stmt 1 view .LVU2325
+3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6762              		.loc 1 3191 11 is_stmt 0 view .LVU2326
+ 6763 0086 E26B     		ldr	r2, [r4, #60]
+3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6764              		.loc 1 3191 39 view .LVU2327
+ 6765 0088 1365     		str	r3, [r2, #80]
+ARM GAS  /tmp/ccVyGVF6.s 			page 290
+
+
+3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6766              		.loc 1 3194 7 is_stmt 1 view .LVU2328
+3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6767              		.loc 1 3194 69 is_stmt 0 view .LVU2329
+ 6768 008a 2168     		ldr	r1, [r4]
+3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 6769              		.loc 1 3194 23 view .LVU2330
+ 6770 008c 238D     		ldrh	r3, [r4, #40]
+ 6771 008e 2A46     		mov	r2, r5
+ 6772 0090 2431     		adds	r1, r1, #36
+ 6773 0092 E06B     		ldr	r0, [r4, #60]
+ 6774 0094 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 6775              	.LVL445:
+3212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6776              		.loc 1 3212 5 is_stmt 1 view .LVU2331
+3212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6777              		.loc 1 3212 8 is_stmt 0 view .LVU2332
+ 6778 0098 0546     		mov	r5, r0
+ 6779 009a 48B3     		cbz	r0, .L451
+3232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6780              		.loc 1 3232 7 is_stmt 1 view .LVU2333
+3232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6781              		.loc 1 3232 23 is_stmt 0 view .LVU2334
+ 6782 009c 2023     		movs	r3, #32
+ 6783 009e 84F84130 		strb	r3, [r4, #65]
+3233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6784              		.loc 1 3233 7 is_stmt 1 view .LVU2335
+3233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6785              		.loc 1 3233 23 is_stmt 0 view .LVU2336
+ 6786 00a2 0022     		movs	r2, #0
+ 6787 00a4 84F84220 		strb	r2, [r4, #66]
+3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6788              		.loc 1 3236 7 is_stmt 1 view .LVU2337
+3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6789              		.loc 1 3236 23 is_stmt 0 view .LVU2338
+ 6790 00a8 636C     		ldr	r3, [r4, #68]
+ 6791 00aa 43F01003 		orr	r3, r3, #16
+ 6792 00ae 6364     		str	r3, [r4, #68]
+3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6793              		.loc 1 3239 7 is_stmt 1 view .LVU2339
+3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6794              		.loc 1 3239 7 view .LVU2340
+ 6795 00b0 84F84020 		strb	r2, [r4, #64]
+3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6796              		.loc 1 3239 7 view .LVU2341
+3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6797              		.loc 1 3241 7 view .LVU2342
+3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6798              		.loc 1 3241 14 is_stmt 0 view .LVU2343
+ 6799 00b4 0125     		movs	r5, #1
+ 6800 00b6 2CE0     		b	.L435
+ 6801              	.LVL446:
+ 6802              	.L449:
+3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6803              		.loc 1 3130 7 is_stmt 1 view .LVU2344
+3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 6804              		.loc 1 3130 23 is_stmt 0 view .LVU2345
+ARM GAS  /tmp/ccVyGVF6.s 			page 291
+
+
+ 6805 00b8 4FF40073 		mov	r3, #512
+ 6806 00bc 6364     		str	r3, [r4, #68]
+3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6807              		.loc 1 3131 7 is_stmt 1 view .LVU2346
+3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6808              		.loc 1 3131 15 is_stmt 0 view .LVU2347
+ 6809 00be 0125     		movs	r5, #1
+ 6810 00c0 27E0     		b	.L435
+ 6811              	.LVL447:
+ 6812              	.L437:
+3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6813              		.loc 1 3159 7 is_stmt 1 view .LVU2348
+3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6814              		.loc 1 3159 28 is_stmt 0 view .LVU2349
+ 6815 00c2 638D     		ldrh	r3, [r4, #42]
+3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6816              		.loc 1 3159 22 view .LVU2350
+ 6817 00c4 2385     		strh	r3, [r4, #40]	@ movhi
+ 6818 00c6 CDE7     		b	.L438
+ 6819              	.L450:
+3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6820              		.loc 1 3166 7 is_stmt 1 view .LVU2351
+3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6821              		.loc 1 3166 30 is_stmt 0 view .LVU2352
+ 6822 00c8 D2B2     		uxtb	r2, r2
+ 6823              	.LVL448:
+3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6824              		.loc 1 3166 28 view .LVU2353
+ 6825 00ca 8A62     		str	r2, [r1, #40]
+3169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6826              		.loc 1 3169 7 is_stmt 1 view .LVU2354
+3169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6827              		.loc 1 3169 24 is_stmt 0 view .LVU2355
+ 6828 00cc 4FF0FF33 		mov	r3, #-1
+ 6829 00d0 2365     		str	r3, [r4, #80]
+ 6830 00d2 CDE7     		b	.L440
+ 6831              	.L441:
+3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6832              		.loc 1 3200 7 is_stmt 1 view .LVU2356
+3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 6833              		.loc 1 3200 23 is_stmt 0 view .LVU2357
+ 6834 00d4 2023     		movs	r3, #32
+ 6835 00d6 84F84130 		strb	r3, [r4, #65]
+3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6836              		.loc 1 3201 7 is_stmt 1 view .LVU2358
+3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6837              		.loc 1 3201 23 is_stmt 0 view .LVU2359
+ 6838 00da 0022     		movs	r2, #0
+ 6839 00dc 84F84220 		strb	r2, [r4, #66]
+3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6840              		.loc 1 3204 7 is_stmt 1 view .LVU2360
+3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6841              		.loc 1 3204 23 is_stmt 0 view .LVU2361
+ 6842 00e0 636C     		ldr	r3, [r4, #68]
+ 6843 00e2 43F08003 		orr	r3, r3, #128
+ 6844 00e6 6364     		str	r3, [r4, #68]
+3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 292
+
+
+ 6845              		.loc 1 3207 7 is_stmt 1 view .LVU2362
+3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6846              		.loc 1 3207 7 view .LVU2363
+ 6847 00e8 84F84020 		strb	r2, [r4, #64]
+3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6848              		.loc 1 3207 7 view .LVU2364
+3209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6849              		.loc 1 3209 7 view .LVU2365
+3209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6850              		.loc 1 3209 14 is_stmt 0 view .LVU2366
+ 6851 00ec 0125     		movs	r5, #1
+ 6852 00ee 10E0     		b	.L435
+ 6853              	.LVL449:
+ 6854              	.L451:
+3215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6855              		.loc 1 3215 7 is_stmt 1 view .LVU2367
+ 6856 00f0 0F4B     		ldr	r3, .L452+16
+ 6857 00f2 0093     		str	r3, [sp]
+ 6858 00f4 0023     		movs	r3, #0
+ 6859 00f6 FAB2     		uxtb	r2, r7
+ 6860 00f8 3146     		mov	r1, r6
+ 6861 00fa 2046     		mov	r0, r4
+ 6862              	.LVL450:
+3215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6863              		.loc 1 3215 7 is_stmt 0 view .LVU2368
+ 6864 00fc FFF7FEFF 		bl	I2C_TransferConfig
+ 6865              	.LVL451:
+3218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6866              		.loc 1 3218 7 is_stmt 1 view .LVU2369
+3218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6867              		.loc 1 3218 7 view .LVU2370
+ 6868 0100 0023     		movs	r3, #0
+ 6869 0102 84F84030 		strb	r3, [r4, #64]
+3218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6870              		.loc 1 3218 7 view .LVU2371
+3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6871              		.loc 1 3227 7 view .LVU2372
+ 6872 0106 0121     		movs	r1, #1
+ 6873 0108 2046     		mov	r0, r4
+ 6874 010a FFF7FEFF 		bl	I2C_Enable_IRQ
+ 6875              	.LVL452:
+3244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6876              		.loc 1 3244 5 view .LVU2373
+3244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6877              		.loc 1 3244 12 is_stmt 0 view .LVU2374
+ 6878 010e 00E0     		b	.L435
+ 6879              	.LVL453:
+ 6880              	.L444:
+3248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 6881              		.loc 1 3248 12 view .LVU2375
+ 6882 0110 0225     		movs	r5, #2
+ 6883              	.LVL454:
+ 6884              	.L435:
+3250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6885              		.loc 1 3250 1 view .LVU2376
+ 6886 0112 2846     		mov	r0, r5
+ 6887 0114 03B0     		add	sp, sp, #12
+ARM GAS  /tmp/ccVyGVF6.s 			page 293
+
+
+ 6888              	.LCFI80:
+ 6889              		.cfi_remember_state
+ 6890              		.cfi_def_cfa_offset 20
+ 6891              		@ sp needed
+ 6892 0116 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 6893              	.LVL455:
+ 6894              	.L445:
+ 6895              	.LCFI81:
+ 6896              		.cfi_restore_state
+3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 6897              		.loc 1 3136 14 view .LVU2377
+ 6898 0118 0225     		movs	r5, #2
+ 6899 011a FAE7     		b	.L435
+ 6900              	.L446:
+3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6901              		.loc 1 3140 5 view .LVU2378
+ 6902 011c 0225     		movs	r5, #2
+ 6903 011e F8E7     		b	.L435
+ 6904              	.L453:
+ 6905              		.align	2
+ 6906              	.L452:
+ 6907 0120 0000FFFF 		.word	-65536
+ 6908 0124 00000000 		.word	I2C_Mem_ISR_DMA
+ 6909 0128 00000000 		.word	I2C_DMAMasterReceiveCplt
+ 6910 012c 00000000 		.word	I2C_DMAError
+ 6911 0130 00200080 		.word	-2147475456
+ 6912              		.cfi_endproc
+ 6913              	.LFE162:
+ 6915              		.section	.text.HAL_I2C_IsDeviceReady,"ax",%progbits
+ 6916              		.align	1
+ 6917              		.global	HAL_I2C_IsDeviceReady
+ 6918              		.syntax unified
+ 6919              		.thumb
+ 6920              		.thumb_func
+ 6921              		.fpu fpv5-d16
+ 6923              	HAL_I2C_IsDeviceReady:
+ 6924              	.LVL456:
+ 6925              	.LFB163:
+3265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 6926              		.loc 1 3265 1 is_stmt 1 view -0
+ 6927              		.cfi_startproc
+ 6928              		@ args = 0, pretend = 0, frame = 8
+ 6929              		@ frame_needed = 0, uses_anonymous_args = 0
+3265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tickstart;
+ 6930              		.loc 1 3265 1 is_stmt 0 view .LVU2380
+ 6931 0000 2DE9F043 		push	{r4, r5, r6, r7, r8, r9, lr}
+ 6932              	.LCFI82:
+ 6933              		.cfi_def_cfa_offset 28
+ 6934              		.cfi_offset 4, -28
+ 6935              		.cfi_offset 5, -24
+ 6936              		.cfi_offset 6, -20
+ 6937              		.cfi_offset 7, -16
+ 6938              		.cfi_offset 8, -12
+ 6939              		.cfi_offset 9, -8
+ 6940              		.cfi_offset 14, -4
+ 6941 0004 85B0     		sub	sp, sp, #20
+ 6942              	.LCFI83:
+ARM GAS  /tmp/ccVyGVF6.s 			page 294
+
+
+ 6943              		.cfi_def_cfa_offset 48
+ 6944 0006 1D46     		mov	r5, r3
+3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6945              		.loc 1 3266 3 is_stmt 1 view .LVU2381
+3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6946              		.loc 1 3268 3 view .LVU2382
+3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6947              		.loc 1 3268 17 is_stmt 0 view .LVU2383
+ 6948 0008 0023     		movs	r3, #0
+ 6949              	.LVL457:
+3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6950              		.loc 1 3268 17 view .LVU2384
+ 6951 000a 0393     		str	r3, [sp, #12]
+3270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   FlagStatus tmp2;
+ 6952              		.loc 1 3270 3 is_stmt 1 view .LVU2385
+3271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6953              		.loc 1 3271 3 view .LVU2386
+3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6954              		.loc 1 3273 3 view .LVU2387
+3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6955              		.loc 1 3273 11 is_stmt 0 view .LVU2388
+ 6956 000c 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 6957 0010 DBB2     		uxtb	r3, r3
+3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 6958              		.loc 1 3273 6 view .LVU2389
+ 6959 0012 202B     		cmp	r3, #32
+ 6960 0014 40F08380 		bne	.L464
+ 6961 0018 0646     		mov	r6, r0
+ 6962 001a 8846     		mov	r8, r1
+ 6963 001c 9146     		mov	r9, r2
+3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6964              		.loc 1 3275 5 is_stmt 1 view .LVU2390
+3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6965              		.loc 1 3275 9 is_stmt 0 view .LVU2391
+ 6966 001e 0368     		ldr	r3, [r0]
+ 6967 0020 9B69     		ldr	r3, [r3, #24]
+3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6968              		.loc 1 3275 8 view .LVU2392
+ 6969 0022 13F4004F 		tst	r3, #32768
+ 6970 0026 7CD1     		bne	.L465
+3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6971              		.loc 1 3281 5 is_stmt 1 view .LVU2393
+3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6972              		.loc 1 3281 5 view .LVU2394
+ 6973 0028 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 6974 002c 012B     		cmp	r3, #1
+ 6975 002e 7AD0     		beq	.L466
+3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6976              		.loc 1 3281 5 discriminator 2 view .LVU2395
+ 6977 0030 0123     		movs	r3, #1
+ 6978 0032 80F84030 		strb	r3, [r0, #64]
+3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6979              		.loc 1 3281 5 discriminator 2 view .LVU2396
+3283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 6980              		.loc 1 3283 5 discriminator 2 view .LVU2397
+3283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 6981              		.loc 1 3283 17 is_stmt 0 discriminator 2 view .LVU2398
+ARM GAS  /tmp/ccVyGVF6.s 			page 295
+
+
+ 6982 0036 2423     		movs	r3, #36
+ 6983 0038 80F84130 		strb	r3, [r0, #65]
+3284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6984              		.loc 1 3284 5 is_stmt 1 discriminator 2 view .LVU2399
+3284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6985              		.loc 1 3284 21 is_stmt 0 discriminator 2 view .LVU2400
+ 6986 003c 0023     		movs	r3, #0
+ 6987 003e 4364     		str	r3, [r0, #68]
+ 6988              	.LVL458:
+ 6989              	.L463:
+3286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 6990              		.loc 1 3286 5 is_stmt 1 view .LVU2401
+3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6991              		.loc 1 3289 7 view .LVU2402
+3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6992              		.loc 1 3289 29 is_stmt 0 view .LVU2403
+ 6993 0040 F368     		ldr	r3, [r6, #12]
+ 6994 0042 012B     		cmp	r3, #1
+ 6995 0044 10D0     		beq	.L470
+3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 6996              		.loc 1 3289 29 discriminator 2 view .LVU2404
+ 6997 0046 C8F30902 		ubfx	r2, r8, #0, #10
+ 6998 004a 3A4B     		ldr	r3, .L473
+ 6999 004c 1343     		orrs	r3, r3, r2
+ 7000              	.L457:
+3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7001              		.loc 1 3289 11 discriminator 4 view .LVU2405
+ 7002 004e 3268     		ldr	r2, [r6]
+3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7003              		.loc 1 3289 27 discriminator 4 view .LVU2406
+ 7004 0050 5360     		str	r3, [r2, #4]
+3293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7005              		.loc 1 3293 7 is_stmt 1 discriminator 4 view .LVU2407
+3293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7006              		.loc 1 3293 19 is_stmt 0 discriminator 4 view .LVU2408
+ 7007 0052 FFF7FEFF 		bl	HAL_GetTick
+ 7008              	.LVL459:
+ 7009 0056 0746     		mov	r7, r0
+ 7010              	.LVL460:
+3295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ 7011              		.loc 1 3295 7 is_stmt 1 discriminator 4 view .LVU2409
+3295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ 7012              		.loc 1 3295 14 is_stmt 0 discriminator 4 view .LVU2410
+ 7013 0058 3268     		ldr	r2, [r6]
+ 7014 005a 9369     		ldr	r3, [r2, #24]
+ 7015 005c C3F34013 		ubfx	r3, r3, #5, #1
+ 7016              	.LVL461:
+3296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7017              		.loc 1 3296 7 is_stmt 1 discriminator 4 view .LVU2411
+3296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7018              		.loc 1 3296 14 is_stmt 0 discriminator 4 view .LVU2412
+ 7019 0060 9469     		ldr	r4, [r2, #24]
+ 7020 0062 C4F3001C 		ubfx	ip, r4, #4, #1
+ 7021              	.LVL462:
+3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7022              		.loc 1 3298 7 is_stmt 1 discriminator 4 view .LVU2413
+3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ARM GAS  /tmp/ccVyGVF6.s 			page 296
+
+
+ 7023              		.loc 1 3298 13 is_stmt 0 discriminator 4 view .LVU2414
+ 7024 0066 0BE0     		b	.L458
+ 7025              	.LVL463:
+ 7026              	.L470:
+3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7027              		.loc 1 3289 29 discriminator 1 view .LVU2415
+ 7028 0068 C8F30902 		ubfx	r2, r8, #0, #10
+ 7029 006c 324B     		ldr	r3, .L473+4
+ 7030 006e 1343     		orrs	r3, r3, r2
+ 7031 0070 EDE7     		b	.L457
+ 7032              	.LVL464:
+ 7033              	.L459:
+3317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ 7034              		.loc 1 3317 9 is_stmt 1 view .LVU2416
+3317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ 7035              		.loc 1 3317 16 is_stmt 0 view .LVU2417
+ 7036 0072 3268     		ldr	r2, [r6]
+ 7037 0074 9369     		ldr	r3, [r2, #24]
+ 7038 0076 C3F34013 		ubfx	r3, r3, #5, #1
+ 7039              	.LVL465:
+3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7040              		.loc 1 3318 9 is_stmt 1 view .LVU2418
+3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7041              		.loc 1 3318 16 is_stmt 0 view .LVU2419
+ 7042 007a 9469     		ldr	r4, [r2, #24]
+ 7043 007c C4F3001C 		ubfx	ip, r4, #4, #1
+ 7044              	.LVL466:
+ 7045              	.L458:
+3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7046              		.loc 1 3298 13 is_stmt 1 view .LVU2420
+ 7047 0080 53EA0C03 		orrs	r3, r3, ip
+ 7048              	.LVL467:
+3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7049              		.loc 1 3298 13 is_stmt 0 view .LVU2421
+ 7050 0084 17D1     		bne	.L471
+3300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 7051              		.loc 1 3300 9 is_stmt 1 view .LVU2422
+3300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 7052              		.loc 1 3300 12 is_stmt 0 view .LVU2423
+ 7053 0086 B5F1FF3F 		cmp	r5, #-1
+ 7054 008a F2D0     		beq	.L459
+3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 7055              		.loc 1 3302 11 is_stmt 1 view .LVU2424
+3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 7056              		.loc 1 3302 17 is_stmt 0 view .LVU2425
+ 7057 008c FFF7FEFF 		bl	HAL_GetTick
+ 7058              	.LVL468:
+3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 7059              		.loc 1 3302 31 view .LVU2426
+ 7060 0090 C01B     		subs	r0, r0, r7
+3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 7061              		.loc 1 3302 14 view .LVU2427
+ 7062 0092 A842     		cmp	r0, r5
+ 7063 0094 01D8     		bhi	.L460
+3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 7064              		.loc 1 3302 55 discriminator 1 view .LVU2428
+ 7065 0096 002D     		cmp	r5, #0
+ARM GAS  /tmp/ccVyGVF6.s 			page 297
+
+
+ 7066 0098 EBD1     		bne	.L459
+ 7067              	.L460:
+3305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7068              		.loc 1 3305 13 is_stmt 1 view .LVU2429
+3305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7069              		.loc 1 3305 25 is_stmt 0 view .LVU2430
+ 7070 009a 2023     		movs	r3, #32
+ 7071 009c 86F84130 		strb	r3, [r6, #65]
+3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7072              		.loc 1 3308 13 is_stmt 1 view .LVU2431
+3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7073              		.loc 1 3308 29 is_stmt 0 view .LVU2432
+ 7074 00a0 736C     		ldr	r3, [r6, #68]
+ 7075 00a2 43F02003 		orr	r3, r3, #32
+ 7076 00a6 7364     		str	r3, [r6, #68]
+3311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7077              		.loc 1 3311 13 is_stmt 1 view .LVU2433
+3311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7078              		.loc 1 3311 13 view .LVU2434
+ 7079 00a8 0023     		movs	r3, #0
+ 7080 00aa 86F84030 		strb	r3, [r6, #64]
+3311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7081              		.loc 1 3311 13 view .LVU2435
+3313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 7082              		.loc 1 3313 13 view .LVU2436
+3313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 7083              		.loc 1 3313 20 is_stmt 0 view .LVU2437
+ 7084 00ae 0120     		movs	r0, #1
+ 7085              	.LVL469:
+ 7086              	.L455:
+3375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7087              		.loc 1 3375 1 view .LVU2438
+ 7088 00b0 05B0     		add	sp, sp, #20
+ 7089              	.LCFI84:
+ 7090              		.cfi_remember_state
+ 7091              		.cfi_def_cfa_offset 28
+ 7092              		@ sp needed
+ 7093 00b2 BDE8F083 		pop	{r4, r5, r6, r7, r8, r9, pc}
+ 7094              	.LVL470:
+ 7095              	.L471:
+ 7096              	.LCFI85:
+ 7097              		.cfi_restore_state
+3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7098              		.loc 1 3322 7 is_stmt 1 view .LVU2439
+3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7099              		.loc 1 3322 11 is_stmt 0 view .LVU2440
+ 7100 00b6 3368     		ldr	r3, [r6]
+ 7101 00b8 9B69     		ldr	r3, [r3, #24]
+3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7102              		.loc 1 3322 10 view .LVU2441
+ 7103 00ba 13F0100F 		tst	r3, #16
+ 7104 00be 1DD0     		beq	.L472
+3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 7105              		.loc 1 3344 9 is_stmt 1 view .LVU2442
+3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 7106              		.loc 1 3344 13 is_stmt 0 view .LVU2443
+ 7107 00c0 0097     		str	r7, [sp]
+ARM GAS  /tmp/ccVyGVF6.s 			page 298
+
+
+ 7108 00c2 2B46     		mov	r3, r5
+ 7109 00c4 0022     		movs	r2, #0
+ 7110 00c6 2021     		movs	r1, #32
+ 7111 00c8 3046     		mov	r0, r6
+ 7112 00ca FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 7113              	.LVL471:
+3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 7114              		.loc 1 3344 12 view .LVU2444
+ 7115 00ce 70BB     		cbnz	r0, .L468
+3350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7116              		.loc 1 3350 9 is_stmt 1 view .LVU2445
+ 7117 00d0 3368     		ldr	r3, [r6]
+ 7118 00d2 1022     		movs	r2, #16
+ 7119 00d4 DA61     		str	r2, [r3, #28]
+3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7120              		.loc 1 3353 9 view .LVU2446
+ 7121 00d6 3368     		ldr	r3, [r6]
+ 7122 00d8 2022     		movs	r2, #32
+ 7123 00da DA61     		str	r2, [r3, #28]
+3357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     } while (I2C_Trials < Trials);
+ 7124              		.loc 1 3357 7 view .LVU2447
+3357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     } while (I2C_Trials < Trials);
+ 7125              		.loc 1 3357 17 is_stmt 0 view .LVU2448
+ 7126 00dc 039B     		ldr	r3, [sp, #12]
+ 7127 00de 0133     		adds	r3, r3, #1
+ 7128 00e0 0393     		str	r3, [sp, #12]
+3358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7129              		.loc 1 3358 13 is_stmt 1 view .LVU2449
+3358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7130              		.loc 1 3358 25 is_stmt 0 view .LVU2450
+ 7131 00e2 039B     		ldr	r3, [sp, #12]
+3358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7132              		.loc 1 3358 5 view .LVU2451
+ 7133 00e4 4B45     		cmp	r3, r9
+ 7134 00e6 ABD3     		bcc	.L463
+3361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7135              		.loc 1 3361 5 is_stmt 1 view .LVU2452
+3361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7136              		.loc 1 3361 17 is_stmt 0 view .LVU2453
+ 7137 00e8 86F84120 		strb	r2, [r6, #65]
+3364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7138              		.loc 1 3364 5 is_stmt 1 view .LVU2454
+3364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7139              		.loc 1 3364 21 is_stmt 0 view .LVU2455
+ 7140 00ec 736C     		ldr	r3, [r6, #68]
+ 7141 00ee 1343     		orrs	r3, r3, r2
+ 7142 00f0 7364     		str	r3, [r6, #68]
+3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7143              		.loc 1 3367 5 is_stmt 1 view .LVU2456
+3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7144              		.loc 1 3367 5 view .LVU2457
+ 7145 00f2 0023     		movs	r3, #0
+ 7146 00f4 86F84030 		strb	r3, [r6, #64]
+3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7147              		.loc 1 3367 5 view .LVU2458
+3369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 7148              		.loc 1 3369 5 view .LVU2459
+ARM GAS  /tmp/ccVyGVF6.s 			page 299
+
+
+3369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 7149              		.loc 1 3369 12 is_stmt 0 view .LVU2460
+ 7150 00f8 0120     		movs	r0, #1
+ 7151 00fa D9E7     		b	.L455
+ 7152              	.LVL472:
+ 7153              	.L472:
+3325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 7154              		.loc 1 3325 9 is_stmt 1 view .LVU2461
+3325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 7155              		.loc 1 3325 13 is_stmt 0 view .LVU2462
+ 7156 00fc 0097     		str	r7, [sp]
+ 7157 00fe 2B46     		mov	r3, r5
+ 7158 0100 0022     		movs	r2, #0
+ 7159 0102 2021     		movs	r1, #32
+ 7160 0104 3046     		mov	r0, r6
+ 7161 0106 FFF7FEFF 		bl	I2C_WaitOnFlagUntilTimeout
+ 7162              	.LVL473:
+3325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 7163              		.loc 1 3325 12 view .LVU2463
+ 7164 010a 70B9     		cbnz	r0, .L467
+3331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7165              		.loc 1 3331 9 is_stmt 1 view .LVU2464
+ 7166 010c 3268     		ldr	r2, [r6]
+ 7167 010e 2023     		movs	r3, #32
+ 7168 0110 D361     		str	r3, [r2, #28]
+3334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7169              		.loc 1 3334 9 view .LVU2465
+3334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7170              		.loc 1 3334 21 is_stmt 0 view .LVU2466
+ 7171 0112 86F84130 		strb	r3, [r6, #65]
+3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7172              		.loc 1 3337 9 is_stmt 1 view .LVU2467
+3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7173              		.loc 1 3337 9 view .LVU2468
+ 7174 0116 0023     		movs	r3, #0
+ 7175 0118 86F84030 		strb	r3, [r6, #64]
+3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7176              		.loc 1 3337 9 view .LVU2469
+3339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7177              		.loc 1 3339 9 view .LVU2470
+3339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7178              		.loc 1 3339 16 is_stmt 0 view .LVU2471
+ 7179 011c C8E7     		b	.L455
+ 7180              	.LVL474:
+ 7181              	.L464:
+3373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 7182              		.loc 1 3373 12 view .LVU2472
+ 7183 011e 0220     		movs	r0, #2
+ 7184              	.LVL475:
+3373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 7185              		.loc 1 3373 12 view .LVU2473
+ 7186 0120 C6E7     		b	.L455
+ 7187              	.LVL476:
+ 7188              	.L465:
+3277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7189              		.loc 1 3277 14 view .LVU2474
+ 7190 0122 0220     		movs	r0, #2
+ARM GAS  /tmp/ccVyGVF6.s 			page 300
+
+
+ 7191              	.LVL477:
+3277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7192              		.loc 1 3277 14 view .LVU2475
+ 7193 0124 C4E7     		b	.L455
+ 7194              	.LVL478:
+ 7195              	.L466:
+3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7196              		.loc 1 3281 5 view .LVU2476
+ 7197 0126 0220     		movs	r0, #2
+ 7198              	.LVL479:
+3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7199              		.loc 1 3281 5 view .LVU2477
+ 7200 0128 C2E7     		b	.L455
+ 7201              	.LVL480:
+ 7202              	.L467:
+3327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 7203              		.loc 1 3327 18 view .LVU2478
+ 7204 012a 0120     		movs	r0, #1
+ 7205 012c C0E7     		b	.L455
+ 7206              	.L468:
+3346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 7207              		.loc 1 3346 18 view .LVU2479
+ 7208 012e 0120     		movs	r0, #1
+ 7209 0130 BEE7     		b	.L455
+ 7210              	.L474:
+ 7211 0132 00BF     		.align	2
+ 7212              	.L473:
+ 7213 0134 00280002 		.word	33564672
+ 7214 0138 00200002 		.word	33562624
+ 7215              		.cfi_endproc
+ 7216              	.LFE163:
+ 7218              		.section	.text.HAL_I2C_Master_Seq_Transmit_IT,"ax",%progbits
+ 7219              		.align	1
+ 7220              		.global	HAL_I2C_Master_Seq_Transmit_IT
+ 7221              		.syntax unified
+ 7222              		.thumb
+ 7223              		.thumb_func
+ 7224              		.fpu fpv5-d16
+ 7226              	HAL_I2C_Master_Seq_Transmit_IT:
+ 7227              	.LVL481:
+ 7228              	.LFB164:
+3391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 7229              		.loc 1 3391 1 is_stmt 1 view -0
+ 7230              		.cfi_startproc
+ 7231              		@ args = 4, pretend = 0, frame = 0
+ 7232              		@ frame_needed = 0, uses_anonymous_args = 0
+3391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 7233              		.loc 1 3391 1 is_stmt 0 view .LVU2481
+ 7234 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 7235              	.LCFI86:
+ 7236              		.cfi_def_cfa_offset 24
+ 7237              		.cfi_offset 4, -24
+ 7238              		.cfi_offset 5, -20
+ 7239              		.cfi_offset 6, -16
+ 7240              		.cfi_offset 7, -12
+ 7241              		.cfi_offset 8, -8
+ 7242              		.cfi_offset 14, -4
+ARM GAS  /tmp/ccVyGVF6.s 			page 301
+
+
+ 7243 0004 82B0     		sub	sp, sp, #8
+ 7244              	.LCFI87:
+ 7245              		.cfi_def_cfa_offset 32
+ 7246 0006 0446     		mov	r4, r0
+ 7247 0008 089E     		ldr	r6, [sp, #32]
+3392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+ 7248              		.loc 1 3392 3 is_stmt 1 view .LVU2482
+3393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t sizetoxfer = 0U;
+ 7249              		.loc 1 3393 3 view .LVU2483
+ 7250              	.LVL482:
+3394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7251              		.loc 1 3394 3 view .LVU2484
+3397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7252              		.loc 1 3397 3 view .LVU2485
+3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7253              		.loc 1 3399 3 view .LVU2486
+3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7254              		.loc 1 3399 11 is_stmt 0 view .LVU2487
+ 7255 000a 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 7256              	.LVL483:
+3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7257              		.loc 1 3399 11 view .LVU2488
+ 7258 000e C0B2     		uxtb	r0, r0
+3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7259              		.loc 1 3399 6 view .LVU2489
+ 7260 0010 2028     		cmp	r0, #32
+ 7261 0012 73D1     		bne	.L484
+ 7262 0014 0D46     		mov	r5, r1
+3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7263              		.loc 1 3402 5 is_stmt 1 view .LVU2490
+3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7264              		.loc 1 3402 5 view .LVU2491
+ 7265 0016 94F84010 		ldrb	r1, [r4, #64]	@ zero_extendqisi2
+ 7266              	.LVL484:
+3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7267              		.loc 1 3402 5 is_stmt 0 view .LVU2492
+ 7268 001a 0129     		cmp	r1, #1
+ 7269 001c 70D0     		beq	.L485
+3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7270              		.loc 1 3402 5 is_stmt 1 discriminator 2 view .LVU2493
+ 7271 001e 0121     		movs	r1, #1
+ 7272 0020 84F84010 		strb	r1, [r4, #64]
+3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7273              		.loc 1 3402 5 discriminator 2 view .LVU2494
+3404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7274              		.loc 1 3404 5 discriminator 2 view .LVU2495
+3404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7275              		.loc 1 3404 21 is_stmt 0 discriminator 2 view .LVU2496
+ 7276 0024 2121     		movs	r1, #33
+ 7277 0026 84F84110 		strb	r1, [r4, #65]
+3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7278              		.loc 1 3405 5 is_stmt 1 discriminator 2 view .LVU2497
+3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7279              		.loc 1 3405 21 is_stmt 0 discriminator 2 view .LVU2498
+ 7280 002a 1021     		movs	r1, #16
+ 7281 002c 84F84210 		strb	r1, [r4, #66]
+3406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 302
+
+
+ 7282              		.loc 1 3406 5 is_stmt 1 discriminator 2 view .LVU2499
+3406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7283              		.loc 1 3406 21 is_stmt 0 discriminator 2 view .LVU2500
+ 7284 0030 0021     		movs	r1, #0
+ 7285 0032 6164     		str	r1, [r4, #68]
+3409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7286              		.loc 1 3409 5 is_stmt 1 discriminator 2 view .LVU2501
+3409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7287              		.loc 1 3409 23 is_stmt 0 discriminator 2 view .LVU2502
+ 7288 0034 6262     		str	r2, [r4, #36]
+3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7289              		.loc 1 3410 5 is_stmt 1 discriminator 2 view .LVU2503
+3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7290              		.loc 1 3410 23 is_stmt 0 discriminator 2 view .LVU2504
+ 7291 0036 6385     		strh	r3, [r4, #42]	@ movhi
+3411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 7292              		.loc 1 3411 5 is_stmt 1 discriminator 2 view .LVU2505
+3411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 7293              		.loc 1 3411 23 is_stmt 0 discriminator 2 view .LVU2506
+ 7294 0038 E662     		str	r6, [r4, #44]
+3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7295              		.loc 1 3412 5 is_stmt 1 discriminator 2 view .LVU2507
+3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7296              		.loc 1 3412 23 is_stmt 0 discriminator 2 view .LVU2508
+ 7297 003a 324B     		ldr	r3, .L491
+ 7298              	.LVL485:
+3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7299              		.loc 1 3412 23 discriminator 2 view .LVU2509
+ 7300 003c 6363     		str	r3, [r4, #52]
+3415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 7301              		.loc 1 3415 5 is_stmt 1 discriminator 2 view .LVU2510
+3415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 7302              		.loc 1 3415 13 is_stmt 0 discriminator 2 view .LVU2511
+ 7303 003e 638D     		ldrh	r3, [r4, #42]
+ 7304 0040 9BB2     		uxth	r3, r3
+3415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 7305              		.loc 1 3415 8 discriminator 2 view .LVU2512
+ 7306 0042 FF2B     		cmp	r3, #255
+ 7307 0044 1BD9     		bls	.L477
+3417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7308              		.loc 1 3417 7 is_stmt 1 view .LVU2513
+3417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7309              		.loc 1 3417 22 is_stmt 0 view .LVU2514
+ 7310 0046 FF23     		movs	r3, #255
+ 7311 0048 2385     		strh	r3, [r4, #40]	@ movhi
+3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7312              		.loc 1 3418 7 is_stmt 1 view .LVU2515
+ 7313              	.LVL486:
+3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7314              		.loc 1 3418 16 is_stmt 0 view .LVU2516
+ 7315 004a 4FF08077 		mov	r7, #16777216
+ 7316              	.LVL487:
+ 7317              	.L478:
+3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ 7318              		.loc 1 3426 5 is_stmt 1 view .LVU2517
+3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ 7319              		.loc 1 3426 14 is_stmt 0 view .LVU2518
+ARM GAS  /tmp/ccVyGVF6.s 			page 303
+
+
+ 7320 004e 238D     		ldrh	r3, [r4, #40]
+3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ 7321              		.loc 1 3426 8 view .LVU2519
+ 7322 0050 CBB1     		cbz	r3, .L486
+3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ 7323              		.loc 1 3426 31 discriminator 1 view .LVU2520
+ 7324 0052 B6F1007F 		cmp	r6, #33554432
+ 7325 0056 18BF     		it	ne
+ 7326 0058 002E     		cmpne	r6, #0
+ 7327 005a 3FD1     		bne	.L487
+3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7328              		.loc 1 3431 7 is_stmt 1 view .LVU2521
+3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7329              		.loc 1 3431 11 is_stmt 0 view .LVU2522
+ 7330 005c 2368     		ldr	r3, [r4]
+3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7331              		.loc 1 3431 30 view .LVU2523
+ 7332 005e 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+ 7333              	.LVL488:
+3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7334              		.loc 1 3431 28 view .LVU2524
+ 7335 0060 9A62     		str	r2, [r3, #40]
+ 7336              	.LVL489:
+3434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7337              		.loc 1 3434 7 is_stmt 1 view .LVU2525
+3434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7338              		.loc 1 3434 11 is_stmt 0 view .LVU2526
+ 7339 0062 636A     		ldr	r3, [r4, #36]
+3434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7340              		.loc 1 3434 21 view .LVU2527
+ 7341 0064 0133     		adds	r3, r3, #1
+ 7342 0066 6362     		str	r3, [r4, #36]
+3436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 7343              		.loc 1 3436 7 is_stmt 1 view .LVU2528
+3436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 7344              		.loc 1 3436 24 is_stmt 0 view .LVU2529
+ 7345 0068 B4F82880 		ldrh	r8, [r4, #40]
+ 7346              	.LVL490:
+3437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 7347              		.loc 1 3437 7 is_stmt 1 view .LVU2530
+3437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 7348              		.loc 1 3437 11 is_stmt 0 view .LVU2531
+ 7349 006c 638D     		ldrh	r3, [r4, #42]
+ 7350 006e 9BB2     		uxth	r3, r3
+3437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 7351              		.loc 1 3437 22 view .LVU2532
+ 7352 0070 013B     		subs	r3, r3, #1
+ 7353 0072 9BB2     		uxth	r3, r3
+ 7354 0074 6385     		strh	r3, [r4, #42]	@ movhi
+3438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7355              		.loc 1 3438 7 is_stmt 1 view .LVU2533
+3438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7356              		.loc 1 3438 21 is_stmt 0 view .LVU2534
+ 7357 0076 08F1FF33 		add	r3, r8, #-1
+ 7358 007a 2385     		strh	r3, [r4, #40]	@ movhi
+ 7359 007c 05E0     		b	.L479
+ 7360              	.LVL491:
+ARM GAS  /tmp/ccVyGVF6.s 			page 304
+
+
+ 7361              	.L477:
+3422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7362              		.loc 1 3422 7 is_stmt 1 view .LVU2535
+3422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7363              		.loc 1 3422 28 is_stmt 0 view .LVU2536
+ 7364 007e 638D     		ldrh	r3, [r4, #42]
+3422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7365              		.loc 1 3422 22 view .LVU2537
+ 7366 0080 2385     		strh	r3, [r4, #40]	@ movhi
+3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7367              		.loc 1 3423 7 is_stmt 1 view .LVU2538
+3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7368              		.loc 1 3423 16 is_stmt 0 view .LVU2539
+ 7369 0082 E76A     		ldr	r7, [r4, #44]
+ 7370              	.LVL492:
+3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7371              		.loc 1 3423 16 view .LVU2540
+ 7372 0084 E3E7     		b	.L478
+ 7373              	.L486:
+3394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7374              		.loc 1 3394 12 view .LVU2541
+ 7375 0086 4FF00008 		mov	r8, #0
+ 7376              	.LVL493:
+ 7377              	.L479:
+3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7378              		.loc 1 3444 5 is_stmt 1 view .LVU2542
+3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7379              		.loc 1 3444 14 is_stmt 0 view .LVU2543
+ 7380 008a 236B     		ldr	r3, [r4, #48]
+3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7381              		.loc 1 3444 8 view .LVU2544
+ 7382 008c 112B     		cmp	r3, #17
+ 7383 008e 04D1     		bne	.L480
+3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7384              		.loc 1 3444 59 discriminator 1 view .LVU2545
+ 7385 0090 B6F52A4F 		cmp	r6, #43520
+ 7386 0094 18BF     		it	ne
+ 7387 0096 AA2E     		cmpne	r6, #170
+ 7388 0098 23D1     		bne	.L488
+ 7389              	.L480:
+3452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7390              		.loc 1 3452 7 is_stmt 1 view .LVU2546
+ 7391 009a 2046     		mov	r0, r4
+ 7392 009c FFF7FEFF 		bl	I2C_ConvertOtherXferOptions
+ 7393              	.LVL494:
+3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7394              		.loc 1 3455 7 view .LVU2547
+3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7395              		.loc 1 3455 15 is_stmt 0 view .LVU2548
+ 7396 00a0 638D     		ldrh	r3, [r4, #42]
+ 7397 00a2 9BB2     		uxth	r3, r3
+3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7398              		.loc 1 3455 10 view .LVU2549
+ 7399 00a4 FF2B     		cmp	r3, #255
+ 7400 00a6 1ED8     		bhi	.L489
+3457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7401              		.loc 1 3457 9 is_stmt 1 view .LVU2550
+ARM GAS  /tmp/ccVyGVF6.s 			page 305
+
+
+3457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7402              		.loc 1 3457 18 is_stmt 0 view .LVU2551
+ 7403 00a8 E76A     		ldr	r7, [r4, #44]
+ 7404              	.LVL495:
+3393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t sizetoxfer = 0U;
+ 7405              		.loc 1 3393 12 view .LVU2552
+ 7406 00aa 174B     		ldr	r3, .L491+4
+ 7407              	.L481:
+ 7408              	.LVL496:
+3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 7409              		.loc 1 3462 5 is_stmt 1 view .LVU2553
+3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 7410              		.loc 1 3462 8 is_stmt 0 view .LVU2554
+ 7411 00ac B6F1007F 		cmp	r6, #33554432
+ 7412 00b0 18BF     		it	ne
+ 7413 00b2 002E     		cmpne	r6, #0
+ 7414 00b4 19D1     		bne	.L482
+3464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7415              		.loc 1 3464 7 is_stmt 1 view .LVU2555
+ 7416 00b6 0093     		str	r3, [sp]
+ 7417 00b8 3B46     		mov	r3, r7
+ 7418              	.LVL497:
+3464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7419              		.loc 1 3464 7 is_stmt 0 view .LVU2556
+ 7420 00ba 5FFA88F2 		uxtb	r2, r8
+ 7421 00be 2946     		mov	r1, r5
+ 7422 00c0 2046     		mov	r0, r4
+ 7423 00c2 FFF7FEFF 		bl	I2C_TransferConfig
+ 7424              	.LVL498:
+ 7425              	.L483:
+3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7426              		.loc 1 3472 5 is_stmt 1 view .LVU2557
+3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7427              		.loc 1 3472 5 view .LVU2558
+ 7428 00c6 0025     		movs	r5, #0
+ 7429 00c8 84F84050 		strb	r5, [r4, #64]
+3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7430              		.loc 1 3472 5 view .LVU2559
+3481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7431              		.loc 1 3481 5 view .LVU2560
+ 7432 00cc 0121     		movs	r1, #1
+ 7433 00ce 2046     		mov	r0, r4
+ 7434 00d0 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 7435              	.LVL499:
+3483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 7436              		.loc 1 3483 5 view .LVU2561
+3483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 7437              		.loc 1 3483 12 is_stmt 0 view .LVU2562
+ 7438 00d4 2846     		mov	r0, r5
+ 7439              	.LVL500:
+ 7440              	.L476:
+3489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7441              		.loc 1 3489 1 view .LVU2563
+ 7442 00d6 02B0     		add	sp, sp, #8
+ 7443              	.LCFI88:
+ 7444              		.cfi_remember_state
+ 7445              		.cfi_def_cfa_offset 24
+ARM GAS  /tmp/ccVyGVF6.s 			page 306
+
+
+ 7446              		@ sp needed
+ 7447 00d8 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 7448              	.LVL501:
+ 7449              	.L487:
+ 7450              	.LCFI89:
+ 7451              		.cfi_restore_state
+3394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7452              		.loc 1 3394 12 view .LVU2564
+ 7453 00dc 4FF00008 		mov	r8, #0
+ 7454 00e0 D3E7     		b	.L479
+ 7455              	.LVL502:
+ 7456              	.L488:
+3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7457              		.loc 1 3447 19 view .LVU2565
+ 7458 00e2 0023     		movs	r3, #0
+ 7459 00e4 E2E7     		b	.L481
+ 7460              	.L489:
+3393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t sizetoxfer = 0U;
+ 7461              		.loc 1 3393 12 view .LVU2566
+ 7462 00e6 084B     		ldr	r3, .L491+4
+ 7463 00e8 E0E7     		b	.L481
+ 7464              	.LVL503:
+ 7465              	.L482:
+3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7466              		.loc 1 3468 7 is_stmt 1 view .LVU2567
+ 7467 00ea 0093     		str	r3, [sp]
+ 7468 00ec 3B46     		mov	r3, r7
+ 7469              	.LVL504:
+3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7470              		.loc 1 3468 7 is_stmt 0 view .LVU2568
+ 7471 00ee 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 7472 00f2 2946     		mov	r1, r5
+ 7473 00f4 2046     		mov	r0, r4
+ 7474 00f6 FFF7FEFF 		bl	I2C_TransferConfig
+ 7475              	.LVL505:
+3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7476              		.loc 1 3468 7 view .LVU2569
+ 7477 00fa E4E7     		b	.L483
+ 7478              	.LVL506:
+ 7479              	.L484:
+3487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 7480              		.loc 1 3487 12 view .LVU2570
+ 7481 00fc 0220     		movs	r0, #2
+ 7482 00fe EAE7     		b	.L476
+ 7483              	.LVL507:
+ 7484              	.L485:
+3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7485              		.loc 1 3402 5 view .LVU2571
+ 7486 0100 0220     		movs	r0, #2
+ 7487 0102 E8E7     		b	.L476
+ 7488              	.L492:
+ 7489              		.align	2
+ 7490              	.L491:
+ 7491 0104 00000000 		.word	I2C_Master_ISR_IT
+ 7492 0108 00200080 		.word	-2147475456
+ 7493              		.cfi_endproc
+ 7494              	.LFE164:
+ARM GAS  /tmp/ccVyGVF6.s 			page 307
+
+
+ 7496              		.section	.text.HAL_I2C_Master_Seq_Transmit_DMA,"ax",%progbits
+ 7497              		.align	1
+ 7498              		.global	HAL_I2C_Master_Seq_Transmit_DMA
+ 7499              		.syntax unified
+ 7500              		.thumb
+ 7501              		.thumb_func
+ 7502              		.fpu fpv5-d16
+ 7504              	HAL_I2C_Master_Seq_Transmit_DMA:
+ 7505              	.LVL508:
+ 7506              	.LFB165:
+3505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 7507              		.loc 1 3505 1 is_stmt 1 view -0
+ 7508              		.cfi_startproc
+ 7509              		@ args = 4, pretend = 0, frame = 0
+ 7510              		@ frame_needed = 0, uses_anonymous_args = 0
+3505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 7511              		.loc 1 3505 1 is_stmt 0 view .LVU2573
+ 7512 0000 2DE9F043 		push	{r4, r5, r6, r7, r8, r9, lr}
+ 7513              	.LCFI90:
+ 7514              		.cfi_def_cfa_offset 28
+ 7515              		.cfi_offset 4, -28
+ 7516              		.cfi_offset 5, -24
+ 7517              		.cfi_offset 6, -20
+ 7518              		.cfi_offset 7, -16
+ 7519              		.cfi_offset 8, -12
+ 7520              		.cfi_offset 9, -8
+ 7521              		.cfi_offset 14, -4
+ 7522 0004 83B0     		sub	sp, sp, #12
+ 7523              	.LCFI91:
+ 7524              		.cfi_def_cfa_offset 40
+ 7525 0006 0446     		mov	r4, r0
+ 7526 0008 0A9E     		ldr	r6, [sp, #40]
+3506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+ 7527              		.loc 1 3506 3 is_stmt 1 view .LVU2574
+3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 7528              		.loc 1 3507 3 view .LVU2575
+ 7529              	.LVL509:
+3508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t sizetoxfer = 0U;
+ 7530              		.loc 1 3508 3 view .LVU2576
+3509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7531              		.loc 1 3509 3 view .LVU2577
+3512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7532              		.loc 1 3512 3 view .LVU2578
+3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7533              		.loc 1 3514 3 view .LVU2579
+3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7534              		.loc 1 3514 11 is_stmt 0 view .LVU2580
+ 7535 000a 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 7536              	.LVL510:
+3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7537              		.loc 1 3514 11 view .LVU2581
+ 7538 000e C0B2     		uxtb	r0, r0
+3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7539              		.loc 1 3514 6 view .LVU2582
+ 7540 0010 2028     		cmp	r0, #32
+ 7541 0012 40F0D780 		bne	.L509
+ 7542 0016 0D46     		mov	r5, r1
+ARM GAS  /tmp/ccVyGVF6.s 			page 308
+
+
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7543              		.loc 1 3517 5 is_stmt 1 view .LVU2583
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7544              		.loc 1 3517 5 view .LVU2584
+ 7545 0018 94F84010 		ldrb	r1, [r4, #64]	@ zero_extendqisi2
+ 7546              	.LVL511:
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7547              		.loc 1 3517 5 is_stmt 0 view .LVU2585
+ 7548 001c 0129     		cmp	r1, #1
+ 7549 001e 00F0D580 		beq	.L510
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7550              		.loc 1 3517 5 is_stmt 1 discriminator 2 view .LVU2586
+ 7551 0022 0121     		movs	r1, #1
+ 7552 0024 84F84010 		strb	r1, [r4, #64]
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7553              		.loc 1 3517 5 discriminator 2 view .LVU2587
+3519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7554              		.loc 1 3519 5 discriminator 2 view .LVU2588
+3519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7555              		.loc 1 3519 21 is_stmt 0 discriminator 2 view .LVU2589
+ 7556 0028 2121     		movs	r1, #33
+ 7557 002a 84F84110 		strb	r1, [r4, #65]
+3520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7558              		.loc 1 3520 5 is_stmt 1 discriminator 2 view .LVU2590
+3520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7559              		.loc 1 3520 21 is_stmt 0 discriminator 2 view .LVU2591
+ 7560 002e 1021     		movs	r1, #16
+ 7561 0030 84F84210 		strb	r1, [r4, #66]
+3521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7562              		.loc 1 3521 5 is_stmt 1 discriminator 2 view .LVU2592
+3521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7563              		.loc 1 3521 21 is_stmt 0 discriminator 2 view .LVU2593
+ 7564 0034 0021     		movs	r1, #0
+ 7565 0036 6164     		str	r1, [r4, #68]
+3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7566              		.loc 1 3524 5 is_stmt 1 discriminator 2 view .LVU2594
+3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7567              		.loc 1 3524 23 is_stmt 0 discriminator 2 view .LVU2595
+ 7568 0038 6262     		str	r2, [r4, #36]
+3525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7569              		.loc 1 3525 5 is_stmt 1 discriminator 2 view .LVU2596
+3525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7570              		.loc 1 3525 23 is_stmt 0 discriminator 2 view .LVU2597
+ 7571 003a 6385     		strh	r3, [r4, #42]	@ movhi
+3526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 7572              		.loc 1 3526 5 is_stmt 1 discriminator 2 view .LVU2598
+3526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 7573              		.loc 1 3526 23 is_stmt 0 discriminator 2 view .LVU2599
+ 7574 003c E662     		str	r6, [r4, #44]
+3527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7575              		.loc 1 3527 5 is_stmt 1 discriminator 2 view .LVU2600
+3527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7576              		.loc 1 3527 23 is_stmt 0 discriminator 2 view .LVU2601
+ 7577 003e 644B     		ldr	r3, .L517
+ 7578              	.LVL512:
+3527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7579              		.loc 1 3527 23 discriminator 2 view .LVU2602
+ARM GAS  /tmp/ccVyGVF6.s 			page 309
+
+
+ 7580 0040 6363     		str	r3, [r4, #52]
+3530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 7581              		.loc 1 3530 5 is_stmt 1 discriminator 2 view .LVU2603
+3530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 7582              		.loc 1 3530 13 is_stmt 0 discriminator 2 view .LVU2604
+ 7583 0042 638D     		ldrh	r3, [r4, #42]
+ 7584 0044 9BB2     		uxth	r3, r3
+3530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 7585              		.loc 1 3530 8 discriminator 2 view .LVU2605
+ 7586 0046 FF2B     		cmp	r3, #255
+ 7587 0048 1BD9     		bls	.L495
+3532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7588              		.loc 1 3532 7 is_stmt 1 view .LVU2606
+3532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 7589              		.loc 1 3532 22 is_stmt 0 view .LVU2607
+ 7590 004a FF23     		movs	r3, #255
+ 7591 004c 2385     		strh	r3, [r4, #40]	@ movhi
+3533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7592              		.loc 1 3533 7 is_stmt 1 view .LVU2608
+ 7593              	.LVL513:
+3533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7594              		.loc 1 3533 16 is_stmt 0 view .LVU2609
+ 7595 004e 4FF08077 		mov	r7, #16777216
+ 7596              	.LVL514:
+ 7597              	.L496:
+3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ 7598              		.loc 1 3541 5 is_stmt 1 view .LVU2610
+3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ 7599              		.loc 1 3541 14 is_stmt 0 view .LVU2611
+ 7600 0052 238D     		ldrh	r3, [r4, #40]
+3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ 7601              		.loc 1 3541 8 view .LVU2612
+ 7602 0054 CBB1     		cbz	r3, .L511
+3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                   (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ 7603              		.loc 1 3541 31 discriminator 1 view .LVU2613
+ 7604 0056 B6F1007F 		cmp	r6, #33554432
+ 7605 005a 18BF     		it	ne
+ 7606 005c 002E     		cmpne	r6, #0
+ 7607 005e 29D1     		bne	.L512
+3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7608              		.loc 1 3546 7 is_stmt 1 view .LVU2614
+3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7609              		.loc 1 3546 11 is_stmt 0 view .LVU2615
+ 7610 0060 2368     		ldr	r3, [r4]
+3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7611              		.loc 1 3546 30 view .LVU2616
+ 7612 0062 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+ 7613              	.LVL515:
+3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7614              		.loc 1 3546 28 view .LVU2617
+ 7615 0064 9A62     		str	r2, [r3, #40]
+ 7616              	.LVL516:
+3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7617              		.loc 1 3549 7 is_stmt 1 view .LVU2618
+3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7618              		.loc 1 3549 11 is_stmt 0 view .LVU2619
+ 7619 0066 636A     		ldr	r3, [r4, #36]
+ARM GAS  /tmp/ccVyGVF6.s 			page 310
+
+
+3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7620              		.loc 1 3549 21 view .LVU2620
+ 7621 0068 0133     		adds	r3, r3, #1
+ 7622 006a 6362     		str	r3, [r4, #36]
+3551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 7623              		.loc 1 3551 7 is_stmt 1 view .LVU2621
+3551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 7624              		.loc 1 3551 24 is_stmt 0 view .LVU2622
+ 7625 006c B4F82880 		ldrh	r8, [r4, #40]
+ 7626              	.LVL517:
+3552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 7627              		.loc 1 3552 7 is_stmt 1 view .LVU2623
+3552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 7628              		.loc 1 3552 11 is_stmt 0 view .LVU2624
+ 7629 0070 638D     		ldrh	r3, [r4, #42]
+ 7630 0072 9BB2     		uxth	r3, r3
+3552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 7631              		.loc 1 3552 22 view .LVU2625
+ 7632 0074 013B     		subs	r3, r3, #1
+ 7633 0076 9BB2     		uxth	r3, r3
+ 7634 0078 6385     		strh	r3, [r4, #42]	@ movhi
+3553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7635              		.loc 1 3553 7 is_stmt 1 view .LVU2626
+3553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7636              		.loc 1 3553 21 is_stmt 0 view .LVU2627
+ 7637 007a 08F1FF33 		add	r3, r8, #-1
+ 7638 007e 2385     		strh	r3, [r4, #40]	@ movhi
+ 7639 0080 05E0     		b	.L497
+ 7640              	.LVL518:
+ 7641              	.L495:
+3537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7642              		.loc 1 3537 7 is_stmt 1 view .LVU2628
+3537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7643              		.loc 1 3537 28 is_stmt 0 view .LVU2629
+ 7644 0082 638D     		ldrh	r3, [r4, #42]
+3537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 7645              		.loc 1 3537 22 view .LVU2630
+ 7646 0084 2385     		strh	r3, [r4, #40]	@ movhi
+3538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7647              		.loc 1 3538 7 is_stmt 1 view .LVU2631
+3538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7648              		.loc 1 3538 16 is_stmt 0 view .LVU2632
+ 7649 0086 E76A     		ldr	r7, [r4, #44]
+ 7650              	.LVL519:
+3538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7651              		.loc 1 3538 16 view .LVU2633
+ 7652 0088 E3E7     		b	.L496
+ 7653              	.L511:
+3509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7654              		.loc 1 3509 12 view .LVU2634
+ 7655 008a 4FF00008 		mov	r8, #0
+ 7656              	.LVL520:
+ 7657              	.L497:
+3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7658              		.loc 1 3559 5 is_stmt 1 view .LVU2635
+3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7659              		.loc 1 3559 14 is_stmt 0 view .LVU2636
+ARM GAS  /tmp/ccVyGVF6.s 			page 311
+
+
+ 7660 008e 236B     		ldr	r3, [r4, #48]
+3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7661              		.loc 1 3559 8 view .LVU2637
+ 7662 0090 112B     		cmp	r3, #17
+ 7663 0092 04D1     		bne	.L498
+3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 7664              		.loc 1 3559 59 discriminator 1 view .LVU2638
+ 7665 0094 B6F52A4F 		cmp	r6, #43520
+ 7666 0098 18BF     		it	ne
+ 7667 009a AA2E     		cmpne	r6, #170
+ 7668 009c 0DD1     		bne	.L513
+ 7669              	.L498:
+3567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7670              		.loc 1 3567 7 is_stmt 1 view .LVU2639
+ 7671 009e 2046     		mov	r0, r4
+ 7672 00a0 FFF7FEFF 		bl	I2C_ConvertOtherXferOptions
+ 7673              	.LVL521:
+3570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7674              		.loc 1 3570 7 view .LVU2640
+3570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7675              		.loc 1 3570 15 is_stmt 0 view .LVU2641
+ 7676 00a4 638D     		ldrh	r3, [r4, #42]
+ 7677 00a6 9BB2     		uxth	r3, r3
+3570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7678              		.loc 1 3570 10 view .LVU2642
+ 7679 00a8 FF2B     		cmp	r3, #255
+ 7680 00aa 09D8     		bhi	.L514
+3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7681              		.loc 1 3572 9 is_stmt 1 view .LVU2643
+3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7682              		.loc 1 3572 18 is_stmt 0 view .LVU2644
+ 7683 00ac E76A     		ldr	r7, [r4, #44]
+ 7684              	.LVL522:
+3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 7685              		.loc 1 3507 12 view .LVU2645
+ 7686 00ae DFF83091 		ldr	r9, .L517+16
+ 7687 00b2 07E0     		b	.L499
+ 7688              	.LVL523:
+ 7689              	.L512:
+3509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7690              		.loc 1 3509 12 view .LVU2646
+ 7691 00b4 4FF00008 		mov	r8, #0
+ 7692 00b8 E9E7     		b	.L497
+ 7693              	.LVL524:
+ 7694              	.L513:
+3562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7695              		.loc 1 3562 19 view .LVU2647
+ 7696 00ba 4FF00009 		mov	r9, #0
+ 7697 00be 01E0     		b	.L499
+ 7698              	.L514:
+3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 7699              		.loc 1 3507 12 view .LVU2648
+ 7700 00c0 DFF81C91 		ldr	r9, .L517+16
+ 7701              	.L499:
+ 7702              	.LVL525:
+3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 7703              		.loc 1 3576 5 is_stmt 1 view .LVU2649
+ARM GAS  /tmp/ccVyGVF6.s 			page 312
+
+
+3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 7704              		.loc 1 3576 13 is_stmt 0 view .LVU2650
+ 7705 00c4 228D     		ldrh	r2, [r4, #40]
+3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 7706              		.loc 1 3576 8 view .LVU2651
+ 7707 00c6 002A     		cmp	r2, #0
+ 7708 00c8 5AD0     		beq	.L500
+3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7709              		.loc 1 3578 7 is_stmt 1 view .LVU2652
+3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7710              		.loc 1 3578 15 is_stmt 0 view .LVU2653
+ 7711 00ca A36B     		ldr	r3, [r4, #56]
+3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7712              		.loc 1 3578 10 view .LVU2654
+ 7713 00cc FBB1     		cbz	r3, .L501
+3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7714              		.loc 1 3581 9 is_stmt 1 view .LVU2655
+3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7715              		.loc 1 3581 40 is_stmt 0 view .LVU2656
+ 7716 00ce 414A     		ldr	r2, .L517+4
+ 7717 00d0 DA63     		str	r2, [r3, #60]
+3584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7718              		.loc 1 3584 9 is_stmt 1 view .LVU2657
+3584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7719              		.loc 1 3584 13 is_stmt 0 view .LVU2658
+ 7720 00d2 A36B     		ldr	r3, [r4, #56]
+3584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7721              		.loc 1 3584 41 view .LVU2659
+ 7722 00d4 404A     		ldr	r2, .L517+8
+ 7723 00d6 DA64     		str	r2, [r3, #76]
+3587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 7724              		.loc 1 3587 9 is_stmt 1 view .LVU2660
+3587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 7725              		.loc 1 3587 13 is_stmt 0 view .LVU2661
+ 7726 00d8 A26B     		ldr	r2, [r4, #56]
+3587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmatx->XferAbortCallback = NULL;
+ 7727              		.loc 1 3587 44 view .LVU2662
+ 7728 00da 0023     		movs	r3, #0
+ 7729 00dc 1364     		str	r3, [r2, #64]
+3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7730              		.loc 1 3588 9 is_stmt 1 view .LVU2663
+3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7731              		.loc 1 3588 13 is_stmt 0 view .LVU2664
+ 7732 00de A26B     		ldr	r2, [r4, #56]
+3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7733              		.loc 1 3588 41 view .LVU2665
+ 7734 00e0 1365     		str	r3, [r2, #80]
+3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ 7735              		.loc 1 3591 9 is_stmt 1 view .LVU2666
+3592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7736              		.loc 1 3592 57 is_stmt 0 view .LVU2667
+ 7737 00e2 2268     		ldr	r2, [r4]
+3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ 7738              		.loc 1 3591 25 view .LVU2668
+ 7739 00e4 238D     		ldrh	r3, [r4, #40]
+ 7740 00e6 2832     		adds	r2, r2, #40
+ 7741 00e8 616A     		ldr	r1, [r4, #36]
+ARM GAS  /tmp/ccVyGVF6.s 			page 313
+
+
+ 7742 00ea A06B     		ldr	r0, [r4, #56]
+ 7743 00ec FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 7744              	.LVL526:
+3609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7745              		.loc 1 3609 7 is_stmt 1 view .LVU2669
+3609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7746              		.loc 1 3609 10 is_stmt 0 view .LVU2670
+ 7747 00f0 D8B1     		cbz	r0, .L502
+3639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7748              		.loc 1 3639 9 is_stmt 1 view .LVU2671
+3639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7749              		.loc 1 3639 25 is_stmt 0 view .LVU2672
+ 7750 00f2 2023     		movs	r3, #32
+ 7751 00f4 84F84130 		strb	r3, [r4, #65]
+3640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7752              		.loc 1 3640 9 is_stmt 1 view .LVU2673
+3640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7753              		.loc 1 3640 25 is_stmt 0 view .LVU2674
+ 7754 00f8 0022     		movs	r2, #0
+ 7755 00fa 84F84220 		strb	r2, [r4, #66]
+3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7756              		.loc 1 3643 9 is_stmt 1 view .LVU2675
+3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7757              		.loc 1 3643 25 is_stmt 0 view .LVU2676
+ 7758 00fe 636C     		ldr	r3, [r4, #68]
+ 7759 0100 43F01003 		orr	r3, r3, #16
+ 7760 0104 6364     		str	r3, [r4, #68]
+3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7761              		.loc 1 3646 9 is_stmt 1 view .LVU2677
+3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7762              		.loc 1 3646 9 view .LVU2678
+ 7763 0106 84F84020 		strb	r2, [r4, #64]
+3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7764              		.loc 1 3646 9 view .LVU2679
+3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7765              		.loc 1 3648 9 view .LVU2680
+3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7766              		.loc 1 3648 16 is_stmt 0 view .LVU2681
+ 7767 010a 0120     		movs	r0, #1
+ 7768              	.LVL527:
+3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7769              		.loc 1 3648 16 view .LVU2682
+ 7770 010c 5BE0     		b	.L494
+ 7771              	.L501:
+3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7772              		.loc 1 3597 9 is_stmt 1 view .LVU2683
+3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 7773              		.loc 1 3597 25 is_stmt 0 view .LVU2684
+ 7774 010e 2023     		movs	r3, #32
+ 7775 0110 84F84130 		strb	r3, [r4, #65]
+3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7776              		.loc 1 3598 9 is_stmt 1 view .LVU2685
+3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7777              		.loc 1 3598 25 is_stmt 0 view .LVU2686
+ 7778 0114 0022     		movs	r2, #0
+ 7779 0116 84F84220 		strb	r2, [r4, #66]
+3601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 314
+
+
+ 7780              		.loc 1 3601 9 is_stmt 1 view .LVU2687
+3601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7781              		.loc 1 3601 25 is_stmt 0 view .LVU2688
+ 7782 011a 636C     		ldr	r3, [r4, #68]
+ 7783 011c 43F08003 		orr	r3, r3, #128
+ 7784 0120 6364     		str	r3, [r4, #68]
+3604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7785              		.loc 1 3604 9 is_stmt 1 view .LVU2689
+3604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7786              		.loc 1 3604 9 view .LVU2690
+ 7787 0122 84F84020 		strb	r2, [r4, #64]
+3604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7788              		.loc 1 3604 9 view .LVU2691
+3606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7789              		.loc 1 3606 9 view .LVU2692
+3606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7790              		.loc 1 3606 16 is_stmt 0 view .LVU2693
+ 7791 0126 0120     		movs	r0, #1
+ 7792 0128 4DE0     		b	.L494
+ 7793              	.LVL528:
+ 7794              	.L502:
+3612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 7795              		.loc 1 3612 9 is_stmt 1 view .LVU2694
+3612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 7796              		.loc 1 3612 12 is_stmt 0 view .LVU2695
+ 7797 012a B6F1007F 		cmp	r6, #33554432
+ 7798 012e 18BF     		it	ne
+ 7799 0130 002E     		cmpne	r6, #0
+ 7800 0132 1BD1     		bne	.L504
+3614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 7801              		.loc 1 3614 11 is_stmt 1 view .LVU2696
+ 7802 0134 CDF80090 		str	r9, [sp]
+ 7803 0138 3B46     		mov	r3, r7
+ 7804 013a 5FFA88F2 		uxtb	r2, r8
+ 7805 013e 2946     		mov	r1, r5
+ 7806 0140 2046     		mov	r0, r4
+ 7807              	.LVL529:
+3614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 7808              		.loc 1 3614 11 is_stmt 0 view .LVU2697
+ 7809 0142 FFF7FEFF 		bl	I2C_TransferConfig
+ 7810              	.LVL530:
+ 7811              	.L505:
+3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7812              		.loc 1 3622 9 is_stmt 1 view .LVU2698
+3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7813              		.loc 1 3622 25 is_stmt 0 view .LVU2699
+ 7814 0146 638D     		ldrh	r3, [r4, #42]
+ 7815 0148 9BB2     		uxth	r3, r3
+3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7816              		.loc 1 3622 32 view .LVU2700
+ 7817 014a 228D     		ldrh	r2, [r4, #40]
+3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7818              		.loc 1 3622 25 view .LVU2701
+ 7819 014c 9B1A     		subs	r3, r3, r2
+ 7820 014e 9BB2     		uxth	r3, r3
+ 7821 0150 6385     		strh	r3, [r4, #42]	@ movhi
+3625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 315
+
+
+ 7822              		.loc 1 3625 9 is_stmt 1 view .LVU2702
+3625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7823              		.loc 1 3625 9 view .LVU2703
+ 7824 0152 0023     		movs	r3, #0
+ 7825 0154 84F84030 		strb	r3, [r4, #64]
+3625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7826              		.loc 1 3625 9 view .LVU2704
+3631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7827              		.loc 1 3631 9 view .LVU2705
+ 7828 0158 1021     		movs	r1, #16
+ 7829 015a 2046     		mov	r0, r4
+ 7830 015c FFF7FEFF 		bl	I2C_Enable_IRQ
+ 7831              	.LVL531:
+3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7832              		.loc 1 3634 9 view .LVU2706
+3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7833              		.loc 1 3634 13 is_stmt 0 view .LVU2707
+ 7834 0160 2268     		ldr	r2, [r4]
+3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7835              		.loc 1 3634 29 view .LVU2708
+ 7836 0162 1368     		ldr	r3, [r2]
+ 7837 0164 43F48043 		orr	r3, r3, #16384
+ 7838 0168 1360     		str	r3, [r2]
+ 7839 016a 20E0     		b	.L506
+ 7840              	.LVL532:
+ 7841              	.L504:
+3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 7842              		.loc 1 3618 11 is_stmt 1 view .LVU2709
+ 7843 016c CDF80090 		str	r9, [sp]
+ 7844 0170 3B46     		mov	r3, r7
+ 7845 0172 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 7846 0176 2946     		mov	r1, r5
+ 7847 0178 2046     		mov	r0, r4
+ 7848              	.LVL533:
+3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 7849              		.loc 1 3618 11 is_stmt 0 view .LVU2710
+ 7850 017a FFF7FEFF 		bl	I2C_TransferConfig
+ 7851              	.LVL534:
+ 7852 017e E2E7     		b	.L505
+ 7853              	.L500:
+3654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7854              		.loc 1 3654 7 is_stmt 1 view .LVU2711
+3654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7855              		.loc 1 3654 21 is_stmt 0 view .LVU2712
+ 7856 0180 164B     		ldr	r3, .L517+12
+ 7857 0182 6363     		str	r3, [r4, #52]
+3658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7858              		.loc 1 3658 7 is_stmt 1 view .LVU2713
+3658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 7859              		.loc 1 3658 10 is_stmt 0 view .LVU2714
+ 7860 0184 B6F1007F 		cmp	r6, #33554432
+ 7861 0188 18BF     		it	ne
+ 7862 018a 002E     		cmpne	r6, #0
+ 7863 018c 11D1     		bne	.L507
+3660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7864              		.loc 1 3660 9 is_stmt 1 view .LVU2715
+ 7865 018e CDF80090 		str	r9, [sp]
+ARM GAS  /tmp/ccVyGVF6.s 			page 316
+
+
+ 7866 0192 3B46     		mov	r3, r7
+ 7867 0194 5FFA88F2 		uxtb	r2, r8
+ 7868 0198 2946     		mov	r1, r5
+ 7869 019a 2046     		mov	r0, r4
+ 7870 019c FFF7FEFF 		bl	I2C_TransferConfig
+ 7871              	.LVL535:
+ 7872              	.L508:
+3668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7873              		.loc 1 3668 7 view .LVU2716
+3668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7874              		.loc 1 3668 7 view .LVU2717
+ 7875 01a0 0023     		movs	r3, #0
+ 7876 01a2 84F84030 		strb	r3, [r4, #64]
+3668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7877              		.loc 1 3668 7 view .LVU2718
+3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 7878              		.loc 1 3677 7 view .LVU2719
+ 7879 01a6 0121     		movs	r1, #1
+ 7880 01a8 2046     		mov	r0, r4
+ 7881 01aa FFF7FEFF 		bl	I2C_Enable_IRQ
+ 7882              	.LVL536:
+ 7883              	.L506:
+3680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 7884              		.loc 1 3680 5 view .LVU2720
+3680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 7885              		.loc 1 3680 12 is_stmt 0 view .LVU2721
+ 7886 01ae 0020     		movs	r0, #0
+ 7887 01b0 09E0     		b	.L494
+ 7888              	.L507:
+3664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 7889              		.loc 1 3664 9 is_stmt 1 view .LVU2722
+ 7890 01b2 CDF80090 		str	r9, [sp]
+ 7891 01b6 3B46     		mov	r3, r7
+ 7892 01b8 D2B2     		uxtb	r2, r2
+ 7893 01ba 2946     		mov	r1, r5
+ 7894 01bc 2046     		mov	r0, r4
+ 7895 01be FFF7FEFF 		bl	I2C_TransferConfig
+ 7896              	.LVL537:
+ 7897 01c2 EDE7     		b	.L508
+ 7898              	.LVL538:
+ 7899              	.L509:
+3684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 7900              		.loc 1 3684 12 is_stmt 0 view .LVU2723
+ 7901 01c4 0220     		movs	r0, #2
+ 7902              	.LVL539:
+ 7903              	.L494:
+3686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7904              		.loc 1 3686 1 view .LVU2724
+ 7905 01c6 03B0     		add	sp, sp, #12
+ 7906              	.LCFI92:
+ 7907              		.cfi_remember_state
+ 7908              		.cfi_def_cfa_offset 28
+ 7909              		@ sp needed
+ 7910 01c8 BDE8F083 		pop	{r4, r5, r6, r7, r8, r9, pc}
+ 7911              	.LVL540:
+ 7912              	.L510:
+ 7913              	.LCFI93:
+ARM GAS  /tmp/ccVyGVF6.s 			page 317
+
+
+ 7914              		.cfi_restore_state
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7915              		.loc 1 3517 5 view .LVU2725
+ 7916 01cc 0220     		movs	r0, #2
+ 7917 01ce FAE7     		b	.L494
+ 7918              	.L518:
+ 7919              		.align	2
+ 7920              	.L517:
+ 7921 01d0 00000000 		.word	I2C_Master_ISR_DMA
+ 7922 01d4 00000000 		.word	I2C_DMAMasterTransmitCplt
+ 7923 01d8 00000000 		.word	I2C_DMAError
+ 7924 01dc 00000000 		.word	I2C_Master_ISR_IT
+ 7925 01e0 00200080 		.word	-2147475456
+ 7926              		.cfi_endproc
+ 7927              	.LFE165:
+ 7929              		.section	.text.HAL_I2C_Master_Seq_Receive_IT,"ax",%progbits
+ 7930              		.align	1
+ 7931              		.global	HAL_I2C_Master_Seq_Receive_IT
+ 7932              		.syntax unified
+ 7933              		.thumb
+ 7934              		.thumb_func
+ 7935              		.fpu fpv5-d16
+ 7937              	HAL_I2C_Master_Seq_Receive_IT:
+ 7938              	.LVL541:
+ 7939              	.LFB166:
+3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 7940              		.loc 1 3702 1 is_stmt 1 view -0
+ 7941              		.cfi_startproc
+ 7942              		@ args = 4, pretend = 0, frame = 0
+ 7943              		@ frame_needed = 0, uses_anonymous_args = 0
+3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 7944              		.loc 1 3702 1 is_stmt 0 view .LVU2727
+ 7945 0000 70B5     		push	{r4, r5, r6, lr}
+ 7946              	.LCFI94:
+ 7947              		.cfi_def_cfa_offset 16
+ 7948              		.cfi_offset 4, -16
+ 7949              		.cfi_offset 5, -12
+ 7950              		.cfi_offset 6, -8
+ 7951              		.cfi_offset 14, -4
+ 7952 0002 82B0     		sub	sp, sp, #8
+ 7953              	.LCFI95:
+ 7954              		.cfi_def_cfa_offset 24
+ 7955 0004 0446     		mov	r4, r0
+ 7956 0006 0D46     		mov	r5, r1
+ 7957 0008 0699     		ldr	r1, [sp, #24]
+ 7958              	.LVL542:
+3703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_READ;
+ 7959              		.loc 1 3703 3 is_stmt 1 view .LVU2728
+3704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7960              		.loc 1 3704 3 view .LVU2729
+3707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7961              		.loc 1 3707 3 view .LVU2730
+3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7962              		.loc 1 3709 3 view .LVU2731
+3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7963              		.loc 1 3709 11 is_stmt 0 view .LVU2732
+ 7964 000a 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ARM GAS  /tmp/ccVyGVF6.s 			page 318
+
+
+ 7965              	.LVL543:
+3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7966              		.loc 1 3709 11 view .LVU2733
+ 7967 000e C0B2     		uxtb	r0, r0
+3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 7968              		.loc 1 3709 6 view .LVU2734
+ 7969 0010 2028     		cmp	r0, #32
+ 7970 0012 46D1     		bne	.L525
+3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7971              		.loc 1 3712 5 is_stmt 1 view .LVU2735
+3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7972              		.loc 1 3712 5 view .LVU2736
+ 7973 0014 94F84000 		ldrb	r0, [r4, #64]	@ zero_extendqisi2
+ 7974 0018 0128     		cmp	r0, #1
+ 7975 001a 44D0     		beq	.L526
+3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7976              		.loc 1 3712 5 discriminator 2 view .LVU2737
+ 7977 001c 0120     		movs	r0, #1
+ 7978 001e 84F84000 		strb	r0, [r4, #64]
+3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7979              		.loc 1 3712 5 discriminator 2 view .LVU2738
+3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7980              		.loc 1 3714 5 discriminator 2 view .LVU2739
+3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 7981              		.loc 1 3714 21 is_stmt 0 discriminator 2 view .LVU2740
+ 7982 0022 2220     		movs	r0, #34
+ 7983 0024 84F84100 		strb	r0, [r4, #65]
+3715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7984              		.loc 1 3715 5 is_stmt 1 discriminator 2 view .LVU2741
+3715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 7985              		.loc 1 3715 21 is_stmt 0 discriminator 2 view .LVU2742
+ 7986 0028 1020     		movs	r0, #16
+ 7987 002a 84F84200 		strb	r0, [r4, #66]
+3716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7988              		.loc 1 3716 5 is_stmt 1 discriminator 2 view .LVU2743
+3716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 7989              		.loc 1 3716 21 is_stmt 0 discriminator 2 view .LVU2744
+ 7990 002e 0020     		movs	r0, #0
+ 7991 0030 6064     		str	r0, [r4, #68]
+3719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7992              		.loc 1 3719 5 is_stmt 1 discriminator 2 view .LVU2745
+3719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 7993              		.loc 1 3719 23 is_stmt 0 discriminator 2 view .LVU2746
+ 7994 0032 6262     		str	r2, [r4, #36]
+3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7995              		.loc 1 3720 5 is_stmt 1 discriminator 2 view .LVU2747
+3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 7996              		.loc 1 3720 23 is_stmt 0 discriminator 2 view .LVU2748
+ 7997 0034 6385     		strh	r3, [r4, #42]	@ movhi
+3721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 7998              		.loc 1 3721 5 is_stmt 1 discriminator 2 view .LVU2749
+3721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_IT;
+ 7999              		.loc 1 3721 23 is_stmt 0 discriminator 2 view .LVU2750
+ 8000 0036 E162     		str	r1, [r4, #44]
+3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8001              		.loc 1 3722 5 is_stmt 1 discriminator 2 view .LVU2751
+3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 319
+
+
+ 8002              		.loc 1 3722 23 is_stmt 0 discriminator 2 view .LVU2752
+ 8003 0038 1C4B     		ldr	r3, .L530
+ 8004              	.LVL544:
+3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8005              		.loc 1 3722 23 discriminator 2 view .LVU2753
+ 8006 003a 6363     		str	r3, [r4, #52]
+3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8007              		.loc 1 3725 5 is_stmt 1 discriminator 2 view .LVU2754
+3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8008              		.loc 1 3725 13 is_stmt 0 discriminator 2 view .LVU2755
+ 8009 003c 638D     		ldrh	r3, [r4, #42]
+ 8010 003e 9BB2     		uxth	r3, r3
+3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8011              		.loc 1 3725 8 discriminator 2 view .LVU2756
+ 8012 0040 FF2B     		cmp	r3, #255
+ 8013 0042 26D9     		bls	.L521
+3727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 8014              		.loc 1 3727 7 is_stmt 1 view .LVU2757
+3727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 8015              		.loc 1 3727 22 is_stmt 0 view .LVU2758
+ 8016 0044 FF23     		movs	r3, #255
+ 8017 0046 2385     		strh	r3, [r4, #40]	@ movhi
+3728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8018              		.loc 1 3728 7 is_stmt 1 view .LVU2759
+ 8019              	.LVL545:
+3728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8020              		.loc 1 3728 16 is_stmt 0 view .LVU2760
+ 8021 0048 4FF08076 		mov	r6, #16777216
+ 8022              	.LVL546:
+ 8023              	.L522:
+3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 8024              		.loc 1 3739 5 is_stmt 1 view .LVU2761
+3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 8025              		.loc 1 3739 14 is_stmt 0 view .LVU2762
+ 8026 004c 236B     		ldr	r3, [r4, #48]
+3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 8027              		.loc 1 3739 8 view .LVU2763
+ 8028 004e 122B     		cmp	r3, #18
+ 8029 0050 04D1     		bne	.L523
+3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 8030              		.loc 1 3739 59 discriminator 1 view .LVU2764
+ 8031 0052 B1F52A4F 		cmp	r1, #43520
+ 8032 0056 18BF     		it	ne
+ 8033 0058 AA29     		cmpne	r1, #170
+ 8034 005a 1ED1     		bne	.L527
+ 8035              	.L523:
+3747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8036              		.loc 1 3747 7 is_stmt 1 view .LVU2765
+ 8037 005c 2046     		mov	r0, r4
+ 8038 005e FFF7FEFF 		bl	I2C_ConvertOtherXferOptions
+ 8039              	.LVL547:
+3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8040              		.loc 1 3750 7 view .LVU2766
+3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8041              		.loc 1 3750 15 is_stmt 0 view .LVU2767
+ 8042 0062 638D     		ldrh	r3, [r4, #42]
+ 8043 0064 9BB2     		uxth	r3, r3
+ARM GAS  /tmp/ccVyGVF6.s 			page 320
+
+
+3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8044              		.loc 1 3750 10 view .LVU2768
+ 8045 0066 FF2B     		cmp	r3, #255
+ 8046 0068 19D8     		bhi	.L528
+3752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8047              		.loc 1 3752 9 is_stmt 1 view .LVU2769
+3752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8048              		.loc 1 3752 18 is_stmt 0 view .LVU2770
+ 8049 006a E66A     		ldr	r6, [r4, #44]
+ 8050              	.LVL548:
+3704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8051              		.loc 1 3704 12 view .LVU2771
+ 8052 006c 104B     		ldr	r3, .L530+4
+ 8053              	.L524:
+ 8054              	.LVL549:
+3757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8055              		.loc 1 3757 5 is_stmt 1 view .LVU2772
+ 8056 006e 0093     		str	r3, [sp]
+ 8057 0070 3346     		mov	r3, r6
+ 8058              	.LVL550:
+3757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8059              		.loc 1 3757 5 is_stmt 0 view .LVU2773
+ 8060 0072 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 8061 0076 2946     		mov	r1, r5
+ 8062 0078 2046     		mov	r0, r4
+ 8063 007a FFF7FEFF 		bl	I2C_TransferConfig
+ 8064              	.LVL551:
+3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8065              		.loc 1 3760 5 is_stmt 1 view .LVU2774
+3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8066              		.loc 1 3760 5 view .LVU2775
+ 8067 007e 0025     		movs	r5, #0
+ 8068 0080 84F84050 		strb	r5, [r4, #64]
+3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8069              		.loc 1 3760 5 view .LVU2776
+3765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8070              		.loc 1 3765 5 view .LVU2777
+ 8071 0084 0221     		movs	r1, #2
+ 8072 0086 2046     		mov	r0, r4
+ 8073 0088 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 8074              	.LVL552:
+3767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 8075              		.loc 1 3767 5 view .LVU2778
+3767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 8076              		.loc 1 3767 12 is_stmt 0 view .LVU2779
+ 8077 008c 2846     		mov	r0, r5
+ 8078              	.LVL553:
+ 8079              	.L520:
+3773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8080              		.loc 1 3773 1 view .LVU2780
+ 8081 008e 02B0     		add	sp, sp, #8
+ 8082              	.LCFI96:
+ 8083              		.cfi_remember_state
+ 8084              		.cfi_def_cfa_offset 16
+ 8085              		@ sp needed
+ 8086 0090 70BD     		pop	{r4, r5, r6, pc}
+ 8087              	.LVL554:
+ARM GAS  /tmp/ccVyGVF6.s 			page 321
+
+
+ 8088              	.L521:
+ 8089              	.LCFI97:
+ 8090              		.cfi_restore_state
+3732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 8091              		.loc 1 3732 7 is_stmt 1 view .LVU2781
+3732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 8092              		.loc 1 3732 28 is_stmt 0 view .LVU2782
+ 8093 0092 638D     		ldrh	r3, [r4, #42]
+3732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 8094              		.loc 1 3732 22 view .LVU2783
+ 8095 0094 2385     		strh	r3, [r4, #40]	@ movhi
+3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8096              		.loc 1 3733 7 is_stmt 1 view .LVU2784
+3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8097              		.loc 1 3733 16 is_stmt 0 view .LVU2785
+ 8098 0096 E66A     		ldr	r6, [r4, #44]
+ 8099              	.LVL555:
+3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8100              		.loc 1 3733 16 view .LVU2786
+ 8101 0098 D8E7     		b	.L522
+ 8102              	.L527:
+3742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8103              		.loc 1 3742 19 view .LVU2787
+ 8104 009a 0023     		movs	r3, #0
+ 8105 009c E7E7     		b	.L524
+ 8106              	.LVL556:
+ 8107              	.L528:
+3704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8108              		.loc 1 3704 12 view .LVU2788
+ 8109 009e 044B     		ldr	r3, .L530+4
+ 8110 00a0 E5E7     		b	.L524
+ 8111              	.LVL557:
+ 8112              	.L525:
+3771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 8113              		.loc 1 3771 12 view .LVU2789
+ 8114 00a2 0220     		movs	r0, #2
+ 8115 00a4 F3E7     		b	.L520
+ 8116              	.L526:
+3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8117              		.loc 1 3712 5 view .LVU2790
+ 8118 00a6 0220     		movs	r0, #2
+ 8119 00a8 F1E7     		b	.L520
+ 8120              	.L531:
+ 8121 00aa 00BF     		.align	2
+ 8122              	.L530:
+ 8123 00ac 00000000 		.word	I2C_Master_ISR_IT
+ 8124 00b0 00240080 		.word	-2147474432
+ 8125              		.cfi_endproc
+ 8126              	.LFE166:
+ 8128              		.section	.text.HAL_I2C_Master_Seq_Receive_DMA,"ax",%progbits
+ 8129              		.align	1
+ 8130              		.global	HAL_I2C_Master_Seq_Receive_DMA
+ 8131              		.syntax unified
+ 8132              		.thumb
+ 8133              		.thumb_func
+ 8134              		.fpu fpv5-d16
+ 8136              	HAL_I2C_Master_Seq_Receive_DMA:
+ARM GAS  /tmp/ccVyGVF6.s 			page 322
+
+
+ 8137              	.LVL558:
+ 8138              	.LFB167:
+3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 8139              		.loc 1 3789 1 is_stmt 1 view -0
+ 8140              		.cfi_startproc
+ 8141              		@ args = 4, pretend = 0, frame = 0
+ 8142              		@ frame_needed = 0, uses_anonymous_args = 0
+3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 8143              		.loc 1 3789 1 is_stmt 0 view .LVU2792
+ 8144 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 8145              	.LCFI98:
+ 8146              		.cfi_def_cfa_offset 24
+ 8147              		.cfi_offset 4, -24
+ 8148              		.cfi_offset 5, -20
+ 8149              		.cfi_offset 6, -16
+ 8150              		.cfi_offset 7, -12
+ 8151              		.cfi_offset 8, -8
+ 8152              		.cfi_offset 14, -4
+ 8153 0004 82B0     		sub	sp, sp, #8
+ 8154              	.LCFI99:
+ 8155              		.cfi_def_cfa_offset 32
+ 8156 0006 0446     		mov	r4, r0
+ 8157 0008 1546     		mov	r5, r2
+ 8158 000a 089A     		ldr	r2, [sp, #32]
+ 8159              	.LVL559:
+3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xferrequest = I2C_GENERATE_START_READ;
+ 8160              		.loc 1 3790 3 is_stmt 1 view .LVU2793
+3791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 8161              		.loc 1 3791 3 view .LVU2794
+3792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8162              		.loc 1 3792 3 view .LVU2795
+3795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8163              		.loc 1 3795 3 view .LVU2796
+3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 8164              		.loc 1 3797 3 view .LVU2797
+3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 8165              		.loc 1 3797 11 is_stmt 0 view .LVU2798
+ 8166 000c 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 8167              	.LVL560:
+3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 8168              		.loc 1 3797 11 view .LVU2799
+ 8169 0010 C0B2     		uxtb	r0, r0
+3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 8170              		.loc 1 3797 6 view .LVU2800
+ 8171 0012 2028     		cmp	r0, #32
+ 8172 0014 40F09D80 		bne	.L543
+ 8173 0018 0E46     		mov	r6, r1
+3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8174              		.loc 1 3800 5 is_stmt 1 view .LVU2801
+3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8175              		.loc 1 3800 5 view .LVU2802
+ 8176 001a 94F84010 		ldrb	r1, [r4, #64]	@ zero_extendqisi2
+ 8177              	.LVL561:
+3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8178              		.loc 1 3800 5 is_stmt 0 view .LVU2803
+ 8179 001e 0129     		cmp	r1, #1
+ 8180 0020 00F09B80 		beq	.L544
+ARM GAS  /tmp/ccVyGVF6.s 			page 323
+
+
+3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8181              		.loc 1 3800 5 is_stmt 1 discriminator 2 view .LVU2804
+ 8182 0024 0121     		movs	r1, #1
+ 8183 0026 84F84010 		strb	r1, [r4, #64]
+3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8184              		.loc 1 3800 5 discriminator 2 view .LVU2805
+3802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 8185              		.loc 1 3802 5 discriminator 2 view .LVU2806
+3802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_MASTER;
+ 8186              		.loc 1 3802 21 is_stmt 0 discriminator 2 view .LVU2807
+ 8187 002a 2221     		movs	r1, #34
+ 8188 002c 84F84110 		strb	r1, [r4, #65]
+3803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8189              		.loc 1 3803 5 is_stmt 1 discriminator 2 view .LVU2808
+3803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8190              		.loc 1 3803 21 is_stmt 0 discriminator 2 view .LVU2809
+ 8191 0030 1021     		movs	r1, #16
+ 8192 0032 84F84210 		strb	r1, [r4, #66]
+3804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8193              		.loc 1 3804 5 is_stmt 1 discriminator 2 view .LVU2810
+3804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8194              		.loc 1 3804 21 is_stmt 0 discriminator 2 view .LVU2811
+ 8195 0036 0021     		movs	r1, #0
+ 8196 0038 6164     		str	r1, [r4, #68]
+3807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8197              		.loc 1 3807 5 is_stmt 1 discriminator 2 view .LVU2812
+3807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8198              		.loc 1 3807 23 is_stmt 0 discriminator 2 view .LVU2813
+ 8199 003a 6562     		str	r5, [r4, #36]
+3808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8200              		.loc 1 3808 5 is_stmt 1 discriminator 2 view .LVU2814
+3808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8201              		.loc 1 3808 23 is_stmt 0 discriminator 2 view .LVU2815
+ 8202 003c 6385     		strh	r3, [r4, #42]	@ movhi
+3809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 8203              		.loc 1 3809 5 is_stmt 1 discriminator 2 view .LVU2816
+3809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Master_ISR_DMA;
+ 8204              		.loc 1 3809 23 is_stmt 0 discriminator 2 view .LVU2817
+ 8205 003e E262     		str	r2, [r4, #44]
+3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8206              		.loc 1 3810 5 is_stmt 1 discriminator 2 view .LVU2818
+3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8207              		.loc 1 3810 23 is_stmt 0 discriminator 2 view .LVU2819
+ 8208 0040 474B     		ldr	r3, .L550
+ 8209              	.LVL562:
+3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8210              		.loc 1 3810 23 discriminator 2 view .LVU2820
+ 8211 0042 6363     		str	r3, [r4, #52]
+3813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8212              		.loc 1 3813 5 is_stmt 1 discriminator 2 view .LVU2821
+3813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8213              		.loc 1 3813 13 is_stmt 0 discriminator 2 view .LVU2822
+ 8214 0044 638D     		ldrh	r3, [r4, #42]
+ 8215 0046 9BB2     		uxth	r3, r3
+3813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8216              		.loc 1 3813 8 discriminator 2 view .LVU2823
+ 8217 0048 FF2B     		cmp	r3, #255
+ARM GAS  /tmp/ccVyGVF6.s 			page 324
+
+
+ 8218 004a 3AD9     		bls	.L534
+3815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 8219              		.loc 1 3815 7 is_stmt 1 view .LVU2824
+3815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = I2C_RELOAD_MODE;
+ 8220              		.loc 1 3815 22 is_stmt 0 view .LVU2825
+ 8221 004c FF23     		movs	r3, #255
+ 8222 004e 2385     		strh	r3, [r4, #40]	@ movhi
+3816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8223              		.loc 1 3816 7 is_stmt 1 view .LVU2826
+ 8224              	.LVL563:
+3816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8225              		.loc 1 3816 16 is_stmt 0 view .LVU2827
+ 8226 0050 4FF08077 		mov	r7, #16777216
+ 8227              	.LVL564:
+ 8228              	.L535:
+3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 8229              		.loc 1 3827 5 is_stmt 1 view .LVU2828
+3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 8230              		.loc 1 3827 14 is_stmt 0 view .LVU2829
+ 8231 0054 236B     		ldr	r3, [r4, #48]
+3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 8232              		.loc 1 3827 8 view .LVU2830
+ 8233 0056 122B     		cmp	r3, #18
+ 8234 0058 04D1     		bne	.L536
+3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ 8235              		.loc 1 3827 59 discriminator 1 view .LVU2831
+ 8236 005a B2F52A4F 		cmp	r2, #43520
+ 8237 005e 18BF     		it	ne
+ 8238 0060 AA2A     		cmpne	r2, #170
+ 8239 0062 32D1     		bne	.L545
+ 8240              	.L536:
+3835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8241              		.loc 1 3835 7 is_stmt 1 view .LVU2832
+ 8242 0064 2046     		mov	r0, r4
+ 8243 0066 FFF7FEFF 		bl	I2C_ConvertOtherXferOptions
+ 8244              	.LVL565:
+3838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8245              		.loc 1 3838 7 view .LVU2833
+3838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8246              		.loc 1 3838 15 is_stmt 0 view .LVU2834
+ 8247 006a 638D     		ldrh	r3, [r4, #42]
+ 8248 006c 9BB2     		uxth	r3, r3
+3838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8249              		.loc 1 3838 10 view .LVU2835
+ 8250 006e FF2B     		cmp	r3, #255
+ 8251 0070 2ED8     		bhi	.L546
+3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8252              		.loc 1 3840 9 is_stmt 1 view .LVU2836
+3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8253              		.loc 1 3840 18 is_stmt 0 view .LVU2837
+ 8254 0072 E76A     		ldr	r7, [r4, #44]
+ 8255              	.LVL566:
+3791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 8256              		.loc 1 3791 12 view .LVU2838
+ 8257 0074 DFF8F880 		ldr	r8, .L550+16
+ 8258              	.L537:
+ 8259              	.LVL567:
+ARM GAS  /tmp/ccVyGVF6.s 			page 325
+
+
+3844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8260              		.loc 1 3844 5 is_stmt 1 view .LVU2839
+3844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8261              		.loc 1 3844 13 is_stmt 0 view .LVU2840
+ 8262 0078 228D     		ldrh	r2, [r4, #40]
+3844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8263              		.loc 1 3844 8 view .LVU2841
+ 8264 007a 002A     		cmp	r2, #0
+ 8265 007c 55D0     		beq	.L538
+3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8266              		.loc 1 3846 7 is_stmt 1 view .LVU2842
+3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8267              		.loc 1 3846 15 is_stmt 0 view .LVU2843
+ 8268 007e E36B     		ldr	r3, [r4, #60]
+3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8269              		.loc 1 3846 10 view .LVU2844
+ 8270 0080 4BB3     		cbz	r3, .L539
+3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8271              		.loc 1 3849 9 is_stmt 1 view .LVU2845
+3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8272              		.loc 1 3849 40 is_stmt 0 view .LVU2846
+ 8273 0082 384A     		ldr	r2, .L550+4
+ 8274 0084 DA63     		str	r2, [r3, #60]
+3852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8275              		.loc 1 3852 9 is_stmt 1 view .LVU2847
+3852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8276              		.loc 1 3852 13 is_stmt 0 view .LVU2848
+ 8277 0086 E36B     		ldr	r3, [r4, #60]
+3852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8278              		.loc 1 3852 41 view .LVU2849
+ 8279 0088 374A     		ldr	r2, .L550+8
+ 8280 008a DA64     		str	r2, [r3, #76]
+3855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 8281              		.loc 1 3855 9 is_stmt 1 view .LVU2850
+3855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 8282              		.loc 1 3855 13 is_stmt 0 view .LVU2851
+ 8283 008c E26B     		ldr	r2, [r4, #60]
+3855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->hdmarx->XferAbortCallback = NULL;
+ 8284              		.loc 1 3855 44 view .LVU2852
+ 8285 008e 0023     		movs	r3, #0
+ 8286 0090 1364     		str	r3, [r2, #64]
+3856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8287              		.loc 1 3856 9 is_stmt 1 view .LVU2853
+3856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8288              		.loc 1 3856 13 is_stmt 0 view .LVU2854
+ 8289 0092 E26B     		ldr	r2, [r4, #60]
+3856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8290              		.loc 1 3856 41 view .LVU2855
+ 8291 0094 1365     		str	r3, [r2, #80]
+3859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 8292              		.loc 1 3859 9 is_stmt 1 view .LVU2856
+3859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 8293              		.loc 1 3859 71 is_stmt 0 view .LVU2857
+ 8294 0096 2168     		ldr	r1, [r4]
+3859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                          hi2c->XferSize);
+ 8295              		.loc 1 3859 25 view .LVU2858
+ 8296 0098 238D     		ldrh	r3, [r4, #40]
+ARM GAS  /tmp/ccVyGVF6.s 			page 326
+
+
+ 8297 009a 2A46     		mov	r2, r5
+ 8298 009c 2431     		adds	r1, r1, #36
+ 8299 009e E06B     		ldr	r0, [r4, #60]
+ 8300 00a0 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 8301              	.LVL568:
+3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8302              		.loc 1 3877 7 is_stmt 1 view .LVU2859
+3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8303              		.loc 1 3877 10 is_stmt 0 view .LVU2860
+ 8304 00a4 28B3     		cbz	r0, .L549
+3900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8305              		.loc 1 3900 9 is_stmt 1 view .LVU2861
+3900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8306              		.loc 1 3900 25 is_stmt 0 view .LVU2862
+ 8307 00a6 2023     		movs	r3, #32
+ 8308 00a8 84F84130 		strb	r3, [r4, #65]
+3901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8309              		.loc 1 3901 9 is_stmt 1 view .LVU2863
+3901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8310              		.loc 1 3901 25 is_stmt 0 view .LVU2864
+ 8311 00ac 0022     		movs	r2, #0
+ 8312 00ae 84F84220 		strb	r2, [r4, #66]
+3904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8313              		.loc 1 3904 9 is_stmt 1 view .LVU2865
+3904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8314              		.loc 1 3904 25 is_stmt 0 view .LVU2866
+ 8315 00b2 636C     		ldr	r3, [r4, #68]
+ 8316 00b4 43F01003 		orr	r3, r3, #16
+ 8317 00b8 6364     		str	r3, [r4, #68]
+3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8318              		.loc 1 3907 9 is_stmt 1 view .LVU2867
+3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8319              		.loc 1 3907 9 view .LVU2868
+ 8320 00ba 84F84020 		strb	r2, [r4, #64]
+3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8321              		.loc 1 3907 9 view .LVU2869
+3909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8322              		.loc 1 3909 9 view .LVU2870
+3909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8323              		.loc 1 3909 16 is_stmt 0 view .LVU2871
+ 8324 00be 0120     		movs	r0, #1
+ 8325              	.LVL569:
+3909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8326              		.loc 1 3909 16 view .LVU2872
+ 8327 00c0 48E0     		b	.L533
+ 8328              	.LVL570:
+ 8329              	.L534:
+3820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 8330              		.loc 1 3820 7 is_stmt 1 view .LVU2873
+3820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 8331              		.loc 1 3820 28 is_stmt 0 view .LVU2874
+ 8332 00c2 638D     		ldrh	r3, [r4, #42]
+3820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       xfermode = hi2c->XferOptions;
+ 8333              		.loc 1 3820 22 view .LVU2875
+ 8334 00c4 2385     		strh	r3, [r4, #40]	@ movhi
+3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8335              		.loc 1 3821 7 is_stmt 1 view .LVU2876
+ARM GAS  /tmp/ccVyGVF6.s 			page 327
+
+
+3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8336              		.loc 1 3821 16 is_stmt 0 view .LVU2877
+ 8337 00c6 E76A     		ldr	r7, [r4, #44]
+ 8338              	.LVL571:
+3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8339              		.loc 1 3821 16 view .LVU2878
+ 8340 00c8 C4E7     		b	.L535
+ 8341              	.L545:
+3830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8342              		.loc 1 3830 19 view .LVU2879
+ 8343 00ca 4FF00008 		mov	r8, #0
+ 8344 00ce D3E7     		b	.L537
+ 8345              	.L546:
+3791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 8346              		.loc 1 3791 12 view .LVU2880
+ 8347 00d0 DFF89C80 		ldr	r8, .L550+16
+ 8348 00d4 D0E7     		b	.L537
+ 8349              	.LVL572:
+ 8350              	.L539:
+3865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8351              		.loc 1 3865 9 is_stmt 1 view .LVU2881
+3865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8352              		.loc 1 3865 25 is_stmt 0 view .LVU2882
+ 8353 00d6 2023     		movs	r3, #32
+ 8354 00d8 84F84130 		strb	r3, [r4, #65]
+3866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8355              		.loc 1 3866 9 is_stmt 1 view .LVU2883
+3866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8356              		.loc 1 3866 25 is_stmt 0 view .LVU2884
+ 8357 00dc 0022     		movs	r2, #0
+ 8358 00de 84F84220 		strb	r2, [r4, #66]
+3869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8359              		.loc 1 3869 9 is_stmt 1 view .LVU2885
+3869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8360              		.loc 1 3869 25 is_stmt 0 view .LVU2886
+ 8361 00e2 636C     		ldr	r3, [r4, #68]
+ 8362 00e4 43F08003 		orr	r3, r3, #128
+ 8363 00e8 6364     		str	r3, [r4, #68]
+3872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8364              		.loc 1 3872 9 is_stmt 1 view .LVU2887
+3872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8365              		.loc 1 3872 9 view .LVU2888
+ 8366 00ea 84F84020 		strb	r2, [r4, #64]
+3872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8367              		.loc 1 3872 9 view .LVU2889
+3874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8368              		.loc 1 3874 9 view .LVU2890
+3874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8369              		.loc 1 3874 16 is_stmt 0 view .LVU2891
+ 8370 00ee 0120     		movs	r0, #1
+ 8371 00f0 30E0     		b	.L533
+ 8372              	.LVL573:
+ 8373              	.L549:
+3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8374              		.loc 1 3880 9 is_stmt 1 view .LVU2892
+ 8375 00f2 CDF80080 		str	r8, [sp]
+ 8376 00f6 3B46     		mov	r3, r7
+ARM GAS  /tmp/ccVyGVF6.s 			page 328
+
+
+ 8377 00f8 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 8378 00fc 3146     		mov	r1, r6
+ 8379 00fe 2046     		mov	r0, r4
+ 8380              	.LVL574:
+3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8381              		.loc 1 3880 9 is_stmt 0 view .LVU2893
+ 8382 0100 FFF7FEFF 		bl	I2C_TransferConfig
+ 8383              	.LVL575:
+3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8384              		.loc 1 3883 9 is_stmt 1 view .LVU2894
+3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8385              		.loc 1 3883 25 is_stmt 0 view .LVU2895
+ 8386 0104 638D     		ldrh	r3, [r4, #42]
+ 8387 0106 9BB2     		uxth	r3, r3
+3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8388              		.loc 1 3883 32 view .LVU2896
+ 8389 0108 228D     		ldrh	r2, [r4, #40]
+3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8390              		.loc 1 3883 25 view .LVU2897
+ 8391 010a 9B1A     		subs	r3, r3, r2
+ 8392 010c 9BB2     		uxth	r3, r3
+ 8393 010e 6385     		strh	r3, [r4, #42]	@ movhi
+3886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8394              		.loc 1 3886 9 is_stmt 1 view .LVU2898
+3886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8395              		.loc 1 3886 9 view .LVU2899
+ 8396 0110 0023     		movs	r3, #0
+ 8397 0112 84F84030 		strb	r3, [r4, #64]
+3886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8398              		.loc 1 3886 9 view .LVU2900
+3892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8399              		.loc 1 3892 9 view .LVU2901
+ 8400 0116 1021     		movs	r1, #16
+ 8401 0118 2046     		mov	r0, r4
+ 8402 011a FFF7FEFF 		bl	I2C_Enable_IRQ
+ 8403              	.LVL576:
+3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8404              		.loc 1 3895 9 view .LVU2902
+3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8405              		.loc 1 3895 13 is_stmt 0 view .LVU2903
+ 8406 011e 2268     		ldr	r2, [r4]
+3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 8407              		.loc 1 3895 29 view .LVU2904
+ 8408 0120 1368     		ldr	r3, [r2]
+ 8409 0122 43F40043 		orr	r3, r3, #32768
+ 8410 0126 1360     		str	r3, [r2]
+ 8411 0128 11E0     		b	.L542
+ 8412              	.L538:
+3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8413              		.loc 1 3915 7 is_stmt 1 view .LVU2905
+3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8414              		.loc 1 3915 21 is_stmt 0 view .LVU2906
+ 8415 012a 104B     		ldr	r3, .L550+12
+ 8416 012c 6363     		str	r3, [r4, #52]
+3919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_GENERATE_START_READ);
+ 8417              		.loc 1 3919 7 is_stmt 1 view .LVU2907
+ 8418 012e 104B     		ldr	r3, .L550+16
+ARM GAS  /tmp/ccVyGVF6.s 			page 329
+
+
+ 8419 0130 0093     		str	r3, [sp]
+ 8420 0132 4FF00073 		mov	r3, #33554432
+ 8421 0136 D2B2     		uxtb	r2, r2
+ 8422 0138 3146     		mov	r1, r6
+ 8423 013a 2046     		mov	r0, r4
+ 8424 013c FFF7FEFF 		bl	I2C_TransferConfig
+ 8425              	.LVL577:
+3923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8426              		.loc 1 3923 7 view .LVU2908
+3923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8427              		.loc 1 3923 7 view .LVU2909
+ 8428 0140 0023     		movs	r3, #0
+ 8429 0142 84F84030 		strb	r3, [r4, #64]
+3923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8430              		.loc 1 3923 7 view .LVU2910
+3932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8431              		.loc 1 3932 7 view .LVU2911
+ 8432 0146 0221     		movs	r1, #2
+ 8433 0148 2046     		mov	r0, r4
+ 8434 014a FFF7FEFF 		bl	I2C_Enable_IRQ
+ 8435              	.LVL578:
+ 8436              	.L542:
+3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 8437              		.loc 1 3935 5 view .LVU2912
+3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 8438              		.loc 1 3935 12 is_stmt 0 view .LVU2913
+ 8439 014e 0020     		movs	r0, #0
+ 8440 0150 00E0     		b	.L533
+ 8441              	.LVL579:
+ 8442              	.L543:
+3939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 8443              		.loc 1 3939 12 view .LVU2914
+ 8444 0152 0220     		movs	r0, #2
+ 8445              	.LVL580:
+ 8446              	.L533:
+3941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8447              		.loc 1 3941 1 view .LVU2915
+ 8448 0154 02B0     		add	sp, sp, #8
+ 8449              	.LCFI100:
+ 8450              		.cfi_remember_state
+ 8451              		.cfi_def_cfa_offset 24
+ 8452              		@ sp needed
+ 8453 0156 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 8454              	.LVL581:
+ 8455              	.L544:
+ 8456              	.LCFI101:
+ 8457              		.cfi_restore_state
+3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8458              		.loc 1 3800 5 view .LVU2916
+ 8459 015a 0220     		movs	r0, #2
+ 8460 015c FAE7     		b	.L533
+ 8461              	.L551:
+ 8462 015e 00BF     		.align	2
+ 8463              	.L550:
+ 8464 0160 00000000 		.word	I2C_Master_ISR_DMA
+ 8465 0164 00000000 		.word	I2C_DMAMasterReceiveCplt
+ 8466 0168 00000000 		.word	I2C_DMAError
+ARM GAS  /tmp/ccVyGVF6.s 			page 330
+
+
+ 8467 016c 00000000 		.word	I2C_Master_ISR_IT
+ 8468 0170 00240080 		.word	-2147474432
+ 8469              		.cfi_endproc
+ 8470              	.LFE167:
+ 8472              		.section	.text.HAL_I2C_Slave_Seq_Transmit_IT,"ax",%progbits
+ 8473              		.align	1
+ 8474              		.global	HAL_I2C_Slave_Seq_Transmit_IT
+ 8475              		.syntax unified
+ 8476              		.thumb
+ 8477              		.thumb_func
+ 8478              		.fpu fpv5-d16
+ 8480              	HAL_I2C_Slave_Seq_Transmit_IT:
+ 8481              	.LVL582:
+ 8482              	.LFB168:
+3955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 8483              		.loc 1 3955 1 is_stmt 1 view -0
+ 8484              		.cfi_startproc
+ 8485              		@ args = 0, pretend = 0, frame = 0
+ 8486              		@ frame_needed = 0, uses_anonymous_args = 0
+3955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 8487              		.loc 1 3955 1 is_stmt 0 view .LVU2918
+ 8488 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 8489              	.LCFI102:
+ 8490              		.cfi_def_cfa_offset 24
+ 8491              		.cfi_offset 3, -24
+ 8492              		.cfi_offset 4, -20
+ 8493              		.cfi_offset 5, -16
+ 8494              		.cfi_offset 6, -12
+ 8495              		.cfi_offset 7, -8
+ 8496              		.cfi_offset 14, -4
+ 8497 0002 0446     		mov	r4, r0
+3957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8498              		.loc 1 3957 3 is_stmt 1 view .LVU2919
+3960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8499              		.loc 1 3960 3 view .LVU2920
+3962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 8500              		.loc 1 3962 3 view .LVU2921
+3962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 8501              		.loc 1 3962 22 is_stmt 0 view .LVU2922
+ 8502 0004 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 8503              	.LVL583:
+3962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 8504              		.loc 1 3962 6 view .LVU2923
+ 8505 0008 00F02800 		and	r0, r0, #40
+ 8506 000c 2828     		cmp	r0, #40
+ 8507 000e 60D1     		bne	.L557
+ 8508 0010 0F46     		mov	r7, r1
+ 8509 0012 1646     		mov	r6, r2
+ 8510 0014 1D46     		mov	r5, r3
+3964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8511              		.loc 1 3964 5 is_stmt 1 view .LVU2924
+3964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8512              		.loc 1 3964 8 is_stmt 0 view .LVU2925
+ 8513 0016 002A     		cmp	r2, #0
+ 8514 0018 18BF     		it	ne
+ 8515 001a 0029     		cmpne	r1, #0
+ 8516 001c 04D1     		bne	.L554
+ARM GAS  /tmp/ccVyGVF6.s 			page 331
+
+
+3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8517              		.loc 1 3966 7 is_stmt 1 view .LVU2926
+3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8518              		.loc 1 3966 23 is_stmt 0 view .LVU2927
+ 8519 001e 4FF40073 		mov	r3, #512
+ 8520              	.LVL584:
+3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8521              		.loc 1 3966 23 view .LVU2928
+ 8522 0022 6364     		str	r3, [r4, #68]
+3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8523              		.loc 1 3967 7 is_stmt 1 view .LVU2929
+3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8524              		.loc 1 3967 15 is_stmt 0 view .LVU2930
+ 8525 0024 0120     		movs	r0, #1
+ 8526 0026 55E0     		b	.L553
+ 8527              	.LVL585:
+ 8528              	.L554:
+3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8529              		.loc 1 3971 5 is_stmt 1 view .LVU2931
+ 8530 0028 48F20101 		movw	r1, #32769
+ 8531              	.LVL586:
+3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8532              		.loc 1 3971 5 is_stmt 0 view .LVU2932
+ 8533 002c 2046     		mov	r0, r4
+ 8534 002e FFF7FEFF 		bl	I2C_Disable_IRQ
+ 8535              	.LVL587:
+3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8536              		.loc 1 3974 5 is_stmt 1 view .LVU2933
+3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8537              		.loc 1 3974 5 view .LVU2934
+ 8538 0032 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 8539 0036 012B     		cmp	r3, #1
+ 8540 0038 4DD0     		beq	.L558
+3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8541              		.loc 1 3974 5 discriminator 2 view .LVU2935
+ 8542 003a 0123     		movs	r3, #1
+ 8543 003c 84F84030 		strb	r3, [r4, #64]
+3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8544              		.loc 1 3974 5 discriminator 2 view .LVU2936
+3978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8545              		.loc 1 3978 5 discriminator 2 view .LVU2937
+3978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8546              		.loc 1 3978 13 is_stmt 0 discriminator 2 view .LVU2938
+ 8547 0040 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 8548 0044 DBB2     		uxtb	r3, r3
+3978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8549              		.loc 1 3978 8 discriminator 2 view .LVU2939
+ 8550 0046 2A2B     		cmp	r3, #42
+ 8551 0048 28D0     		beq	.L560
+ 8552              	.L555:
+4004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8553              		.loc 1 4004 5 is_stmt 1 view .LVU2940
+4004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8554              		.loc 1 4004 21 is_stmt 0 view .LVU2941
+ 8555 004a 2923     		movs	r3, #41
+ 8556 004c 84F84130 		strb	r3, [r4, #65]
+4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ARM GAS  /tmp/ccVyGVF6.s 			page 332
+
+
+ 8557              		.loc 1 4005 5 is_stmt 1 view .LVU2942
+4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8558              		.loc 1 4005 21 is_stmt 0 view .LVU2943
+ 8559 0050 2023     		movs	r3, #32
+ 8560 0052 84F84230 		strb	r3, [r4, #66]
+4006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8561              		.loc 1 4006 5 is_stmt 1 view .LVU2944
+4006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8562              		.loc 1 4006 21 is_stmt 0 view .LVU2945
+ 8563 0056 0023     		movs	r3, #0
+ 8564 0058 6364     		str	r3, [r4, #68]
+4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8565              		.loc 1 4009 5 is_stmt 1 view .LVU2946
+4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8566              		.loc 1 4009 9 is_stmt 0 view .LVU2947
+ 8567 005a 2268     		ldr	r2, [r4]
+4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8568              		.loc 1 4009 25 view .LVU2948
+ 8569 005c 5368     		ldr	r3, [r2, #4]
+ 8570 005e 23F40043 		bic	r3, r3, #32768
+ 8571 0062 5360     		str	r3, [r2, #4]
+4012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8572              		.loc 1 4012 5 is_stmt 1 view .LVU2949
+4012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8573              		.loc 1 4012 23 is_stmt 0 view .LVU2950
+ 8574 0064 6762     		str	r7, [r4, #36]
+4013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 8575              		.loc 1 4013 5 is_stmt 1 view .LVU2951
+4013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 8576              		.loc 1 4013 23 is_stmt 0 view .LVU2952
+ 8577 0066 6685     		strh	r6, [r4, #42]	@ movhi
+4014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8578              		.loc 1 4014 5 is_stmt 1 view .LVU2953
+4014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8579              		.loc 1 4014 29 is_stmt 0 view .LVU2954
+ 8580 0068 638D     		ldrh	r3, [r4, #42]
+4014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8581              		.loc 1 4014 23 view .LVU2955
+ 8582 006a 2385     		strh	r3, [r4, #40]	@ movhi
+4015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 8583              		.loc 1 4015 5 is_stmt 1 view .LVU2956
+4015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 8584              		.loc 1 4015 23 is_stmt 0 view .LVU2957
+ 8585 006c E562     		str	r5, [r4, #44]
+4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8586              		.loc 1 4016 5 is_stmt 1 view .LVU2958
+4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8587              		.loc 1 4016 23 is_stmt 0 view .LVU2959
+ 8588 006e 1B4B     		ldr	r3, .L561
+ 8589 0070 6363     		str	r3, [r4, #52]
+4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
+ 8590              		.loc 1 4018 5 is_stmt 1 view .LVU2960
+4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
+ 8591              		.loc 1 4018 11 is_stmt 0 view .LVU2961
+ 8592 0072 2268     		ldr	r2, [r4]
+ 8593 0074 9369     		ldr	r3, [r2, #24]
+ 8594 0076 03F00803 		and	r3, r3, #8
+ARM GAS  /tmp/ccVyGVF6.s 			page 333
+
+
+ 8595              	.LVL588:
+4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8596              		.loc 1 4019 5 is_stmt 1 view .LVU2962
+4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8597              		.loc 1 4019 10 is_stmt 0 view .LVU2963
+ 8598 007a 9169     		ldr	r1, [r2, #24]
+4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8599              		.loc 1 4019 8 view .LVU2964
+ 8600 007c 11F4803F 		tst	r1, #65536
+ 8601 0080 02D0     		beq	.L556
+4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8602              		.loc 1 4019 54 discriminator 1 view .LVU2965
+ 8603 0082 0BB1     		cbz	r3, .L556
+4023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8604              		.loc 1 4023 7 is_stmt 1 view .LVU2966
+ 8605 0084 0823     		movs	r3, #8
+ 8606              	.LVL589:
+4023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8607              		.loc 1 4023 7 is_stmt 0 view .LVU2967
+ 8608 0086 D361     		str	r3, [r2, #28]
+ 8609              	.L556:
+4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8610              		.loc 1 4027 5 is_stmt 1 view .LVU2968
+4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8611              		.loc 1 4027 5 view .LVU2969
+ 8612 0088 0025     		movs	r5, #0
+ 8613              	.LVL590:
+4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8614              		.loc 1 4027 5 is_stmt 0 view .LVU2970
+ 8615 008a 84F84050 		strb	r5, [r4, #64]
+4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8616              		.loc 1 4027 5 is_stmt 1 view .LVU2971
+4033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8617              		.loc 1 4033 5 view .LVU2972
+ 8618 008e 48F20101 		movw	r1, #32769
+ 8619 0092 2046     		mov	r0, r4
+ 8620 0094 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 8621              	.LVL591:
+4035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 8622              		.loc 1 4035 5 view .LVU2973
+4035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 8623              		.loc 1 4035 12 is_stmt 0 view .LVU2974
+ 8624 0098 2846     		mov	r0, r5
+ 8625 009a 1BE0     		b	.L553
+ 8626              	.LVL592:
+ 8627              	.L560:
+3981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8628              		.loc 1 3981 7 is_stmt 1 view .LVU2975
+ 8629 009c 0221     		movs	r1, #2
+ 8630 009e 2046     		mov	r0, r4
+ 8631 00a0 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 8632              	.LVL593:
+3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8633              		.loc 1 3984 7 view .LVU2976
+3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8634              		.loc 1 3984 16 is_stmt 0 view .LVU2977
+ 8635 00a4 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/ccVyGVF6.s 			page 334
+
+
+3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8636              		.loc 1 3984 26 view .LVU2978
+ 8637 00a6 1A68     		ldr	r2, [r3]
+3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8638              		.loc 1 3984 10 view .LVU2979
+ 8639 00a8 12F4004F 		tst	r2, #32768
+ 8640 00ac CDD0     		beq	.L555
+3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8641              		.loc 1 3986 9 is_stmt 1 view .LVU2980
+3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8642              		.loc 1 3986 29 is_stmt 0 view .LVU2981
+ 8643 00ae 1A68     		ldr	r2, [r3]
+ 8644 00b0 22F40042 		bic	r2, r2, #32768
+ 8645 00b4 1A60     		str	r2, [r3]
+3988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 8646              		.loc 1 3988 9 is_stmt 1 view .LVU2982
+3988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 8647              		.loc 1 3988 17 is_stmt 0 view .LVU2983
+ 8648 00b6 E36B     		ldr	r3, [r4, #60]
+3988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 8649              		.loc 1 3988 12 view .LVU2984
+ 8650 00b8 002B     		cmp	r3, #0
+ 8651 00ba C6D0     		beq	.L555
+3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8652              		.loc 1 3992 11 is_stmt 1 view .LVU2985
+3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8653              		.loc 1 3992 43 is_stmt 0 view .LVU2986
+ 8654 00bc 084A     		ldr	r2, .L561+4
+ 8655 00be 1A65     		str	r2, [r3, #80]
+3995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 8656              		.loc 1 3995 11 is_stmt 1 view .LVU2987
+3995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 8657              		.loc 1 3995 15 is_stmt 0 view .LVU2988
+ 8658 00c0 E06B     		ldr	r0, [r4, #60]
+ 8659 00c2 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 8660              	.LVL594:
+3995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 8661              		.loc 1 3995 14 view .LVU2989
+ 8662 00c6 0028     		cmp	r0, #0
+ 8663 00c8 BFD0     		beq	.L555
+3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8664              		.loc 1 3998 13 is_stmt 1 view .LVU2990
+3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8665              		.loc 1 3998 17 is_stmt 0 view .LVU2991
+ 8666 00ca E06B     		ldr	r0, [r4, #60]
+3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8667              		.loc 1 3998 25 view .LVU2992
+ 8668 00cc 036D     		ldr	r3, [r0, #80]
+3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8669              		.loc 1 3998 13 view .LVU2993
+ 8670 00ce 9847     		blx	r3
+ 8671              	.LVL595:
+ 8672 00d0 BBE7     		b	.L555
+ 8673              	.LVL596:
+ 8674              	.L557:
+4039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 8675              		.loc 1 4039 12 view .LVU2994
+ARM GAS  /tmp/ccVyGVF6.s 			page 335
+
+
+ 8676 00d2 0120     		movs	r0, #1
+ 8677              	.LVL597:
+ 8678              	.L553:
+4041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8679              		.loc 1 4041 1 view .LVU2995
+ 8680 00d4 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 8681              	.LVL598:
+ 8682              	.L558:
+3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8683              		.loc 1 3974 5 view .LVU2996
+ 8684 00d6 0220     		movs	r0, #2
+ 8685 00d8 FCE7     		b	.L553
+ 8686              	.L562:
+ 8687 00da 00BF     		.align	2
+ 8688              	.L561:
+ 8689 00dc 00000000 		.word	I2C_Slave_ISR_IT
+ 8690 00e0 00000000 		.word	I2C_DMAAbort
+ 8691              		.cfi_endproc
+ 8692              	.LFE168:
+ 8694              		.section	.text.HAL_I2C_Slave_Seq_Transmit_DMA,"ax",%progbits
+ 8695              		.align	1
+ 8696              		.global	HAL_I2C_Slave_Seq_Transmit_DMA
+ 8697              		.syntax unified
+ 8698              		.thumb
+ 8699              		.thumb_func
+ 8700              		.fpu fpv5-d16
+ 8702              	HAL_I2C_Slave_Seq_Transmit_DMA:
+ 8703              	.LVL599:
+ 8704              	.LFB169:
+4055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 8705              		.loc 1 4055 1 is_stmt 1 view -0
+ 8706              		.cfi_startproc
+ 8707              		@ args = 0, pretend = 0, frame = 0
+ 8708              		@ frame_needed = 0, uses_anonymous_args = 0
+4055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 8709              		.loc 1 4055 1 is_stmt 0 view .LVU2998
+ 8710 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 8711              	.LCFI103:
+ 8712              		.cfi_def_cfa_offset 24
+ 8713              		.cfi_offset 3, -24
+ 8714              		.cfi_offset 4, -20
+ 8715              		.cfi_offset 5, -16
+ 8716              		.cfi_offset 6, -12
+ 8717              		.cfi_offset 7, -8
+ 8718              		.cfi_offset 14, -4
+ 8719 0002 0446     		mov	r4, r0
+4057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 8720              		.loc 1 4057 3 is_stmt 1 view .LVU2999
+4058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8721              		.loc 1 4058 3 view .LVU3000
+4061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8722              		.loc 1 4061 3 view .LVU3001
+4063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 8723              		.loc 1 4063 3 view .LVU3002
+4063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 8724              		.loc 1 4063 22 is_stmt 0 view .LVU3003
+ 8725 0004 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ARM GAS  /tmp/ccVyGVF6.s 			page 336
+
+
+ 8726              	.LVL600:
+4063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 8727              		.loc 1 4063 6 view .LVU3004
+ 8728 0008 00F02800 		and	r0, r0, #40
+ 8729 000c 2828     		cmp	r0, #40
+ 8730 000e 40F0C080 		bne	.L573
+ 8731 0012 0F46     		mov	r7, r1
+ 8732 0014 1646     		mov	r6, r2
+ 8733 0016 1D46     		mov	r5, r3
+4065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8734              		.loc 1 4065 5 is_stmt 1 view .LVU3005
+4065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8735              		.loc 1 4065 8 is_stmt 0 view .LVU3006
+ 8736 0018 002A     		cmp	r2, #0
+ 8737 001a 18BF     		it	ne
+ 8738 001c 0029     		cmpne	r1, #0
+ 8739 001e 4FD0     		beq	.L577
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8740              		.loc 1 4072 5 is_stmt 1 view .LVU3007
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8741              		.loc 1 4072 5 view .LVU3008
+ 8742 0020 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 8743              	.LVL601:
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8744              		.loc 1 4072 5 is_stmt 0 view .LVU3009
+ 8745 0024 012B     		cmp	r3, #1
+ 8746 0026 00F0B780 		beq	.L574
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8747              		.loc 1 4072 5 is_stmt 1 discriminator 2 view .LVU3010
+ 8748 002a 0123     		movs	r3, #1
+ 8749 002c 84F84030 		strb	r3, [r4, #64]
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8750              		.loc 1 4072 5 discriminator 2 view .LVU3011
+4075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8751              		.loc 1 4075 5 discriminator 2 view .LVU3012
+ 8752 0030 48F20101 		movw	r1, #32769
+ 8753              	.LVL602:
+4075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8754              		.loc 1 4075 5 is_stmt 0 discriminator 2 view .LVU3013
+ 8755 0034 2046     		mov	r0, r4
+ 8756 0036 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 8757              	.LVL603:
+4079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8758              		.loc 1 4079 5 is_stmt 1 discriminator 2 view .LVU3014
+4079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8759              		.loc 1 4079 13 is_stmt 0 discriminator 2 view .LVU3015
+ 8760 003a 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 8761 003e DBB2     		uxtb	r3, r3
+4079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8762              		.loc 1 4079 8 discriminator 2 view .LVU3016
+ 8763 0040 2A2B     		cmp	r3, #42
+ 8764 0042 42D0     		beq	.L578
+4104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8765              		.loc 1 4104 10 is_stmt 1 view .LVU3017
+4104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8766              		.loc 1 4104 18 is_stmt 0 view .LVU3018
+ 8767 0044 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ARM GAS  /tmp/ccVyGVF6.s 			page 337
+
+
+ 8768 0048 DBB2     		uxtb	r3, r3
+4104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8769              		.loc 1 4104 13 view .LVU3019
+ 8770 004a 292B     		cmp	r3, #41
+ 8771 004c 59D0     		beq	.L579
+ 8772              	.L567:
+4129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8773              		.loc 1 4129 5 is_stmt 1 view .LVU3020
+4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8774              		.loc 1 4131 5 view .LVU3021
+4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 8775              		.loc 1 4131 21 is_stmt 0 view .LVU3022
+ 8776 004e 2923     		movs	r3, #41
+ 8777 0050 84F84130 		strb	r3, [r4, #65]
+4132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8778              		.loc 1 4132 5 is_stmt 1 view .LVU3023
+4132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8779              		.loc 1 4132 21 is_stmt 0 view .LVU3024
+ 8780 0054 2023     		movs	r3, #32
+ 8781 0056 84F84230 		strb	r3, [r4, #66]
+4133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8782              		.loc 1 4133 5 is_stmt 1 view .LVU3025
+4133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8783              		.loc 1 4133 21 is_stmt 0 view .LVU3026
+ 8784 005a 0023     		movs	r3, #0
+ 8785 005c 6364     		str	r3, [r4, #68]
+4136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8786              		.loc 1 4136 5 is_stmt 1 view .LVU3027
+4136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8787              		.loc 1 4136 9 is_stmt 0 view .LVU3028
+ 8788 005e 2268     		ldr	r2, [r4]
+4136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8789              		.loc 1 4136 25 view .LVU3029
+ 8790 0060 5368     		ldr	r3, [r2, #4]
+ 8791 0062 23F40043 		bic	r3, r3, #32768
+ 8792 0066 5360     		str	r3, [r2, #4]
+4139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8793              		.loc 1 4139 5 is_stmt 1 view .LVU3030
+4139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 8794              		.loc 1 4139 23 is_stmt 0 view .LVU3031
+ 8795 0068 6762     		str	r7, [r4, #36]
+4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 8796              		.loc 1 4140 5 is_stmt 1 view .LVU3032
+4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 8797              		.loc 1 4140 23 is_stmt 0 view .LVU3033
+ 8798 006a 6685     		strh	r6, [r4, #42]	@ movhi
+4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8799              		.loc 1 4141 5 is_stmt 1 view .LVU3034
+4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8800              		.loc 1 4141 29 is_stmt 0 view .LVU3035
+ 8801 006c 638D     		ldrh	r3, [r4, #42]
+4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 8802              		.loc 1 4141 23 view .LVU3036
+ 8803 006e 2385     		strh	r3, [r4, #40]	@ movhi
+4142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 8804              		.loc 1 4142 5 is_stmt 1 view .LVU3037
+4142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ARM GAS  /tmp/ccVyGVF6.s 			page 338
+
+
+ 8805              		.loc 1 4142 23 is_stmt 0 view .LVU3038
+ 8806 0070 E562     		str	r5, [r4, #44]
+4143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8807              		.loc 1 4143 5 is_stmt 1 view .LVU3039
+4143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8808              		.loc 1 4143 23 is_stmt 0 view .LVU3040
+ 8809 0072 4A4B     		ldr	r3, .L580
+ 8810 0074 6363     		str	r3, [r4, #52]
+4145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8811              		.loc 1 4145 5 is_stmt 1 view .LVU3041
+4145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8812              		.loc 1 4145 13 is_stmt 0 view .LVU3042
+ 8813 0076 A36B     		ldr	r3, [r4, #56]
+4145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8814              		.loc 1 4145 8 view .LVU3043
+ 8815 0078 002B     		cmp	r3, #0
+ 8816 007a 59D0     		beq	.L568
+4148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8817              		.loc 1 4148 7 is_stmt 1 view .LVU3044
+4148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8818              		.loc 1 4148 38 is_stmt 0 view .LVU3045
+ 8819 007c 484A     		ldr	r2, .L580+4
+ 8820 007e DA63     		str	r2, [r3, #60]
+4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8821              		.loc 1 4151 7 is_stmt 1 view .LVU3046
+4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8822              		.loc 1 4151 11 is_stmt 0 view .LVU3047
+ 8823 0080 A36B     		ldr	r3, [r4, #56]
+4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8824              		.loc 1 4151 39 view .LVU3048
+ 8825 0082 484A     		ldr	r2, .L580+8
+ 8826 0084 DA64     		str	r2, [r3, #76]
+4154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 8827              		.loc 1 4154 7 is_stmt 1 view .LVU3049
+4154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 8828              		.loc 1 4154 11 is_stmt 0 view .LVU3050
+ 8829 0086 A26B     		ldr	r2, [r4, #56]
+4154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmatx->XferAbortCallback = NULL;
+ 8830              		.loc 1 4154 42 view .LVU3051
+ 8831 0088 0023     		movs	r3, #0
+ 8832 008a 1364     		str	r3, [r2, #64]
+4155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8833              		.loc 1 4155 7 is_stmt 1 view .LVU3052
+4155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8834              		.loc 1 4155 11 is_stmt 0 view .LVU3053
+ 8835 008c A26B     		ldr	r2, [r4, #56]
+4155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8836              		.loc 1 4155 39 view .LVU3054
+ 8837 008e 1365     		str	r3, [r2, #80]
+4158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 8838              		.loc 1 4158 7 is_stmt 1 view .LVU3055
+4158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 8839              		.loc 1 4158 86 is_stmt 0 view .LVU3056
+ 8840 0090 2268     		ldr	r2, [r4]
+4158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        hi2c->XferSize);
+ 8841              		.loc 1 4158 23 view .LVU3057
+ 8842 0092 238D     		ldrh	r3, [r4, #40]
+ARM GAS  /tmp/ccVyGVF6.s 			page 339
+
+
+ 8843 0094 2832     		adds	r2, r2, #40
+ 8844 0096 3946     		mov	r1, r7
+ 8845 0098 A06B     		ldr	r0, [r4, #56]
+ 8846 009a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 8847              	.LVL604:
+4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8848              		.loc 1 4176 5 is_stmt 1 view .LVU3058
+4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8849              		.loc 1 4176 8 is_stmt 0 view .LVU3059
+ 8850 009e 0546     		mov	r5, r0
+ 8851              	.LVL605:
+4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 8852              		.loc 1 4176 8 view .LVU3060
+ 8853 00a0 0028     		cmp	r0, #0
+ 8854 00a2 53D0     		beq	.L569
+4187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8855              		.loc 1 4187 7 is_stmt 1 view .LVU3061
+4187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8856              		.loc 1 4187 23 is_stmt 0 view .LVU3062
+ 8857 00a4 2823     		movs	r3, #40
+ 8858 00a6 84F84130 		strb	r3, [r4, #65]
+4188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8859              		.loc 1 4188 7 is_stmt 1 view .LVU3063
+4188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8860              		.loc 1 4188 23 is_stmt 0 view .LVU3064
+ 8861 00aa 0022     		movs	r2, #0
+ 8862 00ac 84F84220 		strb	r2, [r4, #66]
+4191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8863              		.loc 1 4191 7 is_stmt 1 view .LVU3065
+4191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8864              		.loc 1 4191 23 is_stmt 0 view .LVU3066
+ 8865 00b0 636C     		ldr	r3, [r4, #68]
+ 8866 00b2 43F01003 		orr	r3, r3, #16
+ 8867 00b6 6364     		str	r3, [r4, #68]
+4194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8868              		.loc 1 4194 7 is_stmt 1 view .LVU3067
+4194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8869              		.loc 1 4194 7 view .LVU3068
+ 8870 00b8 84F84020 		strb	r2, [r4, #64]
+4194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8871              		.loc 1 4194 7 view .LVU3069
+4196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8872              		.loc 1 4196 7 view .LVU3070
+4196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8873              		.loc 1 4196 14 is_stmt 0 view .LVU3071
+ 8874 00bc 0125     		movs	r5, #1
+ 8875 00be 69E0     		b	.L564
+ 8876              	.LVL606:
+ 8877              	.L577:
+4067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8878              		.loc 1 4067 7 is_stmt 1 view .LVU3072
+4067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8879              		.loc 1 4067 23 is_stmt 0 view .LVU3073
+ 8880 00c0 4FF40073 		mov	r3, #512
+ 8881              	.LVL607:
+4067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 8882              		.loc 1 4067 23 view .LVU3074
+ARM GAS  /tmp/ccVyGVF6.s 			page 340
+
+
+ 8883 00c4 6364     		str	r3, [r4, #68]
+4068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8884              		.loc 1 4068 7 is_stmt 1 view .LVU3075
+4068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8885              		.loc 1 4068 15 is_stmt 0 view .LVU3076
+ 8886 00c6 0125     		movs	r5, #1
+ 8887              	.LVL608:
+4068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8888              		.loc 1 4068 15 view .LVU3077
+ 8889 00c8 64E0     		b	.L564
+ 8890              	.LVL609:
+ 8891              	.L578:
+4082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8892              		.loc 1 4082 7 is_stmt 1 view .LVU3078
+ 8893 00ca 0221     		movs	r1, #2
+ 8894 00cc 2046     		mov	r0, r4
+ 8895 00ce FFF7FEFF 		bl	I2C_Disable_IRQ
+ 8896              	.LVL610:
+4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8897              		.loc 1 4084 7 view .LVU3079
+4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8898              		.loc 1 4084 16 is_stmt 0 view .LVU3080
+ 8899 00d2 2368     		ldr	r3, [r4]
+4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8900              		.loc 1 4084 26 view .LVU3081
+ 8901 00d4 1A68     		ldr	r2, [r3]
+4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8902              		.loc 1 4084 10 view .LVU3082
+ 8903 00d6 12F4004F 		tst	r2, #32768
+ 8904 00da B8D0     		beq	.L567
+4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 8905              		.loc 1 4087 9 is_stmt 1 view .LVU3083
+4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 8906              		.loc 1 4087 17 is_stmt 0 view .LVU3084
+ 8907 00dc E26B     		ldr	r2, [r4, #60]
+4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 8908              		.loc 1 4087 12 view .LVU3085
+ 8909 00de 002A     		cmp	r2, #0
+ 8910 00e0 B5D0     		beq	.L567
+4089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8911              		.loc 1 4089 11 is_stmt 1 view .LVU3086
+4089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8912              		.loc 1 4089 31 is_stmt 0 view .LVU3087
+ 8913 00e2 1A68     		ldr	r2, [r3]
+ 8914 00e4 22F40042 		bic	r2, r2, #32768
+ 8915 00e8 1A60     		str	r2, [r3]
+4093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8916              		.loc 1 4093 11 is_stmt 1 view .LVU3088
+4093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8917              		.loc 1 4093 15 is_stmt 0 view .LVU3089
+ 8918 00ea E36B     		ldr	r3, [r4, #60]
+4093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8919              		.loc 1 4093 43 view .LVU3090
+ 8920 00ec 2E4A     		ldr	r2, .L580+12
+ 8921 00ee 1A65     		str	r2, [r3, #80]
+4096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 8922              		.loc 1 4096 11 is_stmt 1 view .LVU3091
+ARM GAS  /tmp/ccVyGVF6.s 			page 341
+
+
+4096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 8923              		.loc 1 4096 15 is_stmt 0 view .LVU3092
+ 8924 00f0 E06B     		ldr	r0, [r4, #60]
+ 8925 00f2 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 8926              	.LVL611:
+4096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 8927              		.loc 1 4096 14 view .LVU3093
+ 8928 00f6 0028     		cmp	r0, #0
+ 8929 00f8 A9D0     		beq	.L567
+4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8930              		.loc 1 4099 13 is_stmt 1 view .LVU3094
+4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8931              		.loc 1 4099 17 is_stmt 0 view .LVU3095
+ 8932 00fa E06B     		ldr	r0, [r4, #60]
+4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8933              		.loc 1 4099 25 view .LVU3096
+ 8934 00fc 036D     		ldr	r3, [r0, #80]
+4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8935              		.loc 1 4099 13 view .LVU3097
+ 8936 00fe 9847     		blx	r3
+ 8937              	.LVL612:
+ 8938 0100 A5E7     		b	.L567
+ 8939              	.L579:
+4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8940              		.loc 1 4106 7 is_stmt 1 view .LVU3098
+4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8941              		.loc 1 4106 16 is_stmt 0 view .LVU3099
+ 8942 0102 2368     		ldr	r3, [r4]
+4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8943              		.loc 1 4106 26 view .LVU3100
+ 8944 0104 1A68     		ldr	r2, [r3]
+4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 8945              		.loc 1 4106 10 view .LVU3101
+ 8946 0106 12F4804F 		tst	r2, #16384
+ 8947 010a A0D0     		beq	.L567
+4108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8948              		.loc 1 4108 9 is_stmt 1 view .LVU3102
+4108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8949              		.loc 1 4108 29 is_stmt 0 view .LVU3103
+ 8950 010c 1A68     		ldr	r2, [r3]
+ 8951 010e 22F48042 		bic	r2, r2, #16384
+ 8952 0112 1A60     		str	r2, [r3]
+4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 8953              		.loc 1 4111 9 is_stmt 1 view .LVU3104
+4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 8954              		.loc 1 4111 17 is_stmt 0 view .LVU3105
+ 8955 0114 A36B     		ldr	r3, [r4, #56]
+4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 8956              		.loc 1 4111 12 view .LVU3106
+ 8957 0116 002B     		cmp	r3, #0
+ 8958 0118 99D0     		beq	.L567
+4115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8959              		.loc 1 4115 11 is_stmt 1 view .LVU3107
+4115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8960              		.loc 1 4115 43 is_stmt 0 view .LVU3108
+ 8961 011a 234A     		ldr	r2, .L580+12
+ 8962 011c 1A65     		str	r2, [r3, #80]
+ARM GAS  /tmp/ccVyGVF6.s 			page 342
+
+
+4118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 8963              		.loc 1 4118 11 is_stmt 1 view .LVU3109
+4118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 8964              		.loc 1 4118 15 is_stmt 0 view .LVU3110
+ 8965 011e A06B     		ldr	r0, [r4, #56]
+ 8966 0120 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 8967              	.LVL613:
+4118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 8968              		.loc 1 4118 14 view .LVU3111
+ 8969 0124 0028     		cmp	r0, #0
+ 8970 0126 92D0     		beq	.L567
+4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8971              		.loc 1 4121 13 is_stmt 1 view .LVU3112
+4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8972              		.loc 1 4121 17 is_stmt 0 view .LVU3113
+ 8973 0128 A06B     		ldr	r0, [r4, #56]
+4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8974              		.loc 1 4121 25 view .LVU3114
+ 8975 012a 036D     		ldr	r3, [r0, #80]
+4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 8976              		.loc 1 4121 13 view .LVU3115
+ 8977 012c 9847     		blx	r3
+ 8978              	.LVL614:
+ 8979 012e 8EE7     		b	.L567
+ 8980              	.L568:
+4164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8981              		.loc 1 4164 7 is_stmt 1 view .LVU3116
+4164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 8982              		.loc 1 4164 23 is_stmt 0 view .LVU3117
+ 8983 0130 2823     		movs	r3, #40
+ 8984 0132 84F84130 		strb	r3, [r4, #65]
+4165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8985              		.loc 1 4165 7 is_stmt 1 view .LVU3118
+4165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8986              		.loc 1 4165 23 is_stmt 0 view .LVU3119
+ 8987 0136 0022     		movs	r2, #0
+ 8988 0138 84F84220 		strb	r2, [r4, #66]
+4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8989              		.loc 1 4168 7 is_stmt 1 view .LVU3120
+4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8990              		.loc 1 4168 23 is_stmt 0 view .LVU3121
+ 8991 013c 636C     		ldr	r3, [r4, #68]
+ 8992 013e 43F08003 		orr	r3, r3, #128
+ 8993 0142 6364     		str	r3, [r4, #68]
+4171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8994              		.loc 1 4171 7 is_stmt 1 view .LVU3122
+4171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8995              		.loc 1 4171 7 view .LVU3123
+ 8996 0144 84F84020 		strb	r2, [r4, #64]
+4171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 8997              		.loc 1 4171 7 view .LVU3124
+4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8998              		.loc 1 4173 7 view .LVU3125
+4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 8999              		.loc 1 4173 14 is_stmt 0 view .LVU3126
+ 9000 0148 0125     		movs	r5, #1
+ 9001              	.LVL615:
+ARM GAS  /tmp/ccVyGVF6.s 			page 343
+
+
+4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9002              		.loc 1 4173 14 view .LVU3127
+ 9003 014a 23E0     		b	.L564
+ 9004              	.LVL616:
+ 9005              	.L569:
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9006              		.loc 1 4179 7 is_stmt 1 view .LVU3128
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9007              		.loc 1 4179 23 is_stmt 0 view .LVU3129
+ 9008 014c 638D     		ldrh	r3, [r4, #42]
+ 9009 014e 9BB2     		uxth	r3, r3
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9010              		.loc 1 4179 30 view .LVU3130
+ 9011 0150 228D     		ldrh	r2, [r4, #40]
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9012              		.loc 1 4179 23 view .LVU3131
+ 9013 0152 9B1A     		subs	r3, r3, r2
+ 9014 0154 9BB2     		uxth	r3, r3
+ 9015 0156 6385     		strh	r3, [r4, #42]	@ movhi
+4182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9016              		.loc 1 4182 7 is_stmt 1 view .LVU3132
+4182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9017              		.loc 1 4182 22 is_stmt 0 view .LVU3133
+ 9018 0158 0023     		movs	r3, #0
+ 9019 015a 2385     		strh	r3, [r4, #40]	@ movhi
+4199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
+ 9020              		.loc 1 4199 5 is_stmt 1 view .LVU3134
+4199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
+ 9021              		.loc 1 4199 11 is_stmt 0 view .LVU3135
+ 9022 015c 2268     		ldr	r2, [r4]
+ 9023 015e 9369     		ldr	r3, [r2, #24]
+ 9024 0160 03F00803 		and	r3, r3, #8
+ 9025              	.LVL617:
+4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9026              		.loc 1 4200 5 is_stmt 1 view .LVU3136
+4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9027              		.loc 1 4200 10 is_stmt 0 view .LVU3137
+ 9028 0164 9169     		ldr	r1, [r2, #24]
+4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9029              		.loc 1 4200 8 view .LVU3138
+ 9030 0166 11F4803F 		tst	r1, #65536
+ 9031 016a 0DD1     		bne	.L571
+ 9032              	.LVL618:
+ 9033              	.L572:
+4208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9034              		.loc 1 4208 5 is_stmt 1 view .LVU3139
+4208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9035              		.loc 1 4208 5 view .LVU3140
+ 9036 016c 0023     		movs	r3, #0
+ 9037 016e 84F84030 		strb	r3, [r4, #64]
+4208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9038              		.loc 1 4208 5 view .LVU3141
+4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9039              		.loc 1 4211 5 view .LVU3142
+4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9040              		.loc 1 4211 9 is_stmt 0 view .LVU3143
+ 9041 0172 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/ccVyGVF6.s 			page 344
+
+
+4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9042              		.loc 1 4211 25 view .LVU3144
+ 9043 0174 1368     		ldr	r3, [r2]
+ 9044 0176 43F48043 		orr	r3, r3, #16384
+ 9045 017a 1360     		str	r3, [r2]
+4217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9046              		.loc 1 4217 5 is_stmt 1 view .LVU3145
+ 9047 017c 4FF40041 		mov	r1, #32768
+ 9048 0180 2046     		mov	r0, r4
+ 9049              	.LVL619:
+4217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9050              		.loc 1 4217 5 is_stmt 0 view .LVU3146
+ 9051 0182 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 9052              	.LVL620:
+4219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9053              		.loc 1 4219 5 is_stmt 1 view .LVU3147
+4219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9054              		.loc 1 4219 12 is_stmt 0 view .LVU3148
+ 9055 0186 05E0     		b	.L564
+ 9056              	.LVL621:
+ 9057              	.L571:
+4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9058              		.loc 1 4200 54 discriminator 1 view .LVU3149
+ 9059 0188 002B     		cmp	r3, #0
+ 9060 018a EFD0     		beq	.L572
+4204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9061              		.loc 1 4204 7 is_stmt 1 view .LVU3150
+ 9062 018c 0823     		movs	r3, #8
+ 9063              	.LVL622:
+4204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9064              		.loc 1 4204 7 is_stmt 0 view .LVU3151
+ 9065 018e D361     		str	r3, [r2, #28]
+ 9066 0190 ECE7     		b	.L572
+ 9067              	.LVL623:
+ 9068              	.L573:
+4223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9069              		.loc 1 4223 12 view .LVU3152
+ 9070 0192 0125     		movs	r5, #1
+ 9071              	.LVL624:
+ 9072              	.L564:
+4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9073              		.loc 1 4225 1 view .LVU3153
+ 9074 0194 2846     		mov	r0, r5
+ 9075 0196 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 9076              	.LVL625:
+ 9077              	.L574:
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9078              		.loc 1 4072 5 view .LVU3154
+ 9079 0198 0225     		movs	r5, #2
+ 9080              	.LVL626:
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9081              		.loc 1 4072 5 view .LVU3155
+ 9082 019a FBE7     		b	.L564
+ 9083              	.L581:
+ 9084              		.align	2
+ 9085              	.L580:
+ 9086 019c 00000000 		.word	I2C_Slave_ISR_DMA
+ARM GAS  /tmp/ccVyGVF6.s 			page 345
+
+
+ 9087 01a0 00000000 		.word	I2C_DMASlaveTransmitCplt
+ 9088 01a4 00000000 		.word	I2C_DMAError
+ 9089 01a8 00000000 		.word	I2C_DMAAbort
+ 9090              		.cfi_endproc
+ 9091              	.LFE169:
+ 9093              		.section	.text.HAL_I2C_Slave_Seq_Receive_IT,"ax",%progbits
+ 9094              		.align	1
+ 9095              		.global	HAL_I2C_Slave_Seq_Receive_IT
+ 9096              		.syntax unified
+ 9097              		.thumb
+ 9098              		.thumb_func
+ 9099              		.fpu fpv5-d16
+ 9101              	HAL_I2C_Slave_Seq_Receive_IT:
+ 9102              	.LVL627:
+ 9103              	.LFB170:
+4239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 9104              		.loc 1 4239 1 is_stmt 1 view -0
+ 9105              		.cfi_startproc
+ 9106              		@ args = 0, pretend = 0, frame = 0
+ 9107              		@ frame_needed = 0, uses_anonymous_args = 0
+4239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 9108              		.loc 1 4239 1 is_stmt 0 view .LVU3157
+ 9109 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 9110              	.LCFI104:
+ 9111              		.cfi_def_cfa_offset 24
+ 9112              		.cfi_offset 3, -24
+ 9113              		.cfi_offset 4, -20
+ 9114              		.cfi_offset 5, -16
+ 9115              		.cfi_offset 6, -12
+ 9116              		.cfi_offset 7, -8
+ 9117              		.cfi_offset 14, -4
+ 9118 0002 0446     		mov	r4, r0
+4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9119              		.loc 1 4241 3 is_stmt 1 view .LVU3158
+4244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9120              		.loc 1 4244 3 view .LVU3159
+4246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9121              		.loc 1 4246 3 view .LVU3160
+4246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9122              		.loc 1 4246 22 is_stmt 0 view .LVU3161
+ 9123 0004 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 9124              	.LVL628:
+4246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9125              		.loc 1 4246 6 view .LVU3162
+ 9126 0008 00F02800 		and	r0, r0, #40
+ 9127 000c 2828     		cmp	r0, #40
+ 9128 000e 60D1     		bne	.L587
+ 9129 0010 0F46     		mov	r7, r1
+ 9130 0012 1646     		mov	r6, r2
+ 9131 0014 1D46     		mov	r5, r3
+4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9132              		.loc 1 4248 5 is_stmt 1 view .LVU3163
+4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9133              		.loc 1 4248 8 is_stmt 0 view .LVU3164
+ 9134 0016 002A     		cmp	r2, #0
+ 9135 0018 18BF     		it	ne
+ 9136 001a 0029     		cmpne	r1, #0
+ARM GAS  /tmp/ccVyGVF6.s 			page 346
+
+
+ 9137 001c 04D1     		bne	.L584
+4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 9138              		.loc 1 4250 7 is_stmt 1 view .LVU3165
+4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 9139              		.loc 1 4250 23 is_stmt 0 view .LVU3166
+ 9140 001e 4FF40073 		mov	r3, #512
+ 9141              	.LVL629:
+4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 9142              		.loc 1 4250 23 view .LVU3167
+ 9143 0022 6364     		str	r3, [r4, #68]
+4251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9144              		.loc 1 4251 7 is_stmt 1 view .LVU3168
+4251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9145              		.loc 1 4251 15 is_stmt 0 view .LVU3169
+ 9146 0024 0120     		movs	r0, #1
+ 9147 0026 55E0     		b	.L583
+ 9148              	.LVL630:
+ 9149              	.L584:
+4255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9150              		.loc 1 4255 5 is_stmt 1 view .LVU3170
+ 9151 0028 48F20201 		movw	r1, #32770
+ 9152              	.LVL631:
+4255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9153              		.loc 1 4255 5 is_stmt 0 view .LVU3171
+ 9154 002c 2046     		mov	r0, r4
+ 9155 002e FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9156              	.LVL632:
+4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9157              		.loc 1 4258 5 is_stmt 1 view .LVU3172
+4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9158              		.loc 1 4258 5 view .LVU3173
+ 9159 0032 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 9160 0036 012B     		cmp	r3, #1
+ 9161 0038 4DD0     		beq	.L588
+4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9162              		.loc 1 4258 5 discriminator 2 view .LVU3174
+ 9163 003a 0123     		movs	r3, #1
+ 9164 003c 84F84030 		strb	r3, [r4, #64]
+4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9165              		.loc 1 4258 5 discriminator 2 view .LVU3175
+4262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9166              		.loc 1 4262 5 discriminator 2 view .LVU3176
+4262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9167              		.loc 1 4262 13 is_stmt 0 discriminator 2 view .LVU3177
+ 9168 0040 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 9169 0044 DBB2     		uxtb	r3, r3
+4262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9170              		.loc 1 4262 8 discriminator 2 view .LVU3178
+ 9171 0046 292B     		cmp	r3, #41
+ 9172 0048 28D0     		beq	.L590
+ 9173              	.L585:
+4288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 9174              		.loc 1 4288 5 is_stmt 1 view .LVU3179
+4288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 9175              		.loc 1 4288 21 is_stmt 0 view .LVU3180
+ 9176 004a 2A23     		movs	r3, #42
+ 9177 004c 84F84130 		strb	r3, [r4, #65]
+ARM GAS  /tmp/ccVyGVF6.s 			page 347
+
+
+4289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 9178              		.loc 1 4289 5 is_stmt 1 view .LVU3181
+4289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 9179              		.loc 1 4289 21 is_stmt 0 view .LVU3182
+ 9180 0050 2023     		movs	r3, #32
+ 9181 0052 84F84230 		strb	r3, [r4, #66]
+4290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9182              		.loc 1 4290 5 is_stmt 1 view .LVU3183
+4290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9183              		.loc 1 4290 21 is_stmt 0 view .LVU3184
+ 9184 0056 0023     		movs	r3, #0
+ 9185 0058 6364     		str	r3, [r4, #68]
+4293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9186              		.loc 1 4293 5 is_stmt 1 view .LVU3185
+4293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9187              		.loc 1 4293 9 is_stmt 0 view .LVU3186
+ 9188 005a 2268     		ldr	r2, [r4]
+4293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9189              		.loc 1 4293 25 view .LVU3187
+ 9190 005c 5368     		ldr	r3, [r2, #4]
+ 9191 005e 23F40043 		bic	r3, r3, #32768
+ 9192 0062 5360     		str	r3, [r2, #4]
+4296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 9193              		.loc 1 4296 5 is_stmt 1 view .LVU3188
+4296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 9194              		.loc 1 4296 23 is_stmt 0 view .LVU3189
+ 9195 0064 6762     		str	r7, [r4, #36]
+4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 9196              		.loc 1 4297 5 is_stmt 1 view .LVU3190
+4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 9197              		.loc 1 4297 23 is_stmt 0 view .LVU3191
+ 9198 0066 6685     		strh	r6, [r4, #42]	@ movhi
+4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 9199              		.loc 1 4298 5 is_stmt 1 view .LVU3192
+4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 9200              		.loc 1 4298 29 is_stmt 0 view .LVU3193
+ 9201 0068 638D     		ldrh	r3, [r4, #42]
+4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 9202              		.loc 1 4298 23 view .LVU3194
+ 9203 006a 2385     		strh	r3, [r4, #40]	@ movhi
+4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 9204              		.loc 1 4299 5 is_stmt 1 view .LVU3195
+4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_IT;
+ 9205              		.loc 1 4299 23 is_stmt 0 view .LVU3196
+ 9206 006c E562     		str	r5, [r4, #44]
+4300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9207              		.loc 1 4300 5 is_stmt 1 view .LVU3197
+4300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9208              		.loc 1 4300 23 is_stmt 0 view .LVU3198
+ 9209 006e 1B4B     		ldr	r3, .L591
+ 9210 0070 6363     		str	r3, [r4, #52]
+4302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
+ 9211              		.loc 1 4302 5 is_stmt 1 view .LVU3199
+4302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
+ 9212              		.loc 1 4302 11 is_stmt 0 view .LVU3200
+ 9213 0072 2268     		ldr	r2, [r4]
+ 9214 0074 9369     		ldr	r3, [r2, #24]
+ARM GAS  /tmp/ccVyGVF6.s 			page 348
+
+
+ 9215 0076 03F00803 		and	r3, r3, #8
+ 9216              	.LVL633:
+4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9217              		.loc 1 4303 5 is_stmt 1 view .LVU3201
+4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9218              		.loc 1 4303 10 is_stmt 0 view .LVU3202
+ 9219 007a 9169     		ldr	r1, [r2, #24]
+4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9220              		.loc 1 4303 8 view .LVU3203
+ 9221 007c 11F4803F 		tst	r1, #65536
+ 9222 0080 02D1     		bne	.L586
+4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9223              		.loc 1 4303 55 discriminator 1 view .LVU3204
+ 9224 0082 0BB1     		cbz	r3, .L586
+4307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9225              		.loc 1 4307 7 is_stmt 1 view .LVU3205
+ 9226 0084 0823     		movs	r3, #8
+ 9227              	.LVL634:
+4307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9228              		.loc 1 4307 7 is_stmt 0 view .LVU3206
+ 9229 0086 D361     		str	r3, [r2, #28]
+ 9230              	.L586:
+4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9231              		.loc 1 4311 5 is_stmt 1 view .LVU3207
+4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9232              		.loc 1 4311 5 view .LVU3208
+ 9233 0088 0025     		movs	r5, #0
+ 9234              	.LVL635:
+4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9235              		.loc 1 4311 5 is_stmt 0 view .LVU3209
+ 9236 008a 84F84050 		strb	r5, [r4, #64]
+4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9237              		.loc 1 4311 5 is_stmt 1 view .LVU3210
+4317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9238              		.loc 1 4317 5 view .LVU3211
+ 9239 008e 48F20201 		movw	r1, #32770
+ 9240 0092 2046     		mov	r0, r4
+ 9241 0094 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 9242              	.LVL636:
+4319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9243              		.loc 1 4319 5 view .LVU3212
+4319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9244              		.loc 1 4319 12 is_stmt 0 view .LVU3213
+ 9245 0098 2846     		mov	r0, r5
+ 9246 009a 1BE0     		b	.L583
+ 9247              	.LVL637:
+ 9248              	.L590:
+4265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9249              		.loc 1 4265 7 is_stmt 1 view .LVU3214
+ 9250 009c 0121     		movs	r1, #1
+ 9251 009e 2046     		mov	r0, r4
+ 9252 00a0 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9253              	.LVL638:
+4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9254              		.loc 1 4267 7 view .LVU3215
+4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9255              		.loc 1 4267 16 is_stmt 0 view .LVU3216
+ARM GAS  /tmp/ccVyGVF6.s 			page 349
+
+
+ 9256 00a4 2368     		ldr	r3, [r4]
+4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9257              		.loc 1 4267 26 view .LVU3217
+ 9258 00a6 1A68     		ldr	r2, [r3]
+4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9259              		.loc 1 4267 10 view .LVU3218
+ 9260 00a8 12F4804F 		tst	r2, #16384
+ 9261 00ac CDD0     		beq	.L585
+4269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9262              		.loc 1 4269 9 is_stmt 1 view .LVU3219
+4269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9263              		.loc 1 4269 29 is_stmt 0 view .LVU3220
+ 9264 00ae 1A68     		ldr	r2, [r3]
+ 9265 00b0 22F48042 		bic	r2, r2, #16384
+ 9266 00b4 1A60     		str	r2, [r3]
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 9267              		.loc 1 4272 9 is_stmt 1 view .LVU3221
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 9268              		.loc 1 4272 17 is_stmt 0 view .LVU3222
+ 9269 00b6 A36B     		ldr	r3, [r4, #56]
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 9270              		.loc 1 4272 12 view .LVU3223
+ 9271 00b8 002B     		cmp	r3, #0
+ 9272 00ba C6D0     		beq	.L585
+4276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9273              		.loc 1 4276 11 is_stmt 1 view .LVU3224
+4276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9274              		.loc 1 4276 43 is_stmt 0 view .LVU3225
+ 9275 00bc 084A     		ldr	r2, .L591+4
+ 9276 00be 1A65     		str	r2, [r3, #80]
+4279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 9277              		.loc 1 4279 11 is_stmt 1 view .LVU3226
+4279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 9278              		.loc 1 4279 15 is_stmt 0 view .LVU3227
+ 9279 00c0 A06B     		ldr	r0, [r4, #56]
+ 9280 00c2 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 9281              	.LVL639:
+4279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 9282              		.loc 1 4279 14 view .LVU3228
+ 9283 00c6 0028     		cmp	r0, #0
+ 9284 00c8 BFD0     		beq	.L585
+4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9285              		.loc 1 4282 13 is_stmt 1 view .LVU3229
+4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9286              		.loc 1 4282 17 is_stmt 0 view .LVU3230
+ 9287 00ca A06B     		ldr	r0, [r4, #56]
+4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9288              		.loc 1 4282 25 view .LVU3231
+ 9289 00cc 036D     		ldr	r3, [r0, #80]
+4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9290              		.loc 1 4282 13 view .LVU3232
+ 9291 00ce 9847     		blx	r3
+ 9292              	.LVL640:
+ 9293 00d0 BBE7     		b	.L585
+ 9294              	.LVL641:
+ 9295              	.L587:
+4323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccVyGVF6.s 			page 350
+
+
+ 9296              		.loc 1 4323 12 view .LVU3233
+ 9297 00d2 0120     		movs	r0, #1
+ 9298              	.LVL642:
+ 9299              	.L583:
+4325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9300              		.loc 1 4325 1 view .LVU3234
+ 9301 00d4 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 9302              	.LVL643:
+ 9303              	.L588:
+4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9304              		.loc 1 4258 5 view .LVU3235
+ 9305 00d6 0220     		movs	r0, #2
+ 9306 00d8 FCE7     		b	.L583
+ 9307              	.L592:
+ 9308 00da 00BF     		.align	2
+ 9309              	.L591:
+ 9310 00dc 00000000 		.word	I2C_Slave_ISR_IT
+ 9311 00e0 00000000 		.word	I2C_DMAAbort
+ 9312              		.cfi_endproc
+ 9313              	.LFE170:
+ 9315              		.section	.text.HAL_I2C_Slave_Seq_Receive_DMA,"ax",%progbits
+ 9316              		.align	1
+ 9317              		.global	HAL_I2C_Slave_Seq_Receive_DMA
+ 9318              		.syntax unified
+ 9319              		.thumb
+ 9320              		.thumb_func
+ 9321              		.fpu fpv5-d16
+ 9323              	HAL_I2C_Slave_Seq_Receive_DMA:
+ 9324              	.LVL644:
+ 9325              	.LFB171:
+4339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 9326              		.loc 1 4339 1 is_stmt 1 view -0
+ 9327              		.cfi_startproc
+ 9328              		@ args = 0, pretend = 0, frame = 0
+ 9329              		@ frame_needed = 0, uses_anonymous_args = 0
+4339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 9330              		.loc 1 4339 1 is_stmt 0 view .LVU3237
+ 9331 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 9332              	.LCFI105:
+ 9333              		.cfi_def_cfa_offset 24
+ 9334              		.cfi_offset 3, -24
+ 9335              		.cfi_offset 4, -20
+ 9336              		.cfi_offset 5, -16
+ 9337              		.cfi_offset 6, -12
+ 9338              		.cfi_offset 7, -8
+ 9339              		.cfi_offset 14, -4
+ 9340 0002 0446     		mov	r4, r0
+4341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_StatusTypeDef dmaxferstatus;
+ 9341              		.loc 1 4341 3 is_stmt 1 view .LVU3238
+4342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9342              		.loc 1 4342 3 view .LVU3239
+4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9343              		.loc 1 4345 3 view .LVU3240
+4347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9344              		.loc 1 4347 3 view .LVU3241
+4347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9345              		.loc 1 4347 22 is_stmt 0 view .LVU3242
+ARM GAS  /tmp/ccVyGVF6.s 			page 351
+
+
+ 9346 0004 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 9347              	.LVL645:
+4347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9348              		.loc 1 4347 6 view .LVU3243
+ 9349 0008 00F02800 		and	r0, r0, #40
+ 9350 000c 2828     		cmp	r0, #40
+ 9351 000e 40F0C080 		bne	.L603
+ 9352 0012 0F46     		mov	r7, r1
+ 9353 0014 1646     		mov	r6, r2
+ 9354 0016 1D46     		mov	r5, r3
+4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9355              		.loc 1 4349 5 is_stmt 1 view .LVU3244
+4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9356              		.loc 1 4349 8 is_stmt 0 view .LVU3245
+ 9357 0018 002A     		cmp	r2, #0
+ 9358 001a 18BF     		it	ne
+ 9359 001c 0029     		cmpne	r1, #0
+ 9360 001e 04D1     		bne	.L595
+4351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 9361              		.loc 1 4351 7 is_stmt 1 view .LVU3246
+4351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 9362              		.loc 1 4351 23 is_stmt 0 view .LVU3247
+ 9363 0020 4FF40073 		mov	r3, #512
+ 9364              	.LVL646:
+4351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       return  HAL_ERROR;
+ 9365              		.loc 1 4351 23 view .LVU3248
+ 9366 0024 6364     		str	r3, [r4, #68]
+4352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9367              		.loc 1 4352 7 is_stmt 1 view .LVU3249
+4352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9368              		.loc 1 4352 15 is_stmt 0 view .LVU3250
+ 9369 0026 0125     		movs	r5, #1
+ 9370              	.LVL647:
+4352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9371              		.loc 1 4352 15 view .LVU3251
+ 9372 0028 B4E0     		b	.L594
+ 9373              	.LVL648:
+ 9374              	.L595:
+4356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9375              		.loc 1 4356 5 is_stmt 1 view .LVU3252
+ 9376 002a 48F20201 		movw	r1, #32770
+ 9377              	.LVL649:
+4356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9378              		.loc 1 4356 5 is_stmt 0 view .LVU3253
+ 9379 002e 2046     		mov	r0, r4
+ 9380 0030 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9381              	.LVL650:
+4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9382              		.loc 1 4359 5 is_stmt 1 view .LVU3254
+4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9383              		.loc 1 4359 5 view .LVU3255
+ 9384 0034 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 9385 0038 012B     		cmp	r3, #1
+ 9386 003a 00F0AD80 		beq	.L604
+4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9387              		.loc 1 4359 5 discriminator 2 view .LVU3256
+ 9388 003e 0123     		movs	r3, #1
+ARM GAS  /tmp/ccVyGVF6.s 			page 352
+
+
+ 9389 0040 84F84030 		strb	r3, [r4, #64]
+4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9390              		.loc 1 4359 5 discriminator 2 view .LVU3257
+4363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9391              		.loc 1 4363 5 discriminator 2 view .LVU3258
+4363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9392              		.loc 1 4363 13 is_stmt 0 discriminator 2 view .LVU3259
+ 9393 0044 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 9394 0048 DBB2     		uxtb	r3, r3
+4363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9395              		.loc 1 4363 8 discriminator 2 view .LVU3260
+ 9396 004a 292B     		cmp	r3, #41
+ 9397 004c 3DD0     		beq	.L607
+4388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9398              		.loc 1 4388 10 is_stmt 1 view .LVU3261
+4388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9399              		.loc 1 4388 18 is_stmt 0 view .LVU3262
+ 9400 004e 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 9401 0052 DBB2     		uxtb	r3, r3
+4388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9402              		.loc 1 4388 13 view .LVU3263
+ 9403 0054 2A2B     		cmp	r3, #42
+ 9404 0056 54D0     		beq	.L608
+ 9405              	.L597:
+4413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9406              		.loc 1 4413 5 is_stmt 1 view .LVU3264
+4415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 9407              		.loc 1 4415 5 view .LVU3265
+4415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+ 9408              		.loc 1 4415 21 is_stmt 0 view .LVU3266
+ 9409 0058 2A23     		movs	r3, #42
+ 9410 005a 84F84130 		strb	r3, [r4, #65]
+4416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 9411              		.loc 1 4416 5 is_stmt 1 view .LVU3267
+4416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 9412              		.loc 1 4416 21 is_stmt 0 view .LVU3268
+ 9413 005e 2023     		movs	r3, #32
+ 9414 0060 84F84230 		strb	r3, [r4, #66]
+4417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9415              		.loc 1 4417 5 is_stmt 1 view .LVU3269
+4417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9416              		.loc 1 4417 21 is_stmt 0 view .LVU3270
+ 9417 0064 0023     		movs	r3, #0
+ 9418 0066 6364     		str	r3, [r4, #68]
+4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9419              		.loc 1 4420 5 is_stmt 1 view .LVU3271
+4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9420              		.loc 1 4420 9 is_stmt 0 view .LVU3272
+ 9421 0068 2268     		ldr	r2, [r4]
+4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9422              		.loc 1 4420 25 view .LVU3273
+ 9423 006a 5368     		ldr	r3, [r2, #4]
+ 9424 006c 23F40043 		bic	r3, r3, #32768
+ 9425 0070 5360     		str	r3, [r2, #4]
+4423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ 9426              		.loc 1 4423 5 is_stmt 1 view .LVU3274
+4423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount   = Size;
+ARM GAS  /tmp/ccVyGVF6.s 			page 353
+
+
+ 9427              		.loc 1 4423 23 is_stmt 0 view .LVU3275
+ 9428 0072 6762     		str	r7, [r4, #36]
+4424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 9429              		.loc 1 4424 5 is_stmt 1 view .LVU3276
+4424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferSize    = hi2c->XferCount;
+ 9430              		.loc 1 4424 23 is_stmt 0 view .LVU3277
+ 9431 0074 6685     		strh	r6, [r4, #42]	@ movhi
+4425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 9432              		.loc 1 4425 5 is_stmt 1 view .LVU3278
+4425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 9433              		.loc 1 4425 29 is_stmt 0 view .LVU3279
+ 9434 0076 638D     		ldrh	r3, [r4, #42]
+4425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferOptions = XferOptions;
+ 9435              		.loc 1 4425 23 view .LVU3280
+ 9436 0078 2385     		strh	r3, [r4, #40]	@ movhi
+4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 9437              		.loc 1 4426 5 is_stmt 1 view .LVU3281
+4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR     = I2C_Slave_ISR_DMA;
+ 9438              		.loc 1 4426 23 is_stmt 0 view .LVU3282
+ 9439 007a E562     		str	r5, [r4, #44]
+4427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9440              		.loc 1 4427 5 is_stmt 1 view .LVU3283
+4427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9441              		.loc 1 4427 23 is_stmt 0 view .LVU3284
+ 9442 007c 474B     		ldr	r3, .L609
+ 9443 007e 6363     		str	r3, [r4, #52]
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9444              		.loc 1 4429 5 is_stmt 1 view .LVU3285
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9445              		.loc 1 4429 13 is_stmt 0 view .LVU3286
+ 9446 0080 E36B     		ldr	r3, [r4, #60]
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9447              		.loc 1 4429 8 view .LVU3287
+ 9448 0082 002B     		cmp	r3, #0
+ 9449 0084 54D0     		beq	.L598
+4432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9450              		.loc 1 4432 7 is_stmt 1 view .LVU3288
+4432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9451              		.loc 1 4432 38 is_stmt 0 view .LVU3289
+ 9452 0086 464A     		ldr	r2, .L609+4
+ 9453 0088 DA63     		str	r2, [r3, #60]
+4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9454              		.loc 1 4435 7 is_stmt 1 view .LVU3290
+4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9455              		.loc 1 4435 11 is_stmt 0 view .LVU3291
+ 9456 008a E36B     		ldr	r3, [r4, #60]
+4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9457              		.loc 1 4435 39 view .LVU3292
+ 9458 008c 454A     		ldr	r2, .L609+8
+ 9459 008e DA64     		str	r2, [r3, #76]
+4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 9460              		.loc 1 4438 7 is_stmt 1 view .LVU3293
+4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 9461              		.loc 1 4438 11 is_stmt 0 view .LVU3294
+ 9462 0090 E26B     		ldr	r2, [r4, #60]
+4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->hdmarx->XferAbortCallback = NULL;
+ 9463              		.loc 1 4438 42 view .LVU3295
+ARM GAS  /tmp/ccVyGVF6.s 			page 354
+
+
+ 9464 0092 0023     		movs	r3, #0
+ 9465 0094 1364     		str	r3, [r2, #64]
+4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9466              		.loc 1 4439 7 is_stmt 1 view .LVU3296
+4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9467              		.loc 1 4439 11 is_stmt 0 view .LVU3297
+ 9468 0096 E26B     		ldr	r2, [r4, #60]
+4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9469              		.loc 1 4439 39 view .LVU3298
+ 9470 0098 1365     		str	r3, [r2, #80]
+4442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        (uint32_t)pData, hi2c->XferSize);
+ 9471              		.loc 1 4442 7 is_stmt 1 view .LVU3299
+4442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        (uint32_t)pData, hi2c->XferSize);
+ 9472              		.loc 1 4442 69 is_stmt 0 view .LVU3300
+ 9473 009a 2168     		ldr	r1, [r4]
+4442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                        (uint32_t)pData, hi2c->XferSize);
+ 9474              		.loc 1 4442 23 view .LVU3301
+ 9475 009c 238D     		ldrh	r3, [r4, #40]
+ 9476 009e 3A46     		mov	r2, r7
+ 9477 00a0 2431     		adds	r1, r1, #36
+ 9478 00a2 E06B     		ldr	r0, [r4, #60]
+ 9479 00a4 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 9480              	.LVL651:
+4460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9481              		.loc 1 4460 5 is_stmt 1 view .LVU3302
+4460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9482              		.loc 1 4460 8 is_stmt 0 view .LVU3303
+ 9483 00a8 0546     		mov	r5, r0
+ 9484              	.LVL652:
+4460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9485              		.loc 1 4460 8 view .LVU3304
+ 9486 00aa 0028     		cmp	r0, #0
+ 9487 00ac 4ED0     		beq	.L599
+4471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 9488              		.loc 1 4471 7 is_stmt 1 view .LVU3305
+4471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 9489              		.loc 1 4471 23 is_stmt 0 view .LVU3306
+ 9490 00ae 2823     		movs	r3, #40
+ 9491 00b0 84F84130 		strb	r3, [r4, #65]
+4472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9492              		.loc 1 4472 7 is_stmt 1 view .LVU3307
+4472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9493              		.loc 1 4472 23 is_stmt 0 view .LVU3308
+ 9494 00b4 0022     		movs	r2, #0
+ 9495 00b6 84F84220 		strb	r2, [r4, #66]
+4475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9496              		.loc 1 4475 7 is_stmt 1 view .LVU3309
+4475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9497              		.loc 1 4475 23 is_stmt 0 view .LVU3310
+ 9498 00ba 636C     		ldr	r3, [r4, #68]
+ 9499 00bc 43F01003 		orr	r3, r3, #16
+ 9500 00c0 6364     		str	r3, [r4, #68]
+4478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9501              		.loc 1 4478 7 is_stmt 1 view .LVU3311
+4478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9502              		.loc 1 4478 7 view .LVU3312
+ 9503 00c2 84F84020 		strb	r2, [r4, #64]
+ARM GAS  /tmp/ccVyGVF6.s 			page 355
+
+
+4478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9504              		.loc 1 4478 7 view .LVU3313
+4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9505              		.loc 1 4480 7 view .LVU3314
+4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9506              		.loc 1 4480 14 is_stmt 0 view .LVU3315
+ 9507 00c6 0125     		movs	r5, #1
+ 9508 00c8 64E0     		b	.L594
+ 9509              	.LVL653:
+ 9510              	.L607:
+4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9511              		.loc 1 4366 7 is_stmt 1 view .LVU3316
+ 9512 00ca 0121     		movs	r1, #1
+ 9513 00cc 2046     		mov	r0, r4
+ 9514 00ce FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9515              	.LVL654:
+4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9516              		.loc 1 4368 7 view .LVU3317
+4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9517              		.loc 1 4368 16 is_stmt 0 view .LVU3318
+ 9518 00d2 2368     		ldr	r3, [r4]
+4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9519              		.loc 1 4368 26 view .LVU3319
+ 9520 00d4 1A68     		ldr	r2, [r3]
+4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9521              		.loc 1 4368 10 view .LVU3320
+ 9522 00d6 12F4804F 		tst	r2, #16384
+ 9523 00da BDD0     		beq	.L597
+4371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 9524              		.loc 1 4371 9 is_stmt 1 view .LVU3321
+4371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 9525              		.loc 1 4371 17 is_stmt 0 view .LVU3322
+ 9526 00dc A26B     		ldr	r2, [r4, #56]
+4371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 9527              		.loc 1 4371 12 view .LVU3323
+ 9528 00de 002A     		cmp	r2, #0
+ 9529 00e0 BAD0     		beq	.L597
+4373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9530              		.loc 1 4373 11 is_stmt 1 view .LVU3324
+4373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9531              		.loc 1 4373 31 is_stmt 0 view .LVU3325
+ 9532 00e2 1A68     		ldr	r2, [r3]
+ 9533 00e4 22F48042 		bic	r2, r2, #16384
+ 9534 00e8 1A60     		str	r2, [r3]
+4377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9535              		.loc 1 4377 11 is_stmt 1 view .LVU3326
+4377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9536              		.loc 1 4377 15 is_stmt 0 view .LVU3327
+ 9537 00ea A36B     		ldr	r3, [r4, #56]
+4377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9538              		.loc 1 4377 43 view .LVU3328
+ 9539 00ec 2E4A     		ldr	r2, .L609+12
+ 9540 00ee 1A65     		str	r2, [r3, #80]
+4380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 9541              		.loc 1 4380 11 is_stmt 1 view .LVU3329
+4380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 9542              		.loc 1 4380 15 is_stmt 0 view .LVU3330
+ARM GAS  /tmp/ccVyGVF6.s 			page 356
+
+
+ 9543 00f0 A06B     		ldr	r0, [r4, #56]
+ 9544 00f2 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 9545              	.LVL655:
+4380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 9546              		.loc 1 4380 14 view .LVU3331
+ 9547 00f6 0028     		cmp	r0, #0
+ 9548 00f8 AED0     		beq	.L597
+4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9549              		.loc 1 4383 13 is_stmt 1 view .LVU3332
+4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9550              		.loc 1 4383 17 is_stmt 0 view .LVU3333
+ 9551 00fa A06B     		ldr	r0, [r4, #56]
+4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9552              		.loc 1 4383 25 view .LVU3334
+ 9553 00fc 036D     		ldr	r3, [r0, #80]
+4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9554              		.loc 1 4383 13 view .LVU3335
+ 9555 00fe 9847     		blx	r3
+ 9556              	.LVL656:
+ 9557 0100 AAE7     		b	.L597
+ 9558              	.L608:
+4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9559              		.loc 1 4390 7 is_stmt 1 view .LVU3336
+4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9560              		.loc 1 4390 16 is_stmt 0 view .LVU3337
+ 9561 0102 2368     		ldr	r3, [r4]
+4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9562              		.loc 1 4390 26 view .LVU3338
+ 9563 0104 1A68     		ldr	r2, [r3]
+4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 9564              		.loc 1 4390 10 view .LVU3339
+ 9565 0106 12F4004F 		tst	r2, #32768
+ 9566 010a A5D0     		beq	.L597
+4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9567              		.loc 1 4392 9 is_stmt 1 view .LVU3340
+4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9568              		.loc 1 4392 29 is_stmt 0 view .LVU3341
+ 9569 010c 1A68     		ldr	r2, [r3]
+ 9570 010e 22F40042 		bic	r2, r2, #32768
+ 9571 0112 1A60     		str	r2, [r3]
+4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 9572              		.loc 1 4395 9 is_stmt 1 view .LVU3342
+4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 9573              		.loc 1 4395 17 is_stmt 0 view .LVU3343
+ 9574 0114 E36B     		ldr	r3, [r4, #60]
+4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 9575              		.loc 1 4395 12 view .LVU3344
+ 9576 0116 002B     		cmp	r3, #0
+ 9577 0118 9ED0     		beq	.L597
+4399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9578              		.loc 1 4399 11 is_stmt 1 view .LVU3345
+4399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9579              		.loc 1 4399 43 is_stmt 0 view .LVU3346
+ 9580 011a 234A     		ldr	r2, .L609+12
+ 9581 011c 1A65     		str	r2, [r3, #80]
+4402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 9582              		.loc 1 4402 11 is_stmt 1 view .LVU3347
+ARM GAS  /tmp/ccVyGVF6.s 			page 357
+
+
+4402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 9583              		.loc 1 4402 15 is_stmt 0 view .LVU3348
+ 9584 011e E06B     		ldr	r0, [r4, #60]
+ 9585 0120 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 9586              	.LVL657:
+4402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 9587              		.loc 1 4402 14 view .LVU3349
+ 9588 0124 0028     		cmp	r0, #0
+ 9589 0126 97D0     		beq	.L597
+4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9590              		.loc 1 4405 13 is_stmt 1 view .LVU3350
+4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9591              		.loc 1 4405 17 is_stmt 0 view .LVU3351
+ 9592 0128 E06B     		ldr	r0, [r4, #60]
+4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9593              		.loc 1 4405 25 view .LVU3352
+ 9594 012a 036D     		ldr	r3, [r0, #80]
+4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 9595              		.loc 1 4405 13 view .LVU3353
+ 9596 012c 9847     		blx	r3
+ 9597              	.LVL658:
+ 9598 012e 93E7     		b	.L597
+ 9599              	.L598:
+4448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 9600              		.loc 1 4448 7 is_stmt 1 view .LVU3354
+4448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->Mode      = HAL_I2C_MODE_NONE;
+ 9601              		.loc 1 4448 23 is_stmt 0 view .LVU3355
+ 9602 0130 2823     		movs	r3, #40
+ 9603 0132 84F84130 		strb	r3, [r4, #65]
+4449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9604              		.loc 1 4449 7 is_stmt 1 view .LVU3356
+4449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9605              		.loc 1 4449 23 is_stmt 0 view .LVU3357
+ 9606 0136 0022     		movs	r2, #0
+ 9607 0138 84F84220 		strb	r2, [r4, #66]
+4452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9608              		.loc 1 4452 7 is_stmt 1 view .LVU3358
+4452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9609              		.loc 1 4452 23 is_stmt 0 view .LVU3359
+ 9610 013c 636C     		ldr	r3, [r4, #68]
+ 9611 013e 43F08003 		orr	r3, r3, #128
+ 9612 0142 6364     		str	r3, [r4, #68]
+4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9613              		.loc 1 4455 7 is_stmt 1 view .LVU3360
+4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9614              		.loc 1 4455 7 view .LVU3361
+ 9615 0144 84F84020 		strb	r2, [r4, #64]
+4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9616              		.loc 1 4455 7 view .LVU3362
+4457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9617              		.loc 1 4457 7 view .LVU3363
+4457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9618              		.loc 1 4457 14 is_stmt 0 view .LVU3364
+ 9619 0148 0125     		movs	r5, #1
+ 9620              	.LVL659:
+4457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9621              		.loc 1 4457 14 view .LVU3365
+ARM GAS  /tmp/ccVyGVF6.s 			page 358
+
+
+ 9622 014a 23E0     		b	.L594
+ 9623              	.LVL660:
+ 9624              	.L599:
+4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9625              		.loc 1 4463 7 is_stmt 1 view .LVU3366
+4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9626              		.loc 1 4463 23 is_stmt 0 view .LVU3367
+ 9627 014c 638D     		ldrh	r3, [r4, #42]
+ 9628 014e 9BB2     		uxth	r3, r3
+4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9629              		.loc 1 4463 30 view .LVU3368
+ 9630 0150 228D     		ldrh	r2, [r4, #40]
+4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9631              		.loc 1 4463 23 view .LVU3369
+ 9632 0152 9B1A     		subs	r3, r3, r2
+ 9633 0154 9BB2     		uxth	r3, r3
+ 9634 0156 6385     		strh	r3, [r4, #42]	@ movhi
+4466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9635              		.loc 1 4466 7 is_stmt 1 view .LVU3370
+4466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9636              		.loc 1 4466 22 is_stmt 0 view .LVU3371
+ 9637 0158 0023     		movs	r3, #0
+ 9638 015a 2385     		strh	r3, [r4, #40]	@ movhi
+4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
+ 9639              		.loc 1 4483 5 is_stmt 1 view .LVU3372
+4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
+ 9640              		.loc 1 4483 11 is_stmt 0 view .LVU3373
+ 9641 015c 2268     		ldr	r2, [r4]
+ 9642 015e 9369     		ldr	r3, [r2, #24]
+ 9643 0160 03F00803 		and	r3, r3, #8
+ 9644              	.LVL661:
+4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9645              		.loc 1 4484 5 is_stmt 1 view .LVU3374
+4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9646              		.loc 1 4484 10 is_stmt 0 view .LVU3375
+ 9647 0164 9169     		ldr	r1, [r2, #24]
+4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9648              		.loc 1 4484 8 view .LVU3376
+ 9649 0166 11F4803F 		tst	r1, #65536
+ 9650 016a 0DD0     		beq	.L601
+ 9651              	.LVL662:
+ 9652              	.L602:
+4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9653              		.loc 1 4492 5 is_stmt 1 view .LVU3377
+4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9654              		.loc 1 4492 5 view .LVU3378
+ 9655 016c 0023     		movs	r3, #0
+ 9656 016e 84F84030 		strb	r3, [r4, #64]
+4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9657              		.loc 1 4492 5 view .LVU3379
+4495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9658              		.loc 1 4495 5 view .LVU3380
+4495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9659              		.loc 1 4495 9 is_stmt 0 view .LVU3381
+ 9660 0172 2268     		ldr	r2, [r4]
+4495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9661              		.loc 1 4495 25 view .LVU3382
+ARM GAS  /tmp/ccVyGVF6.s 			page 359
+
+
+ 9662 0174 1368     		ldr	r3, [r2]
+ 9663 0176 43F40043 		orr	r3, r3, #32768
+ 9664 017a 1360     		str	r3, [r2]
+4501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9665              		.loc 1 4501 5 is_stmt 1 view .LVU3383
+ 9666 017c 48F20201 		movw	r1, #32770
+ 9667 0180 2046     		mov	r0, r4
+ 9668              	.LVL663:
+4501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9669              		.loc 1 4501 5 is_stmt 0 view .LVU3384
+ 9670 0182 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 9671              	.LVL664:
+4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9672              		.loc 1 4503 5 is_stmt 1 view .LVU3385
+4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9673              		.loc 1 4503 12 is_stmt 0 view .LVU3386
+ 9674 0186 05E0     		b	.L594
+ 9675              	.LVL665:
+ 9676              	.L601:
+4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9677              		.loc 1 4484 55 discriminator 1 view .LVU3387
+ 9678 0188 002B     		cmp	r3, #0
+ 9679 018a EFD0     		beq	.L602
+4488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9680              		.loc 1 4488 7 is_stmt 1 view .LVU3388
+ 9681 018c 0823     		movs	r3, #8
+ 9682              	.LVL666:
+4488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9683              		.loc 1 4488 7 is_stmt 0 view .LVU3389
+ 9684 018e D361     		str	r3, [r2, #28]
+ 9685 0190 ECE7     		b	.L602
+ 9686              	.LVL667:
+ 9687              	.L603:
+4507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9688              		.loc 1 4507 12 view .LVU3390
+ 9689 0192 0125     		movs	r5, #1
+ 9690              	.LVL668:
+ 9691              	.L594:
+4509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9692              		.loc 1 4509 1 view .LVU3391
+ 9693 0194 2846     		mov	r0, r5
+ 9694 0196 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 9695              	.LVL669:
+ 9696              	.L604:
+4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9697              		.loc 1 4359 5 view .LVU3392
+ 9698 0198 0225     		movs	r5, #2
+ 9699              	.LVL670:
+4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9700              		.loc 1 4359 5 view .LVU3393
+ 9701 019a FBE7     		b	.L594
+ 9702              	.L610:
+ 9703              		.align	2
+ 9704              	.L609:
+ 9705 019c 00000000 		.word	I2C_Slave_ISR_DMA
+ 9706 01a0 00000000 		.word	I2C_DMASlaveReceiveCplt
+ 9707 01a4 00000000 		.word	I2C_DMAError
+ARM GAS  /tmp/ccVyGVF6.s 			page 360
+
+
+ 9708 01a8 00000000 		.word	I2C_DMAAbort
+ 9709              		.cfi_endproc
+ 9710              	.LFE171:
+ 9712              		.section	.text.HAL_I2C_EnableListen_IT,"ax",%progbits
+ 9713              		.align	1
+ 9714              		.global	HAL_I2C_EnableListen_IT
+ 9715              		.syntax unified
+ 9716              		.thumb
+ 9717              		.thumb_func
+ 9718              		.fpu fpv5-d16
+ 9720              	HAL_I2C_EnableListen_IT:
+ 9721              	.LVL671:
+ 9722              	.LFB172:
+4518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 9723              		.loc 1 4518 1 is_stmt 1 view -0
+ 9724              		.cfi_startproc
+ 9725              		@ args = 0, pretend = 0, frame = 0
+ 9726              		@ frame_needed = 0, uses_anonymous_args = 0
+4518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 9727              		.loc 1 4518 1 is_stmt 0 view .LVU3395
+ 9728 0000 08B5     		push	{r3, lr}
+ 9729              	.LCFI106:
+ 9730              		.cfi_def_cfa_offset 8
+ 9731              		.cfi_offset 3, -8
+ 9732              		.cfi_offset 14, -4
+4519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9733              		.loc 1 4519 3 is_stmt 1 view .LVU3396
+4519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9734              		.loc 1 4519 11 is_stmt 0 view .LVU3397
+ 9735 0002 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 9736 0006 DBB2     		uxtb	r3, r3
+4519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9737              		.loc 1 4519 6 view .LVU3398
+ 9738 0008 202B     		cmp	r3, #32
+ 9739 000a 01D0     		beq	.L615
+4531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9740              		.loc 1 4531 12 view .LVU3399
+ 9741 000c 0220     		movs	r0, #2
+ 9742              	.LVL672:
+ 9743              	.L612:
+4533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9744              		.loc 1 4533 1 view .LVU3400
+ 9745 000e 08BD     		pop	{r3, pc}
+ 9746              	.LVL673:
+ 9747              	.L615:
+4521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR = I2C_Slave_ISR_IT;
+ 9748              		.loc 1 4521 5 is_stmt 1 view .LVU3401
+4521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR = I2C_Slave_ISR_IT;
+ 9749              		.loc 1 4521 17 is_stmt 0 view .LVU3402
+ 9750 0010 2823     		movs	r3, #40
+ 9751 0012 80F84130 		strb	r3, [r0, #65]
+4522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9752              		.loc 1 4522 5 is_stmt 1 view .LVU3403
+4522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9753              		.loc 1 4522 19 is_stmt 0 view .LVU3404
+ 9754 0016 044B     		ldr	r3, .L616
+ 9755 0018 4363     		str	r3, [r0, #52]
+ARM GAS  /tmp/ccVyGVF6.s 			page 361
+
+
+4525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9756              		.loc 1 4525 5 is_stmt 1 view .LVU3405
+ 9757 001a 4FF40041 		mov	r1, #32768
+ 9758 001e FFF7FEFF 		bl	I2C_Enable_IRQ
+ 9759              	.LVL674:
+4527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9760              		.loc 1 4527 5 view .LVU3406
+4527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9761              		.loc 1 4527 12 is_stmt 0 view .LVU3407
+ 9762 0022 0020     		movs	r0, #0
+ 9763 0024 F3E7     		b	.L612
+ 9764              	.L617:
+ 9765 0026 00BF     		.align	2
+ 9766              	.L616:
+ 9767 0028 00000000 		.word	I2C_Slave_ISR_IT
+ 9768              		.cfi_endproc
+ 9769              	.LFE172:
+ 9771              		.section	.text.HAL_I2C_DisableListen_IT,"ax",%progbits
+ 9772              		.align	1
+ 9773              		.global	HAL_I2C_DisableListen_IT
+ 9774              		.syntax unified
+ 9775              		.thumb
+ 9776              		.thumb_func
+ 9777              		.fpu fpv5-d16
+ 9779              	HAL_I2C_DisableListen_IT:
+ 9780              	.LVL675:
+ 9781              	.LFB173:
+4542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 9782              		.loc 1 4542 1 is_stmt 1 view -0
+ 9783              		.cfi_startproc
+ 9784              		@ args = 0, pretend = 0, frame = 0
+ 9785              		@ frame_needed = 0, uses_anonymous_args = 0
+4544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9786              		.loc 1 4544 3 view .LVU3409
+4547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9787              		.loc 1 4547 3 view .LVU3410
+4547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9788              		.loc 1 4547 11 is_stmt 0 view .LVU3411
+ 9789 0000 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 9790 0004 DBB2     		uxtb	r3, r3
+4547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9791              		.loc 1 4547 6 view .LVU3412
+ 9792 0006 282B     		cmp	r3, #40
+ 9793 0008 01D0     		beq	.L625
+4562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9794              		.loc 1 4562 12 view .LVU3413
+ 9795 000a 0220     		movs	r0, #2
+ 9796              	.LVL676:
+4564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9797              		.loc 1 4564 1 view .LVU3414
+ 9798 000c 7047     		bx	lr
+ 9799              	.LVL677:
+ 9800              	.L625:
+4542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ 9801              		.loc 1 4542 1 view .LVU3415
+ 9802 000e 10B5     		push	{r4, lr}
+ 9803              	.LCFI107:
+ARM GAS  /tmp/ccVyGVF6.s 			page 362
+
+
+ 9804              		.cfi_def_cfa_offset 8
+ 9805              		.cfi_offset 4, -8
+ 9806              		.cfi_offset 14, -4
+4549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ 9807              		.loc 1 4549 5 is_stmt 1 view .LVU3416
+4549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ 9808              		.loc 1 4549 26 is_stmt 0 view .LVU3417
+ 9809 0010 90F84120 		ldrb	r2, [r0, #65]	@ zero_extendqisi2
+ 9810              	.LVL678:
+4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 9811              		.loc 1 4550 5 is_stmt 1 view .LVU3418
+4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 9812              		.loc 1 4550 48 is_stmt 0 view .LVU3419
+ 9813 0014 90F84230 		ldrb	r3, [r0, #66]	@ zero_extendqisi2
+4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 9814              		.loc 1 4550 31 view .LVU3420
+ 9815 0018 02F00302 		and	r2, r2, #3
+ 9816              	.LVL679:
+4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 9817              		.loc 1 4550 31 view .LVU3421
+ 9818 001c 1343     		orrs	r3, r3, r2
+4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 9819              		.loc 1 4550 25 view .LVU3422
+ 9820 001e 0363     		str	r3, [r0, #48]
+4551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+ 9821              		.loc 1 4551 5 is_stmt 1 view .LVU3423
+4551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->Mode = HAL_I2C_MODE_NONE;
+ 9822              		.loc 1 4551 17 is_stmt 0 view .LVU3424
+ 9823 0020 2023     		movs	r3, #32
+ 9824 0022 80F84130 		strb	r3, [r0, #65]
+4552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR = NULL;
+ 9825              		.loc 1 4552 5 is_stmt 1 view .LVU3425
+4552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR = NULL;
+ 9826              		.loc 1 4552 16 is_stmt 0 view .LVU3426
+ 9827 0026 0024     		movs	r4, #0
+ 9828 0028 80F84240 		strb	r4, [r0, #66]
+4553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9829              		.loc 1 4553 5 is_stmt 1 view .LVU3427
+4553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9830              		.loc 1 4553 19 is_stmt 0 view .LVU3428
+ 9831 002c 4463     		str	r4, [r0, #52]
+4556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9832              		.loc 1 4556 5 is_stmt 1 view .LVU3429
+ 9833 002e 4FF40041 		mov	r1, #32768
+ 9834 0032 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9835              	.LVL680:
+4558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9836              		.loc 1 4558 5 view .LVU3430
+4558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9837              		.loc 1 4558 12 is_stmt 0 view .LVU3431
+ 9838 0036 2046     		mov	r0, r4
+4564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9839              		.loc 1 4564 1 view .LVU3432
+ 9840 0038 10BD     		pop	{r4, pc}
+ 9841              		.cfi_endproc
+ 9842              	.LFE173:
+ 9844              		.section	.text.HAL_I2C_Master_Abort_IT,"ax",%progbits
+ARM GAS  /tmp/ccVyGVF6.s 			page 363
+
+
+ 9845              		.align	1
+ 9846              		.global	HAL_I2C_Master_Abort_IT
+ 9847              		.syntax unified
+ 9848              		.thumb
+ 9849              		.thumb_func
+ 9850              		.fpu fpv5-d16
+ 9852              	HAL_I2C_Master_Abort_IT:
+ 9853              	.LVL681:
+ 9854              	.LFB174:
+4575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
+ 9855              		.loc 1 4575 1 is_stmt 1 view -0
+ 9856              		.cfi_startproc
+ 9857              		@ args = 0, pretend = 0, frame = 0
+ 9858              		@ frame_needed = 0, uses_anonymous_args = 0
+4576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9859              		.loc 1 4576 3 view .LVU3434
+4576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9860              		.loc 1 4576 23 is_stmt 0 view .LVU3435
+ 9861 0000 90F84230 		ldrb	r3, [r0, #66]	@ zero_extendqisi2
+ 9862 0004 DBB2     		uxtb	r3, r3
+ 9863              	.LVL682:
+4578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9864              		.loc 1 4578 3 is_stmt 1 view .LVU3436
+4578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 9865              		.loc 1 4578 6 is_stmt 0 view .LVU3437
+ 9866 0006 402B     		cmp	r3, #64
+ 9867 0008 18BF     		it	ne
+ 9868 000a 102B     		cmpne	r3, #16
+ 9869 000c 36D1     		bne	.L630
+4575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
+ 9870              		.loc 1 4575 1 view .LVU3438
+ 9871 000e 30B5     		push	{r4, r5, lr}
+ 9872              	.LCFI108:
+ 9873              		.cfi_def_cfa_offset 12
+ 9874              		.cfi_offset 4, -12
+ 9875              		.cfi_offset 5, -8
+ 9876              		.cfi_offset 14, -4
+ 9877 0010 83B0     		sub	sp, sp, #12
+ 9878              	.LCFI109:
+ 9879              		.cfi_def_cfa_offset 24
+ 9880 0012 0446     		mov	r4, r0
+ 9881 0014 0D46     		mov	r5, r1
+4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9882              		.loc 1 4581 5 is_stmt 1 view .LVU3439
+4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9883              		.loc 1 4581 5 view .LVU3440
+ 9884 0016 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 9885              	.LVL683:
+4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9886              		.loc 1 4581 5 is_stmt 0 view .LVU3441
+ 9887 001a 012B     		cmp	r3, #1
+ 9888 001c 30D0     		beq	.L631
+4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9889              		.loc 1 4581 5 is_stmt 1 discriminator 2 view .LVU3442
+ 9890 001e 0123     		movs	r3, #1
+ 9891 0020 80F84030 		strb	r3, [r0, #64]
+4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 364
+
+
+ 9892              		.loc 1 4581 5 discriminator 2 view .LVU3443
+4584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9893              		.loc 1 4584 5 discriminator 2 view .LVU3444
+4584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9894              		.loc 1 4584 13 is_stmt 0 discriminator 2 view .LVU3445
+ 9895 0024 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 9896 0028 DBB2     		uxtb	r3, r3
+4584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9897              		.loc 1 4584 8 discriminator 2 view .LVU3446
+ 9898 002a 212B     		cmp	r3, #33
+ 9899 002c 1AD0     		beq	.L636
+4589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9900              		.loc 1 4589 10 is_stmt 1 view .LVU3447
+4589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9901              		.loc 1 4589 18 is_stmt 0 view .LVU3448
+ 9902 002e 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 9903 0032 DBB2     		uxtb	r3, r3
+4589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 9904              		.loc 1 4589 13 view .LVU3449
+ 9905 0034 222B     		cmp	r3, #34
+ 9906 0036 1BD0     		beq	.L637
+ 9907              	.LVL684:
+ 9908              	.L629:
+4597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9909              		.loc 1 4597 5 is_stmt 1 view .LVU3450
+4600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9910              		.loc 1 4600 5 view .LVU3451
+4600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9911              		.loc 1 4600 17 is_stmt 0 view .LVU3452
+ 9912 0038 6023     		movs	r3, #96
+ 9913 003a 84F84130 		strb	r3, [r4, #65]
+4604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9914              		.loc 1 4604 5 is_stmt 1 view .LVU3453
+ 9915 003e 114B     		ldr	r3, .L638
+ 9916 0040 0093     		str	r3, [sp]
+ 9917 0042 4FF00073 		mov	r3, #33554432
+ 9918 0046 0122     		movs	r2, #1
+ 9919 0048 2946     		mov	r1, r5
+ 9920 004a 2046     		mov	r0, r4
+ 9921 004c FFF7FEFF 		bl	I2C_TransferConfig
+ 9922              	.LVL685:
+4607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9923              		.loc 1 4607 5 view .LVU3454
+4607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9924              		.loc 1 4607 5 view .LVU3455
+ 9925 0050 0025     		movs	r5, #0
+ 9926 0052 84F84050 		strb	r5, [r4, #64]
+4607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9927              		.loc 1 4607 5 view .LVU3456
+4612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9928              		.loc 1 4612 5 view .LVU3457
+ 9929 0056 2021     		movs	r1, #32
+ 9930 0058 2046     		mov	r0, r4
+ 9931 005a FFF7FEFF 		bl	I2C_Enable_IRQ
+ 9932              	.LVL686:
+4614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9933              		.loc 1 4614 5 view .LVU3458
+ARM GAS  /tmp/ccVyGVF6.s 			page 365
+
+
+4614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9934              		.loc 1 4614 12 is_stmt 0 view .LVU3459
+ 9935 005e 2846     		mov	r0, r5
+ 9936              	.L627:
+4622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9937              		.loc 1 4622 1 view .LVU3460
+ 9938 0060 03B0     		add	sp, sp, #12
+ 9939              	.LCFI110:
+ 9940              		.cfi_remember_state
+ 9941              		.cfi_def_cfa_offset 12
+ 9942              		@ sp needed
+ 9943 0062 30BD     		pop	{r4, r5, pc}
+ 9944              	.LVL687:
+ 9945              	.L636:
+ 9946              	.LCFI111:
+ 9947              		.cfi_restore_state
+4586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 9948              		.loc 1 4586 7 is_stmt 1 view .LVU3461
+ 9949 0064 0121     		movs	r1, #1
+ 9950              	.LVL688:
+4586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 9951              		.loc 1 4586 7 is_stmt 0 view .LVU3462
+ 9952 0066 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9953              	.LVL689:
+4587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9954              		.loc 1 4587 7 is_stmt 1 view .LVU3463
+4587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9955              		.loc 1 4587 27 is_stmt 0 view .LVU3464
+ 9956 006a 1123     		movs	r3, #17
+ 9957 006c 2363     		str	r3, [r4, #48]
+ 9958 006e E3E7     		b	.L629
+ 9959              	.LVL690:
+ 9960              	.L637:
+4591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 9961              		.loc 1 4591 7 is_stmt 1 view .LVU3465
+ 9962 0070 0221     		movs	r1, #2
+ 9963              	.LVL691:
+4591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 9964              		.loc 1 4591 7 is_stmt 0 view .LVU3466
+ 9965 0072 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 9966              	.LVL692:
+4592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9967              		.loc 1 4592 7 is_stmt 1 view .LVU3467
+4592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 9968              		.loc 1 4592 27 is_stmt 0 view .LVU3468
+ 9969 0076 1223     		movs	r3, #18
+ 9970 0078 2363     		str	r3, [r4, #48]
+ 9971 007a DDE7     		b	.L629
+ 9972              	.LVL693:
+ 9973              	.L630:
+ 9974              	.LCFI112:
+ 9975              		.cfi_def_cfa_offset 0
+ 9976              		.cfi_restore 4
+ 9977              		.cfi_restore 5
+ 9978              		.cfi_restore 14
+4620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 9979              		.loc 1 4620 12 view .LVU3469
+ARM GAS  /tmp/ccVyGVF6.s 			page 366
+
+
+ 9980 007c 0120     		movs	r0, #1
+ 9981              	.LVL694:
+4622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9982              		.loc 1 4622 1 view .LVU3470
+ 9983 007e 7047     		bx	lr
+ 9984              	.LVL695:
+ 9985              	.L631:
+ 9986              	.LCFI113:
+ 9987              		.cfi_def_cfa_offset 24
+ 9988              		.cfi_offset 4, -12
+ 9989              		.cfi_offset 5, -8
+ 9990              		.cfi_offset 14, -4
+4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9991              		.loc 1 4581 5 view .LVU3471
+ 9992 0080 0220     		movs	r0, #2
+ 9993              	.LVL696:
+4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 9994              		.loc 1 4581 5 view .LVU3472
+ 9995 0082 EDE7     		b	.L627
+ 9996              	.L639:
+ 9997              		.align	2
+ 9998              	.L638:
+ 9999 0084 00400080 		.word	-2147467264
+ 10000              		.cfi_endproc
+ 10001              	.LFE174:
+ 10003              		.section	.text.HAL_I2C_EV_IRQHandler,"ax",%progbits
+ 10004              		.align	1
+ 10005              		.global	HAL_I2C_EV_IRQHandler
+ 10006              		.syntax unified
+ 10007              		.thumb
+ 10008              		.thumb_func
+ 10009              		.fpu fpv5-d16
+ 10011              	HAL_I2C_EV_IRQHandler:
+ 10012              	.LVL697:
+ 10013              	.LFB175:
+4639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Get current IT Flags and IT sources value */
+ 10014              		.loc 1 4639 1 is_stmt 1 view -0
+ 10015              		.cfi_startproc
+ 10016              		@ args = 0, pretend = 0, frame = 0
+ 10017              		@ frame_needed = 0, uses_anonymous_args = 0
+4639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Get current IT Flags and IT sources value */
+ 10018              		.loc 1 4639 1 is_stmt 0 view .LVU3474
+ 10019 0000 08B5     		push	{r3, lr}
+ 10020              	.LCFI114:
+ 10021              		.cfi_def_cfa_offset 8
+ 10022              		.cfi_offset 3, -8
+ 10023              		.cfi_offset 14, -4
+4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 10024              		.loc 1 4641 3 is_stmt 1 view .LVU3475
+4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 10025              		.loc 1 4641 24 is_stmt 0 view .LVU3476
+ 10026 0002 0368     		ldr	r3, [r0]
+4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 10027              		.loc 1 4641 12 view .LVU3477
+ 10028 0004 9969     		ldr	r1, [r3, #24]
+ 10029              	.LVL698:
+4642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 367
+
+
+ 10030              		.loc 1 4642 3 is_stmt 1 view .LVU3478
+4642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10031              		.loc 1 4642 12 is_stmt 0 view .LVU3479
+ 10032 0006 1A68     		ldr	r2, [r3]
+ 10033              	.LVL699:
+4645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10034              		.loc 1 4645 3 is_stmt 1 view .LVU3480
+4645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10035              		.loc 1 4645 11 is_stmt 0 view .LVU3481
+ 10036 0008 436B     		ldr	r3, [r0, #52]
+4645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10037              		.loc 1 4645 6 view .LVU3482
+ 10038 000a 03B1     		cbz	r3, .L640
+4647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10039              		.loc 1 4647 5 is_stmt 1 view .LVU3483
+ 10040 000c 9847     		blx	r3
+ 10041              	.LVL700:
+ 10042              	.L640:
+4649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10043              		.loc 1 4649 1 is_stmt 0 view .LVU3484
+ 10044 000e 08BD     		pop	{r3, pc}
+ 10045              		.cfi_endproc
+ 10046              	.LFE175:
+ 10048              		.section	.text.HAL_I2C_MasterTxCpltCallback,"ax",%progbits
+ 10049              		.align	1
+ 10050              		.weak	HAL_I2C_MasterTxCpltCallback
+ 10051              		.syntax unified
+ 10052              		.thumb
+ 10053              		.thumb_func
+ 10054              		.fpu fpv5-d16
+ 10056              	HAL_I2C_MasterTxCpltCallback:
+ 10057              	.LVL701:
+ 10058              	.LFB177:
+4710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10059              		.loc 1 4710 1 is_stmt 1 view -0
+ 10060              		.cfi_startproc
+ 10061              		@ args = 0, pretend = 0, frame = 0
+ 10062              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10063              		@ link register save eliminated.
+4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10064              		.loc 1 4712 3 view .LVU3486
+4717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10065              		.loc 1 4717 1 is_stmt 0 view .LVU3487
+ 10066 0000 7047     		bx	lr
+ 10067              		.cfi_endproc
+ 10068              	.LFE177:
+ 10070              		.section	.text.HAL_I2C_MasterRxCpltCallback,"ax",%progbits
+ 10071              		.align	1
+ 10072              		.weak	HAL_I2C_MasterRxCpltCallback
+ 10073              		.syntax unified
+ 10074              		.thumb
+ 10075              		.thumb_func
+ 10076              		.fpu fpv5-d16
+ 10078              	HAL_I2C_MasterRxCpltCallback:
+ 10079              	.LVL702:
+ 10080              	.LFB178:
+4726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ARM GAS  /tmp/ccVyGVF6.s 			page 368
+
+
+ 10081              		.loc 1 4726 1 is_stmt 1 view -0
+ 10082              		.cfi_startproc
+ 10083              		@ args = 0, pretend = 0, frame = 0
+ 10084              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10085              		@ link register save eliminated.
+4728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10086              		.loc 1 4728 3 view .LVU3489
+4733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10087              		.loc 1 4733 1 is_stmt 0 view .LVU3490
+ 10088 0000 7047     		bx	lr
+ 10089              		.cfi_endproc
+ 10090              	.LFE178:
+ 10092              		.section	.text.I2C_ITMasterSeqCplt,"ax",%progbits
+ 10093              		.align	1
+ 10094              		.syntax unified
+ 10095              		.thumb
+ 10096              		.thumb_func
+ 10097              		.fpu fpv5-d16
+ 10099              	I2C_ITMasterSeqCplt:
+ 10100              	.LVL703:
+ 10101              	.LFB199:
+6053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Reset I2C handle mode */
+ 10102              		.loc 1 6053 1 is_stmt 1 view -0
+ 10103              		.cfi_startproc
+ 10104              		@ args = 0, pretend = 0, frame = 0
+ 10105              		@ frame_needed = 0, uses_anonymous_args = 0
+6053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Reset I2C handle mode */
+ 10106              		.loc 1 6053 1 is_stmt 0 view .LVU3492
+ 10107 0000 38B5     		push	{r3, r4, r5, lr}
+ 10108              	.LCFI115:
+ 10109              		.cfi_def_cfa_offset 16
+ 10110              		.cfi_offset 3, -16
+ 10111              		.cfi_offset 4, -12
+ 10112              		.cfi_offset 5, -8
+ 10113              		.cfi_offset 14, -4
+ 10114 0002 0446     		mov	r4, r0
+6055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10115              		.loc 1 6055 3 is_stmt 1 view .LVU3493
+6055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10116              		.loc 1 6055 14 is_stmt 0 view .LVU3494
+ 10117 0004 0023     		movs	r3, #0
+ 10118 0006 80F84230 		strb	r3, [r0, #66]
+6059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10119              		.loc 1 6059 3 is_stmt 1 view .LVU3495
+6059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10120              		.loc 1 6059 11 is_stmt 0 view .LVU3496
+ 10121 000a 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 10122 000e DBB2     		uxtb	r3, r3
+6059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10123              		.loc 1 6059 6 view .LVU3497
+ 10124 0010 212B     		cmp	r3, #33
+ 10125 0012 0FD0     		beq	.L649
+6081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 10126              		.loc 1 6081 5 is_stmt 1 view .LVU3498
+6081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 10127              		.loc 1 6081 25 is_stmt 0 view .LVU3499
+ 10128 0014 2023     		movs	r3, #32
+ARM GAS  /tmp/ccVyGVF6.s 			page 369
+
+
+ 10129 0016 80F84130 		strb	r3, [r0, #65]
+6082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+ 10130              		.loc 1 6082 5 is_stmt 1 view .LVU3500
+6082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+ 10131              		.loc 1 6082 25 is_stmt 0 view .LVU3501
+ 10132 001a 1223     		movs	r3, #18
+ 10133 001c 0363     		str	r3, [r0, #48]
+6083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10134              		.loc 1 6083 5 is_stmt 1 view .LVU3502
+6083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10135              		.loc 1 6083 25 is_stmt 0 view .LVU3503
+ 10136 001e 0025     		movs	r5, #0
+ 10137 0020 4563     		str	r5, [r0, #52]
+6086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10138              		.loc 1 6086 5 is_stmt 1 view .LVU3504
+ 10139 0022 0221     		movs	r1, #2
+ 10140 0024 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10141              	.LVL704:
+6089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10142              		.loc 1 6089 5 view .LVU3505
+6089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10143              		.loc 1 6089 5 view .LVU3506
+ 10144 0028 84F84050 		strb	r5, [r4, #64]
+6089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10145              		.loc 1 6089 5 view .LVU3507
+6095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10146              		.loc 1 6095 5 view .LVU3508
+ 10147 002c 2046     		mov	r0, r4
+ 10148 002e FFF7FEFF 		bl	HAL_I2C_MasterRxCpltCallback
+ 10149              	.LVL705:
+ 10150              	.L645:
+6098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10151              		.loc 1 6098 1 is_stmt 0 view .LVU3509
+ 10152 0032 38BD     		pop	{r3, r4, r5, pc}
+ 10153              	.LVL706:
+ 10154              	.L649:
+6061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 10155              		.loc 1 6061 5 is_stmt 1 view .LVU3510
+6061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 10156              		.loc 1 6061 25 is_stmt 0 view .LVU3511
+ 10157 0034 2023     		movs	r3, #32
+ 10158 0036 80F84130 		strb	r3, [r0, #65]
+6062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+ 10159              		.loc 1 6062 5 is_stmt 1 view .LVU3512
+6062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR       = NULL;
+ 10160              		.loc 1 6062 25 is_stmt 0 view .LVU3513
+ 10161 003a 1123     		movs	r3, #17
+ 10162 003c 0363     		str	r3, [r0, #48]
+6063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10163              		.loc 1 6063 5 is_stmt 1 view .LVU3514
+6063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10164              		.loc 1 6063 25 is_stmt 0 view .LVU3515
+ 10165 003e 0025     		movs	r5, #0
+ 10166 0040 4563     		str	r5, [r0, #52]
+6066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10167              		.loc 1 6066 5 is_stmt 1 view .LVU3516
+ 10168 0042 0121     		movs	r1, #1
+ARM GAS  /tmp/ccVyGVF6.s 			page 370
+
+
+ 10169 0044 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10170              	.LVL707:
+6069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10171              		.loc 1 6069 5 view .LVU3517
+6069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10172              		.loc 1 6069 5 view .LVU3518
+ 10173 0048 84F84050 		strb	r5, [r4, #64]
+6069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10174              		.loc 1 6069 5 view .LVU3519
+6075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10175              		.loc 1 6075 5 view .LVU3520
+ 10176 004c 2046     		mov	r0, r4
+ 10177 004e FFF7FEFF 		bl	HAL_I2C_MasterTxCpltCallback
+ 10178              	.LVL708:
+ 10179 0052 EEE7     		b	.L645
+ 10180              		.cfi_endproc
+ 10181              	.LFE199:
+ 10183              		.section	.text.HAL_I2C_SlaveTxCpltCallback,"ax",%progbits
+ 10184              		.align	1
+ 10185              		.weak	HAL_I2C_SlaveTxCpltCallback
+ 10186              		.syntax unified
+ 10187              		.thumb
+ 10188              		.thumb_func
+ 10189              		.fpu fpv5-d16
+ 10191              	HAL_I2C_SlaveTxCpltCallback:
+ 10192              	.LVL709:
+ 10193              	.LFB179:
+4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10194              		.loc 1 4741 1 view -0
+ 10195              		.cfi_startproc
+ 10196              		@ args = 0, pretend = 0, frame = 0
+ 10197              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10198              		@ link register save eliminated.
+4743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10199              		.loc 1 4743 3 view .LVU3522
+4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10200              		.loc 1 4748 1 is_stmt 0 view .LVU3523
+ 10201 0000 7047     		bx	lr
+ 10202              		.cfi_endproc
+ 10203              	.LFE179:
+ 10205              		.section	.text.HAL_I2C_SlaveRxCpltCallback,"ax",%progbits
+ 10206              		.align	1
+ 10207              		.weak	HAL_I2C_SlaveRxCpltCallback
+ 10208              		.syntax unified
+ 10209              		.thumb
+ 10210              		.thumb_func
+ 10211              		.fpu fpv5-d16
+ 10213              	HAL_I2C_SlaveRxCpltCallback:
+ 10214              	.LVL710:
+ 10215              	.LFB180:
+4757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10216              		.loc 1 4757 1 is_stmt 1 view -0
+ 10217              		.cfi_startproc
+ 10218              		@ args = 0, pretend = 0, frame = 0
+ 10219              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10220              		@ link register save eliminated.
+4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 371
+
+
+ 10221              		.loc 1 4759 3 view .LVU3525
+4764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10222              		.loc 1 4764 1 is_stmt 0 view .LVU3526
+ 10223 0000 7047     		bx	lr
+ 10224              		.cfi_endproc
+ 10225              	.LFE180:
+ 10227              		.section	.text.I2C_ITSlaveSeqCplt,"ax",%progbits
+ 10228              		.align	1
+ 10229              		.syntax unified
+ 10230              		.thumb
+ 10231              		.thumb_func
+ 10232              		.fpu fpv5-d16
+ 10234              	I2C_ITSlaveSeqCplt:
+ 10235              	.LVL711:
+ 10236              	.LFB200:
+6106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ 10237              		.loc 1 6106 1 is_stmt 1 view -0
+ 10238              		.cfi_startproc
+ 10239              		@ args = 0, pretend = 0, frame = 0
+ 10240              		@ frame_needed = 0, uses_anonymous_args = 0
+6106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ 10241              		.loc 1 6106 1 is_stmt 0 view .LVU3528
+ 10242 0000 10B5     		push	{r4, lr}
+ 10243              	.LCFI116:
+ 10244              		.cfi_def_cfa_offset 8
+ 10245              		.cfi_offset 4, -8
+ 10246              		.cfi_offset 14, -4
+ 10247 0002 0446     		mov	r4, r0
+6107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10248              		.loc 1 6107 3 is_stmt 1 view .LVU3529
+6107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10249              		.loc 1 6107 26 is_stmt 0 view .LVU3530
+ 10250 0004 0368     		ldr	r3, [r0]
+6107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10251              		.loc 1 6107 12 view .LVU3531
+ 10252 0006 1A68     		ldr	r2, [r3]
+ 10253              	.LVL712:
+6110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10254              		.loc 1 6110 3 is_stmt 1 view .LVU3532
+6110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10255              		.loc 1 6110 14 is_stmt 0 view .LVU3533
+ 10256 0008 0021     		movs	r1, #0
+ 10257 000a 80F84210 		strb	r1, [r0, #66]
+6113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10258              		.loc 1 6113 3 is_stmt 1 view .LVU3534
+6113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10259              		.loc 1 6113 6 is_stmt 0 view .LVU3535
+ 10260 000e 12F4804F 		tst	r2, #16384
+ 10261 0012 0ED0     		beq	.L653
+6116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10262              		.loc 1 6116 5 is_stmt 1 view .LVU3536
+6116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10263              		.loc 1 6116 25 is_stmt 0 view .LVU3537
+ 10264 0014 1A68     		ldr	r2, [r3]
+ 10265              	.LVL713:
+6116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10266              		.loc 1 6116 25 view .LVU3538
+ARM GAS  /tmp/ccVyGVF6.s 			page 372
+
+
+ 10267 0016 22F48042 		bic	r2, r2, #16384
+ 10268 001a 1A60     		str	r2, [r3]
+ 10269              	.L654:
+6126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10270              		.loc 1 6126 3 is_stmt 1 view .LVU3539
+6128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10271              		.loc 1 6128 3 view .LVU3540
+6128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10272              		.loc 1 6128 11 is_stmt 0 view .LVU3541
+ 10273 001c 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 10274 0020 DBB2     		uxtb	r3, r3
+6128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10275              		.loc 1 6128 6 view .LVU3542
+ 10276 0022 292B     		cmp	r3, #41
+ 10277 0024 0DD0     		beq	.L658
+6148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10278              		.loc 1 6148 8 is_stmt 1 view .LVU3543
+6148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10279              		.loc 1 6148 16 is_stmt 0 view .LVU3544
+ 10280 0026 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 10281 002a DBB2     		uxtb	r3, r3
+6148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10282              		.loc 1 6148 11 view .LVU3545
+ 10283 002c 2A2B     		cmp	r3, #42
+ 10284 002e 18D0     		beq	.L659
+ 10285              	.LVL714:
+ 10286              	.L652:
+6171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10287              		.loc 1 6171 1 view .LVU3546
+ 10288 0030 10BD     		pop	{r4, pc}
+ 10289              	.LVL715:
+ 10290              	.L653:
+6118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10291              		.loc 1 6118 8 is_stmt 1 view .LVU3547
+6118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10292              		.loc 1 6118 11 is_stmt 0 view .LVU3548
+ 10293 0032 12F4004F 		tst	r2, #32768
+ 10294 0036 F1D0     		beq	.L654
+6121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10295              		.loc 1 6121 5 is_stmt 1 view .LVU3549
+6121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10296              		.loc 1 6121 25 is_stmt 0 view .LVU3550
+ 10297 0038 1A68     		ldr	r2, [r3]
+ 10298              	.LVL716:
+6121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10299              		.loc 1 6121 25 view .LVU3551
+ 10300 003a 22F40042 		bic	r2, r2, #32768
+ 10301 003e 1A60     		str	r2, [r3]
+ 10302 0040 ECE7     		b	.L654
+ 10303              	.L658:
+6131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ 10304              		.loc 1 6131 5 is_stmt 1 view .LVU3552
+6131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ 10305              		.loc 1 6131 25 is_stmt 0 view .LVU3553
+ 10306 0042 2823     		movs	r3, #40
+ 10307 0044 84F84130 		strb	r3, [r4, #65]
+6132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 373
+
+
+ 10308              		.loc 1 6132 5 is_stmt 1 view .LVU3554
+6132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10309              		.loc 1 6132 25 is_stmt 0 view .LVU3555
+ 10310 0048 2123     		movs	r3, #33
+ 10311 004a 2363     		str	r3, [r4, #48]
+6135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10312              		.loc 1 6135 5 is_stmt 1 view .LVU3556
+ 10313 004c 0121     		movs	r1, #1
+ 10314 004e 2046     		mov	r0, r4
+ 10315              	.LVL717:
+6135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10316              		.loc 1 6135 5 is_stmt 0 view .LVU3557
+ 10317 0050 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10318              	.LVL718:
+6138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10319              		.loc 1 6138 5 is_stmt 1 view .LVU3558
+6138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10320              		.loc 1 6138 5 view .LVU3559
+ 10321 0054 0023     		movs	r3, #0
+ 10322 0056 84F84030 		strb	r3, [r4, #64]
+6138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10323              		.loc 1 6138 5 view .LVU3560
+6144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10324              		.loc 1 6144 5 view .LVU3561
+ 10325 005a 2046     		mov	r0, r4
+ 10326 005c FFF7FEFF 		bl	HAL_I2C_SlaveTxCpltCallback
+ 10327              	.LVL719:
+ 10328 0060 E6E7     		b	.L652
+ 10329              	.LVL720:
+ 10330              	.L659:
+6151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ 10331              		.loc 1 6151 5 view .LVU3562
+6151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ 10332              		.loc 1 6151 25 is_stmt 0 view .LVU3563
+ 10333 0062 2823     		movs	r3, #40
+ 10334 0064 84F84130 		strb	r3, [r4, #65]
+6152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10335              		.loc 1 6152 5 is_stmt 1 view .LVU3564
+6152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10336              		.loc 1 6152 25 is_stmt 0 view .LVU3565
+ 10337 0068 2223     		movs	r3, #34
+ 10338 006a 2363     		str	r3, [r4, #48]
+6155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10339              		.loc 1 6155 5 is_stmt 1 view .LVU3566
+ 10340 006c 0221     		movs	r1, #2
+ 10341 006e 2046     		mov	r0, r4
+ 10342              	.LVL721:
+6155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10343              		.loc 1 6155 5 is_stmt 0 view .LVU3567
+ 10344 0070 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10345              	.LVL722:
+6158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10346              		.loc 1 6158 5 is_stmt 1 view .LVU3568
+6158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10347              		.loc 1 6158 5 view .LVU3569
+ 10348 0074 0023     		movs	r3, #0
+ 10349 0076 84F84030 		strb	r3, [r4, #64]
+ARM GAS  /tmp/ccVyGVF6.s 			page 374
+
+
+6158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10350              		.loc 1 6158 5 view .LVU3570
+6164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10351              		.loc 1 6164 5 view .LVU3571
+ 10352 007a 2046     		mov	r0, r4
+ 10353 007c FFF7FEFF 		bl	HAL_I2C_SlaveRxCpltCallback
+ 10354              	.LVL723:
+6170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 10355              		.loc 1 6170 3 view .LVU3572
+6171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10356              		.loc 1 6171 1 is_stmt 0 view .LVU3573
+ 10357 0080 D6E7     		b	.L652
+ 10358              		.cfi_endproc
+ 10359              	.LFE200:
+ 10361              		.section	.text.I2C_DMASlaveTransmitCplt,"ax",%progbits
+ 10362              		.align	1
+ 10363              		.syntax unified
+ 10364              		.thumb
+ 10365              		.thumb_func
+ 10366              		.fpu fpv5-d16
+ 10368              	I2C_DMASlaveTransmitCplt:
+ 10369              	.LVL724:
+ 10370              	.LFB208:
+6831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 10371              		.loc 1 6831 1 is_stmt 1 view -0
+ 10372              		.cfi_startproc
+ 10373              		@ args = 0, pretend = 0, frame = 0
+ 10374              		@ frame_needed = 0, uses_anonymous_args = 0
+6831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 10375              		.loc 1 6831 1 is_stmt 0 view .LVU3575
+ 10376 0000 08B5     		push	{r3, lr}
+ 10377              	.LCFI117:
+ 10378              		.cfi_def_cfa_offset 8
+ 10379              		.cfi_offset 3, -8
+ 10380              		.cfi_offset 14, -4
+6833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 10381              		.loc 1 6833 3 is_stmt 1 view .LVU3576
+6833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 10382              		.loc 1 6833 22 is_stmt 0 view .LVU3577
+ 10383 0002 806B     		ldr	r0, [r0, #56]
+ 10384              	.LVL725:
+6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10385              		.loc 1 6834 3 is_stmt 1 view .LVU3578
+6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10386              		.loc 1 6834 12 is_stmt 0 view .LVU3579
+ 10387 0004 C36A     		ldr	r3, [r0, #44]
+ 10388              	.LVL726:
+6836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10389              		.loc 1 6836 3 is_stmt 1 view .LVU3580
+6836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10390              		.loc 1 6836 6 is_stmt 0 view .LVU3581
+ 10391 0006 002B     		cmp	r3, #0
+ 10392 0008 18BF     		it	ne
+ 10393 000a B3F1807F 		cmpne	r3, #16777216
+ 10394 000e 00D0     		beq	.L663
+ 10395              	.LVL727:
+ 10396              	.L660:
+ARM GAS  /tmp/ccVyGVF6.s 			page 375
+
+
+6851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10397              		.loc 1 6851 1 view .LVU3582
+ 10398 0010 08BD     		pop	{r3, pc}
+ 10399              	.LVL728:
+ 10400              	.L663:
+6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10401              		.loc 1 6839 5 is_stmt 1 view .LVU3583
+6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10402              		.loc 1 6839 9 is_stmt 0 view .LVU3584
+ 10403 0012 0268     		ldr	r2, [r0]
+6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10404              		.loc 1 6839 25 view .LVU3585
+ 10405 0014 1368     		ldr	r3, [r2]
+ 10406              	.LVL729:
+6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10407              		.loc 1 6839 25 view .LVU3586
+ 10408 0016 23F48043 		bic	r3, r3, #16384
+ 10409 001a 1360     		str	r3, [r2]
+6843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10410              		.loc 1 6843 5 is_stmt 1 view .LVU3587
+ 10411 001c FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 10412              	.LVL730:
+6850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 10413              		.loc 1 6850 3 view .LVU3588
+6851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10414              		.loc 1 6851 1 is_stmt 0 view .LVU3589
+ 10415 0020 F6E7     		b	.L660
+ 10416              		.cfi_endproc
+ 10417              	.LFE208:
+ 10419              		.section	.text.I2C_DMASlaveReceiveCplt,"ax",%progbits
+ 10420              		.align	1
+ 10421              		.syntax unified
+ 10422              		.thumb
+ 10423              		.thumb_func
+ 10424              		.fpu fpv5-d16
+ 10426              	I2C_DMASlaveReceiveCplt:
+ 10427              	.LVL731:
+ 10428              	.LFB210:
+6919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 10429              		.loc 1 6919 1 is_stmt 1 view -0
+ 10430              		.cfi_startproc
+ 10431              		@ args = 0, pretend = 0, frame = 0
+ 10432              		@ frame_needed = 0, uses_anonymous_args = 0
+6919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 10433              		.loc 1 6919 1 is_stmt 0 view .LVU3591
+ 10434 0000 08B5     		push	{r3, lr}
+ 10435              	.LCFI118:
+ 10436              		.cfi_def_cfa_offset 8
+ 10437              		.cfi_offset 3, -8
+ 10438              		.cfi_offset 14, -4
+6921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 10439              		.loc 1 6921 3 is_stmt 1 view .LVU3592
+6921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 10440              		.loc 1 6921 22 is_stmt 0 view .LVU3593
+ 10441 0002 806B     		ldr	r0, [r0, #56]
+ 10442              	.LVL732:
+6922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 376
+
+
+ 10443              		.loc 1 6922 3 is_stmt 1 view .LVU3594
+6922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10444              		.loc 1 6922 12 is_stmt 0 view .LVU3595
+ 10445 0004 C26A     		ldr	r2, [r0, #44]
+ 10446              	.LVL733:
+6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (tmpoptions != I2C_NO_OPTION_FRAME))
+ 10447              		.loc 1 6924 3 is_stmt 1 view .LVU3596
+6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (tmpoptions != I2C_NO_OPTION_FRAME))
+ 10448              		.loc 1 6924 8 is_stmt 0 view .LVU3597
+ 10449 0006 C36B     		ldr	r3, [r0, #60]
+ 10450 0008 1B68     		ldr	r3, [r3]
+ 10451 000a 5B68     		ldr	r3, [r3, #4]
+6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (tmpoptions != I2C_NO_OPTION_FRAME))
+ 10452              		.loc 1 6924 6 view .LVU3598
+ 10453 000c 13B9     		cbnz	r3, .L664
+6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (tmpoptions != I2C_NO_OPTION_FRAME))
+ 10454              		.loc 1 6924 53 discriminator 1 view .LVU3599
+ 10455 000e 12F5803F 		cmn	r2, #65536
+ 10456 0012 00D1     		bne	.L667
+ 10457              	.LVL734:
+ 10458              	.L664:
+6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10459              		.loc 1 6939 1 view .LVU3600
+ 10460 0014 08BD     		pop	{r3, pc}
+ 10461              	.LVL735:
+ 10462              	.L667:
+6928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10463              		.loc 1 6928 5 is_stmt 1 view .LVU3601
+6928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10464              		.loc 1 6928 9 is_stmt 0 view .LVU3602
+ 10465 0016 0268     		ldr	r2, [r0]
+ 10466              	.LVL736:
+6928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10467              		.loc 1 6928 25 view .LVU3603
+ 10468 0018 1368     		ldr	r3, [r2]
+ 10469 001a 23F40043 		bic	r3, r3, #32768
+ 10470 001e 1360     		str	r3, [r2]
+6931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10471              		.loc 1 6931 5 is_stmt 1 view .LVU3604
+ 10472 0020 FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 10473              	.LVL737:
+6938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 10474              		.loc 1 6938 3 view .LVU3605
+6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10475              		.loc 1 6939 1 is_stmt 0 view .LVU3606
+ 10476 0024 F6E7     		b	.L664
+ 10477              		.cfi_endproc
+ 10478              	.LFE210:
+ 10480              		.section	.text.HAL_I2C_AddrCallback,"ax",%progbits
+ 10481              		.align	1
+ 10482              		.weak	HAL_I2C_AddrCallback
+ 10483              		.syntax unified
+ 10484              		.thumb
+ 10485              		.thumb_func
+ 10486              		.fpu fpv5-d16
+ 10488              	HAL_I2C_AddrCallback:
+ 10489              	.LVL738:
+ARM GAS  /tmp/ccVyGVF6.s 			page 377
+
+
+ 10490              	.LFB181:
+4775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10491              		.loc 1 4775 1 is_stmt 1 view -0
+ 10492              		.cfi_startproc
+ 10493              		@ args = 0, pretend = 0, frame = 0
+ 10494              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10495              		@ link register save eliminated.
+4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(TransferDirection);
+ 10496              		.loc 1 4777 3 view .LVU3608
+4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   UNUSED(AddrMatchCode);
+ 10497              		.loc 1 4778 3 view .LVU3609
+4779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10498              		.loc 1 4779 3 view .LVU3610
+4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10499              		.loc 1 4784 1 is_stmt 0 view .LVU3611
+ 10500 0000 7047     		bx	lr
+ 10501              		.cfi_endproc
+ 10502              	.LFE181:
+ 10504              		.section	.text.I2C_ITAddrCplt,"ax",%progbits
+ 10505              		.align	1
+ 10506              		.syntax unified
+ 10507              		.thumb
+ 10508              		.thumb_func
+ 10509              		.fpu fpv5-d16
+ 10511              	I2C_ITAddrCplt:
+ 10512              	.LVL739:
+ 10513              	.LFB198:
+5958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint8_t transferdirection;
+ 10514              		.loc 1 5958 1 is_stmt 1 view -0
+ 10515              		.cfi_startproc
+ 10516              		@ args = 0, pretend = 0, frame = 0
+ 10517              		@ frame_needed = 0, uses_anonymous_args = 0
+5958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint8_t transferdirection;
+ 10518              		.loc 1 5958 1 is_stmt 0 view .LVU3613
+ 10519 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 10520              	.LCFI119:
+ 10521              		.cfi_def_cfa_offset 24
+ 10522              		.cfi_offset 3, -24
+ 10523              		.cfi_offset 4, -20
+ 10524              		.cfi_offset 5, -16
+ 10525              		.cfi_offset 6, -12
+ 10526              		.cfi_offset 7, -8
+ 10527              		.cfi_offset 14, -4
+ 10528 0002 0446     		mov	r4, r0
+5959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t slaveaddrcode;
+ 10529              		.loc 1 5959 3 is_stmt 1 view .LVU3614
+5960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t ownadd1code;
+ 10530              		.loc 1 5960 3 view .LVU3615
+5961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t ownadd2code;
+ 10531              		.loc 1 5961 3 view .LVU3616
+5962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10532              		.loc 1 5962 3 view .LVU3617
+5965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10533              		.loc 1 5965 3 view .LVU3618
+5968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10534              		.loc 1 5968 3 view .LVU3619
+5968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ARM GAS  /tmp/ccVyGVF6.s 			page 378
+
+
+ 10535              		.loc 1 5968 22 is_stmt 0 view .LVU3620
+ 10536 0004 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+5968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10537              		.loc 1 5968 6 view .LVU3621
+ 10538 0008 03F02803 		and	r3, r3, #40
+ 10539 000c 282B     		cmp	r3, #40
+ 10540 000e 06D0     		beq	.L675
+6040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10541              		.loc 1 6040 5 is_stmt 1 view .LVU3622
+ 10542 0010 0368     		ldr	r3, [r0]
+ 10543 0012 0822     		movs	r2, #8
+ 10544 0014 DA61     		str	r2, [r3, #28]
+6043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10545              		.loc 1 6043 5 view .LVU3623
+6043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10546              		.loc 1 6043 5 view .LVU3624
+ 10547 0016 0023     		movs	r3, #0
+ 10548 0018 80F84030 		strb	r3, [r0, #64]
+6043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 10549              		.loc 1 6043 5 view .LVU3625
+ 10550              	.LVL740:
+ 10551              	.L669:
+6045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10552              		.loc 1 6045 1 is_stmt 0 view .LVU3626
+ 10553 001c F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 10554              	.LVL741:
+ 10555              	.L675:
+5970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+ 10556              		.loc 1 5970 5 is_stmt 1 view .LVU3627
+5970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+ 10557              		.loc 1 5970 25 is_stmt 0 view .LVU3628
+ 10558 001e 0368     		ldr	r3, [r0]
+ 10559 0020 9E69     		ldr	r6, [r3, #24]
+5970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+ 10560              		.loc 1 5970 23 view .LVU3629
+ 10561 0022 C6F30046 		ubfx	r6, r6, #16, #1
+ 10562              	.LVL742:
+5971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+ 10563              		.loc 1 5971 5 is_stmt 1 view .LVU3630
+5971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+ 10564              		.loc 1 5971 25 is_stmt 0 view .LVU3631
+ 10565 0026 9A69     		ldr	r2, [r3, #24]
+ 10566 0028 120C     		lsrs	r2, r2, #16
+5971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+ 10567              		.loc 1 5971 23 view .LVU3632
+ 10568 002a 02F0FE05 		and	r5, r2, #254
+ 10569              	.LVL743:
+5972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+ 10570              		.loc 1 5972 5 is_stmt 1 view .LVU3633
+5972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+ 10571              		.loc 1 5972 25 is_stmt 0 view .LVU3634
+ 10572 002e 9A68     		ldr	r2, [r3, #8]
+5972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+ 10573              		.loc 1 5972 23 view .LVU3635
+ 10574 0030 C2F30902 		ubfx	r2, r2, #0, #10
+ 10575              	.LVL744:
+5973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 379
+
+
+ 10576              		.loc 1 5973 5 is_stmt 1 view .LVU3636
+5973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10577              		.loc 1 5973 25 is_stmt 0 view .LVU3637
+ 10578 0034 DF68     		ldr	r7, [r3, #12]
+5973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10579              		.loc 1 5973 23 view .LVU3638
+ 10580 0036 07F0FE07 		and	r7, r7, #254
+ 10581              	.LVL745:
+5976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 10582              		.loc 1 5976 5 is_stmt 1 view .LVU3639
+5976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 10583              		.loc 1 5976 19 is_stmt 0 view .LVU3640
+ 10584 003a C168     		ldr	r1, [r0, #12]
+ 10585              	.LVL746:
+5976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 10586              		.loc 1 5976 8 view .LVU3641
+ 10587 003c 0229     		cmp	r1, #2
+ 10588 003e 22D1     		bne	.L671
+5978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 10589              		.loc 1 5978 7 is_stmt 1 view .LVU3642
+5978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 10590              		.loc 1 5978 44 is_stmt 0 view .LVU3643
+ 10591 0040 85EAD215 		eor	r5, r5, r2, lsr #7
+ 10592              	.LVL747:
+5978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 10593              		.loc 1 5978 10 view .LVU3644
+ 10594 0044 15F0060F 		tst	r5, #6
+ 10595 0048 10D1     		bne	.L672
+5980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         hi2c->AddrEventCount++;
+ 10596              		.loc 1 5980 9 is_stmt 1 view .LVU3645
+ 10597              	.LVL748:
+5981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->AddrEventCount == 2U)
+ 10598              		.loc 1 5981 9 view .LVU3646
+5981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->AddrEventCount == 2U)
+ 10599              		.loc 1 5981 13 is_stmt 0 view .LVU3647
+ 10600 004a 816C     		ldr	r1, [r0, #72]
+5981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->AddrEventCount == 2U)
+ 10601              		.loc 1 5981 29 view .LVU3648
+ 10602 004c 0131     		adds	r1, r1, #1
+ 10603 004e 8164     		str	r1, [r0, #72]
+5982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 10604              		.loc 1 5982 9 is_stmt 1 view .LVU3649
+5982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 10605              		.loc 1 5982 17 is_stmt 0 view .LVU3650
+ 10606 0050 816C     		ldr	r1, [r0, #72]
+5982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 10607              		.loc 1 5982 12 view .LVU3651
+ 10608 0052 0229     		cmp	r1, #2
+ 10609 0054 E2D1     		bne	.L669
+5985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10610              		.loc 1 5985 11 is_stmt 1 view .LVU3652
+5985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10611              		.loc 1 5985 32 is_stmt 0 view .LVU3653
+ 10612 0056 0021     		movs	r1, #0
+ 10613 0058 8164     		str	r1, [r0, #72]
+5988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10614              		.loc 1 5988 11 is_stmt 1 view .LVU3654
+ARM GAS  /tmp/ccVyGVF6.s 			page 380
+
+
+ 10615 005a 0820     		movs	r0, #8
+ 10616              	.LVL749:
+5988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10617              		.loc 1 5988 11 is_stmt 0 view .LVU3655
+ 10618 005c D861     		str	r0, [r3, #28]
+5991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10619              		.loc 1 5991 11 is_stmt 1 view .LVU3656
+5991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10620              		.loc 1 5991 11 view .LVU3657
+ 10621 005e 84F84010 		strb	r1, [r4, #64]
+5991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10622              		.loc 1 5991 11 view .LVU3658
+5997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10623              		.loc 1 5997 11 view .LVU3659
+ 10624 0062 3146     		mov	r1, r6
+ 10625 0064 2046     		mov	r0, r4
+ 10626 0066 FFF7FEFF 		bl	HAL_I2C_AddrCallback
+ 10627              	.LVL750:
+5997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10628              		.loc 1 5997 11 is_stmt 0 view .LVU3660
+ 10629 006a D7E7     		b	.L669
+ 10630              	.LVL751:
+ 10631              	.L672:
+6003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10632              		.loc 1 6003 9 is_stmt 1 view .LVU3661
+6006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10633              		.loc 1 6006 9 view .LVU3662
+ 10634 006c 4FF40041 		mov	r1, #32768
+ 10635 0070 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10636              	.LVL752:
+6009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10637              		.loc 1 6009 9 view .LVU3663
+6009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10638              		.loc 1 6009 9 view .LVU3664
+ 10639 0074 0023     		movs	r3, #0
+ 10640 0076 84F84030 		strb	r3, [r4, #64]
+6009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10641              		.loc 1 6009 9 view .LVU3665
+6015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10642              		.loc 1 6015 9 view .LVU3666
+ 10643 007a 3A46     		mov	r2, r7
+ 10644 007c 3146     		mov	r1, r6
+ 10645 007e 2046     		mov	r0, r4
+ 10646 0080 FFF7FEFF 		bl	HAL_I2C_AddrCallback
+ 10647              	.LVL753:
+ 10648 0084 CAE7     		b	.L669
+ 10649              	.LVL754:
+ 10650              	.L671:
+6023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10651              		.loc 1 6023 7 view .LVU3667
+ 10652 0086 4FF40041 		mov	r1, #32768
+ 10653 008a FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10654              	.LVL755:
+6026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10655              		.loc 1 6026 7 view .LVU3668
+6026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10656              		.loc 1 6026 7 view .LVU3669
+ARM GAS  /tmp/ccVyGVF6.s 			page 381
+
+
+ 10657 008e 0023     		movs	r3, #0
+ 10658 0090 84F84030 		strb	r3, [r4, #64]
+6026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10659              		.loc 1 6026 7 view .LVU3670
+6032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10660              		.loc 1 6032 7 view .LVU3671
+ 10661 0094 2A46     		mov	r2, r5
+ 10662 0096 3146     		mov	r1, r6
+ 10663 0098 2046     		mov	r0, r4
+ 10664 009a FFF7FEFF 		bl	HAL_I2C_AddrCallback
+ 10665              	.LVL756:
+ 10666 009e BDE7     		b	.L669
+ 10667              		.cfi_endproc
+ 10668              	.LFE198:
+ 10670              		.section	.text.HAL_I2C_ListenCpltCallback,"ax",%progbits
+ 10671              		.align	1
+ 10672              		.weak	HAL_I2C_ListenCpltCallback
+ 10673              		.syntax unified
+ 10674              		.thumb
+ 10675              		.thumb_func
+ 10676              		.fpu fpv5-d16
+ 10678              	HAL_I2C_ListenCpltCallback:
+ 10679              	.LVL757:
+ 10680              	.LFB182:
+4793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10681              		.loc 1 4793 1 view -0
+ 10682              		.cfi_startproc
+ 10683              		@ args = 0, pretend = 0, frame = 0
+ 10684              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10685              		@ link register save eliminated.
+4795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10686              		.loc 1 4795 3 view .LVU3673
+4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10687              		.loc 1 4800 1 is_stmt 0 view .LVU3674
+ 10688 0000 7047     		bx	lr
+ 10689              		.cfi_endproc
+ 10690              	.LFE182:
+ 10692              		.section	.text.I2C_ITListenCplt,"ax",%progbits
+ 10693              		.align	1
+ 10694              		.syntax unified
+ 10695              		.thumb
+ 10696              		.thumb_func
+ 10697              		.fpu fpv5-d16
+ 10699              	I2C_ITListenCplt:
+ 10700              	.LVL758:
+ 10701              	.LFB203:
+6539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Reset handle parameters */
+ 10702              		.loc 1 6539 1 is_stmt 1 view -0
+ 10703              		.cfi_startproc
+ 10704              		@ args = 0, pretend = 0, frame = 0
+ 10705              		@ frame_needed = 0, uses_anonymous_args = 0
+6539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Reset handle parameters */
+ 10706              		.loc 1 6539 1 is_stmt 0 view .LVU3676
+ 10707 0000 10B5     		push	{r4, lr}
+ 10708              	.LCFI120:
+ 10709              		.cfi_def_cfa_offset 8
+ 10710              		.cfi_offset 4, -8
+ARM GAS  /tmp/ccVyGVF6.s 			page 382
+
+
+ 10711              		.cfi_offset 14, -4
+ 10712 0002 0446     		mov	r4, r0
+6541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 10713              		.loc 1 6541 3 is_stmt 1 view .LVU3677
+6541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->PreviousState = I2C_STATE_NONE;
+ 10714              		.loc 1 6541 21 is_stmt 0 view .LVU3678
+ 10715 0004 174B     		ldr	r3, .L680
+ 10716 0006 C362     		str	r3, [r0, #44]
+6542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+ 10717              		.loc 1 6542 3 is_stmt 1 view .LVU3679
+6542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->State = HAL_I2C_STATE_READY;
+ 10718              		.loc 1 6542 23 is_stmt 0 view .LVU3680
+ 10719 0008 0023     		movs	r3, #0
+ 10720 000a 0363     		str	r3, [r0, #48]
+6543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 10721              		.loc 1 6543 3 is_stmt 1 view .LVU3681
+6543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->Mode = HAL_I2C_MODE_NONE;
+ 10722              		.loc 1 6543 15 is_stmt 0 view .LVU3682
+ 10723 000c 2022     		movs	r2, #32
+ 10724 000e 80F84120 		strb	r2, [r0, #65]
+6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+ 10725              		.loc 1 6544 3 is_stmt 1 view .LVU3683
+6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+ 10726              		.loc 1 6544 14 is_stmt 0 view .LVU3684
+ 10727 0012 80F84230 		strb	r3, [r0, #66]
+6545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10728              		.loc 1 6545 3 is_stmt 1 view .LVU3685
+6545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10729              		.loc 1 6545 17 is_stmt 0 view .LVU3686
+ 10730 0016 4363     		str	r3, [r0, #52]
+6548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10731              		.loc 1 6548 3 is_stmt 1 view .LVU3687
+6548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10732              		.loc 1 6548 6 is_stmt 0 view .LVU3688
+ 10733 0018 11F0040F 		tst	r1, #4
+ 10734 001c 13D0     		beq	.L678
+6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10735              		.loc 1 6551 5 is_stmt 1 view .LVU3689
+6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10736              		.loc 1 6551 36 is_stmt 0 view .LVU3690
+ 10737 001e 0368     		ldr	r3, [r0]
+6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10738              		.loc 1 6551 46 view .LVU3691
+ 10739 0020 5A6A     		ldr	r2, [r3, #36]
+6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10740              		.loc 1 6551 10 view .LVU3692
+ 10741 0022 436A     		ldr	r3, [r0, #36]
+6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10742              		.loc 1 6551 21 view .LVU3693
+ 10743 0024 1A70     		strb	r2, [r3]
+6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10744              		.loc 1 6554 5 is_stmt 1 view .LVU3694
+6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10745              		.loc 1 6554 9 is_stmt 0 view .LVU3695
+ 10746 0026 436A     		ldr	r3, [r0, #36]
+6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10747              		.loc 1 6554 19 view .LVU3696
+ARM GAS  /tmp/ccVyGVF6.s 			page 383
+
+
+ 10748 0028 0133     		adds	r3, r3, #1
+ 10749 002a 4362     		str	r3, [r0, #36]
+6556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 10750              		.loc 1 6556 5 is_stmt 1 view .LVU3697
+6556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 10751              		.loc 1 6556 14 is_stmt 0 view .LVU3698
+ 10752 002c 038D     		ldrh	r3, [r0, #40]
+6556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 10753              		.loc 1 6556 8 view .LVU3699
+ 10754 002e 53B1     		cbz	r3, .L678
+6558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 10755              		.loc 1 6558 7 is_stmt 1 view .LVU3700
+6558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 10756              		.loc 1 6558 21 is_stmt 0 view .LVU3701
+ 10757 0030 013B     		subs	r3, r3, #1
+ 10758 0032 0385     		strh	r3, [r0, #40]	@ movhi
+6559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10759              		.loc 1 6559 7 is_stmt 1 view .LVU3702
+6559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10760              		.loc 1 6559 11 is_stmt 0 view .LVU3703
+ 10761 0034 438D     		ldrh	r3, [r0, #42]
+ 10762 0036 9BB2     		uxth	r3, r3
+6559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10763              		.loc 1 6559 22 view .LVU3704
+ 10764 0038 013B     		subs	r3, r3, #1
+ 10765 003a 9BB2     		uxth	r3, r3
+ 10766 003c 4385     		strh	r3, [r0, #42]	@ movhi
+6562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 10767              		.loc 1 6562 7 is_stmt 1 view .LVU3705
+6562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 10768              		.loc 1 6562 23 is_stmt 0 view .LVU3706
+ 10769 003e 436C     		ldr	r3, [r0, #68]
+ 10770 0040 43F00403 		orr	r3, r3, #4
+ 10771 0044 4364     		str	r3, [r0, #68]
+ 10772              	.L678:
+6567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10773              		.loc 1 6567 3 is_stmt 1 view .LVU3707
+ 10774 0046 48F20301 		movw	r1, #32771
+ 10775              	.LVL759:
+6567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10776              		.loc 1 6567 3 is_stmt 0 view .LVU3708
+ 10777 004a 2046     		mov	r0, r4
+ 10778              	.LVL760:
+6567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10779              		.loc 1 6567 3 view .LVU3709
+ 10780 004c FFF7FEFF 		bl	I2C_Disable_IRQ
+ 10781              	.LVL761:
+6570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10782              		.loc 1 6570 3 is_stmt 1 view .LVU3710
+ 10783 0050 2368     		ldr	r3, [r4]
+ 10784 0052 1022     		movs	r2, #16
+ 10785 0054 DA61     		str	r2, [r3, #28]
+6573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10786              		.loc 1 6573 3 view .LVU3711
+6573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10787              		.loc 1 6573 3 view .LVU3712
+ 10788 0056 0023     		movs	r3, #0
+ARM GAS  /tmp/ccVyGVF6.s 			page 384
+
+
+ 10789 0058 84F84030 		strb	r3, [r4, #64]
+6573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10790              		.loc 1 6573 3 view .LVU3713
+6579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10791              		.loc 1 6579 3 view .LVU3714
+ 10792 005c 2046     		mov	r0, r4
+ 10793 005e FFF7FEFF 		bl	HAL_I2C_ListenCpltCallback
+ 10794              	.LVL762:
+6581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10795              		.loc 1 6581 1 is_stmt 0 view .LVU3715
+ 10796 0062 10BD     		pop	{r4, pc}
+ 10797              	.LVL763:
+ 10798              	.L681:
+6581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10799              		.loc 1 6581 1 view .LVU3716
+ 10800              		.align	2
+ 10801              	.L680:
+ 10802 0064 0000FFFF 		.word	-65536
+ 10803              		.cfi_endproc
+ 10804              	.LFE203:
+ 10806              		.section	.text.HAL_I2C_MemTxCpltCallback,"ax",%progbits
+ 10807              		.align	1
+ 10808              		.weak	HAL_I2C_MemTxCpltCallback
+ 10809              		.syntax unified
+ 10810              		.thumb
+ 10811              		.thumb_func
+ 10812              		.fpu fpv5-d16
+ 10814              	HAL_I2C_MemTxCpltCallback:
+ 10815              	.LVL764:
+ 10816              	.LFB183:
+4809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10817              		.loc 1 4809 1 is_stmt 1 view -0
+ 10818              		.cfi_startproc
+ 10819              		@ args = 0, pretend = 0, frame = 0
+ 10820              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10821              		@ link register save eliminated.
+4811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10822              		.loc 1 4811 3 view .LVU3718
+4816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10823              		.loc 1 4816 1 is_stmt 0 view .LVU3719
+ 10824 0000 7047     		bx	lr
+ 10825              		.cfi_endproc
+ 10826              	.LFE183:
+ 10828              		.section	.text.HAL_I2C_MemRxCpltCallback,"ax",%progbits
+ 10829              		.align	1
+ 10830              		.weak	HAL_I2C_MemRxCpltCallback
+ 10831              		.syntax unified
+ 10832              		.thumb
+ 10833              		.thumb_func
+ 10834              		.fpu fpv5-d16
+ 10836              	HAL_I2C_MemRxCpltCallback:
+ 10837              	.LVL765:
+ 10838              	.LFB184:
+4825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10839              		.loc 1 4825 1 is_stmt 1 view -0
+ 10840              		.cfi_startproc
+ 10841              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccVyGVF6.s 			page 385
+
+
+ 10842              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10843              		@ link register save eliminated.
+4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10844              		.loc 1 4827 3 view .LVU3721
+4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10845              		.loc 1 4832 1 is_stmt 0 view .LVU3722
+ 10846 0000 7047     		bx	lr
+ 10847              		.cfi_endproc
+ 10848              	.LFE184:
+ 10850              		.section	.text.HAL_I2C_ErrorCallback,"ax",%progbits
+ 10851              		.align	1
+ 10852              		.weak	HAL_I2C_ErrorCallback
+ 10853              		.syntax unified
+ 10854              		.thumb
+ 10855              		.thumb_func
+ 10856              		.fpu fpv5-d16
+ 10858              	HAL_I2C_ErrorCallback:
+ 10859              	.LVL766:
+ 10860              	.LFB185:
+4841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10861              		.loc 1 4841 1 is_stmt 1 view -0
+ 10862              		.cfi_startproc
+ 10863              		@ args = 0, pretend = 0, frame = 0
+ 10864              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10865              		@ link register save eliminated.
+4843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10866              		.loc 1 4843 3 view .LVU3724
+4848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10867              		.loc 1 4848 1 is_stmt 0 view .LVU3725
+ 10868 0000 7047     		bx	lr
+ 10869              		.cfi_endproc
+ 10870              	.LFE185:
+ 10872              		.section	.text.HAL_I2C_AbortCpltCallback,"ax",%progbits
+ 10873              		.align	1
+ 10874              		.weak	HAL_I2C_AbortCpltCallback
+ 10875              		.syntax unified
+ 10876              		.thumb
+ 10877              		.thumb_func
+ 10878              		.fpu fpv5-d16
+ 10880              	HAL_I2C_AbortCpltCallback:
+ 10881              	.LVL767:
+ 10882              	.LFB186:
+4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Prevent unused argument(s) compilation warning */
+ 10883              		.loc 1 4857 1 is_stmt 1 view -0
+ 10884              		.cfi_startproc
+ 10885              		@ args = 0, pretend = 0, frame = 0
+ 10886              		@ frame_needed = 0, uses_anonymous_args = 0
+ 10887              		@ link register save eliminated.
+4859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10888              		.loc 1 4859 3 view .LVU3727
+4864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10889              		.loc 1 4864 1 is_stmt 0 view .LVU3728
+ 10890 0000 7047     		bx	lr
+ 10891              		.cfi_endproc
+ 10892              	.LFE186:
+ 10894              		.section	.text.I2C_TreatErrorCallback,"ax",%progbits
+ 10895              		.align	1
+ARM GAS  /tmp/ccVyGVF6.s 			page 386
+
+
+ 10896              		.syntax unified
+ 10897              		.thumb
+ 10898              		.thumb_func
+ 10899              		.fpu fpv5-d16
+ 10901              	I2C_TreatErrorCallback:
+ 10902              	.LVL768:
+ 10903              	.LFB205:
+6721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_ABORT)
+ 10904              		.loc 1 6721 1 is_stmt 1 view -0
+ 10905              		.cfi_startproc
+ 10906              		@ args = 0, pretend = 0, frame = 0
+ 10907              		@ frame_needed = 0, uses_anonymous_args = 0
+6721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   if (hi2c->State == HAL_I2C_STATE_ABORT)
+ 10908              		.loc 1 6721 1 is_stmt 0 view .LVU3730
+ 10909 0000 08B5     		push	{r3, lr}
+ 10910              	.LCFI121:
+ 10911              		.cfi_def_cfa_offset 8
+ 10912              		.cfi_offset 3, -8
+ 10913              		.cfi_offset 14, -4
+6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10914              		.loc 1 6722 3 is_stmt 1 view .LVU3731
+6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10915              		.loc 1 6722 11 is_stmt 0 view .LVU3732
+ 10916 0002 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 10917 0006 DBB2     		uxtb	r3, r3
+6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 10918              		.loc 1 6722 6 view .LVU3733
+ 10919 0008 602B     		cmp	r3, #96
+ 10920 000a 06D0     		beq	.L690
+6739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10921              		.loc 1 6739 5 is_stmt 1 view .LVU3734
+6739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10922              		.loc 1 6739 25 is_stmt 0 view .LVU3735
+ 10923 000c 0023     		movs	r3, #0
+ 10924 000e 0363     		str	r3, [r0, #48]
+6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10925              		.loc 1 6742 5 is_stmt 1 view .LVU3736
+6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10926              		.loc 1 6742 5 view .LVU3737
+ 10927 0010 80F84030 		strb	r3, [r0, #64]
+6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10928              		.loc 1 6742 5 view .LVU3738
+6748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10929              		.loc 1 6748 5 view .LVU3739
+ 10930 0014 FFF7FEFF 		bl	HAL_I2C_ErrorCallback
+ 10931              	.LVL769:
+ 10932              	.L686:
+6751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10933              		.loc 1 6751 1 is_stmt 0 view .LVU3740
+ 10934 0018 08BD     		pop	{r3, pc}
+ 10935              	.LVL770:
+ 10936              	.L690:
+6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 10937              		.loc 1 6724 5 is_stmt 1 view .LVU3741
+6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 10938              		.loc 1 6724 17 is_stmt 0 view .LVU3742
+ 10939 001a 2023     		movs	r3, #32
+ARM GAS  /tmp/ccVyGVF6.s 			page 387
+
+
+ 10940 001c 80F84130 		strb	r3, [r0, #65]
+6725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10941              		.loc 1 6725 5 is_stmt 1 view .LVU3743
+6725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10942              		.loc 1 6725 25 is_stmt 0 view .LVU3744
+ 10943 0020 0023     		movs	r3, #0
+ 10944 0022 0363     		str	r3, [r0, #48]
+6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10945              		.loc 1 6728 5 is_stmt 1 view .LVU3745
+6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10946              		.loc 1 6728 5 view .LVU3746
+ 10947 0024 80F84030 		strb	r3, [r0, #64]
+6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10948              		.loc 1 6728 5 view .LVU3747
+6734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10949              		.loc 1 6734 5 view .LVU3748
+ 10950 0028 FFF7FEFF 		bl	HAL_I2C_AbortCpltCallback
+ 10951              	.LVL771:
+6734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 10952              		.loc 1 6734 5 is_stmt 0 view .LVU3749
+ 10953 002c F4E7     		b	.L686
+ 10954              		.cfi_endproc
+ 10955              	.LFE205:
+ 10957              		.section	.text.I2C_ITError,"ax",%progbits
+ 10958              		.align	1
+ 10959              		.syntax unified
+ 10960              		.thumb
+ 10961              		.thumb_func
+ 10962              		.fpu fpv5-d16
+ 10964              	I2C_ITError:
+ 10965              	.LVL772:
+ 10966              	.LFB204:
+6590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ 10967              		.loc 1 6590 1 is_stmt 1 view -0
+ 10968              		.cfi_startproc
+ 10969              		@ args = 0, pretend = 0, frame = 0
+ 10970              		@ frame_needed = 0, uses_anonymous_args = 0
+6590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ 10971              		.loc 1 6590 1 is_stmt 0 view .LVU3751
+ 10972 0000 10B5     		push	{r4, lr}
+ 10973              	.LCFI122:
+ 10974              		.cfi_def_cfa_offset 8
+ 10975              		.cfi_offset 4, -8
+ 10976              		.cfi_offset 14, -4
+ 10977 0002 0446     		mov	r4, r0
+6591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10978              		.loc 1 6591 3 is_stmt 1 view .LVU3752
+6591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10979              		.loc 1 6591 24 is_stmt 0 view .LVU3753
+ 10980 0004 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 10981              	.LVL773:
+6593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10982              		.loc 1 6593 3 is_stmt 1 view .LVU3754
+6596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+ 10983              		.loc 1 6596 3 view .LVU3755
+6596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+ 10984              		.loc 1 6596 23 is_stmt 0 view .LVU3756
+ARM GAS  /tmp/ccVyGVF6.s 			page 388
+
+
+ 10985 0008 0020     		movs	r0, #0
+ 10986              	.LVL774:
+6596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+ 10987              		.loc 1 6596 23 view .LVU3757
+ 10988 000a 84F84200 		strb	r0, [r4, #66]
+6597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferCount     = 0U;
+ 10989              		.loc 1 6597 3 is_stmt 1 view .LVU3758
+6597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferCount     = 0U;
+ 10990              		.loc 1 6597 23 is_stmt 0 view .LVU3759
+ 10991 000e 454A     		ldr	r2, .L704
+ 10992 0010 E262     		str	r2, [r4, #44]
+6598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10993              		.loc 1 6598 3 is_stmt 1 view .LVU3760
+6598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10994              		.loc 1 6598 23 is_stmt 0 view .LVU3761
+ 10995 0012 6085     		strh	r0, [r4, #42]	@ movhi
+6601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10996              		.loc 1 6601 3 is_stmt 1 view .LVU3762
+6601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 10997              		.loc 1 6601 19 is_stmt 0 view .LVU3763
+ 10998 0014 626C     		ldr	r2, [r4, #68]
+ 10999 0016 0A43     		orrs	r2, r2, r1
+ 11000 0018 6264     		str	r2, [r4, #68]
+6604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ 11001              		.loc 1 6604 3 is_stmt 1 view .LVU3764
+6605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ 11002              		.loc 1 6605 50 is_stmt 0 view .LVU3765
+ 11003 001a 283B     		subs	r3, r3, #40
+ 11004              	.LVL775:
+6605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ 11005              		.loc 1 6605 50 view .LVU3766
+ 11006 001c DBB2     		uxtb	r3, r3
+6604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ 11007              		.loc 1 6604 6 view .LVU3767
+ 11008 001e 022B     		cmp	r3, #2
+ 11009 0020 2DD8     		bhi	.L692
+6609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11010              		.loc 1 6609 5 is_stmt 1 view .LVU3768
+ 11011 0022 0321     		movs	r1, #3
+ 11012              	.LVL776:
+6609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11013              		.loc 1 6609 5 is_stmt 0 view .LVU3769
+ 11014 0024 2046     		mov	r0, r4
+ 11015 0026 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 11016              	.LVL777:
+6612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR       = I2C_Slave_ISR_IT;
+ 11017              		.loc 1 6612 5 is_stmt 1 view .LVU3770
+6612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferISR       = I2C_Slave_ISR_IT;
+ 11018              		.loc 1 6612 25 is_stmt 0 view .LVU3771
+ 11019 002a 2823     		movs	r3, #40
+ 11020 002c 84F84130 		strb	r3, [r4, #65]
+6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11021              		.loc 1 6613 5 is_stmt 1 view .LVU3772
+6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11022              		.loc 1 6613 25 is_stmt 0 view .LVU3773
+ 11023 0030 3D4B     		ldr	r3, .L704+4
+ 11024 0032 6363     		str	r3, [r4, #52]
+ARM GAS  /tmp/ccVyGVF6.s 			page 389
+
+
+ 11025              	.L693:
+6648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11026              		.loc 1 6648 3 is_stmt 1 view .LVU3774
+6648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11027              		.loc 1 6648 20 is_stmt 0 view .LVU3775
+ 11028 0034 236B     		ldr	r3, [r4, #48]
+ 11029              	.LVL778:
+6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ 11030              		.loc 1 6650 3 is_stmt 1 view .LVU3776
+6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ 11031              		.loc 1 6650 12 is_stmt 0 view .LVU3777
+ 11032 0036 A26B     		ldr	r2, [r4, #56]
+6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ 11033              		.loc 1 6650 6 view .LVU3778
+ 11034 0038 002A     		cmp	r2, #0
+ 11035 003a 49D0     		beq	.L696
+6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ 11036              		.loc 1 6650 30 discriminator 1 view .LVU3779
+ 11037 003c 212B     		cmp	r3, #33
+ 11038 003e 18BF     		it	ne
+ 11039 0040 112B     		cmpne	r3, #17
+ 11040 0042 45D1     		bne	.L696
+6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11041              		.loc 1 6653 5 is_stmt 1 view .LVU3780
+6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11042              		.loc 1 6653 14 is_stmt 0 view .LVU3781
+ 11043 0044 2368     		ldr	r3, [r4]
+ 11044              	.LVL779:
+6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11045              		.loc 1 6653 24 view .LVU3782
+ 11046 0046 1A68     		ldr	r2, [r3]
+6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11047              		.loc 1 6653 8 view .LVU3783
+ 11048 0048 12F4804F 		tst	r2, #16384
+ 11049 004c 03D0     		beq	.L697
+6655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11050              		.loc 1 6655 7 is_stmt 1 view .LVU3784
+6655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11051              		.loc 1 6655 27 is_stmt 0 view .LVU3785
+ 11052 004e 1A68     		ldr	r2, [r3]
+ 11053 0050 22F48042 		bic	r2, r2, #16384
+ 11054 0054 1A60     		str	r2, [r3]
+ 11055              	.L697:
+6658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11056              		.loc 1 6658 5 is_stmt 1 view .LVU3786
+6658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11057              		.loc 1 6658 9 is_stmt 0 view .LVU3787
+ 11058 0056 A06B     		ldr	r0, [r4, #56]
+ 11059 0058 FFF7FEFF 		bl	HAL_DMA_GetState
+ 11060              	.LVL780:
+6658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11061              		.loc 1 6658 8 view .LVU3788
+ 11062 005c 0128     		cmp	r0, #1
+ 11063 005e 33D0     		beq	.L698
+6662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11064              		.loc 1 6662 7 is_stmt 1 view .LVU3789
+6662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 390
+
+
+ 11065              		.loc 1 6662 11 is_stmt 0 view .LVU3790
+ 11066 0060 A36B     		ldr	r3, [r4, #56]
+6662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11067              		.loc 1 6662 39 view .LVU3791
+ 11068 0062 324A     		ldr	r2, .L704+8
+ 11069 0064 1A65     		str	r2, [r3, #80]
+6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11070              		.loc 1 6665 7 is_stmt 1 view .LVU3792
+6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11071              		.loc 1 6665 7 view .LVU3793
+ 11072 0066 0023     		movs	r3, #0
+ 11073 0068 84F84030 		strb	r3, [r4, #64]
+6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11074              		.loc 1 6665 7 view .LVU3794
+6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11075              		.loc 1 6668 7 view .LVU3795
+6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11076              		.loc 1 6668 11 is_stmt 0 view .LVU3796
+ 11077 006c A06B     		ldr	r0, [r4, #56]
+ 11078 006e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 11079              	.LVL781:
+6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11080              		.loc 1 6668 10 view .LVU3797
+ 11081 0072 0028     		cmp	r0, #0
+ 11082 0074 55D0     		beq	.L691
+6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11083              		.loc 1 6671 9 is_stmt 1 view .LVU3798
+6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11084              		.loc 1 6671 13 is_stmt 0 view .LVU3799
+ 11085 0076 A06B     		ldr	r0, [r4, #56]
+6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11086              		.loc 1 6671 21 view .LVU3800
+ 11087 0078 036D     		ldr	r3, [r0, #80]
+6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11088              		.loc 1 6671 9 view .LVU3801
+ 11089 007a 9847     		blx	r3
+ 11090              	.LVL782:
+ 11091 007c 51E0     		b	.L691
+ 11092              	.LVL783:
+ 11093              	.L692:
+6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11094              		.loc 1 6618 5 is_stmt 1 view .LVU3802
+ 11095 007e 48F20301 		movw	r1, #32771
+ 11096              	.LVL784:
+6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11097              		.loc 1 6618 5 is_stmt 0 view .LVU3803
+ 11098 0082 2046     		mov	r0, r4
+ 11099 0084 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 11100              	.LVL785:
+6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11101              		.loc 1 6621 5 is_stmt 1 view .LVU3804
+ 11102 0088 2046     		mov	r0, r4
+ 11103 008a FFF7FEFF 		bl	I2C_Flush_TXDR
+ 11104              	.LVL786:
+6625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11105              		.loc 1 6625 5 view .LVU3805
+6625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccVyGVF6.s 			page 391
+
+
+ 11106              		.loc 1 6625 13 is_stmt 0 view .LVU3806
+ 11107 008e 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11108 0092 DBB2     		uxtb	r3, r3
+6625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11109              		.loc 1 6625 8 view .LVU3807
+ 11110 0094 602B     		cmp	r3, #96
+ 11111 0096 14D0     		beq	.L694
+6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11112              		.loc 1 6628 7 is_stmt 1 view .LVU3808
+6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11113              		.loc 1 6628 27 is_stmt 0 view .LVU3809
+ 11114 0098 2023     		movs	r3, #32
+ 11115 009a 84F84130 		strb	r3, [r4, #65]
+6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11116              		.loc 1 6631 7 is_stmt 1 view .LVU3810
+6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11117              		.loc 1 6631 11 is_stmt 0 view .LVU3811
+ 11118 009e 2368     		ldr	r3, [r4]
+ 11119 00a0 9A69     		ldr	r2, [r3, #24]
+6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11120              		.loc 1 6631 10 view .LVU3812
+ 11121 00a2 12F0200F 		tst	r2, #32
+ 11122 00a6 0CD0     		beq	.L694
+6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 11123              		.loc 1 6633 9 is_stmt 1 view .LVU3813
+6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 11124              		.loc 1 6633 13 is_stmt 0 view .LVU3814
+ 11125 00a8 9A69     		ldr	r2, [r3, #24]
+6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 11126              		.loc 1 6633 12 view .LVU3815
+ 11127 00aa 12F0100F 		tst	r2, #16
+ 11128 00ae 05D0     		beq	.L695
+6635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ 11129              		.loc 1 6635 11 is_stmt 1 view .LVU3816
+ 11130 00b0 1022     		movs	r2, #16
+ 11131 00b2 DA61     		str	r2, [r3, #28]
+6636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 11132              		.loc 1 6636 11 view .LVU3817
+6636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 11133              		.loc 1 6636 27 is_stmt 0 view .LVU3818
+ 11134 00b4 636C     		ldr	r3, [r4, #68]
+ 11135 00b6 43F00403 		orr	r3, r3, #4
+ 11136 00ba 6364     		str	r3, [r4, #68]
+ 11137              	.L695:
+6640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11138              		.loc 1 6640 9 is_stmt 1 view .LVU3819
+ 11139 00bc 2368     		ldr	r3, [r4]
+ 11140 00be 2022     		movs	r2, #32
+ 11141 00c0 DA61     		str	r2, [r3, #28]
+ 11142              	.L694:
+6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11143              		.loc 1 6644 5 view .LVU3820
+6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11144              		.loc 1 6644 25 is_stmt 0 view .LVU3821
+ 11145 00c2 0023     		movs	r3, #0
+ 11146 00c4 6363     		str	r3, [r4, #52]
+ 11147 00c6 B5E7     		b	.L693
+ARM GAS  /tmp/ccVyGVF6.s 			page 392
+
+
+ 11148              	.L698:
+6676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11149              		.loc 1 6676 7 is_stmt 1 view .LVU3822
+ 11150 00c8 2046     		mov	r0, r4
+ 11151 00ca FFF7FEFF 		bl	I2C_TreatErrorCallback
+ 11152              	.LVL787:
+ 11153 00ce 28E0     		b	.L691
+ 11154              	.LVL788:
+ 11155              	.L696:
+6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ 11156              		.loc 1 6680 8 view .LVU3823
+6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ 11157              		.loc 1 6680 17 is_stmt 0 view .LVU3824
+ 11158 00d0 E26B     		ldr	r2, [r4, #60]
+6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ 11159              		.loc 1 6680 11 view .LVU3825
+ 11160 00d2 1AB3     		cbz	r2, .L700
+6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                                       (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ 11161              		.loc 1 6680 35 discriminator 1 view .LVU3826
+ 11162 00d4 222B     		cmp	r3, #34
+ 11163 00d6 18BF     		it	ne
+ 11164 00d8 122B     		cmpne	r3, #18
+ 11165 00da 1FD1     		bne	.L700
+6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11166              		.loc 1 6683 5 is_stmt 1 view .LVU3827
+6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11167              		.loc 1 6683 14 is_stmt 0 view .LVU3828
+ 11168 00dc 2368     		ldr	r3, [r4]
+ 11169              	.LVL789:
+6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11170              		.loc 1 6683 24 view .LVU3829
+ 11171 00de 1A68     		ldr	r2, [r3]
+6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11172              		.loc 1 6683 8 view .LVU3830
+ 11173 00e0 12F4004F 		tst	r2, #32768
+ 11174 00e4 03D0     		beq	.L701
+6685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11175              		.loc 1 6685 7 is_stmt 1 view .LVU3831
+6685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11176              		.loc 1 6685 27 is_stmt 0 view .LVU3832
+ 11177 00e6 1A68     		ldr	r2, [r3]
+ 11178 00e8 22F40042 		bic	r2, r2, #32768
+ 11179 00ec 1A60     		str	r2, [r3]
+ 11180              	.L701:
+6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11181              		.loc 1 6688 5 is_stmt 1 view .LVU3833
+6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11182              		.loc 1 6688 9 is_stmt 0 view .LVU3834
+ 11183 00ee E06B     		ldr	r0, [r4, #60]
+ 11184 00f0 FFF7FEFF 		bl	HAL_DMA_GetState
+ 11185              	.LVL790:
+6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11186              		.loc 1 6688 8 view .LVU3835
+ 11187 00f4 0128     		cmp	r0, #1
+ 11188 00f6 0DD0     		beq	.L702
+6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11189              		.loc 1 6692 7 is_stmt 1 view .LVU3836
+ARM GAS  /tmp/ccVyGVF6.s 			page 393
+
+
+6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11190              		.loc 1 6692 11 is_stmt 0 view .LVU3837
+ 11191 00f8 E36B     		ldr	r3, [r4, #60]
+6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11192              		.loc 1 6692 39 view .LVU3838
+ 11193 00fa 0C4A     		ldr	r2, .L704+8
+ 11194 00fc 1A65     		str	r2, [r3, #80]
+6695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11195              		.loc 1 6695 7 is_stmt 1 view .LVU3839
+6695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11196              		.loc 1 6695 7 view .LVU3840
+ 11197 00fe 0023     		movs	r3, #0
+ 11198 0100 84F84030 		strb	r3, [r4, #64]
+6695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11199              		.loc 1 6695 7 view .LVU3841
+6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11200              		.loc 1 6698 7 view .LVU3842
+6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11201              		.loc 1 6698 11 is_stmt 0 view .LVU3843
+ 11202 0104 E06B     		ldr	r0, [r4, #60]
+ 11203 0106 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 11204              	.LVL791:
+6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11205              		.loc 1 6698 10 view .LVU3844
+ 11206 010a 50B1     		cbz	r0, .L691
+6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11207              		.loc 1 6701 9 is_stmt 1 view .LVU3845
+6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11208              		.loc 1 6701 13 is_stmt 0 view .LVU3846
+ 11209 010c E06B     		ldr	r0, [r4, #60]
+6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11210              		.loc 1 6701 21 view .LVU3847
+ 11211 010e 036D     		ldr	r3, [r0, #80]
+6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11212              		.loc 1 6701 9 view .LVU3848
+ 11213 0110 9847     		blx	r3
+ 11214              	.LVL792:
+ 11215 0112 06E0     		b	.L691
+ 11216              	.L702:
+6706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11217              		.loc 1 6706 7 is_stmt 1 view .LVU3849
+ 11218 0114 2046     		mov	r0, r4
+ 11219 0116 FFF7FEFF 		bl	I2C_TreatErrorCallback
+ 11220              	.LVL793:
+ 11221 011a 02E0     		b	.L691
+ 11222              	.LVL794:
+ 11223              	.L700:
+6711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11224              		.loc 1 6711 5 view .LVU3850
+ 11225 011c 2046     		mov	r0, r4
+ 11226 011e FFF7FEFF 		bl	I2C_TreatErrorCallback
+ 11227              	.LVL795:
+ 11228              	.L691:
+6713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11229              		.loc 1 6713 1 is_stmt 0 view .LVU3851
+ 11230 0122 10BD     		pop	{r4, pc}
+ 11231              	.LVL796:
+ARM GAS  /tmp/ccVyGVF6.s 			page 394
+
+
+ 11232              	.L705:
+6713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11233              		.loc 1 6713 1 view .LVU3852
+ 11234              		.align	2
+ 11235              	.L704:
+ 11236 0124 0000FFFF 		.word	-65536
+ 11237 0128 00000000 		.word	I2C_Slave_ISR_IT
+ 11238 012c 00000000 		.word	I2C_DMAAbort
+ 11239              		.cfi_endproc
+ 11240              	.LFE204:
+ 11242              		.section	.text.I2C_ITSlaveCplt,"ax",%progbits
+ 11243              		.align	1
+ 11244              		.syntax unified
+ 11245              		.thumb
+ 11246              		.thumb_func
+ 11247              		.fpu fpv5-d16
+ 11249              	I2C_ITSlaveCplt:
+ 11250              	.LVL797:
+ 11251              	.LFB202:
+6323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ 11252              		.loc 1 6323 1 is_stmt 1 view -0
+ 11253              		.cfi_startproc
+ 11254              		@ args = 0, pretend = 0, frame = 0
+ 11255              		@ frame_needed = 0, uses_anonymous_args = 0
+6323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ 11256              		.loc 1 6323 1 is_stmt 0 view .LVU3854
+ 11257 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 11258              	.LCFI123:
+ 11259              		.cfi_def_cfa_offset 24
+ 11260              		.cfi_offset 3, -24
+ 11261              		.cfi_offset 4, -20
+ 11262              		.cfi_offset 5, -16
+ 11263              		.cfi_offset 6, -12
+ 11264              		.cfi_offset 7, -8
+ 11265              		.cfi_offset 14, -4
+ 11266 0002 0446     		mov	r4, r0
+ 11267 0004 0D46     		mov	r5, r1
+6324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 11268              		.loc 1 6324 3 is_stmt 1 view .LVU3855
+6324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 11269              		.loc 1 6324 26 is_stmt 0 view .LVU3856
+ 11270 0006 0268     		ldr	r2, [r0]
+6324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 11271              		.loc 1 6324 12 view .LVU3857
+ 11272 0008 1668     		ldr	r6, [r2]
+ 11273              	.LVL798:
+6325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 11274              		.loc 1 6325 3 is_stmt 1 view .LVU3858
+6326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ 11275              		.loc 1 6326 3 view .LVU3859
+6326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ 11276              		.loc 1 6326 12 is_stmt 0 view .LVU3860
+ 11277 000a C76A     		ldr	r7, [r0, #44]
+ 11278              	.LVL799:
+6327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11279              		.loc 1 6327 3 is_stmt 1 view .LVU3861
+6327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 395
+
+
+ 11280              		.loc 1 6327 24 is_stmt 0 view .LVU3862
+ 11281 000c 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 11282 0010 DBB2     		uxtb	r3, r3
+ 11283              	.LVL800:
+6330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11284              		.loc 1 6330 3 is_stmt 1 view .LVU3863
+ 11285 0012 2021     		movs	r1, #32
+ 11286              	.LVL801:
+6330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11287              		.loc 1 6330 3 is_stmt 0 view .LVU3864
+ 11288 0014 D161     		str	r1, [r2, #28]
+6333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11289              		.loc 1 6333 3 is_stmt 1 view .LVU3865
+6333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11290              		.loc 1 6333 6 is_stmt 0 view .LVU3866
+ 11291 0016 292B     		cmp	r3, #41
+ 11292 0018 18BF     		it	ne
+ 11293 001a 212B     		cmpne	r3, #33
+ 11294 001c 74D0     		beq	.L723
+6338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11295              		.loc 1 6338 8 is_stmt 1 view .LVU3867
+6338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11296              		.loc 1 6338 11 is_stmt 0 view .LVU3868
+ 11297 001e 2A2B     		cmp	r3, #42
+ 11298 0020 18BF     		it	ne
+ 11299 0022 222B     		cmpne	r3, #34
+ 11300 0024 77D0     		beq	.L724
+6343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11301              		.loc 1 6343 8 is_stmt 1 view .LVU3869
+6343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11302              		.loc 1 6343 11 is_stmt 0 view .LVU3870
+ 11303 0026 282B     		cmp	r3, #40
+ 11304 0028 7CD0     		beq	.L725
+ 11305              	.LVL802:
+ 11306              	.L708:
+6351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11307              		.loc 1 6351 3 is_stmt 1 view .LVU3871
+6354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11308              		.loc 1 6354 3 view .LVU3872
+6354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11309              		.loc 1 6354 7 is_stmt 0 view .LVU3873
+ 11310 002a 2268     		ldr	r2, [r4]
+6354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11311              		.loc 1 6354 23 view .LVU3874
+ 11312 002c 5368     		ldr	r3, [r2, #4]
+ 11313 002e 43F40043 		orr	r3, r3, #32768
+ 11314 0032 5360     		str	r3, [r2, #4]
+6357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11315              		.loc 1 6357 3 is_stmt 1 view .LVU3875
+ 11316 0034 2268     		ldr	r2, [r4]
+ 11317 0036 5368     		ldr	r3, [r2, #4]
+ 11318 0038 23F0FF73 		bic	r3, r3, #33423360
+ 11319 003c 23F48B33 		bic	r3, r3, #71168
+ 11320 0040 23F4FF73 		bic	r3, r3, #510
+ 11321 0044 23F00103 		bic	r3, r3, #1
+ 11322 0048 5360     		str	r3, [r2, #4]
+6360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 396
+
+
+ 11323              		.loc 1 6360 3 view .LVU3876
+ 11324 004a 2046     		mov	r0, r4
+ 11325 004c FFF7FEFF 		bl	I2C_Flush_TXDR
+ 11326              	.LVL803:
+6363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11327              		.loc 1 6363 3 view .LVU3877
+6363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11328              		.loc 1 6363 6 is_stmt 0 view .LVU3878
+ 11329 0050 16F4804F 		tst	r6, #16384
+ 11330 0054 6DD0     		beq	.L710
+6366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11331              		.loc 1 6366 5 is_stmt 1 view .LVU3879
+6366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11332              		.loc 1 6366 9 is_stmt 0 view .LVU3880
+ 11333 0056 2268     		ldr	r2, [r4]
+6366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11334              		.loc 1 6366 25 view .LVU3881
+ 11335 0058 1368     		ldr	r3, [r2]
+ 11336 005a 23F48043 		bic	r3, r3, #16384
+ 11337 005e 1360     		str	r3, [r2]
+6368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11338              		.loc 1 6368 5 is_stmt 1 view .LVU3882
+6368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11339              		.loc 1 6368 13 is_stmt 0 view .LVU3883
+ 11340 0060 A36B     		ldr	r3, [r4, #56]
+6368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11341              		.loc 1 6368 8 view .LVU3884
+ 11342 0062 1BB1     		cbz	r3, .L711
+6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11343              		.loc 1 6370 7 is_stmt 1 view .LVU3885
+6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11344              		.loc 1 6370 35 is_stmt 0 view .LVU3886
+ 11345 0064 1B68     		ldr	r3, [r3]
+ 11346 0066 5B68     		ldr	r3, [r3, #4]
+6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11347              		.loc 1 6370 25 view .LVU3887
+ 11348 0068 9BB2     		uxth	r3, r3
+6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11349              		.loc 1 6370 23 view .LVU3888
+ 11350 006a 6385     		strh	r3, [r4, #42]	@ movhi
+ 11351              	.L711:
+6386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11352              		.loc 1 6386 3 is_stmt 1 view .LVU3889
+6389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11353              		.loc 1 6389 3 view .LVU3890
+6389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11354              		.loc 1 6389 6 is_stmt 0 view .LVU3891
+ 11355 006c 15F0040F 		tst	r5, #4
+ 11356 0070 11D0     		beq	.L712
+6392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11357              		.loc 1 6392 5 is_stmt 1 view .LVU3892
+6392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11358              		.loc 1 6392 16 is_stmt 0 view .LVU3893
+ 11359 0072 25F00405 		bic	r5, r5, #4
+ 11360              	.LVL804:
+6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11361              		.loc 1 6395 5 is_stmt 1 view .LVU3894
+ARM GAS  /tmp/ccVyGVF6.s 			page 397
+
+
+6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11362              		.loc 1 6395 36 is_stmt 0 view .LVU3895
+ 11363 0076 2368     		ldr	r3, [r4]
+6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11364              		.loc 1 6395 46 view .LVU3896
+ 11365 0078 5A6A     		ldr	r2, [r3, #36]
+6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11366              		.loc 1 6395 10 view .LVU3897
+ 11367 007a 636A     		ldr	r3, [r4, #36]
+6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11368              		.loc 1 6395 21 view .LVU3898
+ 11369 007c 1A70     		strb	r2, [r3]
+6398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11370              		.loc 1 6398 5 is_stmt 1 view .LVU3899
+6398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11371              		.loc 1 6398 9 is_stmt 0 view .LVU3900
+ 11372 007e 636A     		ldr	r3, [r4, #36]
+6398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11373              		.loc 1 6398 19 view .LVU3901
+ 11374 0080 0133     		adds	r3, r3, #1
+ 11375 0082 6362     		str	r3, [r4, #36]
+6400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11376              		.loc 1 6400 5 is_stmt 1 view .LVU3902
+6400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11377              		.loc 1 6400 14 is_stmt 0 view .LVU3903
+ 11378 0084 238D     		ldrh	r3, [r4, #40]
+6400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11379              		.loc 1 6400 8 view .LVU3904
+ 11380 0086 33B1     		cbz	r3, .L712
+6402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 11381              		.loc 1 6402 7 is_stmt 1 view .LVU3905
+6402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 11382              		.loc 1 6402 21 is_stmt 0 view .LVU3906
+ 11383 0088 013B     		subs	r3, r3, #1
+ 11384 008a 2385     		strh	r3, [r4, #40]	@ movhi
+6403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11385              		.loc 1 6403 7 is_stmt 1 view .LVU3907
+6403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11386              		.loc 1 6403 11 is_stmt 0 view .LVU3908
+ 11387 008c 638D     		ldrh	r3, [r4, #42]
+ 11388 008e 9BB2     		uxth	r3, r3
+6403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11389              		.loc 1 6403 22 view .LVU3909
+ 11390 0090 013B     		subs	r3, r3, #1
+ 11391 0092 9BB2     		uxth	r3, r3
+ 11392 0094 6385     		strh	r3, [r4, #42]	@ movhi
+ 11393              	.L712:
+6408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11394              		.loc 1 6408 3 is_stmt 1 view .LVU3910
+6408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11395              		.loc 1 6408 11 is_stmt 0 view .LVU3911
+ 11396 0096 638D     		ldrh	r3, [r4, #42]
+ 11397 0098 9BB2     		uxth	r3, r3
+6408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11398              		.loc 1 6408 6 view .LVU3912
+ 11399 009a 1BB1     		cbz	r3, .L713
+6411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccVyGVF6.s 			page 398
+
+
+ 11400              		.loc 1 6411 5 is_stmt 1 view .LVU3913
+6411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11401              		.loc 1 6411 21 is_stmt 0 view .LVU3914
+ 11402 009c 636C     		ldr	r3, [r4, #68]
+ 11403 009e 43F00403 		orr	r3, r3, #4
+ 11404 00a2 6364     		str	r3, [r4, #68]
+ 11405              	.L713:
+6414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
+ 11406              		.loc 1 6414 3 is_stmt 1 view .LVU3915
+6414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
+ 11407              		.loc 1 6414 6 is_stmt 0 view .LVU3916
+ 11408 00a4 15F0100F 		tst	r5, #16
+ 11409 00a8 13D0     		beq	.L714
+6414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
+ 11410              		.loc 1 6414 58 discriminator 1 view .LVU3917
+ 11411 00aa 16F0100F 		tst	r6, #16
+ 11412 00ae 10D0     		beq	.L714
+6421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11413              		.loc 1 6421 5 is_stmt 1 view .LVU3918
+6421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11414              		.loc 1 6421 13 is_stmt 0 view .LVU3919
+ 11415 00b0 638D     		ldrh	r3, [r4, #42]
+ 11416 00b2 9BB2     		uxth	r3, r3
+6421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11417              		.loc 1 6421 8 view .LVU3920
+ 11418 00b4 002B     		cmp	r3, #0
+ 11419 00b6 61D1     		bne	.L715
+6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11420              		.loc 1 6423 7 is_stmt 1 view .LVU3921
+6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11421              		.loc 1 6423 16 is_stmt 0 view .LVU3922
+ 11422 00b8 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11423 00bc DBB2     		uxtb	r3, r3
+6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11424              		.loc 1 6423 10 view .LVU3923
+ 11425 00be 282B     		cmp	r3, #40
+ 11426 00c0 47D0     		beq	.L726
+ 11427              	.L716:
+6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11428              		.loc 1 6430 12 is_stmt 1 view .LVU3924
+6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11429              		.loc 1 6430 21 is_stmt 0 view .LVU3925
+ 11430 00c2 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11431 00c6 DBB2     		uxtb	r3, r3
+6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11432              		.loc 1 6430 15 view .LVU3926
+ 11433 00c8 292B     		cmp	r3, #41
+ 11434 00ca 4AD0     		beq	.L727
+ 11435              	.L717:
+6445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11436              		.loc 1 6445 9 is_stmt 1 view .LVU3927
+ 11437 00cc 2368     		ldr	r3, [r4]
+ 11438 00ce 1022     		movs	r2, #16
+ 11439 00d0 DA61     		str	r2, [r3, #28]
+ 11440              	.L714:
+6465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+ 11441              		.loc 1 6465 3 view .LVU3928
+ARM GAS  /tmp/ccVyGVF6.s 			page 399
+
+
+6465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferISR = NULL;
+ 11442              		.loc 1 6465 14 is_stmt 0 view .LVU3929
+ 11443 00d2 0023     		movs	r3, #0
+ 11444 00d4 84F84230 		strb	r3, [r4, #66]
+6466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11445              		.loc 1 6466 3 is_stmt 1 view .LVU3930
+6466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11446              		.loc 1 6466 17 is_stmt 0 view .LVU3931
+ 11447 00d8 6363     		str	r3, [r4, #52]
+6468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11448              		.loc 1 6468 3 is_stmt 1 view .LVU3932
+6468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11449              		.loc 1 6468 11 is_stmt 0 view .LVU3933
+ 11450 00da 636C     		ldr	r3, [r4, #68]
+6468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11451              		.loc 1 6468 6 view .LVU3934
+ 11452 00dc 002B     		cmp	r3, #0
+ 11453 00de 5ED1     		bne	.L728
+6480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11454              		.loc 1 6480 8 is_stmt 1 view .LVU3935
+6480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11455              		.loc 1 6480 16 is_stmt 0 view .LVU3936
+ 11456 00e0 E36A     		ldr	r3, [r4, #44]
+6480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11457              		.loc 1 6480 11 view .LVU3937
+ 11458 00e2 13F5803F 		cmn	r3, #65536
+ 11459 00e6 68D1     		bne	.L729
+6500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11460              		.loc 1 6500 8 is_stmt 1 view .LVU3938
+6500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11461              		.loc 1 6500 16 is_stmt 0 view .LVU3939
+ 11462 00e8 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11463 00ec DBB2     		uxtb	r3, r3
+6500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11464              		.loc 1 6500 11 view .LVU3940
+ 11465 00ee 222B     		cmp	r3, #34
+ 11466 00f0 73D0     		beq	.L730
+6517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11467              		.loc 1 6517 5 is_stmt 1 view .LVU3941
+6517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11468              		.loc 1 6517 17 is_stmt 0 view .LVU3942
+ 11469 00f2 2023     		movs	r3, #32
+ 11470 00f4 84F84130 		strb	r3, [r4, #65]
+6518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11471              		.loc 1 6518 5 is_stmt 1 view .LVU3943
+6518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11472              		.loc 1 6518 25 is_stmt 0 view .LVU3944
+ 11473 00f8 0023     		movs	r3, #0
+ 11474 00fa 2363     		str	r3, [r4, #48]
+6521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11475              		.loc 1 6521 5 is_stmt 1 view .LVU3945
+6521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11476              		.loc 1 6521 5 view .LVU3946
+ 11477 00fc 84F84030 		strb	r3, [r4, #64]
+6521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11478              		.loc 1 6521 5 view .LVU3947
+6527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ARM GAS  /tmp/ccVyGVF6.s 			page 400
+
+
+ 11479              		.loc 1 6527 5 view .LVU3948
+ 11480 0100 2046     		mov	r0, r4
+ 11481 0102 FFF7FEFF 		bl	HAL_I2C_SlaveTxCpltCallback
+ 11482              	.LVL805:
+6530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11483              		.loc 1 6530 1 is_stmt 0 view .LVU3949
+ 11484 0106 67E0     		b	.L706
+ 11485              	.LVL806:
+ 11486              	.L723:
+6335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ 11487              		.loc 1 6335 5 is_stmt 1 view .LVU3950
+ 11488 0108 48F20101 		movw	r1, #32769
+ 11489 010c FFF7FEFF 		bl	I2C_Disable_IRQ
+ 11490              	.LVL807:
+6336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11491              		.loc 1 6336 5 view .LVU3951
+6336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11492              		.loc 1 6336 25 is_stmt 0 view .LVU3952
+ 11493 0110 2123     		movs	r3, #33
+ 11494 0112 2363     		str	r3, [r4, #48]
+ 11495 0114 89E7     		b	.L708
+ 11496              	.LVL808:
+ 11497              	.L724:
+6340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ 11498              		.loc 1 6340 5 is_stmt 1 view .LVU3953
+ 11499 0116 48F20201 		movw	r1, #32770
+ 11500 011a FFF7FEFF 		bl	I2C_Disable_IRQ
+ 11501              	.LVL809:
+6341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11502              		.loc 1 6341 5 view .LVU3954
+6341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11503              		.loc 1 6341 25 is_stmt 0 view .LVU3955
+ 11504 011e 2223     		movs	r3, #34
+ 11505 0120 2363     		str	r3, [r4, #48]
+ 11506 0122 82E7     		b	.L708
+ 11507              	.LVL810:
+ 11508              	.L725:
+6345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11509              		.loc 1 6345 5 is_stmt 1 view .LVU3956
+ 11510 0124 48F20301 		movw	r1, #32771
+ 11511 0128 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 11512              	.LVL811:
+6346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11513              		.loc 1 6346 5 view .LVU3957
+6346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11514              		.loc 1 6346 25 is_stmt 0 view .LVU3958
+ 11515 012c 0023     		movs	r3, #0
+ 11516 012e 2363     		str	r3, [r4, #48]
+ 11517 0130 7BE7     		b	.L708
+ 11518              	.L710:
+6373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11519              		.loc 1 6373 8 is_stmt 1 view .LVU3959
+6373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 11520              		.loc 1 6373 11 is_stmt 0 view .LVU3960
+ 11521 0132 16F4004F 		tst	r6, #32768
+ 11522 0136 99D0     		beq	.L711
+6376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 401
+
+
+ 11523              		.loc 1 6376 5 is_stmt 1 view .LVU3961
+6376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11524              		.loc 1 6376 9 is_stmt 0 view .LVU3962
+ 11525 0138 2268     		ldr	r2, [r4]
+6376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11526              		.loc 1 6376 25 view .LVU3963
+ 11527 013a 1368     		ldr	r3, [r2]
+ 11528 013c 23F40043 		bic	r3, r3, #32768
+ 11529 0140 1360     		str	r3, [r2]
+6378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11530              		.loc 1 6378 5 is_stmt 1 view .LVU3964
+6378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11531              		.loc 1 6378 13 is_stmt 0 view .LVU3965
+ 11532 0142 E36B     		ldr	r3, [r4, #60]
+6378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11533              		.loc 1 6378 8 view .LVU3966
+ 11534 0144 002B     		cmp	r3, #0
+ 11535 0146 91D0     		beq	.L711
+6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11536              		.loc 1 6380 7 is_stmt 1 view .LVU3967
+6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11537              		.loc 1 6380 35 is_stmt 0 view .LVU3968
+ 11538 0148 1B68     		ldr	r3, [r3]
+ 11539 014a 5B68     		ldr	r3, [r3, #4]
+6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11540              		.loc 1 6380 25 view .LVU3969
+ 11541 014c 9BB2     		uxth	r3, r3
+6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11542              		.loc 1 6380 23 view .LVU3970
+ 11543 014e 6385     		strh	r3, [r4, #42]	@ movhi
+ 11544 0150 8CE7     		b	.L711
+ 11545              	.LVL812:
+ 11546              	.L726:
+6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11547              		.loc 1 6423 49 discriminator 1 view .LVU3971
+ 11548 0152 B7F1007F 		cmp	r7, #33554432
+ 11549 0156 B4D1     		bne	.L716
+6428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11550              		.loc 1 6428 9 is_stmt 1 view .LVU3972
+ 11551 0158 2946     		mov	r1, r5
+ 11552 015a 2046     		mov	r0, r4
+ 11553 015c FFF7FEFF 		bl	I2C_ITListenCplt
+ 11554              	.LVL813:
+ 11555 0160 B7E7     		b	.L714
+ 11556              	.L727:
+6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11557              		.loc 1 6430 62 is_stmt 0 discriminator 1 view .LVU3973
+ 11558 0162 17F5803F 		cmn	r7, #65536
+ 11559 0166 B1D0     		beq	.L717
+6433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11560              		.loc 1 6433 9 is_stmt 1 view .LVU3974
+ 11561 0168 2368     		ldr	r3, [r4]
+ 11562 016a 1022     		movs	r2, #16
+ 11563 016c DA61     		str	r2, [r3, #28]
+6436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11564              		.loc 1 6436 9 view .LVU3975
+ 11565 016e 2046     		mov	r0, r4
+ARM GAS  /tmp/ccVyGVF6.s 			page 402
+
+
+ 11566 0170 FFF7FEFF 		bl	I2C_Flush_TXDR
+ 11567              	.LVL814:
+6440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11568              		.loc 1 6440 9 view .LVU3976
+ 11569 0174 2046     		mov	r0, r4
+ 11570 0176 FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 11571              	.LVL815:
+ 11572 017a AAE7     		b	.L714
+ 11573              	.L715:
+6452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11574              		.loc 1 6452 7 view .LVU3977
+ 11575 017c 2368     		ldr	r3, [r4]
+ 11576 017e 1022     		movs	r2, #16
+ 11577 0180 DA61     		str	r2, [r3, #28]
+6455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11578              		.loc 1 6455 7 view .LVU3978
+6455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11579              		.loc 1 6455 23 is_stmt 0 view .LVU3979
+ 11580 0182 636C     		ldr	r3, [r4, #68]
+ 11581 0184 43F00403 		orr	r3, r3, #4
+ 11582 0188 6364     		str	r3, [r4, #68]
+6457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11583              		.loc 1 6457 7 is_stmt 1 view .LVU3980
+6457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11584              		.loc 1 6457 10 is_stmt 0 view .LVU3981
+ 11585 018a B7F1807F 		cmp	r7, #16777216
+ 11586 018e 18BF     		it	ne
+ 11587 0190 002F     		cmpne	r7, #0
+ 11588 0192 9ED1     		bne	.L714
+6460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11589              		.loc 1 6460 9 is_stmt 1 view .LVU3982
+ 11590 0194 616C     		ldr	r1, [r4, #68]
+ 11591 0196 2046     		mov	r0, r4
+ 11592 0198 FFF7FEFF 		bl	I2C_ITError
+ 11593              	.LVL816:
+ 11594 019c 99E7     		b	.L714
+ 11595              	.L728:
+6471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11596              		.loc 1 6471 5 view .LVU3983
+ 11597 019e 616C     		ldr	r1, [r4, #68]
+ 11598 01a0 2046     		mov	r0, r4
+ 11599 01a2 FFF7FEFF 		bl	I2C_ITError
+ 11600              	.LVL817:
+6474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11601              		.loc 1 6474 5 view .LVU3984
+6474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11602              		.loc 1 6474 13 is_stmt 0 view .LVU3985
+ 11603 01a6 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11604 01aa DBB2     		uxtb	r3, r3
+6474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11605              		.loc 1 6474 8 view .LVU3986
+ 11606 01ac 282B     		cmp	r3, #40
+ 11607 01ae 13D1     		bne	.L706
+6477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11608              		.loc 1 6477 7 is_stmt 1 view .LVU3987
+ 11609 01b0 2946     		mov	r1, r5
+ 11610 01b2 2046     		mov	r0, r4
+ARM GAS  /tmp/ccVyGVF6.s 			page 403
+
+
+ 11611 01b4 FFF7FEFF 		bl	I2C_ITListenCplt
+ 11612              	.LVL818:
+ 11613 01b8 0EE0     		b	.L706
+ 11614              	.L729:
+6483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11615              		.loc 1 6483 5 view .LVU3988
+ 11616 01ba 2046     		mov	r0, r4
+ 11617 01bc FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 11618              	.LVL819:
+6485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 11619              		.loc 1 6485 5 view .LVU3989
+6485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 11620              		.loc 1 6485 23 is_stmt 0 view .LVU3990
+ 11621 01c0 0B4B     		ldr	r3, .L731
+ 11622 01c2 E362     		str	r3, [r4, #44]
+6486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11623              		.loc 1 6486 5 is_stmt 1 view .LVU3991
+6486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11624              		.loc 1 6486 17 is_stmt 0 view .LVU3992
+ 11625 01c4 2023     		movs	r3, #32
+ 11626 01c6 84F84130 		strb	r3, [r4, #65]
+6487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11627              		.loc 1 6487 5 is_stmt 1 view .LVU3993
+6487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11628              		.loc 1 6487 25 is_stmt 0 view .LVU3994
+ 11629 01ca 0023     		movs	r3, #0
+ 11630 01cc 2363     		str	r3, [r4, #48]
+6490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11631              		.loc 1 6490 5 is_stmt 1 view .LVU3995
+6490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11632              		.loc 1 6490 5 view .LVU3996
+ 11633 01ce 84F84030 		strb	r3, [r4, #64]
+6490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11634              		.loc 1 6490 5 view .LVU3997
+6496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 11635              		.loc 1 6496 5 view .LVU3998
+ 11636 01d2 2046     		mov	r0, r4
+ 11637 01d4 FFF7FEFF 		bl	HAL_I2C_ListenCpltCallback
+ 11638              	.LVL820:
+ 11639              	.L706:
+6530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11640              		.loc 1 6530 1 is_stmt 0 view .LVU3999
+ 11641 01d8 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 11642              	.LVL821:
+ 11643              	.L730:
+6502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11644              		.loc 1 6502 5 is_stmt 1 view .LVU4000
+6502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 11645              		.loc 1 6502 17 is_stmt 0 view .LVU4001
+ 11646 01da 2023     		movs	r3, #32
+ 11647 01dc 84F84130 		strb	r3, [r4, #65]
+6503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11648              		.loc 1 6503 5 is_stmt 1 view .LVU4002
+6503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11649              		.loc 1 6503 25 is_stmt 0 view .LVU4003
+ 11650 01e0 0023     		movs	r3, #0
+ 11651 01e2 2363     		str	r3, [r4, #48]
+ARM GAS  /tmp/ccVyGVF6.s 			page 404
+
+
+6506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11652              		.loc 1 6506 5 is_stmt 1 view .LVU4004
+6506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11653              		.loc 1 6506 5 view .LVU4005
+ 11654 01e4 84F84030 		strb	r3, [r4, #64]
+6506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11655              		.loc 1 6506 5 view .LVU4006
+6512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 11656              		.loc 1 6512 5 view .LVU4007
+ 11657 01e8 2046     		mov	r0, r4
+ 11658 01ea FFF7FEFF 		bl	HAL_I2C_SlaveRxCpltCallback
+ 11659              	.LVL822:
+ 11660 01ee F3E7     		b	.L706
+ 11661              	.L732:
+ 11662              		.align	2
+ 11663              	.L731:
+ 11664 01f0 0000FFFF 		.word	-65536
+ 11665              		.cfi_endproc
+ 11666              	.LFE202:
+ 11668              		.section	.text.I2C_Slave_ISR_IT,"ax",%progbits
+ 11669              		.align	1
+ 11670              		.syntax unified
+ 11671              		.thumb
+ 11672              		.thumb_func
+ 11673              		.fpu fpv5-d16
+ 11675              	I2C_Slave_ISR_IT:
+ 11676              	.LVL823:
+ 11677              	.LFB192:
+5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 11678              		.loc 1 5259 1 view -0
+ 11679              		.cfi_startproc
+ 11680              		@ args = 0, pretend = 0, frame = 0
+ 11681              		@ frame_needed = 0, uses_anonymous_args = 0
+5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 11682              		.loc 1 5259 1 is_stmt 0 view .LVU4009
+ 11683 0000 10B5     		push	{r4, lr}
+ 11684              	.LCFI124:
+ 11685              		.cfi_def_cfa_offset 8
+ 11686              		.cfi_offset 4, -8
+ 11687              		.cfi_offset 14, -4
+ 11688 0002 0446     		mov	r4, r0
+5260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 11689              		.loc 1 5260 3 is_stmt 1 view .LVU4010
+5260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 11690              		.loc 1 5260 12 is_stmt 0 view .LVU4011
+ 11691 0004 C06A     		ldr	r0, [r0, #44]
+ 11692              	.LVL824:
+5261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11693              		.loc 1 5261 3 is_stmt 1 view .LVU4012
+5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11694              		.loc 1 5264 3 view .LVU4013
+5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11695              		.loc 1 5264 3 view .LVU4014
+ 11696 0006 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 11697 000a 012B     		cmp	r3, #1
+ 11698 000c 00F09B80 		beq	.L745
+5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ARM GAS  /tmp/ccVyGVF6.s 			page 405
+
+
+ 11699              		.loc 1 5264 3 discriminator 2 view .LVU4015
+ 11700 0010 0123     		movs	r3, #1
+ 11701 0012 84F84030 		strb	r3, [r4, #64]
+5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11702              		.loc 1 5264 3 discriminator 2 view .LVU4016
+5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 11703              		.loc 1 5267 3 discriminator 2 view .LVU4017
+5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 11704              		.loc 1 5267 6 is_stmt 0 discriminator 2 view .LVU4018
+ 11705 0016 11F0200F 		tst	r1, #32
+ 11706 001a 02D0     		beq	.L735
+5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 11707              		.loc 1 5267 61 discriminator 1 view .LVU4019
+ 11708 001c 12F0200F 		tst	r2, #32
+ 11709 0020 16D1     		bne	.L747
+ 11710              	.L735:
+5273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 11711              		.loc 1 5273 8 is_stmt 1 view .LVU4020
+5273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 11712              		.loc 1 5273 11 is_stmt 0 view .LVU4021
+ 11713 0022 11F0100F 		tst	r1, #16
+ 11714 0026 3FD0     		beq	.L737
+5273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 11715              		.loc 1 5273 63 discriminator 1 view .LVU4022
+ 11716 0028 12F0100F 		tst	r2, #16
+ 11717 002c 3CD0     		beq	.L737
+5280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11718              		.loc 1 5280 5 is_stmt 1 view .LVU4023
+5280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11719              		.loc 1 5280 13 is_stmt 0 view .LVU4024
+ 11720 002e 638D     		ldrh	r3, [r4, #42]
+ 11721 0030 9BB2     		uxth	r3, r3
+5280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11722              		.loc 1 5280 8 view .LVU4025
+ 11723 0032 43BB     		cbnz	r3, .L738
+5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11724              		.loc 1 5282 7 is_stmt 1 view .LVU4026
+5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11725              		.loc 1 5282 16 is_stmt 0 view .LVU4027
+ 11726 0034 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11727 0038 DBB2     		uxtb	r3, r3
+5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11728              		.loc 1 5282 10 view .LVU4028
+ 11729 003a 282B     		cmp	r3, #40
+ 11730 003c 0FD0     		beq	.L748
+ 11731              	.L739:
+5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11732              		.loc 1 5289 12 is_stmt 1 view .LVU4029
+5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11733              		.loc 1 5289 21 is_stmt 0 view .LVU4030
+ 11734 003e 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 11735 0042 DBB2     		uxtb	r3, r3
+5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11736              		.loc 1 5289 15 view .LVU4031
+ 11737 0044 292B     		cmp	r3, #41
+ 11738 0046 11D0     		beq	.L749
+ 11739              	.L740:
+ARM GAS  /tmp/ccVyGVF6.s 			page 406
+
+
+5304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11740              		.loc 1 5304 9 is_stmt 1 view .LVU4032
+ 11741 0048 2368     		ldr	r3, [r4]
+ 11742 004a 1022     		movs	r2, #16
+ 11743              	.LVL825:
+5304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11744              		.loc 1 5304 9 is_stmt 0 view .LVU4033
+ 11745 004c DA61     		str	r2, [r3, #28]
+ 11746 004e 02E0     		b	.L736
+ 11747              	.LVL826:
+ 11748              	.L747:
+5271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11749              		.loc 1 5271 5 is_stmt 1 view .LVU4034
+ 11750 0050 2046     		mov	r0, r4
+ 11751              	.LVL827:
+5271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11752              		.loc 1 5271 5 is_stmt 0 view .LVU4035
+ 11753 0052 FFF7FEFF 		bl	I2C_ITSlaveCplt
+ 11754              	.LVL828:
+ 11755              	.L736:
+5381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11756              		.loc 1 5381 3 is_stmt 1 view .LVU4036
+5384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11757              		.loc 1 5384 3 view .LVU4037
+5384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11758              		.loc 1 5384 3 view .LVU4038
+ 11759 0056 0020     		movs	r0, #0
+ 11760 0058 84F84000 		strb	r0, [r4, #64]
+5384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11761              		.loc 1 5384 3 view .LVU4039
+5386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 11762              		.loc 1 5386 3 view .LVU4040
+ 11763              	.L734:
+5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11764              		.loc 1 5387 1 is_stmt 0 view .LVU4041
+ 11765 005c 10BD     		pop	{r4, pc}
+ 11766              	.LVL829:
+ 11767              	.L748:
+5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 11768              		.loc 1 5282 49 discriminator 1 view .LVU4042
+ 11769 005e B0F1007F 		cmp	r0, #33554432
+ 11770 0062 ECD1     		bne	.L739
+5287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11771              		.loc 1 5287 9 is_stmt 1 view .LVU4043
+ 11772 0064 2046     		mov	r0, r4
+ 11773              	.LVL830:
+5287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11774              		.loc 1 5287 9 is_stmt 0 view .LVU4044
+ 11775 0066 FFF7FEFF 		bl	I2C_ITListenCplt
+ 11776              	.LVL831:
+5287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11777              		.loc 1 5287 9 view .LVU4045
+ 11778 006a F4E7     		b	.L736
+ 11779              	.LVL832:
+ 11780              	.L749:
+5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11781              		.loc 1 5289 62 discriminator 1 view .LVU4046
+ARM GAS  /tmp/ccVyGVF6.s 			page 407
+
+
+ 11782 006c 10F5803F 		cmn	r0, #65536
+ 11783 0070 EAD0     		beq	.L740
+5292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11784              		.loc 1 5292 9 is_stmt 1 view .LVU4047
+ 11785 0072 2368     		ldr	r3, [r4]
+ 11786 0074 1022     		movs	r2, #16
+ 11787              	.LVL833:
+5292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11788              		.loc 1 5292 9 is_stmt 0 view .LVU4048
+ 11789 0076 DA61     		str	r2, [r3, #28]
+5295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11790              		.loc 1 5295 9 is_stmt 1 view .LVU4049
+ 11791 0078 2046     		mov	r0, r4
+ 11792              	.LVL834:
+5295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11793              		.loc 1 5295 9 is_stmt 0 view .LVU4050
+ 11794 007a FFF7FEFF 		bl	I2C_Flush_TXDR
+ 11795              	.LVL835:
+5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11796              		.loc 1 5299 9 is_stmt 1 view .LVU4051
+ 11797 007e 2046     		mov	r0, r4
+ 11798 0080 FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 11799              	.LVL836:
+ 11800 0084 E7E7     		b	.L736
+ 11801              	.LVL837:
+ 11802              	.L738:
+5311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11803              		.loc 1 5311 7 view .LVU4052
+ 11804 0086 2368     		ldr	r3, [r4]
+ 11805 0088 1022     		movs	r2, #16
+ 11806              	.LVL838:
+5311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11807              		.loc 1 5311 7 is_stmt 0 view .LVU4053
+ 11808 008a DA61     		str	r2, [r3, #28]
+5314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11809              		.loc 1 5314 7 is_stmt 1 view .LVU4054
+5314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11810              		.loc 1 5314 23 is_stmt 0 view .LVU4055
+ 11811 008c 636C     		ldr	r3, [r4, #68]
+ 11812 008e 43F00403 		orr	r3, r3, #4
+ 11813 0092 6364     		str	r3, [r4, #68]
+5316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11814              		.loc 1 5316 7 is_stmt 1 view .LVU4056
+5316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11815              		.loc 1 5316 10 is_stmt 0 view .LVU4057
+ 11816 0094 B0F1807F 		cmp	r0, #16777216
+ 11817 0098 18BF     		it	ne
+ 11818 009a 0028     		cmpne	r0, #0
+ 11819 009c DBD1     		bne	.L736
+5319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11820              		.loc 1 5319 9 is_stmt 1 view .LVU4058
+ 11821 009e 616C     		ldr	r1, [r4, #68]
+ 11822              	.LVL839:
+5319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11823              		.loc 1 5319 9 is_stmt 0 view .LVU4059
+ 11824 00a0 2046     		mov	r0, r4
+ 11825              	.LVL840:
+ARM GAS  /tmp/ccVyGVF6.s 			page 408
+
+
+5319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11826              		.loc 1 5319 9 view .LVU4060
+ 11827 00a2 FFF7FEFF 		bl	I2C_ITError
+ 11828              	.LVL841:
+ 11829 00a6 D6E7     		b	.L736
+ 11830              	.LVL842:
+ 11831              	.L737:
+5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 11832              		.loc 1 5323 8 is_stmt 1 view .LVU4061
+5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 11833              		.loc 1 5323 11 is_stmt 0 view .LVU4062
+ 11834 00a8 11F0040F 		tst	r1, #4
+ 11835 00ac 1FD0     		beq	.L741
+5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 11836              		.loc 1 5323 65 discriminator 1 view .LVU4063
+ 11837 00ae 12F0040F 		tst	r2, #4
+ 11838 00b2 1CD0     		beq	.L741
+5326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11839              		.loc 1 5326 5 is_stmt 1 view .LVU4064
+5326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11840              		.loc 1 5326 13 is_stmt 0 view .LVU4065
+ 11841 00b4 638D     		ldrh	r3, [r4, #42]
+ 11842 00b6 9BB2     		uxth	r3, r3
+5326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11843              		.loc 1 5326 8 view .LVU4066
+ 11844 00b8 73B1     		cbz	r3, .L742
+5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11845              		.loc 1 5329 7 is_stmt 1 view .LVU4067
+5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11846              		.loc 1 5329 38 is_stmt 0 view .LVU4068
+ 11847 00ba 2368     		ldr	r3, [r4]
+5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11848              		.loc 1 5329 48 view .LVU4069
+ 11849 00bc 5A6A     		ldr	r2, [r3, #36]
+ 11850              	.LVL843:
+5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11851              		.loc 1 5329 12 view .LVU4070
+ 11852 00be 636A     		ldr	r3, [r4, #36]
+5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11853              		.loc 1 5329 23 view .LVU4071
+ 11854 00c0 1A70     		strb	r2, [r3]
+5332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11855              		.loc 1 5332 7 is_stmt 1 view .LVU4072
+5332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11856              		.loc 1 5332 11 is_stmt 0 view .LVU4073
+ 11857 00c2 636A     		ldr	r3, [r4, #36]
+5332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11858              		.loc 1 5332 21 view .LVU4074
+ 11859 00c4 0133     		adds	r3, r3, #1
+ 11860 00c6 6362     		str	r3, [r4, #36]
+5334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 11861              		.loc 1 5334 7 is_stmt 1 view .LVU4075
+5334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 11862              		.loc 1 5334 11 is_stmt 0 view .LVU4076
+ 11863 00c8 238D     		ldrh	r3, [r4, #40]
+5334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 11864              		.loc 1 5334 21 view .LVU4077
+ARM GAS  /tmp/ccVyGVF6.s 			page 409
+
+
+ 11865 00ca 013B     		subs	r3, r3, #1
+ 11866 00cc 2385     		strh	r3, [r4, #40]	@ movhi
+5335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11867              		.loc 1 5335 7 is_stmt 1 view .LVU4078
+5335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11868              		.loc 1 5335 11 is_stmt 0 view .LVU4079
+ 11869 00ce 638D     		ldrh	r3, [r4, #42]
+ 11870 00d0 9BB2     		uxth	r3, r3
+5335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11871              		.loc 1 5335 22 view .LVU4080
+ 11872 00d2 013B     		subs	r3, r3, #1
+ 11873 00d4 9BB2     		uxth	r3, r3
+ 11874 00d6 6385     		strh	r3, [r4, #42]	@ movhi
+ 11875              	.L742:
+5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (tmpoptions != I2C_NO_OPTION_FRAME))
+ 11876              		.loc 1 5338 5 is_stmt 1 view .LVU4081
+5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (tmpoptions != I2C_NO_OPTION_FRAME))
+ 11877              		.loc 1 5338 14 is_stmt 0 view .LVU4082
+ 11878 00d8 638D     		ldrh	r3, [r4, #42]
+ 11879 00da 9BB2     		uxth	r3, r3
+5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (tmpoptions != I2C_NO_OPTION_FRAME))
+ 11880              		.loc 1 5338 8 view .LVU4083
+ 11881 00dc 002B     		cmp	r3, #0
+ 11882 00de BAD1     		bne	.L736
+5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (tmpoptions != I2C_NO_OPTION_FRAME))
+ 11883              		.loc 1 5338 33 discriminator 1 view .LVU4084
+ 11884 00e0 10F5803F 		cmn	r0, #65536
+ 11885 00e4 B7D0     		beq	.L736
+5342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11886              		.loc 1 5342 7 is_stmt 1 view .LVU4085
+ 11887 00e6 2046     		mov	r0, r4
+ 11888              	.LVL844:
+5342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11889              		.loc 1 5342 7 is_stmt 0 view .LVU4086
+ 11890 00e8 FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 11891              	.LVL845:
+5342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11892              		.loc 1 5342 7 view .LVU4087
+ 11893 00ec B3E7     		b	.L736
+ 11894              	.LVL846:
+ 11895              	.L741:
+5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 11896              		.loc 1 5345 8 is_stmt 1 view .LVU4088
+5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 11897              		.loc 1 5345 11 is_stmt 0 view .LVU4089
+ 11898 00ee 11F0080F 		tst	r1, #8
+ 11899 00f2 02D0     		beq	.L743
+5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 11900              		.loc 1 5345 65 discriminator 1 view .LVU4090
+ 11901 00f4 12F0080F 		tst	r2, #8
+ 11902 00f8 18D1     		bne	.L750
+ 11903              	.L743:
+5350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 11904              		.loc 1 5350 8 is_stmt 1 view .LVU4091
+5350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 11905              		.loc 1 5350 11 is_stmt 0 view .LVU4092
+ 11906 00fa 11F0020F 		tst	r1, #2
+ARM GAS  /tmp/ccVyGVF6.s 			page 410
+
+
+ 11907 00fe AAD0     		beq	.L736
+5350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 11908              		.loc 1 5350 65 discriminator 1 view .LVU4093
+ 11909 0100 12F0020F 		tst	r2, #2
+ 11910 0104 A7D0     		beq	.L736
+5357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11911              		.loc 1 5357 5 is_stmt 1 view .LVU4094
+5357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11912              		.loc 1 5357 13 is_stmt 0 view .LVU4095
+ 11913 0106 638D     		ldrh	r3, [r4, #42]
+ 11914 0108 9BB2     		uxth	r3, r3
+5357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 11915              		.loc 1 5357 8 view .LVU4096
+ 11916 010a 9BB1     		cbz	r3, .L744
+5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11917              		.loc 1 5360 7 is_stmt 1 view .LVU4097
+5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11918              		.loc 1 5360 35 is_stmt 0 view .LVU4098
+ 11919 010c 626A     		ldr	r2, [r4, #36]
+ 11920              	.LVL847:
+5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11921              		.loc 1 5360 11 view .LVU4099
+ 11922 010e 2368     		ldr	r3, [r4]
+5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11923              		.loc 1 5360 30 view .LVU4100
+ 11924 0110 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11925              		.loc 1 5360 28 view .LVU4101
+ 11926 0112 9A62     		str	r2, [r3, #40]
+5363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11927              		.loc 1 5363 7 is_stmt 1 view .LVU4102
+5363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11928              		.loc 1 5363 11 is_stmt 0 view .LVU4103
+ 11929 0114 636A     		ldr	r3, [r4, #36]
+5363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11930              		.loc 1 5363 21 view .LVU4104
+ 11931 0116 0133     		adds	r3, r3, #1
+ 11932 0118 6362     		str	r3, [r4, #36]
+5365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 11933              		.loc 1 5365 7 is_stmt 1 view .LVU4105
+5365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 11934              		.loc 1 5365 11 is_stmt 0 view .LVU4106
+ 11935 011a 638D     		ldrh	r3, [r4, #42]
+ 11936 011c 9BB2     		uxth	r3, r3
+5365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferSize--;
+ 11937              		.loc 1 5365 22 view .LVU4107
+ 11938 011e 013B     		subs	r3, r3, #1
+ 11939 0120 9BB2     		uxth	r3, r3
+ 11940 0122 6385     		strh	r3, [r4, #42]	@ movhi
+5366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11941              		.loc 1 5366 7 is_stmt 1 view .LVU4108
+5366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11942              		.loc 1 5366 11 is_stmt 0 view .LVU4109
+ 11943 0124 238D     		ldrh	r3, [r4, #40]
+5366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 11944              		.loc 1 5366 21 view .LVU4110
+ 11945 0126 013B     		subs	r3, r3, #1
+ARM GAS  /tmp/ccVyGVF6.s 			page 411
+
+
+ 11946 0128 2385     		strh	r3, [r4, #40]	@ movhi
+ 11947 012a 94E7     		b	.L736
+ 11948              	.LVL848:
+ 11949              	.L750:
+5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11950              		.loc 1 5348 5 is_stmt 1 view .LVU4111
+ 11951 012c 2046     		mov	r0, r4
+ 11952              	.LVL849:
+5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11953              		.loc 1 5348 5 is_stmt 0 view .LVU4112
+ 11954 012e FFF7FEFF 		bl	I2C_ITAddrCplt
+ 11955              	.LVL850:
+5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 11956              		.loc 1 5348 5 view .LVU4113
+ 11957 0132 90E7     		b	.L736
+ 11958              	.LVL851:
+ 11959              	.L744:
+5370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11960              		.loc 1 5370 7 is_stmt 1 view .LVU4114
+5370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 11961              		.loc 1 5370 10 is_stmt 0 view .LVU4115
+ 11962 0134 0028     		cmp	r0, #0
+ 11963 0136 18BF     		it	ne
+ 11964 0138 B0F1807F 		cmpne	r0, #16777216
+ 11965 013c 8BD1     		bne	.L736
+5374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11966              		.loc 1 5374 9 is_stmt 1 view .LVU4116
+ 11967 013e 2046     		mov	r0, r4
+ 11968              	.LVL852:
+5374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11969              		.loc 1 5374 9 is_stmt 0 view .LVU4117
+ 11970 0140 FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 11971              	.LVL853:
+5374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 11972              		.loc 1 5374 9 view .LVU4118
+ 11973 0144 87E7     		b	.L736
+ 11974              	.LVL854:
+ 11975              	.L745:
+5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11976              		.loc 1 5264 3 view .LVU4119
+ 11977 0146 0220     		movs	r0, #2
+ 11978              	.LVL855:
+5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 11979              		.loc 1 5264 3 view .LVU4120
+ 11980 0148 88E7     		b	.L734
+ 11981              		.cfi_endproc
+ 11982              	.LFE192:
+ 11984              		.section	.text.I2C_ITMasterCplt,"ax",%progbits
+ 11985              		.align	1
+ 11986              		.syntax unified
+ 11987              		.thumb
+ 11988              		.thumb_func
+ 11989              		.fpu fpv5-d16
+ 11991              	I2C_ITMasterCplt:
+ 11992              	.LVL856:
+ 11993              	.LFB201:
+6180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmperror;
+ARM GAS  /tmp/ccVyGVF6.s 			page 412
+
+
+ 11994              		.loc 1 6180 1 is_stmt 1 view -0
+ 11995              		.cfi_startproc
+ 11996              		@ args = 0, pretend = 0, frame = 8
+ 11997              		@ frame_needed = 0, uses_anonymous_args = 0
+6180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmperror;
+ 11998              		.loc 1 6180 1 is_stmt 0 view .LVU4122
+ 11999 0000 30B5     		push	{r4, r5, lr}
+ 12000              	.LCFI125:
+ 12001              		.cfi_def_cfa_offset 12
+ 12002              		.cfi_offset 4, -12
+ 12003              		.cfi_offset 5, -8
+ 12004              		.cfi_offset 14, -4
+ 12005 0002 83B0     		sub	sp, sp, #12
+ 12006              	.LCFI126:
+ 12007              		.cfi_def_cfa_offset 24
+ 12008 0004 0446     		mov	r4, r0
+ 12009 0006 0D46     		mov	r5, r1
+6181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 12010              		.loc 1 6181 3 is_stmt 1 view .LVU4123
+6182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   __IO uint32_t tmpreg;
+ 12011              		.loc 1 6182 3 view .LVU4124
+ 12012              	.LVL857:
+6183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12013              		.loc 1 6183 3 view .LVU4125
+6186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12014              		.loc 1 6186 3 view .LVU4126
+ 12015 0008 0368     		ldr	r3, [r0]
+ 12016 000a 2022     		movs	r2, #32
+ 12017 000c DA61     		str	r2, [r3, #28]
+6189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12018              		.loc 1 6189 3 view .LVU4127
+6189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12019              		.loc 1 6189 11 is_stmt 0 view .LVU4128
+ 12020 000e 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 12021 0012 DBB2     		uxtb	r3, r3
+6189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12022              		.loc 1 6189 6 view .LVU4129
+ 12023 0014 212B     		cmp	r3, #33
+ 12024 0016 33D0     		beq	.L763
+6194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12025              		.loc 1 6194 8 is_stmt 1 view .LVU4130
+6194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12026              		.loc 1 6194 16 is_stmt 0 view .LVU4131
+ 12027 0018 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 12028 001c DBB2     		uxtb	r3, r3
+6194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12029              		.loc 1 6194 11 view .LVU4132
+ 12030 001e 222B     		cmp	r3, #34
+ 12031 0020 34D0     		beq	.L764
+ 12032              	.LVL858:
+ 12033              	.L753:
+6202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12034              		.loc 1 6202 3 is_stmt 1 view .LVU4133
+6205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12035              		.loc 1 6205 3 view .LVU4134
+ 12036 0022 2268     		ldr	r2, [r4]
+ 12037 0024 5368     		ldr	r3, [r2, #4]
+ARM GAS  /tmp/ccVyGVF6.s 			page 413
+
+
+ 12038 0026 23F0FF73 		bic	r3, r3, #33423360
+ 12039 002a 23F48B33 		bic	r3, r3, #71168
+ 12040 002e 23F4FF73 		bic	r3, r3, #510
+ 12041 0032 23F00103 		bic	r3, r3, #1
+ 12042 0036 5360     		str	r3, [r2, #4]
+6208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+ 12043              		.loc 1 6208 3 view .LVU4135
+6208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+ 12044              		.loc 1 6208 23 is_stmt 0 view .LVU4136
+ 12045 0038 0023     		movs	r3, #0
+ 12046 003a 6363     		str	r3, [r4, #52]
+6209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12047              		.loc 1 6209 3 is_stmt 1 view .LVU4137
+6209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12048              		.loc 1 6209 23 is_stmt 0 view .LVU4138
+ 12049 003c A3F58033 		sub	r3, r3, #65536
+ 12050 0040 E362     		str	r3, [r4, #44]
+6211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12051              		.loc 1 6211 3 is_stmt 1 view .LVU4139
+6211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12052              		.loc 1 6211 6 is_stmt 0 view .LVU4140
+ 12053 0042 15F0100F 		tst	r5, #16
+ 12054 0046 06D0     		beq	.L754
+6214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12055              		.loc 1 6214 5 is_stmt 1 view .LVU4141
+ 12056 0048 2368     		ldr	r3, [r4]
+ 12057 004a 1022     		movs	r2, #16
+ 12058 004c DA61     		str	r2, [r3, #28]
+6217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12059              		.loc 1 6217 5 view .LVU4142
+6217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12060              		.loc 1 6217 21 is_stmt 0 view .LVU4143
+ 12061 004e 636C     		ldr	r3, [r4, #68]
+ 12062 0050 43F00403 		orr	r3, r3, #4
+ 12063 0054 6364     		str	r3, [r4, #68]
+ 12064              	.L754:
+6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12065              		.loc 1 6221 3 is_stmt 1 view .LVU4144
+6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12066              		.loc 1 6221 12 is_stmt 0 view .LVU4145
+ 12067 0056 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 12068 005a DBB2     		uxtb	r3, r3
+6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12069              		.loc 1 6221 6 view .LVU4146
+ 12070 005c 602B     		cmp	r3, #96
+ 12071 005e 1BD0     		beq	.L765
+ 12072              	.L755:
+6229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12073              		.loc 1 6229 3 is_stmt 1 view .LVU4147
+ 12074 0060 2046     		mov	r0, r4
+ 12075 0062 FFF7FEFF 		bl	I2C_Flush_TXDR
+ 12076              	.LVL859:
+6232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12077              		.loc 1 6232 3 view .LVU4148
+6232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12078              		.loc 1 6232 12 is_stmt 0 view .LVU4149
+ 12079 0066 626C     		ldr	r2, [r4, #68]
+ARM GAS  /tmp/ccVyGVF6.s 			page 414
+
+
+ 12080              	.LVL860:
+6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12081              		.loc 1 6235 3 is_stmt 1 view .LVU4150
+6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12082              		.loc 1 6235 12 is_stmt 0 view .LVU4151
+ 12083 0068 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 12084 006c DBB2     		uxtb	r3, r3
+6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12085              		.loc 1 6235 6 view .LVU4152
+ 12086 006e 602B     		cmp	r3, #96
+ 12087 0070 00D0     		beq	.L756
+6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12088              		.loc 1 6235 44 discriminator 1 view .LVU4153
+ 12089 0072 D2B1     		cbz	r2, .L757
+ 12090              	.L756:
+6238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12091              		.loc 1 6238 5 is_stmt 1 view .LVU4154
+ 12092 0074 616C     		ldr	r1, [r4, #68]
+ 12093 0076 2046     		mov	r0, r4
+ 12094 0078 FFF7FEFF 		bl	I2C_ITError
+ 12095              	.LVL861:
+ 12096              	.L751:
+6314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12097              		.loc 1 6314 1 is_stmt 0 view .LVU4155
+ 12098 007c 03B0     		add	sp, sp, #12
+ 12099              	.LCFI127:
+ 12100              		.cfi_remember_state
+ 12101              		.cfi_def_cfa_offset 12
+ 12102              		@ sp needed
+ 12103 007e 30BD     		pop	{r4, r5, pc}
+ 12104              	.LVL862:
+ 12105              	.L763:
+ 12106              	.LCFI128:
+ 12107              		.cfi_restore_state
+6191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 12108              		.loc 1 6191 5 is_stmt 1 view .LVU4156
+ 12109 0080 0121     		movs	r1, #1
+ 12110              	.LVL863:
+6191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ 12111              		.loc 1 6191 5 is_stmt 0 view .LVU4157
+ 12112 0082 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 12113              	.LVL864:
+6192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12114              		.loc 1 6192 5 is_stmt 1 view .LVU4158
+6192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12115              		.loc 1 6192 25 is_stmt 0 view .LVU4159
+ 12116 0086 1123     		movs	r3, #17
+ 12117 0088 2363     		str	r3, [r4, #48]
+ 12118 008a CAE7     		b	.L753
+ 12119              	.LVL865:
+ 12120              	.L764:
+6196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 12121              		.loc 1 6196 5 is_stmt 1 view .LVU4160
+ 12122 008c 0221     		movs	r1, #2
+ 12123              	.LVL866:
+6196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ 12124              		.loc 1 6196 5 is_stmt 0 view .LVU4161
+ARM GAS  /tmp/ccVyGVF6.s 			page 415
+
+
+ 12125 008e FFF7FEFF 		bl	I2C_Disable_IRQ
+ 12126              	.LVL867:
+6197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12127              		.loc 1 6197 5 is_stmt 1 view .LVU4162
+6197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12128              		.loc 1 6197 25 is_stmt 0 view .LVU4163
+ 12129 0092 1223     		movs	r3, #18
+ 12130 0094 2363     		str	r3, [r4, #48]
+ 12131 0096 C4E7     		b	.L753
+ 12132              	.L765:
+6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12133              		.loc 1 6221 44 discriminator 1 view .LVU4164
+ 12134 0098 15F0040F 		tst	r5, #4
+ 12135 009c E0D0     		beq	.L755
+6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     UNUSED(tmpreg);
+ 12136              		.loc 1 6224 5 is_stmt 1 view .LVU4165
+6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     UNUSED(tmpreg);
+ 12137              		.loc 1 6224 27 is_stmt 0 view .LVU4166
+ 12138 009e 2368     		ldr	r3, [r4]
+6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     UNUSED(tmpreg);
+ 12139              		.loc 1 6224 37 view .LVU4167
+ 12140 00a0 5B6A     		ldr	r3, [r3, #36]
+ 12141 00a2 DBB2     		uxtb	r3, r3
+6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     UNUSED(tmpreg);
+ 12142              		.loc 1 6224 12 view .LVU4168
+ 12143 00a4 0193     		str	r3, [sp, #4]
+6225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12144              		.loc 1 6225 5 is_stmt 1 view .LVU4169
+ 12145 00a6 019B     		ldr	r3, [sp, #4]
+ 12146 00a8 DAE7     		b	.L755
+ 12147              	.LVL868:
+ 12148              	.L757:
+6241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12149              		.loc 1 6241 8 view .LVU4170
+6241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12150              		.loc 1 6241 16 is_stmt 0 view .LVU4171
+ 12151 00aa 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 12152 00ae DBB2     		uxtb	r3, r3
+6241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12153              		.loc 1 6241 11 view .LVU4172
+ 12154 00b0 212B     		cmp	r3, #33
+ 12155 00b2 17D0     		beq	.L766
+6276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12156              		.loc 1 6276 8 is_stmt 1 view .LVU4173
+6276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12157              		.loc 1 6276 16 is_stmt 0 view .LVU4174
+ 12158 00b4 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 12159 00b8 DBB2     		uxtb	r3, r3
+6276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 12160              		.loc 1 6276 11 view .LVU4175
+ 12161 00ba 222B     		cmp	r3, #34
+ 12162 00bc DED1     		bne	.L751
+6278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 12163              		.loc 1 6278 5 is_stmt 1 view .LVU4176
+6278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 12164              		.loc 1 6278 17 is_stmt 0 view .LVU4177
+ 12165 00be 2023     		movs	r3, #32
+ARM GAS  /tmp/ccVyGVF6.s 			page 416
+
+
+ 12166 00c0 84F84130 		strb	r3, [r4, #65]
+6279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12167              		.loc 1 6279 5 is_stmt 1 view .LVU4178
+6279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12168              		.loc 1 6279 25 is_stmt 0 view .LVU4179
+ 12169 00c4 0023     		movs	r3, #0
+ 12170 00c6 2363     		str	r3, [r4, #48]
+6281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12171              		.loc 1 6281 5 is_stmt 1 view .LVU4180
+6281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12172              		.loc 1 6281 13 is_stmt 0 view .LVU4181
+ 12173 00c8 94F84230 		ldrb	r3, [r4, #66]	@ zero_extendqisi2
+ 12174 00cc DBB2     		uxtb	r3, r3
+6281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12175              		.loc 1 6281 8 view .LVU4182
+ 12176 00ce 402B     		cmp	r3, #64
+ 12177 00d0 24D0     		beq	.L767
+6297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12178              		.loc 1 6297 7 is_stmt 1 view .LVU4183
+6297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12179              		.loc 1 6297 18 is_stmt 0 view .LVU4184
+ 12180 00d2 0023     		movs	r3, #0
+ 12181 00d4 84F84230 		strb	r3, [r4, #66]
+6300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12182              		.loc 1 6300 7 is_stmt 1 view .LVU4185
+6300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12183              		.loc 1 6300 7 view .LVU4186
+ 12184 00d8 84F84030 		strb	r3, [r4, #64]
+6300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12185              		.loc 1 6300 7 view .LVU4187
+6306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 12186              		.loc 1 6306 7 view .LVU4188
+ 12187 00dc 2046     		mov	r0, r4
+ 12188 00de FFF7FEFF 		bl	HAL_I2C_MasterRxCpltCallback
+ 12189              	.LVL869:
+6313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 12190              		.loc 1 6313 3 view .LVU4189
+6314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12191              		.loc 1 6314 1 is_stmt 0 view .LVU4190
+ 12192 00e2 CBE7     		b	.L751
+ 12193              	.LVL870:
+ 12194              	.L766:
+6243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 12195              		.loc 1 6243 5 is_stmt 1 view .LVU4191
+6243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->PreviousState = I2C_STATE_NONE;
+ 12196              		.loc 1 6243 17 is_stmt 0 view .LVU4192
+ 12197 00e4 2023     		movs	r3, #32
+ 12198 00e6 84F84130 		strb	r3, [r4, #65]
+6244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12199              		.loc 1 6244 5 is_stmt 1 view .LVU4193
+6244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12200              		.loc 1 6244 25 is_stmt 0 view .LVU4194
+ 12201 00ea 0023     		movs	r3, #0
+ 12202 00ec 2363     		str	r3, [r4, #48]
+6246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12203              		.loc 1 6246 5 is_stmt 1 view .LVU4195
+6246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ARM GAS  /tmp/ccVyGVF6.s 			page 417
+
+
+ 12204              		.loc 1 6246 13 is_stmt 0 view .LVU4196
+ 12205 00ee 94F84230 		ldrb	r3, [r4, #66]	@ zero_extendqisi2
+ 12206 00f2 DBB2     		uxtb	r3, r3
+6246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12207              		.loc 1 6246 8 view .LVU4197
+ 12208 00f4 402B     		cmp	r3, #64
+ 12209 00f6 08D0     		beq	.L768
+6262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12210              		.loc 1 6262 7 is_stmt 1 view .LVU4198
+6262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12211              		.loc 1 6262 18 is_stmt 0 view .LVU4199
+ 12212 00f8 0023     		movs	r3, #0
+ 12213 00fa 84F84230 		strb	r3, [r4, #66]
+6265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12214              		.loc 1 6265 7 is_stmt 1 view .LVU4200
+6265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12215              		.loc 1 6265 7 view .LVU4201
+ 12216 00fe 84F84030 		strb	r3, [r4, #64]
+6265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12217              		.loc 1 6265 7 view .LVU4202
+6271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 12218              		.loc 1 6271 7 view .LVU4203
+ 12219 0102 2046     		mov	r0, r4
+ 12220 0104 FFF7FEFF 		bl	HAL_I2C_MasterTxCpltCallback
+ 12221              	.LVL871:
+6271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 12222              		.loc 1 6271 7 is_stmt 0 view .LVU4204
+ 12223 0108 B8E7     		b	.L751
+ 12224              	.LVL872:
+ 12225              	.L768:
+6248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12226              		.loc 1 6248 7 is_stmt 1 view .LVU4205
+6248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12227              		.loc 1 6248 18 is_stmt 0 view .LVU4206
+ 12228 010a 0023     		movs	r3, #0
+ 12229 010c 84F84230 		strb	r3, [r4, #66]
+6251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12230              		.loc 1 6251 7 is_stmt 1 view .LVU4207
+6251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12231              		.loc 1 6251 7 view .LVU4208
+ 12232 0110 84F84030 		strb	r3, [r4, #64]
+6251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12233              		.loc 1 6251 7 view .LVU4209
+6257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 12234              		.loc 1 6257 7 view .LVU4210
+ 12235 0114 2046     		mov	r0, r4
+ 12236 0116 FFF7FEFF 		bl	HAL_I2C_MemTxCpltCallback
+ 12237              	.LVL873:
+6257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 12238              		.loc 1 6257 7 is_stmt 0 view .LVU4211
+ 12239 011a AFE7     		b	.L751
+ 12240              	.LVL874:
+ 12241              	.L767:
+6283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12242              		.loc 1 6283 7 is_stmt 1 view .LVU4212
+6283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12243              		.loc 1 6283 18 is_stmt 0 view .LVU4213
+ARM GAS  /tmp/ccVyGVF6.s 			page 418
+
+
+ 12244 011c 0023     		movs	r3, #0
+ 12245 011e 84F84230 		strb	r3, [r4, #66]
+6286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12246              		.loc 1 6286 7 is_stmt 1 view .LVU4214
+6286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12247              		.loc 1 6286 7 view .LVU4215
+ 12248 0122 84F84030 		strb	r3, [r4, #64]
+6286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12249              		.loc 1 6286 7 view .LVU4216
+6292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 12250              		.loc 1 6292 7 view .LVU4217
+ 12251 0126 2046     		mov	r0, r4
+ 12252 0128 FFF7FEFF 		bl	HAL_I2C_MemRxCpltCallback
+ 12253              	.LVL875:
+6292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ 12254              		.loc 1 6292 7 is_stmt 0 view .LVU4218
+ 12255 012c A6E7     		b	.L751
+ 12256              		.cfi_endproc
+ 12257              	.LFE201:
+ 12259              		.section	.text.I2C_Master_ISR_IT,"ax",%progbits
+ 12260              		.align	1
+ 12261              		.syntax unified
+ 12262              		.thumb
+ 12263              		.thumb_func
+ 12264              		.fpu fpv5-d16
+ 12266              	I2C_Master_ISR_IT:
+ 12267              	.LVL876:
+ 12268              	.LFB190:
+4941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t devaddress;
+ 12269              		.loc 1 4941 1 is_stmt 1 view -0
+ 12270              		.cfi_startproc
+ 12271              		@ args = 0, pretend = 0, frame = 0
+ 12272              		@ frame_needed = 0, uses_anonymous_args = 0
+4942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 12273              		.loc 1 4942 3 view .LVU4220
+4943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12274              		.loc 1 4943 3 view .LVU4221
+4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12275              		.loc 1 4946 3 view .LVU4222
+4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12276              		.loc 1 4946 3 view .LVU4223
+ 12277 0000 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 12278 0004 012B     		cmp	r3, #1
+ 12279 0006 00F0CF80 		beq	.L785
+4941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t devaddress;
+ 12280              		.loc 1 4941 1 is_stmt 0 discriminator 2 view .LVU4224
+ 12281 000a 70B5     		push	{r4, r5, r6, lr}
+ 12282              	.LCFI129:
+ 12283              		.cfi_def_cfa_offset 16
+ 12284              		.cfi_offset 4, -16
+ 12285              		.cfi_offset 5, -12
+ 12286              		.cfi_offset 6, -8
+ 12287              		.cfi_offset 14, -4
+ 12288 000c 82B0     		sub	sp, sp, #8
+ 12289              	.LCFI130:
+ 12290              		.cfi_def_cfa_offset 24
+ 12291 000e 0446     		mov	r4, r0
+ARM GAS  /tmp/ccVyGVF6.s 			page 419
+
+
+ 12292 0010 0D46     		mov	r5, r1
+ 12293 0012 1646     		mov	r6, r2
+4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12294              		.loc 1 4946 3 is_stmt 1 discriminator 2 view .LVU4225
+ 12295 0014 0123     		movs	r3, #1
+ 12296 0016 80F84030 		strb	r3, [r0, #64]
+4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12297              		.loc 1 4946 3 discriminator 2 view .LVU4226
+4948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12298              		.loc 1 4948 3 discriminator 2 view .LVU4227
+4948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12299              		.loc 1 4948 6 is_stmt 0 discriminator 2 view .LVU4228
+ 12300 001a 11F0100F 		tst	r1, #16
+ 12301 001e 02D0     		beq	.L771
+4948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12302              		.loc 1 4948 58 discriminator 1 view .LVU4229
+ 12303 0020 12F0100F 		tst	r2, #16
+ 12304 0024 22D1     		bne	.L790
+ 12305              	.L771:
+4962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 12306              		.loc 1 4962 8 is_stmt 1 view .LVU4230
+4962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 12307              		.loc 1 4962 11 is_stmt 0 view .LVU4231
+ 12308 0026 15F0040F 		tst	r5, #4
+ 12309 002a 29D0     		beq	.L773
+4962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 12310              		.loc 1 4962 65 discriminator 1 view .LVU4232
+ 12311 002c 16F0040F 		tst	r6, #4
+ 12312 0030 26D0     		beq	.L773
+4966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12313              		.loc 1 4966 5 is_stmt 1 view .LVU4233
+4966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12314              		.loc 1 4966 16 is_stmt 0 view .LVU4234
+ 12315 0032 25F00405 		bic	r5, r5, #4
+ 12316              	.LVL877:
+4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12317              		.loc 1 4969 5 is_stmt 1 view .LVU4235
+4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12318              		.loc 1 4969 36 is_stmt 0 view .LVU4236
+ 12319 0036 2368     		ldr	r3, [r4]
+4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12320              		.loc 1 4969 46 view .LVU4237
+ 12321 0038 5A6A     		ldr	r2, [r3, #36]
+ 12322              	.LVL878:
+4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12323              		.loc 1 4969 10 view .LVU4238
+ 12324 003a 636A     		ldr	r3, [r4, #36]
+4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12325              		.loc 1 4969 21 view .LVU4239
+ 12326 003c 1A70     		strb	r2, [r3]
+4972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12327              		.loc 1 4972 5 is_stmt 1 view .LVU4240
+4972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12328              		.loc 1 4972 9 is_stmt 0 view .LVU4241
+ 12329 003e 636A     		ldr	r3, [r4, #36]
+4972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12330              		.loc 1 4972 19 view .LVU4242
+ARM GAS  /tmp/ccVyGVF6.s 			page 420
+
+
+ 12331 0040 0133     		adds	r3, r3, #1
+ 12332 0042 6362     		str	r3, [r4, #36]
+4974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount--;
+ 12333              		.loc 1 4974 5 is_stmt 1 view .LVU4243
+4974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount--;
+ 12334              		.loc 1 4974 9 is_stmt 0 view .LVU4244
+ 12335 0044 238D     		ldrh	r3, [r4, #40]
+4974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount--;
+ 12336              		.loc 1 4974 19 view .LVU4245
+ 12337 0046 013B     		subs	r3, r3, #1
+ 12338 0048 2385     		strh	r3, [r4, #40]	@ movhi
+4975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12339              		.loc 1 4975 5 is_stmt 1 view .LVU4246
+4975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12340              		.loc 1 4975 9 is_stmt 0 view .LVU4247
+ 12341 004a 638D     		ldrh	r3, [r4, #42]
+ 12342 004c 9BB2     		uxth	r3, r3
+4975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12343              		.loc 1 4975 20 view .LVU4248
+ 12344 004e 013B     		subs	r3, r3, #1
+ 12345 0050 9BB2     		uxth	r3, r3
+ 12346 0052 6385     		strh	r3, [r4, #42]	@ movhi
+ 12347              	.LVL879:
+ 12348              	.L772:
+5075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12349              		.loc 1 5075 3 is_stmt 1 view .LVU4249
+5077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 12350              		.loc 1 5077 3 view .LVU4250
+5077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 12351              		.loc 1 5077 6 is_stmt 0 view .LVU4251
+ 12352 0054 15F0200F 		tst	r5, #32
+ 12353 0058 03D0     		beq	.L784
+5077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 12354              		.loc 1 5077 61 discriminator 1 view .LVU4252
+ 12355 005a 16F0200F 		tst	r6, #32
+ 12356 005e 40F09E80 		bne	.L791
+ 12357              	.L784:
+5085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12358              		.loc 1 5085 3 is_stmt 1 view .LVU4253
+5085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12359              		.loc 1 5085 3 view .LVU4254
+ 12360 0062 0020     		movs	r0, #0
+ 12361 0064 84F84000 		strb	r0, [r4, #64]
+5085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12362              		.loc 1 5085 3 view .LVU4255
+5087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 12363              		.loc 1 5087 3 view .LVU4256
+5088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12364              		.loc 1 5088 1 is_stmt 0 view .LVU4257
+ 12365 0068 02B0     		add	sp, sp, #8
+ 12366              	.LCFI131:
+ 12367              		.cfi_remember_state
+ 12368              		.cfi_def_cfa_offset 16
+ 12369              		@ sp needed
+ 12370 006a 70BD     		pop	{r4, r5, r6, pc}
+ 12371              	.LVL880:
+ 12372              	.L790:
+ARM GAS  /tmp/ccVyGVF6.s 			page 421
+
+
+ 12373              	.LCFI132:
+ 12374              		.cfi_restore_state
+4952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12375              		.loc 1 4952 5 is_stmt 1 view .LVU4258
+ 12376 006c 0368     		ldr	r3, [r0]
+ 12377 006e 1022     		movs	r2, #16
+ 12378              	.LVL881:
+4952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12379              		.loc 1 4952 5 is_stmt 0 view .LVU4259
+ 12380 0070 DA61     		str	r2, [r3, #28]
+4957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12381              		.loc 1 4957 5 is_stmt 1 view .LVU4260
+4957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12382              		.loc 1 4957 21 is_stmt 0 view .LVU4261
+ 12383 0072 436C     		ldr	r3, [r0, #68]
+ 12384 0074 43F00403 		orr	r3, r3, #4
+ 12385 0078 4364     		str	r3, [r0, #68]
+4960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12386              		.loc 1 4960 5 is_stmt 1 view .LVU4262
+ 12387 007a FFF7FEFF 		bl	I2C_Flush_TXDR
+ 12388              	.LVL882:
+4960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12389              		.loc 1 4960 5 is_stmt 0 view .LVU4263
+ 12390 007e E9E7     		b	.L772
+ 12391              	.LVL883:
+ 12392              	.L773:
+4977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ 12393              		.loc 1 4977 8 is_stmt 1 view .LVU4264
+4977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ 12394              		.loc 1 4977 13 is_stmt 0 view .LVU4265
+ 12395 0080 C5F38013 		ubfx	r3, r5, #6, #1
+4977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ 12396              		.loc 1 4977 11 view .LVU4266
+ 12397 0084 15F0400F 		tst	r5, #64
+ 12398 0088 19D1     		bne	.L774
+4977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ 12399              		.loc 1 4977 63 discriminator 1 view .LVU4267
+ 12400 008a 15F0020F 		tst	r5, #2
+ 12401 008e 16D0     		beq	.L774
+4978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****             (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
+ 12402              		.loc 1 4978 66 view .LVU4268
+ 12403 0090 16F0020F 		tst	r6, #2
+ 12404 0094 13D0     		beq	.L774
+4982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12405              		.loc 1 4982 5 is_stmt 1 view .LVU4269
+4982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12406              		.loc 1 4982 13 is_stmt 0 view .LVU4270
+ 12407 0096 638D     		ldrh	r3, [r4, #42]
+ 12408 0098 9BB2     		uxth	r3, r3
+4982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12409              		.loc 1 4982 8 view .LVU4271
+ 12410 009a 002B     		cmp	r3, #0
+ 12411 009c DAD0     		beq	.L772
+4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12412              		.loc 1 4985 7 is_stmt 1 view .LVU4272
+4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12413              		.loc 1 4985 35 is_stmt 0 view .LVU4273
+ARM GAS  /tmp/ccVyGVF6.s 			page 422
+
+
+ 12414 009e 626A     		ldr	r2, [r4, #36]
+ 12415              	.LVL884:
+4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12416              		.loc 1 4985 11 view .LVU4274
+ 12417 00a0 2368     		ldr	r3, [r4]
+4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12418              		.loc 1 4985 30 view .LVU4275
+ 12419 00a2 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12420              		.loc 1 4985 28 view .LVU4276
+ 12421 00a4 9A62     		str	r2, [r3, #40]
+4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12422              		.loc 1 4988 7 is_stmt 1 view .LVU4277
+4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12423              		.loc 1 4988 11 is_stmt 0 view .LVU4278
+ 12424 00a6 636A     		ldr	r3, [r4, #36]
+4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12425              		.loc 1 4988 21 view .LVU4279
+ 12426 00a8 0133     		adds	r3, r3, #1
+ 12427 00aa 6362     		str	r3, [r4, #36]
+4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 12428              		.loc 1 4990 7 is_stmt 1 view .LVU4280
+4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 12429              		.loc 1 4990 11 is_stmt 0 view .LVU4281
+ 12430 00ac 238D     		ldrh	r3, [r4, #40]
+4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 12431              		.loc 1 4990 21 view .LVU4282
+ 12432 00ae 013B     		subs	r3, r3, #1
+ 12433 00b0 2385     		strh	r3, [r4, #40]	@ movhi
+4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 12434              		.loc 1 4991 7 is_stmt 1 view .LVU4283
+4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 12435              		.loc 1 4991 11 is_stmt 0 view .LVU4284
+ 12436 00b2 638D     		ldrh	r3, [r4, #42]
+ 12437 00b4 9BB2     		uxth	r3, r3
+4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 12438              		.loc 1 4991 22 view .LVU4285
+ 12439 00b6 013B     		subs	r3, r3, #1
+ 12440 00b8 9BB2     		uxth	r3, r3
+ 12441 00ba 6385     		strh	r3, [r4, #42]	@ movhi
+ 12442 00bc CAE7     		b	.L772
+ 12443              	.LVL885:
+ 12444              	.L774:
+4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12445              		.loc 1 4994 8 is_stmt 1 view .LVU4286
+4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12446              		.loc 1 4994 11 is_stmt 0 view .LVU4287
+ 12447 00be 15F0800F 		tst	r5, #128
+ 12448 00c2 4AD0     		beq	.L775
+4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12449              		.loc 1 4994 64 discriminator 1 view .LVU4288
+ 12450 00c4 16F0400F 		tst	r6, #64
+ 12451 00c8 47D0     		beq	.L775
+4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12452              		.loc 1 4997 5 is_stmt 1 view .LVU4289
+4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12453              		.loc 1 4997 14 is_stmt 0 view .LVU4290
+ARM GAS  /tmp/ccVyGVF6.s 			page 423
+
+
+ 12454 00ca 638D     		ldrh	r3, [r4, #42]
+ 12455 00cc 9BB2     		uxth	r3, r3
+4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12456              		.loc 1 4997 8 view .LVU4291
+ 12457 00ce 002B     		cmp	r3, #0
+ 12458 00d0 35D0     		beq	.L776
+4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12459              		.loc 1 4997 41 discriminator 1 view .LVU4292
+ 12460 00d2 238D     		ldrh	r3, [r4, #40]
+4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12461              		.loc 1 4997 33 discriminator 1 view .LVU4293
+ 12462 00d4 002B     		cmp	r3, #0
+ 12463 00d6 32D1     		bne	.L776
+4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12464              		.loc 1 4999 7 is_stmt 1 view .LVU4294
+4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12465              		.loc 1 4999 35 is_stmt 0 view .LVU4295
+ 12466 00d8 2268     		ldr	r2, [r4]
+ 12467              	.LVL886:
+4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12468              		.loc 1 4999 45 view .LVU4296
+ 12469 00da 5168     		ldr	r1, [r2, #4]
+ 12470              	.LVL887:
+4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12471              		.loc 1 4999 18 view .LVU4297
+ 12472 00dc C1F30901 		ubfx	r1, r1, #0, #10
+ 12473              	.LVL888:
+5001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12474              		.loc 1 5001 7 is_stmt 1 view .LVU4298
+5001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12475              		.loc 1 5001 15 is_stmt 0 view .LVU4299
+ 12476 00e0 638D     		ldrh	r3, [r4, #42]
+ 12477 00e2 9BB2     		uxth	r3, r3
+5001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12478              		.loc 1 5001 10 view .LVU4300
+ 12479 00e4 FF2B     		cmp	r3, #255
+ 12480 00e6 12D9     		bls	.L777
+5004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12481              		.loc 1 5004 9 is_stmt 1 view .LVU4301
+5004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12482              		.loc 1 5004 13 is_stmt 0 view .LVU4302
+ 12483 00e8 9369     		ldr	r3, [r2, #24]
+5004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12484              		.loc 1 5004 12 view .LVU4303
+ 12485 00ea 13F4803F 		tst	r3, #65536
+ 12486 00ee 0BD0     		beq	.L778
+5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12487              		.loc 1 5006 11 is_stmt 1 view .LVU4304
+5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12488              		.loc 1 5006 26 is_stmt 0 view .LVU4305
+ 12489 00f0 0123     		movs	r3, #1
+ 12490 00f2 2385     		strh	r3, [r4, #40]	@ movhi
+ 12491              	.L779:
+5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12492              		.loc 1 5012 9 is_stmt 1 view .LVU4306
+ 12493 00f4 0023     		movs	r3, #0
+ 12494 00f6 0093     		str	r3, [sp]
+ARM GAS  /tmp/ccVyGVF6.s 			page 424
+
+
+ 12495 00f8 4FF08073 		mov	r3, #16777216
+ 12496 00fc 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 12497 0100 2046     		mov	r0, r4
+ 12498              	.LVL889:
+5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12499              		.loc 1 5012 9 is_stmt 0 view .LVU4307
+ 12500 0102 FFF7FEFF 		bl	I2C_TransferConfig
+ 12501              	.LVL890:
+5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12502              		.loc 1 5012 9 view .LVU4308
+ 12503 0106 A5E7     		b	.L772
+ 12504              	.LVL891:
+ 12505              	.L778:
+5010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12506              		.loc 1 5010 11 is_stmt 1 view .LVU4309
+5010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12507              		.loc 1 5010 26 is_stmt 0 view .LVU4310
+ 12508 0108 FF23     		movs	r3, #255
+ 12509 010a 2385     		strh	r3, [r4, #40]	@ movhi
+ 12510 010c F2E7     		b	.L779
+ 12511              	.L777:
+5016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 12512              		.loc 1 5016 9 is_stmt 1 view .LVU4311
+5016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 12513              		.loc 1 5016 30 is_stmt 0 view .LVU4312
+ 12514 010e 628D     		ldrh	r2, [r4, #42]
+ 12515 0110 92B2     		uxth	r2, r2
+5016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 12516              		.loc 1 5016 24 view .LVU4313
+ 12517 0112 2285     		strh	r2, [r4, #40]	@ movhi
+5017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12518              		.loc 1 5017 9 is_stmt 1 view .LVU4314
+5017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12519              		.loc 1 5017 17 is_stmt 0 view .LVU4315
+ 12520 0114 E36A     		ldr	r3, [r4, #44]
+5017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12521              		.loc 1 5017 12 view .LVU4316
+ 12522 0116 13F5803F 		cmn	r3, #65536
+ 12523 011a 07D0     		beq	.L780
+5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              hi2c->XferOptions, I2C_NO_STARTSTOP);
+ 12524              		.loc 1 5019 11 is_stmt 1 view .LVU4317
+ 12525 011c E36A     		ldr	r3, [r4, #44]
+ 12526 011e 0020     		movs	r0, #0
+ 12527              	.LVL892:
+5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              hi2c->XferOptions, I2C_NO_STARTSTOP);
+ 12528              		.loc 1 5019 11 is_stmt 0 view .LVU4318
+ 12529 0120 0090     		str	r0, [sp]
+ 12530 0122 D2B2     		uxtb	r2, r2
+ 12531 0124 2046     		mov	r0, r4
+ 12532 0126 FFF7FEFF 		bl	I2C_TransferConfig
+ 12533              	.LVL893:
+5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              hi2c->XferOptions, I2C_NO_STARTSTOP);
+ 12534              		.loc 1 5019 11 view .LVU4319
+ 12535 012a 93E7     		b	.L772
+ 12536              	.LVL894:
+ 12537              	.L780:
+5024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ARM GAS  /tmp/ccVyGVF6.s 			page 425
+
+
+ 12538              		.loc 1 5024 11 is_stmt 1 view .LVU4320
+ 12539 012c 0023     		movs	r3, #0
+ 12540 012e 0093     		str	r3, [sp]
+ 12541 0130 4FF00073 		mov	r3, #33554432
+ 12542 0134 D2B2     		uxtb	r2, r2
+ 12543 0136 2046     		mov	r0, r4
+ 12544              	.LVL895:
+5024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ 12545              		.loc 1 5024 11 is_stmt 0 view .LVU4321
+ 12546 0138 FFF7FEFF 		bl	I2C_TransferConfig
+ 12547              	.LVL896:
+5024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                              I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ 12548              		.loc 1 5024 11 view .LVU4322
+ 12549 013c 8AE7     		b	.L772
+ 12550              	.LVL897:
+ 12551              	.L776:
+5032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12552              		.loc 1 5032 7 is_stmt 1 view .LVU4323
+5032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12553              		.loc 1 5032 11 is_stmt 0 view .LVU4324
+ 12554 013e 2368     		ldr	r3, [r4]
+ 12555 0140 5B68     		ldr	r3, [r3, #4]
+5032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12556              		.loc 1 5032 10 view .LVU4325
+ 12557 0142 13F0007F 		tst	r3, #33554432
+ 12558 0146 03D1     		bne	.L781
+5035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12559              		.loc 1 5035 9 is_stmt 1 view .LVU4326
+ 12560 0148 2046     		mov	r0, r4
+ 12561              	.LVL898:
+5035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12562              		.loc 1 5035 9 is_stmt 0 view .LVU4327
+ 12563 014a FFF7FEFF 		bl	I2C_ITMasterSeqCplt
+ 12564              	.LVL899:
+5035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12565              		.loc 1 5035 9 view .LVU4328
+ 12566 014e 81E7     		b	.L772
+ 12567              	.LVL900:
+ 12568              	.L781:
+5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12569              		.loc 1 5041 9 is_stmt 1 view .LVU4329
+ 12570 0150 4021     		movs	r1, #64
+ 12571              	.LVL901:
+5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12572              		.loc 1 5041 9 is_stmt 0 view .LVU4330
+ 12573 0152 2046     		mov	r0, r4
+ 12574              	.LVL902:
+5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12575              		.loc 1 5041 9 view .LVU4331
+ 12576 0154 FFF7FEFF 		bl	I2C_ITError
+ 12577              	.LVL903:
+5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12578              		.loc 1 5041 9 view .LVU4332
+ 12579 0158 7CE7     		b	.L772
+ 12580              	.LVL904:
+ 12581              	.L775:
+5045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ARM GAS  /tmp/ccVyGVF6.s 			page 426
+
+
+ 12582              		.loc 1 5045 8 is_stmt 1 view .LVU4333
+5045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12583              		.loc 1 5045 11 is_stmt 0 view .LVU4334
+ 12584 015a 002B     		cmp	r3, #0
+ 12585 015c 3FF47AAF 		beq	.L772
+5045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12586              		.loc 1 5045 63 discriminator 1 view .LVU4335
+ 12587 0160 16F0400F 		tst	r6, #64
+ 12588 0164 3FF476AF 		beq	.L772
+5048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12589              		.loc 1 5048 5 is_stmt 1 view .LVU4336
+5048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12590              		.loc 1 5048 13 is_stmt 0 view .LVU4337
+ 12591 0168 638D     		ldrh	r3, [r4, #42]
+ 12592 016a 9BB2     		uxth	r3, r3
+5048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12593              		.loc 1 5048 8 view .LVU4338
+ 12594 016c 93B9     		cbnz	r3, .L782
+5050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12595              		.loc 1 5050 7 is_stmt 1 view .LVU4339
+5050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12596              		.loc 1 5050 11 is_stmt 0 view .LVU4340
+ 12597 016e 2368     		ldr	r3, [r4]
+ 12598 0170 5A68     		ldr	r2, [r3, #4]
+ 12599              	.LVL905:
+5050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12600              		.loc 1 5050 10 view .LVU4341
+ 12601 0172 12F0007F 		tst	r2, #33554432
+ 12602 0176 7FF46DAF 		bne	.L772
+5053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12603              		.loc 1 5053 9 is_stmt 1 view .LVU4342
+5053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12604              		.loc 1 5053 17 is_stmt 0 view .LVU4343
+ 12605 017a E26A     		ldr	r2, [r4, #44]
+5053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12606              		.loc 1 5053 12 view .LVU4344
+ 12607 017c 12F5803F 		cmn	r2, #65536
+ 12608 0180 04D1     		bne	.L783
+5056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12609              		.loc 1 5056 11 is_stmt 1 view .LVU4345
+5056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12610              		.loc 1 5056 31 is_stmt 0 view .LVU4346
+ 12611 0182 5A68     		ldr	r2, [r3, #4]
+ 12612 0184 42F48042 		orr	r2, r2, #16384
+ 12613 0188 5A60     		str	r2, [r3, #4]
+ 12614 018a 63E7     		b	.L772
+ 12615              	.L783:
+5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12616              		.loc 1 5061 11 is_stmt 1 view .LVU4347
+ 12617 018c 2046     		mov	r0, r4
+ 12618              	.LVL906:
+5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12619              		.loc 1 5061 11 is_stmt 0 view .LVU4348
+ 12620 018e FFF7FEFF 		bl	I2C_ITMasterSeqCplt
+ 12621              	.LVL907:
+5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12622              		.loc 1 5061 11 view .LVU4349
+ARM GAS  /tmp/ccVyGVF6.s 			page 427
+
+
+ 12623 0192 5FE7     		b	.L772
+ 12624              	.LVL908:
+ 12625              	.L782:
+5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 12626              		.loc 1 5069 7 is_stmt 1 view .LVU4350
+ 12627 0194 4021     		movs	r1, #64
+ 12628              	.LVL909:
+5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 12629              		.loc 1 5069 7 is_stmt 0 view .LVU4351
+ 12630 0196 2046     		mov	r0, r4
+ 12631              	.LVL910:
+5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 12632              		.loc 1 5069 7 view .LVU4352
+ 12633 0198 FFF7FEFF 		bl	I2C_ITError
+ 12634              	.LVL911:
+5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 12635              		.loc 1 5069 7 view .LVU4353
+ 12636 019c 5AE7     		b	.L772
+ 12637              	.LVL912:
+ 12638              	.L791:
+5081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12639              		.loc 1 5081 5 is_stmt 1 view .LVU4354
+ 12640 019e 2946     		mov	r1, r5
+ 12641 01a0 2046     		mov	r0, r4
+ 12642 01a2 FFF7FEFF 		bl	I2C_ITMasterCplt
+ 12643              	.LVL913:
+ 12644 01a6 5CE7     		b	.L784
+ 12645              	.LVL914:
+ 12646              	.L785:
+ 12647              	.LCFI133:
+ 12648              		.cfi_def_cfa_offset 0
+ 12649              		.cfi_restore 4
+ 12650              		.cfi_restore 5
+ 12651              		.cfi_restore 6
+ 12652              		.cfi_restore 14
+4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12653              		.loc 1 4946 3 is_stmt 0 view .LVU4355
+ 12654 01a8 0220     		movs	r0, #2
+ 12655              	.LVL915:
+5088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12656              		.loc 1 5088 1 view .LVU4356
+ 12657 01aa 7047     		bx	lr
+ 12658              		.cfi_endproc
+ 12659              	.LFE190:
+ 12661              		.section	.text.I2C_Mem_ISR_DMA,"ax",%progbits
+ 12662              		.align	1
+ 12663              		.syntax unified
+ 12664              		.thumb
+ 12665              		.thumb_func
+ 12666              		.fpu fpv5-d16
+ 12668              	I2C_Mem_ISR_DMA:
+ 12669              	.LVL916:
+ 12670              	.LFB194:
+5547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t direction = I2C_GENERATE_START_WRITE;
+ 12671              		.loc 1 5547 1 is_stmt 1 view -0
+ 12672              		.cfi_startproc
+ 12673              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccVyGVF6.s 			page 428
+
+
+ 12674              		@ frame_needed = 0, uses_anonymous_args = 0
+5548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12675              		.loc 1 5548 3 view .LVU4358
+5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12676              		.loc 1 5551 3 view .LVU4359
+5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12677              		.loc 1 5551 3 view .LVU4360
+ 12678 0000 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 12679 0004 012B     		cmp	r3, #1
+ 12680 0006 00F0DC80 		beq	.L811
+5547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t direction = I2C_GENERATE_START_WRITE;
+ 12681              		.loc 1 5547 1 is_stmt 0 discriminator 2 view .LVU4361
+ 12682 000a 10B5     		push	{r4, lr}
+ 12683              	.LCFI134:
+ 12684              		.cfi_def_cfa_offset 8
+ 12685              		.cfi_offset 4, -8
+ 12686              		.cfi_offset 14, -4
+ 12687 000c 82B0     		sub	sp, sp, #8
+ 12688              	.LCFI135:
+ 12689              		.cfi_def_cfa_offset 16
+ 12690 000e 0446     		mov	r4, r0
+5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12691              		.loc 1 5551 3 is_stmt 1 discriminator 2 view .LVU4362
+ 12692 0010 0123     		movs	r3, #1
+ 12693 0012 80F84030 		strb	r3, [r0, #64]
+5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12694              		.loc 1 5551 3 discriminator 2 view .LVU4363
+5553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12695              		.loc 1 5553 3 discriminator 2 view .LVU4364
+5553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12696              		.loc 1 5553 6 is_stmt 0 discriminator 2 view .LVU4365
+ 12697 0016 11F0100F 		tst	r1, #16
+ 12698 001a 02D0     		beq	.L794
+5553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 12699              		.loc 1 5553 55 discriminator 1 view .LVU4366
+ 12700 001c 12F0100F 		tst	r2, #16
+ 12701 0020 10D1     		bne	.L817
+ 12702              	.L794:
+5570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 12703              		.loc 1 5570 8 is_stmt 1 view .LVU4367
+5570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 12704              		.loc 1 5570 11 is_stmt 0 view .LVU4368
+ 12705 0022 11F0020F 		tst	r1, #2
+ 12706 0026 1BD0     		beq	.L796
+5570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 12707              		.loc 1 5570 62 discriminator 1 view .LVU4369
+ 12708 0028 12F0020F 		tst	r2, #2
+ 12709 002c 18D0     		beq	.L796
+5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12710              		.loc 1 5574 5 is_stmt 1 view .LVU4370
+5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12711              		.loc 1 5574 9 is_stmt 0 view .LVU4371
+ 12712 002e 2368     		ldr	r3, [r4]
+5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12713              		.loc 1 5574 32 view .LVU4372
+ 12714 0030 226D     		ldr	r2, [r4, #80]
+ 12715              	.LVL917:
+ARM GAS  /tmp/ccVyGVF6.s 			page 429
+
+
+5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12716              		.loc 1 5574 26 view .LVU4373
+ 12717 0032 9A62     		str	r2, [r3, #40]
+5577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12718              		.loc 1 5577 5 is_stmt 1 view .LVU4374
+5577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12719              		.loc 1 5577 22 is_stmt 0 view .LVU4375
+ 12720 0034 4FF0FF33 		mov	r3, #-1
+ 12721 0038 2365     		str	r3, [r4, #80]
+ 12722              	.LVL918:
+ 12723              	.L795:
+5693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12724              		.loc 1 5693 3 is_stmt 1 view .LVU4376
+5696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12725              		.loc 1 5696 3 view .LVU4377
+5696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12726              		.loc 1 5696 3 view .LVU4378
+ 12727 003a 0020     		movs	r0, #0
+ 12728 003c 84F84000 		strb	r0, [r4, #64]
+5696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12729              		.loc 1 5696 3 view .LVU4379
+5698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 12730              		.loc 1 5698 3 view .LVU4380
+5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12731              		.loc 1 5699 1 is_stmt 0 view .LVU4381
+ 12732 0040 02B0     		add	sp, sp, #8
+ 12733              	.LCFI136:
+ 12734              		.cfi_remember_state
+ 12735              		.cfi_def_cfa_offset 8
+ 12736              		@ sp needed
+ 12737 0042 10BD     		pop	{r4, pc}
+ 12738              	.LVL919:
+ 12739              	.L817:
+ 12740              	.LCFI137:
+ 12741              		.cfi_restore_state
+5557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12742              		.loc 1 5557 5 is_stmt 1 view .LVU4382
+ 12743 0044 0368     		ldr	r3, [r0]
+ 12744 0046 1022     		movs	r2, #16
+ 12745              	.LVL920:
+5557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12746              		.loc 1 5557 5 is_stmt 0 view .LVU4383
+ 12747 0048 DA61     		str	r2, [r3, #28]
+5560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12748              		.loc 1 5560 5 is_stmt 1 view .LVU4384
+5560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12749              		.loc 1 5560 21 is_stmt 0 view .LVU4385
+ 12750 004a 436C     		ldr	r3, [r0, #68]
+ 12751 004c 43F00403 		orr	r3, r3, #4
+ 12752 0050 4364     		str	r3, [r0, #68]
+5565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12753              		.loc 1 5565 5 is_stmt 1 view .LVU4386
+ 12754 0052 2021     		movs	r1, #32
+ 12755              	.LVL921:
+5565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12756              		.loc 1 5565 5 is_stmt 0 view .LVU4387
+ 12757 0054 FFF7FEFF 		bl	I2C_Enable_IRQ
+ARM GAS  /tmp/ccVyGVF6.s 			page 430
+
+
+ 12758              	.LVL922:
+5568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12759              		.loc 1 5568 5 is_stmt 1 view .LVU4388
+ 12760 0058 2046     		mov	r0, r4
+ 12761 005a FFF7FEFF 		bl	I2C_Flush_TXDR
+ 12762              	.LVL923:
+ 12763 005e ECE7     		b	.L795
+ 12764              	.LVL924:
+ 12765              	.L796:
+5579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12766              		.loc 1 5579 8 view .LVU4389
+5579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12767              		.loc 1 5579 11 is_stmt 0 view .LVU4390
+ 12768 0060 11F0800F 		tst	r1, #128
+ 12769 0064 02D0     		beq	.L797
+5579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12770              		.loc 1 5579 61 discriminator 1 view .LVU4391
+ 12771 0066 12F0400F 		tst	r2, #64
+ 12772 006a 0FD1     		bne	.L818
+ 12773              	.L797:
+5632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12774              		.loc 1 5632 8 is_stmt 1 view .LVU4392
+5632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12775              		.loc 1 5632 11 is_stmt 0 view .LVU4393
+ 12776 006c 11F0400F 		tst	r1, #64
+ 12777 0070 02D0     		beq	.L804
+5632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 12778              		.loc 1 5632 60 discriminator 1 view .LVU4394
+ 12779 0072 12F0400F 		tst	r2, #64
+ 12780 0076 58D1     		bne	.L819
+ 12781              	.L804:
+5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 12782              		.loc 1 5684 8 is_stmt 1 view .LVU4395
+5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 12783              		.loc 1 5684 11 is_stmt 0 view .LVU4396
+ 12784 0078 11F0200F 		tst	r1, #32
+ 12785 007c DDD0     		beq	.L795
+5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 12786              		.loc 1 5684 63 discriminator 1 view .LVU4397
+ 12787 007e 12F0200F 		tst	r2, #32
+ 12788 0082 DAD0     		beq	.L795
+5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12789              		.loc 1 5688 5 is_stmt 1 view .LVU4398
+ 12790 0084 2046     		mov	r0, r4
+ 12791              	.LVL925:
+5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12792              		.loc 1 5688 5 is_stmt 0 view .LVU4399
+ 12793 0086 FFF7FEFF 		bl	I2C_ITMasterCplt
+ 12794              	.LVL926:
+5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 12795              		.loc 1 5688 5 view .LVU4400
+ 12796 008a D6E7     		b	.L795
+ 12797              	.LVL927:
+ 12798              	.L818:
+5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12799              		.loc 1 5583 5 is_stmt 1 view .LVU4401
+ 12800 008c 0121     		movs	r1, #1
+ARM GAS  /tmp/ccVyGVF6.s 			page 431
+
+
+ 12801              	.LVL928:
+5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12802              		.loc 1 5583 5 is_stmt 0 view .LVU4402
+ 12803 008e 2046     		mov	r0, r4
+ 12804              	.LVL929:
+5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12805              		.loc 1 5583 5 view .LVU4403
+ 12806 0090 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 12807              	.LVL930:
+5586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12808              		.loc 1 5586 5 is_stmt 1 view .LVU4404
+ 12809 0094 1021     		movs	r1, #16
+ 12810 0096 2046     		mov	r0, r4
+ 12811 0098 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 12812              	.LVL931:
+5588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12813              		.loc 1 5588 5 view .LVU4405
+5588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12814              		.loc 1 5588 13 is_stmt 0 view .LVU4406
+ 12815 009c 638D     		ldrh	r3, [r4, #42]
+ 12816 009e 9BB2     		uxth	r3, r3
+5588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12817              		.loc 1 5588 8 view .LVU4407
+ 12818 00a0 002B     		cmp	r3, #0
+ 12819 00a2 3DD0     		beq	.L798
+5591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12820              		.loc 1 5591 7 is_stmt 1 view .LVU4408
+5591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12821              		.loc 1 5591 15 is_stmt 0 view .LVU4409
+ 12822 00a4 638D     		ldrh	r3, [r4, #42]
+ 12823 00a6 9BB2     		uxth	r3, r3
+5591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12824              		.loc 1 5591 10 view .LVU4410
+ 12825 00a8 FF2B     		cmp	r3, #255
+ 12826 00aa 25D9     		bls	.L799
+5594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12827              		.loc 1 5594 9 is_stmt 1 view .LVU4411
+5594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12828              		.loc 1 5594 13 is_stmt 0 view .LVU4412
+ 12829 00ac 2368     		ldr	r3, [r4]
+ 12830 00ae 9B69     		ldr	r3, [r3, #24]
+5594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 12831              		.loc 1 5594 12 view .LVU4413
+ 12832 00b0 13F4803F 		tst	r3, #65536
+ 12833 00b4 1DD0     		beq	.L800
+5596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12834              		.loc 1 5596 11 is_stmt 1 view .LVU4414
+5596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12835              		.loc 1 5596 26 is_stmt 0 view .LVU4415
+ 12836 00b6 0123     		movs	r3, #1
+ 12837 00b8 2385     		strh	r3, [r4, #40]	@ movhi
+ 12838              	.L801:
+5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ 12839              		.loc 1 5602 9 is_stmt 1 view .LVU4416
+5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ 12840              		.loc 1 5602 48 is_stmt 0 view .LVU4417
+ 12841 00ba E16C     		ldr	r1, [r4, #76]
+ARM GAS  /tmp/ccVyGVF6.s 			page 432
+
+
+5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ 12842              		.loc 1 5602 9 view .LVU4418
+ 12843 00bc 0023     		movs	r3, #0
+ 12844 00be 0093     		str	r3, [sp]
+ 12845 00c0 4FF08073 		mov	r3, #16777216
+ 12846 00c4 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 12847 00c8 89B2     		uxth	r1, r1
+ 12848 00ca 2046     		mov	r0, r4
+ 12849 00cc FFF7FEFF 		bl	I2C_TransferConfig
+ 12850              	.LVL932:
+ 12851              	.L802:
+5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12852              		.loc 1 5613 7 is_stmt 1 view .LVU4419
+5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12853              		.loc 1 5613 23 is_stmt 0 view .LVU4420
+ 12854 00d0 638D     		ldrh	r3, [r4, #42]
+ 12855 00d2 9BB2     		uxth	r3, r3
+5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12856              		.loc 1 5613 30 view .LVU4421
+ 12857 00d4 228D     		ldrh	r2, [r4, #40]
+5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12858              		.loc 1 5613 23 view .LVU4422
+ 12859 00d6 9B1A     		subs	r3, r3, r2
+ 12860 00d8 9BB2     		uxth	r3, r3
+ 12861 00da 6385     		strh	r3, [r4, #42]	@ movhi
+5616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12862              		.loc 1 5616 7 is_stmt 1 view .LVU4423
+5616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12863              		.loc 1 5616 15 is_stmt 0 view .LVU4424
+ 12864 00dc 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 12865 00e0 DBB2     		uxtb	r3, r3
+5616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12866              		.loc 1 5616 10 view .LVU4425
+ 12867 00e2 222B     		cmp	r3, #34
+ 12868 00e4 16D0     		beq	.L820
+5622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12869              		.loc 1 5622 9 is_stmt 1 view .LVU4426
+5622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12870              		.loc 1 5622 13 is_stmt 0 view .LVU4427
+ 12871 00e6 2268     		ldr	r2, [r4]
+5622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12872              		.loc 1 5622 29 view .LVU4428
+ 12873 00e8 1368     		ldr	r3, [r2]
+ 12874 00ea 43F48043 		orr	r3, r3, #16384
+ 12875 00ee 1360     		str	r3, [r2]
+ 12876 00f0 A3E7     		b	.L795
+ 12877              	.L800:
+5600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12878              		.loc 1 5600 11 is_stmt 1 view .LVU4429
+5600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 12879              		.loc 1 5600 26 is_stmt 0 view .LVU4430
+ 12880 00f2 FF23     		movs	r3, #255
+ 12881 00f4 2385     		strh	r3, [r4, #40]	@ movhi
+ 12882 00f6 E0E7     		b	.L801
+ 12883              	.L799:
+5607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ 12884              		.loc 1 5607 9 is_stmt 1 view .LVU4431
+ARM GAS  /tmp/ccVyGVF6.s 			page 433
+
+
+5607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ 12885              		.loc 1 5607 30 is_stmt 0 view .LVU4432
+ 12886 00f8 628D     		ldrh	r2, [r4, #42]
+ 12887 00fa 92B2     		uxth	r2, r2
+5607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ 12888              		.loc 1 5607 24 view .LVU4433
+ 12889 00fc 2285     		strh	r2, [r4, #40]	@ movhi
+5608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ 12890              		.loc 1 5608 9 is_stmt 1 view .LVU4434
+5608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ 12891              		.loc 1 5608 48 is_stmt 0 view .LVU4435
+ 12892 00fe E16C     		ldr	r1, [r4, #76]
+5608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ 12893              		.loc 1 5608 9 view .LVU4436
+ 12894 0100 0023     		movs	r3, #0
+ 12895 0102 0093     		str	r3, [sp]
+ 12896 0104 4FF00073 		mov	r3, #33554432
+ 12897 0108 D2B2     		uxtb	r2, r2
+ 12898 010a 89B2     		uxth	r1, r1
+ 12899 010c 2046     		mov	r0, r4
+ 12900 010e FFF7FEFF 		bl	I2C_TransferConfig
+ 12901              	.LVL933:
+ 12902 0112 DDE7     		b	.L802
+ 12903              	.L820:
+5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12904              		.loc 1 5618 9 is_stmt 1 view .LVU4437
+5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12905              		.loc 1 5618 13 is_stmt 0 view .LVU4438
+ 12906 0114 2268     		ldr	r2, [r4]
+5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12907              		.loc 1 5618 29 view .LVU4439
+ 12908 0116 1368     		ldr	r3, [r2]
+ 12909 0118 43F40043 		orr	r3, r3, #32768
+ 12910 011c 1360     		str	r3, [r2]
+ 12911 011e 8CE7     		b	.L795
+ 12912              	.L798:
+5629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 12913              		.loc 1 5629 7 is_stmt 1 view .LVU4440
+ 12914 0120 4021     		movs	r1, #64
+ 12915 0122 2046     		mov	r0, r4
+ 12916 0124 FFF7FEFF 		bl	I2C_ITError
+ 12917              	.LVL934:
+ 12918 0128 87E7     		b	.L795
+ 12919              	.LVL935:
+ 12920              	.L819:
+5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12921              		.loc 1 5636 5 view .LVU4441
+ 12922 012a 0121     		movs	r1, #1
+ 12923              	.LVL936:
+5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12924              		.loc 1 5636 5 is_stmt 0 view .LVU4442
+ 12925 012c 2046     		mov	r0, r4
+ 12926              	.LVL937:
+5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12927              		.loc 1 5636 5 view .LVU4443
+ 12928 012e FFF7FEFF 		bl	I2C_Disable_IRQ
+ 12929              	.LVL938:
+ARM GAS  /tmp/ccVyGVF6.s 			page 434
+
+
+5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12930              		.loc 1 5639 5 is_stmt 1 view .LVU4444
+ 12931 0132 1021     		movs	r1, #16
+ 12932 0134 2046     		mov	r0, r4
+ 12933 0136 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 12934              	.LVL939:
+5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12935              		.loc 1 5641 5 view .LVU4445
+5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12936              		.loc 1 5641 13 is_stmt 0 view .LVU4446
+ 12937 013a 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 12938 013e DBB2     		uxtb	r3, r3
+5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12939              		.loc 1 5641 8 view .LVU4447
+ 12940 0140 222B     		cmp	r3, #34
+ 12941 0142 26D0     		beq	.L812
+5548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12942              		.loc 1 5548 12 view .LVU4448
+ 12943 0144 2048     		ldr	r0, .L822
+ 12944              	.L805:
+ 12945              	.LVL940:
+5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12946              		.loc 1 5646 5 is_stmt 1 view .LVU4449
+5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12947              		.loc 1 5646 13 is_stmt 0 view .LVU4450
+ 12948 0146 638D     		ldrh	r3, [r4, #42]
+ 12949 0148 9BB2     		uxth	r3, r3
+5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12950              		.loc 1 5646 8 view .LVU4451
+ 12951 014a FF2B     		cmp	r3, #255
+ 12952 014c 26D9     		bls	.L806
+5649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12953              		.loc 1 5649 7 is_stmt 1 view .LVU4452
+5649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12954              		.loc 1 5649 11 is_stmt 0 view .LVU4453
+ 12955 014e 2368     		ldr	r3, [r4]
+ 12956 0150 9B69     		ldr	r3, [r3, #24]
+5649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 12957              		.loc 1 5649 10 view .LVU4454
+ 12958 0152 13F4803F 		tst	r3, #65536
+ 12959 0156 1ED0     		beq	.L807
+5651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12960              		.loc 1 5651 9 is_stmt 1 view .LVU4455
+5651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 12961              		.loc 1 5651 24 is_stmt 0 view .LVU4456
+ 12962 0158 0123     		movs	r3, #1
+ 12963 015a 2385     		strh	r3, [r4, #40]	@ movhi
+ 12964              	.L808:
+5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_RELOAD_MODE, direction);
+ 12965              		.loc 1 5659 7 is_stmt 1 view .LVU4457
+5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_RELOAD_MODE, direction);
+ 12966              		.loc 1 5659 46 is_stmt 0 view .LVU4458
+ 12967 015c E16C     		ldr	r1, [r4, #76]
+5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_RELOAD_MODE, direction);
+ 12968              		.loc 1 5659 7 view .LVU4459
+ 12969 015e 0090     		str	r0, [sp]
+ 12970 0160 4FF08073 		mov	r3, #16777216
+ARM GAS  /tmp/ccVyGVF6.s 			page 435
+
+
+ 12971 0164 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 12972 0168 89B2     		uxth	r1, r1
+ 12973 016a 2046     		mov	r0, r4
+ 12974              	.LVL941:
+5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_RELOAD_MODE, direction);
+ 12975              		.loc 1 5659 7 view .LVU4460
+ 12976 016c FFF7FEFF 		bl	I2C_TransferConfig
+ 12977              	.LVL942:
+ 12978              	.L809:
+5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12979              		.loc 1 5672 5 is_stmt 1 view .LVU4461
+5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12980              		.loc 1 5672 21 is_stmt 0 view .LVU4462
+ 12981 0170 638D     		ldrh	r3, [r4, #42]
+ 12982 0172 9BB2     		uxth	r3, r3
+5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12983              		.loc 1 5672 28 view .LVU4463
+ 12984 0174 228D     		ldrh	r2, [r4, #40]
+5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 12985              		.loc 1 5672 21 view .LVU4464
+ 12986 0176 9B1A     		subs	r3, r3, r2
+ 12987 0178 9BB2     		uxth	r3, r3
+ 12988 017a 6385     		strh	r3, [r4, #42]	@ movhi
+5675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12989              		.loc 1 5675 5 is_stmt 1 view .LVU4465
+5675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12990              		.loc 1 5675 13 is_stmt 0 view .LVU4466
+ 12991 017c 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 12992 0180 DBB2     		uxtb	r3, r3
+5675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 12993              		.loc 1 5675 8 view .LVU4467
+ 12994 0182 222B     		cmp	r3, #34
+ 12995 0184 17D0     		beq	.L821
+5681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 12996              		.loc 1 5681 7 is_stmt 1 view .LVU4468
+5681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 12997              		.loc 1 5681 11 is_stmt 0 view .LVU4469
+ 12998 0186 2268     		ldr	r2, [r4]
+5681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 12999              		.loc 1 5681 27 view .LVU4470
+ 13000 0188 1368     		ldr	r3, [r2]
+ 13001 018a 43F48043 		orr	r3, r3, #16384
+ 13002 018e 1360     		str	r3, [r2]
+ 13003 0190 53E7     		b	.L795
+ 13004              	.LVL943:
+ 13005              	.L812:
+5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13006              		.loc 1 5643 17 view .LVU4471
+ 13007 0192 0E48     		ldr	r0, .L822+4
+ 13008 0194 D7E7     		b	.L805
+ 13009              	.LVL944:
+ 13010              	.L807:
+5655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13011              		.loc 1 5655 9 is_stmt 1 view .LVU4472
+5655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13012              		.loc 1 5655 24 is_stmt 0 view .LVU4473
+ 13013 0196 FF23     		movs	r3, #255
+ARM GAS  /tmp/ccVyGVF6.s 			page 436
+
+
+ 13014 0198 2385     		strh	r3, [r4, #40]	@ movhi
+ 13015 019a DFE7     		b	.L808
+ 13016              	.L806:
+5664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13017              		.loc 1 5664 7 is_stmt 1 view .LVU4474
+5664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13018              		.loc 1 5664 28 is_stmt 0 view .LVU4475
+ 13019 019c 628D     		ldrh	r2, [r4, #42]
+ 13020 019e 92B2     		uxth	r2, r2
+5664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13021              		.loc 1 5664 22 view .LVU4476
+ 13022 01a0 2285     		strh	r2, [r4, #40]	@ movhi
+5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+ 13023              		.loc 1 5667 7 is_stmt 1 view .LVU4477
+5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+ 13024              		.loc 1 5667 46 is_stmt 0 view .LVU4478
+ 13025 01a2 E16C     		ldr	r1, [r4, #76]
+5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+ 13026              		.loc 1 5667 7 view .LVU4479
+ 13027 01a4 0090     		str	r0, [sp]
+ 13028 01a6 4FF00073 		mov	r3, #33554432
+ 13029 01aa D2B2     		uxtb	r2, r2
+ 13030 01ac 89B2     		uxth	r1, r1
+ 13031 01ae 2046     		mov	r0, r4
+ 13032              	.LVL945:
+5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+ 13033              		.loc 1 5667 7 view .LVU4480
+ 13034 01b0 FFF7FEFF 		bl	I2C_TransferConfig
+ 13035              	.LVL946:
+5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+ 13036              		.loc 1 5667 7 view .LVU4481
+ 13037 01b4 DCE7     		b	.L809
+ 13038              	.L821:
+5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13039              		.loc 1 5677 7 is_stmt 1 view .LVU4482
+5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13040              		.loc 1 5677 11 is_stmt 0 view .LVU4483
+ 13041 01b6 2268     		ldr	r2, [r4]
+5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13042              		.loc 1 5677 27 view .LVU4484
+ 13043 01b8 1368     		ldr	r3, [r2]
+ 13044 01ba 43F40043 		orr	r3, r3, #32768
+ 13045 01be 1360     		str	r3, [r2]
+ 13046 01c0 3BE7     		b	.L795
+ 13047              	.LVL947:
+ 13048              	.L811:
+ 13049              	.LCFI138:
+ 13050              		.cfi_def_cfa_offset 0
+ 13051              		.cfi_restore 4
+ 13052              		.cfi_restore 14
+5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13053              		.loc 1 5551 3 view .LVU4485
+ 13054 01c2 0220     		movs	r0, #2
+ 13055              	.LVL948:
+5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13056              		.loc 1 5699 1 view .LVU4486
+ 13057 01c4 7047     		bx	lr
+ARM GAS  /tmp/ccVyGVF6.s 			page 437
+
+
+ 13058              	.L823:
+ 13059 01c6 00BF     		.align	2
+ 13060              	.L822:
+ 13061 01c8 00200080 		.word	-2147475456
+ 13062 01cc 00240080 		.word	-2147474432
+ 13063              		.cfi_endproc
+ 13064              	.LFE194:
+ 13066              		.section	.text.I2C_Slave_ISR_DMA,"ax",%progbits
+ 13067              		.align	1
+ 13068              		.syntax unified
+ 13069              		.thumb
+ 13070              		.thumb_func
+ 13071              		.fpu fpv5-d16
+ 13073              	I2C_Slave_ISR_DMA:
+ 13074              	.LVL949:
+ 13075              	.LFB195:
+5711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 13076              		.loc 1 5711 1 is_stmt 1 view -0
+ 13077              		.cfi_startproc
+ 13078              		@ args = 0, pretend = 0, frame = 0
+ 13079              		@ frame_needed = 0, uses_anonymous_args = 0
+5711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpoptions = hi2c->XferOptions;
+ 13080              		.loc 1 5711 1 is_stmt 0 view .LVU4488
+ 13081 0000 38B5     		push	{r3, r4, r5, lr}
+ 13082              	.LCFI139:
+ 13083              		.cfi_def_cfa_offset 16
+ 13084              		.cfi_offset 3, -16
+ 13085              		.cfi_offset 4, -12
+ 13086              		.cfi_offset 5, -8
+ 13087              		.cfi_offset 14, -4
+ 13088 0002 0446     		mov	r4, r0
+5712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t treatdmanack = 0U;
+ 13089              		.loc 1 5712 3 is_stmt 1 view .LVU4489
+5712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t treatdmanack = 0U;
+ 13090              		.loc 1 5712 12 is_stmt 0 view .LVU4490
+ 13091 0004 C06A     		ldr	r0, [r0, #44]
+ 13092              	.LVL950:
+5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate;
+ 13093              		.loc 1 5713 3 is_stmt 1 view .LVU4491
+5714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13094              		.loc 1 5714 3 view .LVU4492
+5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13095              		.loc 1 5717 3 view .LVU4493
+5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13096              		.loc 1 5717 3 view .LVU4494
+ 13097 0006 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 13098 000a 012B     		cmp	r3, #1
+ 13099 000c 00F08680 		beq	.L839
+5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13100              		.loc 1 5717 3 discriminator 2 view .LVU4495
+ 13101 0010 0123     		movs	r3, #1
+ 13102 0012 84F84030 		strb	r3, [r4, #64]
+5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13103              		.loc 1 5717 3 discriminator 2 view .LVU4496
+5720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 13104              		.loc 1 5720 3 discriminator 2 view .LVU4497
+5720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ARM GAS  /tmp/ccVyGVF6.s 			page 438
+
+
+ 13105              		.loc 1 5720 6 is_stmt 0 discriminator 2 view .LVU4498
+ 13106 0016 11F0200F 		tst	r1, #32
+ 13107 001a 02D0     		beq	.L826
+5720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 13108              		.loc 1 5720 58 discriminator 1 view .LVU4499
+ 13109 001c 12F0200F 		tst	r2, #32
+ 13110 0020 17D1     		bne	.L844
+ 13111              	.L826:
+5726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 13112              		.loc 1 5726 8 is_stmt 1 view .LVU4500
+5726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 13113              		.loc 1 5726 11 is_stmt 0 view .LVU4501
+ 13114 0022 11F0100F 		tst	r1, #16
+ 13115 0026 6BD0     		beq	.L828
+5726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 13116              		.loc 1 5726 60 discriminator 1 view .LVU4502
+ 13117 0028 12F0100F 		tst	r2, #16
+ 13118 002c 68D0     		beq	.L828
+5733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+ 13119              		.loc 1 5733 5 is_stmt 1 view .LVU4503
+5733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+ 13120              		.loc 1 5733 10 is_stmt 0 view .LVU4504
+ 13121 002e C2F38035 		ubfx	r5, r2, #14, #1
+5733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+ 13122              		.loc 1 5733 8 view .LVU4505
+ 13123 0032 12F4804F 		tst	r2, #16384
+ 13124 0036 02D1     		bne	.L829
+5733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+ 13125              		.loc 1 5733 68 discriminator 1 view .LVU4506
+ 13126 0038 12F4004F 		tst	r2, #32768
+ 13127 003c 5CD0     		beq	.L830
+ 13128              	.L829:
+5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13129              		.loc 1 5737 7 is_stmt 1 view .LVU4507
+5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13130              		.loc 1 5737 15 is_stmt 0 view .LVU4508
+ 13131 003e E36B     		ldr	r3, [r4, #60]
+5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13132              		.loc 1 5737 10 view .LVU4509
+ 13133 0040 5BB1     		cbz	r3, .L840
+5739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13134              		.loc 1 5739 9 is_stmt 1 view .LVU4510
+5739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13135              		.loc 1 5739 12 is_stmt 0 view .LVU4511
+ 13136 0042 12F4004F 		tst	r2, #32768
+ 13137 0046 0AD0     		beq	.L841
+5741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 13138              		.loc 1 5741 11 is_stmt 1 view .LVU4512
+5741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 13139              		.loc 1 5741 15 is_stmt 0 view .LVU4513
+ 13140 0048 1B68     		ldr	r3, [r3]
+ 13141 004a 5B68     		ldr	r3, [r3, #4]
+5741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 13142              		.loc 1 5741 14 view .LVU4514
+ 13143 004c 4BB3     		cbz	r3, .L842
+5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate;
+ 13144              		.loc 1 5713 12 view .LVU4515
+ARM GAS  /tmp/ccVyGVF6.s 			page 439
+
+
+ 13145 004e 0022     		movs	r2, #0
+ 13146              	.LVL951:
+5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate;
+ 13147              		.loc 1 5713 12 view .LVU4516
+ 13148 0050 06E0     		b	.L831
+ 13149              	.LVL952:
+ 13150              	.L844:
+5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13151              		.loc 1 5724 5 is_stmt 1 view .LVU4517
+ 13152 0052 2046     		mov	r0, r4
+ 13153              	.LVL953:
+5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13154              		.loc 1 5724 5 is_stmt 0 view .LVU4518
+ 13155 0054 FFF7FEFF 		bl	I2C_ITSlaveCplt
+ 13156              	.LVL954:
+5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13157              		.loc 1 5724 5 view .LVU4519
+ 13158 0058 58E0     		b	.L827
+ 13159              	.LVL955:
+ 13160              	.L840:
+5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate;
+ 13161              		.loc 1 5713 12 view .LVU4520
+ 13162 005a 0022     		movs	r2, #0
+ 13163              	.LVL956:
+5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate;
+ 13164              		.loc 1 5713 12 view .LVU4521
+ 13165 005c 00E0     		b	.L831
+ 13166              	.LVL957:
+ 13167              	.L841:
+5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   HAL_I2C_StateTypeDef tmpstate;
+ 13168              		.loc 1 5713 12 view .LVU4522
+ 13169 005e 0022     		movs	r2, #0
+ 13170              	.LVL958:
+ 13171              	.L831:
+5749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13172              		.loc 1 5749 7 is_stmt 1 view .LVU4523
+5749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13173              		.loc 1 5749 15 is_stmt 0 view .LVU4524
+ 13174 0060 A36B     		ldr	r3, [r4, #56]
+5749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13175              		.loc 1 5749 10 view .LVU4525
+ 13176 0062 1BB1     		cbz	r3, .L832
+5751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13177              		.loc 1 5751 9 is_stmt 1 view .LVU4526
+5751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13178              		.loc 1 5751 12 is_stmt 0 view .LVU4527
+ 13179 0064 15B1     		cbz	r5, .L832
+5753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 13180              		.loc 1 5753 11 is_stmt 1 view .LVU4528
+5753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 13181              		.loc 1 5753 15 is_stmt 0 view .LVU4529
+ 13182 0066 1B68     		ldr	r3, [r3]
+ 13183 0068 5B68     		ldr	r3, [r3, #4]
+5753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 13184              		.loc 1 5753 14 view .LVU4530
+ 13185 006a E3B1     		cbz	r3, .L833
+ 13186              	.L832:
+ARM GAS  /tmp/ccVyGVF6.s 			page 440
+
+
+5760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13187              		.loc 1 5760 7 is_stmt 1 view .LVU4531
+5760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13188              		.loc 1 5760 10 is_stmt 0 view .LVU4532
+ 13189 006c DAB9     		cbnz	r2, .L833
+5791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13190              		.loc 1 5791 9 is_stmt 1 view .LVU4533
+ 13191 006e 2368     		ldr	r3, [r4]
+ 13192 0070 1022     		movs	r2, #16
+ 13193              	.LVL959:
+5791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13194              		.loc 1 5791 9 is_stmt 0 view .LVU4534
+ 13195 0072 DA61     		str	r2, [r3, #28]
+5794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13196              		.loc 1 5794 9 is_stmt 1 view .LVU4535
+5794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13197              		.loc 1 5794 25 is_stmt 0 view .LVU4536
+ 13198 0074 636C     		ldr	r3, [r4, #68]
+ 13199 0076 43F00403 		orr	r3, r3, #4
+ 13200 007a 6364     		str	r3, [r4, #68]
+5797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13201              		.loc 1 5797 9 is_stmt 1 view .LVU4537
+5797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13202              		.loc 1 5797 18 is_stmt 0 view .LVU4538
+ 13203 007c 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 13204 0080 DBB2     		uxtb	r3, r3
+ 13205              	.LVL960:
+5799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13206              		.loc 1 5799 9 is_stmt 1 view .LVU4539
+5799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13207              		.loc 1 5799 12 is_stmt 0 view .LVU4540
+ 13208 0082 B0F1807F 		cmp	r0, #16777216
+ 13209 0086 18BF     		it	ne
+ 13210 0088 0028     		cmpne	r0, #0
+ 13211 008a 3FD1     		bne	.L827
+5801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 13212              		.loc 1 5801 11 is_stmt 1 view .LVU4541
+5801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 13213              		.loc 1 5801 14 is_stmt 0 view .LVU4542
+ 13214 008c 292B     		cmp	r3, #41
+ 13215 008e 18BF     		it	ne
+ 13216 0090 212B     		cmpne	r3, #33
+ 13217 0092 2AD1     		bne	.L837
+5803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 13218              		.loc 1 5803 13 is_stmt 1 view .LVU4543
+5803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 13219              		.loc 1 5803 33 is_stmt 0 view .LVU4544
+ 13220 0094 2123     		movs	r3, #33
+ 13221              	.LVL961:
+5803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 13222              		.loc 1 5803 33 view .LVU4545
+ 13223 0096 2363     		str	r3, [r4, #48]
+ 13224              	.L838:
+5812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13225              		.loc 1 5812 11 is_stmt 1 view .LVU4546
+5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13226              		.loc 1 5815 11 view .LVU4547
+ARM GAS  /tmp/ccVyGVF6.s 			page 441
+
+
+ 13227 0098 616C     		ldr	r1, [r4, #68]
+ 13228              	.LVL962:
+5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13229              		.loc 1 5815 11 is_stmt 0 view .LVU4548
+ 13230 009a 2046     		mov	r0, r4
+ 13231              	.LVL963:
+5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13232              		.loc 1 5815 11 view .LVU4549
+ 13233 009c FFF7FEFF 		bl	I2C_ITError
+ 13234              	.LVL964:
+ 13235 00a0 34E0     		b	.L827
+ 13236              	.LVL965:
+ 13237              	.L842:
+5743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 13238              		.loc 1 5743 26 view .LVU4550
+ 13239 00a2 0122     		movs	r2, #1
+ 13240              	.LVL966:
+5743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 13241              		.loc 1 5743 26 view .LVU4551
+ 13242 00a4 DCE7     		b	.L831
+ 13243              	.LVL967:
+ 13244              	.L833:
+5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 13245              		.loc 1 5762 9 is_stmt 1 view .LVU4552
+5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 13246              		.loc 1 5762 18 is_stmt 0 view .LVU4553
+ 13247 00a6 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 13248 00aa DBB2     		uxtb	r3, r3
+5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 13249              		.loc 1 5762 12 view .LVU4554
+ 13250 00ac 282B     		cmp	r3, #40
+ 13251 00ae 08D0     		beq	.L845
+ 13252              	.L835:
+5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13253              		.loc 1 5769 14 is_stmt 1 view .LVU4555
+5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13254              		.loc 1 5769 23 is_stmt 0 view .LVU4556
+ 13255 00b0 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 13256 00b4 DBB2     		uxtb	r3, r3
+5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13257              		.loc 1 5769 17 view .LVU4557
+ 13258 00b6 292B     		cmp	r3, #41
+ 13259 00b8 0AD0     		beq	.L846
+ 13260              	.L836:
+5784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13261              		.loc 1 5784 11 is_stmt 1 view .LVU4558
+ 13262 00ba 2368     		ldr	r3, [r4]
+ 13263 00bc 1022     		movs	r2, #16
+ 13264 00be DA61     		str	r2, [r3, #28]
+ 13265 00c0 24E0     		b	.L827
+ 13266              	.L845:
+5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ 13267              		.loc 1 5762 51 is_stmt 0 discriminator 1 view .LVU4559
+ 13268 00c2 B0F1007F 		cmp	r0, #33554432
+ 13269 00c6 F3D1     		bne	.L835
+5767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13270              		.loc 1 5767 11 is_stmt 1 view .LVU4560
+ARM GAS  /tmp/ccVyGVF6.s 			page 442
+
+
+ 13271 00c8 2046     		mov	r0, r4
+ 13272              	.LVL968:
+5767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13273              		.loc 1 5767 11 is_stmt 0 view .LVU4561
+ 13274 00ca FFF7FEFF 		bl	I2C_ITListenCplt
+ 13275              	.LVL969:
+5767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13276              		.loc 1 5767 11 view .LVU4562
+ 13277 00ce 1DE0     		b	.L827
+ 13278              	.LVL970:
+ 13279              	.L846:
+5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13280              		.loc 1 5769 64 discriminator 1 view .LVU4563
+ 13281 00d0 10F5803F 		cmn	r0, #65536
+ 13282 00d4 F1D0     		beq	.L836
+5772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13283              		.loc 1 5772 11 is_stmt 1 view .LVU4564
+ 13284 00d6 2368     		ldr	r3, [r4]
+ 13285 00d8 1022     		movs	r2, #16
+ 13286 00da DA61     		str	r2, [r3, #28]
+5775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13287              		.loc 1 5775 11 view .LVU4565
+ 13288 00dc 2046     		mov	r0, r4
+ 13289              	.LVL971:
+5775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13290              		.loc 1 5775 11 is_stmt 0 view .LVU4566
+ 13291 00de FFF7FEFF 		bl	I2C_Flush_TXDR
+ 13292              	.LVL972:
+5779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13293              		.loc 1 5779 11 is_stmt 1 view .LVU4567
+ 13294 00e2 2046     		mov	r0, r4
+ 13295 00e4 FFF7FEFF 		bl	I2C_ITSlaveSeqCplt
+ 13296              	.LVL973:
+ 13297 00e8 10E0     		b	.L827
+ 13298              	.LVL974:
+ 13299              	.L837:
+5805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 13300              		.loc 1 5805 16 view .LVU4568
+5805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           {
+ 13301              		.loc 1 5805 19 is_stmt 0 view .LVU4569
+ 13302 00ea 2A2B     		cmp	r3, #42
+ 13303 00ec 18BF     		it	ne
+ 13304 00ee 222B     		cmpne	r3, #34
+ 13305 00f0 D2D1     		bne	.L838
+5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 13306              		.loc 1 5807 13 is_stmt 1 view .LVU4570
+5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 13307              		.loc 1 5807 33 is_stmt 0 view .LVU4571
+ 13308 00f2 2223     		movs	r3, #34
+ 13309              	.LVL975:
+5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****           }
+ 13310              		.loc 1 5807 33 view .LVU4572
+ 13311 00f4 2363     		str	r3, [r4, #48]
+ 13312 00f6 CFE7     		b	.L838
+ 13313              	.LVL976:
+ 13314              	.L830:
+5822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ARM GAS  /tmp/ccVyGVF6.s 			page 443
+
+
+ 13315              		.loc 1 5822 7 is_stmt 1 view .LVU4573
+ 13316 00f8 2368     		ldr	r3, [r4]
+ 13317 00fa 1022     		movs	r2, #16
+ 13318              	.LVL977:
+5822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13319              		.loc 1 5822 7 is_stmt 0 view .LVU4574
+ 13320 00fc DA61     		str	r2, [r3, #28]
+ 13321 00fe 05E0     		b	.L827
+ 13322              	.LVL978:
+ 13323              	.L828:
+5825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 13324              		.loc 1 5825 8 is_stmt 1 view .LVU4575
+5825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 13325              		.loc 1 5825 11 is_stmt 0 view .LVU4576
+ 13326 0100 11F0080F 		tst	r1, #8
+ 13327 0104 02D0     		beq	.L827
+5825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 13328              		.loc 1 5825 62 discriminator 1 view .LVU4577
+ 13329 0106 12F0080F 		tst	r2, #8
+ 13330 010a 03D1     		bne	.L847
+ 13331              	.LVL979:
+ 13332              	.L827:
+5833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13333              		.loc 1 5833 3 is_stmt 1 view .LVU4578
+5836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13334              		.loc 1 5836 3 view .LVU4579
+5836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13335              		.loc 1 5836 3 view .LVU4580
+ 13336 010c 0020     		movs	r0, #0
+ 13337 010e 84F84000 		strb	r0, [r4, #64]
+5836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13338              		.loc 1 5836 3 view .LVU4581
+5838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 13339              		.loc 1 5838 3 view .LVU4582
+ 13340              	.L825:
+5839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13341              		.loc 1 5839 1 is_stmt 0 view .LVU4583
+ 13342 0112 38BD     		pop	{r3, r4, r5, pc}
+ 13343              	.LVL980:
+ 13344              	.L847:
+5828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13345              		.loc 1 5828 5 is_stmt 1 view .LVU4584
+ 13346 0114 2046     		mov	r0, r4
+ 13347              	.LVL981:
+5828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13348              		.loc 1 5828 5 is_stmt 0 view .LVU4585
+ 13349 0116 FFF7FEFF 		bl	I2C_ITAddrCplt
+ 13350              	.LVL982:
+5828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13351              		.loc 1 5828 5 view .LVU4586
+ 13352 011a F7E7     		b	.L827
+ 13353              	.LVL983:
+ 13354              	.L839:
+5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13355              		.loc 1 5717 3 view .LVU4587
+ 13356 011c 0220     		movs	r0, #2
+ 13357              	.LVL984:
+ARM GAS  /tmp/ccVyGVF6.s 			page 444
+
+
+5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13358              		.loc 1 5717 3 view .LVU4588
+ 13359 011e F8E7     		b	.L825
+ 13360              		.cfi_endproc
+ 13361              	.LFE195:
+ 13363              		.section	.text.I2C_Master_ISR_DMA,"ax",%progbits
+ 13364              		.align	1
+ 13365              		.syntax unified
+ 13366              		.thumb
+ 13367              		.thumb_func
+ 13368              		.fpu fpv5-d16
+ 13370              	I2C_Master_ISR_DMA:
+ 13371              	.LVL985:
+ 13372              	.LFB193:
+5399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t devaddress;
+ 13373              		.loc 1 5399 1 is_stmt 1 view -0
+ 13374              		.cfi_startproc
+ 13375              		@ args = 0, pretend = 0, frame = 0
+ 13376              		@ frame_needed = 0, uses_anonymous_args = 0
+5400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t xfermode;
+ 13377              		.loc 1 5400 3 view .LVU4590
+5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13378              		.loc 1 5401 3 view .LVU4591
+5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13379              		.loc 1 5404 3 view .LVU4592
+5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13380              		.loc 1 5404 3 view .LVU4593
+ 13381 0000 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 13382 0004 012B     		cmp	r3, #1
+ 13383 0006 00F0A380 		beq	.L862
+5399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint16_t devaddress;
+ 13384              		.loc 1 5399 1 is_stmt 0 discriminator 2 view .LVU4594
+ 13385 000a 10B5     		push	{r4, lr}
+ 13386              	.LCFI140:
+ 13387              		.cfi_def_cfa_offset 8
+ 13388              		.cfi_offset 4, -8
+ 13389              		.cfi_offset 14, -4
+ 13390 000c 82B0     		sub	sp, sp, #8
+ 13391              	.LCFI141:
+ 13392              		.cfi_def_cfa_offset 16
+ 13393 000e 0446     		mov	r4, r0
+5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13394              		.loc 1 5404 3 is_stmt 1 discriminator 2 view .LVU4595
+ 13395 0010 0123     		movs	r3, #1
+ 13396 0012 80F84030 		strb	r3, [r0, #64]
+5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13397              		.loc 1 5404 3 discriminator 2 view .LVU4596
+5406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 13398              		.loc 1 5406 3 discriminator 2 view .LVU4597
+5406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 13399              		.loc 1 5406 6 is_stmt 0 discriminator 2 view .LVU4598
+ 13400 0016 11F0100F 		tst	r1, #16
+ 13401 001a 02D0     		beq	.L850
+5406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 13402              		.loc 1 5406 55 discriminator 1 view .LVU4599
+ 13403 001c 12F0100F 		tst	r2, #16
+ 13404 0020 1FD1     		bne	.L868
+ARM GAS  /tmp/ccVyGVF6.s 			page 445
+
+
+ 13405              	.L850:
+5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 13406              		.loc 1 5423 8 is_stmt 1 view .LVU4600
+5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 13407              		.loc 1 5423 11 is_stmt 0 view .LVU4601
+ 13408 0022 11F0800F 		tst	r1, #128
+ 13409 0026 69D0     		beq	.L852
+5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 13410              		.loc 1 5423 61 discriminator 1 view .LVU4602
+ 13411 0028 12F0400F 		tst	r2, #64
+ 13412 002c 66D0     		beq	.L852
+5427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13413              		.loc 1 5427 5 is_stmt 1 view .LVU4603
+ 13414 002e 2268     		ldr	r2, [r4]
+ 13415              	.LVL986:
+5427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13416              		.loc 1 5427 5 is_stmt 0 view .LVU4604
+ 13417 0030 1368     		ldr	r3, [r2]
+ 13418 0032 23F04003 		bic	r3, r3, #64
+ 13419 0036 1360     		str	r3, [r2]
+5429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13420              		.loc 1 5429 5 is_stmt 1 view .LVU4605
+5429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13421              		.loc 1 5429 13 is_stmt 0 view .LVU4606
+ 13422 0038 638D     		ldrh	r3, [r4, #42]
+ 13423 003a 9BB2     		uxth	r3, r3
+5429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13424              		.loc 1 5429 8 view .LVU4607
+ 13425 003c 002B     		cmp	r3, #0
+ 13426 003e 4FD0     		beq	.L853
+5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13427              		.loc 1 5432 7 is_stmt 1 view .LVU4608
+5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13428              		.loc 1 5432 35 is_stmt 0 view .LVU4609
+ 13429 0040 2268     		ldr	r2, [r4]
+5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13430              		.loc 1 5432 45 view .LVU4610
+ 13431 0042 5168     		ldr	r1, [r2, #4]
+ 13432              	.LVL987:
+5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13433              		.loc 1 5432 18 view .LVU4611
+ 13434 0044 C1F30901 		ubfx	r1, r1, #0, #10
+ 13435              	.LVL988:
+5435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13436              		.loc 1 5435 7 is_stmt 1 view .LVU4612
+5435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13437              		.loc 1 5435 15 is_stmt 0 view .LVU4613
+ 13438 0048 638D     		ldrh	r3, [r4, #42]
+ 13439 004a 9BB2     		uxth	r3, r3
+5435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13440              		.loc 1 5435 10 view .LVU4614
+ 13441 004c FF2B     		cmp	r3, #255
+ 13442 004e 1FD9     		bls	.L854
+5438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13443              		.loc 1 5438 9 is_stmt 1 view .LVU4615
+5438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13444              		.loc 1 5438 13 is_stmt 0 view .LVU4616
+ARM GAS  /tmp/ccVyGVF6.s 			page 446
+
+
+ 13445 0050 9369     		ldr	r3, [r2, #24]
+5438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13446              		.loc 1 5438 12 view .LVU4617
+ 13447 0052 13F4803F 		tst	r3, #65536
+ 13448 0056 16D0     		beq	.L855
+5440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13449              		.loc 1 5440 11 is_stmt 1 view .LVU4618
+5440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13450              		.loc 1 5440 26 is_stmt 0 view .LVU4619
+ 13451 0058 0123     		movs	r3, #1
+ 13452 005a 2385     		strh	r3, [r4, #40]	@ movhi
+5446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13453              		.loc 1 5446 18 view .LVU4620
+ 13454 005c 4FF08073 		mov	r3, #16777216
+ 13455 0060 1DE0     		b	.L856
+ 13456              	.LVL989:
+ 13457              	.L868:
+5410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13458              		.loc 1 5410 5 is_stmt 1 view .LVU4621
+ 13459 0062 0368     		ldr	r3, [r0]
+ 13460 0064 1022     		movs	r2, #16
+ 13461              	.LVL990:
+5410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13462              		.loc 1 5410 5 is_stmt 0 view .LVU4622
+ 13463 0066 DA61     		str	r2, [r3, #28]
+5413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13464              		.loc 1 5413 5 is_stmt 1 view .LVU4623
+5413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13465              		.loc 1 5413 21 is_stmt 0 view .LVU4624
+ 13466 0068 436C     		ldr	r3, [r0, #68]
+ 13467 006a 43F00403 		orr	r3, r3, #4
+ 13468 006e 4364     		str	r3, [r0, #68]
+5418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13469              		.loc 1 5418 5 is_stmt 1 view .LVU4625
+ 13470 0070 2021     		movs	r1, #32
+ 13471              	.LVL991:
+5418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13472              		.loc 1 5418 5 is_stmt 0 view .LVU4626
+ 13473 0072 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 13474              	.LVL992:
+5421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13475              		.loc 1 5421 5 is_stmt 1 view .LVU4627
+ 13476 0076 2046     		mov	r0, r4
+ 13477 0078 FFF7FEFF 		bl	I2C_Flush_TXDR
+ 13478              	.LVL993:
+ 13479              	.L851:
+5529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13480              		.loc 1 5529 3 view .LVU4628
+5532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13481              		.loc 1 5532 3 view .LVU4629
+5532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13482              		.loc 1 5532 3 view .LVU4630
+ 13483 007c 0020     		movs	r0, #0
+ 13484 007e 84F84000 		strb	r0, [r4, #64]
+5532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13485              		.loc 1 5532 3 view .LVU4631
+5534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ARM GAS  /tmp/ccVyGVF6.s 			page 447
+
+
+ 13486              		.loc 1 5534 3 view .LVU4632
+5535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13487              		.loc 1 5535 1 is_stmt 0 view .LVU4633
+ 13488 0082 02B0     		add	sp, sp, #8
+ 13489              	.LCFI142:
+ 13490              		.cfi_remember_state
+ 13491              		.cfi_def_cfa_offset 8
+ 13492              		@ sp needed
+ 13493 0084 10BD     		pop	{r4, pc}
+ 13494              	.LVL994:
+ 13495              	.L855:
+ 13496              	.LCFI143:
+ 13497              		.cfi_restore_state
+5444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13498              		.loc 1 5444 11 is_stmt 1 view .LVU4634
+5444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13499              		.loc 1 5444 26 is_stmt 0 view .LVU4635
+ 13500 0086 FF23     		movs	r3, #255
+ 13501 0088 2385     		strh	r3, [r4, #40]	@ movhi
+5446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13502              		.loc 1 5446 18 view .LVU4636
+ 13503 008a 4FF08073 		mov	r3, #16777216
+ 13504 008e 06E0     		b	.L856
+ 13505              	.L854:
+5450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 13506              		.loc 1 5450 9 is_stmt 1 view .LVU4637
+5450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 13507              		.loc 1 5450 30 is_stmt 0 view .LVU4638
+ 13508 0090 638D     		ldrh	r3, [r4, #42]
+5450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 13509              		.loc 1 5450 24 view .LVU4639
+ 13510 0092 2385     		strh	r3, [r4, #40]	@ movhi
+5451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13511              		.loc 1 5451 9 is_stmt 1 view .LVU4640
+5451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13512              		.loc 1 5451 17 is_stmt 0 view .LVU4641
+ 13513 0094 E36A     		ldr	r3, [r4, #44]
+5451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13514              		.loc 1 5451 12 view .LVU4642
+ 13515 0096 13F5803F 		cmn	r3, #65536
+ 13516 009a 18D0     		beq	.L863
+5453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13517              		.loc 1 5453 11 is_stmt 1 view .LVU4643
+5453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13518              		.loc 1 5453 20 is_stmt 0 view .LVU4644
+ 13519 009c E36A     		ldr	r3, [r4, #44]
+ 13520              	.LVL995:
+ 13521              	.L856:
+5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13522              		.loc 1 5462 7 is_stmt 1 view .LVU4645
+ 13523 009e 0022     		movs	r2, #0
+ 13524 00a0 0092     		str	r2, [sp]
+ 13525 00a2 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 13526 00a6 2046     		mov	r0, r4
+ 13527              	.LVL996:
+5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13528              		.loc 1 5462 7 is_stmt 0 view .LVU4646
+ARM GAS  /tmp/ccVyGVF6.s 			page 448
+
+
+ 13529 00a8 FFF7FEFF 		bl	I2C_TransferConfig
+ 13530              	.LVL997:
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13531              		.loc 1 5465 7 is_stmt 1 view .LVU4647
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13532              		.loc 1 5465 23 is_stmt 0 view .LVU4648
+ 13533 00ac 638D     		ldrh	r3, [r4, #42]
+ 13534 00ae 9BB2     		uxth	r3, r3
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13535              		.loc 1 5465 30 view .LVU4649
+ 13536 00b0 228D     		ldrh	r2, [r4, #40]
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13537              		.loc 1 5465 23 view .LVU4650
+ 13538 00b2 9B1A     		subs	r3, r3, r2
+ 13539 00b4 9BB2     		uxth	r3, r3
+ 13540 00b6 6385     		strh	r3, [r4, #42]	@ movhi
+5468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13541              		.loc 1 5468 7 is_stmt 1 view .LVU4651
+5468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13542              		.loc 1 5468 15 is_stmt 0 view .LVU4652
+ 13543 00b8 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 13544 00bc DBB2     		uxtb	r3, r3
+5468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13545              		.loc 1 5468 10 view .LVU4653
+ 13546 00be 222B     		cmp	r3, #34
+ 13547 00c0 08D0     		beq	.L869
+5474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13548              		.loc 1 5474 9 is_stmt 1 view .LVU4654
+5474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13549              		.loc 1 5474 13 is_stmt 0 view .LVU4655
+ 13550 00c2 2268     		ldr	r2, [r4]
+5474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13551              		.loc 1 5474 29 view .LVU4656
+ 13552 00c4 1368     		ldr	r3, [r2]
+ 13553 00c6 43F48043 		orr	r3, r3, #16384
+ 13554 00ca 1360     		str	r3, [r2]
+ 13555 00cc D6E7     		b	.L851
+ 13556              	.LVL998:
+ 13557              	.L863:
+5457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13558              		.loc 1 5457 20 view .LVU4657
+ 13559 00ce 4FF00073 		mov	r3, #33554432
+ 13560 00d2 E4E7     		b	.L856
+ 13561              	.LVL999:
+ 13562              	.L869:
+5470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13563              		.loc 1 5470 9 is_stmt 1 view .LVU4658
+5470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13564              		.loc 1 5470 13 is_stmt 0 view .LVU4659
+ 13565 00d4 2268     		ldr	r2, [r4]
+5470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13566              		.loc 1 5470 29 view .LVU4660
+ 13567 00d6 1368     		ldr	r3, [r2]
+ 13568 00d8 43F40043 		orr	r3, r3, #32768
+ 13569 00dc 1360     		str	r3, [r2]
+ 13570 00de CDE7     		b	.L851
+ 13571              	.LVL1000:
+ARM GAS  /tmp/ccVyGVF6.s 			page 449
+
+
+ 13572              	.L853:
+5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13573              		.loc 1 5480 7 is_stmt 1 view .LVU4661
+5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13574              		.loc 1 5480 11 is_stmt 0 view .LVU4662
+ 13575 00e0 2368     		ldr	r3, [r4]
+ 13576 00e2 5B68     		ldr	r3, [r3, #4]
+5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13577              		.loc 1 5480 10 view .LVU4663
+ 13578 00e4 13F0007F 		tst	r3, #33554432
+ 13579 00e8 03D1     		bne	.L858
+5483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13580              		.loc 1 5483 9 is_stmt 1 view .LVU4664
+ 13581 00ea 2046     		mov	r0, r4
+ 13582              	.LVL1001:
+5483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13583              		.loc 1 5483 9 is_stmt 0 view .LVU4665
+ 13584 00ec FFF7FEFF 		bl	I2C_ITMasterSeqCplt
+ 13585              	.LVL1002:
+5483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13586              		.loc 1 5483 9 view .LVU4666
+ 13587 00f0 C4E7     		b	.L851
+ 13588              	.LVL1003:
+ 13589              	.L858:
+5489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13590              		.loc 1 5489 9 is_stmt 1 view .LVU4667
+ 13591 00f2 4021     		movs	r1, #64
+ 13592              	.LVL1004:
+5489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13593              		.loc 1 5489 9 is_stmt 0 view .LVU4668
+ 13594 00f4 2046     		mov	r0, r4
+ 13595              	.LVL1005:
+5489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13596              		.loc 1 5489 9 view .LVU4669
+ 13597 00f6 FFF7FEFF 		bl	I2C_ITError
+ 13598              	.LVL1006:
+ 13599 00fa BFE7     		b	.L851
+ 13600              	.LVL1007:
+ 13601              	.L852:
+5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 13602              		.loc 1 5493 8 is_stmt 1 view .LVU4670
+5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 13603              		.loc 1 5493 11 is_stmt 0 view .LVU4671
+ 13604 00fc 11F0400F 		tst	r1, #64
+ 13605 0100 1CD0     		beq	.L859
+5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 13606              		.loc 1 5493 60 discriminator 1 view .LVU4672
+ 13607 0102 12F0400F 		tst	r2, #64
+ 13608 0106 19D0     		beq	.L859
+5496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13609              		.loc 1 5496 5 is_stmt 1 view .LVU4673
+5496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13610              		.loc 1 5496 13 is_stmt 0 view .LVU4674
+ 13611 0108 638D     		ldrh	r3, [r4, #42]
+ 13612 010a 9BB2     		uxth	r3, r3
+5496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13613              		.loc 1 5496 8 view .LVU4675
+ARM GAS  /tmp/ccVyGVF6.s 			page 450
+
+
+ 13614 010c 8BB9     		cbnz	r3, .L860
+5498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13615              		.loc 1 5498 7 is_stmt 1 view .LVU4676
+5498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13616              		.loc 1 5498 11 is_stmt 0 view .LVU4677
+ 13617 010e 2368     		ldr	r3, [r4]
+ 13618 0110 5A68     		ldr	r2, [r3, #4]
+ 13619              	.LVL1008:
+5498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13620              		.loc 1 5498 10 view .LVU4678
+ 13621 0112 12F0007F 		tst	r2, #33554432
+ 13622 0116 B1D1     		bne	.L851
+5501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13623              		.loc 1 5501 9 is_stmt 1 view .LVU4679
+5501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13624              		.loc 1 5501 17 is_stmt 0 view .LVU4680
+ 13625 0118 E26A     		ldr	r2, [r4, #44]
+5501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 13626              		.loc 1 5501 12 view .LVU4681
+ 13627 011a 12F5803F 		cmn	r2, #65536
+ 13628 011e 04D1     		bne	.L861
+5504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13629              		.loc 1 5504 11 is_stmt 1 view .LVU4682
+5504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13630              		.loc 1 5504 31 is_stmt 0 view .LVU4683
+ 13631 0120 5A68     		ldr	r2, [r3, #4]
+ 13632 0122 42F48042 		orr	r2, r2, #16384
+ 13633 0126 5A60     		str	r2, [r3, #4]
+ 13634 0128 A8E7     		b	.L851
+ 13635              	.L861:
+5509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13636              		.loc 1 5509 11 is_stmt 1 view .LVU4684
+ 13637 012a 2046     		mov	r0, r4
+ 13638              	.LVL1009:
+5509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13639              		.loc 1 5509 11 is_stmt 0 view .LVU4685
+ 13640 012c FFF7FEFF 		bl	I2C_ITMasterSeqCplt
+ 13641              	.LVL1010:
+5509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 13642              		.loc 1 5509 11 view .LVU4686
+ 13643 0130 A4E7     		b	.L851
+ 13644              	.LVL1011:
+ 13645              	.L860:
+5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13646              		.loc 1 5517 7 is_stmt 1 view .LVU4687
+ 13647 0132 4021     		movs	r1, #64
+ 13648              	.LVL1012:
+5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13649              		.loc 1 5517 7 is_stmt 0 view .LVU4688
+ 13650 0134 2046     		mov	r0, r4
+ 13651              	.LVL1013:
+5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13652              		.loc 1 5517 7 view .LVU4689
+ 13653 0136 FFF7FEFF 		bl	I2C_ITError
+ 13654              	.LVL1014:
+5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13655              		.loc 1 5517 7 view .LVU4690
+ARM GAS  /tmp/ccVyGVF6.s 			page 451
+
+
+ 13656 013a 9FE7     		b	.L851
+ 13657              	.LVL1015:
+ 13658              	.L859:
+5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 13659              		.loc 1 5520 8 is_stmt 1 view .LVU4691
+5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 13660              		.loc 1 5520 11 is_stmt 0 view .LVU4692
+ 13661 013c 11F0200F 		tst	r1, #32
+ 13662 0140 9CD0     		beq	.L851
+5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 13663              		.loc 1 5520 63 discriminator 1 view .LVU4693
+ 13664 0142 12F0200F 		tst	r2, #32
+ 13665 0146 99D0     		beq	.L851
+5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13666              		.loc 1 5524 5 is_stmt 1 view .LVU4694
+ 13667 0148 2046     		mov	r0, r4
+ 13668              	.LVL1016:
+5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13669              		.loc 1 5524 5 is_stmt 0 view .LVU4695
+ 13670 014a FFF7FEFF 		bl	I2C_ITMasterCplt
+ 13671              	.LVL1017:
+5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13672              		.loc 1 5524 5 view .LVU4696
+ 13673 014e 95E7     		b	.L851
+ 13674              	.LVL1018:
+ 13675              	.L862:
+ 13676              	.LCFI144:
+ 13677              		.cfi_def_cfa_offset 0
+ 13678              		.cfi_restore 4
+ 13679              		.cfi_restore 14
+5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13680              		.loc 1 5404 3 view .LVU4697
+ 13681 0150 0220     		movs	r0, #2
+ 13682              	.LVL1019:
+5535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13683              		.loc 1 5535 1 view .LVU4698
+ 13684 0152 7047     		bx	lr
+ 13685              		.cfi_endproc
+ 13686              	.LFE193:
+ 13688              		.section	.text.I2C_DMAError,"ax",%progbits
+ 13689              		.align	1
+ 13690              		.syntax unified
+ 13691              		.thumb
+ 13692              		.thumb_func
+ 13693              		.fpu fpv5-d16
+ 13695              	I2C_DMAError:
+ 13696              	.LVL1020:
+ 13697              	.LFB211:
+6948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t treatdmaerror = 0U;
+ 13698              		.loc 1 6948 1 is_stmt 1 view -0
+ 13699              		.cfi_startproc
+ 13700              		@ args = 0, pretend = 0, frame = 0
+ 13701              		@ frame_needed = 0, uses_anonymous_args = 0
+6948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t treatdmaerror = 0U;
+ 13702              		.loc 1 6948 1 is_stmt 0 view .LVU4700
+ 13703 0000 38B5     		push	{r3, r4, r5, lr}
+ 13704              	.LCFI145:
+ARM GAS  /tmp/ccVyGVF6.s 			page 452
+
+
+ 13705              		.cfi_def_cfa_offset 16
+ 13706              		.cfi_offset 3, -16
+ 13707              		.cfi_offset 4, -12
+ 13708              		.cfi_offset 5, -8
+ 13709              		.cfi_offset 14, -4
+6949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 13710              		.loc 1 6949 3 is_stmt 1 view .LVU4701
+ 13711              	.LVL1021:
+6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13712              		.loc 1 6951 3 view .LVU4702
+6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13713              		.loc 1 6951 22 is_stmt 0 view .LVU4703
+ 13714 0002 846B     		ldr	r4, [r0, #56]
+ 13715              	.LVL1022:
+6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13716              		.loc 1 6953 3 is_stmt 1 view .LVU4704
+6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13717              		.loc 1 6953 11 is_stmt 0 view .LVU4705
+ 13718 0004 A36B     		ldr	r3, [r4, #56]
+6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13719              		.loc 1 6953 6 view .LVU4706
+ 13720 0006 7BB1     		cbz	r3, .L874
+6955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13721              		.loc 1 6955 5 is_stmt 1 view .LVU4707
+6955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13722              		.loc 1 6955 9 is_stmt 0 view .LVU4708
+ 13723 0008 1B68     		ldr	r3, [r3]
+ 13724 000a 5B68     		ldr	r3, [r3, #4]
+6955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13725              		.loc 1 6955 8 view .LVU4709
+ 13726 000c 73B1     		cbz	r3, .L875
+6949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 13727              		.loc 1 6949 12 view .LVU4710
+ 13728 000e 0025     		movs	r5, #0
+ 13729              	.L871:
+ 13730              	.LVL1023:
+6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13731              		.loc 1 6961 3 is_stmt 1 view .LVU4711
+6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13732              		.loc 1 6961 11 is_stmt 0 view .LVU4712
+ 13733 0010 E36B     		ldr	r3, [r4, #60]
+6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13734              		.loc 1 6961 6 view .LVU4713
+ 13735 0012 1BB1     		cbz	r3, .L872
+6963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13736              		.loc 1 6963 5 is_stmt 1 view .LVU4714
+6963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13737              		.loc 1 6963 9 is_stmt 0 view .LVU4715
+ 13738 0014 1B68     		ldr	r3, [r3]
+ 13739 0016 5B68     		ldr	r3, [r3, #4]
+6963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13740              		.loc 1 6963 8 view .LVU4716
+ 13741 0018 03B9     		cbnz	r3, .L872
+6965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13742              		.loc 1 6965 21 view .LVU4717
+ 13743 001a 0125     		movs	r5, #1
+ 13744              	.LVL1024:
+ARM GAS  /tmp/ccVyGVF6.s 			page 453
+
+
+ 13745              	.L872:
+6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13746              		.loc 1 6970 3 is_stmt 1 view .LVU4718
+6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13747              		.loc 1 6970 10 is_stmt 0 view .LVU4719
+ 13748 001c FFF7FEFF 		bl	HAL_DMA_GetError
+ 13749              	.LVL1025:
+6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13750              		.loc 1 6970 6 view .LVU4720
+ 13751 0020 0228     		cmp	r0, #2
+ 13752 0022 00D0     		beq	.L870
+6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13753              		.loc 1 6970 55 discriminator 1 view .LVU4721
+ 13754 0024 25B9     		cbnz	r5, .L878
+ 13755              	.L870:
+6978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13756              		.loc 1 6978 1 view .LVU4722
+ 13757 0026 38BD     		pop	{r3, r4, r5, pc}
+ 13758              	.LVL1026:
+ 13759              	.L874:
+6949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 13760              		.loc 1 6949 12 view .LVU4723
+ 13761 0028 0025     		movs	r5, #0
+ 13762 002a F1E7     		b	.L871
+ 13763              	.L875:
+6957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13764              		.loc 1 6957 21 view .LVU4724
+ 13765 002c 0125     		movs	r5, #1
+ 13766 002e EFE7     		b	.L871
+ 13767              	.LVL1027:
+ 13768              	.L878:
+6973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13769              		.loc 1 6973 5 is_stmt 1 view .LVU4725
+6973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13770              		.loc 1 6973 9 is_stmt 0 view .LVU4726
+ 13771 0030 2268     		ldr	r2, [r4]
+6973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13772              		.loc 1 6973 25 view .LVU4727
+ 13773 0032 5368     		ldr	r3, [r2, #4]
+ 13774 0034 43F40043 		orr	r3, r3, #32768
+ 13775 0038 5360     		str	r3, [r2, #4]
+6976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13776              		.loc 1 6976 5 is_stmt 1 view .LVU4728
+ 13777 003a 1021     		movs	r1, #16
+ 13778 003c 2046     		mov	r0, r4
+ 13779 003e FFF7FEFF 		bl	I2C_ITError
+ 13780              	.LVL1028:
+6978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13781              		.loc 1 6978 1 is_stmt 0 view .LVU4729
+ 13782 0042 F0E7     		b	.L870
+ 13783              		.cfi_endproc
+ 13784              	.LFE211:
+ 13786              		.section	.text.I2C_DMAMasterTransmitCplt,"ax",%progbits
+ 13787              		.align	1
+ 13788              		.syntax unified
+ 13789              		.thumb
+ 13790              		.thumb_func
+ARM GAS  /tmp/ccVyGVF6.s 			page 454
+
+
+ 13791              		.fpu fpv5-d16
+ 13793              	I2C_DMAMasterTransmitCplt:
+ 13794              	.LVL1029:
+ 13795              	.LFB207:
+6780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 13796              		.loc 1 6780 1 is_stmt 1 view -0
+ 13797              		.cfi_startproc
+ 13798              		@ args = 0, pretend = 0, frame = 0
+ 13799              		@ frame_needed = 0, uses_anonymous_args = 0
+6780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 13800              		.loc 1 6780 1 is_stmt 0 view .LVU4731
+ 13801 0000 10B5     		push	{r4, lr}
+ 13802              	.LCFI146:
+ 13803              		.cfi_def_cfa_offset 8
+ 13804              		.cfi_offset 4, -8
+ 13805              		.cfi_offset 14, -4
+6782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13806              		.loc 1 6782 3 is_stmt 1 view .LVU4732
+6782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13807              		.loc 1 6782 22 is_stmt 0 view .LVU4733
+ 13808 0002 846B     		ldr	r4, [r0, #56]
+ 13809              	.LVL1030:
+6785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13810              		.loc 1 6785 3 is_stmt 1 view .LVU4734
+6785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13811              		.loc 1 6785 7 is_stmt 0 view .LVU4735
+ 13812 0004 2268     		ldr	r2, [r4]
+6785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13813              		.loc 1 6785 23 view .LVU4736
+ 13814 0006 1368     		ldr	r3, [r2]
+ 13815 0008 23F48043 		bic	r3, r3, #16384
+ 13816 000c 1360     		str	r3, [r2]
+6788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13817              		.loc 1 6788 3 is_stmt 1 view .LVU4737
+6788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13818              		.loc 1 6788 11 is_stmt 0 view .LVU4738
+ 13819 000e 638D     		ldrh	r3, [r4, #42]
+ 13820 0010 9BB2     		uxth	r3, r3
+6788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13821              		.loc 1 6788 6 view .LVU4739
+ 13822 0012 ABB1     		cbz	r3, .L886
+6797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13823              		.loc 1 6797 5 is_stmt 1 view .LVU4740
+6797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13824              		.loc 1 6797 27 is_stmt 0 view .LVU4741
+ 13825 0014 238D     		ldrh	r3, [r4, #40]
+6797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13826              		.loc 1 6797 20 view .LVU4742
+ 13827 0016 616A     		ldr	r1, [r4, #36]
+ 13828 0018 1944     		add	r1, r1, r3
+ 13829 001a 6162     		str	r1, [r4, #36]
+6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13830              		.loc 1 6800 5 is_stmt 1 view .LVU4743
+6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13831              		.loc 1 6800 13 is_stmt 0 view .LVU4744
+ 13832 001c 638D     		ldrh	r3, [r4, #42]
+ 13833 001e 9BB2     		uxth	r3, r3
+ARM GAS  /tmp/ccVyGVF6.s 			page 455
+
+
+6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13834              		.loc 1 6800 8 view .LVU4745
+ 13835 0020 FF2B     		cmp	r3, #255
+ 13836 0022 12D9     		bls	.L882
+6802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13837              		.loc 1 6802 7 is_stmt 1 view .LVU4746
+6802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13838              		.loc 1 6802 22 is_stmt 0 view .LVU4747
+ 13839 0024 FF23     		movs	r3, #255
+ 13840 0026 2385     		strh	r3, [r4, #40]	@ movhi
+ 13841              	.L883:
+6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 13842              		.loc 1 6810 5 is_stmt 1 view .LVU4748
+6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 13843              		.loc 1 6810 81 is_stmt 0 view .LVU4749
+ 13844 0028 2268     		ldr	r2, [r4]
+6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 13845              		.loc 1 6810 9 view .LVU4750
+ 13846 002a 238D     		ldrh	r3, [r4, #40]
+ 13847 002c 2832     		adds	r2, r2, #40
+ 13848 002e A06B     		ldr	r0, [r4, #56]
+ 13849              	.LVL1031:
+6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 13850              		.loc 1 6810 9 view .LVU4751
+ 13851 0030 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 13852              	.LVL1032:
+6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 13853              		.loc 1 6810 8 view .LVU4752
+ 13854 0034 60B1     		cbz	r0, .L884
+6814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13855              		.loc 1 6814 7 is_stmt 1 view .LVU4753
+ 13856 0036 1021     		movs	r1, #16
+ 13857 0038 2046     		mov	r0, r4
+ 13858 003a FFF7FEFF 		bl	I2C_ITError
+ 13859              	.LVL1033:
+ 13860              	.L879:
+6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13861              		.loc 1 6822 1 is_stmt 0 view .LVU4754
+ 13862 003e 10BD     		pop	{r4, pc}
+ 13863              	.LVL1034:
+ 13864              	.L886:
+6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13865              		.loc 1 6791 5 is_stmt 1 view .LVU4755
+ 13866 0040 2021     		movs	r1, #32
+ 13867 0042 2046     		mov	r0, r4
+ 13868              	.LVL1035:
+6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13869              		.loc 1 6791 5 is_stmt 0 view .LVU4756
+ 13870 0044 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 13871              	.LVL1036:
+ 13872 0048 F9E7     		b	.L879
+ 13873              	.LVL1037:
+ 13874              	.L882:
+6806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13875              		.loc 1 6806 7 is_stmt 1 view .LVU4757
+6806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13876              		.loc 1 6806 28 is_stmt 0 view .LVU4758
+ARM GAS  /tmp/ccVyGVF6.s 			page 456
+
+
+ 13877 004a 638D     		ldrh	r3, [r4, #42]
+6806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13878              		.loc 1 6806 22 view .LVU4759
+ 13879 004c 2385     		strh	r3, [r4, #40]	@ movhi
+ 13880 004e EBE7     		b	.L883
+ 13881              	.LVL1038:
+ 13882              	.L884:
+6819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13883              		.loc 1 6819 7 is_stmt 1 view .LVU4760
+ 13884 0050 4021     		movs	r1, #64
+ 13885 0052 2046     		mov	r0, r4
+ 13886 0054 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 13887              	.LVL1039:
+6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13888              		.loc 1 6822 1 is_stmt 0 view .LVU4761
+ 13889 0058 F1E7     		b	.L879
+ 13890              		.cfi_endproc
+ 13891              	.LFE207:
+ 13893              		.section	.text.I2C_DMAMasterReceiveCplt,"ax",%progbits
+ 13894              		.align	1
+ 13895              		.syntax unified
+ 13896              		.thumb
+ 13897              		.thumb_func
+ 13898              		.fpu fpv5-d16
+ 13900              	I2C_DMAMasterReceiveCplt:
+ 13901              	.LVL1040:
+ 13902              	.LFB209:
+6860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 13903              		.loc 1 6860 1 is_stmt 1 view -0
+ 13904              		.cfi_startproc
+ 13905              		@ args = 0, pretend = 0, frame = 0
+ 13906              		@ frame_needed = 0, uses_anonymous_args = 0
+6860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 13907              		.loc 1 6860 1 is_stmt 0 view .LVU4763
+ 13908 0000 10B5     		push	{r4, lr}
+ 13909              	.LCFI147:
+ 13910              		.cfi_def_cfa_offset 8
+ 13911              		.cfi_offset 4, -8
+ 13912              		.cfi_offset 14, -4
+6862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13913              		.loc 1 6862 3 is_stmt 1 view .LVU4764
+6862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13914              		.loc 1 6862 22 is_stmt 0 view .LVU4765
+ 13915 0002 846B     		ldr	r4, [r0, #56]
+ 13916              	.LVL1041:
+6865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13917              		.loc 1 6865 3 is_stmt 1 view .LVU4766
+6865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13918              		.loc 1 6865 7 is_stmt 0 view .LVU4767
+ 13919 0004 2268     		ldr	r2, [r4]
+6865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13920              		.loc 1 6865 23 view .LVU4768
+ 13921 0006 1368     		ldr	r3, [r2]
+ 13922 0008 23F40043 		bic	r3, r3, #32768
+ 13923 000c 1360     		str	r3, [r2]
+6868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13924              		.loc 1 6868 3 is_stmt 1 view .LVU4769
+ARM GAS  /tmp/ccVyGVF6.s 			page 457
+
+
+6868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13925              		.loc 1 6868 11 is_stmt 0 view .LVU4770
+ 13926 000e 638D     		ldrh	r3, [r4, #42]
+ 13927 0010 9BB2     		uxth	r3, r3
+6868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 13928              		.loc 1 6868 6 view .LVU4771
+ 13929 0012 7BB1     		cbz	r3, .L895
+6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13930              		.loc 1 6877 5 is_stmt 1 view .LVU4772
+6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13931              		.loc 1 6877 27 is_stmt 0 view .LVU4773
+ 13932 0014 238D     		ldrh	r3, [r4, #40]
+6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13933              		.loc 1 6877 20 view .LVU4774
+ 13934 0016 626A     		ldr	r2, [r4, #36]
+ 13935 0018 1A44     		add	r2, r2, r3
+ 13936 001a 6262     		str	r2, [r4, #36]
+6880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13937              		.loc 1 6880 5 is_stmt 1 view .LVU4775
+6880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13938              		.loc 1 6880 13 is_stmt 0 view .LVU4776
+ 13939 001c 638D     		ldrh	r3, [r4, #42]
+ 13940 001e 9BB2     		uxth	r3, r3
+6880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 13941              		.loc 1 6880 8 view .LVU4777
+ 13942 0020 FF2B     		cmp	r3, #255
+ 13943 0022 0FD9     		bls	.L890
+6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13944              		.loc 1 6883 7 is_stmt 1 view .LVU4778
+6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13945              		.loc 1 6883 11 is_stmt 0 view .LVU4779
+ 13946 0024 2368     		ldr	r3, [r4]
+ 13947 0026 9B69     		ldr	r3, [r3, #24]
+6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 13948              		.loc 1 6883 10 view .LVU4780
+ 13949 0028 13F4803F 		tst	r3, #65536
+ 13950 002c 07D0     		beq	.L891
+6885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13951              		.loc 1 6885 9 is_stmt 1 view .LVU4781
+6885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13952              		.loc 1 6885 24 is_stmt 0 view .LVU4782
+ 13953 002e 0123     		movs	r3, #1
+ 13954 0030 2385     		strh	r3, [r4, #40]	@ movhi
+ 13955 0032 09E0     		b	.L892
+ 13956              	.L895:
+6871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13957              		.loc 1 6871 5 is_stmt 1 view .LVU4783
+ 13958 0034 2021     		movs	r1, #32
+ 13959 0036 2046     		mov	r0, r4
+ 13960              	.LVL1042:
+6871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 13961              		.loc 1 6871 5 is_stmt 0 view .LVU4784
+ 13962 0038 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 13963              	.LVL1043:
+ 13964 003c 0FE0     		b	.L887
+ 13965              	.LVL1044:
+ 13966              	.L891:
+ARM GAS  /tmp/ccVyGVF6.s 			page 458
+
+
+6889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13967              		.loc 1 6889 9 is_stmt 1 view .LVU4785
+6889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 13968              		.loc 1 6889 24 is_stmt 0 view .LVU4786
+ 13969 003e FF23     		movs	r3, #255
+ 13970 0040 2385     		strh	r3, [r4, #40]	@ movhi
+ 13971 0042 01E0     		b	.L892
+ 13972              	.L890:
+6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13973              		.loc 1 6894 7 is_stmt 1 view .LVU4787
+6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13974              		.loc 1 6894 28 is_stmt 0 view .LVU4788
+ 13975 0044 638D     		ldrh	r3, [r4, #42]
+6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13976              		.loc 1 6894 22 view .LVU4789
+ 13977 0046 2385     		strh	r3, [r4, #40]	@ movhi
+ 13978              	.L892:
+6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 13979              		.loc 1 6898 5 is_stmt 1 view .LVU4790
+6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 13980              		.loc 1 6898 55 is_stmt 0 view .LVU4791
+ 13981 0048 2168     		ldr	r1, [r4]
+6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 13982              		.loc 1 6898 9 view .LVU4792
+ 13983 004a 238D     		ldrh	r3, [r4, #40]
+ 13984 004c 2431     		adds	r1, r1, #36
+ 13985 004e E06B     		ldr	r0, [r4, #60]
+ 13986              	.LVL1045:
+6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 13987              		.loc 1 6898 9 view .LVU4793
+ 13988 0050 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 13989              	.LVL1046:
+6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          hi2c->XferSize) != HAL_OK)
+ 13990              		.loc 1 6898 8 view .LVU4794
+ 13991 0054 20B1     		cbz	r0, .L893
+6902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 13992              		.loc 1 6902 7 is_stmt 1 view .LVU4795
+ 13993 0056 1021     		movs	r1, #16
+ 13994 0058 2046     		mov	r0, r4
+ 13995 005a FFF7FEFF 		bl	I2C_ITError
+ 13996              	.LVL1047:
+ 13997              	.L887:
+6910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 13998              		.loc 1 6910 1 is_stmt 0 view .LVU4796
+ 13999 005e 10BD     		pop	{r4, pc}
+ 14000              	.LVL1048:
+ 14001              	.L893:
+6907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 14002              		.loc 1 6907 7 is_stmt 1 view .LVU4797
+ 14003 0060 4021     		movs	r1, #64
+ 14004 0062 2046     		mov	r0, r4
+ 14005 0064 FFF7FEFF 		bl	I2C_Enable_IRQ
+ 14006              	.LVL1049:
+6910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14007              		.loc 1 6910 1 is_stmt 0 view .LVU4798
+ 14008 0068 F9E7     		b	.L887
+ 14009              		.cfi_endproc
+ARM GAS  /tmp/ccVyGVF6.s 			page 459
+
+
+ 14010              	.LFE209:
+ 14012              		.section	.text.I2C_Mem_ISR_IT,"ax",%progbits
+ 14013              		.align	1
+ 14014              		.syntax unified
+ 14015              		.thumb
+ 14016              		.thumb_func
+ 14017              		.fpu fpv5-d16
+ 14019              	I2C_Mem_ISR_IT:
+ 14020              	.LVL1050:
+ 14021              	.LFB191:
+5100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t direction = I2C_GENERATE_START_WRITE;
+ 14022              		.loc 1 5100 1 is_stmt 1 view -0
+ 14023              		.cfi_startproc
+ 14024              		@ args = 0, pretend = 0, frame = 0
+ 14025              		@ frame_needed = 0, uses_anonymous_args = 0
+5101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 14026              		.loc 1 5101 3 view .LVU4800
+5102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14027              		.loc 1 5102 3 view .LVU4801
+5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14028              		.loc 1 5105 3 view .LVU4802
+5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14029              		.loc 1 5105 3 view .LVU4803
+ 14030 0000 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 14031 0004 012B     		cmp	r3, #1
+ 14032 0006 00F0D580 		beq	.L913
+5100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t direction = I2C_GENERATE_START_WRITE;
+ 14033              		.loc 1 5100 1 is_stmt 0 discriminator 2 view .LVU4804
+ 14034 000a 70B5     		push	{r4, r5, r6, lr}
+ 14035              	.LCFI148:
+ 14036              		.cfi_def_cfa_offset 16
+ 14037              		.cfi_offset 4, -16
+ 14038              		.cfi_offset 5, -12
+ 14039              		.cfi_offset 6, -8
+ 14040              		.cfi_offset 14, -4
+ 14041 000c 82B0     		sub	sp, sp, #8
+ 14042              	.LCFI149:
+ 14043              		.cfi_def_cfa_offset 24
+ 14044 000e 0446     		mov	r4, r0
+ 14045 0010 0D46     		mov	r5, r1
+ 14046 0012 1646     		mov	r6, r2
+5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14047              		.loc 1 5105 3 is_stmt 1 discriminator 2 view .LVU4805
+ 14048 0014 0123     		movs	r3, #1
+ 14049 0016 80F84030 		strb	r3, [r0, #64]
+5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14050              		.loc 1 5105 3 discriminator 2 view .LVU4806
+5107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 14051              		.loc 1 5107 3 discriminator 2 view .LVU4807
+5107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 14052              		.loc 1 5107 6 is_stmt 0 discriminator 2 view .LVU4808
+ 14053 001a 11F0100F 		tst	r1, #16
+ 14054 001e 02D0     		beq	.L898
+5107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 14055              		.loc 1 5107 58 discriminator 1 view .LVU4809
+ 14056 0020 12F0100F 		tst	r2, #16
+ 14057 0024 22D1     		bne	.L919
+ARM GAS  /tmp/ccVyGVF6.s 			page 460
+
+
+ 14058              	.L898:
+5121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 14059              		.loc 1 5121 8 is_stmt 1 view .LVU4810
+5121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 14060              		.loc 1 5121 11 is_stmt 0 view .LVU4811
+ 14061 0026 15F0040F 		tst	r5, #4
+ 14062 002a 29D0     		beq	.L900
+5121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 14063              		.loc 1 5121 65 discriminator 1 view .LVU4812
+ 14064 002c 16F0040F 		tst	r6, #4
+ 14065 0030 26D0     		beq	.L900
+5125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14066              		.loc 1 5125 5 is_stmt 1 view .LVU4813
+5125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14067              		.loc 1 5125 16 is_stmt 0 view .LVU4814
+ 14068 0032 25F00405 		bic	r5, r5, #4
+ 14069              	.LVL1051:
+5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14070              		.loc 1 5128 5 is_stmt 1 view .LVU4815
+5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14071              		.loc 1 5128 36 is_stmt 0 view .LVU4816
+ 14072 0036 2368     		ldr	r3, [r4]
+5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14073              		.loc 1 5128 46 view .LVU4817
+ 14074 0038 5A6A     		ldr	r2, [r3, #36]
+ 14075              	.LVL1052:
+5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14076              		.loc 1 5128 10 view .LVU4818
+ 14077 003a 636A     		ldr	r3, [r4, #36]
+5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14078              		.loc 1 5128 21 view .LVU4819
+ 14079 003c 1A70     		strb	r2, [r3]
+5131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14080              		.loc 1 5131 5 is_stmt 1 view .LVU4820
+5131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14081              		.loc 1 5131 9 is_stmt 0 view .LVU4821
+ 14082 003e 636A     		ldr	r3, [r4, #36]
+5131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14083              		.loc 1 5131 19 view .LVU4822
+ 14084 0040 0133     		adds	r3, r3, #1
+ 14085 0042 6362     		str	r3, [r4, #36]
+5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount--;
+ 14086              		.loc 1 5133 5 is_stmt 1 view .LVU4823
+5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount--;
+ 14087              		.loc 1 5133 9 is_stmt 0 view .LVU4824
+ 14088 0044 238D     		ldrh	r3, [r4, #40]
+5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     hi2c->XferCount--;
+ 14089              		.loc 1 5133 19 view .LVU4825
+ 14090 0046 013B     		subs	r3, r3, #1
+ 14091 0048 2385     		strh	r3, [r4, #40]	@ movhi
+5134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14092              		.loc 1 5134 5 is_stmt 1 view .LVU4826
+5134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14093              		.loc 1 5134 9 is_stmt 0 view .LVU4827
+ 14094 004a 638D     		ldrh	r3, [r4, #42]
+ 14095 004c 9BB2     		uxth	r3, r3
+5134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccVyGVF6.s 			page 461
+
+
+ 14096              		.loc 1 5134 20 view .LVU4828
+ 14097 004e 013B     		subs	r3, r3, #1
+ 14098 0050 9BB2     		uxth	r3, r3
+ 14099 0052 6385     		strh	r3, [r4, #42]	@ movhi
+ 14100              	.LVL1053:
+ 14101              	.L899:
+5234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14102              		.loc 1 5234 3 is_stmt 1 view .LVU4829
+5236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 14103              		.loc 1 5236 3 view .LVU4830
+5236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 14104              		.loc 1 5236 6 is_stmt 0 view .LVU4831
+ 14105 0054 15F0200F 		tst	r5, #32
+ 14106 0058 03D0     		beq	.L912
+5236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 14107              		.loc 1 5236 61 discriminator 1 view .LVU4832
+ 14108 005a 16F0200F 		tst	r6, #32
+ 14109 005e 40F0A480 		bne	.L920
+ 14110              	.L912:
+5244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14111              		.loc 1 5244 3 is_stmt 1 view .LVU4833
+5244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14112              		.loc 1 5244 3 view .LVU4834
+ 14113 0062 0020     		movs	r0, #0
+ 14114 0064 84F84000 		strb	r0, [r4, #64]
+5244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14115              		.loc 1 5244 3 view .LVU4835
+5246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 14116              		.loc 1 5246 3 view .LVU4836
+5247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14117              		.loc 1 5247 1 is_stmt 0 view .LVU4837
+ 14118 0068 02B0     		add	sp, sp, #8
+ 14119              	.LCFI150:
+ 14120              		.cfi_remember_state
+ 14121              		.cfi_def_cfa_offset 16
+ 14122              		@ sp needed
+ 14123 006a 70BD     		pop	{r4, r5, r6, pc}
+ 14124              	.LVL1054:
+ 14125              	.L919:
+ 14126              	.LCFI151:
+ 14127              		.cfi_restore_state
+5111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14128              		.loc 1 5111 5 is_stmt 1 view .LVU4838
+ 14129 006c 0368     		ldr	r3, [r0]
+ 14130 006e 1022     		movs	r2, #16
+ 14131              	.LVL1055:
+5111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14132              		.loc 1 5111 5 is_stmt 0 view .LVU4839
+ 14133 0070 DA61     		str	r2, [r3, #28]
+5116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14134              		.loc 1 5116 5 is_stmt 1 view .LVU4840
+5116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14135              		.loc 1 5116 21 is_stmt 0 view .LVU4841
+ 14136 0072 436C     		ldr	r3, [r0, #68]
+ 14137 0074 43F00403 		orr	r3, r3, #4
+ 14138 0078 4364     		str	r3, [r0, #68]
+5119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ARM GAS  /tmp/ccVyGVF6.s 			page 462
+
+
+ 14139              		.loc 1 5119 5 is_stmt 1 view .LVU4842
+ 14140 007a FFF7FEFF 		bl	I2C_Flush_TXDR
+ 14141              	.LVL1056:
+5119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14142              		.loc 1 5119 5 is_stmt 0 view .LVU4843
+ 14143 007e E9E7     		b	.L899
+ 14144              	.LVL1057:
+ 14145              	.L900:
+5136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 14146              		.loc 1 5136 8 is_stmt 1 view .LVU4844
+5136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 14147              		.loc 1 5136 11 is_stmt 0 view .LVU4845
+ 14148 0080 15F0020F 		tst	r5, #2
+ 14149 0084 1DD0     		beq	.L901
+5136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 14150              		.loc 1 5136 65 discriminator 1 view .LVU4846
+ 14151 0086 16F0020F 		tst	r6, #2
+ 14152 008a 1AD0     		beq	.L901
+5139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14153              		.loc 1 5139 5 is_stmt 1 view .LVU4847
+5139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14154              		.loc 1 5139 13 is_stmt 0 view .LVU4848
+ 14155 008c 236D     		ldr	r3, [r4, #80]
+5139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14156              		.loc 1 5139 8 view .LVU4849
+ 14157 008e B3F1FF3F 		cmp	r3, #-1
+ 14158 0092 06D0     		beq	.L921
+5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14159              		.loc 1 5153 7 is_stmt 1 view .LVU4850
+5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14160              		.loc 1 5153 11 is_stmt 0 view .LVU4851
+ 14161 0094 2368     		ldr	r3, [r4]
+5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14162              		.loc 1 5153 34 view .LVU4852
+ 14163 0096 226D     		ldr	r2, [r4, #80]
+ 14164              	.LVL1058:
+5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14165              		.loc 1 5153 28 view .LVU4853
+ 14166 0098 9A62     		str	r2, [r3, #40]
+5156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 14167              		.loc 1 5156 7 is_stmt 1 view .LVU4854
+5156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 14168              		.loc 1 5156 24 is_stmt 0 view .LVU4855
+ 14169 009a 4FF0FF33 		mov	r3, #-1
+ 14170 009e 2365     		str	r3, [r4, #80]
+ 14171 00a0 D8E7     		b	.L899
+ 14172              	.LVL1059:
+ 14173              	.L921:
+5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14174              		.loc 1 5142 7 is_stmt 1 view .LVU4856
+5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14175              		.loc 1 5142 35 is_stmt 0 view .LVU4857
+ 14176 00a2 626A     		ldr	r2, [r4, #36]
+ 14177              	.LVL1060:
+5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14178              		.loc 1 5142 11 view .LVU4858
+ 14179 00a4 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/ccVyGVF6.s 			page 463
+
+
+5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14180              		.loc 1 5142 30 view .LVU4859
+ 14181 00a6 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
+5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14182              		.loc 1 5142 28 view .LVU4860
+ 14183 00a8 9A62     		str	r2, [r3, #40]
+5145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14184              		.loc 1 5145 7 is_stmt 1 view .LVU4861
+5145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14185              		.loc 1 5145 11 is_stmt 0 view .LVU4862
+ 14186 00aa 636A     		ldr	r3, [r4, #36]
+5145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14187              		.loc 1 5145 21 view .LVU4863
+ 14188 00ac 0133     		adds	r3, r3, #1
+ 14189 00ae 6362     		str	r3, [r4, #36]
+5147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 14190              		.loc 1 5147 7 is_stmt 1 view .LVU4864
+5147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 14191              		.loc 1 5147 11 is_stmt 0 view .LVU4865
+ 14192 00b0 238D     		ldrh	r3, [r4, #40]
+5147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       hi2c->XferCount--;
+ 14193              		.loc 1 5147 21 view .LVU4866
+ 14194 00b2 013B     		subs	r3, r3, #1
+ 14195 00b4 2385     		strh	r3, [r4, #40]	@ movhi
+5148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 14196              		.loc 1 5148 7 is_stmt 1 view .LVU4867
+5148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 14197              		.loc 1 5148 11 is_stmt 0 view .LVU4868
+ 14198 00b6 638D     		ldrh	r3, [r4, #42]
+ 14199 00b8 9BB2     		uxth	r3, r3
+5148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 14200              		.loc 1 5148 22 view .LVU4869
+ 14201 00ba 013B     		subs	r3, r3, #1
+ 14202 00bc 9BB2     		uxth	r3, r3
+ 14203 00be 6385     		strh	r3, [r4, #42]	@ movhi
+ 14204 00c0 C8E7     		b	.L899
+ 14205              	.LVL1061:
+ 14206              	.L901:
+5159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 14207              		.loc 1 5159 8 is_stmt 1 view .LVU4870
+5159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 14208              		.loc 1 5159 11 is_stmt 0 view .LVU4871
+ 14209 00c2 15F0800F 		tst	r5, #128
+ 14210 00c6 34D0     		beq	.L903
+5159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 14211              		.loc 1 5159 64 discriminator 1 view .LVU4872
+ 14212 00c8 16F0400F 		tst	r6, #64
+ 14213 00cc 31D0     		beq	.L903
+5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14214              		.loc 1 5162 5 is_stmt 1 view .LVU4873
+5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14215              		.loc 1 5162 14 is_stmt 0 view .LVU4874
+ 14216 00ce 638D     		ldrh	r3, [r4, #42]
+ 14217 00d0 9BB2     		uxth	r3, r3
+5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14218              		.loc 1 5162 8 view .LVU4875
+ 14219 00d2 4BB3     		cbz	r3, .L904
+ARM GAS  /tmp/ccVyGVF6.s 			page 464
+
+
+5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14220              		.loc 1 5162 41 discriminator 1 view .LVU4876
+ 14221 00d4 238D     		ldrh	r3, [r4, #40]
+5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14222              		.loc 1 5162 33 discriminator 1 view .LVU4877
+ 14223 00d6 3BBB     		cbnz	r3, .L904
+5164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 14224              		.loc 1 5164 7 is_stmt 1 view .LVU4878
+5164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 14225              		.loc 1 5164 15 is_stmt 0 view .LVU4879
+ 14226 00d8 638D     		ldrh	r3, [r4, #42]
+ 14227 00da 9BB2     		uxth	r3, r3
+5164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 14228              		.loc 1 5164 10 view .LVU4880
+ 14229 00dc FF2B     		cmp	r3, #255
+ 14230 00de 15D9     		bls	.L905
+5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 14231              		.loc 1 5167 9 is_stmt 1 view .LVU4881
+5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 14232              		.loc 1 5167 13 is_stmt 0 view .LVU4882
+ 14233 00e0 2368     		ldr	r3, [r4]
+ 14234 00e2 9B69     		ldr	r3, [r3, #24]
+5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         {
+ 14235              		.loc 1 5167 12 view .LVU4883
+ 14236 00e4 13F4803F 		tst	r3, #65536
+ 14237 00e8 0DD0     		beq	.L906
+5169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 14238              		.loc 1 5169 11 is_stmt 1 view .LVU4884
+5169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 14239              		.loc 1 5169 26 is_stmt 0 view .LVU4885
+ 14240 00ea 0123     		movs	r3, #1
+ 14241 00ec 2385     		strh	r3, [r4, #40]	@ movhi
+ 14242              	.L907:
+5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ 14243              		.loc 1 5175 9 is_stmt 1 view .LVU4886
+5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ 14244              		.loc 1 5175 48 is_stmt 0 view .LVU4887
+ 14245 00ee E16C     		ldr	r1, [r4, #76]
+ 14246              	.LVL1062:
+5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ 14247              		.loc 1 5175 9 view .LVU4888
+ 14248 00f0 0023     		movs	r3, #0
+ 14249 00f2 0093     		str	r3, [sp]
+ 14250 00f4 4FF08073 		mov	r3, #16777216
+ 14251 00f8 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 14252              	.LVL1063:
+5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ 14253              		.loc 1 5175 9 view .LVU4889
+ 14254 00fc 89B2     		uxth	r1, r1
+ 14255 00fe 2046     		mov	r0, r4
+ 14256              	.LVL1064:
+5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ 14257              		.loc 1 5175 9 view .LVU4890
+ 14258 0100 FFF7FEFF 		bl	I2C_TransferConfig
+ 14259              	.LVL1065:
+ 14260 0104 A6E7     		b	.L899
+ 14261              	.LVL1066:
+ARM GAS  /tmp/ccVyGVF6.s 			page 465
+
+
+ 14262              	.L906:
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 14263              		.loc 1 5173 11 is_stmt 1 view .LVU4891
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         }
+ 14264              		.loc 1 5173 26 is_stmt 0 view .LVU4892
+ 14265 0106 FF23     		movs	r3, #255
+ 14266 0108 2385     		strh	r3, [r4, #40]	@ movhi
+ 14267 010a F0E7     		b	.L907
+ 14268              	.L905:
+5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ 14269              		.loc 1 5180 9 is_stmt 1 view .LVU4893
+5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ 14270              		.loc 1 5180 30 is_stmt 0 view .LVU4894
+ 14271 010c 628D     		ldrh	r2, [r4, #42]
+ 14272              	.LVL1067:
+5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ 14273              		.loc 1 5180 30 view .LVU4895
+ 14274 010e 92B2     		uxth	r2, r2
+5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****         I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ 14275              		.loc 1 5180 24 view .LVU4896
+ 14276 0110 2285     		strh	r2, [r4, #40]	@ movhi
+5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ 14277              		.loc 1 5181 9 is_stmt 1 view .LVU4897
+5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ 14278              		.loc 1 5181 48 is_stmt 0 view .LVU4898
+ 14279 0112 E16C     		ldr	r1, [r4, #76]
+ 14280              	.LVL1068:
+5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ 14281              		.loc 1 5181 9 view .LVU4899
+ 14282 0114 0023     		movs	r3, #0
+ 14283 0116 0093     		str	r3, [sp]
+ 14284 0118 4FF00073 		mov	r3, #33554432
+ 14285 011c D2B2     		uxtb	r2, r2
+ 14286 011e 89B2     		uxth	r1, r1
+ 14287 0120 2046     		mov	r0, r4
+ 14288              	.LVL1069:
+5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                            I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ 14289              		.loc 1 5181 9 view .LVU4900
+ 14290 0122 FFF7FEFF 		bl	I2C_TransferConfig
+ 14291              	.LVL1070:
+ 14292 0126 95E7     		b	.L899
+ 14293              	.LVL1071:
+ 14294              	.L904:
+5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 14295              		.loc 1 5189 7 is_stmt 1 view .LVU4901
+ 14296 0128 4021     		movs	r1, #64
+ 14297              	.LVL1072:
+5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 14298              		.loc 1 5189 7 is_stmt 0 view .LVU4902
+ 14299 012a 2046     		mov	r0, r4
+ 14300              	.LVL1073:
+5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 14301              		.loc 1 5189 7 view .LVU4903
+ 14302 012c FFF7FEFF 		bl	I2C_ITError
+ 14303              	.LVL1074:
+5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 14304              		.loc 1 5189 7 view .LVU4904
+ARM GAS  /tmp/ccVyGVF6.s 			page 466
+
+
+ 14305 0130 90E7     		b	.L899
+ 14306              	.LVL1075:
+ 14307              	.L903:
+5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 14308              		.loc 1 5192 8 is_stmt 1 view .LVU4905
+5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 14309              		.loc 1 5192 11 is_stmt 0 view .LVU4906
+ 14310 0132 15F0400F 		tst	r5, #64
+ 14311 0136 8DD0     		beq	.L899
+5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ 14312              		.loc 1 5192 63 discriminator 1 view .LVU4907
+ 14313 0138 16F0400F 		tst	r6, #64
+ 14314 013c 8AD0     		beq	.L899
+5196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14315              		.loc 1 5196 5 is_stmt 1 view .LVU4908
+ 14316 013e 0121     		movs	r1, #1
+ 14317              	.LVL1076:
+5196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14318              		.loc 1 5196 5 is_stmt 0 view .LVU4909
+ 14319 0140 2046     		mov	r0, r4
+ 14320              	.LVL1077:
+5196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14321              		.loc 1 5196 5 view .LVU4910
+ 14322 0142 FFF7FEFF 		bl	I2C_Disable_IRQ
+ 14323              	.LVL1078:
+5199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14324              		.loc 1 5199 5 is_stmt 1 view .LVU4911
+ 14325 0146 0221     		movs	r1, #2
+ 14326 0148 2046     		mov	r0, r4
+ 14327 014a FFF7FEFF 		bl	I2C_Enable_IRQ
+ 14328              	.LVL1079:
+5201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14329              		.loc 1 5201 5 view .LVU4912
+5201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14330              		.loc 1 5201 13 is_stmt 0 view .LVU4913
+ 14331 014e 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 14332 0152 DBB2     		uxtb	r3, r3
+5201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14333              		.loc 1 5201 8 view .LVU4914
+ 14334 0154 222B     		cmp	r3, #34
+ 14335 0156 16D0     		beq	.L914
+5101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmpITFlags = ITFlags;
+ 14336              		.loc 1 5101 12 view .LVU4915
+ 14337 0158 1748     		ldr	r0, .L922
+ 14338              	.L908:
+ 14339              	.LVL1080:
+5206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14340              		.loc 1 5206 5 is_stmt 1 view .LVU4916
+5206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14341              		.loc 1 5206 13 is_stmt 0 view .LVU4917
+ 14342 015a 638D     		ldrh	r3, [r4, #42]
+ 14343 015c 9BB2     		uxth	r3, r3
+5206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     {
+ 14344              		.loc 1 5206 8 view .LVU4918
+ 14345 015e FF2B     		cmp	r3, #255
+ 14346 0160 16D9     		bls	.L909
+5209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ARM GAS  /tmp/ccVyGVF6.s 			page 467
+
+
+ 14347              		.loc 1 5209 7 is_stmt 1 view .LVU4919
+5209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 14348              		.loc 1 5209 11 is_stmt 0 view .LVU4920
+ 14349 0162 2368     		ldr	r3, [r4]
+ 14350 0164 9B69     		ldr	r3, [r3, #24]
+5209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       {
+ 14351              		.loc 1 5209 10 view .LVU4921
+ 14352 0166 13F4803F 		tst	r3, #65536
+ 14353 016a 0ED0     		beq	.L910
+5211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 14354              		.loc 1 5211 9 is_stmt 1 view .LVU4922
+5211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 14355              		.loc 1 5211 24 is_stmt 0 view .LVU4923
+ 14356 016c 0123     		movs	r3, #1
+ 14357 016e 2385     		strh	r3, [r4, #40]	@ movhi
+ 14358              	.L911:
+5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_RELOAD_MODE, direction);
+ 14359              		.loc 1 5219 7 is_stmt 1 view .LVU4924
+5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_RELOAD_MODE, direction);
+ 14360              		.loc 1 5219 46 is_stmt 0 view .LVU4925
+ 14361 0170 E16C     		ldr	r1, [r4, #76]
+5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_RELOAD_MODE, direction);
+ 14362              		.loc 1 5219 7 view .LVU4926
+ 14363 0172 0090     		str	r0, [sp]
+ 14364 0174 4FF08073 		mov	r3, #16777216
+ 14365 0178 94F82820 		ldrb	r2, [r4, #40]	@ zero_extendqisi2
+ 14366 017c 89B2     		uxth	r1, r1
+ 14367 017e 2046     		mov	r0, r4
+ 14368              	.LVL1081:
+5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_RELOAD_MODE, direction);
+ 14369              		.loc 1 5219 7 view .LVU4927
+ 14370 0180 FFF7FEFF 		bl	I2C_TransferConfig
+ 14371              	.LVL1082:
+5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_RELOAD_MODE, direction);
+ 14372              		.loc 1 5219 7 view .LVU4928
+ 14373 0184 66E7     		b	.L899
+ 14374              	.LVL1083:
+ 14375              	.L914:
+5203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****     }
+ 14376              		.loc 1 5203 17 view .LVU4929
+ 14377 0186 0D48     		ldr	r0, .L922+4
+ 14378 0188 E7E7     		b	.L908
+ 14379              	.LVL1084:
+ 14380              	.L910:
+5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 14381              		.loc 1 5215 9 is_stmt 1 view .LVU4930
+5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       }
+ 14382              		.loc 1 5215 24 is_stmt 0 view .LVU4931
+ 14383 018a FF23     		movs	r3, #255
+ 14384 018c 2385     		strh	r3, [r4, #40]	@ movhi
+ 14385 018e EFE7     		b	.L911
+ 14386              	.L909:
+5224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14387              		.loc 1 5224 7 is_stmt 1 view .LVU4932
+5224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14388              		.loc 1 5224 28 is_stmt 0 view .LVU4933
+ 14389 0190 628D     		ldrh	r2, [r4, #42]
+ARM GAS  /tmp/ccVyGVF6.s 			page 468
+
+
+ 14390 0192 92B2     		uxth	r2, r2
+5224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14391              		.loc 1 5224 22 view .LVU4934
+ 14392 0194 2285     		strh	r2, [r4, #40]	@ movhi
+5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+ 14393              		.loc 1 5227 7 is_stmt 1 view .LVU4935
+5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+ 14394              		.loc 1 5227 46 is_stmt 0 view .LVU4936
+ 14395 0196 E16C     		ldr	r1, [r4, #76]
+5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+ 14396              		.loc 1 5227 7 view .LVU4937
+ 14397 0198 0090     		str	r0, [sp]
+ 14398 019a 4FF00073 		mov	r3, #33554432
+ 14399 019e D2B2     		uxtb	r2, r2
+ 14400 01a0 89B2     		uxth	r1, r1
+ 14401 01a2 2046     		mov	r0, r4
+ 14402              	.LVL1085:
+5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+ 14403              		.loc 1 5227 7 view .LVU4938
+ 14404 01a4 FFF7FEFF 		bl	I2C_TransferConfig
+ 14405              	.LVL1086:
+5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****                          I2C_AUTOEND_MODE, direction);
+ 14406              		.loc 1 5227 7 view .LVU4939
+ 14407 01a8 54E7     		b	.L899
+ 14408              	.LVL1087:
+ 14409              	.L920:
+5240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14410              		.loc 1 5240 5 is_stmt 1 view .LVU4940
+ 14411 01aa 2946     		mov	r1, r5
+ 14412 01ac 2046     		mov	r0, r4
+ 14413 01ae FFF7FEFF 		bl	I2C_ITMasterCplt
+ 14414              	.LVL1088:
+ 14415 01b2 56E7     		b	.L912
+ 14416              	.LVL1089:
+ 14417              	.L913:
+ 14418              	.LCFI152:
+ 14419              		.cfi_def_cfa_offset 0
+ 14420              		.cfi_restore 4
+ 14421              		.cfi_restore 5
+ 14422              		.cfi_restore 6
+ 14423              		.cfi_restore 14
+5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14424              		.loc 1 5105 3 is_stmt 0 view .LVU4941
+ 14425 01b4 0220     		movs	r0, #2
+ 14426              	.LVL1090:
+5247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14427              		.loc 1 5247 1 view .LVU4942
+ 14428 01b6 7047     		bx	lr
+ 14429              	.L923:
+ 14430              		.align	2
+ 14431              	.L922:
+ 14432 01b8 00200080 		.word	-2147475456
+ 14433 01bc 00240080 		.word	-2147474432
+ 14434              		.cfi_endproc
+ 14435              	.LFE191:
+ 14437              		.section	.text.HAL_I2C_ER_IRQHandler,"ax",%progbits
+ 14438              		.align	1
+ARM GAS  /tmp/ccVyGVF6.s 			page 469
+
+
+ 14439              		.global	HAL_I2C_ER_IRQHandler
+ 14440              		.syntax unified
+ 14441              		.thumb
+ 14442              		.thumb_func
+ 14443              		.fpu fpv5-d16
+ 14445              	HAL_I2C_ER_IRQHandler:
+ 14446              	.LVL1091:
+ 14447              	.LFB176:
+4658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+ 14448              		.loc 1 4658 1 is_stmt 1 view -0
+ 14449              		.cfi_startproc
+ 14450              		@ args = 0, pretend = 0, frame = 0
+ 14451              		@ frame_needed = 0, uses_anonymous_args = 0
+4658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+ 14452              		.loc 1 4658 1 is_stmt 0 view .LVU4944
+ 14453 0000 10B5     		push	{r4, lr}
+ 14454              	.LCFI153:
+ 14455              		.cfi_def_cfa_offset 8
+ 14456              		.cfi_offset 4, -8
+ 14457              		.cfi_offset 14, -4
+4659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 14458              		.loc 1 4659 3 is_stmt 1 view .LVU4945
+4659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 14459              		.loc 1 4659 24 is_stmt 0 view .LVU4946
+ 14460 0002 0268     		ldr	r2, [r0]
+4659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 14461              		.loc 1 4659 12 view .LVU4947
+ 14462 0004 9369     		ldr	r3, [r2, #24]
+ 14463              	.LVL1092:
+4660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmperror;
+ 14464              		.loc 1 4660 3 is_stmt 1 view .LVU4948
+4660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   uint32_t tmperror;
+ 14465              		.loc 1 4660 12 is_stmt 0 view .LVU4949
+ 14466 0006 1168     		ldr	r1, [r2]
+ 14467              	.LVL1093:
+4661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14468              		.loc 1 4661 3 is_stmt 1 view .LVU4950
+4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 14469              		.loc 1 4664 3 view .LVU4951
+4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 14470              		.loc 1 4664 6 is_stmt 0 view .LVU4952
+ 14471 0008 13F4807F 		tst	r3, #256
+ 14472 000c 09D0     		beq	.L925
+4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 14473              		.loc 1 4664 57 discriminator 1 view .LVU4953
+ 14474 000e 11F0800F 		tst	r1, #128
+ 14475 0012 06D0     		beq	.L925
+4667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14476              		.loc 1 4667 5 is_stmt 1 view .LVU4954
+4667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14477              		.loc 1 4667 21 is_stmt 0 view .LVU4955
+ 14478 0014 446C     		ldr	r4, [r0, #68]
+ 14479 0016 44F00104 		orr	r4, r4, #1
+ 14480 001a 4464     		str	r4, [r0, #68]
+4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14481              		.loc 1 4670 5 is_stmt 1 view .LVU4956
+ 14482 001c 4FF48074 		mov	r4, #256
+ARM GAS  /tmp/ccVyGVF6.s 			page 470
+
+
+ 14483 0020 D461     		str	r4, [r2, #28]
+ 14484              	.L925:
+4674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 14485              		.loc 1 4674 3 view .LVU4957
+4674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 14486              		.loc 1 4674 6 is_stmt 0 view .LVU4958
+ 14487 0022 13F4806F 		tst	r3, #1024
+ 14488 0026 0AD0     		beq	.L926
+4674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 14489              		.loc 1 4674 56 discriminator 1 view .LVU4959
+ 14490 0028 11F0800F 		tst	r1, #128
+ 14491 002c 07D0     		beq	.L926
+4677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14492              		.loc 1 4677 5 is_stmt 1 view .LVU4960
+4677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14493              		.loc 1 4677 21 is_stmt 0 view .LVU4961
+ 14494 002e 426C     		ldr	r2, [r0, #68]
+ 14495 0030 42F00802 		orr	r2, r2, #8
+ 14496 0034 4264     		str	r2, [r0, #68]
+4680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14497              		.loc 1 4680 5 is_stmt 1 view .LVU4962
+ 14498 0036 0268     		ldr	r2, [r0]
+ 14499 0038 4FF48064 		mov	r4, #1024
+ 14500 003c D461     		str	r4, [r2, #28]
+ 14501              	.L926:
+4684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 14502              		.loc 1 4684 3 view .LVU4963
+4684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 14503              		.loc 1 4684 6 is_stmt 0 view .LVU4964
+ 14504 003e 13F4007F 		tst	r3, #512
+ 14505 0042 0AD0     		beq	.L927
+4684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****       (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 14506              		.loc 1 4684 57 discriminator 1 view .LVU4965
+ 14507 0044 11F0800F 		tst	r1, #128
+ 14508 0048 07D0     		beq	.L927
+4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14509              		.loc 1 4687 5 is_stmt 1 view .LVU4966
+4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14510              		.loc 1 4687 21 is_stmt 0 view .LVU4967
+ 14511 004a 436C     		ldr	r3, [r0, #68]
+ 14512              	.LVL1094:
+4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14513              		.loc 1 4687 21 view .LVU4968
+ 14514 004c 43F00203 		orr	r3, r3, #2
+ 14515 0050 4364     		str	r3, [r0, #68]
+4690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14516              		.loc 1 4690 5 is_stmt 1 view .LVU4969
+ 14517 0052 0368     		ldr	r3, [r0]
+ 14518 0054 4FF40072 		mov	r2, #512
+ 14519 0058 DA61     		str	r2, [r3, #28]
+ 14520              	.L927:
+4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14521              		.loc 1 4694 3 view .LVU4970
+4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14522              		.loc 1 4694 12 is_stmt 0 view .LVU4971
+ 14523 005a 416C     		ldr	r1, [r0, #68]
+ 14524              	.LVL1095:
+ARM GAS  /tmp/ccVyGVF6.s 			page 471
+
+
+4697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 14525              		.loc 1 4697 3 is_stmt 1 view .LVU4972
+4697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 14526              		.loc 1 4697 6 is_stmt 0 view .LVU4973
+ 14527 005c 11F00B0F 		tst	r1, #11
+ 14528 0060 00D1     		bne	.L930
+ 14529              	.LVL1096:
+ 14530              	.L924:
+4701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14531              		.loc 1 4701 1 view .LVU4974
+ 14532 0062 10BD     		pop	{r4, pc}
+ 14533              	.LVL1097:
+ 14534              	.L930:
+4699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14535              		.loc 1 4699 5 is_stmt 1 view .LVU4975
+ 14536 0064 FFF7FEFF 		bl	I2C_ITError
+ 14537              	.LVL1098:
+4701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14538              		.loc 1 4701 1 is_stmt 0 view .LVU4976
+ 14539 0068 FBE7     		b	.L924
+ 14540              		.cfi_endproc
+ 14541              	.LFE176:
+ 14543              		.section	.text.I2C_DMAAbort,"ax",%progbits
+ 14544              		.align	1
+ 14545              		.syntax unified
+ 14546              		.thumb
+ 14547              		.thumb_func
+ 14548              		.fpu fpv5-d16
+ 14550              	I2C_DMAAbort:
+ 14551              	.LVL1099:
+ 14552              	.LFB212:
+6988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 14553              		.loc 1 6988 1 is_stmt 1 view -0
+ 14554              		.cfi_startproc
+ 14555              		@ args = 0, pretend = 0, frame = 0
+ 14556              		@ frame_needed = 0, uses_anonymous_args = 0
+6988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Derogation MISRAC2012-Rule-11.5 */
+ 14557              		.loc 1 6988 1 is_stmt 0 view .LVU4978
+ 14558 0000 08B5     		push	{r3, lr}
+ 14559              	.LCFI154:
+ 14560              		.cfi_def_cfa_offset 8
+ 14561              		.cfi_offset 3, -8
+ 14562              		.cfi_offset 14, -4
+6990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14563              		.loc 1 6990 3 is_stmt 1 view .LVU4979
+6990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14564              		.loc 1 6990 22 is_stmt 0 view .LVU4980
+ 14565 0002 806B     		ldr	r0, [r0, #56]
+ 14566              	.LVL1100:
+6993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 14567              		.loc 1 6993 3 is_stmt 1 view .LVU4981
+6993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 14568              		.loc 1 6993 11 is_stmt 0 view .LVU4982
+ 14569 0004 836B     		ldr	r3, [r0, #56]
+6993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 14570              		.loc 1 6993 6 view .LVU4983
+ 14571 0006 0BB1     		cbz	r3, .L932
+ARM GAS  /tmp/ccVyGVF6.s 			page 472
+
+
+6995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14572              		.loc 1 6995 5 is_stmt 1 view .LVU4984
+6995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14573              		.loc 1 6995 37 is_stmt 0 view .LVU4985
+ 14574 0008 0022     		movs	r2, #0
+ 14575 000a 1A65     		str	r2, [r3, #80]
+ 14576              	.L932:
+6997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 14577              		.loc 1 6997 3 is_stmt 1 view .LVU4986
+6997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 14578              		.loc 1 6997 11 is_stmt 0 view .LVU4987
+ 14579 000c C36B     		ldr	r3, [r0, #60]
+6997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   {
+ 14580              		.loc 1 6997 6 view .LVU4988
+ 14581 000e 0BB1     		cbz	r3, .L933
+6999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14582              		.loc 1 6999 5 is_stmt 1 view .LVU4989
+6999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   }
+ 14583              		.loc 1 6999 37 is_stmt 0 view .LVU4990
+ 14584 0010 0022     		movs	r2, #0
+ 14585 0012 1A65     		str	r2, [r3, #80]
+ 14586              	.L933:
+7002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 14587              		.loc 1 7002 3 is_stmt 1 view .LVU4991
+ 14588 0014 FFF7FEFF 		bl	I2C_TreatErrorCallback
+ 14589              	.LVL1101:
+7003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14590              		.loc 1 7003 1 is_stmt 0 view .LVU4992
+ 14591 0018 08BD     		pop	{r3, pc}
+ 14592              		.cfi_endproc
+ 14593              	.LFE212:
+ 14595              		.section	.text.HAL_I2C_GetState,"ax",%progbits
+ 14596              		.align	1
+ 14597              		.global	HAL_I2C_GetState
+ 14598              		.syntax unified
+ 14599              		.thumb
+ 14600              		.thumb_func
+ 14601              		.fpu fpv5-d16
+ 14603              	HAL_I2C_GetState:
+ 14604              	.LVL1102:
+ 14605              	.LFB187:
+4892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   /* Return I2C handle state */
+ 14606              		.loc 1 4892 1 is_stmt 1 view -0
+ 14607              		.cfi_startproc
+ 14608              		@ args = 0, pretend = 0, frame = 0
+ 14609              		@ frame_needed = 0, uses_anonymous_args = 0
+ 14610              		@ link register save eliminated.
+4894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 14611              		.loc 1 4894 3 view .LVU4994
+4894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 14612              		.loc 1 4894 14 is_stmt 0 view .LVU4995
+ 14613 0000 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 14614              	.LVL1103:
+4895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14615              		.loc 1 4895 1 view .LVU4996
+ 14616 0004 7047     		bx	lr
+ 14617              		.cfi_endproc
+ARM GAS  /tmp/ccVyGVF6.s 			page 473
+
+
+ 14618              	.LFE187:
+ 14620              		.section	.text.HAL_I2C_GetMode,"ax",%progbits
+ 14621              		.align	1
+ 14622              		.global	HAL_I2C_GetMode
+ 14623              		.syntax unified
+ 14624              		.thumb
+ 14625              		.thumb_func
+ 14626              		.fpu fpv5-d16
+ 14628              	HAL_I2C_GetMode:
+ 14629              	.LVL1104:
+ 14630              	.LFB188:
+4904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return hi2c->Mode;
+ 14631              		.loc 1 4904 1 is_stmt 1 view -0
+ 14632              		.cfi_startproc
+ 14633              		@ args = 0, pretend = 0, frame = 0
+ 14634              		@ frame_needed = 0, uses_anonymous_args = 0
+ 14635              		@ link register save eliminated.
+4905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 14636              		.loc 1 4905 3 view .LVU4998
+4905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 14637              		.loc 1 4905 14 is_stmt 0 view .LVU4999
+ 14638 0000 90F84200 		ldrb	r0, [r0, #66]	@ zero_extendqisi2
+ 14639              	.LVL1105:
+4906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14640              		.loc 1 4906 1 view .LVU5000
+ 14641 0004 7047     		bx	lr
+ 14642              		.cfi_endproc
+ 14643              	.LFE188:
+ 14645              		.section	.text.HAL_I2C_GetError,"ax",%progbits
+ 14646              		.align	1
+ 14647              		.global	HAL_I2C_GetError
+ 14648              		.syntax unified
+ 14649              		.thumb
+ 14650              		.thumb_func
+ 14651              		.fpu fpv5-d16
+ 14653              	HAL_I2C_GetError:
+ 14654              	.LVL1106:
+ 14655              	.LFB189:
+4915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c ****   return hi2c->ErrorCode;
+ 14656              		.loc 1 4915 1 is_stmt 1 view -0
+ 14657              		.cfi_startproc
+ 14658              		@ args = 0, pretend = 0, frame = 0
+ 14659              		@ frame_needed = 0, uses_anonymous_args = 0
+ 14660              		@ link register save eliminated.
+4916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 14661              		.loc 1 4916 3 view .LVU5002
+4916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** }
+ 14662              		.loc 1 4916 14 is_stmt 0 view .LVU5003
+ 14663 0000 406C     		ldr	r0, [r0, #68]
+ 14664              	.LVL1107:
+4917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** 
+ 14665              		.loc 1 4917 1 view .LVU5004
+ 14666 0002 7047     		bx	lr
+ 14667              		.cfi_endproc
+ 14668              	.LFE189:
+ 14670              		.text
+ 14671              	.Letext0:
+ARM GAS  /tmp/ccVyGVF6.s 			page 474
+
+
+ 14672              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 14673              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 14674              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 14675              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 14676              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 14677              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h"
+ 14678              		.file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ARM GAS  /tmp/ccVyGVF6.s 			page 475
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_i2c.c
+     /tmp/ccVyGVF6.s:17     .text.I2C_Flush_TXDR:0000000000000000 $t
+     /tmp/ccVyGVF6.s:24     .text.I2C_Flush_TXDR:0000000000000000 I2C_Flush_TXDR
+     /tmp/ccVyGVF6.s:63     .text.I2C_TransferConfig:0000000000000000 $t
+     /tmp/ccVyGVF6.s:69     .text.I2C_TransferConfig:0000000000000000 I2C_TransferConfig
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+     /tmp/ccVyGVF6.s:135    .text.I2C_Enable_IRQ:0000000000000000 I2C_Enable_IRQ
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+     /tmp/ccVyGVF6.s:13370  .text.I2C_Master_ISR_DMA:0000000000000000 I2C_Master_ISR_DMA
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+     /tmp/ccVyGVF6.s:12668  .text.I2C_Mem_ISR_DMA:0000000000000000 I2C_Mem_ISR_DMA
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+     /tmp/ccVyGVF6.s:310    .text.I2C_Disable_IRQ:0000000000000000 I2C_Disable_IRQ
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+     /tmp/ccVyGVF6.s:440    .text.I2C_ConvertOtherXferOptions:0000000000000000 I2C_ConvertOtherXferOptions
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+     /tmp/ccVyGVF6.s:877    .text.I2C_WaitOnFlagUntilTimeout:0000000000000000 I2C_WaitOnFlagUntilTimeout
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+     /tmp/ccVyGVF6.s:992    .text.I2C_RequestMemoryWrite:0000000000000000 I2C_RequestMemoryWrite
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+     /tmp/ccVyGVF6.s:1116   .text.I2C_RequestMemoryRead:0000000000000000 $t
+     /tmp/ccVyGVF6.s:1122   .text.I2C_RequestMemoryRead:0000000000000000 I2C_RequestMemoryRead
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+     /tmp/ccVyGVF6.s:1246   .text.I2C_WaitOnSTOPFlagUntilTimeout:0000000000000000 $t
+     /tmp/ccVyGVF6.s:1252   .text.I2C_WaitOnSTOPFlagUntilTimeout:0000000000000000 I2C_WaitOnSTOPFlagUntilTimeout
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+     /tmp/ccVyGVF6.s:1355   .text.I2C_WaitOnRXNEFlagUntilTimeout:0000000000000000 I2C_WaitOnRXNEFlagUntilTimeout
+     /tmp/ccVyGVF6.s:1518   .text.HAL_I2C_MspInit:0000000000000000 $t
+     /tmp/ccVyGVF6.s:1525   .text.HAL_I2C_MspInit:0000000000000000 HAL_I2C_MspInit
+     /tmp/ccVyGVF6.s:1540   .text.HAL_I2C_Init:0000000000000000 $t
+     /tmp/ccVyGVF6.s:1547   .text.HAL_I2C_Init:0000000000000000 HAL_I2C_Init
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+     /tmp/ccVyGVF6.s:1744   .text.HAL_I2C_MspDeInit:0000000000000000 $t
+     /tmp/ccVyGVF6.s:1751   .text.HAL_I2C_MspDeInit:0000000000000000 HAL_I2C_MspDeInit
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+     /tmp/ccVyGVF6.s:1773   .text.HAL_I2C_DeInit:0000000000000000 HAL_I2C_DeInit
+     /tmp/ccVyGVF6.s:1838   .text.HAL_I2C_Master_Transmit:0000000000000000 $t
+     /tmp/ccVyGVF6.s:1845   .text.HAL_I2C_Master_Transmit:0000000000000000 HAL_I2C_Master_Transmit
+     /tmp/ccVyGVF6.s:2203   .text.HAL_I2C_Master_Transmit:00000000000001a0 $d
+     /tmp/ccVyGVF6.s:2208   .text.HAL_I2C_Master_Receive:0000000000000000 $t
+     /tmp/ccVyGVF6.s:2215   .text.HAL_I2C_Master_Receive:0000000000000000 HAL_I2C_Master_Receive
+     /tmp/ccVyGVF6.s:2524   .text.HAL_I2C_Master_Receive:0000000000000178 $d
+     /tmp/ccVyGVF6.s:2529   .text.HAL_I2C_Slave_Transmit:0000000000000000 $t
+     /tmp/ccVyGVF6.s:2536   .text.HAL_I2C_Slave_Transmit:0000000000000000 HAL_I2C_Slave_Transmit
+     /tmp/ccVyGVF6.s:2980   .text.HAL_I2C_Slave_Receive:0000000000000000 $t
+     /tmp/ccVyGVF6.s:2987   .text.HAL_I2C_Slave_Receive:0000000000000000 HAL_I2C_Slave_Receive
+     /tmp/ccVyGVF6.s:3331   .text.HAL_I2C_Master_Transmit_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:3338   .text.HAL_I2C_Master_Transmit_IT:0000000000000000 HAL_I2C_Master_Transmit_IT
+     /tmp/ccVyGVF6.s:3536   .text.HAL_I2C_Master_Transmit_IT:00000000000000bc $d
+     /tmp/ccVyGVF6.s:12266  .text.I2C_Master_ISR_IT:0000000000000000 I2C_Master_ISR_IT
+     /tmp/ccVyGVF6.s:3543   .text.HAL_I2C_Master_Receive_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:3550   .text.HAL_I2C_Master_Receive_IT:0000000000000000 HAL_I2C_Master_Receive_IT
+ARM GAS  /tmp/ccVyGVF6.s 			page 476
+
+
+     /tmp/ccVyGVF6.s:3702   .text.HAL_I2C_Master_Receive_IT:000000000000008c $d
+     /tmp/ccVyGVF6.s:3709   .text.HAL_I2C_Slave_Transmit_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:3716   .text.HAL_I2C_Slave_Transmit_IT:0000000000000000 HAL_I2C_Slave_Transmit_IT
+     /tmp/ccVyGVF6.s:3859   .text.HAL_I2C_Slave_Transmit_IT:0000000000000084 $d
+     /tmp/ccVyGVF6.s:11675  .text.I2C_Slave_ISR_IT:0000000000000000 I2C_Slave_ISR_IT
+     /tmp/ccVyGVF6.s:3865   .text.HAL_I2C_Slave_Receive_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:3872   .text.HAL_I2C_Slave_Receive_IT:0000000000000000 HAL_I2C_Slave_Receive_IT
+     /tmp/ccVyGVF6.s:3974   .text.HAL_I2C_Slave_Receive_IT:000000000000005c $d
+     /tmp/ccVyGVF6.s:3980   .text.HAL_I2C_Master_Transmit_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:3987   .text.HAL_I2C_Master_Transmit_DMA:0000000000000000 HAL_I2C_Master_Transmit_DMA
+     /tmp/ccVyGVF6.s:4332   .text.HAL_I2C_Master_Transmit_DMA:000000000000015c $d
+     /tmp/ccVyGVF6.s:13793  .text.I2C_DMAMasterTransmitCplt:0000000000000000 I2C_DMAMasterTransmitCplt
+     /tmp/ccVyGVF6.s:13695  .text.I2C_DMAError:0000000000000000 I2C_DMAError
+     /tmp/ccVyGVF6.s:4342   .text.HAL_I2C_Master_Receive_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:4349   .text.HAL_I2C_Master_Receive_DMA:0000000000000000 HAL_I2C_Master_Receive_DMA
+     /tmp/ccVyGVF6.s:4648   .text.HAL_I2C_Master_Receive_DMA:0000000000000138 $d
+     /tmp/ccVyGVF6.s:13900  .text.I2C_DMAMasterReceiveCplt:0000000000000000 I2C_DMAMasterReceiveCplt
+     /tmp/ccVyGVF6.s:4658   .text.HAL_I2C_Slave_Transmit_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:4665   .text.HAL_I2C_Slave_Transmit_DMA:0000000000000000 HAL_I2C_Slave_Transmit_DMA
+     /tmp/ccVyGVF6.s:4965   .text.HAL_I2C_Slave_Transmit_DMA:0000000000000130 $d
+     /tmp/ccVyGVF6.s:10368  .text.I2C_DMASlaveTransmitCplt:0000000000000000 I2C_DMASlaveTransmitCplt
+     /tmp/ccVyGVF6.s:4973   .text.HAL_I2C_Slave_Receive_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:4980   .text.HAL_I2C_Slave_Receive_DMA:0000000000000000 HAL_I2C_Slave_Receive_DMA
+     /tmp/ccVyGVF6.s:5198   .text.HAL_I2C_Slave_Receive_DMA:00000000000000e4 $d
+     /tmp/ccVyGVF6.s:10426  .text.I2C_DMASlaveReceiveCplt:0000000000000000 I2C_DMASlaveReceiveCplt
+     /tmp/ccVyGVF6.s:5206   .text.HAL_I2C_Mem_Write:0000000000000000 $t
+     /tmp/ccVyGVF6.s:5213   .text.HAL_I2C_Mem_Write:0000000000000000 HAL_I2C_Mem_Write
+     /tmp/ccVyGVF6.s:5571   .text.HAL_I2C_Mem_Read:0000000000000000 $t
+     /tmp/ccVyGVF6.s:5578   .text.HAL_I2C_Mem_Read:0000000000000000 HAL_I2C_Mem_Read
+     /tmp/ccVyGVF6.s:5936   .text.HAL_I2C_Mem_Read:00000000000001ac $d
+     /tmp/ccVyGVF6.s:5941   .text.HAL_I2C_Mem_Write_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:5948   .text.HAL_I2C_Mem_Write_IT:0000000000000000 HAL_I2C_Mem_Write_IT
+     /tmp/ccVyGVF6.s:6123   .text.HAL_I2C_Mem_Write_IT:00000000000000ac $d
+     /tmp/ccVyGVF6.s:14019  .text.I2C_Mem_ISR_IT:0000000000000000 I2C_Mem_ISR_IT
+     /tmp/ccVyGVF6.s:6130   .text.HAL_I2C_Mem_Read_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:6137   .text.HAL_I2C_Mem_Read_IT:0000000000000000 HAL_I2C_Mem_Read_IT
+     /tmp/ccVyGVF6.s:6309   .text.HAL_I2C_Mem_Read_IT:00000000000000a8 $d
+     /tmp/ccVyGVF6.s:6316   .text.HAL_I2C_Mem_Write_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:6323   .text.HAL_I2C_Mem_Write_DMA:0000000000000000 HAL_I2C_Mem_Write_DMA
+     /tmp/ccVyGVF6.s:6606   .text.HAL_I2C_Mem_Write_DMA:0000000000000120 $d
+     /tmp/ccVyGVF6.s:6615   .text.HAL_I2C_Mem_Read_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:6622   .text.HAL_I2C_Mem_Read_DMA:0000000000000000 HAL_I2C_Mem_Read_DMA
+     /tmp/ccVyGVF6.s:6907   .text.HAL_I2C_Mem_Read_DMA:0000000000000120 $d
+     /tmp/ccVyGVF6.s:6916   .text.HAL_I2C_IsDeviceReady:0000000000000000 $t
+     /tmp/ccVyGVF6.s:6923   .text.HAL_I2C_IsDeviceReady:0000000000000000 HAL_I2C_IsDeviceReady
+     /tmp/ccVyGVF6.s:7213   .text.HAL_I2C_IsDeviceReady:0000000000000134 $d
+     /tmp/ccVyGVF6.s:7219   .text.HAL_I2C_Master_Seq_Transmit_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:7226   .text.HAL_I2C_Master_Seq_Transmit_IT:0000000000000000 HAL_I2C_Master_Seq_Transmit_IT
+     /tmp/ccVyGVF6.s:7491   .text.HAL_I2C_Master_Seq_Transmit_IT:0000000000000104 $d
+     /tmp/ccVyGVF6.s:7497   .text.HAL_I2C_Master_Seq_Transmit_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:7504   .text.HAL_I2C_Master_Seq_Transmit_DMA:0000000000000000 HAL_I2C_Master_Seq_Transmit_DMA
+     /tmp/ccVyGVF6.s:7921   .text.HAL_I2C_Master_Seq_Transmit_DMA:00000000000001d0 $d
+     /tmp/ccVyGVF6.s:7930   .text.HAL_I2C_Master_Seq_Receive_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:7937   .text.HAL_I2C_Master_Seq_Receive_IT:0000000000000000 HAL_I2C_Master_Seq_Receive_IT
+     /tmp/ccVyGVF6.s:8123   .text.HAL_I2C_Master_Seq_Receive_IT:00000000000000ac $d
+     /tmp/ccVyGVF6.s:8129   .text.HAL_I2C_Master_Seq_Receive_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:8136   .text.HAL_I2C_Master_Seq_Receive_DMA:0000000000000000 HAL_I2C_Master_Seq_Receive_DMA
+ARM GAS  /tmp/ccVyGVF6.s 			page 477
+
+
+     /tmp/ccVyGVF6.s:8464   .text.HAL_I2C_Master_Seq_Receive_DMA:0000000000000160 $d
+     /tmp/ccVyGVF6.s:8473   .text.HAL_I2C_Slave_Seq_Transmit_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:8480   .text.HAL_I2C_Slave_Seq_Transmit_IT:0000000000000000 HAL_I2C_Slave_Seq_Transmit_IT
+     /tmp/ccVyGVF6.s:8689   .text.HAL_I2C_Slave_Seq_Transmit_IT:00000000000000dc $d
+     /tmp/ccVyGVF6.s:14550  .text.I2C_DMAAbort:0000000000000000 I2C_DMAAbort
+     /tmp/ccVyGVF6.s:8695   .text.HAL_I2C_Slave_Seq_Transmit_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:8702   .text.HAL_I2C_Slave_Seq_Transmit_DMA:0000000000000000 HAL_I2C_Slave_Seq_Transmit_DMA
+     /tmp/ccVyGVF6.s:9086   .text.HAL_I2C_Slave_Seq_Transmit_DMA:000000000000019c $d
+     /tmp/ccVyGVF6.s:9094   .text.HAL_I2C_Slave_Seq_Receive_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:9101   .text.HAL_I2C_Slave_Seq_Receive_IT:0000000000000000 HAL_I2C_Slave_Seq_Receive_IT
+     /tmp/ccVyGVF6.s:9310   .text.HAL_I2C_Slave_Seq_Receive_IT:00000000000000dc $d
+     /tmp/ccVyGVF6.s:9316   .text.HAL_I2C_Slave_Seq_Receive_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:9323   .text.HAL_I2C_Slave_Seq_Receive_DMA:0000000000000000 HAL_I2C_Slave_Seq_Receive_DMA
+     /tmp/ccVyGVF6.s:9705   .text.HAL_I2C_Slave_Seq_Receive_DMA:000000000000019c $d
+     /tmp/ccVyGVF6.s:9713   .text.HAL_I2C_EnableListen_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:9720   .text.HAL_I2C_EnableListen_IT:0000000000000000 HAL_I2C_EnableListen_IT
+     /tmp/ccVyGVF6.s:9767   .text.HAL_I2C_EnableListen_IT:0000000000000028 $d
+     /tmp/ccVyGVF6.s:9772   .text.HAL_I2C_DisableListen_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:9779   .text.HAL_I2C_DisableListen_IT:0000000000000000 HAL_I2C_DisableListen_IT
+     /tmp/ccVyGVF6.s:9845   .text.HAL_I2C_Master_Abort_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:9852   .text.HAL_I2C_Master_Abort_IT:0000000000000000 HAL_I2C_Master_Abort_IT
+     /tmp/ccVyGVF6.s:9999   .text.HAL_I2C_Master_Abort_IT:0000000000000084 $d
+     /tmp/ccVyGVF6.s:10004  .text.HAL_I2C_EV_IRQHandler:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10011  .text.HAL_I2C_EV_IRQHandler:0000000000000000 HAL_I2C_EV_IRQHandler
+     /tmp/ccVyGVF6.s:10049  .text.HAL_I2C_MasterTxCpltCallback:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10056  .text.HAL_I2C_MasterTxCpltCallback:0000000000000000 HAL_I2C_MasterTxCpltCallback
+     /tmp/ccVyGVF6.s:10071  .text.HAL_I2C_MasterRxCpltCallback:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10078  .text.HAL_I2C_MasterRxCpltCallback:0000000000000000 HAL_I2C_MasterRxCpltCallback
+     /tmp/ccVyGVF6.s:10093  .text.I2C_ITMasterSeqCplt:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10099  .text.I2C_ITMasterSeqCplt:0000000000000000 I2C_ITMasterSeqCplt
+     /tmp/ccVyGVF6.s:10184  .text.HAL_I2C_SlaveTxCpltCallback:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10191  .text.HAL_I2C_SlaveTxCpltCallback:0000000000000000 HAL_I2C_SlaveTxCpltCallback
+     /tmp/ccVyGVF6.s:10206  .text.HAL_I2C_SlaveRxCpltCallback:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10213  .text.HAL_I2C_SlaveRxCpltCallback:0000000000000000 HAL_I2C_SlaveRxCpltCallback
+     /tmp/ccVyGVF6.s:10228  .text.I2C_ITSlaveSeqCplt:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10234  .text.I2C_ITSlaveSeqCplt:0000000000000000 I2C_ITSlaveSeqCplt
+     /tmp/ccVyGVF6.s:10362  .text.I2C_DMASlaveTransmitCplt:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10420  .text.I2C_DMASlaveReceiveCplt:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10481  .text.HAL_I2C_AddrCallback:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10488  .text.HAL_I2C_AddrCallback:0000000000000000 HAL_I2C_AddrCallback
+     /tmp/ccVyGVF6.s:10505  .text.I2C_ITAddrCplt:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10511  .text.I2C_ITAddrCplt:0000000000000000 I2C_ITAddrCplt
+     /tmp/ccVyGVF6.s:10671  .text.HAL_I2C_ListenCpltCallback:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10678  .text.HAL_I2C_ListenCpltCallback:0000000000000000 HAL_I2C_ListenCpltCallback
+     /tmp/ccVyGVF6.s:10693  .text.I2C_ITListenCplt:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10699  .text.I2C_ITListenCplt:0000000000000000 I2C_ITListenCplt
+     /tmp/ccVyGVF6.s:10802  .text.I2C_ITListenCplt:0000000000000064 $d
+     /tmp/ccVyGVF6.s:10807  .text.HAL_I2C_MemTxCpltCallback:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10814  .text.HAL_I2C_MemTxCpltCallback:0000000000000000 HAL_I2C_MemTxCpltCallback
+     /tmp/ccVyGVF6.s:10829  .text.HAL_I2C_MemRxCpltCallback:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10836  .text.HAL_I2C_MemRxCpltCallback:0000000000000000 HAL_I2C_MemRxCpltCallback
+     /tmp/ccVyGVF6.s:10851  .text.HAL_I2C_ErrorCallback:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10858  .text.HAL_I2C_ErrorCallback:0000000000000000 HAL_I2C_ErrorCallback
+     /tmp/ccVyGVF6.s:10873  .text.HAL_I2C_AbortCpltCallback:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10880  .text.HAL_I2C_AbortCpltCallback:0000000000000000 HAL_I2C_AbortCpltCallback
+     /tmp/ccVyGVF6.s:10895  .text.I2C_TreatErrorCallback:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10901  .text.I2C_TreatErrorCallback:0000000000000000 I2C_TreatErrorCallback
+ARM GAS  /tmp/ccVyGVF6.s 			page 478
+
+
+     /tmp/ccVyGVF6.s:10958  .text.I2C_ITError:0000000000000000 $t
+     /tmp/ccVyGVF6.s:10964  .text.I2C_ITError:0000000000000000 I2C_ITError
+     /tmp/ccVyGVF6.s:11236  .text.I2C_ITError:0000000000000124 $d
+     /tmp/ccVyGVF6.s:11243  .text.I2C_ITSlaveCplt:0000000000000000 $t
+     /tmp/ccVyGVF6.s:11249  .text.I2C_ITSlaveCplt:0000000000000000 I2C_ITSlaveCplt
+     /tmp/ccVyGVF6.s:11664  .text.I2C_ITSlaveCplt:00000000000001f0 $d
+     /tmp/ccVyGVF6.s:11669  .text.I2C_Slave_ISR_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:11985  .text.I2C_ITMasterCplt:0000000000000000 $t
+     /tmp/ccVyGVF6.s:11991  .text.I2C_ITMasterCplt:0000000000000000 I2C_ITMasterCplt
+     /tmp/ccVyGVF6.s:12260  .text.I2C_Master_ISR_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:12662  .text.I2C_Mem_ISR_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:13061  .text.I2C_Mem_ISR_DMA:00000000000001c8 $d
+     /tmp/ccVyGVF6.s:13067  .text.I2C_Slave_ISR_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:13364  .text.I2C_Master_ISR_DMA:0000000000000000 $t
+     /tmp/ccVyGVF6.s:13689  .text.I2C_DMAError:0000000000000000 $t
+     /tmp/ccVyGVF6.s:13787  .text.I2C_DMAMasterTransmitCplt:0000000000000000 $t
+     /tmp/ccVyGVF6.s:13894  .text.I2C_DMAMasterReceiveCplt:0000000000000000 $t
+     /tmp/ccVyGVF6.s:14013  .text.I2C_Mem_ISR_IT:0000000000000000 $t
+     /tmp/ccVyGVF6.s:14432  .text.I2C_Mem_ISR_IT:00000000000001b8 $d
+     /tmp/ccVyGVF6.s:14438  .text.HAL_I2C_ER_IRQHandler:0000000000000000 $t
+     /tmp/ccVyGVF6.s:14445  .text.HAL_I2C_ER_IRQHandler:0000000000000000 HAL_I2C_ER_IRQHandler
+     /tmp/ccVyGVF6.s:14544  .text.I2C_DMAAbort:0000000000000000 $t
+     /tmp/ccVyGVF6.s:14596  .text.HAL_I2C_GetState:0000000000000000 $t
+     /tmp/ccVyGVF6.s:14603  .text.HAL_I2C_GetState:0000000000000000 HAL_I2C_GetState
+     /tmp/ccVyGVF6.s:14621  .text.HAL_I2C_GetMode:0000000000000000 $t
+     /tmp/ccVyGVF6.s:14628  .text.HAL_I2C_GetMode:0000000000000000 HAL_I2C_GetMode
+     /tmp/ccVyGVF6.s:14646  .text.HAL_I2C_GetError:0000000000000000 $t
+     /tmp/ccVyGVF6.s:14653  .text.HAL_I2C_GetError:0000000000000000 HAL_I2C_GetError
+
+UNDEFINED SYMBOLS
+HAL_GetTick
+HAL_DMA_Start_IT
+HAL_DMA_Abort_IT
+HAL_DMA_GetState
+HAL_DMA_GetError
diff --git a/build/stm32f7xx_hal_i2c.o b/build/stm32f7xx_hal_i2c.o
new file mode 100644
index 0000000..971720b
Binary files /dev/null and b/build/stm32f7xx_hal_i2c.o differ
diff --git a/build/stm32f7xx_hal_i2c_ex.d b/build/stm32f7xx_hal_i2c_ex.d
new file mode 100644
index 0000000..271be8e
--- /dev/null
+++ b/build/stm32f7xx_hal_i2c_ex.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_i2c_ex.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_i2c_ex.lst b/build/stm32f7xx_hal_i2c_ex.lst
new file mode 100644
index 0000000..fdfff38
--- /dev/null
+++ b/build/stm32f7xx_hal_i2c_ex.lst
@@ -0,0 +1,628 @@
+ARM GAS  /tmp/ccJs8R3x.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_i2c_ex.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.HAL_I2CEx_ConfigAnalogFilter,"ax",%progbits
+  17              		.align	1
+  18              		.global	HAL_I2CEx_ConfigAnalogFilter
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	HAL_I2CEx_ConfigAnalogFilter:
+  26              	.LVL0:
+  27              	.LFB141:
+  28              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @file    stm32f7xx_hal_i2c_ex.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @brief   I2C Extended HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *          functionalities of I2C Extended peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *           + Filter Mode Functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *           + FastModePlus Functions
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   ******************************************************************************
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @attention
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * Copyright (c) 2017 STMicroelectronics.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * All rights reserved.
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * in the root directory of this software component.
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   ******************************************************************************
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   @verbatim
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   ==============================================================================
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****                ##### I2C peripheral Extended features  #####
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   ==============================================================================
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   [..] Comparing to other previous devices, the I2C interface for STM32F7xx
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****        devices contains the following additional features
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****        (+) Possibility to disable or enable Analog Noise Filter
+ARM GAS  /tmp/ccJs8R3x.s 			page 2
+
+
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****        (+) Use of a configured Digital Noise Filter
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****        (+) Disable or enable Fast Mode Plus
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****                      ##### How to use this driver #####
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   ==============================================================================
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   [..] This driver provides functions to:
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****           (++) HAL_I2CEx_EnableFastModePlus()
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****           (++) HAL_I2CEx_DisableFastModePlus()
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   @endverbatim
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   */
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Includes ------------------------------------------------------------------*/
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** #include "stm32f7xx_hal.h"
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @{
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   */
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** @defgroup I2CEx I2CEx
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @brief I2C Extended HAL module driver
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @{
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   */
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** #ifdef HAL_I2C_MODULE_ENABLED
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private define ------------------------------------------------------------*/
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private macro -------------------------------------------------------------*/
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private variables ---------------------------------------------------------*/
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private function prototypes -----------------------------------------------*/
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private functions ---------------------------------------------------------*/
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @{
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   */
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @brief    Filter Mode Functions
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** @verbatim
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****  ===============================================================================
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****                       ##### Filter Mode Functions #####
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****  ===============================================================================
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     [..] This section provides functions allowing to:
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****       (+) Configure Noise Filters
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** @endverbatim
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @{
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   */
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /**
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @brief  Configure I2C Analog noise filter.
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *                the configuration information for the specified I2Cx peripheral.
+ARM GAS  /tmp/ccJs8R3x.s 			page 3
+
+
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @param  AnalogFilter New state of the Analog filter.
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @retval HAL status
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   */
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** {
+  29              		.loc 1 92 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   /* Check the parameters */
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  34              		.loc 1 94 3 view .LVU1
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+  35              		.loc 1 95 3 view .LVU2
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+  36              		.loc 1 97 3 view .LVU3
+  37              		.loc 1 97 11 is_stmt 0 view .LVU4
+  38 0000 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+  39 0004 DBB2     		uxtb	r3, r3
+  40              		.loc 1 97 6 view .LVU5
+  41 0006 202B     		cmp	r3, #32
+  42 0008 24D1     		bne	.L3
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   {
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Process Locked */
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     __HAL_LOCK(hi2c);
+  43              		.loc 1 100 5 is_stmt 1 view .LVU6
+  44              		.loc 1 100 5 view .LVU7
+  45 000a 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+  46 000e 012B     		cmp	r3, #1
+  47 0010 22D0     		beq	.L4
+  48              		.loc 1 100 5 discriminator 2 view .LVU8
+  49 0012 0123     		movs	r3, #1
+  50 0014 80F84030 		strb	r3, [r0, #64]
+  51              		.loc 1 100 5 discriminator 2 view .LVU9
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_BUSY;
+  52              		.loc 1 102 5 discriminator 2 view .LVU10
+  53              		.loc 1 102 17 is_stmt 0 discriminator 2 view .LVU11
+  54 0018 2423     		movs	r3, #36
+  55 001a 80F84130 		strb	r3, [r0, #65]
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Disable the selected I2C peripheral */
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     __HAL_I2C_DISABLE(hi2c);
+  56              		.loc 1 105 5 is_stmt 1 discriminator 2 view .LVU12
+  57 001e 0268     		ldr	r2, [r0]
+  58 0020 1368     		ldr	r3, [r2]
+  59 0022 23F00103 		bic	r3, r3, #1
+  60 0026 1360     		str	r3, [r2]
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Reset I2Cx ANOFF bit */
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+  61              		.loc 1 108 5 discriminator 2 view .LVU13
+  62              		.loc 1 108 9 is_stmt 0 discriminator 2 view .LVU14
+  63 0028 0268     		ldr	r2, [r0]
+  64              		.loc 1 108 25 discriminator 2 view .LVU15
+ARM GAS  /tmp/ccJs8R3x.s 			page 4
+
+
+  65 002a 1368     		ldr	r3, [r2]
+  66 002c 23F48053 		bic	r3, r3, #4096
+  67 0030 1360     		str	r3, [r2]
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Set analog filter bit*/
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     hi2c->Instance->CR1 |= AnalogFilter;
+  68              		.loc 1 111 5 is_stmt 1 discriminator 2 view .LVU16
+  69              		.loc 1 111 9 is_stmt 0 discriminator 2 view .LVU17
+  70 0032 0268     		ldr	r2, [r0]
+  71              		.loc 1 111 25 discriminator 2 view .LVU18
+  72 0034 1368     		ldr	r3, [r2]
+  73 0036 1943     		orrs	r1, r1, r3
+  74              	.LVL1:
+  75              		.loc 1 111 25 discriminator 2 view .LVU19
+  76 0038 1160     		str	r1, [r2]
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     __HAL_I2C_ENABLE(hi2c);
+  77              		.loc 1 113 5 is_stmt 1 discriminator 2 view .LVU20
+  78 003a 0268     		ldr	r2, [r0]
+  79 003c 1368     		ldr	r3, [r2]
+  80 003e 43F00103 		orr	r3, r3, #1
+  81 0042 1360     		str	r3, [r2]
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_READY;
+  82              		.loc 1 115 5 discriminator 2 view .LVU21
+  83              		.loc 1 115 17 is_stmt 0 discriminator 2 view .LVU22
+  84 0044 2023     		movs	r3, #32
+  85 0046 80F84130 		strb	r3, [r0, #65]
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Process Unlocked */
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     __HAL_UNLOCK(hi2c);
+  86              		.loc 1 118 5 is_stmt 1 discriminator 2 view .LVU23
+  87              		.loc 1 118 5 discriminator 2 view .LVU24
+  88 004a 0023     		movs	r3, #0
+  89 004c 80F84030 		strb	r3, [r0, #64]
+  90              		.loc 1 118 5 discriminator 2 view .LVU25
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     return HAL_OK;
+  91              		.loc 1 120 5 discriminator 2 view .LVU26
+  92              		.loc 1 120 12 is_stmt 0 discriminator 2 view .LVU27
+  93 0050 1846     		mov	r0, r3
+  94              	.LVL2:
+  95              		.loc 1 120 12 discriminator 2 view .LVU28
+  96 0052 7047     		bx	lr
+  97              	.LVL3:
+  98              	.L3:
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   }
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   else
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   {
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     return HAL_BUSY;
+  99              		.loc 1 124 12 view .LVU29
+ 100 0054 0220     		movs	r0, #2
+ 101              	.LVL4:
+ 102              		.loc 1 124 12 view .LVU30
+ 103 0056 7047     		bx	lr
+ 104              	.LVL5:
+ 105              	.L4:
+ARM GAS  /tmp/ccJs8R3x.s 			page 5
+
+
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 106              		.loc 1 100 5 view .LVU31
+ 107 0058 0220     		movs	r0, #2
+ 108              	.LVL6:
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   }
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** }
+ 109              		.loc 1 126 1 view .LVU32
+ 110 005a 7047     		bx	lr
+ 111              		.cfi_endproc
+ 112              	.LFE141:
+ 114              		.section	.text.HAL_I2CEx_ConfigDigitalFilter,"ax",%progbits
+ 115              		.align	1
+ 116              		.global	HAL_I2CEx_ConfigDigitalFilter
+ 117              		.syntax unified
+ 118              		.thumb
+ 119              		.thumb_func
+ 120              		.fpu fpv5-d16
+ 122              	HAL_I2CEx_ConfigDigitalFilter:
+ 123              	.LVL7:
+ 124              	.LFB142:
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /**
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @brief  Configure I2C Digital noise filter.
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *                the configuration information for the specified I2Cx peripheral.
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @retval HAL status
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   */
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** {
+ 125              		.loc 1 136 1 is_stmt 1 view -0
+ 126              		.cfi_startproc
+ 127              		@ args = 0, pretend = 0, frame = 0
+ 128              		@ frame_needed = 0, uses_anonymous_args = 0
+ 129              		@ link register save eliminated.
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   uint32_t tmpreg;
+ 130              		.loc 1 137 3 view .LVU34
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   /* Check the parameters */
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ 131              		.loc 1 140 3 view .LVU35
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+ 132              		.loc 1 141 3 view .LVU36
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   if (hi2c->State == HAL_I2C_STATE_READY)
+ 133              		.loc 1 143 3 view .LVU37
+ 134              		.loc 1 143 11 is_stmt 0 view .LVU38
+ 135 0000 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 136 0004 DBB2     		uxtb	r3, r3
+ 137              		.loc 1 143 6 view .LVU39
+ 138 0006 202B     		cmp	r3, #32
+ 139 0008 22D1     		bne	.L7
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   {
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Process Locked */
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     __HAL_LOCK(hi2c);
+ 140              		.loc 1 146 5 is_stmt 1 view .LVU40
+ 141              		.loc 1 146 5 view .LVU41
+ARM GAS  /tmp/ccJs8R3x.s 			page 6
+
+
+ 142 000a 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 143 000e 012B     		cmp	r3, #1
+ 144 0010 20D0     		beq	.L8
+ 145              		.loc 1 146 5 discriminator 2 view .LVU42
+ 146 0012 0123     		movs	r3, #1
+ 147 0014 80F84030 		strb	r3, [r0, #64]
+ 148              		.loc 1 146 5 discriminator 2 view .LVU43
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_BUSY;
+ 149              		.loc 1 148 5 discriminator 2 view .LVU44
+ 150              		.loc 1 148 17 is_stmt 0 discriminator 2 view .LVU45
+ 151 0018 2423     		movs	r3, #36
+ 152 001a 80F84130 		strb	r3, [r0, #65]
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Disable the selected I2C peripheral */
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     __HAL_I2C_DISABLE(hi2c);
+ 153              		.loc 1 151 5 is_stmt 1 discriminator 2 view .LVU46
+ 154 001e 0268     		ldr	r2, [r0]
+ 155 0020 1368     		ldr	r3, [r2]
+ 156 0022 23F00103 		bic	r3, r3, #1
+ 157 0026 1360     		str	r3, [r2]
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Get the old register value */
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     tmpreg = hi2c->Instance->CR1;
+ 158              		.loc 1 154 5 discriminator 2 view .LVU47
+ 159              		.loc 1 154 18 is_stmt 0 discriminator 2 view .LVU48
+ 160 0028 0268     		ldr	r2, [r0]
+ 161              		.loc 1 154 12 discriminator 2 view .LVU49
+ 162 002a 1368     		ldr	r3, [r2]
+ 163              	.LVL8:
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Reset I2Cx DNF bits [11:8] */
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     tmpreg &= ~(I2C_CR1_DNF);
+ 164              		.loc 1 157 5 is_stmt 1 discriminator 2 view .LVU50
+ 165              		.loc 1 157 12 is_stmt 0 discriminator 2 view .LVU51
+ 166 002c 23F47063 		bic	r3, r3, #3840
+ 167              	.LVL9:
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Set I2Cx DNF coefficient */
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     tmpreg |= DigitalFilter << 8U;
+ 168              		.loc 1 160 5 is_stmt 1 discriminator 2 view .LVU52
+ 169              		.loc 1 160 12 is_stmt 0 discriminator 2 view .LVU53
+ 170 0030 43EA0121 		orr	r1, r3, r1, lsl #8
+ 171              	.LVL10:
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Store the new register value */
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     hi2c->Instance->CR1 = tmpreg;
+ 172              		.loc 1 163 5 is_stmt 1 discriminator 2 view .LVU54
+ 173              		.loc 1 163 25 is_stmt 0 discriminator 2 view .LVU55
+ 174 0034 1160     		str	r1, [r2]
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     __HAL_I2C_ENABLE(hi2c);
+ 175              		.loc 1 165 5 is_stmt 1 discriminator 2 view .LVU56
+ 176 0036 0268     		ldr	r2, [r0]
+ 177 0038 1368     		ldr	r3, [r2]
+ 178 003a 43F00103 		orr	r3, r3, #1
+ 179 003e 1360     		str	r3, [r2]
+ARM GAS  /tmp/ccJs8R3x.s 			page 7
+
+
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     hi2c->State = HAL_I2C_STATE_READY;
+ 180              		.loc 1 167 5 discriminator 2 view .LVU57
+ 181              		.loc 1 167 17 is_stmt 0 discriminator 2 view .LVU58
+ 182 0040 2023     		movs	r3, #32
+ 183 0042 80F84130 		strb	r3, [r0, #65]
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     /* Process Unlocked */
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     __HAL_UNLOCK(hi2c);
+ 184              		.loc 1 170 5 is_stmt 1 discriminator 2 view .LVU59
+ 185              		.loc 1 170 5 discriminator 2 view .LVU60
+ 186 0046 0023     		movs	r3, #0
+ 187 0048 80F84030 		strb	r3, [r0, #64]
+ 188              		.loc 1 170 5 discriminator 2 view .LVU61
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     return HAL_OK;
+ 189              		.loc 1 172 5 discriminator 2 view .LVU62
+ 190              		.loc 1 172 12 is_stmt 0 discriminator 2 view .LVU63
+ 191 004c 1846     		mov	r0, r3
+ 192              	.LVL11:
+ 193              		.loc 1 172 12 discriminator 2 view .LVU64
+ 194 004e 7047     		bx	lr
+ 195              	.LVL12:
+ 196              	.L7:
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   }
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   else
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   {
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     return HAL_BUSY;
+ 197              		.loc 1 176 12 view .LVU65
+ 198 0050 0220     		movs	r0, #2
+ 199              	.LVL13:
+ 200              		.loc 1 176 12 view .LVU66
+ 201 0052 7047     		bx	lr
+ 202              	.LVL14:
+ 203              	.L8:
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 204              		.loc 1 146 5 view .LVU67
+ 205 0054 0220     		movs	r0, #2
+ 206              	.LVL15:
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   }
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** }
+ 207              		.loc 1 178 1 view .LVU68
+ 208 0056 7047     		bx	lr
+ 209              		.cfi_endproc
+ 210              	.LFE142:
+ 212              		.section	.text.HAL_I2CEx_EnableFastModePlus,"ax",%progbits
+ 213              		.align	1
+ 214              		.global	HAL_I2CEx_EnableFastModePlus
+ 215              		.syntax unified
+ 216              		.thumb
+ 217              		.thumb_func
+ 218              		.fpu fpv5-d16
+ 220              	HAL_I2CEx_EnableFastModePlus:
+ 221              	.LVL16:
+ 222              	.LFB143:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /**
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @}
+ARM GAS  /tmp/ccJs8R3x.s 			page 8
+
+
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   */
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** #if  (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @brief    Fast Mode Plus Functions
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** @verbatim
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****  ===============================================================================
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****                       ##### Fast Mode Plus Functions #####
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****  ===============================================================================
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****     [..] This section provides functions allowing to:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****       (+) Configure Fast Mode Plus
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** @endverbatim
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @{
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   */
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /**
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @brief Enable the I2C fast mode plus driving capability.
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @param ConfigFastModePlus Selects the pin.
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *   This parameter can be one of the @ref I2CEx_FastModePlus values
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        on each one of the following pins PB6, PB7, PB8 and PB9.
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @note  For all I2C4 pins fast mode plus driving capability can be enabled
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @retval None
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   */
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** {
+ 223              		.loc 1 216 1 is_stmt 1 view -0
+ 224              		.cfi_startproc
+ 225              		@ args = 0, pretend = 0, frame = 8
+ 226              		@ frame_needed = 0, uses_anonymous_args = 0
+ 227              		@ link register save eliminated.
+ 228              		.loc 1 216 1 is_stmt 0 view .LVU70
+ 229 0000 82B0     		sub	sp, sp, #8
+ 230              	.LCFI0:
+ 231              		.cfi_def_cfa_offset 8
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   /* Check the parameter */
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+ 232              		.loc 1 218 3 is_stmt 1 view .LVU71
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   /* Enable SYSCFG clock */
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 233              		.loc 1 221 3 view .LVU72
+ 234              	.LBB2:
+ 235              		.loc 1 221 3 view .LVU73
+ 236              		.loc 1 221 3 view .LVU74
+ 237 0002 084A     		ldr	r2, .L11
+ 238 0004 516C     		ldr	r1, [r2, #68]
+ARM GAS  /tmp/ccJs8R3x.s 			page 9
+
+
+ 239 0006 41F48041 		orr	r1, r1, #16384
+ 240 000a 5164     		str	r1, [r2, #68]
+ 241              		.loc 1 221 3 view .LVU75
+ 242 000c 526C     		ldr	r2, [r2, #68]
+ 243 000e 02F48042 		and	r2, r2, #16384
+ 244 0012 0192     		str	r2, [sp, #4]
+ 245              		.loc 1 221 3 view .LVU76
+ 246 0014 019B     		ldr	r3, [sp, #4]
+ 247              	.LBE2:
+ 248              		.loc 1 221 3 view .LVU77
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   /* Enable fast mode plus driving capability for selected pin */
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
+ 249              		.loc 1 224 3 view .LVU78
+ 250 0016 044A     		ldr	r2, .L11+4
+ 251 0018 5368     		ldr	r3, [r2, #4]
+ 252 001a 0343     		orrs	r3, r3, r0
+ 253 001c 5360     		str	r3, [r2, #4]
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** }
+ 254              		.loc 1 225 1 is_stmt 0 view .LVU79
+ 255 001e 02B0     		add	sp, sp, #8
+ 256              	.LCFI1:
+ 257              		.cfi_def_cfa_offset 0
+ 258              		@ sp needed
+ 259 0020 7047     		bx	lr
+ 260              	.L12:
+ 261 0022 00BF     		.align	2
+ 262              	.L11:
+ 263 0024 00380240 		.word	1073887232
+ 264 0028 00380140 		.word	1073821696
+ 265              		.cfi_endproc
+ 266              	.LFE143:
+ 268              		.section	.text.HAL_I2CEx_DisableFastModePlus,"ax",%progbits
+ 269              		.align	1
+ 270              		.global	HAL_I2CEx_DisableFastModePlus
+ 271              		.syntax unified
+ 272              		.thumb
+ 273              		.thumb_func
+ 274              		.fpu fpv5-d16
+ 276              	HAL_I2CEx_DisableFastModePlus:
+ 277              	.LVL17:
+ 278              	.LFB144:
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /**
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @brief Disable the I2C fast mode plus driving capability.
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @param ConfigFastModePlus Selects the pin.
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *   This parameter can be one of the @ref I2CEx_FastModePlus values
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        on each one of the following pins PB6, PB7, PB8 and PB9.
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @note  For all I2C4 pins fast mode plus driving capability can be disabled
+ARM GAS  /tmp/ccJs8R3x.s 			page 10
+
+
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   * @retval None
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   */
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** {
+ 279              		.loc 1 245 1 is_stmt 1 view -0
+ 280              		.cfi_startproc
+ 281              		@ args = 0, pretend = 0, frame = 8
+ 282              		@ frame_needed = 0, uses_anonymous_args = 0
+ 283              		@ link register save eliminated.
+ 284              		.loc 1 245 1 is_stmt 0 view .LVU81
+ 285 0000 82B0     		sub	sp, sp, #8
+ 286              	.LCFI2:
+ 287              		.cfi_def_cfa_offset 8
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   /* Check the parameter */
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+ 288              		.loc 1 247 3 is_stmt 1 view .LVU82
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   /* Enable SYSCFG clock */
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 289              		.loc 1 250 3 view .LVU83
+ 290              	.LBB3:
+ 291              		.loc 1 250 3 view .LVU84
+ 292              		.loc 1 250 3 view .LVU85
+ 293 0002 084A     		ldr	r2, .L15
+ 294 0004 516C     		ldr	r1, [r2, #68]
+ 295 0006 41F48041 		orr	r1, r1, #16384
+ 296 000a 5164     		str	r1, [r2, #68]
+ 297              		.loc 1 250 3 view .LVU86
+ 298 000c 526C     		ldr	r2, [r2, #68]
+ 299 000e 02F48042 		and	r2, r2, #16384
+ 300 0012 0192     		str	r2, [sp, #4]
+ 301              		.loc 1 250 3 view .LVU87
+ 302 0014 019B     		ldr	r3, [sp, #4]
+ 303              	.LBE3:
+ 304              		.loc 1 250 3 view .LVU88
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** 
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   /* Disable fast mode plus driving capability for selected pin */
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c ****   CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
+ 305              		.loc 1 253 3 view .LVU89
+ 306 0016 044A     		ldr	r2, .L15+4
+ 307 0018 5368     		ldr	r3, [r2, #4]
+ 308 001a 23EA0003 		bic	r3, r3, r0
+ 309 001e 5360     		str	r3, [r2, #4]
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** }
+ 310              		.loc 1 254 1 is_stmt 0 view .LVU90
+ 311 0020 02B0     		add	sp, sp, #8
+ 312              	.LCFI3:
+ 313              		.cfi_def_cfa_offset 0
+ 314              		@ sp needed
+ 315 0022 7047     		bx	lr
+ 316              	.L16:
+ 317              		.align	2
+ 318              	.L15:
+ 319 0024 00380240 		.word	1073887232
+ 320 0028 00380140 		.word	1073821696
+ 321              		.cfi_endproc
+ARM GAS  /tmp/ccJs8R3x.s 			page 11
+
+
+ 322              	.LFE144:
+ 324              		.text
+ 325              	.Letext0:
+ 326              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 327              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 328              		.file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 329              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 330              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h"
+ARM GAS  /tmp/ccJs8R3x.s 			page 12
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_i2c_ex.c
+     /tmp/ccJs8R3x.s:17     .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000000 $t
+     /tmp/ccJs8R3x.s:25     .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000000 HAL_I2CEx_ConfigAnalogFilter
+     /tmp/ccJs8R3x.s:115    .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000000 $t
+     /tmp/ccJs8R3x.s:122    .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000000 HAL_I2CEx_ConfigDigitalFilter
+     /tmp/ccJs8R3x.s:213    .text.HAL_I2CEx_EnableFastModePlus:0000000000000000 $t
+     /tmp/ccJs8R3x.s:220    .text.HAL_I2CEx_EnableFastModePlus:0000000000000000 HAL_I2CEx_EnableFastModePlus
+     /tmp/ccJs8R3x.s:263    .text.HAL_I2CEx_EnableFastModePlus:0000000000000024 $d
+     /tmp/ccJs8R3x.s:269    .text.HAL_I2CEx_DisableFastModePlus:0000000000000000 $t
+     /tmp/ccJs8R3x.s:276    .text.HAL_I2CEx_DisableFastModePlus:0000000000000000 HAL_I2CEx_DisableFastModePlus
+     /tmp/ccJs8R3x.s:319    .text.HAL_I2CEx_DisableFastModePlus:0000000000000024 $d
+
+NO UNDEFINED SYMBOLS
diff --git a/build/stm32f7xx_hal_i2c_ex.o b/build/stm32f7xx_hal_i2c_ex.o
new file mode 100644
index 0000000..16e9799
Binary files /dev/null and b/build/stm32f7xx_hal_i2c_ex.o differ
diff --git a/build/stm32f7xx_hal_msp.d b/build/stm32f7xx_hal_msp.d
new file mode 100644
index 0000000..3b544a2
--- /dev/null
+++ b/build/stm32f7xx_hal_msp.d
@@ -0,0 +1,88 @@
+build/stm32f7xx_hal_msp.o: Src/stm32f7xx_hal_msp.c Inc/main.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h
+Inc/main.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h:
diff --git a/build/stm32f7xx_hal_msp.lst b/build/stm32f7xx_hal_msp.lst
new file mode 100644
index 0000000..8ee4560
--- /dev/null
+++ b/build/stm32f7xx_hal_msp.lst
@@ -0,0 +1,1415 @@
+ARM GAS  /tmp/ccF0g8wo.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_msp.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.HAL_MspInit,"ax",%progbits
+  17              		.align	1
+  18              		.global	HAL_MspInit
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	HAL_MspInit:
+  26              	.LFB1183:
+  27              		.file 1 "Src/stm32f7xx_hal_msp.c"
+   1:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN Header */
+   2:Src/stm32f7xx_hal_msp.c **** /**
+   3:Src/stm32f7xx_hal_msp.c ****   ******************************************************************************
+   4:Src/stm32f7xx_hal_msp.c ****   * @file         stm32f7xx_hal_msp.c
+   5:Src/stm32f7xx_hal_msp.c ****   * @brief        This file provides code for the MSP Initialization
+   6:Src/stm32f7xx_hal_msp.c ****   *               and de-Initialization codes.
+   7:Src/stm32f7xx_hal_msp.c ****   ******************************************************************************
+   8:Src/stm32f7xx_hal_msp.c ****   * @attention
+   9:Src/stm32f7xx_hal_msp.c ****   *
+  10:Src/stm32f7xx_hal_msp.c ****   * Copyright (c) 2023 STMicroelectronics.
+  11:Src/stm32f7xx_hal_msp.c ****   * All rights reserved.
+  12:Src/stm32f7xx_hal_msp.c ****   *
+  13:Src/stm32f7xx_hal_msp.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  14:Src/stm32f7xx_hal_msp.c ****   * in the root directory of this software component.
+  15:Src/stm32f7xx_hal_msp.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  16:Src/stm32f7xx_hal_msp.c ****   *
+  17:Src/stm32f7xx_hal_msp.c ****   ******************************************************************************
+  18:Src/stm32f7xx_hal_msp.c ****   */
+  19:Src/stm32f7xx_hal_msp.c **** /* USER CODE END Header */
+  20:Src/stm32f7xx_hal_msp.c **** 
+  21:Src/stm32f7xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
+  22:Src/stm32f7xx_hal_msp.c **** #include "main.h"
+  23:Src/stm32f7xx_hal_msp.c **** 
+  24:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN Includes */
+  25:Src/stm32f7xx_hal_msp.c **** 
+  26:Src/stm32f7xx_hal_msp.c **** /* USER CODE END Includes */
+  27:Src/stm32f7xx_hal_msp.c **** 
+  28:Src/stm32f7xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
+  29:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TD */
+  30:Src/stm32f7xx_hal_msp.c **** 
+  31:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TD */
+ARM GAS  /tmp/ccF0g8wo.s 			page 2
+
+
+  32:Src/stm32f7xx_hal_msp.c **** 
+  33:Src/stm32f7xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
+  34:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN Define */
+  35:Src/stm32f7xx_hal_msp.c **** 
+  36:Src/stm32f7xx_hal_msp.c **** /* USER CODE END Define */
+  37:Src/stm32f7xx_hal_msp.c **** 
+  38:Src/stm32f7xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
+  39:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN Macro */
+  40:Src/stm32f7xx_hal_msp.c **** 
+  41:Src/stm32f7xx_hal_msp.c **** /* USER CODE END Macro */
+  42:Src/stm32f7xx_hal_msp.c **** 
+  43:Src/stm32f7xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
+  44:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN PV */
+  45:Src/stm32f7xx_hal_msp.c **** 
+  46:Src/stm32f7xx_hal_msp.c **** /* USER CODE END PV */
+  47:Src/stm32f7xx_hal_msp.c **** 
+  48:Src/stm32f7xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
+  49:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN PFP */
+  50:Src/stm32f7xx_hal_msp.c **** 
+  51:Src/stm32f7xx_hal_msp.c **** /* USER CODE END PFP */
+  52:Src/stm32f7xx_hal_msp.c **** 
+  53:Src/stm32f7xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
+  54:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
+  55:Src/stm32f7xx_hal_msp.c **** 
+  56:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
+  57:Src/stm32f7xx_hal_msp.c **** 
+  58:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN 0 */
+  59:Src/stm32f7xx_hal_msp.c **** 
+  60:Src/stm32f7xx_hal_msp.c **** /* USER CODE END 0 */
+  61:Src/stm32f7xx_hal_msp.c **** /**
+  62:Src/stm32f7xx_hal_msp.c ****   * Initializes the Global MSP.
+  63:Src/stm32f7xx_hal_msp.c ****   */
+  64:Src/stm32f7xx_hal_msp.c **** void HAL_MspInit(void)
+  65:Src/stm32f7xx_hal_msp.c **** {
+  28              		.loc 1 65 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 8
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  33 0000 82B0     		sub	sp, sp, #8
+  34              	.LCFI0:
+  35              		.cfi_def_cfa_offset 8
+  66:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN MspInit 0 */
+  67:Src/stm32f7xx_hal_msp.c **** 
+  68:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END MspInit 0 */
+  69:Src/stm32f7xx_hal_msp.c **** 
+  70:Src/stm32f7xx_hal_msp.c ****   __HAL_RCC_PWR_CLK_ENABLE();
+  36              		.loc 1 70 3 view .LVU1
+  37              	.LBB2:
+  38              		.loc 1 70 3 view .LVU2
+  39              		.loc 1 70 3 view .LVU3
+  40 0002 0A4B     		ldr	r3, .L3
+  41 0004 1A6C     		ldr	r2, [r3, #64]
+  42 0006 42F08052 		orr	r2, r2, #268435456
+  43 000a 1A64     		str	r2, [r3, #64]
+  44              		.loc 1 70 3 view .LVU4
+  45 000c 1A6C     		ldr	r2, [r3, #64]
+ARM GAS  /tmp/ccF0g8wo.s 			page 3
+
+
+  46 000e 02F08052 		and	r2, r2, #268435456
+  47 0012 0092     		str	r2, [sp]
+  48              		.loc 1 70 3 view .LVU5
+  49 0014 009A     		ldr	r2, [sp]
+  50              	.LBE2:
+  51              		.loc 1 70 3 view .LVU6
+  71:Src/stm32f7xx_hal_msp.c ****   __HAL_RCC_SYSCFG_CLK_ENABLE();
+  52              		.loc 1 71 3 view .LVU7
+  53              	.LBB3:
+  54              		.loc 1 71 3 view .LVU8
+  55              		.loc 1 71 3 view .LVU9
+  56 0016 5A6C     		ldr	r2, [r3, #68]
+  57 0018 42F48042 		orr	r2, r2, #16384
+  58 001c 5A64     		str	r2, [r3, #68]
+  59              		.loc 1 71 3 view .LVU10
+  60 001e 5B6C     		ldr	r3, [r3, #68]
+  61 0020 03F48043 		and	r3, r3, #16384
+  62 0024 0193     		str	r3, [sp, #4]
+  63              		.loc 1 71 3 view .LVU11
+  64 0026 019B     		ldr	r3, [sp, #4]
+  65              	.LBE3:
+  66              		.loc 1 71 3 view .LVU12
+  72:Src/stm32f7xx_hal_msp.c **** 
+  73:Src/stm32f7xx_hal_msp.c ****   /* System interrupt init*/
+  74:Src/stm32f7xx_hal_msp.c **** 
+  75:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN MspInit 1 */
+  76:Src/stm32f7xx_hal_msp.c **** 
+  77:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END MspInit 1 */
+  78:Src/stm32f7xx_hal_msp.c **** }
+  67              		.loc 1 78 1 is_stmt 0 view .LVU13
+  68 0028 02B0     		add	sp, sp, #8
+  69              	.LCFI1:
+  70              		.cfi_def_cfa_offset 0
+  71              		@ sp needed
+  72 002a 7047     		bx	lr
+  73              	.L4:
+  74              		.align	2
+  75              	.L3:
+  76 002c 00380240 		.word	1073887232
+  77              		.cfi_endproc
+  78              	.LFE1183:
+  80              		.section	.text.HAL_ADC_MspInit,"ax",%progbits
+  81              		.align	1
+  82              		.global	HAL_ADC_MspInit
+  83              		.syntax unified
+  84              		.thumb
+  85              		.thumb_func
+  86              		.fpu fpv5-d16
+  88              	HAL_ADC_MspInit:
+  89              	.LVL0:
+  90              	.LFB1184:
+  79:Src/stm32f7xx_hal_msp.c **** 
+  80:Src/stm32f7xx_hal_msp.c **** /**
+  81:Src/stm32f7xx_hal_msp.c **** * @brief ADC MSP Initialization
+  82:Src/stm32f7xx_hal_msp.c **** * This function configures the hardware resources used in this example
+  83:Src/stm32f7xx_hal_msp.c **** * @param hadc: ADC handle pointer
+  84:Src/stm32f7xx_hal_msp.c **** * @retval None
+ARM GAS  /tmp/ccF0g8wo.s 			page 4
+
+
+  85:Src/stm32f7xx_hal_msp.c **** */
+  86:Src/stm32f7xx_hal_msp.c **** void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+  87:Src/stm32f7xx_hal_msp.c **** {
+  91              		.loc 1 87 1 is_stmt 1 view -0
+  92              		.cfi_startproc
+  93              		@ args = 0, pretend = 0, frame = 48
+  94              		@ frame_needed = 0, uses_anonymous_args = 0
+  95              		.loc 1 87 1 is_stmt 0 view .LVU15
+  96 0000 30B5     		push	{r4, r5, lr}
+  97              	.LCFI2:
+  98              		.cfi_def_cfa_offset 12
+  99              		.cfi_offset 4, -12
+ 100              		.cfi_offset 5, -8
+ 101              		.cfi_offset 14, -4
+ 102 0002 8DB0     		sub	sp, sp, #52
+ 103              	.LCFI3:
+ 104              		.cfi_def_cfa_offset 64
+  88:Src/stm32f7xx_hal_msp.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 105              		.loc 1 88 3 is_stmt 1 view .LVU16
+ 106              		.loc 1 88 20 is_stmt 0 view .LVU17
+ 107 0004 0023     		movs	r3, #0
+ 108 0006 0793     		str	r3, [sp, #28]
+ 109 0008 0893     		str	r3, [sp, #32]
+ 110 000a 0993     		str	r3, [sp, #36]
+ 111 000c 0A93     		str	r3, [sp, #40]
+ 112 000e 0B93     		str	r3, [sp, #44]
+  89:Src/stm32f7xx_hal_msp.c ****   if(hadc->Instance==ADC1)
+ 113              		.loc 1 89 3 is_stmt 1 view .LVU18
+ 114              		.loc 1 89 10 is_stmt 0 view .LVU19
+ 115 0010 0368     		ldr	r3, [r0]
+ 116              		.loc 1 89 5 view .LVU20
+ 117 0012 384A     		ldr	r2, .L11
+ 118 0014 9342     		cmp	r3, r2
+ 119 0016 04D0     		beq	.L9
+  90:Src/stm32f7xx_hal_msp.c ****   {
+  91:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC1_MspInit 0 */
+  92:Src/stm32f7xx_hal_msp.c **** 
+  93:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END ADC1_MspInit 0 */
+  94:Src/stm32f7xx_hal_msp.c ****     /* Peripheral clock enable */
+  95:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_ADC1_CLK_ENABLE();
+  96:Src/stm32f7xx_hal_msp.c **** 
+  97:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOC_CLK_ENABLE();
+  98:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
+  99:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 100:Src/stm32f7xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 101:Src/stm32f7xx_hal_msp.c ****     PC0     ------> ADC1_IN10
+ 102:Src/stm32f7xx_hal_msp.c ****     PC1     ------> ADC1_IN11
+ 103:Src/stm32f7xx_hal_msp.c ****     PA2     ------> ADC1_IN2
+ 104:Src/stm32f7xx_hal_msp.c ****     PB0     ------> ADC1_IN8
+ 105:Src/stm32f7xx_hal_msp.c ****     PB1     ------> ADC1_IN9
+ 106:Src/stm32f7xx_hal_msp.c ****     */
+ 107:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+ 108:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 109:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 110:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 111:Src/stm32f7xx_hal_msp.c **** 
+ 112:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_2;
+ARM GAS  /tmp/ccF0g8wo.s 			page 5
+
+
+ 113:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 114:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 115:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 116:Src/stm32f7xx_hal_msp.c **** 
+ 117:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+ 118:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 119:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 120:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 121:Src/stm32f7xx_hal_msp.c **** 
+ 122:Src/stm32f7xx_hal_msp.c ****     /* ADC1 interrupt Init */
+ 123:Src/stm32f7xx_hal_msp.c ****     HAL_NVIC_SetPriority(ADC_IRQn, 0, 0);
+ 124:Src/stm32f7xx_hal_msp.c ****     HAL_NVIC_EnableIRQ(ADC_IRQn);
+ 125:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC1_MspInit 1 */
+ 126:Src/stm32f7xx_hal_msp.c **** 
+ 127:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END ADC1_MspInit 1 */
+ 128:Src/stm32f7xx_hal_msp.c ****   }
+ 129:Src/stm32f7xx_hal_msp.c ****   else if(hadc->Instance==ADC3)
+ 120              		.loc 1 129 8 is_stmt 1 view .LVU21
+ 121              		.loc 1 129 10 is_stmt 0 view .LVU22
+ 122 0018 374A     		ldr	r2, .L11+4
+ 123 001a 9342     		cmp	r3, r2
+ 124 001c 46D0     		beq	.L10
+ 125              	.LVL1:
+ 126              	.L5:
+ 130:Src/stm32f7xx_hal_msp.c ****   {
+ 131:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC3_MspInit 0 */
+ 132:Src/stm32f7xx_hal_msp.c **** 
+ 133:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END ADC3_MspInit 0 */
+ 134:Src/stm32f7xx_hal_msp.c ****     /* Peripheral clock enable */
+ 135:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_ADC3_CLK_ENABLE();
+ 136:Src/stm32f7xx_hal_msp.c **** 
+ 137:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOF_CLK_ENABLE();
+ 138:Src/stm32f7xx_hal_msp.c ****     /**ADC3 GPIO Configuration
+ 139:Src/stm32f7xx_hal_msp.c ****     PF5     ------> ADC3_IN15
+ 140:Src/stm32f7xx_hal_msp.c ****     */
+ 141:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_5;
+ 142:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 143:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 144:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 145:Src/stm32f7xx_hal_msp.c **** 
+ 146:Src/stm32f7xx_hal_msp.c ****     /* ADC3 interrupt Init */
+ 147:Src/stm32f7xx_hal_msp.c ****     HAL_NVIC_SetPriority(ADC_IRQn, 0, 0);
+ 148:Src/stm32f7xx_hal_msp.c ****     HAL_NVIC_EnableIRQ(ADC_IRQn);
+ 149:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC3_MspInit 1 */
+ 150:Src/stm32f7xx_hal_msp.c **** 
+ 151:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END ADC3_MspInit 1 */
+ 152:Src/stm32f7xx_hal_msp.c ****   }
+ 153:Src/stm32f7xx_hal_msp.c **** 
+ 154:Src/stm32f7xx_hal_msp.c **** }
+ 127              		.loc 1 154 1 view .LVU23
+ 128 001e 0DB0     		add	sp, sp, #52
+ 129              	.LCFI4:
+ 130              		.cfi_remember_state
+ 131              		.cfi_def_cfa_offset 12
+ 132              		@ sp needed
+ 133 0020 30BD     		pop	{r4, r5, pc}
+ 134              	.LVL2:
+ARM GAS  /tmp/ccF0g8wo.s 			page 6
+
+
+ 135              	.L9:
+ 136              	.LCFI5:
+ 137              		.cfi_restore_state
+  95:Src/stm32f7xx_hal_msp.c **** 
+ 138              		.loc 1 95 5 is_stmt 1 view .LVU24
+ 139              	.LBB4:
+  95:Src/stm32f7xx_hal_msp.c **** 
+ 140              		.loc 1 95 5 view .LVU25
+  95:Src/stm32f7xx_hal_msp.c **** 
+ 141              		.loc 1 95 5 view .LVU26
+ 142 0022 364B     		ldr	r3, .L11+8
+ 143 0024 5A6C     		ldr	r2, [r3, #68]
+ 144 0026 42F48072 		orr	r2, r2, #256
+ 145 002a 5A64     		str	r2, [r3, #68]
+  95:Src/stm32f7xx_hal_msp.c **** 
+ 146              		.loc 1 95 5 view .LVU27
+ 147 002c 5A6C     		ldr	r2, [r3, #68]
+ 148 002e 02F48072 		and	r2, r2, #256
+ 149 0032 0192     		str	r2, [sp, #4]
+  95:Src/stm32f7xx_hal_msp.c **** 
+ 150              		.loc 1 95 5 view .LVU28
+ 151 0034 019A     		ldr	r2, [sp, #4]
+ 152              	.LBE4:
+  95:Src/stm32f7xx_hal_msp.c **** 
+ 153              		.loc 1 95 5 view .LVU29
+  97:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
+ 154              		.loc 1 97 5 view .LVU30
+ 155              	.LBB5:
+  97:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
+ 156              		.loc 1 97 5 view .LVU31
+  97:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
+ 157              		.loc 1 97 5 view .LVU32
+ 158 0036 1A6B     		ldr	r2, [r3, #48]
+ 159 0038 42F00402 		orr	r2, r2, #4
+ 160 003c 1A63     		str	r2, [r3, #48]
+  97:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
+ 161              		.loc 1 97 5 view .LVU33
+ 162 003e 1A6B     		ldr	r2, [r3, #48]
+ 163 0040 02F00402 		and	r2, r2, #4
+ 164 0044 0292     		str	r2, [sp, #8]
+  97:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
+ 165              		.loc 1 97 5 view .LVU34
+ 166 0046 029A     		ldr	r2, [sp, #8]
+ 167              	.LBE5:
+  97:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
+ 168              		.loc 1 97 5 view .LVU35
+  98:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 169              		.loc 1 98 5 view .LVU36
+ 170              	.LBB6:
+  98:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 171              		.loc 1 98 5 view .LVU37
+  98:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 172              		.loc 1 98 5 view .LVU38
+ 173 0048 1A6B     		ldr	r2, [r3, #48]
+ 174 004a 42F00102 		orr	r2, r2, #1
+ 175 004e 1A63     		str	r2, [r3, #48]
+  98:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ARM GAS  /tmp/ccF0g8wo.s 			page 7
+
+
+ 176              		.loc 1 98 5 view .LVU39
+ 177 0050 1A6B     		ldr	r2, [r3, #48]
+ 178 0052 02F00102 		and	r2, r2, #1
+ 179 0056 0392     		str	r2, [sp, #12]
+  98:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 180              		.loc 1 98 5 view .LVU40
+ 181 0058 039A     		ldr	r2, [sp, #12]
+ 182              	.LBE6:
+  98:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
+ 183              		.loc 1 98 5 view .LVU41
+  99:Src/stm32f7xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 184              		.loc 1 99 5 view .LVU42
+ 185              	.LBB7:
+  99:Src/stm32f7xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 186              		.loc 1 99 5 view .LVU43
+  99:Src/stm32f7xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 187              		.loc 1 99 5 view .LVU44
+ 188 005a 1A6B     		ldr	r2, [r3, #48]
+ 189 005c 42F00202 		orr	r2, r2, #2
+ 190 0060 1A63     		str	r2, [r3, #48]
+  99:Src/stm32f7xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 191              		.loc 1 99 5 view .LVU45
+ 192 0062 1B6B     		ldr	r3, [r3, #48]
+ 193 0064 03F00203 		and	r3, r3, #2
+ 194 0068 0493     		str	r3, [sp, #16]
+  99:Src/stm32f7xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 195              		.loc 1 99 5 view .LVU46
+ 196 006a 049B     		ldr	r3, [sp, #16]
+ 197              	.LBE7:
+  99:Src/stm32f7xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 198              		.loc 1 99 5 view .LVU47
+ 107:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 199              		.loc 1 107 5 view .LVU48
+ 107:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 200              		.loc 1 107 25 is_stmt 0 view .LVU49
+ 201 006c 0324     		movs	r4, #3
+ 202 006e 0794     		str	r4, [sp, #28]
+ 108:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 203              		.loc 1 108 5 is_stmt 1 view .LVU50
+ 108:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 204              		.loc 1 108 26 is_stmt 0 view .LVU51
+ 205 0070 0894     		str	r4, [sp, #32]
+ 109:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 206              		.loc 1 109 5 is_stmt 1 view .LVU52
+ 110:Src/stm32f7xx_hal_msp.c **** 
+ 207              		.loc 1 110 5 view .LVU53
+ 208 0072 07A9     		add	r1, sp, #28
+ 209 0074 2248     		ldr	r0, .L11+12
+ 210              	.LVL3:
+ 110:Src/stm32f7xx_hal_msp.c **** 
+ 211              		.loc 1 110 5 is_stmt 0 view .LVU54
+ 212 0076 FFF7FEFF 		bl	HAL_GPIO_Init
+ 213              	.LVL4:
+ 112:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 214              		.loc 1 112 5 is_stmt 1 view .LVU55
+ 112:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 215              		.loc 1 112 25 is_stmt 0 view .LVU56
+ARM GAS  /tmp/ccF0g8wo.s 			page 8
+
+
+ 216 007a 0423     		movs	r3, #4
+ 217 007c 0793     		str	r3, [sp, #28]
+ 113:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 218              		.loc 1 113 5 is_stmt 1 view .LVU57
+ 113:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 219              		.loc 1 113 26 is_stmt 0 view .LVU58
+ 220 007e 0894     		str	r4, [sp, #32]
+ 114:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 221              		.loc 1 114 5 is_stmt 1 view .LVU59
+ 114:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 222              		.loc 1 114 26 is_stmt 0 view .LVU60
+ 223 0080 0025     		movs	r5, #0
+ 224 0082 0995     		str	r5, [sp, #36]
+ 115:Src/stm32f7xx_hal_msp.c **** 
+ 225              		.loc 1 115 5 is_stmt 1 view .LVU61
+ 226 0084 07A9     		add	r1, sp, #28
+ 227 0086 1F48     		ldr	r0, .L11+16
+ 228 0088 FFF7FEFF 		bl	HAL_GPIO_Init
+ 229              	.LVL5:
+ 117:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 230              		.loc 1 117 5 view .LVU62
+ 117:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 231              		.loc 1 117 25 is_stmt 0 view .LVU63
+ 232 008c 0794     		str	r4, [sp, #28]
+ 118:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 233              		.loc 1 118 5 is_stmt 1 view .LVU64
+ 118:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 234              		.loc 1 118 26 is_stmt 0 view .LVU65
+ 235 008e 0894     		str	r4, [sp, #32]
+ 119:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 236              		.loc 1 119 5 is_stmt 1 view .LVU66
+ 119:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 237              		.loc 1 119 26 is_stmt 0 view .LVU67
+ 238 0090 0995     		str	r5, [sp, #36]
+ 120:Src/stm32f7xx_hal_msp.c **** 
+ 239              		.loc 1 120 5 is_stmt 1 view .LVU68
+ 240 0092 07A9     		add	r1, sp, #28
+ 241 0094 1C48     		ldr	r0, .L11+20
+ 242 0096 FFF7FEFF 		bl	HAL_GPIO_Init
+ 243              	.LVL6:
+ 123:Src/stm32f7xx_hal_msp.c ****     HAL_NVIC_EnableIRQ(ADC_IRQn);
+ 244              		.loc 1 123 5 view .LVU69
+ 245 009a 2A46     		mov	r2, r5
+ 246 009c 2946     		mov	r1, r5
+ 247 009e 1220     		movs	r0, #18
+ 248 00a0 FFF7FEFF 		bl	HAL_NVIC_SetPriority
+ 249              	.LVL7:
+ 124:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC1_MspInit 1 */
+ 250              		.loc 1 124 5 view .LVU70
+ 251 00a4 1220     		movs	r0, #18
+ 252 00a6 FFF7FEFF 		bl	HAL_NVIC_EnableIRQ
+ 253              	.LVL8:
+ 254 00aa B8E7     		b	.L5
+ 255              	.LVL9:
+ 256              	.L10:
+ 135:Src/stm32f7xx_hal_msp.c **** 
+ 257              		.loc 1 135 5 view .LVU71
+ARM GAS  /tmp/ccF0g8wo.s 			page 9
+
+
+ 258              	.LBB8:
+ 135:Src/stm32f7xx_hal_msp.c **** 
+ 259              		.loc 1 135 5 view .LVU72
+ 135:Src/stm32f7xx_hal_msp.c **** 
+ 260              		.loc 1 135 5 view .LVU73
+ 261 00ac 134B     		ldr	r3, .L11+8
+ 262 00ae 5A6C     		ldr	r2, [r3, #68]
+ 263 00b0 42F48062 		orr	r2, r2, #1024
+ 264 00b4 5A64     		str	r2, [r3, #68]
+ 135:Src/stm32f7xx_hal_msp.c **** 
+ 265              		.loc 1 135 5 view .LVU74
+ 266 00b6 5A6C     		ldr	r2, [r3, #68]
+ 267 00b8 02F48062 		and	r2, r2, #1024
+ 268 00bc 0592     		str	r2, [sp, #20]
+ 135:Src/stm32f7xx_hal_msp.c **** 
+ 269              		.loc 1 135 5 view .LVU75
+ 270 00be 059A     		ldr	r2, [sp, #20]
+ 271              	.LBE8:
+ 135:Src/stm32f7xx_hal_msp.c **** 
+ 272              		.loc 1 135 5 view .LVU76
+ 137:Src/stm32f7xx_hal_msp.c ****     /**ADC3 GPIO Configuration
+ 273              		.loc 1 137 5 view .LVU77
+ 274              	.LBB9:
+ 137:Src/stm32f7xx_hal_msp.c ****     /**ADC3 GPIO Configuration
+ 275              		.loc 1 137 5 view .LVU78
+ 137:Src/stm32f7xx_hal_msp.c ****     /**ADC3 GPIO Configuration
+ 276              		.loc 1 137 5 view .LVU79
+ 277 00c0 1A6B     		ldr	r2, [r3, #48]
+ 278 00c2 42F02002 		orr	r2, r2, #32
+ 279 00c6 1A63     		str	r2, [r3, #48]
+ 137:Src/stm32f7xx_hal_msp.c ****     /**ADC3 GPIO Configuration
+ 280              		.loc 1 137 5 view .LVU80
+ 281 00c8 1B6B     		ldr	r3, [r3, #48]
+ 282 00ca 03F02003 		and	r3, r3, #32
+ 283 00ce 0693     		str	r3, [sp, #24]
+ 137:Src/stm32f7xx_hal_msp.c ****     /**ADC3 GPIO Configuration
+ 284              		.loc 1 137 5 view .LVU81
+ 285 00d0 069B     		ldr	r3, [sp, #24]
+ 286              	.LBE9:
+ 137:Src/stm32f7xx_hal_msp.c ****     /**ADC3 GPIO Configuration
+ 287              		.loc 1 137 5 view .LVU82
+ 141:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 288              		.loc 1 141 5 view .LVU83
+ 141:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 289              		.loc 1 141 25 is_stmt 0 view .LVU84
+ 290 00d2 2023     		movs	r3, #32
+ 291 00d4 0793     		str	r3, [sp, #28]
+ 142:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 292              		.loc 1 142 5 is_stmt 1 view .LVU85
+ 142:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 293              		.loc 1 142 26 is_stmt 0 view .LVU86
+ 294 00d6 0323     		movs	r3, #3
+ 295 00d8 0893     		str	r3, [sp, #32]
+ 143:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 296              		.loc 1 143 5 is_stmt 1 view .LVU87
+ 144:Src/stm32f7xx_hal_msp.c **** 
+ 297              		.loc 1 144 5 view .LVU88
+ARM GAS  /tmp/ccF0g8wo.s 			page 10
+
+
+ 298 00da 07A9     		add	r1, sp, #28
+ 299 00dc 0B48     		ldr	r0, .L11+24
+ 300              	.LVL10:
+ 144:Src/stm32f7xx_hal_msp.c **** 
+ 301              		.loc 1 144 5 is_stmt 0 view .LVU89
+ 302 00de FFF7FEFF 		bl	HAL_GPIO_Init
+ 303              	.LVL11:
+ 147:Src/stm32f7xx_hal_msp.c ****     HAL_NVIC_EnableIRQ(ADC_IRQn);
+ 304              		.loc 1 147 5 is_stmt 1 view .LVU90
+ 305 00e2 0022     		movs	r2, #0
+ 306 00e4 1146     		mov	r1, r2
+ 307 00e6 1220     		movs	r0, #18
+ 308 00e8 FFF7FEFF 		bl	HAL_NVIC_SetPriority
+ 309              	.LVL12:
+ 148:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC3_MspInit 1 */
+ 310              		.loc 1 148 5 view .LVU91
+ 311 00ec 1220     		movs	r0, #18
+ 312 00ee FFF7FEFF 		bl	HAL_NVIC_EnableIRQ
+ 313              	.LVL13:
+ 314              		.loc 1 154 1 is_stmt 0 view .LVU92
+ 315 00f2 94E7     		b	.L5
+ 316              	.L12:
+ 317              		.align	2
+ 318              	.L11:
+ 319 00f4 00200140 		.word	1073815552
+ 320 00f8 00220140 		.word	1073816064
+ 321 00fc 00380240 		.word	1073887232
+ 322 0100 00080240 		.word	1073874944
+ 323 0104 00000240 		.word	1073872896
+ 324 0108 00040240 		.word	1073873920
+ 325 010c 00140240 		.word	1073878016
+ 326              		.cfi_endproc
+ 327              	.LFE1184:
+ 329              		.section	.text.HAL_ADC_MspDeInit,"ax",%progbits
+ 330              		.align	1
+ 331              		.global	HAL_ADC_MspDeInit
+ 332              		.syntax unified
+ 333              		.thumb
+ 334              		.thumb_func
+ 335              		.fpu fpv5-d16
+ 337              	HAL_ADC_MspDeInit:
+ 338              	.LVL14:
+ 339              	.LFB1185:
+ 155:Src/stm32f7xx_hal_msp.c **** 
+ 156:Src/stm32f7xx_hal_msp.c **** /**
+ 157:Src/stm32f7xx_hal_msp.c **** * @brief ADC MSP De-Initialization
+ 158:Src/stm32f7xx_hal_msp.c **** * This function freeze the hardware resources used in this example
+ 159:Src/stm32f7xx_hal_msp.c **** * @param hadc: ADC handle pointer
+ 160:Src/stm32f7xx_hal_msp.c **** * @retval None
+ 161:Src/stm32f7xx_hal_msp.c **** */
+ 162:Src/stm32f7xx_hal_msp.c **** void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+ 163:Src/stm32f7xx_hal_msp.c **** {
+ 340              		.loc 1 163 1 is_stmt 1 view -0
+ 341              		.cfi_startproc
+ 342              		@ args = 0, pretend = 0, frame = 0
+ 343              		@ frame_needed = 0, uses_anonymous_args = 0
+ 344              		.loc 1 163 1 is_stmt 0 view .LVU94
+ARM GAS  /tmp/ccF0g8wo.s 			page 11
+
+
+ 345 0000 08B5     		push	{r3, lr}
+ 346              	.LCFI6:
+ 347              		.cfi_def_cfa_offset 8
+ 348              		.cfi_offset 3, -8
+ 349              		.cfi_offset 14, -4
+ 164:Src/stm32f7xx_hal_msp.c ****   if(hadc->Instance==ADC1)
+ 350              		.loc 1 164 3 is_stmt 1 view .LVU95
+ 351              		.loc 1 164 10 is_stmt 0 view .LVU96
+ 352 0002 0368     		ldr	r3, [r0]
+ 353              		.loc 1 164 5 view .LVU97
+ 354 0004 124A     		ldr	r2, .L19
+ 355 0006 9342     		cmp	r3, r2
+ 356 0008 03D0     		beq	.L17
+ 165:Src/stm32f7xx_hal_msp.c ****   {
+ 166:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC1_MspDeInit 0 */
+ 167:Src/stm32f7xx_hal_msp.c **** 
+ 168:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END ADC1_MspDeInit 0 */
+ 169:Src/stm32f7xx_hal_msp.c ****     /* Peripheral clock disable */
+ 170:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_ADC1_CLK_DISABLE();
+ 171:Src/stm32f7xx_hal_msp.c **** 
+ 172:Src/stm32f7xx_hal_msp.c ****     /**ADC1 GPIO Configuration
+ 173:Src/stm32f7xx_hal_msp.c ****     PC0     ------> ADC1_IN10
+ 174:Src/stm32f7xx_hal_msp.c ****     PC1     ------> ADC1_IN11
+ 175:Src/stm32f7xx_hal_msp.c ****     PA2     ------> ADC1_IN2
+ 176:Src/stm32f7xx_hal_msp.c ****     PB0     ------> ADC1_IN8
+ 177:Src/stm32f7xx_hal_msp.c ****     PB1     ------> ADC1_IN9
+ 178:Src/stm32f7xx_hal_msp.c ****     */
+ 179:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_1);
+ 180:Src/stm32f7xx_hal_msp.c **** 
+ 181:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2);
+ 182:Src/stm32f7xx_hal_msp.c **** 
+ 183:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1);
+ 184:Src/stm32f7xx_hal_msp.c **** 
+ 185:Src/stm32f7xx_hal_msp.c ****     /* ADC1 interrupt DeInit */
+ 186:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC1:ADC_IRQn disable */
+ 187:Src/stm32f7xx_hal_msp.c ****     /**
+ 188:Src/stm32f7xx_hal_msp.c ****     * Uncomment the line below to disable the "ADC_IRQn" interrupt
+ 189:Src/stm32f7xx_hal_msp.c ****     * Be aware, disabling shared interrupt may affect other IPs
+ 190:Src/stm32f7xx_hal_msp.c ****     */
+ 191:Src/stm32f7xx_hal_msp.c ****     /* HAL_NVIC_DisableIRQ(ADC_IRQn); */
+ 192:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END ADC1:ADC_IRQn disable */
+ 193:Src/stm32f7xx_hal_msp.c **** 
+ 194:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC1_MspDeInit 1 */
+ 195:Src/stm32f7xx_hal_msp.c **** 
+ 196:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END ADC1_MspDeInit 1 */
+ 197:Src/stm32f7xx_hal_msp.c ****   }
+ 198:Src/stm32f7xx_hal_msp.c ****   else if(hadc->Instance==ADC3)
+ 357              		.loc 1 198 8 is_stmt 1 view .LVU98
+ 358              		.loc 1 198 10 is_stmt 0 view .LVU99
+ 359 000a 124A     		ldr	r2, .L19+4
+ 360 000c 9342     		cmp	r3, r2
+ 361 000e 13D0     		beq	.L18
+ 362              	.LVL15:
+ 363              	.L13:
+ 199:Src/stm32f7xx_hal_msp.c ****   {
+ 200:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC3_MspDeInit 0 */
+ 201:Src/stm32f7xx_hal_msp.c **** 
+ARM GAS  /tmp/ccF0g8wo.s 			page 12
+
+
+ 202:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END ADC3_MspDeInit 0 */
+ 203:Src/stm32f7xx_hal_msp.c ****     /* Peripheral clock disable */
+ 204:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_ADC3_CLK_DISABLE();
+ 205:Src/stm32f7xx_hal_msp.c **** 
+ 206:Src/stm32f7xx_hal_msp.c ****     /**ADC3 GPIO Configuration
+ 207:Src/stm32f7xx_hal_msp.c ****     PF5     ------> ADC3_IN15
+ 208:Src/stm32f7xx_hal_msp.c ****     */
+ 209:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOF, GPIO_PIN_5);
+ 210:Src/stm32f7xx_hal_msp.c **** 
+ 211:Src/stm32f7xx_hal_msp.c ****     /* ADC3 interrupt DeInit */
+ 212:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC3:ADC_IRQn disable */
+ 213:Src/stm32f7xx_hal_msp.c ****     /**
+ 214:Src/stm32f7xx_hal_msp.c ****     * Uncomment the line below to disable the "ADC_IRQn" interrupt
+ 215:Src/stm32f7xx_hal_msp.c ****     * Be aware, disabling shared interrupt may affect other IPs
+ 216:Src/stm32f7xx_hal_msp.c ****     */
+ 217:Src/stm32f7xx_hal_msp.c ****     /* HAL_NVIC_DisableIRQ(ADC_IRQn); */
+ 218:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END ADC3:ADC_IRQn disable */
+ 219:Src/stm32f7xx_hal_msp.c **** 
+ 220:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN ADC3_MspDeInit 1 */
+ 221:Src/stm32f7xx_hal_msp.c **** 
+ 222:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END ADC3_MspDeInit 1 */
+ 223:Src/stm32f7xx_hal_msp.c ****   }
+ 224:Src/stm32f7xx_hal_msp.c **** 
+ 225:Src/stm32f7xx_hal_msp.c **** }
+ 364              		.loc 1 225 1 view .LVU100
+ 365 0010 08BD     		pop	{r3, pc}
+ 366              	.LVL16:
+ 367              	.L17:
+ 170:Src/stm32f7xx_hal_msp.c **** 
+ 368              		.loc 1 170 5 is_stmt 1 view .LVU101
+ 369 0012 02F58C32 		add	r2, r2, #71680
+ 370 0016 536C     		ldr	r3, [r2, #68]
+ 371 0018 23F48073 		bic	r3, r3, #256
+ 372 001c 5364     		str	r3, [r2, #68]
+ 179:Src/stm32f7xx_hal_msp.c **** 
+ 373              		.loc 1 179 5 view .LVU102
+ 374 001e 0321     		movs	r1, #3
+ 375 0020 0D48     		ldr	r0, .L19+8
+ 376              	.LVL17:
+ 179:Src/stm32f7xx_hal_msp.c **** 
+ 377              		.loc 1 179 5 is_stmt 0 view .LVU103
+ 378 0022 FFF7FEFF 		bl	HAL_GPIO_DeInit
+ 379              	.LVL18:
+ 181:Src/stm32f7xx_hal_msp.c **** 
+ 380              		.loc 1 181 5 is_stmt 1 view .LVU104
+ 381 0026 0421     		movs	r1, #4
+ 382 0028 0C48     		ldr	r0, .L19+12
+ 383 002a FFF7FEFF 		bl	HAL_GPIO_DeInit
+ 384              	.LVL19:
+ 183:Src/stm32f7xx_hal_msp.c **** 
+ 385              		.loc 1 183 5 view .LVU105
+ 386 002e 0321     		movs	r1, #3
+ 387 0030 0B48     		ldr	r0, .L19+16
+ 388 0032 FFF7FEFF 		bl	HAL_GPIO_DeInit
+ 389              	.LVL20:
+ 390 0036 EBE7     		b	.L13
+ 391              	.LVL21:
+ARM GAS  /tmp/ccF0g8wo.s 			page 13
+
+
+ 392              	.L18:
+ 204:Src/stm32f7xx_hal_msp.c **** 
+ 393              		.loc 1 204 5 view .LVU106
+ 394 0038 02F58B32 		add	r2, r2, #71168
+ 395 003c 536C     		ldr	r3, [r2, #68]
+ 396 003e 23F48063 		bic	r3, r3, #1024
+ 397 0042 5364     		str	r3, [r2, #68]
+ 209:Src/stm32f7xx_hal_msp.c **** 
+ 398              		.loc 1 209 5 view .LVU107
+ 399 0044 2021     		movs	r1, #32
+ 400 0046 0748     		ldr	r0, .L19+20
+ 401              	.LVL22:
+ 209:Src/stm32f7xx_hal_msp.c **** 
+ 402              		.loc 1 209 5 is_stmt 0 view .LVU108
+ 403 0048 FFF7FEFF 		bl	HAL_GPIO_DeInit
+ 404              	.LVL23:
+ 405              		.loc 1 225 1 view .LVU109
+ 406 004c E0E7     		b	.L13
+ 407              	.L20:
+ 408 004e 00BF     		.align	2
+ 409              	.L19:
+ 410 0050 00200140 		.word	1073815552
+ 411 0054 00220140 		.word	1073816064
+ 412 0058 00080240 		.word	1073874944
+ 413 005c 00000240 		.word	1073872896
+ 414 0060 00040240 		.word	1073873920
+ 415 0064 00140240 		.word	1073878016
+ 416              		.cfi_endproc
+ 417              	.LFE1185:
+ 419              		.section	.text.HAL_SD_MspInit,"ax",%progbits
+ 420              		.align	1
+ 421              		.global	HAL_SD_MspInit
+ 422              		.syntax unified
+ 423              		.thumb
+ 424              		.thumb_func
+ 425              		.fpu fpv5-d16
+ 427              	HAL_SD_MspInit:
+ 428              	.LVL24:
+ 429              	.LFB1186:
+ 226:Src/stm32f7xx_hal_msp.c **** 
+ 227:Src/stm32f7xx_hal_msp.c **** /**
+ 228:Src/stm32f7xx_hal_msp.c **** * @brief SD MSP Initialization
+ 229:Src/stm32f7xx_hal_msp.c **** * This function configures the hardware resources used in this example
+ 230:Src/stm32f7xx_hal_msp.c **** * @param hsd: SD handle pointer
+ 231:Src/stm32f7xx_hal_msp.c **** * @retval None
+ 232:Src/stm32f7xx_hal_msp.c **** */
+ 233:Src/stm32f7xx_hal_msp.c **** void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
+ 234:Src/stm32f7xx_hal_msp.c **** {
+ 430              		.loc 1 234 1 is_stmt 1 view -0
+ 431              		.cfi_startproc
+ 432              		@ args = 0, pretend = 0, frame = 176
+ 433              		@ frame_needed = 0, uses_anonymous_args = 0
+ 434              		.loc 1 234 1 is_stmt 0 view .LVU111
+ 435 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 436              	.LCFI7:
+ 437              		.cfi_def_cfa_offset 20
+ 438              		.cfi_offset 4, -20
+ARM GAS  /tmp/ccF0g8wo.s 			page 14
+
+
+ 439              		.cfi_offset 5, -16
+ 440              		.cfi_offset 6, -12
+ 441              		.cfi_offset 7, -8
+ 442              		.cfi_offset 14, -4
+ 443 0002 ADB0     		sub	sp, sp, #180
+ 444              	.LCFI8:
+ 445              		.cfi_def_cfa_offset 200
+ 446 0004 0446     		mov	r4, r0
+ 235:Src/stm32f7xx_hal_msp.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 447              		.loc 1 235 3 is_stmt 1 view .LVU112
+ 448              		.loc 1 235 20 is_stmt 0 view .LVU113
+ 449 0006 0021     		movs	r1, #0
+ 450 0008 2791     		str	r1, [sp, #156]
+ 451 000a 2891     		str	r1, [sp, #160]
+ 452 000c 2991     		str	r1, [sp, #164]
+ 453 000e 2A91     		str	r1, [sp, #168]
+ 454 0010 2B91     		str	r1, [sp, #172]
+ 236:Src/stm32f7xx_hal_msp.c ****   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 455              		.loc 1 236 3 is_stmt 1 view .LVU114
+ 456              		.loc 1 236 28 is_stmt 0 view .LVU115
+ 457 0012 9022     		movs	r2, #144
+ 458 0014 03A8     		add	r0, sp, #12
+ 459              	.LVL25:
+ 460              		.loc 1 236 28 view .LVU116
+ 461 0016 FFF7FEFF 		bl	memset
+ 462              	.LVL26:
+ 237:Src/stm32f7xx_hal_msp.c ****   if(hsd->Instance==SDMMC1)
+ 463              		.loc 1 237 3 is_stmt 1 view .LVU117
+ 464              		.loc 1 237 9 is_stmt 0 view .LVU118
+ 465 001a 2268     		ldr	r2, [r4]
+ 466              		.loc 1 237 5 view .LVU119
+ 467 001c 224B     		ldr	r3, .L27
+ 468 001e 9A42     		cmp	r2, r3
+ 469 0020 01D0     		beq	.L25
+ 470              	.LVL27:
+ 471              	.L21:
+ 238:Src/stm32f7xx_hal_msp.c ****   {
+ 239:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN SDMMC1_MspInit 0 */
+ 240:Src/stm32f7xx_hal_msp.c **** 
+ 241:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END SDMMC1_MspInit 0 */
+ 242:Src/stm32f7xx_hal_msp.c **** 
+ 243:Src/stm32f7xx_hal_msp.c ****   /** Initializes the peripherals clock
+ 244:Src/stm32f7xx_hal_msp.c ****   */
+ 245:Src/stm32f7xx_hal_msp.c ****     PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_CLK48;
+ 246:Src/stm32f7xx_hal_msp.c ****     PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+ 247:Src/stm32f7xx_hal_msp.c ****     PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48;
+ 248:Src/stm32f7xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 249:Src/stm32f7xx_hal_msp.c ****     {
+ 250:Src/stm32f7xx_hal_msp.c ****       Error_Handler();
+ 251:Src/stm32f7xx_hal_msp.c ****     }
+ 252:Src/stm32f7xx_hal_msp.c **** 
+ 253:Src/stm32f7xx_hal_msp.c ****     /* Peripheral clock enable */
+ 254:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_SDMMC1_CLK_ENABLE();
+ 255:Src/stm32f7xx_hal_msp.c **** 
+ 256:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOC_CLK_ENABLE();
+ 257:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOD_CLK_ENABLE();
+ 258:Src/stm32f7xx_hal_msp.c ****     /**SDMMC1 GPIO Configuration
+ARM GAS  /tmp/ccF0g8wo.s 			page 15
+
+
+ 259:Src/stm32f7xx_hal_msp.c ****     PC8     ------> SDMMC1_D0
+ 260:Src/stm32f7xx_hal_msp.c ****     PC9     ------> SDMMC1_D1
+ 261:Src/stm32f7xx_hal_msp.c ****     PC10     ------> SDMMC1_D2
+ 262:Src/stm32f7xx_hal_msp.c ****     PC11     ------> SDMMC1_D3
+ 263:Src/stm32f7xx_hal_msp.c ****     PC12     ------> SDMMC1_CK
+ 264:Src/stm32f7xx_hal_msp.c ****     PD2     ------> SDMMC1_CMD
+ 265:Src/stm32f7xx_hal_msp.c ****     */
+ 266:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
+ 267:Src/stm32f7xx_hal_msp.c ****                           |GPIO_PIN_12;
+ 268:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 269:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 270:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 271:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+ 272:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 273:Src/stm32f7xx_hal_msp.c **** 
+ 274:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_2;
+ 275:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 276:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 277:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 278:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+ 279:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 280:Src/stm32f7xx_hal_msp.c **** 
+ 281:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN SDMMC1_MspInit 1 */
+ 282:Src/stm32f7xx_hal_msp.c **** 
+ 283:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END SDMMC1_MspInit 1 */
+ 284:Src/stm32f7xx_hal_msp.c ****   }
+ 285:Src/stm32f7xx_hal_msp.c **** 
+ 286:Src/stm32f7xx_hal_msp.c **** }
+ 472              		.loc 1 286 1 view .LVU120
+ 473 0022 2DB0     		add	sp, sp, #180
+ 474              	.LCFI9:
+ 475              		.cfi_remember_state
+ 476              		.cfi_def_cfa_offset 20
+ 477              		@ sp needed
+ 478 0024 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 479              	.LVL28:
+ 480              	.L25:
+ 481              	.LCFI10:
+ 482              		.cfi_restore_state
+ 245:Src/stm32f7xx_hal_msp.c ****     PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+ 483              		.loc 1 245 5 is_stmt 1 view .LVU121
+ 245:Src/stm32f7xx_hal_msp.c ****     PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+ 484              		.loc 1 245 46 is_stmt 0 view .LVU122
+ 485 0026 4FF42003 		mov	r3, #10485760
+ 486 002a 0393     		str	r3, [sp, #12]
+ 246:Src/stm32f7xx_hal_msp.c ****     PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48;
+ 487              		.loc 1 246 5 is_stmt 1 view .LVU123
+ 247:Src/stm32f7xx_hal_msp.c ****     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 488              		.loc 1 247 5 view .LVU124
+ 248:Src/stm32f7xx_hal_msp.c ****     {
+ 489              		.loc 1 248 5 view .LVU125
+ 248:Src/stm32f7xx_hal_msp.c ****     {
+ 490              		.loc 1 248 9 is_stmt 0 view .LVU126
+ 491 002c 03A8     		add	r0, sp, #12
+ 492 002e FFF7FEFF 		bl	HAL_RCCEx_PeriphCLKConfig
+ 493              	.LVL29:
+ 248:Src/stm32f7xx_hal_msp.c ****     {
+ARM GAS  /tmp/ccF0g8wo.s 			page 16
+
+
+ 494              		.loc 1 248 8 view .LVU127
+ 495 0032 0028     		cmp	r0, #0
+ 496 0034 35D1     		bne	.L26
+ 497              	.L23:
+ 254:Src/stm32f7xx_hal_msp.c **** 
+ 498              		.loc 1 254 5 is_stmt 1 view .LVU128
+ 499              	.LBB10:
+ 254:Src/stm32f7xx_hal_msp.c **** 
+ 500              		.loc 1 254 5 view .LVU129
+ 254:Src/stm32f7xx_hal_msp.c **** 
+ 501              		.loc 1 254 5 view .LVU130
+ 502 0036 1D4B     		ldr	r3, .L27+4
+ 503 0038 5A6C     		ldr	r2, [r3, #68]
+ 504 003a 42F40062 		orr	r2, r2, #2048
+ 505 003e 5A64     		str	r2, [r3, #68]
+ 254:Src/stm32f7xx_hal_msp.c **** 
+ 506              		.loc 1 254 5 view .LVU131
+ 507 0040 5A6C     		ldr	r2, [r3, #68]
+ 508 0042 02F40062 		and	r2, r2, #2048
+ 509 0046 0092     		str	r2, [sp]
+ 254:Src/stm32f7xx_hal_msp.c **** 
+ 510              		.loc 1 254 5 view .LVU132
+ 511 0048 009A     		ldr	r2, [sp]
+ 512              	.LBE10:
+ 254:Src/stm32f7xx_hal_msp.c **** 
+ 513              		.loc 1 254 5 view .LVU133
+ 256:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOD_CLK_ENABLE();
+ 514              		.loc 1 256 5 view .LVU134
+ 515              	.LBB11:
+ 256:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOD_CLK_ENABLE();
+ 516              		.loc 1 256 5 view .LVU135
+ 256:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOD_CLK_ENABLE();
+ 517              		.loc 1 256 5 view .LVU136
+ 518 004a 1A6B     		ldr	r2, [r3, #48]
+ 519 004c 42F00402 		orr	r2, r2, #4
+ 520 0050 1A63     		str	r2, [r3, #48]
+ 256:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOD_CLK_ENABLE();
+ 521              		.loc 1 256 5 view .LVU137
+ 522 0052 1A6B     		ldr	r2, [r3, #48]
+ 523 0054 02F00402 		and	r2, r2, #4
+ 524 0058 0192     		str	r2, [sp, #4]
+ 256:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOD_CLK_ENABLE();
+ 525              		.loc 1 256 5 view .LVU138
+ 526 005a 019A     		ldr	r2, [sp, #4]
+ 527              	.LBE11:
+ 256:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_GPIOD_CLK_ENABLE();
+ 528              		.loc 1 256 5 view .LVU139
+ 257:Src/stm32f7xx_hal_msp.c ****     /**SDMMC1 GPIO Configuration
+ 529              		.loc 1 257 5 view .LVU140
+ 530              	.LBB12:
+ 257:Src/stm32f7xx_hal_msp.c ****     /**SDMMC1 GPIO Configuration
+ 531              		.loc 1 257 5 view .LVU141
+ 257:Src/stm32f7xx_hal_msp.c ****     /**SDMMC1 GPIO Configuration
+ 532              		.loc 1 257 5 view .LVU142
+ 533 005c 1A6B     		ldr	r2, [r3, #48]
+ 534 005e 42F00802 		orr	r2, r2, #8
+ 535 0062 1A63     		str	r2, [r3, #48]
+ARM GAS  /tmp/ccF0g8wo.s 			page 17
+
+
+ 257:Src/stm32f7xx_hal_msp.c ****     /**SDMMC1 GPIO Configuration
+ 536              		.loc 1 257 5 view .LVU143
+ 537 0064 1B6B     		ldr	r3, [r3, #48]
+ 538 0066 03F00803 		and	r3, r3, #8
+ 539 006a 0293     		str	r3, [sp, #8]
+ 257:Src/stm32f7xx_hal_msp.c ****     /**SDMMC1 GPIO Configuration
+ 540              		.loc 1 257 5 view .LVU144
+ 541 006c 029B     		ldr	r3, [sp, #8]
+ 542              	.LBE12:
+ 257:Src/stm32f7xx_hal_msp.c ****     /**SDMMC1 GPIO Configuration
+ 543              		.loc 1 257 5 view .LVU145
+ 266:Src/stm32f7xx_hal_msp.c ****                           |GPIO_PIN_12;
+ 544              		.loc 1 266 5 view .LVU146
+ 266:Src/stm32f7xx_hal_msp.c ****                           |GPIO_PIN_12;
+ 545              		.loc 1 266 25 is_stmt 0 view .LVU147
+ 546 006e 4FF4F853 		mov	r3, #7936
+ 547 0072 2793     		str	r3, [sp, #156]
+ 268:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 548              		.loc 1 268 5 is_stmt 1 view .LVU148
+ 268:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 549              		.loc 1 268 26 is_stmt 0 view .LVU149
+ 550 0074 0227     		movs	r7, #2
+ 551 0076 2897     		str	r7, [sp, #160]
+ 269:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 552              		.loc 1 269 5 is_stmt 1 view .LVU150
+ 269:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 553              		.loc 1 269 26 is_stmt 0 view .LVU151
+ 554 0078 0026     		movs	r6, #0
+ 555 007a 2996     		str	r6, [sp, #164]
+ 270:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+ 556              		.loc 1 270 5 is_stmt 1 view .LVU152
+ 270:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+ 557              		.loc 1 270 27 is_stmt 0 view .LVU153
+ 558 007c 0325     		movs	r5, #3
+ 559 007e 2A95     		str	r5, [sp, #168]
+ 271:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 560              		.loc 1 271 5 is_stmt 1 view .LVU154
+ 271:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 561              		.loc 1 271 31 is_stmt 0 view .LVU155
+ 562 0080 0C24     		movs	r4, #12
+ 563              	.LVL30:
+ 271:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 564              		.loc 1 271 31 view .LVU156
+ 565 0082 2B94     		str	r4, [sp, #172]
+ 272:Src/stm32f7xx_hal_msp.c **** 
+ 566              		.loc 1 272 5 is_stmt 1 view .LVU157
+ 567 0084 27A9     		add	r1, sp, #156
+ 568 0086 0A48     		ldr	r0, .L27+8
+ 569 0088 FFF7FEFF 		bl	HAL_GPIO_Init
+ 570              	.LVL31:
+ 274:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 571              		.loc 1 274 5 view .LVU158
+ 274:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 572              		.loc 1 274 25 is_stmt 0 view .LVU159
+ 573 008c 0423     		movs	r3, #4
+ 574 008e 2793     		str	r3, [sp, #156]
+ 275:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ARM GAS  /tmp/ccF0g8wo.s 			page 18
+
+
+ 575              		.loc 1 275 5 is_stmt 1 view .LVU160
+ 275:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 576              		.loc 1 275 26 is_stmt 0 view .LVU161
+ 577 0090 2897     		str	r7, [sp, #160]
+ 276:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 578              		.loc 1 276 5 is_stmt 1 view .LVU162
+ 276:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 579              		.loc 1 276 26 is_stmt 0 view .LVU163
+ 580 0092 2996     		str	r6, [sp, #164]
+ 277:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+ 581              		.loc 1 277 5 is_stmt 1 view .LVU164
+ 277:Src/stm32f7xx_hal_msp.c ****     GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+ 582              		.loc 1 277 27 is_stmt 0 view .LVU165
+ 583 0094 2A95     		str	r5, [sp, #168]
+ 278:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 584              		.loc 1 278 5 is_stmt 1 view .LVU166
+ 278:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 585              		.loc 1 278 31 is_stmt 0 view .LVU167
+ 586 0096 2B94     		str	r4, [sp, #172]
+ 279:Src/stm32f7xx_hal_msp.c **** 
+ 587              		.loc 1 279 5 is_stmt 1 view .LVU168
+ 588 0098 27A9     		add	r1, sp, #156
+ 589 009a 0648     		ldr	r0, .L27+12
+ 590 009c FFF7FEFF 		bl	HAL_GPIO_Init
+ 591              	.LVL32:
+ 592              		.loc 1 286 1 is_stmt 0 view .LVU169
+ 593 00a0 BFE7     		b	.L21
+ 594              	.LVL33:
+ 595              	.L26:
+ 250:Src/stm32f7xx_hal_msp.c ****     }
+ 596              		.loc 1 250 7 is_stmt 1 view .LVU170
+ 597 00a2 FFF7FEFF 		bl	Error_Handler
+ 598              	.LVL34:
+ 599 00a6 C6E7     		b	.L23
+ 600              	.L28:
+ 601              		.align	2
+ 602              	.L27:
+ 603 00a8 002C0140 		.word	1073818624
+ 604 00ac 00380240 		.word	1073887232
+ 605 00b0 00080240 		.word	1073874944
+ 606 00b4 000C0240 		.word	1073875968
+ 607              		.cfi_endproc
+ 608              	.LFE1186:
+ 610              		.section	.text.HAL_SD_MspDeInit,"ax",%progbits
+ 611              		.align	1
+ 612              		.global	HAL_SD_MspDeInit
+ 613              		.syntax unified
+ 614              		.thumb
+ 615              		.thumb_func
+ 616              		.fpu fpv5-d16
+ 618              	HAL_SD_MspDeInit:
+ 619              	.LVL35:
+ 620              	.LFB1187:
+ 287:Src/stm32f7xx_hal_msp.c **** 
+ 288:Src/stm32f7xx_hal_msp.c **** /**
+ 289:Src/stm32f7xx_hal_msp.c **** * @brief SD MSP De-Initialization
+ 290:Src/stm32f7xx_hal_msp.c **** * This function freeze the hardware resources used in this example
+ARM GAS  /tmp/ccF0g8wo.s 			page 19
+
+
+ 291:Src/stm32f7xx_hal_msp.c **** * @param hsd: SD handle pointer
+ 292:Src/stm32f7xx_hal_msp.c **** * @retval None
+ 293:Src/stm32f7xx_hal_msp.c **** */
+ 294:Src/stm32f7xx_hal_msp.c **** void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
+ 295:Src/stm32f7xx_hal_msp.c **** {
+ 621              		.loc 1 295 1 view -0
+ 622              		.cfi_startproc
+ 623              		@ args = 0, pretend = 0, frame = 0
+ 624              		@ frame_needed = 0, uses_anonymous_args = 0
+ 625              		.loc 1 295 1 is_stmt 0 view .LVU172
+ 626 0000 08B5     		push	{r3, lr}
+ 627              	.LCFI11:
+ 628              		.cfi_def_cfa_offset 8
+ 629              		.cfi_offset 3, -8
+ 630              		.cfi_offset 14, -4
+ 296:Src/stm32f7xx_hal_msp.c ****   if(hsd->Instance==SDMMC1)
+ 631              		.loc 1 296 3 is_stmt 1 view .LVU173
+ 632              		.loc 1 296 9 is_stmt 0 view .LVU174
+ 633 0002 0268     		ldr	r2, [r0]
+ 634              		.loc 1 296 5 view .LVU175
+ 635 0004 094B     		ldr	r3, .L33
+ 636 0006 9A42     		cmp	r2, r3
+ 637 0008 00D0     		beq	.L32
+ 638              	.LVL36:
+ 639              	.L29:
+ 297:Src/stm32f7xx_hal_msp.c ****   {
+ 298:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN SDMMC1_MspDeInit 0 */
+ 299:Src/stm32f7xx_hal_msp.c **** 
+ 300:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END SDMMC1_MspDeInit 0 */
+ 301:Src/stm32f7xx_hal_msp.c ****     /* Peripheral clock disable */
+ 302:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_SDMMC1_CLK_DISABLE();
+ 303:Src/stm32f7xx_hal_msp.c **** 
+ 304:Src/stm32f7xx_hal_msp.c ****     /**SDMMC1 GPIO Configuration
+ 305:Src/stm32f7xx_hal_msp.c ****     PC8     ------> SDMMC1_D0
+ 306:Src/stm32f7xx_hal_msp.c ****     PC9     ------> SDMMC1_D1
+ 307:Src/stm32f7xx_hal_msp.c ****     PC10     ------> SDMMC1_D2
+ 308:Src/stm32f7xx_hal_msp.c ****     PC11     ------> SDMMC1_D3
+ 309:Src/stm32f7xx_hal_msp.c ****     PC12     ------> SDMMC1_CK
+ 310:Src/stm32f7xx_hal_msp.c ****     PD2     ------> SDMMC1_CMD
+ 311:Src/stm32f7xx_hal_msp.c ****     */
+ 312:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
+ 313:Src/stm32f7xx_hal_msp.c ****                           |GPIO_PIN_12);
+ 314:Src/stm32f7xx_hal_msp.c **** 
+ 315:Src/stm32f7xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
+ 316:Src/stm32f7xx_hal_msp.c **** 
+ 317:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN SDMMC1_MspDeInit 1 */
+ 318:Src/stm32f7xx_hal_msp.c **** 
+ 319:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END SDMMC1_MspDeInit 1 */
+ 320:Src/stm32f7xx_hal_msp.c ****   }
+ 321:Src/stm32f7xx_hal_msp.c **** 
+ 322:Src/stm32f7xx_hal_msp.c **** }
+ 640              		.loc 1 322 1 view .LVU176
+ 641 000a 08BD     		pop	{r3, pc}
+ 642              	.LVL37:
+ 643              	.L32:
+ 302:Src/stm32f7xx_hal_msp.c **** 
+ 644              		.loc 1 302 5 is_stmt 1 view .LVU177
+ARM GAS  /tmp/ccF0g8wo.s 			page 20
+
+
+ 645 000c 084A     		ldr	r2, .L33+4
+ 646 000e 536C     		ldr	r3, [r2, #68]
+ 647 0010 23F40063 		bic	r3, r3, #2048
+ 648 0014 5364     		str	r3, [r2, #68]
+ 312:Src/stm32f7xx_hal_msp.c ****                           |GPIO_PIN_12);
+ 649              		.loc 1 312 5 view .LVU178
+ 650 0016 4FF4F851 		mov	r1, #7936
+ 651 001a 0648     		ldr	r0, .L33+8
+ 652              	.LVL38:
+ 312:Src/stm32f7xx_hal_msp.c ****                           |GPIO_PIN_12);
+ 653              		.loc 1 312 5 is_stmt 0 view .LVU179
+ 654 001c FFF7FEFF 		bl	HAL_GPIO_DeInit
+ 655              	.LVL39:
+ 315:Src/stm32f7xx_hal_msp.c **** 
+ 656              		.loc 1 315 5 is_stmt 1 view .LVU180
+ 657 0020 0421     		movs	r1, #4
+ 658 0022 0548     		ldr	r0, .L33+12
+ 659 0024 FFF7FEFF 		bl	HAL_GPIO_DeInit
+ 660              	.LVL40:
+ 661              		.loc 1 322 1 is_stmt 0 view .LVU181
+ 662 0028 EFE7     		b	.L29
+ 663              	.L34:
+ 664 002a 00BF     		.align	2
+ 665              	.L33:
+ 666 002c 002C0140 		.word	1073818624
+ 667 0030 00380240 		.word	1073887232
+ 668 0034 00080240 		.word	1073874944
+ 669 0038 000C0240 		.word	1073875968
+ 670              		.cfi_endproc
+ 671              	.LFE1187:
+ 673              		.section	.text.HAL_TIM_Base_MspInit,"ax",%progbits
+ 674              		.align	1
+ 675              		.global	HAL_TIM_Base_MspInit
+ 676              		.syntax unified
+ 677              		.thumb
+ 678              		.thumb_func
+ 679              		.fpu fpv5-d16
+ 681              	HAL_TIM_Base_MspInit:
+ 682              	.LVL41:
+ 683              	.LFB1188:
+ 323:Src/stm32f7xx_hal_msp.c **** 
+ 324:Src/stm32f7xx_hal_msp.c **** /**
+ 325:Src/stm32f7xx_hal_msp.c **** * @brief TIM_Base MSP Initialization
+ 326:Src/stm32f7xx_hal_msp.c **** * This function configures the hardware resources used in this example
+ 327:Src/stm32f7xx_hal_msp.c **** * @param htim_base: TIM_Base handle pointer
+ 328:Src/stm32f7xx_hal_msp.c **** * @retval None
+ 329:Src/stm32f7xx_hal_msp.c **** */
+ 330:Src/stm32f7xx_hal_msp.c **** void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+ 331:Src/stm32f7xx_hal_msp.c **** {
+ 684              		.loc 1 331 1 is_stmt 1 view -0
+ 685              		.cfi_startproc
+ 686              		@ args = 0, pretend = 0, frame = 8
+ 687              		@ frame_needed = 0, uses_anonymous_args = 0
+ 332:Src/stm32f7xx_hal_msp.c ****   if(htim_base->Instance==TIM10)
+ 688              		.loc 1 332 3 view .LVU183
+ 689              		.loc 1 332 15 is_stmt 0 view .LVU184
+ 690 0000 0268     		ldr	r2, [r0]
+ARM GAS  /tmp/ccF0g8wo.s 			page 21
+
+
+ 691              		.loc 1 332 5 view .LVU185
+ 692 0002 0E4B     		ldr	r3, .L42
+ 693 0004 9A42     		cmp	r2, r3
+ 694 0006 00D0     		beq	.L41
+ 695 0008 7047     		bx	lr
+ 696              	.L41:
+ 331:Src/stm32f7xx_hal_msp.c ****   if(htim_base->Instance==TIM10)
+ 697              		.loc 1 331 1 view .LVU186
+ 698 000a 00B5     		push	{lr}
+ 699              	.LCFI12:
+ 700              		.cfi_def_cfa_offset 4
+ 701              		.cfi_offset 14, -4
+ 702 000c 83B0     		sub	sp, sp, #12
+ 703              	.LCFI13:
+ 704              		.cfi_def_cfa_offset 16
+ 333:Src/stm32f7xx_hal_msp.c ****   {
+ 334:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN TIM10_MspInit 0 */
+ 335:Src/stm32f7xx_hal_msp.c **** 
+ 336:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END TIM10_MspInit 0 */
+ 337:Src/stm32f7xx_hal_msp.c ****     /* Peripheral clock enable */
+ 338:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_TIM10_CLK_ENABLE();
+ 705              		.loc 1 338 5 is_stmt 1 view .LVU187
+ 706              	.LBB13:
+ 707              		.loc 1 338 5 view .LVU188
+ 708              		.loc 1 338 5 view .LVU189
+ 709 000e 03F57443 		add	r3, r3, #62464
+ 710 0012 5A6C     		ldr	r2, [r3, #68]
+ 711 0014 42F40032 		orr	r2, r2, #131072
+ 712 0018 5A64     		str	r2, [r3, #68]
+ 713              		.loc 1 338 5 view .LVU190
+ 714 001a 5B6C     		ldr	r3, [r3, #68]
+ 715 001c 03F40033 		and	r3, r3, #131072
+ 716 0020 0193     		str	r3, [sp, #4]
+ 717              		.loc 1 338 5 view .LVU191
+ 718 0022 019B     		ldr	r3, [sp, #4]
+ 719              	.LBE13:
+ 720              		.loc 1 338 5 view .LVU192
+ 339:Src/stm32f7xx_hal_msp.c ****     /* TIM10 interrupt Init */
+ 340:Src/stm32f7xx_hal_msp.c ****     HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 0, 0);
+ 721              		.loc 1 340 5 view .LVU193
+ 722 0024 0022     		movs	r2, #0
+ 723 0026 1146     		mov	r1, r2
+ 724 0028 1920     		movs	r0, #25
+ 725              	.LVL42:
+ 726              		.loc 1 340 5 is_stmt 0 view .LVU194
+ 727 002a FFF7FEFF 		bl	HAL_NVIC_SetPriority
+ 728              	.LVL43:
+ 341:Src/stm32f7xx_hal_msp.c ****     HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
+ 729              		.loc 1 341 5 is_stmt 1 view .LVU195
+ 730 002e 1920     		movs	r0, #25
+ 731 0030 FFF7FEFF 		bl	HAL_NVIC_EnableIRQ
+ 732              	.LVL44:
+ 342:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN TIM10_MspInit 1 */
+ 343:Src/stm32f7xx_hal_msp.c **** 
+ 344:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END TIM10_MspInit 1 */
+ 345:Src/stm32f7xx_hal_msp.c ****   }
+ 346:Src/stm32f7xx_hal_msp.c **** 
+ARM GAS  /tmp/ccF0g8wo.s 			page 22
+
+
+ 347:Src/stm32f7xx_hal_msp.c **** }
+ 733              		.loc 1 347 1 is_stmt 0 view .LVU196
+ 734 0034 03B0     		add	sp, sp, #12
+ 735              	.LCFI14:
+ 736              		.cfi_def_cfa_offset 4
+ 737              		@ sp needed
+ 738 0036 5DF804FB 		ldr	pc, [sp], #4
+ 739              	.L43:
+ 740 003a 00BF     		.align	2
+ 741              	.L42:
+ 742 003c 00440140 		.word	1073824768
+ 743              		.cfi_endproc
+ 744              	.LFE1188:
+ 746              		.section	.text.HAL_TIM_Base_MspDeInit,"ax",%progbits
+ 747              		.align	1
+ 748              		.global	HAL_TIM_Base_MspDeInit
+ 749              		.syntax unified
+ 750              		.thumb
+ 751              		.thumb_func
+ 752              		.fpu fpv5-d16
+ 754              	HAL_TIM_Base_MspDeInit:
+ 755              	.LVL45:
+ 756              	.LFB1189:
+ 348:Src/stm32f7xx_hal_msp.c **** 
+ 349:Src/stm32f7xx_hal_msp.c **** /**
+ 350:Src/stm32f7xx_hal_msp.c **** * @brief TIM_Base MSP De-Initialization
+ 351:Src/stm32f7xx_hal_msp.c **** * This function freeze the hardware resources used in this example
+ 352:Src/stm32f7xx_hal_msp.c **** * @param htim_base: TIM_Base handle pointer
+ 353:Src/stm32f7xx_hal_msp.c **** * @retval None
+ 354:Src/stm32f7xx_hal_msp.c **** */
+ 355:Src/stm32f7xx_hal_msp.c **** void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+ 356:Src/stm32f7xx_hal_msp.c **** {
+ 757              		.loc 1 356 1 is_stmt 1 view -0
+ 758              		.cfi_startproc
+ 759              		@ args = 0, pretend = 0, frame = 0
+ 760              		@ frame_needed = 0, uses_anonymous_args = 0
+ 761              		.loc 1 356 1 is_stmt 0 view .LVU198
+ 762 0000 08B5     		push	{r3, lr}
+ 763              	.LCFI15:
+ 764              		.cfi_def_cfa_offset 8
+ 765              		.cfi_offset 3, -8
+ 766              		.cfi_offset 14, -4
+ 357:Src/stm32f7xx_hal_msp.c ****   if(htim_base->Instance==TIM10)
+ 767              		.loc 1 357 3 is_stmt 1 view .LVU199
+ 768              		.loc 1 357 15 is_stmt 0 view .LVU200
+ 769 0002 0268     		ldr	r2, [r0]
+ 770              		.loc 1 357 5 view .LVU201
+ 771 0004 064B     		ldr	r3, .L48
+ 772 0006 9A42     		cmp	r2, r3
+ 773 0008 00D0     		beq	.L47
+ 774              	.LVL46:
+ 775              	.L44:
+ 358:Src/stm32f7xx_hal_msp.c ****   {
+ 359:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN TIM10_MspDeInit 0 */
+ 360:Src/stm32f7xx_hal_msp.c **** 
+ 361:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END TIM10_MspDeInit 0 */
+ 362:Src/stm32f7xx_hal_msp.c ****     /* Peripheral clock disable */
+ARM GAS  /tmp/ccF0g8wo.s 			page 23
+
+
+ 363:Src/stm32f7xx_hal_msp.c ****     __HAL_RCC_TIM10_CLK_DISABLE();
+ 364:Src/stm32f7xx_hal_msp.c **** 
+ 365:Src/stm32f7xx_hal_msp.c ****     /* TIM10 interrupt DeInit */
+ 366:Src/stm32f7xx_hal_msp.c ****     HAL_NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);
+ 367:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN TIM10_MspDeInit 1 */
+ 368:Src/stm32f7xx_hal_msp.c **** 
+ 369:Src/stm32f7xx_hal_msp.c ****   /* USER CODE END TIM10_MspDeInit 1 */
+ 370:Src/stm32f7xx_hal_msp.c ****   }
+ 371:Src/stm32f7xx_hal_msp.c **** 
+ 372:Src/stm32f7xx_hal_msp.c **** }
+ 776              		.loc 1 372 1 view .LVU202
+ 777 000a 08BD     		pop	{r3, pc}
+ 778              	.LVL47:
+ 779              	.L47:
+ 363:Src/stm32f7xx_hal_msp.c **** 
+ 780              		.loc 1 363 5 is_stmt 1 view .LVU203
+ 781 000c 054A     		ldr	r2, .L48+4
+ 782 000e 536C     		ldr	r3, [r2, #68]
+ 783 0010 23F40033 		bic	r3, r3, #131072
+ 784 0014 5364     		str	r3, [r2, #68]
+ 366:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN TIM10_MspDeInit 1 */
+ 785              		.loc 1 366 5 view .LVU204
+ 786 0016 1920     		movs	r0, #25
+ 787              	.LVL48:
+ 366:Src/stm32f7xx_hal_msp.c ****   /* USER CODE BEGIN TIM10_MspDeInit 1 */
+ 788              		.loc 1 366 5 is_stmt 0 view .LVU205
+ 789 0018 FFF7FEFF 		bl	HAL_NVIC_DisableIRQ
+ 790              	.LVL49:
+ 791              		.loc 1 372 1 view .LVU206
+ 792 001c F5E7     		b	.L44
+ 793              	.L49:
+ 794 001e 00BF     		.align	2
+ 795              	.L48:
+ 796 0020 00440140 		.word	1073824768
+ 797 0024 00380240 		.word	1073887232
+ 798              		.cfi_endproc
+ 799              	.LFE1189:
+ 801              		.text
+ 802              	.Letext0:
+ 803              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 804              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 805              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 806              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 807              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h"
+ 808              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h"
+ 809              		.file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 810              		.file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h"
+ 811              		.file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h"
+ 812              		.file 11 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h"
+ 813              		.file 12 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h"
+ 814              		.file 13 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h"
+ 815              		.file 14 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h"
+ 816              		.file 15 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+ 817              		.file 16 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h"
+ 818              		.file 17 "Inc/main.h"
+ 819              		.file 18 ""
+ARM GAS  /tmp/ccF0g8wo.s 			page 24
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_msp.c
+     /tmp/ccF0g8wo.s:17     .text.HAL_MspInit:0000000000000000 $t
+     /tmp/ccF0g8wo.s:25     .text.HAL_MspInit:0000000000000000 HAL_MspInit
+     /tmp/ccF0g8wo.s:76     .text.HAL_MspInit:000000000000002c $d
+     /tmp/ccF0g8wo.s:81     .text.HAL_ADC_MspInit:0000000000000000 $t
+     /tmp/ccF0g8wo.s:88     .text.HAL_ADC_MspInit:0000000000000000 HAL_ADC_MspInit
+     /tmp/ccF0g8wo.s:319    .text.HAL_ADC_MspInit:00000000000000f4 $d
+     /tmp/ccF0g8wo.s:330    .text.HAL_ADC_MspDeInit:0000000000000000 $t
+     /tmp/ccF0g8wo.s:337    .text.HAL_ADC_MspDeInit:0000000000000000 HAL_ADC_MspDeInit
+     /tmp/ccF0g8wo.s:410    .text.HAL_ADC_MspDeInit:0000000000000050 $d
+     /tmp/ccF0g8wo.s:420    .text.HAL_SD_MspInit:0000000000000000 $t
+     /tmp/ccF0g8wo.s:427    .text.HAL_SD_MspInit:0000000000000000 HAL_SD_MspInit
+     /tmp/ccF0g8wo.s:603    .text.HAL_SD_MspInit:00000000000000a8 $d
+     /tmp/ccF0g8wo.s:611    .text.HAL_SD_MspDeInit:0000000000000000 $t
+     /tmp/ccF0g8wo.s:618    .text.HAL_SD_MspDeInit:0000000000000000 HAL_SD_MspDeInit
+     /tmp/ccF0g8wo.s:666    .text.HAL_SD_MspDeInit:000000000000002c $d
+     /tmp/ccF0g8wo.s:674    .text.HAL_TIM_Base_MspInit:0000000000000000 $t
+     /tmp/ccF0g8wo.s:681    .text.HAL_TIM_Base_MspInit:0000000000000000 HAL_TIM_Base_MspInit
+     /tmp/ccF0g8wo.s:742    .text.HAL_TIM_Base_MspInit:000000000000003c $d
+     /tmp/ccF0g8wo.s:747    .text.HAL_TIM_Base_MspDeInit:0000000000000000 $t
+     /tmp/ccF0g8wo.s:754    .text.HAL_TIM_Base_MspDeInit:0000000000000000 HAL_TIM_Base_MspDeInit
+     /tmp/ccF0g8wo.s:796    .text.HAL_TIM_Base_MspDeInit:0000000000000020 $d
+
+UNDEFINED SYMBOLS
+HAL_GPIO_Init
+HAL_NVIC_SetPriority
+HAL_NVIC_EnableIRQ
+HAL_GPIO_DeInit
+memset
+HAL_RCCEx_PeriphCLKConfig
+Error_Handler
+HAL_NVIC_DisableIRQ
diff --git a/build/stm32f7xx_hal_msp.o b/build/stm32f7xx_hal_msp.o
new file mode 100644
index 0000000..4d41b08
Binary files /dev/null and b/build/stm32f7xx_hal_msp.o differ
diff --git a/build/stm32f7xx_hal_pwr.d b/build/stm32f7xx_hal_pwr.d
new file mode 100644
index 0000000..b5ea50f
--- /dev/null
+++ b/build/stm32f7xx_hal_pwr.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_pwr.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_pwr.lst b/build/stm32f7xx_hal_pwr.lst
new file mode 100644
index 0000000..333afef
--- /dev/null
+++ b/build/stm32f7xx_hal_pwr.lst
@@ -0,0 +1,2392 @@
+ARM GAS  /tmp/ccE9MXkV.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_pwr.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.HAL_PWR_DeInit,"ax",%progbits
+  17              		.align	1
+  18              		.global	HAL_PWR_DeInit
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	HAL_PWR_DeInit:
+  26              	.LFB141:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @file    stm32f7xx_hal_pwr.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief   PWR HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *          This file provides firmware functions to manage the following 
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *          functionalities of the Power Controller (PWR) peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           + Peripheral Control functions 
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   ******************************************************************************
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @attention
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * Copyright (c) 2017 STMicroelectronics.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * All rights reserved.
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * in the root directory of this software component.
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   ******************************************************************************
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #include "stm32f7xx_hal.h"
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @{
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR PWR
+ARM GAS  /tmp/ccE9MXkV.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief PWR HAL module driver
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @{
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @addtogroup PWR_Private_Constants
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @{
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 	
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @{
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */     
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #define PVD_MODE_IT               ((uint32_t)0x00010000U)
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #define PVD_MODE_EVT              ((uint32_t)0x00020000U)
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #define PVD_RISING_EDGE           ((uint32_t)0x00000001U)
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #define PVD_FALLING_EDGE          ((uint32_t)0x00000002U)
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @}
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @{
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */  
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #define  PWR_EWUP_MASK                          ((uint32_t)0x00003F00)
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @}
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @}
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @{
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *  @brief    Initialization and de-initialization functions
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** @verbatim
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****  ===============================================================================
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****               ##### Initialization and de-initialization functions #####
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****  ===============================================================================
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     [..]
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       After reset, the backup domain (RTC registers, RTC backup data 
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       registers and backup SRAM) is protected against possible unwanted 
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       write accesses. 
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       To enable access to the RTC Domain and RTC registers, proceed as follows:
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****         (+) Enable the Power Controller (PWR) APB1 interface clock using the
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****             __HAL_RCC_PWR_CLK_ENABLE() macro.
+ARM GAS  /tmp/ccE9MXkV.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****         (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****  
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** @endverbatim
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @{
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+  28              		.loc 1 100 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __HAL_RCC_PWR_FORCE_RESET();
+  33              		.loc 1 101 3 view .LVU1
+  34 0000 044B     		ldr	r3, .L2
+  35 0002 1A6A     		ldr	r2, [r3, #32]
+  36 0004 42F08052 		orr	r2, r2, #268435456
+  37 0008 1A62     		str	r2, [r3, #32]
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __HAL_RCC_PWR_RELEASE_RESET();
+  38              		.loc 1 102 3 view .LVU2
+  39 000a 1A6A     		ldr	r2, [r3, #32]
+  40 000c 22F08052 		bic	r2, r2, #268435456
+  41 0010 1A62     		str	r2, [r3, #32]
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+  42              		.loc 1 103 1 is_stmt 0 view .LVU3
+  43 0012 7047     		bx	lr
+  44              	.L3:
+  45              		.align	2
+  46              	.L2:
+  47 0014 00380240 		.word	1073887232
+  48              		.cfi_endproc
+  49              	.LFE141:
+  51              		.section	.text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
+  52              		.align	1
+  53              		.global	HAL_PWR_EnableBkUpAccess
+  54              		.syntax unified
+  55              		.thumb
+  56              		.thumb_func
+  57              		.fpu fpv5-d16
+  59              	HAL_PWR_EnableBkUpAccess:
+  60              	.LFB142:
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Enables access to the backup domain (RTC registers, RTC 
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         backup data registers and backup SRAM).
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         Backup Domain Access should be kept enabled.
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+  61              		.loc 1 113 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccE9MXkV.s 			page 4
+
+
+  62              		.cfi_startproc
+  63              		@ args = 0, pretend = 0, frame = 0
+  64              		@ frame_needed = 0, uses_anonymous_args = 0
+  65              		@ link register save eliminated.
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Enable access to RTC and backup registers */
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   SET_BIT(PWR->CR1, PWR_CR1_DBP);
+  66              		.loc 1 115 3 view .LVU5
+  67 0000 024A     		ldr	r2, .L5
+  68 0002 1368     		ldr	r3, [r2]
+  69 0004 43F48073 		orr	r3, r3, #256
+  70 0008 1360     		str	r3, [r2]
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+  71              		.loc 1 116 1 is_stmt 0 view .LVU6
+  72 000a 7047     		bx	lr
+  73              	.L6:
+  74              		.align	2
+  75              	.L5:
+  76 000c 00700040 		.word	1073770496
+  77              		.cfi_endproc
+  78              	.LFE142:
+  80              		.section	.text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
+  81              		.align	1
+  82              		.global	HAL_PWR_DisableBkUpAccess
+  83              		.syntax unified
+  84              		.thumb
+  85              		.thumb_func
+  86              		.fpu fpv5-d16
+  88              	HAL_PWR_DisableBkUpAccess:
+  89              	.LFB143:
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Disables access to the backup domain (RTC registers, RTC 
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         backup data registers and backup SRAM).
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         Backup Domain Access should be kept enabled.
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+  90              		.loc 1 126 1 is_stmt 1 view -0
+  91              		.cfi_startproc
+  92              		@ args = 0, pretend = 0, frame = 0
+  93              		@ frame_needed = 0, uses_anonymous_args = 0
+  94              		@ link register save eliminated.
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Disable access to RTC and backup registers */
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 	CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+  95              		.loc 1 128 2 view .LVU8
+  96 0000 024A     		ldr	r2, .L8
+  97 0002 1368     		ldr	r3, [r2]
+  98 0004 23F48073 		bic	r3, r3, #256
+  99 0008 1360     		str	r3, [r2]
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 100              		.loc 1 129 1 is_stmt 0 view .LVU9
+ 101 000a 7047     		bx	lr
+ 102              	.L9:
+ 103              		.align	2
+ 104              	.L8:
+ARM GAS  /tmp/ccE9MXkV.s 			page 5
+
+
+ 105 000c 00700040 		.word	1073770496
+ 106              		.cfi_endproc
+ 107              	.LFE143:
+ 109              		.section	.text.HAL_PWR_ConfigPVD,"ax",%progbits
+ 110              		.align	1
+ 111              		.global	HAL_PWR_ConfigPVD
+ 112              		.syntax unified
+ 113              		.thumb
+ 114              		.thumb_func
+ 115              		.fpu fpv5-d16
+ 117              	HAL_PWR_ConfigPVD:
+ 118              	.LVL0:
+ 119              	.LFB144:
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @}
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *  @brief Low Power modes configuration functions 
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** @verbatim
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****  ===============================================================================
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****                  ##### Peripheral Control functions #####
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****  ===============================================================================
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****      
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     *** PVD configuration ***
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     =========================
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     [..]
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) The PVD is used to monitor the VDD power supply by comparing it to a 
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****           threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****           than the PVD threshold. This event is internally connected to the EXTI 
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****           line16 and can generate an interrupt if enabled. This is done through
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****           __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) The PVD is stopped in Standby mode.
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     *** Wake-up pin configuration ***
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     ================================
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     [..]
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****           forced in input pull-down configuration and is active on rising edges.
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) There are up to 6 Wake-up pin in the STM32F7 devices family
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     *** Low Power modes configuration ***
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     =====================================
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     [..]
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       The devices feature 3 low-power modes:
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) Stop mode: all clocks are stopped, regulator running, regulator 
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****           in low power mode
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) Standby mode: 1.2V domain powered off.
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****    
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****    *** Sleep mode ***
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****    ==================
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     [..]
+ARM GAS  /tmp/ccE9MXkV.s 			page 6
+
+
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) Entry:
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****         The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLE
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****               functions with
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       -@@- The Regulator parameter is not used for the STM32F7 family 
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****               and is kept as parameter just to maintain compatibility with the 
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****               lower power families (STM32L).
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) Exit:
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****         Any peripheral interrupt acknowledged by the nested vectored interrupt 
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****               controller (NVIC) can wake up the device from Sleep mode.
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****    *** Stop mode ***
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****    =================
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     [..]
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       and the HSE RC oscillators are disabled. Internal SRAM and register contents 
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       are preserved.
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       The voltage regulator can be configured either in normal or low-power mode.
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       To minimize the consumption In Stop mode, FLASH can be powered off before 
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       It can be switched on again by software after exiting the Stop mode using
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       the HAL_PWREx_DisableFlashPowerDown() function. 
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) Entry:
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****          The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) 
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****              function with:
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****           (++) Main regulator ON.
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****           (++) Low Power regulator ON.
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) Exit:
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****    *** Standby mode ***
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****    ====================
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     [..]
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     (+)
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       The Standby mode allows to achieve the lowest power consumption. It is based 
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. 
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       the HSE oscillator are also switched off. SRAM and register contents are lost 
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       except for the RTC registers, RTC backup registers, backup SRAM and Standby 
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       circuitry.
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****    
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       The voltage regulator is OFF.
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (++) Entry:
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****         (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (++) Exit:
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****         (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****              wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****    *** Auto-wakeup (AWU) from low-power mode ***
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****    =============================================
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     [..]
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****      (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
+ARM GAS  /tmp/ccE9MXkV.s 			page 7
+
+
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       Wakeup event, a tamper event or a time-stamp event, without depending on 
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       an external interrupt (Auto-wakeup mode).
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****       (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****        
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****         (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****               configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****         (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****              is necessary to configure the RTC to detect the tamper or time stamp event using the
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****                 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****                   
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****         (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****               configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** @endverbatim
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @{
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *        information for the PVD.
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note Refer to the electrical characteristics of your device datasheet for
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         more details about the voltage threshold corresponding to each 
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         detection level.
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 120              		.loc 1 260 1 is_stmt 1 view -0
+ 121              		.cfi_startproc
+ 122              		@ args = 0, pretend = 0, frame = 0
+ 123              		@ frame_needed = 0, uses_anonymous_args = 0
+ 124              		@ link register save eliminated.
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Check the parameters */
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+ 125              		.loc 1 262 3 view .LVU11
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+ 126              		.loc 1 263 3 view .LVU12
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Set PLS[7:5] bits according to PVDLevel value */
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
+ 127              		.loc 1 266 3 view .LVU13
+ 128 0000 1E4A     		ldr	r2, .L15
+ 129 0002 1368     		ldr	r3, [r2]
+ 130 0004 23F0E003 		bic	r3, r3, #224
+ 131 0008 0168     		ldr	r1, [r0]
+ 132 000a 0B43     		orrs	r3, r3, r1
+ 133 000c 1360     		str	r3, [r2]
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+ 134              		.loc 1 269 3 view .LVU14
+ 135 000e 1C4B     		ldr	r3, .L15+4
+ 136 0010 5A68     		ldr	r2, [r3, #4]
+ 137 0012 22F48032 		bic	r2, r2, #65536
+ARM GAS  /tmp/ccE9MXkV.s 			page 8
+
+
+ 138 0016 5A60     		str	r2, [r3, #4]
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __HAL_PWR_PVD_EXTI_DISABLE_IT();
+ 139              		.loc 1 270 3 view .LVU15
+ 140 0018 1A68     		ldr	r2, [r3]
+ 141 001a 22F48032 		bic	r2, r2, #65536
+ 142 001e 1A60     		str	r2, [r3]
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+ 143              		.loc 1 271 3 view .LVU16
+ 144 0020 9A68     		ldr	r2, [r3, #8]
+ 145 0022 22F48032 		bic	r2, r2, #65536
+ 146 0026 9A60     		str	r2, [r3, #8]
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 
+ 147              		.loc 1 272 3 view .LVU17
+ 148 0028 DA68     		ldr	r2, [r3, #12]
+ 149 002a 22F48032 		bic	r2, r2, #65536
+ 150 002e DA60     		str	r2, [r3, #12]
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Configure interrupt mode */
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+ 151              		.loc 1 275 3 view .LVU18
+ 152              		.loc 1 275 17 is_stmt 0 view .LVU19
+ 153 0030 4368     		ldr	r3, [r0, #4]
+ 154              		.loc 1 275 5 view .LVU20
+ 155 0032 13F4803F 		tst	r3, #65536
+ 156 0036 04D0     		beq	.L11
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __HAL_PWR_PVD_EXTI_ENABLE_IT();
+ 157              		.loc 1 277 5 is_stmt 1 view .LVU21
+ 158 0038 114A     		ldr	r2, .L15+4
+ 159 003a 1368     		ldr	r3, [r2]
+ 160 003c 43F48033 		orr	r3, r3, #65536
+ 161 0040 1360     		str	r3, [r2]
+ 162              	.L11:
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Configure event mode */
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+ 163              		.loc 1 281 3 view .LVU22
+ 164              		.loc 1 281 17 is_stmt 0 view .LVU23
+ 165 0042 4368     		ldr	r3, [r0, #4]
+ 166              		.loc 1 281 5 view .LVU24
+ 167 0044 13F4003F 		tst	r3, #131072
+ 168 0048 04D0     		beq	.L12
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+ 169              		.loc 1 283 5 is_stmt 1 view .LVU25
+ 170 004a 0D4A     		ldr	r2, .L15+4
+ 171 004c 5368     		ldr	r3, [r2, #4]
+ 172 004e 43F48033 		orr	r3, r3, #65536
+ 173 0052 5360     		str	r3, [r2, #4]
+ 174              	.L12:
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Configure the edge */
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+ 175              		.loc 1 287 3 view .LVU26
+ 176              		.loc 1 287 17 is_stmt 0 view .LVU27
+ARM GAS  /tmp/ccE9MXkV.s 			page 9
+
+
+ 177 0054 4368     		ldr	r3, [r0, #4]
+ 178              		.loc 1 287 5 view .LVU28
+ 179 0056 13F0010F 		tst	r3, #1
+ 180 005a 04D0     		beq	.L13
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+ 181              		.loc 1 289 5 is_stmt 1 view .LVU29
+ 182 005c 084A     		ldr	r2, .L15+4
+ 183 005e 9368     		ldr	r3, [r2, #8]
+ 184 0060 43F48033 		orr	r3, r3, #65536
+ 185 0064 9360     		str	r3, [r2, #8]
+ 186              	.L13:
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+ 187              		.loc 1 292 3 view .LVU30
+ 188              		.loc 1 292 17 is_stmt 0 view .LVU31
+ 189 0066 4368     		ldr	r3, [r0, #4]
+ 190              		.loc 1 292 5 view .LVU32
+ 191 0068 13F0020F 		tst	r3, #2
+ 192 006c 04D0     		beq	.L10
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+ 193              		.loc 1 294 5 is_stmt 1 view .LVU33
+ 194 006e 044A     		ldr	r2, .L15+4
+ 195 0070 D368     		ldr	r3, [r2, #12]
+ 196 0072 43F48033 		orr	r3, r3, #65536
+ 197 0076 D360     		str	r3, [r2, #12]
+ 198              	.L10:
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 199              		.loc 1 296 1 is_stmt 0 view .LVU34
+ 200 0078 7047     		bx	lr
+ 201              	.L16:
+ 202 007a 00BF     		.align	2
+ 203              	.L15:
+ 204 007c 00700040 		.word	1073770496
+ 205 0080 003C0140 		.word	1073822720
+ 206              		.cfi_endproc
+ 207              	.LFE144:
+ 209              		.section	.text.HAL_PWR_EnablePVD,"ax",%progbits
+ 210              		.align	1
+ 211              		.global	HAL_PWR_EnablePVD
+ 212              		.syntax unified
+ 213              		.thumb
+ 214              		.thumb_func
+ 215              		.fpu fpv5-d16
+ 217              	HAL_PWR_EnablePVD:
+ 218              	.LFB145:
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Enables the Power Voltage Detector(PVD).
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void)
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 219              		.loc 1 303 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccE9MXkV.s 			page 10
+
+
+ 220              		.cfi_startproc
+ 221              		@ args = 0, pretend = 0, frame = 0
+ 222              		@ frame_needed = 0, uses_anonymous_args = 0
+ 223              		@ link register save eliminated.
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Enable the power voltage detector */
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 	SET_BIT(PWR->CR1, PWR_CR1_PVDE);
+ 224              		.loc 1 305 2 view .LVU36
+ 225 0000 024A     		ldr	r2, .L18
+ 226 0002 1368     		ldr	r3, [r2]
+ 227 0004 43F01003 		orr	r3, r3, #16
+ 228 0008 1360     		str	r3, [r2]
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 229              		.loc 1 306 1 is_stmt 0 view .LVU37
+ 230 000a 7047     		bx	lr
+ 231              	.L19:
+ 232              		.align	2
+ 233              	.L18:
+ 234 000c 00700040 		.word	1073770496
+ 235              		.cfi_endproc
+ 236              	.LFE145:
+ 238              		.section	.text.HAL_PWR_DisablePVD,"ax",%progbits
+ 239              		.align	1
+ 240              		.global	HAL_PWR_DisablePVD
+ 241              		.syntax unified
+ 242              		.thumb
+ 243              		.thumb_func
+ 244              		.fpu fpv5-d16
+ 246              	HAL_PWR_DisablePVD:
+ 247              	.LFB146:
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Disables the Power Voltage Detector(PVD).
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void)
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 248              		.loc 1 313 1 is_stmt 1 view -0
+ 249              		.cfi_startproc
+ 250              		@ args = 0, pretend = 0, frame = 0
+ 251              		@ frame_needed = 0, uses_anonymous_args = 0
+ 252              		@ link register save eliminated.
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Disable the power voltage detector */
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 	CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
+ 253              		.loc 1 315 2 view .LVU39
+ 254 0000 024A     		ldr	r2, .L21
+ 255 0002 1368     		ldr	r3, [r2]
+ 256 0004 23F01003 		bic	r3, r3, #16
+ 257 0008 1360     		str	r3, [r2]
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 258              		.loc 1 316 1 is_stmt 0 view .LVU40
+ 259 000a 7047     		bx	lr
+ 260              	.L22:
+ 261              		.align	2
+ 262              	.L21:
+ 263 000c 00700040 		.word	1073770496
+ 264              		.cfi_endproc
+ 265              	.LFE146:
+ARM GAS  /tmp/ccE9MXkV.s 			page 11
+
+
+ 267              		.section	.text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
+ 268              		.align	1
+ 269              		.global	HAL_PWR_EnableWakeUpPin
+ 270              		.syntax unified
+ 271              		.thumb
+ 272              		.thumb_func
+ 273              		.fpu fpv5-d16
+ 275              	HAL_PWR_EnableWakeUpPin:
+ 276              	.LVL1:
+ 277              	.LFB147:
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Enable the WakeUp PINx functionality.
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         This parameter can be one of the following legacy values, which sets the default polari
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         detection on high level (rising edge):
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_P
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         or one of the following value where the user can explicitly states the enabled pin and
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         the chosen polarity  
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW 
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW 
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW 
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW 
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW 
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.               
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 278              		.loc 1 336 1 is_stmt 1 view -0
+ 279              		.cfi_startproc
+ 280              		@ args = 0, pretend = 0, frame = 0
+ 281              		@ frame_needed = 0, uses_anonymous_args = 0
+ 282              		@ link register save eliminated.
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
+ 283              		.loc 1 337 3 view .LVU42
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Enable wake-up pin */
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));
+ 284              		.loc 1 340 3 view .LVU43
+ 285 0000 064A     		ldr	r2, .L24
+ 286 0002 D168     		ldr	r1, [r2, #12]
+ 287 0004 00F47C5C 		and	ip, r0, #16128
+ 288 0008 41EA0C01 		orr	r1, r1, ip
+ 289 000c D160     		str	r1, [r2, #12]
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 	
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Specifies the Wake-Up pin polarity for the event detection
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     (rising or falling edge) */
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));
+ 290              		.loc 1 344 3 view .LVU44
+ 291 000e 9368     		ldr	r3, [r2, #8]
+ 292 0010 23EA0C03 		bic	r3, r3, ip
+ 293 0014 43EA9010 		orr	r0, r3, r0, lsr #6
+ 294              	.LVL2:
+ 295              		.loc 1 344 3 is_stmt 0 view .LVU45
+ 296 0018 9060     		str	r0, [r2, #8]
+ARM GAS  /tmp/ccE9MXkV.s 			page 12
+
+
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 297              		.loc 1 345 1 view .LVU46
+ 298 001a 7047     		bx	lr
+ 299              	.L25:
+ 300              		.align	2
+ 301              	.L24:
+ 302 001c 00700040 		.word	1073770496
+ 303              		.cfi_endproc
+ 304              	.LFE147:
+ 306              		.section	.text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
+ 307              		.align	1
+ 308              		.global	HAL_PWR_DisableWakeUpPin
+ 309              		.syntax unified
+ 310              		.thumb
+ 311              		.thumb_func
+ 312              		.fpu fpv5-d16
+ 314              	HAL_PWR_DisableWakeUpPin:
+ 315              	.LVL3:
+ 316              	.LFB148:
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Disables the WakeUp PINx functionality.
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         This parameter can be one of the following values:
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN1
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN2
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN3
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN4
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN5
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *           @arg PWR_WAKEUP_PIN6 
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 317              		.loc 1 360 1 is_stmt 1 view -0
+ 318              		.cfi_startproc
+ 319              		@ args = 0, pretend = 0, frame = 0
+ 320              		@ frame_needed = 0, uses_anonymous_args = 0
+ 321              		@ link register save eliminated.
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ 322              		.loc 1 361 3 view .LVU48
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   CLEAR_BIT(PWR->CSR2, WakeUpPinx);
+ 323              		.loc 1 363 3 view .LVU49
+ 324 0000 024A     		ldr	r2, .L27
+ 325 0002 D368     		ldr	r3, [r2, #12]
+ 326 0004 23EA0003 		bic	r3, r3, r0
+ 327 0008 D360     		str	r3, [r2, #12]
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 328              		.loc 1 364 1 is_stmt 0 view .LVU50
+ 329 000a 7047     		bx	lr
+ 330              	.L28:
+ 331              		.align	2
+ 332              	.L27:
+ 333 000c 00700040 		.word	1073770496
+ 334              		.cfi_endproc
+ 335              	.LFE148:
+ARM GAS  /tmp/ccE9MXkV.s 			page 13
+
+
+ 337              		.section	.text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
+ 338              		.align	1
+ 339              		.global	HAL_PWR_EnterSLEEPMode
+ 340              		.syntax unified
+ 341              		.thumb
+ 342              		.thumb_func
+ 343              		.fpu fpv5-d16
+ 345              	HAL_PWR_EnterSLEEPMode:
+ 346              	.LVL4:
+ 347              	.LFB149:
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Enters Sleep mode.
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *   
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * 
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *       systick interrupt when used as time base for Timeout 
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *                
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @param Regulator Specifies the regulator state in SLEEP mode.
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *            This parameter can be one of the following values:
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note This parameter is not used for the STM32F7 family and is kept as parameter
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *       just to maintain compatibility with the lower power families.
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *          This parameter can be one of the following values:
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 348              		.loc 1 387 1 is_stmt 1 view -0
+ 349              		.cfi_startproc
+ 350              		@ args = 0, pretend = 0, frame = 0
+ 351              		@ frame_needed = 0, uses_anonymous_args = 0
+ 352              		@ link register save eliminated.
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Check the parameters */
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   assert_param(IS_PWR_REGULATOR(Regulator));
+ 353              		.loc 1 389 3 view .LVU52
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+ 354              		.loc 1 390 3 view .LVU53
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Prevent unused argument(s) compilation warning */
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   UNUSED(Regulator);
+ 355              		.loc 1 393 3 view .LVU54
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+ 356              		.loc 1 396 3 view .LVU55
+ 357 0000 084A     		ldr	r2, .L33
+ 358 0002 1369     		ldr	r3, [r2, #16]
+ 359 0004 23F00403 		bic	r3, r3, #4
+ 360 0008 1361     		str	r3, [r2, #16]
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Ensure that all instructions done before entering SLEEP mode */
+ARM GAS  /tmp/ccE9MXkV.s 			page 14
+
+
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __DSB();
+ 361              		.loc 1 399 3 view .LVU56
+ 362              	.LBB10:
+ 363              	.LBI10:
+ 364              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.0.4
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     09. April 2018
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+ARM GAS  /tmp/ccE9MXkV.s 			page 15
+
+
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccE9MXkV.s 			page 16
+
+
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ARM GAS  /tmp/ccE9MXkV.s 			page 17
+
+
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ARM GAS  /tmp/ccE9MXkV.s 			page 18
+
+
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ARM GAS  /tmp/ccE9MXkV.s 			page 19
+
+
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ARM GAS  /tmp/ccE9MXkV.s 			page 20
+
+
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ARM GAS  /tmp/ccE9MXkV.s 			page 21
+
+
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccE9MXkV.s 			page 22
+
+
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccE9MXkV.s 			page 23
+
+
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ARM GAS  /tmp/ccE9MXkV.s 			page 24
+
+
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ARM GAS  /tmp/ccE9MXkV.s 			page 25
+
+
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ARM GAS  /tmp/ccE9MXkV.s 			page 26
+
+
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccE9MXkV.s 			page 27
+
+
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccE9MXkV.s 			page 28
+
+
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ARM GAS  /tmp/ccE9MXkV.s 			page 29
+
+
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 365              		.loc 2 877 27 view .LVU57
+ 366              	.LBB11:
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 367              		.loc 2 879 3 view .LVU58
+ 368              		.syntax unified
+ 369              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 370 000a BFF34F8F 		dsb 0xF
+ 371              	@ 0 "" 2
+ 372              		.thumb
+ 373              		.syntax unified
+ 374              	.LBE11:
+ 375              	.LBE10:
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __ISB();
+ 376              		.loc 1 400 3 view .LVU59
+ 377              	.LBB12:
+ 378              	.LBI12:
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 379              		.loc 2 866 27 view .LVU60
+ 380              	.LBB13:
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 381              		.loc 2 868 3 view .LVU61
+ 382              		.syntax unified
+ 383              	@ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 384 000e BFF36F8F 		isb 0xF
+ 385              	@ 0 "" 2
+ 386              		.thumb
+ 387              		.syntax unified
+ 388              	.LBE13:
+ 389              	.LBE12:
+ARM GAS  /tmp/ccE9MXkV.s 			page 30
+
+
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Select SLEEP mode entry -------------------------------------------------*/
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ 390              		.loc 1 403 3 view .LVU62
+ 391              		.loc 1 403 5 is_stmt 0 view .LVU63
+ 392 0012 0129     		cmp	r1, #1
+ 393 0014 03D0     		beq	.L32
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {   
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     /* Request Wait For Interrupt */
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __WFI();
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   else
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     /* Request Wait For Event */
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __SEV();
+ 394              		.loc 1 411 5 is_stmt 1 view .LVU64
+ 395              		.syntax unified
+ 396              	@ 411 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1
+ 397 0016 40BF     		sev
+ 398              	@ 0 "" 2
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __WFE();
+ 399              		.loc 1 412 5 view .LVU65
+ 400              	@ 412 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1
+ 401 0018 20BF     		wfe
+ 402              	@ 0 "" 2
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __WFE();
+ 403              		.loc 1 413 5 view .LVU66
+ 404              	@ 413 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1
+ 405 001a 20BF     		wfe
+ 406              	@ 0 "" 2
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 407              		.loc 1 415 1 is_stmt 0 view .LVU67
+ 408              		.thumb
+ 409              		.syntax unified
+ 410 001c 7047     		bx	lr
+ 411              	.L32:
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 412              		.loc 1 406 5 is_stmt 1 view .LVU68
+ 413              		.syntax unified
+ 414              	@ 406 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1
+ 415 001e 30BF     		wfi
+ 416              	@ 0 "" 2
+ 417              		.thumb
+ 418              		.syntax unified
+ 419 0020 7047     		bx	lr
+ 420              	.L34:
+ 421 0022 00BF     		.align	2
+ 422              	.L33:
+ 423 0024 00ED00E0 		.word	-536810240
+ 424              		.cfi_endproc
+ 425              	.LFE149:
+ 427              		.section	.text.HAL_PWR_EnterSTOPMode,"ax",%progbits
+ 428              		.align	1
+ 429              		.global	HAL_PWR_EnterSTOPMode
+ 430              		.syntax unified
+ 431              		.thumb
+ARM GAS  /tmp/ccE9MXkV.s 			page 31
+
+
+ 432              		.thumb_func
+ 433              		.fpu fpv5-d16
+ 435              	HAL_PWR_EnterSTOPMode:
+ 436              	.LVL5:
+ 437              	.LFB150:
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Enters Stop mode. 
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note When exiting Stop mode by issuing an interrupt or a wakeup event, 
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         the HSI RC oscillator is selected as system clock.
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note When the voltage regulator operates in low power mode, an additional 
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         startup delay is incurred when waking up from Stop mode. 
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         By keeping the internal regulator ON during Stop mode, the consumption 
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *         is higher although the startup time is reduced.    
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @param Regulator Specifies the regulator state in Stop mode.
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *          This parameter can be one of the following values:
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *          This parameter can be one of the following values:
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 438              		.loc 1 437 1 view -0
+ 439              		.cfi_startproc
+ 440              		@ args = 0, pretend = 0, frame = 0
+ 441              		@ frame_needed = 0, uses_anonymous_args = 0
+ 442              		@ link register save eliminated.
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   uint32_t tmpreg = 0;
+ 443              		.loc 1 438 3 view .LVU70
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Check the parameters */
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   assert_param(IS_PWR_REGULATOR(Regulator));
+ 444              		.loc 1 441 3 view .LVU71
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+ 445              		.loc 1 442 3 view .LVU72
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Select the regulator state in Stop mode ---------------------------------*/
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   tmpreg = PWR->CR1;
+ 446              		.loc 1 445 3 view .LVU73
+ 447              		.loc 1 445 10 is_stmt 0 view .LVU74
+ 448 0000 0D4A     		ldr	r2, .L39
+ 449 0002 1368     		ldr	r3, [r2]
+ 450              	.LVL6:
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Clear PDDS and LPDS bits */
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);
+ 451              		.loc 1 447 3 is_stmt 1 view .LVU75
+ 452              		.loc 1 447 10 is_stmt 0 view .LVU76
+ 453 0004 23F00303 		bic	r3, r3, #3
+ 454              	.LVL7:
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   tmpreg |= Regulator;
+ARM GAS  /tmp/ccE9MXkV.s 			page 32
+
+
+ 455              		.loc 1 450 3 is_stmt 1 view .LVU77
+ 456              		.loc 1 450 10 is_stmt 0 view .LVU78
+ 457 0008 0343     		orrs	r3, r3, r0
+ 458              	.LVL8:
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Store the new value */
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   PWR->CR1 = tmpreg;
+ 459              		.loc 1 453 3 is_stmt 1 view .LVU79
+ 460              		.loc 1 453 12 is_stmt 0 view .LVU80
+ 461 000a 1360     		str	r3, [r2]
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ 462              		.loc 1 456 3 is_stmt 1 view .LVU81
+ 463              		.loc 1 456 12 is_stmt 0 view .LVU82
+ 464 000c 0B4A     		ldr	r2, .L39+4
+ 465 000e 1369     		ldr	r3, [r2, #16]
+ 466              	.LVL9:
+ 467              		.loc 1 456 12 view .LVU83
+ 468 0010 43F00403 		orr	r3, r3, #4
+ 469 0014 1361     		str	r3, [r2, #16]
+ 470              	.LVL10:
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Ensure that all instructions done before entering STOP mode */
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __DSB();
+ 471              		.loc 1 459 3 is_stmt 1 view .LVU84
+ 472              	.LBB14:
+ 473              	.LBI14:
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 474              		.loc 2 877 27 view .LVU85
+ 475              	.LBB15:
+ 476              		.loc 2 879 3 view .LVU86
+ 477              		.syntax unified
+ 478              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 479 0016 BFF34F8F 		dsb 0xF
+ 480              	@ 0 "" 2
+ 481              		.thumb
+ 482              		.syntax unified
+ 483              	.LBE15:
+ 484              	.LBE14:
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __ISB();
+ 485              		.loc 1 460 3 view .LVU87
+ 486              	.LBB16:
+ 487              	.LBI16:
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 488              		.loc 2 866 27 view .LVU88
+ 489              	.LBB17:
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 490              		.loc 2 868 3 view .LVU89
+ 491              		.syntax unified
+ 492              	@ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 493 001a BFF36F8F 		isb 0xF
+ 494              	@ 0 "" 2
+ 495              		.thumb
+ 496              		.syntax unified
+ 497              	.LBE17:
+ 498              	.LBE16:
+ARM GAS  /tmp/ccE9MXkV.s 			page 33
+
+
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Select Stop mode entry --------------------------------------------------*/
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   if(STOPEntry == PWR_STOPENTRY_WFI)
+ 499              		.loc 1 463 3 view .LVU90
+ 500              		.loc 1 463 5 is_stmt 0 view .LVU91
+ 501 001e 0129     		cmp	r1, #1
+ 502 0020 08D0     		beq	.L38
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {   
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     /* Request Wait For Interrupt */
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __WFI();
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   else
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     /* Request Wait For Event */
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __SEV();
+ 503              		.loc 1 471 5 is_stmt 1 view .LVU92
+ 504              		.syntax unified
+ 505              	@ 471 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1
+ 506 0022 40BF     		sev
+ 507              	@ 0 "" 2
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __WFE();
+ 508              		.loc 1 472 5 view .LVU93
+ 509              	@ 472 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1
+ 510 0024 20BF     		wfe
+ 511              	@ 0 "" 2
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __WFE();
+ 512              		.loc 1 473 5 view .LVU94
+ 513              	@ 473 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1
+ 514 0026 20BF     		wfe
+ 515              	@ 0 "" 2
+ 516              		.thumb
+ 517              		.syntax unified
+ 518              	.L37:
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
+ 519              		.loc 1 476 3 view .LVU95
+ 520              		.loc 1 476 12 is_stmt 0 view .LVU96
+ 521 0028 044A     		ldr	r2, .L39+4
+ 522 002a 1369     		ldr	r3, [r2, #16]
+ 523 002c 23F00403 		bic	r3, r3, #4
+ 524 0030 1361     		str	r3, [r2, #16]
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 525              		.loc 1 477 1 view .LVU97
+ 526 0032 7047     		bx	lr
+ 527              	.L38:
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 528              		.loc 1 466 5 is_stmt 1 view .LVU98
+ 529              		.syntax unified
+ 530              	@ 466 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1
+ 531 0034 30BF     		wfi
+ 532              	@ 0 "" 2
+ 533              		.thumb
+ 534              		.syntax unified
+ 535 0036 F7E7     		b	.L37
+ 536              	.L40:
+ 537              		.align	2
+ARM GAS  /tmp/ccE9MXkV.s 			page 34
+
+
+ 538              	.L39:
+ 539 0038 00700040 		.word	1073770496
+ 540 003c 00ED00E0 		.word	-536810240
+ 541              		.cfi_endproc
+ 542              	.LFE150:
+ 544              		.section	.text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
+ 545              		.align	1
+ 546              		.global	HAL_PWR_EnterSTANDBYMode
+ 547              		.syntax unified
+ 548              		.thumb
+ 549              		.thumb_func
+ 550              		.fpu fpv5-d16
+ 552              	HAL_PWR_EnterSTANDBYMode:
+ 553              	.LFB151:
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Enters Standby mode.
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note In Standby mode, all I/O pins are high impedance except for:
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *          - Reset pad (still available) 
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *            Alarm out, or RTC clock calibration out.
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *          - WKUP pins if enabled.       
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 554              		.loc 1 490 1 view -0
+ 555              		.cfi_startproc
+ 556              		@ args = 0, pretend = 0, frame = 0
+ 557              		@ frame_needed = 0, uses_anonymous_args = 0
+ 558              		@ link register save eliminated.
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Select Standby mode */
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   PWR->CR1 |= PWR_CR1_PDDS;
+ 559              		.loc 1 492 3 view .LVU100
+ 560              		.loc 1 492 12 is_stmt 0 view .LVU101
+ 561 0000 054A     		ldr	r2, .L42
+ 562 0002 1368     		ldr	r3, [r2]
+ 563 0004 43F00203 		orr	r3, r3, #2
+ 564 0008 1360     		str	r3, [r2]
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ 565              		.loc 1 495 3 is_stmt 1 view .LVU102
+ 566              		.loc 1 495 12 is_stmt 0 view .LVU103
+ 567 000a 044A     		ldr	r2, .L42+4
+ 568 000c 1369     		ldr	r3, [r2, #16]
+ 569 000e 43F00403 		orr	r3, r3, #4
+ 570 0012 1361     		str	r3, [r2, #16]
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* This option is used to ensure that store operations are completed */
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #if defined ( __CC_ARM)
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __force_stores();
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #endif
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Request Wait For Interrupt */
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   __WFI();
+ 571              		.loc 1 502 3 is_stmt 1 view .LVU104
+ARM GAS  /tmp/ccE9MXkV.s 			page 35
+
+
+ 572              		.syntax unified
+ 573              	@ 502 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1
+ 574 0014 30BF     		wfi
+ 575              	@ 0 "" 2
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 576              		.loc 1 503 1 is_stmt 0 view .LVU105
+ 577              		.thumb
+ 578              		.syntax unified
+ 579 0016 7047     		bx	lr
+ 580              	.L43:
+ 581              		.align	2
+ 582              	.L42:
+ 583 0018 00700040 		.word	1073770496
+ 584 001c 00ED00E0 		.word	-536810240
+ 585              		.cfi_endproc
+ 586              	.LFE151:
+ 588              		.section	.text.HAL_PWR_PVDCallback,"ax",%progbits
+ 589              		.align	1
+ 590              		.weak	HAL_PWR_PVDCallback
+ 591              		.syntax unified
+ 592              		.thumb
+ 593              		.thumb_func
+ 594              		.fpu fpv5-d16
+ 596              	HAL_PWR_PVDCallback:
+ 597              	.LFB153:
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief This function handles the PWR PVD interrupt request.
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note This API should be called under the PVD_IRQHandler().
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_PVD_IRQHandler(void)
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Check PWR Exti flag */
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     /* PWR PVD interrupt user callback */
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     HAL_PWR_PVDCallback();
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     /* Clear PWR Exti pending bit */
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief  PWR PVD interrupt callback
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void)
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 598              		.loc 1 528 1 is_stmt 1 view -0
+ 599              		.cfi_startproc
+ 600              		@ args = 0, pretend = 0, frame = 0
+ 601              		@ frame_needed = 0, uses_anonymous_args = 0
+ 602              		@ link register save eliminated.
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****             the HAL_PWR_PVDCallback could be implemented in the user file
+ARM GAS  /tmp/ccE9MXkV.s 			page 36
+
+
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****    */ 
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 603              		.loc 1 532 1 view .LVU107
+ 604 0000 7047     		bx	lr
+ 605              		.cfi_endproc
+ 606              	.LFE153:
+ 608              		.section	.text.HAL_PWR_PVD_IRQHandler,"ax",%progbits
+ 609              		.align	1
+ 610              		.global	HAL_PWR_PVD_IRQHandler
+ 611              		.syntax unified
+ 612              		.thumb
+ 613              		.thumb_func
+ 614              		.fpu fpv5-d16
+ 616              	HAL_PWR_PVD_IRQHandler:
+ 617              	.LFB152:
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Check PWR Exti flag */
+ 618              		.loc 1 511 1 view -0
+ 619              		.cfi_startproc
+ 620              		@ args = 0, pretend = 0, frame = 0
+ 621              		@ frame_needed = 0, uses_anonymous_args = 0
+ 622 0000 08B5     		push	{r3, lr}
+ 623              	.LCFI0:
+ 624              		.cfi_def_cfa_offset 8
+ 625              		.cfi_offset 3, -8
+ 626              		.cfi_offset 14, -4
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {
+ 627              		.loc 1 513 3 view .LVU109
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {
+ 628              		.loc 1 513 6 is_stmt 0 view .LVU110
+ 629 0002 064B     		ldr	r3, .L49
+ 630 0004 5B69     		ldr	r3, [r3, #20]
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   {
+ 631              		.loc 1 513 5 view .LVU111
+ 632 0006 13F4803F 		tst	r3, #65536
+ 633 000a 00D1     		bne	.L48
+ 634              	.L45:
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 635              		.loc 1 521 1 view .LVU112
+ 636 000c 08BD     		pop	{r3, pc}
+ 637              	.L48:
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****     
+ 638              		.loc 1 516 5 is_stmt 1 view .LVU113
+ 639 000e FFF7FEFF 		bl	HAL_PWR_PVDCallback
+ 640              	.LVL11:
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   }
+ 641              		.loc 1 519 5 view .LVU114
+ 642 0012 024B     		ldr	r3, .L49
+ 643 0014 4FF48032 		mov	r2, #65536
+ 644 0018 5A61     		str	r2, [r3, #20]
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 645              		.loc 1 521 1 is_stmt 0 view .LVU115
+ 646 001a F7E7     		b	.L45
+ 647              	.L50:
+ 648              		.align	2
+ 649              	.L49:
+ 650 001c 003C0140 		.word	1073822720
+ 651              		.cfi_endproc
+ARM GAS  /tmp/ccE9MXkV.s 			page 37
+
+
+ 652              	.LFE152:
+ 654              		.section	.text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
+ 655              		.align	1
+ 656              		.global	HAL_PWR_EnableSleepOnExit
+ 657              		.syntax unified
+ 658              		.thumb
+ 659              		.thumb_func
+ 660              		.fpu fpv5-d16
+ 662              	HAL_PWR_EnableSleepOnExit:
+ 663              	.LFB154:
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *       re-enters SLEEP mode when an interruption handling is over.
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *       Setting this bit is useful when the processor is expected to run only on
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *       interruptions handling.         
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 664              		.loc 1 543 1 is_stmt 1 view -0
+ 665              		.cfi_startproc
+ 666              		@ args = 0, pretend = 0, frame = 0
+ 667              		@ frame_needed = 0, uses_anonymous_args = 0
+ 668              		@ link register save eliminated.
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+ 669              		.loc 1 545 3 view .LVU117
+ 670 0000 024A     		ldr	r2, .L52
+ 671 0002 1369     		ldr	r3, [r2, #16]
+ 672 0004 43F00203 		orr	r3, r3, #2
+ 673 0008 1361     		str	r3, [r2, #16]
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 674              		.loc 1 546 1 is_stmt 0 view .LVU118
+ 675 000a 7047     		bx	lr
+ 676              	.L53:
+ 677              		.align	2
+ 678              	.L52:
+ 679 000c 00ED00E0 		.word	-536810240
+ 680              		.cfi_endproc
+ 681              	.LFE154:
+ 683              		.section	.text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
+ 684              		.align	1
+ 685              		.global	HAL_PWR_DisableSleepOnExit
+ 686              		.syntax unified
+ 687              		.thumb
+ 688              		.thumb_func
+ 689              		.fpu fpv5-d16
+ 691              	HAL_PWR_DisableSleepOnExit:
+ 692              	.LFB155:
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *       re-enters SLEEP mode when an interruption handling is over.          
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ARM GAS  /tmp/ccE9MXkV.s 			page 38
+
+
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 693              		.loc 1 555 1 is_stmt 1 view -0
+ 694              		.cfi_startproc
+ 695              		@ args = 0, pretend = 0, frame = 0
+ 696              		@ frame_needed = 0, uses_anonymous_args = 0
+ 697              		@ link register save eliminated.
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+ 698              		.loc 1 557 3 view .LVU120
+ 699 0000 024A     		ldr	r2, .L55
+ 700 0002 1369     		ldr	r3, [r2, #16]
+ 701 0004 23F00203 		bic	r3, r3, #2
+ 702 0008 1361     		str	r3, [r2, #16]
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 703              		.loc 1 558 1 is_stmt 0 view .LVU121
+ 704 000a 7047     		bx	lr
+ 705              	.L56:
+ 706              		.align	2
+ 707              	.L55:
+ 708 000c 00ED00E0 		.word	-536810240
+ 709              		.cfi_endproc
+ 710              	.LFE155:
+ 712              		.section	.text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
+ 713              		.align	1
+ 714              		.global	HAL_PWR_EnableSEVOnPend
+ 715              		.syntax unified
+ 716              		.thumb
+ 717              		.thumb_func
+ 718              		.fpu fpv5-d16
+ 720              	HAL_PWR_EnableSEVOnPend:
+ 721              	.LFB156:
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Enables CORTEX M4 SEVONPEND bit. 
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *       WFE to wake up when an interrupt moves from inactive to pended.
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 722              		.loc 1 567 1 is_stmt 1 view -0
+ 723              		.cfi_startproc
+ 724              		@ args = 0, pretend = 0, frame = 0
+ 725              		@ frame_needed = 0, uses_anonymous_args = 0
+ 726              		@ link register save eliminated.
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Set SEVONPEND bit of Cortex System Control Register */
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+ 727              		.loc 1 569 3 view .LVU123
+ 728 0000 024A     		ldr	r2, .L58
+ 729 0002 1369     		ldr	r3, [r2, #16]
+ 730 0004 43F01003 		orr	r3, r3, #16
+ 731 0008 1361     		str	r3, [r2, #16]
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 732              		.loc 1 570 1 is_stmt 0 view .LVU124
+ 733 000a 7047     		bx	lr
+ARM GAS  /tmp/ccE9MXkV.s 			page 39
+
+
+ 734              	.L59:
+ 735              		.align	2
+ 736              	.L58:
+ 737 000c 00ED00E0 		.word	-536810240
+ 738              		.cfi_endproc
+ 739              	.LFE156:
+ 741              		.section	.text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
+ 742              		.align	1
+ 743              		.global	HAL_PWR_DisableSEVOnPend
+ 744              		.syntax unified
+ 745              		.thumb
+ 746              		.thumb_func
+ 747              		.fpu fpv5-d16
+ 749              	HAL_PWR_DisableSEVOnPend:
+ 750              	.LFB157:
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** 
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /**
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @brief Disables CORTEX M4 SEVONPEND bit. 
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   *       WFE to wake up when an interrupt moves from inactive to pended.         
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   * @retval None
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   */
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** {
+ 751              		.loc 1 579 1 is_stmt 1 view -0
+ 752              		.cfi_startproc
+ 753              		@ args = 0, pretend = 0, frame = 0
+ 754              		@ frame_needed = 0, uses_anonymous_args = 0
+ 755              		@ link register save eliminated.
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   /* Clear SEVONPEND bit of Cortex System Control Register */
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+ 756              		.loc 1 581 3 view .LVU126
+ 757 0000 024A     		ldr	r2, .L61
+ 758 0002 1369     		ldr	r3, [r2, #16]
+ 759 0004 23F01003 		bic	r3, r3, #16
+ 760 0008 1361     		str	r3, [r2, #16]
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** }
+ 761              		.loc 1 582 1 is_stmt 0 view .LVU127
+ 762 000a 7047     		bx	lr
+ 763              	.L62:
+ 764              		.align	2
+ 765              	.L61:
+ 766 000c 00ED00E0 		.word	-536810240
+ 767              		.cfi_endproc
+ 768              	.LFE157:
+ 770              		.text
+ 771              	.Letext0:
+ 772              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 773              		.file 4 "Drivers/CMSIS/Include/core_cm7.h"
+ 774              		.file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 775              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h"
+ 776              		.file 7 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ARM GAS  /tmp/ccE9MXkV.s 			page 40
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_pwr.c
+     /tmp/ccE9MXkV.s:17     .text.HAL_PWR_DeInit:0000000000000000 $t
+     /tmp/ccE9MXkV.s:25     .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit
+     /tmp/ccE9MXkV.s:47     .text.HAL_PWR_DeInit:0000000000000014 $d
+     /tmp/ccE9MXkV.s:52     .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t
+     /tmp/ccE9MXkV.s:59     .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess
+     /tmp/ccE9MXkV.s:76     .text.HAL_PWR_EnableBkUpAccess:000000000000000c $d
+     /tmp/ccE9MXkV.s:81     .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t
+     /tmp/ccE9MXkV.s:88     .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess
+     /tmp/ccE9MXkV.s:105    .text.HAL_PWR_DisableBkUpAccess:000000000000000c $d
+     /tmp/ccE9MXkV.s:110    .text.HAL_PWR_ConfigPVD:0000000000000000 $t
+     /tmp/ccE9MXkV.s:117    .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD
+     /tmp/ccE9MXkV.s:204    .text.HAL_PWR_ConfigPVD:000000000000007c $d
+     /tmp/ccE9MXkV.s:210    .text.HAL_PWR_EnablePVD:0000000000000000 $t
+     /tmp/ccE9MXkV.s:217    .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD
+     /tmp/ccE9MXkV.s:234    .text.HAL_PWR_EnablePVD:000000000000000c $d
+     /tmp/ccE9MXkV.s:239    .text.HAL_PWR_DisablePVD:0000000000000000 $t
+     /tmp/ccE9MXkV.s:246    .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD
+     /tmp/ccE9MXkV.s:263    .text.HAL_PWR_DisablePVD:000000000000000c $d
+     /tmp/ccE9MXkV.s:268    .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t
+     /tmp/ccE9MXkV.s:275    .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin
+     /tmp/ccE9MXkV.s:302    .text.HAL_PWR_EnableWakeUpPin:000000000000001c $d
+     /tmp/ccE9MXkV.s:307    .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t
+     /tmp/ccE9MXkV.s:314    .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin
+     /tmp/ccE9MXkV.s:333    .text.HAL_PWR_DisableWakeUpPin:000000000000000c $d
+     /tmp/ccE9MXkV.s:338    .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t
+     /tmp/ccE9MXkV.s:345    .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode
+     /tmp/ccE9MXkV.s:423    .text.HAL_PWR_EnterSLEEPMode:0000000000000024 $d
+     /tmp/ccE9MXkV.s:428    .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t
+     /tmp/ccE9MXkV.s:435    .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode
+     /tmp/ccE9MXkV.s:539    .text.HAL_PWR_EnterSTOPMode:0000000000000038 $d
+     /tmp/ccE9MXkV.s:545    .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t
+     /tmp/ccE9MXkV.s:552    .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode
+     /tmp/ccE9MXkV.s:583    .text.HAL_PWR_EnterSTANDBYMode:0000000000000018 $d
+     /tmp/ccE9MXkV.s:589    .text.HAL_PWR_PVDCallback:0000000000000000 $t
+     /tmp/ccE9MXkV.s:596    .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback
+     /tmp/ccE9MXkV.s:609    .text.HAL_PWR_PVD_IRQHandler:0000000000000000 $t
+     /tmp/ccE9MXkV.s:616    .text.HAL_PWR_PVD_IRQHandler:0000000000000000 HAL_PWR_PVD_IRQHandler
+     /tmp/ccE9MXkV.s:650    .text.HAL_PWR_PVD_IRQHandler:000000000000001c $d
+     /tmp/ccE9MXkV.s:655    .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t
+     /tmp/ccE9MXkV.s:662    .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit
+     /tmp/ccE9MXkV.s:679    .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d
+     /tmp/ccE9MXkV.s:684    .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t
+     /tmp/ccE9MXkV.s:691    .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit
+     /tmp/ccE9MXkV.s:708    .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d
+     /tmp/ccE9MXkV.s:713    .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t
+     /tmp/ccE9MXkV.s:720    .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend
+     /tmp/ccE9MXkV.s:737    .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d
+     /tmp/ccE9MXkV.s:742    .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t
+     /tmp/ccE9MXkV.s:749    .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend
+     /tmp/ccE9MXkV.s:766    .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d
+
+NO UNDEFINED SYMBOLS
diff --git a/build/stm32f7xx_hal_pwr.o b/build/stm32f7xx_hal_pwr.o
new file mode 100644
index 0000000..0993df6
Binary files /dev/null and b/build/stm32f7xx_hal_pwr.o differ
diff --git a/build/stm32f7xx_hal_pwr_ex.d b/build/stm32f7xx_hal_pwr_ex.d
new file mode 100644
index 0000000..8f22bab
--- /dev/null
+++ b/build/stm32f7xx_hal_pwr_ex.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_pwr_ex.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_pwr_ex.lst b/build/stm32f7xx_hal_pwr_ex.lst
new file mode 100644
index 0000000..9f2a736
--- /dev/null
+++ b/build/stm32f7xx_hal_pwr_ex.lst
@@ -0,0 +1,1659 @@
+ARM GAS  /tmp/cc97GYnP.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_pwr_ex.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.HAL_PWREx_EnableBkUpReg,"ax",%progbits
+  17              		.align	1
+  18              		.global	HAL_PWREx_EnableBkUpReg
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	HAL_PWREx_EnableBkUpReg:
+  26              	.LFB141:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @file    stm32f7xx_hal_pwr_ex.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief   Extended PWR HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *          This file provides firmware functions to manage the following 
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *          functionalities of PWR extension peripheral:           
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *           + Peripheral Extended features functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   ******************************************************************************
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @attention
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * Copyright (c) 2017 STMicroelectronics.
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * All rights reserved.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * in the root directory of this software component.
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   ******************************************************************************
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #include "stm32f7xx_hal.h"
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @{
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** @defgroup PWREx PWREx
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief PWR HAL module driver
+ARM GAS  /tmp/cc97GYnP.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @{
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private define ------------------------------------------------------------*/
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** @addtogroup PWREx_Private_Constants
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @{
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */    
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #define PWR_OVERDRIVE_TIMEOUT_VALUE  1000
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #define PWR_UDERDRIVE_TIMEOUT_VALUE  1000
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #define PWR_BKPREG_TIMEOUT_VALUE     1000
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #define PWR_VOSRDY_TIMEOUT_VALUE     1000
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @}
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private macro -------------------------------------------------------------*/
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private variables ---------------------------------------------------------*/
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private function prototypes -----------------------------------------------*/
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private functions ---------------------------------------------------------*/
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *  @{
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions 
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *  @brief Peripheral Extended features functions 
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** @verbatim   
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****  ===============================================================================
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****                  ##### Peripheral extended features functions #####
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****  ===============================================================================
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     *** Main and Backup Regulators configuration ***
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     ================================================
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     [..] 
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from 
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is 
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           retained even in Standby or VBAT mode when the low power backup regulator
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           is enabled. It can be considered as an internal EEPROM when VBAT is 
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           always present. You can use the HAL_PWREx_EnableBkUpReg() function to 
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           enable the low power backup regulator. 
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       (+) When the backup domain is supplied by VDD (analog switch connected to VDD) 
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           the backup SRAM is powered from VDD which replaces the VBAT power supply to 
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           save battery life.
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       (+) The backup SRAM is not mass erased by a tamper event. It is read 
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           protected to prevent confidential data, such as cryptographic private 
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           key, from being accessed. The backup SRAM can be erased only through 
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           the Flash interface when a protection level change from level 1 to 
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           level 0 is requested. 
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       -@- Refer to the description of Read protection (RDP) in the Flash 
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           programming manual.
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ARM GAS  /tmp/cc97GYnP.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       (+) The main internal regulator can be configured to have a tradeoff between 
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           performance and power consumption when the device does not operate at 
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() 
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           macro which configure VOS bit in PWR_CR register
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****         Refer to the product datasheets for more details.
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     *** FLASH Power Down configuration ****
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     =======================================
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     [..] 
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       (+) By setting the FPDS bit in the PWR_CR register by using the 
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power 
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           down mode when the device enters Stop mode. When the Flash memory 
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           is in power down mode, an additional startup delay is incurred when 
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****           waking up from Stop mode.
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     *** Over-Drive and Under-Drive configuration ****
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     =================================================
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     [..]         
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****        (+) In Run mode: the main regulator has 2 operating modes available:
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****         (++) Normal mode: The CPU and core logic operate at maximum frequency at a given 
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****              voltage scaling (scale 1, scale 2 or scale 3)
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****         (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a 
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****             higher frequency than the normal mode for a given voltage scaling (scale 1,  
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****             scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function 
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****             disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mod
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****             the sequence described in Reference manual.
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****              
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****        (+) In Stop mode: the main regulator or low power regulator supplies a low power 
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****            voltage to the 1.2V domain, thus preserving the content of registers 
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****            and internal SRAM. 2 operating modes are available:
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****          (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only 
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****               available when the main regulator or the low power regulator is used in Scale 3 or 
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****               low voltage mode.
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****          (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is 
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****               available when the main regulator or the low power regulator is in low voltage mode.
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** @endverbatim
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @{
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief Enables the Backup Regulator.
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval HAL status
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+  28              		.loc 1 135 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32 0000 10B5     		push	{r4, lr}
+  33              	.LCFI0:
+  34              		.cfi_def_cfa_offset 8
+  35              		.cfi_offset 4, -8
+  36              		.cfi_offset 14, -4
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   uint32_t tickstart = 0;
+ARM GAS  /tmp/cc97GYnP.s 			page 4
+
+
+  37              		.loc 1 136 3 view .LVU1
+  38              	.LVL0:
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Enable Backup regulator */
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   PWR->CSR1 |= PWR_CSR1_BRE;
+  39              		.loc 1 139 3 view .LVU2
+  40              		.loc 1 139 13 is_stmt 0 view .LVU3
+  41 0002 0D4B     		ldr	r3, .L8
+  42 0004 5A68     		ldr	r2, [r3, #4]
+  43 0006 42F40072 		orr	r2, r2, #512
+  44 000a 5A60     		str	r2, [r3, #4]
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Workaround for the following hardware bug: */
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   PWR->CSR1 |= PWR_CSR1_EIWUP;
+  45              		.loc 1 143 3 is_stmt 1 view .LVU4
+  46              		.loc 1 143 13 is_stmt 0 view .LVU5
+  47 000c 5A68     		ldr	r2, [r3, #4]
+  48 000e 42F48072 		orr	r2, r2, #256
+  49 0012 5A60     		str	r2, [r3, #4]
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Get tick */
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick();
+  50              		.loc 1 146 3 is_stmt 1 view .LVU6
+  51              		.loc 1 146 15 is_stmt 0 view .LVU7
+  52 0014 FFF7FEFF 		bl	HAL_GetTick
+  53              	.LVL1:
+  54 0018 0446     		mov	r4, r0
+  55              	.LVL2:
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Wait till Backup regulator ready flag is set */  
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
+  56              		.loc 1 149 3 is_stmt 1 view .LVU8
+  57              	.L2:
+  58              		.loc 1 149 8 view .LVU9
+  59              		.loc 1 149 9 is_stmt 0 view .LVU10
+  60 001a 074B     		ldr	r3, .L8
+  61 001c 5B68     		ldr	r3, [r3, #4]
+  62              		.loc 1 149 8 view .LVU11
+  63 001e 13F0080F 		tst	r3, #8
+  64 0022 07D1     		bne	.L7
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
+  65              		.loc 1 151 5 is_stmt 1 view .LVU12
+  66              		.loc 1 151 9 is_stmt 0 view .LVU13
+  67 0024 FFF7FEFF 		bl	HAL_GetTick
+  68              	.LVL3:
+  69              		.loc 1 151 23 view .LVU14
+  70 0028 001B     		subs	r0, r0, r4
+  71              		.loc 1 151 7 view .LVU15
+  72 002a B0F57A7F 		cmp	r0, #1000
+  73 002e F4D9     		bls	.L2
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       return HAL_TIMEOUT;
+  74              		.loc 1 153 14 view .LVU16
+  75 0030 0320     		movs	r0, #3
+  76 0032 00E0     		b	.L3
+ARM GAS  /tmp/cc97GYnP.s 			page 5
+
+
+  77              	.L7:
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     } 
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   }
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   return HAL_OK;
+  78              		.loc 1 156 10 view .LVU17
+  79 0034 0020     		movs	r0, #0
+  80              	.L3:
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+  81              		.loc 1 157 1 view .LVU18
+  82 0036 10BD     		pop	{r4, pc}
+  83              	.LVL4:
+  84              	.L9:
+  85              		.loc 1 157 1 view .LVU19
+  86              		.align	2
+  87              	.L8:
+  88 0038 00700040 		.word	1073770496
+  89              		.cfi_endproc
+  90              	.LFE141:
+  92              		.section	.text.HAL_PWREx_DisableBkUpReg,"ax",%progbits
+  93              		.align	1
+  94              		.global	HAL_PWREx_DisableBkUpReg
+  95              		.syntax unified
+  96              		.thumb
+  97              		.thumb_func
+  98              		.fpu fpv5-d16
+ 100              	HAL_PWREx_DisableBkUpReg:
+ 101              	.LFB142:
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief Disables the Backup Regulator.
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval HAL status
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+ 102              		.loc 1 164 1 is_stmt 1 view -0
+ 103              		.cfi_startproc
+ 104              		@ args = 0, pretend = 0, frame = 0
+ 105              		@ frame_needed = 0, uses_anonymous_args = 0
+ 106 0000 10B5     		push	{r4, lr}
+ 107              	.LCFI1:
+ 108              		.cfi_def_cfa_offset 8
+ 109              		.cfi_offset 4, -8
+ 110              		.cfi_offset 14, -4
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   uint32_t tickstart = 0;
+ 111              		.loc 1 165 3 view .LVU21
+ 112              	.LVL5:
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Disable Backup regulator */
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
+ 113              		.loc 1 168 3 view .LVU22
+ 114              		.loc 1 168 13 is_stmt 0 view .LVU23
+ 115 0002 0D4B     		ldr	r3, .L17
+ 116 0004 5A68     		ldr	r2, [r3, #4]
+ 117 0006 22F40072 		bic	r2, r2, #512
+ 118 000a 5A60     		str	r2, [r3, #4]
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Workaround for the following hardware bug: */
+ARM GAS  /tmp/cc97GYnP.s 			page 6
+
+
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   PWR->CSR1 |= PWR_CSR1_EIWUP;
+ 119              		.loc 1 172 3 is_stmt 1 view .LVU24
+ 120              		.loc 1 172 13 is_stmt 0 view .LVU25
+ 121 000c 5A68     		ldr	r2, [r3, #4]
+ 122 000e 42F48072 		orr	r2, r2, #256
+ 123 0012 5A60     		str	r2, [r3, #4]
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Get tick */
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick();
+ 124              		.loc 1 175 3 is_stmt 1 view .LVU26
+ 125              		.loc 1 175 15 is_stmt 0 view .LVU27
+ 126 0014 FFF7FEFF 		bl	HAL_GetTick
+ 127              	.LVL6:
+ 128 0018 0446     		mov	r4, r0
+ 129              	.LVL7:
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Wait till Backup regulator ready flag is set */  
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
+ 130              		.loc 1 178 3 is_stmt 1 view .LVU28
+ 131              	.L11:
+ 132              		.loc 1 178 8 view .LVU29
+ 133              		.loc 1 178 9 is_stmt 0 view .LVU30
+ 134 001a 074B     		ldr	r3, .L17
+ 135 001c 5B68     		ldr	r3, [r3, #4]
+ 136              		.loc 1 178 8 view .LVU31
+ 137 001e 13F0080F 		tst	r3, #8
+ 138 0022 07D0     		beq	.L16
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
+ 139              		.loc 1 180 5 is_stmt 1 view .LVU32
+ 140              		.loc 1 180 9 is_stmt 0 view .LVU33
+ 141 0024 FFF7FEFF 		bl	HAL_GetTick
+ 142              	.LVL8:
+ 143              		.loc 1 180 23 view .LVU34
+ 144 0028 001B     		subs	r0, r0, r4
+ 145              		.loc 1 180 7 view .LVU35
+ 146 002a B0F57A7F 		cmp	r0, #1000
+ 147 002e F4D9     		bls	.L11
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       return HAL_TIMEOUT;
+ 148              		.loc 1 182 14 view .LVU36
+ 149 0030 0320     		movs	r0, #3
+ 150 0032 00E0     		b	.L12
+ 151              	.L16:
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     } 
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   }
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   return HAL_OK;
+ 152              		.loc 1 185 10 view .LVU37
+ 153 0034 0020     		movs	r0, #0
+ 154              	.L12:
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 155              		.loc 1 186 1 view .LVU38
+ 156 0036 10BD     		pop	{r4, pc}
+ 157              	.LVL9:
+ 158              	.L18:
+ 159              		.loc 1 186 1 view .LVU39
+ARM GAS  /tmp/cc97GYnP.s 			page 7
+
+
+ 160              		.align	2
+ 161              	.L17:
+ 162 0038 00700040 		.word	1073770496
+ 163              		.cfi_endproc
+ 164              	.LFE142:
+ 166              		.section	.text.HAL_PWREx_EnableFlashPowerDown,"ax",%progbits
+ 167              		.align	1
+ 168              		.global	HAL_PWREx_EnableFlashPowerDown
+ 169              		.syntax unified
+ 170              		.thumb
+ 171              		.thumb_func
+ 172              		.fpu fpv5-d16
+ 174              	HAL_PWREx_EnableFlashPowerDown:
+ 175              	.LFB143:
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief Enables the Flash Power Down in Stop mode.
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval None
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableFlashPowerDown(void)
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+ 176              		.loc 1 193 1 is_stmt 1 view -0
+ 177              		.cfi_startproc
+ 178              		@ args = 0, pretend = 0, frame = 0
+ 179              		@ frame_needed = 0, uses_anonymous_args = 0
+ 180              		@ link register save eliminated.
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Enable the Flash Power Down */
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   PWR->CR1 |= PWR_CR1_FPDS;
+ 181              		.loc 1 195 3 view .LVU41
+ 182              		.loc 1 195 12 is_stmt 0 view .LVU42
+ 183 0000 024A     		ldr	r2, .L20
+ 184 0002 1368     		ldr	r3, [r2]
+ 185 0004 43F40073 		orr	r3, r3, #512
+ 186 0008 1360     		str	r3, [r2]
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 187              		.loc 1 196 1 view .LVU43
+ 188 000a 7047     		bx	lr
+ 189              	.L21:
+ 190              		.align	2
+ 191              	.L20:
+ 192 000c 00700040 		.word	1073770496
+ 193              		.cfi_endproc
+ 194              	.LFE143:
+ 196              		.section	.text.HAL_PWREx_DisableFlashPowerDown,"ax",%progbits
+ 197              		.align	1
+ 198              		.global	HAL_PWREx_DisableFlashPowerDown
+ 199              		.syntax unified
+ 200              		.thumb
+ 201              		.thumb_func
+ 202              		.fpu fpv5-d16
+ 204              	HAL_PWREx_DisableFlashPowerDown:
+ 205              	.LFB144:
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief Disables the Flash Power Down in Stop mode.
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval None
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ARM GAS  /tmp/cc97GYnP.s 			page 8
+
+
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableFlashPowerDown(void)
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+ 206              		.loc 1 203 1 is_stmt 1 view -0
+ 207              		.cfi_startproc
+ 208              		@ args = 0, pretend = 0, frame = 0
+ 209              		@ frame_needed = 0, uses_anonymous_args = 0
+ 210              		@ link register save eliminated.
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Disable the Flash Power Down */
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
+ 211              		.loc 1 205 3 view .LVU45
+ 212              		.loc 1 205 12 is_stmt 0 view .LVU46
+ 213 0000 024A     		ldr	r2, .L23
+ 214 0002 1368     		ldr	r3, [r2]
+ 215 0004 23F40073 		bic	r3, r3, #512
+ 216 0008 1360     		str	r3, [r2]
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 217              		.loc 1 206 1 view .LVU47
+ 218 000a 7047     		bx	lr
+ 219              	.L24:
+ 220              		.align	2
+ 221              	.L23:
+ 222 000c 00700040 		.word	1073770496
+ 223              		.cfi_endproc
+ 224              	.LFE144:
+ 226              		.section	.text.HAL_PWREx_EnableMainRegulatorLowVoltage,"ax",%progbits
+ 227              		.align	1
+ 228              		.global	HAL_PWREx_EnableMainRegulatorLowVoltage
+ 229              		.syntax unified
+ 230              		.thumb
+ 231              		.thumb_func
+ 232              		.fpu fpv5-d16
+ 234              	HAL_PWREx_EnableMainRegulatorLowVoltage:
+ 235              	.LFB145:
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief Enables Main Regulator low voltage mode.
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval None
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+ 236              		.loc 1 213 1 is_stmt 1 view -0
+ 237              		.cfi_startproc
+ 238              		@ args = 0, pretend = 0, frame = 0
+ 239              		@ frame_needed = 0, uses_anonymous_args = 0
+ 240              		@ link register save eliminated.
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Enable Main regulator low voltage */
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   PWR->CR1 |= PWR_CR1_MRUDS;
+ 241              		.loc 1 215 3 view .LVU49
+ 242              		.loc 1 215 12 is_stmt 0 view .LVU50
+ 243 0000 024A     		ldr	r2, .L26
+ 244 0002 1368     		ldr	r3, [r2]
+ 245 0004 43F40063 		orr	r3, r3, #2048
+ 246 0008 1360     		str	r3, [r2]
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 247              		.loc 1 216 1 view .LVU51
+ 248 000a 7047     		bx	lr
+ 249              	.L27:
+ARM GAS  /tmp/cc97GYnP.s 			page 9
+
+
+ 250              		.align	2
+ 251              	.L26:
+ 252 000c 00700040 		.word	1073770496
+ 253              		.cfi_endproc
+ 254              	.LFE145:
+ 256              		.section	.text.HAL_PWREx_DisableMainRegulatorLowVoltage,"ax",%progbits
+ 257              		.align	1
+ 258              		.global	HAL_PWREx_DisableMainRegulatorLowVoltage
+ 259              		.syntax unified
+ 260              		.thumb
+ 261              		.thumb_func
+ 262              		.fpu fpv5-d16
+ 264              	HAL_PWREx_DisableMainRegulatorLowVoltage:
+ 265              	.LFB146:
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief Disables Main Regulator low voltage mode.
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval None
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {  
+ 266              		.loc 1 223 1 is_stmt 1 view -0
+ 267              		.cfi_startproc
+ 268              		@ args = 0, pretend = 0, frame = 0
+ 269              		@ frame_needed = 0, uses_anonymous_args = 0
+ 270              		@ link register save eliminated.
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Disable Main regulator low voltage */
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
+ 271              		.loc 1 225 3 view .LVU53
+ 272              		.loc 1 225 12 is_stmt 0 view .LVU54
+ 273 0000 024A     		ldr	r2, .L29
+ 274 0002 1368     		ldr	r3, [r2]
+ 275 0004 23F40063 		bic	r3, r3, #2048
+ 276 0008 1360     		str	r3, [r2]
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 277              		.loc 1 226 1 view .LVU55
+ 278 000a 7047     		bx	lr
+ 279              	.L30:
+ 280              		.align	2
+ 281              	.L29:
+ 282 000c 00700040 		.word	1073770496
+ 283              		.cfi_endproc
+ 284              	.LFE146:
+ 286              		.section	.text.HAL_PWREx_EnableLowRegulatorLowVoltage,"ax",%progbits
+ 287              		.align	1
+ 288              		.global	HAL_PWREx_EnableLowRegulatorLowVoltage
+ 289              		.syntax unified
+ 290              		.thumb
+ 291              		.thumb_func
+ 292              		.fpu fpv5-d16
+ 294              	HAL_PWREx_EnableLowRegulatorLowVoltage:
+ 295              	.LFB147:
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief Enables Low Power Regulator low voltage mode.
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval None
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ARM GAS  /tmp/cc97GYnP.s 			page 10
+
+
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+ 296              		.loc 1 233 1 is_stmt 1 view -0
+ 297              		.cfi_startproc
+ 298              		@ args = 0, pretend = 0, frame = 0
+ 299              		@ frame_needed = 0, uses_anonymous_args = 0
+ 300              		@ link register save eliminated.
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Enable low power regulator */
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   PWR->CR1 |= PWR_CR1_LPUDS;
+ 301              		.loc 1 235 3 view .LVU57
+ 302              		.loc 1 235 12 is_stmt 0 view .LVU58
+ 303 0000 024A     		ldr	r2, .L32
+ 304 0002 1368     		ldr	r3, [r2]
+ 305 0004 43F48063 		orr	r3, r3, #1024
+ 306 0008 1360     		str	r3, [r2]
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 307              		.loc 1 236 1 view .LVU59
+ 308 000a 7047     		bx	lr
+ 309              	.L33:
+ 310              		.align	2
+ 311              	.L32:
+ 312 000c 00700040 		.word	1073770496
+ 313              		.cfi_endproc
+ 314              	.LFE147:
+ 316              		.section	.text.HAL_PWREx_DisableLowRegulatorLowVoltage,"ax",%progbits
+ 317              		.align	1
+ 318              		.global	HAL_PWREx_DisableLowRegulatorLowVoltage
+ 319              		.syntax unified
+ 320              		.thumb
+ 321              		.thumb_func
+ 322              		.fpu fpv5-d16
+ 324              	HAL_PWREx_DisableLowRegulatorLowVoltage:
+ 325              	.LFB148:
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief Disables Low Power Regulator low voltage mode.
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval None
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+ 326              		.loc 1 243 1 is_stmt 1 view -0
+ 327              		.cfi_startproc
+ 328              		@ args = 0, pretend = 0, frame = 0
+ 329              		@ frame_needed = 0, uses_anonymous_args = 0
+ 330              		@ link register save eliminated.
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Disable low power regulator */
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
+ 331              		.loc 1 245 3 view .LVU61
+ 332              		.loc 1 245 12 is_stmt 0 view .LVU62
+ 333 0000 024A     		ldr	r2, .L35
+ 334 0002 1368     		ldr	r3, [r2]
+ 335 0004 23F48063 		bic	r3, r3, #1024
+ 336 0008 1360     		str	r3, [r2]
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 337              		.loc 1 246 1 view .LVU63
+ 338 000a 7047     		bx	lr
+ 339              	.L36:
+ARM GAS  /tmp/cc97GYnP.s 			page 11
+
+
+ 340              		.align	2
+ 341              	.L35:
+ 342 000c 00700040 		.word	1073770496
+ 343              		.cfi_endproc
+ 344              	.LFE148:
+ 346              		.section	.text.HAL_PWREx_EnableOverDrive,"ax",%progbits
+ 347              		.align	1
+ 348              		.global	HAL_PWREx_EnableOverDrive
+ 349              		.syntax unified
+ 350              		.thumb
+ 351              		.thumb_func
+ 352              		.fpu fpv5-d16
+ 354              	HAL_PWREx_EnableOverDrive:
+ 355              	.LFB149:
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief  Activates the Over-Drive mode.
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note   This mode allows the CPU and the core logic to operate at a higher frequency
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).   
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         critical tasks and when the system clock source is either HSI or HSE. 
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         The peripheral clocks must be enabled once the Over-drive mode is activated.   
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval HAL status
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+ 356              		.loc 1 259 1 is_stmt 1 view -0
+ 357              		.cfi_startproc
+ 358              		@ args = 0, pretend = 0, frame = 8
+ 359              		@ frame_needed = 0, uses_anonymous_args = 0
+ 360 0000 10B5     		push	{r4, lr}
+ 361              	.LCFI2:
+ 362              		.cfi_def_cfa_offset 8
+ 363              		.cfi_offset 4, -8
+ 364              		.cfi_offset 14, -4
+ 365 0002 82B0     		sub	sp, sp, #8
+ 366              	.LCFI3:
+ 367              		.cfi_def_cfa_offset 16
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   uint32_t tickstart = 0;
+ 368              		.loc 1 260 3 view .LVU65
+ 369              	.LVL10:
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   __HAL_RCC_PWR_CLK_ENABLE();
+ 370              		.loc 1 262 3 view .LVU66
+ 371              	.LBB2:
+ 372              		.loc 1 262 3 view .LVU67
+ 373              		.loc 1 262 3 view .LVU68
+ 374 0004 1B4B     		ldr	r3, .L48
+ 375 0006 1A6C     		ldr	r2, [r3, #64]
+ 376 0008 42F08052 		orr	r2, r2, #268435456
+ 377 000c 1A64     		str	r2, [r3, #64]
+ 378              		.loc 1 262 3 view .LVU69
+ 379 000e 1B6C     		ldr	r3, [r3, #64]
+ 380 0010 03F08053 		and	r3, r3, #268435456
+ 381 0014 0193     		str	r3, [sp, #4]
+ 382              		.loc 1 262 3 view .LVU70
+ARM GAS  /tmp/cc97GYnP.s 			page 12
+
+
+ 383 0016 019B     		ldr	r3, [sp, #4]
+ 384              	.LBE2:
+ 385              		.loc 1 262 3 view .LVU71
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Enable the Over-drive to extend the clock frequency to 216 MHz */
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   __HAL_PWR_OVERDRIVE_ENABLE();
+ 386              		.loc 1 265 3 view .LVU72
+ 387 0018 174A     		ldr	r2, .L48+4
+ 388 001a 1368     		ldr	r3, [r2]
+ 389 001c 43F48033 		orr	r3, r3, #65536
+ 390 0020 1360     		str	r3, [r2]
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Get tick */
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick();
+ 391              		.loc 1 268 3 view .LVU73
+ 392              		.loc 1 268 15 is_stmt 0 view .LVU74
+ 393 0022 FFF7FEFF 		bl	HAL_GetTick
+ 394              	.LVL11:
+ 395 0026 0446     		mov	r4, r0
+ 396              	.LVL12:
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+ 397              		.loc 1 270 3 is_stmt 1 view .LVU75
+ 398              	.L38:
+ 399              		.loc 1 270 8 view .LVU76
+ 400              		.loc 1 270 10 is_stmt 0 view .LVU77
+ 401 0028 134B     		ldr	r3, .L48+4
+ 402 002a 5B68     		ldr	r3, [r3, #4]
+ 403              		.loc 1 270 8 view .LVU78
+ 404 002c 13F4803F 		tst	r3, #65536
+ 405 0030 08D1     		bne	.L46
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+ 406              		.loc 1 272 5 is_stmt 1 view .LVU79
+ 407              		.loc 1 272 9 is_stmt 0 view .LVU80
+ 408 0032 FFF7FEFF 		bl	HAL_GetTick
+ 409              	.LVL13:
+ 410              		.loc 1 272 23 view .LVU81
+ 411 0036 001B     		subs	r0, r0, r4
+ 412              		.loc 1 272 7 view .LVU82
+ 413 0038 B0F57A7F 		cmp	r0, #1000
+ 414 003c F4D9     		bls	.L38
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       return HAL_TIMEOUT;
+ 415              		.loc 1 274 14 view .LVU83
+ 416 003e 0320     		movs	r0, #3
+ 417              	.L39:
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     }
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   }
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Enable the Over-drive switch */
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Get tick */
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick();
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+ARM GAS  /tmp/cc97GYnP.s 			page 13
+
+
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       return HAL_TIMEOUT;
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     }
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   } 
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   return HAL_OK;
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 418              		.loc 1 292 1 view .LVU84
+ 419 0040 02B0     		add	sp, sp, #8
+ 420              	.LCFI4:
+ 421              		.cfi_remember_state
+ 422              		.cfi_def_cfa_offset 8
+ 423              		@ sp needed
+ 424 0042 10BD     		pop	{r4, pc}
+ 425              	.LVL14:
+ 426              	.L46:
+ 427              	.LCFI5:
+ 428              		.cfi_restore_state
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 429              		.loc 1 279 3 is_stmt 1 view .LVU85
+ 430 0044 0C4A     		ldr	r2, .L48+4
+ 431 0046 1368     		ldr	r3, [r2]
+ 432 0048 43F40033 		orr	r3, r3, #131072
+ 433 004c 1360     		str	r3, [r2]
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 434              		.loc 1 282 3 view .LVU86
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 435              		.loc 1 282 15 is_stmt 0 view .LVU87
+ 436 004e FFF7FEFF 		bl	HAL_GetTick
+ 437              	.LVL15:
+ 438 0052 0446     		mov	r4, r0
+ 439              	.LVL16:
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 440              		.loc 1 284 3 is_stmt 1 view .LVU88
+ 441              	.L41:
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 442              		.loc 1 284 8 view .LVU89
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 443              		.loc 1 284 10 is_stmt 0 view .LVU90
+ 444 0054 084B     		ldr	r3, .L48+4
+ 445 0056 5B68     		ldr	r3, [r3, #4]
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 446              		.loc 1 284 8 view .LVU91
+ 447 0058 13F4003F 		tst	r3, #131072
+ 448 005c 07D1     		bne	.L47
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 449              		.loc 1 286 5 is_stmt 1 view .LVU92
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 450              		.loc 1 286 9 is_stmt 0 view .LVU93
+ 451 005e FFF7FEFF 		bl	HAL_GetTick
+ 452              	.LVL17:
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 453              		.loc 1 286 23 view .LVU94
+ 454 0062 001B     		subs	r0, r0, r4
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 455              		.loc 1 286 7 view .LVU95
+ARM GAS  /tmp/cc97GYnP.s 			page 14
+
+
+ 456 0064 B0F57A7F 		cmp	r0, #1000
+ 457 0068 F4D9     		bls	.L41
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     }
+ 458              		.loc 1 288 14 view .LVU96
+ 459 006a 0320     		movs	r0, #3
+ 460 006c E8E7     		b	.L39
+ 461              	.L47:
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 462              		.loc 1 291 10 view .LVU97
+ 463 006e 0020     		movs	r0, #0
+ 464 0070 E6E7     		b	.L39
+ 465              	.L49:
+ 466 0072 00BF     		.align	2
+ 467              	.L48:
+ 468 0074 00380240 		.word	1073887232
+ 469 0078 00700040 		.word	1073770496
+ 470              		.cfi_endproc
+ 471              	.LFE149:
+ 473              		.section	.text.HAL_PWREx_DisableOverDrive,"ax",%progbits
+ 474              		.align	1
+ 475              		.global	HAL_PWREx_DisableOverDrive
+ 476              		.syntax unified
+ 477              		.thumb
+ 478              		.thumb_func
+ 479              		.fpu fpv5-d16
+ 481              	HAL_PWREx_DisableOverDrive:
+ 482              	.LFB150:
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief  Deactivates the Over-Drive mode.
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note   This mode allows the CPU and the core logic to operate at a higher frequency
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).    
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         critical tasks and when the system clock source is either HSI or HSE. 
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         The peripheral clocks must be enabled once the Over-drive mode is activated.
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval HAL status
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+ 483              		.loc 1 305 1 is_stmt 1 view -0
+ 484              		.cfi_startproc
+ 485              		@ args = 0, pretend = 0, frame = 8
+ 486              		@ frame_needed = 0, uses_anonymous_args = 0
+ 487 0000 10B5     		push	{r4, lr}
+ 488              	.LCFI6:
+ 489              		.cfi_def_cfa_offset 8
+ 490              		.cfi_offset 4, -8
+ 491              		.cfi_offset 14, -4
+ 492 0002 82B0     		sub	sp, sp, #8
+ 493              	.LCFI7:
+ 494              		.cfi_def_cfa_offset 16
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   uint32_t tickstart = 0;
+ 495              		.loc 1 306 3 view .LVU99
+ 496              	.LVL18:
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   __HAL_RCC_PWR_CLK_ENABLE();
+ARM GAS  /tmp/cc97GYnP.s 			page 15
+
+
+ 497              		.loc 1 308 3 view .LVU100
+ 498              	.LBB3:
+ 499              		.loc 1 308 3 view .LVU101
+ 500              		.loc 1 308 3 view .LVU102
+ 501 0004 1B4B     		ldr	r3, .L61
+ 502 0006 1A6C     		ldr	r2, [r3, #64]
+ 503 0008 42F08052 		orr	r2, r2, #268435456
+ 504 000c 1A64     		str	r2, [r3, #64]
+ 505              		.loc 1 308 3 view .LVU103
+ 506 000e 1B6C     		ldr	r3, [r3, #64]
+ 507 0010 03F08053 		and	r3, r3, #268435456
+ 508 0014 0193     		str	r3, [sp, #4]
+ 509              		.loc 1 308 3 view .LVU104
+ 510 0016 019B     		ldr	r3, [sp, #4]
+ 511              	.LBE3:
+ 512              		.loc 1 308 3 view .LVU105
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Disable the Over-drive switch */
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
+ 513              		.loc 1 311 3 view .LVU106
+ 514 0018 174A     		ldr	r2, .L61+4
+ 515 001a 1368     		ldr	r3, [r2]
+ 516 001c 23F40033 		bic	r3, r3, #131072
+ 517 0020 1360     		str	r3, [r2]
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Get tick */
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick();
+ 518              		.loc 1 314 3 view .LVU107
+ 519              		.loc 1 314 15 is_stmt 0 view .LVU108
+ 520 0022 FFF7FEFF 		bl	HAL_GetTick
+ 521              	.LVL19:
+ 522 0026 0446     		mov	r4, r0
+ 523              	.LVL20:
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****  
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+ 524              		.loc 1 316 3 is_stmt 1 view .LVU109
+ 525              	.L51:
+ 526              		.loc 1 316 8 view .LVU110
+ 527              		.loc 1 316 9 is_stmt 0 view .LVU111
+ 528 0028 134B     		ldr	r3, .L61+4
+ 529 002a 5B68     		ldr	r3, [r3, #4]
+ 530              		.loc 1 316 8 view .LVU112
+ 531 002c 13F4003F 		tst	r3, #131072
+ 532 0030 08D0     		beq	.L59
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+ 533              		.loc 1 318 5 is_stmt 1 view .LVU113
+ 534              		.loc 1 318 9 is_stmt 0 view .LVU114
+ 535 0032 FFF7FEFF 		bl	HAL_GetTick
+ 536              	.LVL21:
+ 537              		.loc 1 318 23 view .LVU115
+ 538 0036 001B     		subs	r0, r0, r4
+ 539              		.loc 1 318 7 view .LVU116
+ 540 0038 B0F57A7F 		cmp	r0, #1000
+ 541 003c F4D9     		bls	.L51
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       return HAL_TIMEOUT;
+ARM GAS  /tmp/cc97GYnP.s 			page 16
+
+
+ 542              		.loc 1 320 14 view .LVU117
+ 543 003e 0320     		movs	r0, #3
+ 544              	.L52:
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     }
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   } 
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Disable the Over-drive */
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   __HAL_PWR_OVERDRIVE_DISABLE();
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Get tick */
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick();
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       return HAL_TIMEOUT;
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     }
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   }
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   return HAL_OK;
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 545              		.loc 1 339 1 view .LVU118
+ 546 0040 02B0     		add	sp, sp, #8
+ 547              	.LCFI8:
+ 548              		.cfi_remember_state
+ 549              		.cfi_def_cfa_offset 8
+ 550              		@ sp needed
+ 551 0042 10BD     		pop	{r4, pc}
+ 552              	.LVL22:
+ 553              	.L59:
+ 554              	.LCFI9:
+ 555              		.cfi_restore_state
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 556              		.loc 1 325 3 is_stmt 1 view .LVU119
+ 557 0044 0C4A     		ldr	r2, .L61+4
+ 558 0046 1368     		ldr	r3, [r2]
+ 559 0048 23F48033 		bic	r3, r3, #65536
+ 560 004c 1360     		str	r3, [r2]
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 561              		.loc 1 328 3 view .LVU120
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 562              		.loc 1 328 15 is_stmt 0 view .LVU121
+ 563 004e FFF7FEFF 		bl	HAL_GetTick
+ 564              	.LVL23:
+ 565 0052 0446     		mov	r4, r0
+ 566              	.LVL24:
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 567              		.loc 1 330 3 is_stmt 1 view .LVU122
+ 568              	.L54:
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 569              		.loc 1 330 8 view .LVU123
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 570              		.loc 1 330 9 is_stmt 0 view .LVU124
+ 571 0054 084B     		ldr	r3, .L61+4
+ 572 0056 5B68     		ldr	r3, [r3, #4]
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ARM GAS  /tmp/cc97GYnP.s 			page 17
+
+
+ 573              		.loc 1 330 8 view .LVU125
+ 574 0058 13F4803F 		tst	r3, #65536
+ 575 005c 07D0     		beq	.L60
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 576              		.loc 1 332 5 is_stmt 1 view .LVU126
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 577              		.loc 1 332 9 is_stmt 0 view .LVU127
+ 578 005e FFF7FEFF 		bl	HAL_GetTick
+ 579              	.LVL25:
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 580              		.loc 1 332 23 view .LVU128
+ 581 0062 001B     		subs	r0, r0, r4
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 582              		.loc 1 332 7 view .LVU129
+ 583 0064 B0F57A7F 		cmp	r0, #1000
+ 584 0068 F4D9     		bls	.L54
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     }
+ 585              		.loc 1 334 14 view .LVU130
+ 586 006a 0320     		movs	r0, #3
+ 587 006c E8E7     		b	.L52
+ 588              	.L60:
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 589              		.loc 1 338 10 view .LVU131
+ 590 006e 0020     		movs	r0, #0
+ 591 0070 E6E7     		b	.L52
+ 592              	.L62:
+ 593 0072 00BF     		.align	2
+ 594              	.L61:
+ 595 0074 00380240 		.word	1073887232
+ 596 0078 00700040 		.word	1073770496
+ 597              		.cfi_endproc
+ 598              	.LFE150:
+ 600              		.section	.text.HAL_PWREx_EnterUnderDriveSTOPMode,"ax",%progbits
+ 601              		.align	1
+ 602              		.global	HAL_PWREx_EnterUnderDriveSTOPMode
+ 603              		.syntax unified
+ 604              		.thumb
+ 605              		.thumb_func
+ 606              		.fpu fpv5-d16
+ 608              	HAL_PWREx_EnterUnderDriveSTOPMode:
+ 609              	.LVL26:
+ 610              	.LFB151:
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief  Enters in Under-Drive STOP mode.
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * 
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note    This mode can be selected only when the Under-Drive is already active 
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *   
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note    This mode is enabled only with STOP low power mode.
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *          mode is only available when the main regulator or the low power regulator 
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *          is in low voltage mode
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *        
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note   If the Under-drive mode was enabled, it is automatically disabled after 
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         exiting Stop mode. 
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         When the voltage regulator operates in Under-drive mode, an additional  
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         startup delay is induced when waking up from Stop mode.
+ARM GAS  /tmp/cc97GYnP.s 			page 18
+
+
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *                    
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *   
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, 
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         the HSI RC oscillator is selected as system clock.
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *           
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note   When the voltage regulator operates in low power mode, an additional 
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         startup delay is incurred when waking up from Stop mode. 
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         By keeping the internal regulator ON during Stop mode, the consumption 
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         is higher although the startup time is reduced.
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *     
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @param  Regulator specifies the regulator state in STOP mode.
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode 
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *                 and Flash memory in power-down when the device is in Stop under-drive mode
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode 
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *                and Flash memory in power-down when the device is in Stop under-drive mode
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @param  STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval None
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+ 611              		.loc 1 379 1 is_stmt 1 view -0
+ 612              		.cfi_startproc
+ 613              		@ args = 0, pretend = 0, frame = 8
+ 614              		@ frame_needed = 0, uses_anonymous_args = 0
+ 615              		.loc 1 379 1 is_stmt 0 view .LVU133
+ 616 0000 70B5     		push	{r4, r5, r6, lr}
+ 617              	.LCFI10:
+ 618              		.cfi_def_cfa_offset 16
+ 619              		.cfi_offset 4, -16
+ 620              		.cfi_offset 5, -12
+ 621              		.cfi_offset 6, -8
+ 622              		.cfi_offset 14, -4
+ 623 0002 82B0     		sub	sp, sp, #8
+ 624              	.LCFI11:
+ 625              		.cfi_def_cfa_offset 24
+ 626 0004 0646     		mov	r6, r0
+ 627 0006 0D46     		mov	r5, r1
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   uint32_t tempreg = 0;
+ 628              		.loc 1 380 3 is_stmt 1 view .LVU134
+ 629              	.LVL27:
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   uint32_t tickstart = 0;
+ 630              		.loc 1 381 3 view .LVU135
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Check the parameters */
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
+ 631              		.loc 1 384 3 view .LVU136
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+ 632              		.loc 1 385 3 view .LVU137
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Enable Power ctrl clock */
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   __HAL_RCC_PWR_CLK_ENABLE();
+ 633              		.loc 1 388 3 view .LVU138
+ARM GAS  /tmp/cc97GYnP.s 			page 19
+
+
+ 634              	.LBB4:
+ 635              		.loc 1 388 3 view .LVU139
+ 636              		.loc 1 388 3 view .LVU140
+ 637 0008 1E4B     		ldr	r3, .L73
+ 638 000a 1A6C     		ldr	r2, [r3, #64]
+ 639 000c 42F08052 		orr	r2, r2, #268435456
+ 640 0010 1A64     		str	r2, [r3, #64]
+ 641              		.loc 1 388 3 view .LVU141
+ 642 0012 1B6C     		ldr	r3, [r3, #64]
+ 643 0014 03F08053 		and	r3, r3, #268435456
+ 644 0018 0193     		str	r3, [sp, #4]
+ 645              		.loc 1 388 3 view .LVU142
+ 646 001a 019B     		ldr	r3, [sp, #4]
+ 647              	.LBE4:
+ 648              		.loc 1 388 3 view .LVU143
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Enable the Under-drive Mode ---------------------------------------------*/
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Clear Under-drive flag */
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   __HAL_PWR_CLEAR_ODRUDR_FLAG();
+ 649              		.loc 1 391 3 view .LVU144
+ 650 001c 1A4B     		ldr	r3, .L73+4
+ 651 001e 5968     		ldr	r1, [r3, #4]
+ 652              	.LVL28:
+ 653              		.loc 1 391 3 is_stmt 0 view .LVU145
+ 654 0020 1A4A     		ldr	r2, .L73+8
+ 655 0022 0A43     		orrs	r2, r2, r1
+ 656 0024 5A60     		str	r2, [r3, #4]
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Enable the Under-drive */ 
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   __HAL_PWR_UNDERDRIVE_ENABLE();
+ 657              		.loc 1 394 3 is_stmt 1 view .LVU146
+ 658 0026 1A68     		ldr	r2, [r3]
+ 659 0028 42F44022 		orr	r2, r2, #786432
+ 660 002c 1A60     		str	r2, [r3]
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Get tick */
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick();
+ 661              		.loc 1 397 3 view .LVU147
+ 662              		.loc 1 397 15 is_stmt 0 view .LVU148
+ 663 002e FFF7FEFF 		bl	HAL_GetTick
+ 664              	.LVL29:
+ 665              		.loc 1 397 15 view .LVU149
+ 666 0032 0446     		mov	r4, r0
+ 667              	.LVL30:
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Wait for UnderDrive mode is ready */
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
+ 668              		.loc 1 400 3 is_stmt 1 view .LVU150
+ 669              	.L64:
+ 670              		.loc 1 400 8 view .LVU151
+ 671              		.loc 1 400 9 is_stmt 0 view .LVU152
+ 672 0034 144B     		ldr	r3, .L73+4
+ 673 0036 5B68     		ldr	r3, [r3, #4]
+ 674 0038 03F44023 		and	r3, r3, #786432
+ 675              		.loc 1 400 8 view .LVU153
+ 676 003c B3F5402F 		cmp	r3, #786432
+ 677 0040 07D1     		bne	.L71
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ARM GAS  /tmp/cc97GYnP.s 			page 20
+
+
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
+ 678              		.loc 1 402 5 is_stmt 1 view .LVU154
+ 679              		.loc 1 402 9 is_stmt 0 view .LVU155
+ 680 0042 FFF7FEFF 		bl	HAL_GetTick
+ 681              	.LVL31:
+ 682              		.loc 1 402 23 view .LVU156
+ 683 0046 001B     		subs	r0, r0, r4
+ 684              		.loc 1 402 7 view .LVU157
+ 685 0048 B0F57A7F 		cmp	r0, #1000
+ 686 004c F2D9     		bls	.L64
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       return HAL_TIMEOUT;
+ 687              		.loc 1 404 14 view .LVU158
+ 688 004e 0320     		movs	r0, #3
+ 689 0050 13E0     		b	.L65
+ 690              	.L71:
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     }
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   }
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Select the regulator state in STOP mode ---------------------------------*/
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   tempreg = PWR->CR1;
+ 691              		.loc 1 409 3 is_stmt 1 view .LVU159
+ 692              		.loc 1 409 11 is_stmt 0 view .LVU160
+ 693 0052 0D4A     		ldr	r2, .L73+4
+ 694 0054 1168     		ldr	r1, [r2]
+ 695              	.LVL32:
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
+ 696              		.loc 1 411 3 is_stmt 1 view .LVU161
+ 697              		.loc 1 411 11 is_stmt 0 view .LVU162
+ 698 0056 0E4B     		ldr	r3, .L73+12
+ 699 0058 0B40     		ands	r3, r3, r1
+ 700              	.LVL33:
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   tempreg |= Regulator;
+ 701              		.loc 1 414 3 is_stmt 1 view .LVU163
+ 702              		.loc 1 414 11 is_stmt 0 view .LVU164
+ 703 005a 3343     		orrs	r3, r3, r6
+ 704              	.LVL34:
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Store the new value */
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   PWR->CR1 = tempreg;
+ 705              		.loc 1 417 3 is_stmt 1 view .LVU165
+ 706              		.loc 1 417 12 is_stmt 0 view .LVU166
+ 707 005c 1360     		str	r3, [r2]
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ 708              		.loc 1 420 3 is_stmt 1 view .LVU167
+ 709              		.loc 1 420 12 is_stmt 0 view .LVU168
+ 710 005e 0D4A     		ldr	r2, .L73+16
+ 711 0060 1369     		ldr	r3, [r2, #16]
+ 712              	.LVL35:
+ 713              		.loc 1 420 12 view .LVU169
+ 714 0062 43F00403 		orr	r3, r3, #4
+ 715 0066 1361     		str	r3, [r2, #16]
+ARM GAS  /tmp/cc97GYnP.s 			page 21
+
+
+ 716              	.LVL36:
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Select STOP mode entry --------------------------------------------------*/
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   if(STOPEntry == PWR_SLEEPENTRY_WFI)
+ 717              		.loc 1 423 3 is_stmt 1 view .LVU170
+ 718              		.loc 1 423 5 is_stmt 0 view .LVU171
+ 719 0068 012D     		cmp	r5, #1
+ 720 006a 08D0     		beq	.L72
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {   
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     /* Request Wait For Interrupt */
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     __WFI();
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   }
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   else
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     /* Request Wait For Event */
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     __WFE();
+ 721              		.loc 1 431 5 is_stmt 1 view .LVU172
+ 722              		.syntax unified
+ 723              	@ 431 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c" 1
+ 724 006c 20BF     		wfe
+ 725              	@ 0 "" 2
+ 726              		.thumb
+ 727              		.syntax unified
+ 728              	.L68:
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   }
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+ 729              		.loc 1 434 3 view .LVU173
+ 730              		.loc 1 434 12 is_stmt 0 view .LVU174
+ 731 006e 094A     		ldr	r2, .L73+16
+ 732 0070 1369     		ldr	r3, [r2, #16]
+ 733 0072 23F00403 		bic	r3, r3, #4
+ 734 0076 1361     		str	r3, [r2, #16]
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   return HAL_OK;  
+ 735              		.loc 1 436 3 is_stmt 1 view .LVU175
+ 736              		.loc 1 436 10 is_stmt 0 view .LVU176
+ 737 0078 0020     		movs	r0, #0
+ 738              	.LVL37:
+ 739              	.L65:
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 740              		.loc 1 437 1 view .LVU177
+ 741 007a 02B0     		add	sp, sp, #8
+ 742              	.LCFI12:
+ 743              		.cfi_remember_state
+ 744              		.cfi_def_cfa_offset 16
+ 745              		@ sp needed
+ 746 007c 70BD     		pop	{r4, r5, r6, pc}
+ 747              	.LVL38:
+ 748              	.L72:
+ 749              	.LCFI13:
+ 750              		.cfi_restore_state
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   }
+ 751              		.loc 1 426 5 is_stmt 1 view .LVU178
+ 752              		.syntax unified
+ 753              	@ 426 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c" 1
+ 754 007e 30BF     		wfi
+ARM GAS  /tmp/cc97GYnP.s 			page 22
+
+
+ 755              	@ 0 "" 2
+ 756              		.thumb
+ 757              		.syntax unified
+ 758 0080 F5E7     		b	.L68
+ 759              	.L74:
+ 760 0082 00BF     		.align	2
+ 761              	.L73:
+ 762 0084 00380240 		.word	1073887232
+ 763 0088 00700040 		.word	1073770496
+ 764 008c 00010C00 		.word	786688
+ 765 0090 FCF3FFFF 		.word	-3076
+ 766 0094 00ED00E0 		.word	-536810240
+ 767              		.cfi_endproc
+ 768              	.LFE151:
+ 770              		.section	.text.HAL_PWREx_GetVoltageRange,"ax",%progbits
+ 771              		.align	1
+ 772              		.global	HAL_PWREx_GetVoltageRange
+ 773              		.syntax unified
+ 774              		.thumb
+ 775              		.thumb_func
+ 776              		.fpu fpv5-d16
+ 778              	HAL_PWREx_GetVoltageRange:
+ 779              	.LFB152:
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief Returns Voltage Scaling Range.
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or 
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *            PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */  
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVoltageRange(void)
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+ 780              		.loc 1 445 1 view -0
+ 781              		.cfi_startproc
+ 782              		@ args = 0, pretend = 0, frame = 0
+ 783              		@ frame_needed = 0, uses_anonymous_args = 0
+ 784              		@ link register save eliminated.
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   return  (PWR->CR1 & PWR_CR1_VOS);
+ 785              		.loc 1 446 3 view .LVU180
+ 786              		.loc 1 446 15 is_stmt 0 view .LVU181
+ 787 0000 024B     		ldr	r3, .L76
+ 788 0002 1868     		ldr	r0, [r3]
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 789              		.loc 1 447 1 view .LVU182
+ 790 0004 00F44040 		and	r0, r0, #49152
+ 791 0008 7047     		bx	lr
+ 792              	.L77:
+ 793 000a 00BF     		.align	2
+ 794              	.L76:
+ 795 000c 00700040 		.word	1073770496
+ 796              		.cfi_endproc
+ 797              	.LFE152:
+ 799              		.section	.text.HAL_PWREx_ControlVoltageScaling,"ax",%progbits
+ 800              		.align	1
+ 801              		.global	HAL_PWREx_ControlVoltageScaling
+ 802              		.syntax unified
+ 803              		.thumb
+ 804              		.thumb_func
+ARM GAS  /tmp/cc97GYnP.s 			page 23
+
+
+ 805              		.fpu fpv5-d16
+ 807              	HAL_PWREx_ControlVoltageScaling:
+ 808              	.LVL39:
+ 809              	.LFB153:
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /**
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @brief Configures the main internal regulator output voltage.
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @param  VoltageScaling specifies the regulator output voltage to achieve
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *         a tradeoff between performance and power consumption.
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *                                                typical output voltage at 1.4 V,  
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *                                                system frequency up to 216 MHz.
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *                                                typical output voltage at 1.2 V,                
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *                                                system frequency up to 180 MHz.
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *                                                typical output voltage at 1.00 V,               
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *                                                system frequency up to 151 MHz.
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note To update the system clock frequency(SYSCLK):
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *        - Call the HAL_RCC_OscConfig() to configure the PLL.
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note The scale can be modified only when the HSI or HSE clock source is selected 
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *        as system clock source, otherwise the API returns HAL_ERROR.  
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   *       value in the PWR_CR1 register are not taken in account.
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @note The new voltage scale is active only when the PLL is ON.  
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   * @retval HAL Status
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   */
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** {
+ 810              		.loc 1 477 1 is_stmt 1 view -0
+ 811              		.cfi_startproc
+ 812              		@ args = 0, pretend = 0, frame = 8
+ 813              		@ frame_needed = 0, uses_anonymous_args = 0
+ 814              		.loc 1 477 1 is_stmt 0 view .LVU184
+ 815 0000 30B5     		push	{r4, r5, lr}
+ 816              	.LCFI14:
+ 817              		.cfi_def_cfa_offset 12
+ 818              		.cfi_offset 4, -12
+ 819              		.cfi_offset 5, -8
+ 820              		.cfi_offset 14, -4
+ 821 0002 83B0     		sub	sp, sp, #12
+ 822              	.LCFI15:
+ 823              		.cfi_def_cfa_offset 24
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   uint32_t tickstart = 0;
+ 824              		.loc 1 478 3 is_stmt 1 view .LVU185
+ 825              	.LVL40:
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
+ 826              		.loc 1 480 3 view .LVU186
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Enable Power ctrl clock */
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   __HAL_RCC_PWR_CLK_ENABLE();
+ARM GAS  /tmp/cc97GYnP.s 			page 24
+
+
+ 827              		.loc 1 483 3 view .LVU187
+ 828              	.LBB5:
+ 829              		.loc 1 483 3 view .LVU188
+ 830              		.loc 1 483 3 view .LVU189
+ 831 0004 2C4B     		ldr	r3, .L94
+ 832 0006 1A6C     		ldr	r2, [r3, #64]
+ 833 0008 42F08052 		orr	r2, r2, #268435456
+ 834 000c 1A64     		str	r2, [r3, #64]
+ 835              		.loc 1 483 3 view .LVU190
+ 836 000e 1A6C     		ldr	r2, [r3, #64]
+ 837 0010 02F08052 		and	r2, r2, #268435456
+ 838 0014 0092     		str	r2, [sp]
+ 839              		.loc 1 483 3 view .LVU191
+ 840 0016 009A     		ldr	r2, [sp]
+ 841              	.LBE5:
+ 842              		.loc 1 483 3 view .LVU192
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** 
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   /* Check if the PLL is used as system clock or not */
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ 843              		.loc 1 486 3 view .LVU193
+ 844              		.loc 1 486 6 is_stmt 0 view .LVU194
+ 845 0018 9B68     		ldr	r3, [r3, #8]
+ 846 001a 03F00C03 		and	r3, r3, #12
+ 847              		.loc 1 486 5 view .LVU195
+ 848 001e 082B     		cmp	r3, #8
+ 849 0020 46D0     		beq	.L86
+ 850 0022 0546     		mov	r5, r0
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     /* Disable the main PLL */
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     __HAL_RCC_PLL_DISABLE();
+ 851              		.loc 1 489 5 is_stmt 1 view .LVU196
+ 852 0024 244A     		ldr	r2, .L94
+ 853 0026 1368     		ldr	r3, [r2]
+ 854 0028 23F08073 		bic	r3, r3, #16777216
+ 855 002c 1360     		str	r3, [r2]
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     /* Get Start Tick */
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     tickstart = HAL_GetTick();    
+ 856              		.loc 1 492 5 view .LVU197
+ 857              		.loc 1 492 17 is_stmt 0 view .LVU198
+ 858 002e FFF7FEFF 		bl	HAL_GetTick
+ 859              	.LVL41:
+ 860              		.loc 1 492 17 view .LVU199
+ 861 0032 0446     		mov	r4, r0
+ 862              	.LVL42:
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     /* Wait till PLL is disabled */  
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ 863              		.loc 1 494 5 is_stmt 1 view .LVU200
+ 864              	.L80:
+ 865              		.loc 1 494 10 view .LVU201
+ 866              		.loc 1 494 11 is_stmt 0 view .LVU202
+ 867 0034 204B     		ldr	r3, .L94
+ 868 0036 1B68     		ldr	r3, [r3]
+ 869              		.loc 1 494 10 view .LVU203
+ 870 0038 13F0007F 		tst	r3, #33554432
+ 871 003c 06D0     		beq	.L91
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ARM GAS  /tmp/cc97GYnP.s 			page 25
+
+
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 872              		.loc 1 496 7 is_stmt 1 view .LVU204
+ 873              		.loc 1 496 11 is_stmt 0 view .LVU205
+ 874 003e FFF7FEFF 		bl	HAL_GetTick
+ 875              	.LVL43:
+ 876              		.loc 1 496 25 view .LVU206
+ 877 0042 031B     		subs	r3, r0, r4
+ 878              		.loc 1 496 9 view .LVU207
+ 879 0044 022B     		cmp	r3, #2
+ 880 0046 F5D9     		bls	.L80
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       {
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****         return HAL_TIMEOUT;
+ 881              		.loc 1 498 16 view .LVU208
+ 882 0048 0320     		movs	r0, #3
+ 883 004a 32E0     		b	.L79
+ 884              	.L91:
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       }
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     }
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     /* Set Range */
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+ 885              		.loc 1 503 5 is_stmt 1 view .LVU209
+ 886              	.LBB6:
+ 887              		.loc 1 503 5 view .LVU210
+ 888              		.loc 1 503 5 view .LVU211
+ 889 004c 1B4A     		ldr	r2, .L94+4
+ 890 004e 1368     		ldr	r3, [r2]
+ 891 0050 23F44043 		bic	r3, r3, #49152
+ 892 0054 1D43     		orrs	r5, r5, r3
+ 893              	.LVL44:
+ 894              		.loc 1 503 5 is_stmt 0 view .LVU212
+ 895 0056 1560     		str	r5, [r2]
+ 896              		.loc 1 503 5 is_stmt 1 view .LVU213
+ 897 0058 1368     		ldr	r3, [r2]
+ 898 005a 03F44043 		and	r3, r3, #49152
+ 899 005e 0193     		str	r3, [sp, #4]
+ 900              		.loc 1 503 5 view .LVU214
+ 901 0060 019B     		ldr	r3, [sp, #4]
+ 902              	.LBE6:
+ 903              		.loc 1 503 5 view .LVU215
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     /* Enable the main PLL */
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     __HAL_RCC_PLL_ENABLE();
+ 904              		.loc 1 506 5 view .LVU216
+ 905 0062 02F5E432 		add	r2, r2, #116736
+ 906 0066 1368     		ldr	r3, [r2]
+ 907 0068 43F08073 		orr	r3, r3, #16777216
+ 908 006c 1360     		str	r3, [r2]
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     /* Get Start Tick */
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     tickstart = HAL_GetTick();
+ 909              		.loc 1 509 5 view .LVU217
+ 910              		.loc 1 509 17 is_stmt 0 view .LVU218
+ 911 006e FFF7FEFF 		bl	HAL_GetTick
+ 912              	.LVL45:
+ 913 0072 0446     		mov	r4, r0
+ 914              	.LVL46:
+ARM GAS  /tmp/cc97GYnP.s 			page 26
+
+
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     /* Wait till PLL is ready */  
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 915              		.loc 1 511 5 is_stmt 1 view .LVU219
+ 916              	.L82:
+ 917              		.loc 1 511 10 view .LVU220
+ 918              		.loc 1 511 11 is_stmt 0 view .LVU221
+ 919 0074 104B     		ldr	r3, .L94
+ 920 0076 1B68     		ldr	r3, [r3]
+ 921              		.loc 1 511 10 view .LVU222
+ 922 0078 13F0007F 		tst	r3, #33554432
+ 923 007c 06D1     		bne	.L92
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 924              		.loc 1 513 7 is_stmt 1 view .LVU223
+ 925              		.loc 1 513 11 is_stmt 0 view .LVU224
+ 926 007e FFF7FEFF 		bl	HAL_GetTick
+ 927              	.LVL47:
+ 928              		.loc 1 513 25 view .LVU225
+ 929 0082 001B     		subs	r0, r0, r4
+ 930              		.loc 1 513 9 view .LVU226
+ 931 0084 0228     		cmp	r0, #2
+ 932 0086 F5D9     		bls	.L82
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       {
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****         return HAL_TIMEOUT;
+ 933              		.loc 1 515 16 view .LVU227
+ 934 0088 0320     		movs	r0, #3
+ 935 008a 12E0     		b	.L79
+ 936              	.L92:
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       } 
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     }
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     /* Get Start Tick */
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     tickstart = HAL_GetTick();
+ 937              		.loc 1 520 5 is_stmt 1 view .LVU228
+ 938              		.loc 1 520 17 is_stmt 0 view .LVU229
+ 939 008c FFF7FEFF 		bl	HAL_GetTick
+ 940              	.LVL48:
+ 941 0090 0446     		mov	r4, r0
+ 942              	.LVL49:
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+ 943              		.loc 1 521 5 is_stmt 1 view .LVU230
+ 944              	.L84:
+ 945              		.loc 1 521 10 view .LVU231
+ 946              		.loc 1 521 12 is_stmt 0 view .LVU232
+ 947 0092 0A4B     		ldr	r3, .L94+4
+ 948 0094 5B68     		ldr	r3, [r3, #4]
+ 949              		.loc 1 521 10 view .LVU233
+ 950 0096 13F4804F 		tst	r3, #16384
+ 951 009a 07D1     		bne	.L93
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     {
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+ 952              		.loc 1 523 7 is_stmt 1 view .LVU234
+ 953              		.loc 1 523 11 is_stmt 0 view .LVU235
+ 954 009c FFF7FEFF 		bl	HAL_GetTick
+ 955              	.LVL50:
+ 956              		.loc 1 523 25 view .LVU236
+ 957 00a0 001B     		subs	r0, r0, r4
+ARM GAS  /tmp/cc97GYnP.s 			page 27
+
+
+ 958              		.loc 1 523 9 view .LVU237
+ 959 00a2 B0F57A7F 		cmp	r0, #1000
+ 960 00a6 F4D9     		bls	.L84
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       {
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****         return HAL_TIMEOUT;
+ 961              		.loc 1 525 16 view .LVU238
+ 962 00a8 0320     		movs	r0, #3
+ 963 00aa 02E0     		b	.L79
+ 964              	.L93:
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****       } 
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     }
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   }
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   else
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   {
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****     return HAL_ERROR;
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   }
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   return HAL_OK;
+ 965              		.loc 1 533 10 view .LVU239
+ 966 00ac 0020     		movs	r0, #0
+ 967 00ae 00E0     		b	.L79
+ 968              	.LVL51:
+ 969              	.L86:
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c ****   }
+ 970              		.loc 1 531 12 view .LVU240
+ 971 00b0 0120     		movs	r0, #1
+ 972              	.LVL52:
+ 973              	.L79:
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** }
+ 974              		.loc 1 534 1 view .LVU241
+ 975 00b2 03B0     		add	sp, sp, #12
+ 976              	.LCFI16:
+ 977              		.cfi_def_cfa_offset 12
+ 978              		@ sp needed
+ 979 00b4 30BD     		pop	{r4, r5, pc}
+ 980              	.L95:
+ 981 00b6 00BF     		.align	2
+ 982              	.L94:
+ 983 00b8 00380240 		.word	1073887232
+ 984 00bc 00700040 		.word	1073770496
+ 985              		.cfi_endproc
+ 986              	.LFE153:
+ 988              		.text
+ 989              	.Letext0:
+ 990              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 991              		.file 3 "Drivers/CMSIS/Include/core_cm7.h"
+ 992              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 993              		.file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 994              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 995              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ARM GAS  /tmp/cc97GYnP.s 			page 28
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_pwr_ex.c
+     /tmp/cc97GYnP.s:17     .text.HAL_PWREx_EnableBkUpReg:0000000000000000 $t
+     /tmp/cc97GYnP.s:25     .text.HAL_PWREx_EnableBkUpReg:0000000000000000 HAL_PWREx_EnableBkUpReg
+     /tmp/cc97GYnP.s:88     .text.HAL_PWREx_EnableBkUpReg:0000000000000038 $d
+     /tmp/cc97GYnP.s:93     .text.HAL_PWREx_DisableBkUpReg:0000000000000000 $t
+     /tmp/cc97GYnP.s:100    .text.HAL_PWREx_DisableBkUpReg:0000000000000000 HAL_PWREx_DisableBkUpReg
+     /tmp/cc97GYnP.s:162    .text.HAL_PWREx_DisableBkUpReg:0000000000000038 $d
+     /tmp/cc97GYnP.s:167    .text.HAL_PWREx_EnableFlashPowerDown:0000000000000000 $t
+     /tmp/cc97GYnP.s:174    .text.HAL_PWREx_EnableFlashPowerDown:0000000000000000 HAL_PWREx_EnableFlashPowerDown
+     /tmp/cc97GYnP.s:192    .text.HAL_PWREx_EnableFlashPowerDown:000000000000000c $d
+     /tmp/cc97GYnP.s:197    .text.HAL_PWREx_DisableFlashPowerDown:0000000000000000 $t
+     /tmp/cc97GYnP.s:204    .text.HAL_PWREx_DisableFlashPowerDown:0000000000000000 HAL_PWREx_DisableFlashPowerDown
+     /tmp/cc97GYnP.s:222    .text.HAL_PWREx_DisableFlashPowerDown:000000000000000c $d
+     /tmp/cc97GYnP.s:227    .text.HAL_PWREx_EnableMainRegulatorLowVoltage:0000000000000000 $t
+     /tmp/cc97GYnP.s:234    .text.HAL_PWREx_EnableMainRegulatorLowVoltage:0000000000000000 HAL_PWREx_EnableMainRegulatorLowVoltage
+     /tmp/cc97GYnP.s:252    .text.HAL_PWREx_EnableMainRegulatorLowVoltage:000000000000000c $d
+     /tmp/cc97GYnP.s:257    .text.HAL_PWREx_DisableMainRegulatorLowVoltage:0000000000000000 $t
+     /tmp/cc97GYnP.s:264    .text.HAL_PWREx_DisableMainRegulatorLowVoltage:0000000000000000 HAL_PWREx_DisableMainRegulatorLowVoltage
+     /tmp/cc97GYnP.s:282    .text.HAL_PWREx_DisableMainRegulatorLowVoltage:000000000000000c $d
+     /tmp/cc97GYnP.s:287    .text.HAL_PWREx_EnableLowRegulatorLowVoltage:0000000000000000 $t
+     /tmp/cc97GYnP.s:294    .text.HAL_PWREx_EnableLowRegulatorLowVoltage:0000000000000000 HAL_PWREx_EnableLowRegulatorLowVoltage
+     /tmp/cc97GYnP.s:312    .text.HAL_PWREx_EnableLowRegulatorLowVoltage:000000000000000c $d
+     /tmp/cc97GYnP.s:317    .text.HAL_PWREx_DisableLowRegulatorLowVoltage:0000000000000000 $t
+     /tmp/cc97GYnP.s:324    .text.HAL_PWREx_DisableLowRegulatorLowVoltage:0000000000000000 HAL_PWREx_DisableLowRegulatorLowVoltage
+     /tmp/cc97GYnP.s:342    .text.HAL_PWREx_DisableLowRegulatorLowVoltage:000000000000000c $d
+     /tmp/cc97GYnP.s:347    .text.HAL_PWREx_EnableOverDrive:0000000000000000 $t
+     /tmp/cc97GYnP.s:354    .text.HAL_PWREx_EnableOverDrive:0000000000000000 HAL_PWREx_EnableOverDrive
+     /tmp/cc97GYnP.s:468    .text.HAL_PWREx_EnableOverDrive:0000000000000074 $d
+     /tmp/cc97GYnP.s:474    .text.HAL_PWREx_DisableOverDrive:0000000000000000 $t
+     /tmp/cc97GYnP.s:481    .text.HAL_PWREx_DisableOverDrive:0000000000000000 HAL_PWREx_DisableOverDrive
+     /tmp/cc97GYnP.s:595    .text.HAL_PWREx_DisableOverDrive:0000000000000074 $d
+     /tmp/cc97GYnP.s:601    .text.HAL_PWREx_EnterUnderDriveSTOPMode:0000000000000000 $t
+     /tmp/cc97GYnP.s:608    .text.HAL_PWREx_EnterUnderDriveSTOPMode:0000000000000000 HAL_PWREx_EnterUnderDriveSTOPMode
+     /tmp/cc97GYnP.s:762    .text.HAL_PWREx_EnterUnderDriveSTOPMode:0000000000000084 $d
+     /tmp/cc97GYnP.s:771    .text.HAL_PWREx_GetVoltageRange:0000000000000000 $t
+     /tmp/cc97GYnP.s:778    .text.HAL_PWREx_GetVoltageRange:0000000000000000 HAL_PWREx_GetVoltageRange
+     /tmp/cc97GYnP.s:795    .text.HAL_PWREx_GetVoltageRange:000000000000000c $d
+     /tmp/cc97GYnP.s:800    .text.HAL_PWREx_ControlVoltageScaling:0000000000000000 $t
+     /tmp/cc97GYnP.s:807    .text.HAL_PWREx_ControlVoltageScaling:0000000000000000 HAL_PWREx_ControlVoltageScaling
+     /tmp/cc97GYnP.s:983    .text.HAL_PWREx_ControlVoltageScaling:00000000000000b8 $d
+
+UNDEFINED SYMBOLS
+HAL_GetTick
diff --git a/build/stm32f7xx_hal_pwr_ex.o b/build/stm32f7xx_hal_pwr_ex.o
new file mode 100644
index 0000000..4dec45c
Binary files /dev/null and b/build/stm32f7xx_hal_pwr_ex.o differ
diff --git a/build/stm32f7xx_hal_rcc.d b/build/stm32f7xx_hal_rcc.d
new file mode 100644
index 0000000..26ab7e4
--- /dev/null
+++ b/build/stm32f7xx_hal_rcc.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_rcc.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_rcc.lst b/build/stm32f7xx_hal_rcc.lst
new file mode 100644
index 0000000..0b57b10
--- /dev/null
+++ b/build/stm32f7xx_hal_rcc.lst
@@ -0,0 +1,5256 @@
+ARM GAS  /tmp/ccgleihc.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_rcc.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.HAL_RCC_DeInit,"ax",%progbits
+  17              		.align	1
+  18              		.global	HAL_RCC_DeInit
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	HAL_RCC_DeInit:
+  26              	.LFB141:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @file    stm32f7xx_hal_rcc.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief   RCC HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *          functionalities of the Reset and Clock Control (RCC) peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *           + Peripheral Control functions
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   @verbatim
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   ==============================================================================
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                       ##### RCC specific features #####
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   ==============================================================================
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     [..]
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       After reset the device is running from Internal High Speed oscillator
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       and I-Cache are disabled, and all peripherals are off except internal
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       SRAM, Flash and JTAG.
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           all peripherals mapped on these buses are running at HSI speed.
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) All GPIOs are in input floating state, except the JTAG pins which
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           are assigned to be used for debug purpose.
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     [..]
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       Once the device started from reset, the user application has to:
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) Configure the clock source to be used to drive the System clock
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (if the application needs higher frequency/performance)
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) Configure the System clock frequency and Flash settings
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) Configure the AHB and APB buses prescalers
+ARM GAS  /tmp/ccgleihc.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) Enable the clock for the peripheral(s) to be used
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) Configure the clock source(s) for peripherals which clocks are not
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                       ##### RCC Limitations #####
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   ==============================================================================
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     [..]
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       A delay between an RCC peripheral clock enable and the effective peripheral
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       enabling should be taken into account in order to manage the peripheral read/write
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       from/to registers.
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) This delay depends on the peripheral mapping.
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           after the clock enable bit is set on the hardware register
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           after the clock enable bit is set on the hardware register
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     [..]
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       Implemented Workaround:
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   @endverbatim
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   ******************************************************************************
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @attention
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * Copyright (c) 2017 STMicroelectronics.
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * All rights reserved.
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * the root directory of this software component.
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   ******************************************************************************
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Includes ------------------------------------------------------------------*/
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #include "stm32f7xx_hal.h"
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @{
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC RCC
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief RCC HAL module driver
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @{
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #ifdef HAL_RCC_MODULE_ENABLED
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private typedef -----------------------------------------------------------*/
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private define ------------------------------------------------------------*/
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private macro -------------------------------------------------------------*/
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Private_Macros RCC Private Macros
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @{
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO1_GPIO_PORT        GPIOA
+ARM GAS  /tmp/ccgleihc.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO1_PIN              GPIO_PIN_8
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO2_GPIO_PORT         GPIOC
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO2_PIN               GPIO_PIN_9
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @}
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private variables ---------------------------------------------------------*/
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Private_Variables RCC Private Variables
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @{
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @}
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Exported functions ---------------------------------------------------------*/
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions RCC Exported Functions
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @{
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *  @brief    Initialization and Configuration functions
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   @verbatim
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   ===============================================================================
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ##### Initialization and de-initialization functions #####
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   ===============================================================================
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     [..]
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       This section provides functions allowing to configure the internal/external oscillators
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       and APB2).
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     [..] Internal/external clock and PLL configuration
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           the PLL as System clock source.
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           clock source.
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           through the PLL as System clock source. Can be used also as RTC clock source.
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         (++) The first output is used to generate the high speed system clock (up to 216 MHz)
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****              the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           and if a HSE clock failure occurs(HSE used directly or through PLL as System
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           clock source), the System clock is automatically switched to HSI and an interrupt
+ARM GAS  /tmp/ccgleihc.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (Non-Maskable Interrupt) exception vector.
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           clock (through a configurable prescaler) on PA8 pin.
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           clock (through a configurable prescaler) on PC9 pin.
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     [..] System, AHB and APB buses clocks configuration
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           HSE and PLL.
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           The AHB clock (HCLK) is derived from System clock through configurable
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           prescaler and used to clock the CPU, memory and peripherals mapped
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           from AHB clock through configurable prescalers and used to clock
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           the peripherals mapped on these buses. You can use
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****               from an external clock mapped on the I2S_CKIN pin.
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****               You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (+@)  SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) o
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****               from an external clock mapped on the I2S_CKIN pin.
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****               divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****               macros to configure this clock.
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****               to work correctly, while the SDIO require a frequency equal or lower than
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****               to 48. This clock is derived of the main PLL through PLLQ divider.
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (+@) IWDG clock which is always the LSI clock.
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @endverbatim
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @{
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Resets the RCC clock configuration to the default reset state.
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   The default reset state of the clock configuration is given below:
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            - HSI ON and used as system clock source
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            - HSE, PLL, PLLI2S and PLLSAI OFF
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            - AHB, APB1 and APB2 prescaler set to 1.
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            - CSS, MCO1 and MCO2 OFF
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            - All interrupts disabled
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   This function doesn't modify the configuration of the
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            - Peripheral clocks
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            - LSI, LSE and RTC clocks
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval None
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_DeInit(void)
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+  28              		.loc 1 197 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32 0000 38B5     		push	{r3, r4, r5, lr}
+ARM GAS  /tmp/ccgleihc.s 			page 5
+
+
+  33              	.LCFI0:
+  34              		.cfi_def_cfa_offset 16
+  35              		.cfi_offset 3, -16
+  36              		.cfi_offset 4, -12
+  37              		.cfi_offset 5, -8
+  38              		.cfi_offset 14, -4
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   uint32_t tickstart;
+  39              		.loc 1 198 3 view .LVU1
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get Start Tick */
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   tickstart = HAL_GetTick();
+  40              		.loc 1 201 3 view .LVU2
+  41              		.loc 1 201 15 is_stmt 0 view .LVU3
+  42 0002 FFF7FEFF 		bl	HAL_GetTick
+  43              	.LVL0:
+  44 0006 0446     		mov	r4, r0
+  45              	.LVL1:
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Set HSION bit to the reset value */
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   SET_BIT(RCC->CR, RCC_CR_HSION);
+  46              		.loc 1 204 3 is_stmt 1 view .LVU4
+  47 0008 4E4A     		ldr	r2, .L28
+  48 000a 1368     		ldr	r3, [r2]
+  49 000c 43F00103 		orr	r3, r3, #1
+  50 0010 1360     		str	r3, [r2]
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Wait till HSI is ready */
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+  51              		.loc 1 207 3 view .LVU5
+  52              	.LVL2:
+  53              	.L2:
+  54              		.loc 1 207 9 view .LVU6
+  55              		.loc 1 207 10 is_stmt 0 view .LVU7
+  56 0012 4C4B     		ldr	r3, .L28
+  57 0014 1B68     		ldr	r3, [r3]
+  58              		.loc 1 207 9 view .LVU8
+  59 0016 13F0020F 		tst	r3, #2
+  60 001a 06D1     		bne	.L22
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+  61              		.loc 1 209 5 is_stmt 1 view .LVU9
+  62              		.loc 1 209 10 is_stmt 0 view .LVU10
+  63 001c FFF7FEFF 		bl	HAL_GetTick
+  64              	.LVL3:
+  65              		.loc 1 209 24 view .LVU11
+  66 0020 001B     		subs	r0, r0, r4
+  67              		.loc 1 209 8 view .LVU12
+  68 0022 0228     		cmp	r0, #2
+  69 0024 F5D9     		bls	.L2
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       return HAL_TIMEOUT;
+  70              		.loc 1 211 14 view .LVU13
+  71 0026 0320     		movs	r0, #3
+  72              	.L3:
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ARM GAS  /tmp/ccgleihc.s 			page 6
+
+
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Set HSITRIM[4:0] bits to the reset value */
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get Start Tick */
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   tickstart = HAL_GetTick();
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Reset CFGR register */
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   CLEAR_REG(RCC->CFGR);
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Wait till clock switch is ready */
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       return HAL_TIMEOUT;
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get Start Tick */
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   tickstart = HAL_GetTick();
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Clear HSEON, HSEBYP and CSSON bits */
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Wait till HSE is disabled */
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       return HAL_TIMEOUT;
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get Start Tick */
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   tickstart = HAL_GetTick();
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Clear PLLON bit */
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Wait till PLL is disabled */
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       return HAL_TIMEOUT;
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get Start Tick */
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   tickstart = HAL_GetTick();
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Reset PLLI2SON bit */
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Wait till PLLI2S is disabled */
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ARM GAS  /tmp/ccgleihc.s 			page 7
+
+
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       return HAL_TIMEOUT;
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get Start Tick */
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   tickstart = HAL_GetTick();
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Reset PLLSAI bit */
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Wait till PLLSAI is disabled */
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       return HAL_TIMEOUT;
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Reset PLLI2SCFGR register to default value */
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Reset PLLSAICFGR register to default value */
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Disable all interrupts */
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | R
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Clear all interrupt flags */
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Clear LSION bit */
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Reset all CSR flags */
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Update the SystemCoreClock global variable */
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   SystemCoreClock = HSI_VALUE;
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Adapt Systick interrupt period */
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (HAL_InitTick(uwTickPrio) != HAL_OK)
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     return HAL_ERROR;
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   else
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     return HAL_OK;
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+  73              		.loc 1 326 1 view .LVU14
+  74 0028 38BD     		pop	{r3, r4, r5, pc}
+ARM GAS  /tmp/ccgleihc.s 			page 8
+
+
+  75              	.LVL4:
+  76              	.L22:
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  77              		.loc 1 216 3 is_stmt 1 view .LVU15
+  78 002a 464D     		ldr	r5, .L28
+  79 002c 2B68     		ldr	r3, [r5]
+  80 002e 43F08003 		orr	r3, r3, #128
+  81 0032 2B60     		str	r3, [r5]
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  82              		.loc 1 219 3 view .LVU16
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  83              		.loc 1 219 15 is_stmt 0 view .LVU17
+  84 0034 FFF7FEFF 		bl	HAL_GetTick
+  85              	.LVL5:
+  86 0038 0446     		mov	r4, r0
+  87              	.LVL6:
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+  88              		.loc 1 222 3 is_stmt 1 view .LVU18
+  89 003a 0023     		movs	r3, #0
+  90 003c AB60     		str	r3, [r5, #8]
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+  91              		.loc 1 225 3 view .LVU19
+  92              	.LVL7:
+  93              	.L5:
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+  94              		.loc 1 225 9 view .LVU20
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+  95              		.loc 1 225 10 is_stmt 0 view .LVU21
+  96 003e 414B     		ldr	r3, .L28
+  97 0040 9B68     		ldr	r3, [r3, #8]
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+  98              		.loc 1 225 9 view .LVU22
+  99 0042 13F00C0F 		tst	r3, #12
+ 100 0046 08D0     		beq	.L23
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 101              		.loc 1 227 5 is_stmt 1 view .LVU23
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 102              		.loc 1 227 10 is_stmt 0 view .LVU24
+ 103 0048 FFF7FEFF 		bl	HAL_GetTick
+ 104              	.LVL8:
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 105              		.loc 1 227 24 view .LVU25
+ 106 004c 001B     		subs	r0, r0, r4
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 107              		.loc 1 227 8 view .LVU26
+ 108 004e 41F28833 		movw	r3, #5000
+ 109 0052 9842     		cmp	r0, r3
+ 110 0054 F3D9     		bls	.L5
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 111              		.loc 1 229 14 view .LVU27
+ 112 0056 0320     		movs	r0, #3
+ 113 0058 E6E7     		b	.L3
+ 114              	.L23:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 115              		.loc 1 234 3 is_stmt 1 view .LVU28
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 116              		.loc 1 234 15 is_stmt 0 view .LVU29
+ARM GAS  /tmp/ccgleihc.s 			page 9
+
+
+ 117 005a FFF7FEFF 		bl	HAL_GetTick
+ 118              	.LVL9:
+ 119 005e 0446     		mov	r4, r0
+ 120              	.LVL10:
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 121              		.loc 1 237 3 is_stmt 1 view .LVU30
+ 122 0060 384A     		ldr	r2, .L28
+ 123 0062 1368     		ldr	r3, [r2]
+ 124 0064 23F45023 		bic	r3, r3, #851968
+ 125 0068 1360     		str	r3, [r2]
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 126              		.loc 1 240 3 view .LVU31
+ 127              	.LVL11:
+ 128              	.L7:
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 129              		.loc 1 240 9 view .LVU32
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 130              		.loc 1 240 10 is_stmt 0 view .LVU33
+ 131 006a 364B     		ldr	r3, .L28
+ 132 006c 1B68     		ldr	r3, [r3]
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 133              		.loc 1 240 9 view .LVU34
+ 134 006e 13F4003F 		tst	r3, #131072
+ 135 0072 06D0     		beq	.L24
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 136              		.loc 1 242 5 is_stmt 1 view .LVU35
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 137              		.loc 1 242 10 is_stmt 0 view .LVU36
+ 138 0074 FFF7FEFF 		bl	HAL_GetTick
+ 139              	.LVL12:
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 140              		.loc 1 242 24 view .LVU37
+ 141 0078 001B     		subs	r0, r0, r4
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 142              		.loc 1 242 8 view .LVU38
+ 143 007a 6428     		cmp	r0, #100
+ 144 007c F5D9     		bls	.L7
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 145              		.loc 1 244 14 view .LVU39
+ 146 007e 0320     		movs	r0, #3
+ 147 0080 D2E7     		b	.L3
+ 148              	.L24:
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 149              		.loc 1 249 3 is_stmt 1 view .LVU40
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 150              		.loc 1 249 15 is_stmt 0 view .LVU41
+ 151 0082 FFF7FEFF 		bl	HAL_GetTick
+ 152              	.LVL13:
+ 153 0086 0446     		mov	r4, r0
+ 154              	.LVL14:
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 155              		.loc 1 252 3 is_stmt 1 view .LVU42
+ 156 0088 2E4A     		ldr	r2, .L28
+ 157 008a 1368     		ldr	r3, [r2]
+ 158 008c 23F08073 		bic	r3, r3, #16777216
+ 159 0090 1360     		str	r3, [r2]
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ARM GAS  /tmp/ccgleihc.s 			page 10
+
+
+ 160              		.loc 1 255 3 view .LVU43
+ 161              	.LVL15:
+ 162              	.L9:
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 163              		.loc 1 255 9 view .LVU44
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 164              		.loc 1 255 10 is_stmt 0 view .LVU45
+ 165 0092 2C4B     		ldr	r3, .L28
+ 166 0094 1B68     		ldr	r3, [r3]
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 167              		.loc 1 255 9 view .LVU46
+ 168 0096 13F0007F 		tst	r3, #33554432
+ 169 009a 06D0     		beq	.L25
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 170              		.loc 1 257 5 is_stmt 1 view .LVU47
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 171              		.loc 1 257 10 is_stmt 0 view .LVU48
+ 172 009c FFF7FEFF 		bl	HAL_GetTick
+ 173              	.LVL16:
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 174              		.loc 1 257 24 view .LVU49
+ 175 00a0 001B     		subs	r0, r0, r4
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 176              		.loc 1 257 8 view .LVU50
+ 177 00a2 0228     		cmp	r0, #2
+ 178 00a4 F5D9     		bls	.L9
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 179              		.loc 1 259 14 view .LVU51
+ 180 00a6 0320     		movs	r0, #3
+ 181 00a8 BEE7     		b	.L3
+ 182              	.L25:
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 183              		.loc 1 264 3 is_stmt 1 view .LVU52
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 184              		.loc 1 264 15 is_stmt 0 view .LVU53
+ 185 00aa FFF7FEFF 		bl	HAL_GetTick
+ 186              	.LVL17:
+ 187 00ae 0446     		mov	r4, r0
+ 188              	.LVL18:
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 189              		.loc 1 267 3 is_stmt 1 view .LVU54
+ 190 00b0 244A     		ldr	r2, .L28
+ 191 00b2 1368     		ldr	r3, [r2]
+ 192 00b4 23F08063 		bic	r3, r3, #67108864
+ 193 00b8 1360     		str	r3, [r2]
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 194              		.loc 1 270 3 view .LVU55
+ 195              	.LVL19:
+ 196              	.L11:
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 197              		.loc 1 270 9 view .LVU56
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 198              		.loc 1 270 10 is_stmt 0 view .LVU57
+ 199 00ba 224B     		ldr	r3, .L28
+ 200 00bc 1B68     		ldr	r3, [r3]
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 201              		.loc 1 270 9 view .LVU58
+ARM GAS  /tmp/ccgleihc.s 			page 11
+
+
+ 202 00be 13F0006F 		tst	r3, #134217728
+ 203 00c2 06D0     		beq	.L26
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 204              		.loc 1 272 5 is_stmt 1 view .LVU59
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 205              		.loc 1 272 10 is_stmt 0 view .LVU60
+ 206 00c4 FFF7FEFF 		bl	HAL_GetTick
+ 207              	.LVL20:
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 208              		.loc 1 272 24 view .LVU61
+ 209 00c8 001B     		subs	r0, r0, r4
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 210              		.loc 1 272 8 view .LVU62
+ 211 00ca 6428     		cmp	r0, #100
+ 212 00cc F5D9     		bls	.L11
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 213              		.loc 1 274 14 view .LVU63
+ 214 00ce 0320     		movs	r0, #3
+ 215 00d0 AAE7     		b	.L3
+ 216              	.L26:
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 217              		.loc 1 279 3 is_stmt 1 view .LVU64
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 218              		.loc 1 279 15 is_stmt 0 view .LVU65
+ 219 00d2 FFF7FEFF 		bl	HAL_GetTick
+ 220              	.LVL21:
+ 221 00d6 0446     		mov	r4, r0
+ 222              	.LVL22:
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 223              		.loc 1 282 3 is_stmt 1 view .LVU66
+ 224 00d8 1A4A     		ldr	r2, .L28
+ 225 00da 1368     		ldr	r3, [r2]
+ 226 00dc 23F08053 		bic	r3, r3, #268435456
+ 227 00e0 1360     		str	r3, [r2]
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 228              		.loc 1 285 3 view .LVU67
+ 229              	.LVL23:
+ 230              	.L13:
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 231              		.loc 1 285 9 view .LVU68
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 232              		.loc 1 285 10 is_stmt 0 view .LVU69
+ 233 00e2 184B     		ldr	r3, .L28
+ 234 00e4 1B68     		ldr	r3, [r3]
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 235              		.loc 1 285 9 view .LVU70
+ 236 00e6 13F0005F 		tst	r3, #536870912
+ 237 00ea 06D0     		beq	.L27
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 238              		.loc 1 287 5 is_stmt 1 view .LVU71
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 239              		.loc 1 287 10 is_stmt 0 view .LVU72
+ 240 00ec FFF7FEFF 		bl	HAL_GetTick
+ 241              	.LVL24:
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 242              		.loc 1 287 24 view .LVU73
+ 243 00f0 001B     		subs	r0, r0, r4
+ARM GAS  /tmp/ccgleihc.s 			page 12
+
+
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 244              		.loc 1 287 8 view .LVU74
+ 245 00f2 6428     		cmp	r0, #100
+ 246 00f4 F5D9     		bls	.L13
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 247              		.loc 1 289 14 view .LVU75
+ 248 00f6 0320     		movs	r0, #3
+ 249 00f8 96E7     		b	.L3
+ 250              	.L27:
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 251              		.loc 1 294 3 is_stmt 1 view .LVU76
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 252              		.loc 1 294 16 is_stmt 0 view .LVU77
+ 253 00fa 124B     		ldr	r3, .L28
+ 254 00fc 124A     		ldr	r2, .L28+4
+ 255 00fe 5A60     		str	r2, [r3, #4]
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 256              		.loc 1 297 3 is_stmt 1 view .LVU78
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 257              		.loc 1 297 19 is_stmt 0 view .LVU79
+ 258 0100 103A     		subs	r2, r2, #16
+ 259 0102 C3F88420 		str	r2, [r3, #132]
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 260              		.loc 1 300 3 is_stmt 1 view .LVU80
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 261              		.loc 1 300 19 is_stmt 0 view .LVU81
+ 262 0106 C3F88820 		str	r2, [r3, #136]
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 263              		.loc 1 303 3 is_stmt 1 view .LVU82
+ 264 010a DA68     		ldr	r2, [r3, #12]
+ 265 010c 22F4FE42 		bic	r2, r2, #32512
+ 266 0110 DA60     		str	r2, [r3, #12]
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 267              		.loc 1 306 3 view .LVU83
+ 268 0112 DA68     		ldr	r2, [r3, #12]
+ 269 0114 42F47F02 		orr	r2, r2, #16711680
+ 270 0118 DA60     		str	r2, [r3, #12]
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 271              		.loc 1 309 3 view .LVU84
+ 272 011a 5A6F     		ldr	r2, [r3, #116]
+ 273 011c 22F00102 		bic	r2, r2, #1
+ 274 0120 5A67     		str	r2, [r3, #116]
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 275              		.loc 1 312 3 view .LVU85
+ 276 0122 5A6F     		ldr	r2, [r3, #116]
+ 277 0124 42F08072 		orr	r2, r2, #16777216
+ 278 0128 5A67     		str	r2, [r3, #116]
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 279              		.loc 1 315 3 view .LVU86
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 280              		.loc 1 315 19 is_stmt 0 view .LVU87
+ 281 012a 084B     		ldr	r3, .L28+8
+ 282 012c 084A     		ldr	r2, .L28+12
+ 283 012e 1A60     		str	r2, [r3]
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 284              		.loc 1 318 3 is_stmt 1 view .LVU88
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ARM GAS  /tmp/ccgleihc.s 			page 13
+
+
+ 285              		.loc 1 318 7 is_stmt 0 view .LVU89
+ 286 0130 084B     		ldr	r3, .L28+16
+ 287 0132 1868     		ldr	r0, [r3]
+ 288 0134 FFF7FEFF 		bl	HAL_InitTick
+ 289              	.LVL25:
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 290              		.loc 1 318 6 view .LVU90
+ 291 0138 0028     		cmp	r0, #0
+ 292 013a 3FF475AF 		beq	.L3
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 293              		.loc 1 320 12 view .LVU91
+ 294 013e 0120     		movs	r0, #1
+ 295 0140 72E7     		b	.L3
+ 296              	.L29:
+ 297 0142 00BF     		.align	2
+ 298              	.L28:
+ 299 0144 00380240 		.word	1073887232
+ 300 0148 10300024 		.word	603992080
+ 301 014c 00000000 		.word	SystemCoreClock
+ 302 0150 0024F400 		.word	16000000
+ 303 0154 00000000 		.word	uwTickPrio
+ 304              		.cfi_endproc
+ 305              	.LFE141:
+ 307              		.section	.text.HAL_RCC_OscConfig,"ax",%progbits
+ 308              		.align	1
+ 309              		.global	HAL_RCC_OscConfig
+ 310              		.syntax unified
+ 311              		.thumb
+ 312              		.thumb_func
+ 313              		.fpu fpv5-d16
+ 315              	HAL_RCC_OscConfig:
+ 316              	.LVL26:
+ 317              	.LFB142:
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         RCC_OscInitTypeDef.
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         contains the configuration information for the RCC Oscillators.
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   The PLL is not disabled when used as system clock.
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         supported by this function. User should request a transition to LSE Off
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         first and then LSE On or LSE Bypass.
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         supported by this function. User should request a transition to HSE Off
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         first and then HSE On or HSE Bypass.
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval HAL status
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 318              		.loc 1 343 1 is_stmt 1 view -0
+ 319              		.cfi_startproc
+ 320              		@ args = 0, pretend = 0, frame = 8
+ 321              		@ frame_needed = 0, uses_anonymous_args = 0
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   uint32_t tickstart;
+ 322              		.loc 1 344 3 view .LVU93
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   uint32_t pll_config;
+ARM GAS  /tmp/ccgleihc.s 			page 14
+
+
+ 323              		.loc 1 345 3 view .LVU94
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   FlagStatus pwrclkchanged = RESET;
+ 324              		.loc 1 346 3 view .LVU95
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Check Null pointer */
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (RCC_OscInitStruct == NULL)
+ 325              		.loc 1 349 3 view .LVU96
+ 326              		.loc 1 349 6 is_stmt 0 view .LVU97
+ 327 0000 0028     		cmp	r0, #0
+ 328 0002 00F00682 		beq	.L82
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   uint32_t tickstart;
+ 329              		.loc 1 343 1 view .LVU98
+ 330 0006 70B5     		push	{r4, r5, r6, lr}
+ 331              	.LCFI1:
+ 332              		.cfi_def_cfa_offset 16
+ 333              		.cfi_offset 4, -16
+ 334              		.cfi_offset 5, -12
+ 335              		.cfi_offset 6, -8
+ 336              		.cfi_offset 14, -4
+ 337 0008 82B0     		sub	sp, sp, #8
+ 338              	.LCFI2:
+ 339              		.cfi_def_cfa_offset 24
+ 340 000a 0446     		mov	r4, r0
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     return HAL_ERROR;
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Check the parameters */
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+ 341              		.loc 1 355 3 is_stmt 1 view .LVU99
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /*------------------------------- HSE Configuration ------------------------*/
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 342              		.loc 1 358 3 view .LVU100
+ 343              		.loc 1 358 26 is_stmt 0 view .LVU101
+ 344 000c 0368     		ldr	r3, [r0]
+ 345              		.loc 1 358 6 view .LVU102
+ 346 000e 13F0010F 		tst	r3, #1
+ 347 0012 29D0     		beq	.L32
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check the parameters */
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ 348              		.loc 1 361 5 is_stmt 1 view .LVU103
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ 349              		.loc 1 363 5 view .LVU104
+ 350              		.loc 1 363 10 is_stmt 0 view .LVU105
+ 351 0014 954B     		ldr	r3, .L124
+ 352 0016 9B68     		ldr	r3, [r3, #8]
+ 353 0018 03F00C03 		and	r3, r3, #12
+ 354              		.loc 1 363 8 view .LVU106
+ 355 001c 042B     		cmp	r3, #4
+ 356 001e 1AD0     		beq	.L33
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R
+ 357              		.loc 1 364 14 view .LVU107
+ 358 0020 924B     		ldr	r3, .L124
+ 359 0022 9B68     		ldr	r3, [r3, #8]
+ARM GAS  /tmp/ccgleihc.s 			page 15
+
+
+ 360 0024 03F00C03 		and	r3, r3, #12
+ 361              		.loc 1 364 9 view .LVU108
+ 362 0028 082B     		cmp	r3, #8
+ 363 002a 0FD0     		beq	.L110
+ 364              	.L34:
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         return HAL_ERROR;
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     else
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Set the new HSE configuration ---------------------------------------*/
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 365              		.loc 1 374 7 is_stmt 1 view .LVU109
+ 366              		.loc 1 374 7 view .LVU110
+ 367 002c 6368     		ldr	r3, [r4, #4]
+ 368 002e B3F5803F 		cmp	r3, #65536
+ 369 0032 40D0     		beq	.L111
+ 370              		.loc 1 374 7 discriminator 2 view .LVU111
+ 371 0034 002B     		cmp	r3, #0
+ 372 0036 54D1     		bne	.L37
+ 373              		.loc 1 374 7 discriminator 4 view .LVU112
+ 374 0038 8C4B     		ldr	r3, .L124
+ 375 003a 1A68     		ldr	r2, [r3]
+ 376 003c 22F48032 		bic	r2, r2, #65536
+ 377 0040 1A60     		str	r2, [r3]
+ 378              		.loc 1 374 7 discriminator 4 view .LVU113
+ 379 0042 1A68     		ldr	r2, [r3]
+ 380 0044 22F48022 		bic	r2, r2, #262144
+ 381 0048 1A60     		str	r2, [r3]
+ 382 004a 39E0     		b	.L36
+ 383              	.L110:
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R
+ 384              		.loc 1 364 87 is_stmt 0 discriminator 1 view .LVU114
+ 385 004c 874B     		ldr	r3, .L124
+ 386 004e 5B68     		ldr	r3, [r3, #4]
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R
+ 387              		.loc 1 364 79 discriminator 1 view .LVU115
+ 388 0050 13F4800F 		tst	r3, #4194304
+ 389 0054 EAD0     		beq	.L34
+ 390              	.L33:
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 391              		.loc 1 366 7 is_stmt 1 view .LVU116
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 392              		.loc 1 366 12 is_stmt 0 view .LVU117
+ 393 0056 854B     		ldr	r3, .L124
+ 394 0058 1B68     		ldr	r3, [r3]
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 395              		.loc 1 366 10 view .LVU118
+ 396 005a 13F4003F 		tst	r3, #131072
+ 397 005e 03D0     		beq	.L32
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 398              		.loc 1 366 79 discriminator 1 view .LVU119
+ 399 0060 6368     		ldr	r3, [r4, #4]
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ARM GAS  /tmp/ccgleihc.s 			page 16
+
+
+ 400              		.loc 1 366 58 discriminator 1 view .LVU120
+ 401 0062 002B     		cmp	r3, #0
+ 402 0064 00F0D781 		beq	.L112
+ 403              	.LVL27:
+ 404              	.L32:
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Check the HSE State */
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Get Start Tick*/
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Wait till HSE is ready */
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       else
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Get Start Tick*/
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Wait till HSE is bypassed or disabled */
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /*----------------------------- HSI Configuration --------------------------*/
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 405              		.loc 1 408 3 is_stmt 1 view .LVU121
+ 406              		.loc 1 408 26 is_stmt 0 view .LVU122
+ 407 0068 2368     		ldr	r3, [r4]
+ 408              		.loc 1 408 6 view .LVU123
+ 409 006a 13F0020F 		tst	r3, #2
+ 410 006e 74D0     		beq	.L44
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check the parameters */
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ 411              		.loc 1 411 5 is_stmt 1 view .LVU124
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+ 412              		.loc 1 412 5 view .LVU125
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock *
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ 413              		.loc 1 415 5 view .LVU126
+ 414              		.loc 1 415 10 is_stmt 0 view .LVU127
+ 415 0070 7E4B     		ldr	r3, .L124
+ARM GAS  /tmp/ccgleihc.s 			page 17
+
+
+ 416 0072 9B68     		ldr	r3, [r3, #8]
+ 417              		.loc 1 415 8 view .LVU128
+ 418 0074 13F00C0F 		tst	r3, #12
+ 419 0078 5ED0     		beq	.L45
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R
+ 420              		.loc 1 416 14 view .LVU129
+ 421 007a 7C4B     		ldr	r3, .L124
+ 422 007c 9B68     		ldr	r3, [r3, #8]
+ 423 007e 03F00C03 		and	r3, r3, #12
+ 424              		.loc 1 416 9 view .LVU130
+ 425 0082 082B     		cmp	r3, #8
+ 426 0084 53D0     		beq	.L113
+ 427              	.L46:
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* When HSI is used as system clock it will not disabled */
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         return HAL_ERROR;
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Otherwise, just the calibration is allowed */
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       else
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     else
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Check the HSI State */
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
+ 428              		.loc 1 433 7 is_stmt 1 view .LVU131
+ 429              		.loc 1 433 29 is_stmt 0 view .LVU132
+ 430 0086 E368     		ldr	r3, [r4, #12]
+ 431              		.loc 1 433 10 view .LVU133
+ 432 0088 002B     		cmp	r3, #0
+ 433 008a 00F08980 		beq	.L48
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Enable the Internal High Speed oscillator (HSI). */
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         __HAL_RCC_HSI_ENABLE();
+ 434              		.loc 1 436 9 is_stmt 1 view .LVU134
+ 435 008e 774A     		ldr	r2, .L124
+ 436 0090 1368     		ldr	r3, [r2]
+ 437 0092 43F00103 		orr	r3, r3, #1
+ 438 0096 1360     		str	r3, [r2]
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Get Start Tick*/
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 439              		.loc 1 439 9 view .LVU135
+ 440              		.loc 1 439 21 is_stmt 0 view .LVU136
+ 441 0098 FFF7FEFF 		bl	HAL_GetTick
+ 442              	.LVL28:
+ 443 009c 0546     		mov	r5, r0
+ 444              	.LVL29:
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Wait till HSI is ready */
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 445              		.loc 1 442 9 is_stmt 1 view .LVU137
+ARM GAS  /tmp/ccgleihc.s 			page 18
+
+
+ 446              	.L49:
+ 447              		.loc 1 442 15 view .LVU138
+ 448              		.loc 1 442 16 is_stmt 0 view .LVU139
+ 449 009e 734B     		ldr	r3, .L124
+ 450 00a0 1B68     		ldr	r3, [r3]
+ 451              		.loc 1 442 15 view .LVU140
+ 452 00a2 13F0020F 		tst	r3, #2
+ 453 00a6 72D1     		bne	.L114
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 454              		.loc 1 444 11 is_stmt 1 view .LVU141
+ 455              		.loc 1 444 16 is_stmt 0 view .LVU142
+ 456 00a8 FFF7FEFF 		bl	HAL_GetTick
+ 457              	.LVL30:
+ 458              		.loc 1 444 30 view .LVU143
+ 459 00ac 401B     		subs	r0, r0, r5
+ 460              		.loc 1 444 14 view .LVU144
+ 461 00ae 0228     		cmp	r0, #2
+ 462 00b0 F5D9     		bls	.L49
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 463              		.loc 1 446 20 view .LVU145
+ 464 00b2 0320     		movs	r0, #3
+ 465 00b4 B4E1     		b	.L31
+ 466              	.LVL31:
+ 467              	.L111:
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 468              		.loc 1 374 7 is_stmt 1 discriminator 1 view .LVU146
+ 469 00b6 6D4A     		ldr	r2, .L124
+ 470 00b8 1368     		ldr	r3, [r2]
+ 471 00ba 43F48033 		orr	r3, r3, #65536
+ 472 00be 1360     		str	r3, [r2]
+ 473              	.L36:
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 474              		.loc 1 374 7 discriminator 10 view .LVU147
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 475              		.loc 1 377 7 discriminator 10 view .LVU148
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 476              		.loc 1 377 28 is_stmt 0 discriminator 10 view .LVU149
+ 477 00c0 6368     		ldr	r3, [r4, #4]
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 478              		.loc 1 377 10 discriminator 10 view .LVU150
+ 479 00c2 2BB3     		cbz	r3, .L39
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 480              		.loc 1 380 9 is_stmt 1 view .LVU151
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 481              		.loc 1 380 21 is_stmt 0 view .LVU152
+ 482 00c4 FFF7FEFF 		bl	HAL_GetTick
+ 483              	.LVL32:
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 484              		.loc 1 380 21 view .LVU153
+ 485 00c8 0546     		mov	r5, r0
+ 486              	.LVL33:
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 487              		.loc 1 383 9 is_stmt 1 view .LVU154
+ 488              	.L40:
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ARM GAS  /tmp/ccgleihc.s 			page 19
+
+
+ 489              		.loc 1 383 15 view .LVU155
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 490              		.loc 1 383 16 is_stmt 0 view .LVU156
+ 491 00ca 684B     		ldr	r3, .L124
+ 492 00cc 1B68     		ldr	r3, [r3]
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 493              		.loc 1 383 15 view .LVU157
+ 494 00ce 13F4003F 		tst	r3, #131072
+ 495 00d2 C9D1     		bne	.L32
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 496              		.loc 1 385 11 is_stmt 1 view .LVU158
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 497              		.loc 1 385 16 is_stmt 0 view .LVU159
+ 498 00d4 FFF7FEFF 		bl	HAL_GetTick
+ 499              	.LVL34:
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 500              		.loc 1 385 30 view .LVU160
+ 501 00d8 401B     		subs	r0, r0, r5
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 502              		.loc 1 385 14 view .LVU161
+ 503 00da 6428     		cmp	r0, #100
+ 504 00dc F5D9     		bls	.L40
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 505              		.loc 1 387 20 view .LVU162
+ 506 00de 0320     		movs	r0, #3
+ 507 00e0 9EE1     		b	.L31
+ 508              	.LVL35:
+ 509              	.L37:
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 510              		.loc 1 374 7 is_stmt 1 discriminator 5 view .LVU163
+ 511 00e2 B3F5A02F 		cmp	r3, #327680
+ 512 00e6 09D0     		beq	.L115
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 513              		.loc 1 374 7 discriminator 8 view .LVU164
+ 514 00e8 604B     		ldr	r3, .L124
+ 515 00ea 1A68     		ldr	r2, [r3]
+ 516 00ec 22F48032 		bic	r2, r2, #65536
+ 517 00f0 1A60     		str	r2, [r3]
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 518              		.loc 1 374 7 discriminator 8 view .LVU165
+ 519 00f2 1A68     		ldr	r2, [r3]
+ 520 00f4 22F48022 		bic	r2, r2, #262144
+ 521 00f8 1A60     		str	r2, [r3]
+ 522 00fa E1E7     		b	.L36
+ 523              	.L115:
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 524              		.loc 1 374 7 discriminator 7 view .LVU166
+ 525 00fc 5B4B     		ldr	r3, .L124
+ 526 00fe 1A68     		ldr	r2, [r3]
+ 527 0100 42F48022 		orr	r2, r2, #262144
+ 528 0104 1A60     		str	r2, [r3]
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 529              		.loc 1 374 7 discriminator 7 view .LVU167
+ 530 0106 1A68     		ldr	r2, [r3]
+ 531 0108 42F48032 		orr	r2, r2, #65536
+ 532 010c 1A60     		str	r2, [r3]
+ 533 010e D7E7     		b	.L36
+ARM GAS  /tmp/ccgleihc.s 			page 20
+
+
+ 534              	.L39:
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 535              		.loc 1 394 9 view .LVU168
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 536              		.loc 1 394 21 is_stmt 0 view .LVU169
+ 537 0110 FFF7FEFF 		bl	HAL_GetTick
+ 538              	.LVL36:
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 539              		.loc 1 394 21 view .LVU170
+ 540 0114 0546     		mov	r5, r0
+ 541              	.LVL37:
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 542              		.loc 1 397 9 is_stmt 1 view .LVU171
+ 543              	.L42:
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 544              		.loc 1 397 15 view .LVU172
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 545              		.loc 1 397 16 is_stmt 0 view .LVU173
+ 546 0116 554B     		ldr	r3, .L124
+ 547 0118 1B68     		ldr	r3, [r3]
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 548              		.loc 1 397 15 view .LVU174
+ 549 011a 13F4003F 		tst	r3, #131072
+ 550 011e A3D0     		beq	.L32
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 551              		.loc 1 399 11 is_stmt 1 view .LVU175
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 552              		.loc 1 399 16 is_stmt 0 view .LVU176
+ 553 0120 FFF7FEFF 		bl	HAL_GetTick
+ 554              	.LVL38:
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 555              		.loc 1 399 30 view .LVU177
+ 556 0124 401B     		subs	r0, r0, r5
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 557              		.loc 1 399 14 view .LVU178
+ 558 0126 6428     		cmp	r0, #100
+ 559 0128 F5D9     		bls	.L42
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 560              		.loc 1 401 20 view .LVU179
+ 561 012a 0320     		movs	r0, #3
+ 562 012c 78E1     		b	.L31
+ 563              	.LVL39:
+ 564              	.L113:
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 565              		.loc 1 416 87 discriminator 1 view .LVU180
+ 566 012e 4F4B     		ldr	r3, .L124
+ 567 0130 5B68     		ldr	r3, [r3, #4]
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 568              		.loc 1 416 79 discriminator 1 view .LVU181
+ 569 0132 13F4800F 		tst	r3, #4194304
+ 570 0136 A6D1     		bne	.L46
+ 571              	.L45:
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 572              		.loc 1 419 7 is_stmt 1 view .LVU182
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 573              		.loc 1 419 12 is_stmt 0 view .LVU183
+ 574 0138 4C4B     		ldr	r3, .L124
+ARM GAS  /tmp/ccgleihc.s 			page 21
+
+
+ 575 013a 1B68     		ldr	r3, [r3]
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 576              		.loc 1 419 10 view .LVU184
+ 577 013c 13F0020F 		tst	r3, #2
+ 578 0140 03D0     		beq	.L47
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 579              		.loc 1 419 79 discriminator 1 view .LVU185
+ 580 0142 E368     		ldr	r3, [r4, #12]
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 581              		.loc 1 419 58 discriminator 1 view .LVU186
+ 582 0144 012B     		cmp	r3, #1
+ 583 0146 40F06881 		bne	.L86
+ 584              	.L47:
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 585              		.loc 1 427 9 is_stmt 1 view .LVU187
+ 586 014a 484A     		ldr	r2, .L124
+ 587 014c 1368     		ldr	r3, [r2]
+ 588 014e 23F0F803 		bic	r3, r3, #248
+ 589 0152 2169     		ldr	r1, [r4, #16]
+ 590 0154 43EAC103 		orr	r3, r3, r1, lsl #3
+ 591 0158 1360     		str	r3, [r2]
+ 592              	.L44:
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       else
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Disable the Internal High Speed oscillator (HSI). */
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         __HAL_RCC_HSI_DISABLE();
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Get Start Tick*/
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Wait till HSI is ready */
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /*------------------------------ LSI Configuration -------------------------*/
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 593              		.loc 1 473 3 view .LVU188
+ 594              		.loc 1 473 26 is_stmt 0 view .LVU189
+ 595 015a 2368     		ldr	r3, [r4]
+ 596              		.loc 1 473 6 view .LVU190
+ 597 015c 13F0080F 		tst	r3, #8
+ 598 0160 46D0     		beq	.L53
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check the parameters */
+ARM GAS  /tmp/ccgleihc.s 			page 22
+
+
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+ 599              		.loc 1 476 5 is_stmt 1 view .LVU191
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check the LSI State */
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
+ 600              		.loc 1 479 5 view .LVU192
+ 601              		.loc 1 479 27 is_stmt 0 view .LVU193
+ 602 0162 6369     		ldr	r3, [r4, #20]
+ 603              		.loc 1 479 8 view .LVU194
+ 604 0164 83B3     		cbz	r3, .L54
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Enable the Internal Low Speed oscillator (LSI). */
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       __HAL_RCC_LSI_ENABLE();
+ 605              		.loc 1 482 7 is_stmt 1 view .LVU195
+ 606 0166 414A     		ldr	r2, .L124
+ 607 0168 536F     		ldr	r3, [r2, #116]
+ 608 016a 43F00103 		orr	r3, r3, #1
+ 609 016e 5367     		str	r3, [r2, #116]
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Get Start Tick*/
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ 610              		.loc 1 485 7 view .LVU196
+ 611              		.loc 1 485 19 is_stmt 0 view .LVU197
+ 612 0170 FFF7FEFF 		bl	HAL_GetTick
+ 613              	.LVL40:
+ 614 0174 0546     		mov	r5, r0
+ 615              	.LVL41:
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Wait till LSI is ready */
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ 616              		.loc 1 488 7 is_stmt 1 view .LVU198
+ 617              	.L55:
+ 618              		.loc 1 488 13 view .LVU199
+ 619              		.loc 1 488 14 is_stmt 0 view .LVU200
+ 620 0176 3D4B     		ldr	r3, .L124
+ 621 0178 5B6F     		ldr	r3, [r3, #116]
+ 622              		.loc 1 488 13 view .LVU201
+ 623 017a 13F0020F 		tst	r3, #2
+ 624 017e 37D1     		bne	.L53
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ 625              		.loc 1 490 9 is_stmt 1 view .LVU202
+ 626              		.loc 1 490 14 is_stmt 0 view .LVU203
+ 627 0180 FFF7FEFF 		bl	HAL_GetTick
+ 628              	.LVL42:
+ 629              		.loc 1 490 28 view .LVU204
+ 630 0184 401B     		subs	r0, r0, r5
+ 631              		.loc 1 490 12 view .LVU205
+ 632 0186 0228     		cmp	r0, #2
+ 633 0188 F5D9     		bls	.L55
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 634              		.loc 1 492 18 view .LVU206
+ 635 018a 0320     		movs	r0, #3
+ 636 018c 48E1     		b	.L31
+ 637              	.L114:
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ARM GAS  /tmp/ccgleihc.s 			page 23
+
+
+ 638              		.loc 1 451 9 is_stmt 1 view .LVU207
+ 639 018e 374A     		ldr	r2, .L124
+ 640 0190 1368     		ldr	r3, [r2]
+ 641 0192 23F0F803 		bic	r3, r3, #248
+ 642 0196 2169     		ldr	r1, [r4, #16]
+ 643 0198 43EAC103 		orr	r3, r3, r1, lsl #3
+ 644 019c 1360     		str	r3, [r2]
+ 645 019e DCE7     		b	.L44
+ 646              	.LVL43:
+ 647              	.L48:
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 648              		.loc 1 456 9 view .LVU208
+ 649 01a0 324A     		ldr	r2, .L124
+ 650 01a2 1368     		ldr	r3, [r2]
+ 651 01a4 23F00103 		bic	r3, r3, #1
+ 652 01a8 1360     		str	r3, [r2]
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 653              		.loc 1 459 9 view .LVU209
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 654              		.loc 1 459 21 is_stmt 0 view .LVU210
+ 655 01aa FFF7FEFF 		bl	HAL_GetTick
+ 656              	.LVL44:
+ 657 01ae 0546     		mov	r5, r0
+ 658              	.LVL45:
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 659              		.loc 1 462 9 is_stmt 1 view .LVU211
+ 660              	.L51:
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 661              		.loc 1 462 15 view .LVU212
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 662              		.loc 1 462 16 is_stmt 0 view .LVU213
+ 663 01b0 2E4B     		ldr	r3, .L124
+ 664 01b2 1B68     		ldr	r3, [r3]
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 665              		.loc 1 462 15 view .LVU214
+ 666 01b4 13F0020F 		tst	r3, #2
+ 667 01b8 CFD0     		beq	.L44
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 668              		.loc 1 464 11 is_stmt 1 view .LVU215
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 669              		.loc 1 464 16 is_stmt 0 view .LVU216
+ 670 01ba FFF7FEFF 		bl	HAL_GetTick
+ 671              	.LVL46:
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 672              		.loc 1 464 30 view .LVU217
+ 673 01be 401B     		subs	r0, r0, r5
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 674              		.loc 1 464 14 view .LVU218
+ 675 01c0 0228     		cmp	r0, #2
+ 676 01c2 F5D9     		bls	.L51
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 677              		.loc 1 466 20 view .LVU219
+ 678 01c4 0320     		movs	r0, #3
+ 679 01c6 2BE1     		b	.L31
+ 680              	.LVL47:
+ 681              	.L54:
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ARM GAS  /tmp/ccgleihc.s 			page 24
+
+
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     else
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Disable the Internal Low Speed oscillator (LSI). */
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       __HAL_RCC_LSI_DISABLE();
+ 682              		.loc 1 499 7 is_stmt 1 view .LVU220
+ 683 01c8 284A     		ldr	r2, .L124
+ 684 01ca 536F     		ldr	r3, [r2, #116]
+ 685 01cc 23F00103 		bic	r3, r3, #1
+ 686 01d0 5367     		str	r3, [r2, #116]
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Get Start Tick*/
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ 687              		.loc 1 502 7 view .LVU221
+ 688              		.loc 1 502 19 is_stmt 0 view .LVU222
+ 689 01d2 FFF7FEFF 		bl	HAL_GetTick
+ 690              	.LVL48:
+ 691 01d6 0546     		mov	r5, r0
+ 692              	.LVL49:
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Wait till LSI is ready */
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ 693              		.loc 1 505 7 is_stmt 1 view .LVU223
+ 694              	.L57:
+ 695              		.loc 1 505 13 view .LVU224
+ 696              		.loc 1 505 14 is_stmt 0 view .LVU225
+ 697 01d8 244B     		ldr	r3, .L124
+ 698 01da 5B6F     		ldr	r3, [r3, #116]
+ 699              		.loc 1 505 13 view .LVU226
+ 700 01dc 13F0020F 		tst	r3, #2
+ 701 01e0 06D0     		beq	.L53
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ 702              		.loc 1 507 9 is_stmt 1 view .LVU227
+ 703              		.loc 1 507 14 is_stmt 0 view .LVU228
+ 704 01e2 FFF7FEFF 		bl	HAL_GetTick
+ 705              	.LVL50:
+ 706              		.loc 1 507 28 view .LVU229
+ 707 01e6 401B     		subs	r0, r0, r5
+ 708              		.loc 1 507 12 view .LVU230
+ 709 01e8 0228     		cmp	r0, #2
+ 710 01ea F5D9     		bls	.L57
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 711              		.loc 1 509 18 view .LVU231
+ 712 01ec 0320     		movs	r0, #3
+ 713 01ee 17E1     		b	.L31
+ 714              	.LVL51:
+ 715              	.L53:
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /*------------------------------ LSE Configuration -------------------------*/
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 716              		.loc 1 515 3 is_stmt 1 view .LVU232
+ARM GAS  /tmp/ccgleihc.s 			page 25
+
+
+ 717              		.loc 1 515 26 is_stmt 0 view .LVU233
+ 718 01f0 2368     		ldr	r3, [r4]
+ 719              		.loc 1 515 6 view .LVU234
+ 720 01f2 13F0040F 		tst	r3, #4
+ 721 01f6 7DD0     		beq	.L59
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check the parameters */
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+ 722              		.loc 1 518 5 is_stmt 1 view .LVU235
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Update LSE configuration in Backup Domain control register    */
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Requires to enable write access to Backup Domain of necessary */
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 723              		.loc 1 522 5 view .LVU236
+ 724              		.loc 1 522 9 is_stmt 0 view .LVU237
+ 725 01f8 1C4B     		ldr	r3, .L124
+ 726 01fa 1B6C     		ldr	r3, [r3, #64]
+ 727              		.loc 1 522 8 view .LVU238
+ 728 01fc 13F0805F 		tst	r3, #268435456
+ 729 0200 1ED1     		bne	.L91
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Enable Power Clock*/
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       __HAL_RCC_PWR_CLK_ENABLE();
+ 730              		.loc 1 525 7 is_stmt 1 view .LVU239
+ 731              	.LBB4:
+ 732              		.loc 1 525 7 view .LVU240
+ 733              		.loc 1 525 7 view .LVU241
+ 734 0202 1A4B     		ldr	r3, .L124
+ 735 0204 1A6C     		ldr	r2, [r3, #64]
+ 736 0206 42F08052 		orr	r2, r2, #268435456
+ 737 020a 1A64     		str	r2, [r3, #64]
+ 738              		.loc 1 525 7 view .LVU242
+ 739 020c 1B6C     		ldr	r3, [r3, #64]
+ 740 020e 03F08053 		and	r3, r3, #268435456
+ 741 0212 0193     		str	r3, [sp, #4]
+ 742              		.loc 1 525 7 view .LVU243
+ 743 0214 019B     		ldr	r3, [sp, #4]
+ 744              	.LBE4:
+ 745              		.loc 1 525 7 view .LVU244
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       pwrclkchanged = SET;
+ 746              		.loc 1 526 7 view .LVU245
+ 747              	.LVL52:
+ 748              		.loc 1 526 21 is_stmt 0 view .LVU246
+ 749 0216 0125     		movs	r5, #1
+ 750              	.LVL53:
+ 751              	.L60:
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 752              		.loc 1 529 5 is_stmt 1 view .LVU247
+ 753              		.loc 1 529 9 is_stmt 0 view .LVU248
+ 754 0218 154B     		ldr	r3, .L124+4
+ 755 021a 1B68     		ldr	r3, [r3]
+ 756              		.loc 1 529 8 view .LVU249
+ 757 021c 13F4807F 		tst	r3, #256
+ 758 0220 10D0     		beq	.L116
+ 759              	.L61:
+ARM GAS  /tmp/ccgleihc.s 			page 26
+
+
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Enable write access to Backup domain */
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       PWR->CR1 |= PWR_CR1_DBP;
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Wait for Backup domain Write protection disable */
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Set the new LSE configuration -----------------------------------------*/
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 760              		.loc 1 547 5 is_stmt 1 view .LVU250
+ 761              		.loc 1 547 5 view .LVU251
+ 762 0222 A368     		ldr	r3, [r4, #8]
+ 763 0224 012B     		cmp	r3, #1
+ 764 0226 25D0     		beq	.L117
+ 765              		.loc 1 547 5 discriminator 2 view .LVU252
+ 766 0228 002B     		cmp	r3, #0
+ 767 022a 3BD1     		bne	.L66
+ 768              		.loc 1 547 5 discriminator 4 view .LVU253
+ 769 022c 0F4B     		ldr	r3, .L124
+ 770 022e 1A6F     		ldr	r2, [r3, #112]
+ 771 0230 22F00102 		bic	r2, r2, #1
+ 772 0234 1A67     		str	r2, [r3, #112]
+ 773              		.loc 1 547 5 discriminator 4 view .LVU254
+ 774 0236 1A6F     		ldr	r2, [r3, #112]
+ 775 0238 22F00402 		bic	r2, r2, #4
+ 776 023c 1A67     		str	r2, [r3, #112]
+ 777 023e 1EE0     		b	.L65
+ 778              	.LVL54:
+ 779              	.L91:
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 780              		.loc 1 346 14 is_stmt 0 view .LVU255
+ 781 0240 0025     		movs	r5, #0
+ 782 0242 E9E7     		b	.L60
+ 783              	.LVL55:
+ 784              	.L116:
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 785              		.loc 1 532 7 is_stmt 1 view .LVU256
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 786              		.loc 1 532 16 is_stmt 0 view .LVU257
+ 787 0244 0A4A     		ldr	r2, .L124+4
+ 788 0246 1368     		ldr	r3, [r2]
+ 789 0248 43F48073 		orr	r3, r3, #256
+ 790 024c 1360     		str	r3, [r2]
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 791              		.loc 1 535 7 is_stmt 1 view .LVU258
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 792              		.loc 1 535 19 is_stmt 0 view .LVU259
+ 793 024e FFF7FEFF 		bl	HAL_GetTick
+ARM GAS  /tmp/ccgleihc.s 			page 27
+
+
+ 794              	.LVL56:
+ 795 0252 0646     		mov	r6, r0
+ 796              	.LVL57:
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 797              		.loc 1 537 7 is_stmt 1 view .LVU260
+ 798              	.L62:
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 799              		.loc 1 537 13 view .LVU261
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 800              		.loc 1 537 14 is_stmt 0 view .LVU262
+ 801 0254 064B     		ldr	r3, .L124+4
+ 802 0256 1B68     		ldr	r3, [r3]
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 803              		.loc 1 537 13 view .LVU263
+ 804 0258 13F4807F 		tst	r3, #256
+ 805 025c E1D1     		bne	.L61
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 806              		.loc 1 539 9 is_stmt 1 view .LVU264
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 807              		.loc 1 539 14 is_stmt 0 view .LVU265
+ 808 025e FFF7FEFF 		bl	HAL_GetTick
+ 809              	.LVL58:
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 810              		.loc 1 539 28 view .LVU266
+ 811 0262 801B     		subs	r0, r0, r6
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 812              		.loc 1 539 12 view .LVU267
+ 813 0264 6428     		cmp	r0, #100
+ 814 0266 F5D9     		bls	.L62
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 815              		.loc 1 541 18 view .LVU268
+ 816 0268 0320     		movs	r0, #3
+ 817 026a D9E0     		b	.L31
+ 818              	.L125:
+ 819              		.align	2
+ 820              	.L124:
+ 821 026c 00380240 		.word	1073887232
+ 822 0270 00700040 		.word	1073770496
+ 823              	.LVL59:
+ 824              	.L117:
+ 825              		.loc 1 547 5 is_stmt 1 discriminator 1 view .LVU269
+ 826 0274 724A     		ldr	r2, .L126
+ 827 0276 136F     		ldr	r3, [r2, #112]
+ 828 0278 43F00103 		orr	r3, r3, #1
+ 829 027c 1367     		str	r3, [r2, #112]
+ 830              	.L65:
+ 831              		.loc 1 547 5 discriminator 10 view .LVU270
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check the LSE State */
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+ 832              		.loc 1 549 5 discriminator 10 view .LVU271
+ 833              		.loc 1 549 27 is_stmt 0 discriminator 10 view .LVU272
+ 834 027e A368     		ldr	r3, [r4, #8]
+ 835              		.loc 1 549 8 discriminator 10 view .LVU273
+ 836 0280 33B3     		cbz	r3, .L68
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Get Start Tick*/
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ARM GAS  /tmp/ccgleihc.s 			page 28
+
+
+ 837              		.loc 1 552 7 is_stmt 1 view .LVU274
+ 838              		.loc 1 552 19 is_stmt 0 view .LVU275
+ 839 0282 FFF7FEFF 		bl	HAL_GetTick
+ 840              	.LVL60:
+ 841 0286 0646     		mov	r6, r0
+ 842              	.LVL61:
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Wait till LSE is ready */
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 843              		.loc 1 555 7 is_stmt 1 view .LVU276
+ 844              	.L69:
+ 845              		.loc 1 555 13 view .LVU277
+ 846              		.loc 1 555 14 is_stmt 0 view .LVU278
+ 847 0288 6D4B     		ldr	r3, .L126
+ 848 028a 1B6F     		ldr	r3, [r3, #112]
+ 849              		.loc 1 555 13 view .LVU279
+ 850 028c 13F0020F 		tst	r3, #2
+ 851 0290 2FD1     		bne	.L71
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 852              		.loc 1 557 9 is_stmt 1 view .LVU280
+ 853              		.loc 1 557 14 is_stmt 0 view .LVU281
+ 854 0292 FFF7FEFF 		bl	HAL_GetTick
+ 855              	.LVL62:
+ 856              		.loc 1 557 28 view .LVU282
+ 857 0296 801B     		subs	r0, r0, r6
+ 858              		.loc 1 557 12 view .LVU283
+ 859 0298 41F28833 		movw	r3, #5000
+ 860 029c 9842     		cmp	r0, r3
+ 861 029e F3D9     		bls	.L69
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 862              		.loc 1 559 18 view .LVU284
+ 863 02a0 0320     		movs	r0, #3
+ 864 02a2 BDE0     		b	.L31
+ 865              	.LVL63:
+ 866              	.L66:
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check the LSE State */
+ 867              		.loc 1 547 5 is_stmt 1 discriminator 5 view .LVU285
+ 868 02a4 052B     		cmp	r3, #5
+ 869 02a6 09D0     		beq	.L118
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check the LSE State */
+ 870              		.loc 1 547 5 discriminator 8 view .LVU286
+ 871 02a8 654B     		ldr	r3, .L126
+ 872 02aa 1A6F     		ldr	r2, [r3, #112]
+ 873 02ac 22F00102 		bic	r2, r2, #1
+ 874 02b0 1A67     		str	r2, [r3, #112]
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check the LSE State */
+ 875              		.loc 1 547 5 discriminator 8 view .LVU287
+ 876 02b2 1A6F     		ldr	r2, [r3, #112]
+ 877 02b4 22F00402 		bic	r2, r2, #4
+ 878 02b8 1A67     		str	r2, [r3, #112]
+ 879 02ba E0E7     		b	.L65
+ 880              	.L118:
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check the LSE State */
+ 881              		.loc 1 547 5 discriminator 7 view .LVU288
+ 882 02bc 604B     		ldr	r3, .L126
+ARM GAS  /tmp/ccgleihc.s 			page 29
+
+
+ 883 02be 1A6F     		ldr	r2, [r3, #112]
+ 884 02c0 42F00402 		orr	r2, r2, #4
+ 885 02c4 1A67     		str	r2, [r3, #112]
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check the LSE State */
+ 886              		.loc 1 547 5 discriminator 7 view .LVU289
+ 887 02c6 1A6F     		ldr	r2, [r3, #112]
+ 888 02c8 42F00102 		orr	r2, r2, #1
+ 889 02cc 1A67     		str	r2, [r3, #112]
+ 890 02ce D6E7     		b	.L65
+ 891              	.L68:
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     else
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Get Start Tick*/
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       tickstart = HAL_GetTick();
+ 892              		.loc 1 566 7 view .LVU290
+ 893              		.loc 1 566 19 is_stmt 0 view .LVU291
+ 894 02d0 FFF7FEFF 		bl	HAL_GetTick
+ 895              	.LVL64:
+ 896 02d4 0646     		mov	r6, r0
+ 897              	.LVL65:
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Wait till LSE is ready */
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ 898              		.loc 1 569 7 is_stmt 1 view .LVU292
+ 899              	.L72:
+ 900              		.loc 1 569 13 view .LVU293
+ 901              		.loc 1 569 14 is_stmt 0 view .LVU294
+ 902 02d6 5A4B     		ldr	r3, .L126
+ 903 02d8 1B6F     		ldr	r3, [r3, #112]
+ 904              		.loc 1 569 13 view .LVU295
+ 905 02da 13F0020F 		tst	r3, #2
+ 906 02de 08D0     		beq	.L71
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 907              		.loc 1 571 9 is_stmt 1 view .LVU296
+ 908              		.loc 1 571 14 is_stmt 0 view .LVU297
+ 909 02e0 FFF7FEFF 		bl	HAL_GetTick
+ 910              	.LVL66:
+ 911              		.loc 1 571 28 view .LVU298
+ 912 02e4 801B     		subs	r0, r0, r6
+ 913              		.loc 1 571 12 view .LVU299
+ 914 02e6 41F28833 		movw	r3, #5000
+ 915 02ea 9842     		cmp	r0, r3
+ 916 02ec F3D9     		bls	.L72
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           return HAL_TIMEOUT;
+ 917              		.loc 1 573 18 view .LVU300
+ 918 02ee 0320     		movs	r0, #3
+ 919 02f0 96E0     		b	.L31
+ 920              	.L71:
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ARM GAS  /tmp/ccgleihc.s 			page 30
+
+
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Restore clock configuration if changed */
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if (pwrclkchanged == SET)
+ 921              		.loc 1 579 5 is_stmt 1 view .LVU301
+ 922              		.loc 1 579 8 is_stmt 0 view .LVU302
+ 923 02f2 FDB9     		cbnz	r5, .L119
+ 924              	.LVL67:
+ 925              	.L59:
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       __HAL_RCC_PWR_CLK_DISABLE();
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /*-------------------------------- PLL Configuration -----------------------*/
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Check the parameters */
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ 926              		.loc 1 586 3 is_stmt 1 view .LVU303
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ 927              		.loc 1 587 3 view .LVU304
+ 928              		.loc 1 587 30 is_stmt 0 view .LVU305
+ 929 02f4 A369     		ldr	r3, [r4, #24]
+ 930              		.loc 1 587 6 view .LVU306
+ 931 02f6 002B     		cmp	r3, #0
+ 932 02f8 00F09180 		beq	.L95
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check if the PLL is used as system clock or not */
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ 933              		.loc 1 590 5 is_stmt 1 view .LVU307
+ 934              		.loc 1 590 9 is_stmt 0 view .LVU308
+ 935 02fc 504A     		ldr	r2, .L126
+ 936 02fe 9268     		ldr	r2, [r2, #8]
+ 937 0300 02F00C02 		and	r2, r2, #12
+ 938              		.loc 1 590 8 view .LVU309
+ 939 0304 082A     		cmp	r2, #8
+ 940 0306 59D0     		beq	.L74
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ 941              		.loc 1 592 7 is_stmt 1 view .LVU310
+ 942              		.loc 1 592 10 is_stmt 0 view .LVU311
+ 943 0308 022B     		cmp	r3, #2
+ 944 030a 19D0     		beq	.L120
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Check the parameters */
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR)
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Disable the main PLL. */
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         __HAL_RCC_PLL_DISABLE();
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Get Start Tick*/
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Wait till PLL is ready */
+ARM GAS  /tmp/ccgleihc.s 			page 31
+
+
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Configure the main PLL clock source, multiplication and division factors. */
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR)
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLM,
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLN,
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLP,
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLQ,
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLR);
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLM,
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLN,
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLP,
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLQ);
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Enable the main PLL. */
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         __HAL_RCC_PLL_ENABLE();
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Get Start Tick*/
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Wait till PLL is ready */
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       else
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Disable the main PLL. */
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         __HAL_RCC_PLL_DISABLE();
+ 945              		.loc 1 653 9 is_stmt 1 view .LVU312
+ 946 030c 4C4A     		ldr	r2, .L126
+ 947 030e 1368     		ldr	r3, [r2]
+ 948 0310 23F08073 		bic	r3, r3, #16777216
+ 949 0314 1360     		str	r3, [r2]
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Get Start Tick*/
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         tickstart = HAL_GetTick();
+ 950              		.loc 1 656 9 view .LVU313
+ 951              		.loc 1 656 21 is_stmt 0 view .LVU314
+ 952 0316 FFF7FEFF 		bl	HAL_GetTick
+ 953              	.LVL68:
+ 954 031a 0446     		mov	r4, r0
+ 955              	.LVL69:
+ARM GAS  /tmp/ccgleihc.s 			page 32
+
+
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* Wait till PLL is ready */
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ 956              		.loc 1 659 9 is_stmt 1 view .LVU315
+ 957              	.L80:
+ 958              		.loc 1 659 15 view .LVU316
+ 959              		.loc 1 659 16 is_stmt 0 view .LVU317
+ 960 031c 484B     		ldr	r3, .L126
+ 961 031e 1B68     		ldr	r3, [r3]
+ 962              		.loc 1 659 15 view .LVU318
+ 963 0320 13F0007F 		tst	r3, #33554432
+ 964 0324 48D0     		beq	.L121
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 965              		.loc 1 661 11 is_stmt 1 view .LVU319
+ 966              		.loc 1 661 16 is_stmt 0 view .LVU320
+ 967 0326 FFF7FEFF 		bl	HAL_GetTick
+ 968              	.LVL70:
+ 969              		.loc 1 661 30 view .LVU321
+ 970 032a 001B     		subs	r0, r0, r4
+ 971              		.loc 1 661 14 view .LVU322
+ 972 032c 0228     		cmp	r0, #2
+ 973 032e F5D9     		bls	.L80
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****             return HAL_TIMEOUT;
+ 974              		.loc 1 663 20 view .LVU323
+ 975 0330 0320     		movs	r0, #3
+ 976 0332 75E0     		b	.L31
+ 977              	.LVL71:
+ 978              	.L119:
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 979              		.loc 1 581 7 is_stmt 1 view .LVU324
+ 980 0334 424A     		ldr	r2, .L126
+ 981 0336 136C     		ldr	r3, [r2, #64]
+ 982 0338 23F08053 		bic	r3, r3, #268435456
+ 983 033c 1364     		str	r3, [r2, #64]
+ 984 033e D9E7     		b	.L59
+ 985              	.LVL72:
+ 986              	.L120:
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+ 987              		.loc 1 595 9 view .LVU325
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+ 988              		.loc 1 596 9 view .LVU326
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+ 989              		.loc 1 597 9 view .LVU327
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+ 990              		.loc 1 598 9 view .LVU328
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR)
+ 991              		.loc 1 599 9 view .LVU329
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif
+ 992              		.loc 1 601 9 view .LVU330
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 993              		.loc 1 605 9 view .LVU331
+ 994 0340 3F4A     		ldr	r2, .L126
+ 995 0342 1368     		ldr	r3, [r2]
+ 996 0344 23F08073 		bic	r3, r3, #16777216
+ 997 0348 1360     		str	r3, [r2]
+ARM GAS  /tmp/ccgleihc.s 			page 33
+
+
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 998              		.loc 1 608 9 view .LVU332
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 999              		.loc 1 608 21 is_stmt 0 view .LVU333
+ 1000 034a FFF7FEFF 		bl	HAL_GetTick
+ 1001              	.LVL73:
+ 1002 034e 0546     		mov	r5, r0
+ 1003              	.LVL74:
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 1004              		.loc 1 611 9 is_stmt 1 view .LVU334
+ 1005              	.L76:
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 1006              		.loc 1 611 15 view .LVU335
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 1007              		.loc 1 611 16 is_stmt 0 view .LVU336
+ 1008 0350 3B4B     		ldr	r3, .L126
+ 1009 0352 1B68     		ldr	r3, [r3]
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 1010              		.loc 1 611 15 view .LVU337
+ 1011 0354 13F0007F 		tst	r3, #33554432
+ 1012 0358 06D0     		beq	.L122
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 1013              		.loc 1 613 11 is_stmt 1 view .LVU338
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 1014              		.loc 1 613 16 is_stmt 0 view .LVU339
+ 1015 035a FFF7FEFF 		bl	HAL_GetTick
+ 1016              	.LVL75:
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 1017              		.loc 1 613 30 view .LVU340
+ 1018 035e 401B     		subs	r0, r0, r5
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 1019              		.loc 1 613 14 view .LVU341
+ 1020 0360 0228     		cmp	r0, #2
+ 1021 0362 F5D9     		bls	.L76
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 1022              		.loc 1 615 20 view .LVU342
+ 1023 0364 0320     		movs	r0, #3
+ 1024 0366 5BE0     		b	.L31
+ 1025              	.L122:
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                              RCC_OscInitStruct->PLL.PLLM,
+ 1026              		.loc 1 621 9 is_stmt 1 view .LVU343
+ 1027 0368 E369     		ldr	r3, [r4, #28]
+ 1028 036a 226A     		ldr	r2, [r4, #32]
+ 1029 036c 1343     		orrs	r3, r3, r2
+ 1030 036e 626A     		ldr	r2, [r4, #36]
+ 1031 0370 43EA8213 		orr	r3, r3, r2, lsl #6
+ 1032 0374 A26A     		ldr	r2, [r4, #40]
+ 1033 0376 5208     		lsrs	r2, r2, #1
+ 1034 0378 013A     		subs	r2, r2, #1
+ 1035 037a 43EA0243 		orr	r3, r3, r2, lsl #16
+ 1036 037e E26A     		ldr	r2, [r4, #44]
+ 1037 0380 43EA0263 		orr	r3, r3, r2, lsl #24
+ 1038 0384 226B     		ldr	r2, [r4, #48]
+ 1039 0386 43EA0273 		orr	r3, r3, r2, lsl #28
+ 1040 038a 2D4A     		ldr	r2, .L126
+ 1041 038c 5360     		str	r3, [r2, #4]
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ARM GAS  /tmp/ccgleihc.s 			page 34
+
+
+ 1042              		.loc 1 636 9 view .LVU344
+ 1043 038e 1368     		ldr	r3, [r2]
+ 1044 0390 43F08073 		orr	r3, r3, #16777216
+ 1045 0394 1360     		str	r3, [r2]
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1046              		.loc 1 639 9 view .LVU345
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1047              		.loc 1 639 21 is_stmt 0 view .LVU346
+ 1048 0396 FFF7FEFF 		bl	HAL_GetTick
+ 1049              	.LVL76:
+ 1050 039a 0446     		mov	r4, r0
+ 1051              	.LVL77:
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 1052              		.loc 1 642 9 is_stmt 1 view .LVU347
+ 1053              	.L78:
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 1054              		.loc 1 642 15 view .LVU348
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 1055              		.loc 1 642 16 is_stmt 0 view .LVU349
+ 1056 039c 284B     		ldr	r3, .L126
+ 1057 039e 1B68     		ldr	r3, [r3]
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         {
+ 1058              		.loc 1 642 15 view .LVU350
+ 1059 03a0 13F0007F 		tst	r3, #33554432
+ 1060 03a4 06D1     		bne	.L123
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 1061              		.loc 1 644 11 is_stmt 1 view .LVU351
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 1062              		.loc 1 644 16 is_stmt 0 view .LVU352
+ 1063 03a6 FFF7FEFF 		bl	HAL_GetTick
+ 1064              	.LVL78:
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 1065              		.loc 1 644 30 view .LVU353
+ 1066 03aa 001B     		subs	r0, r0, r4
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           {
+ 1067              		.loc 1 644 14 view .LVU354
+ 1068 03ac 0228     		cmp	r0, #2
+ 1069 03ae F5D9     		bls	.L78
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 1070              		.loc 1 646 20 view .LVU355
+ 1071 03b0 0320     		movs	r0, #3
+ 1072 03b2 35E0     		b	.L31
+ 1073              	.L123:
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           }
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         }
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     else
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Do not return HAL_ERROR if request repeats the current configuration */
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       pll_config = RCC->PLLCFGR;
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR)
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) 
+ARM GAS  /tmp/ccgleihc.s 			page 35
+
+
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) 
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         return HAL_ERROR;
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   return HAL_OK;
+ 1074              		.loc 1 693 10 view .LVU356
+ 1075 03b4 0020     		movs	r0, #0
+ 1076 03b6 33E0     		b	.L31
+ 1077              	.L121:
+ 1078              		.loc 1 693 10 view .LVU357
+ 1079 03b8 0020     		movs	r0, #0
+ 1080 03ba 31E0     		b	.L31
+ 1081              	.LVL79:
+ 1082              	.L74:
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR)
+ 1083              		.loc 1 671 7 is_stmt 1 view .LVU358
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR)
+ 1084              		.loc 1 671 18 is_stmt 0 view .LVU359
+ 1085 03bc 204A     		ldr	r2, .L126
+ 1086 03be 5268     		ldr	r2, [r2, #4]
+ 1087              	.LVL80:
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 1088              		.loc 1 673 7 is_stmt 1 view .LVU360
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 1089              		.loc 1 673 10 is_stmt 0 view .LVU361
+ 1090 03c0 012B     		cmp	r3, #1
+ 1091 03c2 2FD0     		beq	.L99
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+ 1092              		.loc 1 674 12 discriminator 1 view .LVU362
+ 1093 03c4 02F48003 		and	r3, r2, #4194304
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+ 1094              		.loc 1 674 78 discriminator 1 view .LVU363
+ 1095 03c8 E169     		ldr	r1, [r4, #28]
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 1096              		.loc 1 673 62 discriminator 1 view .LVU364
+ 1097 03ca 8B42     		cmp	r3, r1
+ 1098 03cc 2CD1     		bne	.L100
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL
+ 1099              		.loc 1 675 12 view .LVU365
+ 1100 03ce 02F03F03 		and	r3, r2, #63
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL
+ 1101              		.loc 1 675 76 view .LVU366
+ 1102 03d2 216A     		ldr	r1, [r4, #32]
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+ 1103              		.loc 1 674 90 view .LVU367
+ 1104 03d4 8B42     		cmp	r3, r1
+ARM GAS  /tmp/ccgleihc.s 			page 36
+
+
+ 1105 03d6 29D1     		bne	.L101
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) 
+ 1106              		.loc 1 676 77 view .LVU368
+ 1107 03d8 616A     		ldr	r1, [r4, #36]
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL
+ 1108              		.loc 1 675 83 view .LVU369
+ 1109 03da 47F6C073 		movw	r3, #32704
+ 1110 03de 1340     		ands	r3, r3, r2
+ 1111 03e0 B3EB811F 		cmp	r3, r1, lsl #6
+ 1112 03e4 24D1     		bne	.L102
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL
+ 1113              		.loc 1 677 12 view .LVU370
+ 1114 03e6 02F44031 		and	r1, r2, #196608
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL
+ 1115              		.loc 1 677 80 view .LVU371
+ 1116 03ea A36A     		ldr	r3, [r4, #40]
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL
+ 1117              		.loc 1 677 87 view .LVU372
+ 1118 03ec 5B08     		lsrs	r3, r3, #1
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL
+ 1119              		.loc 1 677 94 view .LVU373
+ 1120 03ee 013B     		subs	r3, r3, #1
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) 
+ 1121              		.loc 1 676 109 view .LVU374
+ 1122 03f0 B1EB034F 		cmp	r1, r3, lsl #16
+ 1123 03f4 1ED1     		bne	.L103
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL
+ 1124              		.loc 1 678 12 view .LVU375
+ 1125 03f6 02F07063 		and	r3, r2, #251658240
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL
+ 1126              		.loc 1 678 77 view .LVU376
+ 1127 03fa E16A     		ldr	r1, [r4, #44]
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL
+ 1128              		.loc 1 677 126 view .LVU377
+ 1129 03fc B3EB016F 		cmp	r3, r1, lsl #24
+ 1130 0400 1AD1     		bne	.L104
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else
+ 1131              		.loc 1 679 12 view .LVU378
+ 1132 0402 02F0E042 		and	r2, r2, #1879048192
+ 1133              	.LVL81:
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else
+ 1134              		.loc 1 679 77 view .LVU379
+ 1135 0406 236B     		ldr	r3, [r4, #48]
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****           (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL
+ 1136              		.loc 1 678 109 view .LVU380
+ 1137 0408 B2EB037F 		cmp	r2, r3, lsl #28
+ 1138 040c 16D1     		bne	.L105
+ 1139              		.loc 1 693 10 view .LVU381
+ 1140 040e 0020     		movs	r0, #0
+ 1141 0410 06E0     		b	.L31
+ 1142              	.LVL82:
+ 1143              	.L82:
+ 1144              	.LCFI3:
+ 1145              		.cfi_def_cfa_offset 0
+ 1146              		.cfi_restore 4
+ 1147              		.cfi_restore 5
+ 1148              		.cfi_restore 6
+ARM GAS  /tmp/ccgleihc.s 			page 37
+
+
+ 1149              		.cfi_restore 14
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 1150              		.loc 1 351 12 view .LVU382
+ 1151 0412 0120     		movs	r0, #1
+ 1152              	.LVL83:
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 1153              		.loc 1 694 1 view .LVU383
+ 1154 0414 7047     		bx	lr
+ 1155              	.LVL84:
+ 1156              	.L112:
+ 1157              	.LCFI4:
+ 1158              		.cfi_def_cfa_offset 24
+ 1159              		.cfi_offset 4, -16
+ 1160              		.cfi_offset 5, -12
+ 1161              		.cfi_offset 6, -8
+ 1162              		.cfi_offset 14, -4
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1163              		.loc 1 368 16 view .LVU384
+ 1164 0416 0120     		movs	r0, #1
+ 1165              	.LVL85:
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1166              		.loc 1 368 16 view .LVU385
+ 1167 0418 02E0     		b	.L31
+ 1168              	.L86:
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1169              		.loc 1 421 16 view .LVU386
+ 1170 041a 0120     		movs	r0, #1
+ 1171 041c 00E0     		b	.L31
+ 1172              	.LVL86:
+ 1173              	.L95:
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 1174              		.loc 1 693 10 view .LVU387
+ 1175 041e 0020     		movs	r0, #0
+ 1176              	.LVL87:
+ 1177              	.L31:
+ 1178              		.loc 1 694 1 view .LVU388
+ 1179 0420 02B0     		add	sp, sp, #8
+ 1180              	.LCFI5:
+ 1181              		.cfi_remember_state
+ 1182              		.cfi_def_cfa_offset 16
+ 1183              		@ sp needed
+ 1184 0422 70BD     		pop	{r4, r5, r6, pc}
+ 1185              	.LVL88:
+ 1186              	.L99:
+ 1187              	.LCFI6:
+ 1188              		.cfi_restore_state
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1189              		.loc 1 689 16 view .LVU389
+ 1190 0424 0120     		movs	r0, #1
+ 1191 0426 FBE7     		b	.L31
+ 1192              	.L100:
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1193              		.loc 1 689 16 view .LVU390
+ 1194 0428 0120     		movs	r0, #1
+ 1195 042a F9E7     		b	.L31
+ 1196              	.L101:
+ 1197 042c 0120     		movs	r0, #1
+ARM GAS  /tmp/ccgleihc.s 			page 38
+
+
+ 1198 042e F7E7     		b	.L31
+ 1199              	.L102:
+ 1200 0430 0120     		movs	r0, #1
+ 1201 0432 F5E7     		b	.L31
+ 1202              	.L103:
+ 1203 0434 0120     		movs	r0, #1
+ 1204 0436 F3E7     		b	.L31
+ 1205              	.L104:
+ 1206 0438 0120     		movs	r0, #1
+ 1207 043a F1E7     		b	.L31
+ 1208              	.LVL89:
+ 1209              	.L105:
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1210              		.loc 1 689 16 view .LVU391
+ 1211 043c 0120     		movs	r0, #1
+ 1212 043e EFE7     		b	.L31
+ 1213              	.L127:
+ 1214              		.align	2
+ 1215              	.L126:
+ 1216 0440 00380240 		.word	1073887232
+ 1217              		.cfi_endproc
+ 1218              	.LFE142:
+ 1220              		.section	.text.HAL_RCC_MCOConfig,"ax",%progbits
+ 1221              		.align	1
+ 1222              		.global	HAL_RCC_MCOConfig
+ 1223              		.syntax unified
+ 1224              		.thumb
+ 1225              		.thumb_func
+ 1226              		.fpu fpv5-d16
+ 1228              	HAL_RCC_MCOConfig:
+ 1229              	.LVL90:
+ 1230              	.LFB144:
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         parameters in the RCC_ClkInitStruct.
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         contains the configuration information for the RCC peripheral.
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @param  FLatency FLASH Latency, this parameter depend on device selected
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   The HSI is used (enabled by hardware) as system clock source after
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         of failure of the HSE used directly or indirectly as system clock
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         (if the Clock Security System CSS is enabled).
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   A switch from one clock source to another occurs only if the target
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         clock source is ready (clock stable after startup delay or PLL locked).
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         If a clock source which is not yet ready is selected, the switch will
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         occur when the clock source will be ready.
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         You can use HAL_RCC_GetClockConfig() function to know which clock is
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         currently used as system clock source.
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   Depending on the device voltage range, the software has to set correctly
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         (for more details refer to section above "Initialization/de-initialization functions")
+ARM GAS  /tmp/ccgleihc.s 			page 39
+
+
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval None
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   uint32_t tickstart = 0;
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Check Null pointer */
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (RCC_ClkInitStruct == NULL)
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     return HAL_ERROR;
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Check the parameters */
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   assert_param(IS_FLASH_LATENCY(FLatency));
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****      must be correctly programmed according to the frequency of the CPU clock
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****      (HCLK) and the supply voltage of the device. */
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Increasing the CPU frequency */
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (FLatency > __HAL_FLASH_GET_LATENCY())
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     __HAL_FLASH_SET_LATENCY(FLatency);
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check that the new number of wait states is taken into account to access the Flash
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     memory by reading the FLASH_ACR register */
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       return HAL_ERROR;
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /*-------------------------- HCLK Configuration --------------------------*/
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Set the highest APBx dividers in order to ensure that we do not go through
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****        a non-spec phase whatever we decrease or increase HCLK. */
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Set the new HCLK clock divider */
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /*------------------------- SYSCLK Configuration ---------------------------*/
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ARM GAS  /tmp/ccgleihc.s 			page 40
+
+
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* HSE is selected as System Clock Source */
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Check the HSE ready flag */
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         return HAL_ERROR;
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* PLL is selected as System Clock Source */
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Check the PLL ready flag */
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         return HAL_ERROR;
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* HSI is selected as System Clock Source */
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     else
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* Check the HSI ready flag */
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         return HAL_ERROR;
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Get Start Tick*/
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     tickstart = HAL_GetTick();
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         return HAL_TIMEOUT;
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Decreasing the number of wait states because of lower CPU frequency */
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (FLatency < __HAL_FLASH_GET_LATENCY())
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     __HAL_FLASH_SET_LATENCY(FLatency);
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Check that the new number of wait states is taken into account to access the Flash
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     memory by reading the FLASH_ACR register */
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     if (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       return HAL_ERROR;
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ARM GAS  /tmp/ccgleihc.s 			page 41
+
+
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /*-------------------------- PCLK1 Configuration ---------------------------*/
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /*-------------------------- PCLK2 Configuration ---------------------------*/
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Update the SystemCoreClock global variable */
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_C
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Configure the source of time base considering new system clocks settings*/
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   HAL_InitTick(uwTickPrio);
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   return HAL_OK;
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @}
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *  @brief   RCC clocks control functions
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   @verbatim
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   ===============================================================================
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****                   ##### Peripheral Control functions #####
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   ===============================================================================
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     [..]
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     This subsection provides a set of functions allowing to control the RCC Clocks
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     frequencies.
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @endverbatim
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @{
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   PA8/PC9 should be configured in alternate function mode.
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @param  RCC_MCOx specifies the output direction for the clock source.
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *          This parameter can be one of the following values:
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @param  RCC_MCOSource specifies the clock source to output.
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *          This parameter can be one of the following values:
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+ARM GAS  /tmp/ccgleihc.s 			page 42
+
+
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @param  RCC_MCODiv specifies the MCOx prescaler.
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *          This parameter can be one of the following values:
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval None
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 1231              		.loc 1 904 1 is_stmt 1 view -0
+ 1232              		.cfi_startproc
+ 1233              		@ args = 0, pretend = 0, frame = 32
+ 1234              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1235              		.loc 1 904 1 is_stmt 0 view .LVU393
+ 1236 0000 70B5     		push	{r4, r5, r6, lr}
+ 1237              	.LCFI7:
+ 1238              		.cfi_def_cfa_offset 16
+ 1239              		.cfi_offset 4, -16
+ 1240              		.cfi_offset 5, -12
+ 1241              		.cfi_offset 6, -8
+ 1242              		.cfi_offset 14, -4
+ 1243 0002 88B0     		sub	sp, sp, #32
+ 1244              	.LCFI8:
+ 1245              		.cfi_def_cfa_offset 48
+ 1246 0004 0C46     		mov	r4, r1
+ 1247 0006 1546     		mov	r5, r2
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   GPIO_InitTypeDef GPIO_InitStruct;
+ 1248              		.loc 1 905 3 is_stmt 1 view .LVU394
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Check the parameters */
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   assert_param(IS_RCC_MCO(RCC_MCOx));
+ 1249              		.loc 1 907 3 view .LVU395
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+ 1250              		.loc 1 908 3 view .LVU396
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* RCC_MCO1 */
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (RCC_MCOx == RCC_MCO1)
+ 1251              		.loc 1 910 3 view .LVU397
+ 1252              		.loc 1 910 6 is_stmt 0 view .LVU398
+ 1253 0008 F8B9     		cbnz	r0, .L129
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+ 1254              		.loc 1 912 5 is_stmt 1 view .LVU399
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* MCO1 Clock Enable */
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     MCO1_CLK_ENABLE();
+ 1255              		.loc 1 915 5 view .LVU400
+ 1256              	.LBB5:
+ 1257              		.loc 1 915 5 view .LVU401
+ 1258              		.loc 1 915 5 view .LVU402
+ 1259 000a 204E     		ldr	r6, .L132
+ 1260 000c 336B     		ldr	r3, [r6, #48]
+ 1261 000e 43F00103 		orr	r3, r3, #1
+ 1262 0012 3363     		str	r3, [r6, #48]
+ARM GAS  /tmp/ccgleihc.s 			page 43
+
+
+ 1263              		.loc 1 915 5 view .LVU403
+ 1264 0014 336B     		ldr	r3, [r6, #48]
+ 1265 0016 03F00103 		and	r3, r3, #1
+ 1266 001a 0193     		str	r3, [sp, #4]
+ 1267              		.loc 1 915 5 view .LVU404
+ 1268 001c 019B     		ldr	r3, [sp, #4]
+ 1269              	.LBE5:
+ 1270              		.loc 1 915 5 view .LVU405
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Configure the MCO1 pin in alternate function mode */
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Pin = MCO1_PIN;
+ 1271              		.loc 1 918 5 view .LVU406
+ 1272              		.loc 1 918 25 is_stmt 0 view .LVU407
+ 1273 001e 4FF48073 		mov	r3, #256
+ 1274 0022 0393     		str	r3, [sp, #12]
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 1275              		.loc 1 919 5 is_stmt 1 view .LVU408
+ 1276              		.loc 1 919 26 is_stmt 0 view .LVU409
+ 1277 0024 0223     		movs	r3, #2
+ 1278 0026 0493     		str	r3, [sp, #16]
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+ 1279              		.loc 1 920 5 is_stmt 1 view .LVU410
+ 1280              		.loc 1 920 27 is_stmt 0 view .LVU411
+ 1281 0028 0323     		movs	r3, #3
+ 1282 002a 0693     		str	r3, [sp, #24]
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 1283              		.loc 1 921 5 is_stmt 1 view .LVU412
+ 1284              		.loc 1 921 26 is_stmt 0 view .LVU413
+ 1285 002c 0023     		movs	r3, #0
+ 1286 002e 0593     		str	r3, [sp, #20]
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+ 1287              		.loc 1 922 5 is_stmt 1 view .LVU414
+ 1288              		.loc 1 922 31 is_stmt 0 view .LVU415
+ 1289 0030 0793     		str	r3, [sp, #28]
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
+ 1290              		.loc 1 923 5 is_stmt 1 view .LVU416
+ 1291 0032 03A9     		add	r1, sp, #12
+ 1292              	.LVL91:
+ 1293              		.loc 1 923 5 is_stmt 0 view .LVU417
+ 1294 0034 1648     		ldr	r0, .L132+4
+ 1295              	.LVL92:
+ 1296              		.loc 1 923 5 view .LVU418
+ 1297 0036 FFF7FEFF 		bl	HAL_GPIO_Init
+ 1298              	.LVL93:
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+ 1299              		.loc 1 926 5 is_stmt 1 view .LVU419
+ 1300 003a B368     		ldr	r3, [r6, #8]
+ 1301 003c 23F0EC63 		bic	r3, r3, #123731968
+ 1302 0040 2543     		orrs	r5, r5, r4
+ 1303              	.LVL94:
+ 1304              		.loc 1 926 5 is_stmt 0 view .LVU420
+ 1305 0042 1D43     		orrs	r5, r5, r3
+ 1306 0044 B560     		str	r5, [r6, #8]
+ 1307              	.LVL95:
+ 1308              	.L128:
+ARM GAS  /tmp/ccgleihc.s 			page 44
+
+
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   else
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* MCO2 Clock Enable */
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     MCO2_CLK_ENABLE();
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Configure the MCO2 pin in alternate function mode */
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Pin = MCO2_PIN;
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 1309              		.loc 1 946 1 view .LVU421
+ 1310 0046 08B0     		add	sp, sp, #32
+ 1311              	.LCFI9:
+ 1312              		.cfi_remember_state
+ 1313              		.cfi_def_cfa_offset 16
+ 1314              		@ sp needed
+ 1315 0048 70BD     		pop	{r4, r5, r6, pc}
+ 1316              	.LVL96:
+ 1317              	.L129:
+ 1318              	.LCFI10:
+ 1319              		.cfi_restore_state
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1320              		.loc 1 930 5 is_stmt 1 view .LVU422
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1321              		.loc 1 933 5 view .LVU423
+ 1322              	.LBB6:
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1323              		.loc 1 933 5 view .LVU424
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1324              		.loc 1 933 5 view .LVU425
+ 1325 004a 104E     		ldr	r6, .L132
+ 1326 004c 336B     		ldr	r3, [r6, #48]
+ 1327 004e 43F00403 		orr	r3, r3, #4
+ 1328 0052 3363     		str	r3, [r6, #48]
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1329              		.loc 1 933 5 view .LVU426
+ 1330 0054 336B     		ldr	r3, [r6, #48]
+ 1331 0056 03F00403 		and	r3, r3, #4
+ 1332 005a 0293     		str	r3, [sp, #8]
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1333              		.loc 1 933 5 view .LVU427
+ 1334 005c 029B     		ldr	r3, [sp, #8]
+ 1335              	.LBE6:
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1336              		.loc 1 933 5 view .LVU428
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 1337              		.loc 1 936 5 view .LVU429
+ARM GAS  /tmp/ccgleihc.s 			page 45
+
+
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 1338              		.loc 1 936 25 is_stmt 0 view .LVU430
+ 1339 005e 4FF40073 		mov	r3, #512
+ 1340 0062 0393     		str	r3, [sp, #12]
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+ 1341              		.loc 1 937 5 is_stmt 1 view .LVU431
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+ 1342              		.loc 1 937 26 is_stmt 0 view .LVU432
+ 1343 0064 0223     		movs	r3, #2
+ 1344 0066 0493     		str	r3, [sp, #16]
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 1345              		.loc 1 938 5 is_stmt 1 view .LVU433
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 1346              		.loc 1 938 27 is_stmt 0 view .LVU434
+ 1347 0068 0323     		movs	r3, #3
+ 1348 006a 0693     		str	r3, [sp, #24]
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+ 1349              		.loc 1 939 5 is_stmt 1 view .LVU435
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+ 1350              		.loc 1 939 26 is_stmt 0 view .LVU436
+ 1351 006c 0023     		movs	r3, #0
+ 1352 006e 0593     		str	r3, [sp, #20]
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+ 1353              		.loc 1 940 5 is_stmt 1 view .LVU437
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+ 1354              		.loc 1 940 31 is_stmt 0 view .LVU438
+ 1355 0070 0793     		str	r3, [sp, #28]
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1356              		.loc 1 941 5 is_stmt 1 view .LVU439
+ 1357 0072 03A9     		add	r1, sp, #12
+ 1358              	.LVL97:
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1359              		.loc 1 941 5 is_stmt 0 view .LVU440
+ 1360 0074 0748     		ldr	r0, .L132+8
+ 1361              	.LVL98:
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1362              		.loc 1 941 5 view .LVU441
+ 1363 0076 FFF7FEFF 		bl	HAL_GPIO_Init
+ 1364              	.LVL99:
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 1365              		.loc 1 944 5 is_stmt 1 view .LVU442
+ 1366 007a B368     		ldr	r3, [r6, #8]
+ 1367 007c 23F07843 		bic	r3, r3, #-134217728
+ 1368 0080 44EAC504 		orr	r4, r4, r5, lsl #3
+ 1369              	.LVL100:
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 1370              		.loc 1 944 5 is_stmt 0 view .LVU443
+ 1371 0084 1C43     		orrs	r4, r4, r3
+ 1372 0086 B460     		str	r4, [r6, #8]
+ 1373              		.loc 1 946 1 view .LVU444
+ 1374 0088 DDE7     		b	.L128
+ 1375              	.L133:
+ 1376 008a 00BF     		.align	2
+ 1377              	.L132:
+ 1378 008c 00380240 		.word	1073887232
+ 1379 0090 00000240 		.word	1073872896
+ 1380 0094 00080240 		.word	1073874944
+ARM GAS  /tmp/ccgleihc.s 			page 46
+
+
+ 1381              		.cfi_endproc
+ 1382              	.LFE144:
+ 1384              		.section	.text.HAL_RCC_EnableCSS,"ax",%progbits
+ 1385              		.align	1
+ 1386              		.global	HAL_RCC_EnableCSS
+ 1387              		.syntax unified
+ 1388              		.thumb
+ 1389              		.thumb_func
+ 1390              		.fpu fpv5-d16
+ 1392              	HAL_RCC_EnableCSS:
+ 1393              	.LFB145:
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Enables the Clock Security System.
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         is automatically disabled and an interrupt is generated to inform the
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         software about the failure (Clock Security System Interrupt, CSSI),
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         allowing the MCU to perform rescue operations. The CSSI is linked to
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval None
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_EnableCSS(void)
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 1394              		.loc 1 958 1 is_stmt 1 view -0
+ 1395              		.cfi_startproc
+ 1396              		@ args = 0, pretend = 0, frame = 0
+ 1397              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1398              		@ link register save eliminated.
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   SET_BIT(RCC->CR, RCC_CR_CSSON);
+ 1399              		.loc 1 959 3 view .LVU446
+ 1400 0000 024A     		ldr	r2, .L135
+ 1401 0002 1368     		ldr	r3, [r2]
+ 1402 0004 43F40023 		orr	r3, r3, #524288
+ 1403 0008 1360     		str	r3, [r2]
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 1404              		.loc 1 960 1 is_stmt 0 view .LVU447
+ 1405 000a 7047     		bx	lr
+ 1406              	.L136:
+ 1407              		.align	2
+ 1408              	.L135:
+ 1409 000c 00380240 		.word	1073887232
+ 1410              		.cfi_endproc
+ 1411              	.LFE145:
+ 1413              		.section	.text.HAL_RCC_DisableCSS,"ax",%progbits
+ 1414              		.align	1
+ 1415              		.global	HAL_RCC_DisableCSS
+ 1416              		.syntax unified
+ 1417              		.thumb
+ 1418              		.thumb_func
+ 1419              		.fpu fpv5-d16
+ 1421              	HAL_RCC_DisableCSS:
+ 1422              	.LFB146:
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Disables the Clock Security System.
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval None
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+ARM GAS  /tmp/ccgleihc.s 			page 47
+
+
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_DisableCSS(void)
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 1423              		.loc 1 967 1 is_stmt 1 view -0
+ 1424              		.cfi_startproc
+ 1425              		@ args = 0, pretend = 0, frame = 0
+ 1426              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1427              		@ link register save eliminated.
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
+ 1428              		.loc 1 968 3 view .LVU449
+ 1429 0000 024A     		ldr	r2, .L138
+ 1430 0002 1368     		ldr	r3, [r2]
+ 1431 0004 23F40023 		bic	r3, r3, #524288
+ 1432 0008 1360     		str	r3, [r2]
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 1433              		.loc 1 969 1 is_stmt 0 view .LVU450
+ 1434 000a 7047     		bx	lr
+ 1435              	.L139:
+ 1436              		.align	2
+ 1437              	.L138:
+ 1438 000c 00380240 		.word	1073887232
+ 1439              		.cfi_endproc
+ 1440              	.LFE146:
+ 1442              		.global	__aeabi_uldivmod
+ 1443              		.section	.text.HAL_RCC_GetSysClockFreq,"ax",%progbits
+ 1444              		.align	1
+ 1445              		.global	HAL_RCC_GetSysClockFreq
+ 1446              		.syntax unified
+ 1447              		.thumb
+ 1448              		.thumb_func
+ 1449              		.fpu fpv5-d16
+ 1451              	HAL_RCC_GetSysClockFreq:
+ 1452              	.LFB147:
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Returns the SYSCLK frequency
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   The system frequency computed by this function is not the real
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         frequency in the chip. It is calculated based on the predefined
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         constant and the selected clock source:
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note     (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *               16 MHz) but the real value may vary depending on the variations
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *               in voltage and temperature.
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note     (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *                frequency of the crystal used. Otherwise, this function may
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *                have wrong result.
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   The result of this function could be not correct when using fractional
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         value for HSE crystal.
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   This function can be used by the user application to compute the
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         baudrate for the communication peripherals or configure other parameters.
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+ARM GAS  /tmp/ccgleihc.s 			page 48
+
+
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   Each time SYSCLK changes, this function must be called to update the
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorre
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval SYSCLK frequency
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetSysClockFreq(void)
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 1453              		.loc 1 1002 1 is_stmt 1 view -0
+ 1454              		.cfi_startproc
+ 1455              		@ args = 0, pretend = 0, frame = 0
+ 1456              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1457 0000 08B5     		push	{r3, lr}
+ 1458              	.LCFI11:
+ 1459              		.cfi_def_cfa_offset 8
+ 1460              		.cfi_offset 3, -8
+ 1461              		.cfi_offset 14, -4
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   uint32_t pllm = 0, pllvco = 0, pllp = 0;
+ 1462              		.loc 1 1003 3 view .LVU452
+ 1463              	.LVL101:
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   uint32_t sysclockfreq = 0;
+ 1464              		.loc 1 1004 3 view .LVU453
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get SYSCLK source -------------------------------------------------------*/
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   switch (RCC->CFGR & RCC_CFGR_SWS)
+ 1465              		.loc 1 1007 3 view .LVU454
+ 1466              		.loc 1 1007 14 is_stmt 0 view .LVU455
+ 1467 0002 254B     		ldr	r3, .L147
+ 1468 0004 9B68     		ldr	r3, [r3, #8]
+ 1469              		.loc 1 1007 21 view .LVU456
+ 1470 0006 03F00C03 		and	r3, r3, #12
+ 1471              		.loc 1 1007 3 view .LVU457
+ 1472 000a 042B     		cmp	r3, #4
+ 1473 000c 3FD0     		beq	.L144
+ 1474 000e 082B     		cmp	r3, #8
+ 1475 0010 3FD1     		bne	.L145
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       sysclockfreq = HSI_VALUE;
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       break;
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       sysclockfreq = HSE_VALUE;
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       break;
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock  source */
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       SYSCLK = PLL_VCO / PLLP */
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ 1476              		.loc 1 1023 7 is_stmt 1 view .LVU458
+ 1477              		.loc 1 1023 17 is_stmt 0 view .LVU459
+ 1478 0012 214B     		ldr	r3, .L147
+ 1479 0014 5A68     		ldr	r2, [r3, #4]
+ 1480              		.loc 1 1023 12 view .LVU460
+ARM GAS  /tmp/ccgleihc.s 			page 49
+
+
+ 1481 0016 02F03F02 		and	r2, r2, #63
+ 1482              	.LVL102:
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
+ 1483              		.loc 1 1024 7 is_stmt 1 view .LVU461
+ 1484              		.loc 1 1024 11 is_stmt 0 view .LVU462
+ 1485 001a 5B68     		ldr	r3, [r3, #4]
+ 1486              		.loc 1 1024 10 view .LVU463
+ 1487 001c 13F4800F 		tst	r3, #4194304
+ 1488 0020 12D0     		beq	.L142
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* HSE used as PLL clock source */
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) 
+ 1489              		.loc 1 1027 9 is_stmt 1 view .LVU464
+ 1490              		.loc 1 1027 70 is_stmt 0 view .LVU465
+ 1491 0022 1D4B     		ldr	r3, .L147
+ 1492 0024 5968     		ldr	r1, [r3, #4]
+ 1493              		.loc 1 1027 55 view .LVU466
+ 1494 0026 C1F38811 		ubfx	r1, r1, #6, #9
+ 1495              		.loc 1 1027 52 view .LVU467
+ 1496 002a 1C48     		ldr	r0, .L147+4
+ 1497              		.loc 1 1027 128 view .LVU468
+ 1498 002c 0023     		movs	r3, #0
+ 1499 002e A1FB0001 		umull	r0, r1, r1, r0
+ 1500 0032 FFF7FEFF 		bl	__aeabi_uldivmod
+ 1501              	.LVL103:
+ 1502              	.L143:
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       else
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         /* HSI used as PLL clock source */
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****         pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) 
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
+ 1503              		.loc 1 1034 7 is_stmt 1 view .LVU469
+ 1504              		.loc 1 1034 21 is_stmt 0 view .LVU470
+ 1505 0036 184B     		ldr	r3, .L147
+ 1506 0038 5B68     		ldr	r3, [r3, #4]
+ 1507              		.loc 1 1034 51 view .LVU471
+ 1508 003a C3F30143 		ubfx	r3, r3, #16, #2
+ 1509              		.loc 1 1034 76 view .LVU472
+ 1510 003e 0133     		adds	r3, r3, #1
+ 1511              		.loc 1 1034 12 view .LVU473
+ 1512 0040 5B00     		lsls	r3, r3, #1
+ 1513              	.LVL104:
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       sysclockfreq = pllvco / pllp;
+ 1514              		.loc 1 1036 7 is_stmt 1 view .LVU474
+ 1515              		.loc 1 1036 20 is_stmt 0 view .LVU475
+ 1516 0042 B0FBF3F0 		udiv	r0, r0, r3
+ 1517              	.LVL105:
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       break;
+ 1518              		.loc 1 1037 7 is_stmt 1 view .LVU476
+ 1519 0046 25E0     		b	.L140
+ 1520              	.LVL106:
+ 1521              	.L142:
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1522              		.loc 1 1032 9 view .LVU477
+ARM GAS  /tmp/ccgleihc.s 			page 50
+
+
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1523              		.loc 1 1032 70 is_stmt 0 view .LVU478
+ 1524 0048 134B     		ldr	r3, .L147
+ 1525 004a 5968     		ldr	r1, [r3, #4]
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1526              		.loc 1 1032 55 view .LVU479
+ 1527 004c C1F3881C 		ubfx	ip, r1, #6, #9
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1528              		.loc 1 1032 52 view .LVU480
+ 1529 0050 4FEA4C11 		lsl	r1, ip, #5
+ 1530 0054 B1EB0C00 		subs	r0, r1, ip
+ 1531 0058 6EEB0E0E 		sbc	lr, lr, lr
+ 1532 005c 4FEA8E13 		lsl	r3, lr, #6
+ 1533 0060 43EA9063 		orr	r3, r3, r0, lsr #26
+ 1534 0064 8101     		lsls	r1, r0, #6
+ 1535 0066 091A     		subs	r1, r1, r0
+ 1536 0068 63EB0E03 		sbc	r3, r3, lr
+ 1537 006c DB00     		lsls	r3, r3, #3
+ 1538 006e 43EA5173 		orr	r3, r3, r1, lsr #29
+ 1539 0072 C900     		lsls	r1, r1, #3
+ 1540 0074 11EB0C0C 		adds	ip, r1, ip
+ 1541 0078 43F10003 		adc	r3, r3, #0
+ 1542 007c 9902     		lsls	r1, r3, #10
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1543              		.loc 1 1032 128 view .LVU481
+ 1544 007e 0023     		movs	r3, #0
+ 1545 0080 4FEA8C20 		lsl	r0, ip, #10
+ 1546 0084 41EA9C51 		orr	r1, r1, ip, lsr #22
+ 1547 0088 FFF7FEFF 		bl	__aeabi_uldivmod
+ 1548              	.LVL107:
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1549              		.loc 1 1032 128 view .LVU482
+ 1550 008c D3E7     		b	.L143
+ 1551              	.LVL108:
+ 1552              	.L144:
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       break;
+ 1553              		.loc 1 1016 20 view .LVU483
+ 1554 008e 0348     		ldr	r0, .L147+4
+ 1555 0090 00E0     		b	.L140
+ 1556              	.L145:
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1557              		.loc 1 1007 3 view .LVU484
+ 1558 0092 0348     		ldr	r0, .L147+8
+ 1559              	.LVL109:
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     default:
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       sysclockfreq = HSI_VALUE;
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       break;
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   return sysclockfreq;
+ 1560              		.loc 1 1045 3 is_stmt 1 view .LVU485
+ 1561              	.L140:
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 1562              		.loc 1 1046 1 is_stmt 0 view .LVU486
+ 1563 0094 08BD     		pop	{r3, pc}
+ARM GAS  /tmp/ccgleihc.s 			page 51
+
+
+ 1564              	.L148:
+ 1565 0096 00BF     		.align	2
+ 1566              	.L147:
+ 1567 0098 00380240 		.word	1073887232
+ 1568 009c 40787D01 		.word	25000000
+ 1569 00a0 0024F400 		.word	16000000
+ 1570              		.cfi_endproc
+ 1571              	.LFE147:
+ 1573              		.section	.text.HAL_RCC_ClockConfig,"ax",%progbits
+ 1574              		.align	1
+ 1575              		.global	HAL_RCC_ClockConfig
+ 1576              		.syntax unified
+ 1577              		.thumb
+ 1578              		.thumb_func
+ 1579              		.fpu fpv5-d16
+ 1581              	HAL_RCC_ClockConfig:
+ 1582              	.LVL110:
+ 1583              	.LFB143:
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   uint32_t tickstart = 0;
+ 1584              		.loc 1 723 1 is_stmt 1 view -0
+ 1585              		.cfi_startproc
+ 1586              		@ args = 0, pretend = 0, frame = 0
+ 1587              		@ frame_needed = 0, uses_anonymous_args = 0
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1588              		.loc 1 724 3 view .LVU488
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1589              		.loc 1 727 3 view .LVU489
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1590              		.loc 1 727 6 is_stmt 0 view .LVU490
+ 1591 0000 0028     		cmp	r0, #0
+ 1592 0002 00F0A080 		beq	.L164
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   uint32_t tickstart = 0;
+ 1593              		.loc 1 723 1 view .LVU491
+ 1594 0006 70B5     		push	{r4, r5, r6, lr}
+ 1595              	.LCFI12:
+ 1596              		.cfi_def_cfa_offset 16
+ 1597              		.cfi_offset 4, -16
+ 1598              		.cfi_offset 5, -12
+ 1599              		.cfi_offset 6, -8
+ 1600              		.cfi_offset 14, -4
+ 1601 0008 0D46     		mov	r5, r1
+ 1602 000a 0446     		mov	r4, r0
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   assert_param(IS_FLASH_LATENCY(FLatency));
+ 1603              		.loc 1 733 3 is_stmt 1 view .LVU492
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1604              		.loc 1 734 3 view .LVU493
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1605              		.loc 1 741 3 view .LVU494
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1606              		.loc 1 741 18 is_stmt 0 view .LVU495
+ 1607 000c 524B     		ldr	r3, .L177
+ 1608 000e 1B68     		ldr	r3, [r3]
+ 1609 0010 03F00F03 		and	r3, r3, #15
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1610              		.loc 1 741 6 view .LVU496
+ 1611 0014 8B42     		cmp	r3, r1
+ 1612 0016 0BD2     		bcs	.L151
+ARM GAS  /tmp/ccgleihc.s 			page 52
+
+
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1613              		.loc 1 744 5 is_stmt 1 view .LVU497
+ 1614 0018 4F4A     		ldr	r2, .L177
+ 1615 001a 1368     		ldr	r3, [r2]
+ 1616 001c 23F00F03 		bic	r3, r3, #15
+ 1617 0020 0B43     		orrs	r3, r3, r1
+ 1618 0022 1360     		str	r3, [r2]
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1619              		.loc 1 748 5 view .LVU498
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1620              		.loc 1 748 9 is_stmt 0 view .LVU499
+ 1621 0024 1368     		ldr	r3, [r2]
+ 1622 0026 03F00F03 		and	r3, r3, #15
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1623              		.loc 1 748 8 view .LVU500
+ 1624 002a 8B42     		cmp	r3, r1
+ 1625 002c 40F08D80 		bne	.L165
+ 1626              	.L151:
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1627              		.loc 1 755 3 is_stmt 1 view .LVU501
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1628              		.loc 1 755 26 is_stmt 0 view .LVU502
+ 1629 0030 2368     		ldr	r3, [r4]
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1630              		.loc 1 755 6 view .LVU503
+ 1631 0032 13F0020F 		tst	r3, #2
+ 1632 0036 17D0     		beq	.L152
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1633              		.loc 1 759 5 is_stmt 1 view .LVU504
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1634              		.loc 1 759 8 is_stmt 0 view .LVU505
+ 1635 0038 13F0040F 		tst	r3, #4
+ 1636 003c 04D0     		beq	.L153
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 1637              		.loc 1 761 7 is_stmt 1 view .LVU506
+ 1638 003e 474A     		ldr	r2, .L177+4
+ 1639 0040 9368     		ldr	r3, [r2, #8]
+ 1640 0042 43F4E053 		orr	r3, r3, #7168
+ 1641 0046 9360     		str	r3, [r2, #8]
+ 1642              	.L153:
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1643              		.loc 1 764 5 view .LVU507
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1644              		.loc 1 764 28 is_stmt 0 view .LVU508
+ 1645 0048 2368     		ldr	r3, [r4]
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1646              		.loc 1 764 8 view .LVU509
+ 1647 004a 13F0080F 		tst	r3, #8
+ 1648 004e 04D0     		beq	.L154
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 1649              		.loc 1 766 7 is_stmt 1 view .LVU510
+ 1650 0050 424A     		ldr	r2, .L177+4
+ 1651 0052 9368     		ldr	r3, [r2, #8]
+ 1652 0054 43F46043 		orr	r3, r3, #57344
+ 1653 0058 9360     		str	r3, [r2, #8]
+ 1654              	.L154:
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ARM GAS  /tmp/ccgleihc.s 			page 53
+
+
+ 1655              		.loc 1 770 5 view .LVU511
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 1656              		.loc 1 771 5 view .LVU512
+ 1657 005a 404A     		ldr	r2, .L177+4
+ 1658 005c 9368     		ldr	r3, [r2, #8]
+ 1659 005e 23F0F003 		bic	r3, r3, #240
+ 1660 0062 A168     		ldr	r1, [r4, #8]
+ 1661              	.LVL111:
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 1662              		.loc 1 771 5 is_stmt 0 view .LVU513
+ 1663 0064 0B43     		orrs	r3, r3, r1
+ 1664 0066 9360     		str	r3, [r2, #8]
+ 1665              	.L152:
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1666              		.loc 1 775 3 is_stmt 1 view .LVU514
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1667              		.loc 1 775 26 is_stmt 0 view .LVU515
+ 1668 0068 2368     		ldr	r3, [r4]
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1669              		.loc 1 775 6 view .LVU516
+ 1670 006a 13F0010F 		tst	r3, #1
+ 1671 006e 31D0     		beq	.L155
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1672              		.loc 1 777 5 is_stmt 1 view .LVU517
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1673              		.loc 1 780 5 view .LVU518
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1674              		.loc 1 780 26 is_stmt 0 view .LVU519
+ 1675 0070 6368     		ldr	r3, [r4, #4]
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1676              		.loc 1 780 8 view .LVU520
+ 1677 0072 012B     		cmp	r3, #1
+ 1678 0074 20D0     		beq	.L175
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1679              		.loc 1 789 10 is_stmt 1 view .LVU521
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1680              		.loc 1 789 13 is_stmt 0 view .LVU522
+ 1681 0076 022B     		cmp	r3, #2
+ 1682 0078 25D0     		beq	.L176
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1683              		.loc 1 801 7 is_stmt 1 view .LVU523
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1684              		.loc 1 801 11 is_stmt 0 view .LVU524
+ 1685 007a 384A     		ldr	r2, .L177+4
+ 1686 007c 1268     		ldr	r2, [r2]
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1687              		.loc 1 801 10 view .LVU525
+ 1688 007e 12F0020F 		tst	r2, #2
+ 1689 0082 64D0     		beq	.L168
+ 1690              	.L157:
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1691              		.loc 1 807 5 is_stmt 1 view .LVU526
+ 1692 0084 3549     		ldr	r1, .L177+4
+ 1693 0086 8A68     		ldr	r2, [r1, #8]
+ 1694 0088 22F00302 		bic	r2, r2, #3
+ 1695 008c 1343     		orrs	r3, r3, r2
+ 1696 008e 8B60     		str	r3, [r1, #8]
+ARM GAS  /tmp/ccgleihc.s 			page 54
+
+
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1697              		.loc 1 810 5 view .LVU527
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1698              		.loc 1 810 17 is_stmt 0 view .LVU528
+ 1699 0090 FFF7FEFF 		bl	HAL_GetTick
+ 1700              	.LVL112:
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1701              		.loc 1 810 17 view .LVU529
+ 1702 0094 0646     		mov	r6, r0
+ 1703              	.LVL113:
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1704              		.loc 1 812 5 is_stmt 1 view .LVU530
+ 1705              	.L159:
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1706              		.loc 1 812 11 view .LVU531
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1707              		.loc 1 812 12 is_stmt 0 view .LVU532
+ 1708 0096 314B     		ldr	r3, .L177+4
+ 1709 0098 9B68     		ldr	r3, [r3, #8]
+ 1710 009a 03F00C03 		and	r3, r3, #12
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1711              		.loc 1 812 63 view .LVU533
+ 1712 009e 6268     		ldr	r2, [r4, #4]
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1713              		.loc 1 812 11 view .LVU534
+ 1714 00a0 B3EB820F 		cmp	r3, r2, lsl #2
+ 1715 00a4 16D0     		beq	.L155
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1716              		.loc 1 814 7 is_stmt 1 view .LVU535
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1717              		.loc 1 814 12 is_stmt 0 view .LVU536
+ 1718 00a6 FFF7FEFF 		bl	HAL_GetTick
+ 1719              	.LVL114:
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1720              		.loc 1 814 26 view .LVU537
+ 1721 00aa 801B     		subs	r0, r0, r6
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1722              		.loc 1 814 10 view .LVU538
+ 1723 00ac 41F28833 		movw	r3, #5000
+ 1724 00b0 9842     		cmp	r0, r3
+ 1725 00b2 F0D9     		bls	.L159
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1726              		.loc 1 816 16 view .LVU539
+ 1727 00b4 0320     		movs	r0, #3
+ 1728 00b6 45E0     		b	.L150
+ 1729              	.LVL115:
+ 1730              	.L175:
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1731              		.loc 1 783 7 is_stmt 1 view .LVU540
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1732              		.loc 1 783 11 is_stmt 0 view .LVU541
+ 1733 00b8 284A     		ldr	r2, .L177+4
+ 1734 00ba 1268     		ldr	r2, [r2]
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1735              		.loc 1 783 10 view .LVU542
+ 1736 00bc 12F4003F 		tst	r2, #131072
+ 1737 00c0 E0D1     		bne	.L157
+ARM GAS  /tmp/ccgleihc.s 			page 55
+
+
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1738              		.loc 1 785 16 view .LVU543
+ 1739 00c2 0120     		movs	r0, #1
+ 1740              	.LVL116:
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1741              		.loc 1 785 16 view .LVU544
+ 1742 00c4 3EE0     		b	.L150
+ 1743              	.LVL117:
+ 1744              	.L176:
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1745              		.loc 1 792 7 is_stmt 1 view .LVU545
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1746              		.loc 1 792 11 is_stmt 0 view .LVU546
+ 1747 00c6 254A     		ldr	r2, .L177+4
+ 1748 00c8 1268     		ldr	r2, [r2]
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       {
+ 1749              		.loc 1 792 10 view .LVU547
+ 1750 00ca 12F0007F 		tst	r2, #33554432
+ 1751 00ce D9D1     		bne	.L157
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1752              		.loc 1 794 16 view .LVU548
+ 1753 00d0 0120     		movs	r0, #1
+ 1754              	.LVL118:
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1755              		.loc 1 794 16 view .LVU549
+ 1756 00d2 37E0     		b	.L150
+ 1757              	.LVL119:
+ 1758              	.L155:
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1759              		.loc 1 822 3 is_stmt 1 view .LVU550
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1760              		.loc 1 822 18 is_stmt 0 view .LVU551
+ 1761 00d4 204B     		ldr	r3, .L177
+ 1762 00d6 1B68     		ldr	r3, [r3]
+ 1763 00d8 03F00F03 		and	r3, r3, #15
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1764              		.loc 1 822 6 view .LVU552
+ 1765 00dc AB42     		cmp	r3, r5
+ 1766 00de 0AD9     		bls	.L161
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1767              		.loc 1 825 5 is_stmt 1 view .LVU553
+ 1768 00e0 1D4A     		ldr	r2, .L177
+ 1769 00e2 1368     		ldr	r3, [r2]
+ 1770 00e4 23F00F03 		bic	r3, r3, #15
+ 1771 00e8 2B43     		orrs	r3, r3, r5
+ 1772 00ea 1360     		str	r3, [r2]
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1773              		.loc 1 829 5 view .LVU554
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1774              		.loc 1 829 9 is_stmt 0 view .LVU555
+ 1775 00ec 1368     		ldr	r3, [r2]
+ 1776 00ee 03F00F03 		and	r3, r3, #15
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     {
+ 1777              		.loc 1 829 8 view .LVU556
+ 1778 00f2 AB42     		cmp	r3, r5
+ 1779 00f4 2DD1     		bne	.L170
+ 1780              	.L161:
+ARM GAS  /tmp/ccgleihc.s 			page 56
+
+
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1781              		.loc 1 836 3 is_stmt 1 view .LVU557
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1782              		.loc 1 836 26 is_stmt 0 view .LVU558
+ 1783 00f6 2368     		ldr	r3, [r4]
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1784              		.loc 1 836 6 view .LVU559
+ 1785 00f8 13F0040F 		tst	r3, #4
+ 1786 00fc 06D0     		beq	.L162
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ 1787              		.loc 1 838 5 is_stmt 1 view .LVU560
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 1788              		.loc 1 839 5 view .LVU561
+ 1789 00fe 174A     		ldr	r2, .L177+4
+ 1790 0100 9368     		ldr	r3, [r2, #8]
+ 1791 0102 23F4E053 		bic	r3, r3, #7168
+ 1792 0106 E168     		ldr	r1, [r4, #12]
+ 1793 0108 0B43     		orrs	r3, r3, r1
+ 1794 010a 9360     		str	r3, [r2, #8]
+ 1795              	.L162:
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1796              		.loc 1 843 3 view .LVU562
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1797              		.loc 1 843 26 is_stmt 0 view .LVU563
+ 1798 010c 2368     		ldr	r3, [r4]
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 1799              		.loc 1 843 6 view .LVU564
+ 1800 010e 13F0080F 		tst	r3, #8
+ 1801 0112 07D0     		beq	.L163
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+ 1802              		.loc 1 845 5 is_stmt 1 view .LVU565
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 1803              		.loc 1 846 5 view .LVU566
+ 1804 0114 114A     		ldr	r2, .L177+4
+ 1805 0116 9368     		ldr	r3, [r2, #8]
+ 1806 0118 23F46043 		bic	r3, r3, #57344
+ 1807 011c 2169     		ldr	r1, [r4, #16]
+ 1808 011e 43EAC103 		orr	r3, r3, r1, lsl #3
+ 1809 0122 9360     		str	r3, [r2, #8]
+ 1810              	.L163:
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1811              		.loc 1 850 3 view .LVU567
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1812              		.loc 1 850 21 is_stmt 0 view .LVU568
+ 1813 0124 FFF7FEFF 		bl	HAL_RCC_GetSysClockFreq
+ 1814              	.LVL120:
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1815              		.loc 1 850 68 view .LVU569
+ 1816 0128 0C4B     		ldr	r3, .L177+4
+ 1817 012a 9B68     		ldr	r3, [r3, #8]
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1818              		.loc 1 850 92 view .LVU570
+ 1819 012c C3F30313 		ubfx	r3, r3, #4, #4
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1820              		.loc 1 850 63 view .LVU571
+ 1821 0130 0B4A     		ldr	r2, .L177+8
+ 1822 0132 D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
+ARM GAS  /tmp/ccgleihc.s 			page 57
+
+
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1823              		.loc 1 850 47 view .LVU572
+ 1824 0134 D840     		lsrs	r0, r0, r3
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1825              		.loc 1 850 19 view .LVU573
+ 1826 0136 0B4B     		ldr	r3, .L177+12
+ 1827 0138 1860     		str	r0, [r3]
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1828              		.loc 1 853 3 is_stmt 1 view .LVU574
+ 1829 013a 0B4B     		ldr	r3, .L177+16
+ 1830 013c 1868     		ldr	r0, [r3]
+ 1831 013e FFF7FEFF 		bl	HAL_InitTick
+ 1832              	.LVL121:
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 1833              		.loc 1 855 3 view .LVU575
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 1834              		.loc 1 855 10 is_stmt 0 view .LVU576
+ 1835 0142 0020     		movs	r0, #0
+ 1836              	.L150:
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1837              		.loc 1 856 1 view .LVU577
+ 1838 0144 70BD     		pop	{r4, r5, r6, pc}
+ 1839              	.LVL122:
+ 1840              	.L164:
+ 1841              	.LCFI13:
+ 1842              		.cfi_def_cfa_offset 0
+ 1843              		.cfi_restore 4
+ 1844              		.cfi_restore 5
+ 1845              		.cfi_restore 6
+ 1846              		.cfi_restore 14
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 1847              		.loc 1 729 12 view .LVU578
+ 1848 0146 0120     		movs	r0, #1
+ 1849              	.LVL123:
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 1850              		.loc 1 856 1 view .LVU579
+ 1851 0148 7047     		bx	lr
+ 1852              	.LVL124:
+ 1853              	.L165:
+ 1854              	.LCFI14:
+ 1855              		.cfi_def_cfa_offset 16
+ 1856              		.cfi_offset 4, -16
+ 1857              		.cfi_offset 5, -12
+ 1858              		.cfi_offset 6, -8
+ 1859              		.cfi_offset 14, -4
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 1860              		.loc 1 750 14 view .LVU580
+ 1861 014a 0120     		movs	r0, #1
+ 1862              	.LVL125:
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 1863              		.loc 1 750 14 view .LVU581
+ 1864 014c FAE7     		b	.L150
+ 1865              	.LVL126:
+ 1866              	.L168:
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1867              		.loc 1 803 16 view .LVU582
+ 1868 014e 0120     		movs	r0, #1
+ARM GAS  /tmp/ccgleihc.s 			page 58
+
+
+ 1869              	.LVL127:
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****       }
+ 1870              		.loc 1 803 16 view .LVU583
+ 1871 0150 F8E7     		b	.L150
+ 1872              	.LVL128:
+ 1873              	.L170:
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     }
+ 1874              		.loc 1 831 14 view .LVU584
+ 1875 0152 0120     		movs	r0, #1
+ 1876 0154 F6E7     		b	.L150
+ 1877              	.L178:
+ 1878 0156 00BF     		.align	2
+ 1879              	.L177:
+ 1880 0158 003C0240 		.word	1073888256
+ 1881 015c 00380240 		.word	1073887232
+ 1882 0160 00000000 		.word	AHBPrescTable
+ 1883 0164 00000000 		.word	SystemCoreClock
+ 1884 0168 00000000 		.word	uwTickPrio
+ 1885              		.cfi_endproc
+ 1886              	.LFE143:
+ 1888              		.section	.text.HAL_RCC_GetHCLKFreq,"ax",%progbits
+ 1889              		.align	1
+ 1890              		.global	HAL_RCC_GetHCLKFreq
+ 1891              		.syntax unified
+ 1892              		.thumb
+ 1893              		.thumb_func
+ 1894              		.fpu fpv5-d16
+ 1896              	HAL_RCC_GetHCLKFreq:
+ 1897              	.LFB148:
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Returns the HCLK frequency
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   Each time HCLK changes, this function must be called to update the
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval HCLK frequency
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetHCLKFreq(void)
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 1898              		.loc 1 1056 1 is_stmt 1 view -0
+ 1899              		.cfi_startproc
+ 1900              		@ args = 0, pretend = 0, frame = 0
+ 1901              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1902              		@ link register save eliminated.
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   return SystemCoreClock;
+ 1903              		.loc 1 1057 3 view .LVU586
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 1904              		.loc 1 1058 1 is_stmt 0 view .LVU587
+ 1905 0000 014B     		ldr	r3, .L180
+ 1906 0002 1868     		ldr	r0, [r3]
+ 1907 0004 7047     		bx	lr
+ 1908              	.L181:
+ 1909 0006 00BF     		.align	2
+ 1910              	.L180:
+ 1911 0008 00000000 		.word	SystemCoreClock
+ 1912              		.cfi_endproc
+ 1913              	.LFE148:
+ARM GAS  /tmp/ccgleihc.s 			page 59
+
+
+ 1915              		.section	.text.HAL_RCC_GetPCLK1Freq,"ax",%progbits
+ 1916              		.align	1
+ 1917              		.global	HAL_RCC_GetPCLK1Freq
+ 1918              		.syntax unified
+ 1919              		.thumb
+ 1920              		.thumb_func
+ 1921              		.fpu fpv5-d16
+ 1923              	HAL_RCC_GetPCLK1Freq:
+ 1924              	.LFB149:
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Returns the PCLK1 frequency
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   Each time PCLK1 changes, this function must be called to update the
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrec
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval PCLK1 frequency
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK1Freq(void)
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 1925              		.loc 1 1067 1 is_stmt 1 view -0
+ 1926              		.cfi_startproc
+ 1927              		@ args = 0, pretend = 0, frame = 0
+ 1928              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1929 0000 08B5     		push	{r3, lr}
+ 1930              	.LCFI15:
+ 1931              		.cfi_def_cfa_offset 8
+ 1932              		.cfi_offset 3, -8
+ 1933              		.cfi_offset 14, -4
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos
+ 1934              		.loc 1 1069 3 view .LVU589
+ 1935              		.loc 1 1069 11 is_stmt 0 view .LVU590
+ 1936 0002 FFF7FEFF 		bl	HAL_RCC_GetHCLKFreq
+ 1937              	.LVL129:
+ 1938              		.loc 1 1069 54 view .LVU591
+ 1939 0006 044B     		ldr	r3, .L184
+ 1940 0008 9B68     		ldr	r3, [r3, #8]
+ 1941              		.loc 1 1069 79 view .LVU592
+ 1942 000a C3F38223 		ubfx	r3, r3, #10, #3
+ 1943              		.loc 1 1069 49 view .LVU593
+ 1944 000e 034A     		ldr	r2, .L184+4
+ 1945 0010 D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 1946              		.loc 1 1070 1 view .LVU594
+ 1947 0012 D840     		lsrs	r0, r0, r3
+ 1948 0014 08BD     		pop	{r3, pc}
+ 1949              	.L185:
+ 1950 0016 00BF     		.align	2
+ 1951              	.L184:
+ 1952 0018 00380240 		.word	1073887232
+ 1953 001c 00000000 		.word	APBPrescTable
+ 1954              		.cfi_endproc
+ 1955              	.LFE149:
+ 1957              		.section	.text.HAL_RCC_GetPCLK2Freq,"ax",%progbits
+ 1958              		.align	1
+ 1959              		.global	HAL_RCC_GetPCLK2Freq
+ 1960              		.syntax unified
+ 1961              		.thumb
+ARM GAS  /tmp/ccgleihc.s 			page 60
+
+
+ 1962              		.thumb_func
+ 1963              		.fpu fpv5-d16
+ 1965              	HAL_RCC_GetPCLK2Freq:
+ 1966              	.LFB150:
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Returns the PCLK2 frequency
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note   Each time PCLK2 changes, this function must be called to update the
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrec
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval PCLK2 frequency
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK2Freq(void)
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 1967              		.loc 1 1079 1 is_stmt 1 view -0
+ 1968              		.cfi_startproc
+ 1969              		@ args = 0, pretend = 0, frame = 0
+ 1970              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1971 0000 08B5     		push	{r3, lr}
+ 1972              	.LCFI16:
+ 1973              		.cfi_def_cfa_offset 8
+ 1974              		.cfi_offset 3, -8
+ 1975              		.cfi_offset 14, -4
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos
+ 1976              		.loc 1 1081 3 view .LVU596
+ 1977              		.loc 1 1081 11 is_stmt 0 view .LVU597
+ 1978 0002 FFF7FEFF 		bl	HAL_RCC_GetHCLKFreq
+ 1979              	.LVL130:
+ 1980              		.loc 1 1081 54 view .LVU598
+ 1981 0006 044B     		ldr	r3, .L188
+ 1982 0008 9B68     		ldr	r3, [r3, #8]
+ 1983              		.loc 1 1081 79 view .LVU599
+ 1984 000a C3F34233 		ubfx	r3, r3, #13, #3
+ 1985              		.loc 1 1081 49 view .LVU600
+ 1986 000e 034A     		ldr	r2, .L188+4
+ 1987 0010 D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 1988              		.loc 1 1082 1 view .LVU601
+ 1989 0012 D840     		lsrs	r0, r0, r3
+ 1990 0014 08BD     		pop	{r3, pc}
+ 1991              	.L189:
+ 1992 0016 00BF     		.align	2
+ 1993              	.L188:
+ 1994 0018 00380240 		.word	1073887232
+ 1995 001c 00000000 		.word	APBPrescTable
+ 1996              		.cfi_endproc
+ 1997              	.LFE150:
+ 1999              		.section	.text.HAL_RCC_GetOscConfig,"ax",%progbits
+ 2000              		.align	1
+ 2001              		.global	HAL_RCC_GetOscConfig
+ 2002              		.syntax unified
+ 2003              		.thumb
+ 2004              		.thumb_func
+ 2005              		.fpu fpv5-d16
+ 2007              	HAL_RCC_GetOscConfig:
+ 2008              	.LVL131:
+ 2009              	.LFB151:
+ARM GAS  /tmp/ccgleihc.s 			page 61
+
+
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Configures the RCC_OscInitStruct according to the internal
+1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * RCC configuration registers.
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * will be configured.
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval None
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 2010              		.loc 1 1092 1 is_stmt 1 view -0
+ 2011              		.cfi_startproc
+ 2012              		@ args = 0, pretend = 0, frame = 0
+ 2013              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2014              		@ link register save eliminated.
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Set all possible values for the Oscillator type parameter ---------------*/
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLA
+ 2015              		.loc 1 1094 3 view .LVU603
+ 2016              		.loc 1 1094 37 is_stmt 0 view .LVU604
+ 2017 0000 0F23     		movs	r3, #15
+ 2018 0002 0360     		str	r3, [r0]
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get the HSE configuration -----------------------------------------------*/
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ 2019              		.loc 1 1097 3 is_stmt 1 view .LVU605
+ 2020              		.loc 1 1097 11 is_stmt 0 view .LVU606
+ 2021 0004 354B     		ldr	r3, .L203
+ 2022 0006 1B68     		ldr	r3, [r3]
+ 2023              		.loc 1 1097 6 view .LVU607
+ 2024 0008 13F4802F 		tst	r3, #262144
+ 2025 000c 46D0     		beq	.L191
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ 2026              		.loc 1 1099 5 is_stmt 1 view .LVU608
+ 2027              		.loc 1 1099 33 is_stmt 0 view .LVU609
+ 2028 000e 4FF4A023 		mov	r3, #327680
+ 2029 0012 4360     		str	r3, [r0, #4]
+ 2030              	.L192:
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   else
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get the HSI configuration -----------------------------------------------*/
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
+ 2031              		.loc 1 1111 3 is_stmt 1 view .LVU610
+ 2032              		.loc 1 1111 11 is_stmt 0 view .LVU611
+ 2033 0014 314B     		ldr	r3, .L203
+ 2034 0016 1B68     		ldr	r3, [r3]
+ 2035              		.loc 1 1111 6 view .LVU612
+ 2036 0018 13F0010F 		tst	r3, #1
+ 2037 001c 4AD0     		beq	.L194
+ARM GAS  /tmp/ccgleihc.s 			page 62
+
+
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ 2038              		.loc 1 1113 5 is_stmt 1 view .LVU613
+ 2039              		.loc 1 1113 33 is_stmt 0 view .LVU614
+ 2040 001e 0123     		movs	r3, #1
+ 2041 0020 C360     		str	r3, [r0, #12]
+ 2042              	.L195:
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   else
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_
+ 2043              		.loc 1 1120 3 is_stmt 1 view .LVU615
+ 2044              		.loc 1 1120 59 is_stmt 0 view .LVU616
+ 2045 0022 2E4A     		ldr	r2, .L203
+ 2046 0024 1368     		ldr	r3, [r2]
+ 2047              		.loc 1 1120 44 view .LVU617
+ 2048 0026 C3F3C403 		ubfx	r3, r3, #3, #5
+ 2049              		.loc 1 1120 42 view .LVU618
+ 2050 002a 0361     		str	r3, [r0, #16]
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get the LSE configuration -----------------------------------------------*/
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ 2051              		.loc 1 1123 3 is_stmt 1 view .LVU619
+ 2052              		.loc 1 1123 11 is_stmt 0 view .LVU620
+ 2053 002c 136F     		ldr	r3, [r2, #112]
+ 2054              		.loc 1 1123 6 view .LVU621
+ 2055 002e 13F0040F 		tst	r3, #4
+ 2056 0032 42D0     		beq	.L196
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ 2057              		.loc 1 1125 5 is_stmt 1 view .LVU622
+ 2058              		.loc 1 1125 33 is_stmt 0 view .LVU623
+ 2059 0034 0523     		movs	r3, #5
+ 2060 0036 8360     		str	r3, [r0, #8]
+ 2061              	.L197:
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   else
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get the LSI configuration -----------------------------------------------*/
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
+ 2062              		.loc 1 1137 3 is_stmt 1 view .LVU624
+ 2063              		.loc 1 1137 11 is_stmt 0 view .LVU625
+ 2064 0038 284B     		ldr	r3, .L203
+ 2065 003a 5B6F     		ldr	r3, [r3, #116]
+ 2066              		.loc 1 1137 6 view .LVU626
+ 2067 003c 13F0010F 		tst	r3, #1
+ 2068 0040 46D0     		beq	.L199
+ARM GAS  /tmp/ccgleihc.s 			page 63
+
+
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ 2069              		.loc 1 1139 5 is_stmt 1 view .LVU627
+ 2070              		.loc 1 1139 33 is_stmt 0 view .LVU628
+ 2071 0042 0123     		movs	r3, #1
+ 2072 0044 4361     		str	r3, [r0, #20]
+ 2073              	.L200:
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   else
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get the PLL configuration -----------------------------------------------*/
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
+ 2074              		.loc 1 1147 3 is_stmt 1 view .LVU629
+ 2075              		.loc 1 1147 11 is_stmt 0 view .LVU630
+ 2076 0046 254B     		ldr	r3, .L203
+ 2077 0048 1B68     		ldr	r3, [r3]
+ 2078              		.loc 1 1147 6 view .LVU631
+ 2079 004a 13F0807F 		tst	r3, #16777216
+ 2080 004e 42D0     		beq	.L201
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ 2081              		.loc 1 1149 5 is_stmt 1 view .LVU632
+ 2082              		.loc 1 1149 37 is_stmt 0 view .LVU633
+ 2083 0050 0223     		movs	r3, #2
+ 2084 0052 8361     		str	r3, [r0, #24]
+ 2085              	.L202:
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   else
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+ 2086              		.loc 1 1155 3 is_stmt 1 view .LVU634
+ 2087              		.loc 1 1155 52 is_stmt 0 view .LVU635
+ 2088 0054 214A     		ldr	r2, .L203
+ 2089 0056 5368     		ldr	r3, [r2, #4]
+ 2090              		.loc 1 1155 38 view .LVU636
+ 2091 0058 03F48003 		and	r3, r3, #4194304
+ 2092              		.loc 1 1155 36 view .LVU637
+ 2093 005c C361     		str	r3, [r0, #28]
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
+ 2094              		.loc 1 1156 3 is_stmt 1 view .LVU638
+ 2095              		.loc 1 1156 47 is_stmt 0 view .LVU639
+ 2096 005e 5368     		ldr	r3, [r2, #4]
+ 2097              		.loc 1 1156 33 view .LVU640
+ 2098 0060 03F03F03 		and	r3, r3, #63
+ 2099              		.loc 1 1156 31 view .LVU641
+ 2100 0064 0362     		str	r3, [r0, #32]
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Po
+ 2101              		.loc 1 1157 3 is_stmt 1 view .LVU642
+ 2102              		.loc 1 1157 48 is_stmt 0 view .LVU643
+ 2103 0066 5368     		ldr	r3, [r2, #4]
+ 2104              		.loc 1 1157 33 view .LVU644
+ 2105 0068 C3F38813 		ubfx	r3, r3, #6, #9
+ARM GAS  /tmp/ccgleihc.s 			page 64
+
+
+ 2106              		.loc 1 1157 31 view .LVU645
+ 2107 006c 4362     		str	r3, [r0, #36]
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0
+ 2108              		.loc 1 1158 3 is_stmt 1 view .LVU646
+ 2109              		.loc 1 1158 50 is_stmt 0 view .LVU647
+ 2110 006e 5368     		ldr	r3, [r2, #4]
+ 2111              		.loc 1 1158 60 view .LVU648
+ 2112 0070 03F44033 		and	r3, r3, #196608
+ 2113              		.loc 1 1158 80 view .LVU649
+ 2114 0074 03F58033 		add	r3, r3, #65536
+ 2115              		.loc 1 1158 33 view .LVU650
+ 2116 0078 DB0B     		lsrs	r3, r3, #15
+ 2117              		.loc 1 1158 31 view .LVU651
+ 2118 007a 8362     		str	r3, [r0, #40]
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Po
+ 2119              		.loc 1 1159 3 is_stmt 1 view .LVU652
+ 2120              		.loc 1 1159 48 is_stmt 0 view .LVU653
+ 2121 007c 5368     		ldr	r3, [r2, #4]
+ 2122              		.loc 1 1159 33 view .LVU654
+ 2123 007e C3F30363 		ubfx	r3, r3, #24, #4
+ 2124              		.loc 1 1159 31 view .LVU655
+ 2125 0082 C362     		str	r3, [r0, #44]
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR)
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PL
+ 2126              		.loc 1 1161 3 is_stmt 1 view .LVU656
+ 2127              		.loc 1 1161 48 is_stmt 0 view .LVU657
+ 2128 0084 5368     		ldr	r3, [r2, #4]
+ 2129              		.loc 1 1161 58 view .LVU658
+ 2130 0086 03F0E043 		and	r3, r3, #1879048192
+ 2131              	.LVL132:
+ 2132              	.LBB7:
+ 2133              	.LBI7:
+ 2134              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.0.4
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     09. April 2018
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccgleihc.s 			page 65
+
+
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ARM GAS  /tmp/ccgleihc.s 			page 66
+
+
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ARM GAS  /tmp/ccgleihc.s 			page 67
+
+
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ARM GAS  /tmp/ccgleihc.s 			page 68
+
+
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ARM GAS  /tmp/ccgleihc.s 			page 69
+
+
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccgleihc.s 			page 70
+
+
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ARM GAS  /tmp/ccgleihc.s 			page 71
+
+
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/ccgleihc.s 			page 72
+
+
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ARM GAS  /tmp/ccgleihc.s 			page 73
+
+
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/ccgleihc.s 			page 74
+
+
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ARM GAS  /tmp/ccgleihc.s 			page 75
+
+
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ARM GAS  /tmp/ccgleihc.s 			page 76
+
+
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ARM GAS  /tmp/ccgleihc.s 			page 77
+
+
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/ccgleihc.s 			page 78
+
+
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ARM GAS  /tmp/ccgleihc.s 			page 79
+
+
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ARM GAS  /tmp/ccgleihc.s 			page 80
+
+
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 891:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 892:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 895:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
+ 896:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
+ 897:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 898:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 899:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+ 901:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ 903:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_bswap32(value);
+ 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 905:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 906:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 908:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 910:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 912:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 915:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
+ 916:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 917:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 918:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+ 920:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 922:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 923:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 924:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 925:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 930:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
+ 931:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 932:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ARM GAS  /tmp/ccgleihc.s 			page 81
+
+
+ 937:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
+ 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 939:Drivers/CMSIS/Include/cmsis_gcc.h ****   int16_t result;
+ 940:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 942:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 945:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 946:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 948:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
+ 949:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
+ 950:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
+ 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
+ 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
+ 953:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 956:Drivers/CMSIS/Include/cmsis_gcc.h ****   op2 %= 32U;
+ 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (op2 == 0U)
+ 958:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 959:Drivers/CMSIS/Include/cmsis_gcc.h ****     return op1;
+ 960:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 961:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
+ 962:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 963:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 964:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 966:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
+ 967:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
+ 968:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
+ 969:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
+ 970:Drivers/CMSIS/Include/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
+ 971:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+ 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 974:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 976:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse bit order of value
+ 977:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
+ 978:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 979:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 980:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+ 2135              		.loc 2 981 31 is_stmt 1 view .LVU659
+ 2136              	.LBB8:
+ 982:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 2137              		.loc 2 983 3 view .LVU660
+ 984:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 986:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 987:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 2138              		.loc 2 988 4 view .LVU661
+ 2139 008a 4FF0E042 		mov	r2, #1879048192
+ARM GAS  /tmp/ccgleihc.s 			page 82
+
+
+ 2140              		.syntax unified
+ 2141              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 2142 008e 92FAA2F2 		rbit r2, r2
+ 2143              	@ 0 "" 2
+ 2144              	.LVL133:
+ 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 990:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+ 991:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 992:Drivers/CMSIS/Include/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
+ 993:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
+ 994:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 995:Drivers/CMSIS/Include/cmsis_gcc.h ****     result <<= 1U;
+ 996:Drivers/CMSIS/Include/cmsis_gcc.h ****     result |= value & 1U;
+ 997:Drivers/CMSIS/Include/cmsis_gcc.h ****     s--;
+ 998:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 999:Drivers/CMSIS/Include/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
+1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1001:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 2145              		.loc 2 1001 3 view .LVU662
+ 2146              		.loc 2 1001 3 is_stmt 0 view .LVU663
+ 2147              		.thumb
+ 2148              		.syntax unified
+ 2149              	.LBE8:
+ 2150              	.LBE7:
+ 2151              		.loc 1 1161 33 view .LVU664
+ 2152 0092 B2FA82F2 		clz	r2, r2
+ 2153 0096 D340     		lsrs	r3, r3, r2
+ 2154              		.loc 1 1161 31 view .LVU665
+ 2155 0098 0363     		str	r3, [r0, #48]
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 2156              		.loc 1 1163 1 view .LVU666
+ 2157 009a 7047     		bx	lr
+ 2158              	.L191:
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 2159              		.loc 1 1101 8 is_stmt 1 view .LVU667
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 2160              		.loc 1 1101 16 is_stmt 0 view .LVU668
+ 2161 009c 0F4B     		ldr	r3, .L203
+ 2162 009e 1B68     		ldr	r3, [r3]
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 2163              		.loc 1 1101 11 view .LVU669
+ 2164 00a0 13F4803F 		tst	r3, #65536
+ 2165 00a4 03D0     		beq	.L193
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2166              		.loc 1 1103 5 is_stmt 1 view .LVU670
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2167              		.loc 1 1103 33 is_stmt 0 view .LVU671
+ 2168 00a6 4FF48033 		mov	r3, #65536
+ 2169 00aa 4360     		str	r3, [r0, #4]
+ 2170 00ac B2E7     		b	.L192
+ 2171              	.L193:
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2172              		.loc 1 1107 5 is_stmt 1 view .LVU672
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2173              		.loc 1 1107 33 is_stmt 0 view .LVU673
+ 2174 00ae 0023     		movs	r3, #0
+ARM GAS  /tmp/ccgleihc.s 			page 83
+
+
+ 2175 00b0 4360     		str	r3, [r0, #4]
+ 2176 00b2 AFE7     		b	.L192
+ 2177              	.L194:
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2178              		.loc 1 1117 5 is_stmt 1 view .LVU674
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2179              		.loc 1 1117 33 is_stmt 0 view .LVU675
+ 2180 00b4 0023     		movs	r3, #0
+ 2181 00b6 C360     		str	r3, [r0, #12]
+ 2182 00b8 B3E7     		b	.L195
+ 2183              	.L196:
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 2184              		.loc 1 1127 8 is_stmt 1 view .LVU676
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 2185              		.loc 1 1127 16 is_stmt 0 view .LVU677
+ 2186 00ba 084B     		ldr	r3, .L203
+ 2187 00bc 1B6F     		ldr	r3, [r3, #112]
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 2188              		.loc 1 1127 11 view .LVU678
+ 2189 00be 13F0010F 		tst	r3, #1
+ 2190 00c2 02D0     		beq	.L198
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2191              		.loc 1 1129 5 is_stmt 1 view .LVU679
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2192              		.loc 1 1129 33 is_stmt 0 view .LVU680
+ 2193 00c4 0123     		movs	r3, #1
+ 2194 00c6 8360     		str	r3, [r0, #8]
+ 2195 00c8 B6E7     		b	.L197
+ 2196              	.L198:
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2197              		.loc 1 1133 5 is_stmt 1 view .LVU681
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2198              		.loc 1 1133 33 is_stmt 0 view .LVU682
+ 2199 00ca 0023     		movs	r3, #0
+ 2200 00cc 8360     		str	r3, [r0, #8]
+ 2201 00ce B3E7     		b	.L197
+ 2202              	.L199:
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2203              		.loc 1 1143 5 is_stmt 1 view .LVU683
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2204              		.loc 1 1143 33 is_stmt 0 view .LVU684
+ 2205 00d0 0023     		movs	r3, #0
+ 2206 00d2 4361     		str	r3, [r0, #20]
+ 2207 00d4 B7E7     		b	.L200
+ 2208              	.L201:
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2209              		.loc 1 1153 5 is_stmt 1 view .LVU685
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2210              		.loc 1 1153 37 is_stmt 0 view .LVU686
+ 2211 00d6 0123     		movs	r3, #1
+ 2212 00d8 8361     		str	r3, [r0, #24]
+ 2213 00da BBE7     		b	.L202
+ 2214              	.L204:
+ 2215              		.align	2
+ 2216              	.L203:
+ 2217 00dc 00380240 		.word	1073887232
+ 2218              		.cfi_endproc
+ARM GAS  /tmp/ccgleihc.s 			page 84
+
+
+ 2219              	.LFE151:
+ 2221              		.section	.text.HAL_RCC_GetClockConfig,"ax",%progbits
+ 2222              		.align	1
+ 2223              		.global	HAL_RCC_GetClockConfig
+ 2224              		.syntax unified
+ 2225              		.thumb
+ 2226              		.thumb_func
+ 2227              		.fpu fpv5-d16
+ 2229              	HAL_RCC_GetClockConfig:
+ 2230              	.LVL134:
+ 2231              	.LFB152:
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  Configures the RCC_ClkInitStruct according to the internal
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * RCC configuration registers.
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * will be configured.
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @param  pFLatency Pointer on the Flash Latency.
+1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval None
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 2232              		.loc 1 1174 1 is_stmt 1 view -0
+ 2233              		.cfi_startproc
+ 2234              		@ args = 0, pretend = 0, frame = 0
+ 2235              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2236              		@ link register save eliminated.
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Set all possible values for the Clock type parameter --------------------*/
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | 
+ 2237              		.loc 1 1176 3 view .LVU688
+ 2238              		.loc 1 1176 32 is_stmt 0 view .LVU689
+ 2239 0000 0F23     		movs	r3, #15
+ 2240 0002 0360     		str	r3, [r0]
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get the SYSCLK configuration --------------------------------------------*/
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+ 2241              		.loc 1 1179 3 is_stmt 1 view .LVU690
+ 2242              		.loc 1 1179 51 is_stmt 0 view .LVU691
+ 2243 0004 0B4B     		ldr	r3, .L206
+ 2244 0006 9A68     		ldr	r2, [r3, #8]
+ 2245              		.loc 1 1179 37 view .LVU692
+ 2246 0008 02F00302 		and	r2, r2, #3
+ 2247              		.loc 1 1179 35 view .LVU693
+ 2248 000c 4260     		str	r2, [r0, #4]
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get the HCLK configuration ----------------------------------------------*/
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+ 2249              		.loc 1 1182 3 is_stmt 1 view .LVU694
+ 2250              		.loc 1 1182 52 is_stmt 0 view .LVU695
+ 2251 000e 9A68     		ldr	r2, [r3, #8]
+ 2252              		.loc 1 1182 38 view .LVU696
+ 2253 0010 02F0F002 		and	r2, r2, #240
+ 2254              		.loc 1 1182 36 view .LVU697
+ 2255 0014 8260     		str	r2, [r0, #8]
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get the APB1 configuration ----------------------------------------------*/
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+ARM GAS  /tmp/ccgleihc.s 			page 85
+
+
+ 2256              		.loc 1 1185 3 is_stmt 1 view .LVU698
+ 2257              		.loc 1 1185 53 is_stmt 0 view .LVU699
+ 2258 0016 9A68     		ldr	r2, [r3, #8]
+ 2259              		.loc 1 1185 39 view .LVU700
+ 2260 0018 02F4E052 		and	r2, r2, #7168
+ 2261              		.loc 1 1185 37 view .LVU701
+ 2262 001c C260     		str	r2, [r0, #12]
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get the APB2 configuration ----------------------------------------------*/
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
+ 2263              		.loc 1 1188 3 is_stmt 1 view .LVU702
+ 2264              		.loc 1 1188 54 is_stmt 0 view .LVU703
+ 2265 001e 9B68     		ldr	r3, [r3, #8]
+ 2266              		.loc 1 1188 39 view .LVU704
+ 2267 0020 DB08     		lsrs	r3, r3, #3
+ 2268 0022 03F4E053 		and	r3, r3, #7168
+ 2269              		.loc 1 1188 37 view .LVU705
+ 2270 0026 0361     		str	r3, [r0, #16]
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Get the Flash Wait State (Latency) configuration ------------------------*/
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+ 2271              		.loc 1 1191 3 is_stmt 1 view .LVU706
+ 2272              		.loc 1 1191 32 is_stmt 0 view .LVU707
+ 2273 0028 034B     		ldr	r3, .L206+4
+ 2274 002a 1B68     		ldr	r3, [r3]
+ 2275              		.loc 1 1191 16 view .LVU708
+ 2276 002c 03F00F03 		and	r3, r3, #15
+ 2277              		.loc 1 1191 14 view .LVU709
+ 2278 0030 0B60     		str	r3, [r1]
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 2279              		.loc 1 1192 1 view .LVU710
+ 2280 0032 7047     		bx	lr
+ 2281              	.L207:
+ 2282              		.align	2
+ 2283              	.L206:
+ 2284 0034 00380240 		.word	1073887232
+ 2285 0038 003C0240 		.word	1073888256
+ 2286              		.cfi_endproc
+ 2287              	.LFE152:
+ 2289              		.section	.text.HAL_RCC_CSSCallback,"ax",%progbits
+ 2290              		.align	1
+ 2291              		.weak	HAL_RCC_CSSCallback
+ 2292              		.syntax unified
+ 2293              		.thumb
+ 2294              		.thumb_func
+ 2295              		.fpu fpv5-d16
+ 2297              	HAL_RCC_CSSCallback:
+ 2298              	.LFB154:
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief This function handles the RCC CSS interrupt request.
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @note This API should be called under the NMI_Handler().
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval None
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_NMI_IRQHandler(void)
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Check RCC CSSF flag  */
+ARM GAS  /tmp/ccgleihc.s 			page 86
+
+
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   if (__HAL_RCC_GET_IT(RCC_IT_CSS))
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* RCC Clock Security System interrupt user callback */
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     HAL_RCC_CSSCallback();
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     /* Clear RCC CSS pending bit */
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /**
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @brief  RCC Clock Security System interrupt callback
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   * @retval None
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   */
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __weak void HAL_RCC_CSSCallback(void)
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** {
+ 2299              		.loc 1 1217 1 is_stmt 1 view -0
+ 2300              		.cfi_startproc
+ 2301              		@ args = 0, pretend = 0, frame = 0
+ 2302              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2303              		@ link register save eliminated.
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****             the HAL_RCC_CSSCallback could be implemented in the user file
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****    */
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** }
+ 2304              		.loc 1 1221 1 view .LVU712
+ 2305 0000 7047     		bx	lr
+ 2306              		.cfi_endproc
+ 2307              	.LFE154:
+ 2309              		.section	.text.HAL_RCC_NMI_IRQHandler,"ax",%progbits
+ 2310              		.align	1
+ 2311              		.global	HAL_RCC_NMI_IRQHandler
+ 2312              		.syntax unified
+ 2313              		.thumb
+ 2314              		.thumb_func
+ 2315              		.fpu fpv5-d16
+ 2317              	HAL_RCC_NMI_IRQHandler:
+ 2318              	.LFB153:
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   /* Check RCC CSSF flag  */
+ 2319              		.loc 1 1200 1 view -0
+ 2320              		.cfi_startproc
+ 2321              		@ args = 0, pretend = 0, frame = 0
+ 2322              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2323 0000 08B5     		push	{r3, lr}
+ 2324              	.LCFI17:
+ 2325              		.cfi_def_cfa_offset 8
+ 2326              		.cfi_offset 3, -8
+ 2327              		.cfi_offset 14, -4
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 2328              		.loc 1 1202 3 view .LVU714
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 2329              		.loc 1 1202 7 is_stmt 0 view .LVU715
+ 2330 0002 064B     		ldr	r3, .L213
+ 2331 0004 DB68     		ldr	r3, [r3, #12]
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   {
+ 2332              		.loc 1 1202 6 view .LVU716
+ 2333 0006 13F0800F 		tst	r3, #128
+ARM GAS  /tmp/ccgleihc.s 			page 87
+
+
+ 2334 000a 00D1     		bne	.L212
+ 2335              	.L209:
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 2336              		.loc 1 1210 1 view .LVU717
+ 2337 000c 08BD     		pop	{r3, pc}
+ 2338              	.L212:
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 2339              		.loc 1 1205 5 is_stmt 1 view .LVU718
+ 2340 000e FFF7FEFF 		bl	HAL_RCC_CSSCallback
+ 2341              	.LVL135:
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c ****   }
+ 2342              		.loc 1 1208 5 view .LVU719
+ 2343 0012 024B     		ldr	r3, .L213
+ 2344 0014 8022     		movs	r2, #128
+ 2345 0016 9A73     		strb	r2, [r3, #14]
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 
+ 2346              		.loc 1 1210 1 is_stmt 0 view .LVU720
+ 2347 0018 F8E7     		b	.L209
+ 2348              	.L214:
+ 2349 001a 00BF     		.align	2
+ 2350              	.L213:
+ 2351 001c 00380240 		.word	1073887232
+ 2352              		.cfi_endproc
+ 2353              	.LFE153:
+ 2355              		.text
+ 2356              	.Letext0:
+ 2357              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 2358              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h"
+ 2359              		.file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 2360              		.file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 2361              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 2362              		.file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h"
+ 2363              		.file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h"
+ 2364              		.file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h"
+ 2365              		.file 11 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ARM GAS  /tmp/ccgleihc.s 			page 88
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_rcc.c
+     /tmp/ccgleihc.s:17     .text.HAL_RCC_DeInit:0000000000000000 $t
+     /tmp/ccgleihc.s:25     .text.HAL_RCC_DeInit:0000000000000000 HAL_RCC_DeInit
+     /tmp/ccgleihc.s:299    .text.HAL_RCC_DeInit:0000000000000144 $d
+     /tmp/ccgleihc.s:308    .text.HAL_RCC_OscConfig:0000000000000000 $t
+     /tmp/ccgleihc.s:315    .text.HAL_RCC_OscConfig:0000000000000000 HAL_RCC_OscConfig
+     /tmp/ccgleihc.s:821    .text.HAL_RCC_OscConfig:000000000000026c $d
+     /tmp/ccgleihc.s:826    .text.HAL_RCC_OscConfig:0000000000000274 $t
+     /tmp/ccgleihc.s:1216   .text.HAL_RCC_OscConfig:0000000000000440 $d
+     /tmp/ccgleihc.s:1221   .text.HAL_RCC_MCOConfig:0000000000000000 $t
+     /tmp/ccgleihc.s:1228   .text.HAL_RCC_MCOConfig:0000000000000000 HAL_RCC_MCOConfig
+     /tmp/ccgleihc.s:1378   .text.HAL_RCC_MCOConfig:000000000000008c $d
+     /tmp/ccgleihc.s:1385   .text.HAL_RCC_EnableCSS:0000000000000000 $t
+     /tmp/ccgleihc.s:1392   .text.HAL_RCC_EnableCSS:0000000000000000 HAL_RCC_EnableCSS
+     /tmp/ccgleihc.s:1409   .text.HAL_RCC_EnableCSS:000000000000000c $d
+     /tmp/ccgleihc.s:1414   .text.HAL_RCC_DisableCSS:0000000000000000 $t
+     /tmp/ccgleihc.s:1421   .text.HAL_RCC_DisableCSS:0000000000000000 HAL_RCC_DisableCSS
+     /tmp/ccgleihc.s:1438   .text.HAL_RCC_DisableCSS:000000000000000c $d
+     /tmp/ccgleihc.s:1444   .text.HAL_RCC_GetSysClockFreq:0000000000000000 $t
+     /tmp/ccgleihc.s:1451   .text.HAL_RCC_GetSysClockFreq:0000000000000000 HAL_RCC_GetSysClockFreq
+     /tmp/ccgleihc.s:1567   .text.HAL_RCC_GetSysClockFreq:0000000000000098 $d
+     /tmp/ccgleihc.s:1574   .text.HAL_RCC_ClockConfig:0000000000000000 $t
+     /tmp/ccgleihc.s:1581   .text.HAL_RCC_ClockConfig:0000000000000000 HAL_RCC_ClockConfig
+     /tmp/ccgleihc.s:1880   .text.HAL_RCC_ClockConfig:0000000000000158 $d
+     /tmp/ccgleihc.s:1889   .text.HAL_RCC_GetHCLKFreq:0000000000000000 $t
+     /tmp/ccgleihc.s:1896   .text.HAL_RCC_GetHCLKFreq:0000000000000000 HAL_RCC_GetHCLKFreq
+     /tmp/ccgleihc.s:1911   .text.HAL_RCC_GetHCLKFreq:0000000000000008 $d
+     /tmp/ccgleihc.s:1916   .text.HAL_RCC_GetPCLK1Freq:0000000000000000 $t
+     /tmp/ccgleihc.s:1923   .text.HAL_RCC_GetPCLK1Freq:0000000000000000 HAL_RCC_GetPCLK1Freq
+     /tmp/ccgleihc.s:1952   .text.HAL_RCC_GetPCLK1Freq:0000000000000018 $d
+     /tmp/ccgleihc.s:1958   .text.HAL_RCC_GetPCLK2Freq:0000000000000000 $t
+     /tmp/ccgleihc.s:1965   .text.HAL_RCC_GetPCLK2Freq:0000000000000000 HAL_RCC_GetPCLK2Freq
+     /tmp/ccgleihc.s:1994   .text.HAL_RCC_GetPCLK2Freq:0000000000000018 $d
+     /tmp/ccgleihc.s:2000   .text.HAL_RCC_GetOscConfig:0000000000000000 $t
+     /tmp/ccgleihc.s:2007   .text.HAL_RCC_GetOscConfig:0000000000000000 HAL_RCC_GetOscConfig
+     /tmp/ccgleihc.s:2217   .text.HAL_RCC_GetOscConfig:00000000000000dc $d
+     /tmp/ccgleihc.s:2222   .text.HAL_RCC_GetClockConfig:0000000000000000 $t
+     /tmp/ccgleihc.s:2229   .text.HAL_RCC_GetClockConfig:0000000000000000 HAL_RCC_GetClockConfig
+     /tmp/ccgleihc.s:2284   .text.HAL_RCC_GetClockConfig:0000000000000034 $d
+     /tmp/ccgleihc.s:2290   .text.HAL_RCC_CSSCallback:0000000000000000 $t
+     /tmp/ccgleihc.s:2297   .text.HAL_RCC_CSSCallback:0000000000000000 HAL_RCC_CSSCallback
+     /tmp/ccgleihc.s:2310   .text.HAL_RCC_NMI_IRQHandler:0000000000000000 $t
+     /tmp/ccgleihc.s:2317   .text.HAL_RCC_NMI_IRQHandler:0000000000000000 HAL_RCC_NMI_IRQHandler
+     /tmp/ccgleihc.s:2351   .text.HAL_RCC_NMI_IRQHandler:000000000000001c $d
+
+UNDEFINED SYMBOLS
+HAL_GetTick
+HAL_InitTick
+SystemCoreClock
+uwTickPrio
+HAL_GPIO_Init
+__aeabi_uldivmod
+AHBPrescTable
+APBPrescTable
diff --git a/build/stm32f7xx_hal_rcc.o b/build/stm32f7xx_hal_rcc.o
new file mode 100644
index 0000000..b6cb205
Binary files /dev/null and b/build/stm32f7xx_hal_rcc.o differ
diff --git a/build/stm32f7xx_hal_rcc_ex.d b/build/stm32f7xx_hal_rcc_ex.d
new file mode 100644
index 0000000..5d04415
--- /dev/null
+++ b/build/stm32f7xx_hal_rcc_ex.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_rcc_ex.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_rcc_ex.lst b/build/stm32f7xx_hal_rcc_ex.lst
new file mode 100644
index 0000000..e8b779c
--- /dev/null
+++ b/build/stm32f7xx_hal_rcc_ex.lst
@@ -0,0 +1,4554 @@
+ARM GAS  /tmp/cc41FM7T.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_rcc_ex.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.HAL_RCCEx_PeriphCLKConfig,"ax",%progbits
+  17              		.align	1
+  18              		.global	HAL_RCCEx_PeriphCLKConfig
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	HAL_RCCEx_PeriphCLKConfig:
+  26              	.LVL0:
+  27              	.LFB141:
+  28              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @file    stm32f7xx_hal_rcc_ex.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @brief   Extension RCC HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *          functionalities RCC extension peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *           + Extended Peripheral Control functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   ******************************************************************************
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @attention
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * Copyright (c) 2017 STMicroelectronics.
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * All rights reserved.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * the root directory of this software component.
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   ******************************************************************************
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Includes ------------------------------------------------------------------*/
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #include "stm32f7xx_hal.h"
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @{
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx RCCEx
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @brief RCCEx HAL module driver
+ARM GAS  /tmp/cc41FM7T.s 			page 2
+
+
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #ifdef HAL_RCC_MODULE_ENABLED
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private define ------------------------------------------------------------*/
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Defines RCCEx Private Defines
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @{
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @}
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private macro -------------------------------------------------------------*/
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  * @{
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  */
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @}
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  * @{
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  */
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @}
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private variables ---------------------------------------------------------*/
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private function prototypes -----------------------------------------------*/
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private functions ---------------------------------------------------------*/
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @{
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  *  @brief  Extended Peripheral Control functions
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  *
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** @verbatim
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  ===============================================================================
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                 ##### Extended Peripheral Control functions  #####
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  ===============================================================================
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     [..]
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     This subsection provides a set of functions allowing to control the RCC Clocks
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     frequencies.
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     [..]
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         select the RTC clock source; in this case the Backup domain will be reset in
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         order to modify the RTC Clock source, as consequence RTC registers (including
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         the backup registers) and RCC_BDCR register will be set to their reset values.
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** @endverbatim
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @{
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+ARM GAS  /tmp/cc41FM7T.s 			page 3
+
+
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     defined (STM32F750xx)
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         parameters in the RCC_PeriphCLKInitTypeDef.
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         contains the configuration information for the Extended Peripherals
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         the RTC clock source; in this case the Backup domain will be reset in
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         order to modify the RTC Clock source, as consequence RTC registers (including
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         the backup registers) are set to their reset values.
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @retval HAL status
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** {
+  29              		.loc 1 106 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 8
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		.loc 1 106 1 is_stmt 0 view .LVU1
+  34 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 20
+  37              		.cfi_offset 4, -20
+  38              		.cfi_offset 5, -16
+  39              		.cfi_offset 6, -12
+  40              		.cfi_offset 7, -8
+  41              		.cfi_offset 14, -4
+  42 0002 83B0     		sub	sp, sp, #12
+  43              	.LCFI1:
+  44              		.cfi_def_cfa_offset 32
+  45 0004 0446     		mov	r4, r0
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tickstart = 0;
+  46              		.loc 1 107 3 is_stmt 1 view .LVU2
+  47              	.LVL1:
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tmpreg0 = 0;
+  48              		.loc 1 108 3 view .LVU3
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tmpreg1 = 0;
+  49              		.loc 1 109 3 view .LVU4
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t plli2sused = 0;
+  50              		.loc 1 110 3 view .LVU5
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t pllsaiused = 0;
+  51              		.loc 1 111 3 view .LVU6
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Check the parameters */
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+  52              		.loc 1 114 3 view .LVU7
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*----------------------------------- I2S configuration ----------------------------------*/
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+  53              		.loc 1 117 3 view .LVU8
+  54              		.loc 1 117 21 is_stmt 0 view .LVU9
+  55 0006 0668     		ldr	r6, [r0]
+ARM GAS  /tmp/cc41FM7T.s 			page 4
+
+
+  56              		.loc 1 117 5 view .LVU10
+  57 0008 16F00106 		ands	r6, r6, #1
+  58 000c 0DD0     		beq	.L2
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
+  59              		.loc 1 120 5 is_stmt 1 view .LVU11
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure I2S Clock source */
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
+  60              		.loc 1 123 5 view .LVU12
+  61              		.loc 1 123 5 view .LVU13
+  62 000e B54B     		ldr	r3, .L87
+  63 0010 9A68     		ldr	r2, [r3, #8]
+  64 0012 22F40002 		bic	r2, r2, #8388608
+  65 0016 9A60     		str	r2, [r3, #8]
+  66              		.loc 1 123 5 view .LVU14
+  67 0018 9A68     		ldr	r2, [r3, #8]
+  68 001a 416B     		ldr	r1, [r0, #52]
+  69 001c 0A43     		orrs	r2, r2, r1
+  70 001e 9A60     		str	r2, [r3, #8]
+  71              		.loc 1 123 5 view .LVU15
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLI2S when it's used as clock source for I2S */
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
+  72              		.loc 1 126 5 view .LVU16
+  73              		.loc 1 126 21 is_stmt 0 view .LVU17
+  74 0020 436B     		ldr	r3, [r0, #52]
+  75              		.loc 1 126 7 view .LVU18
+  76 0022 002B     		cmp	r3, #0
+  77 0024 00F06781 		beq	.L59
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t pllsaiused = 0;
+  78              		.loc 1 110 12 view .LVU19
+  79 0028 0026     		movs	r6, #0
+  80              	.L2:
+  81              	.LVL2:
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       plli2sused = 1;
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------ SAI1 configuration --------------------------------------*
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
+  82              		.loc 1 133 3 is_stmt 1 view .LVU20
+  83              		.loc 1 133 21 is_stmt 0 view .LVU21
+  84 002a 2568     		ldr	r5, [r4]
+  85              		.loc 1 133 5 view .LVU22
+  86 002c 15F40025 		ands	r5, r5, #524288
+  87 0030 11D0     		beq	.L3
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+  88              		.loc 1 136 5 is_stmt 1 view .LVU23
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure SAI1 Clock source */
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+  89              		.loc 1 139 5 view .LVU24
+ARM GAS  /tmp/cc41FM7T.s 			page 5
+
+
+  90 0032 AC4A     		ldr	r2, .L87
+  91 0034 D2F88C30 		ldr	r3, [r2, #140]
+  92 0038 23F44013 		bic	r3, r3, #3145728
+  93 003c E16B     		ldr	r1, [r4, #60]
+  94 003e 0B43     		orrs	r3, r3, r1
+  95 0040 C2F88C30 		str	r3, [r2, #140]
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLI2S when it's used as clock source for SAI */
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
+  96              		.loc 1 141 5 view .LVU25
+  97              		.loc 1 141 21 is_stmt 0 view .LVU26
+  98 0044 E36B     		ldr	r3, [r4, #60]
+  99              		.loc 1 141 7 view .LVU27
+ 100 0046 B3F5801F 		cmp	r3, #1048576
+ 101 004a 00F05681 		beq	.L75
+ 102              	.LVL3:
+ 103              	.L4:
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       plli2sused = 1;
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLSAI when it's used as clock source for SAI */
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
+ 104              		.loc 1 146 5 is_stmt 1 view .LVU28
+ 105              		.loc 1 146 7 is_stmt 0 view .LVU29
+ 106 004e 002B     		cmp	r3, #0
+ 107 0050 00F05581 		beq	.L61
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 108              		.loc 1 111 12 view .LVU30
+ 109 0054 0025     		movs	r5, #0
+ 110              	.L3:
+ 111              	.LVL4:
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       pllsaiused = 1;
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------ SAI2 configuration --------------------------------------*
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
+ 112              		.loc 1 153 3 is_stmt 1 view .LVU31
+ 113              		.loc 1 153 21 is_stmt 0 view .LVU32
+ 114 0056 2368     		ldr	r3, [r4]
+ 115              		.loc 1 153 5 view .LVU33
+ 116 0058 13F4801F 		tst	r3, #1048576
+ 117 005c 0FD0     		beq	.L5
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+ 118              		.loc 1 156 5 is_stmt 1 view .LVU34
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure SAI2 Clock source */
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+ 119              		.loc 1 159 5 view .LVU35
+ 120 005e A14A     		ldr	r2, .L87
+ 121 0060 D2F88C30 		ldr	r3, [r2, #140]
+ 122 0064 23F44003 		bic	r3, r3, #12582912
+ 123 0068 216C     		ldr	r1, [r4, #64]
+ 124 006a 0B43     		orrs	r3, r3, r1
+ 125 006c C2F88C30 		str	r3, [r2, #140]
+ARM GAS  /tmp/cc41FM7T.s 			page 6
+
+
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLI2S when it's used as clock source for SAI */
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
+ 126              		.loc 1 162 5 view .LVU36
+ 127              		.loc 1 162 21 is_stmt 0 view .LVU37
+ 128 0070 236C     		ldr	r3, [r4, #64]
+ 129              		.loc 1 162 7 view .LVU38
+ 130 0072 B3F5800F 		cmp	r3, #4194304
+ 131 0076 00F04481 		beq	.L76
+ 132              	.LVL5:
+ 133              	.L6:
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       plli2sused = 1;
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLSAI when it's used as clock source for SAI */
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
+ 134              		.loc 1 167 5 is_stmt 1 view .LVU39
+ 135              		.loc 1 167 7 is_stmt 0 view .LVU40
+ 136 007a 03B9     		cbnz	r3, .L5
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       pllsaiused = 1;
+ 137              		.loc 1 169 18 view .LVU41
+ 138 007c 0125     		movs	r5, #1
+ 139              	.LVL6:
+ 140              	.L5:
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- SPDIF-RX Configuration ---------------------------------
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+ 141              		.loc 1 174 3 is_stmt 1 view .LVU42
+ 142              		.loc 1 174 21 is_stmt 0 view .LVU43
+ 143 007e 2368     		ldr	r3, [r4]
+ 144              		.loc 1 174 5 view .LVU44
+ 145 0080 13F0807F 		tst	r3, #16777216
+ 146 0084 00D0     		beq	.L7
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       plli2sused = 1;
+ 147              		.loc 1 176 18 view .LVU45
+ 148 0086 0126     		movs	r6, #1
+ 149              	.LVL7:
+ 150              	.L7:
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------ RTC configuration --------------------------------------*/
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ 151              		.loc 1 180 3 is_stmt 1 view .LVU46
+ 152              		.loc 1 180 5 is_stmt 0 view .LVU47
+ 153 0088 13F0200F 		tst	r3, #32
+ 154 008c 40F03B81 		bne	.L77
+ 155              	.LVL8:
+ 156              	.L8:
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check for RTC Parameters used to output RTCCLK */
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable Power Clock*/
+ARM GAS  /tmp/cc41FM7T.s 			page 7
+
+
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_PWR_CLK_ENABLE();
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable write access to Backup domain */
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     PWR->CR1 |= PWR_CR1_DBP;
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Get Start Tick*/
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tickstart = HAL_GetTick();
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Wait for Backup domain Write protection disable */
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     while((PWR->CR1 & PWR_CR1_DBP) == RESET)
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         return HAL_TIMEOUT;
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Store the content of BDCR register before the reset of Backup Domain */
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_BACKUPRESET_FORCE();
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_BACKUPRESET_RELEASE();
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Restore the Content of BDCR register */
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       RCC->BDCR = tmpreg0;
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* Get Start Tick*/
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         tickstart = HAL_GetTick();
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* Wait till LSE is ready */
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           {
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****             return HAL_TIMEOUT;
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           }
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ 157              		.loc 1 234 5 is_stmt 1 discriminator 5 view .LVU48
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------ TIM configuration --------------------------------------*/
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ 158              		.loc 1 238 3 discriminator 5 view .LVU49
+ 159              		.loc 1 238 21 is_stmt 0 discriminator 5 view .LVU50
+ 160 0090 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/cc41FM7T.s 			page 8
+
+
+ 161              		.loc 1 238 5 discriminator 5 view .LVU51
+ 162 0092 13F0100F 		tst	r3, #16
+ 163 0096 0CD0     		beq	.L17
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+ 164              		.loc 1 241 5 is_stmt 1 view .LVU52
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure Timer Prescaler */
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ 165              		.loc 1 244 5 view .LVU53
+ 166              		.loc 1 244 5 view .LVU54
+ 167 0098 924B     		ldr	r3, .L87
+ 168 009a D3F88C20 		ldr	r2, [r3, #140]
+ 169 009e 22F08072 		bic	r2, r2, #16777216
+ 170 00a2 C3F88C20 		str	r2, [r3, #140]
+ 171              		.loc 1 244 5 view .LVU55
+ 172 00a6 D3F88C20 		ldr	r2, [r3, #140]
+ 173 00aa A16B     		ldr	r1, [r4, #56]
+ 174 00ac 0A43     		orrs	r2, r2, r1
+ 175 00ae C3F88C20 		str	r2, [r3, #140]
+ 176              	.L17:
+ 177              		.loc 1 244 5 discriminator 1 view .LVU56
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- I2C1 Configuration -----------------------------------*/
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+ 178              		.loc 1 248 3 discriminator 1 view .LVU57
+ 179              		.loc 1 248 21 is_stmt 0 discriminator 1 view .LVU58
+ 180 00b2 2368     		ldr	r3, [r4]
+ 181              		.loc 1 248 5 discriminator 1 view .LVU59
+ 182 00b4 13F4804F 		tst	r3, #16384
+ 183 00b8 08D0     		beq	.L18
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+ 184              		.loc 1 251 5 is_stmt 1 view .LVU60
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the I2C1 clock source */
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+ 185              		.loc 1 254 5 view .LVU61
+ 186 00ba 8A4A     		ldr	r2, .L87
+ 187 00bc D2F89030 		ldr	r3, [r2, #144]
+ 188 00c0 23F44033 		bic	r3, r3, #196608
+ 189 00c4 616E     		ldr	r1, [r4, #100]
+ 190 00c6 0B43     		orrs	r3, r3, r1
+ 191 00c8 C2F89030 		str	r3, [r2, #144]
+ 192              	.L18:
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- I2C2 Configuration -----------------------------------*/
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+ 193              		.loc 1 258 3 view .LVU62
+ 194              		.loc 1 258 21 is_stmt 0 view .LVU63
+ 195 00cc 2368     		ldr	r3, [r4]
+ 196              		.loc 1 258 5 view .LVU64
+ 197 00ce 13F4004F 		tst	r3, #32768
+ARM GAS  /tmp/cc41FM7T.s 			page 9
+
+
+ 198 00d2 08D0     		beq	.L19
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+ 199              		.loc 1 261 5 is_stmt 1 view .LVU65
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the I2C2 clock source */
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+ 200              		.loc 1 264 5 view .LVU66
+ 201 00d4 834A     		ldr	r2, .L87
+ 202 00d6 D2F89030 		ldr	r3, [r2, #144]
+ 203 00da 23F44023 		bic	r3, r3, #786432
+ 204 00de A16E     		ldr	r1, [r4, #104]
+ 205 00e0 0B43     		orrs	r3, r3, r1
+ 206 00e2 C2F89030 		str	r3, [r2, #144]
+ 207              	.L19:
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- I2C3 Configuration -----------------------------------*/
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+ 208              		.loc 1 268 3 view .LVU67
+ 209              		.loc 1 268 21 is_stmt 0 view .LVU68
+ 210 00e6 2368     		ldr	r3, [r4]
+ 211              		.loc 1 268 5 view .LVU69
+ 212 00e8 13F4803F 		tst	r3, #65536
+ 213 00ec 08D0     		beq	.L20
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+ 214              		.loc 1 271 5 is_stmt 1 view .LVU70
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the I2C3 clock source */
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+ 215              		.loc 1 274 5 view .LVU71
+ 216 00ee 7D4A     		ldr	r2, .L87
+ 217 00f0 D2F89030 		ldr	r3, [r2, #144]
+ 218 00f4 23F44013 		bic	r3, r3, #3145728
+ 219 00f8 E16E     		ldr	r1, [r4, #108]
+ 220 00fa 0B43     		orrs	r3, r3, r1
+ 221 00fc C2F89030 		str	r3, [r2, #144]
+ 222              	.L20:
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- I2C4 Configuration -----------------------------------*/
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+ 223              		.loc 1 278 3 view .LVU72
+ 224              		.loc 1 278 21 is_stmt 0 view .LVU73
+ 225 0100 2368     		ldr	r3, [r4]
+ 226              		.loc 1 278 5 view .LVU74
+ 227 0102 13F4003F 		tst	r3, #131072
+ 228 0106 08D0     		beq	.L21
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+ 229              		.loc 1 281 5 is_stmt 1 view .LVU75
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the I2C4 clock source */
+ARM GAS  /tmp/cc41FM7T.s 			page 10
+
+
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+ 230              		.loc 1 284 5 view .LVU76
+ 231 0108 764A     		ldr	r2, .L87
+ 232 010a D2F89030 		ldr	r3, [r2, #144]
+ 233 010e 23F44003 		bic	r3, r3, #12582912
+ 234 0112 216F     		ldr	r1, [r4, #112]
+ 235 0114 0B43     		orrs	r3, r3, r1
+ 236 0116 C2F89030 		str	r3, [r2, #144]
+ 237              	.L21:
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- USART1 Configuration -----------------------------------
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+ 238              		.loc 1 288 3 view .LVU77
+ 239              		.loc 1 288 21 is_stmt 0 view .LVU78
+ 240 011a 2368     		ldr	r3, [r4]
+ 241              		.loc 1 288 5 view .LVU79
+ 242 011c 13F0400F 		tst	r3, #64
+ 243 0120 08D0     		beq	.L22
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+ 244              		.loc 1 291 5 is_stmt 1 view .LVU80
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the USART1 clock source */
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+ 245              		.loc 1 294 5 view .LVU81
+ 246 0122 704A     		ldr	r2, .L87
+ 247 0124 D2F89030 		ldr	r3, [r2, #144]
+ 248 0128 23F00303 		bic	r3, r3, #3
+ 249 012c 616C     		ldr	r1, [r4, #68]
+ 250 012e 0B43     		orrs	r3, r3, r1
+ 251 0130 C2F89030 		str	r3, [r2, #144]
+ 252              	.L22:
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- USART2 Configuration -----------------------------------
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+ 253              		.loc 1 298 3 view .LVU82
+ 254              		.loc 1 298 21 is_stmt 0 view .LVU83
+ 255 0134 2368     		ldr	r3, [r4]
+ 256              		.loc 1 298 5 view .LVU84
+ 257 0136 13F0800F 		tst	r3, #128
+ 258 013a 08D0     		beq	.L23
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+ 259              		.loc 1 301 5 is_stmt 1 view .LVU85
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the USART2 clock source */
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+ 260              		.loc 1 304 5 view .LVU86
+ 261 013c 694A     		ldr	r2, .L87
+ 262 013e D2F89030 		ldr	r3, [r2, #144]
+ 263 0142 23F00C03 		bic	r3, r3, #12
+ 264 0146 A16C     		ldr	r1, [r4, #72]
+ 265 0148 0B43     		orrs	r3, r3, r1
+ARM GAS  /tmp/cc41FM7T.s 			page 11
+
+
+ 266 014a C2F89030 		str	r3, [r2, #144]
+ 267              	.L23:
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- USART3 Configuration -----------------------------------
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+ 268              		.loc 1 308 3 view .LVU87
+ 269              		.loc 1 308 21 is_stmt 0 view .LVU88
+ 270 014e 2368     		ldr	r3, [r4]
+ 271              		.loc 1 308 5 view .LVU89
+ 272 0150 13F4807F 		tst	r3, #256
+ 273 0154 08D0     		beq	.L24
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+ 274              		.loc 1 311 5 is_stmt 1 view .LVU90
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the USART3 clock source */
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+ 275              		.loc 1 314 5 view .LVU91
+ 276 0156 634A     		ldr	r2, .L87
+ 277 0158 D2F89030 		ldr	r3, [r2, #144]
+ 278 015c 23F03003 		bic	r3, r3, #48
+ 279 0160 E16C     		ldr	r1, [r4, #76]
+ 280 0162 0B43     		orrs	r3, r3, r1
+ 281 0164 C2F89030 		str	r3, [r2, #144]
+ 282              	.L24:
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- UART4 Configuration -----------------------------------*
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+ 283              		.loc 1 318 3 view .LVU92
+ 284              		.loc 1 318 21 is_stmt 0 view .LVU93
+ 285 0168 2368     		ldr	r3, [r4]
+ 286              		.loc 1 318 5 view .LVU94
+ 287 016a 13F4007F 		tst	r3, #512
+ 288 016e 08D0     		beq	.L25
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+ 289              		.loc 1 321 5 is_stmt 1 view .LVU95
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the UART4 clock source */
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+ 290              		.loc 1 324 5 view .LVU96
+ 291 0170 5C4A     		ldr	r2, .L87
+ 292 0172 D2F89030 		ldr	r3, [r2, #144]
+ 293 0176 23F0C003 		bic	r3, r3, #192
+ 294 017a 216D     		ldr	r1, [r4, #80]
+ 295 017c 0B43     		orrs	r3, r3, r1
+ 296 017e C2F89030 		str	r3, [r2, #144]
+ 297              	.L25:
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- UART5 Configuration -----------------------------------*
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+ 298              		.loc 1 328 3 view .LVU97
+ARM GAS  /tmp/cc41FM7T.s 			page 12
+
+
+ 299              		.loc 1 328 21 is_stmt 0 view .LVU98
+ 300 0182 2368     		ldr	r3, [r4]
+ 301              		.loc 1 328 5 view .LVU99
+ 302 0184 13F4806F 		tst	r3, #1024
+ 303 0188 08D0     		beq	.L26
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+ 304              		.loc 1 331 5 is_stmt 1 view .LVU100
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the UART5 clock source */
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+ 305              		.loc 1 334 5 view .LVU101
+ 306 018a 564A     		ldr	r2, .L87
+ 307 018c D2F89030 		ldr	r3, [r2, #144]
+ 308 0190 23F44073 		bic	r3, r3, #768
+ 309 0194 616D     		ldr	r1, [r4, #84]
+ 310 0196 0B43     		orrs	r3, r3, r1
+ 311 0198 C2F89030 		str	r3, [r2, #144]
+ 312              	.L26:
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- USART6 Configuration -----------------------------------
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
+ 313              		.loc 1 338 3 view .LVU102
+ 314              		.loc 1 338 21 is_stmt 0 view .LVU103
+ 315 019c 2368     		ldr	r3, [r4]
+ 316              		.loc 1 338 5 view .LVU104
+ 317 019e 13F4006F 		tst	r3, #2048
+ 318 01a2 08D0     		beq	.L27
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
+ 319              		.loc 1 341 5 is_stmt 1 view .LVU105
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the USART6 clock source */
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
+ 320              		.loc 1 344 5 view .LVU106
+ 321 01a4 4F4A     		ldr	r2, .L87
+ 322 01a6 D2F89030 		ldr	r3, [r2, #144]
+ 323 01aa 23F44063 		bic	r3, r3, #3072
+ 324 01ae A16D     		ldr	r1, [r4, #88]
+ 325 01b0 0B43     		orrs	r3, r3, r1
+ 326 01b2 C2F89030 		str	r3, [r2, #144]
+ 327              	.L27:
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- UART7 Configuration -----------------------------------*
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
+ 328              		.loc 1 348 3 view .LVU107
+ 329              		.loc 1 348 21 is_stmt 0 view .LVU108
+ 330 01b6 2368     		ldr	r3, [r4]
+ 331              		.loc 1 348 5 view .LVU109
+ 332 01b8 13F4805F 		tst	r3, #4096
+ 333 01bc 08D0     		beq	.L28
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ARM GAS  /tmp/cc41FM7T.s 			page 13
+
+
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
+ 334              		.loc 1 351 5 is_stmt 1 view .LVU110
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the UART7 clock source */
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
+ 335              		.loc 1 354 5 view .LVU111
+ 336 01be 494A     		ldr	r2, .L87
+ 337 01c0 D2F89030 		ldr	r3, [r2, #144]
+ 338 01c4 23F44053 		bic	r3, r3, #12288
+ 339 01c8 E16D     		ldr	r1, [r4, #92]
+ 340 01ca 0B43     		orrs	r3, r3, r1
+ 341 01cc C2F89030 		str	r3, [r2, #144]
+ 342              	.L28:
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- UART8 Configuration -----------------------------------*
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
+ 343              		.loc 1 358 3 view .LVU112
+ 344              		.loc 1 358 21 is_stmt 0 view .LVU113
+ 345 01d0 2368     		ldr	r3, [r4]
+ 346              		.loc 1 358 5 view .LVU114
+ 347 01d2 13F4005F 		tst	r3, #8192
+ 348 01d6 08D0     		beq	.L29
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
+ 349              		.loc 1 361 5 is_stmt 1 view .LVU115
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the UART8 clock source */
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
+ 350              		.loc 1 364 5 view .LVU116
+ 351 01d8 424A     		ldr	r2, .L87
+ 352 01da D2F89030 		ldr	r3, [r2, #144]
+ 353 01de 23F44043 		bic	r3, r3, #49152
+ 354 01e2 216E     		ldr	r1, [r4, #96]
+ 355 01e4 0B43     		orrs	r3, r3, r1
+ 356 01e6 C2F89030 		str	r3, [r2, #144]
+ 357              	.L29:
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*--------------------------------------- CEC Configuration -----------------------------------*/
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+ 358              		.loc 1 368 3 view .LVU117
+ 359              		.loc 1 368 21 is_stmt 0 view .LVU118
+ 360 01ea 2368     		ldr	r3, [r4]
+ 361              		.loc 1 368 5 view .LVU119
+ 362 01ec 13F4800F 		tst	r3, #4194304
+ 363 01f0 08D0     		beq	.L30
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+ 364              		.loc 1 371 5 is_stmt 1 view .LVU120
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the CEC clock source */
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ 365              		.loc 1 374 5 view .LVU121
+ 366 01f2 3C4A     		ldr	r2, .L87
+ARM GAS  /tmp/cc41FM7T.s 			page 14
+
+
+ 367 01f4 D2F89030 		ldr	r3, [r2, #144]
+ 368 01f8 23F08063 		bic	r3, r3, #67108864
+ 369 01fc A16F     		ldr	r1, [r4, #120]
+ 370 01fe 0B43     		orrs	r3, r3, r1
+ 371 0200 C2F89030 		str	r3, [r2, #144]
+ 372              	.L30:
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- CK48 Configuration -----------------------------------*/
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+ 373              		.loc 1 378 3 view .LVU122
+ 374              		.loc 1 378 21 is_stmt 0 view .LVU123
+ 375 0204 2368     		ldr	r3, [r4]
+ 376              		.loc 1 378 5 view .LVU124
+ 377 0206 13F4001F 		tst	r3, #2097152
+ 378 020a 0DD0     		beq	.L31
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
+ 379              		.loc 1 381 5 is_stmt 1 view .LVU125
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the CLK48 source */
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+ 380              		.loc 1 384 5 view .LVU126
+ 381 020c 354A     		ldr	r2, .L87
+ 382 020e D2F89030 		ldr	r3, [r2, #144]
+ 383 0212 23F00063 		bic	r3, r3, #134217728
+ 384 0216 E16F     		ldr	r1, [r4, #124]
+ 385 0218 0B43     		orrs	r3, r3, r1
+ 386 021a C2F89030 		str	r3, [r2, #144]
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLSAI when it's used as clock source for CK48 */
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
+ 387              		.loc 1 387 5 view .LVU127
+ 388              		.loc 1 387 21 is_stmt 0 view .LVU128
+ 389 021e E36F     		ldr	r3, [r4, #124]
+ 390              		.loc 1 387 7 view .LVU129
+ 391 0220 B3F1006F 		cmp	r3, #134217728
+ 392 0224 00F0D580 		beq	.L78
+ 393              	.LVL9:
+ 394              	.L31:
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       pllsaiused = 1;
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- LTDC Configuration -----------------------------------*/
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) 
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+ 395              		.loc 1 395 3 is_stmt 1 view .LVU130
+ 396              		.loc 1 395 21 is_stmt 0 view .LVU131
+ 397 0228 2368     		ldr	r3, [r4]
+ 398              		.loc 1 395 5 view .LVU132
+ 399 022a 13F0080F 		tst	r3, #8
+ 400 022e 00D0     		beq	.L32
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     pllsaiused = 1;
+ARM GAS  /tmp/cc41FM7T.s 			page 15
+
+
+ 401              		.loc 1 397 16 view .LVU133
+ 402 0230 0125     		movs	r5, #1
+ 403              	.LVL10:
+ 404              	.L32:
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx ||
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- LPTIM1 Configuration -----------------------------------
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+ 405              		.loc 1 402 3 is_stmt 1 view .LVU134
+ 406              		.loc 1 402 5 is_stmt 0 view .LVU135
+ 407 0232 13F4802F 		tst	r3, #262144
+ 408 0236 08D0     		beq	.L33
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
+ 409              		.loc 1 405 5 is_stmt 1 view .LVU136
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the LTPIM1 clock source */
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+ 410              		.loc 1 408 5 view .LVU137
+ 411 0238 2A4A     		ldr	r2, .L87
+ 412 023a D2F89030 		ldr	r3, [r2, #144]
+ 413 023e 23F04073 		bic	r3, r3, #50331648
+ 414 0242 616F     		ldr	r1, [r4, #116]
+ 415 0244 0B43     		orrs	r3, r3, r1
+ 416 0246 C2F89030 		str	r3, [r2, #144]
+ 417              	.L33:
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****    }
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------- SDMMC1 Configuration ------------------------------------
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
+ 418              		.loc 1 412 3 view .LVU138
+ 419              		.loc 1 412 21 is_stmt 0 view .LVU139
+ 420 024a 2368     		ldr	r3, [r4]
+ 421              		.loc 1 412 5 view .LVU140
+ 422 024c 13F4000F 		tst	r3, #8388608
+ 423 0250 09D0     		beq	.L34
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
+ 424              		.loc 1 415 5 is_stmt 1 view .LVU141
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the SDMMC1 clock source */
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
+ 425              		.loc 1 418 5 view .LVU142
+ 426 0252 244A     		ldr	r2, .L87
+ 427 0254 D2F89030 		ldr	r3, [r2, #144]
+ 428 0258 23F08053 		bic	r3, r3, #268435456
+ 429 025c D4F88010 		ldr	r1, [r4, #128]
+ 430 0260 0B43     		orrs	r3, r3, r1
+ 431 0262 C2F89030 		str	r3, [r2, #144]
+ 432              	.L34:
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------- SDMMC2 Configuration ------------------------------------
+ARM GAS  /tmp/cc41FM7T.s 			page 16
+
+
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
+ 433              		.loc 1 423 3 view .LVU143
+ 434              		.loc 1 423 21 is_stmt 0 view .LVU144
+ 435 0266 2368     		ldr	r3, [r4]
+ 436              		.loc 1 423 5 view .LVU145
+ 437 0268 13F0806F 		tst	r3, #67108864
+ 438 026c 09D0     		beq	.L35
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
+ 439              		.loc 1 426 5 is_stmt 1 view .LVU146
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the SDMMC2 clock source */
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
+ 440              		.loc 1 429 5 view .LVU147
+ 441 026e 1D4A     		ldr	r2, .L87
+ 442 0270 D2F89030 		ldr	r3, [r2, #144]
+ 443 0274 23F00053 		bic	r3, r3, #536870912
+ 444 0278 D4F88410 		ldr	r1, [r4, #132]
+ 445 027c 0B43     		orrs	r3, r3, r1
+ 446 027e C2F89030 		str	r3, [r2, #144]
+ 447              	.L35:
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------- DFSDM1 Configuration ------------------------------------
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+ 448              		.loc 1 433 3 view .LVU148
+ 449              		.loc 1 433 21 is_stmt 0 view .LVU149
+ 450 0282 2368     		ldr	r3, [r4]
+ 451              		.loc 1 433 5 view .LVU150
+ 452 0284 13F0006F 		tst	r3, #134217728
+ 453 0288 09D0     		beq	.L36
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+ 454              		.loc 1 436 5 is_stmt 1 view .LVU151
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the DFSDM1 interface clock source */
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+ 455              		.loc 1 439 5 view .LVU152
+ 456 028a 164A     		ldr	r2, .L87
+ 457 028c D2F88C30 		ldr	r3, [r2, #140]
+ 458 0290 23F00073 		bic	r3, r3, #33554432
+ 459 0294 D4F88810 		ldr	r1, [r4, #136]
+ 460 0298 0B43     		orrs	r3, r3, r1
+ 461 029a C2F88C30 		str	r3, [r2, #140]
+ 462              	.L36:
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------- DFSDM AUDIO Configuration -------------------------------
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_A
+ 463              		.loc 1 443 3 view .LVU153
+ 464              		.loc 1 443 21 is_stmt 0 view .LVU154
+ 465 029e 2368     		ldr	r3, [r4]
+ 466              		.loc 1 443 5 view .LVU155
+ 467 02a0 13F0805F 		tst	r3, #268435456
+ 468 02a4 09D0     		beq	.L37
+ARM GAS  /tmp/cc41FM7T.s 			page 17
+
+
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
+ 469              		.loc 1 446 5 is_stmt 1 view .LVU156
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the DFSDM interface clock source */
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
+ 470              		.loc 1 449 5 view .LVU157
+ 471 02a6 0F4A     		ldr	r2, .L87
+ 472 02a8 D2F88C30 		ldr	r3, [r2, #140]
+ 473 02ac 23F08063 		bic	r3, r3, #67108864
+ 474 02b0 D4F88C10 		ldr	r1, [r4, #140]
+ 475 02b4 0B43     		orrs	r3, r3, r1
+ 476 02b6 C2F88C30 		str	r3, [r2, #140]
+ 477              	.L37:
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERI
+ 478              		.loc 1 455 3 view .LVU158
+ 479              		.loc 1 455 5 is_stmt 0 view .LVU159
+ 480 02ba 26B9     		cbnz	r6, .L38
+ 481              		.loc 1 455 42 discriminator 1 view .LVU160
+ 482 02bc 2368     		ldr	r3, [r4]
+ 483              		.loc 1 455 24 discriminator 1 view .LVU161
+ 484 02be 13F0007F 		tst	r3, #33554432
+ 485 02c2 00F00681 		beq	.L39
+ 486              	.L38:
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Disable the PLLI2S */
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_PLLI2S_DISABLE();
+ 487              		.loc 1 458 5 is_stmt 1 view .LVU162
+ 488 02c6 074A     		ldr	r2, .L87
+ 489 02c8 1368     		ldr	r3, [r2]
+ 490 02ca 23F08063 		bic	r3, r3, #67108864
+ 491 02ce 1360     		str	r3, [r2]
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Get Start Tick*/
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tickstart = HAL_GetTick();
+ 492              		.loc 1 461 5 view .LVU163
+ 493              		.loc 1 461 17 is_stmt 0 view .LVU164
+ 494 02d0 FFF7FEFF 		bl	HAL_GetTick
+ 495              	.LVL11:
+ 496 02d4 0646     		mov	r6, r0
+ 497              	.LVL12:
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Wait till PLLI2S is disabled */
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+ 498              		.loc 1 464 5 is_stmt 1 view .LVU165
+ 499              	.L40:
+ 500              		.loc 1 464 10 view .LVU166
+ 501              		.loc 1 464 11 is_stmt 0 view .LVU167
+ 502 02d6 034B     		ldr	r3, .L87
+ 503 02d8 1B68     		ldr	r3, [r3]
+ 504              		.loc 1 464 10 view .LVU168
+ARM GAS  /tmp/cc41FM7T.s 			page 18
+
+
+ 505 02da 13F0006F 		tst	r3, #134217728
+ 506 02de 7AD0     		beq	.L79
+ 507 02e0 02E0     		b	.L88
+ 508              	.L89:
+ 509 02e2 00BF     		.align	2
+ 510              	.L87:
+ 511 02e4 00380240 		.word	1073887232
+ 512              	.L88:
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ 513              		.loc 1 466 7 is_stmt 1 view .LVU169
+ 514              		.loc 1 466 11 is_stmt 0 view .LVU170
+ 515 02e8 FFF7FEFF 		bl	HAL_GetTick
+ 516              	.LVL13:
+ 517              		.loc 1 466 25 view .LVU171
+ 518 02ec 801B     		subs	r0, r0, r6
+ 519              		.loc 1 466 9 view .LVU172
+ 520 02ee 6428     		cmp	r0, #100
+ 521 02f0 F1D9     		bls	.L40
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* return in case of Timeout detected */
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         return HAL_TIMEOUT;
+ 522              		.loc 1 469 16 view .LVU173
+ 523 02f2 0320     		movs	r0, #3
+ 524 02f4 F0E0     		b	.L10
+ 525              	.LVL14:
+ 526              	.L59:
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 527              		.loc 1 128 18 view .LVU174
+ 528 02f6 0126     		movs	r6, #1
+ 529 02f8 97E6     		b	.L2
+ 530              	.LVL15:
+ 531              	.L75:
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 532              		.loc 1 143 18 view .LVU175
+ 533 02fa 0126     		movs	r6, #1
+ 534              	.LVL16:
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 535              		.loc 1 143 18 view .LVU176
+ 536 02fc A7E6     		b	.L4
+ 537              	.LVL17:
+ 538              	.L61:
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 539              		.loc 1 148 18 view .LVU177
+ 540 02fe 0125     		movs	r5, #1
+ 541 0300 A9E6     		b	.L3
+ 542              	.LVL18:
+ 543              	.L76:
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 544              		.loc 1 164 18 view .LVU178
+ 545 0302 0126     		movs	r6, #1
+ 546              	.LVL19:
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 547              		.loc 1 164 18 view .LVU179
+ 548 0304 B9E6     		b	.L6
+ 549              	.LVL20:
+ 550              	.L77:
+ARM GAS  /tmp/cc41FM7T.s 			page 19
+
+
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 551              		.loc 1 183 5 is_stmt 1 view .LVU180
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 552              		.loc 1 186 5 view .LVU181
+ 553              	.LBB2:
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 554              		.loc 1 186 5 view .LVU182
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 555              		.loc 1 186 5 view .LVU183
+ 556 0306 7F4B     		ldr	r3, .L90
+ 557 0308 1A6C     		ldr	r2, [r3, #64]
+ 558 030a 42F08052 		orr	r2, r2, #268435456
+ 559 030e 1A64     		str	r2, [r3, #64]
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 560              		.loc 1 186 5 view .LVU184
+ 561 0310 1B6C     		ldr	r3, [r3, #64]
+ 562 0312 03F08053 		and	r3, r3, #268435456
+ 563 0316 0193     		str	r3, [sp, #4]
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 564              		.loc 1 186 5 view .LVU185
+ 565 0318 019B     		ldr	r3, [sp, #4]
+ 566              	.LBE2:
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 567              		.loc 1 186 5 view .LVU186
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 568              		.loc 1 189 5 view .LVU187
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 569              		.loc 1 189 14 is_stmt 0 view .LVU188
+ 570 031a 7B4A     		ldr	r2, .L90+4
+ 571 031c 1368     		ldr	r3, [r2]
+ 572 031e 43F48073 		orr	r3, r3, #256
+ 573 0322 1360     		str	r3, [r2]
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 574              		.loc 1 192 5 is_stmt 1 view .LVU189
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 575              		.loc 1 192 17 is_stmt 0 view .LVU190
+ 576 0324 FFF7FEFF 		bl	HAL_GetTick
+ 577              	.LVL21:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 578              		.loc 1 192 17 view .LVU191
+ 579 0328 0746     		mov	r7, r0
+ 580              	.LVL22:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 581              		.loc 1 195 5 is_stmt 1 view .LVU192
+ 582              	.L9:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 583              		.loc 1 195 10 view .LVU193
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 584              		.loc 1 195 15 is_stmt 0 view .LVU194
+ 585 032a 774B     		ldr	r3, .L90+4
+ 586 032c 1B68     		ldr	r3, [r3]
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 587              		.loc 1 195 10 view .LVU195
+ 588 032e 13F4807F 		tst	r3, #256
+ 589 0332 06D1     		bne	.L80
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 590              		.loc 1 197 7 is_stmt 1 view .LVU196
+ARM GAS  /tmp/cc41FM7T.s 			page 20
+
+
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 591              		.loc 1 197 11 is_stmt 0 view .LVU197
+ 592 0334 FFF7FEFF 		bl	HAL_GetTick
+ 593              	.LVL23:
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 594              		.loc 1 197 25 view .LVU198
+ 595 0338 C01B     		subs	r0, r0, r7
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 596              		.loc 1 197 9 view .LVU199
+ 597 033a 6428     		cmp	r0, #100
+ 598 033c F5D9     		bls	.L9
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 599              		.loc 1 199 16 view .LVU200
+ 600 033e 0320     		movs	r0, #3
+ 601 0340 CAE0     		b	.L10
+ 602              	.L80:
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 603              		.loc 1 204 5 is_stmt 1 view .LVU201
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 604              		.loc 1 204 19 is_stmt 0 view .LVU202
+ 605 0342 704B     		ldr	r3, .L90
+ 606 0344 1B6F     		ldr	r3, [r3, #112]
+ 607              	.LVL24:
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 608              		.loc 1 206 5 is_stmt 1 view .LVU203
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 609              		.loc 1 206 7 is_stmt 0 view .LVU204
+ 610 0346 13F44073 		ands	r3, r3, #768
+ 611              	.LVL25:
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 612              		.loc 1 206 7 view .LVU205
+ 613 034a 15D0     		beq	.L12
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 614              		.loc 1 206 62 discriminator 1 view .LVU206
+ 615 034c 226B     		ldr	r2, [r4, #48]
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 616              		.loc 1 206 82 discriminator 1 view .LVU207
+ 617 034e 02F44072 		and	r2, r2, #768
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 618              		.loc 1 206 33 discriminator 1 view .LVU208
+ 619 0352 9A42     		cmp	r2, r3
+ 620 0354 10D0     		beq	.L12
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 621              		.loc 1 209 7 is_stmt 1 view .LVU209
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 622              		.loc 1 209 21 is_stmt 0 view .LVU210
+ 623 0356 6B4B     		ldr	r3, .L90
+ 624              	.LVL26:
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 625              		.loc 1 209 21 view .LVU211
+ 626 0358 1A6F     		ldr	r2, [r3, #112]
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 627              		.loc 1 209 15 view .LVU212
+ 628 035a 22F44072 		bic	r2, r2, #768
+ 629              	.LVL27:
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_BACKUPRESET_RELEASE();
+ 630              		.loc 1 212 7 is_stmt 1 view .LVU213
+ARM GAS  /tmp/cc41FM7T.s 			page 21
+
+
+ 631 035e 196F     		ldr	r1, [r3, #112]
+ 632 0360 41F48031 		orr	r1, r1, #65536
+ 633 0364 1967     		str	r1, [r3, #112]
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 634              		.loc 1 213 7 view .LVU214
+ 635 0366 196F     		ldr	r1, [r3, #112]
+ 636 0368 21F48031 		bic	r1, r1, #65536
+ 637 036c 1967     		str	r1, [r3, #112]
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 638              		.loc 1 216 7 view .LVU215
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 639              		.loc 1 216 17 is_stmt 0 view .LVU216
+ 640 036e 1A67     		str	r2, [r3, #112]
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 641              		.loc 1 219 7 is_stmt 1 view .LVU217
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 642              		.loc 1 219 11 is_stmt 0 view .LVU218
+ 643 0370 1B6F     		ldr	r3, [r3, #112]
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 644              		.loc 1 219 10 view .LVU219
+ 645 0372 13F0010F 		tst	r3, #1
+ 646 0376 12D1     		bne	.L81
+ 647              	.LVL28:
+ 648              	.L12:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 649              		.loc 1 234 5 is_stmt 1 view .LVU220
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 650              		.loc 1 234 5 view .LVU221
+ 651 0378 236B     		ldr	r3, [r4, #48]
+ 652 037a 03F44072 		and	r2, r3, #768
+ 653 037e B2F5407F 		cmp	r2, #768
+ 654 0382 1DD0     		beq	.L82
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 655              		.loc 1 234 5 is_stmt 0 discriminator 2 view .LVU222
+ 656 0384 5F4A     		ldr	r2, .L90
+ 657 0386 9368     		ldr	r3, [r2, #8]
+ 658 0388 23F4F813 		bic	r3, r3, #2031616
+ 659 038c 9360     		str	r3, [r2, #8]
+ 660              	.L16:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 661              		.loc 1 234 5 is_stmt 1 discriminator 4 view .LVU223
+ 662 038e 5D49     		ldr	r1, .L90
+ 663 0390 0B6F     		ldr	r3, [r1, #112]
+ 664 0392 226B     		ldr	r2, [r4, #48]
+ 665 0394 C2F30B02 		ubfx	r2, r2, #0, #12
+ 666 0398 1343     		orrs	r3, r3, r2
+ 667 039a 0B67     		str	r3, [r1, #112]
+ 668 039c 78E6     		b	.L8
+ 669              	.LVL29:
+ 670              	.L81:
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 671              		.loc 1 222 9 view .LVU224
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 672              		.loc 1 222 21 is_stmt 0 view .LVU225
+ 673 039e FFF7FEFF 		bl	HAL_GetTick
+ 674              	.LVL30:
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ARM GAS  /tmp/cc41FM7T.s 			page 22
+
+
+ 675              		.loc 1 222 21 view .LVU226
+ 676 03a2 0746     		mov	r7, r0
+ 677              	.LVL31:
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 678              		.loc 1 225 9 is_stmt 1 view .LVU227
+ 679              	.L13:
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 680              		.loc 1 225 14 view .LVU228
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 681              		.loc 1 225 15 is_stmt 0 view .LVU229
+ 682 03a4 574B     		ldr	r3, .L90
+ 683 03a6 1B6F     		ldr	r3, [r3, #112]
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 684              		.loc 1 225 14 view .LVU230
+ 685 03a8 13F0020F 		tst	r3, #2
+ 686 03ac E4D1     		bne	.L12
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           {
+ 687              		.loc 1 227 11 is_stmt 1 view .LVU231
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           {
+ 688              		.loc 1 227 15 is_stmt 0 view .LVU232
+ 689 03ae FFF7FEFF 		bl	HAL_GetTick
+ 690              	.LVL32:
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           {
+ 691              		.loc 1 227 29 view .LVU233
+ 692 03b2 C01B     		subs	r0, r0, r7
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           {
+ 693              		.loc 1 227 13 view .LVU234
+ 694 03b4 41F28833 		movw	r3, #5000
+ 695 03b8 9842     		cmp	r0, r3
+ 696 03ba F3D9     		bls	.L13
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           }
+ 697              		.loc 1 229 20 view .LVU235
+ 698 03bc 0320     		movs	r0, #3
+ 699 03be 8BE0     		b	.L10
+ 700              	.L82:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 701              		.loc 1 234 5 discriminator 1 view .LVU236
+ 702 03c0 5048     		ldr	r0, .L90
+ 703 03c2 8268     		ldr	r2, [r0, #8]
+ 704 03c4 22F4F812 		bic	r2, r2, #2031616
+ 705 03c8 5049     		ldr	r1, .L90+8
+ 706 03ca 1940     		ands	r1, r1, r3
+ 707 03cc 0A43     		orrs	r2, r2, r1
+ 708 03ce 8260     		str	r2, [r0, #8]
+ 709 03d0 DDE7     		b	.L16
+ 710              	.LVL33:
+ 711              	.L78:
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 712              		.loc 1 389 18 view .LVU237
+ 713 03d2 0125     		movs	r5, #1
+ 714              	.LVL34:
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 715              		.loc 1 389 18 view .LVU238
+ 716 03d4 28E7     		b	.L31
+ 717              	.LVL35:
+ 718              	.L79:
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ARM GAS  /tmp/cc41FM7T.s 			page 23
+
+
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* check for common PLLI2S Parameters */
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+ 719              		.loc 1 474 5 is_stmt 1 view .LVU239
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (Peri
+ 720              		.loc 1 477 5 view .LVU240
+ 721              		.loc 1 477 25 is_stmt 0 view .LVU241
+ 722 03d6 2368     		ldr	r3, [r4]
+ 723              		.loc 1 477 7 view .LVU242
+ 724 03d8 13F0010F 		tst	r3, #1
+ 725 03dc 13D0     		beq	.L42
+ 726              		.loc 1 477 109 discriminator 1 view .LVU243
+ 727 03de 636B     		ldr	r3, [r4, #52]
+ 728              		.loc 1 477 92 discriminator 1 view .LVU244
+ 729 03e0 8BB9     		cbnz	r3, .L42
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* check for Parameters */
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ 730              		.loc 1 480 7 is_stmt 1 view .LVU245
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S 
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
+ 731              		.loc 1 483 7 view .LVU246
+ 732              		.loc 1 483 22 is_stmt 0 view .LVU247
+ 733 03e2 484A     		ldr	r2, .L90
+ 734 03e4 D2F88430 		ldr	r3, [r2, #132]
+ 735              	.LVL36:
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ 736              		.loc 1 484 7 is_stmt 1 view .LVU248
+ 737              		.loc 1 484 22 is_stmt 0 view .LVU249
+ 738 03e8 D2F88410 		ldr	r1, [r2, #132]
+ 739              	.LVL37:
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Configure the PLLI2S division factors */
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI
+ 740              		.loc 1 488 7 is_stmt 1 view .LVU250
+ 741 03ec 6068     		ldr	r0, [r4, #4]
+ 742 03ee 03F44033 		and	r3, r3, #196608
+ 743              	.LVL38:
+ 744              		.loc 1 488 7 is_stmt 0 view .LVU251
+ 745 03f2 43EA8013 		orr	r3, r3, r0, lsl #6
+ 746 03f6 01F07061 		and	r1, r1, #251658240
+ 747              	.LVL39:
+ 748              		.loc 1 488 7 view .LVU252
+ 749 03fa 0B43     		orrs	r3, r3, r1
+ 750 03fc A168     		ldr	r1, [r4, #8]
+ 751 03fe 43EA0173 		orr	r3, r3, r1, lsl #28
+ 752 0402 C2F88430 		str	r3, [r2, #132]
+ 753              	.L42:
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (Pe
+ARM GAS  /tmp/cc41FM7T.s 			page 24
+
+
+ 754              		.loc 1 492 5 is_stmt 1 view .LVU253
+ 755              		.loc 1 492 25 is_stmt 0 view .LVU254
+ 756 0406 2368     		ldr	r3, [r4]
+ 757              		.loc 1 492 7 view .LVU255
+ 758 0408 13F4002F 		tst	r3, #524288
+ 759 040c 03D0     		beq	.L43
+ 760              		.loc 1 492 111 discriminator 1 view .LVU256
+ 761 040e E26B     		ldr	r2, [r4, #60]
+ 762              		.loc 1 492 94 discriminator 1 view .LVU257
+ 763 0410 B2F5801F 		cmp	r2, #1048576
+ 764 0414 06D0     		beq	.L44
+ 765              	.L43:
+ 766              		.loc 1 492 162 discriminator 3 view .LVU258
+ 767 0416 13F4801F 		tst	r3, #1048576
+ 768 041a 1ED0     		beq	.L45
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe
+ 769              		.loc 1 493 111 view .LVU259
+ 770 041c 236C     		ldr	r3, [r4, #64]
+ 771              		.loc 1 493 94 view .LVU260
+ 772 041e B3F5800F 		cmp	r3, #4194304
+ 773 0422 1AD1     		bne	.L45
+ 774              	.L44:
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Check for PLLI2S Parameters */
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ 775              		.loc 1 496 7 is_stmt 1 view .LVU261
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Check for PLLI2S/DIVQ parameters */
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+ 776              		.loc 1 498 7 view .LVU262
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
+ 777              		.loc 1 501 7 view .LVU263
+ 778              		.loc 1 501 22 is_stmt 0 view .LVU264
+ 779 0424 374A     		ldr	r2, .L90
+ 780 0426 D2F88430 		ldr	r3, [r2, #132]
+ 781              	.LVL40:
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ 782              		.loc 1 502 7 is_stmt 1 view .LVU265
+ 783              		.loc 1 502 22 is_stmt 0 view .LVU266
+ 784 042a D2F88410 		ldr	r1, [r2, #132]
+ 785              	.LVL41:
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Configure the PLLI2S division factors */
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ
+ 786              		.loc 1 507 7 is_stmt 1 view .LVU267
+ 787 042e 6068     		ldr	r0, [r4, #4]
+ 788 0430 03F44033 		and	r3, r3, #196608
+ 789              	.LVL42:
+ 790              		.loc 1 507 7 is_stmt 0 view .LVU268
+ 791 0434 43EA8013 		orr	r3, r3, r0, lsl #6
+ 792 0438 E068     		ldr	r0, [r4, #12]
+ 793 043a 43EA0063 		orr	r3, r3, r0, lsl #24
+ 794 043e 01F0E041 		and	r1, r1, #1879048192
+ 795              	.LVL43:
+ARM GAS  /tmp/cc41FM7T.s 			page 25
+
+
+ 796              		.loc 1 507 7 view .LVU269
+ 797 0442 0B43     		orrs	r3, r3, r1
+ 798 0444 C2F88430 		str	r3, [r2, #132]
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+ 799              		.loc 1 510 7 is_stmt 1 view .LVU270
+ 800 0448 D2F88C30 		ldr	r3, [r2, #140]
+ 801 044c 23F01F03 		bic	r3, r3, #31
+ 802 0450 616A     		ldr	r1, [r4, #36]
+ 803 0452 0139     		subs	r1, r1, #1
+ 804 0454 0B43     		orrs	r3, r3, r1
+ 805 0456 C2F88C30 		str	r3, [r2, #140]
+ 806              	.L45:
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX ----------------
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+ 807              		.loc 1 514 5 view .LVU271
+ 808              		.loc 1 514 23 is_stmt 0 view .LVU272
+ 809 045a 2368     		ldr	r3, [r4]
+ 810              		.loc 1 514 7 view .LVU273
+ 811 045c 13F0807F 		tst	r3, #16777216
+ 812 0460 11D0     		beq	.L46
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* check for Parameters */
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+ 813              		.loc 1 517 7 is_stmt 1 view .LVU274
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configur
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ 814              		.loc 1 520 7 view .LVU275
+ 815              		.loc 1 520 22 is_stmt 0 view .LVU276
+ 816 0462 284A     		ldr	r2, .L90
+ 817 0464 D2F88400 		ldr	r0, [r2, #132]
+ 818              	.LVL44:
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ 819              		.loc 1 521 7 is_stmt 1 view .LVU277
+ 820              		.loc 1 521 22 is_stmt 0 view .LVU278
+ 821 0468 D2F88410 		ldr	r1, [r2, #132]
+ 822              	.LVL45:
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Configure the PLLI2S division factors */
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg
+ 823              		.loc 1 525 7 is_stmt 1 view .LVU279
+ 824 046c 6668     		ldr	r6, [r4, #4]
+ 825              	.LVL46:
+ 826              		.loc 1 525 7 is_stmt 0 view .LVU280
+ 827 046e 2369     		ldr	r3, [r4, #16]
+ 828 0470 1B04     		lsls	r3, r3, #16
+ 829 0472 43EA8613 		orr	r3, r3, r6, lsl #6
+ 830 0476 00F07060 		and	r0, r0, #251658240
+ 831              	.LVL47:
+ 832              		.loc 1 525 7 view .LVU281
+ 833 047a 0343     		orrs	r3, r3, r0
+ 834 047c 01F0E041 		and	r1, r1, #1879048192
+ARM GAS  /tmp/cc41FM7T.s 			page 26
+
+
+ 835              	.LVL48:
+ 836              		.loc 1 525 7 view .LVU282
+ 837 0480 0B43     		orrs	r3, r3, r1
+ 838 0482 C2F88430 		str	r3, [r2, #132]
+ 839              	.L46:
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*----------------- In Case of PLLI2S is just selected  -----------------*/
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+ 840              		.loc 1 529 5 is_stmt 1 view .LVU283
+ 841              		.loc 1 529 22 is_stmt 0 view .LVU284
+ 842 0486 2368     		ldr	r3, [r4]
+ 843              		.loc 1 529 7 view .LVU285
+ 844 0488 13F0007F 		tst	r3, #33554432
+ 845 048c 0DD0     		beq	.L47
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Check for Parameters */
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+ 846              		.loc 1 532 7 is_stmt 1 view .LVU286
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+ 847              		.loc 1 533 7 view .LVU287
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ 848              		.loc 1 534 7 view .LVU288
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Configure the PLLI2S division factors */
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, Periph
+ 849              		.loc 1 539 7 view .LVU289
+ 850 048e 6268     		ldr	r2, [r4, #4]
+ 851 0490 2369     		ldr	r3, [r4, #16]
+ 852 0492 1B04     		lsls	r3, r3, #16
+ 853 0494 43EA8213 		orr	r3, r3, r2, lsl #6
+ 854 0498 E268     		ldr	r2, [r4, #12]
+ 855 049a 43EA0263 		orr	r3, r3, r2, lsl #24
+ 856 049e A268     		ldr	r2, [r4, #8]
+ 857 04a0 43EA0273 		orr	r3, r3, r2, lsl #28
+ 858 04a4 174A     		ldr	r2, .L90
+ 859 04a6 C2F88430 		str	r3, [r2, #132]
+ 860              	.L47:
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLI2S */
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_PLLI2S_ENABLE();
+ 861              		.loc 1 543 5 view .LVU290
+ 862 04aa 164A     		ldr	r2, .L90
+ 863 04ac 1368     		ldr	r3, [r2]
+ 864 04ae 43F08063 		orr	r3, r3, #67108864
+ 865 04b2 1360     		str	r3, [r2]
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Get Start Tick*/
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tickstart = HAL_GetTick();
+ 866              		.loc 1 546 5 view .LVU291
+ 867              		.loc 1 546 17 is_stmt 0 view .LVU292
+ 868 04b4 FFF7FEFF 		bl	HAL_GetTick
+ 869              	.LVL49:
+ 870 04b8 0646     		mov	r6, r0
+ARM GAS  /tmp/cc41FM7T.s 			page 27
+
+
+ 871              	.LVL50:
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Wait till PLLI2S is ready */
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+ 872              		.loc 1 549 5 is_stmt 1 view .LVU293
+ 873              	.L48:
+ 874              		.loc 1 549 10 view .LVU294
+ 875              		.loc 1 549 11 is_stmt 0 view .LVU295
+ 876 04ba 124B     		ldr	r3, .L90
+ 877 04bc 1B68     		ldr	r3, [r3]
+ 878              		.loc 1 549 10 view .LVU296
+ 879 04be 13F0006F 		tst	r3, #134217728
+ 880 04c2 06D1     		bne	.L39
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ 881              		.loc 1 551 7 is_stmt 1 view .LVU297
+ 882              		.loc 1 551 11 is_stmt 0 view .LVU298
+ 883 04c4 FFF7FEFF 		bl	HAL_GetTick
+ 884              	.LVL51:
+ 885              		.loc 1 551 25 view .LVU299
+ 886 04c8 801B     		subs	r0, r0, r6
+ 887              		.loc 1 551 9 view .LVU300
+ 888 04ca 6428     		cmp	r0, #100
+ 889 04cc F5D9     		bls	.L48
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* return in case of Timeout detected */
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         return HAL_TIMEOUT;
+ 890              		.loc 1 554 16 view .LVU301
+ 891 04ce 0320     		movs	r0, #3
+ 892 04d0 02E0     		b	.L10
+ 893              	.LVL52:
+ 894              	.L39:
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(pllsaiused == 1)
+ 895              		.loc 1 561 3 is_stmt 1 view .LVU302
+ 896              		.loc 1 561 5 is_stmt 0 view .LVU303
+ 897 04d2 012D     		cmp	r5, #1
+ 898 04d4 02D0     		beq	.L83
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Disable PLLSAI Clock */
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_PLLSAI_DISABLE();
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Get Start Tick*/
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tickstart = HAL_GetTick();
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Wait till PLLSAI is disabled */
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* return in case of Timeout detected */
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         return HAL_TIMEOUT;
+ARM GAS  /tmp/cc41FM7T.s 			page 28
+
+
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the PLLSAI division factors */
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (Pe
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* check for PLLSAIQ Parameter */
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* check for PLLSAI/DIVQ Parameter */
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuratio
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAI
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* In Case of PLLI2S is selected as source clock for CK48 */
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (P
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* check for Parameters */
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Configure the PLLSAI division factors */
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) 
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*---------------------------- LTDC configuration -------------------------------*/
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LT
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+ARM GAS  /tmp/cc41FM7T.s 			page 29
+
+
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLS
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx ||
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable PLLSAI Clock */
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_PLLSAI_ENABLE();
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Get Start Tick*/
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tickstart = HAL_GetTick();
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Wait till PLLSAI is ready */
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* return in case of Timeout detected */
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         return HAL_TIMEOUT;
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   return HAL_OK;
+ 899              		.loc 1 656 10 view .LVU304
+ 900 04d6 0020     		movs	r0, #0
+ 901              	.LVL53:
+ 902              	.L10:
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ 903              		.loc 1 657 1 view .LVU305
+ 904 04d8 03B0     		add	sp, sp, #12
+ 905              	.LCFI2:
+ 906              		.cfi_remember_state
+ 907              		.cfi_def_cfa_offset 20
+ 908              		@ sp needed
+ 909 04da F0BD     		pop	{r4, r5, r6, r7, pc}
+ 910              	.LVL54:
+ 911              	.L83:
+ 912              	.LCFI3:
+ 913              		.cfi_restore_state
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 914              		.loc 1 564 5 is_stmt 1 view .LVU306
+ 915 04dc 094A     		ldr	r2, .L90
+ 916 04de 1368     		ldr	r3, [r2]
+ 917 04e0 23F08053 		bic	r3, r3, #268435456
+ 918 04e4 1360     		str	r3, [r2]
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 919              		.loc 1 567 5 view .LVU307
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 920              		.loc 1 567 17 is_stmt 0 view .LVU308
+ 921 04e6 FFF7FEFF 		bl	HAL_GetTick
+ 922              	.LVL55:
+ 923 04ea 0546     		mov	r5, r0
+ 924              	.LVL56:
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 925              		.loc 1 570 5 is_stmt 1 view .LVU309
+ 926              	.L50:
+ARM GAS  /tmp/cc41FM7T.s 			page 30
+
+
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 927              		.loc 1 570 10 view .LVU310
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 928              		.loc 1 570 11 is_stmt 0 view .LVU311
+ 929 04ec 054B     		ldr	r3, .L90
+ 930 04ee 1B68     		ldr	r3, [r3]
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 931              		.loc 1 570 10 view .LVU312
+ 932 04f0 13F0005F 		tst	r3, #536870912
+ 933 04f4 0CD0     		beq	.L84
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 934              		.loc 1 572 7 is_stmt 1 view .LVU313
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 935              		.loc 1 572 11 is_stmt 0 view .LVU314
+ 936 04f6 FFF7FEFF 		bl	HAL_GetTick
+ 937              	.LVL57:
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 938              		.loc 1 572 25 view .LVU315
+ 939 04fa 401B     		subs	r0, r0, r5
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 940              		.loc 1 572 9 view .LVU316
+ 941 04fc 6428     		cmp	r0, #100
+ 942 04fe F5D9     		bls	.L50
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 943              		.loc 1 575 16 view .LVU317
+ 944 0500 0320     		movs	r0, #3
+ 945 0502 E9E7     		b	.L10
+ 946              	.L91:
+ 947              		.align	2
+ 948              	.L90:
+ 949 0504 00380240 		.word	1073887232
+ 950 0508 00700040 		.word	1073770496
+ 951 050c FFFCFF0F 		.word	268434687
+ 952              	.L84:
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 953              		.loc 1 580 5 is_stmt 1 view .LVU318
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe
+ 954              		.loc 1 583 5 view .LVU319
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe
+ 955              		.loc 1 583 25 is_stmt 0 view .LVU320
+ 956 0510 2368     		ldr	r3, [r4]
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe
+ 957              		.loc 1 583 7 view .LVU321
+ 958 0512 13F4002F 		tst	r3, #524288
+ 959 0516 01D0     		beq	.L52
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe
+ 960              		.loc 1 583 111 discriminator 1 view .LVU322
+ 961 0518 E26B     		ldr	r2, [r4, #60]
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe
+ 962              		.loc 1 583 94 discriminator 1 view .LVU323
+ 963 051a 22B1     		cbz	r2, .L53
+ 964              	.L52:
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe
+ 965              		.loc 1 583 162 discriminator 3 view .LVU324
+ 966 051c 13F4801F 		tst	r3, #1048576
+ 967 0520 1DD0     		beq	.L54
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ARM GAS  /tmp/cc41FM7T.s 			page 31
+
+
+ 968              		.loc 1 584 111 view .LVU325
+ 969 0522 236C     		ldr	r3, [r4, #64]
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 970              		.loc 1 584 94 view .LVU326
+ 971 0524 DBB9     		cbnz	r3, .L54
+ 972              	.L53:
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* check for PLLSAI/DIVQ Parameter */
+ 973              		.loc 1 587 7 is_stmt 1 view .LVU327
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 974              		.loc 1 589 7 view .LVU328
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ 975              		.loc 1 592 7 view .LVU329
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ 976              		.loc 1 592 22 is_stmt 0 view .LVU330
+ 977 0526 354A     		ldr	r2, .L92
+ 978 0528 D2F88830 		ldr	r3, [r2, #136]
+ 979              	.LVL58:
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+ 980              		.loc 1 593 7 is_stmt 1 view .LVU331
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+ 981              		.loc 1 593 22 is_stmt 0 view .LVU332
+ 982 052c D2F88810 		ldr	r1, [r2, #136]
+ 983              	.LVL59:
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 984              		.loc 1 597 7 is_stmt 1 view .LVU333
+ 985 0530 6069     		ldr	r0, [r4, #20]
+ 986 0532 03F44033 		and	r3, r3, #196608
+ 987              	.LVL60:
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 988              		.loc 1 597 7 is_stmt 0 view .LVU334
+ 989 0536 43EA8013 		orr	r3, r3, r0, lsl #6
+ 990 053a A069     		ldr	r0, [r4, #24]
+ 991 053c 43EA0063 		orr	r3, r3, r0, lsl #24
+ 992 0540 01F0E041 		and	r1, r1, #1879048192
+ 993              	.LVL61:
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 994              		.loc 1 597 7 view .LVU335
+ 995 0544 0B43     		orrs	r3, r3, r1
+ 996 0546 C2F88830 		str	r3, [r2, #136]
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 997              		.loc 1 600 7 is_stmt 1 view .LVU336
+ 998 054a D2F88C30 		ldr	r3, [r2, #140]
+ 999 054e 23F4F853 		bic	r3, r3, #7936
+ 1000 0552 A16A     		ldr	r1, [r4, #40]
+ 1001 0554 0139     		subs	r1, r1, #1
+ 1002 0556 43EA0123 		orr	r3, r3, r1, lsl #8
+ 1003 055a C2F88C30 		str	r3, [r2, #140]
+ 1004              	.L54:
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1005              		.loc 1 605 5 view .LVU337
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1006              		.loc 1 605 24 is_stmt 0 view .LVU338
+ 1007 055e 2368     		ldr	r3, [r4]
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1008              		.loc 1 605 7 view .LVU339
+ 1009 0560 13F4001F 		tst	r3, #2097152
+ 1010 0564 03D0     		beq	.L55
+ARM GAS  /tmp/cc41FM7T.s 			page 32
+
+
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1011              		.loc 1 605 112 discriminator 1 view .LVU340
+ 1012 0566 E36F     		ldr	r3, [r4, #124]
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1013              		.loc 1 605 95 discriminator 1 view .LVU341
+ 1014 0568 B3F1006F 		cmp	r3, #134217728
+ 1015 056c 31D0     		beq	.L85
+ 1016              	.LVL62:
+ 1017              	.L55:
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1018              		.loc 1 621 5 is_stmt 1 view .LVU342
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1019              		.loc 1 621 23 is_stmt 0 view .LVU343
+ 1020 056e 2368     		ldr	r3, [r4]
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1021              		.loc 1 621 7 view .LVU344
+ 1022 0570 13F0080F 		tst	r3, #8
+ 1023 0574 19D0     		beq	.L56
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+ 1024              		.loc 1 623 7 is_stmt 1 view .LVU345
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1025              		.loc 1 624 7 view .LVU346
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+ 1026              		.loc 1 627 7 view .LVU347
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+ 1027              		.loc 1 627 22 is_stmt 0 view .LVU348
+ 1028 0576 214A     		ldr	r2, .L92
+ 1029 0578 D2F88810 		ldr	r1, [r2, #136]
+ 1030              	.LVL63:
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1031              		.loc 1 628 7 is_stmt 1 view .LVU349
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1032              		.loc 1 628 22 is_stmt 0 view .LVU350
+ 1033 057c D2F88830 		ldr	r3, [r2, #136]
+ 1034              	.LVL64:
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1035              		.loc 1 633 7 is_stmt 1 view .LVU351
+ 1036 0580 6069     		ldr	r0, [r4, #20]
+ 1037 0582 03F44033 		and	r3, r3, #196608
+ 1038              	.LVL65:
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1039              		.loc 1 633 7 is_stmt 0 view .LVU352
+ 1040 0586 43EA8013 		orr	r3, r3, r0, lsl #6
+ 1041 058a 01F07061 		and	r1, r1, #251658240
+ 1042              	.LVL66:
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1043              		.loc 1 633 7 view .LVU353
+ 1044 058e 0B43     		orrs	r3, r3, r1
+ 1045 0590 E169     		ldr	r1, [r4, #28]
+ 1046 0592 43EA0173 		orr	r3, r3, r1, lsl #28
+ 1047 0596 C2F88830 		str	r3, [r2, #136]
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 1048              		.loc 1 636 7 is_stmt 1 view .LVU354
+ 1049 059a D2F88C30 		ldr	r3, [r2, #140]
+ 1050 059e 23F44033 		bic	r3, r3, #196608
+ 1051 05a2 E16A     		ldr	r1, [r4, #44]
+ 1052 05a4 0B43     		orrs	r3, r3, r1
+ARM GAS  /tmp/cc41FM7T.s 			page 33
+
+
+ 1053 05a6 C2F88C30 		str	r3, [r2, #140]
+ 1054              	.L56:
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1055              		.loc 1 641 5 view .LVU355
+ 1056 05aa 144A     		ldr	r2, .L92
+ 1057 05ac 1368     		ldr	r3, [r2]
+ 1058 05ae 43F08053 		orr	r3, r3, #268435456
+ 1059 05b2 1360     		str	r3, [r2]
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1060              		.loc 1 644 5 view .LVU356
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1061              		.loc 1 644 17 is_stmt 0 view .LVU357
+ 1062 05b4 FFF7FEFF 		bl	HAL_GetTick
+ 1063              	.LVL67:
+ 1064 05b8 0446     		mov	r4, r0
+ 1065              	.LVL68:
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1066              		.loc 1 647 5 is_stmt 1 view .LVU358
+ 1067              	.L57:
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1068              		.loc 1 647 10 view .LVU359
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1069              		.loc 1 647 11 is_stmt 0 view .LVU360
+ 1070 05ba 104B     		ldr	r3, .L92
+ 1071 05bc 1B68     		ldr	r3, [r3]
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1072              		.loc 1 647 10 view .LVU361
+ 1073 05be 13F0005F 		tst	r3, #536870912
+ 1074 05c2 19D1     		bne	.L86
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 1075              		.loc 1 649 7 is_stmt 1 view .LVU362
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 1076              		.loc 1 649 11 is_stmt 0 view .LVU363
+ 1077 05c4 FFF7FEFF 		bl	HAL_GetTick
+ 1078              	.LVL69:
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 1079              		.loc 1 649 25 view .LVU364
+ 1080 05c8 001B     		subs	r0, r0, r4
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 1081              		.loc 1 649 9 view .LVU365
+ 1082 05ca 6428     		cmp	r0, #100
+ 1083 05cc F5D9     		bls	.L57
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 1084              		.loc 1 652 16 view .LVU366
+ 1085 05ce 0320     		movs	r0, #3
+ 1086 05d0 82E7     		b	.L10
+ 1087              	.LVL70:
+ 1088              	.L85:
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48
+ 1089              		.loc 1 608 7 is_stmt 1 view .LVU367
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ 1090              		.loc 1 610 7 view .LVU368
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ 1091              		.loc 1 610 22 is_stmt 0 view .LVU369
+ 1092 05d2 0A4A     		ldr	r2, .L92
+ 1093 05d4 D2F88800 		ldr	r0, [r2, #136]
+ 1094              	.LVL71:
+ARM GAS  /tmp/cc41FM7T.s 			page 34
+
+
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1095              		.loc 1 611 7 is_stmt 1 view .LVU370
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1096              		.loc 1 611 22 is_stmt 0 view .LVU371
+ 1097 05d8 D2F88810 		ldr	r1, [r2, #136]
+ 1098              	.LVL72:
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 1099              		.loc 1 616 7 is_stmt 1 view .LVU372
+ 1100 05dc 6569     		ldr	r5, [r4, #20]
+ 1101              	.LVL73:
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 1102              		.loc 1 616 7 is_stmt 0 view .LVU373
+ 1103 05de 236A     		ldr	r3, [r4, #32]
+ 1104 05e0 1B04     		lsls	r3, r3, #16
+ 1105 05e2 43EA8513 		orr	r3, r3, r5, lsl #6
+ 1106 05e6 00F07060 		and	r0, r0, #251658240
+ 1107              	.LVL74:
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 1108              		.loc 1 616 7 view .LVU374
+ 1109 05ea 0343     		orrs	r3, r3, r0
+ 1110 05ec 01F0E041 		and	r1, r1, #1879048192
+ 1111              	.LVL75:
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 1112              		.loc 1 616 7 view .LVU375
+ 1113 05f0 0B43     		orrs	r3, r3, r1
+ 1114 05f2 C2F88830 		str	r3, [r2, #136]
+ 1115 05f6 BAE7     		b	.L55
+ 1116              	.LVL76:
+ 1117              	.L86:
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ 1118              		.loc 1 656 10 view .LVU376
+ 1119 05f8 0020     		movs	r0, #0
+ 1120 05fa 6DE7     		b	.L10
+ 1121              	.L93:
+ 1122              		.align	2
+ 1123              	.L92:
+ 1124 05fc 00380240 		.word	1073887232
+ 1125              		.cfi_endproc
+ 1126              	.LFE141:
+ 1128              		.section	.text.HAL_RCCEx_GetPeriphCLKConfig,"ax",%progbits
+ 1129              		.align	1
+ 1130              		.global	HAL_RCCEx_GetPeriphCLKConfig
+ 1131              		.syntax unified
+ 1132              		.thumb
+ 1133              		.thumb_func
+ 1134              		.fpu fpv5-d16
+ 1136              	HAL_RCCEx_GetPeriphCLKConfig:
+ 1137              	.LVL77:
+ 1138              	.LFB142:
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         RCC configuration registers.
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @param  PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @retval None
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+ARM GAS  /tmp/cc41FM7T.s 			page 35
+
+
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** {
+ 1139              		.loc 1 666 1 is_stmt 1 view -0
+ 1140              		.cfi_startproc
+ 1141              		@ args = 0, pretend = 0, frame = 0
+ 1142              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1143              		@ link register save eliminated.
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tempreg = 0;
+ 1144              		.loc 1 667 3 view .LVU378
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Set all possible values for the extended clock type parameter------------*/
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\
+ 1145              		.loc 1 671 3 view .LVU379
+ 1146              		.loc 1 671 39 is_stmt 0 view .LVU380
+ 1147 0000 5F4B     		ldr	r3, .L97
+ 1148 0002 0360     		str	r3, [r0]
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_CLK48    | RCC_PERIPHCLK_SDMMC2   |\
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_DFSDM1   | RCC_PERIPHCLK_DFSDM1_AUDIO;
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #else
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_CLK48;
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI
+ 1149              		.loc 1 698 3 is_stmt 1 view .LVU381
+ 1150              		.loc 1 698 50 is_stmt 0 view .LVU382
+ 1151 0004 5F4B     		ldr	r3, .L97+4
+ 1152 0006 D3F88420 		ldr	r2, [r3, #132]
+ 1153              		.loc 1 698 35 view .LVU383
+ 1154 000a C2F38812 		ubfx	r2, r2, #6, #9
+ 1155              		.loc 1 698 33 view .LVU384
+ 1156 000e 4260     		str	r2, [r0, #4]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI
+ 1157              		.loc 1 699 3 is_stmt 1 view .LVU385
+ 1158              		.loc 1 699 50 is_stmt 0 view .LVU386
+ 1159 0010 D3F88420 		ldr	r2, [r3, #132]
+ 1160              		.loc 1 699 35 view .LVU387
+ 1161 0014 C2F30142 		ubfx	r2, r2, #16, #2
+ARM GAS  /tmp/cc41FM7T.s 			page 36
+
+
+ 1162              		.loc 1 699 33 view .LVU388
+ 1163 0018 0261     		str	r2, [r0, #16]
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI
+ 1164              		.loc 1 700 3 is_stmt 1 view .LVU389
+ 1165              		.loc 1 700 50 is_stmt 0 view .LVU390
+ 1166 001a D3F88420 		ldr	r2, [r3, #132]
+ 1167              		.loc 1 700 35 view .LVU391
+ 1168 001e C2F30362 		ubfx	r2, r2, #24, #4
+ 1169              		.loc 1 700 33 view .LVU392
+ 1170 0022 C260     		str	r2, [r0, #12]
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI
+ 1171              		.loc 1 701 3 is_stmt 1 view .LVU393
+ 1172              		.loc 1 701 50 is_stmt 0 view .LVU394
+ 1173 0024 D3F88420 		ldr	r2, [r3, #132]
+ 1174              		.loc 1 701 35 view .LVU395
+ 1175 0028 C2F30272 		ubfx	r2, r2, #28, #3
+ 1176              		.loc 1 701 33 view .LVU396
+ 1177 002c 8260     		str	r2, [r0, #8]
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the PLLSAI Clock configuration -----------------------------------------------*/
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLS
+ 1178              		.loc 1 704 3 is_stmt 1 view .LVU397
+ 1179              		.loc 1 704 50 is_stmt 0 view .LVU398
+ 1180 002e D3F88820 		ldr	r2, [r3, #136]
+ 1181              		.loc 1 704 35 view .LVU399
+ 1182 0032 C2F38812 		ubfx	r2, r2, #6, #9
+ 1183              		.loc 1 704 33 view .LVU400
+ 1184 0036 4261     		str	r2, [r0, #20]
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLS
+ 1185              		.loc 1 705 3 is_stmt 1 view .LVU401
+ 1186              		.loc 1 705 50 is_stmt 0 view .LVU402
+ 1187 0038 D3F88820 		ldr	r2, [r3, #136]
+ 1188              		.loc 1 705 35 view .LVU403
+ 1189 003c C2F30142 		ubfx	r2, r2, #16, #2
+ 1190              		.loc 1 705 33 view .LVU404
+ 1191 0040 0262     		str	r2, [r0, #32]
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLS
+ 1192              		.loc 1 706 3 is_stmt 1 view .LVU405
+ 1193              		.loc 1 706 50 is_stmt 0 view .LVU406
+ 1194 0042 D3F88820 		ldr	r2, [r3, #136]
+ 1195              		.loc 1 706 35 view .LVU407
+ 1196 0046 C2F30362 		ubfx	r2, r2, #24, #4
+ 1197              		.loc 1 706 33 view .LVU408
+ 1198 004a 8261     		str	r2, [r0, #24]
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLS
+ 1199              		.loc 1 707 3 is_stmt 1 view .LVU409
+ 1200              		.loc 1 707 50 is_stmt 0 view .LVU410
+ 1201 004c D3F88820 		ldr	r2, [r3, #136]
+ 1202              		.loc 1 707 35 view .LVU411
+ 1203 0050 C2F30272 		ubfx	r2, r2, #28, #3
+ 1204              		.loc 1 707 33 view .LVU412
+ 1205 0054 C261     		str	r2, [r0, #28]
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_
+ 1206              		.loc 1 710 3 is_stmt 1 view .LVU413
+ 1207              		.loc 1 710 46 is_stmt 0 view .LVU414
+ARM GAS  /tmp/cc41FM7T.s 			page 37
+
+
+ 1208 0056 D3F88C20 		ldr	r2, [r3, #140]
+ 1209              		.loc 1 710 31 view .LVU415
+ 1210 005a 02F01F02 		and	r2, r2, #31
+ 1211              		.loc 1 710 29 view .LVU416
+ 1212 005e 4262     		str	r2, [r0, #36]
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_
+ 1213              		.loc 1 711 3 is_stmt 1 view .LVU417
+ 1214              		.loc 1 711 46 is_stmt 0 view .LVU418
+ 1215 0060 D3F88C20 		ldr	r2, [r3, #140]
+ 1216              		.loc 1 711 31 view .LVU419
+ 1217 0064 C2F30422 		ubfx	r2, r2, #8, #5
+ 1218              		.loc 1 711 29 view .LVU420
+ 1219 0068 8262     		str	r2, [r0, #40]
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_
+ 1220              		.loc 1 712 3 is_stmt 1 view .LVU421
+ 1221              		.loc 1 712 46 is_stmt 0 view .LVU422
+ 1222 006a D3F88C20 		ldr	r2, [r3, #140]
+ 1223              		.loc 1 712 31 view .LVU423
+ 1224 006e C2F30142 		ubfx	r2, r2, #16, #2
+ 1225              		.loc 1 712 29 view .LVU424
+ 1226 0072 C262     		str	r2, [r0, #44]
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the SAI1 clock configuration ----------------------------------------------*/
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+ 1227              		.loc 1 715 3 is_stmt 1 view .LVU425
+ 1228              		.loc 1 715 39 is_stmt 0 view .LVU426
+ 1229 0074 D3F88C20 		ldr	r2, [r3, #140]
+ 1230 0078 02F44012 		and	r2, r2, #3145728
+ 1231              		.loc 1 715 37 view .LVU427
+ 1232 007c C263     		str	r2, [r0, #60]
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the SAI2 clock configuration ----------------------------------------------*/
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+ 1233              		.loc 1 718 3 is_stmt 1 view .LVU428
+ 1234              		.loc 1 718 39 is_stmt 0 view .LVU429
+ 1235 007e D3F88C20 		ldr	r2, [r3, #140]
+ 1236 0082 02F44002 		and	r2, r2, #12582912
+ 1237              		.loc 1 718 37 view .LVU430
+ 1238 0086 0264     		str	r2, [r0, #64]
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the I2S clock configuration ------------------------------------------*/
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
+ 1239              		.loc 1 721 3 is_stmt 1 view .LVU431
+ 1240              		.loc 1 721 38 is_stmt 0 view .LVU432
+ 1241 0088 9A68     		ldr	r2, [r3, #8]
+ 1242 008a 02F40002 		and	r2, r2, #8388608
+ 1243              		.loc 1 721 36 view .LVU433
+ 1244 008e 4263     		str	r2, [r0, #52]
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the I2C1 clock configuration ------------------------------------------*/
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+ 1245              		.loc 1 724 3 is_stmt 1 view .LVU434
+ 1246              		.loc 1 724 39 is_stmt 0 view .LVU435
+ 1247 0090 D3F89020 		ldr	r2, [r3, #144]
+ 1248 0094 02F44032 		and	r2, r2, #196608
+ 1249              		.loc 1 724 37 view .LVU436
+ 1250 0098 4266     		str	r2, [r0, #100]
+ARM GAS  /tmp/cc41FM7T.s 			page 38
+
+
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the I2C2 clock configuration ------------------------------------------*/
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
+ 1251              		.loc 1 727 3 is_stmt 1 view .LVU437
+ 1252              		.loc 1 727 39 is_stmt 0 view .LVU438
+ 1253 009a D3F89020 		ldr	r2, [r3, #144]
+ 1254 009e 02F44022 		and	r2, r2, #786432
+ 1255              		.loc 1 727 37 view .LVU439
+ 1256 00a2 8266     		str	r2, [r0, #104]
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the I2C3 clock configuration ------------------------------------------*/
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
+ 1257              		.loc 1 730 3 is_stmt 1 view .LVU440
+ 1258              		.loc 1 730 39 is_stmt 0 view .LVU441
+ 1259 00a4 D3F89020 		ldr	r2, [r3, #144]
+ 1260 00a8 02F44012 		and	r2, r2, #3145728
+ 1261              		.loc 1 730 37 view .LVU442
+ 1262 00ac C266     		str	r2, [r0, #108]
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the I2C4 clock configuration ------------------------------------------*/
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
+ 1263              		.loc 1 733 3 is_stmt 1 view .LVU443
+ 1264              		.loc 1 733 39 is_stmt 0 view .LVU444
+ 1265 00ae D3F89020 		ldr	r2, [r3, #144]
+ 1266 00b2 02F44002 		and	r2, r2, #12582912
+ 1267              		.loc 1 733 37 view .LVU445
+ 1268 00b6 0267     		str	r2, [r0, #112]
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the USART1 clock configuration ------------------------------------------*/
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+ 1269              		.loc 1 736 3 is_stmt 1 view .LVU446
+ 1270              		.loc 1 736 41 is_stmt 0 view .LVU447
+ 1271 00b8 D3F89020 		ldr	r2, [r3, #144]
+ 1272 00bc 02F00302 		and	r2, r2, #3
+ 1273              		.loc 1 736 39 view .LVU448
+ 1274 00c0 4264     		str	r2, [r0, #68]
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the USART2 clock configuration ------------------------------------------*/
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
+ 1275              		.loc 1 739 3 is_stmt 1 view .LVU449
+ 1276              		.loc 1 739 41 is_stmt 0 view .LVU450
+ 1277 00c2 D3F89020 		ldr	r2, [r3, #144]
+ 1278 00c6 02F00C02 		and	r2, r2, #12
+ 1279              		.loc 1 739 39 view .LVU451
+ 1280 00ca 8264     		str	r2, [r0, #72]
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the USART3 clock configuration ------------------------------------------*/
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
+ 1281              		.loc 1 742 3 is_stmt 1 view .LVU452
+ 1282              		.loc 1 742 41 is_stmt 0 view .LVU453
+ 1283 00cc D3F89020 		ldr	r2, [r3, #144]
+ 1284 00d0 02F03002 		and	r2, r2, #48
+ 1285              		.loc 1 742 39 view .LVU454
+ 1286 00d4 C264     		str	r2, [r0, #76]
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the UART4 clock configuration ------------------------------------------*/
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
+ARM GAS  /tmp/cc41FM7T.s 			page 39
+
+
+ 1287              		.loc 1 745 3 is_stmt 1 view .LVU455
+ 1288              		.loc 1 745 40 is_stmt 0 view .LVU456
+ 1289 00d6 D3F89020 		ldr	r2, [r3, #144]
+ 1290 00da 02F0C002 		and	r2, r2, #192
+ 1291              		.loc 1 745 38 view .LVU457
+ 1292 00de 0265     		str	r2, [r0, #80]
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the UART5 clock configuration ------------------------------------------*/
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
+ 1293              		.loc 1 748 3 is_stmt 1 view .LVU458
+ 1294              		.loc 1 748 40 is_stmt 0 view .LVU459
+ 1295 00e0 D3F89020 		ldr	r2, [r3, #144]
+ 1296 00e4 02F44072 		and	r2, r2, #768
+ 1297              		.loc 1 748 38 view .LVU460
+ 1298 00e8 4265     		str	r2, [r0, #84]
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the USART6 clock configuration ------------------------------------------*/
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
+ 1299              		.loc 1 751 3 is_stmt 1 view .LVU461
+ 1300              		.loc 1 751 41 is_stmt 0 view .LVU462
+ 1301 00ea D3F89020 		ldr	r2, [r3, #144]
+ 1302 00ee 02F44062 		and	r2, r2, #3072
+ 1303              		.loc 1 751 39 view .LVU463
+ 1304 00f2 8265     		str	r2, [r0, #88]
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the UART7 clock configuration ------------------------------------------*/
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
+ 1305              		.loc 1 754 3 is_stmt 1 view .LVU464
+ 1306              		.loc 1 754 40 is_stmt 0 view .LVU465
+ 1307 00f4 D3F89020 		ldr	r2, [r3, #144]
+ 1308 00f8 02F44052 		and	r2, r2, #12288
+ 1309              		.loc 1 754 38 view .LVU466
+ 1310 00fc C265     		str	r2, [r0, #92]
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the UART8 clock configuration ------------------------------------------*/
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
+ 1311              		.loc 1 757 3 is_stmt 1 view .LVU467
+ 1312              		.loc 1 757 40 is_stmt 0 view .LVU468
+ 1313 00fe D3F89020 		ldr	r2, [r3, #144]
+ 1314 0102 02F44042 		and	r2, r2, #49152
+ 1315              		.loc 1 757 38 view .LVU469
+ 1316 0106 0266     		str	r2, [r0, #96]
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the LPTIM1 clock configuration ------------------------------------------*/
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
+ 1317              		.loc 1 760 3 is_stmt 1 view .LVU470
+ 1318              		.loc 1 760 41 is_stmt 0 view .LVU471
+ 1319 0108 D3F89020 		ldr	r2, [r3, #144]
+ 1320 010c 02F04072 		and	r2, r2, #50331648
+ 1321              		.loc 1 760 39 view .LVU472
+ 1322 0110 4267     		str	r2, [r0, #116]
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the CEC clock configuration -----------------------------------------------*/
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
+ 1323              		.loc 1 763 3 is_stmt 1 view .LVU473
+ 1324              		.loc 1 763 38 is_stmt 0 view .LVU474
+ 1325 0112 D3F89020 		ldr	r2, [r3, #144]
+ARM GAS  /tmp/cc41FM7T.s 			page 40
+
+
+ 1326 0116 02F08062 		and	r2, r2, #67108864
+ 1327              		.loc 1 763 36 view .LVU475
+ 1328 011a 8267     		str	r2, [r0, #120]
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the CK48 clock configuration -----------------------------------------------*/
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+ 1329              		.loc 1 766 3 is_stmt 1 view .LVU476
+ 1330              		.loc 1 766 40 is_stmt 0 view .LVU477
+ 1331 011c D3F89020 		ldr	r2, [r3, #144]
+ 1332 0120 02F00062 		and	r2, r2, #134217728
+ 1333              		.loc 1 766 38 view .LVU478
+ 1334 0124 C267     		str	r2, [r0, #124]
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the SDMMC1 clock configuration -----------------------------------------------*/
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
+ 1335              		.loc 1 769 3 is_stmt 1 view .LVU479
+ 1336              		.loc 1 769 41 is_stmt 0 view .LVU480
+ 1337 0126 D3F89020 		ldr	r2, [r3, #144]
+ 1338 012a 02F08052 		and	r2, r2, #268435456
+ 1339              		.loc 1 769 39 view .LVU481
+ 1340 012e C0F88020 		str	r2, [r0, #128]
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the SDMMC2 clock configuration -----------------------------------------------*/
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
+ 1341              		.loc 1 773 3 is_stmt 1 view .LVU482
+ 1342              		.loc 1 773 41 is_stmt 0 view .LVU483
+ 1343 0132 D3F89020 		ldr	r2, [r3, #144]
+ 1344 0136 02F00052 		and	r2, r2, #536870912
+ 1345              		.loc 1 773 39 view .LVU484
+ 1346 013a C0F88420 		str	r2, [r0, #132]
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the DFSDM clock configuration -----------------------------------------------*/
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
+ 1347              		.loc 1 776 3 is_stmt 1 view .LVU485
+ 1348              		.loc 1 776 41 is_stmt 0 view .LVU486
+ 1349 013e D3F88C20 		ldr	r2, [r3, #140]
+ 1350 0142 02F00072 		and	r2, r2, #33554432
+ 1351              		.loc 1 776 39 view .LVU487
+ 1352 0146 C0F88820 		str	r2, [r0, #136]
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
+ 1353              		.loc 1 779 3 is_stmt 1 view .LVU488
+ 1354              		.loc 1 779 46 is_stmt 0 view .LVU489
+ 1355 014a D3F88C20 		ldr	r2, [r3, #140]
+ 1356 014e 02F08062 		and	r2, r2, #67108864
+ 1357              		.loc 1 779 44 view .LVU490
+ 1358 0152 C0F88C20 		str	r2, [r0, #140]
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the RTC Clock configuration -----------------------------------------------*/
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+ 1359              		.loc 1 783 3 is_stmt 1 view .LVU491
+ 1360              		.loc 1 783 17 is_stmt 0 view .LVU492
+ 1361 0156 9968     		ldr	r1, [r3, #8]
+ 1362              		.loc 1 783 11 view .LVU493
+ARM GAS  /tmp/cc41FM7T.s 			page 41
+
+
+ 1363 0158 01F4F811 		and	r1, r1, #2031616
+ 1364              	.LVL78:
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+ 1365              		.loc 1 784 3 is_stmt 1 view .LVU494
+ 1366              		.loc 1 784 65 is_stmt 0 view .LVU495
+ 1367 015c 1A6F     		ldr	r2, [r3, #112]
+ 1368              		.loc 1 784 72 view .LVU496
+ 1369 015e 02F44072 		and	r2, r2, #768
+ 1370              		.loc 1 784 38 view .LVU497
+ 1371 0162 0A43     		orrs	r2, r2, r1
+ 1372              		.loc 1 784 36 view .LVU498
+ 1373 0164 0263     		str	r2, [r0, #48]
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the TIM Prescaler configuration --------------------------------------------*/
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
+ 1374              		.loc 1 787 3 is_stmt 1 view .LVU499
+ 1375              		.loc 1 787 11 is_stmt 0 view .LVU500
+ 1376 0166 D3F88C30 		ldr	r3, [r3, #140]
+ 1377              		.loc 1 787 6 view .LVU501
+ 1378 016a 13F0807F 		tst	r3, #16777216
+ 1379 016e 02D1     		bne	.L95
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+ 1380              		.loc 1 789 5 is_stmt 1 view .LVU502
+ 1381              		.loc 1 789 37 is_stmt 0 view .LVU503
+ 1382 0170 0023     		movs	r3, #0
+ 1383 0172 8363     		str	r3, [r0, #56]
+ 1384 0174 7047     		bx	lr
+ 1385              	.L95:
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   else
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+ 1386              		.loc 1 793 5 is_stmt 1 view .LVU504
+ 1387              		.loc 1 793 37 is_stmt 0 view .LVU505
+ 1388 0176 4FF08073 		mov	r3, #16777216
+ 1389 017a 8363     		str	r3, [r0, #56]
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ 1390              		.loc 1 795 1 view .LVU506
+ 1391 017c 7047     		bx	lr
+ 1392              	.L98:
+ 1393 017e 00BF     		.align	2
+ 1394              	.L97:
+ 1395 0180 F1FFFF1C 		.word	486539249
+ 1396 0184 00380240 		.word	1073887232
+ 1397              		.cfi_endproc
+ 1398              	.LFE142:
+ 1400              		.section	.text.HAL_RCCEx_GetPeriphCLKFreq,"ax",%progbits
+ 1401              		.align	1
+ 1402              		.global	HAL_RCCEx_GetPeriphCLKFreq
+ 1403              		.syntax unified
+ 1404              		.thumb
+ 1405              		.thumb_func
+ 1406              		.fpu fpv5-d16
+ 1408              	HAL_RCCEx_GetPeriphCLKFreq:
+ 1409              	.LVL79:
+ARM GAS  /tmp/cc41FM7T.s 			page 42
+
+
+ 1410              	.LFB143:
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx ||
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @brief  Initializes the RCC extended peripherals clocks according to the specified
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         parameters in the RCC_PeriphCLKInitTypeDef.
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         contains the configuration information for the Extended Peripherals
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         the RTC clock source; in this case the Backup domain will be reset in
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         order to modify the RTC Clock source, as consequence RTC registers (including
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         the backup registers) are set to their reset values.
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @retval HAL status
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** {
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tickstart = 0;
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tmpreg0 = 0;
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t plli2sused = 0;
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t pllsaiused = 0;
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Check the parameters */
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*----------------------------------- I2S configuration ----------------------------------*/
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure I2S Clock source */
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLI2S when it's used as clock source for I2S */
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       plli2sused = 1;
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------ SAI1 configuration --------------------------------------*
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure SAI1 Clock source */
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLI2S when it's used as clock source for SAI */
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       plli2sused = 1;
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ARM GAS  /tmp/cc41FM7T.s 			page 43
+
+
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLSAI when it's used as clock source for SAI */
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       pllsaiused = 1;
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------ SAI2 configuration --------------------------------------*
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure SAI2 Clock source */
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLI2S when it's used as clock source for SAI */
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       plli2sused = 1;
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLSAI when it's used as clock source for SAI */
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       pllsaiused = 1;
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------ RTC configuration --------------------------------------*/
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check for RTC Parameters used to output RTCCLK */
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable Power Clock*/
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_PWR_CLK_ENABLE();
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable write access to Backup domain */
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     PWR->CR1 |= PWR_CR1_DBP;
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Get Start Tick*/
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tickstart = HAL_GetTick();
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Wait for Backup domain Write protection disable */
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     while((PWR->CR1 & PWR_CR1_DBP) == RESET)
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         return HAL_TIMEOUT;
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ARM GAS  /tmp/cc41FM7T.s 			page 44
+
+
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Store the content of BDCR register before the reset of Backup Domain */
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_BACKUPRESET_FORCE();
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_BACKUPRESET_RELEASE();
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Restore the Content of BDCR register */
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       RCC->BDCR = tmpreg0;
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* Get Start Tick*/
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         tickstart = HAL_GetTick();
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* Wait till LSE is ready */
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           {
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****             return HAL_TIMEOUT;
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           }
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------ TIM configuration --------------------------------------*/
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure Timer Prescaler */
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- I2C1 Configuration -----------------------------------*/
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the I2C1 clock source */
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- I2C2 Configuration -----------------------------------*/
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the I2C2 clock source */
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+ARM GAS  /tmp/cc41FM7T.s 			page 45
+
+
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- I2C3 Configuration -----------------------------------*/
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the I2C3 clock source */
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- USART1 Configuration -----------------------------------
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the USART1 clock source */
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- USART2 Configuration -----------------------------------
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the USART2 clock source */
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- USART3 Configuration -----------------------------------
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the USART3 clock source */
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- UART4 Configuration -----------------------------------*
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the UART4 clock source */
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- UART5 Configuration -----------------------------------*
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+ARM GAS  /tmp/cc41FM7T.s 			page 46
+
+
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the UART5 clock source */
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- USART6 Configuration -----------------------------------
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the USART6 clock source */
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- UART7 Configuration -----------------------------------*
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the UART7 clock source */
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- UART8 Configuration -----------------------------------*
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the UART8 clock source */
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- CK48 Configuration -----------------------------------*/
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the CLK48 source */
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLSAI when it's used as clock source for CK48 */
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       pllsaiused = 1;
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- LPTIM1 Configuration -----------------------------------
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ARM GAS  /tmp/cc41FM7T.s 			page 47
+
+
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the LTPIM1 clock source */
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****    }
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------- SDMMC1 Configuration ------------------------------------
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
+1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the SDMMC1 clock source */
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*------------------------------------- SDMMC2 Configuration ------------------------------------
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the parameters */
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
+1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Configure the SDMMC2 clock source */
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERI
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Disable the PLLI2S */
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_PLLI2S_DISABLE();
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Get Start Tick*/
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tickstart = HAL_GetTick();
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Wait till PLLI2S is disabled */
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* return in case of Timeout detected */
+1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         return HAL_TIMEOUT;
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* check for common PLLI2S Parameters */
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (Peri
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* check for Parameters */
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuratio
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Configure the PLLI2S division factors */
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
+ARM GAS  /tmp/cc41FM7T.s 			page 48
+
+
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2S
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (Pe
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Check for PLLI2S Parameters */
+1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Check for PLLI2S/DIVQ parameters */
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Configure the PLLI2S division factors */
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*----------------- In Case of PLLI2S is just selected  -----------------*/
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Check for Parameters */
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Configure the PLLI2S division factors */
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
+1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, Periph
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable the PLLI2S */
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_PLLI2S_ENABLE();
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Get Start Tick*/
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tickstart = HAL_GetTick();
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Wait till PLLI2S is ready */
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* return in case of Timeout detected */
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         return HAL_TIMEOUT;
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if(pllsaiused == 1)
+ARM GAS  /tmp/cc41FM7T.s 			page 49
+
+
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Disable PLLSAI Clock */
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_PLLSAI_DISABLE();
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Get Start Tick*/
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tickstart = HAL_GetTick();
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Wait till PLLSAI is disabled */
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* return in case of Timeout detected */
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         return HAL_TIMEOUT;
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Check the PLLSAI division factors */
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (Pe
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* check for PLLSAIQ Parameter */
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* check for PLLSAI/DIVQ Parameter */
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuratio
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAI
+1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* In Case of PLLI2S is selected as source clock for CK48 */
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (P
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* check for Parameters */
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* Configure the PLLSAI division factors */
+1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Enable PLLSAI Clock */
+1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     __HAL_RCC_PLLSAI_ENABLE();
+ARM GAS  /tmp/cc41FM7T.s 			page 50
+
+
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Get Start Tick*/
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     tickstart = HAL_GetTick();
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     /* Wait till PLLSAI is ready */
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* return in case of Timeout detected */
+1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         return HAL_TIMEOUT;
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   return HAL_OK;
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         RCC configuration registers.
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @param  PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure
+1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @retval None
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** {
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tempreg = 0;
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Set all possible values for the extended clock type parameter------------*/
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
+1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                                         RCC_PERIPHCLK_CLK48    | RCC_PERIPHCLK_SDMMC2;
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI
+1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI
+1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the PLLSAI Clock configuration -----------------------------------------------*/
+1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLS
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLS
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLS
+1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the SAI1 clock configuration ----------------------------------------------*/
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the SAI2 clock configuration ----------------------------------------------*/
+ARM GAS  /tmp/cc41FM7T.s 			page 51
+
+
+1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the I2S clock configuration ------------------------------------------*/
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the I2C1 clock configuration ------------------------------------------*/
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the I2C2 clock configuration ------------------------------------------*/
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
+1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the I2C3 clock configuration ------------------------------------------*/
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
+1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the USART1 clock configuration ------------------------------------------*/
+1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the USART2 clock configuration ------------------------------------------*/
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the USART3 clock configuration ------------------------------------------*/
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the UART4 clock configuration ------------------------------------------*/
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the UART5 clock configuration ------------------------------------------*/
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
+1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the USART6 clock configuration ------------------------------------------*/
+1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
+1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the UART7 clock configuration ------------------------------------------*/
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
+1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the UART8 clock configuration ------------------------------------------*/
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the LPTIM1 clock configuration ------------------------------------------*/
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
+1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the CK48 clock configuration -----------------------------------------------*/
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the SDMMC1 clock configuration -----------------------------------------------*/
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the SDMMC2 clock configuration -----------------------------------------------*/
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
+1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the RTC Clock configuration -----------------------------------------------*/
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Get the TIM Prescaler configuration --------------------------------------------*/
+1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ARM GAS  /tmp/cc41FM7T.s 			page 52
+
+
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   else
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
+1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @note   Return 0 if peripheral clock identifier not managed by this API
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @param  PeriphClk Peripheral clock identifier
+1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         This parameter can be one of the following values:
+1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
+1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @retval Frequency in KHz
+1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** {
+ 1411              		.loc 1 1384 1 is_stmt 1 view -0
+ 1412              		.cfi_startproc
+ 1413              		@ args = 0, pretend = 0, frame = 0
+ 1414              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1415              		@ link register save eliminated.
+ 1416              		.loc 1 1384 1 is_stmt 0 view .LVU508
+ 1417 0000 0346     		mov	r3, r0
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tmpreg = 0;
+ 1418              		.loc 1 1385 3 is_stmt 1 view .LVU509
+ 1419              	.LVL80:
+1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* This variable is used to store the SAI clock frequency (value in Hz) */
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t frequency = 0;
+ 1420              		.loc 1 1387 3 view .LVU510
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* This variable is used to store the VCO Input (value in Hz) */
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t vcoinput = 0;
+ 1421              		.loc 1 1389 3 view .LVU511
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* This variable is used to store the SAI clock source */
+1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t saiclocksource = 0;
+ 1422              		.loc 1 1391 3 view .LVU512
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if (PeriphClk == RCC_PERIPHCLK_SAI1)
+ 1423              		.loc 1 1393 3 view .LVU513
+ 1424              		.loc 1 1393 6 is_stmt 0 view .LVU514
+ 1425 0002 B0F5002F 		cmp	r0, #524288
+ 1426 0006 04D0     		beq	.L123
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* This variable is used to store the VCO Input (value in Hz) */
+ 1427              		.loc 1 1387 12 view .LVU515
+ 1428 0008 0020     		movs	r0, #0
+ 1429              	.LVL81:
+ 1430              	.L100:
+1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     saiclocksource = RCC->DCKCFGR1;
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     switch (saiclocksource)
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     case 0: /* PLLSAI is the clock source for SAI1 */
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+ARM GAS  /tmp/cc41FM7T.s 			page 53
+
+
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* Configure the PLLSAI division factor */
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the PLL Source is HSI (Internal Clock) */
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         else
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the PLL Source is HSE (External Clock) */
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* Configure the PLLI2S division factor */
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the PLL Source is HSI (Internal Clock) */
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         else
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the PLL Source is HSE (External Clock) */
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */
+1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = EXTERNAL_CLOCK_VALUE;
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/
+1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ARM GAS  /tmp/cc41FM7T.s 			page 54
+
+
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the main PLL Source is HSI */
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           frequency = HSI_VALUE;
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         else
+1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the main PLL Source is HSE */
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           frequency = HSE_VALUE;
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     default :
+1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   if (PeriphClk == RCC_PERIPHCLK_SAI2)
+ 1431              		.loc 1 1476 3 is_stmt 1 view .LVU516
+ 1432              		.loc 1 1476 6 is_stmt 0 view .LVU517
+ 1433 000a B3F5801F 		cmp	r3, #1048576
+ 1434 000e 71D0     		beq	.L124
+ 1435              	.LVL82:
+ 1436              	.L99:
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     saiclocksource = RCC->DCKCFGR1;
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     switch (saiclocksource)
+1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     case 0: /* PLLSAI is the clock source for SAI*/
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* Configure the PLLSAI division factor */
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the PLL Source is HSI (Internal Clock) */
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         else
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the PLL Source is HSE (External Clock) */
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* Configure the PLLI2S division factor */
+ARM GAS  /tmp/cc41FM7T.s 			page 55
+
+
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the PLL Source is HSI (Internal Clock) */
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         else
+1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the PLL Source is HSE (External Clock) */
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */
+1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = EXTERNAL_CLOCK_VALUE;
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */
+1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the main PLL Source is HSI */
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           frequency = HSI_VALUE;
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         else
+1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           /* In Case the main PLL Source is HSE */
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****           frequency = HSE_VALUE;
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     default :
+1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       {
+1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   return frequency;
+1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ 1437              		.loc 1 1560 1 view .LVU518
+ 1438 0010 7047     		bx	lr
+ 1439              	.LVL83:
+ 1440              	.L123:
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
+ARM GAS  /tmp/cc41FM7T.s 			page 56
+
+
+ 1441              		.loc 1 1395 5 is_stmt 1 view .LVU519
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
+ 1442              		.loc 1 1395 20 is_stmt 0 view .LVU520
+ 1443 0012 704A     		ldr	r2, .L129
+ 1444 0014 D2F88C20 		ldr	r2, [r2, #140]
+ 1445              	.LVL84:
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     switch (saiclocksource)
+ 1446              		.loc 1 1396 5 is_stmt 1 view .LVU521
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     switch (saiclocksource)
+ 1447              		.loc 1 1396 20 is_stmt 0 view .LVU522
+ 1448 0018 02F44012 		and	r2, r2, #3145728
+ 1449              	.LVL85:
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1450              		.loc 1 1397 5 is_stmt 1 view .LVU523
+ 1451 001c B2F5001F 		cmp	r2, #2097152
+ 1452 0020 64D0     		beq	.L119
+ 1453 0022 26D8     		bhi	.L101
+ 1454 0024 8AB3     		cbz	r2, .L102
+ 1455 0026 B2F5801F 		cmp	r2, #1048576
+ 1456 002a 20D1     		bne	.L125
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1457              		.loc 1 1427 9 view .LVU524
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1458              		.loc 1 1427 16 is_stmt 0 view .LVU525
+ 1459 002c 694A     		ldr	r2, .L129
+ 1460              	.LVL86:
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1461              		.loc 1 1427 16 view .LVU526
+ 1462 002e 5268     		ldr	r2, [r2, #4]
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1463              		.loc 1 1427 11 view .LVU527
+ 1464 0030 12F4800F 		tst	r2, #4194304
+ 1465 0034 52D1     		bne	.L107
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1466              		.loc 1 1430 11 is_stmt 1 view .LVU528
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1467              		.loc 1 1430 49 is_stmt 0 view .LVU529
+ 1468 0036 674A     		ldr	r2, .L129
+ 1469 0038 5068     		ldr	r0, [r2, #4]
+ 1470              	.LVL87:
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1471              		.loc 1 1430 35 view .LVU530
+ 1472 003a 00F03F0C 		and	ip, r0, #63
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1473              		.loc 1 1430 20 view .LVU531
+ 1474 003e 6648     		ldr	r0, .L129+4
+ 1475 0040 B0FBFCFC 		udiv	ip, r0, ip
+ 1476              	.LVL88:
+ 1477              	.L108:
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+ 1478              		.loc 1 1440 9 is_stmt 1 view .LVU532
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+ 1479              		.loc 1 1440 22 is_stmt 0 view .LVU533
+ 1480 0044 634A     		ldr	r2, .L129
+ 1481 0046 D2F88410 		ldr	r1, [r2, #132]
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+ 1482              		.loc 1 1440 16 view .LVU534
+ARM GAS  /tmp/cc41FM7T.s 			page 57
+
+
+ 1483 004a C1F30361 		ubfx	r1, r1, #24, #4
+ 1484              	.LVL89:
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1485              		.loc 1 1441 9 is_stmt 1 view .LVU535
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1486              		.loc 1 1441 38 is_stmt 0 view .LVU536
+ 1487 004e D2F88400 		ldr	r0, [r2, #132]
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1488              		.loc 1 1441 77 view .LVU537
+ 1489 0052 C0F38810 		ubfx	r0, r0, #6, #9
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1490              		.loc 1 1441 31 view .LVU538
+ 1491 0056 0CFB00F0 		mul	r0, ip, r0
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1492              		.loc 1 1441 19 view .LVU539
+ 1493 005a B0FBF1F0 		udiv	r0, r0, r1
+ 1494              	.LVL90:
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1495              		.loc 1 1444 9 is_stmt 1 view .LVU540
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1496              		.loc 1 1444 23 is_stmt 0 view .LVU541
+ 1497 005e D2F88C20 		ldr	r2, [r2, #140]
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1498              		.loc 1 1444 34 view .LVU542
+ 1499 0062 02F01F02 		and	r2, r2, #31
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1500              		.loc 1 1444 16 view .LVU543
+ 1501 0066 0132     		adds	r2, r2, #1
+ 1502              	.LVL91:
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1503              		.loc 1 1445 9 is_stmt 1 view .LVU544
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1504              		.loc 1 1445 19 is_stmt 0 view .LVU545
+ 1505 0068 B0FBF2F0 		udiv	r0, r0, r2
+ 1506              	.LVL92:
+1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 1507              		.loc 1 1446 9 is_stmt 1 view .LVU546
+ 1508 006c CDE7     		b	.L100
+ 1509              	.LVL93:
+ 1510              	.L125:
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1511              		.loc 1 1397 5 is_stmt 0 view .LVU547
+ 1512 006e 0020     		movs	r0, #0
+ 1513              	.LVL94:
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1514              		.loc 1 1397 5 view .LVU548
+ 1515 0070 CBE7     		b	.L100
+ 1516              	.LVL95:
+ 1517              	.L101:
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1518              		.loc 1 1397 5 view .LVU549
+ 1519 0072 B2F5401F 		cmp	r2, #3145728
+ 1520 0076 06D1     		bne	.L126
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1521              		.loc 1 1456 9 is_stmt 1 view .LVU550
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1522              		.loc 1 1456 16 is_stmt 0 view .LVU551
+ARM GAS  /tmp/cc41FM7T.s 			page 58
+
+
+ 1523 0078 564A     		ldr	r2, .L129
+ 1524              	.LVL96:
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1525              		.loc 1 1456 16 view .LVU552
+ 1526 007a 5268     		ldr	r2, [r2, #4]
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1527              		.loc 1 1456 11 view .LVU553
+ 1528 007c 12F4800F 		tst	r2, #4194304
+ 1529 0080 36D1     		bne	.L120
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1530              		.loc 1 1459 21 view .LVU554
+ 1531 0082 5548     		ldr	r0, .L129+4
+ 1532              	.LVL97:
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1533              		.loc 1 1459 21 view .LVU555
+ 1534 0084 C1E7     		b	.L100
+ 1535              	.LVL98:
+ 1536              	.L126:
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1537              		.loc 1 1397 5 view .LVU556
+ 1538 0086 0020     		movs	r0, #0
+ 1539              	.LVL99:
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1540              		.loc 1 1397 5 view .LVU557
+ 1541 0088 BFE7     		b	.L100
+ 1542              	.LVL100:
+ 1543              	.L102:
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1544              		.loc 1 1403 9 is_stmt 1 view .LVU558
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1545              		.loc 1 1403 16 is_stmt 0 view .LVU559
+ 1546 008a 524A     		ldr	r2, .L129
+ 1547              	.LVL101:
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1548              		.loc 1 1403 16 view .LVU560
+ 1549 008c 5268     		ldr	r2, [r2, #4]
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1550              		.loc 1 1403 11 view .LVU561
+ 1551 008e 12F4800F 		tst	r2, #4194304
+ 1552 0092 1BD1     		bne	.L105
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1553              		.loc 1 1406 11 is_stmt 1 view .LVU562
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1554              		.loc 1 1406 49 is_stmt 0 view .LVU563
+ 1555 0094 4F4A     		ldr	r2, .L129
+ 1556 0096 5068     		ldr	r0, [r2, #4]
+ 1557              	.LVL102:
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1558              		.loc 1 1406 35 view .LVU564
+ 1559 0098 00F03F0C 		and	ip, r0, #63
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1560              		.loc 1 1406 20 view .LVU565
+ 1561 009c 4E48     		ldr	r0, .L129+4
+ 1562 009e B0FBFCFC 		udiv	ip, r0, ip
+ 1563              	.LVL103:
+ 1564              	.L106:
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+ARM GAS  /tmp/cc41FM7T.s 			page 59
+
+
+ 1565              		.loc 1 1415 9 is_stmt 1 view .LVU566
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+ 1566              		.loc 1 1415 22 is_stmt 0 view .LVU567
+ 1567 00a2 4C4A     		ldr	r2, .L129
+ 1568 00a4 D2F88810 		ldr	r1, [r2, #136]
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+ 1569              		.loc 1 1415 16 view .LVU568
+ 1570 00a8 C1F30361 		ubfx	r1, r1, #24, #4
+ 1571              	.LVL104:
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1572              		.loc 1 1416 9 is_stmt 1 view .LVU569
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1573              		.loc 1 1416 38 is_stmt 0 view .LVU570
+ 1574 00ac D2F88800 		ldr	r0, [r2, #136]
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1575              		.loc 1 1416 77 view .LVU571
+ 1576 00b0 C0F38810 		ubfx	r0, r0, #6, #9
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1577              		.loc 1 1416 31 view .LVU572
+ 1578 00b4 0CFB00F0 		mul	r0, ip, r0
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1579              		.loc 1 1416 19 view .LVU573
+ 1580 00b8 B0FBF1F0 		udiv	r0, r0, r1
+ 1581              	.LVL105:
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1582              		.loc 1 1419 9 is_stmt 1 view .LVU574
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1583              		.loc 1 1419 24 is_stmt 0 view .LVU575
+ 1584 00bc D2F88C20 		ldr	r2, [r2, #140]
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1585              		.loc 1 1419 62 view .LVU576
+ 1586 00c0 C2F30422 		ubfx	r2, r2, #8, #5
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1587              		.loc 1 1419 16 view .LVU577
+ 1588 00c4 0132     		adds	r2, r2, #1
+ 1589              	.LVL106:
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1590              		.loc 1 1420 9 is_stmt 1 view .LVU578
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1591              		.loc 1 1420 19 is_stmt 0 view .LVU579
+ 1592 00c6 B0FBF2F0 		udiv	r0, r0, r2
+ 1593              	.LVL107:
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 1594              		.loc 1 1421 9 is_stmt 1 view .LVU580
+ 1595 00ca 9EE7     		b	.L100
+ 1596              	.LVL108:
+ 1597              	.L105:
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1598              		.loc 1 1411 11 view .LVU581
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1599              		.loc 1 1411 50 is_stmt 0 view .LVU582
+ 1600 00cc 414A     		ldr	r2, .L129
+ 1601 00ce 5068     		ldr	r0, [r2, #4]
+ 1602              	.LVL109:
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1603              		.loc 1 1411 36 view .LVU583
+ 1604 00d0 00F03F0C 		and	ip, r0, #63
+ARM GAS  /tmp/cc41FM7T.s 			page 60
+
+
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1605              		.loc 1 1411 20 view .LVU584
+ 1606 00d4 4148     		ldr	r0, .L129+8
+ 1607 00d6 B0FBFCFC 		udiv	ip, r0, ip
+ 1608              	.LVL110:
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1609              		.loc 1 1411 20 view .LVU585
+ 1610 00da E2E7     		b	.L106
+ 1611              	.LVL111:
+ 1612              	.L107:
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1613              		.loc 1 1435 11 is_stmt 1 view .LVU586
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1614              		.loc 1 1435 50 is_stmt 0 view .LVU587
+ 1615 00dc 3D4A     		ldr	r2, .L129
+ 1616 00de 5068     		ldr	r0, [r2, #4]
+ 1617              	.LVL112:
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1618              		.loc 1 1435 36 view .LVU588
+ 1619 00e0 00F03F0C 		and	ip, r0, #63
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1620              		.loc 1 1435 20 view .LVU589
+ 1621 00e4 3D48     		ldr	r0, .L129+8
+ 1622 00e6 B0FBFCFC 		udiv	ip, r0, ip
+ 1623              	.LVL113:
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1624              		.loc 1 1435 20 view .LVU590
+ 1625 00ea ABE7     		b	.L108
+ 1626              	.LVL114:
+ 1627              	.L119:
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1628              		.loc 1 1450 19 view .LVU591
+ 1629 00ec 3C48     		ldr	r0, .L129+12
+ 1630              	.LVL115:
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1631              		.loc 1 1450 19 view .LVU592
+ 1632 00ee 8CE7     		b	.L100
+ 1633              	.LVL116:
+ 1634              	.L120:
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1635              		.loc 1 1464 21 view .LVU593
+ 1636 00f0 3A48     		ldr	r0, .L129+8
+ 1637              	.LVL117:
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1638              		.loc 1 1464 21 view .LVU594
+ 1639 00f2 8AE7     		b	.L100
+ 1640              	.LVL118:
+ 1641              	.L124:
+1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
+ 1642              		.loc 1 1478 5 is_stmt 1 view .LVU595
+1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
+ 1643              		.loc 1 1478 20 is_stmt 0 view .LVU596
+ 1644 00f4 374B     		ldr	r3, .L129
+ 1645              	.LVL119:
+1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
+ 1646              		.loc 1 1478 20 view .LVU597
+ 1647 00f6 D3F88C30 		ldr	r3, [r3, #140]
+ARM GAS  /tmp/cc41FM7T.s 			page 61
+
+
+ 1648              	.LVL120:
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     switch (saiclocksource)
+ 1649              		.loc 1 1479 5 is_stmt 1 view .LVU598
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     switch (saiclocksource)
+ 1650              		.loc 1 1479 20 is_stmt 0 view .LVU599
+ 1651 00fa 03F44003 		and	r3, r3, #12582912
+ 1652              	.LVL121:
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1653              		.loc 1 1480 5 is_stmt 1 view .LVU600
+ 1654 00fe B3F5000F 		cmp	r3, #8388608
+ 1655 0102 62D0     		beq	.L121
+ 1656 0104 25D8     		bhi	.L110
+ 1657 0106 7BB3     		cbz	r3, .L111
+ 1658 0108 B3F5800F 		cmp	r3, #4194304
+ 1659 010c 20D1     		bne	.L127
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1660              		.loc 1 1510 9 view .LVU601
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1661              		.loc 1 1510 16 is_stmt 0 view .LVU602
+ 1662 010e 314B     		ldr	r3, .L129
+ 1663              	.LVL122:
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1664              		.loc 1 1510 16 view .LVU603
+ 1665 0110 5B68     		ldr	r3, [r3, #4]
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1666              		.loc 1 1510 11 view .LVU604
+ 1667 0112 13F4800F 		tst	r3, #4194304
+ 1668 0116 50D1     		bne	.L116
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1669              		.loc 1 1513 11 is_stmt 1 view .LVU605
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1670              		.loc 1 1513 49 is_stmt 0 view .LVU606
+ 1671 0118 2E4B     		ldr	r3, .L129
+ 1672 011a 5968     		ldr	r1, [r3, #4]
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1673              		.loc 1 1513 35 view .LVU607
+ 1674 011c 01F03F01 		and	r1, r1, #63
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1675              		.loc 1 1513 20 view .LVU608
+ 1676 0120 2D48     		ldr	r0, .L129+4
+ 1677              	.LVL123:
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1678              		.loc 1 1513 20 view .LVU609
+ 1679 0122 B0FBF1F1 		udiv	r1, r0, r1
+ 1680              	.LVL124:
+ 1681              	.L117:
+1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+ 1682              		.loc 1 1523 9 is_stmt 1 view .LVU610
+1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+ 1683              		.loc 1 1523 22 is_stmt 0 view .LVU611
+ 1684 0126 2B4B     		ldr	r3, .L129
+ 1685 0128 D3F88420 		ldr	r2, [r3, #132]
+1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+ 1686              		.loc 1 1523 16 view .LVU612
+ 1687 012c C2F30362 		ubfx	r2, r2, #24, #4
+ 1688              	.LVL125:
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ARM GAS  /tmp/cc41FM7T.s 			page 62
+
+
+ 1689              		.loc 1 1524 9 is_stmt 1 view .LVU613
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1690              		.loc 1 1524 38 is_stmt 0 view .LVU614
+ 1691 0130 D3F88400 		ldr	r0, [r3, #132]
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1692              		.loc 1 1524 77 view .LVU615
+ 1693 0134 C0F38810 		ubfx	r0, r0, #6, #9
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1694              		.loc 1 1524 31 view .LVU616
+ 1695 0138 01FB00F0 		mul	r0, r1, r0
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1696              		.loc 1 1524 19 view .LVU617
+ 1697 013c B0FBF2F0 		udiv	r0, r0, r2
+ 1698              	.LVL126:
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1699              		.loc 1 1527 9 is_stmt 1 view .LVU618
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1700              		.loc 1 1527 23 is_stmt 0 view .LVU619
+ 1701 0140 D3F88C30 		ldr	r3, [r3, #140]
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1702              		.loc 1 1527 34 view .LVU620
+ 1703 0144 03F01F03 		and	r3, r3, #31
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1704              		.loc 1 1527 16 view .LVU621
+ 1705 0148 0133     		adds	r3, r3, #1
+ 1706              	.LVL127:
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1707              		.loc 1 1528 9 is_stmt 1 view .LVU622
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1708              		.loc 1 1528 19 is_stmt 0 view .LVU623
+ 1709 014a B0FBF3F0 		udiv	r0, r0, r3
+ 1710              	.LVL128:
+1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 1711              		.loc 1 1529 9 is_stmt 1 view .LVU624
+ 1712 014e 7047     		bx	lr
+ 1713              	.LVL129:
+ 1714              	.L127:
+1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 1715              		.loc 1 1529 9 is_stmt 0 view .LVU625
+ 1716 0150 7047     		bx	lr
+ 1717              	.L110:
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1718              		.loc 1 1480 5 view .LVU626
+ 1719 0152 B3F5400F 		cmp	r3, #12582912
+ 1720 0156 06D1     		bne	.L128
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1721              		.loc 1 1539 9 is_stmt 1 view .LVU627
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1722              		.loc 1 1539 16 is_stmt 0 view .LVU628
+ 1723 0158 1E4B     		ldr	r3, .L129
+ 1724              	.LVL130:
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1725              		.loc 1 1539 16 view .LVU629
+ 1726 015a 5B68     		ldr	r3, [r3, #4]
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1727              		.loc 1 1539 11 view .LVU630
+ 1728 015c 13F4800F 		tst	r3, #4194304
+ARM GAS  /tmp/cc41FM7T.s 			page 63
+
+
+ 1729 0160 35D1     		bne	.L122
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1730              		.loc 1 1542 21 view .LVU631
+ 1731 0162 1D48     		ldr	r0, .L129+4
+ 1732              	.LVL131:
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1733              		.loc 1 1542 21 view .LVU632
+ 1734 0164 7047     		bx	lr
+ 1735              	.LVL132:
+ 1736              	.L128:
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1737              		.loc 1 1542 21 view .LVU633
+ 1738 0166 7047     		bx	lr
+ 1739              	.L111:
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1740              		.loc 1 1486 9 is_stmt 1 view .LVU634
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1741              		.loc 1 1486 16 is_stmt 0 view .LVU635
+ 1742 0168 1A4B     		ldr	r3, .L129
+ 1743              	.LVL133:
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1744              		.loc 1 1486 16 view .LVU636
+ 1745 016a 5B68     		ldr	r3, [r3, #4]
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         {
+ 1746              		.loc 1 1486 11 view .LVU637
+ 1747 016c 13F4800F 		tst	r3, #4194304
+ 1748 0170 1BD1     		bne	.L114
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1749              		.loc 1 1489 11 is_stmt 1 view .LVU638
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1750              		.loc 1 1489 49 is_stmt 0 view .LVU639
+ 1751 0172 184B     		ldr	r3, .L129
+ 1752 0174 5968     		ldr	r1, [r3, #4]
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1753              		.loc 1 1489 35 view .LVU640
+ 1754 0176 01F03F01 		and	r1, r1, #63
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1755              		.loc 1 1489 20 view .LVU641
+ 1756 017a 1748     		ldr	r0, .L129+4
+ 1757              	.LVL134:
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1758              		.loc 1 1489 20 view .LVU642
+ 1759 017c B0FBF1F1 		udiv	r1, r0, r1
+ 1760              	.LVL135:
+ 1761              	.L115:
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+ 1762              		.loc 1 1498 9 is_stmt 1 view .LVU643
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+ 1763              		.loc 1 1498 22 is_stmt 0 view .LVU644
+ 1764 0180 144B     		ldr	r3, .L129
+ 1765 0182 D3F88820 		ldr	r2, [r3, #136]
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+ 1766              		.loc 1 1498 16 view .LVU645
+ 1767 0186 C2F30362 		ubfx	r2, r2, #24, #4
+ 1768              	.LVL136:
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1769              		.loc 1 1499 9 is_stmt 1 view .LVU646
+ARM GAS  /tmp/cc41FM7T.s 			page 64
+
+
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1770              		.loc 1 1499 38 is_stmt 0 view .LVU647
+ 1771 018a D3F88800 		ldr	r0, [r3, #136]
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1772              		.loc 1 1499 77 view .LVU648
+ 1773 018e C0F38810 		ubfx	r0, r0, #6, #9
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1774              		.loc 1 1499 31 view .LVU649
+ 1775 0192 01FB00F0 		mul	r0, r1, r0
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1776              		.loc 1 1499 19 view .LVU650
+ 1777 0196 B0FBF2F0 		udiv	r0, r0, r2
+ 1778              	.LVL137:
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1779              		.loc 1 1502 9 is_stmt 1 view .LVU651
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1780              		.loc 1 1502 24 is_stmt 0 view .LVU652
+ 1781 019a D3F88C30 		ldr	r3, [r3, #140]
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1782              		.loc 1 1502 62 view .LVU653
+ 1783 019e C3F30423 		ubfx	r3, r3, #8, #5
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         frequency = frequency/(tmpreg);
+ 1784              		.loc 1 1502 16 view .LVU654
+ 1785 01a2 0133     		adds	r3, r3, #1
+ 1786              	.LVL138:
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1787              		.loc 1 1503 9 is_stmt 1 view .LVU655
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1788              		.loc 1 1503 19 is_stmt 0 view .LVU656
+ 1789 01a4 B0FBF3F0 		udiv	r0, r0, r3
+ 1790              	.LVL139:
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       }
+ 1791              		.loc 1 1504 9 is_stmt 1 view .LVU657
+ 1792 01a8 7047     		bx	lr
+ 1793              	.LVL140:
+ 1794              	.L114:
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1795              		.loc 1 1494 11 view .LVU658
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1796              		.loc 1 1494 50 is_stmt 0 view .LVU659
+ 1797 01aa 0A4B     		ldr	r3, .L129
+ 1798 01ac 5968     		ldr	r1, [r3, #4]
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1799              		.loc 1 1494 36 view .LVU660
+ 1800 01ae 01F03F01 		and	r1, r1, #63
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1801              		.loc 1 1494 20 view .LVU661
+ 1802 01b2 0A48     		ldr	r0, .L129+8
+ 1803              	.LVL141:
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1804              		.loc 1 1494 20 view .LVU662
+ 1805 01b4 B0FBF1F1 		udiv	r1, r0, r1
+ 1806              	.LVL142:
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1807              		.loc 1 1494 20 view .LVU663
+ 1808 01b8 E2E7     		b	.L115
+ 1809              	.LVL143:
+ARM GAS  /tmp/cc41FM7T.s 			page 65
+
+
+ 1810              	.L116:
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1811              		.loc 1 1518 11 is_stmt 1 view .LVU664
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1812              		.loc 1 1518 50 is_stmt 0 view .LVU665
+ 1813 01ba 064B     		ldr	r3, .L129
+ 1814 01bc 5968     		ldr	r1, [r3, #4]
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1815              		.loc 1 1518 36 view .LVU666
+ 1816 01be 01F03F01 		and	r1, r1, #63
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1817              		.loc 1 1518 20 view .LVU667
+ 1818 01c2 0648     		ldr	r0, .L129+8
+ 1819              	.LVL144:
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1820              		.loc 1 1518 20 view .LVU668
+ 1821 01c4 B0FBF1F1 		udiv	r1, r0, r1
+ 1822              	.LVL145:
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1823              		.loc 1 1518 20 view .LVU669
+ 1824 01c8 ADE7     		b	.L117
+ 1825              	.LVL146:
+ 1826              	.L121:
+1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1827              		.loc 1 1533 19 view .LVU670
+ 1828 01ca 0548     		ldr	r0, .L129+12
+ 1829              	.LVL147:
+1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         break;
+ 1830              		.loc 1 1533 19 view .LVU671
+ 1831 01cc 7047     		bx	lr
+ 1832              	.LVL148:
+ 1833              	.L122:
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****         }
+ 1834              		.loc 1 1547 21 view .LVU672
+ 1835 01ce 0348     		ldr	r0, .L129+8
+ 1836              	.LVL149:
+1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ 1837              		.loc 1 1559 3 is_stmt 1 view .LVU673
+1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ 1838              		.loc 1 1559 10 is_stmt 0 view .LVU674
+ 1839 01d0 1EE7     		b	.L99
+ 1840              	.L130:
+ 1841 01d2 00BF     		.align	2
+ 1842              	.L129:
+ 1843 01d4 00380240 		.word	1073887232
+ 1844 01d8 0024F400 		.word	16000000
+ 1845 01dc 40787D01 		.word	25000000
+ 1846 01e0 0080BB00 		.word	12288000
+ 1847              		.cfi_endproc
+ 1848              	.LFE143:
+ 1850              		.section	.text.HAL_RCCEx_EnablePLLI2S,"ax",%progbits
+ 1851              		.align	1
+ 1852              		.global	HAL_RCCEx_EnablePLLI2S
+ 1853              		.syntax unified
+ 1854              		.thumb
+ 1855              		.thumb_func
+ 1856              		.fpu fpv5-d16
+ARM GAS  /tmp/cc41FM7T.s 			page 66
+
+
+ 1858              	HAL_RCCEx_EnablePLLI2S:
+ 1859              	.LVL150:
+ 1860              	.LFB144:
+1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @}
+1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  *  @brief  Extended Clock management functions
+1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  *
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** @verbatim
+1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  ===============================================================================
+1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                 ##### Extended clock management functions  #####
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  ===============================================================================
+1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     [..]
+1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     This subsection provides a set of functions allowing to control the
+1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     activation or deactivation of PLLI2S, PLLSAI.
+1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** @endverbatim
+1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @{
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @brief  Enable PLLI2S.
+1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @param  PLLI2SInit  pointer to an RCC_PLLI2SInitTypeDef structure that
+1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         contains the configuration information for the PLLI2S
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @retval HAL status
+1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
+1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** {
+ 1861              		.loc 1 1587 1 is_stmt 1 view -0
+ 1862              		.cfi_startproc
+ 1863              		@ args = 0, pretend = 0, frame = 0
+ 1864              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1865              		.loc 1 1587 1 is_stmt 0 view .LVU676
+ 1866 0000 38B5     		push	{r3, r4, r5, lr}
+ 1867              	.LCFI4:
+ 1868              		.cfi_def_cfa_offset 16
+ 1869              		.cfi_offset 3, -16
+ 1870              		.cfi_offset 4, -12
+ 1871              		.cfi_offset 5, -8
+ 1872              		.cfi_offset 14, -4
+ 1873 0002 0546     		mov	r5, r0
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tickstart;
+ 1874              		.loc 1 1588 3 is_stmt 1 view .LVU677
+1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Check for parameters */
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));
+ 1875              		.loc 1 1591 3 view .LVU678
+1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));
+ 1876              		.loc 1 1592 3 view .LVU679
+1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));
+ 1877              		.loc 1 1593 3 view .LVU680
+1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined(RCC_PLLI2SCFGR_PLLI2SP)
+1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));
+ 1878              		.loc 1 1595 3 view .LVU681
+1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* RCC_PLLI2SCFGR_PLLI2SP */
+ARM GAS  /tmp/cc41FM7T.s 			page 67
+
+
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Disable the PLLI2S */
+1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   __HAL_RCC_PLLI2S_DISABLE();
+ 1879              		.loc 1 1599 3 view .LVU682
+ 1880 0004 1B4A     		ldr	r2, .L142
+ 1881 0006 1368     		ldr	r3, [r2]
+ 1882 0008 23F08063 		bic	r3, r3, #67108864
+ 1883 000c 1360     		str	r3, [r2]
+1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Wait till PLLI2S is disabled */
+1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   tickstart = HAL_GetTick();
+ 1884              		.loc 1 1602 3 view .LVU683
+ 1885              		.loc 1 1602 15 is_stmt 0 view .LVU684
+ 1886 000e FFF7FEFF 		bl	HAL_GetTick
+ 1887              	.LVL151:
+ 1888              		.loc 1 1602 15 view .LVU685
+ 1889 0012 0446     		mov	r4, r0
+ 1890              	.LVL152:
+1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ 1891              		.loc 1 1603 3 is_stmt 1 view .LVU686
+ 1892              	.L132:
+ 1893              		.loc 1 1603 8 view .LVU687
+ 1894              		.loc 1 1603 9 is_stmt 0 view .LVU688
+ 1895 0014 174B     		ldr	r3, .L142
+ 1896 0016 1B68     		ldr	r3, [r3]
+ 1897              		.loc 1 1603 8 view .LVU689
+ 1898 0018 13F0006F 		tst	r3, #134217728
+ 1899 001c 06D0     		beq	.L140
+1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ 1900              		.loc 1 1605 5 is_stmt 1 view .LVU690
+ 1901              		.loc 1 1605 9 is_stmt 0 view .LVU691
+ 1902 001e FFF7FEFF 		bl	HAL_GetTick
+ 1903              	.LVL153:
+ 1904              		.loc 1 1605 23 view .LVU692
+ 1905 0022 001B     		subs	r0, r0, r4
+ 1906              		.loc 1 1605 7 view .LVU693
+ 1907 0024 6428     		cmp	r0, #100
+ 1908 0026 F5D9     		bls	.L132
+1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* return in case of Timeout detected */
+1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       return HAL_TIMEOUT;
+ 1909              		.loc 1 1608 14 view .LVU694
+ 1910 0028 0320     		movs	r0, #3
+ 1911              	.L133:
+1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Configure the PLLI2S division factors */
+1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx
+1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
+1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #else
+1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
+1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* I2SPCLK = PLLI2S_VCO / PLLI2SP */
+ARM GAS  /tmp/cc41FM7T.s 			page 68
+
+
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit
+1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
+1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Enable the PLLI2S */
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   __HAL_RCC_PLLI2S_ENABLE();
+1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Wait till PLLI2S is ready */
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   tickstart = HAL_GetTick();
+1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* return in case of Timeout detected */
+1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       return HAL_TIMEOUT;
+1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  return HAL_OK;
+1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ 1912              		.loc 1 1641 1 view .LVU695
+ 1913 002a 38BD     		pop	{r3, r4, r5, pc}
+ 1914              	.LVL154:
+ 1915              	.L140:
+1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
+ 1916              		.loc 1 1623 3 is_stmt 1 view .LVU696
+ 1917 002c 2A68     		ldr	r2, [r5]
+ 1918 002e EB68     		ldr	r3, [r5, #12]
+ 1919 0030 1B04     		lsls	r3, r3, #16
+ 1920 0032 43EA8213 		orr	r3, r3, r2, lsl #6
+ 1921 0036 AA68     		ldr	r2, [r5, #8]
+ 1922 0038 43EA0263 		orr	r3, r3, r2, lsl #24
+ 1923 003c 6A68     		ldr	r2, [r5, #4]
+ 1924 003e 43EA0273 		orr	r3, r3, r2, lsl #28
+ 1925 0042 0C4A     		ldr	r2, .L142
+ 1926 0044 C2F88430 		str	r3, [r2, #132]
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 1927              		.loc 1 1627 3 view .LVU697
+ 1928 0048 1368     		ldr	r3, [r2]
+ 1929 004a 43F08063 		orr	r3, r3, #67108864
+ 1930 004e 1360     		str	r3, [r2]
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ 1931              		.loc 1 1630 3 view .LVU698
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ 1932              		.loc 1 1630 15 is_stmt 0 view .LVU699
+ 1933 0050 FFF7FEFF 		bl	HAL_GetTick
+ 1934              	.LVL155:
+ 1935 0054 0446     		mov	r4, r0
+ 1936              	.LVL156:
+1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 1937              		.loc 1 1631 3 is_stmt 1 view .LVU700
+ 1938              	.L135:
+1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 1939              		.loc 1 1631 8 view .LVU701
+1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 1940              		.loc 1 1631 9 is_stmt 0 view .LVU702
+ARM GAS  /tmp/cc41FM7T.s 			page 69
+
+
+ 1941 0056 074B     		ldr	r3, .L142
+ 1942 0058 1B68     		ldr	r3, [r3]
+1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 1943              		.loc 1 1631 8 view .LVU703
+ 1944 005a 13F0006F 		tst	r3, #134217728
+ 1945 005e 06D1     		bne	.L141
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1946              		.loc 1 1633 5 is_stmt 1 view .LVU704
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1947              		.loc 1 1633 9 is_stmt 0 view .LVU705
+ 1948 0060 FFF7FEFF 		bl	HAL_GetTick
+ 1949              	.LVL157:
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1950              		.loc 1 1633 23 view .LVU706
+ 1951 0064 001B     		subs	r0, r0, r4
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 1952              		.loc 1 1633 7 view .LVU707
+ 1953 0066 6428     		cmp	r0, #100
+ 1954 0068 F5D9     		bls	.L135
+1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 1955              		.loc 1 1636 14 view .LVU708
+ 1956 006a 0320     		movs	r0, #3
+ 1957 006c DDE7     		b	.L133
+ 1958              	.L141:
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ 1959              		.loc 1 1640 9 view .LVU709
+ 1960 006e 0020     		movs	r0, #0
+ 1961 0070 DBE7     		b	.L133
+ 1962              	.L143:
+ 1963 0072 00BF     		.align	2
+ 1964              	.L142:
+ 1965 0074 00380240 		.word	1073887232
+ 1966              		.cfi_endproc
+ 1967              	.LFE144:
+ 1969              		.section	.text.HAL_RCCEx_DisablePLLI2S,"ax",%progbits
+ 1970              		.align	1
+ 1971              		.global	HAL_RCCEx_DisablePLLI2S
+ 1972              		.syntax unified
+ 1973              		.thumb
+ 1974              		.thumb_func
+ 1975              		.fpu fpv5-d16
+ 1977              	HAL_RCCEx_DisablePLLI2S:
+ 1978              	.LFB145:
+1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @brief  Disable PLLI2S.
+1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @retval HAL status
+1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
+1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** {
+ 1979              		.loc 1 1648 1 is_stmt 1 view -0
+ 1980              		.cfi_startproc
+ 1981              		@ args = 0, pretend = 0, frame = 0
+ 1982              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1983 0000 10B5     		push	{r4, lr}
+ 1984              	.LCFI5:
+ 1985              		.cfi_def_cfa_offset 8
+ARM GAS  /tmp/cc41FM7T.s 			page 70
+
+
+ 1986              		.cfi_offset 4, -8
+ 1987              		.cfi_offset 14, -4
+1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tickstart;
+ 1988              		.loc 1 1649 3 view .LVU711
+1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Disable the PLLI2S */
+1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   __HAL_RCC_PLLI2S_DISABLE();
+ 1989              		.loc 1 1652 3 view .LVU712
+ 1990 0002 0B4A     		ldr	r2, .L151
+ 1991 0004 1368     		ldr	r3, [r2]
+ 1992 0006 23F08063 		bic	r3, r3, #67108864
+ 1993 000a 1360     		str	r3, [r2]
+1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Wait till PLLI2S is disabled */
+1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   tickstart = HAL_GetTick();
+ 1994              		.loc 1 1655 3 view .LVU713
+ 1995              		.loc 1 1655 15 is_stmt 0 view .LVU714
+ 1996 000c FFF7FEFF 		bl	HAL_GetTick
+ 1997              	.LVL158:
+ 1998 0010 0446     		mov	r4, r0
+ 1999              	.LVL159:
+1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+ 2000              		.loc 1 1656 3 is_stmt 1 view .LVU715
+ 2001              	.L145:
+ 2002              		.loc 1 1656 8 view .LVU716
+ 2003              		.loc 1 1656 9 is_stmt 0 view .LVU717
+ 2004 0012 074B     		ldr	r3, .L151
+ 2005 0014 1B68     		ldr	r3, [r3]
+ 2006              		.loc 1 1656 8 view .LVU718
+ 2007 0016 13F0006F 		tst	r3, #134217728
+ 2008 001a 06D0     		beq	.L150
+1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ 2009              		.loc 1 1658 5 is_stmt 1 view .LVU719
+ 2010              		.loc 1 1658 9 is_stmt 0 view .LVU720
+ 2011 001c FFF7FEFF 		bl	HAL_GetTick
+ 2012              	.LVL160:
+ 2013              		.loc 1 1658 23 view .LVU721
+ 2014 0020 001B     		subs	r0, r0, r4
+ 2015              		.loc 1 1658 7 view .LVU722
+ 2016 0022 6428     		cmp	r0, #100
+ 2017 0024 F5D9     		bls	.L145
+1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* return in case of Timeout detected */
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       return HAL_TIMEOUT;
+ 2018              		.loc 1 1661 14 view .LVU723
+ 2019 0026 0320     		movs	r0, #3
+ 2020 0028 00E0     		b	.L146
+ 2021              	.L150:
+1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   return HAL_OK;
+ 2022              		.loc 1 1665 10 view .LVU724
+ 2023 002a 0020     		movs	r0, #0
+ 2024              	.L146:
+1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ARM GAS  /tmp/cc41FM7T.s 			page 71
+
+
+ 2025              		.loc 1 1666 1 view .LVU725
+ 2026 002c 10BD     		pop	{r4, pc}
+ 2027              	.LVL161:
+ 2028              	.L152:
+ 2029              		.loc 1 1666 1 view .LVU726
+ 2030 002e 00BF     		.align	2
+ 2031              	.L151:
+ 2032 0030 00380240 		.word	1073887232
+ 2033              		.cfi_endproc
+ 2034              	.LFE145:
+ 2036              		.section	.text.HAL_RCCEx_EnablePLLSAI,"ax",%progbits
+ 2037              		.align	1
+ 2038              		.global	HAL_RCCEx_EnablePLLSAI
+ 2039              		.syntax unified
+ 2040              		.thumb
+ 2041              		.thumb_func
+ 2042              		.fpu fpv5-d16
+ 2044              	HAL_RCCEx_EnablePLLSAI:
+ 2045              	.LVL162:
+ 2046              	.LFB146:
+1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @brief  Enable PLLSAI.
+1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @param  PLLSAIInit  pointer to an RCC_PLLSAIInitTypeDef structure that
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   *         contains the configuration information for the PLLSAI
+1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @retval HAL status
+1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit)
+1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** {
+ 2047              		.loc 1 1675 1 is_stmt 1 view -0
+ 2048              		.cfi_startproc
+ 2049              		@ args = 0, pretend = 0, frame = 0
+ 2050              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2051              		.loc 1 1675 1 is_stmt 0 view .LVU728
+ 2052 0000 38B5     		push	{r3, r4, r5, lr}
+ 2053              	.LCFI6:
+ 2054              		.cfi_def_cfa_offset 16
+ 2055              		.cfi_offset 3, -16
+ 2056              		.cfi_offset 4, -12
+ 2057              		.cfi_offset 5, -8
+ 2058              		.cfi_offset 14, -4
+ 2059 0002 0546     		mov	r5, r0
+1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tickstart;
+ 2060              		.loc 1 1676 3 is_stmt 1 view .LVU729
+1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Check for parameters */
+1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));
+ 2061              		.loc 1 1679 3 view .LVU730
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));
+ 2062              		.loc 1 1680 3 view .LVU731
+1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));
+ 2063              		.loc 1 1681 3 view .LVU732
+1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined(RCC_PLLSAICFGR_PLLSAIR)
+1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));
+ 2064              		.loc 1 1683 3 view .LVU733
+1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* RCC_PLLSAICFGR_PLLSAIR */
+1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ARM GAS  /tmp/cc41FM7T.s 			page 72
+
+
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Disable the PLLSAI */
+1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   __HAL_RCC_PLLSAI_DISABLE();
+ 2065              		.loc 1 1687 3 view .LVU734
+ 2066 0004 1B4A     		ldr	r2, .L164
+ 2067 0006 1368     		ldr	r3, [r2]
+ 2068 0008 23F08053 		bic	r3, r3, #268435456
+ 2069 000c 1360     		str	r3, [r2]
+1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Wait till PLLSAI is disabled */
+1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   tickstart = HAL_GetTick();
+ 2070              		.loc 1 1690 3 view .LVU735
+ 2071              		.loc 1 1690 15 is_stmt 0 view .LVU736
+ 2072 000e FFF7FEFF 		bl	HAL_GetTick
+ 2073              	.LVL163:
+ 2074              		.loc 1 1690 15 view .LVU737
+ 2075 0012 0446     		mov	r4, r0
+ 2076              	.LVL164:
+1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ 2077              		.loc 1 1691 3 is_stmt 1 view .LVU738
+ 2078              	.L154:
+ 2079              		.loc 1 1691 8 view .LVU739
+ 2080              		.loc 1 1691 9 is_stmt 0 view .LVU740
+ 2081 0014 174B     		ldr	r3, .L164
+ 2082 0016 1B68     		ldr	r3, [r3]
+ 2083              		.loc 1 1691 8 view .LVU741
+ 2084 0018 13F0005F 		tst	r3, #536870912
+ 2085 001c 06D0     		beq	.L162
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ 2086              		.loc 1 1693 5 is_stmt 1 view .LVU742
+ 2087              		.loc 1 1693 9 is_stmt 0 view .LVU743
+ 2088 001e FFF7FEFF 		bl	HAL_GetTick
+ 2089              	.LVL165:
+ 2090              		.loc 1 1693 23 view .LVU744
+ 2091 0022 001B     		subs	r0, r0, r4
+ 2092              		.loc 1 1693 7 view .LVU745
+ 2093 0024 6428     		cmp	r0, #100
+ 2094 0026 F5D9     		bls	.L154
+1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* return in case of Timeout detected */
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       return HAL_TIMEOUT;
+ 2095              		.loc 1 1696 14 view .LVU746
+ 2096 0028 0320     		movs	r0, #3
+ 2097              	.L155:
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Configure the PLLSAI division factors */
+1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
+1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ);
+1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #else
+1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+ARM GAS  /tmp/cc41FM7T.s 			page 73
+
+
+1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                           PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
+1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Enable the PLLSAI */
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   __HAL_RCC_PLLSAI_ENABLE();
+1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Wait till PLLSAI is ready */
+1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   tickstart = HAL_GetTick();
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* return in case of Timeout detected */
+1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       return HAL_TIMEOUT;
+1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****  return HAL_OK;
+1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ 2098              		.loc 1 1730 1 view .LVU747
+ 2099 002a 38BD     		pop	{r3, r4, r5, pc}
+ 2100              	.LVL166:
+ 2101              	.L162:
+1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****                           PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+ 2102              		.loc 1 1711 3 is_stmt 1 view .LVU748
+ 2103 002c 2A68     		ldr	r2, [r5]
+ 2104 002e EB68     		ldr	r3, [r5, #12]
+ 2105 0030 1B04     		lsls	r3, r3, #16
+ 2106 0032 43EA8213 		orr	r3, r3, r2, lsl #6
+ 2107 0036 6A68     		ldr	r2, [r5, #4]
+ 2108 0038 43EA0263 		orr	r3, r3, r2, lsl #24
+ 2109 003c AA68     		ldr	r2, [r5, #8]
+ 2110 003e 43EA0273 		orr	r3, r3, r2, lsl #28
+ 2111 0042 0C4A     		ldr	r2, .L164
+ 2112 0044 C2F88830 		str	r3, [r2, #136]
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+ 2113              		.loc 1 1716 3 view .LVU749
+ 2114 0048 1368     		ldr	r3, [r2]
+ 2115 004a 43F08053 		orr	r3, r3, #268435456
+ 2116 004e 1360     		str	r3, [r2]
+1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ 2117              		.loc 1 1719 3 view .LVU750
+1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ 2118              		.loc 1 1719 15 is_stmt 0 view .LVU751
+ 2119 0050 FFF7FEFF 		bl	HAL_GetTick
+ 2120              	.LVL167:
+ 2121 0054 0446     		mov	r4, r0
+ 2122              	.LVL168:
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 2123              		.loc 1 1720 3 is_stmt 1 view .LVU752
+ 2124              	.L157:
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 2125              		.loc 1 1720 8 view .LVU753
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 2126              		.loc 1 1720 9 is_stmt 0 view .LVU754
+ARM GAS  /tmp/cc41FM7T.s 			page 74
+
+
+ 2127 0056 074B     		ldr	r3, .L164
+ 2128 0058 1B68     		ldr	r3, [r3]
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+ 2129              		.loc 1 1720 8 view .LVU755
+ 2130 005a 13F0005F 		tst	r3, #536870912
+ 2131 005e 06D1     		bne	.L163
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 2132              		.loc 1 1722 5 is_stmt 1 view .LVU756
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 2133              		.loc 1 1722 9 is_stmt 0 view .LVU757
+ 2134 0060 FFF7FEFF 		bl	HAL_GetTick
+ 2135              	.LVL169:
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 2136              		.loc 1 1722 23 view .LVU758
+ 2137 0064 001B     		subs	r0, r0, r4
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+ 2138              		.loc 1 1722 7 view .LVU759
+ 2139 0066 6428     		cmp	r0, #100
+ 2140 0068 F5D9     		bls	.L157
+1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+ 2141              		.loc 1 1725 14 view .LVU760
+ 2142 006a 0320     		movs	r0, #3
+ 2143 006c DDE7     		b	.L155
+ 2144              	.L163:
+1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ 2145              		.loc 1 1729 9 view .LVU761
+ 2146 006e 0020     		movs	r0, #0
+ 2147 0070 DBE7     		b	.L155
+ 2148              	.L165:
+ 2149 0072 00BF     		.align	2
+ 2150              	.L164:
+ 2151 0074 00380240 		.word	1073887232
+ 2152              		.cfi_endproc
+ 2153              	.LFE146:
+ 2155              		.section	.text.HAL_RCCEx_DisablePLLSAI,"ax",%progbits
+ 2156              		.align	1
+ 2157              		.global	HAL_RCCEx_DisablePLLSAI
+ 2158              		.syntax unified
+ 2159              		.thumb
+ 2160              		.thumb_func
+ 2161              		.fpu fpv5-d16
+ 2163              	HAL_RCCEx_DisablePLLSAI:
+ 2164              	.LFB147:
+1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /**
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @brief  Disable PLLSAI.
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   * @retval HAL status
+1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   */
+1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** {
+ 2165              		.loc 1 1737 1 is_stmt 1 view -0
+ 2166              		.cfi_startproc
+ 2167              		@ args = 0, pretend = 0, frame = 0
+ 2168              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2169 0000 10B5     		push	{r4, lr}
+ 2170              	.LCFI7:
+ 2171              		.cfi_def_cfa_offset 8
+ARM GAS  /tmp/cc41FM7T.s 			page 75
+
+
+ 2172              		.cfi_offset 4, -8
+ 2173              		.cfi_offset 14, -4
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   uint32_t tickstart;
+ 2174              		.loc 1 1738 3 view .LVU763
+1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Disable the PLLSAI */
+1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   __HAL_RCC_PLLSAI_DISABLE();
+ 2175              		.loc 1 1741 3 view .LVU764
+ 2176 0002 0B4A     		ldr	r2, .L173
+ 2177 0004 1368     		ldr	r3, [r2]
+ 2178 0006 23F08053 		bic	r3, r3, #268435456
+ 2179 000a 1360     		str	r3, [r2]
+1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   /* Wait till PLLSAI is disabled */
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   tickstart = HAL_GetTick();
+ 2180              		.loc 1 1744 3 view .LVU765
+ 2181              		.loc 1 1744 15 is_stmt 0 view .LVU766
+ 2182 000c FFF7FEFF 		bl	HAL_GetTick
+ 2183              	.LVL170:
+ 2184 0010 0446     		mov	r4, r0
+ 2185              	.LVL171:
+1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ 2186              		.loc 1 1745 3 is_stmt 1 view .LVU767
+ 2187              	.L167:
+ 2188              		.loc 1 1745 8 view .LVU768
+ 2189              		.loc 1 1745 9 is_stmt 0 view .LVU769
+ 2190 0012 074B     		ldr	r3, .L173
+ 2191 0014 1B68     		ldr	r3, [r3]
+ 2192              		.loc 1 1745 8 view .LVU770
+ 2193 0016 13F0005F 		tst	r3, #536870912
+ 2194 001a 06D0     		beq	.L172
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   {
+1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ 2195              		.loc 1 1747 5 is_stmt 1 view .LVU771
+ 2196              		.loc 1 1747 9 is_stmt 0 view .LVU772
+ 2197 001c FFF7FEFF 		bl	HAL_GetTick
+ 2198              	.LVL172:
+ 2199              		.loc 1 1747 23 view .LVU773
+ 2200 0020 001B     		subs	r0, r0, r4
+ 2201              		.loc 1 1747 7 view .LVU774
+ 2202 0022 6428     		cmp	r0, #100
+ 2203 0024 F5D9     		bls	.L167
+1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     {
+1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       /* return in case of Timeout detected */
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****       return HAL_TIMEOUT;
+ 2204              		.loc 1 1750 14 view .LVU775
+ 2205 0026 0320     		movs	r0, #3
+ 2206 0028 00E0     		b	.L168
+ 2207              	.L172:
+1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****     }
+1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   }
+1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** 
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c ****   return HAL_OK;
+ 2208              		.loc 1 1754 10 view .LVU776
+ 2209 002a 0020     		movs	r0, #0
+ 2210              	.L168:
+1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** }
+ARM GAS  /tmp/cc41FM7T.s 			page 76
+
+
+ 2211              		.loc 1 1755 1 view .LVU777
+ 2212 002c 10BD     		pop	{r4, pc}
+ 2213              	.LVL173:
+ 2214              	.L174:
+ 2215              		.loc 1 1755 1 view .LVU778
+ 2216 002e 00BF     		.align	2
+ 2217              	.L173:
+ 2218 0030 00380240 		.word	1073887232
+ 2219              		.cfi_endproc
+ 2220              	.LFE147:
+ 2222              		.text
+ 2223              	.Letext0:
+ 2224              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 2225              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 2226              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 2227              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 2228              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h"
+ 2229              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ARM GAS  /tmp/cc41FM7T.s 			page 77
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_rcc_ex.c
+     /tmp/cc41FM7T.s:17     .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 $t
+     /tmp/cc41FM7T.s:25     .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 HAL_RCCEx_PeriphCLKConfig
+     /tmp/cc41FM7T.s:511    .text.HAL_RCCEx_PeriphCLKConfig:00000000000002e4 $d
+     /tmp/cc41FM7T.s:515    .text.HAL_RCCEx_PeriphCLKConfig:00000000000002e8 $t
+     /tmp/cc41FM7T.s:949    .text.HAL_RCCEx_PeriphCLKConfig:0000000000000504 $d
+     /tmp/cc41FM7T.s:956    .text.HAL_RCCEx_PeriphCLKConfig:0000000000000510 $t
+     /tmp/cc41FM7T.s:1124   .text.HAL_RCCEx_PeriphCLKConfig:00000000000005fc $d
+     /tmp/cc41FM7T.s:1129   .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 $t
+     /tmp/cc41FM7T.s:1136   .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 HAL_RCCEx_GetPeriphCLKConfig
+     /tmp/cc41FM7T.s:1395   .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000180 $d
+     /tmp/cc41FM7T.s:1401   .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 $t
+     /tmp/cc41FM7T.s:1408   .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 HAL_RCCEx_GetPeriphCLKFreq
+     /tmp/cc41FM7T.s:1843   .text.HAL_RCCEx_GetPeriphCLKFreq:00000000000001d4 $d
+     /tmp/cc41FM7T.s:1851   .text.HAL_RCCEx_EnablePLLI2S:0000000000000000 $t
+     /tmp/cc41FM7T.s:1858   .text.HAL_RCCEx_EnablePLLI2S:0000000000000000 HAL_RCCEx_EnablePLLI2S
+     /tmp/cc41FM7T.s:1965   .text.HAL_RCCEx_EnablePLLI2S:0000000000000074 $d
+     /tmp/cc41FM7T.s:1970   .text.HAL_RCCEx_DisablePLLI2S:0000000000000000 $t
+     /tmp/cc41FM7T.s:1977   .text.HAL_RCCEx_DisablePLLI2S:0000000000000000 HAL_RCCEx_DisablePLLI2S
+     /tmp/cc41FM7T.s:2032   .text.HAL_RCCEx_DisablePLLI2S:0000000000000030 $d
+     /tmp/cc41FM7T.s:2037   .text.HAL_RCCEx_EnablePLLSAI:0000000000000000 $t
+     /tmp/cc41FM7T.s:2044   .text.HAL_RCCEx_EnablePLLSAI:0000000000000000 HAL_RCCEx_EnablePLLSAI
+     /tmp/cc41FM7T.s:2151   .text.HAL_RCCEx_EnablePLLSAI:0000000000000074 $d
+     /tmp/cc41FM7T.s:2156   .text.HAL_RCCEx_DisablePLLSAI:0000000000000000 $t
+     /tmp/cc41FM7T.s:2163   .text.HAL_RCCEx_DisablePLLSAI:0000000000000000 HAL_RCCEx_DisablePLLSAI
+     /tmp/cc41FM7T.s:2218   .text.HAL_RCCEx_DisablePLLSAI:0000000000000030 $d
+
+UNDEFINED SYMBOLS
+HAL_GetTick
diff --git a/build/stm32f7xx_hal_rcc_ex.o b/build/stm32f7xx_hal_rcc_ex.o
new file mode 100644
index 0000000..412c7fb
Binary files /dev/null and b/build/stm32f7xx_hal_rcc_ex.o differ
diff --git a/build/stm32f7xx_hal_sd.d b/build/stm32f7xx_hal_sd.d
new file mode 100644
index 0000000..5f5c956
--- /dev/null
+++ b/build/stm32f7xx_hal_sd.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_sd.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_sd.lst b/build/stm32f7xx_hal_sd.lst
new file mode 100644
index 0000000..8feeae6
--- /dev/null
+++ b/build/stm32f7xx_hal_sd.lst
@@ -0,0 +1,12877 @@
+ARM GAS  /tmp/ccQEYyKb.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_sd.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.SD_DMATransmitCplt,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	SD_DMATransmitCplt:
+  25              	.LVL0:
+  26              	.LFB168:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @file    stm32f7xx_hal_sd.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief   SD card HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          functionalities of the Secure Digital (SD) peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *           + Initialization and de-initialization functions
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *           + IO operation functions
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *           + Peripheral Control functions
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *           + Peripheral State functions
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ******************************************************************************
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @attention
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * Copyright (c) 2017 STMicroelectronics.
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * All rights reserved.
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * in the root directory of this software component.
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ******************************************************************************
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   @verbatim
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ==============================================================================
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                         ##### How to use this driver #####
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ==============================================================================
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     This driver implements a high level communication layer for read and write from/to
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     the user in HAL_SD_MspInit() function (MSP layer).
+ARM GAS  /tmp/ccQEYyKb.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Basically, the MSP layer configuration should be the same as we provide in the
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     examples.
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     You can easily tailor this configuration according to hardware resources.
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     This driver is a generic layered driver for SDMMC memories which uses the HAL
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     SDMMC driver functions to interface with SD and uSD cards devices.
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     It is used as follows:
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API:
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         (##) SDMMC pins configuration for SD card
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENAB
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                   and according to your pin assignment;
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****              and HAL_SD_WriteBlocks_DMA() APIs).
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) Configure the SDMMC and DMA interrupt priorities using functions
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                   HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                   and __HAL_SD_DISABLE_IT() inside the communication process.
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                   and __HAL_SD_CLEAR_IT()
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****              and HAL_SD_WriteBlocks_IT() APIs).
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                   and __HAL_SD_DISABLE_IT() inside the communication process.
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                   and __HAL_SD_CLEAR_IT()
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *** SD Card Initialization and configuration ***
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ================================================
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data tra
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     This function provide the following operations:
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (#) Apply the SD Card initialization process at 400KHz and check the SD Card
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         type (Standard Capacity or High Capacity). You can change or adapt this
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         frequency by adjusting the "ClockDiv" field.
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         The SD Card frequency (SDMMC_CK) is computed as follows:
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****            SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         In initialization mode and according to the SD Card standard,
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         This phase of initialization is done through SDMMC_Init() and
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         SDMMC_PowerState_ON() SDMMC low level APIs.
+ARM GAS  /tmp/ccQEYyKb.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (#) Initialize the SD card. The API used is HAL_SD_InitCard().
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         This phase allows the card initialization and identification
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         and check the SD Card type (Standard Capacity or High Capacity)
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         The initialization flow is compatible with SD standard.
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         of plug-off plug-in.
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (#) Configure the SD Card Data transfer frequency. You can change or adapt this
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         frequency by adjusting the "ClockDiv" field.
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         In transfer mode and according to the SD Card standard, make sure that the
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         To be able to use a frequency higher than 24MHz, you should use the SDMMC
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         peripheral in bypass mode. Refer to the corresponding reference manual
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         for more details.
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (#) Select the corresponding SD Card according to the address read with the step 2.
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (#) Configure the SD Card in wide bus mode: 4-bits data.
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *** SD Card Read operation ***
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ==============================
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         This function support only 512-bytes block length (the block size should be
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         chosen as 512 bytes).
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         You can choose either one block read operation or multiple block read operation
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         by adjusting the "NumberOfBlocks" parameter.
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         After this, you have to ensure that the transfer is done correctly. The check is done
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         through HAL_SD_GetCardState() function for SD card state.
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         This function support only 512-bytes block length (the block size should be
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         chosen as 512 bytes).
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         You can choose either one block read operation or multiple block read operation
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         by adjusting the "NumberOfBlocks" parameter.
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         After this, you have to ensure that the transfer is done correctly. The check is done
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         through HAL_SD_GetCardState() function for SD card state.
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         You could also check the DMA transfer process through the SD Rx interrupt event.
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         This function support only 512-bytes block length (the block size should be
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         chosen as 512 bytes).
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         You can choose either one block read operation or multiple block read operation
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         by adjusting the "NumberOfBlocks" parameter.
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         After this, you have to ensure that the transfer is done correctly. The check is done
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         through HAL_SD_GetCardState() function for SD card state.
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         You could also check the IT transfer process through the SD Rx interrupt event.
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *** SD Card Write operation ***
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ===============================
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         This function support only 512-bytes block length (the block size should be
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         chosen as 512 bytes).
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         You can choose either one block read operation or multiple block read operation
+ARM GAS  /tmp/ccQEYyKb.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         by adjusting the "NumberOfBlocks" parameter.
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         After this, you have to ensure that the transfer is done correctly. The check is done
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         through HAL_SD_GetCardState() function for SD card state.
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         This function support only 512-bytes block length (the block size should be
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         chosen as 512 bytes).
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         You can choose either one block read operation or multiple block read operation
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         by adjusting the "NumberOfBlocks" parameter.
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         After this, you have to ensure that the transfer is done correctly. The check is done
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         through HAL_SD_GetCardState() function for SD card state.
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         You could also check the DMA transfer process through the SD Tx interrupt event.
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         This function support only 512-bytes block length (the block size should be
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         chosen as 512 bytes).
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         You can choose either one block read operation or multiple block read operation
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         by adjusting the "NumberOfBlocks" parameter.
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         After this, you have to ensure that the transfer is done correctly. The check is done
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         through HAL_SD_GetCardState() function for SD card state.
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         You could also check the IT transfer process through the SD Tx interrupt event.
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *** SD card status ***
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ======================
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) The SD Status contains status bits that are related to the SD Memory
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *** SD card information ***
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ===========================
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         It returns useful information about the SD card such as block size, card type,
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         block number ...
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *** SD card CSD register ***
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ============================
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         Some of the CSD parameters are useful for card initialization and identification.
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *** SD card CID register ***
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ============================
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         Some of the CSD parameters are useful for card initialization and identification.
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *** SD HAL driver macros list ***
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ==================================
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Below the list of most used macros in SD HAL driver.
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) __HAL_SD_ENABLE : Enable the SD device
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) __HAL_SD_DISABLE : Disable the SD device
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) __HAL_SD_DMA_ENABLE: Enable the SDMMC DMA transfer
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) __HAL_SD_DMA_DISABLE: Disable the SDMMC DMA transfer
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
+ARM GAS  /tmp/ccQEYyKb.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (@) You can refer to the SD HAL driver header file for more useful macros
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *** Callback registration ***
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   =============================================
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     allows the user to configure dynamically the driver callbacks.
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Use Functions HAL_SD_RegisterCallback() to register a user callback,
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     it allows to register following callbacks:
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) TxCpltCallback : callback when a transmission transfer is completed.
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) RxCpltCallback : callback when a reception transfer is completed.
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) ErrorCallback : callback when error occurs.
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) AbortCpltCallback : callback when abort is completed.
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) MspInitCallback    : SD MspInit.
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) MspDeInitCallback  : SD MspDeInit.
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     This function takes as parameters the HAL peripheral handle, the Callback ID
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     and a pointer to the user callback function.
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Use function HAL_SD_UnRegisterCallback() to reset a callback to the default
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     weak (surcharged) function. It allows to reset following callbacks:
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) TxCpltCallback : callback when a transmission transfer is completed.
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) RxCpltCallback : callback when a reception transfer is completed.
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) ErrorCallback : callback when error occurs.
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) AbortCpltCallback : callback when abort is completed.
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) MspInitCallback    : SD MspInit.
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (+) MspDeInitCallback  : SD MspDeInit.
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     This function) takes as parameters the HAL peripheral handle and the Callback ID.
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Exception done for MspInit and MspDeInit callbacks that are respectively
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     reset to the legacy weak (surcharged) functions in the HAL_SD_Init
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     and  HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Callbacks can be registered/unregistered in READY state only.
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     during the Init/DeInit.
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     In that case first register the MspInit/MspDeInit user callbacks
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     using HAL_SD_RegisterCallback before calling HAL_SD_DeInit
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     or HAL_SD_Init function.
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     not defined, the callback registering feature is not available
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     and weak (surcharged) callbacks are used.
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   @endverbatim
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ******************************************************************************
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Includes ------------------------------------------------------------------*/
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #include "stm32f7xx_hal.h"
+ARM GAS  /tmp/ccQEYyKb.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined(SDMMC1)
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup STM32F7xx_HAL_Driver
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @{
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @{
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #ifdef HAL_SD_MODULE_ENABLED
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private typedef -----------------------------------------------------------*/
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private define ------------------------------------------------------------*/
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Private_Defines
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @{
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @}
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private macro -------------------------------------------------------------*/
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private variables ---------------------------------------------------------*/
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private function prototypes -----------------------------------------------*/
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private functions ---------------------------------------------------------*/
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @defgroup SD_Private_Functions SD Private Functions
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @{
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_PowerOFF(SD_HandleTypeDef *hsd);
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_Write_IT(SD_HandleTypeDef *hsd);
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_Read_IT(SD_HandleTypeDef *hsd);
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMAError(DMA_HandleTypeDef *hdma);
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMATxAbort(DMA_HandleTypeDef *hdma);
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMARxAbort(DMA_HandleTypeDef *hdma);
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @}
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Exported functions --------------------------------------------------------*/
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Exported_Functions
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @{
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Exported_Functions_Group1
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****  *  @brief   Initialization and de-initialization functions
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****  *
+ARM GAS  /tmp/ccQEYyKb.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @verbatim
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ==============================================================================
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           ##### Initialization and de-initialization functions #####
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ==============================================================================
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     This section provides functions allowing to initialize/de-initialize the SD
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     card device to be ready for use.
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @endverbatim
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @{
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Initializes the SD according to the specified parameters in the
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             SD_HandleTypeDef and create the associated handle.
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to the SD handle
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check the SD handle allocation */
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd == NULL)
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check the parameters */
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge));
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass));
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->State == HAL_SD_STATE_RESET)
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Allocate lock resource and initialize it */
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Lock = HAL_UNLOCKED;
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Reset Callback pointers in HAL_SD_STATE_RESET only */
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->TxCpltCallback    = HAL_SD_TxCpltCallback;
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->RxCpltCallback    = HAL_SD_RxCpltCallback;
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCallback     = HAL_SD_ErrorCallback;
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(hsd->MspInitCallback == NULL)
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->MspInitCallback = HAL_SD_MspInit;
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Init the low level hardware */
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->MspInitCallback(hsd);
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     HAL_SD_MspInit(hsd);
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ARM GAS  /tmp/ccQEYyKb.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_BUSY;
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Initialize the Card parameters */
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if (HAL_SD_InitCard(hsd) != HAL_OK)
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Initialize the error code */
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Initialize the SD operation */
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Context = SD_CONTEXT_NONE;
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Initialize the SD state */
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_OK;
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Initializes the SD Card.
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   This function initializes the SD card. It could be used when a card
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             re-initialization is needed.
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_StatusTypeDef status;
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_InitTypeDef Init;
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Default SDMMC peripheral configuration for SD card initialization */
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.ClockBypass         = SDMMC_CLOCK_BYPASS_DISABLE;
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.BusWide             = SDMMC_BUS_WIDE_1B;
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.ClockDiv            = SDMMC_INIT_CLK_DIV;
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Initialize SDMMC peripheral interface with default configuration */
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   status = SDMMC_Init(hsd->Instance, Init);
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(status != HAL_OK)
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Disable SDMMC Clock */
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_SD_DISABLE(hsd);
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Set Power State to ON */
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   (void)SDMMC_PowerState_ON(hsd->Instance);
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Enable SDMMC Clock */
+ARM GAS  /tmp/ccQEYyKb.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_SD_ENABLE(hsd);
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Required power up waiting time before starting the SD initialization  sequence */
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_Delay(2);
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Identify card operating voltage */
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SD_PowerON(hsd);
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Card initialization */
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SD_InitCard(hsd);
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Set Block Size for Card */
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Clear all the static flags */
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_OK;
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  De-Initializes the SD card.
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check the SD handle allocation */
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd == NULL)
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check the parameters */
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_BUSY;
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Set SD power state to off */
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_PowerOFF(hsd);
+ARM GAS  /tmp/ccQEYyKb.s 			page 10
+
+
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->MspDeInitCallback == NULL)
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* DeInit the low level hardware */
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->MspDeInitCallback(hsd);
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* De-Initialize the MSP layer */
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_MspDeInit(hsd);
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_RESET;
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_OK;
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Initializes the SD MSP.
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   UNUSED(hsd);
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             the HAL_SD_MspInit could be implemented in the user file
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****    */
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  De-Initialize SD MSP.
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   UNUSED(hsd);
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             the HAL_SD_MspDeInit could be implemented in the user file
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****    */
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @}
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Exported_Functions_Group2
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****  *  @brief   Data transfer functions
+ARM GAS  /tmp/ccQEYyKb.s 			page 11
+
+
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****  *
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @verbatim
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ==============================================================================
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                         ##### IO operation functions #####
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ==============================================================================
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     This subsection provides a set of functions allowing to manage the data
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     transfer from/to SD card.
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @endverbatim
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @{
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Reads block(s) from a specified address in a card. The Data transfer
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         is managed by polling mode.
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   This API should be followed by a check on the card state through
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         HAL_SD_GetCardState().
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pData: pointer to the buffer that will contain the received data
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  BlockAdd: Block Address from where data is to be read
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  NumberOfBlocks: Number of SD blocks to read
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  Timeout: Specify timeout value
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint3
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t tickstart = HAL_GetTick();
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count, data, dataremaining;
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint8_t *tempbuff = pData;
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(NULL == pData)
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->State == HAL_SD_STATE_READY)
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_BUSY;
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Initialize data control register */
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Instance->DCTRL = 0U;
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ARM GAS  /tmp/ccQEYyKb.s 			page 12
+
+
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       add *= 512U;
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Configure the SD DPSM (Data Path State Machine) */
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataTimeOut   = SDMMC_DATATIMEOUT;
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Read block(s) in polling mode */
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(NumberOfBlocks > 1U)
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Read Multi Block command */
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Read Single Block command */
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Poll on SDMMC flags */
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     dataremaining = config.DataLength;
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | 
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U))
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Read data from SDMMC Rx FIFO */
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         for(count = 0U; count < 8U; count++)
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           data = SDMMC_ReadFIFO(hsd->Instance);
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           *tempbuff = (uint8_t)(data & 0xFFU);
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ARM GAS  /tmp/ccQEYyKb.s 			page 13
+
+
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Clear all the static flags */
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State= HAL_SD_STATE_READY;
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_TIMEOUT;
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Send stop transmission command in case of multiblock read */
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(hsd->SdCard.CardType != CARD_SECURED)
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Send stop transmission command */
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           /* Clear all the static flags */
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->ErrorCode |= errorstate;
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->State = HAL_SD_STATE_READY;
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->Context = SD_CONTEXT_NONE;
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           return HAL_ERROR;
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Get error state */
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+ARM GAS  /tmp/ccQEYyKb.s 			page 14
+
+
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Nothing to do */
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Empty FIFO if there is still any data */
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U))
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       data = SDMMC_ReadFIFO(hsd->Instance);
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tempbuff = (uint8_t)(data & 0xFFU);
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Clear all the static flags */
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State= HAL_SD_STATE_READY;
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Clear all the static flags */
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_OK;
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Allows to write block(s) to a specified address in a card. The Data
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         transfer is managed by polling mode.
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   This API should be followed by a check on the card state through
+ARM GAS  /tmp/ccQEYyKb.s 			page 15
+
+
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         HAL_SD_GetCardState().
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pData: pointer to the buffer that will contain the data to transmit
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  BlockAdd: Block Address where data will be written
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  NumberOfBlocks: Number of SD blocks to write
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  Timeout: Specify timeout value
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t tickstart = HAL_GetTick();
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count, data, dataremaining;
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint8_t *tempbuff = pData;
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(NULL == pData)
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->State == HAL_SD_STATE_READY)
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_BUSY;
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Initialize data control register */
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Instance->DCTRL = 0U;
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       add *= 512U;
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Configure the SD DPSM (Data Path State Machine) */
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataTimeOut   = SDMMC_DATATIMEOUT;
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Write Blocks in Polling mode */
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(NumberOfBlocks > 1U)
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 16
+
+
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Write Multi Block command */
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Write Single Block command */
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Write block(s) in polling mode */
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     dataremaining = config.DataLength;
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U))
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Write data to SDMMC Tx FIFO */
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         for(count = 0U; count < 8U; count++)
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           data = (uint32_t)(*tempbuff);
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           data |= ((uint32_t)(*tempbuff) << 8U);
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           data |= ((uint32_t)(*tempbuff) << 16U);
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           data |= ((uint32_t)(*tempbuff) << 24U);
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Clear all the static flags */
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= errorstate;
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_TIMEOUT;
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Send stop transmission command in case of multiblock write */
+ARM GAS  /tmp/ccQEYyKb.s 			page 17
+
+
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(hsd->SdCard.CardType != CARD_SECURED)
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Send stop transmission command */
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           /* Clear all the static flags */
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->ErrorCode |= errorstate;
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->State = HAL_SD_STATE_READY;
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->Context = SD_CONTEXT_NONE;
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           return HAL_ERROR;
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Get error state */
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Nothing to do */
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Clear all the static flags */
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_OK;
+ARM GAS  /tmp/ccQEYyKb.s 			page 18
+
+
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Reads block(s) from a specified address in a card. The Data transfer
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         is managed in interrupt mode.
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   This API should be followed by a check on the card state through
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         HAL_SD_GetCardState().
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   You could also check the IT transfer process through the SD Rx
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         interrupt event.
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pData: Pointer to the buffer that will contain the received data
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  BlockAdd: Block Address from where data is to be read
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  NumberOfBlocks: Number of blocks to read.
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, ui
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(NULL == pData)
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->State == HAL_SD_STATE_READY)
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_BUSY;
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Initialize data control register */
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Instance->DCTRL = 0U;
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->pRxBuffPtr = pData;
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DA
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       add *= 512U;
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ARM GAS  /tmp/ccQEYyKb.s 			page 19
+
+
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Configure the SD DPSM (Data Path State Machine) */
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataTimeOut   = SDMMC_DATATIMEOUT;
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Read Blocks in IT mode */
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(NumberOfBlocks > 1U)
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Read Multi Block command */
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Read Single Block command */
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_OK;
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_BUSY;
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Writes block(s) to a specified address in a card. The Data transfer
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         is managed in interrupt mode.
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   This API should be followed by a check on the card state through
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         HAL_SD_GetCardState().
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   You could also check the IT transfer process through the SD Tx
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         interrupt event.
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pData: Pointer to the buffer that will contain the data to transmit
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  BlockAdd: Block Address where data will be written
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  NumberOfBlocks: Number of blocks to write
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, u
+ARM GAS  /tmp/ccQEYyKb.s 			page 20
+
+
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(NULL == pData)
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->State == HAL_SD_STATE_READY)
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode = HAL_SD_ERROR_NONE;
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_BUSY;
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Initialize data control register */
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Instance->DCTRL = 0U;
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->pTxBuffPtr = pData;
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Enable transfer interrupts */
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_D
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       add *= 512U;
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Write Blocks in Polling mode */
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(NumberOfBlocks > 1U)
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
+1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Write Multi Block command */
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Write Single Block command */
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+ARM GAS  /tmp/ccQEYyKb.s 			page 21
+
+
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Configure the SD DPSM (Data Path State Machine) */
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataTimeOut   = SDMMC_DATATIMEOUT;
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_OK;
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_BUSY;
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Reads block(s) from a specified address in a card. The Data transfer
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         is managed by DMA mode.
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   This API should be followed by a check on the card state through
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         HAL_SD_GetCardState().
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   You could also check the DMA transfer process through the SD Rx
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         interrupt event.
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer SD handle
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pData: Pointer to the buffer that will contain the received data
+1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  BlockAdd: Block Address from where data is to be read
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  NumberOfBlocks: Number of blocks to read.
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, u
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(NULL == pData)
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->State == HAL_SD_STATE_READY)
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode = HAL_SD_ERROR_NONE;
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 22
+
+
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_BUSY;
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Initialize data control register */
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Instance->DCTRL = 0U;
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DA
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Set the DMA transfer complete callback */
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Set the DMA error callback */
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->hdmarx->XferErrorCallback = SD_DMAError;
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Set the DMA Abort callback */
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->hdmarx->XferAbortCallback = NULL;
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Force DMA Direction */
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction);
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Enable the DMA Channel */
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BL
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Enable SD DMA transfer */
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_DMA_ENABLE(hsd);
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         add *= 512U;
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Configure the SD DPSM (Data Path State Machine) */
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataTimeOut   = SDMMC_DATATIMEOUT;
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DPSM          = SDMMC_DPSM_ENABLE;
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (void)SDMMC_ConfigData(hsd->Instance, &config);
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Read Blocks in DMA mode */
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(NumberOfBlocks > 1U)
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Read Multi Block command */
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       else
+ARM GAS  /tmp/ccQEYyKb.s 			page 23
+
+
+1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Read Single Block command */
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(errorstate != HAL_SD_ERROR_NONE)
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Clear all the static flags */
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= errorstate;
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_OK;
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_BUSY;
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Writes block(s) to a specified address in a card. The Data transfer
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         is managed by DMA mode.
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   This API should be followed by a check on the card state through
+1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         HAL_SD_GetCardState().
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   You could also check the DMA transfer process through the SD Tx
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         interrupt event.
+1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pData: Pointer to the buffer that will contain the data to transmit
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  BlockAdd: Block Address where data will be written
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  NumberOfBlocks: Number of blocks to write
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, 
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(NULL == pData)
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->State == HAL_SD_STATE_READY)
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode = HAL_SD_ERROR_NONE;
+1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ARM GAS  /tmp/ccQEYyKb.s 			page 24
+
+
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_BUSY;
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Initialize data control register */
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Instance->DCTRL = 0U;
+1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Enable SD Error interrupts */
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR));   
+1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Set the DMA transfer complete callback */
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
+1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Set the DMA error callback */
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->hdmatx->XferErrorCallback = SD_DMAError;
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Set the DMA Abort callback */
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->hdmatx->XferAbortCallback = NULL;
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       add *= 512U;
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Write Blocks in Polling mode */
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(NumberOfBlocks > 1U)
+1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Write Multi Block command */
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Write Single Block command */
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Enable SDMMC DMA transfer */
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_DMA_ENABLE(hsd);
+1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Force DMA Direction */
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction);
+1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 25
+
+
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Enable the DMA Channel */
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BL
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR));   
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Configure the SD DPSM (Data Path State Machine) */
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataTimeOut   = SDMMC_DATATIMEOUT;
+1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DPSM          = SDMMC_DPSM_ENABLE;
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (void)SDMMC_ConfigData(hsd->Instance, &config);
+1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_OK;
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_BUSY;
+1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Erases the specified memory area of the given SD card.
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @note   This API should be followed by a check on the card state through
+1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         HAL_SD_GetCardState().
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  BlockStartAdd: Start Block address
+1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  BlockEndAdd: End Block address
+1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t start_add = BlockStartAdd;
+1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t end_add = BlockEndAdd;
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->State == HAL_SD_STATE_READY)
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode = HAL_SD_ERROR_NONE;
+1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(end_add < start_add)
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(end_add > (hsd->SdCard.LogBlockNbr))
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ARM GAS  /tmp/ccQEYyKb.s 			page 26
+
+
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_BUSY;
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Check if the card command class supports erase command */
+1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Get start and end block for high capacity cards */
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       start_add *= 512U;
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       end_add   *= 512U;
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(hsd->SdCard.CardType != CARD_SECURED)
+1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
+1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(errorstate != HAL_SD_ERROR_NONE)
+1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Clear all the static flags */
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= errorstate;
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(errorstate != HAL_SD_ERROR_NONE)
+1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Clear all the static flags */
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= errorstate;
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ARM GAS  /tmp/ccQEYyKb.s 			page 27
+
+
+1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Send CMD38 ERASE */
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdErase(hsd->Instance);
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_OK;
+1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_BUSY;
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  This function handles SD card interrupt request.
+1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t context = hsd->Context;
+1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check for SDMMC interrupt flags */
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     SD_Read_IT(hsd);
+1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
+1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND  | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                              SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR  | SDMMC_IT_TXFIFOHE |\
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                              SDMMC_IT_RXFIFOHF);
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN);
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((context & SD_CONTEXT_IT) != 0U)
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPL
+1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->ErrorCode |= errorstate;
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ARM GAS  /tmp/ccQEYyKb.s 			page 28
+
+
+1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->ErrorCallback(hsd);
+1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           HAL_SD_ErrorCallback(hsd);
+1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear all the static flags */
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_B
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->RxCpltCallback(hsd);
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         HAL_SD_RxCpltCallback(hsd);
+1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       else
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->TxCpltCallback(hsd);
+1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         HAL_SD_TxCpltCallback(hsd);
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else if((context & SD_CONTEXT_DMA) != 0U)
+1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->ErrorCode |= errorstate;
+1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->ErrorCallback(hsd);
+1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           HAL_SD_ErrorCallback(hsd);
+1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_B
+1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         in the SD DCTRL register */
+1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->TxCpltCallback(hsd);
+1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         HAL_SD_TxCpltCallback(hsd);
+1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ARM GAS  /tmp/ccQEYyKb.s 			page 29
+
+
+1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Nothing to do */
+1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0
+1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     SD_Write_IT(hsd);
+1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | S
+1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Set Error code */
+1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL) != RESET)
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT) != RESET)
+1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR) != RESET)
+1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR) != RESET)
+1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Clear All flags */
+1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Disable all interrupts */
+1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                              SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((context & SD_CONTEXT_IT) != 0U)
+1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Set the SD state to ready to be able to start again the process */
+1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCallback(hsd);
+1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       HAL_SD_ErrorCallback(hsd);
+1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else if((context & SD_CONTEXT_DMA) != 0U)
+1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Abort the SD DMA channel */
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE
+ARM GAS  /tmp/ccQEYyKb.s 			page 30
+
+
+1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Set the DMA Tx abort callback */
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Abort DMA in IT mode */
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           SD_DMATxAbort(hsd->hdmatx);
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTI
+1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Set the DMA Rx abort callback */
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Abort DMA in IT mode */
+1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           SD_DMARxAbort(hsd->hdmarx);
+1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       else
+1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode = HAL_SD_ERROR_NONE;
+1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->AbortCpltCallback(hsd);
+1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         HAL_SD_AbortCallback(hsd);
+1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Nothing to do */
+1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Nothing to do */
+1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief return the SD state
+1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param hsd: Pointer to sd handle
+1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL state
+1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
+1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return hsd->State;
+1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief  Return the SD error code
+1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param  hsd : Pointer to a SD_HandleTypeDef structure that contains
+1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *              the configuration information.
+1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval SD Error Code
+ARM GAS  /tmp/ccQEYyKb.s 			page 31
+
+
+1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
+1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return hsd->ErrorCode;
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief Tx Transfer completed callbacks
+1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param hsd: Pointer to SD handle
+1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   UNUSED(hsd);
+1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             the HAL_SD_TxCpltCallback can be implemented in the user file
+1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****    */
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief Rx Transfer completed callbacks
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param hsd: Pointer SD handle
+1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   UNUSED(hsd);
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             the HAL_SD_RxCpltCallback can be implemented in the user file
+1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****    */
+1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief SD error callbacks
+1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param hsd: Pointer SD handle
+1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
+1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   UNUSED(hsd);
+1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             the HAL_SD_ErrorCallback can be implemented in the user file
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****    */
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief SD Abort callbacks
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param hsd: Pointer SD handle
+1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+ARM GAS  /tmp/ccQEYyKb.s 			page 32
+
+
+1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   UNUSED(hsd);
+1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             the HAL_SD_AbortCallback can be implemented in the user file
+1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****    */
+1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Register a User SD Callback
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         To be used instead of the weak (surcharged) predefined callback
+1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param hsd : SD handle
+1756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param CallbackID : ID of the callback to be registered
+1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *        This parameter can be one of the following values:
+1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID
+1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID
+1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID
+1761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID
+1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID
+1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+1764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param pCallback : pointer to the Callback function
+1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval status
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackI
+1768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_StatusTypeDef status = HAL_OK;
+1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(pCallback == NULL)
+1772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Update the error code */
+1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+1776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Process locked */
+1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_LOCK(hsd);
+1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->State == HAL_SD_STATE_READY)
+1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     switch (CallbackID)
+1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_TX_CPLT_CB_ID :
+1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->TxCpltCallback = pCallback;
+1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_RX_CPLT_CB_ID :
+1789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->RxCpltCallback = pCallback;
+1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_ERROR_CB_ID :
+1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCallback = pCallback;
+1793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_ABORT_CB_ID :
+1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->AbortCpltCallback = pCallback;
+1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_MSP_INIT_CB_ID :
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->MspInitCallback = pCallback;
+ARM GAS  /tmp/ccQEYyKb.s 			page 33
+
+
+1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_MSP_DEINIT_CB_ID :
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->MspDeInitCallback = pCallback;
+1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     default :
+1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Update the error code */
+1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* update return status */
+1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       status =  HAL_ERROR;
+1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else if (hsd->State == HAL_SD_STATE_RESET)
+1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     switch (CallbackID)
+1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_MSP_INIT_CB_ID :
+1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->MspInitCallback = pCallback;
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_MSP_DEINIT_CB_ID :
+1819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->MspDeInitCallback = pCallback;
+1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     default :
+1822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Update the error code */
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* update return status */
+1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       status =  HAL_ERROR;
+1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Update the error code */
+1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+1833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* update return status */
+1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status =  HAL_ERROR;
+1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Release Lock */
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_UNLOCK(hsd);
+1839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return status;
+1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Unregister a User SD Callback
+1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         SD Callback is redirected to the weak (surcharged) predefined callback
+1845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param hsd : SD handle
+1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param CallbackID : ID of the callback to be unregistered
+1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *        This parameter can be one of the following values:
+1848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID
+1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID
+1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID
+1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID
+1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID
+1853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval status
+1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ARM GAS  /tmp/ccQEYyKb.s 			page 34
+
+
+1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef Callbac
+1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_StatusTypeDef status = HAL_OK;
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Process locked */
+1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_LOCK(hsd);
+1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->State == HAL_SD_STATE_READY)
+1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     switch (CallbackID)
+1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_TX_CPLT_CB_ID :
+1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_RX_CPLT_CB_ID :
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_ERROR_CB_ID :
+1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCallback = HAL_SD_ErrorCallback;
+1875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_ABORT_CB_ID :
+1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+1878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_MSP_INIT_CB_ID :
+1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->MspInitCallback = HAL_SD_MspInit;
+1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_MSP_DEINIT_CB_ID :
+1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+1884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     default :
+1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Update the error code */
+1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* update return status */
+1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       status =  HAL_ERROR;
+1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else if (hsd->State == HAL_SD_STATE_RESET)
+1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+1895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     switch (CallbackID)
+1896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+1897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_MSP_INIT_CB_ID :
+1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->MspInitCallback = HAL_SD_MspInit;
+1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     case HAL_SD_MSP_DEINIT_CB_ID :
+1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     default :
+1904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Update the error code */
+1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* update return status */
+1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       status =  HAL_ERROR;
+1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+1910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ARM GAS  /tmp/ccQEYyKb.s 			page 35
+
+
+1913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Update the error code */
+1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* update return status */
+1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status =  HAL_ERROR;
+1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+1918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Release Lock */
+1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_UNLOCK(hsd);
+1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return status;
+1922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @}
+1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Exported_Functions_Group3
+1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****  *  @brief   management functions
+1931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****  *
+1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @verbatim
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ==============================================================================
+1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                       ##### Peripheral Control functions #####
+1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   ==============================================================================
+1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   [..]
+1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     This subsection provides a set of functions allowing to control the SD card
+1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     operations and get the related information
+1939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @endverbatim
+1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @{
+1942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Returns information the information of the card which are stored on
+1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         the CID register.
+1947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that  
+1949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         contains all CID register parameters
+1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
+1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
+1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
+1957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
+1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
+1961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
+1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
+1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
+1967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
+1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 36
+
+
+1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
+1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCID->Reserved2 = 1U;
+1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_OK;
+1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Returns information the information of the card which are stored on
+1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         the CSD register.
+1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that  
+1982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         contains all CSD register parameters
+1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
+1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
+1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
+1990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
+1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
+1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
+1996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
+1998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
+2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
+2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->PartBlockRead   = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
+2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
+2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
+2010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->Reserved2 = 0U; /*!< Reserved */
+2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->SdCard.CardType == CARD_SDSC)
+2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U))
+2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
+2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
+2020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
+2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
+2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
+2026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 37
+
+
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
+2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockNbr =  (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockSize = 512U;
+2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
+2035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Byte 7 */
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)
+2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
+2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockSize = 512U;
+2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
+2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+2045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Clear all the static flags */
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
+2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
+2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
+2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
+2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
+2068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->Reserved3 = 0;
+2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
+2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
+2074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
+2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
+2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
+2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+ARM GAS  /tmp/ccQEYyKb.s 			page 38
+
+
+2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
+2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->Reserved4 = 1;
+2088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_OK;
+2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Gets the SD status info.
+2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that 
+2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         will contain the SD card status information
+2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
+2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t sd_status[16];
+2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_StatusTypeDef status = HAL_OK;
+2104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SD_SendSDStatus(hsd, sd_status);
+2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Clear all the static flags */
+2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+2113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
+2117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
+2119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF0000
+2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) <<
+2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                                   ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U
+2124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
+2126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
+2128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
+2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU))
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
+2134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
+2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Set Block Size for Card */
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ARM GAS  /tmp/ccQEYyKb.s 			page 39
+
+
+2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Clear all the static flags */
+2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode = errorstate;
+2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return status;
+2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Gets the SD card info.
+2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         will contain the SD card status information
+2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
+2160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
+2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
+2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
+2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
+2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_OK;
+2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Enables wide bus operation for the requested card if supported by
+2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         card.
+2176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+2177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  WideMode: Specifies the SD card wide bus mode
+2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *          This parameter can be one of the following values:
+2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
+2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
+2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
+2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
+2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_InitTypeDef Init;
+2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_StatusTypeDef status = HAL_OK;
+2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check the parameters */
+2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_BUS_WIDE(WideMode));
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Change State */
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_BUSY;
+2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->SdCard.CardType != CARD_SECURED)
+2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ARM GAS  /tmp/ccQEYyKb.s 			page 40
+
+
+2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(WideMode == SDMMC_BUS_WIDE_8B)
+2199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else if(WideMode == SDMMC_BUS_WIDE_4B)
+2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SD_WideBus_Enable(hsd);
+2205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else if(WideMode == SDMMC_BUS_WIDE_1B)
+2209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       errorstate = SD_WideBus_Disable(hsd);
+2211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+2215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* WideMode is not a valid argument*/
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+2218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+2221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* MMC Card does not support this feature */
+2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+2224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Clear all the static flags */
+2229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+2232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Configure the SDMMC peripheral */
+2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockEdge           = hsd->Init.ClockEdge;
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockBypass         = hsd->Init.ClockBypass;
+2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
+2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.BusWide             = WideMode;
+2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockDiv            = hsd->Init.ClockDiv;
+2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_Init(hsd->Instance, Init);
+2243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Set Block Size for Card */
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+2248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Clear all the static flags */
+2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+2253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 41
+
+
+2255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Change State */
+2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+2257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return status;
+2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Gets the current sd card data state.
+2263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: pointer to SD handle
+2264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval Card state
+2265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
+2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t cardstate;
+2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t resp1 = 0;
+2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SD_SendStatus(hsd, &resp1);
+2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   cardstate = ((resp1 >> 9U) & 0x0FU);
+2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return (HAL_SD_CardStateTypeDef)cardstate;
+2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Abort the current transfer and disable the SD.
+2285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *                the configuration information for SD module.
+2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+2288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t context = hsd->Context;
+2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* DIsable All interrupts */
+2295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+2296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Clear All flags */
+2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN);
+2302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if ((context & SD_CONTEXT_DMA) != 0U)
+2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Disable the SD DMA request */
+2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+2307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Abort the SD DMA Tx channel */
+2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_
+2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK)
+ARM GAS  /tmp/ccQEYyKb.s 			page 42
+
+
+2312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+2315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Abort the SD DMA Rx channel */
+2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIP
+2318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK)
+2320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+2323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Nothing to do */
+2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+2331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Initialize the SD operation */
+2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Context = SD_CONTEXT_NONE;
+2334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   CardState = HAL_SD_GetCardState(hsd);
+2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+2337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+2341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_OK;
+2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Abort the current transfer and disable the SD (IT mode).
+2349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+2350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *                the configuration information for SD module.
+2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval HAL status
+2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t context = hsd->Context;
+2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Disable All interrupts */
+2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+2361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN);
+2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if ((context & SD_CONTEXT_DMA) != 0U)
+2365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Disable the SD DMA request */
+2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+2368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 43
+
+
+2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Abort the SD DMA Tx channel */
+2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_
+2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+2374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->hdmatx = NULL;
+2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+2377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Abort the SD DMA Rx channel */
+2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIP
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+2383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->hdmarx = NULL;
+2385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Nothing to do */
+2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* No transfer ongoing on both DMA channels*/
+2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+2394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Clear All flags */
+2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+2397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     CardState = HAL_SD_GetCardState(hsd);
+2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Context = SD_CONTEXT_NONE;
+2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+2406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+2408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+2410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->AbortCpltCallback(hsd);
+2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       HAL_SD_AbortCallback(hsd);
+2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+2416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_OK;
+2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @}
+2424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 44
+
+
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @}
+2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private function ----------------------------------------------------------*/
+2431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Private_Functions
+2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @{
+2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  DMA SD transmit process complete callback
+2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hdma: DMA handle
+2438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+  28              		.loc 1 2441 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  33              		.loc 1 2442 3 view .LVU1
+  34              		.loc 1 2442 21 is_stmt 0 view .LVU2
+  35 0000 836B     		ldr	r3, [r0, #56]
+  36              	.LVL1:
+2443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Enable DATAEND Interrupt */
+2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DATAEND));
+  37              		.loc 1 2445 3 is_stmt 1 view .LVU3
+  38 0002 1A68     		ldr	r2, [r3]
+  39 0004 D36B     		ldr	r3, [r2, #60]
+  40              	.LVL2:
+  41              		.loc 1 2445 3 is_stmt 0 view .LVU4
+  42 0006 43F48073 		orr	r3, r3, #256
+  43 000a D363     		str	r3, [r2, #60]
+  44              	.LVL3:
+2446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+  45              		.loc 1 2446 1 view .LVU5
+  46 000c 7047     		bx	lr
+  47              		.cfi_endproc
+  48              	.LFE168:
+  50              		.section	.text.SD_PowerON,"ax",%progbits
+  51              		.align	1
+  52              		.syntax unified
+  53              		.thumb
+  54              		.thumb_func
+  55              		.fpu fpv5-d16
+  57              	SD_PowerON:
+  58              	.LVL4:
+  59              	.LFB174:
+2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  DMA SD receive process complete callback
+2450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hdma: DMA handle
+2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+ARM GAS  /tmp/ccQEYyKb.s 			page 45
+
+
+2453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+2456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+2457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Send stop command in multiblock write */
+2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
+2460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+2463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+2466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCallback(hsd);
+2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       HAL_SD_ErrorCallback(hsd);
+2469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   in the SD DCTRL register */
+2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);
+2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Clear all the static flags */
+2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+2479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Context = SD_CONTEXT_NONE;
+2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+2484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->RxCpltCallback(hsd);
+2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_RxCpltCallback(hsd);
+2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+2488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  DMA SD communication error callback
+2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hdma: DMA handle
+2493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMAError(DMA_HandleTypeDef *hdma)
+2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t RxErrorCode, TxErrorCode;
+2500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* if DMA error is FIFO error ignore it */
+2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+2503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     RxErrorCode = hsd->hdmarx->ErrorCode;
+2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     TxErrorCode = hsd->hdmatx->ErrorCode;  
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
+2507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Clear All flags */
+2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ARM GAS  /tmp/ccQEYyKb.s 			page 46
+
+
+2510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Disable All interrupts */
+2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
+2513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+2514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       CardState = HAL_SD_GetCardState(hsd);
+2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+2518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+2520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State= HAL_SD_STATE_READY;
+2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCallback(hsd);
+2528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     HAL_SD_ErrorCallback(hsd);
+2530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  DMA SD Tx Abort callback
+2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hdma: DMA handle
+2537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+2538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Clear All flags */
+2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+2546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   CardState = HAL_SD_GetCardState(hsd);
+2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Context = SD_CONTEXT_NONE;
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+2553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
+2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+2558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->AbortCpltCallback(hsd);
+2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     HAL_SD_AbortCallback(hsd);
+2561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+2562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+2566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCallback(hsd);
+ARM GAS  /tmp/ccQEYyKb.s 			page 47
+
+
+2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     HAL_SD_ErrorCallback(hsd);
+2569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  DMA SD Rx Abort callback
+2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hdma: DMA handle
+2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+2577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
+2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+2581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Clear All flags */
+2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+2585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   CardState = HAL_SD_GetCardState(hsd);
+2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Context = SD_CONTEXT_NONE;
+2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+2592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
+2595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+2597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->AbortCpltCallback(hsd);
+2598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     HAL_SD_AbortCallback(hsd);
+2600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+2601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+2603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+2605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCallback(hsd);
+2606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else
+2607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     HAL_SD_ErrorCallback(hsd);
+2608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+2609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Initializes the sd card.
+2614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+2615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval SD Card error state
+2616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
+2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardCSDTypeDef CSD;
+2620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+2621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint16_t sd_rca = 1U;
+2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check the power State */
+ARM GAS  /tmp/ccQEYyKb.s 			page 48
+
+
+2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(SDMMC_GetPowerState(hsd->Instance) == 0U)
+2625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Power off */
+2627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+2628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->SdCard.CardType != CARD_SECURED)
+2631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Send CMD2 ALL_SEND_CID */
+2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdSendCID(hsd->Instance);
+2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+2635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return errorstate;
+2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+2639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Get Card identification number data */
+2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+2645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->SdCard.CardType != CARD_SECURED)
+2649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Send CMD3 SET_REL_ADDR with argument 0 */
+2651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* SD Card publishes its RCA. */
+2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+2654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return errorstate;
+2656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(hsd->SdCard.CardType != CARD_SECURED)
+2659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Get the SD card RCA */
+2661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.RelCardAdd = sd_rca;
+2662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Send CMD9 SEND_CSD with argument as card's RCA */
+2664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return errorstate;
+2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else
+2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       /* Get Card Specific Data */
+2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+2676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Get the Card Class */
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U);
+ARM GAS  /tmp/ccQEYyKb.s 			page 49
+
+
+2681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Get CSD parameters */
+2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
+2684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Select the Card */
+2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16
+2690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+2691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Configure SDMMC peripheral interface */
+2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   (void)SDMMC_Init(hsd->Instance, hsd->Init);
+2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* All cards are initialized */
+2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_SD_ERROR_NONE;
+2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Enquires cards about their operating voltage and configures clock
+2704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         controls and stores SD information that will be needed in future
+2705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         in the SD handle.
+2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+2707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval error state
+2708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
+2710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+  60              		.loc 1 2710 1 is_stmt 1 view -0
+  61              		.cfi_startproc
+  62              		@ args = 0, pretend = 0, frame = 8
+  63              		@ frame_needed = 0, uses_anonymous_args = 0
+  64              		.loc 1 2710 1 is_stmt 0 view .LVU7
+  65 0000 70B5     		push	{r4, r5, r6, lr}
+  66              	.LCFI0:
+  67              		.cfi_def_cfa_offset 16
+  68              		.cfi_offset 4, -16
+  69              		.cfi_offset 5, -12
+  70              		.cfi_offset 6, -8
+  71              		.cfi_offset 14, -4
+  72 0002 82B0     		sub	sp, sp, #8
+  73              	.LCFI1:
+  74              		.cfi_def_cfa_offset 24
+  75 0004 0446     		mov	r4, r0
+2711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __IO uint32_t count = 0U;
+  76              		.loc 1 2711 3 is_stmt 1 view .LVU8
+  77              		.loc 1 2711 17 is_stmt 0 view .LVU9
+  78 0006 0023     		movs	r3, #0
+  79 0008 0193     		str	r3, [sp, #4]
+2712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t response = 0U, validvoltage = 0U;
+  80              		.loc 1 2712 3 is_stmt 1 view .LVU10
+  81              	.LVL5:
+2713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+  82              		.loc 1 2713 3 view .LVU11
+2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 50
+
+
+2715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* CMD0: GO_IDLE_STATE */
+2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+  83              		.loc 1 2716 3 view .LVU12
+  84              		.loc 1 2716 16 is_stmt 0 view .LVU13
+  85 000a 0068     		ldr	r0, [r0]
+  86              	.LVL6:
+  87              		.loc 1 2716 16 view .LVU14
+  88 000c FFF7FEFF 		bl	SDMMC_CmdGoIdleState
+  89              	.LVL7:
+2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+  90              		.loc 1 2717 3 is_stmt 1 view .LVU15
+  91              		.loc 1 2717 5 is_stmt 0 view .LVU16
+  92 0010 0546     		mov	r5, r0
+  93 0012 10B1     		cbz	r0, .L19
+  94              	.LVL8:
+  95              	.L2:
+2718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+2720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
+2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdOperCond(hsd->Instance);
+2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+2725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.CardVersion = CARD_V1_X;
+2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* CMD0: GO_IDLE_STATE */
+2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+2729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+2730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return errorstate;
+2732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.CardVersion = CARD_V2_X;
+2738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if( hsd->SdCard.CardVersion == CARD_V2_X)
+2741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* SEND CMD55 APP_CMD with RCA as 0 */
+2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+2745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* SD CARD */
+2750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* SEND CMD55 APP_CMD with RCA as 0 */
+2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+2755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return errorstate;
+2758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ARM GAS  /tmp/ccQEYyKb.s 			page 51
+
+
+2759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Send CMD41 */
+2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACI
+2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+2763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+2765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Get command response */
+2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+2769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Get operating voltage*/
+2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+2772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     count++;
+2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(count >= SDMMC_MAX_VOLT_TRIAL)
+2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_INVALID_VOLTRANGE;
+2779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+2782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.CardType = CARD_SDHC_SDXC;
+2784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+2786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.CardType = CARD_SDSC;
+2788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_SD_ERROR_NONE;
+2792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+  96              		.loc 1 2792 1 view .LVU17
+  97 0014 2846     		mov	r0, r5
+  98 0016 02B0     		add	sp, sp, #8
+  99              	.LCFI2:
+ 100              		.cfi_remember_state
+ 101              		.cfi_def_cfa_offset 16
+ 102              		@ sp needed
+ 103 0018 70BD     		pop	{r4, r5, r6, pc}
+ 104              	.LVL9:
+ 105              	.L19:
+ 106              	.LCFI3:
+ 107              		.cfi_restore_state
+2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 108              		.loc 1 2723 3 is_stmt 1 view .LVU18
+2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 109              		.loc 1 2723 16 is_stmt 0 view .LVU19
+ 110 001a 2068     		ldr	r0, [r4]
+ 111              	.LVL10:
+2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 112              		.loc 1 2723 16 view .LVU20
+ 113 001c FFF7FEFF 		bl	SDMMC_CmdOperCond
+ 114              	.LVL11:
+2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ARM GAS  /tmp/ccQEYyKb.s 			page 52
+
+
+ 115              		.loc 1 2724 3 is_stmt 1 view .LVU21
+2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 116              		.loc 1 2724 5 is_stmt 0 view .LVU22
+ 117 0020 38B9     		cbnz	r0, .L20
+2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 118              		.loc 1 2737 5 is_stmt 1 view .LVU23
+2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 119              		.loc 1 2737 29 is_stmt 0 view .LVU24
+ 120 0022 0123     		movs	r3, #1
+ 121 0024 A364     		str	r3, [r4, #72]
+ 122              	.L5:
+2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 123              		.loc 1 2740 3 is_stmt 1 view .LVU25
+2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 124              		.loc 1 2740 18 is_stmt 0 view .LVU26
+ 125 0026 A36C     		ldr	r3, [r4, #72]
+2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 126              		.loc 1 2740 5 view .LVU27
+ 127 0028 012B     		cmp	r3, #1
+ 128 002a 0BD0     		beq	.L6
+ 129              	.L8:
+2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 130              		.loc 1 2771 52 view .LVU28
+ 131 002c 2E46     		mov	r6, r5
+ 132 002e 2846     		mov	r0, r5
+ 133              	.LVL12:
+2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 134              		.loc 1 2771 52 view .LVU29
+ 135 0030 14E0     		b	.L7
+ 136              	.LVL13:
+ 137              	.L20:
+2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* CMD0: GO_IDLE_STATE */
+ 138              		.loc 1 2726 5 is_stmt 1 view .LVU30
+2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* CMD0: GO_IDLE_STATE */
+ 139              		.loc 1 2726 29 is_stmt 0 view .LVU31
+ 140 0032 0023     		movs	r3, #0
+ 141 0034 A364     		str	r3, [r4, #72]
+2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 142              		.loc 1 2728 5 is_stmt 1 view .LVU32
+2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 143              		.loc 1 2728 18 is_stmt 0 view .LVU33
+ 144 0036 2068     		ldr	r0, [r4]
+ 145              	.LVL14:
+2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 146              		.loc 1 2728 18 view .LVU34
+ 147 0038 FFF7FEFF 		bl	SDMMC_CmdGoIdleState
+ 148              	.LVL15:
+2729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 149              		.loc 1 2729 5 is_stmt 1 view .LVU35
+2729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 150              		.loc 1 2729 7 is_stmt 0 view .LVU36
+ 151 003c 0028     		cmp	r0, #0
+ 152 003e F2D0     		beq	.L5
+2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 153              		.loc 1 2731 14 view .LVU37
+ 154 0040 0546     		mov	r5, r0
+ 155 0042 E7E7     		b	.L2
+ARM GAS  /tmp/ccQEYyKb.s 			page 53
+
+
+ 156              	.L6:
+2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 157              		.loc 1 2743 5 is_stmt 1 view .LVU38
+2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 158              		.loc 1 2743 18 is_stmt 0 view .LVU39
+ 159 0044 0021     		movs	r1, #0
+ 160 0046 2068     		ldr	r0, [r4]
+ 161              	.LVL16:
+2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 162              		.loc 1 2743 18 view .LVU40
+ 163 0048 FFF7FEFF 		bl	SDMMC_CmdAppCommand
+ 164              	.LVL17:
+2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 165              		.loc 1 2744 5 is_stmt 1 view .LVU41
+2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 166              		.loc 1 2744 7 is_stmt 0 view .LVU42
+ 167 004c 0028     		cmp	r0, #0
+ 168 004e EDD0     		beq	.L8
+2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 169              		.loc 1 2746 14 view .LVU43
+ 170 0050 4FF08055 		mov	r5, #268435456
+ 171 0054 DEE7     		b	.L2
+ 172              	.LVL18:
+ 173              	.L9:
+2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 174              		.loc 1 2773 5 is_stmt 1 discriminator 4 view .LVU44
+2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 175              		.loc 1 2773 10 is_stmt 0 discriminator 4 view .LVU45
+ 176 0056 019B     		ldr	r3, [sp, #4]
+ 177 0058 0133     		adds	r3, r3, #1
+ 178 005a 0193     		str	r3, [sp, #4]
+ 179              	.LVL19:
+ 180              	.L7:
+2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 181              		.loc 1 2751 8 is_stmt 1 view .LVU46
+2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 182              		.loc 1 2751 16 is_stmt 0 view .LVU47
+ 183 005c 019A     		ldr	r2, [sp, #4]
+2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 184              		.loc 1 2751 8 view .LVU48
+ 185 005e 4FF6FE73 		movw	r3, #65534
+ 186 0062 9A42     		cmp	r2, r3
+ 187 0064 13D8     		bhi	.L10
+2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 188              		.loc 1 2751 40 discriminator 1 view .LVU49
+ 189 0066 96B9     		cbnz	r6, .L10
+2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 190              		.loc 1 2754 5 is_stmt 1 view .LVU50
+2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 191              		.loc 1 2754 18 is_stmt 0 view .LVU51
+ 192 0068 0021     		movs	r1, #0
+ 193 006a 2068     		ldr	r0, [r4]
+ 194              	.LVL20:
+2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 195              		.loc 1 2754 18 view .LVU52
+ 196 006c FFF7FEFF 		bl	SDMMC_CmdAppCommand
+ 197              	.LVL21:
+ARM GAS  /tmp/ccQEYyKb.s 			page 54
+
+
+2755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 198              		.loc 1 2755 5 is_stmt 1 view .LVU53
+2755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 199              		.loc 1 2755 7 is_stmt 0 view .LVU54
+ 200 0070 E0B9     		cbnz	r0, .L15
+2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 201              		.loc 1 2761 5 is_stmt 1 view .LVU55
+2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 202              		.loc 1 2761 18 is_stmt 0 view .LVU56
+ 203 0072 1249     		ldr	r1, .L21
+ 204 0074 2068     		ldr	r0, [r4]
+ 205              	.LVL22:
+2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 206              		.loc 1 2761 18 view .LVU57
+ 207 0076 FFF7FEFF 		bl	SDMMC_CmdAppOperCommand
+ 208              	.LVL23:
+2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 209              		.loc 1 2762 5 is_stmt 1 view .LVU58
+2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 210              		.loc 1 2762 7 is_stmt 0 view .LVU59
+ 211 007a 0646     		mov	r6, r0
+ 212              	.LVL24:
+2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 213              		.loc 1 2762 7 view .LVU60
+ 214 007c C0B9     		cbnz	r0, .L16
+2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 215              		.loc 1 2768 5 is_stmt 1 view .LVU61
+2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 216              		.loc 1 2768 16 is_stmt 0 view .LVU62
+ 217 007e 0021     		movs	r1, #0
+ 218 0080 2068     		ldr	r0, [r4]
+ 219              	.LVL25:
+2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 220              		.loc 1 2768 16 view .LVU63
+ 221 0082 FFF7FEFF 		bl	SDMMC_GetResponse
+ 222              	.LVL26:
+2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 223              		.loc 1 2771 5 is_stmt 1 view .LVU64
+2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 224              		.loc 1 2771 52 is_stmt 0 view .LVU65
+ 225 0086 C30F     		lsrs	r3, r0, #31
+ 226 0088 E5D0     		beq	.L9
+ 227 008a 1E46     		mov	r6, r3
+ 228              	.LVL27:
+2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 229              		.loc 1 2771 52 view .LVU66
+ 230 008c E3E7     		b	.L9
+ 231              	.LVL28:
+ 232              	.L10:
+2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 233              		.loc 1 2776 3 is_stmt 1 view .LVU67
+2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 234              		.loc 1 2776 12 is_stmt 0 view .LVU68
+ 235 008e 019A     		ldr	r2, [sp, #4]
+2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 236              		.loc 1 2776 5 view .LVU69
+ 237 0090 4FF6FE73 		movw	r3, #65534
+ARM GAS  /tmp/ccQEYyKb.s 			page 55
+
+
+ 238 0094 9A42     		cmp	r2, r3
+ 239 0096 0ED8     		bhi	.L17
+2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 240              		.loc 1 2781 3 is_stmt 1 view .LVU70
+2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 241              		.loc 1 2781 5 is_stmt 0 view .LVU71
+ 242 0098 10F08043 		ands	r3, r0, #1073741824
+ 243 009c 02D0     		beq	.L12
+2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 244              		.loc 1 2783 5 is_stmt 1 view .LVU72
+2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 245              		.loc 1 2783 26 is_stmt 0 view .LVU73
+ 246 009e 0123     		movs	r3, #1
+ 247 00a0 6364     		str	r3, [r4, #68]
+ 248 00a2 B7E7     		b	.L2
+ 249              	.L12:
+2787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 250              		.loc 1 2787 5 is_stmt 1 view .LVU74
+2787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 251              		.loc 1 2787 26 is_stmt 0 view .LVU75
+ 252 00a4 0022     		movs	r2, #0
+ 253 00a6 6264     		str	r2, [r4, #68]
+2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 254              		.loc 1 2791 10 view .LVU76
+ 255 00a8 1D46     		mov	r5, r3
+ 256 00aa B3E7     		b	.L2
+ 257              	.LVL29:
+ 258              	.L15:
+2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 259              		.loc 1 2757 14 view .LVU77
+ 260 00ac 0546     		mov	r5, r0
+ 261 00ae B1E7     		b	.L2
+ 262              	.LVL30:
+ 263              	.L16:
+2764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 264              		.loc 1 2764 14 view .LVU78
+ 265 00b0 4FF08055 		mov	r5, #268435456
+ 266 00b4 AEE7     		b	.L2
+ 267              	.LVL31:
+ 268              	.L17:
+2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 269              		.loc 1 2778 12 view .LVU79
+ 270 00b6 4FF08075 		mov	r5, #16777216
+ 271 00ba ABE7     		b	.L2
+ 272              	.L22:
+ 273              		.align	2
+ 274              	.L21:
+ 275 00bc 000010C1 		.word	-1055916032
+ 276              		.cfi_endproc
+ 277              	.LFE174:
+ 279              		.section	.text.SD_PowerOFF,"ax",%progbits
+ 280              		.align	1
+ 281              		.syntax unified
+ 282              		.thumb
+ 283              		.thumb_func
+ 284              		.fpu fpv5-d16
+ 286              	SD_PowerOFF:
+ARM GAS  /tmp/ccQEYyKb.s 			page 56
+
+
+ 287              	.LVL32:
+ 288              	.LFB175:
+2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Turns the SDMMC output signals off.
+2796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+2798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_PowerOFF(SD_HandleTypeDef *hsd)
+2800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+ 289              		.loc 1 2800 1 is_stmt 1 view -0
+ 290              		.cfi_startproc
+ 291              		@ args = 0, pretend = 0, frame = 0
+ 292              		@ frame_needed = 0, uses_anonymous_args = 0
+ 293              		.loc 1 2800 1 is_stmt 0 view .LVU81
+ 294 0000 08B5     		push	{r3, lr}
+ 295              	.LCFI4:
+ 296              		.cfi_def_cfa_offset 8
+ 297              		.cfi_offset 3, -8
+ 298              		.cfi_offset 14, -4
+2801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Set Power State to OFF */
+2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   (void)SDMMC_PowerState_OFF(hsd->Instance);
+ 299              		.loc 1 2802 3 is_stmt 1 view .LVU82
+ 300              		.loc 1 2802 9 is_stmt 0 view .LVU83
+ 301 0002 0068     		ldr	r0, [r0]
+ 302              	.LVL33:
+ 303              		.loc 1 2802 9 view .LVU84
+ 304 0004 FFF7FEFF 		bl	SDMMC_PowerState_OFF
+ 305              	.LVL34:
+2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 306              		.loc 1 2803 1 view .LVU85
+ 307 0008 08BD     		pop	{r3, pc}
+ 308              		.cfi_endproc
+ 309              	.LFE175:
+ 311              		.section	.text.SD_Read_IT,"ax",%progbits
+ 312              		.align	1
+ 313              		.syntax unified
+ 314              		.thumb
+ 315              		.thumb_func
+ 316              		.fpu fpv5-d16
+ 318              	SD_Read_IT:
+ 319              	.LVL35:
+ 320              	.LFB181:
+2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Send Status info command.
+2807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: pointer to SD handle
+2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
+2809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         SD Status register)
+2810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval error state
+2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+2815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t tickstart = HAL_GetTick();
+2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count;
+ARM GAS  /tmp/ccQEYyKb.s 			page 57
+
+
+2818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t *pData = pSDstatus;
+2819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check SD response */
+2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+2824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Set block size for card if it is not equal to current block size for card */
+2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+2829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+2831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Send CMD55 */
+2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+2836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+2837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+2840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Configure the SD DPSM (Data Path State Machine) */
+2843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataTimeOut   = SDMMC_DATATIMEOUT;
+2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataLength    = 64U;
+2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
+2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DPSM          = SDMMC_DPSM_ENABLE;
+2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   (void)SDMMC_ConfigData(hsd->Instance, &config);
+2850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
+2852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
+2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+2854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+2857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Get status data */
+2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SD
+2861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+2863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       for(count = 0U; count < 8U; count++)
+2865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         *pData = SDMMC_ReadFIFO(hsd->Instance);
+2867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         pData++;
+2868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+2869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+2872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_SD_ERROR_TIMEOUT;
+2874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ARM GAS  /tmp/ccQEYyKb.s 			page 58
+
+
+2875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+2878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_DATA_TIMEOUT;
+2880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+2882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_DATA_CRC_FAIL;
+2884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+2886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_RX_OVERRUN;
+2888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Nothing to do */
+2892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)))
+2895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     *pData = SDMMC_ReadFIFO(hsd->Instance);
+2897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pData++;
+2898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+2900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_SD_ERROR_TIMEOUT;
+2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Clear all the static status flags*/
+2906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_SD_ERROR_NONE;
+2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Returns the current card's status.
+2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pCardStatus: pointer to the buffer that will contain the SD card
+2915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *         status (Card Status register)
+2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval error state
+2917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+2921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(pCardStatus == NULL)
+2923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_PARAM;
+2925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Send Status command */
+2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+2930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+ARM GAS  /tmp/ccQEYyKb.s 			page 59
+
+
+2932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Get SD card status */
+2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+2936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_SD_ERROR_NONE;
+2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Enables the SDMMC wide bus mode.
+2942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: pointer to SD handle
+2943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval error state
+2944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+2946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t scr[2U] = {0U, 0U};
+2948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+2951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+2953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Get SCR Register */
+2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SD_FindSCR(hsd, scr);
+2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+2958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+2960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* If requested card supports wide bus operation */
+2963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+2964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Send CMD55 APP_CMD with argument as card's RCA.*/
+2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+2968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return errorstate;
+2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
+2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+2975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+2976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return errorstate;
+2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+2978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_NONE;
+2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+2986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Disables the SDMMC wide bus mode.
+ARM GAS  /tmp/ccQEYyKb.s 			page 60
+
+
+2989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+2990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval error state
+2991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+2992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+2993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t scr[2U] = {0U, 0U};
+2995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+2996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+2999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+3000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Get SCR Register */
+3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SD_FindSCR(hsd, scr);
+3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+3005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* If requested card supports 1 bit mode operation */
+3010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+3011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Send CMD55 APP_CMD with argument as card's RCA */
+3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+3014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+3015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+3016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return errorstate;
+3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+3018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
+3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
+3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+3022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return errorstate;
+3024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+3025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_NONE;
+3027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+3031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+3033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+3036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Finds the SD card SCR register value.
+3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: Pointer to SD handle
+3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  pSCR: pointer to the buffer that will contain the SCR value
+3039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval error state
+3040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+3042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+3043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t tickstart = HAL_GetTick();
+ARM GAS  /tmp/ccQEYyKb.s 			page 61
+
+
+3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t index = 0U;
+3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t tempscr[2U] = {0U, 0U};
+3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t *scr = pSCR;
+3049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Set Block Size To 8 Bytes */
+3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
+3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+3053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Send CMD55 APP_CMD with argument as card's RCA */
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
+3059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+3060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+3062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataTimeOut   = SDMMC_DATATIMEOUT;
+3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataLength    = 8U;
+3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
+3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DPSM          = SDMMC_DPSM_ENABLE;
+3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   (void)SDMMC_ConfigData(hsd->Instance, &config);
+3071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+3073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   errorstate = SDMMC_CmdSendSCR(hsd->Instance);
+3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+3077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT))
+3080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))
+3082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);
+3084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       index++;
+3085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     else if(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXACT))
+3087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+3088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       break;
+3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+3092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_SD_ERROR_TIMEOUT;
+3094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+3100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_DATA_TIMEOUT;
+3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ARM GAS  /tmp/ccQEYyKb.s 			page 62
+
+
+3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+3104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+3106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_DATA_CRC_FAIL;
+3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+3110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_SD_ERROR_RX_OVERRUN;
+3114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   else
+3116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* No error flag set */
+3118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Clear all the static flags */
+3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
+3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+3123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     scr++;
+3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
+3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return HAL_SD_ERROR_NONE;
+3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+3133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Wrap up reading in non-blocking mode.
+3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+3135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *              the configuration information.
+3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+3137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+3138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_Read_IT(SD_HandleTypeDef *hsd)
+3139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+ 321              		.loc 1 3139 1 is_stmt 1 view -0
+ 322              		.cfi_startproc
+ 323              		@ args = 0, pretend = 0, frame = 0
+ 324              		@ frame_needed = 0, uses_anonymous_args = 0
+ 325              		.loc 1 3139 1 is_stmt 0 view .LVU87
+ 326 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 327              	.LCFI5:
+ 328              		.cfi_def_cfa_offset 24
+ 329              		.cfi_offset 3, -24
+ 330              		.cfi_offset 4, -20
+ 331              		.cfi_offset 5, -16
+ 332              		.cfi_offset 6, -12
+ 333              		.cfi_offset 7, -8
+ 334              		.cfi_offset 14, -4
+3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count, data, dataremaining;
+ 335              		.loc 1 3140 3 is_stmt 1 view .LVU88
+3141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint8_t* tmp;
+ 336              		.loc 1 3141 3 view .LVU89
+3142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   tmp = hsd->pRxBuffPtr;
+ARM GAS  /tmp/ccQEYyKb.s 			page 63
+
+
+ 337              		.loc 1 3143 3 view .LVU90
+ 338              		.loc 1 3143 7 is_stmt 0 view .LVU91
+ 339 0002 846A     		ldr	r4, [r0, #40]
+ 340              	.LVL36:
+3144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   dataremaining = hsd->RxXferSize;
+ 341              		.loc 1 3144 3 is_stmt 1 view .LVU92
+ 342              		.loc 1 3144 17 is_stmt 0 view .LVU93
+ 343 0004 C66A     		ldr	r6, [r0, #44]
+ 344              	.LVL37:
+3145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if (dataremaining > 0U)
+ 345              		.loc 1 3146 3 is_stmt 1 view .LVU94
+ 346              		.loc 1 3146 6 is_stmt 0 view .LVU95
+ 347 0006 A6B9     		cbnz	r6, .L29
+ 348              	.LVL38:
+ 349              	.L25:
+3147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Read data from SDMMC Rx FIFO */
+3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     for(count = 0U; count < 8U; count++)
+3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       data = SDMMC_ReadFIFO(hsd->Instance);
+3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tmp = (uint8_t)(data & 0xFFU);
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+3154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+3160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+3162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+3165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->pRxBuffPtr = tmp;
+3167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->RxXferSize = dataremaining;
+3168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 350              		.loc 1 3169 1 view .LVU96
+ 351 0008 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 352              	.LVL39:
+ 353              	.L28:
+3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tmp = (uint8_t)(data & 0xFFU);
+ 354              		.loc 1 3151 7 is_stmt 1 discriminator 3 view .LVU97
+3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tmp = (uint8_t)(data & 0xFFU);
+ 355              		.loc 1 3151 14 is_stmt 0 discriminator 3 view .LVU98
+ 356 000a 3868     		ldr	r0, [r7]
+ 357 000c FFF7FEFF 		bl	SDMMC_ReadFIFO
+ 358              	.LVL40:
+3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 359              		.loc 1 3152 7 is_stmt 1 discriminator 3 view .LVU99
+3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 360              		.loc 1 3152 12 is_stmt 0 discriminator 3 view .LVU100
+ 361 0010 2070     		strb	r0, [r4]
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 362              		.loc 1 3153 7 is_stmt 1 discriminator 3 view .LVU101
+ARM GAS  /tmp/ccQEYyKb.s 			page 64
+
+
+ 363              	.LVL41:
+3154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+ 364              		.loc 1 3154 7 discriminator 3 view .LVU102
+3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 365              		.loc 1 3155 7 discriminator 3 view .LVU103
+3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 366              		.loc 1 3155 14 is_stmt 0 discriminator 3 view .LVU104
+ 367 0012 C0F30723 		ubfx	r3, r0, #8, #8
+3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 368              		.loc 1 3155 12 discriminator 3 view .LVU105
+ 369 0016 6370     		strb	r3, [r4, #1]
+3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 370              		.loc 1 3156 7 is_stmt 1 discriminator 3 view .LVU106
+ 371              	.LVL42:
+3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+ 372              		.loc 1 3157 7 discriminator 3 view .LVU107
+3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 373              		.loc 1 3158 7 discriminator 3 view .LVU108
+3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 374              		.loc 1 3158 14 is_stmt 0 discriminator 3 view .LVU109
+ 375 0018 C0F30743 		ubfx	r3, r0, #16, #8
+3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 376              		.loc 1 3158 12 discriminator 3 view .LVU110
+ 377 001c A370     		strb	r3, [r4, #2]
+3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 378              		.loc 1 3159 7 is_stmt 1 discriminator 3 view .LVU111
+ 379              	.LVL43:
+3160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+ 380              		.loc 1 3160 7 discriminator 3 view .LVU112
+3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 381              		.loc 1 3161 7 discriminator 3 view .LVU113
+3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 382              		.loc 1 3161 14 is_stmt 0 discriminator 3 view .LVU114
+ 383 001e 000E     		lsrs	r0, r0, #24
+ 384              	.LVL44:
+3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 385              		.loc 1 3161 12 discriminator 3 view .LVU115
+ 386 0020 E070     		strb	r0, [r4, #3]
+3162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 387              		.loc 1 3162 7 is_stmt 1 discriminator 3 view .LVU116
+3162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 388              		.loc 1 3162 10 is_stmt 0 discriminator 3 view .LVU117
+ 389 0022 0434     		adds	r4, r4, #4
+ 390              	.LVL45:
+3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 391              		.loc 1 3163 7 is_stmt 1 discriminator 3 view .LVU118
+3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 392              		.loc 1 3163 20 is_stmt 0 discriminator 3 view .LVU119
+ 393 0024 043E     		subs	r6, r6, #4
+ 394              	.LVL46:
+3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 395              		.loc 1 3149 33 is_stmt 1 discriminator 3 view .LVU120
+3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 396              		.loc 1 3149 38 is_stmt 0 discriminator 3 view .LVU121
+ 397 0026 0135     		adds	r5, r5, #1
+ 398              	.LVL47:
+ 399              	.L26:
+ARM GAS  /tmp/ccQEYyKb.s 			page 65
+
+
+3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 400              		.loc 1 3149 21 is_stmt 1 discriminator 1 view .LVU122
+3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 401              		.loc 1 3149 5 is_stmt 0 discriminator 1 view .LVU123
+ 402 0028 072D     		cmp	r5, #7
+ 403 002a EED9     		bls	.L28
+3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->RxXferSize = dataremaining;
+ 404              		.loc 1 3166 5 is_stmt 1 view .LVU124
+3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->RxXferSize = dataremaining;
+ 405              		.loc 1 3166 21 is_stmt 0 view .LVU125
+ 406 002c BC62     		str	r4, [r7, #40]
+3167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 407              		.loc 1 3167 5 is_stmt 1 view .LVU126
+3167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 408              		.loc 1 3167 21 is_stmt 0 view .LVU127
+ 409 002e FE62     		str	r6, [r7, #44]
+ 410              		.loc 1 3169 1 view .LVU128
+ 411 0030 EAE7     		b	.L25
+ 412              	.LVL48:
+ 413              	.L29:
+ 414              		.loc 1 3169 1 view .LVU129
+ 415 0032 0746     		mov	r7, r0
+3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 416              		.loc 1 3149 15 view .LVU130
+ 417 0034 0025     		movs	r5, #0
+ 418 0036 F7E7     		b	.L26
+ 419              		.cfi_endproc
+ 420              	.LFE181:
+ 422              		.section	.text.SD_Write_IT,"ax",%progbits
+ 423              		.align	1
+ 424              		.syntax unified
+ 425              		.thumb
+ 426              		.thumb_func
+ 427              		.fpu fpv5-d16
+ 429              	SD_Write_IT:
+ 430              	.LVL49:
+ 431              	.LFB182:
+3170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /**
+3172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @brief  Wrap up writing in non-blocking mode.
+3173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+3174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   *              the configuration information.
+3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   * @retval None
+3176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   */
+3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_Write_IT(SD_HandleTypeDef *hsd)
+3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** {
+ 432              		.loc 1 3178 1 is_stmt 1 view -0
+ 433              		.cfi_startproc
+ 434              		@ args = 0, pretend = 0, frame = 8
+ 435              		@ frame_needed = 0, uses_anonymous_args = 0
+ 436              		.loc 1 3178 1 is_stmt 0 view .LVU132
+ 437 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 438              	.LCFI6:
+ 439              		.cfi_def_cfa_offset 20
+ 440              		.cfi_offset 4, -20
+ 441              		.cfi_offset 5, -16
+ 442              		.cfi_offset 6, -12
+ARM GAS  /tmp/ccQEYyKb.s 			page 66
+
+
+ 443              		.cfi_offset 7, -8
+ 444              		.cfi_offset 14, -4
+ 445 0002 83B0     		sub	sp, sp, #12
+ 446              	.LCFI7:
+ 447              		.cfi_def_cfa_offset 32
+3179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count, data, dataremaining;
+ 448              		.loc 1 3179 3 is_stmt 1 view .LVU133
+3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint8_t* tmp;
+ 449              		.loc 1 3180 3 view .LVU134
+3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   tmp = hsd->pTxBuffPtr;
+ 450              		.loc 1 3182 3 view .LVU135
+ 451              		.loc 1 3182 7 is_stmt 0 view .LVU136
+ 452 0004 046A     		ldr	r4, [r0, #32]
+ 453              	.LVL50:
+3183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   dataremaining = hsd->TxXferSize;
+ 454              		.loc 1 3183 3 is_stmt 1 view .LVU137
+ 455              		.loc 1 3183 17 is_stmt 0 view .LVU138
+ 456 0006 466A     		ldr	r6, [r0, #36]
+ 457              	.LVL51:
+3184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if (dataremaining > 0U)
+ 458              		.loc 1 3185 3 is_stmt 1 view .LVU139
+ 459              		.loc 1 3185 6 is_stmt 0 view .LVU140
+ 460 0008 DEB9     		cbnz	r6, .L35
+ 461              	.LVL52:
+ 462              	.L31:
+3186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     /* Write data to SDMMC Tx FIFO */
+3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     for(count = 0U; count < 8U; count++)
+3189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       data = (uint32_t)(*tmp);
+3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+3192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       data |= ((uint32_t)(*tmp) << 8U);
+3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+3195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       data |= ((uint32_t)(*tmp) << 16U);
+3197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+3198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       data |= ((uint32_t)(*tmp) << 24U);
+3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+3203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->pTxBuffPtr = tmp;
+3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->TxXferSize = dataremaining;
+3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+3208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 463              		.loc 1 3208 1 view .LVU141
+ 464 000a 03B0     		add	sp, sp, #12
+ 465              	.LCFI8:
+ 466              		.cfi_remember_state
+ 467              		.cfi_def_cfa_offset 20
+ 468              		@ sp needed
+ 469 000c F0BD     		pop	{r4, r5, r6, r7, pc}
+ARM GAS  /tmp/ccQEYyKb.s 			page 67
+
+
+ 470              	.LVL53:
+ 471              	.L34:
+ 472              	.LCFI9:
+ 473              		.cfi_restore_state
+3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 474              		.loc 1 3190 7 is_stmt 1 discriminator 3 view .LVU142
+3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 475              		.loc 1 3190 25 is_stmt 0 discriminator 3 view .LVU143
+ 476 000e 2378     		ldrb	r3, [r4]	@ zero_extendqisi2
+3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 477              		.loc 1 3190 12 discriminator 3 view .LVU144
+ 478 0010 0193     		str	r3, [sp, #4]
+3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 479              		.loc 1 3191 7 is_stmt 1 discriminator 3 view .LVU145
+ 480              	.LVL54:
+3192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       data |= ((uint32_t)(*tmp) << 8U);
+ 481              		.loc 1 3192 7 discriminator 3 view .LVU146
+3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 482              		.loc 1 3193 7 discriminator 3 view .LVU147
+3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 483              		.loc 1 3193 27 is_stmt 0 discriminator 3 view .LVU148
+ 484 0012 6278     		ldrb	r2, [r4, #1]	@ zero_extendqisi2
+3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 485              		.loc 1 3193 12 discriminator 3 view .LVU149
+ 486 0014 43EA0223 		orr	r3, r3, r2, lsl #8
+ 487 0018 0193     		str	r3, [sp, #4]
+3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 488              		.loc 1 3194 7 is_stmt 1 discriminator 3 view .LVU150
+ 489              	.LVL55:
+3195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       data |= ((uint32_t)(*tmp) << 16U);
+ 490              		.loc 1 3195 7 discriminator 3 view .LVU151
+3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 491              		.loc 1 3196 7 discriminator 3 view .LVU152
+3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 492              		.loc 1 3196 27 is_stmt 0 discriminator 3 view .LVU153
+ 493 001a A278     		ldrb	r2, [r4, #2]	@ zero_extendqisi2
+3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 494              		.loc 1 3196 12 discriminator 3 view .LVU154
+ 495 001c 43EA0243 		orr	r3, r3, r2, lsl #16
+ 496 0020 0193     		str	r3, [sp, #4]
+3197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 497              		.loc 1 3197 7 is_stmt 1 discriminator 3 view .LVU155
+ 498              	.LVL56:
+3198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       data |= ((uint32_t)(*tmp) << 24U);
+ 499              		.loc 1 3198 7 discriminator 3 view .LVU156
+3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 500              		.loc 1 3199 7 discriminator 3 view .LVU157
+3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 501              		.loc 1 3199 27 is_stmt 0 discriminator 3 view .LVU158
+ 502 0022 E278     		ldrb	r2, [r4, #3]	@ zero_extendqisi2
+3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tmp++;
+ 503              		.loc 1 3199 12 discriminator 3 view .LVU159
+ 504 0024 43EA0263 		orr	r3, r3, r2, lsl #24
+ 505 0028 0193     		str	r3, [sp, #4]
+3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 506              		.loc 1 3200 7 is_stmt 1 discriminator 3 view .LVU160
+3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ARM GAS  /tmp/ccQEYyKb.s 			page 68
+
+
+ 507              		.loc 1 3200 10 is_stmt 0 discriminator 3 view .LVU161
+ 508 002a 0434     		adds	r4, r4, #4
+ 509              	.LVL57:
+3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+ 510              		.loc 1 3201 7 is_stmt 1 discriminator 3 view .LVU162
+3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+ 511              		.loc 1 3201 20 is_stmt 0 discriminator 3 view .LVU163
+ 512 002c 043E     		subs	r6, r6, #4
+ 513              	.LVL58:
+3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 514              		.loc 1 3202 7 is_stmt 1 discriminator 3 view .LVU164
+3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 515              		.loc 1 3202 13 is_stmt 0 discriminator 3 view .LVU165
+ 516 002e 01A9     		add	r1, sp, #4
+ 517 0030 3868     		ldr	r0, [r7]
+ 518 0032 FFF7FEFF 		bl	SDMMC_WriteFIFO
+ 519              	.LVL59:
+3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 520              		.loc 1 3188 33 is_stmt 1 discriminator 3 view .LVU166
+3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 521              		.loc 1 3188 38 is_stmt 0 discriminator 3 view .LVU167
+ 522 0036 0135     		adds	r5, r5, #1
+ 523              	.LVL60:
+ 524              	.L32:
+3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 525              		.loc 1 3188 21 is_stmt 1 discriminator 1 view .LVU168
+3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 526              		.loc 1 3188 5 is_stmt 0 discriminator 1 view .LVU169
+ 527 0038 072D     		cmp	r5, #7
+ 528 003a E8D9     		bls	.L34
+3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->TxXferSize = dataremaining;
+ 529              		.loc 1 3205 5 is_stmt 1 view .LVU170
+3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->TxXferSize = dataremaining;
+ 530              		.loc 1 3205 21 is_stmt 0 view .LVU171
+ 531 003c 3C62     		str	r4, [r7, #32]
+3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 532              		.loc 1 3206 5 is_stmt 1 view .LVU172
+3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 533              		.loc 1 3206 21 is_stmt 0 view .LVU173
+ 534 003e 7E62     		str	r6, [r7, #36]
+ 535              		.loc 1 3208 1 view .LVU174
+ 536 0040 E3E7     		b	.L31
+ 537              	.LVL61:
+ 538              	.L35:
+ 539              		.loc 1 3208 1 view .LVU175
+ 540 0042 0746     		mov	r7, r0
+3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 541              		.loc 1 3188 15 view .LVU176
+ 542 0044 0025     		movs	r5, #0
+ 543 0046 F7E7     		b	.L32
+ 544              		.cfi_endproc
+ 545              	.LFE182:
+ 547              		.section	.text.SD_SendSDStatus,"ax",%progbits
+ 548              		.align	1
+ 549              		.syntax unified
+ 550              		.thumb
+ 551              		.thumb_func
+ARM GAS  /tmp/ccQEYyKb.s 			page 69
+
+
+ 552              		.fpu fpv5-d16
+ 554              	SD_SendSDStatus:
+ 555              	.LVL62:
+ 556              	.LFB176:
+2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 557              		.loc 1 2813 1 is_stmt 1 view -0
+ 558              		.cfi_startproc
+ 559              		@ args = 0, pretend = 0, frame = 24
+ 560              		@ frame_needed = 0, uses_anonymous_args = 0
+2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 561              		.loc 1 2813 1 is_stmt 0 view .LVU178
+ 562 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 563              	.LCFI10:
+ 564              		.cfi_def_cfa_offset 20
+ 565              		.cfi_offset 4, -20
+ 566              		.cfi_offset 5, -16
+ 567              		.cfi_offset 6, -12
+ 568              		.cfi_offset 7, -8
+ 569              		.cfi_offset 14, -4
+ 570 0002 87B0     		sub	sp, sp, #28
+ 571              	.LCFI11:
+ 572              		.cfi_def_cfa_offset 48
+ 573 0004 0546     		mov	r5, r0
+ 574 0006 0E46     		mov	r6, r1
+2814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 575              		.loc 1 2814 3 is_stmt 1 view .LVU179
+2815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t tickstart = HAL_GetTick();
+ 576              		.loc 1 2815 3 view .LVU180
+2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count;
+ 577              		.loc 1 2816 3 view .LVU181
+2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count;
+ 578              		.loc 1 2816 24 is_stmt 0 view .LVU182
+ 579 0008 FFF7FEFF 		bl	HAL_GetTick
+ 580              	.LVL63:
+2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count;
+ 581              		.loc 1 2816 24 view .LVU183
+ 582 000c 0746     		mov	r7, r0
+ 583              	.LVL64:
+2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t *pData = pSDstatus;
+ 584              		.loc 1 2817 3 is_stmt 1 view .LVU184
+2818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 585              		.loc 1 2818 3 view .LVU185
+2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 586              		.loc 1 2821 3 view .LVU186
+2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 587              		.loc 1 2821 7 is_stmt 0 view .LVU187
+ 588 000e 0021     		movs	r1, #0
+ 589 0010 2868     		ldr	r0, [r5]
+ 590              	.LVL65:
+2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 591              		.loc 1 2821 7 view .LVU188
+ 592 0012 FFF7FEFF 		bl	SDMMC_GetResponse
+ 593              	.LVL66:
+2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 594              		.loc 1 2821 5 view .LVU189
+ 595 0016 10F0007F 		tst	r0, #33554432
+ 596 001a 66D1     		bne	.L48
+ARM GAS  /tmp/ccQEYyKb.s 			page 70
+
+
+2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 597              		.loc 1 2827 3 is_stmt 1 view .LVU190
+2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 598              		.loc 1 2827 16 is_stmt 0 view .LVU191
+ 599 001c 4021     		movs	r1, #64
+ 600 001e 2868     		ldr	r0, [r5]
+ 601 0020 FFF7FEFF 		bl	SDMMC_CmdBlockLength
+ 602              	.LVL67:
+2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 603              		.loc 1 2828 3 is_stmt 1 view .LVU192
+2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 604              		.loc 1 2828 5 is_stmt 0 view .LVU193
+ 605 0024 0346     		mov	r3, r0
+ 606 0026 10B1     		cbz	r0, .L39
+2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+ 607              		.loc 1 2830 5 is_stmt 1 view .LVU194
+2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+ 608              		.loc 1 2830 20 is_stmt 0 view .LVU195
+ 609 0028 AA6B     		ldr	r2, [r5, #56]
+ 610 002a AA63     		str	r2, [r5, #56]
+2831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 611              		.loc 1 2831 5 is_stmt 1 view .LVU196
+2831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 612              		.loc 1 2831 12 is_stmt 0 view .LVU197
+ 613 002c 5FE0     		b	.L37
+ 614              	.L39:
+2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 615              		.loc 1 2835 3 is_stmt 1 view .LVU198
+2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 616              		.loc 1 2835 73 is_stmt 0 view .LVU199
+ 617 002e 296D     		ldr	r1, [r5, #80]
+2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 618              		.loc 1 2835 16 view .LVU200
+ 619 0030 0904     		lsls	r1, r1, #16
+ 620 0032 2868     		ldr	r0, [r5]
+ 621              	.LVL68:
+2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 622              		.loc 1 2835 16 view .LVU201
+ 623 0034 FFF7FEFF 		bl	SDMMC_CmdAppCommand
+ 624              	.LVL69:
+2836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 625              		.loc 1 2836 3 is_stmt 1 view .LVU202
+2836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 626              		.loc 1 2836 5 is_stmt 0 view .LVU203
+ 627 0038 0346     		mov	r3, r0
+ 628 003a 10B1     		cbz	r0, .L40
+2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+ 629              		.loc 1 2838 5 is_stmt 1 view .LVU204
+2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+ 630              		.loc 1 2838 20 is_stmt 0 view .LVU205
+ 631 003c AA6B     		ldr	r2, [r5, #56]
+ 632 003e AA63     		str	r2, [r5, #56]
+2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 633              		.loc 1 2839 5 is_stmt 1 view .LVU206
+2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 634              		.loc 1 2839 12 is_stmt 0 view .LVU207
+ 635 0040 55E0     		b	.L37
+ARM GAS  /tmp/ccQEYyKb.s 			page 71
+
+
+ 636              	.L40:
+2843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataLength    = 64U;
+ 637              		.loc 1 2843 3 is_stmt 1 view .LVU208
+2843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataLength    = 64U;
+ 638              		.loc 1 2843 24 is_stmt 0 view .LVU209
+ 639 0042 4FF0FF33 		mov	r3, #-1
+ 640 0046 0093     		str	r3, [sp]
+2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
+ 641              		.loc 1 2844 3 is_stmt 1 view .LVU210
+2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
+ 642              		.loc 1 2844 24 is_stmt 0 view .LVU211
+ 643 0048 4023     		movs	r3, #64
+ 644 004a 0193     		str	r3, [sp, #4]
+2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 645              		.loc 1 2845 3 is_stmt 1 view .LVU212
+2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 646              		.loc 1 2845 24 is_stmt 0 view .LVU213
+ 647 004c 6023     		movs	r3, #96
+ 648 004e 0293     		str	r3, [sp, #8]
+2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 649              		.loc 1 2846 3 is_stmt 1 view .LVU214
+2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 650              		.loc 1 2846 24 is_stmt 0 view .LVU215
+ 651 0050 0223     		movs	r3, #2
+ 652 0052 0393     		str	r3, [sp, #12]
+2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DPSM          = SDMMC_DPSM_ENABLE;
+ 653              		.loc 1 2847 3 is_stmt 1 view .LVU216
+2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DPSM          = SDMMC_DPSM_ENABLE;
+ 654              		.loc 1 2847 24 is_stmt 0 view .LVU217
+ 655 0054 0023     		movs	r3, #0
+ 656 0056 0493     		str	r3, [sp, #16]
+2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 657              		.loc 1 2848 3 is_stmt 1 view .LVU218
+2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 658              		.loc 1 2848 24 is_stmt 0 view .LVU219
+ 659 0058 0123     		movs	r3, #1
+ 660 005a 0593     		str	r3, [sp, #20]
+2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 661              		.loc 1 2849 3 is_stmt 1 view .LVU220
+2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 662              		.loc 1 2849 9 is_stmt 0 view .LVU221
+ 663 005c 6946     		mov	r1, sp
+ 664 005e 2868     		ldr	r0, [r5]
+ 665              	.LVL70:
+2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 666              		.loc 1 2849 9 view .LVU222
+ 667 0060 FFF7FEFF 		bl	SDMMC_ConfigData
+ 668              	.LVL71:
+2852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 669              		.loc 1 2852 3 is_stmt 1 view .LVU223
+2852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 670              		.loc 1 2852 16 is_stmt 0 view .LVU224
+ 671 0064 2868     		ldr	r0, [r5]
+ 672 0066 FFF7FEFF 		bl	SDMMC_CmdStatusRegister
+ 673              	.LVL72:
+2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 674              		.loc 1 2853 3 is_stmt 1 view .LVU225
+ARM GAS  /tmp/ccQEYyKb.s 			page 72
+
+
+2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 675              		.loc 1 2853 5 is_stmt 0 view .LVU226
+ 676 006a 0346     		mov	r3, r0
+ 677 006c 80B1     		cbz	r0, .L41
+2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+ 678              		.loc 1 2855 5 is_stmt 1 view .LVU227
+2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return errorstate;
+ 679              		.loc 1 2855 20 is_stmt 0 view .LVU228
+ 680 006e AA6B     		ldr	r2, [r5, #56]
+ 681 0070 AA63     		str	r2, [r5, #56]
+2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 682              		.loc 1 2856 5 is_stmt 1 view .LVU229
+2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 683              		.loc 1 2856 12 is_stmt 0 view .LVU230
+ 684 0072 3CE0     		b	.L37
+ 685              	.LVL73:
+ 686              	.L44:
+2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         pData++;
+ 687              		.loc 1 2866 9 is_stmt 1 discriminator 3 view .LVU231
+2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         pData++;
+ 688              		.loc 1 2866 18 is_stmt 0 discriminator 3 view .LVU232
+ 689 0074 2868     		ldr	r0, [r5]
+ 690 0076 FFF7FEFF 		bl	SDMMC_ReadFIFO
+ 691              	.LVL74:
+2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         pData++;
+ 692              		.loc 1 2866 16 discriminator 3 view .LVU233
+ 693 007a 46F8040B 		str	r0, [r6], #4
+ 694              	.LVL75:
+2867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 695              		.loc 1 2867 9 is_stmt 1 discriminator 3 view .LVU234
+2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 696              		.loc 1 2864 35 discriminator 3 view .LVU235
+2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 697              		.loc 1 2864 40 is_stmt 0 discriminator 3 view .LVU236
+ 698 007e 0134     		adds	r4, r4, #1
+ 699              	.LVL76:
+ 700              	.L42:
+2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 701              		.loc 1 2864 23 is_stmt 1 discriminator 1 view .LVU237
+2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 702              		.loc 1 2864 7 is_stmt 0 discriminator 1 view .LVU238
+ 703 0080 072C     		cmp	r4, #7
+ 704 0082 F7D9     		bls	.L44
+ 705              	.LVL77:
+ 706              	.L43:
+2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 707              		.loc 1 2871 5 is_stmt 1 view .LVU239
+2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 708              		.loc 1 2871 9 is_stmt 0 view .LVU240
+ 709 0084 FFF7FEFF 		bl	HAL_GetTick
+ 710              	.LVL78:
+2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 711              		.loc 1 2871 23 view .LVU241
+ 712 0088 C01B     		subs	r0, r0, r7
+2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 713              		.loc 1 2871 7 view .LVU242
+ 714 008a B0F1FF3F 		cmp	r0, #-1
+ARM GAS  /tmp/ccQEYyKb.s 			page 73
+
+
+ 715 008e 31D0     		beq	.L49
+ 716              	.L41:
+2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 717              		.loc 1 2860 8 is_stmt 1 view .LVU243
+2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 718              		.loc 1 2860 10 is_stmt 0 view .LVU244
+ 719 0090 2B68     		ldr	r3, [r5]
+ 720 0092 5C6B     		ldr	r4, [r3, #52]
+ 721 0094 40F22A42 		movw	r2, #1066
+2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 722              		.loc 1 2860 8 view .LVU245
+ 723 0098 1440     		ands	r4, r4, r2
+ 724 009a 04D1     		bne	.L55
+2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 725              		.loc 1 2862 5 is_stmt 1 view .LVU246
+2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 726              		.loc 1 2862 8 is_stmt 0 view .LVU247
+ 727 009c 5B6B     		ldr	r3, [r3, #52]
+2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 728              		.loc 1 2862 7 view .LVU248
+ 729 009e 13F4004F 		tst	r3, #32768
+ 730 00a2 EFD0     		beq	.L43
+ 731 00a4 ECE7     		b	.L42
+ 732              	.L55:
+2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 733              		.loc 1 2877 3 is_stmt 1 view .LVU249
+2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 734              		.loc 1 2877 6 is_stmt 0 view .LVU250
+ 735 00a6 5A6B     		ldr	r2, [r3, #52]
+2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 736              		.loc 1 2877 5 view .LVU251
+ 737 00a8 12F0080F 		tst	r2, #8
+ 738 00ac 25D1     		bne	.L50
+2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 739              		.loc 1 2881 8 is_stmt 1 view .LVU252
+2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 740              		.loc 1 2881 11 is_stmt 0 view .LVU253
+ 741 00ae 5A6B     		ldr	r2, [r3, #52]
+2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 742              		.loc 1 2881 10 view .LVU254
+ 743 00b0 12F0020F 		tst	r2, #2
+ 744 00b4 23D1     		bne	.L51
+2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 745              		.loc 1 2885 8 is_stmt 1 view .LVU255
+2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 746              		.loc 1 2885 11 is_stmt 0 view .LVU256
+ 747 00b6 5B6B     		ldr	r3, [r3, #52]
+2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 748              		.loc 1 2885 10 view .LVU257
+ 749 00b8 13F0200F 		tst	r3, #32
+ 750 00bc 21D1     		bne	.L56
+ 751              	.L46:
+2894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 752              		.loc 1 2894 9 is_stmt 1 view .LVU258
+2894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 753              		.loc 1 2894 11 is_stmt 0 view .LVU259
+ 754 00be 2868     		ldr	r0, [r5]
+ARM GAS  /tmp/ccQEYyKb.s 			page 74
+
+
+ 755 00c0 436B     		ldr	r3, [r0, #52]
+2894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 756              		.loc 1 2894 9 view .LVU260
+ 757 00c2 13F40013 		ands	r3, r3, #2097152
+ 758 00c6 0CD0     		beq	.L57
+2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pData++;
+ 759              		.loc 1 2896 5 is_stmt 1 view .LVU261
+2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pData++;
+ 760              		.loc 1 2896 14 is_stmt 0 view .LVU262
+ 761 00c8 FFF7FEFF 		bl	SDMMC_ReadFIFO
+ 762              	.LVL79:
+2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     pData++;
+ 763              		.loc 1 2896 12 view .LVU263
+ 764 00cc 46F8040B 		str	r0, [r6], #4
+ 765              	.LVL80:
+2897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 766              		.loc 1 2897 5 is_stmt 1 view .LVU264
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 767              		.loc 1 2899 5 view .LVU265
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 768              		.loc 1 2899 9 is_stmt 0 view .LVU266
+ 769 00d0 FFF7FEFF 		bl	HAL_GetTick
+ 770              	.LVL81:
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 771              		.loc 1 2899 23 view .LVU267
+ 772 00d4 C01B     		subs	r0, r0, r7
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 773              		.loc 1 2899 7 view .LVU268
+ 774 00d6 B0F1FF3F 		cmp	r0, #-1
+ 775 00da F0D1     		bne	.L46
+2901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 776              		.loc 1 2901 14 view .LVU269
+ 777 00dc 4FF00043 		mov	r3, #-2147483648
+ 778 00e0 05E0     		b	.L37
+ 779              	.L57:
+2906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 780              		.loc 1 2906 3 is_stmt 1 view .LVU270
+ 781 00e2 40F23A52 		movw	r2, #1338
+ 782 00e6 8263     		str	r2, [r0, #56]
+2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 783              		.loc 1 2908 3 view .LVU271
+2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 784              		.loc 1 2908 10 is_stmt 0 view .LVU272
+ 785 00e8 01E0     		b	.L37
+ 786              	.LVL82:
+ 787              	.L48:
+2823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 788              		.loc 1 2823 12 view .LVU273
+ 789 00ea 4FF40063 		mov	r3, #2048
+ 790              	.LVL83:
+ 791              	.L37:
+2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 792              		.loc 1 2909 1 view .LVU274
+ 793 00ee 1846     		mov	r0, r3
+ 794 00f0 07B0     		add	sp, sp, #28
+ 795              	.LCFI12:
+ 796              		.cfi_remember_state
+ARM GAS  /tmp/ccQEYyKb.s 			page 75
+
+
+ 797              		.cfi_def_cfa_offset 20
+ 798              		@ sp needed
+ 799 00f2 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 800              	.LVL84:
+ 801              	.L49:
+ 802              	.LCFI13:
+ 803              		.cfi_restore_state
+2873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 804              		.loc 1 2873 14 view .LVU275
+ 805 00f4 4FF00043 		mov	r3, #-2147483648
+ 806 00f8 F9E7     		b	.L37
+ 807              	.L50:
+2879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 808              		.loc 1 2879 12 view .LVU276
+ 809 00fa 0823     		movs	r3, #8
+ 810 00fc F7E7     		b	.L37
+ 811              	.L51:
+2883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 812              		.loc 1 2883 12 view .LVU277
+ 813 00fe 0223     		movs	r3, #2
+ 814 0100 F5E7     		b	.L37
+ 815              	.L56:
+2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 816              		.loc 1 2887 12 view .LVU278
+ 817 0102 2023     		movs	r3, #32
+ 818 0104 F3E7     		b	.L37
+ 819              		.cfi_endproc
+ 820              	.LFE176:
+ 822              		.section	.text.SD_FindSCR,"ax",%progbits
+ 823              		.align	1
+ 824              		.syntax unified
+ 825              		.thumb
+ 826              		.thumb_func
+ 827              		.fpu fpv5-d16
+ 829              	SD_FindSCR:
+ 830              	.LVL85:
+ 831              	.LFB180:
+3042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 832              		.loc 1 3042 1 is_stmt 1 view -0
+ 833              		.cfi_startproc
+ 834              		@ args = 0, pretend = 0, frame = 32
+ 835              		@ frame_needed = 0, uses_anonymous_args = 0
+3042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 836              		.loc 1 3042 1 is_stmt 0 view .LVU280
+ 837 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 838              	.LCFI14:
+ 839              		.cfi_def_cfa_offset 20
+ 840              		.cfi_offset 4, -20
+ 841              		.cfi_offset 5, -16
+ 842              		.cfi_offset 6, -12
+ 843              		.cfi_offset 7, -8
+ 844              		.cfi_offset 14, -4
+ 845 0002 89B0     		sub	sp, sp, #36
+ 846              	.LCFI15:
+ 847              		.cfi_def_cfa_offset 56
+ 848 0004 0446     		mov	r4, r0
+ 849 0006 0F46     		mov	r7, r1
+ARM GAS  /tmp/ccQEYyKb.s 			page 76
+
+
+3043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 850              		.loc 1 3043 3 is_stmt 1 view .LVU281
+3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t tickstart = HAL_GetTick();
+ 851              		.loc 1 3044 3 view .LVU282
+3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t index = 0U;
+ 852              		.loc 1 3045 3 view .LVU283
+3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t index = 0U;
+ 853              		.loc 1 3045 24 is_stmt 0 view .LVU284
+ 854 0008 FFF7FEFF 		bl	HAL_GetTick
+ 855              	.LVL86:
+3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t index = 0U;
+ 856              		.loc 1 3045 24 view .LVU285
+ 857 000c 0646     		mov	r6, r0
+ 858              	.LVL87:
+3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t tempscr[2U] = {0U, 0U};
+ 859              		.loc 1 3046 3 is_stmt 1 view .LVU286
+3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t *scr = pSCR;
+ 860              		.loc 1 3047 3 view .LVU287
+3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t *scr = pSCR;
+ 861              		.loc 1 3047 12 is_stmt 0 view .LVU288
+ 862 000e 0023     		movs	r3, #0
+ 863 0010 0093     		str	r3, [sp]
+ 864 0012 0193     		str	r3, [sp, #4]
+3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 865              		.loc 1 3048 3 is_stmt 1 view .LVU289
+ 866              	.LVL88:
+3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 867              		.loc 1 3051 3 view .LVU290
+3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 868              		.loc 1 3051 16 is_stmt 0 view .LVU291
+ 869 0014 0821     		movs	r1, #8
+ 870 0016 2068     		ldr	r0, [r4]
+ 871              	.LVL89:
+3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 872              		.loc 1 3051 16 view .LVU292
+ 873 0018 FFF7FEFF 		bl	SDMMC_CmdBlockLength
+ 874              	.LVL90:
+3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 875              		.loc 1 3052 3 is_stmt 1 view .LVU293
+3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 876              		.loc 1 3052 5 is_stmt 0 view .LVU294
+ 877 001c 0546     		mov	r5, r0
+ 878 001e 10B1     		cbz	r0, .L70
+ 879              	.LVL91:
+ 880              	.L58:
+3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 881              		.loc 1 3130 1 view .LVU295
+ 882 0020 2846     		mov	r0, r5
+ 883 0022 09B0     		add	sp, sp, #36
+ 884              	.LCFI16:
+ 885              		.cfi_remember_state
+ 886              		.cfi_def_cfa_offset 20
+ 887              		@ sp needed
+ 888 0024 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 889              	.LVL92:
+ 890              	.L70:
+ 891              	.LCFI17:
+ARM GAS  /tmp/ccQEYyKb.s 			page 77
+
+
+ 892              		.cfi_restore_state
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 893              		.loc 1 3058 3 is_stmt 1 view .LVU296
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 894              		.loc 1 3058 74 is_stmt 0 view .LVU297
+ 895 0026 216D     		ldr	r1, [r4, #80]
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 896              		.loc 1 3058 16 view .LVU298
+ 897 0028 0904     		lsls	r1, r1, #16
+ 898 002a 2068     		ldr	r0, [r4]
+ 899              	.LVL93:
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 900              		.loc 1 3058 16 view .LVU299
+ 901 002c FFF7FEFF 		bl	SDMMC_CmdAppCommand
+ 902              	.LVL94:
+3059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 903              		.loc 1 3059 3 is_stmt 1 view .LVU300
+3059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 904              		.loc 1 3059 5 is_stmt 0 view .LVU301
+ 905 0030 0546     		mov	r5, r0
+ 906 0032 0028     		cmp	r0, #0
+ 907 0034 F4D1     		bne	.L58
+3064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataLength    = 8U;
+ 908              		.loc 1 3064 3 is_stmt 1 view .LVU302
+3064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataLength    = 8U;
+ 909              		.loc 1 3064 24 is_stmt 0 view .LVU303
+ 910 0036 4FF0FF33 		mov	r3, #-1
+ 911 003a 0293     		str	r3, [sp, #8]
+3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
+ 912              		.loc 1 3065 3 is_stmt 1 view .LVU304
+3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
+ 913              		.loc 1 3065 24 is_stmt 0 view .LVU305
+ 914 003c 0823     		movs	r3, #8
+ 915 003e 0393     		str	r3, [sp, #12]
+3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 916              		.loc 1 3066 3 is_stmt 1 view .LVU306
+3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 917              		.loc 1 3066 24 is_stmt 0 view .LVU307
+ 918 0040 3023     		movs	r3, #48
+ 919 0042 0493     		str	r3, [sp, #16]
+3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 920              		.loc 1 3067 3 is_stmt 1 view .LVU308
+3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 921              		.loc 1 3067 24 is_stmt 0 view .LVU309
+ 922 0044 0223     		movs	r3, #2
+ 923 0046 0593     		str	r3, [sp, #20]
+3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DPSM          = SDMMC_DPSM_ENABLE;
+ 924              		.loc 1 3068 3 is_stmt 1 view .LVU310
+3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   config.DPSM          = SDMMC_DPSM_ENABLE;
+ 925              		.loc 1 3068 24 is_stmt 0 view .LVU311
+ 926 0048 0023     		movs	r3, #0
+ 927 004a 0693     		str	r3, [sp, #24]
+3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 928              		.loc 1 3069 3 is_stmt 1 view .LVU312
+3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 929              		.loc 1 3069 24 is_stmt 0 view .LVU313
+ 930 004c 0123     		movs	r3, #1
+ARM GAS  /tmp/ccQEYyKb.s 			page 78
+
+
+ 931 004e 0793     		str	r3, [sp, #28]
+3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 932              		.loc 1 3070 3 is_stmt 1 view .LVU314
+3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 933              		.loc 1 3070 9 is_stmt 0 view .LVU315
+ 934 0050 02A9     		add	r1, sp, #8
+ 935 0052 2068     		ldr	r0, [r4]
+ 936              	.LVL95:
+3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 937              		.loc 1 3070 9 view .LVU316
+ 938 0054 FFF7FEFF 		bl	SDMMC_ConfigData
+ 939              	.LVL96:
+3073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 940              		.loc 1 3073 3 is_stmt 1 view .LVU317
+3073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 941              		.loc 1 3073 16 is_stmt 0 view .LVU318
+ 942 0058 2068     		ldr	r0, [r4]
+ 943 005a FFF7FEFF 		bl	SDMMC_CmdSendSCR
+ 944              	.LVL97:
+3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 945              		.loc 1 3074 3 is_stmt 1 view .LVU319
+3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 946              		.loc 1 3074 5 is_stmt 0 view .LVU320
+ 947 005e 0546     		mov	r5, r0
+ 948 0060 58B1     		cbz	r0, .L60
+ 949 0062 DDE7     		b	.L58
+ 950              	.LVL98:
+ 951              	.L71:
+3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       index++;
+ 952              		.loc 1 3083 7 is_stmt 1 view .LVU321
+3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       index++;
+ 953              		.loc 1 3083 28 is_stmt 0 view .LVU322
+ 954 0064 FFF7FEFF 		bl	SDMMC_ReadFIFO
+ 955              	.LVL99:
+3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       index++;
+ 956              		.loc 1 3083 26 view .LVU323
+ 957 0068 4DF82500 		str	r0, [sp, r5, lsl #2]
+3084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 958              		.loc 1 3084 7 is_stmt 1 view .LVU324
+3084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 959              		.loc 1 3084 12 is_stmt 0 view .LVU325
+ 960 006c 0135     		adds	r5, r5, #1
+ 961              	.LVL100:
+ 962              	.L62:
+3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 963              		.loc 1 3091 5 is_stmt 1 view .LVU326
+3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 964              		.loc 1 3091 9 is_stmt 0 view .LVU327
+ 965 006e FFF7FEFF 		bl	HAL_GetTick
+ 966              	.LVL101:
+3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 967              		.loc 1 3091 23 view .LVU328
+ 968 0072 831B     		subs	r3, r0, r6
+3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 969              		.loc 1 3091 7 view .LVU329
+ 970 0074 B3F1FF3F 		cmp	r3, #-1
+ 971 0078 3FD0     		beq	.L68
+ARM GAS  /tmp/ccQEYyKb.s 			page 79
+
+
+ 972              	.LVL102:
+ 973              	.L60:
+3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 974              		.loc 1 3079 8 is_stmt 1 view .LVU330
+3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 975              		.loc 1 3079 10 is_stmt 0 view .LVU331
+ 976 007a 2068     		ldr	r0, [r4]
+ 977 007c 436B     		ldr	r3, [r0, #52]
+3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 978              		.loc 1 3079 8 view .LVU332
+ 979 007e 13F02A0F 		tst	r3, #42
+ 980 0082 07D1     		bne	.L63
+3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 981              		.loc 1 3081 5 is_stmt 1 view .LVU333
+3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 982              		.loc 1 3081 8 is_stmt 0 view .LVU334
+ 983 0084 436B     		ldr	r3, [r0, #52]
+3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 984              		.loc 1 3081 7 view .LVU335
+ 985 0086 13F4001F 		tst	r3, #2097152
+ 986 008a EBD1     		bne	.L71
+3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 987              		.loc 1 3086 10 is_stmt 1 view .LVU336
+3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 988              		.loc 1 3086 14 is_stmt 0 view .LVU337
+ 989 008c 436B     		ldr	r3, [r0, #52]
+3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 990              		.loc 1 3086 12 view .LVU338
+ 991 008e 13F4005F 		tst	r3, #8192
+ 992 0092 ECD1     		bne	.L62
+ 993              	.L63:
+3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 994              		.loc 1 3097 3 is_stmt 1 view .LVU339
+3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 995              		.loc 1 3097 6 is_stmt 0 view .LVU340
+ 996 0094 436B     		ldr	r3, [r0, #52]
+3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 997              		.loc 1 3097 5 view .LVU341
+ 998 0096 13F0080F 		tst	r3, #8
+ 999 009a 25D1     		bne	.L72
+3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1000              		.loc 1 3103 8 is_stmt 1 view .LVU342
+3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1001              		.loc 1 3103 11 is_stmt 0 view .LVU343
+ 1002 009c 436B     		ldr	r3, [r0, #52]
+3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1003              		.loc 1 3103 10 view .LVU344
+ 1004 009e 13F0020F 		tst	r3, #2
+ 1005 00a2 24D1     		bne	.L73
+3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1006              		.loc 1 3109 8 is_stmt 1 view .LVU345
+3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1007              		.loc 1 3109 11 is_stmt 0 view .LVU346
+ 1008 00a4 456B     		ldr	r5, [r0, #52]
+ 1009              	.LVL103:
+3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1010              		.loc 1 3109 10 view .LVU347
+ARM GAS  /tmp/ccQEYyKb.s 			page 80
+
+
+ 1011 00a6 15F02005 		ands	r5, r5, #32
+ 1012 00aa 23D1     		bne	.L74
+3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1013              		.loc 1 3119 5 is_stmt 1 view .LVU348
+ 1014 00ac 40F23A53 		movw	r3, #1338
+ 1015 00b0 8363     		str	r3, [r0, #56]
+3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ 1016              		.loc 1 3121 5 view .LVU349
+3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ 1017              		.loc 1 3121 22 is_stmt 0 view .LVU350
+ 1018 00b2 019A     		ldr	r2, [sp, #4]
+3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ 1019              		.loc 1 3121 86 view .LVU351
+ 1020 00b4 1302     		lsls	r3, r2, #8
+ 1021 00b6 03F47F03 		and	r3, r3, #16711680
+3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ 1022              		.loc 1 3121 52 view .LVU352
+ 1023 00ba 43EA0263 		orr	r3, r3, r2, lsl #24
+3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     scr++;
+ 1024              		.loc 1 3122 46 view .LVU353
+ 1025 00be 110A     		lsrs	r1, r2, #8
+ 1026 00c0 01F47F41 		and	r1, r1, #65280
+3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ 1027              		.loc 1 3121 92 view .LVU354
+ 1028 00c4 0B43     		orrs	r3, r3, r1
+3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     scr++;
+ 1029              		.loc 1 3122 52 view .LVU355
+ 1030 00c6 43EA1263 		orr	r3, r3, r2, lsr #24
+3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ 1031              		.loc 1 3121 10 view .LVU356
+ 1032 00ca 3B60     		str	r3, [r7]
+3123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
+ 1033              		.loc 1 3123 5 is_stmt 1 view .LVU357
+ 1034              	.LVL104:
+3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+ 1035              		.loc 1 3124 5 view .LVU358
+3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+ 1036              		.loc 1 3124 22 is_stmt 0 view .LVU359
+ 1037 00cc 009A     		ldr	r2, [sp]
+3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+ 1038              		.loc 1 3124 86 view .LVU360
+ 1039 00ce 1302     		lsls	r3, r2, #8
+ 1040 00d0 03F47F03 		and	r3, r3, #16711680
+3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+ 1041              		.loc 1 3124 52 view .LVU361
+ 1042 00d4 43EA0263 		orr	r3, r3, r2, lsl #24
+3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1043              		.loc 1 3125 46 view .LVU362
+ 1044 00d8 110A     		lsrs	r1, r2, #8
+ 1045 00da 01F47F41 		and	r1, r1, #65280
+3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+ 1046              		.loc 1 3124 92 view .LVU363
+ 1047 00de 0B43     		orrs	r3, r3, r1
+3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1048              		.loc 1 3125 52 view .LVU364
+ 1049 00e0 43EA1263 		orr	r3, r3, r2, lsr #24
+3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****             ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+ARM GAS  /tmp/ccQEYyKb.s 			page 81
+
+
+ 1050              		.loc 1 3124 10 view .LVU365
+ 1051 00e4 7B60     		str	r3, [r7, #4]
+3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 1052              		.loc 1 3129 3 is_stmt 1 view .LVU366
+3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 1053              		.loc 1 3129 10 is_stmt 0 view .LVU367
+ 1054 00e6 9BE7     		b	.L58
+ 1055              	.LVL105:
+ 1056              	.L72:
+3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1057              		.loc 1 3099 5 is_stmt 1 view .LVU368
+ 1058 00e8 0825     		movs	r5, #8
+ 1059              	.LVL106:
+3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1060              		.loc 1 3099 5 is_stmt 0 view .LVU369
+ 1061 00ea 8563     		str	r5, [r0, #56]
+3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1062              		.loc 1 3101 5 is_stmt 1 view .LVU370
+3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1063              		.loc 1 3101 12 is_stmt 0 view .LVU371
+ 1064 00ec 98E7     		b	.L58
+ 1065              	.LVL107:
+ 1066              	.L73:
+3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1067              		.loc 1 3105 5 is_stmt 1 view .LVU372
+ 1068 00ee 0225     		movs	r5, #2
+ 1069              	.LVL108:
+3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1070              		.loc 1 3105 5 is_stmt 0 view .LVU373
+ 1071 00f0 8563     		str	r5, [r0, #56]
+3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1072              		.loc 1 3107 5 is_stmt 1 view .LVU374
+3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1073              		.loc 1 3107 12 is_stmt 0 view .LVU375
+ 1074 00f2 95E7     		b	.L58
+ 1075              	.L74:
+3111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1076              		.loc 1 3111 5 is_stmt 1 view .LVU376
+ 1077 00f4 2025     		movs	r5, #32
+ 1078 00f6 8563     		str	r5, [r0, #56]
+3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1079              		.loc 1 3113 5 view .LVU377
+3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1080              		.loc 1 3113 12 is_stmt 0 view .LVU378
+ 1081 00f8 92E7     		b	.L58
+ 1082              	.LVL109:
+ 1083              	.L68:
+3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1084              		.loc 1 3093 14 view .LVU379
+ 1085 00fa 4FF00045 		mov	r5, #-2147483648
+ 1086              	.LVL110:
+3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1087              		.loc 1 3093 14 view .LVU380
+ 1088 00fe 8FE7     		b	.L58
+ 1089              		.cfi_endproc
+ 1090              	.LFE180:
+ 1092              		.section	.text.SD_WideBus_Enable,"ax",%progbits
+ARM GAS  /tmp/ccQEYyKb.s 			page 82
+
+
+ 1093              		.align	1
+ 1094              		.syntax unified
+ 1095              		.thumb
+ 1096              		.thumb_func
+ 1097              		.fpu fpv5-d16
+ 1099              	SD_WideBus_Enable:
+ 1100              	.LVL111:
+ 1101              	.LFB178:
+2946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t scr[2U] = {0U, 0U};
+ 1102              		.loc 1 2946 1 is_stmt 1 view -0
+ 1103              		.cfi_startproc
+ 1104              		@ args = 0, pretend = 0, frame = 8
+ 1105              		@ frame_needed = 0, uses_anonymous_args = 0
+2946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t scr[2U] = {0U, 0U};
+ 1106              		.loc 1 2946 1 is_stmt 0 view .LVU382
+ 1107 0000 10B5     		push	{r4, lr}
+ 1108              	.LCFI18:
+ 1109              		.cfi_def_cfa_offset 8
+ 1110              		.cfi_offset 4, -8
+ 1111              		.cfi_offset 14, -4
+ 1112 0002 82B0     		sub	sp, sp, #8
+ 1113              	.LCFI19:
+ 1114              		.cfi_def_cfa_offset 16
+ 1115 0004 0446     		mov	r4, r0
+2947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 1116              		.loc 1 2947 3 is_stmt 1 view .LVU383
+2947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 1117              		.loc 1 2947 12 is_stmt 0 view .LVU384
+ 1118 0006 0021     		movs	r1, #0
+ 1119 0008 0091     		str	r1, [sp]
+ 1120 000a 0191     		str	r1, [sp, #4]
+2948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1121              		.loc 1 2948 3 is_stmt 1 view .LVU385
+2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1122              		.loc 1 2950 3 view .LVU386
+2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1123              		.loc 1 2950 7 is_stmt 0 view .LVU387
+ 1124 000c 0068     		ldr	r0, [r0]
+ 1125              	.LVL112:
+2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1126              		.loc 1 2950 7 view .LVU388
+ 1127 000e FFF7FEFF 		bl	SDMMC_GetResponse
+ 1128              	.LVL113:
+2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1129              		.loc 1 2950 5 view .LVU389
+ 1130 0012 10F0007F 		tst	r0, #33554432
+ 1131 0016 13D1     		bne	.L77
+2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 1132              		.loc 1 2956 3 is_stmt 1 view .LVU390
+2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 1133              		.loc 1 2956 16 is_stmt 0 view .LVU391
+ 1134 0018 6946     		mov	r1, sp
+ 1135 001a 2046     		mov	r0, r4
+ 1136 001c FFF7FEFF 		bl	SD_FindSCR
+ 1137              	.LVL114:
+2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1138              		.loc 1 2957 3 is_stmt 1 view .LVU392
+ARM GAS  /tmp/ccQEYyKb.s 			page 83
+
+
+2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1139              		.loc 1 2957 5 is_stmt 0 view .LVU393
+ 1140 0020 80B9     		cbnz	r0, .L75
+2963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1141              		.loc 1 2963 3 is_stmt 1 view .LVU394
+2963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1142              		.loc 1 2963 5 is_stmt 0 view .LVU395
+ 1143 0022 019B     		ldr	r3, [sp, #4]
+ 1144 0024 13F4802F 		tst	r3, #262144
+ 1145 0028 0ED0     		beq	.L78
+2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1146              		.loc 1 2966 5 is_stmt 1 view .LVU396
+2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1147              		.loc 1 2966 75 is_stmt 0 view .LVU397
+ 1148 002a 216D     		ldr	r1, [r4, #80]
+2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1149              		.loc 1 2966 18 view .LVU398
+ 1150 002c 0904     		lsls	r1, r1, #16
+ 1151 002e 2068     		ldr	r0, [r4]
+ 1152              	.LVL115:
+2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1153              		.loc 1 2966 18 view .LVU399
+ 1154 0030 FFF7FEFF 		bl	SDMMC_CmdAppCommand
+ 1155              	.LVL116:
+2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1156              		.loc 1 2967 5 is_stmt 1 view .LVU400
+2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1157              		.loc 1 2967 7 is_stmt 0 view .LVU401
+ 1158 0034 30B9     		cbnz	r0, .L75
+2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1159              		.loc 1 2973 5 is_stmt 1 view .LVU402
+2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1160              		.loc 1 2973 18 is_stmt 0 view .LVU403
+ 1161 0036 0221     		movs	r1, #2
+ 1162 0038 2068     		ldr	r0, [r4]
+ 1163              	.LVL117:
+2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1164              		.loc 1 2973 18 view .LVU404
+ 1165 003a FFF7FEFF 		bl	SDMMC_CmdBusWidth
+ 1166              	.LVL118:
+2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1167              		.loc 1 2974 5 is_stmt 1 view .LVU405
+ 1168 003e 01E0     		b	.L75
+ 1169              	.LVL119:
+ 1170              	.L77:
+2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1171              		.loc 1 2952 12 is_stmt 0 view .LVU406
+ 1172 0040 4FF40060 		mov	r0, #2048
+ 1173              	.L75:
+2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1174              		.loc 1 2985 1 view .LVU407
+ 1175 0044 02B0     		add	sp, sp, #8
+ 1176              	.LCFI20:
+ 1177              		.cfi_remember_state
+ 1178              		.cfi_def_cfa_offset 8
+ 1179              		@ sp needed
+ 1180 0046 10BD     		pop	{r4, pc}
+ARM GAS  /tmp/ccQEYyKb.s 			page 84
+
+
+ 1181              	.LVL120:
+ 1182              	.L78:
+ 1183              	.LCFI21:
+ 1184              		.cfi_restore_state
+2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1185              		.loc 1 2983 12 view .LVU408
+ 1186 0048 4FF08060 		mov	r0, #67108864
+ 1187              	.LVL121:
+2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1188              		.loc 1 2983 12 view .LVU409
+ 1189 004c FAE7     		b	.L75
+ 1190              		.cfi_endproc
+ 1191              	.LFE178:
+ 1193              		.section	.text.SD_WideBus_Disable,"ax",%progbits
+ 1194              		.align	1
+ 1195              		.syntax unified
+ 1196              		.thumb
+ 1197              		.thumb_func
+ 1198              		.fpu fpv5-d16
+ 1200              	SD_WideBus_Disable:
+ 1201              	.LVL122:
+ 1202              	.LFB179:
+2993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t scr[2U] = {0U, 0U};
+ 1203              		.loc 1 2993 1 is_stmt 1 view -0
+ 1204              		.cfi_startproc
+ 1205              		@ args = 0, pretend = 0, frame = 8
+ 1206              		@ frame_needed = 0, uses_anonymous_args = 0
+2993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t scr[2U] = {0U, 0U};
+ 1207              		.loc 1 2993 1 is_stmt 0 view .LVU411
+ 1208 0000 10B5     		push	{r4, lr}
+ 1209              	.LCFI22:
+ 1210              		.cfi_def_cfa_offset 8
+ 1211              		.cfi_offset 4, -8
+ 1212              		.cfi_offset 14, -4
+ 1213 0002 82B0     		sub	sp, sp, #8
+ 1214              	.LCFI23:
+ 1215              		.cfi_def_cfa_offset 16
+ 1216 0004 0446     		mov	r4, r0
+2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 1217              		.loc 1 2994 3 is_stmt 1 view .LVU412
+2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 1218              		.loc 1 2994 12 is_stmt 0 view .LVU413
+ 1219 0006 0021     		movs	r1, #0
+ 1220 0008 0091     		str	r1, [sp]
+ 1221 000a 0191     		str	r1, [sp, #4]
+2995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1222              		.loc 1 2995 3 is_stmt 1 view .LVU414
+2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1223              		.loc 1 2997 3 view .LVU415
+2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1224              		.loc 1 2997 7 is_stmt 0 view .LVU416
+ 1225 000c 0068     		ldr	r0, [r0]
+ 1226              	.LVL123:
+2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1227              		.loc 1 2997 7 view .LVU417
+ 1228 000e FFF7FEFF 		bl	SDMMC_GetResponse
+ 1229              	.LVL124:
+ARM GAS  /tmp/ccQEYyKb.s 			page 85
+
+
+2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1230              		.loc 1 2997 5 view .LVU418
+ 1231 0012 10F0007F 		tst	r0, #33554432
+ 1232 0016 13D1     		bne	.L82
+3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 1233              		.loc 1 3003 3 is_stmt 1 view .LVU419
+3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 1234              		.loc 1 3003 16 is_stmt 0 view .LVU420
+ 1235 0018 6946     		mov	r1, sp
+ 1236 001a 2046     		mov	r0, r4
+ 1237 001c FFF7FEFF 		bl	SD_FindSCR
+ 1238              	.LVL125:
+3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1239              		.loc 1 3004 3 is_stmt 1 view .LVU421
+3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1240              		.loc 1 3004 5 is_stmt 0 view .LVU422
+ 1241 0020 80B9     		cbnz	r0, .L80
+3010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1242              		.loc 1 3010 3 is_stmt 1 view .LVU423
+3010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1243              		.loc 1 3010 5 is_stmt 0 view .LVU424
+ 1244 0022 019B     		ldr	r3, [sp, #4]
+ 1245 0024 13F4803F 		tst	r3, #65536
+ 1246 0028 0ED0     		beq	.L83
+3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1247              		.loc 1 3013 5 is_stmt 1 view .LVU425
+3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1248              		.loc 1 3013 75 is_stmt 0 view .LVU426
+ 1249 002a 216D     		ldr	r1, [r4, #80]
+3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1250              		.loc 1 3013 18 view .LVU427
+ 1251 002c 0904     		lsls	r1, r1, #16
+ 1252 002e 2068     		ldr	r0, [r4]
+ 1253              	.LVL126:
+3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1254              		.loc 1 3013 18 view .LVU428
+ 1255 0030 FFF7FEFF 		bl	SDMMC_CmdAppCommand
+ 1256              	.LVL127:
+3014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1257              		.loc 1 3014 5 is_stmt 1 view .LVU429
+3014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1258              		.loc 1 3014 7 is_stmt 0 view .LVU430
+ 1259 0034 30B9     		cbnz	r0, .L80
+3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1260              		.loc 1 3020 5 is_stmt 1 view .LVU431
+3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1261              		.loc 1 3020 18 is_stmt 0 view .LVU432
+ 1262 0036 0021     		movs	r1, #0
+ 1263 0038 2068     		ldr	r0, [r4]
+ 1264              	.LVL128:
+3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 1265              		.loc 1 3020 18 view .LVU433
+ 1266 003a FFF7FEFF 		bl	SDMMC_CmdBusWidth
+ 1267              	.LVL129:
+3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1268              		.loc 1 3021 5 is_stmt 1 view .LVU434
+ 1269 003e 01E0     		b	.L80
+ARM GAS  /tmp/ccQEYyKb.s 			page 86
+
+
+ 1270              	.LVL130:
+ 1271              	.L82:
+2999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1272              		.loc 1 2999 12 is_stmt 0 view .LVU435
+ 1273 0040 4FF40060 		mov	r0, #2048
+ 1274              	.L80:
+3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1275              		.loc 1 3032 1 view .LVU436
+ 1276 0044 02B0     		add	sp, sp, #8
+ 1277              	.LCFI24:
+ 1278              		.cfi_remember_state
+ 1279              		.cfi_def_cfa_offset 8
+ 1280              		@ sp needed
+ 1281 0046 10BD     		pop	{r4, pc}
+ 1282              	.LVL131:
+ 1283              	.L83:
+ 1284              	.LCFI25:
+ 1285              		.cfi_restore_state
+3030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1286              		.loc 1 3030 12 view .LVU437
+ 1287 0048 4FF08060 		mov	r0, #67108864
+ 1288              	.LVL132:
+3030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1289              		.loc 1 3030 12 view .LVU438
+ 1290 004c FAE7     		b	.L80
+ 1291              		.cfi_endproc
+ 1292              	.LFE179:
+ 1294              		.section	.text.SD_SendStatus,"ax",%progbits
+ 1295              		.align	1
+ 1296              		.syntax unified
+ 1297              		.thumb
+ 1298              		.thumb_func
+ 1299              		.fpu fpv5-d16
+ 1301              	SD_SendStatus:
+ 1302              	.LVL133:
+ 1303              	.LFB177:
+2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 1304              		.loc 1 2919 1 is_stmt 1 view -0
+ 1305              		.cfi_startproc
+ 1306              		@ args = 0, pretend = 0, frame = 0
+ 1307              		@ frame_needed = 0, uses_anonymous_args = 0
+2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 1308              		.loc 1 2919 1 is_stmt 0 view .LVU440
+ 1309 0000 70B5     		push	{r4, r5, r6, lr}
+ 1310              	.LCFI26:
+ 1311              		.cfi_def_cfa_offset 16
+ 1312              		.cfi_offset 4, -16
+ 1313              		.cfi_offset 5, -12
+ 1314              		.cfi_offset 6, -8
+ 1315              		.cfi_offset 14, -4
+2920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1316              		.loc 1 2920 3 is_stmt 1 view .LVU441
+2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1317              		.loc 1 2922 3 view .LVU442
+2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1318              		.loc 1 2922 5 is_stmt 0 view .LVU443
+ 1319 0002 81B1     		cbz	r1, .L87
+ARM GAS  /tmp/ccQEYyKb.s 			page 87
+
+
+ 1320 0004 0446     		mov	r4, r0
+ 1321 0006 0E46     		mov	r6, r1
+2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 1322              		.loc 1 2928 3 is_stmt 1 view .LVU444
+2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 1323              		.loc 1 2928 73 is_stmt 0 view .LVU445
+ 1324 0008 016D     		ldr	r1, [r0, #80]
+ 1325              	.LVL134:
+2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 1326              		.loc 1 2928 16 view .LVU446
+ 1327 000a 0904     		lsls	r1, r1, #16
+ 1328 000c 0068     		ldr	r0, [r0]
+ 1329              	.LVL135:
+2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 1330              		.loc 1 2928 16 view .LVU447
+ 1331 000e FFF7FEFF 		bl	SDMMC_CmdSendStatus
+ 1332              	.LVL136:
+2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1333              		.loc 1 2929 3 is_stmt 1 view .LVU448
+2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1334              		.loc 1 2929 5 is_stmt 0 view .LVU449
+ 1335 0012 0546     		mov	r5, r0
+ 1336 0014 08B1     		cbz	r0, .L89
+ 1337              	.LVL137:
+ 1338              	.L85:
+2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1339              		.loc 1 2938 1 view .LVU450
+ 1340 0016 2846     		mov	r0, r5
+ 1341 0018 70BD     		pop	{r4, r5, r6, pc}
+ 1342              	.LVL138:
+ 1343              	.L89:
+2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1344              		.loc 1 2935 3 is_stmt 1 view .LVU451
+2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1345              		.loc 1 2935 18 is_stmt 0 view .LVU452
+ 1346 001a 0021     		movs	r1, #0
+ 1347 001c 2068     		ldr	r0, [r4]
+ 1348              	.LVL139:
+2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1349              		.loc 1 2935 18 view .LVU453
+ 1350 001e FFF7FEFF 		bl	SDMMC_GetResponse
+ 1351              	.LVL140:
+2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1352              		.loc 1 2935 16 view .LVU454
+ 1353 0022 3060     		str	r0, [r6]
+2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 1354              		.loc 1 2937 3 is_stmt 1 view .LVU455
+2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 1355              		.loc 1 2937 10 is_stmt 0 view .LVU456
+ 1356 0024 F7E7     		b	.L85
+ 1357              	.LVL141:
+ 1358              	.L87:
+2924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1359              		.loc 1 2924 12 view .LVU457
+ 1360 0026 4FF00065 		mov	r5, #134217728
+ 1361 002a F4E7     		b	.L85
+ 1362              		.cfi_endproc
+ARM GAS  /tmp/ccQEYyKb.s 			page 88
+
+
+ 1363              	.LFE177:
+ 1365              		.section	.text.HAL_SD_MspInit,"ax",%progbits
+ 1366              		.align	1
+ 1367              		.weak	HAL_SD_MspInit
+ 1368              		.syntax unified
+ 1369              		.thumb
+ 1370              		.thumb_func
+ 1371              		.fpu fpv5-d16
+ 1373              	HAL_SD_MspInit:
+ 1374              	.LVL142:
+ 1375              	.LFB144:
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+ 1376              		.loc 1 515 1 is_stmt 1 view -0
+ 1377              		.cfi_startproc
+ 1378              		@ args = 0, pretend = 0, frame = 0
+ 1379              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1380              		@ link register save eliminated.
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1381              		.loc 1 517 3 view .LVU459
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1382              		.loc 1 522 1 is_stmt 0 view .LVU460
+ 1383 0000 7047     		bx	lr
+ 1384              		.cfi_endproc
+ 1385              	.LFE144:
+ 1387              		.section	.text.HAL_SD_MspDeInit,"ax",%progbits
+ 1388              		.align	1
+ 1389              		.weak	HAL_SD_MspDeInit
+ 1390              		.syntax unified
+ 1391              		.thumb
+ 1392              		.thumb_func
+ 1393              		.fpu fpv5-d16
+ 1395              	HAL_SD_MspDeInit:
+ 1396              	.LVL143:
+ 1397              	.LFB145:
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+ 1398              		.loc 1 530 1 is_stmt 1 view -0
+ 1399              		.cfi_startproc
+ 1400              		@ args = 0, pretend = 0, frame = 0
+ 1401              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1402              		@ link register save eliminated.
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1403              		.loc 1 532 3 view .LVU462
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1404              		.loc 1 537 1 is_stmt 0 view .LVU463
+ 1405 0000 7047     		bx	lr
+ 1406              		.cfi_endproc
+ 1407              	.LFE145:
+ 1409              		.section	.text.HAL_SD_DeInit,"ax",%progbits
+ 1410              		.align	1
+ 1411              		.global	HAL_SD_DeInit
+ 1412              		.syntax unified
+ 1413              		.thumb
+ 1414              		.thumb_func
+ 1415              		.fpu fpv5-d16
+ 1417              	HAL_SD_DeInit:
+ 1418              	.LVL144:
+ 1419              	.LFB143:
+ARM GAS  /tmp/ccQEYyKb.s 			page 89
+
+
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check the SD handle allocation */
+ 1420              		.loc 1 474 1 is_stmt 1 view -0
+ 1421              		.cfi_startproc
+ 1422              		@ args = 0, pretend = 0, frame = 0
+ 1423              		@ frame_needed = 0, uses_anonymous_args = 0
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1424              		.loc 1 476 3 view .LVU465
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1425              		.loc 1 476 5 is_stmt 0 view .LVU466
+ 1426 0000 70B1     		cbz	r0, .L94
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check the SD handle allocation */
+ 1427              		.loc 1 474 1 view .LVU467
+ 1428 0002 10B5     		push	{r4, lr}
+ 1429              	.LCFI27:
+ 1430              		.cfi_def_cfa_offset 8
+ 1431              		.cfi_offset 4, -8
+ 1432              		.cfi_offset 14, -4
+ 1433 0004 0446     		mov	r4, r0
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1434              		.loc 1 482 3 is_stmt 1 view .LVU468
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1435              		.loc 1 484 3 view .LVU469
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1436              		.loc 1 484 14 is_stmt 0 view .LVU470
+ 1437 0006 0323     		movs	r3, #3
+ 1438 0008 80F83430 		strb	r3, [r0, #52]
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1439              		.loc 1 487 3 is_stmt 1 view .LVU471
+ 1440 000c FFF7FEFF 		bl	SD_PowerOFF
+ 1441              	.LVL145:
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 1442              		.loc 1 499 3 view .LVU472
+ 1443 0010 2046     		mov	r0, r4
+ 1444 0012 FFF7FEFF 		bl	HAL_SD_MspDeInit
+ 1445              	.LVL146:
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_RESET;
+ 1446              		.loc 1 502 3 view .LVU473
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_RESET;
+ 1447              		.loc 1 502 18 is_stmt 0 view .LVU474
+ 1448 0016 0020     		movs	r0, #0
+ 1449 0018 A063     		str	r0, [r4, #56]
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1450              		.loc 1 503 3 is_stmt 1 view .LVU475
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1451              		.loc 1 503 14 is_stmt 0 view .LVU476
+ 1452 001a 84F83400 		strb	r0, [r4, #52]
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 1453              		.loc 1 505 3 is_stmt 1 view .LVU477
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1454              		.loc 1 506 1 is_stmt 0 view .LVU478
+ 1455 001e 10BD     		pop	{r4, pc}
+ 1456              	.LVL147:
+ 1457              	.L94:
+ 1458              	.LCFI28:
+ 1459              		.cfi_def_cfa_offset 0
+ 1460              		.cfi_restore 4
+ 1461              		.cfi_restore 14
+ARM GAS  /tmp/ccQEYyKb.s 			page 90
+
+
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1462              		.loc 1 478 12 view .LVU479
+ 1463 0020 0120     		movs	r0, #1
+ 1464              	.LVL148:
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1465              		.loc 1 506 1 view .LVU480
+ 1466 0022 7047     		bx	lr
+ 1467              		.cfi_endproc
+ 1468              	.LFE143:
+ 1470              		.section	.text.HAL_SD_ReadBlocks,"ax",%progbits
+ 1471              		.align	1
+ 1472              		.global	HAL_SD_ReadBlocks
+ 1473              		.syntax unified
+ 1474              		.thumb
+ 1475              		.thumb_func
+ 1476              		.fpu fpv5-d16
+ 1478              	HAL_SD_ReadBlocks:
+ 1479              	.LVL149:
+ 1480              	.LFB146:
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 1481              		.loc 1 571 1 is_stmt 1 view -0
+ 1482              		.cfi_startproc
+ 1483              		@ args = 4, pretend = 0, frame = 24
+ 1484              		@ frame_needed = 0, uses_anonymous_args = 0
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 1485              		.loc 1 571 1 is_stmt 0 view .LVU482
+ 1486 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 1487              	.LCFI29:
+ 1488              		.cfi_def_cfa_offset 36
+ 1489              		.cfi_offset 4, -36
+ 1490              		.cfi_offset 5, -32
+ 1491              		.cfi_offset 6, -28
+ 1492              		.cfi_offset 7, -24
+ 1493              		.cfi_offset 8, -20
+ 1494              		.cfi_offset 9, -16
+ 1495              		.cfi_offset 10, -12
+ 1496              		.cfi_offset 11, -8
+ 1497              		.cfi_offset 14, -4
+ 1498 0004 87B0     		sub	sp, sp, #28
+ 1499              	.LCFI30:
+ 1500              		.cfi_def_cfa_offset 64
+ 1501 0006 0546     		mov	r5, r0
+ 1502 0008 0C46     		mov	r4, r1
+ 1503 000a 1646     		mov	r6, r2
+ 1504 000c 9B46     		mov	fp, r3
+ 1505 000e DDF840A0 		ldr	r10, [sp, #64]
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 1506              		.loc 1 572 3 is_stmt 1 view .LVU483
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t tickstart = HAL_GetTick();
+ 1507              		.loc 1 573 3 view .LVU484
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count, data, dataremaining;
+ 1508              		.loc 1 574 3 view .LVU485
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count, data, dataremaining;
+ 1509              		.loc 1 574 24 is_stmt 0 view .LVU486
+ 1510 0012 FFF7FEFF 		bl	HAL_GetTick
+ 1511              	.LVL150:
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+ARM GAS  /tmp/ccQEYyKb.s 			page 91
+
+
+ 1512              		.loc 1 575 3 is_stmt 1 view .LVU487
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint8_t *tempbuff = pData;
+ 1513              		.loc 1 576 3 view .LVU488
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1514              		.loc 1 577 3 view .LVU489
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1515              		.loc 1 579 3 view .LVU490
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1516              		.loc 1 579 5 is_stmt 0 view .LVU491
+ 1517 0016 002C     		cmp	r4, #0
+ 1518 0018 36D0     		beq	.L122
+ 1519 001a 8146     		mov	r9, r0
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1520              		.loc 1 585 3 is_stmt 1 view .LVU492
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1521              		.loc 1 585 9 is_stmt 0 view .LVU493
+ 1522 001c 95F83470 		ldrb	r7, [r5, #52]	@ zero_extendqisi2
+ 1523 0020 FFB2     		uxtb	r7, r7
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 1524              		.loc 1 585 5 view .LVU494
+ 1525 0022 012F     		cmp	r7, #1
+ 1526 0024 40F00481 		bne	.L102
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1527              		.loc 1 587 5 is_stmt 1 view .LVU495
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1528              		.loc 1 587 20 is_stmt 0 view .LVU496
+ 1529 0028 0023     		movs	r3, #0
+ 1530 002a AB63     		str	r3, [r5, #56]
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1531              		.loc 1 589 5 is_stmt 1 view .LVU497
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1532              		.loc 1 589 13 is_stmt 0 view .LVU498
+ 1533 002c 06EB0B03 		add	r3, r6, fp
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1534              		.loc 1 589 45 view .LVU499
+ 1535 0030 EA6D     		ldr	r2, [r5, #92]
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1536              		.loc 1 589 7 view .LVU500
+ 1537 0032 9342     		cmp	r3, r2
+ 1538 0034 2ED8     		bhi	.L123
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1539              		.loc 1 595 5 is_stmt 1 view .LVU501
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1540              		.loc 1 595 16 is_stmt 0 view .LVU502
+ 1541 0036 0323     		movs	r3, #3
+ 1542 0038 85F83430 		strb	r3, [r5, #52]
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1543              		.loc 1 598 5 is_stmt 1 view .LVU503
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1544              		.loc 1 598 8 is_stmt 0 view .LVU504
+ 1545 003c 2B68     		ldr	r3, [r5]
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1546              		.loc 1 598 26 view .LVU505
+ 1547 003e 0022     		movs	r2, #0
+ 1548 0040 DA62     		str	r2, [r3, #44]
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1549              		.loc 1 600 5 is_stmt 1 view .LVU506
+ARM GAS  /tmp/ccQEYyKb.s 			page 92
+
+
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1550              		.loc 1 600 19 is_stmt 0 view .LVU507
+ 1551 0042 6B6C     		ldr	r3, [r5, #68]
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1552              		.loc 1 600 7 view .LVU508
+ 1553 0044 012B     		cmp	r3, #1
+ 1554 0046 00D0     		beq	.L104
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1555              		.loc 1 602 7 is_stmt 1 view .LVU509
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1556              		.loc 1 602 11 is_stmt 0 view .LVU510
+ 1557 0048 7602     		lsls	r6, r6, #9
+ 1558              	.LVL151:
+ 1559              	.L104:
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+ 1560              		.loc 1 606 5 is_stmt 1 view .LVU511
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+ 1561              		.loc 1 606 26 is_stmt 0 view .LVU512
+ 1562 004a 4FF0FF33 		mov	r3, #-1
+ 1563 004e 0093     		str	r3, [sp]
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 1564              		.loc 1 607 5 is_stmt 1 view .LVU513
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 1565              		.loc 1 607 43 is_stmt 0 view .LVU514
+ 1566 0050 4FEA4B23 		lsl	r3, fp, #9
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 1567              		.loc 1 607 26 view .LVU515
+ 1568 0054 0193     		str	r3, [sp, #4]
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 1569              		.loc 1 608 5 is_stmt 1 view .LVU516
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 1570              		.loc 1 608 26 is_stmt 0 view .LVU517
+ 1571 0056 9023     		movs	r3, #144
+ 1572 0058 0293     		str	r3, [sp, #8]
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 1573              		.loc 1 609 5 is_stmt 1 view .LVU518
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 1574              		.loc 1 609 26 is_stmt 0 view .LVU519
+ 1575 005a 0223     		movs	r3, #2
+ 1576 005c 0393     		str	r3, [sp, #12]
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+ 1577              		.loc 1 610 5 is_stmt 1 view .LVU520
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+ 1578              		.loc 1 610 26 is_stmt 0 view .LVU521
+ 1579 005e 0023     		movs	r3, #0
+ 1580 0060 0493     		str	r3, [sp, #16]
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 1581              		.loc 1 611 5 is_stmt 1 view .LVU522
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 1582              		.loc 1 611 26 is_stmt 0 view .LVU523
+ 1583 0062 0123     		movs	r3, #1
+ 1584 0064 0593     		str	r3, [sp, #20]
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1585              		.loc 1 612 5 is_stmt 1 view .LVU524
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1586              		.loc 1 612 11 is_stmt 0 view .LVU525
+ 1587 0066 6946     		mov	r1, sp
+ARM GAS  /tmp/ccQEYyKb.s 			page 93
+
+
+ 1588 0068 2868     		ldr	r0, [r5]
+ 1589              	.LVL152:
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1590              		.loc 1 612 11 view .LVU526
+ 1591 006a FFF7FEFF 		bl	SDMMC_ConfigData
+ 1592              	.LVL153:
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1593              		.loc 1 615 5 is_stmt 1 view .LVU527
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1594              		.loc 1 615 7 is_stmt 0 view .LVU528
+ 1595 006e BBF1010F 		cmp	fp, #1
+ 1596 0072 14D9     		bls	.L105
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1597              		.loc 1 617 7 is_stmt 1 view .LVU529
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1598              		.loc 1 617 20 is_stmt 0 view .LVU530
+ 1599 0074 0223     		movs	r3, #2
+ 1600 0076 2B63     		str	r3, [r5, #48]
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1601              		.loc 1 620 7 is_stmt 1 view .LVU531
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1602              		.loc 1 620 20 is_stmt 0 view .LVU532
+ 1603 0078 3146     		mov	r1, r6
+ 1604 007a 2868     		ldr	r0, [r5]
+ 1605 007c FFF7FEFF 		bl	SDMMC_CmdReadMultiBlock
+ 1606              	.LVL154:
+ 1607              	.L106:
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1608              		.loc 1 629 5 is_stmt 1 view .LVU533
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1609              		.loc 1 629 7 is_stmt 0 view .LVU534
+ 1610 0080 A0B9     		cbnz	r0, .L124
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | 
+ 1611              		.loc 1 640 5 is_stmt 1 view .LVU535
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | 
+ 1612              		.loc 1 640 19 is_stmt 0 view .LVU536
+ 1613 0082 DDF80480 		ldr	r8, [sp, #4]
+ 1614              	.LVL155:
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1615              		.loc 1 641 5 is_stmt 1 view .LVU537
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1616              		.loc 1 641 10 is_stmt 0 view .LVU538
+ 1617 0086 38E0     		b	.L108
+ 1618              	.LVL156:
+ 1619              	.L122:
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 1620              		.loc 1 581 5 is_stmt 1 view .LVU539
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 1621              		.loc 1 581 20 is_stmt 0 view .LVU540
+ 1622 0088 AB6B     		ldr	r3, [r5, #56]
+ 1623 008a 43F00063 		orr	r3, r3, #134217728
+ 1624 008e AB63     		str	r3, [r5, #56]
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1625              		.loc 1 582 5 is_stmt 1 view .LVU541
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 1626              		.loc 1 582 12 is_stmt 0 view .LVU542
+ 1627 0090 0127     		movs	r7, #1
+ARM GAS  /tmp/ccQEYyKb.s 			page 94
+
+
+ 1628 0092 D2E0     		b	.L101
+ 1629              	.L123:
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 1630              		.loc 1 591 7 is_stmt 1 view .LVU543
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 1631              		.loc 1 591 22 is_stmt 0 view .LVU544
+ 1632 0094 AB6B     		ldr	r3, [r5, #56]
+ 1633 0096 43F00073 		orr	r3, r3, #33554432
+ 1634 009a AB63     		str	r3, [r5, #56]
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1635              		.loc 1 592 7 is_stmt 1 view .LVU545
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1636              		.loc 1 592 14 is_stmt 0 view .LVU546
+ 1637 009c CDE0     		b	.L101
+ 1638              	.LVL157:
+ 1639              	.L105:
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1640              		.loc 1 624 7 is_stmt 1 view .LVU547
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1641              		.loc 1 624 20 is_stmt 0 view .LVU548
+ 1642 009e 0123     		movs	r3, #1
+ 1643 00a0 2B63     		str	r3, [r5, #48]
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1644              		.loc 1 627 7 is_stmt 1 view .LVU549
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1645              		.loc 1 627 20 is_stmt 0 view .LVU550
+ 1646 00a2 3146     		mov	r1, r6
+ 1647 00a4 2868     		ldr	r0, [r5]
+ 1648 00a6 FFF7FEFF 		bl	SDMMC_CmdReadSingleBlock
+ 1649              	.LVL158:
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1650              		.loc 1 627 20 view .LVU551
+ 1651 00aa E9E7     		b	.L106
+ 1652              	.L124:
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+ 1653              		.loc 1 632 7 is_stmt 1 view .LVU552
+ 1654 00ac 2B68     		ldr	r3, [r5]
+ 1655 00ae 654A     		ldr	r2, .L130
+ 1656 00b0 9A63     		str	r2, [r3, #56]
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 1657              		.loc 1 633 7 view .LVU553
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 1658              		.loc 1 633 22 is_stmt 0 view .LVU554
+ 1659 00b2 AB6B     		ldr	r3, [r5, #56]
+ 1660 00b4 1843     		orrs	r0, r0, r3
+ 1661              	.LVL159:
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 1662              		.loc 1 633 22 view .LVU555
+ 1663 00b6 A863     		str	r0, [r5, #56]
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 1664              		.loc 1 634 7 is_stmt 1 view .LVU556
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 1665              		.loc 1 634 18 is_stmt 0 view .LVU557
+ 1666 00b8 0123     		movs	r3, #1
+ 1667 00ba 85F83430 		strb	r3, [r5, #52]
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 1668              		.loc 1 635 7 is_stmt 1 view .LVU558
+ARM GAS  /tmp/ccQEYyKb.s 			page 95
+
+
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 1669              		.loc 1 635 20 is_stmt 0 view .LVU559
+ 1670 00be 0023     		movs	r3, #0
+ 1671 00c0 2B63     		str	r3, [r5, #48]
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1672              		.loc 1 636 7 is_stmt 1 view .LVU560
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1673              		.loc 1 636 14 is_stmt 0 view .LVU561
+ 1674 00c2 BAE0     		b	.L101
+ 1675              	.LVL160:
+ 1676              	.L111:
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           *tempbuff = (uint8_t)(data & 0xFFU);
+ 1677              		.loc 1 648 11 is_stmt 1 discriminator 3 view .LVU562
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           *tempbuff = (uint8_t)(data & 0xFFU);
+ 1678              		.loc 1 648 18 is_stmt 0 discriminator 3 view .LVU563
+ 1679 00c4 2868     		ldr	r0, [r5]
+ 1680 00c6 FFF7FEFF 		bl	SDMMC_ReadFIFO
+ 1681              	.LVL161:
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 1682              		.loc 1 649 11 is_stmt 1 discriminator 3 view .LVU564
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 1683              		.loc 1 649 21 is_stmt 0 discriminator 3 view .LVU565
+ 1684 00ca 2070     		strb	r0, [r4]
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 1685              		.loc 1 650 11 is_stmt 1 discriminator 3 view .LVU566
+ 1686              	.LVL162:
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ 1687              		.loc 1 651 11 discriminator 3 view .LVU567
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 1688              		.loc 1 652 11 discriminator 3 view .LVU568
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 1689              		.loc 1 652 23 is_stmt 0 discriminator 3 view .LVU569
+ 1690 00cc C0F30723 		ubfx	r3, r0, #8, #8
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 1691              		.loc 1 652 21 discriminator 3 view .LVU570
+ 1692 00d0 6370     		strb	r3, [r4, #1]
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 1693              		.loc 1 653 11 is_stmt 1 discriminator 3 view .LVU571
+ 1694              	.LVL163:
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ 1695              		.loc 1 654 11 discriminator 3 view .LVU572
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 1696              		.loc 1 655 11 discriminator 3 view .LVU573
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 1697              		.loc 1 655 23 is_stmt 0 discriminator 3 view .LVU574
+ 1698 00d2 C0F30743 		ubfx	r3, r0, #16, #8
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 1699              		.loc 1 655 21 discriminator 3 view .LVU575
+ 1700 00d6 A370     		strb	r3, [r4, #2]
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 1701              		.loc 1 656 11 is_stmt 1 discriminator 3 view .LVU576
+ 1702              	.LVL164:
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ 1703              		.loc 1 657 11 discriminator 3 view .LVU577
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 1704              		.loc 1 658 11 discriminator 3 view .LVU578
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ARM GAS  /tmp/ccQEYyKb.s 			page 96
+
+
+ 1705              		.loc 1 658 23 is_stmt 0 discriminator 3 view .LVU579
+ 1706 00d8 000E     		lsrs	r0, r0, #24
+ 1707              	.LVL165:
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 1708              		.loc 1 658 21 discriminator 3 view .LVU580
+ 1709 00da E070     		strb	r0, [r4, #3]
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 1710              		.loc 1 659 11 is_stmt 1 discriminator 3 view .LVU581
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 1711              		.loc 1 659 19 is_stmt 0 discriminator 3 view .LVU582
+ 1712 00dc 0434     		adds	r4, r4, #4
+ 1713              	.LVL166:
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 1714              		.loc 1 660 11 is_stmt 1 discriminator 3 view .LVU583
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 1715              		.loc 1 660 24 is_stmt 0 discriminator 3 view .LVU584
+ 1716 00de A8F10408 		sub	r8, r8, #4
+ 1717              	.LVL167:
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 1718              		.loc 1 646 37 is_stmt 1 discriminator 3 view .LVU585
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 1719              		.loc 1 646 42 is_stmt 0 discriminator 3 view .LVU586
+ 1720 00e2 0136     		adds	r6, r6, #1
+ 1721              	.LVL168:
+ 1722              	.L110:
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 1723              		.loc 1 646 25 is_stmt 1 discriminator 1 view .LVU587
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 1724              		.loc 1 646 9 is_stmt 0 discriminator 1 view .LVU588
+ 1725 00e4 072E     		cmp	r6, #7
+ 1726 00e6 EDD9     		bls	.L111
+ 1727              	.LVL169:
+ 1728              	.L109:
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1729              		.loc 1 664 7 is_stmt 1 view .LVU589
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1730              		.loc 1 664 12 is_stmt 0 view .LVU590
+ 1731 00e8 FFF7FEFF 		bl	HAL_GetTick
+ 1732              	.LVL170:
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1733              		.loc 1 664 25 view .LVU591
+ 1734 00ec A0EB0900 		sub	r0, r0, r9
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1735              		.loc 1 664 9 view .LVU592
+ 1736 00f0 5045     		cmp	r0, r10
+ 1737 00f2 0FD2     		bcs	.L112
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1738              		.loc 1 664 50 discriminator 1 view .LVU593
+ 1739 00f4 BAF1000F 		cmp	r10, #0
+ 1740 00f8 0CD0     		beq	.L112
+ 1741              	.L108:
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1742              		.loc 1 641 10 is_stmt 1 view .LVU594
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1743              		.loc 1 641 12 is_stmt 0 view .LVU595
+ 1744 00fa 2868     		ldr	r0, [r5]
+ 1745 00fc 466B     		ldr	r6, [r0, #52]
+ARM GAS  /tmp/ccQEYyKb.s 			page 97
+
+
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1746              		.loc 1 641 10 view .LVU596
+ 1747 00fe 16F49576 		ands	r6, r6, #298
+ 1748 0102 15D1     		bne	.L125
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1749              		.loc 1 643 7 is_stmt 1 view .LVU597
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1750              		.loc 1 643 10 is_stmt 0 view .LVU598
+ 1751 0104 436B     		ldr	r3, [r0, #52]
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1752              		.loc 1 643 9 view .LVU599
+ 1753 0106 13F4004F 		tst	r3, #32768
+ 1754 010a EDD0     		beq	.L109
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1755              		.loc 1 643 54 discriminator 1 view .LVU600
+ 1756 010c B8F1000F 		cmp	r8, #0
+ 1757 0110 EAD0     		beq	.L109
+ 1758 0112 E7E7     		b	.L110
+ 1759              	.L112:
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+ 1760              		.loc 1 667 9 is_stmt 1 view .LVU601
+ 1761 0114 2B68     		ldr	r3, [r5]
+ 1762 0116 4B4A     		ldr	r2, .L130
+ 1763 0118 9A63     		str	r2, [r3, #56]
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State= HAL_SD_STATE_READY;
+ 1764              		.loc 1 668 9 view .LVU602
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State= HAL_SD_STATE_READY;
+ 1765              		.loc 1 668 24 is_stmt 0 view .LVU603
+ 1766 011a AB6B     		ldr	r3, [r5, #56]
+ 1767 011c 43F00043 		orr	r3, r3, #-2147483648
+ 1768 0120 AB63     		str	r3, [r5, #56]
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 1769              		.loc 1 669 9 is_stmt 1 view .LVU604
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 1770              		.loc 1 669 19 is_stmt 0 view .LVU605
+ 1771 0122 0123     		movs	r3, #1
+ 1772 0124 85F83430 		strb	r3, [r5, #52]
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_TIMEOUT;
+ 1773              		.loc 1 670 9 is_stmt 1 view .LVU606
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_TIMEOUT;
+ 1774              		.loc 1 670 22 is_stmt 0 view .LVU607
+ 1775 0128 0023     		movs	r3, #0
+ 1776 012a 2B63     		str	r3, [r5, #48]
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 1777              		.loc 1 671 9 is_stmt 1 view .LVU608
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 1778              		.loc 1 671 16 is_stmt 0 view .LVU609
+ 1779 012c 0327     		movs	r7, #3
+ 1780 012e 84E0     		b	.L101
+ 1781              	.L125:
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1782              		.loc 1 676 5 is_stmt 1 view .LVU610
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1783              		.loc 1 676 8 is_stmt 0 view .LVU611
+ 1784 0130 436B     		ldr	r3, [r0, #52]
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1785              		.loc 1 676 7 view .LVU612
+ARM GAS  /tmp/ccQEYyKb.s 			page 98
+
+
+ 1786 0132 13F4807F 		tst	r3, #256
+ 1787 0136 05D0     		beq	.L114
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1788              		.loc 1 676 51 discriminator 1 view .LVU613
+ 1789 0138 BBF1010F 		cmp	fp, #1
+ 1790 013c 02D9     		bls	.L114
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1791              		.loc 1 678 7 is_stmt 1 view .LVU614
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1792              		.loc 1 678 21 is_stmt 0 view .LVU615
+ 1793 013e 6B6C     		ldr	r3, [r5, #68]
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1794              		.loc 1 678 9 view .LVU616
+ 1795 0140 032B     		cmp	r3, #3
+ 1796 0142 38D1     		bne	.L126
+ 1797              	.L114:
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1798              		.loc 1 695 5 is_stmt 1 view .LVU617
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1799              		.loc 1 695 8 is_stmt 0 view .LVU618
+ 1800 0144 2B68     		ldr	r3, [r5]
+ 1801 0146 5A6B     		ldr	r2, [r3, #52]
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1802              		.loc 1 695 7 view .LVU619
+ 1803 0148 12F0080F 		tst	r2, #8
+ 1804 014c 44D1     		bne	.L127
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1805              		.loc 1 704 10 is_stmt 1 view .LVU620
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1806              		.loc 1 704 13 is_stmt 0 view .LVU621
+ 1807 014e 5A6B     		ldr	r2, [r3, #52]
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1808              		.loc 1 704 12 view .LVU622
+ 1809 0150 12F0020F 		tst	r2, #2
+ 1810 0154 4CD1     		bne	.L128
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1811              		.loc 1 713 10 is_stmt 1 view .LVU623
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1812              		.loc 1 713 13 is_stmt 0 view .LVU624
+ 1813 0156 5A6B     		ldr	r2, [r3, #52]
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1814              		.loc 1 713 12 view .LVU625
+ 1815 0158 12F0200F 		tst	r2, #32
+ 1816 015c 54D1     		bne	.L129
+ 1817              	.L117:
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1818              		.loc 1 728 11 is_stmt 1 view .LVU626
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1819              		.loc 1 728 13 is_stmt 0 view .LVU627
+ 1820 015e 2868     		ldr	r0, [r5]
+ 1821 0160 436B     		ldr	r3, [r0, #52]
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1822              		.loc 1 728 11 view .LVU628
+ 1823 0162 13F4001F 		tst	r3, #2097152
+ 1824 0166 5BD0     		beq	.L119
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 1825              		.loc 1 728 56 discriminator 1 view .LVU629
+ARM GAS  /tmp/ccQEYyKb.s 			page 99
+
+
+ 1826 0168 B8F1000F 		cmp	r8, #0
+ 1827 016c 58D0     		beq	.L119
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tempbuff = (uint8_t)(data & 0xFFU);
+ 1828              		.loc 1 730 7 is_stmt 1 view .LVU630
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tempbuff = (uint8_t)(data & 0xFFU);
+ 1829              		.loc 1 730 14 is_stmt 0 view .LVU631
+ 1830 016e FFF7FEFF 		bl	SDMMC_ReadFIFO
+ 1831              	.LVL171:
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 1832              		.loc 1 731 7 is_stmt 1 view .LVU632
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 1833              		.loc 1 731 17 is_stmt 0 view .LVU633
+ 1834 0172 2070     		strb	r0, [r4]
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 1835              		.loc 1 732 7 is_stmt 1 view .LVU634
+ 1836              	.LVL172:
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ 1837              		.loc 1 733 7 view .LVU635
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 1838              		.loc 1 734 7 view .LVU636
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 1839              		.loc 1 734 19 is_stmt 0 view .LVU637
+ 1840 0174 C0F30723 		ubfx	r3, r0, #8, #8
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 1841              		.loc 1 734 17 view .LVU638
+ 1842 0178 6370     		strb	r3, [r4, #1]
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 1843              		.loc 1 735 7 is_stmt 1 view .LVU639
+ 1844              	.LVL173:
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ 1845              		.loc 1 736 7 view .LVU640
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 1846              		.loc 1 737 7 view .LVU641
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 1847              		.loc 1 737 19 is_stmt 0 view .LVU642
+ 1848 017a C0F30743 		ubfx	r3, r0, #16, #8
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 1849              		.loc 1 737 17 view .LVU643
+ 1850 017e A370     		strb	r3, [r4, #2]
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 1851              		.loc 1 738 7 is_stmt 1 view .LVU644
+ 1852              	.LVL174:
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ 1853              		.loc 1 739 7 view .LVU645
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 1854              		.loc 1 740 7 view .LVU646
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 1855              		.loc 1 740 19 is_stmt 0 view .LVU647
+ 1856 0180 000E     		lsrs	r0, r0, #24
+ 1857              	.LVL175:
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       tempbuff++;
+ 1858              		.loc 1 740 17 view .LVU648
+ 1859 0182 E070     		strb	r0, [r4, #3]
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 1860              		.loc 1 741 7 is_stmt 1 view .LVU649
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       dataremaining--;
+ 1861              		.loc 1 741 15 is_stmt 0 view .LVU650
+ARM GAS  /tmp/ccQEYyKb.s 			page 100
+
+
+ 1862 0184 0434     		adds	r4, r4, #4
+ 1863              	.LVL176:
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1864              		.loc 1 742 7 is_stmt 1 view .LVU651
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1865              		.loc 1 742 20 is_stmt 0 view .LVU652
+ 1866 0186 A8F10408 		sub	r8, r8, #4
+ 1867              	.LVL177:
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1868              		.loc 1 744 7 is_stmt 1 view .LVU653
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1869              		.loc 1 744 12 is_stmt 0 view .LVU654
+ 1870 018a FFF7FEFF 		bl	HAL_GetTick
+ 1871              	.LVL178:
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1872              		.loc 1 744 25 view .LVU655
+ 1873 018e A0EB0900 		sub	r0, r0, r9
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1874              		.loc 1 744 9 view .LVU656
+ 1875 0192 5045     		cmp	r0, r10
+ 1876 0194 02D2     		bcs	.L118
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 1877              		.loc 1 744 50 discriminator 1 view .LVU657
+ 1878 0196 BAF1000F 		cmp	r10, #0
+ 1879 019a E0D1     		bne	.L117
+ 1880              	.L118:
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+ 1881              		.loc 1 747 9 is_stmt 1 view .LVU658
+ 1882 019c 2B68     		ldr	r3, [r5]
+ 1883 019e 294A     		ldr	r2, .L130
+ 1884 01a0 9A63     		str	r2, [r3, #56]
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State= HAL_SD_STATE_READY;
+ 1885              		.loc 1 748 9 view .LVU659
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State= HAL_SD_STATE_READY;
+ 1886              		.loc 1 748 24 is_stmt 0 view .LVU660
+ 1887 01a2 AB6B     		ldr	r3, [r5, #56]
+ 1888 01a4 43F00043 		orr	r3, r3, #-2147483648
+ 1889 01a8 AB63     		str	r3, [r5, #56]
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 1890              		.loc 1 749 9 is_stmt 1 view .LVU661
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 1891              		.loc 1 749 19 is_stmt 0 view .LVU662
+ 1892 01aa 0123     		movs	r3, #1
+ 1893 01ac 85F83430 		strb	r3, [r5, #52]
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+ 1894              		.loc 1 750 9 is_stmt 1 view .LVU663
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+ 1895              		.loc 1 750 22 is_stmt 0 view .LVU664
+ 1896 01b0 0023     		movs	r3, #0
+ 1897 01b2 2B63     		str	r3, [r5, #48]
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 1898              		.loc 1 751 9 is_stmt 1 view .LVU665
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 1899              		.loc 1 751 16 is_stmt 0 view .LVU666
+ 1900 01b4 41E0     		b	.L101
+ 1901              	.L126:
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ARM GAS  /tmp/ccQEYyKb.s 			page 101
+
+
+ 1902              		.loc 1 681 9 is_stmt 1 view .LVU667
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ 1903              		.loc 1 681 22 is_stmt 0 view .LVU668
+ 1904 01b6 FFF7FEFF 		bl	SDMMC_CmdStopTransfer
+ 1905              	.LVL179:
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 1906              		.loc 1 682 9 is_stmt 1 view .LVU669
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 1907              		.loc 1 682 11 is_stmt 0 view .LVU670
+ 1908 01ba 0346     		mov	r3, r0
+ 1909 01bc 0028     		cmp	r0, #0
+ 1910 01be C1D0     		beq	.L114
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->ErrorCode |= errorstate;
+ 1911              		.loc 1 685 11 is_stmt 1 view .LVU671
+ 1912 01c0 2A68     		ldr	r2, [r5]
+ 1913 01c2 2049     		ldr	r1, .L130
+ 1914 01c4 9163     		str	r1, [r2, #56]
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->State = HAL_SD_STATE_READY;
+ 1915              		.loc 1 686 11 view .LVU672
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->State = HAL_SD_STATE_READY;
+ 1916              		.loc 1 686 26 is_stmt 0 view .LVU673
+ 1917 01c6 AA6B     		ldr	r2, [r5, #56]
+ 1918 01c8 1343     		orrs	r3, r3, r2
+ 1919 01ca AB63     		str	r3, [r5, #56]
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->Context = SD_CONTEXT_NONE;
+ 1920              		.loc 1 687 11 is_stmt 1 view .LVU674
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->Context = SD_CONTEXT_NONE;
+ 1921              		.loc 1 687 22 is_stmt 0 view .LVU675
+ 1922 01cc 0123     		movs	r3, #1
+ 1923 01ce 85F83430 		strb	r3, [r5, #52]
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           return HAL_ERROR;
+ 1924              		.loc 1 688 11 is_stmt 1 view .LVU676
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           return HAL_ERROR;
+ 1925              		.loc 1 688 24 is_stmt 0 view .LVU677
+ 1926 01d2 0023     		movs	r3, #0
+ 1927 01d4 2B63     		str	r3, [r5, #48]
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 1928              		.loc 1 689 11 is_stmt 1 view .LVU678
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 1929              		.loc 1 689 18 is_stmt 0 view .LVU679
+ 1930 01d6 30E0     		b	.L101
+ 1931              	.LVL180:
+ 1932              	.L127:
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ 1933              		.loc 1 698 7 is_stmt 1 view .LVU680
+ 1934 01d8 1A4A     		ldr	r2, .L130
+ 1935 01da 9A63     		str	r2, [r3, #56]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 1936              		.loc 1 699 7 view .LVU681
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 1937              		.loc 1 699 22 is_stmt 0 view .LVU682
+ 1938 01dc AB6B     		ldr	r3, [r5, #56]
+ 1939 01de 43F00803 		orr	r3, r3, #8
+ 1940 01e2 AB63     		str	r3, [r5, #56]
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 1941              		.loc 1 700 7 is_stmt 1 view .LVU683
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ARM GAS  /tmp/ccQEYyKb.s 			page 102
+
+
+ 1942              		.loc 1 700 18 is_stmt 0 view .LVU684
+ 1943 01e4 0123     		movs	r3, #1
+ 1944 01e6 85F83430 		strb	r3, [r5, #52]
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 1945              		.loc 1 701 7 is_stmt 1 view .LVU685
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 1946              		.loc 1 701 20 is_stmt 0 view .LVU686
+ 1947 01ea 0023     		movs	r3, #0
+ 1948 01ec 2B63     		str	r3, [r5, #48]
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1949              		.loc 1 702 7 is_stmt 1 view .LVU687
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1950              		.loc 1 702 14 is_stmt 0 view .LVU688
+ 1951 01ee 24E0     		b	.L101
+ 1952              	.L128:
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ 1953              		.loc 1 707 7 is_stmt 1 view .LVU689
+ 1954 01f0 144A     		ldr	r2, .L130
+ 1955 01f2 9A63     		str	r2, [r3, #56]
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 1956              		.loc 1 708 7 view .LVU690
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 1957              		.loc 1 708 22 is_stmt 0 view .LVU691
+ 1958 01f4 AB6B     		ldr	r3, [r5, #56]
+ 1959 01f6 43F00203 		orr	r3, r3, #2
+ 1960 01fa AB63     		str	r3, [r5, #56]
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 1961              		.loc 1 709 7 is_stmt 1 view .LVU692
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 1962              		.loc 1 709 18 is_stmt 0 view .LVU693
+ 1963 01fc 0123     		movs	r3, #1
+ 1964 01fe 85F83430 		strb	r3, [r5, #52]
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 1965              		.loc 1 710 7 is_stmt 1 view .LVU694
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 1966              		.loc 1 710 20 is_stmt 0 view .LVU695
+ 1967 0202 0023     		movs	r3, #0
+ 1968 0204 2B63     		str	r3, [r5, #48]
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1969              		.loc 1 711 7 is_stmt 1 view .LVU696
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1970              		.loc 1 711 14 is_stmt 0 view .LVU697
+ 1971 0206 18E0     		b	.L101
+ 1972              	.L129:
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ 1973              		.loc 1 716 7 is_stmt 1 view .LVU698
+ 1974 0208 0E4A     		ldr	r2, .L130
+ 1975 020a 9A63     		str	r2, [r3, #56]
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 1976              		.loc 1 717 7 view .LVU699
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 1977              		.loc 1 717 22 is_stmt 0 view .LVU700
+ 1978 020c AB6B     		ldr	r3, [r5, #56]
+ 1979 020e 43F02003 		orr	r3, r3, #32
+ 1980 0212 AB63     		str	r3, [r5, #56]
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 1981              		.loc 1 718 7 is_stmt 1 view .LVU701
+ARM GAS  /tmp/ccQEYyKb.s 			page 103
+
+
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 1982              		.loc 1 718 18 is_stmt 0 view .LVU702
+ 1983 0214 0123     		movs	r3, #1
+ 1984 0216 85F83430 		strb	r3, [r5, #52]
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 1985              		.loc 1 719 7 is_stmt 1 view .LVU703
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 1986              		.loc 1 719 20 is_stmt 0 view .LVU704
+ 1987 021a 0023     		movs	r3, #0
+ 1988 021c 2B63     		str	r3, [r5, #48]
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1989              		.loc 1 720 7 is_stmt 1 view .LVU705
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 1990              		.loc 1 720 14 is_stmt 0 view .LVU706
+ 1991 021e 0CE0     		b	.L101
+ 1992              	.L119:
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1993              		.loc 1 756 5 is_stmt 1 view .LVU707
+ 1994 0220 40F23A53 		movw	r3, #1338
+ 1995 0224 8363     		str	r3, [r0, #56]
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1996              		.loc 1 758 5 view .LVU708
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 1997              		.loc 1 758 16 is_stmt 0 view .LVU709
+ 1998 0226 0123     		movs	r3, #1
+ 1999 0228 85F83430 		strb	r3, [r5, #52]
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2000              		.loc 1 760 5 is_stmt 1 view .LVU710
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2001              		.loc 1 760 12 is_stmt 0 view .LVU711
+ 2002 022c 0027     		movs	r7, #0
+ 2003 022e 04E0     		b	.L101
+ 2004              	.LVL181:
+ 2005              	.L102:
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2006              		.loc 1 764 5 is_stmt 1 view .LVU712
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2007              		.loc 1 764 20 is_stmt 0 view .LVU713
+ 2008 0230 AB6B     		ldr	r3, [r5, #56]
+ 2009 0232 43F00053 		orr	r3, r3, #536870912
+ 2010 0236 AB63     		str	r3, [r5, #56]
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2011              		.loc 1 765 5 is_stmt 1 view .LVU714
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2012              		.loc 1 765 12 is_stmt 0 view .LVU715
+ 2013 0238 0127     		movs	r7, #1
+ 2014              	.LVL182:
+ 2015              	.L101:
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2016              		.loc 1 767 1 view .LVU716
+ 2017 023a 3846     		mov	r0, r7
+ 2018 023c 07B0     		add	sp, sp, #28
+ 2019              	.LCFI31:
+ 2020              		.cfi_def_cfa_offset 36
+ 2021              		@ sp needed
+ 2022 023e BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 2023              	.LVL183:
+ARM GAS  /tmp/ccQEYyKb.s 			page 104
+
+
+ 2024              	.L131:
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2025              		.loc 1 767 1 view .LVU717
+ 2026 0242 00BF     		.align	2
+ 2027              	.L130:
+ 2028 0244 FF054000 		.word	4195839
+ 2029              		.cfi_endproc
+ 2030              	.LFE146:
+ 2032              		.section	.text.HAL_SD_WriteBlocks,"ax",%progbits
+ 2033              		.align	1
+ 2034              		.global	HAL_SD_WriteBlocks
+ 2035              		.syntax unified
+ 2036              		.thumb
+ 2037              		.thumb_func
+ 2038              		.fpu fpv5-d16
+ 2040              	HAL_SD_WriteBlocks:
+ 2041              	.LVL184:
+ 2042              	.LFB147:
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 2043              		.loc 1 782 1 is_stmt 1 view -0
+ 2044              		.cfi_startproc
+ 2045              		@ args = 4, pretend = 0, frame = 40
+ 2046              		@ frame_needed = 0, uses_anonymous_args = 0
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 2047              		.loc 1 782 1 is_stmt 0 view .LVU719
+ 2048 0000 2DE9F04F 		push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 2049              	.LCFI32:
+ 2050              		.cfi_def_cfa_offset 36
+ 2051              		.cfi_offset 4, -36
+ 2052              		.cfi_offset 5, -32
+ 2053              		.cfi_offset 6, -28
+ 2054              		.cfi_offset 7, -24
+ 2055              		.cfi_offset 8, -20
+ 2056              		.cfi_offset 9, -16
+ 2057              		.cfi_offset 10, -12
+ 2058              		.cfi_offset 11, -8
+ 2059              		.cfi_offset 14, -4
+ 2060 0004 8BB0     		sub	sp, sp, #44
+ 2061              	.LCFI33:
+ 2062              		.cfi_def_cfa_offset 80
+ 2063 0006 0546     		mov	r5, r0
+ 2064 0008 0C46     		mov	r4, r1
+ 2065 000a 1646     		mov	r6, r2
+ 2066 000c 9B46     		mov	fp, r3
+ 2067 000e DDF850A0 		ldr	r10, [sp, #80]
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 2068              		.loc 1 783 3 is_stmt 1 view .LVU720
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t tickstart = HAL_GetTick();
+ 2069              		.loc 1 784 3 view .LVU721
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count, data, dataremaining;
+ 2070              		.loc 1 785 3 view .LVU722
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t count, data, dataremaining;
+ 2071              		.loc 1 785 24 is_stmt 0 view .LVU723
+ 2072 0012 FFF7FEFF 		bl	HAL_GetTick
+ 2073              	.LVL185:
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+ 2074              		.loc 1 786 3 is_stmt 1 view .LVU724
+ARM GAS  /tmp/ccQEYyKb.s 			page 105
+
+
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint8_t *tempbuff = pData;
+ 2075              		.loc 1 787 3 view .LVU725
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2076              		.loc 1 788 3 view .LVU726
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2077              		.loc 1 790 3 view .LVU727
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2078              		.loc 1 790 5 is_stmt 0 view .LVU728
+ 2079 0016 002C     		cmp	r4, #0
+ 2080 0018 37D0     		beq	.L152
+ 2081 001a 8046     		mov	r8, r0
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2082              		.loc 1 796 3 is_stmt 1 view .LVU729
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2083              		.loc 1 796 9 is_stmt 0 view .LVU730
+ 2084 001c 95F83470 		ldrb	r7, [r5, #52]	@ zero_extendqisi2
+ 2085 0020 FFB2     		uxtb	r7, r7
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2086              		.loc 1 796 5 view .LVU731
+ 2087 0022 012F     		cmp	r7, #1
+ 2088 0024 40F0E180 		bne	.L135
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2089              		.loc 1 798 5 is_stmt 1 view .LVU732
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2090              		.loc 1 798 20 is_stmt 0 view .LVU733
+ 2091 0028 0023     		movs	r3, #0
+ 2092 002a AB63     		str	r3, [r5, #56]
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2093              		.loc 1 800 5 is_stmt 1 view .LVU734
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2094              		.loc 1 800 13 is_stmt 0 view .LVU735
+ 2095 002c 06EB0B03 		add	r3, r6, fp
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2096              		.loc 1 800 45 view .LVU736
+ 2097 0030 EA6D     		ldr	r2, [r5, #92]
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2098              		.loc 1 800 7 view .LVU737
+ 2099 0032 9342     		cmp	r3, r2
+ 2100 0034 2FD8     		bhi	.L153
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2101              		.loc 1 806 5 is_stmt 1 view .LVU738
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2102              		.loc 1 806 16 is_stmt 0 view .LVU739
+ 2103 0036 0323     		movs	r3, #3
+ 2104 0038 85F83430 		strb	r3, [r5, #52]
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2105              		.loc 1 809 5 is_stmt 1 view .LVU740
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2106              		.loc 1 809 8 is_stmt 0 view .LVU741
+ 2107 003c 2B68     		ldr	r3, [r5]
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2108              		.loc 1 809 26 view .LVU742
+ 2109 003e 0022     		movs	r2, #0
+ 2110 0040 DA62     		str	r2, [r3, #44]
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2111              		.loc 1 811 5 is_stmt 1 view .LVU743
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ARM GAS  /tmp/ccQEYyKb.s 			page 106
+
+
+ 2112              		.loc 1 811 19 is_stmt 0 view .LVU744
+ 2113 0042 6B6C     		ldr	r3, [r5, #68]
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2114              		.loc 1 811 7 view .LVU745
+ 2115 0044 012B     		cmp	r3, #1
+ 2116 0046 00D0     		beq	.L137
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2117              		.loc 1 813 7 is_stmt 1 view .LVU746
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2118              		.loc 1 813 11 is_stmt 0 view .LVU747
+ 2119 0048 7602     		lsls	r6, r6, #9
+ 2120              	.LVL186:
+ 2121              	.L137:
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+ 2122              		.loc 1 817 5 is_stmt 1 view .LVU748
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+ 2123              		.loc 1 817 26 is_stmt 0 view .LVU749
+ 2124 004a 4FF0FF33 		mov	r3, #-1
+ 2125 004e 0493     		str	r3, [sp, #16]
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 2126              		.loc 1 818 5 is_stmt 1 view .LVU750
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 2127              		.loc 1 818 43 is_stmt 0 view .LVU751
+ 2128 0050 4FEA4B23 		lsl	r3, fp, #9
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 2129              		.loc 1 818 26 view .LVU752
+ 2130 0054 0593     		str	r3, [sp, #20]
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+ 2131              		.loc 1 819 5 is_stmt 1 view .LVU753
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+ 2132              		.loc 1 819 26 is_stmt 0 view .LVU754
+ 2133 0056 9023     		movs	r3, #144
+ 2134 0058 0693     		str	r3, [sp, #24]
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 2135              		.loc 1 820 5 is_stmt 1 view .LVU755
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 2136              		.loc 1 820 26 is_stmt 0 view .LVU756
+ 2137 005a 0023     		movs	r3, #0
+ 2138 005c 0793     		str	r3, [sp, #28]
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+ 2139              		.loc 1 821 5 is_stmt 1 view .LVU757
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+ 2140              		.loc 1 821 26 is_stmt 0 view .LVU758
+ 2141 005e 0893     		str	r3, [sp, #32]
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 2142              		.loc 1 822 5 is_stmt 1 view .LVU759
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 2143              		.loc 1 822 26 is_stmt 0 view .LVU760
+ 2144 0060 0123     		movs	r3, #1
+ 2145 0062 0993     		str	r3, [sp, #36]
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2146              		.loc 1 823 5 is_stmt 1 view .LVU761
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2147              		.loc 1 823 11 is_stmt 0 view .LVU762
+ 2148 0064 04A9     		add	r1, sp, #16
+ 2149 0066 2868     		ldr	r0, [r5]
+ 2150              	.LVL187:
+ARM GAS  /tmp/ccQEYyKb.s 			page 107
+
+
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2151              		.loc 1 823 11 view .LVU763
+ 2152 0068 FFF7FEFF 		bl	SDMMC_ConfigData
+ 2153              	.LVL188:
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2154              		.loc 1 826 5 is_stmt 1 view .LVU764
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2155              		.loc 1 826 7 is_stmt 0 view .LVU765
+ 2156 006c BBF1010F 		cmp	fp, #1
+ 2157 0070 16D9     		bls	.L138
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2158              		.loc 1 828 7 is_stmt 1 view .LVU766
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2159              		.loc 1 828 20 is_stmt 0 view .LVU767
+ 2160 0072 2023     		movs	r3, #32
+ 2161 0074 2B63     		str	r3, [r5, #48]
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2162              		.loc 1 831 7 is_stmt 1 view .LVU768
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2163              		.loc 1 831 20 is_stmt 0 view .LVU769
+ 2164 0076 3146     		mov	r1, r6
+ 2165 0078 2868     		ldr	r0, [r5]
+ 2166 007a FFF7FEFF 		bl	SDMMC_CmdWriteMultiBlock
+ 2167              	.LVL189:
+ 2168 007e 0190     		str	r0, [sp, #4]
+ 2169              	.LVL190:
+ 2170              	.L139:
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2171              		.loc 1 840 5 is_stmt 1 view .LVU770
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2172              		.loc 1 840 7 is_stmt 0 view .LVU771
+ 2173 0080 019B     		ldr	r3, [sp, #4]
+ 2174 0082 ABB9     		cbnz	r3, .L154
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+ 2175              		.loc 1 851 5 is_stmt 1 view .LVU772
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+ 2176              		.loc 1 851 19 is_stmt 0 view .LVU773
+ 2177 0084 DDF81490 		ldr	r9, [sp, #20]
+ 2178              	.LVL191:
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2179              		.loc 1 852 5 is_stmt 1 view .LVU774
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2180              		.loc 1 852 10 is_stmt 0 view .LVU775
+ 2181 0088 40E0     		b	.L141
+ 2182              	.LVL192:
+ 2183              	.L152:
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2184              		.loc 1 792 5 is_stmt 1 view .LVU776
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2185              		.loc 1 792 20 is_stmt 0 view .LVU777
+ 2186 008a AB6B     		ldr	r3, [r5, #56]
+ 2187 008c 43F00063 		orr	r3, r3, #134217728
+ 2188 0090 AB63     		str	r3, [r5, #56]
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2189              		.loc 1 793 5 is_stmt 1 view .LVU778
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2190              		.loc 1 793 12 is_stmt 0 view .LVU779
+ARM GAS  /tmp/ccQEYyKb.s 			page 108
+
+
+ 2191 0092 0127     		movs	r7, #1
+ 2192 0094 AEE0     		b	.L134
+ 2193              	.L153:
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2194              		.loc 1 802 7 is_stmt 1 view .LVU780
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2195              		.loc 1 802 22 is_stmt 0 view .LVU781
+ 2196 0096 AB6B     		ldr	r3, [r5, #56]
+ 2197 0098 43F00073 		orr	r3, r3, #33554432
+ 2198 009c AB63     		str	r3, [r5, #56]
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2199              		.loc 1 803 7 is_stmt 1 view .LVU782
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2200              		.loc 1 803 14 is_stmt 0 view .LVU783
+ 2201 009e A9E0     		b	.L134
+ 2202              	.LVL193:
+ 2203              	.L138:
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2204              		.loc 1 835 7 is_stmt 1 view .LVU784
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2205              		.loc 1 835 20 is_stmt 0 view .LVU785
+ 2206 00a0 1023     		movs	r3, #16
+ 2207 00a2 2B63     		str	r3, [r5, #48]
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2208              		.loc 1 838 7 is_stmt 1 view .LVU786
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2209              		.loc 1 838 20 is_stmt 0 view .LVU787
+ 2210 00a4 3146     		mov	r1, r6
+ 2211 00a6 2868     		ldr	r0, [r5]
+ 2212 00a8 FFF7FEFF 		bl	SDMMC_CmdWriteSingleBlock
+ 2213              	.LVL194:
+ 2214 00ac 0190     		str	r0, [sp, #4]
+ 2215              	.LVL195:
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2216              		.loc 1 838 20 view .LVU788
+ 2217 00ae E7E7     		b	.L139
+ 2218              	.LVL196:
+ 2219              	.L154:
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+ 2220              		.loc 1 843 7 is_stmt 1 view .LVU789
+ 2221 00b0 2B68     		ldr	r3, [r5]
+ 2222              	.LVL197:
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+ 2223              		.loc 1 843 7 is_stmt 0 view .LVU790
+ 2224 00b2 524A     		ldr	r2, .L159
+ 2225 00b4 9A63     		str	r2, [r3, #56]
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2226              		.loc 1 844 7 is_stmt 1 view .LVU791
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2227              		.loc 1 844 22 is_stmt 0 view .LVU792
+ 2228 00b6 A86B     		ldr	r0, [r5, #56]
+ 2229 00b8 019B     		ldr	r3, [sp, #4]
+ 2230 00ba 1843     		orrs	r0, r0, r3
+ 2231 00bc A863     		str	r0, [r5, #56]
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 2232              		.loc 1 845 7 is_stmt 1 view .LVU793
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ARM GAS  /tmp/ccQEYyKb.s 			page 109
+
+
+ 2233              		.loc 1 845 18 is_stmt 0 view .LVU794
+ 2234 00be 0123     		movs	r3, #1
+ 2235 00c0 85F83430 		strb	r3, [r5, #52]
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2236              		.loc 1 846 7 is_stmt 1 view .LVU795
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2237              		.loc 1 846 20 is_stmt 0 view .LVU796
+ 2238 00c4 0023     		movs	r3, #0
+ 2239 00c6 2B63     		str	r3, [r5, #48]
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2240              		.loc 1 847 7 is_stmt 1 view .LVU797
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2241              		.loc 1 847 14 is_stmt 0 view .LVU798
+ 2242 00c8 94E0     		b	.L134
+ 2243              	.LVL198:
+ 2244              	.L144:
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2245              		.loc 1 859 11 is_stmt 1 discriminator 3 view .LVU799
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2246              		.loc 1 859 29 is_stmt 0 discriminator 3 view .LVU800
+ 2247 00ca 2378     		ldrb	r3, [r4]	@ zero_extendqisi2
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2248              		.loc 1 859 16 discriminator 3 view .LVU801
+ 2249 00cc 0393     		str	r3, [sp, #12]
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 2250              		.loc 1 860 11 is_stmt 1 discriminator 3 view .LVU802
+ 2251              	.LVL199:
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           data |= ((uint32_t)(*tempbuff) << 8U);
+ 2252              		.loc 1 861 11 discriminator 3 view .LVU803
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2253              		.loc 1 862 11 discriminator 3 view .LVU804
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2254              		.loc 1 862 31 is_stmt 0 discriminator 3 view .LVU805
+ 2255 00ce 6278     		ldrb	r2, [r4, #1]	@ zero_extendqisi2
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2256              		.loc 1 862 16 discriminator 3 view .LVU806
+ 2257 00d0 43EA0223 		orr	r3, r3, r2, lsl #8
+ 2258 00d4 0393     		str	r3, [sp, #12]
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 2259              		.loc 1 863 11 is_stmt 1 discriminator 3 view .LVU807
+ 2260              	.LVL200:
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           data |= ((uint32_t)(*tempbuff) << 16U);
+ 2261              		.loc 1 864 11 discriminator 3 view .LVU808
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2262              		.loc 1 865 11 discriminator 3 view .LVU809
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2263              		.loc 1 865 31 is_stmt 0 discriminator 3 view .LVU810
+ 2264 00d6 A278     		ldrb	r2, [r4, #2]	@ zero_extendqisi2
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2265              		.loc 1 865 16 discriminator 3 view .LVU811
+ 2266 00d8 43EA0243 		orr	r3, r3, r2, lsl #16
+ 2267 00dc 0393     		str	r3, [sp, #12]
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 2268              		.loc 1 866 11 is_stmt 1 discriminator 3 view .LVU812
+ 2269              	.LVL201:
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           data |= ((uint32_t)(*tempbuff) << 24U);
+ 2270              		.loc 1 867 11 discriminator 3 view .LVU813
+ARM GAS  /tmp/ccQEYyKb.s 			page 110
+
+
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2271              		.loc 1 868 11 discriminator 3 view .LVU814
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2272              		.loc 1 868 31 is_stmt 0 discriminator 3 view .LVU815
+ 2273 00de E278     		ldrb	r2, [r4, #3]	@ zero_extendqisi2
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           tempbuff++;
+ 2274              		.loc 1 868 16 discriminator 3 view .LVU816
+ 2275 00e0 43EA0263 		orr	r3, r3, r2, lsl #24
+ 2276 00e4 0393     		str	r3, [sp, #12]
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 2277              		.loc 1 869 11 is_stmt 1 discriminator 3 view .LVU817
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           dataremaining--;
+ 2278              		.loc 1 869 19 is_stmt 0 discriminator 3 view .LVU818
+ 2279 00e6 0434     		adds	r4, r4, #4
+ 2280              	.LVL202:
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+ 2281              		.loc 1 870 11 is_stmt 1 discriminator 3 view .LVU819
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+ 2282              		.loc 1 870 24 is_stmt 0 discriminator 3 view .LVU820
+ 2283 00e8 A9F10409 		sub	r9, r9, #4
+ 2284              	.LVL203:
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 2285              		.loc 1 871 11 is_stmt 1 discriminator 3 view .LVU821
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 2286              		.loc 1 871 17 is_stmt 0 discriminator 3 view .LVU822
+ 2287 00ec 03A9     		add	r1, sp, #12
+ 2288 00ee 2868     		ldr	r0, [r5]
+ 2289 00f0 FFF7FEFF 		bl	SDMMC_WriteFIFO
+ 2290              	.LVL204:
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 2291              		.loc 1 857 37 is_stmt 1 discriminator 3 view .LVU823
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 2292              		.loc 1 857 42 is_stmt 0 discriminator 3 view .LVU824
+ 2293 00f4 0136     		adds	r6, r6, #1
+ 2294              	.LVL205:
+ 2295              	.L143:
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 2296              		.loc 1 857 25 is_stmt 1 discriminator 1 view .LVU825
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 2297              		.loc 1 857 9 is_stmt 0 discriminator 1 view .LVU826
+ 2298 00f6 072E     		cmp	r6, #7
+ 2299 00f8 E7D9     		bls	.L144
+ 2300              	.LVL206:
+ 2301              	.L142:
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2302              		.loc 1 875 7 is_stmt 1 view .LVU827
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2303              		.loc 1 875 12 is_stmt 0 view .LVU828
+ 2304 00fa FFF7FEFF 		bl	HAL_GetTick
+ 2305              	.LVL207:
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2306              		.loc 1 875 25 view .LVU829
+ 2307 00fe A0EB0800 		sub	r0, r0, r8
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2308              		.loc 1 875 9 view .LVU830
+ 2309 0102 5045     		cmp	r0, r10
+ 2310 0104 0FD2     		bcs	.L145
+ARM GAS  /tmp/ccQEYyKb.s 			page 111
+
+
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2311              		.loc 1 875 50 discriminator 1 view .LVU831
+ 2312 0106 BAF1000F 		cmp	r10, #0
+ 2313 010a 0CD0     		beq	.L145
+ 2314              	.L141:
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2315              		.loc 1 852 10 is_stmt 1 view .LVU832
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2316              		.loc 1 852 12 is_stmt 0 view .LVU833
+ 2317 010c 2868     		ldr	r0, [r5]
+ 2318 010e 466B     		ldr	r6, [r0, #52]
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2319              		.loc 1 852 10 view .LVU834
+ 2320 0110 16F48D76 		ands	r6, r6, #282
+ 2321 0114 15D1     		bne	.L155
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2322              		.loc 1 854 7 is_stmt 1 view .LVU835
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2323              		.loc 1 854 10 is_stmt 0 view .LVU836
+ 2324 0116 436B     		ldr	r3, [r0, #52]
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2325              		.loc 1 854 9 view .LVU837
+ 2326 0118 13F4804F 		tst	r3, #16384
+ 2327 011c EDD0     		beq	.L142
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2328              		.loc 1 854 54 discriminator 1 view .LVU838
+ 2329 011e B9F1000F 		cmp	r9, #0
+ 2330 0122 EAD0     		beq	.L142
+ 2331 0124 E7E7     		b	.L143
+ 2332              	.L145:
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= errorstate;
+ 2333              		.loc 1 878 9 is_stmt 1 view .LVU839
+ 2334 0126 2B68     		ldr	r3, [r5]
+ 2335 0128 344A     		ldr	r2, .L159
+ 2336 012a 9A63     		str	r2, [r3, #56]
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 2337              		.loc 1 879 9 view .LVU840
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 2338              		.loc 1 879 24 is_stmt 0 view .LVU841
+ 2339 012c A86B     		ldr	r0, [r5, #56]
+ 2340 012e 019B     		ldr	r3, [sp, #4]
+ 2341 0130 1843     		orrs	r0, r0, r3
+ 2342 0132 A863     		str	r0, [r5, #56]
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 2343              		.loc 1 880 9 is_stmt 1 view .LVU842
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 2344              		.loc 1 880 20 is_stmt 0 view .LVU843
+ 2345 0134 0123     		movs	r3, #1
+ 2346 0136 85F83430 		strb	r3, [r5, #52]
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_TIMEOUT;
+ 2347              		.loc 1 881 9 is_stmt 1 view .LVU844
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_TIMEOUT;
+ 2348              		.loc 1 881 22 is_stmt 0 view .LVU845
+ 2349 013a 0023     		movs	r3, #0
+ 2350 013c 2B63     		str	r3, [r5, #48]
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 2351              		.loc 1 882 9 is_stmt 1 view .LVU846
+ARM GAS  /tmp/ccQEYyKb.s 			page 112
+
+
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 2352              		.loc 1 882 16 is_stmt 0 view .LVU847
+ 2353 013e 0327     		movs	r7, #3
+ 2354 0140 58E0     		b	.L134
+ 2355              	.L155:
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2356              		.loc 1 887 5 is_stmt 1 view .LVU848
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2357              		.loc 1 887 8 is_stmt 0 view .LVU849
+ 2358 0142 436B     		ldr	r3, [r0, #52]
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2359              		.loc 1 887 7 view .LVU850
+ 2360 0144 13F4807F 		tst	r3, #256
+ 2361 0148 05D0     		beq	.L147
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2362              		.loc 1 887 51 discriminator 1 view .LVU851
+ 2363 014a BBF1010F 		cmp	fp, #1
+ 2364 014e 02D9     		bls	.L147
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2365              		.loc 1 889 7 is_stmt 1 view .LVU852
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2366              		.loc 1 889 21 is_stmt 0 view .LVU853
+ 2367 0150 6B6C     		ldr	r3, [r5, #68]
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 2368              		.loc 1 889 9 view .LVU854
+ 2369 0152 032B     		cmp	r3, #3
+ 2370 0154 18D1     		bne	.L156
+ 2371              	.LVL208:
+ 2372              	.L147:
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2373              		.loc 1 906 5 is_stmt 1 view .LVU855
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2374              		.loc 1 906 8 is_stmt 0 view .LVU856
+ 2375 0156 2B68     		ldr	r3, [r5]
+ 2376 0158 5A6B     		ldr	r2, [r3, #52]
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2377              		.loc 1 906 7 view .LVU857
+ 2378 015a 12F0080F 		tst	r2, #8
+ 2379 015e 24D1     		bne	.L157
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2380              		.loc 1 915 10 is_stmt 1 view .LVU858
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2381              		.loc 1 915 13 is_stmt 0 view .LVU859
+ 2382 0160 5A6B     		ldr	r2, [r3, #52]
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2383              		.loc 1 915 12 view .LVU860
+ 2384 0162 12F0020F 		tst	r2, #2
+ 2385 0166 2CD1     		bne	.L158
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2386              		.loc 1 924 10 is_stmt 1 view .LVU861
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2387              		.loc 1 924 13 is_stmt 0 view .LVU862
+ 2388 0168 5A6B     		ldr	r2, [r3, #52]
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2389              		.loc 1 924 12 view .LVU863
+ 2390 016a 12F0100F 		tst	r2, #16
+ 2391 016e 34D0     		beq	.L150
+ARM GAS  /tmp/ccQEYyKb.s 			page 113
+
+
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ 2392              		.loc 1 927 7 is_stmt 1 view .LVU864
+ 2393 0170 224A     		ldr	r2, .L159
+ 2394 0172 9A63     		str	r2, [r3, #56]
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2395              		.loc 1 928 7 view .LVU865
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2396              		.loc 1 928 22 is_stmt 0 view .LVU866
+ 2397 0174 AB6B     		ldr	r3, [r5, #56]
+ 2398 0176 43F01003 		orr	r3, r3, #16
+ 2399 017a AB63     		str	r3, [r5, #56]
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 2400              		.loc 1 929 7 is_stmt 1 view .LVU867
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 2401              		.loc 1 929 18 is_stmt 0 view .LVU868
+ 2402 017c 0123     		movs	r3, #1
+ 2403 017e 85F83430 		strb	r3, [r5, #52]
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2404              		.loc 1 930 7 is_stmt 1 view .LVU869
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2405              		.loc 1 930 20 is_stmt 0 view .LVU870
+ 2406 0182 0023     		movs	r3, #0
+ 2407 0184 2B63     		str	r3, [r5, #48]
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2408              		.loc 1 931 7 is_stmt 1 view .LVU871
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2409              		.loc 1 931 14 is_stmt 0 view .LVU872
+ 2410 0186 35E0     		b	.L134
+ 2411              	.LVL209:
+ 2412              	.L156:
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ 2413              		.loc 1 892 9 is_stmt 1 view .LVU873
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ 2414              		.loc 1 892 22 is_stmt 0 view .LVU874
+ 2415 0188 FFF7FEFF 		bl	SDMMC_CmdStopTransfer
+ 2416              	.LVL210:
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 2417              		.loc 1 893 9 is_stmt 1 view .LVU875
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 2418              		.loc 1 893 11 is_stmt 0 view .LVU876
+ 2419 018c 0346     		mov	r3, r0
+ 2420 018e 0028     		cmp	r0, #0
+ 2421 0190 E1D0     		beq	.L147
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->ErrorCode |= errorstate;
+ 2422              		.loc 1 896 11 is_stmt 1 view .LVU877
+ 2423 0192 2A68     		ldr	r2, [r5]
+ 2424 0194 1949     		ldr	r1, .L159
+ 2425 0196 9163     		str	r1, [r2, #56]
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->State = HAL_SD_STATE_READY;
+ 2426              		.loc 1 897 11 view .LVU878
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->State = HAL_SD_STATE_READY;
+ 2427              		.loc 1 897 26 is_stmt 0 view .LVU879
+ 2428 0198 AA6B     		ldr	r2, [r5, #56]
+ 2429 019a 1343     		orrs	r3, r3, r2
+ 2430 019c AB63     		str	r3, [r5, #56]
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->Context = SD_CONTEXT_NONE;
+ 2431              		.loc 1 898 11 is_stmt 1 view .LVU880
+ARM GAS  /tmp/ccQEYyKb.s 			page 114
+
+
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           hsd->Context = SD_CONTEXT_NONE;
+ 2432              		.loc 1 898 22 is_stmt 0 view .LVU881
+ 2433 019e 0123     		movs	r3, #1
+ 2434 01a0 85F83430 		strb	r3, [r5, #52]
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           return HAL_ERROR;
+ 2435              		.loc 1 899 11 is_stmt 1 view .LVU882
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****           return HAL_ERROR;
+ 2436              		.loc 1 899 24 is_stmt 0 view .LVU883
+ 2437 01a4 0023     		movs	r3, #0
+ 2438 01a6 2B63     		str	r3, [r5, #48]
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 2439              		.loc 1 900 11 is_stmt 1 view .LVU884
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 2440              		.loc 1 900 18 is_stmt 0 view .LVU885
+ 2441 01a8 24E0     		b	.L134
+ 2442              	.LVL211:
+ 2443              	.L157:
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ 2444              		.loc 1 909 7 is_stmt 1 view .LVU886
+ 2445 01aa 144A     		ldr	r2, .L159
+ 2446 01ac 9A63     		str	r2, [r3, #56]
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2447              		.loc 1 910 7 view .LVU887
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2448              		.loc 1 910 22 is_stmt 0 view .LVU888
+ 2449 01ae AB6B     		ldr	r3, [r5, #56]
+ 2450 01b0 43F00803 		orr	r3, r3, #8
+ 2451 01b4 AB63     		str	r3, [r5, #56]
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 2452              		.loc 1 911 7 is_stmt 1 view .LVU889
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 2453              		.loc 1 911 18 is_stmt 0 view .LVU890
+ 2454 01b6 0123     		movs	r3, #1
+ 2455 01b8 85F83430 		strb	r3, [r5, #52]
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2456              		.loc 1 912 7 is_stmt 1 view .LVU891
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2457              		.loc 1 912 20 is_stmt 0 view .LVU892
+ 2458 01bc 0023     		movs	r3, #0
+ 2459 01be 2B63     		str	r3, [r5, #48]
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2460              		.loc 1 913 7 is_stmt 1 view .LVU893
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2461              		.loc 1 913 14 is_stmt 0 view .LVU894
+ 2462 01c0 18E0     		b	.L134
+ 2463              	.L158:
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ 2464              		.loc 1 918 7 is_stmt 1 view .LVU895
+ 2465 01c2 0E4A     		ldr	r2, .L159
+ 2466 01c4 9A63     		str	r2, [r3, #56]
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2467              		.loc 1 919 7 view .LVU896
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2468              		.loc 1 919 22 is_stmt 0 view .LVU897
+ 2469 01c6 AB6B     		ldr	r3, [r5, #56]
+ 2470 01c8 43F00203 		orr	r3, r3, #2
+ 2471 01cc AB63     		str	r3, [r5, #56]
+ARM GAS  /tmp/ccQEYyKb.s 			page 115
+
+
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 2472              		.loc 1 920 7 is_stmt 1 view .LVU898
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 2473              		.loc 1 920 18 is_stmt 0 view .LVU899
+ 2474 01ce 0123     		movs	r3, #1
+ 2475 01d0 85F83430 		strb	r3, [r5, #52]
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2476              		.loc 1 921 7 is_stmt 1 view .LVU900
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2477              		.loc 1 921 20 is_stmt 0 view .LVU901
+ 2478 01d4 0023     		movs	r3, #0
+ 2479 01d6 2B63     		str	r3, [r5, #48]
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2480              		.loc 1 922 7 is_stmt 1 view .LVU902
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2481              		.loc 1 922 14 is_stmt 0 view .LVU903
+ 2482 01d8 0CE0     		b	.L134
+ 2483              	.L150:
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2484              		.loc 1 936 5 is_stmt 1 view .LVU904
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2485              		.loc 1 939 5 view .LVU905
+ 2486 01da 40F23A52 		movw	r2, #1338
+ 2487 01de 9A63     		str	r2, [r3, #56]
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2488              		.loc 1 941 5 view .LVU906
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2489              		.loc 1 941 16 is_stmt 0 view .LVU907
+ 2490 01e0 0123     		movs	r3, #1
+ 2491 01e2 85F83430 		strb	r3, [r5, #52]
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2492              		.loc 1 943 5 is_stmt 1 view .LVU908
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2493              		.loc 1 943 12 is_stmt 0 view .LVU909
+ 2494 01e6 0027     		movs	r7, #0
+ 2495 01e8 04E0     		b	.L134
+ 2496              	.LVL212:
+ 2497              	.L135:
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2498              		.loc 1 947 5 is_stmt 1 view .LVU910
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2499              		.loc 1 947 20 is_stmt 0 view .LVU911
+ 2500 01ea AB6B     		ldr	r3, [r5, #56]
+ 2501 01ec 43F00053 		orr	r3, r3, #536870912
+ 2502 01f0 AB63     		str	r3, [r5, #56]
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2503              		.loc 1 948 5 is_stmt 1 view .LVU912
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2504              		.loc 1 948 12 is_stmt 0 view .LVU913
+ 2505 01f2 0127     		movs	r7, #1
+ 2506              	.LVL213:
+ 2507              	.L134:
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2508              		.loc 1 950 1 view .LVU914
+ 2509 01f4 3846     		mov	r0, r7
+ 2510 01f6 0BB0     		add	sp, sp, #44
+ 2511              	.LCFI34:
+ARM GAS  /tmp/ccQEYyKb.s 			page 116
+
+
+ 2512              		.cfi_def_cfa_offset 36
+ 2513              		@ sp needed
+ 2514 01f8 BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 2515              	.LVL214:
+ 2516              	.L160:
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2517              		.loc 1 950 1 view .LVU915
+ 2518              		.align	2
+ 2519              	.L159:
+ 2520 01fc FF054000 		.word	4195839
+ 2521              		.cfi_endproc
+ 2522              	.LFE147:
+ 2524              		.section	.text.HAL_SD_ReadBlocks_IT,"ax",%progbits
+ 2525              		.align	1
+ 2526              		.global	HAL_SD_ReadBlocks_IT
+ 2527              		.syntax unified
+ 2528              		.thumb
+ 2529              		.thumb_func
+ 2530              		.fpu fpv5-d16
+ 2532              	HAL_SD_ReadBlocks_IT:
+ 2533              	.LVL215:
+ 2534              	.LFB148:
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 2535              		.loc 1 966 1 is_stmt 1 view -0
+ 2536              		.cfi_startproc
+ 2537              		@ args = 0, pretend = 0, frame = 24
+ 2538              		@ frame_needed = 0, uses_anonymous_args = 0
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 2539              		.loc 1 966 1 is_stmt 0 view .LVU917
+ 2540 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 2541              	.LCFI35:
+ 2542              		.cfi_def_cfa_offset 20
+ 2543              		.cfi_offset 4, -20
+ 2544              		.cfi_offset 5, -16
+ 2545              		.cfi_offset 6, -12
+ 2546              		.cfi_offset 7, -8
+ 2547              		.cfi_offset 14, -4
+ 2548 0002 87B0     		sub	sp, sp, #28
+ 2549              	.LCFI36:
+ 2550              		.cfi_def_cfa_offset 48
+ 2551 0004 0446     		mov	r4, r0
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 2552              		.loc 1 967 3 is_stmt 1 view .LVU918
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+ 2553              		.loc 1 968 3 view .LVU919
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2554              		.loc 1 969 3 view .LVU920
+ 2555              	.LVL216:
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2556              		.loc 1 971 3 view .LVU921
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2557              		.loc 1 971 5 is_stmt 0 view .LVU922
+ 2558 0006 0029     		cmp	r1, #0
+ 2559 0008 45D0     		beq	.L171
+ 2560 000a 1646     		mov	r6, r2
+ 2561 000c 1F46     		mov	r7, r3
+ 2562 000e 0A46     		mov	r2, r1
+ARM GAS  /tmp/ccQEYyKb.s 			page 117
+
+
+ 2563              	.LVL217:
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2564              		.loc 1 977 3 is_stmt 1 view .LVU923
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2565              		.loc 1 977 9 is_stmt 0 view .LVU924
+ 2566 0010 90F83450 		ldrb	r5, [r0, #52]	@ zero_extendqisi2
+ 2567 0014 EDB2     		uxtb	r5, r5
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2568              		.loc 1 977 5 view .LVU925
+ 2569 0016 012D     		cmp	r5, #1
+ 2570 0018 4FD1     		bne	.L168
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2571              		.loc 1 979 5 is_stmt 1 view .LVU926
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2572              		.loc 1 979 20 is_stmt 0 view .LVU927
+ 2573 001a 0023     		movs	r3, #0
+ 2574              	.LVL218:
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2575              		.loc 1 979 20 view .LVU928
+ 2576 001c 8363     		str	r3, [r0, #56]
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2577              		.loc 1 981 5 is_stmt 1 view .LVU929
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2578              		.loc 1 981 13 is_stmt 0 view .LVU930
+ 2579 001e F319     		adds	r3, r6, r7
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2580              		.loc 1 981 45 view .LVU931
+ 2581 0020 C16D     		ldr	r1, [r0, #92]
+ 2582              	.LVL219:
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2583              		.loc 1 981 7 view .LVU932
+ 2584 0022 8B42     		cmp	r3, r1
+ 2585 0024 3DD8     		bhi	.L172
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2586              		.loc 1 987 5 is_stmt 1 view .LVU933
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2587              		.loc 1 987 16 is_stmt 0 view .LVU934
+ 2588 0026 0323     		movs	r3, #3
+ 2589 0028 80F83430 		strb	r3, [r0, #52]
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2590              		.loc 1 990 5 is_stmt 1 view .LVU935
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2591              		.loc 1 990 8 is_stmt 0 view .LVU936
+ 2592 002c 0368     		ldr	r3, [r0]
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2593              		.loc 1 990 26 view .LVU937
+ 2594 002e 0021     		movs	r1, #0
+ 2595 0030 D962     		str	r1, [r3, #44]
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+ 2596              		.loc 1 992 5 is_stmt 1 view .LVU938
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+ 2597              		.loc 1 992 21 is_stmt 0 view .LVU939
+ 2598 0032 8262     		str	r2, [r0, #40]
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2599              		.loc 1 993 5 is_stmt 1 view .LVU940
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2600              		.loc 1 993 33 is_stmt 0 view .LVU941
+ARM GAS  /tmp/ccQEYyKb.s 			page 118
+
+
+ 2601 0034 7A02     		lsls	r2, r7, #9
+ 2602              	.LVL220:
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2603              		.loc 1 993 21 view .LVU942
+ 2604 0036 C262     		str	r2, [r0, #44]
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2605              		.loc 1 995 5 is_stmt 1 view .LVU943
+ 2606 0038 0168     		ldr	r1, [r0]
+ 2607 003a C86B     		ldr	r0, [r1, #60]
+ 2608              	.LVL221:
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2609              		.loc 1 995 5 is_stmt 0 view .LVU944
+ 2610 003c 48F22A13 		movw	r3, #33066
+ 2611 0040 0343     		orrs	r3, r3, r0
+ 2612 0042 CB63     		str	r3, [r1, #60]
+ 2613              	.LVL222:
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2614              		.loc 1 997 5 is_stmt 1 view .LVU945
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2615              		.loc 1 997 19 is_stmt 0 view .LVU946
+ 2616 0044 636C     		ldr	r3, [r4, #68]
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2617              		.loc 1 997 7 view .LVU947
+ 2618 0046 012B     		cmp	r3, #1
+ 2619 0048 00D0     		beq	.L165
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2620              		.loc 1 999 7 is_stmt 1 view .LVU948
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2621              		.loc 1 999 11 is_stmt 0 view .LVU949
+ 2622 004a 7602     		lsls	r6, r6, #9
+ 2623              	.LVL223:
+ 2624              	.L165:
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+ 2625              		.loc 1 1003 5 is_stmt 1 view .LVU950
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+ 2626              		.loc 1 1003 26 is_stmt 0 view .LVU951
+ 2627 004c 4FF0FF33 		mov	r3, #-1
+ 2628 0050 0093     		str	r3, [sp]
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 2629              		.loc 1 1004 5 is_stmt 1 view .LVU952
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 2630              		.loc 1 1004 26 is_stmt 0 view .LVU953
+ 2631 0052 0192     		str	r2, [sp, #4]
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 2632              		.loc 1 1005 5 is_stmt 1 view .LVU954
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 2633              		.loc 1 1005 26 is_stmt 0 view .LVU955
+ 2634 0054 9023     		movs	r3, #144
+ 2635 0056 0293     		str	r3, [sp, #8]
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 2636              		.loc 1 1006 5 is_stmt 1 view .LVU956
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 2637              		.loc 1 1006 26 is_stmt 0 view .LVU957
+ 2638 0058 0223     		movs	r3, #2
+ 2639 005a 0393     		str	r3, [sp, #12]
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+ 2640              		.loc 1 1007 5 is_stmt 1 view .LVU958
+ARM GAS  /tmp/ccQEYyKb.s 			page 119
+
+
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+ 2641              		.loc 1 1007 26 is_stmt 0 view .LVU959
+ 2642 005c 0023     		movs	r3, #0
+ 2643 005e 0493     		str	r3, [sp, #16]
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 2644              		.loc 1 1008 5 is_stmt 1 view .LVU960
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 2645              		.loc 1 1008 26 is_stmt 0 view .LVU961
+ 2646 0060 0123     		movs	r3, #1
+ 2647 0062 0593     		str	r3, [sp, #20]
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2648              		.loc 1 1009 5 is_stmt 1 view .LVU962
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2649              		.loc 1 1009 11 is_stmt 0 view .LVU963
+ 2650 0064 6946     		mov	r1, sp
+ 2651 0066 2068     		ldr	r0, [r4]
+ 2652 0068 FFF7FEFF 		bl	SDMMC_ConfigData
+ 2653              	.LVL224:
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2654              		.loc 1 1012 5 is_stmt 1 view .LVU964
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2655              		.loc 1 1012 7 is_stmt 0 view .LVU965
+ 2656 006c 012F     		cmp	r7, #1
+ 2657 006e 1DD9     		bls	.L166
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2658              		.loc 1 1014 7 is_stmt 1 view .LVU966
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2659              		.loc 1 1014 20 is_stmt 0 view .LVU967
+ 2660 0070 0A23     		movs	r3, #10
+ 2661 0072 2363     		str	r3, [r4, #48]
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2662              		.loc 1 1017 7 is_stmt 1 view .LVU968
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2663              		.loc 1 1017 20 is_stmt 0 view .LVU969
+ 2664 0074 3146     		mov	r1, r6
+ 2665 0076 2068     		ldr	r0, [r4]
+ 2666 0078 FFF7FEFF 		bl	SDMMC_CmdReadMultiBlock
+ 2667              	.LVL225:
+ 2668              	.L167:
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2669              		.loc 1 1026 5 is_stmt 1 view .LVU970
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2670              		.loc 1 1026 7 is_stmt 0 view .LVU971
+ 2671 007c 08B3     		cbz	r0, .L169
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+ 2672              		.loc 1 1029 7 is_stmt 1 view .LVU972
+ 2673 007e 2368     		ldr	r3, [r4]
+ 2674 0080 114A     		ldr	r2, .L173
+ 2675 0082 9A63     		str	r2, [r3, #56]
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2676              		.loc 1 1030 7 view .LVU973
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2677              		.loc 1 1030 22 is_stmt 0 view .LVU974
+ 2678 0084 A36B     		ldr	r3, [r4, #56]
+ 2679 0086 1843     		orrs	r0, r0, r3
+ 2680              	.LVL226:
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ARM GAS  /tmp/ccQEYyKb.s 			page 120
+
+
+ 2681              		.loc 1 1030 22 view .LVU975
+ 2682 0088 A063     		str	r0, [r4, #56]
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 2683              		.loc 1 1031 7 is_stmt 1 view .LVU976
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 2684              		.loc 1 1031 18 is_stmt 0 view .LVU977
+ 2685 008a 0123     		movs	r3, #1
+ 2686 008c 84F83430 		strb	r3, [r4, #52]
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2687              		.loc 1 1032 7 is_stmt 1 view .LVU978
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2688              		.loc 1 1032 20 is_stmt 0 view .LVU979
+ 2689 0090 0023     		movs	r3, #0
+ 2690 0092 2363     		str	r3, [r4, #48]
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2691              		.loc 1 1033 7 is_stmt 1 view .LVU980
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2692              		.loc 1 1033 14 is_stmt 0 view .LVU981
+ 2693 0094 12E0     		b	.L163
+ 2694              	.LVL227:
+ 2695              	.L171:
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2696              		.loc 1 973 5 is_stmt 1 view .LVU982
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2697              		.loc 1 973 20 is_stmt 0 view .LVU983
+ 2698 0096 836B     		ldr	r3, [r0, #56]
+ 2699              	.LVL228:
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2700              		.loc 1 973 20 view .LVU984
+ 2701 0098 43F00063 		orr	r3, r3, #134217728
+ 2702 009c 8363     		str	r3, [r0, #56]
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2703              		.loc 1 974 5 is_stmt 1 view .LVU985
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2704              		.loc 1 974 12 is_stmt 0 view .LVU986
+ 2705 009e 0125     		movs	r5, #1
+ 2706 00a0 0CE0     		b	.L163
+ 2707              	.LVL229:
+ 2708              	.L172:
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2709              		.loc 1 983 7 is_stmt 1 view .LVU987
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2710              		.loc 1 983 22 is_stmt 0 view .LVU988
+ 2711 00a2 836B     		ldr	r3, [r0, #56]
+ 2712 00a4 43F00073 		orr	r3, r3, #33554432
+ 2713 00a8 8363     		str	r3, [r0, #56]
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2714              		.loc 1 984 7 is_stmt 1 view .LVU989
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2715              		.loc 1 984 14 is_stmt 0 view .LVU990
+ 2716 00aa 07E0     		b	.L163
+ 2717              	.LVL230:
+ 2718              	.L166:
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2719              		.loc 1 1021 7 is_stmt 1 view .LVU991
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2720              		.loc 1 1021 20 is_stmt 0 view .LVU992
+ARM GAS  /tmp/ccQEYyKb.s 			page 121
+
+
+ 2721 00ac 0923     		movs	r3, #9
+ 2722 00ae 2363     		str	r3, [r4, #48]
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2723              		.loc 1 1024 7 is_stmt 1 view .LVU993
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2724              		.loc 1 1024 20 is_stmt 0 view .LVU994
+ 2725 00b0 3146     		mov	r1, r6
+ 2726 00b2 2068     		ldr	r0, [r4]
+ 2727 00b4 FFF7FEFF 		bl	SDMMC_CmdReadSingleBlock
+ 2728              	.LVL231:
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2729              		.loc 1 1024 20 view .LVU995
+ 2730 00b8 E0E7     		b	.L167
+ 2731              	.LVL232:
+ 2732              	.L168:
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2733              		.loc 1 1040 12 view .LVU996
+ 2734 00ba 0225     		movs	r5, #2
+ 2735              	.LVL233:
+ 2736              	.L163:
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2737              		.loc 1 1042 1 view .LVU997
+ 2738 00bc 2846     		mov	r0, r5
+ 2739 00be 07B0     		add	sp, sp, #28
+ 2740              	.LCFI37:
+ 2741              		.cfi_remember_state
+ 2742              		.cfi_def_cfa_offset 20
+ 2743              		@ sp needed
+ 2744 00c0 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 2745              	.LVL234:
+ 2746              	.L169:
+ 2747              	.LCFI38:
+ 2748              		.cfi_restore_state
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2749              		.loc 1 1036 12 view .LVU998
+ 2750 00c2 0025     		movs	r5, #0
+ 2751 00c4 FAE7     		b	.L163
+ 2752              	.L174:
+ 2753 00c6 00BF     		.align	2
+ 2754              	.L173:
+ 2755 00c8 FF054000 		.word	4195839
+ 2756              		.cfi_endproc
+ 2757              	.LFE148:
+ 2759              		.section	.text.HAL_SD_WriteBlocks_IT,"ax",%progbits
+ 2760              		.align	1
+ 2761              		.global	HAL_SD_WriteBlocks_IT
+ 2762              		.syntax unified
+ 2763              		.thumb
+ 2764              		.thumb_func
+ 2765              		.fpu fpv5-d16
+ 2767              	HAL_SD_WriteBlocks_IT:
+ 2768              	.LVL235:
+ 2769              	.LFB149:
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 2770              		.loc 1 1058 1 is_stmt 1 view -0
+ 2771              		.cfi_startproc
+ 2772              		@ args = 0, pretend = 0, frame = 24
+ARM GAS  /tmp/ccQEYyKb.s 			page 122
+
+
+ 2773              		@ frame_needed = 0, uses_anonymous_args = 0
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 2774              		.loc 1 1058 1 is_stmt 0 view .LVU1000
+ 2775 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 2776              	.LCFI39:
+ 2777              		.cfi_def_cfa_offset 20
+ 2778              		.cfi_offset 4, -20
+ 2779              		.cfi_offset 5, -16
+ 2780              		.cfi_offset 6, -12
+ 2781              		.cfi_offset 7, -8
+ 2782              		.cfi_offset 14, -4
+ 2783 0002 87B0     		sub	sp, sp, #28
+ 2784              	.LCFI40:
+ 2785              		.cfi_def_cfa_offset 48
+ 2786 0004 0446     		mov	r4, r0
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 2787              		.loc 1 1059 3 is_stmt 1 view .LVU1001
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+ 2788              		.loc 1 1060 3 view .LVU1002
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2789              		.loc 1 1061 3 view .LVU1003
+ 2790              	.LVL236:
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2791              		.loc 1 1063 3 view .LVU1004
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2792              		.loc 1 1063 5 is_stmt 0 view .LVU1005
+ 2793 0006 0029     		cmp	r1, #0
+ 2794 0008 33D0     		beq	.L185
+ 2795 000a 0846     		mov	r0, r1
+ 2796              	.LVL237:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2797              		.loc 1 1069 3 is_stmt 1 view .LVU1006
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2798              		.loc 1 1069 9 is_stmt 0 view .LVU1007
+ 2799 000c 94F83450 		ldrb	r5, [r4, #52]	@ zero_extendqisi2
+ 2800 0010 EDB2     		uxtb	r5, r5
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 2801              		.loc 1 1069 5 view .LVU1008
+ 2802 0012 012D     		cmp	r5, #1
+ 2803 0014 4FD1     		bne	.L183
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2804              		.loc 1 1071 5 is_stmt 1 view .LVU1009
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2805              		.loc 1 1071 20 is_stmt 0 view .LVU1010
+ 2806 0016 0021     		movs	r1, #0
+ 2807              	.LVL238:
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2808              		.loc 1 1071 20 view .LVU1011
+ 2809 0018 A163     		str	r1, [r4, #56]
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2810              		.loc 1 1073 5 is_stmt 1 view .LVU1012
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2811              		.loc 1 1073 13 is_stmt 0 view .LVU1013
+ 2812 001a D118     		adds	r1, r2, r3
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2813              		.loc 1 1073 45 view .LVU1014
+ 2814 001c E66D     		ldr	r6, [r4, #92]
+ARM GAS  /tmp/ccQEYyKb.s 			page 123
+
+
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2815              		.loc 1 1073 7 view .LVU1015
+ 2816 001e B142     		cmp	r1, r6
+ 2817 0020 2DD8     		bhi	.L186
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2818              		.loc 1 1079 5 is_stmt 1 view .LVU1016
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2819              		.loc 1 1079 16 is_stmt 0 view .LVU1017
+ 2820 0022 0321     		movs	r1, #3
+ 2821 0024 84F83410 		strb	r1, [r4, #52]
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2822              		.loc 1 1082 5 is_stmt 1 view .LVU1018
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2823              		.loc 1 1082 8 is_stmt 0 view .LVU1019
+ 2824 0028 2168     		ldr	r1, [r4]
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2825              		.loc 1 1082 26 view .LVU1020
+ 2826 002a 0026     		movs	r6, #0
+ 2827 002c CE62     		str	r6, [r1, #44]
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+ 2828              		.loc 1 1084 5 is_stmt 1 view .LVU1021
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+ 2829              		.loc 1 1084 21 is_stmt 0 view .LVU1022
+ 2830 002e 2062     		str	r0, [r4, #32]
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2831              		.loc 1 1085 5 is_stmt 1 view .LVU1023
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2832              		.loc 1 1085 33 is_stmt 0 view .LVU1024
+ 2833 0030 5E02     		lsls	r6, r3, #9
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2834              		.loc 1 1085 21 view .LVU1025
+ 2835 0032 6662     		str	r6, [r4, #36]
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2836              		.loc 1 1088 5 is_stmt 1 view .LVU1026
+ 2837 0034 2068     		ldr	r0, [r4]
+ 2838              	.LVL239:
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2839              		.loc 1 1088 5 is_stmt 0 view .LVU1027
+ 2840 0036 C76B     		ldr	r7, [r0, #60]
+ 2841 0038 44F21A11 		movw	r1, #16666
+ 2842 003c 3943     		orrs	r1, r1, r7
+ 2843 003e C163     		str	r1, [r0, #60]
+ 2844              	.LVL240:
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2845              		.loc 1 1090 5 is_stmt 1 view .LVU1028
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2846              		.loc 1 1090 19 is_stmt 0 view .LVU1029
+ 2847 0040 616C     		ldr	r1, [r4, #68]
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2848              		.loc 1 1090 7 view .LVU1030
+ 2849 0042 0129     		cmp	r1, #1
+ 2850 0044 00D0     		beq	.L179
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2851              		.loc 1 1092 7 is_stmt 1 view .LVU1031
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2852              		.loc 1 1092 11 is_stmt 0 view .LVU1032
+ 2853 0046 5202     		lsls	r2, r2, #9
+ARM GAS  /tmp/ccQEYyKb.s 			page 124
+
+
+ 2854              	.LVL241:
+ 2855              	.L179:
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2856              		.loc 1 1096 5 is_stmt 1 view .LVU1033
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2857              		.loc 1 1096 7 is_stmt 0 view .LVU1034
+ 2858 0048 012B     		cmp	r3, #1
+ 2859 004a 1DD9     		bls	.L180
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2860              		.loc 1 1098 7 is_stmt 1 view .LVU1035
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2861              		.loc 1 1098 20 is_stmt 0 view .LVU1036
+ 2862 004c 2823     		movs	r3, #40
+ 2863              	.LVL242:
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2864              		.loc 1 1098 20 view .LVU1037
+ 2865 004e 2363     		str	r3, [r4, #48]
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2866              		.loc 1 1101 7 is_stmt 1 view .LVU1038
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2867              		.loc 1 1101 20 is_stmt 0 view .LVU1039
+ 2868 0050 1146     		mov	r1, r2
+ 2869 0052 2068     		ldr	r0, [r4]
+ 2870 0054 FFF7FEFF 		bl	SDMMC_CmdWriteMultiBlock
+ 2871              	.LVL243:
+ 2872              	.L181:
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2873              		.loc 1 1110 5 is_stmt 1 view .LVU1040
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 2874              		.loc 1 1110 7 is_stmt 0 view .LVU1041
+ 2875 0058 E8B1     		cbz	r0, .L182
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+ 2876              		.loc 1 1113 7 is_stmt 1 view .LVU1042
+ 2877 005a 2368     		ldr	r3, [r4]
+ 2878 005c 184A     		ldr	r2, .L187
+ 2879 005e 9A63     		str	r2, [r3, #56]
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2880              		.loc 1 1114 7 view .LVU1043
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2881              		.loc 1 1114 22 is_stmt 0 view .LVU1044
+ 2882 0060 A36B     		ldr	r3, [r4, #56]
+ 2883 0062 1843     		orrs	r0, r0, r3
+ 2884              	.LVL244:
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 2885              		.loc 1 1114 22 view .LVU1045
+ 2886 0064 A063     		str	r0, [r4, #56]
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 2887              		.loc 1 1115 7 is_stmt 1 view .LVU1046
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 2888              		.loc 1 1115 18 is_stmt 0 view .LVU1047
+ 2889 0066 0123     		movs	r3, #1
+ 2890 0068 84F83430 		strb	r3, [r4, #52]
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2891              		.loc 1 1116 7 is_stmt 1 view .LVU1048
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2892              		.loc 1 1116 20 is_stmt 0 view .LVU1049
+ 2893 006c 0023     		movs	r3, #0
+ARM GAS  /tmp/ccQEYyKb.s 			page 125
+
+
+ 2894 006e 2363     		str	r3, [r4, #48]
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2895              		.loc 1 1117 7 is_stmt 1 view .LVU1050
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2896              		.loc 1 1117 14 is_stmt 0 view .LVU1051
+ 2897 0070 22E0     		b	.L177
+ 2898              	.LVL245:
+ 2899              	.L185:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2900              		.loc 1 1065 5 is_stmt 1 view .LVU1052
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2901              		.loc 1 1065 20 is_stmt 0 view .LVU1053
+ 2902 0072 836B     		ldr	r3, [r0, #56]
+ 2903              	.LVL246:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 2904              		.loc 1 1065 20 view .LVU1054
+ 2905 0074 43F00063 		orr	r3, r3, #134217728
+ 2906 0078 8363     		str	r3, [r0, #56]
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2907              		.loc 1 1066 5 is_stmt 1 view .LVU1055
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2908              		.loc 1 1066 12 is_stmt 0 view .LVU1056
+ 2909 007a 0125     		movs	r5, #1
+ 2910 007c 1CE0     		b	.L177
+ 2911              	.LVL247:
+ 2912              	.L186:
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2913              		.loc 1 1075 7 is_stmt 1 view .LVU1057
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2914              		.loc 1 1075 22 is_stmt 0 view .LVU1058
+ 2915 007e A36B     		ldr	r3, [r4, #56]
+ 2916              	.LVL248:
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 2917              		.loc 1 1075 22 view .LVU1059
+ 2918 0080 43F00073 		orr	r3, r3, #33554432
+ 2919 0084 A363     		str	r3, [r4, #56]
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2920              		.loc 1 1076 7 is_stmt 1 view .LVU1060
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2921              		.loc 1 1076 14 is_stmt 0 view .LVU1061
+ 2922 0086 17E0     		b	.L177
+ 2923              	.LVL249:
+ 2924              	.L180:
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2925              		.loc 1 1105 7 is_stmt 1 view .LVU1062
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2926              		.loc 1 1105 20 is_stmt 0 view .LVU1063
+ 2927 0088 1823     		movs	r3, #24
+ 2928              	.LVL250:
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2929              		.loc 1 1105 20 view .LVU1064
+ 2930 008a 2363     		str	r3, [r4, #48]
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2931              		.loc 1 1108 7 is_stmt 1 view .LVU1065
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2932              		.loc 1 1108 20 is_stmt 0 view .LVU1066
+ 2933 008c 1146     		mov	r1, r2
+ARM GAS  /tmp/ccQEYyKb.s 			page 126
+
+
+ 2934 008e 2068     		ldr	r0, [r4]
+ 2935 0090 FFF7FEFF 		bl	SDMMC_CmdWriteSingleBlock
+ 2936              	.LVL251:
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 2937              		.loc 1 1108 20 view .LVU1067
+ 2938 0094 E0E7     		b	.L181
+ 2939              	.L182:
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+ 2940              		.loc 1 1121 5 is_stmt 1 view .LVU1068
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+ 2941              		.loc 1 1121 26 is_stmt 0 view .LVU1069
+ 2942 0096 4FF0FF33 		mov	r3, #-1
+ 2943 009a 0093     		str	r3, [sp]
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 2944              		.loc 1 1122 5 is_stmt 1 view .LVU1070
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 2945              		.loc 1 1122 26 is_stmt 0 view .LVU1071
+ 2946 009c 0196     		str	r6, [sp, #4]
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+ 2947              		.loc 1 1123 5 is_stmt 1 view .LVU1072
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+ 2948              		.loc 1 1123 26 is_stmt 0 view .LVU1073
+ 2949 009e 9023     		movs	r3, #144
+ 2950 00a0 0293     		str	r3, [sp, #8]
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 2951              		.loc 1 1124 5 is_stmt 1 view .LVU1074
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 2952              		.loc 1 1124 26 is_stmt 0 view .LVU1075
+ 2953 00a2 0025     		movs	r5, #0
+ 2954 00a4 0395     		str	r5, [sp, #12]
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+ 2955              		.loc 1 1125 5 is_stmt 1 view .LVU1076
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     config.DPSM          = SDMMC_DPSM_ENABLE;
+ 2956              		.loc 1 1125 26 is_stmt 0 view .LVU1077
+ 2957 00a6 0495     		str	r5, [sp, #16]
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 2958              		.loc 1 1126 5 is_stmt 1 view .LVU1078
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 2959              		.loc 1 1126 26 is_stmt 0 view .LVU1079
+ 2960 00a8 0123     		movs	r3, #1
+ 2961 00aa 0593     		str	r3, [sp, #20]
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2962              		.loc 1 1127 5 is_stmt 1 view .LVU1080
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2963              		.loc 1 1127 11 is_stmt 0 view .LVU1081
+ 2964 00ac 6946     		mov	r1, sp
+ 2965 00ae 2068     		ldr	r0, [r4]
+ 2966              	.LVL252:
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2967              		.loc 1 1127 11 view .LVU1082
+ 2968 00b0 FFF7FEFF 		bl	SDMMC_ConfigData
+ 2969              	.LVL253:
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2970              		.loc 1 1129 5 is_stmt 1 view .LVU1083
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2971              		.loc 1 1129 12 is_stmt 0 view .LVU1084
+ 2972 00b4 00E0     		b	.L177
+ARM GAS  /tmp/ccQEYyKb.s 			page 127
+
+
+ 2973              	.LVL254:
+ 2974              	.L183:
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 2975              		.loc 1 1133 12 view .LVU1085
+ 2976 00b6 0225     		movs	r5, #2
+ 2977              	.LVL255:
+ 2978              	.L177:
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2979              		.loc 1 1135 1 view .LVU1086
+ 2980 00b8 2846     		mov	r0, r5
+ 2981 00ba 07B0     		add	sp, sp, #28
+ 2982              	.LCFI41:
+ 2983              		.cfi_def_cfa_offset 20
+ 2984              		@ sp needed
+ 2985 00bc F0BD     		pop	{r4, r5, r6, r7, pc}
+ 2986              	.LVL256:
+ 2987              	.L188:
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 2988              		.loc 1 1135 1 view .LVU1087
+ 2989 00be 00BF     		.align	2
+ 2990              	.L187:
+ 2991 00c0 FF054000 		.word	4195839
+ 2992              		.cfi_endproc
+ 2993              	.LFE149:
+ 2995              		.section	.text.HAL_SD_ReadBlocks_DMA,"ax",%progbits
+ 2996              		.align	1
+ 2997              		.global	HAL_SD_ReadBlocks_DMA
+ 2998              		.syntax unified
+ 2999              		.thumb
+ 3000              		.thumb_func
+ 3001              		.fpu fpv5-d16
+ 3003              	HAL_SD_ReadBlocks_DMA:
+ 3004              	.LVL257:
+ 3005              	.LFB150:
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 3006              		.loc 1 1151 1 is_stmt 1 view -0
+ 3007              		.cfi_startproc
+ 3008              		@ args = 0, pretend = 0, frame = 24
+ 3009              		@ frame_needed = 0, uses_anonymous_args = 0
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 3010              		.loc 1 1151 1 is_stmt 0 view .LVU1089
+ 3011 0000 2DE9F043 		push	{r4, r5, r6, r7, r8, r9, lr}
+ 3012              	.LCFI42:
+ 3013              		.cfi_def_cfa_offset 28
+ 3014              		.cfi_offset 4, -28
+ 3015              		.cfi_offset 5, -24
+ 3016              		.cfi_offset 6, -20
+ 3017              		.cfi_offset 7, -16
+ 3018              		.cfi_offset 8, -12
+ 3019              		.cfi_offset 9, -8
+ 3020              		.cfi_offset 14, -4
+ 3021 0004 87B0     		sub	sp, sp, #28
+ 3022              	.LCFI43:
+ 3023              		.cfi_def_cfa_offset 56
+ 3024 0006 0446     		mov	r4, r0
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 3025              		.loc 1 1152 3 is_stmt 1 view .LVU1090
+ARM GAS  /tmp/ccQEYyKb.s 			page 128
+
+
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+ 3026              		.loc 1 1153 3 view .LVU1091
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3027              		.loc 1 1154 3 view .LVU1092
+ 3028              	.LVL258:
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3029              		.loc 1 1156 3 view .LVU1093
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3030              		.loc 1 1156 5 is_stmt 0 view .LVU1094
+ 3031 0008 91B1     		cbz	r1, .L200
+ 3032 000a 1646     		mov	r6, r2
+ 3033 000c 1F46     		mov	r7, r3
+ 3034 000e 0A46     		mov	r2, r1
+ 3035              	.LVL259:
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3036              		.loc 1 1162 3 is_stmt 1 view .LVU1095
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3037              		.loc 1 1162 9 is_stmt 0 view .LVU1096
+ 3038 0010 90F83450 		ldrb	r5, [r0, #52]	@ zero_extendqisi2
+ 3039 0014 EDB2     		uxtb	r5, r5
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3040              		.loc 1 1162 5 view .LVU1097
+ 3041 0016 012D     		cmp	r5, #1
+ 3042 0018 7FD1     		bne	.L197
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3043              		.loc 1 1164 5 is_stmt 1 view .LVU1098
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3044              		.loc 1 1164 20 is_stmt 0 view .LVU1099
+ 3045 001a 0023     		movs	r3, #0
+ 3046              	.LVL260:
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3047              		.loc 1 1164 20 view .LVU1100
+ 3048 001c 8363     		str	r3, [r0, #56]
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3049              		.loc 1 1166 5 is_stmt 1 view .LVU1101
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3050              		.loc 1 1166 13 is_stmt 0 view .LVU1102
+ 3051 001e F019     		adds	r0, r6, r7
+ 3052              	.LVL261:
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3053              		.loc 1 1166 45 view .LVU1103
+ 3054 0020 E36D     		ldr	r3, [r4, #92]
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3055              		.loc 1 1166 7 view .LVU1104
+ 3056 0022 9842     		cmp	r0, r3
+ 3057 0024 0AD9     		bls	.L192
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3058              		.loc 1 1168 7 is_stmt 1 view .LVU1105
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3059              		.loc 1 1168 22 is_stmt 0 view .LVU1106
+ 3060 0026 A36B     		ldr	r3, [r4, #56]
+ 3061 0028 43F00073 		orr	r3, r3, #33554432
+ 3062 002c A363     		str	r3, [r4, #56]
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3063              		.loc 1 1169 7 is_stmt 1 view .LVU1107
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3064              		.loc 1 1169 14 is_stmt 0 view .LVU1108
+ARM GAS  /tmp/ccQEYyKb.s 			page 129
+
+
+ 3065 002e 75E0     		b	.L191
+ 3066              	.LVL262:
+ 3067              	.L200:
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 3068              		.loc 1 1158 5 is_stmt 1 view .LVU1109
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 3069              		.loc 1 1158 20 is_stmt 0 view .LVU1110
+ 3070 0030 836B     		ldr	r3, [r0, #56]
+ 3071              	.LVL263:
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 3072              		.loc 1 1158 20 view .LVU1111
+ 3073 0032 43F00063 		orr	r3, r3, #134217728
+ 3074 0036 8363     		str	r3, [r0, #56]
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 3075              		.loc 1 1159 5 is_stmt 1 view .LVU1112
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 3076              		.loc 1 1159 12 is_stmt 0 view .LVU1113
+ 3077 0038 0125     		movs	r5, #1
+ 3078 003a 6FE0     		b	.L191
+ 3079              	.LVL264:
+ 3080              	.L192:
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3081              		.loc 1 1172 5 is_stmt 1 view .LVU1114
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3082              		.loc 1 1172 16 is_stmt 0 view .LVU1115
+ 3083 003c 0323     		movs	r3, #3
+ 3084 003e 84F83430 		strb	r3, [r4, #52]
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3085              		.loc 1 1175 5 is_stmt 1 view .LVU1116
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3086              		.loc 1 1175 8 is_stmt 0 view .LVU1117
+ 3087 0042 2168     		ldr	r1, [r4]
+ 3088              	.LVL265:
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3089              		.loc 1 1175 26 view .LVU1118
+ 3090 0044 0023     		movs	r3, #0
+ 3091 0046 CB62     		str	r3, [r1, #44]
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3092              		.loc 1 1177 5 is_stmt 1 view .LVU1119
+ 3093 0048 2068     		ldr	r0, [r4]
+ 3094 004a C16B     		ldr	r1, [r0, #60]
+ 3095 004c 41F49571 		orr	r1, r1, #298
+ 3096 0050 C163     		str	r1, [r0, #60]
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3097              		.loc 1 1180 5 view .LVU1120
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3098              		.loc 1 1180 8 is_stmt 0 view .LVU1121
+ 3099 0052 216C     		ldr	r1, [r4, #64]
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3100              		.loc 1 1180 35 view .LVU1122
+ 3101 0054 3448     		ldr	r0, .L202
+ 3102 0056 C863     		str	r0, [r1, #60]
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3103              		.loc 1 1183 5 is_stmt 1 view .LVU1123
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3104              		.loc 1 1183 8 is_stmt 0 view .LVU1124
+ 3105 0058 216C     		ldr	r1, [r4, #64]
+ARM GAS  /tmp/ccQEYyKb.s 			page 130
+
+
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3106              		.loc 1 1183 36 view .LVU1125
+ 3107 005a 3448     		ldr	r0, .L202+4
+ 3108 005c C864     		str	r0, [r1, #76]
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3109              		.loc 1 1186 5 is_stmt 1 view .LVU1126
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3110              		.loc 1 1186 8 is_stmt 0 view .LVU1127
+ 3111 005e 216C     		ldr	r1, [r4, #64]
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3112              		.loc 1 1186 36 view .LVU1128
+ 3113 0060 0B65     		str	r3, [r1, #80]
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction);
+ 3114              		.loc 1 1189 5 is_stmt 1 view .LVU1129
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction);
+ 3115              		.loc 1 1189 8 is_stmt 0 view .LVU1130
+ 3116 0062 216C     		ldr	r1, [r4, #64]
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction);
+ 3117              		.loc 1 1189 33 view .LVU1131
+ 3118 0064 8B60     		str	r3, [r1, #8]
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3119              		.loc 1 1190 5 is_stmt 1 view .LVU1132
+ 3120 0066 206C     		ldr	r0, [r4, #64]
+ 3121 0068 0168     		ldr	r1, [r0]
+ 3122 006a 0B68     		ldr	r3, [r1]
+ 3123 006c 23F0C003 		bic	r3, r3, #192
+ 3124 0070 8068     		ldr	r0, [r0, #8]
+ 3125 0072 0343     		orrs	r3, r3, r0
+ 3126 0074 0B60     		str	r3, [r1]
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3127              		.loc 1 1193 5 view .LVU1133
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3128              		.loc 1 1193 52 is_stmt 0 view .LVU1134
+ 3129 0076 2168     		ldr	r1, [r4]
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3130              		.loc 1 1193 87 view .LVU1135
+ 3131 0078 4FEA4729 		lsl	r9, r7, #9
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3132              		.loc 1 1193 8 view .LVU1136
+ 3133 007c 4FEA9903 		lsr	r3, r9, #2
+ 3134 0080 8031     		adds	r1, r1, #128
+ 3135 0082 206C     		ldr	r0, [r4, #64]
+ 3136 0084 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3137              	.LVL266:
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3138              		.loc 1 1193 7 view .LVU1137
+ 3139 0088 8046     		mov	r8, r0
+ 3140 008a 0028     		cmp	r0, #0
+ 3141 008c 2ED1     		bne	.L201
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3142              		.loc 1 1204 7 is_stmt 1 view .LVU1138
+ 3143 008e 2268     		ldr	r2, [r4]
+ 3144 0090 D36A     		ldr	r3, [r2, #44]
+ 3145 0092 43F00803 		orr	r3, r3, #8
+ 3146 0096 D362     		str	r3, [r2, #44]
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 3147              		.loc 1 1206 7 view .LVU1139
+ARM GAS  /tmp/ccQEYyKb.s 			page 131
+
+
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 3148              		.loc 1 1206 21 is_stmt 0 view .LVU1140
+ 3149 0098 636C     		ldr	r3, [r4, #68]
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 3150              		.loc 1 1206 9 view .LVU1141
+ 3151 009a 012B     		cmp	r3, #1
+ 3152 009c 00D0     		beq	.L194
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3153              		.loc 1 1208 9 is_stmt 1 view .LVU1142
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3154              		.loc 1 1208 13 is_stmt 0 view .LVU1143
+ 3155 009e 7602     		lsls	r6, r6, #9
+ 3156              	.LVL267:
+ 3157              	.L194:
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+ 3158              		.loc 1 1212 7 is_stmt 1 view .LVU1144
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+ 3159              		.loc 1 1212 28 is_stmt 0 view .LVU1145
+ 3160 00a0 4FF0FF33 		mov	r3, #-1
+ 3161 00a4 0093     		str	r3, [sp]
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 3162              		.loc 1 1213 7 is_stmt 1 view .LVU1146
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 3163              		.loc 1 1213 28 is_stmt 0 view .LVU1147
+ 3164 00a6 CDF80490 		str	r9, [sp, #4]
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 3165              		.loc 1 1214 7 is_stmt 1 view .LVU1148
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ 3166              		.loc 1 1214 28 is_stmt 0 view .LVU1149
+ 3167 00aa 9023     		movs	r3, #144
+ 3168 00ac 0293     		str	r3, [sp, #8]
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 3169              		.loc 1 1215 7 is_stmt 1 view .LVU1150
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 3170              		.loc 1 1215 28 is_stmt 0 view .LVU1151
+ 3171 00ae 0223     		movs	r3, #2
+ 3172 00b0 0393     		str	r3, [sp, #12]
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DPSM          = SDMMC_DPSM_ENABLE;
+ 3173              		.loc 1 1216 7 is_stmt 1 view .LVU1152
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DPSM          = SDMMC_DPSM_ENABLE;
+ 3174              		.loc 1 1216 28 is_stmt 0 view .LVU1153
+ 3175 00b2 0023     		movs	r3, #0
+ 3176 00b4 0493     		str	r3, [sp, #16]
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 3177              		.loc 1 1217 7 is_stmt 1 view .LVU1154
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 3178              		.loc 1 1217 28 is_stmt 0 view .LVU1155
+ 3179 00b6 0123     		movs	r3, #1
+ 3180 00b8 0593     		str	r3, [sp, #20]
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3181              		.loc 1 1218 7 is_stmt 1 view .LVU1156
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3182              		.loc 1 1218 13 is_stmt 0 view .LVU1157
+ 3183 00ba 6946     		mov	r1, sp
+ 3184 00bc 2068     		ldr	r0, [r4]
+ 3185 00be FFF7FEFF 		bl	SDMMC_ConfigData
+ 3186              	.LVL268:
+ARM GAS  /tmp/ccQEYyKb.s 			page 132
+
+
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 3187              		.loc 1 1221 7 is_stmt 1 view .LVU1158
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 3188              		.loc 1 1221 9 is_stmt 0 view .LVU1159
+ 3189 00c2 012F     		cmp	r7, #1
+ 3190 00c4 22D9     		bls	.L195
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3191              		.loc 1 1223 9 is_stmt 1 view .LVU1160
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3192              		.loc 1 1223 22 is_stmt 0 view .LVU1161
+ 3193 00c6 8223     		movs	r3, #130
+ 3194 00c8 2363     		str	r3, [r4, #48]
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3195              		.loc 1 1226 9 is_stmt 1 view .LVU1162
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3196              		.loc 1 1226 22 is_stmt 0 view .LVU1163
+ 3197 00ca 3146     		mov	r1, r6
+ 3198 00cc 2068     		ldr	r0, [r4]
+ 3199 00ce FFF7FEFF 		bl	SDMMC_CmdReadMultiBlock
+ 3200              	.LVL269:
+ 3201              	.L196:
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 3202              		.loc 1 1235 7 is_stmt 1 view .LVU1164
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 3203              		.loc 1 1235 9 is_stmt 0 view .LVU1165
+ 3204 00d2 38B3     		cbz	r0, .L198
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= errorstate;
+ 3205              		.loc 1 1238 9 is_stmt 1 view .LVU1166
+ 3206 00d4 2368     		ldr	r3, [r4]
+ 3207 00d6 164A     		ldr	r2, .L202+8
+ 3208 00d8 9A63     		str	r2, [r3, #56]
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 3209              		.loc 1 1239 9 view .LVU1167
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 3210              		.loc 1 1239 24 is_stmt 0 view .LVU1168
+ 3211 00da A36B     		ldr	r3, [r4, #56]
+ 3212 00dc 1843     		orrs	r0, r0, r3
+ 3213              	.LVL270:
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 3214              		.loc 1 1239 24 view .LVU1169
+ 3215 00de A063     		str	r0, [r4, #56]
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 3216              		.loc 1 1240 9 is_stmt 1 view .LVU1170
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 3217              		.loc 1 1240 20 is_stmt 0 view .LVU1171
+ 3218 00e0 0123     		movs	r3, #1
+ 3219 00e2 84F83430 		strb	r3, [r4, #52]
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+ 3220              		.loc 1 1241 9 is_stmt 1 view .LVU1172
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+ 3221              		.loc 1 1241 22 is_stmt 0 view .LVU1173
+ 3222 00e6 0023     		movs	r3, #0
+ 3223 00e8 2363     		str	r3, [r4, #48]
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3224              		.loc 1 1242 9 is_stmt 1 view .LVU1174
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3225              		.loc 1 1242 16 is_stmt 0 view .LVU1175
+ARM GAS  /tmp/ccQEYyKb.s 			page 133
+
+
+ 3226 00ea 17E0     		b	.L191
+ 3227              	.LVL271:
+ 3228              	.L201:
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 3229              		.loc 1 1195 7 is_stmt 1 view .LVU1176
+ 3230 00ec 2268     		ldr	r2, [r4]
+ 3231 00ee D36B     		ldr	r3, [r2, #60]
+ 3232 00f0 23F49573 		bic	r3, r3, #298
+ 3233 00f4 D363     		str	r3, [r2, #60]
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+ 3234              		.loc 1 1196 7 view .LVU1177
+ 3235 00f6 2368     		ldr	r3, [r4]
+ 3236 00f8 0D4A     		ldr	r2, .L202+8
+ 3237 00fa 9A63     		str	r2, [r3, #56]
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3238              		.loc 1 1197 7 view .LVU1178
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3239              		.loc 1 1197 22 is_stmt 0 view .LVU1179
+ 3240 00fc A36B     		ldr	r3, [r4, #56]
+ 3241 00fe 43F08043 		orr	r3, r3, #1073741824
+ 3242 0102 A363     		str	r3, [r4, #56]
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3243              		.loc 1 1198 7 is_stmt 1 view .LVU1180
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3244              		.loc 1 1198 18 is_stmt 0 view .LVU1181
+ 3245 0104 0123     		movs	r3, #1
+ 3246 0106 84F83430 		strb	r3, [r4, #52]
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3247              		.loc 1 1199 7 is_stmt 1 view .LVU1182
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3248              		.loc 1 1199 14 is_stmt 0 view .LVU1183
+ 3249 010a 07E0     		b	.L191
+ 3250              	.LVL272:
+ 3251              	.L195:
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3252              		.loc 1 1230 9 is_stmt 1 view .LVU1184
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3253              		.loc 1 1230 22 is_stmt 0 view .LVU1185
+ 3254 010c 8123     		movs	r3, #129
+ 3255 010e 2363     		str	r3, [r4, #48]
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3256              		.loc 1 1233 9 is_stmt 1 view .LVU1186
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3257              		.loc 1 1233 22 is_stmt 0 view .LVU1187
+ 3258 0110 3146     		mov	r1, r6
+ 3259 0112 2068     		ldr	r0, [r4]
+ 3260 0114 FFF7FEFF 		bl	SDMMC_CmdReadSingleBlock
+ 3261              	.LVL273:
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3262              		.loc 1 1233 22 view .LVU1188
+ 3263 0118 DBE7     		b	.L196
+ 3264              	.LVL274:
+ 3265              	.L197:
+1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 3266              		.loc 1 1250 12 view .LVU1189
+ 3267 011a 0225     		movs	r5, #2
+ 3268              	.LVL275:
+ARM GAS  /tmp/ccQEYyKb.s 			page 134
+
+
+ 3269              	.L191:
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3270              		.loc 1 1252 1 view .LVU1190
+ 3271 011c 2846     		mov	r0, r5
+ 3272 011e 07B0     		add	sp, sp, #28
+ 3273              	.LCFI44:
+ 3274              		.cfi_remember_state
+ 3275              		.cfi_def_cfa_offset 28
+ 3276              		@ sp needed
+ 3277 0120 BDE8F083 		pop	{r4, r5, r6, r7, r8, r9, pc}
+ 3278              	.LVL276:
+ 3279              	.L198:
+ 3280              	.LCFI45:
+ 3281              		.cfi_restore_state
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3282              		.loc 1 1245 14 view .LVU1191
+ 3283 0124 4546     		mov	r5, r8
+ 3284 0126 F9E7     		b	.L191
+ 3285              	.L203:
+ 3286              		.align	2
+ 3287              	.L202:
+ 3288 0128 00000000 		.word	SD_DMAReceiveCplt
+ 3289 012c 00000000 		.word	SD_DMAError
+ 3290 0130 FF054000 		.word	4195839
+ 3291              		.cfi_endproc
+ 3292              	.LFE150:
+ 3294              		.section	.text.HAL_SD_WriteBlocks_DMA,"ax",%progbits
+ 3295              		.align	1
+ 3296              		.global	HAL_SD_WriteBlocks_DMA
+ 3297              		.syntax unified
+ 3298              		.thumb
+ 3299              		.thumb_func
+ 3300              		.fpu fpv5-d16
+ 3302              	HAL_SD_WriteBlocks_DMA:
+ 3303              	.LVL277:
+ 3304              	.LFB151:
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 3305              		.loc 1 1268 1 is_stmt 1 view -0
+ 3306              		.cfi_startproc
+ 3307              		@ args = 0, pretend = 0, frame = 24
+ 3308              		@ frame_needed = 0, uses_anonymous_args = 0
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_DataInitTypeDef config;
+ 3309              		.loc 1 1268 1 is_stmt 0 view .LVU1193
+ 3310 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 3311              	.LCFI46:
+ 3312              		.cfi_def_cfa_offset 20
+ 3313              		.cfi_offset 4, -20
+ 3314              		.cfi_offset 5, -16
+ 3315              		.cfi_offset 6, -12
+ 3316              		.cfi_offset 7, -8
+ 3317              		.cfi_offset 14, -4
+ 3318 0002 87B0     		sub	sp, sp, #28
+ 3319              	.LCFI47:
+ 3320              		.cfi_def_cfa_offset 48
+ 3321 0004 0446     		mov	r4, r0
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 3322              		.loc 1 1269 3 is_stmt 1 view .LVU1194
+ARM GAS  /tmp/ccQEYyKb.s 			page 135
+
+
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t add = BlockAdd;
+ 3323              		.loc 1 1270 3 view .LVU1195
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3324              		.loc 1 1271 3 view .LVU1196
+ 3325              	.LVL278:
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3326              		.loc 1 1273 3 view .LVU1197
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3327              		.loc 1 1273 5 is_stmt 0 view .LVU1198
+ 3328 0006 0029     		cmp	r1, #0
+ 3329 0008 39D0     		beq	.L215
+ 3330 000a 1E46     		mov	r6, r3
+ 3331 000c 0F46     		mov	r7, r1
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3332              		.loc 1 1279 3 is_stmt 1 view .LVU1199
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3333              		.loc 1 1279 9 is_stmt 0 view .LVU1200
+ 3334 000e 90F83450 		ldrb	r5, [r0, #52]	@ zero_extendqisi2
+ 3335 0012 EDB2     		uxtb	r5, r5
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3336              		.loc 1 1279 5 view .LVU1201
+ 3337 0014 012D     		cmp	r5, #1
+ 3338 0016 40F08180 		bne	.L213
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3339              		.loc 1 1281 5 is_stmt 1 view .LVU1202
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3340              		.loc 1 1281 20 is_stmt 0 view .LVU1203
+ 3341 001a 0023     		movs	r3, #0
+ 3342              	.LVL279:
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3343              		.loc 1 1281 20 view .LVU1204
+ 3344 001c 8363     		str	r3, [r0, #56]
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3345              		.loc 1 1283 5 is_stmt 1 view .LVU1205
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3346              		.loc 1 1283 13 is_stmt 0 view .LVU1206
+ 3347 001e 9319     		adds	r3, r2, r6
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3348              		.loc 1 1283 45 view .LVU1207
+ 3349 0020 C16D     		ldr	r1, [r0, #92]
+ 3350              	.LVL280:
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3351              		.loc 1 1283 7 view .LVU1208
+ 3352 0022 8B42     		cmp	r3, r1
+ 3353 0024 31D8     		bhi	.L216
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3354              		.loc 1 1289 5 is_stmt 1 view .LVU1209
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3355              		.loc 1 1289 16 is_stmt 0 view .LVU1210
+ 3356 0026 0323     		movs	r3, #3
+ 3357 0028 80F83430 		strb	r3, [r0, #52]
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3358              		.loc 1 1292 5 is_stmt 1 view .LVU1211
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3359              		.loc 1 1292 8 is_stmt 0 view .LVU1212
+ 3360 002c 0368     		ldr	r3, [r0]
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 136
+
+
+ 3361              		.loc 1 1292 26 view .LVU1213
+ 3362 002e 0021     		movs	r1, #0
+ 3363 0030 D962     		str	r1, [r3, #44]
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3364              		.loc 1 1295 5 is_stmt 1 view .LVU1214
+ 3365 0032 0068     		ldr	r0, [r0]
+ 3366              	.LVL281:
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3367              		.loc 1 1295 5 is_stmt 0 view .LVU1215
+ 3368 0034 C36B     		ldr	r3, [r0, #60]
+ 3369 0036 43F01A03 		orr	r3, r3, #26
+ 3370 003a C363     		str	r3, [r0, #60]
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3371              		.loc 1 1298 5 is_stmt 1 view .LVU1216
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3372              		.loc 1 1298 8 is_stmt 0 view .LVU1217
+ 3373 003c E36B     		ldr	r3, [r4, #60]
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3374              		.loc 1 1298 35 view .LVU1218
+ 3375 003e 3948     		ldr	r0, .L217
+ 3376 0040 D863     		str	r0, [r3, #60]
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3377              		.loc 1 1301 5 is_stmt 1 view .LVU1219
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3378              		.loc 1 1301 8 is_stmt 0 view .LVU1220
+ 3379 0042 E36B     		ldr	r3, [r4, #60]
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3380              		.loc 1 1301 36 view .LVU1221
+ 3381 0044 3848     		ldr	r0, .L217+4
+ 3382 0046 D864     		str	r0, [r3, #76]
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3383              		.loc 1 1304 5 is_stmt 1 view .LVU1222
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3384              		.loc 1 1304 8 is_stmt 0 view .LVU1223
+ 3385 0048 E36B     		ldr	r3, [r4, #60]
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3386              		.loc 1 1304 36 view .LVU1224
+ 3387 004a 1965     		str	r1, [r3, #80]
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3388              		.loc 1 1306 5 is_stmt 1 view .LVU1225
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3389              		.loc 1 1306 19 is_stmt 0 view .LVU1226
+ 3390 004c 636C     		ldr	r3, [r4, #68]
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3391              		.loc 1 1306 7 view .LVU1227
+ 3392 004e 012B     		cmp	r3, #1
+ 3393 0050 00D0     		beq	.L208
+1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3394              		.loc 1 1308 7 is_stmt 1 view .LVU1228
+1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3395              		.loc 1 1308 11 is_stmt 0 view .LVU1229
+ 3396 0052 5202     		lsls	r2, r2, #9
+ 3397              	.LVL282:
+ 3398              	.L208:
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3399              		.loc 1 1312 5 is_stmt 1 view .LVU1230
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ARM GAS  /tmp/ccQEYyKb.s 			page 137
+
+
+ 3400              		.loc 1 1312 7 is_stmt 0 view .LVU1231
+ 3401 0054 012E     		cmp	r6, #1
+ 3402 0056 1DD9     		bls	.L209
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3403              		.loc 1 1314 7 is_stmt 1 view .LVU1232
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3404              		.loc 1 1314 20 is_stmt 0 view .LVU1233
+ 3405 0058 A023     		movs	r3, #160
+ 3406 005a 2363     		str	r3, [r4, #48]
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3407              		.loc 1 1317 7 is_stmt 1 view .LVU1234
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3408              		.loc 1 1317 20 is_stmt 0 view .LVU1235
+ 3409 005c 1146     		mov	r1, r2
+ 3410 005e 2068     		ldr	r0, [r4]
+ 3411 0060 FFF7FEFF 		bl	SDMMC_CmdWriteMultiBlock
+ 3412              	.LVL283:
+ 3413              	.L210:
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3414              		.loc 1 1326 5 is_stmt 1 view .LVU1236
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3415              		.loc 1 1326 7 is_stmt 0 view .LVU1237
+ 3416 0064 E8B1     		cbz	r0, .L211
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+ 3417              		.loc 1 1329 7 is_stmt 1 view .LVU1238
+ 3418 0066 2368     		ldr	r3, [r4]
+ 3419 0068 304A     		ldr	r2, .L217+8
+ 3420 006a 9A63     		str	r2, [r3, #56]
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3421              		.loc 1 1330 7 view .LVU1239
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3422              		.loc 1 1330 22 is_stmt 0 view .LVU1240
+ 3423 006c A36B     		ldr	r3, [r4, #56]
+ 3424 006e 1843     		orrs	r0, r0, r3
+ 3425              	.LVL284:
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3426              		.loc 1 1330 22 view .LVU1241
+ 3427 0070 A063     		str	r0, [r4, #56]
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 3428              		.loc 1 1331 7 is_stmt 1 view .LVU1242
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 3429              		.loc 1 1331 18 is_stmt 0 view .LVU1243
+ 3430 0072 0123     		movs	r3, #1
+ 3431 0074 84F83430 		strb	r3, [r4, #52]
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3432              		.loc 1 1332 7 is_stmt 1 view .LVU1244
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3433              		.loc 1 1332 20 is_stmt 0 view .LVU1245
+ 3434 0078 0023     		movs	r3, #0
+ 3435 007a 2363     		str	r3, [r4, #48]
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3436              		.loc 1 1333 7 is_stmt 1 view .LVU1246
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3437              		.loc 1 1333 14 is_stmt 0 view .LVU1247
+ 3438 007c 4FE0     		b	.L206
+ 3439              	.LVL285:
+ 3440              	.L215:
+ARM GAS  /tmp/ccQEYyKb.s 			page 138
+
+
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 3441              		.loc 1 1275 5 is_stmt 1 view .LVU1248
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 3442              		.loc 1 1275 20 is_stmt 0 view .LVU1249
+ 3443 007e 836B     		ldr	r3, [r0, #56]
+ 3444              	.LVL286:
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 3445              		.loc 1 1275 20 view .LVU1250
+ 3446 0080 43F00063 		orr	r3, r3, #134217728
+ 3447 0084 8363     		str	r3, [r0, #56]
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 3448              		.loc 1 1276 5 is_stmt 1 view .LVU1251
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 3449              		.loc 1 1276 12 is_stmt 0 view .LVU1252
+ 3450 0086 0125     		movs	r5, #1
+ 3451 0088 49E0     		b	.L206
+ 3452              	.LVL287:
+ 3453              	.L216:
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3454              		.loc 1 1285 7 is_stmt 1 view .LVU1253
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3455              		.loc 1 1285 22 is_stmt 0 view .LVU1254
+ 3456 008a 836B     		ldr	r3, [r0, #56]
+ 3457 008c 43F00073 		orr	r3, r3, #33554432
+ 3458 0090 8363     		str	r3, [r0, #56]
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3459              		.loc 1 1286 7 is_stmt 1 view .LVU1255
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3460              		.loc 1 1286 14 is_stmt 0 view .LVU1256
+ 3461 0092 44E0     		b	.L206
+ 3462              	.LVL288:
+ 3463              	.L209:
+1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3464              		.loc 1 1321 7 is_stmt 1 view .LVU1257
+1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3465              		.loc 1 1321 20 is_stmt 0 view .LVU1258
+ 3466 0094 9023     		movs	r3, #144
+ 3467 0096 2363     		str	r3, [r4, #48]
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3468              		.loc 1 1324 7 is_stmt 1 view .LVU1259
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3469              		.loc 1 1324 20 is_stmt 0 view .LVU1260
+ 3470 0098 1146     		mov	r1, r2
+ 3471 009a 2068     		ldr	r0, [r4]
+ 3472 009c FFF7FEFF 		bl	SDMMC_CmdWriteSingleBlock
+ 3473              	.LVL289:
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3474              		.loc 1 1324 20 view .LVU1261
+ 3475 00a0 E0E7     		b	.L210
+ 3476              	.L211:
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3477              		.loc 1 1337 5 is_stmt 1 view .LVU1262
+ 3478 00a2 2268     		ldr	r2, [r4]
+ 3479 00a4 D36A     		ldr	r3, [r2, #44]
+ 3480 00a6 43F00803 		orr	r3, r3, #8
+ 3481 00aa D362     		str	r3, [r2, #44]
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction);
+ARM GAS  /tmp/ccQEYyKb.s 			page 139
+
+
+ 3482              		.loc 1 1340 5 view .LVU1263
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction);
+ 3483              		.loc 1 1340 8 is_stmt 0 view .LVU1264
+ 3484 00ac E36B     		ldr	r3, [r4, #60]
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction);
+ 3485              		.loc 1 1340 33 view .LVU1265
+ 3486 00ae 4022     		movs	r2, #64
+ 3487 00b0 9A60     		str	r2, [r3, #8]
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3488              		.loc 1 1341 5 is_stmt 1 view .LVU1266
+ 3489 00b2 E16B     		ldr	r1, [r4, #60]
+ 3490 00b4 0A68     		ldr	r2, [r1]
+ 3491 00b6 1368     		ldr	r3, [r2]
+ 3492 00b8 23F0C003 		bic	r3, r3, #192
+ 3493 00bc 8968     		ldr	r1, [r1, #8]
+ 3494 00be 0B43     		orrs	r3, r3, r1
+ 3495 00c0 1360     		str	r3, [r2]
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3496              		.loc 1 1344 5 view .LVU1267
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3497              		.loc 1 1344 69 is_stmt 0 view .LVU1268
+ 3498 00c2 2268     		ldr	r2, [r4]
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3499              		.loc 1 1344 87 view .LVU1269
+ 3500 00c4 7602     		lsls	r6, r6, #9
+ 3501              	.LVL290:
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3502              		.loc 1 1344 8 view .LVU1270
+ 3503 00c6 B308     		lsrs	r3, r6, #2
+ 3504 00c8 8032     		adds	r2, r2, #128
+ 3505 00ca 3946     		mov	r1, r7
+ 3506 00cc E06B     		ldr	r0, [r4, #60]
+ 3507              	.LVL291:
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3508              		.loc 1 1344 8 view .LVU1271
+ 3509 00ce FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3510              	.LVL292:
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3511              		.loc 1 1344 7 view .LVU1272
+ 3512 00d2 0746     		mov	r7, r0
+ 3513              	.LVL293:
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3514              		.loc 1 1344 7 view .LVU1273
+ 3515 00d4 88B1     		cbz	r0, .L212
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ 3516              		.loc 1 1346 7 is_stmt 1 view .LVU1274
+ 3517 00d6 2268     		ldr	r2, [r4]
+ 3518 00d8 D36B     		ldr	r3, [r2, #60]
+ 3519 00da 23F01A03 		bic	r3, r3, #26
+ 3520 00de D363     		str	r3, [r2, #60]
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+ 3521              		.loc 1 1347 7 view .LVU1275
+ 3522 00e0 2368     		ldr	r3, [r4]
+ 3523 00e2 124A     		ldr	r2, .L217+8
+ 3524 00e4 9A63     		str	r2, [r3, #56]
+1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3525              		.loc 1 1348 7 view .LVU1276
+ARM GAS  /tmp/ccQEYyKb.s 			page 140
+
+
+1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3526              		.loc 1 1348 22 is_stmt 0 view .LVU1277
+ 3527 00e6 A36B     		ldr	r3, [r4, #56]
+ 3528 00e8 43F08043 		orr	r3, r3, #1073741824
+ 3529 00ec A363     		str	r3, [r4, #56]
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 3530              		.loc 1 1349 7 is_stmt 1 view .LVU1278
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 3531              		.loc 1 1349 18 is_stmt 0 view .LVU1279
+ 3532 00ee 0123     		movs	r3, #1
+ 3533 00f0 84F83430 		strb	r3, [r4, #52]
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3534              		.loc 1 1350 7 is_stmt 1 view .LVU1280
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3535              		.loc 1 1350 20 is_stmt 0 view .LVU1281
+ 3536 00f4 0023     		movs	r3, #0
+ 3537 00f6 2363     		str	r3, [r4, #48]
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3538              		.loc 1 1351 7 is_stmt 1 view .LVU1282
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3539              		.loc 1 1351 14 is_stmt 0 view .LVU1283
+ 3540 00f8 11E0     		b	.L206
+ 3541              	.L212:
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+ 3542              		.loc 1 1356 7 is_stmt 1 view .LVU1284
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+ 3543              		.loc 1 1356 28 is_stmt 0 view .LVU1285
+ 3544 00fa 4FF0FF33 		mov	r3, #-1
+ 3545 00fe 0093     		str	r3, [sp]
+1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 3546              		.loc 1 1357 7 is_stmt 1 view .LVU1286
+1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ 3547              		.loc 1 1357 28 is_stmt 0 view .LVU1287
+ 3548 0100 0196     		str	r6, [sp, #4]
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+ 3549              		.loc 1 1358 7 is_stmt 1 view .LVU1288
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+ 3550              		.loc 1 1358 28 is_stmt 0 view .LVU1289
+ 3551 0102 9023     		movs	r3, #144
+ 3552 0104 0293     		str	r3, [sp, #8]
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 3553              		.loc 1 1359 7 is_stmt 1 view .LVU1290
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+ 3554              		.loc 1 1359 28 is_stmt 0 view .LVU1291
+ 3555 0106 0023     		movs	r3, #0
+ 3556 0108 0393     		str	r3, [sp, #12]
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DPSM          = SDMMC_DPSM_ENABLE;
+ 3557              		.loc 1 1360 7 is_stmt 1 view .LVU1292
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       config.DPSM          = SDMMC_DPSM_ENABLE;
+ 3558              		.loc 1 1360 28 is_stmt 0 view .LVU1293
+ 3559 010a 0493     		str	r3, [sp, #16]
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 3560              		.loc 1 1361 7 is_stmt 1 view .LVU1294
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       (void)SDMMC_ConfigData(hsd->Instance, &config);
+ 3561              		.loc 1 1361 28 is_stmt 0 view .LVU1295
+ 3562 010c 0123     		movs	r3, #1
+ 3563 010e 0593     		str	r3, [sp, #20]
+ARM GAS  /tmp/ccQEYyKb.s 			page 141
+
+
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3564              		.loc 1 1362 7 is_stmt 1 view .LVU1296
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3565              		.loc 1 1362 13 is_stmt 0 view .LVU1297
+ 3566 0110 6946     		mov	r1, sp
+ 3567 0112 2068     		ldr	r0, [r4]
+ 3568 0114 FFF7FEFF 		bl	SDMMC_ConfigData
+ 3569              	.LVL294:
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3570              		.loc 1 1364 7 is_stmt 1 view .LVU1298
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3571              		.loc 1 1364 14 is_stmt 0 view .LVU1299
+ 3572 0118 3D46     		mov	r5, r7
+ 3573 011a 00E0     		b	.L206
+ 3574              	.LVL295:
+ 3575              	.L213:
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 3576              		.loc 1 1369 12 view .LVU1300
+ 3577 011c 0225     		movs	r5, #2
+ 3578              	.LVL296:
+ 3579              	.L206:
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3580              		.loc 1 1371 1 view .LVU1301
+ 3581 011e 2846     		mov	r0, r5
+ 3582 0120 07B0     		add	sp, sp, #28
+ 3583              	.LCFI48:
+ 3584              		.cfi_def_cfa_offset 20
+ 3585              		@ sp needed
+ 3586 0122 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 3587              	.LVL297:
+ 3588              	.L218:
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3589              		.loc 1 1371 1 view .LVU1302
+ 3590              		.align	2
+ 3591              	.L217:
+ 3592 0124 00000000 		.word	SD_DMATransmitCplt
+ 3593 0128 00000000 		.word	SD_DMAError
+ 3594 012c FF054000 		.word	4195839
+ 3595              		.cfi_endproc
+ 3596              	.LFE151:
+ 3598              		.section	.text.HAL_SD_Erase,"ax",%progbits
+ 3599              		.align	1
+ 3600              		.global	HAL_SD_Erase
+ 3601              		.syntax unified
+ 3602              		.thumb
+ 3603              		.thumb_func
+ 3604              		.fpu fpv5-d16
+ 3606              	HAL_SD_Erase:
+ 3607              	.LVL298:
+ 3608              	.LFB152:
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 3609              		.loc 1 1383 1 is_stmt 1 view -0
+ 3610              		.cfi_startproc
+ 3611              		@ args = 0, pretend = 0, frame = 0
+ 3612              		@ frame_needed = 0, uses_anonymous_args = 0
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 3613              		.loc 1 1383 1 is_stmt 0 view .LVU1304
+ARM GAS  /tmp/ccQEYyKb.s 			page 142
+
+
+ 3614 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 3615              	.LCFI49:
+ 3616              		.cfi_def_cfa_offset 24
+ 3617              		.cfi_offset 3, -24
+ 3618              		.cfi_offset 4, -20
+ 3619              		.cfi_offset 5, -16
+ 3620              		.cfi_offset 6, -12
+ 3621              		.cfi_offset 7, -8
+ 3622              		.cfi_offset 14, -4
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t start_add = BlockStartAdd;
+ 3623              		.loc 1 1384 3 is_stmt 1 view .LVU1305
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t end_add = BlockEndAdd;
+ 3624              		.loc 1 1385 3 view .LVU1306
+ 3625              	.LVL299:
+1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3626              		.loc 1 1386 3 view .LVU1307
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3627              		.loc 1 1388 3 view .LVU1308
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3628              		.loc 1 1388 9 is_stmt 0 view .LVU1309
+ 3629 0002 90F83450 		ldrb	r5, [r0, #52]	@ zero_extendqisi2
+ 3630 0006 EDB2     		uxtb	r5, r5
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3631              		.loc 1 1388 5 view .LVU1310
+ 3632 0008 012D     		cmp	r5, #1
+ 3633 000a 6FD1     		bne	.L229
+ 3634 000c 0446     		mov	r4, r0
+ 3635 000e 0F46     		mov	r7, r1
+ 3636 0010 1646     		mov	r6, r2
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3637              		.loc 1 1390 5 is_stmt 1 view .LVU1311
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3638              		.loc 1 1390 20 is_stmt 0 view .LVU1312
+ 3639 0012 0023     		movs	r3, #0
+ 3640 0014 8363     		str	r3, [r0, #56]
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3641              		.loc 1 1392 5 is_stmt 1 view .LVU1313
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3642              		.loc 1 1392 7 is_stmt 0 view .LVU1314
+ 3643 0016 9142     		cmp	r1, r2
+ 3644 0018 14D8     		bhi	.L231
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3645              		.loc 1 1398 5 is_stmt 1 view .LVU1315
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3646              		.loc 1 1398 30 is_stmt 0 view .LVU1316
+ 3647 001a C36D     		ldr	r3, [r0, #92]
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3648              		.loc 1 1398 7 view .LVU1317
+ 3649 001c 9342     		cmp	r3, r2
+ 3650 001e 16D3     		bcc	.L232
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3651              		.loc 1 1404 5 is_stmt 1 view .LVU1318
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3652              		.loc 1 1404 16 is_stmt 0 view .LVU1319
+ 3653 0020 0323     		movs	r3, #3
+ 3654 0022 80F83430 		strb	r3, [r0, #52]
+1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ARM GAS  /tmp/ccQEYyKb.s 			page 143
+
+
+ 3655              		.loc 1 1407 5 is_stmt 1 view .LVU1320
+1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3656              		.loc 1 1407 21 is_stmt 0 view .LVU1321
+ 3657 0026 C36C     		ldr	r3, [r0, #76]
+1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3658              		.loc 1 1407 7 view .LVU1322
+ 3659 0028 13F0200F 		tst	r3, #32
+ 3660 002c 14D1     		bne	.L223
+1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ 3661              		.loc 1 1410 7 is_stmt 1 view .LVU1323
+ 3662 002e 0368     		ldr	r3, [r0]
+ 3663 0030 304A     		ldr	r2, .L235
+ 3664              	.LVL300:
+1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ 3665              		.loc 1 1410 7 is_stmt 0 view .LVU1324
+ 3666 0032 9A63     		str	r2, [r3, #56]
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3667              		.loc 1 1411 7 is_stmt 1 view .LVU1325
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3668              		.loc 1 1411 22 is_stmt 0 view .LVU1326
+ 3669 0034 836B     		ldr	r3, [r0, #56]
+ 3670 0036 43F08063 		orr	r3, r3, #67108864
+ 3671 003a 8363     		str	r3, [r0, #56]
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3672              		.loc 1 1412 7 is_stmt 1 view .LVU1327
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3673              		.loc 1 1412 18 is_stmt 0 view .LVU1328
+ 3674 003c 0123     		movs	r3, #1
+ 3675 003e 80F83430 		strb	r3, [r0, #52]
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3676              		.loc 1 1413 7 is_stmt 1 view .LVU1329
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3677              		.loc 1 1413 14 is_stmt 0 view .LVU1330
+ 3678 0042 54E0     		b	.L220
+ 3679              	.LVL301:
+ 3680              	.L231:
+1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3681              		.loc 1 1394 7 is_stmt 1 view .LVU1331
+1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3682              		.loc 1 1394 22 is_stmt 0 view .LVU1332
+ 3683 0044 836B     		ldr	r3, [r0, #56]
+ 3684 0046 43F00063 		orr	r3, r3, #134217728
+ 3685 004a 8363     		str	r3, [r0, #56]
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3686              		.loc 1 1395 7 is_stmt 1 view .LVU1333
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3687              		.loc 1 1395 14 is_stmt 0 view .LVU1334
+ 3688 004c 4FE0     		b	.L220
+ 3689              	.L232:
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3690              		.loc 1 1400 7 is_stmt 1 view .LVU1335
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3691              		.loc 1 1400 22 is_stmt 0 view .LVU1336
+ 3692 004e 836B     		ldr	r3, [r0, #56]
+ 3693 0050 43F00073 		orr	r3, r3, #33554432
+ 3694 0054 8363     		str	r3, [r0, #56]
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ARM GAS  /tmp/ccQEYyKb.s 			page 144
+
+
+ 3695              		.loc 1 1401 7 is_stmt 1 view .LVU1337
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3696              		.loc 1 1401 14 is_stmt 0 view .LVU1338
+ 3697 0056 4AE0     		b	.L220
+ 3698              	.L223:
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3699              		.loc 1 1416 5 is_stmt 1 view .LVU1339
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3700              		.loc 1 1416 9 is_stmt 0 view .LVU1340
+ 3701 0058 0021     		movs	r1, #0
+ 3702              	.LVL302:
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3703              		.loc 1 1416 9 view .LVU1341
+ 3704 005a 0068     		ldr	r0, [r0]
+ 3705              	.LVL303:
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3706              		.loc 1 1416 9 view .LVU1342
+ 3707 005c FFF7FEFF 		bl	SDMMC_GetResponse
+ 3708              	.LVL304:
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3709              		.loc 1 1416 7 view .LVU1343
+ 3710 0060 10F0007F 		tst	r0, #33554432
+ 3711 0064 15D1     		bne	.L233
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3712              		.loc 1 1426 5 is_stmt 1 view .LVU1344
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3713              		.loc 1 1426 19 is_stmt 0 view .LVU1345
+ 3714 0066 636C     		ldr	r3, [r4, #68]
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3715              		.loc 1 1426 7 view .LVU1346
+ 3716 0068 012B     		cmp	r3, #1
+ 3717 006a 01D0     		beq	.L225
+1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       end_add   *= 512U;
+ 3718              		.loc 1 1428 7 is_stmt 1 view .LVU1347
+1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       end_add   *= 512U;
+ 3719              		.loc 1 1428 17 is_stmt 0 view .LVU1348
+ 3720 006c 7F02     		lsls	r7, r7, #9
+ 3721              	.LVL305:
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3722              		.loc 1 1429 7 is_stmt 1 view .LVU1349
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3723              		.loc 1 1429 17 is_stmt 0 view .LVU1350
+ 3724 006e 7602     		lsls	r6, r6, #9
+ 3725              	.LVL306:
+ 3726              	.L225:
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3727              		.loc 1 1433 5 is_stmt 1 view .LVU1351
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3728              		.loc 1 1433 7 is_stmt 0 view .LVU1352
+ 3729 0070 032B     		cmp	r3, #3
+ 3730 0072 1ED0     		beq	.L226
+1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(errorstate != HAL_SD_ERROR_NONE)
+ 3731              		.loc 1 1436 7 is_stmt 1 view .LVU1353
+1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(errorstate != HAL_SD_ERROR_NONE)
+ 3732              		.loc 1 1436 20 is_stmt 0 view .LVU1354
+ 3733 0074 3946     		mov	r1, r7
+ 3734 0076 2068     		ldr	r0, [r4]
+ARM GAS  /tmp/ccQEYyKb.s 			page 145
+
+
+ 3735 0078 FFF7FEFF 		bl	SDMMC_CmdSDEraseStartAdd
+ 3736              	.LVL307:
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 3737              		.loc 1 1437 7 is_stmt 1 view .LVU1355
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 3738              		.loc 1 1437 9 is_stmt 0 view .LVU1356
+ 3739 007c A0B1     		cbz	r0, .L227
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= errorstate;
+ 3740              		.loc 1 1440 9 is_stmt 1 view .LVU1357
+ 3741 007e 2368     		ldr	r3, [r4]
+ 3742 0080 1C49     		ldr	r1, .L235
+ 3743 0082 9963     		str	r1, [r3, #56]
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 3744              		.loc 1 1441 9 view .LVU1358
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 3745              		.loc 1 1441 24 is_stmt 0 view .LVU1359
+ 3746 0084 A36B     		ldr	r3, [r4, #56]
+ 3747 0086 0343     		orrs	r3, r3, r0
+ 3748 0088 A363     		str	r3, [r4, #56]
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+ 3749              		.loc 1 1442 9 is_stmt 1 view .LVU1360
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+ 3750              		.loc 1 1442 20 is_stmt 0 view .LVU1361
+ 3751 008a 0123     		movs	r3, #1
+ 3752 008c 84F83430 		strb	r3, [r4, #52]
+1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3753              		.loc 1 1443 9 is_stmt 1 view .LVU1362
+1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3754              		.loc 1 1443 16 is_stmt 0 view .LVU1363
+ 3755 0090 2DE0     		b	.L220
+ 3756              	.LVL308:
+ 3757              	.L233:
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ 3758              		.loc 1 1419 7 is_stmt 1 view .LVU1364
+ 3759 0092 2368     		ldr	r3, [r4]
+ 3760 0094 174A     		ldr	r2, .L235
+ 3761 0096 9A63     		str	r2, [r3, #56]
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3762              		.loc 1 1420 7 view .LVU1365
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3763              		.loc 1 1420 22 is_stmt 0 view .LVU1366
+ 3764 0098 A36B     		ldr	r3, [r4, #56]
+ 3765 009a 43F40063 		orr	r3, r3, #2048
+ 3766 009e A363     		str	r3, [r4, #56]
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3767              		.loc 1 1421 7 is_stmt 1 view .LVU1367
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3768              		.loc 1 1421 18 is_stmt 0 view .LVU1368
+ 3769 00a0 0123     		movs	r3, #1
+ 3770 00a2 84F83430 		strb	r3, [r4, #52]
+1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3771              		.loc 1 1422 7 is_stmt 1 view .LVU1369
+1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3772              		.loc 1 1422 14 is_stmt 0 view .LVU1370
+ 3773 00a6 22E0     		b	.L220
+ 3774              	.LVL309:
+ 3775              	.L227:
+ARM GAS  /tmp/ccQEYyKb.s 			page 146
+
+
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(errorstate != HAL_SD_ERROR_NONE)
+ 3776              		.loc 1 1447 7 is_stmt 1 view .LVU1371
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(errorstate != HAL_SD_ERROR_NONE)
+ 3777              		.loc 1 1447 20 is_stmt 0 view .LVU1372
+ 3778 00a8 3146     		mov	r1, r6
+ 3779 00aa 2068     		ldr	r0, [r4]
+ 3780              	.LVL310:
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(errorstate != HAL_SD_ERROR_NONE)
+ 3781              		.loc 1 1447 20 view .LVU1373
+ 3782 00ac FFF7FEFF 		bl	SDMMC_CmdSDEraseEndAdd
+ 3783              	.LVL311:
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 3784              		.loc 1 1448 7 is_stmt 1 view .LVU1374
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 3785              		.loc 1 1448 9 is_stmt 0 view .LVU1375
+ 3786 00b0 68B9     		cbnz	r0, .L234
+ 3787              	.LVL312:
+ 3788              	.L226:
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 3789              		.loc 1 1459 5 is_stmt 1 view .LVU1376
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 3790              		.loc 1 1459 18 is_stmt 0 view .LVU1377
+ 3791 00b2 2068     		ldr	r0, [r4]
+ 3792 00b4 FFF7FEFF 		bl	SDMMC_CmdErase
+ 3793              	.LVL313:
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3794              		.loc 1 1460 5 is_stmt 1 view .LVU1378
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 3795              		.loc 1 1460 7 is_stmt 0 view .LVU1379
+ 3796 00b8 98B1     		cbz	r0, .L228
+1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->ErrorCode |= errorstate;
+ 3797              		.loc 1 1463 7 is_stmt 1 view .LVU1380
+ 3798 00ba 2368     		ldr	r3, [r4]
+ 3799 00bc 0D49     		ldr	r1, .L235
+ 3800 00be 9963     		str	r1, [r3, #56]
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3801              		.loc 1 1464 7 view .LVU1381
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->State = HAL_SD_STATE_READY;
+ 3802              		.loc 1 1464 22 is_stmt 0 view .LVU1382
+ 3803 00c0 A36B     		ldr	r3, [r4, #56]
+ 3804 00c2 0343     		orrs	r3, r3, r0
+ 3805 00c4 A363     		str	r3, [r4, #56]
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3806              		.loc 1 1465 7 is_stmt 1 view .LVU1383
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       return HAL_ERROR;
+ 3807              		.loc 1 1465 18 is_stmt 0 view .LVU1384
+ 3808 00c6 0123     		movs	r3, #1
+ 3809 00c8 84F83430 		strb	r3, [r4, #52]
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3810              		.loc 1 1466 7 is_stmt 1 view .LVU1385
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 3811              		.loc 1 1466 14 is_stmt 0 view .LVU1386
+ 3812 00cc 0FE0     		b	.L220
+ 3813              	.L234:
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->ErrorCode |= errorstate;
+ 3814              		.loc 1 1451 9 is_stmt 1 view .LVU1387
+ 3815 00ce 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/ccQEYyKb.s 			page 147
+
+
+ 3816 00d0 0849     		ldr	r1, .L235
+ 3817 00d2 9963     		str	r1, [r3, #56]
+1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 3818              		.loc 1 1452 9 view .LVU1388
+1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 3819              		.loc 1 1452 24 is_stmt 0 view .LVU1389
+ 3820 00d4 A36B     		ldr	r3, [r4, #56]
+ 3821 00d6 0343     		orrs	r3, r3, r0
+ 3822 00d8 A363     		str	r3, [r4, #56]
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+ 3823              		.loc 1 1453 9 is_stmt 1 view .LVU1390
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         return HAL_ERROR;
+ 3824              		.loc 1 1453 20 is_stmt 0 view .LVU1391
+ 3825 00da 0123     		movs	r3, #1
+ 3826 00dc 84F83430 		strb	r3, [r4, #52]
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3827              		.loc 1 1454 9 is_stmt 1 view .LVU1392
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 3828              		.loc 1 1454 16 is_stmt 0 view .LVU1393
+ 3829 00e0 05E0     		b	.L220
+ 3830              	.L228:
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3831              		.loc 1 1469 5 is_stmt 1 view .LVU1394
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3832              		.loc 1 1469 16 is_stmt 0 view .LVU1395
+ 3833 00e2 0123     		movs	r3, #1
+ 3834 00e4 84F83430 		strb	r3, [r4, #52]
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 3835              		.loc 1 1471 5 is_stmt 1 view .LVU1396
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 3836              		.loc 1 1471 12 is_stmt 0 view .LVU1397
+ 3837 00e8 0025     		movs	r5, #0
+ 3838 00ea 00E0     		b	.L220
+ 3839              	.LVL314:
+ 3840              	.L229:
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 3841              		.loc 1 1475 12 view .LVU1398
+ 3842 00ec 0225     		movs	r5, #2
+ 3843              	.LVL315:
+ 3844              	.L220:
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3845              		.loc 1 1477 1 view .LVU1399
+ 3846 00ee 2846     		mov	r0, r5
+ 3847 00f0 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 3848              	.L236:
+ 3849 00f2 00BF     		.align	2
+ 3850              	.L235:
+ 3851 00f4 FF054000 		.word	4195839
+ 3852              		.cfi_endproc
+ 3853              	.LFE152:
+ 3855              		.section	.text.HAL_SD_GetState,"ax",%progbits
+ 3856              		.align	1
+ 3857              		.global	HAL_SD_GetState
+ 3858              		.syntax unified
+ 3859              		.thumb
+ 3860              		.thumb_func
+ 3861              		.fpu fpv5-d16
+ARM GAS  /tmp/ccQEYyKb.s 			page 148
+
+
+ 3863              	HAL_SD_GetState:
+ 3864              	.LVL316:
+ 3865              	.LFB154:
+1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return hsd->State;
+ 3866              		.loc 1 1676 1 is_stmt 1 view -0
+ 3867              		.cfi_startproc
+ 3868              		@ args = 0, pretend = 0, frame = 0
+ 3869              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3870              		@ link register save eliminated.
+1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 3871              		.loc 1 1677 3 view .LVU1401
+1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 3872              		.loc 1 1677 13 is_stmt 0 view .LVU1402
+ 3873 0000 90F83400 		ldrb	r0, [r0, #52]	@ zero_extendqisi2
+ 3874              	.LVL317:
+1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3875              		.loc 1 1678 1 view .LVU1403
+ 3876 0004 7047     		bx	lr
+ 3877              		.cfi_endproc
+ 3878              	.LFE154:
+ 3880              		.section	.text.HAL_SD_GetError,"ax",%progbits
+ 3881              		.align	1
+ 3882              		.global	HAL_SD_GetError
+ 3883              		.syntax unified
+ 3884              		.thumb
+ 3885              		.thumb_func
+ 3886              		.fpu fpv5-d16
+ 3888              	HAL_SD_GetError:
+ 3889              	.LVL318:
+ 3890              	.LFB155:
+1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   return hsd->ErrorCode;
+ 3891              		.loc 1 1687 1 is_stmt 1 view -0
+ 3892              		.cfi_startproc
+ 3893              		@ args = 0, pretend = 0, frame = 0
+ 3894              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3895              		@ link register save eliminated.
+1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 3896              		.loc 1 1688 3 view .LVU1405
+1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 3897              		.loc 1 1688 13 is_stmt 0 view .LVU1406
+ 3898 0000 806B     		ldr	r0, [r0, #56]
+ 3899              	.LVL319:
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3900              		.loc 1 1689 1 view .LVU1407
+ 3901 0002 7047     		bx	lr
+ 3902              		.cfi_endproc
+ 3903              	.LFE155:
+ 3905              		.section	.text.HAL_SD_TxCpltCallback,"ax",%progbits
+ 3906              		.align	1
+ 3907              		.weak	HAL_SD_TxCpltCallback
+ 3908              		.syntax unified
+ 3909              		.thumb
+ 3910              		.thumb_func
+ 3911              		.fpu fpv5-d16
+ 3913              	HAL_SD_TxCpltCallback:
+ 3914              	.LVL320:
+ 3915              	.LFB156:
+ARM GAS  /tmp/ccQEYyKb.s 			page 149
+
+
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+ 3916              		.loc 1 1697 1 is_stmt 1 view -0
+ 3917              		.cfi_startproc
+ 3918              		@ args = 0, pretend = 0, frame = 0
+ 3919              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3920              		@ link register save eliminated.
+1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3921              		.loc 1 1699 3 view .LVU1409
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3922              		.loc 1 1704 1 is_stmt 0 view .LVU1410
+ 3923 0000 7047     		bx	lr
+ 3924              		.cfi_endproc
+ 3925              	.LFE156:
+ 3927              		.section	.text.HAL_SD_RxCpltCallback,"ax",%progbits
+ 3928              		.align	1
+ 3929              		.weak	HAL_SD_RxCpltCallback
+ 3930              		.syntax unified
+ 3931              		.thumb
+ 3932              		.thumb_func
+ 3933              		.fpu fpv5-d16
+ 3935              	HAL_SD_RxCpltCallback:
+ 3936              	.LVL321:
+ 3937              	.LFB157:
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+ 3938              		.loc 1 1712 1 is_stmt 1 view -0
+ 3939              		.cfi_startproc
+ 3940              		@ args = 0, pretend = 0, frame = 0
+ 3941              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3942              		@ link register save eliminated.
+1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3943              		.loc 1 1714 3 view .LVU1412
+1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3944              		.loc 1 1719 1 is_stmt 0 view .LVU1413
+ 3945 0000 7047     		bx	lr
+ 3946              		.cfi_endproc
+ 3947              	.LFE157:
+ 3949              		.section	.text.HAL_SD_ErrorCallback,"ax",%progbits
+ 3950              		.align	1
+ 3951              		.weak	HAL_SD_ErrorCallback
+ 3952              		.syntax unified
+ 3953              		.thumb
+ 3954              		.thumb_func
+ 3955              		.fpu fpv5-d16
+ 3957              	HAL_SD_ErrorCallback:
+ 3958              	.LVL322:
+ 3959              	.LFB158:
+1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+ 3960              		.loc 1 1727 1 is_stmt 1 view -0
+ 3961              		.cfi_startproc
+ 3962              		@ args = 0, pretend = 0, frame = 0
+ 3963              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3964              		@ link register save eliminated.
+1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3965              		.loc 1 1729 3 view .LVU1415
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3966              		.loc 1 1734 1 is_stmt 0 view .LVU1416
+ 3967 0000 7047     		bx	lr
+ARM GAS  /tmp/ccQEYyKb.s 			page 150
+
+
+ 3968              		.cfi_endproc
+ 3969              	.LFE158:
+ 3971              		.section	.text.SD_DMAReceiveCplt,"ax",%progbits
+ 3972              		.align	1
+ 3973              		.syntax unified
+ 3974              		.thumb
+ 3975              		.thumb_func
+ 3976              		.fpu fpv5-d16
+ 3978              	SD_DMAReceiveCplt:
+ 3979              	.LVL323:
+ 3980              	.LFB169:
+2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ 3981              		.loc 1 2454 1 is_stmt 1 view -0
+ 3982              		.cfi_startproc
+ 3983              		@ args = 0, pretend = 0, frame = 0
+ 3984              		@ frame_needed = 0, uses_anonymous_args = 0
+2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ 3985              		.loc 1 2454 1 is_stmt 0 view .LVU1418
+ 3986 0000 10B5     		push	{r4, lr}
+ 3987              	.LCFI50:
+ 3988              		.cfi_def_cfa_offset 8
+ 3989              		.cfi_offset 4, -8
+ 3990              		.cfi_offset 14, -4
+2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 3991              		.loc 1 2455 3 is_stmt 1 view .LVU1419
+2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 3992              		.loc 1 2455 21 is_stmt 0 view .LVU1420
+ 3993 0002 846B     		ldr	r4, [r0, #56]
+ 3994              	.LVL324:
+2456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 3995              		.loc 1 2456 3 is_stmt 1 view .LVU1421
+2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3996              		.loc 1 2459 3 view .LVU1422
+2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3997              		.loc 1 2459 9 is_stmt 0 view .LVU1423
+ 3998 0004 236B     		ldr	r3, [r4, #48]
+2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 3999              		.loc 1 2459 5 view .LVU1424
+ 4000 0006 822B     		cmp	r3, #130
+ 4001 0008 11D0     		beq	.L245
+ 4002              	.LVL325:
+ 4003              	.L243:
+2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4004              		.loc 1 2475 3 is_stmt 1 view .LVU1425
+2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4005              		.loc 1 2475 6 is_stmt 0 view .LVU1426
+ 4006 000a 2268     		ldr	r2, [r4]
+2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4007              		.loc 1 2475 24 view .LVU1427
+ 4008 000c D36A     		ldr	r3, [r2, #44]
+ 4009 000e 23F00803 		bic	r3, r3, #8
+ 4010 0012 D362     		str	r3, [r2, #44]
+2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4011              		.loc 1 2478 3 is_stmt 1 view .LVU1428
+ 4012 0014 2368     		ldr	r3, [r4]
+ 4013 0016 40F23A52 		movw	r2, #1338
+ 4014 001a 9A63     		str	r2, [r3, #56]
+ARM GAS  /tmp/ccQEYyKb.s 			page 151
+
+
+2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Context = SD_CONTEXT_NONE;
+ 4015              		.loc 1 2480 3 view .LVU1429
+2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Context = SD_CONTEXT_NONE;
+ 4016              		.loc 1 2480 14 is_stmt 0 view .LVU1430
+ 4017 001c 0123     		movs	r3, #1
+ 4018 001e 84F83430 		strb	r3, [r4, #52]
+2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4019              		.loc 1 2481 3 is_stmt 1 view .LVU1431
+2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4020              		.loc 1 2481 16 is_stmt 0 view .LVU1432
+ 4021 0022 0023     		movs	r3, #0
+ 4022 0024 2363     		str	r3, [r4, #48]
+2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+ 4023              		.loc 1 2486 3 is_stmt 1 view .LVU1433
+ 4024 0026 2046     		mov	r0, r4
+ 4025 0028 FFF7FEFF 		bl	HAL_SD_RxCpltCallback
+ 4026              	.LVL326:
+2488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4027              		.loc 1 2488 1 is_stmt 0 view .LVU1434
+ 4028 002c 10BD     		pop	{r4, pc}
+ 4029              	.LVL327:
+ 4030              	.L245:
+2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 4031              		.loc 1 2461 5 is_stmt 1 view .LVU1435
+2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 4032              		.loc 1 2461 18 is_stmt 0 view .LVU1436
+ 4033 002e 2068     		ldr	r0, [r4]
+ 4034              	.LVL328:
+2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 4035              		.loc 1 2461 18 view .LVU1437
+ 4036 0030 FFF7FEFF 		bl	SDMMC_CmdStopTransfer
+ 4037              	.LVL329:
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 4038              		.loc 1 2462 5 is_stmt 1 view .LVU1438
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 4039              		.loc 1 2462 7 is_stmt 0 view .LVU1439
+ 4040 0034 0346     		mov	r3, r0
+ 4041 0036 0028     		cmp	r0, #0
+ 4042 0038 E7D0     		beq	.L243
+2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ 4043              		.loc 1 2464 7 is_stmt 1 view .LVU1440
+2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ 4044              		.loc 1 2464 22 is_stmt 0 view .LVU1441
+ 4045 003a A26B     		ldr	r2, [r4, #56]
+ 4046 003c 1343     		orrs	r3, r3, r2
+ 4047 003e A363     		str	r3, [r4, #56]
+2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+ 4048              		.loc 1 2468 7 is_stmt 1 view .LVU1442
+ 4049 0040 2046     		mov	r0, r4
+ 4050              	.LVL330:
+2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+ 4051              		.loc 1 2468 7 is_stmt 0 view .LVU1443
+ 4052 0042 FFF7FEFF 		bl	HAL_SD_ErrorCallback
+ 4053              	.LVL331:
+ 4054 0046 E0E7     		b	.L243
+ 4055              		.cfi_endproc
+ 4056              	.LFE169:
+ARM GAS  /tmp/ccQEYyKb.s 			page 152
+
+
+ 4058              		.section	.text.HAL_SD_AbortCallback,"ax",%progbits
+ 4059              		.align	1
+ 4060              		.weak	HAL_SD_AbortCallback
+ 4061              		.syntax unified
+ 4062              		.thumb
+ 4063              		.thumb_func
+ 4064              		.fpu fpv5-d16
+ 4066              	HAL_SD_AbortCallback:
+ 4067              	.LVL332:
+ 4068              	.LFB159:
+1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Prevent unused argument(s) compilation warning */
+ 4069              		.loc 1 1742 1 is_stmt 1 view -0
+ 4070              		.cfi_startproc
+ 4071              		@ args = 0, pretend = 0, frame = 0
+ 4072              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4073              		@ link register save eliminated.
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4074              		.loc 1 1744 3 view .LVU1445
+1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4075              		.loc 1 1749 1 is_stmt 0 view .LVU1446
+ 4076 0000 7047     		bx	lr
+ 4077              		.cfi_endproc
+ 4078              	.LFE159:
+ 4080              		.section	.text.HAL_SD_GetCardCID,"ax",%progbits
+ 4081              		.align	1
+ 4082              		.global	HAL_SD_GetCardCID
+ 4083              		.syntax unified
+ 4084              		.thumb
+ 4085              		.thumb_func
+ 4086              		.fpu fpv5-d16
+ 4088              	HAL_SD_GetCardCID:
+ 4089              	.LVL333:
+ 4090              	.LFB160:
+1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
+ 4091              		.loc 1 1953 1 is_stmt 1 view -0
+ 4092              		.cfi_startproc
+ 4093              		@ args = 0, pretend = 0, frame = 0
+ 4094              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4095              		@ link register save eliminated.
+1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4096              		.loc 1 1954 3 view .LVU1448
+1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4097              		.loc 1 1954 26 is_stmt 0 view .LVU1449
+ 4098 0000 90F87730 		ldrb	r3, [r0, #119]	@ zero_extendqisi2
+1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4099              		.loc 1 1954 24 view .LVU1450
+ 4100 0004 0B70     		strb	r3, [r1]
+1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4101              		.loc 1 1956 3 is_stmt 1 view .LVU1451
+1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4102              		.loc 1 1956 43 is_stmt 0 view .LVU1452
+ 4103 0006 436F     		ldr	r3, [r0, #116]
+1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4104              		.loc 1 1956 23 view .LVU1453
+ 4105 0008 C3F30F23 		ubfx	r3, r3, #8, #16
+1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4106              		.loc 1 1956 21 view .LVU1454
+ARM GAS  /tmp/ccQEYyKb.s 			page 153
+
+
+ 4107 000c 4B80     		strh	r3, [r1, #2]	@ movhi
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4108              		.loc 1 1958 3 is_stmt 1 view .LVU1455
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4109              		.loc 1 1958 32 is_stmt 0 view .LVU1456
+ 4110 000e 426F     		ldr	r2, [r0, #116]
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4111              		.loc 1 1958 71 view .LVU1457
+ 4112 0010 836F     		ldr	r3, [r0, #120]
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4113              		.loc 1 1958 90 view .LVU1458
+ 4114 0012 1B0A     		lsrs	r3, r3, #8
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4115              		.loc 1 1958 59 view .LVU1459
+ 4116 0014 43EA0263 		orr	r3, r3, r2, lsl #24
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4117              		.loc 1 1958 19 view .LVU1460
+ 4118 0018 4B60     		str	r3, [r1, #4]
+1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4119              		.loc 1 1960 3 is_stmt 1 view .LVU1461
+1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4120              		.loc 1 1960 21 is_stmt 0 view .LVU1462
+ 4121 001a 90F87830 		ldrb	r3, [r0, #120]	@ zero_extendqisi2
+1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4122              		.loc 1 1960 19 view .LVU1463
+ 4123 001e 0B72     		strb	r3, [r1, #8]
+1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4124              		.loc 1 1962 3 is_stmt 1 view .LVU1464
+1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4125              		.loc 1 1962 19 is_stmt 0 view .LVU1465
+ 4126 0020 90F87F30 		ldrb	r3, [r0, #127]	@ zero_extendqisi2
+1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4127              		.loc 1 1962 17 view .LVU1466
+ 4128 0024 4B72     		strb	r3, [r1, #9]
+1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4129              		.loc 1 1964 3 is_stmt 1 view .LVU1467
+1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4130              		.loc 1 1964 29 is_stmt 0 view .LVU1468
+ 4131 0026 C26F     		ldr	r2, [r0, #124]
+1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4132              		.loc 1 1964 86 view .LVU1469
+ 4133 0028 90F88330 		ldrb	r3, [r0, #131]	@ zero_extendqisi2
+1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4134              		.loc 1 1964 55 view .LVU1470
+ 4135 002c 43EA0223 		orr	r3, r3, r2, lsl #8
+1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4136              		.loc 1 1964 16 view .LVU1471
+ 4137 0030 CB60     		str	r3, [r1, #12]
+1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4138              		.loc 1 1966 3 is_stmt 1 view .LVU1472
+1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4139              		.loc 1 1966 40 is_stmt 0 view .LVU1473
+ 4140 0032 D0F88030 		ldr	r3, [r0, #128]
+1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4141              		.loc 1 1966 21 view .LVU1474
+ 4142 0036 C3F30353 		ubfx	r3, r3, #20, #4
+1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 154
+
+
+ 4143              		.loc 1 1966 19 view .LVU1475
+ 4144 003a 0B74     		strb	r3, [r1, #16]
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4145              		.loc 1 1968 3 is_stmt 1 view .LVU1476
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4146              		.loc 1 1968 44 is_stmt 0 view .LVU1477
+ 4147 003c D0F88030 		ldr	r3, [r0, #128]
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4148              		.loc 1 1968 24 view .LVU1478
+ 4149 0040 C3F30B23 		ubfx	r3, r3, #8, #12
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4150              		.loc 1 1968 22 view .LVU1479
+ 4151 0044 4B82     		strh	r3, [r1, #18]	@ movhi
+1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4152              		.loc 1 1970 3 is_stmt 1 view .LVU1480
+1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4153              		.loc 1 1970 38 is_stmt 0 view .LVU1481
+ 4154 0046 D0F88030 		ldr	r3, [r0, #128]
+1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4155              		.loc 1 1970 19 view .LVU1482
+ 4156 004a C3F34603 		ubfx	r3, r3, #1, #7
+1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4157              		.loc 1 1970 17 view .LVU1483
+ 4158 004e 0B75     		strb	r3, [r1, #20]
+1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4159              		.loc 1 1972 3 is_stmt 1 view .LVU1484
+1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4160              		.loc 1 1972 19 is_stmt 0 view .LVU1485
+ 4161 0050 0123     		movs	r3, #1
+ 4162 0052 4B75     		strb	r3, [r1, #21]
+1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 4163              		.loc 1 1974 3 is_stmt 1 view .LVU1486
+1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4164              		.loc 1 1975 1 is_stmt 0 view .LVU1487
+ 4165 0054 0020     		movs	r0, #0
+ 4166              	.LVL334:
+1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4167              		.loc 1 1975 1 view .LVU1488
+ 4168 0056 7047     		bx	lr
+ 4169              		.cfi_endproc
+ 4170              	.LFE160:
+ 4172              		.section	.text.HAL_SD_GetCardCSD,"ax",%progbits
+ 4173              		.align	1
+ 4174              		.global	HAL_SD_GetCardCSD
+ 4175              		.syntax unified
+ 4176              		.thumb
+ 4177              		.thumb_func
+ 4178              		.fpu fpv5-d16
+ 4180              	HAL_SD_GetCardCSD:
+ 4181              	.LVL335:
+ 4182              	.LFB161:
+1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
+ 4183              		.loc 1 1986 1 is_stmt 1 view -0
+ 4184              		.cfi_startproc
+ 4185              		@ args = 0, pretend = 0, frame = 0
+ 4186              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4187              		@ link register save eliminated.
+ARM GAS  /tmp/ccQEYyKb.s 			page 155
+
+
+1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4188              		.loc 1 1987 3 view .LVU1490
+1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4189              		.loc 1 1987 40 is_stmt 0 view .LVU1491
+ 4190 0000 436E     		ldr	r3, [r0, #100]
+1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4191              		.loc 1 1987 21 view .LVU1492
+ 4192 0002 9B0F     		lsrs	r3, r3, #30
+1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4193              		.loc 1 1987 19 view .LVU1493
+ 4194 0004 0B70     		strb	r3, [r1]
+1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4195              		.loc 1 1989 3 is_stmt 1 view .LVU1494
+1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4196              		.loc 1 1989 45 is_stmt 0 view .LVU1495
+ 4197 0006 436E     		ldr	r3, [r0, #100]
+1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4198              		.loc 1 1989 26 view .LVU1496
+ 4199 0008 C3F38363 		ubfx	r3, r3, #26, #4
+1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4200              		.loc 1 1989 24 view .LVU1497
+ 4201 000c 4B70     		strb	r3, [r1, #1]
+1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4202              		.loc 1 1991 3 is_stmt 1 view .LVU1498
+1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4203              		.loc 1 1991 59 is_stmt 0 view .LVU1499
+ 4204 000e 90F86730 		ldrb	r3, [r0, #103]	@ zero_extendqisi2
+1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4205              		.loc 1 1991 21 view .LVU1500
+ 4206 0012 03F00303 		and	r3, r3, #3
+1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4207              		.loc 1 1991 19 view .LVU1501
+ 4208 0016 8B70     		strb	r3, [r1, #2]
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4209              		.loc 1 1993 3 is_stmt 1 view .LVU1502
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4210              		.loc 1 1993 16 is_stmt 0 view .LVU1503
+ 4211 0018 90F86630 		ldrb	r3, [r0, #102]	@ zero_extendqisi2
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4212              		.loc 1 1993 14 view .LVU1504
+ 4213 001c CB70     		strb	r3, [r1, #3]
+1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4214              		.loc 1 1995 3 is_stmt 1 view .LVU1505
+1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4215              		.loc 1 1995 16 is_stmt 0 view .LVU1506
+ 4216 001e 90F86530 		ldrb	r3, [r0, #101]	@ zero_extendqisi2
+1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4217              		.loc 1 1995 14 view .LVU1507
+ 4218 0022 0B71     		strb	r3, [r1, #4]
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4219              		.loc 1 1997 3 is_stmt 1 view .LVU1508
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4220              		.loc 1 1997 25 is_stmt 0 view .LVU1509
+ 4221 0024 90F86430 		ldrb	r3, [r0, #100]	@ zero_extendqisi2
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4222              		.loc 1 1997 23 view .LVU1510
+ 4223 0028 4B71     		strb	r3, [r1, #5]
+ARM GAS  /tmp/ccQEYyKb.s 			page 156
+
+
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4224              		.loc 1 1999 3 is_stmt 1 view .LVU1511
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4225              		.loc 1 1999 47 is_stmt 0 view .LVU1512
+ 4226 002a 836E     		ldr	r3, [r0, #104]
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4227              		.loc 1 1999 27 view .LVU1513
+ 4228 002c 1B0D     		lsrs	r3, r3, #20
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4229              		.loc 1 1999 25 view .LVU1514
+ 4230 002e CB80     		strh	r3, [r1, #6]	@ movhi
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4231              		.loc 1 2001 3 is_stmt 1 view .LVU1515
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4232              		.loc 1 2001 60 is_stmt 0 view .LVU1516
+ 4233 0030 B0F86A30 		ldrh	r3, [r0, #106]
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4234              		.loc 1 2001 22 view .LVU1517
+ 4235 0034 03F00F03 		and	r3, r3, #15
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4236              		.loc 1 2001 20 view .LVU1518
+ 4237 0038 0B72     		strb	r3, [r1, #8]
+2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4238              		.loc 1 2003 3 is_stmt 1 view .LVU1519
+2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4239              		.loc 1 2003 46 is_stmt 0 view .LVU1520
+ 4240 003a 836E     		ldr	r3, [r0, #104]
+2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4241              		.loc 1 2003 27 view .LVU1521
+ 4242 003c C3F3C033 		ubfx	r3, r3, #15, #1
+2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4243              		.loc 1 2003 25 view .LVU1522
+ 4244 0040 4B72     		strb	r3, [r1, #9]
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4245              		.loc 1 2005 3 is_stmt 1 view .LVU1523
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4246              		.loc 1 2005 46 is_stmt 0 view .LVU1524
+ 4247 0042 836E     		ldr	r3, [r0, #104]
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4248              		.loc 1 2005 27 view .LVU1525
+ 4249 0044 C3F38033 		ubfx	r3, r3, #14, #1
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4250              		.loc 1 2005 25 view .LVU1526
+ 4251 0048 8B72     		strb	r3, [r1, #10]
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4252              		.loc 1 2007 3 is_stmt 1 view .LVU1527
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4253              		.loc 1 2007 46 is_stmt 0 view .LVU1528
+ 4254 004a 836E     		ldr	r3, [r0, #104]
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4255              		.loc 1 2007 27 view .LVU1529
+ 4256 004c C3F34033 		ubfx	r3, r3, #13, #1
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4257              		.loc 1 2007 25 view .LVU1530
+ 4258 0050 CB72     		strb	r3, [r1, #11]
+2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4259              		.loc 1 2009 3 is_stmt 1 view .LVU1531
+ARM GAS  /tmp/ccQEYyKb.s 			page 157
+
+
+2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4260              		.loc 1 2009 38 is_stmt 0 view .LVU1532
+ 4261 0052 836E     		ldr	r3, [r0, #104]
+2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4262              		.loc 1 2009 19 view .LVU1533
+ 4263 0054 C3F30033 		ubfx	r3, r3, #12, #1
+2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4264              		.loc 1 2009 17 view .LVU1534
+ 4265 0058 0B73     		strb	r3, [r1, #12]
+2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4266              		.loc 1 2011 3 is_stmt 1 view .LVU1535
+2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4267              		.loc 1 2011 19 is_stmt 0 view .LVU1536
+ 4268 005a 0023     		movs	r3, #0
+ 4269 005c 4B73     		strb	r3, [r1, #13]
+2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4270              		.loc 1 2013 3 is_stmt 1 view .LVU1537
+2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4271              		.loc 1 2013 17 is_stmt 0 view .LVU1538
+ 4272 005e 436C     		ldr	r3, [r0, #68]
+2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4273              		.loc 1 2013 5 view .LVU1539
+ 4274 0060 002B     		cmp	r3, #0
+ 4275 0062 40F08680 		bne	.L249
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4276              		.loc 1 2015 5 is_stmt 1 view .LVU1540
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4277              		.loc 1 2015 35 is_stmt 0 view .LVU1541
+ 4278 0066 826E     		ldr	r2, [r0, #104]
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4279              		.loc 1 2015 54 view .LVU1542
+ 4280 0068 40F6FC73 		movw	r3, #4092
+ 4281 006c 03EA8203 		and	r3, r3, r2, lsl #2
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4282              		.loc 1 2015 73 view .LVU1543
+ 4283 0070 C26E     		ldr	r2, [r0, #108]
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4284              		.loc 1 2015 61 view .LVU1544
+ 4285 0072 43EA9273 		orr	r3, r3, r2, lsr #30
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4286              		.loc 1 2015 22 view .LVU1545
+ 4287 0076 0B61     		str	r3, [r1, #16]
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4288              		.loc 1 2017 5 is_stmt 1 view .LVU1546
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4289              		.loc 1 2017 51 is_stmt 0 view .LVU1547
+ 4290 0078 C36E     		ldr	r3, [r0, #108]
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4291              		.loc 1 2017 32 view .LVU1548
+ 4292 007a C3F3C263 		ubfx	r3, r3, #27, #3
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4293              		.loc 1 2017 30 view .LVU1549
+ 4294 007e 0B75     		strb	r3, [r1, #20]
+2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4295              		.loc 1 2019 5 is_stmt 1 view .LVU1550
+2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4296              		.loc 1 2019 70 is_stmt 0 view .LVU1551
+ARM GAS  /tmp/ccQEYyKb.s 			page 158
+
+
+ 4297 0080 90F86F30 		ldrb	r3, [r0, #111]	@ zero_extendqisi2
+2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4298              		.loc 1 2019 32 view .LVU1552
+ 4299 0084 03F00703 		and	r3, r3, #7
+2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4300              		.loc 1 2019 30 view .LVU1553
+ 4301 0088 4B75     		strb	r3, [r1, #21]
+2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4302              		.loc 1 2021 5 is_stmt 1 view .LVU1554
+2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4303              		.loc 1 2021 51 is_stmt 0 view .LVU1555
+ 4304 008a C36E     		ldr	r3, [r0, #108]
+2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4305              		.loc 1 2021 32 view .LVU1556
+ 4306 008c C3F34253 		ubfx	r3, r3, #21, #3
+2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4307              		.loc 1 2021 30 view .LVU1557
+ 4308 0090 8B75     		strb	r3, [r1, #22]
+2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4309              		.loc 1 2023 5 is_stmt 1 view .LVU1558
+2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4310              		.loc 1 2023 51 is_stmt 0 view .LVU1559
+ 4311 0092 C36E     		ldr	r3, [r0, #108]
+2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4312              		.loc 1 2023 32 view .LVU1560
+ 4313 0094 C3F38243 		ubfx	r3, r3, #18, #3
+2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4314              		.loc 1 2023 30 view .LVU1561
+ 4315 0098 CB75     		strb	r3, [r1, #23]
+2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4316              		.loc 1 2025 5 is_stmt 1 view .LVU1562
+2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4317              		.loc 1 2025 46 is_stmt 0 view .LVU1563
+ 4318 009a C36E     		ldr	r3, [r0, #108]
+2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4319              		.loc 1 2025 27 view .LVU1564
+ 4320 009c C3F3C233 		ubfx	r3, r3, #15, #3
+2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4321              		.loc 1 2025 25 view .LVU1565
+ 4322 00a0 0B76     		strb	r3, [r1, #24]
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+ 4323              		.loc 1 2027 5 is_stmt 1 view .LVU1566
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+ 4324              		.loc 1 2027 34 is_stmt 0 view .LVU1567
+ 4325 00a2 0B69     		ldr	r3, [r1, #16]
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+ 4326              		.loc 1 2027 47 view .LVU1568
+ 4327 00a4 0133     		adds	r3, r3, #1
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+ 4328              		.loc 1 2027 27 view .LVU1569
+ 4329 00a6 4365     		str	r3, [r0, #84]
+2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+ 4330              		.loc 1 2028 5 is_stmt 1 view .LVU1570
+2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+ 4331              		.loc 1 2028 43 is_stmt 0 view .LVU1571
+ 4332 00a8 0A7E     		ldrb	r2, [r1, #24]	@ zero_extendqisi2
+2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+ARM GAS  /tmp/ccQEYyKb.s 			page 159
+
+
+ 4333              		.loc 1 2028 59 view .LVU1572
+ 4334 00aa 02F00702 		and	r2, r2, #7
+2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+ 4335              		.loc 1 2028 68 view .LVU1573
+ 4336 00ae 0232     		adds	r2, r2, #2
+2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+ 4337              		.loc 1 2028 26 view .LVU1574
+ 4338 00b0 9340     		lsls	r3, r3, r2
+ 4339 00b2 4365     		str	r3, [r0, #84]
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4340              		.loc 1 2029 5 is_stmt 1 view .LVU1575
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4341              		.loc 1 2029 42 is_stmt 0 view .LVU1576
+ 4342 00b4 0A7A     		ldrb	r2, [r1, #8]	@ zero_extendqisi2
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4343              		.loc 1 2029 55 view .LVU1577
+ 4344 00b6 02F00F0C 		and	ip, r2, #15
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4345              		.loc 1 2029 34 view .LVU1578
+ 4346 00ba 0122     		movs	r2, #1
+ 4347 00bc 02FA0CF2 		lsl	r2, r2, ip
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4348              		.loc 1 2029 27 view .LVU1579
+ 4349 00c0 8265     		str	r2, [r0, #88]
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockSize = 512U;
+ 4350              		.loc 1 2031 5 is_stmt 1 view .LVU1580
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockSize = 512U;
+ 4351              		.loc 1 2031 82 is_stmt 0 view .LVU1581
+ 4352 00c2 520A     		lsrs	r2, r2, #9
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockSize = 512U;
+ 4353              		.loc 1 2031 55 view .LVU1582
+ 4354 00c4 02FB03F3 		mul	r3, r2, r3
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockSize = 512U;
+ 4355              		.loc 1 2031 29 view .LVU1583
+ 4356 00c8 C365     		str	r3, [r0, #92]
+2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4357              		.loc 1 2032 5 is_stmt 1 view .LVU1584
+2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4358              		.loc 1 2032 30 is_stmt 0 view .LVU1585
+ 4359 00ca 4FF40073 		mov	r3, #512
+ 4360 00ce 0366     		str	r3, [r0, #96]
+ 4361              	.L250:
+2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4362              		.loc 1 2053 3 is_stmt 1 view .LVU1586
+2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4363              		.loc 1 2053 42 is_stmt 0 view .LVU1587
+ 4364 00d0 C36E     		ldr	r3, [r0, #108]
+2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4365              		.loc 1 2053 23 view .LVU1588
+ 4366 00d2 C3F38033 		ubfx	r3, r3, #14, #1
+2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4367              		.loc 1 2053 21 view .LVU1589
+ 4368 00d6 4B76     		strb	r3, [r1, #25]
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4369              		.loc 1 2055 3 is_stmt 1 view .LVU1590
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4370              		.loc 1 2055 41 is_stmt 0 view .LVU1591
+ARM GAS  /tmp/ccQEYyKb.s 			page 160
+
+
+ 4371 00d8 C36E     		ldr	r3, [r0, #108]
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4372              		.loc 1 2055 22 view .LVU1592
+ 4373 00da C3F3C613 		ubfx	r3, r3, #7, #7
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4374              		.loc 1 2055 20 view .LVU1593
+ 4375 00de 8B76     		strb	r3, [r1, #26]
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4376              		.loc 1 2057 3 is_stmt 1 view .LVU1594
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4377              		.loc 1 2057 45 is_stmt 0 view .LVU1595
+ 4378 00e0 C36E     		ldr	r3, [r0, #108]
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4379              		.loc 1 2057 27 view .LVU1596
+ 4380 00e2 03F07F03 		and	r3, r3, #127
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4381              		.loc 1 2057 25 view .LVU1597
+ 4382 00e6 CB76     		strb	r3, [r1, #27]
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4383              		.loc 1 2059 3 is_stmt 1 view .LVU1598
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4384              		.loc 1 2059 48 is_stmt 0 view .LVU1599
+ 4385 00e8 036F     		ldr	r3, [r0, #112]
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4386              		.loc 1 2059 29 view .LVU1600
+ 4387 00ea DB0F     		lsrs	r3, r3, #31
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4388              		.loc 1 2059 27 view .LVU1601
+ 4389 00ec 0B77     		strb	r3, [r1, #28]
+2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4390              		.loc 1 2061 3 is_stmt 1 view .LVU1602
+2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4391              		.loc 1 2061 41 is_stmt 0 view .LVU1603
+ 4392 00ee 036F     		ldr	r3, [r0, #112]
+2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4393              		.loc 1 2061 22 view .LVU1604
+ 4394 00f0 C3F34173 		ubfx	r3, r3, #29, #2
+2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4395              		.loc 1 2061 20 view .LVU1605
+ 4396 00f4 4B77     		strb	r3, [r1, #29]
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4397              		.loc 1 2063 3 is_stmt 1 view .LVU1606
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4398              		.loc 1 2063 42 is_stmt 0 view .LVU1607
+ 4399 00f6 036F     		ldr	r3, [r0, #112]
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4400              		.loc 1 2063 23 view .LVU1608
+ 4401 00f8 C3F38263 		ubfx	r3, r3, #26, #3
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4402              		.loc 1 2063 21 view .LVU1609
+ 4403 00fc 8B77     		strb	r3, [r1, #30]
+2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4404              		.loc 1 2065 3 is_stmt 1 view .LVU1610
+2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4405              		.loc 1 2065 43 is_stmt 0 view .LVU1611
+ 4406 00fe 036F     		ldr	r3, [r0, #112]
+2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 161
+
+
+ 4407              		.loc 1 2065 24 view .LVU1612
+ 4408 0100 C3F38353 		ubfx	r3, r3, #22, #4
+2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4409              		.loc 1 2065 22 view .LVU1613
+ 4410 0104 CB77     		strb	r3, [r1, #31]
+2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4411              		.loc 1 2067 3 is_stmt 1 view .LVU1614
+2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4412              		.loc 1 2067 50 is_stmt 0 view .LVU1615
+ 4413 0106 036F     		ldr	r3, [r0, #112]
+2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4414              		.loc 1 2067 31 view .LVU1616
+ 4415 0108 C3F34053 		ubfx	r3, r3, #21, #1
+2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4416              		.loc 1 2067 29 view .LVU1617
+ 4417 010c 81F82030 		strb	r3, [r1, #32]
+2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4418              		.loc 1 2069 3 is_stmt 1 view .LVU1618
+2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4419              		.loc 1 2069 19 is_stmt 0 view .LVU1619
+ 4420 0110 0023     		movs	r3, #0
+ 4421 0112 81F82130 		strb	r3, [r1, #33]
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4422              		.loc 1 2071 3 is_stmt 1 view .LVU1620
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4423              		.loc 1 2071 69 is_stmt 0 view .LVU1621
+ 4424 0116 B0F87220 		ldrh	r2, [r0, #114]
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4425              		.loc 1 2071 31 view .LVU1622
+ 4426 011a 02F00102 		and	r2, r2, #1
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4427              		.loc 1 2071 29 view .LVU1623
+ 4428 011e 81F82220 		strb	r2, [r1, #34]
+2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4429              		.loc 1 2073 3 is_stmt 1 view .LVU1624
+2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4430              		.loc 1 2073 46 is_stmt 0 view .LVU1625
+ 4431 0122 026F     		ldr	r2, [r0, #112]
+2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4432              		.loc 1 2073 27 view .LVU1626
+ 4433 0124 C2F3C032 		ubfx	r2, r2, #15, #1
+2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4434              		.loc 1 2073 25 view .LVU1627
+ 4435 0128 81F82320 		strb	r2, [r1, #35]
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4436              		.loc 1 2075 3 is_stmt 1 view .LVU1628
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4437              		.loc 1 2075 39 is_stmt 0 view .LVU1629
+ 4438 012c 026F     		ldr	r2, [r0, #112]
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4439              		.loc 1 2075 20 view .LVU1630
+ 4440 012e C2F38032 		ubfx	r2, r2, #14, #1
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4441              		.loc 1 2075 18 view .LVU1631
+ 4442 0132 81F82420 		strb	r2, [r1, #36]
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4443              		.loc 1 2077 3 is_stmt 1 view .LVU1632
+ARM GAS  /tmp/ccQEYyKb.s 			page 162
+
+
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4444              		.loc 1 2077 44 is_stmt 0 view .LVU1633
+ 4445 0136 026F     		ldr	r2, [r0, #112]
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4446              		.loc 1 2077 25 view .LVU1634
+ 4447 0138 C2F34032 		ubfx	r2, r2, #13, #1
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4448              		.loc 1 2077 23 view .LVU1635
+ 4449 013c 81F82520 		strb	r2, [r1, #37]
+2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4450              		.loc 1 2079 3 is_stmt 1 view .LVU1636
+2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4451              		.loc 1 2079 44 is_stmt 0 view .LVU1637
+ 4452 0140 026F     		ldr	r2, [r0, #112]
+2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4453              		.loc 1 2079 25 view .LVU1638
+ 4454 0142 C2F30032 		ubfx	r2, r2, #12, #1
+2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4455              		.loc 1 2079 23 view .LVU1639
+ 4456 0146 81F82620 		strb	r2, [r1, #38]
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4457              		.loc 1 2081 3 is_stmt 1 view .LVU1640
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4458              		.loc 1 2081 41 is_stmt 0 view .LVU1641
+ 4459 014a 026F     		ldr	r2, [r0, #112]
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4460              		.loc 1 2081 22 view .LVU1642
+ 4461 014c C2F38122 		ubfx	r2, r2, #10, #2
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4462              		.loc 1 2081 20 view .LVU1643
+ 4463 0150 81F82720 		strb	r2, [r1, #39]
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4464              		.loc 1 2083 3 is_stmt 1 view .LVU1644
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4465              		.loc 1 2083 33 is_stmt 0 view .LVU1645
+ 4466 0154 026F     		ldr	r2, [r0, #112]
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4467              		.loc 1 2083 14 view .LVU1646
+ 4468 0156 C2F30122 		ubfx	r2, r2, #8, #2
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4469              		.loc 1 2083 12 view .LVU1647
+ 4470 015a 81F82820 		strb	r2, [r1, #40]
+2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4471              		.loc 1 2085 3 is_stmt 1 view .LVU1648
+2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4472              		.loc 1 2085 38 is_stmt 0 view .LVU1649
+ 4473 015e 026F     		ldr	r2, [r0, #112]
+2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4474              		.loc 1 2085 19 view .LVU1650
+ 4475 0160 C2F34602 		ubfx	r2, r2, #1, #7
+2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4476              		.loc 1 2085 17 view .LVU1651
+ 4477 0164 81F82920 		strb	r2, [r1, #41]
+2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4478              		.loc 1 2087 3 is_stmt 1 view .LVU1652
+2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4479              		.loc 1 2087 19 is_stmt 0 view .LVU1653
+ARM GAS  /tmp/ccQEYyKb.s 			page 163
+
+
+ 4480 0168 0122     		movs	r2, #1
+ 4481 016a 81F82A20 		strb	r2, [r1, #42]
+2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 4482              		.loc 1 2089 3 is_stmt 1 view .LVU1654
+2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 4483              		.loc 1 2089 10 is_stmt 0 view .LVU1655
+ 4484 016e 1846     		mov	r0, r3
+ 4485              	.LVL336:
+2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4486              		.loc 1 2090 1 view .LVU1656
+ 4487 0170 7047     		bx	lr
+ 4488              	.LVL337:
+ 4489              	.L249:
+2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4490              		.loc 1 2034 8 is_stmt 1 view .LVU1657
+2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4491              		.loc 1 2034 10 is_stmt 0 view .LVU1658
+ 4492 0172 012B     		cmp	r3, #1
+ 4493 0174 11D1     		bne	.L251
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4494              		.loc 1 2037 5 is_stmt 1 view .LVU1659
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4495              		.loc 1 2037 35 is_stmt 0 view .LVU1660
+ 4496 0176 836E     		ldr	r3, [r0, #104]
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4497              		.loc 1 2037 54 view .LVU1661
+ 4498 0178 1B04     		lsls	r3, r3, #16
+ 4499 017a 03F47C13 		and	r3, r3, #4128768
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4500              		.loc 1 2037 93 view .LVU1662
+ 4501 017e B0F86E20 		ldrh	r2, [r0, #110]
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4502              		.loc 1 2037 62 view .LVU1663
+ 4503 0182 1343     		orrs	r3, r3, r2
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4504              		.loc 1 2037 22 view .LVU1664
+ 4505 0184 0B61     		str	r3, [r1, #16]
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+ 4506              		.loc 1 2039 5 is_stmt 1 view .LVU1665
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+ 4507              		.loc 1 2039 34 is_stmt 0 view .LVU1666
+ 4508 0186 0B69     		ldr	r3, [r1, #16]
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+ 4509              		.loc 1 2039 47 view .LVU1667
+ 4510 0188 0133     		adds	r3, r3, #1
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+ 4511              		.loc 1 2039 53 view .LVU1668
+ 4512 018a 9B02     		lsls	r3, r3, #10
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+ 4513              		.loc 1 2039 26 view .LVU1669
+ 4514 018c 4365     		str	r3, [r0, #84]
+2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockSize = 512U;
+ 4515              		.loc 1 2040 5 is_stmt 1 view .LVU1670
+2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.BlockSize = 512U;
+ 4516              		.loc 1 2040 29 is_stmt 0 view .LVU1671
+ 4517 018e C365     		str	r3, [r0, #92]
+2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
+ARM GAS  /tmp/ccQEYyKb.s 			page 164
+
+
+ 4518              		.loc 1 2041 5 is_stmt 1 view .LVU1672
+2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
+ 4519              		.loc 1 2041 27 is_stmt 0 view .LVU1673
+ 4520 0190 4FF40073 		mov	r3, #512
+ 4521 0194 8365     		str	r3, [r0, #88]
+2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4522              		.loc 1 2042 5 is_stmt 1 view .LVU1674
+2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4523              		.loc 1 2042 30 is_stmt 0 view .LVU1675
+ 4524 0196 0366     		str	r3, [r0, #96]
+ 4525 0198 9AE7     		b	.L250
+ 4526              	.L251:
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ 4527              		.loc 1 2047 5 is_stmt 1 view .LVU1676
+ 4528 019a 0368     		ldr	r3, [r0]
+ 4529 019c 054A     		ldr	r2, .L253
+ 4530 019e 9A63     		str	r2, [r3, #56]
+2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 4531              		.loc 1 2048 5 view .LVU1677
+2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 4532              		.loc 1 2048 20 is_stmt 0 view .LVU1678
+ 4533 01a0 836B     		ldr	r3, [r0, #56]
+ 4534 01a2 43F08053 		orr	r3, r3, #268435456
+ 4535 01a6 8363     		str	r3, [r0, #56]
+2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 4536              		.loc 1 2049 5 is_stmt 1 view .LVU1679
+2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 4537              		.loc 1 2049 16 is_stmt 0 view .LVU1680
+ 4538 01a8 0123     		movs	r3, #1
+ 4539 01aa 80F83430 		strb	r3, [r0, #52]
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4540              		.loc 1 2050 5 is_stmt 1 view .LVU1681
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4541              		.loc 1 2050 12 is_stmt 0 view .LVU1682
+ 4542 01ae 1846     		mov	r0, r3
+ 4543              	.LVL338:
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4544              		.loc 1 2050 12 view .LVU1683
+ 4545 01b0 7047     		bx	lr
+ 4546              	.L254:
+ 4547 01b2 00BF     		.align	2
+ 4548              	.L253:
+ 4549 01b4 FF054000 		.word	4195839
+ 4550              		.cfi_endproc
+ 4551              	.LFE161:
+ 4553              		.section	.text.SD_InitCard,"ax",%progbits
+ 4554              		.align	1
+ 4555              		.syntax unified
+ 4556              		.thumb
+ 4557              		.thumb_func
+ 4558              		.fpu fpv5-d16
+ 4560              	SD_InitCard:
+ 4561              	.LVL339:
+ 4562              	.LFB173:
+2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardCSDTypeDef CSD;
+ 4563              		.loc 1 2618 1 is_stmt 1 view -0
+ 4564              		.cfi_startproc
+ARM GAS  /tmp/ccQEYyKb.s 			page 165
+
+
+ 4565              		@ args = 0, pretend = 0, frame = 48
+ 4566              		@ frame_needed = 0, uses_anonymous_args = 0
+2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardCSDTypeDef CSD;
+ 4567              		.loc 1 2618 1 is_stmt 0 view .LVU1685
+ 4568 0000 70B5     		push	{r4, r5, r6, lr}
+ 4569              	.LCFI51:
+ 4570              		.cfi_def_cfa_offset 16
+ 4571              		.cfi_offset 4, -16
+ 4572              		.cfi_offset 5, -12
+ 4573              		.cfi_offset 6, -8
+ 4574              		.cfi_offset 14, -4
+ 4575 0002 90B0     		sub	sp, sp, #64
+ 4576              	.LCFI52:
+ 4577              		.cfi_def_cfa_offset 80
+ 4578 0004 0446     		mov	r4, r0
+2619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 4579              		.loc 1 2619 3 is_stmt 1 view .LVU1686
+2620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint16_t sd_rca = 1U;
+ 4580              		.loc 1 2620 3 view .LVU1687
+2621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4581              		.loc 1 2621 3 view .LVU1688
+2621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4582              		.loc 1 2621 12 is_stmt 0 view .LVU1689
+ 4583 0006 0123     		movs	r3, #1
+ 4584 0008 ADF81230 		strh	r3, [sp, #18]	@ movhi
+2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4585              		.loc 1 2624 3 is_stmt 1 view .LVU1690
+2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4586              		.loc 1 2624 6 is_stmt 0 view .LVU1691
+ 4587 000c 0068     		ldr	r0, [r0]
+ 4588              	.LVL340:
+2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4589              		.loc 1 2624 6 view .LVU1692
+ 4590 000e FFF7FEFF 		bl	SDMMC_GetPowerState
+ 4591              	.LVL341:
+2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4592              		.loc 1 2624 5 view .LVU1693
+ 4593 0012 0028     		cmp	r0, #0
+ 4594 0014 6CD0     		beq	.L260
+2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4595              		.loc 1 2630 3 is_stmt 1 view .LVU1694
+2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4596              		.loc 1 2630 17 is_stmt 0 view .LVU1695
+ 4597 0016 636C     		ldr	r3, [r4, #68]
+2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4598              		.loc 1 2630 5 view .LVU1696
+ 4599 0018 032B     		cmp	r3, #3
+ 4600 001a 45D1     		bne	.L263
+ 4601              	.L257:
+2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4602              		.loc 1 2648 3 is_stmt 1 view .LVU1697
+2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4603              		.loc 1 2648 17 is_stmt 0 view .LVU1698
+ 4604 001c 636C     		ldr	r3, [r4, #68]
+2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4605              		.loc 1 2648 5 view .LVU1699
+ 4606 001e 032B     		cmp	r3, #3
+ARM GAS  /tmp/ccQEYyKb.s 			page 166
+
+
+ 4607 0020 5DD1     		bne	.L264
+ 4608              	.L258:
+2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4609              		.loc 1 2658 3 is_stmt 1 view .LVU1700
+2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4610              		.loc 1 2658 17 is_stmt 0 view .LVU1701
+ 4611 0022 636C     		ldr	r3, [r4, #68]
+2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4612              		.loc 1 2658 5 view .LVU1702
+ 4613 0024 032B     		cmp	r3, #3
+ 4614 0026 1DD0     		beq	.L259
+2661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4615              		.loc 1 2661 5 is_stmt 1 view .LVU1703
+2661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4616              		.loc 1 2661 28 is_stmt 0 view .LVU1704
+ 4617 0028 BDF81210 		ldrh	r1, [sp, #18]
+ 4618 002c 2165     		str	r1, [r4, #80]
+2664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 4619              		.loc 1 2664 5 is_stmt 1 view .LVU1705
+2664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 4620              		.loc 1 2664 18 is_stmt 0 view .LVU1706
+ 4621 002e 0904     		lsls	r1, r1, #16
+ 4622 0030 2068     		ldr	r0, [r4]
+ 4623 0032 FFF7FEFF 		bl	SDMMC_CmdSendCSD
+ 4624              	.LVL342:
+2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 4625              		.loc 1 2665 5 is_stmt 1 view .LVU1707
+2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 4626              		.loc 1 2665 7 is_stmt 0 view .LVU1708
+ 4627 0036 0546     		mov	r5, r0
+ 4628 0038 0028     		cmp	r0, #0
+ 4629 003a 5BD1     		bne	.L255
+2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ 4630              		.loc 1 2672 7 is_stmt 1 view .LVU1709
+2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ 4631              		.loc 1 2672 22 is_stmt 0 view .LVU1710
+ 4632 003c 0021     		movs	r1, #0
+ 4633 003e 2068     		ldr	r0, [r4]
+ 4634              	.LVL343:
+2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ 4635              		.loc 1 2672 22 view .LVU1711
+ 4636 0040 FFF7FEFF 		bl	SDMMC_GetResponse
+ 4637              	.LVL344:
+2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ 4638              		.loc 1 2672 20 view .LVU1712
+ 4639 0044 6066     		str	r0, [r4, #100]
+2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+ 4640              		.loc 1 2673 7 is_stmt 1 view .LVU1713
+2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+ 4641              		.loc 1 2673 22 is_stmt 0 view .LVU1714
+ 4642 0046 0421     		movs	r1, #4
+ 4643 0048 2068     		ldr	r0, [r4]
+ 4644 004a FFF7FEFF 		bl	SDMMC_GetResponse
+ 4645              	.LVL345:
+2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+ 4646              		.loc 1 2673 20 view .LVU1715
+ 4647 004e A066     		str	r0, [r4, #104]
+ARM GAS  /tmp/ccQEYyKb.s 			page 167
+
+
+2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+ 4648              		.loc 1 2674 7 is_stmt 1 view .LVU1716
+2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+ 4649              		.loc 1 2674 22 is_stmt 0 view .LVU1717
+ 4650 0050 0821     		movs	r1, #8
+ 4651 0052 2068     		ldr	r0, [r4]
+ 4652 0054 FFF7FEFF 		bl	SDMMC_GetResponse
+ 4653              	.LVL346:
+2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+ 4654              		.loc 1 2674 20 view .LVU1718
+ 4655 0058 E066     		str	r0, [r4, #108]
+2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 4656              		.loc 1 2675 7 is_stmt 1 view .LVU1719
+2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 4657              		.loc 1 2675 22 is_stmt 0 view .LVU1720
+ 4658 005a 0C21     		movs	r1, #12
+ 4659 005c 2068     		ldr	r0, [r4]
+ 4660 005e FFF7FEFF 		bl	SDMMC_GetResponse
+ 4661              	.LVL347:
+2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 4662              		.loc 1 2675 20 view .LVU1721
+ 4663 0062 2067     		str	r0, [r4, #112]
+ 4664              	.LVL348:
+ 4665              	.L259:
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4666              		.loc 1 2680 3 is_stmt 1 view .LVU1722
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4667              		.loc 1 2680 24 is_stmt 0 view .LVU1723
+ 4668 0064 0421     		movs	r1, #4
+ 4669 0066 2068     		ldr	r0, [r4]
+ 4670 0068 FFF7FEFF 		bl	SDMMC_GetResponse
+ 4671              	.LVL349:
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4672              		.loc 1 2680 70 view .LVU1724
+ 4673 006c 000D     		lsrs	r0, r0, #20
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4674              		.loc 1 2680 21 view .LVU1725
+ 4675 006e E064     		str	r0, [r4, #76]
+2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4676              		.loc 1 2683 3 is_stmt 1 view .LVU1726
+2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4677              		.loc 1 2683 7 is_stmt 0 view .LVU1727
+ 4678 0070 05A9     		add	r1, sp, #20
+ 4679 0072 2046     		mov	r0, r4
+ 4680 0074 FFF7FEFF 		bl	HAL_SD_GetCardCSD
+ 4681              	.LVL350:
+2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4682              		.loc 1 2683 6 view .LVU1728
+ 4683 0078 0028     		cmp	r0, #0
+ 4684 007a 3ED1     		bne	.L261
+2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 4685              		.loc 1 2689 3 is_stmt 1 view .LVU1729
+2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 4686              		.loc 1 2689 82 is_stmt 0 view .LVU1730
+ 4687 007c 226D     		ldr	r2, [r4, #80]
+2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 4688              		.loc 1 2689 16 view .LVU1731
+ARM GAS  /tmp/ccQEYyKb.s 			page 168
+
+
+ 4689 007e 1204     		lsls	r2, r2, #16
+ 4690 0080 0023     		movs	r3, #0
+ 4691 0082 2068     		ldr	r0, [r4]
+ 4692 0084 FFF7FEFF 		bl	SDMMC_CmdSelDesel
+ 4693              	.LVL351:
+2690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4694              		.loc 1 2690 3 is_stmt 1 view .LVU1732
+2690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4695              		.loc 1 2690 5 is_stmt 0 view .LVU1733
+ 4696 0088 0546     		mov	r5, r0
+ 4697 008a 98BB     		cbnz	r0, .L255
+2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4698              		.loc 1 2696 3 is_stmt 1 view .LVU1734
+2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4699              		.loc 1 2696 9 is_stmt 0 view .LVU1735
+ 4700 008c 2346     		mov	r3, r4
+ 4701 008e 53F8106B 		ldr	r6, [r3], #16
+ 4702 0092 93E80700 		ldm	r3, {r0, r1, r2}
+ 4703              	.LVL352:
+2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4704              		.loc 1 2696 9 view .LVU1736
+ 4705 0096 8DE80700 		stm	sp, {r0, r1, r2}
+ 4706 009a 0434     		adds	r4, r4, #4
+ 4707              	.LVL353:
+2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4708              		.loc 1 2696 9 view .LVU1737
+ 4709 009c 94E80E00 		ldm	r4, {r1, r2, r3}
+ 4710 00a0 3046     		mov	r0, r6
+ 4711 00a2 FFF7FEFF 		bl	SDMMC_Init
+ 4712              	.LVL354:
+2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 4713              		.loc 1 2699 3 is_stmt 1 view .LVU1738
+2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 4714              		.loc 1 2699 10 is_stmt 0 view .LVU1739
+ 4715 00a6 25E0     		b	.L255
+ 4716              	.LVL355:
+ 4717              	.L263:
+2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 4718              		.loc 1 2633 5 is_stmt 1 view .LVU1740
+2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 4719              		.loc 1 2633 18 is_stmt 0 view .LVU1741
+ 4720 00a8 2068     		ldr	r0, [r4]
+ 4721 00aa FFF7FEFF 		bl	SDMMC_CmdSendCID
+ 4722              	.LVL356:
+2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 4723              		.loc 1 2634 5 is_stmt 1 view .LVU1742
+2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 4724              		.loc 1 2634 7 is_stmt 0 view .LVU1743
+ 4725 00ae 0546     		mov	r5, r0
+ 4726 00b0 00BB     		cbnz	r0, .L255
+2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ 4727              		.loc 1 2641 7 is_stmt 1 view .LVU1744
+2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ 4728              		.loc 1 2641 22 is_stmt 0 view .LVU1745
+ 4729 00b2 0021     		movs	r1, #0
+ 4730 00b4 2068     		ldr	r0, [r4]
+ 4731              	.LVL357:
+ARM GAS  /tmp/ccQEYyKb.s 			page 169
+
+
+2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ 4732              		.loc 1 2641 22 view .LVU1746
+ 4733 00b6 FFF7FEFF 		bl	SDMMC_GetResponse
+ 4734              	.LVL358:
+2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+ 4735              		.loc 1 2641 20 view .LVU1747
+ 4736 00ba 6067     		str	r0, [r4, #116]
+2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+ 4737              		.loc 1 2642 7 is_stmt 1 view .LVU1748
+2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+ 4738              		.loc 1 2642 22 is_stmt 0 view .LVU1749
+ 4739 00bc 0421     		movs	r1, #4
+ 4740 00be 2068     		ldr	r0, [r4]
+ 4741 00c0 FFF7FEFF 		bl	SDMMC_GetResponse
+ 4742              	.LVL359:
+2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+ 4743              		.loc 1 2642 20 view .LVU1750
+ 4744 00c4 A067     		str	r0, [r4, #120]
+2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+ 4745              		.loc 1 2643 7 is_stmt 1 view .LVU1751
+2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+ 4746              		.loc 1 2643 22 is_stmt 0 view .LVU1752
+ 4747 00c6 0821     		movs	r1, #8
+ 4748 00c8 2068     		ldr	r0, [r4]
+ 4749 00ca FFF7FEFF 		bl	SDMMC_GetResponse
+ 4750              	.LVL360:
+2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+ 4751              		.loc 1 2643 20 view .LVU1753
+ 4752 00ce E067     		str	r0, [r4, #124]
+2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 4753              		.loc 1 2644 7 is_stmt 1 view .LVU1754
+2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 4754              		.loc 1 2644 22 is_stmt 0 view .LVU1755
+ 4755 00d0 0C21     		movs	r1, #12
+ 4756 00d2 2068     		ldr	r0, [r4]
+ 4757 00d4 FFF7FEFF 		bl	SDMMC_GetResponse
+ 4758              	.LVL361:
+2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 4759              		.loc 1 2644 20 view .LVU1756
+ 4760 00d8 C4F88000 		str	r0, [r4, #128]
+ 4761 00dc 9EE7     		b	.L257
+ 4762              	.LVL362:
+ 4763              	.L264:
+2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 4764              		.loc 1 2652 5 is_stmt 1 view .LVU1757
+2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if(errorstate != HAL_SD_ERROR_NONE)
+ 4765              		.loc 1 2652 18 is_stmt 0 view .LVU1758
+ 4766 00de 0DF11201 		add	r1, sp, #18
+ 4767 00e2 2068     		ldr	r0, [r4]
+ 4768 00e4 FFF7FEFF 		bl	SDMMC_CmdSetRelAdd
+ 4769              	.LVL363:
+2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 4770              		.loc 1 2653 5 is_stmt 1 view .LVU1759
+2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 4771              		.loc 1 2653 7 is_stmt 0 view .LVU1760
+ 4772 00e8 0546     		mov	r5, r0
+ 4773 00ea 0028     		cmp	r0, #0
+ARM GAS  /tmp/ccQEYyKb.s 			page 170
+
+
+ 4774 00ec 99D0     		beq	.L258
+ 4775 00ee 01E0     		b	.L255
+ 4776              	.LVL364:
+ 4777              	.L260:
+2627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4778              		.loc 1 2627 12 view .LVU1761
+ 4779 00f0 4FF08065 		mov	r5, #67108864
+ 4780              	.LVL365:
+ 4781              	.L255:
+2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4782              		.loc 1 2700 1 view .LVU1762
+ 4783 00f4 2846     		mov	r0, r5
+ 4784 00f6 10B0     		add	sp, sp, #64
+ 4785              	.LCFI53:
+ 4786              		.cfi_remember_state
+ 4787              		.cfi_def_cfa_offset 16
+ 4788              		@ sp needed
+ 4789 00f8 70BD     		pop	{r4, r5, r6, pc}
+ 4790              	.LVL366:
+ 4791              	.L261:
+ 4792              	.LCFI54:
+ 4793              		.cfi_restore_state
+2685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4794              		.loc 1 2685 12 view .LVU1763
+ 4795 00fa 4FF08055 		mov	r5, #268435456
+ 4796 00fe F9E7     		b	.L255
+ 4797              		.cfi_endproc
+ 4798              	.LFE173:
+ 4800              		.section	.text.HAL_SD_InitCard,"ax",%progbits
+ 4801              		.align	1
+ 4802              		.global	HAL_SD_InitCard
+ 4803              		.syntax unified
+ 4804              		.thumb
+ 4805              		.thumb_func
+ 4806              		.fpu fpv5-d16
+ 4808              	HAL_SD_InitCard:
+ 4809              	.LVL367:
+ 4810              	.LFB142:
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 4811              		.loc 1 404 1 is_stmt 1 view -0
+ 4812              		.cfi_startproc
+ 4813              		@ args = 0, pretend = 0, frame = 24
+ 4814              		@ frame_needed = 0, uses_anonymous_args = 0
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 4815              		.loc 1 404 1 is_stmt 0 view .LVU1765
+ 4816 0000 30B5     		push	{r4, r5, lr}
+ 4817              	.LCFI55:
+ 4818              		.cfi_def_cfa_offset 12
+ 4819              		.cfi_offset 4, -12
+ 4820              		.cfi_offset 5, -8
+ 4821              		.cfi_offset 14, -4
+ 4822 0002 8BB0     		sub	sp, sp, #44
+ 4823              	.LCFI56:
+ 4824              		.cfi_def_cfa_offset 56
+ 4825 0004 0446     		mov	r4, r0
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_StatusTypeDef status;
+ 4826              		.loc 1 405 3 is_stmt 1 view .LVU1766
+ARM GAS  /tmp/ccQEYyKb.s 			page 171
+
+
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_InitTypeDef Init;
+ 4827              		.loc 1 406 3 view .LVU1767
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   
+ 4828              		.loc 1 407 3 view .LVU1768
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.ClockBypass         = SDMMC_CLOCK_BYPASS_DISABLE;
+ 4829              		.loc 1 410 3 view .LVU1769
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.ClockBypass         = SDMMC_CLOCK_BYPASS_DISABLE;
+ 4830              		.loc 1 410 28 is_stmt 0 view .LVU1770
+ 4831 0006 0023     		movs	r3, #0
+ 4832 0008 0493     		str	r3, [sp, #16]
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+ 4833              		.loc 1 411 3 is_stmt 1 view .LVU1771
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+ 4834              		.loc 1 411 28 is_stmt 0 view .LVU1772
+ 4835 000a 0593     		str	r3, [sp, #20]
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.BusWide             = SDMMC_BUS_WIDE_1B;
+ 4836              		.loc 1 412 3 is_stmt 1 view .LVU1773
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.BusWide             = SDMMC_BUS_WIDE_1B;
+ 4837              		.loc 1 412 28 is_stmt 0 view .LVU1774
+ 4838 000c 0693     		str	r3, [sp, #24]
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+ 4839              		.loc 1 413 3 is_stmt 1 view .LVU1775
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+ 4840              		.loc 1 413 28 is_stmt 0 view .LVU1776
+ 4841 000e 0793     		str	r3, [sp, #28]
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.ClockDiv            = SDMMC_INIT_CLK_DIV;
+ 4842              		.loc 1 414 3 is_stmt 1 view .LVU1777
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   Init.ClockDiv            = SDMMC_INIT_CLK_DIV;
+ 4843              		.loc 1 414 28 is_stmt 0 view .LVU1778
+ 4844 0010 0893     		str	r3, [sp, #32]
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4845              		.loc 1 415 3 is_stmt 1 view .LVU1779
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4846              		.loc 1 415 28 is_stmt 0 view .LVU1780
+ 4847 0012 7623     		movs	r3, #118
+ 4848 0014 0993     		str	r3, [sp, #36]
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(status != HAL_OK)
+ 4849              		.loc 1 418 3 is_stmt 1 view .LVU1781
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(status != HAL_OK)
+ 4850              		.loc 1 418 12 is_stmt 0 view .LVU1782
+ 4851 0016 0AAB     		add	r3, sp, #40
+ 4852 0018 13E90700 		ldmdb	r3, {r0, r1, r2}
+ 4853              	.LVL368:
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(status != HAL_OK)
+ 4854              		.loc 1 418 12 view .LVU1783
+ 4855 001c 8DE80700 		stm	sp, {r0, r1, r2}
+ 4856 0020 04AB     		add	r3, sp, #16
+ 4857 0022 0ECB     		ldm	r3, {r1, r2, r3}
+ 4858 0024 2068     		ldr	r0, [r4]
+ 4859 0026 FFF7FEFF 		bl	SDMMC_Init
+ 4860              	.LVL369:
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4861              		.loc 1 419 3 is_stmt 1 view .LVU1784
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4862              		.loc 1 419 5 is_stmt 0 view .LVU1785
+ 4863 002a 18B1     		cbz	r0, .L271
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ARM GAS  /tmp/ccQEYyKb.s 			page 172
+
+
+ 4864              		.loc 1 421 12 view .LVU1786
+ 4865 002c 0125     		movs	r5, #1
+ 4866              	.LVL370:
+ 4867              	.L266:
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4868              		.loc 1 466 1 view .LVU1787
+ 4869 002e 2846     		mov	r0, r5
+ 4870 0030 0BB0     		add	sp, sp, #44
+ 4871              	.LCFI57:
+ 4872              		.cfi_remember_state
+ 4873              		.cfi_def_cfa_offset 12
+ 4874              		@ sp needed
+ 4875 0032 30BD     		pop	{r4, r5, pc}
+ 4876              	.LVL371:
+ 4877              	.L271:
+ 4878              	.LCFI58:
+ 4879              		.cfi_restore_state
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4880              		.loc 1 466 1 view .LVU1788
+ 4881 0034 0546     		mov	r5, r0
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4882              		.loc 1 425 3 is_stmt 1 view .LVU1789
+ 4883 0036 2268     		ldr	r2, [r4]
+ 4884 0038 5368     		ldr	r3, [r2, #4]
+ 4885 003a 23F48073 		bic	r3, r3, #256
+ 4886 003e 5360     		str	r3, [r2, #4]
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4887              		.loc 1 428 3 view .LVU1790
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4888              		.loc 1 428 9 is_stmt 0 view .LVU1791
+ 4889 0040 2068     		ldr	r0, [r4]
+ 4890              	.LVL372:
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4891              		.loc 1 428 9 view .LVU1792
+ 4892 0042 FFF7FEFF 		bl	SDMMC_PowerState_ON
+ 4893              	.LVL373:
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4894              		.loc 1 431 3 is_stmt 1 view .LVU1793
+ 4895 0046 2268     		ldr	r2, [r4]
+ 4896 0048 5368     		ldr	r3, [r2, #4]
+ 4897 004a 43F48073 		orr	r3, r3, #256
+ 4898 004e 5360     		str	r3, [r2, #4]
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 4899              		.loc 1 434 3 view .LVU1794
+ 4900 0050 0220     		movs	r0, #2
+ 4901 0052 FFF7FEFF 		bl	HAL_Delay
+ 4902              	.LVL374:
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 4903              		.loc 1 437 3 view .LVU1795
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 4904              		.loc 1 437 16 is_stmt 0 view .LVU1796
+ 4905 0056 2046     		mov	r0, r4
+ 4906 0058 FFF7FEFF 		bl	SD_PowerON
+ 4907              	.LVL375:
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4908              		.loc 1 438 3 is_stmt 1 view .LVU1797
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ARM GAS  /tmp/ccQEYyKb.s 			page 173
+
+
+ 4909              		.loc 1 438 5 is_stmt 0 view .LVU1798
+ 4910 005c 30B1     		cbz	r0, .L267
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+ 4911              		.loc 1 440 5 is_stmt 1 view .LVU1799
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+ 4912              		.loc 1 440 16 is_stmt 0 view .LVU1800
+ 4913 005e 0125     		movs	r5, #1
+ 4914 0060 84F83450 		strb	r5, [r4, #52]
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 4915              		.loc 1 441 5 is_stmt 1 view .LVU1801
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 4916              		.loc 1 441 20 is_stmt 0 view .LVU1802
+ 4917 0064 A36B     		ldr	r3, [r4, #56]
+ 4918 0066 0343     		orrs	r3, r3, r0
+ 4919 0068 A363     		str	r3, [r4, #56]
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4920              		.loc 1 442 5 is_stmt 1 view .LVU1803
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4921              		.loc 1 442 12 is_stmt 0 view .LVU1804
+ 4922 006a E0E7     		b	.L266
+ 4923              	.L267:
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 4924              		.loc 1 446 3 is_stmt 1 view .LVU1805
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 4925              		.loc 1 446 16 is_stmt 0 view .LVU1806
+ 4926 006c 2046     		mov	r0, r4
+ 4927              	.LVL376:
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 4928              		.loc 1 446 16 view .LVU1807
+ 4929 006e FFF7FEFF 		bl	SD_InitCard
+ 4930              	.LVL377:
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4931              		.loc 1 447 3 is_stmt 1 view .LVU1808
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4932              		.loc 1 447 5 is_stmt 0 view .LVU1809
+ 4933 0072 30B1     		cbz	r0, .L268
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+ 4934              		.loc 1 449 5 is_stmt 1 view .LVU1810
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+ 4935              		.loc 1 449 16 is_stmt 0 view .LVU1811
+ 4936 0074 0125     		movs	r5, #1
+ 4937 0076 84F83450 		strb	r5, [r4, #52]
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 4938              		.loc 1 450 5 is_stmt 1 view .LVU1812
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 4939              		.loc 1 450 20 is_stmt 0 view .LVU1813
+ 4940 007a A36B     		ldr	r3, [r4, #56]
+ 4941 007c 0343     		orrs	r3, r3, r0
+ 4942 007e A363     		str	r3, [r4, #56]
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4943              		.loc 1 451 5 is_stmt 1 view .LVU1814
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4944              		.loc 1 451 12 is_stmt 0 view .LVU1815
+ 4945 0080 D5E7     		b	.L266
+ 4946              	.L268:
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 4947              		.loc 1 455 3 is_stmt 1 view .LVU1816
+ARM GAS  /tmp/ccQEYyKb.s 			page 174
+
+
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 4948              		.loc 1 455 16 is_stmt 0 view .LVU1817
+ 4949 0082 4FF40071 		mov	r1, #512
+ 4950 0086 2068     		ldr	r0, [r4]
+ 4951              	.LVL378:
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 4952              		.loc 1 455 16 view .LVU1818
+ 4953 0088 FFF7FEFF 		bl	SDMMC_CmdBlockLength
+ 4954              	.LVL379:
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4955              		.loc 1 456 3 is_stmt 1 view .LVU1819
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4956              		.loc 1 456 5 is_stmt 0 view .LVU1820
+ 4957 008c 0028     		cmp	r0, #0
+ 4958 008e CED0     		beq	.L266
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+ 4959              		.loc 1 459 5 is_stmt 1 view .LVU1821
+ 4960 0090 2368     		ldr	r3, [r4]
+ 4961 0092 0449     		ldr	r1, .L272
+ 4962 0094 9963     		str	r1, [r3, #56]
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 4963              		.loc 1 460 5 view .LVU1822
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 4964              		.loc 1 460 20 is_stmt 0 view .LVU1823
+ 4965 0096 A36B     		ldr	r3, [r4, #56]
+ 4966 0098 0343     		orrs	r3, r3, r0
+ 4967 009a A363     		str	r3, [r4, #56]
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 4968              		.loc 1 461 5 is_stmt 1 view .LVU1824
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     return HAL_ERROR;
+ 4969              		.loc 1 461 16 is_stmt 0 view .LVU1825
+ 4970 009c 0125     		movs	r5, #1
+ 4971 009e 84F83450 		strb	r5, [r4, #52]
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4972              		.loc 1 462 5 is_stmt 1 view .LVU1826
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 4973              		.loc 1 462 12 is_stmt 0 view .LVU1827
+ 4974 00a2 C4E7     		b	.L266
+ 4975              	.L273:
+ 4976              		.align	2
+ 4977              	.L272:
+ 4978 00a4 FF054000 		.word	4195839
+ 4979              		.cfi_endproc
+ 4980              	.LFE142:
+ 4982              		.section	.text.HAL_SD_Init,"ax",%progbits
+ 4983              		.align	1
+ 4984              		.global	HAL_SD_Init
+ 4985              		.syntax unified
+ 4986              		.thumb
+ 4987              		.thumb_func
+ 4988              		.fpu fpv5-d16
+ 4990              	HAL_SD_Init:
+ 4991              	.LVL380:
+ 4992              	.LFB141:
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check the SD handle allocation */
+ 4993              		.loc 1 336 1 is_stmt 1 view -0
+ 4994              		.cfi_startproc
+ARM GAS  /tmp/ccQEYyKb.s 			page 175
+
+
+ 4995              		@ args = 0, pretend = 0, frame = 0
+ 4996              		@ frame_needed = 0, uses_anonymous_args = 0
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4997              		.loc 1 338 3 view .LVU1829
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 4998              		.loc 1 338 5 is_stmt 0 view .LVU1830
+ 4999 0000 A8B1     		cbz	r0, .L277
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   /* Check the SD handle allocation */
+ 5000              		.loc 1 336 1 view .LVU1831
+ 5001 0002 10B5     		push	{r4, lr}
+ 5002              	.LCFI59:
+ 5003              		.cfi_def_cfa_offset 8
+ 5004              		.cfi_offset 4, -8
+ 5005              		.cfi_offset 14, -4
+ 5006 0004 0446     		mov	r4, r0
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge));
+ 5007              		.loc 1 344 3 is_stmt 1 view .LVU1832
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass));
+ 5008              		.loc 1 345 3 view .LVU1833
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+ 5009              		.loc 1 346 3 view .LVU1834
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));
+ 5010              		.loc 1 347 3 view .LVU1835
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+ 5011              		.loc 1 348 3 view .LVU1836
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
+ 5012              		.loc 1 349 3 view .LVU1837
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5013              		.loc 1 350 3 view .LVU1838
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5014              		.loc 1 352 3 view .LVU1839
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5015              		.loc 1 352 9 is_stmt 0 view .LVU1840
+ 5016 0006 90F83430 		ldrb	r3, [r0, #52]	@ zero_extendqisi2
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5017              		.loc 1 352 5 view .LVU1841
+ 5018 000a 63B1     		cbz	r3, .L283
+ 5019              	.LVL381:
+ 5020              	.L276:
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5021              		.loc 1 376 3 is_stmt 1 view .LVU1842
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5022              		.loc 1 376 14 is_stmt 0 view .LVU1843
+ 5023 000c 0323     		movs	r3, #3
+ 5024 000e 84F83430 		strb	r3, [r4, #52]
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5025              		.loc 1 379 3 is_stmt 1 view .LVU1844
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5026              		.loc 1 379 7 is_stmt 0 view .LVU1845
+ 5027 0012 2046     		mov	r0, r4
+ 5028 0014 FFF7FEFF 		bl	HAL_SD_InitCard
+ 5029              	.LVL382:
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5030              		.loc 1 379 6 view .LVU1846
+ 5031 0018 58B9     		cbnz	r0, .L278
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5032              		.loc 1 385 3 is_stmt 1 view .LVU1847
+ARM GAS  /tmp/ccQEYyKb.s 			page 176
+
+
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5033              		.loc 1 385 18 is_stmt 0 view .LVU1848
+ 5034 001a A063     		str	r0, [r4, #56]
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5035              		.loc 1 388 3 is_stmt 1 view .LVU1849
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5036              		.loc 1 388 16 is_stmt 0 view .LVU1850
+ 5037 001c 2063     		str	r0, [r4, #48]
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5038              		.loc 1 391 3 is_stmt 1 view .LVU1851
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5039              		.loc 1 391 14 is_stmt 0 view .LVU1852
+ 5040 001e 0123     		movs	r3, #1
+ 5041 0020 84F83430 		strb	r3, [r4, #52]
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 5042              		.loc 1 393 3 is_stmt 1 view .LVU1853
+ 5043              	.L275:
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5044              		.loc 1 394 1 is_stmt 0 view .LVU1854
+ 5045 0024 10BD     		pop	{r4, pc}
+ 5046              	.LVL383:
+ 5047              	.L283:
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ 5048              		.loc 1 355 5 is_stmt 1 view .LVU1855
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ 5049              		.loc 1 355 15 is_stmt 0 view .LVU1856
+ 5050 0026 0377     		strb	r3, [r0, #28]
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 5051              		.loc 1 372 5 is_stmt 1 view .LVU1857
+ 5052 0028 FFF7FEFF 		bl	HAL_SD_MspInit
+ 5053              	.LVL384:
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 5054              		.loc 1 372 5 is_stmt 0 view .LVU1858
+ 5055 002c EEE7     		b	.L276
+ 5056              	.LVL385:
+ 5057              	.L277:
+ 5058              	.LCFI60:
+ 5059              		.cfi_def_cfa_offset 0
+ 5060              		.cfi_restore 4
+ 5061              		.cfi_restore 14
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5062              		.loc 1 340 12 view .LVU1859
+ 5063 002e 0120     		movs	r0, #1
+ 5064              	.LVL386:
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5065              		.loc 1 394 1 view .LVU1860
+ 5066 0030 7047     		bx	lr
+ 5067              	.LVL387:
+ 5068              	.L278:
+ 5069              	.LCFI61:
+ 5070              		.cfi_def_cfa_offset 8
+ 5071              		.cfi_offset 4, -8
+ 5072              		.cfi_offset 14, -4
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5073              		.loc 1 381 12 view .LVU1861
+ 5074 0032 0120     		movs	r0, #1
+ 5075 0034 F6E7     		b	.L275
+ARM GAS  /tmp/ccQEYyKb.s 			page 177
+
+
+ 5076              		.cfi_endproc
+ 5077              	.LFE141:
+ 5079              		.section	.text.HAL_SD_GetCardStatus,"ax",%progbits
+ 5080              		.align	1
+ 5081              		.global	HAL_SD_GetCardStatus
+ 5082              		.syntax unified
+ 5083              		.thumb
+ 5084              		.thumb_func
+ 5085              		.fpu fpv5-d16
+ 5087              	HAL_SD_GetCardStatus:
+ 5088              	.LVL388:
+ 5089              	.LFB162:
+2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t sd_status[16];
+ 5090              		.loc 1 2100 1 is_stmt 1 view -0
+ 5091              		.cfi_startproc
+ 5092              		@ args = 0, pretend = 0, frame = 64
+ 5093              		@ frame_needed = 0, uses_anonymous_args = 0
+2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t sd_status[16];
+ 5094              		.loc 1 2100 1 is_stmt 0 view .LVU1863
+ 5095 0000 30B5     		push	{r4, r5, lr}
+ 5096              	.LCFI62:
+ 5097              		.cfi_def_cfa_offset 12
+ 5098              		.cfi_offset 4, -12
+ 5099              		.cfi_offset 5, -8
+ 5100              		.cfi_offset 14, -4
+ 5101 0002 91B0     		sub	sp, sp, #68
+ 5102              	.LCFI63:
+ 5103              		.cfi_def_cfa_offset 80
+ 5104 0004 0546     		mov	r5, r0
+ 5105 0006 0C46     		mov	r4, r1
+2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 5106              		.loc 1 2101 3 is_stmt 1 view .LVU1864
+2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 5107              		.loc 1 2102 3 view .LVU1865
+2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5108              		.loc 1 2103 3 view .LVU1866
+ 5109              	.LVL389:
+2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 5110              		.loc 1 2105 3 view .LVU1867
+2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 5111              		.loc 1 2105 16 is_stmt 0 view .LVU1868
+ 5112 0008 6946     		mov	r1, sp
+ 5113              	.LVL390:
+2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 5114              		.loc 1 2105 16 view .LVU1869
+ 5115 000a FFF7FEFF 		bl	SD_SendSDStatus
+ 5116              	.LVL391:
+2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5117              		.loc 1 2106 3 is_stmt 1 view .LVU1870
+2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5118              		.loc 1 2106 5 is_stmt 0 view .LVU1871
+ 5119 000e C0B1     		cbz	r0, .L285
+2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+ 5120              		.loc 1 2109 5 is_stmt 1 view .LVU1872
+ 5121 0010 2B68     		ldr	r3, [r5]
+ 5122 0012 2549     		ldr	r1, .L289
+ 5123 0014 9963     		str	r1, [r3, #56]
+ARM GAS  /tmp/ccQEYyKb.s 			page 178
+
+
+2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 5124              		.loc 1 2110 5 view .LVU1873
+2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 5125              		.loc 1 2110 20 is_stmt 0 view .LVU1874
+ 5126 0016 AB6B     		ldr	r3, [r5, #56]
+ 5127 0018 0343     		orrs	r3, r3, r0
+ 5128 001a AB63     		str	r3, [r5, #56]
+2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+ 5129              		.loc 1 2111 5 is_stmt 1 view .LVU1875
+2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+ 5130              		.loc 1 2111 16 is_stmt 0 view .LVU1876
+ 5131 001c 0124     		movs	r4, #1
+ 5132              	.LVL392:
+2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+ 5133              		.loc 1 2111 16 view .LVU1877
+ 5134 001e 85F83440 		strb	r4, [r5, #52]
+2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5135              		.loc 1 2112 5 is_stmt 1 view .LVU1878
+ 5136              	.LVL393:
+ 5137              	.L286:
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 5138              		.loc 1 2139 3 view .LVU1879
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 5139              		.loc 1 2139 16 is_stmt 0 view .LVU1880
+ 5140 0022 4FF40071 		mov	r1, #512
+ 5141 0026 2868     		ldr	r0, [r5]
+ 5142              	.LVL394:
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 5143              		.loc 1 2139 16 view .LVU1881
+ 5144 0028 FFF7FEFF 		bl	SDMMC_CmdBlockLength
+ 5145              	.LVL395:
+2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5146              		.loc 1 2140 3 is_stmt 1 view .LVU1882
+2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5147              		.loc 1 2140 5 is_stmt 0 view .LVU1883
+ 5148 002c 30B1     		cbz	r0, .L287
+2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode = errorstate;
+ 5149              		.loc 1 2143 5 is_stmt 1 view .LVU1884
+ 5150 002e 2A68     		ldr	r2, [r5]
+ 5151 0030 1D49     		ldr	r1, .L289
+ 5152 0032 9163     		str	r1, [r2, #56]
+2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 5153              		.loc 1 2144 5 view .LVU1885
+2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 5154              		.loc 1 2144 20 is_stmt 0 view .LVU1886
+ 5155 0034 A863     		str	r0, [r5, #56]
+2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+ 5156              		.loc 1 2145 5 is_stmt 1 view .LVU1887
+2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+ 5157              		.loc 1 2145 16 is_stmt 0 view .LVU1888
+ 5158 0036 0124     		movs	r4, #1
+ 5159              	.LVL396:
+2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+ 5160              		.loc 1 2145 16 view .LVU1889
+ 5161 0038 85F83440 		strb	r4, [r5, #52]
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5162              		.loc 1 2146 5 is_stmt 1 view .LVU1890
+ARM GAS  /tmp/ccQEYyKb.s 			page 179
+
+
+ 5163              	.LVL397:
+ 5164              	.L287:
+2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 5165              		.loc 1 2149 3 view .LVU1891
+2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5166              		.loc 1 2150 1 is_stmt 0 view .LVU1892
+ 5167 003c 2046     		mov	r0, r4
+ 5168              	.LVL398:
+2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5169              		.loc 1 2150 1 view .LVU1893
+ 5170 003e 11B0     		add	sp, sp, #68
+ 5171              	.LCFI64:
+ 5172              		.cfi_remember_state
+ 5173              		.cfi_def_cfa_offset 12
+ 5174              		@ sp needed
+ 5175 0040 30BD     		pop	{r4, r5, pc}
+ 5176              	.LVL399:
+ 5177              	.L285:
+ 5178              	.LCFI65:
+ 5179              		.cfi_restore_state
+2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5180              		.loc 1 2116 5 is_stmt 1 view .LVU1894
+2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5181              		.loc 1 2116 49 is_stmt 0 view .LVU1895
+ 5182 0042 009A     		ldr	r2, [sp]
+2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5183              		.loc 1 2116 29 view .LVU1896
+ 5184 0044 C2F38113 		ubfx	r3, r2, #6, #2
+2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5185              		.loc 1 2116 27 view .LVU1897
+ 5186 0048 2370     		strb	r3, [r4]
+2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5187              		.loc 1 2118 5 is_stmt 1 view .LVU1898
+2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5188              		.loc 1 2118 28 is_stmt 0 view .LVU1899
+ 5189 004a C2F34013 		ubfx	r3, r2, #5, #1
+2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5190              		.loc 1 2118 26 view .LVU1900
+ 5191 004e 6370     		strb	r3, [r4, #1]
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5192              		.loc 1 2120 5 is_stmt 1 view .LVU1901
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5193              		.loc 1 2120 66 is_stmt 0 view .LVU1902
+ 5194 0050 130A     		lsrs	r3, r2, #8
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5195              		.loc 1 2120 25 view .LVU1903
+ 5196 0052 23F0FF03 		bic	r3, r3, #255
+ 5197 0056 43EA1263 		orr	r3, r3, r2, lsr #24
+ 5198 005a 9BB2     		uxth	r3, r3
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5199              		.loc 1 2120 23 view .LVU1904
+ 5200 005c 6380     		strh	r3, [r4, #2]	@ movhi
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                                   ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U
+ 5201              		.loc 1 2122 5 is_stmt 1 view .LVU1905
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                                   ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U
+ 5202              		.loc 1 2122 46 is_stmt 0 view .LVU1906
+ 5203 005e 019A     		ldr	r2, [sp, #4]
+ARM GAS  /tmp/ccQEYyKb.s 			page 180
+
+
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                                   ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U
+ 5204              		.loc 1 2122 98 view .LVU1907
+ 5205 0060 1302     		lsls	r3, r2, #8
+ 5206 0062 03F47F03 		and	r3, r3, #16711680
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                                   ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U
+ 5207              		.loc 1 2122 70 view .LVU1908
+ 5208 0066 43EA0263 		orr	r3, r3, r2, lsl #24
+2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5209              		.loc 1 2123 63 view .LVU1909
+ 5210 006a 110A     		lsrs	r1, r2, #8
+ 5211 006c 01F47F41 		and	r1, r1, #65280
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                                   ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U
+ 5212              		.loc 1 2122 105 view .LVU1910
+ 5213 0070 0B43     		orrs	r3, r3, r1
+2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5214              		.loc 1 2123 70 view .LVU1911
+ 5215 0072 43EA1263 		orr	r3, r3, r2, lsr #24
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                                   ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U
+ 5216              		.loc 1 2122 32 view .LVU1912
+ 5217 0076 6360     		str	r3, [r4, #4]
+2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5218              		.loc 1 2125 5 is_stmt 1 view .LVU1913
+2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5219              		.loc 1 2125 46 is_stmt 0 view .LVU1914
+ 5220 0078 029B     		ldr	r3, [sp, #8]
+2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5221              		.loc 1 2125 27 view .LVU1915
+ 5222 007a DAB2     		uxtb	r2, r3
+2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5223              		.loc 1 2125 25 view .LVU1916
+ 5224 007c 2272     		strb	r2, [r4, #8]
+2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5225              		.loc 1 2127 5 is_stmt 1 view .LVU1917
+2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5226              		.loc 1 2127 32 is_stmt 0 view .LVU1918
+ 5227 007e C3F30722 		ubfx	r2, r3, #8, #8
+2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5228              		.loc 1 2127 30 view .LVU1919
+ 5229 0082 6272     		strb	r2, [r4, #9]
+2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5230              		.loc 1 2129 5 is_stmt 1 view .LVU1920
+2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5231              		.loc 1 2129 35 is_stmt 0 view .LVU1921
+ 5232 0084 C3F30352 		ubfx	r2, r3, #20, #4
+2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5233              		.loc 1 2129 33 view .LVU1922
+ 5234 0088 A272     		strb	r2, [r4, #10]
+2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5235              		.loc 1 2131 5 is_stmt 1 view .LVU1923
+2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5236              		.loc 1 2131 67 is_stmt 0 view .LVU1924
+ 5237 008a 1B0C     		lsrs	r3, r3, #16
+2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5238              		.loc 1 2131 87 view .LVU1925
+ 5239 008c 039A     		ldr	r2, [sp, #12]
+2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5240              		.loc 1 2131 91 view .LVU1926
+ARM GAS  /tmp/ccQEYyKb.s 			page 181
+
+
+ 5241 008e D1B2     		uxtb	r1, r2
+2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5242              		.loc 1 2131 26 view .LVU1927
+ 5243 0090 23F0FF03 		bic	r3, r3, #255
+ 5244 0094 0B43     		orrs	r3, r3, r1
+2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5245              		.loc 1 2131 24 view .LVU1928
+ 5246 0096 A381     		strh	r3, [r4, #12]	@ movhi
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5247              		.loc 1 2133 5 is_stmt 1 view .LVU1929
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5248              		.loc 1 2133 29 is_stmt 0 view .LVU1930
+ 5249 0098 C2F38523 		ubfx	r3, r2, #10, #6
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5250              		.loc 1 2133 27 view .LVU1931
+ 5251 009c A373     		strb	r3, [r4, #14]
+2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5252              		.loc 1 2135 5 is_stmt 1 view .LVU1932
+2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5253              		.loc 1 2135 28 is_stmt 0 view .LVU1933
+ 5254 009e C2F30122 		ubfx	r2, r2, #8, #2
+2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5255              		.loc 1 2135 26 view .LVU1934
+ 5256 00a2 E273     		strb	r2, [r4, #15]
+2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5257              		.loc 1 2103 21 view .LVU1935
+ 5258 00a4 0024     		movs	r4, #0
+ 5259              	.LVL400:
+2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5260              		.loc 1 2103 21 view .LVU1936
+ 5261 00a6 BCE7     		b	.L286
+ 5262              	.L290:
+ 5263              		.align	2
+ 5264              	.L289:
+ 5265 00a8 FF054000 		.word	4195839
+ 5266              		.cfi_endproc
+ 5267              	.LFE162:
+ 5269              		.section	.text.HAL_SD_GetCardInfo,"ax",%progbits
+ 5270              		.align	1
+ 5271              		.global	HAL_SD_GetCardInfo
+ 5272              		.syntax unified
+ 5273              		.thumb
+ 5274              		.thumb_func
+ 5275              		.fpu fpv5-d16
+ 5277              	HAL_SD_GetCardInfo:
+ 5278              	.LVL401:
+ 5279              	.LFB163:
+2160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
+ 5280              		.loc 1 2160 1 is_stmt 1 view -0
+ 5281              		.cfi_startproc
+ 5282              		@ args = 0, pretend = 0, frame = 0
+ 5283              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5284              		@ link register save eliminated.
+2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
+ 5285              		.loc 1 2161 3 view .LVU1938
+2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
+ 5286              		.loc 1 2161 51 is_stmt 0 view .LVU1939
+ARM GAS  /tmp/ccQEYyKb.s 			page 182
+
+
+ 5287 0000 436C     		ldr	r3, [r0, #68]
+2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
+ 5288              		.loc 1 2161 27 view .LVU1940
+ 5289 0002 0B60     		str	r3, [r1]
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
+ 5290              		.loc 1 2162 3 is_stmt 1 view .LVU1941
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
+ 5291              		.loc 1 2162 51 is_stmt 0 view .LVU1942
+ 5292 0004 836C     		ldr	r3, [r0, #72]
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
+ 5293              		.loc 1 2162 27 view .LVU1943
+ 5294 0006 4B60     		str	r3, [r1, #4]
+2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
+ 5295              		.loc 1 2163 3 is_stmt 1 view .LVU1944
+2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
+ 5296              		.loc 1 2163 51 is_stmt 0 view .LVU1945
+ 5297 0008 C36C     		ldr	r3, [r0, #76]
+2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
+ 5298              		.loc 1 2163 27 view .LVU1946
+ 5299 000a 8B60     		str	r3, [r1, #8]
+2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
+ 5300              		.loc 1 2164 3 is_stmt 1 view .LVU1947
+2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
+ 5301              		.loc 1 2164 51 is_stmt 0 view .LVU1948
+ 5302 000c 036D     		ldr	r3, [r0, #80]
+2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
+ 5303              		.loc 1 2164 27 view .LVU1949
+ 5304 000e CB60     		str	r3, [r1, #12]
+2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
+ 5305              		.loc 1 2165 3 is_stmt 1 view .LVU1950
+2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
+ 5306              		.loc 1 2165 51 is_stmt 0 view .LVU1951
+ 5307 0010 436D     		ldr	r3, [r0, #84]
+2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
+ 5308              		.loc 1 2165 27 view .LVU1952
+ 5309 0012 0B61     		str	r3, [r1, #16]
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
+ 5310              		.loc 1 2166 3 is_stmt 1 view .LVU1953
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
+ 5311              		.loc 1 2166 51 is_stmt 0 view .LVU1954
+ 5312 0014 836D     		ldr	r3, [r0, #88]
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
+ 5313              		.loc 1 2166 27 view .LVU1955
+ 5314 0016 4B61     		str	r3, [r1, #20]
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+ 5315              		.loc 1 2167 3 is_stmt 1 view .LVU1956
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+ 5316              		.loc 1 2167 51 is_stmt 0 view .LVU1957
+ 5317 0018 C36D     		ldr	r3, [r0, #92]
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+ 5318              		.loc 1 2167 27 view .LVU1958
+ 5319 001a 8B61     		str	r3, [r1, #24]
+2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5320              		.loc 1 2168 3 is_stmt 1 view .LVU1959
+2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5321              		.loc 1 2168 51 is_stmt 0 view .LVU1960
+ 5322 001c 036E     		ldr	r3, [r0, #96]
+ARM GAS  /tmp/ccQEYyKb.s 			page 183
+
+
+2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5323              		.loc 1 2168 27 view .LVU1961
+ 5324 001e CB61     		str	r3, [r1, #28]
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 5325              		.loc 1 2170 3 is_stmt 1 view .LVU1962
+2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5326              		.loc 1 2171 1 is_stmt 0 view .LVU1963
+ 5327 0020 0020     		movs	r0, #0
+ 5328              	.LVL402:
+2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5329              		.loc 1 2171 1 view .LVU1964
+ 5330 0022 7047     		bx	lr
+ 5331              		.cfi_endproc
+ 5332              	.LFE163:
+ 5334              		.section	.text.HAL_SD_ConfigWideBusOperation,"ax",%progbits
+ 5335              		.align	1
+ 5336              		.global	HAL_SD_ConfigWideBusOperation
+ 5337              		.syntax unified
+ 5338              		.thumb
+ 5339              		.thumb_func
+ 5340              		.fpu fpv5-d16
+ 5342              	HAL_SD_ConfigWideBusOperation:
+ 5343              	.LVL403:
+ 5344              	.LFB164:
+2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_InitTypeDef Init;
+ 5345              		.loc 1 2185 1 is_stmt 1 view -0
+ 5346              		.cfi_startproc
+ 5347              		@ args = 0, pretend = 0, frame = 24
+ 5348              		@ frame_needed = 0, uses_anonymous_args = 0
+2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SDMMC_InitTypeDef Init;
+ 5349              		.loc 1 2185 1 is_stmt 0 view .LVU1966
+ 5350 0000 30B5     		push	{r4, r5, lr}
+ 5351              	.LCFI66:
+ 5352              		.cfi_def_cfa_offset 12
+ 5353              		.cfi_offset 4, -12
+ 5354              		.cfi_offset 5, -8
+ 5355              		.cfi_offset 14, -4
+ 5356 0002 8BB0     		sub	sp, sp, #44
+ 5357              	.LCFI67:
+ 5358              		.cfi_def_cfa_offset 56
+ 5359 0004 0446     		mov	r4, r0
+ 5360 0006 0D46     		mov	r5, r1
+2186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 5361              		.loc 1 2186 3 is_stmt 1 view .LVU1967
+2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 5362              		.loc 1 2187 3 view .LVU1968
+2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5363              		.loc 1 2188 3 view .LVU1969
+ 5364              	.LVL404:
+2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5365              		.loc 1 2191 3 view .LVU1970
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5366              		.loc 1 2194 3 view .LVU1971
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5367              		.loc 1 2194 14 is_stmt 0 view .LVU1972
+ 5368 0008 0323     		movs	r3, #3
+ 5369 000a 80F83430 		strb	r3, [r0, #52]
+ARM GAS  /tmp/ccQEYyKb.s 			page 184
+
+
+2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5370              		.loc 1 2196 3 is_stmt 1 view .LVU1973
+2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5371              		.loc 1 2196 17 is_stmt 0 view .LVU1974
+ 5372 000e 436C     		ldr	r3, [r0, #68]
+2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5373              		.loc 1 2196 5 view .LVU1975
+ 5374 0010 032B     		cmp	r3, #3
+ 5375 0012 1CD0     		beq	.L293
+2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 5376              		.loc 1 2198 5 is_stmt 1 view .LVU1976
+2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 5377              		.loc 1 2198 7 is_stmt 0 view .LVU1977
+ 5378 0014 B1F5805F 		cmp	r1, #4096
+ 5379 0018 08D0     		beq	.L302
+2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 5380              		.loc 1 2202 10 is_stmt 1 view .LVU1978
+2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 5381              		.loc 1 2202 12 is_stmt 0 view .LVU1979
+ 5382 001a B1F5006F 		cmp	r1, #2048
+ 5383 001e 0AD0     		beq	.L303
+2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 5384              		.loc 1 2208 10 is_stmt 1 view .LVU1980
+2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 5385              		.loc 1 2208 12 is_stmt 0 view .LVU1981
+ 5386 0020 79B1     		cbz	r1, .L304
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 5387              		.loc 1 2217 7 is_stmt 1 view .LVU1982
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 5388              		.loc 1 2217 22 is_stmt 0 view .LVU1983
+ 5389 0022 836B     		ldr	r3, [r0, #56]
+ 5390 0024 43F00063 		orr	r3, r3, #134217728
+ 5391 0028 8363     		str	r3, [r0, #56]
+ 5392 002a 14E0     		b	.L295
+ 5393              	.L302:
+2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 5394              		.loc 1 2200 7 is_stmt 1 view .LVU1984
+2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 5395              		.loc 1 2200 22 is_stmt 0 view .LVU1985
+ 5396 002c 836B     		ldr	r3, [r0, #56]
+ 5397 002e 43F08053 		orr	r3, r3, #268435456
+ 5398 0032 8363     		str	r3, [r0, #56]
+ 5399 0034 0FE0     		b	.L295
+ 5400              	.L303:
+2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5401              		.loc 1 2204 7 is_stmt 1 view .LVU1986
+2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5402              		.loc 1 2204 20 is_stmt 0 view .LVU1987
+ 5403 0036 FFF7FEFF 		bl	SD_WideBus_Enable
+ 5404              	.LVL405:
+2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 5405              		.loc 1 2206 7 is_stmt 1 view .LVU1988
+2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 5406              		.loc 1 2206 22 is_stmt 0 view .LVU1989
+ 5407 003a A36B     		ldr	r3, [r4, #56]
+ 5408 003c 0343     		orrs	r3, r3, r0
+ 5409 003e A363     		str	r3, [r4, #56]
+ARM GAS  /tmp/ccQEYyKb.s 			page 185
+
+
+ 5410 0040 09E0     		b	.L295
+ 5411              	.LVL406:
+ 5412              	.L304:
+2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5413              		.loc 1 2210 7 is_stmt 1 view .LVU1990
+2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5414              		.loc 1 2210 20 is_stmt 0 view .LVU1991
+ 5415 0042 FFF7FEFF 		bl	SD_WideBus_Disable
+ 5416              	.LVL407:
+2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 5417              		.loc 1 2212 7 is_stmt 1 view .LVU1992
+2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 5418              		.loc 1 2212 22 is_stmt 0 view .LVU1993
+ 5419 0046 A36B     		ldr	r3, [r4, #56]
+ 5420 0048 0343     		orrs	r3, r3, r0
+ 5421 004a A363     		str	r3, [r4, #56]
+ 5422 004c 03E0     		b	.L295
+ 5423              	.LVL408:
+ 5424              	.L293:
+2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5425              		.loc 1 2223 5 is_stmt 1 view .LVU1994
+2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5426              		.loc 1 2223 20 is_stmt 0 view .LVU1995
+ 5427 004e 836B     		ldr	r3, [r0, #56]
+ 5428 0050 43F08053 		orr	r3, r3, #268435456
+ 5429 0054 8363     		str	r3, [r0, #56]
+ 5430              	.LVL409:
+ 5431              	.L295:
+2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5432              		.loc 1 2226 3 is_stmt 1 view .LVU1996
+2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5433              		.loc 1 2226 9 is_stmt 0 view .LVU1997
+ 5434 0056 A36B     		ldr	r3, [r4, #56]
+2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5435              		.loc 1 2226 5 view .LVU1998
+ 5436 0058 C3B1     		cbz	r3, .L298
+2229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 5437              		.loc 1 2229 5 is_stmt 1 view .LVU1999
+ 5438 005a 2368     		ldr	r3, [r4]
+ 5439 005c 174A     		ldr	r2, .L305
+ 5440 005e 9A63     		str	r2, [r3, #56]
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+ 5441              		.loc 1 2230 5 view .LVU2000
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+ 5442              		.loc 1 2230 16 is_stmt 0 view .LVU2001
+ 5443 0060 0125     		movs	r5, #1
+ 5444              	.LVL410:
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+ 5445              		.loc 1 2230 16 view .LVU2002
+ 5446 0062 84F83450 		strb	r5, [r4, #52]
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5447              		.loc 1 2231 5 is_stmt 1 view .LVU2003
+ 5448              	.LVL411:
+ 5449              	.L299:
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 5450              		.loc 1 2246 3 view .LVU2004
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ARM GAS  /tmp/ccQEYyKb.s 			page 186
+
+
+ 5451              		.loc 1 2246 16 is_stmt 0 view .LVU2005
+ 5452 0066 4FF40071 		mov	r1, #512
+ 5453 006a 2068     		ldr	r0, [r4]
+ 5454 006c FFF7FEFF 		bl	SDMMC_CmdBlockLength
+ 5455              	.LVL412:
+2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5456              		.loc 1 2247 3 is_stmt 1 view .LVU2006
+2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5457              		.loc 1 2247 5 is_stmt 0 view .LVU2007
+ 5458 0070 30B1     		cbz	r0, .L300
+2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->ErrorCode |= errorstate;
+ 5459              		.loc 1 2250 5 is_stmt 1 view .LVU2008
+ 5460 0072 2368     		ldr	r3, [r4]
+ 5461 0074 1149     		ldr	r1, .L305
+ 5462 0076 9963     		str	r1, [r3, #56]
+2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+ 5463              		.loc 1 2251 5 view .LVU2009
+2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     status = HAL_ERROR;
+ 5464              		.loc 1 2251 20 is_stmt 0 view .LVU2010
+ 5465 0078 A36B     		ldr	r3, [r4, #56]
+ 5466 007a 0343     		orrs	r3, r3, r0
+ 5467 007c A363     		str	r3, [r4, #56]
+2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5468              		.loc 1 2252 5 is_stmt 1 view .LVU2011
+ 5469              	.LVL413:
+2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5470              		.loc 1 2252 12 is_stmt 0 view .LVU2012
+ 5471 007e 0125     		movs	r5, #1
+ 5472              	.LVL414:
+ 5473              	.L300:
+2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5474              		.loc 1 2256 3 is_stmt 1 view .LVU2013
+2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5475              		.loc 1 2256 14 is_stmt 0 view .LVU2014
+ 5476 0080 0123     		movs	r3, #1
+ 5477 0082 84F83430 		strb	r3, [r4, #52]
+2258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 5478              		.loc 1 2258 3 is_stmt 1 view .LVU2015
+2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5479              		.loc 1 2259 1 is_stmt 0 view .LVU2016
+ 5480 0086 2846     		mov	r0, r5
+ 5481              	.LVL415:
+2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5482              		.loc 1 2259 1 view .LVU2017
+ 5483 0088 0BB0     		add	sp, sp, #44
+ 5484              	.LCFI68:
+ 5485              		.cfi_remember_state
+ 5486              		.cfi_def_cfa_offset 12
+ 5487              		@ sp needed
+ 5488 008a 30BD     		pop	{r4, r5, pc}
+ 5489              	.LVL416:
+ 5490              	.L298:
+ 5491              	.LCFI69:
+ 5492              		.cfi_restore_state
+2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockBypass         = hsd->Init.ClockBypass;
+ 5493              		.loc 1 2236 5 is_stmt 1 view .LVU2018
+2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockBypass         = hsd->Init.ClockBypass;
+ARM GAS  /tmp/ccQEYyKb.s 			page 187
+
+
+ 5494              		.loc 1 2236 41 is_stmt 0 view .LVU2019
+ 5495 008c 6368     		ldr	r3, [r4, #4]
+2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockBypass         = hsd->Init.ClockBypass;
+ 5496              		.loc 1 2236 30 view .LVU2020
+ 5497 008e 0493     		str	r3, [sp, #16]
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
+ 5498              		.loc 1 2237 5 is_stmt 1 view .LVU2021
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
+ 5499              		.loc 1 2237 41 is_stmt 0 view .LVU2022
+ 5500 0090 A368     		ldr	r3, [r4, #8]
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
+ 5501              		.loc 1 2237 30 view .LVU2023
+ 5502 0092 0593     		str	r3, [sp, #20]
+2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.BusWide             = WideMode;
+ 5503              		.loc 1 2238 5 is_stmt 1 view .LVU2024
+2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.BusWide             = WideMode;
+ 5504              		.loc 1 2238 41 is_stmt 0 view .LVU2025
+ 5505 0094 E368     		ldr	r3, [r4, #12]
+2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.BusWide             = WideMode;
+ 5506              		.loc 1 2238 30 view .LVU2026
+ 5507 0096 0693     		str	r3, [sp, #24]
+2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+ 5508              		.loc 1 2239 5 is_stmt 1 view .LVU2027
+2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+ 5509              		.loc 1 2239 30 is_stmt 0 view .LVU2028
+ 5510 0098 0795     		str	r5, [sp, #28]
+2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockDiv            = hsd->Init.ClockDiv;
+ 5511              		.loc 1 2240 5 is_stmt 1 view .LVU2029
+2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockDiv            = hsd->Init.ClockDiv;
+ 5512              		.loc 1 2240 41 is_stmt 0 view .LVU2030
+ 5513 009a 6369     		ldr	r3, [r4, #20]
+2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     Init.ClockDiv            = hsd->Init.ClockDiv;
+ 5514              		.loc 1 2240 30 view .LVU2031
+ 5515 009c 0893     		str	r3, [sp, #32]
+2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_Init(hsd->Instance, Init);
+ 5516              		.loc 1 2241 5 is_stmt 1 view .LVU2032
+2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_Init(hsd->Instance, Init);
+ 5517              		.loc 1 2241 41 is_stmt 0 view .LVU2033
+ 5518 009e A369     		ldr	r3, [r4, #24]
+2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     (void)SDMMC_Init(hsd->Instance, Init);
+ 5519              		.loc 1 2241 30 view .LVU2034
+ 5520 00a0 0993     		str	r3, [sp, #36]
+2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5521              		.loc 1 2242 5 is_stmt 1 view .LVU2035
+2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5522              		.loc 1 2242 11 is_stmt 0 view .LVU2036
+ 5523 00a2 0AAB     		add	r3, sp, #40
+ 5524 00a4 13E90700 		ldmdb	r3, {r0, r1, r2}
+ 5525 00a8 8DE80700 		stm	sp, {r0, r1, r2}
+ 5526 00ac 04AB     		add	r3, sp, #16
+ 5527 00ae 0ECB     		ldm	r3, {r1, r2, r3}
+ 5528 00b0 2068     		ldr	r0, [r4]
+ 5529 00b2 FFF7FEFF 		bl	SDMMC_Init
+ 5530              	.LVL417:
+2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5531              		.loc 1 2188 21 view .LVU2037
+ 5532 00b6 0025     		movs	r5, #0
+ARM GAS  /tmp/ccQEYyKb.s 			page 188
+
+
+ 5533              	.LVL418:
+2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5534              		.loc 1 2188 21 view .LVU2038
+ 5535 00b8 D5E7     		b	.L299
+ 5536              	.L306:
+ 5537 00ba 00BF     		.align	2
+ 5538              	.L305:
+ 5539 00bc FF054000 		.word	4195839
+ 5540              		.cfi_endproc
+ 5541              	.LFE164:
+ 5543              		.section	.text.HAL_SD_GetCardState,"ax",%progbits
+ 5544              		.align	1
+ 5545              		.global	HAL_SD_GetCardState
+ 5546              		.syntax unified
+ 5547              		.thumb
+ 5548              		.thumb_func
+ 5549              		.fpu fpv5-d16
+ 5551              	HAL_SD_GetCardState:
+ 5552              	.LVL419:
+ 5553              	.LFB165:
+2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t cardstate;
+ 5554              		.loc 1 2267 1 is_stmt 1 view -0
+ 5555              		.cfi_startproc
+ 5556              		@ args = 0, pretend = 0, frame = 8
+ 5557              		@ frame_needed = 0, uses_anonymous_args = 0
+2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t cardstate;
+ 5558              		.loc 1 2267 1 is_stmt 0 view .LVU2040
+ 5559 0000 10B5     		push	{r4, lr}
+ 5560              	.LCFI70:
+ 5561              		.cfi_def_cfa_offset 8
+ 5562              		.cfi_offset 4, -8
+ 5563              		.cfi_offset 14, -4
+ 5564 0002 82B0     		sub	sp, sp, #8
+ 5565              	.LCFI71:
+ 5566              		.cfi_def_cfa_offset 16
+ 5567 0004 0446     		mov	r4, r0
+2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 5568              		.loc 1 2268 3 is_stmt 1 view .LVU2041
+2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t resp1 = 0;
+ 5569              		.loc 1 2269 3 view .LVU2042
+2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5570              		.loc 1 2270 3 view .LVU2043
+2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5571              		.loc 1 2270 12 is_stmt 0 view .LVU2044
+ 5572 0006 0023     		movs	r3, #0
+ 5573 0008 0193     		str	r3, [sp, #4]
+2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 5574              		.loc 1 2272 3 is_stmt 1 view .LVU2045
+2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if(errorstate != HAL_SD_ERROR_NONE)
+ 5575              		.loc 1 2272 16 is_stmt 0 view .LVU2046
+ 5576 000a 01A9     		add	r1, sp, #4
+ 5577 000c FFF7FEFF 		bl	SD_SendStatus
+ 5578              	.LVL420:
+2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5579              		.loc 1 2273 3 is_stmt 1 view .LVU2047
+2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5580              		.loc 1 2273 5 is_stmt 0 view .LVU2048
+ARM GAS  /tmp/ccQEYyKb.s 			page 189
+
+
+ 5581 0010 10B1     		cbz	r0, .L308
+2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5582              		.loc 1 2275 5 is_stmt 1 view .LVU2049
+2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5583              		.loc 1 2275 20 is_stmt 0 view .LVU2050
+ 5584 0012 A36B     		ldr	r3, [r4, #56]
+ 5585 0014 0343     		orrs	r3, r3, r0
+ 5586 0016 A363     		str	r3, [r4, #56]
+ 5587              	.L308:
+2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5588              		.loc 1 2278 3 is_stmt 1 view .LVU2051
+ 5589              	.LVL421:
+2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 5590              		.loc 1 2280 3 view .LVU2052
+2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5591              		.loc 1 2281 1 is_stmt 0 view .LVU2053
+ 5592 0018 0198     		ldr	r0, [sp, #4]
+ 5593              	.LVL422:
+2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5594              		.loc 1 2281 1 view .LVU2054
+ 5595 001a C0F34320 		ubfx	r0, r0, #9, #4
+ 5596              	.LVL423:
+2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5597              		.loc 1 2281 1 view .LVU2055
+ 5598 001e 02B0     		add	sp, sp, #8
+ 5599              	.LCFI72:
+ 5600              		.cfi_def_cfa_offset 8
+ 5601              		@ sp needed
+ 5602 0020 10BD     		pop	{r4, pc}
+2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5603              		.loc 1 2281 1 view .LVU2056
+ 5604              		.cfi_endproc
+ 5605              	.LFE165:
+ 5607              		.section	.text.SD_DMAError,"ax",%progbits
+ 5608              		.align	1
+ 5609              		.syntax unified
+ 5610              		.thumb
+ 5611              		.thumb_func
+ 5612              		.fpu fpv5-d16
+ 5614              	SD_DMAError:
+ 5615              	.LVL424:
+ 5616              	.LFB170:
+2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ 5617              		.loc 1 2496 1 is_stmt 1 view -0
+ 5618              		.cfi_startproc
+ 5619              		@ args = 0, pretend = 0, frame = 0
+ 5620              		@ frame_needed = 0, uses_anonymous_args = 0
+2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ 5621              		.loc 1 2496 1 is_stmt 0 view .LVU2058
+ 5622 0000 10B5     		push	{r4, lr}
+ 5623              	.LCFI73:
+ 5624              		.cfi_def_cfa_offset 8
+ 5625              		.cfi_offset 4, -8
+ 5626              		.cfi_offset 14, -4
+2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+ 5627              		.loc 1 2497 3 is_stmt 1 view .LVU2059
+2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+ARM GAS  /tmp/ccQEYyKb.s 			page 190
+
+
+ 5628              		.loc 1 2497 21 is_stmt 0 view .LVU2060
+ 5629 0002 846B     		ldr	r4, [r0, #56]
+ 5630              	.LVL425:
+2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t RxErrorCode, TxErrorCode;
+ 5631              		.loc 1 2498 3 is_stmt 1 view .LVU2061
+2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5632              		.loc 1 2499 3 view .LVU2062
+2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5633              		.loc 1 2502 3 view .LVU2063
+2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5634              		.loc 1 2502 6 is_stmt 0 view .LVU2064
+ 5635 0004 FFF7FEFF 		bl	HAL_DMA_GetError
+ 5636              	.LVL426:
+2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5637              		.loc 1 2502 5 view .LVU2065
+ 5638 0008 0228     		cmp	r0, #2
+ 5639 000a 0AD0     		beq	.L310
+2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     TxErrorCode = hsd->hdmatx->ErrorCode;  
+ 5640              		.loc 1 2504 5 is_stmt 1 view .LVU2066
+2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     TxErrorCode = hsd->hdmatx->ErrorCode;  
+ 5641              		.loc 1 2504 22 is_stmt 0 view .LVU2067
+ 5642 000c 236C     		ldr	r3, [r4, #64]
+2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     TxErrorCode = hsd->hdmatx->ErrorCode;  
+ 5643              		.loc 1 2504 17 view .LVU2068
+ 5644 000e 5A6D     		ldr	r2, [r3, #84]
+ 5645              	.LVL427:
+2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
+ 5646              		.loc 1 2505 5 is_stmt 1 view .LVU2069
+2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
+ 5647              		.loc 1 2505 22 is_stmt 0 view .LVU2070
+ 5648 0010 E36B     		ldr	r3, [r4, #60]
+2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
+ 5649              		.loc 1 2505 17 view .LVU2071
+ 5650 0012 5B6D     		ldr	r3, [r3, #84]
+ 5651              	.LVL428:
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 5652              		.loc 1 2506 5 is_stmt 1 view .LVU2072
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 5653              		.loc 1 2506 7 is_stmt 0 view .LVU2073
+ 5654 0014 012B     		cmp	r3, #1
+ 5655 0016 18BF     		it	ne
+ 5656 0018 012A     		cmpne	r2, #1
+ 5657 001a 03D0     		beq	.L315
+ 5658              	.LVL429:
+ 5659              	.L312:
+2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+ 5660              		.loc 1 2529 5 is_stmt 1 view .LVU2074
+ 5661 001c 2046     		mov	r0, r4
+ 5662 001e FFF7FEFF 		bl	HAL_SD_ErrorCallback
+ 5663              	.LVL430:
+ 5664              	.L310:
+2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5665              		.loc 1 2532 1 is_stmt 0 view .LVU2075
+ 5666 0022 10BD     		pop	{r4, pc}
+ 5667              	.LVL431:
+ 5668              	.L315:
+2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 191
+
+
+ 5669              		.loc 1 2509 7 is_stmt 1 view .LVU2076
+ 5670 0024 2368     		ldr	r3, [r4]
+ 5671              	.LVL432:
+2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5672              		.loc 1 2509 7 is_stmt 0 view .LVU2077
+ 5673 0026 0F4A     		ldr	r2, .L317
+ 5674              	.LVL433:
+2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5675              		.loc 1 2509 7 view .LVU2078
+ 5676 0028 9A63     		str	r2, [r3, #56]
+2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ 5677              		.loc 1 2512 7 is_stmt 1 view .LVU2079
+ 5678 002a 2268     		ldr	r2, [r4]
+ 5679 002c D36B     		ldr	r3, [r2, #60]
+ 5680 002e 23F49D73 		bic	r3, r3, #314
+ 5681 0032 D363     		str	r3, [r2, #60]
+2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       CardState = HAL_SD_GetCardState(hsd);
+ 5682              		.loc 1 2515 7 view .LVU2080
+2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       CardState = HAL_SD_GetCardState(hsd);
+ 5683              		.loc 1 2515 22 is_stmt 0 view .LVU2081
+ 5684 0034 A36B     		ldr	r3, [r4, #56]
+ 5685 0036 43F08043 		orr	r3, r3, #1073741824
+ 5686 003a A363     		str	r3, [r4, #56]
+2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ 5687              		.loc 1 2516 7 is_stmt 1 view .LVU2082
+2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ 5688              		.loc 1 2516 19 is_stmt 0 view .LVU2083
+ 5689 003c 2046     		mov	r0, r4
+ 5690 003e FFF7FEFF 		bl	HAL_SD_GetCardState
+ 5691              	.LVL434:
+2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 5692              		.loc 1 2517 7 is_stmt 1 view .LVU2084
+2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 5693              		.loc 1 2517 47 is_stmt 0 view .LVU2085
+ 5694 0042 0538     		subs	r0, r0, #5
+ 5695              	.LVL435:
+2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 5696              		.loc 1 2517 9 view .LVU2086
+ 5697 0044 0128     		cmp	r0, #1
+ 5698 0046 05D9     		bls	.L316
+ 5699              	.LVL436:
+ 5700              	.L313:
+2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 5701              		.loc 1 2522 7 is_stmt 1 view .LVU2087
+2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 5702              		.loc 1 2522 17 is_stmt 0 view .LVU2088
+ 5703 0048 0123     		movs	r3, #1
+ 5704 004a 84F83430 		strb	r3, [r4, #52]
+2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 5705              		.loc 1 2523 7 is_stmt 1 view .LVU2089
+2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 5706              		.loc 1 2523 20 is_stmt 0 view .LVU2090
+ 5707 004e 0023     		movs	r3, #0
+ 5708 0050 2363     		str	r3, [r4, #48]
+ 5709 0052 E3E7     		b	.L312
+ 5710              	.LVL437:
+ 5711              	.L316:
+ARM GAS  /tmp/ccQEYyKb.s 			page 192
+
+
+2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 5712              		.loc 1 2519 9 is_stmt 1 view .LVU2091
+2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 5713              		.loc 1 2519 27 is_stmt 0 view .LVU2092
+ 5714 0054 2068     		ldr	r0, [r4]
+ 5715              	.LVL438:
+2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 5716              		.loc 1 2519 27 view .LVU2093
+ 5717 0056 FFF7FEFF 		bl	SDMMC_CmdStopTransfer
+ 5718              	.LVL439:
+2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 5719              		.loc 1 2519 24 view .LVU2094
+ 5720 005a A36B     		ldr	r3, [r4, #56]
+ 5721 005c 0343     		orrs	r3, r3, r0
+ 5722 005e A363     		str	r3, [r4, #56]
+ 5723 0060 F2E7     		b	.L313
+ 5724              	.L318:
+ 5725 0062 00BF     		.align	2
+ 5726              	.L317:
+ 5727 0064 FF054000 		.word	4195839
+ 5728              		.cfi_endproc
+ 5729              	.LFE170:
+ 5731              		.section	.text.SD_DMATxAbort,"ax",%progbits
+ 5732              		.align	1
+ 5733              		.syntax unified
+ 5734              		.thumb
+ 5735              		.thumb_func
+ 5736              		.fpu fpv5-d16
+ 5738              	SD_DMATxAbort:
+ 5739              	.LVL440:
+ 5740              	.LFB171:
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ 5741              		.loc 1 2540 1 is_stmt 1 view -0
+ 5742              		.cfi_startproc
+ 5743              		@ args = 0, pretend = 0, frame = 0
+ 5744              		@ frame_needed = 0, uses_anonymous_args = 0
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ 5745              		.loc 1 2540 1 is_stmt 0 view .LVU2096
+ 5746 0000 10B5     		push	{r4, lr}
+ 5747              	.LCFI74:
+ 5748              		.cfi_def_cfa_offset 8
+ 5749              		.cfi_offset 4, -8
+ 5750              		.cfi_offset 14, -4
+2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+ 5751              		.loc 1 2541 3 is_stmt 1 view .LVU2097
+2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+ 5752              		.loc 1 2541 21 is_stmt 0 view .LVU2098
+ 5753 0002 846B     		ldr	r4, [r0, #56]
+ 5754              	.LVL441:
+2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5755              		.loc 1 2542 3 is_stmt 1 view .LVU2099
+2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5756              		.loc 1 2545 3 view .LVU2100
+ 5757 0004 2368     		ldr	r3, [r4]
+ 5758 0006 40F23A52 		movw	r2, #1338
+ 5759 000a 9A63     		str	r2, [r3, #56]
+2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+ARM GAS  /tmp/ccQEYyKb.s 			page 193
+
+
+ 5760              		.loc 1 2547 3 view .LVU2101
+2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+ 5761              		.loc 1 2547 15 is_stmt 0 view .LVU2102
+ 5762 000c 2046     		mov	r0, r4
+ 5763              	.LVL442:
+2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+ 5764              		.loc 1 2547 15 view .LVU2103
+ 5765 000e FFF7FEFF 		bl	HAL_SD_GetCardState
+ 5766              	.LVL443:
+2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Context = SD_CONTEXT_NONE;
+ 5767              		.loc 1 2548 3 is_stmt 1 view .LVU2104
+2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Context = SD_CONTEXT_NONE;
+ 5768              		.loc 1 2548 14 is_stmt 0 view .LVU2105
+ 5769 0012 0123     		movs	r3, #1
+ 5770 0014 84F83430 		strb	r3, [r4, #52]
+2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ 5771              		.loc 1 2549 3 is_stmt 1 view .LVU2106
+2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ 5772              		.loc 1 2549 16 is_stmt 0 view .LVU2107
+ 5773 0018 0023     		movs	r3, #0
+ 5774 001a 2363     		str	r3, [r4, #48]
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5775              		.loc 1 2550 3 is_stmt 1 view .LVU2108
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5776              		.loc 1 2550 43 is_stmt 0 view .LVU2109
+ 5777 001c 0538     		subs	r0, r0, #5
+ 5778              	.LVL444:
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5779              		.loc 1 2550 5 view .LVU2110
+ 5780 001e 0128     		cmp	r0, #1
+ 5781 0020 05D9     		bls	.L324
+ 5782              	.LVL445:
+ 5783              	.L320:
+2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5784              		.loc 1 2555 3 is_stmt 1 view .LVU2111
+2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5785              		.loc 1 2555 9 is_stmt 0 view .LVU2112
+ 5786 0022 A36B     		ldr	r3, [r4, #56]
+2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5787              		.loc 1 2555 5 view .LVU2113
+ 5788 0024 53B9     		cbnz	r3, .L321
+2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+ 5789              		.loc 1 2560 5 is_stmt 1 view .LVU2114
+ 5790 0026 2046     		mov	r0, r4
+ 5791 0028 FFF7FEFF 		bl	HAL_SD_AbortCallback
+ 5792              	.LVL446:
+ 5793              	.L319:
+2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5794              		.loc 1 2571 1 is_stmt 0 view .LVU2115
+ 5795 002c 10BD     		pop	{r4, pc}
+ 5796              	.LVL447:
+ 5797              	.L324:
+2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5798              		.loc 1 2552 5 is_stmt 1 view .LVU2116
+2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5799              		.loc 1 2552 23 is_stmt 0 view .LVU2117
+ 5800 002e 2068     		ldr	r0, [r4]
+ARM GAS  /tmp/ccQEYyKb.s 			page 194
+
+
+ 5801              	.LVL448:
+2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5802              		.loc 1 2552 23 view .LVU2118
+ 5803 0030 FFF7FEFF 		bl	SDMMC_CmdStopTransfer
+ 5804              	.LVL449:
+2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5805              		.loc 1 2552 20 view .LVU2119
+ 5806 0034 A36B     		ldr	r3, [r4, #56]
+ 5807 0036 0343     		orrs	r3, r3, r0
+ 5808 0038 A363     		str	r3, [r4, #56]
+ 5809 003a F2E7     		b	.L320
+ 5810              	.L321:
+2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+ 5811              		.loc 1 2568 5 is_stmt 1 view .LVU2120
+ 5812 003c 2046     		mov	r0, r4
+ 5813 003e FFF7FEFF 		bl	HAL_SD_ErrorCallback
+ 5814              	.LVL450:
+2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5815              		.loc 1 2571 1 is_stmt 0 view .LVU2121
+ 5816 0042 F3E7     		b	.L319
+ 5817              		.cfi_endproc
+ 5818              	.LFE171:
+ 5820              		.section	.text.SD_DMARxAbort,"ax",%progbits
+ 5821              		.align	1
+ 5822              		.syntax unified
+ 5823              		.thumb
+ 5824              		.thumb_func
+ 5825              		.fpu fpv5-d16
+ 5827              	SD_DMARxAbort:
+ 5828              	.LVL451:
+ 5829              	.LFB172:
+2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ 5830              		.loc 1 2579 1 is_stmt 1 view -0
+ 5831              		.cfi_startproc
+ 5832              		@ args = 0, pretend = 0, frame = 0
+ 5833              		@ frame_needed = 0, uses_anonymous_args = 0
+2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ 5834              		.loc 1 2579 1 is_stmt 0 view .LVU2123
+ 5835 0000 10B5     		push	{r4, lr}
+ 5836              	.LCFI75:
+ 5837              		.cfi_def_cfa_offset 8
+ 5838              		.cfi_offset 4, -8
+ 5839              		.cfi_offset 14, -4
+2580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+ 5840              		.loc 1 2580 3 is_stmt 1 view .LVU2124
+2580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+ 5841              		.loc 1 2580 21 is_stmt 0 view .LVU2125
+ 5842 0002 846B     		ldr	r4, [r0, #56]
+ 5843              	.LVL452:
+2581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5844              		.loc 1 2581 3 is_stmt 1 view .LVU2126
+2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5845              		.loc 1 2584 3 view .LVU2127
+ 5846 0004 2368     		ldr	r3, [r4]
+ 5847 0006 40F23A52 		movw	r2, #1338
+ 5848 000a 9A63     		str	r2, [r3, #56]
+2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+ARM GAS  /tmp/ccQEYyKb.s 			page 195
+
+
+ 5849              		.loc 1 2586 3 view .LVU2128
+2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+ 5850              		.loc 1 2586 15 is_stmt 0 view .LVU2129
+ 5851 000c 2046     		mov	r0, r4
+ 5852              	.LVL453:
+2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->State = HAL_SD_STATE_READY;
+ 5853              		.loc 1 2586 15 view .LVU2130
+ 5854 000e FFF7FEFF 		bl	HAL_SD_GetCardState
+ 5855              	.LVL454:
+2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Context = SD_CONTEXT_NONE;
+ 5856              		.loc 1 2587 3 is_stmt 1 view .LVU2131
+2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   hsd->Context = SD_CONTEXT_NONE;
+ 5857              		.loc 1 2587 14 is_stmt 0 view .LVU2132
+ 5858 0012 0123     		movs	r3, #1
+ 5859 0014 84F83430 		strb	r3, [r4, #52]
+2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ 5860              		.loc 1 2588 3 is_stmt 1 view .LVU2133
+2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ 5861              		.loc 1 2588 16 is_stmt 0 view .LVU2134
+ 5862 0018 0023     		movs	r3, #0
+ 5863 001a 2363     		str	r3, [r4, #48]
+2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5864              		.loc 1 2589 3 is_stmt 1 view .LVU2135
+2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5865              		.loc 1 2589 43 is_stmt 0 view .LVU2136
+ 5866 001c 0538     		subs	r0, r0, #5
+ 5867              	.LVL455:
+2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5868              		.loc 1 2589 5 view .LVU2137
+ 5869 001e 0128     		cmp	r0, #1
+ 5870 0020 05D9     		bls	.L330
+ 5871              	.LVL456:
+ 5872              	.L326:
+2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5873              		.loc 1 2594 3 is_stmt 1 view .LVU2138
+2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5874              		.loc 1 2594 9 is_stmt 0 view .LVU2139
+ 5875 0022 A36B     		ldr	r3, [r4, #56]
+2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5876              		.loc 1 2594 5 view .LVU2140
+ 5877 0024 53B9     		cbnz	r3, .L327
+2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+ 5878              		.loc 1 2599 5 is_stmt 1 view .LVU2141
+ 5879 0026 2046     		mov	r0, r4
+ 5880 0028 FFF7FEFF 		bl	HAL_SD_AbortCallback
+ 5881              	.LVL457:
+ 5882              	.L325:
+2610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5883              		.loc 1 2610 1 is_stmt 0 view .LVU2142
+ 5884 002c 10BD     		pop	{r4, pc}
+ 5885              	.LVL458:
+ 5886              	.L330:
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5887              		.loc 1 2591 5 is_stmt 1 view .LVU2143
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5888              		.loc 1 2591 23 is_stmt 0 view .LVU2144
+ 5889 002e 2068     		ldr	r0, [r4]
+ARM GAS  /tmp/ccQEYyKb.s 			page 196
+
+
+ 5890              	.LVL459:
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5891              		.loc 1 2591 23 view .LVU2145
+ 5892 0030 FFF7FEFF 		bl	SDMMC_CmdStopTransfer
+ 5893              	.LVL460:
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 5894              		.loc 1 2591 20 view .LVU2146
+ 5895 0034 A36B     		ldr	r3, [r4, #56]
+ 5896 0036 0343     		orrs	r3, r3, r0
+ 5897 0038 A363     		str	r3, [r4, #56]
+ 5898 003a F2E7     		b	.L326
+ 5899              	.L327:
+2607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif
+ 5900              		.loc 1 2607 5 is_stmt 1 view .LVU2147
+ 5901 003c 2046     		mov	r0, r4
+ 5902 003e FFF7FEFF 		bl	HAL_SD_ErrorCallback
+ 5903              	.LVL461:
+2610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5904              		.loc 1 2610 1 is_stmt 0 view .LVU2148
+ 5905 0042 F3E7     		b	.L325
+ 5906              		.cfi_endproc
+ 5907              	.LFE172:
+ 5909              		.section	.text.HAL_SD_IRQHandler,"ax",%progbits
+ 5910              		.align	1
+ 5911              		.global	HAL_SD_IRQHandler
+ 5912              		.syntax unified
+ 5913              		.thumb
+ 5914              		.thumb_func
+ 5915              		.fpu fpv5-d16
+ 5917              	HAL_SD_IRQHandler:
+ 5918              	.LVL462:
+ 5919              	.LFB153:
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 5920              		.loc 1 1485 1 is_stmt 1 view -0
+ 5921              		.cfi_startproc
+ 5922              		@ args = 0, pretend = 0, frame = 0
+ 5923              		@ frame_needed = 0, uses_anonymous_args = 0
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t errorstate;
+ 5924              		.loc 1 1485 1 is_stmt 0 view .LVU2150
+ 5925 0000 38B5     		push	{r3, r4, r5, lr}
+ 5926              	.LCFI76:
+ 5927              		.cfi_def_cfa_offset 16
+ 5928              		.cfi_offset 3, -16
+ 5929              		.cfi_offset 4, -12
+ 5930              		.cfi_offset 5, -8
+ 5931              		.cfi_offset 14, -4
+ 5932 0002 0446     		mov	r4, r0
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t context = hsd->Context;
+ 5933              		.loc 1 1486 3 is_stmt 1 view .LVU2151
+1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5934              		.loc 1 1487 3 view .LVU2152
+1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5935              		.loc 1 1487 12 is_stmt 0 view .LVU2153
+ 5936 0004 056B     		ldr	r5, [r0, #48]
+ 5937              	.LVL463:
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5938              		.loc 1 1490 3 is_stmt 1 view .LVU2154
+ARM GAS  /tmp/ccQEYyKb.s 			page 197
+
+
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5939              		.loc 1 1490 7 is_stmt 0 view .LVU2155
+ 5940 0006 0368     		ldr	r3, [r0]
+ 5941 0008 5A6B     		ldr	r2, [r3, #52]
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5942              		.loc 1 1490 5 view .LVU2156
+ 5943 000a 12F4004F 		tst	r2, #32768
+ 5944 000e 02D0     		beq	.L332
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5945              		.loc 1 1490 61 discriminator 1 view .LVU2157
+ 5946 0010 15F0080F 		tst	r5, #8
+ 5947 0014 26D1     		bne	.L348
+ 5948              	.L332:
+1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5949              		.loc 1 1495 8 is_stmt 1 view .LVU2158
+1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5950              		.loc 1 1495 11 is_stmt 0 view .LVU2159
+ 5951 0016 5A6B     		ldr	r2, [r3, #52]
+1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 5952              		.loc 1 1495 10 view .LVU2160
+ 5953 0018 12F4807F 		tst	r2, #256
+ 5954 001c 58D0     		beq	.L334
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5955              		.loc 1 1497 5 is_stmt 1 view .LVU2161
+ 5956 001e 4FF48072 		mov	r2, #256
+ 5957 0022 9A63     		str	r2, [r3, #56]
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                              SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR  | SDMMC_IT_TXFIFOHE |\
+ 5958              		.loc 1 1499 5 view .LVU2162
+ 5959 0024 2268     		ldr	r2, [r4]
+ 5960 0026 D16B     		ldr	r1, [r2, #60]
+ 5961 0028 644B     		ldr	r3, .L354
+ 5962 002a 0B40     		ands	r3, r3, r1
+ 5963 002c D363     		str	r3, [r2, #60]
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     
+ 5964              		.loc 1 1503 5 view .LVU2163
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     
+ 5965              		.loc 1 1503 8 is_stmt 0 view .LVU2164
+ 5966 002e 2268     		ldr	r2, [r4]
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     
+ 5967              		.loc 1 1503 26 view .LVU2165
+ 5968 0030 D36A     		ldr	r3, [r2, #44]
+ 5969 0032 23F00103 		bic	r3, r3, #1
+ 5970 0036 D362     		str	r3, [r2, #44]
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 5971              		.loc 1 1505 5 is_stmt 1 view .LVU2166
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 5972              		.loc 1 1505 7 is_stmt 0 view .LVU2167
+ 5973 0038 15F0080F 		tst	r5, #8
+ 5974 003c 26D0     		beq	.L335
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 5975              		.loc 1 1507 7 is_stmt 1 view .LVU2168
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 5976              		.loc 1 1507 9 is_stmt 0 view .LVU2169
+ 5977 003e 15F0220F 		tst	r5, #34
+ 5978 0042 12D1     		bne	.L349
+ 5979              	.LVL464:
+ 5980              	.L336:
+ARM GAS  /tmp/ccQEYyKb.s 			page 198
+
+
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 5981              		.loc 1 1522 7 is_stmt 1 view .LVU2170
+ 5982 0044 2368     		ldr	r3, [r4]
+ 5983 0046 40F23A52 		movw	r2, #1338
+ 5984 004a 9A63     		str	r2, [r3, #56]
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 5985              		.loc 1 1524 7 view .LVU2171
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 5986              		.loc 1 1524 18 is_stmt 0 view .LVU2172
+ 5987 004c 0123     		movs	r3, #1
+ 5988 004e 84F83430 		strb	r3, [r4, #52]
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_B
+ 5989              		.loc 1 1525 7 is_stmt 1 view .LVU2173
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_B
+ 5990              		.loc 1 1525 20 is_stmt 0 view .LVU2174
+ 5991 0052 0023     		movs	r3, #0
+ 5992 0054 2363     		str	r3, [r4, #48]
+1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 5993              		.loc 1 1526 7 is_stmt 1 view .LVU2175
+1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 5994              		.loc 1 1526 9 is_stmt 0 view .LVU2176
+ 5995 0056 15F0030F 		tst	r5, #3
+ 5996 005a 13D0     		beq	.L337
+1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 5997              		.loc 1 1531 9 is_stmt 1 view .LVU2177
+ 5998 005c 2046     		mov	r0, r4
+ 5999 005e FFF7FEFF 		bl	HAL_SD_RxCpltCallback
+ 6000              	.LVL465:
+ 6001 0062 01E0     		b	.L331
+ 6002              	.LVL466:
+ 6003              	.L348:
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 6004              		.loc 1 1492 5 view .LVU2178
+ 6005 0064 FFF7FEFF 		bl	SD_Read_IT
+ 6006              	.LVL467:
+ 6007              	.L331:
+1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6008              		.loc 1 1668 1 is_stmt 0 view .LVU2179
+ 6009 0068 38BD     		pop	{r3, r4, r5, pc}
+ 6010              	.LVL468:
+ 6011              	.L349:
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ 6012              		.loc 1 1509 9 is_stmt 1 view .LVU2180
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ 6013              		.loc 1 1509 22 is_stmt 0 view .LVU2181
+ 6014 006a 2068     		ldr	r0, [r4]
+ 6015              	.LVL469:
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ 6016              		.loc 1 1509 22 view .LVU2182
+ 6017 006c FFF7FEFF 		bl	SDMMC_CmdStopTransfer
+ 6018              	.LVL470:
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 6019              		.loc 1 1510 9 is_stmt 1 view .LVU2183
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 6020              		.loc 1 1510 11 is_stmt 0 view .LVU2184
+ 6021 0070 0346     		mov	r3, r0
+ 6022 0072 0028     		cmp	r0, #0
+ARM GAS  /tmp/ccQEYyKb.s 			page 199
+
+
+ 6023 0074 E6D0     		beq	.L336
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ 6024              		.loc 1 1512 11 is_stmt 1 view .LVU2185
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ 6025              		.loc 1 1512 26 is_stmt 0 view .LVU2186
+ 6026 0076 A26B     		ldr	r2, [r4, #56]
+ 6027 0078 1343     		orrs	r3, r3, r2
+ 6028 007a A363     		str	r3, [r4, #56]
+1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 6029              		.loc 1 1516 11 is_stmt 1 view .LVU2187
+ 6030 007c 2046     		mov	r0, r4
+ 6031              	.LVL471:
+1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 6032              		.loc 1 1516 11 is_stmt 0 view .LVU2188
+ 6033 007e FFF7FEFF 		bl	HAL_SD_ErrorCallback
+ 6034              	.LVL472:
+ 6035 0082 DFE7     		b	.L336
+ 6036              	.L337:
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 6037              		.loc 1 1539 9 is_stmt 1 view .LVU2189
+ 6038 0084 2046     		mov	r0, r4
+ 6039 0086 FFF7FEFF 		bl	HAL_SD_TxCpltCallback
+ 6040              	.LVL473:
+ 6041 008a EDE7     		b	.L331
+ 6042              	.LVL474:
+ 6043              	.L335:
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6044              		.loc 1 1543 10 view .LVU2190
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6045              		.loc 1 1543 12 is_stmt 0 view .LVU2191
+ 6046 008c 15F0800F 		tst	r5, #128
+ 6047 0090 EAD0     		beq	.L331
+1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6048              		.loc 1 1545 7 is_stmt 1 view .LVU2192
+1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6049              		.loc 1 1545 9 is_stmt 0 view .LVU2193
+ 6050 0092 15F0200F 		tst	r5, #32
+ 6051 0096 0ED1     		bne	.L350
+ 6052              	.LVL475:
+ 6053              	.L338:
+1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6054              		.loc 1 1558 7 is_stmt 1 view .LVU2194
+1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6055              		.loc 1 1558 9 is_stmt 0 view .LVU2195
+ 6056 0098 15F0030F 		tst	r5, #3
+ 6057 009c E4D1     		bne	.L331
+1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6058              		.loc 1 1562 9 is_stmt 1 view .LVU2196
+1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6059              		.loc 1 1562 12 is_stmt 0 view .LVU2197
+ 6060 009e 2268     		ldr	r2, [r4]
+1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6061              		.loc 1 1562 30 view .LVU2198
+ 6062 00a0 D36A     		ldr	r3, [r2, #44]
+ 6063 00a2 23F00803 		bic	r3, r3, #8
+ 6064 00a6 D362     		str	r3, [r2, #44]
+1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ARM GAS  /tmp/ccQEYyKb.s 			page 200
+
+
+ 6065              		.loc 1 1564 9 is_stmt 1 view .LVU2199
+1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6066              		.loc 1 1564 20 is_stmt 0 view .LVU2200
+ 6067 00a8 0123     		movs	r3, #1
+ 6068 00aa 84F83430 		strb	r3, [r4, #52]
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 6069              		.loc 1 1569 9 is_stmt 1 view .LVU2201
+ 6070 00ae 2046     		mov	r0, r4
+ 6071 00b0 FFF7FEFF 		bl	HAL_SD_TxCpltCallback
+ 6072              	.LVL476:
+ 6073 00b4 D8E7     		b	.L331
+ 6074              	.LVL477:
+ 6075              	.L350:
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ 6076              		.loc 1 1547 9 view .LVU2202
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ 6077              		.loc 1 1547 22 is_stmt 0 view .LVU2203
+ 6078 00b6 2068     		ldr	r0, [r4]
+ 6079              	.LVL478:
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         if(errorstate != HAL_SD_ERROR_NONE)
+ 6080              		.loc 1 1547 22 view .LVU2204
+ 6081 00b8 FFF7FEFF 		bl	SDMMC_CmdStopTransfer
+ 6082              	.LVL479:
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 6083              		.loc 1 1548 9 is_stmt 1 view .LVU2205
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 6084              		.loc 1 1548 11 is_stmt 0 view .LVU2206
+ 6085 00bc 0346     		mov	r3, r0
+ 6086 00be 0028     		cmp	r0, #0
+ 6087 00c0 EAD0     		beq	.L338
+1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ 6088              		.loc 1 1550 11 is_stmt 1 view .LVU2207
+1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ 6089              		.loc 1 1550 26 is_stmt 0 view .LVU2208
+ 6090 00c2 A26B     		ldr	r2, [r4, #56]
+ 6091 00c4 1343     		orrs	r3, r3, r2
+ 6092 00c6 A363     		str	r3, [r4, #56]
+1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 6093              		.loc 1 1554 11 is_stmt 1 view .LVU2209
+ 6094 00c8 2046     		mov	r0, r4
+ 6095              	.LVL480:
+1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 6096              		.loc 1 1554 11 is_stmt 0 view .LVU2210
+ 6097 00ca FFF7FEFF 		bl	HAL_SD_ErrorCallback
+ 6098              	.LVL481:
+ 6099 00ce E3E7     		b	.L338
+ 6100              	.LVL482:
+ 6101              	.L334:
+1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6102              		.loc 1 1579 8 is_stmt 1 view .LVU2211
+1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6103              		.loc 1 1579 12 is_stmt 0 view .LVU2212
+ 6104 00d0 5A6B     		ldr	r2, [r3, #52]
+1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6105              		.loc 1 1579 10 view .LVU2213
+ 6106 00d2 12F4804F 		tst	r2, #16384
+ 6107 00d6 02D0     		beq	.L339
+ARM GAS  /tmp/ccQEYyKb.s 			page 201
+
+
+1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6108              		.loc 1 1579 66 discriminator 1 view .LVU2214
+ 6109 00d8 15F0080F 		tst	r5, #8
+ 6110 00dc 4AD1     		bne	.L351
+ 6111              	.L339:
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6112              		.loc 1 1584 8 is_stmt 1 view .LVU2215
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6113              		.loc 1 1584 11 is_stmt 0 view .LVU2216
+ 6114 00de 5A6B     		ldr	r2, [r3, #52]
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6115              		.loc 1 1584 10 view .LVU2217
+ 6116 00e0 12F03A0F 		tst	r2, #58
+ 6117 00e4 C0D0     		beq	.L331
+1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6118              		.loc 1 1587 5 is_stmt 1 view .LVU2218
+1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6119              		.loc 1 1587 8 is_stmt 0 view .LVU2219
+ 6120 00e6 5A6B     		ldr	r2, [r3, #52]
+1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6121              		.loc 1 1587 7 view .LVU2220
+ 6122 00e8 12F0020F 		tst	r2, #2
+ 6123 00ec 03D0     		beq	.L340
+1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6124              		.loc 1 1589 7 is_stmt 1 view .LVU2221
+1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6125              		.loc 1 1589 22 is_stmt 0 view .LVU2222
+ 6126 00ee A26B     		ldr	r2, [r4, #56]
+ 6127 00f0 42F00202 		orr	r2, r2, #2
+ 6128 00f4 A263     		str	r2, [r4, #56]
+ 6129              	.L340:
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6130              		.loc 1 1591 5 is_stmt 1 view .LVU2223
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6131              		.loc 1 1591 8 is_stmt 0 view .LVU2224
+ 6132 00f6 5A6B     		ldr	r2, [r3, #52]
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6133              		.loc 1 1591 7 view .LVU2225
+ 6134 00f8 12F0080F 		tst	r2, #8
+ 6135 00fc 03D0     		beq	.L341
+1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6136              		.loc 1 1593 7 is_stmt 1 view .LVU2226
+1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6137              		.loc 1 1593 22 is_stmt 0 view .LVU2227
+ 6138 00fe A26B     		ldr	r2, [r4, #56]
+ 6139 0100 42F00802 		orr	r2, r2, #8
+ 6140 0104 A263     		str	r2, [r4, #56]
+ 6141              	.L341:
+1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6142              		.loc 1 1595 5 is_stmt 1 view .LVU2228
+1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6143              		.loc 1 1595 8 is_stmt 0 view .LVU2229
+ 6144 0106 5A6B     		ldr	r2, [r3, #52]
+1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6145              		.loc 1 1595 7 view .LVU2230
+ 6146 0108 12F0200F 		tst	r2, #32
+ 6147 010c 03D0     		beq	.L342
+ARM GAS  /tmp/ccQEYyKb.s 			page 202
+
+
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6148              		.loc 1 1597 7 is_stmt 1 view .LVU2231
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6149              		.loc 1 1597 22 is_stmt 0 view .LVU2232
+ 6150 010e A26B     		ldr	r2, [r4, #56]
+ 6151 0110 42F02002 		orr	r2, r2, #32
+ 6152 0114 A263     		str	r2, [r4, #56]
+ 6153              	.L342:
+1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6154              		.loc 1 1599 5 is_stmt 1 view .LVU2233
+1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6155              		.loc 1 1599 8 is_stmt 0 view .LVU2234
+ 6156 0116 5A6B     		ldr	r2, [r3, #52]
+1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6157              		.loc 1 1599 7 view .LVU2235
+ 6158 0118 12F0100F 		tst	r2, #16
+ 6159 011c 03D0     		beq	.L343
+1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6160              		.loc 1 1601 7 is_stmt 1 view .LVU2236
+1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6161              		.loc 1 1601 22 is_stmt 0 view .LVU2237
+ 6162 011e A26B     		ldr	r2, [r4, #56]
+ 6163 0120 42F01002 		orr	r2, r2, #16
+ 6164 0124 A263     		str	r2, [r4, #56]
+ 6165              	.L343:
+1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6166              		.loc 1 1605 5 is_stmt 1 view .LVU2238
+ 6167 0126 40F23A52 		movw	r2, #1338
+ 6168 012a 9A63     		str	r2, [r3, #56]
+1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                              SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ 6169              		.loc 1 1608 5 view .LVU2239
+ 6170 012c 2268     		ldr	r2, [r4]
+ 6171 012e D36B     		ldr	r3, [r2, #60]
+ 6172 0130 23F49D73 		bic	r3, r3, #314
+ 6173 0134 D363     		str	r3, [r2, #60]
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6174              		.loc 1 1611 5 view .LVU2240
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6175              		.loc 1 1611 23 is_stmt 0 view .LVU2241
+ 6176 0136 2068     		ldr	r0, [r4]
+ 6177              	.LVL483:
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6178              		.loc 1 1611 23 view .LVU2242
+ 6179 0138 FFF7FEFF 		bl	SDMMC_CmdStopTransfer
+ 6180              	.LVL484:
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6181              		.loc 1 1611 20 view .LVU2243
+ 6182 013c A36B     		ldr	r3, [r4, #56]
+ 6183 013e 0343     		orrs	r3, r3, r0
+ 6184 0140 A363     		str	r3, [r4, #56]
+1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6185              		.loc 1 1613 5 is_stmt 1 view .LVU2244
+1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6186              		.loc 1 1613 7 is_stmt 0 view .LVU2245
+ 6187 0142 15F0080F 		tst	r5, #8
+ 6188 0146 19D1     		bne	.L352
+1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ARM GAS  /tmp/ccQEYyKb.s 			page 203
+
+
+ 6189              		.loc 1 1624 10 is_stmt 1 view .LVU2246
+1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6190              		.loc 1 1624 12 is_stmt 0 view .LVU2247
+ 6191 0148 15F0800F 		tst	r5, #128
+ 6192 014c 8CD0     		beq	.L331
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6193              		.loc 1 1627 7 is_stmt 1 view .LVU2248
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6194              		.loc 1 1627 9 is_stmt 0 view .LVU2249
+ 6195 014e 15F0300F 		tst	r5, #48
+ 6196 0152 1CD1     		bne	.L353
+1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6197              		.loc 1 1637 12 is_stmt 1 view .LVU2250
+1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6198              		.loc 1 1637 14 is_stmt 0 view .LVU2251
+ 6199 0154 15F0030F 		tst	r5, #3
+ 6200 0158 26D0     		beq	.L346
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Abort DMA in IT mode */
+ 6201              		.loc 1 1640 9 is_stmt 1 view .LVU2252
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Abort DMA in IT mode */
+ 6202              		.loc 1 1640 12 is_stmt 0 view .LVU2253
+ 6203 015a 236C     		ldr	r3, [r4, #64]
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Abort DMA in IT mode */
+ 6204              		.loc 1 1640 40 view .LVU2254
+ 6205 015c 184A     		ldr	r2, .L354+4
+ 6206 015e 1A65     		str	r2, [r3, #80]
+1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 6207              		.loc 1 1642 9 is_stmt 1 view .LVU2255
+1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 6208              		.loc 1 1642 12 is_stmt 0 view .LVU2256
+ 6209 0160 206C     		ldr	r0, [r4, #64]
+ 6210 0162 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 6211              	.LVL485:
+1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 6212              		.loc 1 1642 11 view .LVU2257
+ 6213 0166 0028     		cmp	r0, #0
+ 6214 0168 3FF47EAF 		beq	.L331
+1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 6215              		.loc 1 1644 11 is_stmt 1 view .LVU2258
+ 6216 016c 206C     		ldr	r0, [r4, #64]
+ 6217 016e FFF7FEFF 		bl	SD_DMARxAbort
+ 6218              	.LVL486:
+ 6219 0172 79E7     		b	.L331
+ 6220              	.LVL487:
+ 6221              	.L351:
+1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 6222              		.loc 1 1581 5 view .LVU2259
+ 6223 0174 2046     		mov	r0, r4
+ 6224              	.LVL488:
+1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 6225              		.loc 1 1581 5 is_stmt 0 view .LVU2260
+ 6226 0176 FFF7FEFF 		bl	SD_Write_IT
+ 6227              	.LVL489:
+ 6228 017a 75E7     		b	.L331
+ 6229              	.L352:
+1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 6230              		.loc 1 1616 7 is_stmt 1 view .LVU2261
+ARM GAS  /tmp/ccQEYyKb.s 			page 204
+
+
+1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       hsd->Context = SD_CONTEXT_NONE;
+ 6231              		.loc 1 1616 18 is_stmt 0 view .LVU2262
+ 6232 017c 0123     		movs	r3, #1
+ 6233 017e 84F83430 		strb	r3, [r4, #52]
+1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ 6234              		.loc 1 1617 7 is_stmt 1 view .LVU2263
+1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ 6235              		.loc 1 1617 20 is_stmt 0 view .LVU2264
+ 6236 0182 0023     		movs	r3, #0
+ 6237 0184 2363     		str	r3, [r4, #48]
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 6238              		.loc 1 1621 7 is_stmt 1 view .LVU2265
+ 6239 0186 2046     		mov	r0, r4
+ 6240 0188 FFF7FEFF 		bl	HAL_SD_ErrorCallback
+ 6241              	.LVL490:
+ 6242 018c 6CE7     		b	.L331
+ 6243              	.L353:
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Abort DMA in IT mode */
+ 6244              		.loc 1 1630 9 view .LVU2266
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Abort DMA in IT mode */
+ 6245              		.loc 1 1630 12 is_stmt 0 view .LVU2267
+ 6246 018e E36B     		ldr	r3, [r4, #60]
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         /* Abort DMA in IT mode */
+ 6247              		.loc 1 1630 40 view .LVU2268
+ 6248 0190 0C4A     		ldr	r2, .L354+8
+ 6249 0192 1A65     		str	r2, [r3, #80]
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 6250              		.loc 1 1632 9 is_stmt 1 view .LVU2269
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 6251              		.loc 1 1632 12 is_stmt 0 view .LVU2270
+ 6252 0194 E06B     		ldr	r0, [r4, #60]
+ 6253 0196 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 6254              	.LVL491:
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         {
+ 6255              		.loc 1 1632 11 view .LVU2271
+ 6256 019a 0028     		cmp	r0, #0
+ 6257 019c 3FF464AF 		beq	.L331
+1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         }
+ 6258              		.loc 1 1634 11 is_stmt 1 view .LVU2272
+ 6259 01a0 E06B     		ldr	r0, [r4, #60]
+ 6260 01a2 FFF7FEFF 		bl	SD_DMATxAbort
+ 6261              	.LVL492:
+ 6262 01a6 5FE7     		b	.L331
+ 6263              	.L346:
+1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 6264              		.loc 1 1649 9 view .LVU2273
+1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->State = HAL_SD_STATE_READY;
+ 6265              		.loc 1 1649 24 is_stmt 0 view .LVU2274
+ 6266 01a8 0023     		movs	r3, #0
+ 6267 01aa A363     		str	r3, [r4, #56]
+1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 6268              		.loc 1 1650 9 is_stmt 1 view .LVU2275
+1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****         hsd->Context = SD_CONTEXT_NONE;
+ 6269              		.loc 1 1650 20 is_stmt 0 view .LVU2276
+ 6270 01ac 0122     		movs	r2, #1
+ 6271 01ae 84F83420 		strb	r2, [r4, #52]
+1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ARM GAS  /tmp/ccQEYyKb.s 			page 205
+
+
+ 6272              		.loc 1 1651 9 is_stmt 1 view .LVU2277
+1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ 6273              		.loc 1 1651 22 is_stmt 0 view .LVU2278
+ 6274 01b2 2363     		str	r3, [r4, #48]
+1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 6275              		.loc 1 1655 9 is_stmt 1 view .LVU2279
+ 6276 01b4 2046     		mov	r0, r4
+ 6277 01b6 FFF7FEFF 		bl	HAL_SD_AbortCallback
+ 6278              	.LVL493:
+1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 6279              		.loc 1 1667 3 view .LVU2280
+1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6280              		.loc 1 1668 1 is_stmt 0 view .LVU2281
+ 6281 01ba 55E7     		b	.L331
+ 6282              	.L355:
+ 6283              		.align	2
+ 6284              	.L354:
+ 6285 01bc C53EFFFF 		.word	-49467
+ 6286 01c0 00000000 		.word	SD_DMARxAbort
+ 6287 01c4 00000000 		.word	SD_DMATxAbort
+ 6288              		.cfi_endproc
+ 6289              	.LFE153:
+ 6291              		.section	.text.HAL_SD_Abort,"ax",%progbits
+ 6292              		.align	1
+ 6293              		.global	HAL_SD_Abort
+ 6294              		.syntax unified
+ 6295              		.thumb
+ 6296              		.thumb_func
+ 6297              		.fpu fpv5-d16
+ 6299              	HAL_SD_Abort:
+ 6300              	.LVL494:
+ 6301              	.LFB166:
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+ 6302              		.loc 1 2290 1 is_stmt 1 view -0
+ 6303              		.cfi_startproc
+ 6304              		@ args = 0, pretend = 0, frame = 0
+ 6305              		@ frame_needed = 0, uses_anonymous_args = 0
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+ 6306              		.loc 1 2290 1 is_stmt 0 view .LVU2283
+ 6307 0000 10B5     		push	{r4, lr}
+ 6308              	.LCFI77:
+ 6309              		.cfi_def_cfa_offset 8
+ 6310              		.cfi_offset 4, -8
+ 6311              		.cfi_offset 14, -4
+ 6312 0002 0446     		mov	r4, r0
+2291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t context = hsd->Context;
+ 6313              		.loc 1 2291 3 is_stmt 1 view .LVU2284
+2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6314              		.loc 1 2292 3 view .LVU2285
+2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6315              		.loc 1 2292 12 is_stmt 0 view .LVU2286
+ 6316 0004 016B     		ldr	r1, [r0, #48]
+ 6317              	.LVL495:
+2295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ 6318              		.loc 1 2295 3 is_stmt 1 view .LVU2287
+ 6319 0006 0268     		ldr	r2, [r0]
+ 6320 0008 D36B     		ldr	r3, [r2, #60]
+ARM GAS  /tmp/ccQEYyKb.s 			page 206
+
+
+ 6321 000a 23F49D73 		bic	r3, r3, #314
+ 6322 000e D363     		str	r3, [r2, #60]
+2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6323              		.loc 1 2299 3 view .LVU2288
+ 6324 0010 0368     		ldr	r3, [r0]
+ 6325 0012 40F23A52 		movw	r2, #1338
+ 6326 0016 9A63     		str	r2, [r3, #56]
+2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6327              		.loc 1 2301 3 view .LVU2289
+ 6328 0018 0268     		ldr	r2, [r0]
+ 6329 001a D36A     		ldr	r3, [r2, #44]
+ 6330 001c 23F00103 		bic	r3, r3, #1
+ 6331 0020 D362     		str	r3, [r2, #44]
+2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6332              		.loc 1 2303 3 view .LVU2290
+2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6333              		.loc 1 2303 6 is_stmt 0 view .LVU2291
+ 6334 0022 11F0800F 		tst	r1, #128
+ 6335 0026 0AD0     		beq	.L357
+2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6336              		.loc 1 2306 5 is_stmt 1 view .LVU2292
+2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6337              		.loc 1 2306 8 is_stmt 0 view .LVU2293
+ 6338 0028 0268     		ldr	r2, [r0]
+2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6339              		.loc 1 2306 26 view .LVU2294
+ 6340 002a D36A     		ldr	r3, [r2, #44]
+ 6341 002c 23F00803 		bic	r3, r3, #8
+ 6342 0030 D362     		str	r3, [r2, #44]
+2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6343              		.loc 1 2309 5 is_stmt 1 view .LVU2295
+2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6344              		.loc 1 2309 8 is_stmt 0 view .LVU2296
+ 6345 0032 11F0300F 		tst	r1, #48
+ 6346 0036 11D1     		bne	.L363
+2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6347              		.loc 1 2317 10 is_stmt 1 view .LVU2297
+2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6348              		.loc 1 2317 13 is_stmt 0 view .LVU2298
+ 6349 0038 11F0030F 		tst	r1, #3
+ 6350 003c 18D1     		bne	.L364
+ 6351              	.LVL496:
+ 6352              	.L357:
+2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 6353              		.loc 1 2327 5 is_stmt 1 view .LVU2299
+2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6354              		.loc 1 2330 3 view .LVU2300
+2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6355              		.loc 1 2330 14 is_stmt 0 view .LVU2301
+ 6356 003e 0123     		movs	r3, #1
+ 6357 0040 84F83430 		strb	r3, [r4, #52]
+2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6358              		.loc 1 2333 3 is_stmt 1 view .LVU2302
+2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6359              		.loc 1 2333 16 is_stmt 0 view .LVU2303
+ 6360 0044 0023     		movs	r3, #0
+ 6361 0046 2363     		str	r3, [r4, #48]
+ARM GAS  /tmp/ccQEYyKb.s 			page 207
+
+
+2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ 6362              		.loc 1 2335 3 is_stmt 1 view .LVU2304
+2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ 6363              		.loc 1 2335 15 is_stmt 0 view .LVU2305
+ 6364 0048 2046     		mov	r0, r4
+ 6365 004a FFF7FEFF 		bl	HAL_SD_GetCardState
+ 6366              	.LVL497:
+2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6367              		.loc 1 2336 3 is_stmt 1 view .LVU2306
+2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6368              		.loc 1 2336 43 is_stmt 0 view .LVU2307
+ 6369 004e 0538     		subs	r0, r0, #5
+ 6370              	.LVL498:
+2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6371              		.loc 1 2336 5 view .LVU2308
+ 6372 0050 0128     		cmp	r0, #1
+ 6373 0052 17D9     		bls	.L365
+ 6374              	.LVL499:
+ 6375              	.L359:
+2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6376              		.loc 1 2340 3 is_stmt 1 view .LVU2309
+2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6377              		.loc 1 2340 9 is_stmt 0 view .LVU2310
+ 6378 0054 A36B     		ldr	r3, [r4, #56]
+2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6379              		.loc 1 2340 5 view .LVU2311
+ 6380 0056 D3B9     		cbnz	r3, .L361
+2344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 6381              		.loc 1 2344 10 view .LVU2312
+ 6382 0058 0020     		movs	r0, #0
+ 6383              	.L360:
+2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6384              		.loc 1 2345 1 view .LVU2313
+ 6385 005a 10BD     		pop	{r4, pc}
+ 6386              	.LVL500:
+ 6387              	.L363:
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6388              		.loc 1 2311 7 is_stmt 1 view .LVU2314
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6389              		.loc 1 2311 10 is_stmt 0 view .LVU2315
+ 6390 005c C06B     		ldr	r0, [r0, #60]
+ 6391              	.LVL501:
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6392              		.loc 1 2311 10 view .LVU2316
+ 6393 005e FFF7FEFF 		bl	HAL_DMA_Abort
+ 6394              	.LVL502:
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6395              		.loc 1 2311 9 view .LVU2317
+ 6396 0062 0028     		cmp	r0, #0
+ 6397 0064 EBD0     		beq	.L357
+2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 6398              		.loc 1 2313 9 is_stmt 1 view .LVU2318
+2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 6399              		.loc 1 2313 24 is_stmt 0 view .LVU2319
+ 6400 0066 A36B     		ldr	r3, [r4, #56]
+ 6401 0068 43F08043 		orr	r3, r3, #1073741824
+ 6402 006c A363     		str	r3, [r4, #56]
+ARM GAS  /tmp/ccQEYyKb.s 			page 208
+
+
+ 6403 006e E6E7     		b	.L357
+ 6404              	.LVL503:
+ 6405              	.L364:
+2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6406              		.loc 1 2319 7 is_stmt 1 view .LVU2320
+2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6407              		.loc 1 2319 10 is_stmt 0 view .LVU2321
+ 6408 0070 006C     		ldr	r0, [r0, #64]
+ 6409              	.LVL504:
+2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6410              		.loc 1 2319 10 view .LVU2322
+ 6411 0072 FFF7FEFF 		bl	HAL_DMA_Abort
+ 6412              	.LVL505:
+2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6413              		.loc 1 2319 9 view .LVU2323
+ 6414 0076 0028     		cmp	r0, #0
+ 6415 0078 E1D0     		beq	.L357
+2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 6416              		.loc 1 2321 9 is_stmt 1 view .LVU2324
+2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 6417              		.loc 1 2321 24 is_stmt 0 view .LVU2325
+ 6418 007a A36B     		ldr	r3, [r4, #56]
+ 6419 007c 43F08043 		orr	r3, r3, #1073741824
+ 6420 0080 A363     		str	r3, [r4, #56]
+ 6421 0082 DCE7     		b	.L357
+ 6422              	.LVL506:
+ 6423              	.L365:
+2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 6424              		.loc 1 2338 5 is_stmt 1 view .LVU2326
+2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 6425              		.loc 1 2338 22 is_stmt 0 view .LVU2327
+ 6426 0084 2068     		ldr	r0, [r4]
+ 6427              	.LVL507:
+2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 6428              		.loc 1 2338 22 view .LVU2328
+ 6429 0086 FFF7FEFF 		bl	SDMMC_CmdStopTransfer
+ 6430              	.LVL508:
+2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 6431              		.loc 1 2338 20 view .LVU2329
+ 6432 008a A063     		str	r0, [r4, #56]
+ 6433 008c E2E7     		b	.L359
+ 6434              	.L361:
+2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   }
+ 6435              		.loc 1 2342 12 view .LVU2330
+ 6436 008e 0120     		movs	r0, #1
+ 6437 0090 E3E7     		b	.L360
+ 6438              		.cfi_endproc
+ 6439              	.LFE166:
+ 6441              		.section	.text.HAL_SD_Abort_IT,"ax",%progbits
+ 6442              		.align	1
+ 6443              		.global	HAL_SD_Abort_IT
+ 6444              		.syntax unified
+ 6445              		.thumb
+ 6446              		.thumb_func
+ 6447              		.fpu fpv5-d16
+ 6449              	HAL_SD_Abort_IT:
+ 6450              	.LVL509:
+ARM GAS  /tmp/ccQEYyKb.s 			page 209
+
+
+ 6451              	.LFB167:
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+ 6452              		.loc 1 2354 1 is_stmt 1 view -0
+ 6453              		.cfi_startproc
+ 6454              		@ args = 0, pretend = 0, frame = 0
+ 6455              		@ frame_needed = 0, uses_anonymous_args = 0
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   HAL_SD_CardStateTypeDef CardState;
+ 6456              		.loc 1 2354 1 is_stmt 0 view .LVU2332
+ 6457 0000 10B5     		push	{r4, lr}
+ 6458              	.LCFI78:
+ 6459              		.cfi_def_cfa_offset 8
+ 6460              		.cfi_offset 4, -8
+ 6461              		.cfi_offset 14, -4
+ 6462 0002 0446     		mov	r4, r0
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   uint32_t context = hsd->Context;
+ 6463              		.loc 1 2355 3 is_stmt 1 view .LVU2333
+2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6464              		.loc 1 2356 3 view .LVU2334
+2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6465              		.loc 1 2356 12 is_stmt 0 view .LVU2335
+ 6466 0004 026B     		ldr	r2, [r0, #48]
+ 6467              	.LVL510:
+2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****                            SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ 6468              		.loc 1 2359 3 is_stmt 1 view .LVU2336
+ 6469 0006 0168     		ldr	r1, [r0]
+ 6470 0008 CB6B     		ldr	r3, [r1, #60]
+ 6471 000a 23F49D73 		bic	r3, r3, #314
+ 6472 000e CB63     		str	r3, [r1, #60]
+2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6473              		.loc 1 2362 3 view .LVU2337
+ 6474 0010 0168     		ldr	r1, [r0]
+ 6475 0012 CB6A     		ldr	r3, [r1, #44]
+ 6476 0014 23F00103 		bic	r3, r3, #1
+ 6477 0018 CB62     		str	r3, [r1, #44]
+2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6478              		.loc 1 2364 3 view .LVU2338
+2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****   {
+ 6479              		.loc 1 2364 6 is_stmt 0 view .LVU2339
+ 6480 001a 12F0800F 		tst	r2, #128
+ 6481 001e 22D0     		beq	.L367
+2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6482              		.loc 1 2367 5 is_stmt 1 view .LVU2340
+2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6483              		.loc 1 2367 8 is_stmt 0 view .LVU2341
+ 6484 0020 0168     		ldr	r1, [r0]
+2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6485              		.loc 1 2367 26 view .LVU2342
+ 6486 0022 CB6A     		ldr	r3, [r1, #44]
+ 6487 0024 23F00803 		bic	r3, r3, #8
+ 6488 0028 CB62     		str	r3, [r1, #44]
+2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6489              		.loc 1 2370 5 is_stmt 1 view .LVU2343
+2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6490              		.loc 1 2370 8 is_stmt 0 view .LVU2344
+ 6491 002a 12F0300F 		tst	r2, #48
+ 6492 002e 04D1     		bne	.L374
+2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ARM GAS  /tmp/ccQEYyKb.s 			page 210
+
+
+ 6493              		.loc 1 2379 10 is_stmt 1 view .LVU2345
+2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6494              		.loc 1 2379 13 is_stmt 0 view .LVU2346
+ 6495 0030 12F0030F 		tst	r2, #3
+ 6496 0034 0CD1     		bne	.L375
+2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 6497              		.loc 1 2419 10 view .LVU2347
+ 6498 0036 0020     		movs	r0, #0
+ 6499              	.LVL511:
+ 6500              	.L369:
+2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6501              		.loc 1 2420 1 view .LVU2348
+ 6502 0038 10BD     		pop	{r4, pc}
+ 6503              	.LVL512:
+ 6504              	.L374:
+2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+ 6505              		.loc 1 2372 7 is_stmt 1 view .LVU2349
+2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+ 6506              		.loc 1 2372 10 is_stmt 0 view .LVU2350
+ 6507 003a C36B     		ldr	r3, [r0, #60]
+2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+ 6508              		.loc 1 2372 38 view .LVU2351
+ 6509 003c 184A     		ldr	r2, .L378
+ 6510              	.LVL513:
+2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+ 6511              		.loc 1 2372 38 view .LVU2352
+ 6512 003e 1A65     		str	r2, [r3, #80]
+2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6513              		.loc 1 2373 7 is_stmt 1 view .LVU2353
+2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6514              		.loc 1 2373 10 is_stmt 0 view .LVU2354
+ 6515 0040 C06B     		ldr	r0, [r0, #60]
+ 6516              	.LVL514:
+2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6517              		.loc 1 2373 10 view .LVU2355
+ 6518 0042 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 6519              	.LVL515:
+2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6520              		.loc 1 2373 9 view .LVU2356
+ 6521 0046 0028     		cmp	r0, #0
+ 6522 0048 F6D0     		beq	.L369
+2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 6523              		.loc 1 2375 9 is_stmt 1 view .LVU2357
+2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 6524              		.loc 1 2375 21 is_stmt 0 view .LVU2358
+ 6525 004a 0020     		movs	r0, #0
+ 6526 004c E063     		str	r0, [r4, #60]
+ 6527 004e F3E7     		b	.L369
+ 6528              	.LVL516:
+ 6529              	.L375:
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+ 6530              		.loc 1 2381 7 is_stmt 1 view .LVU2359
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+ 6531              		.loc 1 2381 10 is_stmt 0 view .LVU2360
+ 6532 0050 036C     		ldr	r3, [r0, #64]
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+ 6533              		.loc 1 2381 38 view .LVU2361
+ARM GAS  /tmp/ccQEYyKb.s 			page 211
+
+
+ 6534 0052 144A     		ldr	r2, .L378+4
+ 6535              	.LVL517:
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+ 6536              		.loc 1 2381 38 view .LVU2362
+ 6537 0054 1A65     		str	r2, [r3, #80]
+2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6538              		.loc 1 2382 7 is_stmt 1 view .LVU2363
+2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6539              		.loc 1 2382 10 is_stmt 0 view .LVU2364
+ 6540 0056 006C     		ldr	r0, [r0, #64]
+ 6541              	.LVL518:
+2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6542              		.loc 1 2382 10 view .LVU2365
+ 6543 0058 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 6544              	.LVL519:
+2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       {
+ 6545              		.loc 1 2382 9 view .LVU2366
+ 6546 005c 0028     		cmp	r0, #0
+ 6547 005e EBD0     		beq	.L369
+2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 6548              		.loc 1 2384 9 is_stmt 1 view .LVU2367
+2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****       }
+ 6549              		.loc 1 2384 21 is_stmt 0 view .LVU2368
+ 6550 0060 0020     		movs	r0, #0
+ 6551 0062 2064     		str	r0, [r4, #64]
+ 6552 0064 E8E7     		b	.L369
+ 6553              	.LVL520:
+ 6554              	.L367:
+2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6555              		.loc 1 2396 5 is_stmt 1 view .LVU2369
+ 6556 0066 0368     		ldr	r3, [r0]
+ 6557 0068 40F23A52 		movw	r2, #1338
+ 6558              	.LVL521:
+2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** 
+ 6559              		.loc 1 2396 5 is_stmt 0 view .LVU2370
+ 6560 006c 9A63     		str	r2, [r3, #56]
+2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 6561              		.loc 1 2398 5 is_stmt 1 view .LVU2371
+2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->State = HAL_SD_STATE_READY;
+ 6562              		.loc 1 2398 17 is_stmt 0 view .LVU2372
+ 6563 006e FFF7FEFF 		bl	HAL_SD_GetCardState
+ 6564              	.LVL522:
+2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Context = SD_CONTEXT_NONE;
+ 6565              		.loc 1 2399 5 is_stmt 1 view .LVU2373
+2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     hsd->Context = SD_CONTEXT_NONE;
+ 6566              		.loc 1 2399 16 is_stmt 0 view .LVU2374
+ 6567 0072 0123     		movs	r3, #1
+ 6568 0074 84F83430 		strb	r3, [r4, #52]
+2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ 6569              		.loc 1 2400 5 is_stmt 1 view .LVU2375
+2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ 6570              		.loc 1 2400 18 is_stmt 0 view .LVU2376
+ 6571 0078 0023     		movs	r3, #0
+ 6572 007a 2363     		str	r3, [r4, #48]
+2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6573              		.loc 1 2401 5 is_stmt 1 view .LVU2377
+2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ARM GAS  /tmp/ccQEYyKb.s 			page 212
+
+
+ 6574              		.loc 1 2401 45 is_stmt 0 view .LVU2378
+ 6575 007c 0538     		subs	r0, r0, #5
+ 6576              	.LVL523:
+2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6577              		.loc 1 2401 7 view .LVU2379
+ 6578 007e 0128     		cmp	r0, #1
+ 6579 0080 03D9     		bls	.L376
+ 6580              	.LVL524:
+ 6581              	.L370:
+2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6582              		.loc 1 2405 5 is_stmt 1 view .LVU2380
+2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6583              		.loc 1 2405 11 is_stmt 0 view .LVU2381
+ 6584 0082 A36B     		ldr	r3, [r4, #56]
+2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     {
+ 6585              		.loc 1 2405 7 view .LVU2382
+ 6586 0084 33B1     		cbz	r3, .L377
+2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6587              		.loc 1 2407 14 view .LVU2383
+ 6588 0086 0120     		movs	r0, #1
+ 6589 0088 D6E7     		b	.L369
+ 6590              	.LVL525:
+ 6591              	.L376:
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6592              		.loc 1 2403 7 is_stmt 1 view .LVU2384
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6593              		.loc 1 2403 24 is_stmt 0 view .LVU2385
+ 6594 008a 2068     		ldr	r0, [r4]
+ 6595              	.LVL526:
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6596              		.loc 1 2403 24 view .LVU2386
+ 6597 008c FFF7FEFF 		bl	SDMMC_CmdStopTransfer
+ 6598              	.LVL527:
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c ****     }
+ 6599              		.loc 1 2403 22 view .LVU2387
+ 6600 0090 A063     		str	r0, [r4, #56]
+ 6601 0092 F6E7     		b	.L370
+ 6602              	.L377:
+2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 6603              		.loc 1 2414 7 is_stmt 1 view .LVU2388
+ 6604 0094 2046     		mov	r0, r4
+ 6605 0096 FFF7FEFF 		bl	HAL_SD_AbortCallback
+ 6606              	.LVL528:
+2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** }
+ 6607              		.loc 1 2419 10 is_stmt 0 view .LVU2389
+ 6608 009a 0020     		movs	r0, #0
+ 6609 009c CCE7     		b	.L369
+ 6610              	.L379:
+ 6611 009e 00BF     		.align	2
+ 6612              	.L378:
+ 6613 00a0 00000000 		.word	SD_DMATxAbort
+ 6614 00a4 00000000 		.word	SD_DMARxAbort
+ 6615              		.cfi_endproc
+ 6616              	.LFE167:
+ 6618              		.text
+ 6619              	.Letext0:
+ 6620              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ARM GAS  /tmp/ccQEYyKb.s 			page 213
+
+
+ 6621              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 6622              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 6623              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 6624              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 6625              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h"
+ 6626              		.file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h"
+ 6627              		.file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ARM GAS  /tmp/ccQEYyKb.s 			page 214
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_sd.c
+     /tmp/ccQEYyKb.s:17     .text.SD_DMATransmitCplt:0000000000000000 $t
+     /tmp/ccQEYyKb.s:24     .text.SD_DMATransmitCplt:0000000000000000 SD_DMATransmitCplt
+     /tmp/ccQEYyKb.s:51     .text.SD_PowerON:0000000000000000 $t
+     /tmp/ccQEYyKb.s:57     .text.SD_PowerON:0000000000000000 SD_PowerON
+     /tmp/ccQEYyKb.s:275    .text.SD_PowerON:00000000000000bc $d
+     /tmp/ccQEYyKb.s:280    .text.SD_PowerOFF:0000000000000000 $t
+     /tmp/ccQEYyKb.s:286    .text.SD_PowerOFF:0000000000000000 SD_PowerOFF
+     /tmp/ccQEYyKb.s:312    .text.SD_Read_IT:0000000000000000 $t
+     /tmp/ccQEYyKb.s:318    .text.SD_Read_IT:0000000000000000 SD_Read_IT
+     /tmp/ccQEYyKb.s:423    .text.SD_Write_IT:0000000000000000 $t
+     /tmp/ccQEYyKb.s:429    .text.SD_Write_IT:0000000000000000 SD_Write_IT
+     /tmp/ccQEYyKb.s:548    .text.SD_SendSDStatus:0000000000000000 $t
+     /tmp/ccQEYyKb.s:554    .text.SD_SendSDStatus:0000000000000000 SD_SendSDStatus
+     /tmp/ccQEYyKb.s:823    .text.SD_FindSCR:0000000000000000 $t
+     /tmp/ccQEYyKb.s:829    .text.SD_FindSCR:0000000000000000 SD_FindSCR
+     /tmp/ccQEYyKb.s:1093   .text.SD_WideBus_Enable:0000000000000000 $t
+     /tmp/ccQEYyKb.s:1099   .text.SD_WideBus_Enable:0000000000000000 SD_WideBus_Enable
+     /tmp/ccQEYyKb.s:1194   .text.SD_WideBus_Disable:0000000000000000 $t
+     /tmp/ccQEYyKb.s:1200   .text.SD_WideBus_Disable:0000000000000000 SD_WideBus_Disable
+     /tmp/ccQEYyKb.s:1295   .text.SD_SendStatus:0000000000000000 $t
+     /tmp/ccQEYyKb.s:1301   .text.SD_SendStatus:0000000000000000 SD_SendStatus
+     /tmp/ccQEYyKb.s:1366   .text.HAL_SD_MspInit:0000000000000000 $t
+     /tmp/ccQEYyKb.s:1373   .text.HAL_SD_MspInit:0000000000000000 HAL_SD_MspInit
+     /tmp/ccQEYyKb.s:1388   .text.HAL_SD_MspDeInit:0000000000000000 $t
+     /tmp/ccQEYyKb.s:1395   .text.HAL_SD_MspDeInit:0000000000000000 HAL_SD_MspDeInit
+     /tmp/ccQEYyKb.s:1410   .text.HAL_SD_DeInit:0000000000000000 $t
+     /tmp/ccQEYyKb.s:1417   .text.HAL_SD_DeInit:0000000000000000 HAL_SD_DeInit
+     /tmp/ccQEYyKb.s:1471   .text.HAL_SD_ReadBlocks:0000000000000000 $t
+     /tmp/ccQEYyKb.s:1478   .text.HAL_SD_ReadBlocks:0000000000000000 HAL_SD_ReadBlocks
+     /tmp/ccQEYyKb.s:2028   .text.HAL_SD_ReadBlocks:0000000000000244 $d
+     /tmp/ccQEYyKb.s:2033   .text.HAL_SD_WriteBlocks:0000000000000000 $t
+     /tmp/ccQEYyKb.s:2040   .text.HAL_SD_WriteBlocks:0000000000000000 HAL_SD_WriteBlocks
+     /tmp/ccQEYyKb.s:2520   .text.HAL_SD_WriteBlocks:00000000000001fc $d
+     /tmp/ccQEYyKb.s:2525   .text.HAL_SD_ReadBlocks_IT:0000000000000000 $t
+     /tmp/ccQEYyKb.s:2532   .text.HAL_SD_ReadBlocks_IT:0000000000000000 HAL_SD_ReadBlocks_IT
+     /tmp/ccQEYyKb.s:2755   .text.HAL_SD_ReadBlocks_IT:00000000000000c8 $d
+     /tmp/ccQEYyKb.s:2760   .text.HAL_SD_WriteBlocks_IT:0000000000000000 $t
+     /tmp/ccQEYyKb.s:2767   .text.HAL_SD_WriteBlocks_IT:0000000000000000 HAL_SD_WriteBlocks_IT
+     /tmp/ccQEYyKb.s:2991   .text.HAL_SD_WriteBlocks_IT:00000000000000c0 $d
+     /tmp/ccQEYyKb.s:2996   .text.HAL_SD_ReadBlocks_DMA:0000000000000000 $t
+     /tmp/ccQEYyKb.s:3003   .text.HAL_SD_ReadBlocks_DMA:0000000000000000 HAL_SD_ReadBlocks_DMA
+     /tmp/ccQEYyKb.s:3288   .text.HAL_SD_ReadBlocks_DMA:0000000000000128 $d
+     /tmp/ccQEYyKb.s:3978   .text.SD_DMAReceiveCplt:0000000000000000 SD_DMAReceiveCplt
+     /tmp/ccQEYyKb.s:5614   .text.SD_DMAError:0000000000000000 SD_DMAError
+     /tmp/ccQEYyKb.s:3295   .text.HAL_SD_WriteBlocks_DMA:0000000000000000 $t
+     /tmp/ccQEYyKb.s:3302   .text.HAL_SD_WriteBlocks_DMA:0000000000000000 HAL_SD_WriteBlocks_DMA
+     /tmp/ccQEYyKb.s:3592   .text.HAL_SD_WriteBlocks_DMA:0000000000000124 $d
+     /tmp/ccQEYyKb.s:3599   .text.HAL_SD_Erase:0000000000000000 $t
+     /tmp/ccQEYyKb.s:3606   .text.HAL_SD_Erase:0000000000000000 HAL_SD_Erase
+     /tmp/ccQEYyKb.s:3851   .text.HAL_SD_Erase:00000000000000f4 $d
+     /tmp/ccQEYyKb.s:3856   .text.HAL_SD_GetState:0000000000000000 $t
+     /tmp/ccQEYyKb.s:3863   .text.HAL_SD_GetState:0000000000000000 HAL_SD_GetState
+     /tmp/ccQEYyKb.s:3881   .text.HAL_SD_GetError:0000000000000000 $t
+     /tmp/ccQEYyKb.s:3888   .text.HAL_SD_GetError:0000000000000000 HAL_SD_GetError
+     /tmp/ccQEYyKb.s:3906   .text.HAL_SD_TxCpltCallback:0000000000000000 $t
+ARM GAS  /tmp/ccQEYyKb.s 			page 215
+
+
+     /tmp/ccQEYyKb.s:3913   .text.HAL_SD_TxCpltCallback:0000000000000000 HAL_SD_TxCpltCallback
+     /tmp/ccQEYyKb.s:3928   .text.HAL_SD_RxCpltCallback:0000000000000000 $t
+     /tmp/ccQEYyKb.s:3935   .text.HAL_SD_RxCpltCallback:0000000000000000 HAL_SD_RxCpltCallback
+     /tmp/ccQEYyKb.s:3950   .text.HAL_SD_ErrorCallback:0000000000000000 $t
+     /tmp/ccQEYyKb.s:3957   .text.HAL_SD_ErrorCallback:0000000000000000 HAL_SD_ErrorCallback
+     /tmp/ccQEYyKb.s:3972   .text.SD_DMAReceiveCplt:0000000000000000 $t
+     /tmp/ccQEYyKb.s:4059   .text.HAL_SD_AbortCallback:0000000000000000 $t
+     /tmp/ccQEYyKb.s:4066   .text.HAL_SD_AbortCallback:0000000000000000 HAL_SD_AbortCallback
+     /tmp/ccQEYyKb.s:4081   .text.HAL_SD_GetCardCID:0000000000000000 $t
+     /tmp/ccQEYyKb.s:4088   .text.HAL_SD_GetCardCID:0000000000000000 HAL_SD_GetCardCID
+     /tmp/ccQEYyKb.s:4173   .text.HAL_SD_GetCardCSD:0000000000000000 $t
+     /tmp/ccQEYyKb.s:4180   .text.HAL_SD_GetCardCSD:0000000000000000 HAL_SD_GetCardCSD
+     /tmp/ccQEYyKb.s:4549   .text.HAL_SD_GetCardCSD:00000000000001b4 $d
+     /tmp/ccQEYyKb.s:4554   .text.SD_InitCard:0000000000000000 $t
+     /tmp/ccQEYyKb.s:4560   .text.SD_InitCard:0000000000000000 SD_InitCard
+     /tmp/ccQEYyKb.s:4801   .text.HAL_SD_InitCard:0000000000000000 $t
+     /tmp/ccQEYyKb.s:4808   .text.HAL_SD_InitCard:0000000000000000 HAL_SD_InitCard
+     /tmp/ccQEYyKb.s:4978   .text.HAL_SD_InitCard:00000000000000a4 $d
+     /tmp/ccQEYyKb.s:4983   .text.HAL_SD_Init:0000000000000000 $t
+     /tmp/ccQEYyKb.s:4990   .text.HAL_SD_Init:0000000000000000 HAL_SD_Init
+     /tmp/ccQEYyKb.s:5080   .text.HAL_SD_GetCardStatus:0000000000000000 $t
+     /tmp/ccQEYyKb.s:5087   .text.HAL_SD_GetCardStatus:0000000000000000 HAL_SD_GetCardStatus
+     /tmp/ccQEYyKb.s:5265   .text.HAL_SD_GetCardStatus:00000000000000a8 $d
+     /tmp/ccQEYyKb.s:5270   .text.HAL_SD_GetCardInfo:0000000000000000 $t
+     /tmp/ccQEYyKb.s:5277   .text.HAL_SD_GetCardInfo:0000000000000000 HAL_SD_GetCardInfo
+     /tmp/ccQEYyKb.s:5335   .text.HAL_SD_ConfigWideBusOperation:0000000000000000 $t
+     /tmp/ccQEYyKb.s:5342   .text.HAL_SD_ConfigWideBusOperation:0000000000000000 HAL_SD_ConfigWideBusOperation
+     /tmp/ccQEYyKb.s:5539   .text.HAL_SD_ConfigWideBusOperation:00000000000000bc $d
+     /tmp/ccQEYyKb.s:5544   .text.HAL_SD_GetCardState:0000000000000000 $t
+     /tmp/ccQEYyKb.s:5551   .text.HAL_SD_GetCardState:0000000000000000 HAL_SD_GetCardState
+     /tmp/ccQEYyKb.s:5608   .text.SD_DMAError:0000000000000000 $t
+     /tmp/ccQEYyKb.s:5727   .text.SD_DMAError:0000000000000064 $d
+     /tmp/ccQEYyKb.s:5732   .text.SD_DMATxAbort:0000000000000000 $t
+     /tmp/ccQEYyKb.s:5738   .text.SD_DMATxAbort:0000000000000000 SD_DMATxAbort
+     /tmp/ccQEYyKb.s:5821   .text.SD_DMARxAbort:0000000000000000 $t
+     /tmp/ccQEYyKb.s:5827   .text.SD_DMARxAbort:0000000000000000 SD_DMARxAbort
+     /tmp/ccQEYyKb.s:5910   .text.HAL_SD_IRQHandler:0000000000000000 $t
+     /tmp/ccQEYyKb.s:5917   .text.HAL_SD_IRQHandler:0000000000000000 HAL_SD_IRQHandler
+     /tmp/ccQEYyKb.s:6285   .text.HAL_SD_IRQHandler:00000000000001bc $d
+     /tmp/ccQEYyKb.s:6292   .text.HAL_SD_Abort:0000000000000000 $t
+     /tmp/ccQEYyKb.s:6299   .text.HAL_SD_Abort:0000000000000000 HAL_SD_Abort
+     /tmp/ccQEYyKb.s:6442   .text.HAL_SD_Abort_IT:0000000000000000 $t
+     /tmp/ccQEYyKb.s:6449   .text.HAL_SD_Abort_IT:0000000000000000 HAL_SD_Abort_IT
+     /tmp/ccQEYyKb.s:6613   .text.HAL_SD_Abort_IT:00000000000000a0 $d
+
+UNDEFINED SYMBOLS
+SDMMC_CmdGoIdleState
+SDMMC_CmdOperCond
+SDMMC_CmdAppCommand
+SDMMC_CmdAppOperCommand
+SDMMC_GetResponse
+SDMMC_PowerState_OFF
+SDMMC_ReadFIFO
+SDMMC_WriteFIFO
+HAL_GetTick
+SDMMC_CmdBlockLength
+SDMMC_ConfigData
+ARM GAS  /tmp/ccQEYyKb.s 			page 216
+
+
+SDMMC_CmdStatusRegister
+SDMMC_CmdSendSCR
+SDMMC_CmdBusWidth
+SDMMC_CmdSendStatus
+SDMMC_CmdReadMultiBlock
+SDMMC_CmdReadSingleBlock
+SDMMC_CmdStopTransfer
+SDMMC_CmdWriteMultiBlock
+SDMMC_CmdWriteSingleBlock
+HAL_DMA_Start_IT
+SDMMC_CmdSDEraseStartAdd
+SDMMC_CmdSDEraseEndAdd
+SDMMC_CmdErase
+SDMMC_GetPowerState
+SDMMC_CmdSendCSD
+SDMMC_CmdSelDesel
+SDMMC_Init
+SDMMC_CmdSendCID
+SDMMC_CmdSetRelAdd
+SDMMC_PowerState_ON
+HAL_Delay
+HAL_DMA_GetError
+HAL_DMA_Abort_IT
+HAL_DMA_Abort
diff --git a/build/stm32f7xx_hal_sd.o b/build/stm32f7xx_hal_sd.o
new file mode 100644
index 0000000..1b2c461
Binary files /dev/null and b/build/stm32f7xx_hal_sd.o differ
diff --git a/build/stm32f7xx_hal_tim.d b/build/stm32f7xx_hal_tim.d
new file mode 100644
index 0000000..45e46e6
--- /dev/null
+++ b/build/stm32f7xx_hal_tim.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_tim.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_tim.lst b/build/stm32f7xx_hal_tim.lst
new file mode 100644
index 0000000..7a80865
--- /dev/null
+++ b/build/stm32f7xx_hal_tim.lst
@@ -0,0 +1,29906 @@
+ARM GAS  /tmp/ccPLZXyC.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_tim.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.TIM_OC1_SetConfig,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	TIM_OC1_SetConfig:
+  25              	.LVL0:
+  26              	.LFB246:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @file    stm32f7xx_hal_tim.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief   TIM HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          functionalities of the Timer (TIM) peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Time Base Initialization
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Time Base Start
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Time Base Start Interruption
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Time Base Start DMA
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Output Compare/PWM Initialization
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Output Compare/PWM Channel Configuration
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Output Compare/PWM  Start
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Output Compare/PWM  Start Interruption
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Output Compare/PWM Start DMA
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Input Capture Initialization
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Input Capture Channel Configuration
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Input Capture Start
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Input Capture Start Interruption
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Input Capture Start DMA
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM One Pulse Initialization
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM One Pulse Channel Configuration
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM One Pulse Start
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Encoder Interface Initialization
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Encoder Interface Start
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Encoder Interface Start Interruption
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM Encoder Interface Start DMA
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + Commutation Event configuration with Interruption and DMA
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM OCRef clear configuration
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *           + TIM External Clock configuration
+ARM GAS  /tmp/ccPLZXyC.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ******************************************************************************
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @attention
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * Copyright (c) 2017 STMicroelectronics.
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * All rights reserved.
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * in the root directory of this software component.
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ******************************************************************************
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   @verbatim
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       ##### TIMER Generic features #####
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..] The Timer features include:
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        (#) 16-bit up, down, up/down auto-reload counter.
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            counter clock frequency either by any factor between 1 and 65536.
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        (#) Up to 4 independent channels for:
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) Input Capture
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) Output Compare
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) PWM generation (Edge and Center-aligned Mode)
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) One-pulse mode output
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        (#) Synchronization circuit to control the timer with external signals and to interconnect
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             several timers together.
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        (#) Supports incremental encoder for positioning purposes
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             ##### How to use this driver #####
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     [..]
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****      (#) Initialize the TIM low level resources by implementing the following functions
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****          depending on the selected feature:
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) Time Base : HAL_TIM_Base_MspInit()
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) Input Capture : HAL_TIM_IC_MspInit()
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) Output Compare : HAL_TIM_OC_MspInit()
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) PWM generation : HAL_TIM_PWM_MspInit()
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****      (#) Initialize the TIM low level resources :
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         (##) TIM pins configuration
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             (+++) Enable the clock for the TIM GPIOs using the following function:
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              __HAL_RCC_GPIOx_CLK_ENABLE();
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****      (#) The external Clock can be configured, if needed (the default clock is the
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****          internal clock from the APBx), using the following function:
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****          HAL_TIM_ConfigClockSource, the clock configuration should be done before
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****          any start function.
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****      (#) Configure the TIM in the desired functioning mode using one of the
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        Initialization function of this driver:
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             Output Compare signal.
+ARM GAS  /tmp/ccPLZXyC.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             PWM signal.
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             external signal.
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             in One Pulse Mode.
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****      (#) Activate the TIM peripheral using one of the start functions depending from the feature us
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****      (#) The DMA Burst is managed with the two following functions:
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****          HAL_TIM_DMABurst_WriteStart()
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****          HAL_TIM_DMABurst_ReadStart()
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     *** Callback registration ***
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   =============================================
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   allows the user to configure dynamically the driver callbacks.
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   Use Function HAL_TIM_RegisterCallback() to register a callback.
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   the Callback ID and a pointer to the user callback function.
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   weak function.
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   and the Callback ID.
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   These functions allow to register/unregister following callbacks:
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) TriggerCallback                   : TIM Trigger Callback.
+ARM GAS  /tmp/ccPLZXyC.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) IC_CaptureCallback                : TIM Input Capture Callback.
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) ErrorCallback                     : TIM Error Callback.
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) CommutationCallback               : TIM Commutation Callback.
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) BreakCallback                     : TIM Break Callback.
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Break2Callback                    : TIM Break2 Callback.
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** By default, after the Init and when the state is HAL_TIM_STATE_RESET
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** all interrupt callbacks are set to the corresponding weak functions:
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   functionalities in the Init / DeInit only when these callbacks are null
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     Exception done MspInit / MspDeInit that can be registered / unregistered
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   In that case first register the MspInit/MspDeInit user callbacks
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       not defined, the callback registration feature is not available and all callbacks
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       are set to the corresponding weak functions.
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   @endverbatim
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ******************************************************************************
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Includes ------------------------------------------------------------------*/
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #include "stm32f7xx_hal.h"
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @addtogroup STM32F7xx_HAL_Driver
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM TIM
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief TIM HAL module driver
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #ifdef HAL_TIM_MODULE_ENABLED
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Private typedef -----------------------------------------------------------*/
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Private define ------------------------------------------------------------*/
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Private macros ------------------------------------------------------------*/
+ARM GAS  /tmp/ccPLZXyC.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Private variables ---------------------------------------------------------*/
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Private function prototypes -----------------------------------------------*/
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @addtogroup TIM_Private_Functions
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                               uint32_t TIM_ICFilter);
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                               uint32_t TIM_ICFilter);
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                               uint32_t TIM_ICFilter);
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig);
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Exported functions --------------------------------------------------------*/
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions TIM Exported Functions
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *  @brief    Time Base functions
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****               ##### Time Base functions #####
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     This section provides functions allowing to:
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Initialize and configure the TIM base.
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) De-initialize the TIM base.
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the Time Base.
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the Time Base.
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the Time Base and enable interrupt.
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the Time Base and disable interrupt.
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the Time Base and enable DMA transfer.
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the Time Base and disable DMA transfer.
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ARM GAS  /tmp/ccPLZXyC.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM Time base Unit according to the specified
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim == NULL)
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_ResetCallback(htim);
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (htim->Base_MspInitCallback == NULL)
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Base_MspInitCallback(htim);
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     HAL_TIM_Base_MspInit(htim);
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Time Base configuration */
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the TIM channels state */
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ARM GAS  /tmp/ccPLZXyC.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the TIM state*/
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes the TIM Base peripheral
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->Base_MspDeInitCallback == NULL)
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware */
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Base_MspDeInitCallback(htim);
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_Base_MspDeInit(htim);
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the DMA burst operation state */
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the TIM channels state */
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change TIM state */
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Release Lock */
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM Base MSP.
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ARM GAS  /tmp/ccPLZXyC.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_Base_MspInit could be implemented in the user file
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes TIM Base MSP.
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Base generation.
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM state */
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->State != HAL_TIM_STATE_READY)
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+ARM GAS  /tmp/ccPLZXyC.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Base generation.
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Peripheral */
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Base generation in interrupt mode.
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM state */
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->State != HAL_TIM_STATE_READY)
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the TIM Update interrupt */
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+ARM GAS  /tmp/ccPLZXyC.s 			page 10
+
+
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Base generation in interrupt mode.
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the TIM Update interrupt */
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Peripheral */
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Base generation in DMA mode.
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  pData The source Buffer address.
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Length The length of data to be transferred from memory to peripheral.
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t L
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_BUSY)
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_BUSY;
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (htim->State == HAL_TIM_STATE_READY)
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((pData == NULL) || (Length == 0U))
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ARM GAS  /tmp/ccPLZXyC.s 			page 11
+
+
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->State = HAL_TIM_STATE_BUSY;
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the DMA Period elapsed callbacks */
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the DMA error callback */
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the DMA stream */
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->A
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                        Length) != HAL_OK)
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Return error status */
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the TIM Update DMA request */
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Base generation in DMA mode.
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Base handle
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+ARM GAS  /tmp/ccPLZXyC.s 			page 12
+
+
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the TIM Update DMA request */
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Peripheral */
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *  @brief    TIM Output Compare functions
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                   ##### TIM Output Compare functions #####
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     This section provides functions allowing to:
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Initialize and configure the TIM Output Compare.
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) De-initialize the TIM Output Compare.
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM Output Compare.
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM Output Compare.
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM Output Compare and enable interrupt.
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM Output Compare and disable interrupt.
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM Output Compare and enable DMA transfer.
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM Output Compare and disable DMA transfer.
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM Output Compare according to the specified
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim == NULL)
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ARM GAS  /tmp/ccPLZXyC.s 			page 13
+
+
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_ResetCallback(htim);
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (htim->OC_MspInitCallback == NULL)
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->OC_MspInitCallback(htim);
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     HAL_TIM_OC_MspInit(htim);
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Init the base time for the Output Compare */
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the TIM channels state */
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the TIM state*/
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes the TIM peripheral
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ARM GAS  /tmp/ccPLZXyC.s 			page 14
+
+
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->OC_MspDeInitCallback == NULL)
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware */
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->OC_MspDeInitCallback(htim);
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_OC_MspDeInit(htim);
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the DMA burst operation state */
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the TIM channels state */
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change TIM state */
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Release Lock */
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM Output Compare MSP.
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_OC_MspInit could be implemented in the user file
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes TIM Output Compare MSP.
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ARM GAS  /tmp/ccPLZXyC.s 			page 15
+
+
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Output Compare signal generation.
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channel to be enabled
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM channel state */
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Output compare channel */
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the main output */
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_MOE_ENABLE(htim);
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 16
+
+
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Output Compare signal generation.
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channel to be disabled
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Output compare channel */
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Main Output */
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_MOE_DISABLE(htim);
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Peripheral */
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channel to be enabled
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ARM GAS  /tmp/ccPLZXyC.s 			page 17
+
+
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM channel state */
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 interrupt */
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2 interrupt */
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 3 interrupt */
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4 interrupt */
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the Output compare channel */
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ARM GAS  /tmp/ccPLZXyC.s 			page 18
+
+
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the main output */
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_MOE_ENABLE(htim);
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         __HAL_TIM_ENABLE(htim);
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channel to be disabled
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 interrupt */
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 interrupt */
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 19
+
+
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3 interrupt */
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4 interrupt */
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Output compare channel */
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the Main Output */
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_MOE_DISABLE(htim);
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Peripheral */
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the TIM channel state */
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channel to be enabled
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  pData The source Buffer address.
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Length The length of data to be transferred from memory to TIM peripheral
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *p
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                        uint16_t Length)
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ARM GAS  /tmp/ccPLZXyC.s 			page 20
+
+
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_BUSY;
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((pData == NULL) || (Length == 0U))
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 DMA request */
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 21
+
+
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->
+1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2 DMA request */
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 3 DMA request */
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4 DMA request */
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ARM GAS  /tmp/ccPLZXyC.s 			page 22
+
+
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the Output compare channel */
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the main output */
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_MOE_ENABLE(htim);
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         __HAL_TIM_ENABLE(htim);
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channel to be disabled
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+ARM GAS  /tmp/ccPLZXyC.s 			page 23
+
+
+1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 DMA request */
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 DMA request */
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3 DMA request */
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4 interrupt */
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Output compare channel */
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the Main Output */
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_MOE_DISABLE(htim);
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Peripheral */
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the TIM channel state */
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ARM GAS  /tmp/ccPLZXyC.s 			page 24
+
+
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *  @brief    TIM PWM functions
+1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                           ##### TIM PWM functions #####
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     This section provides functions allowing to:
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Initialize and configure the TIM PWM.
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) De-initialize the TIM PWM.
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM PWM.
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM PWM.
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM PWM and enable interrupt.
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM PWM and disable interrupt.
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM PWM and enable DMA transfer.
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM PWM and disable DMA transfer.
+1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM PWM Time Base according to the specified
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim == NULL)
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ARM GAS  /tmp/ccPLZXyC.s 			page 25
+
+
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_ResetCallback(htim);
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (htim->PWM_MspInitCallback == NULL)
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->PWM_MspInitCallback(htim);
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     HAL_TIM_PWM_MspInit(htim);
+1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Init the base time for the PWM */
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the TIM channels state */
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the TIM state*/
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes the TIM peripheral
+1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->PWM_MspDeInitCallback == NULL)
+1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware */
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->PWM_MspDeInitCallback(htim);
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+ARM GAS  /tmp/ccPLZXyC.s 			page 26
+
+
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_PWM_MspDeInit(htim);
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the DMA burst operation state */
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the TIM channels state */
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change TIM state */
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Release Lock */
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM PWM MSP.
+1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_PWM_MspInit could be implemented in the user file
+1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes TIM PWM MSP.
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the PWM signal generation.
+1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ARM GAS  /tmp/ccPLZXyC.s 			page 27
+
+
+1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM channel state */
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Capture compare channel */
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the main output */
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_MOE_ENABLE(htim);
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the PWM signal generation.
+1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ARM GAS  /tmp/ccPLZXyC.s 			page 28
+
+
+1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Capture compare channel */
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Main Output */
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_MOE_DISABLE(htim);
+1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Peripheral */
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the PWM signal generation in interrupt mode.
+1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channel to be enabled
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM channel state */
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 29
+
+
+1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 interrupt */
+1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2 interrupt */
+1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 3 interrupt */
+1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4 interrupt */
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the Capture compare channel */
+1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the main output */
+1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_MOE_ENABLE(htim);
+1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         __HAL_TIM_ENABLE(htim);
+1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ARM GAS  /tmp/ccPLZXyC.s 			page 30
+
+
+1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the PWM signal generation in interrupt mode.
+1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 interrupt */
+1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 interrupt */
+1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3 interrupt */
+1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4 interrupt */
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+ARM GAS  /tmp/ccPLZXyC.s 			page 31
+
+
+1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Capture compare channel */
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the Main Output */
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_MOE_DISABLE(htim);
+1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Peripheral */
+1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the TIM channel state */
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM PWM signal generation in DMA mode.
+1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  pData The source Buffer address.
+1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Length The length of data to be transferred from memory to TIM peripheral
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *
+1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                         uint16_t Length)
+1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_BUSY;
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((pData == NULL) || (Length == 0U))
+1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ARM GAS  /tmp/ccPLZXyC.s 			page 32
+
+
+1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+1764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+1768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+1772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 DMA request */
+1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->
+1789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+1791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+1793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2 DMA request */
+1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 33
+
+
+1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->
+1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+1811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Output Capture/Compare 3 request */
+1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+1828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->
+1831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+1833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4 DMA request */
+1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+1843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the Capture compare channel */
+1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the main output */
+1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_MOE_ENABLE(htim);
+1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ARM GAS  /tmp/ccPLZXyC.s 			page 34
+
+
+1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         __HAL_TIM_ENABLE(htim);
+1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+1865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+1867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM PWM signal generation in DMA mode.
+1878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM PWM handle
+1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+1895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+1897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 DMA request */
+1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 DMA request */
+1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+ARM GAS  /tmp/ccPLZXyC.s 			page 35
+
+
+1913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3 DMA request */
+1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4 interrupt */
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+1931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Capture compare channel */
+1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+1939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the Main Output */
+1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_MOE_DISABLE(htim);
+1942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Peripheral */
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the TIM channel state */
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+1957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *  @brief    TIM Input Capture functions
+1961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim
+1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****               ##### TIM Input Capture functions #####
+1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****  [..]
+1967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    This section provides functions allowing to:
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) Initialize and configure the TIM Input Capture.
+1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) De-initialize the TIM Input Capture.
+ARM GAS  /tmp/ccPLZXyC.s 			page 36
+
+
+1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) Start the TIM Input Capture.
+1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) Stop the TIM Input Capture.
+1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) Start the TIM Input Capture and enable interrupt.
+1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) Stop the TIM Input Capture and disable interrupt.
+1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) Start the TIM Input Capture and enable DMA transfer.
+1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) Stop the TIM Input Capture and disable DMA transfer.
+1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim
+1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM Input Capture Time base according to the specified
+1982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+1990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim == NULL)
+1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+1996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+1998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_ResetCallback(htim);
+2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (htim->IC_MspInitCallback == NULL)
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->IC_MspInitCallback(htim);
+2020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     HAL_TIM_IC_MspInit(htim);
+2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+ARM GAS  /tmp/ccPLZXyC.s 			page 37
+
+
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Init the base time for the input capture */
+2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the TIM channels state */
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the TIM state*/
+2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes the TIM peripheral
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->IC_MspDeInitCallback == NULL)
+2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware */
+2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->IC_MspDeInitCallback(htim);
+2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+2068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_IC_MspDeInit(htim);
+2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the DMA burst operation state */
+2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+2074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the TIM channels state */
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change TIM state */
+2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Release Lock */
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+ARM GAS  /tmp/ccPLZXyC.s 			page 38
+
+
+2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM Input Capture MSP.
+2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+2092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_IC_MspInit could be implemented in the user file
+2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes TIM Input Capture MSP.
+2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_IC_MspDeInit could be implemented in the user file
+2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Input Capture measurement.
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+2134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM channel state */
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ARM GAS  /tmp/ccPLZXyC.s 			page 39
+
+
+2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Input Capture channel */
+2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Input Capture measurement.
+2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+2177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Input Capture channel */
+2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Peripheral */
+2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ARM GAS  /tmp/ccPLZXyC.s 			page 40
+
+
+2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+2214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+2215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+2218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+2220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+2221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM channel state */
+2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+2224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+2225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 interrupt */
+2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+2243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2 interrupt */
+2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 3 interrupt */
+2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+2253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ARM GAS  /tmp/ccPLZXyC.s 			page 41
+
+
+2255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+2257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4 interrupt */
+2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+2260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+2264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+2265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the Input Capture channel */
+2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         __HAL_TIM_ENABLE(htim);
+2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+2285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+2289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+2296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 42
+
+
+2312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 interrupt */
+2315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+2320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 interrupt */
+2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+2323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3 interrupt */
+2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+2334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4 interrupt */
+2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+2337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+2341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Input Capture channel */
+2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+2349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Peripheral */
+2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the TIM channel state */
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Input Capture measurement in DMA mode.
+2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ARM GAS  /tmp/ccPLZXyC.s 			page 43
+
+
+2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  pData The destination Buffer address.
+2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Length The length of data to be transferred from TIM peripheral to memory.
+2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, 
+2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+2385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_BUSY;
+2392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+2394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((pData == NULL) || (Length == 0U))
+2397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Input Capture channel */
+2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+2417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+2424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+ARM GAS  /tmp/ccPLZXyC.s 			page 44
+
+
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p
+2427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+2431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 1 DMA request */
+2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+2438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p
+2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+2450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+2453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 2  DMA request */
+2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+2463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+2466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)p
+2469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 3  DMA request */
+2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ARM GAS  /tmp/ccPLZXyC.s 			page 45
+
+
+2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+2484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)p
+2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+2493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+2495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Capture/Compare 4  DMA request */
+2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+2501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+2507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+2510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_ENABLE(htim);
+2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+2520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Input Capture measurement in DMA mode.
+2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Input Capture handle
+2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+2528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+2530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+2537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+2539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+ARM GAS  /tmp/ccPLZXyC.s 			page 46
+
+
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Input Capture channel */
+2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+2544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+2546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 1 DMA request */
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 2 DMA request */
+2558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 3  DMA request */
+2566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+2572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the TIM Capture/Compare 4  DMA request */
+2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+2580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+2581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+2585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Peripheral */
+2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE(htim);
+2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the TIM channel state */
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+2592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+2595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ARM GAS  /tmp/ccPLZXyC.s 			page 47
+
+
+2597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+2602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *  @brief    TIM One Pulse functions
+2603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim
+2605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+2606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         ##### TIM One Pulse functions #####
+2607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+2608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+2609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     This section provides functions allowing to:
+2610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Initialize and configure the TIM One Pulse.
+2611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) De-initialize the TIM One Pulse.
+2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM One Pulse.
+2613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM One Pulse.
+2614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM One Pulse and enable interrupt.
+2615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM One Pulse and disable interrupt.
+2616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM One Pulse and enable DMA transfer.
+2617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM One Pulse and disable DMA transfer.
+2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim
+2620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+2621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM One Pulse Time Base according to the specified
+2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+2625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+2626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+2627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+2628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+2629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   When the timer instance is initialized in One Pulse mode, timer
+2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         channels 1 and channel 2 are reserved and cannot be used for other
+2631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         purpose.
+2632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OnePulseMode Select the One pulse mode.
+2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         This parameter can be one of the following values:
+2635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+2636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim == NULL)
+2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+2645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+2649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+2651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ARM GAS  /tmp/ccPLZXyC.s 			page 48
+
+
+2654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+2656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+2659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+2662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_ResetCallback(htim);
+2663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (htim->OnePulse_MspInitCallback == NULL)
+2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+2667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->OnePulse_MspInitCallback(htim);
+2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+2671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     HAL_TIM_OnePulse_MspInit(htim);
+2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+2678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Configure the Time base in the One Pulse Mode */
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+2681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the OPM Bit */
+2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->CR1 &= ~TIM_CR1_OPM;
+2684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Configure the OPM Mode */
+2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->CR1 |= OnePulseMode;
+2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+2690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the TIM channels state */
+2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the TIM state*/
+2698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes the TIM One Pulse
+2705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ARM GAS  /tmp/ccPLZXyC.s 			page 49
+
+
+2711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+2712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->OnePulse_MspDeInitCallback == NULL)
+2720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware */
+2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->OnePulse_MspDeInitCallback(htim);
+2725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_OnePulse_MspDeInit(htim);
+2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the DMA burst operation state */
+2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+2732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel state */
+2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+2735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+2738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change TIM state */
+2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+2741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Release Lock */
+2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM One Pulse MSP.
+2750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+2760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes TIM One Pulse MSP.
+2765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+2767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ARM GAS  /tmp/ccPLZXyC.s 			page 50
+
+
+2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+2769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+2772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+2775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM One Pulse signal generation.
+2780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note Though OutputChannel parameter is deprecated and ignored by the function
+2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        it has been kept to avoid HAL_TIM API compatibility break.
+2782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note The pulse output channel is determined when calling
+2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+2784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OutputChannel See note above
+2786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+2789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+2792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+2794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(OutputChannel);
+2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM channels state */
+2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+2800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+2801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+2805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channels state */
+2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+2809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+2810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+2812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Capture compare and the Input Capture channels
+2814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2
+2815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+2818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     No need to enable the counter, it's enabled automatically by hardware
+2820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (the counter starts in response to a stimulus and generate a pulse */
+2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+2823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+2824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 51
+
+
+2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+2826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the main output */
+2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_MOE_ENABLE(htim);
+2829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+2833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM One Pulse signal generation.
+2837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note Though OutputChannel parameter is deprecated and ignored by the function
+2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        it has been kept to avoid HAL_TIM API compatibility break.
+2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note The pulse output channel is determined when calling
+2840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+2841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OutputChannel See note above
+2843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(OutputChannel);
+2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Capture compare and the Input Capture channels
+2851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+2852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+2854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+2857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+2858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Main Output */
+2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_MOE_DISABLE(htim);
+2863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Peripheral */
+2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+2867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channels state */
+2869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+2875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+2876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+2880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note Though OutputChannel parameter is deprecated and ignored by the function
+2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        it has been kept to avoid HAL_TIM API compatibility break.
+ARM GAS  /tmp/ccPLZXyC.s 			page 52
+
+
+2882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note The pulse output channel is determined when calling
+2883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+2884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OutputChannel See note above
+2886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+2892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+2894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(OutputChannel);
+2897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM channels state */
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+2900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+2901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+2903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channels state */
+2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+2910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+2911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Capture compare and the Input Capture channels
+2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2
+2915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+2917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+2918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     No need to enable the counter, it's enabled automatically by hardware
+2920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (the counter starts in response to a stimulus and generate a pulse */
+2921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the TIM Capture/Compare 1 interrupt */
+2923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+2924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the TIM Capture/Compare 2 interrupt */
+2926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+2927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+2930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+2932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the main output */
+2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_MOE_ENABLE(htim);
+2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+ARM GAS  /tmp/ccPLZXyC.s 			page 53
+
+
+2939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+2943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note Though OutputChannel parameter is deprecated and ignored by the function
+2944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        it has been kept to avoid HAL_TIM API compatibility break.
+2945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note The pulse output channel is determined when calling
+2946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+2947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+2948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OutputChannel See note above
+2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+2953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+2954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(OutputChannel);
+2955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the TIM Capture/Compare 1 interrupt */
+2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+2958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the TIM Capture/Compare 2 interrupt */
+2960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+2961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Capture compare and the Input Capture channels
+2963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+2964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+2965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+2968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+2969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+2971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+2972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the Main Output */
+2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_MOE_DISABLE(htim);
+2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+2975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Peripheral */
+2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+2978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channels state */
+2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+2986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+2987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+2990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+2991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+2992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+2993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *  @brief    TIM Encoder functions
+2995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+ARM GAS  /tmp/ccPLZXyC.s 			page 54
+
+
+2996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim
+2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                           ##### TIM Encoder functions #####
+2999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+3000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     This section provides functions allowing to:
+3002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Initialize and configure the TIM Encoder.
+3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) De-initialize the TIM Encoder.
+3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM Encoder.
+3005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM Encoder.
+3006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM Encoder and enable interrupt.
+3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM Encoder and disable interrupt.
+3008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Start the TIM Encoder and enable DMA transfer.
+3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (+) Stop the TIM Encoder and disable DMA transfer.
+3010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim
+3012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+3016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         requires a timer reset to avoid unexpected direction
+3018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         due to DIR bit readonly in center aligned mode.
+3019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected toge
+3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_Config
+3022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   When the timer instance is initialized in Encoder mode, timer
+3024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         channels 1 and channel 2 are reserved and cannot be used for other
+3025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         purpose.
+3026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  sConfig TIM Encoder Interface configuration structure
+3028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sCon
+3031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+3033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr1;
+3034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim == NULL)
+3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+3040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+3043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+3049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+3050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ARM GAS  /tmp/ccPLZXyC.s 			page 55
+
+
+3053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+3056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+3057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+3059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Allocate lock resource and initialize it */
+3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Lock = HAL_UNLOCKED;
+3062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset interrupt callbacks to legacy weak callbacks */
+3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_ResetCallback(htim);
+3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (htim->Encoder_MspInitCallback == NULL)
+3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Encoder_MspInitCallback(htim);
+3073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     HAL_TIM_Encoder_MspInit(htim);
+3076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM state */
+3080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the SMS and ECE bits */
+3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+3084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Configure the Time base in the Encoder Mode */
+3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+3087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx SMCR register value */
+3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr = htim->Instance->SMCR;
+3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCMR1 register value */
+3092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 = htim->Instance->CCMR1;
+3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = htim->Instance->CCER;
+3096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the encoder Mode */
+3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr |= sConfig->EncoderMode;
+3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+3106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 56
+
+
+3110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TI1 and the TI2 Polarities */
+3111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+3114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx SMCR */
+3116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->SMCR = tmpsmcr;
+3117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR1 */
+3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->CCMR1 = tmpccmr1;
+3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCER */
+3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->CCER = tmpccer;
+3123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the DMA burst operation state */
+3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channels state */
+3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Initialize the TIM state*/
+3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+3135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+3137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+3138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes the TIM Encoder interface
+3142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+3144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+3146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+3147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the TIM Peripheral Clock */
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+3154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->Encoder_MspDeInitCallback == NULL)
+3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware */
+3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Encoder_MspDeInitCallback(htim);
+3162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_Encoder_MspDeInit(htim);
+3165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 57
+
+
+3167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the DMA burst operation state */
+3168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+3169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channels state */
+3171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+3172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+3173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+3174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change TIM state */
+3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_RESET;
+3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Release Lock */
+3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+3183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+3184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM Encoder Interface MSP.
+3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+3189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+3192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_Encoder_MspInit could be implemented in the user file
+3197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+3198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  DeInitializes TIM Encoder Interface MSP.
+3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+3208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+3209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+3211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+3212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+3213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+3214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Encoder Interface.
+3217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+3219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+ARM GAS  /tmp/ccPLZXyC.s 			page 58
+
+
+3224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+3226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+3228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+3229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+3233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+3237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+3240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+3242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+3244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+3250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+3252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+3253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+3255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+3257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+3263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+3270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the encoder interface channels */
+ARM GAS  /tmp/ccPLZXyC.s 			page 59
+
+
+3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+3282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+3284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+3290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+3293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default :
+3296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+3300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Peripheral */
+3303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_ENABLE(htim);
+3304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+3306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+3307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Encoder Interface.
+3311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+3313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+3320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+3321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Input Capture channels 1 and 2
+3325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C
+3326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+3327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+3329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+3332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+3335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ARM GAS  /tmp/ccPLZXyC.s 			page 60
+
+
+3338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default :
+3341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Peripheral */
+3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+3350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+3352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+3358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+3366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+3368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Encoder Interface in interrupt mode.
+3371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+3373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+3378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+3380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+3381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+3382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+3383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+3387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+3390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+3391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+3394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ARM GAS  /tmp/ccPLZXyC.s 			page 61
+
+
+3395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+3396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+3398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+3404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+3406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+3407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+3409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+3411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+3417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+3420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+3421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+3422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+3424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the encoder interface channels */
+3435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the capture compare Interrupts 1 and/or 2 */
+3436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+3437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+3439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+3442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+3443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+3446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+3449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+3450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 62
+
+
+3452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default :
+3453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+3457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+3458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+3459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable the Peripheral */
+3463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_ENABLE(htim);
+3464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+3466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Encoder Interface in interrupt mode.
+3471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be disabled
+3473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+3478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+3481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+3482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Input Capture channels 1 and 2
+3485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C
+3486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+3487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the capture compare Interrupts 1 */
+3491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+3492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+3494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+3496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the capture compare Interrupts 2 */
+3498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+3499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+3501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+3504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the capture compare Interrupts 1 and 2 */
+3506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+3508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ARM GAS  /tmp/ccPLZXyC.s 			page 63
+
+
+3509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Peripheral */
+3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+3512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+3515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+3520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+3528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+3529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+3530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Starts the TIM Encoder Interface in DMA mode.
+3533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+3535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  pData1 The destination Buffer address for IC1.
+3540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  pData2 The destination Buffer address for IC2.
+3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Length The length of data to be transferred from TIM peripheral to memory.
+3542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+3543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pD
+3545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                             uint32_t *pData2, uint16_t Length)
+3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+3547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+3548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+3551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+3553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+3556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+3557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+3560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_BUSY;
+3562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+3564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+3565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ARM GAS  /tmp/ccPLZXyC.s 			page 64
+
+
+3566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if ((pData1 == NULL) || (Length == 0U))
+3567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+3569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       else
+3571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+3577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+3579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+3582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+3584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+3585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_BUSY;
+3587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+3589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+3590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if ((pData2 == NULL) || (Length == 0U))
+3592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+3594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       else
+3596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+3602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+3604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+3607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+3609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+3610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+3611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+3612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_BUSY;
+3614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+3616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+3617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+3619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
+3621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+ARM GAS  /tmp/ccPLZXyC.s 			page 65
+
+
+3623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       else
+3625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+3629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+3630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+3633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+3635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+3639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+3641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+3644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+3645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p
+3651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+3652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+3654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+3655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Input Capture DMA request */
+3657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+3658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the Capture compare channel */
+3660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the Peripheral */
+3663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+3664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+3666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+3669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+3672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+3673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+3675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+3676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p
+3678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+3679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ARM GAS  /tmp/ccPLZXyC.s 			page 66
+
+
+3680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+3681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+3682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Input Capture  DMA request */
+3684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+3685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the Capture compare channel */
+3687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the Peripheral */
+3690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+3691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+3693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+3696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+3700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+3703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p
+3706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+3707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+3710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+3713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+3715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+3717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+3718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p
+3721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+3724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Input Capture  DMA request */
+3728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+3729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Input Capture  DMA request */
+3730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+3731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the Capture compare channel */
+3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+3734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+3735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the Peripheral */
+ARM GAS  /tmp/ccPLZXyC.s 			page 67
+
+
+3737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE(htim);
+3738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+3740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+3744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+3745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+3746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM Encoder Interface in DMA mode.
+3749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+3751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+3752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+3753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+3754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+3755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+3756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+3758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+3759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+3761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Input Capture channels 1 and 2
+3763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C
+3764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+3765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the capture compare DMA Request 1 */
+3769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+3770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+3771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+3773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+3775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the capture compare DMA Request 2 */
+3777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+3778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+3779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+3781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+3783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+3784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the capture compare DMA Request 1 and 2 */
+3786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+3787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+3788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Peripheral */
+3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE(htim);
+ARM GAS  /tmp/ccPLZXyC.s 			page 68
+
+
+3794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TIM channel(s) state */
+3796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+3802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+3806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+3807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+3811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+3812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+3815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+3817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *  @brief    TIM IRQ handler management
+3818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+3819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim
+3820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         ##### IRQ handler management #####
+3822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+3823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   [..]
+3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     This section provides Timer IRQ handler function.
+3825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim
+3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+3828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+3830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  This function handles TIM interrupts requests.
+3831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM  handle
+3832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+3833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+3834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+3835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+3836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t itsource = htim->Instance->DIER;
+3837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t itflag   = htim->Instance->SR;
+3838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Capture compare 1 event */
+3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
+3841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
+3843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
+3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+3847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+3848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Input capture event */
+3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+3850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ARM GAS  /tmp/ccPLZXyC.s 			page 69
+
+
+3851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->IC_CaptureCallback(htim);
+3853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           HAL_TIM_IC_CaptureCallback(htim);
+3855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+3857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Output compare event */
+3858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         else
+3859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+3860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->OC_DelayElapsedCallback(htim);
+3862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->PWM_PulseFinishedCallback(htim);
+3863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           HAL_TIM_OC_DelayElapsedCallback(htim);
+3865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           HAL_TIM_PWM_PulseFinishedCallback(htim);
+3866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+3868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+3869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Capture compare 2 event */
+3873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
+3874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
+3876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
+3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+3879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Input capture event */
+3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+3881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_CaptureCallback(htim);
+3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_IC_CaptureCallback(htim);
+3886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Output compare event */
+3889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       else
+3890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_DelayElapsedCallback(htim);
+3893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_PulseFinishedCallback(htim);
+3894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_OC_DelayElapsedCallback(htim);
+3896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+3897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+3900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Capture compare 3 event */
+3903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
+3904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
+3906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
+ARM GAS  /tmp/ccPLZXyC.s 			page 70
+
+
+3908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+3909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Input capture event */
+3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+3911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_CaptureCallback(htim);
+3914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_IC_CaptureCallback(htim);
+3916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Output compare event */
+3919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       else
+3920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_DelayElapsedCallback(htim);
+3923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_PulseFinishedCallback(htim);
+3924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_OC_DelayElapsedCallback(htim);
+3926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+3927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+3930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Capture compare 4 event */
+3933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
+3934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
+3936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
+3938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+3939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Input capture event */
+3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+3941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_CaptureCallback(htim);
+3944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_IC_CaptureCallback(htim);
+3946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Output compare event */
+3949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       else
+3950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+3951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_DelayElapsedCallback(htim);
+3953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_PulseFinishedCallback(htim);
+3954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_OC_DelayElapsedCallback(htim);
+3956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+3957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+3959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+3960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* TIM Update event */
+3963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
+3964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 71
+
+
+3965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
+3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
+3968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->PeriodElapsedCallback(htim);
+3970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       HAL_TIM_PeriodElapsedCallback(htim);
+3972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* TIM Break input event */
+3976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
+3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
+3978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
+3980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
+3982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->BreakCallback(htim);
+3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       HAL_TIMEx_BreakCallback(htim);
+3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+3987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+3988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+3989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* TIM Break2 input event */
+3990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
+3991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
+3993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+3994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+3995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+3996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Break2Callback(htim);
+3997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       HAL_TIMEx_Break2Callback(htim);
+3999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+4000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* TIM Trigger detection event */
+4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
+4004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
+4006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
+4008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->TriggerCallback(htim);
+4010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+4011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       HAL_TIM_TriggerCallback(htim);
+4012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+4013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* TIM commutation event */
+4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
+4017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
+4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
+4021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ARM GAS  /tmp/ccPLZXyC.s 			page 72
+
+
+4022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->CommutationCallback(htim);
+4023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+4024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       HAL_TIMEx_CommutCallback(htim);
+4025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+4026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+4029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+4031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+4032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+4033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+4035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *  @brief    TIM Peripheral Control functions
+4036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+4037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim
+4038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+4039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                    ##### Peripheral Control functions #####
+4040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+4041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****  [..]
+4042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    This section provides functions allowing to:
+4043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+4044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (+) Configure External Clock source.
+4045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (+) Configure Complementary channels, break features and dead time.
+4046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (+) Configure Master and the Slave synchronization.
+4047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (+) Configure the DMA Burst Mode.
+4048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim
+4050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+4051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+4052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+4054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM Output Compare Channels according to the specified
+4055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         parameters in the TIM_OC_InitTypeDef.
+4056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+4057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  sConfig TIM Output Compare configuration structure
+4058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to configure
+4059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+4060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+4061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+4062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+4063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+4064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+4065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+4066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+4067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+4068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+4069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                            const TIM_OC_InitTypeDef *sConfig,
+4070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                            uint32_t Channel)
+4071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+4075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CHANNELS(Channel));
+4076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+4077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+4078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 73
+
+
+4079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Process Locked */
+4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_LOCK(htim);
+4081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+4083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+4085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+4088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the TIM Channel 1 in Output Compare */
+4090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC1_SetConfig(htim->Instance, sConfig);
+4091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+4095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+4098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the TIM Channel 2 in Output Compare */
+4100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC2_SetConfig(htim->Instance, sConfig);
+4101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+4105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+4108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the TIM Channel 3 in Output Compare */
+4110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC3_SetConfig(htim->Instance, sConfig);
+4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+4115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+4118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the TIM Channel 4 in Output Compare */
+4120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC4_SetConfig(htim->Instance, sConfig);
+4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_5:
+4125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+4128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the TIM Channel 5 in Output Compare */
+4130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC5_SetConfig(htim->Instance, sConfig);
+4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_6:
+4135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ARM GAS  /tmp/ccPLZXyC.s 			page 74
+
+
+4136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+4138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the TIM Channel 6 in Output Compare */
+4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC6_SetConfig(htim->Instance, sConfig);
+4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+4145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+4146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+4150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+4152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+4153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+4155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM Input Capture Channels according to the specified
+4156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         parameters in the TIM_IC_InitTypeDef.
+4157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM IC handle
+4158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  sConfig TIM Input Capture configuration structure
+4159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channel to configure
+4160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+4161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+4162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+4163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+4164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+4165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+4166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+4167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConf
+4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+4172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+4174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+4175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+4177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Process Locked */
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_LOCK(htim);
+4180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (Channel == TIM_CHANNEL_1)
+4182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* TI1 Configuration */
+4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_TI1_SetConfig(htim->Instance,
+4185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+4186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICSelection,
+4187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICFilter);
+4188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the IC1PSC Bits */
+4190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+4191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the IC1PSC value */
+ARM GAS  /tmp/ccPLZXyC.s 			page 75
+
+
+4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+4194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_2)
+4196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* TI2 Configuration */
+4198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+4199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_TI2_SetConfig(htim->Instance,
+4201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+4202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICSelection,
+4203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICFilter);
+4204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the IC2PSC Bits */
+4206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+4207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the IC2PSC value */
+4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+4210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_3)
+4212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* TI3 Configuration */
+4214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+4215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_TI3_SetConfig(htim->Instance,
+4217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+4218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICSelection,
+4219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICFilter);
+4220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the IC3PSC Bits */
+4222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+4223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the IC3PSC value */
+4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+4226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (Channel == TIM_CHANNEL_4)
+4228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* TI4 Configuration */
+4230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+4231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_TI4_SetConfig(htim->Instance,
+4233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+4234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICSelection,
+4235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICFilter);
+4236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the IC4PSC Bits */
+4238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+4239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the IC4PSC value */
+4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+4242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+4244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     status = HAL_ERROR;
+4246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+4249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 76
+
+
+4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+4251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+4252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+4254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM PWM  channels according to the specified
+4255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         parameters in the TIM_OC_InitTypeDef.
+4256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM PWM handle
+4257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  sConfig TIM PWM configuration structure
+4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be configured
+4259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+4260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+4261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+4262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+4263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+4264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+4265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+4266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+4268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+4269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                             const TIM_OC_InitTypeDef *sConfig,
+4270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                             uint32_t Channel)
+4271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+4275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CHANNELS(Channel));
+4276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+4277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+4278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+4279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Process Locked */
+4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_LOCK(htim);
+4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+4284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+4286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+4289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Channel 1 in PWM mode */
+4291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC1_SetConfig(htim->Instance, sConfig);
+4292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the Preload enable bit for channel1 */
+4294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+4295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode;
+4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+4306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 77
+
+
+4307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Channel 2 in PWM mode */
+4308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC2_SetConfig(htim->Instance, sConfig);
+4309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the Preload enable bit for channel2 */
+4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+4312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+4316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+4320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+4323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Channel 3 in PWM mode */
+4325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC3_SetConfig(htim->Instance, sConfig);
+4326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the Preload enable bit for channel3 */
+4328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+4329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode;
+4333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+4337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+4340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Channel 4 in PWM mode */
+4342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC4_SetConfig(htim->Instance, sConfig);
+4343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the Preload enable bit for channel4 */
+4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+4346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+4350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_5:
+4354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+4357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Channel 5 in PWM mode */
+4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC5_SetConfig(htim->Instance, sConfig);
+4360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the Preload enable bit for channel5*/
+4362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+4363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 78
+
+
+4364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode;
+4367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_6:
+4371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+4373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+4374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Channel 6 in PWM mode */
+4376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_OC6_SetConfig(htim->Instance, sConfig);
+4377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the Preload enable bit for channel6 */
+4379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+4380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the Output Fast mode */
+4382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+4384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+4388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+4389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+4393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+4396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+4398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Initializes the TIM One Pulse Channels according to the specified
+4399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         parameters in the TIM_OnePulse_InitTypeDef.
+4400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM One Pulse handle
+4401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  sConfig TIM One Pulse configuration structure
+4402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OutputChannel TIM output channel to configure
+4403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+4404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+4406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  InputChannel TIM input Channel to configure
+4407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+4408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+4409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+4410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note  To output a waveform with a minimum delay user can enable the fast
+4411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+4412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        output is forced in response to the edge detection on TIx input,
+4413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        without taking in account the comparison.
+4414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+4415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+4416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef
+4417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                                  uint32_t OutputChannel,  uint32_t InputChannel)
+4418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+4419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_OC_InitTypeDef temp1;
+ARM GAS  /tmp/ccPLZXyC.s 			page 79
+
+
+4421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+4423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+4424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+4425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (OutputChannel != InputChannel)
+4427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Process Locked */
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_LOCK(htim);
+4430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_BUSY;
+4432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Extract the Output compare configuration from sConfig structure */
+4434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCMode = sConfig->OCMode;
+4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.Pulse = sConfig->Pulse;
+4436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCPolarity = sConfig->OCPolarity;
+4437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCNPolarity = sConfig->OCNPolarity;
+4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCIdleState = sConfig->OCIdleState;
+4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCNIdleState = sConfig->OCNIdleState;
+4440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     switch (OutputChannel)
+4442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case TIM_CHANNEL_1:
+4444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+4445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+4446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_OC1_SetConfig(htim->Instance, &temp1);
+4448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+4449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+4450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case TIM_CHANNEL_2:
+4452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+4453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+4454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_OC2_SetConfig(htim->Instance, &temp1);
+4456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+4457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+4458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       default:
+4460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         status = HAL_ERROR;
+4461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+4462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (status == HAL_OK)
+4465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       switch (InputChannel)
+4467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+4468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         case TIM_CHANNEL_1:
+4469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+4470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+4471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+4473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                             sConfig->ICSelection, sConfig->ICFilter);
+4474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Reset the IC1PSC Bits */
+4476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+4477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 80
+
+
+4478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Select the Trigger source */
+4479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR &= ~TIM_SMCR_TS;
+4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI1FP1;
+4481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Select the Slave Mode */
+4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+4485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           break;
+4486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+4487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         case TIM_CHANNEL_2:
+4489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+4490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+4491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+4493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                             sConfig->ICSelection, sConfig->ICFilter);
+4494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Reset the IC2PSC Bits */
+4496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+4497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Select the Trigger source */
+4499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR &= ~TIM_SMCR_TS;
+4500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI2FP2;
+4501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Select the Slave Mode */
+4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+4504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+4505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           break;
+4506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+4507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         default:
+4509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           status = HAL_ERROR;
+4510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           break;
+4511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+4512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+4515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+4517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return status;
+4519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+4521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+4523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+4525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+4527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+4528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+4529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+4530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR1
+4532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR2
+4533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_SMCR
+4534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_DIER
+ARM GAS  /tmp/ccPLZXyC.s 			page 81
+
+
+4535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_SR
+4536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_EGR
+4537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR1
+4538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR2
+4539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCER
+4540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CNT
+4541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_PSC
+4542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_ARR
+4543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_RCR
+4544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR1
+4545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR2
+4546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR3
+4547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR4
+4548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_BDTR
+4549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_OR
+4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR3
+4551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR5
+4552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR6
+4553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF1  (*)
+4554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF2  (*)
+4555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         (*) value not defined in all devices
+4556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources
+4557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+4559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+4560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+4561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+4562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+4563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_COM: TIM Commutation DMA source
+4564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+4565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstBuffer The Buffer address.
+4566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstLength DMA Burst length. This parameter can be one value
+4567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+4568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   This function should be used only when BurstLength is equal to DMA data transfer length
+4569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+4570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+4571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+4572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                               uint32_t BurstRequestSrc, const uint32_t *BurstBuffer
+4573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                               uint32_t  BurstLength)
+4574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+4575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status;
+4576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, B
+4578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                             ((BurstLength) >> 8U) + 1U);
+4579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+4583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+4584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+4586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+4587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+4588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+4589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR1
+4591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR2
+ARM GAS  /tmp/ccPLZXyC.s 			page 82
+
+
+4592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_SMCR
+4593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_DIER
+4594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_SR
+4595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_EGR
+4596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR1
+4597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR2
+4598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCER
+4599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CNT
+4600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_PSC
+4601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_ARR
+4602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_RCR
+4603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR1
+4604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR2
+4605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR3
+4606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR4
+4607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_BDTR
+4608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_OR
+4609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR3
+4610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR5
+4611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR6
+4612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF1  (*)
+4613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF2  (*)
+4614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         (*) value not defined in all devices
+4615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources
+4616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+4618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+4619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+4620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+4621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+4622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_COM: TIM Commutation DMA source
+4623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+4624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstBuffer The Buffer address.
+4625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstLength DMA Burst length. This parameter can be one value
+4626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+4627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  DataLength Data length. This parameter can be one value
+4628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         between 1 and 0xFFFF.
+4629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+4630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+4631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddre
+4632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                                    uint32_t BurstRequestSrc, const uint32_t *BurstB
+4633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                                    uint32_t  BurstLength,  uint32_t  DataLength)
+4634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+4635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+4638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+4639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+4640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+4642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+4643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+4645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_BUSY;
+4647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+ARM GAS  /tmp/ccPLZXyC.s 			page 83
+
+
+4649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((BurstBuffer == NULL) && (BurstLength > 0U))
+4651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+4653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+4655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+4657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+4660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* nothing to do */
+4662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (BurstRequestSrc)
+4665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_UPDATE:
+4667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA Period elapsed callbacks */
+4669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+4671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+4673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+4674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+4676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+4677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+4679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+4680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+4681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+4682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC1:
+4685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+4688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+4689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+4691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+4692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+4695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+4697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+4698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+4699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+4700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC2:
+4703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+4705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ARM GAS  /tmp/ccPLZXyC.s 			page 84
+
+
+4706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+4707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+4709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+4710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+4713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+4715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+4716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+4717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+4718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC3:
+4721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+4723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+4724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+4725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+4727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+4728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+4730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+4731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+4733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+4734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+4735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+4736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC4:
+4739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA compare callbacks */
+4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+4742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+4743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+4745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+4746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+4749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+4751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+4752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+4753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+4754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_COM:
+4757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA commutation callbacks */
+4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+4760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+4761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+ARM GAS  /tmp/ccPLZXyC.s 			page 85
+
+
+4763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+4764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+4766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+4767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+4769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+4770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+4771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+4772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_TRIGGER:
+4775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA trigger callbacks */
+4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+4779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+4781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+4782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+4785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+4786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+4787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+4788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+4789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+4790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+4793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+4794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+4798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Configure the DMA Burst Mode */
+4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+4801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+4802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+4803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+4806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+4807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+4808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+4810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stops the TIM DMA Burst mode
+4811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+4812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources to disable
+4813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+4814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+4815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+4816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+4817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ARM GAS  /tmp/ccPLZXyC.s 			page 86
+
+
+4820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+4821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Abort the DMA transfer (at least disable the DMA stream) */
+4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (BurstRequestSrc)
+4824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_UPDATE:
+4826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+4828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC1:
+4831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+4833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC2:
+4836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+4838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC3:
+4841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+4843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC4:
+4846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+4848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_COM:
+4851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+4853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_TRIGGER:
+4856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+4858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+4860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+4861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+4862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+4863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+4866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the TIM Update DMA request */
+4868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+4869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Change the DMA burst operation state */
+4871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+4872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+4875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+4876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ARM GAS  /tmp/ccPLZXyC.s 			page 87
+
+
+4877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+4879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+4880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+4881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+4882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR1
+4884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR2
+4885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_SMCR
+4886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_DIER
+4887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_SR
+4888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_EGR
+4889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR1
+4890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR2
+4891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCER
+4892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CNT
+4893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_PSC
+4894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_ARR
+4895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_RCR
+4896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR1
+4897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR2
+4898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR3
+4899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR4
+4900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_BDTR
+4901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_OR
+4902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR3
+4903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR5
+4904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR6
+4905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF1  (*)
+4906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF2  (*)
+4907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         (*) value not defined in all devices
+4908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources
+4909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+4911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+4912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+4913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+4914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+4915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_COM: TIM Commutation DMA source
+4916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+4917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstBuffer The Buffer address.
+4918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstLength DMA Burst length. This parameter can be one value
+4919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+4920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   This function should be used only when BurstLength is equal to DMA data transfer length
+4921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+4922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+4923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+4924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint
+4925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+4926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status;
+4927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bu
+4929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                            ((BurstLength) >> 8U) + 1U);
+4930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+4933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ARM GAS  /tmp/ccPLZXyC.s 			page 88
+
+
+4934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+4936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+4937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+4938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+4939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR1
+4941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CR2
+4942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_SMCR
+4943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_DIER
+4944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_SR
+4945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_EGR
+4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR1
+4947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR2
+4948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCER
+4949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CNT
+4950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_PSC
+4951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_ARR
+4952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_RCR
+4953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR1
+4954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR2
+4955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR3
+4956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR4
+4957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_BDTR
+4958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_OR
+4959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCMR3
+4960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR5
+4961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_CCR6
+4962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF1  (*)
+4963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMABASE_AF2  (*)
+4964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         (*) value not defined in all devices
+4965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources
+4966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         This parameter can be one of the following values:
+4967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+4968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+4970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+4971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+4972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_COM: TIM Commutation DMA source
+4973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+4974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstBuffer The Buffer address.
+4975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstLength DMA Burst length. This parameter can be one value
+4976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+4977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  DataLength Data length. This parameter can be one value
+4978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         between 1 and 0xFFFF.
+4979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+4980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+4981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddres
+4982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+4983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                                   uint32_t  BurstLength, uint32_t  DataLength)
+4984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+4986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+4989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ARM GAS  /tmp/ccPLZXyC.s 			page 89
+
+
+4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+4992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+4993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+4995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+4996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_BUSY;
+4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+4998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if ((BurstBuffer == NULL) && (BurstLength > 0U))
+5001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       return HAL_ERROR;
+5003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     else
+5005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+5007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+5010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* nothing to do */
+5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (BurstRequestSrc)
+5014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_UPDATE:
+5016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA Period elapsed callbacks */
+5018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+5020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+5022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+5023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_
+5026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+5029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+5030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC1:
+5034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+5036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+5037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+5038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+5040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)B
+5044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+5047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+ARM GAS  /tmp/ccPLZXyC.s 			page 90
+
+
+5048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC2:
+5052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+5054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+5055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+5056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+5058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+5059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)B
+5062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+5065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+5066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC3:
+5070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+5072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+5073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+5074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+5076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+5077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)B
+5080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+5083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+5084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC4:
+5088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA capture callbacks */
+5090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+5091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+5092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+5094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+5095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)B
+5098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+5101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+5102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ARM GAS  /tmp/ccPLZXyC.s 			page 91
+
+
+5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_COM:
+5106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA commutation callbacks */
+5108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+5109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+5110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+5112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+5113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (ui
+5116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+5119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+5120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_TRIGGER:
+5124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA trigger callbacks */
+5126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+5127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the DMA error callback */
+5130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+5131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32
+5134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+5135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+5137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+5138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+5143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+5147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Configure the DMA Burst Mode */
+5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+5150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+5152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+5156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+5157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Stop the DMA burst reading
+5161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+ARM GAS  /tmp/ccPLZXyC.s 			page 92
+
+
+5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  BurstRequestSrc TIM DMA Request sources to disable.
+5163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+5164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+5166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+5168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+5170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+5171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Abort the DMA transfer (at least disable the DMA stream) */
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (BurstRequestSrc)
+5174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_UPDATE:
+5176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+5178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC1:
+5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+5183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC2:
+5186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+5188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC3:
+5191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+5193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_CC4:
+5196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+5198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_COM:
+5201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+5203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_DMA_TRIGGER:
+5206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+5208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+5211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+5212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+5216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Disable the TIM Update DMA request */
+5218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ARM GAS  /tmp/ccPLZXyC.s 			page 93
+
+
+5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Change the DMA burst operation state */
+5221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+5222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+5225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+5226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Generate a software event
+5230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+5231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  EventSource specifies the event source.
+5232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+5233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+5234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+5235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+5236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+5237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+5238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+5239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+5240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+5241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+5242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   Basic timers can only generate an update event.
+5243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+5244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+5245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         only for timer instances supporting break input(s).
+5246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+5247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+5250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+5252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+5253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+5254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Process Locked */
+5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_LOCK(htim);
+5257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the TIM state */
+5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+5260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the event sources */
+5262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->EGR = EventSource;
+5263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Change the TIM state */
+5265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+5266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+5268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Return function status */
+5270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+5271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configures the OCRef clear feature
+5275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+ARM GAS  /tmp/ccPLZXyC.s 			page 94
+
+
+5276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+5277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         contains the OCREF clear feature and parameters for the TIM peripheral.
+5278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel specifies the TIM Channel
+5279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+5280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1
+5281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2
+5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3
+5283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4
+5284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5
+5285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6
+5286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+5287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                            const TIM_ClearInputConfigTypeDef *sClearInputConfig,
+5290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                            uint32_t Channel)
+5291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+5293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+5295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+5296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+5297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Process Locked */
+5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_LOCK(htim);
+5300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+5302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (sClearInputConfig->ClearInputSource)
+5304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLEARINPUTSOURCE_NONE:
+5306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Clear the OCREF clear selection bit and the the ETR Bits */
+5308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP))
+5309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLEARINPUTSOURCE_ETR:
+5313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+5315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+5316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+5317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+5318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+5320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+5321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->State = HAL_TIM_STATE_READY;
+5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         __HAL_UNLOCK(htim);
+5324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+5325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_ETR_SetConfig(htim->Instance,
+5328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClearInputConfig->ClearInputPrescaler,
+5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClearInputConfig->ClearInputPolarity,
+5330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClearInputConfig->ClearInputFilter);
+5331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ARM GAS  /tmp/ccPLZXyC.s 			page 95
+
+
+5333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+5335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+5336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (status == HAL_OK)
+5340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     switch (Channel)
+5342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case TIM_CHANNEL_1:
+5344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 1 */
+5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+5349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         else
+5351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 1 */
+5353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+5354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+5356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case TIM_CHANNEL_2:
+5358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 2 */
+5362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+5363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         else
+5365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 2 */
+5367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+5368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+5370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case TIM_CHANNEL_3:
+5372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 3 */
+5376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+5377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         else
+5379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 3 */
+5381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+5382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+5384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case TIM_CHANNEL_4:
+5386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 4 */
+ARM GAS  /tmp/ccPLZXyC.s 			page 96
+
+
+5390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+5391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         else
+5393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 4 */
+5395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+5396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+5398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case TIM_CHANNEL_5:
+5400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 5 */
+5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+5405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         else
+5407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 5 */
+5409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+5410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+5412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case TIM_CHANNEL_6:
+5414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+5415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+5416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Enable the OCREF clear feature for Channel 6 */
+5418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+5419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         else
+5421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+5422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           /* Disable the OCREF clear feature for Channel 6 */
+5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+5424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+5425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+5426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+5427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       default:
+5428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+5429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+5433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+5435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+5437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief   Configures the clock source to be used
+5441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+5442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+5443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         contains the clock source information for the TIM peripheral.
+5444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+5445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *
+ARM GAS  /tmp/ccPLZXyC.s 			page 97
+
+
+5447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+5449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+5450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Process Locked */
+5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_LOCK(htim);
+5453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+5455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+5457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+5458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+5460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr = htim->Instance->SMCR;
+5461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+5463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->SMCR = tmpsmcr;
+5464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (sClockSourceConfig->ClockSource)
+5466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLOCKSOURCE_INTERNAL:
+5468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_INSTANCE(htim->Instance));
+5470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ETRMODE1:
+5474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+5476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+5477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check ETR input conditioning related parameters */
+5479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+5481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+5482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the ETR Clock source */
+5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_ETR_SetConfig(htim->Instance,
+5485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+5486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPolarity,
+5487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockFilter);
+5488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Select the External clock mode1 and the ETRF trigger */
+5490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpsmcr = htim->Instance->SMCR;
+5491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+5492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Write to TIMx SMCR */
+5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->SMCR = tmpsmcr;
+5494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ETRMODE2:
+5498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+5500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+5501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check ETR input conditioning related parameters */
+5503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ARM GAS  /tmp/ccPLZXyC.s 			page 98
+
+
+5504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+5505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+5506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the ETR Clock source */
+5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_ETR_SetConfig(htim->Instance,
+5509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+5510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPolarity,
+5511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockFilter);
+5512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the External clock mode2 */
+5513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->SMCR |= TIM_SMCR_ECE;
+5514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLOCKSOURCE_TI1:
+5518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check whether or not the timer instance supports external clock mode 1 */
+5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+5521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check TI1 input conditioning related parameters */
+5523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+5525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_TI1_ConfigInputStage(htim->Instance,
+5527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+5528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockFilter);
+5529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+5530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLOCKSOURCE_TI2:
+5534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+5536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+5537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check TI2 input conditioning related parameters */
+5539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+5540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+5541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_TI2_ConfigInputStage(htim->Instance,
+5543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+5544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockFilter);
+5545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+5546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLOCKSOURCE_TI1ED:
+5550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check whether or not the timer instance supports external clock mode 1 */
+5552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+5553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check TI1 input conditioning related parameters */
+5555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+5556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+5557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_TI1_ConfigInputStage(htim->Instance,
+5559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+5560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockFilter);
+ARM GAS  /tmp/ccPLZXyC.s 			page 99
+
+
+5561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+5562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR0:
+5566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR1:
+5567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR2:
+5568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CLOCKSOURCE_ITR3:
+5569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check whether or not the timer instance supports internal trigger input */
+5571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+5572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+5578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+5579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+5582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+5584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+5586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+5590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         or a XOR combination between CH1_input, CH2_input & CH3_input
+5591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle.
+5592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+5593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         output of a XOR gate.
+5594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+5595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+5596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+5597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            pins are connected to the TI1 input (XOR combination)
+5598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+5599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+5601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr2;
+5603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+5605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+5606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+5607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+5609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpcr2 = htim->Instance->CR2;
+5610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the TI1 selection */
+5612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpcr2 &= ~TIM_CR2_TI1S;
+5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the TI1 selection */
+5615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpcr2 |= TI1_Selection;
+5616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMxCR2 */
+ARM GAS  /tmp/ccPLZXyC.s 			page 100
+
+
+5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->CR2 = tmpcr2;
+5619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+5621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configures the TIM in Slave mode
+5625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle.
+5626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+5627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         contains the selected trigger (internal trigger input, filtered
+5628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         timer input or external trigger input) and the Slave mode
+5629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+5630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+5631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef 
+5633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+5635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+5637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+5638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_LOCK(htim);
+5640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+5642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+5644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+5647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+5648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable Trigger Interrupt */
+5651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+5652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable Trigger DMA request */
+5654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+5655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+5657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+5661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configures the TIM in Slave mode in interrupt mode
+5665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle.
+5666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         contains the selected trigger (internal trigger input, filtered
+5668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         timer input or external trigger input) and the Slave mode
+5669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+5670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL status
+5671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+5673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                                 const TIM_SlaveConfigTypeDef *sSlaveConfig)
+5674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ARM GAS  /tmp/ccPLZXyC.s 			page 101
+
+
+5675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+5676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+5678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+5679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_LOCK(htim);
+5681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_BUSY;
+5683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+5685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+5687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+5689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Enable Trigger Interrupt */
+5692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+5693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable Trigger DMA request */
+5695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+5696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->State = HAL_TIM_STATE_READY;
+5698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   __HAL_UNLOCK(htim);
+5700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return HAL_OK;
+5702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Read the captured value from Capture Compare unit
+5706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle.
+5707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channels to be enabled
+5708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+5709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+5710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+5711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+5712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval Captured value
+5714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
+5716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpreg = 0U;
+5718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (Channel)
+5720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_1:
+5722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+5725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Return the capture 1 value */
+5727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpreg =  htim->Instance->CCR1;
+5728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_2:
+ARM GAS  /tmp/ccPLZXyC.s 			page 102
+
+
+5732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+5734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+5735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Return the capture 2 value */
+5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpreg =   htim->Instance->CCR2;
+5738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_3:
+5743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+5745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+5746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Return the capture 3 value */
+5748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpreg =   htim->Instance->CCR3;
+5749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_CHANNEL_4:
+5754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+5756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+5757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Return the capture 4 value */
+5759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpreg =   htim->Instance->CCR4;
+5760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+5763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+5765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+5766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return tmpreg;
+5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+5773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+5776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *  @brief    TIM Callbacks functions
+5777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+5778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim
+5779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+5780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         ##### TIM Callbacks functions #####
+5781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+5782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****  [..]
+5783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    This section provides TIM callback functions:
+5784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) TIM Period elapsed callback
+5785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) TIM Output Compare callback
+5786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) TIM Input capture callback
+5787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) TIM Trigger callback
+5788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    (+) TIM Error callback
+ARM GAS  /tmp/ccPLZXyC.s 			page 103
+
+
+5789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim
+5791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+5792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Period elapsed callback in non-blocking mode
+5796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+5797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+5798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+5800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+5803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+5806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Period elapsed half complete callback in non-blocking mode
+5811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+5812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+5813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+5818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+5821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+5822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Output Compare callback in non-blocking mode
+5826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM OC handle
+5827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+5828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+5830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+5833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+5836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+5837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Input Capture callback in non-blocking mode
+5841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM IC handle
+5842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+5843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+5845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ARM GAS  /tmp/ccPLZXyC.s 			page 104
+
+
+5846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+5848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+5851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+5852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Input Capture half complete callback in non-blocking mode
+5856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM IC handle
+5857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+5858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+5863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+5866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+5867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  PWM Pulse finished callback in non-blocking mode
+5871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+5872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+5873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+5878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+5881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+5882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  PWM Pulse finished half complete callback in non-blocking mode
+5886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+5887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+5888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+5890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+5893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+5896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+5897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Hall Trigger detection callback in non-blocking mode
+5901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+5902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+ARM GAS  /tmp/ccPLZXyC.s 			page 105
+
+
+5903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+5905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+5908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_TriggerCallback could be implemented in the user file
+5911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Hall Trigger detection half complete callback in non-blocking mode
+5916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+5917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+5918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+5920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+5923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+5926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+5927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Timer error callback in non-blocking mode
+5931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+5932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+5933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+5935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+5937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   UNUSED(htim);
+5938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+5940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****             the HAL_TIM_ErrorCallback could be implemented in the user file
+5941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****    */
+5942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+5943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+5945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+5946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+5947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param htim tim handle
+5948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param CallbackID ID of the callback to be registered
+5949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        This parameter can be one of the following values:
+5950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+5951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+5952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+5953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+5954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+5955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+5956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+5957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+5958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+5959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ARM GAS  /tmp/ccPLZXyC.s 			page 106
+
+
+5960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+5961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+5962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+5963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+5964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+5965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+5966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+5967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+5968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+5969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+5970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+5971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+5972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callb
+5973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+5974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+5975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+5976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+5977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+5978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @param pCallback pointer to the callback function
+5979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @retval status
+5980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+5981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Callb
+5982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                            pTIM_CallbackTypeDef pCallback)
+5983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+5984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+5985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (pCallback == NULL)
+5987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+5989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+5990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_READY)
+5992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+5993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     switch (CallbackID)
+5994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+5995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BASE_MSPINIT_CB_ID :
+5996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Base_MspInitCallback                 = pCallback;
+5997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+5998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+5999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+6000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Base_MspDeInitCallback               = pCallback;
+6001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_MSPINIT_CB_ID :
+6004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_MspInitCallback                   = pCallback;
+6005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_MSPDEINIT_CB_ID :
+6008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_MspDeInitCallback                 = pCallback;
+6009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_OC_MSPINIT_CB_ID :
+6012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_MspInitCallback                   = pCallback;
+6013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_OC_MSPDEINIT_CB_ID :
+6016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_MspDeInitCallback                 = pCallback;
+ARM GAS  /tmp/ccPLZXyC.s 			page 107
+
+
+6017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_MSPINIT_CB_ID :
+6020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_MspInitCallback                  = pCallback;
+6021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+6024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_MspDeInitCallback                = pCallback;
+6025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+6028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OnePulse_MspInitCallback             = pCallback;
+6029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+6032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OnePulse_MspDeInitCallback           = pCallback;
+6033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+6036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Encoder_MspInitCallback              = pCallback;
+6037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+6040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Encoder_MspDeInitCallback            = pCallback;
+6041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+6044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->HallSensor_MspInitCallback           = pCallback;
+6045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+6048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->HallSensor_MspDeInitCallback         = pCallback;
+6049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+6052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PeriodElapsedCallback                = pCallback;
+6053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+6056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PeriodElapsedHalfCpltCallback        = pCallback;
+6057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_TRIGGER_CB_ID :
+6060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->TriggerCallback                      = pCallback;
+6061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_TRIGGER_HALF_CB_ID :
+6064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->TriggerHalfCpltCallback              = pCallback;
+6065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_CAPTURE_CB_ID :
+6068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_CaptureCallback                   = pCallback;
+6069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+6072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_CaptureHalfCpltCallback           = pCallback;
+6073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+ARM GAS  /tmp/ccPLZXyC.s 			page 108
+
+
+6074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+6076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_DelayElapsedCallback              = pCallback;
+6077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+6080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_PulseFinishedCallback            = pCallback;
+6081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+6084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+6085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ERROR_CB_ID :
+6088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->ErrorCallback                        = pCallback;
+6089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_COMMUTATION_CB_ID :
+6092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->CommutationCallback                  = pCallback;
+6093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_COMMUTATION_HALF_CB_ID :
+6096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->CommutationHalfCpltCallback          = pCallback;
+6097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BREAK_CB_ID :
+6100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->BreakCallback                        = pCallback;
+6101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BREAK2_CB_ID :
+6104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Break2Callback                       = pCallback;
+6105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       default :
+6108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+6109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         status = HAL_ERROR;
+6110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (htim->State == HAL_TIM_STATE_RESET)
+6114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     switch (CallbackID)
+6116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+6117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BASE_MSPINIT_CB_ID :
+6118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Base_MspInitCallback         = pCallback;
+6119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+6122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Base_MspDeInitCallback       = pCallback;
+6123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_MSPINIT_CB_ID :
+6126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_MspInitCallback           = pCallback;
+6127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_MSPDEINIT_CB_ID :
+6130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_MspDeInitCallback         = pCallback;
+ARM GAS  /tmp/ccPLZXyC.s 			page 109
+
+
+6131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_OC_MSPINIT_CB_ID :
+6134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_MspInitCallback           = pCallback;
+6135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_OC_MSPDEINIT_CB_ID :
+6138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_MspDeInitCallback         = pCallback;
+6139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_MSPINIT_CB_ID :
+6142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_MspInitCallback          = pCallback;
+6143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+6146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_MspDeInitCallback        = pCallback;
+6147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+6150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OnePulse_MspInitCallback     = pCallback;
+6151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+6154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OnePulse_MspDeInitCallback   = pCallback;
+6155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+6158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Encoder_MspInitCallback      = pCallback;
+6159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+6162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Encoder_MspDeInitCallback    = pCallback;
+6163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+6166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->HallSensor_MspInitCallback   = pCallback;
+6167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+6170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->HallSensor_MspDeInitCallback = pCallback;
+6171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       default :
+6174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+6175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         status = HAL_ERROR;
+6176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+6180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Return error status */
+6182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     status = HAL_ERROR;
+6183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+6186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 110
+
+
+6188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Unregister a TIM callback
+6190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *         TIM callback is redirected to the weak predefined callback
+6191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param htim tim handle
+6192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param CallbackID ID of the callback to be unregistered
+6193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        This parameter can be one of the following values:
+6194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+6195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+6196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+6197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+6198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+6199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+6200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+6201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+6202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+6203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+6204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+6205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+6206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+6207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+6208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+6209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+6210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+6211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+6212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+6213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+6214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+6215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+6216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callb
+6217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+6218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+6219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+6220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+6222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          @retval status
+6223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Cal
+6225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+6227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->State == HAL_TIM_STATE_READY)
+6229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     switch (CallbackID)
+6231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+6232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BASE_MSPINIT_CB_ID :
+6233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Base MspInit Callback */
+6234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
+6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+6238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Base Msp DeInit Callback */
+6239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
+6240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_MSPINIT_CB_ID :
+6243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak IC Msp Init Callback */
+6244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
+ARM GAS  /tmp/ccPLZXyC.s 			page 111
+
+
+6245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_MSPDEINIT_CB_ID :
+6248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak IC Msp DeInit Callback */
+6249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
+6250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_OC_MSPINIT_CB_ID :
+6253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak OC Msp Init Callback */
+6254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
+6255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_OC_MSPDEINIT_CB_ID :
+6258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak OC Msp DeInit Callback */
+6259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
+6260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_MSPINIT_CB_ID :
+6263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak PWM Msp Init Callback */
+6264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
+6265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+6268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak PWM Msp DeInit Callback */
+6269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
+6270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+6273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak One Pulse Msp Init Callback */
+6274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
+6275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+6278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak One Pulse Msp DeInit Callback */
+6279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
+6280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+6283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Encoder Msp Init Callback */
+6284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
+6285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+6288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Encoder Msp DeInit Callback */
+6289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
+6290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+6293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Hall Sensor Msp Init Callback */
+6294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
+6295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+6298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Hall Sensor Msp DeInit Callback */
+6299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
+6300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 112
+
+
+6302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+6303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Period Elapsed Callback */
+6304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+6305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+6308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Period Elapsed half complete Callback */
+6309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+6310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_TRIGGER_CB_ID :
+6313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Trigger Callback */
+6314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+6315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_TRIGGER_HALF_CB_ID :
+6318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Trigger half complete Callback */
+6319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+6320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_CAPTURE_CB_ID :
+6323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak IC Capture Callback */
+6324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+6325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+6328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak IC Capture half complete Callback */
+6329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+6330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+6333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak OC Delay Elapsed Callback */
+6334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+6335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+6338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak PWM Pulse Finished Callback */
+6339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+6340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+6343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak PWM Pulse Finished half complete Callback */
+6344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+6345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ERROR_CB_ID :
+6348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Error Callback */
+6349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+6350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_COMMUTATION_CB_ID :
+6353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Commutation Callback */
+6354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+6355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_COMMUTATION_HALF_CB_ID :
+6358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Commutation half complete Callback */
+ARM GAS  /tmp/ccPLZXyC.s 			page 113
+
+
+6359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+6360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BREAK_CB_ID :
+6363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Break Callback */
+6364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+6365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BREAK2_CB_ID :
+6368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Break2 Callback */
+6369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
+6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       default :
+6373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+6374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         status = HAL_ERROR;
+6375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (htim->State == HAL_TIM_STATE_RESET)
+6379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     switch (CallbackID)
+6381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+6382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BASE_MSPINIT_CB_ID :
+6383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Base MspInit Callback */
+6384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
+6385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+6388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Base Msp DeInit Callback */
+6389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
+6390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_MSPINIT_CB_ID :
+6393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak IC Msp Init Callback */
+6394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
+6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_IC_MSPDEINIT_CB_ID :
+6398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak IC Msp DeInit Callback */
+6399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
+6400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_OC_MSPINIT_CB_ID :
+6403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak OC Msp Init Callback */
+6404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
+6405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_OC_MSPDEINIT_CB_ID :
+6408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak OC Msp DeInit Callback */
+6409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
+6410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_MSPINIT_CB_ID :
+6413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak PWM Msp Init Callback */
+6414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
+6415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+ARM GAS  /tmp/ccPLZXyC.s 			page 114
+
+
+6416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+6418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak PWM Msp DeInit Callback */
+6419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
+6420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak One Pulse Msp Init Callback */
+6424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
+6425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+6428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak One Pulse Msp DeInit Callback */
+6429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
+6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+6433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Encoder Msp Init Callback */
+6434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
+6435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+6438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Encoder Msp DeInit Callback */
+6439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
+6440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+6443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Hall Sensor Msp Init Callback */
+6444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
+6445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+6448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Legacy weak Hall Sensor Msp DeInit Callback */
+6449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+6450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       default :
+6453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         /* Return error status */
+6454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         status = HAL_ERROR;
+6455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+6456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+6459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Return error status */
+6461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     status = HAL_ERROR;
+6462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+6465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+6470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ARM GAS  /tmp/ccPLZXyC.s 			page 115
+
+
+6473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *  @brief   TIM Peripheral State functions
+6474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *
+6475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim
+6476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+6477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         ##### Peripheral State functions #####
+6478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   ==============================================================================
+6479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     [..]
+6480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     This subsection permits to get in run-time the status of the peripheral
+6481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     and the data flow.
+6482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim
+6484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+6485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Return the TIM Base handle state.
+6489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Base handle
+6490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL state
+6491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
+6493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+6495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Return the TIM OC handle state.
+6499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Output Compare handle
+6500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL state
+6501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
+6503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+6505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Return the TIM PWM handle state.
+6509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+6510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL state
+6511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
+6513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+6515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Return the TIM Input Capture handle state.
+6519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM IC handle
+6520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL state
+6521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
+6523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+6525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Return the TIM One Pulse Mode handle state.
+6529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM OPM handle
+ARM GAS  /tmp/ccPLZXyC.s 			page 116
+
+
+6530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL state
+6531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
+6533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+6535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Return the TIM Encoder Mode handle state.
+6539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM Encoder Interface handle
+6540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval HAL state
+6541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
+6543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+6545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Return the TIM Encoder Mode handle state.
+6549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+6550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval Active channel
+6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
+6553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->Channel;
+6555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Return actual state of the TIM channel.
+6559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+6560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel TIM Channel
+6561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+6562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1
+6563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2
+6564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3
+6565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4
+6566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5
+6567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6
+6568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval TIM Channel state
+6569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channe
+6571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state;
+6573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+6575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+6576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+6578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return channel_state;
+6580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Return actual state of a DMA burst operation.
+6584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+6585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval DMA burst state
+6586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+ARM GAS  /tmp/ccPLZXyC.s 			page 117
+
+
+6587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
+6588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+6590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+6591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->DMABurstState;
+6593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+6597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @}
+6601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Private_Functions TIM Private Functions
+6604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @{
+6605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  TIM DMA error callback
+6609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+6611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_DMAError(DMA_HandleTypeDef *hdma)
+6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+6617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+6619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+6620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+6622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+6624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+6625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+6627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+6629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+6630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+6632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+6634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+6635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+6637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+6639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->ErrorCallback(htim);
+6643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+ARM GAS  /tmp/ccPLZXyC.s 			page 118
+
+
+6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ErrorCallback(htim);
+6645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+6648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  TIM DMA Delay Pulse complete callback.
+6652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+6654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+6656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+6660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+6662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+6666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+6669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+6674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+6675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+6678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+6684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+6687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+6689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+6693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+6696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* nothing to do */
+6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ARM GAS  /tmp/ccPLZXyC.s 			page 119
+
+
+6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->PWM_PulseFinishedCallback(htim);
+6702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+6703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_PWM_PulseFinishedCallback(htim);
+6704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+6707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  TIM DMA Delay Pulse half complete callback.
+6711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+6713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+6715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+6719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+6721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+6723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+6725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+6727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+6729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+6731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+6733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+6735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* nothing to do */
+6737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->PWM_PulseFinishedHalfCpltCallback(htim);
+6741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+6743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+6746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  TIM DMA Capture complete callback.
+6750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+6752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+6754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ARM GAS  /tmp/ccPLZXyC.s 			page 120
+
+
+6758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+6760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+6763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+6764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+6765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+6768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+6770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+6773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+6774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+6775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+6778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+6780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+6783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+6784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+6785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+6788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+6790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+6792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+6793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+6794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+6795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+6796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+6798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* nothing to do */
+6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->IC_CaptureCallback(htim);
+6804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+6805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_IC_CaptureCallback(htim);
+6806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+6809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  TIM DMA Capture half complete callback.
+6813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+ARM GAS  /tmp/ccPLZXyC.s 			page 121
+
+
+6815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+6817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+6821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+6823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+6825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+6827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+6829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+6831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+6833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+6835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+6837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* nothing to do */
+6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->IC_CaptureHalfCpltCallback(htim);
+6843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+6844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+6845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+6848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  TIM DMA Period Elapse complete callback.
+6852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+6854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+6856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
+6860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+6862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->PeriodElapsedCallback(htim);
+6866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+6867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_PeriodElapsedCallback(htim);
+6868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ARM GAS  /tmp/ccPLZXyC.s 			page 122
+
+
+6872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  TIM DMA Period Elapse half complete callback.
+6873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+6875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->PeriodElapsedHalfCpltCallback(htim);
+6882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+6884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  TIM DMA Trigger callback.
+6889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+6891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+6893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
+6897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     htim->State = HAL_TIM_STATE_READY;
+6899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->TriggerCallback(htim);
+6903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+6904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_TriggerCallback(htim);
+6905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  TIM DMA Trigger half complete callback.
+6910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  hdma pointer to DMA handle.
+6911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+6912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+6914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+6916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+6918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->TriggerHalfCpltCallback(htim);
+6919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else
+6920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_TriggerHalfCpltCallback(htim);
+6921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+6922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Time Base configuration
+6926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx TIM peripheral
+6927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Structure TIM Base configuration structure
+6928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+ARM GAS  /tmp/ccPLZXyC.s 			page 123
+
+
+6929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
+6931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+6932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr1;
+6933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpcr1 = TIMx->CR1;
+6934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set TIM Time Base Unit parameters ---------------------------------------*/
+6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+6937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Select the Counter Mode */
+6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+6940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr1 |= Structure->CounterMode;
+6941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+6944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the clock division */
+6946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr1 &= ~TIM_CR1_CKD;
+6947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr1 |= (uint32_t)Structure->ClockDivision;
+6948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the auto-reload preload */
+6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+6952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CR1 = tmpcr1;
+6954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Autoreload value */
+6956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->ARR = (uint32_t)Structure->Period ;
+6957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Prescaler value */
+6959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->PSC = Structure->Prescaler;
+6960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+6962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Repetition Counter value */
+6964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIMx->RCR = Structure->RepetitionCounter;
+6965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Generate an update event to reload the Prescaler
+6968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****      and the repetition counter (only for advanced timer) value immediately */
+6969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->EGR = TIM_EGR_UG;
+6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+6972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+6973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+6974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Clear the update flag */
+6975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+6976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+6977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+6978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+6980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Timer Output Compare 1 configuration
+6981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+6982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+6983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+6984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+6985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+ARM GAS  /tmp/ccPLZXyC.s 			page 124
+
+
+6986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+  28              		.loc 1 6986 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  33              		.loc 1 6986 1 is_stmt 0 view .LVU1
+  34 0000 70B4     		push	{r4, r5, r6}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 12
+  37              		.cfi_offset 4, -12
+  38              		.cfi_offset 5, -8
+  39              		.cfi_offset 6, -4
+6987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmrx;
+  40              		.loc 1 6987 3 is_stmt 1 view .LVU2
+6988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+  41              		.loc 1 6988 3 view .LVU3
+6989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr2;
+  42              		.loc 1 6989 3 view .LVU4
+6990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+6992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+  43              		.loc 1 6992 3 view .LVU5
+  44              		.loc 1 6992 11 is_stmt 0 view .LVU6
+  45 0002 036A     		ldr	r3, [r0, #32]
+  46              	.LVL1:
+6993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Channel 1: Reset the CC1E Bit */
+6995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC1E;
+  47              		.loc 1 6995 3 is_stmt 1 view .LVU7
+  48              		.loc 1 6995 14 is_stmt 0 view .LVU8
+  49 0004 026A     		ldr	r2, [r0, #32]
+  50 0006 22F00102 		bic	r2, r2, #1
+  51 000a 0262     		str	r2, [r0, #32]
+6996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+6997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+6998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+  52              		.loc 1 6998 3 is_stmt 1 view .LVU9
+  53              		.loc 1 6998 10 is_stmt 0 view .LVU10
+  54 000c 4268     		ldr	r2, [r0, #4]
+  55              	.LVL2:
+6999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCMR1 register value */
+7001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR1;
+  56              		.loc 1 7001 3 is_stmt 1 view .LVU11
+  57              		.loc 1 7001 12 is_stmt 0 view .LVU12
+  58 000e 8569     		ldr	r5, [r0, #24]
+  59              	.LVL3:
+7002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Compare Mode Bits */
+7004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR1_OC1M;
+  60              		.loc 1 7004 3 is_stmt 1 view .LVU13
+7005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR1_CC1S;
+  61              		.loc 1 7005 3 view .LVU14
+  62              		.loc 1 7005 12 is_stmt 0 view .LVU15
+  63 0010 124C     		ldr	r4, .L5
+  64 0012 2C40     		ands	r4, r4, r5
+ARM GAS  /tmp/ccPLZXyC.s 			page 125
+
+
+  65              	.LVL4:
+7006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx |= OC_Config->OCMode;
+  66              		.loc 1 7007 3 is_stmt 1 view .LVU16
+  67              		.loc 1 7007 24 is_stmt 0 view .LVU17
+  68 0014 0D68     		ldr	r5, [r1]
+  69              		.loc 1 7007 12 view .LVU18
+  70 0016 2543     		orrs	r5, r5, r4
+  71              	.LVL5:
+7008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~TIM_CCER_CC1P;
+  72              		.loc 1 7010 3 is_stmt 1 view .LVU19
+  73              		.loc 1 7010 11 is_stmt 0 view .LVU20
+  74 0018 23F00204 		bic	r4, r3, #2
+  75              	.LVL6:
+7011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+7012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= OC_Config->OCPolarity;
+  76              		.loc 1 7012 3 is_stmt 1 view .LVU21
+  77              		.loc 1 7012 23 is_stmt 0 view .LVU22
+  78 001c 8B68     		ldr	r3, [r1, #8]
+  79              		.loc 1 7012 11 view .LVU23
+  80 001e 2343     		orrs	r3, r3, r4
+  81              	.LVL7:
+7013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  82              		.loc 1 7014 3 is_stmt 1 view .LVU24
+  83              		.loc 1 7014 7 is_stmt 0 view .LVU25
+  84 0020 0F4C     		ldr	r4, .L5+4
+  85 0022 104E     		ldr	r6, .L5+8
+  86              		.loc 1 7014 6 view .LVU26
+  87 0024 B042     		cmp	r0, r6
+  88 0026 18BF     		it	ne
+  89 0028 A042     		cmpne	r0, r4
+  90 002a 0CBF     		ite	eq
+  91 002c 0124     		moveq	r4, #1
+  92 002e 0024     		movne	r4, #0
+  93 0030 05D1     		bne	.L2
+7015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Check parameters */
+7017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+  94              		.loc 1 7017 5 is_stmt 1 view .LVU27
+7018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output N Polarity level */
+7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC1NP;
+  95              		.loc 1 7020 5 view .LVU28
+  96              		.loc 1 7020 13 is_stmt 0 view .LVU29
+  97 0032 23F00803 		bic	r3, r3, #8
+  98              	.LVL8:
+7021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output N Polarity */
+7022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccer |= OC_Config->OCNPolarity;
+  99              		.loc 1 7022 5 is_stmt 1 view .LVU30
+ 100              		.loc 1 7022 25 is_stmt 0 view .LVU31
+ 101 0036 CE68     		ldr	r6, [r1, #12]
+ 102              		.loc 1 7022 13 view .LVU32
+ 103 0038 3343     		orrs	r3, r3, r6
+ 104              	.LVL9:
+ARM GAS  /tmp/ccPLZXyC.s 			page 126
+
+
+7023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output N State */
+7024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC1NE;
+ 105              		.loc 1 7024 5 is_stmt 1 view .LVU33
+ 106              		.loc 1 7024 13 is_stmt 0 view .LVU34
+ 107 003a 23F00403 		bic	r3, r3, #4
+ 108              	.LVL10:
+ 109              	.L2:
+7025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 110              		.loc 1 7027 3 is_stmt 1 view .LVU35
+ 111              		.loc 1 7027 6 is_stmt 0 view .LVU36
+ 112 003e 2CB1     		cbz	r4, .L3
+7028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Check parameters */
+7030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ 113              		.loc 1 7030 5 is_stmt 1 view .LVU37
+7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+ 114              		.loc 1 7031 5 view .LVU38
+7032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output Compare and Output Compare N IDLE State */
+7034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS1;
+ 115              		.loc 1 7034 5 view .LVU39
+ 116              	.LVL11:
+7035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS1N;
+ 117              		.loc 1 7035 5 view .LVU40
+ 118              		.loc 1 7035 12 is_stmt 0 view .LVU41
+ 119 0040 22F44072 		bic	r2, r2, #768
+ 120              	.LVL12:
+7036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output Idle state */
+7037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 |= OC_Config->OCIdleState;
+ 121              		.loc 1 7037 5 is_stmt 1 view .LVU42
+ 122              		.loc 1 7037 24 is_stmt 0 view .LVU43
+ 123 0044 4C69     		ldr	r4, [r1, #20]
+ 124              		.loc 1 7037 12 view .LVU44
+ 125 0046 1443     		orrs	r4, r4, r2
+ 126              	.LVL13:
+7038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output N Idle state */
+7039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 |= OC_Config->OCNIdleState;
+ 127              		.loc 1 7039 5 is_stmt 1 view .LVU45
+ 128              		.loc 1 7039 24 is_stmt 0 view .LVU46
+ 129 0048 8A69     		ldr	r2, [r1, #24]
+ 130              		.loc 1 7039 12 view .LVU47
+ 131 004a 2243     		orrs	r2, r2, r4
+ 132              	.LVL14:
+ 133              	.L3:
+7040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+ 134              		.loc 1 7043 3 is_stmt 1 view .LVU48
+ 135              		.loc 1 7043 13 is_stmt 0 view .LVU49
+ 136 004c 4260     		str	r2, [r0, #4]
+7044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR1 */
+7046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmrx;
+ 137              		.loc 1 7046 3 is_stmt 1 view .LVU50
+ARM GAS  /tmp/ccPLZXyC.s 			page 127
+
+
+ 138              		.loc 1 7046 15 is_stmt 0 view .LVU51
+ 139 004e 8561     		str	r5, [r0, #24]
+7047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCR1 = OC_Config->Pulse;
+ 140              		.loc 1 7049 3 is_stmt 1 view .LVU52
+ 141              		.loc 1 7049 25 is_stmt 0 view .LVU53
+ 142 0050 4A68     		ldr	r2, [r1, #4]
+ 143              	.LVL15:
+ 144              		.loc 1 7049 14 view .LVU54
+ 145 0052 4263     		str	r2, [r0, #52]
+7050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCER */
+7052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 146              		.loc 1 7052 3 is_stmt 1 view .LVU55
+ 147              		.loc 1 7052 14 is_stmt 0 view .LVU56
+ 148 0054 0362     		str	r3, [r0, #32]
+7053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 149              		.loc 1 7053 1 view .LVU57
+ 150 0056 70BC     		pop	{r4, r5, r6}
+ 151              	.LCFI1:
+ 152              		.cfi_restore 6
+ 153              		.cfi_restore 5
+ 154              		.cfi_restore 4
+ 155              		.cfi_def_cfa_offset 0
+ 156              	.LVL16:
+ 157              		.loc 1 7053 1 view .LVU58
+ 158 0058 7047     		bx	lr
+ 159              	.L6:
+ 160 005a 00BF     		.align	2
+ 161              	.L5:
+ 162 005c 8CFFFEFF 		.word	-65652
+ 163 0060 00000140 		.word	1073807360
+ 164 0064 00040140 		.word	1073808384
+ 165              		.cfi_endproc
+ 166              	.LFE246:
+ 168              		.section	.text.TIM_OC3_SetConfig,"ax",%progbits
+ 169              		.align	1
+ 170              		.syntax unified
+ 171              		.thumb
+ 172              		.thumb_func
+ 173              		.fpu fpv5-d16
+ 175              	TIM_OC3_SetConfig:
+ 176              	.LVL17:
+ 177              	.LFB248:
+7054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Timer Output Compare 2 configuration
+7057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+7059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+7062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmrx;
+7064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+7065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr2;
+ARM GAS  /tmp/ccPLZXyC.s 			page 128
+
+
+7066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+7068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+7069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Channel 2: Reset the CC2E Bit */
+7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC2E;
+7072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+7074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+7075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCMR1 register value */
+7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR1;
+7078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Compare mode and Capture/Compare selection Bits */
+7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR1_OC2M;
+7081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR1_CC2S;
+7082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx |= (OC_Config->OCMode << 8U);
+7085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~TIM_CCER_CC2P;
+7088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+7089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= (OC_Config->OCPolarity << 4U);
+7090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+7092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+7094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output N Polarity level */
+7096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC2NP;
+7097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output N Polarity */
+7098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccer |= (OC_Config->OCNPolarity << 4U);
+7099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output N State */
+7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC2NE;
+7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+7104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Check parameters */
+7106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+7107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+7108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output Compare and Output Compare N IDLE State */
+7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS2;
+7111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS2N;
+7112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output Idle state */
+7113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCIdleState << 2U);
+7114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output N Idle state */
+7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+7116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+7120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR1 */
+7122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmrx;
+ARM GAS  /tmp/ccPLZXyC.s 			page 129
+
+
+7123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCR2 = OC_Config->Pulse;
+7126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCER */
+7128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+7129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+7130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Timer Output Compare 3 configuration
+7133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+7135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+7138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 178              		.loc 1 7138 1 is_stmt 1 view -0
+ 179              		.cfi_startproc
+ 180              		@ args = 0, pretend = 0, frame = 0
+ 181              		@ frame_needed = 0, uses_anonymous_args = 0
+ 182              		@ link register save eliminated.
+ 183              		.loc 1 7138 1 is_stmt 0 view .LVU60
+ 184 0000 70B4     		push	{r4, r5, r6}
+ 185              	.LCFI2:
+ 186              		.cfi_def_cfa_offset 12
+ 187              		.cfi_offset 4, -12
+ 188              		.cfi_offset 5, -8
+ 189              		.cfi_offset 6, -4
+7139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 190              		.loc 1 7139 3 is_stmt 1 view .LVU61
+7140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 191              		.loc 1 7140 3 view .LVU62
+7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr2;
+ 192              		.loc 1 7141 3 view .LVU63
+7142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+7144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 193              		.loc 1 7144 3 view .LVU64
+ 194              		.loc 1 7144 11 is_stmt 0 view .LVU65
+ 195 0002 036A     		ldr	r3, [r0, #32]
+ 196              	.LVL18:
+7145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Channel 3: Reset the CC2E Bit */
+7147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC3E;
+ 197              		.loc 1 7147 3 is_stmt 1 view .LVU66
+ 198              		.loc 1 7147 14 is_stmt 0 view .LVU67
+ 199 0004 026A     		ldr	r2, [r0, #32]
+ 200 0006 22F48072 		bic	r2, r2, #256
+ 201 000a 0262     		str	r2, [r0, #32]
+7148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+ 202              		.loc 1 7150 3 is_stmt 1 view .LVU68
+ 203              		.loc 1 7150 10 is_stmt 0 view .LVU69
+ 204 000c 4268     		ldr	r2, [r0, #4]
+ 205              	.LVL19:
+7151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 130
+
+
+7152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCMR2 register value */
+7153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR2;
+ 206              		.loc 1 7153 3 is_stmt 1 view .LVU70
+ 207              		.loc 1 7153 12 is_stmt 0 view .LVU71
+ 208 000e C569     		ldr	r5, [r0, #28]
+ 209              	.LVL20:
+7154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Compare mode and Capture/Compare selection Bits */
+7156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR2_OC3M;
+ 210              		.loc 1 7156 3 is_stmt 1 view .LVU72
+7157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR2_CC3S;
+ 211              		.loc 1 7157 3 view .LVU73
+ 212              		.loc 1 7157 12 is_stmt 0 view .LVU74
+ 213 0010 144C     		ldr	r4, .L11
+ 214 0012 2C40     		ands	r4, r4, r5
+ 215              	.LVL21:
+7158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx |= OC_Config->OCMode;
+ 216              		.loc 1 7159 3 is_stmt 1 view .LVU75
+ 217              		.loc 1 7159 24 is_stmt 0 view .LVU76
+ 218 0014 0E68     		ldr	r6, [r1]
+ 219              		.loc 1 7159 12 view .LVU77
+ 220 0016 2643     		orrs	r6, r6, r4
+ 221              	.LVL22:
+7160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~TIM_CCER_CC3P;
+ 222              		.loc 1 7162 3 is_stmt 1 view .LVU78
+ 223              		.loc 1 7162 11 is_stmt 0 view .LVU79
+ 224 0018 23F40073 		bic	r3, r3, #512
+ 225              	.LVL23:
+7163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+7164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= (OC_Config->OCPolarity << 8U);
+ 226              		.loc 1 7164 3 is_stmt 1 view .LVU80
+ 227              		.loc 1 7164 24 is_stmt 0 view .LVU81
+ 228 001c 8C68     		ldr	r4, [r1, #8]
+ 229              		.loc 1 7164 11 view .LVU82
+ 230 001e 43EA0423 		orr	r3, r3, r4, lsl #8
+ 231              	.LVL24:
+7165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+ 232              		.loc 1 7166 3 is_stmt 1 view .LVU83
+ 233              		.loc 1 7166 7 is_stmt 0 view .LVU84
+ 234 0022 114C     		ldr	r4, .L11+4
+ 235 0024 114D     		ldr	r5, .L11+8
+ 236              		.loc 1 7166 6 view .LVU85
+ 237 0026 A842     		cmp	r0, r5
+ 238 0028 18BF     		it	ne
+ 239 002a A042     		cmpne	r0, r4
+ 240 002c 0CBF     		ite	eq
+ 241 002e 0124     		moveq	r4, #1
+ 242 0030 0024     		movne	r4, #0
+ 243 0032 06D1     		bne	.L8
+7167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+ 244              		.loc 1 7168 5 is_stmt 1 view .LVU86
+7169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 131
+
+
+7170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output N Polarity level */
+7171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC3NP;
+ 245              		.loc 1 7171 5 view .LVU87
+ 246              		.loc 1 7171 13 is_stmt 0 view .LVU88
+ 247 0034 23F40063 		bic	r3, r3, #2048
+ 248              	.LVL25:
+7172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output N Polarity */
+7173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccer |= (OC_Config->OCNPolarity << 8U);
+ 249              		.loc 1 7173 5 is_stmt 1 view .LVU89
+ 250              		.loc 1 7173 26 is_stmt 0 view .LVU90
+ 251 0038 CD68     		ldr	r5, [r1, #12]
+ 252              		.loc 1 7173 13 view .LVU91
+ 253 003a 43EA0523 		orr	r3, r3, r5, lsl #8
+ 254              	.LVL26:
+7174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output N State */
+7175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccer &= ~TIM_CCER_CC3NE;
+ 255              		.loc 1 7175 5 is_stmt 1 view .LVU92
+ 256              		.loc 1 7175 13 is_stmt 0 view .LVU93
+ 257 003e 23F48063 		bic	r3, r3, #1024
+ 258              	.LVL27:
+ 259              	.L8:
+7176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 260              		.loc 1 7178 3 is_stmt 1 view .LVU94
+ 261              		.loc 1 7178 6 is_stmt 0 view .LVU95
+ 262 0042 3CB1     		cbz	r4, .L9
+7179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Check parameters */
+7181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ 263              		.loc 1 7181 5 is_stmt 1 view .LVU96
+7182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+ 264              		.loc 1 7182 5 view .LVU97
+7183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output Compare and Output Compare N IDLE State */
+7185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS3;
+ 265              		.loc 1 7185 5 view .LVU98
+ 266              	.LVL28:
+7186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS3N;
+ 267              		.loc 1 7186 5 view .LVU99
+ 268              		.loc 1 7186 12 is_stmt 0 view .LVU100
+ 269 0044 22F44052 		bic	r2, r2, #12288
+ 270              	.LVL29:
+7187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output Idle state */
+7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCIdleState << 4U);
+ 271              		.loc 1 7188 5 is_stmt 1 view .LVU101
+ 272              		.loc 1 7188 25 is_stmt 0 view .LVU102
+ 273 0048 4C69     		ldr	r4, [r1, #20]
+ 274              		.loc 1 7188 12 view .LVU103
+ 275 004a 42EA0412 		orr	r2, r2, r4, lsl #4
+ 276              	.LVL30:
+7189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output N Idle state */
+7190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+ 277              		.loc 1 7190 5 is_stmt 1 view .LVU104
+ 278              		.loc 1 7190 25 is_stmt 0 view .LVU105
+ 279 004e 8C69     		ldr	r4, [r1, #24]
+ 280              		.loc 1 7190 12 view .LVU106
+ARM GAS  /tmp/ccPLZXyC.s 			page 132
+
+
+ 281 0050 42EA0412 		orr	r2, r2, r4, lsl #4
+ 282              	.LVL31:
+ 283              	.L9:
+7191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+ 284              		.loc 1 7194 3 is_stmt 1 view .LVU107
+ 285              		.loc 1 7194 13 is_stmt 0 view .LVU108
+ 286 0054 4260     		str	r2, [r0, #4]
+7195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR2 */
+7197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR2 = tmpccmrx;
+ 287              		.loc 1 7197 3 is_stmt 1 view .LVU109
+ 288              		.loc 1 7197 15 is_stmt 0 view .LVU110
+ 289 0056 C661     		str	r6, [r0, #28]
+7198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCR3 = OC_Config->Pulse;
+ 290              		.loc 1 7200 3 is_stmt 1 view .LVU111
+ 291              		.loc 1 7200 25 is_stmt 0 view .LVU112
+ 292 0058 4A68     		ldr	r2, [r1, #4]
+ 293              	.LVL32:
+ 294              		.loc 1 7200 14 view .LVU113
+ 295 005a C263     		str	r2, [r0, #60]
+7201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCER */
+7203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 296              		.loc 1 7203 3 is_stmt 1 view .LVU114
+ 297              		.loc 1 7203 14 is_stmt 0 view .LVU115
+ 298 005c 0362     		str	r3, [r0, #32]
+7204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 299              		.loc 1 7204 1 view .LVU116
+ 300 005e 70BC     		pop	{r4, r5, r6}
+ 301              	.LCFI3:
+ 302              		.cfi_restore 6
+ 303              		.cfi_restore 5
+ 304              		.cfi_restore 4
+ 305              		.cfi_def_cfa_offset 0
+ 306              	.LVL33:
+ 307              		.loc 1 7204 1 view .LVU117
+ 308 0060 7047     		bx	lr
+ 309              	.L12:
+ 310 0062 00BF     		.align	2
+ 311              	.L11:
+ 312 0064 8CFFFEFF 		.word	-65652
+ 313 0068 00000140 		.word	1073807360
+ 314 006c 00040140 		.word	1073808384
+ 315              		.cfi_endproc
+ 316              	.LFE248:
+ 318              		.section	.text.TIM_OC4_SetConfig,"ax",%progbits
+ 319              		.align	1
+ 320              		.syntax unified
+ 321              		.thumb
+ 322              		.thumb_func
+ 323              		.fpu fpv5-d16
+ 325              	TIM_OC4_SetConfig:
+ARM GAS  /tmp/ccPLZXyC.s 			page 133
+
+
+ 326              	.LVL34:
+ 327              	.LFB249:
+7205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Timer Output Compare 4 configuration
+7208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+7210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+7213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 328              		.loc 1 7213 1 is_stmt 1 view -0
+ 329              		.cfi_startproc
+ 330              		@ args = 0, pretend = 0, frame = 0
+ 331              		@ frame_needed = 0, uses_anonymous_args = 0
+ 332              		@ link register save eliminated.
+ 333              		.loc 1 7213 1 is_stmt 0 view .LVU119
+ 334 0000 70B4     		push	{r4, r5, r6}
+ 335              	.LCFI4:
+ 336              		.cfi_def_cfa_offset 12
+ 337              		.cfi_offset 4, -12
+ 338              		.cfi_offset 5, -8
+ 339              		.cfi_offset 6, -4
+7214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 340              		.loc 1 7214 3 is_stmt 1 view .LVU120
+7215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 341              		.loc 1 7215 3 view .LVU121
+7216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr2;
+ 342              		.loc 1 7216 3 view .LVU122
+7217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+7219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 343              		.loc 1 7219 3 view .LVU123
+ 344              		.loc 1 7219 11 is_stmt 0 view .LVU124
+ 345 0002 036A     		ldr	r3, [r0, #32]
+ 346              	.LVL35:
+7220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Channel 4: Reset the CC4E Bit */
+7222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC4E;
+ 347              		.loc 1 7222 3 is_stmt 1 view .LVU125
+ 348              		.loc 1 7222 14 is_stmt 0 view .LVU126
+ 349 0004 026A     		ldr	r2, [r0, #32]
+ 350 0006 22F48052 		bic	r2, r2, #4096
+ 351 000a 0262     		str	r2, [r0, #32]
+7223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+7225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+ 352              		.loc 1 7225 3 is_stmt 1 view .LVU127
+ 353              		.loc 1 7225 10 is_stmt 0 view .LVU128
+ 354 000c 4468     		ldr	r4, [r0, #4]
+ 355              	.LVL36:
+7226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCMR2 register value */
+7228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR2;
+ 356              		.loc 1 7228 3 is_stmt 1 view .LVU129
+ 357              		.loc 1 7228 12 is_stmt 0 view .LVU130
+ 358 000e C569     		ldr	r5, [r0, #28]
+ARM GAS  /tmp/ccPLZXyC.s 			page 134
+
+
+ 359              	.LVL37:
+7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Compare mode and Capture/Compare selection Bits */
+7231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR2_OC4M;
+ 360              		.loc 1 7231 3 is_stmt 1 view .LVU131
+7232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR2_CC4S;
+ 361              		.loc 1 7232 3 view .LVU132
+ 362              		.loc 1 7232 12 is_stmt 0 view .LVU133
+ 363 0010 0D4A     		ldr	r2, .L16
+ 364 0012 2A40     		ands	r2, r2, r5
+ 365              	.LVL38:
+7233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx |= (OC_Config->OCMode << 8U);
+ 366              		.loc 1 7235 3 is_stmt 1 view .LVU134
+ 367              		.loc 1 7235 25 is_stmt 0 view .LVU135
+ 368 0014 0D68     		ldr	r5, [r1]
+ 369              		.loc 1 7235 12 view .LVU136
+ 370 0016 42EA0522 		orr	r2, r2, r5, lsl #8
+ 371              	.LVL39:
+7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~TIM_CCER_CC4P;
+ 372              		.loc 1 7238 3 is_stmt 1 view .LVU137
+ 373              		.loc 1 7238 11 is_stmt 0 view .LVU138
+ 374 001a 23F40053 		bic	r3, r3, #8192
+ 375              	.LVL40:
+7239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+7240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= (OC_Config->OCPolarity << 12U);
+ 376              		.loc 1 7240 3 is_stmt 1 view .LVU139
+ 377              		.loc 1 7240 24 is_stmt 0 view .LVU140
+ 378 001e 8D68     		ldr	r5, [r1, #8]
+ 379              		.loc 1 7240 11 view .LVU141
+ 380 0020 43EA0533 		orr	r3, r3, r5, lsl #12
+ 381              	.LVL41:
+7241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 382              		.loc 1 7242 3 is_stmt 1 view .LVU142
+ 383              		.loc 1 7242 6 is_stmt 0 view .LVU143
+ 384 0024 094E     		ldr	r6, .L16+4
+ 385 0026 0A4D     		ldr	r5, .L16+8
+ 386 0028 A842     		cmp	r0, r5
+ 387 002a 18BF     		it	ne
+ 388 002c B042     		cmpne	r0, r6
+ 389 002e 04D1     		bne	.L14
+7243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Check parameters */
+7245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+ 390              		.loc 1 7245 5 is_stmt 1 view .LVU144
+7246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output Compare IDLE State */
+7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS4;
+ 391              		.loc 1 7248 5 view .LVU145
+ 392              		.loc 1 7248 12 is_stmt 0 view .LVU146
+ 393 0030 24F48044 		bic	r4, r4, #16384
+ 394              	.LVL42:
+7249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 135
+
+
+7250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output Idle state */
+7251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCIdleState << 6U);
+ 395              		.loc 1 7251 5 is_stmt 1 view .LVU147
+ 396              		.loc 1 7251 25 is_stmt 0 view .LVU148
+ 397 0034 4D69     		ldr	r5, [r1, #20]
+ 398              		.loc 1 7251 12 view .LVU149
+ 399 0036 44EA8514 		orr	r4, r4, r5, lsl #6
+ 400              	.LVL43:
+ 401              	.L14:
+7252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+ 402              		.loc 1 7255 3 is_stmt 1 view .LVU150
+ 403              		.loc 1 7255 13 is_stmt 0 view .LVU151
+ 404 003a 4460     		str	r4, [r0, #4]
+7256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR2 */
+7258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR2 = tmpccmrx;
+ 405              		.loc 1 7258 3 is_stmt 1 view .LVU152
+ 406              		.loc 1 7258 15 is_stmt 0 view .LVU153
+ 407 003c C261     		str	r2, [r0, #28]
+7259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCR4 = OC_Config->Pulse;
+ 408              		.loc 1 7261 3 is_stmt 1 view .LVU154
+ 409              		.loc 1 7261 25 is_stmt 0 view .LVU155
+ 410 003e 4A68     		ldr	r2, [r1, #4]
+ 411              	.LVL44:
+ 412              		.loc 1 7261 14 view .LVU156
+ 413 0040 0264     		str	r2, [r0, #64]
+ 414              	.LVL45:
+7262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCER */
+7264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 415              		.loc 1 7264 3 is_stmt 1 view .LVU157
+ 416              		.loc 1 7264 14 is_stmt 0 view .LVU158
+ 417 0042 0362     		str	r3, [r0, #32]
+7265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 418              		.loc 1 7265 1 view .LVU159
+ 419 0044 70BC     		pop	{r4, r5, r6}
+ 420              	.LCFI5:
+ 421              		.cfi_restore 6
+ 422              		.cfi_restore 5
+ 423              		.cfi_restore 4
+ 424              		.cfi_def_cfa_offset 0
+ 425              	.LVL46:
+ 426              		.loc 1 7265 1 view .LVU160
+ 427 0046 7047     		bx	lr
+ 428              	.L17:
+ 429              		.align	2
+ 430              	.L16:
+ 431 0048 FF8CFFFE 		.word	-16806657
+ 432 004c 00000140 		.word	1073807360
+ 433 0050 00040140 		.word	1073808384
+ 434              		.cfi_endproc
+ 435              	.LFE249:
+ARM GAS  /tmp/ccPLZXyC.s 			page 136
+
+
+ 437              		.section	.text.TIM_OC5_SetConfig,"ax",%progbits
+ 438              		.align	1
+ 439              		.syntax unified
+ 440              		.thumb
+ 441              		.thumb_func
+ 442              		.fpu fpv5-d16
+ 444              	TIM_OC5_SetConfig:
+ 445              	.LVL47:
+ 446              	.LFB250:
+7266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Timer Output Compare 5 configuration
+7269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+7271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+7274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                               const TIM_OC_InitTypeDef *OC_Config)
+7275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 447              		.loc 1 7275 1 is_stmt 1 view -0
+ 448              		.cfi_startproc
+ 449              		@ args = 0, pretend = 0, frame = 0
+ 450              		@ frame_needed = 0, uses_anonymous_args = 0
+ 451              		@ link register save eliminated.
+ 452              		.loc 1 7275 1 is_stmt 0 view .LVU162
+ 453 0000 70B4     		push	{r4, r5, r6}
+ 454              	.LCFI6:
+ 455              		.cfi_def_cfa_offset 12
+ 456              		.cfi_offset 4, -12
+ 457              		.cfi_offset 5, -8
+ 458              		.cfi_offset 6, -4
+7276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 459              		.loc 1 7276 3 is_stmt 1 view .LVU163
+7277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 460              		.loc 1 7277 3 view .LVU164
+7278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr2;
+ 461              		.loc 1 7278 3 view .LVU165
+7279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+7281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 462              		.loc 1 7281 3 view .LVU166
+ 463              		.loc 1 7281 11 is_stmt 0 view .LVU167
+ 464 0002 036A     		ldr	r3, [r0, #32]
+ 465              	.LVL48:
+7282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the output: Reset the CCxE Bit */
+7284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC5E;
+ 466              		.loc 1 7284 3 is_stmt 1 view .LVU168
+ 467              		.loc 1 7284 14 is_stmt 0 view .LVU169
+ 468 0004 026A     		ldr	r2, [r0, #32]
+ 469 0006 22F48032 		bic	r2, r2, #65536
+ 470 000a 0262     		str	r2, [r0, #32]
+7285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+7287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+ 471              		.loc 1 7287 3 is_stmt 1 view .LVU170
+ 472              		.loc 1 7287 10 is_stmt 0 view .LVU171
+ARM GAS  /tmp/ccPLZXyC.s 			page 137
+
+
+ 473 000c 4468     		ldr	r4, [r0, #4]
+ 474              	.LVL49:
+7288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCMR1 register value */
+7289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR3;
+ 475              		.loc 1 7289 3 is_stmt 1 view .LVU172
+ 476              		.loc 1 7289 12 is_stmt 0 view .LVU173
+ 477 000e 426D     		ldr	r2, [r0, #84]
+ 478              	.LVL50:
+7290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Compare Mode Bits */
+7292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx &= ~(TIM_CCMR3_OC5M);
+ 479              		.loc 1 7292 3 is_stmt 1 view .LVU174
+ 480              		.loc 1 7292 12 is_stmt 0 view .LVU175
+ 481 0010 0D4D     		ldr	r5, .L21
+ 482 0012 1540     		ands	r5, r5, r2
+ 483              	.LVL51:
+7293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx |= OC_Config->OCMode;
+ 484              		.loc 1 7294 3 is_stmt 1 view .LVU176
+ 485              		.loc 1 7294 24 is_stmt 0 view .LVU177
+ 486 0014 0A68     		ldr	r2, [r1]
+ 487              		.loc 1 7294 12 view .LVU178
+ 488 0016 2A43     		orrs	r2, r2, r5
+ 489              	.LVL52:
+7295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~TIM_CCER_CC5P;
+ 490              		.loc 1 7297 3 is_stmt 1 view .LVU179
+ 491              		.loc 1 7297 11 is_stmt 0 view .LVU180
+ 492 0018 23F40033 		bic	r3, r3, #131072
+ 493              	.LVL53:
+7298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+7299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= (OC_Config->OCPolarity << 16U);
+ 494              		.loc 1 7299 3 is_stmt 1 view .LVU181
+ 495              		.loc 1 7299 24 is_stmt 0 view .LVU182
+ 496 001c 8D68     		ldr	r5, [r1, #8]
+ 497              		.loc 1 7299 11 view .LVU183
+ 498 001e 43EA0543 		orr	r3, r3, r5, lsl #16
+ 499              	.LVL54:
+7300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 500              		.loc 1 7301 3 is_stmt 1 view .LVU184
+ 501              		.loc 1 7301 6 is_stmt 0 view .LVU185
+ 502 0022 0A4E     		ldr	r6, .L21+4
+ 503 0024 0A4D     		ldr	r5, .L21+8
+ 504 0026 A842     		cmp	r0, r5
+ 505 0028 18BF     		it	ne
+ 506 002a B042     		cmpne	r0, r6
+ 507 002c 04D1     		bne	.L19
+7302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output Compare IDLE State */
+7304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS5;
+ 508              		.loc 1 7304 5 is_stmt 1 view .LVU186
+ 509              		.loc 1 7304 12 is_stmt 0 view .LVU187
+ 510 002e 24F48034 		bic	r4, r4, #65536
+ 511              	.LVL55:
+7305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output Idle state */
+ARM GAS  /tmp/ccPLZXyC.s 			page 138
+
+
+7306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCIdleState << 8U);
+ 512              		.loc 1 7306 5 is_stmt 1 view .LVU188
+ 513              		.loc 1 7306 25 is_stmt 0 view .LVU189
+ 514 0032 4D69     		ldr	r5, [r1, #20]
+ 515              		.loc 1 7306 12 view .LVU190
+ 516 0034 44EA0524 		orr	r4, r4, r5, lsl #8
+ 517              	.LVL56:
+ 518              	.L19:
+7307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+ 519              		.loc 1 7309 3 is_stmt 1 view .LVU191
+ 520              		.loc 1 7309 13 is_stmt 0 view .LVU192
+ 521 0038 4460     		str	r4, [r0, #4]
+7310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR3 */
+7312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR3 = tmpccmrx;
+ 522              		.loc 1 7312 3 is_stmt 1 view .LVU193
+ 523              		.loc 1 7312 15 is_stmt 0 view .LVU194
+ 524 003a 4265     		str	r2, [r0, #84]
+7313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCR5 = OC_Config->Pulse;
+ 525              		.loc 1 7315 3 is_stmt 1 view .LVU195
+ 526              		.loc 1 7315 25 is_stmt 0 view .LVU196
+ 527 003c 4A68     		ldr	r2, [r1, #4]
+ 528              	.LVL57:
+ 529              		.loc 1 7315 14 view .LVU197
+ 530 003e 8265     		str	r2, [r0, #88]
+ 531              	.LVL58:
+7316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCER */
+7318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 532              		.loc 1 7318 3 is_stmt 1 view .LVU198
+ 533              		.loc 1 7318 14 is_stmt 0 view .LVU199
+ 534 0040 0362     		str	r3, [r0, #32]
+7319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 535              		.loc 1 7319 1 view .LVU200
+ 536 0042 70BC     		pop	{r4, r5, r6}
+ 537              	.LCFI7:
+ 538              		.cfi_restore 6
+ 539              		.cfi_restore 5
+ 540              		.cfi_restore 4
+ 541              		.cfi_def_cfa_offset 0
+ 542              	.LVL59:
+ 543              		.loc 1 7319 1 view .LVU201
+ 544 0044 7047     		bx	lr
+ 545              	.L22:
+ 546 0046 00BF     		.align	2
+ 547              	.L21:
+ 548 0048 8FFFFEFF 		.word	-65649
+ 549 004c 00000140 		.word	1073807360
+ 550 0050 00040140 		.word	1073808384
+ 551              		.cfi_endproc
+ 552              	.LFE250:
+ 554              		.section	.text.TIM_OC6_SetConfig,"ax",%progbits
+ 555              		.align	1
+ARM GAS  /tmp/ccPLZXyC.s 			page 139
+
+
+ 556              		.syntax unified
+ 557              		.thumb
+ 558              		.thumb_func
+ 559              		.fpu fpv5-d16
+ 561              	TIM_OC6_SetConfig:
+ 562              	.LVL60:
+ 563              	.LFB251:
+7320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Timer Output Compare 6 configuration
+7323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  OC_Config The output configuration structure
+7325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+7328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                               const TIM_OC_InitTypeDef *OC_Config)
+7329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 564              		.loc 1 7329 1 is_stmt 1 view -0
+ 565              		.cfi_startproc
+ 566              		@ args = 0, pretend = 0, frame = 0
+ 567              		@ frame_needed = 0, uses_anonymous_args = 0
+ 568              		@ link register save eliminated.
+ 569              		.loc 1 7329 1 is_stmt 0 view .LVU203
+ 570 0000 70B4     		push	{r4, r5, r6}
+ 571              	.LCFI8:
+ 572              		.cfi_def_cfa_offset 12
+ 573              		.cfi_offset 4, -12
+ 574              		.cfi_offset 5, -8
+ 575              		.cfi_offset 6, -4
+7330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 576              		.loc 1 7330 3 is_stmt 1 view .LVU204
+7331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 577              		.loc 1 7331 3 view .LVU205
+7332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr2;
+ 578              		.loc 1 7332 3 view .LVU206
+7333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCER register value */
+7335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 579              		.loc 1 7335 3 view .LVU207
+ 580              		.loc 1 7335 11 is_stmt 0 view .LVU208
+ 581 0002 036A     		ldr	r3, [r0, #32]
+ 582              	.LVL61:
+7336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the output: Reset the CCxE Bit */
+7338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC6E;
+ 583              		.loc 1 7338 3 is_stmt 1 view .LVU209
+ 584              		.loc 1 7338 14 is_stmt 0 view .LVU210
+ 585 0004 026A     		ldr	r2, [r0, #32]
+ 586 0006 22F48012 		bic	r2, r2, #1048576
+ 587 000a 0262     		str	r2, [r0, #32]
+7339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CR2 register value */
+7341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpcr2 =  TIMx->CR2;
+ 588              		.loc 1 7341 3 is_stmt 1 view .LVU211
+ 589              		.loc 1 7341 10 is_stmt 0 view .LVU212
+ 590 000c 4468     		ldr	r4, [r0, #4]
+ 591              	.LVL62:
+ARM GAS  /tmp/ccPLZXyC.s 			page 140
+
+
+7342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx CCMR1 register value */
+7343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx = TIMx->CCMR3;
+ 592              		.loc 1 7343 3 is_stmt 1 view .LVU213
+ 593              		.loc 1 7343 12 is_stmt 0 view .LVU214
+ 594 000e 456D     		ldr	r5, [r0, #84]
+ 595              	.LVL63:
+7344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Compare Mode Bits */
+7346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx &= ~(TIM_CCMR3_OC6M);
+ 596              		.loc 1 7346 3 is_stmt 1 view .LVU215
+ 597              		.loc 1 7346 12 is_stmt 0 view .LVU216
+ 598 0010 0D4A     		ldr	r2, .L26
+ 599 0012 2A40     		ands	r2, r2, r5
+ 600              	.LVL64:
+7347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Output Compare Mode */
+7348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx |= (OC_Config->OCMode << 8U);
+ 601              		.loc 1 7348 3 is_stmt 1 view .LVU217
+ 602              		.loc 1 7348 25 is_stmt 0 view .LVU218
+ 603 0014 0D68     		ldr	r5, [r1]
+ 604              		.loc 1 7348 12 view .LVU219
+ 605 0016 42EA0522 		orr	r2, r2, r5, lsl #8
+ 606              	.LVL65:
+7349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Output Polarity level */
+7351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ 607              		.loc 1 7351 3 is_stmt 1 view .LVU220
+ 608              		.loc 1 7351 11 is_stmt 0 view .LVU221
+ 609 001a 23F40013 		bic	r3, r3, #2097152
+ 610              	.LVL66:
+7352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+7353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= (OC_Config->OCPolarity << 20U);
+ 611              		.loc 1 7353 3 is_stmt 1 view .LVU222
+ 612              		.loc 1 7353 24 is_stmt 0 view .LVU223
+ 613 001e 8D68     		ldr	r5, [r1, #8]
+ 614              		.loc 1 7353 11 view .LVU224
+ 615 0020 43EA0553 		orr	r3, r3, r5, lsl #20
+ 616              	.LVL67:
+7354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 617              		.loc 1 7355 3 is_stmt 1 view .LVU225
+ 618              		.loc 1 7355 6 is_stmt 0 view .LVU226
+ 619 0024 094E     		ldr	r6, .L26+4
+ 620 0026 0A4D     		ldr	r5, .L26+8
+ 621 0028 A842     		cmp	r0, r5
+ 622 002a 18BF     		it	ne
+ 623 002c B042     		cmpne	r0, r6
+ 624 002e 04D1     		bne	.L24
+7356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output Compare IDLE State */
+7358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS6;
+ 625              		.loc 1 7358 5 is_stmt 1 view .LVU227
+ 626              		.loc 1 7358 12 is_stmt 0 view .LVU228
+ 627 0030 24F48024 		bic	r4, r4, #262144
+ 628              	.LVL68:
+7359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output Idle state */
+7360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 |= (OC_Config->OCIdleState << 10U);
+ 629              		.loc 1 7360 5 is_stmt 1 view .LVU229
+ARM GAS  /tmp/ccPLZXyC.s 			page 141
+
+
+ 630              		.loc 1 7360 25 is_stmt 0 view .LVU230
+ 631 0034 4D69     		ldr	r5, [r1, #20]
+ 632              		.loc 1 7360 12 view .LVU231
+ 633 0036 44EA8524 		orr	r4, r4, r5, lsl #10
+ 634              	.LVL69:
+ 635              	.L24:
+7361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CR2 */
+7364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CR2 = tmpcr2;
+ 636              		.loc 1 7364 3 is_stmt 1 view .LVU232
+ 637              		.loc 1 7364 13 is_stmt 0 view .LVU233
+ 638 003a 4460     		str	r4, [r0, #4]
+7365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR3 */
+7367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR3 = tmpccmrx;
+ 639              		.loc 1 7367 3 is_stmt 1 view .LVU234
+ 640              		.loc 1 7367 15 is_stmt 0 view .LVU235
+ 641 003c 4265     		str	r2, [r0, #84]
+7368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Capture Compare Register value */
+7370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCR6 = OC_Config->Pulse;
+ 642              		.loc 1 7370 3 is_stmt 1 view .LVU236
+ 643              		.loc 1 7370 25 is_stmt 0 view .LVU237
+ 644 003e 4A68     		ldr	r2, [r1, #4]
+ 645              	.LVL70:
+ 646              		.loc 1 7370 14 view .LVU238
+ 647 0040 C265     		str	r2, [r0, #92]
+ 648              	.LVL71:
+7371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCER */
+7373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 649              		.loc 1 7373 3 is_stmt 1 view .LVU239
+ 650              		.loc 1 7373 14 is_stmt 0 view .LVU240
+ 651 0042 0362     		str	r3, [r0, #32]
+7374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 652              		.loc 1 7374 1 view .LVU241
+ 653 0044 70BC     		pop	{r4, r5, r6}
+ 654              	.LCFI9:
+ 655              		.cfi_restore 6
+ 656              		.cfi_restore 5
+ 657              		.cfi_restore 4
+ 658              		.cfi_def_cfa_offset 0
+ 659              	.LVL72:
+ 660              		.loc 1 7374 1 view .LVU242
+ 661 0046 7047     		bx	lr
+ 662              	.L27:
+ 663              		.align	2
+ 664              	.L26:
+ 665 0048 FF8FFFFE 		.word	-16805889
+ 666 004c 00000140 		.word	1073807360
+ 667 0050 00040140 		.word	1073808384
+ 668              		.cfi_endproc
+ 669              	.LFE251:
+ 671              		.section	.text.TIM_TI1_ConfigInputStage,"ax",%progbits
+ 672              		.align	1
+ 673              		.syntax unified
+ARM GAS  /tmp/ccPLZXyC.s 			page 142
+
+
+ 674              		.thumb
+ 675              		.thumb_func
+ 676              		.fpu fpv5-d16
+ 678              	TIM_TI1_ConfigInputStage:
+ 679              	.LVL73:
+ 680              	.LFB254:
+7375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Slave Timer configuration function
+7378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  htim TIM handle
+7379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  sSlaveConfig Slave timer configuration
+7380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+7383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig)
+7384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+7386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+7387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr1;
+7388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+7389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx SMCR register value */
+7391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr = htim->Instance->SMCR;
+7392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the Trigger Selection Bits */
+7394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr &= ~TIM_SMCR_TS;
+7395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Input Trigger source */
+7396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr |= sSlaveConfig->InputTrigger;
+7397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the slave mode Bits */
+7399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr &= ~TIM_SMCR_SMS;
+7400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the slave mode */
+7401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr |= sSlaveConfig->SlaveMode;
+7402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx SMCR */
+7404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->SMCR = tmpsmcr;
+7405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Configure the trigger prescaler, filter, and polarity */
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (sSlaveConfig->InputTrigger)
+7408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_TS_ETRF:
+7410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+7411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+7412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+7413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+7414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+7415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+7416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the ETR Trigger source */
+7417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_ETR_SetConfig(htim->Instance,
+7418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sSlaveConfig->TriggerPrescaler,
+7419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sSlaveConfig->TriggerPolarity,
+7420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sSlaveConfig->TriggerFilter);
+7421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+7422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+7423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_TS_TI1F_ED:
+7425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ARM GAS  /tmp/ccPLZXyC.s 			page 143
+
+
+7426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+7427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+7428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+7429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+7431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+7432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+7433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+7434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Disable the Channel 1: Reset the CC1E Bit */
+7436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpccer = htim->Instance->CCER;
+7437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCER &= ~TIM_CCER_CC1E;
+7438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpccmr1 = htim->Instance->CCMR1;
+7439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Set the filter */
+7441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpccmr1 &= ~TIM_CCMR1_IC1F;
+7442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+7443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Write to TIMx CCMR1 and CCER registers */
+7445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 = tmpccmr1;
+7446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCER = tmpccer;
+7447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+7448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+7449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_TS_TI1FP1:
+7451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+7452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+7453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+7454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+7456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure TI1 Filter and Polarity */
+7458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_TI1_ConfigInputStage(htim->Instance,
+7459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+7460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sSlaveConfig->TriggerFilter);
+7461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+7462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+7463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_TS_TI2FP2:
+7465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+7466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameters */
+7467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+7468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+7469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+7470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure TI2 Filter and Polarity */
+7472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_TI2_ConfigInputStage(htim->Instance,
+7473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+7474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sSlaveConfig->TriggerFilter);
+7475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+7476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+7477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_TS_ITR0:
+7479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_TS_ITR1:
+7480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_TS_ITR2:
+7481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     case TIM_TS_ITR3:
+7482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ARM GAS  /tmp/ccPLZXyC.s 			page 144
+
+
+7483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Check the parameter */
+7484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+7485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+7486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+7487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     default:
+7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       status = HAL_ERROR;
+7490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+7491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return status;
+7494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+7495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configure the TI1 as Input.
+7498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral.
+7499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+7500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICSelection specifies the input to be used.
+7505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+7507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+7508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+7509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+7513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+7514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        protected against un-initialized filter and polarity values.
+7515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+7517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                        uint32_t TIM_ICFilter)
+7518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+7519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr1;
+7520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+7521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Channel 1: Reset the CC1E Bit */
+7523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+7524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC1E;
+7525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+7526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Input */
+7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+7529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccmr1 &= ~TIM_CCMR1_CC1S;
+7531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccmr1 |= TIM_ICSelection;
+7532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   else
+7534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+7535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccmr1 |= TIM_CCMR1_CC1S_0;
+7536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+7537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the filter */
+7539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ARM GAS  /tmp/ccPLZXyC.s 			page 145
+
+
+7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+7541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Polarity and set the CC1E Bit */
+7543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+7544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+7545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR1 and CCER registers */
+7547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmr1;
+7548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+7549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+7550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configure the Polarity and Filter for TI1.
+7553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral.
+7554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+7555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil
+7564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 681              		.loc 1 7564 1 is_stmt 1 view -0
+ 682              		.cfi_startproc
+ 683              		@ args = 0, pretend = 0, frame = 0
+ 684              		@ frame_needed = 0, uses_anonymous_args = 0
+ 685              		@ link register save eliminated.
+ 686              		.loc 1 7564 1 is_stmt 0 view .LVU244
+ 687 0000 10B4     		push	{r4}
+ 688              	.LCFI10:
+ 689              		.cfi_def_cfa_offset 4
+ 690              		.cfi_offset 4, -4
+7565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 691              		.loc 1 7565 3 is_stmt 1 view .LVU245
+7566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 692              		.loc 1 7566 3 view .LVU246
+7567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Channel 1: Reset the CC1E Bit */
+7569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 693              		.loc 1 7569 3 view .LVU247
+ 694              		.loc 1 7569 11 is_stmt 0 view .LVU248
+ 695 0002 036A     		ldr	r3, [r0, #32]
+ 696              	.LVL74:
+7570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC1E;
+ 697              		.loc 1 7570 3 is_stmt 1 view .LVU249
+ 698              		.loc 1 7570 14 is_stmt 0 view .LVU250
+ 699 0004 046A     		ldr	r4, [r0, #32]
+ 700 0006 24F00104 		bic	r4, r4, #1
+ 701 000a 0462     		str	r4, [r0, #32]
+7571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+ 702              		.loc 1 7571 3 is_stmt 1 view .LVU251
+ 703              		.loc 1 7571 12 is_stmt 0 view .LVU252
+ 704 000c 8469     		ldr	r4, [r0, #24]
+ 705              	.LVL75:
+ARM GAS  /tmp/ccPLZXyC.s 			page 146
+
+
+7572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the filter */
+7574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ 706              		.loc 1 7574 3 is_stmt 1 view .LVU253
+ 707              		.loc 1 7574 12 is_stmt 0 view .LVU254
+ 708 000e 24F0F00C 		bic	ip, r4, #240
+ 709              	.LVL76:
+7575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= (TIM_ICFilter << 4U);
+ 710              		.loc 1 7575 3 is_stmt 1 view .LVU255
+ 711              		.loc 1 7575 12 is_stmt 0 view .LVU256
+ 712 0012 4CEA0212 		orr	r2, ip, r2, lsl #4
+ 713              	.LVL77:
+7576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Polarity and set the CC1E Bit */
+7578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ 714              		.loc 1 7578 3 is_stmt 1 view .LVU257
+ 715              		.loc 1 7578 11 is_stmt 0 view .LVU258
+ 716 0016 23F00A03 		bic	r3, r3, #10
+ 717              	.LVL78:
+7579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= TIM_ICPolarity;
+ 718              		.loc 1 7579 3 is_stmt 1 view .LVU259
+ 719              		.loc 1 7579 11 is_stmt 0 view .LVU260
+ 720 001a 0B43     		orrs	r3, r3, r1
+ 721              	.LVL79:
+7580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR1 and CCER registers */
+7582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmr1;
+ 722              		.loc 1 7582 3 is_stmt 1 view .LVU261
+ 723              		.loc 1 7582 15 is_stmt 0 view .LVU262
+ 724 001c 8261     		str	r2, [r0, #24]
+7583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 725              		.loc 1 7583 3 is_stmt 1 view .LVU263
+ 726              		.loc 1 7583 14 is_stmt 0 view .LVU264
+ 727 001e 0362     		str	r3, [r0, #32]
+7584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 728              		.loc 1 7584 1 view .LVU265
+ 729 0020 5DF8044B 		ldr	r4, [sp], #4
+ 730              	.LCFI11:
+ 731              		.cfi_restore 4
+ 732              		.cfi_def_cfa_offset 0
+ 733 0024 7047     		bx	lr
+ 734              		.cfi_endproc
+ 735              	.LFE254:
+ 737              		.section	.text.TIM_TI2_SetConfig,"ax",%progbits
+ 738              		.align	1
+ 739              		.syntax unified
+ 740              		.thumb
+ 741              		.thumb_func
+ 742              		.fpu fpv5-d16
+ 744              	TIM_TI2_SetConfig:
+ 745              	.LVL80:
+ 746              	.LFB255:
+7585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configure the TI2 as Input.
+7588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+ARM GAS  /tmp/ccPLZXyC.s 			page 147
+
+
+7590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICSelection specifies the input to be used.
+7595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+7597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+7598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+7599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+7603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+7604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        protected against un-initialized filter and polarity values.
+7605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+7607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                               uint32_t TIM_ICFilter)
+7608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 747              		.loc 1 7608 1 is_stmt 1 view -0
+ 748              		.cfi_startproc
+ 749              		@ args = 0, pretend = 0, frame = 0
+ 750              		@ frame_needed = 0, uses_anonymous_args = 0
+ 751              		@ link register save eliminated.
+ 752              		.loc 1 7608 1 is_stmt 0 view .LVU267
+ 753 0000 30B4     		push	{r4, r5}
+ 754              	.LCFI12:
+ 755              		.cfi_def_cfa_offset 8
+ 756              		.cfi_offset 4, -8
+ 757              		.cfi_offset 5, -4
+7609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 758              		.loc 1 7609 3 is_stmt 1 view .LVU268
+7610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 759              		.loc 1 7610 3 view .LVU269
+7611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Channel 2: Reset the CC2E Bit */
+7613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 760              		.loc 1 7613 3 view .LVU270
+ 761              		.loc 1 7613 11 is_stmt 0 view .LVU271
+ 762 0002 056A     		ldr	r5, [r0, #32]
+ 763              	.LVL81:
+7614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC2E;
+ 764              		.loc 1 7614 3 is_stmt 1 view .LVU272
+ 765              		.loc 1 7614 14 is_stmt 0 view .LVU273
+ 766 0004 046A     		ldr	r4, [r0, #32]
+ 767 0006 24F01004 		bic	r4, r4, #16
+ 768 000a 0462     		str	r4, [r0, #32]
+7615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+ 769              		.loc 1 7615 3 is_stmt 1 view .LVU274
+ 770              		.loc 1 7615 12 is_stmt 0 view .LVU275
+ 771 000c 8469     		ldr	r4, [r0, #24]
+ 772              	.LVL82:
+7616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Input */
+7618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 &= ~TIM_CCMR1_CC2S;
+ 773              		.loc 1 7618 3 is_stmt 1 view .LVU276
+ 774              		.loc 1 7618 12 is_stmt 0 view .LVU277
+ARM GAS  /tmp/ccPLZXyC.s 			page 148
+
+
+ 775 000e 24F4407C 		bic	ip, r4, #768
+ 776              	.LVL83:
+7619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= (TIM_ICSelection << 8U);
+ 777              		.loc 1 7619 3 is_stmt 1 view .LVU278
+ 778              		.loc 1 7619 12 is_stmt 0 view .LVU279
+ 779 0012 4CEA022C 		orr	ip, ip, r2, lsl #8
+ 780              	.LVL84:
+7620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the filter */
+7622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ 781              		.loc 1 7622 3 is_stmt 1 view .LVU280
+ 782              		.loc 1 7622 12 is_stmt 0 view .LVU281
+ 783 0016 2CF4704C 		bic	ip, ip, #61440
+ 784              	.LVL85:
+7623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+ 785              		.loc 1 7623 3 is_stmt 1 view .LVU282
+ 786              		.loc 1 7623 30 is_stmt 0 view .LVU283
+ 787 001a 1B03     		lsls	r3, r3, #12
+ 788              	.LVL86:
+ 789              		.loc 1 7623 38 view .LVU284
+ 790 001c 9BB2     		uxth	r3, r3
+ 791              		.loc 1 7623 12 view .LVU285
+ 792 001e 43EA0C03 		orr	r3, r3, ip
+ 793              	.LVL87:
+7624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Polarity and set the CC2E Bit */
+7626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 794              		.loc 1 7626 3 is_stmt 1 view .LVU286
+ 795              		.loc 1 7626 11 is_stmt 0 view .LVU287
+ 796 0022 25F0A005 		bic	r5, r5, #160
+ 797              	.LVL88:
+7627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+ 798              		.loc 1 7627 3 is_stmt 1 view .LVU288
+ 799              		.loc 1 7627 31 is_stmt 0 view .LVU289
+ 800 0026 0901     		lsls	r1, r1, #4
+ 801              	.LVL89:
+ 802              		.loc 1 7627 38 view .LVU290
+ 803 0028 01F0A001 		and	r1, r1, #160
+ 804              		.loc 1 7627 11 view .LVU291
+ 805 002c 2943     		orrs	r1, r1, r5
+ 806              	.LVL90:
+7628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR1 and CCER registers */
+7630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmr1 ;
+ 807              		.loc 1 7630 3 is_stmt 1 view .LVU292
+ 808              		.loc 1 7630 15 is_stmt 0 view .LVU293
+ 809 002e 8361     		str	r3, [r0, #24]
+7631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 810              		.loc 1 7631 3 is_stmt 1 view .LVU294
+ 811              		.loc 1 7631 14 is_stmt 0 view .LVU295
+ 812 0030 0162     		str	r1, [r0, #32]
+7632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 813              		.loc 1 7632 1 view .LVU296
+ 814 0032 30BC     		pop	{r4, r5}
+ 815              	.LCFI13:
+ 816              		.cfi_restore 5
+ 817              		.cfi_restore 4
+ARM GAS  /tmp/ccPLZXyC.s 			page 149
+
+
+ 818              		.cfi_def_cfa_offset 0
+ 819 0034 7047     		bx	lr
+ 820              		.cfi_endproc
+ 821              	.LFE255:
+ 823              		.section	.text.TIM_TI2_ConfigInputStage,"ax",%progbits
+ 824              		.align	1
+ 825              		.syntax unified
+ 826              		.thumb
+ 827              		.thumb_func
+ 828              		.fpu fpv5-d16
+ 830              	TIM_TI2_ConfigInputStage:
+ 831              	.LVL91:
+ 832              	.LFB256:
+7633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configure the Polarity and Filter for TI2.
+7636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral.
+7637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+7638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil
+7647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 833              		.loc 1 7647 1 is_stmt 1 view -0
+ 834              		.cfi_startproc
+ 835              		@ args = 0, pretend = 0, frame = 0
+ 836              		@ frame_needed = 0, uses_anonymous_args = 0
+ 837              		@ link register save eliminated.
+ 838              		.loc 1 7647 1 is_stmt 0 view .LVU298
+ 839 0000 10B4     		push	{r4}
+ 840              	.LCFI14:
+ 841              		.cfi_def_cfa_offset 4
+ 842              		.cfi_offset 4, -4
+7648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 843              		.loc 1 7648 3 is_stmt 1 view .LVU299
+7649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 844              		.loc 1 7649 3 view .LVU300
+7650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Channel 2: Reset the CC2E Bit */
+7652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 845              		.loc 1 7652 3 view .LVU301
+ 846              		.loc 1 7652 11 is_stmt 0 view .LVU302
+ 847 0002 036A     		ldr	r3, [r0, #32]
+ 848              	.LVL92:
+7653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC2E;
+ 849              		.loc 1 7653 3 is_stmt 1 view .LVU303
+ 850              		.loc 1 7653 14 is_stmt 0 view .LVU304
+ 851 0004 046A     		ldr	r4, [r0, #32]
+ 852 0006 24F01004 		bic	r4, r4, #16
+ 853 000a 0462     		str	r4, [r0, #32]
+7654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+ 854              		.loc 1 7654 3 is_stmt 1 view .LVU305
+ARM GAS  /tmp/ccPLZXyC.s 			page 150
+
+
+ 855              		.loc 1 7654 12 is_stmt 0 view .LVU306
+ 856 000c 8469     		ldr	r4, [r0, #24]
+ 857              	.LVL93:
+7655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the filter */
+7657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ 858              		.loc 1 7657 3 is_stmt 1 view .LVU307
+ 859              		.loc 1 7657 12 is_stmt 0 view .LVU308
+ 860 000e 24F4704C 		bic	ip, r4, #61440
+ 861              	.LVL94:
+7658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= (TIM_ICFilter << 12U);
+ 862              		.loc 1 7658 3 is_stmt 1 view .LVU309
+ 863              		.loc 1 7658 12 is_stmt 0 view .LVU310
+ 864 0012 4CEA0232 		orr	r2, ip, r2, lsl #12
+ 865              	.LVL95:
+7659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Polarity and set the CC2E Bit */
+7661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 866              		.loc 1 7661 3 is_stmt 1 view .LVU311
+ 867              		.loc 1 7661 11 is_stmt 0 view .LVU312
+ 868 0016 23F0A003 		bic	r3, r3, #160
+ 869              	.LVL96:
+7662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= (TIM_ICPolarity << 4U);
+ 870              		.loc 1 7662 3 is_stmt 1 view .LVU313
+ 871              		.loc 1 7662 11 is_stmt 0 view .LVU314
+ 872 001a 43EA0113 		orr	r3, r3, r1, lsl #4
+ 873              	.LVL97:
+7663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR1 and CCER registers */
+7665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR1 = tmpccmr1 ;
+ 874              		.loc 1 7665 3 is_stmt 1 view .LVU315
+ 875              		.loc 1 7665 15 is_stmt 0 view .LVU316
+ 876 001e 8261     		str	r2, [r0, #24]
+7666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 877              		.loc 1 7666 3 is_stmt 1 view .LVU317
+ 878              		.loc 1 7666 14 is_stmt 0 view .LVU318
+ 879 0020 0362     		str	r3, [r0, #32]
+7667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 880              		.loc 1 7667 1 view .LVU319
+ 881 0022 5DF8044B 		ldr	r4, [sp], #4
+ 882              	.LCFI15:
+ 883              		.cfi_restore 4
+ 884              		.cfi_def_cfa_offset 0
+ 885 0026 7047     		bx	lr
+ 886              		.cfi_endproc
+ 887              	.LFE256:
+ 889              		.section	.text.TIM_TI3_SetConfig,"ax",%progbits
+ 890              		.align	1
+ 891              		.syntax unified
+ 892              		.thumb
+ 893              		.thumb_func
+ 894              		.fpu fpv5-d16
+ 896              	TIM_TI3_SetConfig:
+ 897              	.LVL98:
+ 898              	.LFB257:
+7668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ARM GAS  /tmp/ccPLZXyC.s 			page 151
+
+
+7670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configure the TI3 as Input.
+7671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+7673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICSelection specifies the input to be used.
+7678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+7680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+7681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+7682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+7686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+7687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        protected against un-initialized filter and polarity values.
+7688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+7690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                               uint32_t TIM_ICFilter)
+7691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 899              		.loc 1 7691 1 is_stmt 1 view -0
+ 900              		.cfi_startproc
+ 901              		@ args = 0, pretend = 0, frame = 0
+ 902              		@ frame_needed = 0, uses_anonymous_args = 0
+ 903              		@ link register save eliminated.
+ 904              		.loc 1 7691 1 is_stmt 0 view .LVU321
+ 905 0000 30B4     		push	{r4, r5}
+ 906              	.LCFI16:
+ 907              		.cfi_def_cfa_offset 8
+ 908              		.cfi_offset 4, -8
+ 909              		.cfi_offset 5, -4
+7692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr2;
+ 910              		.loc 1 7692 3 is_stmt 1 view .LVU322
+7693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 911              		.loc 1 7693 3 view .LVU323
+7694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Channel 3: Reset the CC3E Bit */
+7696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 912              		.loc 1 7696 3 view .LVU324
+ 913              		.loc 1 7696 11 is_stmt 0 view .LVU325
+ 914 0002 056A     		ldr	r5, [r0, #32]
+ 915              	.LVL99:
+7697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC3E;
+ 916              		.loc 1 7697 3 is_stmt 1 view .LVU326
+ 917              		.loc 1 7697 14 is_stmt 0 view .LVU327
+ 918 0004 046A     		ldr	r4, [r0, #32]
+ 919 0006 24F48074 		bic	r4, r4, #256
+ 920 000a 0462     		str	r4, [r0, #32]
+7698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr2 = TIMx->CCMR2;
+ 921              		.loc 1 7698 3 is_stmt 1 view .LVU328
+ 922              		.loc 1 7698 12 is_stmt 0 view .LVU329
+ 923 000c C469     		ldr	r4, [r0, #28]
+ 924              	.LVL100:
+7699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Input */
+ARM GAS  /tmp/ccPLZXyC.s 			page 152
+
+
+7701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr2 &= ~TIM_CCMR2_CC3S;
+ 925              		.loc 1 7701 3 is_stmt 1 view .LVU330
+ 926              		.loc 1 7701 12 is_stmt 0 view .LVU331
+ 927 000e 24F0030C 		bic	ip, r4, #3
+ 928              	.LVL101:
+7702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr2 |= TIM_ICSelection;
+ 929              		.loc 1 7702 3 is_stmt 1 view .LVU332
+ 930              		.loc 1 7702 12 is_stmt 0 view .LVU333
+ 931 0012 4CEA020C 		orr	ip, ip, r2
+ 932              	.LVL102:
+7703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the filter */
+7705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr2 &= ~TIM_CCMR2_IC3F;
+ 933              		.loc 1 7705 3 is_stmt 1 view .LVU334
+ 934              		.loc 1 7705 12 is_stmt 0 view .LVU335
+ 935 0016 2CF0F00C 		bic	ip, ip, #240
+ 936              	.LVL103:
+7706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+ 937              		.loc 1 7706 3 is_stmt 1 view .LVU336
+ 938              		.loc 1 7706 30 is_stmt 0 view .LVU337
+ 939 001a 1B01     		lsls	r3, r3, #4
+ 940              	.LVL104:
+ 941              		.loc 1 7706 37 view .LVU338
+ 942 001c DBB2     		uxtb	r3, r3
+ 943              		.loc 1 7706 12 view .LVU339
+ 944 001e 43EA0C03 		orr	r3, r3, ip
+ 945              	.LVL105:
+7707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Polarity and set the CC3E Bit */
+7709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ 946              		.loc 1 7709 3 is_stmt 1 view .LVU340
+ 947              		.loc 1 7709 11 is_stmt 0 view .LVU341
+ 948 0022 25F42065 		bic	r5, r5, #2560
+ 949              	.LVL106:
+7710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+ 950              		.loc 1 7710 3 is_stmt 1 view .LVU342
+ 951              		.loc 1 7710 31 is_stmt 0 view .LVU343
+ 952 0026 0902     		lsls	r1, r1, #8
+ 953              	.LVL107:
+ 954              		.loc 1 7710 38 view .LVU344
+ 955 0028 01F42061 		and	r1, r1, #2560
+ 956              		.loc 1 7710 11 view .LVU345
+ 957 002c 2943     		orrs	r1, r1, r5
+ 958              	.LVL108:
+7711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR2 and CCER registers */
+7713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR2 = tmpccmr2;
+ 959              		.loc 1 7713 3 is_stmt 1 view .LVU346
+ 960              		.loc 1 7713 15 is_stmt 0 view .LVU347
+ 961 002e C361     		str	r3, [r0, #28]
+7714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 962              		.loc 1 7714 3 is_stmt 1 view .LVU348
+ 963              		.loc 1 7714 14 is_stmt 0 view .LVU349
+ 964 0030 0162     		str	r1, [r0, #32]
+7715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 965              		.loc 1 7715 1 view .LVU350
+ 966 0032 30BC     		pop	{r4, r5}
+ARM GAS  /tmp/ccPLZXyC.s 			page 153
+
+
+ 967              	.LCFI17:
+ 968              		.cfi_restore 5
+ 969              		.cfi_restore 4
+ 970              		.cfi_def_cfa_offset 0
+ 971 0034 7047     		bx	lr
+ 972              		.cfi_endproc
+ 973              	.LFE257:
+ 975              		.section	.text.TIM_TI4_SetConfig,"ax",%progbits
+ 976              		.align	1
+ 977              		.syntax unified
+ 978              		.thumb
+ 979              		.thumb_func
+ 980              		.fpu fpv5-d16
+ 982              	TIM_TI4_SetConfig:
+ 983              	.LVL109:
+ 984              	.LFB258:
+7716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configure the TI4 as Input.
+7719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICPolarity The Input Polarity.
+7721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_RISING
+7723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_FALLING
+7724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICPOLARITY_BOTHEDGE
+7725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICSelection specifies the input to be used.
+7726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+7728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+7729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+7730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ICFilter Specifies the Input Capture Filter.
+7731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F.
+7732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+7733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+7734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *        protected against un-initialized filter and polarity values.
+7735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+7738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                               uint32_t TIM_ICFilter)
+7739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 985              		.loc 1 7739 1 is_stmt 1 view -0
+ 986              		.cfi_startproc
+ 987              		@ args = 0, pretend = 0, frame = 0
+ 988              		@ frame_needed = 0, uses_anonymous_args = 0
+ 989              		@ link register save eliminated.
+ 990              		.loc 1 7739 1 is_stmt 0 view .LVU352
+ 991 0000 30B4     		push	{r4, r5}
+ 992              	.LCFI18:
+ 993              		.cfi_def_cfa_offset 8
+ 994              		.cfi_offset 4, -8
+ 995              		.cfi_offset 5, -4
+7740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr2;
+ 996              		.loc 1 7740 3 is_stmt 1 view .LVU353
+7741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 997              		.loc 1 7741 3 view .LVU354
+7742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Disable the Channel 4: Reset the CC4E Bit */
+ARM GAS  /tmp/ccPLZXyC.s 			page 154
+
+
+7744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer = TIMx->CCER;
+ 998              		.loc 1 7744 3 view .LVU355
+ 999              		.loc 1 7744 11 is_stmt 0 view .LVU356
+ 1000 0002 056A     		ldr	r5, [r0, #32]
+ 1001              	.LVL110:
+7745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC4E;
+ 1002              		.loc 1 7745 3 is_stmt 1 view .LVU357
+ 1003              		.loc 1 7745 14 is_stmt 0 view .LVU358
+ 1004 0004 046A     		ldr	r4, [r0, #32]
+ 1005 0006 24F48054 		bic	r4, r4, #4096
+ 1006 000a 0462     		str	r4, [r0, #32]
+7746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr2 = TIMx->CCMR2;
+ 1007              		.loc 1 7746 3 is_stmt 1 view .LVU359
+ 1008              		.loc 1 7746 12 is_stmt 0 view .LVU360
+ 1009 000c C469     		ldr	r4, [r0, #28]
+ 1010              	.LVL111:
+7747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Input */
+7749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr2 &= ~TIM_CCMR2_CC4S;
+ 1011              		.loc 1 7749 3 is_stmt 1 view .LVU361
+ 1012              		.loc 1 7749 12 is_stmt 0 view .LVU362
+ 1013 000e 24F4407C 		bic	ip, r4, #768
+ 1014              	.LVL112:
+7750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr2 |= (TIM_ICSelection << 8U);
+ 1015              		.loc 1 7750 3 is_stmt 1 view .LVU363
+ 1016              		.loc 1 7750 12 is_stmt 0 view .LVU364
+ 1017 0012 4CEA022C 		orr	ip, ip, r2, lsl #8
+ 1018              	.LVL113:
+7751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the filter */
+7753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr2 &= ~TIM_CCMR2_IC4F;
+ 1019              		.loc 1 7753 3 is_stmt 1 view .LVU365
+ 1020              		.loc 1 7753 12 is_stmt 0 view .LVU366
+ 1021 0016 2CF4704C 		bic	ip, ip, #61440
+ 1022              	.LVL114:
+7754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+ 1023              		.loc 1 7754 3 is_stmt 1 view .LVU367
+ 1024              		.loc 1 7754 30 is_stmt 0 view .LVU368
+ 1025 001a 1B03     		lsls	r3, r3, #12
+ 1026              	.LVL115:
+ 1027              		.loc 1 7754 38 view .LVU369
+ 1028 001c 9BB2     		uxth	r3, r3
+ 1029              		.loc 1 7754 12 view .LVU370
+ 1030 001e 43EA0C03 		orr	r3, r3, ip
+ 1031              	.LVL116:
+7755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Select the Polarity and set the CC4E Bit */
+7757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ 1032              		.loc 1 7757 3 is_stmt 1 view .LVU371
+ 1033              		.loc 1 7757 11 is_stmt 0 view .LVU372
+ 1034 0022 25F42045 		bic	r5, r5, #40960
+ 1035              	.LVL117:
+7758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+ 1036              		.loc 1 7758 3 is_stmt 1 view .LVU373
+ 1037              		.loc 1 7758 31 is_stmt 0 view .LVU374
+ 1038 0026 0903     		lsls	r1, r1, #12
+ 1039              	.LVL118:
+ARM GAS  /tmp/ccPLZXyC.s 			page 155
+
+
+ 1040              		.loc 1 7758 39 view .LVU375
+ 1041 0028 01F42041 		and	r1, r1, #40960
+ 1042              		.loc 1 7758 11 view .LVU376
+ 1043 002c 2943     		orrs	r1, r1, r5
+ 1044              	.LVL119:
+7759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx CCMR2 and CCER registers */
+7761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCMR2 = tmpccmr2;
+ 1045              		.loc 1 7761 3 is_stmt 1 view .LVU377
+ 1046              		.loc 1 7761 15 is_stmt 0 view .LVU378
+ 1047 002e C361     		str	r3, [r0, #28]
+7762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer ;
+ 1048              		.loc 1 7762 3 is_stmt 1 view .LVU379
+ 1049              		.loc 1 7762 14 is_stmt 0 view .LVU380
+ 1050 0030 0162     		str	r1, [r0, #32]
+7763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1051              		.loc 1 7763 1 view .LVU381
+ 1052 0032 30BC     		pop	{r4, r5}
+ 1053              	.LCFI19:
+ 1054              		.cfi_restore 5
+ 1055              		.cfi_restore 4
+ 1056              		.cfi_def_cfa_offset 0
+ 1057 0034 7047     		bx	lr
+ 1058              		.cfi_endproc
+ 1059              	.LFE258:
+ 1061              		.section	.text.TIM_ITRx_SetConfig,"ax",%progbits
+ 1062              		.align	1
+ 1063              		.syntax unified
+ 1064              		.thumb
+ 1065              		.thumb_func
+ 1066              		.fpu fpv5-d16
+ 1068              	TIM_ITRx_SetConfig:
+ 1069              	.LVL120:
+ 1070              	.LFB259:
+7764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Selects the Input Trigger source
+7767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  InputTriggerSource The Input Trigger source.
+7769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_TS_ITR0: Internal Trigger 0
+7771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_TS_ITR1: Internal Trigger 1
+7772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_TS_ITR2: Internal Trigger 2
+7773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_TS_ITR3: Internal Trigger 3
+7774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+7775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+7776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+7777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_TS_ETRF: External Trigger input
+7778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+7781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 1071              		.loc 1 7781 1 is_stmt 1 view -0
+ 1072              		.cfi_startproc
+ 1073              		@ args = 0, pretend = 0, frame = 0
+ 1074              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1075              		@ link register save eliminated.
+ARM GAS  /tmp/ccPLZXyC.s 			page 156
+
+
+7782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 1076              		.loc 1 7782 3 view .LVU383
+7783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Get the TIMx SMCR register value */
+7785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr = TIMx->SMCR;
+ 1077              		.loc 1 7785 3 view .LVU384
+ 1078              		.loc 1 7785 11 is_stmt 0 view .LVU385
+ 1079 0000 8368     		ldr	r3, [r0, #8]
+ 1080              	.LVL121:
+7786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the TS Bits */
+7787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr &= ~TIM_SMCR_TS;
+ 1081              		.loc 1 7787 3 is_stmt 1 view .LVU386
+ 1082              		.loc 1 7787 11 is_stmt 0 view .LVU387
+ 1083 0002 23F07003 		bic	r3, r3, #112
+ 1084              	.LVL122:
+7788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Input Trigger source and the slave mode*/
+7789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ 1085              		.loc 1 7789 3 is_stmt 1 view .LVU388
+ 1086              		.loc 1 7789 11 is_stmt 0 view .LVU389
+ 1087 0006 0B43     		orrs	r3, r3, r1
+ 1088              	.LVL123:
+ 1089              		.loc 1 7789 11 view .LVU390
+ 1090 0008 43F00703 		orr	r3, r3, #7
+ 1091              	.LVL124:
+7790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx SMCR */
+7791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->SMCR = tmpsmcr;
+ 1092              		.loc 1 7791 3 is_stmt 1 view .LVU391
+ 1093              		.loc 1 7791 14 is_stmt 0 view .LVU392
+ 1094 000c 8360     		str	r3, [r0, #8]
+7792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1095              		.loc 1 7792 1 view .LVU393
+ 1096 000e 7047     		bx	lr
+ 1097              		.cfi_endproc
+ 1098              	.LFE259:
+ 1100              		.section	.text.HAL_TIM_Base_MspInit,"ax",%progbits
+ 1101              		.align	1
+ 1102              		.weak	HAL_TIM_Base_MspInit
+ 1103              		.syntax unified
+ 1104              		.thumb
+ 1105              		.thumb_func
+ 1106              		.fpu fpv5-d16
+ 1108              	HAL_TIM_Base_MspInit:
+ 1109              	.LVL125:
+ 1110              	.LFB143:
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 1111              		.loc 1 373 1 is_stmt 1 view -0
+ 1112              		.cfi_startproc
+ 1113              		@ args = 0, pretend = 0, frame = 0
+ 1114              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1115              		@ link register save eliminated.
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1116              		.loc 1 375 3 view .LVU395
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1117              		.loc 1 380 1 is_stmt 0 view .LVU396
+ 1118 0000 7047     		bx	lr
+ 1119              		.cfi_endproc
+ 1120              	.LFE143:
+ARM GAS  /tmp/ccPLZXyC.s 			page 157
+
+
+ 1122              		.section	.text.HAL_TIM_Base_MspDeInit,"ax",%progbits
+ 1123              		.align	1
+ 1124              		.weak	HAL_TIM_Base_MspDeInit
+ 1125              		.syntax unified
+ 1126              		.thumb
+ 1127              		.thumb_func
+ 1128              		.fpu fpv5-d16
+ 1130              	HAL_TIM_Base_MspDeInit:
+ 1131              	.LVL126:
+ 1132              	.LFB144:
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 1133              		.loc 1 388 1 is_stmt 1 view -0
+ 1134              		.cfi_startproc
+ 1135              		@ args = 0, pretend = 0, frame = 0
+ 1136              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1137              		@ link register save eliminated.
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1138              		.loc 1 390 3 view .LVU398
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1139              		.loc 1 395 1 is_stmt 0 view .LVU399
+ 1140 0000 7047     		bx	lr
+ 1141              		.cfi_endproc
+ 1142              	.LFE144:
+ 1144              		.section	.text.HAL_TIM_Base_DeInit,"ax",%progbits
+ 1145              		.align	1
+ 1146              		.global	HAL_TIM_Base_DeInit
+ 1147              		.syntax unified
+ 1148              		.thumb
+ 1149              		.thumb_func
+ 1150              		.fpu fpv5-d16
+ 1152              	HAL_TIM_Base_DeInit:
+ 1153              	.LVL127:
+ 1154              	.LFB142:
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 1155              		.loc 1 330 1 is_stmt 1 view -0
+ 1156              		.cfi_startproc
+ 1157              		@ args = 0, pretend = 0, frame = 0
+ 1158              		@ frame_needed = 0, uses_anonymous_args = 0
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 1159              		.loc 1 330 1 is_stmt 0 view .LVU401
+ 1160 0000 10B5     		push	{r4, lr}
+ 1161              	.LCFI20:
+ 1162              		.cfi_def_cfa_offset 8
+ 1163              		.cfi_offset 4, -8
+ 1164              		.cfi_offset 14, -4
+ 1165 0002 0446     		mov	r4, r0
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1166              		.loc 1 332 3 is_stmt 1 view .LVU402
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1167              		.loc 1 334 3 view .LVU403
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1168              		.loc 1 334 15 is_stmt 0 view .LVU404
+ 1169 0004 0223     		movs	r3, #2
+ 1170 0006 80F83D30 		strb	r3, [r0, #61]
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1171              		.loc 1 337 3 is_stmt 1 view .LVU405
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 158
+
+
+ 1172              		.loc 1 337 3 view .LVU406
+ 1173 000a 0368     		ldr	r3, [r0]
+ 1174 000c 196A     		ldr	r1, [r3, #32]
+ 1175 000e 41F21112 		movw	r2, #4369
+ 1176 0012 1142     		tst	r1, r2
+ 1177 0014 08D1     		bne	.L42
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1178              		.loc 1 337 3 discriminator 1 view .LVU407
+ 1179 0016 196A     		ldr	r1, [r3, #32]
+ 1180 0018 40F24442 		movw	r2, #1092
+ 1181 001c 1142     		tst	r1, r2
+ 1182 001e 03D1     		bne	.L42
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1183              		.loc 1 337 3 discriminator 3 view .LVU408
+ 1184 0020 1A68     		ldr	r2, [r3]
+ 1185 0022 22F00102 		bic	r2, r2, #1
+ 1186 0026 1A60     		str	r2, [r3]
+ 1187              	.L42:
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1188              		.loc 1 337 3 discriminator 5 view .LVU409
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 1189              		.loc 1 348 3 discriminator 5 view .LVU410
+ 1190 0028 2046     		mov	r0, r4
+ 1191              	.LVL128:
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 1192              		.loc 1 348 3 is_stmt 0 discriminator 5 view .LVU411
+ 1193 002a FFF7FEFF 		bl	HAL_TIM_Base_MspDeInit
+ 1194              	.LVL129:
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1195              		.loc 1 352 3 is_stmt 1 discriminator 5 view .LVU412
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1196              		.loc 1 352 23 is_stmt 0 discriminator 5 view .LVU413
+ 1197 002e 0020     		movs	r0, #0
+ 1198 0030 84F84800 		strb	r0, [r4, #72]
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1199              		.loc 1 355 3 is_stmt 1 discriminator 5 view .LVU414
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1200              		.loc 1 355 3 discriminator 5 view .LVU415
+ 1201 0034 84F83E00 		strb	r0, [r4, #62]
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1202              		.loc 1 355 3 discriminator 5 view .LVU416
+ 1203 0038 84F83F00 		strb	r0, [r4, #63]
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1204              		.loc 1 355 3 discriminator 5 view .LVU417
+ 1205 003c 84F84000 		strb	r0, [r4, #64]
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1206              		.loc 1 355 3 discriminator 5 view .LVU418
+ 1207 0040 84F84100 		strb	r0, [r4, #65]
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1208              		.loc 1 355 3 discriminator 5 view .LVU419
+ 1209 0044 84F84200 		strb	r0, [r4, #66]
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1210              		.loc 1 355 3 discriminator 5 view .LVU420
+ 1211 0048 84F84300 		strb	r0, [r4, #67]
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1212              		.loc 1 355 3 discriminator 5 view .LVU421
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 159
+
+
+ 1213              		.loc 1 356 3 discriminator 5 view .LVU422
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1214              		.loc 1 356 3 discriminator 5 view .LVU423
+ 1215 004c 84F84400 		strb	r0, [r4, #68]
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1216              		.loc 1 356 3 discriminator 5 view .LVU424
+ 1217 0050 84F84500 		strb	r0, [r4, #69]
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1218              		.loc 1 356 3 discriminator 5 view .LVU425
+ 1219 0054 84F84600 		strb	r0, [r4, #70]
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1220              		.loc 1 356 3 discriminator 5 view .LVU426
+ 1221 0058 84F84700 		strb	r0, [r4, #71]
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1222              		.loc 1 356 3 discriminator 5 view .LVU427
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1223              		.loc 1 359 3 discriminator 5 view .LVU428
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1224              		.loc 1 359 15 is_stmt 0 discriminator 5 view .LVU429
+ 1225 005c 84F83D00 		strb	r0, [r4, #61]
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1226              		.loc 1 362 3 is_stmt 1 discriminator 5 view .LVU430
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1227              		.loc 1 362 3 discriminator 5 view .LVU431
+ 1228 0060 84F83C00 		strb	r0, [r4, #60]
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1229              		.loc 1 362 3 discriminator 5 view .LVU432
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1230              		.loc 1 364 3 discriminator 5 view .LVU433
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1231              		.loc 1 365 1 is_stmt 0 discriminator 5 view .LVU434
+ 1232 0064 10BD     		pop	{r4, pc}
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1233              		.loc 1 365 1 discriminator 5 view .LVU435
+ 1234              		.cfi_endproc
+ 1235              	.LFE142:
+ 1237              		.section	.text.HAL_TIM_Base_Start,"ax",%progbits
+ 1238              		.align	1
+ 1239              		.global	HAL_TIM_Base_Start
+ 1240              		.syntax unified
+ 1241              		.thumb
+ 1242              		.thumb_func
+ 1243              		.fpu fpv5-d16
+ 1245              	HAL_TIM_Base_Start:
+ 1246              	.LVL130:
+ 1247              	.LFB145:
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 1248              		.loc 1 404 1 is_stmt 1 view -0
+ 1249              		.cfi_startproc
+ 1250              		@ args = 0, pretend = 0, frame = 0
+ 1251              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1252              		@ link register save eliminated.
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1253              		.loc 1 405 3 view .LVU437
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1254              		.loc 1 408 3 view .LVU438
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 160
+
+
+ 1255              		.loc 1 411 3 view .LVU439
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1256              		.loc 1 411 11 is_stmt 0 view .LVU440
+ 1257 0000 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+ 1258 0004 DBB2     		uxtb	r3, r3
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1259              		.loc 1 411 6 view .LVU441
+ 1260 0006 012B     		cmp	r3, #1
+ 1261 0008 35D1     		bne	.L48
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1262              		.loc 1 417 3 is_stmt 1 view .LVU442
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1263              		.loc 1 417 15 is_stmt 0 view .LVU443
+ 1264 000a 0223     		movs	r3, #2
+ 1265 000c 80F83D30 		strb	r3, [r0, #61]
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1266              		.loc 1 420 3 is_stmt 1 view .LVU444
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1267              		.loc 1 420 7 is_stmt 0 view .LVU445
+ 1268 0010 0368     		ldr	r3, [r0]
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1269              		.loc 1 420 6 view .LVU446
+ 1270 0012 1B4A     		ldr	r2, .L50
+ 1271 0014 B3F1804F 		cmp	r3, #1073741824
+ 1272 0018 18BF     		it	ne
+ 1273 001a 9342     		cmpne	r3, r2
+ 1274 001c 1DD0     		beq	.L46
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1275              		.loc 1 420 7 discriminator 1 view .LVU447
+ 1276 001e A2F57C42 		sub	r2, r2, #64512
+ 1277 0022 9342     		cmp	r3, r2
+ 1278 0024 19D0     		beq	.L46
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1279              		.loc 1 420 7 discriminator 2 view .LVU448
+ 1280 0026 02F58062 		add	r2, r2, #1024
+ 1281 002a 9342     		cmp	r3, r2
+ 1282 002c 15D0     		beq	.L46
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1283              		.loc 1 420 7 discriminator 3 view .LVU449
+ 1284 002e 02F58062 		add	r2, r2, #1024
+ 1285 0032 9342     		cmp	r3, r2
+ 1286 0034 11D0     		beq	.L46
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1287              		.loc 1 420 7 discriminator 4 view .LVU450
+ 1288 0036 02F57842 		add	r2, r2, #63488
+ 1289 003a 9342     		cmp	r3, r2
+ 1290 003c 0DD0     		beq	.L46
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1291              		.loc 1 420 7 discriminator 5 view .LVU451
+ 1292 003e 02F57052 		add	r2, r2, #15360
+ 1293 0042 9342     		cmp	r3, r2
+ 1294 0044 09D0     		beq	.L46
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1295              		.loc 1 420 7 discriminator 6 view .LVU452
+ 1296 0046 A2F59432 		sub	r2, r2, #75776
+ 1297 004a 9342     		cmp	r3, r2
+ 1298 004c 05D0     		beq	.L46
+ARM GAS  /tmp/ccPLZXyC.s 			page 161
+
+
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 1299              		.loc 1 430 5 is_stmt 1 view .LVU453
+ 1300 004e 1A68     		ldr	r2, [r3]
+ 1301 0050 42F00102 		orr	r2, r2, #1
+ 1302 0054 1A60     		str	r2, [r3]
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1303              		.loc 1 434 10 is_stmt 0 view .LVU454
+ 1304 0056 0020     		movs	r0, #0
+ 1305              	.LVL131:
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1306              		.loc 1 434 10 view .LVU455
+ 1307 0058 7047     		bx	lr
+ 1308              	.LVL132:
+ 1309              	.L46:
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1310              		.loc 1 422 5 is_stmt 1 view .LVU456
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1311              		.loc 1 422 29 is_stmt 0 view .LVU457
+ 1312 005a 9968     		ldr	r1, [r3, #8]
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1313              		.loc 1 422 13 view .LVU458
+ 1314 005c 094A     		ldr	r2, .L50+4
+ 1315 005e 0A40     		ands	r2, r2, r1
+ 1316              	.LVL133:
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 1317              		.loc 1 423 5 is_stmt 1 view .LVU459
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 1318              		.loc 1 423 8 is_stmt 0 view .LVU460
+ 1319 0060 062A     		cmp	r2, #6
+ 1320 0062 18BF     		it	ne
+ 1321 0064 B2F5803F 		cmpne	r2, #65536
+ 1322 0068 07D0     		beq	.L49
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 1323              		.loc 1 425 7 is_stmt 1 view .LVU461
+ 1324 006a 1A68     		ldr	r2, [r3]
+ 1325              	.LVL134:
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 1326              		.loc 1 425 7 is_stmt 0 view .LVU462
+ 1327 006c 42F00102 		orr	r2, r2, #1
+ 1328 0070 1A60     		str	r2, [r3]
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1329              		.loc 1 434 10 view .LVU463
+ 1330 0072 0020     		movs	r0, #0
+ 1331              	.LVL135:
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1332              		.loc 1 434 10 view .LVU464
+ 1333 0074 7047     		bx	lr
+ 1334              	.LVL136:
+ 1335              	.L48:
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 1336              		.loc 1 413 12 view .LVU465
+ 1337 0076 0120     		movs	r0, #1
+ 1338              	.LVL137:
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 1339              		.loc 1 413 12 view .LVU466
+ 1340 0078 7047     		bx	lr
+ 1341              	.LVL138:
+ARM GAS  /tmp/ccPLZXyC.s 			page 162
+
+
+ 1342              	.L49:
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1343              		.loc 1 434 10 view .LVU467
+ 1344 007a 0020     		movs	r0, #0
+ 1345              	.LVL139:
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1346              		.loc 1 435 1 view .LVU468
+ 1347 007c 7047     		bx	lr
+ 1348              	.L51:
+ 1349 007e 00BF     		.align	2
+ 1350              	.L50:
+ 1351 0080 00000140 		.word	1073807360
+ 1352 0084 07000100 		.word	65543
+ 1353              		.cfi_endproc
+ 1354              	.LFE145:
+ 1356              		.section	.text.HAL_TIM_Base_Stop,"ax",%progbits
+ 1357              		.align	1
+ 1358              		.global	HAL_TIM_Base_Stop
+ 1359              		.syntax unified
+ 1360              		.thumb
+ 1361              		.thumb_func
+ 1362              		.fpu fpv5-d16
+ 1364              	HAL_TIM_Base_Stop:
+ 1365              	.LVL140:
+ 1366              	.LFB146:
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 1367              		.loc 1 443 1 is_stmt 1 view -0
+ 1368              		.cfi_startproc
+ 1369              		@ args = 0, pretend = 0, frame = 0
+ 1370              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1371              		@ link register save eliminated.
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1372              		.loc 1 445 3 view .LVU470
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1373              		.loc 1 448 3 view .LVU471
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1374              		.loc 1 448 3 view .LVU472
+ 1375 0000 0368     		ldr	r3, [r0]
+ 1376 0002 196A     		ldr	r1, [r3, #32]
+ 1377 0004 41F21112 		movw	r2, #4369
+ 1378 0008 1142     		tst	r1, r2
+ 1379 000a 08D1     		bne	.L53
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1380              		.loc 1 448 3 discriminator 1 view .LVU473
+ 1381 000c 196A     		ldr	r1, [r3, #32]
+ 1382 000e 40F24442 		movw	r2, #1092
+ 1383 0012 1142     		tst	r1, r2
+ 1384 0014 03D1     		bne	.L53
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1385              		.loc 1 448 3 discriminator 3 view .LVU474
+ 1386 0016 1A68     		ldr	r2, [r3]
+ 1387 0018 22F00102 		bic	r2, r2, #1
+ 1388 001c 1A60     		str	r2, [r3]
+ 1389              	.L53:
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1390              		.loc 1 448 3 discriminator 5 view .LVU475
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 163
+
+
+ 1391              		.loc 1 451 3 discriminator 5 view .LVU476
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1392              		.loc 1 451 15 is_stmt 0 discriminator 5 view .LVU477
+ 1393 001e 0123     		movs	r3, #1
+ 1394 0020 80F83D30 		strb	r3, [r0, #61]
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1395              		.loc 1 454 3 is_stmt 1 discriminator 5 view .LVU478
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1396              		.loc 1 455 1 is_stmt 0 discriminator 5 view .LVU479
+ 1397 0024 0020     		movs	r0, #0
+ 1398              	.LVL141:
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1399              		.loc 1 455 1 discriminator 5 view .LVU480
+ 1400 0026 7047     		bx	lr
+ 1401              		.cfi_endproc
+ 1402              	.LFE146:
+ 1404              		.section	.text.HAL_TIM_Base_Start_IT,"ax",%progbits
+ 1405              		.align	1
+ 1406              		.global	HAL_TIM_Base_Start_IT
+ 1407              		.syntax unified
+ 1408              		.thumb
+ 1409              		.thumb_func
+ 1410              		.fpu fpv5-d16
+ 1412              	HAL_TIM_Base_Start_IT:
+ 1413              	.LVL142:
+ 1414              	.LFB147:
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 1415              		.loc 1 463 1 is_stmt 1 view -0
+ 1416              		.cfi_startproc
+ 1417              		@ args = 0, pretend = 0, frame = 0
+ 1418              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1419              		@ link register save eliminated.
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1420              		.loc 1 464 3 view .LVU482
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1421              		.loc 1 467 3 view .LVU483
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1422              		.loc 1 470 3 view .LVU484
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1423              		.loc 1 470 11 is_stmt 0 view .LVU485
+ 1424 0000 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+ 1425 0004 DBB2     		uxtb	r3, r3
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1426              		.loc 1 470 6 view .LVU486
+ 1427 0006 012B     		cmp	r3, #1
+ 1428 0008 3AD1     		bne	.L58
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1429              		.loc 1 476 3 is_stmt 1 view .LVU487
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1430              		.loc 1 476 15 is_stmt 0 view .LVU488
+ 1431 000a 0223     		movs	r3, #2
+ 1432 000c 80F83D30 		strb	r3, [r0, #61]
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1433              		.loc 1 479 3 is_stmt 1 view .LVU489
+ 1434 0010 0268     		ldr	r2, [r0]
+ 1435 0012 D368     		ldr	r3, [r2, #12]
+ 1436 0014 43F00103 		orr	r3, r3, #1
+ARM GAS  /tmp/ccPLZXyC.s 			page 164
+
+
+ 1437 0018 D360     		str	r3, [r2, #12]
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1438              		.loc 1 482 3 view .LVU490
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1439              		.loc 1 482 7 is_stmt 0 view .LVU491
+ 1440 001a 0368     		ldr	r3, [r0]
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1441              		.loc 1 482 6 view .LVU492
+ 1442 001c 1A4A     		ldr	r2, .L60
+ 1443 001e B3F1804F 		cmp	r3, #1073741824
+ 1444 0022 18BF     		it	ne
+ 1445 0024 9342     		cmpne	r3, r2
+ 1446 0026 1DD0     		beq	.L56
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1447              		.loc 1 482 7 discriminator 1 view .LVU493
+ 1448 0028 A2F57C42 		sub	r2, r2, #64512
+ 1449 002c 9342     		cmp	r3, r2
+ 1450 002e 19D0     		beq	.L56
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1451              		.loc 1 482 7 discriminator 2 view .LVU494
+ 1452 0030 02F58062 		add	r2, r2, #1024
+ 1453 0034 9342     		cmp	r3, r2
+ 1454 0036 15D0     		beq	.L56
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1455              		.loc 1 482 7 discriminator 3 view .LVU495
+ 1456 0038 02F58062 		add	r2, r2, #1024
+ 1457 003c 9342     		cmp	r3, r2
+ 1458 003e 11D0     		beq	.L56
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1459              		.loc 1 482 7 discriminator 4 view .LVU496
+ 1460 0040 02F57842 		add	r2, r2, #63488
+ 1461 0044 9342     		cmp	r3, r2
+ 1462 0046 0DD0     		beq	.L56
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1463              		.loc 1 482 7 discriminator 5 view .LVU497
+ 1464 0048 02F57052 		add	r2, r2, #15360
+ 1465 004c 9342     		cmp	r3, r2
+ 1466 004e 09D0     		beq	.L56
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1467              		.loc 1 482 7 discriminator 6 view .LVU498
+ 1468 0050 A2F59432 		sub	r2, r2, #75776
+ 1469 0054 9342     		cmp	r3, r2
+ 1470 0056 05D0     		beq	.L56
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 1471              		.loc 1 492 5 is_stmt 1 view .LVU499
+ 1472 0058 1A68     		ldr	r2, [r3]
+ 1473 005a 42F00102 		orr	r2, r2, #1
+ 1474 005e 1A60     		str	r2, [r3]
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1475              		.loc 1 496 10 is_stmt 0 view .LVU500
+ 1476 0060 0020     		movs	r0, #0
+ 1477              	.LVL143:
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1478              		.loc 1 496 10 view .LVU501
+ 1479 0062 7047     		bx	lr
+ 1480              	.LVL144:
+ 1481              	.L56:
+ARM GAS  /tmp/ccPLZXyC.s 			page 165
+
+
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1482              		.loc 1 484 5 is_stmt 1 view .LVU502
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1483              		.loc 1 484 29 is_stmt 0 view .LVU503
+ 1484 0064 9968     		ldr	r1, [r3, #8]
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1485              		.loc 1 484 13 view .LVU504
+ 1486 0066 094A     		ldr	r2, .L60+4
+ 1487 0068 0A40     		ands	r2, r2, r1
+ 1488              	.LVL145:
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 1489              		.loc 1 485 5 is_stmt 1 view .LVU505
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 1490              		.loc 1 485 8 is_stmt 0 view .LVU506
+ 1491 006a 062A     		cmp	r2, #6
+ 1492 006c 18BF     		it	ne
+ 1493 006e B2F5803F 		cmpne	r2, #65536
+ 1494 0072 07D0     		beq	.L59
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 1495              		.loc 1 487 7 is_stmt 1 view .LVU507
+ 1496 0074 1A68     		ldr	r2, [r3]
+ 1497              	.LVL146:
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 1498              		.loc 1 487 7 is_stmt 0 view .LVU508
+ 1499 0076 42F00102 		orr	r2, r2, #1
+ 1500 007a 1A60     		str	r2, [r3]
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1501              		.loc 1 496 10 view .LVU509
+ 1502 007c 0020     		movs	r0, #0
+ 1503              	.LVL147:
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1504              		.loc 1 496 10 view .LVU510
+ 1505 007e 7047     		bx	lr
+ 1506              	.LVL148:
+ 1507              	.L58:
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 1508              		.loc 1 472 12 view .LVU511
+ 1509 0080 0120     		movs	r0, #1
+ 1510              	.LVL149:
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 1511              		.loc 1 472 12 view .LVU512
+ 1512 0082 7047     		bx	lr
+ 1513              	.LVL150:
+ 1514              	.L59:
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1515              		.loc 1 496 10 view .LVU513
+ 1516 0084 0020     		movs	r0, #0
+ 1517              	.LVL151:
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1518              		.loc 1 497 1 view .LVU514
+ 1519 0086 7047     		bx	lr
+ 1520              	.L61:
+ 1521              		.align	2
+ 1522              	.L60:
+ 1523 0088 00000140 		.word	1073807360
+ 1524 008c 07000100 		.word	65543
+ 1525              		.cfi_endproc
+ARM GAS  /tmp/ccPLZXyC.s 			page 166
+
+
+ 1526              	.LFE147:
+ 1528              		.section	.text.HAL_TIM_Base_Stop_IT,"ax",%progbits
+ 1529              		.align	1
+ 1530              		.global	HAL_TIM_Base_Stop_IT
+ 1531              		.syntax unified
+ 1532              		.thumb
+ 1533              		.thumb_func
+ 1534              		.fpu fpv5-d16
+ 1536              	HAL_TIM_Base_Stop_IT:
+ 1537              	.LVL152:
+ 1538              	.LFB148:
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 1539              		.loc 1 505 1 is_stmt 1 view -0
+ 1540              		.cfi_startproc
+ 1541              		@ args = 0, pretend = 0, frame = 0
+ 1542              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1543              		@ link register save eliminated.
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1544              		.loc 1 507 3 view .LVU516
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1545              		.loc 1 510 3 view .LVU517
+ 1546 0000 0268     		ldr	r2, [r0]
+ 1547 0002 D368     		ldr	r3, [r2, #12]
+ 1548 0004 23F00103 		bic	r3, r3, #1
+ 1549 0008 D360     		str	r3, [r2, #12]
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1550              		.loc 1 513 3 view .LVU518
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1551              		.loc 1 513 3 view .LVU519
+ 1552 000a 0368     		ldr	r3, [r0]
+ 1553 000c 196A     		ldr	r1, [r3, #32]
+ 1554 000e 41F21112 		movw	r2, #4369
+ 1555 0012 1142     		tst	r1, r2
+ 1556 0014 08D1     		bne	.L63
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1557              		.loc 1 513 3 discriminator 1 view .LVU520
+ 1558 0016 196A     		ldr	r1, [r3, #32]
+ 1559 0018 40F24442 		movw	r2, #1092
+ 1560 001c 1142     		tst	r1, r2
+ 1561 001e 03D1     		bne	.L63
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1562              		.loc 1 513 3 discriminator 3 view .LVU521
+ 1563 0020 1A68     		ldr	r2, [r3]
+ 1564 0022 22F00102 		bic	r2, r2, #1
+ 1565 0026 1A60     		str	r2, [r3]
+ 1566              	.L63:
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1567              		.loc 1 513 3 discriminator 5 view .LVU522
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1568              		.loc 1 516 3 discriminator 5 view .LVU523
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1569              		.loc 1 516 15 is_stmt 0 discriminator 5 view .LVU524
+ 1570 0028 0123     		movs	r3, #1
+ 1571 002a 80F83D30 		strb	r3, [r0, #61]
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1572              		.loc 1 519 3 is_stmt 1 discriminator 5 view .LVU525
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 167
+
+
+ 1573              		.loc 1 520 1 is_stmt 0 discriminator 5 view .LVU526
+ 1574 002e 0020     		movs	r0, #0
+ 1575              	.LVL153:
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1576              		.loc 1 520 1 discriminator 5 view .LVU527
+ 1577 0030 7047     		bx	lr
+ 1578              		.cfi_endproc
+ 1579              	.LFE148:
+ 1581              		.section	.text.HAL_TIM_Base_Start_DMA,"ax",%progbits
+ 1582              		.align	1
+ 1583              		.global	HAL_TIM_Base_Start_DMA
+ 1584              		.syntax unified
+ 1585              		.thumb
+ 1586              		.thumb_func
+ 1587              		.fpu fpv5-d16
+ 1589              	HAL_TIM_Base_Start_DMA:
+ 1590              	.LVL154:
+ 1591              	.LFB149:
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 1592              		.loc 1 530 1 is_stmt 1 view -0
+ 1593              		.cfi_startproc
+ 1594              		@ args = 0, pretend = 0, frame = 0
+ 1595              		@ frame_needed = 0, uses_anonymous_args = 0
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 1596              		.loc 1 530 1 is_stmt 0 view .LVU529
+ 1597 0000 38B5     		push	{r3, r4, r5, lr}
+ 1598              	.LCFI21:
+ 1599              		.cfi_def_cfa_offset 16
+ 1600              		.cfi_offset 3, -16
+ 1601              		.cfi_offset 4, -12
+ 1602              		.cfi_offset 5, -8
+ 1603              		.cfi_offset 14, -4
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1604              		.loc 1 531 3 is_stmt 1 view .LVU530
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1605              		.loc 1 534 3 view .LVU531
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1606              		.loc 1 537 3 view .LVU532
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1607              		.loc 1 537 11 is_stmt 0 view .LVU533
+ 1608 0002 90F83D40 		ldrb	r4, [r0, #61]	@ zero_extendqisi2
+ 1609 0006 E4B2     		uxtb	r4, r4
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1610              		.loc 1 537 6 view .LVU534
+ 1611 0008 022C     		cmp	r4, #2
+ 1612 000a 58D0     		beq	.L65
+ 1613 000c 0546     		mov	r5, r0
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1614              		.loc 1 541 8 is_stmt 1 view .LVU535
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1615              		.loc 1 541 16 is_stmt 0 view .LVU536
+ 1616 000e 90F83D40 		ldrb	r4, [r0, #61]	@ zero_extendqisi2
+ 1617 0012 E4B2     		uxtb	r4, r4
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1618              		.loc 1 541 11 view .LVU537
+ 1619 0014 012C     		cmp	r4, #1
+ 1620 0016 51D1     		bne	.L68
+ARM GAS  /tmp/ccPLZXyC.s 			page 168
+
+
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 1621              		.loc 1 543 5 is_stmt 1 view .LVU538
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 1622              		.loc 1 543 8 is_stmt 0 view .LVU539
+ 1623 0018 002A     		cmp	r2, #0
+ 1624 001a 18BF     		it	ne
+ 1625 001c 0029     		cmpne	r1, #0
+ 1626 001e 4ED0     		beq	.L65
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 1627              		.loc 1 549 7 is_stmt 1 view .LVU540
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 1628              		.loc 1 549 19 is_stmt 0 view .LVU541
+ 1629 0020 0223     		movs	r3, #2
+ 1630 0022 80F83D30 		strb	r3, [r0, #61]
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 1631              		.loc 1 558 3 is_stmt 1 view .LVU542
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 1632              		.loc 1 558 13 is_stmt 0 view .LVU543
+ 1633 0026 036A     		ldr	r3, [r0, #32]
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 1634              		.loc 1 558 51 view .LVU544
+ 1635 0028 2748     		ldr	r0, .L71
+ 1636              	.LVL155:
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 1637              		.loc 1 558 51 view .LVU545
+ 1638 002a D863     		str	r0, [r3, #60]
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1639              		.loc 1 559 3 is_stmt 1 view .LVU546
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1640              		.loc 1 559 13 is_stmt 0 view .LVU547
+ 1641 002c 2B6A     		ldr	r3, [r5, #32]
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1642              		.loc 1 559 55 view .LVU548
+ 1643 002e 2748     		ldr	r0, .L71+4
+ 1644 0030 1864     		str	r0, [r3, #64]
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1645              		.loc 1 562 3 is_stmt 1 view .LVU549
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1646              		.loc 1 562 13 is_stmt 0 view .LVU550
+ 1647 0032 2B6A     		ldr	r3, [r5, #32]
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1648              		.loc 1 562 52 view .LVU551
+ 1649 0034 2648     		ldr	r0, .L71+8
+ 1650 0036 D864     		str	r0, [r3, #76]
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                        Length) != HAL_OK)
+ 1651              		.loc 1 565 3 is_stmt 1 view .LVU552
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                        Length) != HAL_OK)
+ 1652              		.loc 1 565 87 is_stmt 0 view .LVU553
+ 1653 0038 2868     		ldr	r0, [r5]
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                        Length) != HAL_OK)
+ 1654              		.loc 1 565 7 view .LVU554
+ 1655 003a 1346     		mov	r3, r2
+ 1656 003c 00F12C02 		add	r2, r0, #44
+ 1657              	.LVL156:
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                        Length) != HAL_OK)
+ 1658              		.loc 1 565 7 view .LVU555
+ 1659 0040 286A     		ldr	r0, [r5, #32]
+ARM GAS  /tmp/ccPLZXyC.s 			page 169
+
+
+ 1660 0042 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 1661              	.LVL157:
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                        Length) != HAL_OK)
+ 1662              		.loc 1 565 6 view .LVU556
+ 1663 0046 0146     		mov	r1, r0
+ 1664 0048 0028     		cmp	r0, #0
+ 1665 004a 38D1     		bne	.L65
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1666              		.loc 1 573 3 is_stmt 1 view .LVU557
+ 1667 004c 2A68     		ldr	r2, [r5]
+ 1668 004e D368     		ldr	r3, [r2, #12]
+ 1669 0050 43F48073 		orr	r3, r3, #256
+ 1670 0054 D360     		str	r3, [r2, #12]
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1671              		.loc 1 576 3 view .LVU558
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1672              		.loc 1 576 7 is_stmt 0 view .LVU559
+ 1673 0056 2B68     		ldr	r3, [r5]
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1674              		.loc 1 576 6 view .LVU560
+ 1675 0058 1E4A     		ldr	r2, .L71+12
+ 1676 005a B3F1804F 		cmp	r3, #1073741824
+ 1677 005e 18BF     		it	ne
+ 1678 0060 9342     		cmpne	r3, r2
+ 1679 0062 1DD0     		beq	.L66
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1680              		.loc 1 576 7 discriminator 1 view .LVU561
+ 1681 0064 A2F57C42 		sub	r2, r2, #64512
+ 1682 0068 9342     		cmp	r3, r2
+ 1683 006a 19D0     		beq	.L66
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1684              		.loc 1 576 7 discriminator 2 view .LVU562
+ 1685 006c 02F58062 		add	r2, r2, #1024
+ 1686 0070 9342     		cmp	r3, r2
+ 1687 0072 15D0     		beq	.L66
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1688              		.loc 1 576 7 discriminator 3 view .LVU563
+ 1689 0074 02F58062 		add	r2, r2, #1024
+ 1690 0078 9342     		cmp	r3, r2
+ 1691 007a 11D0     		beq	.L66
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1692              		.loc 1 576 7 discriminator 4 view .LVU564
+ 1693 007c 02F57842 		add	r2, r2, #63488
+ 1694 0080 9342     		cmp	r3, r2
+ 1695 0082 0DD0     		beq	.L66
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1696              		.loc 1 576 7 discriminator 5 view .LVU565
+ 1697 0084 02F57052 		add	r2, r2, #15360
+ 1698 0088 9342     		cmp	r3, r2
+ 1699 008a 09D0     		beq	.L66
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 1700              		.loc 1 576 7 discriminator 6 view .LVU566
+ 1701 008c A2F59432 		sub	r2, r2, #75776
+ 1702 0090 9342     		cmp	r3, r2
+ 1703 0092 05D0     		beq	.L66
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 1704              		.loc 1 586 5 is_stmt 1 view .LVU567
+ARM GAS  /tmp/ccPLZXyC.s 			page 170
+
+
+ 1705 0094 1A68     		ldr	r2, [r3]
+ 1706 0096 42F00102 		orr	r2, r2, #1
+ 1707 009a 1A60     		str	r2, [r3]
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1708              		.loc 1 590 10 is_stmt 0 view .LVU568
+ 1709 009c 0446     		mov	r4, r0
+ 1710 009e 0EE0     		b	.L65
+ 1711              	.L66:
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1712              		.loc 1 578 5 is_stmt 1 view .LVU569
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1713              		.loc 1 578 29 is_stmt 0 view .LVU570
+ 1714 00a0 9868     		ldr	r0, [r3, #8]
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1715              		.loc 1 578 13 view .LVU571
+ 1716 00a2 0D4A     		ldr	r2, .L71+16
+ 1717 00a4 0240     		ands	r2, r2, r0
+ 1718              	.LVL158:
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 1719              		.loc 1 579 5 is_stmt 1 view .LVU572
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 1720              		.loc 1 579 8 is_stmt 0 view .LVU573
+ 1721 00a6 062A     		cmp	r2, #6
+ 1722 00a8 18BF     		it	ne
+ 1723 00aa B2F5803F 		cmpne	r2, #65536
+ 1724 00ae 08D0     		beq	.L69
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 1725              		.loc 1 581 7 is_stmt 1 view .LVU574
+ 1726 00b0 1A68     		ldr	r2, [r3]
+ 1727              	.LVL159:
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 1728              		.loc 1 581 7 is_stmt 0 view .LVU575
+ 1729 00b2 42F00102 		orr	r2, r2, #1
+ 1730 00b6 1A60     		str	r2, [r3]
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1731              		.loc 1 590 10 view .LVU576
+ 1732 00b8 0C46     		mov	r4, r1
+ 1733 00ba 00E0     		b	.L65
+ 1734              	.LVL160:
+ 1735              	.L68:
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 1736              		.loc 1 554 12 view .LVU577
+ 1737 00bc 0124     		movs	r4, #1
+ 1738              	.LVL161:
+ 1739              	.L65:
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1740              		.loc 1 591 1 view .LVU578
+ 1741 00be 2046     		mov	r0, r4
+ 1742 00c0 38BD     		pop	{r3, r4, r5, pc}
+ 1743              	.LVL162:
+ 1744              	.L69:
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1745              		.loc 1 590 10 view .LVU579
+ 1746 00c2 0C46     		mov	r4, r1
+ 1747 00c4 FBE7     		b	.L65
+ 1748              	.L72:
+ 1749 00c6 00BF     		.align	2
+ARM GAS  /tmp/ccPLZXyC.s 			page 171
+
+
+ 1750              	.L71:
+ 1751 00c8 00000000 		.word	TIM_DMAPeriodElapsedCplt
+ 1752 00cc 00000000 		.word	TIM_DMAPeriodElapsedHalfCplt
+ 1753 00d0 00000000 		.word	TIM_DMAError
+ 1754 00d4 00000140 		.word	1073807360
+ 1755 00d8 07000100 		.word	65543
+ 1756              		.cfi_endproc
+ 1757              	.LFE149:
+ 1759              		.section	.text.HAL_TIM_Base_Stop_DMA,"ax",%progbits
+ 1760              		.align	1
+ 1761              		.global	HAL_TIM_Base_Stop_DMA
+ 1762              		.syntax unified
+ 1763              		.thumb
+ 1764              		.thumb_func
+ 1765              		.fpu fpv5-d16
+ 1767              	HAL_TIM_Base_Stop_DMA:
+ 1768              	.LVL163:
+ 1769              	.LFB150:
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 1770              		.loc 1 599 1 is_stmt 1 view -0
+ 1771              		.cfi_startproc
+ 1772              		@ args = 0, pretend = 0, frame = 0
+ 1773              		@ frame_needed = 0, uses_anonymous_args = 0
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 1774              		.loc 1 599 1 is_stmt 0 view .LVU581
+ 1775 0000 10B5     		push	{r4, lr}
+ 1776              	.LCFI22:
+ 1777              		.cfi_def_cfa_offset 8
+ 1778              		.cfi_offset 4, -8
+ 1779              		.cfi_offset 14, -4
+ 1780 0002 0446     		mov	r4, r0
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1781              		.loc 1 601 3 is_stmt 1 view .LVU582
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1782              		.loc 1 604 3 view .LVU583
+ 1783 0004 0268     		ldr	r2, [r0]
+ 1784 0006 D368     		ldr	r3, [r2, #12]
+ 1785 0008 23F48073 		bic	r3, r3, #256
+ 1786 000c D360     		str	r3, [r2, #12]
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1787              		.loc 1 606 3 view .LVU584
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1788              		.loc 1 606 9 is_stmt 0 view .LVU585
+ 1789 000e 006A     		ldr	r0, [r0, #32]
+ 1790              	.LVL164:
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1791              		.loc 1 606 9 view .LVU586
+ 1792 0010 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 1793              	.LVL165:
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1794              		.loc 1 609 3 is_stmt 1 view .LVU587
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1795              		.loc 1 609 3 view .LVU588
+ 1796 0014 2368     		ldr	r3, [r4]
+ 1797 0016 196A     		ldr	r1, [r3, #32]
+ 1798 0018 41F21112 		movw	r2, #4369
+ 1799 001c 1142     		tst	r1, r2
+ARM GAS  /tmp/ccPLZXyC.s 			page 172
+
+
+ 1800 001e 08D1     		bne	.L74
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1801              		.loc 1 609 3 discriminator 1 view .LVU589
+ 1802 0020 196A     		ldr	r1, [r3, #32]
+ 1803 0022 40F24442 		movw	r2, #1092
+ 1804 0026 1142     		tst	r1, r2
+ 1805 0028 03D1     		bne	.L74
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1806              		.loc 1 609 3 discriminator 3 view .LVU590
+ 1807 002a 1A68     		ldr	r2, [r3]
+ 1808 002c 22F00102 		bic	r2, r2, #1
+ 1809 0030 1A60     		str	r2, [r3]
+ 1810              	.L74:
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1811              		.loc 1 609 3 discriminator 5 view .LVU591
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1812              		.loc 1 612 3 discriminator 5 view .LVU592
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1813              		.loc 1 612 15 is_stmt 0 discriminator 5 view .LVU593
+ 1814 0032 0123     		movs	r3, #1
+ 1815 0034 84F83D30 		strb	r3, [r4, #61]
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1816              		.loc 1 615 3 is_stmt 1 discriminator 5 view .LVU594
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1817              		.loc 1 616 1 is_stmt 0 discriminator 5 view .LVU595
+ 1818 0038 0020     		movs	r0, #0
+ 1819 003a 10BD     		pop	{r4, pc}
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1820              		.loc 1 616 1 discriminator 5 view .LVU596
+ 1821              		.cfi_endproc
+ 1822              	.LFE150:
+ 1824              		.section	.text.HAL_TIM_OC_MspInit,"ax",%progbits
+ 1825              		.align	1
+ 1826              		.weak	HAL_TIM_OC_MspInit
+ 1827              		.syntax unified
+ 1828              		.thumb
+ 1829              		.thumb_func
+ 1830              		.fpu fpv5-d16
+ 1832              	HAL_TIM_OC_MspInit:
+ 1833              	.LVL166:
+ 1834              	.LFB153:
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 1835              		.loc 1 757 1 is_stmt 1 view -0
+ 1836              		.cfi_startproc
+ 1837              		@ args = 0, pretend = 0, frame = 0
+ 1838              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1839              		@ link register save eliminated.
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1840              		.loc 1 759 3 view .LVU598
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1841              		.loc 1 764 1 is_stmt 0 view .LVU599
+ 1842 0000 7047     		bx	lr
+ 1843              		.cfi_endproc
+ 1844              	.LFE153:
+ 1846              		.section	.text.HAL_TIM_OC_MspDeInit,"ax",%progbits
+ 1847              		.align	1
+ 1848              		.weak	HAL_TIM_OC_MspDeInit
+ARM GAS  /tmp/ccPLZXyC.s 			page 173
+
+
+ 1849              		.syntax unified
+ 1850              		.thumb
+ 1851              		.thumb_func
+ 1852              		.fpu fpv5-d16
+ 1854              	HAL_TIM_OC_MspDeInit:
+ 1855              	.LVL167:
+ 1856              	.LFB154:
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 1857              		.loc 1 772 1 is_stmt 1 view -0
+ 1858              		.cfi_startproc
+ 1859              		@ args = 0, pretend = 0, frame = 0
+ 1860              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1861              		@ link register save eliminated.
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1862              		.loc 1 774 3 view .LVU601
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1863              		.loc 1 779 1 is_stmt 0 view .LVU602
+ 1864 0000 7047     		bx	lr
+ 1865              		.cfi_endproc
+ 1866              	.LFE154:
+ 1868              		.section	.text.HAL_TIM_OC_DeInit,"ax",%progbits
+ 1869              		.align	1
+ 1870              		.global	HAL_TIM_OC_DeInit
+ 1871              		.syntax unified
+ 1872              		.thumb
+ 1873              		.thumb_func
+ 1874              		.fpu fpv5-d16
+ 1876              	HAL_TIM_OC_DeInit:
+ 1877              	.LVL168:
+ 1878              	.LFB152:
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 1879              		.loc 1 714 1 is_stmt 1 view -0
+ 1880              		.cfi_startproc
+ 1881              		@ args = 0, pretend = 0, frame = 0
+ 1882              		@ frame_needed = 0, uses_anonymous_args = 0
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 1883              		.loc 1 714 1 is_stmt 0 view .LVU604
+ 1884 0000 10B5     		push	{r4, lr}
+ 1885              	.LCFI23:
+ 1886              		.cfi_def_cfa_offset 8
+ 1887              		.cfi_offset 4, -8
+ 1888              		.cfi_offset 14, -4
+ 1889 0002 0446     		mov	r4, r0
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1890              		.loc 1 716 3 is_stmt 1 view .LVU605
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1891              		.loc 1 718 3 view .LVU606
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1892              		.loc 1 718 15 is_stmt 0 view .LVU607
+ 1893 0004 0223     		movs	r3, #2
+ 1894 0006 80F83D30 		strb	r3, [r0, #61]
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1895              		.loc 1 721 3 is_stmt 1 view .LVU608
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1896              		.loc 1 721 3 view .LVU609
+ 1897 000a 0368     		ldr	r3, [r0]
+ 1898 000c 196A     		ldr	r1, [r3, #32]
+ARM GAS  /tmp/ccPLZXyC.s 			page 174
+
+
+ 1899 000e 41F21112 		movw	r2, #4369
+ 1900 0012 1142     		tst	r1, r2
+ 1901 0014 08D1     		bne	.L79
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1902              		.loc 1 721 3 discriminator 1 view .LVU610
+ 1903 0016 196A     		ldr	r1, [r3, #32]
+ 1904 0018 40F24442 		movw	r2, #1092
+ 1905 001c 1142     		tst	r1, r2
+ 1906 001e 03D1     		bne	.L79
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1907              		.loc 1 721 3 discriminator 3 view .LVU611
+ 1908 0020 1A68     		ldr	r2, [r3]
+ 1909 0022 22F00102 		bic	r2, r2, #1
+ 1910 0026 1A60     		str	r2, [r3]
+ 1911              	.L79:
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1912              		.loc 1 721 3 discriminator 5 view .LVU612
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 1913              		.loc 1 732 3 discriminator 5 view .LVU613
+ 1914 0028 2046     		mov	r0, r4
+ 1915              	.LVL169:
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 1916              		.loc 1 732 3 is_stmt 0 discriminator 5 view .LVU614
+ 1917 002a FFF7FEFF 		bl	HAL_TIM_OC_MspDeInit
+ 1918              	.LVL170:
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1919              		.loc 1 736 3 is_stmt 1 discriminator 5 view .LVU615
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1920              		.loc 1 736 23 is_stmt 0 discriminator 5 view .LVU616
+ 1921 002e 0020     		movs	r0, #0
+ 1922 0030 84F84800 		strb	r0, [r4, #72]
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1923              		.loc 1 739 3 is_stmt 1 discriminator 5 view .LVU617
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1924              		.loc 1 739 3 discriminator 5 view .LVU618
+ 1925 0034 84F83E00 		strb	r0, [r4, #62]
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1926              		.loc 1 739 3 discriminator 5 view .LVU619
+ 1927 0038 84F83F00 		strb	r0, [r4, #63]
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1928              		.loc 1 739 3 discriminator 5 view .LVU620
+ 1929 003c 84F84000 		strb	r0, [r4, #64]
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1930              		.loc 1 739 3 discriminator 5 view .LVU621
+ 1931 0040 84F84100 		strb	r0, [r4, #65]
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1932              		.loc 1 739 3 discriminator 5 view .LVU622
+ 1933 0044 84F84200 		strb	r0, [r4, #66]
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1934              		.loc 1 739 3 discriminator 5 view .LVU623
+ 1935 0048 84F84300 		strb	r0, [r4, #67]
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 1936              		.loc 1 739 3 discriminator 5 view .LVU624
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1937              		.loc 1 740 3 discriminator 5 view .LVU625
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1938              		.loc 1 740 3 discriminator 5 view .LVU626
+ARM GAS  /tmp/ccPLZXyC.s 			page 175
+
+
+ 1939 004c 84F84400 		strb	r0, [r4, #68]
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1940              		.loc 1 740 3 discriminator 5 view .LVU627
+ 1941 0050 84F84500 		strb	r0, [r4, #69]
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1942              		.loc 1 740 3 discriminator 5 view .LVU628
+ 1943 0054 84F84600 		strb	r0, [r4, #70]
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1944              		.loc 1 740 3 discriminator 5 view .LVU629
+ 1945 0058 84F84700 		strb	r0, [r4, #71]
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1946              		.loc 1 740 3 discriminator 5 view .LVU630
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1947              		.loc 1 743 3 discriminator 5 view .LVU631
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1948              		.loc 1 743 15 is_stmt 0 discriminator 5 view .LVU632
+ 1949 005c 84F83D00 		strb	r0, [r4, #61]
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1950              		.loc 1 746 3 is_stmt 1 discriminator 5 view .LVU633
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1951              		.loc 1 746 3 discriminator 5 view .LVU634
+ 1952 0060 84F83C00 		strb	r0, [r4, #60]
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1953              		.loc 1 746 3 discriminator 5 view .LVU635
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 1954              		.loc 1 748 3 discriminator 5 view .LVU636
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1955              		.loc 1 749 1 is_stmt 0 discriminator 5 view .LVU637
+ 1956 0064 10BD     		pop	{r4, pc}
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1957              		.loc 1 749 1 discriminator 5 view .LVU638
+ 1958              		.cfi_endproc
+ 1959              	.LFE152:
+ 1961              		.section	.text.HAL_TIM_PWM_MspInit,"ax",%progbits
+ 1962              		.align	1
+ 1963              		.weak	HAL_TIM_PWM_MspInit
+ 1964              		.syntax unified
+ 1965              		.thumb
+ 1966              		.thumb_func
+ 1967              		.fpu fpv5-d16
+ 1969              	HAL_TIM_PWM_MspInit:
+ 1970              	.LVL171:
+ 1971              	.LFB163:
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 1972              		.loc 1 1426 1 is_stmt 1 view -0
+ 1973              		.cfi_startproc
+ 1974              		@ args = 0, pretend = 0, frame = 0
+ 1975              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1976              		@ link register save eliminated.
+1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1977              		.loc 1 1428 3 view .LVU640
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1978              		.loc 1 1433 1 is_stmt 0 view .LVU641
+ 1979 0000 7047     		bx	lr
+ 1980              		.cfi_endproc
+ 1981              	.LFE163:
+ 1983              		.section	.text.HAL_TIM_PWM_MspDeInit,"ax",%progbits
+ARM GAS  /tmp/ccPLZXyC.s 			page 176
+
+
+ 1984              		.align	1
+ 1985              		.weak	HAL_TIM_PWM_MspDeInit
+ 1986              		.syntax unified
+ 1987              		.thumb
+ 1988              		.thumb_func
+ 1989              		.fpu fpv5-d16
+ 1991              	HAL_TIM_PWM_MspDeInit:
+ 1992              	.LVL172:
+ 1993              	.LFB164:
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 1994              		.loc 1 1441 1 is_stmt 1 view -0
+ 1995              		.cfi_startproc
+ 1996              		@ args = 0, pretend = 0, frame = 0
+ 1997              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1998              		@ link register save eliminated.
+1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 1999              		.loc 1 1443 3 view .LVU643
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2000              		.loc 1 1448 1 is_stmt 0 view .LVU644
+ 2001 0000 7047     		bx	lr
+ 2002              		.cfi_endproc
+ 2003              	.LFE164:
+ 2005              		.section	.text.HAL_TIM_PWM_DeInit,"ax",%progbits
+ 2006              		.align	1
+ 2007              		.global	HAL_TIM_PWM_DeInit
+ 2008              		.syntax unified
+ 2009              		.thumb
+ 2010              		.thumb_func
+ 2011              		.fpu fpv5-d16
+ 2013              	HAL_TIM_PWM_DeInit:
+ 2014              	.LVL173:
+ 2015              	.LFB162:
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 2016              		.loc 1 1383 1 is_stmt 1 view -0
+ 2017              		.cfi_startproc
+ 2018              		@ args = 0, pretend = 0, frame = 0
+ 2019              		@ frame_needed = 0, uses_anonymous_args = 0
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 2020              		.loc 1 1383 1 is_stmt 0 view .LVU646
+ 2021 0000 10B5     		push	{r4, lr}
+ 2022              	.LCFI24:
+ 2023              		.cfi_def_cfa_offset 8
+ 2024              		.cfi_offset 4, -8
+ 2025              		.cfi_offset 14, -4
+ 2026 0002 0446     		mov	r4, r0
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2027              		.loc 1 1385 3 is_stmt 1 view .LVU647
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2028              		.loc 1 1387 3 view .LVU648
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2029              		.loc 1 1387 15 is_stmt 0 view .LVU649
+ 2030 0004 0223     		movs	r3, #2
+ 2031 0006 80F83D30 		strb	r3, [r0, #61]
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2032              		.loc 1 1390 3 is_stmt 1 view .LVU650
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2033              		.loc 1 1390 3 view .LVU651
+ARM GAS  /tmp/ccPLZXyC.s 			page 177
+
+
+ 2034 000a 0368     		ldr	r3, [r0]
+ 2035 000c 196A     		ldr	r1, [r3, #32]
+ 2036 000e 41F21112 		movw	r2, #4369
+ 2037 0012 1142     		tst	r1, r2
+ 2038 0014 08D1     		bne	.L84
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2039              		.loc 1 1390 3 discriminator 1 view .LVU652
+ 2040 0016 196A     		ldr	r1, [r3, #32]
+ 2041 0018 40F24442 		movw	r2, #1092
+ 2042 001c 1142     		tst	r1, r2
+ 2043 001e 03D1     		bne	.L84
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2044              		.loc 1 1390 3 discriminator 3 view .LVU653
+ 2045 0020 1A68     		ldr	r2, [r3]
+ 2046 0022 22F00102 		bic	r2, r2, #1
+ 2047 0026 1A60     		str	r2, [r3]
+ 2048              	.L84:
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2049              		.loc 1 1390 3 discriminator 5 view .LVU654
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2050              		.loc 1 1401 3 discriminator 5 view .LVU655
+ 2051 0028 2046     		mov	r0, r4
+ 2052              	.LVL174:
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2053              		.loc 1 1401 3 is_stmt 0 discriminator 5 view .LVU656
+ 2054 002a FFF7FEFF 		bl	HAL_TIM_PWM_MspDeInit
+ 2055              	.LVL175:
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2056              		.loc 1 1405 3 is_stmt 1 discriminator 5 view .LVU657
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2057              		.loc 1 1405 23 is_stmt 0 discriminator 5 view .LVU658
+ 2058 002e 0020     		movs	r0, #0
+ 2059 0030 84F84800 		strb	r0, [r4, #72]
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2060              		.loc 1 1408 3 is_stmt 1 discriminator 5 view .LVU659
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2061              		.loc 1 1408 3 discriminator 5 view .LVU660
+ 2062 0034 84F83E00 		strb	r0, [r4, #62]
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2063              		.loc 1 1408 3 discriminator 5 view .LVU661
+ 2064 0038 84F83F00 		strb	r0, [r4, #63]
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2065              		.loc 1 1408 3 discriminator 5 view .LVU662
+ 2066 003c 84F84000 		strb	r0, [r4, #64]
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2067              		.loc 1 1408 3 discriminator 5 view .LVU663
+ 2068 0040 84F84100 		strb	r0, [r4, #65]
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2069              		.loc 1 1408 3 discriminator 5 view .LVU664
+ 2070 0044 84F84200 		strb	r0, [r4, #66]
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2071              		.loc 1 1408 3 discriminator 5 view .LVU665
+ 2072 0048 84F84300 		strb	r0, [r4, #67]
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2073              		.loc 1 1408 3 discriminator 5 view .LVU666
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2074              		.loc 1 1409 3 discriminator 5 view .LVU667
+ARM GAS  /tmp/ccPLZXyC.s 			page 178
+
+
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2075              		.loc 1 1409 3 discriminator 5 view .LVU668
+ 2076 004c 84F84400 		strb	r0, [r4, #68]
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2077              		.loc 1 1409 3 discriminator 5 view .LVU669
+ 2078 0050 84F84500 		strb	r0, [r4, #69]
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2079              		.loc 1 1409 3 discriminator 5 view .LVU670
+ 2080 0054 84F84600 		strb	r0, [r4, #70]
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2081              		.loc 1 1409 3 discriminator 5 view .LVU671
+ 2082 0058 84F84700 		strb	r0, [r4, #71]
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2083              		.loc 1 1409 3 discriminator 5 view .LVU672
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2084              		.loc 1 1412 3 discriminator 5 view .LVU673
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2085              		.loc 1 1412 15 is_stmt 0 discriminator 5 view .LVU674
+ 2086 005c 84F83D00 		strb	r0, [r4, #61]
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2087              		.loc 1 1415 3 is_stmt 1 discriminator 5 view .LVU675
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2088              		.loc 1 1415 3 discriminator 5 view .LVU676
+ 2089 0060 84F83C00 		strb	r0, [r4, #60]
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2090              		.loc 1 1415 3 discriminator 5 view .LVU677
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 2091              		.loc 1 1417 3 discriminator 5 view .LVU678
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2092              		.loc 1 1418 1 is_stmt 0 discriminator 5 view .LVU679
+ 2093 0064 10BD     		pop	{r4, pc}
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2094              		.loc 1 1418 1 discriminator 5 view .LVU680
+ 2095              		.cfi_endproc
+ 2096              	.LFE162:
+ 2098              		.section	.text.HAL_TIM_IC_MspInit,"ax",%progbits
+ 2099              		.align	1
+ 2100              		.weak	HAL_TIM_IC_MspInit
+ 2101              		.syntax unified
+ 2102              		.thumb
+ 2103              		.thumb_func
+ 2104              		.fpu fpv5-d16
+ 2106              	HAL_TIM_IC_MspInit:
+ 2107              	.LVL176:
+ 2108              	.LFB173:
+2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2109              		.loc 1 2094 1 is_stmt 1 view -0
+ 2110              		.cfi_startproc
+ 2111              		@ args = 0, pretend = 0, frame = 0
+ 2112              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2113              		@ link register save eliminated.
+2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2114              		.loc 1 2096 3 view .LVU682
+2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2115              		.loc 1 2101 1 is_stmt 0 view .LVU683
+ 2116 0000 7047     		bx	lr
+ 2117              		.cfi_endproc
+ARM GAS  /tmp/ccPLZXyC.s 			page 179
+
+
+ 2118              	.LFE173:
+ 2120              		.section	.text.HAL_TIM_IC_MspDeInit,"ax",%progbits
+ 2121              		.align	1
+ 2122              		.weak	HAL_TIM_IC_MspDeInit
+ 2123              		.syntax unified
+ 2124              		.thumb
+ 2125              		.thumb_func
+ 2126              		.fpu fpv5-d16
+ 2128              	HAL_TIM_IC_MspDeInit:
+ 2129              	.LVL177:
+ 2130              	.LFB174:
+2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2131              		.loc 1 2109 1 is_stmt 1 view -0
+ 2132              		.cfi_startproc
+ 2133              		@ args = 0, pretend = 0, frame = 0
+ 2134              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2135              		@ link register save eliminated.
+2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2136              		.loc 1 2111 3 view .LVU685
+2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2137              		.loc 1 2116 1 is_stmt 0 view .LVU686
+ 2138 0000 7047     		bx	lr
+ 2139              		.cfi_endproc
+ 2140              	.LFE174:
+ 2142              		.section	.text.HAL_TIM_IC_DeInit,"ax",%progbits
+ 2143              		.align	1
+ 2144              		.global	HAL_TIM_IC_DeInit
+ 2145              		.syntax unified
+ 2146              		.thumb
+ 2147              		.thumb_func
+ 2148              		.fpu fpv5-d16
+ 2150              	HAL_TIM_IC_DeInit:
+ 2151              	.LVL178:
+ 2152              	.LFB172:
+2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 2153              		.loc 1 2051 1 is_stmt 1 view -0
+ 2154              		.cfi_startproc
+ 2155              		@ args = 0, pretend = 0, frame = 0
+ 2156              		@ frame_needed = 0, uses_anonymous_args = 0
+2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 2157              		.loc 1 2051 1 is_stmt 0 view .LVU688
+ 2158 0000 10B5     		push	{r4, lr}
+ 2159              	.LCFI25:
+ 2160              		.cfi_def_cfa_offset 8
+ 2161              		.cfi_offset 4, -8
+ 2162              		.cfi_offset 14, -4
+ 2163 0002 0446     		mov	r4, r0
+2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2164              		.loc 1 2053 3 is_stmt 1 view .LVU689
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2165              		.loc 1 2055 3 view .LVU690
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2166              		.loc 1 2055 15 is_stmt 0 view .LVU691
+ 2167 0004 0223     		movs	r3, #2
+ 2168 0006 80F83D30 		strb	r3, [r0, #61]
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2169              		.loc 1 2058 3 is_stmt 1 view .LVU692
+ARM GAS  /tmp/ccPLZXyC.s 			page 180
+
+
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2170              		.loc 1 2058 3 view .LVU693
+ 2171 000a 0368     		ldr	r3, [r0]
+ 2172 000c 196A     		ldr	r1, [r3, #32]
+ 2173 000e 41F21112 		movw	r2, #4369
+ 2174 0012 1142     		tst	r1, r2
+ 2175 0014 08D1     		bne	.L89
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2176              		.loc 1 2058 3 discriminator 1 view .LVU694
+ 2177 0016 196A     		ldr	r1, [r3, #32]
+ 2178 0018 40F24442 		movw	r2, #1092
+ 2179 001c 1142     		tst	r1, r2
+ 2180 001e 03D1     		bne	.L89
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2181              		.loc 1 2058 3 discriminator 3 view .LVU695
+ 2182 0020 1A68     		ldr	r2, [r3]
+ 2183 0022 22F00102 		bic	r2, r2, #1
+ 2184 0026 1A60     		str	r2, [r3]
+ 2185              	.L89:
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2186              		.loc 1 2058 3 discriminator 5 view .LVU696
+2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2187              		.loc 1 2069 3 discriminator 5 view .LVU697
+ 2188 0028 2046     		mov	r0, r4
+ 2189              	.LVL179:
+2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2190              		.loc 1 2069 3 is_stmt 0 discriminator 5 view .LVU698
+ 2191 002a FFF7FEFF 		bl	HAL_TIM_IC_MspDeInit
+ 2192              	.LVL180:
+2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2193              		.loc 1 2073 3 is_stmt 1 discriminator 5 view .LVU699
+2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2194              		.loc 1 2073 23 is_stmt 0 discriminator 5 view .LVU700
+ 2195 002e 0020     		movs	r0, #0
+ 2196 0030 84F84800 		strb	r0, [r4, #72]
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2197              		.loc 1 2076 3 is_stmt 1 discriminator 5 view .LVU701
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2198              		.loc 1 2076 3 discriminator 5 view .LVU702
+ 2199 0034 84F83E00 		strb	r0, [r4, #62]
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2200              		.loc 1 2076 3 discriminator 5 view .LVU703
+ 2201 0038 84F83F00 		strb	r0, [r4, #63]
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2202              		.loc 1 2076 3 discriminator 5 view .LVU704
+ 2203 003c 84F84000 		strb	r0, [r4, #64]
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2204              		.loc 1 2076 3 discriminator 5 view .LVU705
+ 2205 0040 84F84100 		strb	r0, [r4, #65]
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2206              		.loc 1 2076 3 discriminator 5 view .LVU706
+ 2207 0044 84F84200 		strb	r0, [r4, #66]
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2208              		.loc 1 2076 3 discriminator 5 view .LVU707
+ 2209 0048 84F84300 		strb	r0, [r4, #67]
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ 2210              		.loc 1 2076 3 discriminator 5 view .LVU708
+ARM GAS  /tmp/ccPLZXyC.s 			page 181
+
+
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2211              		.loc 1 2077 3 discriminator 5 view .LVU709
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2212              		.loc 1 2077 3 discriminator 5 view .LVU710
+ 2213 004c 84F84400 		strb	r0, [r4, #68]
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2214              		.loc 1 2077 3 discriminator 5 view .LVU711
+ 2215 0050 84F84500 		strb	r0, [r4, #69]
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2216              		.loc 1 2077 3 discriminator 5 view .LVU712
+ 2217 0054 84F84600 		strb	r0, [r4, #70]
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2218              		.loc 1 2077 3 discriminator 5 view .LVU713
+ 2219 0058 84F84700 		strb	r0, [r4, #71]
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2220              		.loc 1 2077 3 discriminator 5 view .LVU714
+2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2221              		.loc 1 2080 3 discriminator 5 view .LVU715
+2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2222              		.loc 1 2080 15 is_stmt 0 discriminator 5 view .LVU716
+ 2223 005c 84F83D00 		strb	r0, [r4, #61]
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2224              		.loc 1 2083 3 is_stmt 1 discriminator 5 view .LVU717
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2225              		.loc 1 2083 3 discriminator 5 view .LVU718
+ 2226 0060 84F83C00 		strb	r0, [r4, #60]
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2227              		.loc 1 2083 3 discriminator 5 view .LVU719
+2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 2228              		.loc 1 2085 3 discriminator 5 view .LVU720
+2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2229              		.loc 1 2086 1 is_stmt 0 discriminator 5 view .LVU721
+ 2230 0064 10BD     		pop	{r4, pc}
+2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2231              		.loc 1 2086 1 discriminator 5 view .LVU722
+ 2232              		.cfi_endproc
+ 2233              	.LFE172:
+ 2235              		.section	.text.HAL_TIM_OnePulse_MspInit,"ax",%progbits
+ 2236              		.align	1
+ 2237              		.weak	HAL_TIM_OnePulse_MspInit
+ 2238              		.syntax unified
+ 2239              		.thumb
+ 2240              		.thumb_func
+ 2241              		.fpu fpv5-d16
+ 2243              	HAL_TIM_OnePulse_MspInit:
+ 2244              	.LVL181:
+ 2245              	.LFB183:
+2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2246              		.loc 1 2754 1 is_stmt 1 view -0
+ 2247              		.cfi_startproc
+ 2248              		@ args = 0, pretend = 0, frame = 0
+ 2249              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2250              		@ link register save eliminated.
+2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2251              		.loc 1 2756 3 view .LVU724
+2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2252              		.loc 1 2761 1 is_stmt 0 view .LVU725
+ARM GAS  /tmp/ccPLZXyC.s 			page 182
+
+
+ 2253 0000 7047     		bx	lr
+ 2254              		.cfi_endproc
+ 2255              	.LFE183:
+ 2257              		.section	.text.HAL_TIM_OnePulse_MspDeInit,"ax",%progbits
+ 2258              		.align	1
+ 2259              		.weak	HAL_TIM_OnePulse_MspDeInit
+ 2260              		.syntax unified
+ 2261              		.thumb
+ 2262              		.thumb_func
+ 2263              		.fpu fpv5-d16
+ 2265              	HAL_TIM_OnePulse_MspDeInit:
+ 2266              	.LVL182:
+ 2267              	.LFB184:
+2769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2268              		.loc 1 2769 1 is_stmt 1 view -0
+ 2269              		.cfi_startproc
+ 2270              		@ args = 0, pretend = 0, frame = 0
+ 2271              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2272              		@ link register save eliminated.
+2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2273              		.loc 1 2771 3 view .LVU727
+2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2274              		.loc 1 2776 1 is_stmt 0 view .LVU728
+ 2275 0000 7047     		bx	lr
+ 2276              		.cfi_endproc
+ 2277              	.LFE184:
+ 2279              		.section	.text.HAL_TIM_OnePulse_DeInit,"ax",%progbits
+ 2280              		.align	1
+ 2281              		.global	HAL_TIM_OnePulse_DeInit
+ 2282              		.syntax unified
+ 2283              		.thumb
+ 2284              		.thumb_func
+ 2285              		.fpu fpv5-d16
+ 2287              	HAL_TIM_OnePulse_DeInit:
+ 2288              	.LVL183:
+ 2289              	.LFB182:
+2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 2290              		.loc 1 2709 1 is_stmt 1 view -0
+ 2291              		.cfi_startproc
+ 2292              		@ args = 0, pretend = 0, frame = 0
+ 2293              		@ frame_needed = 0, uses_anonymous_args = 0
+2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 2294              		.loc 1 2709 1 is_stmt 0 view .LVU730
+ 2295 0000 10B5     		push	{r4, lr}
+ 2296              	.LCFI26:
+ 2297              		.cfi_def_cfa_offset 8
+ 2298              		.cfi_offset 4, -8
+ 2299              		.cfi_offset 14, -4
+ 2300 0002 0446     		mov	r4, r0
+2711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2301              		.loc 1 2711 3 is_stmt 1 view .LVU731
+2713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2302              		.loc 1 2713 3 view .LVU732
+2713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2303              		.loc 1 2713 15 is_stmt 0 view .LVU733
+ 2304 0004 0223     		movs	r3, #2
+ 2305 0006 80F83D30 		strb	r3, [r0, #61]
+ARM GAS  /tmp/ccPLZXyC.s 			page 183
+
+
+2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2306              		.loc 1 2716 3 is_stmt 1 view .LVU734
+2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2307              		.loc 1 2716 3 view .LVU735
+ 2308 000a 0368     		ldr	r3, [r0]
+ 2309 000c 196A     		ldr	r1, [r3, #32]
+ 2310 000e 41F21112 		movw	r2, #4369
+ 2311 0012 1142     		tst	r1, r2
+ 2312 0014 08D1     		bne	.L94
+2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2313              		.loc 1 2716 3 discriminator 1 view .LVU736
+ 2314 0016 196A     		ldr	r1, [r3, #32]
+ 2315 0018 40F24442 		movw	r2, #1092
+ 2316 001c 1142     		tst	r1, r2
+ 2317 001e 03D1     		bne	.L94
+2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2318              		.loc 1 2716 3 discriminator 3 view .LVU737
+ 2319 0020 1A68     		ldr	r2, [r3]
+ 2320 0022 22F00102 		bic	r2, r2, #1
+ 2321 0026 1A60     		str	r2, [r3]
+ 2322              	.L94:
+2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2323              		.loc 1 2716 3 discriminator 5 view .LVU738
+2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2324              		.loc 1 2727 3 discriminator 5 view .LVU739
+ 2325 0028 2046     		mov	r0, r4
+ 2326              	.LVL184:
+2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2327              		.loc 1 2727 3 is_stmt 0 discriminator 5 view .LVU740
+ 2328 002a FFF7FEFF 		bl	HAL_TIM_OnePulse_MspDeInit
+ 2329              	.LVL185:
+2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2330              		.loc 1 2731 3 is_stmt 1 discriminator 5 view .LVU741
+2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2331              		.loc 1 2731 23 is_stmt 0 discriminator 5 view .LVU742
+ 2332 002e 0020     		movs	r0, #0
+ 2333 0030 84F84800 		strb	r0, [r4, #72]
+2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 2334              		.loc 1 2734 3 is_stmt 1 discriminator 5 view .LVU743
+ 2335 0034 84F83E00 		strb	r0, [r4, #62]
+2735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ 2336              		.loc 1 2735 3 discriminator 5 view .LVU744
+ 2337 0038 84F83F00 		strb	r0, [r4, #63]
+2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 2338              		.loc 1 2736 3 discriminator 5 view .LVU745
+ 2339 003c 84F84400 		strb	r0, [r4, #68]
+2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2340              		.loc 1 2737 3 discriminator 5 view .LVU746
+ 2341 0040 84F84500 		strb	r0, [r4, #69]
+2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2342              		.loc 1 2740 3 discriminator 5 view .LVU747
+2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2343              		.loc 1 2740 15 is_stmt 0 discriminator 5 view .LVU748
+ 2344 0044 84F83D00 		strb	r0, [r4, #61]
+2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2345              		.loc 1 2743 3 is_stmt 1 discriminator 5 view .LVU749
+2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 184
+
+
+ 2346              		.loc 1 2743 3 discriminator 5 view .LVU750
+ 2347 0048 84F83C00 		strb	r0, [r4, #60]
+2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2348              		.loc 1 2743 3 discriminator 5 view .LVU751
+2745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 2349              		.loc 1 2745 3 discriminator 5 view .LVU752
+2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2350              		.loc 1 2746 1 is_stmt 0 discriminator 5 view .LVU753
+ 2351 004c 10BD     		pop	{r4, pc}
+2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2352              		.loc 1 2746 1 discriminator 5 view .LVU754
+ 2353              		.cfi_endproc
+ 2354              	.LFE182:
+ 2356              		.section	.text.HAL_TIM_Encoder_MspInit,"ax",%progbits
+ 2357              		.align	1
+ 2358              		.weak	HAL_TIM_Encoder_MspInit
+ 2359              		.syntax unified
+ 2360              		.thumb
+ 2361              		.thumb_func
+ 2362              		.fpu fpv5-d16
+ 2364              	HAL_TIM_Encoder_MspInit:
+ 2365              	.LVL186:
+ 2366              	.LFB191:
+3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2367              		.loc 1 3191 1 is_stmt 1 view -0
+ 2368              		.cfi_startproc
+ 2369              		@ args = 0, pretend = 0, frame = 0
+ 2370              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2371              		@ link register save eliminated.
+3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2372              		.loc 1 3193 3 view .LVU756
+3198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2373              		.loc 1 3198 1 is_stmt 0 view .LVU757
+ 2374 0000 7047     		bx	lr
+ 2375              		.cfi_endproc
+ 2376              	.LFE191:
+ 2378              		.section	.text.HAL_TIM_Encoder_MspDeInit,"ax",%progbits
+ 2379              		.align	1
+ 2380              		.weak	HAL_TIM_Encoder_MspDeInit
+ 2381              		.syntax unified
+ 2382              		.thumb
+ 2383              		.thumb_func
+ 2384              		.fpu fpv5-d16
+ 2386              	HAL_TIM_Encoder_MspDeInit:
+ 2387              	.LVL187:
+ 2388              	.LFB192:
+3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 2389              		.loc 1 3206 1 is_stmt 1 view -0
+ 2390              		.cfi_startproc
+ 2391              		@ args = 0, pretend = 0, frame = 0
+ 2392              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2393              		@ link register save eliminated.
+3208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2394              		.loc 1 3208 3 view .LVU759
+3213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2395              		.loc 1 3213 1 is_stmt 0 view .LVU760
+ 2396 0000 7047     		bx	lr
+ARM GAS  /tmp/ccPLZXyC.s 			page 185
+
+
+ 2397              		.cfi_endproc
+ 2398              	.LFE192:
+ 2400              		.section	.text.HAL_TIM_Encoder_DeInit,"ax",%progbits
+ 2401              		.align	1
+ 2402              		.global	HAL_TIM_Encoder_DeInit
+ 2403              		.syntax unified
+ 2404              		.thumb
+ 2405              		.thumb_func
+ 2406              		.fpu fpv5-d16
+ 2408              	HAL_TIM_Encoder_DeInit:
+ 2409              	.LVL188:
+ 2410              	.LFB190:
+3146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 2411              		.loc 1 3146 1 is_stmt 1 view -0
+ 2412              		.cfi_startproc
+ 2413              		@ args = 0, pretend = 0, frame = 0
+ 2414              		@ frame_needed = 0, uses_anonymous_args = 0
+3146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 2415              		.loc 1 3146 1 is_stmt 0 view .LVU762
+ 2416 0000 10B5     		push	{r4, lr}
+ 2417              	.LCFI27:
+ 2418              		.cfi_def_cfa_offset 8
+ 2419              		.cfi_offset 4, -8
+ 2420              		.cfi_offset 14, -4
+ 2421 0002 0446     		mov	r4, r0
+3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2422              		.loc 1 3148 3 is_stmt 1 view .LVU763
+3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2423              		.loc 1 3150 3 view .LVU764
+3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2424              		.loc 1 3150 15 is_stmt 0 view .LVU765
+ 2425 0004 0223     		movs	r3, #2
+ 2426 0006 80F83D30 		strb	r3, [r0, #61]
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2427              		.loc 1 3153 3 is_stmt 1 view .LVU766
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2428              		.loc 1 3153 3 view .LVU767
+ 2429 000a 0368     		ldr	r3, [r0]
+ 2430 000c 196A     		ldr	r1, [r3, #32]
+ 2431 000e 41F21112 		movw	r2, #4369
+ 2432 0012 1142     		tst	r1, r2
+ 2433 0014 08D1     		bne	.L99
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2434              		.loc 1 3153 3 discriminator 1 view .LVU768
+ 2435 0016 196A     		ldr	r1, [r3, #32]
+ 2436 0018 40F24442 		movw	r2, #1092
+ 2437 001c 1142     		tst	r1, r2
+ 2438 001e 03D1     		bne	.L99
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2439              		.loc 1 3153 3 discriminator 3 view .LVU769
+ 2440 0020 1A68     		ldr	r2, [r3]
+ 2441 0022 22F00102 		bic	r2, r2, #1
+ 2442 0026 1A60     		str	r2, [r3]
+ 2443              	.L99:
+3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2444              		.loc 1 3153 3 discriminator 5 view .LVU770
+3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ARM GAS  /tmp/ccPLZXyC.s 			page 186
+
+
+ 2445              		.loc 1 3164 3 discriminator 5 view .LVU771
+ 2446 0028 2046     		mov	r0, r4
+ 2447              	.LVL189:
+3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 2448              		.loc 1 3164 3 is_stmt 0 discriminator 5 view .LVU772
+ 2449 002a FFF7FEFF 		bl	HAL_TIM_Encoder_MspDeInit
+ 2450              	.LVL190:
+3168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2451              		.loc 1 3168 3 is_stmt 1 discriminator 5 view .LVU773
+3168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2452              		.loc 1 3168 23 is_stmt 0 discriminator 5 view .LVU774
+ 2453 002e 0020     		movs	r0, #0
+ 2454 0030 84F84800 		strb	r0, [r4, #72]
+3171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 2455              		.loc 1 3171 3 is_stmt 1 discriminator 5 view .LVU775
+ 2456 0034 84F83E00 		strb	r0, [r4, #62]
+3172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ 2457              		.loc 1 3172 3 discriminator 5 view .LVU776
+ 2458 0038 84F83F00 		strb	r0, [r4, #63]
+3173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 2459              		.loc 1 3173 3 discriminator 5 view .LVU777
+ 2460 003c 84F84400 		strb	r0, [r4, #68]
+3174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2461              		.loc 1 3174 3 discriminator 5 view .LVU778
+ 2462 0040 84F84500 		strb	r0, [r4, #69]
+3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2463              		.loc 1 3177 3 discriminator 5 view .LVU779
+3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2464              		.loc 1 3177 15 is_stmt 0 discriminator 5 view .LVU780
+ 2465 0044 84F83D00 		strb	r0, [r4, #61]
+3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2466              		.loc 1 3180 3 is_stmt 1 discriminator 5 view .LVU781
+3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2467              		.loc 1 3180 3 discriminator 5 view .LVU782
+ 2468 0048 84F83C00 		strb	r0, [r4, #60]
+3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2469              		.loc 1 3180 3 discriminator 5 view .LVU783
+3182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 2470              		.loc 1 3182 3 discriminator 5 view .LVU784
+3183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2471              		.loc 1 3183 1 is_stmt 0 discriminator 5 view .LVU785
+ 2472 004c 10BD     		pop	{r4, pc}
+3183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2473              		.loc 1 3183 1 discriminator 5 view .LVU786
+ 2474              		.cfi_endproc
+ 2475              	.LFE190:
+ 2477              		.section	.text.HAL_TIM_DMABurst_MultiWriteStart,"ax",%progbits
+ 2478              		.align	1
+ 2479              		.global	HAL_TIM_DMABurst_MultiWriteStart
+ 2480              		.syntax unified
+ 2481              		.thumb
+ 2482              		.thumb_func
+ 2483              		.fpu fpv5-d16
+ 2485              	HAL_TIM_DMABurst_MultiWriteStart:
+ 2486              	.LVL191:
+ 2487              	.LFB205:
+4634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ARM GAS  /tmp/ccPLZXyC.s 			page 187
+
+
+ 2488              		.loc 1 4634 1 is_stmt 1 view -0
+ 2489              		.cfi_startproc
+ 2490              		@ args = 8, pretend = 0, frame = 0
+ 2491              		@ frame_needed = 0, uses_anonymous_args = 0
+4634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2492              		.loc 1 4634 1 is_stmt 0 view .LVU788
+ 2493 0000 70B5     		push	{r4, r5, r6, lr}
+ 2494              	.LCFI28:
+ 2495              		.cfi_def_cfa_offset 16
+ 2496              		.cfi_offset 4, -16
+ 2497              		.cfi_offset 5, -12
+ 2498              		.cfi_offset 6, -8
+ 2499              		.cfi_offset 14, -4
+ 2500 0002 0546     		mov	r5, r0
+ 2501 0004 1446     		mov	r4, r2
+4635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2502              		.loc 1 4635 3 is_stmt 1 view .LVU789
+ 2503              	.LVL192:
+4638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ 2504              		.loc 1 4638 3 view .LVU790
+4639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ 2505              		.loc 1 4639 3 view .LVU791
+4640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ 2506              		.loc 1 4640 3 view .LVU792
+4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+ 2507              		.loc 1 4641 3 view .LVU793
+4642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2508              		.loc 1 4642 3 view .LVU794
+4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2509              		.loc 1 4644 3 view .LVU795
+4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2510              		.loc 1 4644 11 is_stmt 0 view .LVU796
+ 2511 0006 90F84820 		ldrb	r2, [r0, #72]	@ zero_extendqisi2
+ 2512              	.LVL193:
+4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2513              		.loc 1 4644 11 view .LVU797
+ 2514 000a D0B2     		uxtb	r0, r2
+ 2515              	.LVL194:
+4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2516              		.loc 1 4644 6 view .LVU798
+ 2517 000c 0228     		cmp	r0, #2
+ 2518 000e 4CD0     		beq	.L102
+ 2519 0010 0E46     		mov	r6, r1
+ 2520 0012 1946     		mov	r1, r3
+ 2521              	.LVL195:
+4648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2522              		.loc 1 4648 8 is_stmt 1 view .LVU799
+4648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2523              		.loc 1 4648 16 is_stmt 0 view .LVU800
+ 2524 0014 95F84820 		ldrb	r2, [r5, #72]	@ zero_extendqisi2
+ 2525 0018 D0B2     		uxtb	r0, r2
+4648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2526              		.loc 1 4648 11 view .LVU801
+ 2527 001a 0128     		cmp	r0, #1
+ 2528 001c 1CD0     		beq	.L121
+ 2529              	.LVL196:
+ 2530              	.L103:
+ARM GAS  /tmp/ccPLZXyC.s 			page 188
+
+
+4662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2531              		.loc 1 4662 3 is_stmt 1 view .LVU802
+4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2532              		.loc 1 4664 3 view .LVU803
+ 2533 001e B4F5006F 		cmp	r4, #2048
+ 2534 0022 00F08980 		beq	.L104
+ 2535 0026 43D8     		bhi	.L105
+ 2536 0028 B4F5007F 		cmp	r4, #512
+ 2537 002c 71D0     		beq	.L106
+ 2538 002e B4F5806F 		cmp	r4, #1024
+ 2539 0032 1DD1     		bne	.L122
+4705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2540              		.loc 1 4705 7 view .LVU804
+4705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2541              		.loc 1 4705 17 is_stmt 0 view .LVU805
+ 2542 0034 AB6A     		ldr	r3, [r5, #40]
+4705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2543              		.loc 1 4705 52 view .LVU806
+ 2544 0036 544A     		ldr	r2, .L127
+ 2545 0038 DA63     		str	r2, [r3, #60]
+4706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2546              		.loc 1 4706 7 is_stmt 1 view .LVU807
+4706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2547              		.loc 1 4706 17 is_stmt 0 view .LVU808
+ 2548 003a AB6A     		ldr	r3, [r5, #40]
+4706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2549              		.loc 1 4706 56 view .LVU809
+ 2550 003c 534A     		ldr	r2, .L127+4
+ 2551 003e 1A64     		str	r2, [r3, #64]
+4709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2552              		.loc 1 4709 7 is_stmt 1 view .LVU810
+4709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2553              		.loc 1 4709 17 is_stmt 0 view .LVU811
+ 2554 0040 AB6A     		ldr	r3, [r5, #40]
+4709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2555              		.loc 1 4709 53 view .LVU812
+ 2556 0042 534A     		ldr	r2, .L127+8
+ 2557 0044 DA64     		str	r2, [r3, #76]
+4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2558              		.loc 1 4712 7 is_stmt 1 view .LVU813
+4713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 2559              		.loc 1 4713 43 is_stmt 0 view .LVU814
+ 2560 0046 2A68     		ldr	r2, [r5]
+4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2561              		.loc 1 4712 11 view .LVU815
+ 2562 0048 059B     		ldr	r3, [sp, #20]
+ 2563 004a 4C32     		adds	r2, r2, #76
+ 2564 004c A86A     		ldr	r0, [r5, #40]
+ 2565 004e FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2566              	.LVL197:
+4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2567              		.loc 1 4712 10 view .LVU816
+ 2568 0052 08B3     		cbz	r0, .L112
+4716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 2569              		.loc 1 4716 16 view .LVU817
+ 2570 0054 0120     		movs	r0, #1
+ 2571 0056 28E0     		b	.L102
+ARM GAS  /tmp/ccPLZXyC.s 			page 189
+
+
+ 2572              	.LVL198:
+ 2573              	.L121:
+4650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 2574              		.loc 1 4650 5 is_stmt 1 view .LVU818
+4650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 2575              		.loc 1 4650 31 is_stmt 0 view .LVU819
+ 2576 0058 049A     		ldr	r2, [sp, #16]
+ 2577 005a B3FA83F3 		clz	r3, r3
+ 2578 005e 5B09     		lsrs	r3, r3, #5
+ 2579 0060 002A     		cmp	r2, #0
+ 2580 0062 08BF     		it	eq
+ 2581 0064 0023     		moveq	r3, #0
+4650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 2582              		.loc 1 4650 8 view .LVU820
+ 2583 0066 03BB     		cbnz	r3, .L102
+4656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 2584              		.loc 1 4656 7 is_stmt 1 view .LVU821
+4656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 2585              		.loc 1 4656 27 is_stmt 0 view .LVU822
+ 2586 0068 0223     		movs	r3, #2
+ 2587 006a 85F84830 		strb	r3, [r5, #72]
+ 2588 006e D6E7     		b	.L103
+ 2589              	.L122:
+4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2590              		.loc 1 4664 3 view .LVU823
+ 2591 0070 B4F5807F 		cmp	r4, #256
+ 2592 0074 1AD1     		bne	.L123
+4669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 2593              		.loc 1 4669 7 is_stmt 1 view .LVU824
+4669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 2594              		.loc 1 4669 17 is_stmt 0 view .LVU825
+ 2595 0076 2B6A     		ldr	r3, [r5, #32]
+4669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 2596              		.loc 1 4669 55 view .LVU826
+ 2597 0078 464A     		ldr	r2, .L127+12
+ 2598 007a DA63     		str	r2, [r3, #60]
+4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2599              		.loc 1 4670 7 is_stmt 1 view .LVU827
+4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2600              		.loc 1 4670 17 is_stmt 0 view .LVU828
+ 2601 007c 2B6A     		ldr	r3, [r5, #32]
+4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2602              		.loc 1 4670 59 view .LVU829
+ 2603 007e 464A     		ldr	r2, .L127+16
+ 2604 0080 1A64     		str	r2, [r3, #64]
+4673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2605              		.loc 1 4673 7 is_stmt 1 view .LVU830
+4673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2606              		.loc 1 4673 17 is_stmt 0 view .LVU831
+ 2607 0082 2B6A     		ldr	r3, [r5, #32]
+4673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2608              		.loc 1 4673 56 view .LVU832
+ 2609 0084 424A     		ldr	r2, .L127+8
+ 2610 0086 DA64     		str	r2, [r3, #76]
+4676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2611              		.loc 1 4676 7 is_stmt 1 view .LVU833
+4677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ARM GAS  /tmp/ccPLZXyC.s 			page 190
+
+
+ 2612              		.loc 1 4677 43 is_stmt 0 view .LVU834
+ 2613 0088 2A68     		ldr	r2, [r5]
+4676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2614              		.loc 1 4676 11 view .LVU835
+ 2615 008a 059B     		ldr	r3, [sp, #20]
+ 2616 008c 4C32     		adds	r2, r2, #76
+ 2617 008e 286A     		ldr	r0, [r5, #32]
+ 2618 0090 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2619              	.LVL199:
+4676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2620              		.loc 1 4676 10 view .LVU836
+ 2621 0094 0028     		cmp	r0, #0
+ 2622 0096 75D1     		bne	.L124
+ 2623              	.L112:
+ 2624              	.LVL200:
+4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+ 2625              		.loc 1 4800 5 is_stmt 1 view .LVU837
+4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+ 2626              		.loc 1 4800 9 is_stmt 0 view .LVU838
+ 2627 0098 2B68     		ldr	r3, [r5]
+4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+ 2628              		.loc 1 4800 45 view .LVU839
+ 2629 009a 049A     		ldr	r2, [sp, #16]
+ 2630 009c 1643     		orrs	r6, r6, r2
+ 2631              	.LVL201:
+4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Enable the TIM DMA Request */
+ 2632              		.loc 1 4800 25 view .LVU840
+ 2633 009e 9E64     		str	r6, [r3, #72]
+4802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 2634              		.loc 1 4802 5 is_stmt 1 view .LVU841
+ 2635 00a0 2B68     		ldr	r3, [r5]
+ 2636 00a2 DA68     		ldr	r2, [r3, #12]
+ 2637 00a4 1443     		orrs	r4, r4, r2
+ 2638              	.LVL202:
+4802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 2639              		.loc 1 4802 5 is_stmt 0 view .LVU842
+ 2640 00a6 DC60     		str	r4, [r3, #12]
+ 2641 00a8 0020     		movs	r0, #0
+ 2642              	.L102:
+4807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2643              		.loc 1 4807 1 view .LVU843
+ 2644 00aa 70BD     		pop	{r4, r5, r6, pc}
+ 2645              	.LVL203:
+ 2646              	.L123:
+4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2647              		.loc 1 4664 3 view .LVU844
+ 2648 00ac 0120     		movs	r0, #1
+ 2649 00ae FCE7     		b	.L102
+ 2650              	.L105:
+4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2651              		.loc 1 4664 3 view .LVU845
+ 2652 00b0 B4F5005F 		cmp	r4, #8192
+ 2653 00b4 53D0     		beq	.L109
+ 2654 00b6 B4F5804F 		cmp	r4, #16384
+ 2655 00ba 12D1     		bne	.L125
+4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 2656              		.loc 1 4777 7 is_stmt 1 view .LVU846
+ARM GAS  /tmp/ccPLZXyC.s 			page 191
+
+
+4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 2657              		.loc 1 4777 17 is_stmt 0 view .LVU847
+ 2658 00bc AB6B     		ldr	r3, [r5, #56]
+4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 2659              		.loc 1 4777 56 view .LVU848
+ 2660 00be 374A     		ldr	r2, .L127+20
+ 2661 00c0 DA63     		str	r2, [r3, #60]
+4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2662              		.loc 1 4778 7 is_stmt 1 view .LVU849
+4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2663              		.loc 1 4778 17 is_stmt 0 view .LVU850
+ 2664 00c2 AB6B     		ldr	r3, [r5, #56]
+4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2665              		.loc 1 4778 60 view .LVU851
+ 2666 00c4 364A     		ldr	r2, .L127+24
+ 2667 00c6 1A64     		str	r2, [r3, #64]
+4781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2668              		.loc 1 4781 7 is_stmt 1 view .LVU852
+4781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2669              		.loc 1 4781 17 is_stmt 0 view .LVU853
+ 2670 00c8 AB6B     		ldr	r3, [r5, #56]
+4781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2671              		.loc 1 4781 57 view .LVU854
+ 2672 00ca 314A     		ldr	r2, .L127+8
+ 2673 00cc DA64     		str	r2, [r3, #76]
+4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2674              		.loc 1 4784 7 is_stmt 1 view .LVU855
+4785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 2675              		.loc 1 4785 43 is_stmt 0 view .LVU856
+ 2676 00ce 2A68     		ldr	r2, [r5]
+4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2677              		.loc 1 4784 11 view .LVU857
+ 2678 00d0 059B     		ldr	r3, [sp, #20]
+ 2679 00d2 4C32     		adds	r2, r2, #76
+ 2680 00d4 A86B     		ldr	r0, [r5, #56]
+ 2681 00d6 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2682              	.LVL204:
+4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2683              		.loc 1 4784 10 view .LVU858
+ 2684 00da 0028     		cmp	r0, #0
+ 2685 00dc DCD0     		beq	.L112
+4788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 2686              		.loc 1 4788 16 view .LVU859
+ 2687 00de 0120     		movs	r0, #1
+ 2688 00e0 E3E7     		b	.L102
+ 2689              	.LVL205:
+ 2690              	.L125:
+4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2691              		.loc 1 4664 3 view .LVU860
+ 2692 00e2 B4F5805F 		cmp	r4, #4096
+ 2693 00e6 12D1     		bne	.L126
+4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2694              		.loc 1 4741 7 is_stmt 1 view .LVU861
+4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2695              		.loc 1 4741 17 is_stmt 0 view .LVU862
+ 2696 00e8 2B6B     		ldr	r3, [r5, #48]
+4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ARM GAS  /tmp/ccPLZXyC.s 			page 192
+
+
+ 2697              		.loc 1 4741 52 view .LVU863
+ 2698 00ea 274A     		ldr	r2, .L127
+ 2699 00ec DA63     		str	r2, [r3, #60]
+4742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2700              		.loc 1 4742 7 is_stmt 1 view .LVU864
+4742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2701              		.loc 1 4742 17 is_stmt 0 view .LVU865
+ 2702 00ee 2B6B     		ldr	r3, [r5, #48]
+4742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2703              		.loc 1 4742 56 view .LVU866
+ 2704 00f0 264A     		ldr	r2, .L127+4
+ 2705 00f2 1A64     		str	r2, [r3, #64]
+4745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2706              		.loc 1 4745 7 is_stmt 1 view .LVU867
+4745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2707              		.loc 1 4745 17 is_stmt 0 view .LVU868
+ 2708 00f4 2B6B     		ldr	r3, [r5, #48]
+4745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2709              		.loc 1 4745 53 view .LVU869
+ 2710 00f6 264A     		ldr	r2, .L127+8
+ 2711 00f8 DA64     		str	r2, [r3, #76]
+4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2712              		.loc 1 4748 7 is_stmt 1 view .LVU870
+4749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 2713              		.loc 1 4749 43 is_stmt 0 view .LVU871
+ 2714 00fa 2A68     		ldr	r2, [r5]
+4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2715              		.loc 1 4748 11 view .LVU872
+ 2716 00fc 059B     		ldr	r3, [sp, #20]
+ 2717 00fe 4C32     		adds	r2, r2, #76
+ 2718 0100 286B     		ldr	r0, [r5, #48]
+ 2719 0102 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2720              	.LVL206:
+4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2721              		.loc 1 4748 10 view .LVU873
+ 2722 0106 0028     		cmp	r0, #0
+ 2723 0108 C6D0     		beq	.L112
+4752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 2724              		.loc 1 4752 16 view .LVU874
+ 2725 010a 0120     		movs	r0, #1
+ 2726 010c CDE7     		b	.L102
+ 2727              	.LVL207:
+ 2728              	.L126:
+4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2729              		.loc 1 4664 3 view .LVU875
+ 2730 010e 0120     		movs	r0, #1
+ 2731 0110 CBE7     		b	.L102
+ 2732              	.L106:
+4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2733              		.loc 1 4687 7 is_stmt 1 view .LVU876
+4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2734              		.loc 1 4687 17 is_stmt 0 view .LVU877
+ 2735 0112 6B6A     		ldr	r3, [r5, #36]
+4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2736              		.loc 1 4687 52 view .LVU878
+ 2737 0114 1C4A     		ldr	r2, .L127
+ 2738 0116 DA63     		str	r2, [r3, #60]
+ARM GAS  /tmp/ccPLZXyC.s 			page 193
+
+
+4688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2739              		.loc 1 4688 7 is_stmt 1 view .LVU879
+4688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2740              		.loc 1 4688 17 is_stmt 0 view .LVU880
+ 2741 0118 6B6A     		ldr	r3, [r5, #36]
+4688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2742              		.loc 1 4688 56 view .LVU881
+ 2743 011a 1C4A     		ldr	r2, .L127+4
+ 2744 011c 1A64     		str	r2, [r3, #64]
+4691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2745              		.loc 1 4691 7 is_stmt 1 view .LVU882
+4691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2746              		.loc 1 4691 17 is_stmt 0 view .LVU883
+ 2747 011e 6B6A     		ldr	r3, [r5, #36]
+4691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2748              		.loc 1 4691 53 view .LVU884
+ 2749 0120 1B4A     		ldr	r2, .L127+8
+ 2750 0122 DA64     		str	r2, [r3, #76]
+4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2751              		.loc 1 4694 7 is_stmt 1 view .LVU885
+4695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 2752              		.loc 1 4695 43 is_stmt 0 view .LVU886
+ 2753 0124 2A68     		ldr	r2, [r5]
+4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2754              		.loc 1 4694 11 view .LVU887
+ 2755 0126 059B     		ldr	r3, [sp, #20]
+ 2756 0128 4C32     		adds	r2, r2, #76
+ 2757 012a 686A     		ldr	r0, [r5, #36]
+ 2758 012c FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2759              	.LVL208:
+4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2760              		.loc 1 4694 10 view .LVU888
+ 2761 0130 0028     		cmp	r0, #0
+ 2762 0132 B1D0     		beq	.L112
+4698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 2763              		.loc 1 4698 16 view .LVU889
+ 2764 0134 0120     		movs	r0, #1
+ 2765 0136 B8E7     		b	.L102
+ 2766              	.LVL209:
+ 2767              	.L104:
+4723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2768              		.loc 1 4723 7 is_stmt 1 view .LVU890
+4723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2769              		.loc 1 4723 17 is_stmt 0 view .LVU891
+ 2770 0138 EB6A     		ldr	r3, [r5, #44]
+4723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2771              		.loc 1 4723 52 view .LVU892
+ 2772 013a 134A     		ldr	r2, .L127
+ 2773 013c DA63     		str	r2, [r3, #60]
+4724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2774              		.loc 1 4724 7 is_stmt 1 view .LVU893
+4724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2775              		.loc 1 4724 17 is_stmt 0 view .LVU894
+ 2776 013e EB6A     		ldr	r3, [r5, #44]
+4724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2777              		.loc 1 4724 56 view .LVU895
+ 2778 0140 124A     		ldr	r2, .L127+4
+ARM GAS  /tmp/ccPLZXyC.s 			page 194
+
+
+ 2779 0142 1A64     		str	r2, [r3, #64]
+4727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2780              		.loc 1 4727 7 is_stmt 1 view .LVU896
+4727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2781              		.loc 1 4727 17 is_stmt 0 view .LVU897
+ 2782 0144 EB6A     		ldr	r3, [r5, #44]
+4727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2783              		.loc 1 4727 53 view .LVU898
+ 2784 0146 124A     		ldr	r2, .L127+8
+ 2785 0148 DA64     		str	r2, [r3, #76]
+4730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2786              		.loc 1 4730 7 is_stmt 1 view .LVU899
+4731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 2787              		.loc 1 4731 43 is_stmt 0 view .LVU900
+ 2788 014a 2A68     		ldr	r2, [r5]
+4730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2789              		.loc 1 4730 11 view .LVU901
+ 2790 014c 059B     		ldr	r3, [sp, #20]
+ 2791 014e 4C32     		adds	r2, r2, #76
+ 2792 0150 E86A     		ldr	r0, [r5, #44]
+ 2793 0152 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2794              	.LVL210:
+4730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2795              		.loc 1 4730 10 view .LVU902
+ 2796 0156 0028     		cmp	r0, #0
+ 2797 0158 9ED0     		beq	.L112
+4734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 2798              		.loc 1 4734 16 view .LVU903
+ 2799 015a 0120     		movs	r0, #1
+ 2800 015c A5E7     		b	.L102
+ 2801              	.LVL211:
+ 2802              	.L109:
+4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 2803              		.loc 1 4759 7 is_stmt 1 view .LVU904
+4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 2804              		.loc 1 4759 17 is_stmt 0 view .LVU905
+ 2805 015e 6B6B     		ldr	r3, [r5, #52]
+4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 2806              		.loc 1 4759 60 view .LVU906
+ 2807 0160 104A     		ldr	r2, .L127+28
+ 2808 0162 DA63     		str	r2, [r3, #60]
+4760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2809              		.loc 1 4760 7 is_stmt 1 view .LVU907
+4760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2810              		.loc 1 4760 17 is_stmt 0 view .LVU908
+ 2811 0164 6B6B     		ldr	r3, [r5, #52]
+4760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2812              		.loc 1 4760 64 view .LVU909
+ 2813 0166 104A     		ldr	r2, .L127+32
+ 2814 0168 1A64     		str	r2, [r3, #64]
+4763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2815              		.loc 1 4763 7 is_stmt 1 view .LVU910
+4763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2816              		.loc 1 4763 17 is_stmt 0 view .LVU911
+ 2817 016a 6B6B     		ldr	r3, [r5, #52]
+4763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2818              		.loc 1 4763 61 view .LVU912
+ARM GAS  /tmp/ccPLZXyC.s 			page 195
+
+
+ 2819 016c 084A     		ldr	r2, .L127+8
+ 2820 016e DA64     		str	r2, [r3, #76]
+4766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2821              		.loc 1 4766 7 is_stmt 1 view .LVU913
+4767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 2822              		.loc 1 4767 43 is_stmt 0 view .LVU914
+ 2823 0170 2A68     		ldr	r2, [r5]
+4766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2824              		.loc 1 4766 11 view .LVU915
+ 2825 0172 059B     		ldr	r3, [sp, #20]
+ 2826 0174 4C32     		adds	r2, r2, #76
+ 2827 0176 686B     		ldr	r0, [r5, #52]
+ 2828 0178 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2829              	.LVL212:
+4766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ 2830              		.loc 1 4766 10 view .LVU916
+ 2831 017c 0028     		cmp	r0, #0
+ 2832 017e 8BD0     		beq	.L112
+4770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 2833              		.loc 1 4770 16 view .LVU917
+ 2834 0180 0120     		movs	r0, #1
+ 2835 0182 92E7     		b	.L102
+ 2836              	.L124:
+4680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 2837              		.loc 1 4680 16 view .LVU918
+ 2838 0184 0120     		movs	r0, #1
+ 2839 0186 90E7     		b	.L102
+ 2840              	.L128:
+ 2841              		.align	2
+ 2842              	.L127:
+ 2843 0188 00000000 		.word	TIM_DMADelayPulseCplt
+ 2844 018c 00000000 		.word	TIM_DMADelayPulseHalfCplt
+ 2845 0190 00000000 		.word	TIM_DMAError
+ 2846 0194 00000000 		.word	TIM_DMAPeriodElapsedCplt
+ 2847 0198 00000000 		.word	TIM_DMAPeriodElapsedHalfCplt
+ 2848 019c 00000000 		.word	TIM_DMATriggerCplt
+ 2849 01a0 00000000 		.word	TIM_DMATriggerHalfCplt
+ 2850 01a4 00000000 		.word	TIMEx_DMACommutationCplt
+ 2851 01a8 00000000 		.word	TIMEx_DMACommutationHalfCplt
+ 2852              		.cfi_endproc
+ 2853              	.LFE205:
+ 2855              		.section	.text.HAL_TIM_DMABurst_WriteStart,"ax",%progbits
+ 2856              		.align	1
+ 2857              		.global	HAL_TIM_DMABurst_WriteStart
+ 2858              		.syntax unified
+ 2859              		.thumb
+ 2860              		.thumb_func
+ 2861              		.fpu fpv5-d16
+ 2863              	HAL_TIM_DMABurst_WriteStart:
+ 2864              	.LVL213:
+ 2865              	.LFB204:
+4574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status;
+ 2866              		.loc 1 4574 1 is_stmt 1 view -0
+ 2867              		.cfi_startproc
+ 2868              		@ args = 4, pretend = 0, frame = 0
+ 2869              		@ frame_needed = 0, uses_anonymous_args = 0
+4574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status;
+ARM GAS  /tmp/ccPLZXyC.s 			page 196
+
+
+ 2870              		.loc 1 4574 1 is_stmt 0 view .LVU920
+ 2871 0000 30B5     		push	{r4, r5, lr}
+ 2872              	.LCFI29:
+ 2873              		.cfi_def_cfa_offset 12
+ 2874              		.cfi_offset 4, -12
+ 2875              		.cfi_offset 5, -8
+ 2876              		.cfi_offset 14, -4
+ 2877 0002 83B0     		sub	sp, sp, #12
+ 2878              	.LCFI30:
+ 2879              		.cfi_def_cfa_offset 24
+ 2880 0004 069D     		ldr	r5, [sp, #24]
+4575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2881              		.loc 1 4575 3 is_stmt 1 view .LVU921
+4577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                             ((BurstLength) >> 8U) + 1U);
+ 2882              		.loc 1 4577 3 view .LVU922
+4578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2883              		.loc 1 4578 60 is_stmt 0 view .LVU923
+ 2884 0006 2C0A     		lsrs	r4, r5, #8
+4577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                             ((BurstLength) >> 8U) + 1U);
+ 2885              		.loc 1 4577 12 view .LVU924
+ 2886 0008 0134     		adds	r4, r4, #1
+ 2887 000a 0194     		str	r4, [sp, #4]
+ 2888 000c 0095     		str	r5, [sp]
+ 2889 000e FFF7FEFF 		bl	HAL_TIM_DMABurst_MultiWriteStart
+ 2890              	.LVL214:
+4582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 2891              		.loc 1 4582 3 is_stmt 1 view .LVU925
+4583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2892              		.loc 1 4583 1 is_stmt 0 view .LVU926
+ 2893 0012 03B0     		add	sp, sp, #12
+ 2894              	.LCFI31:
+ 2895              		.cfi_def_cfa_offset 12
+ 2896              		@ sp needed
+ 2897 0014 30BD     		pop	{r4, r5, pc}
+4583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2898              		.loc 1 4583 1 view .LVU927
+ 2899              		.cfi_endproc
+ 2900              	.LFE204:
+ 2902              		.section	.text.HAL_TIM_DMABurst_WriteStop,"ax",%progbits
+ 2903              		.align	1
+ 2904              		.global	HAL_TIM_DMABurst_WriteStop
+ 2905              		.syntax unified
+ 2906              		.thumb
+ 2907              		.thumb_func
+ 2908              		.fpu fpv5-d16
+ 2910              	HAL_TIM_DMABurst_WriteStop:
+ 2911              	.LVL215:
+ 2912              	.LFB206:
+4816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2913              		.loc 1 4816 1 is_stmt 1 view -0
+ 2914              		.cfi_startproc
+ 2915              		@ args = 0, pretend = 0, frame = 0
+ 2916              		@ frame_needed = 0, uses_anonymous_args = 0
+4816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2917              		.loc 1 4816 1 is_stmt 0 view .LVU929
+ 2918 0000 38B5     		push	{r3, r4, r5, lr}
+ 2919              	.LCFI32:
+ARM GAS  /tmp/ccPLZXyC.s 			page 197
+
+
+ 2920              		.cfi_def_cfa_offset 16
+ 2921              		.cfi_offset 3, -16
+ 2922              		.cfi_offset 4, -12
+ 2923              		.cfi_offset 5, -8
+ 2924              		.cfi_offset 14, -4
+ 2925 0002 0546     		mov	r5, r0
+ 2926 0004 0C46     		mov	r4, r1
+4817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2927              		.loc 1 4817 3 is_stmt 1 view .LVU930
+ 2928              	.LVL216:
+4820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2929              		.loc 1 4820 3 view .LVU931
+4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2930              		.loc 1 4823 3 view .LVU932
+ 2931 0006 B1F5006F 		cmp	r1, #2048
+ 2932 000a 33D0     		beq	.L132
+ 2933 000c 1BD8     		bhi	.L133
+ 2934 000e B1F5007F 		cmp	r1, #512
+ 2935 0012 2BD0     		beq	.L134
+ 2936 0014 B1F5806F 		cmp	r1, #1024
+ 2937 0018 03D1     		bne	.L143
+4837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 2938              		.loc 1 4837 7 view .LVU933
+4837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 2939              		.loc 1 4837 13 is_stmt 0 view .LVU934
+ 2940 001a 806A     		ldr	r0, [r0, #40]
+ 2941              	.LVL217:
+4837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 2942              		.loc 1 4837 13 view .LVU935
+ 2943 001c FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 2944              	.LVL218:
+4838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 2945              		.loc 1 4838 7 is_stmt 1 view .LVU936
+4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2946              		.loc 1 4865 3 view .LVU937
+ 2947 0020 05E0     		b	.L141
+ 2948              	.LVL219:
+ 2949              	.L143:
+4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2950              		.loc 1 4823 3 is_stmt 0 view .LVU938
+ 2951 0022 B1F5807F 		cmp	r1, #256
+ 2952 0026 0CD1     		bne	.L144
+4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 2953              		.loc 1 4827 7 is_stmt 1 view .LVU939
+4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 2954              		.loc 1 4827 13 is_stmt 0 view .LVU940
+ 2955 0028 006A     		ldr	r0, [r0, #32]
+ 2956              	.LVL220:
+4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 2957              		.loc 1 4827 13 view .LVU941
+ 2958 002a FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 2959              	.LVL221:
+4828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 2960              		.loc 1 4828 7 is_stmt 1 view .LVU942
+4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2961              		.loc 1 4865 3 view .LVU943
+ 2962              	.L141:
+ARM GAS  /tmp/ccPLZXyC.s 			page 198
+
+
+4868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2963              		.loc 1 4868 5 view .LVU944
+ 2964 002e 2B68     		ldr	r3, [r5]
+ 2965 0030 D968     		ldr	r1, [r3, #12]
+ 2966 0032 21EA0404 		bic	r4, r1, r4
+ 2967              	.LVL222:
+4868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2968              		.loc 1 4868 5 is_stmt 0 view .LVU945
+ 2969 0036 DC60     		str	r4, [r3, #12]
+4871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 2970              		.loc 1 4871 5 is_stmt 1 view .LVU946
+4871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 2971              		.loc 1 4871 25 is_stmt 0 view .LVU947
+ 2972 0038 0123     		movs	r3, #1
+ 2973 003a 85F84830 		strb	r3, [r5, #72]
+ 2974 003e 0020     		movs	r0, #0
+ 2975              	.L137:
+ 2976              	.LVL223:
+4875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 2977              		.loc 1 4875 3 is_stmt 1 view .LVU948
+4876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 2978              		.loc 1 4876 1 is_stmt 0 view .LVU949
+ 2979 0040 38BD     		pop	{r3, r4, r5, pc}
+ 2980              	.LVL224:
+ 2981              	.L144:
+4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2982              		.loc 1 4823 3 view .LVU950
+ 2983 0042 0120     		movs	r0, #1
+ 2984              	.LVL225:
+4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2985              		.loc 1 4823 3 view .LVU951
+ 2986 0044 FCE7     		b	.L137
+ 2987              	.LVL226:
+ 2988              	.L133:
+4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 2989              		.loc 1 4823 3 view .LVU952
+ 2990 0046 B1F5005F 		cmp	r1, #8192
+ 2991 004a 17D0     		beq	.L138
+ 2992 004c B1F5804F 		cmp	r1, #16384
+ 2993 0050 03D1     		bne	.L145
+4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 2994              		.loc 1 4857 7 is_stmt 1 view .LVU953
+4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 2995              		.loc 1 4857 13 is_stmt 0 view .LVU954
+ 2996 0052 806B     		ldr	r0, [r0, #56]
+ 2997              	.LVL227:
+4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 2998              		.loc 1 4857 13 view .LVU955
+ 2999 0054 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3000              	.LVL228:
+4858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3001              		.loc 1 4858 7 is_stmt 1 view .LVU956
+4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3002              		.loc 1 4865 3 view .LVU957
+ 3003 0058 E9E7     		b	.L141
+ 3004              	.LVL229:
+ 3005              	.L145:
+ARM GAS  /tmp/ccPLZXyC.s 			page 199
+
+
+4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3006              		.loc 1 4823 3 is_stmt 0 view .LVU958
+ 3007 005a B1F5805F 		cmp	r1, #4096
+ 3008 005e 03D1     		bne	.L146
+4847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3009              		.loc 1 4847 7 is_stmt 1 view .LVU959
+4847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3010              		.loc 1 4847 13 is_stmt 0 view .LVU960
+ 3011 0060 006B     		ldr	r0, [r0, #48]
+ 3012              	.LVL230:
+4847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3013              		.loc 1 4847 13 view .LVU961
+ 3014 0062 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3015              	.LVL231:
+4848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3016              		.loc 1 4848 7 is_stmt 1 view .LVU962
+4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3017              		.loc 1 4865 3 view .LVU963
+ 3018 0066 E2E7     		b	.L141
+ 3019              	.LVL232:
+ 3020              	.L146:
+4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3021              		.loc 1 4823 3 is_stmt 0 view .LVU964
+ 3022 0068 0120     		movs	r0, #1
+ 3023              	.LVL233:
+4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3024              		.loc 1 4823 3 view .LVU965
+ 3025 006a E9E7     		b	.L137
+ 3026              	.LVL234:
+ 3027              	.L134:
+4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3028              		.loc 1 4832 7 is_stmt 1 view .LVU966
+4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3029              		.loc 1 4832 13 is_stmt 0 view .LVU967
+ 3030 006c 406A     		ldr	r0, [r0, #36]
+ 3031              	.LVL235:
+4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3032              		.loc 1 4832 13 view .LVU968
+ 3033 006e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3034              	.LVL236:
+4833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3035              		.loc 1 4833 7 is_stmt 1 view .LVU969
+4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3036              		.loc 1 4865 3 view .LVU970
+ 3037 0072 DCE7     		b	.L141
+ 3038              	.LVL237:
+ 3039              	.L132:
+4842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3040              		.loc 1 4842 7 view .LVU971
+4842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3041              		.loc 1 4842 13 is_stmt 0 view .LVU972
+ 3042 0074 C06A     		ldr	r0, [r0, #44]
+ 3043              	.LVL238:
+4842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3044              		.loc 1 4842 13 view .LVU973
+ 3045 0076 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3046              	.LVL239:
+ARM GAS  /tmp/ccPLZXyC.s 			page 200
+
+
+4843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3047              		.loc 1 4843 7 is_stmt 1 view .LVU974
+4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3048              		.loc 1 4865 3 view .LVU975
+ 3049 007a D8E7     		b	.L141
+ 3050              	.LVL240:
+ 3051              	.L138:
+4852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3052              		.loc 1 4852 7 view .LVU976
+4852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3053              		.loc 1 4852 13 is_stmt 0 view .LVU977
+ 3054 007c 406B     		ldr	r0, [r0, #52]
+ 3055              	.LVL241:
+4852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3056              		.loc 1 4852 13 view .LVU978
+ 3057 007e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3058              	.LVL242:
+4853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3059              		.loc 1 4853 7 is_stmt 1 view .LVU979
+4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3060              		.loc 1 4865 3 view .LVU980
+ 3061 0082 D4E7     		b	.L141
+ 3062              		.cfi_endproc
+ 3063              	.LFE206:
+ 3065              		.section	.text.HAL_TIM_DMABurst_MultiReadStart,"ax",%progbits
+ 3066              		.align	1
+ 3067              		.global	HAL_TIM_DMABurst_MultiReadStart
+ 3068              		.syntax unified
+ 3069              		.thumb
+ 3070              		.thumb_func
+ 3071              		.fpu fpv5-d16
+ 3073              	HAL_TIM_DMABurst_MultiReadStart:
+ 3074              	.LVL243:
+ 3075              	.LFB208:
+4984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3076              		.loc 1 4984 1 view -0
+ 3077              		.cfi_startproc
+ 3078              		@ args = 8, pretend = 0, frame = 0
+ 3079              		@ frame_needed = 0, uses_anonymous_args = 0
+4984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3080              		.loc 1 4984 1 is_stmt 0 view .LVU982
+ 3081 0000 70B5     		push	{r4, r5, r6, lr}
+ 3082              	.LCFI33:
+ 3083              		.cfi_def_cfa_offset 16
+ 3084              		.cfi_offset 4, -16
+ 3085              		.cfi_offset 5, -12
+ 3086              		.cfi_offset 6, -8
+ 3087              		.cfi_offset 14, -4
+ 3088 0002 0546     		mov	r5, r0
+4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3089              		.loc 1 4985 3 is_stmt 1 view .LVU983
+ 3090              	.LVL244:
+4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ 3091              		.loc 1 4988 3 view .LVU984
+4989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ 3092              		.loc 1 4989 3 view .LVU985
+4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ARM GAS  /tmp/ccPLZXyC.s 			page 201
+
+
+ 3093              		.loc 1 4990 3 view .LVU986
+4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+ 3094              		.loc 1 4991 3 view .LVU987
+4992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3095              		.loc 1 4992 3 view .LVU988
+4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3096              		.loc 1 4994 3 view .LVU989
+4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3097              		.loc 1 4994 11 is_stmt 0 view .LVU990
+ 3098 0004 90F848C0 		ldrb	ip, [r0, #72]	@ zero_extendqisi2
+ 3099 0008 5FFA8CF0 		uxtb	r0, ip
+ 3100              	.LVL245:
+4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3101              		.loc 1 4994 6 view .LVU991
+ 3102 000c 0228     		cmp	r0, #2
+ 3103 000e 4ED0     		beq	.L148
+ 3104 0010 0E46     		mov	r6, r1
+ 3105 0012 1446     		mov	r4, r2
+ 3106 0014 1A46     		mov	r2, r3
+ 3107              	.LVL246:
+4998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3108              		.loc 1 4998 8 is_stmt 1 view .LVU992
+4998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3109              		.loc 1 4998 16 is_stmt 0 view .LVU993
+ 3110 0016 95F848C0 		ldrb	ip, [r5, #72]	@ zero_extendqisi2
+ 3111 001a 5FFA8CF0 		uxtb	r0, ip
+4998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3112              		.loc 1 4998 11 view .LVU994
+ 3113 001e 0128     		cmp	r0, #1
+ 3114 0020 1CD0     		beq	.L167
+ 3115              	.LVL247:
+ 3116              	.L149:
+5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   switch (BurstRequestSrc)
+ 3117              		.loc 1 5012 3 is_stmt 1 view .LVU995
+5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3118              		.loc 1 5013 3 view .LVU996
+ 3119 0022 B4F5006F 		cmp	r4, #2048
+ 3120 0026 00F08980 		beq	.L150
+ 3121 002a 43D8     		bhi	.L151
+ 3122 002c B4F5007F 		cmp	r4, #512
+ 3123 0030 71D0     		beq	.L152
+ 3124 0032 B4F5806F 		cmp	r4, #1024
+ 3125 0036 1DD1     		bne	.L168
+5054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3126              		.loc 1 5054 7 view .LVU997
+5054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3127              		.loc 1 5054 17 is_stmt 0 view .LVU998
+ 3128 0038 AB6A     		ldr	r3, [r5, #40]
+5054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3129              		.loc 1 5054 52 view .LVU999
+ 3130 003a 5449     		ldr	r1, .L173
+ 3131 003c D963     		str	r1, [r3, #60]
+5055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3132              		.loc 1 5055 7 is_stmt 1 view .LVU1000
+5055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3133              		.loc 1 5055 17 is_stmt 0 view .LVU1001
+ 3134 003e AB6A     		ldr	r3, [r5, #40]
+ARM GAS  /tmp/ccPLZXyC.s 			page 202
+
+
+5055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3135              		.loc 1 5055 56 view .LVU1002
+ 3136 0040 5349     		ldr	r1, .L173+4
+ 3137 0042 1964     		str	r1, [r3, #64]
+5058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3138              		.loc 1 5058 7 is_stmt 1 view .LVU1003
+5058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3139              		.loc 1 5058 17 is_stmt 0 view .LVU1004
+ 3140 0044 AB6A     		ldr	r3, [r5, #40]
+5058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3141              		.loc 1 5058 53 view .LVU1005
+ 3142 0046 5349     		ldr	r1, .L173+8
+ 3143 0048 D964     		str	r1, [r3, #76]
+5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3144              		.loc 1 5061 7 is_stmt 1 view .LVU1006
+5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3145              		.loc 1 5061 71 is_stmt 0 view .LVU1007
+ 3146 004a 2968     		ldr	r1, [r5]
+5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3147              		.loc 1 5061 11 view .LVU1008
+ 3148 004c 059B     		ldr	r3, [sp, #20]
+ 3149 004e 4C31     		adds	r1, r1, #76
+ 3150 0050 A86A     		ldr	r0, [r5, #40]
+ 3151 0052 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3152              	.LVL248:
+5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3153              		.loc 1 5061 10 view .LVU1009
+ 3154 0056 08B3     		cbz	r0, .L158
+5065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 3155              		.loc 1 5065 16 view .LVU1010
+ 3156 0058 0120     		movs	r0, #1
+ 3157 005a 28E0     		b	.L148
+ 3158              	.LVL249:
+ 3159              	.L167:
+5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 3160              		.loc 1 5000 5 is_stmt 1 view .LVU1011
+5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 3161              		.loc 1 5000 31 is_stmt 0 view .LVU1012
+ 3162 005c 0499     		ldr	r1, [sp, #16]
+ 3163              	.LVL250:
+5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 3164              		.loc 1 5000 31 view .LVU1013
+ 3165 005e B3FA83F3 		clz	r3, r3
+ 3166 0062 5B09     		lsrs	r3, r3, #5
+ 3167 0064 0029     		cmp	r1, #0
+ 3168 0066 08BF     		it	eq
+ 3169 0068 0023     		moveq	r3, #0
+5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 3170              		.loc 1 5000 8 view .LVU1014
+ 3171 006a 03BB     		cbnz	r3, .L148
+5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3172              		.loc 1 5006 7 is_stmt 1 view .LVU1015
+5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3173              		.loc 1 5006 27 is_stmt 0 view .LVU1016
+ 3174 006c 0223     		movs	r3, #2
+ 3175 006e 85F84830 		strb	r3, [r5, #72]
+ 3176 0072 D6E7     		b	.L149
+ARM GAS  /tmp/ccPLZXyC.s 			page 203
+
+
+ 3177              	.L168:
+5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3178              		.loc 1 5013 3 view .LVU1017
+ 3179 0074 B4F5807F 		cmp	r4, #256
+ 3180 0078 1AD1     		bne	.L169
+5018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 3181              		.loc 1 5018 7 is_stmt 1 view .LVU1018
+5018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 3182              		.loc 1 5018 17 is_stmt 0 view .LVU1019
+ 3183 007a 2B6A     		ldr	r3, [r5, #32]
+5018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+ 3184              		.loc 1 5018 55 view .LVU1020
+ 3185 007c 4649     		ldr	r1, .L173+12
+ 3186 007e D963     		str	r1, [r3, #60]
+5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3187              		.loc 1 5019 7 is_stmt 1 view .LVU1021
+5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3188              		.loc 1 5019 17 is_stmt 0 view .LVU1022
+ 3189 0080 2B6A     		ldr	r3, [r5, #32]
+5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3190              		.loc 1 5019 59 view .LVU1023
+ 3191 0082 4649     		ldr	r1, .L173+16
+ 3192 0084 1964     		str	r1, [r3, #64]
+5022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3193              		.loc 1 5022 7 is_stmt 1 view .LVU1024
+5022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3194              		.loc 1 5022 17 is_stmt 0 view .LVU1025
+ 3195 0086 2B6A     		ldr	r3, [r5, #32]
+5022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3196              		.loc 1 5022 56 view .LVU1026
+ 3197 0088 4249     		ldr	r1, .L173+8
+ 3198 008a D964     		str	r1, [r3, #76]
+5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3199              		.loc 1 5025 7 is_stmt 1 view .LVU1027
+5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3200              		.loc 1 5025 74 is_stmt 0 view .LVU1028
+ 3201 008c 2968     		ldr	r1, [r5]
+5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3202              		.loc 1 5025 11 view .LVU1029
+ 3203 008e 059B     		ldr	r3, [sp, #20]
+ 3204 0090 4C31     		adds	r1, r1, #76
+ 3205 0092 286A     		ldr	r0, [r5, #32]
+ 3206 0094 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3207              	.LVL251:
+5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3208              		.loc 1 5025 10 view .LVU1030
+ 3209 0098 0028     		cmp	r0, #0
+ 3210 009a 75D1     		bne	.L170
+ 3211              	.L158:
+ 3212              	.LVL252:
+5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3213              		.loc 1 5149 5 is_stmt 1 view .LVU1031
+5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3214              		.loc 1 5149 9 is_stmt 0 view .LVU1032
+ 3215 009c 2B68     		ldr	r3, [r5]
+5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3216              		.loc 1 5149 45 view .LVU1033
+ARM GAS  /tmp/ccPLZXyC.s 			page 204
+
+
+ 3217 009e 049A     		ldr	r2, [sp, #16]
+ 3218 00a0 1643     		orrs	r6, r6, r2
+ 3219              	.LVL253:
+5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3220              		.loc 1 5149 25 view .LVU1034
+ 3221 00a2 9E64     		str	r6, [r3, #72]
+5152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 3222              		.loc 1 5152 5 is_stmt 1 view .LVU1035
+ 3223 00a4 2B68     		ldr	r3, [r5]
+ 3224 00a6 DA68     		ldr	r2, [r3, #12]
+ 3225 00a8 1443     		orrs	r4, r4, r2
+ 3226              	.LVL254:
+5152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 3227              		.loc 1 5152 5 is_stmt 0 view .LVU1036
+ 3228 00aa DC60     		str	r4, [r3, #12]
+ 3229 00ac 0020     		movs	r0, #0
+ 3230              	.L148:
+5157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3231              		.loc 1 5157 1 view .LVU1037
+ 3232 00ae 70BD     		pop	{r4, r5, r6, pc}
+ 3233              	.LVL255:
+ 3234              	.L169:
+5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3235              		.loc 1 5013 3 view .LVU1038
+ 3236 00b0 0120     		movs	r0, #1
+ 3237 00b2 FCE7     		b	.L148
+ 3238              	.L151:
+5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3239              		.loc 1 5013 3 view .LVU1039
+ 3240 00b4 B4F5005F 		cmp	r4, #8192
+ 3241 00b8 53D0     		beq	.L155
+ 3242 00ba B4F5804F 		cmp	r4, #16384
+ 3243 00be 12D1     		bne	.L171
+5126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 3244              		.loc 1 5126 7 is_stmt 1 view .LVU1040
+5126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 3245              		.loc 1 5126 17 is_stmt 0 view .LVU1041
+ 3246 00c0 AB6B     		ldr	r3, [r5, #56]
+5126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+ 3247              		.loc 1 5126 56 view .LVU1042
+ 3248 00c2 3749     		ldr	r1, .L173+20
+ 3249 00c4 D963     		str	r1, [r3, #60]
+5127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3250              		.loc 1 5127 7 is_stmt 1 view .LVU1043
+5127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3251              		.loc 1 5127 17 is_stmt 0 view .LVU1044
+ 3252 00c6 AB6B     		ldr	r3, [r5, #56]
+5127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3253              		.loc 1 5127 60 view .LVU1045
+ 3254 00c8 3649     		ldr	r1, .L173+24
+ 3255 00ca 1964     		str	r1, [r3, #64]
+5130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3256              		.loc 1 5130 7 is_stmt 1 view .LVU1046
+5130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3257              		.loc 1 5130 17 is_stmt 0 view .LVU1047
+ 3258 00cc AB6B     		ldr	r3, [r5, #56]
+5130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 205
+
+
+ 3259              		.loc 1 5130 57 view .LVU1048
+ 3260 00ce 3149     		ldr	r1, .L173+8
+ 3261 00d0 D964     		str	r1, [r3, #76]
+5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3262              		.loc 1 5133 7 is_stmt 1 view .LVU1049
+5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3263              		.loc 1 5133 75 is_stmt 0 view .LVU1050
+ 3264 00d2 2968     		ldr	r1, [r5]
+5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3265              		.loc 1 5133 11 view .LVU1051
+ 3266 00d4 059B     		ldr	r3, [sp, #20]
+ 3267 00d6 4C31     		adds	r1, r1, #76
+ 3268 00d8 A86B     		ldr	r0, [r5, #56]
+ 3269 00da FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3270              	.LVL256:
+5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3271              		.loc 1 5133 10 view .LVU1052
+ 3272 00de 0028     		cmp	r0, #0
+ 3273 00e0 DCD0     		beq	.L158
+5137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 3274              		.loc 1 5137 16 view .LVU1053
+ 3275 00e2 0120     		movs	r0, #1
+ 3276 00e4 E3E7     		b	.L148
+ 3277              	.LVL257:
+ 3278              	.L171:
+5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3279              		.loc 1 5013 3 view .LVU1054
+ 3280 00e6 B4F5805F 		cmp	r4, #4096
+ 3281 00ea 12D1     		bne	.L172
+5090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3282              		.loc 1 5090 7 is_stmt 1 view .LVU1055
+5090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3283              		.loc 1 5090 17 is_stmt 0 view .LVU1056
+ 3284 00ec 2B6B     		ldr	r3, [r5, #48]
+5090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3285              		.loc 1 5090 52 view .LVU1057
+ 3286 00ee 2749     		ldr	r1, .L173
+ 3287 00f0 D963     		str	r1, [r3, #60]
+5091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3288              		.loc 1 5091 7 is_stmt 1 view .LVU1058
+5091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3289              		.loc 1 5091 17 is_stmt 0 view .LVU1059
+ 3290 00f2 2B6B     		ldr	r3, [r5, #48]
+5091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3291              		.loc 1 5091 56 view .LVU1060
+ 3292 00f4 2649     		ldr	r1, .L173+4
+ 3293 00f6 1964     		str	r1, [r3, #64]
+5094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3294              		.loc 1 5094 7 is_stmt 1 view .LVU1061
+5094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3295              		.loc 1 5094 17 is_stmt 0 view .LVU1062
+ 3296 00f8 2B6B     		ldr	r3, [r5, #48]
+5094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3297              		.loc 1 5094 53 view .LVU1063
+ 3298 00fa 2649     		ldr	r1, .L173+8
+ 3299 00fc D964     		str	r1, [r3, #76]
+5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ARM GAS  /tmp/ccPLZXyC.s 			page 206
+
+
+ 3300              		.loc 1 5097 7 is_stmt 1 view .LVU1064
+5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3301              		.loc 1 5097 71 is_stmt 0 view .LVU1065
+ 3302 00fe 2968     		ldr	r1, [r5]
+5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3303              		.loc 1 5097 11 view .LVU1066
+ 3304 0100 059B     		ldr	r3, [sp, #20]
+ 3305 0102 4C31     		adds	r1, r1, #76
+ 3306 0104 286B     		ldr	r0, [r5, #48]
+ 3307 0106 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3308              	.LVL258:
+5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3309              		.loc 1 5097 10 view .LVU1067
+ 3310 010a 0028     		cmp	r0, #0
+ 3311 010c C6D0     		beq	.L158
+5101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 3312              		.loc 1 5101 16 view .LVU1068
+ 3313 010e 0120     		movs	r0, #1
+ 3314 0110 CDE7     		b	.L148
+ 3315              	.LVL259:
+ 3316              	.L172:
+5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3317              		.loc 1 5013 3 view .LVU1069
+ 3318 0112 0120     		movs	r0, #1
+ 3319 0114 CBE7     		b	.L148
+ 3320              	.L152:
+5036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3321              		.loc 1 5036 7 is_stmt 1 view .LVU1070
+5036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3322              		.loc 1 5036 17 is_stmt 0 view .LVU1071
+ 3323 0116 6B6A     		ldr	r3, [r5, #36]
+5036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3324              		.loc 1 5036 52 view .LVU1072
+ 3325 0118 1C49     		ldr	r1, .L173
+ 3326 011a D963     		str	r1, [r3, #60]
+5037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3327              		.loc 1 5037 7 is_stmt 1 view .LVU1073
+5037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3328              		.loc 1 5037 17 is_stmt 0 view .LVU1074
+ 3329 011c 6B6A     		ldr	r3, [r5, #36]
+5037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3330              		.loc 1 5037 56 view .LVU1075
+ 3331 011e 1C49     		ldr	r1, .L173+4
+ 3332 0120 1964     		str	r1, [r3, #64]
+5040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3333              		.loc 1 5040 7 is_stmt 1 view .LVU1076
+5040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3334              		.loc 1 5040 17 is_stmt 0 view .LVU1077
+ 3335 0122 6B6A     		ldr	r3, [r5, #36]
+5040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3336              		.loc 1 5040 53 view .LVU1078
+ 3337 0124 1B49     		ldr	r1, .L173+8
+ 3338 0126 D964     		str	r1, [r3, #76]
+5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3339              		.loc 1 5043 7 is_stmt 1 view .LVU1079
+5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3340              		.loc 1 5043 71 is_stmt 0 view .LVU1080
+ARM GAS  /tmp/ccPLZXyC.s 			page 207
+
+
+ 3341 0128 2968     		ldr	r1, [r5]
+5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3342              		.loc 1 5043 11 view .LVU1081
+ 3343 012a 059B     		ldr	r3, [sp, #20]
+ 3344 012c 4C31     		adds	r1, r1, #76
+ 3345 012e 686A     		ldr	r0, [r5, #36]
+ 3346 0130 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3347              	.LVL260:
+5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3348              		.loc 1 5043 10 view .LVU1082
+ 3349 0134 0028     		cmp	r0, #0
+ 3350 0136 B1D0     		beq	.L158
+5047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 3351              		.loc 1 5047 16 view .LVU1083
+ 3352 0138 0120     		movs	r0, #1
+ 3353 013a B8E7     		b	.L148
+ 3354              	.LVL261:
+ 3355              	.L150:
+5072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3356              		.loc 1 5072 7 is_stmt 1 view .LVU1084
+5072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3357              		.loc 1 5072 17 is_stmt 0 view .LVU1085
+ 3358 013c EB6A     		ldr	r3, [r5, #44]
+5072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 3359              		.loc 1 5072 52 view .LVU1086
+ 3360 013e 1349     		ldr	r1, .L173
+ 3361 0140 D963     		str	r1, [r3, #60]
+5073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3362              		.loc 1 5073 7 is_stmt 1 view .LVU1087
+5073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3363              		.loc 1 5073 17 is_stmt 0 view .LVU1088
+ 3364 0142 EB6A     		ldr	r3, [r5, #44]
+5073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3365              		.loc 1 5073 56 view .LVU1089
+ 3366 0144 1249     		ldr	r1, .L173+4
+ 3367 0146 1964     		str	r1, [r3, #64]
+5076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3368              		.loc 1 5076 7 is_stmt 1 view .LVU1090
+5076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3369              		.loc 1 5076 17 is_stmt 0 view .LVU1091
+ 3370 0148 EB6A     		ldr	r3, [r5, #44]
+5076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3371              		.loc 1 5076 53 view .LVU1092
+ 3372 014a 1249     		ldr	r1, .L173+8
+ 3373 014c D964     		str	r1, [r3, #76]
+5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3374              		.loc 1 5079 7 is_stmt 1 view .LVU1093
+5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3375              		.loc 1 5079 71 is_stmt 0 view .LVU1094
+ 3376 014e 2968     		ldr	r1, [r5]
+5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3377              		.loc 1 5079 11 view .LVU1095
+ 3378 0150 059B     		ldr	r3, [sp, #20]
+ 3379 0152 4C31     		adds	r1, r1, #76
+ 3380 0154 E86A     		ldr	r0, [r5, #44]
+ 3381 0156 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3382              	.LVL262:
+ARM GAS  /tmp/ccPLZXyC.s 			page 208
+
+
+5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3383              		.loc 1 5079 10 view .LVU1096
+ 3384 015a 0028     		cmp	r0, #0
+ 3385 015c 9ED0     		beq	.L158
+5083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 3386              		.loc 1 5083 16 view .LVU1097
+ 3387 015e 0120     		movs	r0, #1
+ 3388 0160 A5E7     		b	.L148
+ 3389              	.LVL263:
+ 3390              	.L155:
+5108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 3391              		.loc 1 5108 7 is_stmt 1 view .LVU1098
+5108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 3392              		.loc 1 5108 17 is_stmt 0 view .LVU1099
+ 3393 0162 6B6B     		ldr	r3, [r5, #52]
+5108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+ 3394              		.loc 1 5108 60 view .LVU1100
+ 3395 0164 1049     		ldr	r1, .L173+28
+ 3396 0166 D963     		str	r1, [r3, #60]
+5109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3397              		.loc 1 5109 7 is_stmt 1 view .LVU1101
+5109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3398              		.loc 1 5109 17 is_stmt 0 view .LVU1102
+ 3399 0168 6B6B     		ldr	r3, [r5, #52]
+5109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3400              		.loc 1 5109 64 view .LVU1103
+ 3401 016a 1049     		ldr	r1, .L173+32
+ 3402 016c 1964     		str	r1, [r3, #64]
+5112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3403              		.loc 1 5112 7 is_stmt 1 view .LVU1104
+5112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3404              		.loc 1 5112 17 is_stmt 0 view .LVU1105
+ 3405 016e 6B6B     		ldr	r3, [r5, #52]
+5112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3406              		.loc 1 5112 61 view .LVU1106
+ 3407 0170 0849     		ldr	r1, .L173+8
+ 3408 0172 D964     		str	r1, [r3, #76]
+5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3409              		.loc 1 5115 7 is_stmt 1 view .LVU1107
+5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3410              		.loc 1 5115 79 is_stmt 0 view .LVU1108
+ 3411 0174 2968     		ldr	r1, [r5]
+5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3412              		.loc 1 5115 11 view .LVU1109
+ 3413 0176 059B     		ldr	r3, [sp, #20]
+ 3414 0178 4C31     		adds	r1, r1, #76
+ 3415 017a 686B     		ldr	r0, [r5, #52]
+ 3416 017c FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3417              	.LVL264:
+5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            DataLength) != HAL_OK)
+ 3418              		.loc 1 5115 10 view .LVU1110
+ 3419 0180 0028     		cmp	r0, #0
+ 3420 0182 8BD0     		beq	.L158
+5119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 3421              		.loc 1 5119 16 view .LVU1111
+ 3422 0184 0120     		movs	r0, #1
+ 3423 0186 92E7     		b	.L148
+ARM GAS  /tmp/ccPLZXyC.s 			page 209
+
+
+ 3424              	.L170:
+5029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 3425              		.loc 1 5029 16 view .LVU1112
+ 3426 0188 0120     		movs	r0, #1
+ 3427 018a 90E7     		b	.L148
+ 3428              	.L174:
+ 3429              		.align	2
+ 3430              	.L173:
+ 3431 018c 00000000 		.word	TIM_DMACaptureCplt
+ 3432 0190 00000000 		.word	TIM_DMACaptureHalfCplt
+ 3433 0194 00000000 		.word	TIM_DMAError
+ 3434 0198 00000000 		.word	TIM_DMAPeriodElapsedCplt
+ 3435 019c 00000000 		.word	TIM_DMAPeriodElapsedHalfCplt
+ 3436 01a0 00000000 		.word	TIM_DMATriggerCplt
+ 3437 01a4 00000000 		.word	TIM_DMATriggerHalfCplt
+ 3438 01a8 00000000 		.word	TIMEx_DMACommutationCplt
+ 3439 01ac 00000000 		.word	TIMEx_DMACommutationHalfCplt
+ 3440              		.cfi_endproc
+ 3441              	.LFE208:
+ 3443              		.section	.text.HAL_TIM_DMABurst_ReadStart,"ax",%progbits
+ 3444              		.align	1
+ 3445              		.global	HAL_TIM_DMABurst_ReadStart
+ 3446              		.syntax unified
+ 3447              		.thumb
+ 3448              		.thumb_func
+ 3449              		.fpu fpv5-d16
+ 3451              	HAL_TIM_DMABurst_ReadStart:
+ 3452              	.LVL265:
+ 3453              	.LFB207:
+4925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status;
+ 3454              		.loc 1 4925 1 is_stmt 1 view -0
+ 3455              		.cfi_startproc
+ 3456              		@ args = 4, pretend = 0, frame = 0
+ 3457              		@ frame_needed = 0, uses_anonymous_args = 0
+4925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status;
+ 3458              		.loc 1 4925 1 is_stmt 0 view .LVU1114
+ 3459 0000 30B5     		push	{r4, r5, lr}
+ 3460              	.LCFI34:
+ 3461              		.cfi_def_cfa_offset 12
+ 3462              		.cfi_offset 4, -12
+ 3463              		.cfi_offset 5, -8
+ 3464              		.cfi_offset 14, -4
+ 3465 0002 83B0     		sub	sp, sp, #12
+ 3466              	.LCFI35:
+ 3467              		.cfi_def_cfa_offset 24
+ 3468 0004 069D     		ldr	r5, [sp, #24]
+4926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3469              		.loc 1 4926 3 is_stmt 1 view .LVU1115
+4928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                            ((BurstLength) >> 8U) + 1U);
+ 3470              		.loc 1 4928 3 view .LVU1116
+4929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3471              		.loc 1 4929 59 is_stmt 0 view .LVU1117
+ 3472 0006 2C0A     		lsrs	r4, r5, #8
+4928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                            ((BurstLength) >> 8U) + 1U);
+ 3473              		.loc 1 4928 12 view .LVU1118
+ 3474 0008 0134     		adds	r4, r4, #1
+ 3475 000a 0194     		str	r4, [sp, #4]
+ARM GAS  /tmp/ccPLZXyC.s 			page 210
+
+
+ 3476 000c 0095     		str	r5, [sp]
+ 3477 000e FFF7FEFF 		bl	HAL_TIM_DMABurst_MultiReadStart
+ 3478              	.LVL266:
+4932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 3479              		.loc 1 4932 3 is_stmt 1 view .LVU1119
+4933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3480              		.loc 1 4933 1 is_stmt 0 view .LVU1120
+ 3481 0012 03B0     		add	sp, sp, #12
+ 3482              	.LCFI36:
+ 3483              		.cfi_def_cfa_offset 12
+ 3484              		@ sp needed
+ 3485 0014 30BD     		pop	{r4, r5, pc}
+4933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3486              		.loc 1 4933 1 view .LVU1121
+ 3487              		.cfi_endproc
+ 3488              	.LFE207:
+ 3490              		.section	.text.HAL_TIM_DMABurst_ReadStop,"ax",%progbits
+ 3491              		.align	1
+ 3492              		.global	HAL_TIM_DMABurst_ReadStop
+ 3493              		.syntax unified
+ 3494              		.thumb
+ 3495              		.thumb_func
+ 3496              		.fpu fpv5-d16
+ 3498              	HAL_TIM_DMABurst_ReadStop:
+ 3499              	.LVL267:
+ 3500              	.LFB209:
+5166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3501              		.loc 1 5166 1 is_stmt 1 view -0
+ 3502              		.cfi_startproc
+ 3503              		@ args = 0, pretend = 0, frame = 0
+ 3504              		@ frame_needed = 0, uses_anonymous_args = 0
+5166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3505              		.loc 1 5166 1 is_stmt 0 view .LVU1123
+ 3506 0000 38B5     		push	{r3, r4, r5, lr}
+ 3507              	.LCFI37:
+ 3508              		.cfi_def_cfa_offset 16
+ 3509              		.cfi_offset 3, -16
+ 3510              		.cfi_offset 4, -12
+ 3511              		.cfi_offset 5, -8
+ 3512              		.cfi_offset 14, -4
+ 3513 0002 0546     		mov	r5, r0
+ 3514 0004 0C46     		mov	r4, r1
+5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3515              		.loc 1 5167 3 is_stmt 1 view .LVU1124
+ 3516              	.LVL268:
+5170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3517              		.loc 1 5170 3 view .LVU1125
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3518              		.loc 1 5173 3 view .LVU1126
+ 3519 0006 B1F5006F 		cmp	r1, #2048
+ 3520 000a 33D0     		beq	.L178
+ 3521 000c 1BD8     		bhi	.L179
+ 3522 000e B1F5007F 		cmp	r1, #512
+ 3523 0012 2BD0     		beq	.L180
+ 3524 0014 B1F5806F 		cmp	r1, #1024
+ 3525 0018 03D1     		bne	.L189
+5187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ARM GAS  /tmp/ccPLZXyC.s 			page 211
+
+
+ 3526              		.loc 1 5187 7 view .LVU1127
+5187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3527              		.loc 1 5187 13 is_stmt 0 view .LVU1128
+ 3528 001a 806A     		ldr	r0, [r0, #40]
+ 3529              	.LVL269:
+5187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3530              		.loc 1 5187 13 view .LVU1129
+ 3531 001c FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3532              	.LVL270:
+5188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3533              		.loc 1 5188 7 is_stmt 1 view .LVU1130
+5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3534              		.loc 1 5215 3 view .LVU1131
+ 3535 0020 05E0     		b	.L187
+ 3536              	.LVL271:
+ 3537              	.L189:
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3538              		.loc 1 5173 3 is_stmt 0 view .LVU1132
+ 3539 0022 B1F5807F 		cmp	r1, #256
+ 3540 0026 0CD1     		bne	.L190
+5177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3541              		.loc 1 5177 7 is_stmt 1 view .LVU1133
+5177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3542              		.loc 1 5177 13 is_stmt 0 view .LVU1134
+ 3543 0028 006A     		ldr	r0, [r0, #32]
+ 3544              	.LVL272:
+5177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3545              		.loc 1 5177 13 view .LVU1135
+ 3546 002a FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3547              	.LVL273:
+5178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3548              		.loc 1 5178 7 is_stmt 1 view .LVU1136
+5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3549              		.loc 1 5215 3 view .LVU1137
+ 3550              	.L187:
+5218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3551              		.loc 1 5218 5 view .LVU1138
+ 3552 002e 2B68     		ldr	r3, [r5]
+ 3553 0030 D968     		ldr	r1, [r3, #12]
+ 3554 0032 21EA0404 		bic	r4, r1, r4
+ 3555              	.LVL274:
+5218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3556              		.loc 1 5218 5 is_stmt 0 view .LVU1139
+ 3557 0036 DC60     		str	r4, [r3, #12]
+5221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 3558              		.loc 1 5221 5 is_stmt 1 view .LVU1140
+5221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 3559              		.loc 1 5221 25 is_stmt 0 view .LVU1141
+ 3560 0038 0123     		movs	r3, #1
+ 3561 003a 85F84830 		strb	r3, [r5, #72]
+ 3562 003e 0020     		movs	r0, #0
+ 3563              	.L183:
+ 3564              	.LVL275:
+5225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 3565              		.loc 1 5225 3 is_stmt 1 view .LVU1142
+5226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3566              		.loc 1 5226 1 is_stmt 0 view .LVU1143
+ARM GAS  /tmp/ccPLZXyC.s 			page 212
+
+
+ 3567 0040 38BD     		pop	{r3, r4, r5, pc}
+ 3568              	.LVL276:
+ 3569              	.L190:
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3570              		.loc 1 5173 3 view .LVU1144
+ 3571 0042 0120     		movs	r0, #1
+ 3572              	.LVL277:
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3573              		.loc 1 5173 3 view .LVU1145
+ 3574 0044 FCE7     		b	.L183
+ 3575              	.LVL278:
+ 3576              	.L179:
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3577              		.loc 1 5173 3 view .LVU1146
+ 3578 0046 B1F5005F 		cmp	r1, #8192
+ 3579 004a 17D0     		beq	.L184
+ 3580 004c B1F5804F 		cmp	r1, #16384
+ 3581 0050 03D1     		bne	.L191
+5207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3582              		.loc 1 5207 7 is_stmt 1 view .LVU1147
+5207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3583              		.loc 1 5207 13 is_stmt 0 view .LVU1148
+ 3584 0052 806B     		ldr	r0, [r0, #56]
+ 3585              	.LVL279:
+5207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3586              		.loc 1 5207 13 view .LVU1149
+ 3587 0054 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3588              	.LVL280:
+5208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3589              		.loc 1 5208 7 is_stmt 1 view .LVU1150
+5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3590              		.loc 1 5215 3 view .LVU1151
+ 3591 0058 E9E7     		b	.L187
+ 3592              	.LVL281:
+ 3593              	.L191:
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3594              		.loc 1 5173 3 is_stmt 0 view .LVU1152
+ 3595 005a B1F5805F 		cmp	r1, #4096
+ 3596 005e 03D1     		bne	.L192
+5197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3597              		.loc 1 5197 7 is_stmt 1 view .LVU1153
+5197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3598              		.loc 1 5197 13 is_stmt 0 view .LVU1154
+ 3599 0060 006B     		ldr	r0, [r0, #48]
+ 3600              	.LVL282:
+5197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3601              		.loc 1 5197 13 view .LVU1155
+ 3602 0062 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3603              	.LVL283:
+5198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3604              		.loc 1 5198 7 is_stmt 1 view .LVU1156
+5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3605              		.loc 1 5215 3 view .LVU1157
+ 3606 0066 E2E7     		b	.L187
+ 3607              	.LVL284:
+ 3608              	.L192:
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 213
+
+
+ 3609              		.loc 1 5173 3 is_stmt 0 view .LVU1158
+ 3610 0068 0120     		movs	r0, #1
+ 3611              	.LVL285:
+5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3612              		.loc 1 5173 3 view .LVU1159
+ 3613 006a E9E7     		b	.L183
+ 3614              	.LVL286:
+ 3615              	.L180:
+5182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3616              		.loc 1 5182 7 is_stmt 1 view .LVU1160
+5182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3617              		.loc 1 5182 13 is_stmt 0 view .LVU1161
+ 3618 006c 406A     		ldr	r0, [r0, #36]
+ 3619              	.LVL287:
+5182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3620              		.loc 1 5182 13 view .LVU1162
+ 3621 006e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3622              	.LVL288:
+5183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3623              		.loc 1 5183 7 is_stmt 1 view .LVU1163
+5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3624              		.loc 1 5215 3 view .LVU1164
+ 3625 0072 DCE7     		b	.L187
+ 3626              	.LVL289:
+ 3627              	.L178:
+5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3628              		.loc 1 5192 7 view .LVU1165
+5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3629              		.loc 1 5192 13 is_stmt 0 view .LVU1166
+ 3630 0074 C06A     		ldr	r0, [r0, #44]
+ 3631              	.LVL290:
+5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3632              		.loc 1 5192 13 view .LVU1167
+ 3633 0076 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3634              	.LVL291:
+5193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3635              		.loc 1 5193 7 is_stmt 1 view .LVU1168
+5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3636              		.loc 1 5215 3 view .LVU1169
+ 3637 007a D8E7     		b	.L187
+ 3638              	.LVL292:
+ 3639              	.L184:
+5202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3640              		.loc 1 5202 7 view .LVU1170
+5202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3641              		.loc 1 5202 13 is_stmt 0 view .LVU1171
+ 3642 007c 406B     		ldr	r0, [r0, #52]
+ 3643              	.LVL293:
+5202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 3644              		.loc 1 5202 13 view .LVU1172
+ 3645 007e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3646              	.LVL294:
+5203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3647              		.loc 1 5203 7 is_stmt 1 view .LVU1173
+5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3648              		.loc 1 5215 3 view .LVU1174
+ 3649 0082 D4E7     		b	.L187
+ARM GAS  /tmp/ccPLZXyC.s 			page 214
+
+
+ 3650              		.cfi_endproc
+ 3651              	.LFE209:
+ 3653              		.section	.text.HAL_TIM_GenerateEvent,"ax",%progbits
+ 3654              		.align	1
+ 3655              		.global	HAL_TIM_GenerateEvent
+ 3656              		.syntax unified
+ 3657              		.thumb
+ 3658              		.thumb_func
+ 3659              		.fpu fpv5-d16
+ 3661              	HAL_TIM_GenerateEvent:
+ 3662              	.LVL295:
+ 3663              	.LFB210:
+5250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 3664              		.loc 1 5250 1 view -0
+ 3665              		.cfi_startproc
+ 3666              		@ args = 0, pretend = 0, frame = 0
+ 3667              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3668              		@ link register save eliminated.
+5252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+ 3669              		.loc 1 5252 3 view .LVU1176
+5253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3670              		.loc 1 5253 3 view .LVU1177
+5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3671              		.loc 1 5256 3 view .LVU1178
+5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3672              		.loc 1 5256 3 view .LVU1179
+ 3673 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 3674 0004 012B     		cmp	r3, #1
+ 3675 0006 0ED0     		beq	.L195
+5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3676              		.loc 1 5256 3 discriminator 2 view .LVU1180
+ 3677 0008 0123     		movs	r3, #1
+ 3678 000a 80F83C30 		strb	r3, [r0, #60]
+5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3679              		.loc 1 5256 3 discriminator 2 view .LVU1181
+5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3680              		.loc 1 5259 3 discriminator 2 view .LVU1182
+5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3681              		.loc 1 5259 15 is_stmt 0 discriminator 2 view .LVU1183
+ 3682 000e 0222     		movs	r2, #2
+ 3683 0010 80F83D20 		strb	r2, [r0, #61]
+5262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3684              		.loc 1 5262 3 is_stmt 1 discriminator 2 view .LVU1184
+5262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3685              		.loc 1 5262 7 is_stmt 0 discriminator 2 view .LVU1185
+ 3686 0014 0268     		ldr	r2, [r0]
+5262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3687              		.loc 1 5262 23 discriminator 2 view .LVU1186
+ 3688 0016 5161     		str	r1, [r2, #20]
+5265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3689              		.loc 1 5265 3 is_stmt 1 discriminator 2 view .LVU1187
+5265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3690              		.loc 1 5265 15 is_stmt 0 discriminator 2 view .LVU1188
+ 3691 0018 80F83D30 		strb	r3, [r0, #61]
+5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3692              		.loc 1 5267 3 is_stmt 1 discriminator 2 view .LVU1189
+5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 215
+
+
+ 3693              		.loc 1 5267 3 discriminator 2 view .LVU1190
+ 3694 001c 0023     		movs	r3, #0
+ 3695 001e 80F83C30 		strb	r3, [r0, #60]
+5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3696              		.loc 1 5267 3 discriminator 2 view .LVU1191
+5270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 3697              		.loc 1 5270 3 discriminator 2 view .LVU1192
+5270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 3698              		.loc 1 5270 10 is_stmt 0 discriminator 2 view .LVU1193
+ 3699 0022 1846     		mov	r0, r3
+ 3700              	.LVL296:
+5270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 3701              		.loc 1 5270 10 discriminator 2 view .LVU1194
+ 3702 0024 7047     		bx	lr
+ 3703              	.LVL297:
+ 3704              	.L195:
+5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3705              		.loc 1 5256 3 view .LVU1195
+ 3706 0026 0220     		movs	r0, #2
+ 3707              	.LVL298:
+5271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3708              		.loc 1 5271 1 view .LVU1196
+ 3709 0028 7047     		bx	lr
+ 3710              		.cfi_endproc
+ 3711              	.LFE210:
+ 3713              		.section	.text.HAL_TIM_ConfigTI1Input,"ax",%progbits
+ 3714              		.align	1
+ 3715              		.global	HAL_TIM_ConfigTI1Input
+ 3716              		.syntax unified
+ 3717              		.thumb
+ 3718              		.thumb_func
+ 3719              		.fpu fpv5-d16
+ 3721              	HAL_TIM_ConfigTI1Input:
+ 3722              	.LVL299:
+ 3723              	.LFB213:
+5601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr2;
+ 3724              		.loc 1 5601 1 is_stmt 1 view -0
+ 3725              		.cfi_startproc
+ 3726              		@ args = 0, pretend = 0, frame = 0
+ 3727              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3728              		@ link register save eliminated.
+5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3729              		.loc 1 5602 3 view .LVU1198
+5605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+ 3730              		.loc 1 5605 3 view .LVU1199
+5606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3731              		.loc 1 5606 3 view .LVU1200
+5609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3732              		.loc 1 5609 3 view .LVU1201
+5609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3733              		.loc 1 5609 16 is_stmt 0 view .LVU1202
+ 3734 0000 0268     		ldr	r2, [r0]
+5609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3735              		.loc 1 5609 10 view .LVU1203
+ 3736 0002 5368     		ldr	r3, [r2, #4]
+ 3737              	.LVL300:
+5612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 216
+
+
+ 3738              		.loc 1 5612 3 is_stmt 1 view .LVU1204
+5612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3739              		.loc 1 5612 10 is_stmt 0 view .LVU1205
+ 3740 0004 23F08003 		bic	r3, r3, #128
+ 3741              	.LVL301:
+5615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3742              		.loc 1 5615 3 is_stmt 1 view .LVU1206
+5615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3743              		.loc 1 5615 10 is_stmt 0 view .LVU1207
+ 3744 0008 0B43     		orrs	r3, r3, r1
+ 3745              	.LVL302:
+5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3746              		.loc 1 5618 3 is_stmt 1 view .LVU1208
+5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3747              		.loc 1 5618 23 is_stmt 0 view .LVU1209
+ 3748 000a 5360     		str	r3, [r2, #4]
+5620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 3749              		.loc 1 5620 3 is_stmt 1 view .LVU1210
+5621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3750              		.loc 1 5621 1 is_stmt 0 view .LVU1211
+ 3751 000c 0020     		movs	r0, #0
+ 3752              	.LVL303:
+5621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3753              		.loc 1 5621 1 view .LVU1212
+ 3754 000e 7047     		bx	lr
+ 3755              		.cfi_endproc
+ 3756              	.LFE213:
+ 3758              		.section	.text.HAL_TIM_ReadCapturedValue,"ax",%progbits
+ 3759              		.align	1
+ 3760              		.global	HAL_TIM_ReadCapturedValue
+ 3761              		.syntax unified
+ 3762              		.thumb
+ 3763              		.thumb_func
+ 3764              		.fpu fpv5-d16
+ 3766              	HAL_TIM_ReadCapturedValue:
+ 3767              	.LVL304:
+ 3768              	.LFB216:
+5716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpreg = 0U;
+ 3769              		.loc 1 5716 1 is_stmt 1 view -0
+ 3770              		.cfi_startproc
+ 3771              		@ args = 0, pretend = 0, frame = 0
+ 3772              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3773              		@ link register save eliminated.
+5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3774              		.loc 1 5717 3 view .LVU1214
+5719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3775              		.loc 1 5719 3 view .LVU1215
+ 3776 0000 0C29     		cmp	r1, #12
+ 3777 0002 14D8     		bhi	.L204
+ 3778 0004 DFE801F0 		tbb	[pc, r1]
+ 3779              	.L200:
+ 3780 0008 07       		.byte	(.L203-.L200)/2
+ 3781 0009 13       		.byte	(.L204-.L200)/2
+ 3782 000a 13       		.byte	(.L204-.L200)/2
+ 3783 000b 13       		.byte	(.L204-.L200)/2
+ 3784 000c 0A       		.byte	(.L202-.L200)/2
+ 3785 000d 13       		.byte	(.L204-.L200)/2
+ARM GAS  /tmp/ccPLZXyC.s 			page 217
+
+
+ 3786 000e 13       		.byte	(.L204-.L200)/2
+ 3787 000f 13       		.byte	(.L204-.L200)/2
+ 3788 0010 0D       		.byte	(.L201-.L200)/2
+ 3789 0011 13       		.byte	(.L204-.L200)/2
+ 3790 0012 13       		.byte	(.L204-.L200)/2
+ 3791 0013 13       		.byte	(.L204-.L200)/2
+ 3792 0014 10       		.byte	(.L199-.L200)/2
+ 3793 0015 00       		.p2align 1
+ 3794              	.L203:
+5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3795              		.loc 1 5724 7 view .LVU1216
+5727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3796              		.loc 1 5727 7 view .LVU1217
+5727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3797              		.loc 1 5727 21 is_stmt 0 view .LVU1218
+ 3798 0016 0368     		ldr	r3, [r0]
+5727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3799              		.loc 1 5727 14 view .LVU1219
+ 3800 0018 586B     		ldr	r0, [r3, #52]
+ 3801              	.LVL305:
+5729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3802              		.loc 1 5729 7 is_stmt 1 view .LVU1220
+ 3803 001a 7047     		bx	lr
+ 3804              	.LVL306:
+ 3805              	.L202:
+5734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3806              		.loc 1 5734 7 view .LVU1221
+5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3807              		.loc 1 5737 7 view .LVU1222
+5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3808              		.loc 1 5737 22 is_stmt 0 view .LVU1223
+ 3809 001c 0368     		ldr	r3, [r0]
+5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3810              		.loc 1 5737 14 view .LVU1224
+ 3811 001e 986B     		ldr	r0, [r3, #56]
+ 3812              	.LVL307:
+5739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3813              		.loc 1 5739 7 is_stmt 1 view .LVU1225
+ 3814 0020 7047     		bx	lr
+ 3815              	.LVL308:
+ 3816              	.L201:
+5745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3817              		.loc 1 5745 7 view .LVU1226
+5748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3818              		.loc 1 5748 7 view .LVU1227
+5748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3819              		.loc 1 5748 22 is_stmt 0 view .LVU1228
+ 3820 0022 0368     		ldr	r3, [r0]
+5748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3821              		.loc 1 5748 14 view .LVU1229
+ 3822 0024 D86B     		ldr	r0, [r3, #60]
+ 3823              	.LVL309:
+5750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3824              		.loc 1 5750 7 is_stmt 1 view .LVU1230
+ 3825 0026 7047     		bx	lr
+ 3826              	.LVL310:
+ 3827              	.L199:
+ARM GAS  /tmp/ccPLZXyC.s 			page 218
+
+
+5756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3828              		.loc 1 5756 7 view .LVU1231
+5759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3829              		.loc 1 5759 7 view .LVU1232
+5759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3830              		.loc 1 5759 22 is_stmt 0 view .LVU1233
+ 3831 0028 0368     		ldr	r3, [r0]
+5759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3832              		.loc 1 5759 14 view .LVU1234
+ 3833 002a 186C     		ldr	r0, [r3, #64]
+ 3834              	.LVL311:
+5761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 3835              		.loc 1 5761 7 is_stmt 1 view .LVU1235
+ 3836 002c 7047     		bx	lr
+ 3837              	.LVL312:
+ 3838              	.L204:
+5719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3839              		.loc 1 5719 3 is_stmt 0 view .LVU1236
+ 3840 002e 0020     		movs	r0, #0
+ 3841              	.LVL313:
+5768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 3842              		.loc 1 5768 3 is_stmt 1 view .LVU1237
+5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3843              		.loc 1 5769 1 is_stmt 0 view .LVU1238
+ 3844 0030 7047     		bx	lr
+ 3845              		.cfi_endproc
+ 3846              	.LFE216:
+ 3848              		.section	.text.HAL_TIM_PeriodElapsedCallback,"ax",%progbits
+ 3849              		.align	1
+ 3850              		.weak	HAL_TIM_PeriodElapsedCallback
+ 3851              		.syntax unified
+ 3852              		.thumb
+ 3853              		.thumb_func
+ 3854              		.fpu fpv5-d16
+ 3856              	HAL_TIM_PeriodElapsedCallback:
+ 3857              	.LVL314:
+ 3858              	.LFB217:
+5800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 3859              		.loc 1 5800 1 is_stmt 1 view -0
+ 3860              		.cfi_startproc
+ 3861              		@ args = 0, pretend = 0, frame = 0
+ 3862              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3863              		@ link register save eliminated.
+5802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3864              		.loc 1 5802 3 view .LVU1240
+5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3865              		.loc 1 5807 1 is_stmt 0 view .LVU1241
+ 3866 0000 7047     		bx	lr
+ 3867              		.cfi_endproc
+ 3868              	.LFE217:
+ 3870              		.section	.text.TIM_DMAPeriodElapsedCplt,"ax",%progbits
+ 3871              		.align	1
+ 3872              		.syntax unified
+ 3873              		.thumb
+ 3874              		.thumb_func
+ 3875              		.fpu fpv5-d16
+ 3877              	TIM_DMAPeriodElapsedCplt:
+ARM GAS  /tmp/ccPLZXyC.s 			page 219
+
+
+ 3878              	.LVL315:
+ 3879              	.LFB241:
+6856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 3880              		.loc 1 6856 1 is_stmt 1 view -0
+ 3881              		.cfi_startproc
+ 3882              		@ args = 0, pretend = 0, frame = 0
+ 3883              		@ frame_needed = 0, uses_anonymous_args = 0
+6856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 3884              		.loc 1 6856 1 is_stmt 0 view .LVU1243
+ 3885 0000 08B5     		push	{r3, lr}
+ 3886              	.LCFI38:
+ 3887              		.cfi_def_cfa_offset 8
+ 3888              		.cfi_offset 3, -8
+ 3889              		.cfi_offset 14, -4
+6857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3890              		.loc 1 6857 3 is_stmt 1 view .LVU1244
+6857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3891              		.loc 1 6857 22 is_stmt 0 view .LVU1245
+ 3892 0002 806B     		ldr	r0, [r0, #56]
+ 3893              	.LVL316:
+6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3894              		.loc 1 6859 3 is_stmt 1 view .LVU1246
+6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3895              		.loc 1 6859 17 is_stmt 0 view .LVU1247
+ 3896 0004 036A     		ldr	r3, [r0, #32]
+6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3897              		.loc 1 6859 42 view .LVU1248
+ 3898 0006 DB69     		ldr	r3, [r3, #28]
+6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 3899              		.loc 1 6859 6 view .LVU1249
+ 3900 0008 13B9     		cbnz	r3, .L207
+6861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 3901              		.loc 1 6861 5 is_stmt 1 view .LVU1250
+6861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 3902              		.loc 1 6861 17 is_stmt 0 view .LVU1251
+ 3903 000a 0123     		movs	r3, #1
+ 3904 000c 80F83D30 		strb	r3, [r0, #61]
+ 3905              	.L207:
+6867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 3906              		.loc 1 6867 3 is_stmt 1 view .LVU1252
+ 3907 0010 FFF7FEFF 		bl	HAL_TIM_PeriodElapsedCallback
+ 3908              	.LVL317:
+6869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3909              		.loc 1 6869 1 is_stmt 0 view .LVU1253
+ 3910 0014 08BD     		pop	{r3, pc}
+ 3911              		.cfi_endproc
+ 3912              	.LFE241:
+ 3914              		.section	.text.HAL_TIM_PeriodElapsedHalfCpltCallback,"ax",%progbits
+ 3915              		.align	1
+ 3916              		.weak	HAL_TIM_PeriodElapsedHalfCpltCallback
+ 3917              		.syntax unified
+ 3918              		.thumb
+ 3919              		.thumb_func
+ 3920              		.fpu fpv5-d16
+ 3922              	HAL_TIM_PeriodElapsedHalfCpltCallback:
+ 3923              	.LVL318:
+ 3924              	.LFB218:
+ARM GAS  /tmp/ccPLZXyC.s 			page 220
+
+
+5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 3925              		.loc 1 5815 1 is_stmt 1 view -0
+ 3926              		.cfi_startproc
+ 3927              		@ args = 0, pretend = 0, frame = 0
+ 3928              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3929              		@ link register save eliminated.
+5817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3930              		.loc 1 5817 3 view .LVU1255
+5822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3931              		.loc 1 5822 1 is_stmt 0 view .LVU1256
+ 3932 0000 7047     		bx	lr
+ 3933              		.cfi_endproc
+ 3934              	.LFE218:
+ 3936              		.section	.text.TIM_DMAPeriodElapsedHalfCplt,"ax",%progbits
+ 3937              		.align	1
+ 3938              		.syntax unified
+ 3939              		.thumb
+ 3940              		.thumb_func
+ 3941              		.fpu fpv5-d16
+ 3943              	TIM_DMAPeriodElapsedHalfCplt:
+ 3944              	.LVL319:
+ 3945              	.LFB242:
+6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 3946              		.loc 1 6877 1 is_stmt 1 view -0
+ 3947              		.cfi_startproc
+ 3948              		@ args = 0, pretend = 0, frame = 0
+ 3949              		@ frame_needed = 0, uses_anonymous_args = 0
+6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 3950              		.loc 1 6877 1 is_stmt 0 view .LVU1258
+ 3951 0000 08B5     		push	{r3, lr}
+ 3952              	.LCFI39:
+ 3953              		.cfi_def_cfa_offset 8
+ 3954              		.cfi_offset 3, -8
+ 3955              		.cfi_offset 14, -4
+6878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3956              		.loc 1 6878 3 is_stmt 1 view .LVU1259
+ 3957              	.LVL320:
+6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 3958              		.loc 1 6883 3 view .LVU1260
+ 3959 0002 806B     		ldr	r0, [r0, #56]
+ 3960              	.LVL321:
+6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 3961              		.loc 1 6883 3 is_stmt 0 view .LVU1261
+ 3962 0004 FFF7FEFF 		bl	HAL_TIM_PeriodElapsedHalfCpltCallback
+ 3963              	.LVL322:
+6885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3964              		.loc 1 6885 1 view .LVU1262
+ 3965 0008 08BD     		pop	{r3, pc}
+ 3966              		.cfi_endproc
+ 3967              	.LFE242:
+ 3969              		.section	.text.HAL_TIM_OC_DelayElapsedCallback,"ax",%progbits
+ 3970              		.align	1
+ 3971              		.weak	HAL_TIM_OC_DelayElapsedCallback
+ 3972              		.syntax unified
+ 3973              		.thumb
+ 3974              		.thumb_func
+ 3975              		.fpu fpv5-d16
+ARM GAS  /tmp/ccPLZXyC.s 			page 221
+
+
+ 3977              	HAL_TIM_OC_DelayElapsedCallback:
+ 3978              	.LVL323:
+ 3979              	.LFB219:
+5830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 3980              		.loc 1 5830 1 is_stmt 1 view -0
+ 3981              		.cfi_startproc
+ 3982              		@ args = 0, pretend = 0, frame = 0
+ 3983              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3984              		@ link register save eliminated.
+5832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3985              		.loc 1 5832 3 view .LVU1264
+5837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 3986              		.loc 1 5837 1 is_stmt 0 view .LVU1265
+ 3987 0000 7047     		bx	lr
+ 3988              		.cfi_endproc
+ 3989              	.LFE219:
+ 3991              		.section	.text.HAL_TIM_IC_CaptureCallback,"ax",%progbits
+ 3992              		.align	1
+ 3993              		.weak	HAL_TIM_IC_CaptureCallback
+ 3994              		.syntax unified
+ 3995              		.thumb
+ 3996              		.thumb_func
+ 3997              		.fpu fpv5-d16
+ 3999              	HAL_TIM_IC_CaptureCallback:
+ 4000              	.LVL324:
+ 4001              	.LFB220:
+5845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4002              		.loc 1 5845 1 is_stmt 1 view -0
+ 4003              		.cfi_startproc
+ 4004              		@ args = 0, pretend = 0, frame = 0
+ 4005              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4006              		@ link register save eliminated.
+5847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4007              		.loc 1 5847 3 view .LVU1267
+5852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4008              		.loc 1 5852 1 is_stmt 0 view .LVU1268
+ 4009 0000 7047     		bx	lr
+ 4010              		.cfi_endproc
+ 4011              	.LFE220:
+ 4013              		.section	.text.TIM_DMACaptureCplt,"ax",%progbits
+ 4014              		.align	1
+ 4015              		.global	TIM_DMACaptureCplt
+ 4016              		.syntax unified
+ 4017              		.thumb
+ 4018              		.thumb_func
+ 4019              		.fpu fpv5-d16
+ 4021              	TIM_DMACaptureCplt:
+ 4022              	.LVL325:
+ 4023              	.LFB239:
+6754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4024              		.loc 1 6754 1 is_stmt 1 view -0
+ 4025              		.cfi_startproc
+ 4026              		@ args = 0, pretend = 0, frame = 0
+ 4027              		@ frame_needed = 0, uses_anonymous_args = 0
+6754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4028              		.loc 1 6754 1 is_stmt 0 view .LVU1270
+ 4029 0000 10B5     		push	{r4, lr}
+ARM GAS  /tmp/ccPLZXyC.s 			page 222
+
+
+ 4030              	.LCFI40:
+ 4031              		.cfi_def_cfa_offset 8
+ 4032              		.cfi_offset 4, -8
+ 4033              		.cfi_offset 14, -4
+6755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4034              		.loc 1 6755 3 is_stmt 1 view .LVU1271
+6755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4035              		.loc 1 6755 22 is_stmt 0 view .LVU1272
+ 4036 0002 846B     		ldr	r4, [r0, #56]
+ 4037              	.LVL326:
+6757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4038              		.loc 1 6757 3 is_stmt 1 view .LVU1273
+6757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4039              		.loc 1 6757 25 is_stmt 0 view .LVU1274
+ 4040 0004 636A     		ldr	r3, [r4, #36]
+6757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4041              		.loc 1 6757 6 view .LVU1275
+ 4042 0006 8342     		cmp	r3, r0
+ 4043 0008 0ED0     		beq	.L220
+6767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4044              		.loc 1 6767 8 is_stmt 1 view .LVU1276
+6767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4045              		.loc 1 6767 30 is_stmt 0 view .LVU1277
+ 4046 000a A36A     		ldr	r3, [r4, #40]
+6767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4047              		.loc 1 6767 11 view .LVU1278
+ 4048 000c 8342     		cmp	r3, r0
+ 4049 000e 16D0     		beq	.L221
+6777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4050              		.loc 1 6777 8 is_stmt 1 view .LVU1279
+6777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4051              		.loc 1 6777 30 is_stmt 0 view .LVU1280
+ 4052 0010 E36A     		ldr	r3, [r4, #44]
+6777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4053              		.loc 1 6777 11 view .LVU1281
+ 4054 0012 8342     		cmp	r3, r0
+ 4055 0014 1ED0     		beq	.L222
+6787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4056              		.loc 1 6787 8 is_stmt 1 view .LVU1282
+6787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4057              		.loc 1 6787 30 is_stmt 0 view .LVU1283
+ 4058 0016 236B     		ldr	r3, [r4, #48]
+6787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4059              		.loc 1 6787 11 view .LVU1284
+ 4060 0018 8342     		cmp	r3, r0
+ 4061 001a 26D0     		beq	.L223
+ 4062              	.L216:
+6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4063              		.loc 1 6800 3 is_stmt 1 view .LVU1285
+6805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4064              		.loc 1 6805 3 view .LVU1286
+ 4065 001c 2046     		mov	r0, r4
+ 4066              	.LVL327:
+6805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4067              		.loc 1 6805 3 is_stmt 0 view .LVU1287
+ 4068 001e FFF7FEFF 		bl	HAL_TIM_IC_CaptureCallback
+ 4069              	.LVL328:
+ARM GAS  /tmp/ccPLZXyC.s 			page 223
+
+
+6808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 4070              		.loc 1 6808 3 is_stmt 1 view .LVU1288
+6808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 4071              		.loc 1 6808 17 is_stmt 0 view .LVU1289
+ 4072 0022 0023     		movs	r3, #0
+ 4073 0024 2377     		strb	r3, [r4, #28]
+6809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4074              		.loc 1 6809 1 view .LVU1290
+ 4075 0026 10BD     		pop	{r4, pc}
+ 4076              	.LVL329:
+ 4077              	.L220:
+6759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4078              		.loc 1 6759 5 is_stmt 1 view .LVU1291
+6759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4079              		.loc 1 6759 19 is_stmt 0 view .LVU1292
+ 4080 0028 0123     		movs	r3, #1
+ 4081 002a 2377     		strb	r3, [r4, #28]
+6761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4082              		.loc 1 6761 5 is_stmt 1 view .LVU1293
+6761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4083              		.loc 1 6761 19 is_stmt 0 view .LVU1294
+ 4084 002c C369     		ldr	r3, [r0, #28]
+6761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4085              		.loc 1 6761 8 view .LVU1295
+ 4086 002e 002B     		cmp	r3, #0
+ 4087 0030 F4D1     		bne	.L216
+6763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 4088              		.loc 1 6763 7 is_stmt 1 view .LVU1296
+ 4089 0032 0123     		movs	r3, #1
+ 4090 0034 84F83E30 		strb	r3, [r4, #62]
+6764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4091              		.loc 1 6764 7 view .LVU1297
+ 4092 0038 84F84430 		strb	r3, [r4, #68]
+ 4093 003c EEE7     		b	.L216
+ 4094              	.L221:
+6769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4095              		.loc 1 6769 5 view .LVU1298
+6769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4096              		.loc 1 6769 19 is_stmt 0 view .LVU1299
+ 4097 003e 0223     		movs	r3, #2
+ 4098 0040 2377     		strb	r3, [r4, #28]
+6771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4099              		.loc 1 6771 5 is_stmt 1 view .LVU1300
+6771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4100              		.loc 1 6771 19 is_stmt 0 view .LVU1301
+ 4101 0042 C369     		ldr	r3, [r0, #28]
+6771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4102              		.loc 1 6771 8 view .LVU1302
+ 4103 0044 002B     		cmp	r3, #0
+ 4104 0046 E9D1     		bne	.L216
+6773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 4105              		.loc 1 6773 7 is_stmt 1 view .LVU1303
+ 4106 0048 0123     		movs	r3, #1
+ 4107 004a 84F83F30 		strb	r3, [r4, #63]
+6774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4108              		.loc 1 6774 7 view .LVU1304
+ 4109 004e 84F84530 		strb	r3, [r4, #69]
+ARM GAS  /tmp/ccPLZXyC.s 			page 224
+
+
+ 4110 0052 E3E7     		b	.L216
+ 4111              	.L222:
+6779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4112              		.loc 1 6779 5 view .LVU1305
+6779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4113              		.loc 1 6779 19 is_stmt 0 view .LVU1306
+ 4114 0054 0423     		movs	r3, #4
+ 4115 0056 2377     		strb	r3, [r4, #28]
+6781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4116              		.loc 1 6781 5 is_stmt 1 view .LVU1307
+6781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4117              		.loc 1 6781 19 is_stmt 0 view .LVU1308
+ 4118 0058 C369     		ldr	r3, [r0, #28]
+6781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4119              		.loc 1 6781 8 view .LVU1309
+ 4120 005a 002B     		cmp	r3, #0
+ 4121 005c DED1     		bne	.L216
+6783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ 4122              		.loc 1 6783 7 is_stmt 1 view .LVU1310
+ 4123 005e 0123     		movs	r3, #1
+ 4124 0060 84F84030 		strb	r3, [r4, #64]
+6784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4125              		.loc 1 6784 7 view .LVU1311
+ 4126 0064 84F84630 		strb	r3, [r4, #70]
+ 4127 0068 D8E7     		b	.L216
+ 4128              	.L223:
+6789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4129              		.loc 1 6789 5 view .LVU1312
+6789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4130              		.loc 1 6789 19 is_stmt 0 view .LVU1313
+ 4131 006a 0823     		movs	r3, #8
+ 4132 006c 2377     		strb	r3, [r4, #28]
+6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4133              		.loc 1 6791 5 is_stmt 1 view .LVU1314
+6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4134              		.loc 1 6791 19 is_stmt 0 view .LVU1315
+ 4135 006e C369     		ldr	r3, [r0, #28]
+6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4136              		.loc 1 6791 8 view .LVU1316
+ 4137 0070 002B     		cmp	r3, #0
+ 4138 0072 D3D1     		bne	.L216
+6793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ 4139              		.loc 1 6793 7 is_stmt 1 view .LVU1317
+ 4140 0074 0123     		movs	r3, #1
+ 4141 0076 84F84130 		strb	r3, [r4, #65]
+6794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4142              		.loc 1 6794 7 view .LVU1318
+ 4143 007a 84F84730 		strb	r3, [r4, #71]
+ 4144 007e CDE7     		b	.L216
+ 4145              		.cfi_endproc
+ 4146              	.LFE239:
+ 4148              		.section	.text.HAL_TIM_IC_CaptureHalfCpltCallback,"ax",%progbits
+ 4149              		.align	1
+ 4150              		.weak	HAL_TIM_IC_CaptureHalfCpltCallback
+ 4151              		.syntax unified
+ 4152              		.thumb
+ 4153              		.thumb_func
+ARM GAS  /tmp/ccPLZXyC.s 			page 225
+
+
+ 4154              		.fpu fpv5-d16
+ 4156              	HAL_TIM_IC_CaptureHalfCpltCallback:
+ 4157              	.LVL330:
+ 4158              	.LFB221:
+5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4159              		.loc 1 5860 1 view -0
+ 4160              		.cfi_startproc
+ 4161              		@ args = 0, pretend = 0, frame = 0
+ 4162              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4163              		@ link register save eliminated.
+5862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4164              		.loc 1 5862 3 view .LVU1320
+5867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4165              		.loc 1 5867 1 is_stmt 0 view .LVU1321
+ 4166 0000 7047     		bx	lr
+ 4167              		.cfi_endproc
+ 4168              	.LFE221:
+ 4170              		.section	.text.TIM_DMACaptureHalfCplt,"ax",%progbits
+ 4171              		.align	1
+ 4172              		.global	TIM_DMACaptureHalfCplt
+ 4173              		.syntax unified
+ 4174              		.thumb
+ 4175              		.thumb_func
+ 4176              		.fpu fpv5-d16
+ 4178              	TIM_DMACaptureHalfCplt:
+ 4179              	.LVL331:
+ 4180              	.LFB240:
+6817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4181              		.loc 1 6817 1 is_stmt 1 view -0
+ 4182              		.cfi_startproc
+ 4183              		@ args = 0, pretend = 0, frame = 0
+ 4184              		@ frame_needed = 0, uses_anonymous_args = 0
+6817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4185              		.loc 1 6817 1 is_stmt 0 view .LVU1323
+ 4186 0000 10B5     		push	{r4, lr}
+ 4187              	.LCFI41:
+ 4188              		.cfi_def_cfa_offset 8
+ 4189              		.cfi_offset 4, -8
+ 4190              		.cfi_offset 14, -4
+6818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4191              		.loc 1 6818 3 is_stmt 1 view .LVU1324
+6818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4192              		.loc 1 6818 22 is_stmt 0 view .LVU1325
+ 4193 0002 846B     		ldr	r4, [r0, #56]
+ 4194              	.LVL332:
+6820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4195              		.loc 1 6820 3 is_stmt 1 view .LVU1326
+6820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4196              		.loc 1 6820 25 is_stmt 0 view .LVU1327
+ 4197 0004 636A     		ldr	r3, [r4, #36]
+6820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4198              		.loc 1 6820 6 view .LVU1328
+ 4199 0006 8342     		cmp	r3, r0
+ 4200 0008 0BD0     		beq	.L231
+6824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4201              		.loc 1 6824 8 is_stmt 1 view .LVU1329
+6824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 226
+
+
+ 4202              		.loc 1 6824 30 is_stmt 0 view .LVU1330
+ 4203 000a A36A     		ldr	r3, [r4, #40]
+6824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4204              		.loc 1 6824 11 view .LVU1331
+ 4205 000c 8342     		cmp	r3, r0
+ 4206 000e 10D0     		beq	.L232
+6828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4207              		.loc 1 6828 8 is_stmt 1 view .LVU1332
+6828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4208              		.loc 1 6828 30 is_stmt 0 view .LVU1333
+ 4209 0010 E36A     		ldr	r3, [r4, #44]
+6828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4210              		.loc 1 6828 11 view .LVU1334
+ 4211 0012 8342     		cmp	r3, r0
+ 4212 0014 10D0     		beq	.L233
+6832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4213              		.loc 1 6832 8 is_stmt 1 view .LVU1335
+6832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4214              		.loc 1 6832 30 is_stmt 0 view .LVU1336
+ 4215 0016 236B     		ldr	r3, [r4, #48]
+6832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4216              		.loc 1 6832 11 view .LVU1337
+ 4217 0018 8342     		cmp	r3, r0
+ 4218 001a 04D1     		bne	.L227
+6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4219              		.loc 1 6834 5 is_stmt 1 view .LVU1338
+6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4220              		.loc 1 6834 19 is_stmt 0 view .LVU1339
+ 4221 001c 0823     		movs	r3, #8
+ 4222 001e 2377     		strb	r3, [r4, #28]
+ 4223 0020 01E0     		b	.L227
+ 4224              	.L231:
+6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4225              		.loc 1 6822 5 is_stmt 1 view .LVU1340
+6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4226              		.loc 1 6822 19 is_stmt 0 view .LVU1341
+ 4227 0022 0123     		movs	r3, #1
+ 4228 0024 2377     		strb	r3, [r4, #28]
+ 4229              	.L227:
+6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4230              		.loc 1 6839 3 is_stmt 1 view .LVU1342
+6844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4231              		.loc 1 6844 3 view .LVU1343
+ 4232 0026 2046     		mov	r0, r4
+ 4233              	.LVL333:
+6844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4234              		.loc 1 6844 3 is_stmt 0 view .LVU1344
+ 4235 0028 FFF7FEFF 		bl	HAL_TIM_IC_CaptureHalfCpltCallback
+ 4236              	.LVL334:
+6847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 4237              		.loc 1 6847 3 is_stmt 1 view .LVU1345
+6847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 4238              		.loc 1 6847 17 is_stmt 0 view .LVU1346
+ 4239 002c 0023     		movs	r3, #0
+ 4240 002e 2377     		strb	r3, [r4, #28]
+6848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4241              		.loc 1 6848 1 view .LVU1347
+ARM GAS  /tmp/ccPLZXyC.s 			page 227
+
+
+ 4242 0030 10BD     		pop	{r4, pc}
+ 4243              	.LVL335:
+ 4244              	.L232:
+6826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4245              		.loc 1 6826 5 is_stmt 1 view .LVU1348
+6826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4246              		.loc 1 6826 19 is_stmt 0 view .LVU1349
+ 4247 0032 0223     		movs	r3, #2
+ 4248 0034 2377     		strb	r3, [r4, #28]
+ 4249 0036 F6E7     		b	.L227
+ 4250              	.L233:
+6830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4251              		.loc 1 6830 5 is_stmt 1 view .LVU1350
+6830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4252              		.loc 1 6830 19 is_stmt 0 view .LVU1351
+ 4253 0038 0423     		movs	r3, #4
+ 4254 003a 2377     		strb	r3, [r4, #28]
+ 4255 003c F3E7     		b	.L227
+ 4256              		.cfi_endproc
+ 4257              	.LFE240:
+ 4259              		.section	.text.HAL_TIM_PWM_PulseFinishedCallback,"ax",%progbits
+ 4260              		.align	1
+ 4261              		.weak	HAL_TIM_PWM_PulseFinishedCallback
+ 4262              		.syntax unified
+ 4263              		.thumb
+ 4264              		.thumb_func
+ 4265              		.fpu fpv5-d16
+ 4267              	HAL_TIM_PWM_PulseFinishedCallback:
+ 4268              	.LVL336:
+ 4269              	.LFB222:
+5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4270              		.loc 1 5875 1 is_stmt 1 view -0
+ 4271              		.cfi_startproc
+ 4272              		@ args = 0, pretend = 0, frame = 0
+ 4273              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4274              		@ link register save eliminated.
+5877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4275              		.loc 1 5877 3 view .LVU1353
+5882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4276              		.loc 1 5882 1 is_stmt 0 view .LVU1354
+ 4277 0000 7047     		bx	lr
+ 4278              		.cfi_endproc
+ 4279              	.LFE222:
+ 4281              		.section	.text.TIM_DMADelayPulseCplt,"ax",%progbits
+ 4282              		.align	1
+ 4283              		.syntax unified
+ 4284              		.thumb
+ 4285              		.thumb_func
+ 4286              		.fpu fpv5-d16
+ 4288              	TIM_DMADelayPulseCplt:
+ 4289              	.LVL337:
+ 4290              	.LFB237:
+6656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4291              		.loc 1 6656 1 is_stmt 1 view -0
+ 4292              		.cfi_startproc
+ 4293              		@ args = 0, pretend = 0, frame = 0
+ 4294              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccPLZXyC.s 			page 228
+
+
+6656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4295              		.loc 1 6656 1 is_stmt 0 view .LVU1356
+ 4296 0000 10B5     		push	{r4, lr}
+ 4297              	.LCFI42:
+ 4298              		.cfi_def_cfa_offset 8
+ 4299              		.cfi_offset 4, -8
+ 4300              		.cfi_offset 14, -4
+6657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4301              		.loc 1 6657 3 is_stmt 1 view .LVU1357
+6657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4302              		.loc 1 6657 22 is_stmt 0 view .LVU1358
+ 4303 0002 846B     		ldr	r4, [r0, #56]
+ 4304              	.LVL338:
+6659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4305              		.loc 1 6659 3 is_stmt 1 view .LVU1359
+6659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4306              		.loc 1 6659 25 is_stmt 0 view .LVU1360
+ 4307 0004 636A     		ldr	r3, [r4, #36]
+6659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4308              		.loc 1 6659 6 view .LVU1361
+ 4309 0006 8342     		cmp	r3, r0
+ 4310 0008 0ED0     		beq	.L241
+6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4311              		.loc 1 6668 8 is_stmt 1 view .LVU1362
+6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4312              		.loc 1 6668 30 is_stmt 0 view .LVU1363
+ 4313 000a A36A     		ldr	r3, [r4, #40]
+6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4314              		.loc 1 6668 11 view .LVU1364
+ 4315 000c 8342     		cmp	r3, r0
+ 4316 000e 14D0     		beq	.L242
+6677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4317              		.loc 1 6677 8 is_stmt 1 view .LVU1365
+6677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4318              		.loc 1 6677 30 is_stmt 0 view .LVU1366
+ 4319 0010 E36A     		ldr	r3, [r4, #44]
+6677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4320              		.loc 1 6677 11 view .LVU1367
+ 4321 0012 8342     		cmp	r3, r0
+ 4322 0014 1AD0     		beq	.L243
+6686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4323              		.loc 1 6686 8 is_stmt 1 view .LVU1368
+6686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4324              		.loc 1 6686 30 is_stmt 0 view .LVU1369
+ 4325 0016 236B     		ldr	r3, [r4, #48]
+6686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4326              		.loc 1 6686 11 view .LVU1370
+ 4327 0018 8342     		cmp	r3, r0
+ 4328 001a 20D0     		beq	.L244
+ 4329              	.L237:
+6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4330              		.loc 1 6698 3 is_stmt 1 view .LVU1371
+6703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4331              		.loc 1 6703 3 view .LVU1372
+ 4332 001c 2046     		mov	r0, r4
+ 4333              	.LVL339:
+6703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ARM GAS  /tmp/ccPLZXyC.s 			page 229
+
+
+ 4334              		.loc 1 6703 3 is_stmt 0 view .LVU1373
+ 4335 001e FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ 4336              	.LVL340:
+6706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 4337              		.loc 1 6706 3 is_stmt 1 view .LVU1374
+6706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 4338              		.loc 1 6706 17 is_stmt 0 view .LVU1375
+ 4339 0022 0023     		movs	r3, #0
+ 4340 0024 2377     		strb	r3, [r4, #28]
+6707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4341              		.loc 1 6707 1 view .LVU1376
+ 4342 0026 10BD     		pop	{r4, pc}
+ 4343              	.LVL341:
+ 4344              	.L241:
+6661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4345              		.loc 1 6661 5 is_stmt 1 view .LVU1377
+6661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4346              		.loc 1 6661 19 is_stmt 0 view .LVU1378
+ 4347 0028 0123     		movs	r3, #1
+ 4348 002a 2377     		strb	r3, [r4, #28]
+6663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4349              		.loc 1 6663 5 is_stmt 1 view .LVU1379
+6663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4350              		.loc 1 6663 19 is_stmt 0 view .LVU1380
+ 4351 002c C369     		ldr	r3, [r0, #28]
+6663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4352              		.loc 1 6663 8 view .LVU1381
+ 4353 002e 002B     		cmp	r3, #0
+ 4354 0030 F4D1     		bne	.L237
+6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4355              		.loc 1 6665 7 is_stmt 1 view .LVU1382
+ 4356 0032 0123     		movs	r3, #1
+ 4357 0034 84F83E30 		strb	r3, [r4, #62]
+ 4358 0038 F0E7     		b	.L237
+ 4359              	.L242:
+6670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4360              		.loc 1 6670 5 view .LVU1383
+6670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4361              		.loc 1 6670 19 is_stmt 0 view .LVU1384
+ 4362 003a 0223     		movs	r3, #2
+ 4363 003c 2377     		strb	r3, [r4, #28]
+6672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4364              		.loc 1 6672 5 is_stmt 1 view .LVU1385
+6672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4365              		.loc 1 6672 19 is_stmt 0 view .LVU1386
+ 4366 003e C369     		ldr	r3, [r0, #28]
+6672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4367              		.loc 1 6672 8 view .LVU1387
+ 4368 0040 002B     		cmp	r3, #0
+ 4369 0042 EBD1     		bne	.L237
+6674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4370              		.loc 1 6674 7 is_stmt 1 view .LVU1388
+ 4371 0044 0123     		movs	r3, #1
+ 4372 0046 84F83F30 		strb	r3, [r4, #63]
+ 4373 004a E7E7     		b	.L237
+ 4374              	.L243:
+6679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 230
+
+
+ 4375              		.loc 1 6679 5 view .LVU1389
+6679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4376              		.loc 1 6679 19 is_stmt 0 view .LVU1390
+ 4377 004c 0423     		movs	r3, #4
+ 4378 004e 2377     		strb	r3, [r4, #28]
+6681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4379              		.loc 1 6681 5 is_stmt 1 view .LVU1391
+6681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4380              		.loc 1 6681 19 is_stmt 0 view .LVU1392
+ 4381 0050 C369     		ldr	r3, [r0, #28]
+6681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4382              		.loc 1 6681 8 view .LVU1393
+ 4383 0052 002B     		cmp	r3, #0
+ 4384 0054 E2D1     		bne	.L237
+6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4385              		.loc 1 6683 7 is_stmt 1 view .LVU1394
+ 4386 0056 0123     		movs	r3, #1
+ 4387 0058 84F84030 		strb	r3, [r4, #64]
+ 4388 005c DEE7     		b	.L237
+ 4389              	.L244:
+6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4390              		.loc 1 6688 5 view .LVU1395
+6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4391              		.loc 1 6688 19 is_stmt 0 view .LVU1396
+ 4392 005e 0823     		movs	r3, #8
+ 4393 0060 2377     		strb	r3, [r4, #28]
+6690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4394              		.loc 1 6690 5 is_stmt 1 view .LVU1397
+6690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4395              		.loc 1 6690 19 is_stmt 0 view .LVU1398
+ 4396 0062 C369     		ldr	r3, [r0, #28]
+6690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4397              		.loc 1 6690 8 view .LVU1399
+ 4398 0064 002B     		cmp	r3, #0
+ 4399 0066 D9D1     		bne	.L237
+6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4400              		.loc 1 6692 7 is_stmt 1 view .LVU1400
+ 4401 0068 0123     		movs	r3, #1
+ 4402 006a 84F84130 		strb	r3, [r4, #65]
+ 4403 006e D5E7     		b	.L237
+ 4404              		.cfi_endproc
+ 4405              	.LFE237:
+ 4407              		.section	.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback,"ax",%progbits
+ 4408              		.align	1
+ 4409              		.weak	HAL_TIM_PWM_PulseFinishedHalfCpltCallback
+ 4410              		.syntax unified
+ 4411              		.thumb
+ 4412              		.thumb_func
+ 4413              		.fpu fpv5-d16
+ 4415              	HAL_TIM_PWM_PulseFinishedHalfCpltCallback:
+ 4416              	.LVL342:
+ 4417              	.LFB223:
+5890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4418              		.loc 1 5890 1 view -0
+ 4419              		.cfi_startproc
+ 4420              		@ args = 0, pretend = 0, frame = 0
+ 4421              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccPLZXyC.s 			page 231
+
+
+ 4422              		@ link register save eliminated.
+5892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4423              		.loc 1 5892 3 view .LVU1402
+5897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4424              		.loc 1 5897 1 is_stmt 0 view .LVU1403
+ 4425 0000 7047     		bx	lr
+ 4426              		.cfi_endproc
+ 4427              	.LFE223:
+ 4429              		.section	.text.TIM_DMADelayPulseHalfCplt,"ax",%progbits
+ 4430              		.align	1
+ 4431              		.global	TIM_DMADelayPulseHalfCplt
+ 4432              		.syntax unified
+ 4433              		.thumb
+ 4434              		.thumb_func
+ 4435              		.fpu fpv5-d16
+ 4437              	TIM_DMADelayPulseHalfCplt:
+ 4438              	.LVL343:
+ 4439              	.LFB238:
+6715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4440              		.loc 1 6715 1 is_stmt 1 view -0
+ 4441              		.cfi_startproc
+ 4442              		@ args = 0, pretend = 0, frame = 0
+ 4443              		@ frame_needed = 0, uses_anonymous_args = 0
+6715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4444              		.loc 1 6715 1 is_stmt 0 view .LVU1405
+ 4445 0000 10B5     		push	{r4, lr}
+ 4446              	.LCFI43:
+ 4447              		.cfi_def_cfa_offset 8
+ 4448              		.cfi_offset 4, -8
+ 4449              		.cfi_offset 14, -4
+6716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4450              		.loc 1 6716 3 is_stmt 1 view .LVU1406
+6716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4451              		.loc 1 6716 22 is_stmt 0 view .LVU1407
+ 4452 0002 846B     		ldr	r4, [r0, #56]
+ 4453              	.LVL344:
+6718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4454              		.loc 1 6718 3 is_stmt 1 view .LVU1408
+6718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4455              		.loc 1 6718 25 is_stmt 0 view .LVU1409
+ 4456 0004 636A     		ldr	r3, [r4, #36]
+6718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4457              		.loc 1 6718 6 view .LVU1410
+ 4458 0006 8342     		cmp	r3, r0
+ 4459 0008 0BD0     		beq	.L252
+6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4460              		.loc 1 6722 8 is_stmt 1 view .LVU1411
+6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4461              		.loc 1 6722 30 is_stmt 0 view .LVU1412
+ 4462 000a A36A     		ldr	r3, [r4, #40]
+6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4463              		.loc 1 6722 11 view .LVU1413
+ 4464 000c 8342     		cmp	r3, r0
+ 4465 000e 10D0     		beq	.L253
+6726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4466              		.loc 1 6726 8 is_stmt 1 view .LVU1414
+6726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 232
+
+
+ 4467              		.loc 1 6726 30 is_stmt 0 view .LVU1415
+ 4468 0010 E36A     		ldr	r3, [r4, #44]
+6726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4469              		.loc 1 6726 11 view .LVU1416
+ 4470 0012 8342     		cmp	r3, r0
+ 4471 0014 10D0     		beq	.L254
+6730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4472              		.loc 1 6730 8 is_stmt 1 view .LVU1417
+6730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4473              		.loc 1 6730 30 is_stmt 0 view .LVU1418
+ 4474 0016 236B     		ldr	r3, [r4, #48]
+6730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4475              		.loc 1 6730 11 view .LVU1419
+ 4476 0018 8342     		cmp	r3, r0
+ 4477 001a 04D1     		bne	.L248
+6732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4478              		.loc 1 6732 5 is_stmt 1 view .LVU1420
+6732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4479              		.loc 1 6732 19 is_stmt 0 view .LVU1421
+ 4480 001c 0823     		movs	r3, #8
+ 4481 001e 2377     		strb	r3, [r4, #28]
+ 4482 0020 01E0     		b	.L248
+ 4483              	.L252:
+6720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4484              		.loc 1 6720 5 is_stmt 1 view .LVU1422
+6720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4485              		.loc 1 6720 19 is_stmt 0 view .LVU1423
+ 4486 0022 0123     		movs	r3, #1
+ 4487 0024 2377     		strb	r3, [r4, #28]
+ 4488              	.L248:
+6737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4489              		.loc 1 6737 3 is_stmt 1 view .LVU1424
+6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4490              		.loc 1 6742 3 view .LVU1425
+ 4491 0026 2046     		mov	r0, r4
+ 4492              	.LVL345:
+6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4493              		.loc 1 6742 3 is_stmt 0 view .LVU1426
+ 4494 0028 FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedHalfCpltCallback
+ 4495              	.LVL346:
+6745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 4496              		.loc 1 6745 3 is_stmt 1 view .LVU1427
+6745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 4497              		.loc 1 6745 17 is_stmt 0 view .LVU1428
+ 4498 002c 0023     		movs	r3, #0
+ 4499 002e 2377     		strb	r3, [r4, #28]
+6746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4500              		.loc 1 6746 1 view .LVU1429
+ 4501 0030 10BD     		pop	{r4, pc}
+ 4502              	.LVL347:
+ 4503              	.L253:
+6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4504              		.loc 1 6724 5 is_stmt 1 view .LVU1430
+6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4505              		.loc 1 6724 19 is_stmt 0 view .LVU1431
+ 4506 0032 0223     		movs	r3, #2
+ 4507 0034 2377     		strb	r3, [r4, #28]
+ARM GAS  /tmp/ccPLZXyC.s 			page 233
+
+
+ 4508 0036 F6E7     		b	.L248
+ 4509              	.L254:
+6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4510              		.loc 1 6728 5 is_stmt 1 view .LVU1432
+6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4511              		.loc 1 6728 19 is_stmt 0 view .LVU1433
+ 4512 0038 0423     		movs	r3, #4
+ 4513 003a 2377     		strb	r3, [r4, #28]
+ 4514 003c F3E7     		b	.L248
+ 4515              		.cfi_endproc
+ 4516              	.LFE238:
+ 4518              		.section	.text.HAL_TIM_TriggerCallback,"ax",%progbits
+ 4519              		.align	1
+ 4520              		.weak	HAL_TIM_TriggerCallback
+ 4521              		.syntax unified
+ 4522              		.thumb
+ 4523              		.thumb_func
+ 4524              		.fpu fpv5-d16
+ 4526              	HAL_TIM_TriggerCallback:
+ 4527              	.LVL348:
+ 4528              	.LFB224:
+5905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4529              		.loc 1 5905 1 is_stmt 1 view -0
+ 4530              		.cfi_startproc
+ 4531              		@ args = 0, pretend = 0, frame = 0
+ 4532              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4533              		@ link register save eliminated.
+5907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4534              		.loc 1 5907 3 view .LVU1435
+5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4535              		.loc 1 5912 1 is_stmt 0 view .LVU1436
+ 4536 0000 7047     		bx	lr
+ 4537              		.cfi_endproc
+ 4538              	.LFE224:
+ 4540              		.section	.text.HAL_TIM_IRQHandler,"ax",%progbits
+ 4541              		.align	1
+ 4542              		.global	HAL_TIM_IRQHandler
+ 4543              		.syntax unified
+ 4544              		.thumb
+ 4545              		.thumb_func
+ 4546              		.fpu fpv5-d16
+ 4548              	HAL_TIM_IRQHandler:
+ 4549              	.LVL349:
+ 4550              	.LFB199:
+3835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t itsource = htim->Instance->DIER;
+ 4551              		.loc 1 3835 1 is_stmt 1 view -0
+ 4552              		.cfi_startproc
+ 4553              		@ args = 0, pretend = 0, frame = 0
+ 4554              		@ frame_needed = 0, uses_anonymous_args = 0
+3835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t itsource = htim->Instance->DIER;
+ 4555              		.loc 1 3835 1 is_stmt 0 view .LVU1438
+ 4556 0000 70B5     		push	{r4, r5, r6, lr}
+ 4557              	.LCFI44:
+ 4558              		.cfi_def_cfa_offset 16
+ 4559              		.cfi_offset 4, -16
+ 4560              		.cfi_offset 5, -12
+ 4561              		.cfi_offset 6, -8
+ARM GAS  /tmp/ccPLZXyC.s 			page 234
+
+
+ 4562              		.cfi_offset 14, -4
+ 4563 0002 0446     		mov	r4, r0
+3836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t itflag   = htim->Instance->SR;
+ 4564              		.loc 1 3836 3 is_stmt 1 view .LVU1439
+3836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t itflag   = htim->Instance->SR;
+ 4565              		.loc 1 3836 27 is_stmt 0 view .LVU1440
+ 4566 0004 0368     		ldr	r3, [r0]
+3836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t itflag   = htim->Instance->SR;
+ 4567              		.loc 1 3836 12 view .LVU1441
+ 4568 0006 DE68     		ldr	r6, [r3, #12]
+ 4569              	.LVL350:
+3837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4570              		.loc 1 3837 3 is_stmt 1 view .LVU1442
+3837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4571              		.loc 1 3837 12 is_stmt 0 view .LVU1443
+ 4572 0008 1D69     		ldr	r5, [r3, #16]
+ 4573              	.LVL351:
+3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4574              		.loc 1 3840 3 is_stmt 1 view .LVU1444
+3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4575              		.loc 1 3840 6 is_stmt 0 view .LVU1445
+ 4576 000a 15F0020F 		tst	r5, #2
+ 4577 000e 10D0     		beq	.L257
+3842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4578              		.loc 1 3842 5 is_stmt 1 view .LVU1446
+3842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4579              		.loc 1 3842 8 is_stmt 0 view .LVU1447
+ 4580 0010 16F0020F 		tst	r6, #2
+ 4581 0014 0DD0     		beq	.L257
+3845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ 4582              		.loc 1 3845 9 is_stmt 1 view .LVU1448
+ 4583 0016 6FF00202 		mvn	r2, #2
+ 4584 001a 1A61     		str	r2, [r3, #16]
+3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4585              		.loc 1 3846 9 view .LVU1449
+3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4586              		.loc 1 3846 23 is_stmt 0 view .LVU1450
+ 4587 001c 0123     		movs	r3, #1
+ 4588 001e 0377     		strb	r3, [r0, #28]
+3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 4589              		.loc 1 3849 9 is_stmt 1 view .LVU1451
+3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 4590              		.loc 1 3849 18 is_stmt 0 view .LVU1452
+ 4591 0020 0368     		ldr	r3, [r0]
+3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 4592              		.loc 1 3849 28 view .LVU1453
+ 4593 0022 9B69     		ldr	r3, [r3, #24]
+3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 4594              		.loc 1 3849 12 view .LVU1454
+ 4595 0024 13F0030F 		tst	r3, #3
+ 4596 0028 64D0     		beq	.L258
+3854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4597              		.loc 1 3854 11 is_stmt 1 view .LVU1455
+ 4598 002a FFF7FEFF 		bl	HAL_TIM_IC_CaptureCallback
+ 4599              	.LVL352:
+ 4600              	.L259:
+3868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ARM GAS  /tmp/ccPLZXyC.s 			page 235
+
+
+ 4601              		.loc 1 3868 9 view .LVU1456
+3868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 4602              		.loc 1 3868 23 is_stmt 0 view .LVU1457
+ 4603 002e 0023     		movs	r3, #0
+ 4604 0030 2377     		strb	r3, [r4, #28]
+ 4605              	.L257:
+3873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4606              		.loc 1 3873 3 is_stmt 1 view .LVU1458
+3873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4607              		.loc 1 3873 6 is_stmt 0 view .LVU1459
+ 4608 0032 15F0040F 		tst	r5, #4
+ 4609 0036 12D0     		beq	.L260
+3875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4610              		.loc 1 3875 5 is_stmt 1 view .LVU1460
+3875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4611              		.loc 1 3875 8 is_stmt 0 view .LVU1461
+ 4612 0038 16F0040F 		tst	r6, #4
+ 4613 003c 0FD0     		beq	.L260
+3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ 4614              		.loc 1 3877 7 is_stmt 1 view .LVU1462
+ 4615 003e 2368     		ldr	r3, [r4]
+ 4616 0040 6FF00402 		mvn	r2, #4
+ 4617 0044 1A61     		str	r2, [r3, #16]
+3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Input capture event */
+ 4618              		.loc 1 3878 7 view .LVU1463
+3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Input capture event */
+ 4619              		.loc 1 3878 21 is_stmt 0 view .LVU1464
+ 4620 0046 0223     		movs	r3, #2
+ 4621 0048 2377     		strb	r3, [r4, #28]
+3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4622              		.loc 1 3880 7 is_stmt 1 view .LVU1465
+3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4623              		.loc 1 3880 16 is_stmt 0 view .LVU1466
+ 4624 004a 2368     		ldr	r3, [r4]
+3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4625              		.loc 1 3880 26 view .LVU1467
+ 4626 004c 9B69     		ldr	r3, [r3, #24]
+3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4627              		.loc 1 3880 10 view .LVU1468
+ 4628 004e 13F4407F 		tst	r3, #768
+ 4629 0052 55D0     		beq	.L261
+3885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4630              		.loc 1 3885 9 is_stmt 1 view .LVU1469
+ 4631 0054 2046     		mov	r0, r4
+ 4632 0056 FFF7FEFF 		bl	HAL_TIM_IC_CaptureCallback
+ 4633              	.LVL353:
+ 4634              	.L262:
+3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4635              		.loc 1 3899 7 view .LVU1470
+3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4636              		.loc 1 3899 21 is_stmt 0 view .LVU1471
+ 4637 005a 0023     		movs	r3, #0
+ 4638 005c 2377     		strb	r3, [r4, #28]
+ 4639              	.L260:
+3903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4640              		.loc 1 3903 3 is_stmt 1 view .LVU1472
+3903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 236
+
+
+ 4641              		.loc 1 3903 6 is_stmt 0 view .LVU1473
+ 4642 005e 15F0080F 		tst	r5, #8
+ 4643 0062 12D0     		beq	.L263
+3905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4644              		.loc 1 3905 5 is_stmt 1 view .LVU1474
+3905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4645              		.loc 1 3905 8 is_stmt 0 view .LVU1475
+ 4646 0064 16F0080F 		tst	r6, #8
+ 4647 0068 0FD0     		beq	.L263
+3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ 4648              		.loc 1 3907 7 is_stmt 1 view .LVU1476
+ 4649 006a 2368     		ldr	r3, [r4]
+ 4650 006c 6FF00802 		mvn	r2, #8
+ 4651 0070 1A61     		str	r2, [r3, #16]
+3908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Input capture event */
+ 4652              		.loc 1 3908 7 view .LVU1477
+3908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Input capture event */
+ 4653              		.loc 1 3908 21 is_stmt 0 view .LVU1478
+ 4654 0072 0423     		movs	r3, #4
+ 4655 0074 2377     		strb	r3, [r4, #28]
+3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4656              		.loc 1 3910 7 is_stmt 1 view .LVU1479
+3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4657              		.loc 1 3910 16 is_stmt 0 view .LVU1480
+ 4658 0076 2368     		ldr	r3, [r4]
+3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4659              		.loc 1 3910 26 view .LVU1481
+ 4660 0078 DB69     		ldr	r3, [r3, #28]
+3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4661              		.loc 1 3910 10 view .LVU1482
+ 4662 007a 13F0030F 		tst	r3, #3
+ 4663 007e 46D0     		beq	.L264
+3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4664              		.loc 1 3915 9 is_stmt 1 view .LVU1483
+ 4665 0080 2046     		mov	r0, r4
+ 4666 0082 FFF7FEFF 		bl	HAL_TIM_IC_CaptureCallback
+ 4667              	.LVL354:
+ 4668              	.L265:
+3929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4669              		.loc 1 3929 7 view .LVU1484
+3929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4670              		.loc 1 3929 21 is_stmt 0 view .LVU1485
+ 4671 0086 0023     		movs	r3, #0
+ 4672 0088 2377     		strb	r3, [r4, #28]
+ 4673              	.L263:
+3933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4674              		.loc 1 3933 3 is_stmt 1 view .LVU1486
+3933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4675              		.loc 1 3933 6 is_stmt 0 view .LVU1487
+ 4676 008a 15F0100F 		tst	r5, #16
+ 4677 008e 12D0     		beq	.L266
+3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4678              		.loc 1 3935 5 is_stmt 1 view .LVU1488
+3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4679              		.loc 1 3935 8 is_stmt 0 view .LVU1489
+ 4680 0090 16F0100F 		tst	r6, #16
+ 4681 0094 0FD0     		beq	.L266
+ARM GAS  /tmp/ccPLZXyC.s 			page 237
+
+
+3937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ 4682              		.loc 1 3937 7 is_stmt 1 view .LVU1490
+ 4683 0096 2368     		ldr	r3, [r4]
+ 4684 0098 6FF01002 		mvn	r2, #16
+ 4685 009c 1A61     		str	r2, [r3, #16]
+3938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Input capture event */
+ 4686              		.loc 1 3938 7 view .LVU1491
+3938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Input capture event */
+ 4687              		.loc 1 3938 21 is_stmt 0 view .LVU1492
+ 4688 009e 0823     		movs	r3, #8
+ 4689 00a0 2377     		strb	r3, [r4, #28]
+3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4690              		.loc 1 3940 7 is_stmt 1 view .LVU1493
+3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4691              		.loc 1 3940 16 is_stmt 0 view .LVU1494
+ 4692 00a2 2368     		ldr	r3, [r4]
+3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4693              		.loc 1 3940 26 view .LVU1495
+ 4694 00a4 DB69     		ldr	r3, [r3, #28]
+3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 4695              		.loc 1 3940 10 view .LVU1496
+ 4696 00a6 13F4407F 		tst	r3, #768
+ 4697 00aa 37D0     		beq	.L267
+3945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4698              		.loc 1 3945 9 is_stmt 1 view .LVU1497
+ 4699 00ac 2046     		mov	r0, r4
+ 4700 00ae FFF7FEFF 		bl	HAL_TIM_IC_CaptureCallback
+ 4701              	.LVL355:
+ 4702              	.L268:
+3959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4703              		.loc 1 3959 7 view .LVU1498
+3959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 4704              		.loc 1 3959 21 is_stmt 0 view .LVU1499
+ 4705 00b2 0023     		movs	r3, #0
+ 4706 00b4 2377     		strb	r3, [r4, #28]
+ 4707              	.L266:
+3963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4708              		.loc 1 3963 3 is_stmt 1 view .LVU1500
+3963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4709              		.loc 1 3963 6 is_stmt 0 view .LVU1501
+ 4710 00b6 15F0010F 		tst	r5, #1
+ 4711 00ba 02D0     		beq	.L269
+3965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4712              		.loc 1 3965 5 is_stmt 1 view .LVU1502
+3965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4713              		.loc 1 3965 8 is_stmt 0 view .LVU1503
+ 4714 00bc 16F0010F 		tst	r6, #1
+ 4715 00c0 33D1     		bne	.L275
+ 4716              	.L269:
+3976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
+ 4717              		.loc 1 3976 3 is_stmt 1 view .LVU1504
+3976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
+ 4718              		.loc 1 3976 6 is_stmt 0 view .LVU1505
+ 4719 00c2 15F4025F 		tst	r5, #8320
+ 4720 00c6 02D0     		beq	.L270
+3979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4721              		.loc 1 3979 5 is_stmt 1 view .LVU1506
+ARM GAS  /tmp/ccPLZXyC.s 			page 238
+
+
+3979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4722              		.loc 1 3979 8 is_stmt 0 view .LVU1507
+ 4723 00c8 16F0800F 		tst	r6, #128
+ 4724 00cc 35D1     		bne	.L276
+ 4725              	.L270:
+3990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4726              		.loc 1 3990 3 is_stmt 1 view .LVU1508
+3990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4727              		.loc 1 3990 6 is_stmt 0 view .LVU1509
+ 4728 00ce 15F4807F 		tst	r5, #256
+ 4729 00d2 02D0     		beq	.L271
+3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4730              		.loc 1 3992 5 is_stmt 1 view .LVU1510
+3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4731              		.loc 1 3992 8 is_stmt 0 view .LVU1511
+ 4732 00d4 16F0800F 		tst	r6, #128
+ 4733 00d8 37D1     		bne	.L277
+ 4734              	.L271:
+4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4735              		.loc 1 4003 3 is_stmt 1 view .LVU1512
+4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4736              		.loc 1 4003 6 is_stmt 0 view .LVU1513
+ 4737 00da 15F0400F 		tst	r5, #64
+ 4738 00de 02D0     		beq	.L272
+4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4739              		.loc 1 4005 5 is_stmt 1 view .LVU1514
+4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4740              		.loc 1 4005 8 is_stmt 0 view .LVU1515
+ 4741 00e0 16F0400F 		tst	r6, #64
+ 4742 00e4 39D1     		bne	.L278
+ 4743              	.L272:
+4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4744              		.loc 1 4016 3 is_stmt 1 view .LVU1516
+4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4745              		.loc 1 4016 6 is_stmt 0 view .LVU1517
+ 4746 00e6 15F0200F 		tst	r5, #32
+ 4747 00ea 02D0     		beq	.L256
+4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4748              		.loc 1 4018 5 is_stmt 1 view .LVU1518
+4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 4749              		.loc 1 4018 8 is_stmt 0 view .LVU1519
+ 4750 00ec 16F0200F 		tst	r6, #32
+ 4751 00f0 3BD1     		bne	.L279
+ 4752              	.L256:
+4028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4753              		.loc 1 4028 1 view .LVU1520
+ 4754 00f2 70BD     		pop	{r4, r5, r6, pc}
+ 4755              	.LVL356:
+ 4756              	.L258:
+3864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 4757              		.loc 1 3864 11 is_stmt 1 view .LVU1521
+ 4758 00f4 FFF7FEFF 		bl	HAL_TIM_OC_DelayElapsedCallback
+ 4759              	.LVL357:
+3865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4760              		.loc 1 3865 11 view .LVU1522
+ 4761 00f8 2046     		mov	r0, r4
+ 4762 00fa FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ARM GAS  /tmp/ccPLZXyC.s 			page 239
+
+
+ 4763              	.LVL358:
+ 4764 00fe 96E7     		b	.L259
+ 4765              	.L261:
+3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 4766              		.loc 1 3895 9 view .LVU1523
+ 4767 0100 2046     		mov	r0, r4
+ 4768 0102 FFF7FEFF 		bl	HAL_TIM_OC_DelayElapsedCallback
+ 4769              	.LVL359:
+3896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4770              		.loc 1 3896 9 view .LVU1524
+ 4771 0106 2046     		mov	r0, r4
+ 4772 0108 FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ 4773              	.LVL360:
+ 4774 010c A5E7     		b	.L262
+ 4775              	.L264:
+3925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 4776              		.loc 1 3925 9 view .LVU1525
+ 4777 010e 2046     		mov	r0, r4
+ 4778 0110 FFF7FEFF 		bl	HAL_TIM_OC_DelayElapsedCallback
+ 4779              	.LVL361:
+3926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4780              		.loc 1 3926 9 view .LVU1526
+ 4781 0114 2046     		mov	r0, r4
+ 4782 0116 FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ 4783              	.LVL362:
+ 4784 011a B4E7     		b	.L265
+ 4785              	.L267:
+3955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 4786              		.loc 1 3955 9 view .LVU1527
+ 4787 011c 2046     		mov	r0, r4
+ 4788 011e FFF7FEFF 		bl	HAL_TIM_OC_DelayElapsedCallback
+ 4789              	.LVL363:
+3956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4790              		.loc 1 3956 9 view .LVU1528
+ 4791 0122 2046     		mov	r0, r4
+ 4792 0124 FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ 4793              	.LVL364:
+ 4794 0128 C3E7     		b	.L268
+ 4795              	.L275:
+3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 4796              		.loc 1 3967 7 view .LVU1529
+ 4797 012a 2368     		ldr	r3, [r4]
+ 4798 012c 6FF00102 		mvn	r2, #1
+ 4799 0130 1A61     		str	r2, [r3, #16]
+3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4800              		.loc 1 3971 7 view .LVU1530
+ 4801 0132 2046     		mov	r0, r4
+ 4802 0134 FFF7FEFF 		bl	HAL_TIM_PeriodElapsedCallback
+ 4803              	.LVL365:
+ 4804 0138 C3E7     		b	.L269
+ 4805              	.L276:
+3981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 4806              		.loc 1 3981 7 view .LVU1531
+ 4807 013a 2368     		ldr	r3, [r4]
+ 4808 013c 6FF40252 		mvn	r2, #8320
+ 4809 0140 1A61     		str	r2, [r3, #16]
+3985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ARM GAS  /tmp/ccPLZXyC.s 			page 240
+
+
+ 4810              		.loc 1 3985 7 view .LVU1532
+ 4811 0142 2046     		mov	r0, r4
+ 4812 0144 FFF7FEFF 		bl	HAL_TIMEx_BreakCallback
+ 4813              	.LVL366:
+ 4814 0148 C1E7     		b	.L270
+ 4815              	.L277:
+3994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 4816              		.loc 1 3994 7 view .LVU1533
+ 4817 014a 2368     		ldr	r3, [r4]
+ 4818 014c 6FF48072 		mvn	r2, #256
+ 4819 0150 1A61     		str	r2, [r3, #16]
+3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4820              		.loc 1 3998 7 view .LVU1534
+ 4821 0152 2046     		mov	r0, r4
+ 4822 0154 FFF7FEFF 		bl	HAL_TIMEx_Break2Callback
+ 4823              	.LVL367:
+ 4824 0158 BFE7     		b	.L271
+ 4825              	.L278:
+4007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 4826              		.loc 1 4007 7 view .LVU1535
+ 4827 015a 2368     		ldr	r3, [r4]
+ 4828 015c 6FF04002 		mvn	r2, #64
+ 4829 0160 1A61     		str	r2, [r3, #16]
+4011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4830              		.loc 1 4011 7 view .LVU1536
+ 4831 0162 2046     		mov	r0, r4
+ 4832 0164 FFF7FEFF 		bl	HAL_TIM_TriggerCallback
+ 4833              	.LVL368:
+ 4834 0168 BDE7     		b	.L272
+ 4835              	.L279:
+4020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 4836              		.loc 1 4020 7 view .LVU1537
+ 4837 016a 2368     		ldr	r3, [r4]
+ 4838 016c 6FF02002 		mvn	r2, #32
+ 4839 0170 1A61     		str	r2, [r3, #16]
+4024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4840              		.loc 1 4024 7 view .LVU1538
+ 4841 0172 2046     		mov	r0, r4
+ 4842 0174 FFF7FEFF 		bl	HAL_TIMEx_CommutCallback
+ 4843              	.LVL369:
+4028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4844              		.loc 1 4028 1 is_stmt 0 view .LVU1539
+ 4845 0178 BBE7     		b	.L256
+ 4846              		.cfi_endproc
+ 4847              	.LFE199:
+ 4849              		.section	.text.TIM_DMATriggerCplt,"ax",%progbits
+ 4850              		.align	1
+ 4851              		.syntax unified
+ 4852              		.thumb
+ 4853              		.thumb_func
+ 4854              		.fpu fpv5-d16
+ 4856              	TIM_DMATriggerCplt:
+ 4857              	.LVL370:
+ 4858              	.LFB243:
+6893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4859              		.loc 1 6893 1 is_stmt 1 view -0
+ 4860              		.cfi_startproc
+ARM GAS  /tmp/ccPLZXyC.s 			page 241
+
+
+ 4861              		@ args = 0, pretend = 0, frame = 0
+ 4862              		@ frame_needed = 0, uses_anonymous_args = 0
+6893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4863              		.loc 1 6893 1 is_stmt 0 view .LVU1541
+ 4864 0000 08B5     		push	{r3, lr}
+ 4865              	.LCFI45:
+ 4866              		.cfi_def_cfa_offset 8
+ 4867              		.cfi_offset 3, -8
+ 4868              		.cfi_offset 14, -4
+6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4869              		.loc 1 6894 3 is_stmt 1 view .LVU1542
+6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4870              		.loc 1 6894 22 is_stmt 0 view .LVU1543
+ 4871 0002 806B     		ldr	r0, [r0, #56]
+ 4872              	.LVL371:
+6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4873              		.loc 1 6896 3 is_stmt 1 view .LVU1544
+6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4874              		.loc 1 6896 17 is_stmt 0 view .LVU1545
+ 4875 0004 836B     		ldr	r3, [r0, #56]
+6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4876              		.loc 1 6896 43 view .LVU1546
+ 4877 0006 DB69     		ldr	r3, [r3, #28]
+6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4878              		.loc 1 6896 6 view .LVU1547
+ 4879 0008 13B9     		cbnz	r3, .L281
+6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4880              		.loc 1 6898 5 is_stmt 1 view .LVU1548
+6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 4881              		.loc 1 6898 17 is_stmt 0 view .LVU1549
+ 4882 000a 0123     		movs	r3, #1
+ 4883 000c 80F83D30 		strb	r3, [r0, #61]
+ 4884              	.L281:
+6904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4885              		.loc 1 6904 3 is_stmt 1 view .LVU1550
+ 4886 0010 FFF7FEFF 		bl	HAL_TIM_TriggerCallback
+ 4887              	.LVL372:
+6906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4888              		.loc 1 6906 1 is_stmt 0 view .LVU1551
+ 4889 0014 08BD     		pop	{r3, pc}
+ 4890              		.cfi_endproc
+ 4891              	.LFE243:
+ 4893              		.section	.text.HAL_TIM_TriggerHalfCpltCallback,"ax",%progbits
+ 4894              		.align	1
+ 4895              		.weak	HAL_TIM_TriggerHalfCpltCallback
+ 4896              		.syntax unified
+ 4897              		.thumb
+ 4898              		.thumb_func
+ 4899              		.fpu fpv5-d16
+ 4901              	HAL_TIM_TriggerHalfCpltCallback:
+ 4902              	.LVL373:
+ 4903              	.LFB225:
+5920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4904              		.loc 1 5920 1 is_stmt 1 view -0
+ 4905              		.cfi_startproc
+ 4906              		@ args = 0, pretend = 0, frame = 0
+ 4907              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccPLZXyC.s 			page 242
+
+
+ 4908              		@ link register save eliminated.
+5922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4909              		.loc 1 5922 3 view .LVU1553
+5927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4910              		.loc 1 5927 1 is_stmt 0 view .LVU1554
+ 4911 0000 7047     		bx	lr
+ 4912              		.cfi_endproc
+ 4913              	.LFE225:
+ 4915              		.section	.text.TIM_DMATriggerHalfCplt,"ax",%progbits
+ 4916              		.align	1
+ 4917              		.syntax unified
+ 4918              		.thumb
+ 4919              		.thumb_func
+ 4920              		.fpu fpv5-d16
+ 4922              	TIM_DMATriggerHalfCplt:
+ 4923              	.LVL374:
+ 4924              	.LFB244:
+6914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4925              		.loc 1 6914 1 is_stmt 1 view -0
+ 4926              		.cfi_startproc
+ 4927              		@ args = 0, pretend = 0, frame = 0
+ 4928              		@ frame_needed = 0, uses_anonymous_args = 0
+6914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4929              		.loc 1 6914 1 is_stmt 0 view .LVU1556
+ 4930 0000 08B5     		push	{r3, lr}
+ 4931              	.LCFI46:
+ 4932              		.cfi_def_cfa_offset 8
+ 4933              		.cfi_offset 3, -8
+ 4934              		.cfi_offset 14, -4
+6915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4935              		.loc 1 6915 3 is_stmt 1 view .LVU1557
+ 4936              	.LVL375:
+6920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4937              		.loc 1 6920 3 view .LVU1558
+ 4938 0002 806B     		ldr	r0, [r0, #56]
+ 4939              	.LVL376:
+6920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 4940              		.loc 1 6920 3 is_stmt 0 view .LVU1559
+ 4941 0004 FFF7FEFF 		bl	HAL_TIM_TriggerHalfCpltCallback
+ 4942              	.LVL377:
+6922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4943              		.loc 1 6922 1 view .LVU1560
+ 4944 0008 08BD     		pop	{r3, pc}
+ 4945              		.cfi_endproc
+ 4946              	.LFE244:
+ 4948              		.section	.text.HAL_TIM_ErrorCallback,"ax",%progbits
+ 4949              		.align	1
+ 4950              		.weak	HAL_TIM_ErrorCallback
+ 4951              		.syntax unified
+ 4952              		.thumb
+ 4953              		.thumb_func
+ 4954              		.fpu fpv5-d16
+ 4956              	HAL_TIM_ErrorCallback:
+ 4957              	.LVL378:
+ 4958              	.LFB226:
+5935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 4959              		.loc 1 5935 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccPLZXyC.s 			page 243
+
+
+ 4960              		.cfi_startproc
+ 4961              		@ args = 0, pretend = 0, frame = 0
+ 4962              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4963              		@ link register save eliminated.
+5937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4964              		.loc 1 5937 3 view .LVU1562
+5942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4965              		.loc 1 5942 1 is_stmt 0 view .LVU1563
+ 4966 0000 7047     		bx	lr
+ 4967              		.cfi_endproc
+ 4968              	.LFE226:
+ 4970              		.section	.text.TIM_DMAError,"ax",%progbits
+ 4971              		.align	1
+ 4972              		.global	TIM_DMAError
+ 4973              		.syntax unified
+ 4974              		.thumb
+ 4975              		.thumb_func
+ 4976              		.fpu fpv5-d16
+ 4978              	TIM_DMAError:
+ 4979              	.LVL379:
+ 4980              	.LFB236:
+6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4981              		.loc 1 6613 1 is_stmt 1 view -0
+ 4982              		.cfi_startproc
+ 4983              		@ args = 0, pretend = 0, frame = 0
+ 4984              		@ frame_needed = 0, uses_anonymous_args = 0
+6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 4985              		.loc 1 6613 1 is_stmt 0 view .LVU1565
+ 4986 0000 10B5     		push	{r4, lr}
+ 4987              	.LCFI47:
+ 4988              		.cfi_def_cfa_offset 8
+ 4989              		.cfi_offset 4, -8
+ 4990              		.cfi_offset 14, -4
+6614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4991              		.loc 1 6614 3 is_stmt 1 view .LVU1566
+6614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 4992              		.loc 1 6614 22 is_stmt 0 view .LVU1567
+ 4993 0002 846B     		ldr	r4, [r0, #56]
+ 4994              	.LVL380:
+6616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4995              		.loc 1 6616 3 is_stmt 1 view .LVU1568
+6616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4996              		.loc 1 6616 25 is_stmt 0 view .LVU1569
+ 4997 0004 636A     		ldr	r3, [r4, #36]
+6616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 4998              		.loc 1 6616 6 view .LVU1570
+ 4999 0006 8342     		cmp	r3, r0
+ 5000 0008 0CD0     		beq	.L294
+6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5001              		.loc 1 6621 8 is_stmt 1 view .LVU1571
+6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5002              		.loc 1 6621 30 is_stmt 0 view .LVU1572
+ 5003 000a A36A     		ldr	r3, [r4, #40]
+6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5004              		.loc 1 6621 11 view .LVU1573
+ 5005 000c 8342     		cmp	r3, r0
+ 5006 000e 13D0     		beq	.L295
+ARM GAS  /tmp/ccPLZXyC.s 			page 244
+
+
+6626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5007              		.loc 1 6626 8 is_stmt 1 view .LVU1574
+6626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5008              		.loc 1 6626 30 is_stmt 0 view .LVU1575
+ 5009 0010 E36A     		ldr	r3, [r4, #44]
+6626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5010              		.loc 1 6626 11 view .LVU1576
+ 5011 0012 8342     		cmp	r3, r0
+ 5012 0014 16D0     		beq	.L296
+6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5013              		.loc 1 6631 8 is_stmt 1 view .LVU1577
+6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5014              		.loc 1 6631 30 is_stmt 0 view .LVU1578
+ 5015 0016 236B     		ldr	r3, [r4, #48]
+6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5016              		.loc 1 6631 11 view .LVU1579
+ 5017 0018 8342     		cmp	r3, r0
+ 5018 001a 19D0     		beq	.L297
+6638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5019              		.loc 1 6638 5 is_stmt 1 view .LVU1580
+6638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5020              		.loc 1 6638 17 is_stmt 0 view .LVU1581
+ 5021 001c 0123     		movs	r3, #1
+ 5022 001e 84F83D30 		strb	r3, [r4, #61]
+ 5023 0022 03E0     		b	.L289
+ 5024              	.L294:
+6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 5025              		.loc 1 6618 5 is_stmt 1 view .LVU1582
+6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 5026              		.loc 1 6618 19 is_stmt 0 view .LVU1583
+ 5027 0024 0123     		movs	r3, #1
+ 5028 0026 2377     		strb	r3, [r4, #28]
+6619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5029              		.loc 1 6619 5 is_stmt 1 view .LVU1584
+ 5030 0028 84F83E30 		strb	r3, [r4, #62]
+ 5031              	.L289:
+6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5032              		.loc 1 6644 3 view .LVU1585
+ 5033 002c 2046     		mov	r0, r4
+ 5034              	.LVL381:
+6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5035              		.loc 1 6644 3 is_stmt 0 view .LVU1586
+ 5036 002e FFF7FEFF 		bl	HAL_TIM_ErrorCallback
+ 5037              	.LVL382:
+6647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5038              		.loc 1 6647 3 is_stmt 1 view .LVU1587
+6647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5039              		.loc 1 6647 17 is_stmt 0 view .LVU1588
+ 5040 0032 0023     		movs	r3, #0
+ 5041 0034 2377     		strb	r3, [r4, #28]
+6648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5042              		.loc 1 6648 1 view .LVU1589
+ 5043 0036 10BD     		pop	{r4, pc}
+ 5044              	.LVL383:
+ 5045              	.L295:
+6623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 5046              		.loc 1 6623 5 is_stmt 1 view .LVU1590
+ARM GAS  /tmp/ccPLZXyC.s 			page 245
+
+
+6623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 5047              		.loc 1 6623 19 is_stmt 0 view .LVU1591
+ 5048 0038 0223     		movs	r3, #2
+ 5049 003a 2377     		strb	r3, [r4, #28]
+6624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5050              		.loc 1 6624 5 is_stmt 1 view .LVU1592
+ 5051 003c 0123     		movs	r3, #1
+ 5052 003e 84F83F30 		strb	r3, [r4, #63]
+ 5053 0042 F3E7     		b	.L289
+ 5054              	.L296:
+6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ 5055              		.loc 1 6628 5 view .LVU1593
+6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ 5056              		.loc 1 6628 19 is_stmt 0 view .LVU1594
+ 5057 0044 0423     		movs	r3, #4
+ 5058 0046 2377     		strb	r3, [r4, #28]
+6629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5059              		.loc 1 6629 5 is_stmt 1 view .LVU1595
+ 5060 0048 0123     		movs	r3, #1
+ 5061 004a 84F84030 		strb	r3, [r4, #64]
+ 5062 004e EDE7     		b	.L289
+ 5063              	.L297:
+6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ 5064              		.loc 1 6633 5 view .LVU1596
+6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ 5065              		.loc 1 6633 19 is_stmt 0 view .LVU1597
+ 5066 0050 0823     		movs	r3, #8
+ 5067 0052 2377     		strb	r3, [r4, #28]
+6634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5068              		.loc 1 6634 5 is_stmt 1 view .LVU1598
+ 5069 0054 0123     		movs	r3, #1
+ 5070 0056 84F84130 		strb	r3, [r4, #65]
+ 5071 005a E7E7     		b	.L289
+ 5072              		.cfi_endproc
+ 5073              	.LFE236:
+ 5075              		.section	.text.HAL_TIM_Base_GetState,"ax",%progbits
+ 5076              		.align	1
+ 5077              		.global	HAL_TIM_Base_GetState
+ 5078              		.syntax unified
+ 5079              		.thumb
+ 5080              		.thumb_func
+ 5081              		.fpu fpv5-d16
+ 5083              	HAL_TIM_Base_GetState:
+ 5084              	.LVL384:
+ 5085              	.LFB227:
+6493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+ 5086              		.loc 1 6493 1 view -0
+ 5087              		.cfi_startproc
+ 5088              		@ args = 0, pretend = 0, frame = 0
+ 5089              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5090              		@ link register save eliminated.
+6494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5091              		.loc 1 6494 3 view .LVU1600
+6494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5092              		.loc 1 6494 14 is_stmt 0 view .LVU1601
+ 5093 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5094              	.LVL385:
+ARM GAS  /tmp/ccPLZXyC.s 			page 246
+
+
+6495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5095              		.loc 1 6495 1 view .LVU1602
+ 5096 0004 7047     		bx	lr
+ 5097              		.cfi_endproc
+ 5098              	.LFE227:
+ 5100              		.section	.text.HAL_TIM_OC_GetState,"ax",%progbits
+ 5101              		.align	1
+ 5102              		.global	HAL_TIM_OC_GetState
+ 5103              		.syntax unified
+ 5104              		.thumb
+ 5105              		.thumb_func
+ 5106              		.fpu fpv5-d16
+ 5108              	HAL_TIM_OC_GetState:
+ 5109              	.LVL386:
+ 5110              	.LFB228:
+6503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+ 5111              		.loc 1 6503 1 is_stmt 1 view -0
+ 5112              		.cfi_startproc
+ 5113              		@ args = 0, pretend = 0, frame = 0
+ 5114              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5115              		@ link register save eliminated.
+6504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5116              		.loc 1 6504 3 view .LVU1604
+6504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5117              		.loc 1 6504 14 is_stmt 0 view .LVU1605
+ 5118 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5119              	.LVL387:
+6505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5120              		.loc 1 6505 1 view .LVU1606
+ 5121 0004 7047     		bx	lr
+ 5122              		.cfi_endproc
+ 5123              	.LFE228:
+ 5125              		.section	.text.HAL_TIM_PWM_GetState,"ax",%progbits
+ 5126              		.align	1
+ 5127              		.global	HAL_TIM_PWM_GetState
+ 5128              		.syntax unified
+ 5129              		.thumb
+ 5130              		.thumb_func
+ 5131              		.fpu fpv5-d16
+ 5133              	HAL_TIM_PWM_GetState:
+ 5134              	.LVL388:
+ 5135              	.LFB229:
+6513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+ 5136              		.loc 1 6513 1 is_stmt 1 view -0
+ 5137              		.cfi_startproc
+ 5138              		@ args = 0, pretend = 0, frame = 0
+ 5139              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5140              		@ link register save eliminated.
+6514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5141              		.loc 1 6514 3 view .LVU1608
+6514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5142              		.loc 1 6514 14 is_stmt 0 view .LVU1609
+ 5143 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5144              	.LVL389:
+6515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5145              		.loc 1 6515 1 view .LVU1610
+ 5146 0004 7047     		bx	lr
+ARM GAS  /tmp/ccPLZXyC.s 			page 247
+
+
+ 5147              		.cfi_endproc
+ 5148              	.LFE229:
+ 5150              		.section	.text.HAL_TIM_IC_GetState,"ax",%progbits
+ 5151              		.align	1
+ 5152              		.global	HAL_TIM_IC_GetState
+ 5153              		.syntax unified
+ 5154              		.thumb
+ 5155              		.thumb_func
+ 5156              		.fpu fpv5-d16
+ 5158              	HAL_TIM_IC_GetState:
+ 5159              	.LVL390:
+ 5160              	.LFB230:
+6523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+ 5161              		.loc 1 6523 1 is_stmt 1 view -0
+ 5162              		.cfi_startproc
+ 5163              		@ args = 0, pretend = 0, frame = 0
+ 5164              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5165              		@ link register save eliminated.
+6524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5166              		.loc 1 6524 3 view .LVU1612
+6524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5167              		.loc 1 6524 14 is_stmt 0 view .LVU1613
+ 5168 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5169              	.LVL391:
+6525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5170              		.loc 1 6525 1 view .LVU1614
+ 5171 0004 7047     		bx	lr
+ 5172              		.cfi_endproc
+ 5173              	.LFE230:
+ 5175              		.section	.text.HAL_TIM_OnePulse_GetState,"ax",%progbits
+ 5176              		.align	1
+ 5177              		.global	HAL_TIM_OnePulse_GetState
+ 5178              		.syntax unified
+ 5179              		.thumb
+ 5180              		.thumb_func
+ 5181              		.fpu fpv5-d16
+ 5183              	HAL_TIM_OnePulse_GetState:
+ 5184              	.LVL392:
+ 5185              	.LFB231:
+6533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+ 5186              		.loc 1 6533 1 is_stmt 1 view -0
+ 5187              		.cfi_startproc
+ 5188              		@ args = 0, pretend = 0, frame = 0
+ 5189              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5190              		@ link register save eliminated.
+6534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5191              		.loc 1 6534 3 view .LVU1616
+6534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5192              		.loc 1 6534 14 is_stmt 0 view .LVU1617
+ 5193 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5194              	.LVL393:
+6535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5195              		.loc 1 6535 1 view .LVU1618
+ 5196 0004 7047     		bx	lr
+ 5197              		.cfi_endproc
+ 5198              	.LFE231:
+ 5200              		.section	.text.HAL_TIM_Encoder_GetState,"ax",%progbits
+ARM GAS  /tmp/ccPLZXyC.s 			page 248
+
+
+ 5201              		.align	1
+ 5202              		.global	HAL_TIM_Encoder_GetState
+ 5203              		.syntax unified
+ 5204              		.thumb
+ 5205              		.thumb_func
+ 5206              		.fpu fpv5-d16
+ 5208              	HAL_TIM_Encoder_GetState:
+ 5209              	.LVL394:
+ 5210              	.LFB232:
+6543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->State;
+ 5211              		.loc 1 6543 1 is_stmt 1 view -0
+ 5212              		.cfi_startproc
+ 5213              		@ args = 0, pretend = 0, frame = 0
+ 5214              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5215              		@ link register save eliminated.
+6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5216              		.loc 1 6544 3 view .LVU1620
+6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5217              		.loc 1 6544 14 is_stmt 0 view .LVU1621
+ 5218 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5219              	.LVL395:
+6545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5220              		.loc 1 6545 1 view .LVU1622
+ 5221 0004 7047     		bx	lr
+ 5222              		.cfi_endproc
+ 5223              	.LFE232:
+ 5225              		.section	.text.HAL_TIM_GetActiveChannel,"ax",%progbits
+ 5226              		.align	1
+ 5227              		.global	HAL_TIM_GetActiveChannel
+ 5228              		.syntax unified
+ 5229              		.thumb
+ 5230              		.thumb_func
+ 5231              		.fpu fpv5-d16
+ 5233              	HAL_TIM_GetActiveChannel:
+ 5234              	.LVL396:
+ 5235              	.LFB233:
+6553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   return htim->Channel;
+ 5236              		.loc 1 6553 1 is_stmt 1 view -0
+ 5237              		.cfi_startproc
+ 5238              		@ args = 0, pretend = 0, frame = 0
+ 5239              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5240              		@ link register save eliminated.
+6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5241              		.loc 1 6554 3 view .LVU1624
+6555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5242              		.loc 1 6555 1 is_stmt 0 view .LVU1625
+ 5243 0000 007F     		ldrb	r0, [r0, #28]	@ zero_extendqisi2
+ 5244              	.LVL397:
+6555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5245              		.loc 1 6555 1 view .LVU1626
+ 5246 0002 7047     		bx	lr
+ 5247              		.cfi_endproc
+ 5248              	.LFE233:
+ 5250              		.section	.text.HAL_TIM_GetChannelState,"ax",%progbits
+ 5251              		.align	1
+ 5252              		.global	HAL_TIM_GetChannelState
+ 5253              		.syntax unified
+ARM GAS  /tmp/ccPLZXyC.s 			page 249
+
+
+ 5254              		.thumb
+ 5255              		.thumb_func
+ 5256              		.fpu fpv5-d16
+ 5258              	HAL_TIM_GetChannelState:
+ 5259              	.LVL398:
+ 5260              	.LFB234:
+6571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state;
+ 5261              		.loc 1 6571 1 is_stmt 1 view -0
+ 5262              		.cfi_startproc
+ 5263              		@ args = 0, pretend = 0, frame = 0
+ 5264              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5265              		@ link register save eliminated.
+6572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5266              		.loc 1 6572 3 view .LVU1628
+6575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5267              		.loc 1 6575 3 view .LVU1629
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5268              		.loc 1 6577 3 view .LVU1630
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5269              		.loc 1 6577 19 is_stmt 0 view .LVU1631
+ 5270 0000 19B9     		cbnz	r1, .L306
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5271              		.loc 1 6577 19 discriminator 1 view .LVU1632
+ 5272 0002 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 5273              	.LVL399:
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5274              		.loc 1 6577 19 discriminator 1 view .LVU1633
+ 5275 0006 C0B2     		uxtb	r0, r0
+ 5276 0008 7047     		bx	lr
+ 5277              	.LVL400:
+ 5278              	.L306:
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5279              		.loc 1 6577 19 discriminator 2 view .LVU1634
+ 5280 000a 0429     		cmp	r1, #4
+ 5281 000c 09D0     		beq	.L312
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5282              		.loc 1 6577 19 discriminator 5 view .LVU1635
+ 5283 000e 0829     		cmp	r1, #8
+ 5284 0010 0BD0     		beq	.L313
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5285              		.loc 1 6577 19 discriminator 8 view .LVU1636
+ 5286 0012 0C29     		cmp	r1, #12
+ 5287 0014 0DD0     		beq	.L314
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5288              		.loc 1 6577 19 discriminator 11 view .LVU1637
+ 5289 0016 1029     		cmp	r1, #16
+ 5290 0018 0FD0     		beq	.L315
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5291              		.loc 1 6577 19 discriminator 14 view .LVU1638
+ 5292 001a 90F84300 		ldrb	r0, [r0, #67]	@ zero_extendqisi2
+ 5293              	.LVL401:
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5294              		.loc 1 6577 19 discriminator 14 view .LVU1639
+ 5295 001e C0B2     		uxtb	r0, r0
+ 5296              	.LVL402:
+6579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5297              		.loc 1 6579 3 is_stmt 1 discriminator 14 view .LVU1640
+ARM GAS  /tmp/ccPLZXyC.s 			page 250
+
+
+6580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5298              		.loc 1 6580 1 is_stmt 0 discriminator 14 view .LVU1641
+ 5299 0020 7047     		bx	lr
+ 5300              	.LVL403:
+ 5301              	.L312:
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5302              		.loc 1 6577 19 discriminator 4 view .LVU1642
+ 5303 0022 90F83F00 		ldrb	r0, [r0, #63]	@ zero_extendqisi2
+ 5304              	.LVL404:
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5305              		.loc 1 6577 19 discriminator 4 view .LVU1643
+ 5306 0026 C0B2     		uxtb	r0, r0
+ 5307 0028 7047     		bx	lr
+ 5308              	.LVL405:
+ 5309              	.L313:
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5310              		.loc 1 6577 19 discriminator 7 view .LVU1644
+ 5311 002a 90F84000 		ldrb	r0, [r0, #64]	@ zero_extendqisi2
+ 5312              	.LVL406:
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5313              		.loc 1 6577 19 discriminator 7 view .LVU1645
+ 5314 002e C0B2     		uxtb	r0, r0
+ 5315 0030 7047     		bx	lr
+ 5316              	.LVL407:
+ 5317              	.L314:
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5318              		.loc 1 6577 19 discriminator 10 view .LVU1646
+ 5319 0032 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 5320              	.LVL408:
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5321              		.loc 1 6577 19 discriminator 10 view .LVU1647
+ 5322 0036 C0B2     		uxtb	r0, r0
+ 5323 0038 7047     		bx	lr
+ 5324              	.LVL409:
+ 5325              	.L315:
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5326              		.loc 1 6577 19 discriminator 13 view .LVU1648
+ 5327 003a 90F84200 		ldrb	r0, [r0, #66]	@ zero_extendqisi2
+ 5328              	.LVL410:
+6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5329              		.loc 1 6577 19 discriminator 13 view .LVU1649
+ 5330 003e C0B2     		uxtb	r0, r0
+ 5331 0040 7047     		bx	lr
+ 5332              		.cfi_endproc
+ 5333              	.LFE234:
+ 5335              		.section	.text.HAL_TIM_DMABurstState,"ax",%progbits
+ 5336              		.align	1
+ 5337              		.global	HAL_TIM_DMABurstState
+ 5338              		.syntax unified
+ 5339              		.thumb
+ 5340              		.thumb_func
+ 5341              		.fpu fpv5-d16
+ 5343              	HAL_TIM_DMABurstState:
+ 5344              	.LVL411:
+ 5345              	.LFB235:
+6588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 5346              		.loc 1 6588 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccPLZXyC.s 			page 251
+
+
+ 5347              		.cfi_startproc
+ 5348              		@ args = 0, pretend = 0, frame = 0
+ 5349              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5350              		@ link register save eliminated.
+6590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5351              		.loc 1 6590 3 view .LVU1651
+6592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5352              		.loc 1 6592 3 view .LVU1652
+6592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5353              		.loc 1 6592 14 is_stmt 0 view .LVU1653
+ 5354 0000 90F84800 		ldrb	r0, [r0, #72]	@ zero_extendqisi2
+ 5355              	.LVL412:
+6593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5356              		.loc 1 6593 1 view .LVU1654
+ 5357 0004 7047     		bx	lr
+ 5358              		.cfi_endproc
+ 5359              	.LFE235:
+ 5361              		.section	.text.TIM_Base_SetConfig,"ax",%progbits
+ 5362              		.align	1
+ 5363              		.global	TIM_Base_SetConfig
+ 5364              		.syntax unified
+ 5365              		.thumb
+ 5366              		.thumb_func
+ 5367              		.fpu fpv5-d16
+ 5369              	TIM_Base_SetConfig:
+ 5370              	.LVL413:
+ 5371              	.LFB245:
+6931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr1;
+ 5372              		.loc 1 6931 1 is_stmt 1 view -0
+ 5373              		.cfi_startproc
+ 5374              		@ args = 0, pretend = 0, frame = 0
+ 5375              		@ frame_needed = 0, uses_anonymous_args = 0
+6931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr1;
+ 5376              		.loc 1 6931 1 is_stmt 0 view .LVU1656
+ 5377 0000 30B5     		push	{r4, r5, lr}
+ 5378              	.LCFI48:
+ 5379              		.cfi_def_cfa_offset 12
+ 5380              		.cfi_offset 4, -12
+ 5381              		.cfi_offset 5, -8
+ 5382              		.cfi_offset 14, -4
+6932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpcr1 = TIMx->CR1;
+ 5383              		.loc 1 6932 3 is_stmt 1 view .LVU1657
+6933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5384              		.loc 1 6933 3 view .LVU1658
+6933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5385              		.loc 1 6933 10 is_stmt 0 view .LVU1659
+ 5386 0002 0368     		ldr	r3, [r0]
+ 5387              	.LVL414:
+6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5388              		.loc 1 6936 3 is_stmt 1 view .LVU1660
+6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5389              		.loc 1 6936 7 is_stmt 0 view .LVU1661
+ 5390 0004 3F4A     		ldr	r2, .L327
+ 5391 0006 9042     		cmp	r0, r2
+ 5392 0008 14BF     		ite	ne
+ 5393 000a 4FF0000E 		movne	lr, #0
+ 5394 000e 4FF0010E 		moveq	lr, #1
+ARM GAS  /tmp/ccPLZXyC.s 			page 252
+
+
+ 5395 0012 B0F1804F 		cmp	r0, #1073741824
+ 5396 0016 14BF     		ite	ne
+ 5397 0018 7246     		movne	r2, lr
+ 5398 001a 4EF00102 		orreq	r2, lr, #1
+6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5399              		.loc 1 6936 6 view .LVU1662
+ 5400 001e AAB9     		cbnz	r2, .L318
+6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5401              		.loc 1 6936 7 discriminator 1 view .LVU1663
+ 5402 0020 394C     		ldr	r4, .L327+4
+ 5403 0022 A042     		cmp	r0, r4
+ 5404 0024 14BF     		ite	ne
+ 5405 0026 0024     		movne	r4, #0
+ 5406 0028 0124     		moveq	r4, #1
+ 5407 002a 384D     		ldr	r5, .L327+8
+ 5408 002c A842     		cmp	r0, r5
+ 5409 002e 0DD0     		beq	.L318
+ 5410 0030 64B9     		cbnz	r4, .L318
+6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5411              		.loc 1 6936 7 discriminator 2 view .LVU1664
+ 5412 0032 04F18044 		add	r4, r4, #1073741824
+ 5413 0036 04F58234 		add	r4, r4, #66560
+ 5414 003a A042     		cmp	r0, r4
+ 5415 003c 14BF     		ite	ne
+ 5416 003e 0024     		movne	r4, #0
+ 5417 0040 0124     		moveq	r4, #1
+ 5418 0042 05F50065 		add	r5, r5, #2048
+ 5419 0046 A842     		cmp	r0, r5
+ 5420 0048 00D0     		beq	.L318
+ 5421 004a 1CB1     		cbz	r4, .L319
+ 5422              	.L318:
+6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr1 |= Structure->CounterMode;
+ 5423              		.loc 1 6939 5 is_stmt 1 view .LVU1665
+6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr1 |= Structure->CounterMode;
+ 5424              		.loc 1 6939 12 is_stmt 0 view .LVU1666
+ 5425 004c 23F07003 		bic	r3, r3, #112
+ 5426              	.LVL415:
+6940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5427              		.loc 1 6940 5 is_stmt 1 view .LVU1667
+6940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5428              		.loc 1 6940 24 is_stmt 0 view .LVU1668
+ 5429 0050 4C68     		ldr	r4, [r1, #4]
+6940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5430              		.loc 1 6940 12 view .LVU1669
+ 5431 0052 2343     		orrs	r3, r3, r4
+ 5432              	.LVL416:
+ 5433              	.L319:
+6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5434              		.loc 1 6943 3 is_stmt 1 view .LVU1670
+6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5435              		.loc 1 6943 6 is_stmt 0 view .LVU1671
+ 5436 0054 002A     		cmp	r2, #0
+ 5437 0056 33D1     		bne	.L321
+6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5438              		.loc 1 6943 7 discriminator 1 view .LVU1672
+ 5439 0058 2B4A     		ldr	r2, .L327+4
+ 5440 005a 9042     		cmp	r0, r2
+ARM GAS  /tmp/ccPLZXyC.s 			page 253
+
+
+ 5441 005c 14BF     		ite	ne
+ 5442 005e 0022     		movne	r2, #0
+ 5443 0060 0122     		moveq	r2, #1
+ 5444 0062 2A4C     		ldr	r4, .L327+8
+ 5445 0064 A042     		cmp	r0, r4
+ 5446 0066 2BD0     		beq	.L321
+ 5447 0068 52BB     		cbnz	r2, .L321
+6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5448              		.loc 1 6943 7 discriminator 2 view .LVU1673
+ 5449 006a 02F18042 		add	r2, r2, #1073741824
+ 5450 006e 02F58232 		add	r2, r2, #66560
+ 5451 0072 9042     		cmp	r0, r2
+ 5452 0074 14BF     		ite	ne
+ 5453 0076 0022     		movne	r2, #0
+ 5454 0078 0122     		moveq	r2, #1
+ 5455 007a 04F50064 		add	r4, r4, #2048
+ 5456 007e A042     		cmp	r0, r4
+ 5457 0080 1ED0     		beq	.L321
+ 5458 0082 EAB9     		cbnz	r2, .L321
+6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5459              		.loc 1 6943 7 discriminator 3 view .LVU1674
+ 5460 0084 224A     		ldr	r2, .L327+12
+ 5461 0086 9042     		cmp	r0, r2
+ 5462 0088 14BF     		ite	ne
+ 5463 008a 0022     		movne	r2, #0
+ 5464 008c 0122     		moveq	r2, #1
+ 5465 008e 04F59A34 		add	r4, r4, #78848
+ 5466 0092 A042     		cmp	r0, r4
+ 5467 0094 14D0     		beq	.L321
+ 5468 0096 9AB9     		cbnz	r2, .L321
+6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5469              		.loc 1 6943 7 discriminator 4 view .LVU1675
+ 5470 0098 1E4A     		ldr	r2, .L327+16
+ 5471 009a 9042     		cmp	r0, r2
+ 5472 009c 14BF     		ite	ne
+ 5473 009e 0022     		movne	r2, #0
+ 5474 00a0 0122     		moveq	r2, #1
+ 5475 00a2 04F50064 		add	r4, r4, #2048
+ 5476 00a6 A042     		cmp	r0, r4
+ 5477 00a8 0AD0     		beq	.L321
+ 5478 00aa 4AB9     		cbnz	r2, .L321
+6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5479              		.loc 1 6943 7 discriminator 5 view .LVU1676
+ 5480 00ac 1A4A     		ldr	r2, .L327+20
+ 5481 00ae 9042     		cmp	r0, r2
+ 5482 00b0 14BF     		ite	ne
+ 5483 00b2 0022     		movne	r2, #0
+ 5484 00b4 0122     		moveq	r2, #1
+ 5485 00b6 A4F59634 		sub	r4, r4, #76800
+ 5486 00ba A042     		cmp	r0, r4
+ 5487 00bc 00D0     		beq	.L321
+ 5488 00be 22B1     		cbz	r2, .L322
+ 5489              	.L321:
+6946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 5490              		.loc 1 6946 5 is_stmt 1 view .LVU1677
+6946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 5491              		.loc 1 6946 12 is_stmt 0 view .LVU1678
+ARM GAS  /tmp/ccPLZXyC.s 			page 254
+
+
+ 5492 00c0 23F4407C 		bic	ip, r3, #768
+ 5493              	.LVL417:
+6947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5494              		.loc 1 6947 5 is_stmt 1 view .LVU1679
+6947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5495              		.loc 1 6947 34 is_stmt 0 view .LVU1680
+ 5496 00c4 CB68     		ldr	r3, [r1, #12]
+6947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5497              		.loc 1 6947 12 view .LVU1681
+ 5498 00c6 43EA0C03 		orr	r3, r3, ip
+ 5499              	.LVL418:
+ 5500              	.L322:
+6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5501              		.loc 1 6951 3 is_stmt 1 view .LVU1682
+ 5502 00ca 23F08003 		bic	r3, r3, #128
+ 5503              	.LVL419:
+6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5504              		.loc 1 6951 3 is_stmt 0 view .LVU1683
+ 5505 00ce 4A69     		ldr	r2, [r1, #20]
+ 5506 00d0 1343     		orrs	r3, r3, r2
+ 5507              	.LVL420:
+6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5508              		.loc 1 6953 3 is_stmt 1 view .LVU1684
+6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5509              		.loc 1 6953 13 is_stmt 0 view .LVU1685
+ 5510 00d2 0360     		str	r3, [r0]
+6956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5511              		.loc 1 6956 3 is_stmt 1 view .LVU1686
+6956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5512              		.loc 1 6956 34 is_stmt 0 view .LVU1687
+ 5513 00d4 8A68     		ldr	r2, [r1, #8]
+6956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5514              		.loc 1 6956 13 view .LVU1688
+ 5515 00d6 C262     		str	r2, [r0, #44]
+6959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5516              		.loc 1 6959 3 is_stmt 1 view .LVU1689
+6959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5517              		.loc 1 6959 24 is_stmt 0 view .LVU1690
+ 5518 00d8 0A68     		ldr	r2, [r1]
+6959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5519              		.loc 1 6959 13 view .LVU1691
+ 5520 00da 8262     		str	r2, [r0, #40]
+6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5521              		.loc 1 6961 3 is_stmt 1 view .LVU1692
+6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5522              		.loc 1 6961 7 is_stmt 0 view .LVU1693
+ 5523 00dc 0F4A     		ldr	r2, .L327+24
+ 5524 00de 9042     		cmp	r0, r2
+ 5525 00e0 14BF     		ite	ne
+ 5526 00e2 7346     		movne	r3, lr
+ 5527 00e4 4EF00103 		orreq	r3, lr, #1
+ 5528              	.LVL421:
+6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5529              		.loc 1 6961 6 view .LVU1694
+ 5530 00e8 0BB1     		cbz	r3, .L324
+6964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5531              		.loc 1 6964 5 is_stmt 1 view .LVU1695
+ARM GAS  /tmp/ccPLZXyC.s 			page 255
+
+
+6964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5532              		.loc 1 6964 26 is_stmt 0 view .LVU1696
+ 5533 00ea 0B69     		ldr	r3, [r1, #16]
+6964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5534              		.loc 1 6964 15 view .LVU1697
+ 5535 00ec 0363     		str	r3, [r0, #48]
+ 5536              	.L324:
+6969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5537              		.loc 1 6969 3 is_stmt 1 view .LVU1698
+6969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5538              		.loc 1 6969 13 is_stmt 0 view .LVU1699
+ 5539 00ee 0123     		movs	r3, #1
+ 5540 00f0 4361     		str	r3, [r0, #20]
+6972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5541              		.loc 1 6972 3 is_stmt 1 view .LVU1700
+6972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5542              		.loc 1 6972 7 is_stmt 0 view .LVU1701
+ 5543 00f2 0369     		ldr	r3, [r0, #16]
+6972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5544              		.loc 1 6972 6 view .LVU1702
+ 5545 00f4 13F0010F 		tst	r3, #1
+ 5546 00f8 03D0     		beq	.L317
+6975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5547              		.loc 1 6975 5 is_stmt 1 view .LVU1703
+ 5548 00fa 0369     		ldr	r3, [r0, #16]
+ 5549 00fc 23F00103 		bic	r3, r3, #1
+ 5550 0100 0361     		str	r3, [r0, #16]
+ 5551              	.L317:
+6977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5552              		.loc 1 6977 1 is_stmt 0 view .LVU1704
+ 5553 0102 30BD     		pop	{r4, r5, pc}
+ 5554              	.L328:
+ 5555              		.align	2
+ 5556              	.L327:
+ 5557 0104 00000140 		.word	1073807360
+ 5558 0108 00080040 		.word	1073743872
+ 5559 010c 00040040 		.word	1073742848
+ 5560 0110 00440140 		.word	1073824768
+ 5561 0114 00180040 		.word	1073747968
+ 5562 0118 00200040 		.word	1073750016
+ 5563 011c 00040140 		.word	1073808384
+ 5564              		.cfi_endproc
+ 5565              	.LFE245:
+ 5567              		.section	.text.HAL_TIM_Base_Init,"ax",%progbits
+ 5568              		.align	1
+ 5569              		.global	HAL_TIM_Base_Init
+ 5570              		.syntax unified
+ 5571              		.thumb
+ 5572              		.thumb_func
+ 5573              		.fpu fpv5-d16
+ 5575              	HAL_TIM_Base_Init:
+ 5576              	.LVL422:
+ 5577              	.LFB141:
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5578              		.loc 1 270 1 is_stmt 1 view -0
+ 5579              		.cfi_startproc
+ 5580              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccPLZXyC.s 			page 256
+
+
+ 5581              		@ frame_needed = 0, uses_anonymous_args = 0
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5582              		.loc 1 272 3 view .LVU1706
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5583              		.loc 1 272 6 is_stmt 0 view .LVU1707
+ 5584 0000 60B3     		cbz	r0, .L332
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5585              		.loc 1 270 1 view .LVU1708
+ 5586 0002 10B5     		push	{r4, lr}
+ 5587              	.LCFI49:
+ 5588              		.cfi_def_cfa_offset 8
+ 5589              		.cfi_offset 4, -8
+ 5590              		.cfi_offset 14, -4
+ 5591 0004 0446     		mov	r4, r0
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 5592              		.loc 1 278 3 is_stmt 1 view .LVU1709
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 5593              		.loc 1 279 3 view .LVU1710
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ 5594              		.loc 1 280 3 view .LVU1711
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 5595              		.loc 1 281 3 view .LVU1712
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5596              		.loc 1 282 3 view .LVU1713
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5597              		.loc 1 284 3 view .LVU1714
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5598              		.loc 1 284 11 is_stmt 0 view .LVU1715
+ 5599 0006 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5600              		.loc 1 284 6 view .LVU1716
+ 5601 000a 13B3     		cbz	r3, .L337
+ 5602              	.LVL423:
+ 5603              	.L331:
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5604              		.loc 1 306 3 is_stmt 1 view .LVU1717
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5605              		.loc 1 306 15 is_stmt 0 view .LVU1718
+ 5606 000c 0223     		movs	r3, #2
+ 5607 000e 84F83D30 		strb	r3, [r4, #61]
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5608              		.loc 1 309 3 is_stmt 1 view .LVU1719
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5609              		.loc 1 309 38 is_stmt 0 view .LVU1720
+ 5610 0012 2146     		mov	r1, r4
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5611              		.loc 1 309 3 view .LVU1721
+ 5612 0014 51F8040B 		ldr	r0, [r1], #4
+ 5613 0018 FFF7FEFF 		bl	TIM_Base_SetConfig
+ 5614              	.LVL424:
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5615              		.loc 1 312 3 is_stmt 1 view .LVU1722
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5616              		.loc 1 312 23 is_stmt 0 view .LVU1723
+ 5617 001c 0123     		movs	r3, #1
+ 5618 001e 84F84830 		strb	r3, [r4, #72]
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ARM GAS  /tmp/ccPLZXyC.s 			page 257
+
+
+ 5619              		.loc 1 315 3 is_stmt 1 view .LVU1724
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5620              		.loc 1 315 3 view .LVU1725
+ 5621 0022 84F83E30 		strb	r3, [r4, #62]
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5622              		.loc 1 315 3 view .LVU1726
+ 5623 0026 84F83F30 		strb	r3, [r4, #63]
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5624              		.loc 1 315 3 view .LVU1727
+ 5625 002a 84F84030 		strb	r3, [r4, #64]
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5626              		.loc 1 315 3 view .LVU1728
+ 5627 002e 84F84130 		strb	r3, [r4, #65]
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5628              		.loc 1 315 3 view .LVU1729
+ 5629 0032 84F84230 		strb	r3, [r4, #66]
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5630              		.loc 1 315 3 view .LVU1730
+ 5631 0036 84F84330 		strb	r3, [r4, #67]
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5632              		.loc 1 315 3 view .LVU1731
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5633              		.loc 1 316 3 view .LVU1732
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5634              		.loc 1 316 3 view .LVU1733
+ 5635 003a 84F84430 		strb	r3, [r4, #68]
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5636              		.loc 1 316 3 view .LVU1734
+ 5637 003e 84F84530 		strb	r3, [r4, #69]
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5638              		.loc 1 316 3 view .LVU1735
+ 5639 0042 84F84630 		strb	r3, [r4, #70]
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5640              		.loc 1 316 3 view .LVU1736
+ 5641 0046 84F84730 		strb	r3, [r4, #71]
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5642              		.loc 1 316 3 view .LVU1737
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5643              		.loc 1 319 3 view .LVU1738
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5644              		.loc 1 319 15 is_stmt 0 view .LVU1739
+ 5645 004a 84F83D30 		strb	r3, [r4, #61]
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5646              		.loc 1 321 3 is_stmt 1 view .LVU1740
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5647              		.loc 1 321 10 is_stmt 0 view .LVU1741
+ 5648 004e 0020     		movs	r0, #0
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5649              		.loc 1 322 1 view .LVU1742
+ 5650 0050 10BD     		pop	{r4, pc}
+ 5651              	.LVL425:
+ 5652              	.L337:
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5653              		.loc 1 287 5 is_stmt 1 view .LVU1743
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5654              		.loc 1 287 16 is_stmt 0 view .LVU1744
+ 5655 0052 80F83C30 		strb	r3, [r0, #60]
+ARM GAS  /tmp/ccPLZXyC.s 			page 258
+
+
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5656              		.loc 1 301 5 is_stmt 1 view .LVU1745
+ 5657 0056 FFF7FEFF 		bl	HAL_TIM_Base_MspInit
+ 5658              	.LVL426:
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5659              		.loc 1 301 5 is_stmt 0 view .LVU1746
+ 5660 005a D7E7     		b	.L331
+ 5661              	.LVL427:
+ 5662              	.L332:
+ 5663              	.LCFI50:
+ 5664              		.cfi_def_cfa_offset 0
+ 5665              		.cfi_restore 4
+ 5666              		.cfi_restore 14
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5667              		.loc 1 274 12 view .LVU1747
+ 5668 005c 0120     		movs	r0, #1
+ 5669              	.LVL428:
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5670              		.loc 1 322 1 view .LVU1748
+ 5671 005e 7047     		bx	lr
+ 5672              		.cfi_endproc
+ 5673              	.LFE141:
+ 5675              		.section	.text.HAL_TIM_OC_Init,"ax",%progbits
+ 5676              		.align	1
+ 5677              		.global	HAL_TIM_OC_Init
+ 5678              		.syntax unified
+ 5679              		.thumb
+ 5680              		.thumb_func
+ 5681              		.fpu fpv5-d16
+ 5683              	HAL_TIM_OC_Init:
+ 5684              	.LVL429:
+ 5685              	.LFB151:
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5686              		.loc 1 654 1 is_stmt 1 view -0
+ 5687              		.cfi_startproc
+ 5688              		@ args = 0, pretend = 0, frame = 0
+ 5689              		@ frame_needed = 0, uses_anonymous_args = 0
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5690              		.loc 1 656 3 view .LVU1750
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5691              		.loc 1 656 6 is_stmt 0 view .LVU1751
+ 5692 0000 60B3     		cbz	r0, .L341
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5693              		.loc 1 654 1 view .LVU1752
+ 5694 0002 10B5     		push	{r4, lr}
+ 5695              	.LCFI51:
+ 5696              		.cfi_def_cfa_offset 8
+ 5697              		.cfi_offset 4, -8
+ 5698              		.cfi_offset 14, -4
+ 5699 0004 0446     		mov	r4, r0
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 5700              		.loc 1 662 3 is_stmt 1 view .LVU1753
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 5701              		.loc 1 663 3 view .LVU1754
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ 5702              		.loc 1 664 3 view .LVU1755
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ARM GAS  /tmp/ccPLZXyC.s 			page 259
+
+
+ 5703              		.loc 1 665 3 view .LVU1756
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5704              		.loc 1 666 3 view .LVU1757
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5705              		.loc 1 668 3 view .LVU1758
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5706              		.loc 1 668 11 is_stmt 0 view .LVU1759
+ 5707 0006 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5708              		.loc 1 668 6 view .LVU1760
+ 5709 000a 13B3     		cbz	r3, .L346
+ 5710              	.LVL430:
+ 5711              	.L340:
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5712              		.loc 1 690 3 is_stmt 1 view .LVU1761
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5713              		.loc 1 690 15 is_stmt 0 view .LVU1762
+ 5714 000c 0223     		movs	r3, #2
+ 5715 000e 84F83D30 		strb	r3, [r4, #61]
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5716              		.loc 1 693 3 is_stmt 1 view .LVU1763
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5717              		.loc 1 693 39 is_stmt 0 view .LVU1764
+ 5718 0012 2146     		mov	r1, r4
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5719              		.loc 1 693 3 view .LVU1765
+ 5720 0014 51F8040B 		ldr	r0, [r1], #4
+ 5721 0018 FFF7FEFF 		bl	TIM_Base_SetConfig
+ 5722              	.LVL431:
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5723              		.loc 1 696 3 is_stmt 1 view .LVU1766
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5724              		.loc 1 696 23 is_stmt 0 view .LVU1767
+ 5725 001c 0123     		movs	r3, #1
+ 5726 001e 84F84830 		strb	r3, [r4, #72]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5727              		.loc 1 699 3 is_stmt 1 view .LVU1768
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5728              		.loc 1 699 3 view .LVU1769
+ 5729 0022 84F83E30 		strb	r3, [r4, #62]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5730              		.loc 1 699 3 view .LVU1770
+ 5731 0026 84F83F30 		strb	r3, [r4, #63]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5732              		.loc 1 699 3 view .LVU1771
+ 5733 002a 84F84030 		strb	r3, [r4, #64]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5734              		.loc 1 699 3 view .LVU1772
+ 5735 002e 84F84130 		strb	r3, [r4, #65]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5736              		.loc 1 699 3 view .LVU1773
+ 5737 0032 84F84230 		strb	r3, [r4, #66]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5738              		.loc 1 699 3 view .LVU1774
+ 5739 0036 84F84330 		strb	r3, [r4, #67]
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5740              		.loc 1 699 3 view .LVU1775
+ARM GAS  /tmp/ccPLZXyC.s 			page 260
+
+
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5741              		.loc 1 700 3 view .LVU1776
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5742              		.loc 1 700 3 view .LVU1777
+ 5743 003a 84F84430 		strb	r3, [r4, #68]
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5744              		.loc 1 700 3 view .LVU1778
+ 5745 003e 84F84530 		strb	r3, [r4, #69]
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5746              		.loc 1 700 3 view .LVU1779
+ 5747 0042 84F84630 		strb	r3, [r4, #70]
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5748              		.loc 1 700 3 view .LVU1780
+ 5749 0046 84F84730 		strb	r3, [r4, #71]
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5750              		.loc 1 700 3 view .LVU1781
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5751              		.loc 1 703 3 view .LVU1782
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5752              		.loc 1 703 15 is_stmt 0 view .LVU1783
+ 5753 004a 84F83D30 		strb	r3, [r4, #61]
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5754              		.loc 1 705 3 is_stmt 1 view .LVU1784
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5755              		.loc 1 705 10 is_stmt 0 view .LVU1785
+ 5756 004e 0020     		movs	r0, #0
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5757              		.loc 1 706 1 view .LVU1786
+ 5758 0050 10BD     		pop	{r4, pc}
+ 5759              	.LVL432:
+ 5760              	.L346:
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5761              		.loc 1 671 5 is_stmt 1 view .LVU1787
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5762              		.loc 1 671 16 is_stmt 0 view .LVU1788
+ 5763 0052 80F83C30 		strb	r3, [r0, #60]
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5764              		.loc 1 685 5 is_stmt 1 view .LVU1789
+ 5765 0056 FFF7FEFF 		bl	HAL_TIM_OC_MspInit
+ 5766              	.LVL433:
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5767              		.loc 1 685 5 is_stmt 0 view .LVU1790
+ 5768 005a D7E7     		b	.L340
+ 5769              	.LVL434:
+ 5770              	.L341:
+ 5771              	.LCFI52:
+ 5772              		.cfi_def_cfa_offset 0
+ 5773              		.cfi_restore 4
+ 5774              		.cfi_restore 14
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5775              		.loc 1 658 12 view .LVU1791
+ 5776 005c 0120     		movs	r0, #1
+ 5777              	.LVL435:
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5778              		.loc 1 706 1 view .LVU1792
+ 5779 005e 7047     		bx	lr
+ 5780              		.cfi_endproc
+ARM GAS  /tmp/ccPLZXyC.s 			page 261
+
+
+ 5781              	.LFE151:
+ 5783              		.section	.text.HAL_TIM_PWM_Init,"ax",%progbits
+ 5784              		.align	1
+ 5785              		.global	HAL_TIM_PWM_Init
+ 5786              		.syntax unified
+ 5787              		.thumb
+ 5788              		.thumb_func
+ 5789              		.fpu fpv5-d16
+ 5791              	HAL_TIM_PWM_Init:
+ 5792              	.LVL436:
+ 5793              	.LFB161:
+1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5794              		.loc 1 1323 1 is_stmt 1 view -0
+ 5795              		.cfi_startproc
+ 5796              		@ args = 0, pretend = 0, frame = 0
+ 5797              		@ frame_needed = 0, uses_anonymous_args = 0
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5798              		.loc 1 1325 3 view .LVU1794
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5799              		.loc 1 1325 6 is_stmt 0 view .LVU1795
+ 5800 0000 60B3     		cbz	r0, .L350
+1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5801              		.loc 1 1323 1 view .LVU1796
+ 5802 0002 10B5     		push	{r4, lr}
+ 5803              	.LCFI53:
+ 5804              		.cfi_def_cfa_offset 8
+ 5805              		.cfi_offset 4, -8
+ 5806              		.cfi_offset 14, -4
+ 5807 0004 0446     		mov	r4, r0
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 5808              		.loc 1 1331 3 is_stmt 1 view .LVU1797
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 5809              		.loc 1 1332 3 view .LVU1798
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ 5810              		.loc 1 1333 3 view .LVU1799
+1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 5811              		.loc 1 1334 3 view .LVU1800
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5812              		.loc 1 1335 3 view .LVU1801
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5813              		.loc 1 1337 3 view .LVU1802
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5814              		.loc 1 1337 11 is_stmt 0 view .LVU1803
+ 5815 0006 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5816              		.loc 1 1337 6 view .LVU1804
+ 5817 000a 13B3     		cbz	r3, .L355
+ 5818              	.LVL437:
+ 5819              	.L349:
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5820              		.loc 1 1359 3 is_stmt 1 view .LVU1805
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5821              		.loc 1 1359 15 is_stmt 0 view .LVU1806
+ 5822 000c 0223     		movs	r3, #2
+ 5823 000e 84F83D30 		strb	r3, [r4, #61]
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5824              		.loc 1 1362 3 is_stmt 1 view .LVU1807
+ARM GAS  /tmp/ccPLZXyC.s 			page 262
+
+
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5825              		.loc 1 1362 38 is_stmt 0 view .LVU1808
+ 5826 0012 2146     		mov	r1, r4
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5827              		.loc 1 1362 3 view .LVU1809
+ 5828 0014 51F8040B 		ldr	r0, [r1], #4
+ 5829 0018 FFF7FEFF 		bl	TIM_Base_SetConfig
+ 5830              	.LVL438:
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5831              		.loc 1 1365 3 is_stmt 1 view .LVU1810
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5832              		.loc 1 1365 23 is_stmt 0 view .LVU1811
+ 5833 001c 0123     		movs	r3, #1
+ 5834 001e 84F84830 		strb	r3, [r4, #72]
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5835              		.loc 1 1368 3 is_stmt 1 view .LVU1812
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5836              		.loc 1 1368 3 view .LVU1813
+ 5837 0022 84F83E30 		strb	r3, [r4, #62]
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5838              		.loc 1 1368 3 view .LVU1814
+ 5839 0026 84F83F30 		strb	r3, [r4, #63]
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5840              		.loc 1 1368 3 view .LVU1815
+ 5841 002a 84F84030 		strb	r3, [r4, #64]
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5842              		.loc 1 1368 3 view .LVU1816
+ 5843 002e 84F84130 		strb	r3, [r4, #65]
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5844              		.loc 1 1368 3 view .LVU1817
+ 5845 0032 84F84230 		strb	r3, [r4, #66]
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5846              		.loc 1 1368 3 view .LVU1818
+ 5847 0036 84F84330 		strb	r3, [r4, #67]
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5848              		.loc 1 1368 3 view .LVU1819
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5849              		.loc 1 1369 3 view .LVU1820
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5850              		.loc 1 1369 3 view .LVU1821
+ 5851 003a 84F84430 		strb	r3, [r4, #68]
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5852              		.loc 1 1369 3 view .LVU1822
+ 5853 003e 84F84530 		strb	r3, [r4, #69]
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5854              		.loc 1 1369 3 view .LVU1823
+ 5855 0042 84F84630 		strb	r3, [r4, #70]
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5856              		.loc 1 1369 3 view .LVU1824
+ 5857 0046 84F84730 		strb	r3, [r4, #71]
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5858              		.loc 1 1369 3 view .LVU1825
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5859              		.loc 1 1372 3 view .LVU1826
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5860              		.loc 1 1372 15 is_stmt 0 view .LVU1827
+ 5861 004a 84F83D30 		strb	r3, [r4, #61]
+ARM GAS  /tmp/ccPLZXyC.s 			page 263
+
+
+1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5862              		.loc 1 1374 3 is_stmt 1 view .LVU1828
+1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5863              		.loc 1 1374 10 is_stmt 0 view .LVU1829
+ 5864 004e 0020     		movs	r0, #0
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5865              		.loc 1 1375 1 view .LVU1830
+ 5866 0050 10BD     		pop	{r4, pc}
+ 5867              	.LVL439:
+ 5868              	.L355:
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5869              		.loc 1 1340 5 is_stmt 1 view .LVU1831
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5870              		.loc 1 1340 16 is_stmt 0 view .LVU1832
+ 5871 0052 80F83C30 		strb	r3, [r0, #60]
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5872              		.loc 1 1354 5 is_stmt 1 view .LVU1833
+ 5873 0056 FFF7FEFF 		bl	HAL_TIM_PWM_MspInit
+ 5874              	.LVL440:
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5875              		.loc 1 1354 5 is_stmt 0 view .LVU1834
+ 5876 005a D7E7     		b	.L349
+ 5877              	.LVL441:
+ 5878              	.L350:
+ 5879              	.LCFI54:
+ 5880              		.cfi_def_cfa_offset 0
+ 5881              		.cfi_restore 4
+ 5882              		.cfi_restore 14
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5883              		.loc 1 1327 12 view .LVU1835
+ 5884 005c 0120     		movs	r0, #1
+ 5885              	.LVL442:
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5886              		.loc 1 1375 1 view .LVU1836
+ 5887 005e 7047     		bx	lr
+ 5888              		.cfi_endproc
+ 5889              	.LFE161:
+ 5891              		.section	.text.HAL_TIM_IC_Init,"ax",%progbits
+ 5892              		.align	1
+ 5893              		.global	HAL_TIM_IC_Init
+ 5894              		.syntax unified
+ 5895              		.thumb
+ 5896              		.thumb_func
+ 5897              		.fpu fpv5-d16
+ 5899              	HAL_TIM_IC_Init:
+ 5900              	.LVL443:
+ 5901              	.LFB171:
+1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5902              		.loc 1 1991 1 is_stmt 1 view -0
+ 5903              		.cfi_startproc
+ 5904              		@ args = 0, pretend = 0, frame = 0
+ 5905              		@ frame_needed = 0, uses_anonymous_args = 0
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5906              		.loc 1 1993 3 view .LVU1838
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5907              		.loc 1 1993 6 is_stmt 0 view .LVU1839
+ 5908 0000 60B3     		cbz	r0, .L359
+ARM GAS  /tmp/ccPLZXyC.s 			page 264
+
+
+1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 5909              		.loc 1 1991 1 view .LVU1840
+ 5910 0002 10B5     		push	{r4, lr}
+ 5911              	.LCFI55:
+ 5912              		.cfi_def_cfa_offset 8
+ 5913              		.cfi_offset 4, -8
+ 5914              		.cfi_offset 14, -4
+ 5915 0004 0446     		mov	r4, r0
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 5916              		.loc 1 1999 3 is_stmt 1 view .LVU1841
+2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 5917              		.loc 1 2000 3 view .LVU1842
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ 5918              		.loc 1 2001 3 view .LVU1843
+2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 5919              		.loc 1 2002 3 view .LVU1844
+2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5920              		.loc 1 2003 3 view .LVU1845
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5921              		.loc 1 2005 3 view .LVU1846
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5922              		.loc 1 2005 11 is_stmt 0 view .LVU1847
+ 5923 0006 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 5924              		.loc 1 2005 6 view .LVU1848
+ 5925 000a 13B3     		cbz	r3, .L364
+ 5926              	.LVL444:
+ 5927              	.L358:
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5928              		.loc 1 2027 3 is_stmt 1 view .LVU1849
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5929              		.loc 1 2027 15 is_stmt 0 view .LVU1850
+ 5930 000c 0223     		movs	r3, #2
+ 5931 000e 84F83D30 		strb	r3, [r4, #61]
+2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5932              		.loc 1 2030 3 is_stmt 1 view .LVU1851
+2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5933              		.loc 1 2030 38 is_stmt 0 view .LVU1852
+ 5934 0012 2146     		mov	r1, r4
+2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5935              		.loc 1 2030 3 view .LVU1853
+ 5936 0014 51F8040B 		ldr	r0, [r1], #4
+ 5937 0018 FFF7FEFF 		bl	TIM_Base_SetConfig
+ 5938              	.LVL445:
+2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5939              		.loc 1 2033 3 is_stmt 1 view .LVU1854
+2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5940              		.loc 1 2033 23 is_stmt 0 view .LVU1855
+ 5941 001c 0123     		movs	r3, #1
+ 5942 001e 84F84830 		strb	r3, [r4, #72]
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5943              		.loc 1 2036 3 is_stmt 1 view .LVU1856
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5944              		.loc 1 2036 3 view .LVU1857
+ 5945 0022 84F83E30 		strb	r3, [r4, #62]
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5946              		.loc 1 2036 3 view .LVU1858
+ARM GAS  /tmp/ccPLZXyC.s 			page 265
+
+
+ 5947 0026 84F83F30 		strb	r3, [r4, #63]
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5948              		.loc 1 2036 3 view .LVU1859
+ 5949 002a 84F84030 		strb	r3, [r4, #64]
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5950              		.loc 1 2036 3 view .LVU1860
+ 5951 002e 84F84130 		strb	r3, [r4, #65]
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5952              		.loc 1 2036 3 view .LVU1861
+ 5953 0032 84F84230 		strb	r3, [r4, #66]
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5954              		.loc 1 2036 3 view .LVU1862
+ 5955 0036 84F84330 		strb	r3, [r4, #67]
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 5956              		.loc 1 2036 3 view .LVU1863
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5957              		.loc 1 2037 3 view .LVU1864
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5958              		.loc 1 2037 3 view .LVU1865
+ 5959 003a 84F84430 		strb	r3, [r4, #68]
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5960              		.loc 1 2037 3 view .LVU1866
+ 5961 003e 84F84530 		strb	r3, [r4, #69]
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5962              		.loc 1 2037 3 view .LVU1867
+ 5963 0042 84F84630 		strb	r3, [r4, #70]
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5964              		.loc 1 2037 3 view .LVU1868
+ 5965 0046 84F84730 		strb	r3, [r4, #71]
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5966              		.loc 1 2037 3 view .LVU1869
+2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5967              		.loc 1 2040 3 view .LVU1870
+2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5968              		.loc 1 2040 15 is_stmt 0 view .LVU1871
+ 5969 004a 84F83D30 		strb	r3, [r4, #61]
+2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5970              		.loc 1 2042 3 is_stmt 1 view .LVU1872
+2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 5971              		.loc 1 2042 10 is_stmt 0 view .LVU1873
+ 5972 004e 0020     		movs	r0, #0
+2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5973              		.loc 1 2043 1 view .LVU1874
+ 5974 0050 10BD     		pop	{r4, pc}
+ 5975              	.LVL446:
+ 5976              	.L364:
+2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5977              		.loc 1 2008 5 is_stmt 1 view .LVU1875
+2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5978              		.loc 1 2008 16 is_stmt 0 view .LVU1876
+ 5979 0052 80F83C30 		strb	r3, [r0, #60]
+2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5980              		.loc 1 2022 5 is_stmt 1 view .LVU1877
+ 5981 0056 FFF7FEFF 		bl	HAL_TIM_IC_MspInit
+ 5982              	.LVL447:
+2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5983              		.loc 1 2022 5 is_stmt 0 view .LVU1878
+ARM GAS  /tmp/ccPLZXyC.s 			page 266
+
+
+ 5984 005a D7E7     		b	.L358
+ 5985              	.LVL448:
+ 5986              	.L359:
+ 5987              	.LCFI56:
+ 5988              		.cfi_def_cfa_offset 0
+ 5989              		.cfi_restore 4
+ 5990              		.cfi_restore 14
+1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 5991              		.loc 1 1995 12 view .LVU1879
+ 5992 005c 0120     		movs	r0, #1
+ 5993              	.LVL449:
+2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 5994              		.loc 1 2043 1 view .LVU1880
+ 5995 005e 7047     		bx	lr
+ 5996              		.cfi_endproc
+ 5997              	.LFE171:
+ 5999              		.section	.text.HAL_TIM_OnePulse_Init,"ax",%progbits
+ 6000              		.align	1
+ 6001              		.global	HAL_TIM_OnePulse_Init
+ 6002              		.syntax unified
+ 6003              		.thumb
+ 6004              		.thumb_func
+ 6005              		.fpu fpv5-d16
+ 6007              	HAL_TIM_OnePulse_Init:
+ 6008              	.LVL450:
+ 6009              	.LFB181:
+2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 6010              		.loc 1 2640 1 is_stmt 1 view -0
+ 6011              		.cfi_startproc
+ 6012              		@ args = 0, pretend = 0, frame = 0
+ 6013              		@ frame_needed = 0, uses_anonymous_args = 0
+2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6014              		.loc 1 2642 3 view .LVU1882
+2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6015              		.loc 1 2642 6 is_stmt 0 view .LVU1883
+ 6016 0000 50B3     		cbz	r0, .L368
+2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the TIM handle allocation */
+ 6017              		.loc 1 2640 1 view .LVU1884
+ 6018 0002 38B5     		push	{r3, r4, r5, lr}
+ 6019              	.LCFI57:
+ 6020              		.cfi_def_cfa_offset 16
+ 6021              		.cfi_offset 3, -16
+ 6022              		.cfi_offset 4, -12
+ 6023              		.cfi_offset 5, -8
+ 6024              		.cfi_offset 14, -4
+ 6025 0004 0D46     		mov	r5, r1
+ 6026 0006 0446     		mov	r4, r0
+2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 6027              		.loc 1 2648 3 is_stmt 1 view .LVU1885
+2649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 6028              		.loc 1 2649 3 view .LVU1886
+2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+ 6029              		.loc 1 2650 3 view .LVU1887
+2651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ 6030              		.loc 1 2651 3 view .LVU1888
+2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 6031              		.loc 1 2652 3 view .LVU1889
+ARM GAS  /tmp/ccPLZXyC.s 			page 267
+
+
+2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6032              		.loc 1 2653 3 view .LVU1890
+2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6033              		.loc 1 2655 3 view .LVU1891
+2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6034              		.loc 1 2655 11 is_stmt 0 view .LVU1892
+ 6035 0008 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6036              		.loc 1 2655 6 view .LVU1893
+ 6037 000c FBB1     		cbz	r3, .L373
+ 6038              	.LVL451:
+ 6039              	.L367:
+2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6040              		.loc 1 2677 3 is_stmt 1 view .LVU1894
+2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6041              		.loc 1 2677 15 is_stmt 0 view .LVU1895
+ 6042 000e 0223     		movs	r3, #2
+ 6043 0010 84F83D30 		strb	r3, [r4, #61]
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6044              		.loc 1 2680 3 is_stmt 1 view .LVU1896
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6045              		.loc 1 2680 38 is_stmt 0 view .LVU1897
+ 6046 0014 2146     		mov	r1, r4
+2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6047              		.loc 1 2680 3 view .LVU1898
+ 6048 0016 51F8040B 		ldr	r0, [r1], #4
+ 6049 001a FFF7FEFF 		bl	TIM_Base_SetConfig
+ 6050              	.LVL452:
+2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6051              		.loc 1 2683 3 is_stmt 1 view .LVU1899
+2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6052              		.loc 1 2683 7 is_stmt 0 view .LVU1900
+ 6053 001e 2268     		ldr	r2, [r4]
+2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6054              		.loc 1 2683 23 view .LVU1901
+ 6055 0020 1368     		ldr	r3, [r2]
+ 6056 0022 23F00803 		bic	r3, r3, #8
+ 6057 0026 1360     		str	r3, [r2]
+2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6058              		.loc 1 2686 3 is_stmt 1 view .LVU1902
+2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6059              		.loc 1 2686 7 is_stmt 0 view .LVU1903
+ 6060 0028 2368     		ldr	r3, [r4]
+2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6061              		.loc 1 2686 23 view .LVU1904
+ 6062 002a 1968     		ldr	r1, [r3]
+ 6063 002c 0D43     		orrs	r5, r5, r1
+ 6064              	.LVL453:
+2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6065              		.loc 1 2686 23 view .LVU1905
+ 6066 002e 1D60     		str	r5, [r3]
+2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6067              		.loc 1 2689 3 is_stmt 1 view .LVU1906
+2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6068              		.loc 1 2689 23 is_stmt 0 view .LVU1907
+ 6069 0030 0123     		movs	r3, #1
+ 6070 0032 84F84830 		strb	r3, [r4, #72]
+ARM GAS  /tmp/ccPLZXyC.s 			page 268
+
+
+2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 6071              		.loc 1 2692 3 is_stmt 1 view .LVU1908
+ 6072 0036 84F83E30 		strb	r3, [r4, #62]
+2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 6073              		.loc 1 2693 3 view .LVU1909
+ 6074 003a 84F83F30 		strb	r3, [r4, #63]
+2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 6075              		.loc 1 2694 3 view .LVU1910
+ 6076 003e 84F84430 		strb	r3, [r4, #68]
+2695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6077              		.loc 1 2695 3 view .LVU1911
+ 6078 0042 84F84530 		strb	r3, [r4, #69]
+2698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6079              		.loc 1 2698 3 view .LVU1912
+2698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6080              		.loc 1 2698 15 is_stmt 0 view .LVU1913
+ 6081 0046 84F83D30 		strb	r3, [r4, #61]
+2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 6082              		.loc 1 2700 3 is_stmt 1 view .LVU1914
+2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 6083              		.loc 1 2700 10 is_stmt 0 view .LVU1915
+ 6084 004a 0020     		movs	r0, #0
+2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6085              		.loc 1 2701 1 view .LVU1916
+ 6086 004c 38BD     		pop	{r3, r4, r5, pc}
+ 6087              	.LVL454:
+ 6088              	.L373:
+2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6089              		.loc 1 2658 5 is_stmt 1 view .LVU1917
+2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6090              		.loc 1 2658 16 is_stmt 0 view .LVU1918
+ 6091 004e 80F83C30 		strb	r3, [r0, #60]
+2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6092              		.loc 1 2672 5 is_stmt 1 view .LVU1919
+ 6093 0052 FFF7FEFF 		bl	HAL_TIM_OnePulse_MspInit
+ 6094              	.LVL455:
+2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6095              		.loc 1 2672 5 is_stmt 0 view .LVU1920
+ 6096 0056 DAE7     		b	.L367
+ 6097              	.LVL456:
+ 6098              	.L368:
+ 6099              	.LCFI58:
+ 6100              		.cfi_def_cfa_offset 0
+ 6101              		.cfi_restore 3
+ 6102              		.cfi_restore 4
+ 6103              		.cfi_restore 5
+ 6104              		.cfi_restore 14
+2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 6105              		.loc 1 2644 12 view .LVU1921
+ 6106 0058 0120     		movs	r0, #1
+ 6107              	.LVL457:
+2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6108              		.loc 1 2701 1 view .LVU1922
+ 6109 005a 7047     		bx	lr
+ 6110              		.cfi_endproc
+ 6111              	.LFE181:
+ 6113              		.section	.text.HAL_TIM_Encoder_Init,"ax",%progbits
+ARM GAS  /tmp/ccPLZXyC.s 			page 269
+
+
+ 6114              		.align	1
+ 6115              		.global	HAL_TIM_Encoder_Init
+ 6116              		.syntax unified
+ 6117              		.thumb
+ 6118              		.thumb_func
+ 6119              		.fpu fpv5-d16
+ 6121              	HAL_TIM_Encoder_Init:
+ 6122              	.LVL458:
+ 6123              	.LFB189:
+3031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 6124              		.loc 1 3031 1 is_stmt 1 view -0
+ 6125              		.cfi_startproc
+ 6126              		@ args = 0, pretend = 0, frame = 0
+ 6127              		@ frame_needed = 0, uses_anonymous_args = 0
+3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 6128              		.loc 1 3032 3 view .LVU1924
+3033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 6129              		.loc 1 3033 3 view .LVU1925
+3034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6130              		.loc 1 3034 3 view .LVU1926
+3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6131              		.loc 1 3037 3 view .LVU1927
+3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6132              		.loc 1 3037 6 is_stmt 0 view .LVU1928
+ 6133 0000 0028     		cmp	r0, #0
+ 6134 0002 4FD0     		beq	.L377
+3031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 6135              		.loc 1 3031 1 view .LVU1929
+ 6136 0004 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 6137              	.LCFI59:
+ 6138              		.cfi_def_cfa_offset 24
+ 6139              		.cfi_offset 3, -24
+ 6140              		.cfi_offset 4, -20
+ 6141              		.cfi_offset 5, -16
+ 6142              		.cfi_offset 6, -12
+ 6143              		.cfi_offset 7, -8
+ 6144              		.cfi_offset 14, -4
+ 6145 0006 0D46     		mov	r5, r1
+ 6146 0008 0446     		mov	r4, r0
+3043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 6147              		.loc 1 3043 3 is_stmt 1 view .LVU1930
+3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 6148              		.loc 1 3044 3 view .LVU1931
+3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 6149              		.loc 1 3045 3 view .LVU1932
+3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ 6150              		.loc 1 3046 3 view .LVU1933
+3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ 6151              		.loc 1 3047 3 view .LVU1934
+3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ 6152              		.loc 1 3048 3 view .LVU1935
+3049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+ 6153              		.loc 1 3049 3 view .LVU1936
+3050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+ 6154              		.loc 1 3050 3 view .LVU1937
+3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ 6155              		.loc 1 3051 3 view .LVU1938
+ARM GAS  /tmp/ccPLZXyC.s 			page 270
+
+
+3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ 6156              		.loc 1 3052 3 view .LVU1939
+3053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ 6157              		.loc 1 3053 3 view .LVU1940
+3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+ 6158              		.loc 1 3054 3 view .LVU1941
+3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ 6159              		.loc 1 3055 3 view .LVU1942
+3056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6160              		.loc 1 3056 3 view .LVU1943
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6161              		.loc 1 3058 3 view .LVU1944
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6162              		.loc 1 3058 11 is_stmt 0 view .LVU1945
+ 6163 000a 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6164              		.loc 1 3058 6 view .LVU1946
+ 6165 000e 002B     		cmp	r3, #0
+ 6166 0010 43D0     		beq	.L382
+ 6167              	.LVL459:
+ 6168              	.L376:
+3080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6169              		.loc 1 3080 3 is_stmt 1 view .LVU1947
+3080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6170              		.loc 1 3080 15 is_stmt 0 view .LVU1948
+ 6171 0012 0223     		movs	r3, #2
+ 6172 0014 84F83D30 		strb	r3, [r4, #61]
+3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6173              		.loc 1 3083 3 is_stmt 1 view .LVU1949
+3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6174              		.loc 1 3083 7 is_stmt 0 view .LVU1950
+ 6175 0018 2268     		ldr	r2, [r4]
+3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6176              		.loc 1 3083 24 view .LVU1951
+ 6177 001a 9168     		ldr	r1, [r2, #8]
+ 6178 001c 224B     		ldr	r3, .L383
+ 6179 001e 0B40     		ands	r3, r3, r1
+ 6180 0020 9360     		str	r3, [r2, #8]
+3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6181              		.loc 1 3086 3 is_stmt 1 view .LVU1952
+3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6182              		.loc 1 3086 38 is_stmt 0 view .LVU1953
+ 6183 0022 2146     		mov	r1, r4
+3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6184              		.loc 1 3086 3 view .LVU1954
+ 6185 0024 51F8040B 		ldr	r0, [r1], #4
+ 6186 0028 FFF7FEFF 		bl	TIM_Base_SetConfig
+ 6187              	.LVL460:
+3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6188              		.loc 1 3089 3 is_stmt 1 view .LVU1955
+3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6189              		.loc 1 3089 17 is_stmt 0 view .LVU1956
+ 6190 002c 2068     		ldr	r0, [r4]
+3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6191              		.loc 1 3089 11 view .LVU1957
+ 6192 002e 8168     		ldr	r1, [r0, #8]
+ 6193              	.LVL461:
+ARM GAS  /tmp/ccPLZXyC.s 			page 271
+
+
+3092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6194              		.loc 1 3092 3 is_stmt 1 view .LVU1958
+3092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6195              		.loc 1 3092 12 is_stmt 0 view .LVU1959
+ 6196 0030 8369     		ldr	r3, [r0, #24]
+ 6197              	.LVL462:
+3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6198              		.loc 1 3095 3 is_stmt 1 view .LVU1960
+3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6199              		.loc 1 3095 11 is_stmt 0 view .LVU1961
+ 6200 0032 026A     		ldr	r2, [r0, #32]
+ 6201              	.LVL463:
+3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6202              		.loc 1 3098 3 is_stmt 1 view .LVU1962
+3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6203              		.loc 1 3098 21 is_stmt 0 view .LVU1963
+ 6204 0034 2E68     		ldr	r6, [r5]
+3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6205              		.loc 1 3098 11 view .LVU1964
+ 6206 0036 0E43     		orrs	r6, r6, r1
+ 6207              	.LVL464:
+3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+ 6208              		.loc 1 3101 3 is_stmt 1 view .LVU1965
+3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+ 6209              		.loc 1 3101 12 is_stmt 0 view .LVU1966
+ 6210 0038 1C49     		ldr	r1, .L383+4
+ 6211 003a 1940     		ands	r1, r1, r3
+ 6212              	.LVL465:
+3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6213              		.loc 1 3102 3 is_stmt 1 view .LVU1967
+3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6214              		.loc 1 3102 23 is_stmt 0 view .LVU1968
+ 6215 003c AB68     		ldr	r3, [r5, #8]
+3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6216              		.loc 1 3102 38 view .LVU1969
+ 6217 003e AF69     		ldr	r7, [r5, #24]
+ 6218 0040 43EA0723 		orr	r3, r3, r7, lsl #8
+3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6219              		.loc 1 3102 12 view .LVU1970
+ 6220 0044 43EA010C 		orr	ip, r3, r1
+ 6221              	.LVL466:
+3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ 6222              		.loc 1 3105 3 is_stmt 1 view .LVU1971
+3106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ 6223              		.loc 1 3106 3 view .LVU1972
+3106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ 6224              		.loc 1 3106 12 is_stmt 0 view .LVU1973
+ 6225 0048 194B     		ldr	r3, .L383+8
+ 6226 004a 0CEA0303 		and	r3, ip, r3
+ 6227              	.LVL467:
+3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 6228              		.loc 1 3107 3 is_stmt 1 view .LVU1974
+3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 6229              		.loc 1 3107 22 is_stmt 0 view .LVU1975
+ 6230 004e E968     		ldr	r1, [r5, #12]
+3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 6231              		.loc 1 3107 37 view .LVU1976
+ARM GAS  /tmp/ccPLZXyC.s 			page 272
+
+
+ 6232 0050 EF69     		ldr	r7, [r5, #28]
+ 6233 0052 41EA0721 		orr	r1, r1, r7, lsl #8
+3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 6234              		.loc 1 3107 12 view .LVU1977
+ 6235 0056 1943     		orrs	r1, r1, r3
+ 6236              	.LVL468:
+3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6237              		.loc 1 3108 3 is_stmt 1 view .LVU1978
+3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6238              		.loc 1 3108 52 is_stmt 0 view .LVU1979
+ 6239 0058 2B6A     		ldr	r3, [r5, #32]
+3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6240              		.loc 1 3108 64 view .LVU1980
+ 6241 005a 1B03     		lsls	r3, r3, #12
+3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6242              		.loc 1 3108 42 view .LVU1981
+ 6243 005c 2F69     		ldr	r7, [r5, #16]
+ 6244 005e 43EA0713 		orr	r3, r3, r7, lsl #4
+3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6245              		.loc 1 3108 12 view .LVU1982
+ 6246 0062 0B43     		orrs	r3, r3, r1
+ 6247              	.LVL469:
+3111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ 6248              		.loc 1 3111 3 is_stmt 1 view .LVU1983
+3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+ 6249              		.loc 1 3112 3 view .LVU1984
+3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+ 6250              		.loc 1 3112 11 is_stmt 0 view .LVU1985
+ 6251 0064 22F0AA01 		bic	r1, r2, #170
+ 6252              	.LVL470:
+3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6253              		.loc 1 3113 3 is_stmt 1 view .LVU1986
+3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6254              		.loc 1 3113 21 is_stmt 0 view .LVU1987
+ 6255 0068 6A68     		ldr	r2, [r5, #4]
+3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6256              		.loc 1 3113 45 view .LVU1988
+ 6257 006a 6D69     		ldr	r5, [r5, #20]
+ 6258              	.LVL471:
+3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6259              		.loc 1 3113 35 view .LVU1989
+ 6260 006c 42EA0512 		orr	r2, r2, r5, lsl #4
+3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6261              		.loc 1 3113 11 view .LVU1990
+ 6262 0070 0A43     		orrs	r2, r2, r1
+ 6263              	.LVL472:
+3116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6264              		.loc 1 3116 3 is_stmt 1 view .LVU1991
+3116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6265              		.loc 1 3116 24 is_stmt 0 view .LVU1992
+ 6266 0072 8660     		str	r6, [r0, #8]
+3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6267              		.loc 1 3119 3 is_stmt 1 view .LVU1993
+3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6268              		.loc 1 3119 7 is_stmt 0 view .LVU1994
+ 6269 0074 2168     		ldr	r1, [r4]
+3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 273
+
+
+ 6270              		.loc 1 3119 25 view .LVU1995
+ 6271 0076 8B61     		str	r3, [r1, #24]
+3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6272              		.loc 1 3122 3 is_stmt 1 view .LVU1996
+3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6273              		.loc 1 3122 7 is_stmt 0 view .LVU1997
+ 6274 0078 2368     		ldr	r3, [r4]
+ 6275              	.LVL473:
+3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6276              		.loc 1 3122 24 view .LVU1998
+ 6277 007a 1A62     		str	r2, [r3, #32]
+ 6278              	.LVL474:
+3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6279              		.loc 1 3125 3 is_stmt 1 view .LVU1999
+3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6280              		.loc 1 3125 23 is_stmt 0 view .LVU2000
+ 6281 007c 0123     		movs	r3, #1
+ 6282 007e 84F84830 		strb	r3, [r4, #72]
+3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 6283              		.loc 1 3128 3 is_stmt 1 view .LVU2001
+ 6284 0082 84F83E30 		strb	r3, [r4, #62]
+3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 6285              		.loc 1 3129 3 view .LVU2002
+ 6286 0086 84F83F30 		strb	r3, [r4, #63]
+3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 6287              		.loc 1 3130 3 view .LVU2003
+ 6288 008a 84F84430 		strb	r3, [r4, #68]
+3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6289              		.loc 1 3131 3 view .LVU2004
+ 6290 008e 84F84530 		strb	r3, [r4, #69]
+3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6291              		.loc 1 3134 3 view .LVU2005
+3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6292              		.loc 1 3134 15 is_stmt 0 view .LVU2006
+ 6293 0092 84F83D30 		strb	r3, [r4, #61]
+3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 6294              		.loc 1 3136 3 is_stmt 1 view .LVU2007
+3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 6295              		.loc 1 3136 10 is_stmt 0 view .LVU2008
+ 6296 0096 0020     		movs	r0, #0
+3137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6297              		.loc 1 3137 1 view .LVU2009
+ 6298 0098 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 6299              	.LVL475:
+ 6300              	.L382:
+3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6301              		.loc 1 3061 5 is_stmt 1 view .LVU2010
+3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6302              		.loc 1 3061 16 is_stmt 0 view .LVU2011
+ 6303 009a 80F83C30 		strb	r3, [r0, #60]
+3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6304              		.loc 1 3075 5 is_stmt 1 view .LVU2012
+ 6305 009e FFF7FEFF 		bl	HAL_TIM_Encoder_MspInit
+ 6306              	.LVL476:
+3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 6307              		.loc 1 3075 5 is_stmt 0 view .LVU2013
+ 6308 00a2 B6E7     		b	.L376
+ARM GAS  /tmp/ccPLZXyC.s 			page 274
+
+
+ 6309              	.LVL477:
+ 6310              	.L377:
+ 6311              	.LCFI60:
+ 6312              		.cfi_def_cfa_offset 0
+ 6313              		.cfi_restore 3
+ 6314              		.cfi_restore 4
+ 6315              		.cfi_restore 5
+ 6316              		.cfi_restore 6
+ 6317              		.cfi_restore 7
+ 6318              		.cfi_restore 14
+3039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 6319              		.loc 1 3039 12 view .LVU2014
+ 6320 00a4 0120     		movs	r0, #1
+ 6321              	.LVL478:
+3137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6322              		.loc 1 3137 1 view .LVU2015
+ 6323 00a6 7047     		bx	lr
+ 6324              	.L384:
+ 6325              		.align	2
+ 6326              	.L383:
+ 6327 00a8 F8BFFEFF 		.word	-81928
+ 6328 00ac FCFCFFFF 		.word	-772
+ 6329 00b0 0303FFFF 		.word	-64765
+ 6330              		.cfi_endproc
+ 6331              	.LFE189:
+ 6333              		.section	.text.TIM_OC2_SetConfig,"ax",%progbits
+ 6334              		.align	1
+ 6335              		.global	TIM_OC2_SetConfig
+ 6336              		.syntax unified
+ 6337              		.thumb
+ 6338              		.thumb_func
+ 6339              		.fpu fpv5-d16
+ 6341              	TIM_OC2_SetConfig:
+ 6342              	.LVL479:
+ 6343              	.LFB247:
+7062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 6344              		.loc 1 7062 1 is_stmt 1 view -0
+ 6345              		.cfi_startproc
+ 6346              		@ args = 0, pretend = 0, frame = 0
+ 6347              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6348              		@ link register save eliminated.
+7062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmrx;
+ 6349              		.loc 1 7062 1 is_stmt 0 view .LVU2017
+ 6350 0000 70B4     		push	{r4, r5, r6}
+ 6351              	.LCFI61:
+ 6352              		.cfi_def_cfa_offset 12
+ 6353              		.cfi_offset 4, -12
+ 6354              		.cfi_offset 5, -8
+ 6355              		.cfi_offset 6, -4
+7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 6356              		.loc 1 7063 3 is_stmt 1 view .LVU2018
+7064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpcr2;
+ 6357              		.loc 1 7064 3 view .LVU2019
+7065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6358              		.loc 1 7065 3 view .LVU2020
+7068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6359              		.loc 1 7068 3 view .LVU2021
+ARM GAS  /tmp/ccPLZXyC.s 			page 275
+
+
+7068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6360              		.loc 1 7068 11 is_stmt 0 view .LVU2022
+ 6361 0002 036A     		ldr	r3, [r0, #32]
+ 6362              	.LVL480:
+7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6363              		.loc 1 7071 3 is_stmt 1 view .LVU2023
+7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6364              		.loc 1 7071 14 is_stmt 0 view .LVU2024
+ 6365 0004 026A     		ldr	r2, [r0, #32]
+ 6366 0006 22F01002 		bic	r2, r2, #16
+ 6367 000a 0262     		str	r2, [r0, #32]
+7074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6368              		.loc 1 7074 3 is_stmt 1 view .LVU2025
+7074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6369              		.loc 1 7074 10 is_stmt 0 view .LVU2026
+ 6370 000c 4268     		ldr	r2, [r0, #4]
+ 6371              	.LVL481:
+7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6372              		.loc 1 7077 3 is_stmt 1 view .LVU2027
+7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6373              		.loc 1 7077 12 is_stmt 0 view .LVU2028
+ 6374 000e 8569     		ldr	r5, [r0, #24]
+ 6375              	.LVL482:
+7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmrx &= ~TIM_CCMR1_CC2S;
+ 6376              		.loc 1 7080 3 is_stmt 1 view .LVU2029
+7081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6377              		.loc 1 7081 3 view .LVU2030
+7081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6378              		.loc 1 7081 12 is_stmt 0 view .LVU2031
+ 6379 0010 144C     		ldr	r4, .L389
+ 6380 0012 2C40     		ands	r4, r4, r5
+ 6381              	.LVL483:
+7084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6382              		.loc 1 7084 3 is_stmt 1 view .LVU2032
+7084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6383              		.loc 1 7084 25 is_stmt 0 view .LVU2033
+ 6384 0014 0D68     		ldr	r5, [r1]
+7084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6385              		.loc 1 7084 12 view .LVU2034
+ 6386 0016 44EA0525 		orr	r5, r4, r5, lsl #8
+ 6387              	.LVL484:
+7087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+ 6388              		.loc 1 7087 3 is_stmt 1 view .LVU2035
+7087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Output Compare Polarity */
+ 6389              		.loc 1 7087 11 is_stmt 0 view .LVU2036
+ 6390 001a 23F02003 		bic	r3, r3, #32
+ 6391              	.LVL485:
+7089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6392              		.loc 1 7089 3 is_stmt 1 view .LVU2037
+7089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6393              		.loc 1 7089 24 is_stmt 0 view .LVU2038
+ 6394 001e 8C68     		ldr	r4, [r1, #8]
+7089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6395              		.loc 1 7089 11 view .LVU2039
+ 6396 0020 43EA0413 		orr	r3, r3, r4, lsl #4
+ 6397              	.LVL486:
+7091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 276
+
+
+ 6398              		.loc 1 7091 3 is_stmt 1 view .LVU2040
+7091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6399              		.loc 1 7091 7 is_stmt 0 view .LVU2041
+ 6400 0024 104C     		ldr	r4, .L389+4
+ 6401 0026 114E     		ldr	r6, .L389+8
+7091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6402              		.loc 1 7091 6 view .LVU2042
+ 6403 0028 B042     		cmp	r0, r6
+ 6404 002a 18BF     		it	ne
+ 6405 002c A042     		cmpne	r0, r4
+ 6406 002e 0CBF     		ite	eq
+ 6407 0030 0124     		moveq	r4, #1
+ 6408 0032 0024     		movne	r4, #0
+ 6409 0034 06D1     		bne	.L386
+7093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6410              		.loc 1 7093 5 is_stmt 1 view .LVU2043
+7096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output N Polarity */
+ 6411              		.loc 1 7096 5 view .LVU2044
+7096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output N Polarity */
+ 6412              		.loc 1 7096 13 is_stmt 0 view .LVU2045
+ 6413 0036 23F08003 		bic	r3, r3, #128
+ 6414              	.LVL487:
+7098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output N State */
+ 6415              		.loc 1 7098 5 is_stmt 1 view .LVU2046
+7098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output N State */
+ 6416              		.loc 1 7098 26 is_stmt 0 view .LVU2047
+ 6417 003a CE68     		ldr	r6, [r1, #12]
+7098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Reset the Output N State */
+ 6418              		.loc 1 7098 13 view .LVU2048
+ 6419 003c 43EA0613 		orr	r3, r3, r6, lsl #4
+ 6420              	.LVL488:
+7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 6421              		.loc 1 7100 5 is_stmt 1 view .LVU2049
+7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 6422              		.loc 1 7100 13 is_stmt 0 view .LVU2050
+ 6423 0040 23F04003 		bic	r3, r3, #64
+ 6424              	.LVL489:
+ 6425              	.L386:
+7103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6426              		.loc 1 7103 3 is_stmt 1 view .LVU2051
+7103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6427              		.loc 1 7103 6 is_stmt 0 view .LVU2052
+ 6428 0044 3CB1     		cbz	r4, .L387
+7106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+ 6429              		.loc 1 7106 5 is_stmt 1 view .LVU2053
+7107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6430              		.loc 1 7107 5 view .LVU2054
+7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpcr2 &= ~TIM_CR2_OIS2N;
+ 6431              		.loc 1 7110 5 view .LVU2055
+ 6432              	.LVL490:
+7111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output Idle state */
+ 6433              		.loc 1 7111 5 view .LVU2056
+7111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output Idle state */
+ 6434              		.loc 1 7111 12 is_stmt 0 view .LVU2057
+ 6435 0046 22F44062 		bic	r2, r2, #3072
+ 6436              	.LVL491:
+7113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output N Idle state */
+ARM GAS  /tmp/ccPLZXyC.s 			page 277
+
+
+ 6437              		.loc 1 7113 5 is_stmt 1 view .LVU2058
+7113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output N Idle state */
+ 6438              		.loc 1 7113 25 is_stmt 0 view .LVU2059
+ 6439 004a 4C69     		ldr	r4, [r1, #20]
+7113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     /* Set the Output N Idle state */
+ 6440              		.loc 1 7113 12 view .LVU2060
+ 6441 004c 42EA8402 		orr	r2, r2, r4, lsl #2
+ 6442              	.LVL492:
+7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 6443              		.loc 1 7115 5 is_stmt 1 view .LVU2061
+7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 6444              		.loc 1 7115 25 is_stmt 0 view .LVU2062
+ 6445 0050 8C69     		ldr	r4, [r1, #24]
+7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 6446              		.loc 1 7115 12 view .LVU2063
+ 6447 0052 42EA8402 		orr	r2, r2, r4, lsl #2
+ 6448              	.LVL493:
+ 6449              	.L387:
+7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6450              		.loc 1 7119 3 is_stmt 1 view .LVU2064
+7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6451              		.loc 1 7119 13 is_stmt 0 view .LVU2065
+ 6452 0056 4260     		str	r2, [r0, #4]
+7122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6453              		.loc 1 7122 3 is_stmt 1 view .LVU2066
+7122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6454              		.loc 1 7122 15 is_stmt 0 view .LVU2067
+ 6455 0058 8561     		str	r5, [r0, #24]
+7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6456              		.loc 1 7125 3 is_stmt 1 view .LVU2068
+7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6457              		.loc 1 7125 25 is_stmt 0 view .LVU2069
+ 6458 005a 4A68     		ldr	r2, [r1, #4]
+ 6459              	.LVL494:
+7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6460              		.loc 1 7125 14 view .LVU2070
+ 6461 005c 8263     		str	r2, [r0, #56]
+7128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 6462              		.loc 1 7128 3 is_stmt 1 view .LVU2071
+7128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 6463              		.loc 1 7128 14 is_stmt 0 view .LVU2072
+ 6464 005e 0362     		str	r3, [r0, #32]
+7129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6465              		.loc 1 7129 1 view .LVU2073
+ 6466 0060 70BC     		pop	{r4, r5, r6}
+ 6467              	.LCFI62:
+ 6468              		.cfi_restore 6
+ 6469              		.cfi_restore 5
+ 6470              		.cfi_restore 4
+ 6471              		.cfi_def_cfa_offset 0
+ 6472              	.LVL495:
+7129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6473              		.loc 1 7129 1 view .LVU2074
+ 6474 0062 7047     		bx	lr
+ 6475              	.L390:
+ 6476              		.align	2
+ 6477              	.L389:
+ARM GAS  /tmp/ccPLZXyC.s 			page 278
+
+
+ 6478 0064 FF8CFFFE 		.word	-16806657
+ 6479 0068 00000140 		.word	1073807360
+ 6480 006c 00040140 		.word	1073808384
+ 6481              		.cfi_endproc
+ 6482              	.LFE247:
+ 6484              		.section	.text.HAL_TIM_OC_ConfigChannel,"ax",%progbits
+ 6485              		.align	1
+ 6486              		.global	HAL_TIM_OC_ConfigChannel
+ 6487              		.syntax unified
+ 6488              		.thumb
+ 6489              		.thumb_func
+ 6490              		.fpu fpv5-d16
+ 6492              	HAL_TIM_OC_ConfigChannel:
+ 6493              	.LVL496:
+ 6494              	.LFB200:
+4071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6495              		.loc 1 4071 1 is_stmt 1 view -0
+ 6496              		.cfi_startproc
+ 6497              		@ args = 0, pretend = 0, frame = 0
+ 6498              		@ frame_needed = 0, uses_anonymous_args = 0
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6499              		.loc 1 4072 3 view .LVU2076
+4075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+ 6500              		.loc 1 4075 3 view .LVU2077
+4076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ 6501              		.loc 1 4076 3 view .LVU2078
+4077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6502              		.loc 1 4077 3 view .LVU2079
+4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6503              		.loc 1 4080 3 view .LVU2080
+4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6504              		.loc 1 4080 3 view .LVU2081
+ 6505 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 6506 0004 012B     		cmp	r3, #1
+ 6507 0006 36D0     		beq	.L401
+4071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6508              		.loc 1 4071 1 is_stmt 0 discriminator 2 view .LVU2082
+ 6509 0008 10B5     		push	{r4, lr}
+ 6510              	.LCFI63:
+ 6511              		.cfi_def_cfa_offset 8
+ 6512              		.cfi_offset 4, -8
+ 6513              		.cfi_offset 14, -4
+ 6514 000a 0446     		mov	r4, r0
+4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6515              		.loc 1 4080 3 is_stmt 1 discriminator 2 view .LVU2083
+ 6516 000c 0123     		movs	r3, #1
+ 6517 000e 80F83C30 		strb	r3, [r0, #60]
+4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6518              		.loc 1 4080 3 discriminator 2 view .LVU2084
+4082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6519              		.loc 1 4082 3 discriminator 2 view .LVU2085
+ 6520 0012 142A     		cmp	r2, #20
+ 6521 0014 2AD8     		bhi	.L402
+ 6522 0016 DFE802F0 		tbb	[pc, r2]
+ 6523              	.L395:
+ 6524 001a 0B       		.byte	(.L400-.L395)/2
+ 6525 001b 29       		.byte	(.L402-.L395)/2
+ARM GAS  /tmp/ccPLZXyC.s 			page 279
+
+
+ 6526 001c 29       		.byte	(.L402-.L395)/2
+ 6527 001d 29       		.byte	(.L402-.L395)/2
+ 6528 001e 10       		.byte	(.L399-.L395)/2
+ 6529 001f 29       		.byte	(.L402-.L395)/2
+ 6530 0020 29       		.byte	(.L402-.L395)/2
+ 6531 0021 29       		.byte	(.L402-.L395)/2
+ 6532 0022 15       		.byte	(.L398-.L395)/2
+ 6533 0023 29       		.byte	(.L402-.L395)/2
+ 6534 0024 29       		.byte	(.L402-.L395)/2
+ 6535 0025 29       		.byte	(.L402-.L395)/2
+ 6536 0026 1A       		.byte	(.L397-.L395)/2
+ 6537 0027 29       		.byte	(.L402-.L395)/2
+ 6538 0028 29       		.byte	(.L402-.L395)/2
+ 6539 0029 29       		.byte	(.L402-.L395)/2
+ 6540 002a 1F       		.byte	(.L396-.L395)/2
+ 6541 002b 29       		.byte	(.L402-.L395)/2
+ 6542 002c 29       		.byte	(.L402-.L395)/2
+ 6543 002d 29       		.byte	(.L402-.L395)/2
+ 6544 002e 24       		.byte	(.L394-.L395)/2
+ 6545 002f 00       		.p2align 1
+ 6546              	.L400:
+4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6547              		.loc 1 4087 7 view .LVU2086
+4090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6548              		.loc 1 4090 7 view .LVU2087
+ 6549 0030 0068     		ldr	r0, [r0]
+ 6550              	.LVL497:
+4090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6551              		.loc 1 4090 7 is_stmt 0 view .LVU2088
+ 6552 0032 FFF7FEFF 		bl	TIM_OC1_SetConfig
+ 6553              	.LVL498:
+4091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6554              		.loc 1 4091 7 is_stmt 1 view .LVU2089
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6555              		.loc 1 4072 21 is_stmt 0 view .LVU2090
+ 6556 0036 0020     		movs	r0, #0
+4091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6557              		.loc 1 4091 7 view .LVU2091
+ 6558 0038 19E0     		b	.L393
+ 6559              	.LVL499:
+ 6560              	.L399:
+4097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6561              		.loc 1 4097 7 is_stmt 1 view .LVU2092
+4100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6562              		.loc 1 4100 7 view .LVU2093
+ 6563 003a 0068     		ldr	r0, [r0]
+ 6564              	.LVL500:
+4100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6565              		.loc 1 4100 7 is_stmt 0 view .LVU2094
+ 6566 003c FFF7FEFF 		bl	TIM_OC2_SetConfig
+ 6567              	.LVL501:
+4101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6568              		.loc 1 4101 7 is_stmt 1 view .LVU2095
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6569              		.loc 1 4072 21 is_stmt 0 view .LVU2096
+ 6570 0040 0020     		movs	r0, #0
+4101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ARM GAS  /tmp/ccPLZXyC.s 			page 280
+
+
+ 6571              		.loc 1 4101 7 view .LVU2097
+ 6572 0042 14E0     		b	.L393
+ 6573              	.LVL502:
+ 6574              	.L398:
+4107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6575              		.loc 1 4107 7 is_stmt 1 view .LVU2098
+4110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6576              		.loc 1 4110 7 view .LVU2099
+ 6577 0044 0068     		ldr	r0, [r0]
+ 6578              	.LVL503:
+4110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6579              		.loc 1 4110 7 is_stmt 0 view .LVU2100
+ 6580 0046 FFF7FEFF 		bl	TIM_OC3_SetConfig
+ 6581              	.LVL504:
+4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6582              		.loc 1 4111 7 is_stmt 1 view .LVU2101
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6583              		.loc 1 4072 21 is_stmt 0 view .LVU2102
+ 6584 004a 0020     		movs	r0, #0
+4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6585              		.loc 1 4111 7 view .LVU2103
+ 6586 004c 0FE0     		b	.L393
+ 6587              	.LVL505:
+ 6588              	.L397:
+4117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6589              		.loc 1 4117 7 is_stmt 1 view .LVU2104
+4120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6590              		.loc 1 4120 7 view .LVU2105
+ 6591 004e 0068     		ldr	r0, [r0]
+ 6592              	.LVL506:
+4120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6593              		.loc 1 4120 7 is_stmt 0 view .LVU2106
+ 6594 0050 FFF7FEFF 		bl	TIM_OC4_SetConfig
+ 6595              	.LVL507:
+4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6596              		.loc 1 4121 7 is_stmt 1 view .LVU2107
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6597              		.loc 1 4072 21 is_stmt 0 view .LVU2108
+ 6598 0054 0020     		movs	r0, #0
+4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6599              		.loc 1 4121 7 view .LVU2109
+ 6600 0056 0AE0     		b	.L393
+ 6601              	.LVL508:
+ 6602              	.L396:
+4127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6603              		.loc 1 4127 7 is_stmt 1 view .LVU2110
+4130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6604              		.loc 1 4130 7 view .LVU2111
+ 6605 0058 0068     		ldr	r0, [r0]
+ 6606              	.LVL509:
+4130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6607              		.loc 1 4130 7 is_stmt 0 view .LVU2112
+ 6608 005a FFF7FEFF 		bl	TIM_OC5_SetConfig
+ 6609              	.LVL510:
+4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6610              		.loc 1 4131 7 is_stmt 1 view .LVU2113
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 281
+
+
+ 6611              		.loc 1 4072 21 is_stmt 0 view .LVU2114
+ 6612 005e 0020     		movs	r0, #0
+4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6613              		.loc 1 4131 7 view .LVU2115
+ 6614 0060 05E0     		b	.L393
+ 6615              	.LVL511:
+ 6616              	.L394:
+4137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6617              		.loc 1 4137 7 is_stmt 1 view .LVU2116
+4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6618              		.loc 1 4140 7 view .LVU2117
+ 6619 0062 0068     		ldr	r0, [r0]
+ 6620              	.LVL512:
+4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6621              		.loc 1 4140 7 is_stmt 0 view .LVU2118
+ 6622 0064 FFF7FEFF 		bl	TIM_OC6_SetConfig
+ 6623              	.LVL513:
+4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6624              		.loc 1 4141 7 is_stmt 1 view .LVU2119
+4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6625              		.loc 1 4072 21 is_stmt 0 view .LVU2120
+ 6626 0068 0020     		movs	r0, #0
+4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6627              		.loc 1 4141 7 view .LVU2121
+ 6628 006a 00E0     		b	.L393
+ 6629              	.LVL514:
+ 6630              	.L402:
+4082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6631              		.loc 1 4082 3 view .LVU2122
+ 6632 006c 0120     		movs	r0, #1
+ 6633              	.LVL515:
+ 6634              	.L393:
+4149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6635              		.loc 1 4149 3 is_stmt 1 view .LVU2123
+4149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6636              		.loc 1 4149 3 view .LVU2124
+ 6637 006e 0023     		movs	r3, #0
+ 6638 0070 84F83C30 		strb	r3, [r4, #60]
+4149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6639              		.loc 1 4149 3 view .LVU2125
+4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 6640              		.loc 1 4151 3 view .LVU2126
+4152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6641              		.loc 1 4152 1 is_stmt 0 view .LVU2127
+ 6642 0074 10BD     		pop	{r4, pc}
+ 6643              	.LVL516:
+ 6644              	.L401:
+ 6645              	.LCFI64:
+ 6646              		.cfi_def_cfa_offset 0
+ 6647              		.cfi_restore 4
+ 6648              		.cfi_restore 14
+4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6649              		.loc 1 4080 3 view .LVU2128
+ 6650 0076 0220     		movs	r0, #2
+ 6651              	.LVL517:
+4152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6652              		.loc 1 4152 1 view .LVU2129
+ARM GAS  /tmp/ccPLZXyC.s 			page 282
+
+
+ 6653 0078 7047     		bx	lr
+ 6654              		.cfi_endproc
+ 6655              	.LFE200:
+ 6657              		.section	.text.HAL_TIM_PWM_ConfigChannel,"ax",%progbits
+ 6658              		.align	1
+ 6659              		.global	HAL_TIM_PWM_ConfigChannel
+ 6660              		.syntax unified
+ 6661              		.thumb
+ 6662              		.thumb_func
+ 6663              		.fpu fpv5-d16
+ 6665              	HAL_TIM_PWM_ConfigChannel:
+ 6666              	.LVL518:
+ 6667              	.LFB202:
+4271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6668              		.loc 1 4271 1 is_stmt 1 view -0
+ 6669              		.cfi_startproc
+ 6670              		@ args = 0, pretend = 0, frame = 0
+ 6671              		@ frame_needed = 0, uses_anonymous_args = 0
+4271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 6672              		.loc 1 4271 1 is_stmt 0 view .LVU2131
+ 6673 0000 38B5     		push	{r3, r4, r5, lr}
+ 6674              	.LCFI65:
+ 6675              		.cfi_def_cfa_offset 16
+ 6676              		.cfi_offset 3, -16
+ 6677              		.cfi_offset 4, -12
+ 6678              		.cfi_offset 5, -8
+ 6679              		.cfi_offset 14, -4
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6680              		.loc 1 4272 3 is_stmt 1 view .LVU2132
+ 6681              	.LVL519:
+4275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ 6682              		.loc 1 4275 3 view .LVU2133
+4276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ 6683              		.loc 1 4276 3 view .LVU2134
+4277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+ 6684              		.loc 1 4277 3 view .LVU2135
+4278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6685              		.loc 1 4278 3 view .LVU2136
+4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6686              		.loc 1 4281 3 view .LVU2137
+4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6687              		.loc 1 4281 3 view .LVU2138
+ 6688 0002 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 6689 0006 012B     		cmp	r3, #1
+ 6690 0008 00F09580 		beq	.L417
+ 6691 000c 0446     		mov	r4, r0
+ 6692 000e 0D46     		mov	r5, r1
+4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6693              		.loc 1 4281 3 discriminator 2 view .LVU2139
+ 6694 0010 0123     		movs	r3, #1
+ 6695 0012 80F83C30 		strb	r3, [r0, #60]
+4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6696              		.loc 1 4281 3 discriminator 2 view .LVU2140
+4283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6697              		.loc 1 4283 3 discriminator 2 view .LVU2141
+ 6698 0016 142A     		cmp	r2, #20
+ 6699 0018 00F28880 		bhi	.L418
+ARM GAS  /tmp/ccPLZXyC.s 			page 283
+
+
+ 6700 001c DFE802F0 		tbb	[pc, r2]
+ 6701              	.L411:
+ 6702 0020 0B       		.byte	(.L416-.L411)/2
+ 6703 0021 86       		.byte	(.L418-.L411)/2
+ 6704 0022 86       		.byte	(.L418-.L411)/2
+ 6705 0023 86       		.byte	(.L418-.L411)/2
+ 6706 0024 1F       		.byte	(.L415-.L411)/2
+ 6707 0025 86       		.byte	(.L418-.L411)/2
+ 6708 0026 86       		.byte	(.L418-.L411)/2
+ 6709 0027 86       		.byte	(.L418-.L411)/2
+ 6710 0028 34       		.byte	(.L414-.L411)/2
+ 6711 0029 86       		.byte	(.L418-.L411)/2
+ 6712 002a 86       		.byte	(.L418-.L411)/2
+ 6713 002b 86       		.byte	(.L418-.L411)/2
+ 6714 002c 48       		.byte	(.L413-.L411)/2
+ 6715 002d 86       		.byte	(.L418-.L411)/2
+ 6716 002e 86       		.byte	(.L418-.L411)/2
+ 6717 002f 86       		.byte	(.L418-.L411)/2
+ 6718 0030 5D       		.byte	(.L412-.L411)/2
+ 6719 0031 86       		.byte	(.L418-.L411)/2
+ 6720 0032 86       		.byte	(.L418-.L411)/2
+ 6721 0033 86       		.byte	(.L418-.L411)/2
+ 6722 0034 71       		.byte	(.L410-.L411)/2
+ 6723 0035 00       		.p2align 1
+ 6724              	.L416:
+4288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6725              		.loc 1 4288 7 view .LVU2142
+4291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6726              		.loc 1 4291 7 view .LVU2143
+ 6727 0036 0068     		ldr	r0, [r0]
+ 6728              	.LVL520:
+4291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6729              		.loc 1 4291 7 is_stmt 0 view .LVU2144
+ 6730 0038 FFF7FEFF 		bl	TIM_OC1_SetConfig
+ 6731              	.LVL521:
+4294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6732              		.loc 1 4294 7 is_stmt 1 view .LVU2145
+4294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6733              		.loc 1 4294 11 is_stmt 0 view .LVU2146
+ 6734 003c 2268     		ldr	r2, [r4]
+4294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6735              		.loc 1 4294 29 view .LVU2147
+ 6736 003e 9369     		ldr	r3, [r2, #24]
+ 6737 0040 43F00803 		orr	r3, r3, #8
+ 6738 0044 9361     		str	r3, [r2, #24]
+4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ 6739              		.loc 1 4297 7 is_stmt 1 view .LVU2148
+4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ 6740              		.loc 1 4297 11 is_stmt 0 view .LVU2149
+ 6741 0046 2268     		ldr	r2, [r4]
+4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ 6742              		.loc 1 4297 29 view .LVU2150
+ 6743 0048 9369     		ldr	r3, [r2, #24]
+ 6744 004a 23F00403 		bic	r3, r3, #4
+ 6745 004e 9361     		str	r3, [r2, #24]
+4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6746              		.loc 1 4298 7 is_stmt 1 view .LVU2151
+ARM GAS  /tmp/ccPLZXyC.s 			page 284
+
+
+4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6747              		.loc 1 4298 11 is_stmt 0 view .LVU2152
+ 6748 0050 2268     		ldr	r2, [r4]
+4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6749              		.loc 1 4298 29 view .LVU2153
+ 6750 0052 9369     		ldr	r3, [r2, #24]
+4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6751              		.loc 1 4298 39 view .LVU2154
+ 6752 0054 2969     		ldr	r1, [r5, #16]
+4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6753              		.loc 1 4298 29 view .LVU2155
+ 6754 0056 0B43     		orrs	r3, r3, r1
+ 6755 0058 9361     		str	r3, [r2, #24]
+4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6756              		.loc 1 4299 7 is_stmt 1 view .LVU2156
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6757              		.loc 1 4272 21 is_stmt 0 view .LVU2157
+ 6758 005a 0020     		movs	r0, #0
+4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6759              		.loc 1 4299 7 view .LVU2158
+ 6760 005c 67E0     		b	.L409
+ 6761              	.LVL522:
+ 6762              	.L415:
+4305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6763              		.loc 1 4305 7 is_stmt 1 view .LVU2159
+4308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6764              		.loc 1 4308 7 view .LVU2160
+ 6765 005e 0068     		ldr	r0, [r0]
+ 6766              	.LVL523:
+4308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6767              		.loc 1 4308 7 is_stmt 0 view .LVU2161
+ 6768 0060 FFF7FEFF 		bl	TIM_OC2_SetConfig
+ 6769              	.LVL524:
+4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6770              		.loc 1 4311 7 is_stmt 1 view .LVU2162
+4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6771              		.loc 1 4311 11 is_stmt 0 view .LVU2163
+ 6772 0064 2268     		ldr	r2, [r4]
+4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6773              		.loc 1 4311 29 view .LVU2164
+ 6774 0066 9369     		ldr	r3, [r2, #24]
+ 6775 0068 43F40063 		orr	r3, r3, #2048
+ 6776 006c 9361     		str	r3, [r2, #24]
+4314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 6777              		.loc 1 4314 7 is_stmt 1 view .LVU2165
+4314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 6778              		.loc 1 4314 11 is_stmt 0 view .LVU2166
+ 6779 006e 2268     		ldr	r2, [r4]
+4314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 6780              		.loc 1 4314 29 view .LVU2167
+ 6781 0070 9369     		ldr	r3, [r2, #24]
+ 6782 0072 23F48063 		bic	r3, r3, #1024
+ 6783 0076 9361     		str	r3, [r2, #24]
+4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6784              		.loc 1 4315 7 is_stmt 1 view .LVU2168
+4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6785              		.loc 1 4315 11 is_stmt 0 view .LVU2169
+ARM GAS  /tmp/ccPLZXyC.s 			page 285
+
+
+ 6786 0078 2268     		ldr	r2, [r4]
+4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6787              		.loc 1 4315 29 view .LVU2170
+ 6788 007a 9369     		ldr	r3, [r2, #24]
+4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6789              		.loc 1 4315 39 view .LVU2171
+ 6790 007c 2969     		ldr	r1, [r5, #16]
+4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6791              		.loc 1 4315 29 view .LVU2172
+ 6792 007e 43EA0123 		orr	r3, r3, r1, lsl #8
+ 6793 0082 9361     		str	r3, [r2, #24]
+4316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6794              		.loc 1 4316 7 is_stmt 1 view .LVU2173
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6795              		.loc 1 4272 21 is_stmt 0 view .LVU2174
+ 6796 0084 0020     		movs	r0, #0
+4316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6797              		.loc 1 4316 7 view .LVU2175
+ 6798 0086 52E0     		b	.L409
+ 6799              	.LVL525:
+ 6800              	.L414:
+4322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6801              		.loc 1 4322 7 is_stmt 1 view .LVU2176
+4325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6802              		.loc 1 4325 7 view .LVU2177
+ 6803 0088 0068     		ldr	r0, [r0]
+ 6804              	.LVL526:
+4325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6805              		.loc 1 4325 7 is_stmt 0 view .LVU2178
+ 6806 008a FFF7FEFF 		bl	TIM_OC3_SetConfig
+ 6807              	.LVL527:
+4328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6808              		.loc 1 4328 7 is_stmt 1 view .LVU2179
+4328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6809              		.loc 1 4328 11 is_stmt 0 view .LVU2180
+ 6810 008e 2268     		ldr	r2, [r4]
+4328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6811              		.loc 1 4328 29 view .LVU2181
+ 6812 0090 D369     		ldr	r3, [r2, #28]
+ 6813 0092 43F00803 		orr	r3, r3, #8
+ 6814 0096 D361     		str	r3, [r2, #28]
+4331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ 6815              		.loc 1 4331 7 is_stmt 1 view .LVU2182
+4331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ 6816              		.loc 1 4331 11 is_stmt 0 view .LVU2183
+ 6817 0098 2268     		ldr	r2, [r4]
+4331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ 6818              		.loc 1 4331 29 view .LVU2184
+ 6819 009a D369     		ldr	r3, [r2, #28]
+ 6820 009c 23F00403 		bic	r3, r3, #4
+ 6821 00a0 D361     		str	r3, [r2, #28]
+4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6822              		.loc 1 4332 7 is_stmt 1 view .LVU2185
+4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6823              		.loc 1 4332 11 is_stmt 0 view .LVU2186
+ 6824 00a2 2268     		ldr	r2, [r4]
+4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ARM GAS  /tmp/ccPLZXyC.s 			page 286
+
+
+ 6825              		.loc 1 4332 29 view .LVU2187
+ 6826 00a4 D369     		ldr	r3, [r2, #28]
+4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6827              		.loc 1 4332 39 view .LVU2188
+ 6828 00a6 2969     		ldr	r1, [r5, #16]
+4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6829              		.loc 1 4332 29 view .LVU2189
+ 6830 00a8 0B43     		orrs	r3, r3, r1
+ 6831 00aa D361     		str	r3, [r2, #28]
+4333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6832              		.loc 1 4333 7 is_stmt 1 view .LVU2190
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6833              		.loc 1 4272 21 is_stmt 0 view .LVU2191
+ 6834 00ac 0020     		movs	r0, #0
+4333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6835              		.loc 1 4333 7 view .LVU2192
+ 6836 00ae 3EE0     		b	.L409
+ 6837              	.LVL528:
+ 6838              	.L413:
+4339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6839              		.loc 1 4339 7 is_stmt 1 view .LVU2193
+4342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6840              		.loc 1 4342 7 view .LVU2194
+ 6841 00b0 0068     		ldr	r0, [r0]
+ 6842              	.LVL529:
+4342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6843              		.loc 1 4342 7 is_stmt 0 view .LVU2195
+ 6844 00b2 FFF7FEFF 		bl	TIM_OC4_SetConfig
+ 6845              	.LVL530:
+4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6846              		.loc 1 4345 7 is_stmt 1 view .LVU2196
+4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6847              		.loc 1 4345 11 is_stmt 0 view .LVU2197
+ 6848 00b6 2268     		ldr	r2, [r4]
+4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6849              		.loc 1 4345 29 view .LVU2198
+ 6850 00b8 D369     		ldr	r3, [r2, #28]
+ 6851 00ba 43F40063 		orr	r3, r3, #2048
+ 6852 00be D361     		str	r3, [r2, #28]
+4348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ 6853              		.loc 1 4348 7 is_stmt 1 view .LVU2199
+4348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ 6854              		.loc 1 4348 11 is_stmt 0 view .LVU2200
+ 6855 00c0 2268     		ldr	r2, [r4]
+4348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ 6856              		.loc 1 4348 29 view .LVU2201
+ 6857 00c2 D369     		ldr	r3, [r2, #28]
+ 6858 00c4 23F48063 		bic	r3, r3, #1024
+ 6859 00c8 D361     		str	r3, [r2, #28]
+4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6860              		.loc 1 4349 7 is_stmt 1 view .LVU2202
+4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6861              		.loc 1 4349 11 is_stmt 0 view .LVU2203
+ 6862 00ca 2268     		ldr	r2, [r4]
+4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6863              		.loc 1 4349 29 view .LVU2204
+ 6864 00cc D369     		ldr	r3, [r2, #28]
+ARM GAS  /tmp/ccPLZXyC.s 			page 287
+
+
+4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6865              		.loc 1 4349 39 view .LVU2205
+ 6866 00ce 2969     		ldr	r1, [r5, #16]
+4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6867              		.loc 1 4349 29 view .LVU2206
+ 6868 00d0 43EA0123 		orr	r3, r3, r1, lsl #8
+ 6869 00d4 D361     		str	r3, [r2, #28]
+4350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6870              		.loc 1 4350 7 is_stmt 1 view .LVU2207
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6871              		.loc 1 4272 21 is_stmt 0 view .LVU2208
+ 6872 00d6 0020     		movs	r0, #0
+4350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6873              		.loc 1 4350 7 view .LVU2209
+ 6874 00d8 29E0     		b	.L409
+ 6875              	.LVL531:
+ 6876              	.L412:
+4356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6877              		.loc 1 4356 7 is_stmt 1 view .LVU2210
+4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6878              		.loc 1 4359 7 view .LVU2211
+ 6879 00da 0068     		ldr	r0, [r0]
+ 6880              	.LVL532:
+4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6881              		.loc 1 4359 7 is_stmt 0 view .LVU2212
+ 6882 00dc FFF7FEFF 		bl	TIM_OC5_SetConfig
+ 6883              	.LVL533:
+4362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6884              		.loc 1 4362 7 is_stmt 1 view .LVU2213
+4362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6885              		.loc 1 4362 11 is_stmt 0 view .LVU2214
+ 6886 00e0 2268     		ldr	r2, [r4]
+4362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6887              		.loc 1 4362 29 view .LVU2215
+ 6888 00e2 536D     		ldr	r3, [r2, #84]
+ 6889 00e4 43F00803 		orr	r3, r3, #8
+ 6890 00e8 5365     		str	r3, [r2, #84]
+4365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ 6891              		.loc 1 4365 7 is_stmt 1 view .LVU2216
+4365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ 6892              		.loc 1 4365 11 is_stmt 0 view .LVU2217
+ 6893 00ea 2268     		ldr	r2, [r4]
+4365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ 6894              		.loc 1 4365 29 view .LVU2218
+ 6895 00ec 536D     		ldr	r3, [r2, #84]
+ 6896 00ee 23F00403 		bic	r3, r3, #4
+ 6897 00f2 5365     		str	r3, [r2, #84]
+4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6898              		.loc 1 4366 7 is_stmt 1 view .LVU2219
+4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6899              		.loc 1 4366 11 is_stmt 0 view .LVU2220
+ 6900 00f4 2268     		ldr	r2, [r4]
+4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6901              		.loc 1 4366 29 view .LVU2221
+ 6902 00f6 536D     		ldr	r3, [r2, #84]
+4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6903              		.loc 1 4366 39 view .LVU2222
+ARM GAS  /tmp/ccPLZXyC.s 			page 288
+
+
+ 6904 00f8 2969     		ldr	r1, [r5, #16]
+4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6905              		.loc 1 4366 29 view .LVU2223
+ 6906 00fa 0B43     		orrs	r3, r3, r1
+ 6907 00fc 5365     		str	r3, [r2, #84]
+4367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6908              		.loc 1 4367 7 is_stmt 1 view .LVU2224
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6909              		.loc 1 4272 21 is_stmt 0 view .LVU2225
+ 6910 00fe 0020     		movs	r0, #0
+4367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6911              		.loc 1 4367 7 view .LVU2226
+ 6912 0100 15E0     		b	.L409
+ 6913              	.LVL534:
+ 6914              	.L410:
+4373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6915              		.loc 1 4373 7 is_stmt 1 view .LVU2227
+4376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6916              		.loc 1 4376 7 view .LVU2228
+ 6917 0102 0068     		ldr	r0, [r0]
+ 6918              	.LVL535:
+4376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6919              		.loc 1 4376 7 is_stmt 0 view .LVU2229
+ 6920 0104 FFF7FEFF 		bl	TIM_OC6_SetConfig
+ 6921              	.LVL536:
+4379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6922              		.loc 1 4379 7 is_stmt 1 view .LVU2230
+4379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6923              		.loc 1 4379 11 is_stmt 0 view .LVU2231
+ 6924 0108 2268     		ldr	r2, [r4]
+4379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6925              		.loc 1 4379 29 view .LVU2232
+ 6926 010a 536D     		ldr	r3, [r2, #84]
+ 6927 010c 43F40063 		orr	r3, r3, #2048
+ 6928 0110 5365     		str	r3, [r2, #84]
+4382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ 6929              		.loc 1 4382 7 is_stmt 1 view .LVU2233
+4382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ 6930              		.loc 1 4382 11 is_stmt 0 view .LVU2234
+ 6931 0112 2268     		ldr	r2, [r4]
+4382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ 6932              		.loc 1 4382 29 view .LVU2235
+ 6933 0114 536D     		ldr	r3, [r2, #84]
+ 6934 0116 23F48063 		bic	r3, r3, #1024
+ 6935 011a 5365     		str	r3, [r2, #84]
+4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6936              		.loc 1 4383 7 is_stmt 1 view .LVU2236
+4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6937              		.loc 1 4383 11 is_stmt 0 view .LVU2237
+ 6938 011c 2268     		ldr	r2, [r4]
+4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6939              		.loc 1 4383 29 view .LVU2238
+ 6940 011e 536D     		ldr	r3, [r2, #84]
+4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 6941              		.loc 1 4383 39 view .LVU2239
+ 6942 0120 2969     		ldr	r1, [r5, #16]
+4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ARM GAS  /tmp/ccPLZXyC.s 			page 289
+
+
+ 6943              		.loc 1 4383 29 view .LVU2240
+ 6944 0122 43EA0123 		orr	r3, r3, r1, lsl #8
+ 6945 0126 5365     		str	r3, [r2, #84]
+4384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6946              		.loc 1 4384 7 is_stmt 1 view .LVU2241
+4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6947              		.loc 1 4272 21 is_stmt 0 view .LVU2242
+ 6948 0128 0020     		movs	r0, #0
+4384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 6949              		.loc 1 4384 7 view .LVU2243
+ 6950 012a 00E0     		b	.L409
+ 6951              	.LVL537:
+ 6952              	.L418:
+4283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 6953              		.loc 1 4283 3 view .LVU2244
+ 6954 012c 0120     		movs	r0, #1
+ 6955              	.LVL538:
+ 6956              	.L409:
+4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6957              		.loc 1 4392 3 is_stmt 1 view .LVU2245
+4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6958              		.loc 1 4392 3 view .LVU2246
+ 6959 012e 0023     		movs	r3, #0
+ 6960 0130 84F83C30 		strb	r3, [r4, #60]
+4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6961              		.loc 1 4392 3 view .LVU2247
+4394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 6962              		.loc 1 4394 3 view .LVU2248
+ 6963              	.LVL539:
+ 6964              	.L408:
+4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6965              		.loc 1 4395 1 is_stmt 0 view .LVU2249
+ 6966 0134 38BD     		pop	{r3, r4, r5, pc}
+ 6967              	.LVL540:
+ 6968              	.L417:
+4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6969              		.loc 1 4281 3 view .LVU2250
+ 6970 0136 0220     		movs	r0, #2
+ 6971              	.LVL541:
+4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 6972              		.loc 1 4281 3 view .LVU2251
+ 6973 0138 FCE7     		b	.L408
+ 6974              		.cfi_endproc
+ 6975              	.LFE202:
+ 6977              		.section	.text.TIM_TI1_SetConfig,"ax",%progbits
+ 6978              		.align	1
+ 6979              		.global	TIM_TI1_SetConfig
+ 6980              		.syntax unified
+ 6981              		.thumb
+ 6982              		.thumb_func
+ 6983              		.fpu fpv5-d16
+ 6985              	TIM_TI1_SetConfig:
+ 6986              	.LVL542:
+ 6987              	.LFB253:
+7518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 6988              		.loc 1 7518 1 is_stmt 1 view -0
+ 6989              		.cfi_startproc
+ARM GAS  /tmp/ccPLZXyC.s 			page 290
+
+
+ 6990              		@ args = 0, pretend = 0, frame = 0
+ 6991              		@ frame_needed = 0, uses_anonymous_args = 0
+ 6992              		@ link register save eliminated.
+7518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 6993              		.loc 1 7518 1 is_stmt 0 view .LVU2253
+ 6994 0000 70B4     		push	{r4, r5, r6}
+ 6995              	.LCFI66:
+ 6996              		.cfi_def_cfa_offset 12
+ 6997              		.cfi_offset 4, -12
+ 6998              		.cfi_offset 5, -8
+ 6999              		.cfi_offset 6, -4
+ 7000 0002 9446     		mov	ip, r2
+7519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 7001              		.loc 1 7519 3 is_stmt 1 view .LVU2254
+7520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7002              		.loc 1 7520 3 view .LVU2255
+7523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC1E;
+ 7003              		.loc 1 7523 3 view .LVU2256
+7523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~TIM_CCER_CC1E;
+ 7004              		.loc 1 7523 11 is_stmt 0 view .LVU2257
+ 7005 0004 066A     		ldr	r6, [r0, #32]
+ 7006              	.LVL543:
+7524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+ 7007              		.loc 1 7524 3 is_stmt 1 view .LVU2258
+7524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 = TIMx->CCMR1;
+ 7008              		.loc 1 7524 14 is_stmt 0 view .LVU2259
+ 7009 0006 046A     		ldr	r4, [r0, #32]
+ 7010 0008 24F00104 		bic	r4, r4, #1
+ 7011 000c 0462     		str	r4, [r0, #32]
+7525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7012              		.loc 1 7525 3 is_stmt 1 view .LVU2260
+7525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7013              		.loc 1 7525 12 is_stmt 0 view .LVU2261
+ 7014 000e 8469     		ldr	r4, [r0, #24]
+ 7015              	.LVL544:
+7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7016              		.loc 1 7528 3 is_stmt 1 view .LVU2262
+7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7017              		.loc 1 7528 7 is_stmt 0 view .LVU2263
+ 7018 0010 1D4D     		ldr	r5, .L424
+ 7019 0012 B0F1804F 		cmp	r0, #1073741824
+ 7020 0016 18BF     		it	ne
+ 7021 0018 A842     		cmpne	r0, r5
+ 7022 001a 23D0     		beq	.L421
+7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7023              		.loc 1 7528 7 discriminator 2 view .LVU2264
+ 7024 001c 1B4A     		ldr	r2, .L424+4
+ 7025              	.LVL545:
+7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7026              		.loc 1 7528 7 discriminator 2 view .LVU2265
+ 7027 001e 9042     		cmp	r0, r2
+ 7028 0020 14BF     		ite	ne
+ 7029 0022 0022     		movne	r2, #0
+ 7030 0024 0122     		moveq	r2, #1
+ 7031 0026 A5F57C45 		sub	r5, r5, #64512
+ 7032 002a A842     		cmp	r0, r5
+ 7033 002c 1AD0     		beq	.L421
+ARM GAS  /tmp/ccPLZXyC.s 			page 291
+
+
+ 7034 002e CAB9     		cbnz	r2, .L421
+7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7035              		.loc 1 7528 7 discriminator 4 view .LVU2266
+ 7036 0030 02F18042 		add	r2, r2, #1073741824
+ 7037 0034 02F58232 		add	r2, r2, #66560
+ 7038 0038 9042     		cmp	r0, r2
+ 7039 003a 14BF     		ite	ne
+ 7040 003c 0022     		movne	r2, #0
+ 7041 003e 0122     		moveq	r2, #1
+ 7042 0040 05F50065 		add	r5, r5, #2048
+ 7043 0044 A842     		cmp	r0, r5
+ 7044 0046 0DD0     		beq	.L421
+ 7045 0048 62B9     		cbnz	r2, .L421
+7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7046              		.loc 1 7528 7 discriminator 6 view .LVU2267
+ 7047 004a 114A     		ldr	r2, .L424+8
+ 7048 004c 9042     		cmp	r0, r2
+ 7049 004e 14BF     		ite	ne
+ 7050 0050 0022     		movne	r2, #0
+ 7051 0052 0122     		moveq	r2, #1
+ 7052 0054 05F59A35 		add	r5, r5, #78848
+ 7053 0058 A842     		cmp	r0, r5
+ 7054 005a 03D0     		beq	.L421
+ 7055 005c 12B9     		cbnz	r2, .L421
+7535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7056              		.loc 1 7535 5 is_stmt 1 view .LVU2268
+7535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7057              		.loc 1 7535 14 is_stmt 0 view .LVU2269
+ 7058 005e 44F00102 		orr	r2, r4, #1
+ 7059              	.LVL546:
+7535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7060              		.loc 1 7535 14 view .LVU2270
+ 7061 0062 03E0     		b	.L422
+ 7062              	.LVL547:
+ 7063              	.L421:
+7530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccmr1 |= TIM_ICSelection;
+ 7064              		.loc 1 7530 5 is_stmt 1 view .LVU2271
+7530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     tmpccmr1 |= TIM_ICSelection;
+ 7065              		.loc 1 7530 14 is_stmt 0 view .LVU2272
+ 7066 0064 24F00302 		bic	r2, r4, #3
+ 7067              	.LVL548:
+7531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7068              		.loc 1 7531 5 is_stmt 1 view .LVU2273
+7531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7069              		.loc 1 7531 14 is_stmt 0 view .LVU2274
+ 7070 0068 42EA0C02 		orr	r2, r2, ip
+ 7071              	.LVL549:
+ 7072              	.L422:
+7539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+ 7073              		.loc 1 7539 3 is_stmt 1 view .LVU2275
+7539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+ 7074              		.loc 1 7539 12 is_stmt 0 view .LVU2276
+ 7075 006c 22F0F002 		bic	r2, r2, #240
+ 7076              	.LVL550:
+7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7077              		.loc 1 7540 3 is_stmt 1 view .LVU2277
+7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 292
+
+
+ 7078              		.loc 1 7540 30 is_stmt 0 view .LVU2278
+ 7079 0070 1B01     		lsls	r3, r3, #4
+ 7080              	.LVL551:
+7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7081              		.loc 1 7540 37 view .LVU2279
+ 7082 0072 DBB2     		uxtb	r3, r3
+7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7083              		.loc 1 7540 12 view .LVU2280
+ 7084 0074 1343     		orrs	r3, r3, r2
+ 7085              	.LVL552:
+7543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+ 7086              		.loc 1 7543 3 is_stmt 1 view .LVU2281
+7543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+ 7087              		.loc 1 7543 11 is_stmt 0 view .LVU2282
+ 7088 0076 26F00A02 		bic	r2, r6, #10
+ 7089              	.LVL553:
+7544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7090              		.loc 1 7544 3 is_stmt 1 view .LVU2283
+7544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7091              		.loc 1 7544 30 is_stmt 0 view .LVU2284
+ 7092 007a 01F00A01 		and	r1, r1, #10
+ 7093              	.LVL554:
+7544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7094              		.loc 1 7544 11 view .LVU2285
+ 7095 007e 1143     		orrs	r1, r1, r2
+ 7096              	.LVL555:
+7547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 7097              		.loc 1 7547 3 is_stmt 1 view .LVU2286
+7547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER = tmpccer;
+ 7098              		.loc 1 7547 15 is_stmt 0 view .LVU2287
+ 7099 0080 8361     		str	r3, [r0, #24]
+7548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 7100              		.loc 1 7548 3 is_stmt 1 view .LVU2288
+7548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 7101              		.loc 1 7548 14 is_stmt 0 view .LVU2289
+ 7102 0082 0162     		str	r1, [r0, #32]
+7549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7103              		.loc 1 7549 1 view .LVU2290
+ 7104 0084 70BC     		pop	{r4, r5, r6}
+ 7105              	.LCFI67:
+ 7106              		.cfi_restore 6
+ 7107              		.cfi_restore 5
+ 7108              		.cfi_restore 4
+ 7109              		.cfi_def_cfa_offset 0
+ 7110 0086 7047     		bx	lr
+ 7111              	.L425:
+ 7112              		.align	2
+ 7113              	.L424:
+ 7114 0088 00000140 		.word	1073807360
+ 7115 008c 00080040 		.word	1073743872
+ 7116 0090 00180040 		.word	1073747968
+ 7117              		.cfi_endproc
+ 7118              	.LFE253:
+ 7120              		.section	.text.HAL_TIM_IC_ConfigChannel,"ax",%progbits
+ 7121              		.align	1
+ 7122              		.global	HAL_TIM_IC_ConfigChannel
+ 7123              		.syntax unified
+ARM GAS  /tmp/ccPLZXyC.s 			page 293
+
+
+ 7124              		.thumb
+ 7125              		.thumb_func
+ 7126              		.fpu fpv5-d16
+ 7128              	HAL_TIM_IC_ConfigChannel:
+ 7129              	.LVL556:
+ 7130              	.LFB201:
+4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7131              		.loc 1 4168 1 is_stmt 1 view -0
+ 7132              		.cfi_startproc
+ 7133              		@ args = 0, pretend = 0, frame = 0
+ 7134              		@ frame_needed = 0, uses_anonymous_args = 0
+4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7135              		.loc 1 4168 1 is_stmt 0 view .LVU2292
+ 7136 0000 38B5     		push	{r3, r4, r5, lr}
+ 7137              	.LCFI68:
+ 7138              		.cfi_def_cfa_offset 16
+ 7139              		.cfi_offset 3, -16
+ 7140              		.cfi_offset 4, -12
+ 7141              		.cfi_offset 5, -8
+ 7142              		.cfi_offset 14, -4
+4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7143              		.loc 1 4169 3 is_stmt 1 view .LVU2293
+ 7144              	.LVL557:
+4172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ 7145              		.loc 1 4172 3 view .LVU2294
+4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ 7146              		.loc 1 4173 3 view .LVU2295
+4174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ 7147              		.loc 1 4174 3 view .LVU2296
+4175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+ 7148              		.loc 1 4175 3 view .LVU2297
+4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7149              		.loc 1 4176 3 view .LVU2298
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7150              		.loc 1 4179 3 view .LVU2299
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7151              		.loc 1 4179 3 view .LVU2300
+ 7152 0002 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 7153 0006 012B     		cmp	r3, #1
+ 7154 0008 5AD0     		beq	.L432
+ 7155 000a 0446     		mov	r4, r0
+ 7156 000c 0D46     		mov	r5, r1
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7157              		.loc 1 4179 3 discriminator 2 view .LVU2301
+ 7158 000e 0123     		movs	r3, #1
+ 7159 0010 80F83C30 		strb	r3, [r0, #60]
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7160              		.loc 1 4179 3 discriminator 2 view .LVU2302
+4181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7161              		.loc 1 4181 3 discriminator 2 view .LVU2303
+4181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7162              		.loc 1 4181 6 is_stmt 0 discriminator 2 view .LVU2304
+ 7163 0014 52B1     		cbz	r2, .L435
+4195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7164              		.loc 1 4195 8 is_stmt 1 view .LVU2305
+4195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7165              		.loc 1 4195 11 is_stmt 0 view .LVU2306
+ARM GAS  /tmp/ccPLZXyC.s 			page 294
+
+
+ 7166 0016 042A     		cmp	r2, #4
+ 7167 0018 1AD0     		beq	.L436
+4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7168              		.loc 1 4211 8 is_stmt 1 view .LVU2307
+4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7169              		.loc 1 4211 11 is_stmt 0 view .LVU2308
+ 7170 001a 082A     		cmp	r2, #8
+ 7171 001c 2BD0     		beq	.L437
+4227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7172              		.loc 1 4227 8 is_stmt 1 view .LVU2309
+4227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7173              		.loc 1 4227 11 is_stmt 0 view .LVU2310
+ 7174 001e 0C2A     		cmp	r2, #12
+ 7175 0020 3BD0     		beq	.L438
+4245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7176              		.loc 1 4245 12 view .LVU2311
+ 7177 0022 0120     		movs	r0, #1
+ 7178              	.LVL558:
+ 7179              	.L429:
+4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7180              		.loc 1 4248 3 is_stmt 1 view .LVU2312
+4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7181              		.loc 1 4248 3 view .LVU2313
+ 7182 0024 0023     		movs	r3, #0
+ 7183 0026 84F83C30 		strb	r3, [r4, #60]
+4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7184              		.loc 1 4248 3 view .LVU2314
+4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 7185              		.loc 1 4250 3 view .LVU2315
+ 7186              	.LVL559:
+ 7187              	.L427:
+4251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7188              		.loc 1 4251 1 is_stmt 0 view .LVU2316
+ 7189 002a 38BD     		pop	{r3, r4, r5, pc}
+ 7190              	.LVL560:
+ 7191              	.L435:
+4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7192              		.loc 1 4184 5 is_stmt 1 view .LVU2317
+ 7193 002c CB68     		ldr	r3, [r1, #12]
+ 7194 002e 4A68     		ldr	r2, [r1, #4]
+ 7195              	.LVL561:
+4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7196              		.loc 1 4184 5 is_stmt 0 view .LVU2318
+ 7197 0030 0968     		ldr	r1, [r1]
+ 7198              	.LVL562:
+4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7199              		.loc 1 4184 5 view .LVU2319
+ 7200 0032 0068     		ldr	r0, [r0]
+ 7201              	.LVL563:
+4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7202              		.loc 1 4184 5 view .LVU2320
+ 7203 0034 FFF7FEFF 		bl	TIM_TI1_SetConfig
+ 7204              	.LVL564:
+4190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7205              		.loc 1 4190 5 is_stmt 1 view .LVU2321
+4190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7206              		.loc 1 4190 9 is_stmt 0 view .LVU2322
+ARM GAS  /tmp/ccPLZXyC.s 			page 295
+
+
+ 7207 0038 2268     		ldr	r2, [r4]
+4190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7208              		.loc 1 4190 27 view .LVU2323
+ 7209 003a 9369     		ldr	r3, [r2, #24]
+ 7210 003c 23F00C03 		bic	r3, r3, #12
+ 7211 0040 9361     		str	r3, [r2, #24]
+4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7212              		.loc 1 4193 5 is_stmt 1 view .LVU2324
+4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7213              		.loc 1 4193 9 is_stmt 0 view .LVU2325
+ 7214 0042 2268     		ldr	r2, [r4]
+4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7215              		.loc 1 4193 27 view .LVU2326
+ 7216 0044 9369     		ldr	r3, [r2, #24]
+4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7217              		.loc 1 4193 37 view .LVU2327
+ 7218 0046 A968     		ldr	r1, [r5, #8]
+4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7219              		.loc 1 4193 27 view .LVU2328
+ 7220 0048 0B43     		orrs	r3, r3, r1
+ 7221 004a 9361     		str	r3, [r2, #24]
+4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7222              		.loc 1 4169 21 view .LVU2329
+ 7223 004c 0020     		movs	r0, #0
+ 7224 004e E9E7     		b	.L429
+ 7225              	.LVL565:
+ 7226              	.L436:
+4198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7227              		.loc 1 4198 5 is_stmt 1 view .LVU2330
+4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7228              		.loc 1 4200 5 view .LVU2331
+ 7229 0050 CB68     		ldr	r3, [r1, #12]
+ 7230 0052 4A68     		ldr	r2, [r1, #4]
+ 7231              	.LVL566:
+4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7232              		.loc 1 4200 5 is_stmt 0 view .LVU2332
+ 7233 0054 0968     		ldr	r1, [r1]
+ 7234              	.LVL567:
+4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7235              		.loc 1 4200 5 view .LVU2333
+ 7236 0056 0068     		ldr	r0, [r0]
+ 7237              	.LVL568:
+4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7238              		.loc 1 4200 5 view .LVU2334
+ 7239 0058 FFF7FEFF 		bl	TIM_TI2_SetConfig
+ 7240              	.LVL569:
+4206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7241              		.loc 1 4206 5 is_stmt 1 view .LVU2335
+4206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7242              		.loc 1 4206 9 is_stmt 0 view .LVU2336
+ 7243 005c 2268     		ldr	r2, [r4]
+4206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7244              		.loc 1 4206 27 view .LVU2337
+ 7245 005e 9369     		ldr	r3, [r2, #24]
+ 7246 0060 23F44063 		bic	r3, r3, #3072
+ 7247 0064 9361     		str	r3, [r2, #24]
+4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ARM GAS  /tmp/ccPLZXyC.s 			page 296
+
+
+ 7248              		.loc 1 4209 5 is_stmt 1 view .LVU2338
+4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7249              		.loc 1 4209 9 is_stmt 0 view .LVU2339
+ 7250 0066 2268     		ldr	r2, [r4]
+4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7251              		.loc 1 4209 27 view .LVU2340
+ 7252 0068 9369     		ldr	r3, [r2, #24]
+4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7253              		.loc 1 4209 38 view .LVU2341
+ 7254 006a A968     		ldr	r1, [r5, #8]
+4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7255              		.loc 1 4209 27 view .LVU2342
+ 7256 006c 43EA0123 		orr	r3, r3, r1, lsl #8
+ 7257 0070 9361     		str	r3, [r2, #24]
+4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7258              		.loc 1 4169 21 view .LVU2343
+ 7259 0072 0020     		movs	r0, #0
+ 7260 0074 D6E7     		b	.L429
+ 7261              	.LVL570:
+ 7262              	.L437:
+4214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7263              		.loc 1 4214 5 is_stmt 1 view .LVU2344
+4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7264              		.loc 1 4216 5 view .LVU2345
+ 7265 0076 CB68     		ldr	r3, [r1, #12]
+ 7266 0078 4A68     		ldr	r2, [r1, #4]
+ 7267              	.LVL571:
+4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7268              		.loc 1 4216 5 is_stmt 0 view .LVU2346
+ 7269 007a 0968     		ldr	r1, [r1]
+ 7270              	.LVL572:
+4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7271              		.loc 1 4216 5 view .LVU2347
+ 7272 007c 0068     		ldr	r0, [r0]
+ 7273              	.LVL573:
+4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7274              		.loc 1 4216 5 view .LVU2348
+ 7275 007e FFF7FEFF 		bl	TIM_TI3_SetConfig
+ 7276              	.LVL574:
+4222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7277              		.loc 1 4222 5 is_stmt 1 view .LVU2349
+4222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7278              		.loc 1 4222 9 is_stmt 0 view .LVU2350
+ 7279 0082 2268     		ldr	r2, [r4]
+4222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7280              		.loc 1 4222 27 view .LVU2351
+ 7281 0084 D369     		ldr	r3, [r2, #28]
+ 7282 0086 23F00C03 		bic	r3, r3, #12
+ 7283 008a D361     		str	r3, [r2, #28]
+4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7284              		.loc 1 4225 5 is_stmt 1 view .LVU2352
+4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7285              		.loc 1 4225 9 is_stmt 0 view .LVU2353
+ 7286 008c 2268     		ldr	r2, [r4]
+4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7287              		.loc 1 4225 27 view .LVU2354
+ 7288 008e D369     		ldr	r3, [r2, #28]
+ARM GAS  /tmp/ccPLZXyC.s 			page 297
+
+
+4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7289              		.loc 1 4225 37 view .LVU2355
+ 7290 0090 A968     		ldr	r1, [r5, #8]
+4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7291              		.loc 1 4225 27 view .LVU2356
+ 7292 0092 0B43     		orrs	r3, r3, r1
+ 7293 0094 D361     		str	r3, [r2, #28]
+4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7294              		.loc 1 4169 21 view .LVU2357
+ 7295 0096 0020     		movs	r0, #0
+ 7296 0098 C4E7     		b	.L429
+ 7297              	.LVL575:
+ 7298              	.L438:
+4230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7299              		.loc 1 4230 5 is_stmt 1 view .LVU2358
+4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7300              		.loc 1 4232 5 view .LVU2359
+ 7301 009a CB68     		ldr	r3, [r1, #12]
+ 7302 009c 4A68     		ldr	r2, [r1, #4]
+ 7303              	.LVL576:
+4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7304              		.loc 1 4232 5 is_stmt 0 view .LVU2360
+ 7305 009e 0968     		ldr	r1, [r1]
+ 7306              	.LVL577:
+4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7307              		.loc 1 4232 5 view .LVU2361
+ 7308 00a0 0068     		ldr	r0, [r0]
+ 7309              	.LVL578:
+4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                       sConfig->ICPolarity,
+ 7310              		.loc 1 4232 5 view .LVU2362
+ 7311 00a2 FFF7FEFF 		bl	TIM_TI4_SetConfig
+ 7312              	.LVL579:
+4238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7313              		.loc 1 4238 5 is_stmt 1 view .LVU2363
+4238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7314              		.loc 1 4238 9 is_stmt 0 view .LVU2364
+ 7315 00a6 2268     		ldr	r2, [r4]
+4238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7316              		.loc 1 4238 27 view .LVU2365
+ 7317 00a8 D369     		ldr	r3, [r2, #28]
+ 7318 00aa 23F44063 		bic	r3, r3, #3072
+ 7319 00ae D361     		str	r3, [r2, #28]
+4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7320              		.loc 1 4241 5 is_stmt 1 view .LVU2366
+4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7321              		.loc 1 4241 9 is_stmt 0 view .LVU2367
+ 7322 00b0 2268     		ldr	r2, [r4]
+4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7323              		.loc 1 4241 27 view .LVU2368
+ 7324 00b2 D369     		ldr	r3, [r2, #28]
+4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7325              		.loc 1 4241 38 view .LVU2369
+ 7326 00b4 A968     		ldr	r1, [r5, #8]
+4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7327              		.loc 1 4241 27 view .LVU2370
+ 7328 00b6 43EA0123 		orr	r3, r3, r1, lsl #8
+ 7329 00ba D361     		str	r3, [r2, #28]
+ARM GAS  /tmp/ccPLZXyC.s 			page 298
+
+
+4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7330              		.loc 1 4169 21 view .LVU2371
+ 7331 00bc 0020     		movs	r0, #0
+ 7332 00be B1E7     		b	.L429
+ 7333              	.LVL580:
+ 7334              	.L432:
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7335              		.loc 1 4179 3 view .LVU2372
+ 7336 00c0 0220     		movs	r0, #2
+ 7337              	.LVL581:
+4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7338              		.loc 1 4179 3 view .LVU2373
+ 7339 00c2 B2E7     		b	.L427
+ 7340              		.cfi_endproc
+ 7341              	.LFE201:
+ 7343              		.section	.text.HAL_TIM_OnePulse_ConfigChannel,"ax",%progbits
+ 7344              		.align	1
+ 7345              		.global	HAL_TIM_OnePulse_ConfigChannel
+ 7346              		.syntax unified
+ 7347              		.thumb
+ 7348              		.thumb_func
+ 7349              		.fpu fpv5-d16
+ 7351              	HAL_TIM_OnePulse_ConfigChannel:
+ 7352              	.LVL582:
+ 7353              	.LFB203:
+4418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7354              		.loc 1 4418 1 is_stmt 1 view -0
+ 7355              		.cfi_startproc
+ 7356              		@ args = 0, pretend = 0, frame = 32
+ 7357              		@ frame_needed = 0, uses_anonymous_args = 0
+4419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_OC_InitTypeDef temp1;
+ 7358              		.loc 1 4419 3 view .LVU2375
+4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7359              		.loc 1 4420 3 view .LVU2376
+4423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+ 7360              		.loc 1 4423 3 view .LVU2377
+4424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7361              		.loc 1 4424 3 view .LVU2378
+4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7362              		.loc 1 4426 3 view .LVU2379
+4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7363              		.loc 1 4426 6 is_stmt 0 view .LVU2380
+ 7364 0000 9A42     		cmp	r2, r3
+ 7365 0002 76D0     		beq	.L447
+4418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7366              		.loc 1 4418 1 view .LVU2381
+ 7367 0004 70B5     		push	{r4, r5, r6, lr}
+ 7368              	.LCFI69:
+ 7369              		.cfi_def_cfa_offset 16
+ 7370              		.cfi_offset 4, -16
+ 7371              		.cfi_offset 5, -12
+ 7372              		.cfi_offset 6, -8
+ 7373              		.cfi_offset 14, -4
+ 7374 0006 88B0     		sub	sp, sp, #32
+ 7375              	.LCFI70:
+ 7376              		.cfi_def_cfa_offset 48
+ 7377 0008 0446     		mov	r4, r0
+ARM GAS  /tmp/ccPLZXyC.s 			page 299
+
+
+ 7378 000a 0D46     		mov	r5, r1
+ 7379 000c 1E46     		mov	r6, r3
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7380              		.loc 1 4429 5 is_stmt 1 view .LVU2382
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7381              		.loc 1 4429 5 view .LVU2383
+ 7382 000e 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 7383              	.LVL583:
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7384              		.loc 1 4429 5 is_stmt 0 view .LVU2384
+ 7385 0012 012B     		cmp	r3, #1
+ 7386 0014 6FD0     		beq	.L448
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7387              		.loc 1 4429 5 is_stmt 1 discriminator 2 view .LVU2385
+ 7388 0016 0123     		movs	r3, #1
+ 7389 0018 80F83C30 		strb	r3, [r0, #60]
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7390              		.loc 1 4429 5 discriminator 2 view .LVU2386
+4431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7391              		.loc 1 4431 5 discriminator 2 view .LVU2387
+4431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7392              		.loc 1 4431 17 is_stmt 0 discriminator 2 view .LVU2388
+ 7393 001c 0223     		movs	r3, #2
+ 7394 001e 80F83D30 		strb	r3, [r0, #61]
+4434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.Pulse = sConfig->Pulse;
+ 7395              		.loc 1 4434 5 is_stmt 1 discriminator 2 view .LVU2389
+4434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.Pulse = sConfig->Pulse;
+ 7396              		.loc 1 4434 27 is_stmt 0 discriminator 2 view .LVU2390
+ 7397 0022 0B68     		ldr	r3, [r1]
+4434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.Pulse = sConfig->Pulse;
+ 7398              		.loc 1 4434 18 discriminator 2 view .LVU2391
+ 7399 0024 0193     		str	r3, [sp, #4]
+4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCPolarity = sConfig->OCPolarity;
+ 7400              		.loc 1 4435 5 is_stmt 1 discriminator 2 view .LVU2392
+4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCPolarity = sConfig->OCPolarity;
+ 7401              		.loc 1 4435 26 is_stmt 0 discriminator 2 view .LVU2393
+ 7402 0026 4B68     		ldr	r3, [r1, #4]
+4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCPolarity = sConfig->OCPolarity;
+ 7403              		.loc 1 4435 17 discriminator 2 view .LVU2394
+ 7404 0028 0293     		str	r3, [sp, #8]
+4436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCNPolarity = sConfig->OCNPolarity;
+ 7405              		.loc 1 4436 5 is_stmt 1 discriminator 2 view .LVU2395
+4436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCNPolarity = sConfig->OCNPolarity;
+ 7406              		.loc 1 4436 31 is_stmt 0 discriminator 2 view .LVU2396
+ 7407 002a 8B68     		ldr	r3, [r1, #8]
+4436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCNPolarity = sConfig->OCNPolarity;
+ 7408              		.loc 1 4436 22 discriminator 2 view .LVU2397
+ 7409 002c 0393     		str	r3, [sp, #12]
+4437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCIdleState = sConfig->OCIdleState;
+ 7410              		.loc 1 4437 5 is_stmt 1 discriminator 2 view .LVU2398
+4437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCIdleState = sConfig->OCIdleState;
+ 7411              		.loc 1 4437 32 is_stmt 0 discriminator 2 view .LVU2399
+ 7412 002e CB68     		ldr	r3, [r1, #12]
+4437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCIdleState = sConfig->OCIdleState;
+ 7413              		.loc 1 4437 23 discriminator 2 view .LVU2400
+ 7414 0030 0493     		str	r3, [sp, #16]
+4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCNIdleState = sConfig->OCNIdleState;
+ARM GAS  /tmp/ccPLZXyC.s 			page 300
+
+
+ 7415              		.loc 1 4438 5 is_stmt 1 discriminator 2 view .LVU2401
+4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCNIdleState = sConfig->OCNIdleState;
+ 7416              		.loc 1 4438 32 is_stmt 0 discriminator 2 view .LVU2402
+ 7417 0032 0B69     		ldr	r3, [r1, #16]
+4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     temp1.OCNIdleState = sConfig->OCNIdleState;
+ 7418              		.loc 1 4438 23 discriminator 2 view .LVU2403
+ 7419 0034 0693     		str	r3, [sp, #24]
+4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7420              		.loc 1 4439 5 is_stmt 1 discriminator 2 view .LVU2404
+4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7421              		.loc 1 4439 33 is_stmt 0 discriminator 2 view .LVU2405
+ 7422 0036 4B69     		ldr	r3, [r1, #20]
+4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7423              		.loc 1 4439 24 discriminator 2 view .LVU2406
+ 7424 0038 0793     		str	r3, [sp, #28]
+4441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 7425              		.loc 1 4441 5 is_stmt 1 discriminator 2 view .LVU2407
+ 7426 003a 52B1     		cbz	r2, .L441
+4441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 7427              		.loc 1 4441 5 is_stmt 0 view .LVU2408
+ 7428 003c 042A     		cmp	r2, #4
+ 7429 003e 11D0     		beq	.L442
+ 7430 0040 0120     		movs	r0, #1
+ 7431              	.LVL584:
+ 7432              	.L443:
+4514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7433              		.loc 1 4514 5 is_stmt 1 view .LVU2409
+4514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7434              		.loc 1 4514 17 is_stmt 0 view .LVU2410
+ 7435 0042 0123     		movs	r3, #1
+ 7436 0044 84F83D30 		strb	r3, [r4, #61]
+4516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7437              		.loc 1 4516 5 is_stmt 1 view .LVU2411
+4516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7438              		.loc 1 4516 5 view .LVU2412
+ 7439 0048 0023     		movs	r3, #0
+ 7440 004a 84F83C30 		strb	r3, [r4, #60]
+4516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7441              		.loc 1 4516 5 view .LVU2413
+4518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7442              		.loc 1 4518 5 view .LVU2414
+ 7443              	.LVL585:
+ 7444              	.L440:
+4524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7445              		.loc 1 4524 1 is_stmt 0 view .LVU2415
+ 7446 004e 08B0     		add	sp, sp, #32
+ 7447              	.LCFI71:
+ 7448              		.cfi_remember_state
+ 7449              		.cfi_def_cfa_offset 16
+ 7450              		@ sp needed
+ 7451 0050 70BD     		pop	{r4, r5, r6, pc}
+ 7452              	.LVL586:
+ 7453              	.L441:
+ 7454              	.LCFI72:
+ 7455              		.cfi_restore_state
+4445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7456              		.loc 1 4445 9 is_stmt 1 view .LVU2416
+ARM GAS  /tmp/ccPLZXyC.s 			page 301
+
+
+4447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+ 7457              		.loc 1 4447 9 view .LVU2417
+ 7458 0052 01A9     		add	r1, sp, #4
+ 7459              	.LVL587:
+4447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+ 7460              		.loc 1 4447 9 is_stmt 0 view .LVU2418
+ 7461 0054 0068     		ldr	r0, [r0]
+ 7462              	.LVL588:
+4447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+ 7463              		.loc 1 4447 9 view .LVU2419
+ 7464 0056 FFF7FEFF 		bl	TIM_OC1_SetConfig
+ 7465              	.LVL589:
+4448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 7466              		.loc 1 4448 9 is_stmt 1 view .LVU2420
+4464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 7467              		.loc 1 4464 5 view .LVU2421
+ 7468              	.L444:
+4466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 7469              		.loc 1 4466 7 view .LVU2422
+ 7470 005a 46B1     		cbz	r6, .L445
+ 7471 005c 042E     		cmp	r6, #4
+ 7472 005e 27D0     		beq	.L446
+ 7473 0060 0120     		movs	r0, #1
+ 7474 0062 EEE7     		b	.L443
+ 7475              	.LVL590:
+ 7476              	.L442:
+4453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7477              		.loc 1 4453 9 view .LVU2423
+4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+ 7478              		.loc 1 4455 9 view .LVU2424
+ 7479 0064 01A9     		add	r1, sp, #4
+ 7480              	.LVL591:
+4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+ 7481              		.loc 1 4455 9 is_stmt 0 view .LVU2425
+ 7482 0066 0068     		ldr	r0, [r0]
+ 7483              	.LVL592:
+4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         break;
+ 7484              		.loc 1 4455 9 view .LVU2426
+ 7485 0068 FFF7FEFF 		bl	TIM_OC2_SetConfig
+ 7486              	.LVL593:
+4456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 7487              		.loc 1 4456 9 is_stmt 1 view .LVU2427
+4464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 7488              		.loc 1 4464 5 view .LVU2428
+ 7489 006c F5E7     		b	.L444
+ 7490              	.L445:
+4470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7491              		.loc 1 4470 11 view .LVU2429
+4472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                             sConfig->ICSelection, sConfig->ICFilter);
+ 7492              		.loc 1 4472 11 view .LVU2430
+ 7493 006e 2B6A     		ldr	r3, [r5, #32]
+ 7494 0070 EA69     		ldr	r2, [r5, #28]
+ 7495 0072 A969     		ldr	r1, [r5, #24]
+ 7496 0074 2068     		ldr	r0, [r4]
+ 7497 0076 FFF7FEFF 		bl	TIM_TI1_SetConfig
+ 7498              	.LVL594:
+4476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 302
+
+
+ 7499              		.loc 1 4476 11 view .LVU2431
+4476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7500              		.loc 1 4476 15 is_stmt 0 view .LVU2432
+ 7501 007a 2268     		ldr	r2, [r4]
+4476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7502              		.loc 1 4476 33 view .LVU2433
+ 7503 007c 9369     		ldr	r3, [r2, #24]
+ 7504 007e 23F00C03 		bic	r3, r3, #12
+ 7505 0082 9361     		str	r3, [r2, #24]
+4479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI1FP1;
+ 7506              		.loc 1 4479 11 is_stmt 1 view .LVU2434
+4479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI1FP1;
+ 7507              		.loc 1 4479 15 is_stmt 0 view .LVU2435
+ 7508 0084 2268     		ldr	r2, [r4]
+4479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI1FP1;
+ 7509              		.loc 1 4479 32 view .LVU2436
+ 7510 0086 9368     		ldr	r3, [r2, #8]
+ 7511 0088 23F07003 		bic	r3, r3, #112
+ 7512 008c 9360     		str	r3, [r2, #8]
+4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7513              		.loc 1 4480 11 is_stmt 1 view .LVU2437
+4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7514              		.loc 1 4480 15 is_stmt 0 view .LVU2438
+ 7515 008e 2268     		ldr	r2, [r4]
+4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7516              		.loc 1 4480 32 view .LVU2439
+ 7517 0090 9368     		ldr	r3, [r2, #8]
+ 7518 0092 43F05003 		orr	r3, r3, #80
+ 7519 0096 9360     		str	r3, [r2, #8]
+4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7520              		.loc 1 4483 11 is_stmt 1 view .LVU2440
+4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7521              		.loc 1 4483 15 is_stmt 0 view .LVU2441
+ 7522 0098 2268     		ldr	r2, [r4]
+4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7523              		.loc 1 4483 32 view .LVU2442
+ 7524 009a 9168     		ldr	r1, [r2, #8]
+ 7525 009c 174B     		ldr	r3, .L453
+ 7526 009e 0B40     		ands	r3, r3, r1
+ 7527 00a0 9360     		str	r3, [r2, #8]
+4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           break;
+ 7528              		.loc 1 4484 11 is_stmt 1 view .LVU2443
+4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           break;
+ 7529              		.loc 1 4484 15 is_stmt 0 view .LVU2444
+ 7530 00a2 2268     		ldr	r2, [r4]
+4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           break;
+ 7531              		.loc 1 4484 32 view .LVU2445
+ 7532 00a4 9368     		ldr	r3, [r2, #8]
+ 7533 00a6 43F00603 		orr	r3, r3, #6
+ 7534 00aa 9360     		str	r3, [r2, #8]
+4485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7535              		.loc 1 4485 11 is_stmt 1 view .LVU2446
+ 7536 00ac 0020     		movs	r0, #0
+ 7537 00ae C8E7     		b	.L443
+ 7538              	.L446:
+4490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7539              		.loc 1 4490 11 view .LVU2447
+ARM GAS  /tmp/ccPLZXyC.s 			page 303
+
+
+4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                             sConfig->ICSelection, sConfig->ICFilter);
+ 7540              		.loc 1 4492 11 view .LVU2448
+ 7541 00b0 2B6A     		ldr	r3, [r5, #32]
+ 7542 00b2 EA69     		ldr	r2, [r5, #28]
+ 7543 00b4 A969     		ldr	r1, [r5, #24]
+ 7544 00b6 2068     		ldr	r0, [r4]
+ 7545 00b8 FFF7FEFF 		bl	TIM_TI2_SetConfig
+ 7546              	.LVL595:
+4496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7547              		.loc 1 4496 11 view .LVU2449
+4496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7548              		.loc 1 4496 15 is_stmt 0 view .LVU2450
+ 7549 00bc 2268     		ldr	r2, [r4]
+4496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7550              		.loc 1 4496 33 view .LVU2451
+ 7551 00be 9369     		ldr	r3, [r2, #24]
+ 7552 00c0 23F44063 		bic	r3, r3, #3072
+ 7553 00c4 9361     		str	r3, [r2, #24]
+4499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI2FP2;
+ 7554              		.loc 1 4499 11 is_stmt 1 view .LVU2452
+4499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI2FP2;
+ 7555              		.loc 1 4499 15 is_stmt 0 view .LVU2453
+ 7556 00c6 2268     		ldr	r2, [r4]
+4499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_TS_TI2FP2;
+ 7557              		.loc 1 4499 32 view .LVU2454
+ 7558 00c8 9368     		ldr	r3, [r2, #8]
+ 7559 00ca 23F07003 		bic	r3, r3, #112
+ 7560 00ce 9360     		str	r3, [r2, #8]
+4500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7561              		.loc 1 4500 11 is_stmt 1 view .LVU2455
+4500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7562              		.loc 1 4500 15 is_stmt 0 view .LVU2456
+ 7563 00d0 2268     		ldr	r2, [r4]
+4500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7564              		.loc 1 4500 32 view .LVU2457
+ 7565 00d2 9368     		ldr	r3, [r2, #8]
+ 7566 00d4 43F06003 		orr	r3, r3, #96
+ 7567 00d8 9360     		str	r3, [r2, #8]
+4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7568              		.loc 1 4503 11 is_stmt 1 view .LVU2458
+4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7569              		.loc 1 4503 15 is_stmt 0 view .LVU2459
+ 7570 00da 2268     		ldr	r2, [r4]
+4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ 7571              		.loc 1 4503 32 view .LVU2460
+ 7572 00dc 9168     		ldr	r1, [r2, #8]
+ 7573 00de 074B     		ldr	r3, .L453
+ 7574 00e0 0B40     		ands	r3, r3, r1
+ 7575 00e2 9360     		str	r3, [r2, #8]
+4504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           break;
+ 7576              		.loc 1 4504 11 is_stmt 1 view .LVU2461
+4504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           break;
+ 7577              		.loc 1 4504 15 is_stmt 0 view .LVU2462
+ 7578 00e4 2268     		ldr	r2, [r4]
+4504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****           break;
+ 7579              		.loc 1 4504 32 view .LVU2463
+ 7580 00e6 9368     		ldr	r3, [r2, #8]
+ARM GAS  /tmp/ccPLZXyC.s 			page 304
+
+
+ 7581 00e8 43F00603 		orr	r3, r3, #6
+ 7582 00ec 9360     		str	r3, [r2, #8]
+4505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7583              		.loc 1 4505 11 is_stmt 1 view .LVU2464
+ 7584 00ee 0020     		movs	r0, #0
+ 7585 00f0 A7E7     		b	.L443
+ 7586              	.LVL596:
+ 7587              	.L447:
+ 7588              	.LCFI73:
+ 7589              		.cfi_def_cfa_offset 0
+ 7590              		.cfi_restore 4
+ 7591              		.cfi_restore 5
+ 7592              		.cfi_restore 6
+ 7593              		.cfi_restore 14
+4522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 7594              		.loc 1 4522 12 is_stmt 0 view .LVU2465
+ 7595 00f2 0120     		movs	r0, #1
+ 7596              	.LVL597:
+4524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7597              		.loc 1 4524 1 view .LVU2466
+ 7598 00f4 7047     		bx	lr
+ 7599              	.LVL598:
+ 7600              	.L448:
+ 7601              	.LCFI74:
+ 7602              		.cfi_def_cfa_offset 48
+ 7603              		.cfi_offset 4, -16
+ 7604              		.cfi_offset 5, -12
+ 7605              		.cfi_offset 6, -8
+ 7606              		.cfi_offset 14, -4
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7607              		.loc 1 4429 5 view .LVU2467
+ 7608 00f6 0220     		movs	r0, #2
+ 7609              	.LVL599:
+4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7610              		.loc 1 4429 5 view .LVU2468
+ 7611 00f8 A9E7     		b	.L440
+ 7612              	.L454:
+ 7613 00fa 00BF     		.align	2
+ 7614              	.L453:
+ 7615 00fc F8FFFEFF 		.word	-65544
+ 7616              		.cfi_endproc
+ 7617              	.LFE203:
+ 7619              		.section	.text.TIM_ETR_SetConfig,"ax",%progbits
+ 7620              		.align	1
+ 7621              		.global	TIM_ETR_SetConfig
+ 7622              		.syntax unified
+ 7623              		.thumb
+ 7624              		.thumb_func
+ 7625              		.fpu fpv5-d16
+ 7627              	TIM_ETR_SetConfig:
+ 7628              	.LVL600:
+ 7629              	.LFB260:
+7793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Configures the TIMx External Trigger (ETR).
+7795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+7797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+ARM GAS  /tmp/ccPLZXyC.s 			page 305
+
+
+7798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+7799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+7800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+7801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+7802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+7803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+7805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+7806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  ExtTRGFilter External Trigger Filter.
+7807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter must be a value between 0x00 and 0x0F
+7808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+7811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+7812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ 7630              		.loc 1 7812 1 is_stmt 1 view -0
+ 7631              		.cfi_startproc
+ 7632              		@ args = 0, pretend = 0, frame = 0
+ 7633              		@ frame_needed = 0, uses_anonymous_args = 0
+ 7634              		@ link register save eliminated.
+ 7635              		.loc 1 7812 1 is_stmt 0 view .LVU2470
+ 7636 0000 10B4     		push	{r4}
+ 7637              	.LCFI75:
+ 7638              		.cfi_def_cfa_offset 4
+ 7639              		.cfi_offset 4, -4
+7813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 7640              		.loc 1 7813 3 is_stmt 1 view .LVU2471
+7814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr = TIMx->SMCR;
+ 7641              		.loc 1 7815 3 view .LVU2472
+ 7642              		.loc 1 7815 11 is_stmt 0 view .LVU2473
+ 7643 0002 8468     		ldr	r4, [r0, #8]
+ 7644              	.LVL601:
+7816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the ETR Bits */
+7818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 7645              		.loc 1 7818 3 is_stmt 1 view .LVU2474
+ 7646              		.loc 1 7818 11 is_stmt 0 view .LVU2475
+ 7647 0004 24F47F4C 		bic	ip, r4, #65280
+ 7648              	.LVL602:
+7819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Prescaler, the Filter value and the Polarity */
+7821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+ 7649              		.loc 1 7821 3 is_stmt 1 view .LVU2476
+ 7650              		.loc 1 7821 67 is_stmt 0 view .LVU2477
+ 7651 0008 42EA0322 		orr	r2, r2, r3, lsl #8
+ 7652              	.LVL603:
+ 7653              		.loc 1 7821 45 view .LVU2478
+ 7654 000c 0A43     		orrs	r2, r2, r1
+ 7655              		.loc 1 7821 11 view .LVU2479
+ 7656 000e 42EA0C02 		orr	r2, r2, ip
+ 7657              	.LVL604:
+7822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Write to TIMx SMCR */
+7824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->SMCR = tmpsmcr;
+ 7658              		.loc 1 7824 3 is_stmt 1 view .LVU2480
+ 7659              		.loc 1 7824 14 is_stmt 0 view .LVU2481
+ARM GAS  /tmp/ccPLZXyC.s 			page 306
+
+
+ 7660 0012 8260     		str	r2, [r0, #8]
+7825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 7661              		.loc 1 7825 1 view .LVU2482
+ 7662 0014 5DF8044B 		ldr	r4, [sp], #4
+ 7663              	.LCFI76:
+ 7664              		.cfi_restore 4
+ 7665              		.cfi_def_cfa_offset 0
+ 7666 0018 7047     		bx	lr
+ 7667              		.cfi_endproc
+ 7668              	.LFE260:
+ 7670              		.section	.text.HAL_TIM_ConfigOCrefClear,"ax",%progbits
+ 7671              		.align	1
+ 7672              		.global	HAL_TIM_ConfigOCrefClear
+ 7673              		.syntax unified
+ 7674              		.thumb
+ 7675              		.thumb_func
+ 7676              		.fpu fpv5-d16
+ 7678              	HAL_TIM_ConfigOCrefClear:
+ 7679              	.LVL605:
+ 7680              	.LFB211:
+5291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7681              		.loc 1 5291 1 is_stmt 1 view -0
+ 7682              		.cfi_startproc
+ 7683              		@ args = 0, pretend = 0, frame = 0
+ 7684              		@ frame_needed = 0, uses_anonymous_args = 0
+5292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7685              		.loc 1 5292 3 view .LVU2484
+5295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+ 7686              		.loc 1 5295 3 view .LVU2485
+5296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7687              		.loc 1 5296 3 view .LVU2486
+5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7688              		.loc 1 5299 3 view .LVU2487
+5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7689              		.loc 1 5299 3 view .LVU2488
+ 7690 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 7691 0004 012B     		cmp	r3, #1
+ 7692 0006 00F09B80 		beq	.L477
+5291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7693              		.loc 1 5291 1 is_stmt 0 discriminator 2 view .LVU2489
+ 7694 000a 70B5     		push	{r4, r5, r6, lr}
+ 7695              	.LCFI77:
+ 7696              		.cfi_def_cfa_offset 16
+ 7697              		.cfi_offset 4, -16
+ 7698              		.cfi_offset 5, -12
+ 7699              		.cfi_offset 6, -8
+ 7700              		.cfi_offset 14, -4
+ 7701 000c 0446     		mov	r4, r0
+ 7702 000e 0D46     		mov	r5, r1
+ 7703 0010 1646     		mov	r6, r2
+5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7704              		.loc 1 5299 3 is_stmt 1 discriminator 2 view .LVU2490
+ 7705 0012 0123     		movs	r3, #1
+ 7706 0014 80F83C30 		strb	r3, [r0, #60]
+5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7707              		.loc 1 5299 3 discriminator 2 view .LVU2491
+5301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 307
+
+
+ 7708              		.loc 1 5301 3 discriminator 2 view .LVU2492
+5301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7709              		.loc 1 5301 15 is_stmt 0 discriminator 2 view .LVU2493
+ 7710 0018 0223     		movs	r3, #2
+ 7711 001a 80F83D30 		strb	r3, [r0, #61]
+5303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7712              		.loc 1 5303 3 is_stmt 1 discriminator 2 view .LVU2494
+5303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7713              		.loc 1 5303 28 is_stmt 0 discriminator 2 view .LVU2495
+ 7714 001e 4B68     		ldr	r3, [r1, #4]
+5303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7715              		.loc 1 5303 3 discriminator 2 view .LVU2496
+ 7716 0020 4BB1     		cbz	r3, .L459
+5303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7717              		.loc 1 5303 3 view .LVU2497
+ 7718 0022 012B     		cmp	r3, #1
+ 7719 0024 1BD0     		beq	.L460
+ 7720 0026 0120     		movs	r0, #1
+ 7721              	.LVL606:
+ 7722              	.L461:
+5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7723              		.loc 1 5432 3 is_stmt 1 view .LVU2498
+5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7724              		.loc 1 5432 15 is_stmt 0 view .LVU2499
+ 7725 0028 0123     		movs	r3, #1
+ 7726 002a 84F83D30 		strb	r3, [r4, #61]
+5434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7727              		.loc 1 5434 3 is_stmt 1 view .LVU2500
+5434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7728              		.loc 1 5434 3 view .LVU2501
+ 7729 002e 0023     		movs	r3, #0
+ 7730 0030 84F83C30 		strb	r3, [r4, #60]
+5434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7731              		.loc 1 5434 3 view .LVU2502
+5436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 7732              		.loc 1 5436 3 view .LVU2503
+ 7733              	.L458:
+5437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7734              		.loc 1 5437 1 is_stmt 0 view .LVU2504
+ 7735 0034 70BD     		pop	{r4, r5, r6, pc}
+ 7736              	.LVL607:
+ 7737              	.L459:
+5308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 7738              		.loc 1 5308 7 is_stmt 1 view .LVU2505
+ 7739 0036 0268     		ldr	r2, [r0]
+ 7740              	.LVL608:
+5308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 7741              		.loc 1 5308 7 is_stmt 0 view .LVU2506
+ 7742 0038 9368     		ldr	r3, [r2, #8]
+ 7743 003a 23F47F43 		bic	r3, r3, #65280
+ 7744 003e 9360     		str	r3, [r2, #8]
+5309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 7745              		.loc 1 5309 7 is_stmt 1 view .LVU2507
+5339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7746              		.loc 1 5339 3 view .LVU2508
+ 7747              	.LVL609:
+ 7748              	.L462:
+ARM GAS  /tmp/ccPLZXyC.s 			page 308
+
+
+5341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 7749              		.loc 1 5341 5 view .LVU2509
+ 7750 0040 142E     		cmp	r6, #20
+ 7751 0042 7BD8     		bhi	.L478
+ 7752 0044 DFE806F0 		tbb	[pc, r6]
+ 7753              	.L465:
+ 7754 0048 1A       		.byte	(.L470-.L465)/2
+ 7755 0049 7A       		.byte	(.L478-.L465)/2
+ 7756 004a 7A       		.byte	(.L478-.L465)/2
+ 7757 004b 7A       		.byte	(.L478-.L465)/2
+ 7758 004c 2A       		.byte	(.L469-.L465)/2
+ 7759 004d 7A       		.byte	(.L478-.L465)/2
+ 7760 004e 7A       		.byte	(.L478-.L465)/2
+ 7761 004f 7A       		.byte	(.L478-.L465)/2
+ 7762 0050 3A       		.byte	(.L468-.L465)/2
+ 7763 0051 7A       		.byte	(.L478-.L465)/2
+ 7764 0052 7A       		.byte	(.L478-.L465)/2
+ 7765 0053 7A       		.byte	(.L478-.L465)/2
+ 7766 0054 4A       		.byte	(.L467-.L465)/2
+ 7767 0055 7A       		.byte	(.L478-.L465)/2
+ 7768 0056 7A       		.byte	(.L478-.L465)/2
+ 7769 0057 7A       		.byte	(.L478-.L465)/2
+ 7770 0058 5A       		.byte	(.L466-.L465)/2
+ 7771 0059 7A       		.byte	(.L478-.L465)/2
+ 7772 005a 7A       		.byte	(.L478-.L465)/2
+ 7773 005b 7A       		.byte	(.L478-.L465)/2
+ 7774 005c 6A       		.byte	(.L464-.L465)/2
+ 7775              	.LVL610:
+ 7776 005d 00       		.p2align 1
+ 7777              	.L460:
+5315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ 7778              		.loc 1 5315 7 view .LVU2510
+5316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+ 7779              		.loc 1 5316 7 view .LVU2511
+5317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7780              		.loc 1 5317 7 view .LVU2512
+5320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 7781              		.loc 1 5320 7 view .LVU2513
+5320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 7782              		.loc 1 5320 28 is_stmt 0 view .LVU2514
+ 7783 005e C968     		ldr	r1, [r1, #12]
+ 7784              	.LVL611:
+5320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 7785              		.loc 1 5320 10 view .LVU2515
+ 7786 0060 31B1     		cbz	r1, .L463
+5322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         __HAL_UNLOCK(htim);
+ 7787              		.loc 1 5322 9 is_stmt 1 view .LVU2516
+5322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         __HAL_UNLOCK(htim);
+ 7788              		.loc 1 5322 21 is_stmt 0 view .LVU2517
+ 7789 0062 0120     		movs	r0, #1
+ 7790              	.LVL612:
+5322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         __HAL_UNLOCK(htim);
+ 7791              		.loc 1 5322 21 view .LVU2518
+ 7792 0064 84F83D00 		strb	r0, [r4, #61]
+5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+ 7793              		.loc 1 5323 9 is_stmt 1 view .LVU2519
+5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+ARM GAS  /tmp/ccPLZXyC.s 			page 309
+
+
+ 7794              		.loc 1 5323 9 view .LVU2520
+ 7795 0068 0023     		movs	r3, #0
+ 7796 006a 84F83C30 		strb	r3, [r4, #60]
+5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         return HAL_ERROR;
+ 7797              		.loc 1 5323 9 view .LVU2521
+5324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 7798              		.loc 1 5324 9 view .LVU2522
+5324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 7799              		.loc 1 5324 16 is_stmt 0 view .LVU2523
+ 7800 006e E1E7     		b	.L458
+ 7801              	.LVL613:
+ 7802              	.L463:
+5327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClearInputConfig->ClearInputPrescaler,
+ 7803              		.loc 1 5327 7 is_stmt 1 view .LVU2524
+ 7804 0070 2B69     		ldr	r3, [r5, #16]
+ 7805 0072 AA68     		ldr	r2, [r5, #8]
+ 7806              	.LVL614:
+5327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClearInputConfig->ClearInputPrescaler,
+ 7807              		.loc 1 5327 7 is_stmt 0 view .LVU2525
+ 7808 0074 0068     		ldr	r0, [r0]
+ 7809              	.LVL615:
+5327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClearInputConfig->ClearInputPrescaler,
+ 7810              		.loc 1 5327 7 view .LVU2526
+ 7811 0076 FFF7FEFF 		bl	TIM_ETR_SetConfig
+ 7812              	.LVL616:
+5331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 7813              		.loc 1 5331 7 is_stmt 1 view .LVU2527
+5339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 7814              		.loc 1 5339 3 view .LVU2528
+ 7815 007a E1E7     		b	.L462
+ 7816              	.L470:
+5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7817              		.loc 1 5345 9 view .LVU2529
+5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7818              		.loc 1 5345 30 is_stmt 0 view .LVU2530
+ 7819 007c 2B68     		ldr	r3, [r5]
+5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7820              		.loc 1 5345 12 view .LVU2531
+ 7821 007e 33B1     		cbz	r3, .L471
+5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7822              		.loc 1 5348 11 is_stmt 1 view .LVU2532
+ 7823 0080 2268     		ldr	r2, [r4]
+ 7824 0082 9369     		ldr	r3, [r2, #24]
+ 7825 0084 43F08003 		orr	r3, r3, #128
+ 7826 0088 9361     		str	r3, [r2, #24]
+ 7827 008a 0020     		movs	r0, #0
+ 7828 008c CCE7     		b	.L461
+ 7829              	.L471:
+5353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7830              		.loc 1 5353 11 view .LVU2533
+ 7831 008e 2268     		ldr	r2, [r4]
+ 7832 0090 9369     		ldr	r3, [r2, #24]
+ 7833 0092 23F08003 		bic	r3, r3, #128
+ 7834 0096 9361     		str	r3, [r2, #24]
+ 7835 0098 0020     		movs	r0, #0
+ 7836 009a C5E7     		b	.L461
+ 7837              	.L469:
+ARM GAS  /tmp/ccPLZXyC.s 			page 310
+
+
+5359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7838              		.loc 1 5359 9 view .LVU2534
+5359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7839              		.loc 1 5359 30 is_stmt 0 view .LVU2535
+ 7840 009c 2B68     		ldr	r3, [r5]
+5359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7841              		.loc 1 5359 12 view .LVU2536
+ 7842 009e 33B1     		cbz	r3, .L472
+5362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7843              		.loc 1 5362 11 is_stmt 1 view .LVU2537
+ 7844 00a0 2268     		ldr	r2, [r4]
+ 7845 00a2 9369     		ldr	r3, [r2, #24]
+ 7846 00a4 43F40043 		orr	r3, r3, #32768
+ 7847 00a8 9361     		str	r3, [r2, #24]
+ 7848 00aa 0020     		movs	r0, #0
+ 7849 00ac BCE7     		b	.L461
+ 7850              	.L472:
+5367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7851              		.loc 1 5367 11 view .LVU2538
+ 7852 00ae 2268     		ldr	r2, [r4]
+ 7853 00b0 9369     		ldr	r3, [r2, #24]
+ 7854 00b2 23F40043 		bic	r3, r3, #32768
+ 7855 00b6 9361     		str	r3, [r2, #24]
+ 7856 00b8 0020     		movs	r0, #0
+ 7857 00ba B5E7     		b	.L461
+ 7858              	.L468:
+5373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7859              		.loc 1 5373 9 view .LVU2539
+5373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7860              		.loc 1 5373 30 is_stmt 0 view .LVU2540
+ 7861 00bc 2B68     		ldr	r3, [r5]
+5373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7862              		.loc 1 5373 12 view .LVU2541
+ 7863 00be 33B1     		cbz	r3, .L473
+5376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7864              		.loc 1 5376 11 is_stmt 1 view .LVU2542
+ 7865 00c0 2268     		ldr	r2, [r4]
+ 7866 00c2 D369     		ldr	r3, [r2, #28]
+ 7867 00c4 43F08003 		orr	r3, r3, #128
+ 7868 00c8 D361     		str	r3, [r2, #28]
+ 7869 00ca 0020     		movs	r0, #0
+ 7870 00cc ACE7     		b	.L461
+ 7871              	.L473:
+5381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7872              		.loc 1 5381 11 view .LVU2543
+ 7873 00ce 2268     		ldr	r2, [r4]
+ 7874 00d0 D369     		ldr	r3, [r2, #28]
+ 7875 00d2 23F08003 		bic	r3, r3, #128
+ 7876 00d6 D361     		str	r3, [r2, #28]
+ 7877 00d8 0020     		movs	r0, #0
+ 7878 00da A5E7     		b	.L461
+ 7879              	.L467:
+5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7880              		.loc 1 5387 9 view .LVU2544
+5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7881              		.loc 1 5387 30 is_stmt 0 view .LVU2545
+ 7882 00dc 2B68     		ldr	r3, [r5]
+ARM GAS  /tmp/ccPLZXyC.s 			page 311
+
+
+5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7883              		.loc 1 5387 12 view .LVU2546
+ 7884 00de 33B1     		cbz	r3, .L474
+5390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7885              		.loc 1 5390 11 is_stmt 1 view .LVU2547
+ 7886 00e0 2268     		ldr	r2, [r4]
+ 7887 00e2 D369     		ldr	r3, [r2, #28]
+ 7888 00e4 43F40043 		orr	r3, r3, #32768
+ 7889 00e8 D361     		str	r3, [r2, #28]
+ 7890 00ea 0020     		movs	r0, #0
+ 7891 00ec 9CE7     		b	.L461
+ 7892              	.L474:
+5395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7893              		.loc 1 5395 11 view .LVU2548
+ 7894 00ee 2268     		ldr	r2, [r4]
+ 7895 00f0 D369     		ldr	r3, [r2, #28]
+ 7896 00f2 23F40043 		bic	r3, r3, #32768
+ 7897 00f6 D361     		str	r3, [r2, #28]
+ 7898 00f8 0020     		movs	r0, #0
+ 7899 00fa 95E7     		b	.L461
+ 7900              	.L466:
+5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7901              		.loc 1 5401 9 view .LVU2549
+5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7902              		.loc 1 5401 30 is_stmt 0 view .LVU2550
+ 7903 00fc 2B68     		ldr	r3, [r5]
+5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7904              		.loc 1 5401 12 view .LVU2551
+ 7905 00fe 33B1     		cbz	r3, .L475
+5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7906              		.loc 1 5404 11 is_stmt 1 view .LVU2552
+ 7907 0100 2268     		ldr	r2, [r4]
+ 7908 0102 536D     		ldr	r3, [r2, #84]
+ 7909 0104 43F08003 		orr	r3, r3, #128
+ 7910 0108 5365     		str	r3, [r2, #84]
+ 7911 010a 0020     		movs	r0, #0
+ 7912 010c 8CE7     		b	.L461
+ 7913              	.L475:
+5409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7914              		.loc 1 5409 11 view .LVU2553
+ 7915 010e 2268     		ldr	r2, [r4]
+ 7916 0110 536D     		ldr	r3, [r2, #84]
+ 7917 0112 23F08003 		bic	r3, r3, #128
+ 7918 0116 5365     		str	r3, [r2, #84]
+ 7919 0118 0020     		movs	r0, #0
+ 7920 011a 85E7     		b	.L461
+ 7921              	.L464:
+5415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7922              		.loc 1 5415 9 view .LVU2554
+5415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7923              		.loc 1 5415 30 is_stmt 0 view .LVU2555
+ 7924 011c 2B68     		ldr	r3, [r5]
+5415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         {
+ 7925              		.loc 1 5415 12 view .LVU2556
+ 7926 011e 33B1     		cbz	r3, .L476
+5418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7927              		.loc 1 5418 11 is_stmt 1 view .LVU2557
+ARM GAS  /tmp/ccPLZXyC.s 			page 312
+
+
+ 7928 0120 2268     		ldr	r2, [r4]
+ 7929 0122 536D     		ldr	r3, [r2, #84]
+ 7930 0124 43F40043 		orr	r3, r3, #32768
+ 7931 0128 5365     		str	r3, [r2, #84]
+ 7932 012a 0020     		movs	r0, #0
+ 7933 012c 7CE7     		b	.L461
+ 7934              	.L476:
+5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         }
+ 7935              		.loc 1 5423 11 view .LVU2558
+ 7936 012e 2268     		ldr	r2, [r4]
+ 7937 0130 536D     		ldr	r3, [r2, #84]
+ 7938 0132 23F40043 		bic	r3, r3, #32768
+ 7939 0136 5365     		str	r3, [r2, #84]
+ 7940 0138 0020     		movs	r0, #0
+ 7941 013a 75E7     		b	.L461
+ 7942              	.L478:
+5341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 7943              		.loc 1 5341 5 is_stmt 0 view .LVU2559
+ 7944 013c 0020     		movs	r0, #0
+ 7945 013e 73E7     		b	.L461
+ 7946              	.LVL617:
+ 7947              	.L477:
+ 7948              	.LCFI78:
+ 7949              		.cfi_def_cfa_offset 0
+ 7950              		.cfi_restore 4
+ 7951              		.cfi_restore 5
+ 7952              		.cfi_restore 6
+ 7953              		.cfi_restore 14
+5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7954              		.loc 1 5299 3 view .LVU2560
+ 7955 0140 0220     		movs	r0, #2
+ 7956              	.LVL618:
+5437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7957              		.loc 1 5437 1 view .LVU2561
+ 7958 0142 7047     		bx	lr
+ 7959              		.cfi_endproc
+ 7960              	.LFE211:
+ 7962              		.section	.text.HAL_TIM_ConfigClockSource,"ax",%progbits
+ 7963              		.align	1
+ 7964              		.global	HAL_TIM_ConfigClockSource
+ 7965              		.syntax unified
+ 7966              		.thumb
+ 7967              		.thumb_func
+ 7968              		.fpu fpv5-d16
+ 7970              	HAL_TIM_ConfigClockSource:
+ 7971              	.LVL619:
+ 7972              	.LFB212:
+5447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7973              		.loc 1 5447 1 is_stmt 1 view -0
+ 7974              		.cfi_startproc
+ 7975              		@ args = 0, pretend = 0, frame = 0
+ 7976              		@ frame_needed = 0, uses_anonymous_args = 0
+5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 7977              		.loc 1 5448 3 view .LVU2563
+5449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7978              		.loc 1 5449 3 view .LVU2564
+5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 313
+
+
+ 7979              		.loc 1 5452 3 view .LVU2565
+5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7980              		.loc 1 5452 3 view .LVU2566
+ 7981 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 7982 0004 012B     		cmp	r3, #1
+ 7983 0006 76D0     		beq	.L494
+5447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 7984              		.loc 1 5447 1 is_stmt 0 discriminator 2 view .LVU2567
+ 7985 0008 10B5     		push	{r4, lr}
+ 7986              	.LCFI79:
+ 7987              		.cfi_def_cfa_offset 8
+ 7988              		.cfi_offset 4, -8
+ 7989              		.cfi_offset 14, -4
+ 7990 000a 0446     		mov	r4, r0
+5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7991              		.loc 1 5452 3 is_stmt 1 discriminator 2 view .LVU2568
+ 7992 000c 0123     		movs	r3, #1
+ 7993 000e 80F83C30 		strb	r3, [r0, #60]
+5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7994              		.loc 1 5452 3 discriminator 2 view .LVU2569
+5454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7995              		.loc 1 5454 3 discriminator 2 view .LVU2570
+5454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7996              		.loc 1 5454 15 is_stmt 0 discriminator 2 view .LVU2571
+ 7997 0012 0223     		movs	r3, #2
+ 7998 0014 80F83D30 		strb	r3, [r0, #61]
+5457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 7999              		.loc 1 5457 3 is_stmt 1 discriminator 2 view .LVU2572
+5460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 8000              		.loc 1 5460 3 discriminator 2 view .LVU2573
+5460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 8001              		.loc 1 5460 17 is_stmt 0 discriminator 2 view .LVU2574
+ 8002 0018 0268     		ldr	r2, [r0]
+5460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 8003              		.loc 1 5460 11 discriminator 2 view .LVU2575
+ 8004 001a 9068     		ldr	r0, [r2, #8]
+ 8005              	.LVL620:
+5461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 8006              		.loc 1 5461 3 is_stmt 1 discriminator 2 view .LVU2576
+5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->SMCR = tmpsmcr;
+ 8007              		.loc 1 5462 3 discriminator 2 view .LVU2577
+5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   htim->Instance->SMCR = tmpsmcr;
+ 8008              		.loc 1 5462 11 is_stmt 0 discriminator 2 view .LVU2578
+ 8009 001c 374B     		ldr	r3, .L506
+ 8010 001e 0340     		ands	r3, r3, r0
+ 8011              	.LVL621:
+5463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8012              		.loc 1 5463 3 is_stmt 1 discriminator 2 view .LVU2579
+5463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8013              		.loc 1 5463 24 is_stmt 0 discriminator 2 view .LVU2580
+ 8014 0020 9360     		str	r3, [r2, #8]
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8015              		.loc 1 5465 3 is_stmt 1 discriminator 2 view .LVU2581
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8016              		.loc 1 5465 29 is_stmt 0 discriminator 2 view .LVU2582
+ 8017 0022 0B68     		ldr	r3, [r1]
+ 8018              	.LVL622:
+ARM GAS  /tmp/ccPLZXyC.s 			page 314
+
+
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8019              		.loc 1 5465 3 discriminator 2 view .LVU2583
+ 8020 0024 602B     		cmp	r3, #96
+ 8021 0026 4CD0     		beq	.L485
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8022              		.loc 1 5465 3 view .LVU2584
+ 8023 0028 29D8     		bhi	.L486
+ 8024 002a 402B     		cmp	r3, #64
+ 8025 002c 54D0     		beq	.L487
+ 8026 002e 0CD9     		bls	.L501
+ 8027 0030 502B     		cmp	r3, #80
+ 8028 0032 22D1     		bne	.L502
+5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8029              		.loc 1 5520 7 is_stmt 1 view .LVU2585
+5523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+ 8030              		.loc 1 5523 7 view .LVU2586
+5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8031              		.loc 1 5524 7 view .LVU2587
+5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8032              		.loc 1 5526 7 view .LVU2588
+ 8033 0034 CA68     		ldr	r2, [r1, #12]
+ 8034              	.LVL623:
+5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8035              		.loc 1 5526 7 is_stmt 0 view .LVU2589
+ 8036 0036 4968     		ldr	r1, [r1, #4]
+ 8037              	.LVL624:
+5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8038              		.loc 1 5526 7 view .LVU2590
+ 8039 0038 2068     		ldr	r0, [r4]
+ 8040              	.LVL625:
+5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8041              		.loc 1 5526 7 view .LVU2591
+ 8042 003a FFF7FEFF 		bl	TIM_TI1_ConfigInputStage
+ 8043              	.LVL626:
+5529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8044              		.loc 1 5529 7 is_stmt 1 view .LVU2592
+ 8045 003e 5021     		movs	r1, #80
+ 8046 0040 2068     		ldr	r0, [r4]
+ 8047 0042 FFF7FEFF 		bl	TIM_ITRx_SetConfig
+ 8048              	.LVL627:
+5530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8049              		.loc 1 5530 7 view .LVU2593
+5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8050              		.loc 1 5448 21 is_stmt 0 view .LVU2594
+ 8051 0046 0020     		movs	r0, #0
+5530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8052              		.loc 1 5530 7 view .LVU2595
+ 8053 0048 05E0     		b	.L491
+ 8054              	.LVL628:
+ 8055              	.L501:
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8056              		.loc 1 5465 3 view .LVU2596
+ 8057 004a 202B     		cmp	r3, #32
+ 8058 004c 0DD0     		beq	.L489
+ 8059 004e 09D9     		bls	.L503
+ 8060 0050 302B     		cmp	r3, #48
+ 8061 0052 0AD0     		beq	.L489
+ARM GAS  /tmp/ccPLZXyC.s 			page 315
+
+
+5578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8062              		.loc 1 5578 14 view .LVU2597
+ 8063 0054 0120     		movs	r0, #1
+ 8064              	.LVL629:
+ 8065              	.L491:
+5581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8066              		.loc 1 5581 3 is_stmt 1 view .LVU2598
+5581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8067              		.loc 1 5581 15 is_stmt 0 view .LVU2599
+ 8068 0056 0123     		movs	r3, #1
+ 8069 0058 84F83D30 		strb	r3, [r4, #61]
+5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8070              		.loc 1 5583 3 is_stmt 1 view .LVU2600
+5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8071              		.loc 1 5583 3 view .LVU2601
+ 8072 005c 0023     		movs	r3, #0
+ 8073 005e 84F83C30 		strb	r3, [r4, #60]
+5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8074              		.loc 1 5583 3 view .LVU2602
+5585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 8075              		.loc 1 5585 3 view .LVU2603
+5586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8076              		.loc 1 5586 1 is_stmt 0 view .LVU2604
+ 8077 0062 10BD     		pop	{r4, pc}
+ 8078              	.LVL630:
+ 8079              	.L503:
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8080              		.loc 1 5465 3 view .LVU2605
+ 8081 0064 0BB1     		cbz	r3, .L489
+ 8082 0066 102B     		cmp	r3, #16
+ 8083 0068 05D1     		bne	.L504
+ 8084              	.L489:
+5571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8085              		.loc 1 5571 7 is_stmt 1 view .LVU2606
+5573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8086              		.loc 1 5573 7 view .LVU2607
+ 8087 006a 1946     		mov	r1, r3
+ 8088              	.LVL631:
+5573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8089              		.loc 1 5573 7 is_stmt 0 view .LVU2608
+ 8090 006c 2068     		ldr	r0, [r4]
+ 8091 006e FFF7FEFF 		bl	TIM_ITRx_SetConfig
+ 8092              	.LVL632:
+5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8093              		.loc 1 5574 7 is_stmt 1 view .LVU2609
+5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8094              		.loc 1 5448 21 is_stmt 0 view .LVU2610
+ 8095 0072 0020     		movs	r0, #0
+5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8096              		.loc 1 5574 7 view .LVU2611
+ 8097 0074 EFE7     		b	.L491
+ 8098              	.LVL633:
+ 8099              	.L504:
+5578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8100              		.loc 1 5578 14 view .LVU2612
+ 8101 0076 0120     		movs	r0, #1
+ 8102 0078 EDE7     		b	.L491
+ARM GAS  /tmp/ccPLZXyC.s 			page 316
+
+
+ 8103              	.L502:
+ 8104 007a 0120     		movs	r0, #1
+ 8105 007c EBE7     		b	.L491
+ 8106              	.L486:
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8107              		.loc 1 5465 3 view .LVU2613
+ 8108 007e B3F5805F 		cmp	r3, #4096
+ 8109 0082 34D0     		beq	.L495
+ 8110 0084 B3F5005F 		cmp	r3, #8192
+ 8111 0088 0CD1     		bne	.L505
+5500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8112              		.loc 1 5500 7 is_stmt 1 view .LVU2614
+5503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ 8113              		.loc 1 5503 7 view .LVU2615
+5504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+ 8114              		.loc 1 5504 7 view .LVU2616
+5505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8115              		.loc 1 5505 7 view .LVU2617
+5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8116              		.loc 1 5508 7 view .LVU2618
+ 8117 008a CB68     		ldr	r3, [r1, #12]
+ 8118 008c 4A68     		ldr	r2, [r1, #4]
+ 8119              	.LVL634:
+5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8120              		.loc 1 5508 7 is_stmt 0 view .LVU2619
+ 8121 008e 8968     		ldr	r1, [r1, #8]
+ 8122              	.LVL635:
+5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8123              		.loc 1 5508 7 view .LVU2620
+ 8124 0090 2068     		ldr	r0, [r4]
+ 8125              	.LVL636:
+5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8126              		.loc 1 5508 7 view .LVU2621
+ 8127 0092 FFF7FEFF 		bl	TIM_ETR_SetConfig
+ 8128              	.LVL637:
+5513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8129              		.loc 1 5513 7 is_stmt 1 view .LVU2622
+5513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8130              		.loc 1 5513 11 is_stmt 0 view .LVU2623
+ 8131 0096 2268     		ldr	r2, [r4]
+5513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8132              		.loc 1 5513 28 view .LVU2624
+ 8133 0098 9368     		ldr	r3, [r2, #8]
+ 8134 009a 43F48043 		orr	r3, r3, #16384
+ 8135 009e 9360     		str	r3, [r2, #8]
+5514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8136              		.loc 1 5514 7 is_stmt 1 view .LVU2625
+5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8137              		.loc 1 5448 21 is_stmt 0 view .LVU2626
+ 8138 00a0 0020     		movs	r0, #0
+5514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8139              		.loc 1 5514 7 view .LVU2627
+ 8140 00a2 D8E7     		b	.L491
+ 8141              	.LVL638:
+ 8142              	.L505:
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8143              		.loc 1 5465 3 view .LVU2628
+ARM GAS  /tmp/ccPLZXyC.s 			page 317
+
+
+ 8144 00a4 702B     		cmp	r3, #112
+ 8145 00a6 24D1     		bne	.L496
+5476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8146              		.loc 1 5476 7 is_stmt 1 view .LVU2629
+5479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ 8147              		.loc 1 5479 7 view .LVU2630
+5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+ 8148              		.loc 1 5480 7 view .LVU2631
+5481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8149              		.loc 1 5481 7 view .LVU2632
+5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8150              		.loc 1 5484 7 view .LVU2633
+ 8151 00a8 CB68     		ldr	r3, [r1, #12]
+ 8152 00aa 4A68     		ldr	r2, [r1, #4]
+ 8153              	.LVL639:
+5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8154              		.loc 1 5484 7 is_stmt 0 view .LVU2634
+ 8155 00ac 8968     		ldr	r1, [r1, #8]
+ 8156              	.LVL640:
+5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8157              		.loc 1 5484 7 view .LVU2635
+ 8158 00ae 2068     		ldr	r0, [r4]
+ 8159              	.LVL641:
+5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sClockSourceConfig->ClockPrescaler,
+ 8160              		.loc 1 5484 7 view .LVU2636
+ 8161 00b0 FFF7FEFF 		bl	TIM_ETR_SetConfig
+ 8162              	.LVL642:
+5490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 8163              		.loc 1 5490 7 is_stmt 1 view .LVU2637
+5490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 8164              		.loc 1 5490 21 is_stmt 0 view .LVU2638
+ 8165 00b4 2268     		ldr	r2, [r4]
+5490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 8166              		.loc 1 5490 15 view .LVU2639
+ 8167 00b6 9368     		ldr	r3, [r2, #8]
+ 8168              	.LVL643:
+5491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Write to TIMx SMCR */
+ 8169              		.loc 1 5491 7 is_stmt 1 view .LVU2640
+5491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Write to TIMx SMCR */
+ 8170              		.loc 1 5491 15 is_stmt 0 view .LVU2641
+ 8171 00b8 43F07703 		orr	r3, r3, #119
+ 8172              	.LVL644:
+5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8173              		.loc 1 5493 7 is_stmt 1 view .LVU2642
+5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8174              		.loc 1 5493 28 is_stmt 0 view .LVU2643
+ 8175 00bc 9360     		str	r3, [r2, #8]
+5494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8176              		.loc 1 5494 7 is_stmt 1 view .LVU2644
+5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8177              		.loc 1 5448 21 is_stmt 0 view .LVU2645
+ 8178 00be 0020     		movs	r0, #0
+5494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8179              		.loc 1 5494 7 view .LVU2646
+ 8180 00c0 C9E7     		b	.L491
+ 8181              	.LVL645:
+ 8182              	.L485:
+ARM GAS  /tmp/ccPLZXyC.s 			page 318
+
+
+5536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8183              		.loc 1 5536 7 is_stmt 1 view .LVU2647
+5539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+ 8184              		.loc 1 5539 7 view .LVU2648
+5540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8185              		.loc 1 5540 7 view .LVU2649
+5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8186              		.loc 1 5542 7 view .LVU2650
+ 8187 00c2 CA68     		ldr	r2, [r1, #12]
+ 8188              	.LVL646:
+5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8189              		.loc 1 5542 7 is_stmt 0 view .LVU2651
+ 8190 00c4 4968     		ldr	r1, [r1, #4]
+ 8191              	.LVL647:
+5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8192              		.loc 1 5542 7 view .LVU2652
+ 8193 00c6 2068     		ldr	r0, [r4]
+ 8194              	.LVL648:
+5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8195              		.loc 1 5542 7 view .LVU2653
+ 8196 00c8 FFF7FEFF 		bl	TIM_TI2_ConfigInputStage
+ 8197              	.LVL649:
+5545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8198              		.loc 1 5545 7 is_stmt 1 view .LVU2654
+ 8199 00cc 6021     		movs	r1, #96
+ 8200 00ce 2068     		ldr	r0, [r4]
+ 8201 00d0 FFF7FEFF 		bl	TIM_ITRx_SetConfig
+ 8202              	.LVL650:
+5546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8203              		.loc 1 5546 7 view .LVU2655
+5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8204              		.loc 1 5448 21 is_stmt 0 view .LVU2656
+ 8205 00d4 0020     		movs	r0, #0
+5546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8206              		.loc 1 5546 7 view .LVU2657
+ 8207 00d6 BEE7     		b	.L491
+ 8208              	.LVL651:
+ 8209              	.L487:
+5552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8210              		.loc 1 5552 7 is_stmt 1 view .LVU2658
+5555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+ 8211              		.loc 1 5555 7 view .LVU2659
+5556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8212              		.loc 1 5556 7 view .LVU2660
+5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8213              		.loc 1 5558 7 view .LVU2661
+ 8214 00d8 CA68     		ldr	r2, [r1, #12]
+ 8215              	.LVL652:
+5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8216              		.loc 1 5558 7 is_stmt 0 view .LVU2662
+ 8217 00da 4968     		ldr	r1, [r1, #4]
+ 8218              	.LVL653:
+5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ 8219              		.loc 1 5558 7 view .LVU2663
+ 8220 00dc 2068     		ldr	r0, [r4]
+ 8221              	.LVL654:
+5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sClockSourceConfig->ClockPolarity,
+ARM GAS  /tmp/ccPLZXyC.s 			page 319
+
+
+ 8222              		.loc 1 5558 7 view .LVU2664
+ 8223 00de FFF7FEFF 		bl	TIM_TI1_ConfigInputStage
+ 8224              	.LVL655:
+5561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8225              		.loc 1 5561 7 is_stmt 1 view .LVU2665
+ 8226 00e2 4021     		movs	r1, #64
+ 8227 00e4 2068     		ldr	r0, [r4]
+ 8228 00e6 FFF7FEFF 		bl	TIM_ITRx_SetConfig
+ 8229              	.LVL656:
+5562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8230              		.loc 1 5562 7 view .LVU2666
+5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8231              		.loc 1 5448 21 is_stmt 0 view .LVU2667
+ 8232 00ea 0020     		movs	r0, #0
+5562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8233              		.loc 1 5562 7 view .LVU2668
+ 8234 00ec B3E7     		b	.L491
+ 8235              	.LVL657:
+ 8236              	.L495:
+5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8237              		.loc 1 5465 3 view .LVU2669
+ 8238 00ee 0020     		movs	r0, #0
+ 8239 00f0 B1E7     		b	.L491
+ 8240              	.L496:
+5578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8241              		.loc 1 5578 14 view .LVU2670
+ 8242 00f2 0120     		movs	r0, #1
+ 8243 00f4 AFE7     		b	.L491
+ 8244              	.LVL658:
+ 8245              	.L494:
+ 8246              	.LCFI80:
+ 8247              		.cfi_def_cfa_offset 0
+ 8248              		.cfi_restore 4
+ 8249              		.cfi_restore 14
+5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8250              		.loc 1 5452 3 view .LVU2671
+ 8251 00f6 0220     		movs	r0, #2
+ 8252              	.LVL659:
+5586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8253              		.loc 1 5586 1 view .LVU2672
+ 8254 00f8 7047     		bx	lr
+ 8255              	.L507:
+ 8256 00fa 00BF     		.align	2
+ 8257              	.L506:
+ 8258 00fc 8800FEFF 		.word	-130936
+ 8259              		.cfi_endproc
+ 8260              	.LFE212:
+ 8262              		.section	.text.TIM_SlaveTimer_SetConfig,"ax",%progbits
+ 8263              		.align	1
+ 8264              		.syntax unified
+ 8265              		.thumb
+ 8266              		.thumb_func
+ 8267              		.fpu fpv5-d16
+ 8269              	TIM_SlaveTimer_SetConfig:
+ 8270              	.LVL660:
+ 8271              	.LFB252:
+7384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ARM GAS  /tmp/ccPLZXyC.s 			page 320
+
+
+ 8272              		.loc 1 7384 1 is_stmt 1 view -0
+ 8273              		.cfi_startproc
+ 8274              		@ args = 0, pretend = 0, frame = 0
+ 8275              		@ frame_needed = 0, uses_anonymous_args = 0
+7384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 8276              		.loc 1 7384 1 is_stmt 0 view .LVU2674
+ 8277 0000 10B5     		push	{r4, lr}
+ 8278              	.LCFI81:
+ 8279              		.cfi_def_cfa_offset 8
+ 8280              		.cfi_offset 4, -8
+ 8281              		.cfi_offset 14, -4
+7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8282              		.loc 1 7385 3 is_stmt 1 view .LVU2675
+ 8283              	.LVL661:
+7386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccmr1;
+ 8284              		.loc 1 7386 3 view .LVU2676
+7387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpccer;
+ 8285              		.loc 1 7387 3 view .LVU2677
+7388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8286              		.loc 1 7388 3 view .LVU2678
+7391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8287              		.loc 1 7391 3 view .LVU2679
+7391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8288              		.loc 1 7391 17 is_stmt 0 view .LVU2680
+ 8289 0002 0468     		ldr	r4, [r0]
+7391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8290              		.loc 1 7391 11 view .LVU2681
+ 8291 0004 A268     		ldr	r2, [r4, #8]
+ 8292              	.LVL662:
+7394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Input Trigger source */
+ 8293              		.loc 1 7394 3 is_stmt 1 view .LVU2682
+7394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the Input Trigger source */
+ 8294              		.loc 1 7394 11 is_stmt 0 view .LVU2683
+ 8295 0006 22F07002 		bic	r2, r2, #112
+ 8296              	.LVL663:
+7396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8297              		.loc 1 7396 3 is_stmt 1 view .LVU2684
+7396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8298              		.loc 1 7396 26 is_stmt 0 view .LVU2685
+ 8299 000a 4B68     		ldr	r3, [r1, #4]
+7396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8300              		.loc 1 7396 11 view .LVU2686
+ 8301 000c 1343     		orrs	r3, r3, r2
+ 8302              	.LVL664:
+7399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the slave mode */
+ 8303              		.loc 1 7399 3 is_stmt 1 view .LVU2687
+7399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set the slave mode */
+ 8304              		.loc 1 7399 11 is_stmt 0 view .LVU2688
+ 8305 000e 2A4A     		ldr	r2, .L526
+ 8306 0010 1A40     		ands	r2, r2, r3
+ 8307              	.LVL665:
+7401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8308              		.loc 1 7401 3 is_stmt 1 view .LVU2689
+7401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8309              		.loc 1 7401 26 is_stmt 0 view .LVU2690
+ 8310 0012 0B68     		ldr	r3, [r1]
+7401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 321
+
+
+ 8311              		.loc 1 7401 11 view .LVU2691
+ 8312 0014 1343     		orrs	r3, r3, r2
+ 8313              	.LVL666:
+7404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8314              		.loc 1 7404 3 is_stmt 1 view .LVU2692
+7404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8315              		.loc 1 7404 24 is_stmt 0 view .LVU2693
+ 8316 0016 A360     		str	r3, [r4, #8]
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8317              		.loc 1 7407 3 is_stmt 1 view .LVU2694
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8318              		.loc 1 7407 23 is_stmt 0 view .LVU2695
+ 8319 0018 4B68     		ldr	r3, [r1, #4]
+ 8320              	.LVL667:
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8321              		.loc 1 7407 3 view .LVU2696
+ 8322 001a 502B     		cmp	r3, #80
+ 8323 001c 32D0     		beq	.L509
+ 8324 001e 0BD9     		bls	.L523
+ 8325 0020 602B     		cmp	r3, #96
+ 8326 0022 36D0     		beq	.L514
+ 8327 0024 702B     		cmp	r3, #112
+ 8328 0026 43D1     		bne	.L520
+7412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ 8329              		.loc 1 7412 7 is_stmt 1 view .LVU2697
+7413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ 8330              		.loc 1 7413 7 view .LVU2698
+7414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ 8331              		.loc 1 7414 7 view .LVU2699
+7415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Configure the ETR Trigger source */
+ 8332              		.loc 1 7415 7 view .LVU2700
+7417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sSlaveConfig->TriggerPrescaler,
+ 8333              		.loc 1 7417 7 view .LVU2701
+ 8334 0028 0B69     		ldr	r3, [r1, #16]
+ 8335 002a 8A68     		ldr	r2, [r1, #8]
+ 8336 002c C968     		ldr	r1, [r1, #12]
+ 8337              	.LVL668:
+7417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sSlaveConfig->TriggerPrescaler,
+ 8338              		.loc 1 7417 7 is_stmt 0 view .LVU2702
+ 8339 002e 0068     		ldr	r0, [r0]
+ 8340              	.LVL669:
+7417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                         sSlaveConfig->TriggerPrescaler,
+ 8341              		.loc 1 7417 7 view .LVU2703
+ 8342 0030 FFF7FEFF 		bl	TIM_ETR_SetConfig
+ 8343              	.LVL670:
+7421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8344              		.loc 1 7421 7 is_stmt 1 view .LVU2704
+7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8345              		.loc 1 7385 21 is_stmt 0 view .LVU2705
+ 8346 0034 0020     		movs	r0, #0
+7421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8347              		.loc 1 7421 7 view .LVU2706
+ 8348 0036 0FE0     		b	.L512
+ 8349              	.LVL671:
+ 8350              	.L523:
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8351              		.loc 1 7407 3 view .LVU2707
+ARM GAS  /tmp/ccPLZXyC.s 			page 322
+
+
+ 8352 0038 402B     		cmp	r3, #64
+ 8353 003a 0ED0     		beq	.L511
+ 8354 003c 01D9     		bls	.L524
+7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8355              		.loc 1 7489 14 view .LVU2708
+ 8356 003e 0120     		movs	r0, #1
+ 8357              	.LVL672:
+7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8358              		.loc 1 7489 14 view .LVU2709
+ 8359 0040 0AE0     		b	.L512
+ 8360              	.LVL673:
+ 8361              	.L524:
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8362              		.loc 1 7407 3 view .LVU2710
+ 8363 0042 202B     		cmp	r3, #32
+ 8364 0044 2CD0     		beq	.L516
+ 8365 0046 03D9     		bls	.L525
+ 8366 0048 302B     		cmp	r3, #48
+ 8367 004a 2FD1     		bne	.L519
+ 8368 004c 0020     		movs	r0, #0
+ 8369              	.LVL674:
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8370              		.loc 1 7407 3 view .LVU2711
+ 8371 004e 03E0     		b	.L512
+ 8372              	.LVL675:
+ 8373              	.L525:
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8374              		.loc 1 7407 3 view .LVU2712
+ 8375 0050 43B3     		cbz	r3, .L517
+ 8376 0052 102B     		cmp	r3, #16
+ 8377 0054 28D1     		bne	.L518
+ 8378 0056 0020     		movs	r0, #0
+ 8379              	.LVL676:
+ 8380              	.L512:
+7494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8381              		.loc 1 7494 1 view .LVU2713
+ 8382 0058 10BD     		pop	{r4, pc}
+ 8383              	.LVL677:
+ 8384              	.L511:
+7427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ 8385              		.loc 1 7427 7 is_stmt 1 view .LVU2714
+7428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8386              		.loc 1 7428 7 view .LVU2715
+7430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 8387              		.loc 1 7430 7 view .LVU2716
+7430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 8388              		.loc 1 7430 23 is_stmt 0 view .LVU2717
+ 8389 005a 0B68     		ldr	r3, [r1]
+7430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 8390              		.loc 1 7430 10 view .LVU2718
+ 8391 005c 052B     		cmp	r3, #5
+ 8392 005e 29D0     		beq	.L521
+7436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ 8393              		.loc 1 7436 7 is_stmt 1 view .LVU2719
+7436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ 8394              		.loc 1 7436 21 is_stmt 0 view .LVU2720
+ 8395 0060 0368     		ldr	r3, [r0]
+ARM GAS  /tmp/ccPLZXyC.s 			page 323
+
+
+7436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ 8396              		.loc 1 7436 15 view .LVU2721
+ 8397 0062 1C6A     		ldr	r4, [r3, #32]
+ 8398              	.LVL678:
+7437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpccmr1 = htim->Instance->CCMR1;
+ 8399              		.loc 1 7437 7 is_stmt 1 view .LVU2722
+7437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpccmr1 = htim->Instance->CCMR1;
+ 8400              		.loc 1 7437 28 is_stmt 0 view .LVU2723
+ 8401 0064 1A6A     		ldr	r2, [r3, #32]
+ 8402 0066 22F00102 		bic	r2, r2, #1
+ 8403 006a 1A62     		str	r2, [r3, #32]
+7438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8404              		.loc 1 7438 7 is_stmt 1 view .LVU2724
+7438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8405              		.loc 1 7438 22 is_stmt 0 view .LVU2725
+ 8406 006c 0268     		ldr	r2, [r0]
+7438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8407              		.loc 1 7438 16 view .LVU2726
+ 8408 006e 9369     		ldr	r3, [r2, #24]
+ 8409              	.LVL679:
+7441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+ 8410              		.loc 1 7441 7 is_stmt 1 view .LVU2727
+7441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+ 8411              		.loc 1 7441 16 is_stmt 0 view .LVU2728
+ 8412 0070 23F0F003 		bic	r3, r3, #240
+ 8413              	.LVL680:
+7442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8414              		.loc 1 7442 7 is_stmt 1 view .LVU2729
+7442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8415              		.loc 1 7442 33 is_stmt 0 view .LVU2730
+ 8416 0074 0969     		ldr	r1, [r1, #16]
+ 8417              	.LVL681:
+7442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8418              		.loc 1 7442 16 view .LVU2731
+ 8419 0076 43EA0113 		orr	r3, r3, r1, lsl #4
+ 8420              	.LVL682:
+7445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCER = tmpccer;
+ 8421              		.loc 1 7445 7 is_stmt 1 view .LVU2732
+7445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->Instance->CCER = tmpccer;
+ 8422              		.loc 1 7445 29 is_stmt 0 view .LVU2733
+ 8423 007a 9361     		str	r3, [r2, #24]
+7446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8424              		.loc 1 7446 7 is_stmt 1 view .LVU2734
+7446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8425              		.loc 1 7446 11 is_stmt 0 view .LVU2735
+ 8426 007c 0368     		ldr	r3, [r0]
+ 8427              	.LVL683:
+7446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8428              		.loc 1 7446 28 view .LVU2736
+ 8429 007e 1C62     		str	r4, [r3, #32]
+ 8430              	.LVL684:
+7447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8431              		.loc 1 7447 7 is_stmt 1 view .LVU2737
+7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8432              		.loc 1 7385 21 is_stmt 0 view .LVU2738
+ 8433 0080 0020     		movs	r0, #0
+ 8434              	.LVL685:
+ARM GAS  /tmp/ccPLZXyC.s 			page 324
+
+
+7447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8435              		.loc 1 7447 7 view .LVU2739
+ 8436 0082 E9E7     		b	.L512
+ 8437              	.LVL686:
+ 8438              	.L509:
+7453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ 8439              		.loc 1 7453 7 is_stmt 1 view .LVU2740
+7454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ 8440              		.loc 1 7454 7 view .LVU2741
+7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8441              		.loc 1 7455 7 view .LVU2742
+7458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8442              		.loc 1 7458 7 view .LVU2743
+ 8443 0084 0A69     		ldr	r2, [r1, #16]
+ 8444 0086 8968     		ldr	r1, [r1, #8]
+ 8445              	.LVL687:
+7458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8446              		.loc 1 7458 7 is_stmt 0 view .LVU2744
+ 8447 0088 0068     		ldr	r0, [r0]
+ 8448              	.LVL688:
+7458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8449              		.loc 1 7458 7 view .LVU2745
+ 8450 008a FFF7FEFF 		bl	TIM_TI1_ConfigInputStage
+ 8451              	.LVL689:
+7461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8452              		.loc 1 7461 7 is_stmt 1 view .LVU2746
+7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8453              		.loc 1 7385 21 is_stmt 0 view .LVU2747
+ 8454 008e 0020     		movs	r0, #0
+7461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8455              		.loc 1 7461 7 view .LVU2748
+ 8456 0090 E2E7     		b	.L512
+ 8457              	.LVL690:
+ 8458              	.L514:
+7467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ 8459              		.loc 1 7467 7 is_stmt 1 view .LVU2749
+7468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ 8460              		.loc 1 7468 7 view .LVU2750
+7469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8461              		.loc 1 7469 7 view .LVU2751
+7472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8462              		.loc 1 7472 7 view .LVU2752
+ 8463 0092 0A69     		ldr	r2, [r1, #16]
+ 8464 0094 8968     		ldr	r1, [r1, #8]
+ 8465              	.LVL691:
+7472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8466              		.loc 1 7472 7 is_stmt 0 view .LVU2753
+ 8467 0096 0068     		ldr	r0, [r0]
+ 8468              	.LVL692:
+7472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                                sSlaveConfig->TriggerPolarity,
+ 8469              		.loc 1 7472 7 view .LVU2754
+ 8470 0098 FFF7FEFF 		bl	TIM_TI2_ConfigInputStage
+ 8471              	.LVL693:
+7475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8472              		.loc 1 7475 7 is_stmt 1 view .LVU2755
+7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8473              		.loc 1 7385 21 is_stmt 0 view .LVU2756
+ARM GAS  /tmp/ccPLZXyC.s 			page 325
+
+
+ 8474 009c 0020     		movs	r0, #0
+7475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8475              		.loc 1 7475 7 view .LVU2757
+ 8476 009e DBE7     		b	.L512
+ 8477              	.LVL694:
+ 8478              	.L516:
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8479              		.loc 1 7407 3 view .LVU2758
+ 8480 00a0 0020     		movs	r0, #0
+ 8481              	.LVL695:
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8482              		.loc 1 7407 3 view .LVU2759
+ 8483 00a2 D9E7     		b	.L512
+ 8484              	.LVL696:
+ 8485              	.L517:
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8486              		.loc 1 7407 3 view .LVU2760
+ 8487 00a4 0020     		movs	r0, #0
+ 8488              	.LVL697:
+7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8489              		.loc 1 7407 3 view .LVU2761
+ 8490 00a6 D7E7     		b	.L512
+ 8491              	.LVL698:
+ 8492              	.L518:
+7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8493              		.loc 1 7489 14 view .LVU2762
+ 8494 00a8 0120     		movs	r0, #1
+ 8495              	.LVL699:
+7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8496              		.loc 1 7489 14 view .LVU2763
+ 8497 00aa D5E7     		b	.L512
+ 8498              	.LVL700:
+ 8499              	.L519:
+7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8500              		.loc 1 7489 14 view .LVU2764
+ 8501 00ac 0120     		movs	r0, #1
+ 8502              	.LVL701:
+7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8503              		.loc 1 7489 14 view .LVU2765
+ 8504 00ae D3E7     		b	.L512
+ 8505              	.LVL702:
+ 8506              	.L520:
+7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8507              		.loc 1 7489 14 view .LVU2766
+ 8508 00b0 0120     		movs	r0, #1
+ 8509              	.LVL703:
+7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 8510              		.loc 1 7489 14 view .LVU2767
+ 8511 00b2 D1E7     		b	.L512
+ 8512              	.LVL704:
+ 8513              	.L521:
+7432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 8514              		.loc 1 7432 16 view .LVU2768
+ 8515 00b4 0120     		movs	r0, #1
+ 8516              	.LVL705:
+7432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 8517              		.loc 1 7432 16 view .LVU2769
+ARM GAS  /tmp/ccPLZXyC.s 			page 326
+
+
+ 8518 00b6 CFE7     		b	.L512
+ 8519              	.L527:
+ 8520              		.align	2
+ 8521              	.L526:
+ 8522 00b8 F8FFFEFF 		.word	-65544
+ 8523              		.cfi_endproc
+ 8524              	.LFE252:
+ 8526              		.section	.text.HAL_TIM_SlaveConfigSynchro,"ax",%progbits
+ 8527              		.align	1
+ 8528              		.global	HAL_TIM_SlaveConfigSynchro
+ 8529              		.syntax unified
+ 8530              		.thumb
+ 8531              		.thumb_func
+ 8532              		.fpu fpv5-d16
+ 8534              	HAL_TIM_SlaveConfigSynchro:
+ 8535              	.LVL706:
+ 8536              	.LFB214:
+5633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 8537              		.loc 1 5633 1 is_stmt 1 view -0
+ 8538              		.cfi_startproc
+ 8539              		@ args = 0, pretend = 0, frame = 0
+ 8540              		@ frame_needed = 0, uses_anonymous_args = 0
+5635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ 8541              		.loc 1 5635 3 view .LVU2771
+5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+ 8542              		.loc 1 5636 3 view .LVU2772
+5637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8543              		.loc 1 5637 3 view .LVU2773
+5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8544              		.loc 1 5639 3 view .LVU2774
+5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8545              		.loc 1 5639 3 view .LVU2775
+ 8546 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 8547 0004 012B     		cmp	r3, #1
+ 8548 0006 22D0     		beq	.L531
+5633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 8549              		.loc 1 5633 1 is_stmt 0 discriminator 2 view .LVU2776
+ 8550 0008 10B5     		push	{r4, lr}
+ 8551              	.LCFI82:
+ 8552              		.cfi_def_cfa_offset 8
+ 8553              		.cfi_offset 4, -8
+ 8554              		.cfi_offset 14, -4
+ 8555 000a 0446     		mov	r4, r0
+5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8556              		.loc 1 5639 3 is_stmt 1 discriminator 2 view .LVU2777
+ 8557 000c 0123     		movs	r3, #1
+ 8558 000e 80F83C30 		strb	r3, [r0, #60]
+5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8559              		.loc 1 5639 3 discriminator 2 view .LVU2778
+5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8560              		.loc 1 5641 3 discriminator 2 view .LVU2779
+5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8561              		.loc 1 5641 15 is_stmt 0 discriminator 2 view .LVU2780
+ 8562 0012 0223     		movs	r3, #2
+ 8563 0014 80F83D30 		strb	r3, [r0, #61]
+5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8564              		.loc 1 5643 3 is_stmt 1 discriminator 2 view .LVU2781
+ARM GAS  /tmp/ccPLZXyC.s 			page 327
+
+
+5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8565              		.loc 1 5643 7 is_stmt 0 discriminator 2 view .LVU2782
+ 8566 0018 FFF7FEFF 		bl	TIM_SlaveTimer_SetConfig
+ 8567              	.LVL707:
+5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8568              		.loc 1 5643 6 discriminator 2 view .LVU2783
+ 8569 001c 80B9     		cbnz	r0, .L536
+5651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8570              		.loc 1 5651 3 is_stmt 1 view .LVU2784
+ 8571 001e 2268     		ldr	r2, [r4]
+ 8572 0020 D368     		ldr	r3, [r2, #12]
+ 8573 0022 23F04003 		bic	r3, r3, #64
+ 8574 0026 D360     		str	r3, [r2, #12]
+5654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8575              		.loc 1 5654 3 view .LVU2785
+ 8576 0028 2268     		ldr	r2, [r4]
+ 8577 002a D368     		ldr	r3, [r2, #12]
+ 8578 002c 23F48043 		bic	r3, r3, #16384
+ 8579 0030 D360     		str	r3, [r2, #12]
+5656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8580              		.loc 1 5656 3 view .LVU2786
+5656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8581              		.loc 1 5656 15 is_stmt 0 view .LVU2787
+ 8582 0032 0123     		movs	r3, #1
+ 8583 0034 84F83D30 		strb	r3, [r4, #61]
+5658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8584              		.loc 1 5658 3 is_stmt 1 view .LVU2788
+5658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8585              		.loc 1 5658 3 view .LVU2789
+ 8586 0038 0023     		movs	r3, #0
+ 8587 003a 84F83C30 		strb	r3, [r4, #60]
+5658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8588              		.loc 1 5658 3 view .LVU2790
+5660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 8589              		.loc 1 5660 3 view .LVU2791
+ 8590              	.L529:
+5661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8591              		.loc 1 5661 1 is_stmt 0 view .LVU2792
+ 8592 003e 10BD     		pop	{r4, pc}
+ 8593              	.LVL708:
+ 8594              	.L536:
+5645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+ 8595              		.loc 1 5645 5 is_stmt 1 view .LVU2793
+5645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+ 8596              		.loc 1 5645 17 is_stmt 0 view .LVU2794
+ 8597 0040 0120     		movs	r0, #1
+ 8598 0042 84F83D00 		strb	r0, [r4, #61]
+5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 8599              		.loc 1 5646 5 is_stmt 1 view .LVU2795
+5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 8600              		.loc 1 5646 5 view .LVU2796
+ 8601 0046 0023     		movs	r3, #0
+ 8602 0048 84F83C30 		strb	r3, [r4, #60]
+5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 8603              		.loc 1 5646 5 view .LVU2797
+5647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 8604              		.loc 1 5647 5 view .LVU2798
+ARM GAS  /tmp/ccPLZXyC.s 			page 328
+
+
+5647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 8605              		.loc 1 5647 12 is_stmt 0 view .LVU2799
+ 8606 004c F7E7     		b	.L529
+ 8607              	.LVL709:
+ 8608              	.L531:
+ 8609              	.LCFI83:
+ 8610              		.cfi_def_cfa_offset 0
+ 8611              		.cfi_restore 4
+ 8612              		.cfi_restore 14
+5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8613              		.loc 1 5639 3 view .LVU2800
+ 8614 004e 0220     		movs	r0, #2
+ 8615              	.LVL710:
+5661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8616              		.loc 1 5661 1 view .LVU2801
+ 8617 0050 7047     		bx	lr
+ 8618              		.cfi_endproc
+ 8619              	.LFE214:
+ 8621              		.section	.text.HAL_TIM_SlaveConfigSynchro_IT,"ax",%progbits
+ 8622              		.align	1
+ 8623              		.global	HAL_TIM_SlaveConfigSynchro_IT
+ 8624              		.syntax unified
+ 8625              		.thumb
+ 8626              		.thumb_func
+ 8627              		.fpu fpv5-d16
+ 8629              	HAL_TIM_SlaveConfigSynchro_IT:
+ 8630              	.LVL711:
+ 8631              	.LFB215:
+5674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 8632              		.loc 1 5674 1 is_stmt 1 view -0
+ 8633              		.cfi_startproc
+ 8634              		@ args = 0, pretend = 0, frame = 0
+ 8635              		@ frame_needed = 0, uses_anonymous_args = 0
+5676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ 8636              		.loc 1 5676 3 view .LVU2803
+5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+ 8637              		.loc 1 5677 3 view .LVU2804
+5678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8638              		.loc 1 5678 3 view .LVU2805
+5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8639              		.loc 1 5680 3 view .LVU2806
+5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8640              		.loc 1 5680 3 view .LVU2807
+ 8641 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 8642 0004 012B     		cmp	r3, #1
+ 8643 0006 22D0     		beq	.L540
+5674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 8644              		.loc 1 5674 1 is_stmt 0 discriminator 2 view .LVU2808
+ 8645 0008 10B5     		push	{r4, lr}
+ 8646              	.LCFI84:
+ 8647              		.cfi_def_cfa_offset 8
+ 8648              		.cfi_offset 4, -8
+ 8649              		.cfi_offset 14, -4
+ 8650 000a 0446     		mov	r4, r0
+5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8651              		.loc 1 5680 3 is_stmt 1 discriminator 2 view .LVU2809
+ 8652 000c 0123     		movs	r3, #1
+ARM GAS  /tmp/ccPLZXyC.s 			page 329
+
+
+ 8653 000e 80F83C30 		strb	r3, [r0, #60]
+5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8654              		.loc 1 5680 3 discriminator 2 view .LVU2810
+5682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8655              		.loc 1 5682 3 discriminator 2 view .LVU2811
+5682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8656              		.loc 1 5682 15 is_stmt 0 discriminator 2 view .LVU2812
+ 8657 0012 0223     		movs	r3, #2
+ 8658 0014 80F83D30 		strb	r3, [r0, #61]
+5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8659              		.loc 1 5684 3 is_stmt 1 discriminator 2 view .LVU2813
+5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8660              		.loc 1 5684 7 is_stmt 0 discriminator 2 view .LVU2814
+ 8661 0018 FFF7FEFF 		bl	TIM_SlaveTimer_SetConfig
+ 8662              	.LVL712:
+5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8663              		.loc 1 5684 6 discriminator 2 view .LVU2815
+ 8664 001c 80B9     		cbnz	r0, .L545
+5692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8665              		.loc 1 5692 3 is_stmt 1 view .LVU2816
+ 8666 001e 2268     		ldr	r2, [r4]
+ 8667 0020 D368     		ldr	r3, [r2, #12]
+ 8668 0022 43F04003 		orr	r3, r3, #64
+ 8669 0026 D360     		str	r3, [r2, #12]
+5695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8670              		.loc 1 5695 3 view .LVU2817
+ 8671 0028 2268     		ldr	r2, [r4]
+ 8672 002a D368     		ldr	r3, [r2, #12]
+ 8673 002c 23F48043 		bic	r3, r3, #16384
+ 8674 0030 D360     		str	r3, [r2, #12]
+5697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8675              		.loc 1 5697 3 view .LVU2818
+5697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8676              		.loc 1 5697 15 is_stmt 0 view .LVU2819
+ 8677 0032 0123     		movs	r3, #1
+ 8678 0034 84F83D30 		strb	r3, [r4, #61]
+5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8679              		.loc 1 5699 3 is_stmt 1 view .LVU2820
+5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8680              		.loc 1 5699 3 view .LVU2821
+ 8681 0038 0023     		movs	r3, #0
+ 8682 003a 84F83C30 		strb	r3, [r4, #60]
+5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8683              		.loc 1 5699 3 view .LVU2822
+5701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 8684              		.loc 1 5701 3 view .LVU2823
+ 8685              	.L538:
+5702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8686              		.loc 1 5702 1 is_stmt 0 view .LVU2824
+ 8687 003e 10BD     		pop	{r4, pc}
+ 8688              	.LVL713:
+ 8689              	.L545:
+5686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+ 8690              		.loc 1 5686 5 is_stmt 1 view .LVU2825
+5686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_UNLOCK(htim);
+ 8691              		.loc 1 5686 17 is_stmt 0 view .LVU2826
+ 8692 0040 0120     		movs	r0, #1
+ARM GAS  /tmp/ccPLZXyC.s 			page 330
+
+
+ 8693 0042 84F83D00 		strb	r0, [r4, #61]
+5687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 8694              		.loc 1 5687 5 is_stmt 1 view .LVU2827
+5687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 8695              		.loc 1 5687 5 view .LVU2828
+ 8696 0046 0023     		movs	r3, #0
+ 8697 0048 84F83C30 		strb	r3, [r4, #60]
+5687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     return HAL_ERROR;
+ 8698              		.loc 1 5687 5 view .LVU2829
+5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 8699              		.loc 1 5688 5 view .LVU2830
+5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 8700              		.loc 1 5688 12 is_stmt 0 view .LVU2831
+ 8701 004c F7E7     		b	.L538
+ 8702              	.LVL714:
+ 8703              	.L540:
+ 8704              	.LCFI85:
+ 8705              		.cfi_def_cfa_offset 0
+ 8706              		.cfi_restore 4
+ 8707              		.cfi_restore 14
+5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8708              		.loc 1 5680 3 view .LVU2832
+ 8709 004e 0220     		movs	r0, #2
+ 8710              	.LVL715:
+5702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8711              		.loc 1 5702 1 view .LVU2833
+ 8712 0050 7047     		bx	lr
+ 8713              		.cfi_endproc
+ 8714              	.LFE215:
+ 8716              		.section	.text.TIM_CCxChannelCmd,"ax",%progbits
+ 8717              		.align	1
+ 8718              		.global	TIM_CCxChannelCmd
+ 8719              		.syntax unified
+ 8720              		.thumb
+ 8721              		.thumb_func
+ 8722              		.fpu fpv5-d16
+ 8724              	TIM_CCxChannelCmd:
+ 8725              	.LVL716:
+ 8726              	.LFB261:
+7826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+7828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @brief  Enables or disables the TIM Capture Compare Channel x.
+7829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  TIMx to select the TIM peripheral
+7830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  Channel specifies the TIM Channel
+7831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be one of the following values:
+7832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1
+7833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2
+7834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3
+7835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_4: TIM Channel 4
+7836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+7837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+7838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+7839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+7840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   * @retval None
+7841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   */
+7842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+7843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** {
+ARM GAS  /tmp/ccPLZXyC.s 			page 331
+
+
+ 8727              		.loc 1 7843 1 is_stmt 1 view -0
+ 8728              		.cfi_startproc
+ 8729              		@ args = 0, pretend = 0, frame = 0
+ 8730              		@ frame_needed = 0, uses_anonymous_args = 0
+ 8731              		@ link register save eliminated.
+7844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmp;
+ 8732              		.loc 1 7844 3 view .LVU2835
+7845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+7847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ 8733              		.loc 1 7847 3 view .LVU2836
+7848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_CHANNELS(Channel));
+ 8734              		.loc 1 7848 3 view .LVU2837
+7849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+ 8735              		.loc 1 7850 3 view .LVU2838
+ 8736              		.loc 1 7850 35 is_stmt 0 view .LVU2839
+ 8737 0000 01F01F01 		and	r1, r1, #31
+ 8738              	.LVL717:
+ 8739              		.loc 1 7850 7 view .LVU2840
+ 8740 0004 0123     		movs	r3, #1
+ 8741 0006 03FA01FC 		lsl	ip, r3, r1
+ 8742              	.LVL718:
+7851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Reset the CCxE Bit */
+7853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER &= ~tmp;
+ 8743              		.loc 1 7853 3 is_stmt 1 view .LVU2841
+ 8744              		.loc 1 7853 14 is_stmt 0 view .LVU2842
+ 8745 000a 036A     		ldr	r3, [r0, #32]
+ 8746 000c 23EA0C03 		bic	r3, r3, ip
+ 8747 0010 0362     		str	r3, [r0, #32]
+7854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+7855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Set or reset the CCxE Bit */
+7856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ 8748              		.loc 1 7856 3 is_stmt 1 view .LVU2843
+ 8749              		.loc 1 7856 14 is_stmt 0 view .LVU2844
+ 8750 0012 036A     		ldr	r3, [r0, #32]
+ 8751              		.loc 1 7856 41 view .LVU2845
+ 8752 0014 02FA01F1 		lsl	r1, r2, r1
+ 8753              		.loc 1 7856 14 view .LVU2846
+ 8754 0018 0B43     		orrs	r3, r3, r1
+ 8755 001a 0362     		str	r3, [r0, #32]
+7857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 8756              		.loc 1 7857 1 view .LVU2847
+ 8757 001c 7047     		bx	lr
+ 8758              		.cfi_endproc
+ 8759              	.LFE261:
+ 8761              		.section	.text.HAL_TIM_OC_Start,"ax",%progbits
+ 8762              		.align	1
+ 8763              		.global	HAL_TIM_OC_Start
+ 8764              		.syntax unified
+ 8765              		.thumb
+ 8766              		.thumb_func
+ 8767              		.fpu fpv5-d16
+ 8769              	HAL_TIM_OC_Start:
+ 8770              	.LVL719:
+ 8771              	.LFB155:
+ARM GAS  /tmp/ccPLZXyC.s 			page 332
+
+
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8772              		.loc 1 795 1 is_stmt 1 view -0
+ 8773              		.cfi_startproc
+ 8774              		@ args = 0, pretend = 0, frame = 0
+ 8775              		@ frame_needed = 0, uses_anonymous_args = 0
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 8776              		.loc 1 795 1 is_stmt 0 view .LVU2849
+ 8777 0000 10B5     		push	{r4, lr}
+ 8778              	.LCFI86:
+ 8779              		.cfi_def_cfa_offset 8
+ 8780              		.cfi_offset 4, -8
+ 8781              		.cfi_offset 14, -4
+ 8782 0002 0446     		mov	r4, r0
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8783              		.loc 1 796 3 is_stmt 1 view .LVU2850
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8784              		.loc 1 799 3 view .LVU2851
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8785              		.loc 1 802 3 view .LVU2852
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8786              		.loc 1 802 44 is_stmt 0 view .LVU2853
+ 8787 0004 0846     		mov	r0, r1
+ 8788              	.LVL720:
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8789              		.loc 1 802 44 view .LVU2854
+ 8790 0006 0029     		cmp	r1, #0
+ 8791 0008 42D1     		bne	.L548
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8792              		.loc 1 802 7 discriminator 1 view .LVU2855
+ 8793 000a 94F83E30 		ldrb	r3, [r4, #62]	@ zero_extendqisi2
+ 8794 000e DBB2     		uxtb	r3, r3
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8795              		.loc 1 802 44 discriminator 1 view .LVU2856
+ 8796 0010 013B     		subs	r3, r3, #1
+ 8797 0012 18BF     		it	ne
+ 8798 0014 0123     		movne	r3, #1
+ 8799              	.L549:
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8800              		.loc 1 802 6 discriminator 20 view .LVU2857
+ 8801 0016 002B     		cmp	r3, #0
+ 8802 0018 40F08F80 		bne	.L564
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8803              		.loc 1 808 3 is_stmt 1 view .LVU2858
+ 8804 001c 0028     		cmp	r0, #0
+ 8805 001e 62D1     		bne	.L555
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8806              		.loc 1 808 3 is_stmt 0 discriminator 1 view .LVU2859
+ 8807 0020 0223     		movs	r3, #2
+ 8808 0022 84F83E30 		strb	r3, [r4, #62]
+ 8809              	.L556:
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8810              		.loc 1 811 3 is_stmt 1 view .LVU2860
+ 8811 0026 0122     		movs	r2, #1
+ 8812 0028 0146     		mov	r1, r0
+ 8813              	.LVL721:
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8814              		.loc 1 811 3 is_stmt 0 view .LVU2861
+ARM GAS  /tmp/ccPLZXyC.s 			page 333
+
+
+ 8815 002a 2068     		ldr	r0, [r4]
+ 8816              	.LVL722:
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8817              		.loc 1 811 3 view .LVU2862
+ 8818 002c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 8819              	.LVL723:
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8820              		.loc 1 813 3 is_stmt 1 view .LVU2863
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8821              		.loc 1 813 7 is_stmt 0 view .LVU2864
+ 8822 0030 2368     		ldr	r3, [r4]
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8823              		.loc 1 813 6 view .LVU2865
+ 8824 0032 4449     		ldr	r1, .L575
+ 8825 0034 444A     		ldr	r2, .L575+4
+ 8826 0036 9342     		cmp	r3, r2
+ 8827 0038 18BF     		it	ne
+ 8828 003a 8B42     		cmpne	r3, r1
+ 8829 003c 03D1     		bne	.L561
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 8830              		.loc 1 816 5 is_stmt 1 view .LVU2866
+ 8831 003e 5A6C     		ldr	r2, [r3, #68]
+ 8832 0040 42F40042 		orr	r2, r2, #32768
+ 8833 0044 5A64     		str	r2, [r3, #68]
+ 8834              	.L561:
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8835              		.loc 1 820 3 view .LVU2867
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8836              		.loc 1 820 7 is_stmt 0 view .LVU2868
+ 8837 0046 2368     		ldr	r3, [r4]
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8838              		.loc 1 820 6 view .LVU2869
+ 8839 0048 3E4A     		ldr	r2, .L575
+ 8840 004a B3F1804F 		cmp	r3, #1073741824
+ 8841 004e 18BF     		it	ne
+ 8842 0050 9342     		cmpne	r3, r2
+ 8843 0052 64D0     		beq	.L562
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8844              		.loc 1 820 7 discriminator 1 view .LVU2870
+ 8845 0054 A2F57C42 		sub	r2, r2, #64512
+ 8846 0058 9342     		cmp	r3, r2
+ 8847 005a 60D0     		beq	.L562
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8848              		.loc 1 820 7 discriminator 2 view .LVU2871
+ 8849 005c 02F58062 		add	r2, r2, #1024
+ 8850 0060 9342     		cmp	r3, r2
+ 8851 0062 5CD0     		beq	.L562
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8852              		.loc 1 820 7 discriminator 3 view .LVU2872
+ 8853 0064 02F58062 		add	r2, r2, #1024
+ 8854 0068 9342     		cmp	r3, r2
+ 8855 006a 58D0     		beq	.L562
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8856              		.loc 1 820 7 discriminator 4 view .LVU2873
+ 8857 006c 02F57842 		add	r2, r2, #63488
+ 8858 0070 9342     		cmp	r3, r2
+ 8859 0072 54D0     		beq	.L562
+ARM GAS  /tmp/ccPLZXyC.s 			page 334
+
+
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8860              		.loc 1 820 7 discriminator 5 view .LVU2874
+ 8861 0074 02F57052 		add	r2, r2, #15360
+ 8862 0078 9342     		cmp	r3, r2
+ 8863 007a 50D0     		beq	.L562
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8864              		.loc 1 820 7 discriminator 6 view .LVU2875
+ 8865 007c A2F59432 		sub	r2, r2, #75776
+ 8866 0080 9342     		cmp	r3, r2
+ 8867 0082 4CD0     		beq	.L562
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 8868              		.loc 1 830 5 is_stmt 1 view .LVU2876
+ 8869 0084 1A68     		ldr	r2, [r3]
+ 8870 0086 42F00102 		orr	r2, r2, #1
+ 8871 008a 1A60     		str	r2, [r3]
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 8872              		.loc 1 834 10 is_stmt 0 view .LVU2877
+ 8873 008c 0020     		movs	r0, #0
+ 8874 008e 55E0     		b	.L554
+ 8875              	.LVL724:
+ 8876              	.L548:
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8877              		.loc 1 802 44 discriminator 2 view .LVU2878
+ 8878 0090 0429     		cmp	r1, #4
+ 8879 0092 0CD0     		beq	.L567
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8880              		.loc 1 802 44 discriminator 5 view .LVU2879
+ 8881 0094 0829     		cmp	r1, #8
+ 8882 0096 11D0     		beq	.L568
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8883              		.loc 1 802 44 discriminator 8 view .LVU2880
+ 8884 0098 0C29     		cmp	r1, #12
+ 8885 009a 16D0     		beq	.L569
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8886              		.loc 1 802 44 discriminator 11 view .LVU2881
+ 8887 009c 1029     		cmp	r1, #16
+ 8888 009e 1BD0     		beq	.L570
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8889              		.loc 1 802 7 discriminator 14 view .LVU2882
+ 8890 00a0 94F84330 		ldrb	r3, [r4, #67]	@ zero_extendqisi2
+ 8891 00a4 DBB2     		uxtb	r3, r3
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8892              		.loc 1 802 44 discriminator 14 view .LVU2883
+ 8893 00a6 013B     		subs	r3, r3, #1
+ 8894 00a8 18BF     		it	ne
+ 8895 00aa 0123     		movne	r3, #1
+ 8896 00ac B3E7     		b	.L549
+ 8897              	.L567:
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8898              		.loc 1 802 7 discriminator 4 view .LVU2884
+ 8899 00ae 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 8900 00b2 DBB2     		uxtb	r3, r3
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8901              		.loc 1 802 44 discriminator 4 view .LVU2885
+ 8902 00b4 013B     		subs	r3, r3, #1
+ 8903 00b6 18BF     		it	ne
+ 8904 00b8 0123     		movne	r3, #1
+ARM GAS  /tmp/ccPLZXyC.s 			page 335
+
+
+ 8905 00ba ACE7     		b	.L549
+ 8906              	.L568:
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8907              		.loc 1 802 7 discriminator 7 view .LVU2886
+ 8908 00bc 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 8909 00c0 DBB2     		uxtb	r3, r3
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8910              		.loc 1 802 44 discriminator 7 view .LVU2887
+ 8911 00c2 013B     		subs	r3, r3, #1
+ 8912 00c4 18BF     		it	ne
+ 8913 00c6 0123     		movne	r3, #1
+ 8914 00c8 A5E7     		b	.L549
+ 8915              	.L569:
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8916              		.loc 1 802 7 discriminator 10 view .LVU2888
+ 8917 00ca 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 8918 00ce DBB2     		uxtb	r3, r3
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8919              		.loc 1 802 44 discriminator 10 view .LVU2889
+ 8920 00d0 013B     		subs	r3, r3, #1
+ 8921 00d2 18BF     		it	ne
+ 8922 00d4 0123     		movne	r3, #1
+ 8923 00d6 9EE7     		b	.L549
+ 8924              	.L570:
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8925              		.loc 1 802 7 discriminator 13 view .LVU2890
+ 8926 00d8 94F84230 		ldrb	r3, [r4, #66]	@ zero_extendqisi2
+ 8927 00dc DBB2     		uxtb	r3, r3
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 8928              		.loc 1 802 44 discriminator 13 view .LVU2891
+ 8929 00de 013B     		subs	r3, r3, #1
+ 8930 00e0 18BF     		it	ne
+ 8931 00e2 0123     		movne	r3, #1
+ 8932 00e4 97E7     		b	.L549
+ 8933              	.L555:
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8934              		.loc 1 808 3 discriminator 2 view .LVU2892
+ 8935 00e6 0428     		cmp	r0, #4
+ 8936 00e8 09D0     		beq	.L571
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8937              		.loc 1 808 3 discriminator 4 view .LVU2893
+ 8938 00ea 0828     		cmp	r0, #8
+ 8939 00ec 0BD0     		beq	.L572
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8940              		.loc 1 808 3 discriminator 7 view .LVU2894
+ 8941 00ee 0C28     		cmp	r0, #12
+ 8942 00f0 0DD0     		beq	.L573
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8943              		.loc 1 808 3 discriminator 10 view .LVU2895
+ 8944 00f2 1028     		cmp	r0, #16
+ 8945 00f4 0FD0     		beq	.L574
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8946              		.loc 1 808 3 discriminator 13 view .LVU2896
+ 8947 00f6 0223     		movs	r3, #2
+ 8948 00f8 84F84330 		strb	r3, [r4, #67]
+ 8949 00fc 93E7     		b	.L556
+ 8950              	.L571:
+ARM GAS  /tmp/ccPLZXyC.s 			page 336
+
+
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8951              		.loc 1 808 3 discriminator 3 view .LVU2897
+ 8952 00fe 0223     		movs	r3, #2
+ 8953 0100 84F83F30 		strb	r3, [r4, #63]
+ 8954 0104 8FE7     		b	.L556
+ 8955              	.L572:
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8956              		.loc 1 808 3 discriminator 6 view .LVU2898
+ 8957 0106 0223     		movs	r3, #2
+ 8958 0108 84F84030 		strb	r3, [r4, #64]
+ 8959 010c 8BE7     		b	.L556
+ 8960              	.L573:
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8961              		.loc 1 808 3 discriminator 9 view .LVU2899
+ 8962 010e 0223     		movs	r3, #2
+ 8963 0110 84F84130 		strb	r3, [r4, #65]
+ 8964 0114 87E7     		b	.L556
+ 8965              	.L574:
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 8966              		.loc 1 808 3 discriminator 12 view .LVU2900
+ 8967 0116 0223     		movs	r3, #2
+ 8968 0118 84F84230 		strb	r3, [r4, #66]
+ 8969 011c 83E7     		b	.L556
+ 8970              	.LVL725:
+ 8971              	.L562:
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 8972              		.loc 1 822 5 is_stmt 1 view .LVU2901
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 8973              		.loc 1 822 29 is_stmt 0 view .LVU2902
+ 8974 011e 9968     		ldr	r1, [r3, #8]
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 8975              		.loc 1 822 13 view .LVU2903
+ 8976 0120 0A4A     		ldr	r2, .L575+8
+ 8977 0122 0A40     		ands	r2, r2, r1
+ 8978              	.LVL726:
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 8979              		.loc 1 823 5 is_stmt 1 view .LVU2904
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 8980              		.loc 1 823 8 is_stmt 0 view .LVU2905
+ 8981 0124 062A     		cmp	r2, #6
+ 8982 0126 18BF     		it	ne
+ 8983 0128 B2F5803F 		cmpne	r2, #65536
+ 8984 012c 07D0     		beq	.L565
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8985              		.loc 1 825 7 is_stmt 1 view .LVU2906
+ 8986 012e 1A68     		ldr	r2, [r3]
+ 8987              	.LVL727:
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 8988              		.loc 1 825 7 is_stmt 0 view .LVU2907
+ 8989 0130 42F00102 		orr	r2, r2, #1
+ 8990 0134 1A60     		str	r2, [r3]
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 8991              		.loc 1 834 10 view .LVU2908
+ 8992 0136 0020     		movs	r0, #0
+ 8993 0138 00E0     		b	.L554
+ 8994              	.LVL728:
+ 8995              	.L564:
+ARM GAS  /tmp/ccPLZXyC.s 			page 337
+
+
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 8996              		.loc 1 804 12 view .LVU2909
+ 8997 013a 0120     		movs	r0, #1
+ 8998              	.LVL729:
+ 8999              	.L554:
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9000              		.loc 1 835 1 view .LVU2910
+ 9001 013c 10BD     		pop	{r4, pc}
+ 9002              	.LVL730:
+ 9003              	.L565:
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 9004              		.loc 1 834 10 view .LVU2911
+ 9005 013e 0020     		movs	r0, #0
+ 9006 0140 FCE7     		b	.L554
+ 9007              	.L576:
+ 9008 0142 00BF     		.align	2
+ 9009              	.L575:
+ 9010 0144 00000140 		.word	1073807360
+ 9011 0148 00040140 		.word	1073808384
+ 9012 014c 07000100 		.word	65543
+ 9013              		.cfi_endproc
+ 9014              	.LFE155:
+ 9016              		.section	.text.HAL_TIM_OC_Stop,"ax",%progbits
+ 9017              		.align	1
+ 9018              		.global	HAL_TIM_OC_Stop
+ 9019              		.syntax unified
+ 9020              		.thumb
+ 9021              		.thumb_func
+ 9022              		.fpu fpv5-d16
+ 9024              	HAL_TIM_OC_Stop:
+ 9025              	.LVL731:
+ 9026              	.LFB156:
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 9027              		.loc 1 851 1 is_stmt 1 view -0
+ 9028              		.cfi_startproc
+ 9029              		@ args = 0, pretend = 0, frame = 0
+ 9030              		@ frame_needed = 0, uses_anonymous_args = 0
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 9031              		.loc 1 851 1 is_stmt 0 view .LVU2913
+ 9032 0000 38B5     		push	{r3, r4, r5, lr}
+ 9033              	.LCFI87:
+ 9034              		.cfi_def_cfa_offset 16
+ 9035              		.cfi_offset 3, -16
+ 9036              		.cfi_offset 4, -12
+ 9037              		.cfi_offset 5, -8
+ 9038              		.cfi_offset 14, -4
+ 9039 0002 0446     		mov	r4, r0
+ 9040 0004 0D46     		mov	r5, r1
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9041              		.loc 1 853 3 is_stmt 1 view .LVU2914
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9042              		.loc 1 856 3 view .LVU2915
+ 9043 0006 0022     		movs	r2, #0
+ 9044 0008 0068     		ldr	r0, [r0]
+ 9045              	.LVL732:
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9046              		.loc 1 856 3 is_stmt 0 view .LVU2916
+ARM GAS  /tmp/ccPLZXyC.s 			page 338
+
+
+ 9047 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 9048              	.LVL733:
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9049              		.loc 1 858 3 is_stmt 1 view .LVU2917
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9050              		.loc 1 858 7 is_stmt 0 view .LVU2918
+ 9051 000e 2368     		ldr	r3, [r4]
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9052              		.loc 1 858 6 view .LVU2919
+ 9053 0010 2249     		ldr	r1, .L591
+ 9054 0012 234A     		ldr	r2, .L591+4
+ 9055 0014 9342     		cmp	r3, r2
+ 9056 0016 18BF     		it	ne
+ 9057 0018 8B42     		cmpne	r3, r1
+ 9058 001a 0DD1     		bne	.L578
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9059              		.loc 1 861 5 is_stmt 1 view .LVU2920
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9060              		.loc 1 861 5 view .LVU2921
+ 9061 001c 196A     		ldr	r1, [r3, #32]
+ 9062 001e 41F21112 		movw	r2, #4369
+ 9063 0022 1142     		tst	r1, r2
+ 9064 0024 08D1     		bne	.L578
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9065              		.loc 1 861 5 discriminator 1 view .LVU2922
+ 9066 0026 196A     		ldr	r1, [r3, #32]
+ 9067 0028 40F24442 		movw	r2, #1092
+ 9068 002c 1142     		tst	r1, r2
+ 9069 002e 03D1     		bne	.L578
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9070              		.loc 1 861 5 discriminator 3 view .LVU2923
+ 9071 0030 5A6C     		ldr	r2, [r3, #68]
+ 9072 0032 22F40042 		bic	r2, r2, #32768
+ 9073 0036 5A64     		str	r2, [r3, #68]
+ 9074              	.L578:
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9075              		.loc 1 861 5 discriminator 5 view .LVU2924
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9076              		.loc 1 865 3 discriminator 5 view .LVU2925
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9077              		.loc 1 865 3 discriminator 5 view .LVU2926
+ 9078 0038 2368     		ldr	r3, [r4]
+ 9079 003a 196A     		ldr	r1, [r3, #32]
+ 9080 003c 41F21112 		movw	r2, #4369
+ 9081 0040 1142     		tst	r1, r2
+ 9082 0042 08D1     		bne	.L579
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9083              		.loc 1 865 3 discriminator 1 view .LVU2927
+ 9084 0044 196A     		ldr	r1, [r3, #32]
+ 9085 0046 40F24442 		movw	r2, #1092
+ 9086 004a 1142     		tst	r1, r2
+ 9087 004c 03D1     		bne	.L579
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9088              		.loc 1 865 3 discriminator 3 view .LVU2928
+ 9089 004e 1A68     		ldr	r2, [r3]
+ 9090 0050 22F00102 		bic	r2, r2, #1
+ 9091 0054 1A60     		str	r2, [r3]
+ARM GAS  /tmp/ccPLZXyC.s 			page 339
+
+
+ 9092              	.L579:
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9093              		.loc 1 865 3 discriminator 5 view .LVU2929
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9094              		.loc 1 868 3 discriminator 5 view .LVU2930
+ 9095 0056 25B9     		cbnz	r5, .L580
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9096              		.loc 1 868 3 is_stmt 0 discriminator 1 view .LVU2931
+ 9097 0058 0123     		movs	r3, #1
+ 9098 005a 84F83E30 		strb	r3, [r4, #62]
+ 9099              	.L581:
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 9100              		.loc 1 871 3 is_stmt 1 view .LVU2932
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9101              		.loc 1 872 1 is_stmt 0 view .LVU2933
+ 9102 005e 0020     		movs	r0, #0
+ 9103 0060 38BD     		pop	{r3, r4, r5, pc}
+ 9104              	.LVL734:
+ 9105              	.L580:
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9106              		.loc 1 868 3 discriminator 2 view .LVU2934
+ 9107 0062 042D     		cmp	r5, #4
+ 9108 0064 09D0     		beq	.L587
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9109              		.loc 1 868 3 discriminator 4 view .LVU2935
+ 9110 0066 082D     		cmp	r5, #8
+ 9111 0068 0BD0     		beq	.L588
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9112              		.loc 1 868 3 discriminator 7 view .LVU2936
+ 9113 006a 0C2D     		cmp	r5, #12
+ 9114 006c 0DD0     		beq	.L589
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9115              		.loc 1 868 3 discriminator 10 view .LVU2937
+ 9116 006e 102D     		cmp	r5, #16
+ 9117 0070 0FD0     		beq	.L590
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9118              		.loc 1 868 3 discriminator 13 view .LVU2938
+ 9119 0072 0123     		movs	r3, #1
+ 9120 0074 84F84330 		strb	r3, [r4, #67]
+ 9121 0078 F1E7     		b	.L581
+ 9122              	.L587:
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9123              		.loc 1 868 3 discriminator 3 view .LVU2939
+ 9124 007a 0123     		movs	r3, #1
+ 9125 007c 84F83F30 		strb	r3, [r4, #63]
+ 9126 0080 EDE7     		b	.L581
+ 9127              	.L588:
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9128              		.loc 1 868 3 discriminator 6 view .LVU2940
+ 9129 0082 0123     		movs	r3, #1
+ 9130 0084 84F84030 		strb	r3, [r4, #64]
+ 9131 0088 E9E7     		b	.L581
+ 9132              	.L589:
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9133              		.loc 1 868 3 discriminator 9 view .LVU2941
+ 9134 008a 0123     		movs	r3, #1
+ 9135 008c 84F84130 		strb	r3, [r4, #65]
+ARM GAS  /tmp/ccPLZXyC.s 			page 340
+
+
+ 9136 0090 E5E7     		b	.L581
+ 9137              	.L590:
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9138              		.loc 1 868 3 discriminator 12 view .LVU2942
+ 9139 0092 0123     		movs	r3, #1
+ 9140 0094 84F84230 		strb	r3, [r4, #66]
+ 9141 0098 E1E7     		b	.L581
+ 9142              	.L592:
+ 9143 009a 00BF     		.align	2
+ 9144              	.L591:
+ 9145 009c 00000140 		.word	1073807360
+ 9146 00a0 00040140 		.word	1073808384
+ 9147              		.cfi_endproc
+ 9148              	.LFE156:
+ 9150              		.section	.text.HAL_TIM_OC_Start_IT,"ax",%progbits
+ 9151              		.align	1
+ 9152              		.global	HAL_TIM_OC_Start_IT
+ 9153              		.syntax unified
+ 9154              		.thumb
+ 9155              		.thumb_func
+ 9156              		.fpu fpv5-d16
+ 9158              	HAL_TIM_OC_Start_IT:
+ 9159              	.LVL735:
+ 9160              	.LFB157:
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 9161              		.loc 1 886 1 is_stmt 1 view -0
+ 9162              		.cfi_startproc
+ 9163              		@ args = 0, pretend = 0, frame = 0
+ 9164              		@ frame_needed = 0, uses_anonymous_args = 0
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 9165              		.loc 1 886 1 is_stmt 0 view .LVU2944
+ 9166 0000 10B5     		push	{r4, lr}
+ 9167              	.LCFI88:
+ 9168              		.cfi_def_cfa_offset 8
+ 9169              		.cfi_offset 4, -8
+ 9170              		.cfi_offset 14, -4
+ 9171 0002 0446     		mov	r4, r0
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 9172              		.loc 1 887 3 is_stmt 1 view .LVU2945
+ 9173              	.LVL736:
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9174              		.loc 1 888 3 view .LVU2946
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9175              		.loc 1 891 3 view .LVU2947
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9176              		.loc 1 894 3 view .LVU2948
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9177              		.loc 1 894 44 is_stmt 0 view .LVU2949
+ 9178 0004 0846     		mov	r0, r1
+ 9179              	.LVL737:
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9180              		.loc 1 894 44 view .LVU2950
+ 9181 0006 C9B9     		cbnz	r1, .L594
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9182              		.loc 1 894 7 discriminator 1 view .LVU2951
+ 9183 0008 94F83E30 		ldrb	r3, [r4, #62]	@ zero_extendqisi2
+ 9184 000c DBB2     		uxtb	r3, r3
+ARM GAS  /tmp/ccPLZXyC.s 			page 341
+
+
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9185              		.loc 1 894 44 discriminator 1 view .LVU2952
+ 9186 000e 013B     		subs	r3, r3, #1
+ 9187 0010 18BF     		it	ne
+ 9188 0012 0123     		movne	r3, #1
+ 9189              	.L595:
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9190              		.loc 1 894 6 discriminator 20 view .LVU2953
+ 9191 0014 002B     		cmp	r3, #0
+ 9192 0016 40F0B280 		bne	.L616
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9193              		.loc 1 900 3 is_stmt 1 view .LVU2954
+ 9194 001a 0028     		cmp	r0, #0
+ 9195 001c 39D1     		bne	.L601
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9196              		.loc 1 900 3 is_stmt 0 discriminator 1 view .LVU2955
+ 9197 001e 0223     		movs	r3, #2
+ 9198 0020 84F83E30 		strb	r3, [r4, #62]
+ 9199              	.L602:
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9200              		.loc 1 902 3 is_stmt 1 view .LVU2956
+ 9201 0024 0C28     		cmp	r0, #12
+ 9202 0026 00F2AC80 		bhi	.L617
+ 9203 002a DFE800F0 		tbb	[pc, r0]
+ 9204              	.L608:
+ 9205 002e 4E       		.byte	(.L611-.L608)/2
+ 9206 002f AA       		.byte	(.L617-.L608)/2
+ 9207 0030 AA       		.byte	(.L617-.L608)/2
+ 9208 0031 AA       		.byte	(.L617-.L608)/2
+ 9209 0032 88       		.byte	(.L610-.L608)/2
+ 9210 0033 AA       		.byte	(.L617-.L608)/2
+ 9211 0034 AA       		.byte	(.L617-.L608)/2
+ 9212 0035 AA       		.byte	(.L617-.L608)/2
+ 9213 0036 8E       		.byte	(.L609-.L608)/2
+ 9214 0037 AA       		.byte	(.L617-.L608)/2
+ 9215 0038 AA       		.byte	(.L617-.L608)/2
+ 9216 0039 AA       		.byte	(.L617-.L608)/2
+ 9217 003a 94       		.byte	(.L607-.L608)/2
+ 9218 003b 00       		.p2align 1
+ 9219              	.L594:
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9220              		.loc 1 894 44 is_stmt 0 discriminator 2 view .LVU2957
+ 9221 003c 0429     		cmp	r1, #4
+ 9222 003e 0CD0     		beq	.L620
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9223              		.loc 1 894 44 discriminator 5 view .LVU2958
+ 9224 0040 0829     		cmp	r1, #8
+ 9225 0042 11D0     		beq	.L621
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9226              		.loc 1 894 44 discriminator 8 view .LVU2959
+ 9227 0044 0C29     		cmp	r1, #12
+ 9228 0046 16D0     		beq	.L622
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9229              		.loc 1 894 44 discriminator 11 view .LVU2960
+ 9230 0048 1029     		cmp	r1, #16
+ 9231 004a 1BD0     		beq	.L623
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 342
+
+
+ 9232              		.loc 1 894 7 discriminator 14 view .LVU2961
+ 9233 004c 94F84330 		ldrb	r3, [r4, #67]	@ zero_extendqisi2
+ 9234 0050 DBB2     		uxtb	r3, r3
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9235              		.loc 1 894 44 discriminator 14 view .LVU2962
+ 9236 0052 013B     		subs	r3, r3, #1
+ 9237 0054 18BF     		it	ne
+ 9238 0056 0123     		movne	r3, #1
+ 9239 0058 DCE7     		b	.L595
+ 9240              	.L620:
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9241              		.loc 1 894 7 discriminator 4 view .LVU2963
+ 9242 005a 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 9243 005e DBB2     		uxtb	r3, r3
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9244              		.loc 1 894 44 discriminator 4 view .LVU2964
+ 9245 0060 013B     		subs	r3, r3, #1
+ 9246 0062 18BF     		it	ne
+ 9247 0064 0123     		movne	r3, #1
+ 9248 0066 D5E7     		b	.L595
+ 9249              	.L621:
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9250              		.loc 1 894 7 discriminator 7 view .LVU2965
+ 9251 0068 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 9252 006c DBB2     		uxtb	r3, r3
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9253              		.loc 1 894 44 discriminator 7 view .LVU2966
+ 9254 006e 013B     		subs	r3, r3, #1
+ 9255 0070 18BF     		it	ne
+ 9256 0072 0123     		movne	r3, #1
+ 9257 0074 CEE7     		b	.L595
+ 9258              	.L622:
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9259              		.loc 1 894 7 discriminator 10 view .LVU2967
+ 9260 0076 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 9261 007a DBB2     		uxtb	r3, r3
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9262              		.loc 1 894 44 discriminator 10 view .LVU2968
+ 9263 007c 013B     		subs	r3, r3, #1
+ 9264 007e 18BF     		it	ne
+ 9265 0080 0123     		movne	r3, #1
+ 9266 0082 C7E7     		b	.L595
+ 9267              	.L623:
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9268              		.loc 1 894 7 discriminator 13 view .LVU2969
+ 9269 0084 94F84230 		ldrb	r3, [r4, #66]	@ zero_extendqisi2
+ 9270 0088 DBB2     		uxtb	r3, r3
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9271              		.loc 1 894 44 discriminator 13 view .LVU2970
+ 9272 008a 013B     		subs	r3, r3, #1
+ 9273 008c 18BF     		it	ne
+ 9274 008e 0123     		movne	r3, #1
+ 9275 0090 C0E7     		b	.L595
+ 9276              	.LVL738:
+ 9277              	.L601:
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9278              		.loc 1 900 3 discriminator 2 view .LVU2971
+ARM GAS  /tmp/ccPLZXyC.s 			page 343
+
+
+ 9279 0092 0428     		cmp	r0, #4
+ 9280 0094 09D0     		beq	.L624
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9281              		.loc 1 900 3 discriminator 4 view .LVU2972
+ 9282 0096 0828     		cmp	r0, #8
+ 9283 0098 0BD0     		beq	.L625
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9284              		.loc 1 900 3 discriminator 7 view .LVU2973
+ 9285 009a 0C28     		cmp	r0, #12
+ 9286 009c 0DD0     		beq	.L626
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9287              		.loc 1 900 3 discriminator 10 view .LVU2974
+ 9288 009e 1028     		cmp	r0, #16
+ 9289 00a0 0FD0     		beq	.L627
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9290              		.loc 1 900 3 discriminator 13 view .LVU2975
+ 9291 00a2 0223     		movs	r3, #2
+ 9292 00a4 84F84330 		strb	r3, [r4, #67]
+ 9293 00a8 BCE7     		b	.L602
+ 9294              	.L624:
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9295              		.loc 1 900 3 discriminator 3 view .LVU2976
+ 9296 00aa 0223     		movs	r3, #2
+ 9297 00ac 84F83F30 		strb	r3, [r4, #63]
+ 9298 00b0 B8E7     		b	.L602
+ 9299              	.L625:
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9300              		.loc 1 900 3 discriminator 6 view .LVU2977
+ 9301 00b2 0223     		movs	r3, #2
+ 9302 00b4 84F84030 		strb	r3, [r4, #64]
+ 9303 00b8 B4E7     		b	.L602
+ 9304              	.L626:
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9305              		.loc 1 900 3 discriminator 9 view .LVU2978
+ 9306 00ba 0223     		movs	r3, #2
+ 9307 00bc 84F84130 		strb	r3, [r4, #65]
+ 9308 00c0 B0E7     		b	.L602
+ 9309              	.L627:
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9310              		.loc 1 900 3 discriminator 12 view .LVU2979
+ 9311 00c2 0223     		movs	r3, #2
+ 9312 00c4 84F84230 		strb	r3, [r4, #66]
+ 9313 00c8 ACE7     		b	.L602
+ 9314              	.L611:
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 9315              		.loc 1 907 7 is_stmt 1 view .LVU2980
+ 9316 00ca 2268     		ldr	r2, [r4]
+ 9317 00cc D368     		ldr	r3, [r2, #12]
+ 9318 00ce 43F00203 		orr	r3, r3, #2
+ 9319 00d2 D360     		str	r3, [r2, #12]
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9320              		.loc 1 908 7 view .LVU2981
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9321              		.loc 1 937 3 view .LVU2982
+ 9322              	.L612:
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9323              		.loc 1 940 5 view .LVU2983
+ARM GAS  /tmp/ccPLZXyC.s 			page 344
+
+
+ 9324 00d4 0122     		movs	r2, #1
+ 9325 00d6 0146     		mov	r1, r0
+ 9326 00d8 2068     		ldr	r0, [r4]
+ 9327              	.LVL739:
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9328              		.loc 1 940 5 is_stmt 0 view .LVU2984
+ 9329 00da FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 9330              	.LVL740:
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9331              		.loc 1 942 5 is_stmt 1 view .LVU2985
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9332              		.loc 1 942 9 is_stmt 0 view .LVU2986
+ 9333 00de 2368     		ldr	r3, [r4]
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9334              		.loc 1 942 8 view .LVU2987
+ 9335 00e0 2A49     		ldr	r1, .L628
+ 9336 00e2 2B4A     		ldr	r2, .L628+4
+ 9337 00e4 9342     		cmp	r3, r2
+ 9338 00e6 18BF     		it	ne
+ 9339 00e8 8B42     		cmpne	r3, r1
+ 9340 00ea 03D1     		bne	.L613
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9341              		.loc 1 945 7 is_stmt 1 view .LVU2988
+ 9342 00ec 5A6C     		ldr	r2, [r3, #68]
+ 9343 00ee 42F40042 		orr	r2, r2, #32768
+ 9344 00f2 5A64     		str	r2, [r3, #68]
+ 9345              	.L613:
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9346              		.loc 1 949 5 view .LVU2989
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9347              		.loc 1 949 9 is_stmt 0 view .LVU2990
+ 9348 00f4 2368     		ldr	r3, [r4]
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9349              		.loc 1 949 8 view .LVU2991
+ 9350 00f6 254A     		ldr	r2, .L628
+ 9351 00f8 B3F1804F 		cmp	r3, #1073741824
+ 9352 00fc 18BF     		it	ne
+ 9353 00fe 9342     		cmpne	r3, r2
+ 9354 0100 2FD0     		beq	.L614
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9355              		.loc 1 949 9 discriminator 1 view .LVU2992
+ 9356 0102 A2F57C42 		sub	r2, r2, #64512
+ 9357 0106 9342     		cmp	r3, r2
+ 9358 0108 2BD0     		beq	.L614
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9359              		.loc 1 949 9 discriminator 2 view .LVU2993
+ 9360 010a 02F58062 		add	r2, r2, #1024
+ 9361 010e 9342     		cmp	r3, r2
+ 9362 0110 27D0     		beq	.L614
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9363              		.loc 1 949 9 discriminator 3 view .LVU2994
+ 9364 0112 02F58062 		add	r2, r2, #1024
+ 9365 0116 9342     		cmp	r3, r2
+ 9366 0118 23D0     		beq	.L614
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9367              		.loc 1 949 9 discriminator 4 view .LVU2995
+ 9368 011a 02F57842 		add	r2, r2, #63488
+ARM GAS  /tmp/ccPLZXyC.s 			page 345
+
+
+ 9369 011e 9342     		cmp	r3, r2
+ 9370 0120 1FD0     		beq	.L614
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9371              		.loc 1 949 9 discriminator 5 view .LVU2996
+ 9372 0122 02F57052 		add	r2, r2, #15360
+ 9373 0126 9342     		cmp	r3, r2
+ 9374 0128 1BD0     		beq	.L614
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9375              		.loc 1 949 9 discriminator 6 view .LVU2997
+ 9376 012a A2F59432 		sub	r2, r2, #75776
+ 9377 012e 9342     		cmp	r3, r2
+ 9378 0130 17D0     		beq	.L614
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9379              		.loc 1 959 7 is_stmt 1 view .LVU2998
+ 9380 0132 1A68     		ldr	r2, [r3]
+ 9381 0134 42F00102 		orr	r2, r2, #1
+ 9382 0138 1A60     		str	r2, [r3]
+ 9383 013a 0020     		movs	r0, #0
+ 9384 013c 22E0     		b	.L600
+ 9385              	.LVL741:
+ 9386              	.L610:
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 9387              		.loc 1 914 7 view .LVU2999
+ 9388 013e 2268     		ldr	r2, [r4]
+ 9389 0140 D368     		ldr	r3, [r2, #12]
+ 9390 0142 43F00403 		orr	r3, r3, #4
+ 9391 0146 D360     		str	r3, [r2, #12]
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9392              		.loc 1 915 7 view .LVU3000
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9393              		.loc 1 937 3 view .LVU3001
+ 9394 0148 C4E7     		b	.L612
+ 9395              	.L609:
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 9396              		.loc 1 921 7 view .LVU3002
+ 9397 014a 2268     		ldr	r2, [r4]
+ 9398 014c D368     		ldr	r3, [r2, #12]
+ 9399 014e 43F00803 		orr	r3, r3, #8
+ 9400 0152 D360     		str	r3, [r2, #12]
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9401              		.loc 1 922 7 view .LVU3003
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9402              		.loc 1 937 3 view .LVU3004
+ 9403 0154 BEE7     		b	.L612
+ 9404              	.L607:
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 9405              		.loc 1 928 7 view .LVU3005
+ 9406 0156 2268     		ldr	r2, [r4]
+ 9407 0158 D368     		ldr	r3, [r2, #12]
+ 9408 015a 43F01003 		orr	r3, r3, #16
+ 9409 015e D360     		str	r3, [r2, #12]
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9410              		.loc 1 929 7 view .LVU3006
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9411              		.loc 1 937 3 view .LVU3007
+ 9412 0160 B8E7     		b	.L612
+ 9413              	.LVL742:
+ARM GAS  /tmp/ccPLZXyC.s 			page 346
+
+
+ 9414              	.L614:
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 9415              		.loc 1 951 7 view .LVU3008
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 9416              		.loc 1 951 31 is_stmt 0 view .LVU3009
+ 9417 0162 9968     		ldr	r1, [r3, #8]
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 9418              		.loc 1 951 15 view .LVU3010
+ 9419 0164 0B4A     		ldr	r2, .L628+8
+ 9420 0166 0A40     		ands	r2, r2, r1
+ 9421              	.LVL743:
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 9422              		.loc 1 952 7 is_stmt 1 view .LVU3011
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 9423              		.loc 1 952 10 is_stmt 0 view .LVU3012
+ 9424 0168 062A     		cmp	r2, #6
+ 9425 016a 18BF     		it	ne
+ 9426 016c B2F5803F 		cmpne	r2, #65536
+ 9427 0170 09D0     		beq	.L618
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 9428              		.loc 1 954 9 is_stmt 1 view .LVU3013
+ 9429 0172 1A68     		ldr	r2, [r3]
+ 9430              	.LVL744:
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 9431              		.loc 1 954 9 is_stmt 0 view .LVU3014
+ 9432 0174 42F00102 		orr	r2, r2, #1
+ 9433 0178 1A60     		str	r2, [r3]
+ 9434 017a 0020     		movs	r0, #0
+ 9435 017c 02E0     		b	.L600
+ 9436              	.LVL745:
+ 9437              	.L616:
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9438              		.loc 1 896 12 view .LVU3015
+ 9439 017e 0120     		movs	r0, #1
+ 9440              	.LVL746:
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9441              		.loc 1 896 12 view .LVU3016
+ 9442 0180 00E0     		b	.L600
+ 9443              	.LVL747:
+ 9444              	.L617:
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9445              		.loc 1 902 3 view .LVU3017
+ 9446 0182 0120     		movs	r0, #1
+ 9447              	.LVL748:
+ 9448              	.L600:
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9449              		.loc 1 965 1 view .LVU3018
+ 9450 0184 10BD     		pop	{r4, pc}
+ 9451              	.LVL749:
+ 9452              	.L618:
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9453              		.loc 1 965 1 view .LVU3019
+ 9454 0186 0020     		movs	r0, #0
+ 9455 0188 FCE7     		b	.L600
+ 9456              	.L629:
+ 9457 018a 00BF     		.align	2
+ 9458              	.L628:
+ARM GAS  /tmp/ccPLZXyC.s 			page 347
+
+
+ 9459 018c 00000140 		.word	1073807360
+ 9460 0190 00040140 		.word	1073808384
+ 9461 0194 07000100 		.word	65543
+ 9462              		.cfi_endproc
+ 9463              	.LFE157:
+ 9465              		.section	.text.HAL_TIM_OC_Stop_IT,"ax",%progbits
+ 9466              		.align	1
+ 9467              		.global	HAL_TIM_OC_Stop_IT
+ 9468              		.syntax unified
+ 9469              		.thumb
+ 9470              		.thumb_func
+ 9471              		.fpu fpv5-d16
+ 9473              	HAL_TIM_OC_Stop_IT:
+ 9474              	.LVL750:
+ 9475              	.LFB158:
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 9476              		.loc 1 979 1 is_stmt 1 view -0
+ 9477              		.cfi_startproc
+ 9478              		@ args = 0, pretend = 0, frame = 0
+ 9479              		@ frame_needed = 0, uses_anonymous_args = 0
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 9480              		.loc 1 979 1 is_stmt 0 view .LVU3021
+ 9481 0000 38B5     		push	{r3, r4, r5, lr}
+ 9482              	.LCFI89:
+ 9483              		.cfi_def_cfa_offset 16
+ 9484              		.cfi_offset 3, -16
+ 9485              		.cfi_offset 4, -12
+ 9486              		.cfi_offset 5, -8
+ 9487              		.cfi_offset 14, -4
+ 9488 0002 0546     		mov	r5, r0
+ 9489 0004 0C46     		mov	r4, r1
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9490              		.loc 1 980 3 is_stmt 1 view .LVU3022
+ 9491              	.LVL751:
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9492              		.loc 1 983 3 view .LVU3023
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9493              		.loc 1 985 3 view .LVU3024
+ 9494 0006 0C29     		cmp	r1, #12
+ 9495 0008 6FD8     		bhi	.L645
+ 9496 000a DFE801F0 		tbb	[pc, r1]
+ 9497              	.L633:
+ 9498 000e 07       		.byte	(.L636-.L633)/2
+ 9499 000f 6E       		.byte	(.L645-.L633)/2
+ 9500 0010 6E       		.byte	(.L645-.L633)/2
+ 9501 0011 6E       		.byte	(.L645-.L633)/2
+ 9502 0012 3B       		.byte	(.L635-.L633)/2
+ 9503 0013 6E       		.byte	(.L645-.L633)/2
+ 9504 0014 6E       		.byte	(.L645-.L633)/2
+ 9505 0015 6E       		.byte	(.L645-.L633)/2
+ 9506 0016 41       		.byte	(.L634-.L633)/2
+ 9507 0017 6E       		.byte	(.L645-.L633)/2
+ 9508 0018 6E       		.byte	(.L645-.L633)/2
+ 9509 0019 6E       		.byte	(.L645-.L633)/2
+ 9510 001a 47       		.byte	(.L632-.L633)/2
+ 9511 001b 00       		.p2align 1
+ 9512              	.L636:
+ARM GAS  /tmp/ccPLZXyC.s 			page 348
+
+
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 9513              		.loc 1 990 7 view .LVU3025
+ 9514 001c 0268     		ldr	r2, [r0]
+ 9515 001e D368     		ldr	r3, [r2, #12]
+ 9516 0020 23F00203 		bic	r3, r3, #2
+ 9517 0024 D360     		str	r3, [r2, #12]
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9518              		.loc 1 991 7 view .LVU3026
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9519              		.loc 1 1020 3 view .LVU3027
+ 9520              	.L637:
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9521              		.loc 1 1023 5 view .LVU3028
+ 9522 0026 0022     		movs	r2, #0
+ 9523 0028 2146     		mov	r1, r4
+ 9524              	.LVL752:
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9525              		.loc 1 1023 5 is_stmt 0 view .LVU3029
+ 9526 002a 2868     		ldr	r0, [r5]
+ 9527              	.LVL753:
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9528              		.loc 1 1023 5 view .LVU3030
+ 9529 002c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 9530              	.LVL754:
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9531              		.loc 1 1025 5 is_stmt 1 view .LVU3031
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9532              		.loc 1 1025 9 is_stmt 0 view .LVU3032
+ 9533 0030 2B68     		ldr	r3, [r5]
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9534              		.loc 1 1025 8 view .LVU3033
+ 9535 0032 2F49     		ldr	r1, .L651
+ 9536 0034 2F4A     		ldr	r2, .L651+4
+ 9537 0036 9342     		cmp	r3, r2
+ 9538 0038 18BF     		it	ne
+ 9539 003a 8B42     		cmpne	r3, r1
+ 9540 003c 0DD1     		bne	.L638
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9541              		.loc 1 1028 7 is_stmt 1 view .LVU3034
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9542              		.loc 1 1028 7 view .LVU3035
+ 9543 003e 196A     		ldr	r1, [r3, #32]
+ 9544 0040 41F21112 		movw	r2, #4369
+ 9545 0044 1142     		tst	r1, r2
+ 9546 0046 08D1     		bne	.L638
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9547              		.loc 1 1028 7 discriminator 1 view .LVU3036
+ 9548 0048 196A     		ldr	r1, [r3, #32]
+ 9549 004a 40F24442 		movw	r2, #1092
+ 9550 004e 1142     		tst	r1, r2
+ 9551 0050 03D1     		bne	.L638
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9552              		.loc 1 1028 7 discriminator 3 view .LVU3037
+ 9553 0052 5A6C     		ldr	r2, [r3, #68]
+ 9554 0054 22F40042 		bic	r2, r2, #32768
+ 9555 0058 5A64     		str	r2, [r3, #68]
+ 9556              	.L638:
+ARM GAS  /tmp/ccPLZXyC.s 			page 349
+
+
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9557              		.loc 1 1028 7 discriminator 5 view .LVU3038
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9558              		.loc 1 1032 5 discriminator 5 view .LVU3039
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9559              		.loc 1 1032 5 discriminator 5 view .LVU3040
+ 9560 005a 2B68     		ldr	r3, [r5]
+ 9561 005c 196A     		ldr	r1, [r3, #32]
+ 9562 005e 41F21112 		movw	r2, #4369
+ 9563 0062 1142     		tst	r1, r2
+ 9564 0064 08D1     		bne	.L639
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9565              		.loc 1 1032 5 discriminator 1 view .LVU3041
+ 9566 0066 196A     		ldr	r1, [r3, #32]
+ 9567 0068 40F24442 		movw	r2, #1092
+ 9568 006c 1142     		tst	r1, r2
+ 9569 006e 03D1     		bne	.L639
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9570              		.loc 1 1032 5 discriminator 3 view .LVU3042
+ 9571 0070 1A68     		ldr	r2, [r3]
+ 9572 0072 22F00102 		bic	r2, r2, #1
+ 9573 0076 1A60     		str	r2, [r3]
+ 9574              	.L639:
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9575              		.loc 1 1032 5 discriminator 5 view .LVU3043
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9576              		.loc 1 1035 5 discriminator 5 view .LVU3044
+ 9577 0078 B4B9     		cbnz	r4, .L640
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9578              		.loc 1 1035 5 is_stmt 0 discriminator 1 view .LVU3045
+ 9579 007a 0123     		movs	r3, #1
+ 9580 007c 85F83E30 		strb	r3, [r5, #62]
+ 9581 0080 0020     		movs	r0, #0
+ 9582 0082 33E0     		b	.L631
+ 9583              	.LVL755:
+ 9584              	.L635:
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 9585              		.loc 1 997 7 is_stmt 1 view .LVU3046
+ 9586 0084 0268     		ldr	r2, [r0]
+ 9587 0086 D368     		ldr	r3, [r2, #12]
+ 9588 0088 23F00403 		bic	r3, r3, #4
+ 9589 008c D360     		str	r3, [r2, #12]
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9590              		.loc 1 998 7 view .LVU3047
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9591              		.loc 1 1020 3 view .LVU3048
+ 9592 008e CAE7     		b	.L637
+ 9593              	.L634:
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 9594              		.loc 1 1004 7 view .LVU3049
+ 9595 0090 0268     		ldr	r2, [r0]
+ 9596 0092 D368     		ldr	r3, [r2, #12]
+ 9597 0094 23F00803 		bic	r3, r3, #8
+ 9598 0098 D360     		str	r3, [r2, #12]
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9599              		.loc 1 1005 7 view .LVU3050
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 350
+
+
+ 9600              		.loc 1 1020 3 view .LVU3051
+ 9601 009a C4E7     		b	.L637
+ 9602              	.L632:
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 9603              		.loc 1 1011 7 view .LVU3052
+ 9604 009c 0268     		ldr	r2, [r0]
+ 9605 009e D368     		ldr	r3, [r2, #12]
+ 9606 00a0 23F01003 		bic	r3, r3, #16
+ 9607 00a4 D360     		str	r3, [r2, #12]
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9608              		.loc 1 1012 7 view .LVU3053
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9609              		.loc 1 1020 3 view .LVU3054
+ 9610 00a6 BEE7     		b	.L637
+ 9611              	.LVL756:
+ 9612              	.L640:
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9613              		.loc 1 1035 5 is_stmt 0 discriminator 2 view .LVU3055
+ 9614 00a8 042C     		cmp	r4, #4
+ 9615 00aa 0AD0     		beq	.L647
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9616              		.loc 1 1035 5 discriminator 4 view .LVU3056
+ 9617 00ac 082C     		cmp	r4, #8
+ 9618 00ae 0DD0     		beq	.L648
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9619              		.loc 1 1035 5 discriminator 7 view .LVU3057
+ 9620 00b0 0C2C     		cmp	r4, #12
+ 9621 00b2 10D0     		beq	.L649
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9622              		.loc 1 1035 5 discriminator 10 view .LVU3058
+ 9623 00b4 102C     		cmp	r4, #16
+ 9624 00b6 13D0     		beq	.L650
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9625              		.loc 1 1035 5 discriminator 13 view .LVU3059
+ 9626 00b8 0123     		movs	r3, #1
+ 9627 00ba 85F84330 		strb	r3, [r5, #67]
+ 9628 00be 0020     		movs	r0, #0
+ 9629 00c0 14E0     		b	.L631
+ 9630              	.L647:
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9631              		.loc 1 1035 5 discriminator 3 view .LVU3060
+ 9632 00c2 0123     		movs	r3, #1
+ 9633 00c4 85F83F30 		strb	r3, [r5, #63]
+ 9634 00c8 0020     		movs	r0, #0
+ 9635 00ca 0FE0     		b	.L631
+ 9636              	.L648:
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9637              		.loc 1 1035 5 discriminator 6 view .LVU3061
+ 9638 00cc 0123     		movs	r3, #1
+ 9639 00ce 85F84030 		strb	r3, [r5, #64]
+ 9640 00d2 0020     		movs	r0, #0
+ 9641 00d4 0AE0     		b	.L631
+ 9642              	.L649:
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9643              		.loc 1 1035 5 discriminator 9 view .LVU3062
+ 9644 00d6 0123     		movs	r3, #1
+ 9645 00d8 85F84130 		strb	r3, [r5, #65]
+ARM GAS  /tmp/ccPLZXyC.s 			page 351
+
+
+ 9646 00dc 0020     		movs	r0, #0
+ 9647 00de 05E0     		b	.L631
+ 9648              	.L650:
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 9649              		.loc 1 1035 5 discriminator 12 view .LVU3063
+ 9650 00e0 0123     		movs	r3, #1
+ 9651 00e2 85F84230 		strb	r3, [r5, #66]
+ 9652 00e6 0020     		movs	r0, #0
+ 9653 00e8 00E0     		b	.L631
+ 9654              	.LVL757:
+ 9655              	.L645:
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9656              		.loc 1 985 3 view .LVU3064
+ 9657 00ea 0120     		movs	r0, #1
+ 9658              	.LVL758:
+ 9659              	.L631:
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 9660              		.loc 1 1039 3 is_stmt 1 view .LVU3065
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9661              		.loc 1 1040 1 is_stmt 0 view .LVU3066
+ 9662 00ec 38BD     		pop	{r3, r4, r5, pc}
+ 9663              	.LVL759:
+ 9664              	.L652:
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9665              		.loc 1 1040 1 view .LVU3067
+ 9666 00ee 00BF     		.align	2
+ 9667              	.L651:
+ 9668 00f0 00000140 		.word	1073807360
+ 9669 00f4 00040140 		.word	1073808384
+ 9670              		.cfi_endproc
+ 9671              	.LFE158:
+ 9673              		.section	.text.HAL_TIM_OC_Start_DMA,"ax",%progbits
+ 9674              		.align	1
+ 9675              		.global	HAL_TIM_OC_Start_DMA
+ 9676              		.syntax unified
+ 9677              		.thumb
+ 9678              		.thumb_func
+ 9679              		.fpu fpv5-d16
+ 9681              	HAL_TIM_OC_Start_DMA:
+ 9682              	.LVL760:
+ 9683              	.LFB159:
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 9684              		.loc 1 1057 1 is_stmt 1 view -0
+ 9685              		.cfi_startproc
+ 9686              		@ args = 0, pretend = 0, frame = 0
+ 9687              		@ frame_needed = 0, uses_anonymous_args = 0
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 9688              		.loc 1 1057 1 is_stmt 0 view .LVU3069
+ 9689 0000 38B5     		push	{r3, r4, r5, lr}
+ 9690              	.LCFI90:
+ 9691              		.cfi_def_cfa_offset 16
+ 9692              		.cfi_offset 3, -16
+ 9693              		.cfi_offset 4, -12
+ 9694              		.cfi_offset 5, -8
+ 9695              		.cfi_offset 14, -4
+ 9696 0002 0446     		mov	r4, r0
+ 9697 0004 9446     		mov	ip, r2
+ARM GAS  /tmp/ccPLZXyC.s 			page 352
+
+
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 9698              		.loc 1 1058 3 is_stmt 1 view .LVU3070
+ 9699              	.LVL761:
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9700              		.loc 1 1059 3 view .LVU3071
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9701              		.loc 1 1062 3 view .LVU3072
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9702              		.loc 1 1065 3 view .LVU3073
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9703              		.loc 1 1065 44 is_stmt 0 view .LVU3074
+ 9704 0006 0D46     		mov	r5, r1
+ 9705 0008 0029     		cmp	r1, #0
+ 9706 000a 32D1     		bne	.L654
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9707              		.loc 1 1065 7 discriminator 1 view .LVU3075
+ 9708 000c 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 9709              	.LVL762:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9710              		.loc 1 1065 7 discriminator 1 view .LVU3076
+ 9711 0010 C0B2     		uxtb	r0, r0
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9712              		.loc 1 1065 44 discriminator 1 view .LVU3077
+ 9713 0012 0228     		cmp	r0, #2
+ 9714 0014 14BF     		ite	ne
+ 9715 0016 0020     		movne	r0, #0
+ 9716 0018 0120     		moveq	r0, #1
+ 9717              	.L655:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9718              		.loc 1 1065 6 discriminator 20 view .LVU3078
+ 9719 001a 0028     		cmp	r0, #0
+ 9720 001c 40F04381 		bne	.L682
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9721              		.loc 1 1069 8 is_stmt 1 view .LVU3079
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9722              		.loc 1 1069 49 is_stmt 0 view .LVU3080
+ 9723 0020 002D     		cmp	r5, #0
+ 9724 0022 56D1     		bne	.L661
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9725              		.loc 1 1069 12 discriminator 1 view .LVU3081
+ 9726 0024 94F83E20 		ldrb	r2, [r4, #62]	@ zero_extendqisi2
+ 9727              	.LVL763:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9728              		.loc 1 1069 12 discriminator 1 view .LVU3082
+ 9729 0028 D2B2     		uxtb	r2, r2
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9730              		.loc 1 1069 49 discriminator 1 view .LVU3083
+ 9731 002a 012A     		cmp	r2, #1
+ 9732 002c 14BF     		ite	ne
+ 9733 002e 0022     		movne	r2, #0
+ 9734 0030 0122     		moveq	r2, #1
+ 9735              	.L662:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9736              		.loc 1 1069 11 discriminator 20 view .LVU3084
+ 9737 0032 002A     		cmp	r2, #0
+ 9738 0034 00F03981 		beq	.L683
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ARM GAS  /tmp/ccPLZXyC.s 			page 353
+
+
+ 9739              		.loc 1 1071 5 is_stmt 1 view .LVU3085
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 9740              		.loc 1 1071 8 is_stmt 0 view .LVU3086
+ 9741 0038 002B     		cmp	r3, #0
+ 9742 003a 18BF     		it	ne
+ 9743 003c BCF1000F 		cmpne	ip, #0
+ 9744 0040 00F03581 		beq	.L684
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9745              		.loc 1 1077 7 is_stmt 1 view .LVU3087
+ 9746 0044 002D     		cmp	r5, #0
+ 9747 0046 74D1     		bne	.L667
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9748              		.loc 1 1077 7 is_stmt 0 discriminator 1 view .LVU3088
+ 9749 0048 0222     		movs	r2, #2
+ 9750 004a 84F83E20 		strb	r2, [r4, #62]
+ 9751              	.L668:
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9752              		.loc 1 1085 3 is_stmt 1 view .LVU3089
+ 9753 004e 0C2D     		cmp	r5, #12
+ 9754 0050 00F22F81 		bhi	.L685
+ 9755 0054 DFE815F0 		tbh	[pc, r5, lsl #1]
+ 9756              	.L674:
+ 9757 0058 8900     		.2byte	(.L677-.L674)/2
+ 9758 005a 2D01     		.2byte	(.L685-.L674)/2
+ 9759 005c 2D01     		.2byte	(.L685-.L674)/2
+ 9760 005e 2D01     		.2byte	(.L685-.L674)/2
+ 9761 0060 D500     		.2byte	(.L676-.L674)/2
+ 9762 0062 2D01     		.2byte	(.L685-.L674)/2
+ 9763 0064 2D01     		.2byte	(.L685-.L674)/2
+ 9764 0066 2D01     		.2byte	(.L685-.L674)/2
+ 9765 0068 EC00     		.2byte	(.L675-.L674)/2
+ 9766 006a 2D01     		.2byte	(.L685-.L674)/2
+ 9767 006c 2D01     		.2byte	(.L685-.L674)/2
+ 9768 006e 2D01     		.2byte	(.L685-.L674)/2
+ 9769 0070 0301     		.2byte	(.L673-.L674)/2
+ 9770              	.LVL764:
+ 9771              		.p2align 1
+ 9772              	.L654:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9773              		.loc 1 1065 44 is_stmt 0 discriminator 2 view .LVU3090
+ 9774 0072 0429     		cmp	r1, #4
+ 9775 0074 0DD0     		beq	.L692
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9776              		.loc 1 1065 44 discriminator 5 view .LVU3091
+ 9777 0076 0829     		cmp	r1, #8
+ 9778 0078 13D0     		beq	.L693
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9779              		.loc 1 1065 44 discriminator 8 view .LVU3092
+ 9780 007a 0C29     		cmp	r1, #12
+ 9781 007c 19D0     		beq	.L694
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9782              		.loc 1 1065 44 discriminator 11 view .LVU3093
+ 9783 007e 1029     		cmp	r1, #16
+ 9784 0080 1FD0     		beq	.L695
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9785              		.loc 1 1065 7 discriminator 14 view .LVU3094
+ 9786 0082 90F84300 		ldrb	r0, [r0, #67]	@ zero_extendqisi2
+ARM GAS  /tmp/ccPLZXyC.s 			page 354
+
+
+ 9787              	.LVL765:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9788              		.loc 1 1065 7 discriminator 14 view .LVU3095
+ 9789 0086 C0B2     		uxtb	r0, r0
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9790              		.loc 1 1065 44 discriminator 14 view .LVU3096
+ 9791 0088 0228     		cmp	r0, #2
+ 9792 008a 14BF     		ite	ne
+ 9793 008c 0020     		movne	r0, #0
+ 9794 008e 0120     		moveq	r0, #1
+ 9795 0090 C3E7     		b	.L655
+ 9796              	.LVL766:
+ 9797              	.L692:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9798              		.loc 1 1065 7 discriminator 4 view .LVU3097
+ 9799 0092 90F83F00 		ldrb	r0, [r0, #63]	@ zero_extendqisi2
+ 9800              	.LVL767:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9801              		.loc 1 1065 7 discriminator 4 view .LVU3098
+ 9802 0096 C0B2     		uxtb	r0, r0
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9803              		.loc 1 1065 44 discriminator 4 view .LVU3099
+ 9804 0098 0228     		cmp	r0, #2
+ 9805 009a 14BF     		ite	ne
+ 9806 009c 0020     		movne	r0, #0
+ 9807 009e 0120     		moveq	r0, #1
+ 9808 00a0 BBE7     		b	.L655
+ 9809              	.LVL768:
+ 9810              	.L693:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9811              		.loc 1 1065 7 discriminator 7 view .LVU3100
+ 9812 00a2 90F84000 		ldrb	r0, [r0, #64]	@ zero_extendqisi2
+ 9813              	.LVL769:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9814              		.loc 1 1065 7 discriminator 7 view .LVU3101
+ 9815 00a6 C0B2     		uxtb	r0, r0
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9816              		.loc 1 1065 44 discriminator 7 view .LVU3102
+ 9817 00a8 0228     		cmp	r0, #2
+ 9818 00aa 14BF     		ite	ne
+ 9819 00ac 0020     		movne	r0, #0
+ 9820 00ae 0120     		moveq	r0, #1
+ 9821 00b0 B3E7     		b	.L655
+ 9822              	.LVL770:
+ 9823              	.L694:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9824              		.loc 1 1065 7 discriminator 10 view .LVU3103
+ 9825 00b2 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 9826              	.LVL771:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9827              		.loc 1 1065 7 discriminator 10 view .LVU3104
+ 9828 00b6 C0B2     		uxtb	r0, r0
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9829              		.loc 1 1065 44 discriminator 10 view .LVU3105
+ 9830 00b8 0228     		cmp	r0, #2
+ 9831 00ba 14BF     		ite	ne
+ 9832 00bc 0020     		movne	r0, #0
+ARM GAS  /tmp/ccPLZXyC.s 			page 355
+
+
+ 9833 00be 0120     		moveq	r0, #1
+ 9834 00c0 ABE7     		b	.L655
+ 9835              	.LVL772:
+ 9836              	.L695:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9837              		.loc 1 1065 7 discriminator 13 view .LVU3106
+ 9838 00c2 90F84200 		ldrb	r0, [r0, #66]	@ zero_extendqisi2
+ 9839              	.LVL773:
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9840              		.loc 1 1065 7 discriminator 13 view .LVU3107
+ 9841 00c6 C0B2     		uxtb	r0, r0
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9842              		.loc 1 1065 44 discriminator 13 view .LVU3108
+ 9843 00c8 0228     		cmp	r0, #2
+ 9844 00ca 14BF     		ite	ne
+ 9845 00cc 0020     		movne	r0, #0
+ 9846 00ce 0120     		moveq	r0, #1
+ 9847 00d0 A3E7     		b	.L655
+ 9848              	.L661:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9849              		.loc 1 1069 49 discriminator 2 view .LVU3109
+ 9850 00d2 042D     		cmp	r5, #4
+ 9851 00d4 0DD0     		beq	.L696
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9852              		.loc 1 1069 49 discriminator 5 view .LVU3110
+ 9853 00d6 082D     		cmp	r5, #8
+ 9854 00d8 13D0     		beq	.L697
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9855              		.loc 1 1069 49 discriminator 8 view .LVU3111
+ 9856 00da 0C2D     		cmp	r5, #12
+ 9857 00dc 19D0     		beq	.L698
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9858              		.loc 1 1069 49 discriminator 11 view .LVU3112
+ 9859 00de 102D     		cmp	r5, #16
+ 9860 00e0 1FD0     		beq	.L699
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9861              		.loc 1 1069 12 discriminator 14 view .LVU3113
+ 9862 00e2 94F84320 		ldrb	r2, [r4, #67]	@ zero_extendqisi2
+ 9863              	.LVL774:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9864              		.loc 1 1069 12 discriminator 14 view .LVU3114
+ 9865 00e6 D2B2     		uxtb	r2, r2
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9866              		.loc 1 1069 49 discriminator 14 view .LVU3115
+ 9867 00e8 012A     		cmp	r2, #1
+ 9868 00ea 14BF     		ite	ne
+ 9869 00ec 0022     		movne	r2, #0
+ 9870 00ee 0122     		moveq	r2, #1
+ 9871 00f0 9FE7     		b	.L662
+ 9872              	.LVL775:
+ 9873              	.L696:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9874              		.loc 1 1069 12 discriminator 4 view .LVU3116
+ 9875 00f2 94F83F20 		ldrb	r2, [r4, #63]	@ zero_extendqisi2
+ 9876              	.LVL776:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9877              		.loc 1 1069 12 discriminator 4 view .LVU3117
+ARM GAS  /tmp/ccPLZXyC.s 			page 356
+
+
+ 9878 00f6 D2B2     		uxtb	r2, r2
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9879              		.loc 1 1069 49 discriminator 4 view .LVU3118
+ 9880 00f8 012A     		cmp	r2, #1
+ 9881 00fa 14BF     		ite	ne
+ 9882 00fc 0022     		movne	r2, #0
+ 9883 00fe 0122     		moveq	r2, #1
+ 9884 0100 97E7     		b	.L662
+ 9885              	.LVL777:
+ 9886              	.L697:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9887              		.loc 1 1069 12 discriminator 7 view .LVU3119
+ 9888 0102 94F84020 		ldrb	r2, [r4, #64]	@ zero_extendqisi2
+ 9889              	.LVL778:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9890              		.loc 1 1069 12 discriminator 7 view .LVU3120
+ 9891 0106 D2B2     		uxtb	r2, r2
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9892              		.loc 1 1069 49 discriminator 7 view .LVU3121
+ 9893 0108 012A     		cmp	r2, #1
+ 9894 010a 14BF     		ite	ne
+ 9895 010c 0022     		movne	r2, #0
+ 9896 010e 0122     		moveq	r2, #1
+ 9897 0110 8FE7     		b	.L662
+ 9898              	.LVL779:
+ 9899              	.L698:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9900              		.loc 1 1069 12 discriminator 10 view .LVU3122
+ 9901 0112 94F84120 		ldrb	r2, [r4, #65]	@ zero_extendqisi2
+ 9902              	.LVL780:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9903              		.loc 1 1069 12 discriminator 10 view .LVU3123
+ 9904 0116 D2B2     		uxtb	r2, r2
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9905              		.loc 1 1069 49 discriminator 10 view .LVU3124
+ 9906 0118 012A     		cmp	r2, #1
+ 9907 011a 14BF     		ite	ne
+ 9908 011c 0022     		movne	r2, #0
+ 9909 011e 0122     		moveq	r2, #1
+ 9910 0120 87E7     		b	.L662
+ 9911              	.LVL781:
+ 9912              	.L699:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9913              		.loc 1 1069 12 discriminator 13 view .LVU3125
+ 9914 0122 94F84220 		ldrb	r2, [r4, #66]	@ zero_extendqisi2
+ 9915              	.LVL782:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9916              		.loc 1 1069 12 discriminator 13 view .LVU3126
+ 9917 0126 D2B2     		uxtb	r2, r2
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 9918              		.loc 1 1069 49 discriminator 13 view .LVU3127
+ 9919 0128 012A     		cmp	r2, #1
+ 9920 012a 14BF     		ite	ne
+ 9921 012c 0022     		movne	r2, #0
+ 9922 012e 0122     		moveq	r2, #1
+ 9923 0130 7FE7     		b	.L662
+ 9924              	.L667:
+ARM GAS  /tmp/ccPLZXyC.s 			page 357
+
+
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9925              		.loc 1 1077 7 discriminator 2 view .LVU3128
+ 9926 0132 042D     		cmp	r5, #4
+ 9927 0134 09D0     		beq	.L700
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9928              		.loc 1 1077 7 discriminator 4 view .LVU3129
+ 9929 0136 082D     		cmp	r5, #8
+ 9930 0138 0BD0     		beq	.L701
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9931              		.loc 1 1077 7 discriminator 7 view .LVU3130
+ 9932 013a 0C2D     		cmp	r5, #12
+ 9933 013c 0DD0     		beq	.L702
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9934              		.loc 1 1077 7 discriminator 10 view .LVU3131
+ 9935 013e 102D     		cmp	r5, #16
+ 9936 0140 0FD0     		beq	.L703
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9937              		.loc 1 1077 7 discriminator 13 view .LVU3132
+ 9938 0142 0222     		movs	r2, #2
+ 9939 0144 84F84320 		strb	r2, [r4, #67]
+ 9940 0148 81E7     		b	.L668
+ 9941              	.L700:
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9942              		.loc 1 1077 7 discriminator 3 view .LVU3133
+ 9943 014a 0222     		movs	r2, #2
+ 9944 014c 84F83F20 		strb	r2, [r4, #63]
+ 9945 0150 7DE7     		b	.L668
+ 9946              	.L701:
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9947              		.loc 1 1077 7 discriminator 6 view .LVU3134
+ 9948 0152 0222     		movs	r2, #2
+ 9949 0154 84F84020 		strb	r2, [r4, #64]
+ 9950 0158 79E7     		b	.L668
+ 9951              	.L702:
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9952              		.loc 1 1077 7 discriminator 9 view .LVU3135
+ 9953 015a 0222     		movs	r2, #2
+ 9954 015c 84F84120 		strb	r2, [r4, #65]
+ 9955 0160 75E7     		b	.L668
+ 9956              	.L703:
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9957              		.loc 1 1077 7 discriminator 12 view .LVU3136
+ 9958 0162 0222     		movs	r2, #2
+ 9959 0164 84F84220 		strb	r2, [r4, #66]
+ 9960 0168 71E7     		b	.L668
+ 9961              	.L677:
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 9962              		.loc 1 1090 7 is_stmt 1 view .LVU3137
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 9963              		.loc 1 1090 17 is_stmt 0 view .LVU3138
+ 9964 016a 626A     		ldr	r2, [r4, #36]
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 9965              		.loc 1 1090 52 view .LVU3139
+ 9966 016c 5749     		ldr	r1, .L704
+ 9967              	.LVL783:
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 9968              		.loc 1 1090 52 view .LVU3140
+ARM GAS  /tmp/ccPLZXyC.s 			page 358
+
+
+ 9969 016e D163     		str	r1, [r2, #60]
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9970              		.loc 1 1091 7 is_stmt 1 view .LVU3141
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9971              		.loc 1 1091 17 is_stmt 0 view .LVU3142
+ 9972 0170 626A     		ldr	r2, [r4, #36]
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9973              		.loc 1 1091 56 view .LVU3143
+ 9974 0172 5749     		ldr	r1, .L704+4
+ 9975 0174 1164     		str	r1, [r2, #64]
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9976              		.loc 1 1094 7 is_stmt 1 view .LVU3144
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9977              		.loc 1 1094 17 is_stmt 0 view .LVU3145
+ 9978 0176 626A     		ldr	r2, [r4, #36]
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 9979              		.loc 1 1094 53 view .LVU3146
+ 9980 0178 5649     		ldr	r1, .L704+8
+ 9981 017a D164     		str	r1, [r2, #76]
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 9982              		.loc 1 1097 7 is_stmt 1 view .LVU3147
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 9983              		.loc 1 1097 88 is_stmt 0 view .LVU3148
+ 9984 017c 2268     		ldr	r2, [r4]
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 9985              		.loc 1 1097 11 view .LVU3149
+ 9986 017e 3432     		adds	r2, r2, #52
+ 9987 0180 6146     		mov	r1, ip
+ 9988 0182 606A     		ldr	r0, [r4, #36]
+ 9989 0184 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 9990              	.LVL784:
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 9991              		.loc 1 1097 10 view .LVU3150
+ 9992 0188 0028     		cmp	r0, #0
+ 9993 018a 40F09480 		bne	.L686
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 9994              		.loc 1 1105 7 is_stmt 1 view .LVU3151
+ 9995 018e 2268     		ldr	r2, [r4]
+ 9996 0190 D368     		ldr	r3, [r2, #12]
+ 9997 0192 43F40073 		orr	r3, r3, #512
+ 9998 0196 D360     		str	r3, [r2, #12]
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 9999              		.loc 1 1106 7 view .LVU3152
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10000              		.loc 1 1178 3 view .LVU3153
+ 10001              	.L678:
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10002              		.loc 1 1181 5 view .LVU3154
+ 10003 0198 0122     		movs	r2, #1
+ 10004 019a 2946     		mov	r1, r5
+ 10005 019c 2068     		ldr	r0, [r4]
+ 10006 019e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 10007              	.LVL785:
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10008              		.loc 1 1183 5 view .LVU3155
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10009              		.loc 1 1183 9 is_stmt 0 view .LVU3156
+ARM GAS  /tmp/ccPLZXyC.s 			page 359
+
+
+ 10010 01a2 2368     		ldr	r3, [r4]
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10011              		.loc 1 1183 8 view .LVU3157
+ 10012 01a4 4C49     		ldr	r1, .L704+12
+ 10013 01a6 4D4A     		ldr	r2, .L704+16
+ 10014 01a8 9342     		cmp	r3, r2
+ 10015 01aa 18BF     		it	ne
+ 10016 01ac 8B42     		cmpne	r3, r1
+ 10017 01ae 03D1     		bne	.L679
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10018              		.loc 1 1186 7 is_stmt 1 view .LVU3158
+ 10019 01b0 5A6C     		ldr	r2, [r3, #68]
+ 10020 01b2 42F40042 		orr	r2, r2, #32768
+ 10021 01b6 5A64     		str	r2, [r3, #68]
+ 10022              	.L679:
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10023              		.loc 1 1190 5 view .LVU3159
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10024              		.loc 1 1190 9 is_stmt 0 view .LVU3160
+ 10025 01b8 2368     		ldr	r3, [r4]
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10026              		.loc 1 1190 8 view .LVU3161
+ 10027 01ba 474A     		ldr	r2, .L704+12
+ 10028 01bc B3F1804F 		cmp	r3, #1073741824
+ 10029 01c0 18BF     		it	ne
+ 10030 01c2 9342     		cmpne	r3, r2
+ 10031 01c4 61D0     		beq	.L680
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10032              		.loc 1 1190 9 discriminator 1 view .LVU3162
+ 10033 01c6 A2F57C42 		sub	r2, r2, #64512
+ 10034 01ca 9342     		cmp	r3, r2
+ 10035 01cc 5DD0     		beq	.L680
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10036              		.loc 1 1190 9 discriminator 2 view .LVU3163
+ 10037 01ce 02F58062 		add	r2, r2, #1024
+ 10038 01d2 9342     		cmp	r3, r2
+ 10039 01d4 59D0     		beq	.L680
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10040              		.loc 1 1190 9 discriminator 3 view .LVU3164
+ 10041 01d6 02F58062 		add	r2, r2, #1024
+ 10042 01da 9342     		cmp	r3, r2
+ 10043 01dc 55D0     		beq	.L680
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10044              		.loc 1 1190 9 discriminator 4 view .LVU3165
+ 10045 01de 02F57842 		add	r2, r2, #63488
+ 10046 01e2 9342     		cmp	r3, r2
+ 10047 01e4 51D0     		beq	.L680
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10048              		.loc 1 1190 9 discriminator 5 view .LVU3166
+ 10049 01e6 02F57052 		add	r2, r2, #15360
+ 10050 01ea 9342     		cmp	r3, r2
+ 10051 01ec 4DD0     		beq	.L680
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10052              		.loc 1 1190 9 discriminator 6 view .LVU3167
+ 10053 01ee A2F59432 		sub	r2, r2, #75776
+ 10054 01f2 9342     		cmp	r3, r2
+ 10055 01f4 49D0     		beq	.L680
+ARM GAS  /tmp/ccPLZXyC.s 			page 360
+
+
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10056              		.loc 1 1200 7 is_stmt 1 view .LVU3168
+ 10057 01f6 1A68     		ldr	r2, [r3]
+ 10058 01f8 42F00102 		orr	r2, r2, #1
+ 10059 01fc 1A60     		str	r2, [r3]
+ 10060 01fe 0020     		movs	r0, #0
+ 10061 0200 54E0     		b	.L660
+ 10062              	.LVL786:
+ 10063              	.L676:
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10064              		.loc 1 1112 7 view .LVU3169
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10065              		.loc 1 1112 17 is_stmt 0 view .LVU3170
+ 10066 0202 A26A     		ldr	r2, [r4, #40]
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10067              		.loc 1 1112 52 view .LVU3171
+ 10068 0204 3149     		ldr	r1, .L704
+ 10069              	.LVL787:
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10070              		.loc 1 1112 52 view .LVU3172
+ 10071 0206 D163     		str	r1, [r2, #60]
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10072              		.loc 1 1113 7 is_stmt 1 view .LVU3173
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10073              		.loc 1 1113 17 is_stmt 0 view .LVU3174
+ 10074 0208 A26A     		ldr	r2, [r4, #40]
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10075              		.loc 1 1113 56 view .LVU3175
+ 10076 020a 3149     		ldr	r1, .L704+4
+ 10077 020c 1164     		str	r1, [r2, #64]
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10078              		.loc 1 1116 7 is_stmt 1 view .LVU3176
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10079              		.loc 1 1116 17 is_stmt 0 view .LVU3177
+ 10080 020e A26A     		ldr	r2, [r4, #40]
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10081              		.loc 1 1116 53 view .LVU3178
+ 10082 0210 3049     		ldr	r1, .L704+8
+ 10083 0212 D164     		str	r1, [r2, #76]
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10084              		.loc 1 1119 7 is_stmt 1 view .LVU3179
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10085              		.loc 1 1119 88 is_stmt 0 view .LVU3180
+ 10086 0214 2268     		ldr	r2, [r4]
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10087              		.loc 1 1119 11 view .LVU3181
+ 10088 0216 3832     		adds	r2, r2, #56
+ 10089 0218 6146     		mov	r1, ip
+ 10090 021a A06A     		ldr	r0, [r4, #40]
+ 10091 021c FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 10092              	.LVL788:
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10093              		.loc 1 1119 10 view .LVU3182
+ 10094 0220 0028     		cmp	r0, #0
+ 10095 0222 4AD1     		bne	.L687
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10096              		.loc 1 1127 7 is_stmt 1 view .LVU3183
+ARM GAS  /tmp/ccPLZXyC.s 			page 361
+
+
+ 10097 0224 2268     		ldr	r2, [r4]
+ 10098 0226 D368     		ldr	r3, [r2, #12]
+ 10099 0228 43F48063 		orr	r3, r3, #1024
+ 10100 022c D360     		str	r3, [r2, #12]
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10101              		.loc 1 1128 7 view .LVU3184
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10102              		.loc 1 1178 3 view .LVU3185
+ 10103 022e B3E7     		b	.L678
+ 10104              	.LVL789:
+ 10105              	.L675:
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10106              		.loc 1 1134 7 view .LVU3186
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10107              		.loc 1 1134 17 is_stmt 0 view .LVU3187
+ 10108 0230 E26A     		ldr	r2, [r4, #44]
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10109              		.loc 1 1134 52 view .LVU3188
+ 10110 0232 2649     		ldr	r1, .L704
+ 10111              	.LVL790:
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10112              		.loc 1 1134 52 view .LVU3189
+ 10113 0234 D163     		str	r1, [r2, #60]
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10114              		.loc 1 1135 7 is_stmt 1 view .LVU3190
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10115              		.loc 1 1135 17 is_stmt 0 view .LVU3191
+ 10116 0236 E26A     		ldr	r2, [r4, #44]
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10117              		.loc 1 1135 56 view .LVU3192
+ 10118 0238 2549     		ldr	r1, .L704+4
+ 10119 023a 1164     		str	r1, [r2, #64]
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10120              		.loc 1 1138 7 is_stmt 1 view .LVU3193
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10121              		.loc 1 1138 17 is_stmt 0 view .LVU3194
+ 10122 023c E26A     		ldr	r2, [r4, #44]
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10123              		.loc 1 1138 53 view .LVU3195
+ 10124 023e 2549     		ldr	r1, .L704+8
+ 10125 0240 D164     		str	r1, [r2, #76]
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10126              		.loc 1 1141 7 is_stmt 1 view .LVU3196
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10127              		.loc 1 1141 88 is_stmt 0 view .LVU3197
+ 10128 0242 2268     		ldr	r2, [r4]
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10129              		.loc 1 1141 11 view .LVU3198
+ 10130 0244 3C32     		adds	r2, r2, #60
+ 10131 0246 6146     		mov	r1, ip
+ 10132 0248 E06A     		ldr	r0, [r4, #44]
+ 10133 024a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 10134              	.LVL791:
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10135              		.loc 1 1141 10 view .LVU3199
+ 10136 024e 0028     		cmp	r0, #0
+ 10137 0250 35D1     		bne	.L688
+ARM GAS  /tmp/ccPLZXyC.s 			page 362
+
+
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10138              		.loc 1 1148 7 is_stmt 1 view .LVU3200
+ 10139 0252 2268     		ldr	r2, [r4]
+ 10140 0254 D368     		ldr	r3, [r2, #12]
+ 10141 0256 43F40063 		orr	r3, r3, #2048
+ 10142 025a D360     		str	r3, [r2, #12]
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10143              		.loc 1 1149 7 view .LVU3201
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10144              		.loc 1 1178 3 view .LVU3202
+ 10145 025c 9CE7     		b	.L678
+ 10146              	.LVL792:
+ 10147              	.L673:
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10148              		.loc 1 1155 7 view .LVU3203
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10149              		.loc 1 1155 17 is_stmt 0 view .LVU3204
+ 10150 025e 226B     		ldr	r2, [r4, #48]
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10151              		.loc 1 1155 52 view .LVU3205
+ 10152 0260 1A49     		ldr	r1, .L704
+ 10153              	.LVL793:
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 10154              		.loc 1 1155 52 view .LVU3206
+ 10155 0262 D163     		str	r1, [r2, #60]
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10156              		.loc 1 1156 7 is_stmt 1 view .LVU3207
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10157              		.loc 1 1156 17 is_stmt 0 view .LVU3208
+ 10158 0264 226B     		ldr	r2, [r4, #48]
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10159              		.loc 1 1156 56 view .LVU3209
+ 10160 0266 1A49     		ldr	r1, .L704+4
+ 10161 0268 1164     		str	r1, [r2, #64]
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10162              		.loc 1 1159 7 is_stmt 1 view .LVU3210
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10163              		.loc 1 1159 17 is_stmt 0 view .LVU3211
+ 10164 026a 226B     		ldr	r2, [r4, #48]
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10165              		.loc 1 1159 53 view .LVU3212
+ 10166 026c 1949     		ldr	r1, .L704+8
+ 10167 026e D164     		str	r1, [r2, #76]
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10168              		.loc 1 1162 7 is_stmt 1 view .LVU3213
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10169              		.loc 1 1162 88 is_stmt 0 view .LVU3214
+ 10170 0270 2268     		ldr	r2, [r4]
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10171              		.loc 1 1162 11 view .LVU3215
+ 10172 0272 4032     		adds	r2, r2, #64
+ 10173 0274 6146     		mov	r1, ip
+ 10174 0276 206B     		ldr	r0, [r4, #48]
+ 10175 0278 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 10176              	.LVL794:
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 10177              		.loc 1 1162 10 view .LVU3216
+ARM GAS  /tmp/ccPLZXyC.s 			page 363
+
+
+ 10178 027c 08BB     		cbnz	r0, .L689
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10179              		.loc 1 1169 7 is_stmt 1 view .LVU3217
+ 10180 027e 2268     		ldr	r2, [r4]
+ 10181 0280 D368     		ldr	r3, [r2, #12]
+ 10182 0282 43F48053 		orr	r3, r3, #4096
+ 10183 0286 D360     		str	r3, [r2, #12]
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10184              		.loc 1 1170 7 view .LVU3218
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10185              		.loc 1 1178 3 view .LVU3219
+ 10186 0288 86E7     		b	.L678
+ 10187              	.L680:
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 10188              		.loc 1 1192 7 view .LVU3220
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 10189              		.loc 1 1192 31 is_stmt 0 view .LVU3221
+ 10190 028a 9968     		ldr	r1, [r3, #8]
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 10191              		.loc 1 1192 15 view .LVU3222
+ 10192 028c 144A     		ldr	r2, .L704+20
+ 10193 028e 0A40     		ands	r2, r2, r1
+ 10194              	.LVL795:
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 10195              		.loc 1 1193 7 is_stmt 1 view .LVU3223
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 10196              		.loc 1 1193 10 is_stmt 0 view .LVU3224
+ 10197 0290 062A     		cmp	r2, #6
+ 10198 0292 18BF     		it	ne
+ 10199 0294 B2F5803F 		cmpne	r2, #65536
+ 10200 0298 15D0     		beq	.L690
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 10201              		.loc 1 1195 9 is_stmt 1 view .LVU3225
+ 10202 029a 1A68     		ldr	r2, [r3]
+ 10203              	.LVL796:
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 10204              		.loc 1 1195 9 is_stmt 0 view .LVU3226
+ 10205 029c 42F00102 		orr	r2, r2, #1
+ 10206 02a0 1A60     		str	r2, [r3]
+ 10207 02a2 0020     		movs	r0, #0
+ 10208 02a4 02E0     		b	.L660
+ 10209              	.LVL797:
+ 10210              	.L682:
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10211              		.loc 1 1067 12 view .LVU3227
+ 10212 02a6 0220     		movs	r0, #2
+ 10213 02a8 00E0     		b	.L660
+ 10214              	.LVL798:
+ 10215              	.L683:
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10216              		.loc 1 1082 12 view .LVU3228
+ 10217 02aa 0120     		movs	r0, #1
+ 10218              	.LVL799:
+ 10219              	.L660:
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10220              		.loc 1 1206 1 view .LVU3229
+ 10221 02ac 38BD     		pop	{r3, r4, r5, pc}
+ARM GAS  /tmp/ccPLZXyC.s 			page 364
+
+
+ 10222              	.LVL800:
+ 10223              	.L684:
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10224              		.loc 1 1073 14 view .LVU3230
+ 10225 02ae 0120     		movs	r0, #1
+ 10226 02b0 FCE7     		b	.L660
+ 10227              	.L685:
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10228              		.loc 1 1085 3 view .LVU3231
+ 10229 02b2 0120     		movs	r0, #1
+ 10230 02b4 FAE7     		b	.L660
+ 10231              	.LVL801:
+ 10232              	.L686:
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 10233              		.loc 1 1101 16 view .LVU3232
+ 10234 02b6 0120     		movs	r0, #1
+ 10235 02b8 F8E7     		b	.L660
+ 10236              	.L687:
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 10237              		.loc 1 1123 16 view .LVU3233
+ 10238 02ba 0120     		movs	r0, #1
+ 10239 02bc F6E7     		b	.L660
+ 10240              	.L688:
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 10241              		.loc 1 1145 16 view .LVU3234
+ 10242 02be 0120     		movs	r0, #1
+ 10243 02c0 F4E7     		b	.L660
+ 10244              	.L689:
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 10245              		.loc 1 1166 16 view .LVU3235
+ 10246 02c2 0120     		movs	r0, #1
+ 10247 02c4 F2E7     		b	.L660
+ 10248              	.LVL802:
+ 10249              	.L690:
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 10250              		.loc 1 1166 16 view .LVU3236
+ 10251 02c6 0020     		movs	r0, #0
+ 10252 02c8 F0E7     		b	.L660
+ 10253              	.L705:
+ 10254 02ca 00BF     		.align	2
+ 10255              	.L704:
+ 10256 02cc 00000000 		.word	TIM_DMADelayPulseCplt
+ 10257 02d0 00000000 		.word	TIM_DMADelayPulseHalfCplt
+ 10258 02d4 00000000 		.word	TIM_DMAError
+ 10259 02d8 00000140 		.word	1073807360
+ 10260 02dc 00040140 		.word	1073808384
+ 10261 02e0 07000100 		.word	65543
+ 10262              		.cfi_endproc
+ 10263              	.LFE159:
+ 10265              		.section	.text.HAL_TIM_OC_Stop_DMA,"ax",%progbits
+ 10266              		.align	1
+ 10267              		.global	HAL_TIM_OC_Stop_DMA
+ 10268              		.syntax unified
+ 10269              		.thumb
+ 10270              		.thumb_func
+ 10271              		.fpu fpv5-d16
+ 10273              	HAL_TIM_OC_Stop_DMA:
+ARM GAS  /tmp/ccPLZXyC.s 			page 365
+
+
+ 10274              	.LVL803:
+ 10275              	.LFB160:
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 10276              		.loc 1 1220 1 is_stmt 1 view -0
+ 10277              		.cfi_startproc
+ 10278              		@ args = 0, pretend = 0, frame = 0
+ 10279              		@ frame_needed = 0, uses_anonymous_args = 0
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 10280              		.loc 1 1220 1 is_stmt 0 view .LVU3238
+ 10281 0000 38B5     		push	{r3, r4, r5, lr}
+ 10282              	.LCFI91:
+ 10283              		.cfi_def_cfa_offset 16
+ 10284              		.cfi_offset 3, -16
+ 10285              		.cfi_offset 4, -12
+ 10286              		.cfi_offset 5, -8
+ 10287              		.cfi_offset 14, -4
+ 10288 0002 0446     		mov	r4, r0
+ 10289 0004 0D46     		mov	r5, r1
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10290              		.loc 1 1221 3 is_stmt 1 view .LVU3239
+ 10291              	.LVL804:
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10292              		.loc 1 1224 3 view .LVU3240
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10293              		.loc 1 1226 3 view .LVU3241
+ 10294 0006 0C29     		cmp	r1, #12
+ 10295 0008 7BD8     		bhi	.L721
+ 10296 000a DFE801F0 		tbb	[pc, r1]
+ 10297              	.L709:
+ 10298 000e 07       		.byte	(.L712-.L709)/2
+ 10299 000f 7A       		.byte	(.L721-.L709)/2
+ 10300 0010 7A       		.byte	(.L721-.L709)/2
+ 10301 0011 7A       		.byte	(.L721-.L709)/2
+ 10302 0012 3E       		.byte	(.L711-.L709)/2
+ 10303 0013 7A       		.byte	(.L721-.L709)/2
+ 10304 0014 7A       		.byte	(.L721-.L709)/2
+ 10305 0015 7A       		.byte	(.L721-.L709)/2
+ 10306 0016 47       		.byte	(.L710-.L709)/2
+ 10307 0017 7A       		.byte	(.L721-.L709)/2
+ 10308 0018 7A       		.byte	(.L721-.L709)/2
+ 10309 0019 7A       		.byte	(.L721-.L709)/2
+ 10310 001a 50       		.byte	(.L708-.L709)/2
+ 10311 001b 00       		.p2align 1
+ 10312              	.L712:
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 10313              		.loc 1 1231 7 view .LVU3242
+ 10314 001c 0268     		ldr	r2, [r0]
+ 10315 001e D368     		ldr	r3, [r2, #12]
+ 10316 0020 23F40073 		bic	r3, r3, #512
+ 10317 0024 D360     		str	r3, [r2, #12]
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10318              		.loc 1 1232 7 view .LVU3243
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10319              		.loc 1 1232 13 is_stmt 0 view .LVU3244
+ 10320 0026 406A     		ldr	r0, [r0, #36]
+ 10321              	.LVL805:
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ARM GAS  /tmp/ccPLZXyC.s 			page 366
+
+
+ 10322              		.loc 1 1232 13 view .LVU3245
+ 10323 0028 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 10324              	.LVL806:
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10325              		.loc 1 1233 7 is_stmt 1 view .LVU3246
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10326              		.loc 1 1265 3 view .LVU3247
+ 10327              	.L713:
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10328              		.loc 1 1268 5 view .LVU3248
+ 10329 002c 0022     		movs	r2, #0
+ 10330 002e 2946     		mov	r1, r5
+ 10331 0030 2068     		ldr	r0, [r4]
+ 10332 0032 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 10333              	.LVL807:
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10334              		.loc 1 1270 5 view .LVU3249
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10335              		.loc 1 1270 9 is_stmt 0 view .LVU3250
+ 10336 0036 2368     		ldr	r3, [r4]
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10337              		.loc 1 1270 8 view .LVU3251
+ 10338 0038 3349     		ldr	r1, .L727
+ 10339 003a 344A     		ldr	r2, .L727+4
+ 10340 003c 9342     		cmp	r3, r2
+ 10341 003e 18BF     		it	ne
+ 10342 0040 8B42     		cmpne	r3, r1
+ 10343 0042 0DD1     		bne	.L714
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10344              		.loc 1 1273 7 is_stmt 1 view .LVU3252
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10345              		.loc 1 1273 7 view .LVU3253
+ 10346 0044 196A     		ldr	r1, [r3, #32]
+ 10347 0046 41F21112 		movw	r2, #4369
+ 10348 004a 1142     		tst	r1, r2
+ 10349 004c 08D1     		bne	.L714
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10350              		.loc 1 1273 7 discriminator 1 view .LVU3254
+ 10351 004e 196A     		ldr	r1, [r3, #32]
+ 10352 0050 40F24442 		movw	r2, #1092
+ 10353 0054 1142     		tst	r1, r2
+ 10354 0056 03D1     		bne	.L714
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10355              		.loc 1 1273 7 discriminator 3 view .LVU3255
+ 10356 0058 5A6C     		ldr	r2, [r3, #68]
+ 10357 005a 22F40042 		bic	r2, r2, #32768
+ 10358 005e 5A64     		str	r2, [r3, #68]
+ 10359              	.L714:
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10360              		.loc 1 1273 7 discriminator 5 view .LVU3256
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10361              		.loc 1 1277 5 discriminator 5 view .LVU3257
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10362              		.loc 1 1277 5 discriminator 5 view .LVU3258
+ 10363 0060 2368     		ldr	r3, [r4]
+ 10364 0062 196A     		ldr	r1, [r3, #32]
+ 10365 0064 41F21112 		movw	r2, #4369
+ARM GAS  /tmp/ccPLZXyC.s 			page 367
+
+
+ 10366 0068 1142     		tst	r1, r2
+ 10367 006a 08D1     		bne	.L715
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10368              		.loc 1 1277 5 discriminator 1 view .LVU3259
+ 10369 006c 196A     		ldr	r1, [r3, #32]
+ 10370 006e 40F24442 		movw	r2, #1092
+ 10371 0072 1142     		tst	r1, r2
+ 10372 0074 03D1     		bne	.L715
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10373              		.loc 1 1277 5 discriminator 3 view .LVU3260
+ 10374 0076 1A68     		ldr	r2, [r3]
+ 10375 0078 22F00102 		bic	r2, r2, #1
+ 10376 007c 1A60     		str	r2, [r3]
+ 10377              	.L715:
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10378              		.loc 1 1277 5 discriminator 5 view .LVU3261
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10379              		.loc 1 1280 5 discriminator 5 view .LVU3262
+ 10380 007e FDB9     		cbnz	r5, .L716
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10381              		.loc 1 1280 5 is_stmt 0 discriminator 1 view .LVU3263
+ 10382 0080 0123     		movs	r3, #1
+ 10383 0082 84F83E30 		strb	r3, [r4, #62]
+ 10384 0086 0020     		movs	r0, #0
+ 10385 0088 3CE0     		b	.L707
+ 10386              	.LVL808:
+ 10387              	.L711:
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 10388              		.loc 1 1239 7 is_stmt 1 view .LVU3264
+ 10389 008a 0268     		ldr	r2, [r0]
+ 10390 008c D368     		ldr	r3, [r2, #12]
+ 10391 008e 23F48063 		bic	r3, r3, #1024
+ 10392 0092 D360     		str	r3, [r2, #12]
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10393              		.loc 1 1240 7 view .LVU3265
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10394              		.loc 1 1240 13 is_stmt 0 view .LVU3266
+ 10395 0094 806A     		ldr	r0, [r0, #40]
+ 10396              	.LVL809:
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10397              		.loc 1 1240 13 view .LVU3267
+ 10398 0096 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 10399              	.LVL810:
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10400              		.loc 1 1241 7 is_stmt 1 view .LVU3268
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10401              		.loc 1 1265 3 view .LVU3269
+ 10402 009a C7E7     		b	.L713
+ 10403              	.LVL811:
+ 10404              	.L710:
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ 10405              		.loc 1 1247 7 view .LVU3270
+ 10406 009c 0268     		ldr	r2, [r0]
+ 10407 009e D368     		ldr	r3, [r2, #12]
+ 10408 00a0 23F40063 		bic	r3, r3, #2048
+ 10409 00a4 D360     		str	r3, [r2, #12]
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ARM GAS  /tmp/ccPLZXyC.s 			page 368
+
+
+ 10410              		.loc 1 1248 7 view .LVU3271
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10411              		.loc 1 1248 13 is_stmt 0 view .LVU3272
+ 10412 00a6 C06A     		ldr	r0, [r0, #44]
+ 10413              	.LVL812:
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10414              		.loc 1 1248 13 view .LVU3273
+ 10415 00a8 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 10416              	.LVL813:
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10417              		.loc 1 1249 7 is_stmt 1 view .LVU3274
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10418              		.loc 1 1265 3 view .LVU3275
+ 10419 00ac BEE7     		b	.L713
+ 10420              	.LVL814:
+ 10421              	.L708:
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ 10422              		.loc 1 1255 7 view .LVU3276
+ 10423 00ae 0268     		ldr	r2, [r0]
+ 10424 00b0 D368     		ldr	r3, [r2, #12]
+ 10425 00b2 23F48053 		bic	r3, r3, #4096
+ 10426 00b6 D360     		str	r3, [r2, #12]
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10427              		.loc 1 1256 7 view .LVU3277
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10428              		.loc 1 1256 13 is_stmt 0 view .LVU3278
+ 10429 00b8 006B     		ldr	r0, [r0, #48]
+ 10430              	.LVL815:
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 10431              		.loc 1 1256 13 view .LVU3279
+ 10432 00ba FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 10433              	.LVL816:
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10434              		.loc 1 1257 7 is_stmt 1 view .LVU3280
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10435              		.loc 1 1265 3 view .LVU3281
+ 10436 00be B5E7     		b	.L713
+ 10437              	.L716:
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10438              		.loc 1 1280 5 is_stmt 0 discriminator 2 view .LVU3282
+ 10439 00c0 042D     		cmp	r5, #4
+ 10440 00c2 0AD0     		beq	.L723
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10441              		.loc 1 1280 5 discriminator 4 view .LVU3283
+ 10442 00c4 082D     		cmp	r5, #8
+ 10443 00c6 0DD0     		beq	.L724
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10444              		.loc 1 1280 5 discriminator 7 view .LVU3284
+ 10445 00c8 0C2D     		cmp	r5, #12
+ 10446 00ca 10D0     		beq	.L725
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10447              		.loc 1 1280 5 discriminator 10 view .LVU3285
+ 10448 00cc 102D     		cmp	r5, #16
+ 10449 00ce 13D0     		beq	.L726
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10450              		.loc 1 1280 5 discriminator 13 view .LVU3286
+ 10451 00d0 0123     		movs	r3, #1
+ARM GAS  /tmp/ccPLZXyC.s 			page 369
+
+
+ 10452 00d2 84F84330 		strb	r3, [r4, #67]
+ 10453 00d6 0020     		movs	r0, #0
+ 10454 00d8 14E0     		b	.L707
+ 10455              	.L723:
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10456              		.loc 1 1280 5 discriminator 3 view .LVU3287
+ 10457 00da 0123     		movs	r3, #1
+ 10458 00dc 84F83F30 		strb	r3, [r4, #63]
+ 10459 00e0 0020     		movs	r0, #0
+ 10460 00e2 0FE0     		b	.L707
+ 10461              	.L724:
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10462              		.loc 1 1280 5 discriminator 6 view .LVU3288
+ 10463 00e4 0123     		movs	r3, #1
+ 10464 00e6 84F84030 		strb	r3, [r4, #64]
+ 10465 00ea 0020     		movs	r0, #0
+ 10466 00ec 0AE0     		b	.L707
+ 10467              	.L725:
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10468              		.loc 1 1280 5 discriminator 9 view .LVU3289
+ 10469 00ee 0123     		movs	r3, #1
+ 10470 00f0 84F84130 		strb	r3, [r4, #65]
+ 10471 00f4 0020     		movs	r0, #0
+ 10472 00f6 05E0     		b	.L707
+ 10473              	.L726:
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10474              		.loc 1 1280 5 discriminator 12 view .LVU3290
+ 10475 00f8 0123     		movs	r3, #1
+ 10476 00fa 84F84230 		strb	r3, [r4, #66]
+ 10477 00fe 0020     		movs	r0, #0
+ 10478 0100 00E0     		b	.L707
+ 10479              	.LVL817:
+ 10480              	.L721:
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10481              		.loc 1 1226 3 view .LVU3291
+ 10482 0102 0120     		movs	r0, #1
+ 10483              	.LVL818:
+ 10484              	.L707:
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 10485              		.loc 1 1284 3 is_stmt 1 view .LVU3292
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10486              		.loc 1 1285 1 is_stmt 0 view .LVU3293
+ 10487 0104 38BD     		pop	{r3, r4, r5, pc}
+ 10488              	.LVL819:
+ 10489              	.L728:
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10490              		.loc 1 1285 1 view .LVU3294
+ 10491 0106 00BF     		.align	2
+ 10492              	.L727:
+ 10493 0108 00000140 		.word	1073807360
+ 10494 010c 00040140 		.word	1073808384
+ 10495              		.cfi_endproc
+ 10496              	.LFE160:
+ 10498              		.section	.text.HAL_TIM_PWM_Start,"ax",%progbits
+ 10499              		.align	1
+ 10500              		.global	HAL_TIM_PWM_Start
+ 10501              		.syntax unified
+ARM GAS  /tmp/ccPLZXyC.s 			page 370
+
+
+ 10502              		.thumb
+ 10503              		.thumb_func
+ 10504              		.fpu fpv5-d16
+ 10506              	HAL_TIM_PWM_Start:
+ 10507              	.LVL820:
+ 10508              	.LFB165:
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 10509              		.loc 1 1464 1 is_stmt 1 view -0
+ 10510              		.cfi_startproc
+ 10511              		@ args = 0, pretend = 0, frame = 0
+ 10512              		@ frame_needed = 0, uses_anonymous_args = 0
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 10513              		.loc 1 1464 1 is_stmt 0 view .LVU3296
+ 10514 0000 10B5     		push	{r4, lr}
+ 10515              	.LCFI92:
+ 10516              		.cfi_def_cfa_offset 8
+ 10517              		.cfi_offset 4, -8
+ 10518              		.cfi_offset 14, -4
+ 10519 0002 0446     		mov	r4, r0
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10520              		.loc 1 1465 3 is_stmt 1 view .LVU3297
+1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10521              		.loc 1 1468 3 view .LVU3298
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10522              		.loc 1 1471 3 view .LVU3299
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10523              		.loc 1 1471 44 is_stmt 0 view .LVU3300
+ 10524 0004 0846     		mov	r0, r1
+ 10525              	.LVL821:
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10526              		.loc 1 1471 44 view .LVU3301
+ 10527 0006 0029     		cmp	r1, #0
+ 10528 0008 42D1     		bne	.L730
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10529              		.loc 1 1471 7 discriminator 1 view .LVU3302
+ 10530 000a 94F83E30 		ldrb	r3, [r4, #62]	@ zero_extendqisi2
+ 10531 000e DBB2     		uxtb	r3, r3
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10532              		.loc 1 1471 44 discriminator 1 view .LVU3303
+ 10533 0010 013B     		subs	r3, r3, #1
+ 10534 0012 18BF     		it	ne
+ 10535 0014 0123     		movne	r3, #1
+ 10536              	.L731:
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10537              		.loc 1 1471 6 discriminator 20 view .LVU3304
+ 10538 0016 002B     		cmp	r3, #0
+ 10539 0018 40F08F80 		bne	.L746
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10540              		.loc 1 1477 3 is_stmt 1 view .LVU3305
+ 10541 001c 0028     		cmp	r0, #0
+ 10542 001e 62D1     		bne	.L737
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10543              		.loc 1 1477 3 is_stmt 0 discriminator 1 view .LVU3306
+ 10544 0020 0223     		movs	r3, #2
+ 10545 0022 84F83E30 		strb	r3, [r4, #62]
+ 10546              	.L738:
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 371
+
+
+ 10547              		.loc 1 1480 3 is_stmt 1 view .LVU3307
+ 10548 0026 0122     		movs	r2, #1
+ 10549 0028 0146     		mov	r1, r0
+ 10550              	.LVL822:
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10551              		.loc 1 1480 3 is_stmt 0 view .LVU3308
+ 10552 002a 2068     		ldr	r0, [r4]
+ 10553              	.LVL823:
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10554              		.loc 1 1480 3 view .LVU3309
+ 10555 002c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 10556              	.LVL824:
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10557              		.loc 1 1482 3 is_stmt 1 view .LVU3310
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10558              		.loc 1 1482 7 is_stmt 0 view .LVU3311
+ 10559 0030 2368     		ldr	r3, [r4]
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10560              		.loc 1 1482 6 view .LVU3312
+ 10561 0032 4449     		ldr	r1, .L757
+ 10562 0034 444A     		ldr	r2, .L757+4
+ 10563 0036 9342     		cmp	r3, r2
+ 10564 0038 18BF     		it	ne
+ 10565 003a 8B42     		cmpne	r3, r1
+ 10566 003c 03D1     		bne	.L743
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10567              		.loc 1 1485 5 is_stmt 1 view .LVU3313
+ 10568 003e 5A6C     		ldr	r2, [r3, #68]
+ 10569 0040 42F40042 		orr	r2, r2, #32768
+ 10570 0044 5A64     		str	r2, [r3, #68]
+ 10571              	.L743:
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10572              		.loc 1 1489 3 view .LVU3314
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10573              		.loc 1 1489 7 is_stmt 0 view .LVU3315
+ 10574 0046 2368     		ldr	r3, [r4]
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10575              		.loc 1 1489 6 view .LVU3316
+ 10576 0048 3E4A     		ldr	r2, .L757
+ 10577 004a B3F1804F 		cmp	r3, #1073741824
+ 10578 004e 18BF     		it	ne
+ 10579 0050 9342     		cmpne	r3, r2
+ 10580 0052 64D0     		beq	.L744
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10581              		.loc 1 1489 7 discriminator 1 view .LVU3317
+ 10582 0054 A2F57C42 		sub	r2, r2, #64512
+ 10583 0058 9342     		cmp	r3, r2
+ 10584 005a 60D0     		beq	.L744
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10585              		.loc 1 1489 7 discriminator 2 view .LVU3318
+ 10586 005c 02F58062 		add	r2, r2, #1024
+ 10587 0060 9342     		cmp	r3, r2
+ 10588 0062 5CD0     		beq	.L744
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10589              		.loc 1 1489 7 discriminator 3 view .LVU3319
+ 10590 0064 02F58062 		add	r2, r2, #1024
+ 10591 0068 9342     		cmp	r3, r2
+ARM GAS  /tmp/ccPLZXyC.s 			page 372
+
+
+ 10592 006a 58D0     		beq	.L744
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10593              		.loc 1 1489 7 discriminator 4 view .LVU3320
+ 10594 006c 02F57842 		add	r2, r2, #63488
+ 10595 0070 9342     		cmp	r3, r2
+ 10596 0072 54D0     		beq	.L744
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10597              		.loc 1 1489 7 discriminator 5 view .LVU3321
+ 10598 0074 02F57052 		add	r2, r2, #15360
+ 10599 0078 9342     		cmp	r3, r2
+ 10600 007a 50D0     		beq	.L744
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10601              		.loc 1 1489 7 discriminator 6 view .LVU3322
+ 10602 007c A2F59432 		sub	r2, r2, #75776
+ 10603 0080 9342     		cmp	r3, r2
+ 10604 0082 4CD0     		beq	.L744
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10605              		.loc 1 1499 5 is_stmt 1 view .LVU3323
+ 10606 0084 1A68     		ldr	r2, [r3]
+ 10607 0086 42F00102 		orr	r2, r2, #1
+ 10608 008a 1A60     		str	r2, [r3]
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 10609              		.loc 1 1503 10 is_stmt 0 view .LVU3324
+ 10610 008c 0020     		movs	r0, #0
+ 10611 008e 55E0     		b	.L736
+ 10612              	.LVL825:
+ 10613              	.L730:
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10614              		.loc 1 1471 44 discriminator 2 view .LVU3325
+ 10615 0090 0429     		cmp	r1, #4
+ 10616 0092 0CD0     		beq	.L749
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10617              		.loc 1 1471 44 discriminator 5 view .LVU3326
+ 10618 0094 0829     		cmp	r1, #8
+ 10619 0096 11D0     		beq	.L750
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10620              		.loc 1 1471 44 discriminator 8 view .LVU3327
+ 10621 0098 0C29     		cmp	r1, #12
+ 10622 009a 16D0     		beq	.L751
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10623              		.loc 1 1471 44 discriminator 11 view .LVU3328
+ 10624 009c 1029     		cmp	r1, #16
+ 10625 009e 1BD0     		beq	.L752
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10626              		.loc 1 1471 7 discriminator 14 view .LVU3329
+ 10627 00a0 94F84330 		ldrb	r3, [r4, #67]	@ zero_extendqisi2
+ 10628 00a4 DBB2     		uxtb	r3, r3
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10629              		.loc 1 1471 44 discriminator 14 view .LVU3330
+ 10630 00a6 013B     		subs	r3, r3, #1
+ 10631 00a8 18BF     		it	ne
+ 10632 00aa 0123     		movne	r3, #1
+ 10633 00ac B3E7     		b	.L731
+ 10634              	.L749:
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10635              		.loc 1 1471 7 discriminator 4 view .LVU3331
+ 10636 00ae 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ARM GAS  /tmp/ccPLZXyC.s 			page 373
+
+
+ 10637 00b2 DBB2     		uxtb	r3, r3
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10638              		.loc 1 1471 44 discriminator 4 view .LVU3332
+ 10639 00b4 013B     		subs	r3, r3, #1
+ 10640 00b6 18BF     		it	ne
+ 10641 00b8 0123     		movne	r3, #1
+ 10642 00ba ACE7     		b	.L731
+ 10643              	.L750:
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10644              		.loc 1 1471 7 discriminator 7 view .LVU3333
+ 10645 00bc 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 10646 00c0 DBB2     		uxtb	r3, r3
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10647              		.loc 1 1471 44 discriminator 7 view .LVU3334
+ 10648 00c2 013B     		subs	r3, r3, #1
+ 10649 00c4 18BF     		it	ne
+ 10650 00c6 0123     		movne	r3, #1
+ 10651 00c8 A5E7     		b	.L731
+ 10652              	.L751:
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10653              		.loc 1 1471 7 discriminator 10 view .LVU3335
+ 10654 00ca 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 10655 00ce DBB2     		uxtb	r3, r3
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10656              		.loc 1 1471 44 discriminator 10 view .LVU3336
+ 10657 00d0 013B     		subs	r3, r3, #1
+ 10658 00d2 18BF     		it	ne
+ 10659 00d4 0123     		movne	r3, #1
+ 10660 00d6 9EE7     		b	.L731
+ 10661              	.L752:
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10662              		.loc 1 1471 7 discriminator 13 view .LVU3337
+ 10663 00d8 94F84230 		ldrb	r3, [r4, #66]	@ zero_extendqisi2
+ 10664 00dc DBB2     		uxtb	r3, r3
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10665              		.loc 1 1471 44 discriminator 13 view .LVU3338
+ 10666 00de 013B     		subs	r3, r3, #1
+ 10667 00e0 18BF     		it	ne
+ 10668 00e2 0123     		movne	r3, #1
+ 10669 00e4 97E7     		b	.L731
+ 10670              	.L737:
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10671              		.loc 1 1477 3 discriminator 2 view .LVU3339
+ 10672 00e6 0428     		cmp	r0, #4
+ 10673 00e8 09D0     		beq	.L753
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10674              		.loc 1 1477 3 discriminator 4 view .LVU3340
+ 10675 00ea 0828     		cmp	r0, #8
+ 10676 00ec 0BD0     		beq	.L754
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10677              		.loc 1 1477 3 discriminator 7 view .LVU3341
+ 10678 00ee 0C28     		cmp	r0, #12
+ 10679 00f0 0DD0     		beq	.L755
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10680              		.loc 1 1477 3 discriminator 10 view .LVU3342
+ 10681 00f2 1028     		cmp	r0, #16
+ 10682 00f4 0FD0     		beq	.L756
+ARM GAS  /tmp/ccPLZXyC.s 			page 374
+
+
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10683              		.loc 1 1477 3 discriminator 13 view .LVU3343
+ 10684 00f6 0223     		movs	r3, #2
+ 10685 00f8 84F84330 		strb	r3, [r4, #67]
+ 10686 00fc 93E7     		b	.L738
+ 10687              	.L753:
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10688              		.loc 1 1477 3 discriminator 3 view .LVU3344
+ 10689 00fe 0223     		movs	r3, #2
+ 10690 0100 84F83F30 		strb	r3, [r4, #63]
+ 10691 0104 8FE7     		b	.L738
+ 10692              	.L754:
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10693              		.loc 1 1477 3 discriminator 6 view .LVU3345
+ 10694 0106 0223     		movs	r3, #2
+ 10695 0108 84F84030 		strb	r3, [r4, #64]
+ 10696 010c 8BE7     		b	.L738
+ 10697              	.L755:
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10698              		.loc 1 1477 3 discriminator 9 view .LVU3346
+ 10699 010e 0223     		movs	r3, #2
+ 10700 0110 84F84130 		strb	r3, [r4, #65]
+ 10701 0114 87E7     		b	.L738
+ 10702              	.L756:
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10703              		.loc 1 1477 3 discriminator 12 view .LVU3347
+ 10704 0116 0223     		movs	r3, #2
+ 10705 0118 84F84230 		strb	r3, [r4, #66]
+ 10706 011c 83E7     		b	.L738
+ 10707              	.LVL826:
+ 10708              	.L744:
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 10709              		.loc 1 1491 5 is_stmt 1 view .LVU3348
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 10710              		.loc 1 1491 29 is_stmt 0 view .LVU3349
+ 10711 011e 9968     		ldr	r1, [r3, #8]
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 10712              		.loc 1 1491 13 view .LVU3350
+ 10713 0120 0A4A     		ldr	r2, .L757+8
+ 10714 0122 0A40     		ands	r2, r2, r1
+ 10715              	.LVL827:
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10716              		.loc 1 1492 5 is_stmt 1 view .LVU3351
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 10717              		.loc 1 1492 8 is_stmt 0 view .LVU3352
+ 10718 0124 062A     		cmp	r2, #6
+ 10719 0126 18BF     		it	ne
+ 10720 0128 B2F5803F 		cmpne	r2, #65536
+ 10721 012c 07D0     		beq	.L747
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10722              		.loc 1 1494 7 is_stmt 1 view .LVU3353
+ 10723 012e 1A68     		ldr	r2, [r3]
+ 10724              	.LVL828:
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 10725              		.loc 1 1494 7 is_stmt 0 view .LVU3354
+ 10726 0130 42F00102 		orr	r2, r2, #1
+ 10727 0134 1A60     		str	r2, [r3]
+ARM GAS  /tmp/ccPLZXyC.s 			page 375
+
+
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 10728              		.loc 1 1503 10 view .LVU3355
+ 10729 0136 0020     		movs	r0, #0
+ 10730 0138 00E0     		b	.L736
+ 10731              	.LVL829:
+ 10732              	.L746:
+1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10733              		.loc 1 1473 12 view .LVU3356
+ 10734 013a 0120     		movs	r0, #1
+ 10735              	.LVL830:
+ 10736              	.L736:
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10737              		.loc 1 1504 1 view .LVU3357
+ 10738 013c 10BD     		pop	{r4, pc}
+ 10739              	.LVL831:
+ 10740              	.L747:
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 10741              		.loc 1 1503 10 view .LVU3358
+ 10742 013e 0020     		movs	r0, #0
+ 10743 0140 FCE7     		b	.L736
+ 10744              	.L758:
+ 10745 0142 00BF     		.align	2
+ 10746              	.L757:
+ 10747 0144 00000140 		.word	1073807360
+ 10748 0148 00040140 		.word	1073808384
+ 10749 014c 07000100 		.word	65543
+ 10750              		.cfi_endproc
+ 10751              	.LFE165:
+ 10753              		.section	.text.HAL_TIM_PWM_Stop,"ax",%progbits
+ 10754              		.align	1
+ 10755              		.global	HAL_TIM_PWM_Stop
+ 10756              		.syntax unified
+ 10757              		.thumb
+ 10758              		.thumb_func
+ 10759              		.fpu fpv5-d16
+ 10761              	HAL_TIM_PWM_Stop:
+ 10762              	.LVL832:
+ 10763              	.LFB166:
+1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 10764              		.loc 1 1520 1 is_stmt 1 view -0
+ 10765              		.cfi_startproc
+ 10766              		@ args = 0, pretend = 0, frame = 0
+ 10767              		@ frame_needed = 0, uses_anonymous_args = 0
+1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 10768              		.loc 1 1520 1 is_stmt 0 view .LVU3360
+ 10769 0000 38B5     		push	{r3, r4, r5, lr}
+ 10770              	.LCFI93:
+ 10771              		.cfi_def_cfa_offset 16
+ 10772              		.cfi_offset 3, -16
+ 10773              		.cfi_offset 4, -12
+ 10774              		.cfi_offset 5, -8
+ 10775              		.cfi_offset 14, -4
+ 10776 0002 0446     		mov	r4, r0
+ 10777 0004 0D46     		mov	r5, r1
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10778              		.loc 1 1522 3 is_stmt 1 view .LVU3361
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 376
+
+
+ 10779              		.loc 1 1525 3 view .LVU3362
+ 10780 0006 0022     		movs	r2, #0
+ 10781 0008 0068     		ldr	r0, [r0]
+ 10782              	.LVL833:
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10783              		.loc 1 1525 3 is_stmt 0 view .LVU3363
+ 10784 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 10785              	.LVL834:
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10786              		.loc 1 1527 3 is_stmt 1 view .LVU3364
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10787              		.loc 1 1527 7 is_stmt 0 view .LVU3365
+ 10788 000e 2368     		ldr	r3, [r4]
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10789              		.loc 1 1527 6 view .LVU3366
+ 10790 0010 2249     		ldr	r1, .L773
+ 10791 0012 234A     		ldr	r2, .L773+4
+ 10792 0014 9342     		cmp	r3, r2
+ 10793 0016 18BF     		it	ne
+ 10794 0018 8B42     		cmpne	r3, r1
+ 10795 001a 0DD1     		bne	.L760
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10796              		.loc 1 1530 5 is_stmt 1 view .LVU3367
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10797              		.loc 1 1530 5 view .LVU3368
+ 10798 001c 196A     		ldr	r1, [r3, #32]
+ 10799 001e 41F21112 		movw	r2, #4369
+ 10800 0022 1142     		tst	r1, r2
+ 10801 0024 08D1     		bne	.L760
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10802              		.loc 1 1530 5 discriminator 1 view .LVU3369
+ 10803 0026 196A     		ldr	r1, [r3, #32]
+ 10804 0028 40F24442 		movw	r2, #1092
+ 10805 002c 1142     		tst	r1, r2
+ 10806 002e 03D1     		bne	.L760
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10807              		.loc 1 1530 5 discriminator 3 view .LVU3370
+ 10808 0030 5A6C     		ldr	r2, [r3, #68]
+ 10809 0032 22F40042 		bic	r2, r2, #32768
+ 10810 0036 5A64     		str	r2, [r3, #68]
+ 10811              	.L760:
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 10812              		.loc 1 1530 5 discriminator 5 view .LVU3371
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10813              		.loc 1 1534 3 discriminator 5 view .LVU3372
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10814              		.loc 1 1534 3 discriminator 5 view .LVU3373
+ 10815 0038 2368     		ldr	r3, [r4]
+ 10816 003a 196A     		ldr	r1, [r3, #32]
+ 10817 003c 41F21112 		movw	r2, #4369
+ 10818 0040 1142     		tst	r1, r2
+ 10819 0042 08D1     		bne	.L761
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10820              		.loc 1 1534 3 discriminator 1 view .LVU3374
+ 10821 0044 196A     		ldr	r1, [r3, #32]
+ 10822 0046 40F24442 		movw	r2, #1092
+ 10823 004a 1142     		tst	r1, r2
+ARM GAS  /tmp/ccPLZXyC.s 			page 377
+
+
+ 10824 004c 03D1     		bne	.L761
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10825              		.loc 1 1534 3 discriminator 3 view .LVU3375
+ 10826 004e 1A68     		ldr	r2, [r3]
+ 10827 0050 22F00102 		bic	r2, r2, #1
+ 10828 0054 1A60     		str	r2, [r3]
+ 10829              	.L761:
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10830              		.loc 1 1534 3 discriminator 5 view .LVU3376
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10831              		.loc 1 1537 3 discriminator 5 view .LVU3377
+ 10832 0056 25B9     		cbnz	r5, .L762
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10833              		.loc 1 1537 3 is_stmt 0 discriminator 1 view .LVU3378
+ 10834 0058 0123     		movs	r3, #1
+ 10835 005a 84F83E30 		strb	r3, [r4, #62]
+ 10836              	.L763:
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 10837              		.loc 1 1540 3 is_stmt 1 view .LVU3379
+1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10838              		.loc 1 1541 1 is_stmt 0 view .LVU3380
+ 10839 005e 0020     		movs	r0, #0
+ 10840 0060 38BD     		pop	{r3, r4, r5, pc}
+ 10841              	.LVL835:
+ 10842              	.L762:
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10843              		.loc 1 1537 3 discriminator 2 view .LVU3381
+ 10844 0062 042D     		cmp	r5, #4
+ 10845 0064 09D0     		beq	.L769
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10846              		.loc 1 1537 3 discriminator 4 view .LVU3382
+ 10847 0066 082D     		cmp	r5, #8
+ 10848 0068 0BD0     		beq	.L770
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10849              		.loc 1 1537 3 discriminator 7 view .LVU3383
+ 10850 006a 0C2D     		cmp	r5, #12
+ 10851 006c 0DD0     		beq	.L771
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10852              		.loc 1 1537 3 discriminator 10 view .LVU3384
+ 10853 006e 102D     		cmp	r5, #16
+ 10854 0070 0FD0     		beq	.L772
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10855              		.loc 1 1537 3 discriminator 13 view .LVU3385
+ 10856 0072 0123     		movs	r3, #1
+ 10857 0074 84F84330 		strb	r3, [r4, #67]
+ 10858 0078 F1E7     		b	.L763
+ 10859              	.L769:
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10860              		.loc 1 1537 3 discriminator 3 view .LVU3386
+ 10861 007a 0123     		movs	r3, #1
+ 10862 007c 84F83F30 		strb	r3, [r4, #63]
+ 10863 0080 EDE7     		b	.L763
+ 10864              	.L770:
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10865              		.loc 1 1537 3 discriminator 6 view .LVU3387
+ 10866 0082 0123     		movs	r3, #1
+ 10867 0084 84F84030 		strb	r3, [r4, #64]
+ARM GAS  /tmp/ccPLZXyC.s 			page 378
+
+
+ 10868 0088 E9E7     		b	.L763
+ 10869              	.L771:
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10870              		.loc 1 1537 3 discriminator 9 view .LVU3388
+ 10871 008a 0123     		movs	r3, #1
+ 10872 008c 84F84130 		strb	r3, [r4, #65]
+ 10873 0090 E5E7     		b	.L763
+ 10874              	.L772:
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10875              		.loc 1 1537 3 discriminator 12 view .LVU3389
+ 10876 0092 0123     		movs	r3, #1
+ 10877 0094 84F84230 		strb	r3, [r4, #66]
+ 10878 0098 E1E7     		b	.L763
+ 10879              	.L774:
+ 10880 009a 00BF     		.align	2
+ 10881              	.L773:
+ 10882 009c 00000140 		.word	1073807360
+ 10883 00a0 00040140 		.word	1073808384
+ 10884              		.cfi_endproc
+ 10885              	.LFE166:
+ 10887              		.section	.text.HAL_TIM_PWM_Start_IT,"ax",%progbits
+ 10888              		.align	1
+ 10889              		.global	HAL_TIM_PWM_Start_IT
+ 10890              		.syntax unified
+ 10891              		.thumb
+ 10892              		.thumb_func
+ 10893              		.fpu fpv5-d16
+ 10895              	HAL_TIM_PWM_Start_IT:
+ 10896              	.LVL836:
+ 10897              	.LFB167:
+1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 10898              		.loc 1 1555 1 is_stmt 1 view -0
+ 10899              		.cfi_startproc
+ 10900              		@ args = 0, pretend = 0, frame = 0
+ 10901              		@ frame_needed = 0, uses_anonymous_args = 0
+1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 10902              		.loc 1 1555 1 is_stmt 0 view .LVU3391
+ 10903 0000 10B5     		push	{r4, lr}
+ 10904              	.LCFI94:
+ 10905              		.cfi_def_cfa_offset 8
+ 10906              		.cfi_offset 4, -8
+ 10907              		.cfi_offset 14, -4
+ 10908 0002 0446     		mov	r4, r0
+1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 10909              		.loc 1 1556 3 is_stmt 1 view .LVU3392
+ 10910              	.LVL837:
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10911              		.loc 1 1557 3 view .LVU3393
+1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10912              		.loc 1 1560 3 view .LVU3394
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10913              		.loc 1 1563 3 view .LVU3395
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10914              		.loc 1 1563 44 is_stmt 0 view .LVU3396
+ 10915 0004 0846     		mov	r0, r1
+ 10916              	.LVL838:
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 379
+
+
+ 10917              		.loc 1 1563 44 view .LVU3397
+ 10918 0006 C9B9     		cbnz	r1, .L776
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10919              		.loc 1 1563 7 discriminator 1 view .LVU3398
+ 10920 0008 94F83E30 		ldrb	r3, [r4, #62]	@ zero_extendqisi2
+ 10921 000c DBB2     		uxtb	r3, r3
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10922              		.loc 1 1563 44 discriminator 1 view .LVU3399
+ 10923 000e 013B     		subs	r3, r3, #1
+ 10924 0010 18BF     		it	ne
+ 10925 0012 0123     		movne	r3, #1
+ 10926              	.L777:
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10927              		.loc 1 1563 6 discriminator 20 view .LVU3400
+ 10928 0014 002B     		cmp	r3, #0
+ 10929 0016 40F0B280 		bne	.L798
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10930              		.loc 1 1569 3 is_stmt 1 view .LVU3401
+ 10931 001a 0028     		cmp	r0, #0
+ 10932 001c 39D1     		bne	.L783
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 10933              		.loc 1 1569 3 is_stmt 0 discriminator 1 view .LVU3402
+ 10934 001e 0223     		movs	r3, #2
+ 10935 0020 84F83E30 		strb	r3, [r4, #62]
+ 10936              	.L784:
+1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10937              		.loc 1 1571 3 is_stmt 1 view .LVU3403
+ 10938 0024 0C28     		cmp	r0, #12
+ 10939 0026 00F2AC80 		bhi	.L799
+ 10940 002a DFE800F0 		tbb	[pc, r0]
+ 10941              	.L790:
+ 10942 002e 4E       		.byte	(.L793-.L790)/2
+ 10943 002f AA       		.byte	(.L799-.L790)/2
+ 10944 0030 AA       		.byte	(.L799-.L790)/2
+ 10945 0031 AA       		.byte	(.L799-.L790)/2
+ 10946 0032 88       		.byte	(.L792-.L790)/2
+ 10947 0033 AA       		.byte	(.L799-.L790)/2
+ 10948 0034 AA       		.byte	(.L799-.L790)/2
+ 10949 0035 AA       		.byte	(.L799-.L790)/2
+ 10950 0036 8E       		.byte	(.L791-.L790)/2
+ 10951 0037 AA       		.byte	(.L799-.L790)/2
+ 10952 0038 AA       		.byte	(.L799-.L790)/2
+ 10953 0039 AA       		.byte	(.L799-.L790)/2
+ 10954 003a 94       		.byte	(.L789-.L790)/2
+ 10955 003b 00       		.p2align 1
+ 10956              	.L776:
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10957              		.loc 1 1563 44 is_stmt 0 discriminator 2 view .LVU3404
+ 10958 003c 0429     		cmp	r1, #4
+ 10959 003e 0CD0     		beq	.L802
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10960              		.loc 1 1563 44 discriminator 5 view .LVU3405
+ 10961 0040 0829     		cmp	r1, #8
+ 10962 0042 11D0     		beq	.L803
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10963              		.loc 1 1563 44 discriminator 8 view .LVU3406
+ 10964 0044 0C29     		cmp	r1, #12
+ARM GAS  /tmp/ccPLZXyC.s 			page 380
+
+
+ 10965 0046 16D0     		beq	.L804
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10966              		.loc 1 1563 44 discriminator 11 view .LVU3407
+ 10967 0048 1029     		cmp	r1, #16
+ 10968 004a 1BD0     		beq	.L805
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10969              		.loc 1 1563 7 discriminator 14 view .LVU3408
+ 10970 004c 94F84330 		ldrb	r3, [r4, #67]	@ zero_extendqisi2
+ 10971 0050 DBB2     		uxtb	r3, r3
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10972              		.loc 1 1563 44 discriminator 14 view .LVU3409
+ 10973 0052 013B     		subs	r3, r3, #1
+ 10974 0054 18BF     		it	ne
+ 10975 0056 0123     		movne	r3, #1
+ 10976 0058 DCE7     		b	.L777
+ 10977              	.L802:
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10978              		.loc 1 1563 7 discriminator 4 view .LVU3410
+ 10979 005a 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 10980 005e DBB2     		uxtb	r3, r3
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10981              		.loc 1 1563 44 discriminator 4 view .LVU3411
+ 10982 0060 013B     		subs	r3, r3, #1
+ 10983 0062 18BF     		it	ne
+ 10984 0064 0123     		movne	r3, #1
+ 10985 0066 D5E7     		b	.L777
+ 10986              	.L803:
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10987              		.loc 1 1563 7 discriminator 7 view .LVU3412
+ 10988 0068 94F84030 		ldrb	r3, [r4, #64]	@ zero_extendqisi2
+ 10989 006c DBB2     		uxtb	r3, r3
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10990              		.loc 1 1563 44 discriminator 7 view .LVU3413
+ 10991 006e 013B     		subs	r3, r3, #1
+ 10992 0070 18BF     		it	ne
+ 10993 0072 0123     		movne	r3, #1
+ 10994 0074 CEE7     		b	.L777
+ 10995              	.L804:
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10996              		.loc 1 1563 7 discriminator 10 view .LVU3414
+ 10997 0076 94F84130 		ldrb	r3, [r4, #65]	@ zero_extendqisi2
+ 10998 007a DBB2     		uxtb	r3, r3
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 10999              		.loc 1 1563 44 discriminator 10 view .LVU3415
+ 11000 007c 013B     		subs	r3, r3, #1
+ 11001 007e 18BF     		it	ne
+ 11002 0080 0123     		movne	r3, #1
+ 11003 0082 C7E7     		b	.L777
+ 11004              	.L805:
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11005              		.loc 1 1563 7 discriminator 13 view .LVU3416
+ 11006 0084 94F84230 		ldrb	r3, [r4, #66]	@ zero_extendqisi2
+ 11007 0088 DBB2     		uxtb	r3, r3
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11008              		.loc 1 1563 44 discriminator 13 view .LVU3417
+ 11009 008a 013B     		subs	r3, r3, #1
+ 11010 008c 18BF     		it	ne
+ARM GAS  /tmp/ccPLZXyC.s 			page 381
+
+
+ 11011 008e 0123     		movne	r3, #1
+ 11012 0090 C0E7     		b	.L777
+ 11013              	.LVL839:
+ 11014              	.L783:
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11015              		.loc 1 1569 3 discriminator 2 view .LVU3418
+ 11016 0092 0428     		cmp	r0, #4
+ 11017 0094 09D0     		beq	.L806
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11018              		.loc 1 1569 3 discriminator 4 view .LVU3419
+ 11019 0096 0828     		cmp	r0, #8
+ 11020 0098 0BD0     		beq	.L807
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11021              		.loc 1 1569 3 discriminator 7 view .LVU3420
+ 11022 009a 0C28     		cmp	r0, #12
+ 11023 009c 0DD0     		beq	.L808
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11024              		.loc 1 1569 3 discriminator 10 view .LVU3421
+ 11025 009e 1028     		cmp	r0, #16
+ 11026 00a0 0FD0     		beq	.L809
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11027              		.loc 1 1569 3 discriminator 13 view .LVU3422
+ 11028 00a2 0223     		movs	r3, #2
+ 11029 00a4 84F84330 		strb	r3, [r4, #67]
+ 11030 00a8 BCE7     		b	.L784
+ 11031              	.L806:
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11032              		.loc 1 1569 3 discriminator 3 view .LVU3423
+ 11033 00aa 0223     		movs	r3, #2
+ 11034 00ac 84F83F30 		strb	r3, [r4, #63]
+ 11035 00b0 B8E7     		b	.L784
+ 11036              	.L807:
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11037              		.loc 1 1569 3 discriminator 6 view .LVU3424
+ 11038 00b2 0223     		movs	r3, #2
+ 11039 00b4 84F84030 		strb	r3, [r4, #64]
+ 11040 00b8 B4E7     		b	.L784
+ 11041              	.L808:
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11042              		.loc 1 1569 3 discriminator 9 view .LVU3425
+ 11043 00ba 0223     		movs	r3, #2
+ 11044 00bc 84F84130 		strb	r3, [r4, #65]
+ 11045 00c0 B0E7     		b	.L784
+ 11046              	.L809:
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11047              		.loc 1 1569 3 discriminator 12 view .LVU3426
+ 11048 00c2 0223     		movs	r3, #2
+ 11049 00c4 84F84230 		strb	r3, [r4, #66]
+ 11050 00c8 ACE7     		b	.L784
+ 11051              	.L793:
+1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11052              		.loc 1 1576 7 is_stmt 1 view .LVU3427
+ 11053 00ca 2268     		ldr	r2, [r4]
+ 11054 00cc D368     		ldr	r3, [r2, #12]
+ 11055 00ce 43F00203 		orr	r3, r3, #2
+ 11056 00d2 D360     		str	r3, [r2, #12]
+1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ARM GAS  /tmp/ccPLZXyC.s 			page 382
+
+
+ 11057              		.loc 1 1577 7 view .LVU3428
+1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11058              		.loc 1 1606 3 view .LVU3429
+ 11059              	.L794:
+1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11060              		.loc 1 1609 5 view .LVU3430
+ 11061 00d4 0122     		movs	r2, #1
+ 11062 00d6 0146     		mov	r1, r0
+ 11063 00d8 2068     		ldr	r0, [r4]
+ 11064              	.LVL840:
+1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11065              		.loc 1 1609 5 is_stmt 0 view .LVU3431
+ 11066 00da FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 11067              	.LVL841:
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11068              		.loc 1 1611 5 is_stmt 1 view .LVU3432
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11069              		.loc 1 1611 9 is_stmt 0 view .LVU3433
+ 11070 00de 2368     		ldr	r3, [r4]
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11071              		.loc 1 1611 8 view .LVU3434
+ 11072 00e0 2A49     		ldr	r1, .L810
+ 11073 00e2 2B4A     		ldr	r2, .L810+4
+ 11074 00e4 9342     		cmp	r3, r2
+ 11075 00e6 18BF     		it	ne
+ 11076 00e8 8B42     		cmpne	r3, r1
+ 11077 00ea 03D1     		bne	.L795
+1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11078              		.loc 1 1614 7 is_stmt 1 view .LVU3435
+ 11079 00ec 5A6C     		ldr	r2, [r3, #68]
+ 11080 00ee 42F40042 		orr	r2, r2, #32768
+ 11081 00f2 5A64     		str	r2, [r3, #68]
+ 11082              	.L795:
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11083              		.loc 1 1618 5 view .LVU3436
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11084              		.loc 1 1618 9 is_stmt 0 view .LVU3437
+ 11085 00f4 2368     		ldr	r3, [r4]
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11086              		.loc 1 1618 8 view .LVU3438
+ 11087 00f6 254A     		ldr	r2, .L810
+ 11088 00f8 B3F1804F 		cmp	r3, #1073741824
+ 11089 00fc 18BF     		it	ne
+ 11090 00fe 9342     		cmpne	r3, r2
+ 11091 0100 2FD0     		beq	.L796
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11092              		.loc 1 1618 9 discriminator 1 view .LVU3439
+ 11093 0102 A2F57C42 		sub	r2, r2, #64512
+ 11094 0106 9342     		cmp	r3, r2
+ 11095 0108 2BD0     		beq	.L796
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11096              		.loc 1 1618 9 discriminator 2 view .LVU3440
+ 11097 010a 02F58062 		add	r2, r2, #1024
+ 11098 010e 9342     		cmp	r3, r2
+ 11099 0110 27D0     		beq	.L796
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11100              		.loc 1 1618 9 discriminator 3 view .LVU3441
+ARM GAS  /tmp/ccPLZXyC.s 			page 383
+
+
+ 11101 0112 02F58062 		add	r2, r2, #1024
+ 11102 0116 9342     		cmp	r3, r2
+ 11103 0118 23D0     		beq	.L796
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11104              		.loc 1 1618 9 discriminator 4 view .LVU3442
+ 11105 011a 02F57842 		add	r2, r2, #63488
+ 11106 011e 9342     		cmp	r3, r2
+ 11107 0120 1FD0     		beq	.L796
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11108              		.loc 1 1618 9 discriminator 5 view .LVU3443
+ 11109 0122 02F57052 		add	r2, r2, #15360
+ 11110 0126 9342     		cmp	r3, r2
+ 11111 0128 1BD0     		beq	.L796
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11112              		.loc 1 1618 9 discriminator 6 view .LVU3444
+ 11113 012a A2F59432 		sub	r2, r2, #75776
+ 11114 012e 9342     		cmp	r3, r2
+ 11115 0130 17D0     		beq	.L796
+1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11116              		.loc 1 1628 7 is_stmt 1 view .LVU3445
+ 11117 0132 1A68     		ldr	r2, [r3]
+ 11118 0134 42F00102 		orr	r2, r2, #1
+ 11119 0138 1A60     		str	r2, [r3]
+ 11120 013a 0020     		movs	r0, #0
+ 11121 013c 22E0     		b	.L782
+ 11122              	.LVL842:
+ 11123              	.L792:
+1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11124              		.loc 1 1583 7 view .LVU3446
+ 11125 013e 2268     		ldr	r2, [r4]
+ 11126 0140 D368     		ldr	r3, [r2, #12]
+ 11127 0142 43F00403 		orr	r3, r3, #4
+ 11128 0146 D360     		str	r3, [r2, #12]
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11129              		.loc 1 1584 7 view .LVU3447
+1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11130              		.loc 1 1606 3 view .LVU3448
+ 11131 0148 C4E7     		b	.L794
+ 11132              	.L791:
+1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11133              		.loc 1 1590 7 view .LVU3449
+ 11134 014a 2268     		ldr	r2, [r4]
+ 11135 014c D368     		ldr	r3, [r2, #12]
+ 11136 014e 43F00803 		orr	r3, r3, #8
+ 11137 0152 D360     		str	r3, [r2, #12]
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11138              		.loc 1 1591 7 view .LVU3450
+1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11139              		.loc 1 1606 3 view .LVU3451
+ 11140 0154 BEE7     		b	.L794
+ 11141              	.L789:
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11142              		.loc 1 1597 7 view .LVU3452
+ 11143 0156 2268     		ldr	r2, [r4]
+ 11144 0158 D368     		ldr	r3, [r2, #12]
+ 11145 015a 43F01003 		orr	r3, r3, #16
+ 11146 015e D360     		str	r3, [r2, #12]
+ARM GAS  /tmp/ccPLZXyC.s 			page 384
+
+
+1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11147              		.loc 1 1598 7 view .LVU3453
+1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11148              		.loc 1 1606 3 view .LVU3454
+ 11149 0160 B8E7     		b	.L794
+ 11150              	.LVL843:
+ 11151              	.L796:
+1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11152              		.loc 1 1620 7 view .LVU3455
+1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11153              		.loc 1 1620 31 is_stmt 0 view .LVU3456
+ 11154 0162 9968     		ldr	r1, [r3, #8]
+1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11155              		.loc 1 1620 15 view .LVU3457
+ 11156 0164 0B4A     		ldr	r2, .L810+8
+ 11157 0166 0A40     		ands	r2, r2, r1
+ 11158              	.LVL844:
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 11159              		.loc 1 1621 7 is_stmt 1 view .LVU3458
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 11160              		.loc 1 1621 10 is_stmt 0 view .LVU3459
+ 11161 0168 062A     		cmp	r2, #6
+ 11162 016a 18BF     		it	ne
+ 11163 016c B2F5803F 		cmpne	r2, #65536
+ 11164 0170 09D0     		beq	.L800
+1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 11165              		.loc 1 1623 9 is_stmt 1 view .LVU3460
+ 11166 0172 1A68     		ldr	r2, [r3]
+ 11167              	.LVL845:
+1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 11168              		.loc 1 1623 9 is_stmt 0 view .LVU3461
+ 11169 0174 42F00102 		orr	r2, r2, #1
+ 11170 0178 1A60     		str	r2, [r3]
+ 11171 017a 0020     		movs	r0, #0
+ 11172 017c 02E0     		b	.L782
+ 11173              	.LVL846:
+ 11174              	.L798:
+1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11175              		.loc 1 1565 12 view .LVU3462
+ 11176 017e 0120     		movs	r0, #1
+ 11177              	.LVL847:
+1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11178              		.loc 1 1565 12 view .LVU3463
+ 11179 0180 00E0     		b	.L782
+ 11180              	.LVL848:
+ 11181              	.L799:
+1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11182              		.loc 1 1571 3 view .LVU3464
+ 11183 0182 0120     		movs	r0, #1
+ 11184              	.LVL849:
+ 11185              	.L782:
+1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11186              		.loc 1 1634 1 view .LVU3465
+ 11187 0184 10BD     		pop	{r4, pc}
+ 11188              	.LVL850:
+ 11189              	.L800:
+1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 385
+
+
+ 11190              		.loc 1 1634 1 view .LVU3466
+ 11191 0186 0020     		movs	r0, #0
+ 11192 0188 FCE7     		b	.L782
+ 11193              	.L811:
+ 11194 018a 00BF     		.align	2
+ 11195              	.L810:
+ 11196 018c 00000140 		.word	1073807360
+ 11197 0190 00040140 		.word	1073808384
+ 11198 0194 07000100 		.word	65543
+ 11199              		.cfi_endproc
+ 11200              	.LFE167:
+ 11202              		.section	.text.HAL_TIM_PWM_Stop_IT,"ax",%progbits
+ 11203              		.align	1
+ 11204              		.global	HAL_TIM_PWM_Stop_IT
+ 11205              		.syntax unified
+ 11206              		.thumb
+ 11207              		.thumb_func
+ 11208              		.fpu fpv5-d16
+ 11210              	HAL_TIM_PWM_Stop_IT:
+ 11211              	.LVL851:
+ 11212              	.LFB168:
+1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 11213              		.loc 1 1648 1 is_stmt 1 view -0
+ 11214              		.cfi_startproc
+ 11215              		@ args = 0, pretend = 0, frame = 0
+ 11216              		@ frame_needed = 0, uses_anonymous_args = 0
+1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 11217              		.loc 1 1648 1 is_stmt 0 view .LVU3468
+ 11218 0000 38B5     		push	{r3, r4, r5, lr}
+ 11219              	.LCFI95:
+ 11220              		.cfi_def_cfa_offset 16
+ 11221              		.cfi_offset 3, -16
+ 11222              		.cfi_offset 4, -12
+ 11223              		.cfi_offset 5, -8
+ 11224              		.cfi_offset 14, -4
+ 11225 0002 0546     		mov	r5, r0
+ 11226 0004 0C46     		mov	r4, r1
+1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11227              		.loc 1 1649 3 is_stmt 1 view .LVU3469
+ 11228              	.LVL852:
+1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11229              		.loc 1 1652 3 view .LVU3470
+1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11230              		.loc 1 1654 3 view .LVU3471
+ 11231 0006 0C29     		cmp	r1, #12
+ 11232 0008 6FD8     		bhi	.L827
+ 11233 000a DFE801F0 		tbb	[pc, r1]
+ 11234              	.L815:
+ 11235 000e 07       		.byte	(.L818-.L815)/2
+ 11236 000f 6E       		.byte	(.L827-.L815)/2
+ 11237 0010 6E       		.byte	(.L827-.L815)/2
+ 11238 0011 6E       		.byte	(.L827-.L815)/2
+ 11239 0012 3B       		.byte	(.L817-.L815)/2
+ 11240 0013 6E       		.byte	(.L827-.L815)/2
+ 11241 0014 6E       		.byte	(.L827-.L815)/2
+ 11242 0015 6E       		.byte	(.L827-.L815)/2
+ 11243 0016 41       		.byte	(.L816-.L815)/2
+ARM GAS  /tmp/ccPLZXyC.s 			page 386
+
+
+ 11244 0017 6E       		.byte	(.L827-.L815)/2
+ 11245 0018 6E       		.byte	(.L827-.L815)/2
+ 11246 0019 6E       		.byte	(.L827-.L815)/2
+ 11247 001a 47       		.byte	(.L814-.L815)/2
+ 11248 001b 00       		.p2align 1
+ 11249              	.L818:
+1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11250              		.loc 1 1659 7 view .LVU3472
+ 11251 001c 0268     		ldr	r2, [r0]
+ 11252 001e D368     		ldr	r3, [r2, #12]
+ 11253 0020 23F00203 		bic	r3, r3, #2
+ 11254 0024 D360     		str	r3, [r2, #12]
+1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11255              		.loc 1 1660 7 view .LVU3473
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11256              		.loc 1 1689 3 view .LVU3474
+ 11257              	.L819:
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11258              		.loc 1 1692 5 view .LVU3475
+ 11259 0026 0022     		movs	r2, #0
+ 11260 0028 2146     		mov	r1, r4
+ 11261              	.LVL853:
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11262              		.loc 1 1692 5 is_stmt 0 view .LVU3476
+ 11263 002a 2868     		ldr	r0, [r5]
+ 11264              	.LVL854:
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11265              		.loc 1 1692 5 view .LVU3477
+ 11266 002c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 11267              	.LVL855:
+1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11268              		.loc 1 1694 5 is_stmt 1 view .LVU3478
+1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11269              		.loc 1 1694 9 is_stmt 0 view .LVU3479
+ 11270 0030 2B68     		ldr	r3, [r5]
+1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11271              		.loc 1 1694 8 view .LVU3480
+ 11272 0032 2F49     		ldr	r1, .L833
+ 11273 0034 2F4A     		ldr	r2, .L833+4
+ 11274 0036 9342     		cmp	r3, r2
+ 11275 0038 18BF     		it	ne
+ 11276 003a 8B42     		cmpne	r3, r1
+ 11277 003c 0DD1     		bne	.L820
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11278              		.loc 1 1697 7 is_stmt 1 view .LVU3481
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11279              		.loc 1 1697 7 view .LVU3482
+ 11280 003e 196A     		ldr	r1, [r3, #32]
+ 11281 0040 41F21112 		movw	r2, #4369
+ 11282 0044 1142     		tst	r1, r2
+ 11283 0046 08D1     		bne	.L820
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11284              		.loc 1 1697 7 discriminator 1 view .LVU3483
+ 11285 0048 196A     		ldr	r1, [r3, #32]
+ 11286 004a 40F24442 		movw	r2, #1092
+ 11287 004e 1142     		tst	r1, r2
+ 11288 0050 03D1     		bne	.L820
+ARM GAS  /tmp/ccPLZXyC.s 			page 387
+
+
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11289              		.loc 1 1697 7 discriminator 3 view .LVU3484
+ 11290 0052 5A6C     		ldr	r2, [r3, #68]
+ 11291 0054 22F40042 		bic	r2, r2, #32768
+ 11292 0058 5A64     		str	r2, [r3, #68]
+ 11293              	.L820:
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11294              		.loc 1 1697 7 discriminator 5 view .LVU3485
+1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11295              		.loc 1 1701 5 discriminator 5 view .LVU3486
+1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11296              		.loc 1 1701 5 discriminator 5 view .LVU3487
+ 11297 005a 2B68     		ldr	r3, [r5]
+ 11298 005c 196A     		ldr	r1, [r3, #32]
+ 11299 005e 41F21112 		movw	r2, #4369
+ 11300 0062 1142     		tst	r1, r2
+ 11301 0064 08D1     		bne	.L821
+1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11302              		.loc 1 1701 5 discriminator 1 view .LVU3488
+ 11303 0066 196A     		ldr	r1, [r3, #32]
+ 11304 0068 40F24442 		movw	r2, #1092
+ 11305 006c 1142     		tst	r1, r2
+ 11306 006e 03D1     		bne	.L821
+1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11307              		.loc 1 1701 5 discriminator 3 view .LVU3489
+ 11308 0070 1A68     		ldr	r2, [r3]
+ 11309 0072 22F00102 		bic	r2, r2, #1
+ 11310 0076 1A60     		str	r2, [r3]
+ 11311              	.L821:
+1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11312              		.loc 1 1701 5 discriminator 5 view .LVU3490
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11313              		.loc 1 1704 5 discriminator 5 view .LVU3491
+ 11314 0078 B4B9     		cbnz	r4, .L822
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11315              		.loc 1 1704 5 is_stmt 0 discriminator 1 view .LVU3492
+ 11316 007a 0123     		movs	r3, #1
+ 11317 007c 85F83E30 		strb	r3, [r5, #62]
+ 11318 0080 0020     		movs	r0, #0
+ 11319 0082 33E0     		b	.L813
+ 11320              	.LVL856:
+ 11321              	.L817:
+1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11322              		.loc 1 1666 7 is_stmt 1 view .LVU3493
+ 11323 0084 0268     		ldr	r2, [r0]
+ 11324 0086 D368     		ldr	r3, [r2, #12]
+ 11325 0088 23F00403 		bic	r3, r3, #4
+ 11326 008c D360     		str	r3, [r2, #12]
+1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11327              		.loc 1 1667 7 view .LVU3494
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11328              		.loc 1 1689 3 view .LVU3495
+ 11329 008e CAE7     		b	.L819
+ 11330              	.L816:
+1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11331              		.loc 1 1673 7 view .LVU3496
+ 11332 0090 0268     		ldr	r2, [r0]
+ARM GAS  /tmp/ccPLZXyC.s 			page 388
+
+
+ 11333 0092 D368     		ldr	r3, [r2, #12]
+ 11334 0094 23F00803 		bic	r3, r3, #8
+ 11335 0098 D360     		str	r3, [r2, #12]
+1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11336              		.loc 1 1674 7 view .LVU3497
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11337              		.loc 1 1689 3 view .LVU3498
+ 11338 009a C4E7     		b	.L819
+ 11339              	.L814:
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11340              		.loc 1 1680 7 view .LVU3499
+ 11341 009c 0268     		ldr	r2, [r0]
+ 11342 009e D368     		ldr	r3, [r2, #12]
+ 11343 00a0 23F01003 		bic	r3, r3, #16
+ 11344 00a4 D360     		str	r3, [r2, #12]
+1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11345              		.loc 1 1681 7 view .LVU3500
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11346              		.loc 1 1689 3 view .LVU3501
+ 11347 00a6 BEE7     		b	.L819
+ 11348              	.LVL857:
+ 11349              	.L822:
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11350              		.loc 1 1704 5 is_stmt 0 discriminator 2 view .LVU3502
+ 11351 00a8 042C     		cmp	r4, #4
+ 11352 00aa 0AD0     		beq	.L829
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11353              		.loc 1 1704 5 discriminator 4 view .LVU3503
+ 11354 00ac 082C     		cmp	r4, #8
+ 11355 00ae 0DD0     		beq	.L830
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11356              		.loc 1 1704 5 discriminator 7 view .LVU3504
+ 11357 00b0 0C2C     		cmp	r4, #12
+ 11358 00b2 10D0     		beq	.L831
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11359              		.loc 1 1704 5 discriminator 10 view .LVU3505
+ 11360 00b4 102C     		cmp	r4, #16
+ 11361 00b6 13D0     		beq	.L832
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11362              		.loc 1 1704 5 discriminator 13 view .LVU3506
+ 11363 00b8 0123     		movs	r3, #1
+ 11364 00ba 85F84330 		strb	r3, [r5, #67]
+ 11365 00be 0020     		movs	r0, #0
+ 11366 00c0 14E0     		b	.L813
+ 11367              	.L829:
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11368              		.loc 1 1704 5 discriminator 3 view .LVU3507
+ 11369 00c2 0123     		movs	r3, #1
+ 11370 00c4 85F83F30 		strb	r3, [r5, #63]
+ 11371 00c8 0020     		movs	r0, #0
+ 11372 00ca 0FE0     		b	.L813
+ 11373              	.L830:
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11374              		.loc 1 1704 5 discriminator 6 view .LVU3508
+ 11375 00cc 0123     		movs	r3, #1
+ 11376 00ce 85F84030 		strb	r3, [r5, #64]
+ 11377 00d2 0020     		movs	r0, #0
+ARM GAS  /tmp/ccPLZXyC.s 			page 389
+
+
+ 11378 00d4 0AE0     		b	.L813
+ 11379              	.L831:
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11380              		.loc 1 1704 5 discriminator 9 view .LVU3509
+ 11381 00d6 0123     		movs	r3, #1
+ 11382 00d8 85F84130 		strb	r3, [r5, #65]
+ 11383 00dc 0020     		movs	r0, #0
+ 11384 00de 05E0     		b	.L813
+ 11385              	.L832:
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11386              		.loc 1 1704 5 discriminator 12 view .LVU3510
+ 11387 00e0 0123     		movs	r3, #1
+ 11388 00e2 85F84230 		strb	r3, [r5, #66]
+ 11389 00e6 0020     		movs	r0, #0
+ 11390 00e8 00E0     		b	.L813
+ 11391              	.LVL858:
+ 11392              	.L827:
+1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11393              		.loc 1 1654 3 view .LVU3511
+ 11394 00ea 0120     		movs	r0, #1
+ 11395              	.LVL859:
+ 11396              	.L813:
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 11397              		.loc 1 1708 3 is_stmt 1 view .LVU3512
+1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11398              		.loc 1 1709 1 is_stmt 0 view .LVU3513
+ 11399 00ec 38BD     		pop	{r3, r4, r5, pc}
+ 11400              	.LVL860:
+ 11401              	.L834:
+1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11402              		.loc 1 1709 1 view .LVU3514
+ 11403 00ee 00BF     		.align	2
+ 11404              	.L833:
+ 11405 00f0 00000140 		.word	1073807360
+ 11406 00f4 00040140 		.word	1073808384
+ 11407              		.cfi_endproc
+ 11408              	.LFE168:
+ 11410              		.section	.text.HAL_TIM_PWM_Start_DMA,"ax",%progbits
+ 11411              		.align	1
+ 11412              		.global	HAL_TIM_PWM_Start_DMA
+ 11413              		.syntax unified
+ 11414              		.thumb
+ 11415              		.thumb_func
+ 11416              		.fpu fpv5-d16
+ 11418              	HAL_TIM_PWM_Start_DMA:
+ 11419              	.LVL861:
+ 11420              	.LFB169:
+1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 11421              		.loc 1 1726 1 is_stmt 1 view -0
+ 11422              		.cfi_startproc
+ 11423              		@ args = 0, pretend = 0, frame = 0
+ 11424              		@ frame_needed = 0, uses_anonymous_args = 0
+1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 11425              		.loc 1 1726 1 is_stmt 0 view .LVU3516
+ 11426 0000 38B5     		push	{r3, r4, r5, lr}
+ 11427              	.LCFI96:
+ 11428              		.cfi_def_cfa_offset 16
+ARM GAS  /tmp/ccPLZXyC.s 			page 390
+
+
+ 11429              		.cfi_offset 3, -16
+ 11430              		.cfi_offset 4, -12
+ 11431              		.cfi_offset 5, -8
+ 11432              		.cfi_offset 14, -4
+ 11433 0002 0446     		mov	r4, r0
+ 11434 0004 9446     		mov	ip, r2
+1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 11435              		.loc 1 1727 3 is_stmt 1 view .LVU3517
+ 11436              	.LVL862:
+1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11437              		.loc 1 1728 3 view .LVU3518
+1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11438              		.loc 1 1731 3 view .LVU3519
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11439              		.loc 1 1734 3 view .LVU3520
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11440              		.loc 1 1734 44 is_stmt 0 view .LVU3521
+ 11441 0006 0D46     		mov	r5, r1
+ 11442 0008 0029     		cmp	r1, #0
+ 11443 000a 32D1     		bne	.L836
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11444              		.loc 1 1734 7 discriminator 1 view .LVU3522
+ 11445 000c 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 11446              	.LVL863:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11447              		.loc 1 1734 7 discriminator 1 view .LVU3523
+ 11448 0010 C0B2     		uxtb	r0, r0
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11449              		.loc 1 1734 44 discriminator 1 view .LVU3524
+ 11450 0012 0228     		cmp	r0, #2
+ 11451 0014 14BF     		ite	ne
+ 11452 0016 0020     		movne	r0, #0
+ 11453 0018 0120     		moveq	r0, #1
+ 11454              	.L837:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11455              		.loc 1 1734 6 discriminator 20 view .LVU3525
+ 11456 001a 0028     		cmp	r0, #0
+ 11457 001c 40F04381 		bne	.L864
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11458              		.loc 1 1738 8 is_stmt 1 view .LVU3526
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11459              		.loc 1 1738 49 is_stmt 0 view .LVU3527
+ 11460 0020 002D     		cmp	r5, #0
+ 11461 0022 56D1     		bne	.L843
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11462              		.loc 1 1738 12 discriminator 1 view .LVU3528
+ 11463 0024 94F83E20 		ldrb	r2, [r4, #62]	@ zero_extendqisi2
+ 11464              	.LVL864:
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11465              		.loc 1 1738 12 discriminator 1 view .LVU3529
+ 11466 0028 D2B2     		uxtb	r2, r2
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11467              		.loc 1 1738 49 discriminator 1 view .LVU3530
+ 11468 002a 012A     		cmp	r2, #1
+ 11469 002c 14BF     		ite	ne
+ 11470 002e 0022     		movne	r2, #0
+ 11471 0030 0122     		moveq	r2, #1
+ARM GAS  /tmp/ccPLZXyC.s 			page 391
+
+
+ 11472              	.L844:
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11473              		.loc 1 1738 11 discriminator 20 view .LVU3531
+ 11474 0032 002A     		cmp	r2, #0
+ 11475 0034 00F03981 		beq	.L865
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11476              		.loc 1 1740 5 is_stmt 1 view .LVU3532
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11477              		.loc 1 1740 8 is_stmt 0 view .LVU3533
+ 11478 0038 002B     		cmp	r3, #0
+ 11479 003a 18BF     		it	ne
+ 11480 003c BCF1000F 		cmpne	ip, #0
+ 11481 0040 00F03581 		beq	.L866
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11482              		.loc 1 1746 7 is_stmt 1 view .LVU3534
+ 11483 0044 002D     		cmp	r5, #0
+ 11484 0046 74D1     		bne	.L849
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11485              		.loc 1 1746 7 is_stmt 0 discriminator 1 view .LVU3535
+ 11486 0048 0222     		movs	r2, #2
+ 11487 004a 84F83E20 		strb	r2, [r4, #62]
+ 11488              	.L850:
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11489              		.loc 1 1754 3 is_stmt 1 view .LVU3536
+ 11490 004e 0C2D     		cmp	r5, #12
+ 11491 0050 00F22F81 		bhi	.L867
+ 11492 0054 DFE815F0 		tbh	[pc, r5, lsl #1]
+ 11493              	.L856:
+ 11494 0058 8900     		.2byte	(.L859-.L856)/2
+ 11495 005a 2D01     		.2byte	(.L867-.L856)/2
+ 11496 005c 2D01     		.2byte	(.L867-.L856)/2
+ 11497 005e 2D01     		.2byte	(.L867-.L856)/2
+ 11498 0060 D500     		.2byte	(.L858-.L856)/2
+ 11499 0062 2D01     		.2byte	(.L867-.L856)/2
+ 11500 0064 2D01     		.2byte	(.L867-.L856)/2
+ 11501 0066 2D01     		.2byte	(.L867-.L856)/2
+ 11502 0068 EC00     		.2byte	(.L857-.L856)/2
+ 11503 006a 2D01     		.2byte	(.L867-.L856)/2
+ 11504 006c 2D01     		.2byte	(.L867-.L856)/2
+ 11505 006e 2D01     		.2byte	(.L867-.L856)/2
+ 11506 0070 0301     		.2byte	(.L855-.L856)/2
+ 11507              	.LVL865:
+ 11508              		.p2align 1
+ 11509              	.L836:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11510              		.loc 1 1734 44 is_stmt 0 discriminator 2 view .LVU3537
+ 11511 0072 0429     		cmp	r1, #4
+ 11512 0074 0DD0     		beq	.L874
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11513              		.loc 1 1734 44 discriminator 5 view .LVU3538
+ 11514 0076 0829     		cmp	r1, #8
+ 11515 0078 13D0     		beq	.L875
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11516              		.loc 1 1734 44 discriminator 8 view .LVU3539
+ 11517 007a 0C29     		cmp	r1, #12
+ 11518 007c 19D0     		beq	.L876
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 392
+
+
+ 11519              		.loc 1 1734 44 discriminator 11 view .LVU3540
+ 11520 007e 1029     		cmp	r1, #16
+ 11521 0080 1FD0     		beq	.L877
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11522              		.loc 1 1734 7 discriminator 14 view .LVU3541
+ 11523 0082 90F84300 		ldrb	r0, [r0, #67]	@ zero_extendqisi2
+ 11524              	.LVL866:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11525              		.loc 1 1734 7 discriminator 14 view .LVU3542
+ 11526 0086 C0B2     		uxtb	r0, r0
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11527              		.loc 1 1734 44 discriminator 14 view .LVU3543
+ 11528 0088 0228     		cmp	r0, #2
+ 11529 008a 14BF     		ite	ne
+ 11530 008c 0020     		movne	r0, #0
+ 11531 008e 0120     		moveq	r0, #1
+ 11532 0090 C3E7     		b	.L837
+ 11533              	.LVL867:
+ 11534              	.L874:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11535              		.loc 1 1734 7 discriminator 4 view .LVU3544
+ 11536 0092 90F83F00 		ldrb	r0, [r0, #63]	@ zero_extendqisi2
+ 11537              	.LVL868:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11538              		.loc 1 1734 7 discriminator 4 view .LVU3545
+ 11539 0096 C0B2     		uxtb	r0, r0
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11540              		.loc 1 1734 44 discriminator 4 view .LVU3546
+ 11541 0098 0228     		cmp	r0, #2
+ 11542 009a 14BF     		ite	ne
+ 11543 009c 0020     		movne	r0, #0
+ 11544 009e 0120     		moveq	r0, #1
+ 11545 00a0 BBE7     		b	.L837
+ 11546              	.LVL869:
+ 11547              	.L875:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11548              		.loc 1 1734 7 discriminator 7 view .LVU3547
+ 11549 00a2 90F84000 		ldrb	r0, [r0, #64]	@ zero_extendqisi2
+ 11550              	.LVL870:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11551              		.loc 1 1734 7 discriminator 7 view .LVU3548
+ 11552 00a6 C0B2     		uxtb	r0, r0
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11553              		.loc 1 1734 44 discriminator 7 view .LVU3549
+ 11554 00a8 0228     		cmp	r0, #2
+ 11555 00aa 14BF     		ite	ne
+ 11556 00ac 0020     		movne	r0, #0
+ 11557 00ae 0120     		moveq	r0, #1
+ 11558 00b0 B3E7     		b	.L837
+ 11559              	.LVL871:
+ 11560              	.L876:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11561              		.loc 1 1734 7 discriminator 10 view .LVU3550
+ 11562 00b2 90F84100 		ldrb	r0, [r0, #65]	@ zero_extendqisi2
+ 11563              	.LVL872:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11564              		.loc 1 1734 7 discriminator 10 view .LVU3551
+ARM GAS  /tmp/ccPLZXyC.s 			page 393
+
+
+ 11565 00b6 C0B2     		uxtb	r0, r0
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11566              		.loc 1 1734 44 discriminator 10 view .LVU3552
+ 11567 00b8 0228     		cmp	r0, #2
+ 11568 00ba 14BF     		ite	ne
+ 11569 00bc 0020     		movne	r0, #0
+ 11570 00be 0120     		moveq	r0, #1
+ 11571 00c0 ABE7     		b	.L837
+ 11572              	.LVL873:
+ 11573              	.L877:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11574              		.loc 1 1734 7 discriminator 13 view .LVU3553
+ 11575 00c2 90F84200 		ldrb	r0, [r0, #66]	@ zero_extendqisi2
+ 11576              	.LVL874:
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11577              		.loc 1 1734 7 discriminator 13 view .LVU3554
+ 11578 00c6 C0B2     		uxtb	r0, r0
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11579              		.loc 1 1734 44 discriminator 13 view .LVU3555
+ 11580 00c8 0228     		cmp	r0, #2
+ 11581 00ca 14BF     		ite	ne
+ 11582 00cc 0020     		movne	r0, #0
+ 11583 00ce 0120     		moveq	r0, #1
+ 11584 00d0 A3E7     		b	.L837
+ 11585              	.L843:
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11586              		.loc 1 1738 49 discriminator 2 view .LVU3556
+ 11587 00d2 042D     		cmp	r5, #4
+ 11588 00d4 0DD0     		beq	.L878
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11589              		.loc 1 1738 49 discriminator 5 view .LVU3557
+ 11590 00d6 082D     		cmp	r5, #8
+ 11591 00d8 13D0     		beq	.L879
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11592              		.loc 1 1738 49 discriminator 8 view .LVU3558
+ 11593 00da 0C2D     		cmp	r5, #12
+ 11594 00dc 19D0     		beq	.L880
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11595              		.loc 1 1738 49 discriminator 11 view .LVU3559
+ 11596 00de 102D     		cmp	r5, #16
+ 11597 00e0 1FD0     		beq	.L881
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11598              		.loc 1 1738 12 discriminator 14 view .LVU3560
+ 11599 00e2 94F84320 		ldrb	r2, [r4, #67]	@ zero_extendqisi2
+ 11600              	.LVL875:
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11601              		.loc 1 1738 12 discriminator 14 view .LVU3561
+ 11602 00e6 D2B2     		uxtb	r2, r2
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11603              		.loc 1 1738 49 discriminator 14 view .LVU3562
+ 11604 00e8 012A     		cmp	r2, #1
+ 11605 00ea 14BF     		ite	ne
+ 11606 00ec 0022     		movne	r2, #0
+ 11607 00ee 0122     		moveq	r2, #1
+ 11608 00f0 9FE7     		b	.L844
+ 11609              	.LVL876:
+ 11610              	.L878:
+ARM GAS  /tmp/ccPLZXyC.s 			page 394
+
+
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11611              		.loc 1 1738 12 discriminator 4 view .LVU3563
+ 11612 00f2 94F83F20 		ldrb	r2, [r4, #63]	@ zero_extendqisi2
+ 11613              	.LVL877:
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11614              		.loc 1 1738 12 discriminator 4 view .LVU3564
+ 11615 00f6 D2B2     		uxtb	r2, r2
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11616              		.loc 1 1738 49 discriminator 4 view .LVU3565
+ 11617 00f8 012A     		cmp	r2, #1
+ 11618 00fa 14BF     		ite	ne
+ 11619 00fc 0022     		movne	r2, #0
+ 11620 00fe 0122     		moveq	r2, #1
+ 11621 0100 97E7     		b	.L844
+ 11622              	.LVL878:
+ 11623              	.L879:
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11624              		.loc 1 1738 12 discriminator 7 view .LVU3566
+ 11625 0102 94F84020 		ldrb	r2, [r4, #64]	@ zero_extendqisi2
+ 11626              	.LVL879:
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11627              		.loc 1 1738 12 discriminator 7 view .LVU3567
+ 11628 0106 D2B2     		uxtb	r2, r2
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11629              		.loc 1 1738 49 discriminator 7 view .LVU3568
+ 11630 0108 012A     		cmp	r2, #1
+ 11631 010a 14BF     		ite	ne
+ 11632 010c 0022     		movne	r2, #0
+ 11633 010e 0122     		moveq	r2, #1
+ 11634 0110 8FE7     		b	.L844
+ 11635              	.LVL880:
+ 11636              	.L880:
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11637              		.loc 1 1738 12 discriminator 10 view .LVU3569
+ 11638 0112 94F84120 		ldrb	r2, [r4, #65]	@ zero_extendqisi2
+ 11639              	.LVL881:
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11640              		.loc 1 1738 12 discriminator 10 view .LVU3570
+ 11641 0116 D2B2     		uxtb	r2, r2
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11642              		.loc 1 1738 49 discriminator 10 view .LVU3571
+ 11643 0118 012A     		cmp	r2, #1
+ 11644 011a 14BF     		ite	ne
+ 11645 011c 0022     		movne	r2, #0
+ 11646 011e 0122     		moveq	r2, #1
+ 11647 0120 87E7     		b	.L844
+ 11648              	.LVL882:
+ 11649              	.L881:
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11650              		.loc 1 1738 12 discriminator 13 view .LVU3572
+ 11651 0122 94F84220 		ldrb	r2, [r4, #66]	@ zero_extendqisi2
+ 11652              	.LVL883:
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11653              		.loc 1 1738 12 discriminator 13 view .LVU3573
+ 11654 0126 D2B2     		uxtb	r2, r2
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11655              		.loc 1 1738 49 discriminator 13 view .LVU3574
+ARM GAS  /tmp/ccPLZXyC.s 			page 395
+
+
+ 11656 0128 012A     		cmp	r2, #1
+ 11657 012a 14BF     		ite	ne
+ 11658 012c 0022     		movne	r2, #0
+ 11659 012e 0122     		moveq	r2, #1
+ 11660 0130 7FE7     		b	.L844
+ 11661              	.L849:
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11662              		.loc 1 1746 7 discriminator 2 view .LVU3575
+ 11663 0132 042D     		cmp	r5, #4
+ 11664 0134 09D0     		beq	.L882
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11665              		.loc 1 1746 7 discriminator 4 view .LVU3576
+ 11666 0136 082D     		cmp	r5, #8
+ 11667 0138 0BD0     		beq	.L883
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11668              		.loc 1 1746 7 discriminator 7 view .LVU3577
+ 11669 013a 0C2D     		cmp	r5, #12
+ 11670 013c 0DD0     		beq	.L884
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11671              		.loc 1 1746 7 discriminator 10 view .LVU3578
+ 11672 013e 102D     		cmp	r5, #16
+ 11673 0140 0FD0     		beq	.L885
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11674              		.loc 1 1746 7 discriminator 13 view .LVU3579
+ 11675 0142 0222     		movs	r2, #2
+ 11676 0144 84F84320 		strb	r2, [r4, #67]
+ 11677 0148 81E7     		b	.L850
+ 11678              	.L882:
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11679              		.loc 1 1746 7 discriminator 3 view .LVU3580
+ 11680 014a 0222     		movs	r2, #2
+ 11681 014c 84F83F20 		strb	r2, [r4, #63]
+ 11682 0150 7DE7     		b	.L850
+ 11683              	.L883:
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11684              		.loc 1 1746 7 discriminator 6 view .LVU3581
+ 11685 0152 0222     		movs	r2, #2
+ 11686 0154 84F84020 		strb	r2, [r4, #64]
+ 11687 0158 79E7     		b	.L850
+ 11688              	.L884:
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11689              		.loc 1 1746 7 discriminator 9 view .LVU3582
+ 11690 015a 0222     		movs	r2, #2
+ 11691 015c 84F84120 		strb	r2, [r4, #65]
+ 11692 0160 75E7     		b	.L850
+ 11693              	.L885:
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11694              		.loc 1 1746 7 discriminator 12 view .LVU3583
+ 11695 0162 0222     		movs	r2, #2
+ 11696 0164 84F84220 		strb	r2, [r4, #66]
+ 11697 0168 71E7     		b	.L850
+ 11698              	.L859:
+1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11699              		.loc 1 1759 7 is_stmt 1 view .LVU3584
+1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11700              		.loc 1 1759 17 is_stmt 0 view .LVU3585
+ 11701 016a 626A     		ldr	r2, [r4, #36]
+ARM GAS  /tmp/ccPLZXyC.s 			page 396
+
+
+1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11702              		.loc 1 1759 52 view .LVU3586
+ 11703 016c 5749     		ldr	r1, .L886
+ 11704              	.LVL884:
+1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11705              		.loc 1 1759 52 view .LVU3587
+ 11706 016e D163     		str	r1, [r2, #60]
+1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11707              		.loc 1 1760 7 is_stmt 1 view .LVU3588
+1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11708              		.loc 1 1760 17 is_stmt 0 view .LVU3589
+ 11709 0170 626A     		ldr	r2, [r4, #36]
+1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11710              		.loc 1 1760 56 view .LVU3590
+ 11711 0172 5749     		ldr	r1, .L886+4
+ 11712 0174 1164     		str	r1, [r2, #64]
+1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11713              		.loc 1 1763 7 is_stmt 1 view .LVU3591
+1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11714              		.loc 1 1763 17 is_stmt 0 view .LVU3592
+ 11715 0176 626A     		ldr	r2, [r4, #36]
+1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11716              		.loc 1 1763 53 view .LVU3593
+ 11717 0178 5649     		ldr	r1, .L886+8
+ 11718 017a D164     		str	r1, [r2, #76]
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11719              		.loc 1 1766 7 is_stmt 1 view .LVU3594
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11720              		.loc 1 1766 88 is_stmt 0 view .LVU3595
+ 11721 017c 2268     		ldr	r2, [r4]
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11722              		.loc 1 1766 11 view .LVU3596
+ 11723 017e 3432     		adds	r2, r2, #52
+ 11724 0180 6146     		mov	r1, ip
+ 11725 0182 606A     		ldr	r0, [r4, #36]
+ 11726 0184 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 11727              	.LVL885:
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11728              		.loc 1 1766 10 view .LVU3597
+ 11729 0188 0028     		cmp	r0, #0
+ 11730 018a 40F09480 		bne	.L868
+1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11731              		.loc 1 1774 7 is_stmt 1 view .LVU3598
+ 11732 018e 2268     		ldr	r2, [r4]
+ 11733 0190 D368     		ldr	r3, [r2, #12]
+ 11734 0192 43F40073 		orr	r3, r3, #512
+ 11735 0196 D360     		str	r3, [r2, #12]
+1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11736              		.loc 1 1775 7 view .LVU3599
+1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11737              		.loc 1 1846 3 view .LVU3600
+ 11738              	.L860:
+1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11739              		.loc 1 1849 5 view .LVU3601
+ 11740 0198 0122     		movs	r2, #1
+ 11741 019a 2946     		mov	r1, r5
+ 11742 019c 2068     		ldr	r0, [r4]
+ARM GAS  /tmp/ccPLZXyC.s 			page 397
+
+
+ 11743 019e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 11744              	.LVL886:
+1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11745              		.loc 1 1851 5 view .LVU3602
+1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11746              		.loc 1 1851 9 is_stmt 0 view .LVU3603
+ 11747 01a2 2368     		ldr	r3, [r4]
+1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11748              		.loc 1 1851 8 view .LVU3604
+ 11749 01a4 4C49     		ldr	r1, .L886+12
+ 11750 01a6 4D4A     		ldr	r2, .L886+16
+ 11751 01a8 9342     		cmp	r3, r2
+ 11752 01aa 18BF     		it	ne
+ 11753 01ac 8B42     		cmpne	r3, r1
+ 11754 01ae 03D1     		bne	.L861
+1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11755              		.loc 1 1854 7 is_stmt 1 view .LVU3605
+ 11756 01b0 5A6C     		ldr	r2, [r3, #68]
+ 11757 01b2 42F40042 		orr	r2, r2, #32768
+ 11758 01b6 5A64     		str	r2, [r3, #68]
+ 11759              	.L861:
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11760              		.loc 1 1858 5 view .LVU3606
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11761              		.loc 1 1858 9 is_stmt 0 view .LVU3607
+ 11762 01b8 2368     		ldr	r3, [r4]
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11763              		.loc 1 1858 8 view .LVU3608
+ 11764 01ba 474A     		ldr	r2, .L886+12
+ 11765 01bc B3F1804F 		cmp	r3, #1073741824
+ 11766 01c0 18BF     		it	ne
+ 11767 01c2 9342     		cmpne	r3, r2
+ 11768 01c4 61D0     		beq	.L862
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11769              		.loc 1 1858 9 discriminator 1 view .LVU3609
+ 11770 01c6 A2F57C42 		sub	r2, r2, #64512
+ 11771 01ca 9342     		cmp	r3, r2
+ 11772 01cc 5DD0     		beq	.L862
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11773              		.loc 1 1858 9 discriminator 2 view .LVU3610
+ 11774 01ce 02F58062 		add	r2, r2, #1024
+ 11775 01d2 9342     		cmp	r3, r2
+ 11776 01d4 59D0     		beq	.L862
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11777              		.loc 1 1858 9 discriminator 3 view .LVU3611
+ 11778 01d6 02F58062 		add	r2, r2, #1024
+ 11779 01da 9342     		cmp	r3, r2
+ 11780 01dc 55D0     		beq	.L862
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11781              		.loc 1 1858 9 discriminator 4 view .LVU3612
+ 11782 01de 02F57842 		add	r2, r2, #63488
+ 11783 01e2 9342     		cmp	r3, r2
+ 11784 01e4 51D0     		beq	.L862
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11785              		.loc 1 1858 9 discriminator 5 view .LVU3613
+ 11786 01e6 02F57052 		add	r2, r2, #15360
+ 11787 01ea 9342     		cmp	r3, r2
+ARM GAS  /tmp/ccPLZXyC.s 			page 398
+
+
+ 11788 01ec 4DD0     		beq	.L862
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 11789              		.loc 1 1858 9 discriminator 6 view .LVU3614
+ 11790 01ee A2F59432 		sub	r2, r2, #75776
+ 11791 01f2 9342     		cmp	r3, r2
+ 11792 01f4 49D0     		beq	.L862
+1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11793              		.loc 1 1868 7 is_stmt 1 view .LVU3615
+ 11794 01f6 1A68     		ldr	r2, [r3]
+ 11795 01f8 42F00102 		orr	r2, r2, #1
+ 11796 01fc 1A60     		str	r2, [r3]
+ 11797 01fe 0020     		movs	r0, #0
+ 11798 0200 54E0     		b	.L842
+ 11799              	.LVL887:
+ 11800              	.L858:
+1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11801              		.loc 1 1781 7 view .LVU3616
+1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11802              		.loc 1 1781 17 is_stmt 0 view .LVU3617
+ 11803 0202 A26A     		ldr	r2, [r4, #40]
+1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11804              		.loc 1 1781 52 view .LVU3618
+ 11805 0204 3149     		ldr	r1, .L886
+ 11806              	.LVL888:
+1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11807              		.loc 1 1781 52 view .LVU3619
+ 11808 0206 D163     		str	r1, [r2, #60]
+1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11809              		.loc 1 1782 7 is_stmt 1 view .LVU3620
+1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11810              		.loc 1 1782 17 is_stmt 0 view .LVU3621
+ 11811 0208 A26A     		ldr	r2, [r4, #40]
+1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11812              		.loc 1 1782 56 view .LVU3622
+ 11813 020a 3149     		ldr	r1, .L886+4
+ 11814 020c 1164     		str	r1, [r2, #64]
+1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11815              		.loc 1 1785 7 is_stmt 1 view .LVU3623
+1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11816              		.loc 1 1785 17 is_stmt 0 view .LVU3624
+ 11817 020e A26A     		ldr	r2, [r4, #40]
+1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11818              		.loc 1 1785 53 view .LVU3625
+ 11819 0210 3049     		ldr	r1, .L886+8
+ 11820 0212 D164     		str	r1, [r2, #76]
+1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11821              		.loc 1 1788 7 is_stmt 1 view .LVU3626
+1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11822              		.loc 1 1788 88 is_stmt 0 view .LVU3627
+ 11823 0214 2268     		ldr	r2, [r4]
+1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11824              		.loc 1 1788 11 view .LVU3628
+ 11825 0216 3832     		adds	r2, r2, #56
+ 11826 0218 6146     		mov	r1, ip
+ 11827 021a A06A     		ldr	r0, [r4, #40]
+ 11828 021c FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 11829              	.LVL889:
+ARM GAS  /tmp/ccPLZXyC.s 			page 399
+
+
+1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11830              		.loc 1 1788 10 view .LVU3629
+ 11831 0220 0028     		cmp	r0, #0
+ 11832 0222 4AD1     		bne	.L869
+1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11833              		.loc 1 1795 7 is_stmt 1 view .LVU3630
+ 11834 0224 2268     		ldr	r2, [r4]
+ 11835 0226 D368     		ldr	r3, [r2, #12]
+ 11836 0228 43F48063 		orr	r3, r3, #1024
+ 11837 022c D360     		str	r3, [r2, #12]
+1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11838              		.loc 1 1796 7 view .LVU3631
+1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11839              		.loc 1 1846 3 view .LVU3632
+ 11840 022e B3E7     		b	.L860
+ 11841              	.LVL890:
+ 11842              	.L857:
+1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11843              		.loc 1 1802 7 view .LVU3633
+1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11844              		.loc 1 1802 17 is_stmt 0 view .LVU3634
+ 11845 0230 E26A     		ldr	r2, [r4, #44]
+1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11846              		.loc 1 1802 52 view .LVU3635
+ 11847 0232 2649     		ldr	r1, .L886
+ 11848              	.LVL891:
+1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11849              		.loc 1 1802 52 view .LVU3636
+ 11850 0234 D163     		str	r1, [r2, #60]
+1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11851              		.loc 1 1803 7 is_stmt 1 view .LVU3637
+1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11852              		.loc 1 1803 17 is_stmt 0 view .LVU3638
+ 11853 0236 E26A     		ldr	r2, [r4, #44]
+1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11854              		.loc 1 1803 56 view .LVU3639
+ 11855 0238 2549     		ldr	r1, .L886+4
+ 11856 023a 1164     		str	r1, [r2, #64]
+1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11857              		.loc 1 1806 7 is_stmt 1 view .LVU3640
+1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11858              		.loc 1 1806 17 is_stmt 0 view .LVU3641
+ 11859 023c E26A     		ldr	r2, [r4, #44]
+1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11860              		.loc 1 1806 53 view .LVU3642
+ 11861 023e 2549     		ldr	r1, .L886+8
+ 11862 0240 D164     		str	r1, [r2, #76]
+1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11863              		.loc 1 1809 7 is_stmt 1 view .LVU3643
+1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11864              		.loc 1 1809 88 is_stmt 0 view .LVU3644
+ 11865 0242 2268     		ldr	r2, [r4]
+1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11866              		.loc 1 1809 11 view .LVU3645
+ 11867 0244 3C32     		adds	r2, r2, #60
+ 11868 0246 6146     		mov	r1, ip
+ 11869 0248 E06A     		ldr	r0, [r4, #44]
+ARM GAS  /tmp/ccPLZXyC.s 			page 400
+
+
+ 11870 024a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 11871              	.LVL892:
+1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11872              		.loc 1 1809 10 view .LVU3646
+ 11873 024e 0028     		cmp	r0, #0
+ 11874 0250 35D1     		bne	.L870
+1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11875              		.loc 1 1816 7 is_stmt 1 view .LVU3647
+ 11876 0252 2268     		ldr	r2, [r4]
+ 11877 0254 D368     		ldr	r3, [r2, #12]
+ 11878 0256 43F40063 		orr	r3, r3, #2048
+ 11879 025a D360     		str	r3, [r2, #12]
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11880              		.loc 1 1817 7 view .LVU3648
+1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11881              		.loc 1 1846 3 view .LVU3649
+ 11882 025c 9CE7     		b	.L860
+ 11883              	.LVL893:
+ 11884              	.L855:
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11885              		.loc 1 1823 7 view .LVU3650
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11886              		.loc 1 1823 17 is_stmt 0 view .LVU3651
+ 11887 025e 226B     		ldr	r2, [r4, #48]
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11888              		.loc 1 1823 52 view .LVU3652
+ 11889 0260 1A49     		ldr	r1, .L886
+ 11890              	.LVL894:
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 11891              		.loc 1 1823 52 view .LVU3653
+ 11892 0262 D163     		str	r1, [r2, #60]
+1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11893              		.loc 1 1824 7 is_stmt 1 view .LVU3654
+1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11894              		.loc 1 1824 17 is_stmt 0 view .LVU3655
+ 11895 0264 226B     		ldr	r2, [r4, #48]
+1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11896              		.loc 1 1824 56 view .LVU3656
+ 11897 0266 1A49     		ldr	r1, .L886+4
+ 11898 0268 1164     		str	r1, [r2, #64]
+1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11899              		.loc 1 1827 7 is_stmt 1 view .LVU3657
+1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11900              		.loc 1 1827 17 is_stmt 0 view .LVU3658
+ 11901 026a 226B     		ldr	r2, [r4, #48]
+1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11902              		.loc 1 1827 53 view .LVU3659
+ 11903 026c 1949     		ldr	r1, .L886+8
+ 11904 026e D164     		str	r1, [r2, #76]
+1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11905              		.loc 1 1830 7 is_stmt 1 view .LVU3660
+1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11906              		.loc 1 1830 88 is_stmt 0 view .LVU3661
+ 11907 0270 2268     		ldr	r2, [r4]
+1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11908              		.loc 1 1830 11 view .LVU3662
+ 11909 0272 4032     		adds	r2, r2, #64
+ARM GAS  /tmp/ccPLZXyC.s 			page 401
+
+
+ 11910 0274 6146     		mov	r1, ip
+ 11911 0276 206B     		ldr	r0, [r4, #48]
+ 11912 0278 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 11913              	.LVL895:
+1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 11914              		.loc 1 1830 10 view .LVU3663
+ 11915 027c 08BB     		cbnz	r0, .L871
+1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 11916              		.loc 1 1837 7 is_stmt 1 view .LVU3664
+ 11917 027e 2268     		ldr	r2, [r4]
+ 11918 0280 D368     		ldr	r3, [r2, #12]
+ 11919 0282 43F48053 		orr	r3, r3, #4096
+ 11920 0286 D360     		str	r3, [r2, #12]
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11921              		.loc 1 1838 7 view .LVU3665
+1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11922              		.loc 1 1846 3 view .LVU3666
+ 11923 0288 86E7     		b	.L860
+ 11924              	.L862:
+1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11925              		.loc 1 1860 7 view .LVU3667
+1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11926              		.loc 1 1860 31 is_stmt 0 view .LVU3668
+ 11927 028a 9968     		ldr	r1, [r3, #8]
+1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 11928              		.loc 1 1860 15 view .LVU3669
+ 11929 028c 144A     		ldr	r2, .L886+20
+ 11930 028e 0A40     		ands	r2, r2, r1
+ 11931              	.LVL896:
+1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 11932              		.loc 1 1861 7 is_stmt 1 view .LVU3670
+1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 11933              		.loc 1 1861 10 is_stmt 0 view .LVU3671
+ 11934 0290 062A     		cmp	r2, #6
+ 11935 0292 18BF     		it	ne
+ 11936 0294 B2F5803F 		cmpne	r2, #65536
+ 11937 0298 15D0     		beq	.L872
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 11938              		.loc 1 1863 9 is_stmt 1 view .LVU3672
+ 11939 029a 1A68     		ldr	r2, [r3]
+ 11940              	.LVL897:
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 11941              		.loc 1 1863 9 is_stmt 0 view .LVU3673
+ 11942 029c 42F00102 		orr	r2, r2, #1
+ 11943 02a0 1A60     		str	r2, [r3]
+ 11944 02a2 0020     		movs	r0, #0
+ 11945 02a4 02E0     		b	.L842
+ 11946              	.LVL898:
+ 11947              	.L864:
+1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11948              		.loc 1 1736 12 view .LVU3674
+ 11949 02a6 0220     		movs	r0, #2
+ 11950 02a8 00E0     		b	.L842
+ 11951              	.LVL899:
+ 11952              	.L865:
+1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 11953              		.loc 1 1751 12 view .LVU3675
+ARM GAS  /tmp/ccPLZXyC.s 			page 402
+
+
+ 11954 02aa 0120     		movs	r0, #1
+ 11955              	.LVL900:
+ 11956              	.L842:
+1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 11957              		.loc 1 1874 1 view .LVU3676
+ 11958 02ac 38BD     		pop	{r3, r4, r5, pc}
+ 11959              	.LVL901:
+ 11960              	.L866:
+1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 11961              		.loc 1 1742 14 view .LVU3677
+ 11962 02ae 0120     		movs	r0, #1
+ 11963 02b0 FCE7     		b	.L842
+ 11964              	.L867:
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 11965              		.loc 1 1754 3 view .LVU3678
+ 11966 02b2 0120     		movs	r0, #1
+ 11967 02b4 FAE7     		b	.L842
+ 11968              	.LVL902:
+ 11969              	.L868:
+1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 11970              		.loc 1 1770 16 view .LVU3679
+ 11971 02b6 0120     		movs	r0, #1
+ 11972 02b8 F8E7     		b	.L842
+ 11973              	.L869:
+1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 11974              		.loc 1 1792 16 view .LVU3680
+ 11975 02ba 0120     		movs	r0, #1
+ 11976 02bc F6E7     		b	.L842
+ 11977              	.L870:
+1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 11978              		.loc 1 1813 16 view .LVU3681
+ 11979 02be 0120     		movs	r0, #1
+ 11980 02c0 F4E7     		b	.L842
+ 11981              	.L871:
+1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 11982              		.loc 1 1834 16 view .LVU3682
+ 11983 02c2 0120     		movs	r0, #1
+ 11984 02c4 F2E7     		b	.L842
+ 11985              	.LVL903:
+ 11986              	.L872:
+1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 11987              		.loc 1 1834 16 view .LVU3683
+ 11988 02c6 0020     		movs	r0, #0
+ 11989 02c8 F0E7     		b	.L842
+ 11990              	.L887:
+ 11991 02ca 00BF     		.align	2
+ 11992              	.L886:
+ 11993 02cc 00000000 		.word	TIM_DMADelayPulseCplt
+ 11994 02d0 00000000 		.word	TIM_DMADelayPulseHalfCplt
+ 11995 02d4 00000000 		.word	TIM_DMAError
+ 11996 02d8 00000140 		.word	1073807360
+ 11997 02dc 00040140 		.word	1073808384
+ 11998 02e0 07000100 		.word	65543
+ 11999              		.cfi_endproc
+ 12000              	.LFE169:
+ 12002              		.section	.text.HAL_TIM_PWM_Stop_DMA,"ax",%progbits
+ 12003              		.align	1
+ARM GAS  /tmp/ccPLZXyC.s 			page 403
+
+
+ 12004              		.global	HAL_TIM_PWM_Stop_DMA
+ 12005              		.syntax unified
+ 12006              		.thumb
+ 12007              		.thumb_func
+ 12008              		.fpu fpv5-d16
+ 12010              	HAL_TIM_PWM_Stop_DMA:
+ 12011              	.LVL904:
+ 12012              	.LFB170:
+1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 12013              		.loc 1 1888 1 is_stmt 1 view -0
+ 12014              		.cfi_startproc
+ 12015              		@ args = 0, pretend = 0, frame = 0
+ 12016              		@ frame_needed = 0, uses_anonymous_args = 0
+1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 12017              		.loc 1 1888 1 is_stmt 0 view .LVU3685
+ 12018 0000 38B5     		push	{r3, r4, r5, lr}
+ 12019              	.LCFI97:
+ 12020              		.cfi_def_cfa_offset 16
+ 12021              		.cfi_offset 3, -16
+ 12022              		.cfi_offset 4, -12
+ 12023              		.cfi_offset 5, -8
+ 12024              		.cfi_offset 14, -4
+ 12025 0002 0446     		mov	r4, r0
+ 12026 0004 0D46     		mov	r5, r1
+1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12027              		.loc 1 1889 3 is_stmt 1 view .LVU3686
+ 12028              	.LVL905:
+1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12029              		.loc 1 1892 3 view .LVU3687
+1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12030              		.loc 1 1894 3 view .LVU3688
+ 12031 0006 0C29     		cmp	r1, #12
+ 12032 0008 7BD8     		bhi	.L903
+ 12033 000a DFE801F0 		tbb	[pc, r1]
+ 12034              	.L891:
+ 12035 000e 07       		.byte	(.L894-.L891)/2
+ 12036 000f 7A       		.byte	(.L903-.L891)/2
+ 12037 0010 7A       		.byte	(.L903-.L891)/2
+ 12038 0011 7A       		.byte	(.L903-.L891)/2
+ 12039 0012 3E       		.byte	(.L893-.L891)/2
+ 12040 0013 7A       		.byte	(.L903-.L891)/2
+ 12041 0014 7A       		.byte	(.L903-.L891)/2
+ 12042 0015 7A       		.byte	(.L903-.L891)/2
+ 12043 0016 47       		.byte	(.L892-.L891)/2
+ 12044 0017 7A       		.byte	(.L903-.L891)/2
+ 12045 0018 7A       		.byte	(.L903-.L891)/2
+ 12046 0019 7A       		.byte	(.L903-.L891)/2
+ 12047 001a 50       		.byte	(.L890-.L891)/2
+ 12048 001b 00       		.p2align 1
+ 12049              	.L894:
+1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 12050              		.loc 1 1899 7 view .LVU3689
+ 12051 001c 0268     		ldr	r2, [r0]
+ 12052 001e D368     		ldr	r3, [r2, #12]
+ 12053 0020 23F40073 		bic	r3, r3, #512
+ 12054 0024 D360     		str	r3, [r2, #12]
+1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ARM GAS  /tmp/ccPLZXyC.s 			page 404
+
+
+ 12055              		.loc 1 1900 7 view .LVU3690
+1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12056              		.loc 1 1900 13 is_stmt 0 view .LVU3691
+ 12057 0026 406A     		ldr	r0, [r0, #36]
+ 12058              	.LVL906:
+1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12059              		.loc 1 1900 13 view .LVU3692
+ 12060 0028 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 12061              	.LVL907:
+1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12062              		.loc 1 1901 7 is_stmt 1 view .LVU3693
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12063              		.loc 1 1933 3 view .LVU3694
+ 12064              	.L895:
+1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12065              		.loc 1 1936 5 view .LVU3695
+ 12066 002c 0022     		movs	r2, #0
+ 12067 002e 2946     		mov	r1, r5
+ 12068 0030 2068     		ldr	r0, [r4]
+ 12069 0032 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 12070              	.LVL908:
+1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12071              		.loc 1 1938 5 view .LVU3696
+1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12072              		.loc 1 1938 9 is_stmt 0 view .LVU3697
+ 12073 0036 2368     		ldr	r3, [r4]
+1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12074              		.loc 1 1938 8 view .LVU3698
+ 12075 0038 3349     		ldr	r1, .L909
+ 12076 003a 344A     		ldr	r2, .L909+4
+ 12077 003c 9342     		cmp	r3, r2
+ 12078 003e 18BF     		it	ne
+ 12079 0040 8B42     		cmpne	r3, r1
+ 12080 0042 0DD1     		bne	.L896
+1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12081              		.loc 1 1941 7 is_stmt 1 view .LVU3699
+1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12082              		.loc 1 1941 7 view .LVU3700
+ 12083 0044 196A     		ldr	r1, [r3, #32]
+ 12084 0046 41F21112 		movw	r2, #4369
+ 12085 004a 1142     		tst	r1, r2
+ 12086 004c 08D1     		bne	.L896
+1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12087              		.loc 1 1941 7 discriminator 1 view .LVU3701
+ 12088 004e 196A     		ldr	r1, [r3, #32]
+ 12089 0050 40F24442 		movw	r2, #1092
+ 12090 0054 1142     		tst	r1, r2
+ 12091 0056 03D1     		bne	.L896
+1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12092              		.loc 1 1941 7 discriminator 3 view .LVU3702
+ 12093 0058 5A6C     		ldr	r2, [r3, #68]
+ 12094 005a 22F40042 		bic	r2, r2, #32768
+ 12095 005e 5A64     		str	r2, [r3, #68]
+ 12096              	.L896:
+1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12097              		.loc 1 1941 7 discriminator 5 view .LVU3703
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ARM GAS  /tmp/ccPLZXyC.s 			page 405
+
+
+ 12098              		.loc 1 1945 5 discriminator 5 view .LVU3704
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12099              		.loc 1 1945 5 discriminator 5 view .LVU3705
+ 12100 0060 2368     		ldr	r3, [r4]
+ 12101 0062 196A     		ldr	r1, [r3, #32]
+ 12102 0064 41F21112 		movw	r2, #4369
+ 12103 0068 1142     		tst	r1, r2
+ 12104 006a 08D1     		bne	.L897
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12105              		.loc 1 1945 5 discriminator 1 view .LVU3706
+ 12106 006c 196A     		ldr	r1, [r3, #32]
+ 12107 006e 40F24442 		movw	r2, #1092
+ 12108 0072 1142     		tst	r1, r2
+ 12109 0074 03D1     		bne	.L897
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12110              		.loc 1 1945 5 discriminator 3 view .LVU3707
+ 12111 0076 1A68     		ldr	r2, [r3]
+ 12112 0078 22F00102 		bic	r2, r2, #1
+ 12113 007c 1A60     		str	r2, [r3]
+ 12114              	.L897:
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12115              		.loc 1 1945 5 discriminator 5 view .LVU3708
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12116              		.loc 1 1948 5 discriminator 5 view .LVU3709
+ 12117 007e FDB9     		cbnz	r5, .L898
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12118              		.loc 1 1948 5 is_stmt 0 discriminator 1 view .LVU3710
+ 12119 0080 0123     		movs	r3, #1
+ 12120 0082 84F83E30 		strb	r3, [r4, #62]
+ 12121 0086 0020     		movs	r0, #0
+ 12122 0088 3CE0     		b	.L889
+ 12123              	.LVL909:
+ 12124              	.L893:
+1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 12125              		.loc 1 1907 7 is_stmt 1 view .LVU3711
+ 12126 008a 0268     		ldr	r2, [r0]
+ 12127 008c D368     		ldr	r3, [r2, #12]
+ 12128 008e 23F48063 		bic	r3, r3, #1024
+ 12129 0092 D360     		str	r3, [r2, #12]
+1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12130              		.loc 1 1908 7 view .LVU3712
+1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12131              		.loc 1 1908 13 is_stmt 0 view .LVU3713
+ 12132 0094 806A     		ldr	r0, [r0, #40]
+ 12133              	.LVL910:
+1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12134              		.loc 1 1908 13 view .LVU3714
+ 12135 0096 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 12136              	.LVL911:
+1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12137              		.loc 1 1909 7 is_stmt 1 view .LVU3715
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12138              		.loc 1 1933 3 view .LVU3716
+ 12139 009a C7E7     		b	.L895
+ 12140              	.LVL912:
+ 12141              	.L892:
+1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ARM GAS  /tmp/ccPLZXyC.s 			page 406
+
+
+ 12142              		.loc 1 1915 7 view .LVU3717
+ 12143 009c 0268     		ldr	r2, [r0]
+ 12144 009e D368     		ldr	r3, [r2, #12]
+ 12145 00a0 23F40063 		bic	r3, r3, #2048
+ 12146 00a4 D360     		str	r3, [r2, #12]
+1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12147              		.loc 1 1916 7 view .LVU3718
+1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12148              		.loc 1 1916 13 is_stmt 0 view .LVU3719
+ 12149 00a6 C06A     		ldr	r0, [r0, #44]
+ 12150              	.LVL913:
+1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12151              		.loc 1 1916 13 view .LVU3720
+ 12152 00a8 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 12153              	.LVL914:
+1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12154              		.loc 1 1917 7 is_stmt 1 view .LVU3721
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12155              		.loc 1 1933 3 view .LVU3722
+ 12156 00ac BEE7     		b	.L895
+ 12157              	.LVL915:
+ 12158              	.L890:
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ 12159              		.loc 1 1923 7 view .LVU3723
+ 12160 00ae 0268     		ldr	r2, [r0]
+ 12161 00b0 D368     		ldr	r3, [r2, #12]
+ 12162 00b2 23F48053 		bic	r3, r3, #4096
+ 12163 00b6 D360     		str	r3, [r2, #12]
+1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12164              		.loc 1 1924 7 view .LVU3724
+1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12165              		.loc 1 1924 13 is_stmt 0 view .LVU3725
+ 12166 00b8 006B     		ldr	r0, [r0, #48]
+ 12167              	.LVL916:
+1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12168              		.loc 1 1924 13 view .LVU3726
+ 12169 00ba FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 12170              	.LVL917:
+1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12171              		.loc 1 1925 7 is_stmt 1 view .LVU3727
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12172              		.loc 1 1933 3 view .LVU3728
+ 12173 00be B5E7     		b	.L895
+ 12174              	.L898:
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12175              		.loc 1 1948 5 is_stmt 0 discriminator 2 view .LVU3729
+ 12176 00c0 042D     		cmp	r5, #4
+ 12177 00c2 0AD0     		beq	.L905
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12178              		.loc 1 1948 5 discriminator 4 view .LVU3730
+ 12179 00c4 082D     		cmp	r5, #8
+ 12180 00c6 0DD0     		beq	.L906
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12181              		.loc 1 1948 5 discriminator 7 view .LVU3731
+ 12182 00c8 0C2D     		cmp	r5, #12
+ 12183 00ca 10D0     		beq	.L907
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ARM GAS  /tmp/ccPLZXyC.s 			page 407
+
+
+ 12184              		.loc 1 1948 5 discriminator 10 view .LVU3732
+ 12185 00cc 102D     		cmp	r5, #16
+ 12186 00ce 13D0     		beq	.L908
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12187              		.loc 1 1948 5 discriminator 13 view .LVU3733
+ 12188 00d0 0123     		movs	r3, #1
+ 12189 00d2 84F84330 		strb	r3, [r4, #67]
+ 12190 00d6 0020     		movs	r0, #0
+ 12191 00d8 14E0     		b	.L889
+ 12192              	.L905:
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12193              		.loc 1 1948 5 discriminator 3 view .LVU3734
+ 12194 00da 0123     		movs	r3, #1
+ 12195 00dc 84F83F30 		strb	r3, [r4, #63]
+ 12196 00e0 0020     		movs	r0, #0
+ 12197 00e2 0FE0     		b	.L889
+ 12198              	.L906:
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12199              		.loc 1 1948 5 discriminator 6 view .LVU3735
+ 12200 00e4 0123     		movs	r3, #1
+ 12201 00e6 84F84030 		strb	r3, [r4, #64]
+ 12202 00ea 0020     		movs	r0, #0
+ 12203 00ec 0AE0     		b	.L889
+ 12204              	.L907:
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12205              		.loc 1 1948 5 discriminator 9 view .LVU3736
+ 12206 00ee 0123     		movs	r3, #1
+ 12207 00f0 84F84130 		strb	r3, [r4, #65]
+ 12208 00f4 0020     		movs	r0, #0
+ 12209 00f6 05E0     		b	.L889
+ 12210              	.L908:
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12211              		.loc 1 1948 5 discriminator 12 view .LVU3737
+ 12212 00f8 0123     		movs	r3, #1
+ 12213 00fa 84F84230 		strb	r3, [r4, #66]
+ 12214 00fe 0020     		movs	r0, #0
+ 12215 0100 00E0     		b	.L889
+ 12216              	.LVL918:
+ 12217              	.L903:
+1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12218              		.loc 1 1894 3 view .LVU3738
+ 12219 0102 0120     		movs	r0, #1
+ 12220              	.LVL919:
+ 12221              	.L889:
+1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 12222              		.loc 1 1952 3 is_stmt 1 view .LVU3739
+1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12223              		.loc 1 1953 1 is_stmt 0 view .LVU3740
+ 12224 0104 38BD     		pop	{r3, r4, r5, pc}
+ 12225              	.LVL920:
+ 12226              	.L910:
+1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12227              		.loc 1 1953 1 view .LVU3741
+ 12228 0106 00BF     		.align	2
+ 12229              	.L909:
+ 12230 0108 00000140 		.word	1073807360
+ 12231 010c 00040140 		.word	1073808384
+ARM GAS  /tmp/ccPLZXyC.s 			page 408
+
+
+ 12232              		.cfi_endproc
+ 12233              	.LFE170:
+ 12235              		.section	.text.HAL_TIM_IC_Start,"ax",%progbits
+ 12236              		.align	1
+ 12237              		.global	HAL_TIM_IC_Start
+ 12238              		.syntax unified
+ 12239              		.thumb
+ 12240              		.thumb_func
+ 12241              		.fpu fpv5-d16
+ 12243              	HAL_TIM_IC_Start:
+ 12244              	.LVL921:
+ 12245              	.LFB175:
+2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 12246              		.loc 1 2130 1 is_stmt 1 view -0
+ 12247              		.cfi_startproc
+ 12248              		@ args = 0, pretend = 0, frame = 0
+ 12249              		@ frame_needed = 0, uses_anonymous_args = 0
+2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 12250              		.loc 1 2130 1 is_stmt 0 view .LVU3743
+ 12251 0000 10B5     		push	{r4, lr}
+ 12252              	.LCFI98:
+ 12253              		.cfi_def_cfa_offset 8
+ 12254              		.cfi_offset 4, -8
+ 12255              		.cfi_offset 14, -4
+ 12256 0002 0446     		mov	r4, r0
+2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ 12257              		.loc 1 2131 3 is_stmt 1 view .LVU3744
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12258              		.loc 1 2132 3 view .LVU3745
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12259              		.loc 1 2132 47 is_stmt 0 view .LVU3746
+ 12260 0004 0B46     		mov	r3, r1
+ 12261 0006 0029     		cmp	r1, #0
+ 12262 0008 40D1     		bne	.L912
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12263              		.loc 1 2132 47 discriminator 1 view .LVU3747
+ 12264 000a 90F83E10 		ldrb	r1, [r0, #62]	@ zero_extendqisi2
+ 12265              	.LVL922:
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12266              		.loc 1 2132 47 discriminator 1 view .LVU3748
+ 12267 000e C9B2     		uxtb	r1, r1
+ 12268              	.L913:
+ 12269              	.LVL923:
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12270              		.loc 1 2133 3 is_stmt 1 discriminator 20 view .LVU3749
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12271              		.loc 1 2133 61 is_stmt 0 discriminator 20 view .LVU3750
+ 12272 0010 002B     		cmp	r3, #0
+ 12273 0012 57D1     		bne	.L918
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12274              		.loc 1 2133 61 discriminator 1 view .LVU3751
+ 12275 0014 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 12276 0018 D2B2     		uxtb	r2, r2
+ 12277              	.L919:
+ 12278              	.LVL924:
+2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12279              		.loc 1 2136 3 is_stmt 1 discriminator 12 view .LVU3752
+ARM GAS  /tmp/ccPLZXyC.s 			page 409
+
+
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ 12280              		.loc 1 2139 3 discriminator 12 view .LVU3753
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ 12281              		.loc 1 2139 6 is_stmt 0 discriminator 12 view .LVU3754
+ 12282 001a 012A     		cmp	r2, #1
+ 12283 001c 08BF     		it	eq
+ 12284 001e 0129     		cmpeq	r1, #1
+ 12285 0020 40F09A80 		bne	.L935
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12286              		.loc 1 2146 3 is_stmt 1 view .LVU3755
+ 12287 0024 002B     		cmp	r3, #0
+ 12288 0026 5DD1     		bne	.L923
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12289              		.loc 1 2146 3 is_stmt 0 discriminator 1 view .LVU3756
+ 12290 0028 0222     		movs	r2, #2
+ 12291              	.LVL925:
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12292              		.loc 1 2146 3 discriminator 1 view .LVU3757
+ 12293 002a 84F83E20 		strb	r2, [r4, #62]
+ 12294              	.L924:
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12295              		.loc 1 2147 3 is_stmt 1 view .LVU3758
+ 12296 002e 002B     		cmp	r3, #0
+ 12297 0030 74D1     		bne	.L929
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12298              		.loc 1 2147 3 is_stmt 0 discriminator 1 view .LVU3759
+ 12299 0032 0222     		movs	r2, #2
+ 12300 0034 84F84420 		strb	r2, [r4, #68]
+ 12301              	.L930:
+2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12302              		.loc 1 2150 3 is_stmt 1 view .LVU3760
+ 12303 0038 0122     		movs	r2, #1
+ 12304 003a 1946     		mov	r1, r3
+ 12305              	.LVL926:
+2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12306              		.loc 1 2150 3 is_stmt 0 view .LVU3761
+ 12307 003c 2068     		ldr	r0, [r4]
+ 12308              	.LVL927:
+2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12309              		.loc 1 2150 3 view .LVU3762
+ 12310 003e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 12311              	.LVL928:
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12312              		.loc 1 2153 3 is_stmt 1 view .LVU3763
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12313              		.loc 1 2153 7 is_stmt 0 view .LVU3764
+ 12314 0042 2368     		ldr	r3, [r4]
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12315              		.loc 1 2153 6 view .LVU3765
+ 12316 0044 464A     		ldr	r2, .L950
+ 12317 0046 B3F1804F 		cmp	r3, #1073741824
+ 12318 004a 18BF     		it	ne
+ 12319 004c 9342     		cmpne	r3, r2
+ 12320 004e 75D0     		beq	.L933
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12321              		.loc 1 2153 7 discriminator 1 view .LVU3766
+ 12322 0050 A2F57C42 		sub	r2, r2, #64512
+ARM GAS  /tmp/ccPLZXyC.s 			page 410
+
+
+ 12323 0054 9342     		cmp	r3, r2
+ 12324 0056 71D0     		beq	.L933
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12325              		.loc 1 2153 7 discriminator 2 view .LVU3767
+ 12326 0058 02F58062 		add	r2, r2, #1024
+ 12327 005c 9342     		cmp	r3, r2
+ 12328 005e 6DD0     		beq	.L933
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12329              		.loc 1 2153 7 discriminator 3 view .LVU3768
+ 12330 0060 02F58062 		add	r2, r2, #1024
+ 12331 0064 9342     		cmp	r3, r2
+ 12332 0066 69D0     		beq	.L933
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12333              		.loc 1 2153 7 discriminator 4 view .LVU3769
+ 12334 0068 02F57842 		add	r2, r2, #63488
+ 12335 006c 9342     		cmp	r3, r2
+ 12336 006e 65D0     		beq	.L933
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12337              		.loc 1 2153 7 discriminator 5 view .LVU3770
+ 12338 0070 02F57052 		add	r2, r2, #15360
+ 12339 0074 9342     		cmp	r3, r2
+ 12340 0076 61D0     		beq	.L933
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12341              		.loc 1 2153 7 discriminator 6 view .LVU3771
+ 12342 0078 A2F59432 		sub	r2, r2, #75776
+ 12343 007c 9342     		cmp	r3, r2
+ 12344 007e 5DD0     		beq	.L933
+2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12345              		.loc 1 2163 5 is_stmt 1 view .LVU3772
+ 12346 0080 1A68     		ldr	r2, [r3]
+ 12347 0082 42F00102 		orr	r2, r2, #1
+ 12348 0086 1A60     		str	r2, [r3]
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 12349              		.loc 1 2167 10 is_stmt 0 view .LVU3773
+ 12350 0088 0020     		movs	r0, #0
+ 12351 008a 66E0     		b	.L922
+ 12352              	.LVL929:
+ 12353              	.L912:
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12354              		.loc 1 2132 47 discriminator 2 view .LVU3774
+ 12355 008c 0429     		cmp	r1, #4
+ 12356 008e 09D0     		beq	.L938
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12357              		.loc 1 2132 47 discriminator 5 view .LVU3775
+ 12358 0090 0829     		cmp	r1, #8
+ 12359 0092 0BD0     		beq	.L939
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12360              		.loc 1 2132 47 discriminator 8 view .LVU3776
+ 12361 0094 0C29     		cmp	r1, #12
+ 12362 0096 0DD0     		beq	.L940
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12363              		.loc 1 2132 47 discriminator 11 view .LVU3777
+ 12364 0098 1029     		cmp	r1, #16
+ 12365 009a 0FD0     		beq	.L941
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12366              		.loc 1 2132 47 discriminator 14 view .LVU3778
+ 12367 009c 90F84310 		ldrb	r1, [r0, #67]	@ zero_extendqisi2
+ARM GAS  /tmp/ccPLZXyC.s 			page 411
+
+
+ 12368              	.LVL930:
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12369              		.loc 1 2132 47 discriminator 14 view .LVU3779
+ 12370 00a0 C9B2     		uxtb	r1, r1
+ 12371 00a2 B5E7     		b	.L913
+ 12372              	.LVL931:
+ 12373              	.L938:
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12374              		.loc 1 2132 47 discriminator 4 view .LVU3780
+ 12375 00a4 90F83F10 		ldrb	r1, [r0, #63]	@ zero_extendqisi2
+ 12376              	.LVL932:
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12377              		.loc 1 2132 47 discriminator 4 view .LVU3781
+ 12378 00a8 C9B2     		uxtb	r1, r1
+ 12379 00aa B1E7     		b	.L913
+ 12380              	.LVL933:
+ 12381              	.L939:
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12382              		.loc 1 2132 47 discriminator 7 view .LVU3782
+ 12383 00ac 90F84010 		ldrb	r1, [r0, #64]	@ zero_extendqisi2
+ 12384              	.LVL934:
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12385              		.loc 1 2132 47 discriminator 7 view .LVU3783
+ 12386 00b0 C9B2     		uxtb	r1, r1
+ 12387 00b2 ADE7     		b	.L913
+ 12388              	.LVL935:
+ 12389              	.L940:
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12390              		.loc 1 2132 47 discriminator 10 view .LVU3784
+ 12391 00b4 90F84110 		ldrb	r1, [r0, #65]	@ zero_extendqisi2
+ 12392              	.LVL936:
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12393              		.loc 1 2132 47 discriminator 10 view .LVU3785
+ 12394 00b8 C9B2     		uxtb	r1, r1
+ 12395 00ba A9E7     		b	.L913
+ 12396              	.LVL937:
+ 12397              	.L941:
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12398              		.loc 1 2132 47 discriminator 13 view .LVU3786
+ 12399 00bc 90F84210 		ldrb	r1, [r0, #66]	@ zero_extendqisi2
+ 12400              	.LVL938:
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12401              		.loc 1 2132 47 discriminator 13 view .LVU3787
+ 12402 00c0 C9B2     		uxtb	r1, r1
+ 12403 00c2 A5E7     		b	.L913
+ 12404              	.LVL939:
+ 12405              	.L918:
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12406              		.loc 1 2133 61 discriminator 2 view .LVU3788
+ 12407 00c4 042B     		cmp	r3, #4
+ 12408 00c6 05D0     		beq	.L942
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12409              		.loc 1 2133 61 discriminator 5 view .LVU3789
+ 12410 00c8 082B     		cmp	r3, #8
+ 12411 00ca 07D0     		beq	.L943
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12412              		.loc 1 2133 61 discriminator 8 view .LVU3790
+ARM GAS  /tmp/ccPLZXyC.s 			page 412
+
+
+ 12413 00cc 94F84720 		ldrb	r2, [r4, #71]	@ zero_extendqisi2
+ 12414 00d0 D2B2     		uxtb	r2, r2
+ 12415 00d2 A2E7     		b	.L919
+ 12416              	.L942:
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12417              		.loc 1 2133 61 discriminator 4 view .LVU3791
+ 12418 00d4 94F84520 		ldrb	r2, [r4, #69]	@ zero_extendqisi2
+ 12419 00d8 D2B2     		uxtb	r2, r2
+ 12420 00da 9EE7     		b	.L919
+ 12421              	.L943:
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12422              		.loc 1 2133 61 discriminator 7 view .LVU3792
+ 12423 00dc 94F84620 		ldrb	r2, [r4, #70]	@ zero_extendqisi2
+ 12424 00e0 D2B2     		uxtb	r2, r2
+ 12425 00e2 9AE7     		b	.L919
+ 12426              	.LVL940:
+ 12427              	.L923:
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12428              		.loc 1 2146 3 discriminator 2 view .LVU3793
+ 12429 00e4 042B     		cmp	r3, #4
+ 12430 00e6 09D0     		beq	.L944
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12431              		.loc 1 2146 3 discriminator 4 view .LVU3794
+ 12432 00e8 082B     		cmp	r3, #8
+ 12433 00ea 0BD0     		beq	.L945
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12434              		.loc 1 2146 3 discriminator 7 view .LVU3795
+ 12435 00ec 0C2B     		cmp	r3, #12
+ 12436 00ee 0DD0     		beq	.L946
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12437              		.loc 1 2146 3 discriminator 10 view .LVU3796
+ 12438 00f0 102B     		cmp	r3, #16
+ 12439 00f2 0FD0     		beq	.L947
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12440              		.loc 1 2146 3 discriminator 13 view .LVU3797
+ 12441 00f4 0222     		movs	r2, #2
+ 12442              	.LVL941:
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12443              		.loc 1 2146 3 discriminator 13 view .LVU3798
+ 12444 00f6 84F84320 		strb	r2, [r4, #67]
+ 12445 00fa 98E7     		b	.L924
+ 12446              	.LVL942:
+ 12447              	.L944:
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12448              		.loc 1 2146 3 discriminator 3 view .LVU3799
+ 12449 00fc 0222     		movs	r2, #2
+ 12450              	.LVL943:
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12451              		.loc 1 2146 3 discriminator 3 view .LVU3800
+ 12452 00fe 84F83F20 		strb	r2, [r4, #63]
+ 12453 0102 94E7     		b	.L924
+ 12454              	.LVL944:
+ 12455              	.L945:
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12456              		.loc 1 2146 3 discriminator 6 view .LVU3801
+ 12457 0104 0222     		movs	r2, #2
+ 12458              	.LVL945:
+ARM GAS  /tmp/ccPLZXyC.s 			page 413
+
+
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12459              		.loc 1 2146 3 discriminator 6 view .LVU3802
+ 12460 0106 84F84020 		strb	r2, [r4, #64]
+ 12461 010a 90E7     		b	.L924
+ 12462              	.LVL946:
+ 12463              	.L946:
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12464              		.loc 1 2146 3 discriminator 9 view .LVU3803
+ 12465 010c 0222     		movs	r2, #2
+ 12466              	.LVL947:
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12467              		.loc 1 2146 3 discriminator 9 view .LVU3804
+ 12468 010e 84F84120 		strb	r2, [r4, #65]
+ 12469 0112 8CE7     		b	.L924
+ 12470              	.LVL948:
+ 12471              	.L947:
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12472              		.loc 1 2146 3 discriminator 12 view .LVU3805
+ 12473 0114 0222     		movs	r2, #2
+ 12474              	.LVL949:
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12475              		.loc 1 2146 3 discriminator 12 view .LVU3806
+ 12476 0116 84F84220 		strb	r2, [r4, #66]
+ 12477 011a 88E7     		b	.L924
+ 12478              	.L929:
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12479              		.loc 1 2147 3 discriminator 2 view .LVU3807
+ 12480 011c 042B     		cmp	r3, #4
+ 12481 011e 05D0     		beq	.L948
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12482              		.loc 1 2147 3 discriminator 4 view .LVU3808
+ 12483 0120 082B     		cmp	r3, #8
+ 12484 0122 07D0     		beq	.L949
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12485              		.loc 1 2147 3 discriminator 7 view .LVU3809
+ 12486 0124 0222     		movs	r2, #2
+ 12487 0126 84F84720 		strb	r2, [r4, #71]
+ 12488 012a 85E7     		b	.L930
+ 12489              	.L948:
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12490              		.loc 1 2147 3 discriminator 3 view .LVU3810
+ 12491 012c 0222     		movs	r2, #2
+ 12492 012e 84F84520 		strb	r2, [r4, #69]
+ 12493 0132 81E7     		b	.L930
+ 12494              	.L949:
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12495              		.loc 1 2147 3 discriminator 6 view .LVU3811
+ 12496 0134 0222     		movs	r2, #2
+ 12497 0136 84F84620 		strb	r2, [r4, #70]
+ 12498 013a 7DE7     		b	.L930
+ 12499              	.LVL950:
+ 12500              	.L933:
+2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 12501              		.loc 1 2155 5 is_stmt 1 view .LVU3812
+2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 12502              		.loc 1 2155 29 is_stmt 0 view .LVU3813
+ 12503 013c 9968     		ldr	r1, [r3, #8]
+ARM GAS  /tmp/ccPLZXyC.s 			page 414
+
+
+2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 12504              		.loc 1 2155 13 view .LVU3814
+ 12505 013e 094A     		ldr	r2, .L950+4
+ 12506 0140 0A40     		ands	r2, r2, r1
+ 12507              	.LVL951:
+2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12508              		.loc 1 2156 5 is_stmt 1 view .LVU3815
+2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12509              		.loc 1 2156 8 is_stmt 0 view .LVU3816
+ 12510 0142 062A     		cmp	r2, #6
+ 12511 0144 18BF     		it	ne
+ 12512 0146 B2F5803F 		cmpne	r2, #65536
+ 12513 014a 07D0     		beq	.L936
+2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12514              		.loc 1 2158 7 is_stmt 1 view .LVU3817
+ 12515 014c 1A68     		ldr	r2, [r3]
+ 12516              	.LVL952:
+2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12517              		.loc 1 2158 7 is_stmt 0 view .LVU3818
+ 12518 014e 42F00102 		orr	r2, r2, #1
+ 12519 0152 1A60     		str	r2, [r3]
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 12520              		.loc 1 2167 10 view .LVU3819
+ 12521 0154 0020     		movs	r0, #0
+ 12522 0156 00E0     		b	.L922
+ 12523              	.LVL953:
+ 12524              	.L935:
+2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 12525              		.loc 1 2142 12 view .LVU3820
+ 12526 0158 0120     		movs	r0, #1
+ 12527              	.LVL954:
+ 12528              	.L922:
+2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12529              		.loc 1 2168 1 view .LVU3821
+ 12530 015a 10BD     		pop	{r4, pc}
+ 12531              	.LVL955:
+ 12532              	.L936:
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 12533              		.loc 1 2167 10 view .LVU3822
+ 12534 015c 0020     		movs	r0, #0
+ 12535 015e FCE7     		b	.L922
+ 12536              	.L951:
+ 12537              		.align	2
+ 12538              	.L950:
+ 12539 0160 00000140 		.word	1073807360
+ 12540 0164 07000100 		.word	65543
+ 12541              		.cfi_endproc
+ 12542              	.LFE175:
+ 12544              		.section	.text.HAL_TIM_IC_Stop,"ax",%progbits
+ 12545              		.align	1
+ 12546              		.global	HAL_TIM_IC_Stop
+ 12547              		.syntax unified
+ 12548              		.thumb
+ 12549              		.thumb_func
+ 12550              		.fpu fpv5-d16
+ 12552              	HAL_TIM_IC_Stop:
+ 12553              	.LVL956:
+ARM GAS  /tmp/ccPLZXyC.s 			page 415
+
+
+ 12554              	.LFB176:
+2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 12555              		.loc 1 2182 1 is_stmt 1 view -0
+ 12556              		.cfi_startproc
+ 12557              		@ args = 0, pretend = 0, frame = 0
+ 12558              		@ frame_needed = 0, uses_anonymous_args = 0
+2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 12559              		.loc 1 2182 1 is_stmt 0 view .LVU3824
+ 12560 0000 38B5     		push	{r3, r4, r5, lr}
+ 12561              	.LCFI99:
+ 12562              		.cfi_def_cfa_offset 16
+ 12563              		.cfi_offset 3, -16
+ 12564              		.cfi_offset 4, -12
+ 12565              		.cfi_offset 5, -8
+ 12566              		.cfi_offset 14, -4
+ 12567 0002 0546     		mov	r5, r0
+ 12568 0004 0C46     		mov	r4, r1
+2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12569              		.loc 1 2184 3 is_stmt 1 view .LVU3825
+2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12570              		.loc 1 2187 3 view .LVU3826
+ 12571 0006 0022     		movs	r2, #0
+ 12572 0008 0068     		ldr	r0, [r0]
+ 12573              	.LVL957:
+2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12574              		.loc 1 2187 3 is_stmt 0 view .LVU3827
+ 12575 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 12576              	.LVL958:
+2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12577              		.loc 1 2190 3 is_stmt 1 view .LVU3828
+2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12578              		.loc 1 2190 3 view .LVU3829
+ 12579 000e 2B68     		ldr	r3, [r5]
+ 12580 0010 196A     		ldr	r1, [r3, #32]
+ 12581 0012 41F21112 		movw	r2, #4369
+ 12582 0016 1142     		tst	r1, r2
+ 12583 0018 08D1     		bne	.L953
+2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12584              		.loc 1 2190 3 discriminator 1 view .LVU3830
+ 12585 001a 196A     		ldr	r1, [r3, #32]
+ 12586 001c 40F24442 		movw	r2, #1092
+ 12587 0020 1142     		tst	r1, r2
+ 12588 0022 03D1     		bne	.L953
+2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12589              		.loc 1 2190 3 discriminator 3 view .LVU3831
+ 12590 0024 1A68     		ldr	r2, [r3]
+ 12591 0026 22F00102 		bic	r2, r2, #1
+ 12592 002a 1A60     		str	r2, [r3]
+ 12593              	.L953:
+2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12594              		.loc 1 2190 3 discriminator 5 view .LVU3832
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 12595              		.loc 1 2193 3 discriminator 5 view .LVU3833
+ 12596 002c 44B9     		cbnz	r4, .L954
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 12597              		.loc 1 2193 3 is_stmt 0 discriminator 1 view .LVU3834
+ 12598 002e 0123     		movs	r3, #1
+ARM GAS  /tmp/ccPLZXyC.s 			page 416
+
+
+ 12599 0030 85F83E30 		strb	r3, [r5, #62]
+ 12600              	.L955:
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12601              		.loc 1 2194 3 is_stmt 1 view .LVU3835
+ 12602 0034 04BB     		cbnz	r4, .L960
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12603              		.loc 1 2194 3 is_stmt 0 discriminator 1 view .LVU3836
+ 12604 0036 0123     		movs	r3, #1
+ 12605 0038 85F84430 		strb	r3, [r5, #68]
+ 12606              	.L961:
+2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 12607              		.loc 1 2197 3 is_stmt 1 view .LVU3837
+2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12608              		.loc 1 2198 1 is_stmt 0 view .LVU3838
+ 12609 003c 0020     		movs	r0, #0
+ 12610 003e 38BD     		pop	{r3, r4, r5, pc}
+ 12611              	.LVL959:
+ 12612              	.L954:
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 12613              		.loc 1 2193 3 discriminator 2 view .LVU3839
+ 12614 0040 042C     		cmp	r4, #4
+ 12615 0042 09D0     		beq	.L965
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 12616              		.loc 1 2193 3 discriminator 4 view .LVU3840
+ 12617 0044 082C     		cmp	r4, #8
+ 12618 0046 0BD0     		beq	.L966
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 12619              		.loc 1 2193 3 discriminator 7 view .LVU3841
+ 12620 0048 0C2C     		cmp	r4, #12
+ 12621 004a 0DD0     		beq	.L967
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 12622              		.loc 1 2193 3 discriminator 10 view .LVU3842
+ 12623 004c 102C     		cmp	r4, #16
+ 12624 004e 0FD0     		beq	.L968
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 12625              		.loc 1 2193 3 discriminator 13 view .LVU3843
+ 12626 0050 0123     		movs	r3, #1
+ 12627 0052 85F84330 		strb	r3, [r5, #67]
+ 12628 0056 EDE7     		b	.L955
+ 12629              	.L965:
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 12630              		.loc 1 2193 3 discriminator 3 view .LVU3844
+ 12631 0058 0123     		movs	r3, #1
+ 12632 005a 85F83F30 		strb	r3, [r5, #63]
+ 12633 005e E9E7     		b	.L955
+ 12634              	.L966:
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 12635              		.loc 1 2193 3 discriminator 6 view .LVU3845
+ 12636 0060 0123     		movs	r3, #1
+ 12637 0062 85F84030 		strb	r3, [r5, #64]
+ 12638 0066 E5E7     		b	.L955
+ 12639              	.L967:
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 12640              		.loc 1 2193 3 discriminator 9 view .LVU3846
+ 12641 0068 0123     		movs	r3, #1
+ 12642 006a 85F84130 		strb	r3, [r5, #65]
+ 12643 006e E1E7     		b	.L955
+ARM GAS  /tmp/ccPLZXyC.s 			page 417
+
+
+ 12644              	.L968:
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 12645              		.loc 1 2193 3 discriminator 12 view .LVU3847
+ 12646 0070 0123     		movs	r3, #1
+ 12647 0072 85F84230 		strb	r3, [r5, #66]
+ 12648 0076 DDE7     		b	.L955
+ 12649              	.L960:
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12650              		.loc 1 2194 3 discriminator 2 view .LVU3848
+ 12651 0078 042C     		cmp	r4, #4
+ 12652 007a 05D0     		beq	.L969
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12653              		.loc 1 2194 3 discriminator 4 view .LVU3849
+ 12654 007c 082C     		cmp	r4, #8
+ 12655 007e 07D0     		beq	.L970
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12656              		.loc 1 2194 3 discriminator 7 view .LVU3850
+ 12657 0080 0123     		movs	r3, #1
+ 12658 0082 85F84730 		strb	r3, [r5, #71]
+ 12659 0086 D9E7     		b	.L961
+ 12660              	.L969:
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12661              		.loc 1 2194 3 discriminator 3 view .LVU3851
+ 12662 0088 0123     		movs	r3, #1
+ 12663 008a 85F84530 		strb	r3, [r5, #69]
+ 12664 008e D5E7     		b	.L961
+ 12665              	.L970:
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12666              		.loc 1 2194 3 discriminator 6 view .LVU3852
+ 12667 0090 0123     		movs	r3, #1
+ 12668 0092 85F84630 		strb	r3, [r5, #70]
+ 12669 0096 D1E7     		b	.L961
+ 12670              		.cfi_endproc
+ 12671              	.LFE176:
+ 12673              		.section	.text.HAL_TIM_IC_Start_IT,"ax",%progbits
+ 12674              		.align	1
+ 12675              		.global	HAL_TIM_IC_Start_IT
+ 12676              		.syntax unified
+ 12677              		.thumb
+ 12678              		.thumb_func
+ 12679              		.fpu fpv5-d16
+ 12681              	HAL_TIM_IC_Start_IT:
+ 12682              	.LVL960:
+ 12683              	.LFB177:
+2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 12684              		.loc 1 2212 1 is_stmt 1 view -0
+ 12685              		.cfi_startproc
+ 12686              		@ args = 0, pretend = 0, frame = 0
+ 12687              		@ frame_needed = 0, uses_anonymous_args = 0
+2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 12688              		.loc 1 2212 1 is_stmt 0 view .LVU3854
+ 12689 0000 10B5     		push	{r4, lr}
+ 12690              	.LCFI100:
+ 12691              		.cfi_def_cfa_offset 8
+ 12692              		.cfi_offset 4, -8
+ 12693              		.cfi_offset 14, -4
+ 12694 0002 0446     		mov	r4, r0
+ARM GAS  /tmp/ccPLZXyC.s 			page 418
+
+
+2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 12695              		.loc 1 2213 3 is_stmt 1 view .LVU3855
+ 12696              	.LVL961:
+2214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12697              		.loc 1 2214 3 view .LVU3856
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12698              		.loc 1 2216 3 view .LVU3857
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12699              		.loc 1 2216 47 is_stmt 0 view .LVU3858
+ 12700 0004 0B46     		mov	r3, r1
+ 12701 0006 11BB     		cbnz	r1, .L972
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12702              		.loc 1 2216 47 discriminator 1 view .LVU3859
+ 12703 0008 90F83E10 		ldrb	r1, [r0, #62]	@ zero_extendqisi2
+ 12704              	.LVL962:
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12705              		.loc 1 2216 47 discriminator 1 view .LVU3860
+ 12706 000c C9B2     		uxtb	r1, r1
+ 12707              	.L973:
+ 12708              	.LVL963:
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12709              		.loc 1 2217 3 is_stmt 1 discriminator 20 view .LVU3861
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12710              		.loc 1 2217 61 is_stmt 0 discriminator 20 view .LVU3862
+ 12711 000e 002B     		cmp	r3, #0
+ 12712 0010 39D1     		bne	.L978
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12713              		.loc 1 2217 61 discriminator 1 view .LVU3863
+ 12714 0012 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 12715 0016 D2B2     		uxtb	r2, r2
+ 12716              	.L979:
+ 12717              	.LVL964:
+2220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12718              		.loc 1 2220 3 is_stmt 1 discriminator 12 view .LVU3864
+2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ 12719              		.loc 1 2223 3 discriminator 12 view .LVU3865
+2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ 12720              		.loc 1 2223 6 is_stmt 0 discriminator 12 view .LVU3866
+ 12721 0018 012A     		cmp	r2, #1
+ 12722 001a 08BF     		it	eq
+ 12723 001c 0129     		cmpeq	r1, #1
+ 12724 001e 40F0BD80 		bne	.L1001
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12725              		.loc 1 2230 3 is_stmt 1 view .LVU3867
+ 12726 0022 002B     		cmp	r3, #0
+ 12727 0024 3FD1     		bne	.L983
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12728              		.loc 1 2230 3 is_stmt 0 discriminator 1 view .LVU3868
+ 12729 0026 0222     		movs	r2, #2
+ 12730              	.LVL965:
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12731              		.loc 1 2230 3 discriminator 1 view .LVU3869
+ 12732 0028 84F83E20 		strb	r2, [r4, #62]
+ 12733              	.L984:
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12734              		.loc 1 2231 3 is_stmt 1 view .LVU3870
+ 12735 002c 002B     		cmp	r3, #0
+ARM GAS  /tmp/ccPLZXyC.s 			page 419
+
+
+ 12736 002e 56D1     		bne	.L989
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12737              		.loc 1 2231 3 is_stmt 0 discriminator 1 view .LVU3871
+ 12738 0030 0222     		movs	r2, #2
+ 12739 0032 84F84420 		strb	r2, [r4, #68]
+ 12740              	.L990:
+2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12741              		.loc 1 2233 3 is_stmt 1 view .LVU3872
+ 12742 0036 0C2B     		cmp	r3, #12
+ 12743 0038 00F2B280 		bhi	.L1002
+ 12744 003c DFE803F0 		tbb	[pc, r3]
+ 12745              	.L994:
+ 12746 0040 5F       		.byte	(.L997-.L994)/2
+ 12747 0041 B0       		.byte	(.L1002-.L994)/2
+ 12748 0042 B0       		.byte	(.L1002-.L994)/2
+ 12749 0043 B0       		.byte	(.L1002-.L994)/2
+ 12750 0044 8E       		.byte	(.L996-.L994)/2
+ 12751 0045 B0       		.byte	(.L1002-.L994)/2
+ 12752 0046 B0       		.byte	(.L1002-.L994)/2
+ 12753 0047 B0       		.byte	(.L1002-.L994)/2
+ 12754 0048 94       		.byte	(.L995-.L994)/2
+ 12755 0049 B0       		.byte	(.L1002-.L994)/2
+ 12756 004a B0       		.byte	(.L1002-.L994)/2
+ 12757 004b B0       		.byte	(.L1002-.L994)/2
+ 12758 004c 9A       		.byte	(.L993-.L994)/2
+ 12759              	.LVL966:
+ 12760 004d 00       		.p2align 1
+ 12761              	.L972:
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12762              		.loc 1 2216 47 is_stmt 0 discriminator 2 view .LVU3873
+ 12763 004e 0429     		cmp	r1, #4
+ 12764 0050 09D0     		beq	.L1005
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12765              		.loc 1 2216 47 discriminator 5 view .LVU3874
+ 12766 0052 0829     		cmp	r1, #8
+ 12767 0054 0BD0     		beq	.L1006
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12768              		.loc 1 2216 47 discriminator 8 view .LVU3875
+ 12769 0056 0C29     		cmp	r1, #12
+ 12770 0058 0DD0     		beq	.L1007
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12771              		.loc 1 2216 47 discriminator 11 view .LVU3876
+ 12772 005a 1029     		cmp	r1, #16
+ 12773 005c 0FD0     		beq	.L1008
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12774              		.loc 1 2216 47 discriminator 14 view .LVU3877
+ 12775 005e 90F84310 		ldrb	r1, [r0, #67]	@ zero_extendqisi2
+ 12776              	.LVL967:
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12777              		.loc 1 2216 47 discriminator 14 view .LVU3878
+ 12778 0062 C9B2     		uxtb	r1, r1
+ 12779 0064 D3E7     		b	.L973
+ 12780              	.LVL968:
+ 12781              	.L1005:
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12782              		.loc 1 2216 47 discriminator 4 view .LVU3879
+ 12783 0066 90F83F10 		ldrb	r1, [r0, #63]	@ zero_extendqisi2
+ARM GAS  /tmp/ccPLZXyC.s 			page 420
+
+
+ 12784              	.LVL969:
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12785              		.loc 1 2216 47 discriminator 4 view .LVU3880
+ 12786 006a C9B2     		uxtb	r1, r1
+ 12787 006c CFE7     		b	.L973
+ 12788              	.LVL970:
+ 12789              	.L1006:
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12790              		.loc 1 2216 47 discriminator 7 view .LVU3881
+ 12791 006e 90F84010 		ldrb	r1, [r0, #64]	@ zero_extendqisi2
+ 12792              	.LVL971:
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12793              		.loc 1 2216 47 discriminator 7 view .LVU3882
+ 12794 0072 C9B2     		uxtb	r1, r1
+ 12795 0074 CBE7     		b	.L973
+ 12796              	.LVL972:
+ 12797              	.L1007:
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12798              		.loc 1 2216 47 discriminator 10 view .LVU3883
+ 12799 0076 90F84110 		ldrb	r1, [r0, #65]	@ zero_extendqisi2
+ 12800              	.LVL973:
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12801              		.loc 1 2216 47 discriminator 10 view .LVU3884
+ 12802 007a C9B2     		uxtb	r1, r1
+ 12803 007c C7E7     		b	.L973
+ 12804              	.LVL974:
+ 12805              	.L1008:
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12806              		.loc 1 2216 47 discriminator 13 view .LVU3885
+ 12807 007e 90F84210 		ldrb	r1, [r0, #66]	@ zero_extendqisi2
+ 12808              	.LVL975:
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 12809              		.loc 1 2216 47 discriminator 13 view .LVU3886
+ 12810 0082 C9B2     		uxtb	r1, r1
+ 12811 0084 C3E7     		b	.L973
+ 12812              	.LVL976:
+ 12813              	.L978:
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12814              		.loc 1 2217 61 discriminator 2 view .LVU3887
+ 12815 0086 042B     		cmp	r3, #4
+ 12816 0088 05D0     		beq	.L1009
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12817              		.loc 1 2217 61 discriminator 5 view .LVU3888
+ 12818 008a 082B     		cmp	r3, #8
+ 12819 008c 07D0     		beq	.L1010
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12820              		.loc 1 2217 61 discriminator 8 view .LVU3889
+ 12821 008e 94F84720 		ldrb	r2, [r4, #71]	@ zero_extendqisi2
+ 12822 0092 D2B2     		uxtb	r2, r2
+ 12823 0094 C0E7     		b	.L979
+ 12824              	.L1009:
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12825              		.loc 1 2217 61 discriminator 4 view .LVU3890
+ 12826 0096 94F84520 		ldrb	r2, [r4, #69]	@ zero_extendqisi2
+ 12827 009a D2B2     		uxtb	r2, r2
+ 12828 009c BCE7     		b	.L979
+ 12829              	.L1010:
+ARM GAS  /tmp/ccPLZXyC.s 			page 421
+
+
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12830              		.loc 1 2217 61 discriminator 7 view .LVU3891
+ 12831 009e 94F84620 		ldrb	r2, [r4, #70]	@ zero_extendqisi2
+ 12832 00a2 D2B2     		uxtb	r2, r2
+ 12833 00a4 B8E7     		b	.L979
+ 12834              	.LVL977:
+ 12835              	.L983:
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12836              		.loc 1 2230 3 discriminator 2 view .LVU3892
+ 12837 00a6 042B     		cmp	r3, #4
+ 12838 00a8 09D0     		beq	.L1011
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12839              		.loc 1 2230 3 discriminator 4 view .LVU3893
+ 12840 00aa 082B     		cmp	r3, #8
+ 12841 00ac 0BD0     		beq	.L1012
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12842              		.loc 1 2230 3 discriminator 7 view .LVU3894
+ 12843 00ae 0C2B     		cmp	r3, #12
+ 12844 00b0 0DD0     		beq	.L1013
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12845              		.loc 1 2230 3 discriminator 10 view .LVU3895
+ 12846 00b2 102B     		cmp	r3, #16
+ 12847 00b4 0FD0     		beq	.L1014
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12848              		.loc 1 2230 3 discriminator 13 view .LVU3896
+ 12849 00b6 0222     		movs	r2, #2
+ 12850              	.LVL978:
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12851              		.loc 1 2230 3 discriminator 13 view .LVU3897
+ 12852 00b8 84F84320 		strb	r2, [r4, #67]
+ 12853 00bc B6E7     		b	.L984
+ 12854              	.LVL979:
+ 12855              	.L1011:
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12856              		.loc 1 2230 3 discriminator 3 view .LVU3898
+ 12857 00be 0222     		movs	r2, #2
+ 12858              	.LVL980:
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12859              		.loc 1 2230 3 discriminator 3 view .LVU3899
+ 12860 00c0 84F83F20 		strb	r2, [r4, #63]
+ 12861 00c4 B2E7     		b	.L984
+ 12862              	.LVL981:
+ 12863              	.L1012:
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12864              		.loc 1 2230 3 discriminator 6 view .LVU3900
+ 12865 00c6 0222     		movs	r2, #2
+ 12866              	.LVL982:
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12867              		.loc 1 2230 3 discriminator 6 view .LVU3901
+ 12868 00c8 84F84020 		strb	r2, [r4, #64]
+ 12869 00cc AEE7     		b	.L984
+ 12870              	.LVL983:
+ 12871              	.L1013:
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12872              		.loc 1 2230 3 discriminator 9 view .LVU3902
+ 12873 00ce 0222     		movs	r2, #2
+ 12874              	.LVL984:
+ARM GAS  /tmp/ccPLZXyC.s 			page 422
+
+
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12875              		.loc 1 2230 3 discriminator 9 view .LVU3903
+ 12876 00d0 84F84120 		strb	r2, [r4, #65]
+ 12877 00d4 AAE7     		b	.L984
+ 12878              	.LVL985:
+ 12879              	.L1014:
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12880              		.loc 1 2230 3 discriminator 12 view .LVU3904
+ 12881 00d6 0222     		movs	r2, #2
+ 12882              	.LVL986:
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 12883              		.loc 1 2230 3 discriminator 12 view .LVU3905
+ 12884 00d8 84F84220 		strb	r2, [r4, #66]
+ 12885 00dc A6E7     		b	.L984
+ 12886              	.L989:
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12887              		.loc 1 2231 3 discriminator 2 view .LVU3906
+ 12888 00de 042B     		cmp	r3, #4
+ 12889 00e0 05D0     		beq	.L1015
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12890              		.loc 1 2231 3 discriminator 4 view .LVU3907
+ 12891 00e2 082B     		cmp	r3, #8
+ 12892 00e4 07D0     		beq	.L1016
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12893              		.loc 1 2231 3 discriminator 7 view .LVU3908
+ 12894 00e6 0222     		movs	r2, #2
+ 12895 00e8 84F84720 		strb	r2, [r4, #71]
+ 12896 00ec A3E7     		b	.L990
+ 12897              	.L1015:
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12898              		.loc 1 2231 3 discriminator 3 view .LVU3909
+ 12899 00ee 0222     		movs	r2, #2
+ 12900 00f0 84F84520 		strb	r2, [r4, #69]
+ 12901 00f4 9FE7     		b	.L990
+ 12902              	.L1016:
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12903              		.loc 1 2231 3 discriminator 6 view .LVU3910
+ 12904 00f6 0222     		movs	r2, #2
+ 12905 00f8 84F84620 		strb	r2, [r4, #70]
+ 12906 00fc 9BE7     		b	.L990
+ 12907              	.L997:
+2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12908              		.loc 1 2238 7 is_stmt 1 view .LVU3911
+ 12909 00fe 2168     		ldr	r1, [r4]
+ 12910              	.LVL987:
+2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12911              		.loc 1 2238 7 is_stmt 0 view .LVU3912
+ 12912 0100 CA68     		ldr	r2, [r1, #12]
+ 12913 0102 42F00202 		orr	r2, r2, #2
+ 12914 0106 CA60     		str	r2, [r1, #12]
+2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12915              		.loc 1 2239 7 is_stmt 1 view .LVU3913
+2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12916              		.loc 1 2268 3 view .LVU3914
+ 12917              	.L998:
+2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12918              		.loc 1 2271 5 view .LVU3915
+ARM GAS  /tmp/ccPLZXyC.s 			page 423
+
+
+ 12919 0108 0122     		movs	r2, #1
+ 12920 010a 1946     		mov	r1, r3
+ 12921 010c 2068     		ldr	r0, [r4]
+ 12922              	.LVL988:
+2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 12923              		.loc 1 2271 5 is_stmt 0 view .LVU3916
+ 12924 010e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 12925              	.LVL989:
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12926              		.loc 1 2274 5 is_stmt 1 view .LVU3917
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12927              		.loc 1 2274 9 is_stmt 0 view .LVU3918
+ 12928 0112 2368     		ldr	r3, [r4]
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12929              		.loc 1 2274 8 view .LVU3919
+ 12930 0114 244A     		ldr	r2, .L1017
+ 12931 0116 B3F1804F 		cmp	r3, #1073741824
+ 12932 011a 18BF     		it	ne
+ 12933 011c 9342     		cmpne	r3, r2
+ 12934 011e 2FD0     		beq	.L999
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12935              		.loc 1 2274 9 discriminator 1 view .LVU3920
+ 12936 0120 A2F57C42 		sub	r2, r2, #64512
+ 12937 0124 9342     		cmp	r3, r2
+ 12938 0126 2BD0     		beq	.L999
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12939              		.loc 1 2274 9 discriminator 2 view .LVU3921
+ 12940 0128 02F58062 		add	r2, r2, #1024
+ 12941 012c 9342     		cmp	r3, r2
+ 12942 012e 27D0     		beq	.L999
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12943              		.loc 1 2274 9 discriminator 3 view .LVU3922
+ 12944 0130 02F58062 		add	r2, r2, #1024
+ 12945 0134 9342     		cmp	r3, r2
+ 12946 0136 23D0     		beq	.L999
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12947              		.loc 1 2274 9 discriminator 4 view .LVU3923
+ 12948 0138 02F57842 		add	r2, r2, #63488
+ 12949 013c 9342     		cmp	r3, r2
+ 12950 013e 1FD0     		beq	.L999
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12951              		.loc 1 2274 9 discriminator 5 view .LVU3924
+ 12952 0140 02F57052 		add	r2, r2, #15360
+ 12953 0144 9342     		cmp	r3, r2
+ 12954 0146 1BD0     		beq	.L999
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 12955              		.loc 1 2274 9 discriminator 6 view .LVU3925
+ 12956 0148 A2F59432 		sub	r2, r2, #75776
+ 12957 014c 9342     		cmp	r3, r2
+ 12958 014e 17D0     		beq	.L999
+2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12959              		.loc 1 2284 7 is_stmt 1 view .LVU3926
+ 12960 0150 1A68     		ldr	r2, [r3]
+ 12961 0152 42F00102 		orr	r2, r2, #1
+ 12962 0156 1A60     		str	r2, [r3]
+ 12963 0158 0020     		movs	r0, #0
+ 12964 015a 22E0     		b	.L982
+ARM GAS  /tmp/ccPLZXyC.s 			page 424
+
+
+ 12965              	.LVL990:
+ 12966              	.L996:
+2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12967              		.loc 1 2245 7 view .LVU3927
+ 12968 015c 2168     		ldr	r1, [r4]
+ 12969              	.LVL991:
+2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12970              		.loc 1 2245 7 is_stmt 0 view .LVU3928
+ 12971 015e CA68     		ldr	r2, [r1, #12]
+ 12972 0160 42F00402 		orr	r2, r2, #4
+ 12973 0164 CA60     		str	r2, [r1, #12]
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12974              		.loc 1 2246 7 is_stmt 1 view .LVU3929
+2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12975              		.loc 1 2268 3 view .LVU3930
+ 12976 0166 CFE7     		b	.L998
+ 12977              	.LVL992:
+ 12978              	.L995:
+2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12979              		.loc 1 2252 7 view .LVU3931
+ 12980 0168 2168     		ldr	r1, [r4]
+ 12981              	.LVL993:
+2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12982              		.loc 1 2252 7 is_stmt 0 view .LVU3932
+ 12983 016a CA68     		ldr	r2, [r1, #12]
+ 12984 016c 42F00802 		orr	r2, r2, #8
+ 12985 0170 CA60     		str	r2, [r1, #12]
+2253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12986              		.loc 1 2253 7 is_stmt 1 view .LVU3933
+2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12987              		.loc 1 2268 3 view .LVU3934
+ 12988 0172 C9E7     		b	.L998
+ 12989              	.LVL994:
+ 12990              	.L993:
+2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12991              		.loc 1 2259 7 view .LVU3935
+ 12992 0174 2168     		ldr	r1, [r4]
+ 12993              	.LVL995:
+2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 12994              		.loc 1 2259 7 is_stmt 0 view .LVU3936
+ 12995 0176 CA68     		ldr	r2, [r1, #12]
+ 12996 0178 42F01002 		orr	r2, r2, #16
+ 12997 017c CA60     		str	r2, [r1, #12]
+2260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 12998              		.loc 1 2260 7 is_stmt 1 view .LVU3937
+2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 12999              		.loc 1 2268 3 view .LVU3938
+ 13000 017e C3E7     		b	.L998
+ 13001              	.LVL996:
+ 13002              	.L999:
+2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13003              		.loc 1 2276 7 view .LVU3939
+2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13004              		.loc 1 2276 31 is_stmt 0 view .LVU3940
+ 13005 0180 9968     		ldr	r1, [r3, #8]
+2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13006              		.loc 1 2276 15 view .LVU3941
+ARM GAS  /tmp/ccPLZXyC.s 			page 425
+
+
+ 13007 0182 0A4A     		ldr	r2, .L1017+4
+ 13008 0184 0A40     		ands	r2, r2, r1
+ 13009              	.LVL997:
+2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 13010              		.loc 1 2277 7 is_stmt 1 view .LVU3942
+2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 13011              		.loc 1 2277 10 is_stmt 0 view .LVU3943
+ 13012 0186 062A     		cmp	r2, #6
+ 13013 0188 18BF     		it	ne
+ 13014 018a B2F5803F 		cmpne	r2, #65536
+ 13015 018e 09D0     		beq	.L1003
+2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 13016              		.loc 1 2279 9 is_stmt 1 view .LVU3944
+ 13017 0190 1A68     		ldr	r2, [r3]
+ 13018              	.LVL998:
+2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 13019              		.loc 1 2279 9 is_stmt 0 view .LVU3945
+ 13020 0192 42F00102 		orr	r2, r2, #1
+ 13021 0196 1A60     		str	r2, [r3]
+ 13022 0198 0020     		movs	r0, #0
+ 13023 019a 02E0     		b	.L982
+ 13024              	.LVL999:
+ 13025              	.L1001:
+2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13026              		.loc 1 2226 12 view .LVU3946
+ 13027 019c 0120     		movs	r0, #1
+ 13028              	.LVL1000:
+2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13029              		.loc 1 2226 12 view .LVU3947
+ 13030 019e 00E0     		b	.L982
+ 13031              	.LVL1001:
+ 13032              	.L1002:
+2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13033              		.loc 1 2233 3 view .LVU3948
+ 13034 01a0 0120     		movs	r0, #1
+ 13035              	.LVL1002:
+ 13036              	.L982:
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13037              		.loc 1 2290 1 view .LVU3949
+ 13038 01a2 10BD     		pop	{r4, pc}
+ 13039              	.LVL1003:
+ 13040              	.L1003:
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13041              		.loc 1 2290 1 view .LVU3950
+ 13042 01a4 0020     		movs	r0, #0
+ 13043 01a6 FCE7     		b	.L982
+ 13044              	.L1018:
+ 13045              		.align	2
+ 13046              	.L1017:
+ 13047 01a8 00000140 		.word	1073807360
+ 13048 01ac 07000100 		.word	65543
+ 13049              		.cfi_endproc
+ 13050              	.LFE177:
+ 13052              		.section	.text.HAL_TIM_IC_Stop_IT,"ax",%progbits
+ 13053              		.align	1
+ 13054              		.global	HAL_TIM_IC_Stop_IT
+ 13055              		.syntax unified
+ARM GAS  /tmp/ccPLZXyC.s 			page 426
+
+
+ 13056              		.thumb
+ 13057              		.thumb_func
+ 13058              		.fpu fpv5-d16
+ 13060              	HAL_TIM_IC_Stop_IT:
+ 13061              	.LVL1004:
+ 13062              	.LFB178:
+2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13063              		.loc 1 2304 1 is_stmt 1 view -0
+ 13064              		.cfi_startproc
+ 13065              		@ args = 0, pretend = 0, frame = 0
+ 13066              		@ frame_needed = 0, uses_anonymous_args = 0
+2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13067              		.loc 1 2304 1 is_stmt 0 view .LVU3952
+ 13068 0000 38B5     		push	{r3, r4, r5, lr}
+ 13069              	.LCFI101:
+ 13070              		.cfi_def_cfa_offset 16
+ 13071              		.cfi_offset 3, -16
+ 13072              		.cfi_offset 4, -12
+ 13073              		.cfi_offset 5, -8
+ 13074              		.cfi_offset 14, -4
+ 13075 0002 0546     		mov	r5, r0
+ 13076 0004 0C46     		mov	r4, r1
+2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13077              		.loc 1 2305 3 is_stmt 1 view .LVU3953
+ 13078              	.LVL1005:
+2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13079              		.loc 1 2308 3 view .LVU3954
+2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13080              		.loc 1 2310 3 view .LVU3955
+ 13081 0006 0C29     		cmp	r1, #12
+ 13082 0008 6CD8     		bhi	.L1037
+ 13083 000a DFE801F0 		tbb	[pc, r1]
+ 13084              	.L1022:
+ 13085 000e 07       		.byte	(.L1025-.L1022)/2
+ 13086 000f 6B       		.byte	(.L1037-.L1022)/2
+ 13087 0010 6B       		.byte	(.L1037-.L1022)/2
+ 13088 0011 6B       		.byte	(.L1037-.L1022)/2
+ 13089 0012 2A       		.byte	(.L1024-.L1022)/2
+ 13090 0013 6B       		.byte	(.L1037-.L1022)/2
+ 13091 0014 6B       		.byte	(.L1037-.L1022)/2
+ 13092 0015 6B       		.byte	(.L1037-.L1022)/2
+ 13093 0016 30       		.byte	(.L1023-.L1022)/2
+ 13094 0017 6B       		.byte	(.L1037-.L1022)/2
+ 13095 0018 6B       		.byte	(.L1037-.L1022)/2
+ 13096 0019 6B       		.byte	(.L1037-.L1022)/2
+ 13097 001a 36       		.byte	(.L1021-.L1022)/2
+ 13098 001b 00       		.p2align 1
+ 13099              	.L1025:
+2315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13100              		.loc 1 2315 7 view .LVU3956
+ 13101 001c 0268     		ldr	r2, [r0]
+ 13102 001e D368     		ldr	r3, [r2, #12]
+ 13103 0020 23F00203 		bic	r3, r3, #2
+ 13104 0024 D360     		str	r3, [r2, #12]
+2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13105              		.loc 1 2316 7 view .LVU3957
+2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 427
+
+
+ 13106              		.loc 1 2345 3 view .LVU3958
+ 13107              	.L1026:
+2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13108              		.loc 1 2348 5 view .LVU3959
+ 13109 0026 0022     		movs	r2, #0
+ 13110 0028 2146     		mov	r1, r4
+ 13111              	.LVL1006:
+2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13112              		.loc 1 2348 5 is_stmt 0 view .LVU3960
+ 13113 002a 2868     		ldr	r0, [r5]
+ 13114              	.LVL1007:
+2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13115              		.loc 1 2348 5 view .LVU3961
+ 13116 002c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 13117              	.LVL1008:
+2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13118              		.loc 1 2351 5 is_stmt 1 view .LVU3962
+2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13119              		.loc 1 2351 5 view .LVU3963
+ 13120 0030 2B68     		ldr	r3, [r5]
+ 13121 0032 196A     		ldr	r1, [r3, #32]
+ 13122 0034 41F21112 		movw	r2, #4369
+ 13123 0038 1142     		tst	r1, r2
+ 13124 003a 08D1     		bne	.L1027
+2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13125              		.loc 1 2351 5 discriminator 1 view .LVU3964
+ 13126 003c 196A     		ldr	r1, [r3, #32]
+ 13127 003e 40F24442 		movw	r2, #1092
+ 13128 0042 1142     		tst	r1, r2
+ 13129 0044 03D1     		bne	.L1027
+2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13130              		.loc 1 2351 5 discriminator 3 view .LVU3965
+ 13131 0046 1A68     		ldr	r2, [r3]
+ 13132 0048 22F00102 		bic	r2, r2, #1
+ 13133 004c 1A60     		str	r2, [r3]
+ 13134              	.L1027:
+2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13135              		.loc 1 2351 5 discriminator 5 view .LVU3966
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13136              		.loc 1 2354 5 discriminator 5 view .LVU3967
+ 13137 004e D4B9     		cbnz	r4, .L1028
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13138              		.loc 1 2354 5 is_stmt 0 discriminator 1 view .LVU3968
+ 13139 0050 0123     		movs	r3, #1
+ 13140 0052 85F83E30 		strb	r3, [r5, #62]
+ 13141              	.L1029:
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13142              		.loc 1 2355 5 is_stmt 1 view .LVU3969
+ 13143 0056 94BB     		cbnz	r4, .L1034
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13144              		.loc 1 2355 5 is_stmt 0 discriminator 1 view .LVU3970
+ 13145 0058 0123     		movs	r3, #1
+ 13146 005a 85F84430 		strb	r3, [r5, #68]
+ 13147 005e 0020     		movs	r0, #0
+ 13148 0060 41E0     		b	.L1020
+ 13149              	.LVL1009:
+ 13150              	.L1024:
+ARM GAS  /tmp/ccPLZXyC.s 			page 428
+
+
+2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13151              		.loc 1 2322 7 is_stmt 1 view .LVU3971
+ 13152 0062 0268     		ldr	r2, [r0]
+ 13153 0064 D368     		ldr	r3, [r2, #12]
+ 13154 0066 23F00403 		bic	r3, r3, #4
+ 13155 006a D360     		str	r3, [r2, #12]
+2323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13156              		.loc 1 2323 7 view .LVU3972
+2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13157              		.loc 1 2345 3 view .LVU3973
+ 13158 006c DBE7     		b	.L1026
+ 13159              	.L1023:
+2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13160              		.loc 1 2329 7 view .LVU3974
+ 13161 006e 0268     		ldr	r2, [r0]
+ 13162 0070 D368     		ldr	r3, [r2, #12]
+ 13163 0072 23F00803 		bic	r3, r3, #8
+ 13164 0076 D360     		str	r3, [r2, #12]
+2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13165              		.loc 1 2330 7 view .LVU3975
+2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13166              		.loc 1 2345 3 view .LVU3976
+ 13167 0078 D5E7     		b	.L1026
+ 13168              	.L1021:
+2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13169              		.loc 1 2336 7 view .LVU3977
+ 13170 007a 0268     		ldr	r2, [r0]
+ 13171 007c D368     		ldr	r3, [r2, #12]
+ 13172 007e 23F01003 		bic	r3, r3, #16
+ 13173 0082 D360     		str	r3, [r2, #12]
+2337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13174              		.loc 1 2337 7 view .LVU3978
+2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13175              		.loc 1 2345 3 view .LVU3979
+ 13176 0084 CFE7     		b	.L1026
+ 13177              	.LVL1010:
+ 13178              	.L1028:
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13179              		.loc 1 2354 5 is_stmt 0 discriminator 2 view .LVU3980
+ 13180 0086 042C     		cmp	r4, #4
+ 13181 0088 09D0     		beq	.L1039
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13182              		.loc 1 2354 5 discriminator 4 view .LVU3981
+ 13183 008a 082C     		cmp	r4, #8
+ 13184 008c 0BD0     		beq	.L1040
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13185              		.loc 1 2354 5 discriminator 7 view .LVU3982
+ 13186 008e 0C2C     		cmp	r4, #12
+ 13187 0090 0DD0     		beq	.L1041
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13188              		.loc 1 2354 5 discriminator 10 view .LVU3983
+ 13189 0092 102C     		cmp	r4, #16
+ 13190 0094 0FD0     		beq	.L1042
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13191              		.loc 1 2354 5 discriminator 13 view .LVU3984
+ 13192 0096 0123     		movs	r3, #1
+ 13193 0098 85F84330 		strb	r3, [r5, #67]
+ARM GAS  /tmp/ccPLZXyC.s 			page 429
+
+
+ 13194 009c DBE7     		b	.L1029
+ 13195              	.L1039:
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13196              		.loc 1 2354 5 discriminator 3 view .LVU3985
+ 13197 009e 0123     		movs	r3, #1
+ 13198 00a0 85F83F30 		strb	r3, [r5, #63]
+ 13199 00a4 D7E7     		b	.L1029
+ 13200              	.L1040:
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13201              		.loc 1 2354 5 discriminator 6 view .LVU3986
+ 13202 00a6 0123     		movs	r3, #1
+ 13203 00a8 85F84030 		strb	r3, [r5, #64]
+ 13204 00ac D3E7     		b	.L1029
+ 13205              	.L1041:
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13206              		.loc 1 2354 5 discriminator 9 view .LVU3987
+ 13207 00ae 0123     		movs	r3, #1
+ 13208 00b0 85F84130 		strb	r3, [r5, #65]
+ 13209 00b4 CFE7     		b	.L1029
+ 13210              	.L1042:
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13211              		.loc 1 2354 5 discriminator 12 view .LVU3988
+ 13212 00b6 0123     		movs	r3, #1
+ 13213 00b8 85F84230 		strb	r3, [r5, #66]
+ 13214 00bc CBE7     		b	.L1029
+ 13215              	.L1034:
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13216              		.loc 1 2355 5 discriminator 2 view .LVU3989
+ 13217 00be 042C     		cmp	r4, #4
+ 13218 00c0 06D0     		beq	.L1043
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13219              		.loc 1 2355 5 discriminator 4 view .LVU3990
+ 13220 00c2 082C     		cmp	r4, #8
+ 13221 00c4 09D0     		beq	.L1044
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13222              		.loc 1 2355 5 discriminator 7 view .LVU3991
+ 13223 00c6 0123     		movs	r3, #1
+ 13224 00c8 85F84730 		strb	r3, [r5, #71]
+ 13225 00cc 0020     		movs	r0, #0
+ 13226 00ce 0AE0     		b	.L1020
+ 13227              	.L1043:
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13228              		.loc 1 2355 5 discriminator 3 view .LVU3992
+ 13229 00d0 0123     		movs	r3, #1
+ 13230 00d2 85F84530 		strb	r3, [r5, #69]
+ 13231 00d6 0020     		movs	r0, #0
+ 13232 00d8 05E0     		b	.L1020
+ 13233              	.L1044:
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13234              		.loc 1 2355 5 discriminator 6 view .LVU3993
+ 13235 00da 0123     		movs	r3, #1
+ 13236 00dc 85F84630 		strb	r3, [r5, #70]
+ 13237 00e0 0020     		movs	r0, #0
+ 13238 00e2 00E0     		b	.L1020
+ 13239              	.LVL1011:
+ 13240              	.L1037:
+2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ARM GAS  /tmp/ccPLZXyC.s 			page 430
+
+
+ 13241              		.loc 1 2310 3 view .LVU3994
+ 13242 00e4 0120     		movs	r0, #1
+ 13243              	.LVL1012:
+ 13244              	.L1020:
+2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 13245              		.loc 1 2359 3 is_stmt 1 view .LVU3995
+2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13246              		.loc 1 2360 1 is_stmt 0 view .LVU3996
+ 13247 00e6 38BD     		pop	{r3, r4, r5, pc}
+2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13248              		.loc 1 2360 1 view .LVU3997
+ 13249              		.cfi_endproc
+ 13250              	.LFE178:
+ 13252              		.section	.text.HAL_TIM_IC_Start_DMA,"ax",%progbits
+ 13253              		.align	1
+ 13254              		.global	HAL_TIM_IC_Start_DMA
+ 13255              		.syntax unified
+ 13256              		.thumb
+ 13257              		.thumb_func
+ 13258              		.fpu fpv5-d16
+ 13260              	HAL_TIM_IC_Start_DMA:
+ 13261              	.LVL1013:
+ 13262              	.LFB179:
+2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13263              		.loc 1 2376 1 is_stmt 1 view -0
+ 13264              		.cfi_startproc
+ 13265              		@ args = 0, pretend = 0, frame = 0
+ 13266              		@ frame_needed = 0, uses_anonymous_args = 0
+2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13267              		.loc 1 2376 1 is_stmt 0 view .LVU3999
+ 13268 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 13269              	.LCFI102:
+ 13270              		.cfi_def_cfa_offset 24
+ 13271              		.cfi_offset 3, -24
+ 13272              		.cfi_offset 4, -20
+ 13273              		.cfi_offset 5, -16
+ 13274              		.cfi_offset 6, -12
+ 13275              		.cfi_offset 7, -8
+ 13276              		.cfi_offset 14, -4
+ 13277 0002 0446     		mov	r4, r0
+ 13278 0004 1646     		mov	r6, r2
+ 13279 0006 1F46     		mov	r7, r3
+2377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   uint32_t tmpsmcr;
+ 13280              		.loc 1 2377 3 is_stmt 1 view .LVU4000
+ 13281              	.LVL1014:
+2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13282              		.loc 1 2378 3 view .LVU4001
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13283              		.loc 1 2380 3 view .LVU4002
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13284              		.loc 1 2380 47 is_stmt 0 view .LVU4003
+ 13285 0008 0D46     		mov	r5, r1
+ 13286 000a 0029     		cmp	r1, #0
+ 13287 000c 37D1     		bne	.L1046
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13288              		.loc 1 2380 47 discriminator 1 view .LVU4004
+ 13289 000e 90F83E30 		ldrb	r3, [r0, #62]	@ zero_extendqisi2
+ARM GAS  /tmp/ccPLZXyC.s 			page 431
+
+
+ 13290              	.LVL1015:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13291              		.loc 1 2380 47 discriminator 1 view .LVU4005
+ 13292 0012 DBB2     		uxtb	r3, r3
+ 13293              	.L1047:
+ 13294              	.LVL1016:
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13295              		.loc 1 2381 3 is_stmt 1 discriminator 20 view .LVU4006
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13296              		.loc 1 2381 61 is_stmt 0 discriminator 20 view .LVU4007
+ 13297 0014 002D     		cmp	r5, #0
+ 13298 0016 4ED1     		bne	.L1052
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13299              		.loc 1 2381 61 discriminator 1 view .LVU4008
+ 13300 0018 94F84410 		ldrb	r1, [r4, #68]	@ zero_extendqisi2
+ 13301              	.LVL1017:
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13302              		.loc 1 2381 61 discriminator 1 view .LVU4009
+ 13303 001c C9B2     		uxtb	r1, r1
+ 13304              	.L1053:
+ 13305              	.LVL1018:
+2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ 13306              		.loc 1 2384 3 is_stmt 1 discriminator 12 view .LVU4010
+2385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13307              		.loc 1 2385 3 discriminator 12 view .LVU4011
+2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 13308              		.loc 1 2388 3 discriminator 12 view .LVU4012
+2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 13309              		.loc 1 2388 6 is_stmt 0 discriminator 12 view .LVU4013
+ 13310 001e 0229     		cmp	r1, #2
+ 13311 0020 18BF     		it	ne
+ 13312 0022 022B     		cmpne	r3, #2
+ 13313 0024 00F01681 		beq	.L1075
+2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+ 13314              		.loc 1 2393 8 is_stmt 1 view .LVU4014
+2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+ 13315              		.loc 1 2393 11 is_stmt 0 view .LVU4015
+ 13316 0028 012B     		cmp	r3, #1
+ 13317 002a 08BF     		it	eq
+ 13318 002c 0129     		cmpeq	r1, #1
+ 13319 002e 40F01381 		bne	.L1076
+2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 13320              		.loc 1 2396 5 is_stmt 1 view .LVU4016
+2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 13321              		.loc 1 2396 8 is_stmt 0 view .LVU4017
+ 13322 0032 002F     		cmp	r7, #0
+ 13323 0034 18BF     		it	ne
+ 13324 0036 002E     		cmpne	r6, #0
+ 13325 0038 00F01081 		beq	.L1077
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13326              		.loc 1 2402 7 is_stmt 1 view .LVU4018
+ 13327 003c 002D     		cmp	r5, #0
+ 13328 003e 4AD1     		bne	.L1057
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13329              		.loc 1 2402 7 is_stmt 0 discriminator 1 view .LVU4019
+ 13330 0040 0223     		movs	r3, #2
+ 13331              	.LVL1019:
+ARM GAS  /tmp/ccPLZXyC.s 			page 432
+
+
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13332              		.loc 1 2402 7 discriminator 1 view .LVU4020
+ 13333 0042 84F83E30 		strb	r3, [r4, #62]
+ 13334              	.L1058:
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13335              		.loc 1 2403 7 is_stmt 1 view .LVU4021
+ 13336 0046 002D     		cmp	r5, #0
+ 13337 0048 61D1     		bne	.L1063
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13338              		.loc 1 2403 7 is_stmt 0 discriminator 1 view .LVU4022
+ 13339 004a 0223     		movs	r3, #2
+ 13340 004c 84F84430 		strb	r3, [r4, #68]
+ 13341              	.L1064:
+2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13342              		.loc 1 2412 3 is_stmt 1 view .LVU4023
+ 13343 0050 0122     		movs	r2, #1
+ 13344              	.LVL1020:
+2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13345              		.loc 1 2412 3 is_stmt 0 view .LVU4024
+ 13346 0052 2946     		mov	r1, r5
+ 13347              	.LVL1021:
+2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13348              		.loc 1 2412 3 view .LVU4025
+ 13349 0054 2068     		ldr	r0, [r4]
+ 13350              	.LVL1022:
+2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13351              		.loc 1 2412 3 view .LVU4026
+ 13352 0056 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 13353              	.LVL1023:
+2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13354              		.loc 1 2414 3 is_stmt 1 view .LVU4027
+ 13355 005a 0C2D     		cmp	r5, #12
+ 13356 005c 00F2C880 		bhi	.L1078
+ 13357 0060 DFE815F0 		tbh	[pc, r5, lsl #1]
+ 13358              	.L1069:
+ 13359 0064 6500     		.2byte	(.L1072-.L1069)/2
+ 13360 0066 C600     		.2byte	(.L1078-.L1069)/2
+ 13361 0068 C600     		.2byte	(.L1078-.L1069)/2
+ 13362 006a C600     		.2byte	(.L1078-.L1069)/2
+ 13363 006c 7E00     		.2byte	(.L1071-.L1069)/2
+ 13364 006e C600     		.2byte	(.L1078-.L1069)/2
+ 13365 0070 C600     		.2byte	(.L1078-.L1069)/2
+ 13366 0072 C600     		.2byte	(.L1078-.L1069)/2
+ 13367 0074 9600     		.2byte	(.L1070-.L1069)/2
+ 13368 0076 C600     		.2byte	(.L1078-.L1069)/2
+ 13369 0078 C600     		.2byte	(.L1078-.L1069)/2
+ 13370 007a C600     		.2byte	(.L1078-.L1069)/2
+ 13371 007c AE00     		.2byte	(.L1068-.L1069)/2
+ 13372              	.LVL1024:
+ 13373              		.p2align 1
+ 13374              	.L1046:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13375              		.loc 1 2380 47 is_stmt 0 discriminator 2 view .LVU4028
+ 13376 007e 0429     		cmp	r1, #4
+ 13377 0080 09D0     		beq	.L1084
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13378              		.loc 1 2380 47 discriminator 5 view .LVU4029
+ARM GAS  /tmp/ccPLZXyC.s 			page 433
+
+
+ 13379 0082 0829     		cmp	r1, #8
+ 13380 0084 0BD0     		beq	.L1085
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13381              		.loc 1 2380 47 discriminator 8 view .LVU4030
+ 13382 0086 0C29     		cmp	r1, #12
+ 13383 0088 0DD0     		beq	.L1086
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13384              		.loc 1 2380 47 discriminator 11 view .LVU4031
+ 13385 008a 1029     		cmp	r1, #16
+ 13386 008c 0FD0     		beq	.L1087
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13387              		.loc 1 2380 47 discriminator 14 view .LVU4032
+ 13388 008e 90F84330 		ldrb	r3, [r0, #67]	@ zero_extendqisi2
+ 13389              	.LVL1025:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13390              		.loc 1 2380 47 discriminator 14 view .LVU4033
+ 13391 0092 DBB2     		uxtb	r3, r3
+ 13392 0094 BEE7     		b	.L1047
+ 13393              	.LVL1026:
+ 13394              	.L1084:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13395              		.loc 1 2380 47 discriminator 4 view .LVU4034
+ 13396 0096 90F83F30 		ldrb	r3, [r0, #63]	@ zero_extendqisi2
+ 13397              	.LVL1027:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13398              		.loc 1 2380 47 discriminator 4 view .LVU4035
+ 13399 009a DBB2     		uxtb	r3, r3
+ 13400 009c BAE7     		b	.L1047
+ 13401              	.LVL1028:
+ 13402              	.L1085:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13403              		.loc 1 2380 47 discriminator 7 view .LVU4036
+ 13404 009e 90F84030 		ldrb	r3, [r0, #64]	@ zero_extendqisi2
+ 13405              	.LVL1029:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13406              		.loc 1 2380 47 discriminator 7 view .LVU4037
+ 13407 00a2 DBB2     		uxtb	r3, r3
+ 13408 00a4 B6E7     		b	.L1047
+ 13409              	.LVL1030:
+ 13410              	.L1086:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13411              		.loc 1 2380 47 discriminator 10 view .LVU4038
+ 13412 00a6 90F84130 		ldrb	r3, [r0, #65]	@ zero_extendqisi2
+ 13413              	.LVL1031:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13414              		.loc 1 2380 47 discriminator 10 view .LVU4039
+ 13415 00aa DBB2     		uxtb	r3, r3
+ 13416 00ac B2E7     		b	.L1047
+ 13417              	.LVL1032:
+ 13418              	.L1087:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13419              		.loc 1 2380 47 discriminator 13 view .LVU4040
+ 13420 00ae 90F84230 		ldrb	r3, [r0, #66]	@ zero_extendqisi2
+ 13421              	.LVL1033:
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+ 13422              		.loc 1 2380 47 discriminator 13 view .LVU4041
+ 13423 00b2 DBB2     		uxtb	r3, r3
+ARM GAS  /tmp/ccPLZXyC.s 			page 434
+
+
+ 13424 00b4 AEE7     		b	.L1047
+ 13425              	.LVL1034:
+ 13426              	.L1052:
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13427              		.loc 1 2381 61 discriminator 2 view .LVU4042
+ 13428 00b6 042D     		cmp	r5, #4
+ 13429 00b8 05D0     		beq	.L1088
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13430              		.loc 1 2381 61 discriminator 5 view .LVU4043
+ 13431 00ba 082D     		cmp	r5, #8
+ 13432 00bc 07D0     		beq	.L1089
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13433              		.loc 1 2381 61 discriminator 8 view .LVU4044
+ 13434 00be 94F84710 		ldrb	r1, [r4, #71]	@ zero_extendqisi2
+ 13435              	.LVL1035:
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13436              		.loc 1 2381 61 discriminator 8 view .LVU4045
+ 13437 00c2 C9B2     		uxtb	r1, r1
+ 13438 00c4 ABE7     		b	.L1053
+ 13439              	.LVL1036:
+ 13440              	.L1088:
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13441              		.loc 1 2381 61 discriminator 4 view .LVU4046
+ 13442 00c6 94F84510 		ldrb	r1, [r4, #69]	@ zero_extendqisi2
+ 13443              	.LVL1037:
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13444              		.loc 1 2381 61 discriminator 4 view .LVU4047
+ 13445 00ca C9B2     		uxtb	r1, r1
+ 13446 00cc A7E7     		b	.L1053
+ 13447              	.LVL1038:
+ 13448              	.L1089:
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13449              		.loc 1 2381 61 discriminator 7 view .LVU4048
+ 13450 00ce 94F84610 		ldrb	r1, [r4, #70]	@ zero_extendqisi2
+ 13451              	.LVL1039:
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13452              		.loc 1 2381 61 discriminator 7 view .LVU4049
+ 13453 00d2 C9B2     		uxtb	r1, r1
+ 13454 00d4 A3E7     		b	.L1053
+ 13455              	.LVL1040:
+ 13456              	.L1057:
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13457              		.loc 1 2402 7 discriminator 2 view .LVU4050
+ 13458 00d6 042D     		cmp	r5, #4
+ 13459 00d8 09D0     		beq	.L1090
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13460              		.loc 1 2402 7 discriminator 4 view .LVU4051
+ 13461 00da 082D     		cmp	r5, #8
+ 13462 00dc 0BD0     		beq	.L1091
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13463              		.loc 1 2402 7 discriminator 7 view .LVU4052
+ 13464 00de 0C2D     		cmp	r5, #12
+ 13465 00e0 0DD0     		beq	.L1092
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13466              		.loc 1 2402 7 discriminator 10 view .LVU4053
+ 13467 00e2 102D     		cmp	r5, #16
+ 13468 00e4 0FD0     		beq	.L1093
+ARM GAS  /tmp/ccPLZXyC.s 			page 435
+
+
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13469              		.loc 1 2402 7 discriminator 13 view .LVU4054
+ 13470 00e6 0223     		movs	r3, #2
+ 13471              	.LVL1041:
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13472              		.loc 1 2402 7 discriminator 13 view .LVU4055
+ 13473 00e8 84F84330 		strb	r3, [r4, #67]
+ 13474 00ec ABE7     		b	.L1058
+ 13475              	.LVL1042:
+ 13476              	.L1090:
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13477              		.loc 1 2402 7 discriminator 3 view .LVU4056
+ 13478 00ee 0223     		movs	r3, #2
+ 13479              	.LVL1043:
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13480              		.loc 1 2402 7 discriminator 3 view .LVU4057
+ 13481 00f0 84F83F30 		strb	r3, [r4, #63]
+ 13482 00f4 A7E7     		b	.L1058
+ 13483              	.LVL1044:
+ 13484              	.L1091:
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13485              		.loc 1 2402 7 discriminator 6 view .LVU4058
+ 13486 00f6 0223     		movs	r3, #2
+ 13487              	.LVL1045:
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13488              		.loc 1 2402 7 discriminator 6 view .LVU4059
+ 13489 00f8 84F84030 		strb	r3, [r4, #64]
+ 13490 00fc A3E7     		b	.L1058
+ 13491              	.LVL1046:
+ 13492              	.L1092:
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13493              		.loc 1 2402 7 discriminator 9 view .LVU4060
+ 13494 00fe 0223     		movs	r3, #2
+ 13495              	.LVL1047:
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13496              		.loc 1 2402 7 discriminator 9 view .LVU4061
+ 13497 0100 84F84130 		strb	r3, [r4, #65]
+ 13498 0104 9FE7     		b	.L1058
+ 13499              	.LVL1048:
+ 13500              	.L1093:
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13501              		.loc 1 2402 7 discriminator 12 view .LVU4062
+ 13502 0106 0223     		movs	r3, #2
+ 13503              	.LVL1049:
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 13504              		.loc 1 2402 7 discriminator 12 view .LVU4063
+ 13505 0108 84F84230 		strb	r3, [r4, #66]
+ 13506 010c 9BE7     		b	.L1058
+ 13507              	.L1063:
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13508              		.loc 1 2403 7 discriminator 2 view .LVU4064
+ 13509 010e 042D     		cmp	r5, #4
+ 13510 0110 05D0     		beq	.L1094
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13511              		.loc 1 2403 7 discriminator 4 view .LVU4065
+ 13512 0112 082D     		cmp	r5, #8
+ 13513 0114 07D0     		beq	.L1095
+ARM GAS  /tmp/ccPLZXyC.s 			page 436
+
+
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13514              		.loc 1 2403 7 discriminator 7 view .LVU4066
+ 13515 0116 0223     		movs	r3, #2
+ 13516 0118 84F84730 		strb	r3, [r4, #71]
+ 13517 011c 98E7     		b	.L1064
+ 13518              	.L1094:
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13519              		.loc 1 2403 7 discriminator 3 view .LVU4067
+ 13520 011e 0223     		movs	r3, #2
+ 13521 0120 84F84530 		strb	r3, [r4, #69]
+ 13522 0124 94E7     		b	.L1064
+ 13523              	.L1095:
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13524              		.loc 1 2403 7 discriminator 6 view .LVU4068
+ 13525 0126 0223     		movs	r3, #2
+ 13526 0128 84F84630 		strb	r3, [r4, #70]
+ 13527 012c 90E7     		b	.L1064
+ 13528              	.LVL1050:
+ 13529              	.L1072:
+2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13530              		.loc 1 2419 7 is_stmt 1 view .LVU4069
+2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13531              		.loc 1 2419 17 is_stmt 0 view .LVU4070
+ 13532 012e 636A     		ldr	r3, [r4, #36]
+2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13533              		.loc 1 2419 52 view .LVU4071
+ 13534 0130 4F4A     		ldr	r2, .L1096
+ 13535 0132 DA63     		str	r2, [r3, #60]
+2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13536              		.loc 1 2420 7 is_stmt 1 view .LVU4072
+2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13537              		.loc 1 2420 17 is_stmt 0 view .LVU4073
+ 13538 0134 636A     		ldr	r3, [r4, #36]
+2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13539              		.loc 1 2420 56 view .LVU4074
+ 13540 0136 4F4A     		ldr	r2, .L1096+4
+ 13541 0138 1A64     		str	r2, [r3, #64]
+2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13542              		.loc 1 2423 7 is_stmt 1 view .LVU4075
+2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13543              		.loc 1 2423 17 is_stmt 0 view .LVU4076
+ 13544 013a 636A     		ldr	r3, [r4, #36]
+2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13545              		.loc 1 2423 53 view .LVU4077
+ 13546 013c 4E4A     		ldr	r2, .L1096+8
+ 13547 013e DA64     		str	r2, [r3, #76]
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13548              		.loc 1 2426 7 is_stmt 1 view .LVU4078
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13549              		.loc 1 2426 71 is_stmt 0 view .LVU4079
+ 13550 0140 2168     		ldr	r1, [r4]
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13551              		.loc 1 2426 11 view .LVU4080
+ 13552 0142 3B46     		mov	r3, r7
+ 13553 0144 3246     		mov	r2, r6
+ 13554 0146 3431     		adds	r1, r1, #52
+ 13555 0148 606A     		ldr	r0, [r4, #36]
+ARM GAS  /tmp/ccPLZXyC.s 			page 437
+
+
+ 13556 014a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 13557              	.LVL1051:
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13558              		.loc 1 2426 10 view .LVU4081
+ 13559 014e 0028     		cmp	r0, #0
+ 13560 0150 40F08680 		bne	.L1079
+2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13561              		.loc 1 2433 7 is_stmt 1 view .LVU4082
+ 13562 0154 2268     		ldr	r2, [r4]
+ 13563 0156 D368     		ldr	r3, [r2, #12]
+ 13564 0158 43F40073 		orr	r3, r3, #512
+ 13565 015c D360     		str	r3, [r2, #12]
+2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13566              		.loc 1 2434 7 view .LVU4083
+ 13567 015e 48E0     		b	.L1067
+ 13568              	.L1071:
+2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13569              		.loc 1 2440 7 view .LVU4084
+2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13570              		.loc 1 2440 17 is_stmt 0 view .LVU4085
+ 13571 0160 A36A     		ldr	r3, [r4, #40]
+2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13572              		.loc 1 2440 52 view .LVU4086
+ 13573 0162 434A     		ldr	r2, .L1096
+ 13574 0164 DA63     		str	r2, [r3, #60]
+2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13575              		.loc 1 2441 7 is_stmt 1 view .LVU4087
+2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13576              		.loc 1 2441 17 is_stmt 0 view .LVU4088
+ 13577 0166 A36A     		ldr	r3, [r4, #40]
+2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13578              		.loc 1 2441 56 view .LVU4089
+ 13579 0168 424A     		ldr	r2, .L1096+4
+ 13580 016a 1A64     		str	r2, [r3, #64]
+2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13581              		.loc 1 2444 7 is_stmt 1 view .LVU4090
+2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13582              		.loc 1 2444 17 is_stmt 0 view .LVU4091
+ 13583 016c A36A     		ldr	r3, [r4, #40]
+2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13584              		.loc 1 2444 53 view .LVU4092
+ 13585 016e 424A     		ldr	r2, .L1096+8
+ 13586 0170 DA64     		str	r2, [r3, #76]
+2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13587              		.loc 1 2447 7 is_stmt 1 view .LVU4093
+2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13588              		.loc 1 2447 71 is_stmt 0 view .LVU4094
+ 13589 0172 2168     		ldr	r1, [r4]
+2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13590              		.loc 1 2447 11 view .LVU4095
+ 13591 0174 3B46     		mov	r3, r7
+ 13592 0176 3246     		mov	r2, r6
+ 13593 0178 3831     		adds	r1, r1, #56
+ 13594 017a A06A     		ldr	r0, [r4, #40]
+ 13595 017c FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 13596              	.LVL1052:
+2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ARM GAS  /tmp/ccPLZXyC.s 			page 438
+
+
+ 13597              		.loc 1 2447 10 view .LVU4096
+ 13598 0180 0028     		cmp	r0, #0
+ 13599 0182 6FD1     		bne	.L1080
+2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13600              		.loc 1 2454 7 is_stmt 1 view .LVU4097
+ 13601 0184 2268     		ldr	r2, [r4]
+ 13602 0186 D368     		ldr	r3, [r2, #12]
+ 13603 0188 43F48063 		orr	r3, r3, #1024
+ 13604 018c D360     		str	r3, [r2, #12]
+2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13605              		.loc 1 2455 7 view .LVU4098
+ 13606 018e 30E0     		b	.L1067
+ 13607              	.L1070:
+2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13608              		.loc 1 2461 7 view .LVU4099
+2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13609              		.loc 1 2461 17 is_stmt 0 view .LVU4100
+ 13610 0190 E36A     		ldr	r3, [r4, #44]
+2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13611              		.loc 1 2461 52 view .LVU4101
+ 13612 0192 374A     		ldr	r2, .L1096
+ 13613 0194 DA63     		str	r2, [r3, #60]
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13614              		.loc 1 2462 7 is_stmt 1 view .LVU4102
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13615              		.loc 1 2462 17 is_stmt 0 view .LVU4103
+ 13616 0196 E36A     		ldr	r3, [r4, #44]
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13617              		.loc 1 2462 56 view .LVU4104
+ 13618 0198 364A     		ldr	r2, .L1096+4
+ 13619 019a 1A64     		str	r2, [r3, #64]
+2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13620              		.loc 1 2465 7 is_stmt 1 view .LVU4105
+2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13621              		.loc 1 2465 17 is_stmt 0 view .LVU4106
+ 13622 019c E36A     		ldr	r3, [r4, #44]
+2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13623              		.loc 1 2465 53 view .LVU4107
+ 13624 019e 364A     		ldr	r2, .L1096+8
+ 13625 01a0 DA64     		str	r2, [r3, #76]
+2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13626              		.loc 1 2468 7 is_stmt 1 view .LVU4108
+2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13627              		.loc 1 2468 71 is_stmt 0 view .LVU4109
+ 13628 01a2 2168     		ldr	r1, [r4]
+2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13629              		.loc 1 2468 11 view .LVU4110
+ 13630 01a4 3B46     		mov	r3, r7
+ 13631 01a6 3246     		mov	r2, r6
+ 13632 01a8 3C31     		adds	r1, r1, #60
+ 13633 01aa E06A     		ldr	r0, [r4, #44]
+ 13634 01ac FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 13635              	.LVL1053:
+2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13636              		.loc 1 2468 10 view .LVU4111
+ 13637 01b0 0028     		cmp	r0, #0
+ 13638 01b2 59D1     		bne	.L1081
+ARM GAS  /tmp/ccPLZXyC.s 			page 439
+
+
+2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13639              		.loc 1 2475 7 is_stmt 1 view .LVU4112
+ 13640 01b4 2268     		ldr	r2, [r4]
+ 13641 01b6 D368     		ldr	r3, [r2, #12]
+ 13642 01b8 43F40063 		orr	r3, r3, #2048
+ 13643 01bc D360     		str	r3, [r2, #12]
+2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13644              		.loc 1 2476 7 view .LVU4113
+ 13645 01be 18E0     		b	.L1067
+ 13646              	.L1068:
+2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13647              		.loc 1 2482 7 view .LVU4114
+2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13648              		.loc 1 2482 17 is_stmt 0 view .LVU4115
+ 13649 01c0 236B     		ldr	r3, [r4, #48]
+2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 13650              		.loc 1 2482 52 view .LVU4116
+ 13651 01c2 2B4A     		ldr	r2, .L1096
+ 13652 01c4 DA63     		str	r2, [r3, #60]
+2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13653              		.loc 1 2483 7 is_stmt 1 view .LVU4117
+2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13654              		.loc 1 2483 17 is_stmt 0 view .LVU4118
+ 13655 01c6 236B     		ldr	r3, [r4, #48]
+2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13656              		.loc 1 2483 56 view .LVU4119
+ 13657 01c8 2A4A     		ldr	r2, .L1096+4
+ 13658 01ca 1A64     		str	r2, [r3, #64]
+2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13659              		.loc 1 2486 7 is_stmt 1 view .LVU4120
+2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13660              		.loc 1 2486 17 is_stmt 0 view .LVU4121
+ 13661 01cc 236B     		ldr	r3, [r4, #48]
+2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13662              		.loc 1 2486 53 view .LVU4122
+ 13663 01ce 2A4A     		ldr	r2, .L1096+8
+ 13664 01d0 DA64     		str	r2, [r3, #76]
+2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13665              		.loc 1 2489 7 is_stmt 1 view .LVU4123
+2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13666              		.loc 1 2489 71 is_stmt 0 view .LVU4124
+ 13667 01d2 2168     		ldr	r1, [r4]
+2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13668              		.loc 1 2489 11 view .LVU4125
+ 13669 01d4 3B46     		mov	r3, r7
+ 13670 01d6 3246     		mov	r2, r6
+ 13671 01d8 4031     		adds	r1, r1, #64
+ 13672 01da 206B     		ldr	r0, [r4, #48]
+ 13673 01dc FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 13674              	.LVL1054:
+2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 13675              		.loc 1 2489 10 view .LVU4126
+ 13676 01e0 0028     		cmp	r0, #0
+ 13677 01e2 43D1     		bne	.L1082
+2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13678              		.loc 1 2496 7 is_stmt 1 view .LVU4127
+ 13679 01e4 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/ccPLZXyC.s 			page 440
+
+
+ 13680 01e6 D368     		ldr	r3, [r2, #12]
+ 13681 01e8 43F48053 		orr	r3, r3, #4096
+ 13682 01ec D360     		str	r3, [r2, #12]
+2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13683              		.loc 1 2497 7 view .LVU4128
+ 13684 01ee 00E0     		b	.L1067
+ 13685              	.L1078:
+2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13686              		.loc 1 2414 3 is_stmt 0 view .LVU4129
+ 13687 01f0 0120     		movs	r0, #1
+ 13688              	.L1067:
+ 13689              	.LVL1055:
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13690              		.loc 1 2506 3 is_stmt 1 view .LVU4130
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13691              		.loc 1 2506 7 is_stmt 0 view .LVU4131
+ 13692 01f2 2368     		ldr	r3, [r4]
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13693              		.loc 1 2506 6 view .LVU4132
+ 13694 01f4 214A     		ldr	r2, .L1096+12
+ 13695 01f6 B3F1804F 		cmp	r3, #1073741824
+ 13696 01fa 18BF     		it	ne
+ 13697 01fc 9342     		cmpne	r3, r2
+ 13698 01fe 1CD0     		beq	.L1073
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13699              		.loc 1 2506 7 discriminator 1 view .LVU4133
+ 13700 0200 A2F57C42 		sub	r2, r2, #64512
+ 13701 0204 9342     		cmp	r3, r2
+ 13702 0206 18D0     		beq	.L1073
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13703              		.loc 1 2506 7 discriminator 2 view .LVU4134
+ 13704 0208 02F58062 		add	r2, r2, #1024
+ 13705 020c 9342     		cmp	r3, r2
+ 13706 020e 14D0     		beq	.L1073
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13707              		.loc 1 2506 7 discriminator 3 view .LVU4135
+ 13708 0210 02F58062 		add	r2, r2, #1024
+ 13709 0214 9342     		cmp	r3, r2
+ 13710 0216 10D0     		beq	.L1073
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13711              		.loc 1 2506 7 discriminator 4 view .LVU4136
+ 13712 0218 02F57842 		add	r2, r2, #63488
+ 13713 021c 9342     		cmp	r3, r2
+ 13714 021e 0CD0     		beq	.L1073
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13715              		.loc 1 2506 7 discriminator 5 view .LVU4137
+ 13716 0220 02F57052 		add	r2, r2, #15360
+ 13717 0224 9342     		cmp	r3, r2
+ 13718 0226 08D0     		beq	.L1073
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13719              		.loc 1 2506 7 discriminator 6 view .LVU4138
+ 13720 0228 A2F59432 		sub	r2, r2, #75776
+ 13721 022c 9342     		cmp	r3, r2
+ 13722 022e 04D0     		beq	.L1073
+2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13723              		.loc 1 2516 5 is_stmt 1 view .LVU4139
+ 13724 0230 1A68     		ldr	r2, [r3]
+ARM GAS  /tmp/ccPLZXyC.s 			page 441
+
+
+ 13725 0232 42F00102 		orr	r2, r2, #1
+ 13726 0236 1A60     		str	r2, [r3]
+ 13727 0238 0FE0     		b	.L1056
+ 13728              	.L1073:
+2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13729              		.loc 1 2508 5 view .LVU4140
+2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13730              		.loc 1 2508 29 is_stmt 0 view .LVU4141
+ 13731 023a 9968     		ldr	r1, [r3, #8]
+2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 13732              		.loc 1 2508 13 view .LVU4142
+ 13733 023c 104A     		ldr	r2, .L1096+16
+ 13734 023e 0A40     		ands	r2, r2, r1
+ 13735              	.LVL1056:
+2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 13736              		.loc 1 2509 5 is_stmt 1 view .LVU4143
+2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 13737              		.loc 1 2509 8 is_stmt 0 view .LVU4144
+ 13738 0240 062A     		cmp	r2, #6
+ 13739 0242 18BF     		it	ne
+ 13740 0244 B2F5803F 		cmpne	r2, #65536
+ 13741 0248 07D0     		beq	.L1056
+2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13742              		.loc 1 2511 7 is_stmt 1 view .LVU4145
+ 13743 024a 1A68     		ldr	r2, [r3]
+ 13744              	.LVL1057:
+2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13745              		.loc 1 2511 7 is_stmt 0 view .LVU4146
+ 13746 024c 42F00102 		orr	r2, r2, #1
+ 13747 0250 1A60     		str	r2, [r3]
+ 13748 0252 02E0     		b	.L1056
+ 13749              	.LVL1058:
+ 13750              	.L1075:
+2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13751              		.loc 1 2391 12 view .LVU4147
+ 13752 0254 0220     		movs	r0, #2
+ 13753              	.LVL1059:
+2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13754              		.loc 1 2391 12 view .LVU4148
+ 13755 0256 00E0     		b	.L1056
+ 13756              	.LVL1060:
+ 13757              	.L1076:
+2408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13758              		.loc 1 2408 12 view .LVU4149
+ 13759 0258 0120     		movs	r0, #1
+ 13760              	.LVL1061:
+ 13761              	.L1056:
+2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13762              		.loc 1 2521 1 view .LVU4150
+ 13763 025a F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 13764              	.LVL1062:
+ 13765              	.L1077:
+2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13766              		.loc 1 2398 14 view .LVU4151
+ 13767 025c 0120     		movs	r0, #1
+ 13768              	.LVL1063:
+2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ARM GAS  /tmp/ccPLZXyC.s 			page 442
+
+
+ 13769              		.loc 1 2398 14 view .LVU4152
+ 13770 025e FCE7     		b	.L1056
+ 13771              	.LVL1064:
+ 13772              	.L1079:
+2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 13773              		.loc 1 2430 16 view .LVU4153
+ 13774 0260 0120     		movs	r0, #1
+ 13775 0262 FAE7     		b	.L1056
+ 13776              	.L1080:
+2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 13777              		.loc 1 2451 16 view .LVU4154
+ 13778 0264 0120     		movs	r0, #1
+ 13779 0266 F8E7     		b	.L1056
+ 13780              	.L1081:
+2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 13781              		.loc 1 2472 16 view .LVU4155
+ 13782 0268 0120     		movs	r0, #1
+ 13783 026a F6E7     		b	.L1056
+ 13784              	.L1082:
+2493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 13785              		.loc 1 2493 16 view .LVU4156
+ 13786 026c 0120     		movs	r0, #1
+ 13787 026e F4E7     		b	.L1056
+ 13788              	.L1097:
+ 13789              		.align	2
+ 13790              	.L1096:
+ 13791 0270 00000000 		.word	TIM_DMACaptureCplt
+ 13792 0274 00000000 		.word	TIM_DMACaptureHalfCplt
+ 13793 0278 00000000 		.word	TIM_DMAError
+ 13794 027c 00000140 		.word	1073807360
+ 13795 0280 07000100 		.word	65543
+ 13796              		.cfi_endproc
+ 13797              	.LFE179:
+ 13799              		.section	.text.HAL_TIM_IC_Stop_DMA,"ax",%progbits
+ 13800              		.align	1
+ 13801              		.global	HAL_TIM_IC_Stop_DMA
+ 13802              		.syntax unified
+ 13803              		.thumb
+ 13804              		.thumb_func
+ 13805              		.fpu fpv5-d16
+ 13807              	HAL_TIM_IC_Stop_DMA:
+ 13808              	.LVL1065:
+ 13809              	.LFB180:
+2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13810              		.loc 1 2535 1 is_stmt 1 view -0
+ 13811              		.cfi_startproc
+ 13812              		@ args = 0, pretend = 0, frame = 0
+ 13813              		@ frame_needed = 0, uses_anonymous_args = 0
+2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 13814              		.loc 1 2535 1 is_stmt 0 view .LVU4158
+ 13815 0000 38B5     		push	{r3, r4, r5, lr}
+ 13816              	.LCFI103:
+ 13817              		.cfi_def_cfa_offset 16
+ 13818              		.cfi_offset 3, -16
+ 13819              		.cfi_offset 4, -12
+ 13820              		.cfi_offset 5, -8
+ 13821              		.cfi_offset 14, -4
+ARM GAS  /tmp/ccPLZXyC.s 			page 443
+
+
+ 13822 0002 0546     		mov	r5, r0
+ 13823 0004 0C46     		mov	r4, r1
+2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13824              		.loc 1 2536 3 is_stmt 1 view .LVU4159
+ 13825              	.LVL1066:
+2539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ 13826              		.loc 1 2539 3 view .LVU4160
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13827              		.loc 1 2540 3 view .LVU4161
+2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13828              		.loc 1 2543 3 view .LVU4162
+ 13829 0006 0022     		movs	r2, #0
+ 13830 0008 0068     		ldr	r0, [r0]
+ 13831              	.LVL1067:
+2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13832              		.loc 1 2543 3 is_stmt 0 view .LVU4163
+ 13833 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 13834              	.LVL1068:
+2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13835              		.loc 1 2545 3 is_stmt 1 view .LVU4164
+ 13836 000e 0C2C     		cmp	r4, #12
+ 13837 0010 74D8     		bhi	.L1116
+ 13838 0012 DFE804F0 		tbb	[pc, r4]
+ 13839              	.L1101:
+ 13840 0016 07       		.byte	(.L1104-.L1101)/2
+ 13841 0017 73       		.byte	(.L1116-.L1101)/2
+ 13842 0018 73       		.byte	(.L1116-.L1101)/2
+ 13843 0019 73       		.byte	(.L1116-.L1101)/2
+ 13844 001a 29       		.byte	(.L1103-.L1101)/2
+ 13845 001b 73       		.byte	(.L1116-.L1101)/2
+ 13846 001c 73       		.byte	(.L1116-.L1101)/2
+ 13847 001d 73       		.byte	(.L1116-.L1101)/2
+ 13848 001e 32       		.byte	(.L1102-.L1101)/2
+ 13849 001f 73       		.byte	(.L1116-.L1101)/2
+ 13850 0020 73       		.byte	(.L1116-.L1101)/2
+ 13851 0021 73       		.byte	(.L1116-.L1101)/2
+ 13852 0022 3B       		.byte	(.L1100-.L1101)/2
+ 13853 0023 00       		.p2align 1
+ 13854              	.L1104:
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 13855              		.loc 1 2550 7 view .LVU4165
+ 13856 0024 2A68     		ldr	r2, [r5]
+ 13857 0026 D368     		ldr	r3, [r2, #12]
+ 13858 0028 23F40073 		bic	r3, r3, #512
+ 13859 002c D360     		str	r3, [r2, #12]
+2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13860              		.loc 1 2551 7 view .LVU4166
+2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13861              		.loc 1 2551 13 is_stmt 0 view .LVU4167
+ 13862 002e 686A     		ldr	r0, [r5, #36]
+ 13863 0030 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 13864              	.LVL1069:
+2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13865              		.loc 1 2552 7 is_stmt 1 view .LVU4168
+2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13866              		.loc 1 2584 3 view .LVU4169
+ 13867              	.L1105:
+ARM GAS  /tmp/ccPLZXyC.s 			page 444
+
+
+2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13868              		.loc 1 2587 5 view .LVU4170
+2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13869              		.loc 1 2587 5 view .LVU4171
+ 13870 0034 2B68     		ldr	r3, [r5]
+ 13871 0036 196A     		ldr	r1, [r3, #32]
+ 13872 0038 41F21112 		movw	r2, #4369
+ 13873 003c 1142     		tst	r1, r2
+ 13874 003e 08D1     		bne	.L1106
+2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13875              		.loc 1 2587 5 discriminator 1 view .LVU4172
+ 13876 0040 196A     		ldr	r1, [r3, #32]
+ 13877 0042 40F24442 		movw	r2, #1092
+ 13878 0046 1142     		tst	r1, r2
+ 13879 0048 03D1     		bne	.L1106
+2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13880              		.loc 1 2587 5 discriminator 3 view .LVU4173
+ 13881 004a 1A68     		ldr	r2, [r3]
+ 13882 004c 22F00102 		bic	r2, r2, #1
+ 13883 0050 1A60     		str	r2, [r3]
+ 13884              	.L1106:
+2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 13885              		.loc 1 2587 5 discriminator 5 view .LVU4174
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13886              		.loc 1 2590 5 discriminator 5 view .LVU4175
+ 13887 0052 24BB     		cbnz	r4, .L1107
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13888              		.loc 1 2590 5 is_stmt 0 discriminator 1 view .LVU4176
+ 13889 0054 0123     		movs	r3, #1
+ 13890 0056 85F83E30 		strb	r3, [r5, #62]
+ 13891              	.L1108:
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13892              		.loc 1 2591 5 is_stmt 1 view .LVU4177
+ 13893 005a 002C     		cmp	r4, #0
+ 13894 005c 3BD1     		bne	.L1113
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13895              		.loc 1 2591 5 is_stmt 0 discriminator 1 view .LVU4178
+ 13896 005e 0123     		movs	r3, #1
+ 13897 0060 85F84430 		strb	r3, [r5, #68]
+ 13898 0064 0020     		movs	r0, #0
+ 13899 0066 4AE0     		b	.L1099
+ 13900              	.L1103:
+2558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 13901              		.loc 1 2558 7 is_stmt 1 view .LVU4179
+ 13902 0068 2A68     		ldr	r2, [r5]
+ 13903 006a D368     		ldr	r3, [r2, #12]
+ 13904 006c 23F48063 		bic	r3, r3, #1024
+ 13905 0070 D360     		str	r3, [r2, #12]
+2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13906              		.loc 1 2559 7 view .LVU4180
+2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13907              		.loc 1 2559 13 is_stmt 0 view .LVU4181
+ 13908 0072 A86A     		ldr	r0, [r5, #40]
+ 13909 0074 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 13910              	.LVL1070:
+2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13911              		.loc 1 2560 7 is_stmt 1 view .LVU4182
+ARM GAS  /tmp/ccPLZXyC.s 			page 445
+
+
+2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13912              		.loc 1 2584 3 view .LVU4183
+ 13913 0078 DCE7     		b	.L1105
+ 13914              	.L1102:
+2566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ 13915              		.loc 1 2566 7 view .LVU4184
+ 13916 007a 2A68     		ldr	r2, [r5]
+ 13917 007c D368     		ldr	r3, [r2, #12]
+ 13918 007e 23F40063 		bic	r3, r3, #2048
+ 13919 0082 D360     		str	r3, [r2, #12]
+2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13920              		.loc 1 2567 7 view .LVU4185
+2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13921              		.loc 1 2567 13 is_stmt 0 view .LVU4186
+ 13922 0084 E86A     		ldr	r0, [r5, #44]
+ 13923 0086 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 13924              	.LVL1071:
+2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13925              		.loc 1 2568 7 is_stmt 1 view .LVU4187
+2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13926              		.loc 1 2584 3 view .LVU4188
+ 13927 008a D3E7     		b	.L1105
+ 13928              	.L1100:
+2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ 13929              		.loc 1 2574 7 view .LVU4189
+ 13930 008c 2A68     		ldr	r2, [r5]
+ 13931 008e D368     		ldr	r3, [r2, #12]
+ 13932 0090 23F48053 		bic	r3, r3, #4096
+ 13933 0094 D360     		str	r3, [r2, #12]
+2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13934              		.loc 1 2575 7 view .LVU4190
+2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 13935              		.loc 1 2575 13 is_stmt 0 view .LVU4191
+ 13936 0096 286B     		ldr	r0, [r5, #48]
+ 13937 0098 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 13938              	.LVL1072:
+2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 13939              		.loc 1 2576 7 is_stmt 1 view .LVU4192
+2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 13940              		.loc 1 2584 3 view .LVU4193
+ 13941 009c CAE7     		b	.L1105
+ 13942              	.L1107:
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13943              		.loc 1 2590 5 is_stmt 0 discriminator 2 view .LVU4194
+ 13944 009e 042C     		cmp	r4, #4
+ 13945 00a0 09D0     		beq	.L1118
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13946              		.loc 1 2590 5 discriminator 4 view .LVU4195
+ 13947 00a2 082C     		cmp	r4, #8
+ 13948 00a4 0BD0     		beq	.L1119
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13949              		.loc 1 2590 5 discriminator 7 view .LVU4196
+ 13950 00a6 0C2C     		cmp	r4, #12
+ 13951 00a8 0DD0     		beq	.L1120
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13952              		.loc 1 2590 5 discriminator 10 view .LVU4197
+ 13953 00aa 102C     		cmp	r4, #16
+ARM GAS  /tmp/ccPLZXyC.s 			page 446
+
+
+ 13954 00ac 0FD0     		beq	.L1121
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13955              		.loc 1 2590 5 discriminator 13 view .LVU4198
+ 13956 00ae 0123     		movs	r3, #1
+ 13957 00b0 85F84330 		strb	r3, [r5, #67]
+ 13958 00b4 D1E7     		b	.L1108
+ 13959              	.L1118:
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13960              		.loc 1 2590 5 discriminator 3 view .LVU4199
+ 13961 00b6 0123     		movs	r3, #1
+ 13962 00b8 85F83F30 		strb	r3, [r5, #63]
+ 13963 00bc CDE7     		b	.L1108
+ 13964              	.L1119:
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13965              		.loc 1 2590 5 discriminator 6 view .LVU4200
+ 13966 00be 0123     		movs	r3, #1
+ 13967 00c0 85F84030 		strb	r3, [r5, #64]
+ 13968 00c4 C9E7     		b	.L1108
+ 13969              	.L1120:
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13970              		.loc 1 2590 5 discriminator 9 view .LVU4201
+ 13971 00c6 0123     		movs	r3, #1
+ 13972 00c8 85F84130 		strb	r3, [r5, #65]
+ 13973 00cc C5E7     		b	.L1108
+ 13974              	.L1121:
+2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 13975              		.loc 1 2590 5 discriminator 12 view .LVU4202
+ 13976 00ce 0123     		movs	r3, #1
+ 13977 00d0 85F84230 		strb	r3, [r5, #66]
+ 13978 00d4 C1E7     		b	.L1108
+ 13979              	.L1113:
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13980              		.loc 1 2591 5 discriminator 2 view .LVU4203
+ 13981 00d6 042C     		cmp	r4, #4
+ 13982 00d8 06D0     		beq	.L1122
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13983              		.loc 1 2591 5 discriminator 4 view .LVU4204
+ 13984 00da 082C     		cmp	r4, #8
+ 13985 00dc 09D0     		beq	.L1123
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13986              		.loc 1 2591 5 discriminator 7 view .LVU4205
+ 13987 00de 0123     		movs	r3, #1
+ 13988 00e0 85F84730 		strb	r3, [r5, #71]
+ 13989 00e4 0020     		movs	r0, #0
+ 13990 00e6 0AE0     		b	.L1099
+ 13991              	.L1122:
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13992              		.loc 1 2591 5 discriminator 3 view .LVU4206
+ 13993 00e8 0123     		movs	r3, #1
+ 13994 00ea 85F84530 		strb	r3, [r5, #69]
+ 13995 00ee 0020     		movs	r0, #0
+ 13996 00f0 05E0     		b	.L1099
+ 13997              	.L1123:
+2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 13998              		.loc 1 2591 5 discriminator 6 view .LVU4207
+ 13999 00f2 0123     		movs	r3, #1
+ 14000 00f4 85F84630 		strb	r3, [r5, #70]
+ARM GAS  /tmp/ccPLZXyC.s 			page 447
+
+
+ 14001 00f8 0020     		movs	r0, #0
+ 14002 00fa 00E0     		b	.L1099
+ 14003              	.L1116:
+2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14004              		.loc 1 2545 3 view .LVU4208
+ 14005 00fc 0120     		movs	r0, #1
+ 14006              	.L1099:
+ 14007              	.LVL1073:
+2595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 14008              		.loc 1 2595 3 is_stmt 1 view .LVU4209
+2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 14009              		.loc 1 2596 1 is_stmt 0 view .LVU4210
+ 14010 00fe 38BD     		pop	{r3, r4, r5, pc}
+2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /**
+ 14011              		.loc 1 2596 1 view .LVU4211
+ 14012              		.cfi_endproc
+ 14013              	.LFE180:
+ 14015              		.section	.text.HAL_TIM_OnePulse_Start,"ax",%progbits
+ 14016              		.align	1
+ 14017              		.global	HAL_TIM_OnePulse_Start
+ 14018              		.syntax unified
+ 14019              		.thumb
+ 14020              		.thumb_func
+ 14021              		.fpu fpv5-d16
+ 14023              	HAL_TIM_OnePulse_Start:
+ 14024              	.LVL1074:
+ 14025              	.LFB185:
+2789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 14026              		.loc 1 2789 1 is_stmt 1 view -0
+ 14027              		.cfi_startproc
+ 14028              		@ args = 0, pretend = 0, frame = 0
+ 14029              		@ frame_needed = 0, uses_anonymous_args = 0
+2789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 14030              		.loc 1 2789 1 is_stmt 0 view .LVU4213
+ 14031 0000 10B5     		push	{r4, lr}
+ 14032              	.LCFI104:
+ 14033              		.cfi_def_cfa_offset 8
+ 14034              		.cfi_offset 4, -8
+ 14035              		.cfi_offset 14, -4
+ 14036 0002 0446     		mov	r4, r0
+2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14037              		.loc 1 2790 3 is_stmt 1 view .LVU4214
+2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14038              		.loc 1 2790 31 is_stmt 0 view .LVU4215
+ 14039 0004 90F83E10 		ldrb	r1, [r0, #62]	@ zero_extendqisi2
+ 14040              	.LVL1075:
+2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14041              		.loc 1 2790 31 view .LVU4216
+ 14042 0008 C9B2     		uxtb	r1, r1
+ 14043              	.LVL1076:
+2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14044              		.loc 1 2791 3 is_stmt 1 view .LVU4217
+2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14045              		.loc 1 2791 31 is_stmt 0 view .LVU4218
+ 14046 000a 90F83F20 		ldrb	r2, [r0, #63]	@ zero_extendqisi2
+ 14047 000e D2B2     		uxtb	r2, r2
+ 14048              	.LVL1077:
+ARM GAS  /tmp/ccPLZXyC.s 			page 448
+
+
+2792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14049              		.loc 1 2792 3 is_stmt 1 view .LVU4219
+2792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14050              		.loc 1 2792 31 is_stmt 0 view .LVU4220
+ 14051 0010 90F84430 		ldrb	r3, [r0, #68]	@ zero_extendqisi2
+ 14052 0014 D8B2     		uxtb	r0, r3
+ 14053              	.LVL1078:
+2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14054              		.loc 1 2793 3 is_stmt 1 view .LVU4221
+2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14055              		.loc 1 2793 31 is_stmt 0 view .LVU4222
+ 14056 0016 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 14057              	.LVL1079:
+2796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14058              		.loc 1 2796 3 is_stmt 1 view .LVU4223
+2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 14059              		.loc 1 2799 3 view .LVU4224
+2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 14060              		.loc 1 2799 6 is_stmt 0 view .LVU4225
+ 14061 001a 012A     		cmp	r2, #1
+ 14062 001c 08BF     		it	eq
+ 14063 001e 0129     		cmpeq	r1, #1
+ 14064 0020 26D1     		bne	.L1126
+ 14065 0022 DBB2     		uxtb	r3, r3
+2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14066              		.loc 1 2802 41 view .LVU4226
+ 14067 0024 013B     		subs	r3, r3, #1
+ 14068              	.LVL1080:
+2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14069              		.loc 1 2802 41 view .LVU4227
+ 14070 0026 18BF     		it	ne
+ 14071 0028 0123     		movne	r3, #1
+ 14072              	.LVL1081:
+2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14073              		.loc 1 2802 7 view .LVU4228
+ 14074 002a 0128     		cmp	r0, #1
+ 14075 002c 22D1     		bne	.L1127
+ 14076 002e 0BBB     		cbnz	r3, .L1127
+2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14077              		.loc 1 2808 3 is_stmt 1 view .LVU4229
+ 14078 0030 0223     		movs	r3, #2
+ 14079 0032 84F83E30 		strb	r3, [r4, #62]
+2809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14080              		.loc 1 2809 3 view .LVU4230
+ 14081 0036 84F83F30 		strb	r3, [r4, #63]
+2810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14082              		.loc 1 2810 3 view .LVU4231
+ 14083 003a 84F84430 		strb	r3, [r4, #68]
+2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14084              		.loc 1 2811 3 view .LVU4232
+ 14085 003e 84F84530 		strb	r3, [r4, #69]
+2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14086              		.loc 1 2822 3 view .LVU4233
+ 14087 0042 0122     		movs	r2, #1
+ 14088              	.LVL1082:
+2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14089              		.loc 1 2822 3 is_stmt 0 view .LVU4234
+ARM GAS  /tmp/ccPLZXyC.s 			page 449
+
+
+ 14090 0044 0021     		movs	r1, #0
+ 14091              	.LVL1083:
+2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14092              		.loc 1 2822 3 view .LVU4235
+ 14093 0046 2068     		ldr	r0, [r4]
+ 14094              	.LVL1084:
+2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14095              		.loc 1 2822 3 view .LVU4236
+ 14096 0048 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14097              	.LVL1085:
+2823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14098              		.loc 1 2823 3 is_stmt 1 view .LVU4237
+ 14099 004c 0122     		movs	r2, #1
+ 14100 004e 0421     		movs	r1, #4
+ 14101 0050 2068     		ldr	r0, [r4]
+ 14102 0052 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14103              	.LVL1086:
+2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14104              		.loc 1 2825 3 view .LVU4238
+2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14105              		.loc 1 2825 7 is_stmt 0 view .LVU4239
+ 14106 0056 2368     		ldr	r3, [r4]
+2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14107              		.loc 1 2825 6 view .LVU4240
+ 14108 0058 0849     		ldr	r1, .L1130
+ 14109 005a 094A     		ldr	r2, .L1130+4
+ 14110 005c 9342     		cmp	r3, r2
+ 14111 005e 18BF     		it	ne
+ 14112 0060 8B42     		cmpne	r3, r1
+ 14113 0062 09D1     		bne	.L1128
+2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14114              		.loc 1 2828 5 is_stmt 1 view .LVU4241
+ 14115 0064 5A6C     		ldr	r2, [r3, #68]
+ 14116 0066 42F40042 		orr	r2, r2, #32768
+ 14117 006a 5A64     		str	r2, [r3, #68]
+2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 14118              		.loc 1 2832 10 is_stmt 0 view .LVU4242
+ 14119 006c 0020     		movs	r0, #0
+ 14120 006e 00E0     		b	.L1125
+ 14121              	.LVL1087:
+ 14122              	.L1126:
+2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14123              		.loc 1 2804 12 view .LVU4243
+ 14124 0070 0120     		movs	r0, #1
+ 14125              	.LVL1088:
+ 14126              	.L1125:
+2833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14127              		.loc 1 2833 1 view .LVU4244
+ 14128 0072 10BD     		pop	{r4, pc}
+ 14129              	.LVL1089:
+ 14130              	.L1127:
+2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14131              		.loc 1 2804 12 view .LVU4245
+ 14132 0074 0120     		movs	r0, #1
+ 14133              	.LVL1090:
+2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14134              		.loc 1 2804 12 view .LVU4246
+ARM GAS  /tmp/ccPLZXyC.s 			page 450
+
+
+ 14135 0076 FCE7     		b	.L1125
+ 14136              	.LVL1091:
+ 14137              	.L1128:
+2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 14138              		.loc 1 2832 10 view .LVU4247
+ 14139 0078 0020     		movs	r0, #0
+ 14140 007a FAE7     		b	.L1125
+ 14141              	.L1131:
+ 14142              		.align	2
+ 14143              	.L1130:
+ 14144 007c 00000140 		.word	1073807360
+ 14145 0080 00040140 		.word	1073808384
+ 14146              		.cfi_endproc
+ 14147              	.LFE185:
+ 14149              		.section	.text.HAL_TIM_OnePulse_Stop,"ax",%progbits
+ 14150              		.align	1
+ 14151              		.global	HAL_TIM_OnePulse_Stop
+ 14152              		.syntax unified
+ 14153              		.thumb
+ 14154              		.thumb_func
+ 14155              		.fpu fpv5-d16
+ 14157              	HAL_TIM_OnePulse_Stop:
+ 14158              	.LVL1092:
+ 14159              	.LFB186:
+2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 14160              		.loc 1 2846 1 is_stmt 1 view -0
+ 14161              		.cfi_startproc
+ 14162              		@ args = 0, pretend = 0, frame = 0
+ 14163              		@ frame_needed = 0, uses_anonymous_args = 0
+2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 14164              		.loc 1 2846 1 is_stmt 0 view .LVU4249
+ 14165 0000 10B5     		push	{r4, lr}
+ 14166              	.LCFI105:
+ 14167              		.cfi_def_cfa_offset 8
+ 14168              		.cfi_offset 4, -8
+ 14169              		.cfi_offset 14, -4
+ 14170 0002 0446     		mov	r4, r0
+2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14171              		.loc 1 2848 3 is_stmt 1 view .LVU4250
+2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14172              		.loc 1 2856 3 view .LVU4251
+ 14173 0004 0022     		movs	r2, #0
+ 14174 0006 1146     		mov	r1, r2
+ 14175              	.LVL1093:
+2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14176              		.loc 1 2856 3 is_stmt 0 view .LVU4252
+ 14177 0008 0068     		ldr	r0, [r0]
+ 14178              	.LVL1094:
+2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14179              		.loc 1 2856 3 view .LVU4253
+ 14180 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14181              	.LVL1095:
+2857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14182              		.loc 1 2857 3 is_stmt 1 view .LVU4254
+ 14183 000e 0022     		movs	r2, #0
+ 14184 0010 0421     		movs	r1, #4
+ 14185 0012 2068     		ldr	r0, [r4]
+ARM GAS  /tmp/ccPLZXyC.s 			page 451
+
+
+ 14186 0014 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14187              	.LVL1096:
+2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14188              		.loc 1 2859 3 view .LVU4255
+2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14189              		.loc 1 2859 7 is_stmt 0 view .LVU4256
+ 14190 0018 2368     		ldr	r3, [r4]
+2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14191              		.loc 1 2859 6 view .LVU4257
+ 14192 001a 1749     		ldr	r1, .L1136
+ 14193 001c 174A     		ldr	r2, .L1136+4
+ 14194 001e 9342     		cmp	r3, r2
+ 14195 0020 18BF     		it	ne
+ 14196 0022 8B42     		cmpne	r3, r1
+ 14197 0024 0DD1     		bne	.L1133
+2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14198              		.loc 1 2862 5 is_stmt 1 view .LVU4258
+2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14199              		.loc 1 2862 5 view .LVU4259
+ 14200 0026 196A     		ldr	r1, [r3, #32]
+ 14201 0028 41F21112 		movw	r2, #4369
+ 14202 002c 1142     		tst	r1, r2
+ 14203 002e 08D1     		bne	.L1133
+2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14204              		.loc 1 2862 5 discriminator 1 view .LVU4260
+ 14205 0030 196A     		ldr	r1, [r3, #32]
+ 14206 0032 40F24442 		movw	r2, #1092
+ 14207 0036 1142     		tst	r1, r2
+ 14208 0038 03D1     		bne	.L1133
+2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14209              		.loc 1 2862 5 discriminator 3 view .LVU4261
+ 14210 003a 5A6C     		ldr	r2, [r3, #68]
+ 14211 003c 22F40042 		bic	r2, r2, #32768
+ 14212 0040 5A64     		str	r2, [r3, #68]
+ 14213              	.L1133:
+2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14214              		.loc 1 2862 5 discriminator 5 view .LVU4262
+2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14215              		.loc 1 2866 3 discriminator 5 view .LVU4263
+2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14216              		.loc 1 2866 3 discriminator 5 view .LVU4264
+ 14217 0042 2368     		ldr	r3, [r4]
+ 14218 0044 196A     		ldr	r1, [r3, #32]
+ 14219 0046 41F21112 		movw	r2, #4369
+ 14220 004a 1142     		tst	r1, r2
+ 14221 004c 08D1     		bne	.L1134
+2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14222              		.loc 1 2866 3 discriminator 1 view .LVU4265
+ 14223 004e 196A     		ldr	r1, [r3, #32]
+ 14224 0050 40F24442 		movw	r2, #1092
+ 14225 0054 1142     		tst	r1, r2
+ 14226 0056 03D1     		bne	.L1134
+2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14227              		.loc 1 2866 3 discriminator 3 view .LVU4266
+ 14228 0058 1A68     		ldr	r2, [r3]
+ 14229 005a 22F00102 		bic	r2, r2, #1
+ 14230 005e 1A60     		str	r2, [r3]
+ARM GAS  /tmp/ccPLZXyC.s 			page 452
+
+
+ 14231              	.L1134:
+2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14232              		.loc 1 2866 3 discriminator 5 view .LVU4267
+2869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 14233              		.loc 1 2869 3 discriminator 5 view .LVU4268
+ 14234 0060 0123     		movs	r3, #1
+ 14235 0062 84F83E30 		strb	r3, [r4, #62]
+2870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 14236              		.loc 1 2870 3 discriminator 5 view .LVU4269
+ 14237 0066 84F83F30 		strb	r3, [r4, #63]
+2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 14238              		.loc 1 2871 3 discriminator 5 view .LVU4270
+ 14239 006a 84F84430 		strb	r3, [r4, #68]
+2872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14240              		.loc 1 2872 3 discriminator 5 view .LVU4271
+ 14241 006e 84F84530 		strb	r3, [r4, #69]
+2875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 14242              		.loc 1 2875 3 discriminator 5 view .LVU4272
+2876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14243              		.loc 1 2876 1 is_stmt 0 discriminator 5 view .LVU4273
+ 14244 0072 0020     		movs	r0, #0
+ 14245 0074 10BD     		pop	{r4, pc}
+ 14246              	.LVL1097:
+ 14247              	.L1137:
+2876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14248              		.loc 1 2876 1 discriminator 5 view .LVU4274
+ 14249 0076 00BF     		.align	2
+ 14250              	.L1136:
+ 14251 0078 00000140 		.word	1073807360
+ 14252 007c 00040140 		.word	1073808384
+ 14253              		.cfi_endproc
+ 14254              	.LFE186:
+ 14256              		.section	.text.HAL_TIM_OnePulse_Start_IT,"ax",%progbits
+ 14257              		.align	1
+ 14258              		.global	HAL_TIM_OnePulse_Start_IT
+ 14259              		.syntax unified
+ 14260              		.thumb
+ 14261              		.thumb_func
+ 14262              		.fpu fpv5-d16
+ 14264              	HAL_TIM_OnePulse_Start_IT:
+ 14265              	.LVL1098:
+ 14266              	.LFB187:
+2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 14267              		.loc 1 2889 1 is_stmt 1 view -0
+ 14268              		.cfi_startproc
+ 14269              		@ args = 0, pretend = 0, frame = 0
+ 14270              		@ frame_needed = 0, uses_anonymous_args = 0
+2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 14271              		.loc 1 2889 1 is_stmt 0 view .LVU4276
+ 14272 0000 10B5     		push	{r4, lr}
+ 14273              	.LCFI106:
+ 14274              		.cfi_def_cfa_offset 8
+ 14275              		.cfi_offset 4, -8
+ 14276              		.cfi_offset 14, -4
+ 14277 0002 0446     		mov	r4, r0
+2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14278              		.loc 1 2890 3 is_stmt 1 view .LVU4277
+ARM GAS  /tmp/ccPLZXyC.s 			page 453
+
+
+2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14279              		.loc 1 2890 31 is_stmt 0 view .LVU4278
+ 14280 0004 90F83E10 		ldrb	r1, [r0, #62]	@ zero_extendqisi2
+ 14281              	.LVL1099:
+2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14282              		.loc 1 2890 31 view .LVU4279
+ 14283 0008 C9B2     		uxtb	r1, r1
+ 14284              	.LVL1100:
+2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14285              		.loc 1 2891 3 is_stmt 1 view .LVU4280
+2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14286              		.loc 1 2891 31 is_stmt 0 view .LVU4281
+ 14287 000a 90F83F20 		ldrb	r2, [r0, #63]	@ zero_extendqisi2
+ 14288 000e D2B2     		uxtb	r2, r2
+ 14289              	.LVL1101:
+2892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14290              		.loc 1 2892 3 is_stmt 1 view .LVU4282
+2892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14291              		.loc 1 2892 31 is_stmt 0 view .LVU4283
+ 14292 0010 90F84430 		ldrb	r3, [r0, #68]	@ zero_extendqisi2
+ 14293 0014 D8B2     		uxtb	r0, r3
+ 14294              	.LVL1102:
+2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14295              		.loc 1 2893 3 is_stmt 1 view .LVU4284
+2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14296              		.loc 1 2893 31 is_stmt 0 view .LVU4285
+ 14297 0016 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 14298              	.LVL1103:
+2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14299              		.loc 1 2896 3 is_stmt 1 view .LVU4286
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 14300              		.loc 1 2899 3 view .LVU4287
+2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 14301              		.loc 1 2899 6 is_stmt 0 view .LVU4288
+ 14302 001a 012A     		cmp	r2, #1
+ 14303 001c 08BF     		it	eq
+ 14304 001e 0129     		cmpeq	r1, #1
+ 14305 0020 30D1     		bne	.L1140
+ 14306 0022 DBB2     		uxtb	r3, r3
+2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14307              		.loc 1 2902 41 view .LVU4289
+ 14308 0024 013B     		subs	r3, r3, #1
+ 14309              	.LVL1104:
+2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14310              		.loc 1 2902 41 view .LVU4290
+ 14311 0026 18BF     		it	ne
+ 14312 0028 0123     		movne	r3, #1
+ 14313              	.LVL1105:
+2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14314              		.loc 1 2902 7 view .LVU4291
+ 14315 002a 0128     		cmp	r0, #1
+ 14316 002c 2CD1     		bne	.L1141
+ 14317 002e 5BBB     		cbnz	r3, .L1141
+2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14318              		.loc 1 2908 3 is_stmt 1 view .LVU4292
+ 14319 0030 0223     		movs	r3, #2
+ 14320 0032 84F83E30 		strb	r3, [r4, #62]
+ARM GAS  /tmp/ccPLZXyC.s 			page 454
+
+
+2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14321              		.loc 1 2909 3 view .LVU4293
+ 14322 0036 84F83F30 		strb	r3, [r4, #63]
+2910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14323              		.loc 1 2910 3 view .LVU4294
+ 14324 003a 84F84430 		strb	r3, [r4, #68]
+2911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14325              		.loc 1 2911 3 view .LVU4295
+ 14326 003e 84F84530 		strb	r3, [r4, #69]
+2923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14327              		.loc 1 2923 3 view .LVU4296
+ 14328 0042 2268     		ldr	r2, [r4]
+ 14329              	.LVL1106:
+2923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14330              		.loc 1 2923 3 is_stmt 0 view .LVU4297
+ 14331 0044 D368     		ldr	r3, [r2, #12]
+ 14332 0046 43F00203 		orr	r3, r3, #2
+ 14333 004a D360     		str	r3, [r2, #12]
+2926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14334              		.loc 1 2926 3 is_stmt 1 view .LVU4298
+ 14335 004c 2268     		ldr	r2, [r4]
+ 14336 004e D368     		ldr	r3, [r2, #12]
+ 14337 0050 43F00403 		orr	r3, r3, #4
+ 14338 0054 D360     		str	r3, [r2, #12]
+2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14339              		.loc 1 2928 3 view .LVU4299
+ 14340 0056 0122     		movs	r2, #1
+ 14341 0058 0021     		movs	r1, #0
+ 14342              	.LVL1107:
+2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14343              		.loc 1 2928 3 is_stmt 0 view .LVU4300
+ 14344 005a 2068     		ldr	r0, [r4]
+ 14345              	.LVL1108:
+2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14346              		.loc 1 2928 3 view .LVU4301
+ 14347 005c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14348              	.LVL1109:
+2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14349              		.loc 1 2929 3 is_stmt 1 view .LVU4302
+ 14350 0060 0122     		movs	r2, #1
+ 14351 0062 0421     		movs	r1, #4
+ 14352 0064 2068     		ldr	r0, [r4]
+ 14353 0066 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14354              	.LVL1110:
+2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14355              		.loc 1 2931 3 view .LVU4303
+2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14356              		.loc 1 2931 7 is_stmt 0 view .LVU4304
+ 14357 006a 2368     		ldr	r3, [r4]
+2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14358              		.loc 1 2931 6 view .LVU4305
+ 14359 006c 0849     		ldr	r1, .L1144
+ 14360 006e 094A     		ldr	r2, .L1144+4
+ 14361 0070 9342     		cmp	r3, r2
+ 14362 0072 18BF     		it	ne
+ 14363 0074 8B42     		cmpne	r3, r1
+ 14364 0076 09D1     		bne	.L1142
+ARM GAS  /tmp/ccPLZXyC.s 			page 455
+
+
+2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14365              		.loc 1 2934 5 is_stmt 1 view .LVU4306
+ 14366 0078 5A6C     		ldr	r2, [r3, #68]
+ 14367 007a 42F40042 		orr	r2, r2, #32768
+ 14368 007e 5A64     		str	r2, [r3, #68]
+2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 14369              		.loc 1 2938 10 is_stmt 0 view .LVU4307
+ 14370 0080 0020     		movs	r0, #0
+ 14371 0082 00E0     		b	.L1139
+ 14372              	.LVL1111:
+ 14373              	.L1140:
+2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14374              		.loc 1 2904 12 view .LVU4308
+ 14375 0084 0120     		movs	r0, #1
+ 14376              	.LVL1112:
+ 14377              	.L1139:
+2939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14378              		.loc 1 2939 1 view .LVU4309
+ 14379 0086 10BD     		pop	{r4, pc}
+ 14380              	.LVL1113:
+ 14381              	.L1141:
+2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14382              		.loc 1 2904 12 view .LVU4310
+ 14383 0088 0120     		movs	r0, #1
+ 14384              	.LVL1114:
+2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14385              		.loc 1 2904 12 view .LVU4311
+ 14386 008a FCE7     		b	.L1139
+ 14387              	.LVL1115:
+ 14388              	.L1142:
+2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 14389              		.loc 1 2938 10 view .LVU4312
+ 14390 008c 0020     		movs	r0, #0
+ 14391 008e FAE7     		b	.L1139
+ 14392              	.L1145:
+ 14393              		.align	2
+ 14394              	.L1144:
+ 14395 0090 00000140 		.word	1073807360
+ 14396 0094 00040140 		.word	1073808384
+ 14397              		.cfi_endproc
+ 14398              	.LFE187:
+ 14400              		.section	.text.HAL_TIM_OnePulse_Stop_IT,"ax",%progbits
+ 14401              		.align	1
+ 14402              		.global	HAL_TIM_OnePulse_Stop_IT
+ 14403              		.syntax unified
+ 14404              		.thumb
+ 14405              		.thumb_func
+ 14406              		.fpu fpv5-d16
+ 14408              	HAL_TIM_OnePulse_Stop_IT:
+ 14409              	.LVL1116:
+ 14410              	.LFB188:
+2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ 14411              		.loc 1 2952 1 is_stmt 1 view -0
+ 14412              		.cfi_startproc
+ 14413              		@ args = 0, pretend = 0, frame = 0
+ 14414              		@ frame_needed = 0, uses_anonymous_args = 0
+2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Prevent unused argument(s) compilation warning */
+ARM GAS  /tmp/ccPLZXyC.s 			page 456
+
+
+ 14415              		.loc 1 2952 1 is_stmt 0 view .LVU4314
+ 14416 0000 10B5     		push	{r4, lr}
+ 14417              	.LCFI107:
+ 14418              		.cfi_def_cfa_offset 8
+ 14419              		.cfi_offset 4, -8
+ 14420              		.cfi_offset 14, -4
+ 14421 0002 0446     		mov	r4, r0
+2954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14422              		.loc 1 2954 3 is_stmt 1 view .LVU4315
+2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14423              		.loc 1 2957 3 view .LVU4316
+ 14424 0004 0268     		ldr	r2, [r0]
+ 14425 0006 D368     		ldr	r3, [r2, #12]
+ 14426 0008 23F00203 		bic	r3, r3, #2
+ 14427 000c D360     		str	r3, [r2, #12]
+2960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14428              		.loc 1 2960 3 view .LVU4317
+ 14429 000e 0268     		ldr	r2, [r0]
+ 14430 0010 D368     		ldr	r3, [r2, #12]
+ 14431 0012 23F00403 		bic	r3, r3, #4
+ 14432 0016 D360     		str	r3, [r2, #12]
+2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14433              		.loc 1 2967 3 view .LVU4318
+ 14434 0018 0022     		movs	r2, #0
+ 14435 001a 1146     		mov	r1, r2
+ 14436              	.LVL1117:
+2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14437              		.loc 1 2967 3 is_stmt 0 view .LVU4319
+ 14438 001c 0068     		ldr	r0, [r0]
+ 14439              	.LVL1118:
+2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14440              		.loc 1 2967 3 view .LVU4320
+ 14441 001e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14442              	.LVL1119:
+2968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14443              		.loc 1 2968 3 is_stmt 1 view .LVU4321
+ 14444 0022 0022     		movs	r2, #0
+ 14445 0024 0421     		movs	r1, #4
+ 14446 0026 2068     		ldr	r0, [r4]
+ 14447 0028 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14448              	.LVL1120:
+2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14449              		.loc 1 2970 3 view .LVU4322
+2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14450              		.loc 1 2970 7 is_stmt 0 view .LVU4323
+ 14451 002c 2368     		ldr	r3, [r4]
+2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14452              		.loc 1 2970 6 view .LVU4324
+ 14453 002e 1749     		ldr	r1, .L1150
+ 14454 0030 174A     		ldr	r2, .L1150+4
+ 14455 0032 9342     		cmp	r3, r2
+ 14456 0034 18BF     		it	ne
+ 14457 0036 8B42     		cmpne	r3, r1
+ 14458 0038 0DD1     		bne	.L1147
+2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14459              		.loc 1 2973 5 is_stmt 1 view .LVU4325
+2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ARM GAS  /tmp/ccPLZXyC.s 			page 457
+
+
+ 14460              		.loc 1 2973 5 view .LVU4326
+ 14461 003a 196A     		ldr	r1, [r3, #32]
+ 14462 003c 41F21112 		movw	r2, #4369
+ 14463 0040 1142     		tst	r1, r2
+ 14464 0042 08D1     		bne	.L1147
+2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14465              		.loc 1 2973 5 discriminator 1 view .LVU4327
+ 14466 0044 196A     		ldr	r1, [r3, #32]
+ 14467 0046 40F24442 		movw	r2, #1092
+ 14468 004a 1142     		tst	r1, r2
+ 14469 004c 03D1     		bne	.L1147
+2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14470              		.loc 1 2973 5 discriminator 3 view .LVU4328
+ 14471 004e 5A6C     		ldr	r2, [r3, #68]
+ 14472 0050 22F40042 		bic	r2, r2, #32768
+ 14473 0054 5A64     		str	r2, [r3, #68]
+ 14474              	.L1147:
+2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14475              		.loc 1 2973 5 discriminator 5 view .LVU4329
+2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14476              		.loc 1 2977 3 discriminator 5 view .LVU4330
+2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14477              		.loc 1 2977 3 discriminator 5 view .LVU4331
+ 14478 0056 2368     		ldr	r3, [r4]
+ 14479 0058 196A     		ldr	r1, [r3, #32]
+ 14480 005a 41F21112 		movw	r2, #4369
+ 14481 005e 1142     		tst	r1, r2
+ 14482 0060 08D1     		bne	.L1148
+2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14483              		.loc 1 2977 3 discriminator 1 view .LVU4332
+ 14484 0062 196A     		ldr	r1, [r3, #32]
+ 14485 0064 40F24442 		movw	r2, #1092
+ 14486 0068 1142     		tst	r1, r2
+ 14487 006a 03D1     		bne	.L1148
+2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14488              		.loc 1 2977 3 discriminator 3 view .LVU4333
+ 14489 006c 1A68     		ldr	r2, [r3]
+ 14490 006e 22F00102 		bic	r2, r2, #1
+ 14491 0072 1A60     		str	r2, [r3]
+ 14492              	.L1148:
+2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14493              		.loc 1 2977 3 discriminator 5 view .LVU4334
+2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 14494              		.loc 1 2980 3 discriminator 5 view .LVU4335
+ 14495 0074 0123     		movs	r3, #1
+ 14496 0076 84F83E30 		strb	r3, [r4, #62]
+2981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 14497              		.loc 1 2981 3 discriminator 5 view .LVU4336
+ 14498 007a 84F83F30 		strb	r3, [r4, #63]
+2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 14499              		.loc 1 2982 3 discriminator 5 view .LVU4337
+ 14500 007e 84F84430 		strb	r3, [r4, #68]
+2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14501              		.loc 1 2983 3 discriminator 5 view .LVU4338
+ 14502 0082 84F84530 		strb	r3, [r4, #69]
+2986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 14503              		.loc 1 2986 3 discriminator 5 view .LVU4339
+ARM GAS  /tmp/ccPLZXyC.s 			page 458
+
+
+2987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14504              		.loc 1 2987 1 is_stmt 0 discriminator 5 view .LVU4340
+ 14505 0086 0020     		movs	r0, #0
+ 14506 0088 10BD     		pop	{r4, pc}
+ 14507              	.LVL1121:
+ 14508              	.L1151:
+2987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14509              		.loc 1 2987 1 discriminator 5 view .LVU4341
+ 14510 008a 00BF     		.align	2
+ 14511              	.L1150:
+ 14512 008c 00000140 		.word	1073807360
+ 14513 0090 00040140 		.word	1073808384
+ 14514              		.cfi_endproc
+ 14515              	.LFE188:
+ 14517              		.section	.text.HAL_TIM_Encoder_Start,"ax",%progbits
+ 14518              		.align	1
+ 14519              		.global	HAL_TIM_Encoder_Start
+ 14520              		.syntax unified
+ 14521              		.thumb
+ 14522              		.thumb_func
+ 14523              		.fpu fpv5-d16
+ 14525              	HAL_TIM_Encoder_Start:
+ 14526              	.LVL1122:
+ 14527              	.LFB193:
+3226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 14528              		.loc 1 3226 1 is_stmt 1 view -0
+ 14529              		.cfi_startproc
+ 14530              		@ args = 0, pretend = 0, frame = 0
+ 14531              		@ frame_needed = 0, uses_anonymous_args = 0
+3226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 14532              		.loc 1 3226 1 is_stmt 0 view .LVU4343
+ 14533 0000 38B5     		push	{r3, r4, r5, lr}
+ 14534              	.LCFI108:
+ 14535              		.cfi_def_cfa_offset 16
+ 14536              		.cfi_offset 3, -16
+ 14537              		.cfi_offset 4, -12
+ 14538              		.cfi_offset 5, -8
+ 14539              		.cfi_offset 14, -4
+ 14540 0002 0446     		mov	r4, r0
+3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14541              		.loc 1 3227 3 is_stmt 1 view .LVU4344
+3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14542              		.loc 1 3227 31 is_stmt 0 view .LVU4345
+ 14543 0004 90F83E30 		ldrb	r3, [r0, #62]	@ zero_extendqisi2
+ 14544 0008 DBB2     		uxtb	r3, r3
+ 14545              	.LVL1123:
+3228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14546              		.loc 1 3228 3 is_stmt 1 view .LVU4346
+3228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14547              		.loc 1 3228 31 is_stmt 0 view .LVU4347
+ 14548 000a 90F83F20 		ldrb	r2, [r0, #63]	@ zero_extendqisi2
+ 14549 000e 5FFA82FC 		uxtb	ip, r2
+ 14550              	.LVL1124:
+3229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14551              		.loc 1 3229 3 is_stmt 1 view .LVU4348
+3229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14552              		.loc 1 3229 31 is_stmt 0 view .LVU4349
+ARM GAS  /tmp/ccPLZXyC.s 			page 459
+
+
+ 14553 0012 90F84420 		ldrb	r2, [r0, #68]	@ zero_extendqisi2
+ 14554 0016 D0B2     		uxtb	r0, r2
+ 14555              	.LVL1125:
+3230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14556              		.loc 1 3230 3 is_stmt 1 view .LVU4350
+3230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14557              		.loc 1 3230 31 is_stmt 0 view .LVU4351
+ 14558 0018 94F84520 		ldrb	r2, [r4, #69]	@ zero_extendqisi2
+ 14559              	.LVL1126:
+3233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14560              		.loc 1 3233 3 is_stmt 1 view .LVU4352
+3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14561              		.loc 1 3236 3 view .LVU4353
+3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14562              		.loc 1 3236 6 is_stmt 0 view .LVU4354
+ 14563 001c 0D46     		mov	r5, r1
+ 14564 001e B1B9     		cbnz	r1, .L1153
+3238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ 14565              		.loc 1 3238 5 is_stmt 1 view .LVU4355
+3238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ 14566              		.loc 1 3238 8 is_stmt 0 view .LVU4356
+ 14567 0020 0128     		cmp	r0, #1
+ 14568 0022 08BF     		it	eq
+ 14569 0024 012B     		cmpeq	r3, #1
+ 14570 0026 47D1     		bne	.L1161
+3245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14571              		.loc 1 3245 7 is_stmt 1 view .LVU4357
+ 14572 0028 0223     		movs	r3, #2
+ 14573              	.LVL1127:
+3245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14574              		.loc 1 3245 7 is_stmt 0 view .LVU4358
+ 14575 002a 84F83E30 		strb	r3, [r4, #62]
+3246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14576              		.loc 1 3246 7 is_stmt 1 view .LVU4359
+ 14577 002e 84F84430 		strb	r3, [r4, #68]
+ 14578              	.LVL1128:
+ 14579              	.L1155:
+3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14580              		.loc 1 3281 3 view .LVU4360
+ 14581 0032 7DB3     		cbz	r5, .L1157
+ 14582 0034 042D     		cmp	r5, #4
+ 14583 0036 39D0     		beq	.L1158
+3297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14584              		.loc 1 3297 7 view .LVU4361
+ 14585 0038 0122     		movs	r2, #1
+ 14586 003a 0021     		movs	r1, #0
+ 14587              	.LVL1129:
+3297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14588              		.loc 1 3297 7 is_stmt 0 view .LVU4362
+ 14589 003c 2068     		ldr	r0, [r4]
+ 14590              	.LVL1130:
+3297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14591              		.loc 1 3297 7 view .LVU4363
+ 14592 003e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14593              	.LVL1131:
+3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14594              		.loc 1 3298 7 is_stmt 1 view .LVU4364
+ARM GAS  /tmp/ccPLZXyC.s 			page 460
+
+
+ 14595 0042 0122     		movs	r2, #1
+ 14596 0044 0421     		movs	r1, #4
+ 14597 0046 2068     		ldr	r0, [r4]
+ 14598 0048 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14599              	.LVL1132:
+3299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14600              		.loc 1 3299 7 view .LVU4365
+ 14601 004c 27E0     		b	.L1160
+ 14602              	.LVL1133:
+ 14603              	.L1153:
+3299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14604              		.loc 1 3299 7 is_stmt 0 view .LVU4366
+ 14605 004e D2B2     		uxtb	r2, r2
+3249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14606              		.loc 1 3249 8 is_stmt 1 view .LVU4367
+3249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14607              		.loc 1 3249 11 is_stmt 0 view .LVU4368
+ 14608 0050 0429     		cmp	r1, #4
+ 14609 0052 14D0     		beq	.L1167
+3264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 14610              		.loc 1 3264 5 is_stmt 1 view .LVU4369
+3264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 14611              		.loc 1 3264 8 is_stmt 0 view .LVU4370
+ 14612 0054 BCF1010F 		cmp	ip, #1
+ 14613 0058 08BF     		it	eq
+ 14614 005a 012B     		cmpeq	r3, #1
+ 14615 005c 30D1     		bne	.L1163
+3267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 14616              		.loc 1 3267 43 view .LVU4371
+ 14617 005e 013A     		subs	r2, r2, #1
+ 14618              	.LVL1134:
+3267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 14619              		.loc 1 3267 43 view .LVU4372
+ 14620 0060 18BF     		it	ne
+ 14621 0062 0122     		movne	r2, #1
+ 14622              	.LVL1135:
+3267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 14623              		.loc 1 3267 9 view .LVU4373
+ 14624 0064 0128     		cmp	r0, #1
+ 14625 0066 2DD1     		bne	.L1164
+ 14626 0068 62BB     		cbnz	r2, .L1164
+3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14627              		.loc 1 3273 7 is_stmt 1 view .LVU4374
+ 14628 006a 0223     		movs	r3, #2
+ 14629              	.LVL1136:
+3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14630              		.loc 1 3273 7 is_stmt 0 view .LVU4375
+ 14631 006c 84F83E30 		strb	r3, [r4, #62]
+3274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14632              		.loc 1 3274 7 is_stmt 1 view .LVU4376
+ 14633 0070 84F83F30 		strb	r3, [r4, #63]
+3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14634              		.loc 1 3275 7 view .LVU4377
+ 14635 0074 84F84430 		strb	r3, [r4, #68]
+3276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14636              		.loc 1 3276 7 view .LVU4378
+ 14637 0078 84F84530 		strb	r3, [r4, #69]
+ARM GAS  /tmp/ccPLZXyC.s 			page 461
+
+
+ 14638 007c D9E7     		b	.L1155
+ 14639              	.LVL1137:
+ 14640              	.L1167:
+3251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 14641              		.loc 1 3251 5 view .LVU4379
+3251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 14642              		.loc 1 3251 8 is_stmt 0 view .LVU4380
+ 14643 007e 012A     		cmp	r2, #1
+ 14644 0080 08BF     		it	eq
+ 14645 0082 BCF1010F 		cmpeq	ip, #1
+ 14646 0086 19D1     		bne	.L1162
+3258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14647              		.loc 1 3258 7 is_stmt 1 view .LVU4381
+ 14648 0088 0223     		movs	r3, #2
+ 14649              	.LVL1138:
+3258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14650              		.loc 1 3258 7 is_stmt 0 view .LVU4382
+ 14651 008a 84F83F30 		strb	r3, [r4, #63]
+3259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14652              		.loc 1 3259 7 is_stmt 1 view .LVU4383
+ 14653 008e 84F84530 		strb	r3, [r4, #69]
+ 14654 0092 CEE7     		b	.L1155
+ 14655              	.LVL1139:
+ 14656              	.L1157:
+3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14657              		.loc 1 3285 7 view .LVU4384
+ 14658 0094 0122     		movs	r2, #1
+ 14659 0096 0021     		movs	r1, #0
+ 14660              	.LVL1140:
+3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14661              		.loc 1 3285 7 is_stmt 0 view .LVU4385
+ 14662 0098 2068     		ldr	r0, [r4]
+ 14663              	.LVL1141:
+3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14664              		.loc 1 3285 7 view .LVU4386
+ 14665 009a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14666              	.LVL1142:
+3286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14667              		.loc 1 3286 7 is_stmt 1 view .LVU4387
+ 14668              	.L1160:
+3303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14669              		.loc 1 3303 3 view .LVU4388
+ 14670 009e 2268     		ldr	r2, [r4]
+ 14671 00a0 1368     		ldr	r3, [r2]
+ 14672 00a2 43F00103 		orr	r3, r3, #1
+ 14673 00a6 1360     		str	r3, [r2]
+3306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 14674              		.loc 1 3306 3 view .LVU4389
+3306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 14675              		.loc 1 3306 10 is_stmt 0 view .LVU4390
+ 14676 00a8 0020     		movs	r0, #0
+ 14677              	.L1154:
+3307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14678              		.loc 1 3307 1 view .LVU4391
+ 14679 00aa 38BD     		pop	{r3, r4, r5, pc}
+ 14680              	.LVL1143:
+ 14681              	.L1158:
+ARM GAS  /tmp/ccPLZXyC.s 			page 462
+
+
+3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14682              		.loc 1 3291 7 is_stmt 1 view .LVU4392
+ 14683 00ac 0122     		movs	r2, #1
+ 14684 00ae 0421     		movs	r1, #4
+ 14685              	.LVL1144:
+3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14686              		.loc 1 3291 7 is_stmt 0 view .LVU4393
+ 14687 00b0 2068     		ldr	r0, [r4]
+ 14688              	.LVL1145:
+3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14689              		.loc 1 3291 7 view .LVU4394
+ 14690 00b2 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14691              	.LVL1146:
+3292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14692              		.loc 1 3292 7 is_stmt 1 view .LVU4395
+ 14693 00b6 F2E7     		b	.L1160
+ 14694              	.LVL1147:
+ 14695              	.L1161:
+3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14696              		.loc 1 3241 14 is_stmt 0 view .LVU4396
+ 14697 00b8 0120     		movs	r0, #1
+ 14698              	.LVL1148:
+3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14699              		.loc 1 3241 14 view .LVU4397
+ 14700 00ba F6E7     		b	.L1154
+ 14701              	.LVL1149:
+ 14702              	.L1162:
+3254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14703              		.loc 1 3254 14 view .LVU4398
+ 14704 00bc 0120     		movs	r0, #1
+ 14705              	.LVL1150:
+3254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14706              		.loc 1 3254 14 view .LVU4399
+ 14707 00be F4E7     		b	.L1154
+ 14708              	.LVL1151:
+ 14709              	.L1163:
+3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14710              		.loc 1 3269 14 view .LVU4400
+ 14711 00c0 0120     		movs	r0, #1
+ 14712              	.LVL1152:
+3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14713              		.loc 1 3269 14 view .LVU4401
+ 14714 00c2 F2E7     		b	.L1154
+ 14715              	.LVL1153:
+ 14716              	.L1164:
+3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14717              		.loc 1 3269 14 view .LVU4402
+ 14718 00c4 0120     		movs	r0, #1
+ 14719              	.LVL1154:
+3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14720              		.loc 1 3269 14 view .LVU4403
+ 14721 00c6 F0E7     		b	.L1154
+ 14722              		.cfi_endproc
+ 14723              	.LFE193:
+ 14725              		.section	.text.HAL_TIM_Encoder_Stop,"ax",%progbits
+ 14726              		.align	1
+ 14727              		.global	HAL_TIM_Encoder_Stop
+ARM GAS  /tmp/ccPLZXyC.s 			page 463
+
+
+ 14728              		.syntax unified
+ 14729              		.thumb
+ 14730              		.thumb_func
+ 14731              		.fpu fpv5-d16
+ 14733              	HAL_TIM_Encoder_Stop:
+ 14734              	.LVL1155:
+ 14735              	.LFB194:
+3320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 14736              		.loc 1 3320 1 is_stmt 1 view -0
+ 14737              		.cfi_startproc
+ 14738              		@ args = 0, pretend = 0, frame = 0
+ 14739              		@ frame_needed = 0, uses_anonymous_args = 0
+3320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 14740              		.loc 1 3320 1 is_stmt 0 view .LVU4405
+ 14741 0000 38B5     		push	{r3, r4, r5, lr}
+ 14742              	.LCFI109:
+ 14743              		.cfi_def_cfa_offset 16
+ 14744              		.cfi_offset 3, -16
+ 14745              		.cfi_offset 4, -12
+ 14746              		.cfi_offset 5, -8
+ 14747              		.cfi_offset 14, -4
+ 14748 0002 0446     		mov	r4, r0
+3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14749              		.loc 1 3322 3 is_stmt 1 view .LVU4406
+3326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14750              		.loc 1 3326 3 view .LVU4407
+ 14751 0004 0D46     		mov	r5, r1
+ 14752 0006 61B1     		cbz	r1, .L1169
+ 14753 0008 0429     		cmp	r1, #4
+ 14754 000a 2BD0     		beq	.L1170
+3342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14755              		.loc 1 3342 7 view .LVU4408
+ 14756 000c 0022     		movs	r2, #0
+ 14757 000e 1146     		mov	r1, r2
+ 14758              	.LVL1156:
+3342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14759              		.loc 1 3342 7 is_stmt 0 view .LVU4409
+ 14760 0010 0068     		ldr	r0, [r0]
+ 14761              	.LVL1157:
+3342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 14762              		.loc 1 3342 7 view .LVU4410
+ 14763 0012 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14764              	.LVL1158:
+3343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14765              		.loc 1 3343 7 is_stmt 1 view .LVU4411
+ 14766 0016 0022     		movs	r2, #0
+ 14767 0018 0421     		movs	r1, #4
+ 14768 001a 2068     		ldr	r0, [r4]
+ 14769 001c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14770              	.LVL1159:
+3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14771              		.loc 1 3344 7 view .LVU4412
+ 14772 0020 04E0     		b	.L1172
+ 14773              	.LVL1160:
+ 14774              	.L1169:
+3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14775              		.loc 1 3330 7 view .LVU4413
+ARM GAS  /tmp/ccPLZXyC.s 			page 464
+
+
+ 14776 0022 0022     		movs	r2, #0
+ 14777 0024 1146     		mov	r1, r2
+ 14778              	.LVL1161:
+3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14779              		.loc 1 3330 7 is_stmt 0 view .LVU4414
+ 14780 0026 0068     		ldr	r0, [r0]
+ 14781              	.LVL1162:
+3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14782              		.loc 1 3330 7 view .LVU4415
+ 14783 0028 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14784              	.LVL1163:
+3331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14785              		.loc 1 3331 7 is_stmt 1 view .LVU4416
+ 14786              	.L1172:
+3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14787              		.loc 1 3349 3 view .LVU4417
+3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14788              		.loc 1 3349 3 view .LVU4418
+ 14789 002c 2368     		ldr	r3, [r4]
+ 14790 002e 196A     		ldr	r1, [r3, #32]
+ 14791 0030 41F21112 		movw	r2, #4369
+ 14792 0034 1142     		tst	r1, r2
+ 14793 0036 08D1     		bne	.L1173
+3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14794              		.loc 1 3349 3 discriminator 1 view .LVU4419
+ 14795 0038 196A     		ldr	r1, [r3, #32]
+ 14796 003a 40F24442 		movw	r2, #1092
+ 14797 003e 1142     		tst	r1, r2
+ 14798 0040 03D1     		bne	.L1173
+3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14799              		.loc 1 3349 3 discriminator 3 view .LVU4420
+ 14800 0042 1A68     		ldr	r2, [r3]
+ 14801 0044 22F00102 		bic	r2, r2, #1
+ 14802 0048 1A60     		str	r2, [r3]
+ 14803              	.L1173:
+3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14804              		.loc 1 3349 3 discriminator 5 view .LVU4421
+3352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14805              		.loc 1 3352 3 discriminator 5 view .LVU4422
+3352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14806              		.loc 1 3352 6 is_stmt 0 discriminator 5 view .LVU4423
+ 14807 004a 042D     		cmp	r5, #4
+ 14808 004c 18BF     		it	ne
+ 14809 004e 002D     		cmpne	r5, #0
+ 14810 0050 3AD1     		bne	.L1174
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14811              		.loc 1 3354 5 is_stmt 1 view .LVU4424
+ 14812 0052 6DB9     		cbnz	r5, .L1175
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14813              		.loc 1 3354 5 is_stmt 0 discriminator 1 view .LVU4425
+ 14814 0054 0123     		movs	r3, #1
+ 14815 0056 84F83E30 		strb	r3, [r4, #62]
+ 14816              	.L1176:
+3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14817              		.loc 1 3355 5 is_stmt 1 view .LVU4426
+ 14818 005a 2DBB     		cbnz	r5, .L1181
+3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ARM GAS  /tmp/ccPLZXyC.s 			page 465
+
+
+ 14819              		.loc 1 3355 5 is_stmt 0 discriminator 1 view .LVU4427
+ 14820 005c 0123     		movs	r3, #1
+ 14821 005e 84F84430 		strb	r3, [r4, #68]
+ 14822 0062 3AE0     		b	.L1182
+ 14823              	.LVL1164:
+ 14824              	.L1170:
+3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14825              		.loc 1 3336 7 is_stmt 1 view .LVU4428
+ 14826 0064 0022     		movs	r2, #0
+ 14827 0066 0421     		movs	r1, #4
+ 14828              	.LVL1165:
+3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14829              		.loc 1 3336 7 is_stmt 0 view .LVU4429
+ 14830 0068 0068     		ldr	r0, [r0]
+ 14831              	.LVL1166:
+3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 14832              		.loc 1 3336 7 view .LVU4430
+ 14833 006a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14834              	.LVL1167:
+3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14835              		.loc 1 3337 7 is_stmt 1 view .LVU4431
+ 14836 006e DDE7     		b	.L1172
+ 14837              	.L1175:
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14838              		.loc 1 3354 5 is_stmt 0 discriminator 2 view .LVU4432
+ 14839 0070 042D     		cmp	r5, #4
+ 14840 0072 09D0     		beq	.L1187
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14841              		.loc 1 3354 5 discriminator 4 view .LVU4433
+ 14842 0074 082D     		cmp	r5, #8
+ 14843 0076 0BD0     		beq	.L1188
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14844              		.loc 1 3354 5 discriminator 7 view .LVU4434
+ 14845 0078 0C2D     		cmp	r5, #12
+ 14846 007a 0DD0     		beq	.L1189
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14847              		.loc 1 3354 5 discriminator 10 view .LVU4435
+ 14848 007c 102D     		cmp	r5, #16
+ 14849 007e 0FD0     		beq	.L1190
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14850              		.loc 1 3354 5 discriminator 13 view .LVU4436
+ 14851 0080 0123     		movs	r3, #1
+ 14852 0082 84F84330 		strb	r3, [r4, #67]
+ 14853 0086 E8E7     		b	.L1176
+ 14854              	.L1187:
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14855              		.loc 1 3354 5 discriminator 3 view .LVU4437
+ 14856 0088 0123     		movs	r3, #1
+ 14857 008a 84F83F30 		strb	r3, [r4, #63]
+ 14858 008e E4E7     		b	.L1176
+ 14859              	.L1188:
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14860              		.loc 1 3354 5 discriminator 6 view .LVU4438
+ 14861 0090 0123     		movs	r3, #1
+ 14862 0092 84F84030 		strb	r3, [r4, #64]
+ 14863 0096 E0E7     		b	.L1176
+ 14864              	.L1189:
+ARM GAS  /tmp/ccPLZXyC.s 			page 466
+
+
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14865              		.loc 1 3354 5 discriminator 9 view .LVU4439
+ 14866 0098 0123     		movs	r3, #1
+ 14867 009a 84F84130 		strb	r3, [r4, #65]
+ 14868 009e DCE7     		b	.L1176
+ 14869              	.L1190:
+3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 14870              		.loc 1 3354 5 discriminator 12 view .LVU4440
+ 14871 00a0 0123     		movs	r3, #1
+ 14872 00a2 84F84230 		strb	r3, [r4, #66]
+ 14873 00a6 D8E7     		b	.L1176
+ 14874              	.L1181:
+3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14875              		.loc 1 3355 5 discriminator 2 view .LVU4441
+ 14876 00a8 042D     		cmp	r5, #4
+ 14877 00aa 05D0     		beq	.L1191
+3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14878              		.loc 1 3355 5 discriminator 4 view .LVU4442
+ 14879 00ac 082D     		cmp	r5, #8
+ 14880 00ae 07D0     		beq	.L1192
+3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14881              		.loc 1 3355 5 discriminator 7 view .LVU4443
+ 14882 00b0 0123     		movs	r3, #1
+ 14883 00b2 84F84730 		strb	r3, [r4, #71]
+ 14884 00b6 10E0     		b	.L1182
+ 14885              	.L1191:
+3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14886              		.loc 1 3355 5 discriminator 3 view .LVU4444
+ 14887 00b8 0123     		movs	r3, #1
+ 14888 00ba 84F84530 		strb	r3, [r4, #69]
+ 14889 00be 0CE0     		b	.L1182
+ 14890              	.L1192:
+3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14891              		.loc 1 3355 5 discriminator 6 view .LVU4445
+ 14892 00c0 0123     		movs	r3, #1
+ 14893 00c2 84F84630 		strb	r3, [r4, #70]
+ 14894 00c6 08E0     		b	.L1182
+ 14895              	.L1174:
+3359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 14896              		.loc 1 3359 5 is_stmt 1 view .LVU4446
+ 14897 00c8 0123     		movs	r3, #1
+ 14898 00ca 84F83E30 		strb	r3, [r4, #62]
+3360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 14899              		.loc 1 3360 5 view .LVU4447
+ 14900 00ce 84F83F30 		strb	r3, [r4, #63]
+3361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 14901              		.loc 1 3361 5 view .LVU4448
+ 14902 00d2 84F84430 		strb	r3, [r4, #68]
+3362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 14903              		.loc 1 3362 5 view .LVU4449
+ 14904 00d6 84F84530 		strb	r3, [r4, #69]
+ 14905              	.L1182:
+3366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 14906              		.loc 1 3366 3 view .LVU4450
+3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14907              		.loc 1 3367 1 is_stmt 0 view .LVU4451
+ 14908 00da 0020     		movs	r0, #0
+ARM GAS  /tmp/ccPLZXyC.s 			page 467
+
+
+ 14909 00dc 38BD     		pop	{r3, r4, r5, pc}
+3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14910              		.loc 1 3367 1 view .LVU4452
+ 14911              		.cfi_endproc
+ 14912              	.LFE194:
+ 14914              		.section	.text.HAL_TIM_Encoder_Start_IT,"ax",%progbits
+ 14915              		.align	1
+ 14916              		.global	HAL_TIM_Encoder_Start_IT
+ 14917              		.syntax unified
+ 14918              		.thumb
+ 14919              		.thumb_func
+ 14920              		.fpu fpv5-d16
+ 14922              	HAL_TIM_Encoder_Start_IT:
+ 14923              	.LVL1168:
+ 14924              	.LFB195:
+3380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 14925              		.loc 1 3380 1 is_stmt 1 view -0
+ 14926              		.cfi_startproc
+ 14927              		@ args = 0, pretend = 0, frame = 0
+ 14928              		@ frame_needed = 0, uses_anonymous_args = 0
+3380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 14929              		.loc 1 3380 1 is_stmt 0 view .LVU4454
+ 14930 0000 38B5     		push	{r3, r4, r5, lr}
+ 14931              	.LCFI110:
+ 14932              		.cfi_def_cfa_offset 16
+ 14933              		.cfi_offset 3, -16
+ 14934              		.cfi_offset 4, -12
+ 14935              		.cfi_offset 5, -8
+ 14936              		.cfi_offset 14, -4
+ 14937 0002 0446     		mov	r4, r0
+3381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14938              		.loc 1 3381 3 is_stmt 1 view .LVU4455
+3381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 14939              		.loc 1 3381 31 is_stmt 0 view .LVU4456
+ 14940 0004 90F83E30 		ldrb	r3, [r0, #62]	@ zero_extendqisi2
+ 14941 0008 DBB2     		uxtb	r3, r3
+ 14942              	.LVL1169:
+3382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14943              		.loc 1 3382 3 is_stmt 1 view .LVU4457
+3382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14944              		.loc 1 3382 31 is_stmt 0 view .LVU4458
+ 14945 000a 90F83F20 		ldrb	r2, [r0, #63]	@ zero_extendqisi2
+ 14946 000e 5FFA82FC 		uxtb	ip, r2
+ 14947              	.LVL1170:
+3383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14948              		.loc 1 3383 3 is_stmt 1 view .LVU4459
+3383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 14949              		.loc 1 3383 31 is_stmt 0 view .LVU4460
+ 14950 0012 90F84420 		ldrb	r2, [r0, #68]	@ zero_extendqisi2
+ 14951 0016 D0B2     		uxtb	r0, r2
+ 14952              	.LVL1171:
+3384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14953              		.loc 1 3384 3 is_stmt 1 view .LVU4461
+3384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14954              		.loc 1 3384 31 is_stmt 0 view .LVU4462
+ 14955 0018 94F84520 		ldrb	r2, [r4, #69]	@ zero_extendqisi2
+ 14956              	.LVL1172:
+ARM GAS  /tmp/ccPLZXyC.s 			page 468
+
+
+3387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 14957              		.loc 1 3387 3 is_stmt 1 view .LVU4463
+3390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14958              		.loc 1 3390 3 view .LVU4464
+3390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14959              		.loc 1 3390 6 is_stmt 0 view .LVU4465
+ 14960 001c 0D46     		mov	r5, r1
+ 14961 001e 09BB     		cbnz	r1, .L1194
+3392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ 14962              		.loc 1 3392 5 is_stmt 1 view .LVU4466
+3392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ 14963              		.loc 1 3392 8 is_stmt 0 view .LVU4467
+ 14964 0020 0128     		cmp	r0, #1
+ 14965 0022 08BF     		it	eq
+ 14966 0024 012B     		cmpeq	r3, #1
+ 14967 0026 5DD1     		bne	.L1202
+3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14968              		.loc 1 3399 7 is_stmt 1 view .LVU4468
+ 14969 0028 0223     		movs	r3, #2
+ 14970              	.LVL1173:
+3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 14971              		.loc 1 3399 7 is_stmt 0 view .LVU4469
+ 14972 002a 84F83E30 		strb	r3, [r4, #62]
+3400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 14973              		.loc 1 3400 7 is_stmt 1 view .LVU4470
+ 14974 002e 84F84430 		strb	r3, [r4, #68]
+ 14975              	.LVL1174:
+ 14976              	.L1196:
+3436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 14977              		.loc 1 3436 3 view .LVU4471
+ 14978 0032 002D     		cmp	r5, #0
+ 14979 0034 3AD0     		beq	.L1198
+ 14980 0036 042D     		cmp	r5, #4
+ 14981 0038 49D0     		beq	.L1199
+3454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14982              		.loc 1 3454 7 view .LVU4472
+ 14983 003a 0122     		movs	r2, #1
+ 14984 003c 0021     		movs	r1, #0
+ 14985              	.LVL1175:
+3454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14986              		.loc 1 3454 7 is_stmt 0 view .LVU4473
+ 14987 003e 2068     		ldr	r0, [r4]
+ 14988              	.LVL1176:
+3454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 14989              		.loc 1 3454 7 view .LVU4474
+ 14990 0040 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14991              	.LVL1177:
+3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 14992              		.loc 1 3455 7 is_stmt 1 view .LVU4475
+ 14993 0044 0122     		movs	r2, #1
+ 14994 0046 0421     		movs	r1, #4
+ 14995 0048 2068     		ldr	r0, [r4]
+ 14996 004a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 14997              	.LVL1178:
+3456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 14998              		.loc 1 3456 7 view .LVU4476
+ 14999 004e 2268     		ldr	r2, [r4]
+ARM GAS  /tmp/ccPLZXyC.s 			page 469
+
+
+ 15000 0050 D368     		ldr	r3, [r2, #12]
+ 15001 0052 43F00203 		orr	r3, r3, #2
+ 15002 0056 D360     		str	r3, [r2, #12]
+3457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 15003              		.loc 1 3457 7 view .LVU4477
+ 15004 0058 2268     		ldr	r2, [r4]
+ 15005 005a D368     		ldr	r3, [r2, #12]
+ 15006 005c 43F00403 		orr	r3, r3, #4
+ 15007 0060 D360     		str	r3, [r2, #12]
+3458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15008              		.loc 1 3458 7 view .LVU4478
+ 15009 0062 2DE0     		b	.L1201
+ 15010              	.LVL1179:
+ 15011              	.L1194:
+3458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15012              		.loc 1 3458 7 is_stmt 0 view .LVU4479
+ 15013 0064 D2B2     		uxtb	r2, r2
+3403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15014              		.loc 1 3403 8 is_stmt 1 view .LVU4480
+3403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15015              		.loc 1 3403 11 is_stmt 0 view .LVU4481
+ 15016 0066 0429     		cmp	r1, #4
+ 15017 0068 15D0     		beq	.L1208
+3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15018              		.loc 1 3418 5 is_stmt 1 view .LVU4482
+3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 15019              		.loc 1 3418 8 is_stmt 0 view .LVU4483
+ 15020 006a BCF1010F 		cmp	ip, #1
+ 15021 006e 08BF     		it	eq
+ 15022 0070 012B     		cmpeq	r3, #1
+ 15023 0072 3BD1     		bne	.L1204
+3421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 15024              		.loc 1 3421 43 view .LVU4484
+ 15025 0074 013A     		subs	r2, r2, #1
+ 15026              	.LVL1180:
+3421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 15027              		.loc 1 3421 43 view .LVU4485
+ 15028 0076 18BF     		it	ne
+ 15029 0078 0122     		movne	r2, #1
+ 15030              	.LVL1181:
+3421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 15031              		.loc 1 3421 9 view .LVU4486
+ 15032 007a 0128     		cmp	r0, #1
+ 15033 007c 38D1     		bne	.L1205
+ 15034 007e 002A     		cmp	r2, #0
+ 15035 0080 36D1     		bne	.L1205
+3427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15036              		.loc 1 3427 7 is_stmt 1 view .LVU4487
+ 15037 0082 0223     		movs	r3, #2
+ 15038              	.LVL1182:
+3427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15039              		.loc 1 3427 7 is_stmt 0 view .LVU4488
+ 15040 0084 84F83E30 		strb	r3, [r4, #62]
+3428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15041              		.loc 1 3428 7 is_stmt 1 view .LVU4489
+ 15042 0088 84F83F30 		strb	r3, [r4, #63]
+3429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ARM GAS  /tmp/ccPLZXyC.s 			page 470
+
+
+ 15043              		.loc 1 3429 7 view .LVU4490
+ 15044 008c 84F84430 		strb	r3, [r4, #68]
+3430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15045              		.loc 1 3430 7 view .LVU4491
+ 15046 0090 84F84530 		strb	r3, [r4, #69]
+ 15047 0094 CDE7     		b	.L1196
+ 15048              	.LVL1183:
+ 15049              	.L1208:
+3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15050              		.loc 1 3405 5 view .LVU4492
+3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 15051              		.loc 1 3405 8 is_stmt 0 view .LVU4493
+ 15052 0096 012A     		cmp	r2, #1
+ 15053 0098 08BF     		it	eq
+ 15054 009a BCF1010F 		cmpeq	ip, #1
+ 15055 009e 23D1     		bne	.L1203
+3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15056              		.loc 1 3412 7 is_stmt 1 view .LVU4494
+ 15057 00a0 0223     		movs	r3, #2
+ 15058              	.LVL1184:
+3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15059              		.loc 1 3412 7 is_stmt 0 view .LVU4495
+ 15060 00a2 84F83F30 		strb	r3, [r4, #63]
+3413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15061              		.loc 1 3413 7 is_stmt 1 view .LVU4496
+ 15062 00a6 84F84530 		strb	r3, [r4, #69]
+ 15063 00aa C2E7     		b	.L1196
+ 15064              	.LVL1185:
+ 15065              	.L1198:
+3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 15066              		.loc 1 3440 7 view .LVU4497
+ 15067 00ac 0122     		movs	r2, #1
+ 15068 00ae 0021     		movs	r1, #0
+ 15069              	.LVL1186:
+3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 15070              		.loc 1 3440 7 is_stmt 0 view .LVU4498
+ 15071 00b0 2068     		ldr	r0, [r4]
+ 15072              	.LVL1187:
+3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 15073              		.loc 1 3440 7 view .LVU4499
+ 15074 00b2 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15075              	.LVL1188:
+3441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 15076              		.loc 1 3441 7 is_stmt 1 view .LVU4500
+ 15077 00b6 2268     		ldr	r2, [r4]
+ 15078 00b8 D368     		ldr	r3, [r2, #12]
+ 15079 00ba 43F00203 		orr	r3, r3, #2
+ 15080 00be D360     		str	r3, [r2, #12]
+3442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15081              		.loc 1 3442 7 view .LVU4501
+ 15082              	.L1201:
+3463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15083              		.loc 1 3463 3 view .LVU4502
+ 15084 00c0 2268     		ldr	r2, [r4]
+ 15085 00c2 1368     		ldr	r3, [r2]
+ 15086 00c4 43F00103 		orr	r3, r3, #1
+ 15087 00c8 1360     		str	r3, [r2]
+ARM GAS  /tmp/ccPLZXyC.s 			page 471
+
+
+3466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 15088              		.loc 1 3466 3 view .LVU4503
+3466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 15089              		.loc 1 3466 10 is_stmt 0 view .LVU4504
+ 15090 00ca 0020     		movs	r0, #0
+ 15091              	.L1195:
+3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15092              		.loc 1 3467 1 view .LVU4505
+ 15093 00cc 38BD     		pop	{r3, r4, r5, pc}
+ 15094              	.LVL1189:
+ 15095              	.L1199:
+3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 15096              		.loc 1 3447 7 is_stmt 1 view .LVU4506
+ 15097 00ce 0122     		movs	r2, #1
+ 15098 00d0 0421     		movs	r1, #4
+ 15099              	.LVL1190:
+3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 15100              		.loc 1 3447 7 is_stmt 0 view .LVU4507
+ 15101 00d2 2068     		ldr	r0, [r4]
+ 15102              	.LVL1191:
+3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 15103              		.loc 1 3447 7 view .LVU4508
+ 15104 00d4 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15105              	.LVL1192:
+3448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       break;
+ 15106              		.loc 1 3448 7 is_stmt 1 view .LVU4509
+ 15107 00d8 2268     		ldr	r2, [r4]
+ 15108 00da D368     		ldr	r3, [r2, #12]
+ 15109 00dc 43F00403 		orr	r3, r3, #4
+ 15110 00e0 D360     		str	r3, [r2, #12]
+3449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15111              		.loc 1 3449 7 view .LVU4510
+ 15112 00e2 EDE7     		b	.L1201
+ 15113              	.LVL1193:
+ 15114              	.L1202:
+3395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15115              		.loc 1 3395 14 is_stmt 0 view .LVU4511
+ 15116 00e4 0120     		movs	r0, #1
+ 15117              	.LVL1194:
+3395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15118              		.loc 1 3395 14 view .LVU4512
+ 15119 00e6 F1E7     		b	.L1195
+ 15120              	.LVL1195:
+ 15121              	.L1203:
+3408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15122              		.loc 1 3408 14 view .LVU4513
+ 15123 00e8 0120     		movs	r0, #1
+ 15124              	.LVL1196:
+3408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15125              		.loc 1 3408 14 view .LVU4514
+ 15126 00ea EFE7     		b	.L1195
+ 15127              	.LVL1197:
+ 15128              	.L1204:
+3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15129              		.loc 1 3423 14 view .LVU4515
+ 15130 00ec 0120     		movs	r0, #1
+ 15131              	.LVL1198:
+ARM GAS  /tmp/ccPLZXyC.s 			page 472
+
+
+3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15132              		.loc 1 3423 14 view .LVU4516
+ 15133 00ee EDE7     		b	.L1195
+ 15134              	.LVL1199:
+ 15135              	.L1205:
+3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15136              		.loc 1 3423 14 view .LVU4517
+ 15137 00f0 0120     		movs	r0, #1
+ 15138              	.LVL1200:
+3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15139              		.loc 1 3423 14 view .LVU4518
+ 15140 00f2 EBE7     		b	.L1195
+ 15141              		.cfi_endproc
+ 15142              	.LFE195:
+ 15144              		.section	.text.HAL_TIM_Encoder_Stop_IT,"ax",%progbits
+ 15145              		.align	1
+ 15146              		.global	HAL_TIM_Encoder_Stop_IT
+ 15147              		.syntax unified
+ 15148              		.thumb
+ 15149              		.thumb_func
+ 15150              		.fpu fpv5-d16
+ 15152              	HAL_TIM_Encoder_Stop_IT:
+ 15153              	.LVL1201:
+ 15154              	.LFB196:
+3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 15155              		.loc 1 3480 1 is_stmt 1 view -0
+ 15156              		.cfi_startproc
+ 15157              		@ args = 0, pretend = 0, frame = 0
+ 15158              		@ frame_needed = 0, uses_anonymous_args = 0
+3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 15159              		.loc 1 3480 1 is_stmt 0 view .LVU4520
+ 15160 0000 38B5     		push	{r3, r4, r5, lr}
+ 15161              	.LCFI111:
+ 15162              		.cfi_def_cfa_offset 16
+ 15163              		.cfi_offset 3, -16
+ 15164              		.cfi_offset 4, -12
+ 15165              		.cfi_offset 5, -8
+ 15166              		.cfi_offset 14, -4
+ 15167 0002 0446     		mov	r4, r0
+3482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15168              		.loc 1 3482 3 is_stmt 1 view .LVU4521
+3486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15169              		.loc 1 3486 3 view .LVU4522
+3486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15170              		.loc 1 3486 6 is_stmt 0 view .LVU4523
+ 15171 0004 0D46     		mov	r5, r1
+ 15172 0006 0029     		cmp	r1, #0
+ 15173 0008 31D0     		beq	.L1226
+3493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15174              		.loc 1 3493 8 is_stmt 1 view .LVU4524
+3493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15175              		.loc 1 3493 11 is_stmt 0 view .LVU4525
+ 15176 000a 0429     		cmp	r1, #4
+ 15177 000c 3AD0     		beq	.L1227
+3502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15178              		.loc 1 3502 5 is_stmt 1 view .LVU4526
+ 15179 000e 0022     		movs	r2, #0
+ARM GAS  /tmp/ccPLZXyC.s 			page 473
+
+
+ 15180 0010 1146     		mov	r1, r2
+ 15181              	.LVL1202:
+3502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15182              		.loc 1 3502 5 is_stmt 0 view .LVU4527
+ 15183 0012 0068     		ldr	r0, [r0]
+ 15184              	.LVL1203:
+3502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15185              		.loc 1 3502 5 view .LVU4528
+ 15186 0014 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15187              	.LVL1204:
+3503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15188              		.loc 1 3503 5 is_stmt 1 view .LVU4529
+ 15189 0018 0022     		movs	r2, #0
+ 15190 001a 0421     		movs	r1, #4
+ 15191 001c 2068     		ldr	r0, [r4]
+ 15192 001e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15193              	.LVL1205:
+3506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ 15194              		.loc 1 3506 5 view .LVU4530
+ 15195 0022 2268     		ldr	r2, [r4]
+ 15196 0024 D368     		ldr	r3, [r2, #12]
+ 15197 0026 23F00203 		bic	r3, r3, #2
+ 15198 002a D360     		str	r3, [r2, #12]
+3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15199              		.loc 1 3507 5 view .LVU4531
+ 15200 002c 2268     		ldr	r2, [r4]
+ 15201 002e D368     		ldr	r3, [r2, #12]
+ 15202 0030 23F00403 		bic	r3, r3, #4
+ 15203 0034 D360     		str	r3, [r2, #12]
+ 15204              	.L1211:
+3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15205              		.loc 1 3511 3 view .LVU4532
+3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15206              		.loc 1 3511 3 view .LVU4533
+ 15207 0036 2368     		ldr	r3, [r4]
+ 15208 0038 196A     		ldr	r1, [r3, #32]
+ 15209 003a 41F21112 		movw	r2, #4369
+ 15210 003e 1142     		tst	r1, r2
+ 15211 0040 08D1     		bne	.L1213
+3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15212              		.loc 1 3511 3 discriminator 1 view .LVU4534
+ 15213 0042 196A     		ldr	r1, [r3, #32]
+ 15214 0044 40F24442 		movw	r2, #1092
+ 15215 0048 1142     		tst	r1, r2
+ 15216 004a 03D1     		bne	.L1213
+3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15217              		.loc 1 3511 3 discriminator 3 view .LVU4535
+ 15218 004c 1A68     		ldr	r2, [r3]
+ 15219 004e 22F00102 		bic	r2, r2, #1
+ 15220 0052 1A60     		str	r2, [r3]
+ 15221              	.L1213:
+3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15222              		.loc 1 3511 3 discriminator 5 view .LVU4536
+3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15223              		.loc 1 3514 3 discriminator 5 view .LVU4537
+3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15224              		.loc 1 3514 6 is_stmt 0 discriminator 5 view .LVU4538
+ARM GAS  /tmp/ccPLZXyC.s 			page 474
+
+
+ 15225 0054 042D     		cmp	r5, #4
+ 15226 0056 18BF     		it	ne
+ 15227 0058 002D     		cmpne	r5, #0
+ 15228 005a 4AD1     		bne	.L1214
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15229              		.loc 1 3516 5 is_stmt 1 view .LVU4539
+ 15230 005c EDB9     		cbnz	r5, .L1215
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15231              		.loc 1 3516 5 is_stmt 0 discriminator 1 view .LVU4540
+ 15232 005e 0123     		movs	r3, #1
+ 15233 0060 84F83E30 		strb	r3, [r4, #62]
+ 15234              	.L1216:
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15235              		.loc 1 3517 5 is_stmt 1 view .LVU4541
+ 15236 0064 ADBB     		cbnz	r5, .L1221
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15237              		.loc 1 3517 5 is_stmt 0 discriminator 1 view .LVU4542
+ 15238 0066 0123     		movs	r3, #1
+ 15239 0068 84F84430 		strb	r3, [r4, #68]
+ 15240 006c 4AE0     		b	.L1222
+ 15241              	.LVL1206:
+ 15242              	.L1226:
+3488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15243              		.loc 1 3488 5 is_stmt 1 view .LVU4543
+ 15244 006e 0022     		movs	r2, #0
+ 15245 0070 1146     		mov	r1, r2
+ 15246              	.LVL1207:
+3488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15247              		.loc 1 3488 5 is_stmt 0 view .LVU4544
+ 15248 0072 0068     		ldr	r0, [r0]
+ 15249              	.LVL1208:
+3488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15250              		.loc 1 3488 5 view .LVU4545
+ 15251 0074 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15252              	.LVL1209:
+3491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15253              		.loc 1 3491 5 is_stmt 1 view .LVU4546
+ 15254 0078 2268     		ldr	r2, [r4]
+ 15255 007a D368     		ldr	r3, [r2, #12]
+ 15256 007c 23F00203 		bic	r3, r3, #2
+ 15257 0080 D360     		str	r3, [r2, #12]
+ 15258 0082 D8E7     		b	.L1211
+ 15259              	.LVL1210:
+ 15260              	.L1227:
+3495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15261              		.loc 1 3495 5 view .LVU4547
+ 15262 0084 0022     		movs	r2, #0
+ 15263 0086 0421     		movs	r1, #4
+ 15264              	.LVL1211:
+3495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15265              		.loc 1 3495 5 is_stmt 0 view .LVU4548
+ 15266 0088 0068     		ldr	r0, [r0]
+ 15267              	.LVL1212:
+3495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15268              		.loc 1 3495 5 view .LVU4549
+ 15269 008a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15270              	.LVL1213:
+ARM GAS  /tmp/ccPLZXyC.s 			page 475
+
+
+3498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15271              		.loc 1 3498 5 is_stmt 1 view .LVU4550
+ 15272 008e 2268     		ldr	r2, [r4]
+ 15273 0090 D368     		ldr	r3, [r2, #12]
+ 15274 0092 23F00403 		bic	r3, r3, #4
+ 15275 0096 D360     		str	r3, [r2, #12]
+ 15276 0098 CDE7     		b	.L1211
+ 15277              	.L1215:
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15278              		.loc 1 3516 5 is_stmt 0 discriminator 2 view .LVU4551
+ 15279 009a 042D     		cmp	r5, #4
+ 15280 009c 09D0     		beq	.L1228
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15281              		.loc 1 3516 5 discriminator 4 view .LVU4552
+ 15282 009e 082D     		cmp	r5, #8
+ 15283 00a0 0BD0     		beq	.L1229
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15284              		.loc 1 3516 5 discriminator 7 view .LVU4553
+ 15285 00a2 0C2D     		cmp	r5, #12
+ 15286 00a4 0DD0     		beq	.L1230
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15287              		.loc 1 3516 5 discriminator 10 view .LVU4554
+ 15288 00a6 102D     		cmp	r5, #16
+ 15289 00a8 0FD0     		beq	.L1231
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15290              		.loc 1 3516 5 discriminator 13 view .LVU4555
+ 15291 00aa 0123     		movs	r3, #1
+ 15292 00ac 84F84330 		strb	r3, [r4, #67]
+ 15293 00b0 D8E7     		b	.L1216
+ 15294              	.L1228:
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15295              		.loc 1 3516 5 discriminator 3 view .LVU4556
+ 15296 00b2 0123     		movs	r3, #1
+ 15297 00b4 84F83F30 		strb	r3, [r4, #63]
+ 15298 00b8 D4E7     		b	.L1216
+ 15299              	.L1229:
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15300              		.loc 1 3516 5 discriminator 6 view .LVU4557
+ 15301 00ba 0123     		movs	r3, #1
+ 15302 00bc 84F84030 		strb	r3, [r4, #64]
+ 15303 00c0 D0E7     		b	.L1216
+ 15304              	.L1230:
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15305              		.loc 1 3516 5 discriminator 9 view .LVU4558
+ 15306 00c2 0123     		movs	r3, #1
+ 15307 00c4 84F84130 		strb	r3, [r4, #65]
+ 15308 00c8 CCE7     		b	.L1216
+ 15309              	.L1231:
+3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15310              		.loc 1 3516 5 discriminator 12 view .LVU4559
+ 15311 00ca 0123     		movs	r3, #1
+ 15312 00cc 84F84230 		strb	r3, [r4, #66]
+ 15313 00d0 C8E7     		b	.L1216
+ 15314              	.L1221:
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15315              		.loc 1 3517 5 discriminator 2 view .LVU4560
+ 15316 00d2 042D     		cmp	r5, #4
+ARM GAS  /tmp/ccPLZXyC.s 			page 476
+
+
+ 15317 00d4 05D0     		beq	.L1232
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15318              		.loc 1 3517 5 discriminator 4 view .LVU4561
+ 15319 00d6 082D     		cmp	r5, #8
+ 15320 00d8 07D0     		beq	.L1233
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15321              		.loc 1 3517 5 discriminator 7 view .LVU4562
+ 15322 00da 0123     		movs	r3, #1
+ 15323 00dc 84F84730 		strb	r3, [r4, #71]
+ 15324 00e0 10E0     		b	.L1222
+ 15325              	.L1232:
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15326              		.loc 1 3517 5 discriminator 3 view .LVU4563
+ 15327 00e2 0123     		movs	r3, #1
+ 15328 00e4 84F84530 		strb	r3, [r4, #69]
+ 15329 00e8 0CE0     		b	.L1222
+ 15330              	.L1233:
+3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15331              		.loc 1 3517 5 discriminator 6 view .LVU4564
+ 15332 00ea 0123     		movs	r3, #1
+ 15333 00ec 84F84630 		strb	r3, [r4, #70]
+ 15334 00f0 08E0     		b	.L1222
+ 15335              	.L1214:
+3521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 15336              		.loc 1 3521 5 is_stmt 1 view .LVU4565
+ 15337 00f2 0123     		movs	r3, #1
+ 15338 00f4 84F83E30 		strb	r3, [r4, #62]
+3522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 15339              		.loc 1 3522 5 view .LVU4566
+ 15340 00f8 84F83F30 		strb	r3, [r4, #63]
+3523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 15341              		.loc 1 3523 5 view .LVU4567
+ 15342 00fc 84F84430 		strb	r3, [r4, #68]
+3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15343              		.loc 1 3524 5 view .LVU4568
+ 15344 0100 84F84530 		strb	r3, [r4, #69]
+ 15345              	.L1222:
+3528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 15346              		.loc 1 3528 3 view .LVU4569
+3529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15347              		.loc 1 3529 1 is_stmt 0 view .LVU4570
+ 15348 0104 0020     		movs	r0, #0
+ 15349 0106 38BD     		pop	{r3, r4, r5, pc}
+3529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15350              		.loc 1 3529 1 view .LVU4571
+ 15351              		.cfi_endproc
+ 15352              	.LFE196:
+ 15354              		.section	.text.HAL_TIM_Encoder_Start_DMA,"ax",%progbits
+ 15355              		.align	1
+ 15356              		.global	HAL_TIM_Encoder_Start_DMA
+ 15357              		.syntax unified
+ 15358              		.thumb
+ 15359              		.thumb_func
+ 15360              		.fpu fpv5-d16
+ 15362              	HAL_TIM_Encoder_Start_DMA:
+ 15363              	.LVL1214:
+ 15364              	.LFB197:
+ARM GAS  /tmp/ccPLZXyC.s 			page 477
+
+
+3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 15365              		.loc 1 3546 1 is_stmt 1 view -0
+ 15366              		.cfi_startproc
+ 15367              		@ args = 4, pretend = 0, frame = 0
+ 15368              		@ frame_needed = 0, uses_anonymous_args = 0
+3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 15369              		.loc 1 3546 1 is_stmt 0 view .LVU4573
+ 15370 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 15371              	.LCFI112:
+ 15372              		.cfi_def_cfa_offset 24
+ 15373              		.cfi_offset 3, -24
+ 15374              		.cfi_offset 4, -20
+ 15375              		.cfi_offset 5, -16
+ 15376              		.cfi_offset 6, -12
+ 15377              		.cfi_offset 7, -8
+ 15378              		.cfi_offset 14, -4
+ 15379 0002 0446     		mov	r4, r0
+ 15380 0004 1D46     		mov	r5, r3
+ 15381 0006 BDF81860 		ldrh	r6, [sp, #24]
+3547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 15382              		.loc 1 3547 3 is_stmt 1 view .LVU4574
+3547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 15383              		.loc 1 3547 31 is_stmt 0 view .LVU4575
+ 15384 000a 90F83E00 		ldrb	r0, [r0, #62]	@ zero_extendqisi2
+ 15385              	.LVL1215:
+3547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 15386              		.loc 1 3547 31 view .LVU4576
+ 15387 000e C0B2     		uxtb	r0, r0
+ 15388              	.LVL1216:
+3548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15389              		.loc 1 3548 3 is_stmt 1 view .LVU4577
+3548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15390              		.loc 1 3548 31 is_stmt 0 view .LVU4578
+ 15391 0010 94F83F30 		ldrb	r3, [r4, #63]	@ zero_extendqisi2
+ 15392              	.LVL1217:
+3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15393              		.loc 1 3549 3 is_stmt 1 view .LVU4579
+3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 15394              		.loc 1 3549 31 is_stmt 0 view .LVU4580
+ 15395 0014 94F844C0 		ldrb	ip, [r4, #68]	@ zero_extendqisi2
+ 15396 0018 5FFA8CFC 		uxtb	ip, ip
+ 15397              	.LVL1218:
+3550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15398              		.loc 1 3550 3 is_stmt 1 view .LVU4581
+3550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15399              		.loc 1 3550 31 is_stmt 0 view .LVU4582
+ 15400 001c 94F845E0 		ldrb	lr, [r4, #69]	@ zero_extendqisi2
+ 15401              	.LVL1219:
+3553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15402              		.loc 1 3553 3 is_stmt 1 view .LVU4583
+3556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15403              		.loc 1 3556 3 view .LVU4584
+3556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15404              		.loc 1 3556 6 is_stmt 0 view .LVU4585
+ 15405 0020 0F46     		mov	r7, r1
+ 15406 0022 71BB     		cbnz	r1, .L1235
+3558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ARM GAS  /tmp/ccPLZXyC.s 			page 478
+
+
+ 15407              		.loc 1 3558 5 is_stmt 1 view .LVU4586
+3558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 15408              		.loc 1 3558 8 is_stmt 0 view .LVU4587
+ 15409 0024 BCF1020F 		cmp	ip, #2
+ 15410 0028 18BF     		it	ne
+ 15411 002a 0228     		cmpne	r0, #2
+ 15412 002c 00F0EE80 		beq	.L1242
+3563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ 15413              		.loc 1 3563 10 is_stmt 1 view .LVU4588
+3563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ 15414              		.loc 1 3563 13 is_stmt 0 view .LVU4589
+ 15415 0030 0128     		cmp	r0, #1
+ 15416 0032 08BF     		it	eq
+ 15417 0034 BCF1010F 		cmpeq	ip, #1
+ 15418 0038 40F0EA80 		bne	.L1243
+3566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 15419              		.loc 1 3566 7 is_stmt 1 view .LVU4590
+3566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 15420              		.loc 1 3566 10 is_stmt 0 view .LVU4591
+ 15421 003c 002E     		cmp	r6, #0
+ 15422 003e 18BF     		it	ne
+ 15423 0040 002A     		cmpne	r2, #0
+ 15424 0042 00F0E880 		beq	.L1244
+3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15425              		.loc 1 3572 9 is_stmt 1 view .LVU4592
+ 15426 0046 0223     		movs	r3, #2
+ 15427              	.LVL1220:
+3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15428              		.loc 1 3572 9 is_stmt 0 view .LVU4593
+ 15429 0048 84F83E30 		strb	r3, [r4, #62]
+3573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15430              		.loc 1 3573 9 is_stmt 1 view .LVU4594
+ 15431 004c 84F84430 		strb	r3, [r4, #68]
+ 15432              	.LVL1221:
+ 15433              	.L1237:
+3638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15434              		.loc 1 3638 3 view .LVU4595
+ 15435 0050 002F     		cmp	r7, #0
+ 15436 0052 66D0     		beq	.L1239
+ 15437 0054 042F     		cmp	r7, #4
+ 15438 0056 00F08780 		beq	.L1240
+3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15439              		.loc 1 3698 7 view .LVU4596
+3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15440              		.loc 1 3698 17 is_stmt 0 view .LVU4597
+ 15441 005a 636A     		ldr	r3, [r4, #36]
+3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15442              		.loc 1 3698 52 view .LVU4598
+ 15443 005c 7849     		ldr	r1, .L1265
+ 15444 005e D963     		str	r1, [r3, #60]
+3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15445              		.loc 1 3699 7 is_stmt 1 view .LVU4599
+3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15446              		.loc 1 3699 17 is_stmt 0 view .LVU4600
+ 15447 0060 636A     		ldr	r3, [r4, #36]
+3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15448              		.loc 1 3699 56 view .LVU4601
+ARM GAS  /tmp/ccPLZXyC.s 			page 479
+
+
+ 15449 0062 7849     		ldr	r1, .L1265+4
+ 15450 0064 1964     		str	r1, [r3, #64]
+3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15451              		.loc 1 3702 7 is_stmt 1 view .LVU4602
+3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15452              		.loc 1 3702 17 is_stmt 0 view .LVU4603
+ 15453 0066 636A     		ldr	r3, [r4, #36]
+3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15454              		.loc 1 3702 53 view .LVU4604
+ 15455 0068 7749     		ldr	r1, .L1265+8
+ 15456 006a D964     		str	r1, [r3, #76]
+3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15457              		.loc 1 3705 7 is_stmt 1 view .LVU4605
+3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15458              		.loc 1 3705 71 is_stmt 0 view .LVU4606
+ 15459 006c 2168     		ldr	r1, [r4]
+3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15460              		.loc 1 3705 11 view .LVU4607
+ 15461 006e 3346     		mov	r3, r6
+ 15462 0070 3431     		adds	r1, r1, #52
+ 15463 0072 606A     		ldr	r0, [r4, #36]
+ 15464              	.LVL1222:
+3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15465              		.loc 1 3705 11 view .LVU4608
+ 15466 0074 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 15467              	.LVL1223:
+3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15468              		.loc 1 3705 10 view .LVU4609
+ 15469 0078 0028     		cmp	r0, #0
+ 15470 007a 00F09980 		beq	.L1260
+3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15471              		.loc 1 3709 16 view .LVU4610
+ 15472 007e 0125     		movs	r5, #1
+ 15473              	.LVL1224:
+3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15474              		.loc 1 3709 16 view .LVU4611
+ 15475 0080 C7E0     		b	.L1236
+ 15476              	.LVL1225:
+ 15477              	.L1235:
+3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15478              		.loc 1 3709 16 view .LVU4612
+ 15479 0082 DBB2     		uxtb	r3, r3
+3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15480              		.loc 1 3709 16 view .LVU4613
+ 15481 0084 5FFA8EFE 		uxtb	lr, lr
+3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15482              		.loc 1 3581 8 is_stmt 1 view .LVU4614
+3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15483              		.loc 1 3581 11 is_stmt 0 view .LVU4615
+ 15484 0088 0429     		cmp	r1, #4
+ 15485 008a 33D0     		beq	.L1261
+3608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ 15486              		.loc 1 3608 5 is_stmt 1 view .LVU4616
+3608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ 15487              		.loc 1 3608 8 is_stmt 0 view .LVU4617
+ 15488 008c 022B     		cmp	r3, #2
+ 15489 008e 18BF     		it	ne
+ARM GAS  /tmp/ccPLZXyC.s 			page 480
+
+
+ 15490 0090 0228     		cmpne	r0, #2
+ 15491 0092 00F0C880 		beq	.L1248
+3611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 15492              		.loc 1 3611 43 view .LVU4618
+ 15493 0096 BEF1020F 		cmp	lr, #2
+ 15494 009a 14BF     		ite	ne
+ 15495 009c 0021     		movne	r1, #0
+ 15496              	.LVL1226:
+3611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 15497              		.loc 1 3611 43 view .LVU4619
+ 15498 009e 0121     		moveq	r1, #1
+3611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 15499              		.loc 1 3611 9 view .LVU4620
+ 15500 00a0 BCF1020F 		cmp	ip, #2
+ 15501 00a4 00F0C180 		beq	.L1249
+ 15502 00a8 0029     		cmp	r1, #0
+ 15503 00aa 40F0BE80 		bne	.L1249
+3615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ 15504              		.loc 1 3615 10 is_stmt 1 view .LVU4621
+3615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ 15505              		.loc 1 3615 13 is_stmt 0 view .LVU4622
+ 15506 00ae 0128     		cmp	r0, #1
+ 15507 00b0 08BF     		it	eq
+ 15508 00b2 012B     		cmpeq	r3, #1
+ 15509 00b4 40F0BB80 		bne	.L1250
+3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 15510              		.loc 1 3618 48 view .LVU4623
+ 15511 00b8 BEF1010F 		cmp	lr, #1
+ 15512 00bc 14BF     		ite	ne
+ 15513 00be 0023     		movne	r3, #0
+ 15514              	.LVL1227:
+3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 15515              		.loc 1 3618 48 view .LVU4624
+ 15516 00c0 0123     		moveq	r3, #1
+3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     {
+ 15517              		.loc 1 3618 14 view .LVU4625
+ 15518 00c2 BCF1010F 		cmp	ip, #1
+ 15519 00c6 40F0B480 		bne	.L1251
+ 15520 00ca 002B     		cmp	r3, #0
+ 15521 00cc 00F0B180 		beq	.L1251
+3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 15522              		.loc 1 3620 7 is_stmt 1 view .LVU4626
+3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 15523              		.loc 1 3620 10 is_stmt 0 view .LVU4627
+ 15524 00d0 002D     		cmp	r5, #0
+ 15525 00d2 18BF     		it	ne
+ 15526 00d4 002A     		cmpne	r2, #0
+ 15527 00d6 00F0AE80 		beq	.L1252
+3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 15528              		.loc 1 3620 52 discriminator 1 view .LVU4628
+ 15529 00da 002E     		cmp	r6, #0
+ 15530 00dc 00F0AD80 		beq	.L1253
+3626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15531              		.loc 1 3626 9 is_stmt 1 view .LVU4629
+ 15532 00e0 0223     		movs	r3, #2
+ 15533 00e2 84F83E30 		strb	r3, [r4, #62]
+3627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ARM GAS  /tmp/ccPLZXyC.s 			page 481
+
+
+ 15534              		.loc 1 3627 9 view .LVU4630
+ 15535 00e6 84F83F30 		strb	r3, [r4, #63]
+3628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15536              		.loc 1 3628 9 view .LVU4631
+ 15537 00ea 84F84430 		strb	r3, [r4, #68]
+3629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15538              		.loc 1 3629 9 view .LVU4632
+ 15539 00ee 84F84530 		strb	r3, [r4, #69]
+3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 15540              		.loc 1 3620 10 is_stmt 0 view .LVU4633
+ 15541 00f2 ADE7     		b	.L1237
+ 15542              	.LVL1228:
+ 15543              	.L1261:
+3583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 15544              		.loc 1 3583 5 is_stmt 1 view .LVU4634
+3583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 15545              		.loc 1 3583 8 is_stmt 0 view .LVU4635
+ 15546 00f4 BEF1020F 		cmp	lr, #2
+ 15547 00f8 18BF     		it	ne
+ 15548 00fa 022B     		cmpne	r3, #2
+ 15549 00fc 00F08D80 		beq	.L1245
+3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ 15550              		.loc 1 3588 10 is_stmt 1 view .LVU4636
+3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ 15551              		.loc 1 3588 13 is_stmt 0 view .LVU4637
+ 15552 0100 012B     		cmp	r3, #1
+ 15553 0102 08BF     		it	eq
+ 15554 0104 BEF1010F 		cmpeq	lr, #1
+ 15555 0108 40F08980 		bne	.L1246
+3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 15556              		.loc 1 3591 7 is_stmt 1 view .LVU4638
+3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       {
+ 15557              		.loc 1 3591 10 is_stmt 0 view .LVU4639
+ 15558 010c 002E     		cmp	r6, #0
+ 15559 010e 18BF     		it	ne
+ 15560 0110 002D     		cmpne	r5, #0
+ 15561 0112 00F08680 		beq	.L1247
+3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15562              		.loc 1 3597 9 is_stmt 1 view .LVU4640
+ 15563 0116 0223     		movs	r3, #2
+ 15564              	.LVL1229:
+3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 15565              		.loc 1 3597 9 is_stmt 0 view .LVU4641
+ 15566 0118 84F83F30 		strb	r3, [r4, #63]
+3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15567              		.loc 1 3598 9 is_stmt 1 view .LVU4642
+ 15568 011c 84F84530 		strb	r3, [r4, #69]
+ 15569 0120 96E7     		b	.L1237
+ 15570              	.LVL1230:
+ 15571              	.L1239:
+3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15572              		.loc 1 3643 7 view .LVU4643
+3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15573              		.loc 1 3643 17 is_stmt 0 view .LVU4644
+ 15574 0122 636A     		ldr	r3, [r4, #36]
+3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15575              		.loc 1 3643 52 view .LVU4645
+ARM GAS  /tmp/ccPLZXyC.s 			page 482
+
+
+ 15576 0124 4649     		ldr	r1, .L1265
+ 15577 0126 D963     		str	r1, [r3, #60]
+3644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15578              		.loc 1 3644 7 is_stmt 1 view .LVU4646
+3644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15579              		.loc 1 3644 17 is_stmt 0 view .LVU4647
+ 15580 0128 636A     		ldr	r3, [r4, #36]
+3644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15581              		.loc 1 3644 56 view .LVU4648
+ 15582 012a 4649     		ldr	r1, .L1265+4
+ 15583 012c 1964     		str	r1, [r3, #64]
+3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15584              		.loc 1 3647 7 is_stmt 1 view .LVU4649
+3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15585              		.loc 1 3647 17 is_stmt 0 view .LVU4650
+ 15586 012e 636A     		ldr	r3, [r4, #36]
+3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15587              		.loc 1 3647 53 view .LVU4651
+ 15588 0130 4549     		ldr	r1, .L1265+8
+ 15589 0132 D964     		str	r1, [r3, #76]
+3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15590              		.loc 1 3650 7 is_stmt 1 view .LVU4652
+3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15591              		.loc 1 3650 71 is_stmt 0 view .LVU4653
+ 15592 0134 2168     		ldr	r1, [r4]
+3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15593              		.loc 1 3650 11 view .LVU4654
+ 15594 0136 3346     		mov	r3, r6
+ 15595 0138 3431     		adds	r1, r1, #52
+ 15596 013a 606A     		ldr	r0, [r4, #36]
+ 15597              	.LVL1231:
+3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15598              		.loc 1 3650 11 view .LVU4655
+ 15599 013c FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 15600              	.LVL1232:
+3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15601              		.loc 1 3650 10 view .LVU4656
+ 15602 0140 0546     		mov	r5, r0
+ 15603              	.LVL1233:
+3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15604              		.loc 1 3650 10 view .LVU4657
+ 15605 0142 08B1     		cbz	r0, .L1262
+3654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15606              		.loc 1 3654 16 view .LVU4658
+ 15607 0144 0125     		movs	r5, #1
+ 15608 0146 64E0     		b	.L1236
+ 15609              	.L1262:
+3657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15610              		.loc 1 3657 7 is_stmt 1 view .LVU4659
+ 15611 0148 2268     		ldr	r2, [r4]
+ 15612 014a D368     		ldr	r3, [r2, #12]
+ 15613 014c 43F40073 		orr	r3, r3, #512
+ 15614 0150 D360     		str	r3, [r2, #12]
+3660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15615              		.loc 1 3660 7 view .LVU4660
+ 15616 0152 0122     		movs	r2, #1
+ 15617 0154 0021     		movs	r1, #0
+ARM GAS  /tmp/ccPLZXyC.s 			page 483
+
+
+ 15618 0156 2068     		ldr	r0, [r4]
+ 15619 0158 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15620              	.LVL1234:
+3663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15621              		.loc 1 3663 7 view .LVU4661
+ 15622 015c 2268     		ldr	r2, [r4]
+ 15623 015e 1368     		ldr	r3, [r2]
+ 15624 0160 43F00103 		orr	r3, r3, #1
+ 15625 0164 1360     		str	r3, [r2]
+3665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15626              		.loc 1 3665 7 view .LVU4662
+ 15627 0166 54E0     		b	.L1236
+ 15628              	.LVL1235:
+ 15629              	.L1240:
+3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15630              		.loc 1 3671 7 view .LVU4663
+3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15631              		.loc 1 3671 17 is_stmt 0 view .LVU4664
+ 15632 0168 A36A     		ldr	r3, [r4, #40]
+3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15633              		.loc 1 3671 52 view .LVU4665
+ 15634 016a 354A     		ldr	r2, .L1265
+ 15635              	.LVL1236:
+3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15636              		.loc 1 3671 52 view .LVU4666
+ 15637 016c DA63     		str	r2, [r3, #60]
+3672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15638              		.loc 1 3672 7 is_stmt 1 view .LVU4667
+3672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15639              		.loc 1 3672 17 is_stmt 0 view .LVU4668
+ 15640 016e A36A     		ldr	r3, [r4, #40]
+3672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15641              		.loc 1 3672 56 view .LVU4669
+ 15642 0170 344A     		ldr	r2, .L1265+4
+ 15643 0172 1A64     		str	r2, [r3, #64]
+3675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+ 15644              		.loc 1 3675 7 is_stmt 1 view .LVU4670
+3675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+ 15645              		.loc 1 3675 17 is_stmt 0 view .LVU4671
+ 15646 0174 A36A     		ldr	r3, [r4, #40]
+3675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the DMA stream */
+ 15647              		.loc 1 3675 53 view .LVU4672
+ 15648 0176 344A     		ldr	r2, .L1265+8
+ 15649 0178 DA64     		str	r2, [r3, #76]
+3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15650              		.loc 1 3677 7 is_stmt 1 view .LVU4673
+3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15651              		.loc 1 3677 71 is_stmt 0 view .LVU4674
+ 15652 017a 2168     		ldr	r1, [r4]
+3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15653              		.loc 1 3677 11 view .LVU4675
+ 15654 017c 3346     		mov	r3, r6
+ 15655 017e 2A46     		mov	r2, r5
+ 15656 0180 3831     		adds	r1, r1, #56
+ 15657 0182 A06A     		ldr	r0, [r4, #40]
+ 15658              	.LVL1237:
+3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ARM GAS  /tmp/ccPLZXyC.s 			page 484
+
+
+ 15659              		.loc 1 3677 11 view .LVU4676
+ 15660 0184 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 15661              	.LVL1238:
+3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15662              		.loc 1 3677 10 view .LVU4677
+ 15663 0188 0546     		mov	r5, r0
+ 15664              	.LVL1239:
+3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15665              		.loc 1 3677 10 view .LVU4678
+ 15666 018a 08B1     		cbz	r0, .L1263
+3681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15667              		.loc 1 3681 16 view .LVU4679
+ 15668 018c 0125     		movs	r5, #1
+ 15669 018e 40E0     		b	.L1236
+ 15670              	.L1263:
+3684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15671              		.loc 1 3684 7 is_stmt 1 view .LVU4680
+ 15672 0190 2268     		ldr	r2, [r4]
+ 15673 0192 D368     		ldr	r3, [r2, #12]
+ 15674 0194 43F48063 		orr	r3, r3, #1024
+ 15675 0198 D360     		str	r3, [r2, #12]
+3687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15676              		.loc 1 3687 7 view .LVU4681
+ 15677 019a 0122     		movs	r2, #1
+ 15678 019c 0421     		movs	r1, #4
+ 15679 019e 2068     		ldr	r0, [r4]
+ 15680 01a0 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15681              	.LVL1240:
+3690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15682              		.loc 1 3690 7 view .LVU4682
+ 15683 01a4 2268     		ldr	r2, [r4]
+ 15684 01a6 1368     		ldr	r3, [r2]
+ 15685 01a8 43F00103 		orr	r3, r3, #1
+ 15686 01ac 1360     		str	r3, [r2]
+3692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15687              		.loc 1 3692 7 view .LVU4683
+ 15688 01ae 30E0     		b	.L1236
+ 15689              	.LVL1241:
+ 15690              	.L1260:
+3713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15691              		.loc 1 3713 7 view .LVU4684
+3713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15692              		.loc 1 3713 17 is_stmt 0 view .LVU4685
+ 15693 01b0 A36A     		ldr	r3, [r4, #40]
+3713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 15694              		.loc 1 3713 52 view .LVU4686
+ 15695 01b2 234A     		ldr	r2, .L1265
+ 15696 01b4 DA63     		str	r2, [r3, #60]
+3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15697              		.loc 1 3714 7 is_stmt 1 view .LVU4687
+3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15698              		.loc 1 3714 17 is_stmt 0 view .LVU4688
+ 15699 01b6 A36A     		ldr	r3, [r4, #40]
+3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15700              		.loc 1 3714 56 view .LVU4689
+ 15701 01b8 224A     		ldr	r2, .L1265+4
+ 15702 01ba 1A64     		str	r2, [r3, #64]
+ARM GAS  /tmp/ccPLZXyC.s 			page 485
+
+
+3717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15703              		.loc 1 3717 7 is_stmt 1 view .LVU4690
+3717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15704              		.loc 1 3717 17 is_stmt 0 view .LVU4691
+ 15705 01bc A36A     		ldr	r3, [r4, #40]
+3717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15706              		.loc 1 3717 53 view .LVU4692
+ 15707 01be 224A     		ldr	r2, .L1265+8
+ 15708 01c0 DA64     		str	r2, [r3, #76]
+3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15709              		.loc 1 3720 7 is_stmt 1 view .LVU4693
+3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15710              		.loc 1 3720 71 is_stmt 0 view .LVU4694
+ 15711 01c2 2168     		ldr	r1, [r4]
+3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15712              		.loc 1 3720 11 view .LVU4695
+ 15713 01c4 3346     		mov	r3, r6
+ 15714 01c6 2A46     		mov	r2, r5
+ 15715 01c8 3831     		adds	r1, r1, #56
+ 15716 01ca A06A     		ldr	r0, [r4, #40]
+ 15717 01cc FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 15718              	.LVL1242:
+3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15719              		.loc 1 3720 10 view .LVU4696
+ 15720 01d0 0546     		mov	r5, r0
+ 15721              	.LVL1243:
+3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****                            Length) != HAL_OK)
+ 15722              		.loc 1 3720 10 view .LVU4697
+ 15723 01d2 08B1     		cbz	r0, .L1264
+3724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15724              		.loc 1 3724 16 view .LVU4698
+ 15725 01d4 0125     		movs	r5, #1
+ 15726 01d6 1CE0     		b	.L1236
+ 15727              	.L1264:
+3728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       /* Enable the TIM Input Capture  DMA request */
+ 15728              		.loc 1 3728 7 is_stmt 1 view .LVU4699
+ 15729 01d8 2268     		ldr	r2, [r4]
+ 15730 01da D368     		ldr	r3, [r2, #12]
+ 15731 01dc 43F40073 		orr	r3, r3, #512
+ 15732 01e0 D360     		str	r3, [r2, #12]
+3730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15733              		.loc 1 3730 7 view .LVU4700
+ 15734 01e2 2268     		ldr	r2, [r4]
+ 15735 01e4 D368     		ldr	r3, [r2, #12]
+ 15736 01e6 43F48063 		orr	r3, r3, #1024
+ 15737 01ea D360     		str	r3, [r2, #12]
+3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 15738              		.loc 1 3733 7 view .LVU4701
+ 15739 01ec 0122     		movs	r2, #1
+ 15740 01ee 0021     		movs	r1, #0
+ 15741 01f0 2068     		ldr	r0, [r4]
+ 15742 01f2 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15743              	.LVL1244:
+3734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15744              		.loc 1 3734 7 view .LVU4702
+ 15745 01f6 0122     		movs	r2, #1
+ 15746 01f8 0421     		movs	r1, #4
+ARM GAS  /tmp/ccPLZXyC.s 			page 486
+
+
+ 15747 01fa 2068     		ldr	r0, [r4]
+ 15748 01fc FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15749              	.LVL1245:
+3737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15750              		.loc 1 3737 7 view .LVU4703
+ 15751 0200 2268     		ldr	r2, [r4]
+ 15752 0202 1368     		ldr	r3, [r2]
+ 15753 0204 43F00103 		orr	r3, r3, #1
+ 15754 0208 1360     		str	r3, [r2]
+3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15755              		.loc 1 3739 7 view .LVU4704
+ 15756 020a 02E0     		b	.L1236
+ 15757              	.LVL1246:
+ 15758              	.L1242:
+3561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15759              		.loc 1 3561 14 is_stmt 0 view .LVU4705
+ 15760 020c 0225     		movs	r5, #2
+ 15761              	.LVL1247:
+3561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15762              		.loc 1 3561 14 view .LVU4706
+ 15763 020e 00E0     		b	.L1236
+ 15764              	.LVL1248:
+ 15765              	.L1243:
+3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15766              		.loc 1 3578 14 view .LVU4707
+ 15767 0210 0125     		movs	r5, #1
+ 15768              	.LVL1249:
+ 15769              	.L1236:
+3745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15770              		.loc 1 3745 1 view .LVU4708
+ 15771 0212 2846     		mov	r0, r5
+ 15772 0214 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 15773              	.LVL1250:
+ 15774              	.L1244:
+3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15775              		.loc 1 3568 16 view .LVU4709
+ 15776 0216 0125     		movs	r5, #1
+ 15777              	.LVL1251:
+3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15778              		.loc 1 3568 16 view .LVU4710
+ 15779 0218 FBE7     		b	.L1236
+ 15780              	.LVL1252:
+ 15781              	.L1245:
+3586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15782              		.loc 1 3586 14 view .LVU4711
+ 15783 021a 0225     		movs	r5, #2
+ 15784              	.LVL1253:
+3586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15785              		.loc 1 3586 14 view .LVU4712
+ 15786 021c F9E7     		b	.L1236
+ 15787              	.LVL1254:
+ 15788              	.L1246:
+3603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15789              		.loc 1 3603 14 view .LVU4713
+ 15790 021e 0125     		movs	r5, #1
+ 15791              	.LVL1255:
+3603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ARM GAS  /tmp/ccPLZXyC.s 			page 487
+
+
+ 15792              		.loc 1 3603 14 view .LVU4714
+ 15793 0220 F7E7     		b	.L1236
+ 15794              	.LVL1256:
+ 15795              	.L1247:
+3593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15796              		.loc 1 3593 16 view .LVU4715
+ 15797 0222 0125     		movs	r5, #1
+ 15798              	.LVL1257:
+3593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15799              		.loc 1 3593 16 view .LVU4716
+ 15800 0224 F5E7     		b	.L1236
+ 15801              	.LVL1258:
+ 15802              	.L1248:
+3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15803              		.loc 1 3613 14 view .LVU4717
+ 15804 0226 0225     		movs	r5, #2
+ 15805              	.LVL1259:
+3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15806              		.loc 1 3613 14 view .LVU4718
+ 15807 0228 F3E7     		b	.L1236
+ 15808              	.LVL1260:
+ 15809              	.L1249:
+3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15810              		.loc 1 3613 14 view .LVU4719
+ 15811 022a 0225     		movs	r5, #2
+ 15812              	.LVL1261:
+3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15813              		.loc 1 3613 14 view .LVU4720
+ 15814 022c F1E7     		b	.L1236
+ 15815              	.LVL1262:
+ 15816              	.L1250:
+3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15817              		.loc 1 3634 14 view .LVU4721
+ 15818 022e 0125     		movs	r5, #1
+ 15819              	.LVL1263:
+3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15820              		.loc 1 3634 14 view .LVU4722
+ 15821 0230 EFE7     		b	.L1236
+ 15822              	.LVL1264:
+ 15823              	.L1251:
+3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15824              		.loc 1 3634 14 view .LVU4723
+ 15825 0232 0125     		movs	r5, #1
+ 15826              	.LVL1265:
+3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     }
+ 15827              		.loc 1 3634 14 view .LVU4724
+ 15828 0234 EDE7     		b	.L1236
+ 15829              	.LVL1266:
+ 15830              	.L1252:
+3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15831              		.loc 1 3622 16 view .LVU4725
+ 15832 0236 0125     		movs	r5, #1
+ 15833              	.LVL1267:
+3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15834              		.loc 1 3622 16 view .LVU4726
+ 15835 0238 EBE7     		b	.L1236
+ 15836              	.LVL1268:
+ARM GAS  /tmp/ccPLZXyC.s 			page 488
+
+
+ 15837              	.L1253:
+3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15838              		.loc 1 3622 16 view .LVU4727
+ 15839 023a 0125     		movs	r5, #1
+ 15840              	.LVL1269:
+3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****       }
+ 15841              		.loc 1 3622 16 view .LVU4728
+ 15842 023c E9E7     		b	.L1236
+ 15843              	.L1266:
+ 15844 023e 00BF     		.align	2
+ 15845              	.L1265:
+ 15846 0240 00000000 		.word	TIM_DMACaptureCplt
+ 15847 0244 00000000 		.word	TIM_DMACaptureHalfCplt
+ 15848 0248 00000000 		.word	TIM_DMAError
+ 15849              		.cfi_endproc
+ 15850              	.LFE197:
+ 15852              		.section	.text.HAL_TIM_Encoder_Stop_DMA,"ax",%progbits
+ 15853              		.align	1
+ 15854              		.global	HAL_TIM_Encoder_Stop_DMA
+ 15855              		.syntax unified
+ 15856              		.thumb
+ 15857              		.thumb_func
+ 15858              		.fpu fpv5-d16
+ 15860              	HAL_TIM_Encoder_Stop_DMA:
+ 15861              	.LVL1270:
+ 15862              	.LFB198:
+3758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 15863              		.loc 1 3758 1 is_stmt 1 view -0
+ 15864              		.cfi_startproc
+ 15865              		@ args = 0, pretend = 0, frame = 0
+ 15866              		@ frame_needed = 0, uses_anonymous_args = 0
+3758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   /* Check the parameters */
+ 15867              		.loc 1 3758 1 is_stmt 0 view .LVU4730
+ 15868 0000 38B5     		push	{r3, r4, r5, lr}
+ 15869              	.LCFI113:
+ 15870              		.cfi_def_cfa_offset 16
+ 15871              		.cfi_offset 3, -16
+ 15872              		.cfi_offset 4, -12
+ 15873              		.cfi_offset 5, -8
+ 15874              		.cfi_offset 14, -4
+ 15875 0002 0446     		mov	r4, r0
+3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15876              		.loc 1 3760 3 is_stmt 1 view .LVU4731
+3764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15877              		.loc 1 3764 3 view .LVU4732
+3764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15878              		.loc 1 3764 6 is_stmt 0 view .LVU4733
+ 15879 0004 0D46     		mov	r5, r1
+ 15880 0006 0029     		cmp	r1, #0
+ 15881 0008 38D0     		beq	.L1284
+3772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15882              		.loc 1 3772 8 is_stmt 1 view .LVU4734
+3772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15883              		.loc 1 3772 11 is_stmt 0 view .LVU4735
+ 15884 000a 0429     		cmp	r1, #4
+ 15885 000c 44D0     		beq	.L1285
+3782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ARM GAS  /tmp/ccPLZXyC.s 			page 489
+
+
+ 15886              		.loc 1 3782 5 is_stmt 1 view .LVU4736
+ 15887 000e 0022     		movs	r2, #0
+ 15888 0010 1146     		mov	r1, r2
+ 15889              	.LVL1271:
+3782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15890              		.loc 1 3782 5 is_stmt 0 view .LVU4737
+ 15891 0012 0068     		ldr	r0, [r0]
+ 15892              	.LVL1272:
+3782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ 15893              		.loc 1 3782 5 view .LVU4738
+ 15894 0014 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15895              	.LVL1273:
+3783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15896              		.loc 1 3783 5 is_stmt 1 view .LVU4739
+ 15897 0018 0022     		movs	r2, #0
+ 15898 001a 0421     		movs	r1, #4
+ 15899 001c 2068     		ldr	r0, [r4]
+ 15900 001e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15901              	.LVL1274:
+3786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ 15902              		.loc 1 3786 5 view .LVU4740
+ 15903 0022 2268     		ldr	r2, [r4]
+ 15904 0024 D368     		ldr	r3, [r2, #12]
+ 15905 0026 23F40073 		bic	r3, r3, #512
+ 15906 002a D360     		str	r3, [r2, #12]
+3787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 15907              		.loc 1 3787 5 view .LVU4741
+ 15908 002c 2268     		ldr	r2, [r4]
+ 15909 002e D368     		ldr	r3, [r2, #12]
+ 15910 0030 23F48063 		bic	r3, r3, #1024
+ 15911 0034 D360     		str	r3, [r2, #12]
+3788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 15912              		.loc 1 3788 5 view .LVU4742
+3788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 15913              		.loc 1 3788 11 is_stmt 0 view .LVU4743
+ 15914 0036 606A     		ldr	r0, [r4, #36]
+ 15915 0038 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 15916              	.LVL1275:
+3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15917              		.loc 1 3789 5 is_stmt 1 view .LVU4744
+3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15918              		.loc 1 3789 11 is_stmt 0 view .LVU4745
+ 15919 003c A06A     		ldr	r0, [r4, #40]
+ 15920 003e FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 15921              	.LVL1276:
+ 15922              	.L1269:
+3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15923              		.loc 1 3793 3 is_stmt 1 view .LVU4746
+3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15924              		.loc 1 3793 3 view .LVU4747
+ 15925 0042 2368     		ldr	r3, [r4]
+ 15926 0044 196A     		ldr	r1, [r3, #32]
+ 15927 0046 41F21112 		movw	r2, #4369
+ 15928 004a 1142     		tst	r1, r2
+ 15929 004c 08D1     		bne	.L1271
+3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15930              		.loc 1 3793 3 discriminator 1 view .LVU4748
+ARM GAS  /tmp/ccPLZXyC.s 			page 490
+
+
+ 15931 004e 196A     		ldr	r1, [r3, #32]
+ 15932 0050 40F24442 		movw	r2, #1092
+ 15933 0054 1142     		tst	r1, r2
+ 15934 0056 03D1     		bne	.L1271
+3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15935              		.loc 1 3793 3 discriminator 3 view .LVU4749
+ 15936 0058 1A68     		ldr	r2, [r3]
+ 15937 005a 22F00102 		bic	r2, r2, #1
+ 15938 005e 1A60     		str	r2, [r3]
+ 15939              	.L1271:
+3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15940              		.loc 1 3793 3 discriminator 5 view .LVU4750
+3796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15941              		.loc 1 3796 3 discriminator 5 view .LVU4751
+3796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   {
+ 15942              		.loc 1 3796 6 is_stmt 0 discriminator 5 view .LVU4752
+ 15943 0060 042D     		cmp	r5, #4
+ 15944 0062 18BF     		it	ne
+ 15945 0064 002D     		cmpne	r5, #0
+ 15946 0066 51D1     		bne	.L1272
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15947              		.loc 1 3798 5 is_stmt 1 view .LVU4753
+ 15948 0068 25BB     		cbnz	r5, .L1273
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 15949              		.loc 1 3798 5 is_stmt 0 discriminator 1 view .LVU4754
+ 15950 006a 0123     		movs	r3, #1
+ 15951 006c 84F83E30 		strb	r3, [r4, #62]
+ 15952              	.L1274:
+3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15953              		.loc 1 3799 5 is_stmt 1 view .LVU4755
+ 15954 0070 002D     		cmp	r5, #0
+ 15955 0072 3BD1     		bne	.L1279
+3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15956              		.loc 1 3799 5 is_stmt 0 discriminator 1 view .LVU4756
+ 15957 0074 0123     		movs	r3, #1
+ 15958 0076 84F84430 		strb	r3, [r4, #68]
+ 15959 007a 50E0     		b	.L1280
+ 15960              	.LVL1277:
+ 15961              	.L1284:
+3766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15962              		.loc 1 3766 5 is_stmt 1 view .LVU4757
+ 15963 007c 0022     		movs	r2, #0
+ 15964 007e 1146     		mov	r1, r2
+ 15965              	.LVL1278:
+3766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15966              		.loc 1 3766 5 is_stmt 0 view .LVU4758
+ 15967 0080 0068     		ldr	r0, [r0]
+ 15968              	.LVL1279:
+3766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15969              		.loc 1 3766 5 view .LVU4759
+ 15970 0082 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15971              	.LVL1280:
+3769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 15972              		.loc 1 3769 5 is_stmt 1 view .LVU4760
+ 15973 0086 2268     		ldr	r2, [r4]
+ 15974 0088 D368     		ldr	r3, [r2, #12]
+ 15975 008a 23F40073 		bic	r3, r3, #512
+ARM GAS  /tmp/ccPLZXyC.s 			page 491
+
+
+ 15976 008e D360     		str	r3, [r2, #12]
+3770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15977              		.loc 1 3770 5 view .LVU4761
+3770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 15978              		.loc 1 3770 11 is_stmt 0 view .LVU4762
+ 15979 0090 606A     		ldr	r0, [r4, #36]
+ 15980 0092 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 15981              	.LVL1281:
+ 15982 0096 D4E7     		b	.L1269
+ 15983              	.LVL1282:
+ 15984              	.L1285:
+3774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15985              		.loc 1 3774 5 is_stmt 1 view .LVU4763
+ 15986 0098 0022     		movs	r2, #0
+ 15987 009a 0421     		movs	r1, #4
+ 15988              	.LVL1283:
+3774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15989              		.loc 1 3774 5 is_stmt 0 view .LVU4764
+ 15990 009c 0068     		ldr	r0, [r0]
+ 15991              	.LVL1284:
+3774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 15992              		.loc 1 3774 5 view .LVU4765
+ 15993 009e FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 15994              	.LVL1285:
+3777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 15995              		.loc 1 3777 5 is_stmt 1 view .LVU4766
+ 15996 00a2 2268     		ldr	r2, [r4]
+ 15997 00a4 D368     		ldr	r3, [r2, #12]
+ 15998 00a6 23F48063 		bic	r3, r3, #1024
+ 15999 00aa D360     		str	r3, [r2, #12]
+3778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 16000              		.loc 1 3778 5 view .LVU4767
+3778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 16001              		.loc 1 3778 11 is_stmt 0 view .LVU4768
+ 16002 00ac A06A     		ldr	r0, [r4, #40]
+ 16003 00ae FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 16004              	.LVL1286:
+ 16005 00b2 C6E7     		b	.L1269
+ 16006              	.L1273:
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16007              		.loc 1 3798 5 discriminator 2 view .LVU4769
+ 16008 00b4 042D     		cmp	r5, #4
+ 16009 00b6 09D0     		beq	.L1286
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16010              		.loc 1 3798 5 discriminator 4 view .LVU4770
+ 16011 00b8 082D     		cmp	r5, #8
+ 16012 00ba 0BD0     		beq	.L1287
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16013              		.loc 1 3798 5 discriminator 7 view .LVU4771
+ 16014 00bc 0C2D     		cmp	r5, #12
+ 16015 00be 0DD0     		beq	.L1288
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16016              		.loc 1 3798 5 discriminator 10 view .LVU4772
+ 16017 00c0 102D     		cmp	r5, #16
+ 16018 00c2 0FD0     		beq	.L1289
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16019              		.loc 1 3798 5 discriminator 13 view .LVU4773
+ARM GAS  /tmp/ccPLZXyC.s 			page 492
+
+
+ 16020 00c4 0123     		movs	r3, #1
+ 16021 00c6 84F84330 		strb	r3, [r4, #67]
+ 16022 00ca D1E7     		b	.L1274
+ 16023              	.L1286:
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16024              		.loc 1 3798 5 discriminator 3 view .LVU4774
+ 16025 00cc 0123     		movs	r3, #1
+ 16026 00ce 84F83F30 		strb	r3, [r4, #63]
+ 16027 00d2 CDE7     		b	.L1274
+ 16028              	.L1287:
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16029              		.loc 1 3798 5 discriminator 6 view .LVU4775
+ 16030 00d4 0123     		movs	r3, #1
+ 16031 00d6 84F84030 		strb	r3, [r4, #64]
+ 16032 00da C9E7     		b	.L1274
+ 16033              	.L1288:
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16034              		.loc 1 3798 5 discriminator 9 view .LVU4776
+ 16035 00dc 0123     		movs	r3, #1
+ 16036 00de 84F84130 		strb	r3, [r4, #65]
+ 16037 00e2 C5E7     		b	.L1274
+ 16038              	.L1289:
+3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 16039              		.loc 1 3798 5 discriminator 12 view .LVU4777
+ 16040 00e4 0123     		movs	r3, #1
+ 16041 00e6 84F84230 		strb	r3, [r4, #66]
+ 16042 00ea C1E7     		b	.L1274
+ 16043              	.L1279:
+3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 16044              		.loc 1 3799 5 discriminator 2 view .LVU4778
+ 16045 00ec 042D     		cmp	r5, #4
+ 16046 00ee 05D0     		beq	.L1290
+3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 16047              		.loc 1 3799 5 discriminator 4 view .LVU4779
+ 16048 00f0 082D     		cmp	r5, #8
+ 16049 00f2 07D0     		beq	.L1291
+3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 16050              		.loc 1 3799 5 discriminator 7 view .LVU4780
+ 16051 00f4 0123     		movs	r3, #1
+ 16052 00f6 84F84730 		strb	r3, [r4, #71]
+ 16053 00fa 10E0     		b	.L1280
+ 16054              	.L1290:
+3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 16055              		.loc 1 3799 5 discriminator 3 view .LVU4781
+ 16056 00fc 0123     		movs	r3, #1
+ 16057 00fe 84F84530 		strb	r3, [r4, #69]
+ 16058 0102 0CE0     		b	.L1280
+ 16059              	.L1291:
+3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 16060              		.loc 1 3799 5 discriminator 6 view .LVU4782
+ 16061 0104 0123     		movs	r3, #1
+ 16062 0106 84F84630 		strb	r3, [r4, #70]
+ 16063 010a 08E0     		b	.L1280
+ 16064              	.L1272:
+3803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 16065              		.loc 1 3803 5 is_stmt 1 view .LVU4783
+ 16066 010c 0123     		movs	r3, #1
+ARM GAS  /tmp/ccPLZXyC.s 			page 493
+
+
+ 16067 010e 84F83E30 		strb	r3, [r4, #62]
+3804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 16068              		.loc 1 3804 5 view .LVU4784
+ 16069 0112 84F83F30 		strb	r3, [r4, #63]
+3805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 16070              		.loc 1 3805 5 view .LVU4785
+ 16071 0116 84F84430 		strb	r3, [r4, #68]
+3806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c ****   }
+ 16072              		.loc 1 3806 5 view .LVU4786
+ 16073 011a 84F84530 		strb	r3, [r4, #69]
+ 16074              	.L1280:
+3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** }
+ 16075              		.loc 1 3810 3 view .LVU4787
+3811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 16076              		.loc 1 3811 1 is_stmt 0 view .LVU4788
+ 16077 011e 0020     		movs	r0, #0
+ 16078 0120 38BD     		pop	{r3, r4, r5, pc}
+3811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** 
+ 16079              		.loc 1 3811 1 view .LVU4789
+ 16080              		.cfi_endproc
+ 16081              	.LFE198:
+ 16083              		.text
+ 16084              	.Letext0:
+ 16085              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 16086              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 16087              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 16088              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 16089              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 16090              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h"
+ 16091              		.file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h"
+ARM GAS  /tmp/ccPLZXyC.s 			page 494
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_tim.c
+     /tmp/ccPLZXyC.s:17     .text.TIM_OC1_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:24     .text.TIM_OC1_SetConfig:0000000000000000 TIM_OC1_SetConfig
+     /tmp/ccPLZXyC.s:162    .text.TIM_OC1_SetConfig:000000000000005c $d
+     /tmp/ccPLZXyC.s:169    .text.TIM_OC3_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:175    .text.TIM_OC3_SetConfig:0000000000000000 TIM_OC3_SetConfig
+     /tmp/ccPLZXyC.s:312    .text.TIM_OC3_SetConfig:0000000000000064 $d
+     /tmp/ccPLZXyC.s:319    .text.TIM_OC4_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:325    .text.TIM_OC4_SetConfig:0000000000000000 TIM_OC4_SetConfig
+     /tmp/ccPLZXyC.s:431    .text.TIM_OC4_SetConfig:0000000000000048 $d
+     /tmp/ccPLZXyC.s:438    .text.TIM_OC5_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:444    .text.TIM_OC5_SetConfig:0000000000000000 TIM_OC5_SetConfig
+     /tmp/ccPLZXyC.s:548    .text.TIM_OC5_SetConfig:0000000000000048 $d
+     /tmp/ccPLZXyC.s:555    .text.TIM_OC6_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:561    .text.TIM_OC6_SetConfig:0000000000000000 TIM_OC6_SetConfig
+     /tmp/ccPLZXyC.s:665    .text.TIM_OC6_SetConfig:0000000000000048 $d
+     /tmp/ccPLZXyC.s:672    .text.TIM_TI1_ConfigInputStage:0000000000000000 $t
+     /tmp/ccPLZXyC.s:678    .text.TIM_TI1_ConfigInputStage:0000000000000000 TIM_TI1_ConfigInputStage
+     /tmp/ccPLZXyC.s:738    .text.TIM_TI2_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:744    .text.TIM_TI2_SetConfig:0000000000000000 TIM_TI2_SetConfig
+     /tmp/ccPLZXyC.s:824    .text.TIM_TI2_ConfigInputStage:0000000000000000 $t
+     /tmp/ccPLZXyC.s:830    .text.TIM_TI2_ConfigInputStage:0000000000000000 TIM_TI2_ConfigInputStage
+     /tmp/ccPLZXyC.s:890    .text.TIM_TI3_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:896    .text.TIM_TI3_SetConfig:0000000000000000 TIM_TI3_SetConfig
+     /tmp/ccPLZXyC.s:976    .text.TIM_TI4_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:982    .text.TIM_TI4_SetConfig:0000000000000000 TIM_TI4_SetConfig
+     /tmp/ccPLZXyC.s:1062   .text.TIM_ITRx_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1068   .text.TIM_ITRx_SetConfig:0000000000000000 TIM_ITRx_SetConfig
+     /tmp/ccPLZXyC.s:1101   .text.HAL_TIM_Base_MspInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1108   .text.HAL_TIM_Base_MspInit:0000000000000000 HAL_TIM_Base_MspInit
+     /tmp/ccPLZXyC.s:1123   .text.HAL_TIM_Base_MspDeInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1130   .text.HAL_TIM_Base_MspDeInit:0000000000000000 HAL_TIM_Base_MspDeInit
+     /tmp/ccPLZXyC.s:1145   .text.HAL_TIM_Base_DeInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1152   .text.HAL_TIM_Base_DeInit:0000000000000000 HAL_TIM_Base_DeInit
+     /tmp/ccPLZXyC.s:1238   .text.HAL_TIM_Base_Start:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1245   .text.HAL_TIM_Base_Start:0000000000000000 HAL_TIM_Base_Start
+     /tmp/ccPLZXyC.s:1351   .text.HAL_TIM_Base_Start:0000000000000080 $d
+     /tmp/ccPLZXyC.s:1357   .text.HAL_TIM_Base_Stop:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1364   .text.HAL_TIM_Base_Stop:0000000000000000 HAL_TIM_Base_Stop
+     /tmp/ccPLZXyC.s:1405   .text.HAL_TIM_Base_Start_IT:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1412   .text.HAL_TIM_Base_Start_IT:0000000000000000 HAL_TIM_Base_Start_IT
+     /tmp/ccPLZXyC.s:1523   .text.HAL_TIM_Base_Start_IT:0000000000000088 $d
+     /tmp/ccPLZXyC.s:1529   .text.HAL_TIM_Base_Stop_IT:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1536   .text.HAL_TIM_Base_Stop_IT:0000000000000000 HAL_TIM_Base_Stop_IT
+     /tmp/ccPLZXyC.s:1582   .text.HAL_TIM_Base_Start_DMA:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1589   .text.HAL_TIM_Base_Start_DMA:0000000000000000 HAL_TIM_Base_Start_DMA
+     /tmp/ccPLZXyC.s:1751   .text.HAL_TIM_Base_Start_DMA:00000000000000c8 $d
+     /tmp/ccPLZXyC.s:3877   .text.TIM_DMAPeriodElapsedCplt:0000000000000000 TIM_DMAPeriodElapsedCplt
+     /tmp/ccPLZXyC.s:3943   .text.TIM_DMAPeriodElapsedHalfCplt:0000000000000000 TIM_DMAPeriodElapsedHalfCplt
+     /tmp/ccPLZXyC.s:4978   .text.TIM_DMAError:0000000000000000 TIM_DMAError
+     /tmp/ccPLZXyC.s:1760   .text.HAL_TIM_Base_Stop_DMA:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1767   .text.HAL_TIM_Base_Stop_DMA:0000000000000000 HAL_TIM_Base_Stop_DMA
+     /tmp/ccPLZXyC.s:1825   .text.HAL_TIM_OC_MspInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1832   .text.HAL_TIM_OC_MspInit:0000000000000000 HAL_TIM_OC_MspInit
+     /tmp/ccPLZXyC.s:1847   .text.HAL_TIM_OC_MspDeInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1854   .text.HAL_TIM_OC_MspDeInit:0000000000000000 HAL_TIM_OC_MspDeInit
+ARM GAS  /tmp/ccPLZXyC.s 			page 495
+
+
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+     /tmp/ccPLZXyC.s:1876   .text.HAL_TIM_OC_DeInit:0000000000000000 HAL_TIM_OC_DeInit
+     /tmp/ccPLZXyC.s:1962   .text.HAL_TIM_PWM_MspInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1969   .text.HAL_TIM_PWM_MspInit:0000000000000000 HAL_TIM_PWM_MspInit
+     /tmp/ccPLZXyC.s:1984   .text.HAL_TIM_PWM_MspDeInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:1991   .text.HAL_TIM_PWM_MspDeInit:0000000000000000 HAL_TIM_PWM_MspDeInit
+     /tmp/ccPLZXyC.s:2006   .text.HAL_TIM_PWM_DeInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2013   .text.HAL_TIM_PWM_DeInit:0000000000000000 HAL_TIM_PWM_DeInit
+     /tmp/ccPLZXyC.s:2099   .text.HAL_TIM_IC_MspInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2106   .text.HAL_TIM_IC_MspInit:0000000000000000 HAL_TIM_IC_MspInit
+     /tmp/ccPLZXyC.s:2121   .text.HAL_TIM_IC_MspDeInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2128   .text.HAL_TIM_IC_MspDeInit:0000000000000000 HAL_TIM_IC_MspDeInit
+     /tmp/ccPLZXyC.s:2143   .text.HAL_TIM_IC_DeInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2150   .text.HAL_TIM_IC_DeInit:0000000000000000 HAL_TIM_IC_DeInit
+     /tmp/ccPLZXyC.s:2236   .text.HAL_TIM_OnePulse_MspInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2243   .text.HAL_TIM_OnePulse_MspInit:0000000000000000 HAL_TIM_OnePulse_MspInit
+     /tmp/ccPLZXyC.s:2258   .text.HAL_TIM_OnePulse_MspDeInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2265   .text.HAL_TIM_OnePulse_MspDeInit:0000000000000000 HAL_TIM_OnePulse_MspDeInit
+     /tmp/ccPLZXyC.s:2280   .text.HAL_TIM_OnePulse_DeInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2287   .text.HAL_TIM_OnePulse_DeInit:0000000000000000 HAL_TIM_OnePulse_DeInit
+     /tmp/ccPLZXyC.s:2357   .text.HAL_TIM_Encoder_MspInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2364   .text.HAL_TIM_Encoder_MspInit:0000000000000000 HAL_TIM_Encoder_MspInit
+     /tmp/ccPLZXyC.s:2379   .text.HAL_TIM_Encoder_MspDeInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2386   .text.HAL_TIM_Encoder_MspDeInit:0000000000000000 HAL_TIM_Encoder_MspDeInit
+     /tmp/ccPLZXyC.s:2401   .text.HAL_TIM_Encoder_DeInit:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2408   .text.HAL_TIM_Encoder_DeInit:0000000000000000 HAL_TIM_Encoder_DeInit
+     /tmp/ccPLZXyC.s:2478   .text.HAL_TIM_DMABurst_MultiWriteStart:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2485   .text.HAL_TIM_DMABurst_MultiWriteStart:0000000000000000 HAL_TIM_DMABurst_MultiWriteStart
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+     /tmp/ccPLZXyC.s:4288   .text.TIM_DMADelayPulseCplt:0000000000000000 TIM_DMADelayPulseCplt
+     /tmp/ccPLZXyC.s:4437   .text.TIM_DMADelayPulseHalfCplt:0000000000000000 TIM_DMADelayPulseHalfCplt
+     /tmp/ccPLZXyC.s:4856   .text.TIM_DMATriggerCplt:0000000000000000 TIM_DMATriggerCplt
+     /tmp/ccPLZXyC.s:4922   .text.TIM_DMATriggerHalfCplt:0000000000000000 TIM_DMATriggerHalfCplt
+     /tmp/ccPLZXyC.s:2856   .text.HAL_TIM_DMABurst_WriteStart:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2863   .text.HAL_TIM_DMABurst_WriteStart:0000000000000000 HAL_TIM_DMABurst_WriteStart
+     /tmp/ccPLZXyC.s:2903   .text.HAL_TIM_DMABurst_WriteStop:0000000000000000 $t
+     /tmp/ccPLZXyC.s:2910   .text.HAL_TIM_DMABurst_WriteStop:0000000000000000 HAL_TIM_DMABurst_WriteStop
+     /tmp/ccPLZXyC.s:3066   .text.HAL_TIM_DMABurst_MultiReadStart:0000000000000000 $t
+     /tmp/ccPLZXyC.s:3073   .text.HAL_TIM_DMABurst_MultiReadStart:0000000000000000 HAL_TIM_DMABurst_MultiReadStart
+     /tmp/ccPLZXyC.s:3431   .text.HAL_TIM_DMABurst_MultiReadStart:000000000000018c $d
+     /tmp/ccPLZXyC.s:4021   .text.TIM_DMACaptureCplt:0000000000000000 TIM_DMACaptureCplt
+     /tmp/ccPLZXyC.s:4178   .text.TIM_DMACaptureHalfCplt:0000000000000000 TIM_DMACaptureHalfCplt
+     /tmp/ccPLZXyC.s:3444   .text.HAL_TIM_DMABurst_ReadStart:0000000000000000 $t
+     /tmp/ccPLZXyC.s:3451   .text.HAL_TIM_DMABurst_ReadStart:0000000000000000 HAL_TIM_DMABurst_ReadStart
+     /tmp/ccPLZXyC.s:3491   .text.HAL_TIM_DMABurst_ReadStop:0000000000000000 $t
+     /tmp/ccPLZXyC.s:3498   .text.HAL_TIM_DMABurst_ReadStop:0000000000000000 HAL_TIM_DMABurst_ReadStop
+     /tmp/ccPLZXyC.s:3654   .text.HAL_TIM_GenerateEvent:0000000000000000 $t
+     /tmp/ccPLZXyC.s:3661   .text.HAL_TIM_GenerateEvent:0000000000000000 HAL_TIM_GenerateEvent
+     /tmp/ccPLZXyC.s:3714   .text.HAL_TIM_ConfigTI1Input:0000000000000000 $t
+     /tmp/ccPLZXyC.s:3721   .text.HAL_TIM_ConfigTI1Input:0000000000000000 HAL_TIM_ConfigTI1Input
+     /tmp/ccPLZXyC.s:3759   .text.HAL_TIM_ReadCapturedValue:0000000000000000 $t
+     /tmp/ccPLZXyC.s:3766   .text.HAL_TIM_ReadCapturedValue:0000000000000000 HAL_TIM_ReadCapturedValue
+     /tmp/ccPLZXyC.s:3780   .text.HAL_TIM_ReadCapturedValue:0000000000000008 $d
+     /tmp/ccPLZXyC.s:3849   .text.HAL_TIM_PeriodElapsedCallback:0000000000000000 $t
+     /tmp/ccPLZXyC.s:3856   .text.HAL_TIM_PeriodElapsedCallback:0000000000000000 HAL_TIM_PeriodElapsedCallback
+     /tmp/ccPLZXyC.s:3871   .text.TIM_DMAPeriodElapsedCplt:0000000000000000 $t
+     /tmp/ccPLZXyC.s:3915   .text.HAL_TIM_PeriodElapsedHalfCpltCallback:0000000000000000 $t
+ARM GAS  /tmp/ccPLZXyC.s 			page 496
+
+
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+     /tmp/ccPLZXyC.s:3937   .text.TIM_DMAPeriodElapsedHalfCplt:0000000000000000 $t
+     /tmp/ccPLZXyC.s:3970   .text.HAL_TIM_OC_DelayElapsedCallback:0000000000000000 $t
+     /tmp/ccPLZXyC.s:3977   .text.HAL_TIM_OC_DelayElapsedCallback:0000000000000000 HAL_TIM_OC_DelayElapsedCallback
+     /tmp/ccPLZXyC.s:3992   .text.HAL_TIM_IC_CaptureCallback:0000000000000000 $t
+     /tmp/ccPLZXyC.s:3999   .text.HAL_TIM_IC_CaptureCallback:0000000000000000 HAL_TIM_IC_CaptureCallback
+     /tmp/ccPLZXyC.s:4014   .text.TIM_DMACaptureCplt:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4149   .text.HAL_TIM_IC_CaptureHalfCpltCallback:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4156   .text.HAL_TIM_IC_CaptureHalfCpltCallback:0000000000000000 HAL_TIM_IC_CaptureHalfCpltCallback
+     /tmp/ccPLZXyC.s:4171   .text.TIM_DMACaptureHalfCplt:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4260   .text.HAL_TIM_PWM_PulseFinishedCallback:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4267   .text.HAL_TIM_PWM_PulseFinishedCallback:0000000000000000 HAL_TIM_PWM_PulseFinishedCallback
+     /tmp/ccPLZXyC.s:4282   .text.TIM_DMADelayPulseCplt:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4408   .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4415   .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback:0000000000000000 HAL_TIM_PWM_PulseFinishedHalfCpltCallback
+     /tmp/ccPLZXyC.s:4430   .text.TIM_DMADelayPulseHalfCplt:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4519   .text.HAL_TIM_TriggerCallback:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4526   .text.HAL_TIM_TriggerCallback:0000000000000000 HAL_TIM_TriggerCallback
+     /tmp/ccPLZXyC.s:4541   .text.HAL_TIM_IRQHandler:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4548   .text.HAL_TIM_IRQHandler:0000000000000000 HAL_TIM_IRQHandler
+     /tmp/ccPLZXyC.s:4850   .text.TIM_DMATriggerCplt:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4894   .text.HAL_TIM_TriggerHalfCpltCallback:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4901   .text.HAL_TIM_TriggerHalfCpltCallback:0000000000000000 HAL_TIM_TriggerHalfCpltCallback
+     /tmp/ccPLZXyC.s:4916   .text.TIM_DMATriggerHalfCplt:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4949   .text.HAL_TIM_ErrorCallback:0000000000000000 $t
+     /tmp/ccPLZXyC.s:4956   .text.HAL_TIM_ErrorCallback:0000000000000000 HAL_TIM_ErrorCallback
+     /tmp/ccPLZXyC.s:4971   .text.TIM_DMAError:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5076   .text.HAL_TIM_Base_GetState:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5083   .text.HAL_TIM_Base_GetState:0000000000000000 HAL_TIM_Base_GetState
+     /tmp/ccPLZXyC.s:5101   .text.HAL_TIM_OC_GetState:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5108   .text.HAL_TIM_OC_GetState:0000000000000000 HAL_TIM_OC_GetState
+     /tmp/ccPLZXyC.s:5126   .text.HAL_TIM_PWM_GetState:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5133   .text.HAL_TIM_PWM_GetState:0000000000000000 HAL_TIM_PWM_GetState
+     /tmp/ccPLZXyC.s:5151   .text.HAL_TIM_IC_GetState:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5158   .text.HAL_TIM_IC_GetState:0000000000000000 HAL_TIM_IC_GetState
+     /tmp/ccPLZXyC.s:5176   .text.HAL_TIM_OnePulse_GetState:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5183   .text.HAL_TIM_OnePulse_GetState:0000000000000000 HAL_TIM_OnePulse_GetState
+     /tmp/ccPLZXyC.s:5201   .text.HAL_TIM_Encoder_GetState:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5208   .text.HAL_TIM_Encoder_GetState:0000000000000000 HAL_TIM_Encoder_GetState
+     /tmp/ccPLZXyC.s:5226   .text.HAL_TIM_GetActiveChannel:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5233   .text.HAL_TIM_GetActiveChannel:0000000000000000 HAL_TIM_GetActiveChannel
+     /tmp/ccPLZXyC.s:5251   .text.HAL_TIM_GetChannelState:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5258   .text.HAL_TIM_GetChannelState:0000000000000000 HAL_TIM_GetChannelState
+     /tmp/ccPLZXyC.s:5336   .text.HAL_TIM_DMABurstState:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5343   .text.HAL_TIM_DMABurstState:0000000000000000 HAL_TIM_DMABurstState
+     /tmp/ccPLZXyC.s:5362   .text.TIM_Base_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5369   .text.TIM_Base_SetConfig:0000000000000000 TIM_Base_SetConfig
+     /tmp/ccPLZXyC.s:5557   .text.TIM_Base_SetConfig:0000000000000104 $d
+     /tmp/ccPLZXyC.s:5568   .text.HAL_TIM_Base_Init:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5575   .text.HAL_TIM_Base_Init:0000000000000000 HAL_TIM_Base_Init
+     /tmp/ccPLZXyC.s:5676   .text.HAL_TIM_OC_Init:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5683   .text.HAL_TIM_OC_Init:0000000000000000 HAL_TIM_OC_Init
+     /tmp/ccPLZXyC.s:5784   .text.HAL_TIM_PWM_Init:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5791   .text.HAL_TIM_PWM_Init:0000000000000000 HAL_TIM_PWM_Init
+     /tmp/ccPLZXyC.s:5892   .text.HAL_TIM_IC_Init:0000000000000000 $t
+     /tmp/ccPLZXyC.s:5899   .text.HAL_TIM_IC_Init:0000000000000000 HAL_TIM_IC_Init
+     /tmp/ccPLZXyC.s:6000   .text.HAL_TIM_OnePulse_Init:0000000000000000 $t
+ARM GAS  /tmp/ccPLZXyC.s 			page 497
+
+
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+     /tmp/ccPLZXyC.s:6114   .text.HAL_TIM_Encoder_Init:0000000000000000 $t
+     /tmp/ccPLZXyC.s:6121   .text.HAL_TIM_Encoder_Init:0000000000000000 HAL_TIM_Encoder_Init
+     /tmp/ccPLZXyC.s:6327   .text.HAL_TIM_Encoder_Init:00000000000000a8 $d
+     /tmp/ccPLZXyC.s:6334   .text.TIM_OC2_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:6341   .text.TIM_OC2_SetConfig:0000000000000000 TIM_OC2_SetConfig
+     /tmp/ccPLZXyC.s:6478   .text.TIM_OC2_SetConfig:0000000000000064 $d
+     /tmp/ccPLZXyC.s:6485   .text.HAL_TIM_OC_ConfigChannel:0000000000000000 $t
+     /tmp/ccPLZXyC.s:6492   .text.HAL_TIM_OC_ConfigChannel:0000000000000000 HAL_TIM_OC_ConfigChannel
+     /tmp/ccPLZXyC.s:6524   .text.HAL_TIM_OC_ConfigChannel:000000000000001a $d
+     /tmp/ccPLZXyC.s:6658   .text.HAL_TIM_PWM_ConfigChannel:0000000000000000 $t
+     /tmp/ccPLZXyC.s:6665   .text.HAL_TIM_PWM_ConfigChannel:0000000000000000 HAL_TIM_PWM_ConfigChannel
+     /tmp/ccPLZXyC.s:6702   .text.HAL_TIM_PWM_ConfigChannel:0000000000000020 $d
+     /tmp/ccPLZXyC.s:6978   .text.TIM_TI1_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:6985   .text.TIM_TI1_SetConfig:0000000000000000 TIM_TI1_SetConfig
+     /tmp/ccPLZXyC.s:7114   .text.TIM_TI1_SetConfig:0000000000000088 $d
+     /tmp/ccPLZXyC.s:7121   .text.HAL_TIM_IC_ConfigChannel:0000000000000000 $t
+     /tmp/ccPLZXyC.s:7128   .text.HAL_TIM_IC_ConfigChannel:0000000000000000 HAL_TIM_IC_ConfigChannel
+     /tmp/ccPLZXyC.s:7344   .text.HAL_TIM_OnePulse_ConfigChannel:0000000000000000 $t
+     /tmp/ccPLZXyC.s:7351   .text.HAL_TIM_OnePulse_ConfigChannel:0000000000000000 HAL_TIM_OnePulse_ConfigChannel
+     /tmp/ccPLZXyC.s:7615   .text.HAL_TIM_OnePulse_ConfigChannel:00000000000000fc $d
+     /tmp/ccPLZXyC.s:7620   .text.TIM_ETR_SetConfig:0000000000000000 $t
+     /tmp/ccPLZXyC.s:7627   .text.TIM_ETR_SetConfig:0000000000000000 TIM_ETR_SetConfig
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+     /tmp/ccPLZXyC.s:7678   .text.HAL_TIM_ConfigOCrefClear:0000000000000000 HAL_TIM_ConfigOCrefClear
+     /tmp/ccPLZXyC.s:7754   .text.HAL_TIM_ConfigOCrefClear:0000000000000048 $d
+     /tmp/ccPLZXyC.s:7963   .text.HAL_TIM_ConfigClockSource:0000000000000000 $t
+     /tmp/ccPLZXyC.s:7970   .text.HAL_TIM_ConfigClockSource:0000000000000000 HAL_TIM_ConfigClockSource
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+     /tmp/ccPLZXyC.s:8269   .text.TIM_SlaveTimer_SetConfig:0000000000000000 TIM_SlaveTimer_SetConfig
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+     /tmp/ccPLZXyC.s:8534   .text.HAL_TIM_SlaveConfigSynchro:0000000000000000 HAL_TIM_SlaveConfigSynchro
+     /tmp/ccPLZXyC.s:8622   .text.HAL_TIM_SlaveConfigSynchro_IT:0000000000000000 $t
+     /tmp/ccPLZXyC.s:8629   .text.HAL_TIM_SlaveConfigSynchro_IT:0000000000000000 HAL_TIM_SlaveConfigSynchro_IT
+     /tmp/ccPLZXyC.s:8717   .text.TIM_CCxChannelCmd:0000000000000000 $t
+     /tmp/ccPLZXyC.s:8724   .text.TIM_CCxChannelCmd:0000000000000000 TIM_CCxChannelCmd
+     /tmp/ccPLZXyC.s:8762   .text.HAL_TIM_OC_Start:0000000000000000 $t
+     /tmp/ccPLZXyC.s:8769   .text.HAL_TIM_OC_Start:0000000000000000 HAL_TIM_OC_Start
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+     /tmp/ccPLZXyC.s:9024   .text.HAL_TIM_OC_Stop:0000000000000000 HAL_TIM_OC_Stop
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+     /tmp/ccPLZXyC.s:9473   .text.HAL_TIM_OC_Stop_IT:0000000000000000 HAL_TIM_OC_Stop_IT
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+     /tmp/ccPLZXyC.s:9681   .text.HAL_TIM_OC_Start_DMA:0000000000000000 HAL_TIM_OC_Start_DMA
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+     /tmp/ccPLZXyC.s:10256  .text.HAL_TIM_OC_Start_DMA:00000000000002cc $d
+ARM GAS  /tmp/ccPLZXyC.s 			page 498
+
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+     /tmp/ccPLZXyC.s:10273  .text.HAL_TIM_OC_Stop_DMA:0000000000000000 HAL_TIM_OC_Stop_DMA
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+     /tmp/ccPLZXyC.s:10506  .text.HAL_TIM_PWM_Start:0000000000000000 HAL_TIM_PWM_Start
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+     /tmp/ccPLZXyC.s:10761  .text.HAL_TIM_PWM_Stop:0000000000000000 HAL_TIM_PWM_Stop
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+     /tmp/ccPLZXyC.s:11418  .text.HAL_TIM_PWM_Start_DMA:0000000000000000 HAL_TIM_PWM_Start_DMA
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+     /tmp/ccPLZXyC.s:12010  .text.HAL_TIM_PWM_Stop_DMA:0000000000000000 HAL_TIM_PWM_Stop_DMA
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+     /tmp/ccPLZXyC.s:12552  .text.HAL_TIM_IC_Stop:0000000000000000 HAL_TIM_IC_Stop
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+     /tmp/ccPLZXyC.s:13373  .text.HAL_TIM_IC_Start_DMA:000000000000007e $t
+     /tmp/ccPLZXyC.s:13791  .text.HAL_TIM_IC_Start_DMA:0000000000000270 $d
+     /tmp/ccPLZXyC.s:13800  .text.HAL_TIM_IC_Stop_DMA:0000000000000000 $t
+     /tmp/ccPLZXyC.s:13807  .text.HAL_TIM_IC_Stop_DMA:0000000000000000 HAL_TIM_IC_Stop_DMA
+     /tmp/ccPLZXyC.s:13840  .text.HAL_TIM_IC_Stop_DMA:0000000000000016 $d
+     /tmp/ccPLZXyC.s:14016  .text.HAL_TIM_OnePulse_Start:0000000000000000 $t
+     /tmp/ccPLZXyC.s:14023  .text.HAL_TIM_OnePulse_Start:0000000000000000 HAL_TIM_OnePulse_Start
+     /tmp/ccPLZXyC.s:14144  .text.HAL_TIM_OnePulse_Start:000000000000007c $d
+     /tmp/ccPLZXyC.s:14150  .text.HAL_TIM_OnePulse_Stop:0000000000000000 $t
+     /tmp/ccPLZXyC.s:14157  .text.HAL_TIM_OnePulse_Stop:0000000000000000 HAL_TIM_OnePulse_Stop
+     /tmp/ccPLZXyC.s:14251  .text.HAL_TIM_OnePulse_Stop:0000000000000078 $d
+     /tmp/ccPLZXyC.s:14257  .text.HAL_TIM_OnePulse_Start_IT:0000000000000000 $t
+     /tmp/ccPLZXyC.s:14264  .text.HAL_TIM_OnePulse_Start_IT:0000000000000000 HAL_TIM_OnePulse_Start_IT
+     /tmp/ccPLZXyC.s:14395  .text.HAL_TIM_OnePulse_Start_IT:0000000000000090 $d
+     /tmp/ccPLZXyC.s:14401  .text.HAL_TIM_OnePulse_Stop_IT:0000000000000000 $t
+ARM GAS  /tmp/ccPLZXyC.s 			page 499
+
+
+     /tmp/ccPLZXyC.s:14408  .text.HAL_TIM_OnePulse_Stop_IT:0000000000000000 HAL_TIM_OnePulse_Stop_IT
+     /tmp/ccPLZXyC.s:14512  .text.HAL_TIM_OnePulse_Stop_IT:000000000000008c $d
+     /tmp/ccPLZXyC.s:14518  .text.HAL_TIM_Encoder_Start:0000000000000000 $t
+     /tmp/ccPLZXyC.s:14525  .text.HAL_TIM_Encoder_Start:0000000000000000 HAL_TIM_Encoder_Start
+     /tmp/ccPLZXyC.s:14726  .text.HAL_TIM_Encoder_Stop:0000000000000000 $t
+     /tmp/ccPLZXyC.s:14733  .text.HAL_TIM_Encoder_Stop:0000000000000000 HAL_TIM_Encoder_Stop
+     /tmp/ccPLZXyC.s:14915  .text.HAL_TIM_Encoder_Start_IT:0000000000000000 $t
+     /tmp/ccPLZXyC.s:14922  .text.HAL_TIM_Encoder_Start_IT:0000000000000000 HAL_TIM_Encoder_Start_IT
+     /tmp/ccPLZXyC.s:15145  .text.HAL_TIM_Encoder_Stop_IT:0000000000000000 $t
+     /tmp/ccPLZXyC.s:15152  .text.HAL_TIM_Encoder_Stop_IT:0000000000000000 HAL_TIM_Encoder_Stop_IT
+     /tmp/ccPLZXyC.s:15355  .text.HAL_TIM_Encoder_Start_DMA:0000000000000000 $t
+     /tmp/ccPLZXyC.s:15362  .text.HAL_TIM_Encoder_Start_DMA:0000000000000000 HAL_TIM_Encoder_Start_DMA
+     /tmp/ccPLZXyC.s:15846  .text.HAL_TIM_Encoder_Start_DMA:0000000000000240 $d
+     /tmp/ccPLZXyC.s:15853  .text.HAL_TIM_Encoder_Stop_DMA:0000000000000000 $t
+     /tmp/ccPLZXyC.s:15860  .text.HAL_TIM_Encoder_Stop_DMA:0000000000000000 HAL_TIM_Encoder_Stop_DMA
+     /tmp/ccPLZXyC.s:3793   .text.HAL_TIM_ReadCapturedValue:0000000000000015 $d
+     /tmp/ccPLZXyC.s:3793   .text.HAL_TIM_ReadCapturedValue:0000000000000016 $t
+     /tmp/ccPLZXyC.s:6545   .text.HAL_TIM_OC_ConfigChannel:000000000000002f $d
+     /tmp/ccPLZXyC.s:6545   .text.HAL_TIM_OC_ConfigChannel:0000000000000030 $t
+     /tmp/ccPLZXyC.s:6723   .text.HAL_TIM_PWM_ConfigChannel:0000000000000035 $d
+     /tmp/ccPLZXyC.s:6723   .text.HAL_TIM_PWM_ConfigChannel:0000000000000036 $t
+     /tmp/ccPLZXyC.s:7776   .text.HAL_TIM_ConfigOCrefClear:000000000000005d $d
+     /tmp/ccPLZXyC.s:7776   .text.HAL_TIM_ConfigOCrefClear:000000000000005e $t
+     /tmp/ccPLZXyC.s:9218   .text.HAL_TIM_OC_Start_IT:000000000000003b $d
+     /tmp/ccPLZXyC.s:9218   .text.HAL_TIM_OC_Start_IT:000000000000003c $t
+     /tmp/ccPLZXyC.s:9511   .text.HAL_TIM_OC_Stop_IT:000000000000001b $d
+     /tmp/ccPLZXyC.s:9511   .text.HAL_TIM_OC_Stop_IT:000000000000001c $t
+     /tmp/ccPLZXyC.s:10311  .text.HAL_TIM_OC_Stop_DMA:000000000000001b $d
+     /tmp/ccPLZXyC.s:10311  .text.HAL_TIM_OC_Stop_DMA:000000000000001c $t
+     /tmp/ccPLZXyC.s:10955  .text.HAL_TIM_PWM_Start_IT:000000000000003b $d
+     /tmp/ccPLZXyC.s:10955  .text.HAL_TIM_PWM_Start_IT:000000000000003c $t
+     /tmp/ccPLZXyC.s:11248  .text.HAL_TIM_PWM_Stop_IT:000000000000001b $d
+     /tmp/ccPLZXyC.s:11248  .text.HAL_TIM_PWM_Stop_IT:000000000000001c $t
+     /tmp/ccPLZXyC.s:12048  .text.HAL_TIM_PWM_Stop_DMA:000000000000001b $d
+     /tmp/ccPLZXyC.s:12048  .text.HAL_TIM_PWM_Stop_DMA:000000000000001c $t
+     /tmp/ccPLZXyC.s:12760  .text.HAL_TIM_IC_Start_IT:000000000000004d $d
+     /tmp/ccPLZXyC.s:12760  .text.HAL_TIM_IC_Start_IT:000000000000004e $t
+     /tmp/ccPLZXyC.s:13098  .text.HAL_TIM_IC_Stop_IT:000000000000001b $d
+     /tmp/ccPLZXyC.s:13098  .text.HAL_TIM_IC_Stop_IT:000000000000001c $t
+     /tmp/ccPLZXyC.s:13853  .text.HAL_TIM_IC_Stop_DMA:0000000000000023 $d
+     /tmp/ccPLZXyC.s:13853  .text.HAL_TIM_IC_Stop_DMA:0000000000000024 $t
+
+UNDEFINED SYMBOLS
+HAL_DMA_Start_IT
+HAL_DMA_Abort_IT
+TIMEx_DMACommutationCplt
+TIMEx_DMACommutationHalfCplt
+HAL_TIMEx_BreakCallback
+HAL_TIMEx_Break2Callback
+HAL_TIMEx_CommutCallback
diff --git a/build/stm32f7xx_hal_tim.o b/build/stm32f7xx_hal_tim.o
new file mode 100644
index 0000000..4ae249e
Binary files /dev/null and b/build/stm32f7xx_hal_tim.o differ
diff --git a/build/stm32f7xx_hal_tim_ex.d b/build/stm32f7xx_hal_tim_ex.d
new file mode 100644
index 0000000..2480e32
--- /dev/null
+++ b/build/stm32f7xx_hal_tim_ex.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_hal_tim_ex.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_hal_tim_ex.lst b/build/stm32f7xx_hal_tim_ex.lst
new file mode 100644
index 0000000..4bc7280
--- /dev/null
+++ b/build/stm32f7xx_hal_tim_ex.lst
@@ -0,0 +1,10645 @@
+ARM GAS  /tmp/cc7KL1Mv.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_hal_tim_ex.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.TIM_CCxNChannelCmd,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	TIM_CCxNChannelCmd:
+  25              	.LVL0:
+  26              	.LFB185:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @file    stm32f7xx_hal_tim_ex.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief   TIM HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This file provides firmware functions to manage the following
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          functionalities of the Timer Extended peripheral:
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *           + Time Hall Sensor Interface Initialization
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *           + Time Hall Sensor Interface Start
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *           + Time Complementary signal break and dead time configuration
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *           + Time Master and Slave synchronization configuration
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *           + Timer remapping capabilities configuration
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ******************************************************************************
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @attention
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * Copyright (c) 2017 STMicroelectronics.
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * All rights reserved.
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * in the root directory of this software component.
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ******************************************************************************
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   @verbatim
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                       ##### TIMER Extended features #####
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   [..]
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     The Timer Extended features include:
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (#) Complementary outputs with programmable dead-time for :
+ARM GAS  /tmp/cc7KL1Mv.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         (++) Output Compare
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         (++) PWM generation (Edge and Center-aligned Mode)
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         (++) One-pulse mode output
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (#) Synchronization circuit to control the timer with external signals and to
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         interconnect several timers together.
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (#) Break input to put the timer output signals in reset state or in a known state.
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         positioning purposes
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****             ##### How to use this driver #####
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     [..]
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****      (#) Initialize the TIM low level resources by implementing the following functions
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****          depending on the selected feature:
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****            (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****      (#) Initialize the TIM low level resources :
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         (##) TIM pins configuration
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****             (+++) Enable the clock for the TIM GPIOs using the following function:
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****               __HAL_RCC_GPIOx_CLK_ENABLE();
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****      (#) The external Clock can be configured, if needed (the default clock is the
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****          internal clock from the APBx), using the following function:
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****          HAL_TIM_ConfigClockSource, the clock configuration should be done before
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****          any start function.
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****      (#) Configure the TIM in the desired functioning mode using one of the
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****          initialization function of this driver:
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****           (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                Timer Hall Sensor Interface and the commutation event with the corresponding
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                Interrupt and DMA request if needed (Note that One Timer is used to interface
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                with the Hall sensor Interface and another Timer should be used to use
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                the commutation event).
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****      (#) Activate the TIM peripheral using one of the start functions:
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                 HAL_TIMEx_OCN_Start_IT()
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                 HAL_TIMEx_PWMN_Start_IT()
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePul
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA()
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                 HAL_TIMEx_HallSensor_Start_IT().
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   @endverbatim
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ******************************************************************************
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Includes ------------------------------------------------------------------*/
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #include "stm32f7xx_hal.h"
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @{
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx TIMEx
+ARM GAS  /tmp/cc7KL1Mv.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief TIM Extended HAL module driver
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @{
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #ifdef HAL_TIM_MODULE_ENABLED
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private typedef -----------------------------------------------------------*/
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private define ------------------------------------------------------------*/
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private macros ------------------------------------------------------------*/
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private variables ---------------------------------------------------------*/
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private function prototypes -----------------------------------------------*/
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Exported functions --------------------------------------------------------*/
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @{
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief    Timer Hall Sensor functions
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                       ##### Timer Hall Sensor functions #####
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   [..]
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     This section provides functions allowing to:
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Initialize and configure TIM HAL Sensor.
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) De-initialize TIM HAL Sensor.
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Start the Hall Sensor Interface.
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Stop the Hall Sensor Interface.
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Start the Hall Sensor Interface and enable interrupts.
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Stop the Hall Sensor Interface and disable interrupts.
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Start the Hall Sensor Interface and enable DMA transfers.
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Stop the Hall Sensor Interface and disable DMA transfers.
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @{
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @note   When the timer instance is initialized in Hall Sensor Interface mode,
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         timer channels 1 and channel 2 are reserved and cannot be used for
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         other purpose.
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  sConfig TIM Hall Sensor configuration structure
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeD
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_OC_InitTypeDef OC_Config;
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the TIM handle allocation */
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (htim == NULL)
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (htim->State == HAL_TIM_STATE_RESET)
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Allocate lock resource and initialize it */
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Lock = HAL_UNLOCKED;
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Reset interrupt callbacks to legacy week callbacks */
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_ResetCallback(htim);
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (htim->HallSensor_MspInitCallback == NULL)
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->HallSensor_MspInitCallback(htim);
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     HAL_TIMEx_HallSensor_MspInit(htim);
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM state */
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Configure the Time base in the Encoder Mode */
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sens
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Reset the IC1PSC Bits */
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the IC1PSC value */
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Hall sensor interface (XOR function of the three inputs) */
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_CR2_TI1S;
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ARM GAS  /tmp/cc7KL1Mv.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCMode = TIM_OCMODE_PWM2;
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.Pulse = sConfig->Commutation_Delay;
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     register to 101 */
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Initialize the DMA burst operation state */
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Initialize the TIM channels state */
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Initialize the TIM state*/
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  DeInitializes the TIM Hall Sensor interface
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_INSTANCE(htim->Instance));
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_BUSY;
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the TIM Peripheral Clock */
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (htim->HallSensor_MspDeInitCallback == NULL)
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* DeInit the low level hardware */
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->HallSensor_MspDeInitCallback(htim);
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ARM GAS  /tmp/cc7KL1Mv.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIMEx_HallSensor_MspDeInit(htim);
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Change the DMA burst operation state */
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Change the TIM channels state */
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Change TIM state */
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_RESET;
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Release Lock */
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Initializes the TIM Hall Sensor MSP.
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval None
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   UNUSED(htim);
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****    */
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  DeInitializes TIM Hall Sensor MSP.
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval None
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   UNUSED(htim);
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****    */
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Starts the TIM Hall Sensor Interface.
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+ARM GAS  /tmp/cc7KL1Mv.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the TIM channels state */
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Input Capture channel 1
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE(htim);
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Stops the TIM Hall sensor Interface.
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ARM GAS  /tmp/cc7KL1Mv.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Input Capture channels 1, 2 and 3
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the TIM channels state */
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the capture compare Interrupts 1 event */
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Input Capture channel 1
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ARM GAS  /tmp/cc7KL1Mv.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE(htim);
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Input Capture channel 1
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the capture compare Interrupts event */
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  pData The destination Buffer address.
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Length The length of data to be transferred from TIM peripheral to memory.
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ARM GAS  /tmp/cc7KL1Mv.s 			page 10
+
+
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM channel state */
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_BUSY;
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****            && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if ((pData == NULL) || (Length == 0U))
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       return HAL_ERROR;
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     else
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Input Capture channel 1
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the DMA Input Capture 1 Callbacks */
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the DMA stream for Capture 1*/
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Return error status */
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the capture compare 1 Interrupt */
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ARM GAS  /tmp/cc7KL1Mv.s 			page 11
+
+
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE(htim);
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor Interface handle
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Input Capture channel 1
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the capture compare Interrupts 1 event */
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM channel state */
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @}
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *  @brief   Timer Complementary Output Compare functions
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****               ##### Timer Complementary Output Compare functions #####
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+ARM GAS  /tmp/cc7KL1Mv.s 			page 12
+
+
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   [..]
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     This section provides functions allowing to:
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Start the Complementary Output Compare/PWM.
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Stop the Complementary Output Compare/PWM.
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Start the Complementary Output Compare/PWM and enable interrupts.
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @{
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Starts the TIM Output Compare signal generation on the complementary
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         output.
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Output Compare handle
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be enabled
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the TIM complementary channel state */
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Capture compare channel N */
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Main Output */
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_MOE_ENABLE(htim);
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 13
+
+
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE(htim);
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Stops the TIM Output Compare signal generation on the complementary
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         output.
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Capture compare channel N */
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Main Output */
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_MOE_DISABLE(htim);
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         on the complementary output.
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM OC handle
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be enabled
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ARM GAS  /tmp/cc7KL1Mv.s 			page 14
+
+
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the TIM complementary channel state */
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   switch (Channel)
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare interrupt */
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare interrupt */
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare interrupt */
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     default:
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       status = HAL_ERROR;
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (status == HAL_OK)
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the TIM Break interrupt */
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the Capture compare channel N */
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the Main Output */
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_MOE_ENABLE(htim);
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         __HAL_TIM_ENABLE(htim);
+ARM GAS  /tmp/cc7KL1Mv.s 			page 15
+
+
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     else
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return status;
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         on the complementary output.
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Output Compare handle
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpccer;
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   switch (Channel)
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare interrupt */
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare interrupt */
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare interrupt */
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     default:
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       status = HAL_ERROR;
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ARM GAS  /tmp/cc7KL1Mv.s 			page 16
+
+
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (status == HAL_OK)
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the Capture compare channel N */
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the TIM Break interrupt (only if no more channel is active) */
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     tmpccer = htim->Instance->CCER;
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the Main Output */
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_MOE_DISABLE(htim);
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the Peripheral */
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_DISABLE(htim);
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Set the TIM complementary channel state */
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return status;
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Starts the TIM Output Compare signal generation in DMA mode
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         on the complementary output.
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Output Compare handle
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be enabled
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  pData The source Buffer address.
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Length The length of data to be transferred from memory to TIM peripheral
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                                           uint16_t Length)
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_BUSY;
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 17
+
+
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if ((pData == NULL) || (Length == 0U))
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       return HAL_ERROR;
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     else
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   switch (Channel)
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the DMA stream */
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         /* Return error status */
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         return HAL_ERROR;
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare DMA request */
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the DMA stream */
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         /* Return error status */
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         return HAL_ERROR;
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare DMA request */
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ARM GAS  /tmp/cc7KL1Mv.s 			page 18
+
+
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the DMA stream */
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         /* Return error status */
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         return HAL_ERROR;
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Output Compare DMA request */
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     default:
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       status = HAL_ERROR;
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (status == HAL_OK)
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the Capture compare channel N */
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the Main Output */
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_MOE_ENABLE(htim);
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         __HAL_TIM_ENABLE(htim);
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     else
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return status;
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Stops the TIM Output Compare signal generation in DMA mode
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         on the complementary output.
+ARM GAS  /tmp/cc7KL1Mv.s 			page 19
+
+
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Output Compare handle
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   switch (Channel)
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare DMA request */
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare DMA request */
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Output Compare DMA request */
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     default:
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       status = HAL_ERROR;
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (status == HAL_OK)
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the Capture compare channel N */
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the Main Output */
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_MOE_DISABLE(htim);
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the Peripheral */
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_DISABLE(htim);
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc7KL1Mv.s 			page 20
+
+
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Set the TIM complementary channel state */
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return status;
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @}
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief    Timer Complementary PWM functions
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                  ##### Timer Complementary PWM functions #####
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   [..]
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     This section provides functions allowing to:
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Start the Complementary PWM.
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Stop the Complementary PWM.
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Start the Complementary PWM and enable interrupts.
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Stop the Complementary PWM and disable interrupts.
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Start the Complementary PWM and enable DMA transfers.
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Stop the Complementary PWM and disable DMA transfers.
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim
+1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @{
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Starts the PWM signal generation on the complementary output.
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be enabled
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the TIM complementary channel state */
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc7KL1Mv.s 			page 21
+
+
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the complementary PWM output  */
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Main Output */
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_MOE_ENABLE(htim);
+1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger 
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE(htim);
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Stops the PWM signal generation on the complementary output.
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the complementary PWM output  */
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Main Output */
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_MOE_DISABLE(htim);
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Starts the PWM signal generation in interrupt mode on the
+ARM GAS  /tmp/cc7KL1Mv.s 			page 22
+
+
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         complementary output.
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the TIM complementary channel state */
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   switch (Channel)
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 1 interrupt */
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 2 interrupt */
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 3 interrupt */
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     default:
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       status = HAL_ERROR;
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (status == HAL_OK)
+1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the TIM Break interrupt */
+ARM GAS  /tmp/cc7KL1Mv.s 			page 23
+
+
+1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the complementary PWM output  */
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the Main Output */
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_MOE_ENABLE(htim);
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         __HAL_TIM_ENABLE(htim);
+1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     else
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return status;
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Stops the PWM signal generation in interrupt mode on the
+1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         complementary output.
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpccer;
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   switch (Channel)
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 1 interrupt */
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 24
+
+
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 2 interrupt */
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 3 interrupt */
+1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     default:
+1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       status = HAL_ERROR;
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (status == HAL_OK)
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the complementary PWM output  */
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the TIM Break interrupt (only if no more channel is active) */
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     tmpccer = htim->Instance->CCER;
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the Main Output */
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_MOE_DISABLE(htim);
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the Peripheral */
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_DISABLE(htim);
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Set the TIM complementary channel state */
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return status;
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Starts the TIM PWM signal generation in DMA mode on the
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         complementary output
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be enabled
+1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  pData The source Buffer address.
+1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Length The length of data to be transferred from memory to TIM peripheral
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_
+ARM GAS  /tmp/cc7KL1Mv.s 			page 25
+
+
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                                            uint16_t Length)
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM complementary channel state */
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_BUSY;
+1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if ((pData == NULL) || (Length == 0U))
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       return HAL_ERROR;
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     else
+1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   switch (Channel)
+1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the DMA stream */
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         /* Return error status */
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         return HAL_ERROR;
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 1 DMA request */
+1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ARM GAS  /tmp/cc7KL1Mv.s 			page 26
+
+
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the DMA stream */
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         /* Return error status */
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         return HAL_ERROR;
+1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 2 DMA request */
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA compare callbacks */
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the DMA error callback */
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the DMA stream */
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         /* Return error status */
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         return HAL_ERROR;
+1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the TIM Capture/Compare 3 DMA request */
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     default:
+1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       status = HAL_ERROR;
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (status == HAL_OK)
+1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the complementary PWM output  */
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the Main Output */
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_MOE_ENABLE(htim);
+1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         __HAL_TIM_ENABLE(htim);
+ARM GAS  /tmp/cc7KL1Mv.s 			page 27
+
+
+1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     else
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_ENABLE(htim);
+1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return status;
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         output
+1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel TIM Channel to be disabled
+1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   switch (Channel)
+1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_1:
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 1 DMA request */
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_2:
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 2 DMA request */
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_CHANNEL_3:
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Disable the TIM Capture/Compare 3 DMA request */
+1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     default:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 28
+
+
+1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       status = HAL_ERROR;
+1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (status == HAL_OK)
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the complementary PWM output */
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the Main Output */
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_MOE_DISABLE(htim);
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Disable the Peripheral */
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     __HAL_TIM_DISABLE(htim);
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Set the TIM complementary channel state */
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return status;
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @}
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief    Timer Complementary One Pulse functions
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *
+1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim
+1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                 ##### Timer Complementary One Pulse functions #####
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   [..]
+1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     This section provides functions allowing to:
+1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Start the Complementary One Pulse generation.
+1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Stop the Complementary One Pulse.
+1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Start the Complementary One Pulse and enable interrupts.
+1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Stop the Complementary One Pulse and disable interrupts.
+1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim
+1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @{
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Starts the TIM One Pulse signal generation on the complementary
+1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         output.
+1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @note OutputChannel must match the pulse output channel chosen when calling
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM One Pulse handle
+1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  OutputChannel pulse output channel to enable
+1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+ARM GAS  /tmp/cc7KL1Mv.s 			page 29
+
+
+1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the TIM channels state */
+1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the complementary One Pulse output channel and the Input Capture channel */
+1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Main Output */
+1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_MOE_ENABLE(htim);
+1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Stops the TIM One Pulse signal generation on the complementary
+1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         output.
+1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @note OutputChannel must match the pulse output channel chosen when calling
+1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM One Pulse handle
+1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  OutputChannel pulse output channel to disable
+1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the complementary One Pulse output channel and the Input Capture channel */
+ARM GAS  /tmp/cc7KL1Mv.s 			page 30
+
+
+1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Main Output */
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_MOE_DISABLE(htim);
+1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM  channels state */
+1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         complementary channel.
+1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @note OutputChannel must match the pulse output channel chosen when calling
+1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM One Pulse handle
+1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  OutputChannel pulse output channel to enable
+1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the TIM channels state */
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     return HAL_ERROR;
+1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM channels state */
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc7KL1Mv.s 			page 31
+
+
+1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the TIM Capture/Compare 1 interrupt */
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the TIM Capture/Compare 2 interrupt */
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the complementary One Pulse output channel and the Input Capture channel */
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Main Output */
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_MOE_ENABLE(htim);
+1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         complementary channel.
+1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @note OutputChannel must match the pulse output channel chosen when calling
+1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *       @ref HAL_TIM_OnePulse_ConfigChannel().
+1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM One Pulse handle
+1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  OutputChannel pulse output channel to disable
+1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the TIM Capture/Compare 1 interrupt */
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the TIM Capture/Compare 2 interrupt */
+1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the complementary One Pulse output channel and the Input Capture channel */
+1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Main Output */
+1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_MOE_DISABLE(htim);
+1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable the Peripheral */
+1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE(htim);
+1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the TIM  channels state */
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ARM GAS  /tmp/cc7KL1Mv.s 			page 32
+
+
+1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Return function status */
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @}
+1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief    Peripheral Control functions
+1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *
+1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim
+1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+1756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                     ##### Peripheral Control functions #####
+1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   [..]
+1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     This section provides functions allowing to:
+1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (+) Configure the commutation event in case of use of the Hall sensor interface.
+1761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (+) Configure Output channels for OC and PWM mode.
+1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (+) Configure Complementary channels, break features and dead time.
+1764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (+) Configure Master synchronization.
+1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (+) Configure timer remapping capabilities.
+1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (+) Enable or disable channel grouping.
+1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim
+1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @{
+1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Configure the TIM commutation event sequence.
+1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @note  This function is mandatory to use the commutation event in order to
+1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        update the configuration at each commutation detection on the TRGI input of the Timer,
+1776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        the typical use of this feature is with the use of another Timer(interface Timer)
+1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        configured in Hall sensor interface, this interface Timer will generate the
+1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        commutation at its TRGO output (connected to Timer used in this function) each time
+1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall 
+1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_NONE: No trigger is needed
+1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  CommutationSource the Commutation Event source
+1789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+1791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG
+1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                                               uint32_t  CommutationSource)
+1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ARM GAS  /tmp/cc7KL1Mv.s 			page 33
+
+
+1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Select the Input trigger */
+1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR &= ~TIM_SMCR_TS;
+1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Capture Compare preload feature */
+1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_CR2_CCPC;
+1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable Commutation Interrupt */
+1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+1819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable Commutation DMA request */
+1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+1822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Configure the TIM commutation event sequence with interrupt.
+1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @note  This function is mandatory to use the commutation event in order to
+1831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        update the configuration at each commutation detection on the TRGI input of the Timer,
+1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        the typical use of this feature is with the use of another Timer(interface Timer)
+1833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        configured in Hall sensor interface, this interface Timer will generate the
+1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        commutation at its TRGO output (connected to Timer used in this function) each time
+1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall 
+1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+1843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_NONE: No trigger is needed
+1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  CommutationSource the Commutation Event source
+1845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG
+1848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                                                  uint32_t  CommutationSource)
+1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+ARM GAS  /tmp/cc7KL1Mv.s 			page 34
+
+
+1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Select the Input trigger */
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR &= ~TIM_SMCR_TS;
+1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+1865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Capture Compare preload feature */
+1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_CR2_CCPC;
+1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable Commutation DMA request */
+1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+1875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Commutation Interrupt */
+1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+1878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Configure the TIM commutation event sequence with DMA.
+1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @note  This function is mandatory to use the commutation event in order to
+1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        update the configuration at each commutation detection on the TRGI input of the Timer,
+1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        the typical use of this feature is with the use of another Timer(interface Timer)
+1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        configured in Hall sensor interface, this interface Timer will generate the
+1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        commutation at its TRGO output (connected to Timer used in this function) each time
+1891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @note  The user should configure the DMA in his own software, in This function only the COMDE b
+1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall 
+1895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+1897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TS_NONE: No trigger is needed
+1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  CommutationSource the Commutation Event source
+1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+1903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+1904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG
+1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                                                   uint32_t  CommutationSource)
+1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+ARM GAS  /tmp/cc7KL1Mv.s 			page 35
+
+
+1913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+1918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Select the Input trigger */
+1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR &= ~TIM_SMCR_TS;
+1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+1922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Capture Compare preload feature */
+1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_CR2_CCPC;
+1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Commutation DMA Request */
+1931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the DMA Commutation Callback */
+1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Disable Commutation Interrupt */
+1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+1939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Enable the Commutation DMA Request */
+1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+1942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+1944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+1947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+1949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Configures the TIM in master mode.
+1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         contains the selected trigger output (TRGO) and the Master/Slave
+1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         mode.
+1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+1957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                                                         const TIM_MasterConfigTypeDef *sMasterConfi
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpcr2;
+1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+1961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check input state */
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc7KL1Mv.s 			page 36
+
+
+1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Change the handler state */
+1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_BUSY;
+1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Get the TIMx CR2 register value */
+1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   tmpcr2 = htim->Instance->CR2;
+1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Get the TIMx SMCR register value */
+1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   tmpsmcr = htim->Instance->SMCR;
+1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+1982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Check the parameters */
+1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Clear the MMS2 bits */
+1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     tmpcr2 &= ~TIM_CR2_MMS2;
+1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Select the TRGO2 source*/
+1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+1990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Reset the MMS Bits */
+1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   tmpcr2 &= ~TIM_CR2_MMS;
+1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the TRGO source */
+1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Update TIMx CR2 */
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 = tmpcr2;
+1998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Reset the MSM Bit */
+2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     tmpsmcr &= ~TIM_SMCR_MSM;
+2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Set master mode */
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     tmpsmcr |= sMasterConfig->MasterSlaveMode;
+2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Update TIMx SMCR */
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR = tmpsmcr;
+2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Change the htim state */
+2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+2020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         and the AOE(automatic output enable).
+2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         contains the BDTR Register configuration  information for the TIM peripheral.
+2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @note   Interrupts can be generated when an active level is detected on the
+2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         break input, the break 2 input or the system break input. Break
+2026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+ARM GAS  /tmp/cc7KL1Mv.s 			page 37
+
+
+2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                                                 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTim
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpbdtr = 0U;
+2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+2045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check input state */
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****      the OSSI State, the dead time value and the Automatic Output Enable Bit */
+2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the BDTR bits */
+2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Check the parameters */
+2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+2068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Set the BREAK2 input related BDTR bits */
+2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set TIMx_BDTR */
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->BDTR = tmpbdtr;
+2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(TIM_BREAK_INPUT_SUPPORT)
+2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc7KL1Mv.s 			page 38
+
+
+2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Configures the break input source.
+2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  BreakInput Break input to configure
+2088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_BREAKINPUT_BRK: Timer break input
+2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  sBreakInputConfig Break input source configuration
+2092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+2093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                                              uint32_t BreakInput,
+2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                                              const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig
+2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmporx;
+2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t bkin_enable_mask;
+2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t bkin_polarity_mask;
+2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t bkin_enable_bitpos;
+2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t bkin_polarity_bitpos;
+2104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUT(BreakInput));
+2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(DFSDM1_Channel0)
+2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+2114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else
+2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+2117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */
+2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check input state */
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   switch (sBreakInputConfig->Source)
+2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_BREAKINPUTSOURCE_BKIN:
+2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+2126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_enable_mask = TIM1_AF1_BKINE;
+2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+2128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_polarity_mask = TIM1_AF1_BKINP;
+2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(DFSDM1_Channel0)
+2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_BREAKINPUTSOURCE_DFSDM1:
+2134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_enable_mask = TIM1_AF1_BKDF1BKE;
+2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKDF1BKE_Pos;
+2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_polarity_mask = 0U;
+2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_polarity_bitpos = 0U;
+2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ARM GAS  /tmp/cc7KL1Mv.s 			page 39
+
+
+2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */
+2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     default:
+2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_enable_mask = 0U;
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_polarity_mask = 0U;
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_enable_bitpos = 0U;
+2148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_polarity_bitpos = 0U;
+2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   switch (BreakInput)
+2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_BREAKINPUT_BRK:
+2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Get the TIMx_AF1 register value */
+2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmporx = htim->Instance->AF1;
+2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the break input */
+2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmporx &= ~bkin_enable_mask;
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the break input polarity */
+2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(DFSDM1_Channel0)
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */
+2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         tmporx &= ~bkin_polarity_mask;
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set TIMx_AF1 */
+2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->Instance->AF1 = tmporx;
+2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+2176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+2177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     case TIM_BREAKINPUT_BRK2:
+2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Get the TIMx_AF2 register value */
+2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmporx = htim->Instance->AF2;
+2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Enable the break input */
+2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmporx &= ~bkin_enable_mask;
+2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set the break input polarity */
+2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(DFSDM1_Channel0)
+2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */
+2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         tmporx &= ~bkin_polarity_mask;
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       /* Set TIMx_AF2 */
+2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->Instance->AF2 = tmporx;
+2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ARM GAS  /tmp/cc7KL1Mv.s 			page 40
+
+
+2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+2199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     default:
+2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       status = HAL_ERROR;
+2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return status;
+2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /*TIM_BREAK_INPUT_SUPPORT */
+2209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Configures the TIMx Remapping input capabilities.
+2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Remap specifies the TIM remapping source.
+2214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default
+2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_ETH_PTP:   TIM2 ITR1 input is connected to ETH PTP trigger output.
+2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
+2218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
+2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_GPIO:      TIM5 CH4 input is connected to dedicated Timer pin(default)
+2220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_LSI:       TIM5 CH4 input is connected to LSI clock.
+2221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_LSE:       TIM5 CH4 input is connected to LSE clock.
+2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM5_RTC:       TIM5 CH4 input is connected to RTC Output event.
+2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default
+2224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM11_SPDIF:    SPDIF Frame synchronous
+2225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock
+2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *                                     (HSE divided by a programmable prescaler)
+2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_TIM11_MCO1:     TIM11 CH1 input is connected to MCO1
+2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *
+2229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+2232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check parameters */
+2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+2235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_REMAP(Remap));
+2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the Timer remapping configuration */
+2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->OR = Remap;
+2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+2243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Group channel 5 and channel 1, 2 or 3
+2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle.
+2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
+2253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         This parameter can be any combination of the following values:
+2254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+ARM GAS  /tmp/cc7KL1Mv.s 			page 41
+
+
+2255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+2257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+2258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL status
+2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check parameters */
+2263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+2264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_GROUPCH5(Channels));
+2265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Process Locked */
+2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_LOCK(htim);
+2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_BUSY;
+2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Clear GC5Cx bit fields */
+2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set GC5Cx bit fields */
+2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CCR5 |= Channels;
+2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Change the htim state */
+2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   __HAL_UNLOCK(htim);
+2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return HAL_OK;
+2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @}
+2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief    Extended Callbacks functions
+2291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *
+2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim
+2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                     ##### Extended Callbacks functions #####
+2295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+2296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   [..]
+2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     This section provides Extended TIM callback functions:
+2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Timer Commutation callback
+2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     (+) Timer Break callback
+2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim
+2302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @{
+2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Commutation callback in non-blocking mode
+2307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval None
+2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 42
+
+
+2312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   UNUSED(htim);
+2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****             the HAL_TIMEx_CommutCallback could be implemented in the user file
+2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****    */
+2318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Commutation half complete callback in non-blocking mode
+2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval None
+2323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   UNUSED(htim);
+2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****             the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+2331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****    */
+2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Break detection callback in non-blocking mode
+2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+2337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval None
+2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   UNUSED(htim);
+2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
+2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****             the HAL_TIMEx_BreakCallback could be implemented in the user file
+2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****    */
+2347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Break2 detection callback in non blocking mode
+2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim: TIM handle
+2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval None
+2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   UNUSED(htim);
+2358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
+2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****             the HAL_TIMEx_Break2Callback could be implemented in the user file
+2361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****    */
+2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @}
+2365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+2368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief    Extended Peripheral State functions
+ARM GAS  /tmp/cc7KL1Mv.s 			page 43
+
+
+2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *
+2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim
+2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                 ##### Extended Peripheral State functions #####
+2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   ==============================================================================
+2374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   [..]
+2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     This subsection permits to get in run-time the status of the peripheral
+2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     and the data flow.
+2377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim
+2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @{
+2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Return the TIM Hall Sensor interface handle state.
+2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM Hall Sensor handle
+2385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval HAL state
+2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
+2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return htim->State;
+2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Return actual state of the TIM complementary channel.
+2394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  htim TIM handle
+2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  ChannelN TIM Complementary channel
+2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1
+2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2
+2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3
+2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval TIM Complementary channel state
+2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t Cha
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_state;
+2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+2408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+2410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return channel_state;
+2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @}
+2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @}
+2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private functions ---------------------------------------------------------*/
+2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @{
+2424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc7KL1Mv.s 			page 44
+
+
+2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  TIM DMA Commutation callback.
+2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  hdma pointer to DMA handle.
+2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval None
+2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Change the htim state */
+2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->CommutationCallback(htim);
+2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else
+2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIMEx_CommutCallback(htim);
+2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  TIM DMA Commutation half complete callback.
+2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  hdma pointer to DMA handle.
+2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval None
+2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+2453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Change the htim state */
+2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->State = HAL_TIM_STATE_READY;
+2456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->CommutationHalfCpltCallback(htim);
+2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else
+2460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIMEx_CommutHalfCpltCallback(htim);
+2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  TIM DMA Delay Pulse complete callback (complementary channel).
+2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  hdma pointer to DMA handle.
+2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval None
+2469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+2477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+2479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ARM GAS  /tmp/cc7KL1Mv.s 			page 45
+
+
+2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+2484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+2488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+2493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+2495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (hdma->Init.Mode == DMA_NORMAL)
+2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+2500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else
+2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* nothing to do */
+2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->PWM_PulseFinishedCallback(htim);
+2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else
+2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_PWM_PulseFinishedCallback(htim);
+2510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+2513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  TIM DMA error callback (complementary channel)
+2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  hdma pointer to DMA handle.
+2518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval None
+2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+2528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+2530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+2537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+2538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   else
+ARM GAS  /tmp/cc7KL1Mv.s 			page 46
+
+
+2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* nothing to do */
+2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->ErrorCallback(htim);
+2546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else
+2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ErrorCallback(htim);
+2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+2554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @brief  Enables or disables the TIM Capture Compare Channel xN.
+2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  TIMx to select the TIM peripheral
+2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  Channel specifies the TIM Channel
+2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be one of the following values:
+2558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_1: TIM Channel 1
+2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_2: TIM Channel 2
+2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *            @arg TIM_CHANNEL_3: TIM Channel 3
+2561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+2562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   * @retval None
+2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   */
+2565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+2566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** {
+  28              		.loc 1 2566 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmp;
+  33              		.loc 1 2567 3 view .LVU1
+2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
+  34              		.loc 1 2569 3 view .LVU2
+  35              		.loc 1 2569 36 is_stmt 0 view .LVU3
+  36 0000 01F00F01 		and	r1, r1, #15
+  37              	.LVL1:
+  38              		.loc 1 2569 7 view .LVU4
+  39 0004 0423     		movs	r3, #4
+  40 0006 03FA01FC 		lsl	ip, r3, r1
+  41              	.LVL2:
+2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Reset the CCxNE Bit */
+2572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIMx->CCER &=  ~tmp;
+  42              		.loc 1 2572 3 is_stmt 1 view .LVU5
+  43              		.loc 1 2572 14 is_stmt 0 view .LVU6
+  44 000a 036A     		ldr	r3, [r0, #32]
+  45 000c 23EA0C03 		bic	r3, r3, ip
+  46 0010 0362     		str	r3, [r0, #32]
+2573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set or reset the CCxNE Bit */
+2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
+  47              		.loc 1 2575 3 is_stmt 1 view .LVU7
+  48              		.loc 1 2575 14 is_stmt 0 view .LVU8
+ARM GAS  /tmp/cc7KL1Mv.s 			page 47
+
+
+  49 0012 036A     		ldr	r3, [r0, #32]
+  50              		.loc 1 2575 42 view .LVU9
+  51 0014 02FA01F1 		lsl	r1, r2, r1
+  52              		.loc 1 2575 14 view .LVU10
+  53 0018 0B43     		orrs	r3, r3, r1
+  54 001a 0362     		str	r3, [r0, #32]
+2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+  55              		.loc 1 2576 1 view .LVU11
+  56 001c 7047     		bx	lr
+  57              		.cfi_endproc
+  58              	.LFE185:
+  60              		.section	.text.TIM_DMAErrorCCxN,"ax",%progbits
+  61              		.align	1
+  62              		.syntax unified
+  63              		.thumb
+  64              		.thumb_func
+  65              		.fpu fpv5-d16
+  67              	TIM_DMAErrorCCxN:
+  68              	.LVL3:
+  69              	.LFB184:
+2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  70              		.loc 1 2521 1 is_stmt 1 view -0
+  71              		.cfi_startproc
+  72              		@ args = 0, pretend = 0, frame = 0
+  73              		@ frame_needed = 0, uses_anonymous_args = 0
+2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  74              		.loc 1 2521 1 is_stmt 0 view .LVU13
+  75 0000 10B5     		push	{r4, lr}
+  76              	.LCFI0:
+  77              		.cfi_def_cfa_offset 8
+  78              		.cfi_offset 4, -8
+  79              		.cfi_offset 14, -4
+2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  80              		.loc 1 2522 3 is_stmt 1 view .LVU14
+2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+  81              		.loc 1 2522 22 is_stmt 0 view .LVU15
+  82 0002 846B     		ldr	r4, [r0, #56]
+  83              	.LVL4:
+2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+  84              		.loc 1 2524 3 is_stmt 1 view .LVU16
+2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+  85              		.loc 1 2524 25 is_stmt 0 view .LVU17
+  86 0004 636A     		ldr	r3, [r4, #36]
+2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+  87              		.loc 1 2524 6 view .LVU18
+  88 0006 8342     		cmp	r3, r0
+  89 0008 0BD0     		beq	.L7
+2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+  90              		.loc 1 2529 8 is_stmt 1 view .LVU19
+2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+  91              		.loc 1 2529 30 is_stmt 0 view .LVU20
+  92 000a A36A     		ldr	r3, [r4, #40]
+2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+  93              		.loc 1 2529 11 view .LVU21
+  94 000c 8342     		cmp	r3, r0
+  95 000e 0DD0     		beq	.L8
+2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 48
+
+
+  96              		.loc 1 2534 8 is_stmt 1 view .LVU22
+2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+  97              		.loc 1 2534 30 is_stmt 0 view .LVU23
+  98 0010 E36A     		ldr	r3, [r4, #44]
+2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+  99              		.loc 1 2534 11 view .LVU24
+ 100 0012 8342     		cmp	r3, r0
+ 101 0014 10D0     		beq	.L9
+ 102              	.L4:
+2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 103              		.loc 1 2542 3 is_stmt 1 view .LVU25
+2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 104              		.loc 1 2547 3 view .LVU26
+ 105 0016 2046     		mov	r0, r4
+ 106              	.LVL5:
+2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 107              		.loc 1 2547 3 is_stmt 0 view .LVU27
+ 108 0018 FFF7FEFF 		bl	HAL_TIM_ErrorCallback
+ 109              	.LVL6:
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 110              		.loc 1 2550 3 is_stmt 1 view .LVU28
+2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 111              		.loc 1 2550 17 is_stmt 0 view .LVU29
+ 112 001c 0023     		movs	r3, #0
+ 113 001e 2377     		strb	r3, [r4, #28]
+2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 114              		.loc 1 2551 1 view .LVU30
+ 115 0020 10BD     		pop	{r4, pc}
+ 116              	.LVL7:
+ 117              	.L7:
+2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 118              		.loc 1 2526 5 is_stmt 1 view .LVU31
+2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 119              		.loc 1 2526 19 is_stmt 0 view .LVU32
+ 120 0022 0123     		movs	r3, #1
+ 121 0024 2377     		strb	r3, [r4, #28]
+2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 122              		.loc 1 2527 5 is_stmt 1 view .LVU33
+ 123 0026 84F84430 		strb	r3, [r4, #68]
+ 124 002a F4E7     		b	.L4
+ 125              	.L8:
+2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 126              		.loc 1 2531 5 view .LVU34
+2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 127              		.loc 1 2531 19 is_stmt 0 view .LVU35
+ 128 002c 0223     		movs	r3, #2
+ 129 002e 2377     		strb	r3, [r4, #28]
+2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 130              		.loc 1 2532 5 is_stmt 1 view .LVU36
+ 131 0030 0123     		movs	r3, #1
+ 132 0032 84F84530 		strb	r3, [r4, #69]
+ 133 0036 EEE7     		b	.L4
+ 134              	.L9:
+2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ 135              		.loc 1 2536 5 view .LVU37
+2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ 136              		.loc 1 2536 19 is_stmt 0 view .LVU38
+ARM GAS  /tmp/cc7KL1Mv.s 			page 49
+
+
+ 137 0038 0423     		movs	r3, #4
+ 138 003a 2377     		strb	r3, [r4, #28]
+2537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 139              		.loc 1 2537 5 is_stmt 1 view .LVU39
+ 140 003c 0123     		movs	r3, #1
+ 141 003e 84F84630 		strb	r3, [r4, #70]
+ 142 0042 E8E7     		b	.L4
+ 143              		.cfi_endproc
+ 144              	.LFE184:
+ 146              		.section	.text.TIM_DMADelayPulseNCplt,"ax",%progbits
+ 147              		.align	1
+ 148              		.syntax unified
+ 149              		.thumb
+ 150              		.thumb_func
+ 151              		.fpu fpv5-d16
+ 153              	TIM_DMADelayPulseNCplt:
+ 154              	.LVL8:
+ 155              	.LFB183:
+2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 156              		.loc 1 2471 1 view -0
+ 157              		.cfi_startproc
+ 158              		@ args = 0, pretend = 0, frame = 0
+ 159              		@ frame_needed = 0, uses_anonymous_args = 0
+2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 160              		.loc 1 2471 1 is_stmt 0 view .LVU41
+ 161 0000 10B5     		push	{r4, lr}
+ 162              	.LCFI1:
+ 163              		.cfi_def_cfa_offset 8
+ 164              		.cfi_offset 4, -8
+ 165              		.cfi_offset 14, -4
+2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 166              		.loc 1 2472 3 is_stmt 1 view .LVU42
+2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 167              		.loc 1 2472 22 is_stmt 0 view .LVU43
+ 168 0002 846B     		ldr	r4, [r0, #56]
+ 169              	.LVL9:
+2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 170              		.loc 1 2474 3 is_stmt 1 view .LVU44
+2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 171              		.loc 1 2474 25 is_stmt 0 view .LVU45
+ 172 0004 636A     		ldr	r3, [r4, #36]
+2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 173              		.loc 1 2474 6 view .LVU46
+ 174 0006 8342     		cmp	r3, r0
+ 175 0008 0BD0     		beq	.L15
+2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 176              		.loc 1 2483 8 is_stmt 1 view .LVU47
+2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 177              		.loc 1 2483 30 is_stmt 0 view .LVU48
+ 178 000a A36A     		ldr	r3, [r4, #40]
+2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 179              		.loc 1 2483 11 view .LVU49
+ 180 000c 8342     		cmp	r3, r0
+ 181 000e 11D0     		beq	.L16
+2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 182              		.loc 1 2492 8 is_stmt 1 view .LVU50
+2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 50
+
+
+ 183              		.loc 1 2492 30 is_stmt 0 view .LVU51
+ 184 0010 E36A     		ldr	r3, [r4, #44]
+2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 185              		.loc 1 2492 11 view .LVU52
+ 186 0012 8342     		cmp	r3, r0
+ 187 0014 17D0     		beq	.L17
+ 188              	.L12:
+2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 189              		.loc 1 2504 3 is_stmt 1 view .LVU53
+2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 190              		.loc 1 2509 3 view .LVU54
+ 191 0016 2046     		mov	r0, r4
+ 192              	.LVL10:
+2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 193              		.loc 1 2509 3 is_stmt 0 view .LVU55
+ 194 0018 FFF7FEFF 		bl	HAL_TIM_PWM_PulseFinishedCallback
+ 195              	.LVL11:
+2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 196              		.loc 1 2512 3 is_stmt 1 view .LVU56
+2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 197              		.loc 1 2512 17 is_stmt 0 view .LVU57
+ 198 001c 0023     		movs	r3, #0
+ 199 001e 2377     		strb	r3, [r4, #28]
+2513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 200              		.loc 1 2513 1 view .LVU58
+ 201 0020 10BD     		pop	{r4, pc}
+ 202              	.LVL12:
+ 203              	.L15:
+2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 204              		.loc 1 2476 5 is_stmt 1 view .LVU59
+2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 205              		.loc 1 2476 19 is_stmt 0 view .LVU60
+ 206 0022 0123     		movs	r3, #1
+ 207 0024 2377     		strb	r3, [r4, #28]
+2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 208              		.loc 1 2478 5 is_stmt 1 view .LVU61
+2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 209              		.loc 1 2478 19 is_stmt 0 view .LVU62
+ 210 0026 C369     		ldr	r3, [r0, #28]
+2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 211              		.loc 1 2478 8 view .LVU63
+ 212 0028 002B     		cmp	r3, #0
+ 213 002a F4D1     		bne	.L12
+2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 214              		.loc 1 2480 7 is_stmt 1 view .LVU64
+ 215 002c 0123     		movs	r3, #1
+ 216 002e 84F84430 		strb	r3, [r4, #68]
+ 217 0032 F0E7     		b	.L12
+ 218              	.L16:
+2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 219              		.loc 1 2485 5 view .LVU65
+2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 220              		.loc 1 2485 19 is_stmt 0 view .LVU66
+ 221 0034 0223     		movs	r3, #2
+ 222 0036 2377     		strb	r3, [r4, #28]
+2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 223              		.loc 1 2487 5 is_stmt 1 view .LVU67
+ARM GAS  /tmp/cc7KL1Mv.s 			page 51
+
+
+2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 224              		.loc 1 2487 19 is_stmt 0 view .LVU68
+ 225 0038 C369     		ldr	r3, [r0, #28]
+2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 226              		.loc 1 2487 8 view .LVU69
+ 227 003a 002B     		cmp	r3, #0
+ 228 003c EBD1     		bne	.L12
+2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 229              		.loc 1 2489 7 is_stmt 1 view .LVU70
+ 230 003e 0123     		movs	r3, #1
+ 231 0040 84F84530 		strb	r3, [r4, #69]
+ 232 0044 E7E7     		b	.L12
+ 233              	.L17:
+2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 234              		.loc 1 2494 5 view .LVU71
+2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 235              		.loc 1 2494 19 is_stmt 0 view .LVU72
+ 236 0046 0423     		movs	r3, #4
+ 237 0048 2377     		strb	r3, [r4, #28]
+2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 238              		.loc 1 2496 5 is_stmt 1 view .LVU73
+2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 239              		.loc 1 2496 19 is_stmt 0 view .LVU74
+ 240 004a C369     		ldr	r3, [r0, #28]
+2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 241              		.loc 1 2496 8 view .LVU75
+ 242 004c 002B     		cmp	r3, #0
+ 243 004e E2D1     		bne	.L12
+2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 244              		.loc 1 2498 7 is_stmt 1 view .LVU76
+ 245 0050 0123     		movs	r3, #1
+ 246 0052 84F84630 		strb	r3, [r4, #70]
+ 247 0056 DEE7     		b	.L12
+ 248              		.cfi_endproc
+ 249              	.LFE183:
+ 251              		.section	.text.HAL_TIMEx_HallSensor_MspInit,"ax",%progbits
+ 252              		.align	1
+ 253              		.weak	HAL_TIMEx_HallSensor_MspInit
+ 254              		.syntax unified
+ 255              		.thumb
+ 256              		.thumb_func
+ 257              		.fpu fpv5-d16
+ 259              	HAL_TIMEx_HallSensor_MspInit:
+ 260              	.LVL13:
+ 261              	.LFB143:
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 262              		.loc 1 287 1 view -0
+ 263              		.cfi_startproc
+ 264              		@ args = 0, pretend = 0, frame = 0
+ 265              		@ frame_needed = 0, uses_anonymous_args = 0
+ 266              		@ link register save eliminated.
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 267              		.loc 1 289 3 view .LVU78
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 268              		.loc 1 294 1 is_stmt 0 view .LVU79
+ 269 0000 7047     		bx	lr
+ 270              		.cfi_endproc
+ARM GAS  /tmp/cc7KL1Mv.s 			page 52
+
+
+ 271              	.LFE143:
+ 273              		.section	.text.HAL_TIMEx_HallSensor_Init,"ax",%progbits
+ 274              		.align	1
+ 275              		.global	HAL_TIMEx_HallSensor_Init
+ 276              		.syntax unified
+ 277              		.thumb
+ 278              		.thumb_func
+ 279              		.fpu fpv5-d16
+ 281              	HAL_TIMEx_HallSensor_Init:
+ 282              	.LVL14:
+ 283              	.LFB141:
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_OC_InitTypeDef OC_Config;
+ 284              		.loc 1 140 1 is_stmt 1 view -0
+ 285              		.cfi_startproc
+ 286              		@ args = 0, pretend = 0, frame = 32
+ 287              		@ frame_needed = 0, uses_anonymous_args = 0
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 288              		.loc 1 141 3 view .LVU81
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 289              		.loc 1 144 3 view .LVU82
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 290              		.loc 1 144 6 is_stmt 0 view .LVU83
+ 291 0000 0028     		cmp	r0, #0
+ 292 0002 65D0     		beq	.L22
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_OC_InitTypeDef OC_Config;
+ 293              		.loc 1 140 1 view .LVU84
+ 294 0004 70B5     		push	{r4, r5, r6, lr}
+ 295              	.LCFI2:
+ 296              		.cfi_def_cfa_offset 16
+ 297              		.cfi_offset 4, -16
+ 298              		.cfi_offset 5, -12
+ 299              		.cfi_offset 6, -8
+ 300              		.cfi_offset 14, -4
+ 301 0006 88B0     		sub	sp, sp, #32
+ 302              	.LCFI3:
+ 303              		.cfi_def_cfa_offset 48
+ 304 0008 0E46     		mov	r6, r1
+ 305 000a 0446     		mov	r4, r0
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ 306              		.loc 1 150 3 is_stmt 1 view .LVU85
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 307              		.loc 1 151 3 view .LVU86
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ 308              		.loc 1 152 3 view .LVU87
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ 309              		.loc 1 153 3 view .LVU88
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+ 310              		.loc 1 154 3 view .LVU89
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ 311              		.loc 1 155 3 view .LVU90
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ 312              		.loc 1 156 3 view .LVU91
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 313              		.loc 1 157 3 view .LVU92
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 314              		.loc 1 159 3 view .LVU93
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 53
+
+
+ 315              		.loc 1 159 11 is_stmt 0 view .LVU94
+ 316 000c 90F83D30 		ldrb	r3, [r0, #61]	@ zero_extendqisi2
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 317              		.loc 1 159 6 view .LVU95
+ 318 0010 002B     		cmp	r3, #0
+ 319 0012 58D0     		beq	.L27
+ 320              	.LVL15:
+ 321              	.L21:
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 322              		.loc 1 181 3 is_stmt 1 view .LVU96
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 323              		.loc 1 181 15 is_stmt 0 view .LVU97
+ 324 0014 0223     		movs	r3, #2
+ 325 0016 84F83D30 		strb	r3, [r4, #61]
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 326              		.loc 1 184 3 is_stmt 1 view .LVU98
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 327              		.loc 1 184 38 is_stmt 0 view .LVU99
+ 328 001a 2146     		mov	r1, r4
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 329              		.loc 1 184 3 view .LVU100
+ 330 001c 51F8040B 		ldr	r0, [r1], #4
+ 331 0020 FFF7FEFF 		bl	TIM_Base_SetConfig
+ 332              	.LVL16:
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 333              		.loc 1 187 3 is_stmt 1 view .LVU101
+ 334 0024 B368     		ldr	r3, [r6, #8]
+ 335 0026 0322     		movs	r2, #3
+ 336 0028 3168     		ldr	r1, [r6]
+ 337 002a 2068     		ldr	r0, [r4]
+ 338 002c FFF7FEFF 		bl	TIM_TI1_SetConfig
+ 339              	.LVL17:
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the IC1PSC value */
+ 340              		.loc 1 190 3 view .LVU102
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the IC1PSC value */
+ 341              		.loc 1 190 7 is_stmt 0 view .LVU103
+ 342 0030 2268     		ldr	r2, [r4]
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the IC1PSC value */
+ 343              		.loc 1 190 25 view .LVU104
+ 344 0032 9369     		ldr	r3, [r2, #24]
+ 345 0034 23F00C03 		bic	r3, r3, #12
+ 346 0038 9361     		str	r3, [r2, #24]
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 347              		.loc 1 192 3 is_stmt 1 view .LVU105
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 348              		.loc 1 192 7 is_stmt 0 view .LVU106
+ 349 003a 2268     		ldr	r2, [r4]
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 350              		.loc 1 192 25 view .LVU107
+ 351 003c 9369     		ldr	r3, [r2, #24]
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 352              		.loc 1 192 35 view .LVU108
+ 353 003e 7168     		ldr	r1, [r6, #4]
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 354              		.loc 1 192 25 view .LVU109
+ 355 0040 0B43     		orrs	r3, r3, r1
+ 356 0042 9361     		str	r3, [r2, #24]
+ARM GAS  /tmp/cc7KL1Mv.s 			page 54
+
+
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 357              		.loc 1 195 3 is_stmt 1 view .LVU110
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 358              		.loc 1 195 7 is_stmt 0 view .LVU111
+ 359 0044 2268     		ldr	r2, [r4]
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 360              		.loc 1 195 23 view .LVU112
+ 361 0046 5368     		ldr	r3, [r2, #4]
+ 362 0048 43F08003 		orr	r3, r3, #128
+ 363 004c 5360     		str	r3, [r2, #4]
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+ 364              		.loc 1 198 3 is_stmt 1 view .LVU113
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+ 365              		.loc 1 198 7 is_stmt 0 view .LVU114
+ 366 004e 2268     		ldr	r2, [r4]
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+ 367              		.loc 1 198 24 view .LVU115
+ 368 0050 9368     		ldr	r3, [r2, #8]
+ 369 0052 23F07003 		bic	r3, r3, #112
+ 370 0056 9360     		str	r3, [r2, #8]
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 371              		.loc 1 199 3 is_stmt 1 view .LVU116
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 372              		.loc 1 199 7 is_stmt 0 view .LVU117
+ 373 0058 2268     		ldr	r2, [r4]
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 374              		.loc 1 199 24 view .LVU118
+ 375 005a 9368     		ldr	r3, [r2, #8]
+ 376 005c 43F04003 		orr	r3, r3, #64
+ 377 0060 9360     		str	r3, [r2, #8]
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+ 378              		.loc 1 202 3 is_stmt 1 view .LVU119
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+ 379              		.loc 1 202 7 is_stmt 0 view .LVU120
+ 380 0062 2268     		ldr	r2, [r4]
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+ 381              		.loc 1 202 24 view .LVU121
+ 382 0064 9168     		ldr	r1, [r2, #8]
+ 383 0066 1B4B     		ldr	r3, .L28
+ 384 0068 0B40     		ands	r3, r3, r1
+ 385 006a 9360     		str	r3, [r2, #8]
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 386              		.loc 1 203 3 is_stmt 1 view .LVU122
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 387              		.loc 1 203 7 is_stmt 0 view .LVU123
+ 388 006c 2268     		ldr	r2, [r4]
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 389              		.loc 1 203 24 view .LVU124
+ 390 006e 9368     		ldr	r3, [r2, #8]
+ 391 0070 43F00403 		orr	r3, r3, #4
+ 392 0074 9360     		str	r3, [r2, #8]
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ 393              		.loc 1 206 3 is_stmt 1 view .LVU125
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ 394              		.loc 1 206 24 is_stmt 0 view .LVU126
+ 395 0076 0025     		movs	r5, #0
+ 396 0078 0595     		str	r5, [sp, #20]
+ARM GAS  /tmp/cc7KL1Mv.s 			page 55
+
+
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCMode = TIM_OCMODE_PWM2;
+ 397              		.loc 1 207 3 is_stmt 1 view .LVU127
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCMode = TIM_OCMODE_PWM2;
+ 398              		.loc 1 207 25 is_stmt 0 view .LVU128
+ 399 007a 0695     		str	r5, [sp, #24]
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ 400              		.loc 1 208 3 is_stmt 1 view .LVU129
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ 401              		.loc 1 208 20 is_stmt 0 view .LVU130
+ 402 007c 7023     		movs	r3, #112
+ 403 007e 0193     		str	r3, [sp, #4]
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ 404              		.loc 1 209 3 is_stmt 1 view .LVU131
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ 405              		.loc 1 209 26 is_stmt 0 view .LVU132
+ 406 0080 0795     		str	r5, [sp, #28]
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 407              		.loc 1 210 3 is_stmt 1 view .LVU133
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 408              		.loc 1 210 25 is_stmt 0 view .LVU134
+ 409 0082 0495     		str	r5, [sp, #16]
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.Pulse = sConfig->Commutation_Delay;
+ 410              		.loc 1 211 3 is_stmt 1 view .LVU135
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   OC_Config.Pulse = sConfig->Commutation_Delay;
+ 411              		.loc 1 211 24 is_stmt 0 view .LVU136
+ 412 0084 0395     		str	r5, [sp, #12]
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 413              		.loc 1 212 3 is_stmt 1 view .LVU137
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 414              		.loc 1 212 28 is_stmt 0 view .LVU138
+ 415 0086 F368     		ldr	r3, [r6, #12]
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 416              		.loc 1 212 19 view .LVU139
+ 417 0088 0293     		str	r3, [sp, #8]
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 418              		.loc 1 214 3 is_stmt 1 view .LVU140
+ 419 008a 01A9     		add	r1, sp, #4
+ 420 008c 2068     		ldr	r0, [r4]
+ 421 008e FFF7FEFF 		bl	TIM_OC2_SetConfig
+ 422              	.LVL18:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ 423              		.loc 1 218 3 view .LVU141
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ 424              		.loc 1 218 7 is_stmt 0 view .LVU142
+ 425 0092 2268     		ldr	r2, [r4]
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ 426              		.loc 1 218 23 view .LVU143
+ 427 0094 5368     		ldr	r3, [r2, #4]
+ 428 0096 23F07003 		bic	r3, r3, #112
+ 429 009a 5360     		str	r3, [r2, #4]
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 430              		.loc 1 219 3 is_stmt 1 view .LVU144
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 431              		.loc 1 219 7 is_stmt 0 view .LVU145
+ 432 009c 2268     		ldr	r2, [r4]
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 433              		.loc 1 219 23 view .LVU146
+ARM GAS  /tmp/cc7KL1Mv.s 			page 56
+
+
+ 434 009e 5368     		ldr	r3, [r2, #4]
+ 435 00a0 43F05003 		orr	r3, r3, #80
+ 436 00a4 5360     		str	r3, [r2, #4]
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 437              		.loc 1 222 3 is_stmt 1 view .LVU147
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 438              		.loc 1 222 23 is_stmt 0 view .LVU148
+ 439 00a6 0123     		movs	r3, #1
+ 440 00a8 84F84830 		strb	r3, [r4, #72]
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 441              		.loc 1 225 3 is_stmt 1 view .LVU149
+ 442 00ac 84F83E30 		strb	r3, [r4, #62]
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 443              		.loc 1 226 3 view .LVU150
+ 444 00b0 84F83F30 		strb	r3, [r4, #63]
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 445              		.loc 1 227 3 view .LVU151
+ 446 00b4 84F84430 		strb	r3, [r4, #68]
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 447              		.loc 1 228 3 view .LVU152
+ 448 00b8 84F84530 		strb	r3, [r4, #69]
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 449              		.loc 1 231 3 view .LVU153
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 450              		.loc 1 231 15 is_stmt 0 view .LVU154
+ 451 00bc 84F83D30 		strb	r3, [r4, #61]
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 452              		.loc 1 233 3 is_stmt 1 view .LVU155
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 453              		.loc 1 233 10 is_stmt 0 view .LVU156
+ 454 00c0 2846     		mov	r0, r5
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 455              		.loc 1 234 1 view .LVU157
+ 456 00c2 08B0     		add	sp, sp, #32
+ 457              	.LCFI4:
+ 458              		.cfi_remember_state
+ 459              		.cfi_def_cfa_offset 16
+ 460              		@ sp needed
+ 461 00c4 70BD     		pop	{r4, r5, r6, pc}
+ 462              	.LVL19:
+ 463              	.L27:
+ 464              	.LCFI5:
+ 465              		.cfi_restore_state
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 466              		.loc 1 162 5 is_stmt 1 view .LVU158
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 467              		.loc 1 162 16 is_stmt 0 view .LVU159
+ 468 00c6 80F83C30 		strb	r3, [r0, #60]
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 469              		.loc 1 176 5 is_stmt 1 view .LVU160
+ 470 00ca FFF7FEFF 		bl	HAL_TIMEx_HallSensor_MspInit
+ 471              	.LVL20:
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 472              		.loc 1 176 5 is_stmt 0 view .LVU161
+ 473 00ce A1E7     		b	.L21
+ 474              	.LVL21:
+ 475              	.L22:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 57
+
+
+ 476              	.LCFI6:
+ 477              		.cfi_def_cfa_offset 0
+ 478              		.cfi_restore 4
+ 479              		.cfi_restore 5
+ 480              		.cfi_restore 6
+ 481              		.cfi_restore 14
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 482              		.loc 1 146 12 view .LVU162
+ 483 00d0 0120     		movs	r0, #1
+ 484              	.LVL22:
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 485              		.loc 1 234 1 view .LVU163
+ 486 00d2 7047     		bx	lr
+ 487              	.L29:
+ 488              		.align	2
+ 489              	.L28:
+ 490 00d4 F8FFFEFF 		.word	-65544
+ 491              		.cfi_endproc
+ 492              	.LFE141:
+ 494              		.section	.text.HAL_TIMEx_HallSensor_MspDeInit,"ax",%progbits
+ 495              		.align	1
+ 496              		.weak	HAL_TIMEx_HallSensor_MspDeInit
+ 497              		.syntax unified
+ 498              		.thumb
+ 499              		.thumb_func
+ 500              		.fpu fpv5-d16
+ 502              	HAL_TIMEx_HallSensor_MspDeInit:
+ 503              	.LVL23:
+ 504              	.LFB144:
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 505              		.loc 1 302 1 is_stmt 1 view -0
+ 506              		.cfi_startproc
+ 507              		@ args = 0, pretend = 0, frame = 0
+ 508              		@ frame_needed = 0, uses_anonymous_args = 0
+ 509              		@ link register save eliminated.
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 510              		.loc 1 304 3 view .LVU165
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 511              		.loc 1 309 1 is_stmt 0 view .LVU166
+ 512 0000 7047     		bx	lr
+ 513              		.cfi_endproc
+ 514              	.LFE144:
+ 516              		.section	.text.HAL_TIMEx_HallSensor_DeInit,"ax",%progbits
+ 517              		.align	1
+ 518              		.global	HAL_TIMEx_HallSensor_DeInit
+ 519              		.syntax unified
+ 520              		.thumb
+ 521              		.thumb_func
+ 522              		.fpu fpv5-d16
+ 524              	HAL_TIMEx_HallSensor_DeInit:
+ 525              	.LVL24:
+ 526              	.LFB142:
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 527              		.loc 1 242 1 is_stmt 1 view -0
+ 528              		.cfi_startproc
+ 529              		@ args = 0, pretend = 0, frame = 0
+ 530              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cc7KL1Mv.s 			page 58
+
+
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 531              		.loc 1 242 1 is_stmt 0 view .LVU168
+ 532 0000 10B5     		push	{r4, lr}
+ 533              	.LCFI7:
+ 534              		.cfi_def_cfa_offset 8
+ 535              		.cfi_offset 4, -8
+ 536              		.cfi_offset 14, -4
+ 537 0002 0446     		mov	r4, r0
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 538              		.loc 1 244 3 is_stmt 1 view .LVU169
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 539              		.loc 1 246 3 view .LVU170
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 540              		.loc 1 246 15 is_stmt 0 view .LVU171
+ 541 0004 0223     		movs	r3, #2
+ 542 0006 80F83D30 		strb	r3, [r0, #61]
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 543              		.loc 1 249 3 is_stmt 1 view .LVU172
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 544              		.loc 1 249 3 view .LVU173
+ 545 000a 0368     		ldr	r3, [r0]
+ 546 000c 196A     		ldr	r1, [r3, #32]
+ 547 000e 41F21112 		movw	r2, #4369
+ 548 0012 1142     		tst	r1, r2
+ 549 0014 08D1     		bne	.L32
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 550              		.loc 1 249 3 discriminator 1 view .LVU174
+ 551 0016 196A     		ldr	r1, [r3, #32]
+ 552 0018 40F24442 		movw	r2, #1092
+ 553 001c 1142     		tst	r1, r2
+ 554 001e 03D1     		bne	.L32
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 555              		.loc 1 249 3 discriminator 3 view .LVU175
+ 556 0020 1A68     		ldr	r2, [r3]
+ 557 0022 22F00102 		bic	r2, r2, #1
+ 558 0026 1A60     		str	r2, [r3]
+ 559              	.L32:
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 560              		.loc 1 249 3 discriminator 5 view .LVU176
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 561              		.loc 1 260 3 discriminator 5 view .LVU177
+ 562 0028 2046     		mov	r0, r4
+ 563              	.LVL25:
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 564              		.loc 1 260 3 is_stmt 0 discriminator 5 view .LVU178
+ 565 002a FFF7FEFF 		bl	HAL_TIMEx_HallSensor_MspDeInit
+ 566              	.LVL26:
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 567              		.loc 1 264 3 is_stmt 1 discriminator 5 view .LVU179
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 568              		.loc 1 264 23 is_stmt 0 discriminator 5 view .LVU180
+ 569 002e 0020     		movs	r0, #0
+ 570 0030 84F84800 		strb	r0, [r4, #72]
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 571              		.loc 1 267 3 is_stmt 1 discriminator 5 view .LVU181
+ 572 0034 84F83E00 		strb	r0, [r4, #62]
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ARM GAS  /tmp/cc7KL1Mv.s 			page 59
+
+
+ 573              		.loc 1 268 3 discriminator 5 view .LVU182
+ 574 0038 84F83F00 		strb	r0, [r4, #63]
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ 575              		.loc 1 269 3 discriminator 5 view .LVU183
+ 576 003c 84F84400 		strb	r0, [r4, #68]
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 577              		.loc 1 270 3 discriminator 5 view .LVU184
+ 578 0040 84F84500 		strb	r0, [r4, #69]
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 579              		.loc 1 273 3 discriminator 5 view .LVU185
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 580              		.loc 1 273 15 is_stmt 0 discriminator 5 view .LVU186
+ 581 0044 84F83D00 		strb	r0, [r4, #61]
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 582              		.loc 1 276 3 is_stmt 1 discriminator 5 view .LVU187
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 583              		.loc 1 276 3 discriminator 5 view .LVU188
+ 584 0048 84F83C00 		strb	r0, [r4, #60]
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 585              		.loc 1 276 3 discriminator 5 view .LVU189
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 586              		.loc 1 278 3 discriminator 5 view .LVU190
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 587              		.loc 1 279 1 is_stmt 0 discriminator 5 view .LVU191
+ 588 004c 10BD     		pop	{r4, pc}
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 589              		.loc 1 279 1 discriminator 5 view .LVU192
+ 590              		.cfi_endproc
+ 591              	.LFE142:
+ 593              		.section	.text.HAL_TIMEx_HallSensor_Start,"ax",%progbits
+ 594              		.align	1
+ 595              		.global	HAL_TIMEx_HallSensor_Start
+ 596              		.syntax unified
+ 597              		.thumb
+ 598              		.thumb_func
+ 599              		.fpu fpv5-d16
+ 601              	HAL_TIMEx_HallSensor_Start:
+ 602              	.LVL27:
+ 603              	.LFB145:
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 604              		.loc 1 317 1 is_stmt 1 view -0
+ 605              		.cfi_startproc
+ 606              		@ args = 0, pretend = 0, frame = 0
+ 607              		@ frame_needed = 0, uses_anonymous_args = 0
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 608              		.loc 1 317 1 is_stmt 0 view .LVU194
+ 609 0000 10B5     		push	{r4, lr}
+ 610              	.LCFI8:
+ 611              		.cfi_def_cfa_offset 8
+ 612              		.cfi_offset 4, -8
+ 613              		.cfi_offset 14, -4
+ 614 0002 0446     		mov	r4, r0
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 615              		.loc 1 318 3 is_stmt 1 view .LVU195
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 616              		.loc 1 319 3 view .LVU196
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ARM GAS  /tmp/cc7KL1Mv.s 			page 60
+
+
+ 617              		.loc 1 319 31 is_stmt 0 view .LVU197
+ 618 0004 90F83E10 		ldrb	r1, [r0, #62]	@ zero_extendqisi2
+ 619 0008 C9B2     		uxtb	r1, r1
+ 620              	.LVL28:
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 621              		.loc 1 320 3 is_stmt 1 view .LVU198
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 622              		.loc 1 320 31 is_stmt 0 view .LVU199
+ 623 000a 90F83F20 		ldrb	r2, [r0, #63]	@ zero_extendqisi2
+ 624 000e D2B2     		uxtb	r2, r2
+ 625              	.LVL29:
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 626              		.loc 1 321 3 is_stmt 1 view .LVU200
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 627              		.loc 1 321 31 is_stmt 0 view .LVU201
+ 628 0010 90F84430 		ldrb	r3, [r0, #68]	@ zero_extendqisi2
+ 629 0014 D8B2     		uxtb	r0, r3
+ 630              	.LVL30:
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 631              		.loc 1 322 3 is_stmt 1 view .LVU202
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 632              		.loc 1 322 31 is_stmt 0 view .LVU203
+ 633 0016 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 634              	.LVL31:
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 635              		.loc 1 325 3 is_stmt 1 view .LVU204
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 636              		.loc 1 328 3 view .LVU205
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 637              		.loc 1 328 6 is_stmt 0 view .LVU206
+ 638 001a 012A     		cmp	r2, #1
+ 639 001c 08BF     		it	eq
+ 640 001e 0129     		cmpeq	r1, #1
+ 641 0020 48D1     		bne	.L38
+ 642 0022 DBB2     		uxtb	r3, r3
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 643              		.loc 1 331 41 view .LVU207
+ 644 0024 013B     		subs	r3, r3, #1
+ 645              	.LVL32:
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 646              		.loc 1 331 41 view .LVU208
+ 647 0026 18BF     		it	ne
+ 648 0028 0123     		movne	r3, #1
+ 649              	.LVL33:
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 650              		.loc 1 331 7 view .LVU209
+ 651 002a 0128     		cmp	r0, #1
+ 652 002c 44D1     		bne	.L39
+ 653 002e 002B     		cmp	r3, #0
+ 654 0030 42D1     		bne	.L39
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 655              		.loc 1 337 3 is_stmt 1 view .LVU210
+ 656 0032 0223     		movs	r3, #2
+ 657 0034 84F83E30 		strb	r3, [r4, #62]
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 658              		.loc 1 338 3 view .LVU211
+ 659 0038 84F83F30 		strb	r3, [r4, #63]
+ARM GAS  /tmp/cc7KL1Mv.s 			page 61
+
+
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 660              		.loc 1 339 3 view .LVU212
+ 661 003c 84F84430 		strb	r3, [r4, #68]
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 662              		.loc 1 340 3 view .LVU213
+ 663 0040 84F84530 		strb	r3, [r4, #69]
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 664              		.loc 1 345 3 view .LVU214
+ 665 0044 0122     		movs	r2, #1
+ 666              	.LVL34:
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 667              		.loc 1 345 3 is_stmt 0 view .LVU215
+ 668 0046 0021     		movs	r1, #0
+ 669              	.LVL35:
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 670              		.loc 1 345 3 view .LVU216
+ 671 0048 2068     		ldr	r0, [r4]
+ 672              	.LVL36:
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 673              		.loc 1 345 3 view .LVU217
+ 674 004a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 675              	.LVL37:
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 676              		.loc 1 348 3 is_stmt 1 view .LVU218
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 677              		.loc 1 348 7 is_stmt 0 view .LVU219
+ 678 004e 2368     		ldr	r3, [r4]
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 679              		.loc 1 348 6 view .LVU220
+ 680 0050 1B4A     		ldr	r2, .L42
+ 681 0052 B3F1804F 		cmp	r3, #1073741824
+ 682 0056 18BF     		it	ne
+ 683 0058 9342     		cmpne	r3, r2
+ 684 005a 1DD0     		beq	.L36
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 685              		.loc 1 348 7 discriminator 1 view .LVU221
+ 686 005c A2F57C42 		sub	r2, r2, #64512
+ 687 0060 9342     		cmp	r3, r2
+ 688 0062 19D0     		beq	.L36
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 689              		.loc 1 348 7 discriminator 2 view .LVU222
+ 690 0064 02F58062 		add	r2, r2, #1024
+ 691 0068 9342     		cmp	r3, r2
+ 692 006a 15D0     		beq	.L36
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 693              		.loc 1 348 7 discriminator 3 view .LVU223
+ 694 006c 02F58062 		add	r2, r2, #1024
+ 695 0070 9342     		cmp	r3, r2
+ 696 0072 11D0     		beq	.L36
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 697              		.loc 1 348 7 discriminator 4 view .LVU224
+ 698 0074 02F57842 		add	r2, r2, #63488
+ 699 0078 9342     		cmp	r3, r2
+ 700 007a 0DD0     		beq	.L36
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 701              		.loc 1 348 7 discriminator 5 view .LVU225
+ 702 007c 02F57052 		add	r2, r2, #15360
+ARM GAS  /tmp/cc7KL1Mv.s 			page 62
+
+
+ 703 0080 9342     		cmp	r3, r2
+ 704 0082 09D0     		beq	.L36
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 705              		.loc 1 348 7 discriminator 6 view .LVU226
+ 706 0084 A2F59432 		sub	r2, r2, #75776
+ 707 0088 9342     		cmp	r3, r2
+ 708 008a 05D0     		beq	.L36
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 709              		.loc 1 358 5 is_stmt 1 view .LVU227
+ 710 008c 1A68     		ldr	r2, [r3]
+ 711 008e 42F00102 		orr	r2, r2, #1
+ 712 0092 1A60     		str	r2, [r3]
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 713              		.loc 1 362 10 is_stmt 0 view .LVU228
+ 714 0094 0020     		movs	r0, #0
+ 715 0096 0EE0     		b	.L35
+ 716              	.L36:
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 717              		.loc 1 350 5 is_stmt 1 view .LVU229
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 718              		.loc 1 350 29 is_stmt 0 view .LVU230
+ 719 0098 9968     		ldr	r1, [r3, #8]
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 720              		.loc 1 350 13 view .LVU231
+ 721 009a 0A4A     		ldr	r2, .L42+4
+ 722 009c 0A40     		ands	r2, r2, r1
+ 723              	.LVL38:
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 724              		.loc 1 351 5 is_stmt 1 view .LVU232
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 725              		.loc 1 351 8 is_stmt 0 view .LVU233
+ 726 009e 062A     		cmp	r2, #6
+ 727 00a0 18BF     		it	ne
+ 728 00a2 B2F5803F 		cmpne	r2, #65536
+ 729 00a6 09D0     		beq	.L40
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 730              		.loc 1 353 7 is_stmt 1 view .LVU234
+ 731 00a8 1A68     		ldr	r2, [r3]
+ 732              	.LVL39:
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 733              		.loc 1 353 7 is_stmt 0 view .LVU235
+ 734 00aa 42F00102 		orr	r2, r2, #1
+ 735 00ae 1A60     		str	r2, [r3]
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 736              		.loc 1 362 10 view .LVU236
+ 737 00b0 0020     		movs	r0, #0
+ 738 00b2 00E0     		b	.L35
+ 739              	.LVL40:
+ 740              	.L38:
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 741              		.loc 1 333 12 view .LVU237
+ 742 00b4 0120     		movs	r0, #1
+ 743              	.LVL41:
+ 744              	.L35:
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 745              		.loc 1 363 1 view .LVU238
+ 746 00b6 10BD     		pop	{r4, pc}
+ARM GAS  /tmp/cc7KL1Mv.s 			page 63
+
+
+ 747              	.LVL42:
+ 748              	.L39:
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 749              		.loc 1 333 12 view .LVU239
+ 750 00b8 0120     		movs	r0, #1
+ 751              	.LVL43:
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 752              		.loc 1 333 12 view .LVU240
+ 753 00ba FCE7     		b	.L35
+ 754              	.LVL44:
+ 755              	.L40:
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 756              		.loc 1 362 10 view .LVU241
+ 757 00bc 0020     		movs	r0, #0
+ 758 00be FAE7     		b	.L35
+ 759              	.L43:
+ 760              		.align	2
+ 761              	.L42:
+ 762 00c0 00000140 		.word	1073807360
+ 763 00c4 07000100 		.word	65543
+ 764              		.cfi_endproc
+ 765              	.LFE145:
+ 767              		.section	.text.HAL_TIMEx_HallSensor_Stop,"ax",%progbits
+ 768              		.align	1
+ 769              		.global	HAL_TIMEx_HallSensor_Stop
+ 770              		.syntax unified
+ 771              		.thumb
+ 772              		.thumb_func
+ 773              		.fpu fpv5-d16
+ 775              	HAL_TIMEx_HallSensor_Stop:
+ 776              	.LVL45:
+ 777              	.LFB146:
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 778              		.loc 1 371 1 is_stmt 1 view -0
+ 779              		.cfi_startproc
+ 780              		@ args = 0, pretend = 0, frame = 0
+ 781              		@ frame_needed = 0, uses_anonymous_args = 0
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 782              		.loc 1 371 1 is_stmt 0 view .LVU243
+ 783 0000 10B5     		push	{r4, lr}
+ 784              	.LCFI9:
+ 785              		.cfi_def_cfa_offset 8
+ 786              		.cfi_offset 4, -8
+ 787              		.cfi_offset 14, -4
+ 788 0002 0446     		mov	r4, r0
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 789              		.loc 1 373 3 is_stmt 1 view .LVU244
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 790              		.loc 1 378 3 view .LVU245
+ 791 0004 0022     		movs	r2, #0
+ 792 0006 1146     		mov	r1, r2
+ 793 0008 0068     		ldr	r0, [r0]
+ 794              	.LVL46:
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 795              		.loc 1 378 3 is_stmt 0 view .LVU246
+ 796 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 797              	.LVL47:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 64
+
+
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 798              		.loc 1 381 3 is_stmt 1 view .LVU247
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 799              		.loc 1 381 3 view .LVU248
+ 800 000e 2368     		ldr	r3, [r4]
+ 801 0010 196A     		ldr	r1, [r3, #32]
+ 802 0012 41F21112 		movw	r2, #4369
+ 803 0016 1142     		tst	r1, r2
+ 804 0018 08D1     		bne	.L45
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 805              		.loc 1 381 3 discriminator 1 view .LVU249
+ 806 001a 196A     		ldr	r1, [r3, #32]
+ 807 001c 40F24442 		movw	r2, #1092
+ 808 0020 1142     		tst	r1, r2
+ 809 0022 03D1     		bne	.L45
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 810              		.loc 1 381 3 discriminator 3 view .LVU250
+ 811 0024 1A68     		ldr	r2, [r3]
+ 812 0026 22F00102 		bic	r2, r2, #1
+ 813 002a 1A60     		str	r2, [r3]
+ 814              	.L45:
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 815              		.loc 1 381 3 discriminator 5 view .LVU251
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 816              		.loc 1 384 3 discriminator 5 view .LVU252
+ 817 002c 0123     		movs	r3, #1
+ 818 002e 84F83E30 		strb	r3, [r4, #62]
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 819              		.loc 1 385 3 discriminator 5 view .LVU253
+ 820 0032 84F83F30 		strb	r3, [r4, #63]
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 821              		.loc 1 386 3 discriminator 5 view .LVU254
+ 822 0036 84F84430 		strb	r3, [r4, #68]
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 823              		.loc 1 387 3 discriminator 5 view .LVU255
+ 824 003a 84F84530 		strb	r3, [r4, #69]
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 825              		.loc 1 390 3 discriminator 5 view .LVU256
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 826              		.loc 1 391 1 is_stmt 0 discriminator 5 view .LVU257
+ 827 003e 0020     		movs	r0, #0
+ 828 0040 10BD     		pop	{r4, pc}
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 829              		.loc 1 391 1 discriminator 5 view .LVU258
+ 830              		.cfi_endproc
+ 831              	.LFE146:
+ 833              		.section	.text.HAL_TIMEx_HallSensor_Start_IT,"ax",%progbits
+ 834              		.align	1
+ 835              		.global	HAL_TIMEx_HallSensor_Start_IT
+ 836              		.syntax unified
+ 837              		.thumb
+ 838              		.thumb_func
+ 839              		.fpu fpv5-d16
+ 841              	HAL_TIMEx_HallSensor_Start_IT:
+ 842              	.LVL48:
+ 843              	.LFB147:
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ARM GAS  /tmp/cc7KL1Mv.s 			page 65
+
+
+ 844              		.loc 1 399 1 is_stmt 1 view -0
+ 845              		.cfi_startproc
+ 846              		@ args = 0, pretend = 0, frame = 0
+ 847              		@ frame_needed = 0, uses_anonymous_args = 0
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 848              		.loc 1 399 1 is_stmt 0 view .LVU260
+ 849 0000 10B5     		push	{r4, lr}
+ 850              	.LCFI10:
+ 851              		.cfi_def_cfa_offset 8
+ 852              		.cfi_offset 4, -8
+ 853              		.cfi_offset 14, -4
+ 854 0002 0446     		mov	r4, r0
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 855              		.loc 1 400 3 is_stmt 1 view .LVU261
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 856              		.loc 1 401 3 view .LVU262
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 857              		.loc 1 401 31 is_stmt 0 view .LVU263
+ 858 0004 90F83E10 		ldrb	r1, [r0, #62]	@ zero_extendqisi2
+ 859 0008 C9B2     		uxtb	r1, r1
+ 860              	.LVL49:
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 861              		.loc 1 402 3 is_stmt 1 view .LVU264
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 862              		.loc 1 402 31 is_stmt 0 view .LVU265
+ 863 000a 90F83F20 		ldrb	r2, [r0, #63]	@ zero_extendqisi2
+ 864 000e D2B2     		uxtb	r2, r2
+ 865              	.LVL50:
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 866              		.loc 1 403 3 is_stmt 1 view .LVU266
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 867              		.loc 1 403 31 is_stmt 0 view .LVU267
+ 868 0010 90F84430 		ldrb	r3, [r0, #68]	@ zero_extendqisi2
+ 869 0014 D8B2     		uxtb	r0, r3
+ 870              	.LVL51:
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 871              		.loc 1 404 3 is_stmt 1 view .LVU268
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 872              		.loc 1 404 31 is_stmt 0 view .LVU269
+ 873 0016 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 874              	.LVL52:
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 875              		.loc 1 407 3 is_stmt 1 view .LVU270
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 876              		.loc 1 410 3 view .LVU271
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 877              		.loc 1 410 6 is_stmt 0 view .LVU272
+ 878 001a 012A     		cmp	r2, #1
+ 879 001c 08BF     		it	eq
+ 880 001e 0129     		cmpeq	r1, #1
+ 881 0020 4DD1     		bne	.L51
+ 882 0022 DBB2     		uxtb	r3, r3
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 883              		.loc 1 413 41 view .LVU273
+ 884 0024 013B     		subs	r3, r3, #1
+ 885              	.LVL53:
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 66
+
+
+ 886              		.loc 1 413 41 view .LVU274
+ 887 0026 18BF     		it	ne
+ 888 0028 0123     		movne	r3, #1
+ 889              	.LVL54:
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 890              		.loc 1 413 7 view .LVU275
+ 891 002a 0128     		cmp	r0, #1
+ 892 002c 49D1     		bne	.L52
+ 893 002e 002B     		cmp	r3, #0
+ 894 0030 47D1     		bne	.L52
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 895              		.loc 1 419 3 is_stmt 1 view .LVU276
+ 896 0032 0223     		movs	r3, #2
+ 897 0034 84F83E30 		strb	r3, [r4, #62]
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 898              		.loc 1 420 3 view .LVU277
+ 899 0038 84F83F30 		strb	r3, [r4, #63]
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 900              		.loc 1 421 3 view .LVU278
+ 901 003c 84F84430 		strb	r3, [r4, #68]
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 902              		.loc 1 422 3 view .LVU279
+ 903 0040 84F84530 		strb	r3, [r4, #69]
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 904              		.loc 1 425 3 view .LVU280
+ 905 0044 2268     		ldr	r2, [r4]
+ 906              	.LVL55:
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 907              		.loc 1 425 3 is_stmt 0 view .LVU281
+ 908 0046 D368     		ldr	r3, [r2, #12]
+ 909 0048 43F00203 		orr	r3, r3, #2
+ 910 004c D360     		str	r3, [r2, #12]
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 911              		.loc 1 430 3 is_stmt 1 view .LVU282
+ 912 004e 0122     		movs	r2, #1
+ 913 0050 0021     		movs	r1, #0
+ 914              	.LVL56:
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 915              		.loc 1 430 3 is_stmt 0 view .LVU283
+ 916 0052 2068     		ldr	r0, [r4]
+ 917              	.LVL57:
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 918              		.loc 1 430 3 view .LVU284
+ 919 0054 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 920              	.LVL58:
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 921              		.loc 1 433 3 is_stmt 1 view .LVU285
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 922              		.loc 1 433 7 is_stmt 0 view .LVU286
+ 923 0058 2368     		ldr	r3, [r4]
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 924              		.loc 1 433 6 view .LVU287
+ 925 005a 1C4A     		ldr	r2, .L55
+ 926 005c B3F1804F 		cmp	r3, #1073741824
+ 927 0060 18BF     		it	ne
+ 928 0062 9342     		cmpne	r3, r2
+ 929 0064 1DD0     		beq	.L49
+ARM GAS  /tmp/cc7KL1Mv.s 			page 67
+
+
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 930              		.loc 1 433 7 discriminator 1 view .LVU288
+ 931 0066 A2F57C42 		sub	r2, r2, #64512
+ 932 006a 9342     		cmp	r3, r2
+ 933 006c 19D0     		beq	.L49
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 934              		.loc 1 433 7 discriminator 2 view .LVU289
+ 935 006e 02F58062 		add	r2, r2, #1024
+ 936 0072 9342     		cmp	r3, r2
+ 937 0074 15D0     		beq	.L49
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 938              		.loc 1 433 7 discriminator 3 view .LVU290
+ 939 0076 02F58062 		add	r2, r2, #1024
+ 940 007a 9342     		cmp	r3, r2
+ 941 007c 11D0     		beq	.L49
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 942              		.loc 1 433 7 discriminator 4 view .LVU291
+ 943 007e 02F57842 		add	r2, r2, #63488
+ 944 0082 9342     		cmp	r3, r2
+ 945 0084 0DD0     		beq	.L49
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 946              		.loc 1 433 7 discriminator 5 view .LVU292
+ 947 0086 02F57052 		add	r2, r2, #15360
+ 948 008a 9342     		cmp	r3, r2
+ 949 008c 09D0     		beq	.L49
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 950              		.loc 1 433 7 discriminator 6 view .LVU293
+ 951 008e A2F59432 		sub	r2, r2, #75776
+ 952 0092 9342     		cmp	r3, r2
+ 953 0094 05D0     		beq	.L49
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 954              		.loc 1 443 5 is_stmt 1 view .LVU294
+ 955 0096 1A68     		ldr	r2, [r3]
+ 956 0098 42F00102 		orr	r2, r2, #1
+ 957 009c 1A60     		str	r2, [r3]
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 958              		.loc 1 447 10 is_stmt 0 view .LVU295
+ 959 009e 0020     		movs	r0, #0
+ 960 00a0 0EE0     		b	.L48
+ 961              	.L49:
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 962              		.loc 1 435 5 is_stmt 1 view .LVU296
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 963              		.loc 1 435 29 is_stmt 0 view .LVU297
+ 964 00a2 9968     		ldr	r1, [r3, #8]
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 965              		.loc 1 435 13 view .LVU298
+ 966 00a4 0A4A     		ldr	r2, .L55+4
+ 967 00a6 0A40     		ands	r2, r2, r1
+ 968              	.LVL59:
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 969              		.loc 1 436 5 is_stmt 1 view .LVU299
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 970              		.loc 1 436 8 is_stmt 0 view .LVU300
+ 971 00a8 062A     		cmp	r2, #6
+ 972 00aa 18BF     		it	ne
+ 973 00ac B2F5803F 		cmpne	r2, #65536
+ARM GAS  /tmp/cc7KL1Mv.s 			page 68
+
+
+ 974 00b0 09D0     		beq	.L53
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 975              		.loc 1 438 7 is_stmt 1 view .LVU301
+ 976 00b2 1A68     		ldr	r2, [r3]
+ 977              	.LVL60:
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 978              		.loc 1 438 7 is_stmt 0 view .LVU302
+ 979 00b4 42F00102 		orr	r2, r2, #1
+ 980 00b8 1A60     		str	r2, [r3]
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 981              		.loc 1 447 10 view .LVU303
+ 982 00ba 0020     		movs	r0, #0
+ 983 00bc 00E0     		b	.L48
+ 984              	.LVL61:
+ 985              	.L51:
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 986              		.loc 1 415 12 view .LVU304
+ 987 00be 0120     		movs	r0, #1
+ 988              	.LVL62:
+ 989              	.L48:
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 990              		.loc 1 448 1 view .LVU305
+ 991 00c0 10BD     		pop	{r4, pc}
+ 992              	.LVL63:
+ 993              	.L52:
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 994              		.loc 1 415 12 view .LVU306
+ 995 00c2 0120     		movs	r0, #1
+ 996              	.LVL64:
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 997              		.loc 1 415 12 view .LVU307
+ 998 00c4 FCE7     		b	.L48
+ 999              	.LVL65:
+ 1000              	.L53:
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 1001              		.loc 1 447 10 view .LVU308
+ 1002 00c6 0020     		movs	r0, #0
+ 1003 00c8 FAE7     		b	.L48
+ 1004              	.L56:
+ 1005 00ca 00BF     		.align	2
+ 1006              	.L55:
+ 1007 00cc 00000140 		.word	1073807360
+ 1008 00d0 07000100 		.word	65543
+ 1009              		.cfi_endproc
+ 1010              	.LFE147:
+ 1012              		.section	.text.HAL_TIMEx_HallSensor_Stop_IT,"ax",%progbits
+ 1013              		.align	1
+ 1014              		.global	HAL_TIMEx_HallSensor_Stop_IT
+ 1015              		.syntax unified
+ 1016              		.thumb
+ 1017              		.thumb_func
+ 1018              		.fpu fpv5-d16
+ 1020              	HAL_TIMEx_HallSensor_Stop_IT:
+ 1021              	.LVL66:
+ 1022              	.LFB148:
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1023              		.loc 1 456 1 is_stmt 1 view -0
+ARM GAS  /tmp/cc7KL1Mv.s 			page 69
+
+
+ 1024              		.cfi_startproc
+ 1025              		@ args = 0, pretend = 0, frame = 0
+ 1026              		@ frame_needed = 0, uses_anonymous_args = 0
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1027              		.loc 1 456 1 is_stmt 0 view .LVU310
+ 1028 0000 10B5     		push	{r4, lr}
+ 1029              	.LCFI11:
+ 1030              		.cfi_def_cfa_offset 8
+ 1031              		.cfi_offset 4, -8
+ 1032              		.cfi_offset 14, -4
+ 1033 0002 0446     		mov	r4, r0
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1034              		.loc 1 458 3 is_stmt 1 view .LVU311
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1035              		.loc 1 463 3 view .LVU312
+ 1036 0004 0022     		movs	r2, #0
+ 1037 0006 1146     		mov	r1, r2
+ 1038 0008 0068     		ldr	r0, [r0]
+ 1039              	.LVL67:
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1040              		.loc 1 463 3 is_stmt 0 view .LVU313
+ 1041 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 1042              	.LVL68:
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1043              		.loc 1 466 3 is_stmt 1 view .LVU314
+ 1044 000e 2268     		ldr	r2, [r4]
+ 1045 0010 D368     		ldr	r3, [r2, #12]
+ 1046 0012 23F00203 		bic	r3, r3, #2
+ 1047 0016 D360     		str	r3, [r2, #12]
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1048              		.loc 1 469 3 view .LVU315
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1049              		.loc 1 469 3 view .LVU316
+ 1050 0018 2368     		ldr	r3, [r4]
+ 1051 001a 196A     		ldr	r1, [r3, #32]
+ 1052 001c 41F21112 		movw	r2, #4369
+ 1053 0020 1142     		tst	r1, r2
+ 1054 0022 08D1     		bne	.L58
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1055              		.loc 1 469 3 discriminator 1 view .LVU317
+ 1056 0024 196A     		ldr	r1, [r3, #32]
+ 1057 0026 40F24442 		movw	r2, #1092
+ 1058 002a 1142     		tst	r1, r2
+ 1059 002c 03D1     		bne	.L58
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1060              		.loc 1 469 3 discriminator 3 view .LVU318
+ 1061 002e 1A68     		ldr	r2, [r3]
+ 1062 0030 22F00102 		bic	r2, r2, #1
+ 1063 0034 1A60     		str	r2, [r3]
+ 1064              	.L58:
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1065              		.loc 1 469 3 discriminator 5 view .LVU319
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 1066              		.loc 1 472 3 discriminator 5 view .LVU320
+ 1067 0036 0123     		movs	r3, #1
+ 1068 0038 84F83E30 		strb	r3, [r4, #62]
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ARM GAS  /tmp/cc7KL1Mv.s 			page 70
+
+
+ 1069              		.loc 1 473 3 discriminator 5 view .LVU321
+ 1070 003c 84F83F30 		strb	r3, [r4, #63]
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 1071              		.loc 1 474 3 discriminator 5 view .LVU322
+ 1072 0040 84F84430 		strb	r3, [r4, #68]
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1073              		.loc 1 475 3 discriminator 5 view .LVU323
+ 1074 0044 84F84530 		strb	r3, [r4, #69]
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 1075              		.loc 1 478 3 discriminator 5 view .LVU324
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1076              		.loc 1 479 1 is_stmt 0 discriminator 5 view .LVU325
+ 1077 0048 0020     		movs	r0, #0
+ 1078 004a 10BD     		pop	{r4, pc}
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1079              		.loc 1 479 1 discriminator 5 view .LVU326
+ 1080              		.cfi_endproc
+ 1081              	.LFE148:
+ 1083              		.section	.text.HAL_TIMEx_HallSensor_Start_DMA,"ax",%progbits
+ 1084              		.align	1
+ 1085              		.global	HAL_TIMEx_HallSensor_Start_DMA
+ 1086              		.syntax unified
+ 1087              		.thumb
+ 1088              		.thumb_func
+ 1089              		.fpu fpv5-d16
+ 1091              	HAL_TIMEx_HallSensor_Start_DMA:
+ 1092              	.LVL69:
+ 1093              	.LFB149:
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 1094              		.loc 1 489 1 is_stmt 1 view -0
+ 1095              		.cfi_startproc
+ 1096              		@ args = 0, pretend = 0, frame = 0
+ 1097              		@ frame_needed = 0, uses_anonymous_args = 0
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 1098              		.loc 1 489 1 is_stmt 0 view .LVU328
+ 1099 0000 70B5     		push	{r4, r5, r6, lr}
+ 1100              	.LCFI12:
+ 1101              		.cfi_def_cfa_offset 16
+ 1102              		.cfi_offset 4, -16
+ 1103              		.cfi_offset 5, -12
+ 1104              		.cfi_offset 6, -8
+ 1105              		.cfi_offset 14, -4
+ 1106 0002 0446     		mov	r4, r0
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 1107              		.loc 1 490 3 is_stmt 1 view .LVU329
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 1108              		.loc 1 491 3 view .LVU330
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 1109              		.loc 1 491 31 is_stmt 0 view .LVU331
+ 1110 0004 90F83EC0 		ldrb	ip, [r0, #62]	@ zero_extendqisi2
+ 1111 0008 5FFA8CFC 		uxtb	ip, ip
+ 1112              	.LVL70:
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1113              		.loc 1 492 3 is_stmt 1 view .LVU332
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1114              		.loc 1 492 31 is_stmt 0 view .LVU333
+ 1115 000c 90F84400 		ldrb	r0, [r0, #68]	@ zero_extendqisi2
+ARM GAS  /tmp/cc7KL1Mv.s 			page 71
+
+
+ 1116              	.LVL71:
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1117              		.loc 1 492 31 view .LVU334
+ 1118 0010 C0B2     		uxtb	r0, r0
+ 1119              	.LVL72:
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1120              		.loc 1 495 3 is_stmt 1 view .LVU335
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 1121              		.loc 1 498 3 view .LVU336
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ 1122              		.loc 1 498 6 is_stmt 0 view .LVU337
+ 1123 0012 0228     		cmp	r0, #2
+ 1124 0014 18BF     		it	ne
+ 1125 0016 BCF1020F 		cmpne	ip, #2
+ 1126 001a 5ED0     		beq	.L64
+ 1127 001c 0E46     		mov	r6, r1
+ 1128 001e 1546     		mov	r5, r2
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****            && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ 1129              		.loc 1 503 8 is_stmt 1 view .LVU338
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****            && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ 1130              		.loc 1 503 11 is_stmt 0 view .LVU339
+ 1131 0020 BCF1010F 		cmp	ip, #1
+ 1132 0024 08BF     		it	eq
+ 1133 0026 0128     		cmpeq	r0, #1
+ 1134 0028 59D1     		bne	.L65
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1135              		.loc 1 506 5 is_stmt 1 view .LVU340
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1136              		.loc 1 506 8 is_stmt 0 view .LVU341
+ 1137 002a 002A     		cmp	r2, #0
+ 1138 002c 18BF     		it	ne
+ 1139 002e 0029     		cmpne	r1, #0
+ 1140 0030 01D1     		bne	.L69
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1141              		.loc 1 508 14 view .LVU342
+ 1142 0032 0120     		movs	r0, #1
+ 1143              	.LVL73:
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1144              		.loc 1 508 14 view .LVU343
+ 1145 0034 54E0     		b	.L61
+ 1146              	.LVL74:
+ 1147              	.L69:
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 1148              		.loc 1 512 7 is_stmt 1 view .LVU344
+ 1149 0036 0223     		movs	r3, #2
+ 1150 0038 84F83E30 		strb	r3, [r4, #62]
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1151              		.loc 1 513 7 view .LVU345
+ 1152 003c 84F84430 		strb	r3, [r4, #68]
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1153              		.loc 1 524 3 view .LVU346
+ 1154 0040 0122     		movs	r2, #1
+ 1155              	.LVL75:
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1156              		.loc 1 524 3 is_stmt 0 view .LVU347
+ 1157 0042 0021     		movs	r1, #0
+ 1158              	.LVL76:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 72
+
+
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1159              		.loc 1 524 3 view .LVU348
+ 1160 0044 2068     		ldr	r0, [r4]
+ 1161              	.LVL77:
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1162              		.loc 1 524 3 view .LVU349
+ 1163 0046 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 1164              	.LVL78:
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 1165              		.loc 1 527 3 is_stmt 1 view .LVU350
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 1166              		.loc 1 527 13 is_stmt 0 view .LVU351
+ 1167 004a 636A     		ldr	r3, [r4, #36]
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ 1168              		.loc 1 527 48 view .LVU352
+ 1169 004c 264A     		ldr	r2, .L70
+ 1170 004e DA63     		str	r2, [r3, #60]
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 1171              		.loc 1 528 3 is_stmt 1 view .LVU353
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 1172              		.loc 1 528 13 is_stmt 0 view .LVU354
+ 1173 0050 636A     		ldr	r3, [r4, #36]
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 1174              		.loc 1 528 52 view .LVU355
+ 1175 0052 264A     		ldr	r2, .L70+4
+ 1176 0054 1A64     		str	r2, [r3, #64]
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1177              		.loc 1 530 3 is_stmt 1 view .LVU356
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1178              		.loc 1 530 13 is_stmt 0 view .LVU357
+ 1179 0056 636A     		ldr	r3, [r4, #36]
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1180              		.loc 1 530 49 view .LVU358
+ 1181 0058 254A     		ldr	r2, .L70+8
+ 1182 005a DA64     		str	r2, [r3, #76]
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1183              		.loc 1 533 3 is_stmt 1 view .LVU359
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1184              		.loc 1 533 67 is_stmt 0 view .LVU360
+ 1185 005c 2168     		ldr	r1, [r4]
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1186              		.loc 1 533 7 view .LVU361
+ 1187 005e 2B46     		mov	r3, r5
+ 1188 0060 3246     		mov	r2, r6
+ 1189 0062 3431     		adds	r1, r1, #52
+ 1190 0064 606A     		ldr	r0, [r4, #36]
+ 1191 0066 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 1192              	.LVL79:
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1193              		.loc 1 533 6 view .LVU362
+ 1194 006a 0028     		cmp	r0, #0
+ 1195 006c 39D1     		bne	.L67
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1196              		.loc 1 539 3 is_stmt 1 view .LVU363
+ 1197 006e 2268     		ldr	r2, [r4]
+ 1198 0070 D368     		ldr	r3, [r2, #12]
+ 1199 0072 43F40073 		orr	r3, r3, #512
+ARM GAS  /tmp/cc7KL1Mv.s 			page 73
+
+
+ 1200 0076 D360     		str	r3, [r2, #12]
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1201              		.loc 1 542 3 view .LVU364
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1202              		.loc 1 542 7 is_stmt 0 view .LVU365
+ 1203 0078 2368     		ldr	r3, [r4]
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1204              		.loc 1 542 6 view .LVU366
+ 1205 007a 1E4A     		ldr	r2, .L70+12
+ 1206 007c B3F1804F 		cmp	r3, #1073741824
+ 1207 0080 18BF     		it	ne
+ 1208 0082 9342     		cmpne	r3, r2
+ 1209 0084 1CD0     		beq	.L62
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1210              		.loc 1 542 7 discriminator 1 view .LVU367
+ 1211 0086 A2F57C42 		sub	r2, r2, #64512
+ 1212 008a 9342     		cmp	r3, r2
+ 1213 008c 18D0     		beq	.L62
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1214              		.loc 1 542 7 discriminator 2 view .LVU368
+ 1215 008e 02F58062 		add	r2, r2, #1024
+ 1216 0092 9342     		cmp	r3, r2
+ 1217 0094 14D0     		beq	.L62
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1218              		.loc 1 542 7 discriminator 3 view .LVU369
+ 1219 0096 02F58062 		add	r2, r2, #1024
+ 1220 009a 9342     		cmp	r3, r2
+ 1221 009c 10D0     		beq	.L62
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1222              		.loc 1 542 7 discriminator 4 view .LVU370
+ 1223 009e 02F57842 		add	r2, r2, #63488
+ 1224 00a2 9342     		cmp	r3, r2
+ 1225 00a4 0CD0     		beq	.L62
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1226              		.loc 1 542 7 discriminator 5 view .LVU371
+ 1227 00a6 02F57052 		add	r2, r2, #15360
+ 1228 00aa 9342     		cmp	r3, r2
+ 1229 00ac 08D0     		beq	.L62
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1230              		.loc 1 542 7 discriminator 6 view .LVU372
+ 1231 00ae A2F59432 		sub	r2, r2, #75776
+ 1232 00b2 9342     		cmp	r3, r2
+ 1233 00b4 04D0     		beq	.L62
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 1234              		.loc 1 552 5 is_stmt 1 view .LVU373
+ 1235 00b6 1A68     		ldr	r2, [r3]
+ 1236 00b8 42F00102 		orr	r2, r2, #1
+ 1237 00bc 1A60     		str	r2, [r3]
+ 1238 00be 0FE0     		b	.L61
+ 1239              	.L62:
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1240              		.loc 1 544 5 view .LVU374
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1241              		.loc 1 544 29 is_stmt 0 view .LVU375
+ 1242 00c0 9968     		ldr	r1, [r3, #8]
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1243              		.loc 1 544 13 view .LVU376
+ARM GAS  /tmp/cc7KL1Mv.s 			page 74
+
+
+ 1244 00c2 0D4A     		ldr	r2, .L70+16
+ 1245 00c4 0A40     		ands	r2, r2, r1
+ 1246              	.LVL80:
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1247              		.loc 1 545 5 is_stmt 1 view .LVU377
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1248              		.loc 1 545 8 is_stmt 0 view .LVU378
+ 1249 00c6 062A     		cmp	r2, #6
+ 1250 00c8 18BF     		it	ne
+ 1251 00ca B2F5803F 		cmpne	r2, #65536
+ 1252 00ce 07D0     		beq	.L61
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1253              		.loc 1 547 7 is_stmt 1 view .LVU379
+ 1254 00d0 1A68     		ldr	r2, [r3]
+ 1255              	.LVL81:
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1256              		.loc 1 547 7 is_stmt 0 view .LVU380
+ 1257 00d2 42F00102 		orr	r2, r2, #1
+ 1258 00d6 1A60     		str	r2, [r3]
+ 1259 00d8 02E0     		b	.L61
+ 1260              	.LVL82:
+ 1261              	.L64:
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 1262              		.loc 1 501 12 view .LVU381
+ 1263 00da 0220     		movs	r0, #2
+ 1264              	.LVL83:
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 1265              		.loc 1 501 12 view .LVU382
+ 1266 00dc 00E0     		b	.L61
+ 1267              	.LVL84:
+ 1268              	.L65:
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 1269              		.loc 1 518 12 view .LVU383
+ 1270 00de 0120     		movs	r0, #1
+ 1271              	.LVL85:
+ 1272              	.L61:
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1273              		.loc 1 557 1 view .LVU384
+ 1274 00e0 70BD     		pop	{r4, r5, r6, pc}
+ 1275              	.LVL86:
+ 1276              	.L67:
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 1277              		.loc 1 536 12 view .LVU385
+ 1278 00e2 0120     		movs	r0, #1
+ 1279 00e4 FCE7     		b	.L61
+ 1280              	.L71:
+ 1281 00e6 00BF     		.align	2
+ 1282              	.L70:
+ 1283 00e8 00000000 		.word	TIM_DMACaptureCplt
+ 1284 00ec 00000000 		.word	TIM_DMACaptureHalfCplt
+ 1285 00f0 00000000 		.word	TIM_DMAError
+ 1286 00f4 00000140 		.word	1073807360
+ 1287 00f8 07000100 		.word	65543
+ 1288              		.cfi_endproc
+ 1289              	.LFE149:
+ 1291              		.section	.text.HAL_TIMEx_HallSensor_Stop_DMA,"ax",%progbits
+ 1292              		.align	1
+ARM GAS  /tmp/cc7KL1Mv.s 			page 75
+
+
+ 1293              		.global	HAL_TIMEx_HallSensor_Stop_DMA
+ 1294              		.syntax unified
+ 1295              		.thumb
+ 1296              		.thumb_func
+ 1297              		.fpu fpv5-d16
+ 1299              	HAL_TIMEx_HallSensor_Stop_DMA:
+ 1300              	.LVL87:
+ 1301              	.LFB150:
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1302              		.loc 1 565 1 is_stmt 1 view -0
+ 1303              		.cfi_startproc
+ 1304              		@ args = 0, pretend = 0, frame = 0
+ 1305              		@ frame_needed = 0, uses_anonymous_args = 0
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1306              		.loc 1 565 1 is_stmt 0 view .LVU387
+ 1307 0000 10B5     		push	{r4, lr}
+ 1308              	.LCFI13:
+ 1309              		.cfi_def_cfa_offset 8
+ 1310              		.cfi_offset 4, -8
+ 1311              		.cfi_offset 14, -4
+ 1312 0002 0446     		mov	r4, r0
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1313              		.loc 1 567 3 is_stmt 1 view .LVU388
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1314              		.loc 1 572 3 view .LVU389
+ 1315 0004 0022     		movs	r2, #0
+ 1316 0006 1146     		mov	r1, r2
+ 1317 0008 0068     		ldr	r0, [r0]
+ 1318              	.LVL88:
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1319              		.loc 1 572 3 is_stmt 0 view .LVU390
+ 1320 000a FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 1321              	.LVL89:
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1322              		.loc 1 576 3 is_stmt 1 view .LVU391
+ 1323 000e 2268     		ldr	r2, [r4]
+ 1324 0010 D368     		ldr	r3, [r2, #12]
+ 1325 0012 23F40073 		bic	r3, r3, #512
+ 1326 0016 D360     		str	r3, [r2, #12]
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1327              		.loc 1 578 3 view .LVU392
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1328              		.loc 1 578 9 is_stmt 0 view .LVU393
+ 1329 0018 606A     		ldr	r0, [r4, #36]
+ 1330 001a FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 1331              	.LVL90:
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1332              		.loc 1 581 3 is_stmt 1 view .LVU394
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1333              		.loc 1 581 3 view .LVU395
+ 1334 001e 2368     		ldr	r3, [r4]
+ 1335 0020 196A     		ldr	r1, [r3, #32]
+ 1336 0022 41F21112 		movw	r2, #4369
+ 1337 0026 1142     		tst	r1, r2
+ 1338 0028 08D1     		bne	.L73
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1339              		.loc 1 581 3 discriminator 1 view .LVU396
+ARM GAS  /tmp/cc7KL1Mv.s 			page 76
+
+
+ 1340 002a 196A     		ldr	r1, [r3, #32]
+ 1341 002c 40F24442 		movw	r2, #1092
+ 1342 0030 1142     		tst	r1, r2
+ 1343 0032 03D1     		bne	.L73
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1344              		.loc 1 581 3 discriminator 3 view .LVU397
+ 1345 0034 1A68     		ldr	r2, [r3]
+ 1346 0036 22F00102 		bic	r2, r2, #1
+ 1347 003a 1A60     		str	r2, [r3]
+ 1348              	.L73:
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1349              		.loc 1 581 3 discriminator 5 view .LVU398
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 1350              		.loc 1 584 3 discriminator 5 view .LVU399
+ 1351 003c 0123     		movs	r3, #1
+ 1352 003e 84F83E30 		strb	r3, [r4, #62]
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1353              		.loc 1 585 3 discriminator 5 view .LVU400
+ 1354 0042 84F84430 		strb	r3, [r4, #68]
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 1355              		.loc 1 588 3 discriminator 5 view .LVU401
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1356              		.loc 1 589 1 is_stmt 0 discriminator 5 view .LVU402
+ 1357 0046 0020     		movs	r0, #0
+ 1358 0048 10BD     		pop	{r4, pc}
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1359              		.loc 1 589 1 discriminator 5 view .LVU403
+ 1360              		.cfi_endproc
+ 1361              	.LFE150:
+ 1363              		.section	.text.HAL_TIMEx_OCN_Start,"ax",%progbits
+ 1364              		.align	1
+ 1365              		.global	HAL_TIMEx_OCN_Start
+ 1366              		.syntax unified
+ 1367              		.thumb
+ 1368              		.thumb_func
+ 1369              		.fpu fpv5-d16
+ 1371              	HAL_TIMEx_OCN_Start:
+ 1372              	.LVL91:
+ 1373              	.LFB151:
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 1374              		.loc 1 627 1 is_stmt 1 view -0
+ 1375              		.cfi_startproc
+ 1376              		@ args = 0, pretend = 0, frame = 0
+ 1377              		@ frame_needed = 0, uses_anonymous_args = 0
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 1378              		.loc 1 627 1 is_stmt 0 view .LVU405
+ 1379 0000 10B5     		push	{r4, lr}
+ 1380              	.LCFI14:
+ 1381              		.cfi_def_cfa_offset 8
+ 1382              		.cfi_offset 4, -8
+ 1383              		.cfi_offset 14, -4
+ 1384 0002 0446     		mov	r4, r0
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1385              		.loc 1 628 3 is_stmt 1 view .LVU406
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1386              		.loc 1 631 3 view .LVU407
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 77
+
+
+ 1387              		.loc 1 634 3 view .LVU408
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1388              		.loc 1 634 46 is_stmt 0 view .LVU409
+ 1389 0004 0846     		mov	r0, r1
+ 1390              	.LVL92:
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1391              		.loc 1 634 46 view .LVU410
+ 1392 0006 0029     		cmp	r1, #0
+ 1393 0008 3BD1     		bne	.L76
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1394              		.loc 1 634 7 discriminator 1 view .LVU411
+ 1395 000a 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ 1396 000e DBB2     		uxtb	r3, r3
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1397              		.loc 1 634 46 discriminator 1 view .LVU412
+ 1398 0010 013B     		subs	r3, r3, #1
+ 1399 0012 18BF     		it	ne
+ 1400 0014 0123     		movne	r3, #1
+ 1401              	.L77:
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1402              		.loc 1 634 6 discriminator 12 view .LVU413
+ 1403 0016 002B     		cmp	r3, #0
+ 1404 0018 6AD1     		bne	.L87
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1405              		.loc 1 640 3 is_stmt 1 view .LVU414
+ 1406 001a 0028     		cmp	r0, #0
+ 1407 001c 4AD1     		bne	.L81
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1408              		.loc 1 640 3 is_stmt 0 discriminator 1 view .LVU415
+ 1409 001e 0223     		movs	r3, #2
+ 1410 0020 84F84430 		strb	r3, [r4, #68]
+ 1411              	.L82:
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1412              		.loc 1 643 3 is_stmt 1 view .LVU416
+ 1413 0024 0422     		movs	r2, #4
+ 1414 0026 0146     		mov	r1, r0
+ 1415              	.LVL93:
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1416              		.loc 1 643 3 is_stmt 0 view .LVU417
+ 1417 0028 2068     		ldr	r0, [r4]
+ 1418              	.LVL94:
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1419              		.loc 1 643 3 view .LVU418
+ 1420 002a FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 1421              	.LVL95:
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1422              		.loc 1 646 3 is_stmt 1 view .LVU419
+ 1423 002e 2268     		ldr	r2, [r4]
+ 1424 0030 536C     		ldr	r3, [r2, #68]
+ 1425 0032 43F40043 		orr	r3, r3, #32768
+ 1426 0036 5364     		str	r3, [r2, #68]
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1427              		.loc 1 649 3 view .LVU420
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1428              		.loc 1 649 7 is_stmt 0 view .LVU421
+ 1429 0038 2368     		ldr	r3, [r4]
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 78
+
+
+ 1430              		.loc 1 649 6 view .LVU422
+ 1431 003a 2F4A     		ldr	r2, .L94
+ 1432 003c B3F1804F 		cmp	r3, #1073741824
+ 1433 0040 18BF     		it	ne
+ 1434 0042 9342     		cmpne	r3, r2
+ 1435 0044 46D0     		beq	.L85
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1436              		.loc 1 649 7 discriminator 1 view .LVU423
+ 1437 0046 A2F57C42 		sub	r2, r2, #64512
+ 1438 004a 9342     		cmp	r3, r2
+ 1439 004c 42D0     		beq	.L85
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1440              		.loc 1 649 7 discriminator 2 view .LVU424
+ 1441 004e 02F58062 		add	r2, r2, #1024
+ 1442 0052 9342     		cmp	r3, r2
+ 1443 0054 3ED0     		beq	.L85
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1444              		.loc 1 649 7 discriminator 3 view .LVU425
+ 1445 0056 02F58062 		add	r2, r2, #1024
+ 1446 005a 9342     		cmp	r3, r2
+ 1447 005c 3AD0     		beq	.L85
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1448              		.loc 1 649 7 discriminator 4 view .LVU426
+ 1449 005e 02F57842 		add	r2, r2, #63488
+ 1450 0062 9342     		cmp	r3, r2
+ 1451 0064 36D0     		beq	.L85
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1452              		.loc 1 649 7 discriminator 5 view .LVU427
+ 1453 0066 02F57052 		add	r2, r2, #15360
+ 1454 006a 9342     		cmp	r3, r2
+ 1455 006c 32D0     		beq	.L85
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1456              		.loc 1 649 7 discriminator 6 view .LVU428
+ 1457 006e A2F59432 		sub	r2, r2, #75776
+ 1458 0072 9342     		cmp	r3, r2
+ 1459 0074 2ED0     		beq	.L85
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 1460              		.loc 1 659 5 is_stmt 1 view .LVU429
+ 1461 0076 1A68     		ldr	r2, [r3]
+ 1462 0078 42F00102 		orr	r2, r2, #1
+ 1463 007c 1A60     		str	r2, [r3]
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 1464              		.loc 1 663 10 is_stmt 0 view .LVU430
+ 1465 007e 0020     		movs	r0, #0
+ 1466 0080 37E0     		b	.L80
+ 1467              	.LVL96:
+ 1468              	.L76:
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1469              		.loc 1 634 46 discriminator 2 view .LVU431
+ 1470 0082 0429     		cmp	r1, #4
+ 1471 0084 08D0     		beq	.L90
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1472              		.loc 1 634 46 discriminator 5 view .LVU432
+ 1473 0086 0829     		cmp	r1, #8
+ 1474 0088 0DD0     		beq	.L91
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1475              		.loc 1 634 7 discriminator 8 view .LVU433
+ARM GAS  /tmp/cc7KL1Mv.s 			page 79
+
+
+ 1476 008a 94F84730 		ldrb	r3, [r4, #71]	@ zero_extendqisi2
+ 1477 008e DBB2     		uxtb	r3, r3
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1478              		.loc 1 634 46 discriminator 8 view .LVU434
+ 1479 0090 013B     		subs	r3, r3, #1
+ 1480 0092 18BF     		it	ne
+ 1481 0094 0123     		movne	r3, #1
+ 1482 0096 BEE7     		b	.L77
+ 1483              	.L90:
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1484              		.loc 1 634 7 discriminator 4 view .LVU435
+ 1485 0098 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 1486 009c DBB2     		uxtb	r3, r3
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1487              		.loc 1 634 46 discriminator 4 view .LVU436
+ 1488 009e 013B     		subs	r3, r3, #1
+ 1489 00a0 18BF     		it	ne
+ 1490 00a2 0123     		movne	r3, #1
+ 1491 00a4 B7E7     		b	.L77
+ 1492              	.L91:
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1493              		.loc 1 634 7 discriminator 7 view .LVU437
+ 1494 00a6 94F84630 		ldrb	r3, [r4, #70]	@ zero_extendqisi2
+ 1495 00aa DBB2     		uxtb	r3, r3
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1496              		.loc 1 634 46 discriminator 7 view .LVU438
+ 1497 00ac 013B     		subs	r3, r3, #1
+ 1498 00ae 18BF     		it	ne
+ 1499 00b0 0123     		movne	r3, #1
+ 1500 00b2 B0E7     		b	.L77
+ 1501              	.L81:
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1502              		.loc 1 640 3 discriminator 2 view .LVU439
+ 1503 00b4 0428     		cmp	r0, #4
+ 1504 00b6 05D0     		beq	.L92
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1505              		.loc 1 640 3 discriminator 4 view .LVU440
+ 1506 00b8 0828     		cmp	r0, #8
+ 1507 00ba 07D0     		beq	.L93
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1508              		.loc 1 640 3 discriminator 7 view .LVU441
+ 1509 00bc 0223     		movs	r3, #2
+ 1510 00be 84F84730 		strb	r3, [r4, #71]
+ 1511 00c2 AFE7     		b	.L82
+ 1512              	.L92:
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1513              		.loc 1 640 3 discriminator 3 view .LVU442
+ 1514 00c4 0223     		movs	r3, #2
+ 1515 00c6 84F84530 		strb	r3, [r4, #69]
+ 1516 00ca ABE7     		b	.L82
+ 1517              	.L93:
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1518              		.loc 1 640 3 discriminator 6 view .LVU443
+ 1519 00cc 0223     		movs	r3, #2
+ 1520 00ce 84F84630 		strb	r3, [r4, #70]
+ 1521 00d2 A7E7     		b	.L82
+ 1522              	.LVL97:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 80
+
+
+ 1523              	.L85:
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1524              		.loc 1 651 5 is_stmt 1 view .LVU444
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1525              		.loc 1 651 29 is_stmt 0 view .LVU445
+ 1526 00d4 9968     		ldr	r1, [r3, #8]
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1527              		.loc 1 651 13 view .LVU446
+ 1528 00d6 094A     		ldr	r2, .L94+4
+ 1529 00d8 0A40     		ands	r2, r2, r1
+ 1530              	.LVL98:
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1531              		.loc 1 652 5 is_stmt 1 view .LVU447
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1532              		.loc 1 652 8 is_stmt 0 view .LVU448
+ 1533 00da 062A     		cmp	r2, #6
+ 1534 00dc 18BF     		it	ne
+ 1535 00de B2F5803F 		cmpne	r2, #65536
+ 1536 00e2 07D0     		beq	.L88
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1537              		.loc 1 654 7 is_stmt 1 view .LVU449
+ 1538 00e4 1A68     		ldr	r2, [r3]
+ 1539              	.LVL99:
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1540              		.loc 1 654 7 is_stmt 0 view .LVU450
+ 1541 00e6 42F00102 		orr	r2, r2, #1
+ 1542 00ea 1A60     		str	r2, [r3]
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 1543              		.loc 1 663 10 view .LVU451
+ 1544 00ec 0020     		movs	r0, #0
+ 1545 00ee 00E0     		b	.L80
+ 1546              	.LVL100:
+ 1547              	.L87:
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 1548              		.loc 1 636 12 view .LVU452
+ 1549 00f0 0120     		movs	r0, #1
+ 1550              	.LVL101:
+ 1551              	.L80:
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1552              		.loc 1 664 1 view .LVU453
+ 1553 00f2 10BD     		pop	{r4, pc}
+ 1554              	.LVL102:
+ 1555              	.L88:
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 1556              		.loc 1 663 10 view .LVU454
+ 1557 00f4 0020     		movs	r0, #0
+ 1558 00f6 FCE7     		b	.L80
+ 1559              	.L95:
+ 1560              		.align	2
+ 1561              	.L94:
+ 1562 00f8 00000140 		.word	1073807360
+ 1563 00fc 07000100 		.word	65543
+ 1564              		.cfi_endproc
+ 1565              	.LFE151:
+ 1567              		.section	.text.HAL_TIMEx_OCN_Stop,"ax",%progbits
+ 1568              		.align	1
+ 1569              		.global	HAL_TIMEx_OCN_Stop
+ARM GAS  /tmp/cc7KL1Mv.s 			page 81
+
+
+ 1570              		.syntax unified
+ 1571              		.thumb
+ 1572              		.thumb_func
+ 1573              		.fpu fpv5-d16
+ 1575              	HAL_TIMEx_OCN_Stop:
+ 1576              	.LVL103:
+ 1577              	.LFB152:
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1578              		.loc 1 678 1 is_stmt 1 view -0
+ 1579              		.cfi_startproc
+ 1580              		@ args = 0, pretend = 0, frame = 0
+ 1581              		@ frame_needed = 0, uses_anonymous_args = 0
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 1582              		.loc 1 678 1 is_stmt 0 view .LVU456
+ 1583 0000 38B5     		push	{r3, r4, r5, lr}
+ 1584              	.LCFI15:
+ 1585              		.cfi_def_cfa_offset 16
+ 1586              		.cfi_offset 3, -16
+ 1587              		.cfi_offset 4, -12
+ 1588              		.cfi_offset 5, -8
+ 1589              		.cfi_offset 14, -4
+ 1590 0002 0446     		mov	r4, r0
+ 1591 0004 0D46     		mov	r5, r1
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1592              		.loc 1 680 3 is_stmt 1 view .LVU457
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1593              		.loc 1 683 3 view .LVU458
+ 1594 0006 0022     		movs	r2, #0
+ 1595 0008 0068     		ldr	r0, [r0]
+ 1596              	.LVL104:
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1597              		.loc 1 683 3 is_stmt 0 view .LVU459
+ 1598 000a FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 1599              	.LVL105:
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1600              		.loc 1 686 3 is_stmt 1 view .LVU460
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1601              		.loc 1 686 3 view .LVU461
+ 1602 000e 2368     		ldr	r3, [r4]
+ 1603 0010 196A     		ldr	r1, [r3, #32]
+ 1604 0012 41F21112 		movw	r2, #4369
+ 1605 0016 1142     		tst	r1, r2
+ 1606 0018 08D1     		bne	.L97
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1607              		.loc 1 686 3 discriminator 1 view .LVU462
+ 1608 001a 196A     		ldr	r1, [r3, #32]
+ 1609 001c 40F24442 		movw	r2, #1092
+ 1610 0020 1142     		tst	r1, r2
+ 1611 0022 03D1     		bne	.L97
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1612              		.loc 1 686 3 discriminator 3 view .LVU463
+ 1613 0024 5A6C     		ldr	r2, [r3, #68]
+ 1614 0026 22F40042 		bic	r2, r2, #32768
+ 1615 002a 5A64     		str	r2, [r3, #68]
+ 1616              	.L97:
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1617              		.loc 1 686 3 discriminator 5 view .LVU464
+ARM GAS  /tmp/cc7KL1Mv.s 			page 82
+
+
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1618              		.loc 1 689 3 discriminator 5 view .LVU465
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1619              		.loc 1 689 3 discriminator 5 view .LVU466
+ 1620 002c 2368     		ldr	r3, [r4]
+ 1621 002e 196A     		ldr	r1, [r3, #32]
+ 1622 0030 41F21112 		movw	r2, #4369
+ 1623 0034 1142     		tst	r1, r2
+ 1624 0036 08D1     		bne	.L98
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1625              		.loc 1 689 3 discriminator 1 view .LVU467
+ 1626 0038 196A     		ldr	r1, [r3, #32]
+ 1627 003a 40F24442 		movw	r2, #1092
+ 1628 003e 1142     		tst	r1, r2
+ 1629 0040 03D1     		bne	.L98
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1630              		.loc 1 689 3 discriminator 3 view .LVU468
+ 1631 0042 1A68     		ldr	r2, [r3]
+ 1632 0044 22F00102 		bic	r2, r2, #1
+ 1633 0048 1A60     		str	r2, [r3]
+ 1634              	.L98:
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1635              		.loc 1 689 3 discriminator 5 view .LVU469
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1636              		.loc 1 692 3 discriminator 5 view .LVU470
+ 1637 004a 25B9     		cbnz	r5, .L99
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1638              		.loc 1 692 3 is_stmt 0 discriminator 1 view .LVU471
+ 1639 004c 0123     		movs	r3, #1
+ 1640 004e 84F84430 		strb	r3, [r4, #68]
+ 1641              	.L100:
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 1642              		.loc 1 695 3 is_stmt 1 view .LVU472
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1643              		.loc 1 696 1 is_stmt 0 view .LVU473
+ 1644 0052 0020     		movs	r0, #0
+ 1645 0054 38BD     		pop	{r3, r4, r5, pc}
+ 1646              	.LVL106:
+ 1647              	.L99:
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1648              		.loc 1 692 3 discriminator 2 view .LVU474
+ 1649 0056 042D     		cmp	r5, #4
+ 1650 0058 05D0     		beq	.L104
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1651              		.loc 1 692 3 discriminator 4 view .LVU475
+ 1652 005a 082D     		cmp	r5, #8
+ 1653 005c 07D0     		beq	.L105
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1654              		.loc 1 692 3 discriminator 7 view .LVU476
+ 1655 005e 0123     		movs	r3, #1
+ 1656 0060 84F84730 		strb	r3, [r4, #71]
+ 1657 0064 F5E7     		b	.L100
+ 1658              	.L104:
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1659              		.loc 1 692 3 discriminator 3 view .LVU477
+ 1660 0066 0123     		movs	r3, #1
+ 1661 0068 84F84530 		strb	r3, [r4, #69]
+ARM GAS  /tmp/cc7KL1Mv.s 			page 83
+
+
+ 1662 006c F1E7     		b	.L100
+ 1663              	.L105:
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1664              		.loc 1 692 3 discriminator 6 view .LVU478
+ 1665 006e 0123     		movs	r3, #1
+ 1666 0070 84F84630 		strb	r3, [r4, #70]
+ 1667 0074 EDE7     		b	.L100
+ 1668              		.cfi_endproc
+ 1669              	.LFE152:
+ 1671              		.section	.text.HAL_TIMEx_OCN_Start_IT,"ax",%progbits
+ 1672              		.align	1
+ 1673              		.global	HAL_TIMEx_OCN_Start_IT
+ 1674              		.syntax unified
+ 1675              		.thumb
+ 1676              		.thumb_func
+ 1677              		.fpu fpv5-d16
+ 1679              	HAL_TIMEx_OCN_Start_IT:
+ 1680              	.LVL107:
+ 1681              	.LFB153:
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1682              		.loc 1 710 1 is_stmt 1 view -0
+ 1683              		.cfi_startproc
+ 1684              		@ args = 0, pretend = 0, frame = 0
+ 1685              		@ frame_needed = 0, uses_anonymous_args = 0
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1686              		.loc 1 710 1 is_stmt 0 view .LVU480
+ 1687 0000 10B5     		push	{r4, lr}
+ 1688              	.LCFI16:
+ 1689              		.cfi_def_cfa_offset 8
+ 1690              		.cfi_offset 4, -8
+ 1691              		.cfi_offset 14, -4
+ 1692 0002 0446     		mov	r4, r0
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 1693              		.loc 1 711 3 is_stmt 1 view .LVU481
+ 1694              	.LVL108:
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1695              		.loc 1 712 3 view .LVU482
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1696              		.loc 1 715 3 view .LVU483
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1697              		.loc 1 718 3 view .LVU484
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1698              		.loc 1 718 46 is_stmt 0 view .LVU485
+ 1699 0004 0846     		mov	r0, r1
+ 1700              	.LVL109:
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1701              		.loc 1 718 46 view .LVU486
+ 1702 0006 99B9     		cbnz	r1, .L107
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1703              		.loc 1 718 7 discriminator 1 view .LVU487
+ 1704 0008 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ 1705 000c DBB2     		uxtb	r3, r3
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1706              		.loc 1 718 46 discriminator 1 view .LVU488
+ 1707 000e 013B     		subs	r3, r3, #1
+ 1708 0010 18BF     		it	ne
+ 1709 0012 0123     		movne	r3, #1
+ARM GAS  /tmp/cc7KL1Mv.s 			page 84
+
+
+ 1710              	.L108:
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1711              		.loc 1 718 6 discriminator 12 view .LVU489
+ 1712 0014 002B     		cmp	r3, #0
+ 1713 0016 40F08780 		bne	.L121
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1714              		.loc 1 724 3 is_stmt 1 view .LVU490
+ 1715 001a 10BB     		cbnz	r0, .L112
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1716              		.loc 1 724 3 is_stmt 0 discriminator 1 view .LVU491
+ 1717 001c 0223     		movs	r3, #2
+ 1718 001e 84F84430 		strb	r3, [r4, #68]
+ 1719              	.L113:
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1720              		.loc 1 726 3 is_stmt 1 view .LVU492
+ 1721 0022 0428     		cmp	r0, #4
+ 1722 0024 66D0     		beq	.L116
+ 1723 0026 0828     		cmp	r0, #8
+ 1724 0028 6AD0     		beq	.L117
+ 1725 002a 50B3     		cbz	r0, .L125
+ 1726 002c 0120     		movs	r0, #1
+ 1727              	.LVL110:
+ 1728              	.L111:
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1729              		.loc 1 783 1 is_stmt 0 view .LVU493
+ 1730 002e 10BD     		pop	{r4, pc}
+ 1731              	.LVL111:
+ 1732              	.L107:
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1733              		.loc 1 718 46 discriminator 2 view .LVU494
+ 1734 0030 0429     		cmp	r1, #4
+ 1735 0032 08D0     		beq	.L126
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1736              		.loc 1 718 46 discriminator 5 view .LVU495
+ 1737 0034 0829     		cmp	r1, #8
+ 1738 0036 0DD0     		beq	.L127
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1739              		.loc 1 718 7 discriminator 8 view .LVU496
+ 1740 0038 94F84730 		ldrb	r3, [r4, #71]	@ zero_extendqisi2
+ 1741 003c DBB2     		uxtb	r3, r3
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1742              		.loc 1 718 46 discriminator 8 view .LVU497
+ 1743 003e 013B     		subs	r3, r3, #1
+ 1744 0040 18BF     		it	ne
+ 1745 0042 0123     		movne	r3, #1
+ 1746 0044 E6E7     		b	.L108
+ 1747              	.L126:
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1748              		.loc 1 718 7 discriminator 4 view .LVU498
+ 1749 0046 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 1750 004a DBB2     		uxtb	r3, r3
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1751              		.loc 1 718 46 discriminator 4 view .LVU499
+ 1752 004c 013B     		subs	r3, r3, #1
+ 1753 004e 18BF     		it	ne
+ 1754 0050 0123     		movne	r3, #1
+ 1755 0052 DFE7     		b	.L108
+ARM GAS  /tmp/cc7KL1Mv.s 			page 85
+
+
+ 1756              	.L127:
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1757              		.loc 1 718 7 discriminator 7 view .LVU500
+ 1758 0054 94F84630 		ldrb	r3, [r4, #70]	@ zero_extendqisi2
+ 1759 0058 DBB2     		uxtb	r3, r3
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1760              		.loc 1 718 46 discriminator 7 view .LVU501
+ 1761 005a 013B     		subs	r3, r3, #1
+ 1762 005c 18BF     		it	ne
+ 1763 005e 0123     		movne	r3, #1
+ 1764 0060 D8E7     		b	.L108
+ 1765              	.L112:
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1766              		.loc 1 724 3 discriminator 2 view .LVU502
+ 1767 0062 0428     		cmp	r0, #4
+ 1768 0064 05D0     		beq	.L128
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1769              		.loc 1 724 3 discriminator 4 view .LVU503
+ 1770 0066 0828     		cmp	r0, #8
+ 1771 0068 07D0     		beq	.L129
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1772              		.loc 1 724 3 discriminator 7 view .LVU504
+ 1773 006a 0223     		movs	r3, #2
+ 1774 006c 84F84730 		strb	r3, [r4, #71]
+ 1775 0070 D7E7     		b	.L113
+ 1776              	.L128:
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1777              		.loc 1 724 3 discriminator 3 view .LVU505
+ 1778 0072 0223     		movs	r3, #2
+ 1779 0074 84F84530 		strb	r3, [r4, #69]
+ 1780 0078 D3E7     		b	.L113
+ 1781              	.L129:
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1782              		.loc 1 724 3 discriminator 6 view .LVU506
+ 1783 007a 0223     		movs	r3, #2
+ 1784 007c 84F84630 		strb	r3, [r4, #70]
+ 1785 0080 CFE7     		b	.L113
+ 1786              	.L125:
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 1787              		.loc 1 731 7 is_stmt 1 view .LVU507
+ 1788 0082 2268     		ldr	r2, [r4]
+ 1789 0084 D368     		ldr	r3, [r2, #12]
+ 1790 0086 43F00203 		orr	r3, r3, #2
+ 1791 008a D360     		str	r3, [r2, #12]
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1792              		.loc 1 732 7 view .LVU508
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1793              		.loc 1 755 3 view .LVU509
+ 1794              	.L118:
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1795              		.loc 1 758 5 view .LVU510
+ 1796 008c 2268     		ldr	r2, [r4]
+ 1797 008e D368     		ldr	r3, [r2, #12]
+ 1798 0090 43F08003 		orr	r3, r3, #128
+ 1799 0094 D360     		str	r3, [r2, #12]
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1800              		.loc 1 761 5 view .LVU511
+ARM GAS  /tmp/cc7KL1Mv.s 			page 86
+
+
+ 1801 0096 0422     		movs	r2, #4
+ 1802 0098 0146     		mov	r1, r0
+ 1803 009a 2068     		ldr	r0, [r4]
+ 1804              	.LVL112:
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1805              		.loc 1 761 5 is_stmt 0 view .LVU512
+ 1806 009c FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 1807              	.LVL113:
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1808              		.loc 1 764 5 is_stmt 1 view .LVU513
+ 1809 00a0 2268     		ldr	r2, [r4]
+ 1810 00a2 536C     		ldr	r3, [r2, #68]
+ 1811 00a4 43F40043 		orr	r3, r3, #32768
+ 1812 00a8 5364     		str	r3, [r2, #68]
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1813              		.loc 1 767 5 view .LVU514
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1814              		.loc 1 767 9 is_stmt 0 view .LVU515
+ 1815 00aa 2368     		ldr	r3, [r4]
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1816              		.loc 1 767 8 view .LVU516
+ 1817 00ac 204A     		ldr	r2, .L130
+ 1818 00ae B3F1804F 		cmp	r3, #1073741824
+ 1819 00b2 18BF     		it	ne
+ 1820 00b4 9342     		cmpne	r3, r2
+ 1821 00b6 29D0     		beq	.L119
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1822              		.loc 1 767 9 discriminator 1 view .LVU517
+ 1823 00b8 A2F57C42 		sub	r2, r2, #64512
+ 1824 00bc 9342     		cmp	r3, r2
+ 1825 00be 25D0     		beq	.L119
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1826              		.loc 1 767 9 discriminator 2 view .LVU518
+ 1827 00c0 02F58062 		add	r2, r2, #1024
+ 1828 00c4 9342     		cmp	r3, r2
+ 1829 00c6 21D0     		beq	.L119
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1830              		.loc 1 767 9 discriminator 3 view .LVU519
+ 1831 00c8 02F58062 		add	r2, r2, #1024
+ 1832 00cc 9342     		cmp	r3, r2
+ 1833 00ce 1DD0     		beq	.L119
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1834              		.loc 1 767 9 discriminator 4 view .LVU520
+ 1835 00d0 02F57842 		add	r2, r2, #63488
+ 1836 00d4 9342     		cmp	r3, r2
+ 1837 00d6 19D0     		beq	.L119
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1838              		.loc 1 767 9 discriminator 5 view .LVU521
+ 1839 00d8 02F57052 		add	r2, r2, #15360
+ 1840 00dc 9342     		cmp	r3, r2
+ 1841 00de 15D0     		beq	.L119
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1842              		.loc 1 767 9 discriminator 6 view .LVU522
+ 1843 00e0 A2F59432 		sub	r2, r2, #75776
+ 1844 00e4 9342     		cmp	r3, r2
+ 1845 00e6 11D0     		beq	.L119
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ARM GAS  /tmp/cc7KL1Mv.s 			page 87
+
+
+ 1846              		.loc 1 777 7 is_stmt 1 view .LVU523
+ 1847 00e8 1A68     		ldr	r2, [r3]
+ 1848 00ea 42F00102 		orr	r2, r2, #1
+ 1849 00ee 1A60     		str	r2, [r3]
+ 1850 00f0 0020     		movs	r0, #0
+ 1851 00f2 9CE7     		b	.L111
+ 1852              	.LVL114:
+ 1853              	.L116:
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 1854              		.loc 1 738 7 view .LVU524
+ 1855 00f4 2268     		ldr	r2, [r4]
+ 1856 00f6 D368     		ldr	r3, [r2, #12]
+ 1857 00f8 43F00403 		orr	r3, r3, #4
+ 1858 00fc D360     		str	r3, [r2, #12]
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1859              		.loc 1 739 7 view .LVU525
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1860              		.loc 1 755 3 view .LVU526
+ 1861 00fe C5E7     		b	.L118
+ 1862              	.L117:
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 1863              		.loc 1 745 7 view .LVU527
+ 1864 0100 2268     		ldr	r2, [r4]
+ 1865 0102 D368     		ldr	r3, [r2, #12]
+ 1866 0104 43F00803 		orr	r3, r3, #8
+ 1867 0108 D360     		str	r3, [r2, #12]
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1868              		.loc 1 746 7 view .LVU528
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1869              		.loc 1 755 3 view .LVU529
+ 1870 010a BFE7     		b	.L118
+ 1871              	.LVL115:
+ 1872              	.L119:
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1873              		.loc 1 769 7 view .LVU530
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1874              		.loc 1 769 31 is_stmt 0 view .LVU531
+ 1875 010c 9968     		ldr	r1, [r3, #8]
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 1876              		.loc 1 769 15 view .LVU532
+ 1877 010e 094A     		ldr	r2, .L130+4
+ 1878 0110 0A40     		ands	r2, r2, r1
+ 1879              	.LVL116:
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 1880              		.loc 1 770 7 is_stmt 1 view .LVU533
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 1881              		.loc 1 770 10 is_stmt 0 view .LVU534
+ 1882 0112 062A     		cmp	r2, #6
+ 1883 0114 18BF     		it	ne
+ 1884 0116 B2F5803F 		cmpne	r2, #65536
+ 1885 011a 07D0     		beq	.L123
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 1886              		.loc 1 772 9 is_stmt 1 view .LVU535
+ 1887 011c 1A68     		ldr	r2, [r3]
+ 1888              	.LVL117:
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 1889              		.loc 1 772 9 is_stmt 0 view .LVU536
+ARM GAS  /tmp/cc7KL1Mv.s 			page 88
+
+
+ 1890 011e 42F00102 		orr	r2, r2, #1
+ 1891 0122 1A60     		str	r2, [r3]
+ 1892 0124 0020     		movs	r0, #0
+ 1893 0126 82E7     		b	.L111
+ 1894              	.LVL118:
+ 1895              	.L121:
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 1896              		.loc 1 720 12 view .LVU537
+ 1897 0128 0120     		movs	r0, #1
+ 1898              	.LVL119:
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 1899              		.loc 1 720 12 view .LVU538
+ 1900 012a 80E7     		b	.L111
+ 1901              	.LVL120:
+ 1902              	.L123:
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 1903              		.loc 1 720 12 view .LVU539
+ 1904 012c 0020     		movs	r0, #0
+ 1905 012e 7EE7     		b	.L111
+ 1906              	.L131:
+ 1907              		.align	2
+ 1908              	.L130:
+ 1909 0130 00000140 		.word	1073807360
+ 1910 0134 07000100 		.word	65543
+ 1911              		.cfi_endproc
+ 1912              	.LFE153:
+ 1914              		.section	.text.HAL_TIMEx_OCN_Stop_IT,"ax",%progbits
+ 1915              		.align	1
+ 1916              		.global	HAL_TIMEx_OCN_Stop_IT
+ 1917              		.syntax unified
+ 1918              		.thumb
+ 1919              		.thumb_func
+ 1920              		.fpu fpv5-d16
+ 1922              	HAL_TIMEx_OCN_Stop_IT:
+ 1923              	.LVL121:
+ 1924              	.LFB154:
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1925              		.loc 1 797 1 is_stmt 1 view -0
+ 1926              		.cfi_startproc
+ 1927              		@ args = 0, pretend = 0, frame = 0
+ 1928              		@ frame_needed = 0, uses_anonymous_args = 0
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 1929              		.loc 1 797 1 is_stmt 0 view .LVU541
+ 1930 0000 38B5     		push	{r3, r4, r5, lr}
+ 1931              	.LCFI17:
+ 1932              		.cfi_def_cfa_offset 16
+ 1933              		.cfi_offset 3, -16
+ 1934              		.cfi_offset 4, -12
+ 1935              		.cfi_offset 5, -8
+ 1936              		.cfi_offset 14, -4
+ 1937 0002 0546     		mov	r5, r0
+ 1938 0004 0C46     		mov	r4, r1
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpccer;
+ 1939              		.loc 1 798 3 is_stmt 1 view .LVU542
+ 1940              	.LVL122:
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1941              		.loc 1 799 3 view .LVU543
+ARM GAS  /tmp/cc7KL1Mv.s 			page 89
+
+
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1942              		.loc 1 802 3 view .LVU544
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1943              		.loc 1 804 3 view .LVU545
+ 1944 0006 0429     		cmp	r1, #4
+ 1945 0008 3CD0     		beq	.L133
+ 1946 000a 0829     		cmp	r1, #8
+ 1947 000c 40D0     		beq	.L134
+ 1948 000e 09B1     		cbz	r1, .L145
+ 1949 0010 0120     		movs	r0, #1
+ 1950              	.LVL123:
+ 1951              	.L135:
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 1952              		.loc 1 855 3 view .LVU546
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1953              		.loc 1 856 1 is_stmt 0 view .LVU547
+ 1954 0012 38BD     		pop	{r3, r4, r5, pc}
+ 1955              	.LVL124:
+ 1956              	.L145:
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 1957              		.loc 1 809 7 is_stmt 1 view .LVU548
+ 1958 0014 0268     		ldr	r2, [r0]
+ 1959 0016 D368     		ldr	r3, [r2, #12]
+ 1960 0018 23F00203 		bic	r3, r3, #2
+ 1961 001c D360     		str	r3, [r2, #12]
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1962              		.loc 1 810 7 view .LVU549
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 1963              		.loc 1 832 3 view .LVU550
+ 1964              	.L136:
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1965              		.loc 1 835 5 view .LVU551
+ 1966 001e 0022     		movs	r2, #0
+ 1967 0020 2146     		mov	r1, r4
+ 1968              	.LVL125:
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1969              		.loc 1 835 5 is_stmt 0 view .LVU552
+ 1970 0022 2868     		ldr	r0, [r5]
+ 1971              	.LVL126:
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1972              		.loc 1 835 5 view .LVU553
+ 1973 0024 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 1974              	.LVL127:
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+ 1975              		.loc 1 838 5 is_stmt 1 view .LVU554
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+ 1976              		.loc 1 838 19 is_stmt 0 view .LVU555
+ 1977 0028 2B68     		ldr	r3, [r5]
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+ 1978              		.loc 1 838 13 view .LVU556
+ 1979 002a 196A     		ldr	r1, [r3, #32]
+ 1980              	.LVL128:
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1981              		.loc 1 839 5 is_stmt 1 view .LVU557
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 1982              		.loc 1 839 8 is_stmt 0 view .LVU558
+ 1983 002c 40F24442 		movw	r2, #1092
+ARM GAS  /tmp/cc7KL1Mv.s 			page 90
+
+
+ 1984 0030 1142     		tst	r1, r2
+ 1985 0032 03D1     		bne	.L137
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 1986              		.loc 1 841 7 is_stmt 1 view .LVU559
+ 1987 0034 DA68     		ldr	r2, [r3, #12]
+ 1988 0036 22F08002 		bic	r2, r2, #128
+ 1989 003a DA60     		str	r2, [r3, #12]
+ 1990              	.L137:
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1991              		.loc 1 845 5 view .LVU560
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1992              		.loc 1 845 5 view .LVU561
+ 1993 003c 2B68     		ldr	r3, [r5]
+ 1994 003e 196A     		ldr	r1, [r3, #32]
+ 1995              	.LVL129:
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 1996              		.loc 1 845 5 is_stmt 0 view .LVU562
+ 1997 0040 41F21112 		movw	r2, #4369
+ 1998 0044 1142     		tst	r1, r2
+ 1999 0046 08D1     		bne	.L138
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2000              		.loc 1 845 5 is_stmt 1 discriminator 1 view .LVU563
+ 2001 0048 196A     		ldr	r1, [r3, #32]
+ 2002 004a 40F24442 		movw	r2, #1092
+ 2003 004e 1142     		tst	r1, r2
+ 2004 0050 03D1     		bne	.L138
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2005              		.loc 1 845 5 discriminator 3 view .LVU564
+ 2006 0052 5A6C     		ldr	r2, [r3, #68]
+ 2007 0054 22F40042 		bic	r2, r2, #32768
+ 2008 0058 5A64     		str	r2, [r3, #68]
+ 2009              	.L138:
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2010              		.loc 1 845 5 discriminator 5 view .LVU565
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2011              		.loc 1 848 5 discriminator 5 view .LVU566
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2012              		.loc 1 848 5 discriminator 5 view .LVU567
+ 2013 005a 2B68     		ldr	r3, [r5]
+ 2014 005c 196A     		ldr	r1, [r3, #32]
+ 2015 005e 41F21112 		movw	r2, #4369
+ 2016 0062 1142     		tst	r1, r2
+ 2017 0064 08D1     		bne	.L139
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2018              		.loc 1 848 5 discriminator 1 view .LVU568
+ 2019 0066 196A     		ldr	r1, [r3, #32]
+ 2020 0068 40F24442 		movw	r2, #1092
+ 2021 006c 1142     		tst	r1, r2
+ 2022 006e 03D1     		bne	.L139
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2023              		.loc 1 848 5 discriminator 3 view .LVU569
+ 2024 0070 1A68     		ldr	r2, [r3]
+ 2025 0072 22F00102 		bic	r2, r2, #1
+ 2026 0076 1A60     		str	r2, [r3]
+ 2027              	.L139:
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2028              		.loc 1 848 5 discriminator 5 view .LVU570
+ARM GAS  /tmp/cc7KL1Mv.s 			page 91
+
+
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2029              		.loc 1 851 5 discriminator 5 view .LVU571
+ 2030 0078 84B9     		cbnz	r4, .L140
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2031              		.loc 1 851 5 is_stmt 0 discriminator 1 view .LVU572
+ 2032 007a 0123     		movs	r3, #1
+ 2033 007c 85F84430 		strb	r3, [r5, #68]
+ 2034 0080 0020     		movs	r0, #0
+ 2035 0082 C6E7     		b	.L135
+ 2036              	.LVL130:
+ 2037              	.L133:
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2038              		.loc 1 816 7 is_stmt 1 view .LVU573
+ 2039 0084 0268     		ldr	r2, [r0]
+ 2040 0086 D368     		ldr	r3, [r2, #12]
+ 2041 0088 23F00403 		bic	r3, r3, #4
+ 2042 008c D360     		str	r3, [r2, #12]
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2043              		.loc 1 817 7 view .LVU574
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2044              		.loc 1 832 3 view .LVU575
+ 2045 008e C6E7     		b	.L136
+ 2046              	.L134:
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2047              		.loc 1 823 7 view .LVU576
+ 2048 0090 0268     		ldr	r2, [r0]
+ 2049 0092 D368     		ldr	r3, [r2, #12]
+ 2050 0094 23F00803 		bic	r3, r3, #8
+ 2051 0098 D360     		str	r3, [r2, #12]
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2052              		.loc 1 824 7 view .LVU577
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2053              		.loc 1 832 3 view .LVU578
+ 2054 009a C0E7     		b	.L136
+ 2055              	.LVL131:
+ 2056              	.L140:
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2057              		.loc 1 851 5 is_stmt 0 discriminator 2 view .LVU579
+ 2058 009c 042C     		cmp	r4, #4
+ 2059 009e 06D0     		beq	.L146
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2060              		.loc 1 851 5 discriminator 4 view .LVU580
+ 2061 00a0 082C     		cmp	r4, #8
+ 2062 00a2 09D0     		beq	.L147
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2063              		.loc 1 851 5 discriminator 7 view .LVU581
+ 2064 00a4 0123     		movs	r3, #1
+ 2065 00a6 85F84730 		strb	r3, [r5, #71]
+ 2066 00aa 0020     		movs	r0, #0
+ 2067 00ac B1E7     		b	.L135
+ 2068              	.L146:
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2069              		.loc 1 851 5 discriminator 3 view .LVU582
+ 2070 00ae 0123     		movs	r3, #1
+ 2071 00b0 85F84530 		strb	r3, [r5, #69]
+ 2072 00b4 0020     		movs	r0, #0
+ 2073 00b6 ACE7     		b	.L135
+ARM GAS  /tmp/cc7KL1Mv.s 			page 92
+
+
+ 2074              	.L147:
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2075              		.loc 1 851 5 discriminator 6 view .LVU583
+ 2076 00b8 0123     		movs	r3, #1
+ 2077 00ba 85F84630 		strb	r3, [r5, #70]
+ 2078 00be 0020     		movs	r0, #0
+ 2079 00c0 A7E7     		b	.L135
+ 2080              		.cfi_endproc
+ 2081              	.LFE154:
+ 2083              		.section	.text.HAL_TIMEx_OCN_Start_DMA,"ax",%progbits
+ 2084              		.align	1
+ 2085              		.global	HAL_TIMEx_OCN_Start_DMA
+ 2086              		.syntax unified
+ 2087              		.thumb
+ 2088              		.thumb_func
+ 2089              		.fpu fpv5-d16
+ 2091              	HAL_TIMEx_OCN_Start_DMA:
+ 2092              	.LVL132:
+ 2093              	.LFB155:
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2094              		.loc 1 873 1 is_stmt 1 view -0
+ 2095              		.cfi_startproc
+ 2096              		@ args = 0, pretend = 0, frame = 0
+ 2097              		@ frame_needed = 0, uses_anonymous_args = 0
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2098              		.loc 1 873 1 is_stmt 0 view .LVU585
+ 2099 0000 38B5     		push	{r3, r4, r5, lr}
+ 2100              	.LCFI18:
+ 2101              		.cfi_def_cfa_offset 16
+ 2102              		.cfi_offset 3, -16
+ 2103              		.cfi_offset 4, -12
+ 2104              		.cfi_offset 5, -8
+ 2105              		.cfi_offset 14, -4
+ 2106 0002 0446     		mov	r4, r0
+ 2107 0004 9446     		mov	ip, r2
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 2108              		.loc 1 874 3 is_stmt 1 view .LVU586
+ 2109              	.LVL133:
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2110              		.loc 1 875 3 view .LVU587
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2111              		.loc 1 878 3 view .LVU588
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2112              		.loc 1 881 3 view .LVU589
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2113              		.loc 1 881 46 is_stmt 0 view .LVU590
+ 2114 0006 0D46     		mov	r5, r1
+ 2115 0008 51BB     		cbnz	r1, .L149
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2116              		.loc 1 881 7 discriminator 1 view .LVU591
+ 2117 000a 90F84400 		ldrb	r0, [r0, #68]	@ zero_extendqisi2
+ 2118              	.LVL134:
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2119              		.loc 1 881 7 discriminator 1 view .LVU592
+ 2120 000e C0B2     		uxtb	r0, r0
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2121              		.loc 1 881 46 discriminator 1 view .LVU593
+ARM GAS  /tmp/cc7KL1Mv.s 			page 93
+
+
+ 2122 0010 0228     		cmp	r0, #2
+ 2123 0012 14BF     		ite	ne
+ 2124 0014 0020     		movne	r0, #0
+ 2125 0016 0120     		moveq	r0, #1
+ 2126              	.L150:
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2127              		.loc 1 881 6 discriminator 12 view .LVU594
+ 2128 0018 0028     		cmp	r0, #0
+ 2129 001a 40F0E980 		bne	.L167
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2130              		.loc 1 885 8 is_stmt 1 view .LVU595
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2131              		.loc 1 885 51 is_stmt 0 view .LVU596
+ 2132 001e 002D     		cmp	r5, #0
+ 2133 0020 3AD1     		bne	.L154
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2134              		.loc 1 885 12 discriminator 1 view .LVU597
+ 2135 0022 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 2136              	.LVL135:
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2137              		.loc 1 885 12 discriminator 1 view .LVU598
+ 2138 0026 D2B2     		uxtb	r2, r2
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2139              		.loc 1 885 51 discriminator 1 view .LVU599
+ 2140 0028 012A     		cmp	r2, #1
+ 2141 002a 14BF     		ite	ne
+ 2142 002c 0022     		movne	r2, #0
+ 2143 002e 0122     		moveq	r2, #1
+ 2144              	.L155:
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2145              		.loc 1 885 11 discriminator 12 view .LVU600
+ 2146 0030 002A     		cmp	r2, #0
+ 2147 0032 00F0DF80 		beq	.L168
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2148              		.loc 1 887 5 is_stmt 1 view .LVU601
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2149              		.loc 1 887 8 is_stmt 0 view .LVU602
+ 2150 0036 002B     		cmp	r3, #0
+ 2151 0038 18BF     		it	ne
+ 2152 003a BCF1000F 		cmpne	ip, #0
+ 2153 003e 00F0DB80 		beq	.L169
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2154              		.loc 1 893 7 is_stmt 1 view .LVU603
+ 2155 0042 002D     		cmp	r5, #0
+ 2156 0044 44D1     		bne	.L158
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2157              		.loc 1 893 7 is_stmt 0 discriminator 1 view .LVU604
+ 2158 0046 0222     		movs	r2, #2
+ 2159 0048 84F84420 		strb	r2, [r4, #68]
+ 2160              	.L159:
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2161              		.loc 1 901 3 is_stmt 1 view .LVU605
+ 2162 004c 042D     		cmp	r5, #4
+ 2163 004e 00F09480 		beq	.L162
+ 2164 0052 082D     		cmp	r5, #8
+ 2165 0054 00F0A880 		beq	.L163
+ 2166 0058 002D     		cmp	r5, #0
+ARM GAS  /tmp/cc7KL1Mv.s 			page 94
+
+
+ 2167 005a 49D0     		beq	.L176
+ 2168 005c 0120     		movs	r0, #1
+ 2169 005e CAE0     		b	.L153
+ 2170              	.LVL136:
+ 2171              	.L149:
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2172              		.loc 1 881 46 is_stmt 0 discriminator 2 view .LVU606
+ 2173 0060 0429     		cmp	r1, #4
+ 2174 0062 09D0     		beq	.L177
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2175              		.loc 1 881 46 discriminator 5 view .LVU607
+ 2176 0064 0829     		cmp	r1, #8
+ 2177 0066 0FD0     		beq	.L178
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2178              		.loc 1 881 7 discriminator 8 view .LVU608
+ 2179 0068 90F84700 		ldrb	r0, [r0, #71]	@ zero_extendqisi2
+ 2180              	.LVL137:
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2181              		.loc 1 881 7 discriminator 8 view .LVU609
+ 2182 006c C0B2     		uxtb	r0, r0
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2183              		.loc 1 881 46 discriminator 8 view .LVU610
+ 2184 006e 0228     		cmp	r0, #2
+ 2185 0070 14BF     		ite	ne
+ 2186 0072 0020     		movne	r0, #0
+ 2187 0074 0120     		moveq	r0, #1
+ 2188 0076 CFE7     		b	.L150
+ 2189              	.LVL138:
+ 2190              	.L177:
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2191              		.loc 1 881 7 discriminator 4 view .LVU611
+ 2192 0078 90F84500 		ldrb	r0, [r0, #69]	@ zero_extendqisi2
+ 2193              	.LVL139:
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2194              		.loc 1 881 7 discriminator 4 view .LVU612
+ 2195 007c C0B2     		uxtb	r0, r0
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2196              		.loc 1 881 46 discriminator 4 view .LVU613
+ 2197 007e 0228     		cmp	r0, #2
+ 2198 0080 14BF     		ite	ne
+ 2199 0082 0020     		movne	r0, #0
+ 2200 0084 0120     		moveq	r0, #1
+ 2201 0086 C7E7     		b	.L150
+ 2202              	.LVL140:
+ 2203              	.L178:
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2204              		.loc 1 881 7 discriminator 7 view .LVU614
+ 2205 0088 90F84600 		ldrb	r0, [r0, #70]	@ zero_extendqisi2
+ 2206              	.LVL141:
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2207              		.loc 1 881 7 discriminator 7 view .LVU615
+ 2208 008c C0B2     		uxtb	r0, r0
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2209              		.loc 1 881 46 discriminator 7 view .LVU616
+ 2210 008e 0228     		cmp	r0, #2
+ 2211 0090 14BF     		ite	ne
+ 2212 0092 0020     		movne	r0, #0
+ARM GAS  /tmp/cc7KL1Mv.s 			page 95
+
+
+ 2213 0094 0120     		moveq	r0, #1
+ 2214 0096 BFE7     		b	.L150
+ 2215              	.L154:
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2216              		.loc 1 885 51 discriminator 2 view .LVU617
+ 2217 0098 042D     		cmp	r5, #4
+ 2218 009a 09D0     		beq	.L179
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2219              		.loc 1 885 51 discriminator 5 view .LVU618
+ 2220 009c 082D     		cmp	r5, #8
+ 2221 009e 0FD0     		beq	.L180
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2222              		.loc 1 885 12 discriminator 8 view .LVU619
+ 2223 00a0 94F84720 		ldrb	r2, [r4, #71]	@ zero_extendqisi2
+ 2224              	.LVL142:
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2225              		.loc 1 885 12 discriminator 8 view .LVU620
+ 2226 00a4 D2B2     		uxtb	r2, r2
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2227              		.loc 1 885 51 discriminator 8 view .LVU621
+ 2228 00a6 012A     		cmp	r2, #1
+ 2229 00a8 14BF     		ite	ne
+ 2230 00aa 0022     		movne	r2, #0
+ 2231 00ac 0122     		moveq	r2, #1
+ 2232 00ae BFE7     		b	.L155
+ 2233              	.LVL143:
+ 2234              	.L179:
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2235              		.loc 1 885 12 discriminator 4 view .LVU622
+ 2236 00b0 94F84520 		ldrb	r2, [r4, #69]	@ zero_extendqisi2
+ 2237              	.LVL144:
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2238              		.loc 1 885 12 discriminator 4 view .LVU623
+ 2239 00b4 D2B2     		uxtb	r2, r2
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2240              		.loc 1 885 51 discriminator 4 view .LVU624
+ 2241 00b6 012A     		cmp	r2, #1
+ 2242 00b8 14BF     		ite	ne
+ 2243 00ba 0022     		movne	r2, #0
+ 2244 00bc 0122     		moveq	r2, #1
+ 2245 00be B7E7     		b	.L155
+ 2246              	.LVL145:
+ 2247              	.L180:
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2248              		.loc 1 885 12 discriminator 7 view .LVU625
+ 2249 00c0 94F84620 		ldrb	r2, [r4, #70]	@ zero_extendqisi2
+ 2250              	.LVL146:
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2251              		.loc 1 885 12 discriminator 7 view .LVU626
+ 2252 00c4 D2B2     		uxtb	r2, r2
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2253              		.loc 1 885 51 discriminator 7 view .LVU627
+ 2254 00c6 012A     		cmp	r2, #1
+ 2255 00c8 14BF     		ite	ne
+ 2256 00ca 0022     		movne	r2, #0
+ 2257 00cc 0122     		moveq	r2, #1
+ 2258 00ce AFE7     		b	.L155
+ARM GAS  /tmp/cc7KL1Mv.s 			page 96
+
+
+ 2259              	.L158:
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2260              		.loc 1 893 7 discriminator 2 view .LVU628
+ 2261 00d0 042D     		cmp	r5, #4
+ 2262 00d2 05D0     		beq	.L181
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2263              		.loc 1 893 7 discriminator 4 view .LVU629
+ 2264 00d4 082D     		cmp	r5, #8
+ 2265 00d6 07D0     		beq	.L182
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2266              		.loc 1 893 7 discriminator 7 view .LVU630
+ 2267 00d8 0222     		movs	r2, #2
+ 2268 00da 84F84720 		strb	r2, [r4, #71]
+ 2269 00de B5E7     		b	.L159
+ 2270              	.L181:
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2271              		.loc 1 893 7 discriminator 3 view .LVU631
+ 2272 00e0 0222     		movs	r2, #2
+ 2273 00e2 84F84520 		strb	r2, [r4, #69]
+ 2274 00e6 B1E7     		b	.L159
+ 2275              	.L182:
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2276              		.loc 1 893 7 discriminator 6 view .LVU632
+ 2277 00e8 0222     		movs	r2, #2
+ 2278 00ea 84F84620 		strb	r2, [r4, #70]
+ 2279 00ee ADE7     		b	.L159
+ 2280              	.L176:
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2281              		.loc 1 906 7 is_stmt 1 view .LVU633
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2282              		.loc 1 906 17 is_stmt 0 view .LVU634
+ 2283 00f0 626A     		ldr	r2, [r4, #36]
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2284              		.loc 1 906 52 view .LVU635
+ 2285 00f2 4649     		ldr	r1, .L183
+ 2286              	.LVL147:
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2287              		.loc 1 906 52 view .LVU636
+ 2288 00f4 D163     		str	r1, [r2, #60]
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2289              		.loc 1 907 7 is_stmt 1 view .LVU637
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2290              		.loc 1 907 17 is_stmt 0 view .LVU638
+ 2291 00f6 626A     		ldr	r2, [r4, #36]
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2292              		.loc 1 907 56 view .LVU639
+ 2293 00f8 4549     		ldr	r1, .L183+4
+ 2294 00fa 1164     		str	r1, [r2, #64]
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2295              		.loc 1 910 7 is_stmt 1 view .LVU640
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2296              		.loc 1 910 17 is_stmt 0 view .LVU641
+ 2297 00fc 626A     		ldr	r2, [r4, #36]
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2298              		.loc 1 910 53 view .LVU642
+ 2299 00fe 4549     		ldr	r1, .L183+8
+ 2300 0100 D164     		str	r1, [r2, #76]
+ARM GAS  /tmp/cc7KL1Mv.s 			page 97
+
+
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2301              		.loc 1 913 7 is_stmt 1 view .LVU643
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2302              		.loc 1 913 88 is_stmt 0 view .LVU644
+ 2303 0102 2268     		ldr	r2, [r4]
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2304              		.loc 1 913 11 view .LVU645
+ 2305 0104 3432     		adds	r2, r2, #52
+ 2306 0106 6146     		mov	r1, ip
+ 2307 0108 606A     		ldr	r0, [r4, #36]
+ 2308 010a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2309              	.LVL148:
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2310              		.loc 1 913 10 view .LVU646
+ 2311 010e 0028     		cmp	r0, #0
+ 2312 0110 74D1     		bne	.L171
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2313              		.loc 1 920 7 is_stmt 1 view .LVU647
+ 2314 0112 2268     		ldr	r2, [r4]
+ 2315 0114 D368     		ldr	r3, [r2, #12]
+ 2316 0116 43F40073 		orr	r3, r3, #512
+ 2317 011a D360     		str	r3, [r2, #12]
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2318              		.loc 1 921 7 view .LVU648
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2319              		.loc 1 971 3 view .LVU649
+ 2320              	.L164:
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2321              		.loc 1 974 5 view .LVU650
+ 2322 011c 0422     		movs	r2, #4
+ 2323 011e 2946     		mov	r1, r5
+ 2324 0120 2068     		ldr	r0, [r4]
+ 2325 0122 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 2326              	.LVL149:
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2327              		.loc 1 977 5 view .LVU651
+ 2328 0126 2268     		ldr	r2, [r4]
+ 2329 0128 536C     		ldr	r3, [r2, #68]
+ 2330 012a 43F40043 		orr	r3, r3, #32768
+ 2331 012e 5364     		str	r3, [r2, #68]
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2332              		.loc 1 980 5 view .LVU652
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2333              		.loc 1 980 9 is_stmt 0 view .LVU653
+ 2334 0130 2368     		ldr	r3, [r4]
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2335              		.loc 1 980 8 view .LVU654
+ 2336 0132 394A     		ldr	r2, .L183+12
+ 2337 0134 B3F1804F 		cmp	r3, #1073741824
+ 2338 0138 18BF     		it	ne
+ 2339 013a 9342     		cmpne	r3, r2
+ 2340 013c 4AD0     		beq	.L165
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2341              		.loc 1 980 9 discriminator 1 view .LVU655
+ 2342 013e A2F57C42 		sub	r2, r2, #64512
+ 2343 0142 9342     		cmp	r3, r2
+ 2344 0144 46D0     		beq	.L165
+ARM GAS  /tmp/cc7KL1Mv.s 			page 98
+
+
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2345              		.loc 1 980 9 discriminator 2 view .LVU656
+ 2346 0146 02F58062 		add	r2, r2, #1024
+ 2347 014a 9342     		cmp	r3, r2
+ 2348 014c 42D0     		beq	.L165
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2349              		.loc 1 980 9 discriminator 3 view .LVU657
+ 2350 014e 02F58062 		add	r2, r2, #1024
+ 2351 0152 9342     		cmp	r3, r2
+ 2352 0154 3ED0     		beq	.L165
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2353              		.loc 1 980 9 discriminator 4 view .LVU658
+ 2354 0156 02F57842 		add	r2, r2, #63488
+ 2355 015a 9342     		cmp	r3, r2
+ 2356 015c 3AD0     		beq	.L165
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2357              		.loc 1 980 9 discriminator 5 view .LVU659
+ 2358 015e 02F57052 		add	r2, r2, #15360
+ 2359 0162 9342     		cmp	r3, r2
+ 2360 0164 36D0     		beq	.L165
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2361              		.loc 1 980 9 discriminator 6 view .LVU660
+ 2362 0166 A2F59432 		sub	r2, r2, #75776
+ 2363 016a 9342     		cmp	r3, r2
+ 2364 016c 32D0     		beq	.L165
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2365              		.loc 1 990 7 is_stmt 1 view .LVU661
+ 2366 016e 1A68     		ldr	r2, [r3]
+ 2367 0170 42F00102 		orr	r2, r2, #1
+ 2368 0174 1A60     		str	r2, [r3]
+ 2369 0176 0020     		movs	r0, #0
+ 2370 0178 3DE0     		b	.L153
+ 2371              	.LVL150:
+ 2372              	.L162:
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2373              		.loc 1 927 7 view .LVU662
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2374              		.loc 1 927 17 is_stmt 0 view .LVU663
+ 2375 017a A26A     		ldr	r2, [r4, #40]
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2376              		.loc 1 927 52 view .LVU664
+ 2377 017c 2349     		ldr	r1, .L183
+ 2378              	.LVL151:
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2379              		.loc 1 927 52 view .LVU665
+ 2380 017e D163     		str	r1, [r2, #60]
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2381              		.loc 1 928 7 is_stmt 1 view .LVU666
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2382              		.loc 1 928 17 is_stmt 0 view .LVU667
+ 2383 0180 A26A     		ldr	r2, [r4, #40]
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2384              		.loc 1 928 56 view .LVU668
+ 2385 0182 2349     		ldr	r1, .L183+4
+ 2386 0184 1164     		str	r1, [r2, #64]
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2387              		.loc 1 931 7 is_stmt 1 view .LVU669
+ARM GAS  /tmp/cc7KL1Mv.s 			page 99
+
+
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2388              		.loc 1 931 17 is_stmt 0 view .LVU670
+ 2389 0186 A26A     		ldr	r2, [r4, #40]
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2390              		.loc 1 931 53 view .LVU671
+ 2391 0188 2249     		ldr	r1, .L183+8
+ 2392 018a D164     		str	r1, [r2, #76]
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2393              		.loc 1 934 7 is_stmt 1 view .LVU672
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2394              		.loc 1 934 88 is_stmt 0 view .LVU673
+ 2395 018c 2268     		ldr	r2, [r4]
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2396              		.loc 1 934 11 view .LVU674
+ 2397 018e 3832     		adds	r2, r2, #56
+ 2398 0190 6146     		mov	r1, ip
+ 2399 0192 A06A     		ldr	r0, [r4, #40]
+ 2400 0194 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2401              	.LVL152:
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2402              		.loc 1 934 10 view .LVU675
+ 2403 0198 0028     		cmp	r0, #0
+ 2404 019a 31D1     		bne	.L172
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2405              		.loc 1 941 7 is_stmt 1 view .LVU676
+ 2406 019c 2268     		ldr	r2, [r4]
+ 2407 019e D368     		ldr	r3, [r2, #12]
+ 2408 01a0 43F48063 		orr	r3, r3, #1024
+ 2409 01a4 D360     		str	r3, [r2, #12]
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2410              		.loc 1 942 7 view .LVU677
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2411              		.loc 1 971 3 view .LVU678
+ 2412 01a6 B9E7     		b	.L164
+ 2413              	.LVL153:
+ 2414              	.L163:
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2415              		.loc 1 948 7 view .LVU679
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2416              		.loc 1 948 17 is_stmt 0 view .LVU680
+ 2417 01a8 E26A     		ldr	r2, [r4, #44]
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2418              		.loc 1 948 52 view .LVU681
+ 2419 01aa 1849     		ldr	r1, .L183
+ 2420              	.LVL154:
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 2421              		.loc 1 948 52 view .LVU682
+ 2422 01ac D163     		str	r1, [r2, #60]
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2423              		.loc 1 949 7 is_stmt 1 view .LVU683
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2424              		.loc 1 949 17 is_stmt 0 view .LVU684
+ 2425 01ae E26A     		ldr	r2, [r4, #44]
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2426              		.loc 1 949 56 view .LVU685
+ 2427 01b0 1749     		ldr	r1, .L183+4
+ 2428 01b2 1164     		str	r1, [r2, #64]
+ARM GAS  /tmp/cc7KL1Mv.s 			page 100
+
+
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2429              		.loc 1 952 7 is_stmt 1 view .LVU686
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2430              		.loc 1 952 17 is_stmt 0 view .LVU687
+ 2431 01b4 E26A     		ldr	r2, [r4, #44]
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2432              		.loc 1 952 53 view .LVU688
+ 2433 01b6 1749     		ldr	r1, .L183+8
+ 2434 01b8 D164     		str	r1, [r2, #76]
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2435              		.loc 1 955 7 is_stmt 1 view .LVU689
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2436              		.loc 1 955 88 is_stmt 0 view .LVU690
+ 2437 01ba 2268     		ldr	r2, [r4]
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2438              		.loc 1 955 11 view .LVU691
+ 2439 01bc 3C32     		adds	r2, r2, #60
+ 2440 01be 6146     		mov	r1, ip
+ 2441 01c0 E06A     		ldr	r0, [r4, #44]
+ 2442 01c2 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 2443              	.LVL155:
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 2444              		.loc 1 955 10 view .LVU692
+ 2445 01c6 E8B9     		cbnz	r0, .L173
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2446              		.loc 1 962 7 is_stmt 1 view .LVU693
+ 2447 01c8 2268     		ldr	r2, [r4]
+ 2448 01ca D368     		ldr	r3, [r2, #12]
+ 2449 01cc 43F40063 		orr	r3, r3, #2048
+ 2450 01d0 D360     		str	r3, [r2, #12]
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2451              		.loc 1 963 7 view .LVU694
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2452              		.loc 1 971 3 view .LVU695
+ 2453 01d2 A3E7     		b	.L164
+ 2454              	.L165:
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 2455              		.loc 1 982 7 view .LVU696
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 2456              		.loc 1 982 31 is_stmt 0 view .LVU697
+ 2457 01d4 9968     		ldr	r1, [r3, #8]
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 2458              		.loc 1 982 15 view .LVU698
+ 2459 01d6 114A     		ldr	r2, .L183+16
+ 2460 01d8 0A40     		ands	r2, r2, r1
+ 2461              	.LVL156:
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 2462              		.loc 1 983 7 is_stmt 1 view .LVU699
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 2463              		.loc 1 983 10 is_stmt 0 view .LVU700
+ 2464 01da 062A     		cmp	r2, #6
+ 2465 01dc 18BF     		it	ne
+ 2466 01de B2F5803F 		cmpne	r2, #65536
+ 2467 01e2 11D0     		beq	.L174
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 2468              		.loc 1 985 9 is_stmt 1 view .LVU701
+ 2469 01e4 1A68     		ldr	r2, [r3]
+ARM GAS  /tmp/cc7KL1Mv.s 			page 101
+
+
+ 2470              	.LVL157:
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 2471              		.loc 1 985 9 is_stmt 0 view .LVU702
+ 2472 01e6 42F00102 		orr	r2, r2, #1
+ 2473 01ea 1A60     		str	r2, [r3]
+ 2474 01ec 0020     		movs	r0, #0
+ 2475 01ee 02E0     		b	.L153
+ 2476              	.LVL158:
+ 2477              	.L167:
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2478              		.loc 1 883 12 view .LVU703
+ 2479 01f0 0220     		movs	r0, #2
+ 2480 01f2 00E0     		b	.L153
+ 2481              	.LVL159:
+ 2482              	.L168:
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2483              		.loc 1 898 12 view .LVU704
+ 2484 01f4 0120     		movs	r0, #1
+ 2485              	.LVL160:
+ 2486              	.L153:
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2487              		.loc 1 996 1 view .LVU705
+ 2488 01f6 38BD     		pop	{r3, r4, r5, pc}
+ 2489              	.LVL161:
+ 2490              	.L169:
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2491              		.loc 1 889 14 view .LVU706
+ 2492 01f8 0120     		movs	r0, #1
+ 2493 01fa FCE7     		b	.L153
+ 2494              	.LVL162:
+ 2495              	.L171:
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 2496              		.loc 1 917 16 view .LVU707
+ 2497 01fc 0120     		movs	r0, #1
+ 2498 01fe FAE7     		b	.L153
+ 2499              	.L172:
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 2500              		.loc 1 938 16 view .LVU708
+ 2501 0200 0120     		movs	r0, #1
+ 2502 0202 F8E7     		b	.L153
+ 2503              	.L173:
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 2504              		.loc 1 959 16 view .LVU709
+ 2505 0204 0120     		movs	r0, #1
+ 2506 0206 F6E7     		b	.L153
+ 2507              	.LVL163:
+ 2508              	.L174:
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 2509              		.loc 1 959 16 view .LVU710
+ 2510 0208 0020     		movs	r0, #0
+ 2511 020a F4E7     		b	.L153
+ 2512              	.L184:
+ 2513              		.align	2
+ 2514              	.L183:
+ 2515 020c 00000000 		.word	TIM_DMADelayPulseNCplt
+ 2516 0210 00000000 		.word	TIM_DMADelayPulseHalfCplt
+ 2517 0214 00000000 		.word	TIM_DMAErrorCCxN
+ARM GAS  /tmp/cc7KL1Mv.s 			page 102
+
+
+ 2518 0218 00000140 		.word	1073807360
+ 2519 021c 07000100 		.word	65543
+ 2520              		.cfi_endproc
+ 2521              	.LFE155:
+ 2523              		.section	.text.HAL_TIMEx_OCN_Stop_DMA,"ax",%progbits
+ 2524              		.align	1
+ 2525              		.global	HAL_TIMEx_OCN_Stop_DMA
+ 2526              		.syntax unified
+ 2527              		.thumb
+ 2528              		.thumb_func
+ 2529              		.fpu fpv5-d16
+ 2531              	HAL_TIMEx_OCN_Stop_DMA:
+ 2532              	.LVL164:
+ 2533              	.LFB156:
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2534              		.loc 1 1010 1 is_stmt 1 view -0
+ 2535              		.cfi_startproc
+ 2536              		@ args = 0, pretend = 0, frame = 0
+ 2537              		@ frame_needed = 0, uses_anonymous_args = 0
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 2538              		.loc 1 1010 1 is_stmt 0 view .LVU712
+ 2539 0000 38B5     		push	{r3, r4, r5, lr}
+ 2540              	.LCFI19:
+ 2541              		.cfi_def_cfa_offset 16
+ 2542              		.cfi_offset 3, -16
+ 2543              		.cfi_offset 4, -12
+ 2544              		.cfi_offset 5, -8
+ 2545              		.cfi_offset 14, -4
+ 2546 0002 0546     		mov	r5, r0
+ 2547 0004 0C46     		mov	r4, r1
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2548              		.loc 1 1011 3 is_stmt 1 view .LVU713
+ 2549              	.LVL165:
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2550              		.loc 1 1014 3 view .LVU714
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2551              		.loc 1 1016 3 view .LVU715
+ 2552 0006 0429     		cmp	r1, #4
+ 2553 0008 35D0     		beq	.L186
+ 2554 000a 0829     		cmp	r1, #8
+ 2555 000c 3CD0     		beq	.L187
+ 2556 000e 09B1     		cbz	r1, .L197
+ 2557 0010 0120     		movs	r0, #1
+ 2558              	.LVL166:
+ 2559              	.L188:
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 2560              		.loc 1 1063 3 view .LVU716
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2561              		.loc 1 1064 1 is_stmt 0 view .LVU717
+ 2562 0012 38BD     		pop	{r3, r4, r5, pc}
+ 2563              	.LVL167:
+ 2564              	.L197:
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 2565              		.loc 1 1021 7 is_stmt 1 view .LVU718
+ 2566 0014 0268     		ldr	r2, [r0]
+ 2567 0016 D368     		ldr	r3, [r2, #12]
+ 2568 0018 23F40073 		bic	r3, r3, #512
+ARM GAS  /tmp/cc7KL1Mv.s 			page 103
+
+
+ 2569 001c D360     		str	r3, [r2, #12]
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2570              		.loc 1 1022 7 view .LVU719
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2571              		.loc 1 1022 13 is_stmt 0 view .LVU720
+ 2572 001e 406A     		ldr	r0, [r0, #36]
+ 2573              	.LVL168:
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2574              		.loc 1 1022 13 view .LVU721
+ 2575 0020 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 2576              	.LVL169:
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2577              		.loc 1 1023 7 is_stmt 1 view .LVU722
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2578              		.loc 1 1047 3 view .LVU723
+ 2579              	.L189:
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2580              		.loc 1 1050 5 view .LVU724
+ 2581 0024 0022     		movs	r2, #0
+ 2582 0026 2146     		mov	r1, r4
+ 2583 0028 2868     		ldr	r0, [r5]
+ 2584 002a FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 2585              	.LVL170:
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2586              		.loc 1 1053 5 view .LVU725
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2587              		.loc 1 1053 5 view .LVU726
+ 2588 002e 2B68     		ldr	r3, [r5]
+ 2589 0030 196A     		ldr	r1, [r3, #32]
+ 2590 0032 41F21112 		movw	r2, #4369
+ 2591 0036 1142     		tst	r1, r2
+ 2592 0038 08D1     		bne	.L190
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2593              		.loc 1 1053 5 discriminator 1 view .LVU727
+ 2594 003a 196A     		ldr	r1, [r3, #32]
+ 2595 003c 40F24442 		movw	r2, #1092
+ 2596 0040 1142     		tst	r1, r2
+ 2597 0042 03D1     		bne	.L190
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2598              		.loc 1 1053 5 discriminator 3 view .LVU728
+ 2599 0044 5A6C     		ldr	r2, [r3, #68]
+ 2600 0046 22F40042 		bic	r2, r2, #32768
+ 2601 004a 5A64     		str	r2, [r3, #68]
+ 2602              	.L190:
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2603              		.loc 1 1053 5 discriminator 5 view .LVU729
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2604              		.loc 1 1056 5 discriminator 5 view .LVU730
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2605              		.loc 1 1056 5 discriminator 5 view .LVU731
+ 2606 004c 2B68     		ldr	r3, [r5]
+ 2607 004e 196A     		ldr	r1, [r3, #32]
+ 2608 0050 41F21112 		movw	r2, #4369
+ 2609 0054 1142     		tst	r1, r2
+ 2610 0056 08D1     		bne	.L191
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2611              		.loc 1 1056 5 discriminator 1 view .LVU732
+ARM GAS  /tmp/cc7KL1Mv.s 			page 104
+
+
+ 2612 0058 196A     		ldr	r1, [r3, #32]
+ 2613 005a 40F24442 		movw	r2, #1092
+ 2614 005e 1142     		tst	r1, r2
+ 2615 0060 03D1     		bne	.L191
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2616              		.loc 1 1056 5 discriminator 3 view .LVU733
+ 2617 0062 1A68     		ldr	r2, [r3]
+ 2618 0064 22F00102 		bic	r2, r2, #1
+ 2619 0068 1A60     		str	r2, [r3]
+ 2620              	.L191:
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2621              		.loc 1 1056 5 discriminator 5 view .LVU734
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2622              		.loc 1 1059 5 discriminator 5 view .LVU735
+ 2623 006a B4B9     		cbnz	r4, .L192
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2624              		.loc 1 1059 5 is_stmt 0 discriminator 1 view .LVU736
+ 2625 006c 0123     		movs	r3, #1
+ 2626 006e 85F84430 		strb	r3, [r5, #68]
+ 2627 0072 0020     		movs	r0, #0
+ 2628 0074 CDE7     		b	.L188
+ 2629              	.LVL171:
+ 2630              	.L186:
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 2631              		.loc 1 1029 7 is_stmt 1 view .LVU737
+ 2632 0076 0268     		ldr	r2, [r0]
+ 2633 0078 D368     		ldr	r3, [r2, #12]
+ 2634 007a 23F48063 		bic	r3, r3, #1024
+ 2635 007e D360     		str	r3, [r2, #12]
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2636              		.loc 1 1030 7 view .LVU738
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2637              		.loc 1 1030 13 is_stmt 0 view .LVU739
+ 2638 0080 806A     		ldr	r0, [r0, #40]
+ 2639              	.LVL172:
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2640              		.loc 1 1030 13 view .LVU740
+ 2641 0082 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 2642              	.LVL173:
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2643              		.loc 1 1031 7 is_stmt 1 view .LVU741
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2644              		.loc 1 1047 3 view .LVU742
+ 2645 0086 CDE7     		b	.L189
+ 2646              	.LVL174:
+ 2647              	.L187:
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ 2648              		.loc 1 1037 7 view .LVU743
+ 2649 0088 0268     		ldr	r2, [r0]
+ 2650 008a D368     		ldr	r3, [r2, #12]
+ 2651 008c 23F40063 		bic	r3, r3, #2048
+ 2652 0090 D360     		str	r3, [r2, #12]
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2653              		.loc 1 1038 7 view .LVU744
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2654              		.loc 1 1038 13 is_stmt 0 view .LVU745
+ 2655 0092 C06A     		ldr	r0, [r0, #44]
+ARM GAS  /tmp/cc7KL1Mv.s 			page 105
+
+
+ 2656              	.LVL175:
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 2657              		.loc 1 1038 13 view .LVU746
+ 2658 0094 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 2659              	.LVL176:
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2660              		.loc 1 1039 7 is_stmt 1 view .LVU747
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2661              		.loc 1 1047 3 view .LVU748
+ 2662 0098 C4E7     		b	.L189
+ 2663              	.L192:
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2664              		.loc 1 1059 5 is_stmt 0 discriminator 2 view .LVU749
+ 2665 009a 042C     		cmp	r4, #4
+ 2666 009c 06D0     		beq	.L198
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2667              		.loc 1 1059 5 discriminator 4 view .LVU750
+ 2668 009e 082C     		cmp	r4, #8
+ 2669 00a0 09D0     		beq	.L199
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2670              		.loc 1 1059 5 discriminator 7 view .LVU751
+ 2671 00a2 0123     		movs	r3, #1
+ 2672 00a4 85F84730 		strb	r3, [r5, #71]
+ 2673 00a8 0020     		movs	r0, #0
+ 2674 00aa B2E7     		b	.L188
+ 2675              	.L198:
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2676              		.loc 1 1059 5 discriminator 3 view .LVU752
+ 2677 00ac 0123     		movs	r3, #1
+ 2678 00ae 85F84530 		strb	r3, [r5, #69]
+ 2679 00b2 0020     		movs	r0, #0
+ 2680 00b4 ADE7     		b	.L188
+ 2681              	.L199:
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2682              		.loc 1 1059 5 discriminator 6 view .LVU753
+ 2683 00b6 0123     		movs	r3, #1
+ 2684 00b8 85F84630 		strb	r3, [r5, #70]
+ 2685 00bc 0020     		movs	r0, #0
+ 2686 00be A8E7     		b	.L188
+ 2687              		.cfi_endproc
+ 2688              	.LFE156:
+ 2690              		.section	.text.HAL_TIMEx_PWMN_Start,"ax",%progbits
+ 2691              		.align	1
+ 2692              		.global	HAL_TIMEx_PWMN_Start
+ 2693              		.syntax unified
+ 2694              		.thumb
+ 2695              		.thumb_func
+ 2696              		.fpu fpv5-d16
+ 2698              	HAL_TIMEx_PWMN_Start:
+ 2699              	.LVL177:
+ 2700              	.LFB157:
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 2701              		.loc 1 1100 1 is_stmt 1 view -0
+ 2702              		.cfi_startproc
+ 2703              		@ args = 0, pretend = 0, frame = 0
+ 2704              		@ frame_needed = 0, uses_anonymous_args = 0
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ARM GAS  /tmp/cc7KL1Mv.s 			page 106
+
+
+ 2705              		.loc 1 1100 1 is_stmt 0 view .LVU755
+ 2706 0000 10B5     		push	{r4, lr}
+ 2707              	.LCFI20:
+ 2708              		.cfi_def_cfa_offset 8
+ 2709              		.cfi_offset 4, -8
+ 2710              		.cfi_offset 14, -4
+ 2711 0002 0446     		mov	r4, r0
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2712              		.loc 1 1101 3 is_stmt 1 view .LVU756
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2713              		.loc 1 1104 3 view .LVU757
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2714              		.loc 1 1107 3 view .LVU758
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2715              		.loc 1 1107 46 is_stmt 0 view .LVU759
+ 2716 0004 0846     		mov	r0, r1
+ 2717              	.LVL178:
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2718              		.loc 1 1107 46 view .LVU760
+ 2719 0006 0029     		cmp	r1, #0
+ 2720 0008 3BD1     		bne	.L201
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2721              		.loc 1 1107 7 discriminator 1 view .LVU761
+ 2722 000a 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ 2723 000e DBB2     		uxtb	r3, r3
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2724              		.loc 1 1107 46 discriminator 1 view .LVU762
+ 2725 0010 013B     		subs	r3, r3, #1
+ 2726 0012 18BF     		it	ne
+ 2727 0014 0123     		movne	r3, #1
+ 2728              	.L202:
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2729              		.loc 1 1107 6 discriminator 12 view .LVU763
+ 2730 0016 002B     		cmp	r3, #0
+ 2731 0018 6AD1     		bne	.L212
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2732              		.loc 1 1113 3 is_stmt 1 view .LVU764
+ 2733 001a 0028     		cmp	r0, #0
+ 2734 001c 4AD1     		bne	.L206
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2735              		.loc 1 1113 3 is_stmt 0 discriminator 1 view .LVU765
+ 2736 001e 0223     		movs	r3, #2
+ 2737 0020 84F84430 		strb	r3, [r4, #68]
+ 2738              	.L207:
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2739              		.loc 1 1116 3 is_stmt 1 view .LVU766
+ 2740 0024 0422     		movs	r2, #4
+ 2741 0026 0146     		mov	r1, r0
+ 2742              	.LVL179:
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2743              		.loc 1 1116 3 is_stmt 0 view .LVU767
+ 2744 0028 2068     		ldr	r0, [r4]
+ 2745              	.LVL180:
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2746              		.loc 1 1116 3 view .LVU768
+ 2747 002a FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 2748              	.LVL181:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 107
+
+
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2749              		.loc 1 1119 3 is_stmt 1 view .LVU769
+ 2750 002e 2268     		ldr	r2, [r4]
+ 2751 0030 536C     		ldr	r3, [r2, #68]
+ 2752 0032 43F40043 		orr	r3, r3, #32768
+ 2753 0036 5364     		str	r3, [r2, #68]
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2754              		.loc 1 1122 3 view .LVU770
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2755              		.loc 1 1122 7 is_stmt 0 view .LVU771
+ 2756 0038 2368     		ldr	r3, [r4]
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2757              		.loc 1 1122 6 view .LVU772
+ 2758 003a 2F4A     		ldr	r2, .L219
+ 2759 003c B3F1804F 		cmp	r3, #1073741824
+ 2760 0040 18BF     		it	ne
+ 2761 0042 9342     		cmpne	r3, r2
+ 2762 0044 46D0     		beq	.L210
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2763              		.loc 1 1122 7 discriminator 1 view .LVU773
+ 2764 0046 A2F57C42 		sub	r2, r2, #64512
+ 2765 004a 9342     		cmp	r3, r2
+ 2766 004c 42D0     		beq	.L210
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2767              		.loc 1 1122 7 discriminator 2 view .LVU774
+ 2768 004e 02F58062 		add	r2, r2, #1024
+ 2769 0052 9342     		cmp	r3, r2
+ 2770 0054 3ED0     		beq	.L210
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2771              		.loc 1 1122 7 discriminator 3 view .LVU775
+ 2772 0056 02F58062 		add	r2, r2, #1024
+ 2773 005a 9342     		cmp	r3, r2
+ 2774 005c 3AD0     		beq	.L210
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2775              		.loc 1 1122 7 discriminator 4 view .LVU776
+ 2776 005e 02F57842 		add	r2, r2, #63488
+ 2777 0062 9342     		cmp	r3, r2
+ 2778 0064 36D0     		beq	.L210
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2779              		.loc 1 1122 7 discriminator 5 view .LVU777
+ 2780 0066 02F57052 		add	r2, r2, #15360
+ 2781 006a 9342     		cmp	r3, r2
+ 2782 006c 32D0     		beq	.L210
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2783              		.loc 1 1122 7 discriminator 6 view .LVU778
+ 2784 006e A2F59432 		sub	r2, r2, #75776
+ 2785 0072 9342     		cmp	r3, r2
+ 2786 0074 2ED0     		beq	.L210
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2787              		.loc 1 1132 5 is_stmt 1 view .LVU779
+ 2788 0076 1A68     		ldr	r2, [r3]
+ 2789 0078 42F00102 		orr	r2, r2, #1
+ 2790 007c 1A60     		str	r2, [r3]
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 2791              		.loc 1 1136 10 is_stmt 0 view .LVU780
+ 2792 007e 0020     		movs	r0, #0
+ 2793 0080 37E0     		b	.L205
+ARM GAS  /tmp/cc7KL1Mv.s 			page 108
+
+
+ 2794              	.LVL182:
+ 2795              	.L201:
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2796              		.loc 1 1107 46 discriminator 2 view .LVU781
+ 2797 0082 0429     		cmp	r1, #4
+ 2798 0084 08D0     		beq	.L215
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2799              		.loc 1 1107 46 discriminator 5 view .LVU782
+ 2800 0086 0829     		cmp	r1, #8
+ 2801 0088 0DD0     		beq	.L216
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2802              		.loc 1 1107 7 discriminator 8 view .LVU783
+ 2803 008a 94F84730 		ldrb	r3, [r4, #71]	@ zero_extendqisi2
+ 2804 008e DBB2     		uxtb	r3, r3
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2805              		.loc 1 1107 46 discriminator 8 view .LVU784
+ 2806 0090 013B     		subs	r3, r3, #1
+ 2807 0092 18BF     		it	ne
+ 2808 0094 0123     		movne	r3, #1
+ 2809 0096 BEE7     		b	.L202
+ 2810              	.L215:
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2811              		.loc 1 1107 7 discriminator 4 view .LVU785
+ 2812 0098 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 2813 009c DBB2     		uxtb	r3, r3
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2814              		.loc 1 1107 46 discriminator 4 view .LVU786
+ 2815 009e 013B     		subs	r3, r3, #1
+ 2816 00a0 18BF     		it	ne
+ 2817 00a2 0123     		movne	r3, #1
+ 2818 00a4 B7E7     		b	.L202
+ 2819              	.L216:
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2820              		.loc 1 1107 7 discriminator 7 view .LVU787
+ 2821 00a6 94F84630 		ldrb	r3, [r4, #70]	@ zero_extendqisi2
+ 2822 00aa DBB2     		uxtb	r3, r3
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 2823              		.loc 1 1107 46 discriminator 7 view .LVU788
+ 2824 00ac 013B     		subs	r3, r3, #1
+ 2825 00ae 18BF     		it	ne
+ 2826 00b0 0123     		movne	r3, #1
+ 2827 00b2 B0E7     		b	.L202
+ 2828              	.L206:
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2829              		.loc 1 1113 3 discriminator 2 view .LVU789
+ 2830 00b4 0428     		cmp	r0, #4
+ 2831 00b6 05D0     		beq	.L217
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2832              		.loc 1 1113 3 discriminator 4 view .LVU790
+ 2833 00b8 0828     		cmp	r0, #8
+ 2834 00ba 07D0     		beq	.L218
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2835              		.loc 1 1113 3 discriminator 7 view .LVU791
+ 2836 00bc 0223     		movs	r3, #2
+ 2837 00be 84F84730 		strb	r3, [r4, #71]
+ 2838 00c2 AFE7     		b	.L207
+ 2839              	.L217:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 109
+
+
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2840              		.loc 1 1113 3 discriminator 3 view .LVU792
+ 2841 00c4 0223     		movs	r3, #2
+ 2842 00c6 84F84530 		strb	r3, [r4, #69]
+ 2843 00ca ABE7     		b	.L207
+ 2844              	.L218:
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2845              		.loc 1 1113 3 discriminator 6 view .LVU793
+ 2846 00cc 0223     		movs	r3, #2
+ 2847 00ce 84F84630 		strb	r3, [r4, #70]
+ 2848 00d2 A7E7     		b	.L207
+ 2849              	.LVL183:
+ 2850              	.L210:
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 2851              		.loc 1 1124 5 is_stmt 1 view .LVU794
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 2852              		.loc 1 1124 29 is_stmt 0 view .LVU795
+ 2853 00d4 9968     		ldr	r1, [r3, #8]
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 2854              		.loc 1 1124 13 view .LVU796
+ 2855 00d6 094A     		ldr	r2, .L219+4
+ 2856 00d8 0A40     		ands	r2, r2, r1
+ 2857              	.LVL184:
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2858              		.loc 1 1125 5 is_stmt 1 view .LVU797
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 2859              		.loc 1 1125 8 is_stmt 0 view .LVU798
+ 2860 00da 062A     		cmp	r2, #6
+ 2861 00dc 18BF     		it	ne
+ 2862 00de B2F5803F 		cmpne	r2, #65536
+ 2863 00e2 07D0     		beq	.L213
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2864              		.loc 1 1127 7 is_stmt 1 view .LVU799
+ 2865 00e4 1A68     		ldr	r2, [r3]
+ 2866              	.LVL185:
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 2867              		.loc 1 1127 7 is_stmt 0 view .LVU800
+ 2868 00e6 42F00102 		orr	r2, r2, #1
+ 2869 00ea 1A60     		str	r2, [r3]
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 2870              		.loc 1 1136 10 view .LVU801
+ 2871 00ec 0020     		movs	r0, #0
+ 2872 00ee 00E0     		b	.L205
+ 2873              	.LVL186:
+ 2874              	.L212:
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 2875              		.loc 1 1109 12 view .LVU802
+ 2876 00f0 0120     		movs	r0, #1
+ 2877              	.LVL187:
+ 2878              	.L205:
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2879              		.loc 1 1137 1 view .LVU803
+ 2880 00f2 10BD     		pop	{r4, pc}
+ 2881              	.LVL188:
+ 2882              	.L213:
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 2883              		.loc 1 1136 10 view .LVU804
+ARM GAS  /tmp/cc7KL1Mv.s 			page 110
+
+
+ 2884 00f4 0020     		movs	r0, #0
+ 2885 00f6 FCE7     		b	.L205
+ 2886              	.L220:
+ 2887              		.align	2
+ 2888              	.L219:
+ 2889 00f8 00000140 		.word	1073807360
+ 2890 00fc 07000100 		.word	65543
+ 2891              		.cfi_endproc
+ 2892              	.LFE157:
+ 2894              		.section	.text.HAL_TIMEx_PWMN_Stop,"ax",%progbits
+ 2895              		.align	1
+ 2896              		.global	HAL_TIMEx_PWMN_Stop
+ 2897              		.syntax unified
+ 2898              		.thumb
+ 2899              		.thumb_func
+ 2900              		.fpu fpv5-d16
+ 2902              	HAL_TIMEx_PWMN_Stop:
+ 2903              	.LVL189:
+ 2904              	.LFB158:
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 2905              		.loc 1 1150 1 is_stmt 1 view -0
+ 2906              		.cfi_startproc
+ 2907              		@ args = 0, pretend = 0, frame = 0
+ 2908              		@ frame_needed = 0, uses_anonymous_args = 0
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 2909              		.loc 1 1150 1 is_stmt 0 view .LVU806
+ 2910 0000 38B5     		push	{r3, r4, r5, lr}
+ 2911              	.LCFI21:
+ 2912              		.cfi_def_cfa_offset 16
+ 2913              		.cfi_offset 3, -16
+ 2914              		.cfi_offset 4, -12
+ 2915              		.cfi_offset 5, -8
+ 2916              		.cfi_offset 14, -4
+ 2917 0002 0446     		mov	r4, r0
+ 2918 0004 0D46     		mov	r5, r1
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2919              		.loc 1 1152 3 is_stmt 1 view .LVU807
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2920              		.loc 1 1155 3 view .LVU808
+ 2921 0006 0022     		movs	r2, #0
+ 2922 0008 0068     		ldr	r0, [r0]
+ 2923              	.LVL190:
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2924              		.loc 1 1155 3 is_stmt 0 view .LVU809
+ 2925 000a FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 2926              	.LVL191:
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2927              		.loc 1 1158 3 is_stmt 1 view .LVU810
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2928              		.loc 1 1158 3 view .LVU811
+ 2929 000e 2368     		ldr	r3, [r4]
+ 2930 0010 196A     		ldr	r1, [r3, #32]
+ 2931 0012 41F21112 		movw	r2, #4369
+ 2932 0016 1142     		tst	r1, r2
+ 2933 0018 08D1     		bne	.L222
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2934              		.loc 1 1158 3 discriminator 1 view .LVU812
+ARM GAS  /tmp/cc7KL1Mv.s 			page 111
+
+
+ 2935 001a 196A     		ldr	r1, [r3, #32]
+ 2936 001c 40F24442 		movw	r2, #1092
+ 2937 0020 1142     		tst	r1, r2
+ 2938 0022 03D1     		bne	.L222
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2939              		.loc 1 1158 3 discriminator 3 view .LVU813
+ 2940 0024 5A6C     		ldr	r2, [r3, #68]
+ 2941 0026 22F40042 		bic	r2, r2, #32768
+ 2942 002a 5A64     		str	r2, [r3, #68]
+ 2943              	.L222:
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2944              		.loc 1 1158 3 discriminator 5 view .LVU814
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2945              		.loc 1 1161 3 discriminator 5 view .LVU815
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2946              		.loc 1 1161 3 discriminator 5 view .LVU816
+ 2947 002c 2368     		ldr	r3, [r4]
+ 2948 002e 196A     		ldr	r1, [r3, #32]
+ 2949 0030 41F21112 		movw	r2, #4369
+ 2950 0034 1142     		tst	r1, r2
+ 2951 0036 08D1     		bne	.L223
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2952              		.loc 1 1161 3 discriminator 1 view .LVU817
+ 2953 0038 196A     		ldr	r1, [r3, #32]
+ 2954 003a 40F24442 		movw	r2, #1092
+ 2955 003e 1142     		tst	r1, r2
+ 2956 0040 03D1     		bne	.L223
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2957              		.loc 1 1161 3 discriminator 3 view .LVU818
+ 2958 0042 1A68     		ldr	r2, [r3]
+ 2959 0044 22F00102 		bic	r2, r2, #1
+ 2960 0048 1A60     		str	r2, [r3]
+ 2961              	.L223:
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2962              		.loc 1 1161 3 discriminator 5 view .LVU819
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2963              		.loc 1 1164 3 discriminator 5 view .LVU820
+ 2964 004a 25B9     		cbnz	r5, .L224
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2965              		.loc 1 1164 3 is_stmt 0 discriminator 1 view .LVU821
+ 2966 004c 0123     		movs	r3, #1
+ 2967 004e 84F84430 		strb	r3, [r4, #68]
+ 2968              	.L225:
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 2969              		.loc 1 1167 3 is_stmt 1 view .LVU822
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2970              		.loc 1 1168 1 is_stmt 0 view .LVU823
+ 2971 0052 0020     		movs	r0, #0
+ 2972 0054 38BD     		pop	{r3, r4, r5, pc}
+ 2973              	.LVL192:
+ 2974              	.L224:
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2975              		.loc 1 1164 3 discriminator 2 view .LVU824
+ 2976 0056 042D     		cmp	r5, #4
+ 2977 0058 05D0     		beq	.L229
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2978              		.loc 1 1164 3 discriminator 4 view .LVU825
+ARM GAS  /tmp/cc7KL1Mv.s 			page 112
+
+
+ 2979 005a 082D     		cmp	r5, #8
+ 2980 005c 07D0     		beq	.L230
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2981              		.loc 1 1164 3 discriminator 7 view .LVU826
+ 2982 005e 0123     		movs	r3, #1
+ 2983 0060 84F84730 		strb	r3, [r4, #71]
+ 2984 0064 F5E7     		b	.L225
+ 2985              	.L229:
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2986              		.loc 1 1164 3 discriminator 3 view .LVU827
+ 2987 0066 0123     		movs	r3, #1
+ 2988 0068 84F84530 		strb	r3, [r4, #69]
+ 2989 006c F1E7     		b	.L225
+ 2990              	.L230:
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 2991              		.loc 1 1164 3 discriminator 6 view .LVU828
+ 2992 006e 0123     		movs	r3, #1
+ 2993 0070 84F84630 		strb	r3, [r4, #70]
+ 2994 0074 EDE7     		b	.L225
+ 2995              		.cfi_endproc
+ 2996              	.LFE158:
+ 2998              		.section	.text.HAL_TIMEx_PWMN_Start_IT,"ax",%progbits
+ 2999              		.align	1
+ 3000              		.global	HAL_TIMEx_PWMN_Start_IT
+ 3001              		.syntax unified
+ 3002              		.thumb
+ 3003              		.thumb_func
+ 3004              		.fpu fpv5-d16
+ 3006              	HAL_TIMEx_PWMN_Start_IT:
+ 3007              	.LVL193:
+ 3008              	.LFB159:
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3009              		.loc 1 1182 1 is_stmt 1 view -0
+ 3010              		.cfi_startproc
+ 3011              		@ args = 0, pretend = 0, frame = 0
+ 3012              		@ frame_needed = 0, uses_anonymous_args = 0
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3013              		.loc 1 1182 1 is_stmt 0 view .LVU830
+ 3014 0000 10B5     		push	{r4, lr}
+ 3015              	.LCFI22:
+ 3016              		.cfi_def_cfa_offset 8
+ 3017              		.cfi_offset 4, -8
+ 3018              		.cfi_offset 14, -4
+ 3019 0002 0446     		mov	r4, r0
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 3020              		.loc 1 1183 3 is_stmt 1 view .LVU831
+ 3021              	.LVL194:
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3022              		.loc 1 1184 3 view .LVU832
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3023              		.loc 1 1187 3 view .LVU833
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3024              		.loc 1 1190 3 view .LVU834
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3025              		.loc 1 1190 46 is_stmt 0 view .LVU835
+ 3026 0004 0846     		mov	r0, r1
+ 3027              	.LVL195:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 113
+
+
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3028              		.loc 1 1190 46 view .LVU836
+ 3029 0006 99B9     		cbnz	r1, .L232
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3030              		.loc 1 1190 7 discriminator 1 view .LVU837
+ 3031 0008 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ 3032 000c DBB2     		uxtb	r3, r3
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3033              		.loc 1 1190 46 discriminator 1 view .LVU838
+ 3034 000e 013B     		subs	r3, r3, #1
+ 3035 0010 18BF     		it	ne
+ 3036 0012 0123     		movne	r3, #1
+ 3037              	.L233:
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3038              		.loc 1 1190 6 discriminator 12 view .LVU839
+ 3039 0014 002B     		cmp	r3, #0
+ 3040 0016 40F08780 		bne	.L246
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3041              		.loc 1 1196 3 is_stmt 1 view .LVU840
+ 3042 001a 10BB     		cbnz	r0, .L237
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3043              		.loc 1 1196 3 is_stmt 0 discriminator 1 view .LVU841
+ 3044 001c 0223     		movs	r3, #2
+ 3045 001e 84F84430 		strb	r3, [r4, #68]
+ 3046              	.L238:
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3047              		.loc 1 1198 3 is_stmt 1 view .LVU842
+ 3048 0022 0428     		cmp	r0, #4
+ 3049 0024 66D0     		beq	.L241
+ 3050 0026 0828     		cmp	r0, #8
+ 3051 0028 6AD0     		beq	.L242
+ 3052 002a 50B3     		cbz	r0, .L250
+ 3053 002c 0120     		movs	r0, #1
+ 3054              	.LVL196:
+ 3055              	.L236:
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3056              		.loc 1 1254 1 is_stmt 0 view .LVU843
+ 3057 002e 10BD     		pop	{r4, pc}
+ 3058              	.LVL197:
+ 3059              	.L232:
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3060              		.loc 1 1190 46 discriminator 2 view .LVU844
+ 3061 0030 0429     		cmp	r1, #4
+ 3062 0032 08D0     		beq	.L251
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3063              		.loc 1 1190 46 discriminator 5 view .LVU845
+ 3064 0034 0829     		cmp	r1, #8
+ 3065 0036 0DD0     		beq	.L252
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3066              		.loc 1 1190 7 discriminator 8 view .LVU846
+ 3067 0038 94F84730 		ldrb	r3, [r4, #71]	@ zero_extendqisi2
+ 3068 003c DBB2     		uxtb	r3, r3
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3069              		.loc 1 1190 46 discriminator 8 view .LVU847
+ 3070 003e 013B     		subs	r3, r3, #1
+ 3071 0040 18BF     		it	ne
+ 3072 0042 0123     		movne	r3, #1
+ARM GAS  /tmp/cc7KL1Mv.s 			page 114
+
+
+ 3073 0044 E6E7     		b	.L233
+ 3074              	.L251:
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3075              		.loc 1 1190 7 discriminator 4 view .LVU848
+ 3076 0046 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 3077 004a DBB2     		uxtb	r3, r3
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3078              		.loc 1 1190 46 discriminator 4 view .LVU849
+ 3079 004c 013B     		subs	r3, r3, #1
+ 3080 004e 18BF     		it	ne
+ 3081 0050 0123     		movne	r3, #1
+ 3082 0052 DFE7     		b	.L233
+ 3083              	.L252:
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3084              		.loc 1 1190 7 discriminator 7 view .LVU850
+ 3085 0054 94F84630 		ldrb	r3, [r4, #70]	@ zero_extendqisi2
+ 3086 0058 DBB2     		uxtb	r3, r3
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3087              		.loc 1 1190 46 discriminator 7 view .LVU851
+ 3088 005a 013B     		subs	r3, r3, #1
+ 3089 005c 18BF     		it	ne
+ 3090 005e 0123     		movne	r3, #1
+ 3091 0060 D8E7     		b	.L233
+ 3092              	.L237:
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3093              		.loc 1 1196 3 discriminator 2 view .LVU852
+ 3094 0062 0428     		cmp	r0, #4
+ 3095 0064 05D0     		beq	.L253
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3096              		.loc 1 1196 3 discriminator 4 view .LVU853
+ 3097 0066 0828     		cmp	r0, #8
+ 3098 0068 07D0     		beq	.L254
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3099              		.loc 1 1196 3 discriminator 7 view .LVU854
+ 3100 006a 0223     		movs	r3, #2
+ 3101 006c 84F84730 		strb	r3, [r4, #71]
+ 3102 0070 D7E7     		b	.L238
+ 3103              	.L253:
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3104              		.loc 1 1196 3 discriminator 3 view .LVU855
+ 3105 0072 0223     		movs	r3, #2
+ 3106 0074 84F84530 		strb	r3, [r4, #69]
+ 3107 0078 D3E7     		b	.L238
+ 3108              	.L254:
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3109              		.loc 1 1196 3 discriminator 6 view .LVU856
+ 3110 007a 0223     		movs	r3, #2
+ 3111 007c 84F84630 		strb	r3, [r4, #70]
+ 3112 0080 CFE7     		b	.L238
+ 3113              	.L250:
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3114              		.loc 1 1203 7 is_stmt 1 view .LVU857
+ 3115 0082 2268     		ldr	r2, [r4]
+ 3116 0084 D368     		ldr	r3, [r2, #12]
+ 3117 0086 43F00203 		orr	r3, r3, #2
+ 3118 008a D360     		str	r3, [r2, #12]
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ARM GAS  /tmp/cc7KL1Mv.s 			page 115
+
+
+ 3119              		.loc 1 1204 7 view .LVU858
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3120              		.loc 1 1226 3 view .LVU859
+ 3121              	.L243:
+1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3122              		.loc 1 1229 5 view .LVU860
+ 3123 008c 2268     		ldr	r2, [r4]
+ 3124 008e D368     		ldr	r3, [r2, #12]
+ 3125 0090 43F08003 		orr	r3, r3, #128
+ 3126 0094 D360     		str	r3, [r2, #12]
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3127              		.loc 1 1232 5 view .LVU861
+ 3128 0096 0422     		movs	r2, #4
+ 3129 0098 0146     		mov	r1, r0
+ 3130 009a 2068     		ldr	r0, [r4]
+ 3131              	.LVL198:
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3132              		.loc 1 1232 5 is_stmt 0 view .LVU862
+ 3133 009c FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 3134              	.LVL199:
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3135              		.loc 1 1235 5 is_stmt 1 view .LVU863
+ 3136 00a0 2268     		ldr	r2, [r4]
+ 3137 00a2 536C     		ldr	r3, [r2, #68]
+ 3138 00a4 43F40043 		orr	r3, r3, #32768
+ 3139 00a8 5364     		str	r3, [r2, #68]
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3140              		.loc 1 1238 5 view .LVU864
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3141              		.loc 1 1238 9 is_stmt 0 view .LVU865
+ 3142 00aa 2368     		ldr	r3, [r4]
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3143              		.loc 1 1238 8 view .LVU866
+ 3144 00ac 204A     		ldr	r2, .L255
+ 3145 00ae B3F1804F 		cmp	r3, #1073741824
+ 3146 00b2 18BF     		it	ne
+ 3147 00b4 9342     		cmpne	r3, r2
+ 3148 00b6 29D0     		beq	.L244
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3149              		.loc 1 1238 9 discriminator 1 view .LVU867
+ 3150 00b8 A2F57C42 		sub	r2, r2, #64512
+ 3151 00bc 9342     		cmp	r3, r2
+ 3152 00be 25D0     		beq	.L244
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3153              		.loc 1 1238 9 discriminator 2 view .LVU868
+ 3154 00c0 02F58062 		add	r2, r2, #1024
+ 3155 00c4 9342     		cmp	r3, r2
+ 3156 00c6 21D0     		beq	.L244
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3157              		.loc 1 1238 9 discriminator 3 view .LVU869
+ 3158 00c8 02F58062 		add	r2, r2, #1024
+ 3159 00cc 9342     		cmp	r3, r2
+ 3160 00ce 1DD0     		beq	.L244
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3161              		.loc 1 1238 9 discriminator 4 view .LVU870
+ 3162 00d0 02F57842 		add	r2, r2, #63488
+ 3163 00d4 9342     		cmp	r3, r2
+ARM GAS  /tmp/cc7KL1Mv.s 			page 116
+
+
+ 3164 00d6 19D0     		beq	.L244
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3165              		.loc 1 1238 9 discriminator 5 view .LVU871
+ 3166 00d8 02F57052 		add	r2, r2, #15360
+ 3167 00dc 9342     		cmp	r3, r2
+ 3168 00de 15D0     		beq	.L244
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3169              		.loc 1 1238 9 discriminator 6 view .LVU872
+ 3170 00e0 A2F59432 		sub	r2, r2, #75776
+ 3171 00e4 9342     		cmp	r3, r2
+ 3172 00e6 11D0     		beq	.L244
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3173              		.loc 1 1248 7 is_stmt 1 view .LVU873
+ 3174 00e8 1A68     		ldr	r2, [r3]
+ 3175 00ea 42F00102 		orr	r2, r2, #1
+ 3176 00ee 1A60     		str	r2, [r3]
+ 3177 00f0 0020     		movs	r0, #0
+ 3178 00f2 9CE7     		b	.L236
+ 3179              	.LVL200:
+ 3180              	.L241:
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3181              		.loc 1 1210 7 view .LVU874
+ 3182 00f4 2268     		ldr	r2, [r4]
+ 3183 00f6 D368     		ldr	r3, [r2, #12]
+ 3184 00f8 43F00403 		orr	r3, r3, #4
+ 3185 00fc D360     		str	r3, [r2, #12]
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3186              		.loc 1 1211 7 view .LVU875
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3187              		.loc 1 1226 3 view .LVU876
+ 3188 00fe C5E7     		b	.L243
+ 3189              	.L242:
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3190              		.loc 1 1217 7 view .LVU877
+ 3191 0100 2268     		ldr	r2, [r4]
+ 3192 0102 D368     		ldr	r3, [r2, #12]
+ 3193 0104 43F00803 		orr	r3, r3, #8
+ 3194 0108 D360     		str	r3, [r2, #12]
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3195              		.loc 1 1218 7 view .LVU878
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3196              		.loc 1 1226 3 view .LVU879
+ 3197 010a BFE7     		b	.L243
+ 3198              	.LVL201:
+ 3199              	.L244:
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 3200              		.loc 1 1240 7 view .LVU880
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 3201              		.loc 1 1240 31 is_stmt 0 view .LVU881
+ 3202 010c 9968     		ldr	r1, [r3, #8]
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 3203              		.loc 1 1240 15 view .LVU882
+ 3204 010e 094A     		ldr	r2, .L255+4
+ 3205 0110 0A40     		ands	r2, r2, r1
+ 3206              	.LVL202:
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 3207              		.loc 1 1241 7 is_stmt 1 view .LVU883
+ARM GAS  /tmp/cc7KL1Mv.s 			page 117
+
+
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 3208              		.loc 1 1241 10 is_stmt 0 view .LVU884
+ 3209 0112 062A     		cmp	r2, #6
+ 3210 0114 18BF     		it	ne
+ 3211 0116 B2F5803F 		cmpne	r2, #65536
+ 3212 011a 07D0     		beq	.L248
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 3213              		.loc 1 1243 9 is_stmt 1 view .LVU885
+ 3214 011c 1A68     		ldr	r2, [r3]
+ 3215              	.LVL203:
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 3216              		.loc 1 1243 9 is_stmt 0 view .LVU886
+ 3217 011e 42F00102 		orr	r2, r2, #1
+ 3218 0122 1A60     		str	r2, [r3]
+ 3219 0124 0020     		movs	r0, #0
+ 3220 0126 82E7     		b	.L236
+ 3221              	.LVL204:
+ 3222              	.L246:
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3223              		.loc 1 1192 12 view .LVU887
+ 3224 0128 0120     		movs	r0, #1
+ 3225              	.LVL205:
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3226              		.loc 1 1192 12 view .LVU888
+ 3227 012a 80E7     		b	.L236
+ 3228              	.LVL206:
+ 3229              	.L248:
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3230              		.loc 1 1192 12 view .LVU889
+ 3231 012c 0020     		movs	r0, #0
+ 3232 012e 7EE7     		b	.L236
+ 3233              	.L256:
+ 3234              		.align	2
+ 3235              	.L255:
+ 3236 0130 00000140 		.word	1073807360
+ 3237 0134 07000100 		.word	65543
+ 3238              		.cfi_endproc
+ 3239              	.LFE159:
+ 3241              		.section	.text.HAL_TIMEx_PWMN_Stop_IT,"ax",%progbits
+ 3242              		.align	1
+ 3243              		.global	HAL_TIMEx_PWMN_Stop_IT
+ 3244              		.syntax unified
+ 3245              		.thumb
+ 3246              		.thumb_func
+ 3247              		.fpu fpv5-d16
+ 3249              	HAL_TIMEx_PWMN_Stop_IT:
+ 3250              	.LVL207:
+ 3251              	.LFB160:
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3252              		.loc 1 1268 1 is_stmt 1 view -0
+ 3253              		.cfi_startproc
+ 3254              		@ args = 0, pretend = 0, frame = 0
+ 3255              		@ frame_needed = 0, uses_anonymous_args = 0
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3256              		.loc 1 1268 1 is_stmt 0 view .LVU891
+ 3257 0000 38B5     		push	{r3, r4, r5, lr}
+ 3258              	.LCFI23:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 118
+
+
+ 3259              		.cfi_def_cfa_offset 16
+ 3260              		.cfi_offset 3, -16
+ 3261              		.cfi_offset 4, -12
+ 3262              		.cfi_offset 5, -8
+ 3263              		.cfi_offset 14, -4
+ 3264 0002 0546     		mov	r5, r0
+ 3265 0004 0C46     		mov	r4, r1
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpccer;
+ 3266              		.loc 1 1269 3 is_stmt 1 view .LVU892
+ 3267              	.LVL208:
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3268              		.loc 1 1270 3 view .LVU893
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3269              		.loc 1 1273 3 view .LVU894
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3270              		.loc 1 1275 3 view .LVU895
+ 3271 0006 0429     		cmp	r1, #4
+ 3272 0008 3CD0     		beq	.L258
+ 3273 000a 0829     		cmp	r1, #8
+ 3274 000c 40D0     		beq	.L259
+ 3275 000e 09B1     		cbz	r1, .L270
+ 3276 0010 0120     		movs	r0, #1
+ 3277              	.LVL209:
+ 3278              	.L260:
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 3279              		.loc 1 1326 3 view .LVU896
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3280              		.loc 1 1327 1 is_stmt 0 view .LVU897
+ 3281 0012 38BD     		pop	{r3, r4, r5, pc}
+ 3282              	.LVL210:
+ 3283              	.L270:
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3284              		.loc 1 1280 7 is_stmt 1 view .LVU898
+ 3285 0014 0268     		ldr	r2, [r0]
+ 3286 0016 D368     		ldr	r3, [r2, #12]
+ 3287 0018 23F00203 		bic	r3, r3, #2
+ 3288 001c D360     		str	r3, [r2, #12]
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3289              		.loc 1 1281 7 view .LVU899
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3290              		.loc 1 1303 3 view .LVU900
+ 3291              	.L261:
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3292              		.loc 1 1306 5 view .LVU901
+ 3293 001e 0022     		movs	r2, #0
+ 3294 0020 2146     		mov	r1, r4
+ 3295              	.LVL211:
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3296              		.loc 1 1306 5 is_stmt 0 view .LVU902
+ 3297 0022 2868     		ldr	r0, [r5]
+ 3298              	.LVL212:
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3299              		.loc 1 1306 5 view .LVU903
+ 3300 0024 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 3301              	.LVL213:
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+ 3302              		.loc 1 1309 5 is_stmt 1 view .LVU904
+ARM GAS  /tmp/cc7KL1Mv.s 			page 119
+
+
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+ 3303              		.loc 1 1309 19 is_stmt 0 view .LVU905
+ 3304 0028 2B68     		ldr	r3, [r5]
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+ 3305              		.loc 1 1309 13 view .LVU906
+ 3306 002a 196A     		ldr	r1, [r3, #32]
+ 3307              	.LVL214:
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3308              		.loc 1 1310 5 is_stmt 1 view .LVU907
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3309              		.loc 1 1310 8 is_stmt 0 view .LVU908
+ 3310 002c 40F24442 		movw	r2, #1092
+ 3311 0030 1142     		tst	r1, r2
+ 3312 0032 03D1     		bne	.L262
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3313              		.loc 1 1312 7 is_stmt 1 view .LVU909
+ 3314 0034 DA68     		ldr	r2, [r3, #12]
+ 3315 0036 22F08002 		bic	r2, r2, #128
+ 3316 003a DA60     		str	r2, [r3, #12]
+ 3317              	.L262:
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3318              		.loc 1 1316 5 view .LVU910
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3319              		.loc 1 1316 5 view .LVU911
+ 3320 003c 2B68     		ldr	r3, [r5]
+ 3321 003e 196A     		ldr	r1, [r3, #32]
+ 3322              	.LVL215:
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3323              		.loc 1 1316 5 is_stmt 0 view .LVU912
+ 3324 0040 41F21112 		movw	r2, #4369
+ 3325 0044 1142     		tst	r1, r2
+ 3326 0046 08D1     		bne	.L263
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3327              		.loc 1 1316 5 is_stmt 1 discriminator 1 view .LVU913
+ 3328 0048 196A     		ldr	r1, [r3, #32]
+ 3329 004a 40F24442 		movw	r2, #1092
+ 3330 004e 1142     		tst	r1, r2
+ 3331 0050 03D1     		bne	.L263
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3332              		.loc 1 1316 5 discriminator 3 view .LVU914
+ 3333 0052 5A6C     		ldr	r2, [r3, #68]
+ 3334 0054 22F40042 		bic	r2, r2, #32768
+ 3335 0058 5A64     		str	r2, [r3, #68]
+ 3336              	.L263:
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3337              		.loc 1 1316 5 discriminator 5 view .LVU915
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3338              		.loc 1 1319 5 discriminator 5 view .LVU916
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3339              		.loc 1 1319 5 discriminator 5 view .LVU917
+ 3340 005a 2B68     		ldr	r3, [r5]
+ 3341 005c 196A     		ldr	r1, [r3, #32]
+ 3342 005e 41F21112 		movw	r2, #4369
+ 3343 0062 1142     		tst	r1, r2
+ 3344 0064 08D1     		bne	.L264
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3345              		.loc 1 1319 5 discriminator 1 view .LVU918
+ARM GAS  /tmp/cc7KL1Mv.s 			page 120
+
+
+ 3346 0066 196A     		ldr	r1, [r3, #32]
+ 3347 0068 40F24442 		movw	r2, #1092
+ 3348 006c 1142     		tst	r1, r2
+ 3349 006e 03D1     		bne	.L264
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3350              		.loc 1 1319 5 discriminator 3 view .LVU919
+ 3351 0070 1A68     		ldr	r2, [r3]
+ 3352 0072 22F00102 		bic	r2, r2, #1
+ 3353 0076 1A60     		str	r2, [r3]
+ 3354              	.L264:
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3355              		.loc 1 1319 5 discriminator 5 view .LVU920
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3356              		.loc 1 1322 5 discriminator 5 view .LVU921
+ 3357 0078 84B9     		cbnz	r4, .L265
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3358              		.loc 1 1322 5 is_stmt 0 discriminator 1 view .LVU922
+ 3359 007a 0123     		movs	r3, #1
+ 3360 007c 85F84430 		strb	r3, [r5, #68]
+ 3361 0080 0020     		movs	r0, #0
+ 3362 0082 C6E7     		b	.L260
+ 3363              	.LVL216:
+ 3364              	.L258:
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3365              		.loc 1 1287 7 is_stmt 1 view .LVU923
+ 3366 0084 0268     		ldr	r2, [r0]
+ 3367 0086 D368     		ldr	r3, [r2, #12]
+ 3368 0088 23F00403 		bic	r3, r3, #4
+ 3369 008c D360     		str	r3, [r2, #12]
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3370              		.loc 1 1288 7 view .LVU924
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3371              		.loc 1 1303 3 view .LVU925
+ 3372 008e C6E7     		b	.L261
+ 3373              	.L259:
+1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3374              		.loc 1 1294 7 view .LVU926
+ 3375 0090 0268     		ldr	r2, [r0]
+ 3376 0092 D368     		ldr	r3, [r2, #12]
+ 3377 0094 23F00803 		bic	r3, r3, #8
+ 3378 0098 D360     		str	r3, [r2, #12]
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3379              		.loc 1 1295 7 view .LVU927
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3380              		.loc 1 1303 3 view .LVU928
+ 3381 009a C0E7     		b	.L261
+ 3382              	.LVL217:
+ 3383              	.L265:
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3384              		.loc 1 1322 5 is_stmt 0 discriminator 2 view .LVU929
+ 3385 009c 042C     		cmp	r4, #4
+ 3386 009e 06D0     		beq	.L271
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3387              		.loc 1 1322 5 discriminator 4 view .LVU930
+ 3388 00a0 082C     		cmp	r4, #8
+ 3389 00a2 09D0     		beq	.L272
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ARM GAS  /tmp/cc7KL1Mv.s 			page 121
+
+
+ 3390              		.loc 1 1322 5 discriminator 7 view .LVU931
+ 3391 00a4 0123     		movs	r3, #1
+ 3392 00a6 85F84730 		strb	r3, [r5, #71]
+ 3393 00aa 0020     		movs	r0, #0
+ 3394 00ac B1E7     		b	.L260
+ 3395              	.L271:
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3396              		.loc 1 1322 5 discriminator 3 view .LVU932
+ 3397 00ae 0123     		movs	r3, #1
+ 3398 00b0 85F84530 		strb	r3, [r5, #69]
+ 3399 00b4 0020     		movs	r0, #0
+ 3400 00b6 ACE7     		b	.L260
+ 3401              	.L272:
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3402              		.loc 1 1322 5 discriminator 6 view .LVU933
+ 3403 00b8 0123     		movs	r3, #1
+ 3404 00ba 85F84630 		strb	r3, [r5, #70]
+ 3405 00be 0020     		movs	r0, #0
+ 3406 00c0 A7E7     		b	.L260
+ 3407              		.cfi_endproc
+ 3408              	.LFE160:
+ 3410              		.section	.text.HAL_TIMEx_PWMN_Start_DMA,"ax",%progbits
+ 3411              		.align	1
+ 3412              		.global	HAL_TIMEx_PWMN_Start_DMA
+ 3413              		.syntax unified
+ 3414              		.thumb
+ 3415              		.thumb_func
+ 3416              		.fpu fpv5-d16
+ 3418              	HAL_TIMEx_PWMN_Start_DMA:
+ 3419              	.LVL218:
+ 3420              	.LFB161:
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3421              		.loc 1 1344 1 is_stmt 1 view -0
+ 3422              		.cfi_startproc
+ 3423              		@ args = 0, pretend = 0, frame = 0
+ 3424              		@ frame_needed = 0, uses_anonymous_args = 0
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3425              		.loc 1 1344 1 is_stmt 0 view .LVU935
+ 3426 0000 38B5     		push	{r3, r4, r5, lr}
+ 3427              	.LCFI24:
+ 3428              		.cfi_def_cfa_offset 16
+ 3429              		.cfi_offset 3, -16
+ 3430              		.cfi_offset 4, -12
+ 3431              		.cfi_offset 5, -8
+ 3432              		.cfi_offset 14, -4
+ 3433 0002 0446     		mov	r4, r0
+ 3434 0004 9446     		mov	ip, r2
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 3435              		.loc 1 1345 3 is_stmt 1 view .LVU936
+ 3436              	.LVL219:
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3437              		.loc 1 1346 3 view .LVU937
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3438              		.loc 1 1349 3 view .LVU938
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3439              		.loc 1 1352 3 view .LVU939
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ARM GAS  /tmp/cc7KL1Mv.s 			page 122
+
+
+ 3440              		.loc 1 1352 46 is_stmt 0 view .LVU940
+ 3441 0006 0D46     		mov	r5, r1
+ 3442 0008 51BB     		cbnz	r1, .L274
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3443              		.loc 1 1352 7 discriminator 1 view .LVU941
+ 3444 000a 90F84400 		ldrb	r0, [r0, #68]	@ zero_extendqisi2
+ 3445              	.LVL220:
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3446              		.loc 1 1352 7 discriminator 1 view .LVU942
+ 3447 000e C0B2     		uxtb	r0, r0
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3448              		.loc 1 1352 46 discriminator 1 view .LVU943
+ 3449 0010 0228     		cmp	r0, #2
+ 3450 0012 14BF     		ite	ne
+ 3451 0014 0020     		movne	r0, #0
+ 3452 0016 0120     		moveq	r0, #1
+ 3453              	.L275:
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3454              		.loc 1 1352 6 discriminator 12 view .LVU944
+ 3455 0018 0028     		cmp	r0, #0
+ 3456 001a 40F0E980 		bne	.L292
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3457              		.loc 1 1356 8 is_stmt 1 view .LVU945
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3458              		.loc 1 1356 51 is_stmt 0 view .LVU946
+ 3459 001e 002D     		cmp	r5, #0
+ 3460 0020 3AD1     		bne	.L279
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3461              		.loc 1 1356 12 discriminator 1 view .LVU947
+ 3462 0022 94F84420 		ldrb	r2, [r4, #68]	@ zero_extendqisi2
+ 3463              	.LVL221:
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3464              		.loc 1 1356 12 discriminator 1 view .LVU948
+ 3465 0026 D2B2     		uxtb	r2, r2
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3466              		.loc 1 1356 51 discriminator 1 view .LVU949
+ 3467 0028 012A     		cmp	r2, #1
+ 3468 002a 14BF     		ite	ne
+ 3469 002c 0022     		movne	r2, #0
+ 3470 002e 0122     		moveq	r2, #1
+ 3471              	.L280:
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3472              		.loc 1 1356 11 discriminator 12 view .LVU950
+ 3473 0030 002A     		cmp	r2, #0
+ 3474 0032 00F0DF80 		beq	.L293
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3475              		.loc 1 1358 5 is_stmt 1 view .LVU951
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3476              		.loc 1 1358 8 is_stmt 0 view .LVU952
+ 3477 0036 002B     		cmp	r3, #0
+ 3478 0038 18BF     		it	ne
+ 3479 003a BCF1000F 		cmpne	ip, #0
+ 3480 003e 00F0DB80 		beq	.L294
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3481              		.loc 1 1364 7 is_stmt 1 view .LVU953
+ 3482 0042 002D     		cmp	r5, #0
+ 3483 0044 44D1     		bne	.L283
+ARM GAS  /tmp/cc7KL1Mv.s 			page 123
+
+
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3484              		.loc 1 1364 7 is_stmt 0 discriminator 1 view .LVU954
+ 3485 0046 0222     		movs	r2, #2
+ 3486 0048 84F84420 		strb	r2, [r4, #68]
+ 3487              	.L284:
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3488              		.loc 1 1372 3 is_stmt 1 view .LVU955
+ 3489 004c 042D     		cmp	r5, #4
+ 3490 004e 00F09480 		beq	.L287
+ 3491 0052 082D     		cmp	r5, #8
+ 3492 0054 00F0A880 		beq	.L288
+ 3493 0058 002D     		cmp	r5, #0
+ 3494 005a 49D0     		beq	.L301
+ 3495 005c 0120     		movs	r0, #1
+ 3496 005e CAE0     		b	.L278
+ 3497              	.LVL222:
+ 3498              	.L274:
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3499              		.loc 1 1352 46 is_stmt 0 discriminator 2 view .LVU956
+ 3500 0060 0429     		cmp	r1, #4
+ 3501 0062 09D0     		beq	.L302
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3502              		.loc 1 1352 46 discriminator 5 view .LVU957
+ 3503 0064 0829     		cmp	r1, #8
+ 3504 0066 0FD0     		beq	.L303
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3505              		.loc 1 1352 7 discriminator 8 view .LVU958
+ 3506 0068 90F84700 		ldrb	r0, [r0, #71]	@ zero_extendqisi2
+ 3507              	.LVL223:
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3508              		.loc 1 1352 7 discriminator 8 view .LVU959
+ 3509 006c C0B2     		uxtb	r0, r0
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3510              		.loc 1 1352 46 discriminator 8 view .LVU960
+ 3511 006e 0228     		cmp	r0, #2
+ 3512 0070 14BF     		ite	ne
+ 3513 0072 0020     		movne	r0, #0
+ 3514 0074 0120     		moveq	r0, #1
+ 3515 0076 CFE7     		b	.L275
+ 3516              	.LVL224:
+ 3517              	.L302:
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3518              		.loc 1 1352 7 discriminator 4 view .LVU961
+ 3519 0078 90F84500 		ldrb	r0, [r0, #69]	@ zero_extendqisi2
+ 3520              	.LVL225:
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3521              		.loc 1 1352 7 discriminator 4 view .LVU962
+ 3522 007c C0B2     		uxtb	r0, r0
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3523              		.loc 1 1352 46 discriminator 4 view .LVU963
+ 3524 007e 0228     		cmp	r0, #2
+ 3525 0080 14BF     		ite	ne
+ 3526 0082 0020     		movne	r0, #0
+ 3527 0084 0120     		moveq	r0, #1
+ 3528 0086 C7E7     		b	.L275
+ 3529              	.LVL226:
+ 3530              	.L303:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 124
+
+
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3531              		.loc 1 1352 7 discriminator 7 view .LVU964
+ 3532 0088 90F84600 		ldrb	r0, [r0, #70]	@ zero_extendqisi2
+ 3533              	.LVL227:
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3534              		.loc 1 1352 7 discriminator 7 view .LVU965
+ 3535 008c C0B2     		uxtb	r0, r0
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3536              		.loc 1 1352 46 discriminator 7 view .LVU966
+ 3537 008e 0228     		cmp	r0, #2
+ 3538 0090 14BF     		ite	ne
+ 3539 0092 0020     		movne	r0, #0
+ 3540 0094 0120     		moveq	r0, #1
+ 3541 0096 BFE7     		b	.L275
+ 3542              	.L279:
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3543              		.loc 1 1356 51 discriminator 2 view .LVU967
+ 3544 0098 042D     		cmp	r5, #4
+ 3545 009a 09D0     		beq	.L304
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3546              		.loc 1 1356 51 discriminator 5 view .LVU968
+ 3547 009c 082D     		cmp	r5, #8
+ 3548 009e 0FD0     		beq	.L305
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3549              		.loc 1 1356 12 discriminator 8 view .LVU969
+ 3550 00a0 94F84720 		ldrb	r2, [r4, #71]	@ zero_extendqisi2
+ 3551              	.LVL228:
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3552              		.loc 1 1356 12 discriminator 8 view .LVU970
+ 3553 00a4 D2B2     		uxtb	r2, r2
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3554              		.loc 1 1356 51 discriminator 8 view .LVU971
+ 3555 00a6 012A     		cmp	r2, #1
+ 3556 00a8 14BF     		ite	ne
+ 3557 00aa 0022     		movne	r2, #0
+ 3558 00ac 0122     		moveq	r2, #1
+ 3559 00ae BFE7     		b	.L280
+ 3560              	.LVL229:
+ 3561              	.L304:
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3562              		.loc 1 1356 12 discriminator 4 view .LVU972
+ 3563 00b0 94F84520 		ldrb	r2, [r4, #69]	@ zero_extendqisi2
+ 3564              	.LVL230:
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3565              		.loc 1 1356 12 discriminator 4 view .LVU973
+ 3566 00b4 D2B2     		uxtb	r2, r2
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3567              		.loc 1 1356 51 discriminator 4 view .LVU974
+ 3568 00b6 012A     		cmp	r2, #1
+ 3569 00b8 14BF     		ite	ne
+ 3570 00ba 0022     		movne	r2, #0
+ 3571 00bc 0122     		moveq	r2, #1
+ 3572 00be B7E7     		b	.L280
+ 3573              	.LVL231:
+ 3574              	.L305:
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3575              		.loc 1 1356 12 discriminator 7 view .LVU975
+ARM GAS  /tmp/cc7KL1Mv.s 			page 125
+
+
+ 3576 00c0 94F84620 		ldrb	r2, [r4, #70]	@ zero_extendqisi2
+ 3577              	.LVL232:
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3578              		.loc 1 1356 12 discriminator 7 view .LVU976
+ 3579 00c4 D2B2     		uxtb	r2, r2
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3580              		.loc 1 1356 51 discriminator 7 view .LVU977
+ 3581 00c6 012A     		cmp	r2, #1
+ 3582 00c8 14BF     		ite	ne
+ 3583 00ca 0022     		movne	r2, #0
+ 3584 00cc 0122     		moveq	r2, #1
+ 3585 00ce AFE7     		b	.L280
+ 3586              	.L283:
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3587              		.loc 1 1364 7 discriminator 2 view .LVU978
+ 3588 00d0 042D     		cmp	r5, #4
+ 3589 00d2 05D0     		beq	.L306
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3590              		.loc 1 1364 7 discriminator 4 view .LVU979
+ 3591 00d4 082D     		cmp	r5, #8
+ 3592 00d6 07D0     		beq	.L307
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3593              		.loc 1 1364 7 discriminator 7 view .LVU980
+ 3594 00d8 0222     		movs	r2, #2
+ 3595 00da 84F84720 		strb	r2, [r4, #71]
+ 3596 00de B5E7     		b	.L284
+ 3597              	.L306:
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3598              		.loc 1 1364 7 discriminator 3 view .LVU981
+ 3599 00e0 0222     		movs	r2, #2
+ 3600 00e2 84F84520 		strb	r2, [r4, #69]
+ 3601 00e6 B1E7     		b	.L284
+ 3602              	.L307:
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3603              		.loc 1 1364 7 discriminator 6 view .LVU982
+ 3604 00e8 0222     		movs	r2, #2
+ 3605 00ea 84F84620 		strb	r2, [r4, #70]
+ 3606 00ee ADE7     		b	.L284
+ 3607              	.L301:
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3608              		.loc 1 1377 7 is_stmt 1 view .LVU983
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3609              		.loc 1 1377 17 is_stmt 0 view .LVU984
+ 3610 00f0 626A     		ldr	r2, [r4, #36]
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3611              		.loc 1 1377 52 view .LVU985
+ 3612 00f2 4649     		ldr	r1, .L308
+ 3613              	.LVL233:
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3614              		.loc 1 1377 52 view .LVU986
+ 3615 00f4 D163     		str	r1, [r2, #60]
+1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3616              		.loc 1 1378 7 is_stmt 1 view .LVU987
+1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3617              		.loc 1 1378 17 is_stmt 0 view .LVU988
+ 3618 00f6 626A     		ldr	r2, [r4, #36]
+1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc7KL1Mv.s 			page 126
+
+
+ 3619              		.loc 1 1378 56 view .LVU989
+ 3620 00f8 4549     		ldr	r1, .L308+4
+ 3621 00fa 1164     		str	r1, [r2, #64]
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3622              		.loc 1 1381 7 is_stmt 1 view .LVU990
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3623              		.loc 1 1381 17 is_stmt 0 view .LVU991
+ 3624 00fc 626A     		ldr	r2, [r4, #36]
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3625              		.loc 1 1381 53 view .LVU992
+ 3626 00fe 4549     		ldr	r1, .L308+8
+ 3627 0100 D164     		str	r1, [r2, #76]
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3628              		.loc 1 1384 7 is_stmt 1 view .LVU993
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3629              		.loc 1 1384 88 is_stmt 0 view .LVU994
+ 3630 0102 2268     		ldr	r2, [r4]
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3631              		.loc 1 1384 11 view .LVU995
+ 3632 0104 3432     		adds	r2, r2, #52
+ 3633 0106 6146     		mov	r1, ip
+ 3634 0108 606A     		ldr	r0, [r4, #36]
+ 3635 010a FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3636              	.LVL234:
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3637              		.loc 1 1384 10 view .LVU996
+ 3638 010e 0028     		cmp	r0, #0
+ 3639 0110 74D1     		bne	.L296
+1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3640              		.loc 1 1391 7 is_stmt 1 view .LVU997
+ 3641 0112 2268     		ldr	r2, [r4]
+ 3642 0114 D368     		ldr	r3, [r2, #12]
+ 3643 0116 43F40073 		orr	r3, r3, #512
+ 3644 011a D360     		str	r3, [r2, #12]
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3645              		.loc 1 1392 7 view .LVU998
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3646              		.loc 1 1442 3 view .LVU999
+ 3647              	.L289:
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3648              		.loc 1 1445 5 view .LVU1000
+ 3649 011c 0422     		movs	r2, #4
+ 3650 011e 2946     		mov	r1, r5
+ 3651 0120 2068     		ldr	r0, [r4]
+ 3652 0122 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 3653              	.LVL235:
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3654              		.loc 1 1448 5 view .LVU1001
+ 3655 0126 2268     		ldr	r2, [r4]
+ 3656 0128 536C     		ldr	r3, [r2, #68]
+ 3657 012a 43F40043 		orr	r3, r3, #32768
+ 3658 012e 5364     		str	r3, [r2, #68]
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3659              		.loc 1 1451 5 view .LVU1002
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3660              		.loc 1 1451 9 is_stmt 0 view .LVU1003
+ 3661 0130 2368     		ldr	r3, [r4]
+ARM GAS  /tmp/cc7KL1Mv.s 			page 127
+
+
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3662              		.loc 1 1451 8 view .LVU1004
+ 3663 0132 394A     		ldr	r2, .L308+12
+ 3664 0134 B3F1804F 		cmp	r3, #1073741824
+ 3665 0138 18BF     		it	ne
+ 3666 013a 9342     		cmpne	r3, r2
+ 3667 013c 4AD0     		beq	.L290
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3668              		.loc 1 1451 9 discriminator 1 view .LVU1005
+ 3669 013e A2F57C42 		sub	r2, r2, #64512
+ 3670 0142 9342     		cmp	r3, r2
+ 3671 0144 46D0     		beq	.L290
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3672              		.loc 1 1451 9 discriminator 2 view .LVU1006
+ 3673 0146 02F58062 		add	r2, r2, #1024
+ 3674 014a 9342     		cmp	r3, r2
+ 3675 014c 42D0     		beq	.L290
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3676              		.loc 1 1451 9 discriminator 3 view .LVU1007
+ 3677 014e 02F58062 		add	r2, r2, #1024
+ 3678 0152 9342     		cmp	r3, r2
+ 3679 0154 3ED0     		beq	.L290
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3680              		.loc 1 1451 9 discriminator 4 view .LVU1008
+ 3681 0156 02F57842 		add	r2, r2, #63488
+ 3682 015a 9342     		cmp	r3, r2
+ 3683 015c 3AD0     		beq	.L290
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3684              		.loc 1 1451 9 discriminator 5 view .LVU1009
+ 3685 015e 02F57052 		add	r2, r2, #15360
+ 3686 0162 9342     		cmp	r3, r2
+ 3687 0164 36D0     		beq	.L290
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     {
+ 3688              		.loc 1 1451 9 discriminator 6 view .LVU1010
+ 3689 0166 A2F59432 		sub	r2, r2, #75776
+ 3690 016a 9342     		cmp	r3, r2
+ 3691 016c 32D0     		beq	.L290
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3692              		.loc 1 1461 7 is_stmt 1 view .LVU1011
+ 3693 016e 1A68     		ldr	r2, [r3]
+ 3694 0170 42F00102 		orr	r2, r2, #1
+ 3695 0174 1A60     		str	r2, [r3]
+ 3696 0176 0020     		movs	r0, #0
+ 3697 0178 3DE0     		b	.L278
+ 3698              	.LVL236:
+ 3699              	.L287:
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3700              		.loc 1 1398 7 view .LVU1012
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3701              		.loc 1 1398 17 is_stmt 0 view .LVU1013
+ 3702 017a A26A     		ldr	r2, [r4, #40]
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3703              		.loc 1 1398 52 view .LVU1014
+ 3704 017c 2349     		ldr	r1, .L308
+ 3705              	.LVL237:
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3706              		.loc 1 1398 52 view .LVU1015
+ARM GAS  /tmp/cc7KL1Mv.s 			page 128
+
+
+ 3707 017e D163     		str	r1, [r2, #60]
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3708              		.loc 1 1399 7 is_stmt 1 view .LVU1016
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3709              		.loc 1 1399 17 is_stmt 0 view .LVU1017
+ 3710 0180 A26A     		ldr	r2, [r4, #40]
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3711              		.loc 1 1399 56 view .LVU1018
+ 3712 0182 2349     		ldr	r1, .L308+4
+ 3713 0184 1164     		str	r1, [r2, #64]
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3714              		.loc 1 1402 7 is_stmt 1 view .LVU1019
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3715              		.loc 1 1402 17 is_stmt 0 view .LVU1020
+ 3716 0186 A26A     		ldr	r2, [r4, #40]
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3717              		.loc 1 1402 53 view .LVU1021
+ 3718 0188 2249     		ldr	r1, .L308+8
+ 3719 018a D164     		str	r1, [r2, #76]
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3720              		.loc 1 1405 7 is_stmt 1 view .LVU1022
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3721              		.loc 1 1405 88 is_stmt 0 view .LVU1023
+ 3722 018c 2268     		ldr	r2, [r4]
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3723              		.loc 1 1405 11 view .LVU1024
+ 3724 018e 3832     		adds	r2, r2, #56
+ 3725 0190 6146     		mov	r1, ip
+ 3726 0192 A06A     		ldr	r0, [r4, #40]
+ 3727 0194 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3728              	.LVL238:
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3729              		.loc 1 1405 10 view .LVU1025
+ 3730 0198 0028     		cmp	r0, #0
+ 3731 019a 31D1     		bne	.L297
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3732              		.loc 1 1412 7 is_stmt 1 view .LVU1026
+ 3733 019c 2268     		ldr	r2, [r4]
+ 3734 019e D368     		ldr	r3, [r2, #12]
+ 3735 01a0 43F48063 		orr	r3, r3, #1024
+ 3736 01a4 D360     		str	r3, [r2, #12]
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3737              		.loc 1 1413 7 view .LVU1027
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3738              		.loc 1 1442 3 view .LVU1028
+ 3739 01a6 B9E7     		b	.L289
+ 3740              	.LVL239:
+ 3741              	.L288:
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3742              		.loc 1 1419 7 view .LVU1029
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3743              		.loc 1 1419 17 is_stmt 0 view .LVU1030
+ 3744 01a8 E26A     		ldr	r2, [r4, #44]
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3745              		.loc 1 1419 52 view .LVU1031
+ 3746 01aa 1849     		ldr	r1, .L308
+ 3747              	.LVL240:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 129
+
+
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+ 3748              		.loc 1 1419 52 view .LVU1032
+ 3749 01ac D163     		str	r1, [r2, #60]
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3750              		.loc 1 1420 7 is_stmt 1 view .LVU1033
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3751              		.loc 1 1420 17 is_stmt 0 view .LVU1034
+ 3752 01ae E26A     		ldr	r2, [r4, #44]
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3753              		.loc 1 1420 56 view .LVU1035
+ 3754 01b0 1749     		ldr	r1, .L308+4
+ 3755 01b2 1164     		str	r1, [r2, #64]
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3756              		.loc 1 1423 7 is_stmt 1 view .LVU1036
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3757              		.loc 1 1423 17 is_stmt 0 view .LVU1037
+ 3758 01b4 E26A     		ldr	r2, [r4, #44]
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3759              		.loc 1 1423 53 view .LVU1038
+ 3760 01b6 1749     		ldr	r1, .L308+8
+ 3761 01b8 D164     		str	r1, [r2, #76]
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3762              		.loc 1 1426 7 is_stmt 1 view .LVU1039
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3763              		.loc 1 1426 88 is_stmt 0 view .LVU1040
+ 3764 01ba 2268     		ldr	r2, [r4]
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3765              		.loc 1 1426 11 view .LVU1041
+ 3766 01bc 3C32     		adds	r2, r2, #60
+ 3767 01be 6146     		mov	r1, ip
+ 3768 01c0 E06A     		ldr	r0, [r4, #44]
+ 3769 01c2 FFF7FEFF 		bl	HAL_DMA_Start_IT
+ 3770              	.LVL241:
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****                            Length) != HAL_OK)
+ 3771              		.loc 1 1426 10 view .LVU1042
+ 3772 01c6 E8B9     		cbnz	r0, .L298
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3773              		.loc 1 1433 7 is_stmt 1 view .LVU1043
+ 3774 01c8 2268     		ldr	r2, [r4]
+ 3775 01ca D368     		ldr	r3, [r2, #12]
+ 3776 01cc 43F40063 		orr	r3, r3, #2048
+ 3777 01d0 D360     		str	r3, [r2, #12]
+1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3778              		.loc 1 1434 7 view .LVU1044
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3779              		.loc 1 1442 3 view .LVU1045
+ 3780 01d2 A3E7     		b	.L289
+ 3781              	.L290:
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 3782              		.loc 1 1453 7 view .LVU1046
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 3783              		.loc 1 1453 31 is_stmt 0 view .LVU1047
+ 3784 01d4 9968     		ldr	r1, [r3, #8]
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 3785              		.loc 1 1453 15 view .LVU1048
+ 3786 01d6 114A     		ldr	r2, .L308+16
+ 3787 01d8 0A40     		ands	r2, r2, r1
+ARM GAS  /tmp/cc7KL1Mv.s 			page 130
+
+
+ 3788              	.LVL242:
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 3789              		.loc 1 1454 7 is_stmt 1 view .LVU1049
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       {
+ 3790              		.loc 1 1454 10 is_stmt 0 view .LVU1050
+ 3791 01da 062A     		cmp	r2, #6
+ 3792 01dc 18BF     		it	ne
+ 3793 01de B2F5803F 		cmpne	r2, #65536
+ 3794 01e2 11D0     		beq	.L299
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 3795              		.loc 1 1456 9 is_stmt 1 view .LVU1051
+ 3796 01e4 1A68     		ldr	r2, [r3]
+ 3797              	.LVL243:
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 3798              		.loc 1 1456 9 is_stmt 0 view .LVU1052
+ 3799 01e6 42F00102 		orr	r2, r2, #1
+ 3800 01ea 1A60     		str	r2, [r3]
+ 3801 01ec 0020     		movs	r0, #0
+ 3802 01ee 02E0     		b	.L278
+ 3803              	.LVL244:
+ 3804              	.L292:
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3805              		.loc 1 1354 12 view .LVU1053
+ 3806 01f0 0220     		movs	r0, #2
+ 3807 01f2 00E0     		b	.L278
+ 3808              	.LVL245:
+ 3809              	.L293:
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3810              		.loc 1 1369 12 view .LVU1054
+ 3811 01f4 0120     		movs	r0, #1
+ 3812              	.LVL246:
+ 3813              	.L278:
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3814              		.loc 1 1467 1 view .LVU1055
+ 3815 01f6 38BD     		pop	{r3, r4, r5, pc}
+ 3816              	.LVL247:
+ 3817              	.L294:
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3818              		.loc 1 1360 14 view .LVU1056
+ 3819 01f8 0120     		movs	r0, #1
+ 3820 01fa FCE7     		b	.L278
+ 3821              	.LVL248:
+ 3822              	.L296:
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 3823              		.loc 1 1388 16 view .LVU1057
+ 3824 01fc 0120     		movs	r0, #1
+ 3825 01fe FAE7     		b	.L278
+ 3826              	.L297:
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 3827              		.loc 1 1409 16 view .LVU1058
+ 3828 0200 0120     		movs	r0, #1
+ 3829 0202 F8E7     		b	.L278
+ 3830              	.L298:
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 3831              		.loc 1 1430 16 view .LVU1059
+ 3832 0204 0120     		movs	r0, #1
+ 3833 0206 F6E7     		b	.L278
+ARM GAS  /tmp/cc7KL1Mv.s 			page 131
+
+
+ 3834              	.LVL249:
+ 3835              	.L299:
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 3836              		.loc 1 1430 16 view .LVU1060
+ 3837 0208 0020     		movs	r0, #0
+ 3838 020a F4E7     		b	.L278
+ 3839              	.L309:
+ 3840              		.align	2
+ 3841              	.L308:
+ 3842 020c 00000000 		.word	TIM_DMADelayPulseNCplt
+ 3843 0210 00000000 		.word	TIM_DMADelayPulseHalfCplt
+ 3844 0214 00000000 		.word	TIM_DMAErrorCCxN
+ 3845 0218 00000140 		.word	1073807360
+ 3846 021c 07000100 		.word	65543
+ 3847              		.cfi_endproc
+ 3848              	.LFE161:
+ 3850              		.section	.text.HAL_TIMEx_PWMN_Stop_DMA,"ax",%progbits
+ 3851              		.align	1
+ 3852              		.global	HAL_TIMEx_PWMN_Stop_DMA
+ 3853              		.syntax unified
+ 3854              		.thumb
+ 3855              		.thumb_func
+ 3856              		.fpu fpv5-d16
+ 3858              	HAL_TIMEx_PWMN_Stop_DMA:
+ 3859              	.LVL250:
+ 3860              	.LFB162:
+1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3861              		.loc 1 1481 1 is_stmt 1 view -0
+ 3862              		.cfi_startproc
+ 3863              		@ args = 0, pretend = 0, frame = 0
+ 3864              		@ frame_needed = 0, uses_anonymous_args = 0
+1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 3865              		.loc 1 1481 1 is_stmt 0 view .LVU1062
+ 3866 0000 38B5     		push	{r3, r4, r5, lr}
+ 3867              	.LCFI25:
+ 3868              		.cfi_def_cfa_offset 16
+ 3869              		.cfi_offset 3, -16
+ 3870              		.cfi_offset 4, -12
+ 3871              		.cfi_offset 5, -8
+ 3872              		.cfi_offset 14, -4
+ 3873 0002 0546     		mov	r5, r0
+ 3874 0004 0C46     		mov	r4, r1
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3875              		.loc 1 1482 3 is_stmt 1 view .LVU1063
+ 3876              	.LVL251:
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3877              		.loc 1 1485 3 view .LVU1064
+1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3878              		.loc 1 1487 3 view .LVU1065
+ 3879 0006 0429     		cmp	r1, #4
+ 3880 0008 35D0     		beq	.L311
+ 3881 000a 0829     		cmp	r1, #8
+ 3882 000c 3CD0     		beq	.L312
+ 3883 000e 09B1     		cbz	r1, .L322
+ 3884 0010 0120     		movs	r0, #1
+ 3885              	.LVL252:
+ 3886              	.L313:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 132
+
+
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 3887              		.loc 1 1534 3 view .LVU1066
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3888              		.loc 1 1535 1 is_stmt 0 view .LVU1067
+ 3889 0012 38BD     		pop	{r3, r4, r5, pc}
+ 3890              	.LVL253:
+ 3891              	.L322:
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ 3892              		.loc 1 1492 7 is_stmt 1 view .LVU1068
+ 3893 0014 0268     		ldr	r2, [r0]
+ 3894 0016 D368     		ldr	r3, [r2, #12]
+ 3895 0018 23F40073 		bic	r3, r3, #512
+ 3896 001c D360     		str	r3, [r2, #12]
+1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3897              		.loc 1 1493 7 view .LVU1069
+1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3898              		.loc 1 1493 13 is_stmt 0 view .LVU1070
+ 3899 001e 406A     		ldr	r0, [r0, #36]
+ 3900              	.LVL254:
+1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3901              		.loc 1 1493 13 view .LVU1071
+ 3902 0020 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3903              	.LVL255:
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3904              		.loc 1 1494 7 is_stmt 1 view .LVU1072
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3905              		.loc 1 1518 3 view .LVU1073
+ 3906              	.L314:
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3907              		.loc 1 1521 5 view .LVU1074
+ 3908 0024 0022     		movs	r2, #0
+ 3909 0026 2146     		mov	r1, r4
+ 3910 0028 2868     		ldr	r0, [r5]
+ 3911 002a FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 3912              	.LVL256:
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3913              		.loc 1 1524 5 view .LVU1075
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3914              		.loc 1 1524 5 view .LVU1076
+ 3915 002e 2B68     		ldr	r3, [r5]
+ 3916 0030 196A     		ldr	r1, [r3, #32]
+ 3917 0032 41F21112 		movw	r2, #4369
+ 3918 0036 1142     		tst	r1, r2
+ 3919 0038 08D1     		bne	.L315
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3920              		.loc 1 1524 5 discriminator 1 view .LVU1077
+ 3921 003a 196A     		ldr	r1, [r3, #32]
+ 3922 003c 40F24442 		movw	r2, #1092
+ 3923 0040 1142     		tst	r1, r2
+ 3924 0042 03D1     		bne	.L315
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3925              		.loc 1 1524 5 discriminator 3 view .LVU1078
+ 3926 0044 5A6C     		ldr	r2, [r3, #68]
+ 3927 0046 22F40042 		bic	r2, r2, #32768
+ 3928 004a 5A64     		str	r2, [r3, #68]
+ 3929              	.L315:
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc7KL1Mv.s 			page 133
+
+
+ 3930              		.loc 1 1524 5 discriminator 5 view .LVU1079
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3931              		.loc 1 1527 5 discriminator 5 view .LVU1080
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3932              		.loc 1 1527 5 discriminator 5 view .LVU1081
+ 3933 004c 2B68     		ldr	r3, [r5]
+ 3934 004e 196A     		ldr	r1, [r3, #32]
+ 3935 0050 41F21112 		movw	r2, #4369
+ 3936 0054 1142     		tst	r1, r2
+ 3937 0056 08D1     		bne	.L316
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3938              		.loc 1 1527 5 discriminator 1 view .LVU1082
+ 3939 0058 196A     		ldr	r1, [r3, #32]
+ 3940 005a 40F24442 		movw	r2, #1092
+ 3941 005e 1142     		tst	r1, r2
+ 3942 0060 03D1     		bne	.L316
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3943              		.loc 1 1527 5 discriminator 3 view .LVU1083
+ 3944 0062 1A68     		ldr	r2, [r3]
+ 3945 0064 22F00102 		bic	r2, r2, #1
+ 3946 0068 1A60     		str	r2, [r3]
+ 3947              	.L316:
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 3948              		.loc 1 1527 5 discriminator 5 view .LVU1084
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3949              		.loc 1 1530 5 discriminator 5 view .LVU1085
+ 3950 006a B4B9     		cbnz	r4, .L317
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3951              		.loc 1 1530 5 is_stmt 0 discriminator 1 view .LVU1086
+ 3952 006c 0123     		movs	r3, #1
+ 3953 006e 85F84430 		strb	r3, [r5, #68]
+ 3954 0072 0020     		movs	r0, #0
+ 3955 0074 CDE7     		b	.L313
+ 3956              	.LVL257:
+ 3957              	.L311:
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ 3958              		.loc 1 1500 7 is_stmt 1 view .LVU1087
+ 3959 0076 0268     		ldr	r2, [r0]
+ 3960 0078 D368     		ldr	r3, [r2, #12]
+ 3961 007a 23F48063 		bic	r3, r3, #1024
+ 3962 007e D360     		str	r3, [r2, #12]
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3963              		.loc 1 1501 7 view .LVU1088
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3964              		.loc 1 1501 13 is_stmt 0 view .LVU1089
+ 3965 0080 806A     		ldr	r0, [r0, #40]
+ 3966              	.LVL258:
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3967              		.loc 1 1501 13 view .LVU1090
+ 3968 0082 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3969              	.LVL259:
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3970              		.loc 1 1502 7 is_stmt 1 view .LVU1091
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3971              		.loc 1 1518 3 view .LVU1092
+ 3972 0086 CDE7     		b	.L314
+ 3973              	.LVL260:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 134
+
+
+ 3974              	.L312:
+1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ 3975              		.loc 1 1508 7 view .LVU1093
+ 3976 0088 0268     		ldr	r2, [r0]
+ 3977 008a D368     		ldr	r3, [r2, #12]
+ 3978 008c 23F40063 		bic	r3, r3, #2048
+ 3979 0090 D360     		str	r3, [r2, #12]
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3980              		.loc 1 1509 7 view .LVU1094
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3981              		.loc 1 1509 13 is_stmt 0 view .LVU1095
+ 3982 0092 C06A     		ldr	r0, [r0, #44]
+ 3983              	.LVL261:
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 3984              		.loc 1 1509 13 view .LVU1096
+ 3985 0094 FFF7FEFF 		bl	HAL_DMA_Abort_IT
+ 3986              	.LVL262:
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 3987              		.loc 1 1510 7 is_stmt 1 view .LVU1097
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 3988              		.loc 1 1518 3 view .LVU1098
+ 3989 0098 C4E7     		b	.L314
+ 3990              	.L317:
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3991              		.loc 1 1530 5 is_stmt 0 discriminator 2 view .LVU1099
+ 3992 009a 042C     		cmp	r4, #4
+ 3993 009c 06D0     		beq	.L323
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3994              		.loc 1 1530 5 discriminator 4 view .LVU1100
+ 3995 009e 082C     		cmp	r4, #8
+ 3996 00a0 09D0     		beq	.L324
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 3997              		.loc 1 1530 5 discriminator 7 view .LVU1101
+ 3998 00a2 0123     		movs	r3, #1
+ 3999 00a4 85F84730 		strb	r3, [r5, #71]
+ 4000 00a8 0020     		movs	r0, #0
+ 4001 00aa B2E7     		b	.L313
+ 4002              	.L323:
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4003              		.loc 1 1530 5 discriminator 3 view .LVU1102
+ 4004 00ac 0123     		movs	r3, #1
+ 4005 00ae 85F84530 		strb	r3, [r5, #69]
+ 4006 00b2 0020     		movs	r0, #0
+ 4007 00b4 ADE7     		b	.L313
+ 4008              	.L324:
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4009              		.loc 1 1530 5 discriminator 6 view .LVU1103
+ 4010 00b6 0123     		movs	r3, #1
+ 4011 00b8 85F84630 		strb	r3, [r5, #70]
+ 4012 00bc 0020     		movs	r0, #0
+ 4013 00be A8E7     		b	.L313
+ 4014              		.cfi_endproc
+ 4015              	.LFE162:
+ 4017              		.section	.text.HAL_TIMEx_OnePulseN_Start,"ax",%progbits
+ 4018              		.align	1
+ 4019              		.global	HAL_TIMEx_OnePulseN_Start
+ 4020              		.syntax unified
+ARM GAS  /tmp/cc7KL1Mv.s 			page 135
+
+
+ 4021              		.thumb
+ 4022              		.thumb_func
+ 4023              		.fpu fpv5-d16
+ 4025              	HAL_TIMEx_OnePulseN_Start:
+ 4026              	.LVL263:
+ 4027              	.LFB163:
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4028              		.loc 1 1572 1 is_stmt 1 view -0
+ 4029              		.cfi_startproc
+ 4030              		@ args = 0, pretend = 0, frame = 0
+ 4031              		@ frame_needed = 0, uses_anonymous_args = 0
+1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4032              		.loc 1 1572 1 is_stmt 0 view .LVU1105
+ 4033 0000 38B5     		push	{r3, r4, r5, lr}
+ 4034              	.LCFI26:
+ 4035              		.cfi_def_cfa_offset 16
+ 4036              		.cfi_offset 3, -16
+ 4037              		.cfi_offset 4, -12
+ 4038              		.cfi_offset 5, -8
+ 4039              		.cfi_offset 14, -4
+ 4040 0002 0446     		mov	r4, r0
+1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4041              		.loc 1 1573 3 is_stmt 1 view .LVU1106
+1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4042              		.loc 1 1573 77 is_stmt 0 view .LVU1107
+ 4043 0004 8E46     		mov	lr, r1
+ 4044 0006 91BB     		cbnz	r1, .L328
+ 4045 0008 0425     		movs	r5, #4
+ 4046              	.L326:
+ 4047              	.LVL264:
+1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4048              		.loc 1 1574 3 is_stmt 1 discriminator 4 view .LVU1108
+1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4049              		.loc 1 1574 31 is_stmt 0 discriminator 4 view .LVU1109
+ 4050 000a 94F83E00 		ldrb	r0, [r4, #62]	@ zero_extendqisi2
+ 4051              	.LVL265:
+1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4052              		.loc 1 1574 31 discriminator 4 view .LVU1110
+ 4053 000e C0B2     		uxtb	r0, r0
+ 4054              	.LVL266:
+1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4055              		.loc 1 1575 3 is_stmt 1 discriminator 4 view .LVU1111
+1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4056              		.loc 1 1575 31 is_stmt 0 discriminator 4 view .LVU1112
+ 4057 0010 94F83F20 		ldrb	r2, [r4, #63]	@ zero_extendqisi2
+ 4058 0014 D2B2     		uxtb	r2, r2
+ 4059              	.LVL267:
+1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4060              		.loc 1 1576 3 is_stmt 1 discriminator 4 view .LVU1113
+1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4061              		.loc 1 1576 31 is_stmt 0 discriminator 4 view .LVU1114
+ 4062 0016 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ 4063 001a 5FFA83FC 		uxtb	ip, r3
+ 4064              	.LVL268:
+1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4065              		.loc 1 1577 3 is_stmt 1 discriminator 4 view .LVU1115
+1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc7KL1Mv.s 			page 136
+
+
+ 4066              		.loc 1 1577 31 is_stmt 0 discriminator 4 view .LVU1116
+ 4067 001e 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 4068 0022 DBB2     		uxtb	r3, r3
+ 4069              	.LVL269:
+1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4070              		.loc 1 1580 3 is_stmt 1 discriminator 4 view .LVU1117
+1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 4071              		.loc 1 1583 3 discriminator 4 view .LVU1118
+1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 4072              		.loc 1 1583 6 is_stmt 0 discriminator 4 view .LVU1119
+ 4073 0024 012A     		cmp	r2, #1
+ 4074 0026 08BF     		it	eq
+ 4075 0028 0128     		cmpeq	r0, #1
+ 4076 002a 22D1     		bne	.L329
+1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4077              		.loc 1 1586 41 view .LVU1120
+ 4078 002c 013B     		subs	r3, r3, #1
+ 4079              	.LVL270:
+1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4080              		.loc 1 1586 41 view .LVU1121
+ 4081 002e 18BF     		it	ne
+ 4082 0030 0123     		movne	r3, #1
+ 4083              	.LVL271:
+1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4084              		.loc 1 1586 7 view .LVU1122
+ 4085 0032 BCF1010F 		cmp	ip, #1
+ 4086 0036 1ED1     		bne	.L330
+ 4087 0038 EBB9     		cbnz	r3, .L330
+1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4088              		.loc 1 1592 3 is_stmt 1 view .LVU1123
+ 4089 003a 0223     		movs	r3, #2
+ 4090 003c 84F83E30 		strb	r3, [r4, #62]
+1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4091              		.loc 1 1593 3 view .LVU1124
+ 4092 0040 84F83F30 		strb	r3, [r4, #63]
+1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4093              		.loc 1 1594 3 view .LVU1125
+ 4094 0044 84F84430 		strb	r3, [r4, #68]
+1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4095              		.loc 1 1595 3 view .LVU1126
+ 4096 0048 84F84530 		strb	r3, [r4, #69]
+1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4097              		.loc 1 1598 3 view .LVU1127
+ 4098 004c 0422     		movs	r2, #4
+ 4099              	.LVL272:
+1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4100              		.loc 1 1598 3 is_stmt 0 view .LVU1128
+ 4101 004e 7146     		mov	r1, lr
+ 4102              	.LVL273:
+1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4103              		.loc 1 1598 3 view .LVU1129
+ 4104 0050 2068     		ldr	r0, [r4]
+ 4105              	.LVL274:
+1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4106              		.loc 1 1598 3 view .LVU1130
+ 4107 0052 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 4108              	.LVL275:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 137
+
+
+1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4109              		.loc 1 1599 3 is_stmt 1 view .LVU1131
+ 4110 0056 0122     		movs	r2, #1
+ 4111 0058 2946     		mov	r1, r5
+ 4112 005a 2068     		ldr	r0, [r4]
+ 4113 005c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 4114              	.LVL276:
+1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4115              		.loc 1 1602 3 view .LVU1132
+ 4116 0060 2268     		ldr	r2, [r4]
+ 4117 0062 536C     		ldr	r3, [r2, #68]
+ 4118 0064 43F40043 		orr	r3, r3, #32768
+ 4119 0068 5364     		str	r3, [r2, #68]
+1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 4120              		.loc 1 1605 3 view .LVU1133
+1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 4121              		.loc 1 1605 10 is_stmt 0 view .LVU1134
+ 4122 006a 0020     		movs	r0, #0
+ 4123 006c 02E0     		b	.L327
+ 4124              	.LVL277:
+ 4125              	.L328:
+1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4126              		.loc 1 1573 77 view .LVU1135
+ 4127 006e 0025     		movs	r5, #0
+ 4128 0070 CBE7     		b	.L326
+ 4129              	.LVL278:
+ 4130              	.L329:
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4131              		.loc 1 1588 12 view .LVU1136
+ 4132 0072 0120     		movs	r0, #1
+ 4133              	.LVL279:
+ 4134              	.L327:
+1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4135              		.loc 1 1606 1 view .LVU1137
+ 4136 0074 38BD     		pop	{r3, r4, r5, pc}
+ 4137              	.LVL280:
+ 4138              	.L330:
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4139              		.loc 1 1588 12 view .LVU1138
+ 4140 0076 0120     		movs	r0, #1
+ 4141              	.LVL281:
+1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4142              		.loc 1 1588 12 view .LVU1139
+ 4143 0078 FCE7     		b	.L327
+ 4144              		.cfi_endproc
+ 4145              	.LFE163:
+ 4147              		.section	.text.HAL_TIMEx_OnePulseN_Stop,"ax",%progbits
+ 4148              		.align	1
+ 4149              		.global	HAL_TIMEx_OnePulseN_Stop
+ 4150              		.syntax unified
+ 4151              		.thumb
+ 4152              		.thumb_func
+ 4153              		.fpu fpv5-d16
+ 4155              	HAL_TIMEx_OnePulseN_Stop:
+ 4156              	.LVL282:
+ 4157              	.LFB164:
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ARM GAS  /tmp/cc7KL1Mv.s 			page 138
+
+
+ 4158              		.loc 1 1621 1 is_stmt 1 view -0
+ 4159              		.cfi_startproc
+ 4160              		@ args = 0, pretend = 0, frame = 0
+ 4161              		@ frame_needed = 0, uses_anonymous_args = 0
+1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4162              		.loc 1 1621 1 is_stmt 0 view .LVU1141
+ 4163 0000 38B5     		push	{r3, r4, r5, lr}
+ 4164              	.LCFI27:
+ 4165              		.cfi_def_cfa_offset 16
+ 4166              		.cfi_offset 3, -16
+ 4167              		.cfi_offset 4, -12
+ 4168              		.cfi_offset 5, -8
+ 4169              		.cfi_offset 14, -4
+ 4170 0002 0446     		mov	r4, r0
+1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4171              		.loc 1 1622 3 is_stmt 1 view .LVU1142
+1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4172              		.loc 1 1622 77 is_stmt 0 view .LVU1143
+ 4173 0004 0029     		cmp	r1, #0
+ 4174 0006 32D1     		bne	.L336
+ 4175 0008 0425     		movs	r5, #4
+ 4176              	.L333:
+ 4177              	.LVL283:
+1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4178              		.loc 1 1625 3 is_stmt 1 discriminator 4 view .LVU1144
+1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+ 4179              		.loc 1 1628 3 discriminator 4 view .LVU1145
+ 4180 000a 0022     		movs	r2, #0
+ 4181 000c 2068     		ldr	r0, [r4]
+ 4182              	.LVL284:
+1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+ 4183              		.loc 1 1628 3 is_stmt 0 discriminator 4 view .LVU1146
+ 4184 000e FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 4185              	.LVL285:
+1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4186              		.loc 1 1629 3 is_stmt 1 discriminator 4 view .LVU1147
+ 4187 0012 0022     		movs	r2, #0
+ 4188 0014 2946     		mov	r1, r5
+ 4189 0016 2068     		ldr	r0, [r4]
+ 4190 0018 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 4191              	.LVL286:
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4192              		.loc 1 1632 3 discriminator 4 view .LVU1148
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4193              		.loc 1 1632 3 discriminator 4 view .LVU1149
+ 4194 001c 2368     		ldr	r3, [r4]
+ 4195 001e 196A     		ldr	r1, [r3, #32]
+ 4196 0020 41F21112 		movw	r2, #4369
+ 4197 0024 1142     		tst	r1, r2
+ 4198 0026 08D1     		bne	.L334
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4199              		.loc 1 1632 3 discriminator 1 view .LVU1150
+ 4200 0028 196A     		ldr	r1, [r3, #32]
+ 4201 002a 40F24442 		movw	r2, #1092
+ 4202 002e 1142     		tst	r1, r2
+ 4203 0030 03D1     		bne	.L334
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc7KL1Mv.s 			page 139
+
+
+ 4204              		.loc 1 1632 3 discriminator 3 view .LVU1151
+ 4205 0032 5A6C     		ldr	r2, [r3, #68]
+ 4206 0034 22F40042 		bic	r2, r2, #32768
+ 4207 0038 5A64     		str	r2, [r3, #68]
+ 4208              	.L334:
+1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4209              		.loc 1 1632 3 discriminator 5 view .LVU1152
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4210              		.loc 1 1635 3 discriminator 5 view .LVU1153
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4211              		.loc 1 1635 3 discriminator 5 view .LVU1154
+ 4212 003a 2368     		ldr	r3, [r4]
+ 4213 003c 196A     		ldr	r1, [r3, #32]
+ 4214 003e 41F21112 		movw	r2, #4369
+ 4215 0042 1142     		tst	r1, r2
+ 4216 0044 08D1     		bne	.L335
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4217              		.loc 1 1635 3 discriminator 1 view .LVU1155
+ 4218 0046 196A     		ldr	r1, [r3, #32]
+ 4219 0048 40F24442 		movw	r2, #1092
+ 4220 004c 1142     		tst	r1, r2
+ 4221 004e 03D1     		bne	.L335
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4222              		.loc 1 1635 3 discriminator 3 view .LVU1156
+ 4223 0050 1A68     		ldr	r2, [r3]
+ 4224 0052 22F00102 		bic	r2, r2, #1
+ 4225 0056 1A60     		str	r2, [r3]
+ 4226              	.L335:
+1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4227              		.loc 1 1635 3 discriminator 5 view .LVU1157
+1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 4228              		.loc 1 1638 3 discriminator 5 view .LVU1158
+ 4229 0058 0123     		movs	r3, #1
+ 4230 005a 84F83E30 		strb	r3, [r4, #62]
+1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 4231              		.loc 1 1639 3 discriminator 5 view .LVU1159
+ 4232 005e 84F83F30 		strb	r3, [r4, #63]
+1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 4233              		.loc 1 1640 3 discriminator 5 view .LVU1160
+ 4234 0062 84F84430 		strb	r3, [r4, #68]
+1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4235              		.loc 1 1641 3 discriminator 5 view .LVU1161
+ 4236 0066 84F84530 		strb	r3, [r4, #69]
+1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 4237              		.loc 1 1644 3 discriminator 5 view .LVU1162
+1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4238              		.loc 1 1645 1 is_stmt 0 discriminator 5 view .LVU1163
+ 4239 006a 0020     		movs	r0, #0
+ 4240 006c 38BD     		pop	{r3, r4, r5, pc}
+ 4241              	.LVL287:
+ 4242              	.L336:
+1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4243              		.loc 1 1622 77 view .LVU1164
+ 4244 006e 0025     		movs	r5, #0
+ 4245 0070 CBE7     		b	.L333
+ 4246              		.cfi_endproc
+ 4247              	.LFE164:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 140
+
+
+ 4249              		.section	.text.HAL_TIMEx_OnePulseN_Start_IT,"ax",%progbits
+ 4250              		.align	1
+ 4251              		.global	HAL_TIMEx_OnePulseN_Start_IT
+ 4252              		.syntax unified
+ 4253              		.thumb
+ 4254              		.thumb_func
+ 4255              		.fpu fpv5-d16
+ 4257              	HAL_TIMEx_OnePulseN_Start_IT:
+ 4258              	.LVL288:
+ 4259              	.LFB165:
+1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4260              		.loc 1 1660 1 is_stmt 1 view -0
+ 4261              		.cfi_startproc
+ 4262              		@ args = 0, pretend = 0, frame = 0
+ 4263              		@ frame_needed = 0, uses_anonymous_args = 0
+1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4264              		.loc 1 1660 1 is_stmt 0 view .LVU1166
+ 4265 0000 38B5     		push	{r3, r4, r5, lr}
+ 4266              	.LCFI28:
+ 4267              		.cfi_def_cfa_offset 16
+ 4268              		.cfi_offset 3, -16
+ 4269              		.cfi_offset 4, -12
+ 4270              		.cfi_offset 5, -8
+ 4271              		.cfi_offset 14, -4
+ 4272 0002 0446     		mov	r4, r0
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4273              		.loc 1 1661 3 is_stmt 1 view .LVU1167
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4274              		.loc 1 1661 77 is_stmt 0 view .LVU1168
+ 4275 0004 8E46     		mov	lr, r1
+ 4276 0006 0029     		cmp	r1, #0
+ 4277 0008 3CD1     		bne	.L341
+ 4278 000a 0425     		movs	r5, #4
+ 4279              	.L339:
+ 4280              	.LVL289:
+1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4281              		.loc 1 1662 3 is_stmt 1 discriminator 4 view .LVU1169
+1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4282              		.loc 1 1662 31 is_stmt 0 discriminator 4 view .LVU1170
+ 4283 000c 94F83E00 		ldrb	r0, [r4, #62]	@ zero_extendqisi2
+ 4284              	.LVL290:
+1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 4285              		.loc 1 1662 31 discriminator 4 view .LVU1171
+ 4286 0010 C0B2     		uxtb	r0, r0
+ 4287              	.LVL291:
+1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4288              		.loc 1 1663 3 is_stmt 1 discriminator 4 view .LVU1172
+1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4289              		.loc 1 1663 31 is_stmt 0 discriminator 4 view .LVU1173
+ 4290 0012 94F83F20 		ldrb	r2, [r4, #63]	@ zero_extendqisi2
+ 4291 0016 D2B2     		uxtb	r2, r2
+ 4292              	.LVL292:
+1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4293              		.loc 1 1664 3 is_stmt 1 discriminator 4 view .LVU1174
+1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA
+ 4294              		.loc 1 1664 31 is_stmt 0 discriminator 4 view .LVU1175
+ 4295 0018 94F84430 		ldrb	r3, [r4, #68]	@ zero_extendqisi2
+ARM GAS  /tmp/cc7KL1Mv.s 			page 141
+
+
+ 4296 001c 5FFA83FC 		uxtb	ip, r3
+ 4297              	.LVL293:
+1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4298              		.loc 1 1665 3 is_stmt 1 discriminator 4 view .LVU1176
+1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4299              		.loc 1 1665 31 is_stmt 0 discriminator 4 view .LVU1177
+ 4300 0020 94F84530 		ldrb	r3, [r4, #69]	@ zero_extendqisi2
+ 4301 0024 DBB2     		uxtb	r3, r3
+ 4302              	.LVL294:
+1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4303              		.loc 1 1668 3 is_stmt 1 discriminator 4 view .LVU1178
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 4304              		.loc 1 1671 3 discriminator 4 view .LVU1179
+1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 4305              		.loc 1 1671 6 is_stmt 0 discriminator 4 view .LVU1180
+ 4306 0026 012A     		cmp	r2, #1
+ 4307 0028 08BF     		it	eq
+ 4308 002a 0128     		cmpeq	r0, #1
+ 4309 002c 2CD1     		bne	.L342
+1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4310              		.loc 1 1674 41 view .LVU1181
+ 4311 002e 013B     		subs	r3, r3, #1
+ 4312              	.LVL295:
+1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4313              		.loc 1 1674 41 view .LVU1182
+ 4314 0030 18BF     		it	ne
+ 4315 0032 0123     		movne	r3, #1
+ 4316              	.LVL296:
+1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4317              		.loc 1 1674 7 view .LVU1183
+ 4318 0034 BCF1010F 		cmp	ip, #1
+ 4319 0038 28D1     		bne	.L343
+ 4320 003a 3BBB     		cbnz	r3, .L343
+1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4321              		.loc 1 1680 3 is_stmt 1 view .LVU1184
+ 4322 003c 0223     		movs	r3, #2
+ 4323 003e 84F83E30 		strb	r3, [r4, #62]
+1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4324              		.loc 1 1681 3 view .LVU1185
+ 4325 0042 84F83F30 		strb	r3, [r4, #63]
+1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 4326              		.loc 1 1682 3 view .LVU1186
+ 4327 0046 84F84430 		strb	r3, [r4, #68]
+1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4328              		.loc 1 1683 3 view .LVU1187
+ 4329 004a 84F84530 		strb	r3, [r4, #69]
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4330              		.loc 1 1686 3 view .LVU1188
+ 4331 004e 2268     		ldr	r2, [r4]
+ 4332              	.LVL297:
+1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4333              		.loc 1 1686 3 is_stmt 0 view .LVU1189
+ 4334 0050 D368     		ldr	r3, [r2, #12]
+ 4335 0052 43F00203 		orr	r3, r3, #2
+ 4336 0056 D360     		str	r3, [r2, #12]
+1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4337              		.loc 1 1689 3 is_stmt 1 view .LVU1190
+ARM GAS  /tmp/cc7KL1Mv.s 			page 142
+
+
+ 4338 0058 2268     		ldr	r2, [r4]
+ 4339 005a D368     		ldr	r3, [r2, #12]
+ 4340 005c 43F00403 		orr	r3, r3, #4
+ 4341 0060 D360     		str	r3, [r2, #12]
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4342              		.loc 1 1692 3 view .LVU1191
+ 4343 0062 0422     		movs	r2, #4
+ 4344 0064 7146     		mov	r1, lr
+ 4345              	.LVL298:
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4346              		.loc 1 1692 3 is_stmt 0 view .LVU1192
+ 4347 0066 2068     		ldr	r0, [r4]
+ 4348              	.LVL299:
+1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+ 4349              		.loc 1 1692 3 view .LVU1193
+ 4350 0068 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 4351              	.LVL300:
+1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4352              		.loc 1 1693 3 is_stmt 1 view .LVU1194
+ 4353 006c 0122     		movs	r2, #1
+ 4354 006e 2946     		mov	r1, r5
+ 4355 0070 2068     		ldr	r0, [r4]
+ 4356 0072 FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 4357              	.LVL301:
+1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4358              		.loc 1 1696 3 view .LVU1195
+ 4359 0076 2268     		ldr	r2, [r4]
+ 4360 0078 536C     		ldr	r3, [r2, #68]
+ 4361 007a 43F40043 		orr	r3, r3, #32768
+ 4362 007e 5364     		str	r3, [r2, #68]
+1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 4363              		.loc 1 1699 3 view .LVU1196
+1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 4364              		.loc 1 1699 10 is_stmt 0 view .LVU1197
+ 4365 0080 0020     		movs	r0, #0
+ 4366 0082 02E0     		b	.L340
+ 4367              	.LVL302:
+ 4368              	.L341:
+1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 4369              		.loc 1 1661 77 view .LVU1198
+ 4370 0084 0025     		movs	r5, #0
+ 4371 0086 C1E7     		b	.L339
+ 4372              	.LVL303:
+ 4373              	.L342:
+1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4374              		.loc 1 1676 12 view .LVU1199
+ 4375 0088 0120     		movs	r0, #1
+ 4376              	.LVL304:
+ 4377              	.L340:
+1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4378              		.loc 1 1700 1 view .LVU1200
+ 4379 008a 38BD     		pop	{r3, r4, r5, pc}
+ 4380              	.LVL305:
+ 4381              	.L343:
+1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4382              		.loc 1 1676 12 view .LVU1201
+ 4383 008c 0120     		movs	r0, #1
+ARM GAS  /tmp/cc7KL1Mv.s 			page 143
+
+
+ 4384              	.LVL306:
+1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4385              		.loc 1 1676 12 view .LVU1202
+ 4386 008e FCE7     		b	.L340
+ 4387              		.cfi_endproc
+ 4388              	.LFE165:
+ 4390              		.section	.text.HAL_TIMEx_OnePulseN_Stop_IT,"ax",%progbits
+ 4391              		.align	1
+ 4392              		.global	HAL_TIMEx_OnePulseN_Stop_IT
+ 4393              		.syntax unified
+ 4394              		.thumb
+ 4395              		.thumb_func
+ 4396              		.fpu fpv5-d16
+ 4398              	HAL_TIMEx_OnePulseN_Stop_IT:
+ 4399              	.LVL307:
+ 4400              	.LFB166:
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4401              		.loc 1 1715 1 is_stmt 1 view -0
+ 4402              		.cfi_startproc
+ 4403              		@ args = 0, pretend = 0, frame = 0
+ 4404              		@ frame_needed = 0, uses_anonymous_args = 0
+1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ 4405              		.loc 1 1715 1 is_stmt 0 view .LVU1204
+ 4406 0000 38B5     		push	{r3, r4, r5, lr}
+ 4407              	.LCFI29:
+ 4408              		.cfi_def_cfa_offset 16
+ 4409              		.cfi_offset 3, -16
+ 4410              		.cfi_offset 4, -12
+ 4411              		.cfi_offset 5, -8
+ 4412              		.cfi_offset 14, -4
+ 4413 0002 0446     		mov	r4, r0
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4414              		.loc 1 1716 3 is_stmt 1 view .LVU1205
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4415              		.loc 1 1716 77 is_stmt 0 view .LVU1206
+ 4416 0004 0029     		cmp	r1, #0
+ 4417 0006 3CD1     		bne	.L349
+ 4418 0008 0425     		movs	r5, #4
+ 4419              	.L346:
+ 4420              	.LVL308:
+1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4421              		.loc 1 1719 3 is_stmt 1 discriminator 4 view .LVU1207
+1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4422              		.loc 1 1722 3 discriminator 4 view .LVU1208
+ 4423 000a 2268     		ldr	r2, [r4]
+ 4424 000c D368     		ldr	r3, [r2, #12]
+ 4425 000e 23F00203 		bic	r3, r3, #2
+ 4426 0012 D360     		str	r3, [r2, #12]
+1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4427              		.loc 1 1725 3 discriminator 4 view .LVU1209
+ 4428 0014 2268     		ldr	r2, [r4]
+ 4429 0016 D368     		ldr	r3, [r2, #12]
+ 4430 0018 23F00403 		bic	r3, r3, #4
+ 4431 001c D360     		str	r3, [r2, #12]
+1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+ 4432              		.loc 1 1728 3 discriminator 4 view .LVU1210
+ 4433 001e 0022     		movs	r2, #0
+ARM GAS  /tmp/cc7KL1Mv.s 			page 144
+
+
+ 4434 0020 2068     		ldr	r0, [r4]
+ 4435              	.LVL309:
+1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+ 4436              		.loc 1 1728 3 is_stmt 0 discriminator 4 view .LVU1211
+ 4437 0022 FFF7FEFF 		bl	TIM_CCxNChannelCmd
+ 4438              	.LVL310:
+1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4439              		.loc 1 1729 3 is_stmt 1 discriminator 4 view .LVU1212
+ 4440 0026 0022     		movs	r2, #0
+ 4441 0028 2946     		mov	r1, r5
+ 4442 002a 2068     		ldr	r0, [r4]
+ 4443 002c FFF7FEFF 		bl	TIM_CCxChannelCmd
+ 4444              	.LVL311:
+1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4445              		.loc 1 1732 3 discriminator 4 view .LVU1213
+1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4446              		.loc 1 1732 3 discriminator 4 view .LVU1214
+ 4447 0030 2368     		ldr	r3, [r4]
+ 4448 0032 196A     		ldr	r1, [r3, #32]
+ 4449 0034 41F21112 		movw	r2, #4369
+ 4450 0038 1142     		tst	r1, r2
+ 4451 003a 08D1     		bne	.L347
+1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4452              		.loc 1 1732 3 discriminator 1 view .LVU1215
+ 4453 003c 196A     		ldr	r1, [r3, #32]
+ 4454 003e 40F24442 		movw	r2, #1092
+ 4455 0042 1142     		tst	r1, r2
+ 4456 0044 03D1     		bne	.L347
+1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4457              		.loc 1 1732 3 discriminator 3 view .LVU1216
+ 4458 0046 5A6C     		ldr	r2, [r3, #68]
+ 4459 0048 22F40042 		bic	r2, r2, #32768
+ 4460 004c 5A64     		str	r2, [r3, #68]
+ 4461              	.L347:
+1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4462              		.loc 1 1732 3 discriminator 5 view .LVU1217
+1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4463              		.loc 1 1735 3 discriminator 5 view .LVU1218
+1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4464              		.loc 1 1735 3 discriminator 5 view .LVU1219
+ 4465 004e 2368     		ldr	r3, [r4]
+ 4466 0050 196A     		ldr	r1, [r3, #32]
+ 4467 0052 41F21112 		movw	r2, #4369
+ 4468 0056 1142     		tst	r1, r2
+ 4469 0058 08D1     		bne	.L348
+1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4470              		.loc 1 1735 3 discriminator 1 view .LVU1220
+ 4471 005a 196A     		ldr	r1, [r3, #32]
+ 4472 005c 40F24442 		movw	r2, #1092
+ 4473 0060 1142     		tst	r1, r2
+ 4474 0062 03D1     		bne	.L348
+1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4475              		.loc 1 1735 3 discriminator 3 view .LVU1221
+ 4476 0064 1A68     		ldr	r2, [r3]
+ 4477 0066 22F00102 		bic	r2, r2, #1
+ 4478 006a 1A60     		str	r2, [r3]
+ 4479              	.L348:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 145
+
+
+1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4480              		.loc 1 1735 3 discriminator 5 view .LVU1222
+1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 4481              		.loc 1 1738 3 discriminator 5 view .LVU1223
+ 4482 006c 0123     		movs	r3, #1
+ 4483 006e 84F83E30 		strb	r3, [r4, #62]
+1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 4484              		.loc 1 1739 3 discriminator 5 view .LVU1224
+ 4485 0072 84F83F30 		strb	r3, [r4, #63]
+1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 4486              		.loc 1 1740 3 discriminator 5 view .LVU1225
+ 4487 0076 84F84430 		strb	r3, [r4, #68]
+1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4488              		.loc 1 1741 3 discriminator 5 view .LVU1226
+ 4489 007a 84F84530 		strb	r3, [r4, #69]
+1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 4490              		.loc 1 1744 3 discriminator 5 view .LVU1227
+1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4491              		.loc 1 1745 1 is_stmt 0 discriminator 5 view .LVU1228
+ 4492 007e 0020     		movs	r0, #0
+ 4493 0080 38BD     		pop	{r3, r4, r5, pc}
+ 4494              	.LVL312:
+ 4495              	.L349:
+1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4496              		.loc 1 1716 77 view .LVU1229
+ 4497 0082 0025     		movs	r5, #0
+ 4498 0084 C1E7     		b	.L346
+ 4499              		.cfi_endproc
+ 4500              	.LFE166:
+ 4502              		.section	.text.HAL_TIMEx_ConfigCommutEvent,"ax",%progbits
+ 4503              		.align	1
+ 4504              		.global	HAL_TIMEx_ConfigCommutEvent
+ 4505              		.syntax unified
+ 4506              		.thumb
+ 4507              		.thumb_func
+ 4508              		.fpu fpv5-d16
+ 4510              	HAL_TIMEx_ConfigCommutEvent:
+ 4511              	.LVL313:
+ 4512              	.LFB167:
+1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 4513              		.loc 1 1796 1 is_stmt 1 view -0
+ 4514              		.cfi_startproc
+ 4515              		@ args = 0, pretend = 0, frame = 0
+ 4516              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4517              		@ link register save eliminated.
+1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+ 4518              		.loc 1 1798 3 view .LVU1231
+1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4519              		.loc 1 1799 3 view .LVU1232
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4520              		.loc 1 1801 3 view .LVU1233
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4521              		.loc 1 1801 3 view .LVU1234
+ 4522 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 4523 0004 012B     		cmp	r3, #1
+ 4524 0006 36D0     		beq	.L356
+1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ARM GAS  /tmp/cc7KL1Mv.s 			page 146
+
+
+ 4525              		.loc 1 1796 1 is_stmt 0 discriminator 2 view .LVU1235
+ 4526 0008 10B4     		push	{r4}
+ 4527              	.LCFI30:
+ 4528              		.cfi_def_cfa_offset 4
+ 4529              		.cfi_offset 4, -4
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4530              		.loc 1 1801 3 is_stmt 1 discriminator 2 view .LVU1236
+ 4531 000a 0123     		movs	r3, #1
+ 4532 000c 80F83C30 		strb	r3, [r0, #60]
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4533              		.loc 1 1801 3 discriminator 2 view .LVU1237
+1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ 4534              		.loc 1 1803 3 discriminator 2 view .LVU1238
+1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ 4535              		.loc 1 1803 6 is_stmt 0 discriminator 2 view .LVU1239
+ 4536 0010 1029     		cmp	r1, #16
+ 4537 0012 18BF     		it	ne
+ 4538 0014 0029     		cmpne	r1, #0
+ 4539 0016 06D0     		beq	.L353
+1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4540              		.loc 1 1804 54 view .LVU1240
+ 4541 0018 3029     		cmp	r1, #48
+ 4542 001a 14BF     		ite	ne
+ 4543 001c 0023     		movne	r3, #0
+ 4544 001e 0123     		moveq	r3, #1
+1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4545              		.loc 1 1804 37 view .LVU1241
+ 4546 0020 2029     		cmp	r1, #32
+ 4547 0022 00D0     		beq	.L353
+ 4548 0024 43B1     		cbz	r3, .L354
+ 4549              	.L353:
+1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4550              		.loc 1 1807 5 is_stmt 1 view .LVU1242
+1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4551              		.loc 1 1807 9 is_stmt 0 view .LVU1243
+ 4552 0026 0468     		ldr	r4, [r0]
+1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4553              		.loc 1 1807 26 view .LVU1244
+ 4554 0028 A368     		ldr	r3, [r4, #8]
+ 4555 002a 23F07003 		bic	r3, r3, #112
+ 4556 002e A360     		str	r3, [r4, #8]
+1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4557              		.loc 1 1808 5 is_stmt 1 view .LVU1245
+1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4558              		.loc 1 1808 9 is_stmt 0 view .LVU1246
+ 4559 0030 0468     		ldr	r4, [r0]
+1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4560              		.loc 1 1808 26 view .LVU1247
+ 4561 0032 A368     		ldr	r3, [r4, #8]
+ 4562 0034 1943     		orrs	r1, r1, r3
+ 4563              	.LVL314:
+1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4564              		.loc 1 1808 26 view .LVU1248
+ 4565 0036 A160     		str	r1, [r4, #8]
+ 4566              	.L354:
+1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4567              		.loc 1 1812 3 is_stmt 1 view .LVU1249
+ARM GAS  /tmp/cc7KL1Mv.s 			page 147
+
+
+1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4568              		.loc 1 1812 7 is_stmt 0 view .LVU1250
+ 4569 0038 0168     		ldr	r1, [r0]
+1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4570              		.loc 1 1812 23 view .LVU1251
+ 4571 003a 4B68     		ldr	r3, [r1, #4]
+ 4572 003c 43F00103 		orr	r3, r3, #1
+ 4573 0040 4B60     		str	r3, [r1, #4]
+1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4574              		.loc 1 1814 3 is_stmt 1 view .LVU1252
+1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4575              		.loc 1 1814 7 is_stmt 0 view .LVU1253
+ 4576 0042 0168     		ldr	r1, [r0]
+1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4577              		.loc 1 1814 23 view .LVU1254
+ 4578 0044 4B68     		ldr	r3, [r1, #4]
+ 4579 0046 23F00403 		bic	r3, r3, #4
+ 4580 004a 4B60     		str	r3, [r1, #4]
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4581              		.loc 1 1815 3 is_stmt 1 view .LVU1255
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4582              		.loc 1 1815 7 is_stmt 0 view .LVU1256
+ 4583 004c 0168     		ldr	r1, [r0]
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4584              		.loc 1 1815 23 view .LVU1257
+ 4585 004e 4B68     		ldr	r3, [r1, #4]
+ 4586 0050 1A43     		orrs	r2, r2, r3
+ 4587              	.LVL315:
+1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4588              		.loc 1 1815 23 view .LVU1258
+ 4589 0052 4A60     		str	r2, [r1, #4]
+1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4590              		.loc 1 1818 3 is_stmt 1 view .LVU1259
+ 4591 0054 0268     		ldr	r2, [r0]
+ 4592 0056 D368     		ldr	r3, [r2, #12]
+ 4593 0058 23F02003 		bic	r3, r3, #32
+ 4594 005c D360     		str	r3, [r2, #12]
+1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4595              		.loc 1 1821 3 view .LVU1260
+ 4596 005e 0268     		ldr	r2, [r0]
+ 4597 0060 D368     		ldr	r3, [r2, #12]
+ 4598 0062 23F40053 		bic	r3, r3, #8192
+ 4599 0066 D360     		str	r3, [r2, #12]
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4600              		.loc 1 1823 3 view .LVU1261
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4601              		.loc 1 1823 3 view .LVU1262
+ 4602 0068 0023     		movs	r3, #0
+ 4603 006a 80F83C30 		strb	r3, [r0, #60]
+1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4604              		.loc 1 1823 3 view .LVU1263
+1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 4605              		.loc 1 1825 3 view .LVU1264
+1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 4606              		.loc 1 1825 10 is_stmt 0 view .LVU1265
+ 4607 006e 1846     		mov	r0, r3
+ 4608              	.LVL316:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 148
+
+
+1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4609              		.loc 1 1826 1 view .LVU1266
+ 4610 0070 5DF8044B 		ldr	r4, [sp], #4
+ 4611              	.LCFI31:
+ 4612              		.cfi_restore 4
+ 4613              		.cfi_def_cfa_offset 0
+ 4614 0074 7047     		bx	lr
+ 4615              	.LVL317:
+ 4616              	.L356:
+1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4617              		.loc 1 1801 3 view .LVU1267
+ 4618 0076 0220     		movs	r0, #2
+ 4619              	.LVL318:
+1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4620              		.loc 1 1826 1 view .LVU1268
+ 4621 0078 7047     		bx	lr
+ 4622              		.cfi_endproc
+ 4623              	.LFE167:
+ 4625              		.section	.text.HAL_TIMEx_ConfigCommutEvent_IT,"ax",%progbits
+ 4626              		.align	1
+ 4627              		.global	HAL_TIMEx_ConfigCommutEvent_IT
+ 4628              		.syntax unified
+ 4629              		.thumb
+ 4630              		.thumb_func
+ 4631              		.fpu fpv5-d16
+ 4633              	HAL_TIMEx_ConfigCommutEvent_IT:
+ 4634              	.LVL319:
+ 4635              	.LFB168:
+1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 4636              		.loc 1 1852 1 is_stmt 1 view -0
+ 4637              		.cfi_startproc
+ 4638              		@ args = 0, pretend = 0, frame = 0
+ 4639              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4640              		@ link register save eliminated.
+1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+ 4641              		.loc 1 1854 3 view .LVU1270
+1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4642              		.loc 1 1855 3 view .LVU1271
+1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4643              		.loc 1 1857 3 view .LVU1272
+1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4644              		.loc 1 1857 3 view .LVU1273
+ 4645 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 4646 0004 012B     		cmp	r3, #1
+ 4647 0006 36D0     		beq	.L366
+1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 4648              		.loc 1 1852 1 is_stmt 0 discriminator 2 view .LVU1274
+ 4649 0008 10B4     		push	{r4}
+ 4650              	.LCFI32:
+ 4651              		.cfi_def_cfa_offset 4
+ 4652              		.cfi_offset 4, -4
+1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4653              		.loc 1 1857 3 is_stmt 1 discriminator 2 view .LVU1275
+ 4654 000a 0123     		movs	r3, #1
+ 4655 000c 80F83C30 		strb	r3, [r0, #60]
+1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4656              		.loc 1 1857 3 discriminator 2 view .LVU1276
+ARM GAS  /tmp/cc7KL1Mv.s 			page 149
+
+
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ 4657              		.loc 1 1859 3 discriminator 2 view .LVU1277
+1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ 4658              		.loc 1 1859 6 is_stmt 0 discriminator 2 view .LVU1278
+ 4659 0010 1029     		cmp	r1, #16
+ 4660 0012 18BF     		it	ne
+ 4661 0014 0029     		cmpne	r1, #0
+ 4662 0016 06D0     		beq	.L363
+1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4663              		.loc 1 1860 54 view .LVU1279
+ 4664 0018 3029     		cmp	r1, #48
+ 4665 001a 14BF     		ite	ne
+ 4666 001c 0023     		movne	r3, #0
+ 4667 001e 0123     		moveq	r3, #1
+1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4668              		.loc 1 1860 37 view .LVU1280
+ 4669 0020 2029     		cmp	r1, #32
+ 4670 0022 00D0     		beq	.L363
+ 4671 0024 43B1     		cbz	r3, .L364
+ 4672              	.L363:
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4673              		.loc 1 1863 5 is_stmt 1 view .LVU1281
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4674              		.loc 1 1863 9 is_stmt 0 view .LVU1282
+ 4675 0026 0468     		ldr	r4, [r0]
+1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4676              		.loc 1 1863 26 view .LVU1283
+ 4677 0028 A368     		ldr	r3, [r4, #8]
+ 4678 002a 23F07003 		bic	r3, r3, #112
+ 4679 002e A360     		str	r3, [r4, #8]
+1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4680              		.loc 1 1864 5 is_stmt 1 view .LVU1284
+1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4681              		.loc 1 1864 9 is_stmt 0 view .LVU1285
+ 4682 0030 0468     		ldr	r4, [r0]
+1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4683              		.loc 1 1864 26 view .LVU1286
+ 4684 0032 A368     		ldr	r3, [r4, #8]
+ 4685 0034 1943     		orrs	r1, r1, r3
+ 4686              	.LVL320:
+1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4687              		.loc 1 1864 26 view .LVU1287
+ 4688 0036 A160     		str	r1, [r4, #8]
+ 4689              	.L364:
+1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4690              		.loc 1 1868 3 is_stmt 1 view .LVU1288
+1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4691              		.loc 1 1868 7 is_stmt 0 view .LVU1289
+ 4692 0038 0168     		ldr	r1, [r0]
+1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4693              		.loc 1 1868 23 view .LVU1290
+ 4694 003a 4B68     		ldr	r3, [r1, #4]
+ 4695 003c 43F00103 		orr	r3, r3, #1
+ 4696 0040 4B60     		str	r3, [r1, #4]
+1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4697              		.loc 1 1870 3 is_stmt 1 view .LVU1291
+1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ARM GAS  /tmp/cc7KL1Mv.s 			page 150
+
+
+ 4698              		.loc 1 1870 7 is_stmt 0 view .LVU1292
+ 4699 0042 0168     		ldr	r1, [r0]
+1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4700              		.loc 1 1870 23 view .LVU1293
+ 4701 0044 4B68     		ldr	r3, [r1, #4]
+ 4702 0046 23F00403 		bic	r3, r3, #4
+ 4703 004a 4B60     		str	r3, [r1, #4]
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4704              		.loc 1 1871 3 is_stmt 1 view .LVU1294
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4705              		.loc 1 1871 7 is_stmt 0 view .LVU1295
+ 4706 004c 0168     		ldr	r1, [r0]
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4707              		.loc 1 1871 23 view .LVU1296
+ 4708 004e 4B68     		ldr	r3, [r1, #4]
+ 4709 0050 1A43     		orrs	r2, r2, r3
+ 4710              	.LVL321:
+1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4711              		.loc 1 1871 23 view .LVU1297
+ 4712 0052 4A60     		str	r2, [r1, #4]
+1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4713              		.loc 1 1874 3 is_stmt 1 view .LVU1298
+ 4714 0054 0268     		ldr	r2, [r0]
+ 4715 0056 D368     		ldr	r3, [r2, #12]
+ 4716 0058 23F40053 		bic	r3, r3, #8192
+ 4717 005c D360     		str	r3, [r2, #12]
+1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4718              		.loc 1 1877 3 view .LVU1299
+ 4719 005e 0268     		ldr	r2, [r0]
+ 4720 0060 D368     		ldr	r3, [r2, #12]
+ 4721 0062 43F02003 		orr	r3, r3, #32
+ 4722 0066 D360     		str	r3, [r2, #12]
+1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4723              		.loc 1 1879 3 view .LVU1300
+1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4724              		.loc 1 1879 3 view .LVU1301
+ 4725 0068 0023     		movs	r3, #0
+ 4726 006a 80F83C30 		strb	r3, [r0, #60]
+1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4727              		.loc 1 1879 3 view .LVU1302
+1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 4728              		.loc 1 1881 3 view .LVU1303
+1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 4729              		.loc 1 1881 10 is_stmt 0 view .LVU1304
+ 4730 006e 1846     		mov	r0, r3
+ 4731              	.LVL322:
+1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4732              		.loc 1 1882 1 view .LVU1305
+ 4733 0070 5DF8044B 		ldr	r4, [sp], #4
+ 4734              	.LCFI33:
+ 4735              		.cfi_restore 4
+ 4736              		.cfi_def_cfa_offset 0
+ 4737 0074 7047     		bx	lr
+ 4738              	.LVL323:
+ 4739              	.L366:
+1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4740              		.loc 1 1857 3 view .LVU1306
+ARM GAS  /tmp/cc7KL1Mv.s 			page 151
+
+
+ 4741 0076 0220     		movs	r0, #2
+ 4742              	.LVL324:
+1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4743              		.loc 1 1882 1 view .LVU1307
+ 4744 0078 7047     		bx	lr
+ 4745              		.cfi_endproc
+ 4746              	.LFE168:
+ 4748              		.section	.text.HAL_TIMEx_ConfigCommutEvent_DMA,"ax",%progbits
+ 4749              		.align	1
+ 4750              		.global	HAL_TIMEx_ConfigCommutEvent_DMA
+ 4751              		.syntax unified
+ 4752              		.thumb
+ 4753              		.thumb_func
+ 4754              		.fpu fpv5-d16
+ 4756              	HAL_TIMEx_ConfigCommutEvent_DMA:
+ 4757              	.LVL325:
+ 4758              	.LFB169:
+1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 4759              		.loc 1 1909 1 is_stmt 1 view -0
+ 4760              		.cfi_startproc
+ 4761              		@ args = 0, pretend = 0, frame = 0
+ 4762              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4763              		@ link register save eliminated.
+1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+ 4764              		.loc 1 1911 3 view .LVU1309
+1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4765              		.loc 1 1912 3 view .LVU1310
+1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4766              		.loc 1 1914 3 view .LVU1311
+1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4767              		.loc 1 1914 3 view .LVU1312
+ 4768 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 4769 0004 012B     		cmp	r3, #1
+ 4770 0006 3FD0     		beq	.L376
+1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check the parameters */
+ 4771              		.loc 1 1909 1 is_stmt 0 discriminator 2 view .LVU1313
+ 4772 0008 10B4     		push	{r4}
+ 4773              	.LCFI34:
+ 4774              		.cfi_def_cfa_offset 4
+ 4775              		.cfi_offset 4, -4
+1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4776              		.loc 1 1914 3 is_stmt 1 discriminator 2 view .LVU1314
+ 4777 000a 0123     		movs	r3, #1
+ 4778 000c 80F83C30 		strb	r3, [r0, #60]
+1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4779              		.loc 1 1914 3 discriminator 2 view .LVU1315
+1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ 4780              		.loc 1 1916 3 discriminator 2 view .LVU1316
+1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ 4781              		.loc 1 1916 6 is_stmt 0 discriminator 2 view .LVU1317
+ 4782 0010 1029     		cmp	r1, #16
+ 4783 0012 18BF     		it	ne
+ 4784 0014 0029     		cmpne	r1, #0
+ 4785 0016 06D0     		beq	.L373
+1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4786              		.loc 1 1917 54 view .LVU1318
+ 4787 0018 3029     		cmp	r1, #48
+ARM GAS  /tmp/cc7KL1Mv.s 			page 152
+
+
+ 4788 001a 14BF     		ite	ne
+ 4789 001c 0023     		movne	r3, #0
+ 4790 001e 0123     		moveq	r3, #1
+1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4791              		.loc 1 1917 37 view .LVU1319
+ 4792 0020 2029     		cmp	r1, #32
+ 4793 0022 00D0     		beq	.L373
+ 4794 0024 43B1     		cbz	r3, .L374
+ 4795              	.L373:
+1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4796              		.loc 1 1920 5 is_stmt 1 view .LVU1320
+1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4797              		.loc 1 1920 9 is_stmt 0 view .LVU1321
+ 4798 0026 0468     		ldr	r4, [r0]
+1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     htim->Instance->SMCR |= InputTrigger;
+ 4799              		.loc 1 1920 26 view .LVU1322
+ 4800 0028 A368     		ldr	r3, [r4, #8]
+ 4801 002a 23F07003 		bic	r3, r3, #112
+ 4802 002e A360     		str	r3, [r4, #8]
+1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4803              		.loc 1 1921 5 is_stmt 1 view .LVU1323
+1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4804              		.loc 1 1921 9 is_stmt 0 view .LVU1324
+ 4805 0030 0468     		ldr	r4, [r0]
+1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4806              		.loc 1 1921 26 view .LVU1325
+ 4807 0032 A368     		ldr	r3, [r4, #8]
+ 4808 0034 1943     		orrs	r1, r1, r3
+ 4809              	.LVL326:
+1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4810              		.loc 1 1921 26 view .LVU1326
+ 4811 0036 A160     		str	r1, [r4, #8]
+ 4812              	.L374:
+1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4813              		.loc 1 1925 3 is_stmt 1 view .LVU1327
+1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4814              		.loc 1 1925 7 is_stmt 0 view .LVU1328
+ 4815 0038 0168     		ldr	r1, [r0]
+1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the Commutation event source */
+ 4816              		.loc 1 1925 23 view .LVU1329
+ 4817 003a 4B68     		ldr	r3, [r1, #4]
+ 4818 003c 43F00103 		orr	r3, r3, #1
+ 4819 0040 4B60     		str	r3, [r1, #4]
+1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4820              		.loc 1 1927 3 is_stmt 1 view .LVU1330
+1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4821              		.loc 1 1927 7 is_stmt 0 view .LVU1331
+ 4822 0042 0168     		ldr	r1, [r0]
+1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->Instance->CR2 |= CommutationSource;
+ 4823              		.loc 1 1927 23 view .LVU1332
+ 4824 0044 4B68     		ldr	r3, [r1, #4]
+ 4825 0046 23F00403 		bic	r3, r3, #4
+ 4826 004a 4B60     		str	r3, [r1, #4]
+1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4827              		.loc 1 1928 3 is_stmt 1 view .LVU1333
+1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4828              		.loc 1 1928 7 is_stmt 0 view .LVU1334
+ARM GAS  /tmp/cc7KL1Mv.s 			page 153
+
+
+ 4829 004c 0168     		ldr	r1, [r0]
+1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4830              		.loc 1 1928 23 view .LVU1335
+ 4831 004e 4B68     		ldr	r3, [r1, #4]
+ 4832 0050 1A43     		orrs	r2, r2, r3
+ 4833              	.LVL327:
+1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4834              		.loc 1 1928 23 view .LVU1336
+ 4835 0052 4A60     		str	r2, [r1, #4]
+1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+ 4836              		.loc 1 1932 3 is_stmt 1 view .LVU1337
+1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+ 4837              		.loc 1 1932 13 is_stmt 0 view .LVU1338
+ 4838 0054 436B     		ldr	r3, [r0, #52]
+1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+ 4839              		.loc 1 1932 56 view .LVU1339
+ 4840 0056 0D4A     		ldr	r2, .L381
+ 4841 0058 DA63     		str	r2, [r3, #60]
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 4842              		.loc 1 1933 3 is_stmt 1 view .LVU1340
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 4843              		.loc 1 1933 13 is_stmt 0 view .LVU1341
+ 4844 005a 436B     		ldr	r3, [r0, #52]
+1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Set the DMA error callback */
+ 4845              		.loc 1 1933 60 view .LVU1342
+ 4846 005c 0C4A     		ldr	r2, .L381+4
+ 4847 005e 1A64     		str	r2, [r3, #64]
+1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4848              		.loc 1 1935 3 is_stmt 1 view .LVU1343
+1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4849              		.loc 1 1935 13 is_stmt 0 view .LVU1344
+ 4850 0060 436B     		ldr	r3, [r0, #52]
+1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4851              		.loc 1 1935 57 view .LVU1345
+ 4852 0062 0C4A     		ldr	r2, .L381+8
+ 4853 0064 DA64     		str	r2, [r3, #76]
+1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4854              		.loc 1 1938 3 is_stmt 1 view .LVU1346
+ 4855 0066 0268     		ldr	r2, [r0]
+ 4856 0068 D368     		ldr	r3, [r2, #12]
+ 4857 006a 23F02003 		bic	r3, r3, #32
+ 4858 006e D360     		str	r3, [r2, #12]
+1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4859              		.loc 1 1941 3 view .LVU1347
+ 4860 0070 0268     		ldr	r2, [r0]
+ 4861 0072 D368     		ldr	r3, [r2, #12]
+ 4862 0074 43F40053 		orr	r3, r3, #8192
+ 4863 0078 D360     		str	r3, [r2, #12]
+1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4864              		.loc 1 1943 3 view .LVU1348
+1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4865              		.loc 1 1943 3 view .LVU1349
+ 4866 007a 0023     		movs	r3, #0
+ 4867 007c 80F83C30 		strb	r3, [r0, #60]
+1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4868              		.loc 1 1943 3 view .LVU1350
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ARM GAS  /tmp/cc7KL1Mv.s 			page 154
+
+
+ 4869              		.loc 1 1945 3 view .LVU1351
+1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 4870              		.loc 1 1945 10 is_stmt 0 view .LVU1352
+ 4871 0080 1846     		mov	r0, r3
+ 4872              	.LVL328:
+1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4873              		.loc 1 1946 1 view .LVU1353
+ 4874 0082 5DF8044B 		ldr	r4, [sp], #4
+ 4875              	.LCFI35:
+ 4876              		.cfi_restore 4
+ 4877              		.cfi_def_cfa_offset 0
+ 4878 0086 7047     		bx	lr
+ 4879              	.LVL329:
+ 4880              	.L376:
+1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4881              		.loc 1 1914 3 view .LVU1354
+ 4882 0088 0220     		movs	r0, #2
+ 4883              	.LVL330:
+1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4884              		.loc 1 1946 1 view .LVU1355
+ 4885 008a 7047     		bx	lr
+ 4886              	.L382:
+ 4887              		.align	2
+ 4888              	.L381:
+ 4889 008c 00000000 		.word	TIMEx_DMACommutationCplt
+ 4890 0090 00000000 		.word	TIMEx_DMACommutationHalfCplt
+ 4891 0094 00000000 		.word	TIM_DMAError
+ 4892              		.cfi_endproc
+ 4893              	.LFE169:
+ 4895              		.section	.text.HAL_TIMEx_MasterConfigSynchronization,"ax",%progbits
+ 4896              		.align	1
+ 4897              		.global	HAL_TIMEx_MasterConfigSynchronization
+ 4898              		.syntax unified
+ 4899              		.thumb
+ 4900              		.thumb_func
+ 4901              		.fpu fpv5-d16
+ 4903              	HAL_TIMEx_MasterConfigSynchronization:
+ 4904              	.LVL331:
+ 4905              	.LFB170:
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpcr2;
+ 4906              		.loc 1 1958 1 is_stmt 1 view -0
+ 4907              		.cfi_startproc
+ 4908              		@ args = 0, pretend = 0, frame = 0
+ 4909              		@ frame_needed = 0, uses_anonymous_args = 0
+ 4910              		@ link register save eliminated.
+1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpsmcr;
+ 4911              		.loc 1 1959 3 view .LVU1357
+1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4912              		.loc 1 1960 3 view .LVU1358
+1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ 4913              		.loc 1 1963 3 view .LVU1359
+1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+ 4914              		.loc 1 1964 3 view .LVU1360
+1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4915              		.loc 1 1965 3 view .LVU1361
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4916              		.loc 1 1968 3 view .LVU1362
+ARM GAS  /tmp/cc7KL1Mv.s 			page 155
+
+
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4917              		.loc 1 1968 3 view .LVU1363
+ 4918 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 4919 0004 012B     		cmp	r3, #1
+ 4920 0006 45D0     		beq	.L388
+1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmpcr2;
+ 4921              		.loc 1 1958 1 is_stmt 0 discriminator 2 view .LVU1364
+ 4922 0008 70B4     		push	{r4, r5, r6}
+ 4923              	.LCFI36:
+ 4924              		.cfi_def_cfa_offset 12
+ 4925              		.cfi_offset 4, -12
+ 4926              		.cfi_offset 5, -8
+ 4927              		.cfi_offset 6, -4
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4928              		.loc 1 1968 3 is_stmt 1 discriminator 2 view .LVU1365
+ 4929 000a 0123     		movs	r3, #1
+ 4930 000c 80F83C30 		strb	r3, [r0, #60]
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4931              		.loc 1 1968 3 discriminator 2 view .LVU1366
+1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4932              		.loc 1 1971 3 discriminator 2 view .LVU1367
+1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4933              		.loc 1 1971 15 is_stmt 0 discriminator 2 view .LVU1368
+ 4934 0010 0223     		movs	r3, #2
+ 4935 0012 80F83D30 		strb	r3, [r0, #61]
+1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4936              		.loc 1 1974 3 is_stmt 1 discriminator 2 view .LVU1369
+1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4937              		.loc 1 1974 16 is_stmt 0 discriminator 2 view .LVU1370
+ 4938 0016 0368     		ldr	r3, [r0]
+1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4939              		.loc 1 1974 10 discriminator 2 view .LVU1371
+ 4940 0018 5A68     		ldr	r2, [r3, #4]
+ 4941              	.LVL332:
+1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4942              		.loc 1 1977 3 is_stmt 1 discriminator 2 view .LVU1372
+1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4943              		.loc 1 1977 11 is_stmt 0 discriminator 2 view .LVU1373
+ 4944 001a 9C68     		ldr	r4, [r3, #8]
+ 4945              	.LVL333:
+1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4946              		.loc 1 1980 3 is_stmt 1 discriminator 2 view .LVU1374
+1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4947              		.loc 1 1980 6 is_stmt 0 discriminator 2 view .LVU1375
+ 4948 001c 1E4E     		ldr	r6, .L393
+ 4949 001e 1F4D     		ldr	r5, .L393+4
+ 4950 0020 AB42     		cmp	r3, r5
+ 4951 0022 18BF     		it	ne
+ 4952 0024 B342     		cmpne	r3, r6
+ 4953 0026 03D1     		bne	.L385
+1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4954              		.loc 1 1983 5 is_stmt 1 view .LVU1376
+1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Select the TRGO2 source*/
+ 4955              		.loc 1 1986 5 view .LVU1377
+1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Select the TRGO2 source*/
+ 4956              		.loc 1 1986 12 is_stmt 0 view .LVU1378
+ 4957 0028 22F47002 		bic	r2, r2, #15728640
+ARM GAS  /tmp/cc7KL1Mv.s 			page 156
+
+
+ 4958              	.LVL334:
+1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4959              		.loc 1 1988 5 is_stmt 1 view .LVU1379
+1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4960              		.loc 1 1988 28 is_stmt 0 view .LVU1380
+ 4961 002c 4D68     		ldr	r5, [r1, #4]
+1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 4962              		.loc 1 1988 12 view .LVU1381
+ 4963 002e 2A43     		orrs	r2, r2, r5
+ 4964              	.LVL335:
+ 4965              	.L385:
+1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the TRGO source */
+ 4966              		.loc 1 1992 3 is_stmt 1 view .LVU1382
+1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Select the TRGO source */
+ 4967              		.loc 1 1992 10 is_stmt 0 view .LVU1383
+ 4968 0030 22F07002 		bic	r2, r2, #112
+ 4969              	.LVL336:
+1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4970              		.loc 1 1994 3 is_stmt 1 view .LVU1384
+1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4971              		.loc 1 1994 10 is_stmt 0 view .LVU1385
+ 4972 0034 0D68     		ldr	r5, [r1]
+ 4973 0036 2A43     		orrs	r2, r2, r5
+ 4974              	.LVL337:
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4975              		.loc 1 1997 3 is_stmt 1 view .LVU1386
+1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 4976              		.loc 1 1997 23 is_stmt 0 view .LVU1387
+ 4977 0038 5A60     		str	r2, [r3, #4]
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4978              		.loc 1 1999 3 is_stmt 1 view .LVU1388
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4979              		.loc 1 1999 7 is_stmt 0 view .LVU1389
+ 4980 003a 0368     		ldr	r3, [r0]
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4981              		.loc 1 1999 6 view .LVU1390
+ 4982 003c 164A     		ldr	r2, .L393
+ 4983              	.LVL338:
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4984              		.loc 1 1999 6 view .LVU1391
+ 4985 003e B3F1804F 		cmp	r3, #1073741824
+ 4986 0042 18BF     		it	ne
+ 4987 0044 9342     		cmpne	r3, r2
+ 4988 0046 17D0     		beq	.L386
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4989              		.loc 1 1999 7 discriminator 1 view .LVU1392
+ 4990 0048 A2F57C42 		sub	r2, r2, #64512
+ 4991 004c 9342     		cmp	r3, r2
+ 4992 004e 13D0     		beq	.L386
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4993              		.loc 1 1999 7 discriminator 2 view .LVU1393
+ 4994 0050 02F58062 		add	r2, r2, #1024
+ 4995 0054 9342     		cmp	r3, r2
+ 4996 0056 0FD0     		beq	.L386
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 4997              		.loc 1 1999 7 discriminator 3 view .LVU1394
+ 4998 0058 02F58062 		add	r2, r2, #1024
+ARM GAS  /tmp/cc7KL1Mv.s 			page 157
+
+
+ 4999 005c 9342     		cmp	r3, r2
+ 5000 005e 0BD0     		beq	.L386
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5001              		.loc 1 1999 7 discriminator 4 view .LVU1395
+ 5002 0060 02F57842 		add	r2, r2, #63488
+ 5003 0064 9342     		cmp	r3, r2
+ 5004 0066 07D0     		beq	.L386
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5005              		.loc 1 1999 7 discriminator 5 view .LVU1396
+ 5006 0068 02F57052 		add	r2, r2, #15360
+ 5007 006c 9342     		cmp	r3, r2
+ 5008 006e 03D0     		beq	.L386
+1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5009              		.loc 1 1999 7 discriminator 6 view .LVU1397
+ 5010 0070 A2F59432 		sub	r2, r2, #75776
+ 5011 0074 9342     		cmp	r3, r2
+ 5012 0076 04D1     		bne	.L387
+ 5013              	.L386:
+2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Set master mode */
+ 5014              		.loc 1 2002 5 is_stmt 1 view .LVU1398
+2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     /* Set master mode */
+ 5015              		.loc 1 2002 13 is_stmt 0 view .LVU1399
+ 5016 0078 24F08004 		bic	r4, r4, #128
+ 5017              	.LVL339:
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5018              		.loc 1 2004 5 is_stmt 1 view .LVU1400
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5019              		.loc 1 2004 29 is_stmt 0 view .LVU1401
+ 5020 007c 8A68     		ldr	r2, [r1, #8]
+2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5021              		.loc 1 2004 13 view .LVU1402
+ 5022 007e 1443     		orrs	r4, r4, r2
+ 5023              	.LVL340:
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 5024              		.loc 1 2007 5 is_stmt 1 view .LVU1403
+2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 5025              		.loc 1 2007 26 is_stmt 0 view .LVU1404
+ 5026 0080 9C60     		str	r4, [r3, #8]
+ 5027              	.L387:
+2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5028              		.loc 1 2011 3 is_stmt 1 view .LVU1405
+2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5029              		.loc 1 2011 15 is_stmt 0 view .LVU1406
+ 5030 0082 0123     		movs	r3, #1
+ 5031 0084 80F83D30 		strb	r3, [r0, #61]
+2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5032              		.loc 1 2013 3 is_stmt 1 view .LVU1407
+2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5033              		.loc 1 2013 3 view .LVU1408
+ 5034 0088 0023     		movs	r3, #0
+ 5035 008a 80F83C30 		strb	r3, [r0, #60]
+2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5036              		.loc 1 2013 3 view .LVU1409
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5037              		.loc 1 2015 3 view .LVU1410
+2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5038              		.loc 1 2015 10 is_stmt 0 view .LVU1411
+ARM GAS  /tmp/cc7KL1Mv.s 			page 158
+
+
+ 5039 008e 1846     		mov	r0, r3
+ 5040              	.LVL341:
+2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5041              		.loc 1 2016 1 view .LVU1412
+ 5042 0090 70BC     		pop	{r4, r5, r6}
+ 5043              	.LCFI37:
+ 5044              		.cfi_restore 6
+ 5045              		.cfi_restore 5
+ 5046              		.cfi_restore 4
+ 5047              		.cfi_def_cfa_offset 0
+ 5048              	.LVL342:
+2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5049              		.loc 1 2016 1 view .LVU1413
+ 5050 0092 7047     		bx	lr
+ 5051              	.LVL343:
+ 5052              	.L388:
+1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5053              		.loc 1 1968 3 view .LVU1414
+ 5054 0094 0220     		movs	r0, #2
+ 5055              	.LVL344:
+2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5056              		.loc 1 2016 1 view .LVU1415
+ 5057 0096 7047     		bx	lr
+ 5058              	.L394:
+ 5059              		.align	2
+ 5060              	.L393:
+ 5061 0098 00000140 		.word	1073807360
+ 5062 009c 00040140 		.word	1073808384
+ 5063              		.cfi_endproc
+ 5064              	.LFE170:
+ 5066              		.section	.text.HAL_TIMEx_ConfigBreakDeadTime,"ax",%progbits
+ 5067              		.align	1
+ 5068              		.global	HAL_TIMEx_ConfigBreakDeadTime
+ 5069              		.syntax unified
+ 5070              		.thumb
+ 5071              		.thumb_func
+ 5072              		.fpu fpv5-d16
+ 5074              	HAL_TIMEx_ConfigBreakDeadTime:
+ 5075              	.LVL345:
+ 5076              	.LFB171:
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+ 5077              		.loc 1 2031 1 is_stmt 1 view -0
+ 5078              		.cfi_startproc
+ 5079              		@ args = 0, pretend = 0, frame = 0
+ 5080              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5081              		@ link register save eliminated.
+2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5082              		.loc 1 2033 3 view .LVU1417
+2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ 5083              		.loc 1 2036 3 view .LVU1418
+2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ 5084              		.loc 1 2037 3 view .LVU1419
+2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ 5085              		.loc 1 2038 3 view .LVU1420
+2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ 5086              		.loc 1 2039 3 view .LVU1421
+2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ARM GAS  /tmp/cc7KL1Mv.s 			page 159
+
+
+ 5087              		.loc 1 2040 3 view .LVU1422
+2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ 5088              		.loc 1 2041 3 view .LVU1423
+2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+ 5089              		.loc 1 2042 3 view .LVU1424
+2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+ 5090              		.loc 1 2043 3 view .LVU1425
+2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5091              		.loc 1 2044 3 view .LVU1426
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5092              		.loc 1 2047 3 view .LVU1427
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5093              		.loc 1 2047 3 view .LVU1428
+ 5094 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 5095 0004 012B     		cmp	r3, #1
+ 5096 0006 3CD0     		beq	.L398
+2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+ 5097              		.loc 1 2031 1 is_stmt 0 discriminator 2 view .LVU1429
+ 5098 0008 30B4     		push	{r4, r5}
+ 5099              	.LCFI38:
+ 5100              		.cfi_def_cfa_offset 8
+ 5101              		.cfi_offset 4, -8
+ 5102              		.cfi_offset 5, -4
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5103              		.loc 1 2047 3 is_stmt 1 discriminator 2 view .LVU1430
+ 5104 000a 0123     		movs	r3, #1
+ 5105 000c 80F83C30 		strb	r3, [r0, #60]
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5106              		.loc 1 2047 3 discriminator 2 view .LVU1431
+2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ 5107              		.loc 1 2053 3 discriminator 2 view .LVU1432
+ 5108 0010 CB68     		ldr	r3, [r1, #12]
+ 5109              	.LVL346:
+2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ 5110              		.loc 1 2054 3 discriminator 2 view .LVU1433
+ 5111 0012 23F44073 		bic	r3, r3, #768
+ 5112              	.LVL347:
+2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ 5113              		.loc 1 2054 3 is_stmt 0 discriminator 2 view .LVU1434
+ 5114 0016 8A68     		ldr	r2, [r1, #8]
+ 5115 0018 1343     		orrs	r3, r3, r2
+ 5116              	.LVL348:
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ 5117              		.loc 1 2055 3 is_stmt 1 discriminator 2 view .LVU1435
+ 5118 001a 23F48063 		bic	r3, r3, #1024
+ 5119              	.LVL349:
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ 5120              		.loc 1 2055 3 is_stmt 0 discriminator 2 view .LVU1436
+ 5121 001e 4A68     		ldr	r2, [r1, #4]
+ 5122              	.LVL350:
+2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ 5123              		.loc 1 2055 3 discriminator 2 view .LVU1437
+ 5124 0020 1343     		orrs	r3, r3, r2
+ 5125              	.LVL351:
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ 5126              		.loc 1 2056 3 is_stmt 1 discriminator 2 view .LVU1438
+ 5127 0022 23F40063 		bic	r3, r3, #2048
+ARM GAS  /tmp/cc7KL1Mv.s 			page 160
+
+
+ 5128              	.LVL352:
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ 5129              		.loc 1 2056 3 is_stmt 0 discriminator 2 view .LVU1439
+ 5130 0026 0A68     		ldr	r2, [r1]
+ 5131              	.LVL353:
+2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ 5132              		.loc 1 2056 3 discriminator 2 view .LVU1440
+ 5133 0028 1343     		orrs	r3, r3, r2
+ 5134              	.LVL354:
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ 5135              		.loc 1 2057 3 is_stmt 1 discriminator 2 view .LVU1441
+ 5136 002a 23F48053 		bic	r3, r3, #4096
+ 5137              	.LVL355:
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ 5138              		.loc 1 2057 3 is_stmt 0 discriminator 2 view .LVU1442
+ 5139 002e 0A69     		ldr	r2, [r1, #16]
+ 5140              	.LVL356:
+2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ 5141              		.loc 1 2057 3 discriminator 2 view .LVU1443
+ 5142 0030 1343     		orrs	r3, r3, r2
+ 5143              	.LVL357:
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ 5144              		.loc 1 2058 3 is_stmt 1 discriminator 2 view .LVU1444
+ 5145 0032 23F40053 		bic	r3, r3, #8192
+ 5146              	.LVL358:
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ 5147              		.loc 1 2058 3 is_stmt 0 discriminator 2 view .LVU1445
+ 5148 0036 4A69     		ldr	r2, [r1, #20]
+ 5149              	.LVL359:
+2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ 5150              		.loc 1 2058 3 discriminator 2 view .LVU1446
+ 5151 0038 1343     		orrs	r3, r3, r2
+ 5152              	.LVL360:
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+ 5153              		.loc 1 2059 3 is_stmt 1 discriminator 2 view .LVU1447
+ 5154 003a 23F48043 		bic	r3, r3, #16384
+ 5155              	.LVL361:
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+ 5156              		.loc 1 2059 3 is_stmt 0 discriminator 2 view .LVU1448
+ 5157 003e 8A6A     		ldr	r2, [r1, #40]
+ 5158              	.LVL362:
+2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+ 5159              		.loc 1 2059 3 discriminator 2 view .LVU1449
+ 5160 0040 1343     		orrs	r3, r3, r2
+ 5161              	.LVL363:
+2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5162              		.loc 1 2060 3 is_stmt 1 discriminator 2 view .LVU1450
+ 5163 0042 23F47023 		bic	r3, r3, #983040
+ 5164              	.LVL364:
+2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5165              		.loc 1 2060 3 is_stmt 0 discriminator 2 view .LVU1451
+ 5166 0046 8A69     		ldr	r2, [r1, #24]
+ 5167              	.LVL365:
+2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5168              		.loc 1 2060 3 discriminator 2 view .LVU1452
+ 5169 0048 43EA0243 		orr	r3, r3, r2, lsl #16
+ 5170              	.LVL366:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 161
+
+
+2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5171              		.loc 1 2062 3 is_stmt 1 discriminator 2 view .LVU1453
+2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5172              		.loc 1 2062 7 is_stmt 0 discriminator 2 view .LVU1454
+ 5173 004c 0268     		ldr	r2, [r0]
+2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5174              		.loc 1 2062 6 discriminator 2 view .LVU1455
+ 5175 004e 0E4D     		ldr	r5, .L403
+ 5176 0050 0E4C     		ldr	r4, .L403+4
+ 5177 0052 A242     		cmp	r2, r4
+ 5178 0054 18BF     		it	ne
+ 5179 0056 AA42     		cmpne	r2, r5
+ 5180 0058 0CD1     		bne	.L397
+2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+ 5181              		.loc 1 2065 5 is_stmt 1 view .LVU1456
+2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+ 5182              		.loc 1 2066 5 view .LVU1457
+2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5183              		.loc 1 2067 5 view .LVU1458
+2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+ 5184              		.loc 1 2070 5 view .LVU1459
+ 5185 005a 23F47003 		bic	r3, r3, #15728640
+ 5186              	.LVL367:
+2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+ 5187              		.loc 1 2070 5 is_stmt 0 view .LVU1460
+ 5188 005e 4C6A     		ldr	r4, [r1, #36]
+ 5189 0060 43EA0453 		orr	r3, r3, r4, lsl #20
+ 5190              	.LVL368:
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+ 5191              		.loc 1 2071 5 is_stmt 1 view .LVU1461
+ 5192 0064 23F08073 		bic	r3, r3, #16777216
+ 5193              	.LVL369:
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+ 5194              		.loc 1 2071 5 is_stmt 0 view .LVU1462
+ 5195 0068 CC69     		ldr	r4, [r1, #28]
+ 5196              	.LVL370:
+2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+ 5197              		.loc 1 2071 5 view .LVU1463
+ 5198 006a 2343     		orrs	r3, r3, r4
+ 5199              	.LVL371:
+2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 5200              		.loc 1 2072 5 is_stmt 1 view .LVU1464
+ 5201 006c 23F00073 		bic	r3, r3, #33554432
+ 5202              	.LVL372:
+2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 5203              		.loc 1 2072 5 is_stmt 0 view .LVU1465
+ 5204 0070 096A     		ldr	r1, [r1, #32]
+ 5205              	.LVL373:
+2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 5206              		.loc 1 2072 5 view .LVU1466
+ 5207 0072 0B43     		orrs	r3, r3, r1
+ 5208              	.LVL374:
+ 5209              	.L397:
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5210              		.loc 1 2076 3 is_stmt 1 view .LVU1467
+2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5211              		.loc 1 2076 24 is_stmt 0 view .LVU1468
+ARM GAS  /tmp/cc7KL1Mv.s 			page 162
+
+
+ 5212 0074 5364     		str	r3, [r2, #68]
+2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5213              		.loc 1 2078 3 is_stmt 1 view .LVU1469
+2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5214              		.loc 1 2078 3 view .LVU1470
+ 5215 0076 0023     		movs	r3, #0
+ 5216              	.LVL375:
+2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5217              		.loc 1 2078 3 is_stmt 0 view .LVU1471
+ 5218 0078 80F83C30 		strb	r3, [r0, #60]
+ 5219              	.LVL376:
+2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5220              		.loc 1 2078 3 is_stmt 1 view .LVU1472
+2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5221              		.loc 1 2080 3 view .LVU1473
+2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5222              		.loc 1 2080 10 is_stmt 0 view .LVU1474
+ 5223 007c 1846     		mov	r0, r3
+ 5224              	.LVL377:
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(TIM_BREAK_INPUT_SUPPORT)
+ 5225              		.loc 1 2081 1 view .LVU1475
+ 5226 007e 30BC     		pop	{r4, r5}
+ 5227              	.LCFI39:
+ 5228              		.cfi_restore 5
+ 5229              		.cfi_restore 4
+ 5230              		.cfi_def_cfa_offset 0
+ 5231 0080 7047     		bx	lr
+ 5232              	.LVL378:
+ 5233              	.L398:
+2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5234              		.loc 1 2047 3 view .LVU1476
+ 5235 0082 0220     		movs	r0, #2
+ 5236              	.LVL379:
+2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(TIM_BREAK_INPUT_SUPPORT)
+ 5237              		.loc 1 2081 1 view .LVU1477
+ 5238 0084 7047     		bx	lr
+ 5239              	.L404:
+ 5240 0086 00BF     		.align	2
+ 5241              	.L403:
+ 5242 0088 00000140 		.word	1073807360
+ 5243 008c 00040140 		.word	1073808384
+ 5244              		.cfi_endproc
+ 5245              	.LFE171:
+ 5247              		.section	.text.HAL_TIMEx_ConfigBreakInput,"ax",%progbits
+ 5248              		.align	1
+ 5249              		.global	HAL_TIMEx_ConfigBreakInput
+ 5250              		.syntax unified
+ 5251              		.thumb
+ 5252              		.thumb_func
+ 5253              		.fpu fpv5-d16
+ 5255              	HAL_TIMEx_ConfigBreakInput:
+ 5256              	.LVL380:
+ 5257              	.LFB172:
+2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 5258              		.loc 1 2097 1 is_stmt 1 view -0
+ 5259              		.cfi_startproc
+ 5260              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/cc7KL1Mv.s 			page 163
+
+
+ 5261              		@ frame_needed = 0, uses_anonymous_args = 0
+2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 5262              		.loc 1 2097 1 is_stmt 0 view .LVU1479
+ 5263 0000 0346     		mov	r3, r0
+2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmporx;
+ 5264              		.loc 1 2098 3 is_stmt 1 view .LVU1480
+ 5265              	.LVL381:
+2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t bkin_enable_mask;
+ 5266              		.loc 1 2099 3 view .LVU1481
+2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t bkin_polarity_mask;
+ 5267              		.loc 1 2100 3 view .LVU1482
+2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t bkin_enable_bitpos;
+ 5268              		.loc 1 2101 3 view .LVU1483
+2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t bkin_polarity_bitpos;
+ 5269              		.loc 1 2102 3 view .LVU1484
+2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5270              		.loc 1 2103 3 view .LVU1485
+2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUT(BreakInput));
+ 5271              		.loc 1 2106 3 view .LVU1486
+2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+ 5272              		.loc 1 2107 3 view .LVU1487
+2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+ 5273              		.loc 1 2108 3 view .LVU1488
+2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(DFSDM1_Channel0)
+ 5274              		.loc 1 2109 3 view .LVU1489
+2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5275              		.loc 1 2111 3 view .LVU1490
+2113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   }
+ 5276              		.loc 1 2113 5 view .LVU1491
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5277              		.loc 1 2120 3 view .LVU1492
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5278              		.loc 1 2120 3 view .LVU1493
+ 5279 0002 90F83C00 		ldrb	r0, [r0, #60]	@ zero_extendqisi2
+ 5280              	.LVL382:
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5281              		.loc 1 2120 3 is_stmt 0 view .LVU1494
+ 5282 0006 0128     		cmp	r0, #1
+ 5283 0008 4ED0     		beq	.L413
+2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
+ 5284              		.loc 1 2097 1 discriminator 2 view .LVU1495
+ 5285 000a F0B5     		push	{r4, r5, r6, r7, lr}
+ 5286              	.LCFI40:
+ 5287              		.cfi_def_cfa_offset 20
+ 5288              		.cfi_offset 4, -20
+ 5289              		.cfi_offset 5, -16
+ 5290              		.cfi_offset 6, -12
+ 5291              		.cfi_offset 7, -8
+ 5292              		.cfi_offset 14, -4
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5293              		.loc 1 2120 3 is_stmt 1 discriminator 2 view .LVU1496
+ 5294 000c 0120     		movs	r0, #1
+ 5295 000e 83F83C00 		strb	r0, [r3, #60]
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5296              		.loc 1 2120 3 discriminator 2 view .LVU1497
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5297              		.loc 1 2122 3 discriminator 2 view .LVU1498
+ARM GAS  /tmp/cc7KL1Mv.s 			page 164
+
+
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5298              		.loc 1 2122 28 is_stmt 0 discriminator 2 view .LVU1499
+ 5299 0012 1068     		ldr	r0, [r2]
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5300              		.loc 1 2122 3 discriminator 2 view .LVU1500
+ 5301 0014 0128     		cmp	r0, #1
+ 5302 0016 10D0     		beq	.L414
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5303              		.loc 1 2122 3 view .LVU1501
+ 5304 0018 0828     		cmp	r0, #8
+ 5305 001a 15D1     		bne	.L415
+2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_polarity_mask = 0U;
+ 5306              		.loc 1 2136 26 view .LVU1502
+ 5307 001c 0546     		mov	r5, r0
+2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 5308              		.loc 1 2138 28 view .LVU1503
+ 5309 001e 4FF0000C 		mov	ip, #0
+2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_polarity_bitpos = 0U;
+ 5310              		.loc 1 2137 26 view .LVU1504
+ 5311 0022 E646     		mov	lr, ip
+2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_enable_bitpos = TIM1_AF1_BKDF1BKE_Pos;
+ 5312              		.loc 1 2135 24 view .LVU1505
+ 5313 0024 4FF48074 		mov	r4, #256
+ 5314              	.L407:
+ 5315              	.LVL383:
+2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5316              		.loc 1 2153 3 is_stmt 1 view .LVU1506
+ 5317 0028 0129     		cmp	r1, #1
+ 5318 002a 13D0     		beq	.L408
+ 5319 002c 0229     		cmp	r1, #2
+ 5320 002e 26D0     		beq	.L409
+ 5321 0030 0120     		movs	r0, #1
+ 5322              	.LVL384:
+ 5323              	.L410:
+2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5324              		.loc 1 2204 3 view .LVU1507
+2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5325              		.loc 1 2204 3 view .LVU1508
+ 5326 0032 0022     		movs	r2, #0
+ 5327 0034 83F83C20 		strb	r2, [r3, #60]
+2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5328              		.loc 1 2204 3 view .LVU1509
+2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5329              		.loc 1 2206 3 view .LVU1510
+2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /*TIM_BREAK_INPUT_SUPPORT */
+ 5330              		.loc 1 2207 1 is_stmt 0 view .LVU1511
+ 5331 0038 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 5332              	.LVL385:
+ 5333              	.L414:
+2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   {
+ 5334              		.loc 1 2122 3 view .LVU1512
+ 5335 003a 0446     		mov	r4, r0
+ 5336 003c 4FF0090C 		mov	ip, #9
+ 5337 0040 0025     		movs	r5, #0
+ 5338 0042 4FF4007E 		mov	lr, #512
+ 5339 0046 EFE7     		b	.L407
+ 5340              	.L415:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 165
+
+
+2148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 5341              		.loc 1 2148 28 view .LVU1513
+ 5342 0048 4FF0000C 		mov	ip, #0
+2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_polarity_bitpos = 0U;
+ 5343              		.loc 1 2147 26 view .LVU1514
+ 5344 004c 6546     		mov	r5, ip
+2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_enable_bitpos = 0U;
+ 5345              		.loc 1 2146 26 view .LVU1515
+ 5346 004e E646     		mov	lr, ip
+2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       bkin_polarity_mask = 0U;
+ 5347              		.loc 1 2145 24 view .LVU1516
+ 5348 0050 6446     		mov	r4, ip
+ 5349 0052 E9E7     		b	.L407
+ 5350              	.LVL386:
+ 5351              	.L408:
+2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5352              		.loc 1 2158 7 is_stmt 1 view .LVU1517
+2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5353              		.loc 1 2158 20 is_stmt 0 view .LVU1518
+ 5354 0054 1E68     		ldr	r6, [r3]
+2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5355              		.loc 1 2158 14 view .LVU1519
+ 5356 0056 376E     		ldr	r7, [r6, #96]
+ 5357              	.LVL387:
+2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+ 5358              		.loc 1 2161 7 is_stmt 1 view .LVU1520
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5359              		.loc 1 2162 7 view .LVU1521
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5360              		.loc 1 2162 35 is_stmt 0 view .LVU1522
+ 5361 0058 5168     		ldr	r1, [r2, #4]
+ 5362              	.LVL388:
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5363              		.loc 1 2162 44 view .LVU1523
+ 5364 005a A940     		lsls	r1, r1, r5
+ 5365 005c 7940     		eors	r1, r1, r7
+ 5366 005e 2140     		ands	r1, r1, r4
+2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5367              		.loc 1 2162 14 view .LVU1524
+ 5368 0060 7940     		eors	r1, r1, r7
+ 5369              	.LVL389:
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */
+ 5370              		.loc 1 2166 7 is_stmt 1 view .LVU1525
+2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */
+ 5371              		.loc 1 2166 10 is_stmt 0 view .LVU1526
+ 5372 0062 0828     		cmp	r0, #8
+ 5373 0064 08D0     		beq	.L411
+2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ 5374              		.loc 1 2169 9 is_stmt 1 view .LVU1527
+ 5375              	.LVL390:
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 5376              		.loc 1 2170 9 view .LVU1528
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 5377              		.loc 1 2170 37 is_stmt 0 view .LVU1529
+ 5378 0066 9268     		ldr	r2, [r2, #8]
+ 5379              	.LVL391:
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ARM GAS  /tmp/cc7KL1Mv.s 			page 166
+
+
+ 5380              		.loc 1 2170 48 view .LVU1530
+ 5381 0068 02FA0CFC 		lsl	ip, r2, ip
+ 5382              	.LVL392:
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 5383              		.loc 1 2170 48 view .LVU1531
+ 5384 006c 8CEA010C 		eor	ip, ip, r1
+ 5385 0070 0CEA0E0E 		and	lr, ip, lr
+ 5386              	.LVL393:
+2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 5387              		.loc 1 2170 16 view .LVU1532
+ 5388 0074 81EA0E01 		eor	r1, r1, lr
+ 5389              	.LVL394:
+ 5390              	.L411:
+2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 5391              		.loc 1 2174 7 is_stmt 1 view .LVU1533
+2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 5392              		.loc 1 2174 27 is_stmt 0 view .LVU1534
+ 5393 0078 3166     		str	r1, [r6, #96]
+2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 5394              		.loc 1 2175 7 is_stmt 1 view .LVU1535
+2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmporx;
+ 5395              		.loc 1 2098 21 is_stmt 0 view .LVU1536
+ 5396 007a 0020     		movs	r0, #0
+2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 5397              		.loc 1 2175 7 view .LVU1537
+ 5398 007c D9E7     		b	.L410
+ 5399              	.LVL395:
+ 5400              	.L409:
+2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5401              		.loc 1 2180 7 is_stmt 1 view .LVU1538
+2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5402              		.loc 1 2180 20 is_stmt 0 view .LVU1539
+ 5403 007e 1E68     		ldr	r6, [r3]
+2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5404              		.loc 1 2180 14 view .LVU1540
+ 5405 0080 776E     		ldr	r7, [r6, #100]
+ 5406              	.LVL396:
+2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+ 5407              		.loc 1 2183 7 is_stmt 1 view .LVU1541
+2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5408              		.loc 1 2184 7 view .LVU1542
+2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5409              		.loc 1 2184 35 is_stmt 0 view .LVU1543
+ 5410 0082 5168     		ldr	r1, [r2, #4]
+ 5411              	.LVL397:
+2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5412              		.loc 1 2184 44 view .LVU1544
+ 5413 0084 A940     		lsls	r1, r1, r5
+ 5414 0086 7940     		eors	r1, r1, r7
+ 5415 0088 2140     		ands	r1, r1, r4
+2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5416              		.loc 1 2184 14 view .LVU1545
+ 5417 008a 7940     		eors	r1, r1, r7
+ 5418              	.LVL398:
+2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */
+ 5419              		.loc 1 2188 7 is_stmt 1 view .LVU1546
+2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */
+ARM GAS  /tmp/cc7KL1Mv.s 			page 167
+
+
+ 5420              		.loc 1 2188 10 is_stmt 0 view .LVU1547
+ 5421 008c 0828     		cmp	r0, #8
+ 5422 008e 08D0     		beq	.L412
+2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****         tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ 5423              		.loc 1 2191 9 is_stmt 1 view .LVU1548
+ 5424              	.LVL399:
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 5425              		.loc 1 2192 9 view .LVU1549
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 5426              		.loc 1 2192 37 is_stmt 0 view .LVU1550
+ 5427 0090 9268     		ldr	r2, [r2, #8]
+ 5428              	.LVL400:
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 5429              		.loc 1 2192 48 view .LVU1551
+ 5430 0092 02FA0CFC 		lsl	ip, r2, ip
+ 5431              	.LVL401:
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 5432              		.loc 1 2192 48 view .LVU1552
+ 5433 0096 8CEA010C 		eor	ip, ip, r1
+ 5434 009a 0CEA0E0E 		and	lr, ip, lr
+ 5435              	.LVL402:
+2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       }
+ 5436              		.loc 1 2192 16 view .LVU1553
+ 5437 009e 81EA0E01 		eor	r1, r1, lr
+ 5438              	.LVL403:
+ 5439              	.L412:
+2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 5440              		.loc 1 2196 7 is_stmt 1 view .LVU1554
+2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****       break;
+ 5441              		.loc 1 2196 27 is_stmt 0 view .LVU1555
+ 5442 00a2 7166     		str	r1, [r6, #100]
+2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 5443              		.loc 1 2197 7 is_stmt 1 view .LVU1556
+2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   uint32_t tmporx;
+ 5444              		.loc 1 2098 21 is_stmt 0 view .LVU1557
+ 5445 00a4 0020     		movs	r0, #0
+2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****     }
+ 5446              		.loc 1 2197 7 view .LVU1558
+ 5447 00a6 C4E7     		b	.L410
+ 5448              	.LVL404:
+ 5449              	.L413:
+ 5450              	.LCFI41:
+ 5451              		.cfi_def_cfa_offset 0
+ 5452              		.cfi_restore 4
+ 5453              		.cfi_restore 5
+ 5454              		.cfi_restore 6
+ 5455              		.cfi_restore 7
+ 5456              		.cfi_restore 14
+2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5457              		.loc 1 2120 3 view .LVU1559
+ 5458 00a8 0220     		movs	r0, #2
+2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /*TIM_BREAK_INPUT_SUPPORT */
+ 5459              		.loc 1 2207 1 view .LVU1560
+ 5460 00aa 7047     		bx	lr
+ 5461              		.cfi_endproc
+ 5462              	.LFE172:
+ 5464              		.section	.text.HAL_TIMEx_RemapConfig,"ax",%progbits
+ARM GAS  /tmp/cc7KL1Mv.s 			page 168
+
+
+ 5465              		.align	1
+ 5466              		.global	HAL_TIMEx_RemapConfig
+ 5467              		.syntax unified
+ 5468              		.thumb
+ 5469              		.thumb_func
+ 5470              		.fpu fpv5-d16
+ 5472              	HAL_TIMEx_RemapConfig:
+ 5473              	.LVL405:
+ 5474              	.LFB173:
+2232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check parameters */
+ 5475              		.loc 1 2232 1 is_stmt 1 view -0
+ 5476              		.cfi_startproc
+ 5477              		@ args = 0, pretend = 0, frame = 0
+ 5478              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5479              		@ link register save eliminated.
+2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_REMAP(Remap));
+ 5480              		.loc 1 2234 3 view .LVU1562
+2235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5481              		.loc 1 2235 3 view .LVU1563
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5482              		.loc 1 2237 3 view .LVU1564
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5483              		.loc 1 2237 3 view .LVU1565
+ 5484 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 5485 0004 012B     		cmp	r3, #1
+ 5486 0006 0BD0     		beq	.L422
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5487              		.loc 1 2237 3 discriminator 2 view .LVU1566
+ 5488 0008 0123     		movs	r3, #1
+ 5489 000a 80F83C30 		strb	r3, [r0, #60]
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5490              		.loc 1 2237 3 discriminator 2 view .LVU1567
+2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5491              		.loc 1 2240 3 discriminator 2 view .LVU1568
+2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5492              		.loc 1 2240 7 is_stmt 0 discriminator 2 view .LVU1569
+ 5493 000e 0268     		ldr	r2, [r0]
+2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5494              		.loc 1 2240 22 discriminator 2 view .LVU1570
+ 5495 0010 1165     		str	r1, [r2, #80]
+2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5496              		.loc 1 2242 3 is_stmt 1 discriminator 2 view .LVU1571
+2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5497              		.loc 1 2242 15 is_stmt 0 discriminator 2 view .LVU1572
+ 5498 0012 80F83D30 		strb	r3, [r0, #61]
+2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5499              		.loc 1 2244 3 is_stmt 1 discriminator 2 view .LVU1573
+2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5500              		.loc 1 2244 3 discriminator 2 view .LVU1574
+ 5501 0016 0023     		movs	r3, #0
+ 5502 0018 80F83C30 		strb	r3, [r0, #60]
+2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5503              		.loc 1 2244 3 discriminator 2 view .LVU1575
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5504              		.loc 1 2246 3 discriminator 2 view .LVU1576
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5505              		.loc 1 2246 10 is_stmt 0 discriminator 2 view .LVU1577
+ARM GAS  /tmp/cc7KL1Mv.s 			page 169
+
+
+ 5506 001c 1846     		mov	r0, r3
+ 5507              	.LVL406:
+2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5508              		.loc 1 2246 10 discriminator 2 view .LVU1578
+ 5509 001e 7047     		bx	lr
+ 5510              	.LVL407:
+ 5511              	.L422:
+2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5512              		.loc 1 2237 3 view .LVU1579
+ 5513 0020 0220     		movs	r0, #2
+ 5514              	.LVL408:
+2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5515              		.loc 1 2247 1 view .LVU1580
+ 5516 0022 7047     		bx	lr
+ 5517              		.cfi_endproc
+ 5518              	.LFE173:
+ 5520              		.section	.text.HAL_TIMEx_GroupChannel5,"ax",%progbits
+ 5521              		.align	1
+ 5522              		.global	HAL_TIMEx_GroupChannel5
+ 5523              		.syntax unified
+ 5524              		.thumb
+ 5525              		.thumb_func
+ 5526              		.fpu fpv5-d16
+ 5528              	HAL_TIMEx_GroupChannel5:
+ 5529              	.LVL409:
+ 5530              	.LFB174:
+2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check parameters */
+ 5531              		.loc 1 2261 1 is_stmt 1 view -0
+ 5532              		.cfi_startproc
+ 5533              		@ args = 0, pretend = 0, frame = 0
+ 5534              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5535              		@ link register save eliminated.
+2263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   assert_param(IS_TIM_GROUPCH5(Channels));
+ 5536              		.loc 1 2263 3 view .LVU1582
+2264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5537              		.loc 1 2264 3 view .LVU1583
+2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5538              		.loc 1 2267 3 view .LVU1584
+2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5539              		.loc 1 2267 3 view .LVU1585
+ 5540 0000 90F83C30 		ldrb	r3, [r0, #60]	@ zero_extendqisi2
+ 5541 0004 012B     		cmp	r3, #1
+ 5542 0006 18D0     		beq	.L425
+2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Check parameters */
+ 5543              		.loc 1 2261 1 is_stmt 0 discriminator 2 view .LVU1586
+ 5544 0008 10B4     		push	{r4}
+ 5545              	.LCFI42:
+ 5546              		.cfi_def_cfa_offset 4
+ 5547              		.cfi_offset 4, -4
+2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5548              		.loc 1 2267 3 is_stmt 1 discriminator 2 view .LVU1587
+ 5549 000a 0122     		movs	r2, #1
+ 5550 000c 80F83C20 		strb	r2, [r0, #60]
+2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5551              		.loc 1 2267 3 discriminator 2 view .LVU1588
+2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5552              		.loc 1 2269 3 discriminator 2 view .LVU1589
+ARM GAS  /tmp/cc7KL1Mv.s 			page 170
+
+
+2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5553              		.loc 1 2269 15 is_stmt 0 discriminator 2 view .LVU1590
+ 5554 0010 0223     		movs	r3, #2
+ 5555 0012 80F83D30 		strb	r3, [r0, #61]
+2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5556              		.loc 1 2272 3 is_stmt 1 discriminator 2 view .LVU1591
+2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5557              		.loc 1 2272 7 is_stmt 0 discriminator 2 view .LVU1592
+ 5558 0016 0468     		ldr	r4, [r0]
+2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5559              		.loc 1 2272 24 discriminator 2 view .LVU1593
+ 5560 0018 A36D     		ldr	r3, [r4, #88]
+ 5561 001a 23F06043 		bic	r3, r3, #-536870912
+ 5562 001e A365     		str	r3, [r4, #88]
+2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5563              		.loc 1 2275 3 is_stmt 1 discriminator 2 view .LVU1594
+2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5564              		.loc 1 2275 7 is_stmt 0 discriminator 2 view .LVU1595
+ 5565 0020 0468     		ldr	r4, [r0]
+2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5566              		.loc 1 2275 24 discriminator 2 view .LVU1596
+ 5567 0022 A36D     		ldr	r3, [r4, #88]
+ 5568 0024 1943     		orrs	r1, r1, r3
+ 5569              	.LVL410:
+2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5570              		.loc 1 2275 24 discriminator 2 view .LVU1597
+ 5571 0026 A165     		str	r1, [r4, #88]
+2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5572              		.loc 1 2278 3 is_stmt 1 discriminator 2 view .LVU1598
+2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5573              		.loc 1 2278 15 is_stmt 0 discriminator 2 view .LVU1599
+ 5574 0028 80F83D20 		strb	r2, [r0, #61]
+2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5575              		.loc 1 2280 3 is_stmt 1 discriminator 2 view .LVU1600
+2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5576              		.loc 1 2280 3 discriminator 2 view .LVU1601
+ 5577 002c 0023     		movs	r3, #0
+ 5578 002e 80F83C30 		strb	r3, [r0, #60]
+2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5579              		.loc 1 2280 3 discriminator 2 view .LVU1602
+2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5580              		.loc 1 2282 3 discriminator 2 view .LVU1603
+2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5581              		.loc 1 2282 10 is_stmt 0 discriminator 2 view .LVU1604
+ 5582 0032 1846     		mov	r0, r3
+ 5583              	.LVL411:
+2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5584              		.loc 1 2283 1 discriminator 2 view .LVU1605
+ 5585 0034 5DF8044B 		ldr	r4, [sp], #4
+ 5586              	.LCFI43:
+ 5587              		.cfi_restore 4
+ 5588              		.cfi_def_cfa_offset 0
+ 5589 0038 7047     		bx	lr
+ 5590              	.LVL412:
+ 5591              	.L425:
+2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5592              		.loc 1 2267 3 view .LVU1606
+ARM GAS  /tmp/cc7KL1Mv.s 			page 171
+
+
+ 5593 003a 0220     		movs	r0, #2
+ 5594              	.LVL413:
+2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5595              		.loc 1 2283 1 view .LVU1607
+ 5596 003c 7047     		bx	lr
+ 5597              		.cfi_endproc
+ 5598              	.LFE174:
+ 5600              		.section	.text.HAL_TIMEx_CommutCallback,"ax",%progbits
+ 5601              		.align	1
+ 5602              		.weak	HAL_TIMEx_CommutCallback
+ 5603              		.syntax unified
+ 5604              		.thumb
+ 5605              		.thumb_func
+ 5606              		.fpu fpv5-d16
+ 5608              	HAL_TIMEx_CommutCallback:
+ 5609              	.LVL414:
+ 5610              	.LFB175:
+2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 5611              		.loc 1 2311 1 is_stmt 1 view -0
+ 5612              		.cfi_startproc
+ 5613              		@ args = 0, pretend = 0, frame = 0
+ 5614              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5615              		@ link register save eliminated.
+2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5616              		.loc 1 2313 3 view .LVU1609
+2318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 5617              		.loc 1 2318 1 is_stmt 0 view .LVU1610
+ 5618 0000 7047     		bx	lr
+ 5619              		.cfi_endproc
+ 5620              	.LFE175:
+ 5622              		.section	.text.TIMEx_DMACommutationCplt,"ax",%progbits
+ 5623              		.align	1
+ 5624              		.global	TIMEx_DMACommutationCplt
+ 5625              		.syntax unified
+ 5626              		.thumb
+ 5627              		.thumb_func
+ 5628              		.fpu fpv5-d16
+ 5630              	TIMEx_DMACommutationCplt:
+ 5631              	.LVL415:
+ 5632              	.LFB181:
+2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5633              		.loc 1 2432 1 is_stmt 1 view -0
+ 5634              		.cfi_startproc
+ 5635              		@ args = 0, pretend = 0, frame = 0
+ 5636              		@ frame_needed = 0, uses_anonymous_args = 0
+2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5637              		.loc 1 2432 1 is_stmt 0 view .LVU1612
+ 5638 0000 08B5     		push	{r3, lr}
+ 5639              	.LCFI44:
+ 5640              		.cfi_def_cfa_offset 8
+ 5641              		.cfi_offset 3, -8
+ 5642              		.cfi_offset 14, -4
+2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5643              		.loc 1 2433 3 is_stmt 1 view .LVU1613
+2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5644              		.loc 1 2433 22 is_stmt 0 view .LVU1614
+ 5645 0002 806B     		ldr	r0, [r0, #56]
+ARM GAS  /tmp/cc7KL1Mv.s 			page 172
+
+
+ 5646              	.LVL416:
+2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5647              		.loc 1 2436 3 is_stmt 1 view .LVU1615
+2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5648              		.loc 1 2436 15 is_stmt 0 view .LVU1616
+ 5649 0004 0123     		movs	r3, #1
+ 5650 0006 80F83D30 		strb	r3, [r0, #61]
+2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5651              		.loc 1 2441 3 is_stmt 1 view .LVU1617
+ 5652 000a FFF7FEFF 		bl	HAL_TIMEx_CommutCallback
+ 5653              	.LVL417:
+2443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5654              		.loc 1 2443 1 is_stmt 0 view .LVU1618
+ 5655 000e 08BD     		pop	{r3, pc}
+ 5656              		.cfi_endproc
+ 5657              	.LFE181:
+ 5659              		.section	.text.HAL_TIMEx_CommutHalfCpltCallback,"ax",%progbits
+ 5660              		.align	1
+ 5661              		.weak	HAL_TIMEx_CommutHalfCpltCallback
+ 5662              		.syntax unified
+ 5663              		.thumb
+ 5664              		.thumb_func
+ 5665              		.fpu fpv5-d16
+ 5667              	HAL_TIMEx_CommutHalfCpltCallback:
+ 5668              	.LVL418:
+ 5669              	.LFB176:
+2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 5670              		.loc 1 2325 1 is_stmt 1 view -0
+ 5671              		.cfi_startproc
+ 5672              		@ args = 0, pretend = 0, frame = 0
+ 5673              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5674              		@ link register save eliminated.
+2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5675              		.loc 1 2327 3 view .LVU1620
+2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5676              		.loc 1 2332 1 is_stmt 0 view .LVU1621
+ 5677 0000 7047     		bx	lr
+ 5678              		.cfi_endproc
+ 5679              	.LFE176:
+ 5681              		.section	.text.TIMEx_DMACommutationHalfCplt,"ax",%progbits
+ 5682              		.align	1
+ 5683              		.global	TIMEx_DMACommutationHalfCplt
+ 5684              		.syntax unified
+ 5685              		.thumb
+ 5686              		.thumb_func
+ 5687              		.fpu fpv5-d16
+ 5689              	TIMEx_DMACommutationHalfCplt:
+ 5690              	.LVL419:
+ 5691              	.LFB182:
+2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5692              		.loc 1 2451 1 is_stmt 1 view -0
+ 5693              		.cfi_startproc
+ 5694              		@ args = 0, pretend = 0, frame = 0
+ 5695              		@ frame_needed = 0, uses_anonymous_args = 0
+2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ 5696              		.loc 1 2451 1 is_stmt 0 view .LVU1623
+ 5697 0000 08B5     		push	{r3, lr}
+ARM GAS  /tmp/cc7KL1Mv.s 			page 173
+
+
+ 5698              	.LCFI45:
+ 5699              		.cfi_def_cfa_offset 8
+ 5700              		.cfi_offset 3, -8
+ 5701              		.cfi_offset 14, -4
+2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5702              		.loc 1 2452 3 is_stmt 1 view .LVU1624
+2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5703              		.loc 1 2452 22 is_stmt 0 view .LVU1625
+ 5704 0002 806B     		ldr	r0, [r0, #56]
+ 5705              	.LVL420:
+2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5706              		.loc 1 2455 3 is_stmt 1 view .LVU1626
+2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5707              		.loc 1 2455 15 is_stmt 0 view .LVU1627
+ 5708 0004 0123     		movs	r3, #1
+ 5709 0006 80F83D30 		strb	r3, [r0, #61]
+2460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ 5710              		.loc 1 2460 3 is_stmt 1 view .LVU1628
+ 5711 000a FFF7FEFF 		bl	HAL_TIMEx_CommutHalfCpltCallback
+ 5712              	.LVL421:
+2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5713              		.loc 1 2462 1 is_stmt 0 view .LVU1629
+ 5714 000e 08BD     		pop	{r3, pc}
+ 5715              		.cfi_endproc
+ 5716              	.LFE182:
+ 5718              		.section	.text.HAL_TIMEx_BreakCallback,"ax",%progbits
+ 5719              		.align	1
+ 5720              		.weak	HAL_TIMEx_BreakCallback
+ 5721              		.syntax unified
+ 5722              		.thumb
+ 5723              		.thumb_func
+ 5724              		.fpu fpv5-d16
+ 5726              	HAL_TIMEx_BreakCallback:
+ 5727              	.LVL422:
+ 5728              	.LFB177:
+2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 5729              		.loc 1 2340 1 is_stmt 1 view -0
+ 5730              		.cfi_startproc
+ 5731              		@ args = 0, pretend = 0, frame = 0
+ 5732              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5733              		@ link register save eliminated.
+2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5734              		.loc 1 2342 3 view .LVU1631
+2347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5735              		.loc 1 2347 1 is_stmt 0 view .LVU1632
+ 5736 0000 7047     		bx	lr
+ 5737              		.cfi_endproc
+ 5738              	.LFE177:
+ 5740              		.section	.text.HAL_TIMEx_Break2Callback,"ax",%progbits
+ 5741              		.align	1
+ 5742              		.weak	HAL_TIMEx_Break2Callback
+ 5743              		.syntax unified
+ 5744              		.thumb
+ 5745              		.thumb_func
+ 5746              		.fpu fpv5-d16
+ 5748              	HAL_TIMEx_Break2Callback:
+ 5749              	.LVL423:
+ARM GAS  /tmp/cc7KL1Mv.s 			page 174
+
+
+ 5750              	.LFB178:
+2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   /* Prevent unused argument(s) compilation warning */
+ 5751              		.loc 1 2355 1 is_stmt 1 view -0
+ 5752              		.cfi_startproc
+ 5753              		@ args = 0, pretend = 0, frame = 0
+ 5754              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5755              		@ link register save eliminated.
+2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5756              		.loc 1 2357 3 view .LVU1634
+2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 5757              		.loc 1 2362 1 is_stmt 0 view .LVU1635
+ 5758 0000 7047     		bx	lr
+ 5759              		.cfi_endproc
+ 5760              	.LFE178:
+ 5762              		.section	.text.HAL_TIMEx_HallSensor_GetState,"ax",%progbits
+ 5763              		.align	1
+ 5764              		.global	HAL_TIMEx_HallSensor_GetState
+ 5765              		.syntax unified
+ 5766              		.thumb
+ 5767              		.thumb_func
+ 5768              		.fpu fpv5-d16
+ 5770              	HAL_TIMEx_HallSensor_GetState:
+ 5771              	.LVL424:
+ 5772              	.LFB179:
+2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   return htim->State;
+ 5773              		.loc 1 2388 1 is_stmt 1 view -0
+ 5774              		.cfi_startproc
+ 5775              		@ args = 0, pretend = 0, frame = 0
+ 5776              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5777              		@ link register save eliminated.
+2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5778              		.loc 1 2389 3 view .LVU1637
+2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5779              		.loc 1 2389 14 is_stmt 0 view .LVU1638
+ 5780 0000 90F83D00 		ldrb	r0, [r0, #61]	@ zero_extendqisi2
+ 5781              	.LVL425:
+2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5782              		.loc 1 2390 1 view .LVU1639
+ 5783 0004 7047     		bx	lr
+ 5784              		.cfi_endproc
+ 5785              	.LFE179:
+ 5787              		.section	.text.HAL_TIMEx_GetChannelNState,"ax",%progbits
+ 5788              		.align	1
+ 5789              		.global	HAL_TIMEx_GetChannelNState
+ 5790              		.syntax unified
+ 5791              		.thumb
+ 5792              		.thumb_func
+ 5793              		.fpu fpv5-d16
+ 5795              	HAL_TIMEx_GetChannelNState:
+ 5796              	.LVL426:
+ 5797              	.LFB180:
+2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c ****   HAL_TIM_ChannelStateTypeDef channel_state;
+ 5798              		.loc 1 2403 1 is_stmt 1 view -0
+ 5799              		.cfi_startproc
+ 5800              		@ args = 0, pretend = 0, frame = 0
+ 5801              		@ frame_needed = 0, uses_anonymous_args = 0
+ 5802              		@ link register save eliminated.
+ARM GAS  /tmp/cc7KL1Mv.s 			page 175
+
+
+2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5803              		.loc 1 2404 3 view .LVU1641
+2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5804              		.loc 1 2407 3 view .LVU1642
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5805              		.loc 1 2409 3 view .LVU1643
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5806              		.loc 1 2409 19 is_stmt 0 view .LVU1644
+ 5807 0000 19B9     		cbnz	r1, .L440
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5808              		.loc 1 2409 19 discriminator 1 view .LVU1645
+ 5809 0002 90F84400 		ldrb	r0, [r0, #68]	@ zero_extendqisi2
+ 5810              	.LVL427:
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5811              		.loc 1 2409 19 discriminator 1 view .LVU1646
+ 5812 0006 C0B2     		uxtb	r0, r0
+ 5813 0008 7047     		bx	lr
+ 5814              	.LVL428:
+ 5815              	.L440:
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5816              		.loc 1 2409 19 discriminator 2 view .LVU1647
+ 5817 000a 0429     		cmp	r1, #4
+ 5818 000c 05D0     		beq	.L444
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5819              		.loc 1 2409 19 discriminator 5 view .LVU1648
+ 5820 000e 0829     		cmp	r1, #8
+ 5821 0010 07D0     		beq	.L445
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5822              		.loc 1 2409 19 discriminator 8 view .LVU1649
+ 5823 0012 90F84700 		ldrb	r0, [r0, #71]	@ zero_extendqisi2
+ 5824              	.LVL429:
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5825              		.loc 1 2409 19 discriminator 8 view .LVU1650
+ 5826 0016 C0B2     		uxtb	r0, r0
+ 5827              	.LVL430:
+2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** }
+ 5828              		.loc 1 2411 3 is_stmt 1 discriminator 8 view .LVU1651
+2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /**
+ 5829              		.loc 1 2412 1 is_stmt 0 discriminator 8 view .LVU1652
+ 5830 0018 7047     		bx	lr
+ 5831              	.LVL431:
+ 5832              	.L444:
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5833              		.loc 1 2409 19 discriminator 4 view .LVU1653
+ 5834 001a 90F84500 		ldrb	r0, [r0, #69]	@ zero_extendqisi2
+ 5835              	.LVL432:
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5836              		.loc 1 2409 19 discriminator 4 view .LVU1654
+ 5837 001e C0B2     		uxtb	r0, r0
+ 5838 0020 7047     		bx	lr
+ 5839              	.LVL433:
+ 5840              	.L445:
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ 5841              		.loc 1 2409 19 discriminator 7 view .LVU1655
+ 5842 0022 90F84600 		ldrb	r0, [r0, #70]	@ zero_extendqisi2
+ 5843              	.LVL434:
+2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** 
+ARM GAS  /tmp/cc7KL1Mv.s 			page 176
+
+
+ 5844              		.loc 1 2409 19 discriminator 7 view .LVU1656
+ 5845 0026 C0B2     		uxtb	r0, r0
+ 5846 0028 7047     		bx	lr
+ 5847              		.cfi_endproc
+ 5848              	.LFE180:
+ 5850              		.text
+ 5851              	.Letext0:
+ 5852              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 5853              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 5854              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 5855              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 5856              		.file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 5857              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h"
+ 5858              		.file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h"
+ARM GAS  /tmp/cc7KL1Mv.s 			page 177
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_hal_tim_ex.c
+     /tmp/cc7KL1Mv.s:17     .text.TIM_CCxNChannelCmd:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:24     .text.TIM_CCxNChannelCmd:0000000000000000 TIM_CCxNChannelCmd
+     /tmp/cc7KL1Mv.s:61     .text.TIM_DMAErrorCCxN:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:67     .text.TIM_DMAErrorCCxN:0000000000000000 TIM_DMAErrorCCxN
+     /tmp/cc7KL1Mv.s:147    .text.TIM_DMADelayPulseNCplt:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:153    .text.TIM_DMADelayPulseNCplt:0000000000000000 TIM_DMADelayPulseNCplt
+     /tmp/cc7KL1Mv.s:252    .text.HAL_TIMEx_HallSensor_MspInit:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:259    .text.HAL_TIMEx_HallSensor_MspInit:0000000000000000 HAL_TIMEx_HallSensor_MspInit
+     /tmp/cc7KL1Mv.s:274    .text.HAL_TIMEx_HallSensor_Init:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:281    .text.HAL_TIMEx_HallSensor_Init:0000000000000000 HAL_TIMEx_HallSensor_Init
+     /tmp/cc7KL1Mv.s:490    .text.HAL_TIMEx_HallSensor_Init:00000000000000d4 $d
+     /tmp/cc7KL1Mv.s:495    .text.HAL_TIMEx_HallSensor_MspDeInit:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:502    .text.HAL_TIMEx_HallSensor_MspDeInit:0000000000000000 HAL_TIMEx_HallSensor_MspDeInit
+     /tmp/cc7KL1Mv.s:517    .text.HAL_TIMEx_HallSensor_DeInit:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:524    .text.HAL_TIMEx_HallSensor_DeInit:0000000000000000 HAL_TIMEx_HallSensor_DeInit
+     /tmp/cc7KL1Mv.s:594    .text.HAL_TIMEx_HallSensor_Start:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:601    .text.HAL_TIMEx_HallSensor_Start:0000000000000000 HAL_TIMEx_HallSensor_Start
+     /tmp/cc7KL1Mv.s:762    .text.HAL_TIMEx_HallSensor_Start:00000000000000c0 $d
+     /tmp/cc7KL1Mv.s:768    .text.HAL_TIMEx_HallSensor_Stop:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:775    .text.HAL_TIMEx_HallSensor_Stop:0000000000000000 HAL_TIMEx_HallSensor_Stop
+     /tmp/cc7KL1Mv.s:834    .text.HAL_TIMEx_HallSensor_Start_IT:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:841    .text.HAL_TIMEx_HallSensor_Start_IT:0000000000000000 HAL_TIMEx_HallSensor_Start_IT
+     /tmp/cc7KL1Mv.s:1007   .text.HAL_TIMEx_HallSensor_Start_IT:00000000000000cc $d
+     /tmp/cc7KL1Mv.s:1013   .text.HAL_TIMEx_HallSensor_Stop_IT:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:1020   .text.HAL_TIMEx_HallSensor_Stop_IT:0000000000000000 HAL_TIMEx_HallSensor_Stop_IT
+     /tmp/cc7KL1Mv.s:1084   .text.HAL_TIMEx_HallSensor_Start_DMA:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:1091   .text.HAL_TIMEx_HallSensor_Start_DMA:0000000000000000 HAL_TIMEx_HallSensor_Start_DMA
+     /tmp/cc7KL1Mv.s:1283   .text.HAL_TIMEx_HallSensor_Start_DMA:00000000000000e8 $d
+     /tmp/cc7KL1Mv.s:1292   .text.HAL_TIMEx_HallSensor_Stop_DMA:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:1299   .text.HAL_TIMEx_HallSensor_Stop_DMA:0000000000000000 HAL_TIMEx_HallSensor_Stop_DMA
+     /tmp/cc7KL1Mv.s:1364   .text.HAL_TIMEx_OCN_Start:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:1371   .text.HAL_TIMEx_OCN_Start:0000000000000000 HAL_TIMEx_OCN_Start
+     /tmp/cc7KL1Mv.s:1562   .text.HAL_TIMEx_OCN_Start:00000000000000f8 $d
+     /tmp/cc7KL1Mv.s:1568   .text.HAL_TIMEx_OCN_Stop:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:1575   .text.HAL_TIMEx_OCN_Stop:0000000000000000 HAL_TIMEx_OCN_Stop
+     /tmp/cc7KL1Mv.s:1672   .text.HAL_TIMEx_OCN_Start_IT:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:1679   .text.HAL_TIMEx_OCN_Start_IT:0000000000000000 HAL_TIMEx_OCN_Start_IT
+     /tmp/cc7KL1Mv.s:1909   .text.HAL_TIMEx_OCN_Start_IT:0000000000000130 $d
+     /tmp/cc7KL1Mv.s:1915   .text.HAL_TIMEx_OCN_Stop_IT:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:1922   .text.HAL_TIMEx_OCN_Stop_IT:0000000000000000 HAL_TIMEx_OCN_Stop_IT
+     /tmp/cc7KL1Mv.s:2084   .text.HAL_TIMEx_OCN_Start_DMA:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:2091   .text.HAL_TIMEx_OCN_Start_DMA:0000000000000000 HAL_TIMEx_OCN_Start_DMA
+     /tmp/cc7KL1Mv.s:2515   .text.HAL_TIMEx_OCN_Start_DMA:000000000000020c $d
+     /tmp/cc7KL1Mv.s:2524   .text.HAL_TIMEx_OCN_Stop_DMA:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:2531   .text.HAL_TIMEx_OCN_Stop_DMA:0000000000000000 HAL_TIMEx_OCN_Stop_DMA
+     /tmp/cc7KL1Mv.s:2691   .text.HAL_TIMEx_PWMN_Start:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:2698   .text.HAL_TIMEx_PWMN_Start:0000000000000000 HAL_TIMEx_PWMN_Start
+     /tmp/cc7KL1Mv.s:2889   .text.HAL_TIMEx_PWMN_Start:00000000000000f8 $d
+     /tmp/cc7KL1Mv.s:2895   .text.HAL_TIMEx_PWMN_Stop:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:2902   .text.HAL_TIMEx_PWMN_Stop:0000000000000000 HAL_TIMEx_PWMN_Stop
+     /tmp/cc7KL1Mv.s:2999   .text.HAL_TIMEx_PWMN_Start_IT:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:3006   .text.HAL_TIMEx_PWMN_Start_IT:0000000000000000 HAL_TIMEx_PWMN_Start_IT
+     /tmp/cc7KL1Mv.s:3236   .text.HAL_TIMEx_PWMN_Start_IT:0000000000000130 $d
+     /tmp/cc7KL1Mv.s:3242   .text.HAL_TIMEx_PWMN_Stop_IT:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:3249   .text.HAL_TIMEx_PWMN_Stop_IT:0000000000000000 HAL_TIMEx_PWMN_Stop_IT
+ARM GAS  /tmp/cc7KL1Mv.s 			page 178
+
+
+     /tmp/cc7KL1Mv.s:3411   .text.HAL_TIMEx_PWMN_Start_DMA:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:3418   .text.HAL_TIMEx_PWMN_Start_DMA:0000000000000000 HAL_TIMEx_PWMN_Start_DMA
+     /tmp/cc7KL1Mv.s:3842   .text.HAL_TIMEx_PWMN_Start_DMA:000000000000020c $d
+     /tmp/cc7KL1Mv.s:3851   .text.HAL_TIMEx_PWMN_Stop_DMA:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:3858   .text.HAL_TIMEx_PWMN_Stop_DMA:0000000000000000 HAL_TIMEx_PWMN_Stop_DMA
+     /tmp/cc7KL1Mv.s:4018   .text.HAL_TIMEx_OnePulseN_Start:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:4025   .text.HAL_TIMEx_OnePulseN_Start:0000000000000000 HAL_TIMEx_OnePulseN_Start
+     /tmp/cc7KL1Mv.s:4148   .text.HAL_TIMEx_OnePulseN_Stop:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:4155   .text.HAL_TIMEx_OnePulseN_Stop:0000000000000000 HAL_TIMEx_OnePulseN_Stop
+     /tmp/cc7KL1Mv.s:4250   .text.HAL_TIMEx_OnePulseN_Start_IT:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:4257   .text.HAL_TIMEx_OnePulseN_Start_IT:0000000000000000 HAL_TIMEx_OnePulseN_Start_IT
+     /tmp/cc7KL1Mv.s:4391   .text.HAL_TIMEx_OnePulseN_Stop_IT:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:4398   .text.HAL_TIMEx_OnePulseN_Stop_IT:0000000000000000 HAL_TIMEx_OnePulseN_Stop_IT
+     /tmp/cc7KL1Mv.s:4503   .text.HAL_TIMEx_ConfigCommutEvent:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:4510   .text.HAL_TIMEx_ConfigCommutEvent:0000000000000000 HAL_TIMEx_ConfigCommutEvent
+     /tmp/cc7KL1Mv.s:4626   .text.HAL_TIMEx_ConfigCommutEvent_IT:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:4633   .text.HAL_TIMEx_ConfigCommutEvent_IT:0000000000000000 HAL_TIMEx_ConfigCommutEvent_IT
+     /tmp/cc7KL1Mv.s:4749   .text.HAL_TIMEx_ConfigCommutEvent_DMA:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:4756   .text.HAL_TIMEx_ConfigCommutEvent_DMA:0000000000000000 HAL_TIMEx_ConfigCommutEvent_DMA
+     /tmp/cc7KL1Mv.s:4889   .text.HAL_TIMEx_ConfigCommutEvent_DMA:000000000000008c $d
+     /tmp/cc7KL1Mv.s:5630   .text.TIMEx_DMACommutationCplt:0000000000000000 TIMEx_DMACommutationCplt
+     /tmp/cc7KL1Mv.s:5689   .text.TIMEx_DMACommutationHalfCplt:0000000000000000 TIMEx_DMACommutationHalfCplt
+     /tmp/cc7KL1Mv.s:4896   .text.HAL_TIMEx_MasterConfigSynchronization:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:4903   .text.HAL_TIMEx_MasterConfigSynchronization:0000000000000000 HAL_TIMEx_MasterConfigSynchronization
+     /tmp/cc7KL1Mv.s:5061   .text.HAL_TIMEx_MasterConfigSynchronization:0000000000000098 $d
+     /tmp/cc7KL1Mv.s:5067   .text.HAL_TIMEx_ConfigBreakDeadTime:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5074   .text.HAL_TIMEx_ConfigBreakDeadTime:0000000000000000 HAL_TIMEx_ConfigBreakDeadTime
+     /tmp/cc7KL1Mv.s:5242   .text.HAL_TIMEx_ConfigBreakDeadTime:0000000000000088 $d
+     /tmp/cc7KL1Mv.s:5248   .text.HAL_TIMEx_ConfigBreakInput:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5255   .text.HAL_TIMEx_ConfigBreakInput:0000000000000000 HAL_TIMEx_ConfigBreakInput
+     /tmp/cc7KL1Mv.s:5465   .text.HAL_TIMEx_RemapConfig:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5472   .text.HAL_TIMEx_RemapConfig:0000000000000000 HAL_TIMEx_RemapConfig
+     /tmp/cc7KL1Mv.s:5521   .text.HAL_TIMEx_GroupChannel5:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5528   .text.HAL_TIMEx_GroupChannel5:0000000000000000 HAL_TIMEx_GroupChannel5
+     /tmp/cc7KL1Mv.s:5601   .text.HAL_TIMEx_CommutCallback:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5608   .text.HAL_TIMEx_CommutCallback:0000000000000000 HAL_TIMEx_CommutCallback
+     /tmp/cc7KL1Mv.s:5623   .text.TIMEx_DMACommutationCplt:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5660   .text.HAL_TIMEx_CommutHalfCpltCallback:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5667   .text.HAL_TIMEx_CommutHalfCpltCallback:0000000000000000 HAL_TIMEx_CommutHalfCpltCallback
+     /tmp/cc7KL1Mv.s:5682   .text.TIMEx_DMACommutationHalfCplt:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5719   .text.HAL_TIMEx_BreakCallback:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5726   .text.HAL_TIMEx_BreakCallback:0000000000000000 HAL_TIMEx_BreakCallback
+     /tmp/cc7KL1Mv.s:5741   .text.HAL_TIMEx_Break2Callback:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5748   .text.HAL_TIMEx_Break2Callback:0000000000000000 HAL_TIMEx_Break2Callback
+     /tmp/cc7KL1Mv.s:5763   .text.HAL_TIMEx_HallSensor_GetState:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5770   .text.HAL_TIMEx_HallSensor_GetState:0000000000000000 HAL_TIMEx_HallSensor_GetState
+     /tmp/cc7KL1Mv.s:5788   .text.HAL_TIMEx_GetChannelNState:0000000000000000 $t
+     /tmp/cc7KL1Mv.s:5795   .text.HAL_TIMEx_GetChannelNState:0000000000000000 HAL_TIMEx_GetChannelNState
+
+UNDEFINED SYMBOLS
+HAL_TIM_ErrorCallback
+HAL_TIM_PWM_PulseFinishedCallback
+TIM_Base_SetConfig
+TIM_TI1_SetConfig
+TIM_OC2_SetConfig
+TIM_CCxChannelCmd
+HAL_DMA_Start_IT
+ARM GAS  /tmp/cc7KL1Mv.s 			page 179
+
+
+TIM_DMACaptureCplt
+TIM_DMACaptureHalfCplt
+TIM_DMAError
+HAL_DMA_Abort_IT
+TIM_DMADelayPulseHalfCplt
diff --git a/build/stm32f7xx_hal_tim_ex.o b/build/stm32f7xx_hal_tim_ex.o
new file mode 100644
index 0000000..76dbe1a
Binary files /dev/null and b/build/stm32f7xx_hal_tim_ex.o differ
diff --git a/build/stm32f7xx_it.d b/build/stm32f7xx_it.d
new file mode 100644
index 0000000..cb943c5
--- /dev/null
+++ b/build/stm32f7xx_it.d
@@ -0,0 +1,89 @@
+build/stm32f7xx_it.o: Src/stm32f7xx_it.c Inc/main.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/stm32f7xx_it.h
+Inc/main.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h:
+Inc/stm32f7xx_it.h:
diff --git a/build/stm32f7xx_it.lst b/build/stm32f7xx_it.lst
new file mode 100644
index 0000000..d6927c5
--- /dev/null
+++ b/build/stm32f7xx_it.lst
@@ -0,0 +1,13782 @@
+ARM GAS  /tmp/cc8Pc1nf.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_it.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.NMI_Handler,"ax",%progbits
+  17              		.align	1
+  18              		.global	NMI_Handler
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	NMI_Handler:
+  26              	.LFB1183:
+  27              		.file 1 "Src/stm32f7xx_it.c"
+   1:Src/stm32f7xx_it.c **** /* USER CODE BEGIN Header */
+   2:Src/stm32f7xx_it.c **** /**
+   3:Src/stm32f7xx_it.c ****   ******************************************************************************
+   4:Src/stm32f7xx_it.c ****   * @file    stm32f7xx_it.c
+   5:Src/stm32f7xx_it.c ****   * @brief   Interrupt Service Routines.
+   6:Src/stm32f7xx_it.c ****   ******************************************************************************
+   7:Src/stm32f7xx_it.c ****   * @attention
+   8:Src/stm32f7xx_it.c ****   *
+   9:Src/stm32f7xx_it.c ****   * Copyright (c) 2023 STMicroelectronics.
+  10:Src/stm32f7xx_it.c ****   * All rights reserved.
+  11:Src/stm32f7xx_it.c ****   *
+  12:Src/stm32f7xx_it.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Src/stm32f7xx_it.c ****   * in the root directory of this software component.
+  14:Src/stm32f7xx_it.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Src/stm32f7xx_it.c ****   *
+  16:Src/stm32f7xx_it.c ****   ******************************************************************************
+  17:Src/stm32f7xx_it.c ****   */
+  18:Src/stm32f7xx_it.c **** /* USER CODE END Header */
+  19:Src/stm32f7xx_it.c **** 
+  20:Src/stm32f7xx_it.c **** /* Includes ------------------------------------------------------------------*/
+  21:Src/stm32f7xx_it.c **** #include "main.h"
+  22:Src/stm32f7xx_it.c **** #include "stm32f7xx_it.h"
+  23:Src/stm32f7xx_it.c **** /* Private includes ----------------------------------------------------------*/
+  24:Src/stm32f7xx_it.c **** /* USER CODE BEGIN Includes */
+  25:Src/stm32f7xx_it.c **** /* USER CODE END Includes */
+  26:Src/stm32f7xx_it.c **** 
+  27:Src/stm32f7xx_it.c **** /* Private typedef -----------------------------------------------------------*/
+  28:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TD */
+  29:Src/stm32f7xx_it.c **** 
+  30:Src/stm32f7xx_it.c **** /* USER CODE END TD */
+  31:Src/stm32f7xx_it.c **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 2
+
+
+  32:Src/stm32f7xx_it.c **** /* Private define ------------------------------------------------------------*/
+  33:Src/stm32f7xx_it.c **** /* USER CODE BEGIN PD */
+  34:Src/stm32f7xx_it.c **** 
+  35:Src/stm32f7xx_it.c **** /* USER CODE END PD */
+  36:Src/stm32f7xx_it.c **** 
+  37:Src/stm32f7xx_it.c **** /* Private macro -------------------------------------------------------------*/
+  38:Src/stm32f7xx_it.c **** /* USER CODE BEGIN PM */
+  39:Src/stm32f7xx_it.c **** 
+  40:Src/stm32f7xx_it.c **** /* USER CODE END PM */
+  41:Src/stm32f7xx_it.c **** 
+  42:Src/stm32f7xx_it.c **** /* Private variables ---------------------------------------------------------*/
+  43:Src/stm32f7xx_it.c **** /* USER CODE BEGIN PV */
+  44:Src/stm32f7xx_it.c **** 	extern uint32_t TO6, TO7, TO6_uart, TO10, TO10_counter;
+  45:Src/stm32f7xx_it.c **** 	extern uint16_t UART_rec_incr, UART_header, COMMAND[CL_16];
+  46:Src/stm32f7xx_it.c **** 	extern uint8_t uart_buf, flg_tmt, CPU_state, State_Data[2], UART_transmission_request, u_tx_flg, T
+  47:Src/stm32f7xx_it.c **** 	extern  task_t task;
+  48:Src/stm32f7xx_it.c **** /* USER CODE END PV */
+  49:Src/stm32f7xx_it.c **** 
+  50:Src/stm32f7xx_it.c **** /* Private function prototypes -----------------------------------------------*/
+  51:Src/stm32f7xx_it.c **** /* USER CODE BEGIN PFP */
+  52:Src/stm32f7xx_it.c **** void UART_RxCpltCallback(void);
+  53:Src/stm32f7xx_it.c **** void DMA2_Stream7_TransferComplete(void);
+  54:Src/stm32f7xx_it.c **** /* USER CODE END PFP */
+  55:Src/stm32f7xx_it.c **** 
+  56:Src/stm32f7xx_it.c **** /* Private user code ---------------------------------------------------------*/
+  57:Src/stm32f7xx_it.c **** /* USER CODE BEGIN 0 */
+  58:Src/stm32f7xx_it.c **** 
+  59:Src/stm32f7xx_it.c **** /* USER CODE END 0 */
+  60:Src/stm32f7xx_it.c **** 
+  61:Src/stm32f7xx_it.c **** /* External variables --------------------------------------------------------*/
+  62:Src/stm32f7xx_it.c **** extern ADC_HandleTypeDef hadc1;
+  63:Src/stm32f7xx_it.c **** extern ADC_HandleTypeDef hadc3;
+  64:Src/stm32f7xx_it.c **** extern TIM_HandleTypeDef htim10;
+  65:Src/stm32f7xx_it.c **** /* USER CODE BEGIN EV */
+  66:Src/stm32f7xx_it.c **** 
+  67:Src/stm32f7xx_it.c **** /* USER CODE END EV */
+  68:Src/stm32f7xx_it.c **** 
+  69:Src/stm32f7xx_it.c **** /******************************************************************************/
+  70:Src/stm32f7xx_it.c **** /*           Cortex-M7 Processor Interruption and Exception Handlers          */
+  71:Src/stm32f7xx_it.c **** /******************************************************************************/
+  72:Src/stm32f7xx_it.c **** /**
+  73:Src/stm32f7xx_it.c ****   * @brief This function handles Non maskable interrupt.
+  74:Src/stm32f7xx_it.c ****   */
+  75:Src/stm32f7xx_it.c **** void NMI_Handler(void)
+  76:Src/stm32f7xx_it.c **** {
+  28              		.loc 1 76 1 view -0
+  29              		.cfi_startproc
+  30              		@ Volatile: function does not return.
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+  34              	.L2:
+  77:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+  78:Src/stm32f7xx_it.c **** 
+  79:Src/stm32f7xx_it.c ****   /* USER CODE END NonMaskableInt_IRQn 0 */
+  80:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+  81:Src/stm32f7xx_it.c ****   while (1)
+ARM GAS  /tmp/cc8Pc1nf.s 			page 3
+
+
+  35              		.loc 1 81 3 discriminator 1 view .LVU1
+  82:Src/stm32f7xx_it.c ****   {
+  83:Src/stm32f7xx_it.c ****   }
+  36              		.loc 1 83 3 discriminator 1 view .LVU2
+  81:Src/stm32f7xx_it.c ****   {
+  37              		.loc 1 81 9 discriminator 1 view .LVU3
+  38 0000 FEE7     		b	.L2
+  39              		.cfi_endproc
+  40              	.LFE1183:
+  42              		.section	.text.HardFault_Handler,"ax",%progbits
+  43              		.align	1
+  44              		.global	HardFault_Handler
+  45              		.syntax unified
+  46              		.thumb
+  47              		.thumb_func
+  48              		.fpu fpv5-d16
+  50              	HardFault_Handler:
+  51              	.LFB1184:
+  84:Src/stm32f7xx_it.c ****   /* USER CODE END NonMaskableInt_IRQn 1 */
+  85:Src/stm32f7xx_it.c **** }
+  86:Src/stm32f7xx_it.c **** 
+  87:Src/stm32f7xx_it.c **** /**
+  88:Src/stm32f7xx_it.c ****   * @brief This function handles Hard fault interrupt.
+  89:Src/stm32f7xx_it.c ****   */
+  90:Src/stm32f7xx_it.c **** void HardFault_Handler(void)
+  91:Src/stm32f7xx_it.c **** {
+  52              		.loc 1 91 1 view -0
+  53              		.cfi_startproc
+  54              		@ Volatile: function does not return.
+  55              		@ args = 0, pretend = 0, frame = 0
+  56              		@ frame_needed = 0, uses_anonymous_args = 0
+  57              		@ link register save eliminated.
+  58              	.L4:
+  92:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN HardFault_IRQn 0 */
+  93:Src/stm32f7xx_it.c **** 
+  94:Src/stm32f7xx_it.c ****   /* USER CODE END HardFault_IRQn 0 */
+  95:Src/stm32f7xx_it.c ****   while (1)
+  59              		.loc 1 95 3 discriminator 1 view .LVU5
+  96:Src/stm32f7xx_it.c ****   {
+  97:Src/stm32f7xx_it.c ****     /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+  98:Src/stm32f7xx_it.c ****     /* USER CODE END W1_HardFault_IRQn 0 */
+  99:Src/stm32f7xx_it.c ****   }
+  60              		.loc 1 99 3 discriminator 1 view .LVU6
+  95:Src/stm32f7xx_it.c ****   {
+  61              		.loc 1 95 9 discriminator 1 view .LVU7
+  62 0000 FEE7     		b	.L4
+  63              		.cfi_endproc
+  64              	.LFE1184:
+  66              		.section	.text.MemManage_Handler,"ax",%progbits
+  67              		.align	1
+  68              		.global	MemManage_Handler
+  69              		.syntax unified
+  70              		.thumb
+  71              		.thumb_func
+  72              		.fpu fpv5-d16
+  74              	MemManage_Handler:
+  75              	.LFB1185:
+ARM GAS  /tmp/cc8Pc1nf.s 			page 4
+
+
+ 100:Src/stm32f7xx_it.c **** }
+ 101:Src/stm32f7xx_it.c **** 
+ 102:Src/stm32f7xx_it.c **** /**
+ 103:Src/stm32f7xx_it.c ****   * @brief This function handles Memory management fault.
+ 104:Src/stm32f7xx_it.c ****   */
+ 105:Src/stm32f7xx_it.c **** void MemManage_Handler(void)
+ 106:Src/stm32f7xx_it.c **** {
+  76              		.loc 1 106 1 view -0
+  77              		.cfi_startproc
+  78              		@ Volatile: function does not return.
+  79              		@ args = 0, pretend = 0, frame = 0
+  80              		@ frame_needed = 0, uses_anonymous_args = 0
+  81              		@ link register save eliminated.
+  82              	.L6:
+ 107:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+ 108:Src/stm32f7xx_it.c **** 
+ 109:Src/stm32f7xx_it.c ****   /* USER CODE END MemoryManagement_IRQn 0 */
+ 110:Src/stm32f7xx_it.c ****   while (1)
+  83              		.loc 1 110 3 discriminator 1 view .LVU9
+ 111:Src/stm32f7xx_it.c ****   {
+ 112:Src/stm32f7xx_it.c ****     /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ 113:Src/stm32f7xx_it.c ****     /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ 114:Src/stm32f7xx_it.c ****   }
+  84              		.loc 1 114 3 discriminator 1 view .LVU10
+ 110:Src/stm32f7xx_it.c ****   {
+  85              		.loc 1 110 9 discriminator 1 view .LVU11
+  86 0000 FEE7     		b	.L6
+  87              		.cfi_endproc
+  88              	.LFE1185:
+  90              		.section	.text.BusFault_Handler,"ax",%progbits
+  91              		.align	1
+  92              		.global	BusFault_Handler
+  93              		.syntax unified
+  94              		.thumb
+  95              		.thumb_func
+  96              		.fpu fpv5-d16
+  98              	BusFault_Handler:
+  99              	.LFB1186:
+ 115:Src/stm32f7xx_it.c **** }
+ 116:Src/stm32f7xx_it.c **** 
+ 117:Src/stm32f7xx_it.c **** /**
+ 118:Src/stm32f7xx_it.c ****   * @brief This function handles Pre-fetch fault, memory access fault.
+ 119:Src/stm32f7xx_it.c ****   */
+ 120:Src/stm32f7xx_it.c **** void BusFault_Handler(void)
+ 121:Src/stm32f7xx_it.c **** {
+ 100              		.loc 1 121 1 view -0
+ 101              		.cfi_startproc
+ 102              		@ Volatile: function does not return.
+ 103              		@ args = 0, pretend = 0, frame = 0
+ 104              		@ frame_needed = 0, uses_anonymous_args = 0
+ 105              		@ link register save eliminated.
+ 106              	.L8:
+ 122:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN BusFault_IRQn 0 */
+ 123:Src/stm32f7xx_it.c **** 
+ 124:Src/stm32f7xx_it.c ****   /* USER CODE END BusFault_IRQn 0 */
+ 125:Src/stm32f7xx_it.c ****   while (1)
+ 107              		.loc 1 125 3 discriminator 1 view .LVU13
+ARM GAS  /tmp/cc8Pc1nf.s 			page 5
+
+
+ 126:Src/stm32f7xx_it.c ****   {
+ 127:Src/stm32f7xx_it.c ****     /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ 128:Src/stm32f7xx_it.c ****     /* USER CODE END W1_BusFault_IRQn 0 */
+ 129:Src/stm32f7xx_it.c ****   }
+ 108              		.loc 1 129 3 discriminator 1 view .LVU14
+ 125:Src/stm32f7xx_it.c ****   {
+ 109              		.loc 1 125 9 discriminator 1 view .LVU15
+ 110 0000 FEE7     		b	.L8
+ 111              		.cfi_endproc
+ 112              	.LFE1186:
+ 114              		.section	.text.UsageFault_Handler,"ax",%progbits
+ 115              		.align	1
+ 116              		.global	UsageFault_Handler
+ 117              		.syntax unified
+ 118              		.thumb
+ 119              		.thumb_func
+ 120              		.fpu fpv5-d16
+ 122              	UsageFault_Handler:
+ 123              	.LFB1187:
+ 130:Src/stm32f7xx_it.c **** }
+ 131:Src/stm32f7xx_it.c **** 
+ 132:Src/stm32f7xx_it.c **** /**
+ 133:Src/stm32f7xx_it.c ****   * @brief This function handles Undefined instruction or illegal state.
+ 134:Src/stm32f7xx_it.c ****   */
+ 135:Src/stm32f7xx_it.c **** void UsageFault_Handler(void)
+ 136:Src/stm32f7xx_it.c **** {
+ 124              		.loc 1 136 1 view -0
+ 125              		.cfi_startproc
+ 126              		@ Volatile: function does not return.
+ 127              		@ args = 0, pretend = 0, frame = 0
+ 128              		@ frame_needed = 0, uses_anonymous_args = 0
+ 129              		@ link register save eliminated.
+ 130              	.L10:
+ 137:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN UsageFault_IRQn 0 */
+ 138:Src/stm32f7xx_it.c **** 
+ 139:Src/stm32f7xx_it.c ****   /* USER CODE END UsageFault_IRQn 0 */
+ 140:Src/stm32f7xx_it.c ****   while (1)
+ 131              		.loc 1 140 3 discriminator 1 view .LVU17
+ 141:Src/stm32f7xx_it.c ****   {
+ 142:Src/stm32f7xx_it.c ****     /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ 143:Src/stm32f7xx_it.c ****     /* USER CODE END W1_UsageFault_IRQn 0 */
+ 144:Src/stm32f7xx_it.c ****   }
+ 132              		.loc 1 144 3 discriminator 1 view .LVU18
+ 140:Src/stm32f7xx_it.c ****   {
+ 133              		.loc 1 140 9 discriminator 1 view .LVU19
+ 134 0000 FEE7     		b	.L10
+ 135              		.cfi_endproc
+ 136              	.LFE1187:
+ 138              		.section	.text.SVC_Handler,"ax",%progbits
+ 139              		.align	1
+ 140              		.global	SVC_Handler
+ 141              		.syntax unified
+ 142              		.thumb
+ 143              		.thumb_func
+ 144              		.fpu fpv5-d16
+ 146              	SVC_Handler:
+ 147              	.LFB1188:
+ARM GAS  /tmp/cc8Pc1nf.s 			page 6
+
+
+ 145:Src/stm32f7xx_it.c **** }
+ 146:Src/stm32f7xx_it.c **** 
+ 147:Src/stm32f7xx_it.c **** /**
+ 148:Src/stm32f7xx_it.c ****   * @brief This function handles System service call via SWI instruction.
+ 149:Src/stm32f7xx_it.c ****   */
+ 150:Src/stm32f7xx_it.c **** void SVC_Handler(void)
+ 151:Src/stm32f7xx_it.c **** {
+ 148              		.loc 1 151 1 view -0
+ 149              		.cfi_startproc
+ 150              		@ args = 0, pretend = 0, frame = 0
+ 151              		@ frame_needed = 0, uses_anonymous_args = 0
+ 152              		@ link register save eliminated.
+ 152:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN SVCall_IRQn 0 */
+ 153:Src/stm32f7xx_it.c **** 
+ 154:Src/stm32f7xx_it.c ****   /* USER CODE END SVCall_IRQn 0 */
+ 155:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN SVCall_IRQn 1 */
+ 156:Src/stm32f7xx_it.c **** 
+ 157:Src/stm32f7xx_it.c ****   /* USER CODE END SVCall_IRQn 1 */
+ 158:Src/stm32f7xx_it.c **** }
+ 153              		.loc 1 158 1 view .LVU21
+ 154 0000 7047     		bx	lr
+ 155              		.cfi_endproc
+ 156              	.LFE1188:
+ 158              		.section	.text.DebugMon_Handler,"ax",%progbits
+ 159              		.align	1
+ 160              		.global	DebugMon_Handler
+ 161              		.syntax unified
+ 162              		.thumb
+ 163              		.thumb_func
+ 164              		.fpu fpv5-d16
+ 166              	DebugMon_Handler:
+ 167              	.LFB1189:
+ 159:Src/stm32f7xx_it.c **** 
+ 160:Src/stm32f7xx_it.c **** /**
+ 161:Src/stm32f7xx_it.c ****   * @brief This function handles Debug monitor.
+ 162:Src/stm32f7xx_it.c ****   */
+ 163:Src/stm32f7xx_it.c **** void DebugMon_Handler(void)
+ 164:Src/stm32f7xx_it.c **** {
+ 168              		.loc 1 164 1 view -0
+ 169              		.cfi_startproc
+ 170              		@ args = 0, pretend = 0, frame = 0
+ 171              		@ frame_needed = 0, uses_anonymous_args = 0
+ 172              		@ link register save eliminated.
+ 165:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+ 166:Src/stm32f7xx_it.c **** 
+ 167:Src/stm32f7xx_it.c ****   /* USER CODE END DebugMonitor_IRQn 0 */
+ 168:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+ 169:Src/stm32f7xx_it.c **** 
+ 170:Src/stm32f7xx_it.c ****   /* USER CODE END DebugMonitor_IRQn 1 */
+ 171:Src/stm32f7xx_it.c **** }
+ 173              		.loc 1 171 1 view .LVU23
+ 174 0000 7047     		bx	lr
+ 175              		.cfi_endproc
+ 176              	.LFE1189:
+ 178              		.section	.text.PendSV_Handler,"ax",%progbits
+ 179              		.align	1
+ 180              		.global	PendSV_Handler
+ARM GAS  /tmp/cc8Pc1nf.s 			page 7
+
+
+ 181              		.syntax unified
+ 182              		.thumb
+ 183              		.thumb_func
+ 184              		.fpu fpv5-d16
+ 186              	PendSV_Handler:
+ 187              	.LFB1190:
+ 172:Src/stm32f7xx_it.c **** 
+ 173:Src/stm32f7xx_it.c **** /**
+ 174:Src/stm32f7xx_it.c ****   * @brief This function handles Pendable request for system service.
+ 175:Src/stm32f7xx_it.c ****   */
+ 176:Src/stm32f7xx_it.c **** void PendSV_Handler(void)
+ 177:Src/stm32f7xx_it.c **** {
+ 188              		.loc 1 177 1 view -0
+ 189              		.cfi_startproc
+ 190              		@ args = 0, pretend = 0, frame = 0
+ 191              		@ frame_needed = 0, uses_anonymous_args = 0
+ 192              		@ link register save eliminated.
+ 178:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN PendSV_IRQn 0 */
+ 179:Src/stm32f7xx_it.c **** 
+ 180:Src/stm32f7xx_it.c ****   /* USER CODE END PendSV_IRQn 0 */
+ 181:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN PendSV_IRQn 1 */
+ 182:Src/stm32f7xx_it.c **** 
+ 183:Src/stm32f7xx_it.c ****   /* USER CODE END PendSV_IRQn 1 */
+ 184:Src/stm32f7xx_it.c **** }
+ 193              		.loc 1 184 1 view .LVU25
+ 194 0000 7047     		bx	lr
+ 195              		.cfi_endproc
+ 196              	.LFE1190:
+ 198              		.section	.text.SysTick_Handler,"ax",%progbits
+ 199              		.align	1
+ 200              		.global	SysTick_Handler
+ 201              		.syntax unified
+ 202              		.thumb
+ 203              		.thumb_func
+ 204              		.fpu fpv5-d16
+ 206              	SysTick_Handler:
+ 207              	.LFB1191:
+ 185:Src/stm32f7xx_it.c **** 
+ 186:Src/stm32f7xx_it.c **** /**
+ 187:Src/stm32f7xx_it.c ****   * @brief This function handles System tick timer.
+ 188:Src/stm32f7xx_it.c ****   */
+ 189:Src/stm32f7xx_it.c **** void SysTick_Handler(void)
+ 190:Src/stm32f7xx_it.c **** {
+ 208              		.loc 1 190 1 view -0
+ 209              		.cfi_startproc
+ 210              		@ args = 0, pretend = 0, frame = 0
+ 211              		@ frame_needed = 0, uses_anonymous_args = 0
+ 212 0000 08B5     		push	{r3, lr}
+ 213              	.LCFI0:
+ 214              		.cfi_def_cfa_offset 8
+ 215              		.cfi_offset 3, -8
+ 216              		.cfi_offset 14, -4
+ 191:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN SysTick_IRQn 0 */
+ 192:Src/stm32f7xx_it.c **** 
+ 193:Src/stm32f7xx_it.c ****   /* USER CODE END SysTick_IRQn 0 */
+ 194:Src/stm32f7xx_it.c ****   HAL_IncTick();
+ 217              		.loc 1 194 3 view .LVU27
+ARM GAS  /tmp/cc8Pc1nf.s 			page 8
+
+
+ 218 0002 FFF7FEFF 		bl	HAL_IncTick
+ 219              	.LVL0:
+ 195:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN SysTick_IRQn 1 */
+ 196:Src/stm32f7xx_it.c **** 
+ 197:Src/stm32f7xx_it.c ****   /* USER CODE END SysTick_IRQn 1 */
+ 198:Src/stm32f7xx_it.c **** }
+ 220              		.loc 1 198 1 is_stmt 0 view .LVU28
+ 221 0006 08BD     		pop	{r3, pc}
+ 222              		.cfi_endproc
+ 223              	.LFE1191:
+ 225              		.section	.text.ADC_IRQHandler,"ax",%progbits
+ 226              		.align	1
+ 227              		.global	ADC_IRQHandler
+ 228              		.syntax unified
+ 229              		.thumb
+ 230              		.thumb_func
+ 231              		.fpu fpv5-d16
+ 233              	ADC_IRQHandler:
+ 234              	.LFB1192:
+ 199:Src/stm32f7xx_it.c **** 
+ 200:Src/stm32f7xx_it.c **** /******************************************************************************/
+ 201:Src/stm32f7xx_it.c **** /* STM32F7xx Peripheral Interrupt Handlers                                    */
+ 202:Src/stm32f7xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals.                  */
+ 203:Src/stm32f7xx_it.c **** /* For the available peripheral interrupt handler names,                      */
+ 204:Src/stm32f7xx_it.c **** /* please refer to the startup file (startup_stm32f7xx.s).                    */
+ 205:Src/stm32f7xx_it.c **** /******************************************************************************/
+ 206:Src/stm32f7xx_it.c **** 
+ 207:Src/stm32f7xx_it.c **** /**
+ 208:Src/stm32f7xx_it.c ****   * @brief This function handles ADC1, ADC2 and ADC3 global interrupts.
+ 209:Src/stm32f7xx_it.c ****   */
+ 210:Src/stm32f7xx_it.c **** void ADC_IRQHandler(void)
+ 211:Src/stm32f7xx_it.c **** {
+ 235              		.loc 1 211 1 is_stmt 1 view -0
+ 236              		.cfi_startproc
+ 237              		@ args = 0, pretend = 0, frame = 0
+ 238              		@ frame_needed = 0, uses_anonymous_args = 0
+ 239 0000 08B5     		push	{r3, lr}
+ 240              	.LCFI1:
+ 241              		.cfi_def_cfa_offset 8
+ 242              		.cfi_offset 3, -8
+ 243              		.cfi_offset 14, -4
+ 212:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN ADC_IRQn 0 */
+ 213:Src/stm32f7xx_it.c **** 
+ 214:Src/stm32f7xx_it.c ****   /* USER CODE END ADC_IRQn 0 */
+ 215:Src/stm32f7xx_it.c ****   HAL_ADC_IRQHandler(&hadc1);
+ 244              		.loc 1 215 3 view .LVU30
+ 245 0002 0348     		ldr	r0, .L18
+ 246 0004 FFF7FEFF 		bl	HAL_ADC_IRQHandler
+ 247              	.LVL1:
+ 216:Src/stm32f7xx_it.c ****   HAL_ADC_IRQHandler(&hadc3);
+ 248              		.loc 1 216 3 view .LVU31
+ 249 0008 0248     		ldr	r0, .L18+4
+ 250 000a FFF7FEFF 		bl	HAL_ADC_IRQHandler
+ 251              	.LVL2:
+ 217:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN ADC_IRQn 1 */
+ 218:Src/stm32f7xx_it.c **** 
+ 219:Src/stm32f7xx_it.c ****   /* USER CODE END ADC_IRQn 1 */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 9
+
+
+ 220:Src/stm32f7xx_it.c **** }
+ 252              		.loc 1 220 1 is_stmt 0 view .LVU32
+ 253 000e 08BD     		pop	{r3, pc}
+ 254              	.L19:
+ 255              		.align	2
+ 256              	.L18:
+ 257 0010 00000000 		.word	hadc1
+ 258 0014 00000000 		.word	hadc3
+ 259              		.cfi_endproc
+ 260              	.LFE1192:
+ 262              		.section	.text.TIM1_UP_TIM10_IRQHandler,"ax",%progbits
+ 263              		.align	1
+ 264              		.global	TIM1_UP_TIM10_IRQHandler
+ 265              		.syntax unified
+ 266              		.thumb
+ 267              		.thumb_func
+ 268              		.fpu fpv5-d16
+ 270              	TIM1_UP_TIM10_IRQHandler:
+ 271              	.LFB1193:
+ 221:Src/stm32f7xx_it.c **** 
+ 222:Src/stm32f7xx_it.c **** /**
+ 223:Src/stm32f7xx_it.c ****   * @brief This function handles TIM1 update interrupt and TIM10 global interrupt.
+ 224:Src/stm32f7xx_it.c ****   */
+ 225:Src/stm32f7xx_it.c **** void TIM1_UP_TIM10_IRQHandler(void)
+ 226:Src/stm32f7xx_it.c **** {
+ 272              		.loc 1 226 1 is_stmt 1 view -0
+ 273              		.cfi_startproc
+ 274              		@ args = 0, pretend = 0, frame = 0
+ 275              		@ frame_needed = 0, uses_anonymous_args = 0
+ 276 0000 08B5     		push	{r3, lr}
+ 277              	.LCFI2:
+ 278              		.cfi_def_cfa_offset 8
+ 279              		.cfi_offset 3, -8
+ 280              		.cfi_offset 14, -4
+ 227:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */
+ 228:Src/stm32f7xx_it.c **** 	TO10++;
+ 281              		.loc 1 228 2 view .LVU34
+ 282              		.loc 1 228 6 is_stmt 0 view .LVU35
+ 283 0002 084A     		ldr	r2, .L24
+ 284 0004 1368     		ldr	r3, [r2]
+ 285 0006 0133     		adds	r3, r3, #1
+ 286 0008 1360     		str	r3, [r2]
+ 229:Src/stm32f7xx_it.c **** 	if (TO10 == TO10_counter)
+ 287              		.loc 1 229 2 is_stmt 1 view .LVU36
+ 288              		.loc 1 229 11 is_stmt 0 view .LVU37
+ 289 000a 074A     		ldr	r2, .L24+4
+ 290 000c 1268     		ldr	r2, [r2]
+ 291              		.loc 1 229 5 view .LVU38
+ 292 000e 9342     		cmp	r3, r2
+ 293 0010 03D0     		beq	.L23
+ 294              	.L21:
+ 230:Src/stm32f7xx_it.c **** 		TIM10_coflag = 1;
+ 231:Src/stm32f7xx_it.c ****   /* USER CODE END TIM1_UP_TIM10_IRQn 0 */
+ 232:Src/stm32f7xx_it.c ****   HAL_TIM_IRQHandler(&htim10);
+ 295              		.loc 1 232 3 is_stmt 1 view .LVU39
+ 296 0012 0648     		ldr	r0, .L24+8
+ 297 0014 FFF7FEFF 		bl	HAL_TIM_IRQHandler
+ARM GAS  /tmp/cc8Pc1nf.s 			page 10
+
+
+ 298              	.LVL3:
+ 233:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */
+ 234:Src/stm32f7xx_it.c **** 
+ 235:Src/stm32f7xx_it.c ****   /* USER CODE END TIM1_UP_TIM10_IRQn 1 */
+ 236:Src/stm32f7xx_it.c **** }
+ 299              		.loc 1 236 1 is_stmt 0 view .LVU40
+ 300 0018 08BD     		pop	{r3, pc}
+ 301              	.L23:
+ 230:Src/stm32f7xx_it.c **** 		TIM10_coflag = 1;
+ 302              		.loc 1 230 3 is_stmt 1 view .LVU41
+ 230:Src/stm32f7xx_it.c **** 		TIM10_coflag = 1;
+ 303              		.loc 1 230 16 is_stmt 0 view .LVU42
+ 304 001a 054B     		ldr	r3, .L24+12
+ 305 001c 0122     		movs	r2, #1
+ 306 001e 1A70     		strb	r2, [r3]
+ 307 0020 F7E7     		b	.L21
+ 308              	.L25:
+ 309 0022 00BF     		.align	2
+ 310              	.L24:
+ 311 0024 00000000 		.word	TO10
+ 312 0028 00000000 		.word	TO10_counter
+ 313 002c 00000000 		.word	htim10
+ 314 0030 00000000 		.word	TIM10_coflag
+ 315              		.cfi_endproc
+ 316              	.LFE1193:
+ 318              		.section	.text.TIM2_IRQHandler,"ax",%progbits
+ 319              		.align	1
+ 320              		.global	TIM2_IRQHandler
+ 321              		.syntax unified
+ 322              		.thumb
+ 323              		.thumb_func
+ 324              		.fpu fpv5-d16
+ 326              	TIM2_IRQHandler:
+ 327              	.LFB1194:
+ 237:Src/stm32f7xx_it.c **** 
+ 238:Src/stm32f7xx_it.c **** /**
+ 239:Src/stm32f7xx_it.c ****   * @brief This function handles TIM2 global interrupt.
+ 240:Src/stm32f7xx_it.c ****   */
+ 241:Src/stm32f7xx_it.c **** void TIM2_IRQHandler(void)
+ 242:Src/stm32f7xx_it.c **** {
+ 328              		.loc 1 242 1 is_stmt 1 view -0
+ 329              		.cfi_startproc
+ 330              		@ args = 0, pretend = 0, frame = 0
+ 331              		@ frame_needed = 0, uses_anonymous_args = 0
+ 332              		@ link register save eliminated.
+ 243:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN TIM2_IRQn 0 */
+ 244:Src/stm32f7xx_it.c **** 
+ 245:Src/stm32f7xx_it.c ****   /* USER CODE END TIM2_IRQn 0 */
+ 246:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN TIM2_IRQn 1 */
+ 247:Src/stm32f7xx_it.c **** 
+ 248:Src/stm32f7xx_it.c ****   /* USER CODE END TIM2_IRQn 1 */
+ 249:Src/stm32f7xx_it.c **** }
+ 333              		.loc 1 249 1 view .LVU44
+ 334 0000 7047     		bx	lr
+ 335              		.cfi_endproc
+ 336              	.LFE1194:
+ 338              		.section	.text.TIM5_IRQHandler,"ax",%progbits
+ARM GAS  /tmp/cc8Pc1nf.s 			page 11
+
+
+ 339              		.align	1
+ 340              		.global	TIM5_IRQHandler
+ 341              		.syntax unified
+ 342              		.thumb
+ 343              		.thumb_func
+ 344              		.fpu fpv5-d16
+ 346              	TIM5_IRQHandler:
+ 347              	.LFB1196:
+ 250:Src/stm32f7xx_it.c **** 
+ 251:Src/stm32f7xx_it.c **** /**
+ 252:Src/stm32f7xx_it.c ****   * @brief This function handles USART1 global interrupt.
+ 253:Src/stm32f7xx_it.c ****   */
+ 254:Src/stm32f7xx_it.c **** void USART1_IRQHandler(void)
+ 255:Src/stm32f7xx_it.c **** {
+ 256:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN USART1_IRQn 0 */
+ 257:Src/stm32f7xx_it.c ****   volatile uint8_t temp;
+ 258:Src/stm32f7xx_it.c ****   if(LL_USART_IsActiveFlag_RXNE(USART1) && LL_USART_IsEnabledIT_RXNE(USART1))
+ 259:Src/stm32f7xx_it.c ****   {
+ 260:Src/stm32f7xx_it.c ****     UART_RxCpltCallback();
+ 261:Src/stm32f7xx_it.c ****   }
+ 262:Src/stm32f7xx_it.c ****   else
+ 263:Src/stm32f7xx_it.c ****   {
+ 264:Src/stm32f7xx_it.c ****     if(LL_USART_IsActiveFlag_ORE(USART1))
+ 265:Src/stm32f7xx_it.c ****     {
+ 266:Src/stm32f7xx_it.c ****       //temp = USART1->RDR;
+ 267:Src/stm32f7xx_it.c ****       temp+= LL_USART_ReceiveData8(USART1);
+ 268:Src/stm32f7xx_it.c ****     }
+ 269:Src/stm32f7xx_it.c ****     else if(LL_USART_IsActiveFlag_FE(USART1))
+ 270:Src/stm32f7xx_it.c ****     {
+ 271:Src/stm32f7xx_it.c ****       //(void) USART1->RDR;
+ 272:Src/stm32f7xx_it.c ****       temp+= LL_USART_ReceiveData8(USART1);
+ 273:Src/stm32f7xx_it.c ****     }
+ 274:Src/stm32f7xx_it.c ****     else if(LL_USART_IsActiveFlag_NE(USART1))
+ 275:Src/stm32f7xx_it.c ****     {
+ 276:Src/stm32f7xx_it.c ****       //(void) USART1->RDR;
+ 277:Src/stm32f7xx_it.c ****       temp+= LL_USART_ReceiveData8(USART1);
+ 278:Src/stm32f7xx_it.c ****     }
+ 279:Src/stm32f7xx_it.c ****     else if(LL_USART_IsActiveFlag_PE(USART1))
+ 280:Src/stm32f7xx_it.c ****     {
+ 281:Src/stm32f7xx_it.c ****       //(void) USART1->RDR;
+ 282:Src/stm32f7xx_it.c ****       temp+= LL_USART_ReceiveData8(USART1);
+ 283:Src/stm32f7xx_it.c ****     }
+ 284:Src/stm32f7xx_it.c ****     else
+ 285:Src/stm32f7xx_it.c ****     {
+ 286:Src/stm32f7xx_it.c ****       if(LL_USART_IsActiveFlag_TC(USART6) && LL_USART_IsEnabledIT_TC(USART6))
+ 287:Src/stm32f7xx_it.c ****       {		
+ 288:Src/stm32f7xx_it.c ****         LL_USART_ClearFlag_TC(USART1);
+ 289:Src/stm32f7xx_it.c ****         //test_counter += 1;
+ 290:Src/stm32f7xx_it.c ****         //if(UART_transmission_busy == 1){
+ 291:Src/stm32f7xx_it.c ****         LL_USART_DisableIT_TC(USART1);
+ 292:Src/stm32f7xx_it.c ****         //UART_transmission_busy = 0;
+ 293:Src/stm32f7xx_it.c ****       }
+ 294:Src/stm32f7xx_it.c ****     }
+ 295:Src/stm32f7xx_it.c ****   }
+ 296:Src/stm32f7xx_it.c **** 	
+ 297:Src/stm32f7xx_it.c ****   /* USER CODE END USART1_IRQn 0 */
+ 298:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN USART1_IRQn 1 */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 12
+
+
+ 299:Src/stm32f7xx_it.c **** 
+ 300:Src/stm32f7xx_it.c ****   /* USER CODE END USART1_IRQn 1 */
+ 301:Src/stm32f7xx_it.c **** }
+ 302:Src/stm32f7xx_it.c **** 
+ 303:Src/stm32f7xx_it.c **** /**
+ 304:Src/stm32f7xx_it.c ****   * @brief This function handles TIM5 global interrupt.
+ 305:Src/stm32f7xx_it.c ****   */
+ 306:Src/stm32f7xx_it.c **** void TIM5_IRQHandler(void)
+ 307:Src/stm32f7xx_it.c **** {
+ 348              		.loc 1 307 1 view -0
+ 349              		.cfi_startproc
+ 350              		@ args = 0, pretend = 0, frame = 0
+ 351              		@ frame_needed = 0, uses_anonymous_args = 0
+ 352              		@ link register save eliminated.
+ 308:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN TIM5_IRQn 0 */
+ 309:Src/stm32f7xx_it.c **** 
+ 310:Src/stm32f7xx_it.c ****   /* USER CODE END TIM5_IRQn 0 */
+ 311:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN TIM5_IRQn 1 */
+ 312:Src/stm32f7xx_it.c **** 
+ 313:Src/stm32f7xx_it.c ****   /* USER CODE END TIM5_IRQn 1 */
+ 314:Src/stm32f7xx_it.c **** }
+ 353              		.loc 1 314 1 view .LVU46
+ 354 0000 7047     		bx	lr
+ 355              		.cfi_endproc
+ 356              	.LFE1196:
+ 358              		.section	.text.TIM6_DAC_IRQHandler,"ax",%progbits
+ 359              		.align	1
+ 360              		.global	TIM6_DAC_IRQHandler
+ 361              		.syntax unified
+ 362              		.thumb
+ 363              		.thumb_func
+ 364              		.fpu fpv5-d16
+ 366              	TIM6_DAC_IRQHandler:
+ 367              	.LFB1197:
+ 315:Src/stm32f7xx_it.c **** 
+ 316:Src/stm32f7xx_it.c **** /**
+ 317:Src/stm32f7xx_it.c ****   * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
+ 318:Src/stm32f7xx_it.c ****   */
+ 319:Src/stm32f7xx_it.c **** void TIM6_DAC_IRQHandler(void)
+ 320:Src/stm32f7xx_it.c **** {
+ 368              		.loc 1 320 1 view -0
+ 369              		.cfi_startproc
+ 370              		@ args = 0, pretend = 0, frame = 0
+ 371              		@ frame_needed = 0, uses_anonymous_args = 0
+ 372 0000 08B5     		push	{r3, lr}
+ 373              	.LCFI3:
+ 374              		.cfi_def_cfa_offset 8
+ 375              		.cfi_offset 3, -8
+ 376              		.cfi_offset 14, -4
+ 321:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
+ 322:Src/stm32f7xx_it.c **** 
+ 323:Src/stm32f7xx_it.c ****   /* USER CODE END TIM6_DAC_IRQn 0 */
+ 324:Src/stm32f7xx_it.c **** 
+ 325:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
+ 326:Src/stm32f7xx_it.c ****   if(LL_TIM_IsActiveFlag_UPDATE(TIM6))
+ 377              		.loc 1 326 3 view .LVU48
+ 378              	.LVL4:
+ARM GAS  /tmp/cc8Pc1nf.s 			page 13
+
+
+ 379              	.LBB58:
+ 380              	.LBI58:
+ 381              		.file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @file    stm32f7xx_ll_tim.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief   Header file of TIM LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifndef __STM32F7xx_LL_TIM_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __STM32F7xx_LL_TIM_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defi
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL TIM
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] =
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 0: TIMx_CH1  */
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 1: TIMx_CH1N */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 2: TIMx_CH2  */
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 3: TIMx_CH2N */
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x04U,   /* 4: TIMx_CH3  */
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x04U,   /* 5: TIMx_CH3N */
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x04U,   /* 6: TIMx_CH4  */
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x3CU,   /* 7: TIMx_CH5  */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 14
+
+
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x3CU    /* 8: TIMx_CH6  */
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] =
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: OC1M, OC1FE, OC1PE */
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 1: - NA */
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 2: OC2M, OC2FE, OC2PE */
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 3: - NA */
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 4: OC3M, OC3FE, OC3PE */
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 5: - NA */
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 6: OC4M, OC4FE, OC4PE */
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 7: OC5M, OC5FE, OC5PE */
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U             /* 8: OC6M, OC6FE, OC6PE */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] =
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: CC1S, IC1PSC, IC1F */
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 1: - NA */
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 2: CC2S, IC2PSC, IC2F */
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 3: - NA */
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 4: CC3S, IC3PSC, IC3F */
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 5: - NA */
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 6: CC4S, IC4PSC, IC4F */
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 7: - NA */
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U             /* 8: - NA */
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] =
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: CC1P */
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   2U,            /* 1: CC1NP */
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   4U,            /* 2: CC2P */
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   6U,            /* 3: CC2NP */
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 4: CC3P */
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   10U,           /* 5: CC3NP */
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   12U,           /* 6: CC4P */
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   16U,           /* 7: CC5P */
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   20U            /* 8: CC6P */
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OISx[] =
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: OIS1 */
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   1U,            /* 1: OIS1N */
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   2U,            /* 2: OIS2 */
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   3U,            /* 3: OIS2N */
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   4U,            /* 4: OIS3 */
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   5U,            /* 5: OIS3N */
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   6U,            /* 6: OIS4 */
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 7: OIS5 */
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   10U            /* 8: OIS6 */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 15
+
+
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if   defined(TIM_BREAK_INPUT_SUPPORT)
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Defines used for the bit position in the register and perform offsets */
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_POSITION_BRK_SOURCE           (POSITION_VAL(Source) & 0x1FUL)
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Generic bit definitions for TIMx_AF1 register */
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_AF1_BKINP        TIM1_AF1_BKINP       /*!< BRK BKIN input polarity */
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Remap mask definitions */
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_SHIFT  16U
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_MASK   0x0000FFFFU
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM2_OR_RMP_MASK   (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM5_OR_RMP_MASK   (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM11_OR_RMP_MASK  (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_1 ((uint8_t)0x7F)
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_2 ((uint8_t)0x3F)
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_3 ((uint8_t)0x1F)
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_4 ((uint8_t)0x1F)
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_1 ((uint8_t)0x00)
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_2 ((uint8_t)0x80)
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_3 ((uint8_t)0xC0)
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_4 ((uint8_t)0xE0)
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief  Convert channel id into channel index.
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval none
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+ARM GAS  /tmp/cc8Pc1nf.s 			page 16
+
+
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief  Calculate the deadtime sampling period(in ps).
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz).
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CKD__ This parameter can be one of the following values:
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval none
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Time Base configuration structure definition.
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter can be a number between Min_Data=0x0000 and Max_D
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetPrescaler().*/
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t CounterMode;       /*!< Specifies the counter mode.
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetCounterMode().*/
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Auto-Reload Register at the next update event.
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter must be a number between Min_Data=0x0000 and Max_
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Some timer instances may support 32 bits counters. In that case 
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    be a number between 0x0000 and 0xFFFFFFFF.
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetAutoReload().*/
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 17
+
+
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ClockDivision;     /*!< Specifies the clock division.
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetClockDivision().*/
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downc
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    reaches zero, an update event is generated and counting restarts
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    from the RCR value (N).
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This means in PWM mode that (N+1) corresponds to:
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       - the number of PWM periods in edge-aligned mode
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       - the number of half PWM period in center-aligned mode
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    GP timers: this parameter must be a number between Min_Data = 0x
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Max_Data = 0xFF.
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Advanced timers: this parameter must be a number between Min_Dat
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Max_Data = 0xFFFF.
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetRepetitionCounter().*/
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_InitTypeDef;
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Output Compare configuration structure definition.
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCMode;        /*!< Specifies the output mode.
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetMode().*/
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary functions
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary functions
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Re
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a number between Min_Data=0x0000 and Max_Data=
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                LL_TIM_OC_SetCompareCHx (x=1..6).*/
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCPolarity;    /*!< Specifies the output polarity.
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetPolarity().*/
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+ARM GAS  /tmp/cc8Pc1nf.s 			page 18
+
+
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetPolarity().*/
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetIdleState().*/
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetIdleState().*/
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef;
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Input Capture configuration structure definition.
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetPolarity().*/
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICActiveInput; /*!< Specifies the input.
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetActiveInput().*/
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetPrescaler().*/
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICFilter;      /*!< Specifies the input capture filter.
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetFilter().*/
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef;
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Encoder interface configuration structure definition.
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 19
+
+
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_SetEncoderMode().*/
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPolarity().*/
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetActiveInput().*/
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPrescaler().*/
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetFilter().*/
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPolarity().*/
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetActiveInput().*/
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPrescaler().*/
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetFilter().*/
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef;
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 20
+
+
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Hall sensor interface configuration structure definition.
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_IC_SetPolarity().*/
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     Prescaler must be set to get a maximum counter period longer th
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     time interval between 2 consecutive changes on the Hall inputs.
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_IC_SetPrescaler().*/
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a value of
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref TIM_LL_EC_IC_FILTER.
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_IC_SetFilter().*/
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compa
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     A positive pulse (TRGO event) is generated with a programmable 
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     a change occurs on the Hall inputs.
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a number between Min_Data = 0x0000 and Ma
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_OC_SetCompareCH2().*/
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_HALLSENSOR_InitTypeDef;
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  BDTR (Break and Dead Time) structure definition
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_SetOffStates()
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field cannot be modified as long as LOCK level
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                        programmed. */
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_SetOffStates()
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field cannot be modified as long as LOCK level
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 21
+
+
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note The LOCK bits can be written only once after the reset.
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       register has been written, their content is frozen until the 
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       switching-on of the outputs.
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a number between Min_Data = 0x00 and Ma
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_OC_SetDeadTime()
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                        programmed. */
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARIT
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK()
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK()
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARI
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ARM GAS  /tmp/cc8Pc1nf.s 			page 22
+
+
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK2()
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK2()
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTP
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAut
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_BDTR_InitTypeDef;
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrup
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrup
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrup
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrup
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrup
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrup
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt fla
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapt
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapt
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapt
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapt
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt fla
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 23
+
+
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by 
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by softw
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrup
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrup
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrup
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrup
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable *
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/unde
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ARM GAS  /tmp/cc8Pc1nf.s 			page 24
+
+
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at 
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at 
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!< Counter used as upcounter 
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounte
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and 
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!< The counter counts up and 
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and 
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down 
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bi
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bi
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when 
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+ARM GAS  /tmp/cc8Pc1nf.s 			page 25
+
+
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CHANNEL Channel
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output ch
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output ch
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output ch
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** Legacy definitions for compatibility purpose
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @cond 0
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @endcond
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FROZEN                   0x00000000U                                         
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                    
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                    
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)               
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                    
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)               
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)               
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1
+ARM GAS  /tmp/cc8Pc1nf.s 			page 26
+
+
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                    
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)               
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)               
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                 
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!__REG__, (__VAL
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Read a value in TIM register.
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __INSTANCE__ TIM Instance
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __REG__ Register to be read
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Register value
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ARM GAS  /tmp/cc8Pc1nf.s 			page 34
+
+
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        to TIMx_CNT register bit 31)
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CNT__ Counter value
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval UIF status bit
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested de
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CKD__ This parameter can be one of the following values:
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __DT__ deadtime duration (in ns)
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval DTG[0:7]
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__C
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                  (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) 
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__C
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                  (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) 
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                  (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) 
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     0U)
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock freq
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CNTCLK__ counter clock frequency (in Hz)
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal fr
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PSC__ prescaler
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __FREQ__ output signal frequency (in Hz)
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+ARM GAS  /tmp/cc8Pc1nf.s 			page 35
+
+
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the compare value required to achieve the required timer outpu
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         active/inactive delay.
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PSC__ prescaler
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __DELAY__ timer output compare active/inactive delay (in us)
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (when the timer operates in one pulse mode).
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PSC__ prescaler
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __DELAY__ timer output compare active/inactive delay (in us)
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PULSE__ pulse duration (in us)
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****               + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __ICPSC__ This parameter can be one of the following values:
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV2
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV4
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV8
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable timer counter.
+ARM GAS  /tmp/cc8Pc1nf.s 			page 36
+
+
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable timer counter.
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the timer counter is enabled.
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable update event generation.
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable update event generation.
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether update event generation is enabled.
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+ARM GAS  /tmp/cc8Pc1nf.s 			page 37
+
+
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Inverted state of bit (0 or 1).
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set update event source
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       generate an update interrupt or DMA request if enabled:
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        - Counter overflow/underflow
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        - Setting the UG bit
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        - Update generation through the slave mode controller
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       overflow/underflow generates an update interrupt or DMA request if enabled.
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  UpdateSource This parameter can be one of the following values:
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual event update source
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set one pulse mode (one shot v.s. repetitive).
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  OnePulseMode This parameter can be one of the following values:
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual one pulse mode.
+ARM GAS  /tmp/cc8Pc1nf.s 			page 38
+
+
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the timer counter counting mode.
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       check whether or not the counter mode selection feature is supported
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       by a timer instance.
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       requires a timer reset to avoid unexpected direction
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       due to DIR bit readonly in center aligned mode.
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR1          CMS           LL_TIM_SetCounterMode
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CounterMode This parameter can be one of the following values:
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_UP
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual counter mode.
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       check whether or not the counter mode selection feature is supported
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       by a timer instance.
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR1          CMS           LL_TIM_GetCounterMode
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_UP
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t counter_mode;
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   if (counter_mode == 0U)
+ARM GAS  /tmp/cc8Pc1nf.s 			page 39
+
+
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   {
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   }
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return counter_mode;
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable auto-reload (ARR) preload.
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable auto-reload (ARR) preload.
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (when supported) and the digital filters.
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not the clock division feature is supported by the timer
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       instance.
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ClockDivision This parameter can be one of the following values:
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+ARM GAS  /tmp/cc8Pc1nf.s 			page 40
+
+
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by t
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         generators (when supported) and the digital filters.
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not the clock division feature is supported by the timer
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       instance.
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the counter value.
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CNT          CNT           LL_TIM_SetCounter
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CNT, Counter);
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the counter value.
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CNT          CNT           LL_TIM_GetCounter
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CNT));
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current direction of the counter
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          DIR           LL_TIM_GetDirection
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 41
+
+
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the prescaler value.
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The prescaler can be changed on the fly as this control register is buffered. The new
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       prescaler ratio is taken into account at the next update event.
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Prescaler between Min_Data=0 and Max_Data=65535
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->PSC, Prescaler);
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the prescaler value.
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->PSC));
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the auto-reload value.
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The counter is blocked while the auto-reload value is null.
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  AutoReload between Min_Data=0 and Max_Data=65535
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->ARR, AutoReload);
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the auto-reload value.
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Auto-reload value
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->ARR));
+ARM GAS  /tmp/cc8Pc1nf.s 			page 42
+
+
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the repetition counter value.
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note For advanced timer instances RepetitionCounter can be up to 65535.
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a repetition counter.
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->RCR, RepetitionCounter);
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the repetition counter value.
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a repetition counter.
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Repetition counter value
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->RCR));
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter regis
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This allows both the counter value and a potential roll-over condition signalled by the U
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       in an atomic way.
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable update interrupt flag (UIF) remapping.
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether update interrupt flag (UIF) copy is set.
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Counter Counter value
+ARM GAS  /tmp/cc8Pc1nf.s 			page 43
+
+
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       they are updated only when a commutation event (COM) occurs.
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Only on channels that have a complementary output.
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance is able to generate a commutation event.
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance is able to generate a commutation event.
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is en
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCPC          LL_TIM_CC_IsEnabledPreload
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ARM GAS  /tmp/cc8Pc1nf.s 			page 44
+
+
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance is able to generate a commutation event.
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CCUpdateSource This parameter can be one of the following values:
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the trigger of the capture/compare DMA request.
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DMAReqTrigger This parameter can be one of the following values:
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual trigger of the capture/compare DMA request.
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the lock level to freeze the
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         configuration of several capture/compare parameters.
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       the lock mechanism is supported by a timer instance.
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  LockLevel This parameter can be one of the following values:
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_1
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_2
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_3
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+ARM GAS  /tmp/cc8Pc1nf.s 			page 45
+
+
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable capture/compare channels.
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
+1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
+1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6E          LL_TIM_CC_EnableChannel
+1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channels This parameter can be a combination of the following values:
+1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CCER, Channels);
+1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable capture/compare channels.
+1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
+1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
+1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6E          LL_TIM_CC_DisableChannel
+1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channels This parameter can be a combination of the following values:
+1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 46
+
+
+1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CCER, Channels);
+1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether channel(s) is(are) enabled.
+1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
+1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
+1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
+1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channels This parameter can be a combination of the following values:
+1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
+1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure an output channel.
+1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
+1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
+1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
+1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
+1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
+ARM GAS  /tmp/cc8Pc1nf.s 			page 47
+
+
+1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
+1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS6          LL_TIM_OC_ConfigOutput
+1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Configuration This parameter must be a combination of all the following values:
+1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura
+1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Define the behavior of the output reference signal OCxREF from which
+1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         OCx and OCxN (when relevant) are derived.
+1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
+1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
+1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6M          LL_TIM_OC_SetMode
+1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Mode This parameter can be one of the following values:
+1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FROZEN
+1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ACTIVE
+1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_INACTIVE
+1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_TOGGLE
+1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM1
+1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM2
+1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ARM GAS  /tmp/cc8Pc1nf.s 			page 48
+
+
+1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT
+2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the output compare mode of an output channel.
+2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
+2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
+2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6M          LL_TIM_OC_GetMode
+2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FROZEN
+2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ACTIVE
+2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_INACTIVE
+2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_TOGGLE
+2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM1
+2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM2
+2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
+2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT
+2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the polarity of an output channel.
+2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+ARM GAS  /tmp/cc8Pc1nf.s 			page 49
+
+
+2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
+2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
+2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6P          LL_TIM_OC_SetPolarity
+2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Polarity This parameter can be one of the following values:
+2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_LOW
+2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[i
+2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the polarity of an output channel.
+2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
+2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
+2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6P          LL_TIM_OC_GetPolarity
+2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_LOW
+2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan
+2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 50
+
+
+2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the IDLE state of an output channel
+2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function is significant only for the timer instances
+2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       can be used to check whether or not a timer instance provides
+2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a break input.
+2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
+2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
+2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS6          LL_TIM_OC_SetIdleState
+2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  IdleState This parameter can be one of the following values:
+2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState
+2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iC
+2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the IDLE state of an output channel
+2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
+2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS6          LL_TIM_OC_GetIdleState
+2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+ARM GAS  /tmp/cc8Pc1nf.s 			page 51
+
+
+2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
+2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChanne
+2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable fast mode for the output channel.
+2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
+2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
+2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
+2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable fast mode for the output channel.
+2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
+2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
+2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
+2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 52
+
+
+2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether fast mode is enabled for the output channel.
+2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
+2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
+2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
+2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
+2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
+2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
+2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+ARM GAS  /tmp/cc8Pc1nf.s 			page 53
+
+
+2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
+2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
+2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
+2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe
+2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
+2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
+2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
+2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable clearing the output channel on an external event.
+2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function can only be used in Output compare and PWM modes. It does not work in Force
+2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ARM GAS  /tmp/cc8Pc1nf.s 			page 54
+
+
+2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance can clear the OCxREF signal on an external event.
+2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
+2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
+2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
+2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable clearing the output channel on an external event.
+2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance can clear the OCxREF signal on an external event.
+2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
+2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
+2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
+2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates clearing the output channel on an external event is enabled for the output ch
+2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function enables clearing the output channel on an external event.
+2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function can only be used in Output compare and PWM modes. It does not work in Force
+2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance can clear the OCxREF signal on an external event.
+ARM GAS  /tmp/cc8Pc1nf.s 			page 55
+
+
+2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
+2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
+2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
+2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal an
+2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         the Ocx and OCxN signals).
+2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       dead-time insertion feature is supported by a timer instance.
+2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DeadTime between Min_Data=0 and Max_Data=255
+2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 1 is supported by a timer instance.
+2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR1, CompareValue);
+2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 56
+
+
+2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 2 is supported by a timer instance.
+2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR2, CompareValue);
+2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel is supported by a timer instance.
+2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR3, CompareValue);
+2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 4 is supported by a timer instance.
+2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR4, CompareValue);
+2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 5 (TIMx_CCR5).
+2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 5 is supported by a timer instance.
+2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
+2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+ARM GAS  /tmp/cc8Pc1nf.s 			page 57
+
+
+2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 6 (TIMx_CCR6).
+2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 6 is supported by a timer instance.
+2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
+2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR6, CompareValue);
+2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 1 is supported by a timer instance.
+2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
+2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR1));
+2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 2 is supported by a timer instance.
+2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
+2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR2));
+2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+ARM GAS  /tmp/cc8Pc1nf.s 			page 58
+
+
+2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 3 is supported by a timer instance.
+2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
+2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR3));
+2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 4 is supported by a timer instance.
+2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
+2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR4));
+2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
+2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 5 is supported by a timer instance.
+2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
+2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
+2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
+2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 6 is supported by a timer instance.
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
+2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
+2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR6));
+2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Select on which reference signal the OC5REF is combined to.
+ARM GAS  /tmp/cc8Pc1nf.s 			page 59
+
+
+2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports the combined 3-phase PWM mode.
+2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
+2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
+2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
+2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  GroupCH5 This parameter can be a combination of the following values:
+2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_NONE
+2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
+2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
+2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
+2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
+2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure input channel.
+2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC1F          LL_TIM_IC_Config\n
+2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_IC_Config\n
+2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2F          LL_TIM_IC_Config\n
+2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_IC_Config\n
+2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3F          LL_TIM_IC_Config\n
+2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_IC_Config\n
+2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4F          LL_TIM_IC_Config\n
+2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1P          LL_TIM_IC_Config\n
+2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_IC_Config\n
+2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_IC_Config\n
+2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_IC_Config\n
+2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_IC_Config\n
+2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_IC_Config\n
+2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_IC_Config\n
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4NP         LL_TIM_IC_Config
+2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Configuration This parameter must be a combination of all the following values:
+2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_
+2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+ARM GAS  /tmp/cc8Pc1nf.s 			page 60
+
+
+2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_I
+2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne
+2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))       
+2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              << SHIFT_TAB_ICxx[iChannel]);
+2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the active input.
+2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICActiveInput This parameter can be one of the following values:
+2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv
+2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT
+2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current active input.
+2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
+ARM GAS  /tmp/cc8Pc1nf.s 			page 61
+
+
+2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann
+2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the prescaler of input channel.
+2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICPrescaler This parameter can be one of the following values:
+2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1
+2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV2
+2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV4
+2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV8
+2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal
+2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT
+2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current prescaler value acting on an  input channel.
+2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1
+2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV2
+2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV4
+2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV8
+2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
+2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha
+2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 62
+
+
+2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the input filter duration.
+2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICFilter This parameter can be one of the following values:
+2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_
+2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the input filter duration.
+2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ARM GAS  /tmp/cc8Pc1nf.s 			page 63
+
+
+2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
+2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann
+2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the input channel polarity.
+2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICPolarity This parameter can be one of the following values:
+2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_RISING
+2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity
+2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current input channel polarity.
+2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+ARM GAS  /tmp/cc8Pc1nf.s 			page 64
+
+
+2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_RISING
+2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****           SHIFT_TAB_CCxP[iChannel]);
+2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides an XOR input.
+2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides an XOR input.
+2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * a timer instance provides an XOR input.
+2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
+2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 65
+
+
+2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 1.
+2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 1 is supported by a timer instance.
+2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
+2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR1));
+2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 2.
+2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 2 is supported by a timer instance.
+2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
+2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR2));
+2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 3.
+2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 3 is supported by a timer instance.
+3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
+3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR3));
+3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 4.
+3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 4 is supported by a timer instance.
+3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+ARM GAS  /tmp/cc8Pc1nf.s 			page 66
+
+
+3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
+3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR4));
+3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable external clock mode 2.
+3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET
+3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable external clock mode 2.
+3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether external clock mode 2 is enabled.
+3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
+3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the clock source of the counter clock.
+3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note when selected clock source is external clock mode 1, the timer input
+ARM GAS  /tmp/cc8Pc1nf.s 			page 67
+
+
+3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       function. This timer input must be configured by calling
+3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       the @ref LL_TIM_IC_Config() function.
+3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode1.
+3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         SMCR         ECE           LL_TIM_SetClockSource
+3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ClockSource This parameter can be one of the following values:
+3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the encoder interface mode.
+3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports the encoder mode.
+3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  EncoderMode This parameter can be one of the following values:
+3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the trigger output (TRGO) used for timer synchronization .
+3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance can operate as a master timer.
+3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TimerSynchronization This parameter can be one of the following values:
+3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_RESET
+3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_ENABLE
+3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_UPDATE
+3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_CC1IF
+3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC1REF
+ARM GAS  /tmp/cc8Pc1nf.s 			page 68
+
+
+3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC2REF
+3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC3REF
+3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC4REF
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
+3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance can be used for ADC synchronization.
+3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
+3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer Instance
+3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ADCSynchronization This parameter can be one of the following values:
+3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_RESET
+3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_ENABLE
+3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_UPDATE
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_CC1F
+3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC1
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC2
+3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC3
+3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4
+3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC5
+3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC6
+3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the synchronization mode of a slave timer.
+3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  SlaveMode This parameter can be one of the following values:
+3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_RESET
+3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_GATED
+3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+ARM GAS  /tmp/cc8Pc1nf.s 			page 69
+
+
+3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the selects the trigger input to be used to synchronize the counter.
+3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TriggerInput This parameter can be one of the following values:
+3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR0
+3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR1
+3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR2
+3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR3
+3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_TI1F_ED
+3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_TI1FP1
+3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_TI2FP2
+3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ETRF
+3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the Master/Slave mode.
+3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the Master/Slave mode.
+3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief Indicates whether the Master/Slave mode is enabled.
+3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * a timer instance can operate as a slave timer.
+3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+ARM GAS  /tmp/cc8Pc1nf.s 			page 70
+
+
+3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
+3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure the external trigger (ETR) input.
+3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides an external trigger input.
+3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         SMCR         ETPS          LL_TIM_ConfigETR\n
+3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         SMCR         ETF           LL_TIM_ConfigETR
+3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ETRPolarity This parameter can be one of the following values:
+3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ETRPrescaler This parameter can be one of the following values:
+3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ETRFilter This parameter can be one of the following values:
+3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale
+3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       uint32_t ETRFilter)
+3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | 
+3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Break_Function Break function configuration
+3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the break function.
+3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ARM GAS  /tmp/cc8Pc1nf.s 			page 71
+
+
+3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the break function.
+3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure the break input.
+3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         BDTR         BKF           LL_TIM_ConfigBRK
+3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakPolarity This parameter can be one of the following values:
+3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakFilter This parameter can be one of the following values:
+3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
+3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       uint32_t BreakFilter)
+3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
+3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ARM GAS  /tmp/cc8Pc1nf.s 			page 72
+
+
+3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the break 2 function.
+3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a second break input.
+3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
+3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the break  2 function.
+3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a second break input.
+3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
+3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure the break 2 input.
+3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a second break input.
+3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         BDTR         BK2F          LL_TIM_ConfigBRK2
+3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Break2Polarity This parameter can be one of the following values:
+3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Break2Filter This parameter can be one of the following values:
+3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2F
+ARM GAS  /tmp/cc8Pc1nf.s 			page 73
+
+
+3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
+3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         BDTR         OSSR          LL_TIM_SetOffStates
+3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  OffStateIdle This parameter can be one of the following values:
+3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSI_DISABLE
+3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSI_ENABLE
+3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  OffStateRun This parameter can be one of the following values:
+3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSR_DISABLE
+3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSR_ENABLE
+3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat
+3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input
+3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable automatic output (MOE can be set only by software).
+3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether automatic output is enabled.
+3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+ARM GAS  /tmp/cc8Pc1nf.s 			page 74
+
+
+3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
+3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       software and is reset in case of break or break2 event
+3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       software and is reset in case of break or break2 event.
+3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether outputs are enabled.
+3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
+3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT)
+3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the signals connected to the designated timer break input.
+3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance allows for break input selection.
+3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll AF1          BKINE          LL_TIM_EnableBreakInputSource\n
+3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF1          BKDFBKE        LL_TIM_EnableBreakInputSource\n
+3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2INE         LL_TIM_EnableBreakInputSource\n
+ARM GAS  /tmp/cc8Pc1nf.s 			page 75
+
+
+3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2DFBKE       LL_TIM_EnableBreakInputSource
+3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakInput This parameter can be one of the following values:
+3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Source This parameter can be one of the following values:
+3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t
+3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, Source);
+3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the signals connected to the designated timer break input.
+3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance allows for break input selection.
+3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll AF1          BKINE          LL_TIM_DisableBreakInputSource\n
+3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF1          BKDFBKE        LL_TIM_DisableBreakInputSource\n
+3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2INE         LL_TIM_DisableBreakInputSource\n
+3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2DFBKE       LL_TIM_DisableBreakInputSource
+3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakInput This parameter can be one of the following values:
+3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Source This parameter can be one of the following values:
+3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_
+3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, Source);
+3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the polarity of the break signal for the timer break input.
+3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance allows for break input selection.
+3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll AF1          BKINP          LL_TIM_SetBreakInputSourcePolarity\n
+3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF1          BKDFBKP        LL_TIM_SetBreakInputSourcePolarity\n
+3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2INP         LL_TIM_SetBreakInputSourcePolarity\n
+3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2DFBKP       LL_TIM_SetBreakInputSourcePolarity
+3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakInput This parameter can be one of the following values:
+3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Source This parameter can be one of the following values:
+3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Polarity This parameter can be one of the following values:
+3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
+3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+ARM GAS  /tmp/cc8Pc1nf.s 			page 76
+
+
+3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uin
+3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                         uint32_t Polarity)
+3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOUR
+3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */
+3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configures the timer DMA burst feature.
+3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       not a timer instance supports the DMA burst mode.
+3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         DCR          DBA           LL_TIM_ConfigDMABurst
+3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DMABurstBaseAddress This parameter can be one of the following values:
+3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR
+3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1  (*)
+3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2  (*)
+3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (*) value not defined in all devices
+3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DMABurstLength This parameter can be one of the following values:
+3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+ARM GAS  /tmp/cc8Pc1nf.s 			page 77
+
+
+3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_
+3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
+3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Remap TIM inputs (input channel, internal/external triggers).
+3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a some timer inputs can be remapped.
+3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll TIM2_OR     ITR1_RMP          LL_TIM_SetRemap\n
+3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM5_OR     TI4_RMP           LL_TIM_SetRemap\n
+3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM11_OR    TI1_RMP           LL_TIM_SetRemap
+3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Remap Remap param depends on the TIMx. Description available only
+3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         in CHM version of the User Manual (not in .pdf).
+3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         Otherwise see Reference Manual description of OR registers.
+3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         Below description summarizes "Timer Instance" and "Remap" param combinations:
+3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM2: one of the following values
+3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            ITR1_RMP can be one of the following values
+3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
+3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP
+3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
+3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
+3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM5: one of the following values
+3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
+3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
+3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
+3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
+3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM11: one of the following values
+3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
+ARM GAS  /tmp/cc8Pc1nf.s 			page 78
+
+
+3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX
+3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_HSE
+3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1
+3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the update interrupt flag (UIF).
+3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
+ 382              		.loc 2 3738 26 view .LVU49
+ 383              	.LBB59:
+3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+ 384              		.loc 2 3740 3 view .LVU50
+ 385              		.loc 2 3740 12 is_stmt 0 view .LVU51
+ 386 0002 094B     		ldr	r3, .L31
+ 387 0004 1B69     		ldr	r3, [r3, #16]
+ 388              		.loc 2 3740 66 view .LVU52
+ 389 0006 13F0010F 		tst	r3, #1
+ 390 000a 0BD0     		beq	.L28
+ 391              	.LVL5:
+ 392              		.loc 2 3740 66 view .LVU53
+ 393              	.LBE59:
+ 394              	.LBE58:
+ 327:Src/stm32f7xx_it.c ****   {
+ 328:Src/stm32f7xx_it.c ****     LL_TIM_ClearFlag_UPDATE(TIM6);
+ 395              		.loc 1 328 5 is_stmt 1 view .LVU54
+ 396              	.LBB60:
+ 397              	.LBI60:
+3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 79
+
+
+ 398              		.loc 2 3727 22 view .LVU55
+ 399              	.LBB61:
+3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 400              		.loc 2 3729 3 view .LVU56
+ 401 000c 064B     		ldr	r3, .L31
+ 402 000e 6FF00102 		mvn	r2, #1
+ 403 0012 1A61     		str	r2, [r3, #16]
+ 404              	.LVL6:
+3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 405              		.loc 2 3729 3 is_stmt 0 view .LVU57
+ 406              	.LBE61:
+ 407              	.LBE60:
+ 329:Src/stm32f7xx_it.c ****     TO6++;//increment tick
+ 408              		.loc 1 329 5 is_stmt 1 view .LVU58
+ 409              		.loc 1 329 8 is_stmt 0 view .LVU59
+ 410 0014 054A     		ldr	r2, .L31+4
+ 411 0016 1368     		ldr	r3, [r2]
+ 412 0018 0133     		adds	r3, r3, #1
+ 413 001a 1360     		str	r3, [r2]
+ 330:Src/stm32f7xx_it.c ****     //10 ms or 100 Hz
+ 331:Src/stm32f7xx_it.c ****     HAL_GPIO_TogglePin(TEST_01_GPIO_Port, TEST_01_Pin);
+ 414              		.loc 1 331 5 is_stmt 1 view .LVU60
+ 415 001c 0221     		movs	r1, #2
+ 416 001e 0448     		ldr	r0, .L31+8
+ 417 0020 FFF7FEFF 		bl	HAL_GPIO_TogglePin
+ 418              	.LVL7:
+ 419              	.L28:
+ 332:Src/stm32f7xx_it.c ****     //HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_12);
+ 333:Src/stm32f7xx_it.c ****   }
+ 334:Src/stm32f7xx_it.c ****   /* USER CODE END TIM6_DAC_IRQn 1 */
+ 335:Src/stm32f7xx_it.c **** }
+ 420              		.loc 1 335 1 is_stmt 0 view .LVU61
+ 421 0024 08BD     		pop	{r3, pc}
+ 422              	.L32:
+ 423 0026 00BF     		.align	2
+ 424              	.L31:
+ 425 0028 00100040 		.word	1073745920
+ 426 002c 00000000 		.word	TO6
+ 427 0030 000C0240 		.word	1073875968
+ 428              		.cfi_endproc
+ 429              	.LFE1197:
+ 431              		.section	.text.TIM7_IRQHandler,"ax",%progbits
+ 432              		.align	1
+ 433              		.global	TIM7_IRQHandler
+ 434              		.syntax unified
+ 435              		.thumb
+ 436              		.thumb_func
+ 437              		.fpu fpv5-d16
+ 439              	TIM7_IRQHandler:
+ 440              	.LFB1198:
+ 336:Src/stm32f7xx_it.c **** 
+ 337:Src/stm32f7xx_it.c **** /**
+ 338:Src/stm32f7xx_it.c ****   * @brief This function handles TIM7 global interrupt.
+ 339:Src/stm32f7xx_it.c ****   */
+ 340:Src/stm32f7xx_it.c **** void TIM7_IRQHandler(void)
+ 341:Src/stm32f7xx_it.c **** {
+ 441              		.loc 1 341 1 is_stmt 1 view -0
+ARM GAS  /tmp/cc8Pc1nf.s 			page 80
+
+
+ 442              		.cfi_startproc
+ 443              		@ args = 0, pretend = 0, frame = 0
+ 444              		@ frame_needed = 0, uses_anonymous_args = 0
+ 445              		@ link register save eliminated.
+ 342:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN TIM7_IRQn 0 */
+ 343:Src/stm32f7xx_it.c **** 
+ 344:Src/stm32f7xx_it.c ****   /* USER CODE END TIM7_IRQn 0 */
+ 345:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN TIM7_IRQn 1 */
+ 346:Src/stm32f7xx_it.c ****   if(LL_TIM_IsActiveFlag_UPDATE(TIM7))
+ 446              		.loc 1 346 3 view .LVU63
+ 447              	.LVL8:
+ 448              	.LBB62:
+ 449              	.LBI62:
+3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 450              		.loc 2 3738 26 view .LVU64
+ 451              	.LBB63:
+ 452              		.loc 2 3740 3 view .LVU65
+ 453              		.loc 2 3740 12 is_stmt 0 view .LVU66
+ 454 0000 064B     		ldr	r3, .L35
+ 455 0002 1B69     		ldr	r3, [r3, #16]
+ 456              		.loc 2 3740 66 view .LVU67
+ 457 0004 13F0010F 		tst	r3, #1
+ 458 0008 07D0     		beq	.L33
+ 459              	.LVL9:
+ 460              		.loc 2 3740 66 view .LVU68
+ 461              	.LBE63:
+ 462              	.LBE62:
+ 347:Src/stm32f7xx_it.c ****   {
+ 348:Src/stm32f7xx_it.c ****     LL_TIM_ClearFlag_UPDATE(TIM7);
+ 463              		.loc 1 348 5 is_stmt 1 view .LVU69
+ 464              	.LBB64:
+ 465              	.LBI64:
+3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 466              		.loc 2 3727 22 view .LVU70
+ 467              	.LBB65:
+3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 468              		.loc 2 3729 3 view .LVU71
+ 469 000a 044B     		ldr	r3, .L35
+ 470 000c 6FF00102 		mvn	r2, #1
+ 471 0010 1A61     		str	r2, [r3, #16]
+ 472              	.LVL10:
+3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 473              		.loc 2 3729 3 is_stmt 0 view .LVU72
+ 474              	.LBE65:
+ 475              	.LBE64:
+ 349:Src/stm32f7xx_it.c ****     TO7++;
+ 476              		.loc 1 349 5 is_stmt 1 view .LVU73
+ 477              		.loc 1 349 8 is_stmt 0 view .LVU74
+ 478 0012 034A     		ldr	r2, .L35+4
+ 479 0014 1368     		ldr	r3, [r2]
+ 480 0016 0133     		adds	r3, r3, #1
+ 481 0018 1360     		str	r3, [r2]
+ 482              	.L33:
+ 350:Src/stm32f7xx_it.c ****     //1 ms or 1000 Hz
+ 351:Src/stm32f7xx_it.c ****     //HAL_GPIO_TogglePin(TEST_01_GPIO_Port, TEST_01_Pin);
+ 352:Src/stm32f7xx_it.c ****   }
+ 353:Src/stm32f7xx_it.c ****   /* USER CODE END TIM7_IRQn 1 */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 81
+
+
+ 354:Src/stm32f7xx_it.c **** }
+ 483              		.loc 1 354 1 view .LVU75
+ 484 001a 7047     		bx	lr
+ 485              	.L36:
+ 486              		.align	2
+ 487              	.L35:
+ 488 001c 00140040 		.word	1073746944
+ 489 0020 00000000 		.word	TO7
+ 490              		.cfi_endproc
+ 491              	.LFE1198:
+ 493              		.section	.text.UART_RxCpltCallback,"ax",%progbits
+ 494              		.align	1
+ 495              		.global	UART_RxCpltCallback
+ 496              		.syntax unified
+ 497              		.thumb
+ 498              		.thumb_func
+ 499              		.fpu fpv5-d16
+ 501              	UART_RxCpltCallback:
+ 502              	.LFB1200:
+ 355:Src/stm32f7xx_it.c **** 
+ 356:Src/stm32f7xx_it.c **** /**
+ 357:Src/stm32f7xx_it.c ****   * @brief This function handles DMA2 stream7 global interrupt.
+ 358:Src/stm32f7xx_it.c ****   */
+ 359:Src/stm32f7xx_it.c **** void DMA2_Stream7_IRQHandler(void)
+ 360:Src/stm32f7xx_it.c **** {
+ 361:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
+ 362:Src/stm32f7xx_it.c ****   if(LL_DMA_IsActiveFlag_TC7(DMA2) == 1)
+ 363:Src/stm32f7xx_it.c ****   {
+ 364:Src/stm32f7xx_it.c ****     DMA2_Stream7_TransferComplete();
+ 365:Src/stm32f7xx_it.c ****     u_tx_flg = 0;//indicate that transfer compete
+ 366:Src/stm32f7xx_it.c ****   }
+ 367:Src/stm32f7xx_it.c ****   else if(LL_DMA_IsActiveFlag_TE7(DMA2) == 1)
+ 368:Src/stm32f7xx_it.c ****   {
+ 369:Src/stm32f7xx_it.c ****     LL_DMA_ClearFlag_TE7(DMA2);
+ 370:Src/stm32f7xx_it.c ****   }
+ 371:Src/stm32f7xx_it.c ****   /* USER CODE END DMA2_Stream7_IRQn 0 */
+ 372:Src/stm32f7xx_it.c **** 
+ 373:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */
+ 374:Src/stm32f7xx_it.c **** 
+ 375:Src/stm32f7xx_it.c ****   /* USER CODE END DMA2_Stream7_IRQn 1 */
+ 376:Src/stm32f7xx_it.c **** }
+ 377:Src/stm32f7xx_it.c **** 
+ 378:Src/stm32f7xx_it.c **** /* USER CODE BEGIN 1 */
+ 379:Src/stm32f7xx_it.c **** void UART_RxCpltCallback(void)
+ 380:Src/stm32f7xx_it.c **** {
+ 503              		.loc 1 380 1 is_stmt 1 view -0
+ 504              		.cfi_startproc
+ 505              		@ args = 0, pretend = 0, frame = 0
+ 506              		@ frame_needed = 0, uses_anonymous_args = 0
+ 507              		@ link register save eliminated.
+ 508 0000 10B4     		push	{r4}
+ 509              	.LCFI4:
+ 510              		.cfi_def_cfa_offset 4
+ 511              		.cfi_offset 4, -4
+ 381:Src/stm32f7xx_it.c ****     uart_buf = LL_USART_ReceiveData8(USART1);
+ 512              		.loc 1 381 5 view .LVU77
+ 513              	.LVL11:
+ARM GAS  /tmp/cc8Pc1nf.s 			page 82
+
+
+ 514              	.LBB66:
+ 515              	.LBI66:
+ 516              		.file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @file    stm32f7xx_ll_usart.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief   Header file of USART LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifndef STM32F7xx_LL_USART_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define STM32F7xx_LL_USART_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****  || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8)
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL USART
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private types -------------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private variables ---------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private constants ---------------------------------------------------------*/
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Constants USART Private Constants
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private macros ------------------------------------------------------------*/
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER)
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Macros USART Private Macros
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ARM GAS  /tmp/cc8Pc1nf.s 			page 83
+
+
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported types ------------------------------------------------------------*/
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER)
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief LL USART Init Structure definition
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rat
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetBaudRate().*/
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or receive
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_DATAWI
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetDataWidth().*/
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_STOPBI
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetStopBitsLength().*/
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t Parity;                    /*!< Specifies the parity mode.
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_PARITY
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetParity().*/
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is en
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_DIRECT
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetTransferDirection().*/
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enab
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_HWCONT
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetHWFlowCtrl().*/
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_OVERSA
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+ARM GAS  /tmp/cc8Pc1nf.s 			page 84
+
+
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetOverSampling().*/
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_InitTypeDef;
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief LL USART Clock Init Structure definition
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_CLOCK.
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_Disabl
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_POLARI
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            functions @ref LL_USART_SetClockPolarity().
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture 
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_PHASE.
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            functions @ref LL_USART_SetClockPhase().
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the l
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            data bit (MSB) has to be output on the SCLK pin in synch
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_LASTCL
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            functions @ref LL_USART_SetLastClkPulseOutput().
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_ClockInitTypeDef;
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USE_FULL_LL_DRIVER */
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported constants --------------------------------------------------------*/
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Constants USART Exported Constants
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief    Flags defines which can be used with LL_USART_WriteReg function
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error cle
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error cl
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_NCF                        USART_ICR_NCF                 /*!< Noise error dete
+ARM GAS  /tmp/cc8Pc1nf.s 			page 85
+
+
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error cl
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detect
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission com
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission com
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detect
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag *
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block cle
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match 
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief    Flags defines which can be used with LL_USART_ReadReg function
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error fla
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error fl
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected f
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error fl
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detect
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RXNE                       USART_ISR_RXNE                /*!< Read data regist
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission com
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TXE                        USART_ISR_TXE                 /*!< Transmit data re
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detect
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt fl
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block fla
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate e
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate f
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match 
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag 
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup 
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable 
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK)
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable a
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission com
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ARM GAS  /tmp/cc8Pc1nf.s 			page 86
+
+
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IT IT Defines
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt e
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data regist
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission com
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data re
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match 
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block int
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detect
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt 
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt en
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission com
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DIRECTION Communication Direction
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PARITY Parity Control
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity co
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity co
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity co
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP Wakeup
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ARM GAS  /tmp/cc8Pc1nf.s 			page 87
+
+
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : S
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : S
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : S
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER)
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLOCK Clock Signal
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provid
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided *
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the l
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the l
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PHASE Clock Phase
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transiti
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transit
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_POLARITY Clock Polarity
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCL
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 88
+
+
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_STOPBITS Stop Bits
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 s
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 s
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as d
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works usin
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works usin
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the da
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the da
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BITORDER Bit Order
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/rece
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/rece
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ARM GAS  /tmp/cc8Pc1nf.s 			page 89
+
+
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Me
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Fa
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection 
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection 
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and R
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS outpu
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode 
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and R
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS)
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake u
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake u
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake u
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode *
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+ARM GAS  /tmp/cc8Pc1nf.s 			page 90
+
+
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection m
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection m
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low 
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data regis
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data regis
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported macro ------------------------------------------------------------*/
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Macros USART Exported Macros
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Write a value in USART register
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __INSTANCE__ USART Instance
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __REG__ Register to be written
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __VALUE__ Value to be written in the register
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Read a value in USART register
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __INSTANCE__ USART Instance
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __REG__ Register to be read
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Register value
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ARM GAS  /tmp/cc8Pc1nf.s 			page 91
+
+
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Compute USARTDIV value according to Peripheral Clock and
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __BAUDRATE__ Baud rate value to achieve
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                                                 + ((__BAUDRATE__)/2U))/(__BAUDRATE_
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Compute USARTDIV value according to Peripheral Clock and
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __BAUDRATE__ Baud rate value to achieve
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported functions --------------------------------------------------------*/
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Functions USART Exported Functions
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration Configuration functions
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART Enable
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UE            LL_USART_Enable
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR1, USART_CR1_UE);
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART Disable (all USART prescalers and outputs are disabled)
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+ARM GAS  /tmp/cc8Pc1nf.s 			page 92
+
+
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         and current operations are discarded. The configuration of the USART is kept, but all t
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         flags, in the USARTx_ISR are set to their default values.
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UE            LL_USART_Disable
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if USART is enabled
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UE            LL_USART_IsEnabled
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART enabled in STOP Mode.
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provide
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         USART clock selection is HSI or LSE in RCC.
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART disabled in STOP Mode.
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+ARM GAS  /tmp/cc8Pc1nf.s 			page 93
+
+
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_UCESM)
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART Clock enabled in STOP Mode
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is called, USART Clock is enabled while in STOP mode
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          UCESM         LL_USART_EnableClockInStopMode
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx)
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM);
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART clock disabled in STOP Mode
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is called, USART Clock is disabled while in STOP mode
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          UCESM         LL_USART_DisableClockInStopMode
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx)
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM);
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if USART clock is enabled in STOP Mode
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          UCESM         LL_USART_IsClockEnabledInStopMode
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx)
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM));
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_UCESM */
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM*/
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 94
+
+
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Receiver Disable
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Transmitter Enable
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Transmitter Disable
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure simultaneously enabled/disabled states
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         of Transmitter and Receiver
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          TE            LL_USART_SetTransferDirection
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  TransferDirection This parameter can be one of the following values:
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_NONE
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_RX
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX_RX
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirectio
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return enabled/disabled states of Transmitter and Receiver
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          TE            LL_USART_GetTransferDirection
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ARM GAS  /tmp/cc8Pc1nf.s 			page 95
+
+
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_NONE
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_RX
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX_RX
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   This function selects if hardware parity control (generation and detection) is enabled 
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at th
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PS            LL_USART_SetParity\n
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          PCE           LL_USART_SetParity
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Parity This parameter can be one of the following values:
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_NONE
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_EVEN
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_ODD
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PS            LL_USART_GetParity\n
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          PCE           LL_USART_GetParity
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_NONE
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_EVEN
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_ODD
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Receiver Wake Up method from Mute mode.
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Method This parameter can be one of the following values:
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_IDLELINE
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ARM GAS  /tmp/cc8Pc1nf.s 			page 96
+
+
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Receiver Wake Up method from Mute mode
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_IDLELINE
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M1            LL_USART_SetDataWidth
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  DataWidth This parameter can be one of the following values:
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_7B
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_8B
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_9B
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M1            LL_USART_GetDataWidth
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_7B
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_8B
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_9B
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Allow switch between Mute Mode and Active mode
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 97
+
+
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Oversampling to 8-bit or 16-bit mode
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  OverSampling This parameter can be one of the following values:
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_16
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_8
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Oversampling mode
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_16
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_8
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  LastBitClockPulse This parameter can be one of the following values:
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ARM GAS  /tmp/cc8Pc1nf.s 			page 98
+
+
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPul
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve Clock pulse of the last data bit output configuration
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (Last bit Clock pulse output to the SCLK pin or not)
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  ClockPhase This parameter can be one of the following values:
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_1EDGE
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_2EDGE
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_1EDGE
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_2EDGE
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ARM GAS  /tmp/cc8Pc1nf.s 			page 99
+
+
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  ClockPolarity This parameter can be one of the following values:
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_LOW
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_HIGH
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_LOW
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_HIGH
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutpu
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CPOL          LL_USART_ConfigClock\n
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          LBCL          LL_USART_ConfigClock
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Phase This parameter can be one of the following values:
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_1EDGE
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_2EDGE
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Polarity This parameter can be one of the following values:
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_LOW
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_HIGH
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  LBCPOutput This parameter can be one of the following values:
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity,
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCP
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 100
+
+
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Clock output on SCLK pin
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Clock output on SCLK pin
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Clock output on SCLK pin is enabled
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set the length of the stop bits
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  StopBits This parameter can be one of the following values:
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_0_5
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1_5
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_2
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve the length of the stop bits
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+ARM GAS  /tmp/cc8Pc1nf.s 			page 101
+
+
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_0_5
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1_5
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_2
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          PCE           LL_USART_ConfigCharacter\n
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M0            LL_USART_ConfigCharacter\n
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M1            LL_USART_ConfigCharacter\n
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          STOP          LL_USART_ConfigCharacter
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  DataWidth This parameter can be one of the following values:
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_7B
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_8B
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_9B
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Parity This parameter can be one of the following values:
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_NONE
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_EVEN
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_ODD
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  StopBits This parameter can be one of the following values:
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_0_5
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1_5
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_2
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t P
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                               uint32_t StopBits)
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure TX/RX pins swapping setting.
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  SwapConfig This parameter can be one of the following values:
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_STANDARD
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_SWAPPED
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 102
+
+
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve TX/RX pins swapping configuration.
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_STANDARD
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_SWAPPED
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure RX pin active level logic
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PinInvMethod This parameter can be one of the following values:
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve RX pin active level logic configuration
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure TX pin active level logic
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PinInvMethod This parameter can be one of the following values:
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 103
+
+
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve TX pin active level logic configuration
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Binary data logic.
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Allow to define how Logical data from the data register are send/received :
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  DataLogic This parameter can be one of the following values:
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve Binary data configuration
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   MSB First means data is transmitted/received with the MSB first, following the start bi
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LSB First means data is transmitted/received with data bit 0 first, following the start
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  BitOrder This parameter can be one of the following values:
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_LSBFIRST
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_MSBFIRST
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ARM GAS  /tmp/cc8Pc1nf.s 			page 104
+
+
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   MSB First means data is transmitted/received with the MSB first, following the start bi
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LSB First means data is transmitted/received with data bit 0 first, following the start
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_LSBFIRST
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_MSBFIRST
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Auto Baud-Rate Detection
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Auto Baud-Rate Detection
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Auto Baud-Rate mode bits
+ARM GAS  /tmp/cc8Pc1nf.s 			page 105
+
+
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  AutoBaudRateMode This parameter can be one of the following values:
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Auto Baud-Rate mode
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Receiver Timeout
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Receiver Timeout
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Receiver Timeout feature is enabled
+ARM GAS  /tmp/cc8Pc1nf.s 			page 106
+
+
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Address of the USART node.
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         for wake up with address mark detection.
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (b7-b4 should be set to 0)
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         for wake up with 7-bit address mark detection.
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         The MSB of the character sent by the transmitter should be equal to 1.
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         It may also be used for character detection during normal reception,
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         value and CMF flag is set on match)
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  AddressLen This parameter can be one of the following values:
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  NodeAddress 4 or 7 bit Address of the USART node.
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   If 4-bit Address Detection is selected in ADDM7,
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         If 7-bit Address Detection is selected in ADDM7,
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ARM GAS  /tmp/cc8Pc1nf.s 			page 107
+
+
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable RTS HW Flow Control
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable RTS HW Flow Control
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable CTS HW Flow Control
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable CTS HW Flow Control
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+ARM GAS  /tmp/cc8Pc1nf.s 			page 108
+
+
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure HW Flow Control mode (both CTS and RTS)
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  HardwareFlowControl This parameter can be one of the following values:
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_NONE
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_CTS
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return HW Flow Control configuration (both CTS and RTS)
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_NONE
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_CTS
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable One bit sampling method
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable One bit sampling method
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ARM GAS  /tmp/cc8Pc1nf.s 			page 109
+
+
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if One bit sampling method is enabled
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Overrun detection
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Overrun detection
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Overrun detection is enabled
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS)
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+ARM GAS  /tmp/cc8Pc1nf.s 			page 110
+
+
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Type This parameter can be one of the following values:
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (Baud rate value != 0)
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PeriphClk Peripheral Clock
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  OverSampling This parameter can be one of the following values:
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_16
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_8
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  BaudRate Baud Rate
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverS
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                           uint32_t BaudRate)
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t usartdiv;
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t brrtemp;
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   if (OverSampling == LL_USART_OVERSAMPLING_8)
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp = usartdiv & 0xFFF0U;
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ARM GAS  /tmp/cc8Pc1nf.s 			page 111
+
+
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     USARTx->BRR = brrtemp;
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   else
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be ret
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PeriphClk Peripheral Clock
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  OverSampling This parameter can be one of the following values:
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_16
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_8
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Baud Rate
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t usartdiv;
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t brrresult = 0x0U;
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   usartdiv = USARTx->BRR;
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   if (usartdiv == 0U)
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     /* Do not perform a division by 0 */
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   else if (OverSampling == LL_USART_OVERSAMPLING_8)
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     if (usartdiv != 0U)
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     {
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****       brrresult = (PeriphClk * 2U) / usartdiv;
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     }
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   else
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     if ((usartdiv & 0xFFFFU) != 0U)
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     {
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****       brrresult = PeriphClk / usartdiv;
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     }
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (brrresult);
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 112
+
+
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Block Length value in reception
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Get Block Length value in reception
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable IrDA mode
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          IREN          LL_USART_EnableIrda
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 113
+
+
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_IREN);
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable IrDA mode
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          IREN          LL_USART_DisableIrda
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if IrDA mode is enabled
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure IrDA Power Mode (Normal or Low Power)
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PowerMode This parameter can be one of the following values:
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_IRDA_POWER_LOW
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_2EDGE
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 114
+
+
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Irda prescaler value, used for dividing the USART clock source
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         to achieve the Irda Low Power frequency (8 bits value)
+1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Irda prescaler value, used for dividing the USART clock source
+1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         to achieve the Irda Low Power frequency (8 bits value)
+1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
+1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feat
+1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Smartcard NACK transmission
+1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_NACK);
+1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Smartcard NACK transmission
+1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+ARM GAS  /tmp/cc8Pc1nf.s 			page 115
+
+
+1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Smartcard NACK transmission is enabled
+1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
+1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Smartcard mode
+1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Smartcard mode
+1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Smartcard mode is enabled
+1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
+ARM GAS  /tmp/cc8Pc1nf.s 			page 116
+
+
+1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mo
+1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         In transmission mode, it specifies the number of automatic retransmission retries, befo
+1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         generating a transmission error (FE bit set).
+1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         In reception mode, it specifies the number or erroneous reception trials, before genera
+1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         reception error (RXNE and PE bits set)
+1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryC
+1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
+1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         source to provide the SMARTCARD Clock (5 bits value)
+1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         source to provide the SMARTCARD Clock (5 bits value)
+1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+ARM GAS  /tmp/cc8Pc1nf.s 			page 117
+
+
+1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
+1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (GT[7:0] bits : Guard time value)
+2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (GT[7:0] bits : Guard time value)
+2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
+2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex f
+2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Single Wire Half-Duplex mode
+2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Half-Duplex mode is supported by the USARTx instance.
+2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ARM GAS  /tmp/cc8Pc1nf.s 			page 118
+
+
+2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Single Wire Half-Duplex mode
+2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Half-Duplex mode is supported by the USARTx instance.
+2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Half-Duplex mode is supported by the USARTx instance.
+2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
+2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set LIN Break Detection Length
+2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  LINBDLength This parameter can be one of the following values:
+2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return LIN Break Detection Length
+2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ARM GAS  /tmp/cc8Pc1nf.s 			page 119
+
+
+2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
+2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable LIN mode
+2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable LIN mode
+2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if LIN mode is enabled
+2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
+2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 120
+
+
+2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits)
+2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Time Value between Min_Data=0 and Max_Data=31
+2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return DEDT (Driver Enable De-Assertion Time)
+2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
+2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Time Value between Min_Data=0 and Max_Data=31
+2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return DEAT (Driver Enable Assertion Time)
+2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
+2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Driver Enable (DE) Mode
+2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+ARM GAS  /tmp/cc8Pc1nf.s 			page 121
+
+
+2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_DEM);
+2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Driver Enable (DE) Mode
+2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Driver Enable (DE) Mode is enabled
+2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
+2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Select Driver Enable Polarity
+2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Polarity This parameter can be one of the following values:
+2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DE_POLARITY_HIGH
+2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DE_POLARITY_LOW
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Driver Enable Polarity
+2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Driver Enable feature is supported by the USARTx instance.
+2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ARM GAS  /tmp/cc8Pc1nf.s 			page 122
+
+
+2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DE_POLARITY_HIGH
+2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DE_POLARITY_LOW
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
+2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In UART mode, the following bits must be kept cleared:
+2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - CLKEN bit in the USART_CR2 register,
+2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Asynchronous Mode
+2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, Parity, ...) should be set using
+2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In Asynchronous mode, the following bits must be kept cleared:
+2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN, CLKEN bits in the USART_CR2 register,
+2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In Synchronous mode, the following bits must be kept cleared:
+2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+ARM GAS  /tmp/cc8Pc1nf.s 			page 123
+
+
+2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         This function also sets the USART in Synchronous mode.
+2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Synchronous Mode
+2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigSyncMode\n
+2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigSyncMode
+2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In Synchronous mode, the following bits must be kept cleared:
+2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN bit in the USART_CR2 register,
+2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* set the UART/USART in Synchronous mode */
+2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In LIN mode, the following bits must be kept cleared:
+2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - STOP and CLKEN bits in the USART_CR2 register,
+2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         This function also set the UART/USART in LIN mode.
+2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to LIN Mode
+2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          STOP          LL_USART_ConfigLINMode\n
+2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          LINEN         LL_USART_ConfigLINMode\n
+ARM GAS  /tmp/cc8Pc1nf.s 			page 124
+
+
+2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigLINMode\n
+2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigLINMode\n
+2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigLINMode
+2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In LIN mode, the following bits must be kept cleared:
+2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - STOP and CLKEN bits in the USART_CR2 register,
+2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* Set the UART/USART in LIN mode */
+2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In Half Duplex mode, the following bits must be kept cleared:
+2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - CLKEN bit in the USART_CR2 register,
+2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         This function also sets the UART/USART in Half Duplex mode.
+2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Half-Duplex mode is supported by the USARTx instance.
+2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Half Duplex Mode
+2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, Parity, ...) should be set using
+2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In Half Duplex mode, the following bits must be kept cleared:
+2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN and CLKEN bits in the USART_CR2 register,
+2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - SCEN and IREN bits in the USART_CR3 register.
+2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* set the UART/USART in Half Duplex mode */
+2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 125
+
+
+2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In Smartcard mode, the following bits must be kept cleared:
+2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         This function also configures Stop bits to 1.5 bits and
+2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         sets the USART in Smartcard mode (SCEN bit).
+2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Clock Output is also enabled (CLKEN).
+2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Smartcard Mode
+2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, Parity, ...) should be set using
+2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In Smartcard mode, the following bits must be kept cleared:
+2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN bit in the USART_CR2 register,
+2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - IREN and HDSEL bits in the USART_CR3 register.
+2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* Configure Stop bits to 1.5 bits */
+2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* Synchronous mode is activated by default */
+2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* set the UART/USART in Smartcard mode */
+2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In IRDA mode, the following bits must be kept cleared:
+2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - STOP and CLKEN bits in the USART_CR2 register,
+2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         This function also sets the UART/USART in IRDA mode (IREN bit).
+2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         IrDA feature is supported by the USARTx instance.
+2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ARM GAS  /tmp/cc8Pc1nf.s 			page 126
+
+
+2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Irda Mode
+2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Word length, Power mode, ...) should be set using
+2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigIrdaMode
+2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In IRDA mode, the following bits must be kept cleared:
+2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - SCEN and HDSEL bits in the USART_CR3 register.
+2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* set the UART/USART in IRDA mode */
+2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_IREN);
+2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (several USARTs connected in a network, one of the USARTs can be the master,
+2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         its TX output connected to the RX inputs of the other slaves USARTs).
+2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In MultiProcessor mode, the following bits must be kept cleared:
+2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - LINEN bit in the USART_CR2 register,
+2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - CLKEN bit in the USART_CR2 register,
+2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - SCEN bit in the USART_CR3 register,
+2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - IREN bit in the USART_CR3 register,
+2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           - HDSEL bit in the USART_CR3 register.
+2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Other remaining configurations items related to Multi processor Mode
+2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         dedicated functions
+2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 127
+
+
+2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   /* In Multi Processor mode, the following bits must be kept cleared:
+2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - LINEN and CLKEN bits in the USART_CR2 register,
+2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Parity Error Flag is set or not
+2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
+2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Framing Error Flag is set or not
+2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
+2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Noise error detected Flag is set or not
+2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
+2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
+2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART OverRun Error Flag is set or not
+2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
+2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 128
+
+
+2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART IDLE line detected Flag is set or not
+2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
+2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
+2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          RXNE          LL_USART_IsActiveFlag_RXNE
+2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx)
+2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
+2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Transmission Complete Flag is set or not
+2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
+2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
+2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          TXE           LL_USART_IsActiveFlag_TXE
+2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx)
+2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
+2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART LIN Break Detection Flag is set or not
+2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
+2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 129
+
+
+2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART CTS interrupt Flag is set or not
+2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
+2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART CTS Flag is set or not
+2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
+2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Receiver Time Out Flag is set or not
+2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
+2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART End Of Block Flag is set or not
+2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
+2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+ARM GAS  /tmp/cc8Pc1nf.s 			page 130
+
+
+2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
+2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
+2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Busy Flag is set or not
+2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
+2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Character Match Flag is set or not
+2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
+2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Send Break Flag is set or not
+2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
+2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+ARM GAS  /tmp/cc8Pc1nf.s 			page 131
+
+
+2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
+2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
+2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
+2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK)
+2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
+2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */
+2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */
+2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ARM GAS  /tmp/cc8Pc1nf.s 			page 132
+
+
+2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx)
+2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Parity Error Flag
+2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Framing Error Flag
+2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Noise Error detected Flag
+2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          NCF           LL_USART_ClearFlag_NE
+2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_NCF);
+2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear OverRun Error Flag
+2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear IDLE line detected Flag
+2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 133
+
+
+2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Transmission Complete Flag
+2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */
+2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear LIN Break Detection Flag
+2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear CTS Interrupt Flag
+2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 134
+
+
+2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Receiver Time Out Flag
+2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear End Of Block Flag
+2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Character Match Flag
+2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Clear Wake Up from stop mode Flag
+3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_IT_Management IT_Management
+3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ARM GAS  /tmp/cc8Pc1nf.s 			page 135
+
+
+3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable IDLE Interrupt
+3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable RX Not Empty Interrupt
+3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
+3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Transmission Complete Interrupt
+3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable TX Empty Interrupt
+3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
+3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Parity Error Interrupt
+3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 136
+
+
+3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Character Match Interrupt
+3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Receiver Timeout Interrupt
+3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable End Of Block Interrupt
+3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable LIN Break Detection Interrupt
+3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Error Interrupt
+3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram
+3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           0: Interrupt is inhibited
+3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ARM GAS  /tmp/cc8Pc1nf.s 			page 137
+
+
+3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable CTS Interrupt
+3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Wake Up from Stop Mode Interrupt
+3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */
+3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable IDLE Interrupt
+3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ARM GAS  /tmp/cc8Pc1nf.s 			page 138
+
+
+3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable RX Not Empty Interrupt
+3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
+3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Transmission Complete Interrupt
+3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable TX Empty Interrupt
+3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
+3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Parity Error Interrupt
+3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Character Match Interrupt
+3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+ARM GAS  /tmp/cc8Pc1nf.s 			page 139
+
+
+3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Receiver Timeout Interrupt
+3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable End Of Block Interrupt
+3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable LIN Break Detection Interrupt
+3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Error Interrupt
+3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram
+3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           0: Interrupt is inhibited
+3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 140
+
+
+3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable CTS Interrupt
+3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Wake Up from Stop Mode Interrupt
+3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */
+3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
+3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 141
+
+
+3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
+3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
+3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx)
+3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U);
+3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
+3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
+3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
+3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx)
+3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U);
+3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
+3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
+3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+ARM GAS  /tmp/cc8Pc1nf.s 			page 142
+
+
+3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
+3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
+3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LIN feature is supported by the USARTx instance.
+3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
+3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Error Interrupt is enabled or disabled.
+3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
+3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
+3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ARM GAS  /tmp/cc8Pc1nf.s 			page 143
+
+
+3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
+3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */
+3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or 
+3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Smartcard feature is supported by the USARTx instance.
+3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx)
+3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_DMA_Management DMA_Management
+3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable DMA Mode for reception
+3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable DMA Mode for reception
+3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ARM GAS  /tmp/cc8Pc1nf.s 			page 144
+
+
+3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if DMA Mode is enabled for reception
+3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
+3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable DMA Mode for transmission
+3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable DMA Mode for transmission
+3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Check if DMA Mode is enabled for transmission
+3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
+3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable DMA Disabling on Reception Error
+3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 145
+
+
+3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable DMA Disabling on Reception Error
+3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if DMA Disabling on Reception Error is disabled
+3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
+3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Get the data register address used for DMA transfer
+3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Direction This parameter can be one of the following values:
+3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Address of data register
+3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
+3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t data_reg_addr;
+3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     /* return address of TDR register */
+3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     data_reg_addr = (uint32_t) &(USARTx->TDR);
+3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   else
+3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     /* return address of RDR register */
+3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     data_reg_addr = (uint32_t) &(USARTx->RDR);
+3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return data_reg_addr;
+3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ARM GAS  /tmp/cc8Pc1nf.s 			page 146
+
+
+3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Data_Management Data_Management
+3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll RDR          RDR           LL_USART_ReceiveData8
+3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
+ 517              		.loc 3 3658 25 view .LVU78
+ 518              	.LBB67:
+3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+ 519              		.loc 3 3660 3 view .LVU79
+ 520              		.loc 3 3660 20 is_stmt 0 view .LVU80
+ 521 0002 974B     		ldr	r3, .L71
+ 522 0004 5A6A     		ldr	r2, [r3, #36]
+ 523              		.loc 3 3660 10 view .LVU81
+ 524 0006 D2B2     		uxtb	r2, r2
+ 525              	.LVL12:
+ 526              		.loc 3 3660 10 view .LVU82
+ 527              	.LBE67:
+ 528              	.LBE66:
+ 529              		.loc 1 381 14 view .LVU83
+ 530 0008 964B     		ldr	r3, .L71+4
+ 531 000a 1A70     		strb	r2, [r3]
+ 382:Src/stm32f7xx_it.c ****     switch (UART_rec_incr)
+ 532              		.loc 1 382 5 is_stmt 1 view .LVU84
+ 533 000c 964B     		ldr	r3, .L71+8
+ 534 000e 1B88     		ldrh	r3, [r3]
+ 535 0010 1F2B     		cmp	r3, #31
+ 536 0012 00F20B81 		bhi	.L38
+ 537 0016 DFE813F0 		tbh	[pc, r3, lsl #1]
+ 538              	.L40:
+ 539 001a 2000     		.2byte	(.L43-.L40)/2
+ 540 001c 2F00     		.2byte	(.L42-.L40)/2
+ 541 001e 0901     		.2byte	(.L38-.L40)/2
+ 542 0020 0901     		.2byte	(.L38-.L40)/2
+ 543 0022 0901     		.2byte	(.L38-.L40)/2
+ 544 0024 0901     		.2byte	(.L38-.L40)/2
+ 545 0026 0901     		.2byte	(.L38-.L40)/2
+ 546 0028 0901     		.2byte	(.L38-.L40)/2
+ 547 002a 0901     		.2byte	(.L38-.L40)/2
+ 548 002c 0901     		.2byte	(.L38-.L40)/2
+ 549 002e 0901     		.2byte	(.L38-.L40)/2
+ 550 0030 0901     		.2byte	(.L38-.L40)/2
+ 551 0032 0901     		.2byte	(.L38-.L40)/2
+ 552 0034 0901     		.2byte	(.L38-.L40)/2
+ 553 0036 0901     		.2byte	(.L38-.L40)/2
+ 554 0038 0901     		.2byte	(.L38-.L40)/2
+ 555 003a 0901     		.2byte	(.L38-.L40)/2
+ 556 003c 0901     		.2byte	(.L38-.L40)/2
+ 557 003e 0901     		.2byte	(.L38-.L40)/2
+ARM GAS  /tmp/cc8Pc1nf.s 			page 147
+
+
+ 558 0040 0901     		.2byte	(.L38-.L40)/2
+ 559 0042 0901     		.2byte	(.L38-.L40)/2
+ 560 0044 0901     		.2byte	(.L38-.L40)/2
+ 561 0046 0901     		.2byte	(.L38-.L40)/2
+ 562 0048 0901     		.2byte	(.L38-.L40)/2
+ 563 004a 0901     		.2byte	(.L38-.L40)/2
+ 564 004c 0901     		.2byte	(.L38-.L40)/2
+ 565 004e 0901     		.2byte	(.L38-.L40)/2
+ 566 0050 0901     		.2byte	(.L38-.L40)/2
+ 567 0052 0901     		.2byte	(.L38-.L40)/2
+ 568 0054 9500     		.2byte	(.L41-.L40)/2
+ 569 0056 0901     		.2byte	(.L38-.L40)/2
+ 570 0058 CF00     		.2byte	(.L39-.L40)/2
+ 571              		.p2align 1
+ 572              	.L43:
+ 383:Src/stm32f7xx_it.c ****     {
+ 384:Src/stm32f7xx_it.c ****     case 0:
+ 385:Src/stm32f7xx_it.c ****         TO6_uart = TO6;//Save the time of start rec. command
+ 573              		.loc 1 385 9 view .LVU85
+ 574              		.loc 1 385 18 is_stmt 0 view .LVU86
+ 575 005a 8449     		ldr	r1, .L71+12
+ 576 005c 0868     		ldr	r0, [r1]
+ 577 005e 8449     		ldr	r1, .L71+16
+ 578 0060 0860     		str	r0, [r1]
+ 386:Src/stm32f7xx_it.c ****         flg_tmt = 1;//Set the timeout flag
+ 579              		.loc 1 386 9 is_stmt 1 view .LVU87
+ 580              		.loc 1 386 17 is_stmt 0 view .LVU88
+ 581 0062 8449     		ldr	r1, .L71+20
+ 582 0064 0120     		movs	r0, #1
+ 583 0066 0870     		strb	r0, [r1]
+ 387:Src/stm32f7xx_it.c ****         UART_header = uart_buf;
+ 584              		.loc 1 387 9 is_stmt 1 view .LVU89
+ 585              		.loc 1 387 21 is_stmt 0 view .LVU90
+ 586 0068 8349     		ldr	r1, .L71+24
+ 587 006a 0A80     		strh	r2, [r1]	@ movhi
+ 388:Src/stm32f7xx_it.c ****         UART_rec_incr++;
+ 588              		.loc 1 388 9 is_stmt 1 view .LVU91
+ 589              		.loc 1 388 22 is_stmt 0 view .LVU92
+ 590 006c 0344     		add	r3, r3, r0
+ 591 006e 7E4A     		ldr	r2, .L71+8
+ 592 0070 1380     		strh	r3, [r2]	@ movhi
+ 389:Src/stm32f7xx_it.c ****     break;
+ 593              		.loc 1 389 5 is_stmt 1 view .LVU93
+ 594              	.L37:
+ 390:Src/stm32f7xx_it.c ****     case 1:
+ 391:Src/stm32f7xx_it.c ****         UART_header += ((uint16_t)uart_buf<<8);
+ 392:Src/stm32f7xx_it.c ****         switch (UART_header)
+ 393:Src/stm32f7xx_it.c ****         {
+ 394:Src/stm32f7xx_it.c ****         case 0x1111: //received long packet
+ 395:Src/stm32f7xx_it.c ****             UART_rec_incr = 2;//timeout flag is still setting!
+ 396:Src/stm32f7xx_it.c ****         break;
+ 397:Src/stm32f7xx_it.c ****         case 0x2222: //Back to default
+ 398:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 399:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 400:Src/stm32f7xx_it.c ****             CPU_state = DEFAULT_ENABLE;
+ 401:Src/stm32f7xx_it.c ****         break;
+ 402:Src/stm32f7xx_it.c ****         case 0x3333: //Transmith saved DATA
+ARM GAS  /tmp/cc8Pc1nf.s 			page 148
+
+
+ 403:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 404:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 405:Src/stm32f7xx_it.c ****             CPU_state = TRANS_S_ENABLE;
+ 406:Src/stm32f7xx_it.c ****         break;
+ 407:Src/stm32f7xx_it.c ****         case 0x4444: //Received packet
+ 408:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 409:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 410:Src/stm32f7xx_it.c ****             CPU_state = TRANS_ENABLE;
+ 411:Src/stm32f7xx_it.c ****         break;
+ 412:Src/stm32f7xx_it.c ****         case 0x5555: //Erase saved DATA
+ 413:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 414:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 415:Src/stm32f7xx_it.c ****             CPU_state = REMOVE_FILE;
+ 416:Src/stm32f7xx_it.c ****         break;
+ 417:Src/stm32f7xx_it.c ****         case 0x6666: //Request state
+ 418:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 419:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 420:Src/stm32f7xx_it.c ****             CPU_state = STATE;
+ 421:Src/stm32f7xx_it.c ****         break;
+ 422:Src/stm32f7xx_it.c ****         case 0x7777:
+ 423:Src/stm32f7xx_it.c ****             UART_rec_incr = 2;//timeout flag is still setting!
+ 424:Src/stm32f7xx_it.c ****             break;
+ 425:Src/stm32f7xx_it.c ****         default: //error decoding header
+ 426:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 427:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 428:Src/stm32f7xx_it.c ****             //UART_transmission_request = MESS_01;
+ 429:Src/stm32f7xx_it.c ****             //CPU_state = HALT;
+ 430:Src/stm32f7xx_it.c ****             State_Data[0] |= UART_ERR;
+ 431:Src/stm32f7xx_it.c ****             CPU_state = DEFAULT_ENABLE;//Parking system and send error state!
+ 432:Src/stm32f7xx_it.c ****         break;
+ 433:Src/stm32f7xx_it.c ****         }
+ 434:Src/stm32f7xx_it.c ****     break;
+ 435:Src/stm32f7xx_it.c **** 
+ 436:Src/stm32f7xx_it.c ****     case (CL_8 - 1):
+ 437:Src/stm32f7xx_it.c ****         if (UART_header == 0x1111)
+ 438:Src/stm32f7xx_it.c ****         {
+ 439:Src/stm32f7xx_it.c ****             if ((UART_rec_incr & 0x0001) > 0)
+ 440:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr >> 1) - 1] += ((uint16_t)(uart_buf)) << 8;
+ 441:Src/stm32f7xx_it.c ****             else
+ 442:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr >> 1) - 1] = (uint16_t)(uart_buf);
+ 443:Src/stm32f7xx_it.c ****             CPU_state = DECODE_ENABLE;
+ 444:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 445:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 446:Src/stm32f7xx_it.c ****         }
+ 447:Src/stm32f7xx_it.c ****         else
+ 448:Src/stm32f7xx_it.c ****         {
+ 449:Src/stm32f7xx_it.c ****             if ((UART_rec_incr&0x0001)>0)
+ 450:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 451:Src/stm32f7xx_it.c ****             else
+ 452:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf);
+ 453:Src/stm32f7xx_it.c ****            UART_rec_incr++;
+ 454:Src/stm32f7xx_it.c ****            UART_transmission_request = NO_MESS;
+ 455:Src/stm32f7xx_it.c ****         }
+ 456:Src/stm32f7xx_it.c ****     break;
+ 457:Src/stm32f7xx_it.c ****     case (TSK_8 - 1):
+ 458:Src/stm32f7xx_it.c ****         if (UART_header == 0x7777)
+ 459:Src/stm32f7xx_it.c ****         {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 149
+
+
+ 460:Src/stm32f7xx_it.c ****             if ((UART_rec_incr&0x0001)>0)
+ 461:Src/stm32f7xx_it.c ****     	          COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 462:Src/stm32f7xx_it.c ****     	      else
+ 463:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf);
+ 464:Src/stm32f7xx_it.c ****             CPU_state = DECODE_TASK;
+ 465:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 466:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 467:Src/stm32f7xx_it.c ****         }
+ 468:Src/stm32f7xx_it.c ****         else
+ 469:Src/stm32f7xx_it.c ****         {
+ 470:Src/stm32f7xx_it.c ****             if ((UART_rec_incr&0x0001)>0)
+ 471:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 472:Src/stm32f7xx_it.c ****             else
+ 473:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf);
+ 474:Src/stm32f7xx_it.c ****             UART_rec_incr++;
+ 475:Src/stm32f7xx_it.c ****             UART_transmission_request = NO_MESS;
+ 476:Src/stm32f7xx_it.c ****         }
+ 477:Src/stm32f7xx_it.c ****     break;
+ 478:Src/stm32f7xx_it.c ****     default:
+ 479:Src/stm32f7xx_it.c ****         if ((UART_rec_incr&0x0001)>0)
+ 480:Src/stm32f7xx_it.c ****             COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 481:Src/stm32f7xx_it.c ****         else
+ 482:Src/stm32f7xx_it.c ****             COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf);
+ 483:Src/stm32f7xx_it.c ****         UART_rec_incr++;
+ 484:Src/stm32f7xx_it.c ****         UART_transmission_request = NO_MESS;
+ 485:Src/stm32f7xx_it.c ****     break;
+ 486:Src/stm32f7xx_it.c ****     }
+ 487:Src/stm32f7xx_it.c **** //    HAL_UART_Receive_IT(&huart1, &uart_buf, 1);
+ 488:Src/stm32f7xx_it.c **** }
+ 595              		.loc 1 488 1 is_stmt 0 view .LVU94
+ 596 0072 5DF8044B 		ldr	r4, [sp], #4
+ 597              	.LCFI5:
+ 598              		.cfi_remember_state
+ 599              		.cfi_restore 4
+ 600              		.cfi_def_cfa_offset 0
+ 601 0076 7047     		bx	lr
+ 602              	.L42:
+ 603              	.LCFI6:
+ 604              		.cfi_restore_state
+ 391:Src/stm32f7xx_it.c ****         switch (UART_header)
+ 605              		.loc 1 391 9 is_stmt 1 view .LVU95
+ 391:Src/stm32f7xx_it.c ****         switch (UART_header)
+ 606              		.loc 1 391 21 is_stmt 0 view .LVU96
+ 607 0078 7F49     		ldr	r1, .L71+24
+ 608 007a 0B88     		ldrh	r3, [r1]
+ 609 007c 03EB0222 		add	r2, r3, r2, lsl #8
+ 610 0080 92B2     		uxth	r2, r2
+ 611 0082 0A80     		strh	r2, [r1]	@ movhi
+ 392:Src/stm32f7xx_it.c ****         {
+ 612              		.loc 1 392 9 is_stmt 1 view .LVU97
+ 613 0084 44F24443 		movw	r3, #17476
+ 614 0088 9A42     		cmp	r2, r3
+ 615 008a 3BD0     		beq	.L45
+ 616 008c 18D8     		bhi	.L46
+ 617 008e 42F22223 		movw	r3, #8738
+ 618 0092 9A42     		cmp	r2, r3
+ 619 0094 2DD0     		beq	.L47
+ARM GAS  /tmp/cc8Pc1nf.s 			page 150
+
+
+ 620 0096 43F23333 		movw	r3, #13107
+ 621 009a 9A42     		cmp	r2, r3
+ 622 009c 08D1     		bne	.L67
+ 403:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 623              		.loc 1 403 13 view .LVU98
+ 403:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 624              		.loc 1 403 27 is_stmt 0 view .LVU99
+ 625 009e 0023     		movs	r3, #0
+ 626 00a0 714A     		ldr	r2, .L71+8
+ 627 00a2 1380     		strh	r3, [r2]	@ movhi
+ 404:Src/stm32f7xx_it.c ****             CPU_state = TRANS_S_ENABLE;
+ 628              		.loc 1 404 13 is_stmt 1 view .LVU100
+ 404:Src/stm32f7xx_it.c ****             CPU_state = TRANS_S_ENABLE;
+ 629              		.loc 1 404 21 is_stmt 0 view .LVU101
+ 630 00a4 734A     		ldr	r2, .L71+20
+ 631 00a6 1370     		strb	r3, [r2]
+ 405:Src/stm32f7xx_it.c ****         break;
+ 632              		.loc 1 405 13 is_stmt 1 view .LVU102
+ 405:Src/stm32f7xx_it.c ****         break;
+ 633              		.loc 1 405 23 is_stmt 0 view .LVU103
+ 634 00a8 744B     		ldr	r3, .L71+28
+ 635 00aa 0322     		movs	r2, #3
+ 636 00ac 1A70     		strb	r2, [r3]
+ 406:Src/stm32f7xx_it.c ****         case 0x4444: //Received packet
+ 637              		.loc 1 406 9 is_stmt 1 view .LVU104
+ 638 00ae E0E7     		b	.L37
+ 639              	.L67:
+ 640 00b0 41F21113 		movw	r3, #4369
+ 641 00b4 9A42     		cmp	r2, r3
+ 642 00b6 37D1     		bne	.L50
+ 395:Src/stm32f7xx_it.c ****         break;
+ 643              		.loc 1 395 13 view .LVU105
+ 395:Src/stm32f7xx_it.c ****         break;
+ 644              		.loc 1 395 27 is_stmt 0 view .LVU106
+ 645 00b8 6B4B     		ldr	r3, .L71+8
+ 646 00ba 0222     		movs	r2, #2
+ 647 00bc 1A80     		strh	r2, [r3]	@ movhi
+ 396:Src/stm32f7xx_it.c ****         case 0x2222: //Back to default
+ 648              		.loc 1 396 9 is_stmt 1 view .LVU107
+ 649 00be D8E7     		b	.L37
+ 650              	.L46:
+ 651 00c0 46F26663 		movw	r3, #26214
+ 652 00c4 9A42     		cmp	r2, r3
+ 653 00c6 26D0     		beq	.L51
+ 654 00c8 47F27773 		movw	r3, #30583
+ 655 00cc 9A42     		cmp	r2, r3
+ 656 00ce 03D1     		bne	.L68
+ 423:Src/stm32f7xx_it.c ****             break;
+ 657              		.loc 1 423 13 view .LVU108
+ 423:Src/stm32f7xx_it.c ****             break;
+ 658              		.loc 1 423 27 is_stmt 0 view .LVU109
+ 659 00d0 654B     		ldr	r3, .L71+8
+ 660 00d2 0222     		movs	r2, #2
+ 661 00d4 1A80     		strh	r2, [r3]	@ movhi
+ 424:Src/stm32f7xx_it.c ****         default: //error decoding header
+ 662              		.loc 1 424 13 is_stmt 1 view .LVU110
+ 663 00d6 CCE7     		b	.L37
+ARM GAS  /tmp/cc8Pc1nf.s 			page 151
+
+
+ 664              	.L68:
+ 665 00d8 45F25553 		movw	r3, #21845
+ 666 00dc 9A42     		cmp	r2, r3
+ 667 00de 23D1     		bne	.L50
+ 413:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 668              		.loc 1 413 13 view .LVU111
+ 413:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 669              		.loc 1 413 27 is_stmt 0 view .LVU112
+ 670 00e0 0023     		movs	r3, #0
+ 671 00e2 614A     		ldr	r2, .L71+8
+ 672 00e4 1380     		strh	r3, [r2]	@ movhi
+ 414:Src/stm32f7xx_it.c ****             CPU_state = REMOVE_FILE;
+ 673              		.loc 1 414 13 is_stmt 1 view .LVU113
+ 414:Src/stm32f7xx_it.c ****             CPU_state = REMOVE_FILE;
+ 674              		.loc 1 414 21 is_stmt 0 view .LVU114
+ 675 00e6 634A     		ldr	r2, .L71+20
+ 676 00e8 1370     		strb	r3, [r2]
+ 415:Src/stm32f7xx_it.c ****         break;
+ 677              		.loc 1 415 13 is_stmt 1 view .LVU115
+ 415:Src/stm32f7xx_it.c ****         break;
+ 678              		.loc 1 415 23 is_stmt 0 view .LVU116
+ 679 00ea 644B     		ldr	r3, .L71+28
+ 680 00ec 0522     		movs	r2, #5
+ 681 00ee 1A70     		strb	r2, [r3]
+ 416:Src/stm32f7xx_it.c ****         case 0x6666: //Request state
+ 682              		.loc 1 416 9 is_stmt 1 view .LVU117
+ 683 00f0 BFE7     		b	.L37
+ 684              	.L47:
+ 398:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 685              		.loc 1 398 13 view .LVU118
+ 398:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 686              		.loc 1 398 27 is_stmt 0 view .LVU119
+ 687 00f2 0023     		movs	r3, #0
+ 688 00f4 5C4A     		ldr	r2, .L71+8
+ 689 00f6 1380     		strh	r3, [r2]	@ movhi
+ 399:Src/stm32f7xx_it.c ****             CPU_state = DEFAULT_ENABLE;
+ 690              		.loc 1 399 13 is_stmt 1 view .LVU120
+ 399:Src/stm32f7xx_it.c ****             CPU_state = DEFAULT_ENABLE;
+ 691              		.loc 1 399 21 is_stmt 0 view .LVU121
+ 692 00f8 5E4A     		ldr	r2, .L71+20
+ 693 00fa 1370     		strb	r3, [r2]
+ 400:Src/stm32f7xx_it.c ****         break;
+ 694              		.loc 1 400 13 is_stmt 1 view .LVU122
+ 400:Src/stm32f7xx_it.c ****         break;
+ 695              		.loc 1 400 23 is_stmt 0 view .LVU123
+ 696 00fc 5F4B     		ldr	r3, .L71+28
+ 697 00fe 0222     		movs	r2, #2
+ 698 0100 1A70     		strb	r2, [r3]
+ 401:Src/stm32f7xx_it.c ****         case 0x3333: //Transmith saved DATA
+ 699              		.loc 1 401 9 is_stmt 1 view .LVU124
+ 700 0102 B6E7     		b	.L37
+ 701              	.L45:
+ 408:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 702              		.loc 1 408 13 view .LVU125
+ 408:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 703              		.loc 1 408 27 is_stmt 0 view .LVU126
+ 704 0104 0023     		movs	r3, #0
+ARM GAS  /tmp/cc8Pc1nf.s 			page 152
+
+
+ 705 0106 584A     		ldr	r2, .L71+8
+ 706 0108 1380     		strh	r3, [r2]	@ movhi
+ 409:Src/stm32f7xx_it.c ****             CPU_state = TRANS_ENABLE;
+ 707              		.loc 1 409 13 is_stmt 1 view .LVU127
+ 409:Src/stm32f7xx_it.c ****             CPU_state = TRANS_ENABLE;
+ 708              		.loc 1 409 21 is_stmt 0 view .LVU128
+ 709 010a 5A4A     		ldr	r2, .L71+20
+ 710 010c 1370     		strb	r3, [r2]
+ 410:Src/stm32f7xx_it.c ****         break;
+ 711              		.loc 1 410 13 is_stmt 1 view .LVU129
+ 410:Src/stm32f7xx_it.c ****         break;
+ 712              		.loc 1 410 23 is_stmt 0 view .LVU130
+ 713 010e 5B4B     		ldr	r3, .L71+28
+ 714 0110 0422     		movs	r2, #4
+ 715 0112 1A70     		strb	r2, [r3]
+ 411:Src/stm32f7xx_it.c ****         case 0x5555: //Erase saved DATA
+ 716              		.loc 1 411 9 is_stmt 1 view .LVU131
+ 717 0114 ADE7     		b	.L37
+ 718              	.L51:
+ 418:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 719              		.loc 1 418 13 view .LVU132
+ 418:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 720              		.loc 1 418 27 is_stmt 0 view .LVU133
+ 721 0116 0023     		movs	r3, #0
+ 722 0118 534A     		ldr	r2, .L71+8
+ 723 011a 1380     		strh	r3, [r2]	@ movhi
+ 419:Src/stm32f7xx_it.c ****             CPU_state = STATE;
+ 724              		.loc 1 419 13 is_stmt 1 view .LVU134
+ 419:Src/stm32f7xx_it.c ****             CPU_state = STATE;
+ 725              		.loc 1 419 21 is_stmt 0 view .LVU135
+ 726 011c 554A     		ldr	r2, .L71+20
+ 727 011e 1370     		strb	r3, [r2]
+ 420:Src/stm32f7xx_it.c ****         break;
+ 728              		.loc 1 420 13 is_stmt 1 view .LVU136
+ 420:Src/stm32f7xx_it.c ****         break;
+ 729              		.loc 1 420 23 is_stmt 0 view .LVU137
+ 730 0120 564B     		ldr	r3, .L71+28
+ 731 0122 0622     		movs	r2, #6
+ 732 0124 1A70     		strb	r2, [r3]
+ 421:Src/stm32f7xx_it.c ****         case 0x7777:
+ 733              		.loc 1 421 9 is_stmt 1 view .LVU138
+ 734 0126 A4E7     		b	.L37
+ 735              	.L50:
+ 426:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 736              		.loc 1 426 13 view .LVU139
+ 426:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 737              		.loc 1 426 27 is_stmt 0 view .LVU140
+ 738 0128 0023     		movs	r3, #0
+ 739 012a 4F4A     		ldr	r2, .L71+8
+ 740 012c 1380     		strh	r3, [r2]	@ movhi
+ 427:Src/stm32f7xx_it.c ****             //UART_transmission_request = MESS_01;
+ 741              		.loc 1 427 13 is_stmt 1 view .LVU141
+ 427:Src/stm32f7xx_it.c ****             //UART_transmission_request = MESS_01;
+ 742              		.loc 1 427 21 is_stmt 0 view .LVU142
+ 743 012e 514A     		ldr	r2, .L71+20
+ 744 0130 1370     		strb	r3, [r2]
+ 430:Src/stm32f7xx_it.c ****             CPU_state = DEFAULT_ENABLE;//Parking system and send error state!
+ARM GAS  /tmp/cc8Pc1nf.s 			page 153
+
+
+ 745              		.loc 1 430 13 is_stmt 1 view .LVU143
+ 430:Src/stm32f7xx_it.c ****             CPU_state = DEFAULT_ENABLE;//Parking system and send error state!
+ 746              		.loc 1 430 27 is_stmt 0 view .LVU144
+ 747 0132 534A     		ldr	r2, .L71+32
+ 748 0134 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
+ 749 0136 43F00203 		orr	r3, r3, #2
+ 750 013a 1370     		strb	r3, [r2]
+ 431:Src/stm32f7xx_it.c ****         break;
+ 751              		.loc 1 431 13 is_stmt 1 view .LVU145
+ 431:Src/stm32f7xx_it.c ****         break;
+ 752              		.loc 1 431 23 is_stmt 0 view .LVU146
+ 753 013c 4F4B     		ldr	r3, .L71+28
+ 754 013e 0222     		movs	r2, #2
+ 755 0140 1A70     		strb	r2, [r3]
+ 432:Src/stm32f7xx_it.c ****         }
+ 756              		.loc 1 432 9 is_stmt 1 view .LVU147
+ 757 0142 96E7     		b	.L37
+ 758              	.L41:
+ 437:Src/stm32f7xx_it.c ****         {
+ 759              		.loc 1 437 9 view .LVU148
+ 437:Src/stm32f7xx_it.c ****         {
+ 760              		.loc 1 437 25 is_stmt 0 view .LVU149
+ 761 0144 4C49     		ldr	r1, .L71+24
+ 762 0146 0888     		ldrh	r0, [r1]
+ 437:Src/stm32f7xx_it.c ****         {
+ 763              		.loc 1 437 12 view .LVU150
+ 764 0148 41F21111 		movw	r1, #4369
+ 765 014c 8842     		cmp	r0, r1
+ 766 014e 12D0     		beq	.L69
+ 449:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 767              		.loc 1 449 13 is_stmt 1 view .LVU151
+ 449:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 768              		.loc 1 449 16 is_stmt 0 view .LVU152
+ 769 0150 13F0010F 		tst	r3, #1
+ 770 0154 2AD0     		beq	.L57
+ 450:Src/stm32f7xx_it.c ****             else
+ 771              		.loc 1 450 17 is_stmt 1 view .LVU153
+ 450:Src/stm32f7xx_it.c ****             else
+ 772              		.loc 1 450 47 is_stmt 0 view .LVU154
+ 773 0156 5908     		lsrs	r1, r3, #1
+ 774 0158 0139     		subs	r1, r1, #1
+ 775 015a 4A4C     		ldr	r4, .L71+36
+ 776 015c 34F81100 		ldrh	r0, [r4, r1, lsl #1]
+ 777 0160 00EB0222 		add	r2, r0, r2, lsl #8
+ 778 0164 24F81120 		strh	r2, [r4, r1, lsl #1]	@ movhi
+ 779              	.L58:
+ 453:Src/stm32f7xx_it.c ****            UART_transmission_request = NO_MESS;
+ 780              		.loc 1 453 12 is_stmt 1 view .LVU155
+ 453:Src/stm32f7xx_it.c ****            UART_transmission_request = NO_MESS;
+ 781              		.loc 1 453 25 is_stmt 0 view .LVU156
+ 782 0168 0133     		adds	r3, r3, #1
+ 783 016a 3F4A     		ldr	r2, .L71+8
+ 784 016c 1380     		strh	r3, [r2]	@ movhi
+ 454:Src/stm32f7xx_it.c ****         }
+ 785              		.loc 1 454 12 is_stmt 1 view .LVU157
+ 454:Src/stm32f7xx_it.c ****         }
+ 786              		.loc 1 454 38 is_stmt 0 view .LVU158
+ARM GAS  /tmp/cc8Pc1nf.s 			page 154
+
+
+ 787 016e 464B     		ldr	r3, .L71+40
+ 788 0170 0022     		movs	r2, #0
+ 789 0172 1A70     		strb	r2, [r3]
+ 790 0174 7DE7     		b	.L37
+ 791              	.L69:
+ 439:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr >> 1) - 1] += ((uint16_t)(uart_buf)) << 8;
+ 792              		.loc 1 439 13 is_stmt 1 view .LVU159
+ 439:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr >> 1) - 1] += ((uint16_t)(uart_buf)) << 8;
+ 793              		.loc 1 439 16 is_stmt 0 view .LVU160
+ 794 0176 13F0010F 		tst	r3, #1
+ 795 017a 11D0     		beq	.L55
+ 440:Src/stm32f7xx_it.c ****             else
+ 796              		.loc 1 440 17 is_stmt 1 view .LVU161
+ 440:Src/stm32f7xx_it.c ****             else
+ 797              		.loc 1 440 51 is_stmt 0 view .LVU162
+ 798 017c 5B08     		lsrs	r3, r3, #1
+ 799 017e 013B     		subs	r3, r3, #1
+ 800 0180 4048     		ldr	r0, .L71+36
+ 801 0182 30F81310 		ldrh	r1, [r0, r3, lsl #1]
+ 802 0186 01EB0222 		add	r2, r1, r2, lsl #8
+ 803 018a 20F81320 		strh	r2, [r0, r3, lsl #1]	@ movhi
+ 804              	.L56:
+ 443:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 805              		.loc 1 443 13 is_stmt 1 view .LVU163
+ 443:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 806              		.loc 1 443 23 is_stmt 0 view .LVU164
+ 807 018e 3B4B     		ldr	r3, .L71+28
+ 808 0190 0122     		movs	r2, #1
+ 809 0192 1A70     		strb	r2, [r3]
+ 444:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 810              		.loc 1 444 13 is_stmt 1 view .LVU165
+ 444:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 811              		.loc 1 444 27 is_stmt 0 view .LVU166
+ 812 0194 0023     		movs	r3, #0
+ 813 0196 344A     		ldr	r2, .L71+8
+ 814 0198 1380     		strh	r3, [r2]	@ movhi
+ 445:Src/stm32f7xx_it.c ****         }
+ 815              		.loc 1 445 13 is_stmt 1 view .LVU167
+ 445:Src/stm32f7xx_it.c ****         }
+ 816              		.loc 1 445 21 is_stmt 0 view .LVU168
+ 817 019a 364A     		ldr	r2, .L71+20
+ 818 019c 1370     		strb	r3, [r2]
+ 819 019e 68E7     		b	.L37
+ 820              	.L55:
+ 442:Src/stm32f7xx_it.c ****             CPU_state = DECODE_ENABLE;
+ 821              		.loc 1 442 17 is_stmt 1 view .LVU169
+ 442:Src/stm32f7xx_it.c ****             CPU_state = DECODE_ENABLE;
+ 822              		.loc 1 442 40 is_stmt 0 view .LVU170
+ 823 01a0 5B08     		lsrs	r3, r3, #1
+ 442:Src/stm32f7xx_it.c ****             CPU_state = DECODE_ENABLE;
+ 824              		.loc 1 442 46 view .LVU171
+ 825 01a2 013B     		subs	r3, r3, #1
+ 442:Src/stm32f7xx_it.c ****             CPU_state = DECODE_ENABLE;
+ 826              		.loc 1 442 51 view .LVU172
+ 827 01a4 3749     		ldr	r1, .L71+36
+ 828 01a6 21F81320 		strh	r2, [r1, r3, lsl #1]	@ movhi
+ 829 01aa F0E7     		b	.L56
+ARM GAS  /tmp/cc8Pc1nf.s 			page 155
+
+
+ 830              	.L57:
+ 452:Src/stm32f7xx_it.c ****            UART_rec_incr++;
+ 831              		.loc 1 452 17 is_stmt 1 view .LVU173
+ 452:Src/stm32f7xx_it.c ****            UART_rec_incr++;
+ 832              		.loc 1 452 39 is_stmt 0 view .LVU174
+ 833 01ac 5908     		lsrs	r1, r3, #1
+ 452:Src/stm32f7xx_it.c ****            UART_rec_incr++;
+ 834              		.loc 1 452 43 view .LVU175
+ 835 01ae 0139     		subs	r1, r1, #1
+ 452:Src/stm32f7xx_it.c ****            UART_rec_incr++;
+ 836              		.loc 1 452 47 view .LVU176
+ 837 01b0 3448     		ldr	r0, .L71+36
+ 838 01b2 20F81120 		strh	r2, [r0, r1, lsl #1]	@ movhi
+ 839 01b6 D7E7     		b	.L58
+ 840              	.L39:
+ 458:Src/stm32f7xx_it.c ****         {
+ 841              		.loc 1 458 9 is_stmt 1 view .LVU177
+ 458:Src/stm32f7xx_it.c ****         {
+ 842              		.loc 1 458 25 is_stmt 0 view .LVU178
+ 843 01b8 2F49     		ldr	r1, .L71+24
+ 844 01ba 0888     		ldrh	r0, [r1]
+ 458:Src/stm32f7xx_it.c ****         {
+ 845              		.loc 1 458 12 view .LVU179
+ 846 01bc 47F27771 		movw	r1, #30583
+ 847 01c0 8842     		cmp	r0, r1
+ 848 01c2 12D0     		beq	.L70
+ 470:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 849              		.loc 1 470 13 is_stmt 1 view .LVU180
+ 470:Src/stm32f7xx_it.c ****                 COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 850              		.loc 1 470 16 is_stmt 0 view .LVU181
+ 851 01c4 13F0010F 		tst	r3, #1
+ 852 01c8 2AD0     		beq	.L62
+ 471:Src/stm32f7xx_it.c ****             else
+ 853              		.loc 1 471 17 is_stmt 1 view .LVU182
+ 471:Src/stm32f7xx_it.c ****             else
+ 854              		.loc 1 471 47 is_stmt 0 view .LVU183
+ 855 01ca 5908     		lsrs	r1, r3, #1
+ 856 01cc 0139     		subs	r1, r1, #1
+ 857 01ce 2D4C     		ldr	r4, .L71+36
+ 858 01d0 34F81100 		ldrh	r0, [r4, r1, lsl #1]
+ 859 01d4 00EB0222 		add	r2, r0, r2, lsl #8
+ 860 01d8 24F81120 		strh	r2, [r4, r1, lsl #1]	@ movhi
+ 861              	.L63:
+ 474:Src/stm32f7xx_it.c ****             UART_transmission_request = NO_MESS;
+ 862              		.loc 1 474 13 is_stmt 1 view .LVU184
+ 474:Src/stm32f7xx_it.c ****             UART_transmission_request = NO_MESS;
+ 863              		.loc 1 474 26 is_stmt 0 view .LVU185
+ 864 01dc 0133     		adds	r3, r3, #1
+ 865 01de 224A     		ldr	r2, .L71+8
+ 866 01e0 1380     		strh	r3, [r2]	@ movhi
+ 475:Src/stm32f7xx_it.c ****         }
+ 867              		.loc 1 475 13 is_stmt 1 view .LVU186
+ 475:Src/stm32f7xx_it.c ****         }
+ 868              		.loc 1 475 39 is_stmt 0 view .LVU187
+ 869 01e2 294B     		ldr	r3, .L71+40
+ 870 01e4 0022     		movs	r2, #0
+ 871 01e6 1A70     		strb	r2, [r3]
+ARM GAS  /tmp/cc8Pc1nf.s 			page 156
+
+
+ 872 01e8 43E7     		b	.L37
+ 873              	.L70:
+ 460:Src/stm32f7xx_it.c ****     	          COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 874              		.loc 1 460 13 is_stmt 1 view .LVU188
+ 460:Src/stm32f7xx_it.c ****     	          COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 875              		.loc 1 460 16 is_stmt 0 view .LVU189
+ 876 01ea 13F0010F 		tst	r3, #1
+ 877 01ee 11D0     		beq	.L60
+ 461:Src/stm32f7xx_it.c ****     	      else
+ 878              		.loc 1 461 16 is_stmt 1 view .LVU190
+ 461:Src/stm32f7xx_it.c ****     	      else
+ 879              		.loc 1 461 46 is_stmt 0 view .LVU191
+ 880 01f0 5B08     		lsrs	r3, r3, #1
+ 881 01f2 013B     		subs	r3, r3, #1
+ 882 01f4 2348     		ldr	r0, .L71+36
+ 883 01f6 30F81310 		ldrh	r1, [r0, r3, lsl #1]
+ 884 01fa 01EB0222 		add	r2, r1, r2, lsl #8
+ 885 01fe 20F81320 		strh	r2, [r0, r3, lsl #1]	@ movhi
+ 886              	.L61:
+ 464:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 887              		.loc 1 464 13 is_stmt 1 view .LVU192
+ 464:Src/stm32f7xx_it.c ****             UART_rec_incr = 0;
+ 888              		.loc 1 464 23 is_stmt 0 view .LVU193
+ 889 0202 1E4B     		ldr	r3, .L71+28
+ 890 0204 0822     		movs	r2, #8
+ 891 0206 1A70     		strb	r2, [r3]
+ 465:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 892              		.loc 1 465 13 is_stmt 1 view .LVU194
+ 465:Src/stm32f7xx_it.c ****             flg_tmt = 0;//Reset the timeout flag
+ 893              		.loc 1 465 27 is_stmt 0 view .LVU195
+ 894 0208 0023     		movs	r3, #0
+ 895 020a 174A     		ldr	r2, .L71+8
+ 896 020c 1380     		strh	r3, [r2]	@ movhi
+ 466:Src/stm32f7xx_it.c ****         }
+ 897              		.loc 1 466 13 is_stmt 1 view .LVU196
+ 466:Src/stm32f7xx_it.c ****         }
+ 898              		.loc 1 466 21 is_stmt 0 view .LVU197
+ 899 020e 194A     		ldr	r2, .L71+20
+ 900 0210 1370     		strb	r3, [r2]
+ 901 0212 2EE7     		b	.L37
+ 902              	.L60:
+ 463:Src/stm32f7xx_it.c ****             CPU_state = DECODE_TASK;
+ 903              		.loc 1 463 17 is_stmt 1 view .LVU198
+ 463:Src/stm32f7xx_it.c ****             CPU_state = DECODE_TASK;
+ 904              		.loc 1 463 39 is_stmt 0 view .LVU199
+ 905 0214 5B08     		lsrs	r3, r3, #1
+ 463:Src/stm32f7xx_it.c ****             CPU_state = DECODE_TASK;
+ 906              		.loc 1 463 43 view .LVU200
+ 907 0216 013B     		subs	r3, r3, #1
+ 463:Src/stm32f7xx_it.c ****             CPU_state = DECODE_TASK;
+ 908              		.loc 1 463 47 view .LVU201
+ 909 0218 1A49     		ldr	r1, .L71+36
+ 910 021a 21F81320 		strh	r2, [r1, r3, lsl #1]	@ movhi
+ 911 021e F0E7     		b	.L61
+ 912              	.L62:
+ 473:Src/stm32f7xx_it.c ****             UART_rec_incr++;
+ 913              		.loc 1 473 17 is_stmt 1 view .LVU202
+ARM GAS  /tmp/cc8Pc1nf.s 			page 157
+
+
+ 473:Src/stm32f7xx_it.c ****             UART_rec_incr++;
+ 914              		.loc 1 473 39 is_stmt 0 view .LVU203
+ 915 0220 5908     		lsrs	r1, r3, #1
+ 473:Src/stm32f7xx_it.c ****             UART_rec_incr++;
+ 916              		.loc 1 473 43 view .LVU204
+ 917 0222 0139     		subs	r1, r1, #1
+ 473:Src/stm32f7xx_it.c ****             UART_rec_incr++;
+ 918              		.loc 1 473 47 view .LVU205
+ 919 0224 1748     		ldr	r0, .L71+36
+ 920 0226 20F81120 		strh	r2, [r0, r1, lsl #1]	@ movhi
+ 921 022a D7E7     		b	.L63
+ 922              	.L38:
+ 479:Src/stm32f7xx_it.c ****             COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 923              		.loc 1 479 9 is_stmt 1 view .LVU206
+ 479:Src/stm32f7xx_it.c ****             COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
+ 924              		.loc 1 479 12 is_stmt 0 view .LVU207
+ 925 022c 13F0010F 		tst	r3, #1
+ 926 0230 0FD0     		beq	.L64
+ 480:Src/stm32f7xx_it.c ****         else
+ 927              		.loc 1 480 13 is_stmt 1 view .LVU208
+ 480:Src/stm32f7xx_it.c ****         else
+ 928              		.loc 1 480 43 is_stmt 0 view .LVU209
+ 929 0232 5908     		lsrs	r1, r3, #1
+ 930 0234 0139     		subs	r1, r1, #1
+ 931 0236 134C     		ldr	r4, .L71+36
+ 932 0238 34F81100 		ldrh	r0, [r4, r1, lsl #1]
+ 933 023c 00EB0222 		add	r2, r0, r2, lsl #8
+ 934 0240 24F81120 		strh	r2, [r4, r1, lsl #1]	@ movhi
+ 935              	.L65:
+ 483:Src/stm32f7xx_it.c ****         UART_transmission_request = NO_MESS;
+ 936              		.loc 1 483 9 is_stmt 1 view .LVU210
+ 483:Src/stm32f7xx_it.c ****         UART_transmission_request = NO_MESS;
+ 937              		.loc 1 483 22 is_stmt 0 view .LVU211
+ 938 0244 0133     		adds	r3, r3, #1
+ 939 0246 084A     		ldr	r2, .L71+8
+ 940 0248 1380     		strh	r3, [r2]	@ movhi
+ 484:Src/stm32f7xx_it.c ****     break;
+ 941              		.loc 1 484 9 is_stmt 1 view .LVU212
+ 484:Src/stm32f7xx_it.c ****     break;
+ 942              		.loc 1 484 35 is_stmt 0 view .LVU213
+ 943 024a 0F4B     		ldr	r3, .L71+40
+ 944 024c 0022     		movs	r2, #0
+ 945 024e 1A70     		strb	r2, [r3]
+ 485:Src/stm32f7xx_it.c ****     }
+ 946              		.loc 1 485 5 is_stmt 1 view .LVU214
+ 947              		.loc 1 488 1 is_stmt 0 view .LVU215
+ 948 0250 0FE7     		b	.L37
+ 949              	.L64:
+ 482:Src/stm32f7xx_it.c ****         UART_rec_incr++;
+ 950              		.loc 1 482 13 is_stmt 1 view .LVU216
+ 482:Src/stm32f7xx_it.c ****         UART_rec_incr++;
+ 951              		.loc 1 482 35 is_stmt 0 view .LVU217
+ 952 0252 5908     		lsrs	r1, r3, #1
+ 482:Src/stm32f7xx_it.c ****         UART_rec_incr++;
+ 953              		.loc 1 482 39 view .LVU218
+ 954 0254 0139     		subs	r1, r1, #1
+ 482:Src/stm32f7xx_it.c ****         UART_rec_incr++;
+ARM GAS  /tmp/cc8Pc1nf.s 			page 158
+
+
+ 955              		.loc 1 482 43 view .LVU219
+ 956 0256 0B48     		ldr	r0, .L71+36
+ 957 0258 20F81120 		strh	r2, [r0, r1, lsl #1]	@ movhi
+ 958 025c F2E7     		b	.L65
+ 959              	.L72:
+ 960 025e 00BF     		.align	2
+ 961              	.L71:
+ 962 0260 00100140 		.word	1073811456
+ 963 0264 00000000 		.word	uart_buf
+ 964 0268 00000000 		.word	UART_rec_incr
+ 965 026c 00000000 		.word	TO6
+ 966 0270 00000000 		.word	TO6_uart
+ 967 0274 00000000 		.word	flg_tmt
+ 968 0278 00000000 		.word	UART_header
+ 969 027c 00000000 		.word	CPU_state
+ 970 0280 00000000 		.word	State_Data
+ 971 0284 00000000 		.word	COMMAND
+ 972 0288 00000000 		.word	UART_transmission_request
+ 973              		.cfi_endproc
+ 974              	.LFE1200:
+ 976              		.section	.text.USART1_IRQHandler,"ax",%progbits
+ 977              		.align	1
+ 978              		.global	USART1_IRQHandler
+ 979              		.syntax unified
+ 980              		.thumb
+ 981              		.thumb_func
+ 982              		.fpu fpv5-d16
+ 984              	USART1_IRQHandler:
+ 985              	.LFB1195:
+ 255:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN USART1_IRQn 0 */
+ 986              		.loc 1 255 1 is_stmt 1 view -0
+ 987              		.cfi_startproc
+ 988              		@ args = 0, pretend = 0, frame = 8
+ 989              		@ frame_needed = 0, uses_anonymous_args = 0
+ 990 0000 00B5     		push	{lr}
+ 991              	.LCFI7:
+ 992              		.cfi_def_cfa_offset 4
+ 993              		.cfi_offset 14, -4
+ 994 0002 83B0     		sub	sp, sp, #12
+ 995              	.LCFI8:
+ 996              		.cfi_def_cfa_offset 16
+ 257:Src/stm32f7xx_it.c ****   if(LL_USART_IsActiveFlag_RXNE(USART1) && LL_USART_IsEnabledIT_RXNE(USART1))
+ 997              		.loc 1 257 3 view .LVU221
+ 258:Src/stm32f7xx_it.c ****   {
+ 998              		.loc 1 258 3 view .LVU222
+ 999              	.LVL13:
+ 1000              	.LBB68:
+ 1001              	.LBI68:
+2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1002              		.loc 3 2640 26 view .LVU223
+ 1003              	.LBB69:
+2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1004              		.loc 3 2642 3 view .LVU224
+2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1005              		.loc 3 2642 12 is_stmt 0 view .LVU225
+ 1006 0004 304B     		ldr	r3, .L89
+ 1007 0006 DB69     		ldr	r3, [r3, #28]
+ARM GAS  /tmp/cc8Pc1nf.s 			page 159
+
+
+2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1008              		.loc 3 2642 77 view .LVU226
+ 1009 0008 13F0200F 		tst	r3, #32
+ 1010 000c 07D0     		beq	.L74
+ 1011              	.LVL14:
+2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1012              		.loc 3 2642 77 view .LVU227
+ 1013              	.LBE69:
+ 1014              	.LBE68:
+ 1015              	.LBB70:
+ 1016              	.LBI70:
+3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1017              		.loc 3 3366 26 is_stmt 1 view .LVU228
+ 1018              	.LBB71:
+3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1019              		.loc 3 3368 3 view .LVU229
+3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1020              		.loc 3 3368 12 is_stmt 0 view .LVU230
+ 1021 000e 2E4B     		ldr	r3, .L89
+ 1022 0010 1B68     		ldr	r3, [r3]
+3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1023              		.loc 3 3368 80 view .LVU231
+ 1024 0012 13F0200F 		tst	r3, #32
+ 1025 0016 02D0     		beq	.L74
+ 1026              	.LVL15:
+3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1027              		.loc 3 3368 80 view .LVU232
+ 1028              	.LBE71:
+ 1029              	.LBE70:
+ 260:Src/stm32f7xx_it.c ****   }
+ 1030              		.loc 1 260 5 is_stmt 1 view .LVU233
+ 1031 0018 FFF7FEFF 		bl	UART_RxCpltCallback
+ 1032              	.LVL16:
+ 1033 001c 33E0     		b	.L73
+ 1034              	.L74:
+ 264:Src/stm32f7xx_it.c ****     {
+ 1035              		.loc 1 264 5 view .LVU234
+ 1036              	.LVL17:
+ 1037              	.LBB72:
+ 1038              	.LBI72:
+2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1039              		.loc 3 2618 26 view .LVU235
+ 1040              	.LBB73:
+2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1041              		.loc 3 2620 3 view .LVU236
+2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1042              		.loc 3 2620 12 is_stmt 0 view .LVU237
+ 1043 001e 2A4B     		ldr	r3, .L89
+ 1044 0020 DB69     		ldr	r3, [r3, #28]
+2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1045              		.loc 3 2620 75 view .LVU238
+ 1046 0022 13F0080F 		tst	r3, #8
+ 1047 0026 25D1     		bne	.L76
+ 1048              	.LVL18:
+2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1049              		.loc 3 2620 75 view .LVU239
+ 1050              	.LBE73:
+ARM GAS  /tmp/cc8Pc1nf.s 			page 160
+
+
+ 1051              	.LBE72:
+ 269:Src/stm32f7xx_it.c ****     {
+ 1052              		.loc 1 269 10 is_stmt 1 view .LVU240
+ 1053              	.LBB74:
+ 1054              	.LBI74:
+2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1055              		.loc 3 2596 26 view .LVU241
+ 1056              	.LBB75:
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1057              		.loc 3 2598 3 view .LVU242
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1058              		.loc 3 2598 12 is_stmt 0 view .LVU243
+ 1059 0028 274B     		ldr	r3, .L89
+ 1060 002a DB69     		ldr	r3, [r3, #28]
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1061              		.loc 3 2598 73 view .LVU244
+ 1062 002c 13F0020F 		tst	r3, #2
+ 1063 0030 2CD1     		bne	.L77
+ 1064              	.LVL19:
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1065              		.loc 3 2598 73 view .LVU245
+ 1066              	.LBE75:
+ 1067              	.LBE74:
+ 274:Src/stm32f7xx_it.c ****     {
+ 1068              		.loc 1 274 10 is_stmt 1 view .LVU246
+ 1069              	.LBB76:
+ 1070              	.LBI76:
+2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1071              		.loc 3 2607 26 view .LVU247
+ 1072              	.LBB77:
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1073              		.loc 3 2609 3 view .LVU248
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1074              		.loc 3 2609 12 is_stmt 0 view .LVU249
+ 1075 0032 254B     		ldr	r3, .L89
+ 1076 0034 DB69     		ldr	r3, [r3, #28]
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1077              		.loc 3 2609 73 view .LVU250
+ 1078 0036 13F0040F 		tst	r3, #4
+ 1079 003a 31D1     		bne	.L79
+ 1080              	.LVL20:
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1081              		.loc 3 2609 73 view .LVU251
+ 1082              	.LBE77:
+ 1083              	.LBE76:
+ 279:Src/stm32f7xx_it.c ****     {
+ 1084              		.loc 1 279 10 is_stmt 1 view .LVU252
+ 1085              	.LBB78:
+ 1086              	.LBI78:
+2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1087              		.loc 3 2585 26 view .LVU253
+ 1088              	.LBB79:
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1089              		.loc 3 2587 3 view .LVU254
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1090              		.loc 3 2587 12 is_stmt 0 view .LVU255
+ 1091 003c 224B     		ldr	r3, .L89
+ARM GAS  /tmp/cc8Pc1nf.s 			page 161
+
+
+ 1092 003e DB69     		ldr	r3, [r3, #28]
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1093              		.loc 3 2587 73 view .LVU256
+ 1094 0040 13F0010F 		tst	r3, #1
+ 1095 0044 36D1     		bne	.L81
+ 1096              	.LVL21:
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1097              		.loc 3 2587 73 view .LVU257
+ 1098              	.LBE79:
+ 1099              	.LBE78:
+ 286:Src/stm32f7xx_it.c ****       {		
+ 1100              		.loc 1 286 7 is_stmt 1 view .LVU258
+ 1101              	.LBB80:
+ 1102              	.LBI80:
+2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1103              		.loc 3 2651 26 view .LVU259
+ 1104              	.LBB81:
+2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1105              		.loc 3 2653 3 view .LVU260
+2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1106              		.loc 3 2653 12 is_stmt 0 view .LVU261
+ 1107 0046 214B     		ldr	r3, .L89+4
+ 1108 0048 DB69     		ldr	r3, [r3, #28]
+2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1109              		.loc 3 2653 73 view .LVU262
+ 1110 004a 13F0400F 		tst	r3, #64
+ 1111 004e 1AD0     		beq	.L73
+ 1112              	.LVL22:
+2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1113              		.loc 3 2653 73 view .LVU263
+ 1114              	.LBE81:
+ 1115              	.LBE80:
+ 1116              	.LBB82:
+ 1117              	.LBI82:
+3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1118              		.loc 3 3377 26 is_stmt 1 view .LVU264
+ 1119              	.LBB83:
+3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1120              		.loc 3 3379 3 view .LVU265
+3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1121              		.loc 3 3379 12 is_stmt 0 view .LVU266
+ 1122 0050 1E4B     		ldr	r3, .L89+4
+ 1123 0052 1B68     		ldr	r3, [r3]
+3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1124              		.loc 3 3379 77 view .LVU267
+ 1125 0054 13F0400F 		tst	r3, #64
+ 1126 0058 15D0     		beq	.L73
+ 1127              	.LVL23:
+3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1128              		.loc 3 3379 77 view .LVU268
+ 1129              	.LBE83:
+ 1130              	.LBE82:
+ 288:Src/stm32f7xx_it.c ****         //test_counter += 1;
+ 1131              		.loc 1 288 9 is_stmt 1 view .LVU269
+ 1132              	.LBB84:
+ 1133              	.LBI84:
+2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 162
+
+
+ 1134              		.loc 3 2916 22 view .LVU270
+ 1135              	.LBB85:
+2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1136              		.loc 3 2918 3 view .LVU271
+ 1137 005a 1B4B     		ldr	r3, .L89
+ 1138 005c 4022     		movs	r2, #64
+ 1139 005e 1A62     		str	r2, [r3, #32]
+ 1140              	.LVL24:
+ 1141              	.L84:
+2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1142              		.loc 3 2918 3 is_stmt 0 view .LVU272
+ 1143              	.LBE85:
+ 1144              	.LBE84:
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1145              		.loc 3 3215 3 is_stmt 1 view .LVU273
+ 1146              	.LBB86:
+ 1147              	.LBB87:
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1148              		.loc 3 3215 3 view .LVU274
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1149              		.loc 3 3215 3 view .LVU275
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1150              		.loc 3 3215 3 view .LVU276
+ 1151 0060 194A     		ldr	r2, .L89
+ 1152              	.LVL25:
+ 1153              	.LBB88:
+ 1154              	.LBI88:
+ 1155              		.file 4 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.0.4
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     09. April 2018
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+ARM GAS  /tmp/cc8Pc1nf.s 			page 163
+
+
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+ARM GAS  /tmp/cc8Pc1nf.s 			page 164
+
+
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ARM GAS  /tmp/cc8Pc1nf.s 			page 165
+
+
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 166
+
+
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 167
+
+
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ARM GAS  /tmp/cc8Pc1nf.s 			page 168
+
+
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 169
+
+
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/cc8Pc1nf.s 			page 170
+
+
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 171
+
+
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ARM GAS  /tmp/cc8Pc1nf.s 			page 172
+
+
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ARM GAS  /tmp/cc8Pc1nf.s 			page 173
+
+
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ARM GAS  /tmp/cc8Pc1nf.s 			page 174
+
+
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/cc8Pc1nf.s 			page 175
+
+
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 176
+
+
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ARM GAS  /tmp/cc8Pc1nf.s 			page 177
+
+
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ARM GAS  /tmp/cc8Pc1nf.s 			page 178
+
+
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 891:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 892:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 895:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
+ 896:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
+ 897:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 898:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 899:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+ 901:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ 903:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_bswap32(value);
+ 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 905:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 906:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 908:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 910:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 912:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 915:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
+ 916:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 917:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 918:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+ 920:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 922:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 923:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 924:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 925:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 930:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
+ 931:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 932:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ 937:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
+ 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 939:Drivers/CMSIS/Include/cmsis_gcc.h ****   int16_t result;
+ 940:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ARM GAS  /tmp/cc8Pc1nf.s 			page 179
+
+
+ 942:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 945:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 946:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 948:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
+ 949:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
+ 950:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
+ 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
+ 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
+ 953:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 956:Drivers/CMSIS/Include/cmsis_gcc.h ****   op2 %= 32U;
+ 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (op2 == 0U)
+ 958:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 959:Drivers/CMSIS/Include/cmsis_gcc.h ****     return op1;
+ 960:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 961:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
+ 962:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 963:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 964:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 966:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
+ 967:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
+ 968:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
+ 969:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
+ 970:Drivers/CMSIS/Include/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
+ 971:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+ 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 974:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 976:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse bit order of value
+ 977:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
+ 978:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 979:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 980:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+ 982:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 984:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 986:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 987:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 990:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+ 991:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 992:Drivers/CMSIS/Include/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
+ 993:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
+ 994:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 995:Drivers/CMSIS/Include/cmsis_gcc.h ****     result <<= 1U;
+ 996:Drivers/CMSIS/Include/cmsis_gcc.h ****     result |= value & 1U;
+ 997:Drivers/CMSIS/Include/cmsis_gcc.h ****     s--;
+ 998:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ARM GAS  /tmp/cc8Pc1nf.s 			page 180
+
+
+ 999:Drivers/CMSIS/Include/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
+1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1001:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+1002:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1003:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1004:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1005:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1006:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Count leading zeros
+1007:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
+1008:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
+1009:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             number of leading zeros in value
+1010:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1011:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CLZ             (uint8_t)__builtin_clz
+1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1014:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+1015:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+1016:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+1017:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+1018:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1019:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (8 bit)
+1020:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 8 bit value.
+1021:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1022:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
+1023:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1024:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+1025:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1026:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+1027:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1028:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1029:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+1030:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1031:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+1032:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
+1033:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
+1034:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+1035:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1036:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
+1037:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1038:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1039:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1040:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1041:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (16 bit)
+1042:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 16 bit values.
+1043:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1044:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
+1045:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1046:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+1047:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1048:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+1049:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1050:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+1051:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+1053:Drivers/CMSIS/Include/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+1054:Drivers/CMSIS/Include/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
+1055:Drivers/CMSIS/Include/cmsis_gcc.h ****     */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 181
+
+
+1056:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+1057:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1058:Drivers/CMSIS/Include/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
+1059:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1060:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1061:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1062:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1063:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   LDR Exclusive (32 bit)
+1064:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 32 bit values.
+1065:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
+1066:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
+1067:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1068:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+ 1156              		.loc 4 1068 31 view .LVU277
+ 1157              	.LBB89:
+1069:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1070:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t result;
+ 1158              		.loc 4 1070 5 view .LVU278
+1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1072:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 1159              		.loc 4 1072 4 view .LVU279
+ 1160              		.syntax unified
+ 1161              	@ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1162 0062 52E8003F 		ldrex r3, [r2]
+ 1163              	@ 0 "" 2
+ 1164              	.LVL26:
+1073:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1165              		.loc 4 1073 4 view .LVU280
+ 1166              		.loc 4 1073 4 is_stmt 0 view .LVU281
+ 1167              		.thumb
+ 1168              		.syntax unified
+ 1169              	.LBE89:
+ 1170              	.LBE88:
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1171              		.loc 3 3215 3 view .LVU282
+ 1172 0066 23F04003 		bic	r3, r3, #64
+ 1173              	.LVL27:
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1174              		.loc 3 3215 3 is_stmt 1 view .LVU283
+ 1175              	.LBB90:
+ 1176              	.LBI90:
+1074:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1075:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1076:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1077:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1078:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (8 bit)
+1079:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 8 bit values.
+1080:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1081:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1082:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1083:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1084:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1085:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+1086:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1087:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+1088:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1089:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ARM GAS  /tmp/cc8Pc1nf.s 			page 182
+
+
+1090:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+1091:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1092:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1093:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1094:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1095:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (16 bit)
+1096:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 16 bit values.
+1097:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1098:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1099:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1100:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1101:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1102:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+1103:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1104:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+1105:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1106:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+1107:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+1108:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+1109:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1110:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1111:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+1112:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   STR Exclusive (32 bit)
+1113:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 32 bit values.
+1114:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to store
+1115:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
+1116:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          0  Function succeeded
+1117:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return          1  Function failed
+1118:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+1119:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+ 1177              		.loc 4 1119 31 view .LVU284
+ 1178              	.LBB91:
+1120:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+1121:Drivers/CMSIS/Include/cmsis_gcc.h ****    uint32_t result;
+ 1179              		.loc 4 1121 4 view .LVU285
+1122:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+1123:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 1180              		.loc 4 1123 4 view .LVU286
+ 1181              		.syntax unified
+ 1182              	@ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 1183 006a 42E80031 		strex r1, r3, [r2]
+ 1184              	@ 0 "" 2
+ 1185              	.LVL28:
+1124:Drivers/CMSIS/Include/cmsis_gcc.h ****    return(result);
+ 1186              		.loc 4 1124 4 view .LVU287
+ 1187              		.loc 4 1124 4 is_stmt 0 view .LVU288
+ 1188              		.thumb
+ 1189              		.syntax unified
+ 1190              	.LBE91:
+ 1191              	.LBE90:
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1192              		.loc 3 3215 3 view .LVU289
+ 1193 006e 0029     		cmp	r1, #0
+ 1194 0070 F6D1     		bne	.L84
+ 1195 0072 08E0     		b	.L73
+ 1196              	.LVL29:
+ 1197              	.L76:
+ARM GAS  /tmp/cc8Pc1nf.s 			page 183
+
+
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 1198              		.loc 3 3215 3 view .LVU290
+ 1199              	.LBE87:
+ 1200              	.LBE86:
+ 267:Src/stm32f7xx_it.c ****     }
+ 1201              		.loc 1 267 7 is_stmt 1 view .LVU291
+ 1202              	.LBB92:
+ 1203              	.LBI92:
+3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1204              		.loc 3 3658 25 view .LVU292
+ 1205              	.LBB93:
+ 1206              		.loc 3 3660 3 view .LVU293
+ 1207              		.loc 3 3660 20 is_stmt 0 view .LVU294
+ 1208 0074 144B     		ldr	r3, .L89
+ 1209 0076 5B6A     		ldr	r3, [r3, #36]
+ 1210              	.LVL30:
+ 1211              		.loc 3 3660 20 view .LVU295
+ 1212              	.LBE93:
+ 1213              	.LBE92:
+ 267:Src/stm32f7xx_it.c ****     }
+ 1214              		.loc 1 267 11 view .LVU296
+ 1215 0078 9DF80720 		ldrb	r2, [sp, #7]	@ zero_extendqisi2
+ 1216 007c 52FA83F3 		uxtab	r3, r2, r3
+ 1217 0080 DBB2     		uxtb	r3, r3
+ 1218 0082 8DF80730 		strb	r3, [sp, #7]
+ 1219              	.L73:
+ 301:Src/stm32f7xx_it.c **** 
+ 1220              		.loc 1 301 1 view .LVU297
+ 1221 0086 03B0     		add	sp, sp, #12
+ 1222              	.LCFI9:
+ 1223              		.cfi_remember_state
+ 1224              		.cfi_def_cfa_offset 4
+ 1225              		@ sp needed
+ 1226 0088 5DF804FB 		ldr	pc, [sp], #4
+ 1227              	.LVL31:
+ 1228              	.L77:
+ 1229              	.LCFI10:
+ 1230              		.cfi_restore_state
+ 272:Src/stm32f7xx_it.c ****     }
+ 1231              		.loc 1 272 7 is_stmt 1 view .LVU298
+ 1232              	.LBB94:
+ 1233              	.LBI94:
+3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1234              		.loc 3 3658 25 view .LVU299
+ 1235              	.LBB95:
+ 1236              		.loc 3 3660 3 view .LVU300
+ 1237              		.loc 3 3660 20 is_stmt 0 view .LVU301
+ 1238 008c 0E4B     		ldr	r3, .L89
+ 1239 008e 5B6A     		ldr	r3, [r3, #36]
+ 1240              	.LVL32:
+ 1241              		.loc 3 3660 20 view .LVU302
+ 1242              	.LBE95:
+ 1243              	.LBE94:
+ 272:Src/stm32f7xx_it.c ****     }
+ 1244              		.loc 1 272 11 view .LVU303
+ 1245 0090 9DF80720 		ldrb	r2, [sp, #7]	@ zero_extendqisi2
+ 1246 0094 52FA83F3 		uxtab	r3, r2, r3
+ARM GAS  /tmp/cc8Pc1nf.s 			page 184
+
+
+ 1247 0098 DBB2     		uxtb	r3, r3
+ 1248 009a 8DF80730 		strb	r3, [sp, #7]
+ 1249 009e F2E7     		b	.L73
+ 1250              	.LVL33:
+ 1251              	.L79:
+ 277:Src/stm32f7xx_it.c ****     }
+ 1252              		.loc 1 277 7 is_stmt 1 view .LVU304
+ 1253              	.LBB96:
+ 1254              	.LBI96:
+3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1255              		.loc 3 3658 25 view .LVU305
+ 1256              	.LBB97:
+ 1257              		.loc 3 3660 3 view .LVU306
+ 1258              		.loc 3 3660 20 is_stmt 0 view .LVU307
+ 1259 00a0 094B     		ldr	r3, .L89
+ 1260 00a2 5B6A     		ldr	r3, [r3, #36]
+ 1261              	.LVL34:
+ 1262              		.loc 3 3660 20 view .LVU308
+ 1263              	.LBE97:
+ 1264              	.LBE96:
+ 277:Src/stm32f7xx_it.c ****     }
+ 1265              		.loc 1 277 11 view .LVU309
+ 1266 00a4 9DF80720 		ldrb	r2, [sp, #7]	@ zero_extendqisi2
+ 1267 00a8 52FA83F3 		uxtab	r3, r2, r3
+ 1268 00ac DBB2     		uxtb	r3, r3
+ 1269 00ae 8DF80730 		strb	r3, [sp, #7]
+ 1270 00b2 E8E7     		b	.L73
+ 1271              	.LVL35:
+ 1272              	.L81:
+ 282:Src/stm32f7xx_it.c ****     }
+ 1273              		.loc 1 282 7 is_stmt 1 view .LVU310
+ 1274              	.LBB98:
+ 1275              	.LBI98:
+3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 1276              		.loc 3 3658 25 view .LVU311
+ 1277              	.LBB99:
+ 1278              		.loc 3 3660 3 view .LVU312
+ 1279              		.loc 3 3660 20 is_stmt 0 view .LVU313
+ 1280 00b4 044B     		ldr	r3, .L89
+ 1281 00b6 5B6A     		ldr	r3, [r3, #36]
+ 1282              	.LVL36:
+ 1283              		.loc 3 3660 20 view .LVU314
+ 1284              	.LBE99:
+ 1285              	.LBE98:
+ 282:Src/stm32f7xx_it.c ****     }
+ 1286              		.loc 1 282 11 view .LVU315
+ 1287 00b8 9DF80720 		ldrb	r2, [sp, #7]	@ zero_extendqisi2
+ 1288 00bc 52FA83F3 		uxtab	r3, r2, r3
+ 1289 00c0 DBB2     		uxtb	r3, r3
+ 1290 00c2 8DF80730 		strb	r3, [sp, #7]
+ 1291 00c6 DEE7     		b	.L73
+ 1292              	.L90:
+ 1293              		.align	2
+ 1294              	.L89:
+ 1295 00c8 00100140 		.word	1073811456
+ 1296 00cc 00140140 		.word	1073812480
+ 1297              		.cfi_endproc
+ARM GAS  /tmp/cc8Pc1nf.s 			page 185
+
+
+ 1298              	.LFE1195:
+ 1300              		.section	.text.DMA2_Stream7_TransferComplete,"ax",%progbits
+ 1301              		.align	1
+ 1302              		.global	DMA2_Stream7_TransferComplete
+ 1303              		.syntax unified
+ 1304              		.thumb
+ 1305              		.thumb_func
+ 1306              		.fpu fpv5-d16
+ 1308              	DMA2_Stream7_TransferComplete:
+ 1309              	.LFB1201:
+ 489:Src/stm32f7xx_it.c **** 
+ 490:Src/stm32f7xx_it.c **** //-----------------------------------------------
+ 491:Src/stm32f7xx_it.c **** void DMA2_Stream7_TransferComplete(void)
+ 492:Src/stm32f7xx_it.c **** {
+ 1310              		.loc 1 492 1 is_stmt 1 view -0
+ 1311              		.cfi_startproc
+ 1312              		@ args = 0, pretend = 0, frame = 0
+ 1313              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1314              		@ link register save eliminated.
+ 493:Src/stm32f7xx_it.c ****   LL_DMA_ClearFlag_TC7(DMA2);
+ 1315              		.loc 1 493 3 view .LVU317
+ 1316              	.LVL37:
+ 1317              	.LBB100:
+ 1318              	.LBI100:
+ 1319              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @file    stm32f7xx_ll_dma.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief   Header file of DMA LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * This software is licensed under terms that can be found in the LICENSE file in
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifndef __STM32F7xx_LL_DMA_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __STM32F7xx_LL_DMA_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 186
+
+
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined (DMA1) || defined (DMA2)
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL DMA
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** static const uint8_t STREAM_OFFSET_TAB[] =
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** };
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Constants DMA Private Constants
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_SxCR_CHSEL_3)
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define DMA_CHANNEL_SELECTION_8_15
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_SxCR_CHSEL_3 */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER)
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** typedef struct
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         or as Source base address in case of memory to memory trans
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter must be a value between Min_Data = 0 and Max
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         or as Destination base address in case of memory to memory 
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 187
+
+
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter must be a value between Min_Data = 0 and Max
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to pe
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         from memory to memory or from peripheral to memory.
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MODE
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The circular buffer mode cannot be used if the memory
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                               data transfer direction is configured on the selected
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address 
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         is incremented or not.
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PERIPH
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         is incremented or not.
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MEMORY
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         in case of memory to memory transfer direction.
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         in case of memory to memory transfer direction.
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         The data unit is equal to the source buffer configuration s
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         or MemorySize parameters depending in the transfer directio
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter must be a value between Min_Data = 0 and Max
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Channel;                /*!< Specifies the peripheral channel.
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_CHANNEL
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Priority;               /*!< Specifies the channel priority level.
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 188
+
+
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_FIFOMODE
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The Direct mode (FIFO mode disabled) cannot be used i
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         memory-to-memory data transfer is configured on the selecte
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHO
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory t
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         It specifies the amount of data to be transferred in a sing
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         transaction.
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MBURST 
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The burst mode is possible only if the address Increm
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripher
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         It specifies the amount of data to be transferred in a sing
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         transaction. 
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PBURST
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The burst mode is possible only if the address Increm
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } LL_DMA_InitTypeDef;
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_STREAM STREAM
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_0                   0x00000000U
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_1                   0x00000001U
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_2                   0x00000002U
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_3                   0x00000003U
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_4                   0x00000004U
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_5                   0x00000005U
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_6                   0x00000006U
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_7                   0x00000007U
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_ALL                 0xFFFF0000U
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direc
+ARM GAS  /tmp/cc8Pc1nf.s 			page 189
+
+
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direc
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE MODE
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode               
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode             
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mo
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering m
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mo
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH PERIPH
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode 
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode 
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY MEMORY
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disa
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enab
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment 
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment 
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment 
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : By
+ARM GAS  /tmp/cc8Pc1nf.s 			page 190
+
+
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : Ha
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Wo
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offse
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offse
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low      
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium   
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High     
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_0                  0x00000000U                                              
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_1                  DMA_SxCR_CHSEL_0                                         
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_2                  DMA_SxCR_CHSEL_1                                         
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_3                  (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1)                    
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_4                  DMA_SxCR_CHSEL_2                                         
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_5                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)                    
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_6                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)                    
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_7                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_CHANNEL_SELECTION_8_15)
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_8                  DMA_SxCR_CHSEL_3                                         
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_9                  (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0)                    
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_10                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1)                    
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_11                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_12                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2)                    
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_13                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) 
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_14                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) 
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_15                 DMA_SxCR_CHSEL                                           
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_CHANNEL_SELECTION_8_15 */
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MBURST MBURST
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst
+ARM GAS  /tmp/cc8Pc1nf.s 			page 191
+
+
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PBURST PBURST
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral b
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral b
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral b
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral b
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode di
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode en
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */  
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_lev
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_l
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_l
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_l
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empt
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO thresho
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO thresho
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO thresho
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO thresho
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentT
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentT
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 192
+
+
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Write a value in DMA register
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __INSTANCE__ DMA Instance
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __REG__ Register to be written
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __VALUE__ Value to be written in the register
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Read a value in DMA register
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __INSTANCE__ DMA Instance
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __REG__ Register to be read
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Register value
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Convert DMAx_Streamy into DMAx
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __STREAM_INSTANCE__ DMAx_Streamy
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval DMAx
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __STREAM_INSTANCE__ DMAx_Streamy
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval LL_DMA_CHANNEL_y
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
+ARM GAS  /tmp/cc8Pc1nf.s 			page 193
+
+
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  LL_DMA_STREAM_7)
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __DMA_INSTANCE__ DMAx
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __STREAM__ LL_DMA_STREAM_y
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval DMAx_Streamy
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  DMA2_Stream7)
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable DMA stream.
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          EN            LL_DMA_EnableStream
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ARM GAS  /tmp/cc8Pc1nf.s 			page 194
+
+
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Disable DMA stream.
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          EN            LL_DMA_DisableStream
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Check if DMA stream is enabled or disabled.
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          EN            LL_DMA_IsEnabledStream
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Configure all parameters linked to DMA transfer.
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          CIRC          LL_DMA_ConfigTransfer\n
+ARM GAS  /tmp/cc8Pc1nf.s 			page 195
+
+
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PINC          LL_DMA_ConfigTransfer\n
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          MINC          LL_DMA_ConfigTransfer\n
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PSIZE         LL_DMA_ConfigTransfer\n
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          MSIZE         LL_DMA_ConfigTransfer\n
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PL            LL_DMA_ConfigTransfer\n
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PFCTRL        LL_DMA_ConfigTransfer
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Configuration This parameter must be a combination of all the following values:
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *@retval None
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configurati
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****              DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****              Configuration);
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Data transfer direction (read from peripheral or from memory).
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Direction This parameter can be one of the following values:
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 196
+
+
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Data transfer direction (read from peripheral or from memory).
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set DMA mode normal, circular or peripheral flow control.
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CIRC           LL_DMA_SetMode\n
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PFCTRL         LL_DMA_SetMode
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Mode This parameter can be one of the following values:
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_NORMAL
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_CIRCULAR
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_PFCTRL
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get DMA mode normal, circular or peripheral flow control.
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CIRC           LL_DMA_GetMode\n
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PFCTRL         LL_DMA_GetMode
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ARM GAS  /tmp/cc8Pc1nf.s 			page 197
+
+
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_NORMAL
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_CIRCULAR
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_PFCTRL
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Peripheral increment mode.
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  IncrementMode This parameter can be one of the following values:
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_INCREMENT
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral increment mode.
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_INCREMENT
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 198
+
+
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Memory increment mode.
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  IncrementMode This parameter can be one of the following values:
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_INCREMENT
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Memory increment mode.
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_INCREMENT
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Peripheral size.
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ARM GAS  /tmp/cc8Pc1nf.s 			page 199
+
+
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Size This parameter can be one of the following values:
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_WORD
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral size.
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_WORD
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Memory size.
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Size This parameter can be one of the following values:
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_WORD
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 200
+
+
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Memory size.
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_WORD
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Peripheral increment offset size.
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  OffsetSize This parameter can be one of the following values:
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSiz
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral increment offset size.
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ARM GAS  /tmp/cc8Pc1nf.s 			page 201
+
+
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Stream priority level.
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Priority This parameter can be one of the following values:
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_LOW
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_HIGH
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Pr
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream priority level.
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_LOW
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+ARM GAS  /tmp/cc8Pc1nf.s 			page 202
+
+
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_HIGH
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Number of data to transfer.
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This action has no effect if
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         stream is enabled.
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  NbData Between 0 to 0xFFFFFFFF
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR,
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Number of data to transfer.
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Once the stream is enabled, the return value indicate the
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         remaining bytes to be transmitted.
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Select Channel number associated to the Stream.
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CHSEL           LL_DMA_SetChannelSelection
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ARM GAS  /tmp/cc8Pc1nf.s 			page 203
+
+
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Channel This parameter can be one of the following values:
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_0
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_1
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_2
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_3
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_4
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_5
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_6
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_7
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_8 (*)
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_9 (*)
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_10 (*)
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_11 (*)
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_12 (*)
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_13 (*)
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_14 (*)
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_15 (*)
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         (*) value not defined in all devices.
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channe
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get the Channel number associated to the Stream.
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CHSEL           LL_DMA_GetChannelSelection
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_0
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_1
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_2
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_3
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_4
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_5
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_6
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_7
+ARM GAS  /tmp/cc8Pc1nf.s 			page 204
+
+
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_8 (*)
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_9 (*)
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_10 (*)
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_11 (*)
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_12 (*)
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_13 (*)
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_14 (*)
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_15 (*)
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         (*) value not defined in all devices.
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Memory burst transfer configuration.
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Mburst This parameter can be one of the following values:
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_SINGLE
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC4
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC8
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC16
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Memory burst transfer configuration.
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_SINGLE
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC4
+ARM GAS  /tmp/cc8Pc1nf.s 			page 205
+
+
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC8
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC16
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set  Peripheral burst transfer configuration.
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Pburst This parameter can be one of the following values:
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_SINGLE
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC4
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC8
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC16
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral burst transfer configuration.
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_SINGLE
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC4
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC8
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC16
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 206
+
+
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem 
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param CurrentMemory This parameter can be one of the following values:
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Curren
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****    MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem 
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable the double buffer mode.
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ARM GAS  /tmp/cc8Pc1nf.s 			page 207
+
+
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Disable the double buffer mode.
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode 
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get FIFO status.
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_0_25
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_25_50
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_50_75
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_75_100
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_FULL
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Disable Fifo mode.
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
+ARM GAS  /tmp/cc8Pc1nf.s 			page 208
+
+
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable Fifo mode.
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode 
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DM
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Select FIFO threshold.
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Threshold This parameter can be one of the following values:
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 209
+
+
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get FIFO threshold.
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Configure the FIFO .
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         FCR         DMDIS        LL_DMA_ConfigFifo
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  FifoMode This parameter can be one of the following values:
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOMODE_ENABLE
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOMODE_DISABLE
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  FifoThreshold This parameter can be one of the following values:
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint3
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ARM GAS  /tmp/cc8Pc1nf.s 			page 210
+
+
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Configure the Source and Destination addresses.
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA stream is enabled.
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n 
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         PAR         PA          LL_DMA_ConfigAddresses
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  SrcAddress Between 0 to 0xFFFFFFFF
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DstAddress Between 0 to 0xFFFFFFFF
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Direction This parameter can be one of the following values:
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   /* Direction Memory to Periph */
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR,
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   /* Direction Periph to Memory and Memory to Memory */
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   else
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR,
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Set the Memory address.
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA channel is enabled.
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ARM GAS  /tmp/cc8Pc1nf.s 			page 211
+
+
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, 
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Set the Peripheral address.
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA channel is enabled.
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  PeriphAddress Between 0 to 0xFFFFFFFF
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAdd
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, P
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Get the Memory address.
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Get the Peripheral address.
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ARM GAS  /tmp/cc8Pc1nf.s 			page 212
+
+
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Set the Memory to Memory Source address.
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA channel is enabled.
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, M
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Set the Memory to Memory Destination address.
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA channel is enabled.
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 213
+
+
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Get the Memory to Memory Source address.
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****    return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream]))
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Get the Memory to Memory Destination address.
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Memory 1 address (used in case of Double buffer mode).
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ARM GAS  /tmp/cc8Pc1nf.s 			page 214
+
+
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Address Between 0 to 0xFFFFFFFF
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR,
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Memory 1 address (used in case of Double buffer mode).
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 0 half transfer flag.
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 1 half transfer flag.
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
+ARM GAS  /tmp/cc8Pc1nf.s 			page 215
+
+
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 2 half transfer flag.
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 3 half transfer flag.
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 4 half transfer flag.
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 5 half transfer flag.
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 6 half transfer flag.
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ARM GAS  /tmp/cc8Pc1nf.s 			page 216
+
+
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 7 half transfer flag.
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 0 transfer complete flag.
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 1 transfer complete flag.
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 2 transfer complete flag.
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 3 transfer complete flag.
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 4 transfer complete flag.
+ARM GAS  /tmp/cc8Pc1nf.s 			page 217
+
+
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 5 transfer complete flag.
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 6 transfer complete flag.
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
+1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 7 transfer complete flag.
+1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7
+1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
+1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 0 transfer error flag.
+1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0
+1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
+1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
+1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 1 transfer error flag.
+1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1
+1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ARM GAS  /tmp/cc8Pc1nf.s 			page 218
+
+
+1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
+1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 2 transfer error flag.
+1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2
+1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
+1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 3 transfer error flag.
+1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3
+1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
+1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 4 transfer error flag.
+1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4
+1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
+1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 5 transfer error flag.
+1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5
+1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
+1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 6 transfer error flag.
+1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6
+1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ARM GAS  /tmp/cc8Pc1nf.s 			page 219
+
+
+1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
+1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 7 transfer error flag.
+1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7
+1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
+1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 0 direct mode error flag.
+1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0
+1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
+1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
+1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 1 direct mode error flag.
+1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1
+1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
+1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
+1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 2 direct mode error flag.
+1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2
+1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
+1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
+1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 3 direct mode error flag.
+1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3
+1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
+1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ARM GAS  /tmp/cc8Pc1nf.s 			page 220
+
+
+1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
+1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 4 direct mode error flag.
+1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4
+1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
+1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
+1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 5 direct mode error flag.
+1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5
+1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 6 direct mode error flag.
+1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6
+1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
+2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
+2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 7 direct mode error flag.
+2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7
+2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
+2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
+2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 0 FIFO error flag.
+2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0
+2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
+2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
+2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ARM GAS  /tmp/cc8Pc1nf.s 			page 221
+
+
+2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 1 FIFO error flag.
+2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
+2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
+2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 2 FIFO error flag.
+2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2
+2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
+2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
+2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 3 FIFO error flag.
+2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3
+2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
+2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
+2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 4 FIFO error flag.
+2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4
+2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
+2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
+2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 5 FIFO error flag.
+2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5
+2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
+2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
+2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 222
+
+
+2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 6 FIFO error flag.
+2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6
+2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
+2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
+2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream 7 FIFO error flag.
+2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7
+2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
+2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
+2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 0 half transfer flag.
+2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0
+2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
+2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
+2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 1 half transfer flag.
+2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1
+2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
+2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 2 half transfer flag.
+2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2
+2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
+2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 3 half transfer flag.
+2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3
+ARM GAS  /tmp/cc8Pc1nf.s 			page 223
+
+
+2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
+2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 4 half transfer flag.
+2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4
+2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
+2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 5 half transfer flag.
+2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5
+2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
+2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 6 half transfer flag.
+2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6
+2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
+2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 7 half transfer flag.
+2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7
+2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
+2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 0 transfer complete flag.
+2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0
+2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ARM GAS  /tmp/cc8Pc1nf.s 			page 224
+
+
+2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
+2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
+2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 1 transfer complete flag.
+2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1
+2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
+2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 2 transfer complete flag.
+2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2
+2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
+2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 3 transfer complete flag.
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3
+2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
+2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 4 transfer complete flag.
+2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4
+2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
+2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 5 transfer complete flag.
+2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5
+2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+ARM GAS  /tmp/cc8Pc1nf.s 			page 225
+
+
+2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
+2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 6 transfer complete flag.
+2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6
+2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
+2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 7 transfer complete flag.
+2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7
+2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+ 1320              		.loc 5 2277 22 view .LVU318
+ 1321              	.LBB101:
+2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
+ 1322              		.loc 5 2279 3 view .LVU319
+ 1323 0000 024B     		ldr	r3, .L92
+ 1324 0002 4FF00062 		mov	r2, #134217728
+ 1325 0006 DA60     		str	r2, [r3, #12]
+ 1326              	.LVL38:
+ 1327              		.loc 5 2279 3 is_stmt 0 view .LVU320
+ 1328              	.LBE101:
+ 1329              	.LBE100:
+ 494:Src/stm32f7xx_it.c **** }
+ 1330              		.loc 1 494 1 view .LVU321
+ 1331 0008 7047     		bx	lr
+ 1332              	.L93:
+ 1333 000a 00BF     		.align	2
+ 1334              	.L92:
+ 1335 000c 00640240 		.word	1073898496
+ 1336              		.cfi_endproc
+ 1337              	.LFE1201:
+ 1339              		.section	.text.DMA2_Stream7_IRQHandler,"ax",%progbits
+ 1340              		.align	1
+ 1341              		.global	DMA2_Stream7_IRQHandler
+ 1342              		.syntax unified
+ 1343              		.thumb
+ 1344              		.thumb_func
+ 1345              		.fpu fpv5-d16
+ 1347              	DMA2_Stream7_IRQHandler:
+ 1348              	.LFB1199:
+ 360:Src/stm32f7xx_it.c ****   /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
+ 1349              		.loc 1 360 1 is_stmt 1 view -0
+ 1350              		.cfi_startproc
+ 1351              		@ args = 0, pretend = 0, frame = 0
+ 1352              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/cc8Pc1nf.s 			page 226
+
+
+ 1353 0000 08B5     		push	{r3, lr}
+ 1354              	.LCFI11:
+ 1355              		.cfi_def_cfa_offset 8
+ 1356              		.cfi_offset 3, -8
+ 1357              		.cfi_offset 14, -4
+ 362:Src/stm32f7xx_it.c ****   {
+ 1358              		.loc 1 362 3 view .LVU323
+ 1359              	.LVL39:
+ 1360              	.LBB102:
+ 1361              	.LBI102:
+1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 1362              		.loc 5 1837 26 view .LVU324
+ 1363              	.LBB103:
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+ 1364              		.loc 5 1839 3 view .LVU325
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+ 1365              		.loc 5 1839 11 is_stmt 0 view .LVU326
+ 1366 0002 0A4B     		ldr	r3, .L99
+ 1367 0004 5B68     		ldr	r3, [r3, #4]
+ 1368              	.LVL40:
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+ 1369              		.loc 5 1839 11 view .LVU327
+ 1370              	.LBE103:
+ 1371              	.LBE102:
+ 362:Src/stm32f7xx_it.c ****   {
+ 1372              		.loc 1 362 5 view .LVU328
+ 1373 0006 13F0006F 		tst	r3, #134217728
+ 1374 000a 09D1     		bne	.L98
+ 367:Src/stm32f7xx_it.c ****   {
+ 1375              		.loc 1 367 8 is_stmt 1 view .LVU329
+ 1376              	.LVL41:
+ 1377              	.LBB104:
+ 1378              	.LBI104:
+1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 1379              		.loc 5 1925 26 view .LVU330
+ 1380              	.LBB105:
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+ 1381              		.loc 5 1927 3 view .LVU331
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+ 1382              		.loc 5 1927 11 is_stmt 0 view .LVU332
+ 1383 000c 074B     		ldr	r3, .L99
+ 1384 000e 5B68     		ldr	r3, [r3, #4]
+ 1385              	.LVL42:
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 
+ 1386              		.loc 5 1927 11 view .LVU333
+ 1387              	.LBE105:
+ 1388              	.LBE104:
+ 367:Src/stm32f7xx_it.c ****   {
+ 1389              		.loc 1 367 10 view .LVU334
+ 1390 0010 13F0007F 		tst	r3, #33554432
+ 1391 0014 03D0     		beq	.L94
+ 369:Src/stm32f7xx_it.c ****   }
+ 1392              		.loc 1 369 5 is_stmt 1 view .LVU335
+ 1393              	.LVL43:
+ 1394              	.LBB106:
+ 1395              	.LBI106:
+2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ARM GAS  /tmp/cc8Pc1nf.s 			page 227
+
+
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 0 transfer error flag.
+2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0
+2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
+2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
+2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 1 transfer error flag.
+2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1
+2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
+2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 2 transfer error flag.
+2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2
+2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
+2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 3 transfer error flag.
+2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3
+2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
+2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 4 transfer error flag.
+2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4
+2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
+2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ARM GAS  /tmp/cc8Pc1nf.s 			page 228
+
+
+2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 5 transfer error flag.
+2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5
+2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
+2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 6 transfer error flag.
+2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6
+2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
+2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Clear Stream 7 transfer error flag.
+2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7
+2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+ 1396              		.loc 5 2365 22 view .LVU336
+ 1397              	.LBB107:
+2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
+ 1398              		.loc 5 2367 3 view .LVU337
+ 1399 0016 054B     		ldr	r3, .L99
+ 1400 0018 4FF00072 		mov	r2, #33554432
+ 1401 001c DA60     		str	r2, [r3, #12]
+ 1402              	.LVL44:
+ 1403              	.L94:
+ 1404              		.loc 5 2367 3 is_stmt 0 view .LVU338
+ 1405              	.LBE107:
+ 1406              	.LBE106:
+ 376:Src/stm32f7xx_it.c **** 
+ 1407              		.loc 1 376 1 view .LVU339
+ 1408 001e 08BD     		pop	{r3, pc}
+ 1409              	.L98:
+ 364:Src/stm32f7xx_it.c ****     u_tx_flg = 0;//indicate that transfer compete
+ 1410              		.loc 1 364 5 is_stmt 1 view .LVU340
+ 1411 0020 FFF7FEFF 		bl	DMA2_Stream7_TransferComplete
+ 1412              	.LVL45:
+ 365:Src/stm32f7xx_it.c ****   }
+ 1413              		.loc 1 365 5 view .LVU341
+ 365:Src/stm32f7xx_it.c ****   }
+ 1414              		.loc 1 365 14 is_stmt 0 view .LVU342
+ 1415 0024 024B     		ldr	r3, .L99+4
+ 1416 0026 0022     		movs	r2, #0
+ 1417 0028 1A70     		strb	r2, [r3]
+ 1418 002a F8E7     		b	.L94
+ARM GAS  /tmp/cc8Pc1nf.s 			page 229
+
+
+ 1419              	.L100:
+ 1420              		.align	2
+ 1421              	.L99:
+ 1422 002c 00640240 		.word	1073898496
+ 1423 0030 00000000 		.word	u_tx_flg
+ 1424              		.cfi_endproc
+ 1425              	.LFE1199:
+ 1427              		.text
+ 1428              	.Letext0:
+ 1429              		.file 6 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 1430              		.file 7 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 1431              		.file 8 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 1432              		.file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 1433              		.file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h"
+ 1434              		.file 11 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h"
+ 1435              		.file 12 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h"
+ 1436              		.file 13 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+ 1437              		.file 14 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h"
+ 1438              		.file 15 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h"
+ARM GAS  /tmp/cc8Pc1nf.s 			page 230
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_it.c
+     /tmp/cc8Pc1nf.s:17     .text.NMI_Handler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:25     .text.NMI_Handler:0000000000000000 NMI_Handler
+     /tmp/cc8Pc1nf.s:43     .text.HardFault_Handler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:50     .text.HardFault_Handler:0000000000000000 HardFault_Handler
+     /tmp/cc8Pc1nf.s:67     .text.MemManage_Handler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:74     .text.MemManage_Handler:0000000000000000 MemManage_Handler
+     /tmp/cc8Pc1nf.s:91     .text.BusFault_Handler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:98     .text.BusFault_Handler:0000000000000000 BusFault_Handler
+     /tmp/cc8Pc1nf.s:115    .text.UsageFault_Handler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:122    .text.UsageFault_Handler:0000000000000000 UsageFault_Handler
+     /tmp/cc8Pc1nf.s:139    .text.SVC_Handler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:146    .text.SVC_Handler:0000000000000000 SVC_Handler
+     /tmp/cc8Pc1nf.s:159    .text.DebugMon_Handler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:166    .text.DebugMon_Handler:0000000000000000 DebugMon_Handler
+     /tmp/cc8Pc1nf.s:179    .text.PendSV_Handler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:186    .text.PendSV_Handler:0000000000000000 PendSV_Handler
+     /tmp/cc8Pc1nf.s:199    .text.SysTick_Handler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:206    .text.SysTick_Handler:0000000000000000 SysTick_Handler
+     /tmp/cc8Pc1nf.s:226    .text.ADC_IRQHandler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:233    .text.ADC_IRQHandler:0000000000000000 ADC_IRQHandler
+     /tmp/cc8Pc1nf.s:257    .text.ADC_IRQHandler:0000000000000010 $d
+     /tmp/cc8Pc1nf.s:263    .text.TIM1_UP_TIM10_IRQHandler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:270    .text.TIM1_UP_TIM10_IRQHandler:0000000000000000 TIM1_UP_TIM10_IRQHandler
+     /tmp/cc8Pc1nf.s:311    .text.TIM1_UP_TIM10_IRQHandler:0000000000000024 $d
+     /tmp/cc8Pc1nf.s:319    .text.TIM2_IRQHandler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:326    .text.TIM2_IRQHandler:0000000000000000 TIM2_IRQHandler
+     /tmp/cc8Pc1nf.s:339    .text.TIM5_IRQHandler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:346    .text.TIM5_IRQHandler:0000000000000000 TIM5_IRQHandler
+     /tmp/cc8Pc1nf.s:359    .text.TIM6_DAC_IRQHandler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:366    .text.TIM6_DAC_IRQHandler:0000000000000000 TIM6_DAC_IRQHandler
+     /tmp/cc8Pc1nf.s:425    .text.TIM6_DAC_IRQHandler:0000000000000028 $d
+     /tmp/cc8Pc1nf.s:432    .text.TIM7_IRQHandler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:439    .text.TIM7_IRQHandler:0000000000000000 TIM7_IRQHandler
+     /tmp/cc8Pc1nf.s:488    .text.TIM7_IRQHandler:000000000000001c $d
+     /tmp/cc8Pc1nf.s:494    .text.UART_RxCpltCallback:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:501    .text.UART_RxCpltCallback:0000000000000000 UART_RxCpltCallback
+     /tmp/cc8Pc1nf.s:539    .text.UART_RxCpltCallback:000000000000001a $d
+     /tmp/cc8Pc1nf.s:571    .text.UART_RxCpltCallback:000000000000005a $t
+     /tmp/cc8Pc1nf.s:962    .text.UART_RxCpltCallback:0000000000000260 $d
+     /tmp/cc8Pc1nf.s:977    .text.USART1_IRQHandler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:984    .text.USART1_IRQHandler:0000000000000000 USART1_IRQHandler
+     /tmp/cc8Pc1nf.s:1295   .text.USART1_IRQHandler:00000000000000c8 $d
+     /tmp/cc8Pc1nf.s:1301   .text.DMA2_Stream7_TransferComplete:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:1308   .text.DMA2_Stream7_TransferComplete:0000000000000000 DMA2_Stream7_TransferComplete
+     /tmp/cc8Pc1nf.s:1335   .text.DMA2_Stream7_TransferComplete:000000000000000c $d
+     /tmp/cc8Pc1nf.s:1340   .text.DMA2_Stream7_IRQHandler:0000000000000000 $t
+     /tmp/cc8Pc1nf.s:1347   .text.DMA2_Stream7_IRQHandler:0000000000000000 DMA2_Stream7_IRQHandler
+     /tmp/cc8Pc1nf.s:1422   .text.DMA2_Stream7_IRQHandler:000000000000002c $d
+
+UNDEFINED SYMBOLS
+HAL_IncTick
+HAL_ADC_IRQHandler
+hadc1
+hadc3
+HAL_TIM_IRQHandler
+ARM GAS  /tmp/cc8Pc1nf.s 			page 231
+
+
+TO10
+TO10_counter
+htim10
+TIM10_coflag
+HAL_GPIO_TogglePin
+TO6
+TO7
+uart_buf
+UART_rec_incr
+TO6_uart
+flg_tmt
+UART_header
+CPU_state
+State_Data
+COMMAND
+UART_transmission_request
+u_tx_flg
diff --git a/build/stm32f7xx_it.o b/build/stm32f7xx_it.o
new file mode 100644
index 0000000..f961b3c
Binary files /dev/null and b/build/stm32f7xx_it.o differ
diff --git a/build/stm32f7xx_ll_dma.d b/build/stm32f7xx_ll_dma.d
new file mode 100644
index 0000000..49f232a
--- /dev/null
+++ b/build/stm32f7xx_ll_dma.d
@@ -0,0 +1,68 @@
+build/stm32f7xx_ll_dma.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
diff --git a/build/stm32f7xx_ll_dma.lst b/build/stm32f7xx_ll_dma.lst
new file mode 100644
index 0000000..643c2ca
--- /dev/null
+++ b/build/stm32f7xx_ll_dma.lst
@@ -0,0 +1,3509 @@
+ARM GAS  /tmp/ccmfsuWO.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_ll_dma.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.LL_DMA_DeInit,"ax",%progbits
+  17              		.align	1
+  18              		.global	LL_DMA_DeInit
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	LL_DMA_DeInit:
+  26              	.LVL0:
+  27              	.LFB320:
+  28              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @file    stm32f7xx_ll_dma.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @brief   DMA LL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #if defined(USE_FULL_LL_DRIVER)
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Includes ------------------------------------------------------------------*/
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #include "stm32f7xx_ll_dma.h"
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #include "stm32f7xx_ll_bus.h"
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #ifdef  USE_FULL_ASSERT
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #include "stm32_assert.h"
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #else
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define assert_param(expr) ((void)0U)
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #endif
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** @addtogroup STM32F7xx_LL_Driver
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @{
+ARM GAS  /tmp/ccmfsuWO.s 			page 2
+
+
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   */
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #if defined (DMA1) || defined (DMA2)
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** @defgroup DMA_LL DMA
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @{
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   */
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Private types -------------------------------------------------------------*/
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Private variables ---------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Private constants ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Private macros ------------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** @addtogroup DMA_LL_Private_Macros
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @{
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   */
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY)
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL)    || \
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR)  || \
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_MODE_PFCTRL))
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #if  defined(DMA_CHANNEL_SELECTION_8_15)
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_CHANNEL(__VALUE__)            (((__VALUE__) == LL_DMA_CHANNEL_0)  || \
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_1)  || \
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_2)  || \
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_3)  || \
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_4)  || \
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_5)  || \
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_6)  || \
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_7)  || \
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_8)  || \
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_9)  || \
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_10)  || \
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_11)  || \
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_12)  || \
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_13)  || \
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_14)  || \
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_15))
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ARM GAS  /tmp/ccmfsuWO.s 			page 3
+
+
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #else
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_CHANNEL(__VALUE__)            (((__VALUE__) == LL_DMA_CHANNEL_0)  || \
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_1)  || \
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_2)  || \
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_3)  || \
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_4)  || \
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_5)  || \
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_6)  || \
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_CHANNEL_7))
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #endif /* DMA_CHANNEL_SELECTION_8_15 */
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)   ((((INSTANCE) == DMA1) && \
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                            (((STREAM) == LL_DMA_STREAM_0) || \
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                             ((STREAM) == LL_DMA_STREAM_1) || \
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                             ((STREAM) == LL_DMA_STREAM_2) || \
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                             ((STREAM) == LL_DMA_STREAM_3) || \
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                             ((STREAM) == LL_DMA_STREAM_4) || \
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                             ((STREAM) == LL_DMA_STREAM_5) || \
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                             ((STREAM) == LL_DMA_STREAM_6) || \
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                             ((STREAM) == LL_DMA_STREAM_7) || \
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                             ((STREAM) == LL_DMA_STREAM_ALL))) ||\
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                             (((INSTANCE) == DMA2) && \
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                           (((STREAM) == LL_DMA_STREAM_0) || \
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                            ((STREAM) == LL_DMA_STREAM_1) || \
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                            ((STREAM) == LL_DMA_STREAM_2) || \
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                            ((STREAM) == LL_DMA_STREAM_3) || \
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                            ((STREAM) == LL_DMA_STREAM_4) || \
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                            ((STREAM) == LL_DMA_STREAM_5) || \
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                            ((STREAM) == LL_DMA_STREAM_6) || \
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                            ((STREAM) == LL_DMA_STREAM_7) || \
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                                            ((STREAM) == LL_DMA_STREAM_ALL))))
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                           ((STATE) == LL_DMA_FIFOMODE_ENABLE))
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                              ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2)  || \
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                              ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4)  || \
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                              ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                        ((BURST) == LL_DMA_MBURST_INC4)   || \
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                        ((BURST) == LL_DMA_MBURST_INC8)   || \
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                        ((BURST) == LL_DMA_MBURST_INC16))
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                            ((BURST) == LL_DMA_PBURST_INC4)   || \
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                            ((BURST) == LL_DMA_PBURST_INC8)   || \
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                                            ((BURST) == LL_DMA_PBURST_INC16))
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /**
+ARM GAS  /tmp/ccmfsuWO.s 			page 4
+
+
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @}
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   */
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Private function prototypes -----------------------------------------------*/
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Exported functions --------------------------------------------------------*/
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** @addtogroup DMA_LL_Exported_Functions
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @{
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   */
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** @addtogroup DMA_LL_EF_Init
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @{
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   */
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /**
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @brief  De-initialize the DMA registers to their default reset values.
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @param  DMAx DMAx Instance
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @param  Stream This parameter can be one of the following values:
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_0
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_1
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_2
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_3
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_4
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_5
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_6
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_7
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_ALL
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @retval An ErrorStatus enumeration value:
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *          - SUCCESS: DMA registers are de-initialized
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *          - ERROR: DMA registers are not de-initialized
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   */
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** {
+  29              		.loc 1 177 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
+  33              		.loc 1 178 3 view .LVU1
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   ErrorStatus status = SUCCESS;
+  34              		.loc 1 179 3 view .LVU2
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   /* Check the DMA Instance DMAx and Stream parameters*/
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
+  35              		.loc 1 182 3 view .LVU3
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   if (Stream == LL_DMA_STREAM_ALL)
+  36              		.loc 1 184 3 view .LVU4
+  37              		.loc 1 184 6 is_stmt 0 view .LVU5
+  38 0000 11F5803F 		cmn	r1, #65536
+  39 0004 58D0     		beq	.L33
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
+  40              		.loc 1 177 1 view .LVU6
+  41 0006 10B5     		push	{r4, lr}
+  42              	.LCFI0:
+  43              		.cfi_def_cfa_offset 8
+  44              		.cfi_offset 4, -8
+ARM GAS  /tmp/ccmfsuWO.s 			page 5
+
+
+  45              		.cfi_offset 14, -4
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   {
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     if (DMAx == DMA1)
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****       /* Force reset of DMA clock */
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****       /* Release reset of DMA clock */
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     else if (DMAx == DMA2)
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****       /* Force reset of DMA clock */
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****       /* Release reset of DMA clock */
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     else
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****       status = ERROR;
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   }
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   else
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   {
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /* Disable the selected Stream */
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     LL_DMA_DisableStream(DMAx,Stream);
+  46              		.loc 1 210 5 is_stmt 1 view .LVU7
+  47              	.LVL1:
+  48              	.LBB30:
+  49              	.LBI30:
+  50              		.file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @file    stm32f7xx_ll_dma.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief   Header file of DMA LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * This software is licensed under terms that can be found in the LICENSE file in
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifndef __STM32F7xx_LL_DMA_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __STM32F7xx_LL_DMA_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif
+ARM GAS  /tmp/ccmfsuWO.s 			page 6
+
+
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined (DMA1) || defined (DMA2)
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL DMA
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** static const uint8_t STREAM_OFFSET_TAB[] =
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** };
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Constants DMA Private Constants
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_SxCR_CHSEL_3)
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define DMA_CHANNEL_SELECTION_8_15
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_SxCR_CHSEL_3 */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER)
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** typedef struct
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+ARM GAS  /tmp/ccmfsuWO.s 			page 7
+
+
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         or as Source base address in case of memory to memory trans
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter must be a value between Min_Data = 0 and Max
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         or as Destination base address in case of memory to memory 
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter must be a value between Min_Data = 0 and Max
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to pe
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         from memory to memory or from peripheral to memory.
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MODE
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The circular buffer mode cannot be used if the memory
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                               data transfer direction is configured on the selected
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address 
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         is incremented or not.
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PERIPH
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         is incremented or not.
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MEMORY
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         in case of memory to memory transfer direction.
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         in case of memory to memory transfer direction.
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         The data unit is equal to the source buffer configuration s
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         or MemorySize parameters depending in the transfer directio
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter must be a value between Min_Data = 0 and Max
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Channel;                /*!< Specifies the peripheral channel.
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_CHANNEL
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ARM GAS  /tmp/ccmfsuWO.s 			page 8
+
+
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t Priority;               /*!< Specifies the channel priority level.
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for 
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_FIFOMODE
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The Direct mode (FIFO mode disabled) cannot be used i
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         memory-to-memory data transfer is configured on the selecte
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHO
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory t
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         It specifies the amount of data to be transferred in a sing
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         transaction.
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_MBURST 
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The burst mode is possible only if the address Increm
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripher
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         It specifies the amount of data to be transferred in a sing
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         transaction. 
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This parameter can be a value of @ref DMA_LL_EC_PBURST
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         @note The burst mode is possible only if the address Increm
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****                                         This feature can be modified afterwards using unitary funct
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } LL_DMA_InitTypeDef;
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_STREAM STREAM
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_0                   0x00000000U
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_1                   0x00000001U
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_2                   0x00000002U
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_3                   0x00000003U
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_4                   0x00000004U
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_5                   0x00000005U
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_6                   0x00000006U
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_7                   0x00000007U
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_ALL                 0xFFFF0000U
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ARM GAS  /tmp/ccmfsuWO.s 			page 9
+
+
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direc
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direc
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE MODE
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode               
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode             
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mo
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering m
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mo
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH PERIPH
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode 
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode 
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY MEMORY
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disa
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enab
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment 
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment 
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment 
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ARM GAS  /tmp/ccmfsuWO.s 			page 10
+
+
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : By
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : Ha
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Wo
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offse
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offse
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low      
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium   
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High     
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_0                  0x00000000U                                              
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_1                  DMA_SxCR_CHSEL_0                                         
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_2                  DMA_SxCR_CHSEL_1                                         
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_3                  (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1)                    
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_4                  DMA_SxCR_CHSEL_2                                         
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_5                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)                    
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_6                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)                    
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_7                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_CHANNEL_SELECTION_8_15)
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_8                  DMA_SxCR_CHSEL_3                                         
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_9                  (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0)                    
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_10                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1)                    
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_11                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_12                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2)                    
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_13                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) 
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_14                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) 
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_15                 DMA_SxCR_CHSEL                                           
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_CHANNEL_SELECTION_8_15 */
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ARM GAS  /tmp/ccmfsuWO.s 			page 11
+
+
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MBURST MBURST
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PBURST PBURST
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral b
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral b
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral b
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral b
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode di
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode en
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */  
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_lev
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_l
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_l
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_l
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empt
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO thresho
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO thresho
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO thresho
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO thresho
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+ARM GAS  /tmp/ccmfsuWO.s 			page 12
+
+
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentT
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentT
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Write a value in DMA register
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __INSTANCE__ DMA Instance
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __REG__ Register to be written
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __VALUE__ Value to be written in the register
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Read a value in DMA register
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __INSTANCE__ DMA Instance
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __REG__ Register to be read
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Register value
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Convert DMAx_Streamy into DMAx
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __STREAM_INSTANCE__ DMAx_Streamy
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval DMAx
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __STREAM_INSTANCE__ DMAx_Streamy
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval LL_DMA_CHANNEL_y
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
+ARM GAS  /tmp/ccmfsuWO.s 			page 13
+
+
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  LL_DMA_STREAM_7)
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __DMA_INSTANCE__ DMAx
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  __STREAM__ LL_DMA_STREAM_y
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval DMAx_Streamy
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  DMA2_Stream7)
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @}
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****  /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @{
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ARM GAS  /tmp/ccmfsuWO.s 			page 14
+
+
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable DMA stream.
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          EN            LL_DMA_EnableStream
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Disable DMA stream.
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          EN            LL_DMA_DisableStream
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+  51              		.loc 2 517 22 view .LVU8
+  52              	.LBB31:
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+  53              		.loc 2 519 3 view .LVU9
+  54 0008 6C4B     		ldr	r3, .L43
+  55 000a 13F801C0 		ldrb	ip, [r3, r1]	@ zero_extendqisi2
+  56 000e 50F80C30 		ldr	r3, [r0, ip]
+  57 0012 23F00103 		bic	r3, r3, #1
+  58 0016 40F80C30 		str	r3, [r0, ip]
+  59              	.LVL2:
+  60              		.loc 2 519 3 is_stmt 0 view .LVU10
+  61              	.LBE31:
+  62              	.LBE30:
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /* Get the DMA Stream Instance */
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
+  63              		.loc 1 213 5 is_stmt 1 view .LVU11
+  64              		.loc 1 213 34 is_stmt 0 view .LVU12
+  65 001a 694B     		ldr	r3, .L43+4
+  66 001c C31A     		subs	r3, r0, r3
+ARM GAS  /tmp/ccmfsuWO.s 			page 15
+
+
+  67 001e 18BF     		it	ne
+  68 0020 0123     		movne	r3, #1
+  69 0022 0A1E     		subs	r2, r1, #0
+  70 0024 18BF     		it	ne
+  71 0026 0122     		movne	r2, #1
+  72              		.loc 1 213 11 view .LVU13
+  73 0028 53EA0204 		orrs	r4, r3, r2
+  74 002c 64D0     		beq	.L14
+  75              		.loc 1 213 34 discriminator 1 view .LVU14
+  76 002e 654C     		ldr	r4, .L43+8
+  77 0030 B0EB040E 		subs	lr, r0, r4
+  78 0034 18BF     		it	ne
+  79 0036 4FF0010E 		movne	lr, #1
+  80 003a 52EA0E02 		orrs	r2, r2, lr
+  81 003e 6FD0     		beq	.L15
+  82              		.loc 1 213 34 discriminator 3 view .LVU15
+  83 0040 4A1E     		subs	r2, r1, #1
+  84 0042 18BF     		it	ne
+  85 0044 0122     		movne	r2, #1
+  86 0046 53EA0204 		orrs	r4, r3, r2
+  87 004a 6BD0     		beq	.L16
+  88              		.loc 1 213 34 discriminator 5 view .LVU16
+  89 004c 5EEA0202 		orrs	r2, lr, r2
+  90 0050 6AD0     		beq	.L17
+  91              		.loc 1 213 34 discriminator 7 view .LVU17
+  92 0052 8A1E     		subs	r2, r1, #2
+  93 0054 18BF     		it	ne
+  94 0056 0122     		movne	r2, #1
+  95 0058 53EA0204 		orrs	r4, r3, r2
+  96 005c 66D0     		beq	.L18
+  97              		.loc 1 213 34 discriminator 9 view .LVU18
+  98 005e 5EEA0202 		orrs	r2, lr, r2
+  99 0062 65D0     		beq	.L19
+ 100              		.loc 1 213 34 discriminator 11 view .LVU19
+ 101 0064 CA1E     		subs	r2, r1, #3
+ 102 0066 18BF     		it	ne
+ 103 0068 0122     		movne	r2, #1
+ 104 006a 53EA0204 		orrs	r4, r3, r2
+ 105 006e 61D0     		beq	.L20
+ 106              		.loc 1 213 34 discriminator 13 view .LVU20
+ 107 0070 5EEA0202 		orrs	r2, lr, r2
+ 108 0074 60D0     		beq	.L21
+ 109              		.loc 1 213 34 discriminator 15 view .LVU21
+ 110 0076 0A1F     		subs	r2, r1, #4
+ 111 0078 18BF     		it	ne
+ 112 007a 0122     		movne	r2, #1
+ 113 007c 53EA0204 		orrs	r4, r3, r2
+ 114 0080 5CD0     		beq	.L22
+ 115              		.loc 1 213 34 discriminator 17 view .LVU22
+ 116 0082 5EEA0202 		orrs	r2, lr, r2
+ 117 0086 5BD0     		beq	.L23
+ 118              		.loc 1 213 34 discriminator 19 view .LVU23
+ 119 0088 4A1F     		subs	r2, r1, #5
+ 120 008a 18BF     		it	ne
+ 121 008c 0122     		movne	r2, #1
+ 122 008e 53EA0204 		orrs	r4, r3, r2
+ 123 0092 57D0     		beq	.L24
+ARM GAS  /tmp/ccmfsuWO.s 			page 16
+
+
+ 124              		.loc 1 213 34 discriminator 21 view .LVU24
+ 125 0094 5EEA0202 		orrs	r2, lr, r2
+ 126 0098 56D0     		beq	.L25
+ 127              		.loc 1 213 34 discriminator 23 view .LVU25
+ 128 009a 8A1F     		subs	r2, r1, #6
+ 129 009c 18BF     		it	ne
+ 130 009e 0122     		movne	r2, #1
+ 131 00a0 1343     		orrs	r3, r3, r2
+ 132 00a2 53D0     		beq	.L26
+ 133              		.loc 1 213 34 discriminator 25 view .LVU26
+ 134 00a4 5EEA0203 		orrs	r3, lr, r2
+ 135 00a8 52D0     		beq	.L27
+ 136              		.loc 1 213 34 discriminator 27 view .LVU27
+ 137 00aa 454B     		ldr	r3, .L43+4
+ 138 00ac 9842     		cmp	r0, r3
+ 139 00ae 08BF     		it	eq
+ 140 00b0 0729     		cmpeq	r1, #7
+ 141 00b2 4FD1     		bne	.L28
+ 142              		.loc 1 213 34 view .LVU28
+ 143 00b4 B833     		adds	r3, r3, #184
+ 144 00b6 20E0     		b	.L5
+ 145              	.L33:
+ 146              	.LCFI1:
+ 147              		.cfi_def_cfa_offset 0
+ 148              		.cfi_restore 4
+ 149              		.cfi_restore 14
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 150              		.loc 1 186 5 is_stmt 1 view .LVU29
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 151              		.loc 1 186 8 is_stmt 0 view .LVU30
+ 152 00b8 414B     		ldr	r3, .L43+4
+ 153 00ba 9842     		cmp	r0, r3
+ 154 00bc 04D0     		beq	.L34
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 155              		.loc 1 194 10 is_stmt 1 view .LVU31
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 156              		.loc 1 194 13 is_stmt 0 view .LVU32
+ 157 00be 414B     		ldr	r3, .L43+8
+ 158 00c0 9842     		cmp	r0, r3
+ 159 00c2 0DD0     		beq	.L35
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 160              		.loc 1 204 14 view .LVU33
+ 161 00c4 0120     		movs	r0, #1
+ 162              	.LVL3:
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /* Reset DMAx_Streamy configuration register */
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     LL_DMA_WriteReg(tmp, CR, 0U);
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /* Reset DMAx_Streamy remaining bytes register */
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     LL_DMA_WriteReg(tmp, NDTR, 0U);
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /* Reset DMAx_Streamy peripheral address register */
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     LL_DMA_WriteReg(tmp, PAR, 0U);
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /* Reset DMAx_Streamy memory address register */
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     LL_DMA_WriteReg(tmp, M0AR, 0U);
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ARM GAS  /tmp/ccmfsuWO.s 			page 17
+
+
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /* Reset DMAx_Streamy memory address register */
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     LL_DMA_WriteReg(tmp, M1AR, 0U);
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /* Reset DMAx_Streamy FIFO control register */
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /* Reset Channel register field for DMAx Stream*/
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     if(Stream == LL_DMA_STREAM_0)
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        /* Reset the Stream0 pending flags */
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        DMAx->LIFCR = 0x0000003FU;
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     else if(Stream == LL_DMA_STREAM_1)
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        /* Reset the Stream1 pending flags */
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        DMAx->LIFCR = 0x00000F40U;
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     else if(Stream == LL_DMA_STREAM_2)
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        /* Reset the Stream2 pending flags */
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        DMAx->LIFCR = 0x003F0000U;
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     else if(Stream == LL_DMA_STREAM_3)
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        /* Reset the Stream3 pending flags */
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        DMAx->LIFCR = 0x0F400000U;
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     else if(Stream == LL_DMA_STREAM_4)
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        /* Reset the Stream4 pending flags */
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        DMAx->HIFCR = 0x0000003FU;
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     else if(Stream == LL_DMA_STREAM_5)
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        /* Reset the Stream5 pending flags */
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        DMAx->HIFCR = 0x00000F40U;
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     else if(Stream == LL_DMA_STREAM_6)
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        /* Reset the Stream6 pending flags */
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        DMAx->HIFCR = 0x003F0000U;
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     else if(Stream == LL_DMA_STREAM_7)
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        /* Reset the Stream7 pending flags */
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****        DMAx->HIFCR = 0x0F400000U;
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     else
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****       status = ERROR;
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   }
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   return status;
+ 163              		.loc 1 282 3 is_stmt 1 view .LVU34
+ARM GAS  /tmp/ccmfsuWO.s 			page 18
+
+
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** }
+ 164              		.loc 1 283 1 is_stmt 0 view .LVU35
+ 165 00c6 7047     		bx	lr
+ 166              	.LVL4:
+ 167              	.L34:
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 168              		.loc 1 189 7 is_stmt 1 view .LVU36
+ 169              	.LBB32:
+ 170              	.LBI32:
+ 171              		.file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @file    stm32f7xx_ll_bus.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief   Header file of BUS LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @verbatim
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****                       ##### RCC Limitations #####
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ==============================================================================
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       A delay between an RCC peripheral clock enable and the effective peripheral 
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       enabling should be taken into account in order to manage the peripheral read/write 
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       from/to registers.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (+) This delay depends on the peripheral mapping.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****         (++) AHB & APB peripherals, 1 dummy read is necessary
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       Workarounds:
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @endverbatim
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @attention
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * Copyright (c) 2017 STMicroelectronics.
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * All rights reserved.
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * This software is licensed under terms that can be found in the LICENSE file in
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * the root directory of this software component.
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" {
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h"
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ARM GAS  /tmp/ccmfsuWO.s 			page 19
+
+
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC)
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ)
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK)
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM         RCC_AHB1ENR_DTCMRAMEN
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D)
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH)
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI             RCC_AHB1LPENR_AXILPEN
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN
+ARM GAS  /tmp/ccmfsuWO.s 			page 20
+
+
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI)
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG)
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG           RCC_AHB2ENR_JPEGEN
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) 
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES)
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH)
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX)
+ARM GAS  /tmp/ccmfsuWO.s 			page 21
+
+
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4)
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4           RCC_APB1ENR_I2C4EN
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2)
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3)
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC)
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN)
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCEN
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1       RCC_APB2ENR_SDMMC1EN
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2)
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2       RCC_APB2ENR_SDMMC2EN
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6)
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN
+ARM GAS  /tmp/ccmfsuWO.s 			page 22
+
+
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC)
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI)
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0)
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS)
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO         RCC_APB2ENR_MDIOEN
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC)
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC      RCC_APB2ENR_OTGPHYCEN
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB1 peripherals clock.
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\n
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\n
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\n
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\n
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\n
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\n
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\n
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\n
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\n
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\n
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\n
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\n
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\n
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\n
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\n
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\n
+ARM GAS  /tmp/ccmfsuWO.s 			page 23
+
+
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\n
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\n
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\n
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\n
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1ENR, Periphs);
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB1 peripheral clock is enabled or not
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\n
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ARM GAS  /tmp/ccmfsuWO.s 			page 24
+
+
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\n
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\n
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_IsEnabledClock
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB1 peripherals clock.
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\n
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\n
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\n
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\n
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\n
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\n
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\n
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\n
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\n
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\n
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\n
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\n
+ARM GAS  /tmp/ccmfsuWO.s 			page 25
+
+
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\n
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\n
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\n
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\n
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\n
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\n
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\n
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\n
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_DisableClock
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1ENR, Periphs);
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB1 peripherals reset.
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\n
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\n
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\n
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\n
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\n
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\n
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\n
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\n
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\n
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\n
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\n
+ARM GAS  /tmp/ccmfsuWO.s 			page 26
+
+
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\n
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\n
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+ 172              		.loc 3 476 22 view .LVU37
+ 173              	.LBB33:
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1RSTR, Periphs);
+ 174              		.loc 3 478 3 view .LVU38
+ 175 00c8 A3F52053 		sub	r3, r3, #10240
+ 176 00cc 1A69     		ldr	r2, [r3, #16]
+ 177 00ce 42F40012 		orr	r2, r2, #2097152
+ 178 00d2 1A61     		str	r2, [r3, #16]
+ 179              	.LVL5:
+ 180              		.loc 3 478 3 is_stmt 0 view .LVU39
+ 181              	.LBE33:
+ 182              	.LBE32:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 183              		.loc 1 192 7 is_stmt 1 view .LVU40
+ 184              	.LBB34:
+ 185              	.LBI34:
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB1 peripherals reset.
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
+ARM GAS  /tmp/ccmfsuWO.s 			page 27
+
+
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\n
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\n
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\n
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\n
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\n
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+ 186              		.loc 3 523 22 view .LVU41
+ 187              	.LBB35:
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+ 188              		.loc 3 525 3 view .LVU42
+ 189 00d4 1A69     		ldr	r2, [r3, #16]
+ 190 00d6 22F40012 		bic	r2, r2, #2097152
+ 191 00da 1A61     		str	r2, [r3, #16]
+ 192              	.LBE35:
+ 193              	.LBE34:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 194              		.loc 1 179 15 is_stmt 0 view .LVU43
+ 195 00dc 0020     		movs	r0, #0
+ 196              	.LVL6:
+ 197              	.LBB37:
+ 198              	.LBB36:
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 199              		.loc 3 526 1 view .LVU44
+ 200 00de 7047     		bx	lr
+ 201              	.LVL7:
+ 202              	.L35:
+ 203              		.loc 3 526 1 view .LVU45
+ARM GAS  /tmp/ccmfsuWO.s 			page 28
+
+
+ 204              	.LBE36:
+ 205              	.LBE37:
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 206              		.loc 1 197 7 is_stmt 1 view .LVU46
+ 207              	.LBB38:
+ 208              	.LBI38:
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 209              		.loc 3 476 22 view .LVU47
+ 210              	.LBB39:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 211              		.loc 3 478 3 view .LVU48
+ 212 00e0 A3F53053 		sub	r3, r3, #11264
+ 213 00e4 1A69     		ldr	r2, [r3, #16]
+ 214 00e6 42F48002 		orr	r2, r2, #4194304
+ 215 00ea 1A61     		str	r2, [r3, #16]
+ 216              	.LVL8:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 217              		.loc 3 478 3 is_stmt 0 view .LVU49
+ 218              	.LBE39:
+ 219              	.LBE38:
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 220              		.loc 1 200 7 is_stmt 1 view .LVU50
+ 221              	.LBB40:
+ 222              	.LBI40:
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 223              		.loc 3 523 22 view .LVU51
+ 224              	.LBB41:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 225              		.loc 3 525 3 view .LVU52
+ 226 00ec 1A69     		ldr	r2, [r3, #16]
+ 227 00ee 22F48002 		bic	r2, r2, #4194304
+ 228 00f2 1A61     		str	r2, [r3, #16]
+ 229              	.LBE41:
+ 230              	.LBE40:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 231              		.loc 1 179 15 is_stmt 0 view .LVU53
+ 232 00f4 0020     		movs	r0, #0
+ 233              	.LVL9:
+ 234              	.LBB43:
+ 235              	.LBB42:
+ 236              		.loc 3 526 1 view .LVU54
+ 237 00f6 7047     		bx	lr
+ 238              	.LVL10:
+ 239              	.L14:
+ 240              	.LCFI2:
+ 241              		.cfi_def_cfa_offset 8
+ 242              		.cfi_offset 4, -8
+ 243              		.cfi_offset 14, -4
+ 244              		.loc 3 526 1 view .LVU55
+ 245              	.LBE42:
+ 246              	.LBE43:
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 247              		.loc 1 213 11 view .LVU56
+ 248 00f8 334B     		ldr	r3, .L43+12
+ 249              	.L5:
+ 250              	.LVL11:
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ARM GAS  /tmp/ccmfsuWO.s 			page 29
+
+
+ 251              		.loc 1 216 5 is_stmt 1 discriminator 60 view .LVU57
+ 252 00fa 0022     		movs	r2, #0
+ 253 00fc 1A60     		str	r2, [r3]
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 254              		.loc 1 219 5 discriminator 60 view .LVU58
+ 255 00fe 5A60     		str	r2, [r3, #4]
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 256              		.loc 1 222 5 discriminator 60 view .LVU59
+ 257 0100 9A60     		str	r2, [r3, #8]
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 258              		.loc 1 225 5 discriminator 60 view .LVU60
+ 259 0102 DA60     		str	r2, [r3, #12]
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 260              		.loc 1 228 5 discriminator 60 view .LVU61
+ 261 0104 1A61     		str	r2, [r3, #16]
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 262              		.loc 1 231 5 discriminator 60 view .LVU62
+ 263 0106 2122     		movs	r2, #33
+ 264 0108 5A61     		str	r2, [r3, #20]
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 265              		.loc 1 234 5 discriminator 60 view .LVU63
+ 266              	.LVL12:
+ 267              	.LBB44:
+ 268              	.LBI44:
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Check if DMA stream is enabled or disabled.
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          EN            LL_DMA_IsEnabledStream
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval State of bit (1 or 0).
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Configure all parameters linked to DMA transfer.
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          CIRC          LL_DMA_ConfigTransfer\n
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PINC          LL_DMA_ConfigTransfer\n
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          MINC          LL_DMA_ConfigTransfer\n
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PSIZE         LL_DMA_ConfigTransfer\n
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          MSIZE         LL_DMA_ConfigTransfer\n
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PL            LL_DMA_ConfigTransfer\n
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PFCTRL        LL_DMA_ConfigTransfer
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ARM GAS  /tmp/ccmfsuWO.s 			page 30
+
+
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Configuration This parameter must be a combination of all the following values:
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *@retval None
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configurati
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****              DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****              Configuration);
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Data transfer direction (read from peripheral or from memory).
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Direction This parameter can be one of the following values:
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Data transfer direction (read from peripheral or from memory).
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ARM GAS  /tmp/ccmfsuWO.s 			page 31
+
+
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set DMA mode normal, circular or peripheral flow control.
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CIRC           LL_DMA_SetMode\n
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PFCTRL         LL_DMA_SetMode
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Mode This parameter can be one of the following values:
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_NORMAL
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_CIRCULAR
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_PFCTRL
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get DMA mode normal, circular or peripheral flow control.
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CIRC           LL_DMA_GetMode\n
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         CR          PFCTRL         LL_DMA_GetMode
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_NORMAL
+ARM GAS  /tmp/ccmfsuWO.s 			page 32
+
+
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_CIRCULAR
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MODE_PFCTRL
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Peripheral increment mode.
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  IncrementMode This parameter can be one of the following values:
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_INCREMENT
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral increment mode.
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PERIPH_INCREMENT
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Memory increment mode.
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ARM GAS  /tmp/ccmfsuWO.s 			page 33
+
+
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  IncrementMode This parameter can be one of the following values:
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_INCREMENT
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Memory increment mode.
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MEMORY_INCREMENT
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Peripheral size.
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Size This parameter can be one of the following values:
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ARM GAS  /tmp/ccmfsuWO.s 			page 34
+
+
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_WORD
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral size.
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PDATAALIGN_WORD
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Memory size.
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Size This parameter can be one of the following values:
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_WORD
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Memory size.
+ARM GAS  /tmp/ccmfsuWO.s 			page 35
+
+
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MDATAALIGN_WORD
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Peripheral increment offset size.
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  OffsetSize This parameter can be one of the following values:
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSiz
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral increment offset size.
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ARM GAS  /tmp/ccmfsuWO.s 			page 36
+
+
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Stream priority level.
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Priority This parameter can be one of the following values:
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_LOW
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_HIGH
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Pr
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Stream priority level.
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_LOW
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_HIGH
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ARM GAS  /tmp/ccmfsuWO.s 			page 37
+
+
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Number of data to transfer.
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This action has no effect if
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         stream is enabled.
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  NbData Between 0 to 0xFFFFFFFF
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR,
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Number of data to transfer.
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Once the stream is enabled, the return value indicate the
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         remaining bytes to be transmitted.
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Between 0 to 0xFFFFFFFF
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Select Channel number associated to the Stream.
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CHSEL           LL_DMA_SetChannelSelection
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+ARM GAS  /tmp/ccmfsuWO.s 			page 38
+
+
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Channel This parameter can be one of the following values:
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_0
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_1
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_2
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_3
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_4
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_5
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_6
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_7
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_8 (*)
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_9 (*)
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_10 (*)
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_11 (*)
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_12 (*)
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_13 (*)
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_14 (*)
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_15 (*)
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         (*) value not defined in all devices.
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channe
+ 269              		.loc 2 1032 22 discriminator 60 view .LVU64
+ 270              	.LBB45:
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ 271              		.loc 2 1034 3 discriminator 60 view .LVU65
+ 272 010a 50F80C30 		ldr	r3, [r0, ip]
+ 273              	.LVL13:
+ 274              		.loc 2 1034 3 is_stmt 0 discriminator 60 view .LVU66
+ 275 010e 23F0F053 		bic	r3, r3, #503316480
+ 276 0112 40F80C30 		str	r3, [r0, ip]
+ 277              	.LVL14:
+ 278              		.loc 2 1034 3 discriminator 60 view .LVU67
+ 279              	.LBE45:
+ 280              	.LBE44:
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 281              		.loc 1 236 5 is_stmt 1 discriminator 60 view .LVU68
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 282              		.loc 1 236 7 is_stmt 0 discriminator 60 view .LVU69
+ 283 0116 F9B9     		cbnz	r1, .L6
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 284              		.loc 1 239 8 is_stmt 1 view .LVU70
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 285              		.loc 1 239 20 is_stmt 0 view .LVU71
+ 286 0118 3F23     		movs	r3, #63
+ 287 011a 8360     		str	r3, [r0, #8]
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 288              		.loc 1 179 15 view .LVU72
+ 289 011c 0020     		movs	r0, #0
+ 290              	.LVL15:
+ 291              	.L4:
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** }
+ 292              		.loc 1 282 3 is_stmt 1 view .LVU73
+ 293              		.loc 1 283 1 is_stmt 0 view .LVU74
+ARM GAS  /tmp/ccmfsuWO.s 			page 39
+
+
+ 294 011e 10BD     		pop	{r4, pc}
+ 295              	.LVL16:
+ 296              	.L15:
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 297              		.loc 1 213 34 view .LVU75
+ 298 0120 2A4B     		ldr	r3, .L43+16
+ 299 0122 EAE7     		b	.L5
+ 300              	.L16:
+ 301 0124 2A4B     		ldr	r3, .L43+20
+ 302 0126 E8E7     		b	.L5
+ 303              	.L17:
+ 304 0128 2A4B     		ldr	r3, .L43+24
+ 305 012a E6E7     		b	.L5
+ 306              	.L18:
+ 307 012c 2A4B     		ldr	r3, .L43+28
+ 308 012e E4E7     		b	.L5
+ 309              	.L19:
+ 310 0130 2A4B     		ldr	r3, .L43+32
+ 311 0132 E2E7     		b	.L5
+ 312              	.L20:
+ 313 0134 2A4B     		ldr	r3, .L43+36
+ 314 0136 E0E7     		b	.L5
+ 315              	.L21:
+ 316 0138 2A4B     		ldr	r3, .L43+40
+ 317 013a DEE7     		b	.L5
+ 318              	.L22:
+ 319 013c 2A4B     		ldr	r3, .L43+44
+ 320 013e DCE7     		b	.L5
+ 321              	.L23:
+ 322 0140 2A4B     		ldr	r3, .L43+48
+ 323 0142 DAE7     		b	.L5
+ 324              	.L24:
+ 325 0144 2A4B     		ldr	r3, .L43+52
+ 326 0146 D8E7     		b	.L5
+ 327              	.L25:
+ 328 0148 2A4B     		ldr	r3, .L43+56
+ 329 014a D6E7     		b	.L5
+ 330              	.L26:
+ 331 014c 2A4B     		ldr	r3, .L43+60
+ 332 014e D4E7     		b	.L5
+ 333              	.L27:
+ 334 0150 2A4B     		ldr	r3, .L43+64
+ 335 0152 D2E7     		b	.L5
+ 336              	.L28:
+ 337 0154 2A4B     		ldr	r3, .L43+68
+ 338 0156 D0E7     		b	.L5
+ 339              	.LVL17:
+ 340              	.L6:
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 341              		.loc 1 241 10 is_stmt 1 view .LVU76
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 342              		.loc 1 241 12 is_stmt 0 view .LVU77
+ 343 0158 0129     		cmp	r1, #1
+ 344 015a 0DD0     		beq	.L36
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 345              		.loc 1 246 10 is_stmt 1 view .LVU78
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ARM GAS  /tmp/ccmfsuWO.s 			page 40
+
+
+ 346              		.loc 1 246 12 is_stmt 0 view .LVU79
+ 347 015c 0229     		cmp	r1, #2
+ 348 015e 10D0     		beq	.L37
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 349              		.loc 1 251 10 is_stmt 1 view .LVU80
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 350              		.loc 1 251 12 is_stmt 0 view .LVU81
+ 351 0160 0329     		cmp	r1, #3
+ 352 0162 13D0     		beq	.L38
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 353              		.loc 1 256 10 is_stmt 1 view .LVU82
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 354              		.loc 1 256 12 is_stmt 0 view .LVU83
+ 355 0164 0429     		cmp	r1, #4
+ 356 0166 16D0     		beq	.L39
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 357              		.loc 1 261 10 is_stmt 1 view .LVU84
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 358              		.loc 1 261 12 is_stmt 0 view .LVU85
+ 359 0168 0529     		cmp	r1, #5
+ 360 016a 18D0     		beq	.L40
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 361              		.loc 1 266 10 is_stmt 1 view .LVU86
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 362              		.loc 1 266 12 is_stmt 0 view .LVU87
+ 363 016c 0629     		cmp	r1, #6
+ 364 016e 1BD0     		beq	.L41
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 365              		.loc 1 271 10 is_stmt 1 view .LVU88
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     {
+ 366              		.loc 1 271 12 is_stmt 0 view .LVU89
+ 367 0170 0729     		cmp	r1, #7
+ 368 0172 1ED0     		beq	.L42
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 369              		.loc 1 278 14 view .LVU90
+ 370 0174 0120     		movs	r0, #1
+ 371              	.LVL18:
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 372              		.loc 1 278 14 view .LVU91
+ 373 0176 D2E7     		b	.L4
+ 374              	.LVL19:
+ 375              	.L36:
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 376              		.loc 1 244 8 is_stmt 1 view .LVU92
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 377              		.loc 1 244 20 is_stmt 0 view .LVU93
+ 378 0178 4FF47463 		mov	r3, #3904
+ 379 017c 8360     		str	r3, [r0, #8]
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 380              		.loc 1 179 15 view .LVU94
+ 381 017e 0020     		movs	r0, #0
+ 382              	.LVL20:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 383              		.loc 1 179 15 view .LVU95
+ 384 0180 CDE7     		b	.L4
+ 385              	.LVL21:
+ 386              	.L37:
+ARM GAS  /tmp/ccmfsuWO.s 			page 41
+
+
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 387              		.loc 1 249 8 is_stmt 1 view .LVU96
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 388              		.loc 1 249 20 is_stmt 0 view .LVU97
+ 389 0182 4FF47C13 		mov	r3, #4128768
+ 390 0186 8360     		str	r3, [r0, #8]
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 391              		.loc 1 179 15 view .LVU98
+ 392 0188 0020     		movs	r0, #0
+ 393              	.LVL22:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 394              		.loc 1 179 15 view .LVU99
+ 395 018a C8E7     		b	.L4
+ 396              	.LVL23:
+ 397              	.L38:
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 398              		.loc 1 254 8 is_stmt 1 view .LVU100
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 399              		.loc 1 254 20 is_stmt 0 view .LVU101
+ 400 018c 4FF07463 		mov	r3, #255852544
+ 401 0190 8360     		str	r3, [r0, #8]
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 402              		.loc 1 179 15 view .LVU102
+ 403 0192 0020     		movs	r0, #0
+ 404              	.LVL24:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 405              		.loc 1 179 15 view .LVU103
+ 406 0194 C3E7     		b	.L4
+ 407              	.LVL25:
+ 408              	.L39:
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 409              		.loc 1 259 8 is_stmt 1 view .LVU104
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 410              		.loc 1 259 20 is_stmt 0 view .LVU105
+ 411 0196 3F23     		movs	r3, #63
+ 412 0198 C360     		str	r3, [r0, #12]
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 413              		.loc 1 179 15 view .LVU106
+ 414 019a 0020     		movs	r0, #0
+ 415              	.LVL26:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 416              		.loc 1 179 15 view .LVU107
+ 417 019c BFE7     		b	.L4
+ 418              	.LVL27:
+ 419              	.L40:
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 420              		.loc 1 264 8 is_stmt 1 view .LVU108
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 421              		.loc 1 264 20 is_stmt 0 view .LVU109
+ 422 019e 4FF47463 		mov	r3, #3904
+ 423 01a2 C360     		str	r3, [r0, #12]
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 424              		.loc 1 179 15 view .LVU110
+ 425 01a4 0020     		movs	r0, #0
+ 426              	.LVL28:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 427              		.loc 1 179 15 view .LVU111
+ARM GAS  /tmp/ccmfsuWO.s 			page 42
+
+
+ 428 01a6 BAE7     		b	.L4
+ 429              	.LVL29:
+ 430              	.L41:
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 431              		.loc 1 269 8 is_stmt 1 view .LVU112
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 432              		.loc 1 269 20 is_stmt 0 view .LVU113
+ 433 01a8 4FF47C13 		mov	r3, #4128768
+ 434 01ac C360     		str	r3, [r0, #12]
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 435              		.loc 1 179 15 view .LVU114
+ 436 01ae 0020     		movs	r0, #0
+ 437              	.LVL30:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 438              		.loc 1 179 15 view .LVU115
+ 439 01b0 B5E7     		b	.L4
+ 440              	.LVL31:
+ 441              	.L42:
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 442              		.loc 1 274 8 is_stmt 1 view .LVU116
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     }
+ 443              		.loc 1 274 20 is_stmt 0 view .LVU117
+ 444 01b2 4FF07463 		mov	r3, #255852544
+ 445 01b6 C360     		str	r3, [r0, #12]
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 446              		.loc 1 179 15 view .LVU118
+ 447 01b8 0020     		movs	r0, #0
+ 448              	.LVL32:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 449              		.loc 1 179 15 view .LVU119
+ 450 01ba B0E7     		b	.L4
+ 451              	.L44:
+ 452              		.align	2
+ 453              	.L43:
+ 454 01bc 00000000 		.word	.LANCHOR0
+ 455 01c0 00600240 		.word	1073897472
+ 456 01c4 00640240 		.word	1073898496
+ 457 01c8 10600240 		.word	1073897488
+ 458 01cc 10640240 		.word	1073898512
+ 459 01d0 28600240 		.word	1073897512
+ 460 01d4 28640240 		.word	1073898536
+ 461 01d8 40600240 		.word	1073897536
+ 462 01dc 40640240 		.word	1073898560
+ 463 01e0 58600240 		.word	1073897560
+ 464 01e4 58640240 		.word	1073898584
+ 465 01e8 70600240 		.word	1073897584
+ 466 01ec 70640240 		.word	1073898608
+ 467 01f0 88600240 		.word	1073897608
+ 468 01f4 88640240 		.word	1073898632
+ 469 01f8 A0600240 		.word	1073897632
+ 470 01fc A0640240 		.word	1073898656
+ 471 0200 B8640240 		.word	1073898680
+ 472              		.cfi_endproc
+ 473              	.LFE320:
+ 475              		.section	.text.LL_DMA_Init,"ax",%progbits
+ 476              		.align	1
+ 477              		.global	LL_DMA_Init
+ARM GAS  /tmp/ccmfsuWO.s 			page 43
+
+
+ 478              		.syntax unified
+ 479              		.thumb
+ 480              		.thumb_func
+ 481              		.fpu fpv5-d16
+ 483              	LL_DMA_Init:
+ 484              	.LVL33:
+ 485              	.LFB321:
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /**
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @note   To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref __LL_DMA_GET_INSTANCE
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref __LL_DMA_GET_STREAM
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @param  DMAx DMAx Instance
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @param  Stream This parameter can be one of the following values:
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_0
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_1
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_2
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_3
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_4
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_5
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_6
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *         @arg @ref LL_DMA_STREAM_7
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @retval An ErrorStatus enumeration value:
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *          - SUCCESS: DMA registers are initialized
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   *          - ERROR: Not applicable
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   */
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** {
+ 486              		.loc 1 306 1 is_stmt 1 view -0
+ 487              		.cfi_startproc
+ 488              		@ args = 0, pretend = 0, frame = 0
+ 489              		@ frame_needed = 0, uses_anonymous_args = 0
+ 490              		@ link register save eliminated.
+ 491              		.loc 1 306 1 is_stmt 0 view .LVU121
+ 492 0000 30B4     		push	{r4, r5}
+ 493              	.LCFI3:
+ 494              		.cfi_def_cfa_offset 8
+ 495              		.cfi_offset 4, -8
+ 496              		.cfi_offset 5, -4
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   /* Check the DMA Instance DMAx and Stream parameters*/
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
+ 497              		.loc 1 308 3 is_stmt 1 view .LVU122
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   /* Check the DMA parameters from DMA_InitStruct */
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+ 498              		.loc 1 311 3 view .LVU123
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+ 499              		.loc 1 312 3 view .LVU124
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+ 500              		.loc 1 313 3 view .LVU125
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+ 501              		.loc 1 314 3 view .LVU126
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+ 502              		.loc 1 315 3 view .LVU127
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+ARM GAS  /tmp/ccmfsuWO.s 			page 44
+
+
+ 503              		.loc 1 316 3 view .LVU128
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+ 504              		.loc 1 317 3 view .LVU129
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
+ 505              		.loc 1 318 3 view .LVU130
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+ 506              		.loc 1 319 3 view .LVU131
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
+ 507              		.loc 1 320 3 view .LVU132
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****      when FIFO mode is enabled */
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
+ 508              		.loc 1 323 3 view .LVU133
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   {
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
+ 509              		.loc 1 325 5 view .LVU134
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
+ 510              		.loc 1 326 5 view .LVU135
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
+ 511              		.loc 1 327 5 view .LVU136
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   }
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   /*---------------------------- DMAx SxCR Configuration ------------------------
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * Configure DMAx_Streamy: data transfer direction, data transfer mode,
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    *                          peripheral and memory increment mode,
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    *                          data size alignment and  priority level with parameters :
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * - Direction:      DMA_SxCR_DIR[1:0] bits
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * - Mode:           DMA_SxCR_CIRC bit
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * - PeriphOrM2MSrcIncMode:  DMA_SxCR_PINC bit
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * - MemoryOrM2MDstIncMode:  DMA_SxCR_MINC bit
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * - Priority:               DMA_SxCR_PL[1:0] bits
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    */
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
+ 512              		.loc 1 342 3 view .LVU137
+ 513              		.loc 1 342 53 is_stmt 0 view .LVU138
+ 514 0002 9368     		ldr	r3, [r2, #8]
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->Mode                    | \
+ 515              		.loc 1 343 39 view .LVU139
+ 516 0004 D468     		ldr	r4, [r2, #12]
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->Mode                    | \
+ 517              		.loc 1 342 65 view .LVU140
+ 518 0006 2343     		orrs	r3, r3, r4
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->PeriphOrM2MSrcIncMode   | \
+ 519              		.loc 1 344 39 view .LVU141
+ 520 0008 1469     		ldr	r4, [r2, #16]
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->Mode                    | \
+ 521              		.loc 1 343 65 view .LVU142
+ 522 000a 2343     		orrs	r3, r3, r4
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->MemoryOrM2MDstIncMode   | \
+ 523              		.loc 1 345 39 view .LVU143
+ 524 000c 5469     		ldr	r4, [r2, #20]
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->PeriphOrM2MSrcIncMode   | \
+ 525              		.loc 1 344 65 view .LVU144
+ 526 000e 2343     		orrs	r3, r3, r4
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->PeriphOrM2MSrcDataSize  | \
+ARM GAS  /tmp/ccmfsuWO.s 			page 45
+
+
+ 527              		.loc 1 346 39 view .LVU145
+ 528 0010 9469     		ldr	r4, [r2, #24]
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->MemoryOrM2MDstIncMode   | \
+ 529              		.loc 1 345 65 view .LVU146
+ 530 0012 2343     		orrs	r3, r3, r4
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->MemoryOrM2MDstDataSize  | \
+ 531              		.loc 1 347 39 view .LVU147
+ 532 0014 D469     		ldr	r4, [r2, #28]
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->PeriphOrM2MSrcDataSize  | \
+ 533              		.loc 1 346 65 view .LVU148
+ 534 0016 2343     		orrs	r3, r3, r4
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->Priority
+ 535              		.loc 1 348 39 view .LVU149
+ 536 0018 946A     		ldr	r4, [r2, #40]
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         DMA_InitStruct->Mode                    | \
+ 537              		.loc 1 342 3 view .LVU150
+ 538 001a 2343     		orrs	r3, r3, r4
+ 539              	.LVL34:
+ 540              	.LBB46:
+ 541              	.LBI46:
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 542              		.loc 2 572 22 is_stmt 1 view .LVU151
+ 543              	.LBB47:
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****              DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx
+ 544              		.loc 2 574 3 view .LVU152
+ 545 001c 1B4C     		ldr	r4, .L48
+ 546 001e 615C     		ldrb	r1, [r4, r1]	@ zero_extendqisi2
+ 547              	.LVL35:
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****              DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx
+ 548              		.loc 2 574 3 is_stmt 0 view .LVU153
+ 549 0020 01EB000C 		add	ip, r1, r0
+ 550 0024 0D58     		ldr	r5, [r1, r0]
+ 551 0026 1A4C     		ldr	r4, .L48+4
+ 552 0028 2C40     		ands	r4, r4, r5
+ 553 002a 2343     		orrs	r3, r3, r4
+ 554              	.LVL36:
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****              DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx
+ 555              		.loc 2 574 3 view .LVU154
+ 556 002c 0B50     		str	r3, [r1, r0]
+ 557              	.LVL37:
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****              DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx
+ 558              		.loc 2 574 3 view .LVU155
+ 559              	.LBE47:
+ 560              	.LBE46:
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****                         );
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
+ 561              		.loc 1 351 3 is_stmt 1 view .LVU156
+ 562              		.loc 1 351 20 is_stmt 0 view .LVU157
+ 563 002e D36A     		ldr	r3, [r2, #44]
+ 564              		.loc 1 351 5 view .LVU158
+ 565 0030 A3B1     		cbz	r3, .L46
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   {
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /*---------------------------- DMAx SxFCR Configuration ------------------------
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****      * Configure DMAx_Streamy:  fifo mode and fifo threshold with parameters :
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****      * - FIFOMode:                DMA_SxFCR_DMDIS bit
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****      * - FIFOThreshold:           DMA_SxFCR_FTH[1:0] bits
+ARM GAS  /tmp/ccmfsuWO.s 			page 46
+
+
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****      */
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);   
+ 566              		.loc 1 358 5 is_stmt 1 view .LVU159
+ 567 0032 156B     		ldr	r5, [r2, #48]
+ 568              	.LVL38:
+ 569              	.LBB48:
+ 570              	.LBI48:
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get the Channel number associated to the Stream.
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CHSEL           LL_DMA_GetChannelSelection
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_0
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_1
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_2
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_3
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_4
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_5
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_6
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_7
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_8 (*)
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_9 (*)
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_10 (*)
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_11 (*)
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_12 (*)
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_13 (*)
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_14 (*)
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CHANNEL_15 (*)
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         (*) value not defined in all devices.
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Memory burst transfer configuration.
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+ARM GAS  /tmp/ccmfsuWO.s 			page 47
+
+
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Mburst This parameter can be one of the following values:
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_SINGLE
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC4
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC8
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC16
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Memory burst transfer configuration.
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_SINGLE
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC4
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC8
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_MBURST_INC16
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set  Peripheral burst transfer configuration.
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Pburst This parameter can be one of the following values:
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_SINGLE
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC4
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC8
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC16
+ARM GAS  /tmp/ccmfsuWO.s 			page 48
+
+
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get Peripheral burst transfer configuration.
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_SINGLE
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC4
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC8
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_PBURST_INC16
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem 
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param CurrentMemory This parameter can be one of the following values:
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Curren
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****    MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem 
+ARM GAS  /tmp/ccmfsuWO.s 			page 49
+
+
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable the double buffer mode.
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Disable the double buffer mode.
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode 
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D
+ARM GAS  /tmp/ccmfsuWO.s 			page 50
+
+
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get FIFO status.
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_0_25
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_25_50
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_50_75
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_75_100
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOSTATUS_FULL
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Disable Fifo mode.
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Enable Fifo mode.
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode 
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+ARM GAS  /tmp/ccmfsuWO.s 			page 51
+
+
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DM
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Select FIFO threshold.
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Threshold This parameter can be one of the following values:
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Get FIFO threshold.
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval Returned value can be one of the following values:
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ARM GAS  /tmp/ccmfsuWO.s 			page 52
+
+
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Configure the FIFO .
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         FCR         DMDIS        LL_DMA_ConfigFifo
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  FifoMode This parameter can be one of the following values:
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOMODE_ENABLE
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOMODE_DISABLE
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  FifoThreshold This parameter can be one of the following values:
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint3
+ 571              		.loc 2 1397 22 view .LVU160
+ 572              	.LBB49:
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 
+ 573              		.loc 2 1399 3 view .LVU161
+ 574 0034 DCF81440 		ldr	r4, [ip, #20]
+ 575 0038 24F00704 		bic	r4, r4, #7
+ 576 003c 2B43     		orrs	r3, r3, r5
+ 577              	.LVL39:
+ 578              		.loc 2 1399 3 is_stmt 0 view .LVU162
+ 579 003e 2343     		orrs	r3, r3, r4
+ 580 0040 CCF81430 		str	r3, [ip, #20]
+ 581              	.LVL40:
+ 582              		.loc 2 1399 3 view .LVU163
+ 583              	.LBE49:
+ 584              	.LBE48:
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /*---------------------------- DMAx SxCR Configuration --------------------------
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****      * Configure DMAx_Streamy:  memory burst transfer with parameters :
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****      * - MemBurst:                DMA_SxCR_MBURST[1:0] bits
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****      */
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst); 
+ 585              		.loc 1 364 5 is_stmt 1 view .LVU164
+ 586 0044 536B     		ldr	r3, [r2, #52]
+ 587              	.LVL41:
+ 588              	.LBB50:
+ 589              	.LBI50:
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 590              		.loc 2 1095 22 view .LVU165
+ARM GAS  /tmp/ccmfsuWO.s 			page 53
+
+
+ 591              	.LBB51:
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 592              		.loc 2 1097 3 view .LVU166
+ 593 0046 0C58     		ldr	r4, [r1, r0]
+ 594 0048 24F0C074 		bic	r4, r4, #25165824
+ 595 004c 2343     		orrs	r3, r3, r4
+ 596              	.LVL42:
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 597              		.loc 2 1097 3 is_stmt 0 view .LVU167
+ 598 004e 0B50     		str	r3, [r1, r0]
+ 599              	.LVL43:
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 600              		.loc 2 1097 3 view .LVU168
+ 601              	.LBE51:
+ 602              	.LBE50:
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     /*---------------------------- DMAx SxCR Configuration --------------------------
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****      * Configure DMAx_Streamy:  peripheral burst transfer with parameters :
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****      * - PeriphBurst:             DMA_SxCR_PBURST[1:0] bits
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****      */
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****     LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
+ 603              		.loc 1 370 5 is_stmt 1 view .LVU169
+ 604 0050 936B     		ldr	r3, [r2, #56]
+ 605              	.LVL44:
+ 606              	.LBB52:
+ 607              	.LBI52:
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 608              		.loc 2 1144 22 view .LVU170
+ 609              	.LBB53:
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 610              		.loc 2 1146 3 view .LVU171
+ 611 0052 0C58     		ldr	r4, [r1, r0]
+ 612 0054 24F4C004 		bic	r4, r4, #6291456
+ 613 0058 2343     		orrs	r3, r3, r4
+ 614              	.LVL45:
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 615              		.loc 2 1146 3 is_stmt 0 view .LVU172
+ 616 005a 0B50     		str	r3, [r1, r0]
+ 617              	.LVL46:
+ 618              	.L46:
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 619              		.loc 2 1146 3 view .LVU173
+ 620              	.LBE53:
+ 621              	.LBE52:
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   }
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   /*-------------------------- DMAx SxM0AR Configuration --------------------------
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * Configure the memory or destination base address with parameter :
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * - MemoryOrM2MDstAddress:     DMA_SxM0AR_M0A[31:0] bits
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    */
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
+ 622              		.loc 1 377 3 is_stmt 1 view .LVU174
+ 623 005c 5368     		ldr	r3, [r2, #4]
+ 624              	.LVL47:
+ 625              	.LBB54:
+ 626              	.LBI54:
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ARM GAS  /tmp/ccmfsuWO.s 			page 54
+
+
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief Configure the Source and Destination addresses.
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA stream is enabled.
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n 
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         PAR         PA          LL_DMA_ConfigAddresses
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  SrcAddress Between 0 to 0xFFFFFFFF
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DstAddress Between 0 to 0xFFFFFFFF
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Direction This parameter can be one of the following values:
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   /* Direction Memory to Periph */
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR,
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   /* Direction Periph to Memory and Memory to Memory */
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   else
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   {
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR,
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****     WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   }
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Set the Memory address.
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA channel is enabled.
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+ARM GAS  /tmp/ccmfsuWO.s 			page 55
+
+
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd
+ 627              		.loc 2 1459 22 view .LVU175
+ 628              	.LBB55:
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, 
+ 629              		.loc 2 1461 3 view .LVU176
+ 630 005e CCF80C30 		str	r3, [ip, #12]
+ 631              	.LVL48:
+ 632              		.loc 2 1461 3 is_stmt 0 view .LVU177
+ 633              	.LBE55:
+ 634              	.LBE54:
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   /*-------------------------- DMAx SxPAR Configuration ---------------------------
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * Configure the peripheral or source base address with parameter :
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * - PeriphOrM2MSrcAddress:     DMA_SxPAR_PA[31:0] bits
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    */
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
+ 635              		.loc 1 383 3 is_stmt 1 view .LVU178
+ 636 0062 1368     		ldr	r3, [r2]
+ 637              	.LVL49:
+ 638              	.LBB56:
+ 639              	.LBI56:
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /**
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @brief  Set the Peripheral address.
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @note   This API must not be called when the DMA channel is enabled.
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  DMAx DMAx Instance
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  Stream This parameter can be one of the following values:
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_0
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_1
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_2
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_3
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_4
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_5
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_6
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   *         @arg @ref LL_DMA_STREAM_7
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @param  PeriphAddress Between 0 to 0xFFFFFFFF
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   * @retval None
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   */
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAdd
+ 640              		.loc 2 1482 22 view .LVU179
+ 641              	.LBB57:
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h ****   WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, P
+ 642              		.loc 2 1484 3 view .LVU180
+ 643 0064 CCF80830 		str	r3, [ip, #8]
+ 644              	.LVL50:
+ 645              		.loc 2 1484 3 is_stmt 0 view .LVU181
+ 646              	.LBE57:
+ 647              	.LBE56:
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   /*--------------------------- DMAx SxNDTR Configuration -------------------------
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * Configure the peripheral base address with parameter :
+ARM GAS  /tmp/ccmfsuWO.s 			page 56
+
+
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * - NbData:                    DMA_SxNDT[15:0] bits
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    */
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
+ 648              		.loc 1 389 3 is_stmt 1 view .LVU182
+ 649 0068 136A     		ldr	r3, [r2, #32]
+ 650              	.LVL51:
+ 651              	.LBB58:
+ 652              	.LBI58:
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 653              		.loc 2 971 22 view .LVU183
+ 654              	.LBB59:
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 655              		.loc 2 973 3 view .LVU184
+ 656 006a DCF80450 		ldr	r5, [ip, #4]
+ 657 006e 094C     		ldr	r4, .L48+8
+ 658 0070 2C40     		ands	r4, r4, r5
+ 659 0072 2343     		orrs	r3, r3, r4
+ 660              	.LVL52:
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 661              		.loc 2 973 3 is_stmt 0 view .LVU185
+ 662 0074 CCF80430 		str	r3, [ip, #4]
+ 663              	.LVL53:
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 664              		.loc 2 973 3 view .LVU186
+ 665              	.LBE59:
+ 666              	.LBE58:
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * Configure the peripheral base address with parameter :
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    * - PeriphRequest:             DMA_SxCR_CHSEL[3:0] bits
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****    */
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
+ 667              		.loc 1 395 3 is_stmt 1 view .LVU187
+ 668 0078 536A     		ldr	r3, [r2, #36]
+ 669              	.LVL54:
+ 670              	.LBB60:
+ 671              	.LBI60:
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** {
+ 672              		.loc 2 1032 22 view .LVU188
+ 673              	.LBB61:
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 674              		.loc 2 1034 3 view .LVU189
+ 675 007a 0A58     		ldr	r2, [r1, r0]
+ 676              	.LVL55:
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 677              		.loc 2 1034 3 is_stmt 0 view .LVU190
+ 678 007c 22F0F052 		bic	r2, r2, #503316480
+ 679 0080 1343     		orrs	r3, r3, r2
+ 680              	.LVL56:
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 681              		.loc 2 1034 3 view .LVU191
+ 682 0082 0B50     		str	r3, [r1, r0]
+ 683              	.LVL57:
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }
+ 684              		.loc 2 1034 3 view .LVU192
+ 685              	.LBE61:
+ 686              	.LBE60:
+ARM GAS  /tmp/ccmfsuWO.s 			page 57
+
+
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   return SUCCESS;
+ 687              		.loc 1 397 3 is_stmt 1 view .LVU193
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** }
+ 688              		.loc 1 398 1 is_stmt 0 view .LVU194
+ 689 0084 0020     		movs	r0, #0
+ 690              	.LVL58:
+ 691              		.loc 1 398 1 view .LVU195
+ 692 0086 30BC     		pop	{r4, r5}
+ 693              	.LCFI4:
+ 694              		.cfi_restore 5
+ 695              		.cfi_restore 4
+ 696              		.cfi_def_cfa_offset 0
+ 697 0088 7047     		bx	lr
+ 698              	.L49:
+ 699 008a 00BF     		.align	2
+ 700              	.L48:
+ 701 008c 00000000 		.word	.LANCHOR0
+ 702 0090 1F80FCFF 		.word	-229345
+ 703 0094 0000FFFF 		.word	-65536
+ 704              		.cfi_endproc
+ 705              	.LFE321:
+ 707              		.section	.text.LL_DMA_StructInit,"ax",%progbits
+ 708              		.align	1
+ 709              		.global	LL_DMA_StructInit
+ 710              		.syntax unified
+ 711              		.thumb
+ 712              		.thumb_func
+ 713              		.fpu fpv5-d16
+ 715              	LL_DMA_StructInit:
+ 716              	.LVL59:
+ 717              	.LFB322:
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** 
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /**
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   * @retval None
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   */
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** {
+ 718              		.loc 1 406 1 is_stmt 1 view -0
+ 719              		.cfi_startproc
+ 720              		@ args = 0, pretend = 0, frame = 0
+ 721              		@ frame_needed = 0, uses_anonymous_args = 0
+ 722              		@ link register save eliminated.
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   /* Set DMA_InitStruct fields to default values */
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
+ 723              		.loc 1 408 3 view .LVU197
+ 724              		.loc 1 408 42 is_stmt 0 view .LVU198
+ 725 0000 0023     		movs	r3, #0
+ 726 0002 0360     		str	r3, [r0]
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
+ 727              		.loc 1 409 3 is_stmt 1 view .LVU199
+ 728              		.loc 1 409 42 is_stmt 0 view .LVU200
+ 729 0004 4360     		str	r3, [r0, #4]
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+ 730              		.loc 1 410 3 is_stmt 1 view .LVU201
+ARM GAS  /tmp/ccmfsuWO.s 			page 58
+
+
+ 731              		.loc 1 410 42 is_stmt 0 view .LVU202
+ 732 0006 8360     		str	r3, [r0, #8]
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
+ 733              		.loc 1 411 3 is_stmt 1 view .LVU203
+ 734              		.loc 1 411 42 is_stmt 0 view .LVU204
+ 735 0008 C360     		str	r3, [r0, #12]
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
+ 736              		.loc 1 412 3 is_stmt 1 view .LVU205
+ 737              		.loc 1 412 42 is_stmt 0 view .LVU206
+ 738 000a 0361     		str	r3, [r0, #16]
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
+ 739              		.loc 1 413 3 is_stmt 1 view .LVU207
+ 740              		.loc 1 413 42 is_stmt 0 view .LVU208
+ 741 000c 4361     		str	r3, [r0, #20]
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+ 742              		.loc 1 414 3 is_stmt 1 view .LVU209
+ 743              		.loc 1 414 42 is_stmt 0 view .LVU210
+ 744 000e 8361     		str	r3, [r0, #24]
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+ 745              		.loc 1 415 3 is_stmt 1 view .LVU211
+ 746              		.loc 1 415 42 is_stmt 0 view .LVU212
+ 747 0010 C361     		str	r3, [r0, #28]
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->NbData                 = 0x00000000U;
+ 748              		.loc 1 416 3 is_stmt 1 view .LVU213
+ 749              		.loc 1 416 42 is_stmt 0 view .LVU214
+ 750 0012 0362     		str	r3, [r0, #32]
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->Channel                = LL_DMA_CHANNEL_0;
+ 751              		.loc 1 417 3 is_stmt 1 view .LVU215
+ 752              		.loc 1 417 42 is_stmt 0 view .LVU216
+ 753 0014 4362     		str	r3, [r0, #36]
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
+ 754              		.loc 1 418 3 is_stmt 1 view .LVU217
+ 755              		.loc 1 418 42 is_stmt 0 view .LVU218
+ 756 0016 8362     		str	r3, [r0, #40]
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->FIFOMode               = LL_DMA_FIFOMODE_DISABLE;
+ 757              		.loc 1 419 3 is_stmt 1 view .LVU219
+ 758              		.loc 1 419 42 is_stmt 0 view .LVU220
+ 759 0018 C362     		str	r3, [r0, #44]
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->FIFOThreshold          = LL_DMA_FIFOTHRESHOLD_1_4;
+ 760              		.loc 1 420 3 is_stmt 1 view .LVU221
+ 761              		.loc 1 420 42 is_stmt 0 view .LVU222
+ 762 001a 0363     		str	r3, [r0, #48]
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->MemBurst               = LL_DMA_MBURST_SINGLE;
+ 763              		.loc 1 421 3 is_stmt 1 view .LVU223
+ 764              		.loc 1 421 42 is_stmt 0 view .LVU224
+ 765 001c 4363     		str	r3, [r0, #52]
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c ****   DMA_InitStruct->PeriphBurst            = LL_DMA_PBURST_SINGLE;
+ 766              		.loc 1 422 3 is_stmt 1 view .LVU225
+ 767              		.loc 1 422 42 is_stmt 0 view .LVU226
+ 768 001e 8363     		str	r3, [r0, #56]
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** }
+ 769              		.loc 1 423 1 view .LVU227
+ 770 0020 7047     		bx	lr
+ 771              		.cfi_endproc
+ 772              	.LFE322:
+ 774              		.section	.rodata.STREAM_OFFSET_TAB,"a"
+ 775              		.align	2
+ARM GAS  /tmp/ccmfsuWO.s 			page 59
+
+
+ 776              		.set	.LANCHOR0,. + 0
+ 779              	STREAM_OFFSET_TAB:
+ 780 0000 10284058 		.ascii	"\020(@Xp\210\240\270"
+ 780      7088A0B8 
+ 781              		.text
+ 782              	.Letext0:
+ 783              		.file 4 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 784              		.file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 785              		.file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ARM GAS  /tmp/ccmfsuWO.s 			page 60
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_ll_dma.c
+     /tmp/ccmfsuWO.s:17     .text.LL_DMA_DeInit:0000000000000000 $t
+     /tmp/ccmfsuWO.s:25     .text.LL_DMA_DeInit:0000000000000000 LL_DMA_DeInit
+     /tmp/ccmfsuWO.s:454    .text.LL_DMA_DeInit:00000000000001bc $d
+     /tmp/ccmfsuWO.s:476    .text.LL_DMA_Init:0000000000000000 $t
+     /tmp/ccmfsuWO.s:483    .text.LL_DMA_Init:0000000000000000 LL_DMA_Init
+     /tmp/ccmfsuWO.s:701    .text.LL_DMA_Init:000000000000008c $d
+     /tmp/ccmfsuWO.s:708    .text.LL_DMA_StructInit:0000000000000000 $t
+     /tmp/ccmfsuWO.s:715    .text.LL_DMA_StructInit:0000000000000000 LL_DMA_StructInit
+     /tmp/ccmfsuWO.s:775    .rodata.STREAM_OFFSET_TAB:0000000000000000 $d
+     /tmp/ccmfsuWO.s:779    .rodata.STREAM_OFFSET_TAB:0000000000000000 STREAM_OFFSET_TAB
+
+NO UNDEFINED SYMBOLS
diff --git a/build/stm32f7xx_ll_dma.o b/build/stm32f7xx_ll_dma.o
new file mode 100644
index 0000000..e29d593
Binary files /dev/null and b/build/stm32f7xx_ll_dma.o differ
diff --git a/build/stm32f7xx_ll_exti.d b/build/stm32f7xx_ll_exti.d
new file mode 100644
index 0000000..f77c5f5
--- /dev/null
+++ b/build/stm32f7xx_ll_exti.d
@@ -0,0 +1,66 @@
+build/stm32f7xx_ll_exti.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_ll_exti.lst b/build/stm32f7xx_ll_exti.lst
new file mode 100644
index 0000000..ef7cfc1
--- /dev/null
+++ b/build/stm32f7xx_ll_exti.lst
@@ -0,0 +1,1505 @@
+ARM GAS  /tmp/ccGZVeUT.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_ll_exti.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.LL_EXTI_DeInit,"ax",%progbits
+  17              		.align	1
+  18              		.global	LL_EXTI_DeInit
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	LL_EXTI_DeInit:
+  26              	.LFB157:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @file    stm32f7xx_ll_exti.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @brief   EXTI LL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #if defined(USE_FULL_LL_DRIVER)
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Includes ------------------------------------------------------------------*/
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #include "stm32f7xx_ll_exti.h"
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #ifdef  USE_FULL_ASSERT
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #include "stm32_assert.h"
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #else
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #define assert_param(expr) ((void)0U)
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #endif
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** @addtogroup STM32F7xx_LL_Driver
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @{
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   */
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+ARM GAS  /tmp/ccGZVeUT.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #if defined (EXTI)
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** @defgroup EXTI_LL EXTI
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @{
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   */
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Private types -------------------------------------------------------------*/
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Private variables ---------------------------------------------------------*/
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Private constants ---------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Private macros ------------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** @addtogroup EXTI_LL_Private_Macros
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @{
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   */
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x0
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****                                                    || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****                                                    || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLIN
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /**
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @}
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   */
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Private function prototypes -----------------------------------------------*/
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Exported functions --------------------------------------------------------*/
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** @addtogroup EXTI_LL_Exported_Functions
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @{
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   */
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** @addtogroup EXTI_LL_EF_Init
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @{
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   */
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /**
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @brief  De-initialize the EXTI registers to their default reset values.
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @retval An ErrorStatus enumeration value:
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   *          - SUCCESS: EXTI registers are de-initialized
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   *          - ERROR: not applicable
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   */
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** uint32_t LL_EXTI_DeInit(void)
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** {
+  28              		.loc 1 80 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* Interrupt mask register set to default reset values */
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   LL_EXTI_WriteReg(IMR,   0x00000000U);
+  33              		.loc 1 82 3 view .LVU1
+ARM GAS  /tmp/ccGZVeUT.s 			page 3
+
+
+  34 0000 054B     		ldr	r3, .L2
+  35 0002 0020     		movs	r0, #0
+  36 0004 1860     		str	r0, [r3]
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* Event mask register set to default reset values */
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   LL_EXTI_WriteReg(EMR,   0x00000000U);
+  37              		.loc 1 84 3 view .LVU2
+  38 0006 5860     		str	r0, [r3, #4]
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* Rising Trigger selection register set to default reset values */
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   LL_EXTI_WriteReg(RTSR,  0x00000000U);
+  39              		.loc 1 86 3 view .LVU3
+  40 0008 9860     		str	r0, [r3, #8]
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* Falling Trigger selection register set to default reset values */
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   LL_EXTI_WriteReg(FTSR,  0x00000000U);
+  41              		.loc 1 88 3 view .LVU4
+  42 000a D860     		str	r0, [r3, #12]
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* Software interrupt event register set to default reset values */
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   LL_EXTI_WriteReg(SWIER, 0x00000000U);
+  43              		.loc 1 90 3 view .LVU5
+  44 000c 1861     		str	r0, [r3, #16]
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* Pending register set to default reset values */
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   LL_EXTI_WriteReg(PR,    0x01FFFFFFU);
+  45              		.loc 1 92 3 view .LVU6
+  46 000e 6FF07E42 		mvn	r2, #-33554432
+  47 0012 5A61     		str	r2, [r3, #20]
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   return SUCCESS;
+  48              		.loc 1 94 3 view .LVU7
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** }
+  49              		.loc 1 95 1 is_stmt 0 view .LVU8
+  50 0014 7047     		bx	lr
+  51              	.L3:
+  52 0016 00BF     		.align	2
+  53              	.L2:
+  54 0018 003C0140 		.word	1073822720
+  55              		.cfi_endproc
+  56              	.LFE157:
+  58              		.section	.text.LL_EXTI_Init,"ax",%progbits
+  59              		.align	1
+  60              		.global	LL_EXTI_Init
+  61              		.syntax unified
+  62              		.thumb
+  63              		.thumb_func
+  64              		.fpu fpv5-d16
+  66              	LL_EXTI_Init:
+  67              	.LVL0:
+  68              	.LFB158:
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /**
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @retval An ErrorStatus enumeration value:
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   *          - SUCCESS: EXTI registers are initialized
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   *          - ERROR: not applicable
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   */
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** {
+  69              		.loc 1 105 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccGZVeUT.s 			page 4
+
+
+  70              		.cfi_startproc
+  71              		@ args = 0, pretend = 0, frame = 0
+  72              		@ frame_needed = 0, uses_anonymous_args = 0
+  73              		@ link register save eliminated.
+  74              		.loc 1 105 1 is_stmt 0 view .LVU10
+  75 0000 10B4     		push	{r4}
+  76              	.LCFI0:
+  77              		.cfi_def_cfa_offset 4
+  78              		.cfi_offset 4, -4
+  79 0002 0346     		mov	r3, r0
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   ErrorStatus status = SUCCESS;
+  80              		.loc 1 106 3 is_stmt 1 view .LVU11
+  81              	.LVL1:
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* Check the parameters */
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+  82              		.loc 1 108 3 view .LVU12
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+  83              		.loc 1 109 3 view .LVU13
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+  84              		.loc 1 110 3 view .LVU14
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* ENABLE LineCommand */
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   if (EXTI_InitStruct->LineCommand != DISABLE)
+  85              		.loc 1 113 3 view .LVU15
+  86              		.loc 1 113 22 is_stmt 0 view .LVU16
+  87 0004 0079     		ldrb	r0, [r0, #4]	@ zero_extendqisi2
+  88              	.LVL2:
+  89              		.loc 1 113 6 view .LVU17
+  90 0006 0028     		cmp	r0, #0
+  91 0008 53D0     		beq	.L5
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   {
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****     assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+  92              		.loc 1 115 5 is_stmt 1 view .LVU18
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****     /* Configure EXTI Lines in range from 0 to 31 */
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****     if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+  93              		.loc 1 118 5 view .LVU19
+  94              		.loc 1 118 24 is_stmt 0 view .LVU20
+  95 000a 1A68     		ldr	r2, [r3]
+  96              		.loc 1 118 8 view .LVU21
+  97 000c 002A     		cmp	r2, #0
+  98 000e 5ED0     		beq	.L12
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****     {
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****       switch (EXTI_InitStruct->Mode)
+  99              		.loc 1 120 7 is_stmt 1 view .LVU22
+ 100              		.loc 1 120 30 is_stmt 0 view .LVU23
+ 101 0010 5879     		ldrb	r0, [r3, #5]	@ zero_extendqisi2
+ 102              		.loc 1 120 7 view .LVU24
+ 103 0012 0128     		cmp	r0, #1
+ 104 0014 18D0     		beq	.L7
+ 105 0016 0228     		cmp	r0, #2
+ 106 0018 21D0     		beq	.L8
+ 107 001a 58B1     		cbz	r0, .L16
+ 108 001c 0120     		movs	r0, #1
+ 109              	.L9:
+ 110              	.LVL3:
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****       {
+ARM GAS  /tmp/ccGZVeUT.s 			page 5
+
+
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****         case LL_EXTI_MODE_IT:
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           /* First Disable Event on provided Lines */
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           /* Then Enable IT on provided Lines */
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           break;
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****         case LL_EXTI_MODE_EVENT:
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           /* First Disable IT on provided Lines */
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           /* Then Enable Event on provided Lines */
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           break;
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****         case LL_EXTI_MODE_IT_EVENT:
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           /* Directly Enable IT & Event on provided Lines */
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           break;
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****         default:
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           status = ERROR;
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           break;
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****       }
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ 111              		.loc 1 143 7 is_stmt 1 view .LVU25
+ 112              		.loc 1 143 26 is_stmt 0 view .LVU26
+ 113 001e 9A79     		ldrb	r2, [r3, #6]	@ zero_extendqisi2
+ 114              		.loc 1 143 10 view .LVU27
+ 115 0020 002A     		cmp	r2, #0
+ 116 0022 51D0     		beq	.L6
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****       {
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****         switch (EXTI_InitStruct->Trigger)
+ 117              		.loc 1 145 9 is_stmt 1 view .LVU28
+ 118 0024 022A     		cmp	r2, #2
+ 119 0026 2FD0     		beq	.L10
+ 120 0028 032A     		cmp	r2, #3
+ 121 002a 38D0     		beq	.L11
+ 122 002c 012A     		cmp	r2, #1
+ 123 002e 20D0     		beq	.L17
+ 124 0030 0120     		movs	r0, #1
+ 125              	.LVL4:
+ 126              		.loc 1 145 9 is_stmt 0 view .LVU29
+ 127 0032 49E0     		b	.L6
+ 128              	.LVL5:
+ 129              	.L16:
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           /* Then Enable IT on provided Lines */
+ 130              		.loc 1 124 11 is_stmt 1 view .LVU30
+ 131              	.LBB30:
+ 132              	.LBI30:
+ 133              		.file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @file    stm32f7xx_ll_exti.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief   Header file of EXTI LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * Copyright (c) 2017 STMicroelectronics.
+ARM GAS  /tmp/ccGZVeUT.s 			page 6
+
+
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #ifndef __STM32F7xx_LL_EXTI_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define __STM32F7xx_LL_EXTI_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined (EXTI)
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL EXTI
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Private constants ---------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Private Macros ------------------------------------------------------------*/
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER)
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @}
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Exported types ------------------------------------------------------------*/
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER)
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** typedef struct
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines i
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE 
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****                                      This parameter can be set either to ENABLE or DISABLE */
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
+ARM GAS  /tmp/ccGZVeUT.s 			page 7
+
+
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****                                      This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****                                      This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } LL_EXTI_InitTypeDef;
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @}
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Exported constants --------------------------------------------------------*/
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_LINE LINE
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM16)
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM18)
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM20)
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM21)
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM22)
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM24)
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM25)
+ARM GAS  /tmp/ccGZVeUT.s 			page 8
+
+
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM26)
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM27)
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM28)
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM29)
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM30)
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM31)
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER)
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @}
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER)
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_MODE Mode
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @}
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @}
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ARM GAS  /tmp/ccGZVeUT.s 			page 9
+
+
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @}
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Exported macro ------------------------------------------------------------*/
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Write a value in EXTI register
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  __REG__ Register to be written
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  __VALUE__ Value to be written in the register
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval None
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Read a value in EXTI register
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  __REG__ Register to be read
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval Register value
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @}
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @}
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Exported functions --------------------------------------------------------*/
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****  * @{
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****  */
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_IT_Management IT_Management
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note The reset value for the direct or internal lines (see RM)
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       is set to 1 in order to enable the interrupt by default.
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       Bits are set automatically at Power on.
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  ExtiLine This parameter can be one of the following values:
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_0
+ARM GAS  /tmp/ccGZVeUT.s 			page 10
+
+
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_1
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_2
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_3
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_4
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_5
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_6
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_7
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_8
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_9
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_10
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_11
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_12
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_13
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_14
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_15
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_16
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_17
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_18
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_19
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_20
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_21
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_22
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_23
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_24(*)
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_ALL_0_31
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   (*): Available in some devices
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   Please check each device line mapping for EXTI Line availability
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval None
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   SET_BIT(EXTI->IMR, ExtiLine);
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note The reset value for the direct or internal lines (see RM)
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       is set to 1 in order to enable the interrupt by default.
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       Bits are set automatically at Power on.
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  ExtiLine This parameter can be one of the following values:
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_0
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_1
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_2
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_3
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_4
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_5
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_6
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_7
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_8
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_9
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_10
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_11
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_12
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_13
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_14
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_15
+ARM GAS  /tmp/ccGZVeUT.s 			page 11
+
+
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_16
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_17
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_18
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_19
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_20
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_21
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_22
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_23
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_24(*)
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_ALL_0_31
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   (*): Available in some devices
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   Please check each device line mapping for EXTI Line availability
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval None
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   CLEAR_BIT(EXTI->IMR, ExtiLine);
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note The reset value for the direct or internal lines (see RM)
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       is set to 1 in order to enable the interrupt by default.
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       Bits are set automatically at Power on.
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  ExtiLine This parameter can be one of the following values:
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_0
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_1
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_2
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_3
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_4
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_5
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_6
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_7
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_8
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_9
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_10
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_11
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_12
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_13
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_14
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_15
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_16
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_17
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_18
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_19
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_20
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_21
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_22
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_23
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_24(*)
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_ALL_0_31
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   (*): Available in some devices
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   Please check each device line mapping for EXTI Line availability
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval State of bit (1 or 0).
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ARM GAS  /tmp/ccGZVeUT.s 			page 12
+
+
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @}
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Event_Management Event_Management
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  ExtiLine This parameter can be one of the following values:
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_0
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_1
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_2
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_3
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_4
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_5
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_6
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_7
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_8
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_9
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_10
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_11
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_12
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_13
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_14
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_15
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_16
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_17
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_18
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_19
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_20
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_21
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_22
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_23
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_24(*)
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_ALL_0_31
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   (*): Available in some devices
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   Please check each device line mapping for EXTI Line availability
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval None
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   SET_BIT(EXTI->EMR, ExtiLine);
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
+ARM GAS  /tmp/ccGZVeUT.s 			page 13
+
+
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  ExtiLine This parameter can be one of the following values:
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_0
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_1
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_2
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_3
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_4
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_5
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_6
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_7
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_8
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_9
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_10
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_11
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_12
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_13
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_14
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_15
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_16
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_17
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_18
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_19
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_20
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_21
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_22
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_23
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_24(*)
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_ALL_0_31
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   (*): Available in some devices
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   Please check each device line mapping for EXTI Line availability
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval None
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+ 134              		.loc 2 441 22 view .LVU31
+ 135              	.LBB31:
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   CLEAR_BIT(EXTI->EMR, ExtiLine);
+ 136              		.loc 2 443 3 view .LVU32
+ 137 0034 2749     		ldr	r1, .L18
+ 138 0036 4C68     		ldr	r4, [r1, #4]
+ 139 0038 24EA0202 		bic	r2, r4, r2
+ 140              	.LVL6:
+ 141              		.loc 2 443 3 is_stmt 0 view .LVU33
+ 142 003c 4A60     		str	r2, [r1, #4]
+ 143              	.LVL7:
+ 144              		.loc 2 443 3 view .LVU34
+ 145              	.LBE31:
+ 146              	.LBE30:
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           break;
+ 147              		.loc 1 126 11 is_stmt 1 view .LVU35
+ 148 003e 1A68     		ldr	r2, [r3]
+ 149              	.LVL8:
+ 150              	.LBB32:
+ 151              	.LBI32:
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 152              		.loc 2 267 22 view .LVU36
+ 153              	.LBB33:
+ARM GAS  /tmp/ccGZVeUT.s 			page 14
+
+
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 154              		.loc 2 269 3 view .LVU37
+ 155 0040 0C68     		ldr	r4, [r1]
+ 156 0042 2243     		orrs	r2, r2, r4
+ 157              	.LVL9:
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 158              		.loc 2 269 3 is_stmt 0 view .LVU38
+ 159 0044 0A60     		str	r2, [r1]
+ 160              	.LVL10:
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 161              		.loc 2 270 1 view .LVU39
+ 162 0046 EAE7     		b	.L9
+ 163              	.L7:
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 164              		.loc 2 270 1 view .LVU40
+ 165              	.LBE33:
+ 166              	.LBE32:
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           /* Then Enable Event on provided Lines */
+ 167              		.loc 1 130 11 is_stmt 1 view .LVU41
+ 168              	.LVL11:
+ 169              	.LBB34:
+ 170              	.LBI34:
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 171              		.loc 2 309 22 view .LVU42
+ 172              	.LBB35:
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 173              		.loc 2 311 3 view .LVU43
+ 174 0048 2249     		ldr	r1, .L18
+ 175 004a 0868     		ldr	r0, [r1]
+ 176 004c 20EA0202 		bic	r2, r0, r2
+ 177              	.LVL12:
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 178              		.loc 2 311 3 is_stmt 0 view .LVU44
+ 179 0050 0A60     		str	r2, [r1]
+ 180              	.LVL13:
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 181              		.loc 2 311 3 view .LVU45
+ 182              	.LBE35:
+ 183              	.LBE34:
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           break;
+ 184              		.loc 1 132 11 is_stmt 1 view .LVU46
+ 185 0052 1A68     		ldr	r2, [r3]
+ 186              	.LVL14:
+ 187              	.LBB36:
+ 188              	.LBI36:
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 189              		.loc 2 400 22 view .LVU47
+ 190              	.LBB37:
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 191              		.loc 2 402 3 view .LVU48
+ 192 0054 4868     		ldr	r0, [r1, #4]
+ 193 0056 0243     		orrs	r2, r2, r0
+ 194              	.LVL15:
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 195              		.loc 2 402 3 is_stmt 0 view .LVU49
+ 196 0058 4A60     		str	r2, [r1, #4]
+ 197              	.LVL16:
+ARM GAS  /tmp/ccGZVeUT.s 			page 15
+
+
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 198              		.loc 2 402 3 view .LVU50
+ 199              	.LBE37:
+ 200              	.LBE36:
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* Check the parameters */
+ 201              		.loc 1 106 15 view .LVU51
+ 202 005a 0020     		movs	r0, #0
+ 203              	.LBB39:
+ 204              	.LBB38:
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 205              		.loc 2 404 1 view .LVU52
+ 206 005c DFE7     		b	.L9
+ 207              	.L8:
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 208              		.loc 2 404 1 view .LVU53
+ 209              	.LBE38:
+ 210              	.LBE39:
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ 211              		.loc 1 136 11 is_stmt 1 view .LVU54
+ 212              	.LVL17:
+ 213              	.LBB40:
+ 214              	.LBI40:
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 215              		.loc 2 267 22 view .LVU55
+ 216              	.LBB41:
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 217              		.loc 2 269 3 view .LVU56
+ 218 005e 1D49     		ldr	r1, .L18
+ 219 0060 0868     		ldr	r0, [r1]
+ 220 0062 0243     		orrs	r2, r2, r0
+ 221              	.LVL18:
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 222              		.loc 2 269 3 is_stmt 0 view .LVU57
+ 223 0064 0A60     		str	r2, [r1]
+ 224              	.LVL19:
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 225              		.loc 2 269 3 view .LVU58
+ 226              	.LBE41:
+ 227              	.LBE40:
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           break;
+ 228              		.loc 1 137 11 is_stmt 1 view .LVU59
+ 229 0066 1A68     		ldr	r2, [r3]
+ 230              	.LVL20:
+ 231              	.LBB42:
+ 232              	.LBI42:
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 233              		.loc 2 400 22 view .LVU60
+ 234              	.LBB43:
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 235              		.loc 2 402 3 view .LVU61
+ 236 0068 4868     		ldr	r0, [r1, #4]
+ 237 006a 0243     		orrs	r2, r2, r0
+ 238              	.LVL21:
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 239              		.loc 2 402 3 is_stmt 0 view .LVU62
+ 240 006c 4A60     		str	r2, [r1, #4]
+ 241              	.LVL22:
+ARM GAS  /tmp/ccGZVeUT.s 			page 16
+
+
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 242              		.loc 2 402 3 view .LVU63
+ 243              	.LBE43:
+ 244              	.LBE42:
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* Check the parameters */
+ 245              		.loc 1 106 15 view .LVU64
+ 246 006e 0020     		movs	r0, #0
+ 247              	.LBB45:
+ 248              	.LBB44:
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 249              		.loc 2 404 1 view .LVU65
+ 250 0070 D5E7     		b	.L9
+ 251              	.LVL23:
+ 252              	.L17:
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 253              		.loc 2 404 1 view .LVU66
+ 254              	.LBE44:
+ 255              	.LBE45:
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****         {
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           case LL_EXTI_TRIGGER_RISING:
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             /* First Disable Falling Trigger on provided Lines */
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ 256              		.loc 1 149 13 is_stmt 1 view .LVU67
+ 257 0072 1C68     		ldr	r4, [r3]
+ 258              	.LVL24:
+ 259              	.LBB46:
+ 260              	.LBI46:
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  ExtiLine This parameter can be one of the following values:
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_0
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_1
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_2
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_3
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_4
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_5
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_6
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_7
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_8
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_9
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_10
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_11
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_12
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_13
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_14
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_15
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_16
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_17
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_18
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_19
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_20
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_21
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_22
+ARM GAS  /tmp/ccGZVeUT.s 			page 17
+
+
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_23
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_24(*)
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_ALL_0_31
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   (*): Available in some devices
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   Please check each device line mapping for EXTI Line availability
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval State of bit (1 or 0).
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @}
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       generated on these lines. If a rising edge on a configurable interrupt
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       line occurs during a write operation in the EXTI_RTSR register, the
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       pending bit is not set.
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       Rising and falling edge triggers can be set for
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       the same interrupt line. In this case, both generate a trigger
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       condition.
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  ExtiLine This parameter can be a combination of the following values:
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_0
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_1
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_2
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_3
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_4
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_5
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_6
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_7
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_8
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_9
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_10
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_11
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_12
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_13
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_14
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_15
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_16
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_18
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_19
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_20
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_21
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_22
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   Please check each device line mapping for EXTI Line availability
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval None
+ARM GAS  /tmp/ccGZVeUT.s 			page 18
+
+
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   SET_BIT(EXTI->RTSR, ExtiLine);
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       generated on these lines. If a rising edge on a configurable interrupt
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       line occurs during a write operation in the EXTI_RTSR register, the
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       pending bit is not set.
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       Rising and falling edge triggers can be set for
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       the same interrupt line. In this case, both generate a trigger
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       condition.
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  ExtiLine This parameter can be a combination of the following values:
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_0
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_1
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_2
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_3
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_4
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_5
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_6
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_7
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_8
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_9
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_10
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_11
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_12
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_13
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_14
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_15
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_16
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_18
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_19
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_20
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_21
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_22
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   Please check each device line mapping for EXTI Line availability
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval None
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   CLEAR_BIT(EXTI->RTSR, ExtiLine);
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  ExtiLine This parameter can be a combination of the following values:
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_0
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_1
+ARM GAS  /tmp/ccGZVeUT.s 			page 19
+
+
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_2
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_3
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_4
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_5
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_6
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_7
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_8
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_9
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_10
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_11
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_12
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_13
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_14
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_15
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_16
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_18
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_19
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_20
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_21
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_22
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   Please check each device line mapping for EXTI Line availability
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval State of bit (1 or 0).
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @}
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @{
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       generated on these lines. If a falling edge on a configurable interrupt
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       line occurs during a write operation in the EXTI_FTSR register, the
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       pending bit is not set.
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       Rising and falling edge triggers can be set for
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       the same interrupt line. In this case, both generate a trigger
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       condition.
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  ExtiLine This parameter can be a combination of the following values:
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_0
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_1
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_2
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_3
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_4
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_5
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_6
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_7
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_8
+ARM GAS  /tmp/ccGZVeUT.s 			page 20
+
+
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_9
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_10
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_11
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_12
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_13
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_14
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_15
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_16
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_18
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_19
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_20
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_21
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_22
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   Please check each device line mapping for EXTI Line availability
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval None
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   SET_BIT(EXTI->FTSR, ExtiLine);
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /**
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       generated on these lines. If a Falling edge on a configurable interrupt
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       line occurs during a write operation in the EXTI_FTSR register, the
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       pending bit is not set.
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       Rising and falling edge triggers can be set for the same interrupt line.
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *       In this case, both generate a trigger condition.
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @param  ExtiLine This parameter can be a combination of the following values:
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_0
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_1
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_2
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_3
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_4
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_5
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_6
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_7
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_8
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_9
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_10
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_11
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_12
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_13
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_14
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_15
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_16
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_18
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_19
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_20
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_21
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   *         @arg @ref LL_EXTI_LINE_22
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @note   Please check each device line mapping for EXTI Line availability
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   * @retval None
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   */
+ARM GAS  /tmp/ccGZVeUT.s 			page 21
+
+
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+ 261              		.loc 2 702 22 view .LVU68
+ 262              	.LBB47:
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h ****   CLEAR_BIT(EXTI->FTSR, ExtiLine);
+ 263              		.loc 2 704 3 view .LVU69
+ 264 0074 174A     		ldr	r2, .L18
+ 265 0076 D168     		ldr	r1, [r2, #12]
+ 266 0078 21EA0401 		bic	r1, r1, r4
+ 267 007c D160     		str	r1, [r2, #12]
+ 268              	.LVL25:
+ 269              		.loc 2 704 3 is_stmt 0 view .LVU70
+ 270              	.LBE47:
+ 271              	.LBE46:
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             /* Then Enable Rising Trigger on provided Lines */
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ 272              		.loc 1 151 13 is_stmt 1 view .LVU71
+ 273 007e 1B68     		ldr	r3, [r3]
+ 274              	.LVL26:
+ 275              	.LBB48:
+ 276              	.LBI48:
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 277              		.loc 2 532 22 view .LVU72
+ 278              	.LBB49:
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 279              		.loc 2 534 3 view .LVU73
+ 280 0080 9168     		ldr	r1, [r2, #8]
+ 281 0082 0B43     		orrs	r3, r3, r1
+ 282              	.LVL27:
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 283              		.loc 2 534 3 is_stmt 0 view .LVU74
+ 284 0084 9360     		str	r3, [r2, #8]
+ 285              	.LVL28:
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 286              		.loc 2 536 1 view .LVU75
+ 287 0086 1FE0     		b	.L6
+ 288              	.LVL29:
+ 289              	.L10:
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 290              		.loc 2 536 1 view .LVU76
+ 291              	.LBE49:
+ 292              	.LBE48:
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             break;
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           case LL_EXTI_TRIGGER_FALLING:
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             /* First Disable Rising Trigger on provided Lines */
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ 293              		.loc 1 155 13 is_stmt 1 view .LVU77
+ 294 0088 1C68     		ldr	r4, [r3]
+ 295              	.LVL30:
+ 296              	.LBB50:
+ 297              	.LBI50:
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 298              		.loc 2 575 22 view .LVU78
+ 299              	.LBB51:
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 300              		.loc 2 577 3 view .LVU79
+ 301 008a 124A     		ldr	r2, .L18
+ARM GAS  /tmp/ccGZVeUT.s 			page 22
+
+
+ 302 008c 9168     		ldr	r1, [r2, #8]
+ 303 008e 21EA0401 		bic	r1, r1, r4
+ 304 0092 9160     		str	r1, [r2, #8]
+ 305              	.LVL31:
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 306              		.loc 2 577 3 is_stmt 0 view .LVU80
+ 307              	.LBE51:
+ 308              	.LBE50:
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             /* Then Enable Falling Trigger on provided Lines */
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ 309              		.loc 1 157 13 is_stmt 1 view .LVU81
+ 310 0094 1B68     		ldr	r3, [r3]
+ 311              	.LVL32:
+ 312              	.LBB52:
+ 313              	.LBI52:
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 314              		.loc 2 661 22 view .LVU82
+ 315              	.LBB53:
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 316              		.loc 2 663 3 view .LVU83
+ 317 0096 D168     		ldr	r1, [r2, #12]
+ 318 0098 0B43     		orrs	r3, r3, r1
+ 319              	.LVL33:
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 320              		.loc 2 663 3 is_stmt 0 view .LVU84
+ 321 009a D360     		str	r3, [r2, #12]
+ 322              	.LVL34:
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 323              		.loc 2 664 1 view .LVU85
+ 324 009c 14E0     		b	.L6
+ 325              	.LVL35:
+ 326              	.L11:
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 327              		.loc 2 664 1 view .LVU86
+ 328              	.LBE53:
+ 329              	.LBE52:
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             break;
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           case LL_EXTI_TRIGGER_RISING_FALLING:
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ 330              		.loc 1 160 13 is_stmt 1 view .LVU87
+ 331 009e 1968     		ldr	r1, [r3]
+ 332              	.LVL36:
+ 333              	.LBB54:
+ 334              	.LBI54:
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 335              		.loc 2 532 22 view .LVU88
+ 336              	.LBB55:
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 337              		.loc 2 534 3 view .LVU89
+ 338 00a0 0C4A     		ldr	r2, .L18
+ 339 00a2 9468     		ldr	r4, [r2, #8]
+ 340 00a4 2143     		orrs	r1, r1, r4
+ 341              	.LVL37:
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 342              		.loc 2 534 3 is_stmt 0 view .LVU90
+ 343 00a6 9160     		str	r1, [r2, #8]
+ 344              	.LVL38:
+ARM GAS  /tmp/ccGZVeUT.s 			page 23
+
+
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 345              		.loc 2 534 3 view .LVU91
+ 346              	.LBE55:
+ 347              	.LBE54:
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ 348              		.loc 1 161 13 is_stmt 1 view .LVU92
+ 349 00a8 1B68     		ldr	r3, [r3]
+ 350              	.LVL39:
+ 351              	.LBB56:
+ 352              	.LBI56:
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 353              		.loc 2 661 22 view .LVU93
+ 354              	.LBB57:
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 355              		.loc 2 663 3 view .LVU94
+ 356 00aa D168     		ldr	r1, [r2, #12]
+ 357 00ac 0B43     		orrs	r3, r3, r1
+ 358              	.LVL40:
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 359              		.loc 2 663 3 is_stmt 0 view .LVU95
+ 360 00ae D360     		str	r3, [r2, #12]
+ 361              	.LVL41:
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 362              		.loc 2 664 1 view .LVU96
+ 363 00b0 0AE0     		b	.L6
+ 364              	.LVL42:
+ 365              	.L5:
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** 
+ 366              		.loc 2 664 1 view .LVU97
+ 367              	.LBE57:
+ 368              	.LBE56:
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             break;
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****           default:
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             status = ERROR;
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****             break;
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****         }
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****       }
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****     }
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   }
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* DISABLE LineCommand */
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   else
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   {
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****     /* De-configure EXTI Lines in range from 0 to 31 */
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****     LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ 369              		.loc 1 174 5 is_stmt 1 view .LVU98
+ 370              	.LBB58:
+ 371              	.LBI58:
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 372              		.loc 2 309 22 view .LVU99
+ 373              	.LBB59:
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 374              		.loc 2 311 3 view .LVU100
+ 375 00b2 084A     		ldr	r2, .L18
+ 376 00b4 1168     		ldr	r1, [r2]
+ 377 00b6 1C68     		ldr	r4, [r3]
+ 378 00b8 21EA0401 		bic	r1, r1, r4
+ 379 00bc 1160     		str	r1, [r2]
+ARM GAS  /tmp/ccGZVeUT.s 			page 24
+
+
+ 380              	.LVL43:
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 381              		.loc 2 311 3 is_stmt 0 view .LVU101
+ 382              	.LBE59:
+ 383              	.LBE58:
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****     LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ 384              		.loc 1 175 5 is_stmt 1 view .LVU102
+ 385 00be 1968     		ldr	r1, [r3]
+ 386              	.LVL44:
+ 387              	.LBB60:
+ 388              	.LBI60:
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** {
+ 389              		.loc 2 441 22 view .LVU103
+ 390              	.LBB61:
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 391              		.loc 2 443 3 view .LVU104
+ 392 00c0 5368     		ldr	r3, [r2, #4]
+ 393              	.LVL45:
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 394              		.loc 2 443 3 is_stmt 0 view .LVU105
+ 395 00c2 23EA0103 		bic	r3, r3, r1
+ 396 00c6 5360     		str	r3, [r2, #4]
+ 397              	.LVL46:
+ 398              	.L6:
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** }
+ 399              		.loc 2 443 3 view .LVU106
+ 400              	.LBE61:
+ 401              	.LBE60:
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   }
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   return status;
+ 402              		.loc 1 177 3 is_stmt 1 view .LVU107
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** }
+ 403              		.loc 1 178 1 is_stmt 0 view .LVU108
+ 404 00c8 5DF8044B 		ldr	r4, [sp], #4
+ 405              	.LCFI1:
+ 406              		.cfi_remember_state
+ 407              		.cfi_restore 4
+ 408              		.cfi_def_cfa_offset 0
+ 409 00cc 7047     		bx	lr
+ 410              	.LVL47:
+ 411              	.L12:
+ 412              	.LCFI2:
+ 413              		.cfi_restore_state
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   /* Check the parameters */
+ 414              		.loc 1 106 15 view .LVU109
+ 415 00ce 0020     		movs	r0, #0
+ 416 00d0 FAE7     		b	.L6
+ 417              	.L19:
+ 418 00d2 00BF     		.align	2
+ 419              	.L18:
+ 420 00d4 003C0140 		.word	1073822720
+ 421              		.cfi_endproc
+ 422              	.LFE158:
+ 424              		.section	.text.LL_EXTI_StructInit,"ax",%progbits
+ 425              		.align	1
+ 426              		.global	LL_EXTI_StructInit
+ 427              		.syntax unified
+ARM GAS  /tmp/ccGZVeUT.s 			page 25
+
+
+ 428              		.thumb
+ 429              		.thumb_func
+ 430              		.fpu fpv5-d16
+ 432              	LL_EXTI_StructInit:
+ 433              	.LVL48:
+ 434              	.LFB159:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** 
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /**
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   * @retval None
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   */
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** {
+ 435              		.loc 1 186 1 is_stmt 1 view -0
+ 436              		.cfi_startproc
+ 437              		@ args = 0, pretend = 0, frame = 0
+ 438              		@ frame_needed = 0, uses_anonymous_args = 0
+ 439              		@ link register save eliminated.
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
+ 440              		.loc 1 187 3 view .LVU111
+ 441              		.loc 1 187 35 is_stmt 0 view .LVU112
+ 442 0000 0023     		movs	r3, #0
+ 443 0002 0360     		str	r3, [r0]
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   EXTI_InitStruct->LineCommand    = DISABLE;
+ 444              		.loc 1 188 3 is_stmt 1 view .LVU113
+ 445              		.loc 1 188 35 is_stmt 0 view .LVU114
+ 446 0004 0371     		strb	r3, [r0, #4]
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
+ 447              		.loc 1 189 3 is_stmt 1 view .LVU115
+ 448              		.loc 1 189 35 is_stmt 0 view .LVU116
+ 449 0006 4371     		strb	r3, [r0, #5]
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c ****   EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
+ 450              		.loc 1 190 3 is_stmt 1 view .LVU117
+ 451              		.loc 1 190 35 is_stmt 0 view .LVU118
+ 452 0008 0223     		movs	r3, #2
+ 453 000a 8371     		strb	r3, [r0, #6]
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** }
+ 454              		.loc 1 191 1 view .LVU119
+ 455 000c 7047     		bx	lr
+ 456              		.cfi_endproc
+ 457              	.LFE159:
+ 459              		.text
+ 460              	.Letext0:
+ 461              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 462              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 463              		.file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ARM GAS  /tmp/ccGZVeUT.s 			page 26
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_ll_exti.c
+     /tmp/ccGZVeUT.s:17     .text.LL_EXTI_DeInit:0000000000000000 $t
+     /tmp/ccGZVeUT.s:25     .text.LL_EXTI_DeInit:0000000000000000 LL_EXTI_DeInit
+     /tmp/ccGZVeUT.s:54     .text.LL_EXTI_DeInit:0000000000000018 $d
+     /tmp/ccGZVeUT.s:59     .text.LL_EXTI_Init:0000000000000000 $t
+     /tmp/ccGZVeUT.s:66     .text.LL_EXTI_Init:0000000000000000 LL_EXTI_Init
+     /tmp/ccGZVeUT.s:420    .text.LL_EXTI_Init:00000000000000d4 $d
+     /tmp/ccGZVeUT.s:425    .text.LL_EXTI_StructInit:0000000000000000 $t
+     /tmp/ccGZVeUT.s:432    .text.LL_EXTI_StructInit:0000000000000000 LL_EXTI_StructInit
+
+NO UNDEFINED SYMBOLS
diff --git a/build/stm32f7xx_ll_exti.o b/build/stm32f7xx_ll_exti.o
new file mode 100644
index 0000000..c92f506
Binary files /dev/null and b/build/stm32f7xx_ll_exti.o differ
diff --git a/build/stm32f7xx_ll_gpio.d b/build/stm32f7xx_ll_gpio.d
new file mode 100644
index 0000000..a07a144
--- /dev/null
+++ b/build/stm32f7xx_ll_gpio.d
@@ -0,0 +1,68 @@
+build/stm32f7xx_ll_gpio.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
diff --git a/build/stm32f7xx_ll_gpio.lst b/build/stm32f7xx_ll_gpio.lst
new file mode 100644
index 0000000..4159896
--- /dev/null
+++ b/build/stm32f7xx_ll_gpio.lst
@@ -0,0 +1,3896 @@
+ARM GAS  /tmp/ccM5oG95.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_ll_gpio.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.LL_GPIO_DeInit,"ax",%progbits
+  17              		.align	1
+  18              		.global	LL_GPIO_DeInit
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	LL_GPIO_DeInit:
+  26              	.LVL0:
+  27              	.LFB199:
+  28              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @file    stm32f7xx_ll_gpio.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @brief   GPIO LL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(USE_FULL_LL_DRIVER)
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Includes ------------------------------------------------------------------*/
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #include "stm32f7xx_ll_gpio.h"
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #include "stm32f7xx_ll_bus.h"
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #ifdef  USE_FULL_ASSERT
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #include "stm32_assert.h"
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #else
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define assert_param(expr) ((void)0U)
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** @addtogroup STM32F7xx_LL_Driver
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @{
+ARM GAS  /tmp/ccM5oG95.s 			page 2
+
+
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   */
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || 
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** @addtogroup GPIO_LL
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @{
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   */
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Private types -------------------------------------------------------------*/
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Private variables ---------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Private constants ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Private macros ------------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** @addtogroup GPIO_LL_Private_Macros
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @{
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   */
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GP
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_PULL_DOWN))
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_1  )   ||\
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_2  )   ||\
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_3  )   ||\
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_4  )   ||\
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_5  )   ||\
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_6  )   ||\
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_7  )   ||\
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_8  )   ||\
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_9  )   ||\
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_10 )   ||\
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_11 )   ||\
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_12 )   ||\
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_13 )   ||\
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_14 )   ||\
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****                                             ((__VALUE__) == LL_GPIO_AF_15 ))
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /**
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @}
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   */
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Private function prototypes -----------------------------------------------*/
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Exported functions --------------------------------------------------------*/
+ARM GAS  /tmp/ccM5oG95.s 			page 3
+
+
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** @addtogroup GPIO_LL_Exported_Functions
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @{
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   */
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** @addtogroup GPIO_LL_EF_Init
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @{
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   */
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /**
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @brief  De-initialize GPIO registers (Registers restored to their default values).
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @param  GPIOx GPIO Port
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @retval An ErrorStatus enumeration value:
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   *          - SUCCESS: GPIO registers are de-initialized
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   *          - ERROR:   Wrong GPIO Port
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   */
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** {
+  29              		.loc 1 104 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   ErrorStatus status = SUCCESS;
+  34              		.loc 1 105 3 view .LVU1
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   /* Check the parameters */
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  35              		.loc 1 108 3 view .LVU2
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   /* Force and Release reset on clock of GPIOx Port */
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   if (GPIOx == GPIOA)
+  36              		.loc 1 111 3 view .LVU3
+  37              		.loc 1 111 6 is_stmt 0 view .LVU4
+  38 0000 534B     		ldr	r3, .L25
+  39 0002 9842     		cmp	r0, r3
+  40 0004 1FD0     		beq	.L14
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   else if (GPIOx == GPIOB)
+  41              		.loc 1 116 8 is_stmt 1 view .LVU5
+  42              		.loc 1 116 11 is_stmt 0 view .LVU6
+  43 0006 534B     		ldr	r3, .L25+4
+  44 0008 9842     		cmp	r0, r3
+  45 000a 28D0     		beq	.L15
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   else if (GPIOx == GPIOC)
+  46              		.loc 1 121 8 is_stmt 1 view .LVU7
+  47              		.loc 1 121 11 is_stmt 0 view .LVU8
+  48 000c 524B     		ldr	r3, .L25+8
+  49 000e 9842     		cmp	r0, r3
+  50 0010 31D0     		beq	.L16
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ARM GAS  /tmp/ccM5oG95.s 			page 4
+
+
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOD)
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   else if (GPIOx == GPIOD)
+  51              		.loc 1 127 8 is_stmt 1 view .LVU9
+  52              		.loc 1 127 11 is_stmt 0 view .LVU10
+  53 0012 524B     		ldr	r3, .L25+12
+  54 0014 9842     		cmp	r0, r3
+  55 0016 3AD0     		beq	.L17
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOD */
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOE)
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   else if (GPIOx == GPIOE)
+  56              		.loc 1 134 8 is_stmt 1 view .LVU11
+  57              		.loc 1 134 11 is_stmt 0 view .LVU12
+  58 0018 514B     		ldr	r3, .L25+16
+  59 001a 9842     		cmp	r0, r3
+  60 001c 43D0     		beq	.L18
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOE */
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOF)
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   else if (GPIOx == GPIOF)
+  61              		.loc 1 141 8 is_stmt 1 view .LVU13
+  62              		.loc 1 141 11 is_stmt 0 view .LVU14
+  63 001e 514B     		ldr	r3, .L25+20
+  64 0020 9842     		cmp	r0, r3
+  65 0022 4CD0     		beq	.L19
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOF */
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOG)
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   else if (GPIOx == GPIOG)
+  66              		.loc 1 148 8 is_stmt 1 view .LVU15
+  67              		.loc 1 148 11 is_stmt 0 view .LVU16
+  68 0024 504B     		ldr	r3, .L25+24
+  69 0026 9842     		cmp	r0, r3
+  70 0028 55D0     		beq	.L20
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOG */
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOH)
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   else if (GPIOx == GPIOH)
+  71              		.loc 1 155 8 is_stmt 1 view .LVU17
+  72              		.loc 1 155 11 is_stmt 0 view .LVU18
+  73 002a 504B     		ldr	r3, .L25+28
+  74 002c 9842     		cmp	r0, r3
+ARM GAS  /tmp/ccM5oG95.s 			page 5
+
+
+  75 002e 5ED0     		beq	.L21
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOH */
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOI)
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   else if (GPIOx == GPIOI)
+  76              		.loc 1 162 8 is_stmt 1 view .LVU19
+  77              		.loc 1 162 11 is_stmt 0 view .LVU20
+  78 0030 4F4B     		ldr	r3, .L25+32
+  79 0032 9842     		cmp	r0, r3
+  80 0034 67D0     		beq	.L22
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOI);
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI);
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOI */
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOJ)
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   else if (GPIOx == GPIOJ)
+  81              		.loc 1 169 8 is_stmt 1 view .LVU21
+  82              		.loc 1 169 11 is_stmt 0 view .LVU22
+  83 0036 4F4B     		ldr	r3, .L25+36
+  84 0038 9842     		cmp	r0, r3
+  85 003a 70D0     		beq	.L23
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOJ */
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOK)
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   else if (GPIOx == GPIOK)
+  86              		.loc 1 176 8 is_stmt 1 view .LVU23
+  87              		.loc 1 176 11 is_stmt 0 view .LVU24
+  88 003c 4E4B     		ldr	r3, .L25+40
+  89 003e 9842     		cmp	r0, r3
+  90 0040 79D0     		beq	.L24
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOK);
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK);
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOK */
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   else
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     status = ERROR;
+  91              		.loc 1 184 12 view .LVU25
+  92 0042 0120     		movs	r0, #1
+  93              	.LVL1:
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   return (status);
+  94              		.loc 1 187 3 is_stmt 1 view .LVU26
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** }
+  95              		.loc 1 188 1 is_stmt 0 view .LVU27
+  96 0044 7047     		bx	lr
+  97              	.LVL2:
+  98              	.L14:
+ARM GAS  /tmp/ccM5oG95.s 			page 6
+
+
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
+  99              		.loc 1 113 5 is_stmt 1 view .LVU28
+ 100              	.LBB76:
+ 101              	.LBI76:
+ 102              		.file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @file    stm32f7xx_ll_bus.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief   Header file of BUS LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @verbatim
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****                       ##### RCC Limitations #####
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ==============================================================================
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       A delay between an RCC peripheral clock enable and the effective peripheral 
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       enabling should be taken into account in order to manage the peripheral read/write 
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       from/to registers.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (+) This delay depends on the peripheral mapping.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****         (++) AHB & APB peripherals, 1 dummy read is necessary
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       Workarounds:
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @endverbatim
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @attention
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * Copyright (c) 2017 STMicroelectronics.
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * All rights reserved.
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * This software is licensed under terms that can be found in the LICENSE file in
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * the root directory of this software component.
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" {
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h"
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC)
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS
+ARM GAS  /tmp/ccM5oG95.s 			page 7
+
+
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ)
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK)
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM         RCC_AHB1ENR_DTCMRAMEN
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D)
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH)
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI             RCC_AHB1LPENR_AXILPEN
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+ARM GAS  /tmp/ccM5oG95.s 			page 8
+
+
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI)
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG)
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG           RCC_AHB2ENR_JPEGEN
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) 
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES)
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH)
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX)
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
+ARM GAS  /tmp/ccM5oG95.s 			page 9
+
+
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4)
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4           RCC_APB1ENR_I2C4EN
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2)
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3)
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC)
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN)
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCEN
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1       RCC_APB2ENR_SDMMC1EN
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2)
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2       RCC_APB2ENR_SDMMC2EN
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6)
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC)
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN
+ARM GAS  /tmp/ccM5oG95.s 			page 10
+
+
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI)
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0)
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS)
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO         RCC_APB2ENR_MDIOEN
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC)
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC      RCC_APB2ENR_OTGPHYCEN
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB1 peripherals clock.
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\n
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\n
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\n
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\n
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\n
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\n
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\n
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\n
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\n
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\n
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\n
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\n
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\n
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\n
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\n
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\n
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\n
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\n
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\n
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\n
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock
+ARM GAS  /tmp/ccM5oG95.s 			page 11
+
+
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1ENR, Periphs);
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB1 peripheral clock is enabled or not
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\n
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\n
+ARM GAS  /tmp/ccM5oG95.s 			page 12
+
+
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\n
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_IsEnabledClock
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB1 peripherals clock.
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\n
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\n
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\n
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\n
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\n
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\n
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\n
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\n
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\n
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\n
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\n
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\n
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\n
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\n
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\n
+ARM GAS  /tmp/ccM5oG95.s 			page 13
+
+
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\n
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\n
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\n
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\n
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\n
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_DisableClock
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1ENR, Periphs);
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB1 peripherals reset.
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\n
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\n
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\n
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\n
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\n
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\n
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\n
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\n
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\n
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\n
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\n
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\n
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\n
+ARM GAS  /tmp/ccM5oG95.s 			page 14
+
+
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+ 103              		.loc 2 476 22 view .LVU29
+ 104              	.LBB77:
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1RSTR, Periphs);
+ 105              		.loc 2 478 3 view .LVU30
+ 106 0046 03F56053 		add	r3, r3, #14336
+ 107 004a 1A69     		ldr	r2, [r3, #16]
+ 108 004c 42F00102 		orr	r2, r2, #1
+ 109 0050 1A61     		str	r2, [r3, #16]
+ 110              	.LVL3:
+ 111              		.loc 2 478 3 is_stmt 0 view .LVU31
+ 112              	.LBE77:
+ 113              	.LBE76:
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 114              		.loc 1 114 5 is_stmt 1 view .LVU32
+ 115              	.LBB78:
+ 116              	.LBI78:
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB1 peripherals reset.
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\n
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\n
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\n
+ARM GAS  /tmp/ccM5oG95.s 			page 15
+
+
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\n
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\n
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+ 117              		.loc 2 523 22 view .LVU33
+ 118              	.LBB79:
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+ 119              		.loc 2 525 3 view .LVU34
+ 120 0052 1A69     		ldr	r2, [r3, #16]
+ 121 0054 22F00102 		bic	r2, r2, #1
+ 122 0058 1A61     		str	r2, [r3, #16]
+ 123              	.LBE79:
+ 124              	.LBE78:
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 125              		.loc 1 105 15 is_stmt 0 view .LVU35
+ 126 005a 0020     		movs	r0, #0
+ 127              	.LVL4:
+ 128              	.LBB81:
+ 129              	.LBB80:
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 130              		.loc 2 526 1 view .LVU36
+ 131 005c 7047     		bx	lr
+ 132              	.LVL5:
+ 133              	.L15:
+ 134              		.loc 2 526 1 view .LVU37
+ 135              	.LBE80:
+ 136              	.LBE81:
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
+ 137              		.loc 1 118 5 is_stmt 1 view .LVU38
+ 138              	.LBB82:
+ARM GAS  /tmp/ccM5oG95.s 			page 16
+
+
+ 139              	.LBI82:
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 140              		.loc 2 476 22 view .LVU39
+ 141              	.LBB83:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 142              		.loc 2 478 3 view .LVU40
+ 143 005e 03F55053 		add	r3, r3, #13312
+ 144 0062 1A69     		ldr	r2, [r3, #16]
+ 145 0064 42F00202 		orr	r2, r2, #2
+ 146 0068 1A61     		str	r2, [r3, #16]
+ 147              	.LVL6:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 148              		.loc 2 478 3 is_stmt 0 view .LVU41
+ 149              	.LBE83:
+ 150              	.LBE82:
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 151              		.loc 1 119 5 is_stmt 1 view .LVU42
+ 152              	.LBB84:
+ 153              	.LBI84:
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 154              		.loc 2 523 22 view .LVU43
+ 155              	.LBB85:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 156              		.loc 2 525 3 view .LVU44
+ 157 006a 1A69     		ldr	r2, [r3, #16]
+ 158 006c 22F00202 		bic	r2, r2, #2
+ 159 0070 1A61     		str	r2, [r3, #16]
+ 160              	.LBE85:
+ 161              	.LBE84:
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 162              		.loc 1 105 15 is_stmt 0 view .LVU45
+ 163 0072 0020     		movs	r0, #0
+ 164              	.LVL7:
+ 165              	.LBB87:
+ 166              	.LBB86:
+ 167              		.loc 2 526 1 view .LVU46
+ 168 0074 7047     		bx	lr
+ 169              	.LVL8:
+ 170              	.L16:
+ 171              		.loc 2 526 1 view .LVU47
+ 172              	.LBE86:
+ 173              	.LBE87:
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
+ 174              		.loc 1 123 5 is_stmt 1 view .LVU48
+ 175              	.LBB88:
+ 176              	.LBI88:
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 177              		.loc 2 476 22 view .LVU49
+ 178              	.LBB89:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 179              		.loc 2 478 3 view .LVU50
+ 180 0076 03F54053 		add	r3, r3, #12288
+ 181 007a 1A69     		ldr	r2, [r3, #16]
+ 182 007c 42F00402 		orr	r2, r2, #4
+ 183 0080 1A61     		str	r2, [r3, #16]
+ 184              	.LVL9:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ARM GAS  /tmp/ccM5oG95.s 			page 17
+
+
+ 185              		.loc 2 478 3 is_stmt 0 view .LVU51
+ 186              	.LBE89:
+ 187              	.LBE88:
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 188              		.loc 1 124 5 is_stmt 1 view .LVU52
+ 189              	.LBB90:
+ 190              	.LBI90:
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 191              		.loc 2 523 22 view .LVU53
+ 192              	.LBB91:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 193              		.loc 2 525 3 view .LVU54
+ 194 0082 1A69     		ldr	r2, [r3, #16]
+ 195 0084 22F00402 		bic	r2, r2, #4
+ 196 0088 1A61     		str	r2, [r3, #16]
+ 197              	.LBE91:
+ 198              	.LBE90:
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 199              		.loc 1 105 15 is_stmt 0 view .LVU55
+ 200 008a 0020     		movs	r0, #0
+ 201              	.LVL10:
+ 202              	.LBB93:
+ 203              	.LBB92:
+ 204              		.loc 2 526 1 view .LVU56
+ 205 008c 7047     		bx	lr
+ 206              	.LVL11:
+ 207              	.L17:
+ 208              		.loc 2 526 1 view .LVU57
+ 209              	.LBE92:
+ 210              	.LBE93:
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
+ 211              		.loc 1 129 5 is_stmt 1 view .LVU58
+ 212              	.LBB94:
+ 213              	.LBI94:
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 214              		.loc 2 476 22 view .LVU59
+ 215              	.LBB95:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 216              		.loc 2 478 3 view .LVU60
+ 217 008e 03F53053 		add	r3, r3, #11264
+ 218 0092 1A69     		ldr	r2, [r3, #16]
+ 219 0094 42F00802 		orr	r2, r2, #8
+ 220 0098 1A61     		str	r2, [r3, #16]
+ 221              	.LVL12:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 222              		.loc 2 478 3 is_stmt 0 view .LVU61
+ 223              	.LBE95:
+ 224              	.LBE94:
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 225              		.loc 1 130 5 is_stmt 1 view .LVU62
+ 226              	.LBB96:
+ 227              	.LBI96:
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 228              		.loc 2 523 22 view .LVU63
+ 229              	.LBB97:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 230              		.loc 2 525 3 view .LVU64
+ARM GAS  /tmp/ccM5oG95.s 			page 18
+
+
+ 231 009a 1A69     		ldr	r2, [r3, #16]
+ 232 009c 22F00802 		bic	r2, r2, #8
+ 233 00a0 1A61     		str	r2, [r3, #16]
+ 234              	.LBE97:
+ 235              	.LBE96:
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 236              		.loc 1 105 15 is_stmt 0 view .LVU65
+ 237 00a2 0020     		movs	r0, #0
+ 238              	.LVL13:
+ 239              	.LBB99:
+ 240              	.LBB98:
+ 241              		.loc 2 526 1 view .LVU66
+ 242 00a4 7047     		bx	lr
+ 243              	.LVL14:
+ 244              	.L18:
+ 245              		.loc 2 526 1 view .LVU67
+ 246              	.LBE98:
+ 247              	.LBE99:
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
+ 248              		.loc 1 136 5 is_stmt 1 view .LVU68
+ 249              	.LBB100:
+ 250              	.LBI100:
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 251              		.loc 2 476 22 view .LVU69
+ 252              	.LBB101:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 253              		.loc 2 478 3 view .LVU70
+ 254 00a6 03F52053 		add	r3, r3, #10240
+ 255 00aa 1A69     		ldr	r2, [r3, #16]
+ 256 00ac 42F01002 		orr	r2, r2, #16
+ 257 00b0 1A61     		str	r2, [r3, #16]
+ 258              	.LVL15:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 259              		.loc 2 478 3 is_stmt 0 view .LVU71
+ 260              	.LBE101:
+ 261              	.LBE100:
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 262              		.loc 1 137 5 is_stmt 1 view .LVU72
+ 263              	.LBB102:
+ 264              	.LBI102:
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 265              		.loc 2 523 22 view .LVU73
+ 266              	.LBB103:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 267              		.loc 2 525 3 view .LVU74
+ 268 00b2 1A69     		ldr	r2, [r3, #16]
+ 269 00b4 22F01002 		bic	r2, r2, #16
+ 270 00b8 1A61     		str	r2, [r3, #16]
+ 271              	.LBE103:
+ 272              	.LBE102:
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 273              		.loc 1 105 15 is_stmt 0 view .LVU75
+ 274 00ba 0020     		movs	r0, #0
+ 275              	.LVL16:
+ 276              	.LBB105:
+ 277              	.LBB104:
+ 278              		.loc 2 526 1 view .LVU76
+ARM GAS  /tmp/ccM5oG95.s 			page 19
+
+
+ 279 00bc 7047     		bx	lr
+ 280              	.LVL17:
+ 281              	.L19:
+ 282              		.loc 2 526 1 view .LVU77
+ 283              	.LBE104:
+ 284              	.LBE105:
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
+ 285              		.loc 1 143 5 is_stmt 1 view .LVU78
+ 286              	.LBB106:
+ 287              	.LBI106:
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 288              		.loc 2 476 22 view .LVU79
+ 289              	.LBB107:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 290              		.loc 2 478 3 view .LVU80
+ 291 00be 03F51053 		add	r3, r3, #9216
+ 292 00c2 1A69     		ldr	r2, [r3, #16]
+ 293 00c4 42F02002 		orr	r2, r2, #32
+ 294 00c8 1A61     		str	r2, [r3, #16]
+ 295              	.LVL18:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 296              		.loc 2 478 3 is_stmt 0 view .LVU81
+ 297              	.LBE107:
+ 298              	.LBE106:
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 299              		.loc 1 144 5 is_stmt 1 view .LVU82
+ 300              	.LBB108:
+ 301              	.LBI108:
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 302              		.loc 2 523 22 view .LVU83
+ 303              	.LBB109:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 304              		.loc 2 525 3 view .LVU84
+ 305 00ca 1A69     		ldr	r2, [r3, #16]
+ 306 00cc 22F02002 		bic	r2, r2, #32
+ 307 00d0 1A61     		str	r2, [r3, #16]
+ 308              	.LBE109:
+ 309              	.LBE108:
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 310              		.loc 1 105 15 is_stmt 0 view .LVU85
+ 311 00d2 0020     		movs	r0, #0
+ 312              	.LVL19:
+ 313              	.LBB111:
+ 314              	.LBB110:
+ 315              		.loc 2 526 1 view .LVU86
+ 316 00d4 7047     		bx	lr
+ 317              	.LVL20:
+ 318              	.L20:
+ 319              		.loc 2 526 1 view .LVU87
+ 320              	.LBE110:
+ 321              	.LBE111:
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
+ 322              		.loc 1 150 5 is_stmt 1 view .LVU88
+ 323              	.LBB112:
+ 324              	.LBI112:
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 325              		.loc 2 476 22 view .LVU89
+ARM GAS  /tmp/ccM5oG95.s 			page 20
+
+
+ 326              	.LBB113:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 327              		.loc 2 478 3 view .LVU90
+ 328 00d6 03F50053 		add	r3, r3, #8192
+ 329 00da 1A69     		ldr	r2, [r3, #16]
+ 330 00dc 42F04002 		orr	r2, r2, #64
+ 331 00e0 1A61     		str	r2, [r3, #16]
+ 332              	.LVL21:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 333              		.loc 2 478 3 is_stmt 0 view .LVU91
+ 334              	.LBE113:
+ 335              	.LBE112:
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 336              		.loc 1 151 5 is_stmt 1 view .LVU92
+ 337              	.LBB114:
+ 338              	.LBI114:
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 339              		.loc 2 523 22 view .LVU93
+ 340              	.LBB115:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 341              		.loc 2 525 3 view .LVU94
+ 342 00e2 1A69     		ldr	r2, [r3, #16]
+ 343 00e4 22F04002 		bic	r2, r2, #64
+ 344 00e8 1A61     		str	r2, [r3, #16]
+ 345              	.LBE115:
+ 346              	.LBE114:
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 347              		.loc 1 105 15 is_stmt 0 view .LVU95
+ 348 00ea 0020     		movs	r0, #0
+ 349              	.LVL22:
+ 350              	.LBB117:
+ 351              	.LBB116:
+ 352              		.loc 2 526 1 view .LVU96
+ 353 00ec 7047     		bx	lr
+ 354              	.LVL23:
+ 355              	.L21:
+ 356              		.loc 2 526 1 view .LVU97
+ 357              	.LBE116:
+ 358              	.LBE117:
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
+ 359              		.loc 1 157 5 is_stmt 1 view .LVU98
+ 360              	.LBB118:
+ 361              	.LBI118:
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 362              		.loc 2 476 22 view .LVU99
+ 363              	.LBB119:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 364              		.loc 2 478 3 view .LVU100
+ 365 00ee 03F5E053 		add	r3, r3, #7168
+ 366 00f2 1A69     		ldr	r2, [r3, #16]
+ 367 00f4 42F08002 		orr	r2, r2, #128
+ 368 00f8 1A61     		str	r2, [r3, #16]
+ 369              	.LVL24:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 370              		.loc 2 478 3 is_stmt 0 view .LVU101
+ 371              	.LBE119:
+ 372              	.LBE118:
+ARM GAS  /tmp/ccM5oG95.s 			page 21
+
+
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 373              		.loc 1 158 5 is_stmt 1 view .LVU102
+ 374              	.LBB120:
+ 375              	.LBI120:
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 376              		.loc 2 523 22 view .LVU103
+ 377              	.LBB121:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 378              		.loc 2 525 3 view .LVU104
+ 379 00fa 1A69     		ldr	r2, [r3, #16]
+ 380 00fc 22F08002 		bic	r2, r2, #128
+ 381 0100 1A61     		str	r2, [r3, #16]
+ 382              	.LBE121:
+ 383              	.LBE120:
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 384              		.loc 1 105 15 is_stmt 0 view .LVU105
+ 385 0102 0020     		movs	r0, #0
+ 386              	.LVL25:
+ 387              	.LBB123:
+ 388              	.LBB122:
+ 389              		.loc 2 526 1 view .LVU106
+ 390 0104 7047     		bx	lr
+ 391              	.LVL26:
+ 392              	.L22:
+ 393              		.loc 2 526 1 view .LVU107
+ 394              	.LBE122:
+ 395              	.LBE123:
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI);
+ 396              		.loc 1 164 5 is_stmt 1 view .LVU108
+ 397              	.LBB124:
+ 398              	.LBI124:
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 399              		.loc 2 476 22 view .LVU109
+ 400              	.LBB125:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 401              		.loc 2 478 3 view .LVU110
+ 402 0106 03F5C053 		add	r3, r3, #6144
+ 403 010a 1A69     		ldr	r2, [r3, #16]
+ 404 010c 42F48072 		orr	r2, r2, #256
+ 405 0110 1A61     		str	r2, [r3, #16]
+ 406              	.LVL27:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 407              		.loc 2 478 3 is_stmt 0 view .LVU111
+ 408              	.LBE125:
+ 409              	.LBE124:
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 410              		.loc 1 165 5 is_stmt 1 view .LVU112
+ 411              	.LBB126:
+ 412              	.LBI126:
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 413              		.loc 2 523 22 view .LVU113
+ 414              	.LBB127:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 415              		.loc 2 525 3 view .LVU114
+ 416 0112 1A69     		ldr	r2, [r3, #16]
+ 417 0114 22F48072 		bic	r2, r2, #256
+ 418 0118 1A61     		str	r2, [r3, #16]
+ARM GAS  /tmp/ccM5oG95.s 			page 22
+
+
+ 419              	.LBE127:
+ 420              	.LBE126:
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 421              		.loc 1 105 15 is_stmt 0 view .LVU115
+ 422 011a 0020     		movs	r0, #0
+ 423              	.LVL28:
+ 424              	.LBB129:
+ 425              	.LBB128:
+ 426              		.loc 2 526 1 view .LVU116
+ 427 011c 7047     		bx	lr
+ 428              	.LVL29:
+ 429              	.L23:
+ 430              		.loc 2 526 1 view .LVU117
+ 431              	.LBE128:
+ 432              	.LBE129:
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
+ 433              		.loc 1 171 5 is_stmt 1 view .LVU118
+ 434              	.LBB130:
+ 435              	.LBI130:
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 436              		.loc 2 476 22 view .LVU119
+ 437              	.LBB131:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 438              		.loc 2 478 3 view .LVU120
+ 439 011e 03F5A053 		add	r3, r3, #5120
+ 440 0122 1A69     		ldr	r2, [r3, #16]
+ 441 0124 42F40072 		orr	r2, r2, #512
+ 442 0128 1A61     		str	r2, [r3, #16]
+ 443              	.LVL30:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 444              		.loc 2 478 3 is_stmt 0 view .LVU121
+ 445              	.LBE131:
+ 446              	.LBE130:
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 447              		.loc 1 172 5 is_stmt 1 view .LVU122
+ 448              	.LBB132:
+ 449              	.LBI132:
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 450              		.loc 2 523 22 view .LVU123
+ 451              	.LBB133:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 452              		.loc 2 525 3 view .LVU124
+ 453 012a 1A69     		ldr	r2, [r3, #16]
+ 454 012c 22F40072 		bic	r2, r2, #512
+ 455 0130 1A61     		str	r2, [r3, #16]
+ 456              	.LBE133:
+ 457              	.LBE132:
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 458              		.loc 1 105 15 is_stmt 0 view .LVU125
+ 459 0132 0020     		movs	r0, #0
+ 460              	.LVL31:
+ 461              	.LBB135:
+ 462              	.LBB134:
+ 463              		.loc 2 526 1 view .LVU126
+ 464 0134 7047     		bx	lr
+ 465              	.LVL32:
+ 466              	.L24:
+ARM GAS  /tmp/ccM5oG95.s 			page 23
+
+
+ 467              		.loc 2 526 1 view .LVU127
+ 468              	.LBE134:
+ 469              	.LBE135:
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK);
+ 470              		.loc 1 178 5 is_stmt 1 view .LVU128
+ 471              	.LBB136:
+ 472              	.LBI136:
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 473              		.loc 2 476 22 view .LVU129
+ 474              	.LBB137:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 475              		.loc 2 478 3 view .LVU130
+ 476 0136 03F58053 		add	r3, r3, #4096
+ 477 013a 1A69     		ldr	r2, [r3, #16]
+ 478 013c 42F48062 		orr	r2, r2, #1024
+ 479 0140 1A61     		str	r2, [r3, #16]
+ 480              	.LVL33:
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 481              		.loc 2 478 3 is_stmt 0 view .LVU131
+ 482              	.LBE137:
+ 483              	.LBE136:
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 484              		.loc 1 179 5 is_stmt 1 view .LVU132
+ 485              	.LBB138:
+ 486              	.LBI138:
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 487              		.loc 2 523 22 view .LVU133
+ 488              	.LBB139:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 489              		.loc 2 525 3 view .LVU134
+ 490 0142 1A69     		ldr	r2, [r3, #16]
+ 491 0144 22F48062 		bic	r2, r2, #1024
+ 492 0148 1A61     		str	r2, [r3, #16]
+ 493              	.LBE139:
+ 494              	.LBE138:
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 495              		.loc 1 105 15 is_stmt 0 view .LVU135
+ 496 014a 0020     		movs	r0, #0
+ 497              	.LVL34:
+ 498              	.LBB141:
+ 499              	.LBB140:
+ 500              		.loc 2 526 1 view .LVU136
+ 501 014c 7047     		bx	lr
+ 502              	.L26:
+ 503 014e 00BF     		.align	2
+ 504              	.L25:
+ 505 0150 00000240 		.word	1073872896
+ 506 0154 00040240 		.word	1073873920
+ 507 0158 00080240 		.word	1073874944
+ 508 015c 000C0240 		.word	1073875968
+ 509 0160 00100240 		.word	1073876992
+ 510 0164 00140240 		.word	1073878016
+ 511 0168 00180240 		.word	1073879040
+ 512 016c 001C0240 		.word	1073880064
+ 513 0170 00200240 		.word	1073881088
+ 514 0174 00240240 		.word	1073882112
+ 515 0178 00280240 		.word	1073883136
+ARM GAS  /tmp/ccM5oG95.s 			page 24
+
+
+ 516              	.LBE140:
+ 517              	.LBE141:
+ 518              		.cfi_endproc
+ 519              	.LFE199:
+ 521              		.section	.text.LL_GPIO_Init,"ax",%progbits
+ 522              		.align	1
+ 523              		.global	LL_GPIO_Init
+ 524              		.syntax unified
+ 525              		.thumb
+ 526              		.thumb_func
+ 527              		.fpu fpv5-d16
+ 529              	LL_GPIO_Init:
+ 530              	.LVL35:
+ 531              	.LFB200:
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /**
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @param  GPIOx GPIO Port
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @param  GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   *         that contains the configuration information for the specified GPIO peripheral.
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @retval An ErrorStatus enumeration value:
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   *          - ERROR:   Not applicable
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   */
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** {
+ 532              		.loc 1 200 1 is_stmt 1 view -0
+ 533              		.cfi_startproc
+ 534              		@ args = 0, pretend = 0, frame = 0
+ 535              		@ frame_needed = 0, uses_anonymous_args = 0
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   uint32_t pinpos     = 0x00000000U;
+ 536              		.loc 1 201 3 view .LVU138
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   uint32_t currentpin = 0x00000000U;
+ 537              		.loc 1 202 3 view .LVU139
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   /* Check the parameters */
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ 538              		.loc 1 205 3 view .LVU140
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+ 539              		.loc 1 206 3 view .LVU141
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+ 540              		.loc 1 207 3 view .LVU142
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+ 541              		.loc 1 208 3 view .LVU143
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   /* ------------------------- Configure the port pins ---------------- */
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   /* Initialize  pinpos on first pin set */
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+ 542              		.loc 1 212 3 view .LVU144
+ 543              		.loc 1 212 12 is_stmt 0 view .LVU145
+ 544 0000 0B68     		ldr	r3, [r1]
+ 545              	.LVL36:
+ 546              	.LBB178:
+ 547              	.LBI178:
+ 548              		.file 3 "Drivers/CMSIS/Include/cmsis_gcc.h"
+   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
+   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+ARM GAS  /tmp/ccM5oG95.s 			page 25
+
+
+   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
+   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.0.4
+   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     09. April 2018
+   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
+   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
+   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
+  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
+  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
+  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
+  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
+  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
+  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
+  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
+  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
+  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
+  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
+  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
+  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
+  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
+  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
+  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
+  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
+  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
+  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
+  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
+  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
+  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
+  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
+  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
+  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
+  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
+  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
+  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
+  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
+ARM GAS  /tmp/ccM5oG95.s 			page 26
+
+
+  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
+  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
+  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
+  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
+  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
+  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
+  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
+  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
+  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
+  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
+  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
+ 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
+ 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
+ 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
+ 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
+ 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
+ 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
+ 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
+ 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
+ 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
+ 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
+ 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ARM GAS  /tmp/ccM5oG95.s 			page 27
+
+
+ 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+ 120:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ 121:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 122:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+ 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 128:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
+ 130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 131:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+ 132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 136:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+ 137:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ 138:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 139:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
+ 141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 142:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+ 143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
+ 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+ 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
+ 150:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+ 152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 153:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+ 156:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 162:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
+ 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
+ 164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
+ 165:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+ 167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 168:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 170:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ 171:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ARM GAS  /tmp/ccM5oG95.s 			page 28
+
+
+ 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 177:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
+ 178:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+ 179:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 180:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+ 182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 183:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ 184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 189:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
+ 190:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
+ 191:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+ 192:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+ 194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 195:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 201:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 202:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
+ 204:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 207:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 210:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
+ 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 217:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
+ 218:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
+ 220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 221:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 224:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ARM GAS  /tmp/ccM5oG95.s 			page 29
+
+
+ 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
+ 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 243:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 246:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
+ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 249:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 251:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+ 252:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
+ 259:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
+ 260:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
+ 261:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+ 263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 264:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 266:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+ 267:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 273:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 275:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 276:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+ 278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 279:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 285:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 286:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
+ 287:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ARM GAS  /tmp/ccM5oG95.s 			page 30
+
+
+ 288:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+ 290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 299:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 300:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
+ 302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 303:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ 306:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
+ 313:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
+ 314:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
+ 315:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+ 317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 320:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ 321:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 328:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 329:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 330:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+ 332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+ 334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 339:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
+ 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 342:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ARM GAS  /tmp/ccM5oG95.s 			page 31
+
+
+ 345:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
+ 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
+ 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+ 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 360:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ 361:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
+ 367:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ 368:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
+ 369:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+ 371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 378:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 381:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 384:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 386:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 393:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
+ 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
+ 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
+ 396:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 399:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 401:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ARM GAS  /tmp/ccM5oG95.s 			page 32
+
+
+ 402:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 409:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 410:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 411:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+ 413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 414:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
+ 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ 422:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 423:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 426:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+ 427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 432:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 433:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
+ 436:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 437:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 438:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
+ 440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 441:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
+ 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 448:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 449:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
+ 451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 452:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 457:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
+ 458:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ARM GAS  /tmp/ccM5oG95.s 			page 33
+
+
+ 459:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 460:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+ 462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 463:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 465:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 472:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
+ 473:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
+ 474:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
+ 475:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+ 477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 478:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 480:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
+ 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+ 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+ 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 499:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
+ 500:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ 501:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 502:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+ 504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 505:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 511:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 512:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 513:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 515:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/ccM5oG95.s 			page 34
+
+
+ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 518:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+ 519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 523:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 526:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 529:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 531:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 538:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
+ 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
+ 541:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 544:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 546:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 553:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 556:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 559:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 565:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
+ 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 568:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 571:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+ 572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ARM GAS  /tmp/ccM5oG95.s 			page 35
+
+
+ 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 576:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 577:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 581:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 584:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
+ 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 586:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 587:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 588:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 589:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 591:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 595:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 596:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 597:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 600:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+ 601:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+ 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
+ 608:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 609:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
+ 612:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
+ 613:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+ 615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 617:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 618:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+ 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 629:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
+ARM GAS  /tmp/ccM5oG95.s 			page 36
+
+
+ 630:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 631:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   
+ 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ 635:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 636:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+ 638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 640:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 641:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 642:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 644:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
+ 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
+ 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ 657:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 661:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
+ 662:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
+ 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+ 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 671:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
+ 672:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 673:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
+ 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ 677:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 678:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+ 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 682:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 683:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 686:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ARM GAS  /tmp/ccM5oG95.s 			page 37
+
+
+ 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 695:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
+ 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
+ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
+ 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
+ 701:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+ 703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 705:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 706:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
+ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ 710:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 717:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
+ 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
+ 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
+ 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+ 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ 728:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 730:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 732:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+ 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+ 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
+ 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
+ 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
+ARM GAS  /tmp/ccM5oG95.s 			page 38
+
+
+ 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+ 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ 749:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
+ 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
+ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 752:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+ 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ 758:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
+ 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 765:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+ 767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 769:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
+ 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 774:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
+ 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 778:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 779:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
+ 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 782:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
+ 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 788:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
+ 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+ 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ 795:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+ 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
+ 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
+ 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ 800:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
+ARM GAS  /tmp/ccM5oG95.s 			page 39
+
+
+ 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 802:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+ 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 805:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
+ 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 815:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
+ 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
+ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
+ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 820:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 821:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+ 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+ 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 833:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
+ 834:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 835:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
+ 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 839:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 841:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
+ 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
+ 847:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 848:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
+ 849:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
+ 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 854:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
+ 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 856:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
+ARM GAS  /tmp/ccM5oG95.s 			page 40
+
+
+ 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 861:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 862:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 863:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 864:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
+ 865:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
+ 867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 868:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 873:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 874:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 875:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 876:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
+ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 879:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 880:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 884:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 885:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 886:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
+ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 890:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 891:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 892:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 895:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
+ 896:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
+ 897:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 898:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 899:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+ 901:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ 903:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_bswap32(value);
+ 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 905:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 906:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 908:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 910:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 912:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ARM GAS  /tmp/ccM5oG95.s 			page 41
+
+
+ 915:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
+ 916:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 917:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 918:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+ 920:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 922:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 923:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 924:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 925:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 930:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
+ 931:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 932:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 933:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+ 935:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ 937:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
+ 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 939:Drivers/CMSIS/Include/cmsis_gcc.h ****   int16_t result;
+ 940:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 942:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 945:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 946:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 948:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
+ 949:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
+ 950:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
+ 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
+ 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
+ 953:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 956:Drivers/CMSIS/Include/cmsis_gcc.h ****   op2 %= 32U;
+ 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (op2 == 0U)
+ 958:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 959:Drivers/CMSIS/Include/cmsis_gcc.h ****     return op1;
+ 960:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 961:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
+ 962:Drivers/CMSIS/Include/cmsis_gcc.h **** }
+ 963:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 964:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 966:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
+ 967:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
+ 968:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
+ 969:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
+ 970:Drivers/CMSIS/Include/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
+ 971:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ARM GAS  /tmp/ccM5oG95.s 			page 42
+
+
+ 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+ 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 974:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
+ 976:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse bit order of value
+ 977:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
+ 978:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 979:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
+ 980:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+ 549              		.loc 3 981 31 is_stmt 1 view .LVU146
+ 550              	.LBB179:
+ 982:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
+ 551              		.loc 3 983 3 view .LVU147
+ 984:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+ 986:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+ 987:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 552              		.loc 3 988 4 view .LVU148
+ 553              		.syntax unified
+ 554              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 555 0002 93FAA3F3 		rbit r3, r3
+ 556              	@ 0 "" 2
+ 557              	.LVL37:
+ 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 990:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+ 991:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 992:Drivers/CMSIS/Include/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
+ 993:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
+ 994:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
+ 995:Drivers/CMSIS/Include/cmsis_gcc.h ****     result <<= 1U;
+ 996:Drivers/CMSIS/Include/cmsis_gcc.h ****     result |= value & 1U;
+ 997:Drivers/CMSIS/Include/cmsis_gcc.h ****     s--;
+ 998:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
+ 999:Drivers/CMSIS/Include/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
+1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
+1001:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
+ 558              		.loc 3 1001 3 view .LVU149
+ 559              		.loc 3 1001 3 is_stmt 0 view .LVU150
+ 560              		.thumb
+ 561              		.syntax unified
+ 562              	.LBE179:
+ 563              	.LBE178:
+ 564              		.loc 1 212 10 view .LVU151
+ 565 0006 B3FA83FC 		clz	ip, r3
+ 566              	.LVL38:
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   /* Configure the port pins */
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+ 567              		.loc 1 215 3 is_stmt 1 view .LVU152
+ 568              		.loc 1 215 9 is_stmt 0 view .LVU153
+ 569 000a 57E0     		b	.L35
+ 570              	.LVL39:
+ 571              	.L43:
+ 572              	.LCFI0:
+ARM GAS  /tmp/ccM5oG95.s 			page 43
+
+
+ 573              		.cfi_def_cfa_offset 16
+ 574              		.cfi_offset 4, -16
+ 575              		.cfi_offset 5, -12
+ 576              		.cfi_offset 6, -8
+ 577              		.cfi_offset 14, -4
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     /* Get current io position */
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     if (currentpin)
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     {
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       {
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         /* Check Speed mode parameters */
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+ 578              		.loc 1 225 9 is_stmt 1 view .LVU154
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         /* Speed mode configuration */
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+ 579              		.loc 1 228 9 view .LVU155
+ 580 000c 8D68     		ldr	r5, [r1, #8]
+ 581              	.LVL40:
+ 582              	.LBB180:
+ 583              	.LBI180:
+ 584              		.file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @file    stm32f7xx_ll_gpio.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief   Header file of GPIO LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #ifndef __STM32F7xx_LL_GPIO_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define __STM32F7xx_LL_GPIO_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ARM GAS  /tmp/ccM5oG95.s 			page 44
+
+
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || 
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL GPIO
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /* Private constants ---------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /* Private macros ------------------------------------------------------------*/
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #if defined(USE_FULL_LL_DRIVER)
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @}
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #endif /*USE_FULL_LL_DRIVER*/
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /* Exported types ------------------------------------------------------------*/
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #if defined(USE_FULL_LL_DRIVER)
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief LL GPIO Init Structure definition
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** typedef struct
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                               This parameter can be any value of @ref GPIO_LL_EC_PIN */
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                               This parameter can be a value of @ref GPIO_LL_EC_MODE.
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                               GPIO HW configuration can be modified afterwards using unitary functi
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   uint32_t Speed;        /*!< Specifies the speed for the selected pins.
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                               This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                               GPIO HW configuration can be modified afterwards using unitary functi
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                               This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                               GPIO HW configuration can be modified afterwards using unitary functi
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                               This parameter can be a value of @ref GPIO_LL_EC_PULL.
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                               GPIO HW configuration can be modified afterwards using unitary functi
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                               This parameter can be a value of @ref GPIO_LL_EC_AF.
+ARM GAS  /tmp/ccM5oG95.s 			page 45
+
+
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                               GPIO HW configuration can be modified afterwards using unitary functi
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } LL_GPIO_InitTypeDef;
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @}
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #endif /* USE_FULL_LL_DRIVER */
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /* Exported constants --------------------------------------------------------*/
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_PIN PIN
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_0                      GPIO_BSRR_BS_0 /*!< Select pin 0 */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_1                      GPIO_BSRR_BS_1 /*!< Select pin 1 */
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_2                      GPIO_BSRR_BS_2 /*!< Select pin 2 */
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_3                      GPIO_BSRR_BS_3 /*!< Select pin 3 */
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_4                      GPIO_BSRR_BS_4 /*!< Select pin 4 */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_5                      GPIO_BSRR_BS_5 /*!< Select pin 5 */
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_6                      GPIO_BSRR_BS_6 /*!< Select pin 6 */
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_7                      GPIO_BSRR_BS_7 /*!< Select pin 7 */
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_8                      GPIO_BSRR_BS_8 /*!< Select pin 8 */
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_9                      GPIO_BSRR_BS_9 /*!< Select pin 9 */
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_10                     GPIO_BSRR_BS_10 /*!< Select pin 10 */
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_11                     GPIO_BSRR_BS_11 /*!< Select pin 11 */
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_12                     GPIO_BSRR_BS_12 /*!< Select pin 12 */
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_13                     GPIO_BSRR_BS_13 /*!< Select pin 13 */
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_14                     GPIO_BSRR_BS_14 /*!< Select pin 14 */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_15                     GPIO_BSRR_BS_15 /*!< Select pin 15 */
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                                            GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                                            GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                                            GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                                            GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                                            GPIO_BSRR_BS_15) /*!< Select all pins */
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @}
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_MODE Mode
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODER0_0  /*!< Select output mode */
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODER0_1  /*!< Select alternate function mode
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODER0    /*!< Select analog mode */
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @}
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_OUTPUT Output Type
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ARM GAS  /tmp/ccM5oG95.s 			page 46
+
+
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type *
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @}
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_SPEED Output Speed
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output s
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output spe
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDER_OSPEEDR0   /*!< Select I/O high output spe
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @}
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @}
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_AF Alternate Function
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @}
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @}
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /* Exported macro ------------------------------------------------------------*/
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+ARM GAS  /tmp/ccM5oG95.s 			page 47
+
+
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Write a value in GPIO register
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  __INSTANCE__ GPIO Instance
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  __REG__ Register to be written
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  __VALUE__ Value to be written in the register
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval None
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Read a value in GPIO register
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  __INSTANCE__ GPIO Instance
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  __REG__ Register to be read
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval Register value
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @}
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @}
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /* Exported functions --------------------------------------------------------*/
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @{
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Configure gpio mode for a dedicated pin on dedicated port.
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Warning: only one pin can be passed as parameter.
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  GPIOx GPIO Port
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Pin This parameter can be one of the following values:
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_0
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_1
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_2
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_3
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_4
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_5
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_6
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_7
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_8
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_9
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_10
+ARM GAS  /tmp/ccM5oG95.s 			page 48
+
+
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_11
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_12
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_13
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_14
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_15
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Mode This parameter can be one of the following values:
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_MODE_INPUT
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_MODE_OUTPUT
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_MODE_ALTERNATE
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_MODE_ANALOG
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval None
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Return gpio mode for a dedicated pin on dedicated port.
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Warning: only one pin can be passed as parameter.
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  GPIOx GPIO Port
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Pin This parameter can be one of the following values:
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_0
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_1
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_2
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_3
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_4
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_5
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_6
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_7
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_8
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_9
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_10
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_11
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_12
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_13
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_14
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_15
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval Returned value can be one of the following values:
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_MODE_INPUT
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_MODE_OUTPUT
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_MODE_ALTERNATE
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_MODE_ANALOG
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   return (uint32_t)(READ_BIT(GPIOx->MODER,
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                              (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin)
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Configure gpio output type for several pins on dedicated port.
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Output type as to be set when gpio pin is in output or
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         alternate modes. Possible type are Push-pull or Open-drain.
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
+ARM GAS  /tmp/ccM5oG95.s 			page 49
+
+
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  GPIOx GPIO Port
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  PinMask This parameter can be a combination of the following values:
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_0
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_1
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_2
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_3
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_4
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_5
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_6
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_7
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_8
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_9
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_10
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_11
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_12
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_13
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_14
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_15
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_ALL
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  OutputType This parameter can be one of the following values:
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval None
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t Outpu
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Return gpio output type for several pins on dedicated port.
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Output type as to be set when gpio pin is in output or
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         alternate modes. Possible type are Push-pull or Open-drain.
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Warning: only one pin can be passed as parameter.
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  GPIOx GPIO Port
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Pin This parameter can be one of the following values:
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_0
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_1
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_2
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_3
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_4
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_5
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_6
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_7
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_8
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_9
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_10
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_11
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_12
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_13
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_14
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_15
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_ALL
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval Returned value can be one of the following values:
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ARM GAS  /tmp/ccM5oG95.s 			page 50
+
+
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Configure gpio speed for a dedicated pin on dedicated port.
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   I/O speed can be Low, Medium, Fast or High speed.
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Warning: only one pin can be passed as parameter.
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Refer to datasheet for frequency specifications and the power
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         supply and load conditions for each speed.
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  GPIOx GPIO Port
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Pin This parameter can be one of the following values:
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_0
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_1
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_2
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_3
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_4
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_5
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_6
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_7
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_8
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_9
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_10
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_11
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_12
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_13
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_14
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_15
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Speed This parameter can be one of the following values:
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval None
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
+ 585              		.loc 4 413 22 view .LVU156
+ 586              	.LBB181:
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
+ 587              		.loc 4 415 3 view .LVU157
+ 588 000e 8268     		ldr	r2, [r0, #8]
+ 589              	.LVL41:
+ 590              	.LBB182:
+ 591              	.LBI182:
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 592              		.loc 3 981 31 view .LVU158
+ 593              	.LBB183:
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 594              		.loc 3 983 3 view .LVU159
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 595              		.loc 3 988 4 view .LVU160
+ 596              		.syntax unified
+ 597              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ARM GAS  /tmp/ccM5oG95.s 			page 51
+
+
+ 598 0010 93FAA3F4 		rbit r4, r3
+ 599              	@ 0 "" 2
+ 600              	.LVL42:
+ 601              		.loc 3 1001 3 view .LVU161
+ 602              		.loc 3 1001 3 is_stmt 0 view .LVU162
+ 603              		.thumb
+ 604              		.syntax unified
+ 605              	.LBE183:
+ 606              	.LBE182:
+ 607              		.loc 4 415 3 view .LVU163
+ 608 0014 B4FA84F4 		clz	r4, r4
+ 609 0018 6400     		lsls	r4, r4, #1
+ 610 001a 4FF0030E 		mov	lr, #3
+ 611 001e 0EFA04F4 		lsl	r4, lr, r4
+ 612 0022 22EA0402 		bic	r2, r2, r4
+ 613              	.LVL43:
+ 614              	.LBB184:
+ 615              	.LBI184:
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 616              		.loc 3 981 31 is_stmt 1 view .LVU164
+ 617              	.LBB185:
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 618              		.loc 3 983 3 view .LVU165
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 619              		.loc 3 988 4 view .LVU166
+ 620              		.syntax unified
+ 621              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 622 0026 93FAA3F4 		rbit r4, r3
+ 623              	@ 0 "" 2
+ 624              	.LVL44:
+ 625              		.loc 3 1001 3 view .LVU167
+ 626              		.loc 3 1001 3 is_stmt 0 view .LVU168
+ 627              		.thumb
+ 628              		.syntax unified
+ 629              	.LBE185:
+ 630              	.LBE184:
+ 631              		.loc 4 415 3 view .LVU169
+ 632 002a B4FA84F4 		clz	r4, r4
+ 633 002e 6400     		lsls	r4, r4, #1
+ 634 0030 05FA04F4 		lsl	r4, r5, r4
+ 635 0034 2243     		orrs	r2, r2, r4
+ 636 0036 8260     		str	r2, [r0, #8]
+ 637              	.LVL45:
+ 638              		.loc 4 415 3 view .LVU170
+ 639              	.LBE181:
+ 640              	.LBE180:
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         /* Check Output mode parameters */
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+ 641              		.loc 1 231 9 is_stmt 1 view .LVU171
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         /* Output mode configuration*/
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+ 642              		.loc 1 234 9 view .LVU172
+ 643 0038 0C68     		ldr	r4, [r1]
+ 644 003a CD68     		ldr	r5, [r1, #12]
+ 645              	.LVL46:
+ARM GAS  /tmp/ccM5oG95.s 			page 52
+
+
+ 646              	.LBB186:
+ 647              	.LBI186:
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 648              		.loc 4 342 22 view .LVU173
+ 649              	.LBB187:
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 650              		.loc 4 344 3 view .LVU174
+ 651 003c 4268     		ldr	r2, [r0, #4]
+ 652 003e 22EA0402 		bic	r2, r2, r4
+ 653 0042 05FB04F4 		mul	r4, r5, r4
+ 654              	.LVL47:
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 655              		.loc 4 344 3 is_stmt 0 view .LVU175
+ 656 0046 2243     		orrs	r2, r2, r4
+ 657 0048 4260     		str	r2, [r0, #4]
+ 658              	.LVL48:
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 659              		.loc 4 345 1 view .LVU176
+ 660 004a 45E0     		b	.L30
+ 661              	.LVL49:
+ 662              	.L44:
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 663              		.loc 4 345 1 view .LVU177
+ 664              	.LBE187:
+ 665              	.LBE186:
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       }
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       /* Pull-up Pull down resistor configuration*/
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       {
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         /* Check Alternate parameter */
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+ 666              		.loc 1 243 9 is_stmt 1 view .LVU178
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         /* Speed mode configuration */
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         if (POSITION_VAL(currentpin) < 0x00000008U)
+ 667              		.loc 1 246 9 view .LVU179
+ 668              	.LBB188:
+ 669              	.LBI188:
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 670              		.loc 3 981 31 view .LVU180
+ 671              	.LBB189:
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 672              		.loc 3 983 3 view .LVU181
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 673              		.loc 3 988 4 view .LVU182
+ 674              		.syntax unified
+ 675              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 676 004c 93FAA3F2 		rbit r2, r3
+ 677              	@ 0 "" 2
+ 678              	.LVL50:
+ 679              		.loc 3 1001 3 view .LVU183
+ 680              		.loc 3 1001 3 is_stmt 0 view .LVU184
+ 681              		.thumb
+ 682              		.syntax unified
+ARM GAS  /tmp/ccM5oG95.s 			page 53
+
+
+ 683              	.LBE189:
+ 684              	.LBE188:
+ 685              		.loc 1 246 13 view .LVU185
+ 686 0050 B2FA82F2 		clz	r2, r2
+ 687              		.loc 1 246 12 view .LVU186
+ 688 0054 072A     		cmp	r2, #7
+ 689 0056 15D8     		bhi	.L32
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         {
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****           LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ 690              		.loc 1 248 11 is_stmt 1 view .LVU187
+ 691 0058 4D69     		ldr	r5, [r1, #20]
+ 692              	.LVL51:
+ 693              	.LBB190:
+ 694              	.LBI190:
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****              (Speed << (POSITION_VAL(Pin) * 2U)));
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Return gpio speed for a dedicated pin on dedicated port.
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   I/O speed can be Low, Medium, Fast or High speed.
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Warning: only one pin can be passed as parameter.
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Refer to datasheet for frequency specifications and the power
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         supply and load conditions for each speed.
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  GPIOx GPIO Port
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Pin This parameter can be one of the following values:
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_0
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_1
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_2
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_3
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_4
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_5
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_6
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_7
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_8
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_9
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_10
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_11
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_12
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_13
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_14
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_15
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval Returned value can be one of the following values:
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                              (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Warning: only one pin can be passed as parameter.
+ARM GAS  /tmp/ccM5oG95.s 			page 54
+
+
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  GPIOx GPIO Port
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Pin This parameter can be one of the following values:
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_0
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_1
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_2
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_3
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_4
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_5
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_6
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_7
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_8
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_9
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_10
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_11
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_12
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_13
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_14
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_15
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Pull This parameter can be one of the following values:
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PULL_NO
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PULL_UP
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PULL_DOWN
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval None
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Warning: only one pin can be passed as parameter.
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  GPIOx GPIO Port
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Pin This parameter can be one of the following values:
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_0
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_1
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_2
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_3
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_4
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_5
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_6
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_7
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_8
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_9
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_10
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_11
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_12
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_13
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_14
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_15
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval Returned value can be one of the following values:
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PULL_NO
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PULL_UP
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PULL_DOWN
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ARM GAS  /tmp/ccM5oG95.s 			page 55
+
+
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                              (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin)
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Possible values are from AF0 to AF15 depending on target.
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Warning: only one pin can be passed as parameter.
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  GPIOx GPIO Port
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Pin This parameter can be one of the following values:
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_0
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_1
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_2
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_3
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_4
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_5
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_6
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_7
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Alternate This parameter can be one of the following values:
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_0
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_1
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_2
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_3
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_4
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_5
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_6
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_7
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_8
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_9
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_10
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_11
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_12
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_13
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_14
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_15
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval None
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+ 695              		.loc 4 556 22 view .LVU188
+ 696              	.LBB191:
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)),
+ 697              		.loc 4 558 3 view .LVU189
+ 698 005a 026A     		ldr	r2, [r0, #32]
+ 699              	.LVL52:
+ 700              	.LBB192:
+ 701              	.LBI192:
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 702              		.loc 3 981 31 view .LVU190
+ 703              	.LBB193:
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 704              		.loc 3 983 3 view .LVU191
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 705              		.loc 3 988 4 view .LVU192
+ARM GAS  /tmp/ccM5oG95.s 			page 56
+
+
+ 706              		.syntax unified
+ 707              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 708 005c 93FAA3F4 		rbit r4, r3
+ 709              	@ 0 "" 2
+ 710              	.LVL53:
+ 711              		.loc 3 1001 3 view .LVU193
+ 712              		.loc 3 1001 3 is_stmt 0 view .LVU194
+ 713              		.thumb
+ 714              		.syntax unified
+ 715              	.LBE193:
+ 716              	.LBE192:
+ 717              		.loc 4 558 3 view .LVU195
+ 718 0060 B4FA84F4 		clz	r4, r4
+ 719 0064 A400     		lsls	r4, r4, #2
+ 720 0066 0F26     		movs	r6, #15
+ 721 0068 06FA04F4 		lsl	r4, r6, r4
+ 722 006c 22EA0402 		bic	r2, r2, r4
+ 723              	.LVL54:
+ 724              	.LBB194:
+ 725              	.LBI194:
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 726              		.loc 3 981 31 is_stmt 1 view .LVU196
+ 727              	.LBB195:
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 728              		.loc 3 983 3 view .LVU197
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 729              		.loc 3 988 4 view .LVU198
+ 730              		.syntax unified
+ 731              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 732 0070 93FAA3F4 		rbit r4, r3
+ 733              	@ 0 "" 2
+ 734              	.LVL55:
+ 735              		.loc 3 1001 3 view .LVU199
+ 736              		.loc 3 1001 3 is_stmt 0 view .LVU200
+ 737              		.thumb
+ 738              		.syntax unified
+ 739              	.LBE195:
+ 740              	.LBE194:
+ 741              		.loc 4 558 3 view .LVU201
+ 742 0074 B4FA84F4 		clz	r4, r4
+ 743 0078 A400     		lsls	r4, r4, #2
+ 744 007a 05FA04F4 		lsl	r4, r5, r4
+ 745 007e 2243     		orrs	r2, r2, r4
+ 746 0080 0262     		str	r2, [r0, #32]
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****              (Alternate << (POSITION_VAL(Pin) * 4U)));
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 747              		.loc 4 560 1 view .LVU202
+ 748 0082 41E0     		b	.L31
+ 749              	.LVL56:
+ 750              	.L32:
+ 751              		.loc 4 560 1 view .LVU203
+ 752              	.LBE191:
+ 753              	.LBE190:
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         }
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         else
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         {
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****           LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ARM GAS  /tmp/ccM5oG95.s 			page 57
+
+
+ 754              		.loc 1 252 11 is_stmt 1 view .LVU204
+ 755 0084 4C69     		ldr	r4, [r1, #20]
+ 756              	.LVL57:
+ 757              	.LBB196:
+ 758              	.LBI196:
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  GPIOx GPIO Port
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Pin This parameter can be one of the following values:
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_0
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_1
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_2
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_3
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_4
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_5
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_6
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_7
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval Returned value can be one of the following values:
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_0
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_1
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_2
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_3
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_4
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_5
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_6
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_7
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_8
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_9
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_10
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_11
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_12
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_13
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_14
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_15
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****                              (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) *
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** 
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /**
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Possible values are from AF0 to AF15 depending on target.
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @note   Warning: only one pin can be passed as parameter.
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  GPIOx GPIO Port
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Pin This parameter can be one of the following values:
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_8
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_9
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_10
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_11
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_12
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_13
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_14
+ARM GAS  /tmp/ccM5oG95.s 			page 58
+
+
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_PIN_15
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @param  Alternate This parameter can be one of the following values:
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_0
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_1
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_2
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_3
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_4
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_5
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_6
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_7
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_8
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_9
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_10
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_11
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_12
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_13
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_14
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   *         @arg @ref LL_GPIO_AF_15
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   * @retval None
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   */
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+ 759              		.loc 4 633 22 view .LVU205
+ 760              	.LBB197:
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****   MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)),
+ 761              		.loc 4 635 3 view .LVU206
+ 762 0086 456A     		ldr	r5, [r0, #36]
+ 763 0088 1A0A     		lsrs	r2, r3, #8
+ 764              	.LVL58:
+ 765              	.LBB198:
+ 766              	.LBI198:
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 767              		.loc 3 981 31 view .LVU207
+ 768              	.LBB199:
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 769              		.loc 3 983 3 view .LVU208
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 770              		.loc 3 988 4 view .LVU209
+ 771              		.syntax unified
+ 772              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 773 008a 92FAA2FE 		rbit lr, r2
+ 774              	@ 0 "" 2
+ 775              	.LVL59:
+ 776              		.loc 3 1001 3 view .LVU210
+ 777              		.loc 3 1001 3 is_stmt 0 view .LVU211
+ 778              		.thumb
+ 779              		.syntax unified
+ 780              	.LBE199:
+ 781              	.LBE198:
+ 782              		.loc 4 635 3 view .LVU212
+ 783 008e BEFA8EFE 		clz	lr, lr
+ 784 0092 4FEA8E0E 		lsl	lr, lr, #2
+ 785 0096 0F26     		movs	r6, #15
+ 786 0098 06FA0EFE 		lsl	lr, r6, lr
+ 787 009c 25EA0E05 		bic	r5, r5, lr
+ 788              	.LVL60:
+ 789              	.LBB200:
+ARM GAS  /tmp/ccM5oG95.s 			page 59
+
+
+ 790              	.LBI200:
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 791              		.loc 3 981 31 is_stmt 1 view .LVU213
+ 792              	.LBB201:
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 793              		.loc 3 983 3 view .LVU214
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 794              		.loc 3 988 4 view .LVU215
+ 795              		.syntax unified
+ 796              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 797 00a0 92FAA2F2 		rbit r2, r2
+ 798              	@ 0 "" 2
+ 799              	.LVL61:
+ 800              		.loc 3 1001 3 view .LVU216
+ 801              		.loc 3 1001 3 is_stmt 0 view .LVU217
+ 802              		.thumb
+ 803              		.syntax unified
+ 804              	.LBE201:
+ 805              	.LBE200:
+ 806              		.loc 4 635 3 view .LVU218
+ 807 00a4 B2FA82F2 		clz	r2, r2
+ 808 00a8 9200     		lsls	r2, r2, #2
+ 809 00aa 04FA02F2 		lsl	r2, r4, r2
+ 810 00ae 2A43     		orrs	r2, r2, r5
+ 811 00b0 4262     		str	r2, [r0, #36]
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h ****              (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 812              		.loc 4 637 1 view .LVU219
+ 813 00b2 29E0     		b	.L31
+ 814              	.LVL62:
+ 815              	.L45:
+ 816              		.loc 4 637 1 view .LVU220
+ 817              	.LBE197:
+ 818              	.LBE196:
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****         }
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       }
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       /* Pin Mode configuration */
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     }
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     pinpos++;
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   return (SUCCESS);
+ 819              		.loc 1 260 3 is_stmt 1 view .LVU221
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** }
+ 820              		.loc 1 261 1 is_stmt 0 view .LVU222
+ 821 00b4 0020     		movs	r0, #0
+ 822              	.LVL63:
+ 823              		.loc 1 261 1 view .LVU223
+ 824 00b6 70BD     		pop	{r4, r5, r6, pc}
+ 825              	.LVL64:
+ 826              	.L42:
+ 827              	.LCFI1:
+ 828              		.cfi_def_cfa_offset 0
+ 829              		.cfi_restore 4
+ 830              		.cfi_restore 5
+ 831              		.cfi_restore 6
+ 832              		.cfi_restore 14
+ARM GAS  /tmp/ccM5oG95.s 			page 60
+
+
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 833              		.loc 1 258 5 is_stmt 1 view .LVU224
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 834              		.loc 1 258 11 is_stmt 0 view .LVU225
+ 835 00b8 0CF1010C 		add	ip, ip, #1
+ 836              	.LVL65:
+ 837              	.L35:
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 838              		.loc 1 215 9 is_stmt 1 view .LVU226
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 839              		.loc 1 215 27 is_stmt 0 view .LVU227
+ 840 00bc 0B68     		ldr	r3, [r1]
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 841              		.loc 1 215 9 view .LVU228
+ 842 00be 33FA0CF2 		lsrs	r2, r3, ip
+ 843 00c2 44D0     		beq	.L41
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 844              		.loc 1 218 5 is_stmt 1 view .LVU229
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 845              		.loc 1 218 56 is_stmt 0 view .LVU230
+ 846 00c4 0122     		movs	r2, #1
+ 847 00c6 02FA0CF2 		lsl	r2, r2, ip
+ 848              	.LVL66:
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     {
+ 849              		.loc 1 220 5 is_stmt 1 view .LVU231
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     {
+ 850              		.loc 1 220 8 is_stmt 0 view .LVU232
+ 851 00ca 1340     		ands	r3, r2, r3
+ 852              	.LVL67:
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     {
+ 853              		.loc 1 220 8 view .LVU233
+ 854 00cc F4D0     		beq	.L42
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   uint32_t pinpos     = 0x00000000U;
+ 855              		.loc 1 200 1 view .LVU234
+ 856 00ce 70B5     		push	{r4, r5, r6, lr}
+ 857              	.LCFI2:
+ 858              		.cfi_def_cfa_offset 16
+ 859              		.cfi_offset 4, -16
+ 860              		.cfi_offset 5, -12
+ 861              		.cfi_offset 6, -8
+ 862              		.cfi_offset 14, -4
+ 863              	.L36:
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       {
+ 864              		.loc 1 222 7 is_stmt 1 view .LVU235
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       {
+ 865              		.loc 1 222 27 is_stmt 0 view .LVU236
+ 866 00d0 4A68     		ldr	r2, [r1, #4]
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       {
+ 867              		.loc 1 222 58 view .LVU237
+ 868 00d2 013A     		subs	r2, r2, #1
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       {
+ 869              		.loc 1 222 10 view .LVU238
+ 870 00d4 012A     		cmp	r2, #1
+ 871 00d6 99D9     		bls	.L43
+ 872              	.L30:
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 873              		.loc 1 238 7 is_stmt 1 view .LVU239
+ARM GAS  /tmp/ccM5oG95.s 			page 61
+
+
+ 874              	.LVL68:
+ 875              	.LBB202:
+ 876              	.LBI202:
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 877              		.loc 4 484 22 view .LVU240
+ 878              	.LBB203:
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 879              		.loc 4 486 3 view .LVU241
+ 880 00d8 C268     		ldr	r2, [r0, #12]
+ 881              	.LVL69:
+ 882              	.LBB204:
+ 883              	.LBI204:
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 884              		.loc 3 981 31 view .LVU242
+ 885              	.LBB205:
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 886              		.loc 3 983 3 view .LVU243
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 887              		.loc 3 988 4 view .LVU244
+ 888              		.syntax unified
+ 889              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 890 00da 93FAA3F4 		rbit r4, r3
+ 891              	@ 0 "" 2
+ 892              	.LVL70:
+ 893              		.loc 3 1001 3 view .LVU245
+ 894              		.loc 3 1001 3 is_stmt 0 view .LVU246
+ 895              		.thumb
+ 896              		.syntax unified
+ 897              	.LBE205:
+ 898              	.LBE204:
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 899              		.loc 4 486 3 view .LVU247
+ 900 00de B4FA84F4 		clz	r4, r4
+ 901 00e2 6400     		lsls	r4, r4, #1
+ 902 00e4 0325     		movs	r5, #3
+ 903 00e6 05FA04F4 		lsl	r4, r5, r4
+ 904 00ea 22EA0402 		bic	r2, r2, r4
+ 905              	.LVL71:
+ 906              	.LBB206:
+ 907              	.LBI206:
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 908              		.loc 3 981 31 is_stmt 1 view .LVU248
+ 909              	.LBB207:
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 910              		.loc 3 983 3 view .LVU249
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 911              		.loc 3 988 4 view .LVU250
+ 912              		.syntax unified
+ 913              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 914 00ee 93FAA3F4 		rbit r4, r3
+ 915              	@ 0 "" 2
+ 916              	.LVL72:
+ 917              		.loc 3 1001 3 view .LVU251
+ 918              		.loc 3 1001 3 is_stmt 0 view .LVU252
+ 919              		.thumb
+ 920              		.syntax unified
+ 921              	.LBE207:
+ARM GAS  /tmp/ccM5oG95.s 			page 62
+
+
+ 922              	.LBE206:
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 923              		.loc 4 486 3 view .LVU253
+ 924 00f2 B4FA84F4 		clz	r4, r4
+ 925 00f6 6400     		lsls	r4, r4, #1
+ 926 00f8 0D69     		ldr	r5, [r1, #16]
+ 927 00fa 05FA04F4 		lsl	r4, r5, r4
+ 928 00fe 2243     		orrs	r2, r2, r4
+ 929 0100 C260     		str	r2, [r0, #12]
+ 930              	.LVL73:
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 931              		.loc 4 486 3 view .LVU254
+ 932              	.LBE203:
+ 933              	.LBE202:
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       {
+ 934              		.loc 1 240 7 is_stmt 1 view .LVU255
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       {
+ 935              		.loc 1 240 26 is_stmt 0 view .LVU256
+ 936 0102 4A68     		ldr	r2, [r1, #4]
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****       {
+ 937              		.loc 1 240 10 view .LVU257
+ 938 0104 022A     		cmp	r2, #2
+ 939 0106 A1D0     		beq	.L44
+ 940              	.L31:
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     }
+ 941              		.loc 1 256 7 is_stmt 1 view .LVU258
+ 942 0108 4A68     		ldr	r2, [r1, #4]
+ 943              	.LVL74:
+ 944              	.LBB208:
+ 945              	.LBI208:
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** {
+ 946              		.loc 4 273 22 view .LVU259
+ 947              	.LBB209:
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 948              		.loc 4 275 3 view .LVU260
+ 949 010a 0468     		ldr	r4, [r0]
+ 950              	.LVL75:
+ 951              	.LBB210:
+ 952              	.LBI210:
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 953              		.loc 3 981 31 view .LVU261
+ 954              	.LBB211:
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 955              		.loc 3 983 3 view .LVU262
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 956              		.loc 3 988 4 view .LVU263
+ 957              		.syntax unified
+ 958              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 959 010c 93FAA3FE 		rbit lr, r3
+ 960              	@ 0 "" 2
+ 961              	.LVL76:
+ 962              		.loc 3 1001 3 view .LVU264
+ 963              		.loc 3 1001 3 is_stmt 0 view .LVU265
+ 964              		.thumb
+ 965              		.syntax unified
+ 966              	.LBE211:
+ 967              	.LBE210:
+ARM GAS  /tmp/ccM5oG95.s 			page 63
+
+
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 968              		.loc 4 275 3 view .LVU266
+ 969 0110 BEFA8EFE 		clz	lr, lr
+ 970 0114 4FEA4E0E 		lsl	lr, lr, #1
+ 971 0118 0325     		movs	r5, #3
+ 972 011a 05FA0EFE 		lsl	lr, r5, lr
+ 973 011e 24EA0E0E 		bic	lr, r4, lr
+ 974              	.LVL77:
+ 975              	.LBB212:
+ 976              	.LBI212:
+ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
+ 977              		.loc 3 981 31 is_stmt 1 view .LVU267
+ 978              	.LBB213:
+ 983:Drivers/CMSIS/Include/cmsis_gcc.h **** 
+ 979              		.loc 3 983 3 view .LVU268
+ 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
+ 980              		.loc 3 988 4 view .LVU269
+ 981              		.syntax unified
+ 982              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
+ 983 0122 93FAA3F3 		rbit r3, r3
+ 984              	@ 0 "" 2
+ 985              	.LVL78:
+ 986              		.loc 3 1001 3 view .LVU270
+ 987              		.loc 3 1001 3 is_stmt 0 view .LVU271
+ 988              		.thumb
+ 989              		.syntax unified
+ 990              	.LBE213:
+ 991              	.LBE212:
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 992              		.loc 4 275 3 view .LVU272
+ 993 0126 B3FA83F3 		clz	r3, r3
+ 994 012a 5B00     		lsls	r3, r3, #1
+ 995 012c 02FA03F3 		lsl	r3, r2, r3
+ 996 0130 4EEA0303 		orr	r3, lr, r3
+ 997 0134 0360     		str	r3, [r0]
+ 998              	.LVL79:
+ 999              	.L29:
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** }
+ 1000              		.loc 4 275 3 view .LVU273
+ 1001              	.LBE209:
+ 1002              	.LBE208:
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 1003              		.loc 1 258 5 is_stmt 1 view .LVU274
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   }
+ 1004              		.loc 1 258 11 is_stmt 0 view .LVU275
+ 1005 0136 0CF1010C 		add	ip, ip, #1
+ 1006              	.LVL80:
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 1007              		.loc 1 215 9 is_stmt 1 view .LVU276
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 1008              		.loc 1 215 27 is_stmt 0 view .LVU277
+ 1009 013a 0B68     		ldr	r3, [r1]
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   {
+ 1010              		.loc 1 215 9 view .LVU278
+ 1011 013c 33FA0CF2 		lsrs	r2, r3, ip
+ 1012 0140 B8D0     		beq	.L45
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ARM GAS  /tmp/ccM5oG95.s 			page 64
+
+
+ 1013              		.loc 1 218 5 is_stmt 1 view .LVU279
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 1014              		.loc 1 218 56 is_stmt 0 view .LVU280
+ 1015 0142 0122     		movs	r2, #1
+ 1016 0144 02FA0CF2 		lsl	r2, r2, ip
+ 1017              	.LVL81:
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     {
+ 1018              		.loc 1 220 5 is_stmt 1 view .LVU281
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     {
+ 1019              		.loc 1 220 8 is_stmt 0 view .LVU282
+ 1020 0148 1340     		ands	r3, r2, r3
+ 1021              	.LVL82:
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****     {
+ 1022              		.loc 1 220 8 view .LVU283
+ 1023 014a F4D0     		beq	.L29
+ 1024 014c C0E7     		b	.L36
+ 1025              	.LVL83:
+ 1026              	.L41:
+ 1027              	.LCFI3:
+ 1028              		.cfi_def_cfa_offset 0
+ 1029              		.cfi_restore 4
+ 1030              		.cfi_restore 5
+ 1031              		.cfi_restore 6
+ 1032              		.cfi_restore 14
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** }
+ 1033              		.loc 1 260 3 is_stmt 1 view .LVU284
+ 1034              		.loc 1 261 1 is_stmt 0 view .LVU285
+ 1035 014e 0020     		movs	r0, #0
+ 1036              	.LVL84:
+ 1037              		.loc 1 261 1 view .LVU286
+ 1038 0150 7047     		bx	lr
+ 1039              		.cfi_endproc
+ 1040              	.LFE200:
+ 1042              		.section	.text.LL_GPIO_StructInit,"ax",%progbits
+ 1043              		.align	1
+ 1044              		.global	LL_GPIO_StructInit
+ 1045              		.syntax unified
+ 1046              		.thumb
+ 1047              		.thumb_func
+ 1048              		.fpu fpv5-d16
+ 1050              	LL_GPIO_StructInit:
+ 1051              	.LVL85:
+ 1052              	.LFB201:
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /**
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   *                          whose fields will be set to default values.
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   * @retval None
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   */
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** 
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** {
+ 1053              		.loc 1 271 1 is_stmt 1 view -0
+ 1054              		.cfi_startproc
+ 1055              		@ args = 0, pretend = 0, frame = 0
+ 1056              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccM5oG95.s 			page 65
+
+
+ 1057              		@ link register save eliminated.
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   /* Reset GPIO init structure parameters values */
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
+ 1058              		.loc 1 273 3 view .LVU288
+ 1059              		.loc 1 273 31 is_stmt 0 view .LVU289
+ 1060 0000 4FF6FF73 		movw	r3, #65535
+ 1061 0004 0360     		str	r3, [r0]
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
+ 1062              		.loc 1 274 3 is_stmt 1 view .LVU290
+ 1063              		.loc 1 274 31 is_stmt 0 view .LVU291
+ 1064 0006 0323     		movs	r3, #3
+ 1065 0008 4360     		str	r3, [r0, #4]
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
+ 1066              		.loc 1 275 3 is_stmt 1 view .LVU292
+ 1067              		.loc 1 275 31 is_stmt 0 view .LVU293
+ 1068 000a 0023     		movs	r3, #0
+ 1069 000c 8360     		str	r3, [r0, #8]
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 1070              		.loc 1 276 3 is_stmt 1 view .LVU294
+ 1071              		.loc 1 276 31 is_stmt 0 view .LVU295
+ 1072 000e C360     		str	r3, [r0, #12]
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
+ 1073              		.loc 1 277 3 is_stmt 1 view .LVU296
+ 1074              		.loc 1 277 31 is_stmt 0 view .LVU297
+ 1075 0010 0361     		str	r3, [r0, #16]
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c ****   GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
+ 1076              		.loc 1 278 3 is_stmt 1 view .LVU298
+ 1077              		.loc 1 278 31 is_stmt 0 view .LVU299
+ 1078 0012 4361     		str	r3, [r0, #20]
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** }
+ 1079              		.loc 1 279 1 view .LVU300
+ 1080 0014 7047     		bx	lr
+ 1081              		.cfi_endproc
+ 1082              	.LFE201:
+ 1084              		.text
+ 1085              	.Letext0:
+ 1086              		.file 5 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 1087              		.file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 1088              		.file 7 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ARM GAS  /tmp/ccM5oG95.s 			page 66
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_ll_gpio.c
+     /tmp/ccM5oG95.s:17     .text.LL_GPIO_DeInit:0000000000000000 $t
+     /tmp/ccM5oG95.s:25     .text.LL_GPIO_DeInit:0000000000000000 LL_GPIO_DeInit
+     /tmp/ccM5oG95.s:505    .text.LL_GPIO_DeInit:0000000000000150 $d
+     /tmp/ccM5oG95.s:522    .text.LL_GPIO_Init:0000000000000000 $t
+     /tmp/ccM5oG95.s:529    .text.LL_GPIO_Init:0000000000000000 LL_GPIO_Init
+     /tmp/ccM5oG95.s:1043   .text.LL_GPIO_StructInit:0000000000000000 $t
+     /tmp/ccM5oG95.s:1050   .text.LL_GPIO_StructInit:0000000000000000 LL_GPIO_StructInit
+
+NO UNDEFINED SYMBOLS
diff --git a/build/stm32f7xx_ll_gpio.o b/build/stm32f7xx_ll_gpio.o
new file mode 100644
index 0000000..4737eea
Binary files /dev/null and b/build/stm32f7xx_ll_gpio.o differ
diff --git a/build/stm32f7xx_ll_rcc.d b/build/stm32f7xx_ll_rcc.d
new file mode 100644
index 0000000..d72a6bc
--- /dev/null
+++ b/build/stm32f7xx_ll_rcc.d
@@ -0,0 +1,66 @@
+build/stm32f7xx_ll_rcc.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_ll_rcc.lst b/build/stm32f7xx_ll_rcc.lst
new file mode 100644
index 0000000..9ea0494
--- /dev/null
+++ b/build/stm32f7xx_ll_rcc.lst
@@ -0,0 +1,11380 @@
+ARM GAS  /tmp/ccTMI75D.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_ll_rcc.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.LL_RCC_DeInit,"ax",%progbits
+  17              		.align	1
+  18              		.global	LL_RCC_DeInit
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	LL_RCC_DeInit:
+  26              	.LFB295:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @file    stm32f7xx_ll_rcc.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief   RCC LL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * This software is licensed under terms that can be found in the LICENSE file in
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   ******************************************************************************
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(USE_FULL_LL_DRIVER)
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Includes ------------------------------------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #include "stm32f7xx_ll_rcc.h"
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #ifdef  USE_FULL_ASSERT
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   #include "stm32_assert.h"
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #else
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   #define assert_param(expr) ((void)0U)
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup STM32F7xx_LL_Driver
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @{
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(RCC)
+ARM GAS  /tmp/ccTMI75D.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @{
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Private types -------------------------------------------------------------*/
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Private variables ---------------------------------------------------------*/
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Private constants ---------------------------------------------------------*/
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Private macros ------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL_Private_Macros
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @{
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                             || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                             || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                             || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE))
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                              || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                              || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                              || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE))
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(I2C4)
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                             || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                             || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                             || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #else
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                             || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                             || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* I2C4 */
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                             || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SDMMC2)
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                             || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE))
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #else
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SDMMC2 */
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DFSDM1_Channel0)
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURC
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DFSDM1_Channel0 */
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ARM GAS  /tmp/ccTMI75D.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(CEC)
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* CEC */
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DSI)
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DSI */
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(LTDC)
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* LTDC */
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SPDIFRX)
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SPDIFRX */
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @}
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Private function prototypes -----------------------------------------------*/
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @defgroup RCC_LL_Private_Functions RCC Private functions
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @{
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetSystemClockFreq(void);
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_SAI(void);
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_48M(void);
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DSI)
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_DSI(void);
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DSI */
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(LTDC)
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* LTDC */
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SPDIFRX)
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SPDIFRX */
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @}
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Exported functions --------------------------------------------------------*/
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL_Exported_Functions
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @{
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL_EF_Init
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @{
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ARM GAS  /tmp/ccTMI75D.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Reset the RCC clock configuration to the default reset state.
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @note   The default reset state of the clock configuration is given below:
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - HSI ON and used as system clock source
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - HSE, PLL, PLLI2S, PLLSAI OFF
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - AHB, APB1 and APB2 prescaler set to 1.
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - CSS, MCO OFF
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - All interrupts disabled
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @note   This function doesn't modify the configuration of the
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - Peripheral clocks
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - LSI, LSE and RTC clocks
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval An ErrorStatus enumeration value:
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *          - SUCCESS: RCC registers are de-initialized
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *          - ERROR: not applicable
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** ErrorStatus LL_RCC_DeInit(void)
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+  28              		.loc 1 163 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 8
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  33 0000 82B0     		sub	sp, sp, #8
+  34              	.LCFI0:
+  35              		.cfi_def_cfa_offset 8
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   __IO uint32_t vl_mask;
+  36              		.loc 1 164 3 view .LVU1
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Set HSION bit */
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   LL_RCC_HSI_Enable();
+  37              		.loc 1 167 3 view .LVU2
+  38              	.LBB234:
+  39              	.LBI234:
+  40              		.file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @file    stm32f7xx_ll_rcc.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief   Header file of RCC LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * This software is licensed under terms that can be found in the LICENSE file in
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   ******************************************************************************
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #ifndef __STM32F7xx_LL_RCC_H
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __STM32F7xx_LL_RCC_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #ifdef __cplusplus
+ARM GAS  /tmp/ccTMI75D.s 			page 5
+
+
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** extern "C" {
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Includes ------------------------------------------------------------------*/
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #include "stm32f7xx.h"
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @addtogroup STM32F7xx_LL_Driver
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC)
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL RCC
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private types -------------------------------------------------------------*/
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private variables ---------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private constants ---------------------------------------------------------*/
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private macros ------------------------------------------------------------*/
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER)
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /*USE_FULL_LL_DRIVER*/
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported types ------------------------------------------------------------*/
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER)
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  RCC Clocks Frequency Structure
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** typedef struct
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
+ARM GAS  /tmp/ccTMI75D.s 			page 6
+
+
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } LL_RCC_ClocksTypeDef;
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported constants --------------------------------------------------------*/
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief    Defines used to adapt values of different oscillators
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note     These values could be modified in the user environment according to 
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *           HW set-up.
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined  (HSE_VALUE)
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* HSE_VALUE */
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined  (HSI_VALUE)
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* HSI_VALUE */
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined  (LSE_VALUE)
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LSE_VALUE */
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined  (LSI_VALUE)
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LSI_VALUE */
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined  (EXTERNAL_CLOCK_VALUE)
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_CLOCK_VALUE */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_SAI1_CLOCK_VALUE    48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_SAI2_CLOCK_VALUE    48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief    Flags defines which can be used with LL_RCC_WriteReg function
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ARM GAS  /tmp/ccTMI75D.s 			page 7
+
+
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYC             RCC_CIR_PLLI2SRDYC  /*!< PLLI2S Ready Interrupt Clear */
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYC             RCC_CIR_PLLSAIRDYC  /*!< PLLSAI Ready Interrupt Clear */
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt 
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief    Flags defines which can be used with LL_RCC_ReadReg function
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYF             RCC_CIR_PLLI2SRDYF  /*!< PLLI2S Ready Interrupt flag */
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYF             RCC_CIR_PLLSAIRDYF  /*!< PLLSAI Ready Interrupt flag */
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF        /*!< Clock Security System Interrupt 
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_PORRSTF                 RCC_CSR_PORRSTF    /*!< POR/PDR reset flag */
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag 
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_IT IT Defines
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYIE            RCC_CIR_PLLI2SRDYIE   /*!< PLLI2S Ready Interrupt Enable 
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYIE            RCC_CIR_PLLSAIRDYIE   /*!< PLLSAI Ready Interrupt Enable 
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_LOW                0x00000000U             /*!< Xtal mode lower driving cap
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium high drivi
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium low drivin
+ARM GAS  /tmp/ccTMI75D.s 			page 8
+
+
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving ca
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
+ARM GAS  /tmp/ccTMI75D.s 			page 9
+
+
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI              (uint32_t)(RCC_CFGR_MCO1|0x00000000U)                   
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U))      
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U))      
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)(RCC_CFGR_MCO2|0x00000000U)                   
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_PLLI2S           (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U))      
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U))      
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_1                  (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U)                
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_2                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U))
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_3                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFG
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_4                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFG
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_5                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U))  
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_1                  (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U)                
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_2                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U))
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_3                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFG
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_4                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFG
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_5                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U))  
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_NOCLOCK                  0x00000000U             /*!< HSE not divided */
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_2                RCC_CFGR_RTCPRE_1       /*!< HSE clock divided by 2 */
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_3                (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE cl
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_4                RCC_CFGR_RTCPRE_2       /*!< HSE clock divided by 4 */
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_5                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE cl
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_6                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE cl
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_7                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_8                RCC_CFGR_RTCPRE_3       /*!< HSE clock divided by 8 */
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_9                (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE cl
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_10               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE cl
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_11               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_12               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE cl
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_13               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_14               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_15               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|
+ARM GAS  /tmp/ccTMI75D.s 			page 10
+
+
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_16               RCC_CFGR_RTCPRE_4       /*!< HSE clock divided by 16 */
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_17               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)       /*!< HSE cl
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_18               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)       /*!< HSE cl
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_19               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_20               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)       /*!< HSE cl
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_21               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_22               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_23               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_24               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)       /*!< HSE cl
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_25               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_26               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_27               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_28               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_29               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_30               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_31               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER)
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for th
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be pro
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_PCLK2      (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | 0x00000000U
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | 0x00000000U
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | 0x00000000U
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_PCLK2      (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | 0x00000000U
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_UARTx_CLKSOURCE  Peripheral UART clock source selection
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ARM GAS  /tmp/ccTMI75D.s 			page 11
+
+
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | 0x00000000U) 
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | 0x00000000U) 
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | 0x00000000U) 
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | 0x00000000U) 
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C1SEL|0x00000000U) /*!< PCLK1 
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_0 
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_1 
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C2SEL|0x00000000U) /*!< PCLK1 
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_0 
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_1 
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C3SEL|0x00000000U) /*!< PCLK1 
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_0 
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_1 
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(I2C4)
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C4SEL|0x00000000U) /*!< PCLK1 
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_0 
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_1 
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* I2C4 */
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1       0x00000000U                 /*!< PCLK1 clock used as LP
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSI         RCC_DCKCFGR2_LPTIM1SEL_0    /*!< LSI oscillator clock u
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_HSI         RCC_DCKCFGR2_LPTIM1SEL_1    /*!< HSI oscillator clock u
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSE         (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTI
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR1_SAI1SEL | 0x00000000U)          
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_
+ARM GAS  /tmp/ccTMI75D.s 			page 12
+
+
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PIN          (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLSRC       (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL 
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR1_SAI2SEL | 0x00000000U)          
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PIN          (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLSRC       (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL 
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE  Peripheral SDMMC clock source selection
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK       (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | 0x00000000U)    
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK         (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | (RCC_DCKCFGR2_SD
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SDMMC2)
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK       (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | 0x00000000U)    
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK         (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | (RCC_DCKCFGR2_SD
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SDMMC2 */
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_PLL          0x00000000U            /*!< PLL clock used as RNG clock s
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_PLLSAI       RCC_DCKCFGR2_CK48MSEL  /*!< PLLSAI clock used as RNG cloc
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL          0x00000000U            /*!< PLL clock used as USB clock s
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLLSAI       RCC_DCKCFGR2_CK48MSEL  /*!< PLLSAI1 clock used as USB clo
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE_PHY          0x00000000U           /*!< DSI-PHY clock used as DSI byte
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE_PLL          RCC_DCKCFGR2_DSISEL   /*!< PLL clock used as DSI byte lan
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC)
+ARM GAS  /tmp/ccTMI75D.s 			page 13
+
+
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_LSE               0x00000000U                /*!< LSE oscillator clock
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488        RCC_DCKCFGR2_CECSEL        /*!< HSI oscillator clock
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE  Peripheral I2S clock source selection
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PLLI2S           0x00000000U                /*!< I2S oscillator clock
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PIN              RCC_CFGR_I2SSRC            /*!< External pin clock u
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE  Peripheral 48Mhz domain clock source selection
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE_PLL             0x00000000U                /*!< PLL oscillator clock
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE_PLLSAI          RCC_DCKCFGR2_CK48MSEL      /*!< PLLSAI oscillator cl
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0)
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE  Peripheral DFSDM Audio clock source selection
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1     0x00000000U                /*!< SAI1 clock used as D
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2     RCC_DCKCFGR1_ADFSDM1SEL    /*!< SAI2 clock used as D
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE  Peripheral DFSDM clock source selection
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as 
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         RCC_DCKCFGR1_DFSDM1SEL     /*!< System clock used as
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USARTx  Peripheral USART get clock source
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE            RCC_DCKCFGR2_USART1SEL /*!< USART1 Clock source selectio
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE            RCC_DCKCFGR2_USART2SEL /*!< USART2 Clock source selectio
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE            RCC_DCKCFGR2_USART3SEL /*!< USART3 Clock source selectio
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE            RCC_DCKCFGR2_USART6SEL /*!< USART6 Clock source selectio
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ARM GAS  /tmp/ccTMI75D.s 			page 14
+
+
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_UARTx  Peripheral UART get clock source
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE             RCC_DCKCFGR2_UART4SEL /*!< UART4 Clock source selection 
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE             RCC_DCKCFGR2_UART5SEL /*!< UART5 Clock source selection 
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE             RCC_DCKCFGR2_UART7SEL /*!< UART7 Clock source selection 
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE             RCC_DCKCFGR2_UART8SEL /*!< UART8 Clock source selection 
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2Cx  Peripheral I2C get clock source
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE              RCC_DCKCFGR2_I2C1SEL  /*!< I2C1 Clock source selection *
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE              RCC_DCKCFGR2_I2C2SEL  /*!< I2C2 Clock source selection *
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE              RCC_DCKCFGR2_I2C3SEL  /*!< I2C3 Clock source selection *
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(I2C4)
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE              RCC_DCKCFGR2_I2C4SEL  /*!< I2C4 Clock source selection *
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* I2C4 */
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1  Peripheral LPTIM get clock source
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE            RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selectio
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE              RCC_DCKCFGR1_SAI1SEL /*!< SAI1 Clock source selection */
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE              RCC_DCKCFGR1_SAI2SEL /*!< SAI2 Clock source selection */
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SDMMCx  Peripheral SDMMC get clock source
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE            RCC_DCKCFGR2_SDMMC1SEL /*!< SDMMC1 Clock source selectio
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SDMMC2)
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE            RCC_DCKCFGR2_SDMMC2SEL /*!< SDMMC2 Clock source selectio
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SDMMC2 */
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CK48M  Peripheral CK48M get clock source
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ARM GAS  /tmp/ccTMI75D.s 			page 15
+
+
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source sel
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE               RCC_DCKCFGR2_CK48MSEL /*!< RNG Clock source selection */
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE               RCC_DCKCFGR2_CK48MSEL /*!< USB Clock source selection */
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC)
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC  Peripheral CEC get clock source
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE               RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2S1  Peripheral I2S get clock source
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE              RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0)
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM_AUDIO  Peripheral DFSDM Audio get clock source
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE      RCC_DCKCFGR1_ADFSDM1SEL /*!< DFSDM Audio Clock source se
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE            RCC_DCKCFGR1_DFSDM1SEL /*!< DFSDM Clock source selection
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+ARM GAS  /tmp/ccTMI75D.s 			page 16
+
+
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE               RCC_DCKCFGR2_DSISEL /*!< DSI Clock source selection */
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(LTDC)
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LTDC  Peripheral LTDC get clock source
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LTDC_CLKSOURCE              RCC_DCKCFGR1_PLLSAIDIVR /*!< LTDC Clock source selection
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LTDC */
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX)
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SPDIFRX  Peripheral SPDIFRX get clock source
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPDIFRX1_CLKSOURCE           RCC_PLLI2SCFGR_PLLI2SP /*!< SPDIFRX Clock source select
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U             /*!< No clock used as RTC clock 
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used a
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used a
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_HSE           RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divide
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_TIM_PRESCALER_TWICE          0x00000000U                  /*!< Timers clock to twice
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_TIM_PRESCALER_FOUR_TIMES     RCC_DCKCFGR1_TIMPRE          /*!< Timers clock to four 
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLI2S and PLLSAI entry clock source
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL e
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ARM GAS  /tmp/ccTMI75D.s 			page 17
+
+
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLM_DIV  PLL, PLLI2S and PLLSAI division factor
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI divisio
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_4                  (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI divisio
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI divisio
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_9                  (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_10                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_11                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_12                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_13                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_14                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_15                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_16                 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI divisio
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_17                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_18                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_19                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_20                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_21                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_22                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_23                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_24                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_25                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_26                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_27                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_28                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_29                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_30                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_31                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_32                 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI divisio
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_33                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_34                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_35                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_36                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_37                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_38                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_39                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_40                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_41                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_42                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_43                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_44                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_45                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_46                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_47                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_48                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_49                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_50                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_51                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_52                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_53                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_54                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ARM GAS  /tmp/ccTMI75D.s 			page 18
+
+
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_55                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_56                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_57                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_58                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_59                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_60                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_61                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_62                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_63                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLCFGR_PLLR)
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_2                  (RCC_PLLCFGR_PLLR_1)                     /*!< Main PLL d
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_3                  (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL d
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_2)                     /*!< Main PLL d
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_5                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL d
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)  /*!< Main PLL d
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_7                  (RCC_PLLCFGR_PLLR)                       /*!< Main PLL d
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLCFGR_PLLR */
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_2                  0x00000000U            /*!< Main PLL division factor for
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_4                  RCC_PLLCFGR_PLLP_0     /*!< Main PLL division factor for
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_6                  RCC_PLLCFGR_PLLP_1     /*!< Main PLL division factor for
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)   /*!< Main PL
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_2                  RCC_PLLCFGR_PLLQ_1                      /*!< Main PLL di
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_3                  (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_4                  RCC_PLLCFGR_PLLQ_2                      /*!< Main PLL di
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_5                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL di
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_7                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_8                  RCC_PLLCFGR_PLLQ_3                      /*!< Main PLL di
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_9                  (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_10                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL di
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_11                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_12                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL di
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_13                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_14                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_15                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ARM GAS  /tmp/ccTMI75D.s 			page 19
+
+
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_SPRE_SEL  PLL Spread Spectrum Selection
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPREAD_SELECT_CENTER        0x00000000U                   /*!< PLL center spread spe
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPREAD_SELECT_DOWN          RCC_SSCGR_SPREADSEL           /*!< PLL down spread spect
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SQ  PLLI2SQ division factor (PLLI2SQ)
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_2              RCC_PLLI2SCFGR_PLLI2SQ_1        /*!< PLLI2S division fact
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_3              (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)    
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_4              RCC_PLLI2SCFGR_PLLI2SQ_2        /*!< PLLI2S division fact
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_5              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)    
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_6              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)    
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_7              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RC
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_8              RCC_PLLI2SCFGR_PLLI2SQ_3        /*!< PLLI2S division fact
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_9              (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0)    
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_10             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1)    
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_11             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RC
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_12             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2)    
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_13             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_14             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_15             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SDIVQ  PLLI2SDIVQ division factor (PLLI2SDIVQ)
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_1           0x00000000U                        /*!< PLLI2S division f
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_2           RCC_DCKCFGR1_PLLI2SDIVQ_0          /*!< PLLI2S division f
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_3           RCC_DCKCFGR1_PLLI2SDIVQ_1          /*!< PLLI2S division f
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_4           (RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0)  
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_5           RCC_DCKCFGR1_PLLI2SDIVQ_2          /*!< PLLI2S division f
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_6           (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0)  
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_7           (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1)  
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_8           (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | 
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_9           RCC_DCKCFGR1_PLLI2SDIVQ_3          /*!< PLLI2S division f
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_10          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0)  
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_11          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1)  
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_12          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | 
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_13          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2)  
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_14          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_15          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_16          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_17          RCC_DCKCFGR1_PLLI2SDIVQ_4          /*!< PLLI2S division f
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_18          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_0)  
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_19          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1)  
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_20          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | 
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_21          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2)  
+ARM GAS  /tmp/ccTMI75D.s 			page 20
+
+
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_22          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_23          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_24          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_25          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3)  
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_26          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_27          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_28          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_29          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_30          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_31          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_32          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SR  PLLI2SR division factor (PLLI2SR)
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_2              RCC_PLLI2SCFGR_PLLI2SR_1                                 
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_3              (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)    
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_4              RCC_PLLI2SCFGR_PLLI2SR_2                                 
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_5              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0)    
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_6              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1)    
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_7              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RC
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLI2SCFGR_PLLI2SP)
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SP  PLLI2SP division factor (PLLI2SP)
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_2              0x00000000U            /*!< PLLI2S division factor for PL
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_4              RCC_PLLI2SCFGR_PLLI2SP_0        /*!< PLLI2S division fact
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_6              RCC_PLLI2SCFGR_PLLI2SP_1        /*!< PLLI2S division fact
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_8              (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0)    
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLI2SCFGR_PLLI2SP */
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIQ  PLLSAIQ division factor (PLLSAIQ)
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_2              RCC_PLLSAICFGR_PLLSAIQ_1        /*!< PLLSAI division fact
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_3              (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)    
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_4              RCC_PLLSAICFGR_PLLSAIQ_2        /*!< PLLSAI division fact
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_5              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)    
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_6              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)    
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_7              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RC
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_8              RCC_PLLSAICFGR_PLLSAIQ_3        /*!< PLLSAI division fact
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_9              (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0)    
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_10             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1)    
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_11             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RC
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_12             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2)    
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_13             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_14             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC
+ARM GAS  /tmp/ccTMI75D.s 			page 21
+
+
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_15             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIDIVQ  PLLSAIDIVQ division factor (PLLSAIDIVQ)
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_1           0x00000000U               /*!< PLLSAI division factor for
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_2           RCC_DCKCFGR1_PLLSAIDIVQ_0          /*!< PLLSAI division f
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_3           RCC_DCKCFGR1_PLLSAIDIVQ_1          /*!< PLLSAI division f
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_4           (RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0)  
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_5           RCC_DCKCFGR1_PLLSAIDIVQ_2          /*!< PLLSAI division f
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_6           (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0)  
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_7           (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1)  
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_8           (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | 
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_9           RCC_DCKCFGR1_PLLSAIDIVQ_3          /*!< PLLSAI division f
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_10          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0)  
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_11          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1)  
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_12          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | 
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_13          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2)  
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_14          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_15          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_16          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_17          RCC_DCKCFGR1_PLLSAIDIVQ_4         /*!< PLLSAI division fa
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_18          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_0)  
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_19          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1)  
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_20          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | 
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_21          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2)  
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_22          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_23          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_24          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_25          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3)  
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_26          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_27          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_28          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_29          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_30          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_31          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_32          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLSAICFGR_PLLSAIR)
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIR  PLLSAIR division factor (PLLSAIR)
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_2              RCC_PLLSAICFGR_PLLSAIR_1                                 
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_3              (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)    
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_4              RCC_PLLSAICFGR_PLLSAIR_2                                 
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_5              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0)    
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_6              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1)    
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_7              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RC
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ARM GAS  /tmp/ccTMI75D.s 			page 22
+
+
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLSAICFGR_PLLSAIR */
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIDIVR  PLLSAIDIVR division factor (PLLSAIDIVR)
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_2           0x00000000U             /*!< PLLSAI division factor for P
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_4           RCC_DCKCFGR1_PLLSAIDIVR_0        /*!< PLLSAI division fac
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_8           RCC_DCKCFGR1_PLLSAIDIVR_1        /*!< PLLSAI division fac
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_16          (RCC_DCKCFGR1_PLLSAIDIVR_1 | RCC_DCKCFGR1_PLLSAIDIVR_0)  
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIP  PLLSAIP division factor (PLLSAIP)
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_2              0x00000000U               /*!< PLLSAI division factor for
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_4              RCC_PLLSAICFGR_PLLSAIP_0        /*!< PLLSAI division fact
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_6              RCC_PLLSAICFGR_PLLSAIP_1        /*!< PLLSAI division fact
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_8              (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0)    
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported macro ------------------------------------------------------------*/
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Write a value in RCC register
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __REG__ Register to be written
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __VALUE__ Value to be written in the register
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Read a value in RCC register
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __REG__ Register to be read
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Register value
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ARM GAS  /tmp/ccTMI75D.s 			page 23
+
+
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLCLK frequency on system domain
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+ARM GAS  /tmp/ccTMI75D.s 			page 24
+
+
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLN__ Between 50 and 432
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLP__ This parameter can be one of the following values:
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_2
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_4
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_6
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_8
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLL clock frequency (in Hz)
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+ARM GAS  /tmp/ccTMI75D.s 			page 25
+
+
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLN__ Between 50 and 432
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLQ__ This parameter can be one of the following values:
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_2
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_3
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_4
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_5
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_6
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_7
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_8
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_9
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_10
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_11
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_12
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_13
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_14
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_15
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLL clock frequency (in Hz)
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__)
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
+ARM GAS  /tmp/ccTMI75D.s 			page 26
+
+
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLCLK frequency used on DSI
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+ARM GAS  /tmp/ccTMI75D.s 			page 27
+
+
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLN__ Between 50 and 432
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLR__ This parameter can be one of the following values:
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_2
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_3
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_4
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_5
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_6
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_7
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLL clock frequency (in Hz)
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__)
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ 
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+ARM GAS  /tmp/ccTMI75D.s 			page 28
+
+
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIN__ Between 50 and 432
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIQ__ This parameter can be one of the following values:
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIDIVQ__ This parameter can be one of the following values:
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+ARM GAS  /tmp/ccTMI75D.s 			page 29
+
+
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLSAI clock frequency (in Hz)
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDI
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCF
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+ARM GAS  /tmp/ccTMI75D.s 			page 30
+
+
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIN__ Between 50 and 432
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIP__ This parameter can be one of the following values:
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLSAI clock frequency (in Hz)
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUT
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U))
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ARM GAS  /tmp/ccTMI75D.s 			page 31
+
+
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(LTDC)
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLSAI frequency used for LTDC domain
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR 
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+ARM GAS  /tmp/ccTMI75D.s 			page 32
+
+
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIN__ Between 50 and 432
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIR__ This parameter can be one of the following values:
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIDIVR__ This parameter can be one of the following values:
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLSAI clock frequency (in Hz)
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAID
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__P
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LTDC */
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ 
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+ARM GAS  /tmp/ccTMI75D.s 			page 33
+
+
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SN__ Between 50 and 432
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SQ__ This parameter can be one of the following values:
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+ARM GAS  /tmp/ccTMI75D.s 			page 34
+
+
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SDIVQ__ This parameter can be one of the following values:
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLI2S clock frequency (in Hz)
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDI
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    (((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCF
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX)
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+ARM GAS  /tmp/ccTMI75D.s 			page 35
+
+
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SN__ Between 50 and 432
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SP__ This parameter can be one of the following values:
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+ARM GAS  /tmp/ccTMI75D.s 			page 36
+
+
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLI2S clock frequency (in Hz)
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__I
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLI2S frequency used for I2S domain
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+ARM GAS  /tmp/ccTMI75D.s 			page 37
+
+
+1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SN__ Between 50 and 432
+1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SR__ This parameter can be one of the following values:
+1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLI2S clock frequency (in Hz)
+1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUT
+1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
+1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the HCLK frequency
+1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __AHBPRESCALER__ This parameter can be one of the following values:
+1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_1
+1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_2
+1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_4
+1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_8
+1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_16
+1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_64
+1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_128
+1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_256
+1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_512
+1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval HCLK clock frequency (in Hz)
+1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTabl
+1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __HCLKFREQ__ HCLK frequency
+1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __APB1PRESCALER__ This parameter can be one of the following values:
+1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_1
+1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_2
+1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_4
+1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_8
+1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_16
+1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PCLK1 clock frequency (in Hz)
+ARM GAS  /tmp/ccTMI75D.s 			page 38
+
+
+1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[
+1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __HCLKFREQ__ HCLK frequency
+1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __APB2PRESCALER__ This parameter can be one of the following values:
+1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_1
+1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_2
+1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_4
+1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_8
+1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_16
+1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PCLK2 clock frequency (in Hz)
+1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[
+1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported functions --------------------------------------------------------*/
+1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSE HSE
+1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable the Clock Security System.
+1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
+1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_CSSON);
+1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable HSE external oscillator (HSE Bypass)
+1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
+1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable HSE external oscillator (HSE Bypass)
+1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
+1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+ARM GAS  /tmp/ccTMI75D.s 			page 39
+
+
+1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable HSE crystal oscillator (HSE ON)
+1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
+1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Enable(void)
+1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_HSEON);
+1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable HSE crystal oscillator (HSE ON)
+1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
+1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Disable(void)
+1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if HSE oscillator Ready
+1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
+1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI HSI
+2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable HSI oscillator
+2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSION         LL_RCC_HSI_Enable
+2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Enable(void)
+  41              		.loc 2 2010 22 view .LVU3
+  42              	.LBB235:
+2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_HSION);
+  43              		.loc 2 2012 3 view .LVU4
+  44 0002 224A     		ldr	r2, .L7
+  45 0004 1368     		ldr	r3, [r2]
+ARM GAS  /tmp/ccTMI75D.s 			page 40
+
+
+  46 0006 43F00103 		orr	r3, r3, #1
+  47 000a 1360     		str	r3, [r2]
+  48              	.L2:
+  49              	.LBE235:
+  50              	.LBE234:
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Wait for HSI READY bit */
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   while(LL_RCC_HSI_IsReady() != 1U)
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+  51              		.loc 1 171 4 discriminator 1 view .LVU5
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+  52              		.loc 1 170 8 discriminator 1 view .LVU6
+  53              	.LBB236:
+  54              	.LBI236:
+2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable HSI oscillator
+2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSION         LL_RCC_HSI_Disable
+2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Disable(void)
+2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if HSI clock is ready
+2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
+2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+  55              		.loc 2 2030 26 discriminator 1 view .LVU7
+  56              	.LBB237:
+2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+  57              		.loc 2 2032 3 discriminator 1 view .LVU8
+  58              		.loc 2 2032 11 is_stmt 0 discriminator 1 view .LVU9
+  59 000c 1F4B     		ldr	r3, .L7
+  60 000e 1B68     		ldr	r3, [r3]
+  61              	.LBE237:
+  62              	.LBE236:
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+  63              		.loc 1 170 8 discriminator 1 view .LVU10
+  64 0010 13F0020F 		tst	r3, #2
+  65 0014 FAD0     		beq	.L2
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Reset CFGR register */
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   LL_RCC_WriteReg(CFGR, 0x00000000U);
+  66              		.loc 1 174 3 is_stmt 1 view .LVU11
+  67 0016 1D4B     		ldr	r3, .L7
+  68 0018 0022     		movs	r2, #0
+  69 001a 9A60     		str	r2, [r3, #8]
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Read CR register */
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   vl_mask = LL_RCC_ReadReg(CR);
+  70              		.loc 1 177 3 view .LVU12
+ARM GAS  /tmp/ccTMI75D.s 			page 41
+
+
+  71              		.loc 1 177 13 is_stmt 0 view .LVU13
+  72 001c 1A68     		ldr	r2, [r3]
+  73              		.loc 1 177 11 view .LVU14
+  74 001e 0192     		str	r2, [sp, #4]
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION 
+  75              		.loc 1 180 3 is_stmt 1 view .LVU15
+  76 0020 0199     		ldr	r1, [sp, #4]
+  77 0022 1B4A     		ldr	r2, .L7+4
+  78 0024 0A40     		ands	r2, r2, r1
+  79 0026 0192     		str	r2, [sp, #4]
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Write new value in CR register */
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   LL_RCC_WriteReg(CR, vl_mask);
+  80              		.loc 1 183 3 view .LVU16
+  81 0028 019A     		ldr	r2, [sp, #4]
+  82 002a 1A60     		str	r2, [r3]
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Set HSITRIM bits to the reset value*/
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   LL_RCC_HSI_SetCalibTrimming(0x10U);
+  83              		.loc 1 186 3 view .LVU17
+  84              	.LVL0:
+  85              	.LBB238:
+  86              	.LBI238:
+2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get HSI Calibration value
+2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note When HSITRIM is written, HSICAL is updated with the sum of
+2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       HSITRIM and the factory trim value
+2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR        HSICAL        LL_RCC_HSI_GetCalibration
+2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
+2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set HSI Calibration trimming
+2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note user-programmable trimming value that is added to the HSICAL
+2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note Default value is 16, which, when added to the HSICAL value,
+2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       should trim the HSI to 16 MHz +/- 1 %
+2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
+2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Value Between Min_Data = 0 and Max_Data = 31
+2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+  87              		.loc 2 2056 22 view .LVU18
+  88              	.LBB239:
+2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
+  89              		.loc 2 2058 3 view .LVU19
+  90 002c 1A68     		ldr	r2, [r3]
+  91 002e 22F0F802 		bic	r2, r2, #248
+  92 0032 42F08002 		orr	r2, r2, #128
+ARM GAS  /tmp/ccTMI75D.s 			page 42
+
+
+  93 0036 1A60     		str	r2, [r3]
+  94              	.LVL1:
+  95              	.L3:
+  96              		.loc 2 2058 3 is_stmt 0 view .LVU20
+  97              	.LBE239:
+  98              	.LBE238:
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Wait for PLL READY bit to be reset */
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   while(LL_RCC_PLL_IsReady() != 0U)
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+  99              		.loc 1 190 4 is_stmt 1 discriminator 1 view .LVU21
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+ 100              		.loc 1 189 8 discriminator 1 view .LVU22
+ 101              	.LBB240:
+ 102              	.LBI240:
+2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get HSI Calibration trimming
+2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
+2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between Min_Data = 0 and Max_Data = 31
+2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSE LSE
+2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable  Low Speed External (LSE) crystal.
+2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
+2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Enable(void)
+2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable  Low Speed External (LSE) crystal.
+2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
+2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Disable(void)
+2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable external clock source (LSE bypass).
+ARM GAS  /tmp/ccTMI75D.s 			page 43
+
+
+2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
+2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable external clock source (LSE bypass).
+2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
+2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set LSE oscillator drive capability
+2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note The oscillator is in Xtal mode when it is not in bypass mode.
+2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
+2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  LSEDrive This parameter can be one of the following values:
+2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_LOW
+2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get LSE oscillator drive capability
+2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
+2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_LOW
+2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if LSE oscillator Ready
+2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
+2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
+2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ARM GAS  /tmp/ccTMI75D.s 			page 44
+
+
+2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSI LSI
+2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable LSI Oscillator
+2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
+2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Enable(void)
+2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CSR, RCC_CSR_LSION);
+2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable LSI Oscillator
+2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
+2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Disable(void)
+2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if LSI is Ready
+2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
+2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_System System
+2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure the system clock source
+2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
+2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+ARM GAS  /tmp/ccTMI75D.s 			page 45
+
+
+2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get the system clock source
+2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
+2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set AHB prescaler
+2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
+2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Prescaler This parameter can be one of the following values:
+2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_1
+2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_2
+2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_4
+2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_8
+2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_16
+2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_64
+2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_128
+2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_256
+2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_512
+2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set APB1 prescaler
+2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
+2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Prescaler This parameter can be one of the following values:
+2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_1
+2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_2
+2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_4
+2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_8
+2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_16
+2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set APB2 prescaler
+2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
+2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Prescaler This parameter can be one of the following values:
+ARM GAS  /tmp/ccTMI75D.s 			page 46
+
+
+2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_1
+2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_2
+2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_4
+2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_8
+2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_16
+2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get AHB prescaler
+2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
+2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_1
+2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_2
+2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_4
+2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_8
+2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_16
+2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_64
+2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_128
+2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_256
+2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_512
+2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get APB1 prescaler
+2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
+2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_1
+2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_2
+2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_4
+2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_8
+2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_16
+2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get APB2 prescaler
+2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
+2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_1
+2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_2
+2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_4
+2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_8
+2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_16
+2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+ARM GAS  /tmp/ccTMI75D.s 			page 47
+
+
+2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_MCO MCO
+2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure MCOx
+2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
+2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
+2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         CFGR         MCO2          LL_RCC_ConfigMCO\n
+2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
+2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  MCOxSource This parameter can be one of the following values:
+2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
+2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
+2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2SOURCE_HSE
+2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
+2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  MCOxPrescaler This parameter can be one of the following values:
+2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1_DIV_1
+2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1_DIV_2
+2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1_DIV_3
+2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1_DIV_4
+2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1_DIV_5
+2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2_DIV_1
+2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2_DIV_2
+2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2_DIV_3
+2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2_DIV_4
+2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2_DIV_5
+2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U),  (MCOxSource <<
+2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure USARTx clock source
+2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        USART1SEL     LL_RCC_SetUSARTClockSource\n
+2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART2SEL     LL_RCC_SetUSARTClockSource\n
+ARM GAS  /tmp/ccTMI75D.s 			page 48
+
+
+2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART3SEL     LL_RCC_SetUSARTClockSource\n
+2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART6SEL     LL_RCC_SetUSARTClockSource
+2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  USARTxSource This parameter can be one of the following values:
+2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
+2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
+2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
+2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
+2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
+2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
+2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure UARTx clock source
+2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        UART4SEL      LL_RCC_SetUARTClockSource\n
+2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART5SEL      LL_RCC_SetUARTClockSource\n
+2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART7SEL      LL_RCC_SetUARTClockSource\n
+2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART8SEL      LL_RCC_SetUARTClockSource
+2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  UARTxSource This parameter can be one of the following values:
+2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
+2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
+2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
+2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
+2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
+2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
+2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
+2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
+2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
+2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
+2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ARM GAS  /tmp/ccTMI75D.s 			page 49
+
+
+2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure I2Cx clock source
+2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        I2C1SEL       LL_RCC_SetI2CClockSource\n
+2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C2SEL       LL_RCC_SetI2CClockSource\n
+2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C3SEL       LL_RCC_SetI2CClockSource\n
+2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C4SEL       LL_RCC_SetI2CClockSource
+2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  I2CxSource This parameter can be one of the following values:
+2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U),  (I2CxSource << 16U));
+2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure LPTIMx clock source
+2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_SetLPTIMClockSource
+2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  LPTIMxSource This parameter can be one of the following values:
+2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
+2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
+2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure SAIx clock source
+2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1        SAI1SEL       LL_RCC_SetSAIClockSource\n
+2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR1        SAI2SEL       LL_RCC_SetSAIClockSource
+2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  SAIxSource This parameter can be one of the following values:
+2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
+2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
+2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
+2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
+2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
+2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
+2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+ARM GAS  /tmp/ccTMI75D.s 			page 50
+
+
+2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
+2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
+2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure SDMMC clock source
+2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        SDMMC1SEL      LL_RCC_SetSDMMCClockSource\n
+2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        SDMMC2SEL      LL_RCC_SetSDMMCClockSource
+2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  SDMMCxSource This parameter can be one of the following values:
+2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
+2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
+2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
+2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
+2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
+2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U));
+2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure 48Mhz domain clock source
+2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_SetCK48MClockSource
+2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  CK48MxSource This parameter can be one of the following values:
+2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
+2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
+2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
+2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure RNG clock source
+2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_SetRNGClockSource
+2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  RNGxSource This parameter can be one of the following values:
+2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
+2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
+2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
+2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure USB clock source
+2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_SetUSBClockSource
+2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  USBxSource This parameter can be one of the following values:
+2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
+ARM GAS  /tmp/ccTMI75D.s 			page 51
+
+
+2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
+2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC)
+2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure CEC clock source
+2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2         CECSEL        LL_RCC_SetCECClockSource
+2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
+2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
+2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */
+2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure I2S clock source
+2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         I2SSRC        LL_RCC_SetI2SClockSource
+2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
+2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
+2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
+2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure DSI clock source
+2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2         DSISEL        LL_RCC_SetDSIClockSource
+2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
+2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source);
+2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0)
+2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure DFSDM Audio clock source
+2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         ADFSDM1SEL        LL_RCC_SetDFSDMAudioClockSource
+2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
+2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
+ARM GAS  /tmp/ccTMI75D.s 			page 52
+
+
+2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
+2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source);
+2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure DFSDM Kernel clock source
+2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         DFSDM1SEL        LL_RCC_SetDFSDMClockSource
+2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
+2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source);
+2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */
+2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get USARTx clock source
+2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        USART1SEL     LL_RCC_GetUSARTClockSource\n
+2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART2SEL     LL_RCC_GetUSARTClockSource\n
+2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART3SEL     LL_RCC_GetUSARTClockSource\n
+2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART6SEL     LL_RCC_GetUSARTClockSource
+2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  USARTx This parameter can be one of the following values:
+2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE
+2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE
+2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE
+2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE
+2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
+2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
+2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
+2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
+2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
+2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U));
+2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get UARTx clock source
+ARM GAS  /tmp/ccTMI75D.s 			page 53
+
+
+2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        UART4SEL      LL_RCC_GetUARTClockSource\n
+2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART5SEL      LL_RCC_GetUARTClockSource\n
+2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART7SEL      LL_RCC_GetUARTClockSource\n
+2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART8SEL      LL_RCC_GetUARTClockSource
+2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  UARTx This parameter can be one of the following values:
+2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE
+2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE
+2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE
+2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE
+2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
+2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
+2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
+2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
+2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
+2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
+2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
+2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
+2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
+2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U));
+2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2Cx clock source
+2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        I2C1SEL       LL_RCC_GetI2CClockSource\n
+2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C2SEL       LL_RCC_GetI2CClockSource\n
+2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C3SEL       LL_RCC_GetI2CClockSource\n
+2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C4SEL       LL_RCC_GetI2CClockSource
+2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  I2Cx This parameter can be one of the following values:
+2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE
+2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
+2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+ARM GAS  /tmp/ccTMI75D.s 			page 54
+
+
+2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****  */
+2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
+2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx);
+2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get LPTIMx clock source
+2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_GetLPTIMClockSource
+2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  LPTIMx This parameter can be one of the following values:
+2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
+2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
+2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get SAIx clock source
+2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1        SAI1SEL       LL_RCC_GetSAIClockSource\n
+2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR1        SAI2SEL       LL_RCC_GetSAIClockSource
+2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  SAIx This parameter can be one of the following values:
+2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE
+2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
+2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
+2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
+2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
+2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
+2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
+2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
+2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U | SAIx);
+2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get SDMMCx clock source
+2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        SDMMC1SEL      LL_RCC_GetSDMMCClockSource\n
+2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        SDMMC2SEL      LL_RCC_GetSDMMCClockSource
+2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  SDMMCx This parameter can be one of the following values:
+2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*)
+2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
+2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
+ARM GAS  /tmp/ccTMI75D.s 			page 55
+
+
+2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
+2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
+2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
+2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx);
+2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get 48Mhz domain clock source
+2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_GetCK48MClockSource
+2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  CK48Mx This parameter can be one of the following values:
+2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CK48M_CLKSOURCE
+2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
+2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
+2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
+2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get RNGx clock source
+2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_GetRNGClockSource
+2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  RNGx This parameter can be one of the following values:
+2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RNG_CLKSOURCE
+2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
+2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
+2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
+2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get USBx clock source
+2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_GetUSBClockSource
+2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  USBx This parameter can be one of the following values:
+2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USB_CLKSOURCE
+2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
+2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
+2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC)
+2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get CEC Clock Source
+2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2         CECSEL        LL_RCC_GetCECClockSource
+2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  CECx This parameter can be one of the following values:
+ARM GAS  /tmp/ccTMI75D.s 			page 56
+
+
+2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CEC_CLKSOURCE
+2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
+2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
+2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */
+2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2S Clock Source
+2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         I2SSRC        LL_RCC_GetI2SClockSource
+2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  I2Sx This parameter can be one of the following values:
+2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2S1_CLKSOURCE
+2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
+2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
+2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0)
+2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get DFSDM Audio Clock Source
+2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         ADFSDM1SEL        LL_RCC_GetDFSDMAudioClockSource
+2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  DFSDMx This parameter can be one of the following values:
+2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
+2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
+2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
+2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
+2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get DFSDM Audio Clock Source
+2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         DFSDM1SEL        LL_RCC_GetDFSDMClockSource
+2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  DFSDMx This parameter can be one of the following values:
+2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
+2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
+2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */
+2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ARM GAS  /tmp/ccTMI75D.s 			page 57
+
+
+2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get DSI Clock Source
+2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2         DSISEL        LL_RCC_GetDSIClockSource
+2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  DSIx This parameter can be one of the following values:
+2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DSI_CLKSOURCE
+2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
+2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx));
+2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_RTC RTC
+2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set RTC Clock Source
+2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
+2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       set). The BDRST bit can be used to reset them.
+2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
+2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get RTC Clock Source
+2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
+2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable RTC
+2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
+ARM GAS  /tmp/ccTMI75D.s 			page 58
+
+
+2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_EnableRTC(void)
+2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable RTC
+2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
+2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_DisableRTC(void)
+2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if RTC has been enabled or not
+2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
+2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
+2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Force the Backup domain reset
+2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
+2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Release the Backup domain reset
+2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
+2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set HSE Prescalers for RTC Clock
+3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
+3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Prescaler This parameter can be one of the following values:
+3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_NOCLOCK
+3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+ARM GAS  /tmp/ccTMI75D.s 			page 59
+
+
+3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
+3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
+3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get HSE Prescalers for RTC Clock
+3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
+3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_NOCLOCK
+3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+ARM GAS  /tmp/ccTMI75D.s 			page 60
+
+
+3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
+3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
+3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
+3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set Timers Clock Prescalers
+3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         TIMPRE        LL_RCC_SetTIMPrescaler
+3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Prescaler This parameter can be one of the following values:
+3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
+3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler);
+3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Timers Clock Prescalers
+3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         TIMPRE        LL_RCC_GetTIMPrescaler
+3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
+3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE));
+3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLL PLL
+3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ARM GAS  /tmp/ccTMI75D.s 			page 61
+
+
+3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable PLL
+3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
+3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Enable(void)
+3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_PLLON);
+3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable PLL
+3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note Cannot be disabled if the PLL clock is used as the system clock
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
+3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Disable(void)
+3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if PLL Ready
+3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
+3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+ 103              		.loc 2 3153 26 discriminator 1 view .LVU23
+ 104              	.LBB241:
+3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+ 105              		.loc 2 3155 3 discriminator 1 view .LVU24
+ 106              		.loc 2 3155 11 is_stmt 0 discriminator 1 view .LVU25
+ 107 0038 144B     		ldr	r3, .L7
+ 108 003a 1B68     		ldr	r3, [r3]
+ 109              	.LBE241:
+ 110              	.LBE240:
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+ 111              		.loc 1 189 8 discriminator 1 view .LVU26
+ 112 003c 13F0007F 		tst	r3, #33554432
+ 113 0040 FAD1     		bne	.L3
+ 114              	.L4:
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Wait for PLLI2S READY bit to be reset */
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   while(LL_RCC_PLLI2S_IsReady() != 0U)
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+ 115              		.loc 1 194 4 is_stmt 1 discriminator 1 view .LVU27
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+ 116              		.loc 1 193 8 discriminator 1 view .LVU28
+ 117              	.LBB242:
+ 118              	.LBI242:
+3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLL used for SYSCLK Domain
+3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+ARM GAS  /tmp/ccTMI75D.s 			page 62
+
+
+3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLP can be written only when PLL is disabled
+3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
+3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
+3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
+3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SYS
+3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+ARM GAS  /tmp/ccTMI75D.s 			page 63
+
+
+3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLP This parameter can be one of the following values:
+3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_2
+3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_4
+3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_6
+3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_8
+3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin
+3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P
+3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLL used for 48Mhz domain clock
+3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLQ can be written only when PLL is disabled
+3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This  can be selected for USB, RNG, SDMMC1
+3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
+3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
+3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
+3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
+3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+ARM GAS  /tmp/ccTMI75D.s 			page 64
+
+
+3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLQ This parameter can be one of the following values:
+3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_2
+3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_3
+3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_4
+3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_5
+3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_6
+3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_7
+3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_8
+3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_9
+ARM GAS  /tmp/ccTMI75D.s 			page 65
+
+
+3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_10
+3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_11
+3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_12
+3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_13
+3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_14
+3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_15
+3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin
+3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P
+3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
+3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLL used for DSI clock
+3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLR can be written only when PLL is disabled
+3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This  can be selected for DSI
+3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_DSI\n
+3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_DSI\n
+3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_DSI\n
+3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_DSI
+3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+ARM GAS  /tmp/ccTMI75D.s 			page 66
+
+
+3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLR This parameter can be one of the following values:
+3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_2
+3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_3
+3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_4
+3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_5
+3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_6
+3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_7
+3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin
+3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P
+3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLL clock source
+3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource
+3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param PLLSource This parameter can be one of the following values:
+3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+ARM GAS  /tmp/ccTMI75D.s 			page 67
+
+
+3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get the oscillator used as PLL clock source.
+3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
+3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Main PLL multiplication factor for VCO
+3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
+3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between 50 and 432
+3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
+3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
+3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Main PLL division factor for PLLP 
+3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLP       LL_RCC_PLL_GetP
+3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_2
+3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_4
+3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_6
+3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_8
+3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
+3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
+3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Main PLL division factor for PLLQ
+3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock)
+3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
+3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_2
+3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_3
+3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_4
+3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_5
+3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_6
+3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_7
+3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_8
+3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_9
+3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_10
+ARM GAS  /tmp/ccTMI75D.s 			page 68
+
+
+3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_11
+3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_12
+3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_13
+3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_14
+3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_15
+3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
+3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
+3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLCFGR_PLLR)
+3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Main PLL division factor for PLLR
+3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used for PLLCLK (system clock)
+3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
+3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_2
+3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_3
+3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_4
+3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_5
+3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_6
+3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_7
+3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
+3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
+3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLCFGR_PLLR */
+3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Division factor for the main PLL and other PLL
+3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
+3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+ARM GAS  /tmp/ccTMI75D.s 			page 69
+
+
+3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
+3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure Spread Spectrum used for PLL
+3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note These bits must be written before enabling PLL
+3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR        MODPER        LL_RCC_PLL_ConfigSpreadSpectrum\n
+3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         SSCGR        INCSTEP       LL_RCC_PLL_ConfigSpreadSpectrum\n
+3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         SSCGR        SPREADSEL     LL_RCC_PLL_ConfigSpreadSpectrum
+3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Mod Between Min_Data=0 and Max_Data=8191
+3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Inc Between Min_Data=0 and Max_Data=32767
+3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Sel This parameter can be one of the following values:
+3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+ARM GAS  /tmp/ccTMI75D.s 			page 70
+
+
+3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
+3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << 
+3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Spread Spectrum Modulation Period for PLL
+3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR         MODPER        LL_RCC_PLL_GetPeriodModulation
+3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between Min_Data=0 and Max_Data=8191
+3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
+3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
+3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Spread Spectrum Incrementation Step for PLL
+3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note Must be written before enabling PLL
+3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR         INCSTEP        LL_RCC_PLL_GetStepIncrementation
+3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between Min_Data=0 and Max_Data=32767
+3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
+3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
+3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Spread Spectrum Selection for PLL
+3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note Must be written before enabling PLL
+3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR         SPREADSEL        LL_RCC_PLL_GetSpreadSelection
+3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
+3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
+3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable Spread Spectrum for PLL.
+3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Enable
+3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
+3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable Spread Spectrum for PLL.
+3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Disable
+3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
+3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ARM GAS  /tmp/ccTMI75D.s 			page 71
+
+
+3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
+3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable PLLI2S
+3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Enable
+3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
+3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
+3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable PLLI2S
+3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Disable
+3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
+3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if PLLI2S Ready
+3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLI2SRDY    LL_RCC_PLLI2S_IsReady
+3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
+ 119              		.loc 2 3711 26 discriminator 1 view .LVU29
+ 120              	.LBB243:
+3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
+ 121              		.loc 2 3713 3 discriminator 1 view .LVU30
+ 122              		.loc 2 3713 11 is_stmt 0 discriminator 1 view .LVU31
+ 123 0042 124B     		ldr	r3, .L7
+ 124 0044 1B68     		ldr	r3, [r3]
+ 125              	.LBE243:
+ 126              	.LBE242:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+ 127              		.loc 1 193 8 discriminator 1 view .LVU32
+ 128 0046 13F0006F 		tst	r3, #134217728
+ 129 004a FAD1     		bne	.L4
+ 130              	.L5:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Wait for PLLSAI READY bit to be reset */
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   while(LL_RCC_PLLSAI_IsReady() != 0U)
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+ 131              		.loc 1 198 4 is_stmt 1 discriminator 1 view .LVU33
+ARM GAS  /tmp/ccTMI75D.s 			page 72
+
+
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+ 132              		.loc 1 197 8 discriminator 1 view .LVU34
+ 133              	.LBB244:
+ 134              	.LBI244:
+3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLLI2S used for SAI1 and SAI2 domain clock
+3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLQ can be written only when PLLI2S is disabled
+3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This can be selected for SAI1 and SAI2
+3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SAI\n
+3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SAI\n
+3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR1      PLLI2SDIVQ    LL_RCC_PLLI2S_ConfigDomain_SAI
+3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+ARM GAS  /tmp/ccTMI75D.s 			page 73
+
+
+3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLQ This parameter can be one of the following values:
+3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLDIVQ This parameter can be one of the following values:
+3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+ARM GAS  /tmp/ccTMI75D.s 			page 74
+
+
+3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, 
+3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCF
+3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ);
+3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX)
+3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief Configure PLLI2S used for SPDIFRX domain clock
+3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLP can be written only when PLLI2S is disabled
+3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This  can be selected for SPDIFRX
+3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SP       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
+3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+ARM GAS  /tmp/ccTMI75D.s 			page 75
+
+
+3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLP This parameter can be one of the following values:
+3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PL
+3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ARM GAS  /tmp/ccTMI75D.s 			page 76
+
+
+3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCF
+3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */
+3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLLI2S used for I2S1 domain clock
+3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLR can be written only when PLLI2S is disabled
+3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This  can be selected for I2S
+3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_I2S\n
+3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_I2S\n
+3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_I2S\n
+3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_I2S
+3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+ARM GAS  /tmp/ccTMI75D.s 			page 77
+
+
+3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLR This parameter can be one of the following values:
+4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, 
+4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCF
+4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2SPLL multiplication factor for VCO
+4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLI2SCFGR  PLLI2SN      LL_RCC_PLLI2S_GetN
+4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between 50 and 432
+4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
+4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos
+4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2SPLL division factor for PLLI2SQ
+4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLI2SCFGR  PLLI2SQ      LL_RCC_PLLI2S_GetQ
+4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+ARM GAS  /tmp/ccTMI75D.s 			page 78
+
+
+4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
+4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
+4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2SPLL division factor for PLLI2SR
+4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used for PLLI2SCLK (I2S clock)
+4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLI2SCFGR  PLLI2SR      LL_RCC_PLLI2S_GetR
+4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
+4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
+4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLI2SCFGR_PLLI2SP)
+4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2SPLL division factor for PLLI2SP
+4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
+4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLI2SCFGR  PLLI2SP      LL_RCC_PLLI2S_GetP
+4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+4093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+4094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+4095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+4096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
+4098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
+4100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLI2SCFGR_PLLI2SP */
+4102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2SPLL division factor for PLLI2SDIVQ
+4105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
+4106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1   PLLI2SDIVQ      LL_RCC_PLLI2S_GetDIVQ
+4107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+ARM GAS  /tmp/ccTMI75D.s 			page 79
+
+
+4109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+4110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+4111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+4112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+4113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+4114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+4115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+4116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+4117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+4118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+4119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+4120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+4121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+4122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+4123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+4124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+4125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+4126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+4127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+4128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+4129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+4130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+4131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+4132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+4133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+4134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+4135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+4136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+4137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+4138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+4139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+4140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
+4142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ));
+4144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+4148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLLSAI PLLSAI
+4151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+4152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable PLLSAI
+4156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Enable
+4157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+4158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
+4160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_PLLSAION);
+4162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable PLLSAI
+ARM GAS  /tmp/ccTMI75D.s 			page 80
+
+
+4166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Disable
+4167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+4168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
+4170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+4172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if PLLSAI Ready
+4176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLSAIRDY    LL_RCC_PLLSAI_IsReady
+4177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+4178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
+ 135              		.loc 2 4179 26 discriminator 1 view .LVU35
+ 136              	.LBB245:
+4180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
+ 137              		.loc 2 4181 3 discriminator 1 view .LVU36
+ 138              		.loc 2 4181 11 is_stmt 0 discriminator 1 view .LVU37
+ 139 004c 0F4B     		ldr	r3, .L7
+ 140 004e 1B68     		ldr	r3, [r3]
+ 141              	.LBE245:
+ 142              	.LBE244:
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {}
+ 143              		.loc 1 197 8 discriminator 1 view .LVU38
+ 144 0050 13F0005F 		tst	r3, #536870912
+ 145 0054 FAD1     		bne	.L5
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Reset PLLCFGR register */
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   LL_RCC_WriteReg(PLLCFGR, 0x24003010U);
+ 146              		.loc 1 201 3 is_stmt 1 view .LVU39
+ 147 0056 0D4B     		ldr	r3, .L7
+ 148 0058 0E4A     		ldr	r2, .L7+8
+ 149 005a 5A60     		str	r2, [r3, #4]
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Reset PLLI2SCFGR register */
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U);
+ 150              		.loc 1 204 3 view .LVU40
+ 151 005c 103A     		subs	r2, r2, #16
+ 152 005e C3F88420 		str	r2, [r3, #132]
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Reset PLLSAICFGR register */
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U);
+ 153              		.loc 1 207 3 view .LVU41
+ 154 0062 C3F88820 		str	r2, [r3, #136]
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Disable all interrupts */
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | R
+ 155              		.loc 1 210 3 view .LVU42
+ 156 0066 DA68     		ldr	r2, [r3, #12]
+ 157 0068 22F4FE42 		bic	r2, r2, #32512
+ 158 006c DA60     		str	r2, [r3, #12]
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Clear all interrupt flags */
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR
+ 159              		.loc 1 213 3 view .LVU43
+ARM GAS  /tmp/ccTMI75D.s 			page 81
+
+
+ 160 006e DA68     		ldr	r2, [r3, #12]
+ 161 0070 42F47F02 		orr	r2, r2, #16711680
+ 162 0074 DA60     		str	r2, [r3, #12]
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Clear LSION bit */
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+ 163              		.loc 1 216 3 view .LVU44
+ 164 0076 5A6F     		ldr	r2, [r3, #116]
+ 165 0078 22F00102 		bic	r2, r2, #1
+ 166 007c 5A67     		str	r2, [r3, #116]
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Reset all CSR flags */
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+ 167              		.loc 1 219 3 view .LVU45
+ 168 007e 5A6F     		ldr	r2, [r3, #116]
+ 169 0080 42F08072 		orr	r2, r2, #16777216
+ 170 0084 5A67     		str	r2, [r3, #116]
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return SUCCESS;
+ 171              		.loc 1 221 3 view .LVU46
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 172              		.loc 1 222 1 is_stmt 0 view .LVU47
+ 173 0086 0020     		movs	r0, #0
+ 174 0088 02B0     		add	sp, sp, #8
+ 175              	.LCFI1:
+ 176              		.cfi_def_cfa_offset 0
+ 177              		@ sp needed
+ 178 008a 7047     		bx	lr
+ 179              	.L8:
+ 180              		.align	2
+ 181              	.L7:
+ 182 008c 00380240 		.word	1073887232
+ 183 0090 FFFFF2EA 		.word	-353173505
+ 184 0094 10300024 		.word	603992080
+ 185              		.cfi_endproc
+ 186              	.LFE295:
+ 188              		.section	.text.LL_RCC_GetCECClockFreq,"ax",%progbits
+ 189              		.align	1
+ 190              		.global	LL_RCC_GetCECClockFreq
+ 191              		.syntax unified
+ 192              		.thumb
+ 193              		.thumb_func
+ 194              		.fpu fpv5-d16
+ 196              	LL_RCC_GetCECClockFreq:
+ 197              	.LVL2:
+ 198              	.LFB305:
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @}
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL_EF_Get_Freq
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses c
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         and different peripheral clocks available on the device.
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
+ARM GAS  /tmp/ccTMI75D.s 			page 82
+
+
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         or HSI_VALUE(**) multiplied/divided by the PLL factors.
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @note   (**) HSI_VALUE is a constant defined in this file (default value
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *              16 MHz) but the real value may vary depending on the variations
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *              in voltage and temperature.
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @note   (***) HSE_VALUE is a constant defined in this file (default value
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *               25 MHz), user has to ensure that HSE_VALUE is same as the real
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *               frequency of the crystal used. Otherwise, this function may
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *               have wrong result.
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @note   The result of this function could be incorrect when using fractional
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         value for HSE crystal.
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @note   This function can be used by the user application to compute the
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         baud-rate for the communication peripherals or configure other parameters.
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @{
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses c
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         must be called to update structure fields. Otherwise, any
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         configuration based on this function will be incorrect.
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks 
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval None
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Get SYSCLK frequency */
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* HCLK clock frequency */
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PCLK1 clock frequency */
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PCLK2 clock frequency */
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return USARTx clock frequency
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  USARTxSource This parameter can be one of the following values:
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval USART clock frequency (in Hz)
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ARM GAS  /tmp/ccTMI75D.s 			page 83
+
+
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* USART1CLK clock frequency */
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         usart_frequency = RCC_GetSystemClockFreq();
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_HSI_IsReady())
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           usart_frequency = HSI_VALUE;
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_LSE_IsReady())
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           usart_frequency = LSE_VALUE;
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART1_CLKSOURCE_PCLK2:  /* USART1 Clock is PCLK2 */
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* USART2CLK clock frequency */
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         usart_frequency = RCC_GetSystemClockFreq();
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_HSI_IsReady())
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           usart_frequency = HSI_VALUE;
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_LSE_IsReady())
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           usart_frequency = LSE_VALUE;
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else if (USARTxSource == LL_RCC_USART6_CLKSOURCE)
+ARM GAS  /tmp/ccTMI75D.s 			page 84
+
+
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* USART6CLK clock frequency */
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         usart_frequency = RCC_GetSystemClockFreq();
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART6_CLKSOURCE_HSI:    /* USART6 Clock is HSI Osc. */
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_HSI_IsReady())
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           usart_frequency = HSI_VALUE;
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART6_CLKSOURCE_LSE:    /* USART6 Clock is LSE Osc. */
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_LSE_IsReady())
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           usart_frequency = LSE_VALUE;
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_USART6_CLKSOURCE_PCLK2:  /* USART6 Clock is PCLK2 */
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       /* USART3CLK clock frequency */
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           usart_frequency = RCC_GetSystemClockFreq();
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_USART3_CLKSOURCE_HSI:    /* USART3 Clock is HSI Osc. */
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           if (LL_RCC_HSI_IsReady())
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             usart_frequency = HSI_VALUE;
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           }
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_USART3_CLKSOURCE_LSE:    /* USART3 Clock is LSE Osc. */
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           if (LL_RCC_LSE_IsReady())
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             usart_frequency = LSE_VALUE;
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           }
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_USART3_CLKSOURCE_PCLK1:  /* USART3 Clock is PCLK1 */
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         default:
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ARM GAS  /tmp/ccTMI75D.s 			page 85
+
+
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return usart_frequency;
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return UARTx clock frequency
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  UARTxSource This parameter can be one of the following values:
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval UART clock frequency (in Hz)
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* UART4CLK clock frequency */
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         uart_frequency = RCC_GetSystemClockFreq();
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART4_CLKSOURCE_HSI:    /* UART4 Clock is HSI Osc. */
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_HSI_IsReady())
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           uart_frequency = HSI_VALUE;
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART4_CLKSOURCE_LSE:    /* UART4 Clock is LSE Osc. */
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_LSE_IsReady())
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           uart_frequency = LSE_VALUE;
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART4_CLKSOURCE_PCLK1:  /* UART4 Clock is PCLK1 */
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* UART5CLK clock frequency */
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ARM GAS  /tmp/ccTMI75D.s 			page 86
+
+
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         uart_frequency = RCC_GetSystemClockFreq();
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART5_CLKSOURCE_HSI:    /* UART5 Clock is HSI Osc. */
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_HSI_IsReady())
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           uart_frequency = HSI_VALUE;
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART5_CLKSOURCE_LSE:    /* UART5 Clock is LSE Osc. */
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_LSE_IsReady())
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           uart_frequency = LSE_VALUE;
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART5_CLKSOURCE_PCLK1:  /* UART5 Clock is PCLK1 */
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else if (UARTxSource == LL_RCC_UART7_CLKSOURCE)
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* UART7CLK clock frequency */
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART7_CLKSOURCE_SYSCLK: /* UART7 Clock is System Clock */
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         uart_frequency = RCC_GetSystemClockFreq();
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART7_CLKSOURCE_HSI:    /* UART7 Clock is HSI Osc. */
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_HSI_IsReady())
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           uart_frequency = HSI_VALUE;
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART7_CLKSOURCE_LSE:    /* UART7 Clock is LSE Osc. */
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_LSE_IsReady())
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           uart_frequency = LSE_VALUE;
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_UART7_CLKSOURCE_PCLK1:  /* UART7 Clock is PCLK1 */
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     if (UARTxSource == LL_RCC_UART8_CLKSOURCE)
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ARM GAS  /tmp/ccTMI75D.s 			page 87
+
+
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       /* UART8CLK clock frequency */
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_UART8_CLKSOURCE_SYSCLK: /* UART8 Clock is System Clock */
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           uart_frequency = RCC_GetSystemClockFreq();
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_UART8_CLKSOURCE_HSI:    /* UART8 Clock is HSI Osc. */
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           if (LL_RCC_HSI_IsReady())
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             uart_frequency = HSI_VALUE;
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           }
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_UART8_CLKSOURCE_LSE:    /* UART8 Clock is LSE Osc. */
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           if (LL_RCC_LSE_IsReady())
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             uart_frequency = LSE_VALUE;
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           }
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_UART8_CLKSOURCE_PCLK1:  /* UART8 Clock is PCLK1 */
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         default:
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return uart_frequency;
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return I2Cx clock frequency
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  I2CxSource This parameter can be one of the following values:
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         (*) value not defined in all devices.
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval I2C clock frequency (in Hz)
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* I2C1 CLK clock frequency */
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         i2c_frequency = RCC_GetSystemClockFreq();
+ARM GAS  /tmp/ccTMI75D.s 			page 88
+
+
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_HSI_IsReady())
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           i2c_frequency = HSI_VALUE;
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* I2C2 CLK clock frequency */
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         i2c_frequency = RCC_GetSystemClockFreq();
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_I2C2_CLKSOURCE_HSI:    /* I2C2 Clock is HSI Osc. */
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_HSI_IsReady())
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           i2c_frequency = HSI_VALUE;
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_I2C2_CLKSOURCE_PCLK1:  /* I2C2 Clock is PCLK1 */
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* I2C3 CLK clock frequency */
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         i2c_frequency = RCC_GetSystemClockFreq();
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_I2C3_CLKSOURCE_HSI:    /* I2C3 Clock is HSI Osc. */
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_HSI_IsReady())
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           i2c_frequency = HSI_VALUE;
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_I2C3_CLKSOURCE_PCLK1:  /* I2C3 Clock is PCLK1 */
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ARM GAS  /tmp/ccTMI75D.s 			page 89
+
+
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(I2C4)
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       /* I2C4 CLK clock frequency */
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           i2c_frequency = RCC_GetSystemClockFreq();
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_I2C4_CLKSOURCE_HSI:    /* I2C4 Clock is HSI Osc. */
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           if (LL_RCC_HSI_IsReady())
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             i2c_frequency = HSI_VALUE;
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           }
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_I2C4_CLKSOURCE_PCLK1:  /* I2C4 Clock is PCLK1 */
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         default:
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #else
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* Nothing to do */
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* I2C4 */
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return i2c_frequency;
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return I2Sx clock frequency
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  I2SxSource This parameter can be one of the following values:
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_I2S1_CLKSOURCE
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval I2S clock frequency (in Hz)
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLLI2S oscillator is not ready
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* I2S1 CLK clock frequency */
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetI2SClockSource(I2SxSource))
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ARM GAS  /tmp/ccTMI75D.s 			page 90
+
+
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_I2S1_CLKSOURCE_PLLI2S:       /* I2S1 Clock is PLLI2S */
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_PLLI2S_IsReady())
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_I2S1_CLKSOURCE_PIN:          /* I2S1 Clock is External clock */
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         i2s_frequency = EXTERNAL_CLOCK_VALUE;
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return i2s_frequency;
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return LPTIMx clock frequency
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  LPTIMxSource This parameter can be one of the following values:
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval LPTIM clock frequency (in Hz)
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not r
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* LPTIM1CLK clock frequency */
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_LSI_IsReady())
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           lptim_frequency = LSI_VALUE;
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_HSI_IsReady())
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           lptim_frequency = HSI_VALUE;
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_LSE_IsReady())
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           lptim_frequency = LSE_VALUE;
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ARM GAS  /tmp/ccTMI75D.s 			page 91
+
+
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return lptim_frequency;
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return SAIx clock frequency
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  SAIxSource This parameter can be one of the following values:
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval SAI clock frequency (in Hz)
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* SAI1CLK clock frequency */
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetSAIClockSource(SAIxSource))
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_SAI1_CLKSOURCE_PLLSAI:    /* PLLSAI clock used as SAI1 clock source */
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_PLLSAI_IsReady())
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_SAI1_CLKSOURCE_PLLI2S:    /* PLLI2S clock used as SAI1 clock source */
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_PLLI2S_IsReady())
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_SAI1_CLKSOURCE_PLLSRC:
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         switch (LL_RCC_PLL_GetMainSource())
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****            case LL_RCC_PLLSOURCE_HSE:       /* HSE clock used as SAI1 clock source */
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              if (LL_RCC_HSE_IsReady())
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                sai_frequency = HSE_VALUE;
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              break;
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****            case LL_RCC_PLLSOURCE_HSI:       /* HSI clock used as SAI1 clock source */
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****            default:
+ARM GAS  /tmp/ccTMI75D.s 			page 92
+
+
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              if (LL_RCC_HSI_IsReady())
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                sai_frequency = HSI_VALUE;
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              break;
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_SAI1_CLKSOURCE_PIN:        /* External input clock used as SAI1 clock source */
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       /* SAI2CLK clock frequency */
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       switch (LL_RCC_GetSAIClockSource(SAIxSource))
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_SAI2_CLKSOURCE_PLLSAI:    /* PLLSAI clock used as SAI2 clock source */
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_PLLSAI_IsReady())
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_SAI2_CLKSOURCE_PLLI2S:    /* PLLI2S clock used as SAI2 clock source */
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         if (LL_RCC_PLLI2S_IsReady())
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         switch (LL_RCC_PLL_GetMainSource())
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****            case LL_RCC_PLLSOURCE_HSE:       /* HSE clock used as SAI2 clock source */
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              if (LL_RCC_HSE_IsReady())
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                sai_frequency = HSE_VALUE;
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              break;
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****            case LL_RCC_PLLSOURCE_HSI:       /* HSI clock used as SAI2 clock source */
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****            default:
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              if (LL_RCC_HSI_IsReady())
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                sai_frequency = HSI_VALUE;
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              break;
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ARM GAS  /tmp/ccTMI75D.s 			page 93
+
+
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         case LL_RCC_SAI2_CLKSOURCE_PIN:      /* External input clock used as SAI2 clock source */
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return sai_frequency;
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return SDMMCx clock frequency
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  SDMMCxSource This parameter can be one of the following values:
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         (*) value not defined in all devices.
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval SDMMC clock frequency (in Hz)
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLL is not ready
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE)
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     /* SDMMC1CLK clock frequency */
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK:        /* PLL48 clock used as SDMMC1 clock source */
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           case LL_RCC_CK48M_CLKSOURCE_PLL:         /* PLL clock used as 48Mhz domain clock */
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             if (LL_RCC_PLL_IsReady())
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             {
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****               sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             }
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           case LL_RCC_CK48M_CLKSOURCE_PLLSAI:      /* PLLSAI clock used as 48Mhz domain clock */
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           default:
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             if (LL_RCC_PLLSAI_IsReady())
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             {
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****               sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             }
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             break;
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       case LL_RCC_SDMMC1_CLKSOURCE_SYSCLK:        /* PLL clock used as SDMMC1 clock source */
+ARM GAS  /tmp/ccTMI75D.s 			page 94
+
+
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       default:
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       sdmmc_frequency = RCC_GetSystemClockFreq();
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SDMMC2)
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   else
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      /* SDMMC2CLK clock frequency */
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      {
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****        case LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK:        /* PLL48 clock used as SDMMC2 clock source */
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****          switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****          {
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****            case LL_RCC_CK48M_CLKSOURCE_PLL:         /* PLL clock used as 48Mhz domain clock */
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              if (LL_RCC_PLL_IsReady())
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****            break;
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****            case LL_RCC_CK48M_CLKSOURCE_PLLSAI:      /* PLLSAI clock used as 48Mhz domain clock */
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****            default:
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              if (LL_RCC_PLLSAI_IsReady())
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              break;
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****          }
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****          break;
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****        case LL_RCC_SDMMC2_CLKSOURCE_SYSCLK:        /* PLL clock used as SDMMC2 clock source */
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****        default:
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****        sdmmc_frequency = RCC_GetSystemClockFreq();
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****        break;
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      }
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SDMMC2 */
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return sdmmc_frequency;
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return RNGx clock frequency
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  RNGxSource This parameter can be one of the following values:
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_RNG_CLKSOURCE
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval RNG clock frequency (in Hz)
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* RNGCLK clock frequency */
+ARM GAS  /tmp/ccTMI75D.s 			page 95
+
+
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (LL_RCC_GetRNGClockSource(RNGxSource))
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_RNG_CLKSOURCE_PLL:           /* PLL clock used as RNG clock source */
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       if (LL_RCC_PLL_IsReady())
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         rng_frequency = RCC_PLL_GetFreqDomain_48M();
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_RNG_CLKSOURCE_PLLSAI:       /* PLLSAI clock used as RNG clock source */
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       if (LL_RCC_PLLSAI_IsReady())
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return rng_frequency;
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(CEC)
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return CEC clock frequency
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  CECxSource This parameter can be one of the following values:
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_CEC_CLKSOURCE
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval CEC clock frequency (in Hz)
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 199              		.loc 1 1005 1 is_stmt 1 view -0
+ 200              		.cfi_startproc
+ 201              		@ args = 0, pretend = 0, frame = 0
+ 202              		@ frame_needed = 0, uses_anonymous_args = 0
+ 203              		@ link register save eliminated.
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 204              		.loc 1 1006 3 view .LVU49
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
+ 205              		.loc 1 1009 3 view .LVU50
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* CECCLK clock frequency */
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (LL_RCC_GetCECClockSource(CECxSource))
+ 206              		.loc 1 1012 3 view .LVU51
+ 207              	.LBB246:
+ 208              	.LBI246:
+2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 209              		.loc 2 2847 26 view .LVU52
+ 210              	.LBB247:
+2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 211              		.loc 2 2849 3 view .LVU53
+2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 212              		.loc 2 2849 21 is_stmt 0 view .LVU54
+ 213 0000 0A4B     		ldr	r3, .L15
+ 214 0002 D3F89030 		ldr	r3, [r3, #144]
+ARM GAS  /tmp/ccTMI75D.s 			page 96
+
+
+ 215              	.LVL3:
+2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 216              		.loc 2 2849 21 view .LVU55
+ 217              	.LBE247:
+ 218              	.LBE246:
+ 219              		.loc 1 1012 3 view .LVU56
+ 220 0006 1842     		tst	r0, r3
+ 221 0008 05D1     		bne	.L10
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_CEC_CLKSOURCE_LSE:           /* CEC Clock is LSE Osc. */
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       if (LL_RCC_LSE_IsReady())
+ 222              		.loc 1 1015 7 is_stmt 1 view .LVU57
+ 223              	.LBB248:
+ 224              	.LBI248:
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 225              		.loc 2 2154 26 view .LVU58
+ 226              	.LBB249:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 227              		.loc 2 2156 3 view .LVU59
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 228              		.loc 2 2156 11 is_stmt 0 view .LVU60
+ 229 000a 084B     		ldr	r3, .L15
+ 230 000c 186F     		ldr	r0, [r3, #112]
+ 231              	.LVL4:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 232              		.loc 2 2156 11 view .LVU61
+ 233              	.LBE249:
+ 234              	.LBE248:
+ 235              		.loc 1 1015 10 view .LVU62
+ 236 000e 10F00200 		ands	r0, r0, #2
+ 237 0012 08D1     		bne	.L14
+ 238              	.LVL5:
+ 239              	.L9:
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         cec_frequency = LSE_VALUE;
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_CEC_CLKSOURCE_HSI_DIV488:    /* CEC Clock is HSI Osc. */
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       if (LL_RCC_HSI_IsReady())
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         cec_frequency = HSI_VALUE/488U;
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return cec_frequency;
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 240              		.loc 1 1031 1 view .LVU63
+ 241 0014 7047     		bx	lr
+ 242              	.LVL6:
+ 243              	.L10:
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 244              		.loc 1 1023 7 is_stmt 1 view .LVU64
+ 245              	.LBB250:
+ 246              	.LBI250:
+ARM GAS  /tmp/ccTMI75D.s 			page 97
+
+
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 247              		.loc 2 2030 26 view .LVU65
+ 248              	.LBB251:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 249              		.loc 2 2032 3 view .LVU66
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 250              		.loc 2 2032 11 is_stmt 0 view .LVU67
+ 251 0016 054B     		ldr	r3, .L15
+ 252 0018 1868     		ldr	r0, [r3]
+ 253              	.LVL7:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 254              		.loc 2 2032 11 view .LVU68
+ 255              	.LBE251:
+ 256              	.LBE250:
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 257              		.loc 1 1023 10 view .LVU69
+ 258 001a 10F00200 		ands	r0, r0, #2
+ 259 001e F9D0     		beq	.L9
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 260              		.loc 1 1025 23 view .LVU70
+ 261 0020 48F21200 		movw	r0, #32786
+ 262              	.LVL8:
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 263              		.loc 1 1030 3 is_stmt 1 view .LVU71
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 264              		.loc 1 1030 10 is_stmt 0 view .LVU72
+ 265 0024 F6E7     		b	.L9
+ 266              	.LVL9:
+ 267              	.L14:
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 268              		.loc 1 1017 23 view .LVU73
+ 269 0026 4FF40040 		mov	r0, #32768
+ 270 002a 7047     		bx	lr
+ 271              	.L16:
+ 272              		.align	2
+ 273              	.L15:
+ 274 002c 00380240 		.word	1073887232
+ 275              		.cfi_endproc
+ 276              	.LFE305:
+ 278              		.section	.text.RCC_GetHCLKClockFreq,"ax",%progbits
+ 279              		.align	1
+ 280              		.global	RCC_GetHCLKClockFreq
+ 281              		.syntax unified
+ 282              		.thumb
+ 283              		.thumb_func
+ 284              		.fpu fpv5-d16
+ 286              	RCC_GetHCLKClockFreq:
+ 287              	.LVL10:
+ 288              	.LFB312:
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* CEC */
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return USBx clock frequency
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  USBxSource This parameter can be one of the following values:
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_USB_CLKSOURCE
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval USB clock frequency (in Hz)
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+ARM GAS  /tmp/ccTMI75D.s 			page 98
+
+
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* USBCLK clock frequency */
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (LL_RCC_GetUSBClockSource(USBxSource))
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_USB_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       if (LL_RCC_PLL_IsReady())
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         usb_frequency = RCC_PLL_GetFreqDomain_48M();
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_USB_CLKSOURCE_PLLSAI:       /* PLLSAI clock used as USB clock source */
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       if (LL_RCC_PLLSAI_IsReady())
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return usb_frequency;
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DFSDM1_Channel0)
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return DFSDMx clock frequency
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  DFSDMxSource This parameter can be one of the following values:
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval DFSDM clock frequency (in Hz)
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* DFSDM1CLK clock frequency */
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:     /* DFSDM1 Clock is SYSCLK */
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       dfsdm_frequency = RCC_GetSystemClockFreq();
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:      /* DFSDM1 Clock is PCLK2 */
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return dfsdm_frequency;
+ARM GAS  /tmp/ccTMI75D.s 			page 99
+
+
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return DFSDMx Audio clock frequency
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  DFSDMxSource This parameter can be one of the following values:
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval DFSDM clock frequency (in Hz)
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* DFSDM1CLK clock frequency */
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1:     /* SAI1 clock used as DFSDM1 audio clock */
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2:     /* SAI2 clock used as DFSDM1 audio clock */
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE);
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return dfsdm_frequency;
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DFSDM1_Channel0 */
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DSI)
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return DSI clock frequency
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  DSIxSource This parameter can be one of the following values:
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_DSI_CLKSOURCE
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval DSI clock frequency (in Hz)
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* DSICLK clock frequency */
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (LL_RCC_GetDSIClockSource(DSIxSource))
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_DSI_CLKSOURCE_PLL:     /* DSI Clock is PLL Osc. */
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       if (LL_RCC_PLL_IsReady())
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ARM GAS  /tmp/ccTMI75D.s 			page 100
+
+
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_DSI_CLKSOURCE_PHY:    /* DSI Clock is DSI physical clock. */
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return dsi_frequency;
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DSI */
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(LTDC)
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return LTDC clock frequency
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  LTDCxSource This parameter can be one of the following values:
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_LTDC_CLKSOURCE
+1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval LTDC clock frequency (in Hz)
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   if (LL_RCC_PLLSAI_IsReady())
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return ltdc_frequency;
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* LTDC */
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SPDIFRX)
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return SPDIFRX clock frequency
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  SPDIFRXxSource This parameter can be one of the following values:
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval SPDIFRX clock frequency (in Hz)
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Check parameter */
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   if (LL_RCC_PLLI2S_IsReady())
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return spdifrx_frequency;
+ARM GAS  /tmp/ccTMI75D.s 			page 101
+
+
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SPDIFRX */
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @}
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @}
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL_Private_Functions
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @{
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return SYSTEM clock frequency
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval SYSTEM clock frequency (in Hz)
+1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetSystemClockFreq(void)
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t frequency = 0U;
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Get SYSCLK source -------------------------------------------------------*/
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (LL_RCC_GetSysClkSource())
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       frequency = HSI_VALUE;
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       frequency = HSE_VALUE;
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       frequency = RCC_PLL_GetFreqDomain_SYS();
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       frequency = HSI_VALUE;
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return frequency;
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return HCLK clock frequency
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  SYSCLK_Frequency SYSCLK clock frequency
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval HCLK clock frequency (in Hz)
+1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 289              		.loc 1 1263 1 is_stmt 1 view -0
+ 290              		.cfi_startproc
+ 291              		@ args = 0, pretend = 0, frame = 0
+ 292              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccTMI75D.s 			page 102
+
+
+ 293              		@ link register save eliminated.
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* HCLK clock frequency */
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+ 294              		.loc 1 1265 3 view .LVU75
+ 295              	.LBB252:
+ 296              	.LBI252:
+2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 297              		.loc 2 2298 26 view .LVU76
+ 298              	.LBB253:
+2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 299              		.loc 2 2300 3 view .LVU77
+2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 300              		.loc 2 2300 21 is_stmt 0 view .LVU78
+ 301 0000 034B     		ldr	r3, .L18
+ 302 0002 9B68     		ldr	r3, [r3, #8]
+ 303              	.LBE253:
+ 304              	.LBE252:
+ 305              		.loc 1 1265 10 view .LVU79
+ 306 0004 C3F30313 		ubfx	r3, r3, #4, #4
+ 307 0008 024A     		ldr	r2, .L18+4
+ 308 000a D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 309              		.loc 1 1266 1 view .LVU80
+ 310 000c D840     		lsrs	r0, r0, r3
+ 311              	.LVL11:
+ 312              		.loc 1 1266 1 view .LVU81
+ 313 000e 7047     		bx	lr
+ 314              	.L19:
+ 315              		.align	2
+ 316              	.L18:
+ 317 0010 00380240 		.word	1073887232
+ 318 0014 00000000 		.word	AHBPrescTable
+ 319              		.cfi_endproc
+ 320              	.LFE312:
+ 322              		.section	.text.RCC_GetPCLK1ClockFreq,"ax",%progbits
+ 323              		.align	1
+ 324              		.global	RCC_GetPCLK1ClockFreq
+ 325              		.syntax unified
+ 326              		.thumb
+ 327              		.thumb_func
+ 328              		.fpu fpv5-d16
+ 330              	RCC_GetPCLK1ClockFreq:
+ 331              	.LVL12:
+ 332              	.LFB313:
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return PCLK1 clock frequency
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  HCLK_Frequency HCLK clock frequency
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval PCLK1 clock frequency (in Hz)
+1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 333              		.loc 1 1274 1 is_stmt 1 view -0
+ 334              		.cfi_startproc
+ 335              		@ args = 0, pretend = 0, frame = 0
+ 336              		@ frame_needed = 0, uses_anonymous_args = 0
+ 337              		@ link register save eliminated.
+ARM GAS  /tmp/ccTMI75D.s 			page 103
+
+
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PCLK1 clock frequency */
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+ 338              		.loc 1 1276 3 view .LVU83
+ 339              	.LBB254:
+ 340              	.LBI254:
+2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 341              		.loc 2 2313 26 view .LVU84
+ 342              	.LBB255:
+2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 343              		.loc 2 2315 3 view .LVU85
+2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 344              		.loc 2 2315 21 is_stmt 0 view .LVU86
+ 345 0000 034B     		ldr	r3, .L21
+ 346 0002 9B68     		ldr	r3, [r3, #8]
+ 347              	.LBE255:
+ 348              	.LBE254:
+ 349              		.loc 1 1276 10 view .LVU87
+ 350 0004 C3F38223 		ubfx	r3, r3, #10, #3
+ 351 0008 024A     		ldr	r2, .L21+4
+ 352 000a D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 353              		.loc 1 1277 1 view .LVU88
+ 354 000c D840     		lsrs	r0, r0, r3
+ 355              	.LVL13:
+ 356              		.loc 1 1277 1 view .LVU89
+ 357 000e 7047     		bx	lr
+ 358              	.L22:
+ 359              		.align	2
+ 360              	.L21:
+ 361 0010 00380240 		.word	1073887232
+ 362 0014 00000000 		.word	APBPrescTable
+ 363              		.cfi_endproc
+ 364              	.LFE313:
+ 366              		.section	.text.RCC_GetPCLK2ClockFreq,"ax",%progbits
+ 367              		.align	1
+ 368              		.global	RCC_GetPCLK2ClockFreq
+ 369              		.syntax unified
+ 370              		.thumb
+ 371              		.thumb_func
+ 372              		.fpu fpv5-d16
+ 374              	RCC_GetPCLK2ClockFreq:
+ 375              	.LVL14:
+ 376              	.LFB314:
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return PCLK2 clock frequency
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @param  HCLK_Frequency HCLK clock frequency
+1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval PCLK2 clock frequency (in Hz)
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 377              		.loc 1 1285 1 is_stmt 1 view -0
+ 378              		.cfi_startproc
+ 379              		@ args = 0, pretend = 0, frame = 0
+ 380              		@ frame_needed = 0, uses_anonymous_args = 0
+ 381              		@ link register save eliminated.
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PCLK2 clock frequency */
+ARM GAS  /tmp/ccTMI75D.s 			page 104
+
+
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+ 382              		.loc 1 1287 3 view .LVU91
+ 383              	.LBB256:
+ 384              	.LBI256:
+2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 385              		.loc 2 2328 26 view .LVU92
+ 386              	.LBB257:
+2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 387              		.loc 2 2330 3 view .LVU93
+2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 388              		.loc 2 2330 21 is_stmt 0 view .LVU94
+ 389 0000 034B     		ldr	r3, .L24
+ 390 0002 9B68     		ldr	r3, [r3, #8]
+ 391              	.LBE257:
+ 392              	.LBE256:
+ 393              		.loc 1 1287 10 view .LVU95
+ 394 0004 C3F34233 		ubfx	r3, r3, #13, #3
+ 395 0008 024A     		ldr	r2, .L24+4
+ 396 000a D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 397              		.loc 1 1288 1 view .LVU96
+ 398 000c D840     		lsrs	r0, r0, r3
+ 399              	.LVL15:
+ 400              		.loc 1 1288 1 view .LVU97
+ 401 000e 7047     		bx	lr
+ 402              	.L25:
+ 403              		.align	2
+ 404              	.L24:
+ 405 0010 00380240 		.word	1073887232
+ 406 0014 00000000 		.word	APBPrescTable
+ 407              		.cfi_endproc
+ 408              	.LFE314:
+ 410              		.section	.text.RCC_PLL_GetFreqDomain_SYS,"ax",%progbits
+ 411              		.align	1
+ 412              		.global	RCC_PLL_GetFreqDomain_SYS
+ 413              		.syntax unified
+ 414              		.thumb
+ 415              		.thumb_func
+ 416              		.fpu fpv5-d16
+ 418              	RCC_PLL_GetFreqDomain_SYS:
+ 419              	.LFB315:
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return PLL clock frequency used for system domain
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval PLL clock frequency (in Hz)
+1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 420              		.loc 1 1295 1 is_stmt 1 view -0
+ 421              		.cfi_startproc
+ 422              		@ args = 0, pretend = 0, frame = 0
+ 423              		@ frame_needed = 0, uses_anonymous_args = 0
+ 424              		@ link register save eliminated.
+1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t pllinputfreq = 0U, pllsource = 0U;
+ 425              		.loc 1 1296 3 view .LVU99
+ 426              	.LVL16:
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ARM GAS  /tmp/ccTMI75D.s 			page 105
+
+
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      SYSCLK = PLL_VCO / PLLP
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   pllsource = LL_RCC_PLL_GetMainSource();
+ 427              		.loc 1 1301 3 view .LVU100
+ 428              	.LBB258:
+ 429              	.LBI258:
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 430              		.loc 2 3461 26 view .LVU101
+ 431              	.LBB259:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 432              		.loc 2 3463 3 view .LVU102
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 433              		.loc 2 3463 21 is_stmt 0 view .LVU103
+ 434 0000 0D4B     		ldr	r3, .L29
+ 435 0002 5B68     		ldr	r3, [r3, #4]
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 436              		.loc 2 3463 10 view .LVU104
+ 437 0004 03F48003 		and	r3, r3, #4194304
+ 438              	.LVL17:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 439              		.loc 2 3463 10 view .LVU105
+ 440              	.LBE259:
+ 441              	.LBE258:
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (pllsource)
+ 442              		.loc 1 1303 3 is_stmt 1 view .LVU106
+ 443 0008 9BB9     		cbnz	r3, .L28
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+ 444              		.loc 1 1306 20 is_stmt 0 view .LVU107
+ 445 000a 0C48     		ldr	r0, .L29+4
+ 446              	.L27:
+ 447              	.LVL18:
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSE_VALUE;
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ 448              		.loc 1 1317 3 is_stmt 1 view .LVU108
+ 449              	.LBB260:
+ 450              	.LBI260:
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 451              		.loc 2 3601 26 view .LVU109
+ 452              	.LBB261:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 453              		.loc 2 3603 3 view .LVU110
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 454              		.loc 2 3603 21 is_stmt 0 view .LVU111
+ 455 000c 0A4B     		ldr	r3, .L29
+ARM GAS  /tmp/ccTMI75D.s 			page 106
+
+
+ 456              	.LVL19:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 457              		.loc 2 3603 21 view .LVU112
+ 458 000e 5A68     		ldr	r2, [r3, #4]
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 459              		.loc 2 3603 10 view .LVU113
+ 460 0010 02F03F02 		and	r2, r2, #63
+ 461              	.LBE261:
+ 462              	.LBE260:
+ 463              		.loc 1 1317 10 view .LVU114
+ 464 0014 B0FBF2F0 		udiv	r0, r0, r2
+ 465              	.LVL20:
+ 466              	.LBB262:
+ 467              	.LBI262:
+3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 468              		.loc 2 3471 26 is_stmt 1 view .LVU115
+ 469              	.LBB263:
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 470              		.loc 2 3473 3 view .LVU116
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 471              		.loc 2 3473 21 is_stmt 0 view .LVU117
+ 472 0018 5A68     		ldr	r2, [r3, #4]
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 473              		.loc 2 3473 10 view .LVU118
+ 474 001a C2F38812 		ubfx	r2, r2, #6, #9
+ 475              	.LBE263:
+ 476              	.LBE262:
+ 477              		.loc 1 1317 10 view .LVU119
+ 478 001e 02FB00F0 		mul	r0, r2, r0
+ 479              	.LBB264:
+ 480              	.LBI264:
+3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 481              		.loc 2 3485 26 is_stmt 1 view .LVU120
+ 482              	.LBB265:
+3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 483              		.loc 2 3487 3 view .LVU121
+3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 484              		.loc 2 3487 21 is_stmt 0 view .LVU122
+ 485 0022 5B68     		ldr	r3, [r3, #4]
+ 486              	.LBE265:
+ 487              	.LBE264:
+ 488              		.loc 1 1317 10 view .LVU123
+ 489 0024 C3F30143 		ubfx	r3, r3, #16, #2
+ 490 0028 0133     		adds	r3, r3, #1
+ 491 002a 5B00     		lsls	r3, r3, #1
+1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 492              		.loc 1 1319 1 view .LVU124
+ 493 002c B0FBF3F0 		udiv	r0, r0, r3
+ 494 0030 7047     		bx	lr
+ 495              	.LVL21:
+ 496              	.L28:
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 497              		.loc 1 1310 20 view .LVU125
+ 498 0032 0348     		ldr	r0, .L29+8
+ 499 0034 EAE7     		b	.L27
+ 500              	.L30:
+ARM GAS  /tmp/ccTMI75D.s 			page 107
+
+
+ 501 0036 00BF     		.align	2
+ 502              	.L29:
+ 503 0038 00380240 		.word	1073887232
+ 504 003c 0024F400 		.word	16000000
+ 505 0040 40787D01 		.word	25000000
+ 506              		.cfi_endproc
+ 507              	.LFE315:
+ 509              		.section	.text.RCC_GetSystemClockFreq,"ax",%progbits
+ 510              		.align	1
+ 511              		.global	RCC_GetSystemClockFreq
+ 512              		.syntax unified
+ 513              		.thumb
+ 514              		.thumb_func
+ 515              		.fpu fpv5-d16
+ 517              	RCC_GetSystemClockFreq:
+ 518              	.LFB311:
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t frequency = 0U;
+ 519              		.loc 1 1231 1 is_stmt 1 view -0
+ 520              		.cfi_startproc
+ 521              		@ args = 0, pretend = 0, frame = 0
+ 522              		@ frame_needed = 0, uses_anonymous_args = 0
+ 523 0000 08B5     		push	{r3, lr}
+ 524              	.LCFI2:
+ 525              		.cfi_def_cfa_offset 8
+ 526              		.cfi_offset 3, -8
+ 527              		.cfi_offset 14, -4
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 528              		.loc 1 1232 3 view .LVU127
+ 529              	.LVL22:
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 530              		.loc 1 1235 3 view .LVU128
+ 531              	.LBB266:
+ 532              	.LBI266:
+2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 533              		.loc 2 2227 26 view .LVU129
+ 534              	.LBB267:
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 535              		.loc 2 2229 3 view .LVU130
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 536              		.loc 2 2229 21 is_stmt 0 view .LVU131
+ 537 0002 074B     		ldr	r3, .L36
+ 538 0004 9B68     		ldr	r3, [r3, #8]
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 539              		.loc 2 2229 10 view .LVU132
+ 540 0006 03F00C03 		and	r3, r3, #12
+ 541              	.LBE267:
+ 542              	.LBE266:
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 543              		.loc 1 1235 3 view .LVU133
+ 544 000a 042B     		cmp	r3, #4
+ 545 000c 04D0     		beq	.L33
+ 546 000e 082B     		cmp	r3, #8
+ 547 0010 04D1     		bne	.L34
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 548              		.loc 1 1246 7 is_stmt 1 view .LVU134
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 549              		.loc 1 1246 19 is_stmt 0 view .LVU135
+ARM GAS  /tmp/ccTMI75D.s 			page 108
+
+
+ 550 0012 FFF7FEFF 		bl	RCC_PLL_GetFreqDomain_SYS
+ 551              	.LVL23:
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 552              		.loc 1 1247 7 is_stmt 1 view .LVU136
+ 553 0016 02E0     		b	.L31
+ 554              	.LVL24:
+ 555              	.L33:
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 556              		.loc 1 1242 17 is_stmt 0 view .LVU137
+ 557 0018 0248     		ldr	r0, .L36+4
+ 558 001a 00E0     		b	.L31
+ 559              	.L34:
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 560              		.loc 1 1235 3 view .LVU138
+ 561 001c 0248     		ldr	r0, .L36+8
+ 562              	.LVL25:
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 563              		.loc 1 1254 3 is_stmt 1 view .LVU139
+ 564              	.L31:
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 565              		.loc 1 1255 1 is_stmt 0 view .LVU140
+ 566 001e 08BD     		pop	{r3, pc}
+ 567              	.L37:
+ 568              		.align	2
+ 569              	.L36:
+ 570 0020 00380240 		.word	1073887232
+ 571 0024 40787D01 		.word	25000000
+ 572 0028 0024F400 		.word	16000000
+ 573              		.cfi_endproc
+ 574              	.LFE311:
+ 576              		.section	.text.LL_RCC_GetSystemClocksFreq,"ax",%progbits
+ 577              		.align	1
+ 578              		.global	LL_RCC_GetSystemClocksFreq
+ 579              		.syntax unified
+ 580              		.thumb
+ 581              		.thumb_func
+ 582              		.fpu fpv5-d16
+ 584              	LL_RCC_GetSystemClocksFreq:
+ 585              	.LVL26:
+ 586              	.LFB296:
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Get SYSCLK frequency */
+ 587              		.loc 1 258 1 is_stmt 1 view -0
+ 588              		.cfi_startproc
+ 589              		@ args = 0, pretend = 0, frame = 0
+ 590              		@ frame_needed = 0, uses_anonymous_args = 0
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* Get SYSCLK frequency */
+ 591              		.loc 1 258 1 is_stmt 0 view .LVU142
+ 592 0000 10B5     		push	{r4, lr}
+ 593              	.LCFI3:
+ 594              		.cfi_def_cfa_offset 8
+ 595              		.cfi_offset 4, -8
+ 596              		.cfi_offset 14, -4
+ 597 0002 0446     		mov	r4, r0
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 598              		.loc 1 260 3 is_stmt 1 view .LVU143
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 599              		.loc 1 260 34 is_stmt 0 view .LVU144
+ARM GAS  /tmp/ccTMI75D.s 			page 109
+
+
+ 600 0004 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 601              	.LVL27:
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 602              		.loc 1 260 32 view .LVU145
+ 603 0008 2060     		str	r0, [r4]
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 604              		.loc 1 263 3 is_stmt 1 view .LVU146
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 605              		.loc 1 263 34 is_stmt 0 view .LVU147
+ 606 000a FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 607              	.LVL28:
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 608              		.loc 1 263 32 view .LVU148
+ 609 000e 6060     		str	r0, [r4, #4]
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 610              		.loc 1 266 3 is_stmt 1 view .LVU149
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 611              		.loc 1 266 34 is_stmt 0 view .LVU150
+ 612 0010 FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 613              	.LVL29:
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 614              		.loc 1 266 32 view .LVU151
+ 615 0014 A060     		str	r0, [r4, #8]
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 616              		.loc 1 269 3 is_stmt 1 view .LVU152
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 617              		.loc 1 269 34 is_stmt 0 view .LVU153
+ 618 0016 6068     		ldr	r0, [r4, #4]
+ 619 0018 FFF7FEFF 		bl	RCC_GetPCLK2ClockFreq
+ 620              	.LVL30:
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 621              		.loc 1 269 32 view .LVU154
+ 622 001c E060     		str	r0, [r4, #12]
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 623              		.loc 1 270 1 view .LVU155
+ 624 001e 10BD     		pop	{r4, pc}
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 625              		.loc 1 270 1 view .LVU156
+ 626              		.cfi_endproc
+ 627              	.LFE296:
+ 629              		.section	.text.LL_RCC_GetUSARTClockFreq,"ax",%progbits
+ 630              		.align	1
+ 631              		.global	LL_RCC_GetUSARTClockFreq
+ 632              		.syntax unified
+ 633              		.thumb
+ 634              		.thumb_func
+ 635              		.fpu fpv5-d16
+ 637              	LL_RCC_GetUSARTClockFreq:
+ 638              	.LVL31:
+ 639              	.LFB297:
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 640              		.loc 1 283 1 is_stmt 1 view -0
+ 641              		.cfi_startproc
+ 642              		@ args = 0, pretend = 0, frame = 0
+ 643              		@ frame_needed = 0, uses_anonymous_args = 0
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 644              		.loc 1 283 1 is_stmt 0 view .LVU158
+ARM GAS  /tmp/ccTMI75D.s 			page 110
+
+
+ 645 0000 08B5     		push	{r3, lr}
+ 646              	.LCFI4:
+ 647              		.cfi_def_cfa_offset 8
+ 648              		.cfi_offset 3, -8
+ 649              		.cfi_offset 14, -4
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 650              		.loc 1 284 3 is_stmt 1 view .LVU159
+ 651              	.LVL32:
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 652              		.loc 1 287 3 view .LVU160
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 653              		.loc 1 289 3 view .LVU161
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 654              		.loc 1 289 6 is_stmt 0 view .LVU162
+ 655 0002 0328     		cmp	r0, #3
+ 656 0004 08D0     		beq	.L67
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 657              		.loc 1 318 8 is_stmt 1 view .LVU163
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 658              		.loc 1 318 11 is_stmt 0 view .LVU164
+ 659 0006 0C28     		cmp	r0, #12
+ 660 0008 2ED0     		beq	.L68
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 661              		.loc 1 347 8 is_stmt 1 view .LVU165
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 662              		.loc 1 347 11 is_stmt 0 view .LVU166
+ 663 000a B0F5406F 		cmp	r0, #3072
+ 664 000e 53D0     		beq	.L69
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 665              		.loc 1 378 5 is_stmt 1 view .LVU167
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 666              		.loc 1 378 8 is_stmt 0 view .LVU168
+ 667 0010 3028     		cmp	r0, #48
+ 668 0012 7AD0     		beq	.L70
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 669              		.loc 1 284 12 view .LVU169
+ 670 0014 0020     		movs	r0, #0
+ 671              	.LVL33:
+ 672              	.L40:
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 673              		.loc 1 409 1 view .LVU170
+ 674 0016 08BD     		pop	{r3, pc}
+ 675              	.LVL34:
+ 676              	.L67:
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 677              		.loc 1 292 5 is_stmt 1 view .LVU171
+ 678              	.LBB268:
+ 679              	.LBI268:
+2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 680              		.loc 2 2664 26 view .LVU172
+ 681              	.LBB269:
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 682              		.loc 2 2666 3 view .LVU173
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 683              		.loc 2 2666 21 is_stmt 0 view .LVU174
+ 684 0018 514B     		ldr	r3, .L75
+ 685 001a D3F89030 		ldr	r3, [r3, #144]
+ARM GAS  /tmp/ccTMI75D.s 			page 111
+
+
+ 686 001e 0340     		ands	r3, r3, r0
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 687              		.loc 2 2666 10 view .LVU175
+ 688 0020 43EA0040 		orr	r0, r3, r0, lsl #16
+ 689              	.LVL35:
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 690              		.loc 2 2666 10 view .LVU176
+ 691              	.LBE269:
+ 692              	.LBE268:
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 693              		.loc 1 292 5 view .LVU177
+ 694 0024 4F4B     		ldr	r3, .L75+4
+ 695 0026 9842     		cmp	r0, r3
+ 696 0028 0FD0     		beq	.L42
+ 697 002a B0F1031F 		cmp	r0, #196611
+ 698 002e 13D0     		beq	.L43
+ 699 0030 013B     		subs	r3, r3, #1
+ 700 0032 9842     		cmp	r0, r3
+ 701 0034 06D0     		beq	.L71
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 702              		.loc 1 314 9 is_stmt 1 view .LVU178
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 703              		.loc 1 314 27 is_stmt 0 view .LVU179
+ 704 0036 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 705              	.LVL36:
+ 706 003a FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 707              	.LVL37:
+ 708 003e FFF7FEFF 		bl	RCC_GetPCLK2ClockFreq
+ 709              	.LVL38:
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 710              		.loc 1 315 9 is_stmt 1 view .LVU180
+ 711 0042 E8E7     		b	.L40
+ 712              	.LVL39:
+ 713              	.L71:
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 714              		.loc 1 295 9 view .LVU181
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 715              		.loc 1 295 27 is_stmt 0 view .LVU182
+ 716 0044 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 717              	.LVL40:
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 718              		.loc 1 296 9 is_stmt 1 view .LVU183
+ 719 0048 E5E7     		b	.L40
+ 720              	.LVL41:
+ 721              	.L42:
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 722              		.loc 1 299 9 view .LVU184
+ 723              	.LBB270:
+ 724              	.LBI270:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 725              		.loc 2 2030 26 view .LVU185
+ 726              	.LBB271:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 727              		.loc 2 2032 3 view .LVU186
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 728              		.loc 2 2032 11 is_stmt 0 view .LVU187
+ 729 004a 454B     		ldr	r3, .L75
+ARM GAS  /tmp/ccTMI75D.s 			page 112
+
+
+ 730 004c 1868     		ldr	r0, [r3]
+ 731              	.LBE271:
+ 732              	.LBE270:
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 733              		.loc 1 299 12 view .LVU188
+ 734 004e 10F00200 		ands	r0, r0, #2
+ 735 0052 E0D0     		beq	.L40
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 736              		.loc 1 301 27 view .LVU189
+ 737 0054 4448     		ldr	r0, .L75+8
+ 738 0056 DEE7     		b	.L40
+ 739              	.L43:
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 740              		.loc 1 306 9 is_stmt 1 view .LVU190
+ 741              	.LBB272:
+ 742              	.LBI272:
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 743              		.loc 2 2154 26 view .LVU191
+ 744              	.LBB273:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 745              		.loc 2 2156 3 view .LVU192
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 746              		.loc 2 2156 11 is_stmt 0 view .LVU193
+ 747 0058 414B     		ldr	r3, .L75
+ 748 005a 186F     		ldr	r0, [r3, #112]
+ 749              	.LBE273:
+ 750              	.LBE272:
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 751              		.loc 1 306 12 view .LVU194
+ 752 005c 10F00200 		ands	r0, r0, #2
+ 753 0060 D9D0     		beq	.L40
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 754              		.loc 1 308 27 view .LVU195
+ 755 0062 4FF40040 		mov	r0, #32768
+ 756 0066 D6E7     		b	.L40
+ 757              	.LVL42:
+ 758              	.L68:
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 759              		.loc 1 321 5 is_stmt 1 view .LVU196
+ 760              	.LBB274:
+ 761              	.LBI274:
+2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 762              		.loc 2 2664 26 view .LVU197
+ 763              	.LBB275:
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 764              		.loc 2 2666 3 view .LVU198
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 765              		.loc 2 2666 21 is_stmt 0 view .LVU199
+ 766 0068 3D4B     		ldr	r3, .L75
+ 767 006a D3F89030 		ldr	r3, [r3, #144]
+ 768 006e 0340     		ands	r3, r3, r0
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 769              		.loc 2 2666 10 view .LVU200
+ 770 0070 43EA0040 		orr	r0, r3, r0, lsl #16
+ 771              	.LVL43:
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 772              		.loc 2 2666 10 view .LVU201
+ARM GAS  /tmp/ccTMI75D.s 			page 113
+
+
+ 773              	.LBE275:
+ 774              	.LBE274:
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 775              		.loc 1 321 5 view .LVU202
+ 776 0074 3D4B     		ldr	r3, .L75+12
+ 777 0076 9842     		cmp	r0, r3
+ 778 0078 0FD0     		beq	.L47
+ 779 007a B0F10C1F 		cmp	r0, #786444
+ 780 007e 13D0     		beq	.L48
+ 781 0080 043B     		subs	r3, r3, #4
+ 782 0082 9842     		cmp	r0, r3
+ 783 0084 06D0     		beq	.L72
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 784              		.loc 1 343 9 is_stmt 1 view .LVU203
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 785              		.loc 1 343 27 is_stmt 0 view .LVU204
+ 786 0086 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 787              	.LVL44:
+ 788 008a FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 789              	.LVL45:
+ 790 008e FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 791              	.LVL46:
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 792              		.loc 1 344 9 is_stmt 1 view .LVU205
+ 793 0092 C0E7     		b	.L40
+ 794              	.LVL47:
+ 795              	.L72:
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 796              		.loc 1 324 9 view .LVU206
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 797              		.loc 1 324 27 is_stmt 0 view .LVU207
+ 798 0094 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 799              	.LVL48:
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 800              		.loc 1 325 9 is_stmt 1 view .LVU208
+ 801 0098 BDE7     		b	.L40
+ 802              	.LVL49:
+ 803              	.L47:
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 804              		.loc 1 328 9 view .LVU209
+ 805              	.LBB276:
+ 806              	.LBI276:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 807              		.loc 2 2030 26 view .LVU210
+ 808              	.LBB277:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 809              		.loc 2 2032 3 view .LVU211
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 810              		.loc 2 2032 11 is_stmt 0 view .LVU212
+ 811 009a 314B     		ldr	r3, .L75
+ 812 009c 1868     		ldr	r0, [r3]
+ 813              	.LBE277:
+ 814              	.LBE276:
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 815              		.loc 1 328 12 view .LVU213
+ 816 009e 10F00200 		ands	r0, r0, #2
+ 817 00a2 B8D0     		beq	.L40
+ARM GAS  /tmp/ccTMI75D.s 			page 114
+
+
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 818              		.loc 1 330 27 view .LVU214
+ 819 00a4 3048     		ldr	r0, .L75+8
+ 820 00a6 B6E7     		b	.L40
+ 821              	.L48:
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 822              		.loc 1 335 9 is_stmt 1 view .LVU215
+ 823              	.LBB278:
+ 824              	.LBI278:
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 825              		.loc 2 2154 26 view .LVU216
+ 826              	.LBB279:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 827              		.loc 2 2156 3 view .LVU217
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 828              		.loc 2 2156 11 is_stmt 0 view .LVU218
+ 829 00a8 2D4B     		ldr	r3, .L75
+ 830 00aa 186F     		ldr	r0, [r3, #112]
+ 831              	.LBE279:
+ 832              	.LBE278:
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 833              		.loc 1 335 12 view .LVU219
+ 834 00ac 10F00200 		ands	r0, r0, #2
+ 835 00b0 B1D0     		beq	.L40
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 836              		.loc 1 337 27 view .LVU220
+ 837 00b2 4FF40040 		mov	r0, #32768
+ 838 00b6 AEE7     		b	.L40
+ 839              	.LVL50:
+ 840              	.L69:
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 841              		.loc 1 350 5 is_stmt 1 view .LVU221
+ 842              	.LBB280:
+ 843              	.LBI280:
+2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 844              		.loc 2 2664 26 view .LVU222
+ 845              	.LBB281:
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 846              		.loc 2 2666 3 view .LVU223
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 847              		.loc 2 2666 21 is_stmt 0 view .LVU224
+ 848 00b8 294B     		ldr	r3, .L75
+ 849 00ba D3F89030 		ldr	r3, [r3, #144]
+ 850 00be 0340     		ands	r3, r3, r0
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 851              		.loc 2 2666 10 view .LVU225
+ 852 00c0 43EA0040 		orr	r0, r3, r0, lsl #16
+ 853              	.LVL51:
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 854              		.loc 2 2666 10 view .LVU226
+ 855              	.LBE281:
+ 856              	.LBE280:
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 857              		.loc 1 350 5 view .LVU227
+ 858 00c4 2A4B     		ldr	r3, .L75+16
+ 859 00c6 9842     		cmp	r0, r3
+ 860 00c8 10D0     		beq	.L51
+ARM GAS  /tmp/ccTMI75D.s 			page 115
+
+
+ 861 00ca B0F10C2F 		cmp	r0, #201329664
+ 862 00ce 14D0     		beq	.L52
+ 863 00d0 A3F58063 		sub	r3, r3, #1024
+ 864 00d4 9842     		cmp	r0, r3
+ 865 00d6 06D0     		beq	.L73
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 866              		.loc 1 372 9 is_stmt 1 view .LVU228
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 867              		.loc 1 372 27 is_stmt 0 view .LVU229
+ 868 00d8 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 869              	.LVL52:
+ 870 00dc FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 871              	.LVL53:
+ 872 00e0 FFF7FEFF 		bl	RCC_GetPCLK2ClockFreq
+ 873              	.LVL54:
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 874              		.loc 1 373 9 is_stmt 1 view .LVU230
+ 875 00e4 97E7     		b	.L40
+ 876              	.LVL55:
+ 877              	.L73:
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 878              		.loc 1 353 9 view .LVU231
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 879              		.loc 1 353 27 is_stmt 0 view .LVU232
+ 880 00e6 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 881              	.LVL56:
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 882              		.loc 1 354 9 is_stmt 1 view .LVU233
+ 883 00ea 94E7     		b	.L40
+ 884              	.LVL57:
+ 885              	.L51:
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 886              		.loc 1 357 9 view .LVU234
+ 887              	.LBB282:
+ 888              	.LBI282:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 889              		.loc 2 2030 26 view .LVU235
+ 890              	.LBB283:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 891              		.loc 2 2032 3 view .LVU236
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 892              		.loc 2 2032 11 is_stmt 0 view .LVU237
+ 893 00ec 1C4B     		ldr	r3, .L75
+ 894 00ee 1868     		ldr	r0, [r3]
+ 895              	.LBE283:
+ 896              	.LBE282:
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 897              		.loc 1 357 12 view .LVU238
+ 898 00f0 10F00200 		ands	r0, r0, #2
+ 899 00f4 8FD0     		beq	.L40
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 900              		.loc 1 359 27 view .LVU239
+ 901 00f6 1C48     		ldr	r0, .L75+8
+ 902 00f8 8DE7     		b	.L40
+ 903              	.L52:
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 904              		.loc 1 364 9 is_stmt 1 view .LVU240
+ARM GAS  /tmp/ccTMI75D.s 			page 116
+
+
+ 905              	.LBB284:
+ 906              	.LBI284:
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 907              		.loc 2 2154 26 view .LVU241
+ 908              	.LBB285:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 909              		.loc 2 2156 3 view .LVU242
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 910              		.loc 2 2156 11 is_stmt 0 view .LVU243
+ 911 00fa 194B     		ldr	r3, .L75
+ 912 00fc 186F     		ldr	r0, [r3, #112]
+ 913              	.LBE285:
+ 914              	.LBE284:
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 915              		.loc 1 364 12 view .LVU244
+ 916 00fe 10F00200 		ands	r0, r0, #2
+ 917 0102 88D0     		beq	.L40
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 918              		.loc 1 366 27 view .LVU245
+ 919 0104 4FF40040 		mov	r0, #32768
+ 920 0108 85E7     		b	.L40
+ 921              	.LVL58:
+ 922              	.L70:
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 923              		.loc 1 381 7 is_stmt 1 view .LVU246
+ 924              	.LBB286:
+ 925              	.LBI286:
+2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 926              		.loc 2 2664 26 view .LVU247
+ 927              	.LBB287:
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 928              		.loc 2 2666 3 view .LVU248
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 929              		.loc 2 2666 21 is_stmt 0 view .LVU249
+ 930 010a 154B     		ldr	r3, .L75
+ 931 010c D3F89030 		ldr	r3, [r3, #144]
+ 932 0110 0340     		ands	r3, r3, r0
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 933              		.loc 2 2666 10 view .LVU250
+ 934 0112 43EA0040 		orr	r0, r3, r0, lsl #16
+ 935              	.LVL59:
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 936              		.loc 2 2666 10 view .LVU251
+ 937              	.LBE287:
+ 938              	.LBE286:
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 939              		.loc 1 381 7 view .LVU252
+ 940 0116 174B     		ldr	r3, .L75+20
+ 941 0118 9842     		cmp	r0, r3
+ 942 011a 0FD0     		beq	.L54
+ 943 011c B0F1301F 		cmp	r0, #3145776
+ 944 0120 14D0     		beq	.L55
+ 945 0122 103B     		subs	r3, r3, #16
+ 946 0124 9842     		cmp	r0, r3
+ 947 0126 06D0     		beq	.L74
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 948              		.loc 1 403 11 is_stmt 1 view .LVU253
+ARM GAS  /tmp/ccTMI75D.s 			page 117
+
+
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 949              		.loc 1 403 29 is_stmt 0 view .LVU254
+ 950 0128 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 951              	.LVL60:
+ 952 012c FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 953              	.LVL61:
+ 954 0130 FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 955              	.LVL62:
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 956              		.loc 1 404 11 is_stmt 1 view .LVU255
+ 957 0134 6FE7     		b	.L40
+ 958              	.LVL63:
+ 959              	.L74:
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 960              		.loc 1 384 11 view .LVU256
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 961              		.loc 1 384 29 is_stmt 0 view .LVU257
+ 962 0136 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 963              	.LVL64:
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 964              		.loc 1 385 11 is_stmt 1 view .LVU258
+ 965 013a 6CE7     		b	.L40
+ 966              	.LVL65:
+ 967              	.L54:
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 968              		.loc 1 388 11 view .LVU259
+ 969              	.LBB288:
+ 970              	.LBI288:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 971              		.loc 2 2030 26 view .LVU260
+ 972              	.LBB289:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 973              		.loc 2 2032 3 view .LVU261
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 974              		.loc 2 2032 11 is_stmt 0 view .LVU262
+ 975 013c 084B     		ldr	r3, .L75
+ 976 013e 1868     		ldr	r0, [r3]
+ 977              	.LBE289:
+ 978              	.LBE288:
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 979              		.loc 1 388 14 view .LVU263
+ 980 0140 10F00200 		ands	r0, r0, #2
+ 981 0144 3FF467AF 		beq	.L40
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           }
+ 982              		.loc 1 390 29 view .LVU264
+ 983 0148 0748     		ldr	r0, .L75+8
+ 984 014a 64E7     		b	.L40
+ 985              	.L55:
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 986              		.loc 1 395 11 is_stmt 1 view .LVU265
+ 987              	.LBB290:
+ 988              	.LBI290:
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 989              		.loc 2 2154 26 view .LVU266
+ 990              	.LBB291:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 991              		.loc 2 2156 3 view .LVU267
+ARM GAS  /tmp/ccTMI75D.s 			page 118
+
+
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 992              		.loc 2 2156 11 is_stmt 0 view .LVU268
+ 993 014c 044B     		ldr	r3, .L75
+ 994 014e 186F     		ldr	r0, [r3, #112]
+ 995              	.LBE291:
+ 996              	.LBE290:
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 997              		.loc 1 395 14 view .LVU269
+ 998 0150 10F00200 		ands	r0, r0, #2
+ 999 0154 3FF45FAF 		beq	.L40
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           }
+ 1000              		.loc 1 397 29 view .LVU270
+ 1001 0158 4FF40040 		mov	r0, #32768
+ 1002              	.LVL66:
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 1003              		.loc 1 408 3 is_stmt 1 view .LVU271
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 1004              		.loc 1 408 10 is_stmt 0 view .LVU272
+ 1005 015c 5BE7     		b	.L40
+ 1006              	.L76:
+ 1007 015e 00BF     		.align	2
+ 1008              	.L75:
+ 1009 0160 00380240 		.word	1073887232
+ 1010 0164 02000300 		.word	196610
+ 1011 0168 0024F400 		.word	16000000
+ 1012 016c 08000C00 		.word	786440
+ 1013 0170 0008000C 		.word	201328640
+ 1014 0174 20003000 		.word	3145760
+ 1015              		.cfi_endproc
+ 1016              	.LFE297:
+ 1018              		.section	.text.LL_RCC_GetUARTClockFreq,"ax",%progbits
+ 1019              		.align	1
+ 1020              		.global	LL_RCC_GetUARTClockFreq
+ 1021              		.syntax unified
+ 1022              		.thumb
+ 1023              		.thumb_func
+ 1024              		.fpu fpv5-d16
+ 1026              	LL_RCC_GetUARTClockFreq:
+ 1027              	.LVL67:
+ 1028              	.LFB298:
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 1029              		.loc 1 422 1 is_stmt 1 view -0
+ 1030              		.cfi_startproc
+ 1031              		@ args = 0, pretend = 0, frame = 0
+ 1032              		@ frame_needed = 0, uses_anonymous_args = 0
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 1033              		.loc 1 422 1 is_stmt 0 view .LVU274
+ 1034 0000 08B5     		push	{r3, lr}
+ 1035              	.LCFI5:
+ 1036              		.cfi_def_cfa_offset 8
+ 1037              		.cfi_offset 3, -8
+ 1038              		.cfi_offset 14, -4
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1039              		.loc 1 423 3 is_stmt 1 view .LVU275
+ 1040              	.LVL68:
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1041              		.loc 1 426 3 view .LVU276
+ARM GAS  /tmp/ccTMI75D.s 			page 119
+
+
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1042              		.loc 1 428 3 view .LVU277
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1043              		.loc 1 428 6 is_stmt 0 view .LVU278
+ 1044 0002 C028     		cmp	r0, #192
+ 1045 0004 0AD0     		beq	.L104
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1046              		.loc 1 457 8 is_stmt 1 view .LVU279
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1047              		.loc 1 457 11 is_stmt 0 view .LVU280
+ 1048 0006 B0F5407F 		cmp	r0, #768
+ 1049 000a 2FD0     		beq	.L105
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1050              		.loc 1 486 8 is_stmt 1 view .LVU281
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1051              		.loc 1 486 11 is_stmt 0 view .LVU282
+ 1052 000c B0F5405F 		cmp	r0, #12288
+ 1053 0010 55D0     		beq	.L106
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1054              		.loc 1 517 5 is_stmt 1 view .LVU283
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1055              		.loc 1 517 8 is_stmt 0 view .LVU284
+ 1056 0012 B0F5404F 		cmp	r0, #49152
+ 1057 0016 7BD0     		beq	.L107
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1058              		.loc 1 423 12 view .LVU285
+ 1059 0018 0020     		movs	r0, #0
+ 1060              	.LVL69:
+ 1061              	.L77:
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1062              		.loc 1 548 1 view .LVU286
+ 1063 001a 08BD     		pop	{r3, pc}
+ 1064              	.LVL70:
+ 1065              	.L104:
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1066              		.loc 1 431 5 is_stmt 1 view .LVU287
+ 1067              	.LBB292:
+ 1068              	.LBI292:
+2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1069              		.loc 2 2698 26 view .LVU288
+ 1070              	.LBB293:
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1071              		.loc 2 2700 3 view .LVU289
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1072              		.loc 2 2700 21 is_stmt 0 view .LVU290
+ 1073 001c 524B     		ldr	r3, .L112
+ 1074 001e D3F89030 		ldr	r3, [r3, #144]
+ 1075 0022 0340     		ands	r3, r3, r0
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1076              		.loc 2 2700 10 view .LVU291
+ 1077 0024 43EA0040 		orr	r0, r3, r0, lsl #16
+ 1078              	.LVL71:
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1079              		.loc 2 2700 10 view .LVU292
+ 1080              	.LBE293:
+ 1081              	.LBE292:
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ARM GAS  /tmp/ccTMI75D.s 			page 120
+
+
+ 1082              		.loc 1 431 5 view .LVU293
+ 1083 0028 504B     		ldr	r3, .L112+4
+ 1084 002a 9842     		cmp	r0, r3
+ 1085 002c 0FD0     		beq	.L79
+ 1086 002e B0F1C01F 		cmp	r0, #12583104
+ 1087 0032 13D0     		beq	.L80
+ 1088 0034 403B     		subs	r3, r3, #64
+ 1089 0036 9842     		cmp	r0, r3
+ 1090 0038 06D0     		beq	.L108
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1091              		.loc 1 453 9 is_stmt 1 view .LVU294
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1092              		.loc 1 453 26 is_stmt 0 view .LVU295
+ 1093 003a FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1094              	.LVL72:
+ 1095 003e FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 1096              	.LVL73:
+ 1097 0042 FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 1098              	.LVL74:
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 1099              		.loc 1 454 9 is_stmt 1 view .LVU296
+ 1100 0046 E8E7     		b	.L77
+ 1101              	.LVL75:
+ 1102              	.L108:
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1103              		.loc 1 434 9 view .LVU297
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1104              		.loc 1 434 26 is_stmt 0 view .LVU298
+ 1105 0048 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1106              	.LVL76:
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1107              		.loc 1 435 9 is_stmt 1 view .LVU299
+ 1108 004c E5E7     		b	.L77
+ 1109              	.LVL77:
+ 1110              	.L79:
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1111              		.loc 1 438 9 view .LVU300
+ 1112              	.LBB294:
+ 1113              	.LBI294:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1114              		.loc 2 2030 26 view .LVU301
+ 1115              	.LBB295:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1116              		.loc 2 2032 3 view .LVU302
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1117              		.loc 2 2032 11 is_stmt 0 view .LVU303
+ 1118 004e 464B     		ldr	r3, .L112
+ 1119 0050 1868     		ldr	r0, [r3]
+ 1120              	.LBE295:
+ 1121              	.LBE294:
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1122              		.loc 1 438 12 view .LVU304
+ 1123 0052 10F00200 		ands	r0, r0, #2
+ 1124 0056 E0D0     		beq	.L77
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1125              		.loc 1 440 26 view .LVU305
+ 1126 0058 4548     		ldr	r0, .L112+8
+ARM GAS  /tmp/ccTMI75D.s 			page 121
+
+
+ 1127 005a DEE7     		b	.L77
+ 1128              	.L80:
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1129              		.loc 1 445 9 is_stmt 1 view .LVU306
+ 1130              	.LBB296:
+ 1131              	.LBI296:
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1132              		.loc 2 2154 26 view .LVU307
+ 1133              	.LBB297:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1134              		.loc 2 2156 3 view .LVU308
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1135              		.loc 2 2156 11 is_stmt 0 view .LVU309
+ 1136 005c 424B     		ldr	r3, .L112
+ 1137 005e 186F     		ldr	r0, [r3, #112]
+ 1138              	.LBE297:
+ 1139              	.LBE296:
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1140              		.loc 1 445 12 view .LVU310
+ 1141 0060 10F00200 		ands	r0, r0, #2
+ 1142 0064 D9D0     		beq	.L77
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1143              		.loc 1 447 26 view .LVU311
+ 1144 0066 4FF40040 		mov	r0, #32768
+ 1145 006a D6E7     		b	.L77
+ 1146              	.LVL78:
+ 1147              	.L105:
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1148              		.loc 1 460 5 is_stmt 1 view .LVU312
+ 1149              	.LBB298:
+ 1150              	.LBI298:
+2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1151              		.loc 2 2698 26 view .LVU313
+ 1152              	.LBB299:
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1153              		.loc 2 2700 3 view .LVU314
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1154              		.loc 2 2700 21 is_stmt 0 view .LVU315
+ 1155 006c 3E4B     		ldr	r3, .L112
+ 1156 006e D3F89030 		ldr	r3, [r3, #144]
+ 1157 0072 0340     		ands	r3, r3, r0
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1158              		.loc 2 2700 10 view .LVU316
+ 1159 0074 43EA0040 		orr	r0, r3, r0, lsl #16
+ 1160              	.LVL79:
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1161              		.loc 2 2700 10 view .LVU317
+ 1162              	.LBE299:
+ 1163              	.LBE298:
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1164              		.loc 1 460 5 view .LVU318
+ 1165 0078 3E4B     		ldr	r3, .L112+12
+ 1166 007a 9842     		cmp	r0, r3
+ 1167 007c 10D0     		beq	.L84
+ 1168 007e B0F1032F 		cmp	r0, #50332416
+ 1169 0082 14D0     		beq	.L85
+ 1170 0084 A3F58073 		sub	r3, r3, #256
+ARM GAS  /tmp/ccTMI75D.s 			page 122
+
+
+ 1171 0088 9842     		cmp	r0, r3
+ 1172 008a 06D0     		beq	.L109
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1173              		.loc 1 482 9 is_stmt 1 view .LVU319
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1174              		.loc 1 482 26 is_stmt 0 view .LVU320
+ 1175 008c FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1176              	.LVL80:
+ 1177 0090 FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 1178              	.LVL81:
+ 1179 0094 FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 1180              	.LVL82:
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 1181              		.loc 1 483 9 is_stmt 1 view .LVU321
+ 1182 0098 BFE7     		b	.L77
+ 1183              	.LVL83:
+ 1184              	.L109:
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1185              		.loc 1 463 9 view .LVU322
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1186              		.loc 1 463 26 is_stmt 0 view .LVU323
+ 1187 009a FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1188              	.LVL84:
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1189              		.loc 1 464 9 is_stmt 1 view .LVU324
+ 1190 009e BCE7     		b	.L77
+ 1191              	.LVL85:
+ 1192              	.L84:
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1193              		.loc 1 467 9 view .LVU325
+ 1194              	.LBB300:
+ 1195              	.LBI300:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1196              		.loc 2 2030 26 view .LVU326
+ 1197              	.LBB301:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1198              		.loc 2 2032 3 view .LVU327
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1199              		.loc 2 2032 11 is_stmt 0 view .LVU328
+ 1200 00a0 314B     		ldr	r3, .L112
+ 1201 00a2 1868     		ldr	r0, [r3]
+ 1202              	.LBE301:
+ 1203              	.LBE300:
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1204              		.loc 1 467 12 view .LVU329
+ 1205 00a4 10F00200 		ands	r0, r0, #2
+ 1206 00a8 B7D0     		beq	.L77
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1207              		.loc 1 469 26 view .LVU330
+ 1208 00aa 3148     		ldr	r0, .L112+8
+ 1209 00ac B5E7     		b	.L77
+ 1210              	.L85:
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1211              		.loc 1 474 9 is_stmt 1 view .LVU331
+ 1212              	.LBB302:
+ 1213              	.LBI302:
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ARM GAS  /tmp/ccTMI75D.s 			page 123
+
+
+ 1214              		.loc 2 2154 26 view .LVU332
+ 1215              	.LBB303:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1216              		.loc 2 2156 3 view .LVU333
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1217              		.loc 2 2156 11 is_stmt 0 view .LVU334
+ 1218 00ae 2E4B     		ldr	r3, .L112
+ 1219 00b0 186F     		ldr	r0, [r3, #112]
+ 1220              	.LBE303:
+ 1221              	.LBE302:
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1222              		.loc 1 474 12 view .LVU335
+ 1223 00b2 10F00200 		ands	r0, r0, #2
+ 1224 00b6 B0D0     		beq	.L77
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1225              		.loc 1 476 26 view .LVU336
+ 1226 00b8 4FF40040 		mov	r0, #32768
+ 1227 00bc ADE7     		b	.L77
+ 1228              	.LVL86:
+ 1229              	.L106:
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1230              		.loc 1 489 5 is_stmt 1 view .LVU337
+ 1231              	.LBB304:
+ 1232              	.LBI304:
+2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1233              		.loc 2 2698 26 view .LVU338
+ 1234              	.LBB305:
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1235              		.loc 2 2700 3 view .LVU339
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1236              		.loc 2 2700 21 is_stmt 0 view .LVU340
+ 1237 00be 2A4B     		ldr	r3, .L112
+ 1238 00c0 D3F89030 		ldr	r3, [r3, #144]
+ 1239 00c4 0340     		ands	r3, r3, r0
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1240              		.loc 2 2700 10 view .LVU341
+ 1241 00c6 43EA0040 		orr	r0, r3, r0, lsl #16
+ 1242              	.LVL87:
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1243              		.loc 2 2700 10 view .LVU342
+ 1244              	.LBE305:
+ 1245              	.LBE304:
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1246              		.loc 1 489 5 view .LVU343
+ 1247 00ca 2B4B     		ldr	r3, .L112+16
+ 1248 00cc 9842     		cmp	r0, r3
+ 1249 00ce 10D0     		beq	.L88
+ 1250 00d0 B0F1302F 		cmp	r0, #805318656
+ 1251 00d4 14D0     		beq	.L89
+ 1252 00d6 A3F58053 		sub	r3, r3, #4096
+ 1253 00da 9842     		cmp	r0, r3
+ 1254 00dc 06D0     		beq	.L110
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1255              		.loc 1 511 9 is_stmt 1 view .LVU344
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1256              		.loc 1 511 26 is_stmt 0 view .LVU345
+ 1257 00de FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ARM GAS  /tmp/ccTMI75D.s 			page 124
+
+
+ 1258              	.LVL88:
+ 1259 00e2 FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 1260              	.LVL89:
+ 1261 00e6 FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 1262              	.LVL90:
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 1263              		.loc 1 512 9 is_stmt 1 view .LVU346
+ 1264 00ea 96E7     		b	.L77
+ 1265              	.LVL91:
+ 1266              	.L110:
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1267              		.loc 1 492 9 view .LVU347
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1268              		.loc 1 492 26 is_stmt 0 view .LVU348
+ 1269 00ec FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1270              	.LVL92:
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1271              		.loc 1 493 9 is_stmt 1 view .LVU349
+ 1272 00f0 93E7     		b	.L77
+ 1273              	.LVL93:
+ 1274              	.L88:
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1275              		.loc 1 496 9 view .LVU350
+ 1276              	.LBB306:
+ 1277              	.LBI306:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1278              		.loc 2 2030 26 view .LVU351
+ 1279              	.LBB307:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1280              		.loc 2 2032 3 view .LVU352
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1281              		.loc 2 2032 11 is_stmt 0 view .LVU353
+ 1282 00f2 1D4B     		ldr	r3, .L112
+ 1283 00f4 1868     		ldr	r0, [r3]
+ 1284              	.LBE307:
+ 1285              	.LBE306:
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1286              		.loc 1 496 12 view .LVU354
+ 1287 00f6 10F00200 		ands	r0, r0, #2
+ 1288 00fa 8ED0     		beq	.L77
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1289              		.loc 1 498 26 view .LVU355
+ 1290 00fc 1C48     		ldr	r0, .L112+8
+ 1291 00fe 8CE7     		b	.L77
+ 1292              	.L89:
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1293              		.loc 1 503 9 is_stmt 1 view .LVU356
+ 1294              	.LBB308:
+ 1295              	.LBI308:
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1296              		.loc 2 2154 26 view .LVU357
+ 1297              	.LBB309:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1298              		.loc 2 2156 3 view .LVU358
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1299              		.loc 2 2156 11 is_stmt 0 view .LVU359
+ 1300 0100 194B     		ldr	r3, .L112
+ARM GAS  /tmp/ccTMI75D.s 			page 125
+
+
+ 1301 0102 186F     		ldr	r0, [r3, #112]
+ 1302              	.LBE309:
+ 1303              	.LBE308:
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1304              		.loc 1 503 12 view .LVU360
+ 1305 0104 10F00200 		ands	r0, r0, #2
+ 1306 0108 87D0     		beq	.L77
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1307              		.loc 1 505 26 view .LVU361
+ 1308 010a 4FF40040 		mov	r0, #32768
+ 1309 010e 84E7     		b	.L77
+ 1310              	.LVL94:
+ 1311              	.L107:
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 1312              		.loc 1 520 7 is_stmt 1 view .LVU362
+ 1313              	.LBB310:
+ 1314              	.LBI310:
+2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1315              		.loc 2 2698 26 view .LVU363
+ 1316              	.LBB311:
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1317              		.loc 2 2700 3 view .LVU364
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1318              		.loc 2 2700 21 is_stmt 0 view .LVU365
+ 1319 0110 154B     		ldr	r3, .L112
+ 1320 0112 D3F89030 		ldr	r3, [r3, #144]
+ 1321 0116 0340     		ands	r3, r3, r0
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1322              		.loc 2 2700 10 view .LVU366
+ 1323 0118 43EA0040 		orr	r0, r3, r0, lsl #16
+ 1324              	.LVL95:
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1325              		.loc 2 2700 10 view .LVU367
+ 1326              	.LBE311:
+ 1327              	.LBE310:
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 1328              		.loc 1 520 7 view .LVU368
+ 1329 011c 174B     		ldr	r3, .L112+20
+ 1330 011e 9842     		cmp	r0, r3
+ 1331 0120 10D0     		beq	.L91
+ 1332 0122 B0F1C02F 		cmp	r0, #-1073692672
+ 1333 0126 15D0     		beq	.L92
+ 1334 0128 A3F58043 		sub	r3, r3, #16384
+ 1335 012c 9842     		cmp	r0, r3
+ 1336 012e 06D0     		beq	.L111
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 1337              		.loc 1 542 11 is_stmt 1 view .LVU369
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 1338              		.loc 1 542 28 is_stmt 0 view .LVU370
+ 1339 0130 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1340              	.LVL96:
+ 1341 0134 FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 1342              	.LVL97:
+ 1343 0138 FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 1344              	.LVL98:
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 1345              		.loc 1 543 11 is_stmt 1 view .LVU371
+ARM GAS  /tmp/ccTMI75D.s 			page 126
+
+
+ 1346 013c 6DE7     		b	.L77
+ 1347              	.LVL99:
+ 1348              	.L111:
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 1349              		.loc 1 523 11 view .LVU372
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 1350              		.loc 1 523 28 is_stmt 0 view .LVU373
+ 1351 013e FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1352              	.LVL100:
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1353              		.loc 1 524 11 is_stmt 1 view .LVU374
+ 1354 0142 6AE7     		b	.L77
+ 1355              	.LVL101:
+ 1356              	.L91:
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 1357              		.loc 1 527 11 view .LVU375
+ 1358              	.LBB312:
+ 1359              	.LBI312:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1360              		.loc 2 2030 26 view .LVU376
+ 1361              	.LBB313:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1362              		.loc 2 2032 3 view .LVU377
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1363              		.loc 2 2032 11 is_stmt 0 view .LVU378
+ 1364 0144 084B     		ldr	r3, .L112
+ 1365 0146 1868     		ldr	r0, [r3]
+ 1366              	.LBE313:
+ 1367              	.LBE312:
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 1368              		.loc 1 527 14 view .LVU379
+ 1369 0148 10F00200 		ands	r0, r0, #2
+ 1370 014c 3FF465AF 		beq	.L77
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           }
+ 1371              		.loc 1 529 28 view .LVU380
+ 1372 0150 0748     		ldr	r0, .L112+8
+ 1373 0152 62E7     		b	.L77
+ 1374              	.L92:
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 1375              		.loc 1 534 11 is_stmt 1 view .LVU381
+ 1376              	.LBB314:
+ 1377              	.LBI314:
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1378              		.loc 2 2154 26 view .LVU382
+ 1379              	.LBB315:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1380              		.loc 2 2156 3 view .LVU383
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1381              		.loc 2 2156 11 is_stmt 0 view .LVU384
+ 1382 0154 044B     		ldr	r3, .L112
+ 1383 0156 186F     		ldr	r0, [r3, #112]
+ 1384              	.LBE315:
+ 1385              	.LBE314:
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 1386              		.loc 1 534 14 view .LVU385
+ 1387 0158 10F00200 		ands	r0, r0, #2
+ 1388 015c 3FF45DAF 		beq	.L77
+ARM GAS  /tmp/ccTMI75D.s 			page 127
+
+
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           }
+ 1389              		.loc 1 536 28 view .LVU386
+ 1390 0160 4FF40040 		mov	r0, #32768
+ 1391              	.LVL102:
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 1392              		.loc 1 547 3 is_stmt 1 view .LVU387
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 1393              		.loc 1 547 10 is_stmt 0 view .LVU388
+ 1394 0164 59E7     		b	.L77
+ 1395              	.L113:
+ 1396 0166 00BF     		.align	2
+ 1397              	.L112:
+ 1398 0168 00380240 		.word	1073887232
+ 1399 016c 8000C000 		.word	12583040
+ 1400 0170 0024F400 		.word	16000000
+ 1401 0174 00020003 		.word	50332160
+ 1402 0178 00200030 		.word	805314560
+ 1403 017c 008000C0 		.word	-1073709056
+ 1404              		.cfi_endproc
+ 1405              	.LFE298:
+ 1407              		.section	.text.LL_RCC_GetI2CClockFreq,"ax",%progbits
+ 1408              		.align	1
+ 1409              		.global	LL_RCC_GetI2CClockFreq
+ 1410              		.syntax unified
+ 1411              		.thumb
+ 1412              		.thumb_func
+ 1413              		.fpu fpv5-d16
+ 1415              	LL_RCC_GetI2CClockFreq:
+ 1416              	.LVL103:
+ 1417              	.LFB299:
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 1418              		.loc 1 563 1 is_stmt 1 view -0
+ 1419              		.cfi_startproc
+ 1420              		@ args = 0, pretend = 0, frame = 0
+ 1421              		@ frame_needed = 0, uses_anonymous_args = 0
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 1422              		.loc 1 563 1 is_stmt 0 view .LVU390
+ 1423 0000 08B5     		push	{r3, lr}
+ 1424              	.LCFI6:
+ 1425              		.cfi_def_cfa_offset 8
+ 1426              		.cfi_offset 3, -8
+ 1427              		.cfi_offset 14, -4
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1428              		.loc 1 564 3 is_stmt 1 view .LVU391
+ 1429              	.LVL104:
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1430              		.loc 1 567 3 view .LVU392
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1431              		.loc 1 569 3 view .LVU393
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1432              		.loc 1 569 6 is_stmt 0 view .LVU394
+ 1433 0002 B0F5403F 		cmp	r0, #196608
+ 1434 0006 0AD0     		beq	.L141
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1435              		.loc 1 591 8 is_stmt 1 view .LVU395
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1436              		.loc 1 591 11 is_stmt 0 view .LVU396
+ARM GAS  /tmp/ccTMI75D.s 			page 128
+
+
+ 1437 0008 B0F5402F 		cmp	r0, #786432
+ 1438 000c 24D0     		beq	.L142
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1439              		.loc 1 613 8 is_stmt 1 view .LVU397
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1440              		.loc 1 613 11 is_stmt 0 view .LVU398
+ 1441 000e B0F5401F 		cmp	r0, #3145728
+ 1442 0012 3ED0     		beq	.L143
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1443              		.loc 1 638 5 is_stmt 1 view .LVU399
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1444              		.loc 1 638 8 is_stmt 0 view .LVU400
+ 1445 0014 B0F5400F 		cmp	r0, #12582912
+ 1446 0018 58D0     		beq	.L144
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1447              		.loc 1 564 12 view .LVU401
+ 1448 001a 0020     		movs	r0, #0
+ 1449              	.LVL105:
+ 1450              	.L114:
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1451              		.loc 1 669 1 view .LVU402
+ 1452 001c 08BD     		pop	{r3, pc}
+ 1453              	.LVL106:
+ 1454              	.L141:
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1455              		.loc 1 572 5 is_stmt 1 view .LVU403
+ 1456              	.LBB316:
+ 1457              	.LBI316:
+2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1458              		.loc 2 2730 26 view .LVU404
+ 1459              	.LBB317:
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1460              		.loc 2 2732 3 view .LVU405
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1461              		.loc 2 2732 22 is_stmt 0 view .LVU406
+ 1462 001e 3A4B     		ldr	r3, .L145
+ 1463 0020 D3F89030 		ldr	r3, [r3, #144]
+ 1464 0024 0340     		ands	r3, r3, r0
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1465              		.loc 2 2732 10 view .LVU407
+ 1466 0026 40EA1340 		orr	r0, r0, r3, lsr #16
+ 1467              	.LVL107:
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1468              		.loc 2 2732 10 view .LVU408
+ 1469              	.LBE317:
+ 1470              	.LBE316:
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1471              		.loc 1 572 5 view .LVU409
+ 1472 002a 384B     		ldr	r3, .L145+4
+ 1473 002c 9842     		cmp	r0, r3
+ 1474 002e 09D0     		beq	.L116
+ 1475 0030 0133     		adds	r3, r3, #1
+ 1476 0032 9842     		cmp	r0, r3
+ 1477 0034 09D0     		beq	.L117
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1478              		.loc 1 587 9 is_stmt 1 view .LVU410
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ARM GAS  /tmp/ccTMI75D.s 			page 129
+
+
+ 1479              		.loc 1 587 25 is_stmt 0 view .LVU411
+ 1480 0036 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1481              	.LVL108:
+ 1482 003a FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 1483              	.LVL109:
+ 1484 003e FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 1485              	.LVL110:
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 1486              		.loc 1 588 9 is_stmt 1 view .LVU412
+ 1487 0042 EBE7     		b	.L114
+ 1488              	.LVL111:
+ 1489              	.L116:
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1490              		.loc 1 575 9 view .LVU413
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1491              		.loc 1 575 25 is_stmt 0 view .LVU414
+ 1492 0044 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1493              	.LVL112:
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1494              		.loc 1 576 9 is_stmt 1 view .LVU415
+ 1495 0048 E8E7     		b	.L114
+ 1496              	.LVL113:
+ 1497              	.L117:
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1498              		.loc 1 579 9 view .LVU416
+ 1499              	.LBB318:
+ 1500              	.LBI318:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1501              		.loc 2 2030 26 view .LVU417
+ 1502              	.LBB319:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1503              		.loc 2 2032 3 view .LVU418
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1504              		.loc 2 2032 11 is_stmt 0 view .LVU419
+ 1505 004a 2F4B     		ldr	r3, .L145
+ 1506 004c 1868     		ldr	r0, [r3]
+ 1507              	.LBE319:
+ 1508              	.LBE318:
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1509              		.loc 1 579 12 view .LVU420
+ 1510 004e 10F00200 		ands	r0, r0, #2
+ 1511 0052 E3D0     		beq	.L114
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1512              		.loc 1 581 25 view .LVU421
+ 1513 0054 2E48     		ldr	r0, .L145+8
+ 1514 0056 E1E7     		b	.L114
+ 1515              	.LVL114:
+ 1516              	.L142:
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1517              		.loc 1 594 5 is_stmt 1 view .LVU422
+ 1518              	.LBB320:
+ 1519              	.LBI320:
+2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1520              		.loc 2 2730 26 view .LVU423
+ 1521              	.LBB321:
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1522              		.loc 2 2732 3 view .LVU424
+ARM GAS  /tmp/ccTMI75D.s 			page 130
+
+
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1523              		.loc 2 2732 22 is_stmt 0 view .LVU425
+ 1524 0058 2B4B     		ldr	r3, .L145
+ 1525 005a D3F89030 		ldr	r3, [r3, #144]
+ 1526 005e 0340     		ands	r3, r3, r0
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1527              		.loc 2 2732 10 view .LVU426
+ 1528 0060 40EA1340 		orr	r0, r0, r3, lsr #16
+ 1529              	.LVL115:
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1530              		.loc 2 2732 10 view .LVU427
+ 1531              	.LBE321:
+ 1532              	.LBE320:
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1533              		.loc 1 594 5 view .LVU428
+ 1534 0064 2B4B     		ldr	r3, .L145+12
+ 1535 0066 9842     		cmp	r0, r3
+ 1536 0068 09D0     		beq	.L121
+ 1537 006a 0433     		adds	r3, r3, #4
+ 1538 006c 9842     		cmp	r0, r3
+ 1539 006e 09D0     		beq	.L122
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1540              		.loc 1 609 9 is_stmt 1 view .LVU429
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1541              		.loc 1 609 25 is_stmt 0 view .LVU430
+ 1542 0070 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1543              	.LVL116:
+ 1544 0074 FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 1545              	.LVL117:
+ 1546 0078 FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 1547              	.LVL118:
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 1548              		.loc 1 610 9 is_stmt 1 view .LVU431
+ 1549 007c CEE7     		b	.L114
+ 1550              	.LVL119:
+ 1551              	.L121:
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1552              		.loc 1 597 9 view .LVU432
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1553              		.loc 1 597 25 is_stmt 0 view .LVU433
+ 1554 007e FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1555              	.LVL120:
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1556              		.loc 1 598 9 is_stmt 1 view .LVU434
+ 1557 0082 CBE7     		b	.L114
+ 1558              	.LVL121:
+ 1559              	.L122:
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1560              		.loc 1 601 9 view .LVU435
+ 1561              	.LBB322:
+ 1562              	.LBI322:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1563              		.loc 2 2030 26 view .LVU436
+ 1564              	.LBB323:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1565              		.loc 2 2032 3 view .LVU437
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ARM GAS  /tmp/ccTMI75D.s 			page 131
+
+
+ 1566              		.loc 2 2032 11 is_stmt 0 view .LVU438
+ 1567 0084 204B     		ldr	r3, .L145
+ 1568 0086 1868     		ldr	r0, [r3]
+ 1569              	.LBE323:
+ 1570              	.LBE322:
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1571              		.loc 1 601 12 view .LVU439
+ 1572 0088 10F00200 		ands	r0, r0, #2
+ 1573 008c C6D0     		beq	.L114
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1574              		.loc 1 603 25 view .LVU440
+ 1575 008e 2048     		ldr	r0, .L145+8
+ 1576 0090 C4E7     		b	.L114
+ 1577              	.LVL122:
+ 1578              	.L143:
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1579              		.loc 1 616 5 is_stmt 1 view .LVU441
+ 1580              	.LBB324:
+ 1581              	.LBI324:
+2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1582              		.loc 2 2730 26 view .LVU442
+ 1583              	.LBB325:
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1584              		.loc 2 2732 3 view .LVU443
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1585              		.loc 2 2732 22 is_stmt 0 view .LVU444
+ 1586 0092 1D4B     		ldr	r3, .L145
+ 1587 0094 D3F89030 		ldr	r3, [r3, #144]
+ 1588 0098 0340     		ands	r3, r3, r0
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1589              		.loc 2 2732 10 view .LVU445
+ 1590 009a 40EA1340 		orr	r0, r0, r3, lsr #16
+ 1591              	.LVL123:
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1592              		.loc 2 2732 10 view .LVU446
+ 1593              	.LBE325:
+ 1594              	.LBE324:
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1595              		.loc 1 616 5 view .LVU447
+ 1596 009e 1E4B     		ldr	r3, .L145+16
+ 1597 00a0 9842     		cmp	r0, r3
+ 1598 00a2 09D0     		beq	.L125
+ 1599 00a4 1033     		adds	r3, r3, #16
+ 1600 00a6 9842     		cmp	r0, r3
+ 1601 00a8 09D0     		beq	.L126
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1602              		.loc 1 631 9 is_stmt 1 view .LVU448
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1603              		.loc 1 631 25 is_stmt 0 view .LVU449
+ 1604 00aa FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1605              	.LVL124:
+ 1606 00ae FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 1607              	.LVL125:
+ 1608 00b2 FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 1609              	.LVL126:
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 1610              		.loc 1 632 9 is_stmt 1 view .LVU450
+ARM GAS  /tmp/ccTMI75D.s 			page 132
+
+
+ 1611 00b6 B1E7     		b	.L114
+ 1612              	.LVL127:
+ 1613              	.L125:
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1614              		.loc 1 619 9 view .LVU451
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1615              		.loc 1 619 25 is_stmt 0 view .LVU452
+ 1616 00b8 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1617              	.LVL128:
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1618              		.loc 1 620 9 is_stmt 1 view .LVU453
+ 1619 00bc AEE7     		b	.L114
+ 1620              	.LVL129:
+ 1621              	.L126:
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1622              		.loc 1 623 9 view .LVU454
+ 1623              	.LBB326:
+ 1624              	.LBI326:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1625              		.loc 2 2030 26 view .LVU455
+ 1626              	.LBB327:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1627              		.loc 2 2032 3 view .LVU456
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1628              		.loc 2 2032 11 is_stmt 0 view .LVU457
+ 1629 00be 124B     		ldr	r3, .L145
+ 1630 00c0 1868     		ldr	r0, [r3]
+ 1631              	.LBE327:
+ 1632              	.LBE326:
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1633              		.loc 1 623 12 view .LVU458
+ 1634 00c2 10F00200 		ands	r0, r0, #2
+ 1635 00c6 A9D0     		beq	.L114
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1636              		.loc 1 625 25 view .LVU459
+ 1637 00c8 1148     		ldr	r0, .L145+8
+ 1638 00ca A7E7     		b	.L114
+ 1639              	.LVL130:
+ 1640              	.L144:
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 1641              		.loc 1 641 7 is_stmt 1 view .LVU460
+ 1642              	.LBB328:
+ 1643              	.LBI328:
+2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1644              		.loc 2 2730 26 view .LVU461
+ 1645              	.LBB329:
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1646              		.loc 2 2732 3 view .LVU462
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1647              		.loc 2 2732 22 is_stmt 0 view .LVU463
+ 1648 00cc 0E4B     		ldr	r3, .L145
+ 1649 00ce D3F89030 		ldr	r3, [r3, #144]
+ 1650 00d2 0340     		ands	r3, r3, r0
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1651              		.loc 2 2732 10 view .LVU464
+ 1652 00d4 40EA1340 		orr	r0, r0, r3, lsr #16
+ 1653              	.LVL131:
+ARM GAS  /tmp/ccTMI75D.s 			page 133
+
+
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1654              		.loc 2 2732 10 view .LVU465
+ 1655              	.LBE329:
+ 1656              	.LBE328:
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 1657              		.loc 1 641 7 view .LVU466
+ 1658 00d8 104B     		ldr	r3, .L145+20
+ 1659 00da 9842     		cmp	r0, r3
+ 1660 00dc 09D0     		beq	.L128
+ 1661 00de 4033     		adds	r3, r3, #64
+ 1662 00e0 9842     		cmp	r0, r3
+ 1663 00e2 09D0     		beq	.L129
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 1664              		.loc 1 656 11 is_stmt 1 view .LVU467
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 1665              		.loc 1 656 27 is_stmt 0 view .LVU468
+ 1666 00e4 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1667              	.LVL132:
+ 1668 00e8 FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 1669              	.LVL133:
+ 1670 00ec FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 1671              	.LVL134:
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 1672              		.loc 1 657 11 is_stmt 1 view .LVU469
+ 1673 00f0 94E7     		b	.L114
+ 1674              	.LVL135:
+ 1675              	.L128:
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 1676              		.loc 1 644 11 view .LVU470
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 1677              		.loc 1 644 27 is_stmt 0 view .LVU471
+ 1678 00f2 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1679              	.LVL136:
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1680              		.loc 1 645 11 is_stmt 1 view .LVU472
+ 1681 00f6 91E7     		b	.L114
+ 1682              	.LVL137:
+ 1683              	.L129:
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 1684              		.loc 1 648 11 view .LVU473
+ 1685              	.LBB330:
+ 1686              	.LBI330:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1687              		.loc 2 2030 26 view .LVU474
+ 1688              	.LBB331:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1689              		.loc 2 2032 3 view .LVU475
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1690              		.loc 2 2032 11 is_stmt 0 view .LVU476
+ 1691 00f8 034B     		ldr	r3, .L145
+ 1692 00fa 1868     		ldr	r0, [r3]
+ 1693              	.LBE331:
+ 1694              	.LBE330:
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           {
+ 1695              		.loc 1 648 14 view .LVU477
+ 1696 00fc 10F00200 		ands	r0, r0, #2
+ 1697 0100 8CD0     		beq	.L114
+ARM GAS  /tmp/ccTMI75D.s 			page 134
+
+
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           }
+ 1698              		.loc 1 650 27 view .LVU478
+ 1699 0102 0348     		ldr	r0, .L145+8
+ 1700              	.LVL138:
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 1701              		.loc 1 668 3 is_stmt 1 view .LVU479
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 1702              		.loc 1 668 10 is_stmt 0 view .LVU480
+ 1703 0104 8AE7     		b	.L114
+ 1704              	.L146:
+ 1705 0106 00BF     		.align	2
+ 1706              	.L145:
+ 1707 0108 00380240 		.word	1073887232
+ 1708 010c 01000300 		.word	196609
+ 1709 0110 0024F400 		.word	16000000
+ 1710 0114 04000C00 		.word	786436
+ 1711 0118 10003000 		.word	3145744
+ 1712 011c 4000C000 		.word	12582976
+ 1713              		.cfi_endproc
+ 1714              	.LFE299:
+ 1716              		.section	.text.LL_RCC_GetLPTIMClockFreq,"ax",%progbits
+ 1717              		.align	1
+ 1718              		.global	LL_RCC_GetLPTIMClockFreq
+ 1719              		.syntax unified
+ 1720              		.thumb
+ 1721              		.thumb_func
+ 1722              		.fpu fpv5-d16
+ 1724              	LL_RCC_GetLPTIMClockFreq:
+ 1725              	.LVL139:
+ 1726              	.LFB301:
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 1727              		.loc 1 715 1 is_stmt 1 view -0
+ 1728              		.cfi_startproc
+ 1729              		@ args = 0, pretend = 0, frame = 0
+ 1730              		@ frame_needed = 0, uses_anonymous_args = 0
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1731              		.loc 1 716 3 view .LVU482
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1732              		.loc 1 719 3 view .LVU483
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1733              		.loc 1 721 3 view .LVU484
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1734              		.loc 1 721 6 is_stmt 0 view .LVU485
+ 1735 0000 B0F1407F 		cmp	r0, #50331648
+ 1736 0004 01D0     		beq	.L160
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1737              		.loc 1 716 12 view .LVU486
+ 1738 0006 0020     		movs	r0, #0
+ 1739              	.LVL140:
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1740              		.loc 1 755 1 view .LVU487
+ 1741 0008 7047     		bx	lr
+ 1742              	.LVL141:
+ 1743              	.L160:
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 1744              		.loc 1 715 1 view .LVU488
+ 1745 000a 08B5     		push	{r3, lr}
+ARM GAS  /tmp/ccTMI75D.s 			page 135
+
+
+ 1746              	.LCFI7:
+ 1747              		.cfi_def_cfa_offset 8
+ 1748              		.cfi_offset 3, -8
+ 1749              		.cfi_offset 14, -4
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1750              		.loc 1 724 5 is_stmt 1 view .LVU489
+ 1751              	.LVL142:
+ 1752              	.LBB332:
+ 1753              	.LBI332:
+2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1754              		.loc 2 2746 26 view .LVU490
+ 1755              	.LBB333:
+2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1756              		.loc 2 2748 3 view .LVU491
+2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1757              		.loc 2 2748 21 is_stmt 0 view .LVU492
+ 1758 000c 154B     		ldr	r3, .L162
+ 1759 000e D3F89030 		ldr	r3, [r3, #144]
+2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1760              		.loc 2 2748 10 view .LVU493
+ 1761 0012 03F04073 		and	r3, r3, #50331648
+ 1762              	.LVL143:
+2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1763              		.loc 2 2748 10 view .LVU494
+ 1764              	.LBE333:
+ 1765              	.LBE332:
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 1766              		.loc 1 724 5 view .LVU495
+ 1767 0016 B3F1007F 		cmp	r3, #33554432
+ 1768 001a 14D0     		beq	.L149
+ 1769 001c B3F1407F 		cmp	r3, #50331648
+ 1770 0020 18D0     		beq	.L150
+ 1771 0022 B3F1807F 		cmp	r3, #16777216
+ 1772 0026 06D0     		beq	.L161
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1773              		.loc 1 749 9 is_stmt 1 view .LVU496
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1774              		.loc 1 749 27 is_stmt 0 view .LVU497
+ 1775 0028 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1776              	.LVL144:
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 1777              		.loc 1 749 27 view .LVU498
+ 1778 002c FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 1779              	.LVL145:
+ 1780 0030 FFF7FEFF 		bl	RCC_GetPCLK1ClockFreq
+ 1781              	.LVL146:
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 1782              		.loc 1 750 9 is_stmt 1 view .LVU499
+ 1783              	.L147:
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1784              		.loc 1 755 1 is_stmt 0 view .LVU500
+ 1785 0034 08BD     		pop	{r3, pc}
+ 1786              	.LVL147:
+ 1787              	.L161:
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1788              		.loc 1 727 9 is_stmt 1 view .LVU501
+ 1789              	.LBB334:
+ARM GAS  /tmp/ccTMI75D.s 			page 136
+
+
+ 1790              	.LBI334:
+2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1791              		.loc 2 2192 26 view .LVU502
+ 1792              	.LBB335:
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1793              		.loc 2 2194 3 view .LVU503
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1794              		.loc 2 2194 11 is_stmt 0 view .LVU504
+ 1795 0036 0B4B     		ldr	r3, .L162
+ 1796 0038 586F     		ldr	r0, [r3, #116]
+ 1797              	.LVL148:
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1798              		.loc 2 2194 11 view .LVU505
+ 1799              	.LBE335:
+ 1800              	.LBE334:
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1801              		.loc 1 727 12 view .LVU506
+ 1802 003a 10F00200 		ands	r0, r0, #2
+ 1803 003e F9D0     		beq	.L147
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1804              		.loc 1 729 27 view .LVU507
+ 1805 0040 4FF4FA40 		mov	r0, #32000
+ 1806 0044 F6E7     		b	.L147
+ 1807              	.LVL149:
+ 1808              	.L149:
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1809              		.loc 1 734 9 is_stmt 1 view .LVU508
+ 1810              	.LBB336:
+ 1811              	.LBI336:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1812              		.loc 2 2030 26 view .LVU509
+ 1813              	.LBB337:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1814              		.loc 2 2032 3 view .LVU510
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1815              		.loc 2 2032 11 is_stmt 0 view .LVU511
+ 1816 0046 074B     		ldr	r3, .L162
+ 1817 0048 1868     		ldr	r0, [r3]
+ 1818              	.LVL150:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1819              		.loc 2 2032 11 view .LVU512
+ 1820              	.LBE337:
+ 1821              	.LBE336:
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1822              		.loc 1 734 12 view .LVU513
+ 1823 004a 10F00200 		ands	r0, r0, #2
+ 1824 004e F1D0     		beq	.L147
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1825              		.loc 1 736 27 view .LVU514
+ 1826 0050 0548     		ldr	r0, .L162+4
+ 1827 0052 EFE7     		b	.L147
+ 1828              	.LVL151:
+ 1829              	.L150:
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1830              		.loc 1 741 9 is_stmt 1 view .LVU515
+ 1831              	.LBB338:
+ 1832              	.LBI338:
+ARM GAS  /tmp/ccTMI75D.s 			page 137
+
+
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1833              		.loc 2 2154 26 view .LVU516
+ 1834              	.LBB339:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1835              		.loc 2 2156 3 view .LVU517
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1836              		.loc 2 2156 11 is_stmt 0 view .LVU518
+ 1837 0054 034B     		ldr	r3, .L162
+ 1838 0056 186F     		ldr	r0, [r3, #112]
+ 1839              	.LVL152:
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1840              		.loc 2 2156 11 view .LVU519
+ 1841              	.LBE339:
+ 1842              	.LBE338:
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 1843              		.loc 1 741 12 view .LVU520
+ 1844 0058 10F00200 		ands	r0, r0, #2
+ 1845 005c EAD0     		beq	.L147
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 1846              		.loc 1 743 27 view .LVU521
+ 1847 005e 4FF40040 		mov	r0, #32768
+ 1848              	.LVL153:
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 1849              		.loc 1 754 3 is_stmt 1 view .LVU522
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 1850              		.loc 1 754 10 is_stmt 0 view .LVU523
+ 1851 0062 E7E7     		b	.L147
+ 1852              	.L163:
+ 1853              		.align	2
+ 1854              	.L162:
+ 1855 0064 00380240 		.word	1073887232
+ 1856 0068 0024F400 		.word	16000000
+ 1857              		.cfi_endproc
+ 1858              	.LFE301:
+ 1860              		.section	.text.LL_RCC_GetDFSDMClockFreq,"ax",%progbits
+ 1861              		.align	1
+ 1862              		.global	LL_RCC_GetDFSDMClockFreq
+ 1863              		.syntax unified
+ 1864              		.thumb
+ 1865              		.thumb_func
+ 1866              		.fpu fpv5-d16
+ 1868              	LL_RCC_GetDFSDMClockFreq:
+ 1869              	.LVL154:
+ 1870              	.LFB307:
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 1871              		.loc 1 1077 1 is_stmt 1 view -0
+ 1872              		.cfi_startproc
+ 1873              		@ args = 0, pretend = 0, frame = 0
+ 1874              		@ frame_needed = 0, uses_anonymous_args = 0
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 1875              		.loc 1 1077 1 is_stmt 0 view .LVU525
+ 1876 0000 08B5     		push	{r3, lr}
+ 1877              	.LCFI8:
+ 1878              		.cfi_def_cfa_offset 8
+ 1879              		.cfi_offset 3, -8
+ 1880              		.cfi_offset 14, -4
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ARM GAS  /tmp/ccTMI75D.s 			page 138
+
+
+ 1881              		.loc 1 1078 3 is_stmt 1 view .LVU526
+ 1882              	.LVL155:
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1883              		.loc 1 1081 3 view .LVU527
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1884              		.loc 1 1084 3 view .LVU528
+ 1885              	.LBB340:
+ 1886              	.LBI340:
+2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1887              		.loc 2 2891 26 view .LVU529
+ 1888              	.LBB341:
+2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1889              		.loc 2 2893 3 view .LVU530
+2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1890              		.loc 2 2893 21 is_stmt 0 view .LVU531
+ 1891 0002 084B     		ldr	r3, .L169
+ 1892 0004 D3F88C30 		ldr	r3, [r3, #140]
+2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1893              		.loc 2 2893 10 view .LVU532
+ 1894 0008 1840     		ands	r0, r0, r3
+ 1895              	.LVL156:
+2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1896              		.loc 2 2893 10 view .LVU533
+ 1897              	.LBE341:
+ 1898              	.LBE340:
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 1899              		.loc 1 1084 3 view .LVU534
+ 1900 000a B0F1007F 		cmp	r0, #33554432
+ 1901 000e 06D0     		beq	.L168
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 1902              		.loc 1 1092 7 is_stmt 1 view .LVU535
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 1903              		.loc 1 1092 25 is_stmt 0 view .LVU536
+ 1904 0010 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1905              	.LVL157:
+ 1906 0014 FFF7FEFF 		bl	RCC_GetHCLKClockFreq
+ 1907              	.LVL158:
+ 1908 0018 FFF7FEFF 		bl	RCC_GetPCLK2ClockFreq
+ 1909              	.LVL159:
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 1910              		.loc 1 1093 7 is_stmt 1 view .LVU537
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 1911              		.loc 1 1096 3 view .LVU538
+ 1912              	.L164:
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1913              		.loc 1 1097 1 is_stmt 0 view .LVU539
+ 1914 001c 08BD     		pop	{r3, pc}
+ 1915              	.LVL160:
+ 1916              	.L168:
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 1917              		.loc 1 1087 7 is_stmt 1 view .LVU540
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 1918              		.loc 1 1087 25 is_stmt 0 view .LVU541
+ 1919 001e FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 1920              	.LVL161:
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 1921              		.loc 1 1088 7 is_stmt 1 view .LVU542
+ARM GAS  /tmp/ccTMI75D.s 			page 139
+
+
+ 1922 0022 FBE7     		b	.L164
+ 1923              	.L170:
+ 1924              		.align	2
+ 1925              	.L169:
+ 1926 0024 00380240 		.word	1073887232
+ 1927              		.cfi_endproc
+ 1928              	.LFE307:
+ 1930              		.section	.text.RCC_PLL_GetFreqDomain_48M,"ax",%progbits
+ 1931              		.align	1
+ 1932              		.global	RCC_PLL_GetFreqDomain_48M
+ 1933              		.syntax unified
+ 1934              		.thumb
+ 1935              		.thumb_func
+ 1936              		.fpu fpv5-d16
+ 1938              	RCC_PLL_GetFreqDomain_48M:
+ 1939              	.LFB316:
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return PLL clock frequency used for 48 MHz domain
+1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval PLL clock frequency (in Hz)
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_48M(void)
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 1940              		.loc 1 1326 1 view -0
+ 1941              		.cfi_startproc
+ 1942              		@ args = 0, pretend = 0, frame = 0
+ 1943              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1944              		@ link register save eliminated.
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t pllinputfreq = 0U, pllsource = 0U;
+ 1945              		.loc 1 1327 3 view .LVU544
+ 1946              	.LVL162:
+1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      48M Domain clock = PLL_VCO / PLLQ
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   pllsource = LL_RCC_PLL_GetMainSource();
+ 1947              		.loc 1 1332 3 view .LVU545
+ 1948              	.LBB342:
+ 1949              	.LBI342:
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1950              		.loc 2 3461 26 view .LVU546
+ 1951              	.LBB343:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1952              		.loc 2 3463 3 view .LVU547
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1953              		.loc 2 3463 21 is_stmt 0 view .LVU548
+ 1954 0000 0C4B     		ldr	r3, .L174
+ 1955 0002 5B68     		ldr	r3, [r3, #4]
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1956              		.loc 2 3463 10 view .LVU549
+ 1957 0004 03F48003 		and	r3, r3, #4194304
+ 1958              	.LVL163:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1959              		.loc 2 3463 10 view .LVU550
+ 1960              	.LBE343:
+ 1961              	.LBE342:
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ARM GAS  /tmp/ccTMI75D.s 			page 140
+
+
+1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (pllsource)
+ 1962              		.loc 1 1334 3 is_stmt 1 view .LVU551
+ 1963 0008 8BB9     		cbnz	r3, .L173
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+ 1964              		.loc 1 1337 20 is_stmt 0 view .LVU552
+ 1965 000a 0B4B     		ldr	r3, .L174+4
+ 1966              	.LVL164:
+ 1967              	.L172:
+1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSE_VALUE;
+1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ 1968              		.loc 1 1348 3 is_stmt 1 view .LVU553
+ 1969              	.LBB344:
+ 1970              	.LBI344:
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1971              		.loc 2 3601 26 view .LVU554
+ 1972              	.LBB345:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1973              		.loc 2 3603 3 view .LVU555
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1974              		.loc 2 3603 21 is_stmt 0 view .LVU556
+ 1975 000c 094A     		ldr	r2, .L174
+ 1976 000e 5068     		ldr	r0, [r2, #4]
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1977              		.loc 2 3603 10 view .LVU557
+ 1978 0010 00F03F00 		and	r0, r0, #63
+ 1979              	.LBE345:
+ 1980              	.LBE344:
+ 1981              		.loc 1 1348 10 view .LVU558
+ 1982 0014 B3FBF0F3 		udiv	r3, r3, r0
+ 1983              	.LVL165:
+ 1984              	.LBB346:
+ 1985              	.LBI346:
+3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1986              		.loc 2 3471 26 is_stmt 1 view .LVU559
+ 1987              	.LBB347:
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1988              		.loc 2 3473 3 view .LVU560
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1989              		.loc 2 3473 21 is_stmt 0 view .LVU561
+ 1990 0018 5068     		ldr	r0, [r2, #4]
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1991              		.loc 2 3473 10 view .LVU562
+ 1992 001a C0F38810 		ubfx	r0, r0, #6, #9
+ 1993              	.LBE347:
+ 1994              	.LBE346:
+ 1995              		.loc 1 1348 10 view .LVU563
+ARM GAS  /tmp/ccTMI75D.s 			page 141
+
+
+ 1996 001e 00FB03F3 		mul	r3, r0, r3
+ 1997              	.LBB348:
+ 1998              	.LBI348:
+3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1999              		.loc 2 3510 26 is_stmt 1 view .LVU564
+ 2000              	.LBB349:
+3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2001              		.loc 2 3512 3 view .LVU565
+3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2002              		.loc 2 3512 21 is_stmt 0 view .LVU566
+ 2003 0022 5068     		ldr	r0, [r2, #4]
+ 2004              	.LBE349:
+ 2005              	.LBE348:
+ 2006              		.loc 1 1348 10 view .LVU567
+ 2007 0024 C0F30360 		ubfx	r0, r0, #24, #4
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2008              		.loc 1 1350 1 view .LVU568
+ 2009 0028 B3FBF0F0 		udiv	r0, r3, r0
+ 2010 002c 7047     		bx	lr
+ 2011              	.LVL166:
+ 2012              	.L173:
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 2013              		.loc 1 1341 20 view .LVU569
+ 2014 002e 034B     		ldr	r3, .L174+8
+ 2015              	.LVL167:
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 2016              		.loc 1 1341 20 view .LVU570
+ 2017 0030 ECE7     		b	.L172
+ 2018              	.L175:
+ 2019 0032 00BF     		.align	2
+ 2020              	.L174:
+ 2021 0034 00380240 		.word	1073887232
+ 2022 0038 0024F400 		.word	16000000
+ 2023 003c 40787D01 		.word	25000000
+ 2024              		.cfi_endproc
+ 2025              	.LFE316:
+ 2027              		.section	.text.RCC_PLLSAI_GetFreqDomain_SAI,"ax",%progbits
+ 2028              		.align	1
+ 2029              		.global	RCC_PLLSAI_GetFreqDomain_SAI
+ 2030              		.syntax unified
+ 2031              		.thumb
+ 2032              		.thumb_func
+ 2033              		.fpu fpv5-d16
+ 2035              	RCC_PLLSAI_GetFreqDomain_SAI:
+ 2036              	.LFB317:
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DSI)
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return PLL clock frequency used for DSI clock
+1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval PLL clock frequency (in Hz)
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_DSI(void)
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t pllinputfreq = 0U, pllsource = 0U;
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ARM GAS  /tmp/ccTMI75D.s 			page 142
+
+
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      DSICLK = PLL_VCO / PLLR
+1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   pllsource = LL_RCC_PLL_GetMainSource();
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (pllsource)
+1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSE_VALUE;
+1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
+1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DSI */
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return PLLSAI clock frequency used for SAI1 and SAI2 domains
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval PLLSAI clock frequency (in Hz)
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 2037              		.loc 1 1387 1 is_stmt 1 view -0
+ 2038              		.cfi_startproc
+ 2039              		@ args = 0, pretend = 0, frame = 0
+ 2040              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2041              		@ link register save eliminated.
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t pllinputfreq = 0U, pllsource = 0U;
+ 2042              		.loc 1 1388 3 view .LVU572
+ 2043              	.LVL168:
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
+1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      SAI1 and SAI2 domains clock  = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   pllsource = LL_RCC_PLL_GetMainSource();
+ 2044              		.loc 1 1393 3 view .LVU573
+ 2045              	.LBB350:
+ 2046              	.LBI350:
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2047              		.loc 2 3461 26 view .LVU574
+ 2048              	.LBB351:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2049              		.loc 2 3463 3 view .LVU575
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2050              		.loc 2 3463 21 is_stmt 0 view .LVU576
+ 2051 0000 104B     		ldr	r3, .L179
+ 2052 0002 5B68     		ldr	r3, [r3, #4]
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2053              		.loc 2 3463 10 view .LVU577
+ 2054 0004 03F48003 		and	r3, r3, #4194304
+ 2055              	.LVL169:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2056              		.loc 2 3463 10 view .LVU578
+ARM GAS  /tmp/ccTMI75D.s 			page 143
+
+
+ 2057              	.LBE351:
+ 2058              	.LBE350:
+1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (pllsource)
+ 2059              		.loc 1 1395 3 is_stmt 1 view .LVU579
+ 2060 0008 CBB9     		cbnz	r3, .L178
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+ 2061              		.loc 1 1398 20 is_stmt 0 view .LVU580
+ 2062 000a 0F48     		ldr	r0, .L179+4
+ 2063              	.L177:
+ 2064              	.LVL170:
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSE_VALUE;
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ 2065              		.loc 1 1409 3 is_stmt 1 view .LVU581
+ 2066              	.LBB352:
+ 2067              	.LBI352:
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2068              		.loc 2 3601 26 view .LVU582
+ 2069              	.LBB353:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2070              		.loc 2 3603 3 view .LVU583
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2071              		.loc 2 3603 21 is_stmt 0 view .LVU584
+ 2072 000c 0D4A     		ldr	r2, .L179
+ 2073 000e 5368     		ldr	r3, [r2, #4]
+ 2074              	.LVL171:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2075              		.loc 2 3603 10 view .LVU585
+ 2076 0010 03F03F03 		and	r3, r3, #63
+ 2077              	.LBE353:
+ 2078              	.LBE352:
+ 2079              		.loc 1 1409 10 view .LVU586
+ 2080 0014 B0FBF3F0 		udiv	r0, r0, r3
+ 2081              	.LVL172:
+ 2082              	.LBB354:
+ 2083              	.LBI354:
+4182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLLSAI used for SAI1 and SAI2 domain clock
+4186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+4187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+4188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLQ can be written only when PLLSAI is disabled
+4189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This can be selected for SAI1 and SAI2
+4190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_SAI\n
+4191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_SAI\n
+ARM GAS  /tmp/ccTMI75D.s 			page 144
+
+
+4192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_SAI\n
+4193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLSAICFGR   PLLSAIQ       LL_RCC_PLLSAI_ConfigDomain_SAI\n
+4194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR1     PLLSAIDIVQ    LL_RCC_PLLSAI_ConfigDomain_SAI
+4195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+4196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+4197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+4198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+4199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+4200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+4201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+4202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+4203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+4204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+4205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+4206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+4207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+4208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+4209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+4210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+4211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+4212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+4213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+4214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+4215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+4216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+4217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+4218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+4219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+4220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+4221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+4222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+4223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+4224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+4225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+4226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+4227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+4228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+4229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+4230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+4231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+4232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+4233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+4234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+4235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+4236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+4237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+4238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+4239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+4240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+4241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+4242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+4243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+4244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+4245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+4246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+4247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+4248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+ARM GAS  /tmp/ccTMI75D.s 			page 145
+
+
+4249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+4250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+4251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+4252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+4253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+4254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+4255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+4256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+4257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+4258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+4259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+4260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+4261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+4262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLQ This parameter can be one of the following values:
+4263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+4264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+4265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+4266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+4267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+4268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+4269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+4270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+4271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+4272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+4273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+4274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+4275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+4276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+4277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLDIVQ This parameter can be one of the following values:
+4278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+4279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+4280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+4281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+4282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+4283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+4284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+4285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+4286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+4287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+4288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+4289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+4290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+4291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+4292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+4293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+4294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+4295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+4296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+4297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+4298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+4299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+4300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+4301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+4302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+4303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+4304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+4305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+ARM GAS  /tmp/ccTMI75D.s 			page 146
+
+
+4306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+4307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+4308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+4309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+4310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+4311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, 
+4313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+4315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICF
+4316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, PLLDIVQ);
+4317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief Configure PLLSAI used for 48Mhz domain clock
+4321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+4322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+4323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLP can be written only when PLLSAI is disabled
+4324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This  can be selected for USB, RNG, SDMMC1
+4325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_48M\n
+4326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_48M\n
+4327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_48M\n
+4328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLSAICFGR   PLLSAIP       LL_RCC_PLLSAI_ConfigDomain_48M
+4329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+4330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+4331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+4332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+4333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+4334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+4335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+4336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+4337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+4338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+4339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+4340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+4341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+4342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+4343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+4344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+4345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+4346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+4347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+4348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+4349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+4350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+4351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+4352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+4353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+4354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+4355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+4356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+4357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+4358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+4359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+4360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+4361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+4362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+ARM GAS  /tmp/ccTMI75D.s 			page 147
+
+
+4363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+4364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+4365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+4366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+4367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+4368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+4369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+4370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+4371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+4372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+4373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+4374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+4375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+4376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+4377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+4378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+4379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+4380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+4381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+4382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+4383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+4384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+4385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+4386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+4387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+4388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+4389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+4390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+4391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+4392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+4393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+4394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+4395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+4396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLP This parameter can be one of the following values:
+4397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+4398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+4399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+4400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+4401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+4402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, 
+4404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+4406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICF
+4407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(LTDC)
+4410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLLSAI used for LTDC domain clock
+4412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+4413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+4414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLR can be written only when PLLSAI is disabled
+4415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This  can be selected for LTDC
+4416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+4417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+4418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+4419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLSAICFGR   PLLSAIR       LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+ARM GAS  /tmp/ccTMI75D.s 			page 148
+
+
+4420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR1     PLLSAIDIVR    LL_RCC_PLLSAI_ConfigDomain_LTDC
+4421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+4422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+4423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+4424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+4425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+4426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+4427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+4428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+4429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+4430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+4431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+4432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+4433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+4434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+4435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+4436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+4437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+4438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+4439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+4440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+4441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+4442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+4443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+4444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+4445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+4446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+4447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+4448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+4449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+4450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+4451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+4452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+4453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+4454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+4455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+4456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+4457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+4458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+4459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+4460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+4461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+4462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+4463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+4464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+4465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+4466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+4467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+4468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+4469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+4470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+4471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+4472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+4473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+4474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+4475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+4476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+ARM GAS  /tmp/ccTMI75D.s 			page 149
+
+
+4477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+4478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+4479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+4480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+4481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+4482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+4483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+4484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+4485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+4486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+4487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+4488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLR This parameter can be one of the following values:
+4489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+4490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+4491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+4492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+4493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+4494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+4495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLDIVR This parameter can be one of the following values:
+4496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+4497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+4498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+4499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+4500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+4501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN,
+4503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+4505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICF
+4506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, PLLDIVR);
+4507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LTDC */
+4509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get SAIPLL multiplication factor for VCO
+4512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLSAICFGR  PLLSAIN      LL_RCC_PLLSAI_GetN
+4513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between 50 and 432
+4514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
+ 2084              		.loc 2 4515 26 is_stmt 1 view .LVU587
+ 2085              	.LBB355:
+4516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos
+ 2086              		.loc 2 4517 3 view .LVU588
+ 2087              		.loc 2 4517 21 is_stmt 0 view .LVU589
+ 2088 0018 D2F88830 		ldr	r3, [r2, #136]
+ 2089              		.loc 2 4517 10 view .LVU590
+ 2090 001c C3F38813 		ubfx	r3, r3, #6, #9
+ 2091              	.LBE355:
+ 2092              	.LBE354:
+ 2093              		.loc 1 1409 10 view .LVU591
+ 2094 0020 03FB00F0 		mul	r0, r3, r0
+ 2095              	.LBB356:
+ 2096              	.LBI356:
+4518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ARM GAS  /tmp/ccTMI75D.s 			page 150
+
+
+4521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get SAIPLL division factor for PLLSAIQ
+4522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLSAICFGR  PLLSAIQ      LL_RCC_PLLSAI_GetQ
+4523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+4525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+4526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+4527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+4528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+4529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+4530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+4531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+4532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+4533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+4534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+4535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+4536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+4537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+4538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
+ 2097              		.loc 2 4539 26 is_stmt 1 view .LVU592
+ 2098              	.LBB357:
+4540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
+ 2099              		.loc 2 4541 3 view .LVU593
+ 2100              		.loc 2 4541 21 is_stmt 0 view .LVU594
+ 2101 0024 D2F88830 		ldr	r3, [r2, #136]
+ 2102              	.LBE357:
+ 2103              	.LBE356:
+ 2104              		.loc 1 1409 10 view .LVU595
+ 2105 0028 C3F30363 		ubfx	r3, r3, #24, #4
+ 2106              	.LBB358:
+ 2107              	.LBI358:
+4542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLSAICFGR_PLLSAIR)
+4545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get SAIPLL division factor for PLLSAIR
+4547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used for PLLSAICLK (SAI clock)
+4548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLSAICFGR  PLLSAIR      LL_RCC_PLLSAI_GetR
+4549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+4551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+4552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+4553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+4554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+4555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+4556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
+4558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
+4560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLSAICFGR_PLLSAIR */
+4562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get SAIPLL division factor for PLLSAIP
+4565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used for PLL48MCLK (48M domain clock)
+4566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLSAICFGR  PLLSAIP      LL_RCC_PLLSAI_GetP
+ARM GAS  /tmp/ccTMI75D.s 			page 151
+
+
+4567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+4569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+4570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+4571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+4572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
+4574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
+4576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get SAIPLL division factor for PLLSAIDIVQ
+4580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
+4581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1   PLLSAIDIVQ      LL_RCC_PLLSAI_GetDIVQ
+4582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+4584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+4585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+4586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+4587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+4588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+4589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+4590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+4591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+4592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+4593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+4594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+4595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+4596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+4597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+4598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+4599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+4600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+4601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+4602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+4603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+4604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+4605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+4606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+4607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+4608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+4609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+4610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+4611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+4612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+4613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+4614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+4615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
+ 2108              		.loc 2 4616 26 is_stmt 1 view .LVU596
+ 2109              	.LBB359:
+4617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ));
+ 2110              		.loc 2 4618 3 view .LVU597
+ 2111              		.loc 2 4618 21 is_stmt 0 view .LVU598
+ 2112 002c D2F88C20 		ldr	r2, [r2, #140]
+ARM GAS  /tmp/ccTMI75D.s 			page 152
+
+
+ 2113              	.LBE359:
+ 2114              	.LBE358:
+ 2115              		.loc 1 1409 10 view .LVU599
+ 2116 0030 C2F30422 		ubfx	r2, r2, #8, #5
+ 2117 0034 02FB0333 		mla	r3, r2, r3, r3
+1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                         LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_G
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2118              		.loc 1 1411 1 view .LVU600
+ 2119 0038 B0FBF3F0 		udiv	r0, r0, r3
+ 2120 003c 7047     		bx	lr
+ 2121              	.LVL173:
+ 2122              	.L178:
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 2123              		.loc 1 1402 20 view .LVU601
+ 2124 003e 0348     		ldr	r0, .L179+8
+ 2125 0040 E4E7     		b	.L177
+ 2126              	.L180:
+ 2127 0042 00BF     		.align	2
+ 2128              	.L179:
+ 2129 0044 00380240 		.word	1073887232
+ 2130 0048 0024F400 		.word	16000000
+ 2131 004c 40787D01 		.word	25000000
+ 2132              		.cfi_endproc
+ 2133              	.LFE317:
+ 2135              		.section	.text.RCC_PLLSAI_GetFreqDomain_48M,"ax",%progbits
+ 2136              		.align	1
+ 2137              		.global	RCC_PLLSAI_GetFreqDomain_48M
+ 2138              		.syntax unified
+ 2139              		.thumb
+ 2140              		.thumb_func
+ 2141              		.fpu fpv5-d16
+ 2143              	RCC_PLLSAI_GetFreqDomain_48M:
+ 2144              	.LFB318:
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return PLLSAI clock frequency used for 48Mhz domain
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval PLLSAI clock frequency (in Hz)
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 2145              		.loc 1 1418 1 is_stmt 1 view -0
+ 2146              		.cfi_startproc
+ 2147              		@ args = 0, pretend = 0, frame = 0
+ 2148              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2149              		@ link register save eliminated.
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t pllinputfreq = 0U, pllsource = 0U;
+ 2150              		.loc 1 1419 3 view .LVU603
+ 2151              	.LVL174:
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
+1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      48M Domain clock  = PLLSAI_VCO / PLLSAIP
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   pllsource = LL_RCC_PLL_GetMainSource();
+ 2152              		.loc 1 1424 3 view .LVU604
+ 2153              	.LBB360:
+ 2154              	.LBI360:
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ARM GAS  /tmp/ccTMI75D.s 			page 153
+
+
+ 2155              		.loc 2 3461 26 view .LVU605
+ 2156              	.LBB361:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2157              		.loc 2 3463 3 view .LVU606
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2158              		.loc 2 3463 21 is_stmt 0 view .LVU607
+ 2159 0000 0E4B     		ldr	r3, .L184
+ 2160 0002 5B68     		ldr	r3, [r3, #4]
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2161              		.loc 2 3463 10 view .LVU608
+ 2162 0004 03F48003 		and	r3, r3, #4194304
+ 2163              	.LVL175:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2164              		.loc 2 3463 10 view .LVU609
+ 2165              	.LBE361:
+ 2166              	.LBE360:
+1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (pllsource)
+ 2167              		.loc 1 1426 3 is_stmt 1 view .LVU610
+ 2168 0008 ABB9     		cbnz	r3, .L183
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+ 2169              		.loc 1 1429 20 is_stmt 0 view .LVU611
+ 2170 000a 0D48     		ldr	r0, .L184+4
+ 2171              	.L182:
+ 2172              	.LVL176:
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSE_VALUE;
+1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ 2173              		.loc 1 1440 3 is_stmt 1 view .LVU612
+ 2174              	.LBB362:
+ 2175              	.LBI362:
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2176              		.loc 2 3601 26 view .LVU613
+ 2177              	.LBB363:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2178              		.loc 2 3603 3 view .LVU614
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2179              		.loc 2 3603 21 is_stmt 0 view .LVU615
+ 2180 000c 0B4B     		ldr	r3, .L184
+ 2181              	.LVL177:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2182              		.loc 2 3603 21 view .LVU616
+ 2183 000e 5A68     		ldr	r2, [r3, #4]
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2184              		.loc 2 3603 10 view .LVU617
+ 2185 0010 02F03F02 		and	r2, r2, #63
+ 2186              	.LBE363:
+ARM GAS  /tmp/ccTMI75D.s 			page 154
+
+
+ 2187              	.LBE362:
+ 2188              		.loc 1 1440 10 view .LVU618
+ 2189 0014 B0FBF2F0 		udiv	r0, r0, r2
+ 2190              	.LVL178:
+ 2191              	.LBB364:
+ 2192              	.LBI364:
+4515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2193              		.loc 2 4515 26 is_stmt 1 view .LVU619
+ 2194              	.LBB365:
+4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2195              		.loc 2 4517 3 view .LVU620
+4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2196              		.loc 2 4517 21 is_stmt 0 view .LVU621
+ 2197 0018 D3F88820 		ldr	r2, [r3, #136]
+4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2198              		.loc 2 4517 10 view .LVU622
+ 2199 001c C2F38812 		ubfx	r2, r2, #6, #9
+ 2200              	.LBE365:
+ 2201              	.LBE364:
+ 2202              		.loc 1 1440 10 view .LVU623
+ 2203 0020 02FB00F0 		mul	r0, r2, r0
+ 2204              	.LBB366:
+ 2205              	.LBI366:
+4573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2206              		.loc 2 4573 26 is_stmt 1 view .LVU624
+ 2207              	.LBB367:
+4575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2208              		.loc 2 4575 3 view .LVU625
+4575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2209              		.loc 2 4575 21 is_stmt 0 view .LVU626
+ 2210 0024 D3F88830 		ldr	r3, [r3, #136]
+ 2211              	.LBE367:
+ 2212              	.LBE366:
+ 2213              		.loc 1 1440 10 view .LVU627
+ 2214 0028 C3F30143 		ubfx	r3, r3, #16, #2
+ 2215 002c 0133     		adds	r3, r3, #1
+ 2216 002e 5B00     		lsls	r3, r3, #1
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                         LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2217              		.loc 1 1442 1 view .LVU628
+ 2218 0030 B0FBF3F0 		udiv	r0, r0, r3
+ 2219 0034 7047     		bx	lr
+ 2220              	.LVL179:
+ 2221              	.L183:
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 2222              		.loc 1 1433 20 view .LVU629
+ 2223 0036 0348     		ldr	r0, .L184+8
+ 2224 0038 E8E7     		b	.L182
+ 2225              	.L185:
+ 2226 003a 00BF     		.align	2
+ 2227              	.L184:
+ 2228 003c 00380240 		.word	1073887232
+ 2229 0040 0024F400 		.word	16000000
+ 2230 0044 40787D01 		.word	25000000
+ 2231              		.cfi_endproc
+ 2232              	.LFE318:
+ 2234              		.section	.text.LL_RCC_GetSDMMCClockFreq,"ax",%progbits
+ARM GAS  /tmp/ccTMI75D.s 			page 155
+
+
+ 2235              		.align	1
+ 2236              		.global	LL_RCC_GetSDMMCClockFreq
+ 2237              		.syntax unified
+ 2238              		.thumb
+ 2239              		.thumb_func
+ 2240              		.fpu fpv5-d16
+ 2242              	LL_RCC_GetSDMMCClockFreq:
+ 2243              	.LVL180:
+ 2244              	.LFB303:
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 2245              		.loc 1 886 1 is_stmt 1 view -0
+ 2246              		.cfi_startproc
+ 2247              		@ args = 0, pretend = 0, frame = 0
+ 2248              		@ frame_needed = 0, uses_anonymous_args = 0
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 2249              		.loc 1 886 1 is_stmt 0 view .LVU631
+ 2250 0000 08B5     		push	{r3, lr}
+ 2251              	.LCFI9:
+ 2252              		.cfi_def_cfa_offset 8
+ 2253              		.cfi_offset 3, -8
+ 2254              		.cfi_offset 14, -4
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2255              		.loc 1 887 3 is_stmt 1 view .LVU632
+ 2256              	.LVL181:
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2257              		.loc 1 890 3 view .LVU633
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 2258              		.loc 1 892 3 view .LVU634
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 2259              		.loc 1 892 6 is_stmt 0 view .LVU635
+ 2260 0002 B0F1805F 		cmp	r0, #268435456
+ 2261 0006 16D0     		beq	.L194
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      {
+ 2262              		.loc 1 927 6 is_stmt 1 view .LVU636
+ 2263              	.LVL182:
+ 2264              	.LBB368:
+ 2265              	.LBI368:
+2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2266              		.loc 2 2790 26 view .LVU637
+ 2267              	.LBB369:
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2268              		.loc 2 2792 3 view .LVU638
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2269              		.loc 2 2792 21 is_stmt 0 view .LVU639
+ 2270 0008 214B     		ldr	r3, .L195
+ 2271 000a D3F89030 		ldr	r3, [r3, #144]
+ 2272 000e 0340     		ands	r3, r3, r0
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2273              		.loc 2 2792 10 view .LVU640
+ 2274 0010 40EA1340 		orr	r0, r0, r3, lsr #16
+ 2275              	.LVL183:
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2276              		.loc 2 2792 10 view .LVU641
+ 2277              	.LBE369:
+ 2278              	.LBE368:
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      {
+ 2279              		.loc 1 927 6 view .LVU642
+ARM GAS  /tmp/ccTMI75D.s 			page 156
+
+
+ 2280 0014 B0F1005F 		cmp	r0, #536870912
+ 2281 0018 37D1     		bne	.L191
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****          {
+ 2282              		.loc 1 930 10 is_stmt 1 view .LVU643
+ 2283              	.LVL184:
+ 2284              	.LBB370:
+ 2285              	.LBI370:
+2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2286              		.loc 2 2804 26 view .LVU644
+ 2287              	.LBB371:
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2288              		.loc 2 2806 3 view .LVU645
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2289              		.loc 2 2806 21 is_stmt 0 view .LVU646
+ 2290 001a 1D4B     		ldr	r3, .L195
+ 2291 001c D3F89030 		ldr	r3, [r3, #144]
+ 2292              	.LVL185:
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2293              		.loc 2 2806 21 view .LVU647
+ 2294              	.LBE371:
+ 2295              	.LBE370:
+ 2296 0020 13F0006F 		tst	r3, #134217728
+ 2297 0024 29D1     		bne	.L192
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 2298              		.loc 1 933 14 is_stmt 1 view .LVU648
+ 2299              	.LBB372:
+ 2300              	.LBI372:
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2301              		.loc 2 3153 26 view .LVU649
+ 2302              	.LBB373:
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2303              		.loc 2 3155 3 view .LVU650
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2304              		.loc 2 3155 11 is_stmt 0 view .LVU651
+ 2305 0026 1A4B     		ldr	r3, .L195
+ 2306 0028 1868     		ldr	r0, [r3]
+ 2307              	.LBE373:
+ 2308              	.LBE372:
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 2309              		.loc 1 933 17 view .LVU652
+ 2310 002a 10F00070 		ands	r0, r0, #33554432
+ 2311 002e 2ED0     		beq	.L186
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 2312              		.loc 1 935 16 is_stmt 1 view .LVU653
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 2313              		.loc 1 935 34 is_stmt 0 view .LVU654
+ 2314 0030 FFF7FEFF 		bl	RCC_PLL_GetFreqDomain_48M
+ 2315              	.LVL186:
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 2316              		.loc 1 935 34 view .LVU655
+ 2317 0034 2BE0     		b	.L186
+ 2318              	.LVL187:
+ 2319              	.L194:
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 2320              		.loc 1 895 5 is_stmt 1 view .LVU656
+ 2321              	.LBB374:
+ 2322              	.LBI374:
+ARM GAS  /tmp/ccTMI75D.s 			page 157
+
+
+2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2323              		.loc 2 2790 26 view .LVU657
+ 2324              	.LBB375:
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2325              		.loc 2 2792 3 view .LVU658
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2326              		.loc 2 2792 21 is_stmt 0 view .LVU659
+ 2327 0036 164B     		ldr	r3, .L195
+ 2328 0038 D3F89030 		ldr	r3, [r3, #144]
+ 2329 003c 0340     		ands	r3, r3, r0
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2330              		.loc 2 2792 10 view .LVU660
+ 2331 003e 40EA1340 		orr	r0, r0, r3, lsr #16
+ 2332              	.LVL188:
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2333              		.loc 2 2792 10 view .LVU661
+ 2334              	.LBE375:
+ 2335              	.LBE374:
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 2336              		.loc 1 895 5 view .LVU662
+ 2337 0042 B0F1805F 		cmp	r0, #268435456
+ 2338 0046 15D1     		bne	.L188
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 2339              		.loc 1 898 9 is_stmt 1 view .LVU663
+ 2340              	.LVL189:
+ 2341              	.LBB376:
+ 2342              	.LBI376:
+2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2343              		.loc 2 2804 26 view .LVU664
+ 2344              	.LBB377:
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2345              		.loc 2 2806 3 view .LVU665
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2346              		.loc 2 2806 21 is_stmt 0 view .LVU666
+ 2347 0048 114B     		ldr	r3, .L195
+ 2348 004a D3F89030 		ldr	r3, [r3, #144]
+ 2349              	.LVL190:
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2350              		.loc 2 2806 21 view .LVU667
+ 2351              	.LBE377:
+ 2352              	.LBE376:
+ 2353 004e 13F0006F 		tst	r3, #134217728
+ 2354 0052 07D1     		bne	.L189
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             {
+ 2355              		.loc 1 901 13 is_stmt 1 view .LVU668
+ 2356              	.LBB378:
+ 2357              	.LBI378:
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2358              		.loc 2 3153 26 view .LVU669
+ 2359              	.LBB379:
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2360              		.loc 2 3155 3 view .LVU670
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2361              		.loc 2 3155 11 is_stmt 0 view .LVU671
+ 2362 0054 0E4B     		ldr	r3, .L195
+ 2363 0056 1868     		ldr	r0, [r3]
+ 2364              	.LBE379:
+ARM GAS  /tmp/ccTMI75D.s 			page 158
+
+
+ 2365              	.LBE378:
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             {
+ 2366              		.loc 1 901 16 view .LVU672
+ 2367 0058 10F00070 		ands	r0, r0, #33554432
+ 2368 005c 17D0     		beq	.L186
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             }
+ 2369              		.loc 1 903 15 is_stmt 1 view .LVU673
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             }
+ 2370              		.loc 1 903 33 is_stmt 0 view .LVU674
+ 2371 005e FFF7FEFF 		bl	RCC_PLL_GetFreqDomain_48M
+ 2372              	.LVL191:
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             }
+ 2373              		.loc 1 903 33 view .LVU675
+ 2374 0062 14E0     		b	.L186
+ 2375              	.LVL192:
+ 2376              	.L189:
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             {
+ 2377              		.loc 1 909 13 is_stmt 1 view .LVU676
+ 2378              	.LBB380:
+ 2379              	.LBI380:
+4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2380              		.loc 2 4179 26 view .LVU677
+ 2381              	.LBB381:
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2382              		.loc 2 4181 3 view .LVU678
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2383              		.loc 2 4181 11 is_stmt 0 view .LVU679
+ 2384 0064 0A4B     		ldr	r3, .L195
+ 2385 0066 1868     		ldr	r0, [r3]
+ 2386              	.LBE381:
+ 2387              	.LBE380:
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             {
+ 2388              		.loc 1 909 16 view .LVU680
+ 2389 0068 10F00050 		ands	r0, r0, #536870912
+ 2390 006c 0FD0     		beq	.L186
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             }
+ 2391              		.loc 1 911 15 is_stmt 1 view .LVU681
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             }
+ 2392              		.loc 1 911 33 is_stmt 0 view .LVU682
+ 2393 006e FFF7FEFF 		bl	RCC_PLLSAI_GetFreqDomain_48M
+ 2394              	.LVL193:
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****             }
+ 2395              		.loc 1 911 33 view .LVU683
+ 2396 0072 0CE0     		b	.L186
+ 2397              	.LVL194:
+ 2398              	.L188:
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 2399              		.loc 1 919 7 is_stmt 1 view .LVU684
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 2400              		.loc 1 919 25 is_stmt 0 view .LVU685
+ 2401 0074 FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 2402              	.LVL195:
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     }
+ 2403              		.loc 1 920 7 is_stmt 1 view .LVU686
+ 2404 0078 09E0     		b	.L186
+ 2405              	.LVL196:
+ 2406              	.L192:
+ARM GAS  /tmp/ccTMI75D.s 			page 159
+
+
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 2407              		.loc 1 941 14 view .LVU687
+ 2408              	.LBB382:
+ 2409              	.LBI382:
+4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2410              		.loc 2 4179 26 view .LVU688
+ 2411              	.LBB383:
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2412              		.loc 2 4181 3 view .LVU689
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2413              		.loc 2 4181 11 is_stmt 0 view .LVU690
+ 2414 007a 054B     		ldr	r3, .L195
+ 2415 007c 1868     		ldr	r0, [r3]
+ 2416              	.LBE383:
+ 2417              	.LBE382:
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 2418              		.loc 1 941 17 view .LVU691
+ 2419 007e 10F00050 		ands	r0, r0, #536870912
+ 2420 0082 04D0     		beq	.L186
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 2421              		.loc 1 943 16 is_stmt 1 view .LVU692
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 2422              		.loc 1 943 34 is_stmt 0 view .LVU693
+ 2423 0084 FFF7FEFF 		bl	RCC_PLLSAI_GetFreqDomain_48M
+ 2424              	.LVL197:
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 2425              		.loc 1 943 34 view .LVU694
+ 2426 0088 01E0     		b	.L186
+ 2427              	.LVL198:
+ 2428              	.L191:
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****        break;
+ 2429              		.loc 1 951 8 is_stmt 1 view .LVU695
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****        break;
+ 2430              		.loc 1 951 26 is_stmt 0 view .LVU696
+ 2431 008a FFF7FEFF 		bl	RCC_GetSystemClockFreq
+ 2432              	.LVL199:
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      }
+ 2433              		.loc 1 952 8 is_stmt 1 view .LVU697
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2434              		.loc 1 957 3 view .LVU698
+ 2435              	.L186:
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2436              		.loc 1 958 1 is_stmt 0 view .LVU699
+ 2437 008e 08BD     		pop	{r3, pc}
+ 2438              	.L196:
+ 2439              		.align	2
+ 2440              	.L195:
+ 2441 0090 00380240 		.word	1073887232
+ 2442              		.cfi_endproc
+ 2443              	.LFE303:
+ 2445              		.section	.text.LL_RCC_GetRNGClockFreq,"ax",%progbits
+ 2446              		.align	1
+ 2447              		.global	LL_RCC_GetRNGClockFreq
+ 2448              		.syntax unified
+ 2449              		.thumb
+ 2450              		.thumb_func
+ 2451              		.fpu fpv5-d16
+ARM GAS  /tmp/ccTMI75D.s 			page 160
+
+
+ 2453              	LL_RCC_GetRNGClockFreq:
+ 2454              	.LVL200:
+ 2455              	.LFB304:
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 2456              		.loc 1 968 1 is_stmt 1 view -0
+ 2457              		.cfi_startproc
+ 2458              		@ args = 0, pretend = 0, frame = 0
+ 2459              		@ frame_needed = 0, uses_anonymous_args = 0
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 2460              		.loc 1 968 1 is_stmt 0 view .LVU701
+ 2461 0000 08B5     		push	{r3, lr}
+ 2462              	.LCFI10:
+ 2463              		.cfi_def_cfa_offset 8
+ 2464              		.cfi_offset 3, -8
+ 2465              		.cfi_offset 14, -4
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2466              		.loc 1 969 3 is_stmt 1 view .LVU702
+ 2467              	.LVL201:
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2468              		.loc 1 972 3 view .LVU703
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 2469              		.loc 1 975 3 view .LVU704
+ 2470              	.LBB384:
+ 2471              	.LBI384:
+2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2472              		.loc 2 2818 26 view .LVU705
+ 2473              	.LBB385:
+2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2474              		.loc 2 2820 3 view .LVU706
+2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2475              		.loc 2 2820 21 is_stmt 0 view .LVU707
+ 2476 0002 0B4B     		ldr	r3, .L202
+ 2477 0004 D3F89030 		ldr	r3, [r3, #144]
+ 2478              	.LVL202:
+2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2479              		.loc 2 2820 21 view .LVU708
+ 2480              	.LBE385:
+ 2481              	.LBE384:
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 2482              		.loc 1 975 3 view .LVU709
+ 2483 0008 1842     		tst	r0, r3
+ 2484 000a 08D1     		bne	.L198
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 2485              		.loc 1 978 7 is_stmt 1 view .LVU710
+ 2486              	.LBB386:
+ 2487              	.LBI386:
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2488              		.loc 2 3153 26 view .LVU711
+ 2489              	.LBB387:
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2490              		.loc 2 3155 3 view .LVU712
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2491              		.loc 2 3155 11 is_stmt 0 view .LVU713
+ 2492 000c 084B     		ldr	r3, .L202
+ 2493 000e 1868     		ldr	r0, [r3]
+ 2494              	.LVL203:
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ARM GAS  /tmp/ccTMI75D.s 			page 161
+
+
+ 2495              		.loc 2 3155 11 view .LVU714
+ 2496              	.LBE387:
+ 2497              	.LBE386:
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 2498              		.loc 1 978 10 view .LVU715
+ 2499 0010 10F00070 		ands	r0, r0, #33554432
+ 2500 0014 00D1     		bne	.L201
+ 2501              	.LVL204:
+ 2502              	.L197:
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2503              		.loc 1 994 1 view .LVU716
+ 2504 0016 08BD     		pop	{r3, pc}
+ 2505              	.LVL205:
+ 2506              	.L201:
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 2507              		.loc 1 980 9 is_stmt 1 view .LVU717
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 2508              		.loc 1 980 25 is_stmt 0 view .LVU718
+ 2509 0018 FFF7FEFF 		bl	RCC_PLL_GetFreqDomain_48M
+ 2510              	.LVL206:
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 2511              		.loc 1 980 25 view .LVU719
+ 2512 001c FBE7     		b	.L197
+ 2513              	.LVL207:
+ 2514              	.L198:
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 2515              		.loc 1 986 7 is_stmt 1 view .LVU720
+ 2516              	.LBB388:
+ 2517              	.LBI388:
+4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2518              		.loc 2 4179 26 view .LVU721
+ 2519              	.LBB389:
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2520              		.loc 2 4181 3 view .LVU722
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2521              		.loc 2 4181 11 is_stmt 0 view .LVU723
+ 2522 001e 044B     		ldr	r3, .L202
+ 2523 0020 1868     		ldr	r0, [r3]
+ 2524              	.LVL208:
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2525              		.loc 2 4181 11 view .LVU724
+ 2526              	.LBE389:
+ 2527              	.LBE388:
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 2528              		.loc 1 986 10 view .LVU725
+ 2529 0022 10F00050 		ands	r0, r0, #536870912
+ 2530 0026 F6D0     		beq	.L197
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 2531              		.loc 1 988 9 is_stmt 1 view .LVU726
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 2532              		.loc 1 988 25 is_stmt 0 view .LVU727
+ 2533 0028 FFF7FEFF 		bl	RCC_PLLSAI_GetFreqDomain_48M
+ 2534              	.LVL209:
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2535              		.loc 1 993 3 is_stmt 1 view .LVU728
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2536              		.loc 1 993 10 is_stmt 0 view .LVU729
+ARM GAS  /tmp/ccTMI75D.s 			page 162
+
+
+ 2537 002c F3E7     		b	.L197
+ 2538              	.L203:
+ 2539 002e 00BF     		.align	2
+ 2540              	.L202:
+ 2541 0030 00380240 		.word	1073887232
+ 2542              		.cfi_endproc
+ 2543              	.LFE304:
+ 2545              		.section	.text.LL_RCC_GetUSBClockFreq,"ax",%progbits
+ 2546              		.align	1
+ 2547              		.global	LL_RCC_GetUSBClockFreq
+ 2548              		.syntax unified
+ 2549              		.thumb
+ 2550              		.thumb_func
+ 2551              		.fpu fpv5-d16
+ 2553              	LL_RCC_GetUSBClockFreq:
+ 2554              	.LVL210:
+ 2555              	.LFB306:
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 2556              		.loc 1 1041 1 is_stmt 1 view -0
+ 2557              		.cfi_startproc
+ 2558              		@ args = 0, pretend = 0, frame = 0
+ 2559              		@ frame_needed = 0, uses_anonymous_args = 0
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 2560              		.loc 1 1041 1 is_stmt 0 view .LVU731
+ 2561 0000 08B5     		push	{r3, lr}
+ 2562              	.LCFI11:
+ 2563              		.cfi_def_cfa_offset 8
+ 2564              		.cfi_offset 3, -8
+ 2565              		.cfi_offset 14, -4
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2566              		.loc 1 1042 3 is_stmt 1 view .LVU732
+ 2567              	.LVL211:
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2568              		.loc 1 1045 3 view .LVU733
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 2569              		.loc 1 1048 3 view .LVU734
+ 2570              	.LBB390:
+ 2571              	.LBI390:
+2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2572              		.loc 2 2832 26 view .LVU735
+ 2573              	.LBB391:
+2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2574              		.loc 2 2834 3 view .LVU736
+2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2575              		.loc 2 2834 21 is_stmt 0 view .LVU737
+ 2576 0002 0B4B     		ldr	r3, .L209
+ 2577 0004 D3F89030 		ldr	r3, [r3, #144]
+ 2578              	.LVL212:
+2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2579              		.loc 2 2834 21 view .LVU738
+ 2580              	.LBE391:
+ 2581              	.LBE390:
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 2582              		.loc 1 1048 3 view .LVU739
+ 2583 0008 1842     		tst	r0, r3
+ 2584 000a 08D1     		bne	.L205
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ARM GAS  /tmp/ccTMI75D.s 			page 163
+
+
+ 2585              		.loc 1 1051 7 is_stmt 1 view .LVU740
+ 2586              	.LBB392:
+ 2587              	.LBI392:
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2588              		.loc 2 3153 26 view .LVU741
+ 2589              	.LBB393:
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2590              		.loc 2 3155 3 view .LVU742
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2591              		.loc 2 3155 11 is_stmt 0 view .LVU743
+ 2592 000c 084B     		ldr	r3, .L209
+ 2593 000e 1868     		ldr	r0, [r3]
+ 2594              	.LVL213:
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2595              		.loc 2 3155 11 view .LVU744
+ 2596              	.LBE393:
+ 2597              	.LBE392:
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 2598              		.loc 1 1051 10 view .LVU745
+ 2599 0010 10F00070 		ands	r0, r0, #33554432
+ 2600 0014 00D1     		bne	.L208
+ 2601              	.LVL214:
+ 2602              	.L204:
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2603              		.loc 1 1067 1 view .LVU746
+ 2604 0016 08BD     		pop	{r3, pc}
+ 2605              	.LVL215:
+ 2606              	.L208:
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 2607              		.loc 1 1053 9 is_stmt 1 view .LVU747
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 2608              		.loc 1 1053 25 is_stmt 0 view .LVU748
+ 2609 0018 FFF7FEFF 		bl	RCC_PLL_GetFreqDomain_48M
+ 2610              	.LVL216:
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 2611              		.loc 1 1053 25 view .LVU749
+ 2612 001c FBE7     		b	.L204
+ 2613              	.LVL217:
+ 2614              	.L205:
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 2615              		.loc 1 1059 7 is_stmt 1 view .LVU750
+ 2616              	.LBB394:
+ 2617              	.LBI394:
+4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2618              		.loc 2 4179 26 view .LVU751
+ 2619              	.LBB395:
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2620              		.loc 2 4181 3 view .LVU752
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2621              		.loc 2 4181 11 is_stmt 0 view .LVU753
+ 2622 001e 044B     		ldr	r3, .L209
+ 2623 0020 1868     		ldr	r0, [r3]
+ 2624              	.LVL218:
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2625              		.loc 2 4181 11 view .LVU754
+ 2626              	.LBE395:
+ 2627              	.LBE394:
+ARM GAS  /tmp/ccTMI75D.s 			page 164
+
+
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 2628              		.loc 1 1059 10 view .LVU755
+ 2629 0022 10F00050 		ands	r0, r0, #536870912
+ 2630 0026 F6D0     		beq	.L204
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 2631              		.loc 1 1061 9 is_stmt 1 view .LVU756
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       }
+ 2632              		.loc 1 1061 25 is_stmt 0 view .LVU757
+ 2633 0028 FFF7FEFF 		bl	RCC_PLLSAI_GetFreqDomain_48M
+ 2634              	.LVL219:
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2635              		.loc 1 1066 3 is_stmt 1 view .LVU758
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2636              		.loc 1 1066 10 is_stmt 0 view .LVU759
+ 2637 002c F3E7     		b	.L204
+ 2638              	.L210:
+ 2639 002e 00BF     		.align	2
+ 2640              	.L209:
+ 2641 0030 00380240 		.word	1073887232
+ 2642              		.cfi_endproc
+ 2643              	.LFE306:
+ 2645              		.section	.text.RCC_PLLSAI_GetFreqDomain_LTDC,"ax",%progbits
+ 2646              		.align	1
+ 2647              		.global	RCC_PLLSAI_GetFreqDomain_LTDC
+ 2648              		.syntax unified
+ 2649              		.thumb
+ 2650              		.thumb_func
+ 2651              		.fpu fpv5-d16
+ 2653              	RCC_PLLSAI_GetFreqDomain_LTDC:
+ 2654              	.LFB319:
+1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(LTDC)
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return PLLSAI clock frequency used for LTDC domain
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval PLLSAI clock frequency (in Hz)
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 2655              		.loc 1 1450 1 is_stmt 1 view -0
+ 2656              		.cfi_startproc
+ 2657              		@ args = 0, pretend = 0, frame = 0
+ 2658              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2659              		@ link register save eliminated.
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t pllinputfreq = 0U, pllsource = 0U;
+ 2660              		.loc 1 1451 3 view .LVU761
+ 2661              	.LVL220:
+1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      LTDC Domain clock  = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
+1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   pllsource = LL_RCC_PLL_GetMainSource();
+ 2662              		.loc 1 1456 3 view .LVU762
+ 2663              	.LBB396:
+ 2664              	.LBI396:
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2665              		.loc 2 3461 26 view .LVU763
+ 2666              	.LBB397:
+ARM GAS  /tmp/ccTMI75D.s 			page 165
+
+
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2667              		.loc 2 3463 3 view .LVU764
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2668              		.loc 2 3463 21 is_stmt 0 view .LVU765
+ 2669 0000 114B     		ldr	r3, .L214
+ 2670 0002 5B68     		ldr	r3, [r3, #4]
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2671              		.loc 2 3463 10 view .LVU766
+ 2672 0004 03F48003 		and	r3, r3, #4194304
+ 2673              	.LVL221:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2674              		.loc 2 3463 10 view .LVU767
+ 2675              	.LBE397:
+ 2676              	.LBE396:
+1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (pllsource)
+ 2677              		.loc 1 1458 3 is_stmt 1 view .LVU768
+ 2678 0008 DBB9     		cbnz	r3, .L213
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+ 2679              		.loc 1 1461 20 is_stmt 0 view .LVU769
+ 2680 000a 1048     		ldr	r0, .L214+4
+ 2681              	.L212:
+ 2682              	.LVL222:
+1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSE_VALUE;
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ 2683              		.loc 1 1472 3 is_stmt 1 view .LVU770
+ 2684              	.LBB398:
+ 2685              	.LBI398:
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2686              		.loc 2 3601 26 view .LVU771
+ 2687              	.LBB399:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2688              		.loc 2 3603 3 view .LVU772
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2689              		.loc 2 3603 21 is_stmt 0 view .LVU773
+ 2690 000c 0E4A     		ldr	r2, .L214
+ 2691 000e 5368     		ldr	r3, [r2, #4]
+ 2692              	.LVL223:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2693              		.loc 2 3603 10 view .LVU774
+ 2694 0010 03F03F03 		and	r3, r3, #63
+ 2695              	.LBE399:
+ 2696              	.LBE398:
+ 2697              		.loc 1 1472 10 view .LVU775
+ 2698 0014 B0FBF3F0 		udiv	r0, r0, r3
+ 2699              	.LVL224:
+ARM GAS  /tmp/ccTMI75D.s 			page 166
+
+
+ 2700              	.LBB400:
+ 2701              	.LBI400:
+4515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2702              		.loc 2 4515 26 is_stmt 1 view .LVU776
+ 2703              	.LBB401:
+4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2704              		.loc 2 4517 3 view .LVU777
+4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2705              		.loc 2 4517 21 is_stmt 0 view .LVU778
+ 2706 0018 D2F88830 		ldr	r3, [r2, #136]
+4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2707              		.loc 2 4517 10 view .LVU779
+ 2708 001c C3F38813 		ubfx	r3, r3, #6, #9
+ 2709              	.LBE401:
+ 2710              	.LBE400:
+ 2711              		.loc 1 1472 10 view .LVU780
+ 2712 0020 03FB00F0 		mul	r0, r3, r0
+ 2713              	.LBB402:
+ 2714              	.LBI402:
+4557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2715              		.loc 2 4557 26 is_stmt 1 view .LVU781
+ 2716              	.LBB403:
+4559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2717              		.loc 2 4559 3 view .LVU782
+4559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2718              		.loc 2 4559 21 is_stmt 0 view .LVU783
+ 2719 0024 D2F88830 		ldr	r3, [r2, #136]
+ 2720              	.LBE403:
+ 2721              	.LBE402:
+ 2722              		.loc 1 1472 10 view .LVU784
+ 2723 0028 C3F30273 		ubfx	r3, r3, #28, #3
+ 2724              	.LBB404:
+ 2725              	.LBI404:
+4619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
+4622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get SAIPLL division factor for PLLSAIDIVR
+4624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used for LTDC domain clock
+4625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1  PLLSAIDIVR      LL_RCC_PLLSAI_GetDIVR
+4626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+4628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+4629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+4630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+4631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
+ 2726              		.loc 2 4632 26 is_stmt 1 view .LVU785
+ 2727              	.LBB405:
+4633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR));
+ 2728              		.loc 2 4634 3 view .LVU786
+ 2729              		.loc 2 4634 21 is_stmt 0 view .LVU787
+ 2730 002c D2F88C20 		ldr	r2, [r2, #140]
+ 2731              	.LBE405:
+ 2732              	.LBE404:
+ 2733              		.loc 1 1472 10 view .LVU788
+ARM GAS  /tmp/ccTMI75D.s 			page 167
+
+
+ 2734 0030 C2F30142 		ubfx	r2, r2, #16, #2
+ 2735 0034 0649     		ldr	r1, .L214+8
+ 2736 0036 8A5C     		ldrb	r2, [r1, r2]	@ zero_extendqisi2
+ 2737 0038 02FB03F3 		mul	r3, r2, r3
+1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                         LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_G
+1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2738              		.loc 1 1474 1 view .LVU789
+ 2739 003c B0FBF3F0 		udiv	r0, r0, r3
+ 2740 0040 7047     		bx	lr
+ 2741              	.LVL225:
+ 2742              	.L213:
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 2743              		.loc 1 1465 20 view .LVU790
+ 2744 0042 0448     		ldr	r0, .L214+12
+ 2745 0044 E2E7     		b	.L212
+ 2746              	.L215:
+ 2747 0046 00BF     		.align	2
+ 2748              	.L214:
+ 2749 0048 00380240 		.word	1073887232
+ 2750 004c 0024F400 		.word	16000000
+ 2751 0050 00000000 		.word	.LANCHOR0
+ 2752 0054 40787D01 		.word	25000000
+ 2753              		.cfi_endproc
+ 2754              	.LFE319:
+ 2756              		.section	.text.LL_RCC_GetLTDCClockFreq,"ax",%progbits
+ 2757              		.align	1
+ 2758              		.global	LL_RCC_GetLTDCClockFreq
+ 2759              		.syntax unified
+ 2760              		.thumb
+ 2761              		.thumb_func
+ 2762              		.fpu fpv5-d16
+ 2764              	LL_RCC_GetLTDCClockFreq:
+ 2765              	.LVL226:
+ 2766              	.LFB309:
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 2767              		.loc 1 1175 1 is_stmt 1 view -0
+ 2768              		.cfi_startproc
+ 2769              		@ args = 0, pretend = 0, frame = 0
+ 2770              		@ frame_needed = 0, uses_anonymous_args = 0
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 2771              		.loc 1 1175 1 is_stmt 0 view .LVU792
+ 2772 0000 08B5     		push	{r3, lr}
+ 2773              	.LCFI12:
+ 2774              		.cfi_def_cfa_offset 8
+ 2775              		.cfi_offset 3, -8
+ 2776              		.cfi_offset 14, -4
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2777              		.loc 1 1176 3 is_stmt 1 view .LVU793
+ 2778              	.LVL227:
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2779              		.loc 1 1179 3 view .LVU794
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 2780              		.loc 1 1181 3 view .LVU795
+ 2781              	.LBB406:
+ 2782              	.LBI406:
+4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2783              		.loc 2 4179 26 view .LVU796
+ARM GAS  /tmp/ccTMI75D.s 			page 168
+
+
+ 2784              	.LBB407:
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2785              		.loc 2 4181 3 view .LVU797
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2786              		.loc 2 4181 11 is_stmt 0 view .LVU798
+ 2787 0002 044B     		ldr	r3, .L220
+ 2788 0004 1868     		ldr	r0, [r3]
+ 2789              	.LVL228:
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2790              		.loc 2 4181 11 view .LVU799
+ 2791              	.LBE407:
+ 2792              	.LBE406:
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 2793              		.loc 1 1181 6 view .LVU800
+ 2794 0006 10F00050 		ands	r0, r0, #536870912
+ 2795 000a 00D1     		bne	.L219
+ 2796              	.LVL229:
+ 2797              	.L216:
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* LTDC */
+ 2798              		.loc 1 1187 1 view .LVU801
+ 2799 000c 08BD     		pop	{r3, pc}
+ 2800              	.LVL230:
+ 2801              	.L219:
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 2802              		.loc 1 1183 6 is_stmt 1 view .LVU802
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 2803              		.loc 1 1183 23 is_stmt 0 view .LVU803
+ 2804 000e FFF7FEFF 		bl	RCC_PLLSAI_GetFreqDomain_LTDC
+ 2805              	.LVL231:
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2806              		.loc 1 1186 3 is_stmt 1 view .LVU804
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2807              		.loc 1 1186 10 is_stmt 0 view .LVU805
+ 2808 0012 FBE7     		b	.L216
+ 2809              	.L221:
+ 2810              		.align	2
+ 2811              	.L220:
+ 2812 0014 00380240 		.word	1073887232
+ 2813              		.cfi_endproc
+ 2814              	.LFE309:
+ 2816              		.section	.text.RCC_PLLI2S_GetFreqDomain_SAI,"ax",%progbits
+ 2817              		.align	1
+ 2818              		.global	RCC_PLLI2S_GetFreqDomain_SAI
+ 2819              		.syntax unified
+ 2820              		.thumb
+ 2821              		.thumb_func
+ 2822              		.fpu fpv5-d16
+ 2824              	RCC_PLLI2S_GetFreqDomain_SAI:
+ 2825              	.LFB320:
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* LTDC */
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return PLLI2S clock frequency used for SAI1 and SAI2 domains
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval PLLI2S clock frequency (in Hz)
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ARM GAS  /tmp/ccTMI75D.s 			page 169
+
+
+ 2826              		.loc 1 1482 1 is_stmt 1 view -0
+ 2827              		.cfi_startproc
+ 2828              		@ args = 0, pretend = 0, frame = 0
+ 2829              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2830              		@ link register save eliminated.
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t pllinputfreq = 0U, pllsource = 0U;
+ 2831              		.loc 1 1483 3 view .LVU807
+ 2832              	.LVL232:
+1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      SAI1 and SAI2 domains clock  = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
+1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   pllsource = LL_RCC_PLL_GetMainSource();
+ 2833              		.loc 1 1488 3 view .LVU808
+ 2834              	.LBB408:
+ 2835              	.LBI408:
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2836              		.loc 2 3461 26 view .LVU809
+ 2837              	.LBB409:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2838              		.loc 2 3463 3 view .LVU810
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2839              		.loc 2 3463 21 is_stmt 0 view .LVU811
+ 2840 0000 104B     		ldr	r3, .L225
+ 2841 0002 5B68     		ldr	r3, [r3, #4]
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2842              		.loc 2 3463 10 view .LVU812
+ 2843 0004 03F48003 		and	r3, r3, #4194304
+ 2844              	.LVL233:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2845              		.loc 2 3463 10 view .LVU813
+ 2846              	.LBE409:
+ 2847              	.LBE408:
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (pllsource)
+ 2848              		.loc 1 1490 3 is_stmt 1 view .LVU814
+ 2849 0008 CBB9     		cbnz	r3, .L224
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLI2S clock source */
+1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+ 2850              		.loc 1 1493 20 is_stmt 0 view .LVU815
+ 2851 000a 0F48     		ldr	r0, .L225+4
+ 2852              	.L223:
+ 2853              	.LVL234:
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLI2S clock source */
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSE_VALUE;
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ 2854              		.loc 1 1504 3 is_stmt 1 view .LVU816
+ 2855              	.LBB410:
+ARM GAS  /tmp/ccTMI75D.s 			page 170
+
+
+ 2856              	.LBI410:
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2857              		.loc 2 3601 26 view .LVU817
+ 2858              	.LBB411:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2859              		.loc 2 3603 3 view .LVU818
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2860              		.loc 2 3603 21 is_stmt 0 view .LVU819
+ 2861 000c 0D4A     		ldr	r2, .L225
+ 2862 000e 5368     		ldr	r3, [r2, #4]
+ 2863              	.LVL235:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2864              		.loc 2 3603 10 view .LVU820
+ 2865 0010 03F03F03 		and	r3, r3, #63
+ 2866              	.LBE411:
+ 2867              	.LBE410:
+ 2868              		.loc 1 1504 10 view .LVU821
+ 2869 0014 B0FBF3F0 		udiv	r0, r0, r3
+ 2870              	.LVL236:
+ 2871              	.LBB412:
+ 2872              	.LBI412:
+4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2873              		.loc 2 4040 26 is_stmt 1 view .LVU822
+ 2874              	.LBB413:
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2875              		.loc 2 4042 3 view .LVU823
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2876              		.loc 2 4042 21 is_stmt 0 view .LVU824
+ 2877 0018 D2F88430 		ldr	r3, [r2, #132]
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2878              		.loc 2 4042 10 view .LVU825
+ 2879 001c C3F38813 		ubfx	r3, r3, #6, #9
+ 2880              	.LBE413:
+ 2881              	.LBE412:
+ 2882              		.loc 1 1504 10 view .LVU826
+ 2883 0020 03FB00F0 		mul	r0, r3, r0
+ 2884              	.LBB414:
+ 2885              	.LBI414:
+4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2886              		.loc 2 4064 26 is_stmt 1 view .LVU827
+ 2887              	.LBB415:
+4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2888              		.loc 2 4066 3 view .LVU828
+4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2889              		.loc 2 4066 21 is_stmt 0 view .LVU829
+ 2890 0024 D2F88430 		ldr	r3, [r2, #132]
+ 2891              	.LBE415:
+ 2892              	.LBE414:
+ 2893              		.loc 1 1504 10 view .LVU830
+ 2894 0028 C3F30363 		ubfx	r3, r3, #24, #4
+ 2895              	.LBB416:
+ 2896              	.LBI416:
+4141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2897              		.loc 2 4141 26 is_stmt 1 view .LVU831
+ 2898              	.LBB417:
+4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2899              		.loc 2 4143 3 view .LVU832
+ARM GAS  /tmp/ccTMI75D.s 			page 171
+
+
+4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2900              		.loc 2 4143 21 is_stmt 0 view .LVU833
+ 2901 002c D2F88C20 		ldr	r2, [r2, #140]
+4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2902              		.loc 2 4143 10 view .LVU834
+ 2903 0030 02F01F02 		and	r2, r2, #31
+ 2904              	.LBE417:
+ 2905              	.LBE416:
+ 2906              		.loc 1 1504 10 view .LVU835
+ 2907 0034 02FB0333 		mla	r3, r2, r3, r3
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                         LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_G
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 2908              		.loc 1 1506 1 view .LVU836
+ 2909 0038 B0FBF3F0 		udiv	r0, r0, r3
+ 2910 003c 7047     		bx	lr
+ 2911              	.LVL237:
+ 2912              	.L224:
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 2913              		.loc 1 1497 20 view .LVU837
+ 2914 003e 0348     		ldr	r0, .L225+8
+ 2915 0040 E4E7     		b	.L223
+ 2916              	.L226:
+ 2917 0042 00BF     		.align	2
+ 2918              	.L225:
+ 2919 0044 00380240 		.word	1073887232
+ 2920 0048 0024F400 		.word	16000000
+ 2921 004c 40787D01 		.word	25000000
+ 2922              		.cfi_endproc
+ 2923              	.LFE320:
+ 2925              		.section	.text.LL_RCC_GetSAIClockFreq,"ax",%progbits
+ 2926              		.align	1
+ 2927              		.global	LL_RCC_GetSAIClockFreq
+ 2928              		.syntax unified
+ 2929              		.thumb
+ 2930              		.thumb_func
+ 2931              		.fpu fpv5-d16
+ 2933              	LL_RCC_GetSAIClockFreq:
+ 2934              	.LVL238:
+ 2935              	.LFB302:
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 2936              		.loc 1 766 1 is_stmt 1 view -0
+ 2937              		.cfi_startproc
+ 2938              		@ args = 0, pretend = 0, frame = 0
+ 2939              		@ frame_needed = 0, uses_anonymous_args = 0
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 2940              		.loc 1 766 1 is_stmt 0 view .LVU839
+ 2941 0000 08B5     		push	{r3, lr}
+ 2942              	.LCFI13:
+ 2943              		.cfi_def_cfa_offset 8
+ 2944              		.cfi_offset 3, -8
+ 2945              		.cfi_offset 14, -4
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2946              		.loc 1 767 3 is_stmt 1 view .LVU840
+ 2947              	.LVL239:
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2948              		.loc 1 770 3 view .LVU841
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ARM GAS  /tmp/ccTMI75D.s 			page 172
+
+
+ 2949              		.loc 1 772 3 view .LVU842
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 2950              		.loc 1 772 6 is_stmt 0 view .LVU843
+ 2951 0002 B0F5401F 		cmp	r0, #3145728
+ 2952 0006 04D0     		beq	.L248
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 2953              		.loc 1 822 5 is_stmt 1 view .LVU844
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 2954              		.loc 1 822 8 is_stmt 0 view .LVU845
+ 2955 0008 B0F5400F 		cmp	r0, #12582912
+ 2956 000c 3BD0     		beq	.L249
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2957              		.loc 1 767 12 view .LVU846
+ 2958 000e 0020     		movs	r0, #0
+ 2959              	.LVL240:
+ 2960              	.L227:
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 2961              		.loc 1 873 1 view .LVU847
+ 2962 0010 08BD     		pop	{r3, pc}
+ 2963              	.LVL241:
+ 2964              	.L248:
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 2965              		.loc 1 775 5 is_stmt 1 view .LVU848
+ 2966              	.LBB418:
+ 2967              	.LBI418:
+2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2968              		.loc 2 2770 26 view .LVU849
+ 2969              	.LBB419:
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2970              		.loc 2 2772 3 view .LVU850
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2971              		.loc 2 2772 21 is_stmt 0 view .LVU851
+ 2972 0012 3D4B     		ldr	r3, .L254
+ 2973 0014 D3F88C30 		ldr	r3, [r3, #140]
+ 2974 0018 0340     		ands	r3, r3, r0
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2975              		.loc 2 2772 10 view .LVU852
+ 2976 001a 40EA1340 		orr	r0, r0, r3, lsr #16
+ 2977              	.LVL242:
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2978              		.loc 2 2772 10 view .LVU853
+ 2979              	.LBE419:
+ 2980              	.LBE418:
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 2981              		.loc 1 775 5 view .LVU854
+ 2982 001e 3B4B     		ldr	r3, .L254+4
+ 2983 0020 9842     		cmp	r0, r3
+ 2984 0022 6AD0     		beq	.L240
+ 2985 0024 0FD8     		bhi	.L230
+ 2986 0026 B0F5401F 		cmp	r0, #3145728
+ 2987 002a 1DD0     		beq	.L231
+ 2988 002c 103B     		subs	r3, r3, #16
+ 2989 002e 9842     		cmp	r0, r3
+ 2990 0030 07D1     		bne	.L250
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 2991              		.loc 1 785 9 is_stmt 1 view .LVU855
+ 2992              	.LBB420:
+ARM GAS  /tmp/ccTMI75D.s 			page 173
+
+
+ 2993              	.LBI420:
+3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 2994              		.loc 2 3711 26 view .LVU856
+ 2995              	.LBB421:
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2996              		.loc 2 3713 3 view .LVU857
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 2997              		.loc 2 3713 11 is_stmt 0 view .LVU858
+ 2998 0032 354B     		ldr	r3, .L254
+ 2999 0034 1868     		ldr	r0, [r3]
+ 3000              	.LBE421:
+ 3001              	.LBE420:
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 3002              		.loc 1 785 12 view .LVU859
+ 3003 0036 10F00060 		ands	r0, r0, #134217728
+ 3004 003a E9D0     		beq	.L227
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3005              		.loc 1 787 11 is_stmt 1 view .LVU860
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3006              		.loc 1 787 27 is_stmt 0 view .LVU861
+ 3007 003c FFF7FEFF 		bl	RCC_PLLI2S_GetFreqDomain_SAI
+ 3008              	.LVL243:
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3009              		.loc 1 787 27 view .LVU862
+ 3010 0040 E6E7     		b	.L227
+ 3011              	.LVL244:
+ 3012              	.L250:
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 3013              		.loc 1 775 5 view .LVU863
+ 3014 0042 0020     		movs	r0, #0
+ 3015 0044 E4E7     		b	.L227
+ 3016              	.L230:
+ 3017 0046 B0F1301F 		cmp	r0, #3145776
+ 3018 004a 0BD1     		bne	.L251
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 3019              		.loc 1 793 9 is_stmt 1 view .LVU864
+ 3020              	.LBB422:
+ 3021              	.LBI422:
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3022              		.loc 2 3461 26 view .LVU865
+ 3023              	.LBB423:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3024              		.loc 2 3463 3 view .LVU866
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3025              		.loc 2 3463 21 is_stmt 0 view .LVU867
+ 3026 004c 2E4B     		ldr	r3, .L254
+ 3027 004e 5B68     		ldr	r3, [r3, #4]
+ 3028              	.LBE423:
+ 3029              	.LBE422:
+ 3030 0050 13F4800F 		tst	r3, #4194304
+ 3031 0054 10D0     		beq	.L234
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 3032              		.loc 1 796 14 is_stmt 1 view .LVU868
+ 3033              	.LBB424:
+ 3034              	.LBI424:
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3035              		.loc 2 1992 26 view .LVU869
+ARM GAS  /tmp/ccTMI75D.s 			page 174
+
+
+ 3036              	.LBB425:
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3037              		.loc 2 1994 3 view .LVU870
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3038              		.loc 2 1994 11 is_stmt 0 view .LVU871
+ 3039 0056 2C4B     		ldr	r3, .L254
+ 3040 0058 1868     		ldr	r0, [r3]
+ 3041              	.LBE425:
+ 3042              	.LBE424:
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 3043              		.loc 1 796 17 view .LVU872
+ 3044 005a 10F40030 		ands	r0, r0, #131072
+ 3045 005e D7D0     		beq	.L227
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 3046              		.loc 1 798 30 view .LVU873
+ 3047 0060 2B48     		ldr	r0, .L254+8
+ 3048 0062 D5E7     		b	.L227
+ 3049              	.L251:
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 3050              		.loc 1 775 5 view .LVU874
+ 3051 0064 0020     		movs	r0, #0
+ 3052 0066 D3E7     		b	.L227
+ 3053              	.L231:
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 3054              		.loc 1 778 9 is_stmt 1 view .LVU875
+ 3055              	.LBB426:
+ 3056              	.LBI426:
+4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3057              		.loc 2 4179 26 view .LVU876
+ 3058              	.LBB427:
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3059              		.loc 2 4181 3 view .LVU877
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3060              		.loc 2 4181 11 is_stmt 0 view .LVU878
+ 3061 0068 274B     		ldr	r3, .L254
+ 3062 006a 1868     		ldr	r0, [r3]
+ 3063              	.LBE427:
+ 3064              	.LBE426:
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 3065              		.loc 1 778 12 view .LVU879
+ 3066 006c 10F00050 		ands	r0, r0, #536870912
+ 3067 0070 CED0     		beq	.L227
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3068              		.loc 1 780 11 is_stmt 1 view .LVU880
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3069              		.loc 1 780 27 is_stmt 0 view .LVU881
+ 3070 0072 FFF7FEFF 		bl	RCC_PLLSAI_GetFreqDomain_SAI
+ 3071              	.LVL245:
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3072              		.loc 1 780 27 view .LVU882
+ 3073 0076 CBE7     		b	.L227
+ 3074              	.LVL246:
+ 3075              	.L234:
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 3076              		.loc 1 804 14 is_stmt 1 view .LVU883
+ 3077              	.LBB428:
+ 3078              	.LBI428:
+ARM GAS  /tmp/ccTMI75D.s 			page 175
+
+
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3079              		.loc 2 2030 26 view .LVU884
+ 3080              	.LBB429:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3081              		.loc 2 2032 3 view .LVU885
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3082              		.loc 2 2032 11 is_stmt 0 view .LVU886
+ 3083 0078 234B     		ldr	r3, .L254
+ 3084 007a 1868     		ldr	r0, [r3]
+ 3085              	.LBE429:
+ 3086              	.LBE428:
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 3087              		.loc 1 804 17 view .LVU887
+ 3088 007c 10F00200 		ands	r0, r0, #2
+ 3089 0080 C6D0     		beq	.L227
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 3090              		.loc 1 806 30 view .LVU888
+ 3091 0082 2448     		ldr	r0, .L254+12
+ 3092 0084 C4E7     		b	.L227
+ 3093              	.LVL247:
+ 3094              	.L249:
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 3095              		.loc 1 825 7 is_stmt 1 view .LVU889
+ 3096              	.LBB430:
+ 3097              	.LBI430:
+2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3098              		.loc 2 2770 26 view .LVU890
+ 3099              	.LBB431:
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3100              		.loc 2 2772 3 view .LVU891
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3101              		.loc 2 2772 21 is_stmt 0 view .LVU892
+ 3102 0086 204B     		ldr	r3, .L254
+ 3103 0088 D3F88C30 		ldr	r3, [r3, #140]
+ 3104 008c 0340     		ands	r3, r3, r0
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3105              		.loc 2 2772 10 view .LVU893
+ 3106 008e 40EA1340 		orr	r0, r0, r3, lsr #16
+ 3107              	.LVL248:
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3108              		.loc 2 2772 10 view .LVU894
+ 3109              	.LBE431:
+ 3110              	.LBE430:
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 3111              		.loc 1 825 7 view .LVU895
+ 3112 0092 214B     		ldr	r3, .L254+16
+ 3113 0094 9842     		cmp	r0, r3
+ 3114 0096 33D0     		beq	.L244
+ 3115 0098 0FD8     		bhi	.L235
+ 3116 009a B0F5400F 		cmp	r0, #12582912
+ 3117 009e 1DD0     		beq	.L236
+ 3118 00a0 403B     		subs	r3, r3, #64
+ 3119 00a2 9842     		cmp	r0, r3
+ 3120 00a4 07D1     		bne	.L252
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 3121              		.loc 1 835 9 is_stmt 1 view .LVU896
+ 3122              	.LBB432:
+ARM GAS  /tmp/ccTMI75D.s 			page 176
+
+
+ 3123              	.LBI432:
+3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3124              		.loc 2 3711 26 view .LVU897
+ 3125              	.LBB433:
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3126              		.loc 2 3713 3 view .LVU898
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3127              		.loc 2 3713 11 is_stmt 0 view .LVU899
+ 3128 00a6 184B     		ldr	r3, .L254
+ 3129 00a8 1868     		ldr	r0, [r3]
+ 3130              	.LBE433:
+ 3131              	.LBE432:
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 3132              		.loc 1 835 12 view .LVU900
+ 3133 00aa 10F00060 		ands	r0, r0, #134217728
+ 3134 00ae AFD0     		beq	.L227
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3135              		.loc 1 837 11 is_stmt 1 view .LVU901
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3136              		.loc 1 837 27 is_stmt 0 view .LVU902
+ 3137 00b0 FFF7FEFF 		bl	RCC_PLLI2S_GetFreqDomain_SAI
+ 3138              	.LVL249:
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3139              		.loc 1 837 27 view .LVU903
+ 3140 00b4 ACE7     		b	.L227
+ 3141              	.LVL250:
+ 3142              	.L252:
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 3143              		.loc 1 825 7 view .LVU904
+ 3144 00b6 0020     		movs	r0, #0
+ 3145 00b8 AAE7     		b	.L227
+ 3146              	.L235:
+ 3147 00ba B0F1C01F 		cmp	r0, #12583104
+ 3148 00be 0BD1     		bne	.L253
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 3149              		.loc 1 843 9 is_stmt 1 view .LVU905
+ 3150              	.LBB434:
+ 3151              	.LBI434:
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3152              		.loc 2 3461 26 view .LVU906
+ 3153              	.LBB435:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3154              		.loc 2 3463 3 view .LVU907
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3155              		.loc 2 3463 21 is_stmt 0 view .LVU908
+ 3156 00c0 114B     		ldr	r3, .L254
+ 3157 00c2 5B68     		ldr	r3, [r3, #4]
+ 3158              	.LBE435:
+ 3159              	.LBE434:
+ 3160 00c4 13F4800F 		tst	r3, #4194304
+ 3161 00c8 10D0     		beq	.L239
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 3162              		.loc 1 846 14 is_stmt 1 view .LVU909
+ 3163              	.LBB436:
+ 3164              	.LBI436:
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3165              		.loc 2 1992 26 view .LVU910
+ARM GAS  /tmp/ccTMI75D.s 			page 177
+
+
+ 3166              	.LBB437:
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3167              		.loc 2 1994 3 view .LVU911
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3168              		.loc 2 1994 11 is_stmt 0 view .LVU912
+ 3169 00ca 0F4B     		ldr	r3, .L254
+ 3170 00cc 1868     		ldr	r0, [r3]
+ 3171              	.LBE437:
+ 3172              	.LBE436:
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 3173              		.loc 1 846 17 view .LVU913
+ 3174 00ce 10F40030 		ands	r0, r0, #131072
+ 3175 00d2 9DD0     		beq	.L227
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 3176              		.loc 1 848 30 view .LVU914
+ 3177 00d4 0E48     		ldr	r0, .L254+8
+ 3178 00d6 9BE7     		b	.L227
+ 3179              	.L253:
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       {
+ 3180              		.loc 1 825 7 view .LVU915
+ 3181 00d8 0020     		movs	r0, #0
+ 3182 00da 99E7     		b	.L227
+ 3183              	.L236:
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 3184              		.loc 1 828 9 is_stmt 1 view .LVU916
+ 3185              	.LBB438:
+ 3186              	.LBI438:
+4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3187              		.loc 2 4179 26 view .LVU917
+ 3188              	.LBB439:
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3189              		.loc 2 4181 3 view .LVU918
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3190              		.loc 2 4181 11 is_stmt 0 view .LVU919
+ 3191 00dc 0A4B     		ldr	r3, .L254
+ 3192 00de 1868     		ldr	r0, [r3]
+ 3193              	.LBE439:
+ 3194              	.LBE438:
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 3195              		.loc 1 828 12 view .LVU920
+ 3196 00e0 10F00050 		ands	r0, r0, #536870912
+ 3197 00e4 94D0     		beq	.L227
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3198              		.loc 1 830 11 is_stmt 1 view .LVU921
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3199              		.loc 1 830 27 is_stmt 0 view .LVU922
+ 3200 00e6 FFF7FEFF 		bl	RCC_PLLSAI_GetFreqDomain_SAI
+ 3201              	.LVL251:
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3202              		.loc 1 830 27 view .LVU923
+ 3203 00ea 91E7     		b	.L227
+ 3204              	.LVL252:
+ 3205              	.L239:
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 3206              		.loc 1 854 14 is_stmt 1 view .LVU924
+ 3207              	.LBB440:
+ 3208              	.LBI440:
+ARM GAS  /tmp/ccTMI75D.s 			page 178
+
+
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3209              		.loc 2 2030 26 view .LVU925
+ 3210              	.LBB441:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3211              		.loc 2 2032 3 view .LVU926
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3212              		.loc 2 2032 11 is_stmt 0 view .LVU927
+ 3213 00ec 064B     		ldr	r3, .L254
+ 3214 00ee 1868     		ldr	r0, [r3]
+ 3215              	.LBE441:
+ 3216              	.LBE440:
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              {
+ 3217              		.loc 1 854 17 view .LVU928
+ 3218 00f0 10F00200 		ands	r0, r0, #2
+ 3219 00f4 8CD0     		beq	.L227
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****              }
+ 3220              		.loc 1 856 30 view .LVU929
+ 3221 00f6 0748     		ldr	r0, .L254+12
+ 3222              	.LVL253:
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 3223              		.loc 1 872 3 is_stmt 1 view .LVU930
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 3224              		.loc 1 872 10 is_stmt 0 view .LVU931
+ 3225 00f8 8AE7     		b	.L227
+ 3226              	.LVL254:
+ 3227              	.L240:
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 3228              		.loc 1 813 23 view .LVU932
+ 3229 00fa 4BF68030 		movw	r0, #48000
+ 3230 00fe 87E7     		b	.L227
+ 3231              	.L244:
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****           break;
+ 3232              		.loc 1 863 25 view .LVU933
+ 3233 0100 4BF68030 		movw	r0, #48000
+ 3234 0104 84E7     		b	.L227
+ 3235              	.L255:
+ 3236 0106 00BF     		.align	2
+ 3237              	.L254:
+ 3238 0108 00380240 		.word	1073887232
+ 3239 010c 20003000 		.word	3145760
+ 3240 0110 40787D01 		.word	25000000
+ 3241 0114 0024F400 		.word	16000000
+ 3242 0118 8000C000 		.word	12583040
+ 3243              		.cfi_endproc
+ 3244              	.LFE302:
+ 3246              		.section	.text.LL_RCC_GetDFSDMAudioClockFreq,"ax",%progbits
+ 3247              		.align	1
+ 3248              		.global	LL_RCC_GetDFSDMAudioClockFreq
+ 3249              		.syntax unified
+ 3250              		.thumb
+ 3251              		.thumb_func
+ 3252              		.fpu fpv5-d16
+ 3254              	LL_RCC_GetDFSDMAudioClockFreq:
+ 3255              	.LVL255:
+ 3256              	.LFB308:
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 3257              		.loc 1 1107 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccTMI75D.s 			page 179
+
+
+ 3258              		.cfi_startproc
+ 3259              		@ args = 0, pretend = 0, frame = 0
+ 3260              		@ frame_needed = 0, uses_anonymous_args = 0
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 3261              		.loc 1 1107 1 is_stmt 0 view .LVU935
+ 3262 0000 08B5     		push	{r3, lr}
+ 3263              	.LCFI14:
+ 3264              		.cfi_def_cfa_offset 8
+ 3265              		.cfi_offset 3, -8
+ 3266              		.cfi_offset 14, -4
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 3267              		.loc 1 1108 3 is_stmt 1 view .LVU936
+ 3268              	.LVL256:
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 3269              		.loc 1 1111 3 view .LVU937
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 3270              		.loc 1 1114 3 view .LVU938
+ 3271              	.LBB442:
+ 3272              	.LBI442:
+2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3273              		.loc 2 2877 26 view .LVU939
+ 3274              	.LBB443:
+2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3275              		.loc 2 2879 3 view .LVU940
+2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3276              		.loc 2 2879 21 is_stmt 0 view .LVU941
+ 3277 0002 074B     		ldr	r3, .L260
+ 3278 0004 D3F88C30 		ldr	r3, [r3, #140]
+ 3279              	.LVL257:
+2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3280              		.loc 2 2879 21 view .LVU942
+ 3281              	.LBE443:
+ 3282              	.LBE442:
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 3283              		.loc 1 1114 3 view .LVU943
+ 3284 0008 1842     		tst	r0, r3
+ 3285 000a 04D1     		bne	.L257
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 3286              		.loc 1 1117 7 is_stmt 1 view .LVU944
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 3287              		.loc 1 1117 25 is_stmt 0 view .LVU945
+ 3288 000c 4FF44010 		mov	r0, #3145728
+ 3289              	.LVL258:
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 3290              		.loc 1 1117 25 view .LVU946
+ 3291 0010 FFF7FEFF 		bl	LL_RCC_GetSAIClockFreq
+ 3292              	.LVL259:
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 3293              		.loc 1 1118 7 is_stmt 1 view .LVU947
+ 3294              	.L256:
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DFSDM1_Channel0 */
+ 3295              		.loc 1 1127 1 is_stmt 0 view .LVU948
+ 3296 0014 08BD     		pop	{r3, pc}
+ 3297              	.LVL260:
+ 3298              	.L257:
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 3299              		.loc 1 1122 7 is_stmt 1 view .LVU949
+ARM GAS  /tmp/ccTMI75D.s 			page 180
+
+
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 3300              		.loc 1 1122 25 is_stmt 0 view .LVU950
+ 3301 0016 4FF44000 		mov	r0, #12582912
+ 3302              	.LVL261:
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 3303              		.loc 1 1122 25 view .LVU951
+ 3304 001a FFF7FEFF 		bl	LL_RCC_GetSAIClockFreq
+ 3305              	.LVL262:
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 3306              		.loc 1 1123 7 is_stmt 1 view .LVU952
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 3307              		.loc 1 1126 3 view .LVU953
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 3308              		.loc 1 1126 10 is_stmt 0 view .LVU954
+ 3309 001e F9E7     		b	.L256
+ 3310              	.L261:
+ 3311              		.align	2
+ 3312              	.L260:
+ 3313 0020 00380240 		.word	1073887232
+ 3314              		.cfi_endproc
+ 3315              	.LFE308:
+ 3317              		.section	.text.RCC_PLLI2S_GetFreqDomain_SPDIFRX,"ax",%progbits
+ 3318              		.align	1
+ 3319              		.global	RCC_PLLI2S_GetFreqDomain_SPDIFRX
+ 3320              		.syntax unified
+ 3321              		.thumb
+ 3322              		.thumb_func
+ 3323              		.fpu fpv5-d16
+ 3325              	RCC_PLLI2S_GetFreqDomain_SPDIFRX:
+ 3326              	.LFB321:
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SPDIFRX)
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return PLLI2S clock frequency used for SPDIFRX domain
+1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval PLLI2S clock frequency (in Hz)
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
+1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 3327              		.loc 1 1514 1 is_stmt 1 view -0
+ 3328              		.cfi_startproc
+ 3329              		@ args = 0, pretend = 0, frame = 0
+ 3330              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3331              		@ link register save eliminated.
+1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t pllinputfreq = 0U, pllsource = 0U;
+ 3332              		.loc 1 1515 3 view .LVU956
+ 3333              	.LVL263:
+1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      SPDIFRX Domain clock  = PLLI2S_VCO / PLLI2SP
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   pllsource = LL_RCC_PLL_GetMainSource();
+ 3334              		.loc 1 1520 3 view .LVU957
+ 3335              	.LBB444:
+ 3336              	.LBI444:
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3337              		.loc 2 3461 26 view .LVU958
+ 3338              	.LBB445:
+ARM GAS  /tmp/ccTMI75D.s 			page 181
+
+
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3339              		.loc 2 3463 3 view .LVU959
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3340              		.loc 2 3463 21 is_stmt 0 view .LVU960
+ 3341 0000 0E4B     		ldr	r3, .L265
+ 3342 0002 5B68     		ldr	r3, [r3, #4]
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3343              		.loc 2 3463 10 view .LVU961
+ 3344 0004 03F48003 		and	r3, r3, #4194304
+ 3345              	.LVL264:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3346              		.loc 2 3463 10 view .LVU962
+ 3347              	.LBE445:
+ 3348              	.LBE444:
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (pllsource)
+ 3349              		.loc 1 1522 3 is_stmt 1 view .LVU963
+ 3350 0008 ABB9     		cbnz	r3, .L264
+1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLI2S clock source */
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+ 3351              		.loc 1 1525 20 is_stmt 0 view .LVU964
+ 3352 000a 0D48     		ldr	r0, .L265+4
+ 3353              	.L263:
+ 3354              	.LVL265:
+1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLI2S clock source */
+1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSE_VALUE;
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ 3355              		.loc 1 1537 3 is_stmt 1 view .LVU965
+ 3356              	.LBB446:
+ 3357              	.LBI446:
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3358              		.loc 2 3601 26 view .LVU966
+ 3359              	.LBB447:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3360              		.loc 2 3603 3 view .LVU967
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3361              		.loc 2 3603 21 is_stmt 0 view .LVU968
+ 3362 000c 0B4B     		ldr	r3, .L265
+ 3363              	.LVL266:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3364              		.loc 2 3603 21 view .LVU969
+ 3365 000e 5A68     		ldr	r2, [r3, #4]
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3366              		.loc 2 3603 10 view .LVU970
+ 3367 0010 02F03F02 		and	r2, r2, #63
+ 3368              	.LBE447:
+ 3369              	.LBE446:
+ARM GAS  /tmp/ccTMI75D.s 			page 182
+
+
+ 3370              		.loc 1 1537 10 view .LVU971
+ 3371 0014 B0FBF2F0 		udiv	r0, r0, r2
+ 3372              	.LVL267:
+ 3373              	.LBB448:
+ 3374              	.LBI448:
+4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3375              		.loc 2 4040 26 is_stmt 1 view .LVU972
+ 3376              	.LBB449:
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3377              		.loc 2 4042 3 view .LVU973
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3378              		.loc 2 4042 21 is_stmt 0 view .LVU974
+ 3379 0018 D3F88420 		ldr	r2, [r3, #132]
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3380              		.loc 2 4042 10 view .LVU975
+ 3381 001c C2F38812 		ubfx	r2, r2, #6, #9
+ 3382              	.LBE449:
+ 3383              	.LBE448:
+ 3384              		.loc 1 1537 10 view .LVU976
+ 3385 0020 02FB00F0 		mul	r0, r2, r0
+ 3386              	.LBB450:
+ 3387              	.LBI450:
+4097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3388              		.loc 2 4097 26 is_stmt 1 view .LVU977
+ 3389              	.LBB451:
+4099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3390              		.loc 2 4099 3 view .LVU978
+4099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3391              		.loc 2 4099 21 is_stmt 0 view .LVU979
+ 3392 0024 D3F88430 		ldr	r3, [r3, #132]
+ 3393              	.LBE451:
+ 3394              	.LBE450:
+ 3395              		.loc 1 1537 10 view .LVU980
+ 3396 0028 C3F30143 		ubfx	r3, r3, #16, #2
+ 3397 002c 0133     		adds	r3, r3, #1
+ 3398 002e 5B00     		lsls	r3, r3, #1
+1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                         LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 3399              		.loc 1 1539 1 view .LVU981
+ 3400 0030 B0FBF3F0 		udiv	r0, r0, r3
+ 3401 0034 7047     		bx	lr
+ 3402              	.LVL268:
+ 3403              	.L264:
+1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 3404              		.loc 1 1529 20 view .LVU982
+ 3405 0036 0348     		ldr	r0, .L265+8
+ 3406 0038 E8E7     		b	.L263
+ 3407              	.L266:
+ 3408 003a 00BF     		.align	2
+ 3409              	.L265:
+ 3410 003c 00380240 		.word	1073887232
+ 3411 0040 0024F400 		.word	16000000
+ 3412 0044 40787D01 		.word	25000000
+ 3413              		.cfi_endproc
+ 3414              	.LFE321:
+ 3416              		.section	.text.LL_RCC_GetSPDIFRXClockFreq,"ax",%progbits
+ 3417              		.align	1
+ARM GAS  /tmp/ccTMI75D.s 			page 183
+
+
+ 3418              		.global	LL_RCC_GetSPDIFRXClockFreq
+ 3419              		.syntax unified
+ 3420              		.thumb
+ 3421              		.thumb_func
+ 3422              		.fpu fpv5-d16
+ 3424              	LL_RCC_GetSPDIFRXClockFreq:
+ 3425              	.LVL269:
+ 3426              	.LFB310:
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 3427              		.loc 1 1199 1 is_stmt 1 view -0
+ 3428              		.cfi_startproc
+ 3429              		@ args = 0, pretend = 0, frame = 0
+ 3430              		@ frame_needed = 0, uses_anonymous_args = 0
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 3431              		.loc 1 1199 1 is_stmt 0 view .LVU984
+ 3432 0000 08B5     		push	{r3, lr}
+ 3433              	.LCFI15:
+ 3434              		.cfi_def_cfa_offset 8
+ 3435              		.cfi_offset 3, -8
+ 3436              		.cfi_offset 14, -4
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 3437              		.loc 1 1200 3 is_stmt 1 view .LVU985
+ 3438              	.LVL270:
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 3439              		.loc 1 1203 3 view .LVU986
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 3440              		.loc 1 1205 3 view .LVU987
+ 3441              	.LBB452:
+ 3442              	.LBI452:
+3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3443              		.loc 2 3711 26 view .LVU988
+ 3444              	.LBB453:
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3445              		.loc 2 3713 3 view .LVU989
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3446              		.loc 2 3713 11 is_stmt 0 view .LVU990
+ 3447 0002 044B     		ldr	r3, .L271
+ 3448 0004 1868     		ldr	r0, [r3]
+ 3449              	.LVL271:
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3450              		.loc 2 3713 11 view .LVU991
+ 3451              	.LBE453:
+ 3452              	.LBE452:
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 3453              		.loc 1 1205 6 view .LVU992
+ 3454 0006 10F00060 		ands	r0, r0, #134217728
+ 3455 000a 00D1     		bne	.L270
+ 3456              	.LVL272:
+ 3457              	.L267:
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SPDIFRX */
+ 3458              		.loc 1 1211 1 view .LVU993
+ 3459 000c 08BD     		pop	{r3, pc}
+ 3460              	.LVL273:
+ 3461              	.L270:
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ 3462              		.loc 1 1207 6 is_stmt 1 view .LVU994
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+ARM GAS  /tmp/ccTMI75D.s 			page 184
+
+
+ 3463              		.loc 1 1207 26 is_stmt 0 view .LVU995
+ 3464 000e FFF7FEFF 		bl	RCC_PLLI2S_GetFreqDomain_SPDIFRX
+ 3465              	.LVL274:
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 3466              		.loc 1 1210 3 is_stmt 1 view .LVU996
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 3467              		.loc 1 1210 10 is_stmt 0 view .LVU997
+ 3468 0012 FBE7     		b	.L267
+ 3469              	.L272:
+ 3470              		.align	2
+ 3471              	.L271:
+ 3472 0014 00380240 		.word	1073887232
+ 3473              		.cfi_endproc
+ 3474              	.LFE310:
+ 3476              		.section	.text.RCC_PLLI2S_GetFreqDomain_I2S,"ax",%progbits
+ 3477              		.align	1
+ 3478              		.global	RCC_PLLI2S_GetFreqDomain_I2S
+ 3479              		.syntax unified
+ 3480              		.thumb
+ 3481              		.thumb_func
+ 3482              		.fpu fpv5-d16
+ 3484              	RCC_PLLI2S_GetFreqDomain_I2S:
+ 3485              	.LFB322:
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SPDIFRX */
+1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /**
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @brief  Return PLLI2S clock frequency used for I2S domain
+1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   * @retval PLLI2S clock frequency (in Hz)
+1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {
+ 3486              		.loc 1 1547 1 is_stmt 1 view -0
+ 3487              		.cfi_startproc
+ 3488              		@ args = 0, pretend = 0, frame = 0
+ 3489              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3490              		@ link register save eliminated.
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t pllinputfreq = 0U, pllsource = 0U;
+ 3491              		.loc 1 1548 3 view .LVU999
+ 3492              	.LVL275:
+1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
+1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****      I2S Domain clock  = PLLI2S_VCO / PLLI2SR
+1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   */
+1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   pllsource = LL_RCC_PLL_GetMainSource();
+ 3493              		.loc 1 1553 3 view .LVU1000
+ 3494              	.LBB454:
+ 3495              	.LBI454:
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3496              		.loc 2 3461 26 view .LVU1001
+ 3497              	.LBB455:
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3498              		.loc 2 3463 3 view .LVU1002
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3499              		.loc 2 3463 21 is_stmt 0 view .LVU1003
+ 3500 0000 0D4B     		ldr	r3, .L276
+ 3501 0002 5B68     		ldr	r3, [r3, #4]
+ 3502              	.LVL276:
+ARM GAS  /tmp/ccTMI75D.s 			page 185
+
+
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3503              		.loc 2 3463 21 view .LVU1004
+ 3504              	.LBE455:
+ 3505              	.LBE454:
+1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   switch (pllsource)
+ 3506              		.loc 1 1555 3 is_stmt 1 view .LVU1005
+ 3507 0004 13F4800F 		tst	r3, #4194304
+ 3508 0008 13D0     		beq	.L275
+1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLI2S clock source */
+1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSE_VALUE;
+ 3509              		.loc 1 1558 20 is_stmt 0 view .LVU1006
+ 3510 000a 0C4B     		ldr	r3, .L276+4
+ 3511              	.LVL277:
+ 3512              	.L274:
+1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLI2S clock source */
+1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     default:
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       pllinputfreq = HSI_VALUE;
+1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   }
+1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   return __LL_RCC_CALC_PLLI2S_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ 3513              		.loc 1 1566 3 is_stmt 1 view .LVU1007
+ 3514              	.LBB456:
+ 3515              	.LBI456:
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3516              		.loc 2 3601 26 view .LVU1008
+ 3517              	.LBB457:
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3518              		.loc 2 3603 3 view .LVU1009
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3519              		.loc 2 3603 21 is_stmt 0 view .LVU1010
+ 3520 000c 0A4A     		ldr	r2, .L276
+ 3521 000e 5068     		ldr	r0, [r2, #4]
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3522              		.loc 2 3603 10 view .LVU1011
+ 3523 0010 00F03F00 		and	r0, r0, #63
+ 3524              	.LBE457:
+ 3525              	.LBE456:
+ 3526              		.loc 1 1566 10 view .LVU1012
+ 3527 0014 B3FBF0F3 		udiv	r3, r3, r0
+ 3528              	.LVL278:
+ 3529              	.LBB458:
+ 3530              	.LBI458:
+4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3531              		.loc 2 4040 26 is_stmt 1 view .LVU1013
+ 3532              	.LBB459:
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3533              		.loc 2 4042 3 view .LVU1014
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3534              		.loc 2 4042 21 is_stmt 0 view .LVU1015
+ 3535 0018 D2F88400 		ldr	r0, [r2, #132]
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3536              		.loc 2 4042 10 view .LVU1016
+ 3537 001c C0F38810 		ubfx	r0, r0, #6, #9
+ARM GAS  /tmp/ccTMI75D.s 			page 186
+
+
+ 3538              	.LBE459:
+ 3539              	.LBE458:
+ 3540              		.loc 1 1566 10 view .LVU1017
+ 3541 0020 00FB03F3 		mul	r3, r0, r3
+ 3542              	.LBB460:
+ 3543              	.LBI460:
+4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3544              		.loc 2 4081 26 is_stmt 1 view .LVU1018
+ 3545              	.LBB461:
+4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3546              		.loc 2 4083 3 view .LVU1019
+4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3547              		.loc 2 4083 21 is_stmt 0 view .LVU1020
+ 3548 0024 D2F88400 		ldr	r0, [r2, #132]
+ 3549              	.LBE461:
+ 3550              	.LBE460:
+ 3551              		.loc 1 1566 10 view .LVU1021
+ 3552 0028 C0F30270 		ubfx	r0, r0, #28, #3
+1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****                                         LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
+1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 3553              		.loc 1 1568 1 view .LVU1022
+ 3554 002c B3FBF0F0 		udiv	r0, r3, r0
+ 3555 0030 7047     		bx	lr
+ 3556              	.LVL279:
+ 3557              	.L275:
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 3558              		.loc 1 1563 20 view .LVU1023
+ 3559 0032 034B     		ldr	r3, .L276+8
+ 3560              	.LVL280:
+1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****       break;
+ 3561              		.loc 1 1563 20 view .LVU1024
+ 3562 0034 EAE7     		b	.L274
+ 3563              	.L277:
+ 3564 0036 00BF     		.align	2
+ 3565              	.L276:
+ 3566 0038 00380240 		.word	1073887232
+ 3567 003c 40787D01 		.word	25000000
+ 3568 0040 0024F400 		.word	16000000
+ 3569              		.cfi_endproc
+ 3570              	.LFE322:
+ 3572              		.section	.text.LL_RCC_GetI2SClockFreq,"ax",%progbits
+ 3573              		.align	1
+ 3574              		.global	LL_RCC_GetI2SClockFreq
+ 3575              		.syntax unified
+ 3576              		.thumb
+ 3577              		.thumb_func
+ 3578              		.fpu fpv5-d16
+ 3580              	LL_RCC_GetI2SClockFreq:
+ 3581              	.LVL281:
+ 3582              	.LFB300:
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 3583              		.loc 1 679 1 is_stmt 1 view -0
+ 3584              		.cfi_startproc
+ 3585              		@ args = 0, pretend = 0, frame = 0
+ 3586              		@ frame_needed = 0, uses_anonymous_args = 0
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 3587              		.loc 1 680 3 view .LVU1026
+ARM GAS  /tmp/ccTMI75D.s 			page 187
+
+
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 3588              		.loc 1 683 3 view .LVU1027
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 3589              		.loc 1 685 3 view .LVU1028
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   {
+ 3590              		.loc 1 685 6 is_stmt 0 view .LVU1029
+ 3591 0000 B0F5000F 		cmp	r0, #8388608
+ 3592 0004 01D0     		beq	.L286
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 3593              		.loc 1 680 12 view .LVU1030
+ 3594 0006 0020     		movs	r0, #0
+ 3595              	.LVL282:
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 3596              		.loc 1 705 1 view .LVU1031
+ 3597 0008 7047     		bx	lr
+ 3598              	.LVL283:
+ 3599              	.L286:
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****   uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 3600              		.loc 1 679 1 view .LVU1032
+ 3601 000a 08B5     		push	{r3, lr}
+ 3602              	.LCFI16:
+ 3603              		.cfi_def_cfa_offset 8
+ 3604              		.cfi_offset 3, -8
+ 3605              		.cfi_offset 14, -4
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 3606              		.loc 1 688 5 is_stmt 1 view .LVU1033
+ 3607              	.LVL284:
+ 3608              	.LBB462:
+ 3609              	.LBI462:
+2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3610              		.loc 2 2862 26 view .LVU1034
+ 3611              	.LBB463:
+2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3612              		.loc 2 2864 3 view .LVU1035
+2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3613              		.loc 2 2864 21 is_stmt 0 view .LVU1036
+ 3614 000c 074B     		ldr	r3, .L288
+ 3615 000e 9B68     		ldr	r3, [r3, #8]
+ 3616              	.LVL285:
+2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3617              		.loc 2 2864 21 view .LVU1037
+ 3618              	.LBE463:
+ 3619              	.LBE462:
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****     {
+ 3620              		.loc 1 688 5 view .LVU1038
+ 3621 0010 1842     		tst	r0, r3
+ 3622 0012 08D1     		bne	.L281
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 3623              		.loc 1 691 9 is_stmt 1 view .LVU1039
+ 3624              	.LBB464:
+ 3625              	.LBI464:
+3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 3626              		.loc 2 3711 26 view .LVU1040
+ 3627              	.LBB465:
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3628              		.loc 2 3713 3 view .LVU1041
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ARM GAS  /tmp/ccTMI75D.s 			page 188
+
+
+ 3629              		.loc 2 3713 11 is_stmt 0 view .LVU1042
+ 3630 0014 054B     		ldr	r3, .L288
+ 3631 0016 1868     		ldr	r0, [r3]
+ 3632              	.LVL286:
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 3633              		.loc 2 3713 11 view .LVU1043
+ 3634              	.LBE465:
+ 3635              	.LBE464:
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         {
+ 3636              		.loc 1 691 12 view .LVU1044
+ 3637 0018 10F00060 		ands	r0, r0, #134217728
+ 3638 001c 00D1     		bne	.L287
+ 3639              	.LVL287:
+ 3640              	.L278:
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 
+ 3641              		.loc 1 705 1 view .LVU1045
+ 3642 001e 08BD     		pop	{r3, pc}
+ 3643              	.LVL288:
+ 3644              	.L287:
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3645              		.loc 1 693 11 is_stmt 1 view .LVU1046
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3646              		.loc 1 693 27 is_stmt 0 view .LVU1047
+ 3647 0020 FFF7FEFF 		bl	RCC_PLLI2S_GetFreqDomain_I2S
+ 3648              	.LVL289:
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         }
+ 3649              		.loc 1 693 27 view .LVU1048
+ 3650 0024 FBE7     		b	.L278
+ 3651              	.LVL290:
+ 3652              	.L281:
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c ****         break;
+ 3653              		.loc 1 699 23 view .LVU1049
+ 3654 0026 0248     		ldr	r0, .L288+4
+ 3655              	.LVL291:
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 3656              		.loc 1 704 3 is_stmt 1 view .LVU1050
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** }
+ 3657              		.loc 1 704 10 is_stmt 0 view .LVU1051
+ 3658 0028 F9E7     		b	.L278
+ 3659              	.L289:
+ 3660 002a 00BF     		.align	2
+ 3661              	.L288:
+ 3662 002c 00380240 		.word	1073887232
+ 3663 0030 0080BB00 		.word	12288000
+ 3664              		.cfi_endproc
+ 3665              	.LFE300:
+ 3667              		.section	.rodata.aRCC_PLLSAIDIVRPrescTable,"a"
+ 3668              		.align	2
+ 3669              		.set	.LANCHOR0,. + 0
+ 3672              	aRCC_PLLSAIDIVRPrescTable:
+ 3673 0000 02040810 		.ascii	"\002\004\010\020"
+ 3674              		.text
+ 3675              	.Letext0:
+ 3676              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 3677              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h"
+ 3678              		.file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 3679              		.file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ARM GAS  /tmp/ccTMI75D.s 			page 189
+
+
+ARM GAS  /tmp/ccTMI75D.s 			page 190
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_ll_rcc.c
+     /tmp/ccTMI75D.s:17     .text.LL_RCC_DeInit:0000000000000000 $t
+     /tmp/ccTMI75D.s:25     .text.LL_RCC_DeInit:0000000000000000 LL_RCC_DeInit
+     /tmp/ccTMI75D.s:182    .text.LL_RCC_DeInit:000000000000008c $d
+     /tmp/ccTMI75D.s:189    .text.LL_RCC_GetCECClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:196    .text.LL_RCC_GetCECClockFreq:0000000000000000 LL_RCC_GetCECClockFreq
+     /tmp/ccTMI75D.s:274    .text.LL_RCC_GetCECClockFreq:000000000000002c $d
+     /tmp/ccTMI75D.s:279    .text.RCC_GetHCLKClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:286    .text.RCC_GetHCLKClockFreq:0000000000000000 RCC_GetHCLKClockFreq
+     /tmp/ccTMI75D.s:317    .text.RCC_GetHCLKClockFreq:0000000000000010 $d
+     /tmp/ccTMI75D.s:323    .text.RCC_GetPCLK1ClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:330    .text.RCC_GetPCLK1ClockFreq:0000000000000000 RCC_GetPCLK1ClockFreq
+     /tmp/ccTMI75D.s:361    .text.RCC_GetPCLK1ClockFreq:0000000000000010 $d
+     /tmp/ccTMI75D.s:367    .text.RCC_GetPCLK2ClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:374    .text.RCC_GetPCLK2ClockFreq:0000000000000000 RCC_GetPCLK2ClockFreq
+     /tmp/ccTMI75D.s:405    .text.RCC_GetPCLK2ClockFreq:0000000000000010 $d
+     /tmp/ccTMI75D.s:411    .text.RCC_PLL_GetFreqDomain_SYS:0000000000000000 $t
+     /tmp/ccTMI75D.s:418    .text.RCC_PLL_GetFreqDomain_SYS:0000000000000000 RCC_PLL_GetFreqDomain_SYS
+     /tmp/ccTMI75D.s:503    .text.RCC_PLL_GetFreqDomain_SYS:0000000000000038 $d
+     /tmp/ccTMI75D.s:510    .text.RCC_GetSystemClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:517    .text.RCC_GetSystemClockFreq:0000000000000000 RCC_GetSystemClockFreq
+     /tmp/ccTMI75D.s:570    .text.RCC_GetSystemClockFreq:0000000000000020 $d
+     /tmp/ccTMI75D.s:577    .text.LL_RCC_GetSystemClocksFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:584    .text.LL_RCC_GetSystemClocksFreq:0000000000000000 LL_RCC_GetSystemClocksFreq
+     /tmp/ccTMI75D.s:630    .text.LL_RCC_GetUSARTClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:637    .text.LL_RCC_GetUSARTClockFreq:0000000000000000 LL_RCC_GetUSARTClockFreq
+     /tmp/ccTMI75D.s:1009   .text.LL_RCC_GetUSARTClockFreq:0000000000000160 $d
+     /tmp/ccTMI75D.s:1019   .text.LL_RCC_GetUARTClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:1026   .text.LL_RCC_GetUARTClockFreq:0000000000000000 LL_RCC_GetUARTClockFreq
+     /tmp/ccTMI75D.s:1398   .text.LL_RCC_GetUARTClockFreq:0000000000000168 $d
+     /tmp/ccTMI75D.s:1408   .text.LL_RCC_GetI2CClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:1415   .text.LL_RCC_GetI2CClockFreq:0000000000000000 LL_RCC_GetI2CClockFreq
+     /tmp/ccTMI75D.s:1707   .text.LL_RCC_GetI2CClockFreq:0000000000000108 $d
+     /tmp/ccTMI75D.s:1717   .text.LL_RCC_GetLPTIMClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:1724   .text.LL_RCC_GetLPTIMClockFreq:0000000000000000 LL_RCC_GetLPTIMClockFreq
+     /tmp/ccTMI75D.s:1855   .text.LL_RCC_GetLPTIMClockFreq:0000000000000064 $d
+     /tmp/ccTMI75D.s:1861   .text.LL_RCC_GetDFSDMClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:1868   .text.LL_RCC_GetDFSDMClockFreq:0000000000000000 LL_RCC_GetDFSDMClockFreq
+     /tmp/ccTMI75D.s:1926   .text.LL_RCC_GetDFSDMClockFreq:0000000000000024 $d
+     /tmp/ccTMI75D.s:1931   .text.RCC_PLL_GetFreqDomain_48M:0000000000000000 $t
+     /tmp/ccTMI75D.s:1938   .text.RCC_PLL_GetFreqDomain_48M:0000000000000000 RCC_PLL_GetFreqDomain_48M
+     /tmp/ccTMI75D.s:2021   .text.RCC_PLL_GetFreqDomain_48M:0000000000000034 $d
+     /tmp/ccTMI75D.s:2028   .text.RCC_PLLSAI_GetFreqDomain_SAI:0000000000000000 $t
+     /tmp/ccTMI75D.s:2035   .text.RCC_PLLSAI_GetFreqDomain_SAI:0000000000000000 RCC_PLLSAI_GetFreqDomain_SAI
+     /tmp/ccTMI75D.s:2129   .text.RCC_PLLSAI_GetFreqDomain_SAI:0000000000000044 $d
+     /tmp/ccTMI75D.s:2136   .text.RCC_PLLSAI_GetFreqDomain_48M:0000000000000000 $t
+     /tmp/ccTMI75D.s:2143   .text.RCC_PLLSAI_GetFreqDomain_48M:0000000000000000 RCC_PLLSAI_GetFreqDomain_48M
+     /tmp/ccTMI75D.s:2228   .text.RCC_PLLSAI_GetFreqDomain_48M:000000000000003c $d
+     /tmp/ccTMI75D.s:2235   .text.LL_RCC_GetSDMMCClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:2242   .text.LL_RCC_GetSDMMCClockFreq:0000000000000000 LL_RCC_GetSDMMCClockFreq
+     /tmp/ccTMI75D.s:2441   .text.LL_RCC_GetSDMMCClockFreq:0000000000000090 $d
+     /tmp/ccTMI75D.s:2446   .text.LL_RCC_GetRNGClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:2453   .text.LL_RCC_GetRNGClockFreq:0000000000000000 LL_RCC_GetRNGClockFreq
+     /tmp/ccTMI75D.s:2541   .text.LL_RCC_GetRNGClockFreq:0000000000000030 $d
+     /tmp/ccTMI75D.s:2546   .text.LL_RCC_GetUSBClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:2553   .text.LL_RCC_GetUSBClockFreq:0000000000000000 LL_RCC_GetUSBClockFreq
+ARM GAS  /tmp/ccTMI75D.s 			page 191
+
+
+     /tmp/ccTMI75D.s:2641   .text.LL_RCC_GetUSBClockFreq:0000000000000030 $d
+     /tmp/ccTMI75D.s:2646   .text.RCC_PLLSAI_GetFreqDomain_LTDC:0000000000000000 $t
+     /tmp/ccTMI75D.s:2653   .text.RCC_PLLSAI_GetFreqDomain_LTDC:0000000000000000 RCC_PLLSAI_GetFreqDomain_LTDC
+     /tmp/ccTMI75D.s:2749   .text.RCC_PLLSAI_GetFreqDomain_LTDC:0000000000000048 $d
+     /tmp/ccTMI75D.s:2757   .text.LL_RCC_GetLTDCClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:2764   .text.LL_RCC_GetLTDCClockFreq:0000000000000000 LL_RCC_GetLTDCClockFreq
+     /tmp/ccTMI75D.s:2812   .text.LL_RCC_GetLTDCClockFreq:0000000000000014 $d
+     /tmp/ccTMI75D.s:2817   .text.RCC_PLLI2S_GetFreqDomain_SAI:0000000000000000 $t
+     /tmp/ccTMI75D.s:2824   .text.RCC_PLLI2S_GetFreqDomain_SAI:0000000000000000 RCC_PLLI2S_GetFreqDomain_SAI
+     /tmp/ccTMI75D.s:2919   .text.RCC_PLLI2S_GetFreqDomain_SAI:0000000000000044 $d
+     /tmp/ccTMI75D.s:2926   .text.LL_RCC_GetSAIClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:2933   .text.LL_RCC_GetSAIClockFreq:0000000000000000 LL_RCC_GetSAIClockFreq
+     /tmp/ccTMI75D.s:3238   .text.LL_RCC_GetSAIClockFreq:0000000000000108 $d
+     /tmp/ccTMI75D.s:3247   .text.LL_RCC_GetDFSDMAudioClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:3254   .text.LL_RCC_GetDFSDMAudioClockFreq:0000000000000000 LL_RCC_GetDFSDMAudioClockFreq
+     /tmp/ccTMI75D.s:3313   .text.LL_RCC_GetDFSDMAudioClockFreq:0000000000000020 $d
+     /tmp/ccTMI75D.s:3318   .text.RCC_PLLI2S_GetFreqDomain_SPDIFRX:0000000000000000 $t
+     /tmp/ccTMI75D.s:3325   .text.RCC_PLLI2S_GetFreqDomain_SPDIFRX:0000000000000000 RCC_PLLI2S_GetFreqDomain_SPDIFRX
+     /tmp/ccTMI75D.s:3410   .text.RCC_PLLI2S_GetFreqDomain_SPDIFRX:000000000000003c $d
+     /tmp/ccTMI75D.s:3417   .text.LL_RCC_GetSPDIFRXClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:3424   .text.LL_RCC_GetSPDIFRXClockFreq:0000000000000000 LL_RCC_GetSPDIFRXClockFreq
+     /tmp/ccTMI75D.s:3472   .text.LL_RCC_GetSPDIFRXClockFreq:0000000000000014 $d
+     /tmp/ccTMI75D.s:3477   .text.RCC_PLLI2S_GetFreqDomain_I2S:0000000000000000 $t
+     /tmp/ccTMI75D.s:3484   .text.RCC_PLLI2S_GetFreqDomain_I2S:0000000000000000 RCC_PLLI2S_GetFreqDomain_I2S
+     /tmp/ccTMI75D.s:3566   .text.RCC_PLLI2S_GetFreqDomain_I2S:0000000000000038 $d
+     /tmp/ccTMI75D.s:3573   .text.LL_RCC_GetI2SClockFreq:0000000000000000 $t
+     /tmp/ccTMI75D.s:3580   .text.LL_RCC_GetI2SClockFreq:0000000000000000 LL_RCC_GetI2SClockFreq
+     /tmp/ccTMI75D.s:3662   .text.LL_RCC_GetI2SClockFreq:000000000000002c $d
+     /tmp/ccTMI75D.s:3668   .rodata.aRCC_PLLSAIDIVRPrescTable:0000000000000000 $d
+     /tmp/ccTMI75D.s:3672   .rodata.aRCC_PLLSAIDIVRPrescTable:0000000000000000 aRCC_PLLSAIDIVRPrescTable
+
+UNDEFINED SYMBOLS
+AHBPrescTable
+APBPrescTable
diff --git a/build/stm32f7xx_ll_rcc.o b/build/stm32f7xx_ll_rcc.o
new file mode 100644
index 0000000..d331cc9
Binary files /dev/null and b/build/stm32f7xx_ll_rcc.o differ
diff --git a/build/stm32f7xx_ll_sdmmc.d b/build/stm32f7xx_ll_sdmmc.d
new file mode 100644
index 0000000..67d561b
--- /dev/null
+++ b/build/stm32f7xx_ll_sdmmc.d
@@ -0,0 +1,64 @@
+build/stm32f7xx_ll_sdmmc.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/stm32f7xx_ll_sdmmc.lst b/build/stm32f7xx_ll_sdmmc.lst
new file mode 100644
index 0000000..6409ab0
--- /dev/null
+++ b/build/stm32f7xx_ll_sdmmc.lst
@@ -0,0 +1,6130 @@
+ARM GAS  /tmp/ccODg7xx.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_ll_sdmmc.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.SDMMC_GetCmdError,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	SDMMC_GetCmdError:
+  25              	.LVL0:
+  26              	.LFB186:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @file    stm32f7xx_ll_sdmmc.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief   SDMMC Low Layer HAL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *    
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *          This file provides firmware functions to manage the following 
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *          functionalities of the SDMMC peripheral:
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *           + Initialization/de-initialization functions
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *           + I/O operation functions
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *           + Peripheral Control functions 
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *           + Peripheral State functions
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   ******************************************************************************
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @attention
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * Copyright (c) 2017 STMicroelectronics.
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * All rights reserved.
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * in the root directory of this software component.
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   ******************************************************************************
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   @verbatim
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   ==============================================================================
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        ##### SDMMC peripheral features #####
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   ==============================================================================        
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          devices.
+ARM GAS  /tmp/ccODg7xx.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..] The SDMMC features include the following:
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              for three different databus modes: 1-bit (default), 4-bit and 8-bit
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          (+) Full compliance with SD Memory Card Specifications Version 2.0
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              different data bus modes: 1-bit (default) and 4-bit
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Rev1.1)
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          (+) Data transfer up to 48 MHz for the 8 bit mode
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          (+) Data and command output enable signals to control external bidirectional drivers
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****    
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                            ##### How to use this driver #####
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   ==============================================================================
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..]
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       This driver is a considered as a driver of service for external devices drivers 
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       that interfaces with the SDMMC peripheral.
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs 
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       is used in the device's driver to perform SDMMC operations and functionalities.
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****    
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       This driver is almost transparent for the final user, it is only used to implement other
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       functionalities of the external device.
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****    
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..]
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           PLL is well configured.
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           The SDMMC peripheral uses two clock signals:
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           (++) APB2 bus clock (PCLK2)
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****        
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           peripheral.
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (+) Enable the Power ON State using the SDMMC_PowerState_ON() 
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           function and disable it using the function SDMMC_PowerState_OFF().
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                 
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT() 
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           and __SDMMC_DISABLE_IT() if you need to use interrupt mode. 
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (+) When using the DMA mode 
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           (++) Configure the DMA in the MSP layer of the external device
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           (++) Active the needed channel Request 
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                __SDMMC_DMA_DISABLE().
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (+) To control the CPSM (Command Path State Machine) and send 
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           commands to the card use the SDMMC_SendCommand(), 
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according 
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           to the selected command to be sent.
+ARM GAS  /tmp/ccODg7xx.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           The parameters that should be filled are:
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            (++) Command Argument
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            (++) Command Index
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            (++) Command Response type
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            (++) Command Wait
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            (++) CPSM Status (Enable or Disable).
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           -@@- To check if the command is well received, read the SDMMC_CMDRESP
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****               register using the SDMMC_GetCommandResponse().
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****               The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****               SDMMC_GetResponse() function.
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (+) To control the DPSM (Data Path State Machine) and send/receive 
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), 
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     *** Read Operations ***
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     =======================
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..]
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (#) First, user has to fill the data structure (pointer to
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           SDMMC_DataInitTypeDef) according to the selected data type to be received.
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           The parameters that should be filled are:
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            (++) Data TimeOut
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            (++) Data Length
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            (++) Data Block size
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            (++) Data Transfer direction: should be from card (To SDMMC)
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            (++) Data Transfer mode
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****            (++) DPSM Status (Enable or Disable)
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                                      
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (#) Configure the SDMMC resources to receive the data from the card
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           according to selected transfer mode (Refer to Step 8, 9 and 10).
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (#) Send the selected Read command (refer to step 11).
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                     
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       (#) Use the SDMMC flags/interrupts to check the transfer status.
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     *** Write Operations ***
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     ========================
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..]
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****      (#) First, user has to fill the data structure (pointer to
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          SDMMC_DataInitTypeDef) according to the selected data type to be received.
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          The parameters that should be filled are:
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           (++) Data TimeOut
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           (++) Data Length
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           (++) Data Block size
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           (++) Data Transfer direction:  should be to card (To CARD)
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           (++) Data Transfer mode
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****           (++) DPSM Status (Enable or Disable)
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****      (#) Configure the SDMMC resources to send the data to the card according to 
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          selected transfer mode.
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                      
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****      (#) Send the selected Write command.
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                     
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****      (#) Use the SDMMC flags/interrupts to check the transfer status.
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****        
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     *** Command management operations ***
+ARM GAS  /tmp/ccODg7xx.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     =====================================
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..]
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****      (#) The commands used for Read/Write/Erase operations are managed in 
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          separate functions. 
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          Each function allows to send the needed command with the related argument,
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          then check the response.
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          By the same approach, you could implement a command and check the response.
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   @endverbatim
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   ******************************************************************************
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */ 
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Includes ------------------------------------------------------------------*/
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** #include "stm32f7xx_hal.h"
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** #if defined(SDMMC1)
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @addtogroup STM32F7xx_HAL_Driver
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @{
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup SDMMC_LL SDMMC Low Layer
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief Low layer module for SD
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @{
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private typedef -----------------------------------------------------------*/
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private define ------------------------------------------------------------*/
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private macro -------------------------------------------------------------*/
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private variables ---------------------------------------------------------*/
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private function prototypes -----------------------------------------------*/
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx);
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Exported functions --------------------------------------------------------*/
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @{
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions 
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  *  @brief    Initialization and Configuration functions 
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  *
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @verbatim    
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  ===============================================================================
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****               ##### Initialization/de-initialization functions #####
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  ===============================================================================
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..]  This section provides functions allowing to:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @endverbatim
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @{
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Initializes the SDMMC according to the specified
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         parameters in the SDMMC_InitTypeDef and create the associated handle.
+ARM GAS  /tmp/ccODg7xx.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  Init: SDMMC initialization structure   
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t tmpreg = 0;
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check the parameters */
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); 
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set SDMMC configuration parameters */
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   tmpreg |= (Init.ClockEdge           |\
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.ClockBypass         |\
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.ClockPowerSave      |\
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.BusWide             |\
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.HardwareFlowControl |\
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.ClockDiv
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              ); 
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Write to SDMMC CLKCR */
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);  
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return HAL_OK;
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @}
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions 
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  *  @brief   Data transfers functions 
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  *
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @verbatim   
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  ===============================================================================
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                       ##### I/O operation functions #####
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  ===============================================================================  
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..]
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     This subsection provides a set of functions allowing to manage the SDMMC data 
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     transfers.
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @endverbatim
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @{
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Read data (word) from Rx FIFO in blocking mode (polling) 
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ARM GAS  /tmp/ccODg7xx.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Read data from Rx FIFO */ 
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return (SDMMCx->FIFO);
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Write data (word) to Tx FIFO in blocking mode (polling) 
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  pWriteData: pointer to data to write
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { 
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Write data to FIFO */ 
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMCx->FIFO = *pWriteData;
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return HAL_OK;
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @}
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions 
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  *  @brief   management functions 
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  *
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @verbatim   
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  ===============================================================================
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                       ##### Peripheral Control functions #####
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  ===============================================================================  
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..]
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     This subsection provides a set of functions allowing to control the SDMMC data 
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     transfers.
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @endverbatim
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @{
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Set SDMMC Power state to ON. 
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {  
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set power state to ON */ 
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMCx->POWER = SDMMC_POWER_PWRCTRL;
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return HAL_OK;
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Set SDMMC Power state to OFF. 
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ARM GAS  /tmp/ccODg7xx.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set power state to OFF */
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMCx->POWER = (uint32_t)0x00000000;
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return HAL_OK;
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Get SDMMC Power state. 
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval Power status of the controller. The returned value can be one of the 
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         following values:
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *            - 0x00: Power OFF
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *            - 0x02: Power UP
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *            - 0x03: Power ON 
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)  
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Configure the SDMMC command path according to the specified parameters in
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         SDMMC_CmdInitTypeDef structure and send the command 
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  Command: pointer to a SDMMC_CmdInitTypeDef structure that contains 
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         the configuration information for the SDMMC command
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t tmpreg = 0;
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check the parameters */
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_RESPONSE(Command->Response));
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_CPSM(Command->CPSM));
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set the SDMMC Argument value */
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMCx->ARG = Command->Argument;
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set SDMMC command parameters */
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   tmpreg |= (uint32_t)(Command->CmdIndex         |\
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Command->Response         |\
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Command->WaitForInterrupt |\
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Command->CPSM);
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Write to SDMMC CMD register */
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); 
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return HAL_OK;  
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Return the command index of last command for which response received
+ARM GAS  /tmp/ccODg7xx.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval Command index of the last command response received
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return (uint8_t)(SDMMCx->RESPCMD);
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Return the response received from the card for the last command
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base    
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  Response: Specifies the SDMMC response register. 
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *          This parameter can be one of the following values:
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *            @arg SDMMC_RESP1: Response Register 1
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *            @arg SDMMC_RESP2: Response Register 2
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *            @arg SDMMC_RESP3: Response Register 3
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *            @arg SDMMC_RESP4: Response Register 4  
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval The Corresponding response register value
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t tmp;
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check the parameters */
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_RESP(Response));
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Get the response */
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response;
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return (*(__IO uint32_t *) tmp);
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }  
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Configure the SDMMC data path according to the specified 
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         parameters in the SDMMC_DataInitTypeDef.
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base  
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  Data : pointer to a SDMMC_DataInitTypeDef structure 
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         that contains the configuration information for the SDMMC data.
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t tmpreg = 0;
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check the parameters */
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_DPSM(Data->DPSM));
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set the SDMMC Data TimeOut value */
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMCx->DTIMER = Data->DataTimeOut;
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set the SDMMC DataLength value */
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMCx->DLEN = Data->DataLength;
+ARM GAS  /tmp/ccODg7xx.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set the SDMMC data configuration parameters */
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   tmpreg |= (uint32_t)(Data->DataBlockSize |\
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Data->TransferDir   |\
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Data->TransferMode  |\
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Data->DPSM);
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Write to SDMMC DCTRL */
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return HAL_OK;
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Returns number of remaining data bytes to be transferred.
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval Number of remaining data bytes to be transferred
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return (SDMMCx->DCOUNT);
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Get the FIFO data
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval Data received
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return (SDMMCx->FIFO);
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Sets one of the two options of inserting read wait interval.
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base   
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *          This parameter can be:
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *            @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *            @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval None
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check the parameters */
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set SDMMC read wait mode */
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return HAL_OK;  
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @}
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ARM GAS  /tmp/ccODg7xx.s 			page 10
+
+
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup HAL_SDMMC_LL_Group4 Command management functions 
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  *  @brief   Data transfers functions 
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  *
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @verbatim   
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  ===============================================================================
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                    ##### Commands management functions #####
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  ===============================================================================  
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..]
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     This subsection provides a set of functions allowing to manage the needed commands.
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @endverbatim
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @{
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Data Block Length command and check the response
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set Block Size for Card */ 
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)BlockSize;
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Read Single Block command and check the response
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set Block Size for Card */ 
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ARM GAS  /tmp/ccODg7xx.s 			page 11
+
+
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Read Multi Block command and check the response
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set Block Size for Card */ 
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Write Single Block command and check the response
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set Block Size for Card */ 
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Write Multi Block command and check the response
+ARM GAS  /tmp/ccODg7xx.s 			page 12
+
+
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set Block Size for Card */ 
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Start Address Erase command for SD and check the response
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set Block Size for Card */ 
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the End Address Erase command for SD and check the response
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set Block Size for Card */ 
+ARM GAS  /tmp/ccODg7xx.s 			page 13
+
+
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Start Address Erase command and check the response
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set Block Size for Card */ 
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the End Address Erase command and check the response
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set Block Size for Card */ 
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+ARM GAS  /tmp/ccODg7xx.s 			page 14
+
+
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Erase command and check the response
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set Block Size for Card */ 
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = 0U;
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT);
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Stop Transfer command and check the response.
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Send CMD12 STOP_TRANSMISSION  */
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = 0U;
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT);
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Select Deselect command and check the response.
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  addr: Address of the card to be selected  
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ARM GAS  /tmp/ccODg7xx.s 			page 15
+
+
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Send CMD7 SDMMC_SEL_DESEL_CARD */
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)Addr;
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Go Idle State command and check the response.
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = 0U;
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_NO;
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdError(SDMMCx);
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Operating Condition command and check the response.
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Send CMD8 to verify SD card interface operating condition */
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Argument: - [31:12]: Reserved (shall be set to '0')
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   - [7:0]: Check Pattern (recommended 0xAA) */
+ARM GAS  /tmp/ccODg7xx.s 			page 16
+
+
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* CMD Response: R7 */
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = SDMMC_CHECK_PATTERN;
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp7(SDMMCx);
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Application command to verify that that the next command 
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         is an application specific com-mand rather than a standard command
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         and check the response.
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  Argument: Command Argument 
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)Argument;
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* If there is a HAL_ERROR, it is a MMC card, else
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   it is a SD card: SD card 2.0 (voltage range mismatch)
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****      or SD card 1.x */
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT);
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the command asking the accessed card to send its operating 
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         condition register (OCR)
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  Argument: Command Argument
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = SDMMC_VOLTAGE_WINDOW_SD | Argument;
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
+ARM GAS  /tmp/ccODg7xx.s 			page 17
+
+
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp3(SDMMCx);
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Bus Width command and check the response.
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  BusWidth: BusWidth
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = (uint32_t)BusWidth;
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Send SCR command and check the response.
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Send CMD51 SD_APP_SEND_SCR */
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = 0U;
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ARM GAS  /tmp/ccODg7xx.s 			page 18
+
+
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Send CID command and check the response.
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Send CMD2 ALL_SEND_CID */
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = 0U;
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp2(SDMMCx);
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Send CSD command and check the response.
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  Argument: Command Argument
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Send CMD9 SEND_CSD */
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = Argument;
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp2(SDMMCx);
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Send CSD command and check the response.
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  pRCA: Card RCA  
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+ARM GAS  /tmp/ccODg7xx.s 			page 19
+
+
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Send CMD3 SD_CMD_SET_REL_ADDR */
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = 0U;
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA);
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Set Relative Address command to MMC card (not SD card).
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx Pointer to SDMMC register base
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  RCA Card RCA
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA)
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Send CMD3 SD_CMD_SET_REL_ADDR */
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = ((uint32_t)RCA << 16U);
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT);
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Status command and check the response.
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  Argument: Command Argument
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = Argument;
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;
+ARM GAS  /tmp/ccODg7xx.s 			page 20
+
+
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Status register command and check the response.
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = 0U;
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Sends host capacity support information and activates the card's 
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         initialization process. Send SDMMC_CMD_SEND_OP_COND command
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @parame Argument: Argument used for the command
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = Argument;
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp3(SDMMCx);
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+ARM GAS  /tmp/ccODg7xx.s 			page 21
+
+
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx: Pointer to SDMMC register base 
+1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @parame Argument: Argument used for the command
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* CMD Response: R1 */
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT);
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Send the Send EXT_CSD command and check the response.
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx Pointer to SDMMC register base
+1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  Argument Command Argument
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval HAL status
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Send CMD9 SEND_CSD */
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Argument         = Argument;
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check for error conditions */
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT);
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return errorstate;
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @}
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ARM GAS  /tmp/ccODg7xx.s 			page 22
+
+
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup HAL_SDMMC_LL_Group5 Responses management functions
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  *  @brief   Responses functions
+1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  *
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @verbatim
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  ===============================================================================
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                    ##### Responses management functions #####
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****  ===============================================================================
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     [..]
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     This subsection provides a set of functions allowing to manage the needed responses.
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @endverbatim
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @{
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Checks for error conditions for R1 response.
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx Pointer to SDMMC register base
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SD_CMD: The sent command index  
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval SD Card error state
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t response_r1;
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* 8 is the number of required instructions cycles for the below loop statement.
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   The Timeout is expressed in ms */
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   do
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     if (count-- == 0U)
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       return SDMMC_ERROR_TIMEOUT;
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     sta_reg = SDMMCx->STA;
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CMD_CRC_FAIL;
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     /* Nothing to do */
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Clear all the static flags */
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+ARM GAS  /tmp/ccODg7xx.s 			page 23
+
+
+1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check response received is of desired command */
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CMD_CRC_FAIL;
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* We have received response, retrieve it for analysis  */
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_NONE;
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_ADDR_MISALIGNED;
+1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_BLOCK_LEN_ERR;
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_ERASE_SEQ_ERR;
+1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_BAD_ERASE_PARAM;
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_WRITE_PROT_VIOLATION;
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_COM_CRC_FAILED;
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_ILLEGAL_CMD;
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CARD_ECC_FAILED;
+1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CC_ERR;
+ARM GAS  /tmp/ccODg7xx.s 			page 24
+
+
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_STREAM_READ_UNDERRUN;
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
+1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CID_CSD_OVERWRITE;
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_WP_ERASE_SKIP;
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CARD_ECC_DISABLED;
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_ERASE_RESET;
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_AKE_SEQ_ERR;
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Checks for error conditions for R2 (CID or CSD) response.
+1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx Pointer to SDMMC register base
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval SD Card error state
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* 8 is the number of required instructions cycles for the below loop statement.
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   The SDMMC_CMDTIMEOUT is expressed in ms */
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   do
+1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     if (count-- == 0U)
+1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       return SDMMC_ERROR_TIMEOUT;
+1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     sta_reg = SDMMCx->STA;
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ARM GAS  /tmp/ccODg7xx.s 			page 25
+
+
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CMD_CRC_FAIL;
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     /* No error flag set */
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     /* Clear all the static flags */
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return SDMMC_ERROR_NONE;
+1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Checks for error conditions for R3 (OCR) response.
+1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx Pointer to SDMMC register base
+1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval SD Card error state
+1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* 8 is the number of required instructions cycles for the below loop statement.
+1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   The SDMMC_CMDTIMEOUT is expressed in ms */
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   do
+1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     if (count-- == 0U)
+1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       return SDMMC_ERROR_TIMEOUT;
+1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     sta_reg = SDMMCx->STA;
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else
+1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {  
+1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     /* Clear all the static flags */
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return SDMMC_ERROR_NONE;
+ARM GAS  /tmp/ccODg7xx.s 			page 26
+
+
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Checks for error conditions for R6 (RCA) response.
+1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx Pointer to SDMMC register base
+1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SD_CMD: The sent command index
+1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  pRCA: Pointer to the variable that will contain the SD card relative 
+1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   *         address RCA   
+1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval SD Card error state
+1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t response_r1;
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* 8 is the number of required instructions cycles for the below loop statement.
+1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   The SDMMC_CMDTIMEOUT is expressed in ms */
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   do
+1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     if (count-- == 0U)
+1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       return SDMMC_ERROR_TIMEOUT;
+1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     sta_reg = SDMMCx->STA;
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CMD_CRC_FAIL;
+1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else
+1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     /* Nothing to do */
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check response received is of desired command */
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CMD_CRC_FAIL;
+1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Clear all the static flags */
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* We have received response, retrieve it.  */
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+ARM GAS  /tmp/ccODg7xx.s 			page 27
+
+
+1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILE
+1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     *pRCA = (uint16_t) (response_r1 >> 16);
+1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_NONE;
+1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_ILLEGAL_CMD;
+1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_COM_CRC_FAILED;
+1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else
+1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Checks for error conditions for R7 response.
+1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx Pointer to SDMMC register base
+1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval SD Card error state
+1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
+1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* 8 is the number of required instructions cycles for the below loop statement.
+1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   The SDMMC_CMDTIMEOUT is expressed in ms */
+1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   do
+1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     if (count-- == 0U)
+1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       return SDMMC_ERROR_TIMEOUT;
+1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     sta_reg = SDMMCx->STA;
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     /* Card is SD V2.0 compliant */
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     /* Card is SD V2.0 compliant */
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     return SDMMC_ERROR_CMD_CRC_FAIL;
+1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ARM GAS  /tmp/ccODg7xx.s 			page 28
+
+
+1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   else
+1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     /* Nothing to do */
+1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
+1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     /* Card is SD V2.0 compliant */
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
+1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return SDMMC_ERROR_NONE;
+1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @}
+1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private function ----------------------------------------------------------*/  
+1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @addtogroup SD_Private_Functions
+1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @{
+1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /**
+1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @brief  Checks for error conditions for CMD0.
+1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @param  SDMMCx Pointer to SDMMC register base
+1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   * @retval SD Card error state
+1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   */
+1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
+1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** {
+  28              		.loc 1 1544 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* 8 is the number of required instructions cycles for the below loop statement.
+1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   The SDMMC_CMDTIMEOUT is expressed in ms */
+1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  33              		.loc 1 1547 3 view .LVU1
+  34              		.loc 1 1547 61 is_stmt 0 view .LVU2
+  35 0000 0B4B     		ldr	r3, .L5
+  36 0002 1B68     		ldr	r3, [r3]
+  37 0004 0B4A     		ldr	r2, .L5+4
+  38 0006 A2FB0323 		umull	r2, r3, r2, r3
+  39 000a 5B0A     		lsrs	r3, r3, #9
+  40              		.loc 1 1547 12 view .LVU3
+  41 000c 41F28832 		movw	r2, #5000
+  42 0010 02FB03F3 		mul	r3, r2, r3
+  43              	.LVL1:
+  44              	.L3:
+1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   do
+  45              		.loc 1 1549 3 is_stmt 1 view .LVU4
+1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     if (count-- == 0U)
+  46              		.loc 1 1551 5 view .LVU5
+ARM GAS  /tmp/ccODg7xx.s 			page 29
+
+
+  47 0014 1A46     		mov	r2, r3
+  48              		.loc 1 1551 14 is_stmt 0 view .LVU6
+  49 0016 013B     		subs	r3, r3, #1
+  50              	.LVL2:
+  51              		.loc 1 1551 8 view .LVU7
+  52 0018 3AB1     		cbz	r2, .L4
+1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****       return SDMMC_ERROR_TIMEOUT;
+1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
+  53              		.loc 1 1556 9 is_stmt 1 view .LVU8
+  54              		.loc 1 1556 11 is_stmt 0 view .LVU9
+  55 001a 426B     		ldr	r2, [r0, #52]
+  56              		.loc 1 1556 3 view .LVU10
+  57 001c 12F0800F 		tst	r2, #128
+  58 0020 F8D0     		beq	.L3
+1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Clear all the static flags */
+1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  59              		.loc 1 1559 3 is_stmt 1 view .LVU11
+  60 0022 C523     		movs	r3, #197
+  61              	.LVL3:
+  62              		.loc 1 1559 3 is_stmt 0 view .LVU12
+  63 0024 8363     		str	r3, [r0, #56]
+1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return SDMMC_ERROR_NONE;
+  64              		.loc 1 1561 3 is_stmt 1 view .LVU13
+  65              		.loc 1 1561 10 is_stmt 0 view .LVU14
+  66 0026 0020     		movs	r0, #0
+  67              	.LVL4:
+  68              		.loc 1 1561 10 view .LVU15
+  69 0028 7047     		bx	lr
+  70              	.LVL5:
+  71              	.L4:
+1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+  72              		.loc 1 1553 14 view .LVU16
+  73 002a 4FF00040 		mov	r0, #-2147483648
+  74              	.LVL6:
+1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+  75              		.loc 1 1562 1 view .LVU17
+  76 002e 7047     		bx	lr
+  77              	.L6:
+  78              		.align	2
+  79              	.L5:
+  80 0030 00000000 		.word	SystemCoreClock
+  81 0034 D34D6210 		.word	274877907
+  82              		.cfi_endproc
+  83              	.LFE186:
+  85              		.section	.text.SDMMC_Init,"ax",%progbits
+  86              		.align	1
+  87              		.global	SDMMC_Init
+  88              		.syntax unified
+  89              		.thumb
+  90              		.thumb_func
+  91              		.fpu fpv5-d16
+  93              	SDMMC_Init:
+ARM GAS  /tmp/ccODg7xx.s 			page 30
+
+
+  94              	.LVL7:
+  95              	.LFB141:
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t tmpreg = 0;
+  96              		.loc 1 208 1 is_stmt 1 view -0
+  97              		.cfi_startproc
+  98              		@ args = 28, pretend = 16, frame = 0
+  99              		@ frame_needed = 0, uses_anonymous_args = 0
+ 100              		@ link register save eliminated.
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t tmpreg = 0;
+ 101              		.loc 1 208 1 is_stmt 0 view .LVU19
+ 102 0000 84B0     		sub	sp, sp, #16
+ 103              	.LCFI0:
+ 104              		.cfi_def_cfa_offset 16
+ 105 0002 0DF1040C 		add	ip, sp, #4
+ 106 0006 8CE80E00 		stm	ip, {r1, r2, r3}
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 107              		.loc 1 209 3 is_stmt 1 view .LVU20
+ 108              	.LVL8:
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); 
+ 109              		.loc 1 212 3 view .LVU21
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));
+ 110              		.loc 1 213 3 view .LVU22
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
+ 111              		.loc 1 214 3 view .LVU23
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
+ 112              		.loc 1 215 3 view .LVU24
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+ 113              		.loc 1 216 3 view .LVU25
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
+ 114              		.loc 1 217 3 view .LVU26
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 115              		.loc 1 218 3 view .LVU27
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.ClockBypass         |\
+ 116              		.loc 1 221 3 view .LVU28
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.ClockBypass         |\
+ 117              		.loc 1 221 39 is_stmt 0 view .LVU29
+ 118 000a 0B46     		mov	r3, r1
+ 119 000c 1343     		orrs	r3, r3, r2
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.BusWide             |\
+ 120              		.loc 1 223 18 view .LVU30
+ 121 000e 039A     		ldr	r2, [sp, #12]
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.ClockPowerSave      |\
+ 122              		.loc 1 222 39 view .LVU31
+ 123 0010 1343     		orrs	r3, r3, r2
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.HardwareFlowControl |\
+ 124              		.loc 1 224 18 view .LVU32
+ 125 0012 049A     		ldr	r2, [sp, #16]
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.BusWide             |\
+ 126              		.loc 1 223 39 view .LVU33
+ 127 0014 1343     		orrs	r3, r3, r2
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.ClockDiv
+ 128              		.loc 1 225 18 view .LVU34
+ 129 0016 059A     		ldr	r2, [sp, #20]
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.HardwareFlowControl |\
+ 130              		.loc 1 224 39 view .LVU35
+ 131 0018 1343     		orrs	r3, r3, r2
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              ); 
+ARM GAS  /tmp/ccODg7xx.s 			page 31
+
+
+ 132              		.loc 1 226 18 view .LVU36
+ 133 001a 069A     		ldr	r2, [sp, #24]
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****              Init.ClockDiv
+ 134              		.loc 1 225 39 view .LVU37
+ 135 001c 1343     		orrs	r3, r3, r2
+ 136              	.LVL9:
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 137              		.loc 1 230 3 is_stmt 1 view .LVU38
+ 138 001e 4168     		ldr	r1, [r0, #4]
+ 139 0020 034A     		ldr	r2, .L9
+ 140 0022 0A40     		ands	r2, r2, r1
+ 141 0024 1343     		orrs	r3, r3, r2
+ 142              	.LVL10:
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 143              		.loc 1 230 3 is_stmt 0 view .LVU39
+ 144 0026 4360     		str	r3, [r0, #4]
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 145              		.loc 1 232 3 is_stmt 1 view .LVU40
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 146              		.loc 1 233 1 is_stmt 0 view .LVU41
+ 147 0028 0020     		movs	r0, #0
+ 148              	.LVL11:
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 149              		.loc 1 233 1 view .LVU42
+ 150 002a 04B0     		add	sp, sp, #16
+ 151              	.LCFI1:
+ 152              		.cfi_def_cfa_offset 0
+ 153 002c 7047     		bx	lr
+ 154              	.L10:
+ 155 002e 00BF     		.align	2
+ 156              	.L9:
+ 157 0030 0081FFFF 		.word	-32512
+ 158              		.cfi_endproc
+ 159              	.LFE141:
+ 161              		.section	.text.SDMMC_ReadFIFO,"ax",%progbits
+ 162              		.align	1
+ 163              		.global	SDMMC_ReadFIFO
+ 164              		.syntax unified
+ 165              		.thumb
+ 166              		.thumb_func
+ 167              		.fpu fpv5-d16
+ 169              	SDMMC_ReadFIFO:
+ 170              	.LVL12:
+ 171              	.LFB142:
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Read data from Rx FIFO */ 
+ 172              		.loc 1 261 1 is_stmt 1 view -0
+ 173              		.cfi_startproc
+ 174              		@ args = 0, pretend = 0, frame = 0
+ 175              		@ frame_needed = 0, uses_anonymous_args = 0
+ 176              		@ link register save eliminated.
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 177              		.loc 1 263 3 view .LVU44
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 178              		.loc 1 263 17 is_stmt 0 view .LVU45
+ 179 0000 D0F88000 		ldr	r0, [r0, #128]
+ 180              	.LVL13:
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ARM GAS  /tmp/ccODg7xx.s 			page 32
+
+
+ 181              		.loc 1 264 1 view .LVU46
+ 182 0004 7047     		bx	lr
+ 183              		.cfi_endproc
+ 184              	.LFE142:
+ 186              		.section	.text.SDMMC_WriteFIFO,"ax",%progbits
+ 187              		.align	1
+ 188              		.global	SDMMC_WriteFIFO
+ 189              		.syntax unified
+ 190              		.thumb
+ 191              		.thumb_func
+ 192              		.fpu fpv5-d16
+ 194              	SDMMC_WriteFIFO:
+ 195              	.LVL14:
+ 196              	.LFB143:
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Write data to FIFO */ 
+ 197              		.loc 1 273 1 is_stmt 1 view -0
+ 198              		.cfi_startproc
+ 199              		@ args = 0, pretend = 0, frame = 0
+ 200              		@ frame_needed = 0, uses_anonymous_args = 0
+ 201              		@ link register save eliminated.
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 202              		.loc 1 275 3 view .LVU48
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 203              		.loc 1 275 18 is_stmt 0 view .LVU49
+ 204 0000 0B68     		ldr	r3, [r1]
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 205              		.loc 1 275 16 view .LVU50
+ 206 0002 C0F88030 		str	r3, [r0, #128]
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 207              		.loc 1 277 3 is_stmt 1 view .LVU51
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 208              		.loc 1 278 1 is_stmt 0 view .LVU52
+ 209 0006 0020     		movs	r0, #0
+ 210              	.LVL15:
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 211              		.loc 1 278 1 view .LVU53
+ 212 0008 7047     		bx	lr
+ 213              		.cfi_endproc
+ 214              	.LFE143:
+ 216              		.section	.text.SDMMC_PowerState_ON,"ax",%progbits
+ 217              		.align	1
+ 218              		.global	SDMMC_PowerState_ON
+ 219              		.syntax unified
+ 220              		.thumb
+ 221              		.thumb_func
+ 222              		.fpu fpv5-d16
+ 224              	SDMMC_PowerState_ON:
+ 225              	.LVL16:
+ 226              	.LFB144:
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set power state to ON */ 
+ 227              		.loc 1 305 1 is_stmt 1 view -0
+ 228              		.cfi_startproc
+ 229              		@ args = 0, pretend = 0, frame = 0
+ 230              		@ frame_needed = 0, uses_anonymous_args = 0
+ 231              		@ link register save eliminated.
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 232              		.loc 1 307 3 view .LVU55
+ARM GAS  /tmp/ccODg7xx.s 			page 33
+
+
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 233              		.loc 1 307 17 is_stmt 0 view .LVU56
+ 234 0000 0323     		movs	r3, #3
+ 235 0002 0360     		str	r3, [r0]
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 236              		.loc 1 309 3 is_stmt 1 view .LVU57
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 237              		.loc 1 310 1 is_stmt 0 view .LVU58
+ 238 0004 0020     		movs	r0, #0
+ 239              	.LVL17:
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 240              		.loc 1 310 1 view .LVU59
+ 241 0006 7047     		bx	lr
+ 242              		.cfi_endproc
+ 243              	.LFE144:
+ 245              		.section	.text.SDMMC_PowerState_OFF,"ax",%progbits
+ 246              		.align	1
+ 247              		.global	SDMMC_PowerState_OFF
+ 248              		.syntax unified
+ 249              		.thumb
+ 250              		.thumb_func
+ 251              		.fpu fpv5-d16
+ 253              	SDMMC_PowerState_OFF:
+ 254              	.LVL18:
+ 255              	.LFB145:
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set power state to OFF */
+ 256              		.loc 1 318 1 is_stmt 1 view -0
+ 257              		.cfi_startproc
+ 258              		@ args = 0, pretend = 0, frame = 0
+ 259              		@ frame_needed = 0, uses_anonymous_args = 0
+ 260              		@ link register save eliminated.
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Set power state to OFF */
+ 261              		.loc 1 318 1 is_stmt 0 view .LVU61
+ 262 0000 0346     		mov	r3, r0
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 263              		.loc 1 320 3 is_stmt 1 view .LVU62
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 264              		.loc 1 320 17 is_stmt 0 view .LVU63
+ 265 0002 0020     		movs	r0, #0
+ 266              	.LVL19:
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 267              		.loc 1 320 17 view .LVU64
+ 268 0004 1860     		str	r0, [r3]
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 269              		.loc 1 322 3 is_stmt 1 view .LVU65
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 270              		.loc 1 323 1 is_stmt 0 view .LVU66
+ 271 0006 7047     		bx	lr
+ 272              		.cfi_endproc
+ 273              	.LFE145:
+ 275              		.section	.text.SDMMC_GetPowerState,"ax",%progbits
+ 276              		.align	1
+ 277              		.global	SDMMC_GetPowerState
+ 278              		.syntax unified
+ 279              		.thumb
+ 280              		.thumb_func
+ 281              		.fpu fpv5-d16
+ARM GAS  /tmp/ccODg7xx.s 			page 34
+
+
+ 283              	SDMMC_GetPowerState:
+ 284              	.LVL20:
+ 285              	.LFB146:
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
+ 286              		.loc 1 335 1 is_stmt 1 view -0
+ 287              		.cfi_startproc
+ 288              		@ args = 0, pretend = 0, frame = 0
+ 289              		@ frame_needed = 0, uses_anonymous_args = 0
+ 290              		@ link register save eliminated.
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 291              		.loc 1 336 3 view .LVU68
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 292              		.loc 1 336 17 is_stmt 0 view .LVU69
+ 293 0000 0068     		ldr	r0, [r0]
+ 294              	.LVL21:
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 295              		.loc 1 337 1 view .LVU70
+ 296 0002 00F00300 		and	r0, r0, #3
+ 297 0006 7047     		bx	lr
+ 298              		.cfi_endproc
+ 299              	.LFE146:
+ 301              		.section	.text.SDMMC_SendCommand,"ax",%progbits
+ 302              		.align	1
+ 303              		.global	SDMMC_SendCommand
+ 304              		.syntax unified
+ 305              		.thumb
+ 306              		.thumb_func
+ 307              		.fpu fpv5-d16
+ 309              	SDMMC_SendCommand:
+ 310              	.LVL22:
+ 311              	.LFB147:
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t tmpreg = 0;
+ 312              		.loc 1 348 1 is_stmt 1 view -0
+ 313              		.cfi_startproc
+ 314              		@ args = 0, pretend = 0, frame = 0
+ 315              		@ frame_needed = 0, uses_anonymous_args = 0
+ 316              		@ link register save eliminated.
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 317              		.loc 1 349 3 view .LVU72
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_RESPONSE(Command->Response));
+ 318              		.loc 1 352 3 view .LVU73
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
+ 319              		.loc 1 353 3 view .LVU74
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_CPSM(Command->CPSM));
+ 320              		.loc 1 354 3 view .LVU75
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 321              		.loc 1 355 3 view .LVU76
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 322              		.loc 1 358 3 view .LVU77
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 323              		.loc 1 358 24 is_stmt 0 view .LVU78
+ 324 0000 0B68     		ldr	r3, [r1]
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 325              		.loc 1 358 15 view .LVU79
+ 326 0002 8360     		str	r3, [r0, #8]
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Command->Response         |\
+ 327              		.loc 1 361 3 is_stmt 1 view .LVU80
+ARM GAS  /tmp/ccODg7xx.s 			page 35
+
+
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Command->Response         |\
+ 328              		.loc 1 361 31 is_stmt 0 view .LVU81
+ 329 0004 4B68     		ldr	r3, [r1, #4]
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Command->WaitForInterrupt |\
+ 330              		.loc 1 362 31 view .LVU82
+ 331 0006 8A68     		ldr	r2, [r1, #8]
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Command->Response         |\
+ 332              		.loc 1 361 50 view .LVU83
+ 333 0008 1343     		orrs	r3, r3, r2
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Command->CPSM);
+ 334              		.loc 1 363 31 view .LVU84
+ 335 000a CA68     		ldr	r2, [r1, #12]
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Command->WaitForInterrupt |\
+ 336              		.loc 1 362 50 view .LVU85
+ 337 000c 1343     		orrs	r3, r3, r2
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 338              		.loc 1 364 31 view .LVU86
+ 339 000e 0A69     		ldr	r2, [r1, #16]
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Command->CPSM);
+ 340              		.loc 1 363 50 view .LVU87
+ 341 0010 1343     		orrs	r3, r3, r2
+ 342              	.LVL23:
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 343              		.loc 1 367 3 is_stmt 1 view .LVU88
+ 344 0012 C168     		ldr	r1, [r0, #12]
+ 345              	.LVL24:
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 346              		.loc 1 367 3 is_stmt 0 view .LVU89
+ 347 0014 024A     		ldr	r2, .L17
+ 348 0016 0A40     		ands	r2, r2, r1
+ 349 0018 1343     		orrs	r3, r3, r2
+ 350              	.LVL25:
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 351              		.loc 1 367 3 view .LVU90
+ 352 001a C360     		str	r3, [r0, #12]
+ 353              	.LVL26:
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 354              		.loc 1 369 3 is_stmt 1 view .LVU91
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 355              		.loc 1 370 1 is_stmt 0 view .LVU92
+ 356 001c 0020     		movs	r0, #0
+ 357              	.LVL27:
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 358              		.loc 1 370 1 view .LVU93
+ 359 001e 7047     		bx	lr
+ 360              	.L18:
+ 361              		.align	2
+ 362              	.L17:
+ 363 0020 00F0FFFF 		.word	-4096
+ 364              		.cfi_endproc
+ 365              	.LFE147:
+ 367              		.section	.text.SDMMC_GetCommandResponse,"ax",%progbits
+ 368              		.align	1
+ 369              		.global	SDMMC_GetCommandResponse
+ 370              		.syntax unified
+ 371              		.thumb
+ 372              		.thumb_func
+ARM GAS  /tmp/ccODg7xx.s 			page 36
+
+
+ 373              		.fpu fpv5-d16
+ 375              	SDMMC_GetCommandResponse:
+ 376              	.LVL28:
+ 377              	.LFB148:
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return (uint8_t)(SDMMCx->RESPCMD);
+ 378              		.loc 1 378 1 is_stmt 1 view -0
+ 379              		.cfi_startproc
+ 380              		@ args = 0, pretend = 0, frame = 0
+ 381              		@ frame_needed = 0, uses_anonymous_args = 0
+ 382              		@ link register save eliminated.
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 383              		.loc 1 379 3 view .LVU95
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 384              		.loc 1 379 26 is_stmt 0 view .LVU96
+ 385 0000 0069     		ldr	r0, [r0, #16]
+ 386              	.LVL29:
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 387              		.loc 1 380 1 view .LVU97
+ 388 0002 C0B2     		uxtb	r0, r0
+ 389 0004 7047     		bx	lr
+ 390              		.cfi_endproc
+ 391              	.LFE148:
+ 393              		.section	.text.SDMMC_GetResponse,"ax",%progbits
+ 394              		.align	1
+ 395              		.global	SDMMC_GetResponse
+ 396              		.syntax unified
+ 397              		.thumb
+ 398              		.thumb_func
+ 399              		.fpu fpv5-d16
+ 401              	SDMMC_GetResponse:
+ 402              	.LVL30:
+ 403              	.LFB149:
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t tmp;
+ 404              		.loc 1 395 1 is_stmt 1 view -0
+ 405              		.cfi_startproc
+ 406              		@ args = 0, pretend = 0, frame = 0
+ 407              		@ frame_needed = 0, uses_anonymous_args = 0
+ 408              		@ link register save eliminated.
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 409              		.loc 1 396 3 view .LVU99
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 410              		.loc 1 399 3 view .LVU100
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 411              		.loc 1 402 3 view .LVU101
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 412              		.loc 1 402 20 is_stmt 0 view .LVU102
+ 413 0000 1430     		adds	r0, r0, #20
+ 414              	.LVL31:
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }  
+ 415              		.loc 1 404 3 is_stmt 1 view .LVU103
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }  
+ 416              		.loc 1 404 11 is_stmt 0 view .LVU104
+ 417 0002 4058     		ldr	r0, [r0, r1]
+ 418              	.LVL32:
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 419              		.loc 1 405 1 view .LVU105
+ 420 0004 7047     		bx	lr
+ARM GAS  /tmp/ccODg7xx.s 			page 37
+
+
+ 421              		.cfi_endproc
+ 422              	.LFE149:
+ 424              		.section	.text.SDMMC_ConfigData,"ax",%progbits
+ 425              		.align	1
+ 426              		.global	SDMMC_ConfigData
+ 427              		.syntax unified
+ 428              		.thumb
+ 429              		.thumb_func
+ 430              		.fpu fpv5-d16
+ 432              	SDMMC_ConfigData:
+ 433              	.LVL33:
+ 434              	.LFB150:
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t tmpreg = 0;
+ 435              		.loc 1 416 1 is_stmt 1 view -0
+ 436              		.cfi_startproc
+ 437              		@ args = 0, pretend = 0, frame = 0
+ 438              		@ frame_needed = 0, uses_anonymous_args = 0
+ 439              		@ link register save eliminated.
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 440              		.loc 1 417 3 view .LVU107
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
+ 441              		.loc 1 420 3 view .LVU108
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
+ 442              		.loc 1 421 3 view .LVU109
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
+ 443              		.loc 1 422 3 view .LVU110
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   assert_param(IS_SDMMC_DPSM(Data->DPSM));
+ 444              		.loc 1 423 3 view .LVU111
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 445              		.loc 1 424 3 view .LVU112
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 446              		.loc 1 427 3 view .LVU113
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 447              		.loc 1 427 24 is_stmt 0 view .LVU114
+ 448 0000 0B68     		ldr	r3, [r1]
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 449              		.loc 1 427 18 view .LVU115
+ 450 0002 4362     		str	r3, [r0, #36]
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 451              		.loc 1 430 3 is_stmt 1 view .LVU116
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 452              		.loc 1 430 22 is_stmt 0 view .LVU117
+ 453 0004 4B68     		ldr	r3, [r1, #4]
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 454              		.loc 1 430 16 view .LVU118
+ 455 0006 8362     		str	r3, [r0, #40]
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Data->TransferDir   |\
+ 456              		.loc 1 433 3 is_stmt 1 view .LVU119
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Data->TransferDir   |\
+ 457              		.loc 1 433 28 is_stmt 0 view .LVU120
+ 458 0008 8B68     		ldr	r3, [r1, #8]
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Data->TransferMode  |\
+ 459              		.loc 1 434 28 view .LVU121
+ 460 000a CA68     		ldr	r2, [r1, #12]
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Data->TransferDir   |\
+ 461              		.loc 1 433 44 view .LVU122
+ 462 000c 1343     		orrs	r3, r3, r2
+ARM GAS  /tmp/ccODg7xx.s 			page 38
+
+
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Data->DPSM);
+ 463              		.loc 1 435 28 view .LVU123
+ 464 000e 0A69     		ldr	r2, [r1, #16]
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Data->TransferMode  |\
+ 465              		.loc 1 434 44 view .LVU124
+ 466 0010 1343     		orrs	r3, r3, r2
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 467              		.loc 1 436 28 view .LVU125
+ 468 0012 4A69     		ldr	r2, [r1, #20]
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****                        Data->DPSM);
+ 469              		.loc 1 435 44 view .LVU126
+ 470 0014 1343     		orrs	r3, r3, r2
+ 471              	.LVL34:
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 472              		.loc 1 439 3 is_stmt 1 view .LVU127
+ 473 0016 C26A     		ldr	r2, [r0, #44]
+ 474 0018 22F0F702 		bic	r2, r2, #247
+ 475 001c 1343     		orrs	r3, r3, r2
+ 476              	.LVL35:
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 477              		.loc 1 439 3 is_stmt 0 view .LVU128
+ 478 001e C362     		str	r3, [r0, #44]
+ 479              	.LVL36:
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 480              		.loc 1 441 3 is_stmt 1 view .LVU129
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 481              		.loc 1 443 1 is_stmt 0 view .LVU130
+ 482 0020 0020     		movs	r0, #0
+ 483              	.LVL37:
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 484              		.loc 1 443 1 view .LVU131
+ 485 0022 7047     		bx	lr
+ 486              		.cfi_endproc
+ 487              	.LFE150:
+ 489              		.section	.text.SDMMC_GetDataCounter,"ax",%progbits
+ 490              		.align	1
+ 491              		.global	SDMMC_GetDataCounter
+ 492              		.syntax unified
+ 493              		.thumb
+ 494              		.thumb_func
+ 495              		.fpu fpv5-d16
+ 497              	SDMMC_GetDataCounter:
+ 498              	.LVL38:
+ 499              	.LFB151:
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return (SDMMCx->DCOUNT);
+ 500              		.loc 1 451 1 is_stmt 1 view -0
+ 501              		.cfi_startproc
+ 502              		@ args = 0, pretend = 0, frame = 0
+ 503              		@ frame_needed = 0, uses_anonymous_args = 0
+ 504              		@ link register save eliminated.
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 505              		.loc 1 452 3 view .LVU133
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 506              		.loc 1 452 17 is_stmt 0 view .LVU134
+ 507 0000 006B     		ldr	r0, [r0, #48]
+ 508              	.LVL39:
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ARM GAS  /tmp/ccODg7xx.s 			page 39
+
+
+ 509              		.loc 1 453 1 view .LVU135
+ 510 0002 7047     		bx	lr
+ 511              		.cfi_endproc
+ 512              	.LFE151:
+ 514              		.section	.text.SDMMC_GetFIFOCount,"ax",%progbits
+ 515              		.align	1
+ 516              		.global	SDMMC_GetFIFOCount
+ 517              		.syntax unified
+ 518              		.thumb
+ 519              		.thumb_func
+ 520              		.fpu fpv5-d16
+ 522              	SDMMC_GetFIFOCount:
+ 523              	.LVL40:
+ 524              	.LFB152:
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   return (SDMMCx->FIFO);
+ 525              		.loc 1 461 1 is_stmt 1 view -0
+ 526              		.cfi_startproc
+ 527              		@ args = 0, pretend = 0, frame = 0
+ 528              		@ frame_needed = 0, uses_anonymous_args = 0
+ 529              		@ link register save eliminated.
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 530              		.loc 1 462 3 view .LVU137
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 531              		.loc 1 462 17 is_stmt 0 view .LVU138
+ 532 0000 D0F88000 		ldr	r0, [r0, #128]
+ 533              	.LVL41:
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 534              		.loc 1 463 1 view .LVU139
+ 535 0004 7047     		bx	lr
+ 536              		.cfi_endproc
+ 537              	.LFE152:
+ 539              		.section	.text.SDMMC_SetSDMMCReadWaitMode,"ax",%progbits
+ 540              		.align	1
+ 541              		.global	SDMMC_SetSDMMCReadWaitMode
+ 542              		.syntax unified
+ 543              		.thumb
+ 544              		.thumb_func
+ 545              		.fpu fpv5-d16
+ 547              	SDMMC_SetSDMMCReadWaitMode:
+ 548              	.LVL42:
+ 549              	.LFB153:
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* Check the parameters */
+ 550              		.loc 1 475 1 is_stmt 1 view -0
+ 551              		.cfi_startproc
+ 552              		@ args = 0, pretend = 0, frame = 0
+ 553              		@ frame_needed = 0, uses_anonymous_args = 0
+ 554              		@ link register save eliminated.
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 555              		.loc 1 477 3 view .LVU141
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 556              		.loc 1 480 3 view .LVU142
+ 557 0000 C36A     		ldr	r3, [r0, #44]
+ 558 0002 23F48063 		bic	r3, r3, #1024
+ 559 0006 0B43     		orrs	r3, r3, r1
+ 560 0008 C362     		str	r3, [r0, #44]
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 561              		.loc 1 482 3 view .LVU143
+ARM GAS  /tmp/ccODg7xx.s 			page 40
+
+
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 562              		.loc 1 483 1 is_stmt 0 view .LVU144
+ 563 000a 0020     		movs	r0, #0
+ 564              	.LVL43:
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 565              		.loc 1 483 1 view .LVU145
+ 566 000c 7047     		bx	lr
+ 567              		.cfi_endproc
+ 568              	.LFE153:
+ 570              		.section	.text.SDMMC_CmdGoIdleState,"ax",%progbits
+ 571              		.align	1
+ 572              		.global	SDMMC_CmdGoIdleState
+ 573              		.syntax unified
+ 574              		.thumb
+ 575              		.thumb_func
+ 576              		.fpu fpv5-d16
+ 578              	SDMMC_CmdGoIdleState:
+ 579              	.LVL44:
+ 580              	.LFB166:
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 581              		.loc 1 799 1 is_stmt 1 view -0
+ 582              		.cfi_startproc
+ 583              		@ args = 0, pretend = 0, frame = 24
+ 584              		@ frame_needed = 0, uses_anonymous_args = 0
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 585              		.loc 1 799 1 is_stmt 0 view .LVU147
+ 586 0000 10B5     		push	{r4, lr}
+ 587              	.LCFI2:
+ 588              		.cfi_def_cfa_offset 8
+ 589              		.cfi_offset 4, -8
+ 590              		.cfi_offset 14, -4
+ 591 0002 86B0     		sub	sp, sp, #24
+ 592              	.LCFI3:
+ 593              		.cfi_def_cfa_offset 32
+ 594 0004 0446     		mov	r4, r0
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 595              		.loc 1 800 3 is_stmt 1 view .LVU148
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 596              		.loc 1 801 3 view .LVU149
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;
+ 597              		.loc 1 803 3 view .LVU150
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;
+ 598              		.loc 1 803 34 is_stmt 0 view .LVU151
+ 599 0006 0023     		movs	r3, #0
+ 600 0008 0193     		str	r3, [sp, #4]
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_NO;
+ 601              		.loc 1 804 3 is_stmt 1 view .LVU152
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_NO;
+ 602              		.loc 1 804 34 is_stmt 0 view .LVU153
+ 603 000a 0293     		str	r3, [sp, #8]
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 604              		.loc 1 805 3 is_stmt 1 view .LVU154
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 605              		.loc 1 805 34 is_stmt 0 view .LVU155
+ 606 000c 0393     		str	r3, [sp, #12]
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 607              		.loc 1 806 3 is_stmt 1 view .LVU156
+ARM GAS  /tmp/ccODg7xx.s 			page 41
+
+
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 608              		.loc 1 806 34 is_stmt 0 view .LVU157
+ 609 000e 0493     		str	r3, [sp, #16]
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 610              		.loc 1 807 3 is_stmt 1 view .LVU158
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 611              		.loc 1 807 34 is_stmt 0 view .LVU159
+ 612 0010 4FF48063 		mov	r3, #1024
+ 613 0014 0593     		str	r3, [sp, #20]
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 614              		.loc 1 808 3 is_stmt 1 view .LVU160
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 615              		.loc 1 808 9 is_stmt 0 view .LVU161
+ 616 0016 01A9     		add	r1, sp, #4
+ 617 0018 FFF7FEFF 		bl	SDMMC_SendCommand
+ 618              	.LVL45:
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 619              		.loc 1 811 3 is_stmt 1 view .LVU162
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 620              		.loc 1 811 16 is_stmt 0 view .LVU163
+ 621 001c 2046     		mov	r0, r4
+ 622 001e FFF7FEFF 		bl	SDMMC_GetCmdError
+ 623              	.LVL46:
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 624              		.loc 1 813 3 is_stmt 1 view .LVU164
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 625              		.loc 1 814 1 is_stmt 0 view .LVU165
+ 626 0022 06B0     		add	sp, sp, #24
+ 627              	.LCFI4:
+ 628              		.cfi_def_cfa_offset 8
+ 629              		@ sp needed
+ 630 0024 10BD     		pop	{r4, pc}
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 631              		.loc 1 814 1 view .LVU166
+ 632              		.cfi_endproc
+ 633              	.LFE166:
+ 635              		.section	.text.SDMMC_GetCmdResp1,"ax",%progbits
+ 636              		.align	1
+ 637              		.global	SDMMC_GetCmdResp1
+ 638              		.syntax unified
+ 639              		.thumb
+ 640              		.thumb_func
+ 641              		.fpu fpv5-d16
+ 643              	SDMMC_GetCmdResp1:
+ 644              	.LVL47:
+ 645              	.LFB181:
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t response_r1;
+ 646              		.loc 1 1192 1 is_stmt 1 view -0
+ 647              		.cfi_startproc
+ 648              		@ args = 0, pretend = 0, frame = 0
+ 649              		@ frame_needed = 0, uses_anonymous_args = 0
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t response_r1;
+ 650              		.loc 1 1192 1 is_stmt 0 view .LVU168
+ 651 0000 38B5     		push	{r3, r4, r5, lr}
+ 652              	.LCFI5:
+ 653              		.cfi_def_cfa_offset 16
+ 654              		.cfi_offset 3, -16
+ARM GAS  /tmp/ccODg7xx.s 			page 42
+
+
+ 655              		.cfi_offset 4, -12
+ 656              		.cfi_offset 5, -8
+ 657              		.cfi_offset 14, -4
+ 658 0002 0446     		mov	r4, r0
+ 659 0004 0D46     		mov	r5, r1
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+ 660              		.loc 1 1193 3 is_stmt 1 view .LVU169
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 661              		.loc 1 1194 3 view .LVU170
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 662              		.loc 1 1198 3 view .LVU171
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 663              		.loc 1 1198 52 is_stmt 0 view .LVU172
+ 664 0006 504B     		ldr	r3, .L55
+ 665 0008 1B68     		ldr	r3, [r3]
+ 666 000a 5049     		ldr	r1, .L55+4
+ 667              	.LVL48:
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 668              		.loc 1 1198 52 view .LVU173
+ 669 000c A1FB0313 		umull	r1, r3, r1, r3
+ 670 0010 5B0A     		lsrs	r3, r3, #9
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 671              		.loc 1 1198 12 view .LVU174
+ 672 0012 03FB02F2 		mul	r2, r3, r2
+ 673              	.LVL49:
+ 674              	.L29:
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 675              		.loc 1 1200 3 is_stmt 1 view .LVU175
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 676              		.loc 1 1202 5 view .LVU176
+ 677 0016 1346     		mov	r3, r2
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 678              		.loc 1 1202 14 is_stmt 0 view .LVU177
+ 679 0018 013A     		subs	r2, r2, #1
+ 680              	.LVL50:
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 681              		.loc 1 1202 8 view .LVU178
+ 682 001a 002B     		cmp	r3, #0
+ 683 001c 5DD0     		beq	.L32
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 684              		.loc 1 1206 5 is_stmt 1 view .LVU179
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 685              		.loc 1 1206 13 is_stmt 0 view .LVU180
+ 686 001e 636B     		ldr	r3, [r4, #52]
+ 687              	.LVL51:
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ 688              		.loc 1 1207 9 is_stmt 1 view .LVU181
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 689              		.loc 1 1208 10 is_stmt 0 view .LVU182
+ 690 0020 13F0450F 		tst	r3, #69
+ 691 0024 F7D0     		beq	.L29
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ 692              		.loc 1 1207 95 discriminator 1 view .LVU183
+ 693 0026 13F4006F 		tst	r3, #2048
+ 694 002a F4D1     		bne	.L29
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 695              		.loc 1 1210 3 is_stmt 1 view .LVU184
+ARM GAS  /tmp/ccODg7xx.s 			page 43
+
+
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 696              		.loc 1 1210 6 is_stmt 0 view .LVU185
+ 697 002c 636B     		ldr	r3, [r4, #52]
+ 698              	.LVL52:
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 699              		.loc 1 1210 5 view .LVU186
+ 700 002e 13F0040F 		tst	r3, #4
+ 701 0032 06D1     		bne	.L53
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 702              		.loc 1 1216 8 is_stmt 1 view .LVU187
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 703              		.loc 1 1216 11 is_stmt 0 view .LVU188
+ 704 0034 636B     		ldr	r3, [r4, #52]
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 705              		.loc 1 1216 10 view .LVU189
+ 706 0036 13F0010F 		tst	r3, #1
+ 707 003a 05D0     		beq	.L31
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 708              		.loc 1 1218 5 is_stmt 1 view .LVU190
+ 709 003c 0120     		movs	r0, #1
+ 710              	.LVL53:
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 711              		.loc 1 1218 5 is_stmt 0 view .LVU191
+ 712 003e A063     		str	r0, [r4, #56]
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 713              		.loc 1 1220 5 is_stmt 1 view .LVU192
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 714              		.loc 1 1220 12 is_stmt 0 view .LVU193
+ 715 0040 4DE0     		b	.L27
+ 716              	.LVL54:
+ 717              	.L53:
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 718              		.loc 1 1212 5 is_stmt 1 view .LVU194
+ 719 0042 0420     		movs	r0, #4
+ 720              	.LVL55:
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 721              		.loc 1 1212 5 is_stmt 0 view .LVU195
+ 722 0044 A063     		str	r0, [r4, #56]
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 723              		.loc 1 1214 5 is_stmt 1 view .LVU196
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 724              		.loc 1 1214 12 is_stmt 0 view .LVU197
+ 725 0046 4AE0     		b	.L27
+ 726              	.LVL56:
+ 727              	.L31:
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 728              		.loc 1 1225 3 is_stmt 1 view .LVU198
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 729              		.loc 1 1228 3 view .LVU199
+ 730 0048 C523     		movs	r3, #197
+ 731 004a A363     		str	r3, [r4, #56]
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 732              		.loc 1 1231 3 view .LVU200
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 733              		.loc 1 1231 6 is_stmt 0 view .LVU201
+ 734 004c 2046     		mov	r0, r4
+ 735              	.LVL57:
+ARM GAS  /tmp/ccODg7xx.s 			page 44
+
+
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 736              		.loc 1 1231 6 view .LVU202
+ 737 004e FFF7FEFF 		bl	SDMMC_GetCommandResponse
+ 738              	.LVL58:
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 739              		.loc 1 1231 5 view .LVU203
+ 740 0052 A842     		cmp	r0, r5
+ 741 0054 01D0     		beq	.L54
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 742              		.loc 1 1233 12 view .LVU204
+ 743 0056 0120     		movs	r0, #1
+ 744 0058 41E0     		b	.L27
+ 745              	.L54:
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 746              		.loc 1 1237 3 is_stmt 1 view .LVU205
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 747              		.loc 1 1237 17 is_stmt 0 view .LVU206
+ 748 005a 0021     		movs	r1, #0
+ 749 005c 2046     		mov	r0, r4
+ 750 005e FFF7FEFF 		bl	SDMMC_GetResponse
+ 751              	.LVL59:
+ 752 0062 0346     		mov	r3, r0
+ 753              	.LVL60:
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 754              		.loc 1 1239 3 is_stmt 1 view .LVU207
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 755              		.loc 1 1239 19 is_stmt 0 view .LVU208
+ 756 0064 3A48     		ldr	r0, .L55+8
+ 757              	.LVL61:
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 758              		.loc 1 1239 19 view .LVU209
+ 759 0066 1840     		ands	r0, r0, r3
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 760              		.loc 1 1239 5 view .LVU210
+ 761 0068 C8B3     		cbz	r0, .L27
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 762              		.loc 1 1243 8 is_stmt 1 view .LVU211
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 763              		.loc 1 1243 10 is_stmt 0 view .LVU212
+ 764 006a 002B     		cmp	r3, #0
+ 765 006c 38DB     		blt	.L34
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 766              		.loc 1 1247 8 is_stmt 1 view .LVU213
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 767              		.loc 1 1247 10 is_stmt 0 view .LVU214
+ 768 006e 13F0804F 		tst	r3, #1073741824
+ 769 0072 38D1     		bne	.L35
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 770              		.loc 1 1251 8 is_stmt 1 view .LVU215
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 771              		.loc 1 1251 10 is_stmt 0 view .LVU216
+ 772 0074 13F0005F 		tst	r3, #536870912
+ 773 0078 37D1     		bne	.L36
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 774              		.loc 1 1255 8 is_stmt 1 view .LVU217
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 775              		.loc 1 1255 10 is_stmt 0 view .LVU218
+ARM GAS  /tmp/ccODg7xx.s 			page 45
+
+
+ 776 007a 13F0805F 		tst	r3, #268435456
+ 777 007e 36D1     		bne	.L37
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 778              		.loc 1 1259 8 is_stmt 1 view .LVU219
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 779              		.loc 1 1259 10 is_stmt 0 view .LVU220
+ 780 0080 13F0006F 		tst	r3, #134217728
+ 781 0084 36D1     		bne	.L38
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 782              		.loc 1 1263 8 is_stmt 1 view .LVU221
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 783              		.loc 1 1263 10 is_stmt 0 view .LVU222
+ 784 0086 13F0806F 		tst	r3, #67108864
+ 785 008a 36D1     		bne	.L39
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 786              		.loc 1 1267 8 is_stmt 1 view .LVU223
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 787              		.loc 1 1267 10 is_stmt 0 view .LVU224
+ 788 008c 13F0807F 		tst	r3, #16777216
+ 789 0090 36D1     		bne	.L40
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 790              		.loc 1 1271 8 is_stmt 1 view .LVU225
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 791              		.loc 1 1271 10 is_stmt 0 view .LVU226
+ 792 0092 13F4000F 		tst	r3, #8388608
+ 793 0096 36D1     		bne	.L41
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 794              		.loc 1 1275 8 is_stmt 1 view .LVU227
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 795              		.loc 1 1275 10 is_stmt 0 view .LVU228
+ 796 0098 13F4800F 		tst	r3, #4194304
+ 797 009c 36D1     		bne	.L42
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 798              		.loc 1 1279 8 is_stmt 1 view .LVU229
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 799              		.loc 1 1279 10 is_stmt 0 view .LVU230
+ 800 009e 13F4001F 		tst	r3, #2097152
+ 801 00a2 36D1     		bne	.L43
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 802              		.loc 1 1283 8 is_stmt 1 view .LVU231
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 803              		.loc 1 1283 10 is_stmt 0 view .LVU232
+ 804 00a4 13F4801F 		tst	r3, #1048576
+ 805 00a8 36D1     		bne	.L44
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 806              		.loc 1 1287 8 is_stmt 1 view .LVU233
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 807              		.loc 1 1287 10 is_stmt 0 view .LVU234
+ 808 00aa 13F4802F 		tst	r3, #262144
+ 809 00ae 36D1     		bne	.L45
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 810              		.loc 1 1291 8 is_stmt 1 view .LVU235
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 811              		.loc 1 1291 10 is_stmt 0 view .LVU236
+ 812 00b0 13F4003F 		tst	r3, #131072
+ 813 00b4 36D1     		bne	.L46
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ARM GAS  /tmp/ccODg7xx.s 			page 46
+
+
+ 814              		.loc 1 1295 8 is_stmt 1 view .LVU237
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 815              		.loc 1 1295 10 is_stmt 0 view .LVU238
+ 816 00b6 13F4803F 		tst	r3, #65536
+ 817 00ba 36D1     		bne	.L47
+1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 818              		.loc 1 1299 8 is_stmt 1 view .LVU239
+1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 819              		.loc 1 1299 10 is_stmt 0 view .LVU240
+ 820 00bc 13F4004F 		tst	r3, #32768
+ 821 00c0 36D1     		bne	.L48
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 822              		.loc 1 1303 8 is_stmt 1 view .LVU241
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 823              		.loc 1 1303 10 is_stmt 0 view .LVU242
+ 824 00c2 13F4804F 		tst	r3, #16384
+ 825 00c6 36D1     		bne	.L49
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 826              		.loc 1 1307 8 is_stmt 1 view .LVU243
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 827              		.loc 1 1307 10 is_stmt 0 view .LVU244
+ 828 00c8 13F4005F 		tst	r3, #8192
+ 829 00cc 36D1     		bne	.L50
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 830              		.loc 1 1311 8 is_stmt 1 view .LVU245
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 831              		.loc 1 1311 10 is_stmt 0 view .LVU246
+ 832 00ce 13F0080F 		tst	r3, #8
+ 833 00d2 36D0     		beq	.L51
+1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 834              		.loc 1 1313 12 view .LVU247
+ 835 00d4 4FF40000 		mov	r0, #8388608
+ 836 00d8 01E0     		b	.L27
+ 837              	.LVL62:
+ 838              	.L32:
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+ 839              		.loc 1 1204 14 view .LVU248
+ 840 00da 4FF00040 		mov	r0, #-2147483648
+ 841              	.LVL63:
+ 842              	.L27:
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 843              		.loc 1 1319 1 view .LVU249
+ 844 00de 38BD     		pop	{r3, r4, r5, pc}
+ 845              	.LVL64:
+ 846              	.L34:
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 847              		.loc 1 1245 12 view .LVU250
+ 848 00e0 4FF00070 		mov	r0, #33554432
+ 849 00e4 FBE7     		b	.L27
+ 850              	.L35:
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 851              		.loc 1 1249 12 view .LVU251
+ 852 00e6 4020     		movs	r0, #64
+ 853 00e8 F9E7     		b	.L27
+ 854              	.L36:
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 855              		.loc 1 1253 12 view .LVU252
+ARM GAS  /tmp/ccODg7xx.s 			page 47
+
+
+ 856 00ea 8020     		movs	r0, #128
+ 857 00ec F7E7     		b	.L27
+ 858              	.L37:
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 859              		.loc 1 1257 12 view .LVU253
+ 860 00ee 4FF48070 		mov	r0, #256
+ 861 00f2 F4E7     		b	.L27
+ 862              	.L38:
+1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 863              		.loc 1 1261 12 view .LVU254
+ 864 00f4 4FF40070 		mov	r0, #512
+ 865 00f8 F1E7     		b	.L27
+ 866              	.L39:
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 867              		.loc 1 1265 12 view .LVU255
+ 868 00fa 4FF48060 		mov	r0, #1024
+ 869 00fe EEE7     		b	.L27
+ 870              	.L40:
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 871              		.loc 1 1269 12 view .LVU256
+ 872 0100 4FF40060 		mov	r0, #2048
+ 873 0104 EBE7     		b	.L27
+ 874              	.L41:
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 875              		.loc 1 1273 12 view .LVU257
+ 876 0106 4FF48050 		mov	r0, #4096
+ 877 010a E8E7     		b	.L27
+ 878              	.L42:
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 879              		.loc 1 1277 12 view .LVU258
+ 880 010c 4FF40050 		mov	r0, #8192
+ 881 0110 E5E7     		b	.L27
+ 882              	.L43:
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 883              		.loc 1 1281 12 view .LVU259
+ 884 0112 4FF48040 		mov	r0, #16384
+ 885 0116 E2E7     		b	.L27
+ 886              	.L44:
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 887              		.loc 1 1285 12 view .LVU260
+ 888 0118 4FF40040 		mov	r0, #32768
+ 889 011c DFE7     		b	.L27
+ 890              	.L45:
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 891              		.loc 1 1289 12 view .LVU261
+ 892 011e 4FF40030 		mov	r0, #131072
+ 893 0122 DCE7     		b	.L27
+ 894              	.L46:
+1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 895              		.loc 1 1293 12 view .LVU262
+ 896 0124 4FF48020 		mov	r0, #262144
+ 897 0128 D9E7     		b	.L27
+ 898              	.L47:
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 899              		.loc 1 1297 12 view .LVU263
+ 900 012a 4FF40020 		mov	r0, #524288
+ 901 012e D6E7     		b	.L27
+ARM GAS  /tmp/ccODg7xx.s 			page 48
+
+
+ 902              	.L48:
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 903              		.loc 1 1301 12 view .LVU264
+ 904 0130 4FF48010 		mov	r0, #1048576
+ 905 0134 D3E7     		b	.L27
+ 906              	.L49:
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 907              		.loc 1 1305 12 view .LVU265
+ 908 0136 4FF40010 		mov	r0, #2097152
+ 909 013a D0E7     		b	.L27
+ 910              	.L50:
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 911              		.loc 1 1309 12 view .LVU266
+ 912 013c 4FF48000 		mov	r0, #4194304
+ 913 0140 CDE7     		b	.L27
+ 914              	.L51:
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 915              		.loc 1 1317 12 view .LVU267
+ 916 0142 4FF48030 		mov	r0, #65536
+ 917 0146 CAE7     		b	.L27
+ 918              	.L56:
+ 919              		.align	2
+ 920              	.L55:
+ 921 0148 00000000 		.word	SystemCoreClock
+ 922 014c D34D6210 		.word	274877907
+ 923 0150 08E0FFFD 		.word	-33562616
+ 924              		.cfi_endproc
+ 925              	.LFE181:
+ 927              		.section	.text.SDMMC_CmdBlockLength,"ax",%progbits
+ 928              		.align	1
+ 929              		.global	SDMMC_CmdBlockLength
+ 930              		.syntax unified
+ 931              		.thumb
+ 932              		.thumb_func
+ 933              		.fpu fpv5-d16
+ 935              	SDMMC_CmdBlockLength:
+ 936              	.LVL65:
+ 937              	.LFB154:
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 938              		.loc 1 510 1 is_stmt 1 view -0
+ 939              		.cfi_startproc
+ 940              		@ args = 0, pretend = 0, frame = 24
+ 941              		@ frame_needed = 0, uses_anonymous_args = 0
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 942              		.loc 1 510 1 is_stmt 0 view .LVU269
+ 943 0000 30B5     		push	{r4, r5, lr}
+ 944              	.LCFI6:
+ 945              		.cfi_def_cfa_offset 12
+ 946              		.cfi_offset 4, -12
+ 947              		.cfi_offset 5, -8
+ 948              		.cfi_offset 14, -4
+ 949 0002 87B0     		sub	sp, sp, #28
+ 950              	.LCFI7:
+ 951              		.cfi_def_cfa_offset 40
+ 952 0004 0446     		mov	r4, r0
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 953              		.loc 1 511 3 is_stmt 1 view .LVU270
+ARM GAS  /tmp/ccODg7xx.s 			page 49
+
+
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 954              		.loc 1 512 3 view .LVU271
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;
+ 955              		.loc 1 515 3 view .LVU272
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;
+ 956              		.loc 1 515 34 is_stmt 0 view .LVU273
+ 957 0006 0191     		str	r1, [sp, #4]
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 958              		.loc 1 516 3 is_stmt 1 view .LVU274
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 959              		.loc 1 516 34 is_stmt 0 view .LVU275
+ 960 0008 1025     		movs	r5, #16
+ 961 000a 0295     		str	r5, [sp, #8]
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 962              		.loc 1 517 3 is_stmt 1 view .LVU276
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 963              		.loc 1 517 34 is_stmt 0 view .LVU277
+ 964 000c 4023     		movs	r3, #64
+ 965 000e 0393     		str	r3, [sp, #12]
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 966              		.loc 1 518 3 is_stmt 1 view .LVU278
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 967              		.loc 1 518 34 is_stmt 0 view .LVU279
+ 968 0010 0023     		movs	r3, #0
+ 969 0012 0493     		str	r3, [sp, #16]
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 970              		.loc 1 519 3 is_stmt 1 view .LVU280
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 971              		.loc 1 519 34 is_stmt 0 view .LVU281
+ 972 0014 4FF48063 		mov	r3, #1024
+ 973 0018 0593     		str	r3, [sp, #20]
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 974              		.loc 1 520 3 is_stmt 1 view .LVU282
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 975              		.loc 1 520 9 is_stmt 0 view .LVU283
+ 976 001a 01A9     		add	r1, sp, #4
+ 977              	.LVL66:
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 978              		.loc 1 520 9 view .LVU284
+ 979 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 980              	.LVL67:
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 981              		.loc 1 523 3 is_stmt 1 view .LVU285
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 982              		.loc 1 523 16 is_stmt 0 view .LVU286
+ 983 0020 41F28832 		movw	r2, #5000
+ 984 0024 2946     		mov	r1, r5
+ 985 0026 2046     		mov	r0, r4
+ 986 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 987              	.LVL68:
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 988              		.loc 1 525 3 is_stmt 1 view .LVU287
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 989              		.loc 1 526 1 is_stmt 0 view .LVU288
+ 990 002c 07B0     		add	sp, sp, #28
+ 991              	.LCFI8:
+ 992              		.cfi_def_cfa_offset 12
+ARM GAS  /tmp/ccODg7xx.s 			page 50
+
+
+ 993              		@ sp needed
+ 994 002e 30BD     		pop	{r4, r5, pc}
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 995              		.loc 1 526 1 view .LVU289
+ 996              		.cfi_endproc
+ 997              	.LFE154:
+ 999              		.section	.text.SDMMC_CmdReadSingleBlock,"ax",%progbits
+ 1000              		.align	1
+ 1001              		.global	SDMMC_CmdReadSingleBlock
+ 1002              		.syntax unified
+ 1003              		.thumb
+ 1004              		.thumb_func
+ 1005              		.fpu fpv5-d16
+ 1007              	SDMMC_CmdReadSingleBlock:
+ 1008              	.LVL69:
+ 1009              	.LFB155:
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1010              		.loc 1 534 1 is_stmt 1 view -0
+ 1011              		.cfi_startproc
+ 1012              		@ args = 0, pretend = 0, frame = 24
+ 1013              		@ frame_needed = 0, uses_anonymous_args = 0
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1014              		.loc 1 534 1 is_stmt 0 view .LVU291
+ 1015 0000 30B5     		push	{r4, r5, lr}
+ 1016              	.LCFI9:
+ 1017              		.cfi_def_cfa_offset 12
+ 1018              		.cfi_offset 4, -12
+ 1019              		.cfi_offset 5, -8
+ 1020              		.cfi_offset 14, -4
+ 1021 0002 87B0     		sub	sp, sp, #28
+ 1022              	.LCFI10:
+ 1023              		.cfi_def_cfa_offset 40
+ 1024 0004 0446     		mov	r4, r0
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1025              		.loc 1 535 3 is_stmt 1 view .LVU292
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1026              		.loc 1 536 3 view .LVU293
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;
+ 1027              		.loc 1 539 3 view .LVU294
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;
+ 1028              		.loc 1 539 34 is_stmt 0 view .LVU295
+ 1029 0006 0191     		str	r1, [sp, #4]
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1030              		.loc 1 540 3 is_stmt 1 view .LVU296
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1031              		.loc 1 540 34 is_stmt 0 view .LVU297
+ 1032 0008 1125     		movs	r5, #17
+ 1033 000a 0295     		str	r5, [sp, #8]
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1034              		.loc 1 541 3 is_stmt 1 view .LVU298
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1035              		.loc 1 541 34 is_stmt 0 view .LVU299
+ 1036 000c 4023     		movs	r3, #64
+ 1037 000e 0393     		str	r3, [sp, #12]
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1038              		.loc 1 542 3 is_stmt 1 view .LVU300
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ARM GAS  /tmp/ccODg7xx.s 			page 51
+
+
+ 1039              		.loc 1 542 34 is_stmt 0 view .LVU301
+ 1040 0010 0023     		movs	r3, #0
+ 1041 0012 0493     		str	r3, [sp, #16]
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1042              		.loc 1 543 3 is_stmt 1 view .LVU302
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1043              		.loc 1 543 34 is_stmt 0 view .LVU303
+ 1044 0014 4FF48063 		mov	r3, #1024
+ 1045 0018 0593     		str	r3, [sp, #20]
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1046              		.loc 1 544 3 is_stmt 1 view .LVU304
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1047              		.loc 1 544 9 is_stmt 0 view .LVU305
+ 1048 001a 01A9     		add	r1, sp, #4
+ 1049              	.LVL70:
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1050              		.loc 1 544 9 view .LVU306
+ 1051 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1052              	.LVL71:
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1053              		.loc 1 547 3 is_stmt 1 view .LVU307
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1054              		.loc 1 547 16 is_stmt 0 view .LVU308
+ 1055 0020 41F28832 		movw	r2, #5000
+ 1056 0024 2946     		mov	r1, r5
+ 1057 0026 2046     		mov	r0, r4
+ 1058 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1059              	.LVL72:
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1060              		.loc 1 549 3 is_stmt 1 view .LVU309
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1061              		.loc 1 550 1 is_stmt 0 view .LVU310
+ 1062 002c 07B0     		add	sp, sp, #28
+ 1063              	.LCFI11:
+ 1064              		.cfi_def_cfa_offset 12
+ 1065              		@ sp needed
+ 1066 002e 30BD     		pop	{r4, r5, pc}
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1067              		.loc 1 550 1 view .LVU311
+ 1068              		.cfi_endproc
+ 1069              	.LFE155:
+ 1071              		.section	.text.SDMMC_CmdReadMultiBlock,"ax",%progbits
+ 1072              		.align	1
+ 1073              		.global	SDMMC_CmdReadMultiBlock
+ 1074              		.syntax unified
+ 1075              		.thumb
+ 1076              		.thumb_func
+ 1077              		.fpu fpv5-d16
+ 1079              	SDMMC_CmdReadMultiBlock:
+ 1080              	.LVL73:
+ 1081              	.LFB156:
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1082              		.loc 1 558 1 is_stmt 1 view -0
+ 1083              		.cfi_startproc
+ 1084              		@ args = 0, pretend = 0, frame = 24
+ 1085              		@ frame_needed = 0, uses_anonymous_args = 0
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ARM GAS  /tmp/ccODg7xx.s 			page 52
+
+
+ 1086              		.loc 1 558 1 is_stmt 0 view .LVU313
+ 1087 0000 30B5     		push	{r4, r5, lr}
+ 1088              	.LCFI12:
+ 1089              		.cfi_def_cfa_offset 12
+ 1090              		.cfi_offset 4, -12
+ 1091              		.cfi_offset 5, -8
+ 1092              		.cfi_offset 14, -4
+ 1093 0002 87B0     		sub	sp, sp, #28
+ 1094              	.LCFI13:
+ 1095              		.cfi_def_cfa_offset 40
+ 1096 0004 0446     		mov	r4, r0
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1097              		.loc 1 559 3 is_stmt 1 view .LVU314
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1098              		.loc 1 560 3 view .LVU315
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;
+ 1099              		.loc 1 563 3 view .LVU316
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;
+ 1100              		.loc 1 563 34 is_stmt 0 view .LVU317
+ 1101 0006 0191     		str	r1, [sp, #4]
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1102              		.loc 1 564 3 is_stmt 1 view .LVU318
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1103              		.loc 1 564 34 is_stmt 0 view .LVU319
+ 1104 0008 1225     		movs	r5, #18
+ 1105 000a 0295     		str	r5, [sp, #8]
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1106              		.loc 1 565 3 is_stmt 1 view .LVU320
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1107              		.loc 1 565 34 is_stmt 0 view .LVU321
+ 1108 000c 4023     		movs	r3, #64
+ 1109 000e 0393     		str	r3, [sp, #12]
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1110              		.loc 1 566 3 is_stmt 1 view .LVU322
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1111              		.loc 1 566 34 is_stmt 0 view .LVU323
+ 1112 0010 0023     		movs	r3, #0
+ 1113 0012 0493     		str	r3, [sp, #16]
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1114              		.loc 1 567 3 is_stmt 1 view .LVU324
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1115              		.loc 1 567 34 is_stmt 0 view .LVU325
+ 1116 0014 4FF48063 		mov	r3, #1024
+ 1117 0018 0593     		str	r3, [sp, #20]
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1118              		.loc 1 568 3 is_stmt 1 view .LVU326
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1119              		.loc 1 568 9 is_stmt 0 view .LVU327
+ 1120 001a 01A9     		add	r1, sp, #4
+ 1121              	.LVL74:
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1122              		.loc 1 568 9 view .LVU328
+ 1123 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1124              	.LVL75:
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1125              		.loc 1 571 3 is_stmt 1 view .LVU329
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ARM GAS  /tmp/ccODg7xx.s 			page 53
+
+
+ 1126              		.loc 1 571 16 is_stmt 0 view .LVU330
+ 1127 0020 41F28832 		movw	r2, #5000
+ 1128 0024 2946     		mov	r1, r5
+ 1129 0026 2046     		mov	r0, r4
+ 1130 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1131              	.LVL76:
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1132              		.loc 1 573 3 is_stmt 1 view .LVU331
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1133              		.loc 1 574 1 is_stmt 0 view .LVU332
+ 1134 002c 07B0     		add	sp, sp, #28
+ 1135              	.LCFI14:
+ 1136              		.cfi_def_cfa_offset 12
+ 1137              		@ sp needed
+ 1138 002e 30BD     		pop	{r4, r5, pc}
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1139              		.loc 1 574 1 view .LVU333
+ 1140              		.cfi_endproc
+ 1141              	.LFE156:
+ 1143              		.section	.text.SDMMC_CmdWriteSingleBlock,"ax",%progbits
+ 1144              		.align	1
+ 1145              		.global	SDMMC_CmdWriteSingleBlock
+ 1146              		.syntax unified
+ 1147              		.thumb
+ 1148              		.thumb_func
+ 1149              		.fpu fpv5-d16
+ 1151              	SDMMC_CmdWriteSingleBlock:
+ 1152              	.LVL77:
+ 1153              	.LFB157:
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1154              		.loc 1 582 1 is_stmt 1 view -0
+ 1155              		.cfi_startproc
+ 1156              		@ args = 0, pretend = 0, frame = 24
+ 1157              		@ frame_needed = 0, uses_anonymous_args = 0
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1158              		.loc 1 582 1 is_stmt 0 view .LVU335
+ 1159 0000 30B5     		push	{r4, r5, lr}
+ 1160              	.LCFI15:
+ 1161              		.cfi_def_cfa_offset 12
+ 1162              		.cfi_offset 4, -12
+ 1163              		.cfi_offset 5, -8
+ 1164              		.cfi_offset 14, -4
+ 1165 0002 87B0     		sub	sp, sp, #28
+ 1166              	.LCFI16:
+ 1167              		.cfi_def_cfa_offset 40
+ 1168 0004 0446     		mov	r4, r0
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1169              		.loc 1 583 3 is_stmt 1 view .LVU336
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1170              		.loc 1 584 3 view .LVU337
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+ 1171              		.loc 1 587 3 view .LVU338
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+ 1172              		.loc 1 587 34 is_stmt 0 view .LVU339
+ 1173 0006 0191     		str	r1, [sp, #4]
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1174              		.loc 1 588 3 is_stmt 1 view .LVU340
+ARM GAS  /tmp/ccODg7xx.s 			page 54
+
+
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1175              		.loc 1 588 34 is_stmt 0 view .LVU341
+ 1176 0008 1825     		movs	r5, #24
+ 1177 000a 0295     		str	r5, [sp, #8]
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1178              		.loc 1 589 3 is_stmt 1 view .LVU342
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1179              		.loc 1 589 34 is_stmt 0 view .LVU343
+ 1180 000c 4023     		movs	r3, #64
+ 1181 000e 0393     		str	r3, [sp, #12]
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1182              		.loc 1 590 3 is_stmt 1 view .LVU344
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1183              		.loc 1 590 34 is_stmt 0 view .LVU345
+ 1184 0010 0023     		movs	r3, #0
+ 1185 0012 0493     		str	r3, [sp, #16]
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1186              		.loc 1 591 3 is_stmt 1 view .LVU346
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1187              		.loc 1 591 34 is_stmt 0 view .LVU347
+ 1188 0014 4FF48063 		mov	r3, #1024
+ 1189 0018 0593     		str	r3, [sp, #20]
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1190              		.loc 1 592 3 is_stmt 1 view .LVU348
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1191              		.loc 1 592 9 is_stmt 0 view .LVU349
+ 1192 001a 01A9     		add	r1, sp, #4
+ 1193              	.LVL78:
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1194              		.loc 1 592 9 view .LVU350
+ 1195 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1196              	.LVL79:
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1197              		.loc 1 595 3 is_stmt 1 view .LVU351
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1198              		.loc 1 595 16 is_stmt 0 view .LVU352
+ 1199 0020 41F28832 		movw	r2, #5000
+ 1200 0024 2946     		mov	r1, r5
+ 1201 0026 2046     		mov	r0, r4
+ 1202 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1203              	.LVL80:
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1204              		.loc 1 597 3 is_stmt 1 view .LVU353
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1205              		.loc 1 598 1 is_stmt 0 view .LVU354
+ 1206 002c 07B0     		add	sp, sp, #28
+ 1207              	.LCFI17:
+ 1208              		.cfi_def_cfa_offset 12
+ 1209              		@ sp needed
+ 1210 002e 30BD     		pop	{r4, r5, pc}
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1211              		.loc 1 598 1 view .LVU355
+ 1212              		.cfi_endproc
+ 1213              	.LFE157:
+ 1215              		.section	.text.SDMMC_CmdWriteMultiBlock,"ax",%progbits
+ 1216              		.align	1
+ 1217              		.global	SDMMC_CmdWriteMultiBlock
+ARM GAS  /tmp/ccODg7xx.s 			page 55
+
+
+ 1218              		.syntax unified
+ 1219              		.thumb
+ 1220              		.thumb_func
+ 1221              		.fpu fpv5-d16
+ 1223              	SDMMC_CmdWriteMultiBlock:
+ 1224              	.LVL81:
+ 1225              	.LFB158:
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1226              		.loc 1 606 1 is_stmt 1 view -0
+ 1227              		.cfi_startproc
+ 1228              		@ args = 0, pretend = 0, frame = 24
+ 1229              		@ frame_needed = 0, uses_anonymous_args = 0
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1230              		.loc 1 606 1 is_stmt 0 view .LVU357
+ 1231 0000 30B5     		push	{r4, r5, lr}
+ 1232              	.LCFI18:
+ 1233              		.cfi_def_cfa_offset 12
+ 1234              		.cfi_offset 4, -12
+ 1235              		.cfi_offset 5, -8
+ 1236              		.cfi_offset 14, -4
+ 1237 0002 87B0     		sub	sp, sp, #28
+ 1238              	.LCFI19:
+ 1239              		.cfi_def_cfa_offset 40
+ 1240 0004 0446     		mov	r4, r0
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1241              		.loc 1 607 3 is_stmt 1 view .LVU358
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1242              		.loc 1 608 3 view .LVU359
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;
+ 1243              		.loc 1 611 3 view .LVU360
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;
+ 1244              		.loc 1 611 34 is_stmt 0 view .LVU361
+ 1245 0006 0191     		str	r1, [sp, #4]
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1246              		.loc 1 612 3 is_stmt 1 view .LVU362
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1247              		.loc 1 612 34 is_stmt 0 view .LVU363
+ 1248 0008 1925     		movs	r5, #25
+ 1249 000a 0295     		str	r5, [sp, #8]
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1250              		.loc 1 613 3 is_stmt 1 view .LVU364
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1251              		.loc 1 613 34 is_stmt 0 view .LVU365
+ 1252 000c 4023     		movs	r3, #64
+ 1253 000e 0393     		str	r3, [sp, #12]
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1254              		.loc 1 614 3 is_stmt 1 view .LVU366
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1255              		.loc 1 614 34 is_stmt 0 view .LVU367
+ 1256 0010 0023     		movs	r3, #0
+ 1257 0012 0493     		str	r3, [sp, #16]
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1258              		.loc 1 615 3 is_stmt 1 view .LVU368
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1259              		.loc 1 615 34 is_stmt 0 view .LVU369
+ 1260 0014 4FF48063 		mov	r3, #1024
+ 1261 0018 0593     		str	r3, [sp, #20]
+ARM GAS  /tmp/ccODg7xx.s 			page 56
+
+
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1262              		.loc 1 616 3 is_stmt 1 view .LVU370
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1263              		.loc 1 616 9 is_stmt 0 view .LVU371
+ 1264 001a 01A9     		add	r1, sp, #4
+ 1265              	.LVL82:
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1266              		.loc 1 616 9 view .LVU372
+ 1267 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1268              	.LVL83:
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1269              		.loc 1 619 3 is_stmt 1 view .LVU373
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1270              		.loc 1 619 16 is_stmt 0 view .LVU374
+ 1271 0020 41F28832 		movw	r2, #5000
+ 1272 0024 2946     		mov	r1, r5
+ 1273 0026 2046     		mov	r0, r4
+ 1274 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1275              	.LVL84:
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1276              		.loc 1 621 3 is_stmt 1 view .LVU375
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1277              		.loc 1 622 1 is_stmt 0 view .LVU376
+ 1278 002c 07B0     		add	sp, sp, #28
+ 1279              	.LCFI20:
+ 1280              		.cfi_def_cfa_offset 12
+ 1281              		@ sp needed
+ 1282 002e 30BD     		pop	{r4, r5, pc}
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1283              		.loc 1 622 1 view .LVU377
+ 1284              		.cfi_endproc
+ 1285              	.LFE158:
+ 1287              		.section	.text.SDMMC_CmdSDEraseStartAdd,"ax",%progbits
+ 1288              		.align	1
+ 1289              		.global	SDMMC_CmdSDEraseStartAdd
+ 1290              		.syntax unified
+ 1291              		.thumb
+ 1292              		.thumb_func
+ 1293              		.fpu fpv5-d16
+ 1295              	SDMMC_CmdSDEraseStartAdd:
+ 1296              	.LVL85:
+ 1297              	.LFB159:
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1298              		.loc 1 630 1 is_stmt 1 view -0
+ 1299              		.cfi_startproc
+ 1300              		@ args = 0, pretend = 0, frame = 24
+ 1301              		@ frame_needed = 0, uses_anonymous_args = 0
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1302              		.loc 1 630 1 is_stmt 0 view .LVU379
+ 1303 0000 30B5     		push	{r4, r5, lr}
+ 1304              	.LCFI21:
+ 1305              		.cfi_def_cfa_offset 12
+ 1306              		.cfi_offset 4, -12
+ 1307              		.cfi_offset 5, -8
+ 1308              		.cfi_offset 14, -4
+ 1309 0002 87B0     		sub	sp, sp, #28
+ 1310              	.LCFI22:
+ARM GAS  /tmp/ccODg7xx.s 			page 57
+
+
+ 1311              		.cfi_def_cfa_offset 40
+ 1312 0004 0446     		mov	r4, r0
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1313              		.loc 1 631 3 is_stmt 1 view .LVU380
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1314              		.loc 1 632 3 view .LVU381
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;
+ 1315              		.loc 1 635 3 view .LVU382
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;
+ 1316              		.loc 1 635 34 is_stmt 0 view .LVU383
+ 1317 0006 0191     		str	r1, [sp, #4]
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1318              		.loc 1 636 3 is_stmt 1 view .LVU384
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1319              		.loc 1 636 34 is_stmt 0 view .LVU385
+ 1320 0008 2025     		movs	r5, #32
+ 1321 000a 0295     		str	r5, [sp, #8]
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1322              		.loc 1 637 3 is_stmt 1 view .LVU386
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1323              		.loc 1 637 34 is_stmt 0 view .LVU387
+ 1324 000c 4023     		movs	r3, #64
+ 1325 000e 0393     		str	r3, [sp, #12]
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1326              		.loc 1 638 3 is_stmt 1 view .LVU388
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1327              		.loc 1 638 34 is_stmt 0 view .LVU389
+ 1328 0010 0023     		movs	r3, #0
+ 1329 0012 0493     		str	r3, [sp, #16]
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1330              		.loc 1 639 3 is_stmt 1 view .LVU390
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1331              		.loc 1 639 34 is_stmt 0 view .LVU391
+ 1332 0014 4FF48063 		mov	r3, #1024
+ 1333 0018 0593     		str	r3, [sp, #20]
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1334              		.loc 1 640 3 is_stmt 1 view .LVU392
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1335              		.loc 1 640 9 is_stmt 0 view .LVU393
+ 1336 001a 01A9     		add	r1, sp, #4
+ 1337              	.LVL86:
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1338              		.loc 1 640 9 view .LVU394
+ 1339 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1340              	.LVL87:
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1341              		.loc 1 643 3 is_stmt 1 view .LVU395
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1342              		.loc 1 643 16 is_stmt 0 view .LVU396
+ 1343 0020 41F28832 		movw	r2, #5000
+ 1344 0024 2946     		mov	r1, r5
+ 1345 0026 2046     		mov	r0, r4
+ 1346 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1347              	.LVL88:
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1348              		.loc 1 645 3 is_stmt 1 view .LVU397
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ARM GAS  /tmp/ccODg7xx.s 			page 58
+
+
+ 1349              		.loc 1 646 1 is_stmt 0 view .LVU398
+ 1350 002c 07B0     		add	sp, sp, #28
+ 1351              	.LCFI23:
+ 1352              		.cfi_def_cfa_offset 12
+ 1353              		@ sp needed
+ 1354 002e 30BD     		pop	{r4, r5, pc}
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1355              		.loc 1 646 1 view .LVU399
+ 1356              		.cfi_endproc
+ 1357              	.LFE159:
+ 1359              		.section	.text.SDMMC_CmdSDEraseEndAdd,"ax",%progbits
+ 1360              		.align	1
+ 1361              		.global	SDMMC_CmdSDEraseEndAdd
+ 1362              		.syntax unified
+ 1363              		.thumb
+ 1364              		.thumb_func
+ 1365              		.fpu fpv5-d16
+ 1367              	SDMMC_CmdSDEraseEndAdd:
+ 1368              	.LVL89:
+ 1369              	.LFB160:
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1370              		.loc 1 654 1 is_stmt 1 view -0
+ 1371              		.cfi_startproc
+ 1372              		@ args = 0, pretend = 0, frame = 24
+ 1373              		@ frame_needed = 0, uses_anonymous_args = 0
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1374              		.loc 1 654 1 is_stmt 0 view .LVU401
+ 1375 0000 30B5     		push	{r4, r5, lr}
+ 1376              	.LCFI24:
+ 1377              		.cfi_def_cfa_offset 12
+ 1378              		.cfi_offset 4, -12
+ 1379              		.cfi_offset 5, -8
+ 1380              		.cfi_offset 14, -4
+ 1381 0002 87B0     		sub	sp, sp, #28
+ 1382              	.LCFI25:
+ 1383              		.cfi_def_cfa_offset 40
+ 1384 0004 0446     		mov	r4, r0
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1385              		.loc 1 655 3 is_stmt 1 view .LVU402
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1386              		.loc 1 656 3 view .LVU403
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;
+ 1387              		.loc 1 659 3 view .LVU404
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;
+ 1388              		.loc 1 659 34 is_stmt 0 view .LVU405
+ 1389 0006 0191     		str	r1, [sp, #4]
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1390              		.loc 1 660 3 is_stmt 1 view .LVU406
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1391              		.loc 1 660 34 is_stmt 0 view .LVU407
+ 1392 0008 2125     		movs	r5, #33
+ 1393 000a 0295     		str	r5, [sp, #8]
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1394              		.loc 1 661 3 is_stmt 1 view .LVU408
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1395              		.loc 1 661 34 is_stmt 0 view .LVU409
+ 1396 000c 4023     		movs	r3, #64
+ARM GAS  /tmp/ccODg7xx.s 			page 59
+
+
+ 1397 000e 0393     		str	r3, [sp, #12]
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1398              		.loc 1 662 3 is_stmt 1 view .LVU410
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1399              		.loc 1 662 34 is_stmt 0 view .LVU411
+ 1400 0010 0023     		movs	r3, #0
+ 1401 0012 0493     		str	r3, [sp, #16]
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1402              		.loc 1 663 3 is_stmt 1 view .LVU412
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1403              		.loc 1 663 34 is_stmt 0 view .LVU413
+ 1404 0014 4FF48063 		mov	r3, #1024
+ 1405 0018 0593     		str	r3, [sp, #20]
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1406              		.loc 1 664 3 is_stmt 1 view .LVU414
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1407              		.loc 1 664 9 is_stmt 0 view .LVU415
+ 1408 001a 01A9     		add	r1, sp, #4
+ 1409              	.LVL90:
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1410              		.loc 1 664 9 view .LVU416
+ 1411 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1412              	.LVL91:
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1413              		.loc 1 667 3 is_stmt 1 view .LVU417
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1414              		.loc 1 667 16 is_stmt 0 view .LVU418
+ 1415 0020 41F28832 		movw	r2, #5000
+ 1416 0024 2946     		mov	r1, r5
+ 1417 0026 2046     		mov	r0, r4
+ 1418 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1419              	.LVL92:
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1420              		.loc 1 669 3 is_stmt 1 view .LVU419
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1421              		.loc 1 670 1 is_stmt 0 view .LVU420
+ 1422 002c 07B0     		add	sp, sp, #28
+ 1423              	.LCFI26:
+ 1424              		.cfi_def_cfa_offset 12
+ 1425              		@ sp needed
+ 1426 002e 30BD     		pop	{r4, r5, pc}
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1427              		.loc 1 670 1 view .LVU421
+ 1428              		.cfi_endproc
+ 1429              	.LFE160:
+ 1431              		.section	.text.SDMMC_CmdEraseStartAdd,"ax",%progbits
+ 1432              		.align	1
+ 1433              		.global	SDMMC_CmdEraseStartAdd
+ 1434              		.syntax unified
+ 1435              		.thumb
+ 1436              		.thumb_func
+ 1437              		.fpu fpv5-d16
+ 1439              	SDMMC_CmdEraseStartAdd:
+ 1440              	.LVL93:
+ 1441              	.LFB161:
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1442              		.loc 1 678 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccODg7xx.s 			page 60
+
+
+ 1443              		.cfi_startproc
+ 1444              		@ args = 0, pretend = 0, frame = 24
+ 1445              		@ frame_needed = 0, uses_anonymous_args = 0
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1446              		.loc 1 678 1 is_stmt 0 view .LVU423
+ 1447 0000 30B5     		push	{r4, r5, lr}
+ 1448              	.LCFI27:
+ 1449              		.cfi_def_cfa_offset 12
+ 1450              		.cfi_offset 4, -12
+ 1451              		.cfi_offset 5, -8
+ 1452              		.cfi_offset 14, -4
+ 1453 0002 87B0     		sub	sp, sp, #28
+ 1454              	.LCFI28:
+ 1455              		.cfi_def_cfa_offset 40
+ 1456 0004 0446     		mov	r4, r0
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1457              		.loc 1 679 3 is_stmt 1 view .LVU424
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1458              		.loc 1 680 3 view .LVU425
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;
+ 1459              		.loc 1 683 3 view .LVU426
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;
+ 1460              		.loc 1 683 34 is_stmt 0 view .LVU427
+ 1461 0006 0191     		str	r1, [sp, #4]
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1462              		.loc 1 684 3 is_stmt 1 view .LVU428
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1463              		.loc 1 684 34 is_stmt 0 view .LVU429
+ 1464 0008 2325     		movs	r5, #35
+ 1465 000a 0295     		str	r5, [sp, #8]
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1466              		.loc 1 685 3 is_stmt 1 view .LVU430
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1467              		.loc 1 685 34 is_stmt 0 view .LVU431
+ 1468 000c 4023     		movs	r3, #64
+ 1469 000e 0393     		str	r3, [sp, #12]
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1470              		.loc 1 686 3 is_stmt 1 view .LVU432
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1471              		.loc 1 686 34 is_stmt 0 view .LVU433
+ 1472 0010 0023     		movs	r3, #0
+ 1473 0012 0493     		str	r3, [sp, #16]
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1474              		.loc 1 687 3 is_stmt 1 view .LVU434
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1475              		.loc 1 687 34 is_stmt 0 view .LVU435
+ 1476 0014 4FF48063 		mov	r3, #1024
+ 1477 0018 0593     		str	r3, [sp, #20]
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1478              		.loc 1 688 3 is_stmt 1 view .LVU436
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1479              		.loc 1 688 9 is_stmt 0 view .LVU437
+ 1480 001a 01A9     		add	r1, sp, #4
+ 1481              	.LVL94:
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1482              		.loc 1 688 9 view .LVU438
+ 1483 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ARM GAS  /tmp/ccODg7xx.s 			page 61
+
+
+ 1484              	.LVL95:
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1485              		.loc 1 691 3 is_stmt 1 view .LVU439
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1486              		.loc 1 691 16 is_stmt 0 view .LVU440
+ 1487 0020 41F28832 		movw	r2, #5000
+ 1488 0024 2946     		mov	r1, r5
+ 1489 0026 2046     		mov	r0, r4
+ 1490 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1491              	.LVL96:
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1492              		.loc 1 693 3 is_stmt 1 view .LVU441
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1493              		.loc 1 694 1 is_stmt 0 view .LVU442
+ 1494 002c 07B0     		add	sp, sp, #28
+ 1495              	.LCFI29:
+ 1496              		.cfi_def_cfa_offset 12
+ 1497              		@ sp needed
+ 1498 002e 30BD     		pop	{r4, r5, pc}
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1499              		.loc 1 694 1 view .LVU443
+ 1500              		.cfi_endproc
+ 1501              	.LFE161:
+ 1503              		.section	.text.SDMMC_CmdEraseEndAdd,"ax",%progbits
+ 1504              		.align	1
+ 1505              		.global	SDMMC_CmdEraseEndAdd
+ 1506              		.syntax unified
+ 1507              		.thumb
+ 1508              		.thumb_func
+ 1509              		.fpu fpv5-d16
+ 1511              	SDMMC_CmdEraseEndAdd:
+ 1512              	.LVL97:
+ 1513              	.LFB162:
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1514              		.loc 1 702 1 is_stmt 1 view -0
+ 1515              		.cfi_startproc
+ 1516              		@ args = 0, pretend = 0, frame = 24
+ 1517              		@ frame_needed = 0, uses_anonymous_args = 0
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1518              		.loc 1 702 1 is_stmt 0 view .LVU445
+ 1519 0000 30B5     		push	{r4, r5, lr}
+ 1520              	.LCFI30:
+ 1521              		.cfi_def_cfa_offset 12
+ 1522              		.cfi_offset 4, -12
+ 1523              		.cfi_offset 5, -8
+ 1524              		.cfi_offset 14, -4
+ 1525 0002 87B0     		sub	sp, sp, #28
+ 1526              	.LCFI31:
+ 1527              		.cfi_def_cfa_offset 40
+ 1528 0004 0446     		mov	r4, r0
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1529              		.loc 1 703 3 is_stmt 1 view .LVU446
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1530              		.loc 1 704 3 view .LVU447
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;
+ 1531              		.loc 1 707 3 view .LVU448
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;
+ARM GAS  /tmp/ccODg7xx.s 			page 62
+
+
+ 1532              		.loc 1 707 34 is_stmt 0 view .LVU449
+ 1533 0006 0191     		str	r1, [sp, #4]
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1534              		.loc 1 708 3 is_stmt 1 view .LVU450
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1535              		.loc 1 708 34 is_stmt 0 view .LVU451
+ 1536 0008 2425     		movs	r5, #36
+ 1537 000a 0295     		str	r5, [sp, #8]
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1538              		.loc 1 709 3 is_stmt 1 view .LVU452
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1539              		.loc 1 709 34 is_stmt 0 view .LVU453
+ 1540 000c 4023     		movs	r3, #64
+ 1541 000e 0393     		str	r3, [sp, #12]
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1542              		.loc 1 710 3 is_stmt 1 view .LVU454
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1543              		.loc 1 710 34 is_stmt 0 view .LVU455
+ 1544 0010 0023     		movs	r3, #0
+ 1545 0012 0493     		str	r3, [sp, #16]
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1546              		.loc 1 711 3 is_stmt 1 view .LVU456
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1547              		.loc 1 711 34 is_stmt 0 view .LVU457
+ 1548 0014 4FF48063 		mov	r3, #1024
+ 1549 0018 0593     		str	r3, [sp, #20]
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1550              		.loc 1 712 3 is_stmt 1 view .LVU458
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1551              		.loc 1 712 9 is_stmt 0 view .LVU459
+ 1552 001a 01A9     		add	r1, sp, #4
+ 1553              	.LVL98:
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1554              		.loc 1 712 9 view .LVU460
+ 1555 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1556              	.LVL99:
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1557              		.loc 1 715 3 is_stmt 1 view .LVU461
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1558              		.loc 1 715 16 is_stmt 0 view .LVU462
+ 1559 0020 41F28832 		movw	r2, #5000
+ 1560 0024 2946     		mov	r1, r5
+ 1561 0026 2046     		mov	r0, r4
+ 1562 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1563              	.LVL100:
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1564              		.loc 1 717 3 is_stmt 1 view .LVU463
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1565              		.loc 1 718 1 is_stmt 0 view .LVU464
+ 1566 002c 07B0     		add	sp, sp, #28
+ 1567              	.LCFI32:
+ 1568              		.cfi_def_cfa_offset 12
+ 1569              		@ sp needed
+ 1570 002e 30BD     		pop	{r4, r5, pc}
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1571              		.loc 1 718 1 view .LVU465
+ 1572              		.cfi_endproc
+ARM GAS  /tmp/ccODg7xx.s 			page 63
+
+
+ 1573              	.LFE162:
+ 1575              		.section	.text.SDMMC_CmdErase,"ax",%progbits
+ 1576              		.align	1
+ 1577              		.global	SDMMC_CmdErase
+ 1578              		.syntax unified
+ 1579              		.thumb
+ 1580              		.thumb_func
+ 1581              		.fpu fpv5-d16
+ 1583              	SDMMC_CmdErase:
+ 1584              	.LVL101:
+ 1585              	.LFB163:
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1586              		.loc 1 726 1 is_stmt 1 view -0
+ 1587              		.cfi_startproc
+ 1588              		@ args = 0, pretend = 0, frame = 24
+ 1589              		@ frame_needed = 0, uses_anonymous_args = 0
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1590              		.loc 1 726 1 is_stmt 0 view .LVU467
+ 1591 0000 30B5     		push	{r4, r5, lr}
+ 1592              	.LCFI33:
+ 1593              		.cfi_def_cfa_offset 12
+ 1594              		.cfi_offset 4, -12
+ 1595              		.cfi_offset 5, -8
+ 1596              		.cfi_offset 14, -4
+ 1597 0002 87B0     		sub	sp, sp, #28
+ 1598              	.LCFI34:
+ 1599              		.cfi_def_cfa_offset 40
+ 1600 0004 0446     		mov	r4, r0
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1601              		.loc 1 727 3 is_stmt 1 view .LVU468
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1602              		.loc 1 728 3 view .LVU469
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;
+ 1603              		.loc 1 731 3 view .LVU470
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;
+ 1604              		.loc 1 731 34 is_stmt 0 view .LVU471
+ 1605 0006 0023     		movs	r3, #0
+ 1606 0008 0193     		str	r3, [sp, #4]
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1607              		.loc 1 732 3 is_stmt 1 view .LVU472
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1608              		.loc 1 732 34 is_stmt 0 view .LVU473
+ 1609 000a 2625     		movs	r5, #38
+ 1610 000c 0295     		str	r5, [sp, #8]
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1611              		.loc 1 733 3 is_stmt 1 view .LVU474
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1612              		.loc 1 733 34 is_stmt 0 view .LVU475
+ 1613 000e 4022     		movs	r2, #64
+ 1614 0010 0392     		str	r2, [sp, #12]
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1615              		.loc 1 734 3 is_stmt 1 view .LVU476
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1616              		.loc 1 734 34 is_stmt 0 view .LVU477
+ 1617 0012 0493     		str	r3, [sp, #16]
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1618              		.loc 1 735 3 is_stmt 1 view .LVU478
+ARM GAS  /tmp/ccODg7xx.s 			page 64
+
+
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1619              		.loc 1 735 34 is_stmt 0 view .LVU479
+ 1620 0014 4FF48063 		mov	r3, #1024
+ 1621 0018 0593     		str	r3, [sp, #20]
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1622              		.loc 1 736 3 is_stmt 1 view .LVU480
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1623              		.loc 1 736 9 is_stmt 0 view .LVU481
+ 1624 001a 01A9     		add	r1, sp, #4
+ 1625 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1626              	.LVL102:
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1627              		.loc 1 739 3 is_stmt 1 view .LVU482
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1628              		.loc 1 739 16 is_stmt 0 view .LVU483
+ 1629 0020 4FF21862 		movw	r2, #63000
+ 1630 0024 2946     		mov	r1, r5
+ 1631 0026 2046     		mov	r0, r4
+ 1632 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1633              	.LVL103:
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1634              		.loc 1 741 3 is_stmt 1 view .LVU484
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1635              		.loc 1 742 1 is_stmt 0 view .LVU485
+ 1636 002c 07B0     		add	sp, sp, #28
+ 1637              	.LCFI35:
+ 1638              		.cfi_def_cfa_offset 12
+ 1639              		@ sp needed
+ 1640 002e 30BD     		pop	{r4, r5, pc}
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1641              		.loc 1 742 1 view .LVU486
+ 1642              		.cfi_endproc
+ 1643              	.LFE163:
+ 1645              		.section	.text.SDMMC_CmdStopTransfer,"ax",%progbits
+ 1646              		.align	1
+ 1647              		.global	SDMMC_CmdStopTransfer
+ 1648              		.syntax unified
+ 1649              		.thumb
+ 1650              		.thumb_func
+ 1651              		.fpu fpv5-d16
+ 1653              	SDMMC_CmdStopTransfer:
+ 1654              	.LVL104:
+ 1655              	.LFB164:
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1656              		.loc 1 750 1 is_stmt 1 view -0
+ 1657              		.cfi_startproc
+ 1658              		@ args = 0, pretend = 0, frame = 24
+ 1659              		@ frame_needed = 0, uses_anonymous_args = 0
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1660              		.loc 1 750 1 is_stmt 0 view .LVU488
+ 1661 0000 30B5     		push	{r4, r5, lr}
+ 1662              	.LCFI36:
+ 1663              		.cfi_def_cfa_offset 12
+ 1664              		.cfi_offset 4, -12
+ 1665              		.cfi_offset 5, -8
+ 1666              		.cfi_offset 14, -4
+ 1667 0002 87B0     		sub	sp, sp, #28
+ARM GAS  /tmp/ccODg7xx.s 			page 65
+
+
+ 1668              	.LCFI37:
+ 1669              		.cfi_def_cfa_offset 40
+ 1670 0004 0446     		mov	r4, r0
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1671              		.loc 1 751 3 is_stmt 1 view .LVU489
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1672              		.loc 1 752 3 view .LVU490
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;
+ 1673              		.loc 1 755 3 view .LVU491
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;
+ 1674              		.loc 1 755 34 is_stmt 0 view .LVU492
+ 1675 0006 0023     		movs	r3, #0
+ 1676 0008 0193     		str	r3, [sp, #4]
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1677              		.loc 1 756 3 is_stmt 1 view .LVU493
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1678              		.loc 1 756 34 is_stmt 0 view .LVU494
+ 1679 000a 0C25     		movs	r5, #12
+ 1680 000c 0295     		str	r5, [sp, #8]
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1681              		.loc 1 757 3 is_stmt 1 view .LVU495
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1682              		.loc 1 757 34 is_stmt 0 view .LVU496
+ 1683 000e 4022     		movs	r2, #64
+ 1684 0010 0392     		str	r2, [sp, #12]
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1685              		.loc 1 758 3 is_stmt 1 view .LVU497
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1686              		.loc 1 758 34 is_stmt 0 view .LVU498
+ 1687 0012 0493     		str	r3, [sp, #16]
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1688              		.loc 1 759 3 is_stmt 1 view .LVU499
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1689              		.loc 1 759 34 is_stmt 0 view .LVU500
+ 1690 0014 4FF48063 		mov	r3, #1024
+ 1691 0018 0593     		str	r3, [sp, #20]
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1692              		.loc 1 760 3 is_stmt 1 view .LVU501
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1693              		.loc 1 760 9 is_stmt 0 view .LVU502
+ 1694 001a 01A9     		add	r1, sp, #4
+ 1695 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1696              	.LVL105:
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1697              		.loc 1 763 3 is_stmt 1 view .LVU503
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1698              		.loc 1 763 16 is_stmt 0 view .LVU504
+ 1699 0020 034A     		ldr	r2, .L79
+ 1700 0022 2946     		mov	r1, r5
+ 1701 0024 2046     		mov	r0, r4
+ 1702 0026 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1703              	.LVL106:
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1704              		.loc 1 765 3 is_stmt 1 view .LVU505
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1705              		.loc 1 766 1 is_stmt 0 view .LVU506
+ 1706 002a 07B0     		add	sp, sp, #28
+ARM GAS  /tmp/ccODg7xx.s 			page 66
+
+
+ 1707              	.LCFI38:
+ 1708              		.cfi_def_cfa_offset 12
+ 1709              		@ sp needed
+ 1710 002c 30BD     		pop	{r4, r5, pc}
+ 1711              	.LVL107:
+ 1712              	.L80:
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1713              		.loc 1 766 1 view .LVU507
+ 1714 002e 00BF     		.align	2
+ 1715              	.L79:
+ 1716 0030 00E1F505 		.word	100000000
+ 1717              		.cfi_endproc
+ 1718              	.LFE164:
+ 1720              		.section	.text.SDMMC_CmdSelDesel,"ax",%progbits
+ 1721              		.align	1
+ 1722              		.global	SDMMC_CmdSelDesel
+ 1723              		.syntax unified
+ 1724              		.thumb
+ 1725              		.thumb_func
+ 1726              		.fpu fpv5-d16
+ 1728              	SDMMC_CmdSelDesel:
+ 1729              	.LVL108:
+ 1730              	.LFB165:
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1731              		.loc 1 775 1 is_stmt 1 view -0
+ 1732              		.cfi_startproc
+ 1733              		@ args = 0, pretend = 0, frame = 24
+ 1734              		@ frame_needed = 0, uses_anonymous_args = 0
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1735              		.loc 1 775 1 is_stmt 0 view .LVU509
+ 1736 0000 30B5     		push	{r4, r5, lr}
+ 1737              	.LCFI39:
+ 1738              		.cfi_def_cfa_offset 12
+ 1739              		.cfi_offset 4, -12
+ 1740              		.cfi_offset 5, -8
+ 1741              		.cfi_offset 14, -4
+ 1742 0002 87B0     		sub	sp, sp, #28
+ 1743              	.LCFI40:
+ 1744              		.cfi_def_cfa_offset 40
+ 1745 0004 0446     		mov	r4, r0
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1746              		.loc 1 776 3 is_stmt 1 view .LVU510
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1747              		.loc 1 777 3 view .LVU511
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;
+ 1748              		.loc 1 780 3 view .LVU512
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;
+ 1749              		.loc 1 780 34 is_stmt 0 view .LVU513
+ 1750 0006 0192     		str	r2, [sp, #4]
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1751              		.loc 1 781 3 is_stmt 1 view .LVU514
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1752              		.loc 1 781 34 is_stmt 0 view .LVU515
+ 1753 0008 0725     		movs	r5, #7
+ 1754 000a 0295     		str	r5, [sp, #8]
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1755              		.loc 1 782 3 is_stmt 1 view .LVU516
+ARM GAS  /tmp/ccODg7xx.s 			page 67
+
+
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1756              		.loc 1 782 34 is_stmt 0 view .LVU517
+ 1757 000c 4023     		movs	r3, #64
+ 1758 000e 0393     		str	r3, [sp, #12]
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1759              		.loc 1 783 3 is_stmt 1 view .LVU518
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1760              		.loc 1 783 34 is_stmt 0 view .LVU519
+ 1761 0010 0023     		movs	r3, #0
+ 1762 0012 0493     		str	r3, [sp, #16]
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1763              		.loc 1 784 3 is_stmt 1 view .LVU520
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1764              		.loc 1 784 34 is_stmt 0 view .LVU521
+ 1765 0014 4FF48063 		mov	r3, #1024
+ 1766 0018 0593     		str	r3, [sp, #20]
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1767              		.loc 1 785 3 is_stmt 1 view .LVU522
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1768              		.loc 1 785 9 is_stmt 0 view .LVU523
+ 1769 001a 01A9     		add	r1, sp, #4
+ 1770 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1771              	.LVL109:
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1772              		.loc 1 788 3 is_stmt 1 view .LVU524
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1773              		.loc 1 788 16 is_stmt 0 view .LVU525
+ 1774 0020 41F28832 		movw	r2, #5000
+ 1775 0024 2946     		mov	r1, r5
+ 1776 0026 2046     		mov	r0, r4
+ 1777 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1778              	.LVL110:
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1779              		.loc 1 790 3 is_stmt 1 view .LVU526
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1780              		.loc 1 791 1 is_stmt 0 view .LVU527
+ 1781 002c 07B0     		add	sp, sp, #28
+ 1782              	.LCFI41:
+ 1783              		.cfi_def_cfa_offset 12
+ 1784              		@ sp needed
+ 1785 002e 30BD     		pop	{r4, r5, pc}
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1786              		.loc 1 791 1 view .LVU528
+ 1787              		.cfi_endproc
+ 1788              	.LFE165:
+ 1790              		.section	.text.SDMMC_CmdAppCommand,"ax",%progbits
+ 1791              		.align	1
+ 1792              		.global	SDMMC_CmdAppCommand
+ 1793              		.syntax unified
+ 1794              		.thumb
+ 1795              		.thumb_func
+ 1796              		.fpu fpv5-d16
+ 1798              	SDMMC_CmdAppCommand:
+ 1799              	.LVL111:
+ 1800              	.LFB168:
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1801              		.loc 1 853 1 is_stmt 1 view -0
+ARM GAS  /tmp/ccODg7xx.s 			page 68
+
+
+ 1802              		.cfi_startproc
+ 1803              		@ args = 0, pretend = 0, frame = 24
+ 1804              		@ frame_needed = 0, uses_anonymous_args = 0
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1805              		.loc 1 853 1 is_stmt 0 view .LVU530
+ 1806 0000 30B5     		push	{r4, r5, lr}
+ 1807              	.LCFI42:
+ 1808              		.cfi_def_cfa_offset 12
+ 1809              		.cfi_offset 4, -12
+ 1810              		.cfi_offset 5, -8
+ 1811              		.cfi_offset 14, -4
+ 1812 0002 87B0     		sub	sp, sp, #28
+ 1813              	.LCFI43:
+ 1814              		.cfi_def_cfa_offset 40
+ 1815 0004 0446     		mov	r4, r0
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1816              		.loc 1 854 3 is_stmt 1 view .LVU531
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1817              		.loc 1 855 3 view .LVU532
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;
+ 1818              		.loc 1 857 3 view .LVU533
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;
+ 1819              		.loc 1 857 34 is_stmt 0 view .LVU534
+ 1820 0006 0191     		str	r1, [sp, #4]
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1821              		.loc 1 858 3 is_stmt 1 view .LVU535
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1822              		.loc 1 858 34 is_stmt 0 view .LVU536
+ 1823 0008 3725     		movs	r5, #55
+ 1824 000a 0295     		str	r5, [sp, #8]
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1825              		.loc 1 859 3 is_stmt 1 view .LVU537
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1826              		.loc 1 859 34 is_stmt 0 view .LVU538
+ 1827 000c 4023     		movs	r3, #64
+ 1828 000e 0393     		str	r3, [sp, #12]
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1829              		.loc 1 860 3 is_stmt 1 view .LVU539
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1830              		.loc 1 860 34 is_stmt 0 view .LVU540
+ 1831 0010 0023     		movs	r3, #0
+ 1832 0012 0493     		str	r3, [sp, #16]
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1833              		.loc 1 861 3 is_stmt 1 view .LVU541
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1834              		.loc 1 861 34 is_stmt 0 view .LVU542
+ 1835 0014 4FF48063 		mov	r3, #1024
+ 1836 0018 0593     		str	r3, [sp, #20]
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1837              		.loc 1 862 3 is_stmt 1 view .LVU543
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1838              		.loc 1 862 9 is_stmt 0 view .LVU544
+ 1839 001a 01A9     		add	r1, sp, #4
+ 1840              	.LVL112:
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1841              		.loc 1 862 9 view .LVU545
+ 1842 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ARM GAS  /tmp/ccODg7xx.s 			page 69
+
+
+ 1843              	.LVL113:
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1844              		.loc 1 868 3 is_stmt 1 view .LVU546
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1845              		.loc 1 868 16 is_stmt 0 view .LVU547
+ 1846 0020 41F28832 		movw	r2, #5000
+ 1847 0024 2946     		mov	r1, r5
+ 1848 0026 2046     		mov	r0, r4
+ 1849 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1850              	.LVL114:
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1851              		.loc 1 870 3 is_stmt 1 view .LVU548
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1852              		.loc 1 871 1 is_stmt 0 view .LVU549
+ 1853 002c 07B0     		add	sp, sp, #28
+ 1854              	.LCFI44:
+ 1855              		.cfi_def_cfa_offset 12
+ 1856              		@ sp needed
+ 1857 002e 30BD     		pop	{r4, r5, pc}
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1858              		.loc 1 871 1 view .LVU550
+ 1859              		.cfi_endproc
+ 1860              	.LFE168:
+ 1862              		.section	.text.SDMMC_CmdBusWidth,"ax",%progbits
+ 1863              		.align	1
+ 1864              		.global	SDMMC_CmdBusWidth
+ 1865              		.syntax unified
+ 1866              		.thumb
+ 1867              		.thumb_func
+ 1868              		.fpu fpv5-d16
+ 1870              	SDMMC_CmdBusWidth:
+ 1871              	.LVL115:
+ 1872              	.LFB170:
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1873              		.loc 1 905 1 is_stmt 1 view -0
+ 1874              		.cfi_startproc
+ 1875              		@ args = 0, pretend = 0, frame = 24
+ 1876              		@ frame_needed = 0, uses_anonymous_args = 0
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1877              		.loc 1 905 1 is_stmt 0 view .LVU552
+ 1878 0000 30B5     		push	{r4, r5, lr}
+ 1879              	.LCFI45:
+ 1880              		.cfi_def_cfa_offset 12
+ 1881              		.cfi_offset 4, -12
+ 1882              		.cfi_offset 5, -8
+ 1883              		.cfi_offset 14, -4
+ 1884 0002 87B0     		sub	sp, sp, #28
+ 1885              	.LCFI46:
+ 1886              		.cfi_def_cfa_offset 40
+ 1887 0004 0446     		mov	r4, r0
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1888              		.loc 1 906 3 is_stmt 1 view .LVU553
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1889              		.loc 1 907 3 view .LVU554
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+ 1890              		.loc 1 909 3 view .LVU555
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+ARM GAS  /tmp/ccODg7xx.s 			page 70
+
+
+ 1891              		.loc 1 909 34 is_stmt 0 view .LVU556
+ 1892 0006 0191     		str	r1, [sp, #4]
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1893              		.loc 1 910 3 is_stmt 1 view .LVU557
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1894              		.loc 1 910 34 is_stmt 0 view .LVU558
+ 1895 0008 0625     		movs	r5, #6
+ 1896 000a 0295     		str	r5, [sp, #8]
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1897              		.loc 1 911 3 is_stmt 1 view .LVU559
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1898              		.loc 1 911 34 is_stmt 0 view .LVU560
+ 1899 000c 4023     		movs	r3, #64
+ 1900 000e 0393     		str	r3, [sp, #12]
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1901              		.loc 1 912 3 is_stmt 1 view .LVU561
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1902              		.loc 1 912 34 is_stmt 0 view .LVU562
+ 1903 0010 0023     		movs	r3, #0
+ 1904 0012 0493     		str	r3, [sp, #16]
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1905              		.loc 1 913 3 is_stmt 1 view .LVU563
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1906              		.loc 1 913 34 is_stmt 0 view .LVU564
+ 1907 0014 4FF48063 		mov	r3, #1024
+ 1908 0018 0593     		str	r3, [sp, #20]
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1909              		.loc 1 914 3 is_stmt 1 view .LVU565
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1910              		.loc 1 914 9 is_stmt 0 view .LVU566
+ 1911 001a 01A9     		add	r1, sp, #4
+ 1912              	.LVL116:
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1913              		.loc 1 914 9 view .LVU567
+ 1914 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1915              	.LVL117:
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1916              		.loc 1 917 3 is_stmt 1 view .LVU568
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1917              		.loc 1 917 16 is_stmt 0 view .LVU569
+ 1918 0020 41F28832 		movw	r2, #5000
+ 1919 0024 2946     		mov	r1, r5
+ 1920 0026 2046     		mov	r0, r4
+ 1921 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1922              	.LVL118:
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1923              		.loc 1 919 3 is_stmt 1 view .LVU570
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1924              		.loc 1 920 1 is_stmt 0 view .LVU571
+ 1925 002c 07B0     		add	sp, sp, #28
+ 1926              	.LCFI47:
+ 1927              		.cfi_def_cfa_offset 12
+ 1928              		@ sp needed
+ 1929 002e 30BD     		pop	{r4, r5, pc}
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1930              		.loc 1 920 1 view .LVU572
+ 1931              		.cfi_endproc
+ARM GAS  /tmp/ccODg7xx.s 			page 71
+
+
+ 1932              	.LFE170:
+ 1934              		.section	.text.SDMMC_CmdSendSCR,"ax",%progbits
+ 1935              		.align	1
+ 1936              		.global	SDMMC_CmdSendSCR
+ 1937              		.syntax unified
+ 1938              		.thumb
+ 1939              		.thumb_func
+ 1940              		.fpu fpv5-d16
+ 1942              	SDMMC_CmdSendSCR:
+ 1943              	.LVL119:
+ 1944              	.LFB171:
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1945              		.loc 1 928 1 is_stmt 1 view -0
+ 1946              		.cfi_startproc
+ 1947              		@ args = 0, pretend = 0, frame = 24
+ 1948              		@ frame_needed = 0, uses_anonymous_args = 0
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 1949              		.loc 1 928 1 is_stmt 0 view .LVU574
+ 1950 0000 30B5     		push	{r4, r5, lr}
+ 1951              	.LCFI48:
+ 1952              		.cfi_def_cfa_offset 12
+ 1953              		.cfi_offset 4, -12
+ 1954              		.cfi_offset 5, -8
+ 1955              		.cfi_offset 14, -4
+ 1956 0002 87B0     		sub	sp, sp, #28
+ 1957              	.LCFI49:
+ 1958              		.cfi_def_cfa_offset 40
+ 1959 0004 0446     		mov	r4, r0
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 1960              		.loc 1 929 3 is_stmt 1 view .LVU575
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1961              		.loc 1 930 3 view .LVU576
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;
+ 1962              		.loc 1 933 3 view .LVU577
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;
+ 1963              		.loc 1 933 34 is_stmt 0 view .LVU578
+ 1964 0006 0023     		movs	r3, #0
+ 1965 0008 0193     		str	r3, [sp, #4]
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1966              		.loc 1 934 3 is_stmt 1 view .LVU579
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 1967              		.loc 1 934 34 is_stmt 0 view .LVU580
+ 1968 000a 3325     		movs	r5, #51
+ 1969 000c 0295     		str	r5, [sp, #8]
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1970              		.loc 1 935 3 is_stmt 1 view .LVU581
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 1971              		.loc 1 935 34 is_stmt 0 view .LVU582
+ 1972 000e 4022     		movs	r2, #64
+ 1973 0010 0392     		str	r2, [sp, #12]
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1974              		.loc 1 936 3 is_stmt 1 view .LVU583
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 1975              		.loc 1 936 34 is_stmt 0 view .LVU584
+ 1976 0012 0493     		str	r3, [sp, #16]
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1977              		.loc 1 937 3 is_stmt 1 view .LVU585
+ARM GAS  /tmp/ccODg7xx.s 			page 72
+
+
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 1978              		.loc 1 937 34 is_stmt 0 view .LVU586
+ 1979 0014 4FF48063 		mov	r3, #1024
+ 1980 0018 0593     		str	r3, [sp, #20]
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1981              		.loc 1 938 3 is_stmt 1 view .LVU587
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 1982              		.loc 1 938 9 is_stmt 0 view .LVU588
+ 1983 001a 01A9     		add	r1, sp, #4
+ 1984 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 1985              	.LVL120:
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1986              		.loc 1 941 3 is_stmt 1 view .LVU589
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1987              		.loc 1 941 16 is_stmt 0 view .LVU590
+ 1988 0020 41F28832 		movw	r2, #5000
+ 1989 0024 2946     		mov	r1, r5
+ 1990 0026 2046     		mov	r0, r4
+ 1991 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 1992              	.LVL121:
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 1993              		.loc 1 943 3 is_stmt 1 view .LVU591
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 1994              		.loc 1 944 1 is_stmt 0 view .LVU592
+ 1995 002c 07B0     		add	sp, sp, #28
+ 1996              	.LCFI50:
+ 1997              		.cfi_def_cfa_offset 12
+ 1998              		@ sp needed
+ 1999 002e 30BD     		pop	{r4, r5, pc}
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2000              		.loc 1 944 1 view .LVU593
+ 2001              		.cfi_endproc
+ 2002              	.LFE171:
+ 2004              		.section	.text.SDMMC_CmdSetRelAddMmc,"ax",%progbits
+ 2005              		.align	1
+ 2006              		.global	SDMMC_CmdSetRelAddMmc
+ 2007              		.syntax unified
+ 2008              		.thumb
+ 2009              		.thumb_func
+ 2010              		.fpu fpv5-d16
+ 2012              	SDMMC_CmdSetRelAddMmc:
+ 2013              	.LVL122:
+ 2014              	.LFB175:
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2015              		.loc 1 1027 1 is_stmt 1 view -0
+ 2016              		.cfi_startproc
+ 2017              		@ args = 0, pretend = 0, frame = 24
+ 2018              		@ frame_needed = 0, uses_anonymous_args = 0
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2019              		.loc 1 1027 1 is_stmt 0 view .LVU595
+ 2020 0000 30B5     		push	{r4, r5, lr}
+ 2021              	.LCFI51:
+ 2022              		.cfi_def_cfa_offset 12
+ 2023              		.cfi_offset 4, -12
+ 2024              		.cfi_offset 5, -8
+ 2025              		.cfi_offset 14, -4
+ 2026 0002 87B0     		sub	sp, sp, #28
+ARM GAS  /tmp/ccODg7xx.s 			page 73
+
+
+ 2027              	.LCFI52:
+ 2028              		.cfi_def_cfa_offset 40
+ 2029 0004 0446     		mov	r4, r0
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 2030              		.loc 1 1028 3 is_stmt 1 view .LVU596
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2031              		.loc 1 1029 3 view .LVU597
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+ 2032              		.loc 1 1032 3 view .LVU598
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+ 2033              		.loc 1 1032 51 is_stmt 0 view .LVU599
+ 2034 0006 0904     		lsls	r1, r1, #16
+ 2035              	.LVL123:
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+ 2036              		.loc 1 1032 34 view .LVU600
+ 2037 0008 0191     		str	r1, [sp, #4]
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2038              		.loc 1 1033 3 is_stmt 1 view .LVU601
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2039              		.loc 1 1033 34 is_stmt 0 view .LVU602
+ 2040 000a 0325     		movs	r5, #3
+ 2041 000c 0295     		str	r5, [sp, #8]
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2042              		.loc 1 1034 3 is_stmt 1 view .LVU603
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2043              		.loc 1 1034 34 is_stmt 0 view .LVU604
+ 2044 000e 4023     		movs	r3, #64
+ 2045 0010 0393     		str	r3, [sp, #12]
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2046              		.loc 1 1035 3 is_stmt 1 view .LVU605
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2047              		.loc 1 1035 34 is_stmt 0 view .LVU606
+ 2048 0012 0023     		movs	r3, #0
+ 2049 0014 0493     		str	r3, [sp, #16]
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2050              		.loc 1 1036 3 is_stmt 1 view .LVU607
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2051              		.loc 1 1036 34 is_stmt 0 view .LVU608
+ 2052 0016 4FF48063 		mov	r3, #1024
+ 2053 001a 0593     		str	r3, [sp, #20]
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2054              		.loc 1 1037 3 is_stmt 1 view .LVU609
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2055              		.loc 1 1037 9 is_stmt 0 view .LVU610
+ 2056 001c 01A9     		add	r1, sp, #4
+ 2057 001e FFF7FEFF 		bl	SDMMC_SendCommand
+ 2058              	.LVL124:
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2059              		.loc 1 1040 3 is_stmt 1 view .LVU611
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2060              		.loc 1 1040 16 is_stmt 0 view .LVU612
+ 2061 0022 41F28832 		movw	r2, #5000
+ 2062 0026 2946     		mov	r1, r5
+ 2063 0028 2046     		mov	r0, r4
+ 2064 002a FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 2065              	.LVL125:
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ARM GAS  /tmp/ccODg7xx.s 			page 74
+
+
+ 2066              		.loc 1 1042 3 is_stmt 1 view .LVU613
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2067              		.loc 1 1043 1 is_stmt 0 view .LVU614
+ 2068 002e 07B0     		add	sp, sp, #28
+ 2069              	.LCFI53:
+ 2070              		.cfi_def_cfa_offset 12
+ 2071              		@ sp needed
+ 2072 0030 30BD     		pop	{r4, r5, pc}
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2073              		.loc 1 1043 1 view .LVU615
+ 2074              		.cfi_endproc
+ 2075              	.LFE175:
+ 2077              		.section	.text.SDMMC_CmdSendStatus,"ax",%progbits
+ 2078              		.align	1
+ 2079              		.global	SDMMC_CmdSendStatus
+ 2080              		.syntax unified
+ 2081              		.thumb
+ 2082              		.thumb_func
+ 2083              		.fpu fpv5-d16
+ 2085              	SDMMC_CmdSendStatus:
+ 2086              	.LVL126:
+ 2087              	.LFB176:
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2088              		.loc 1 1052 1 is_stmt 1 view -0
+ 2089              		.cfi_startproc
+ 2090              		@ args = 0, pretend = 0, frame = 24
+ 2091              		@ frame_needed = 0, uses_anonymous_args = 0
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2092              		.loc 1 1052 1 is_stmt 0 view .LVU617
+ 2093 0000 30B5     		push	{r4, r5, lr}
+ 2094              	.LCFI54:
+ 2095              		.cfi_def_cfa_offset 12
+ 2096              		.cfi_offset 4, -12
+ 2097              		.cfi_offset 5, -8
+ 2098              		.cfi_offset 14, -4
+ 2099 0002 87B0     		sub	sp, sp, #28
+ 2100              	.LCFI55:
+ 2101              		.cfi_def_cfa_offset 40
+ 2102 0004 0446     		mov	r4, r0
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 2103              		.loc 1 1053 3 is_stmt 1 view .LVU618
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2104              		.loc 1 1054 3 view .LVU619
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;
+ 2105              		.loc 1 1056 3 view .LVU620
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;
+ 2106              		.loc 1 1056 34 is_stmt 0 view .LVU621
+ 2107 0006 0191     		str	r1, [sp, #4]
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2108              		.loc 1 1057 3 is_stmt 1 view .LVU622
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2109              		.loc 1 1057 34 is_stmt 0 view .LVU623
+ 2110 0008 0D25     		movs	r5, #13
+ 2111 000a 0295     		str	r5, [sp, #8]
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2112              		.loc 1 1058 3 is_stmt 1 view .LVU624
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ARM GAS  /tmp/ccODg7xx.s 			page 75
+
+
+ 2113              		.loc 1 1058 34 is_stmt 0 view .LVU625
+ 2114 000c 4023     		movs	r3, #64
+ 2115 000e 0393     		str	r3, [sp, #12]
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2116              		.loc 1 1059 3 is_stmt 1 view .LVU626
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2117              		.loc 1 1059 34 is_stmt 0 view .LVU627
+ 2118 0010 0023     		movs	r3, #0
+ 2119 0012 0493     		str	r3, [sp, #16]
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2120              		.loc 1 1060 3 is_stmt 1 view .LVU628
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2121              		.loc 1 1060 34 is_stmt 0 view .LVU629
+ 2122 0014 4FF48063 		mov	r3, #1024
+ 2123 0018 0593     		str	r3, [sp, #20]
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2124              		.loc 1 1061 3 is_stmt 1 view .LVU630
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2125              		.loc 1 1061 9 is_stmt 0 view .LVU631
+ 2126 001a 01A9     		add	r1, sp, #4
+ 2127              	.LVL127:
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2128              		.loc 1 1061 9 view .LVU632
+ 2129 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 2130              	.LVL128:
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2131              		.loc 1 1064 3 is_stmt 1 view .LVU633
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2132              		.loc 1 1064 16 is_stmt 0 view .LVU634
+ 2133 0020 41F28832 		movw	r2, #5000
+ 2134 0024 2946     		mov	r1, r5
+ 2135 0026 2046     		mov	r0, r4
+ 2136 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 2137              	.LVL129:
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2138              		.loc 1 1066 3 is_stmt 1 view .LVU635
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2139              		.loc 1 1067 1 is_stmt 0 view .LVU636
+ 2140 002c 07B0     		add	sp, sp, #28
+ 2141              	.LCFI56:
+ 2142              		.cfi_def_cfa_offset 12
+ 2143              		@ sp needed
+ 2144 002e 30BD     		pop	{r4, r5, pc}
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2145              		.loc 1 1067 1 view .LVU637
+ 2146              		.cfi_endproc
+ 2147              	.LFE176:
+ 2149              		.section	.text.SDMMC_CmdStatusRegister,"ax",%progbits
+ 2150              		.align	1
+ 2151              		.global	SDMMC_CmdStatusRegister
+ 2152              		.syntax unified
+ 2153              		.thumb
+ 2154              		.thumb_func
+ 2155              		.fpu fpv5-d16
+ 2157              	SDMMC_CmdStatusRegister:
+ 2158              	.LVL130:
+ 2159              	.LFB177:
+ARM GAS  /tmp/ccODg7xx.s 			page 76
+
+
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2160              		.loc 1 1075 1 is_stmt 1 view -0
+ 2161              		.cfi_startproc
+ 2162              		@ args = 0, pretend = 0, frame = 24
+ 2163              		@ frame_needed = 0, uses_anonymous_args = 0
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2164              		.loc 1 1075 1 is_stmt 0 view .LVU639
+ 2165 0000 30B5     		push	{r4, r5, lr}
+ 2166              	.LCFI57:
+ 2167              		.cfi_def_cfa_offset 12
+ 2168              		.cfi_offset 4, -12
+ 2169              		.cfi_offset 5, -8
+ 2170              		.cfi_offset 14, -4
+ 2171 0002 87B0     		sub	sp, sp, #28
+ 2172              	.LCFI58:
+ 2173              		.cfi_def_cfa_offset 40
+ 2174 0004 0446     		mov	r4, r0
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 2175              		.loc 1 1076 3 is_stmt 1 view .LVU640
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2176              		.loc 1 1077 3 view .LVU641
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;
+ 2177              		.loc 1 1079 3 view .LVU642
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;
+ 2178              		.loc 1 1079 34 is_stmt 0 view .LVU643
+ 2179 0006 0023     		movs	r3, #0
+ 2180 0008 0193     		str	r3, [sp, #4]
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2181              		.loc 1 1080 3 is_stmt 1 view .LVU644
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2182              		.loc 1 1080 34 is_stmt 0 view .LVU645
+ 2183 000a 0D25     		movs	r5, #13
+ 2184 000c 0295     		str	r5, [sp, #8]
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2185              		.loc 1 1081 3 is_stmt 1 view .LVU646
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2186              		.loc 1 1081 34 is_stmt 0 view .LVU647
+ 2187 000e 4022     		movs	r2, #64
+ 2188 0010 0392     		str	r2, [sp, #12]
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2189              		.loc 1 1082 3 is_stmt 1 view .LVU648
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2190              		.loc 1 1082 34 is_stmt 0 view .LVU649
+ 2191 0012 0493     		str	r3, [sp, #16]
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2192              		.loc 1 1083 3 is_stmt 1 view .LVU650
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2193              		.loc 1 1083 34 is_stmt 0 view .LVU651
+ 2194 0014 4FF48063 		mov	r3, #1024
+ 2195 0018 0593     		str	r3, [sp, #20]
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2196              		.loc 1 1084 3 is_stmt 1 view .LVU652
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2197              		.loc 1 1084 9 is_stmt 0 view .LVU653
+ 2198 001a 01A9     		add	r1, sp, #4
+ 2199 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 2200              	.LVL131:
+ARM GAS  /tmp/ccODg7xx.s 			page 77
+
+
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2201              		.loc 1 1087 3 is_stmt 1 view .LVU654
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2202              		.loc 1 1087 16 is_stmt 0 view .LVU655
+ 2203 0020 41F28832 		movw	r2, #5000
+ 2204 0024 2946     		mov	r1, r5
+ 2205 0026 2046     		mov	r0, r4
+ 2206 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 2207              	.LVL132:
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2208              		.loc 1 1089 3 is_stmt 1 view .LVU656
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2209              		.loc 1 1090 1 is_stmt 0 view .LVU657
+ 2210 002c 07B0     		add	sp, sp, #28
+ 2211              	.LCFI59:
+ 2212              		.cfi_def_cfa_offset 12
+ 2213              		@ sp needed
+ 2214 002e 30BD     		pop	{r4, r5, pc}
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2215              		.loc 1 1090 1 view .LVU658
+ 2216              		.cfi_endproc
+ 2217              	.LFE177:
+ 2219              		.section	.text.SDMMC_CmdSwitch,"ax",%progbits
+ 2220              		.align	1
+ 2221              		.global	SDMMC_CmdSwitch
+ 2222              		.syntax unified
+ 2223              		.thumb
+ 2224              		.thumb_func
+ 2225              		.fpu fpv5-d16
+ 2227              	SDMMC_CmdSwitch:
+ 2228              	.LVL133:
+ 2229              	.LFB179:
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2230              		.loc 1 1124 1 is_stmt 1 view -0
+ 2231              		.cfi_startproc
+ 2232              		@ args = 0, pretend = 0, frame = 24
+ 2233              		@ frame_needed = 0, uses_anonymous_args = 0
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2234              		.loc 1 1124 1 is_stmt 0 view .LVU660
+ 2235 0000 30B5     		push	{r4, r5, lr}
+ 2236              	.LCFI60:
+ 2237              		.cfi_def_cfa_offset 12
+ 2238              		.cfi_offset 4, -12
+ 2239              		.cfi_offset 5, -8
+ 2240              		.cfi_offset 14, -4
+ 2241 0002 87B0     		sub	sp, sp, #28
+ 2242              	.LCFI61:
+ 2243              		.cfi_def_cfa_offset 40
+ 2244 0004 0446     		mov	r4, r0
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 2245              		.loc 1 1125 3 is_stmt 1 view .LVU661
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2246              		.loc 1 1126 3 view .LVU662
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;
+ 2247              		.loc 1 1130 3 view .LVU663
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;
+ 2248              		.loc 1 1130 34 is_stmt 0 view .LVU664
+ARM GAS  /tmp/ccODg7xx.s 			page 78
+
+
+ 2249 0006 0191     		str	r1, [sp, #4]
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2250              		.loc 1 1131 3 is_stmt 1 view .LVU665
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2251              		.loc 1 1131 34 is_stmt 0 view .LVU666
+ 2252 0008 0625     		movs	r5, #6
+ 2253 000a 0295     		str	r5, [sp, #8]
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2254              		.loc 1 1132 3 is_stmt 1 view .LVU667
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2255              		.loc 1 1132 34 is_stmt 0 view .LVU668
+ 2256 000c 4023     		movs	r3, #64
+ 2257 000e 0393     		str	r3, [sp, #12]
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2258              		.loc 1 1133 3 is_stmt 1 view .LVU669
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2259              		.loc 1 1133 34 is_stmt 0 view .LVU670
+ 2260 0010 0023     		movs	r3, #0
+ 2261 0012 0493     		str	r3, [sp, #16]
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2262              		.loc 1 1134 3 is_stmt 1 view .LVU671
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2263              		.loc 1 1134 34 is_stmt 0 view .LVU672
+ 2264 0014 4FF48063 		mov	r3, #1024
+ 2265 0018 0593     		str	r3, [sp, #20]
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2266              		.loc 1 1135 3 is_stmt 1 view .LVU673
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2267              		.loc 1 1135 9 is_stmt 0 view .LVU674
+ 2268 001a 01A9     		add	r1, sp, #4
+ 2269              	.LVL134:
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2270              		.loc 1 1135 9 view .LVU675
+ 2271 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 2272              	.LVL135:
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2273              		.loc 1 1138 3 is_stmt 1 view .LVU676
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2274              		.loc 1 1138 16 is_stmt 0 view .LVU677
+ 2275 0020 41F28832 		movw	r2, #5000
+ 2276 0024 2946     		mov	r1, r5
+ 2277 0026 2046     		mov	r0, r4
+ 2278 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 2279              	.LVL136:
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2280              		.loc 1 1140 3 is_stmt 1 view .LVU678
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2281              		.loc 1 1141 1 is_stmt 0 view .LVU679
+ 2282 002c 07B0     		add	sp, sp, #28
+ 2283              	.LCFI62:
+ 2284              		.cfi_def_cfa_offset 12
+ 2285              		@ sp needed
+ 2286 002e 30BD     		pop	{r4, r5, pc}
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2287              		.loc 1 1141 1 view .LVU680
+ 2288              		.cfi_endproc
+ 2289              	.LFE179:
+ARM GAS  /tmp/ccODg7xx.s 			page 79
+
+
+ 2291              		.section	.text.SDMMC_CmdSendEXTCSD,"ax",%progbits
+ 2292              		.align	1
+ 2293              		.global	SDMMC_CmdSendEXTCSD
+ 2294              		.syntax unified
+ 2295              		.thumb
+ 2296              		.thumb_func
+ 2297              		.fpu fpv5-d16
+ 2299              	SDMMC_CmdSendEXTCSD:
+ 2300              	.LVL137:
+ 2301              	.LFB180:
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2302              		.loc 1 1150 1 is_stmt 1 view -0
+ 2303              		.cfi_startproc
+ 2304              		@ args = 0, pretend = 0, frame = 24
+ 2305              		@ frame_needed = 0, uses_anonymous_args = 0
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2306              		.loc 1 1150 1 is_stmt 0 view .LVU682
+ 2307 0000 30B5     		push	{r4, r5, lr}
+ 2308              	.LCFI63:
+ 2309              		.cfi_def_cfa_offset 12
+ 2310              		.cfi_offset 4, -12
+ 2311              		.cfi_offset 5, -8
+ 2312              		.cfi_offset 14, -4
+ 2313 0002 87B0     		sub	sp, sp, #28
+ 2314              	.LCFI64:
+ 2315              		.cfi_def_cfa_offset 40
+ 2316 0004 0446     		mov	r4, r0
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 2317              		.loc 1 1151 3 is_stmt 1 view .LVU683
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2318              		.loc 1 1152 3 view .LVU684
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+ 2319              		.loc 1 1155 3 view .LVU685
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+ 2320              		.loc 1 1155 34 is_stmt 0 view .LVU686
+ 2321 0006 0191     		str	r1, [sp, #4]
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2322              		.loc 1 1156 3 is_stmt 1 view .LVU687
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2323              		.loc 1 1156 34 is_stmt 0 view .LVU688
+ 2324 0008 0825     		movs	r5, #8
+ 2325 000a 0295     		str	r5, [sp, #8]
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2326              		.loc 1 1157 3 is_stmt 1 view .LVU689
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2327              		.loc 1 1157 34 is_stmt 0 view .LVU690
+ 2328 000c 4023     		movs	r3, #64
+ 2329 000e 0393     		str	r3, [sp, #12]
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2330              		.loc 1 1158 3 is_stmt 1 view .LVU691
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2331              		.loc 1 1158 34 is_stmt 0 view .LVU692
+ 2332 0010 0023     		movs	r3, #0
+ 2333 0012 0493     		str	r3, [sp, #16]
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2334              		.loc 1 1159 3 is_stmt 1 view .LVU693
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ARM GAS  /tmp/ccODg7xx.s 			page 80
+
+
+ 2335              		.loc 1 1159 34 is_stmt 0 view .LVU694
+ 2336 0014 4FF48063 		mov	r3, #1024
+ 2337 0018 0593     		str	r3, [sp, #20]
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2338              		.loc 1 1160 3 is_stmt 1 view .LVU695
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2339              		.loc 1 1160 9 is_stmt 0 view .LVU696
+ 2340 001a 01A9     		add	r1, sp, #4
+ 2341              	.LVL138:
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2342              		.loc 1 1160 9 view .LVU697
+ 2343 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 2344              	.LVL139:
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2345              		.loc 1 1163 3 is_stmt 1 view .LVU698
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2346              		.loc 1 1163 16 is_stmt 0 view .LVU699
+ 2347 0020 41F28832 		movw	r2, #5000
+ 2348 0024 2946     		mov	r1, r5
+ 2349 0026 2046     		mov	r0, r4
+ 2350 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp1
+ 2351              	.LVL140:
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2352              		.loc 1 1165 3 is_stmt 1 view .LVU700
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2353              		.loc 1 1166 1 is_stmt 0 view .LVU701
+ 2354 002c 07B0     		add	sp, sp, #28
+ 2355              	.LCFI65:
+ 2356              		.cfi_def_cfa_offset 12
+ 2357              		@ sp needed
+ 2358 002e 30BD     		pop	{r4, r5, pc}
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2359              		.loc 1 1166 1 view .LVU702
+ 2360              		.cfi_endproc
+ 2361              	.LFE180:
+ 2363              		.section	.text.SDMMC_GetCmdResp2,"ax",%progbits
+ 2364              		.align	1
+ 2365              		.global	SDMMC_GetCmdResp2
+ 2366              		.syntax unified
+ 2367              		.thumb
+ 2368              		.thumb_func
+ 2369              		.fpu fpv5-d16
+ 2371              	SDMMC_GetCmdResp2:
+ 2372              	.LVL141:
+ 2373              	.LFB182:
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+ 2374              		.loc 1 1327 1 is_stmt 1 view -0
+ 2375              		.cfi_startproc
+ 2376              		@ args = 0, pretend = 0, frame = 0
+ 2377              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2378              		@ link register save eliminated.
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+ 2379              		.loc 1 1327 1 is_stmt 0 view .LVU704
+ 2380 0000 0146     		mov	r1, r0
+1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* 8 is the number of required instructions cycles for the below loop statement.
+ 2381              		.loc 1 1328 3 is_stmt 1 view .LVU705
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ARM GAS  /tmp/ccODg7xx.s 			page 81
+
+
+ 2382              		.loc 1 1331 3 view .LVU706
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2383              		.loc 1 1331 61 is_stmt 0 view .LVU707
+ 2384 0002 144B     		ldr	r3, .L107
+ 2385 0004 1B68     		ldr	r3, [r3]
+ 2386 0006 144A     		ldr	r2, .L107+4
+ 2387 0008 A2FB0323 		umull	r2, r3, r2, r3
+ 2388 000c 5B0A     		lsrs	r3, r3, #9
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2389              		.loc 1 1331 12 view .LVU708
+ 2390 000e 41F28832 		movw	r2, #5000
+ 2391 0012 02FB03F3 		mul	r3, r2, r3
+ 2392              	.LVL142:
+ 2393              	.L101:
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2394              		.loc 1 1333 3 is_stmt 1 view .LVU709
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 2395              		.loc 1 1335 5 view .LVU710
+ 2396 0016 1A46     		mov	r2, r3
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 2397              		.loc 1 1335 14 is_stmt 0 view .LVU711
+ 2398 0018 013B     		subs	r3, r3, #1
+ 2399              	.LVL143:
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 2400              		.loc 1 1335 8 view .LVU712
+ 2401 001a BAB1     		cbz	r2, .L104
+1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 2402              		.loc 1 1339 5 is_stmt 1 view .LVU713
+1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 2403              		.loc 1 1339 13 is_stmt 0 view .LVU714
+ 2404 001c 4A6B     		ldr	r2, [r1, #52]
+ 2405              	.LVL144:
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ 2406              		.loc 1 1340 9 is_stmt 1 view .LVU715
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2407              		.loc 1 1341 10 is_stmt 0 view .LVU716
+ 2408 001e 12F0450F 		tst	r2, #69
+ 2409 0022 F8D0     		beq	.L101
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ 2410              		.loc 1 1340 95 discriminator 1 view .LVU717
+ 2411 0024 12F4006F 		tst	r2, #2048
+ 2412 0028 F5D1     		bne	.L101
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2413              		.loc 1 1343 3 is_stmt 1 view .LVU718
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2414              		.loc 1 1343 7 is_stmt 0 view .LVU719
+ 2415 002a 4B6B     		ldr	r3, [r1, #52]
+ 2416              	.LVL145:
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2417              		.loc 1 1343 6 view .LVU720
+ 2418 002c 13F0040F 		tst	r3, #4
+ 2419 0030 06D1     		bne	.L105
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2420              		.loc 1 1349 8 is_stmt 1 view .LVU721
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2421              		.loc 1 1349 12 is_stmt 0 view .LVU722
+ 2422 0032 486B     		ldr	r0, [r1, #52]
+ARM GAS  /tmp/ccODg7xx.s 			page 82
+
+
+ 2423              	.LVL146:
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2424              		.loc 1 1349 11 view .LVU723
+ 2425 0034 10F00100 		ands	r0, r0, #1
+ 2426 0038 05D1     		bne	.L106
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2427              		.loc 1 1359 5 is_stmt 1 view .LVU724
+ 2428 003a C523     		movs	r3, #197
+ 2429 003c 8B63     		str	r3, [r1, #56]
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2430              		.loc 1 1362 3 view .LVU725
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2431              		.loc 1 1362 10 is_stmt 0 view .LVU726
+ 2432 003e 7047     		bx	lr
+ 2433              	.LVL147:
+ 2434              	.L105:
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2435              		.loc 1 1345 5 is_stmt 1 view .LVU727
+ 2436 0040 0420     		movs	r0, #4
+ 2437              	.LVL148:
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2438              		.loc 1 1345 5 is_stmt 0 view .LVU728
+ 2439 0042 8863     		str	r0, [r1, #56]
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2440              		.loc 1 1347 5 is_stmt 1 view .LVU729
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2441              		.loc 1 1347 12 is_stmt 0 view .LVU730
+ 2442 0044 7047     		bx	lr
+ 2443              	.L106:
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2444              		.loc 1 1351 5 is_stmt 1 view .LVU731
+ 2445 0046 0120     		movs	r0, #1
+ 2446 0048 8863     		str	r0, [r1, #56]
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2447              		.loc 1 1353 5 view .LVU732
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2448              		.loc 1 1353 12 is_stmt 0 view .LVU733
+ 2449 004a 7047     		bx	lr
+ 2450              	.LVL149:
+ 2451              	.L104:
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+ 2452              		.loc 1 1337 14 view .LVU734
+ 2453 004c 4FF00040 		mov	r0, #-2147483648
+ 2454              	.LVL150:
+1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2455              		.loc 1 1363 1 view .LVU735
+ 2456 0050 7047     		bx	lr
+ 2457              	.L108:
+ 2458 0052 00BF     		.align	2
+ 2459              	.L107:
+ 2460 0054 00000000 		.word	SystemCoreClock
+ 2461 0058 D34D6210 		.word	274877907
+ 2462              		.cfi_endproc
+ 2463              	.LFE182:
+ 2465              		.section	.text.SDMMC_CmdSendCID,"ax",%progbits
+ 2466              		.align	1
+ 2467              		.global	SDMMC_CmdSendCID
+ARM GAS  /tmp/ccODg7xx.s 			page 83
+
+
+ 2468              		.syntax unified
+ 2469              		.thumb
+ 2470              		.thumb_func
+ 2471              		.fpu fpv5-d16
+ 2473              	SDMMC_CmdSendCID:
+ 2474              	.LVL151:
+ 2475              	.LFB172:
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2476              		.loc 1 952 1 is_stmt 1 view -0
+ 2477              		.cfi_startproc
+ 2478              		@ args = 0, pretend = 0, frame = 24
+ 2479              		@ frame_needed = 0, uses_anonymous_args = 0
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2480              		.loc 1 952 1 is_stmt 0 view .LVU737
+ 2481 0000 10B5     		push	{r4, lr}
+ 2482              	.LCFI66:
+ 2483              		.cfi_def_cfa_offset 8
+ 2484              		.cfi_offset 4, -8
+ 2485              		.cfi_offset 14, -4
+ 2486 0002 86B0     		sub	sp, sp, #24
+ 2487              	.LCFI67:
+ 2488              		.cfi_def_cfa_offset 32
+ 2489 0004 0446     		mov	r4, r0
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 2490              		.loc 1 953 3 is_stmt 1 view .LVU738
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2491              		.loc 1 954 3 view .LVU739
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;
+ 2492              		.loc 1 957 3 view .LVU740
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;
+ 2493              		.loc 1 957 34 is_stmt 0 view .LVU741
+ 2494 0006 0023     		movs	r3, #0
+ 2495 0008 0193     		str	r3, [sp, #4]
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+ 2496              		.loc 1 958 3 is_stmt 1 view .LVU742
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+ 2497              		.loc 1 958 34 is_stmt 0 view .LVU743
+ 2498 000a 0222     		movs	r2, #2
+ 2499 000c 0292     		str	r2, [sp, #8]
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2500              		.loc 1 959 3 is_stmt 1 view .LVU744
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2501              		.loc 1 959 34 is_stmt 0 view .LVU745
+ 2502 000e C022     		movs	r2, #192
+ 2503 0010 0392     		str	r2, [sp, #12]
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2504              		.loc 1 960 3 is_stmt 1 view .LVU746
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2505              		.loc 1 960 34 is_stmt 0 view .LVU747
+ 2506 0012 0493     		str	r3, [sp, #16]
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2507              		.loc 1 961 3 is_stmt 1 view .LVU748
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2508              		.loc 1 961 34 is_stmt 0 view .LVU749
+ 2509 0014 4FF48063 		mov	r3, #1024
+ 2510 0018 0593     		str	r3, [sp, #20]
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ARM GAS  /tmp/ccODg7xx.s 			page 84
+
+
+ 2511              		.loc 1 962 3 is_stmt 1 view .LVU750
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2512              		.loc 1 962 9 is_stmt 0 view .LVU751
+ 2513 001a 01A9     		add	r1, sp, #4
+ 2514 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 2515              	.LVL152:
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2516              		.loc 1 965 3 is_stmt 1 view .LVU752
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2517              		.loc 1 965 16 is_stmt 0 view .LVU753
+ 2518 0020 2046     		mov	r0, r4
+ 2519 0022 FFF7FEFF 		bl	SDMMC_GetCmdResp2
+ 2520              	.LVL153:
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2521              		.loc 1 967 3 is_stmt 1 view .LVU754
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2522              		.loc 1 968 1 is_stmt 0 view .LVU755
+ 2523 0026 06B0     		add	sp, sp, #24
+ 2524              	.LCFI68:
+ 2525              		.cfi_def_cfa_offset 8
+ 2526              		@ sp needed
+ 2527 0028 10BD     		pop	{r4, pc}
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2528              		.loc 1 968 1 view .LVU756
+ 2529              		.cfi_endproc
+ 2530              	.LFE172:
+ 2532              		.section	.text.SDMMC_CmdSendCSD,"ax",%progbits
+ 2533              		.align	1
+ 2534              		.global	SDMMC_CmdSendCSD
+ 2535              		.syntax unified
+ 2536              		.thumb
+ 2537              		.thumb_func
+ 2538              		.fpu fpv5-d16
+ 2540              	SDMMC_CmdSendCSD:
+ 2541              	.LVL154:
+ 2542              	.LFB173:
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2543              		.loc 1 977 1 is_stmt 1 view -0
+ 2544              		.cfi_startproc
+ 2545              		@ args = 0, pretend = 0, frame = 24
+ 2546              		@ frame_needed = 0, uses_anonymous_args = 0
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2547              		.loc 1 977 1 is_stmt 0 view .LVU758
+ 2548 0000 10B5     		push	{r4, lr}
+ 2549              	.LCFI69:
+ 2550              		.cfi_def_cfa_offset 8
+ 2551              		.cfi_offset 4, -8
+ 2552              		.cfi_offset 14, -4
+ 2553 0002 86B0     		sub	sp, sp, #24
+ 2554              	.LCFI70:
+ 2555              		.cfi_def_cfa_offset 32
+ 2556 0004 0446     		mov	r4, r0
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 2557              		.loc 1 978 3 is_stmt 1 view .LVU759
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2558              		.loc 1 979 3 view .LVU760
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;
+ARM GAS  /tmp/ccODg7xx.s 			page 85
+
+
+ 2559              		.loc 1 982 3 view .LVU761
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;
+ 2560              		.loc 1 982 34 is_stmt 0 view .LVU762
+ 2561 0006 0191     		str	r1, [sp, #4]
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+ 2562              		.loc 1 983 3 is_stmt 1 view .LVU763
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+ 2563              		.loc 1 983 34 is_stmt 0 view .LVU764
+ 2564 0008 0923     		movs	r3, #9
+ 2565 000a 0293     		str	r3, [sp, #8]
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2566              		.loc 1 984 3 is_stmt 1 view .LVU765
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2567              		.loc 1 984 34 is_stmt 0 view .LVU766
+ 2568 000c C023     		movs	r3, #192
+ 2569 000e 0393     		str	r3, [sp, #12]
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2570              		.loc 1 985 3 is_stmt 1 view .LVU767
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2571              		.loc 1 985 34 is_stmt 0 view .LVU768
+ 2572 0010 0023     		movs	r3, #0
+ 2573 0012 0493     		str	r3, [sp, #16]
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2574              		.loc 1 986 3 is_stmt 1 view .LVU769
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2575              		.loc 1 986 34 is_stmt 0 view .LVU770
+ 2576 0014 4FF48063 		mov	r3, #1024
+ 2577 0018 0593     		str	r3, [sp, #20]
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2578              		.loc 1 987 3 is_stmt 1 view .LVU771
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2579              		.loc 1 987 9 is_stmt 0 view .LVU772
+ 2580 001a 01A9     		add	r1, sp, #4
+ 2581              	.LVL155:
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2582              		.loc 1 987 9 view .LVU773
+ 2583 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 2584              	.LVL156:
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2585              		.loc 1 990 3 is_stmt 1 view .LVU774
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2586              		.loc 1 990 16 is_stmt 0 view .LVU775
+ 2587 0020 2046     		mov	r0, r4
+ 2588 0022 FFF7FEFF 		bl	SDMMC_GetCmdResp2
+ 2589              	.LVL157:
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2590              		.loc 1 992 3 is_stmt 1 view .LVU776
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2591              		.loc 1 993 1 is_stmt 0 view .LVU777
+ 2592 0026 06B0     		add	sp, sp, #24
+ 2593              	.LCFI71:
+ 2594              		.cfi_def_cfa_offset 8
+ 2595              		@ sp needed
+ 2596 0028 10BD     		pop	{r4, pc}
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2597              		.loc 1 993 1 view .LVU778
+ 2598              		.cfi_endproc
+ARM GAS  /tmp/ccODg7xx.s 			page 86
+
+
+ 2599              	.LFE173:
+ 2601              		.section	.text.SDMMC_GetCmdResp3,"ax",%progbits
+ 2602              		.align	1
+ 2603              		.global	SDMMC_GetCmdResp3
+ 2604              		.syntax unified
+ 2605              		.thumb
+ 2606              		.thumb_func
+ 2607              		.fpu fpv5-d16
+ 2609              	SDMMC_GetCmdResp3:
+ 2610              	.LVL158:
+ 2611              	.LFB183:
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+ 2612              		.loc 1 1371 1 is_stmt 1 view -0
+ 2613              		.cfi_startproc
+ 2614              		@ args = 0, pretend = 0, frame = 0
+ 2615              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2616              		@ link register save eliminated.
+1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+ 2617              		.loc 1 1371 1 is_stmt 0 view .LVU780
+ 2618 0000 0146     		mov	r1, r0
+1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* 8 is the number of required instructions cycles for the below loop statement.
+ 2619              		.loc 1 1372 3 is_stmt 1 view .LVU781
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2620              		.loc 1 1375 3 view .LVU782
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2621              		.loc 1 1375 61 is_stmt 0 view .LVU783
+ 2622 0002 104B     		ldr	r3, .L119
+ 2623 0004 1B68     		ldr	r3, [r3]
+ 2624 0006 104A     		ldr	r2, .L119+4
+ 2625 0008 A2FB0323 		umull	r2, r3, r2, r3
+ 2626 000c 5B0A     		lsrs	r3, r3, #9
+1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2627              		.loc 1 1375 12 view .LVU784
+ 2628 000e 41F28832 		movw	r2, #5000
+ 2629 0012 02FB03F3 		mul	r3, r2, r3
+ 2630              	.LVL159:
+ 2631              	.L115:
+1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2632              		.loc 1 1377 3 is_stmt 1 view .LVU785
+1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 2633              		.loc 1 1379 5 view .LVU786
+ 2634 0016 1A46     		mov	r2, r3
+1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 2635              		.loc 1 1379 14 is_stmt 0 view .LVU787
+ 2636 0018 013B     		subs	r3, r3, #1
+ 2637              	.LVL160:
+1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 2638              		.loc 1 1379 8 view .LVU788
+ 2639 001a 82B1     		cbz	r2, .L117
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 2640              		.loc 1 1383 5 is_stmt 1 view .LVU789
+1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 2641              		.loc 1 1383 13 is_stmt 0 view .LVU790
+ 2642 001c 4A6B     		ldr	r2, [r1, #52]
+ 2643              	.LVL161:
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ 2644              		.loc 1 1384 9 is_stmt 1 view .LVU791
+ARM GAS  /tmp/ccODg7xx.s 			page 87
+
+
+1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2645              		.loc 1 1385 10 is_stmt 0 view .LVU792
+ 2646 001e 12F0450F 		tst	r2, #69
+ 2647 0022 F8D0     		beq	.L115
+1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ 2648              		.loc 1 1384 95 discriminator 1 view .LVU793
+ 2649 0024 12F4006F 		tst	r2, #2048
+ 2650 0028 F5D1     		bne	.L115
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2651              		.loc 1 1387 3 is_stmt 1 view .LVU794
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2652              		.loc 1 1387 6 is_stmt 0 view .LVU795
+ 2653 002a 486B     		ldr	r0, [r1, #52]
+ 2654              	.LVL162:
+1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2655              		.loc 1 1387 5 view .LVU796
+ 2656 002c 10F00400 		ands	r0, r0, #4
+ 2657 0030 02D1     		bne	.L118
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2658              		.loc 1 1396 5 is_stmt 1 view .LVU797
+ 2659 0032 C523     		movs	r3, #197
+ 2660              	.LVL163:
+1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2661              		.loc 1 1396 5 is_stmt 0 view .LVU798
+ 2662 0034 8B63     		str	r3, [r1, #56]
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2663              		.loc 1 1399 3 is_stmt 1 view .LVU799
+1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2664              		.loc 1 1399 10 is_stmt 0 view .LVU800
+ 2665 0036 7047     		bx	lr
+ 2666              	.LVL164:
+ 2667              	.L118:
+1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2668              		.loc 1 1389 5 is_stmt 1 view .LVU801
+ 2669 0038 0420     		movs	r0, #4
+ 2670 003a 8863     		str	r0, [r1, #56]
+1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2671              		.loc 1 1391 5 view .LVU802
+1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2672              		.loc 1 1391 12 is_stmt 0 view .LVU803
+ 2673 003c 7047     		bx	lr
+ 2674              	.LVL165:
+ 2675              	.L117:
+1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+ 2676              		.loc 1 1381 14 view .LVU804
+ 2677 003e 4FF00040 		mov	r0, #-2147483648
+ 2678              	.LVL166:
+1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2679              		.loc 1 1400 1 view .LVU805
+ 2680 0042 7047     		bx	lr
+ 2681              	.L120:
+ 2682              		.align	2
+ 2683              	.L119:
+ 2684 0044 00000000 		.word	SystemCoreClock
+ 2685 0048 D34D6210 		.word	274877907
+ 2686              		.cfi_endproc
+ 2687              	.LFE183:
+ARM GAS  /tmp/ccODg7xx.s 			page 88
+
+
+ 2689              		.section	.text.SDMMC_CmdAppOperCommand,"ax",%progbits
+ 2690              		.align	1
+ 2691              		.global	SDMMC_CmdAppOperCommand
+ 2692              		.syntax unified
+ 2693              		.thumb
+ 2694              		.thumb_func
+ 2695              		.fpu fpv5-d16
+ 2697              	SDMMC_CmdAppOperCommand:
+ 2698              	.LVL167:
+ 2699              	.LFB169:
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2700              		.loc 1 881 1 is_stmt 1 view -0
+ 2701              		.cfi_startproc
+ 2702              		@ args = 0, pretend = 0, frame = 24
+ 2703              		@ frame_needed = 0, uses_anonymous_args = 0
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2704              		.loc 1 881 1 is_stmt 0 view .LVU807
+ 2705 0000 10B5     		push	{r4, lr}
+ 2706              	.LCFI72:
+ 2707              		.cfi_def_cfa_offset 8
+ 2708              		.cfi_offset 4, -8
+ 2709              		.cfi_offset 14, -4
+ 2710 0002 86B0     		sub	sp, sp, #24
+ 2711              	.LCFI73:
+ 2712              		.cfi_def_cfa_offset 32
+ 2713 0004 0446     		mov	r4, r0
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 2714              		.loc 1 882 3 is_stmt 1 view .LVU808
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2715              		.loc 1 883 3 view .LVU809
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
+ 2716              		.loc 1 885 3 view .LVU810
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
+ 2717              		.loc 1 885 60 is_stmt 0 view .LVU811
+ 2718 0006 0A4B     		ldr	r3, .L123
+ 2719 0008 0B43     		orrs	r3, r3, r1
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
+ 2720              		.loc 1 885 34 view .LVU812
+ 2721 000a 0193     		str	r3, [sp, #4]
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2722              		.loc 1 886 3 is_stmt 1 view .LVU813
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2723              		.loc 1 886 34 is_stmt 0 view .LVU814
+ 2724 000c 2923     		movs	r3, #41
+ 2725 000e 0293     		str	r3, [sp, #8]
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2726              		.loc 1 887 3 is_stmt 1 view .LVU815
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2727              		.loc 1 887 34 is_stmt 0 view .LVU816
+ 2728 0010 4023     		movs	r3, #64
+ 2729 0012 0393     		str	r3, [sp, #12]
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2730              		.loc 1 888 3 is_stmt 1 view .LVU817
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2731              		.loc 1 888 34 is_stmt 0 view .LVU818
+ 2732 0014 0023     		movs	r3, #0
+ 2733 0016 0493     		str	r3, [sp, #16]
+ARM GAS  /tmp/ccODg7xx.s 			page 89
+
+
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2734              		.loc 1 889 3 is_stmt 1 view .LVU819
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2735              		.loc 1 889 34 is_stmt 0 view .LVU820
+ 2736 0018 4FF48063 		mov	r3, #1024
+ 2737 001c 0593     		str	r3, [sp, #20]
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2738              		.loc 1 890 3 is_stmt 1 view .LVU821
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2739              		.loc 1 890 9 is_stmt 0 view .LVU822
+ 2740 001e 01A9     		add	r1, sp, #4
+ 2741              	.LVL168:
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2742              		.loc 1 890 9 view .LVU823
+ 2743 0020 FFF7FEFF 		bl	SDMMC_SendCommand
+ 2744              	.LVL169:
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2745              		.loc 1 893 3 is_stmt 1 view .LVU824
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2746              		.loc 1 893 16 is_stmt 0 view .LVU825
+ 2747 0024 2046     		mov	r0, r4
+ 2748 0026 FFF7FEFF 		bl	SDMMC_GetCmdResp3
+ 2749              	.LVL170:
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2750              		.loc 1 895 3 is_stmt 1 view .LVU826
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2751              		.loc 1 896 1 is_stmt 0 view .LVU827
+ 2752 002a 06B0     		add	sp, sp, #24
+ 2753              	.LCFI74:
+ 2754              		.cfi_def_cfa_offset 8
+ 2755              		@ sp needed
+ 2756 002c 10BD     		pop	{r4, pc}
+ 2757              	.LVL171:
+ 2758              	.L124:
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2759              		.loc 1 896 1 view .LVU828
+ 2760 002e 00BF     		.align	2
+ 2761              	.L123:
+ 2762 0030 00001080 		.word	-2146435072
+ 2763              		.cfi_endproc
+ 2764              	.LFE169:
+ 2766              		.section	.text.SDMMC_CmdOpCondition,"ax",%progbits
+ 2767              		.align	1
+ 2768              		.global	SDMMC_CmdOpCondition
+ 2769              		.syntax unified
+ 2770              		.thumb
+ 2771              		.thumb_func
+ 2772              		.fpu fpv5-d16
+ 2774              	SDMMC_CmdOpCondition:
+ 2775              	.LVL172:
+ 2776              	.LFB178:
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 2777              		.loc 1 1100 1 is_stmt 1 view -0
+ 2778              		.cfi_startproc
+ 2779              		@ args = 0, pretend = 0, frame = 24
+ 2780              		@ frame_needed = 0, uses_anonymous_args = 0
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ARM GAS  /tmp/ccODg7xx.s 			page 90
+
+
+ 2781              		.loc 1 1100 1 is_stmt 0 view .LVU830
+ 2782 0000 10B5     		push	{r4, lr}
+ 2783              	.LCFI75:
+ 2784              		.cfi_def_cfa_offset 8
+ 2785              		.cfi_offset 4, -8
+ 2786              		.cfi_offset 14, -4
+ 2787 0002 86B0     		sub	sp, sp, #24
+ 2788              	.LCFI76:
+ 2789              		.cfi_def_cfa_offset 32
+ 2790 0004 0446     		mov	r4, r0
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 2791              		.loc 1 1101 3 is_stmt 1 view .LVU831
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2792              		.loc 1 1102 3 view .LVU832
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;
+ 2793              		.loc 1 1104 3 view .LVU833
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;
+ 2794              		.loc 1 1104 34 is_stmt 0 view .LVU834
+ 2795 0006 0191     		str	r1, [sp, #4]
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2796              		.loc 1 1105 3 is_stmt 1 view .LVU835
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 2797              		.loc 1 1105 34 is_stmt 0 view .LVU836
+ 2798 0008 0123     		movs	r3, #1
+ 2799 000a 0293     		str	r3, [sp, #8]
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2800              		.loc 1 1106 3 is_stmt 1 view .LVU837
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 2801              		.loc 1 1106 34 is_stmt 0 view .LVU838
+ 2802 000c 4023     		movs	r3, #64
+ 2803 000e 0393     		str	r3, [sp, #12]
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2804              		.loc 1 1107 3 is_stmt 1 view .LVU839
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 2805              		.loc 1 1107 34 is_stmt 0 view .LVU840
+ 2806 0010 0023     		movs	r3, #0
+ 2807 0012 0493     		str	r3, [sp, #16]
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2808              		.loc 1 1108 3 is_stmt 1 view .LVU841
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 2809              		.loc 1 1108 34 is_stmt 0 view .LVU842
+ 2810 0014 4FF48063 		mov	r3, #1024
+ 2811 0018 0593     		str	r3, [sp, #20]
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2812              		.loc 1 1109 3 is_stmt 1 view .LVU843
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2813              		.loc 1 1109 9 is_stmt 0 view .LVU844
+ 2814 001a 01A9     		add	r1, sp, #4
+ 2815              	.LVL173:
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2816              		.loc 1 1109 9 view .LVU845
+ 2817 001c FFF7FEFF 		bl	SDMMC_SendCommand
+ 2818              	.LVL174:
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2819              		.loc 1 1112 3 is_stmt 1 view .LVU846
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2820              		.loc 1 1112 16 is_stmt 0 view .LVU847
+ARM GAS  /tmp/ccODg7xx.s 			page 91
+
+
+ 2821 0020 2046     		mov	r0, r4
+ 2822 0022 FFF7FEFF 		bl	SDMMC_GetCmdResp3
+ 2823              	.LVL175:
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 2824              		.loc 1 1114 3 is_stmt 1 view .LVU848
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2825              		.loc 1 1115 1 is_stmt 0 view .LVU849
+ 2826 0026 06B0     		add	sp, sp, #24
+ 2827              	.LCFI77:
+ 2828              		.cfi_def_cfa_offset 8
+ 2829              		@ sp needed
+ 2830 0028 10BD     		pop	{r4, pc}
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2831              		.loc 1 1115 1 view .LVU850
+ 2832              		.cfi_endproc
+ 2833              	.LFE178:
+ 2835              		.section	.text.SDMMC_GetCmdResp6,"ax",%progbits
+ 2836              		.align	1
+ 2837              		.global	SDMMC_GetCmdResp6
+ 2838              		.syntax unified
+ 2839              		.thumb
+ 2840              		.thumb_func
+ 2841              		.fpu fpv5-d16
+ 2843              	SDMMC_GetCmdResp6:
+ 2844              	.LVL176:
+ 2845              	.LFB184:
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t response_r1;
+ 2846              		.loc 1 1411 1 is_stmt 1 view -0
+ 2847              		.cfi_startproc
+ 2848              		@ args = 0, pretend = 0, frame = 0
+ 2849              		@ frame_needed = 0, uses_anonymous_args = 0
+1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t response_r1;
+ 2850              		.loc 1 1411 1 is_stmt 0 view .LVU852
+ 2851 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 2852              	.LCFI78:
+ 2853              		.cfi_def_cfa_offset 24
+ 2854              		.cfi_offset 3, -24
+ 2855              		.cfi_offset 4, -20
+ 2856              		.cfi_offset 5, -16
+ 2857              		.cfi_offset 6, -12
+ 2858              		.cfi_offset 7, -8
+ 2859              		.cfi_offset 14, -4
+ 2860 0002 0546     		mov	r5, r0
+ 2861 0004 0E46     		mov	r6, r1
+ 2862 0006 1746     		mov	r7, r2
+1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+ 2863              		.loc 1 1412 3 is_stmt 1 view .LVU853
+1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2864              		.loc 1 1413 3 view .LVU854
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2865              		.loc 1 1417 3 view .LVU855
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2866              		.loc 1 1417 61 is_stmt 0 view .LVU856
+ 2867 0008 234B     		ldr	r3, .L141
+ 2868 000a 1B68     		ldr	r3, [r3]
+ 2869 000c 234A     		ldr	r2, .L141+4
+ 2870              	.LVL177:
+ARM GAS  /tmp/ccODg7xx.s 			page 92
+
+
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2871              		.loc 1 1417 61 view .LVU857
+ 2872 000e A2FB0323 		umull	r2, r3, r2, r3
+ 2873 0012 5B0A     		lsrs	r3, r3, #9
+1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2874              		.loc 1 1417 12 view .LVU858
+ 2875 0014 41F28832 		movw	r2, #5000
+ 2876 0018 02FB03F3 		mul	r3, r2, r3
+ 2877              	.LVL178:
+ 2878              	.L129:
+1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2879              		.loc 1 1419 3 is_stmt 1 view .LVU859
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 2880              		.loc 1 1421 5 view .LVU860
+ 2881 001c 1A46     		mov	r2, r3
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 2882              		.loc 1 1421 14 is_stmt 0 view .LVU861
+ 2883 001e 013B     		subs	r3, r3, #1
+ 2884              	.LVL179:
+1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 2885              		.loc 1 1421 8 view .LVU862
+ 2886 0020 8AB3     		cbz	r2, .L133
+1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 2887              		.loc 1 1425 5 is_stmt 1 view .LVU863
+1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 2888              		.loc 1 1425 13 is_stmt 0 view .LVU864
+ 2889 0022 6C6B     		ldr	r4, [r5, #52]
+ 2890              	.LVL180:
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ 2891              		.loc 1 1426 9 is_stmt 1 view .LVU865
+1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2892              		.loc 1 1427 10 is_stmt 0 view .LVU866
+ 2893 0024 14F0450F 		tst	r4, #69
+ 2894 0028 F8D0     		beq	.L129
+1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ 2895              		.loc 1 1426 95 discriminator 1 view .LVU867
+ 2896 002a 14F4006F 		tst	r4, #2048
+ 2897 002e F5D1     		bne	.L129
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2898              		.loc 1 1429 3 is_stmt 1 view .LVU868
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2899              		.loc 1 1429 6 is_stmt 0 view .LVU869
+ 2900 0030 6B6B     		ldr	r3, [r5, #52]
+ 2901              	.LVL181:
+1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2902              		.loc 1 1429 5 view .LVU870
+ 2903 0032 13F0040F 		tst	r3, #4
+ 2904 0036 06D1     		bne	.L138
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2905              		.loc 1 1435 8 is_stmt 1 view .LVU871
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2906              		.loc 1 1435 11 is_stmt 0 view .LVU872
+ 2907 0038 6B6B     		ldr	r3, [r5, #52]
+1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2908              		.loc 1 1435 10 view .LVU873
+ 2909 003a 13F0010F 		tst	r3, #1
+ 2910 003e 05D0     		beq	.L131
+ARM GAS  /tmp/ccODg7xx.s 			page 93
+
+
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2911              		.loc 1 1437 5 is_stmt 1 view .LVU874
+ 2912 0040 0120     		movs	r0, #1
+ 2913              	.LVL182:
+1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2914              		.loc 1 1437 5 is_stmt 0 view .LVU875
+ 2915 0042 A863     		str	r0, [r5, #56]
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2916              		.loc 1 1439 5 is_stmt 1 view .LVU876
+1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2917              		.loc 1 1439 12 is_stmt 0 view .LVU877
+ 2918 0044 21E0     		b	.L127
+ 2919              	.LVL183:
+ 2920              	.L138:
+1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2921              		.loc 1 1431 5 is_stmt 1 view .LVU878
+ 2922 0046 0420     		movs	r0, #4
+ 2923              	.LVL184:
+1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2924              		.loc 1 1431 5 is_stmt 0 view .LVU879
+ 2925 0048 A863     		str	r0, [r5, #56]
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2926              		.loc 1 1433 5 is_stmt 1 view .LVU880
+1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2927              		.loc 1 1433 12 is_stmt 0 view .LVU881
+ 2928 004a 1EE0     		b	.L127
+ 2929              	.LVL185:
+ 2930              	.L131:
+1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2931              		.loc 1 1444 3 is_stmt 1 view .LVU882
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2932              		.loc 1 1447 3 view .LVU883
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2933              		.loc 1 1447 6 is_stmt 0 view .LVU884
+ 2934 004c 2846     		mov	r0, r5
+ 2935              	.LVL186:
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2936              		.loc 1 1447 6 view .LVU885
+ 2937 004e FFF7FEFF 		bl	SDMMC_GetCommandResponse
+ 2938              	.LVL187:
+1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2939              		.loc 1 1447 5 view .LVU886
+ 2940 0052 B042     		cmp	r0, r6
+ 2941 0054 01D0     		beq	.L139
+1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2942              		.loc 1 1449 12 view .LVU887
+ 2943 0056 0120     		movs	r0, #1
+ 2944 0058 17E0     		b	.L127
+ 2945              	.L139:
+1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2946              		.loc 1 1453 3 is_stmt 1 view .LVU888
+ 2947 005a C523     		movs	r3, #197
+ 2948 005c AB63     		str	r3, [r5, #56]
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2949              		.loc 1 1456 3 view .LVU889
+1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 2950              		.loc 1 1456 17 is_stmt 0 view .LVU890
+ARM GAS  /tmp/ccODg7xx.s 			page 94
+
+
+ 2951 005e 0021     		movs	r1, #0
+ 2952 0060 2846     		mov	r0, r5
+ 2953 0062 FFF7FEFF 		bl	SDMMC_GetResponse
+ 2954              	.LVL188:
+ 2955 0066 0346     		mov	r3, r0
+ 2956              	.LVL189:
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2957              		.loc 1 1458 3 is_stmt 1 view .LVU891
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2958              		.loc 1 1458 5 is_stmt 0 view .LVU892
+ 2959 0068 10F46040 		ands	r0, r0, #57344
+ 2960              	.LVL190:
+1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2961              		.loc 1 1458 5 view .LVU893
+ 2962 006c 08D0     		beq	.L140
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2963              		.loc 1 1464 8 is_stmt 1 view .LVU894
+1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2964              		.loc 1 1464 10 is_stmt 0 view .LVU895
+ 2965 006e 13F4804F 		tst	r3, #16384
+ 2966 0072 0BD1     		bne	.L135
+1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2967              		.loc 1 1468 8 is_stmt 1 view .LVU896
+1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 2968              		.loc 1 1468 10 is_stmt 0 view .LVU897
+ 2969 0074 13F4004F 		tst	r3, #32768
+ 2970 0078 0BD0     		beq	.L136
+1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2971              		.loc 1 1470 12 view .LVU898
+ 2972 007a 4FF48050 		mov	r0, #4096
+ 2973 007e 04E0     		b	.L127
+ 2974              	.L140:
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2975              		.loc 1 1460 5 is_stmt 1 view .LVU899
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2976              		.loc 1 1460 13 is_stmt 0 view .LVU900
+ 2977 0080 1B0C     		lsrs	r3, r3, #16
+ 2978              	.LVL191:
+1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 2979              		.loc 1 1460 11 view .LVU901
+ 2980 0082 3B80     		strh	r3, [r7]	@ movhi
+1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2981              		.loc 1 1462 5 is_stmt 1 view .LVU902
+1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2982              		.loc 1 1462 12 is_stmt 0 view .LVU903
+ 2983 0084 01E0     		b	.L127
+ 2984              	.LVL192:
+ 2985              	.L133:
+1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+ 2986              		.loc 1 1423 14 view .LVU904
+ 2987 0086 4FF00040 		mov	r0, #-2147483648
+ 2988              	.LVL193:
+ 2989              	.L127:
+1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 2990              		.loc 1 1476 1 view .LVU905
+ 2991 008a F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 2992              	.LVL194:
+ARM GAS  /tmp/ccODg7xx.s 			page 95
+
+
+ 2993              	.L135:
+1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2994              		.loc 1 1466 12 view .LVU906
+ 2995 008c 4FF40050 		mov	r0, #8192
+ 2996 0090 FBE7     		b	.L127
+ 2997              	.L136:
+1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 2998              		.loc 1 1474 12 view .LVU907
+ 2999 0092 4FF48030 		mov	r0, #65536
+ 3000 0096 F8E7     		b	.L127
+ 3001              	.L142:
+ 3002              		.align	2
+ 3003              	.L141:
+ 3004 0098 00000000 		.word	SystemCoreClock
+ 3005 009c D34D6210 		.word	274877907
+ 3006              		.cfi_endproc
+ 3007              	.LFE184:
+ 3009              		.section	.text.SDMMC_CmdSetRelAdd,"ax",%progbits
+ 3010              		.align	1
+ 3011              		.global	SDMMC_CmdSetRelAdd
+ 3012              		.syntax unified
+ 3013              		.thumb
+ 3014              		.thumb_func
+ 3015              		.fpu fpv5-d16
+ 3017              	SDMMC_CmdSetRelAdd:
+ 3018              	.LVL195:
+ 3019              	.LFB174:
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 3020              		.loc 1 1002 1 is_stmt 1 view -0
+ 3021              		.cfi_startproc
+ 3022              		@ args = 0, pretend = 0, frame = 24
+ 3023              		@ frame_needed = 0, uses_anonymous_args = 0
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 3024              		.loc 1 1002 1 is_stmt 0 view .LVU909
+ 3025 0000 70B5     		push	{r4, r5, r6, lr}
+ 3026              	.LCFI79:
+ 3027              		.cfi_def_cfa_offset 16
+ 3028              		.cfi_offset 4, -16
+ 3029              		.cfi_offset 5, -12
+ 3030              		.cfi_offset 6, -8
+ 3031              		.cfi_offset 14, -4
+ 3032 0002 86B0     		sub	sp, sp, #24
+ 3033              	.LCFI80:
+ 3034              		.cfi_def_cfa_offset 40
+ 3035 0004 0446     		mov	r4, r0
+ 3036 0006 0D46     		mov	r5, r1
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 3037              		.loc 1 1003 3 is_stmt 1 view .LVU910
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3038              		.loc 1 1004 3 view .LVU911
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+ 3039              		.loc 1 1007 3 view .LVU912
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+ 3040              		.loc 1 1007 34 is_stmt 0 view .LVU913
+ 3041 0008 0023     		movs	r3, #0
+ 3042 000a 0193     		str	r3, [sp, #4]
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ARM GAS  /tmp/ccODg7xx.s 			page 96
+
+
+ 3043              		.loc 1 1008 3 is_stmt 1 view .LVU914
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 3044              		.loc 1 1008 34 is_stmt 0 view .LVU915
+ 3045 000c 0326     		movs	r6, #3
+ 3046 000e 0296     		str	r6, [sp, #8]
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 3047              		.loc 1 1009 3 is_stmt 1 view .LVU916
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 3048              		.loc 1 1009 34 is_stmt 0 view .LVU917
+ 3049 0010 4022     		movs	r2, #64
+ 3050 0012 0392     		str	r2, [sp, #12]
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 3051              		.loc 1 1010 3 is_stmt 1 view .LVU918
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 3052              		.loc 1 1010 34 is_stmt 0 view .LVU919
+ 3053 0014 0493     		str	r3, [sp, #16]
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 3054              		.loc 1 1011 3 is_stmt 1 view .LVU920
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 3055              		.loc 1 1011 34 is_stmt 0 view .LVU921
+ 3056 0016 4FF48063 		mov	r3, #1024
+ 3057 001a 0593     		str	r3, [sp, #20]
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3058              		.loc 1 1012 3 is_stmt 1 view .LVU922
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3059              		.loc 1 1012 9 is_stmt 0 view .LVU923
+ 3060 001c 01A9     		add	r1, sp, #4
+ 3061              	.LVL196:
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3062              		.loc 1 1012 9 view .LVU924
+ 3063 001e FFF7FEFF 		bl	SDMMC_SendCommand
+ 3064              	.LVL197:
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 3065              		.loc 1 1015 3 is_stmt 1 view .LVU925
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 3066              		.loc 1 1015 16 is_stmt 0 view .LVU926
+ 3067 0022 2A46     		mov	r2, r5
+ 3068 0024 3146     		mov	r1, r6
+ 3069 0026 2046     		mov	r0, r4
+ 3070 0028 FFF7FEFF 		bl	SDMMC_GetCmdResp6
+ 3071              	.LVL198:
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 3072              		.loc 1 1017 3 is_stmt 1 view .LVU927
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 3073              		.loc 1 1018 1 is_stmt 0 view .LVU928
+ 3074 002c 06B0     		add	sp, sp, #24
+ 3075              	.LCFI81:
+ 3076              		.cfi_def_cfa_offset 16
+ 3077              		@ sp needed
+ 3078 002e 70BD     		pop	{r4, r5, r6, pc}
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 3079              		.loc 1 1018 1 view .LVU929
+ 3080              		.cfi_endproc
+ 3081              	.LFE174:
+ 3083              		.section	.text.SDMMC_GetCmdResp7,"ax",%progbits
+ 3084              		.align	1
+ 3085              		.global	SDMMC_GetCmdResp7
+ARM GAS  /tmp/ccODg7xx.s 			page 97
+
+
+ 3086              		.syntax unified
+ 3087              		.thumb
+ 3088              		.thumb_func
+ 3089              		.fpu fpv5-d16
+ 3091              	SDMMC_GetCmdResp7:
+ 3092              	.LVL199:
+ 3093              	.LFB185:
+1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+ 3094              		.loc 1 1484 1 is_stmt 1 view -0
+ 3095              		.cfi_startproc
+ 3096              		@ args = 0, pretend = 0, frame = 0
+ 3097              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3098              		@ link register save eliminated.
+1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t sta_reg;
+ 3099              		.loc 1 1484 1 is_stmt 0 view .LVU931
+ 3100 0000 0146     		mov	r1, r0
+1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   /* 8 is the number of required instructions cycles for the below loop statement.
+ 3101              		.loc 1 1485 3 is_stmt 1 view .LVU932
+1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3102              		.loc 1 1488 3 view .LVU933
+1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3103              		.loc 1 1488 61 is_stmt 0 view .LVU934
+ 3104 0002 164B     		ldr	r3, .L153
+ 3105 0004 1B68     		ldr	r3, [r3]
+ 3106 0006 164A     		ldr	r2, .L153+4
+ 3107 0008 A2FB0323 		umull	r2, r3, r2, r3
+ 3108 000c 5B0A     		lsrs	r3, r3, #9
+1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3109              		.loc 1 1488 12 view .LVU935
+ 3110 000e 41F28832 		movw	r2, #5000
+ 3111 0012 02FB03F3 		mul	r3, r2, r3
+ 3112              	.LVL200:
+ 3113              	.L147:
+1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 3114              		.loc 1 1490 3 is_stmt 1 view .LVU936
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 3115              		.loc 1 1492 5 view .LVU937
+ 3116 0016 1A46     		mov	r2, r3
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 3117              		.loc 1 1492 14 is_stmt 0 view .LVU938
+ 3118 0018 013B     		subs	r3, r3, #1
+ 3119              	.LVL201:
+1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     {
+ 3120              		.loc 1 1492 8 view .LVU939
+ 3121 001a E2B1     		cbz	r2, .L150
+1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 3122              		.loc 1 1496 5 is_stmt 1 view .LVU940
+1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ 3123              		.loc 1 1496 13 is_stmt 0 view .LVU941
+ 3124 001c 4A6B     		ldr	r2, [r1, #52]
+ 3125              	.LVL202:
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ 3126              		.loc 1 1497 9 is_stmt 1 view .LVU942
+1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 3127              		.loc 1 1498 10 is_stmt 0 view .LVU943
+ 3128 001e 12F0450F 		tst	r2, #69
+ 3129 0022 F8D0     		beq	.L147
+ARM GAS  /tmp/ccODg7xx.s 			page 98
+
+
+1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****          ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ 3130              		.loc 1 1497 95 discriminator 1 view .LVU944
+ 3131 0024 12F4006F 		tst	r2, #2048
+ 3132 0028 F5D1     		bne	.L147
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 3133              		.loc 1 1500 3 is_stmt 1 view .LVU945
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 3134              		.loc 1 1500 6 is_stmt 0 view .LVU946
+ 3135 002a 4B6B     		ldr	r3, [r1, #52]
+ 3136              	.LVL203:
+1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 3137              		.loc 1 1500 5 view .LVU947
+ 3138 002c 13F0040F 		tst	r3, #4
+ 3139 0030 0BD1     		bne	.L151
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 3140              		.loc 1 1507 8 is_stmt 1 view .LVU948
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 3141              		.loc 1 1507 11 is_stmt 0 view .LVU949
+ 3142 0032 4B6B     		ldr	r3, [r1, #52]
+1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 3143              		.loc 1 1507 10 view .LVU950
+ 3144 0034 13F00103 		ands	r3, r3, #1
+ 3145 0038 0AD1     		bne	.L152
+1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3146              		.loc 1 1517 3 is_stmt 1 view .LVU951
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 3147              		.loc 1 1519 3 view .LVU952
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 3148              		.loc 1 1519 6 is_stmt 0 view .LVU953
+ 3149 003a 486B     		ldr	r0, [r1, #52]
+ 3150              	.LVL204:
+1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   {
+ 3151              		.loc 1 1519 5 view .LVU954
+ 3152 003c 10F04000 		ands	r0, r0, #64
+ 3153 0040 0BD0     		beq	.L145
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 3154              		.loc 1 1522 5 is_stmt 1 view .LVU955
+ 3155 0042 4022     		movs	r2, #64
+ 3156              	.LVL205:
+1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 3157              		.loc 1 1522 5 is_stmt 0 view .LVU956
+ 3158 0044 8A63     		str	r2, [r1, #56]
+1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3159              		.loc 1 1525 10 view .LVU957
+ 3160 0046 1846     		mov	r0, r3
+ 3161 0048 7047     		bx	lr
+ 3162              	.LVL206:
+ 3163              	.L151:
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 3164              		.loc 1 1503 5 is_stmt 1 view .LVU958
+ 3165 004a 0420     		movs	r0, #4
+ 3166              	.LVL207:
+1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 3167              		.loc 1 1503 5 is_stmt 0 view .LVU959
+ 3168 004c 8863     		str	r0, [r1, #56]
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 3169              		.loc 1 1505 5 is_stmt 1 view .LVU960
+ARM GAS  /tmp/ccODg7xx.s 			page 99
+
+
+1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 3170              		.loc 1 1505 12 is_stmt 0 view .LVU961
+ 3171 004e 7047     		bx	lr
+ 3172              	.LVL208:
+ 3173              	.L152:
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 3174              		.loc 1 1510 5 is_stmt 1 view .LVU962
+ 3175 0050 0120     		movs	r0, #1
+ 3176              	.LVL209:
+1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     
+ 3177              		.loc 1 1510 5 is_stmt 0 view .LVU963
+ 3178 0052 8863     		str	r0, [r1, #56]
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 3179              		.loc 1 1512 5 is_stmt 1 view .LVU964
+1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   }
+ 3180              		.loc 1 1512 12 is_stmt 0 view .LVU965
+ 3181 0054 7047     		bx	lr
+ 3182              	.LVL210:
+ 3183              	.L150:
+1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****     }
+ 3184              		.loc 1 1494 14 view .LVU966
+ 3185 0056 4FF00040 		mov	r0, #-2147483648
+ 3186              	.LVL211:
+ 3187              	.L145:
+1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 3188              		.loc 1 1527 1 view .LVU967
+ 3189 005a 7047     		bx	lr
+ 3190              	.L154:
+ 3191              		.align	2
+ 3192              	.L153:
+ 3193 005c 00000000 		.word	SystemCoreClock
+ 3194 0060 D34D6210 		.word	274877907
+ 3195              		.cfi_endproc
+ 3196              	.LFE185:
+ 3198              		.section	.text.SDMMC_CmdOperCond,"ax",%progbits
+ 3199              		.align	1
+ 3200              		.global	SDMMC_CmdOperCond
+ 3201              		.syntax unified
+ 3202              		.thumb
+ 3203              		.thumb_func
+ 3204              		.fpu fpv5-d16
+ 3206              	SDMMC_CmdOperCond:
+ 3207              	.LVL212:
+ 3208              	.LFB167:
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 3209              		.loc 1 822 1 is_stmt 1 view -0
+ 3210              		.cfi_startproc
+ 3211              		@ args = 0, pretend = 0, frame = 24
+ 3212              		@ frame_needed = 0, uses_anonymous_args = 0
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+ 3213              		.loc 1 822 1 is_stmt 0 view .LVU969
+ 3214 0000 10B5     		push	{r4, lr}
+ 3215              	.LCFI82:
+ 3216              		.cfi_def_cfa_offset 8
+ 3217              		.cfi_offset 4, -8
+ 3218              		.cfi_offset 14, -4
+ 3219 0002 86B0     		sub	sp, sp, #24
+ARM GAS  /tmp/ccODg7xx.s 			page 100
+
+
+ 3220              	.LCFI83:
+ 3221              		.cfi_def_cfa_offset 32
+ 3222 0004 0446     		mov	r4, r0
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   uint32_t errorstate;
+ 3223              		.loc 1 823 3 is_stmt 1 view .LVU970
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3224              		.loc 1 824 3 view .LVU971
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+ 3225              		.loc 1 831 3 view .LVU972
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+ 3226              		.loc 1 831 34 is_stmt 0 view .LVU973
+ 3227 0006 4FF4D573 		mov	r3, #426
+ 3228 000a 0193     		str	r3, [sp, #4]
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 3229              		.loc 1 832 3 is_stmt 1 view .LVU974
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+ 3230              		.loc 1 832 34 is_stmt 0 view .LVU975
+ 3231 000c 0823     		movs	r3, #8
+ 3232 000e 0293     		str	r3, [sp, #8]
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 3233              		.loc 1 833 3 is_stmt 1 view .LVU976
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ 3234              		.loc 1 833 34 is_stmt 0 view .LVU977
+ 3235 0010 4023     		movs	r3, #64
+ 3236 0012 0393     		str	r3, [sp, #12]
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 3237              		.loc 1 834 3 is_stmt 1 view .LVU978
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+ 3238              		.loc 1 834 34 is_stmt 0 view .LVU979
+ 3239 0014 0023     		movs	r3, #0
+ 3240 0016 0493     		str	r3, [sp, #16]
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 3241              		.loc 1 835 3 is_stmt 1 view .LVU980
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+ 3242              		.loc 1 835 34 is_stmt 0 view .LVU981
+ 3243 0018 4FF48063 		mov	r3, #1024
+ 3244 001c 0593     		str	r3, [sp, #20]
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3245              		.loc 1 836 3 is_stmt 1 view .LVU982
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c ****   
+ 3246              		.loc 1 836 9 is_stmt 0 view .LVU983
+ 3247 001e 01A9     		add	r1, sp, #4
+ 3248 0020 FFF7FEFF 		bl	SDMMC_SendCommand
+ 3249              	.LVL213:
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 3250              		.loc 1 839 3 is_stmt 1 view .LVU984
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 3251              		.loc 1 839 16 is_stmt 0 view .LVU985
+ 3252 0024 2046     		mov	r0, r4
+ 3253 0026 FFF7FEFF 		bl	SDMMC_GetCmdResp7
+ 3254              	.LVL214:
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }
+ 3255              		.loc 1 841 3 is_stmt 1 view .LVU986
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 3256              		.loc 1 842 1 is_stmt 0 view .LVU987
+ 3257 002a 06B0     		add	sp, sp, #24
+ 3258              	.LCFI84:
+ARM GAS  /tmp/ccODg7xx.s 			page 101
+
+
+ 3259              		.cfi_def_cfa_offset 8
+ 3260              		@ sp needed
+ 3261 002c 10BD     		pop	{r4, pc}
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** 
+ 3262              		.loc 1 842 1 view .LVU988
+ 3263              		.cfi_endproc
+ 3264              	.LFE167:
+ 3266              		.text
+ 3267              	.Letext0:
+ 3268              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 3269              		.file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 3270              		.file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h"
+ 3271              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h"
+ 3272              		.file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h"
+ARM GAS  /tmp/ccODg7xx.s 			page 102
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_ll_sdmmc.c
+     /tmp/ccODg7xx.s:17     .text.SDMMC_GetCmdError:0000000000000000 $t
+     /tmp/ccODg7xx.s:24     .text.SDMMC_GetCmdError:0000000000000000 SDMMC_GetCmdError
+     /tmp/ccODg7xx.s:80     .text.SDMMC_GetCmdError:0000000000000030 $d
+     /tmp/ccODg7xx.s:86     .text.SDMMC_Init:0000000000000000 $t
+     /tmp/ccODg7xx.s:93     .text.SDMMC_Init:0000000000000000 SDMMC_Init
+     /tmp/ccODg7xx.s:157    .text.SDMMC_Init:0000000000000030 $d
+     /tmp/ccODg7xx.s:162    .text.SDMMC_ReadFIFO:0000000000000000 $t
+     /tmp/ccODg7xx.s:169    .text.SDMMC_ReadFIFO:0000000000000000 SDMMC_ReadFIFO
+     /tmp/ccODg7xx.s:187    .text.SDMMC_WriteFIFO:0000000000000000 $t
+     /tmp/ccODg7xx.s:194    .text.SDMMC_WriteFIFO:0000000000000000 SDMMC_WriteFIFO
+     /tmp/ccODg7xx.s:217    .text.SDMMC_PowerState_ON:0000000000000000 $t
+     /tmp/ccODg7xx.s:224    .text.SDMMC_PowerState_ON:0000000000000000 SDMMC_PowerState_ON
+     /tmp/ccODg7xx.s:246    .text.SDMMC_PowerState_OFF:0000000000000000 $t
+     /tmp/ccODg7xx.s:253    .text.SDMMC_PowerState_OFF:0000000000000000 SDMMC_PowerState_OFF
+     /tmp/ccODg7xx.s:276    .text.SDMMC_GetPowerState:0000000000000000 $t
+     /tmp/ccODg7xx.s:283    .text.SDMMC_GetPowerState:0000000000000000 SDMMC_GetPowerState
+     /tmp/ccODg7xx.s:302    .text.SDMMC_SendCommand:0000000000000000 $t
+     /tmp/ccODg7xx.s:309    .text.SDMMC_SendCommand:0000000000000000 SDMMC_SendCommand
+     /tmp/ccODg7xx.s:363    .text.SDMMC_SendCommand:0000000000000020 $d
+     /tmp/ccODg7xx.s:368    .text.SDMMC_GetCommandResponse:0000000000000000 $t
+     /tmp/ccODg7xx.s:375    .text.SDMMC_GetCommandResponse:0000000000000000 SDMMC_GetCommandResponse
+     /tmp/ccODg7xx.s:394    .text.SDMMC_GetResponse:0000000000000000 $t
+     /tmp/ccODg7xx.s:401    .text.SDMMC_GetResponse:0000000000000000 SDMMC_GetResponse
+     /tmp/ccODg7xx.s:425    .text.SDMMC_ConfigData:0000000000000000 $t
+     /tmp/ccODg7xx.s:432    .text.SDMMC_ConfigData:0000000000000000 SDMMC_ConfigData
+     /tmp/ccODg7xx.s:490    .text.SDMMC_GetDataCounter:0000000000000000 $t
+     /tmp/ccODg7xx.s:497    .text.SDMMC_GetDataCounter:0000000000000000 SDMMC_GetDataCounter
+     /tmp/ccODg7xx.s:515    .text.SDMMC_GetFIFOCount:0000000000000000 $t
+     /tmp/ccODg7xx.s:522    .text.SDMMC_GetFIFOCount:0000000000000000 SDMMC_GetFIFOCount
+     /tmp/ccODg7xx.s:540    .text.SDMMC_SetSDMMCReadWaitMode:0000000000000000 $t
+     /tmp/ccODg7xx.s:547    .text.SDMMC_SetSDMMCReadWaitMode:0000000000000000 SDMMC_SetSDMMCReadWaitMode
+     /tmp/ccODg7xx.s:571    .text.SDMMC_CmdGoIdleState:0000000000000000 $t
+     /tmp/ccODg7xx.s:578    .text.SDMMC_CmdGoIdleState:0000000000000000 SDMMC_CmdGoIdleState
+     /tmp/ccODg7xx.s:636    .text.SDMMC_GetCmdResp1:0000000000000000 $t
+     /tmp/ccODg7xx.s:643    .text.SDMMC_GetCmdResp1:0000000000000000 SDMMC_GetCmdResp1
+     /tmp/ccODg7xx.s:921    .text.SDMMC_GetCmdResp1:0000000000000148 $d
+     /tmp/ccODg7xx.s:928    .text.SDMMC_CmdBlockLength:0000000000000000 $t
+     /tmp/ccODg7xx.s:935    .text.SDMMC_CmdBlockLength:0000000000000000 SDMMC_CmdBlockLength
+     /tmp/ccODg7xx.s:1000   .text.SDMMC_CmdReadSingleBlock:0000000000000000 $t
+     /tmp/ccODg7xx.s:1007   .text.SDMMC_CmdReadSingleBlock:0000000000000000 SDMMC_CmdReadSingleBlock
+     /tmp/ccODg7xx.s:1072   .text.SDMMC_CmdReadMultiBlock:0000000000000000 $t
+     /tmp/ccODg7xx.s:1079   .text.SDMMC_CmdReadMultiBlock:0000000000000000 SDMMC_CmdReadMultiBlock
+     /tmp/ccODg7xx.s:1144   .text.SDMMC_CmdWriteSingleBlock:0000000000000000 $t
+     /tmp/ccODg7xx.s:1151   .text.SDMMC_CmdWriteSingleBlock:0000000000000000 SDMMC_CmdWriteSingleBlock
+     /tmp/ccODg7xx.s:1216   .text.SDMMC_CmdWriteMultiBlock:0000000000000000 $t
+     /tmp/ccODg7xx.s:1223   .text.SDMMC_CmdWriteMultiBlock:0000000000000000 SDMMC_CmdWriteMultiBlock
+     /tmp/ccODg7xx.s:1288   .text.SDMMC_CmdSDEraseStartAdd:0000000000000000 $t
+     /tmp/ccODg7xx.s:1295   .text.SDMMC_CmdSDEraseStartAdd:0000000000000000 SDMMC_CmdSDEraseStartAdd
+     /tmp/ccODg7xx.s:1360   .text.SDMMC_CmdSDEraseEndAdd:0000000000000000 $t
+     /tmp/ccODg7xx.s:1367   .text.SDMMC_CmdSDEraseEndAdd:0000000000000000 SDMMC_CmdSDEraseEndAdd
+     /tmp/ccODg7xx.s:1432   .text.SDMMC_CmdEraseStartAdd:0000000000000000 $t
+     /tmp/ccODg7xx.s:1439   .text.SDMMC_CmdEraseStartAdd:0000000000000000 SDMMC_CmdEraseStartAdd
+     /tmp/ccODg7xx.s:1504   .text.SDMMC_CmdEraseEndAdd:0000000000000000 $t
+     /tmp/ccODg7xx.s:1511   .text.SDMMC_CmdEraseEndAdd:0000000000000000 SDMMC_CmdEraseEndAdd
+     /tmp/ccODg7xx.s:1576   .text.SDMMC_CmdErase:0000000000000000 $t
+ARM GAS  /tmp/ccODg7xx.s 			page 103
+
+
+     /tmp/ccODg7xx.s:1583   .text.SDMMC_CmdErase:0000000000000000 SDMMC_CmdErase
+     /tmp/ccODg7xx.s:1646   .text.SDMMC_CmdStopTransfer:0000000000000000 $t
+     /tmp/ccODg7xx.s:1653   .text.SDMMC_CmdStopTransfer:0000000000000000 SDMMC_CmdStopTransfer
+     /tmp/ccODg7xx.s:1716   .text.SDMMC_CmdStopTransfer:0000000000000030 $d
+     /tmp/ccODg7xx.s:1721   .text.SDMMC_CmdSelDesel:0000000000000000 $t
+     /tmp/ccODg7xx.s:1728   .text.SDMMC_CmdSelDesel:0000000000000000 SDMMC_CmdSelDesel
+     /tmp/ccODg7xx.s:1791   .text.SDMMC_CmdAppCommand:0000000000000000 $t
+     /tmp/ccODg7xx.s:1798   .text.SDMMC_CmdAppCommand:0000000000000000 SDMMC_CmdAppCommand
+     /tmp/ccODg7xx.s:1863   .text.SDMMC_CmdBusWidth:0000000000000000 $t
+     /tmp/ccODg7xx.s:1870   .text.SDMMC_CmdBusWidth:0000000000000000 SDMMC_CmdBusWidth
+     /tmp/ccODg7xx.s:1935   .text.SDMMC_CmdSendSCR:0000000000000000 $t
+     /tmp/ccODg7xx.s:1942   .text.SDMMC_CmdSendSCR:0000000000000000 SDMMC_CmdSendSCR
+     /tmp/ccODg7xx.s:2005   .text.SDMMC_CmdSetRelAddMmc:0000000000000000 $t
+     /tmp/ccODg7xx.s:2012   .text.SDMMC_CmdSetRelAddMmc:0000000000000000 SDMMC_CmdSetRelAddMmc
+     /tmp/ccODg7xx.s:2078   .text.SDMMC_CmdSendStatus:0000000000000000 $t
+     /tmp/ccODg7xx.s:2085   .text.SDMMC_CmdSendStatus:0000000000000000 SDMMC_CmdSendStatus
+     /tmp/ccODg7xx.s:2150   .text.SDMMC_CmdStatusRegister:0000000000000000 $t
+     /tmp/ccODg7xx.s:2157   .text.SDMMC_CmdStatusRegister:0000000000000000 SDMMC_CmdStatusRegister
+     /tmp/ccODg7xx.s:2220   .text.SDMMC_CmdSwitch:0000000000000000 $t
+     /tmp/ccODg7xx.s:2227   .text.SDMMC_CmdSwitch:0000000000000000 SDMMC_CmdSwitch
+     /tmp/ccODg7xx.s:2292   .text.SDMMC_CmdSendEXTCSD:0000000000000000 $t
+     /tmp/ccODg7xx.s:2299   .text.SDMMC_CmdSendEXTCSD:0000000000000000 SDMMC_CmdSendEXTCSD
+     /tmp/ccODg7xx.s:2364   .text.SDMMC_GetCmdResp2:0000000000000000 $t
+     /tmp/ccODg7xx.s:2371   .text.SDMMC_GetCmdResp2:0000000000000000 SDMMC_GetCmdResp2
+     /tmp/ccODg7xx.s:2460   .text.SDMMC_GetCmdResp2:0000000000000054 $d
+     /tmp/ccODg7xx.s:2466   .text.SDMMC_CmdSendCID:0000000000000000 $t
+     /tmp/ccODg7xx.s:2473   .text.SDMMC_CmdSendCID:0000000000000000 SDMMC_CmdSendCID
+     /tmp/ccODg7xx.s:2533   .text.SDMMC_CmdSendCSD:0000000000000000 $t
+     /tmp/ccODg7xx.s:2540   .text.SDMMC_CmdSendCSD:0000000000000000 SDMMC_CmdSendCSD
+     /tmp/ccODg7xx.s:2602   .text.SDMMC_GetCmdResp3:0000000000000000 $t
+     /tmp/ccODg7xx.s:2609   .text.SDMMC_GetCmdResp3:0000000000000000 SDMMC_GetCmdResp3
+     /tmp/ccODg7xx.s:2684   .text.SDMMC_GetCmdResp3:0000000000000044 $d
+     /tmp/ccODg7xx.s:2690   .text.SDMMC_CmdAppOperCommand:0000000000000000 $t
+     /tmp/ccODg7xx.s:2697   .text.SDMMC_CmdAppOperCommand:0000000000000000 SDMMC_CmdAppOperCommand
+     /tmp/ccODg7xx.s:2762   .text.SDMMC_CmdAppOperCommand:0000000000000030 $d
+     /tmp/ccODg7xx.s:2767   .text.SDMMC_CmdOpCondition:0000000000000000 $t
+     /tmp/ccODg7xx.s:2774   .text.SDMMC_CmdOpCondition:0000000000000000 SDMMC_CmdOpCondition
+     /tmp/ccODg7xx.s:2836   .text.SDMMC_GetCmdResp6:0000000000000000 $t
+     /tmp/ccODg7xx.s:2843   .text.SDMMC_GetCmdResp6:0000000000000000 SDMMC_GetCmdResp6
+     /tmp/ccODg7xx.s:3004   .text.SDMMC_GetCmdResp6:0000000000000098 $d
+     /tmp/ccODg7xx.s:3010   .text.SDMMC_CmdSetRelAdd:0000000000000000 $t
+     /tmp/ccODg7xx.s:3017   .text.SDMMC_CmdSetRelAdd:0000000000000000 SDMMC_CmdSetRelAdd
+     /tmp/ccODg7xx.s:3084   .text.SDMMC_GetCmdResp7:0000000000000000 $t
+     /tmp/ccODg7xx.s:3091   .text.SDMMC_GetCmdResp7:0000000000000000 SDMMC_GetCmdResp7
+     /tmp/ccODg7xx.s:3193   .text.SDMMC_GetCmdResp7:000000000000005c $d
+     /tmp/ccODg7xx.s:3199   .text.SDMMC_CmdOperCond:0000000000000000 $t
+     /tmp/ccODg7xx.s:3206   .text.SDMMC_CmdOperCond:0000000000000000 SDMMC_CmdOperCond
+
+UNDEFINED SYMBOLS
+SystemCoreClock
diff --git a/build/stm32f7xx_ll_sdmmc.o b/build/stm32f7xx_ll_sdmmc.o
new file mode 100644
index 0000000..1a52482
Binary files /dev/null and b/build/stm32f7xx_ll_sdmmc.o differ
diff --git a/build/stm32f7xx_ll_spi.d b/build/stm32f7xx_ll_spi.d
new file mode 100644
index 0000000..dbe9ddb
--- /dev/null
+++ b/build/stm32f7xx_ll_spi.d
@@ -0,0 +1,70 @@
+build/stm32f7xx_ll_spi.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
diff --git a/build/stm32f7xx_ll_spi.lst b/build/stm32f7xx_ll_spi.lst
new file mode 100644
index 0000000..08175b7
--- /dev/null
+++ b/build/stm32f7xx_ll_spi.lst
@@ -0,0 +1,5257 @@
+ARM GAS  /tmp/cc532wt1.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_ll_spi.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.LL_SPI_DeInit,"ax",%progbits
+  17              		.align	1
+  18              		.global	LL_SPI_DeInit
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	LL_SPI_DeInit:
+  26              	.LVL0:
+  27              	.LFB451:
+  28              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @file    stm32f7xx_ll_spi.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @brief   SPI LL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(USE_FULL_LL_DRIVER)
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Includes ------------------------------------------------------------------*/
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #include "stm32f7xx_ll_spi.h"
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #include "stm32f7xx_ll_bus.h"
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #include "stm32f7xx_ll_rcc.h"
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #ifdef  USE_FULL_ASSERT
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #include "stm32_assert.h"
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #else
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define assert_param(expr) ((void)0U)
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* USE_FULL_ASSERT */
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ARM GAS  /tmp/cc532wt1.s 			page 2
+
+
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup STM32F7xx_LL_Driver
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @{
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defin
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup SPI_LL
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @{
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private types -------------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private variables ---------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private constants ---------------------------------------------------------*/
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @defgroup SPI_LL_Private_Constants SPI Private Constants
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @{
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* SPI registers Masks */
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                             SPI_CR1_BIDIMODE)
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @}
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private macros ------------------------------------------------------------*/
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @defgroup SPI_LL_Private_Macros SPI Private Macros
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @{
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                                  || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                    || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                        || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+ARM GAS  /tmp/cc532wt1.s 			page 3
+
+
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                     || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT)          \
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                   || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                   || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                        || ((__VALUE__) == LL_SPI_MSB_FIRST))
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                              || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @}
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private function prototypes -----------------------------------------------*/
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Exported functions --------------------------------------------------------*/
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup SPI_LL_Exported_Functions
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @{
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup SPI_LL_EF_Init
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @{
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @brief  De-initialize the SPI registers to their default reset values.
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @param  SPIx SPI Instance
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @retval An ErrorStatus enumeration value:
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *          - SUCCESS: SPI registers are de-initialized
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *          - ERROR: SPI registers are not de-initialized
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** {
+  29              		.loc 1 134 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+  34              		.loc 1 134 1 is_stmt 0 view .LVU1
+  35 0000 0346     		mov	r3, r0
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   ErrorStatus status = ERROR;
+  36              		.loc 1 135 3 is_stmt 1 view .LVU2
+  37              	.LVL1:
+ARM GAS  /tmp/cc532wt1.s 			page 4
+
+
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   /* Check the parameters */
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+  38              		.loc 1 138 3 view .LVU3
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI1)
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   if (SPIx == SPI1)
+  39              		.loc 1 141 3 view .LVU4
+  40              		.loc 1 141 6 is_stmt 0 view .LVU5
+  41 0002 2D4A     		ldr	r2, .L15
+  42 0004 9042     		cmp	r0, r2
+  43 0006 10D0     		beq	.L9
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  44              		.loc 1 135 15 view .LVU6
+  45 0008 0120     		movs	r0, #1
+  46              	.LVL2:
+  47              	.L2:
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   {
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Force reset of SPI clock */
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Release reset of SPI clock */
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     status = SUCCESS;
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI1 */
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI2)
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   if (SPIx == SPI2)
+  48              		.loc 1 153 3 is_stmt 1 view .LVU7
+  49              		.loc 1 153 6 is_stmt 0 view .LVU8
+  50 000a 2C4A     		ldr	r2, .L15+4
+  51 000c 9342     		cmp	r3, r2
+  52 000e 18D0     		beq	.L10
+  53              	.LVL3:
+  54              	.L3:
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   {
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Force reset of SPI clock */
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Release reset of SPI clock */
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     status = SUCCESS;
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI2 */
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI3)
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   if (SPIx == SPI3)
+  55              		.loc 1 165 3 is_stmt 1 view .LVU9
+  56              		.loc 1 165 6 is_stmt 0 view .LVU10
+  57 0010 2B4A     		ldr	r2, .L15+8
+  58 0012 9342     		cmp	r3, r2
+  59 0014 21D0     		beq	.L11
+  60              	.LVL4:
+  61              	.L4:
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   {
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Force reset of SPI clock */
+ARM GAS  /tmp/cc532wt1.s 			page 5
+
+
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Release reset of SPI clock */
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     status = SUCCESS;
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI3 */
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI4)
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   if (SPIx == SPI4)
+  62              		.loc 1 177 3 is_stmt 1 view .LVU11
+  63              		.loc 1 177 6 is_stmt 0 view .LVU12
+  64 0016 2B4A     		ldr	r2, .L15+12
+  65 0018 9342     		cmp	r3, r2
+  66 001a 2AD0     		beq	.L12
+  67              	.LVL5:
+  68              	.L5:
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   {
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Force reset of SPI clock */
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Release reset of SPI clock */
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     status = SUCCESS;
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI4 */
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI5)
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   if (SPIx == SPI5)
+  69              		.loc 1 189 3 is_stmt 1 view .LVU13
+  70              		.loc 1 189 6 is_stmt 0 view .LVU14
+  71 001c 2A4A     		ldr	r2, .L15+16
+  72 001e 9342     		cmp	r3, r2
+  73 0020 33D0     		beq	.L13
+  74              	.LVL6:
+  75              	.L6:
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   {
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Force reset of SPI clock */
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Release reset of SPI clock */
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     status = SUCCESS;
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI5 */
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI6)
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   if (SPIx == SPI6)
+  76              		.loc 1 201 3 is_stmt 1 view .LVU15
+  77              		.loc 1 201 6 is_stmt 0 view .LVU16
+  78 0022 2A4A     		ldr	r2, .L15+20
+  79 0024 9342     		cmp	r3, r2
+  80 0026 3CD0     		beq	.L14
+  81              	.LVL7:
+  82              	.L7:
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   {
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Force reset of SPI clock */
+ARM GAS  /tmp/cc532wt1.s 			page 6
+
+
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Release reset of SPI clock */
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     status = SUCCESS;
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI6 */
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   return status;
+  83              		.loc 1 213 3 is_stmt 1 view .LVU17
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** }
+  84              		.loc 1 214 1 is_stmt 0 view .LVU18
+  85 0028 7047     		bx	lr
+  86              	.LVL8:
+  87              	.L9:
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+  88              		.loc 1 144 5 is_stmt 1 view .LVU19
+  89              	.LBB34:
+  90              	.LBI34:
+  91              		.file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @file    stm32f7xx_ll_bus.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief   Header file of BUS LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @verbatim
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****                       ##### RCC Limitations #####
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ==============================================================================
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       A delay between an RCC peripheral clock enable and the effective peripheral 
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       enabling should be taken into account in order to manage the peripheral read/write 
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       from/to registers.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (+) This delay depends on the peripheral mapping.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****         (++) AHB & APB peripherals, 1 dummy read is necessary
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       Workarounds:
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @endverbatim
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @attention
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * Copyright (c) 2017 STMicroelectronics.
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * All rights reserved.
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * This software is licensed under terms that can be found in the LICENSE file in
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * the root directory of this software component.
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H
+ARM GAS  /tmp/cc532wt1.s 			page 7
+
+
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" {
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h"
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC)
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ)
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK)
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM         RCC_AHB1ENR_DTCMRAMEN
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D)
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH)
+ARM GAS  /tmp/cc532wt1.s 			page 8
+
+
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI             RCC_AHB1LPENR_AXILPEN
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI)
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG)
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG           RCC_AHB2ENR_JPEGEN
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) 
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES)
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH)
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
+ARM GAS  /tmp/cc532wt1.s 			page 9
+
+
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX)
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4)
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4           RCC_APB1ENR_I2C4EN
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2)
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3)
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC)
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN)
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCEN
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1       RCC_APB2ENR_SDMMC1EN
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2)
+ARM GAS  /tmp/cc532wt1.s 			page 10
+
+
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2       RCC_APB2ENR_SDMMC2EN
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6)
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC)
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI)
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0)
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS)
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO         RCC_APB2ENR_MDIOEN
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC)
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC      RCC_APB2ENR_OTGPHYCEN
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB1 peripherals clock.
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\n
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\n
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\n
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\n
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\n
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\n
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\n
+ARM GAS  /tmp/cc532wt1.s 			page 11
+
+
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\n
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\n
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\n
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\n
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\n
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\n
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\n
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\n
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\n
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\n
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\n
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\n
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\n
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1ENR, Periphs);
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB1 peripheral clock is enabled or not
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\n
+ARM GAS  /tmp/cc532wt1.s 			page 12
+
+
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\n
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\n
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\n
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_IsEnabledClock
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB1 peripherals clock.
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\n
+ARM GAS  /tmp/cc532wt1.s 			page 13
+
+
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\n
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\n
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\n
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\n
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\n
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\n
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\n
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\n
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\n
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\n
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\n
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\n
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\n
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\n
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\n
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\n
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\n
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\n
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\n
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_DisableClock
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1ENR, Periphs);
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB1 peripherals reset.
+ARM GAS  /tmp/cc532wt1.s 			page 14
+
+
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\n
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\n
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\n
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\n
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\n
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\n
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\n
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\n
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\n
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\n
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\n
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\n
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\n
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1RSTR, Periphs);
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB1 peripherals reset.
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\n
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\n
+ARM GAS  /tmp/cc532wt1.s 			page 15
+
+
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\n
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\n
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\n
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB1 peripheral clocks in low-power mode
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    AXILPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DTCMRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+ARM GAS  /tmp/cc532wt1.s 			page 16
+
+
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_EnableClockLowPower\n
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_EnableClockLowPower\n
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockLowPower
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_AXI
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1LPENR, Periphs);
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB1 peripheral clocks in low-power mode
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ARM GAS  /tmp/cc532wt1.s 			page 17
+
+
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    AXILPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DTCMRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_DisableClockLowPower\n
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_DisableClockLowPower\n
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockLowPower
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_AXI
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1LPENR, Periphs);
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ARM GAS  /tmp/cc532wt1.s 			page 18
+
+
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB2 peripherals clock.
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_EnableClock\n
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_EnableClock\n
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_EnableClock\n
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_EnableClock\n
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_EnableClock\n
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_EnableClock\n
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_EnableClock
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2ENR, Periphs);
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB2 peripheral clock is enabled or not
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_IsEnabledClock\n
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_IsEnabledClock\n
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_IsEnabledClock
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ARM GAS  /tmp/cc532wt1.s 			page 19
+
+
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB2 peripherals clock.
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_DisableClock\n
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_DisableClock\n
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_DisableClock\n
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_DisableClock\n
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_DisableClock\n
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_DisableClock\n
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_DisableClock
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2ENR, Periphs);
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB2 peripherals reset.
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ForceReset\n
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     JPEGRST      LL_AHB2_GRP1_ForceReset\n
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ForceReset\n
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ForceReset\n
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ForceReset\n
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ForceReset\n
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ForceReset
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ARM GAS  /tmp/cc532wt1.s 			page 20
+
+
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2RSTR, Periphs);
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB2 peripherals reset.
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ReleaseReset\n
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     JPEGRST      LL_AHB2_GRP1_ReleaseReset\n
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ReleaseReset\n
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ReleaseReset\n
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ReleaseReset\n
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ReleaseReset\n
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ReleaseReset
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB2 peripheral clocks in low-power mode
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    JPEGLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_EnableClockLowPower
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2LPENR, Periphs);
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
+ARM GAS  /tmp/cc532wt1.s 			page 21
+
+
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB2 peripheral clocks in low-power mode
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    JPEGLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_DisableClockLowPower
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2LPENR, Periphs);
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB3 peripherals clock.
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3ENR, Periphs);
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ARM GAS  /tmp/cc532wt1.s 			page 22
+
+
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB3 peripheral clock is enabled or not
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB3 peripherals clock.
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3ENR, Periphs);
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB3 peripherals reset.
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3RSTR, Periphs);
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB3 peripherals reset.
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ARM GAS  /tmp/cc532wt1.s 			page 23
+
+
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB3 peripheral clocks in low-power mode
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockLowPower\n
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockLowPower
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3LPENR, Periphs);
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB3 peripheral clocks in low-power mode
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockLowPower\n
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockLowPower
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3LPENR, Periphs);
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB1 peripherals clock.
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
+ARM GAS  /tmp/cc532wt1.s 			page 24
+
+
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\n
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\n
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_EnableClock\n
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_EnableClock\n
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_EnableClock\n
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_EnableClock\n
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_EnableClock\n
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_EnableClock\n
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_EnableClock\n
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_EnableClock\n
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\n
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\n
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_EnableClock\n
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_EnableClock\n
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_EnableClock
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ARM GAS  /tmp/cc532wt1.s 			page 25
+
+
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1ENR, Periphs);
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if APB1 peripheral clock is enabled or not
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_IsEnabledClock\n
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_IsEnabledClock\n
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_IsEnabledClock\n
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_IsEnabledClock\n
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\n
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\n
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_IsEnabledClock\n
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_IsEnabledClock
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ARM GAS  /tmp/cc532wt1.s 			page 26
+
+
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable APB1 peripherals clock.
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\n
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\n
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_DisableClock\n
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_DisableClock\n
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_DisableClock\n
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
+ARM GAS  /tmp/cc532wt1.s 			page 27
+
+
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_DisableClock\n
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_DisableClock\n
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_DisableClock\n
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_DisableClock\n
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_DisableClock\n
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\n
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\n
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_DisableClock\n
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_DisableClock\n
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_DisableClock
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1ENR, Periphs);
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force APB1 peripherals reset.
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\n
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\n
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ForceReset\n
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ForceReset\n
+ARM GAS  /tmp/cc532wt1.s 			page 28
+
+
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\n
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\n
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ForceReset\n
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ForceReset\n
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ForceReset\n
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset\n
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\n
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\n
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ForceReset\n
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ForceReset\n
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\n
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART3RST      LL_APB1_GRP1_ForceReset\n
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART4RST       LL_APB1_GRP1_ForceReset\n
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART5RST       LL_APB1_GRP1_ForceReset\n
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\n
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\n
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\n
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C4RST        LL_APB1_GRP1_ForceReset\n
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ForceReset\n
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ForceReset\n
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ForceReset\n
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CECRST         LL_APB1_GRP1_ForceReset\n
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\n
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\n
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART7RST       LL_APB1_GRP1_ForceReset\n
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART8RST       LL_APB1_GRP1_ForceReset
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+ARM GAS  /tmp/cc532wt1.s 			page 29
+
+
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1RSTR, Periphs);
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release APB1 peripherals reset.
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ReleaseReset\n
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ReleaseReset\n
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ReleaseReset\n
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ReleaseReset\n
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ReleaseReset\n
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset\n
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\n
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ReleaseReset\n
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ReleaseReset\n
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\n
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART3RST      LL_APB1_GRP1_ReleaseReset\n
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART4RST       LL_APB1_GRP1_ReleaseReset\n
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART5RST       LL_APB1_GRP1_ReleaseReset\n
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C4RST        LL_APB1_GRP1_ReleaseReset\n
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ReleaseReset\n
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ReleaseReset\n
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ReleaseReset\n
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CECRST         LL_APB1_GRP1_ReleaseReset\n
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\n
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\n
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART7RST       LL_APB1_GRP1_ReleaseReset\n
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART8RST       LL_APB1_GRP1_ReleaseReset
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ARM GAS  /tmp/cc532wt1.s 			page 30
+
+
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1RSTR, Periphs);
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB1 peripheral clocks in low-power mode
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_EnableClockLowPower\n
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CECLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     DACLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     RTCLPEN         LL_APB1_GRP1_EnableClockLowPower
+ARM GAS  /tmp/cc532wt1.s 			page 31
+
+
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1LPENR, Periphs);
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable APB1 peripheral clocks in low-power mode
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+ARM GAS  /tmp/cc532wt1.s 			page 32
+
+
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_DisableClockLowPower\n
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CECLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     DACLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     RTCLPEN         LL_APB1_GRP1_DisableClockLowPower
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ARM GAS  /tmp/cc532wt1.s 			page 33
+
+
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1LPENR, Periphs);
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB2 peripherals clock.
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_EnableClock\n
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM8EN        LL_APB2_GRP1_EnableClock\n
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART1EN      LL_APB2_GRP1_EnableClock\n
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART6EN      LL_APB2_GRP1_EnableClock\n
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC1EN        LL_APB2_GRP1_EnableClock\n
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC2EN        LL_APB2_GRP1_EnableClock\n
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC3EN        LL_APB2_GRP1_EnableClock\n
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_EnableClock\n
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_EnableClock\n
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI1EN        LL_APB2_GRP1_EnableClock\n
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI4EN        LL_APB2_GRP1_EnableClock\n
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_EnableClock\n
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM9EN        LL_APB2_GRP1_EnableClock\n
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM10EN       LL_APB2_GRP1_EnableClock\n
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM11EN       LL_APB2_GRP1_EnableClock\n
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI5EN        LL_APB2_GRP1_EnableClock\n
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI6EN        LL_APB2_GRP1_EnableClock\n
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI1EN        LL_APB2_GRP1_EnableClock\n
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI2EN        LL_APB2_GRP1_EnableClock\n
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     LTDCEN        LL_APB2_GRP1_EnableClock\n
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DSIEN         LL_APB2_GRP1_EnableClock\n
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_EnableClock\n
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     MDIOEN        LL_APB2_GRP1_EnableClock\n
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_EnableClock
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+ARM GAS  /tmp/cc532wt1.s 			page 34
+
+
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB2ENR, Periphs);
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if APB2 peripheral clock is enabled or not
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART6EN      LL_APB2_GRP1_IsEnabledClock\n
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC1EN        LL_APB2_GRP1_IsEnabledClock\n
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC2EN        LL_APB2_GRP1_IsEnabledClock\n
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC3EN        LL_APB2_GRP1_IsEnabledClock\n
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_IsEnabledClock\n
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_IsEnabledClock\n
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM9EN        LL_APB2_GRP1_IsEnabledClock\n
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM10EN       LL_APB2_GRP1_IsEnabledClock\n
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM11EN       LL_APB2_GRP1_IsEnabledClock\n
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI6EN        LL_APB2_GRP1_IsEnabledClock\n
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     LTDCEN        LL_APB2_GRP1_IsEnabledClock\n
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DSIEN         LL_APB2_GRP1_IsEnabledClock\n
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     MDIOEN        LL_APB2_GRP1_IsEnabledClock\n
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_IsEnabledClock
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ARM GAS  /tmp/cc532wt1.s 			page 35
+
+
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable APB2 peripherals clock.
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_DisableClock\n
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM8EN        LL_APB2_GRP1_DisableClock\n
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART1EN      LL_APB2_GRP1_DisableClock\n
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART6EN      LL_APB2_GRP1_DisableClock\n
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC1EN        LL_APB2_GRP1_DisableClock\n
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC2EN        LL_APB2_GRP1_DisableClock\n
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC3EN        LL_APB2_GRP1_DisableClock\n
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_DisableClock\n
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_DisableClock\n
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI1EN        LL_APB2_GRP1_DisableClock\n
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI4EN        LL_APB2_GRP1_DisableClock\n
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_DisableClock\n
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM9EN        LL_APB2_GRP1_DisableClock\n
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM10EN       LL_APB2_GRP1_DisableClock\n
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM11EN       LL_APB2_GRP1_DisableClock\n
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI5EN        LL_APB2_GRP1_DisableClock\n
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI6EN        LL_APB2_GRP1_DisableClock\n
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI1EN        LL_APB2_GRP1_DisableClock\n
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI2EN        LL_APB2_GRP1_DisableClock\n
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     LTDCEN        LL_APB2_GRP1_DisableClock\n
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DSIEN         LL_APB2_GRP1_DisableClock\n
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_DisableClock\n
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     MDIOEN        LL_APB2_GRP1_DisableClock\n
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_DisableClock
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+ARM GAS  /tmp/cc532wt1.s 			page 36
+
+
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB2ENR, Periphs);
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force APB2 peripherals reset.
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ForceReset\n
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ForceReset\n
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART1RST      LL_APB2_GRP1_ForceReset\n
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART6RST      LL_APB2_GRP1_ForceReset\n
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     ADCRST         LL_APB2_GRP1_ForceReset\n
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC1RST      LL_APB2_GRP1_ForceReset\n
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC2RST      LL_APB2_GRP1_ForceReset\n
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ForceReset\n
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ForceReset\n
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ForceReset\n
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ForceReset\n
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ForceReset\n
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ForceReset\n
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ForceReset\n
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ForceReset\n
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ForceReset\n
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ForceReset\n
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ForceReset\n
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DSIRST         LL_APB2_GRP1_ForceReset\n
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ForceReset\n
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     MDIORST        LL_APB2_GRP1_ForceReset\n
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     OTGPHYCRST     LL_APB2_GRP1_ForceReset
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+ARM GAS  /tmp/cc532wt1.s 			page 37
+
+
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+  92              		.loc 2 1768 22 view .LVU20
+  93              	.LBB35:
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB2RSTR, Periphs);
+  94              		.loc 2 1770 3 view .LVU21
+  95 002a 02F58432 		add	r2, r2, #67584
+  96 002e 516A     		ldr	r1, [r2, #36]
+  97 0030 41F48051 		orr	r1, r1, #4096
+  98 0034 5162     		str	r1, [r2, #36]
+  99              	.LVL9:
+ 100              		.loc 2 1770 3 is_stmt 0 view .LVU22
+ 101              	.LBE35:
+ 102              	.LBE34:
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 103              		.loc 1 147 5 is_stmt 1 view .LVU23
+ 104              	.LBB36:
+ 105              	.LBI36:
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release APB2 peripherals reset.
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ReleaseReset\n
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ReleaseReset\n
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART1RST      LL_APB2_GRP1_ReleaseReset\n
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART6RST      LL_APB2_GRP1_ReleaseReset\n
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     ADCRST         LL_APB2_GRP1_ReleaseReset\n
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC1RST      LL_APB2_GRP1_ReleaseReset\n
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC2RST      LL_APB2_GRP1_ReleaseReset\n
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ReleaseReset\n
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ReleaseReset\n
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ReleaseReset\n
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ReleaseReset\n
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ReleaseReset\n
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ReleaseReset\n
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ReleaseReset\n
+ARM GAS  /tmp/cc532wt1.s 			page 38
+
+
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ReleaseReset\n
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ReleaseReset\n
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ReleaseReset\n
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ReleaseReset\n
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DSIRST         LL_APB2_GRP1_ReleaseReset\n
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ReleaseReset\n
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     MDIORST        LL_APB2_GRP1_ReleaseReset\n
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     OTGPHYCRST     LL_APB2_GRP1_ReleaseReset
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+ 106              		.loc 2 1825 22 view .LVU24
+ 107              	.LBB37:
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB2RSTR, Periphs);
+ 108              		.loc 2 1827 3 view .LVU25
+ 109 0036 516A     		ldr	r1, [r2, #36]
+ 110 0038 21F48051 		bic	r1, r1, #4096
+ 111 003c 5162     		str	r1, [r2, #36]
+ 112              	.LVL10:
+ 113              		.loc 2 1827 3 is_stmt 0 view .LVU26
+ 114              	.LBE37:
+ 115              	.LBE36:
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 116              		.loc 1 149 5 is_stmt 1 view .LVU27
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 117              		.loc 1 149 12 is_stmt 0 view .LVU28
+ 118 003e 0020     		movs	r0, #0
+ 119              	.LVL11:
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 120              		.loc 1 149 12 view .LVU29
+ARM GAS  /tmp/cc532wt1.s 			page 39
+
+
+ 121 0040 E3E7     		b	.L2
+ 122              	.LVL12:
+ 123              	.L10:
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 124              		.loc 1 156 5 is_stmt 1 view .LVU30
+ 125              	.LBB38:
+ 126              	.LBI38:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 127              		.loc 2 1295 22 view .LVU31
+ 128              	.LBB39:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 129              		.loc 2 1297 3 view .LVU32
+ 130 0042 02F50032 		add	r2, r2, #131072
+ 131 0046 116A     		ldr	r1, [r2, #32]
+ 132 0048 41F48041 		orr	r1, r1, #16384
+ 133 004c 1162     		str	r1, [r2, #32]
+ 134              	.LVL13:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 135              		.loc 2 1297 3 is_stmt 0 view .LVU33
+ 136              	.LBE39:
+ 137              	.LBE38:
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 138              		.loc 1 159 5 is_stmt 1 view .LVU34
+ 139              	.LBB40:
+ 140              	.LBI40:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 141              		.loc 2 1367 22 view .LVU35
+ 142              	.LBB41:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 143              		.loc 2 1369 3 view .LVU36
+ 144 004e 116A     		ldr	r1, [r2, #32]
+ 145 0050 21F48041 		bic	r1, r1, #16384
+ 146 0054 1162     		str	r1, [r2, #32]
+ 147              	.LVL14:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 148              		.loc 2 1369 3 is_stmt 0 view .LVU37
+ 149              	.LBE41:
+ 150              	.LBE40:
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 151              		.loc 1 161 5 is_stmt 1 view .LVU38
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 152              		.loc 1 161 12 is_stmt 0 view .LVU39
+ 153 0056 0020     		movs	r0, #0
+ 154 0058 DAE7     		b	.L3
+ 155              	.LVL15:
+ 156              	.L11:
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 157              		.loc 1 168 5 is_stmt 1 view .LVU40
+ 158              	.LBB42:
+ 159              	.LBI42:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 160              		.loc 2 1295 22 view .LVU41
+ 161              	.LBB43:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 162              		.loc 2 1297 3 view .LVU42
+ 163 005a 02F5FE32 		add	r2, r2, #130048
+ 164 005e 116A     		ldr	r1, [r2, #32]
+ARM GAS  /tmp/cc532wt1.s 			page 40
+
+
+ 165 0060 41F40041 		orr	r1, r1, #32768
+ 166 0064 1162     		str	r1, [r2, #32]
+ 167              	.LVL16:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 168              		.loc 2 1297 3 is_stmt 0 view .LVU43
+ 169              	.LBE43:
+ 170              	.LBE42:
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 171              		.loc 1 171 5 is_stmt 1 view .LVU44
+ 172              	.LBB44:
+ 173              	.LBI44:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 174              		.loc 2 1367 22 view .LVU45
+ 175              	.LBB45:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 176              		.loc 2 1369 3 view .LVU46
+ 177 0066 116A     		ldr	r1, [r2, #32]
+ 178 0068 21F40041 		bic	r1, r1, #32768
+ 179 006c 1162     		str	r1, [r2, #32]
+ 180              	.LVL17:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 181              		.loc 2 1369 3 is_stmt 0 view .LVU47
+ 182              	.LBE45:
+ 183              	.LBE44:
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 184              		.loc 1 173 5 is_stmt 1 view .LVU48
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 185              		.loc 1 173 12 is_stmt 0 view .LVU49
+ 186 006e 0020     		movs	r0, #0
+ 187 0070 D1E7     		b	.L4
+ 188              	.LVL18:
+ 189              	.L12:
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 190              		.loc 1 180 5 is_stmt 1 view .LVU50
+ 191              	.LBB46:
+ 192              	.LBI46:
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 193              		.loc 2 1768 22 view .LVU51
+ 194              	.LBB47:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 195              		.loc 2 1770 3 view .LVU52
+ 196 0072 02F58232 		add	r2, r2, #66560
+ 197 0076 516A     		ldr	r1, [r2, #36]
+ 198 0078 41F40051 		orr	r1, r1, #8192
+ 199 007c 5162     		str	r1, [r2, #36]
+ 200              	.LVL19:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 201              		.loc 2 1770 3 is_stmt 0 view .LVU53
+ 202              	.LBE47:
+ 203              	.LBE46:
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 204              		.loc 1 183 5 is_stmt 1 view .LVU54
+ 205              	.LBB48:
+ 206              	.LBI48:
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 207              		.loc 2 1825 22 view .LVU55
+ 208              	.LBB49:
+ARM GAS  /tmp/cc532wt1.s 			page 41
+
+
+ 209              		.loc 2 1827 3 view .LVU56
+ 210 007e 516A     		ldr	r1, [r2, #36]
+ 211 0080 21F40051 		bic	r1, r1, #8192
+ 212 0084 5162     		str	r1, [r2, #36]
+ 213              	.LVL20:
+ 214              		.loc 2 1827 3 is_stmt 0 view .LVU57
+ 215              	.LBE49:
+ 216              	.LBE48:
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 217              		.loc 1 185 5 is_stmt 1 view .LVU58
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 218              		.loc 1 185 12 is_stmt 0 view .LVU59
+ 219 0086 0020     		movs	r0, #0
+ 220 0088 C8E7     		b	.L5
+ 221              	.LVL21:
+ 222              	.L13:
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 223              		.loc 1 192 5 is_stmt 1 view .LVU60
+ 224              	.LBB50:
+ 225              	.LBI50:
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 226              		.loc 2 1768 22 view .LVU61
+ 227              	.LBB51:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 228              		.loc 2 1770 3 view .LVU62
+ 229 008a 02F56842 		add	r2, r2, #59392
+ 230 008e 516A     		ldr	r1, [r2, #36]
+ 231 0090 41F48011 		orr	r1, r1, #1048576
+ 232 0094 5162     		str	r1, [r2, #36]
+ 233              	.LVL22:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 234              		.loc 2 1770 3 is_stmt 0 view .LVU63
+ 235              	.LBE51:
+ 236              	.LBE50:
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 237              		.loc 1 195 5 is_stmt 1 view .LVU64
+ 238              	.LBB52:
+ 239              	.LBI52:
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 240              		.loc 2 1825 22 view .LVU65
+ 241              	.LBB53:
+ 242              		.loc 2 1827 3 view .LVU66
+ 243 0096 516A     		ldr	r1, [r2, #36]
+ 244 0098 21F48011 		bic	r1, r1, #1048576
+ 245 009c 5162     		str	r1, [r2, #36]
+ 246              	.LVL23:
+ 247              		.loc 2 1827 3 is_stmt 0 view .LVU67
+ 248              	.LBE53:
+ 249              	.LBE52:
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 250              		.loc 1 197 5 is_stmt 1 view .LVU68
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 251              		.loc 1 197 12 is_stmt 0 view .LVU69
+ 252 009e 0020     		movs	r0, #0
+ 253 00a0 BFE7     		b	.L6
+ 254              	.LVL24:
+ 255              	.L14:
+ARM GAS  /tmp/cc532wt1.s 			page 42
+
+
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 256              		.loc 1 204 5 is_stmt 1 view .LVU70
+ 257              	.LBB54:
+ 258              	.LBI54:
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 259              		.loc 2 1768 22 view .LVU71
+ 260              	.LBB55:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 261              		.loc 2 1770 3 view .LVU72
+ 262 00a2 0B4B     		ldr	r3, .L15+24
+ 263              	.LVL25:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 264              		.loc 2 1770 3 is_stmt 0 view .LVU73
+ 265 00a4 5A6A     		ldr	r2, [r3, #36]
+ 266 00a6 42F40012 		orr	r2, r2, #2097152
+ 267 00aa 5A62     		str	r2, [r3, #36]
+ 268              	.LVL26:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 269              		.loc 2 1770 3 view .LVU74
+ 270              	.LBE55:
+ 271              	.LBE54:
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 272              		.loc 1 207 5 is_stmt 1 view .LVU75
+ 273              	.LBB56:
+ 274              	.LBI56:
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 275              		.loc 2 1825 22 view .LVU76
+ 276              	.LBB57:
+ 277              		.loc 2 1827 3 view .LVU77
+ 278 00ac 5A6A     		ldr	r2, [r3, #36]
+ 279 00ae 22F40012 		bic	r2, r2, #2097152
+ 280 00b2 5A62     		str	r2, [r3, #36]
+ 281              	.LVL27:
+ 282              		.loc 2 1827 3 is_stmt 0 view .LVU78
+ 283              	.LBE57:
+ 284              	.LBE56:
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 285              		.loc 1 209 5 is_stmt 1 view .LVU79
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 286              		.loc 1 209 12 is_stmt 0 view .LVU80
+ 287 00b4 0020     		movs	r0, #0
+ 288 00b6 B7E7     		b	.L7
+ 289              	.L16:
+ 290              		.align	2
+ 291              	.L15:
+ 292 00b8 00300140 		.word	1073819648
+ 293 00bc 00380040 		.word	1073756160
+ 294 00c0 003C0040 		.word	1073757184
+ 295 00c4 00340140 		.word	1073820672
+ 296 00c8 00500140 		.word	1073827840
+ 297 00cc 00540140 		.word	1073828864
+ 298 00d0 00380240 		.word	1073887232
+ 299              		.cfi_endproc
+ 300              	.LFE451:
+ 302              		.section	.text.LL_SPI_Init,"ax",%progbits
+ 303              		.align	1
+ 304              		.global	LL_SPI_Init
+ARM GAS  /tmp/cc532wt1.s 			page 43
+
+
+ 305              		.syntax unified
+ 306              		.thumb
+ 307              		.thumb_func
+ 308              		.fpu fpv5-d16
+ 310              	LL_SPI_Init:
+ 311              	.LVL28:
+ 312              	.LFB452:
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @note   As some bits in SPI configuration registers can only be written when the SPI is disable
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERRO
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @param  SPIx SPI Instance
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** {
+ 313              		.loc 1 225 1 is_stmt 1 view -0
+ 314              		.cfi_startproc
+ 315              		@ args = 0, pretend = 0, frame = 0
+ 316              		@ frame_needed = 0, uses_anonymous_args = 0
+ 317              		@ link register save eliminated.
+ 318              		.loc 1 225 1 is_stmt 0 view .LVU82
+ 319 0000 0346     		mov	r3, r0
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   ErrorStatus status = ERROR;
+ 320              		.loc 1 226 3 is_stmt 1 view .LVU83
+ 321              	.LVL29:
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   /* Check the SPI Instance SPIx*/
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+ 322              		.loc 1 229 3 view .LVU84
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   /* Check the SPI parameters from SPI_InitStruct*/
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+ 323              		.loc 1 232 3 view .LVU85
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+ 324              		.loc 1 233 3 view .LVU86
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+ 325              		.loc 1 234 3 view .LVU87
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+ 326              		.loc 1 235 3 view .LVU88
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+ 327              		.loc 1 236 3 view .LVU89
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+ 328              		.loc 1 237 3 view .LVU90
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+ 329              		.loc 1 238 3 view .LVU91
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+ 330              		.loc 1 239 3 view .LVU92
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+ 331              		.loc 1 240 3 view .LVU93
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+ 332              		.loc 1 242 3 view .LVU94
+ 333              	.LBB58:
+ 334              	.LBI58:
+ARM GAS  /tmp/cc532wt1.s 			page 44
+
+
+ 335              		.file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @file    stm32f7xx_ll_spi.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief   Header file of SPI LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifndef STM32F7xx_LL_SPI_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define STM32F7xx_LL_SPI_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defin
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL SPI
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER)
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  SPI Init structures definition
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** typedef struct
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mod
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_M
+ARM GAS  /tmp/cc532wt1.s 			page 45
+
+
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t DataWidth;               /*!< Specifies the SPI data width.
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (N
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used 
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPR
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          @note The communication clock is derived from the master c
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCUL
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter must be a number between Min_Data = 0x00 an
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } LL_SPI_InitTypeDef;
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/
+ARM GAS  /tmp/cc532wt1.s 			page 46
+
+
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag 
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag     
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag           
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag          
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag             
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format erro
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty inter
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable   
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_MODE Operation Mode
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuratio
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as de
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                  
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PHASE Clock Phase
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition i
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ARM GAS  /tmp/cc532wt1.s 			page 47
+
+
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< Baud
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< Baud
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< Baud
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< Baud
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< Baud
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< Baud
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< Baud
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< Baud
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/recei
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/recei
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mo
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mod
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed inter
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in I
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in O
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ARM GAS  /tmp/cc532wt1.s 			page 48
+
+
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                           
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                          
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                           
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                           
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)            
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                          
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                           
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                           
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)            
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                           
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)            
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)            
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER)
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled 
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated i
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated i
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception em
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception fu
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ARM GAS  /tmp/cc532wt1.s 			page 49
+
+
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Write a value in SPI register
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __INSTANCE__ SPI Instance
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __REG__ Register to be written
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __VALUE__ Value to be written in the register
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Read a value in SPI register
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __INSTANCE__ SPI Instance
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __REG__ Register to be read
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Register value
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ARM GAS  /tmp/cc532wt1.s 			page 50
+
+
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Configuration Configuration
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable SPI peripheral
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          SPE           LL_SPI_Enable
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable SPI peripheral
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          SPE           LL_SPI_Disable
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if SPI peripheral is enabled
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+ 336              		.loc 3 381 26 view .LVU95
+ 337              	.LBB59:
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
+ 338              		.loc 3 383 3 view .LVU96
+ 339              		.loc 3 383 12 is_stmt 0 view .LVU97
+ 340 0002 0268     		ldr	r2, [r0]
+ 341              		.loc 3 383 69 view .LVU98
+ 342 0004 12F0400F 		tst	r2, #64
+ 343 0008 36D1     		bne	.L20
+ 344              	.LBE59:
+ 345              	.LBE58:
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   ErrorStatus status = ERROR;
+ 346              		.loc 1 225 1 view .LVU99
+ 347 000a 10B4     		push	{r4}
+ 348              	.LCFI0:
+ 349              		.cfi_def_cfa_offset 4
+ARM GAS  /tmp/cc532wt1.s 			page 51
+
+
+ 350              		.cfi_offset 4, -4
+ 351              	.LVL30:
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   {
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /*---------------------------- SPIx CR1 Configuration ------------------------
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * Configure SPIx CR1 with parameters:
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - Master/Slave Mode:  SPI_CR1_MSTR bit
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - ClockPolarity:      SPI_CR1_CPOL bit
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - ClockPhase:         SPI_CR1_CPHA bit
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - NSS management:     SPI_CR1_SSM bit
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - BitOrder:           SPI_CR1_LSBFIRST bit
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - CRCCalculation:     SPI_CR1_CRCEN bit
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      */
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     MODIFY_REG(SPIx->CR1,
+ 352              		.loc 1 255 5 is_stmt 1 view .LVU100
+ 353 000c 0268     		ldr	r2, [r0]
+ 354 000e 1D48     		ldr	r0, .L27
+ 355              	.LVL31:
+ 356              		.loc 1 255 5 is_stmt 0 view .LVU101
+ 357 0010 1040     		ands	r0, r0, r2
+ 358 0012 0A68     		ldr	r2, [r1]
+ 359 0014 4C68     		ldr	r4, [r1, #4]
+ 360 0016 2243     		orrs	r2, r2, r4
+ 361 0018 CC68     		ldr	r4, [r1, #12]
+ 362 001a 2243     		orrs	r2, r2, r4
+ 363 001c 0C69     		ldr	r4, [r1, #16]
+ 364 001e 2243     		orrs	r2, r2, r4
+ 365 0020 4C69     		ldr	r4, [r1, #20]
+ 366 0022 2243     		orrs	r2, r2, r4
+ 367 0024 8C69     		ldr	r4, [r1, #24]
+ 368 0026 2243     		orrs	r2, r2, r4
+ 369 0028 CC69     		ldr	r4, [r1, #28]
+ 370 002a 2243     		orrs	r2, r2, r4
+ 371 002c 0C6A     		ldr	r4, [r1, #32]
+ 372 002e 2243     		orrs	r2, r2, r4
+ 373 0030 0243     		orrs	r2, r2, r0
+ 374 0032 1A60     		str	r2, [r3]
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                SPI_CR1_CLEAR_MASK,
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /*---------------------------- SPIx CR2 Configuration ------------------------
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * Configure SPIx CR2 with parameters:
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - DataWidth:          DS[3:0] bits
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - NSS management:     SSOE bit
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      */
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     MODIFY_REG(SPIx->CR2,
+ 375              		.loc 1 267 5 is_stmt 1 view .LVU102
+ 376 0034 5868     		ldr	r0, [r3, #4]
+ 377 0036 144A     		ldr	r2, .L27+4
+ 378 0038 0240     		ands	r2, r2, r0
+ 379 003a 8868     		ldr	r0, [r1, #8]
+ 380 003c B1F816C0 		ldrh	ip, [r1, #22]
+ 381 0040 40EA0C00 		orr	r0, r0, ip
+ARM GAS  /tmp/cc532wt1.s 			page 52
+
+
+ 382 0044 0243     		orrs	r2, r2, r0
+ 383 0046 5A60     		str	r2, [r3, #4]
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                SPI_CR2_DS | SPI_CR2_SSOE,
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
+ 384              		.loc 1 272 5 view .LVU103
+ 385              		.loc 1 272 23 is_stmt 0 view .LVU104
+ 386 0048 8A68     		ldr	r2, [r1, #8]
+ 387              		.loc 1 272 8 view .LVU105
+ 388 004a B2F5006F 		cmp	r2, #2048
+ 389 004e 03D2     		bcs	.L19
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     {
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
+ 390              		.loc 1 274 7 is_stmt 1 view .LVU106
+ 391              	.LVL32:
+ 392              	.LBB60:
+ 393              	.LBI60:
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set SPI operation mode to Master or Slave
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing.
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          SSI           LL_SPI_SetMode
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  Mode This parameter can be one of the following values:
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MODE_MASTER
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MODE_SLAVE
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get SPI operation mode (Master or Slave)
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          SSI           LL_SPI_GetMode
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MODE_MASTER
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MODE_SLAVE
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set serial protocol used
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          FRF           LL_SPI_SetStandard
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  Standard This parameter can be one of the following values:
+ARM GAS  /tmp/cc532wt1.s 			page 53
+
+
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PROTOCOL_TI
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get serial protocol used
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          FRF           LL_SPI_GetStandard
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PROTOCOL_TI
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set clock phase
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing.
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         This bit is not used in SPI TI mode.
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  ClockPhase This parameter can be one of the following values:
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PHASE_1EDGE
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PHASE_2EDGE
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get clock phase
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PHASE_1EDGE
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_PHASE_2EDGE
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set clock polarity
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing.
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         This bit is not used in SPI TI mode.
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ARM GAS  /tmp/cc532wt1.s 			page 54
+
+
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  ClockPolarity This parameter can be one of the following values:
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_POLARITY_LOW
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_POLARITY_HIGH
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get clock polarity
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_POLARITY_LOW
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_POLARITY_HIGH
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set baud rate prescaler
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Pr
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  BaudRate This parameter can be one of the following values:
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get baud rate prescaler
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ARM GAS  /tmp/cc532wt1.s 			page 55
+
+
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set transfer bit order
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing. This bit is not used in S
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  BitOrder This parameter can be one of the following values:
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_LSB_FIRST
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MSB_FIRST
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get transfer bit order
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_LSB_FIRST
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_MSB_FIRST
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set transfer direction mode
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   For Half-Duplex mode, Rx Direction is set by default.
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-D
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          BIDIOE        LL_SPI_SetTransferDirection
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  TransferDirection This parameter can be one of the following values:
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_FULL_DUPLEX
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_SIMPLEX_RX
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get transfer direction mode
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
+ARM GAS  /tmp/cc532wt1.s 			page 56
+
+
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         CR1          BIDIOE        LL_SPI_GetTransferDirection
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_FULL_DUPLEX
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_SIMPLEX_RX
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set frame data width
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          DS            LL_SPI_SetDataWidth
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  DataWidth This parameter can be one of the following values:
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get frame data width
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          DS            LL_SPI_GetDataWidth
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+ARM GAS  /tmp/cc532wt1.s 			page 57
+
+
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set threshold of RXFIFO that triggers an RXNE event
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  Threshold This parameter can be one of the following values:
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
+ 394              		.loc 3 665 22 view .LVU107
+ 395              	.LBB61:
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
+ 396              		.loc 3 667 3 view .LVU108
+ 397 0050 5A68     		ldr	r2, [r3, #4]
+ 398 0052 42F48052 		orr	r2, r2, #4096
+ 399 0056 5A60     		str	r2, [r3, #4]
+ 400              	.LVL33:
+ 401              	.L19:
+ 402              		.loc 3 667 3 is_stmt 0 view .LVU109
+ 403              	.LBE61:
+ 404              	.LBE60:
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     }
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /*---------------------------- SPIx CRCPR Configuration ----------------------
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * Configure SPIx CRCPR with parameters:
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - CRCPoly:            CRCPOLY[15:0] bits
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      */
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+ 405              		.loc 1 281 5 is_stmt 1 view .LVU110
+ 406              		.loc 1 281 23 is_stmt 0 view .LVU111
+ 407 0058 0A6A     		ldr	r2, [r1, #32]
+ 408              		.loc 1 281 8 view .LVU112
+ 409 005a B2F5005F 		cmp	r2, #8192
+ 410 005e 07D0     		beq	.L26
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     {
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     }
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     status = SUCCESS;
+ 411              		.loc 1 286 12 view .LVU113
+ 412 0060 0020     		movs	r0, #0
+ 413              	.L18:
+ 414              	.LVL34:
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+ 415              		.loc 1 290 3 is_stmt 1 view .LVU114
+ 416 0062 DA69     		ldr	r2, [r3, #28]
+ARM GAS  /tmp/cc532wt1.s 			page 58
+
+
+ 417 0064 22F40062 		bic	r2, r2, #2048
+ 418 0068 DA61     		str	r2, [r3, #28]
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   return status;
+ 419              		.loc 1 291 3 view .LVU115
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** }
+ 420              		.loc 1 292 1 is_stmt 0 view .LVU116
+ 421 006a 5DF8044B 		ldr	r4, [sp], #4
+ 422              	.LCFI1:
+ 423              		.cfi_remember_state
+ 424              		.cfi_restore 4
+ 425              		.cfi_def_cfa_offset 0
+ 426 006e 7047     		bx	lr
+ 427              	.LVL35:
+ 428              	.L26:
+ 429              	.LCFI2:
+ 430              		.cfi_restore_state
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+ 431              		.loc 1 283 7 is_stmt 1 view .LVU117
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     }
+ 432              		.loc 1 284 7 view .LVU118
+ 433              	.LBB62:
+ 434              	.LBI62:
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get threshold of RXFIFO that triggers an RXNE event
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_CRC_Management CRC Management
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable CRC
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ARM GAS  /tmp/cc532wt1.s 			page 59
+
+
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable CRC
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if CRC is enabled
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set CRC Length
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  CRCLength This parameter can be one of the following values:
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_CRC_8BIT
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_CRC_16BIT
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get CRC Length
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_CRC_8BIT
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_CRC_16BIT
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set CRCNext to transfer CRC on the line
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ARM GAS  /tmp/cc532wt1.s 			page 60
+
+
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set polynomial for CRC calculation
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+ 435              		.loc 3 774 22 view .LVU119
+ 436              	.LBB63:
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+ 437              		.loc 3 776 3 view .LVU120
+ 438 0070 8A8C     		ldrh	r2, [r1, #36]
+ 439 0072 1A61     		str	r2, [r3, #16]
+ 440              	.LVL36:
+ 441              		.loc 3 776 3 is_stmt 0 view .LVU121
+ 442              	.LBE63:
+ 443              	.LBE62:
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 444              		.loc 1 286 12 view .LVU122
+ 445 0074 0020     		movs	r0, #0
+ 446              	.LBB65:
+ 447              	.LBB64:
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 448              		.loc 3 777 1 view .LVU123
+ 449 0076 F4E7     		b	.L18
+ 450              	.LVL37:
+ 451              	.L20:
+ 452              	.LCFI3:
+ 453              		.cfi_def_cfa_offset 0
+ 454              		.cfi_restore 4
+ 455              		.loc 3 777 1 view .LVU124
+ 456              	.LBE64:
+ 457              	.LBE65:
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 458              		.loc 1 226 15 view .LVU125
+ 459 0078 0120     		movs	r0, #1
+ 460              	.LVL38:
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   return status;
+ 461              		.loc 1 290 3 is_stmt 1 view .LVU126
+ 462 007a DA69     		ldr	r2, [r3, #28]
+ 463 007c 22F40062 		bic	r2, r2, #2048
+ 464 0080 DA61     		str	r2, [r3, #28]
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** }
+ 465              		.loc 1 291 3 view .LVU127
+ 466              		.loc 1 292 1 is_stmt 0 view .LVU128
+ 467 0082 7047     		bx	lr
+ 468              	.L28:
+ 469              		.align	2
+ARM GAS  /tmp/cc532wt1.s 			page 61
+
+
+ 470              	.L27:
+ 471 0084 4000FFFF 		.word	-65472
+ 472 0088 FBF0FFFF 		.word	-3845
+ 473              		.cfi_endproc
+ 474              	.LFE452:
+ 476              		.section	.text.LL_SPI_StructInit,"ax",%progbits
+ 477              		.align	1
+ 478              		.global	LL_SPI_StructInit
+ 479              		.syntax unified
+ 480              		.thumb
+ 481              		.thumb_func
+ 482              		.fpu fpv5-d16
+ 484              	LL_SPI_StructInit:
+ 485              	.LVL39:
+ 486              	.LFB453:
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * whose fields will be set to default values.
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @retval None
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** {
+ 487              		.loc 1 301 1 is_stmt 1 view -0
+ 488              		.cfi_startproc
+ 489              		@ args = 0, pretend = 0, frame = 0
+ 490              		@ frame_needed = 0, uses_anonymous_args = 0
+ 491              		@ link register save eliminated.
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   /* Set SPI_InitStruct fields to default values */
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+ 492              		.loc 1 303 3 view .LVU130
+ 493              		.loc 1 303 37 is_stmt 0 view .LVU131
+ 494 0000 0023     		movs	r3, #0
+ 495 0002 0360     		str	r3, [r0]
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
+ 496              		.loc 1 304 3 is_stmt 1 view .LVU132
+ 497              		.loc 1 304 37 is_stmt 0 view .LVU133
+ 498 0004 4360     		str	r3, [r0, #4]
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
+ 499              		.loc 1 305 3 is_stmt 1 view .LVU134
+ 500              		.loc 1 305 37 is_stmt 0 view .LVU135
+ 501 0006 4FF4E062 		mov	r2, #1792
+ 502 000a 8260     		str	r2, [r0, #8]
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
+ 503              		.loc 1 306 3 is_stmt 1 view .LVU136
+ 504              		.loc 1 306 37 is_stmt 0 view .LVU137
+ 505 000c C360     		str	r3, [r0, #12]
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
+ 506              		.loc 1 307 3 is_stmt 1 view .LVU138
+ 507              		.loc 1 307 37 is_stmt 0 view .LVU139
+ 508 000e 0361     		str	r3, [r0, #16]
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
+ 509              		.loc 1 308 3 is_stmt 1 view .LVU140
+ 510              		.loc 1 308 37 is_stmt 0 view .LVU141
+ 511 0010 4361     		str	r3, [r0, #20]
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
+ARM GAS  /tmp/cc532wt1.s 			page 62
+
+
+ 512              		.loc 1 309 3 is_stmt 1 view .LVU142
+ 513              		.loc 1 309 37 is_stmt 0 view .LVU143
+ 514 0012 8361     		str	r3, [r0, #24]
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
+ 515              		.loc 1 310 3 is_stmt 1 view .LVU144
+ 516              		.loc 1 310 37 is_stmt 0 view .LVU145
+ 517 0014 C361     		str	r3, [r0, #28]
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
+ 518              		.loc 1 311 3 is_stmt 1 view .LVU146
+ 519              		.loc 1 311 37 is_stmt 0 view .LVU147
+ 520 0016 0362     		str	r3, [r0, #32]
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   SPI_InitStruct->CRCPoly           = 7U;
+ 521              		.loc 1 312 3 is_stmt 1 view .LVU148
+ 522              		.loc 1 312 37 is_stmt 0 view .LVU149
+ 523 0018 0723     		movs	r3, #7
+ 524 001a 4362     		str	r3, [r0, #36]
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** }
+ 525              		.loc 1 313 1 view .LVU150
+ 526 001c 7047     		bx	lr
+ 527              		.cfi_endproc
+ 528              	.LFE453:
+ 530              		.section	.text.LL_I2S_DeInit,"ax",%progbits
+ 531              		.align	1
+ 532              		.global	LL_I2S_DeInit
+ 533              		.syntax unified
+ 534              		.thumb
+ 535              		.thumb_func
+ 536              		.fpu fpv5-d16
+ 538              	LL_I2S_DeInit:
+ 539              	.LVL40:
+ 540              	.LFB454:
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @}
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @}
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @}
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup I2S_LL
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @{
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private types -------------------------------------------------------------*/
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private variables ---------------------------------------------------------*/
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private constants ---------------------------------------------------------*/
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @defgroup I2S_LL_Private_Constants I2S Private Constants
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @{
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* I2S registers Masks */
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                             SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
+ARM GAS  /tmp/cc532wt1.s 			page 63
+
+
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                             SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define I2S_I2SPR_CLEAR_MASK               0x0002U
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @}
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private macros ------------------------------------------------------------*/
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @defgroup I2S_LL_Private_Macros I2S Private Macros
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @{
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)             \
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)      \
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)     \
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)       \
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                           && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                          || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                                                || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @}
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private function prototypes -----------------------------------------------*/
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Exported functions --------------------------------------------------------*/
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup I2S_LL_Exported_Functions
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @{
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup I2S_LL_EF_Init
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @{
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ARM GAS  /tmp/cc532wt1.s 			page 64
+
+
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @brief  De-initialize the SPI/I2S registers to their default reset values.
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @param  SPIx SPI Instance
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @retval An ErrorStatus enumeration value:
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *          - SUCCESS: SPI registers are de-initialized
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *          - ERROR: SPI registers are not de-initialized
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** {
+ 541              		.loc 1 404 1 is_stmt 1 view -0
+ 542              		.cfi_startproc
+ 543              		@ args = 0, pretend = 0, frame = 0
+ 544              		@ frame_needed = 0, uses_anonymous_args = 0
+ 545              		.loc 1 404 1 is_stmt 0 view .LVU152
+ 546 0000 08B5     		push	{r3, lr}
+ 547              	.LCFI4:
+ 548              		.cfi_def_cfa_offset 8
+ 549              		.cfi_offset 3, -8
+ 550              		.cfi_offset 14, -4
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   return LL_SPI_DeInit(SPIx);
+ 551              		.loc 1 405 3 is_stmt 1 view .LVU153
+ 552              		.loc 1 405 10 is_stmt 0 view .LVU154
+ 553 0002 FFF7FEFF 		bl	LL_SPI_DeInit
+ 554              	.LVL41:
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** }
+ 555              		.loc 1 406 1 view .LVU155
+ 556 0006 08BD     		pop	{r3, pc}
+ 557              		.cfi_endproc
+ 558              	.LFE454:
+ 560              		.section	.text.LL_I2S_Init,"ax",%progbits
+ 561              		.align	1
+ 562              		.global	LL_I2S_Init
+ 563              		.syntax unified
+ 564              		.thumb
+ 565              		.thumb_func
+ 566              		.fpu fpv5-d16
+ 568              	LL_I2S_Init:
+ 569              	.LVL42:
+ 570              	.LFB455:
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStru
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @note   As some bits in SPI configuration registers can only be written when the SPI is disable
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERRO
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @param  SPIx SPI Instance
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @retval An ErrorStatus enumeration value:
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *          - SUCCESS: SPI registers are Initialized
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *          - ERROR: SPI registers are not Initialized
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** {
+ 571              		.loc 1 419 1 is_stmt 1 view -0
+ 572              		.cfi_startproc
+ 573              		@ args = 0, pretend = 0, frame = 0
+ 574              		@ frame_needed = 0, uses_anonymous_args = 0
+ 575              		.loc 1 419 1 is_stmt 0 view .LVU157
+ 576 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ARM GAS  /tmp/cc532wt1.s 			page 65
+
+
+ 577              	.LCFI5:
+ 578              		.cfi_def_cfa_offset 24
+ 579              		.cfi_offset 3, -24
+ 580              		.cfi_offset 4, -20
+ 581              		.cfi_offset 5, -16
+ 582              		.cfi_offset 6, -12
+ 583              		.cfi_offset 7, -8
+ 584              		.cfi_offset 14, -4
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   uint32_t i2sdiv = 2U;
+ 585              		.loc 1 420 3 is_stmt 1 view .LVU158
+ 586              	.LVL43:
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   uint32_t i2sodd = 0U;
+ 587              		.loc 1 421 3 view .LVU159
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   uint32_t packetlength = 1U;
+ 588              		.loc 1 422 3 view .LVU160
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   uint32_t tmp;
+ 589              		.loc 1 423 3 view .LVU161
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   uint32_t sourceclock;
+ 590              		.loc 1 424 3 view .LVU162
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   ErrorStatus status = ERROR;
+ 591              		.loc 1 425 3 view .LVU163
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   /* Check the I2S parameters */
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ 592              		.loc 1 428 3 view .LVU164
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+ 593              		.loc 1 429 3 view .LVU165
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+ 594              		.loc 1 430 3 view .LVU166
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+ 595              		.loc 1 431 3 view .LVU167
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+ 596              		.loc 1 432 3 view .LVU168
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+ 597              		.loc 1 433 3 view .LVU169
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+ 598              		.loc 1 434 3 view .LVU170
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
+ 599              		.loc 1 436 3 view .LVU171
+ 600              	.LBB66:
+ 601              	.LBI66:
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get polynomial for CRC calculation
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_REG(SPIx->CRCPR));
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get Rx CRC
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
+ARM GAS  /tmp/cc532wt1.s 			page 66
+
+
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_REG(SPIx->RXCRCR));
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get Tx CRC
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_REG(SPIx->TXCRCR));
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set NSS mode
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  NSS This parameter can be one of the following values:
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_SOFT
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_HARD_INPUT
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get NSS mode
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_SOFT
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_HARD_INPUT
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ARM GAS  /tmp/cc532wt1.s 			page 67
+
+
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (Ssm | Ssoe);
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable NSS pulse management
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing. This bit is not used in S
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable NSS pulse management
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing. This bit is not used in S
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if NSS pulse is enabled
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit should not be changed when communication is ongoing. This bit is not used in S
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if Rx buffer is not empty
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ARM GAS  /tmp/cc532wt1.s 			page 68
+
+
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if Tx buffer is empty
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get CRC error flag
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get mode fault error flag
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get overrun error flag
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get busy flag
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   The BSY flag is cleared under any one of the following conditions:
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * -When the SPI is correctly disabled
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * -When a fault is detected in Master mode (MODF bit set to 1)
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * -In Master mode, when it finishes a data transmission and no new data is ready to be
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * sent
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * each data transfer.
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
+ARM GAS  /tmp/cc532wt1.s 			page 69
+
+
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get frame format error flag
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get FIFO reception Level
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_EMPTY
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_RX_FIFO_FULL
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get FIFO Transmission Level
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_TX_FIFO_EMPTY
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_TX_FIFO_FULL
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Clear CRC error flag
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+ARM GAS  /tmp/cc532wt1.s 			page 70
+
+
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Clear mode fault error flag
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   Clearing this flag is done by a read access to the SPIx_SR
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         register followed by a write access to the SPIx_CR1 register
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   __IO uint32_t tmpreg_sr;
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   tmpreg_sr = SPIx->SR;
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   (void) tmpreg_sr;
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Clear overrun error flag
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   Clearing this flag is done by a read access to the SPIx_DR
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         register followed by a read access to the SPIx_SR register
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   __IO uint32_t tmpreg;
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   tmpreg = SPIx->DR;
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   (void) tmpreg;
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   tmpreg = SPIx->SR;
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   (void) tmpreg;
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Clear frame format error flag
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   Clearing this flag is done by reading SPIx_SR register
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   __IO uint32_t tmpreg;
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   tmpreg = SPIx->SR;
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   (void) tmpreg;
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ARM GAS  /tmp/cc532wt1.s 			page 71
+
+
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable error interrupt
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable Rx buffer not empty interrupt
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable Tx buffer empty interrupt
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable error interrupt
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable Rx buffer not empty interrupt
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+ARM GAS  /tmp/cc532wt1.s 			page 72
+
+
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable Tx buffer empty interrupt
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if error interrupt is enabled
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if Rx buffer not empty interrupt is enabled
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if Tx buffer empty interrupt
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DMA_Management DMA Management
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable DMA Rx
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+ARM GAS  /tmp/cc532wt1.s 			page 73
+
+
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable DMA Rx
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if DMA Rx is enabled
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Enable DMA Tx
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable DMA Tx
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if DMA Tx is enabled
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ARM GAS  /tmp/cc532wt1.s 			page 74
+
+
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set parity of  Last DMA reception
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  Parity This parameter can be one of the following values:
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_ODD
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get parity configuration for  Last DMA reception
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_ODD
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Set parity of  Last DMA transmission
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  Parity This parameter can be one of the following values:
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_ODD
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get parity configuration for Last DMA transmission
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Returned value can be one of the following values:
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_ODD
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
+ARM GAS  /tmp/cc532wt1.s 			page 75
+
+
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Get the data register address used for DMA transfer
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Address of data register
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint32_t) &(SPIx->DR);
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DATA_Management DATA Management
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Read 8-Bits in the data register
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll DR           DR            LL_SPI_ReceiveData8
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (*((__IO uint8_t *)&SPIx->DR));
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Read 16-Bits in the data register
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll DR           DR            LL_SPI_ReceiveData16
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return (uint16_t)(READ_REG(SPIx->DR));
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Write 8-Bits in the data register
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll DR           DR            LL_SPI_TransmitData8
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__)
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *spidr = TxData;
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #else
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *((__IO uint8_t *)&SPIx->DR) = TxData;
+ARM GAS  /tmp/cc532wt1.s 			page 76
+
+
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* __GNUC__ */
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Write 16-Bits in the data register
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll DR           DR            LL_SPI_TransmitData16
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__)
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *spidr = TxData;
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #else
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SPIx->DR = TxData;
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* __GNUC__ */
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER)
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL I2S
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private constants ---------------------------------------------------------*/
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER)
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ARM GAS  /tmp/cc532wt1.s 			page 77
+
+
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  I2S Init structure definition
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** typedef struct
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t Mode;                    /*!< Specifies the I2S operating mode.
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref I2S_LL_EC_MODE
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref I2S_LL_EC_STANDARD
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref I2S_LL_EC_DATA_FORMA
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPU
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          Audio Frequency can be modified afterwards using Reference
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          and unitary functions @ref LL_I2S_SetPrescalerLinear() and
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This parameter can be a value of @ref I2S_LL_EC_POLARITY
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****                                          This feature can be modified afterwards using unitary func
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } LL_I2S_InitTypeDef;
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /*USE_FULL_LL_DRIVER*/
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief    Flags defines which can be used with LL_I2S_ReadReg function
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+ARM GAS  /tmp/cc532wt1.s 			page 78
+
+
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag 
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag     
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag            
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag             
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format erro
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty inter
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable   
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data 
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data 
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data 
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data 
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is hig
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_STANDARD I2s Standard
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_STANDARD_PHILIPS            0x00000000U                                             
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                  
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                  
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)           
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCF
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_MODE Operation Mode
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+ARM GAS  /tmp/cc532wt1.s 			page 79
+
+
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Maste
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Maste
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider 
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider 
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER)
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is di
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is en
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_192K              192000U       /*!< Audio Frequency configuration 192000 
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_96K               96000U        /*!< Audio Frequency configuration  96000 
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_48K               48000U        /*!< Audio Frequency configuration  48000 
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_44K               44100U        /*!< Audio Frequency configuration  44100 
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_32K               32000U        /*!< Audio Frequency configuration  32000 
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_22K               22050U        /*!< Audio Frequency configuration  22050 
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_16K               16000U        /*!< Audio Frequency configuration  16000 
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_11K               11025U        /*!< Audio Frequency configuration  11025 
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_8K                8000U         /*!< Audio Frequency configuration   8000 
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_DEFAULT           2U            /*!< Audio Freq not specified. Register I2
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+ARM GAS  /tmp/cc532wt1.s 			page 80
+
+
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Write a value in I2S register
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __INSTANCE__ I2S Instance
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __REG__ Register to be written
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __VALUE__ Value to be written in the register
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Read a value in I2S register
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __INSTANCE__ I2S Instance
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  __REG__ Register to be read
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval Register value
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @}
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EF_Configuration Configuration
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @{
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Select I2S mode and Enable I2S peripheral
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   *         I2SCFGR      I2SE          LL_I2S_Enable
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Disable I2S peripheral
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval None
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
+ARM GAS  /tmp/cc532wt1.s 			page 81
+
+
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** }
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /**
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @brief  Check if I2S peripheral is enabled
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @param  SPIx SPI Instance
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   * @retval State of bit (1 or 0).
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   */
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
+ 602              		.loc 3 1658 26 view .LVU172
+ 603              	.LBB67:
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** {
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h ****   return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
+ 604              		.loc 3 1660 3 view .LVU173
+ 605              		.loc 3 1660 12 is_stmt 0 view .LVU174
+ 606 0002 C669     		ldr	r6, [r0, #28]
+ 607              		.loc 3 1660 83 view .LVU175
+ 608 0004 16F48066 		ands	r6, r6, #1024
+ 609 0008 49D1     		bne	.L39
+ 610 000a 0446     		mov	r4, r0
+ 611 000c 0D46     		mov	r5, r1
+ 612              	.LVL44:
+ 613              		.loc 3 1660 83 view .LVU176
+ 614              	.LBE67:
+ 615              	.LBE66:
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   {
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /*---------------------------- SPIx I2SCFGR Configuration --------------------
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * Configure SPIx I2SCFGR with parameters:
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      */
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Write to SPIx I2SCFGR */
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     MODIFY_REG(SPIx->I2SCFGR,
+ 616              		.loc 1 447 5 is_stmt 1 view .LVU177
+ 617 000e C269     		ldr	r2, [r0, #28]
+ 618 0010 244B     		ldr	r3, .L45
+ 619 0012 1340     		ands	r3, r3, r2
+ 620 0014 0A68     		ldr	r2, [r1]
+ 621 0016 4968     		ldr	r1, [r1, #4]
+ 622              	.LVL45:
+ 623              		.loc 1 447 5 is_stmt 0 view .LVU178
+ 624 0018 0A43     		orrs	r2, r2, r1
+ 625 001a A968     		ldr	r1, [r5, #8]
+ 626 001c 0A43     		orrs	r2, r2, r1
+ 627 001e 6969     		ldr	r1, [r5, #20]
+ 628 0020 0A43     		orrs	r2, r2, r1
+ 629 0022 1343     		orrs	r3, r3, r2
+ 630 0024 43F40063 		orr	r3, r3, #2048
+ 631 0028 C361     		str	r3, [r0, #28]
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                I2S_I2SCFGR_CLEAR_MASK,
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                I2S_InitStruct->Mode | I2S_InitStruct->Standard |
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+ARM GAS  /tmp/cc532wt1.s 			page 82
+
+
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****                SPI_I2SCFGR_I2SMOD);
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /*---------------------------- SPIx I2SPR Configuration ----------------------
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * Configure SPIx I2SPR with parameters:
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - MCLKOutput:    SPI_I2SPR_MCKOE bit
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      */
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****      */
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+ 632              		.loc 1 462 5 is_stmt 1 view .LVU179
+ 633              		.loc 1 462 23 is_stmt 0 view .LVU180
+ 634 002a 2B69     		ldr	r3, [r5, #16]
+ 635              		.loc 1 462 8 view .LVU181
+ 636 002c 022B     		cmp	r3, #2
+ 637 002e 32D0     		beq	.L40
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     {
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       /* Check the frame length (For the Prescaler computing)
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****        * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****        */
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+ 638              		.loc 1 467 7 is_stmt 1 view .LVU182
+ 639              		.loc 1 467 25 is_stmt 0 view .LVU183
+ 640 0030 AB68     		ldr	r3, [r5, #8]
+ 641              		.loc 1 467 10 view .LVU184
+ 642 0032 2BBB     		cbnz	r3, .L41
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   uint32_t tmp;
+ 643              		.loc 1 422 12 view .LVU185
+ 644 0034 0127     		movs	r7, #1
+ 645              	.L35:
+ 646              	.LVL46:
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       {
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****         /* Packet length is 32 bits */
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****         packetlength = 2U;
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       }
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       /* If an external I2S clock has to be used, the specific define should be set
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       in the project configuration or in the stm32f7xx_ll_rcc.h file */
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       /* Get the I2S source clock value */
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
+ 647              		.loc 1 476 7 is_stmt 1 view .LVU186
+ 648              		.loc 1 476 21 is_stmt 0 view .LVU187
+ 649 0036 4FF40000 		mov	r0, #8388608
+ 650              	.LVL47:
+ 651              		.loc 1 476 21 view .LVU188
+ 652 003a FFF7FEFF 		bl	LL_RCC_GetI2SClockFreq
+ 653              	.LVL48:
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       /* Compute the Real divider depending on the MCLK output state with a floating point */
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+ 654              		.loc 1 479 7 is_stmt 1 view .LVU189
+ 655              		.loc 1 479 25 is_stmt 0 view .LVU190
+ 656 003e EB68     		ldr	r3, [r5, #12]
+ 657              		.loc 1 479 10 view .LVU191
+ 658 0040 B3F5007F 		cmp	r3, #512
+ARM GAS  /tmp/cc532wt1.s 			page 83
+
+
+ 659 0044 1ED0     		beq	.L44
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       {
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****         /* MCLK output is enabled */
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****         tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       }
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       else
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       {
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****         /* MCLK output is disabled */
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****         tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ 660              		.loc 1 487 9 is_stmt 1 view .LVU192
+ 661              		.loc 1 487 39 is_stmt 0 view .LVU193
+ 662 0046 7F01     		lsls	r7, r7, #5
+ 663              	.LVL49:
+ 664              		.loc 1 487 32 view .LVU194
+ 665 0048 B0FBF7F0 		udiv	r0, r0, r7
+ 666              	.LVL50:
+ 667              		.loc 1 487 56 view .LVU195
+ 668 004c 00EB8000 		add	r0, r0, r0, lsl #2
+ 669 0050 4300     		lsls	r3, r0, #1
+ 670              		.loc 1 487 79 view .LVU196
+ 671 0052 2869     		ldr	r0, [r5, #16]
+ 672              		.loc 1 487 63 view .LVU197
+ 673 0054 B3FBF0F3 		udiv	r3, r3, r0
+ 674              		.loc 1 487 13 view .LVU198
+ 675 0058 0533     		adds	r3, r3, #5
+ 676              	.LVL51:
+ 677              	.L37:
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       }
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       /* Remove the floating point */
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       tmp = tmp / 10U;
+ 678              		.loc 1 491 7 is_stmt 1 view .LVU199
+ 679              		.loc 1 491 11 is_stmt 0 view .LVU200
+ 680 005a 134A     		ldr	r2, .L45+4
+ 681 005c A2FB0323 		umull	r2, r3, r2, r3
+ 682              	.LVL52:
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       /* Check the parity of the divider */
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       i2sodd = (tmp & (uint16_t)0x0001U);
+ 683              		.loc 1 494 7 is_stmt 1 view .LVU201
+ 684              		.loc 1 494 14 is_stmt 0 view .LVU202
+ 685 0060 C3F3C002 		ubfx	r2, r3, #3, #1
+ 686              	.LVL53:
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       /* Compute the i2sdiv prescaler */
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       i2sdiv = ((tmp - i2sodd) / 2U);
+ 687              		.loc 1 497 7 is_stmt 1 view .LVU203
+ 688              		.loc 1 497 22 is_stmt 0 view .LVU204
+ 689 0064 C2EBD303 		rsb	r3, r2, r3, lsr #3
+ 690              	.LVL54:
+ 691              		.loc 1 497 14 view .LVU205
+ 692 0068 5B08     		lsrs	r3, r3, #1
+ 693              	.LVL55:
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       i2sodd = (i2sodd << 8U);
+ 694              		.loc 1 500 7 is_stmt 1 view .LVU206
+ARM GAS  /tmp/cc532wt1.s 			page 84
+
+
+ 695              		.loc 1 500 14 is_stmt 0 view .LVU207
+ 696 006a 1202     		lsls	r2, r2, #8
+ 697              	.LVL56:
+ 698              	.L34:
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     }
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Test if the divider is 1 or 0 or greater than 0xFF */
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ 699              		.loc 1 504 5 is_stmt 1 view .LVU208
+ 700              		.loc 1 504 23 is_stmt 0 view .LVU209
+ 701 006c 991E     		subs	r1, r3, #2
+ 702              		.loc 1 504 8 view .LVU210
+ 703 006e FD29     		cmp	r1, #253
+ 704 0070 13D8     		bhi	.L42
+ 705 0072 1646     		mov	r6, r2
+ 706              	.LVL57:
+ 707              	.L38:
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     {
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       /* Set the default values */
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       i2sdiv = 2U;
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       i2sodd = 0U;
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     }
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     /* Write to SPIx I2SPR register the computed value */
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
+ 708              		.loc 1 512 5 is_stmt 1 view .LVU211
+ 709 0074 3343     		orrs	r3, r3, r6
+ 710              	.LVL58:
+ 711              		.loc 1 512 5 is_stmt 0 view .LVU212
+ 712 0076 EA68     		ldr	r2, [r5, #12]
+ 713 0078 1343     		orrs	r3, r3, r2
+ 714 007a 2362     		str	r3, [r4, #32]
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****     status = SUCCESS;
+ 715              		.loc 1 514 5 is_stmt 1 view .LVU213
+ 716              	.LVL59:
+ 717              		.loc 1 514 12 is_stmt 0 view .LVU214
+ 718 007c 0020     		movs	r0, #0
+ 719              	.LVL60:
+ 720              	.L33:
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   }
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   return status;
+ 721              		.loc 1 516 3 is_stmt 1 view .LVU215
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** }
+ 722              		.loc 1 517 1 is_stmt 0 view .LVU216
+ 723 007e F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 724              	.LVL61:
+ 725              	.L41:
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       }
+ 726              		.loc 1 470 22 view .LVU217
+ 727 0080 0227     		movs	r7, #2
+ 728 0082 D8E7     		b	.L35
+ 729              	.LVL62:
+ 730              	.L44:
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       }
+ 731              		.loc 1 482 9 is_stmt 1 view .LVU218
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       }
+ARM GAS  /tmp/cc532wt1.s 			page 85
+
+
+ 732              		.loc 1 482 32 is_stmt 0 view .LVU219
+ 733 0084 000A     		lsrs	r0, r0, #8
+ 734              	.LVL63:
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       }
+ 735              		.loc 1 482 40 view .LVU220
+ 736 0086 00EB8000 		add	r0, r0, r0, lsl #2
+ 737 008a 4300     		lsls	r3, r0, #1
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       }
+ 738              		.loc 1 482 63 view .LVU221
+ 739 008c 2869     		ldr	r0, [r5, #16]
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       }
+ 740              		.loc 1 482 47 view .LVU222
+ 741 008e B3FBF0F3 		udiv	r3, r3, r0
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       }
+ 742              		.loc 1 482 13 view .LVU223
+ 743 0092 0533     		adds	r3, r3, #5
+ 744              	.LVL64:
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       }
+ 745              		.loc 1 482 13 view .LVU224
+ 746 0094 E1E7     		b	.L37
+ 747              	.LVL65:
+ 748              	.L40:
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   uint32_t packetlength = 1U;
+ 749              		.loc 1 421 12 view .LVU225
+ 750 0096 3246     		mov	r2, r6
+ 751 0098 E8E7     		b	.L34
+ 752              	.LVL66:
+ 753              	.L42:
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       i2sodd = 0U;
+ 754              		.loc 1 507 14 view .LVU226
+ 755 009a 0223     		movs	r3, #2
+ 756              	.LVL67:
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****       i2sodd = 0U;
+ 757              		.loc 1 507 14 view .LVU227
+ 758 009c EAE7     		b	.L38
+ 759              	.LVL68:
+ 760              	.L39:
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 761              		.loc 1 425 15 view .LVU228
+ 762 009e 0120     		movs	r0, #1
+ 763              	.LVL69:
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 764              		.loc 1 425 15 view .LVU229
+ 765 00a0 EDE7     		b	.L33
+ 766              	.L46:
+ 767 00a2 00BF     		.align	2
+ 768              	.L45:
+ 769 00a4 C0F4FFFF 		.word	-2880
+ 770 00a8 CDCCCCCC 		.word	-858993459
+ 771              		.cfi_endproc
+ 772              	.LFE455:
+ 774              		.section	.text.LL_I2S_StructInit,"ax",%progbits
+ 775              		.align	1
+ 776              		.global	LL_I2S_StructInit
+ 777              		.syntax unified
+ 778              		.thumb
+ 779              		.thumb_func
+ARM GAS  /tmp/cc532wt1.s 			page 86
+
+
+ 780              		.fpu fpv5-d16
+ 782              	LL_I2S_StructInit:
+ 783              	.LVL70:
+ 784              	.LFB456:
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *         whose fields will be set to default values.
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @retval None
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** {
+ 785              		.loc 1 526 1 is_stmt 1 view -0
+ 786              		.cfi_startproc
+ 787              		@ args = 0, pretend = 0, frame = 0
+ 788              		@ frame_needed = 0, uses_anonymous_args = 0
+ 789              		@ link register save eliminated.
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   /*--------------- Reset I2S init structure parameters values -----------------*/
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
+ 790              		.loc 1 528 3 view .LVU231
+ 791              		.loc 1 528 37 is_stmt 0 view .LVU232
+ 792 0000 0023     		movs	r3, #0
+ 793 0002 0360     		str	r3, [r0]
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
+ 794              		.loc 1 529 3 is_stmt 1 view .LVU233
+ 795              		.loc 1 529 37 is_stmt 0 view .LVU234
+ 796 0004 4360     		str	r3, [r0, #4]
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
+ 797              		.loc 1 530 3 is_stmt 1 view .LVU235
+ 798              		.loc 1 530 37 is_stmt 0 view .LVU236
+ 799 0006 8360     		str	r3, [r0, #8]
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
+ 800              		.loc 1 531 3 is_stmt 1 view .LVU237
+ 801              		.loc 1 531 37 is_stmt 0 view .LVU238
+ 802 0008 C360     		str	r3, [r0, #12]
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
+ 803              		.loc 1 532 3 is_stmt 1 view .LVU239
+ 804              		.loc 1 532 37 is_stmt 0 view .LVU240
+ 805 000a 0222     		movs	r2, #2
+ 806 000c 0261     		str	r2, [r0, #16]
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
+ 807              		.loc 1 533 3 is_stmt 1 view .LVU241
+ 808              		.loc 1 533 37 is_stmt 0 view .LVU242
+ 809 000e 4361     		str	r3, [r0, #20]
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** }
+ 810              		.loc 1 534 1 view .LVU243
+ 811 0010 7047     		bx	lr
+ 812              		.cfi_endproc
+ 813              	.LFE456:
+ 815              		.section	.text.LL_I2S_ConfigPrescaler,"ax",%progbits
+ 816              		.align	1
+ 817              		.global	LL_I2S_ConfigPrescaler
+ 818              		.syntax unified
+ 819              		.thumb
+ 820              		.thumb_func
+ 821              		.fpu fpv5-d16
+ARM GAS  /tmp/cc532wt1.s 			page 87
+
+
+ 823              	LL_I2S_ConfigPrescaler:
+ 824              	.LVL71:
+ 825              	.LFB457:
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /**
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @brief  Set linear and parity prescaler.
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @param  SPIx SPI Instance
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @param  PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @param  PrescalerParity This parameter can be one of the following values:
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   * @retval None
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   */
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** {
+ 826              		.loc 1 548 1 is_stmt 1 view -0
+ 827              		.cfi_startproc
+ 828              		@ args = 0, pretend = 0, frame = 0
+ 829              		@ frame_needed = 0, uses_anonymous_args = 0
+ 830              		@ link register save eliminated.
+ 831              		.loc 1 548 1 is_stmt 0 view .LVU245
+ 832 0000 10B4     		push	{r4}
+ 833              	.LCFI6:
+ 834              		.cfi_def_cfa_offset 4
+ 835              		.cfi_offset 4, -4
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   /* Check the I2S parameters */
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ 836              		.loc 1 550 3 is_stmt 1 view .LVU246
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+ 837              		.loc 1 551 3 view .LVU247
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+ 838              		.loc 1 552 3 view .LVU248
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** 
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   /* Write to SPIx I2SPR */
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c ****   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8
+ 839              		.loc 1 555 3 view .LVU249
+ 840 0002 046A     		ldr	r4, [r0, #32]
+ 841 0004 044B     		ldr	r3, .L50
+ 842 0006 2340     		ands	r3, r3, r4
+ 843 0008 41EA0221 		orr	r1, r1, r2, lsl #8
+ 844              	.LVL72:
+ 845              		.loc 1 555 3 is_stmt 0 view .LVU250
+ 846 000c 0B43     		orrs	r3, r3, r1
+ 847 000e 0362     		str	r3, [r0, #32]
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** }
+ 848              		.loc 1 556 1 view .LVU251
+ 849 0010 5DF8044B 		ldr	r4, [sp], #4
+ 850              	.LCFI7:
+ 851              		.cfi_restore 4
+ 852              		.cfi_def_cfa_offset 0
+ 853 0014 7047     		bx	lr
+ 854              	.L51:
+ 855 0016 00BF     		.align	2
+ 856              	.L50:
+ 857 0018 00FEFFFF 		.word	-512
+ARM GAS  /tmp/cc532wt1.s 			page 88
+
+
+ 858              		.cfi_endproc
+ 859              	.LFE457:
+ 861              		.text
+ 862              	.Letext0:
+ 863              		.file 4 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 864              		.file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 865              		.file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 866              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+ARM GAS  /tmp/cc532wt1.s 			page 89
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_ll_spi.c
+     /tmp/cc532wt1.s:17     .text.LL_SPI_DeInit:0000000000000000 $t
+     /tmp/cc532wt1.s:25     .text.LL_SPI_DeInit:0000000000000000 LL_SPI_DeInit
+     /tmp/cc532wt1.s:292    .text.LL_SPI_DeInit:00000000000000b8 $d
+     /tmp/cc532wt1.s:303    .text.LL_SPI_Init:0000000000000000 $t
+     /tmp/cc532wt1.s:310    .text.LL_SPI_Init:0000000000000000 LL_SPI_Init
+     /tmp/cc532wt1.s:471    .text.LL_SPI_Init:0000000000000084 $d
+     /tmp/cc532wt1.s:477    .text.LL_SPI_StructInit:0000000000000000 $t
+     /tmp/cc532wt1.s:484    .text.LL_SPI_StructInit:0000000000000000 LL_SPI_StructInit
+     /tmp/cc532wt1.s:531    .text.LL_I2S_DeInit:0000000000000000 $t
+     /tmp/cc532wt1.s:538    .text.LL_I2S_DeInit:0000000000000000 LL_I2S_DeInit
+     /tmp/cc532wt1.s:561    .text.LL_I2S_Init:0000000000000000 $t
+     /tmp/cc532wt1.s:568    .text.LL_I2S_Init:0000000000000000 LL_I2S_Init
+     /tmp/cc532wt1.s:769    .text.LL_I2S_Init:00000000000000a4 $d
+     /tmp/cc532wt1.s:775    .text.LL_I2S_StructInit:0000000000000000 $t
+     /tmp/cc532wt1.s:782    .text.LL_I2S_StructInit:0000000000000000 LL_I2S_StructInit
+     /tmp/cc532wt1.s:816    .text.LL_I2S_ConfigPrescaler:0000000000000000 $t
+     /tmp/cc532wt1.s:823    .text.LL_I2S_ConfigPrescaler:0000000000000000 LL_I2S_ConfigPrescaler
+     /tmp/cc532wt1.s:857    .text.LL_I2S_ConfigPrescaler:0000000000000018 $d
+
+UNDEFINED SYMBOLS
+LL_RCC_GetI2SClockFreq
diff --git a/build/stm32f7xx_ll_spi.o b/build/stm32f7xx_ll_spi.o
new file mode 100644
index 0000000..d004b39
Binary files /dev/null and b/build/stm32f7xx_ll_spi.o differ
diff --git a/build/stm32f7xx_ll_tim.d b/build/stm32f7xx_ll_tim.d
new file mode 100644
index 0000000..42a7842
--- /dev/null
+++ b/build/stm32f7xx_ll_tim.d
@@ -0,0 +1,68 @@
+build/stm32f7xx_ll_tim.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
diff --git a/build/stm32f7xx_ll_tim.lst b/build/stm32f7xx_ll_tim.lst
new file mode 100644
index 0000000..4f5ac25
--- /dev/null
+++ b/build/stm32f7xx_ll_tim.lst
@@ -0,0 +1,11765 @@
+ARM GAS  /tmp/ccI26Lsx.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_ll_tim.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.OC1Config,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	OC1Config:
+  25              	.LVL0:
+  26              	.LFB391:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @file    stm32f7xx_ll_tim.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief   TIM LL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(USE_FULL_LL_DRIVER)
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Includes ------------------------------------------------------------------*/
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #include "stm32f7xx_ll_tim.h"
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #include "stm32f7xx_ll_bus.h"
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #ifdef  USE_FULL_ASSERT
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #include "stm32_assert.h"
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #else
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define assert_param(expr) ((void)0U)
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* USE_FULL_ASSERT */
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @{
+ARM GAS  /tmp/ccI26Lsx.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defi
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup TIM_LL
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Private constants ---------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Private macros ------------------------------------------------------------*/
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup TIM_LL_Private_Macros
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @{
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                      || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                          || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+ARM GAS  /tmp/ccI26Lsx.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                                   || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                          || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                          || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                           || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                              || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
+ARM GAS  /tmp/ccI26Lsx.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                            || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                               || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****                                                      || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENAB
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @}
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Private function prototypes -----------------------------------------------*/
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @defgroup TIM_LL_Private_Functions TIM Private Functions
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @{
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @}
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Exported functions --------------------------------------------------------*/
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup TIM_LL_Exported_Functions
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @{
+ARM GAS  /tmp/ccI26Lsx.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup TIM_LL_EF_Init
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @{
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Set TIMx registers to their reset values.
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer instance
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: invalid TIMx instance
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   ErrorStatus result = SUCCESS;
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_INSTANCE(TIMx));
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   if (TIMx == TIM1)
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM2)
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM3)
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM3)
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM3 */
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM4)
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM4)
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM4 */
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM5)
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM5)
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM5 */
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM6)
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM6)
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ARM GAS  /tmp/ccI26Lsx.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM6 */
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined (TIM7)
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM7)
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM7 */
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM8)
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM8)
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM8 */
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM9)
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM9)
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM9 */
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM10)
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM10)
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM10 */
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM11)
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM11)
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM11 */
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM12)
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM12)
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM12 */
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM13)
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM13)
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM13 */
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM14)
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else if (TIMx == TIM14)
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM14 */
+ARM GAS  /tmp/ccI26Lsx.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   else
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     result = ERROR;
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return result;
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Set the fields of the time base unit configuration data structure
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         to their default values.
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configura
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval None
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->RepetitionCounter = 0x00000000U;
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx time base unit.
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         (TIMx time base unit configuration data structure)
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpcr1;
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_INSTANCE(TIMx));
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Select the Counter Mode */
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the clock division */
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CR1 */
+ARM GAS  /tmp/ccI26Lsx.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Autoreload value */
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Prescaler value */
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the Repetition Counter value */
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Generate an update event to reload the Prescaler
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****      and the repetition counter value (if applicable) immediately */
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_GenerateEvent_UPDATE(TIMx);
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Set the fields of the TIMx output channel configuration data
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         structure to their default values.
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         (the output channel configuration data structure)
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval None
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->CompareValue = 0x00000000U;
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx output channel.
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  Channel This parameter can be one of the following values:
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channe
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         data structure)
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx output channel is initialized
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: TIMx output channel is not initialized
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ARM GAS  /tmp/ccI26Lsx.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   ErrorStatus result = ERROR;
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   switch (Channel)
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH1:
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       result = OC1Config(TIMx, TIM_OC_InitStruct);
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH2:
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       result = OC2Config(TIMx, TIM_OC_InitStruct);
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH3:
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       result = OC3Config(TIMx, TIM_OC_InitStruct);
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH4:
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       result = OC4Config(TIMx, TIM_OC_InitStruct);
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH5:
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       result = OC5Config(TIMx, TIM_OC_InitStruct);
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH6:
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       result = OC6Config(TIMx, TIM_OC_InitStruct);
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     default:
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return result;
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Set the fields of the TIMx input channel configuration data
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         structure to their default values.
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel c
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         data structure)
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval None
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx input channel.
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  Channel This parameter can be one of the following values:
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         structure)
+ARM GAS  /tmp/ccI26Lsx.s 			page 10
+
+
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx output channel is initialized
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: TIMx output channel is not initialized
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   ErrorStatus result = ERROR;
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   switch (Channel)
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH1:
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       result = IC1Config(TIMx, TIM_IC_InitStruct);
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH2:
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       result = IC2Config(TIMx, TIM_IC_InitStruct);
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH3:
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       result = IC3Config(TIMx, TIM_IC_InitStruct);
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH4:
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       result = IC4Config(TIMx, TIM_IC_InitStruct);
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     default:
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return result;
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Fills each TIM_EncoderInitStruct field with its default value
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder i
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         configuration data structure)
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval None
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the encoder interface of the timer instance.
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx enco
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         configuration data structure)
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+ARM GAS  /tmp/ccI26Lsx.s 			page 11
+
+
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderIni
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccmr1;
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccer;
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCMR1 register value */
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCER register value */
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Configure TI1 */
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Configure TI2 */
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set encoder mode */
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCMR1 */
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCER */
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 12
+
+
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         structure to their default values.
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HAL
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         configuration data structure)
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval None
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the Hall sensor interface of the timer instance.
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *       to the TI1 input channel
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @note TIMx slave mode controller is configured in reset mode.
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****           Selected internal trigger is TI1F_ED.
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *       between 2 changes on the inputs. It gives information about motor speed.
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @note Channel 2 is configured in output PWM 2 mode.
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @note OC2REF is selected as trigger output on TRGO.
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *       when TIMx operates in Hall sensor interface mode.
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIM
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         interface configuration data structure)
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_Hall
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpcr2;
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccmr1;
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccer;
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpsmcr;
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CR2 register value */
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCMR1 register value */
+ARM GAS  /tmp/ccI26Lsx.s 			page 13
+
+
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCER register value */
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx SMCR register value */
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpcr2 |= TIM_CR2_TI1S;
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* OC2REF signal is used as trigger output (TRGO) */
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpcr2 |= LL_TIM_TRGO_OC2REF;
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Configure the slave mode controller */
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpsmcr |= LL_TIM_TS_TI1F_ED;
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Configure input channel 1 */
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Configure input channel 2 */
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CR2 */
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx SMCR */
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCMR1 */
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCER */
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCR2 */
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Set the fields of the Break and Dead Time configuration data structure
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         to their default values.
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead 
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         data structure)
+ARM GAS  /tmp/ccI26Lsx.s 			page 14
+
+
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval None
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the Break and Dead Time feature of the timer instance.
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *  can be necessary to configure all of them during the first write access to
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *  the TIMx_BDTR register.
+ 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *       a timer instance provides a break input.
+ 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *       a timer instance provides a second break input.
+ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+ 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead 
+ 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *         data structure)
+ 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: Break and Dead Time is initialized
+ 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+ 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpbdtr = 0;
+ 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the BDTR bits */
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+ARM GAS  /tmp/ccI26Lsx.s 			page 15
+
+
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   if (IS_TIM_BKIN2_INSTANCE(TIMx))
+ 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the BREAK2 input related BDTR bit-fields */
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+ 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set TIMx_BDTR */
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @}
+ 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @}
+ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+ 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *  @brief   Private functions
+ 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @{
+ 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx output channel 1.
+ 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+ 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+ 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+ 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+ 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+ 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+  28              		.loc 1 816 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  33              		.loc 1 816 1 is_stmt 0 view .LVU1
+  34 0000 70B4     		push	{r4, r5, r6}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 12
+  37              		.cfi_offset 4, -12
+  38              		.cfi_offset 5, -8
+  39              		.cfi_offset 6, -4
+ 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccmr1;
+ARM GAS  /tmp/ccI26Lsx.s 			page 16
+
+
+  40              		.loc 1 817 3 is_stmt 1 view .LVU2
+ 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccer;
+  41              		.loc 1 818 3 view .LVU3
+ 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpcr2;
+  42              		.loc 1 819 3 view .LVU4
+ 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  43              		.loc 1 822 3 view .LVU5
+ 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  44              		.loc 1 823 3 view .LVU6
+ 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  45              		.loc 1 824 3 view .LVU7
+ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+  46              		.loc 1 825 3 view .LVU8
+ 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the Channel 1: Reset the CC1E Bit */
+ 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+  47              		.loc 1 828 3 view .LVU9
+  48 0002 036A     		ldr	r3, [r0, #32]
+  49 0004 23F00103 		bic	r3, r3, #1
+  50 0008 0362     		str	r3, [r0, #32]
+ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCER register value */
+ 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+  51              		.loc 1 831 3 view .LVU10
+  52              		.loc 1 831 11 is_stmt 0 view .LVU11
+  53 000a 036A     		ldr	r3, [r0, #32]
+  54              	.LVL1:
+ 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CR2 register value */
+ 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+  55              		.loc 1 834 3 is_stmt 1 view .LVU12
+  56              		.loc 1 834 10 is_stmt 0 view .LVU13
+  57 000c 4268     		ldr	r2, [r0, #4]
+  58              	.LVL2:
+ 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCMR1 register value */
+ 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+  59              		.loc 1 837 3 is_stmt 1 view .LVU14
+  60              		.loc 1 837 12 is_stmt 0 view .LVU15
+  61 000e 8569     		ldr	r5, [r0, #24]
+  62              	.LVL3:
+ 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Reset Capture/Compare selection Bits */
+ 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+  63              		.loc 1 840 3 is_stmt 1 view .LVU16
+ 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output Compare Mode */
+ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+  64              		.loc 1 843 3 view .LVU17
+  65 0010 164C     		ldr	r4, .L4
+  66 0012 2C40     		ands	r4, r4, r5
+  67 0014 0D68     		ldr	r5, [r1]
+  68              	.LVL4:
+  69              		.loc 1 843 3 is_stmt 0 view .LVU18
+  70 0016 2C43     		orrs	r4, r4, r5
+ARM GAS  /tmp/ccI26Lsx.s 			page 17
+
+
+  71              	.LVL5:
+ 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output Compare Polarity */
+ 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+  72              		.loc 1 846 3 is_stmt 1 view .LVU19
+  73 0018 23F00203 		bic	r3, r3, #2
+  74              	.LVL6:
+  75              		.loc 1 846 3 is_stmt 0 view .LVU20
+  76 001c 0D69     		ldr	r5, [r1, #16]
+  77 001e 2B43     		orrs	r3, r3, r5
+  78              	.LVL7:
+ 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output State */
+ 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+  79              		.loc 1 849 3 is_stmt 1 view .LVU21
+  80 0020 23F00103 		bic	r3, r3, #1
+  81              	.LVL8:
+  82              		.loc 1 849 3 is_stmt 0 view .LVU22
+  83 0024 4D68     		ldr	r5, [r1, #4]
+  84 0026 2B43     		orrs	r3, r3, r5
+  85              	.LVL9:
+ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+  86              		.loc 1 851 3 is_stmt 1 view .LVU23
+  87              		.loc 1 851 6 is_stmt 0 view .LVU24
+  88 0028 114E     		ldr	r6, .L4+4
+  89 002a 124D     		ldr	r5, .L4+8
+  90 002c A842     		cmp	r0, r5
+  91 002e 18BF     		it	ne
+  92 0030 B042     		cmpne	r0, r6
+  93 0032 12D1     		bne	.L2
+ 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+  94              		.loc 1 853 5 is_stmt 1 view .LVU25
+ 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+  95              		.loc 1 854 5 view .LVU26
+ 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+  96              		.loc 1 855 5 view .LVU27
+ 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+  97              		.loc 1 856 5 view .LVU28
+ 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the complementary output Polarity */
+ 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
+  98              		.loc 1 859 5 view .LVU29
+  99 0034 23F00803 		bic	r3, r3, #8
+ 100              	.LVL10:
+ 101              		.loc 1 859 5 is_stmt 0 view .LVU30
+ 102 0038 4D69     		ldr	r5, [r1, #20]
+ 103 003a 43EA8503 		orr	r3, r3, r5, lsl #2
+ 104              	.LVL11:
+ 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the complementary output State */
+ 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
+ 105              		.loc 1 862 5 is_stmt 1 view .LVU31
+ 106 003e 23F00403 		bic	r3, r3, #4
+ 107              	.LVL12:
+ 108              		.loc 1 862 5 is_stmt 0 view .LVU32
+ARM GAS  /tmp/ccI26Lsx.s 			page 18
+
+
+ 109 0042 8D68     		ldr	r5, [r1, #8]
+ 110              		.loc 1 862 5 view .LVU33
+ 111 0044 43EA8503 		orr	r3, r3, r5, lsl #2
+ 112              	.LVL13:
+ 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the Output Idle state */
+ 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
+ 113              		.loc 1 865 5 is_stmt 1 view .LVU34
+ 114 0048 22F48072 		bic	r2, r2, #256
+ 115              	.LVL14:
+ 116              		.loc 1 865 5 is_stmt 0 view .LVU35
+ 117 004c 8D69     		ldr	r5, [r1, #24]
+ 118 004e 2A43     		orrs	r2, r2, r5
+ 119              	.LVL15:
+ 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the complementary output Idle state */
+ 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
+ 120              		.loc 1 868 5 is_stmt 1 view .LVU36
+ 121 0050 22F40072 		bic	r2, r2, #512
+ 122              	.LVL16:
+ 123              		.loc 1 868 5 is_stmt 0 view .LVU37
+ 124 0054 CD69     		ldr	r5, [r1, #28]
+ 125 0056 42EA4502 		orr	r2, r2, r5, lsl #1
+ 126              	.LVL17:
+ 127              	.L2:
+ 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CR2 */
+ 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+ 128              		.loc 1 872 3 is_stmt 1 view .LVU38
+ 129 005a 4260     		str	r2, [r0, #4]
+ 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCMR1 */
+ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+ 130              		.loc 1 875 3 view .LVU39
+ 131 005c 8461     		str	r4, [r0, #24]
+ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Capture Compare Register value */
+ 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+ 132              		.loc 1 878 3 view .LVU40
+ 133 005e CA68     		ldr	r2, [r1, #12]
+ 134              	.LVL18:
+ 135              	.LBB82:
+ 136              	.LBI82:
+ 137              		.file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @file    stm32f7xx_ll_tim.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief   Header file of TIM LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * This software is licensed under terms that can be found in the LICENSE file
+ARM GAS  /tmp/ccI26Lsx.s 			page 19
+
+
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifndef __STM32F7xx_LL_TIM_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __STM32F7xx_LL_TIM_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defi
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL TIM
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] =
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 0: TIMx_CH1  */
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 1: TIMx_CH1N */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 2: TIMx_CH2  */
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x00U,   /* 3: TIMx_CH2N */
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x04U,   /* 4: TIMx_CH3  */
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x04U,   /* 5: TIMx_CH3N */
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x04U,   /* 6: TIMx_CH4  */
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x3CU,   /* 7: TIMx_CH5  */
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0x3CU    /* 8: TIMx_CH6  */
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] =
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: OC1M, OC1FE, OC1PE */
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 1: - NA */
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 2: OC2M, OC2FE, OC2PE */
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 3: - NA */
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 4: OC3M, OC3FE, OC3PE */
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 5: - NA */
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 6: OC4M, OC4FE, OC4PE */
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 7: OC5M, OC5FE, OC5PE */
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U             /* 8: OC6M, OC6FE, OC6PE */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+ARM GAS  /tmp/ccI26Lsx.s 			page 20
+
+
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] =
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: CC1S, IC1PSC, IC1F */
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 1: - NA */
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 2: CC2S, IC2PSC, IC2F */
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 3: - NA */
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 4: CC3S, IC3PSC, IC3F */
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 5: - NA */
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 6: CC4S, IC4PSC, IC4F */
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 7: - NA */
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U             /* 8: - NA */
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] =
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: CC1P */
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   2U,            /* 1: CC1NP */
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   4U,            /* 2: CC2P */
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   6U,            /* 3: CC2NP */
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 4: CC3P */
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   10U,           /* 5: CC3NP */
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   12U,           /* 6: CC4P */
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   16U,           /* 7: CC5P */
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   20U            /* 8: CC6P */
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OISx[] =
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   0U,            /* 0: OIS1 */
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   1U,            /* 1: OIS1N */
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   2U,            /* 2: OIS2 */
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   3U,            /* 3: OIS2N */
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   4U,            /* 4: OIS3 */
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   5U,            /* 5: OIS3N */
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   6U,            /* 6: OIS4 */
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   8U,            /* 7: OIS5 */
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   10U            /* 8: OIS6 */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** };
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if   defined(TIM_BREAK_INPUT_SUPPORT)
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Defines used for the bit position in the register and perform offsets */
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_POSITION_BRK_SOURCE           (POSITION_VAL(Source) & 0x1FUL)
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Generic bit definitions for TIMx_AF1 register */
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_AF1_BKINP        TIM1_AF1_BKINP       /*!< BRK BKIN input polarity */
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Remap mask definitions */
+ARM GAS  /tmp/ccI26Lsx.s 			page 21
+
+
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_SHIFT  16U
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_MASK   0x0000FFFFU
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM2_OR_RMP_MASK   (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM5_OR_RMP_MASK   (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM11_OR_RMP_MASK  (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_1 ((uint8_t)0x7F)
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_2 ((uint8_t)0x3F)
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_3 ((uint8_t)0x1F)
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_4 ((uint8_t)0x1F)
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_1 ((uint8_t)0x00)
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_2 ((uint8_t)0x80)
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_3 ((uint8_t)0xC0)
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_4 ((uint8_t)0xE0)
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief  Convert channel id into channel index.
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CHANNEL__ This parameter can be one of the following values:
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval none
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief  Calculate the deadtime sampling period(in ps).
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz).
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CKD__ This parameter can be one of the following values:
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval none
+ARM GAS  /tmp/ccI26Lsx.s 			page 22
+
+
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****    ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Time Base configuration structure definition.
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter can be a number between Min_Data=0x0000 and Max_D
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetPrescaler().*/
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t CounterMode;       /*!< Specifies the counter mode.
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetCounterMode().*/
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Auto-Reload Register at the next update event.
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter must be a number between Min_Data=0x0000 and Max_
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Some timer instances may support 32 bits counters. In that case 
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    be a number between 0x0000 and 0xFFFFFFFF.
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetAutoReload().*/
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ClockDivision;     /*!< Specifies the clock division.
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetClockDivision().*/
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downc
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    reaches zero, an update event is generated and counting restarts
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    from the RCR value (N).
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This means in PWM mode that (N+1) corresponds to:
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       - the number of PWM periods in edge-aligned mode
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       - the number of half PWM period in center-aligned mode
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    GP timers: this parameter must be a number between Min_Data = 0x
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Max_Data = 0xFF.
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Advanced timers: this parameter must be a number between Min_Dat
+ARM GAS  /tmp/ccI26Lsx.s 			page 23
+
+
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    Max_Data = 0xFFFF.
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    This feature can be modified afterwards using unitary function
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                    @ref LL_TIM_SetRepetitionCounter().*/
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_InitTypeDef;
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Output Compare configuration structure definition.
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCMode;        /*!< Specifies the output mode.
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetMode().*/
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary functions
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary functions
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Re
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a number between Min_Data=0x0000 and Max_Data=
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                LL_TIM_OC_SetCompareCHx (x=1..6).*/
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCPolarity;    /*!< Specifies the output polarity.
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetPolarity().*/
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetPolarity().*/
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetIdleState().*/
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 24
+
+
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_OC_SetIdleState().*/
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef;
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Input Capture configuration structure definition.
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetPolarity().*/
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICActiveInput; /*!< Specifies the input.
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetActiveInput().*/
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetPrescaler().*/
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t ICFilter;      /*!< Specifies the input capture filter.
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                This feature can be modified afterwards using unitary function
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                @ref LL_TIM_IC_SetFilter().*/
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef;
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Encoder interface configuration structure definition.
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_SetEncoderMode().*/
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPolarity().*/
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 25
+
+
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetActiveInput().*/
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPrescaler().*/
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetFilter().*/
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPolarity().*/
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetActiveInput().*/
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetPrescaler().*/
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  This feature can be modified afterwards using unitary function
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                  @ref LL_TIM_IC_SetFilter().*/
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef;
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  TIM Hall sensor interface configuration structure definition.
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_IC_SetPolarity().*/
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     Prescaler must be set to get a maximum counter period longer th
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     time interval between 2 consecutive changes on the Hall inputs.
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+ARM GAS  /tmp/ccI26Lsx.s 			page 26
+
+
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_IC_SetPrescaler().*/
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a value of
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref TIM_LL_EC_IC_FILTER.
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_IC_SetFilter().*/
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compa
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     A positive pulse (TRGO event) is generated with a programmable 
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     a change occurs on the Hall inputs.
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This parameter can be a number between Min_Data = 0x0000 and Ma
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     This feature can be modified afterwards using unitary function
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                     @ref LL_TIM_OC_SetCompareCH2().*/
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_HALLSENSOR_InitTypeDef;
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  BDTR (Break and Dead Time) structure definition
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_SetOffStates()
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field cannot be modified as long as LOCK level
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                        programmed. */
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_SetOffStates()
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field cannot be modified as long as LOCK level
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note The LOCK bits can be written only once after the reset.
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       register has been written, their content is frozen until the 
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       switching-on of the outputs.
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a number between Min_Data = 0x00 and Ma
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_OC_SetDeadTime()
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ARM GAS  /tmp/ccI26Lsx.s 			page 27
+
+
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                        programmed. */
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARIT
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK()
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK()
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARI
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK2()
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_ConfigBRK2()
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled
+ARM GAS  /tmp/ccI26Lsx.s 			page 28
+
+
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTP
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       This feature can be modified afterwards using unitary functio
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAut
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       @note This bit-field can not be modified as long as LOCK leve
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       programmed. */
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_BDTR_InitTypeDef;
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrup
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrup
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrup
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrup
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrup
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrup
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt fla
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapt
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapt
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapt
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapt
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt fla
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
+ARM GAS  /tmp/ccI26Lsx.s 			page 29
+
+
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by 
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by softw
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrup
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrup
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrup
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrup
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable *
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/unde
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at 
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at 
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!< Counter used as upcounter 
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounte
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and 
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!< The counter counts up and 
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and 
+ARM GAS  /tmp/ccI26Lsx.s 			page 30
+
+
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down 
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bi
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bi
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when 
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CHANNEL Channel
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output ch
+ARM GAS  /tmp/ccI26Lsx.s 			page 31
+
+
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output ch
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output ch
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** Legacy definitions for compatibility purpose
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @cond 0
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @endcond
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FROZEN                   0x00000000U                                         
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                    
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                    
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)               
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                    
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)               
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)               
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                    
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)               
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)               
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                 
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+ARM GAS  /tmp/ccI26Lsx.s 			page 32
+
+
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!__REG__, (__VAL
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Read a value in TIM register.
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __INSTANCE__ TIM Instance
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __REG__ Register to be read
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Register value
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        to TIMx_CNT register bit 31)
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CNT__ Counter value
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval UIF status bit
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested de
+ARM GAS  /tmp/ccI26Lsx.s 			page 40
+
+
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CKD__ This parameter can be one of the following values:
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __DT__ deadtime duration (in ns)
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval DTG[0:7]
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__C
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                  (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) 
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__C
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                  (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) 
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                  (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) 
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     0U)
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock freq
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __CNTCLK__ counter clock frequency (in Hz)
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal fr
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PSC__ prescaler
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __FREQ__ output signal frequency (in Hz)
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the compare value required to achieve the required timer outpu
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         active/inactive delay.
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PSC__ prescaler
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __DELAY__ timer output compare active/inactive delay (in us)
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 41
+
+
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (when the timer operates in one pulse mode).
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __TIMCLK__ timer input clock frequency (in Hz)
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PSC__ prescaler
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __DELAY__ timer output compare active/inactive delay (in us)
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __PULSE__ pulse duration (in us)
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****               + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  __ICPSC__ This parameter can be one of the following values:
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV2
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV4
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV8
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable timer counter.
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable timer counter.
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/ccI26Lsx.s 			page 42
+
+
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the timer counter is enabled.
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable update event generation.
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable update event generation.
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether update event generation is enabled.
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Inverted state of bit (0 or 1).
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set update event source
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       generate an update interrupt or DMA request if enabled:
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        - Counter overflow/underflow
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        - Setting the UG bit
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *        - Update generation through the slave mode controller
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+ARM GAS  /tmp/ccI26Lsx.s 			page 43
+
+
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       overflow/underflow generates an update interrupt or DMA request if enabled.
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  UpdateSource This parameter can be one of the following values:
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual event update source
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set one pulse mode (one shot v.s. repetitive).
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  OnePulseMode This parameter can be one of the following values:
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual one pulse mode.
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the timer counter counting mode.
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       check whether or not the counter mode selection feature is supported
+ARM GAS  /tmp/ccI26Lsx.s 			page 44
+
+
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       by a timer instance.
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       requires a timer reset to avoid unexpected direction
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       due to DIR bit readonly in center aligned mode.
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR1          CMS           LL_TIM_SetCounterMode
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CounterMode This parameter can be one of the following values:
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_UP
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual counter mode.
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       check whether or not the counter mode selection feature is supported
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       by a timer instance.
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR1          CMS           LL_TIM_GetCounterMode
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_UP
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t counter_mode;
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   if (counter_mode == 0U)
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   {
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****     counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   }
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return counter_mode;
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable auto-reload (ARR) preload.
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ARM GAS  /tmp/ccI26Lsx.s 			page 45
+
+
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable auto-reload (ARR) preload.
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (when supported) and the digital filters.
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not the clock division feature is supported by the timer
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       instance.
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ClockDivision This parameter can be one of the following values:
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by t
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         generators (when supported) and the digital filters.
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not the clock division feature is supported by the timer
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       instance.
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/ccI26Lsx.s 			page 46
+
+
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the counter value.
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CNT          CNT           LL_TIM_SetCounter
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CNT, Counter);
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the counter value.
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CNT          CNT           LL_TIM_GetCounter
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CNT));
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current direction of the counter
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          DIR           LL_TIM_GetDirection
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the prescaler value.
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The prescaler can be changed on the fly as this control register is buffered. The new
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       prescaler ratio is taken into account at the next update event.
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Prescaler between Min_Data=0 and Max_Data=65535
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+ARM GAS  /tmp/ccI26Lsx.s 			page 47
+
+
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->PSC, Prescaler);
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the prescaler value.
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->PSC));
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the auto-reload value.
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The counter is blocked while the auto-reload value is null.
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  AutoReload between Min_Data=0 and Max_Data=65535
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->ARR, AutoReload);
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the auto-reload value.
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Auto-reload value
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->ARR));
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the repetition counter value.
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note For advanced timer instances RepetitionCounter can be up to 65535.
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a repetition counter.
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->RCR, RepetitionCounter);
+ARM GAS  /tmp/ccI26Lsx.s 			page 48
+
+
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the repetition counter value.
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a repetition counter.
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Repetition counter value
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->RCR));
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter regis
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This allows both the counter value and a potential roll-over condition signalled by the U
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       in an atomic way.
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable update interrupt flag (UIF) remapping.
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether update interrupt flag (UIF) copy is set.
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Counter Counter value
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ARM GAS  /tmp/ccI26Lsx.s 			page 49
+
+
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       they are updated only when a commutation event (COM) occurs.
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Only on channels that have a complementary output.
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance is able to generate a commutation event.
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance is able to generate a commutation event.
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is en
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCPC          LL_TIM_CC_IsEnabledPreload
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance is able to generate a commutation event.
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CCUpdateSource This parameter can be one of the following values:
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the trigger of the capture/compare DMA request.
+ARM GAS  /tmp/ccI26Lsx.s 			page 50
+
+
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DMAReqTrigger This parameter can be one of the following values:
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get actual trigger of the capture/compare DMA request.
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the lock level to freeze the
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         configuration of several capture/compare parameters.
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       the lock mechanism is supported by a timer instance.
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  LockLevel This parameter can be one of the following values:
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_1
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_2
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_LOCKLEVEL_3
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable capture/compare channels.
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
+1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
+1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6E          LL_TIM_CC_EnableChannel
+1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channels This parameter can be a combination of the following values:
+ARM GAS  /tmp/ccI26Lsx.s 			page 51
+
+
+1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CCER, Channels);
+1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable capture/compare channels.
+1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
+1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
+1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6E          LL_TIM_CC_DisableChannel
+1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channels This parameter can be a combination of the following values:
+1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CCER, Channels);
+1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether channel(s) is(are) enabled.
+1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
+1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
+1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
+1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+ARM GAS  /tmp/ccI26Lsx.s 			page 52
+
+
+1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channels This parameter can be a combination of the following values:
+1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
+1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure an output channel.
+1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
+1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
+1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
+1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
+1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
+1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
+1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2          OIS6          LL_TIM_OC_ConfigOutput
+1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Configuration This parameter must be a combination of all the following values:
+1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/ccI26Lsx.s 			page 53
+
+
+1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura
+1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Define the behavior of the output reference signal OCxREF from which
+1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         OCx and OCxN (when relevant) are derived.
+1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
+1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
+1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6M          LL_TIM_OC_SetMode
+1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Mode This parameter can be one of the following values:
+1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FROZEN
+1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ACTIVE
+1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_INACTIVE
+1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_TOGGLE
+1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM1
+1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM2
+1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT
+2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the output compare mode of an output channel.
+2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 54
+
+
+2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
+2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
+2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6M          LL_TIM_OC_GetMode
+2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FROZEN
+2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ACTIVE
+2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_INACTIVE
+2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_TOGGLE
+2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM1
+2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_PWM2
+2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
+2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT
+2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the polarity of an output channel.
+2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
+2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
+2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6P          LL_TIM_OC_SetPolarity
+2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Polarity This parameter can be one of the following values:
+ARM GAS  /tmp/ccI26Lsx.s 			page 55
+
+
+2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_LOW
+2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[i
+2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the polarity of an output channel.
+2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
+2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
+2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC6P          LL_TIM_OC_GetPolarity
+2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCPOLARITY_LOW
+2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan
+2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the IDLE state of an output channel
+2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function is significant only for the timer instances
+2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       can be used to check whether or not a timer instance provides
+2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a break input.
+2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
+2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
+2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS6          LL_TIM_OC_SetIdleState
+ARM GAS  /tmp/ccI26Lsx.s 			page 56
+
+
+2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  IdleState This parameter can be one of the following values:
+2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState
+2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iC
+2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the IDLE state of an output channel
+2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
+2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CR2         OIS6          LL_TIM_OC_GetIdleState
+2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1N
+2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2N
+2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3N
+2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
+2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChanne
+2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable fast mode for the output channel.
+2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+ARM GAS  /tmp/ccI26Lsx.s 			page 57
+
+
+2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
+2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
+2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
+2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable fast mode for the output channel.
+2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
+2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
+2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
+2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether fast mode is enabled for the output channel.
+2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 58
+
+
+2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
+2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
+2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
+2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
+2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
+2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
+2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
+2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
+2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+ARM GAS  /tmp/ccI26Lsx.s 			page 59
+
+
+2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe
+2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
+2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
+2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
+2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable clearing the output channel on an external event.
+2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function can only be used in Output compare and PWM modes. It does not work in Force
+2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance can clear the OCxREF signal on an external event.
+2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
+2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
+2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
+2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+ARM GAS  /tmp/ccI26Lsx.s 			page 60
+
+
+2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable clearing the output channel on an external event.
+2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance can clear the OCxREF signal on an external event.
+2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
+2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
+2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
+2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates clearing the output channel on an external event is enabled for the output ch
+2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function enables clearing the output channel on an external event.
+2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note This function can only be used in Output compare and PWM modes. It does not work in Force
+2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance can clear the OCxREF signal on an external event.
+2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
+2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
+2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH5
+2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH6
+2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+ARM GAS  /tmp/ccI26Lsx.s 			page 61
+
+
+2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
+2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal an
+2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         the Ocx and OCxN signals).
+2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       dead-time insertion feature is supported by a timer instance.
+2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DeadTime between Min_Data=0 and Max_Data=255
+2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 1 is supported by a timer instance.
+2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+ 138              		.loc 2 2444 22 view .LVU41
+ 139              	.LBB83:
+2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR1, CompareValue);
+ 140              		.loc 2 2446 3 view .LVU42
+ 141 0060 4263     		str	r2, [r0, #52]
+ 142              	.LVL19:
+ 143              		.loc 2 2446 3 is_stmt 0 view .LVU43
+ 144              	.LBE83:
+ 145              	.LBE82:
+ 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCER */
+ 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+ 146              		.loc 1 881 3 is_stmt 1 view .LVU44
+ 147 0062 0362     		str	r3, [r0, #32]
+ 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 148              		.loc 1 883 3 view .LVU45
+ 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ARM GAS  /tmp/ccI26Lsx.s 			page 62
+
+
+ 149              		.loc 1 884 1 is_stmt 0 view .LVU46
+ 150 0064 0020     		movs	r0, #0
+ 151              	.LVL20:
+ 152              		.loc 1 884 1 view .LVU47
+ 153 0066 70BC     		pop	{r4, r5, r6}
+ 154              	.LCFI1:
+ 155              		.cfi_restore 6
+ 156              		.cfi_restore 5
+ 157              		.cfi_restore 4
+ 158              		.cfi_def_cfa_offset 0
+ 159              	.LVL21:
+ 160              		.loc 1 884 1 view .LVU48
+ 161 0068 7047     		bx	lr
+ 162              	.L5:
+ 163 006a 00BF     		.align	2
+ 164              	.L4:
+ 165 006c 8CFFFEFF 		.word	-65652
+ 166 0070 00000140 		.word	1073807360
+ 167 0074 00040140 		.word	1073808384
+ 168              		.cfi_endproc
+ 169              	.LFE391:
+ 171              		.section	.text.OC2Config,"ax",%progbits
+ 172              		.align	1
+ 173              		.syntax unified
+ 174              		.thumb
+ 175              		.thumb_func
+ 176              		.fpu fpv5-d16
+ 178              	OC2Config:
+ 179              	.LVL22:
+ 180              	.LFB392:
+ 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx output channel 2.
+ 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+ 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+ 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+ 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+ 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+ 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+ 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 181              		.loc 1 895 1 is_stmt 1 view -0
+ 182              		.cfi_startproc
+ 183              		@ args = 0, pretend = 0, frame = 0
+ 184              		@ frame_needed = 0, uses_anonymous_args = 0
+ 185              		@ link register save eliminated.
+ 186              		.loc 1 895 1 is_stmt 0 view .LVU50
+ 187 0000 70B4     		push	{r4, r5, r6}
+ 188              	.LCFI2:
+ 189              		.cfi_def_cfa_offset 12
+ 190              		.cfi_offset 4, -12
+ 191              		.cfi_offset 5, -8
+ 192              		.cfi_offset 6, -4
+ 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccmr1;
+ 193              		.loc 1 896 3 is_stmt 1 view .LVU51
+ 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccer;
+ 194              		.loc 1 897 3 view .LVU52
+ARM GAS  /tmp/ccI26Lsx.s 			page 63
+
+
+ 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpcr2;
+ 195              		.loc 1 898 3 view .LVU53
+ 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+ 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ 196              		.loc 1 901 3 view .LVU54
+ 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ 197              		.loc 1 902 3 view .LVU55
+ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ 198              		.loc 1 903 3 view .LVU56
+ 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ 199              		.loc 1 904 3 view .LVU57
+ 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the Channel 2: Reset the CC2E Bit */
+ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+ 200              		.loc 1 907 3 view .LVU58
+ 201 0002 036A     		ldr	r3, [r0, #32]
+ 202 0004 23F01003 		bic	r3, r3, #16
+ 203 0008 0362     		str	r3, [r0, #32]
+ 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCER register value */
+ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
+ 204              		.loc 1 910 3 view .LVU59
+ 205              		.loc 1 910 11 is_stmt 0 view .LVU60
+ 206 000a 036A     		ldr	r3, [r0, #32]
+ 207              	.LVL23:
+ 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CR2 register value */
+ 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+ 208              		.loc 1 913 3 is_stmt 1 view .LVU61
+ 209              		.loc 1 913 10 is_stmt 0 view .LVU62
+ 210 000c 4268     		ldr	r2, [r0, #4]
+ 211              	.LVL24:
+ 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCMR1 register value */
+ 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+ 212              		.loc 1 916 3 is_stmt 1 view .LVU63
+ 213              		.loc 1 916 12 is_stmt 0 view .LVU64
+ 214 000e 8569     		ldr	r5, [r0, #24]
+ 215              	.LVL25:
+ 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Reset Capture/Compare selection Bits */
+ 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+ 216              		.loc 1 919 3 is_stmt 1 view .LVU65
+ 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Output Compare Mode */
+ 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+ 217              		.loc 1 922 3 view .LVU66
+ 218 0010 184C     		ldr	r4, .L9
+ 219 0012 2C40     		ands	r4, r4, r5
+ 220 0014 0D68     		ldr	r5, [r1]
+ 221              	.LVL26:
+ 222              		.loc 1 922 3 is_stmt 0 view .LVU67
+ 223 0016 44EA0524 		orr	r4, r4, r5, lsl #8
+ 224              	.LVL27:
+ 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output Compare Polarity */
+ARM GAS  /tmp/ccI26Lsx.s 			page 64
+
+
+ 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+ 225              		.loc 1 925 3 is_stmt 1 view .LVU68
+ 226 001a 23F02003 		bic	r3, r3, #32
+ 227              	.LVL28:
+ 228              		.loc 1 925 3 is_stmt 0 view .LVU69
+ 229 001e 0D69     		ldr	r5, [r1, #16]
+ 230 0020 43EA0513 		orr	r3, r3, r5, lsl #4
+ 231              	.LVL29:
+ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output State */
+ 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+ 232              		.loc 1 928 3 is_stmt 1 view .LVU70
+ 233 0024 23F01003 		bic	r3, r3, #16
+ 234              	.LVL30:
+ 235              		.loc 1 928 3 is_stmt 0 view .LVU71
+ 236 0028 4D68     		ldr	r5, [r1, #4]
+ 237              		.loc 1 928 3 view .LVU72
+ 238 002a 43EA0513 		orr	r3, r3, r5, lsl #4
+ 239              	.LVL31:
+ 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 240              		.loc 1 930 3 is_stmt 1 view .LVU73
+ 241              		.loc 1 930 6 is_stmt 0 view .LVU74
+ 242 002e 124E     		ldr	r6, .L9+4
+ 243 0030 124D     		ldr	r5, .L9+8
+ 244 0032 A842     		cmp	r0, r5
+ 245 0034 18BF     		it	ne
+ 246 0036 B042     		cmpne	r0, r6
+ 247 0038 13D1     		bne	.L7
+ 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ 248              		.loc 1 932 5 is_stmt 1 view .LVU75
+ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ 249              		.loc 1 933 5 view .LVU76
+ 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ 250              		.loc 1 934 5 view .LVU77
+ 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ 251              		.loc 1 935 5 view .LVU78
+ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the complementary output Polarity */
+ 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
+ 252              		.loc 1 938 5 view .LVU79
+ 253 003a 23F08003 		bic	r3, r3, #128
+ 254              	.LVL32:
+ 255              		.loc 1 938 5 is_stmt 0 view .LVU80
+ 256 003e 4D69     		ldr	r5, [r1, #20]
+ 257 0040 43EA8513 		orr	r3, r3, r5, lsl #6
+ 258              	.LVL33:
+ 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the complementary output State */
+ 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
+ 259              		.loc 1 941 5 is_stmt 1 view .LVU81
+ 260 0044 23F04003 		bic	r3, r3, #64
+ 261              	.LVL34:
+ 262              		.loc 1 941 5 is_stmt 0 view .LVU82
+ 263 0048 8D68     		ldr	r5, [r1, #8]
+ 264              		.loc 1 941 5 view .LVU83
+ARM GAS  /tmp/ccI26Lsx.s 			page 65
+
+
+ 265 004a 43EA8513 		orr	r3, r3, r5, lsl #6
+ 266              	.LVL35:
+ 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the Output Idle state */
+ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
+ 267              		.loc 1 944 5 is_stmt 1 view .LVU84
+ 268 004e 22F48062 		bic	r2, r2, #1024
+ 269              	.LVL36:
+ 270              		.loc 1 944 5 is_stmt 0 view .LVU85
+ 271 0052 8D69     		ldr	r5, [r1, #24]
+ 272 0054 42EA8502 		orr	r2, r2, r5, lsl #2
+ 273              	.LVL37:
+ 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the complementary output Idle state */
+ 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
+ 274              		.loc 1 947 5 is_stmt 1 view .LVU86
+ 275 0058 22F40062 		bic	r2, r2, #2048
+ 276              	.LVL38:
+ 277              		.loc 1 947 5 is_stmt 0 view .LVU87
+ 278 005c CD69     		ldr	r5, [r1, #28]
+ 279              		.loc 1 947 5 view .LVU88
+ 280 005e 42EAC502 		orr	r2, r2, r5, lsl #3
+ 281              	.LVL39:
+ 282              	.L7:
+ 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CR2 */
+ 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+ 283              		.loc 1 951 3 is_stmt 1 view .LVU89
+ 284 0062 4260     		str	r2, [r0, #4]
+ 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCMR1 */
+ 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+ 285              		.loc 1 954 3 view .LVU90
+ 286 0064 8461     		str	r4, [r0, #24]
+ 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Capture Compare Register value */
+ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+ 287              		.loc 1 957 3 view .LVU91
+ 288 0066 CA68     		ldr	r2, [r1, #12]
+ 289              	.LVL40:
+ 290              	.LBB84:
+ 291              	.LBI84:
+2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 2 is supported by a timer instance.
+2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/ccI26Lsx.s 			page 66
+
+
+2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+ 292              		.loc 2 2461 22 view .LVU92
+ 293              	.LBB85:
+2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR2, CompareValue);
+ 294              		.loc 2 2463 3 view .LVU93
+ 295 0068 8263     		str	r2, [r0, #56]
+ 296              	.LVL41:
+ 297              		.loc 2 2463 3 is_stmt 0 view .LVU94
+ 298              	.LBE85:
+ 299              	.LBE84:
+ 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCER */
+ 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+ 300              		.loc 1 960 3 is_stmt 1 view .LVU95
+ 301 006a 0362     		str	r3, [r0, #32]
+ 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 302              		.loc 1 962 3 view .LVU96
+ 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 303              		.loc 1 963 1 is_stmt 0 view .LVU97
+ 304 006c 0020     		movs	r0, #0
+ 305              	.LVL42:
+ 306              		.loc 1 963 1 view .LVU98
+ 307 006e 70BC     		pop	{r4, r5, r6}
+ 308              	.LCFI3:
+ 309              		.cfi_restore 6
+ 310              		.cfi_restore 5
+ 311              		.cfi_restore 4
+ 312              		.cfi_def_cfa_offset 0
+ 313              	.LVL43:
+ 314              		.loc 1 963 1 view .LVU99
+ 315 0070 7047     		bx	lr
+ 316              	.L10:
+ 317 0072 00BF     		.align	2
+ 318              	.L9:
+ 319 0074 FF8CFFFE 		.word	-16806657
+ 320 0078 00000140 		.word	1073807360
+ 321 007c 00040140 		.word	1073808384
+ 322              		.cfi_endproc
+ 323              	.LFE392:
+ 325              		.section	.text.OC3Config,"ax",%progbits
+ 326              		.align	1
+ 327              		.syntax unified
+ 328              		.thumb
+ 329              		.thumb_func
+ 330              		.fpu fpv5-d16
+ 332              	OC3Config:
+ 333              	.LVL44:
+ 334              	.LFB393:
+ 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx output channel 3.
+ 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+ 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+ 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+ 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+ARM GAS  /tmp/ccI26Lsx.s 			page 67
+
+
+ 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+ 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+ 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 335              		.loc 1 974 1 is_stmt 1 view -0
+ 336              		.cfi_startproc
+ 337              		@ args = 0, pretend = 0, frame = 0
+ 338              		@ frame_needed = 0, uses_anonymous_args = 0
+ 339              		@ link register save eliminated.
+ 340              		.loc 1 974 1 is_stmt 0 view .LVU101
+ 341 0000 70B4     		push	{r4, r5, r6}
+ 342              	.LCFI4:
+ 343              		.cfi_def_cfa_offset 12
+ 344              		.cfi_offset 4, -12
+ 345              		.cfi_offset 5, -8
+ 346              		.cfi_offset 6, -4
+ 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccmr2;
+ 347              		.loc 1 975 3 is_stmt 1 view .LVU102
+ 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccer;
+ 348              		.loc 1 976 3 view .LVU103
+ 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpcr2;
+ 349              		.loc 1 977 3 view .LVU104
+ 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+ 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ 350              		.loc 1 980 3 view .LVU105
+ 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ 351              		.loc 1 981 3 view .LVU106
+ 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ 352              		.loc 1 982 3 view .LVU107
+ 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ 353              		.loc 1 983 3 view .LVU108
+ 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the Channel 3: Reset the CC3E Bit */
+ 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+ 354              		.loc 1 986 3 view .LVU109
+ 355 0002 036A     		ldr	r3, [r0, #32]
+ 356 0004 23F48073 		bic	r3, r3, #256
+ 357 0008 0362     		str	r3, [r0, #32]
+ 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCER register value */
+ 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
+ 358              		.loc 1 989 3 view .LVU110
+ 359              		.loc 1 989 11 is_stmt 0 view .LVU111
+ 360 000a 036A     		ldr	r3, [r0, #32]
+ 361              	.LVL45:
+ 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CR2 register value */
+ 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+ 362              		.loc 1 992 3 is_stmt 1 view .LVU112
+ 363              		.loc 1 992 10 is_stmt 0 view .LVU113
+ 364 000c 4268     		ldr	r2, [r0, #4]
+ 365              	.LVL46:
+ 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCMR2 register value */
+ 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+ 366              		.loc 1 995 3 is_stmt 1 view .LVU114
+ARM GAS  /tmp/ccI26Lsx.s 			page 68
+
+
+ 367              		.loc 1 995 12 is_stmt 0 view .LVU115
+ 368 000e C569     		ldr	r5, [r0, #28]
+ 369              	.LVL47:
+ 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Reset Capture/Compare selection Bits */
+ 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+ 370              		.loc 1 998 3 is_stmt 1 view .LVU116
+ 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Output Compare Mode */
+1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+ 371              		.loc 1 1001 3 view .LVU117
+ 372 0010 174C     		ldr	r4, .L14
+ 373 0012 2C40     		ands	r4, r4, r5
+ 374 0014 0D68     		ldr	r5, [r1]
+ 375              	.LVL48:
+ 376              		.loc 1 1001 3 is_stmt 0 view .LVU118
+ 377 0016 2C43     		orrs	r4, r4, r5
+ 378              	.LVL49:
+1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output Compare Polarity */
+1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+ 379              		.loc 1 1004 3 is_stmt 1 view .LVU119
+ 380 0018 23F40073 		bic	r3, r3, #512
+ 381              	.LVL50:
+ 382              		.loc 1 1004 3 is_stmt 0 view .LVU120
+ 383 001c 0D69     		ldr	r5, [r1, #16]
+ 384 001e 43EA0523 		orr	r3, r3, r5, lsl #8
+ 385              	.LVL51:
+1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output State */
+1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+ 386              		.loc 1 1007 3 is_stmt 1 view .LVU121
+ 387 0022 23F48073 		bic	r3, r3, #256
+ 388              	.LVL52:
+ 389              		.loc 1 1007 3 is_stmt 0 view .LVU122
+ 390 0026 4D68     		ldr	r5, [r1, #4]
+ 391              		.loc 1 1007 3 view .LVU123
+ 392 0028 43EA0523 		orr	r3, r3, r5, lsl #8
+ 393              	.LVL53:
+1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 394              		.loc 1 1009 3 is_stmt 1 view .LVU124
+ 395              		.loc 1 1009 6 is_stmt 0 view .LVU125
+ 396 002c 114E     		ldr	r6, .L14+4
+ 397 002e 124D     		ldr	r5, .L14+8
+ 398 0030 A842     		cmp	r0, r5
+ 399 0032 18BF     		it	ne
+ 400 0034 B042     		cmpne	r0, r6
+ 401 0036 13D1     		bne	.L12
+1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ 402              		.loc 1 1011 5 is_stmt 1 view .LVU126
+1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ 403              		.loc 1 1012 5 view .LVU127
+1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ 404              		.loc 1 1013 5 view .LVU128
+1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ARM GAS  /tmp/ccI26Lsx.s 			page 69
+
+
+ 405              		.loc 1 1014 5 view .LVU129
+1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the complementary output Polarity */
+1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
+ 406              		.loc 1 1017 5 view .LVU130
+ 407 0038 23F40063 		bic	r3, r3, #2048
+ 408              	.LVL54:
+ 409              		.loc 1 1017 5 is_stmt 0 view .LVU131
+ 410 003c 4D69     		ldr	r5, [r1, #20]
+ 411 003e 43EA8523 		orr	r3, r3, r5, lsl #10
+ 412              	.LVL55:
+1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the complementary output State */
+1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
+ 413              		.loc 1 1020 5 is_stmt 1 view .LVU132
+ 414 0042 23F48063 		bic	r3, r3, #1024
+ 415              	.LVL56:
+ 416              		.loc 1 1020 5 is_stmt 0 view .LVU133
+ 417 0046 8D68     		ldr	r5, [r1, #8]
+ 418              		.loc 1 1020 5 view .LVU134
+ 419 0048 43EA8523 		orr	r3, r3, r5, lsl #10
+ 420              	.LVL57:
+1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the Output Idle state */
+1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
+ 421              		.loc 1 1023 5 is_stmt 1 view .LVU135
+ 422 004c 22F48052 		bic	r2, r2, #4096
+ 423              	.LVL58:
+ 424              		.loc 1 1023 5 is_stmt 0 view .LVU136
+ 425 0050 8D69     		ldr	r5, [r1, #24]
+ 426 0052 42EA0512 		orr	r2, r2, r5, lsl #4
+ 427              	.LVL59:
+1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the complementary output Idle state */
+1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
+ 428              		.loc 1 1026 5 is_stmt 1 view .LVU137
+ 429 0056 22F40052 		bic	r2, r2, #8192
+ 430              	.LVL60:
+ 431              		.loc 1 1026 5 is_stmt 0 view .LVU138
+ 432 005a CD69     		ldr	r5, [r1, #28]
+ 433              		.loc 1 1026 5 view .LVU139
+ 434 005c 42EA4512 		orr	r2, r2, r5, lsl #5
+ 435              	.LVL61:
+ 436              	.L12:
+1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CR2 */
+1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+ 437              		.loc 1 1030 3 is_stmt 1 view .LVU140
+ 438 0060 4260     		str	r2, [r0, #4]
+1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCMR2 */
+1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+ 439              		.loc 1 1033 3 view .LVU141
+ 440 0062 C461     		str	r4, [r0, #28]
+1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Capture Compare Register value */
+ARM GAS  /tmp/ccI26Lsx.s 			page 70
+
+
+1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+ 441              		.loc 1 1036 3 view .LVU142
+ 442 0064 CA68     		ldr	r2, [r1, #12]
+ 443              	.LVL62:
+ 444              	.LBB86:
+ 445              	.LBI86:
+2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel is supported by a timer instance.
+2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+ 446              		.loc 2 2478 22 view .LVU143
+ 447              	.LBB87:
+2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR3, CompareValue);
+ 448              		.loc 2 2480 3 view .LVU144
+ 449 0066 C263     		str	r2, [r0, #60]
+ 450              	.LVL63:
+ 451              		.loc 2 2480 3 is_stmt 0 view .LVU145
+ 452              	.LBE87:
+ 453              	.LBE86:
+1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCER */
+1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+ 454              		.loc 1 1039 3 is_stmt 1 view .LVU146
+ 455 0068 0362     		str	r3, [r0, #32]
+1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 456              		.loc 1 1041 3 view .LVU147
+1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 457              		.loc 1 1042 1 is_stmt 0 view .LVU148
+ 458 006a 0020     		movs	r0, #0
+ 459              	.LVL64:
+ 460              		.loc 1 1042 1 view .LVU149
+ 461 006c 70BC     		pop	{r4, r5, r6}
+ 462              	.LCFI5:
+ 463              		.cfi_restore 6
+ 464              		.cfi_restore 5
+ 465              		.cfi_restore 4
+ 466              		.cfi_def_cfa_offset 0
+ 467              	.LVL65:
+ 468              		.loc 1 1042 1 view .LVU150
+ 469 006e 7047     		bx	lr
+ 470              	.L15:
+ 471              		.align	2
+ 472              	.L14:
+ 473 0070 8CFFFEFF 		.word	-65652
+ARM GAS  /tmp/ccI26Lsx.s 			page 71
+
+
+ 474 0074 00000140 		.word	1073807360
+ 475 0078 00040140 		.word	1073808384
+ 476              		.cfi_endproc
+ 477              	.LFE393:
+ 479              		.section	.text.OC4Config,"ax",%progbits
+ 480              		.align	1
+ 481              		.syntax unified
+ 482              		.thumb
+ 483              		.thumb_func
+ 484              		.fpu fpv5-d16
+ 486              	OC4Config:
+ 487              	.LVL66:
+ 488              	.LFB394:
+1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx output channel 4.
+1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 489              		.loc 1 1053 1 is_stmt 1 view -0
+ 490              		.cfi_startproc
+ 491              		@ args = 0, pretend = 0, frame = 0
+ 492              		@ frame_needed = 0, uses_anonymous_args = 0
+ 493              		@ link register save eliminated.
+ 494              		.loc 1 1053 1 is_stmt 0 view .LVU152
+ 495 0000 70B4     		push	{r4, r5, r6}
+ 496              	.LCFI6:
+ 497              		.cfi_def_cfa_offset 12
+ 498              		.cfi_offset 4, -12
+ 499              		.cfi_offset 5, -8
+ 500              		.cfi_offset 6, -4
+1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccmr2;
+ 501              		.loc 1 1054 3 is_stmt 1 view .LVU153
+1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccer;
+ 502              		.loc 1 1055 3 view .LVU154
+1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpcr2;
+ 503              		.loc 1 1056 3 view .LVU155
+1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ 504              		.loc 1 1059 3 view .LVU156
+1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ 505              		.loc 1 1060 3 view .LVU157
+1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ 506              		.loc 1 1061 3 view .LVU158
+1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ 507              		.loc 1 1062 3 view .LVU159
+1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the Channel 4: Reset the CC4E Bit */
+1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+ 508              		.loc 1 1065 3 view .LVU160
+ 509 0002 036A     		ldr	r3, [r0, #32]
+ARM GAS  /tmp/ccI26Lsx.s 			page 72
+
+
+ 510 0004 23F48053 		bic	r3, r3, #4096
+ 511 0008 0362     		str	r3, [r0, #32]
+1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCER register value */
+1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+ 512              		.loc 1 1068 3 view .LVU161
+ 513              		.loc 1 1068 11 is_stmt 0 view .LVU162
+ 514 000a 036A     		ldr	r3, [r0, #32]
+ 515              	.LVL67:
+1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CR2 register value */
+1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
+ 516              		.loc 1 1071 3 is_stmt 1 view .LVU163
+ 517              		.loc 1 1071 10 is_stmt 0 view .LVU164
+ 518 000c 4468     		ldr	r4, [r0, #4]
+ 519              	.LVL68:
+1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCMR2 register value */
+1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+ 520              		.loc 1 1074 3 is_stmt 1 view .LVU165
+ 521              		.loc 1 1074 12 is_stmt 0 view .LVU166
+ 522 000e C569     		ldr	r5, [r0, #28]
+ 523              	.LVL69:
+1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Reset Capture/Compare selection Bits */
+1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+ 524              		.loc 1 1077 3 is_stmt 1 view .LVU167
+1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Output Compare Mode */
+1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+ 525              		.loc 1 1080 3 view .LVU168
+ 526 0010 104A     		ldr	r2, .L19
+ 527 0012 2A40     		ands	r2, r2, r5
+ 528 0014 0D68     		ldr	r5, [r1]
+ 529              	.LVL70:
+ 530              		.loc 1 1080 3 is_stmt 0 view .LVU169
+ 531 0016 42EA0522 		orr	r2, r2, r5, lsl #8
+ 532              	.LVL71:
+1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output Compare Polarity */
+1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+ 533              		.loc 1 1083 3 is_stmt 1 view .LVU170
+ 534 001a 23F40053 		bic	r3, r3, #8192
+ 535              	.LVL72:
+ 536              		.loc 1 1083 3 is_stmt 0 view .LVU171
+ 537 001e 0D69     		ldr	r5, [r1, #16]
+ 538 0020 43EA0533 		orr	r3, r3, r5, lsl #12
+ 539              	.LVL73:
+1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output State */
+1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+ 540              		.loc 1 1086 3 is_stmt 1 view .LVU172
+ 541 0024 23F48053 		bic	r3, r3, #4096
+ 542              	.LVL74:
+ 543              		.loc 1 1086 3 is_stmt 0 view .LVU173
+ 544 0028 4D68     		ldr	r5, [r1, #4]
+ 545              		.loc 1 1086 3 view .LVU174
+ARM GAS  /tmp/ccI26Lsx.s 			page 73
+
+
+ 546 002a 43EA0533 		orr	r3, r3, r5, lsl #12
+ 547              	.LVL75:
+1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 548              		.loc 1 1088 3 is_stmt 1 view .LVU175
+ 549              		.loc 1 1088 6 is_stmt 0 view .LVU176
+ 550 002e 0A4E     		ldr	r6, .L19+4
+ 551 0030 0A4D     		ldr	r5, .L19+8
+ 552 0032 A842     		cmp	r0, r5
+ 553 0034 18BF     		it	ne
+ 554 0036 B042     		cmpne	r0, r6
+ 555 0038 04D1     		bne	.L17
+1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ 556              		.loc 1 1090 5 is_stmt 1 view .LVU177
+1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the Output Idle state */
+1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
+ 557              		.loc 1 1093 5 view .LVU178
+ 558 003a 24F48044 		bic	r4, r4, #16384
+ 559              	.LVL76:
+ 560              		.loc 1 1093 5 is_stmt 0 view .LVU179
+ 561 003e 8D69     		ldr	r5, [r1, #24]
+ 562 0040 44EA8514 		orr	r4, r4, r5, lsl #6
+ 563              	.LVL77:
+ 564              	.L17:
+1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CR2 */
+1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+ 565              		.loc 1 1097 3 is_stmt 1 view .LVU180
+ 566 0044 4460     		str	r4, [r0, #4]
+1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCMR2 */
+1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+ 567              		.loc 1 1100 3 view .LVU181
+ 568 0046 C261     		str	r2, [r0, #28]
+1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Capture Compare Register value */
+1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+ 569              		.loc 1 1103 3 view .LVU182
+ 570 0048 CA68     		ldr	r2, [r1, #12]
+ 571              	.LVL78:
+ 572              	.LBB88:
+ 573              	.LBI88:
+2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 4 is supported by a timer instance.
+2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+ARM GAS  /tmp/ccI26Lsx.s 			page 74
+
+
+2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+ 574              		.loc 2 2495 22 view .LVU183
+ 575              	.LBB89:
+2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR4, CompareValue);
+ 576              		.loc 2 2497 3 view .LVU184
+ 577 004a 0264     		str	r2, [r0, #64]
+ 578              	.LVL79:
+ 579              		.loc 2 2497 3 is_stmt 0 view .LVU185
+ 580              	.LBE89:
+ 581              	.LBE88:
+1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCER */
+1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+ 582              		.loc 1 1106 3 is_stmt 1 view .LVU186
+ 583 004c 0362     		str	r3, [r0, #32]
+1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 584              		.loc 1 1108 3 view .LVU187
+1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 585              		.loc 1 1109 1 is_stmt 0 view .LVU188
+ 586 004e 0020     		movs	r0, #0
+ 587              	.LVL80:
+ 588              		.loc 1 1109 1 view .LVU189
+ 589 0050 70BC     		pop	{r4, r5, r6}
+ 590              	.LCFI7:
+ 591              		.cfi_restore 6
+ 592              		.cfi_restore 5
+ 593              		.cfi_restore 4
+ 594              		.cfi_def_cfa_offset 0
+ 595              	.LVL81:
+ 596              		.loc 1 1109 1 view .LVU190
+ 597 0052 7047     		bx	lr
+ 598              	.L20:
+ 599              		.align	2
+ 600              	.L19:
+ 601 0054 FF8CFFFE 		.word	-16806657
+ 602 0058 00000140 		.word	1073807360
+ 603 005c 00040140 		.word	1073808384
+ 604              		.cfi_endproc
+ 605              	.LFE394:
+ 607              		.section	.text.OC5Config,"ax",%progbits
+ 608              		.align	1
+ 609              		.syntax unified
+ 610              		.thumb
+ 611              		.thumb_func
+ 612              		.fpu fpv5-d16
+ 614              	OC5Config:
+ 615              	.LVL82:
+ 616              	.LFB395:
+1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx output channel 5.
+1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
+ARM GAS  /tmp/ccI26Lsx.s 			page 75
+
+
+1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 617              		.loc 1 1120 1 is_stmt 1 view -0
+ 618              		.cfi_startproc
+ 619              		@ args = 0, pretend = 0, frame = 0
+ 620              		@ frame_needed = 0, uses_anonymous_args = 0
+ 621              		@ link register save eliminated.
+ 622              		.loc 1 1120 1 is_stmt 0 view .LVU192
+ 623 0000 30B4     		push	{r4, r5}
+ 624              	.LCFI8:
+ 625              		.cfi_def_cfa_offset 8
+ 626              		.cfi_offset 4, -8
+ 627              		.cfi_offset 5, -4
+1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccmr3;
+ 628              		.loc 1 1121 3 is_stmt 1 view .LVU193
+1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccer;
+ 629              		.loc 1 1122 3 view .LVU194
+1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
+ 630              		.loc 1 1125 3 view .LVU195
+1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ 631              		.loc 1 1126 3 view .LVU196
+1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ 632              		.loc 1 1127 3 view .LVU197
+1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ 633              		.loc 1 1128 3 view .LVU198
+1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ 634              		.loc 1 1129 3 view .LVU199
+1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ 635              		.loc 1 1130 3 view .LVU200
+1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the Channel 5: Reset the CC5E Bit */
+1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
+ 636              		.loc 1 1133 3 view .LVU201
+ 637 0002 036A     		ldr	r3, [r0, #32]
+ 638 0004 23F48033 		bic	r3, r3, #65536
+ 639 0008 0362     		str	r3, [r0, #32]
+1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCER register value */
+1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+ 640              		.loc 1 1136 3 view .LVU202
+ 641              		.loc 1 1136 11 is_stmt 0 view .LVU203
+ 642 000a 036A     		ldr	r3, [r0, #32]
+ 643              	.LVL83:
+1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCMR3 register value */
+1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+ 644              		.loc 1 1139 3 is_stmt 1 view .LVU204
+ 645              		.loc 1 1139 12 is_stmt 0 view .LVU205
+ 646 000c 446D     		ldr	r4, [r0, #84]
+ 647              	.LVL84:
+1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 76
+
+
+1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Output Compare Mode */
+1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
+ 648              		.loc 1 1142 3 is_stmt 1 view .LVU206
+ 649 000e 114A     		ldr	r2, .L24
+ 650 0010 2240     		ands	r2, r2, r4
+ 651 0012 0C68     		ldr	r4, [r1]
+ 652              	.LVL85:
+ 653              		.loc 1 1142 3 is_stmt 0 view .LVU207
+ 654 0014 2243     		orrs	r2, r2, r4
+ 655              	.LVL86:
+1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output Compare Polarity */
+1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
+ 656              		.loc 1 1145 3 is_stmt 1 view .LVU208
+ 657 0016 23F40033 		bic	r3, r3, #131072
+ 658              	.LVL87:
+ 659              		.loc 1 1145 3 is_stmt 0 view .LVU209
+ 660 001a 0C69     		ldr	r4, [r1, #16]
+ 661 001c 43EA0443 		orr	r3, r3, r4, lsl #16
+ 662              	.LVL88:
+1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output State */
+1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
+ 663              		.loc 1 1148 3 is_stmt 1 view .LVU210
+ 664 0020 23F48033 		bic	r3, r3, #65536
+ 665              	.LVL89:
+ 666              		.loc 1 1148 3 is_stmt 0 view .LVU211
+ 667 0024 4C68     		ldr	r4, [r1, #4]
+ 668              		.loc 1 1148 3 view .LVU212
+ 669 0026 43EA0443 		orr	r3, r3, r4, lsl #16
+ 670              	.LVL90:
+1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 671              		.loc 1 1150 3 is_stmt 1 view .LVU213
+ 672              		.loc 1 1150 6 is_stmt 0 view .LVU214
+ 673 002a 0B4D     		ldr	r5, .L24+4
+ 674 002c 0B4C     		ldr	r4, .L24+8
+ 675 002e A042     		cmp	r0, r4
+ 676 0030 18BF     		it	ne
+ 677 0032 A842     		cmpne	r0, r5
+ 678 0034 06D1     		bne	.L22
+1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ 679              		.loc 1 1152 5 is_stmt 1 view .LVU215
+1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ 680              		.loc 1 1153 5 view .LVU216
+1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the Output Idle state */
+1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
+ 681              		.loc 1 1156 5 view .LVU217
+ 682 0036 4468     		ldr	r4, [r0, #4]
+ 683 0038 24F48034 		bic	r4, r4, #65536
+ 684 003c 8D69     		ldr	r5, [r1, #24]
+ 685 003e 44EA0524 		orr	r4, r4, r5, lsl #8
+ 686 0042 4460     		str	r4, [r0, #4]
+ 687              	.L22:
+1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 77
+
+
+1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCMR3 */
+1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+ 688              		.loc 1 1161 3 view .LVU218
+ 689 0044 4265     		str	r2, [r0, #84]
+1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Capture Compare Register value */
+1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
+ 690              		.loc 1 1164 3 view .LVU219
+ 691 0046 CA68     		ldr	r2, [r1, #12]
+ 692              	.LVL91:
+ 693              	.LBB90:
+ 694              	.LBI90:
+2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 5 (TIMx_CCR5).
+2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 5 is supported by a timer instance.
+2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
+2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+ 695              		.loc 2 2509 22 view .LVU220
+ 696              	.LBB91:
+2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+ 697              		.loc 2 2511 3 view .LVU221
+ 698 0048 816D     		ldr	r1, [r0, #88]
+ 699              	.LVL92:
+ 700              		.loc 2 2511 3 is_stmt 0 view .LVU222
+ 701 004a 8265     		str	r2, [r0, #88]
+ 702              	.LVL93:
+ 703              		.loc 2 2511 3 view .LVU223
+ 704              	.LBE91:
+ 705              	.LBE90:
+1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCER */
+1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+ 706              		.loc 1 1167 3 is_stmt 1 view .LVU224
+ 707 004c 0362     		str	r3, [r0, #32]
+1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 708              		.loc 1 1169 3 view .LVU225
+1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 709              		.loc 1 1170 1 is_stmt 0 view .LVU226
+ 710 004e 0020     		movs	r0, #0
+ 711              	.LVL94:
+ 712              		.loc 1 1170 1 view .LVU227
+ 713 0050 30BC     		pop	{r4, r5}
+ 714              	.LCFI9:
+ 715              		.cfi_restore 5
+ 716              		.cfi_restore 4
+ 717              		.cfi_def_cfa_offset 0
+ARM GAS  /tmp/ccI26Lsx.s 			page 78
+
+
+ 718 0052 7047     		bx	lr
+ 719              	.L25:
+ 720              		.align	2
+ 721              	.L24:
+ 722 0054 8FFFFEFF 		.word	-65649
+ 723 0058 00000140 		.word	1073807360
+ 724 005c 00040140 		.word	1073808384
+ 725              		.cfi_endproc
+ 726              	.LFE395:
+ 728              		.section	.text.OC6Config,"ax",%progbits
+ 729              		.align	1
+ 730              		.syntax unified
+ 731              		.thumb
+ 732              		.thumb_func
+ 733              		.fpu fpv5-d16
+ 735              	OC6Config:
+ 736              	.LVL95:
+ 737              	.LFB396:
+1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx output channel 6.
+1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
+1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 738              		.loc 1 1181 1 is_stmt 1 view -0
+ 739              		.cfi_startproc
+ 740              		@ args = 0, pretend = 0, frame = 0
+ 741              		@ frame_needed = 0, uses_anonymous_args = 0
+ 742              		@ link register save eliminated.
+ 743              		.loc 1 1181 1 is_stmt 0 view .LVU229
+ 744 0000 30B4     		push	{r4, r5}
+ 745              	.LCFI10:
+ 746              		.cfi_def_cfa_offset 8
+ 747              		.cfi_offset 4, -8
+ 748              		.cfi_offset 5, -4
+1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccmr3;
+ 749              		.loc 1 1182 3 is_stmt 1 view .LVU230
+1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccer;
+ 750              		.loc 1 1183 3 view .LVU231
+1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
+ 751              		.loc 1 1186 3 view .LVU232
+1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ 752              		.loc 1 1187 3 view .LVU233
+1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ 753              		.loc 1 1188 3 view .LVU234
+1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ 754              		.loc 1 1189 3 view .LVU235
+1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ 755              		.loc 1 1190 3 view .LVU236
+1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ARM GAS  /tmp/ccI26Lsx.s 			page 79
+
+
+ 756              		.loc 1 1191 3 view .LVU237
+1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the Channel 5: Reset the CC6E Bit */
+1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
+ 757              		.loc 1 1194 3 view .LVU238
+ 758 0002 036A     		ldr	r3, [r0, #32]
+ 759 0004 23F48013 		bic	r3, r3, #1048576
+ 760 0008 0362     		str	r3, [r0, #32]
+1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCER register value */
+1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+ 761              		.loc 1 1197 3 view .LVU239
+ 762              		.loc 1 1197 11 is_stmt 0 view .LVU240
+ 763 000a 036A     		ldr	r3, [r0, #32]
+ 764              	.LVL96:
+1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Get the TIMx CCMR3 register value */
+1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+ 765              		.loc 1 1200 3 is_stmt 1 view .LVU241
+ 766              		.loc 1 1200 12 is_stmt 0 view .LVU242
+ 767 000c 446D     		ldr	r4, [r0, #84]
+ 768              	.LVL97:
+1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Output Compare Mode */
+1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
+ 769              		.loc 1 1203 3 is_stmt 1 view .LVU243
+ 770 000e 114A     		ldr	r2, .L29
+ 771 0010 2240     		ands	r2, r2, r4
+ 772 0012 0C68     		ldr	r4, [r1]
+ 773              	.LVL98:
+ 774              		.loc 1 1203 3 is_stmt 0 view .LVU244
+ 775 0014 42EA0422 		orr	r2, r2, r4, lsl #8
+ 776              	.LVL99:
+1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output Compare Polarity */
+1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
+ 777              		.loc 1 1206 3 is_stmt 1 view .LVU245
+ 778 0018 23F40013 		bic	r3, r3, #2097152
+ 779              	.LVL100:
+ 780              		.loc 1 1206 3 is_stmt 0 view .LVU246
+ 781 001c 0C69     		ldr	r4, [r1, #16]
+ 782 001e 43EA0453 		orr	r3, r3, r4, lsl #20
+ 783              	.LVL101:
+1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Output State */
+1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
+ 784              		.loc 1 1209 3 is_stmt 1 view .LVU247
+ 785 0022 23F48013 		bic	r3, r3, #1048576
+ 786              	.LVL102:
+ 787              		.loc 1 1209 3 is_stmt 0 view .LVU248
+ 788 0026 4C68     		ldr	r4, [r1, #4]
+ 789              		.loc 1 1209 3 view .LVU249
+ 790 0028 43EA0453 		orr	r3, r3, r4, lsl #20
+ 791              	.LVL103:
+1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 792              		.loc 1 1211 3 is_stmt 1 view .LVU250
+ARM GAS  /tmp/ccI26Lsx.s 			page 80
+
+
+ 793              		.loc 1 1211 6 is_stmt 0 view .LVU251
+ 794 002c 0A4D     		ldr	r5, .L29+4
+ 795 002e 0B4C     		ldr	r4, .L29+8
+ 796 0030 A042     		cmp	r0, r4
+ 797 0032 18BF     		it	ne
+ 798 0034 A842     		cmpne	r0, r5
+ 799 0036 06D1     		bne	.L27
+1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ 800              		.loc 1 1213 5 is_stmt 1 view .LVU252
+1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ 801              		.loc 1 1214 5 view .LVU253
+1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     /* Set the Output Idle state */
+1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
+ 802              		.loc 1 1217 5 view .LVU254
+ 803 0038 4468     		ldr	r4, [r0, #4]
+ 804 003a 24F48024 		bic	r4, r4, #262144
+ 805 003e 8D69     		ldr	r5, [r1, #24]
+ 806 0040 44EA8524 		orr	r4, r4, r5, lsl #10
+ 807 0044 4460     		str	r4, [r0, #4]
+ 808              	.L27:
+1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCMR3 */
+1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+ 809              		.loc 1 1221 3 view .LVU255
+ 810 0046 4265     		str	r2, [r0, #84]
+1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the Capture Compare Register value */
+1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
+ 811              		.loc 1 1224 3 view .LVU256
+ 812 0048 CA68     		ldr	r2, [r1, #12]
+ 813              	.LVL104:
+ 814              	.LBB92:
+ 815              	.LBI92:
+2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set compare value for output channel 6 (TIMx_CCR6).
+2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 6 is supported by a timer instance.
+2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
+2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  CompareValue between Min_Data=0 and Max_Data=65535
+2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+ 816              		.loc 2 2523 22 view .LVU257
+ 817              	.LBB93:
+2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->CCR6, CompareValue);
+ 818              		.loc 2 2525 3 view .LVU258
+ 819 004a C265     		str	r2, [r0, #92]
+ 820              	.LVL105:
+ 821              		.loc 2 2525 3 is_stmt 0 view .LVU259
+ 822              	.LBE93:
+ARM GAS  /tmp/ccI26Lsx.s 			page 81
+
+
+ 823              	.LBE92:
+1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Write to TIMx CCER */
+1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+ 824              		.loc 1 1227 3 is_stmt 1 view .LVU260
+ 825 004c 0362     		str	r3, [r0, #32]
+1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 826              		.loc 1 1229 3 view .LVU261
+1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 827              		.loc 1 1230 1 is_stmt 0 view .LVU262
+ 828 004e 0020     		movs	r0, #0
+ 829              	.LVL106:
+ 830              		.loc 1 1230 1 view .LVU263
+ 831 0050 30BC     		pop	{r4, r5}
+ 832              	.LCFI11:
+ 833              		.cfi_restore 5
+ 834              		.cfi_restore 4
+ 835              		.cfi_def_cfa_offset 0
+ 836 0052 7047     		bx	lr
+ 837              	.L30:
+ 838              		.align	2
+ 839              	.L29:
+ 840 0054 FF8FFFFE 		.word	-16805889
+ 841 0058 00000140 		.word	1073807360
+ 842 005c 00040140 		.word	1073808384
+ 843              		.cfi_endproc
+ 844              	.LFE396:
+ 846              		.section	.text.IC1Config,"ax",%progbits
+ 847              		.align	1
+ 848              		.syntax unified
+ 849              		.thumb
+ 850              		.thumb_func
+ 851              		.fpu fpv5-d16
+ 853              	IC1Config:
+ 854              	.LVL107:
+ 855              	.LFB397:
+1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx input channel 1.
+1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 856              		.loc 1 1241 1 is_stmt 1 view -0
+ 857              		.cfi_startproc
+ 858              		@ args = 0, pretend = 0, frame = 0
+ 859              		@ frame_needed = 0, uses_anonymous_args = 0
+ 860              		@ link register save eliminated.
+ 861              		.loc 1 1241 1 is_stmt 0 view .LVU265
+ 862 0000 10B4     		push	{r4}
+ 863              	.LCFI12:
+ 864              		.cfi_def_cfa_offset 4
+ARM GAS  /tmp/ccI26Lsx.s 			page 82
+
+
+ 865              		.cfi_offset 4, -4
+1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ 866              		.loc 1 1243 3 is_stmt 1 view .LVU266
+1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ 867              		.loc 1 1244 3 view .LVU267
+1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ 868              		.loc 1 1245 3 view .LVU268
+1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ 869              		.loc 1 1246 3 view .LVU269
+1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+ 870              		.loc 1 1247 3 view .LVU270
+1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the Channel 1: Reset the CC1E Bit */
+1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+ 871              		.loc 1 1250 3 view .LVU271
+ 872              		.loc 1 1250 14 is_stmt 0 view .LVU272
+ 873 0002 036A     		ldr	r3, [r0, #32]
+ 874 0004 23F00103 		bic	r3, r3, #1
+ 875 0008 0362     		str	r3, [r0, #32]
+1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Input and set the filter and the prescaler value */
+1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(TIMx->CCMR1,
+ 876              		.loc 1 1253 3 is_stmt 1 view .LVU273
+ 877 000a 8369     		ldr	r3, [r0, #24]
+ 878 000c 23F0FF03 		bic	r3, r3, #255
+ 879 0010 4A68     		ldr	r2, [r1, #4]
+ 880 0012 CC68     		ldr	r4, [r1, #12]
+ 881 0014 2243     		orrs	r2, r2, r4
+ 882 0016 8C68     		ldr	r4, [r1, #8]
+ 883 0018 2243     		orrs	r2, r2, r4
+ 884 001a 43EA1243 		orr	r3, r3, r2, lsr #16
+ 885 001e 8361     		str	r3, [r0, #24]
+1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr
+1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Polarity and set the CC1E Bit */
+1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(TIMx->CCER,
+ 886              		.loc 1 1258 3 view .LVU274
+ 887 0020 036A     		ldr	r3, [r0, #32]
+ 888 0022 23F00A03 		bic	r3, r3, #10
+ 889 0026 0A68     		ldr	r2, [r1]
+ 890 0028 1343     		orrs	r3, r3, r2
+ 891 002a 43F00103 		orr	r3, r3, #1
+ 892 002e 0362     		str	r3, [r0, #32]
+1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 893              		.loc 1 1262 3 view .LVU275
+1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 894              		.loc 1 1263 1 is_stmt 0 view .LVU276
+ 895 0030 0020     		movs	r0, #0
+ 896              	.LVL108:
+ 897              		.loc 1 1263 1 view .LVU277
+ 898 0032 5DF8044B 		ldr	r4, [sp], #4
+ 899              	.LCFI13:
+ARM GAS  /tmp/ccI26Lsx.s 			page 83
+
+
+ 900              		.cfi_restore 4
+ 901              		.cfi_def_cfa_offset 0
+ 902 0036 7047     		bx	lr
+ 903              		.cfi_endproc
+ 904              	.LFE397:
+ 906              		.section	.text.IC2Config,"ax",%progbits
+ 907              		.align	1
+ 908              		.syntax unified
+ 909              		.thumb
+ 910              		.thumb_func
+ 911              		.fpu fpv5-d16
+ 913              	IC2Config:
+ 914              	.LVL109:
+ 915              	.LFB398:
+1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx input channel 2.
+1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 916              		.loc 1 1274 1 is_stmt 1 view -0
+ 917              		.cfi_startproc
+ 918              		@ args = 0, pretend = 0, frame = 0
+ 919              		@ frame_needed = 0, uses_anonymous_args = 0
+ 920              		@ link register save eliminated.
+ 921              		.loc 1 1274 1 is_stmt 0 view .LVU279
+ 922 0000 10B4     		push	{r4}
+ 923              	.LCFI14:
+ 924              		.cfi_def_cfa_offset 4
+ 925              		.cfi_offset 4, -4
+1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ 926              		.loc 1 1276 3 is_stmt 1 view .LVU280
+1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ 927              		.loc 1 1277 3 view .LVU281
+1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ 928              		.loc 1 1278 3 view .LVU282
+1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ 929              		.loc 1 1279 3 view .LVU283
+1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+ 930              		.loc 1 1280 3 view .LVU284
+1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the Channel 2: Reset the CC2E Bit */
+1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+ 931              		.loc 1 1283 3 view .LVU285
+ 932              		.loc 1 1283 14 is_stmt 0 view .LVU286
+ 933 0002 036A     		ldr	r3, [r0, #32]
+ 934 0004 23F01003 		bic	r3, r3, #16
+ 935 0008 0362     		str	r3, [r0, #32]
+1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Input and set the filter and the prescaler value */
+1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(TIMx->CCMR1,
+ARM GAS  /tmp/ccI26Lsx.s 			page 84
+
+
+ 936              		.loc 1 1286 3 is_stmt 1 view .LVU287
+ 937 000a 8369     		ldr	r3, [r0, #24]
+ 938 000c 23F47F43 		bic	r3, r3, #65280
+ 939 0010 4A68     		ldr	r2, [r1, #4]
+ 940 0012 CC68     		ldr	r4, [r1, #12]
+ 941 0014 2243     		orrs	r2, r2, r4
+ 942 0016 8C68     		ldr	r4, [r1, #8]
+ 943 0018 2243     		orrs	r2, r2, r4
+ 944 001a 43EA1223 		orr	r3, r3, r2, lsr #8
+ 945 001e 8361     		str	r3, [r0, #24]
+1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr
+1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Polarity and set the CC2E Bit */
+1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(TIMx->CCER,
+ 946              		.loc 1 1291 3 view .LVU288
+ 947 0020 036A     		ldr	r3, [r0, #32]
+ 948 0022 23F0A003 		bic	r3, r3, #160
+ 949 0026 0A68     		ldr	r2, [r1]
+ 950 0028 43EA0213 		orr	r3, r3, r2, lsl #4
+ 951 002c 43F01003 		orr	r3, r3, #16
+ 952 0030 0362     		str	r3, [r0, #32]
+1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 953              		.loc 1 1295 3 view .LVU289
+1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 954              		.loc 1 1296 1 is_stmt 0 view .LVU290
+ 955 0032 0020     		movs	r0, #0
+ 956              	.LVL110:
+ 957              		.loc 1 1296 1 view .LVU291
+ 958 0034 5DF8044B 		ldr	r4, [sp], #4
+ 959              	.LCFI15:
+ 960              		.cfi_restore 4
+ 961              		.cfi_def_cfa_offset 0
+ 962 0038 7047     		bx	lr
+ 963              		.cfi_endproc
+ 964              	.LFE398:
+ 966              		.section	.text.IC3Config,"ax",%progbits
+ 967              		.align	1
+ 968              		.syntax unified
+ 969              		.thumb
+ 970              		.thumb_func
+ 971              		.fpu fpv5-d16
+ 973              	IC3Config:
+ 974              	.LVL111:
+ 975              	.LFB399:
+1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx input channel 3.
+1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+ARM GAS  /tmp/ccI26Lsx.s 			page 85
+
+
+1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 976              		.loc 1 1307 1 is_stmt 1 view -0
+ 977              		.cfi_startproc
+ 978              		@ args = 0, pretend = 0, frame = 0
+ 979              		@ frame_needed = 0, uses_anonymous_args = 0
+ 980              		@ link register save eliminated.
+ 981              		.loc 1 1307 1 is_stmt 0 view .LVU293
+ 982 0000 10B4     		push	{r4}
+ 983              	.LCFI16:
+ 984              		.cfi_def_cfa_offset 4
+ 985              		.cfi_offset 4, -4
+1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ 986              		.loc 1 1309 3 is_stmt 1 view .LVU294
+1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ 987              		.loc 1 1310 3 view .LVU295
+1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ 988              		.loc 1 1311 3 view .LVU296
+1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ 989              		.loc 1 1312 3 view .LVU297
+1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+ 990              		.loc 1 1313 3 view .LVU298
+1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the Channel 3: Reset the CC3E Bit */
+1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+ 991              		.loc 1 1316 3 view .LVU299
+ 992              		.loc 1 1316 14 is_stmt 0 view .LVU300
+ 993 0002 036A     		ldr	r3, [r0, #32]
+ 994 0004 23F48073 		bic	r3, r3, #256
+ 995 0008 0362     		str	r3, [r0, #32]
+1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Input and set the filter and the prescaler value */
+1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(TIMx->CCMR2,
+ 996              		.loc 1 1319 3 is_stmt 1 view .LVU301
+ 997 000a C369     		ldr	r3, [r0, #28]
+ 998 000c 23F0FF03 		bic	r3, r3, #255
+ 999 0010 4A68     		ldr	r2, [r1, #4]
+ 1000 0012 CC68     		ldr	r4, [r1, #12]
+ 1001 0014 2243     		orrs	r2, r2, r4
+ 1002 0016 8C68     		ldr	r4, [r1, #8]
+ 1003 0018 2243     		orrs	r2, r2, r4
+ 1004 001a 43EA1243 		orr	r3, r3, r2, lsr #16
+ 1005 001e C361     		str	r3, [r0, #28]
+1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr
+1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Polarity and set the CC3E Bit */
+1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(TIMx->CCER,
+ 1006              		.loc 1 1324 3 view .LVU302
+ 1007 0020 036A     		ldr	r3, [r0, #32]
+ 1008 0022 23F42063 		bic	r3, r3, #2560
+ 1009 0026 0A68     		ldr	r2, [r1]
+ 1010 0028 43EA0223 		orr	r3, r3, r2, lsl #8
+ 1011 002c 43F48073 		orr	r3, r3, #256
+ 1012 0030 0362     		str	r3, [r0, #32]
+1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+ARM GAS  /tmp/ccI26Lsx.s 			page 86
+
+
+1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 1013              		.loc 1 1328 3 view .LVU303
+1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 1014              		.loc 1 1329 1 is_stmt 0 view .LVU304
+ 1015 0032 0020     		movs	r0, #0
+ 1016              	.LVL112:
+ 1017              		.loc 1 1329 1 view .LVU305
+ 1018 0034 5DF8044B 		ldr	r4, [sp], #4
+ 1019              	.LCFI17:
+ 1020              		.cfi_restore 4
+ 1021              		.cfi_def_cfa_offset 0
+ 1022 0038 7047     		bx	lr
+ 1023              		.cfi_endproc
+ 1024              	.LFE399:
+ 1026              		.section	.text.IC4Config,"ax",%progbits
+ 1027              		.align	1
+ 1028              		.syntax unified
+ 1029              		.thumb
+ 1030              		.thumb_func
+ 1031              		.fpu fpv5-d16
+ 1033              	IC4Config:
+ 1034              	.LVL113:
+ 1035              	.LFB400:
+1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @brief  Configure the TIMx input channel 4.
+1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIMx Timer Instance
+1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   * @retval An ErrorStatus enumeration value:
+1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - SUCCESS: TIMx registers are de-initialized
+1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   *          - ERROR: not applicable
+1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   */
+1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** {
+ 1036              		.loc 1 1340 1 is_stmt 1 view -0
+ 1037              		.cfi_startproc
+ 1038              		@ args = 0, pretend = 0, frame = 0
+ 1039              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1040              		@ link register save eliminated.
+ 1041              		.loc 1 1340 1 is_stmt 0 view .LVU307
+ 1042 0000 10B4     		push	{r4}
+ 1043              	.LCFI18:
+ 1044              		.cfi_def_cfa_offset 4
+ 1045              		.cfi_offset 4, -4
+1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Check the parameters */
+1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ 1046              		.loc 1 1342 3 is_stmt 1 view .LVU308
+1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ 1047              		.loc 1 1343 3 view .LVU309
+1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ 1048              		.loc 1 1344 3 view .LVU310
+1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ 1049              		.loc 1 1345 3 view .LVU311
+1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+ 1050              		.loc 1 1346 3 view .LVU312
+ARM GAS  /tmp/ccI26Lsx.s 			page 87
+
+
+1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Disable the Channel 4: Reset the CC4E Bit */
+1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+ 1051              		.loc 1 1349 3 view .LVU313
+ 1052              		.loc 1 1349 14 is_stmt 0 view .LVU314
+ 1053 0002 036A     		ldr	r3, [r0, #32]
+ 1054 0004 23F48053 		bic	r3, r3, #4096
+ 1055 0008 0362     		str	r3, [r0, #32]
+1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Input and set the filter and the prescaler value */
+1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(TIMx->CCMR2,
+ 1056              		.loc 1 1352 3 is_stmt 1 view .LVU315
+ 1057 000a C369     		ldr	r3, [r0, #28]
+ 1058 000c 23F47F43 		bic	r3, r3, #65280
+ 1059 0010 4A68     		ldr	r2, [r1, #4]
+ 1060 0012 CC68     		ldr	r4, [r1, #12]
+ 1061 0014 2243     		orrs	r2, r2, r4
+ 1062 0016 8C68     		ldr	r4, [r1, #8]
+ 1063 0018 2243     		orrs	r2, r2, r4
+ 1064 001a 43EA1223 		orr	r3, r3, r2, lsr #8
+ 1065 001e C361     		str	r3, [r0, #28]
+1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr
+1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Select the Polarity and set the CC4E Bit */
+1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(TIMx->CCER,
+ 1066              		.loc 1 1357 3 view .LVU316
+ 1067 0020 036A     		ldr	r3, [r0, #32]
+ 1068 0022 23F42043 		bic	r3, r3, #40960
+ 1069 0026 0A68     		ldr	r2, [r1]
+ 1070 0028 43EA0233 		orr	r3, r3, r2, lsl #12
+ 1071 002c 43F48053 		orr	r3, r3, #4096
+ 1072 0030 0362     		str	r3, [r0, #32]
+1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
+1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   return SUCCESS;
+ 1073              		.loc 1 1361 3 view .LVU317
+1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 1074              		.loc 1 1362 1 is_stmt 0 view .LVU318
+ 1075 0032 0020     		movs	r0, #0
+ 1076              	.LVL114:
+ 1077              		.loc 1 1362 1 view .LVU319
+ 1078 0034 5DF8044B 		ldr	r4, [sp], #4
+ 1079              	.LCFI19:
+ 1080              		.cfi_restore 4
+ 1081              		.cfi_def_cfa_offset 0
+ 1082 0038 7047     		bx	lr
+ 1083              		.cfi_endproc
+ 1084              	.LFE400:
+ 1086              		.section	.text.LL_TIM_DeInit,"ax",%progbits
+ 1087              		.align	1
+ 1088              		.global	LL_TIM_DeInit
+ 1089              		.syntax unified
+ 1090              		.thumb
+ 1091              		.thumb_func
+ 1092              		.fpu fpv5-d16
+ARM GAS  /tmp/ccI26Lsx.s 			page 88
+
+
+ 1094              	LL_TIM_DeInit:
+ 1095              	.LVL115:
+ 1096              	.LFB378:
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   ErrorStatus result = SUCCESS;
+ 1097              		.loc 1 217 1 is_stmt 1 view -0
+ 1098              		.cfi_startproc
+ 1099              		@ args = 0, pretend = 0, frame = 0
+ 1100              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1101              		@ link register save eliminated.
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1102              		.loc 1 218 3 view .LVU321
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1103              		.loc 1 221 3 view .LVU322
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1104              		.loc 1 223 3 view .LVU323
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1105              		.loc 1 223 6 is_stmt 0 view .LVU324
+ 1106 0000 6B4B     		ldr	r3, .L69
+ 1107 0002 9842     		cmp	r0, r3
+ 1108 0004 2CD0     		beq	.L55
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1109              		.loc 1 228 8 is_stmt 1 view .LVU325
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1110              		.loc 1 228 11 is_stmt 0 view .LVU326
+ 1111 0006 B0F1804F 		cmp	r0, #1073741824
+ 1112 000a 35D0     		beq	.L56
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1113              		.loc 1 234 8 is_stmt 1 view .LVU327
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1114              		.loc 1 234 11 is_stmt 0 view .LVU328
+ 1115 000c 694B     		ldr	r3, .L69+4
+ 1116 000e 9842     		cmp	r0, r3
+ 1117 0010 3DD0     		beq	.L57
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1118              		.loc 1 241 8 is_stmt 1 view .LVU329
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1119              		.loc 1 241 11 is_stmt 0 view .LVU330
+ 1120 0012 694B     		ldr	r3, .L69+8
+ 1121 0014 9842     		cmp	r0, r3
+ 1122 0016 46D0     		beq	.L58
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1123              		.loc 1 248 8 is_stmt 1 view .LVU331
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1124              		.loc 1 248 11 is_stmt 0 view .LVU332
+ 1125 0018 684B     		ldr	r3, .L69+12
+ 1126 001a 9842     		cmp	r0, r3
+ 1127 001c 4FD0     		beq	.L59
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1128              		.loc 1 255 8 is_stmt 1 view .LVU333
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1129              		.loc 1 255 11 is_stmt 0 view .LVU334
+ 1130 001e 684B     		ldr	r3, .L69+16
+ 1131 0020 9842     		cmp	r0, r3
+ 1132 0022 58D0     		beq	.L60
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1133              		.loc 1 262 8 is_stmt 1 view .LVU335
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ARM GAS  /tmp/ccI26Lsx.s 			page 89
+
+
+ 1134              		.loc 1 262 11 is_stmt 0 view .LVU336
+ 1135 0024 674B     		ldr	r3, .L69+20
+ 1136 0026 9842     		cmp	r0, r3
+ 1137 0028 61D0     		beq	.L61
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1138              		.loc 1 269 8 is_stmt 1 view .LVU337
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1139              		.loc 1 269 11 is_stmt 0 view .LVU338
+ 1140 002a 674B     		ldr	r3, .L69+24
+ 1141 002c 9842     		cmp	r0, r3
+ 1142 002e 6AD0     		beq	.L62
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1143              		.loc 1 276 8 is_stmt 1 view .LVU339
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1144              		.loc 1 276 11 is_stmt 0 view .LVU340
+ 1145 0030 664B     		ldr	r3, .L69+28
+ 1146 0032 9842     		cmp	r0, r3
+ 1147 0034 73D0     		beq	.L63
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1148              		.loc 1 283 8 is_stmt 1 view .LVU341
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1149              		.loc 1 283 11 is_stmt 0 view .LVU342
+ 1150 0036 664B     		ldr	r3, .L69+32
+ 1151 0038 9842     		cmp	r0, r3
+ 1152 003a 7CD0     		beq	.L64
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1153              		.loc 1 290 8 is_stmt 1 view .LVU343
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1154              		.loc 1 290 11 is_stmt 0 view .LVU344
+ 1155 003c 654B     		ldr	r3, .L69+36
+ 1156 003e 9842     		cmp	r0, r3
+ 1157 0040 00F08580 		beq	.L65
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1158              		.loc 1 297 8 is_stmt 1 view .LVU345
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1159              		.loc 1 297 11 is_stmt 0 view .LVU346
+ 1160 0044 644B     		ldr	r3, .L69+40
+ 1161 0046 9842     		cmp	r0, r3
+ 1162 0048 00F08D80 		beq	.L66
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1163              		.loc 1 304 8 is_stmt 1 view .LVU347
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1164              		.loc 1 304 11 is_stmt 0 view .LVU348
+ 1165 004c 634B     		ldr	r3, .L69+44
+ 1166 004e 9842     		cmp	r0, r3
+ 1167 0050 00F09580 		beq	.L67
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1168              		.loc 1 311 8 is_stmt 1 view .LVU349
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1169              		.loc 1 311 11 is_stmt 0 view .LVU350
+ 1170 0054 624B     		ldr	r3, .L69+48
+ 1171 0056 9842     		cmp	r0, r3
+ 1172 0058 00F09D80 		beq	.L68
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1173              		.loc 1 319 12 view .LVU351
+ 1174 005c 0120     		movs	r0, #1
+ 1175              	.LVL116:
+ARM GAS  /tmp/ccI26Lsx.s 			page 90
+
+
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 1176              		.loc 1 322 3 is_stmt 1 view .LVU352
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1177              		.loc 1 323 1 is_stmt 0 view .LVU353
+ 1178 005e 7047     		bx	lr
+ 1179              	.LVL117:
+ 1180              	.L55:
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+ 1181              		.loc 1 225 5 is_stmt 1 view .LVU354
+ 1182              	.LBB94:
+ 1183              	.LBI94:
+ 1184              		.file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @file    stm32f7xx_ll_bus.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief   Header file of BUS LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @verbatim
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****                       ##### RCC Limitations #####
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ==============================================================================
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       A delay between an RCC peripheral clock enable and the effective peripheral 
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       enabling should be taken into account in order to manage the peripheral read/write 
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       from/to registers.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (+) This delay depends on the peripheral mapping.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****         (++) AHB & APB peripherals, 1 dummy read is necessary
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       Workarounds:
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @endverbatim
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @attention
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * Copyright (c) 2017 STMicroelectronics.
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * All rights reserved.
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * This software is licensed under terms that can be found in the LICENSE file in
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * the root directory of this software component.
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" {
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h"
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 91
+
+
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC)
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ)
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK)
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM         RCC_AHB1ENR_DTCMRAMEN
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D)
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH)
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI             RCC_AHB1LPENR_AXILPEN
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN
+ARM GAS  /tmp/ccI26Lsx.s 			page 92
+
+
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI)
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG)
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG           RCC_AHB2ENR_JPEGEN
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) 
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES)
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH)
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
+ARM GAS  /tmp/ccI26Lsx.s 			page 93
+
+
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX)
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4)
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4           RCC_APB1ENR_I2C4EN
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2)
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3)
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC)
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN)
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCEN
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1       RCC_APB2ENR_SDMMC1EN
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2)
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2       RCC_APB2ENR_SDMMC2EN
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN
+ARM GAS  /tmp/ccI26Lsx.s 			page 94
+
+
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6)
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC)
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI)
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0)
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS)
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO         RCC_APB2ENR_MDIOEN
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC)
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC      RCC_APB2ENR_OTGPHYCEN
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB1 peripherals clock.
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\n
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\n
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\n
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\n
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\n
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\n
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\n
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\n
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\n
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\n
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\n
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\n
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\n
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 95
+
+
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\n
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\n
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\n
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\n
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\n
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\n
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1ENR, Periphs);
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB1 peripheral clock is enabled or not
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 96
+
+
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\n
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\n
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\n
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_IsEnabledClock
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB1 peripherals clock.
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\n
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\n
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\n
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\n
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\n
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\n
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\n
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\n
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\n
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 97
+
+
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\n
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\n
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\n
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\n
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\n
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\n
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\n
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\n
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\n
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\n
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_DisableClock
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1ENR, Periphs);
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB1 peripherals reset.
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\n
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\n
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\n
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\n
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\n
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\n
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\n
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\n
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 98
+
+
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\n
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\n
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\n
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\n
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1RSTR, Periphs);
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB1 peripherals reset.
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\n
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\n
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\n
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\n
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\n
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ARM GAS  /tmp/ccI26Lsx.s 			page 99
+
+
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB1 peripheral clocks in low-power mode
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    AXILPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DTCMRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_EnableClockLowPower\n
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_EnableClockLowPower\n
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockLowPower
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ARM GAS  /tmp/ccI26Lsx.s 			page 100
+
+
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_AXI
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1LPENR, Periphs);
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB1 peripheral clocks in low-power mode
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    AXILPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 101
+
+
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DTCMRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_DisableClockLowPower\n
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_DisableClockLowPower\n
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockLowPower
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_AXI
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1LPENR, Periphs);
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ARM GAS  /tmp/ccI26Lsx.s 			page 102
+
+
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB2 peripherals clock.
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_EnableClock\n
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_EnableClock\n
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_EnableClock\n
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_EnableClock\n
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_EnableClock\n
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_EnableClock\n
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_EnableClock
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2ENR, Periphs);
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB2 peripheral clock is enabled or not
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_IsEnabledClock\n
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_IsEnabledClock\n
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_IsEnabledClock
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB2 peripherals clock.
+ARM GAS  /tmp/ccI26Lsx.s 			page 103
+
+
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_DisableClock\n
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_DisableClock\n
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_DisableClock\n
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_DisableClock\n
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_DisableClock\n
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_DisableClock\n
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_DisableClock
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2ENR, Periphs);
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB2 peripherals reset.
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ForceReset\n
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     JPEGRST      LL_AHB2_GRP1_ForceReset\n
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ForceReset\n
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ForceReset\n
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ForceReset\n
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ForceReset\n
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ForceReset
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2RSTR, Periphs);
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB2 peripherals reset.
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ReleaseReset\n
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     JPEGRST      LL_AHB2_GRP1_ReleaseReset\n
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ReleaseReset\n
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ReleaseReset\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 104
+
+
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ReleaseReset\n
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ReleaseReset\n
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ReleaseReset
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB2 peripheral clocks in low-power mode
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    JPEGLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_EnableClockLowPower
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2LPENR, Periphs);
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB2 peripheral clocks in low-power mode
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    JPEGLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 105
+
+
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_DisableClockLowPower
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2LPENR, Periphs);
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB3 peripherals clock.
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3ENR, Periphs);
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB3 peripheral clock is enabled or not
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ARM GAS  /tmp/ccI26Lsx.s 			page 106
+
+
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB3 peripherals clock.
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3ENR, Periphs);
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB3 peripherals reset.
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3RSTR, Periphs);
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB3 peripherals reset.
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 107
+
+
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB3 peripheral clocks in low-power mode
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockLowPower\n
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockLowPower
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3LPENR, Periphs);
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB3 peripheral clocks in low-power mode
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockLowPower\n
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockLowPower
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3LPENR, Periphs);
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB1 peripherals clock.
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 108
+
+
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\n
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_EnableClock\n
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_EnableClock\n
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_EnableClock\n
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_EnableClock\n
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_EnableClock\n
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_EnableClock\n
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_EnableClock\n
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_EnableClock\n
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\n
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\n
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_EnableClock\n
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_EnableClock\n
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_EnableClock
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+ARM GAS  /tmp/ccI26Lsx.s 			page 109
+
+
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1ENR, Periphs);
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if APB1 peripheral clock is enabled or not
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_IsEnabledClock\n
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_IsEnabledClock\n
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_IsEnabledClock\n
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_IsEnabledClock\n
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\n
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\n
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_IsEnabledClock\n
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_IsEnabledClock
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ARM GAS  /tmp/ccI26Lsx.s 			page 110
+
+
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable APB1 peripherals clock.
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\n
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\n
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_DisableClock\n
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_DisableClock\n
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_DisableClock\n
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_DisableClock\n
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_DisableClock\n
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_DisableClock\n
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_DisableClock\n
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_DisableClock\n
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\n
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\n
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_DisableClock\n
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_DisableClock\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 111
+
+
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_DisableClock
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1ENR, Periphs);
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force APB1 peripherals reset.
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\n
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\n
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ForceReset\n
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ForceReset\n
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\n
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\n
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ForceReset\n
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ForceReset\n
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ForceReset\n
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset\n
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\n
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\n
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ForceReset\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 112
+
+
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ForceReset\n
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\n
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART3RST      LL_APB1_GRP1_ForceReset\n
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART4RST       LL_APB1_GRP1_ForceReset\n
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART5RST       LL_APB1_GRP1_ForceReset\n
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\n
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\n
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\n
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C4RST        LL_APB1_GRP1_ForceReset\n
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ForceReset\n
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ForceReset\n
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ForceReset\n
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CECRST         LL_APB1_GRP1_ForceReset\n
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\n
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\n
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART7RST       LL_APB1_GRP1_ForceReset\n
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART8RST       LL_APB1_GRP1_ForceReset
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1RSTR, Periphs);
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 113
+
+
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release APB1 peripherals reset.
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ReleaseReset\n
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ReleaseReset\n
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ReleaseReset\n
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ReleaseReset\n
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ReleaseReset\n
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset\n
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\n
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ReleaseReset\n
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ReleaseReset\n
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\n
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART3RST      LL_APB1_GRP1_ReleaseReset\n
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART4RST       LL_APB1_GRP1_ReleaseReset\n
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART5RST       LL_APB1_GRP1_ReleaseReset\n
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C4RST        LL_APB1_GRP1_ReleaseReset\n
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ReleaseReset\n
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ReleaseReset\n
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ReleaseReset\n
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CECRST         LL_APB1_GRP1_ReleaseReset\n
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\n
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\n
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART7RST       LL_APB1_GRP1_ReleaseReset\n
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART8RST       LL_APB1_GRP1_ReleaseReset
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ARM GAS  /tmp/ccI26Lsx.s 			page 114
+
+
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1RSTR, Periphs);
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB1 peripheral clocks in low-power mode
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_EnableClockLowPower\n
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CECLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     DACLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     RTCLPEN         LL_APB1_GRP1_EnableClockLowPower
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+ARM GAS  /tmp/ccI26Lsx.s 			page 115
+
+
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1LPENR, Periphs);
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable APB1 peripheral clocks in low-power mode
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_DisableClockLowPower\n
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 116
+
+
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CECLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     DACLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     RTCLPEN         LL_APB1_GRP1_DisableClockLowPower
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1LPENR, Periphs);
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 117
+
+
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB2 peripherals clock.
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_EnableClock\n
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM8EN        LL_APB2_GRP1_EnableClock\n
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART1EN      LL_APB2_GRP1_EnableClock\n
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART6EN      LL_APB2_GRP1_EnableClock\n
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC1EN        LL_APB2_GRP1_EnableClock\n
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC2EN        LL_APB2_GRP1_EnableClock\n
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC3EN        LL_APB2_GRP1_EnableClock\n
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_EnableClock\n
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_EnableClock\n
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI1EN        LL_APB2_GRP1_EnableClock\n
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI4EN        LL_APB2_GRP1_EnableClock\n
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_EnableClock\n
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM9EN        LL_APB2_GRP1_EnableClock\n
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM10EN       LL_APB2_GRP1_EnableClock\n
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM11EN       LL_APB2_GRP1_EnableClock\n
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI5EN        LL_APB2_GRP1_EnableClock\n
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI6EN        LL_APB2_GRP1_EnableClock\n
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI1EN        LL_APB2_GRP1_EnableClock\n
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI2EN        LL_APB2_GRP1_EnableClock\n
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     LTDCEN        LL_APB2_GRP1_EnableClock\n
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DSIEN         LL_APB2_GRP1_EnableClock\n
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_EnableClock\n
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     MDIOEN        LL_APB2_GRP1_EnableClock\n
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_EnableClock
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ARM GAS  /tmp/ccI26Lsx.s 			page 118
+
+
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB2ENR, Periphs);
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if APB2 peripheral clock is enabled or not
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART6EN      LL_APB2_GRP1_IsEnabledClock\n
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC1EN        LL_APB2_GRP1_IsEnabledClock\n
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC2EN        LL_APB2_GRP1_IsEnabledClock\n
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC3EN        LL_APB2_GRP1_IsEnabledClock\n
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_IsEnabledClock\n
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_IsEnabledClock\n
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM9EN        LL_APB2_GRP1_IsEnabledClock\n
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM10EN       LL_APB2_GRP1_IsEnabledClock\n
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM11EN       LL_APB2_GRP1_IsEnabledClock\n
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI6EN        LL_APB2_GRP1_IsEnabledClock\n
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     LTDCEN        LL_APB2_GRP1_IsEnabledClock\n
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DSIEN         LL_APB2_GRP1_IsEnabledClock\n
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     MDIOEN        LL_APB2_GRP1_IsEnabledClock\n
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_IsEnabledClock
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+ARM GAS  /tmp/ccI26Lsx.s 			page 119
+
+
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable APB2 peripherals clock.
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_DisableClock\n
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM8EN        LL_APB2_GRP1_DisableClock\n
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART1EN      LL_APB2_GRP1_DisableClock\n
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART6EN      LL_APB2_GRP1_DisableClock\n
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC1EN        LL_APB2_GRP1_DisableClock\n
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC2EN        LL_APB2_GRP1_DisableClock\n
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC3EN        LL_APB2_GRP1_DisableClock\n
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_DisableClock\n
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_DisableClock\n
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI1EN        LL_APB2_GRP1_DisableClock\n
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI4EN        LL_APB2_GRP1_DisableClock\n
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_DisableClock\n
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM9EN        LL_APB2_GRP1_DisableClock\n
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM10EN       LL_APB2_GRP1_DisableClock\n
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM11EN       LL_APB2_GRP1_DisableClock\n
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI5EN        LL_APB2_GRP1_DisableClock\n
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI6EN        LL_APB2_GRP1_DisableClock\n
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI1EN        LL_APB2_GRP1_DisableClock\n
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI2EN        LL_APB2_GRP1_DisableClock\n
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     LTDCEN        LL_APB2_GRP1_DisableClock\n
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DSIEN         LL_APB2_GRP1_DisableClock\n
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_DisableClock\n
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     MDIOEN        LL_APB2_GRP1_DisableClock\n
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_DisableClock
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+ARM GAS  /tmp/ccI26Lsx.s 			page 120
+
+
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB2ENR, Periphs);
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force APB2 peripherals reset.
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ForceReset\n
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ForceReset\n
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART1RST      LL_APB2_GRP1_ForceReset\n
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART6RST      LL_APB2_GRP1_ForceReset\n
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     ADCRST         LL_APB2_GRP1_ForceReset\n
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC1RST      LL_APB2_GRP1_ForceReset\n
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC2RST      LL_APB2_GRP1_ForceReset\n
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ForceReset\n
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ForceReset\n
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ForceReset\n
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ForceReset\n
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ForceReset\n
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ForceReset\n
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ForceReset\n
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ForceReset\n
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ForceReset\n
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ForceReset\n
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ForceReset\n
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DSIRST         LL_APB2_GRP1_ForceReset\n
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ForceReset\n
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     MDIORST        LL_APB2_GRP1_ForceReset\n
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     OTGPHYCRST     LL_APB2_GRP1_ForceReset
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+ARM GAS  /tmp/ccI26Lsx.s 			page 121
+
+
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+ 1185              		.loc 3 1768 22 view .LVU355
+ 1186              	.LBB95:
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB2RSTR, Periphs);
+ 1187              		.loc 3 1770 3 view .LVU356
+ 1188 0060 03F59C33 		add	r3, r3, #79872
+ 1189 0064 5A6A     		ldr	r2, [r3, #36]
+ 1190 0066 42F00102 		orr	r2, r2, #1
+ 1191 006a 5A62     		str	r2, [r3, #36]
+ 1192              	.LVL118:
+ 1193              		.loc 3 1770 3 is_stmt 0 view .LVU357
+ 1194              	.LBE95:
+ 1195              	.LBE94:
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1196              		.loc 1 226 5 is_stmt 1 view .LVU358
+ 1197              	.LBB96:
+ 1198              	.LBI96:
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release APB2 peripherals reset.
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ReleaseReset\n
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ReleaseReset\n
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART1RST      LL_APB2_GRP1_ReleaseReset\n
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART6RST      LL_APB2_GRP1_ReleaseReset\n
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     ADCRST         LL_APB2_GRP1_ReleaseReset\n
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC1RST      LL_APB2_GRP1_ReleaseReset\n
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC2RST      LL_APB2_GRP1_ReleaseReset\n
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ReleaseReset\n
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ReleaseReset\n
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ReleaseReset\n
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ReleaseReset\n
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ReleaseReset\n
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ReleaseReset\n
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ReleaseReset\n
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ReleaseReset\n
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ReleaseReset\n
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ReleaseReset\n
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ReleaseReset\n
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DSIRST         LL_APB2_GRP1_ReleaseReset\n
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ReleaseReset\n
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     MDIORST        LL_APB2_GRP1_ReleaseReset\n
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     OTGPHYCRST     LL_APB2_GRP1_ReleaseReset
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ARM GAS  /tmp/ccI26Lsx.s 			page 122
+
+
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+ 1199              		.loc 3 1825 22 view .LVU359
+ 1200              	.LBB97:
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB2RSTR, Periphs);
+ 1201              		.loc 3 1827 3 view .LVU360
+ 1202 006c 5A6A     		ldr	r2, [r3, #36]
+ 1203 006e 22F00102 		bic	r2, r2, #1
+ 1204 0072 5A62     		str	r2, [r3, #36]
+ 1205              	.LBE97:
+ 1206              	.LBE96:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1207              		.loc 1 218 15 is_stmt 0 view .LVU361
+ 1208 0074 0020     		movs	r0, #0
+ 1209              	.LVL119:
+ 1210              	.LBB99:
+ 1211              	.LBB98:
+1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1212              		.loc 3 1828 1 view .LVU362
+ 1213 0076 7047     		bx	lr
+ 1214              	.LVL120:
+ 1215              	.L56:
+ 1216              		.loc 3 1828 1 view .LVU363
+ 1217              	.LBE98:
+ 1218              	.LBE99:
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+ 1219              		.loc 1 230 5 is_stmt 1 view .LVU364
+ 1220              	.LBB100:
+ 1221              	.LBI100:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ARM GAS  /tmp/ccI26Lsx.s 			page 123
+
+
+ 1222              		.loc 3 1295 22 view .LVU365
+ 1223              	.LBB101:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1224              		.loc 3 1297 3 view .LVU366
+ 1225 0078 5A4B     		ldr	r3, .L69+52
+ 1226 007a 1A6A     		ldr	r2, [r3, #32]
+ 1227 007c 42F00102 		orr	r2, r2, #1
+ 1228 0080 1A62     		str	r2, [r3, #32]
+ 1229              	.LVL121:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1230              		.loc 3 1297 3 is_stmt 0 view .LVU367
+ 1231              	.LBE101:
+ 1232              	.LBE100:
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1233              		.loc 1 231 5 is_stmt 1 view .LVU368
+ 1234              	.LBB102:
+ 1235              	.LBI102:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1236              		.loc 3 1367 22 view .LVU369
+ 1237              	.LBB103:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1238              		.loc 3 1369 3 view .LVU370
+ 1239 0082 1A6A     		ldr	r2, [r3, #32]
+ 1240 0084 22F00102 		bic	r2, r2, #1
+ 1241 0088 1A62     		str	r2, [r3, #32]
+ 1242              	.LBE103:
+ 1243              	.LBE102:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1244              		.loc 1 218 15 is_stmt 0 view .LVU371
+ 1245 008a 0020     		movs	r0, #0
+ 1246              	.LVL122:
+ 1247              	.LBB105:
+ 1248              	.LBB104:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1249              		.loc 3 1370 1 view .LVU372
+ 1250 008c 7047     		bx	lr
+ 1251              	.LVL123:
+ 1252              	.L57:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1253              		.loc 3 1370 1 view .LVU373
+ 1254              	.LBE104:
+ 1255              	.LBE105:
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+ 1256              		.loc 1 236 5 is_stmt 1 view .LVU374
+ 1257              	.LBB106:
+ 1258              	.LBI106:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1259              		.loc 3 1295 22 view .LVU375
+ 1260              	.LBB107:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1261              		.loc 3 1297 3 view .LVU376
+ 1262 008e 03F50D33 		add	r3, r3, #144384
+ 1263 0092 1A6A     		ldr	r2, [r3, #32]
+ 1264 0094 42F00202 		orr	r2, r2, #2
+ 1265 0098 1A62     		str	r2, [r3, #32]
+ 1266              	.LVL124:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ARM GAS  /tmp/ccI26Lsx.s 			page 124
+
+
+ 1267              		.loc 3 1297 3 is_stmt 0 view .LVU377
+ 1268              	.LBE107:
+ 1269              	.LBE106:
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1270              		.loc 1 237 5 is_stmt 1 view .LVU378
+ 1271              	.LBB108:
+ 1272              	.LBI108:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1273              		.loc 3 1367 22 view .LVU379
+ 1274              	.LBB109:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1275              		.loc 3 1369 3 view .LVU380
+ 1276 009a 1A6A     		ldr	r2, [r3, #32]
+ 1277 009c 22F00202 		bic	r2, r2, #2
+ 1278 00a0 1A62     		str	r2, [r3, #32]
+ 1279              	.LBE109:
+ 1280              	.LBE108:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1281              		.loc 1 218 15 is_stmt 0 view .LVU381
+ 1282 00a2 0020     		movs	r0, #0
+ 1283              	.LVL125:
+ 1284              	.LBB111:
+ 1285              	.LBB110:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1286              		.loc 3 1370 1 view .LVU382
+ 1287 00a4 7047     		bx	lr
+ 1288              	.LVL126:
+ 1289              	.L58:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1290              		.loc 3 1370 1 view .LVU383
+ 1291              	.LBE110:
+ 1292              	.LBE111:
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
+ 1293              		.loc 1 243 5 is_stmt 1 view .LVU384
+ 1294              	.LBB112:
+ 1295              	.LBI112:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1296              		.loc 3 1295 22 view .LVU385
+ 1297              	.LBB113:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1298              		.loc 3 1297 3 view .LVU386
+ 1299 00a6 03F50C33 		add	r3, r3, #143360
+ 1300 00aa 1A6A     		ldr	r2, [r3, #32]
+ 1301 00ac 42F00402 		orr	r2, r2, #4
+ 1302 00b0 1A62     		str	r2, [r3, #32]
+ 1303              	.LVL127:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1304              		.loc 3 1297 3 is_stmt 0 view .LVU387
+ 1305              	.LBE113:
+ 1306              	.LBE112:
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1307              		.loc 1 244 5 is_stmt 1 view .LVU388
+ 1308              	.LBB114:
+ 1309              	.LBI114:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1310              		.loc 3 1367 22 view .LVU389
+ 1311              	.LBB115:
+ARM GAS  /tmp/ccI26Lsx.s 			page 125
+
+
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1312              		.loc 3 1369 3 view .LVU390
+ 1313 00b2 1A6A     		ldr	r2, [r3, #32]
+ 1314 00b4 22F00402 		bic	r2, r2, #4
+ 1315 00b8 1A62     		str	r2, [r3, #32]
+ 1316              	.LBE115:
+ 1317              	.LBE114:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1318              		.loc 1 218 15 is_stmt 0 view .LVU391
+ 1319 00ba 0020     		movs	r0, #0
+ 1320              	.LVL128:
+ 1321              	.LBB117:
+ 1322              	.LBB116:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1323              		.loc 3 1370 1 view .LVU392
+ 1324 00bc 7047     		bx	lr
+ 1325              	.LVL129:
+ 1326              	.L59:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1327              		.loc 3 1370 1 view .LVU393
+ 1328              	.LBE116:
+ 1329              	.LBE117:
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
+ 1330              		.loc 1 250 5 is_stmt 1 view .LVU394
+ 1331              	.LBB118:
+ 1332              	.LBI118:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1333              		.loc 3 1295 22 view .LVU395
+ 1334              	.LBB119:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1335              		.loc 3 1297 3 view .LVU396
+ 1336 00be 03F50B33 		add	r3, r3, #142336
+ 1337 00c2 1A6A     		ldr	r2, [r3, #32]
+ 1338 00c4 42F00802 		orr	r2, r2, #8
+ 1339 00c8 1A62     		str	r2, [r3, #32]
+ 1340              	.LVL130:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1341              		.loc 3 1297 3 is_stmt 0 view .LVU397
+ 1342              	.LBE119:
+ 1343              	.LBE118:
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1344              		.loc 1 251 5 is_stmt 1 view .LVU398
+ 1345              	.LBB120:
+ 1346              	.LBI120:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1347              		.loc 3 1367 22 view .LVU399
+ 1348              	.LBB121:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1349              		.loc 3 1369 3 view .LVU400
+ 1350 00ca 1A6A     		ldr	r2, [r3, #32]
+ 1351 00cc 22F00802 		bic	r2, r2, #8
+ 1352 00d0 1A62     		str	r2, [r3, #32]
+ 1353              	.LBE121:
+ 1354              	.LBE120:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1355              		.loc 1 218 15 is_stmt 0 view .LVU401
+ 1356 00d2 0020     		movs	r0, #0
+ARM GAS  /tmp/ccI26Lsx.s 			page 126
+
+
+ 1357              	.LVL131:
+ 1358              	.LBB123:
+ 1359              	.LBB122:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1360              		.loc 3 1370 1 view .LVU402
+ 1361 00d4 7047     		bx	lr
+ 1362              	.LVL132:
+ 1363              	.L60:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1364              		.loc 3 1370 1 view .LVU403
+ 1365              	.LBE122:
+ 1366              	.LBE123:
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+ 1367              		.loc 1 257 5 is_stmt 1 view .LVU404
+ 1368              	.LBB124:
+ 1369              	.LBI124:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1370              		.loc 3 1295 22 view .LVU405
+ 1371              	.LBB125:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1372              		.loc 3 1297 3 view .LVU406
+ 1373 00d6 03F50A33 		add	r3, r3, #141312
+ 1374 00da 1A6A     		ldr	r2, [r3, #32]
+ 1375 00dc 42F01002 		orr	r2, r2, #16
+ 1376 00e0 1A62     		str	r2, [r3, #32]
+ 1377              	.LVL133:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1378              		.loc 3 1297 3 is_stmt 0 view .LVU407
+ 1379              	.LBE125:
+ 1380              	.LBE124:
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1381              		.loc 1 258 5 is_stmt 1 view .LVU408
+ 1382              	.LBB126:
+ 1383              	.LBI126:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1384              		.loc 3 1367 22 view .LVU409
+ 1385              	.LBB127:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1386              		.loc 3 1369 3 view .LVU410
+ 1387 00e2 1A6A     		ldr	r2, [r3, #32]
+ 1388 00e4 22F01002 		bic	r2, r2, #16
+ 1389 00e8 1A62     		str	r2, [r3, #32]
+ 1390              	.LBE127:
+ 1391              	.LBE126:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1392              		.loc 1 218 15 is_stmt 0 view .LVU411
+ 1393 00ea 0020     		movs	r0, #0
+ 1394              	.LVL134:
+ 1395              	.LBB129:
+ 1396              	.LBB128:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1397              		.loc 3 1370 1 view .LVU412
+ 1398 00ec 7047     		bx	lr
+ 1399              	.LVL135:
+ 1400              	.L61:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1401              		.loc 3 1370 1 view .LVU413
+ARM GAS  /tmp/ccI26Lsx.s 			page 127
+
+
+ 1402              	.LBE128:
+ 1403              	.LBE129:
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+ 1404              		.loc 1 264 5 is_stmt 1 view .LVU414
+ 1405              	.LBB130:
+ 1406              	.LBI130:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1407              		.loc 3 1295 22 view .LVU415
+ 1408              	.LBB131:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1409              		.loc 3 1297 3 view .LVU416
+ 1410 00ee 03F50933 		add	r3, r3, #140288
+ 1411 00f2 1A6A     		ldr	r2, [r3, #32]
+ 1412 00f4 42F02002 		orr	r2, r2, #32
+ 1413 00f8 1A62     		str	r2, [r3, #32]
+ 1414              	.LVL136:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1415              		.loc 3 1297 3 is_stmt 0 view .LVU417
+ 1416              	.LBE131:
+ 1417              	.LBE130:
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1418              		.loc 1 265 5 is_stmt 1 view .LVU418
+ 1419              	.LBB132:
+ 1420              	.LBI132:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1421              		.loc 3 1367 22 view .LVU419
+ 1422              	.LBB133:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1423              		.loc 3 1369 3 view .LVU420
+ 1424 00fa 1A6A     		ldr	r2, [r3, #32]
+ 1425 00fc 22F02002 		bic	r2, r2, #32
+ 1426 0100 1A62     		str	r2, [r3, #32]
+ 1427              	.LBE133:
+ 1428              	.LBE132:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1429              		.loc 1 218 15 is_stmt 0 view .LVU421
+ 1430 0102 0020     		movs	r0, #0
+ 1431              	.LVL137:
+ 1432              	.LBB135:
+ 1433              	.LBB134:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1434              		.loc 3 1370 1 view .LVU422
+ 1435 0104 7047     		bx	lr
+ 1436              	.LVL138:
+ 1437              	.L62:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1438              		.loc 3 1370 1 view .LVU423
+ 1439              	.LBE134:
+ 1440              	.LBE135:
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
+ 1441              		.loc 1 271 5 is_stmt 1 view .LVU424
+ 1442              	.LBB136:
+ 1443              	.LBI136:
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1444              		.loc 3 1768 22 view .LVU425
+ 1445              	.LBB137:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ARM GAS  /tmp/ccI26Lsx.s 			page 128
+
+
+ 1446              		.loc 3 1770 3 view .LVU426
+ 1447 0106 03F59A33 		add	r3, r3, #78848
+ 1448 010a 5A6A     		ldr	r2, [r3, #36]
+ 1449 010c 42F00202 		orr	r2, r2, #2
+ 1450 0110 5A62     		str	r2, [r3, #36]
+ 1451              	.LVL139:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1452              		.loc 3 1770 3 is_stmt 0 view .LVU427
+ 1453              	.LBE137:
+ 1454              	.LBE136:
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1455              		.loc 1 272 5 is_stmt 1 view .LVU428
+ 1456              	.LBB138:
+ 1457              	.LBI138:
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1458              		.loc 3 1825 22 view .LVU429
+ 1459              	.LBB139:
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1460              		.loc 3 1827 3 view .LVU430
+ 1461 0112 5A6A     		ldr	r2, [r3, #36]
+ 1462 0114 22F00202 		bic	r2, r2, #2
+ 1463 0118 5A62     		str	r2, [r3, #36]
+ 1464              	.LBE139:
+ 1465              	.LBE138:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1466              		.loc 1 218 15 is_stmt 0 view .LVU431
+ 1467 011a 0020     		movs	r0, #0
+ 1468              	.LVL140:
+ 1469              	.LBB141:
+ 1470              	.LBB140:
+ 1471              		.loc 3 1828 1 view .LVU432
+ 1472 011c 7047     		bx	lr
+ 1473              	.LVL141:
+ 1474              	.L63:
+ 1475              		.loc 3 1828 1 view .LVU433
+ 1476              	.LBE140:
+ 1477              	.LBE141:
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
+ 1478              		.loc 1 278 5 is_stmt 1 view .LVU434
+ 1479              	.LBB142:
+ 1480              	.LBI142:
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1481              		.loc 3 1768 22 view .LVU435
+ 1482              	.LBB143:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1483              		.loc 3 1770 3 view .LVU436
+ 1484 011e 03F57843 		add	r3, r3, #63488
+ 1485 0122 5A6A     		ldr	r2, [r3, #36]
+ 1486 0124 42F48032 		orr	r2, r2, #65536
+ 1487 0128 5A62     		str	r2, [r3, #36]
+ 1488              	.LVL142:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1489              		.loc 3 1770 3 is_stmt 0 view .LVU437
+ 1490              	.LBE143:
+ 1491              	.LBE142:
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1492              		.loc 1 279 5 is_stmt 1 view .LVU438
+ARM GAS  /tmp/ccI26Lsx.s 			page 129
+
+
+ 1493              	.LBB144:
+ 1494              	.LBI144:
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1495              		.loc 3 1825 22 view .LVU439
+ 1496              	.LBB145:
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1497              		.loc 3 1827 3 view .LVU440
+ 1498 012a 5A6A     		ldr	r2, [r3, #36]
+ 1499 012c 22F48032 		bic	r2, r2, #65536
+ 1500 0130 5A62     		str	r2, [r3, #36]
+ 1501              	.LBE145:
+ 1502              	.LBE144:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1503              		.loc 1 218 15 is_stmt 0 view .LVU441
+ 1504 0132 0020     		movs	r0, #0
+ 1505              	.LVL143:
+ 1506              	.LBB147:
+ 1507              	.LBB146:
+ 1508              		.loc 3 1828 1 view .LVU442
+ 1509 0134 7047     		bx	lr
+ 1510              	.LVL144:
+ 1511              	.L64:
+ 1512              		.loc 3 1828 1 view .LVU443
+ 1513              	.LBE146:
+ 1514              	.LBE147:
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
+ 1515              		.loc 1 285 5 is_stmt 1 view .LVU444
+ 1516              	.LBB148:
+ 1517              	.LBI148:
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1518              		.loc 3 1768 22 view .LVU445
+ 1519              	.LBB149:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1520              		.loc 3 1770 3 view .LVU446
+ 1521 0136 03F57443 		add	r3, r3, #62464
+ 1522 013a 5A6A     		ldr	r2, [r3, #36]
+ 1523 013c 42F40032 		orr	r2, r2, #131072
+ 1524 0140 5A62     		str	r2, [r3, #36]
+ 1525              	.LVL145:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1526              		.loc 3 1770 3 is_stmt 0 view .LVU447
+ 1527              	.LBE149:
+ 1528              	.LBE148:
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1529              		.loc 1 286 5 is_stmt 1 view .LVU448
+ 1530              	.LBB150:
+ 1531              	.LBI150:
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1532              		.loc 3 1825 22 view .LVU449
+ 1533              	.LBB151:
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1534              		.loc 3 1827 3 view .LVU450
+ 1535 0142 5A6A     		ldr	r2, [r3, #36]
+ 1536 0144 22F40032 		bic	r2, r2, #131072
+ 1537 0148 5A62     		str	r2, [r3, #36]
+ 1538              	.LBE151:
+ 1539              	.LBE150:
+ARM GAS  /tmp/ccI26Lsx.s 			page 130
+
+
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1540              		.loc 1 218 15 is_stmt 0 view .LVU451
+ 1541 014a 0020     		movs	r0, #0
+ 1542              	.LVL146:
+ 1543              	.LBB153:
+ 1544              	.LBB152:
+ 1545              		.loc 3 1828 1 view .LVU452
+ 1546 014c 7047     		bx	lr
+ 1547              	.LVL147:
+ 1548              	.L65:
+ 1549              		.loc 3 1828 1 view .LVU453
+ 1550              	.LBE152:
+ 1551              	.LBE153:
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
+ 1552              		.loc 1 292 5 is_stmt 1 view .LVU454
+ 1553              	.LBB154:
+ 1554              	.LBI154:
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1555              		.loc 3 1768 22 view .LVU455
+ 1556              	.LBB155:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1557              		.loc 3 1770 3 view .LVU456
+ 1558 014e 03F57043 		add	r3, r3, #61440
+ 1559 0152 5A6A     		ldr	r2, [r3, #36]
+ 1560 0154 42F48022 		orr	r2, r2, #262144
+ 1561 0158 5A62     		str	r2, [r3, #36]
+ 1562              	.LVL148:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1563              		.loc 3 1770 3 is_stmt 0 view .LVU457
+ 1564              	.LBE155:
+ 1565              	.LBE154:
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1566              		.loc 1 293 5 is_stmt 1 view .LVU458
+ 1567              	.LBB156:
+ 1568              	.LBI156:
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1569              		.loc 3 1825 22 view .LVU459
+ 1570              	.LBB157:
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1571              		.loc 3 1827 3 view .LVU460
+ 1572 015a 5A6A     		ldr	r2, [r3, #36]
+ 1573 015c 22F48022 		bic	r2, r2, #262144
+ 1574 0160 5A62     		str	r2, [r3, #36]
+ 1575              	.LBE157:
+ 1576              	.LBE156:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1577              		.loc 1 218 15 is_stmt 0 view .LVU461
+ 1578 0162 0020     		movs	r0, #0
+ 1579              	.LVL149:
+ 1580              	.LBB159:
+ 1581              	.LBB158:
+ 1582              		.loc 3 1828 1 view .LVU462
+ 1583 0164 7047     		bx	lr
+ 1584              	.LVL150:
+ 1585              	.L66:
+ 1586              		.loc 3 1828 1 view .LVU463
+ 1587              	.LBE158:
+ARM GAS  /tmp/ccI26Lsx.s 			page 131
+
+
+ 1588              	.LBE159:
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
+ 1589              		.loc 1 299 5 is_stmt 1 view .LVU464
+ 1590              	.LBB160:
+ 1591              	.LBI160:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1592              		.loc 3 1295 22 view .LVU465
+ 1593              	.LBB161:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1594              		.loc 3 1297 3 view .LVU466
+ 1595 0166 03F50833 		add	r3, r3, #139264
+ 1596 016a 1A6A     		ldr	r2, [r3, #32]
+ 1597 016c 42F04002 		orr	r2, r2, #64
+ 1598 0170 1A62     		str	r2, [r3, #32]
+ 1599              	.LVL151:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1600              		.loc 3 1297 3 is_stmt 0 view .LVU467
+ 1601              	.LBE161:
+ 1602              	.LBE160:
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1603              		.loc 1 300 5 is_stmt 1 view .LVU468
+ 1604              	.LBB162:
+ 1605              	.LBI162:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1606              		.loc 3 1367 22 view .LVU469
+ 1607              	.LBB163:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1608              		.loc 3 1369 3 view .LVU470
+ 1609 0172 1A6A     		ldr	r2, [r3, #32]
+ 1610 0174 22F04002 		bic	r2, r2, #64
+ 1611 0178 1A62     		str	r2, [r3, #32]
+ 1612              	.LBE163:
+ 1613              	.LBE162:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1614              		.loc 1 218 15 is_stmt 0 view .LVU471
+ 1615 017a 0020     		movs	r0, #0
+ 1616              	.LVL152:
+ 1617              	.LBB165:
+ 1618              	.LBB164:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1619              		.loc 3 1370 1 view .LVU472
+ 1620 017c 7047     		bx	lr
+ 1621              	.LVL153:
+ 1622              	.L67:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1623              		.loc 3 1370 1 view .LVU473
+ 1624              	.LBE164:
+ 1625              	.LBE165:
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
+ 1626              		.loc 1 306 5 is_stmt 1 view .LVU474
+ 1627              	.LBB166:
+ 1628              	.LBI166:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1629              		.loc 3 1295 22 view .LVU475
+ 1630              	.LBB167:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1631              		.loc 3 1297 3 view .LVU476
+ARM GAS  /tmp/ccI26Lsx.s 			page 132
+
+
+ 1632 017e 03F50733 		add	r3, r3, #138240
+ 1633 0182 1A6A     		ldr	r2, [r3, #32]
+ 1634 0184 42F08002 		orr	r2, r2, #128
+ 1635 0188 1A62     		str	r2, [r3, #32]
+ 1636              	.LVL154:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1637              		.loc 3 1297 3 is_stmt 0 view .LVU477
+ 1638              	.LBE167:
+ 1639              	.LBE166:
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1640              		.loc 1 307 5 is_stmt 1 view .LVU478
+ 1641              	.LBB168:
+ 1642              	.LBI168:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1643              		.loc 3 1367 22 view .LVU479
+ 1644              	.LBB169:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1645              		.loc 3 1369 3 view .LVU480
+ 1646 018a 1A6A     		ldr	r2, [r3, #32]
+ 1647 018c 22F08002 		bic	r2, r2, #128
+ 1648 0190 1A62     		str	r2, [r3, #32]
+ 1649              	.LBE169:
+ 1650              	.LBE168:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1651              		.loc 1 218 15 is_stmt 0 view .LVU481
+ 1652 0192 0020     		movs	r0, #0
+ 1653              	.LVL155:
+ 1654              	.LBB171:
+ 1655              	.LBB170:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1656              		.loc 3 1370 1 view .LVU482
+ 1657 0194 7047     		bx	lr
+ 1658              	.LVL156:
+ 1659              	.L68:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1660              		.loc 3 1370 1 view .LVU483
+ 1661              	.LBE170:
+ 1662              	.LBE171:
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
+ 1663              		.loc 1 313 5 is_stmt 1 view .LVU484
+ 1664              	.LBB172:
+ 1665              	.LBI172:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1666              		.loc 3 1295 22 view .LVU485
+ 1667              	.LBB173:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1668              		.loc 3 1297 3 view .LVU486
+ 1669 0196 03F50633 		add	r3, r3, #137216
+ 1670 019a 1A6A     		ldr	r2, [r3, #32]
+ 1671 019c 42F48072 		orr	r2, r2, #256
+ 1672 01a0 1A62     		str	r2, [r3, #32]
+ 1673              	.LVL157:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1674              		.loc 3 1297 3 is_stmt 0 view .LVU487
+ 1675              	.LBE173:
+ 1676              	.LBE172:
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ARM GAS  /tmp/ccI26Lsx.s 			page 133
+
+
+ 1677              		.loc 1 314 5 is_stmt 1 view .LVU488
+ 1678              	.LBB174:
+ 1679              	.LBI174:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 1680              		.loc 3 1367 22 view .LVU489
+ 1681              	.LBB175:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 1682              		.loc 3 1369 3 view .LVU490
+ 1683 01a2 1A6A     		ldr	r2, [r3, #32]
+ 1684 01a4 22F48072 		bic	r2, r2, #256
+ 1685 01a8 1A62     		str	r2, [r3, #32]
+ 1686              	.LBE175:
+ 1687              	.LBE174:
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1688              		.loc 1 218 15 is_stmt 0 view .LVU491
+ 1689 01aa 0020     		movs	r0, #0
+ 1690              	.LVL158:
+ 1691              	.LBB177:
+ 1692              	.LBB176:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 1693              		.loc 3 1370 1 view .LVU492
+ 1694 01ac 7047     		bx	lr
+ 1695              	.L70:
+ 1696 01ae 00BF     		.align	2
+ 1697              	.L69:
+ 1698 01b0 00000140 		.word	1073807360
+ 1699 01b4 00040040 		.word	1073742848
+ 1700 01b8 00080040 		.word	1073743872
+ 1701 01bc 000C0040 		.word	1073744896
+ 1702 01c0 00100040 		.word	1073745920
+ 1703 01c4 00140040 		.word	1073746944
+ 1704 01c8 00040140 		.word	1073808384
+ 1705 01cc 00400140 		.word	1073823744
+ 1706 01d0 00440140 		.word	1073824768
+ 1707 01d4 00480140 		.word	1073825792
+ 1708 01d8 00180040 		.word	1073747968
+ 1709 01dc 001C0040 		.word	1073748992
+ 1710 01e0 00200040 		.word	1073750016
+ 1711 01e4 00380240 		.word	1073887232
+ 1712              	.LBE176:
+ 1713              	.LBE177:
+ 1714              		.cfi_endproc
+ 1715              	.LFE378:
+ 1717              		.section	.text.LL_TIM_StructInit,"ax",%progbits
+ 1718              		.align	1
+ 1719              		.global	LL_TIM_StructInit
+ 1720              		.syntax unified
+ 1721              		.thumb
+ 1722              		.thumb_func
+ 1723              		.fpu fpv5-d16
+ 1725              	LL_TIM_StructInit:
+ 1726              	.LVL159:
+ 1727              	.LFB379:
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 1728              		.loc 1 332 1 is_stmt 1 view -0
+ 1729              		.cfi_startproc
+ 1730              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccI26Lsx.s 			page 134
+
+
+ 1731              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1732              		@ link register save eliminated.
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
+ 1733              		.loc 1 334 3 view .LVU494
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
+ 1734              		.loc 1 334 37 is_stmt 0 view .LVU495
+ 1735 0000 0023     		movs	r3, #0
+ 1736 0002 0380     		strh	r3, [r0]	@ movhi
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
+ 1737              		.loc 1 335 3 is_stmt 1 view .LVU496
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
+ 1738              		.loc 1 335 37 is_stmt 0 view .LVU497
+ 1739 0004 4360     		str	r3, [r0, #4]
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
+ 1740              		.loc 1 336 3 is_stmt 1 view .LVU498
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
+ 1741              		.loc 1 336 37 is_stmt 0 view .LVU499
+ 1742 0006 4FF0FF32 		mov	r2, #-1
+ 1743 000a 8260     		str	r2, [r0, #8]
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->RepetitionCounter = 0x00000000U;
+ 1744              		.loc 1 337 3 is_stmt 1 view .LVU500
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_InitStruct->RepetitionCounter = 0x00000000U;
+ 1745              		.loc 1 337 37 is_stmt 0 view .LVU501
+ 1746 000c C360     		str	r3, [r0, #12]
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 1747              		.loc 1 338 3 is_stmt 1 view .LVU502
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 1748              		.loc 1 338 37 is_stmt 0 view .LVU503
+ 1749 000e 0361     		str	r3, [r0, #16]
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1750              		.loc 1 339 1 view .LVU504
+ 1751 0010 7047     		bx	lr
+ 1752              		.cfi_endproc
+ 1753              	.LFE379:
+ 1755              		.section	.text.LL_TIM_Init,"ax",%progbits
+ 1756              		.align	1
+ 1757              		.global	LL_TIM_Init
+ 1758              		.syntax unified
+ 1759              		.thumb
+ 1760              		.thumb_func
+ 1761              		.fpu fpv5-d16
+ 1763              	LL_TIM_Init:
+ 1764              	.LVL160:
+ 1765              	.LFB380:
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpcr1;
+ 1766              		.loc 1 351 1 is_stmt 1 view -0
+ 1767              		.cfi_startproc
+ 1768              		@ args = 0, pretend = 0, frame = 0
+ 1769              		@ frame_needed = 0, uses_anonymous_args = 0
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpcr1;
+ 1770              		.loc 1 351 1 is_stmt 0 view .LVU506
+ 1771 0000 30B5     		push	{r4, r5, lr}
+ 1772              	.LCFI20:
+ 1773              		.cfi_def_cfa_offset 12
+ 1774              		.cfi_offset 4, -12
+ 1775              		.cfi_offset 5, -8
+ 1776              		.cfi_offset 14, -4
+ARM GAS  /tmp/ccI26Lsx.s 			page 135
+
+
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1777              		.loc 1 352 3 is_stmt 1 view .LVU507
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+ 1778              		.loc 1 355 3 view .LVU508
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+ 1779              		.loc 1 356 3 view .LVU509
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1780              		.loc 1 357 3 view .LVU510
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1781              		.loc 1 359 3 view .LVU511
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1782              		.loc 1 359 10 is_stmt 0 view .LVU512
+ 1783 0002 0368     		ldr	r3, [r0]
+ 1784              	.LVL161:
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1785              		.loc 1 361 3 is_stmt 1 view .LVU513
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1786              		.loc 1 361 7 is_stmt 0 view .LVU514
+ 1787 0004 3B4A     		ldr	r2, .L81
+ 1788 0006 9042     		cmp	r0, r2
+ 1789 0008 14BF     		ite	ne
+ 1790 000a 4FF0000E 		movne	lr, #0
+ 1791 000e 4FF0010E 		moveq	lr, #1
+ 1792 0012 B0F1804F 		cmp	r0, #1073741824
+ 1793 0016 14BF     		ite	ne
+ 1794 0018 7246     		movne	r2, lr
+ 1795 001a 4EF00102 		orreq	r2, lr, #1
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1796              		.loc 1 361 6 view .LVU515
+ 1797 001e AAB9     		cbnz	r2, .L73
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1798              		.loc 1 361 7 discriminator 1 view .LVU516
+ 1799 0020 354C     		ldr	r4, .L81+4
+ 1800 0022 A042     		cmp	r0, r4
+ 1801 0024 14BF     		ite	ne
+ 1802 0026 0024     		movne	r4, #0
+ 1803 0028 0124     		moveq	r4, #1
+ 1804 002a 344D     		ldr	r5, .L81+8
+ 1805 002c A842     		cmp	r0, r5
+ 1806 002e 0DD0     		beq	.L73
+ 1807 0030 64B9     		cbnz	r4, .L73
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1808              		.loc 1 361 7 discriminator 2 view .LVU517
+ 1809 0032 04F18044 		add	r4, r4, #1073741824
+ 1810 0036 04F58234 		add	r4, r4, #66560
+ 1811 003a A042     		cmp	r0, r4
+ 1812 003c 14BF     		ite	ne
+ 1813 003e 0024     		movne	r4, #0
+ 1814 0040 0124     		moveq	r4, #1
+ 1815 0042 05F50065 		add	r5, r5, #2048
+ 1816 0046 A842     		cmp	r0, r5
+ 1817 0048 00D0     		beq	.L73
+ 1818 004a 1CB1     		cbz	r4, .L74
+ 1819              	.L73:
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1820              		.loc 1 364 5 is_stmt 1 view .LVU518
+ 1821 004c 23F07003 		bic	r3, r3, #112
+ARM GAS  /tmp/ccI26Lsx.s 			page 136
+
+
+ 1822              	.LVL162:
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1823              		.loc 1 364 5 is_stmt 0 view .LVU519
+ 1824 0050 4C68     		ldr	r4, [r1, #4]
+ 1825 0052 2343     		orrs	r3, r3, r4
+ 1826              	.LVL163:
+ 1827              	.L74:
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1828              		.loc 1 367 3 is_stmt 1 view .LVU520
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1829              		.loc 1 367 6 is_stmt 0 view .LVU521
+ 1830 0054 002A     		cmp	r2, #0
+ 1831 0056 33D1     		bne	.L76
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1832              		.loc 1 367 7 discriminator 1 view .LVU522
+ 1833 0058 274A     		ldr	r2, .L81+4
+ 1834 005a 9042     		cmp	r0, r2
+ 1835 005c 14BF     		ite	ne
+ 1836 005e 0022     		movne	r2, #0
+ 1837 0060 0122     		moveq	r2, #1
+ 1838 0062 264C     		ldr	r4, .L81+8
+ 1839 0064 A042     		cmp	r0, r4
+ 1840 0066 2BD0     		beq	.L76
+ 1841 0068 52BB     		cbnz	r2, .L76
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1842              		.loc 1 367 7 discriminator 2 view .LVU523
+ 1843 006a 02F18042 		add	r2, r2, #1073741824
+ 1844 006e 02F58232 		add	r2, r2, #66560
+ 1845 0072 9042     		cmp	r0, r2
+ 1846 0074 14BF     		ite	ne
+ 1847 0076 0022     		movne	r2, #0
+ 1848 0078 0122     		moveq	r2, #1
+ 1849 007a 04F50064 		add	r4, r4, #2048
+ 1850 007e A042     		cmp	r0, r4
+ 1851 0080 1ED0     		beq	.L76
+ 1852 0082 EAB9     		cbnz	r2, .L76
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1853              		.loc 1 367 7 discriminator 3 view .LVU524
+ 1854 0084 1E4A     		ldr	r2, .L81+12
+ 1855 0086 9042     		cmp	r0, r2
+ 1856 0088 14BF     		ite	ne
+ 1857 008a 0022     		movne	r2, #0
+ 1858 008c 0122     		moveq	r2, #1
+ 1859 008e 04F59A34 		add	r4, r4, #78848
+ 1860 0092 A042     		cmp	r0, r4
+ 1861 0094 14D0     		beq	.L76
+ 1862 0096 9AB9     		cbnz	r2, .L76
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1863              		.loc 1 367 7 discriminator 4 view .LVU525
+ 1864 0098 1A4A     		ldr	r2, .L81+16
+ 1865 009a 9042     		cmp	r0, r2
+ 1866 009c 14BF     		ite	ne
+ 1867 009e 0022     		movne	r2, #0
+ 1868 00a0 0122     		moveq	r2, #1
+ 1869 00a2 04F50064 		add	r4, r4, #2048
+ 1870 00a6 A042     		cmp	r0, r4
+ 1871 00a8 0AD0     		beq	.L76
+ARM GAS  /tmp/ccI26Lsx.s 			page 137
+
+
+ 1872 00aa 4AB9     		cbnz	r2, .L76
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1873              		.loc 1 367 7 discriminator 5 view .LVU526
+ 1874 00ac 164A     		ldr	r2, .L81+20
+ 1875 00ae 9042     		cmp	r0, r2
+ 1876 00b0 14BF     		ite	ne
+ 1877 00b2 0022     		movne	r2, #0
+ 1878 00b4 0122     		moveq	r2, #1
+ 1879 00b6 A4F59634 		sub	r4, r4, #76800
+ 1880 00ba A042     		cmp	r0, r4
+ 1881 00bc 00D0     		beq	.L76
+ 1882 00be 22B1     		cbz	r2, .L77
+ 1883              	.L76:
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1884              		.loc 1 370 5 is_stmt 1 view .LVU527
+ 1885 00c0 23F4407C 		bic	ip, r3, #768
+ 1886 00c4 CB68     		ldr	r3, [r1, #12]
+ 1887              	.LVL164:
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1888              		.loc 1 370 5 is_stmt 0 view .LVU528
+ 1889 00c6 4CEA0303 		orr	r3, ip, r3
+ 1890              	.LVL165:
+ 1891              	.L77:
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1892              		.loc 1 374 3 is_stmt 1 view .LVU529
+ 1893 00ca 0360     		str	r3, [r0]
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1894              		.loc 1 377 3 view .LVU530
+ 1895 00cc 8A68     		ldr	r2, [r1, #8]
+ 1896              	.LVL166:
+ 1897              	.LBB178:
+ 1898              	.LBI178:
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 1899              		.loc 2 1635 22 view .LVU531
+ 1900              	.LBB179:
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 1901              		.loc 2 1637 3 view .LVU532
+ 1902 00ce C262     		str	r2, [r0, #44]
+ 1903              	.LVL167:
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 1904              		.loc 2 1637 3 is_stmt 0 view .LVU533
+ 1905              	.LBE179:
+ 1906              	.LBE178:
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1907              		.loc 1 380 3 is_stmt 1 view .LVU534
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1908              		.loc 1 380 43 is_stmt 0 view .LVU535
+ 1909 00d0 0A88     		ldrh	r2, [r1]
+ 1910              	.LVL168:
+ 1911              	.LBB180:
+ 1912              	.LBI180:
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 1913              		.loc 2 1608 22 is_stmt 1 view .LVU536
+ 1914              	.LBB181:
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 1915              		.loc 2 1610 3 view .LVU537
+ 1916 00d2 8262     		str	r2, [r0, #40]
+ARM GAS  /tmp/ccI26Lsx.s 			page 138
+
+
+ 1917              	.LVL169:
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 1918              		.loc 2 1610 3 is_stmt 0 view .LVU538
+ 1919              	.LBE181:
+ 1920              	.LBE180:
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1921              		.loc 1 382 3 is_stmt 1 view .LVU539
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1922              		.loc 1 382 7 is_stmt 0 view .LVU540
+ 1923 00d4 0D4A     		ldr	r2, .L81+24
+ 1924 00d6 9042     		cmp	r0, r2
+ 1925 00d8 14BF     		ite	ne
+ 1926 00da 7346     		movne	r3, lr
+ 1927 00dc 4EF00103 		orreq	r3, lr, #1
+ 1928              	.LVL170:
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 1929              		.loc 1 382 6 view .LVU541
+ 1930 00e0 0BB1     		cbz	r3, .L79
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 1931              		.loc 1 385 5 is_stmt 1 view .LVU542
+ 1932 00e2 0B69     		ldr	r3, [r1, #16]
+ 1933              	.LVL171:
+ 1934              	.LBB182:
+ 1935              	.LBI182:
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 1936              		.loc 2 1663 22 view .LVU543
+ 1937              	.LBB183:
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 1938              		.loc 2 1665 3 view .LVU544
+ 1939 00e4 0363     		str	r3, [r0, #48]
+ 1940              	.LVL172:
+ 1941              	.L79:
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 1942              		.loc 2 1665 3 is_stmt 0 view .LVU545
+ 1943              	.LBE183:
+ 1944              	.LBE182:
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1945              		.loc 1 390 3 is_stmt 1 view .LVU546
+ 1946              	.LBB184:
+ 1947              	.LBI184:
+2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 1 is supported by a timer instance.
+2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
+2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR1));
+2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ARM GAS  /tmp/ccI26Lsx.s 			page 139
+
+
+2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 2 is supported by a timer instance.
+2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
+2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR2));
+2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 3 is supported by a timer instance.
+2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
+2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR3));
+2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF
+2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 4 is supported by a timer instance.
+2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
+2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR4));
+2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
+2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 5 is supported by a timer instance.
+2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
+2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/ccI26Lsx.s 			page 140
+
+
+2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
+2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
+2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       output channel 6 is supported by a timer instance.
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
+2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
+2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR6));
+2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Select on which reference signal the OC5REF is combined to.
+2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports the combined 3-phase PWM mode.
+2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
+2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
+2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
+2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  GroupCH5 This parameter can be a combination of the following values:
+2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_NONE
+2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
+2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
+2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
+2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
+2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure input channel.
+2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC1F          LL_TIM_IC_Config\n
+2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_IC_Config\n
+2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2F          LL_TIM_IC_Config\n
+2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_IC_Config\n
+2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3F          LL_TIM_IC_Config\n
+2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_IC_Config\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 141
+
+
+2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4F          LL_TIM_IC_Config\n
+2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1P          LL_TIM_IC_Config\n
+2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_IC_Config\n
+2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_IC_Config\n
+2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_IC_Config\n
+2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_IC_Config\n
+2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_IC_Config\n
+2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_IC_Config\n
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4NP         LL_TIM_IC_Config
+2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Configuration This parameter must be a combination of all the following values:
+2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_
+2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_I
+2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne
+2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))       
+2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              << SHIFT_TAB_ICxx[iChannel]);
+2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the active input.
+2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICActiveInput This parameter can be one of the following values:
+2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv
+2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT
+ARM GAS  /tmp/ccI26Lsx.s 			page 142
+
+
+2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current active input.
+2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
+2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann
+2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the prescaler of input channel.
+2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICPrescaler This parameter can be one of the following values:
+2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1
+2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV2
+2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV4
+2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV8
+2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal
+2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT
+2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current prescaler value acting on an  input channel.
+2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+ARM GAS  /tmp/ccI26Lsx.s 			page 143
+
+
+2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV1
+2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV2
+2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV4
+2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ICPSC_DIV8
+2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
+2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha
+2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the input filter duration.
+2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICFilter This parameter can be one of the following values:
+2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
+2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_
+2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ARM GAS  /tmp/ccI26Lsx.s 			page 144
+
+
+2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the input filter duration.
+2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
+2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
+2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann
+2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the input channel polarity.
+2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ICPolarity This parameter can be one of the following values:
+2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_RISING
+2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+ARM GAS  /tmp/ccI26Lsx.s 			page 145
+
+
+2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity
+2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****              ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get the current input channel polarity.
+2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Channel This parameter can be one of the following values:
+2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH1
+2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH2
+2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH3
+2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CHANNEL_CH4
+2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval Returned value can be one of the following values:
+2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_RISING
+2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****           SHIFT_TAB_CCxP[iChannel]);
+2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides an XOR input.
+2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides an XOR input.
+2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+ARM GAS  /tmp/ccI26Lsx.s 			page 146
+
+
+2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * a timer instance provides an XOR input.
+2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
+2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 1.
+2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 1 is supported by a timer instance.
+2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
+2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR1));
+2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 2.
+2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 2 is supported by a timer instance.
+2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
+2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR2));
+2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 3.
+2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+ARM GAS  /tmp/ccI26Lsx.s 			page 147
+
+
+2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 3 is supported by a timer instance.
+3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
+3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR3));
+3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Get captured value for input channel 4.
+3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF
+3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports a 32 bits counter.
+3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       input channel 4 is supported by a timer instance.
+3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
+3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return (uint32_t)(READ_REG(TIMx->CCR4));
+3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable external clock mode 2.
+3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET
+3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable external clock mode 2.
+3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+ARM GAS  /tmp/ccI26Lsx.s 			page 148
+
+
+3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether external clock mode 2 is enabled.
+3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
+3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the clock source of the counter clock.
+3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note when selected clock source is external clock mode 1, the timer input
+3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       function. This timer input must be configured by calling
+3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       the @ref LL_TIM_IC_Config() function.
+3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode1.
+3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports external clock mode2.
+3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         SMCR         ECE           LL_TIM_SetClockSource
+3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ClockSource This parameter can be one of the following values:
+3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the encoder interface mode.
+3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance supports the encoder mode.
+3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  EncoderMode This parameter can be one of the following values:
+3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ARM GAS  /tmp/ccI26Lsx.s 			page 149
+
+
+3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the trigger output (TRGO) used for timer synchronization .
+3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance can operate as a master timer.
+3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TimerSynchronization This parameter can be one of the following values:
+3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_RESET
+3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_ENABLE
+3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_UPDATE
+3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_CC1IF
+3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC1REF
+3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC2REF
+3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC3REF
+3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO_OC4REF
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
+3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       whether or not a timer instance can be used for ADC synchronization.
+3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
+3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer Instance
+3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ADCSynchronization This parameter can be one of the following values:
+3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_RESET
+3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_ENABLE
+3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_UPDATE
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_CC1F
+3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC1
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC2
+3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC3
+3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4
+3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC5
+3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC6
+3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ARM GAS  /tmp/ccI26Lsx.s 			page 150
+
+
+3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the synchronization mode of a slave timer.
+3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  SlaveMode This parameter can be one of the following values:
+3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_RESET
+3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_GATED
+3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the selects the trigger input to be used to synchronize the counter.
+3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TriggerInput This parameter can be one of the following values:
+3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR0
+3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR1
+3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR2
+3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ITR3
+3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_TI1F_ED
+3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_TI1FP1
+3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_TI2FP2
+3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_TS_ETRF
+3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the Master/Slave mode.
+3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 151
+
+
+3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the Master/Slave mode.
+3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance can operate as a slave timer.
+3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief Indicates whether the Master/Slave mode is enabled.
+3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * a timer instance can operate as a slave timer.
+3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
+3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure the external trigger (ETR) input.
+3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides an external trigger input.
+3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         SMCR         ETPS          LL_TIM_ConfigETR\n
+3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         SMCR         ETF           LL_TIM_ConfigETR
+3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ETRPolarity This parameter can be one of the following values:
+3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ETRPrescaler This parameter can be one of the following values:
+3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  ETRFilter This parameter can be one of the following values:
+3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+ARM GAS  /tmp/ccI26Lsx.s 			page 152
+
+
+3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale
+3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       uint32_t ETRFilter)
+3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | 
+3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Break_Function Break function configuration
+3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the break function.
+3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the break function.
+3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure the break input.
+3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         BDTR         BKF           LL_TIM_ConfigBRK
+3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakPolarity This parameter can be one of the following values:
+3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakFilter This parameter can be one of the following values:
+3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+ARM GAS  /tmp/ccI26Lsx.s 			page 153
+
+
+3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
+3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                       uint32_t BreakFilter)
+3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
+3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the break 2 function.
+3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a second break input.
+3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
+3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the break  2 function.
+3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a second break input.
+3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
+3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configure the break 2 input.
+3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a second break input.
+3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         BDTR         BK2F          LL_TIM_ConfigBRK2
+3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Break2Polarity This parameter can be one of the following values:
+3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+ARM GAS  /tmp/ccI26Lsx.s 			page 154
+
+
+3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Break2Filter This parameter can be one of the following values:
+3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2F
+3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
+3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         BDTR         OSSR          LL_TIM_SetOffStates
+3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  OffStateIdle This parameter can be one of the following values:
+3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSI_DISABLE
+3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSI_ENABLE
+3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  OffStateRun This parameter can be one of the following values:
+3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSR_DISABLE
+3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_OSSR_ENABLE
+3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat
+3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input
+3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 155
+
+
+3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable automatic output (MOE can be set only by software).
+3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether automatic output is enabled.
+3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
+3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       software and is reset in case of break or break2 event
+3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       software and is reset in case of break or break2 event.
+3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ARM GAS  /tmp/ccI26Lsx.s 			page 156
+
+
+3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether outputs are enabled.
+3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a timer instance provides a break input.
+3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
+3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT)
+3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable the signals connected to the designated timer break input.
+3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance allows for break input selection.
+3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll AF1          BKINE          LL_TIM_EnableBreakInputSource\n
+3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF1          BKDFBKE        LL_TIM_EnableBreakInputSource\n
+3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2INE         LL_TIM_EnableBreakInputSource\n
+3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2DFBKE       LL_TIM_EnableBreakInputSource
+3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakInput This parameter can be one of the following values:
+3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Source This parameter can be one of the following values:
+3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t
+3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(*pReg, Source);
+3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable the signals connected to the designated timer break input.
+3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance allows for break input selection.
+3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll AF1          BKINE          LL_TIM_DisableBreakInputSource\n
+3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF1          BKDFBKE        LL_TIM_DisableBreakInputSource\n
+3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2INE         LL_TIM_DisableBreakInputSource\n
+3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2DFBKE       LL_TIM_DisableBreakInputSource
+3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakInput This parameter can be one of the following values:
+3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Source This parameter can be one of the following values:
+3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_
+3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(*pReg, Source);
+ARM GAS  /tmp/ccI26Lsx.s 			page 157
+
+
+3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Set the polarity of the break signal for the timer break input.
+3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       or not a timer instance allows for break input selection.
+3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll AF1          BKINP          LL_TIM_SetBreakInputSourcePolarity\n
+3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF1          BKDFBKP        LL_TIM_SetBreakInputSourcePolarity\n
+3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2INP         LL_TIM_SetBreakInputSourcePolarity\n
+3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         AF2          BK2DFBKP       LL_TIM_SetBreakInputSourcePolarity
+3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  BreakInput This parameter can be one of the following values:
+3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Source This parameter can be one of the following values:
+3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Polarity This parameter can be one of the following values:
+3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
+3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uin
+3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****                                                         uint32_t Polarity)
+3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOUR
+3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */
+3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Configures the timer DMA burst feature.
+3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       not a timer instance supports the DMA burst mode.
+3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         DCR          DBA           LL_TIM_ConfigDMABurst
+3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DMABurstBaseAddress This parameter can be one of the following values:
+3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+ARM GAS  /tmp/ccI26Lsx.s 			page 158
+
+
+3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR
+3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1  (*)
+3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2  (*)
+3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (*) value not defined in all devices
+3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  DMABurstLength This parameter can be one of the following values:
+3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_
+3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
+3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Remap TIM inputs (input channel, internal/external triggers).
+3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *       a some timer inputs can be remapped.
+3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll TIM2_OR     ITR1_RMP          LL_TIM_SetRemap\n
+3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM5_OR     TI4_RMP           LL_TIM_SetRemap\n
+3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM11_OR    TI1_RMP           LL_TIM_SetRemap
+3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  Remap Remap param depends on the TIMx. Description available only
+3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         in CHM version of the User Manual (not in .pdf).
+3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         Otherwise see Reference Manual description of OR registers.
+3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+ARM GAS  /tmp/ccI26Lsx.s 			page 159
+
+
+3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         Below description summarizes "Timer Instance" and "Remap" param combinations:
+3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM2: one of the following values
+3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            ITR1_RMP can be one of the following values
+3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
+3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP
+3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
+3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
+3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM5: one of the following values
+3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
+3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
+3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
+3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
+3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         TIM11: one of the following values
+3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
+3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX
+3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_HSE
+3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *            @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1
+3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *
+3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the update interrupt flag (UIF).
+3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
+3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ARM GAS  /tmp/ccI26Lsx.s 			page 160
+
+
+3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 inte
+3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
+3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 inte
+3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
+3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ARM GAS  /tmp/ccI26Lsx.s 			page 161
+
+
+3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 inte
+3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
+3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 inte
+3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
+3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
+3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
+3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 inte
+3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
+3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
+3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
+3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ARM GAS  /tmp/ccI26Lsx.s 			page 162
+
+
+3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
+3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
+3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 inte
+3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
+3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
+3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
+3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the commutation interrupt flag (COMIF).
+3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
+3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pe
+3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
+3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
+3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the trigger interrupt flag (TIF).
+3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+ARM GAS  /tmp/ccI26Lsx.s 			page 163
+
+
+3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
+3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the break interrupt flag (BIF).
+3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
+3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
+3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
+3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the break 2 interrupt flag (B2IF).
+3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
+3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
+3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
+3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
+3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+ARM GAS  /tmp/ccI26Lsx.s 			page 164
+
+
+3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (Capture/Compare 1 interrupt is pending).
+3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
+3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (Capture/Compare 2 over-capture interrupt is pending).
+4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
+4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (Capture/Compare 3 over-capture interrupt is pending).
+4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+ARM GAS  /tmp/ccI26Lsx.s 			page 165
+
+
+4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
+4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   *         (Capture/Compare 4 over-capture interrupt is pending).
+4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
+4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Clear the system break interrupt flag (SBIF).
+4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
+4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
+4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is p
+4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
+4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
+4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
+4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_IT_Management IT-Management
+ARM GAS  /tmp/ccI26Lsx.s 			page 166
+
+
+4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable update interrupt (UIE).
+4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+4093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable update interrupt (UIE).
+4097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+4098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+4102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+4104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the update interrupt (UIE) is enabled.
+4108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+4109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
+4113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+4115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable capture/compare 1 interrupt (CC1IE).
+4119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+4120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+4124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+4126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable capture/compare 1  interrupt (CC1IE).
+4130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+4131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+4135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+4137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 167
+
+
+4139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+4141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+4142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
+4146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+4148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable capture/compare 2 interrupt (CC2IE).
+4152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+4153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+4157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+4159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable capture/compare 2  interrupt (CC2IE).
+4163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+4164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+4168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+4170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+4174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+4175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
+4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable capture/compare 3 interrupt (CC3IE).
+4185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+4186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+4190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+4192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable capture/compare 3  interrupt (CC3IE).
+ARM GAS  /tmp/ccI26Lsx.s 			page 168
+
+
+4196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+4197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+4201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+4203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+4207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+4208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
+4212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+4214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable capture/compare 4 interrupt (CC4IE).
+4218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+4219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+4223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+4225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable capture/compare 4  interrupt (CC4IE).
+4229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+4230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+4234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+4236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+4240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+4241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
+4245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+4247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable commutation interrupt (COMIE).
+4251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
+4252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+ARM GAS  /tmp/ccI26Lsx.s 			page 169
+
+
+4253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+4256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+4258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable commutation interrupt (COMIE).
+4262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
+4263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+4267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+4269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
+4273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
+4274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
+4278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
+4280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable trigger interrupt (TIE).
+4284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+4285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+4289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+4291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable trigger interrupt (TIE).
+4295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+4296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+4300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+4302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+4306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+4307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+ARM GAS  /tmp/ccI26Lsx.s 			page 170
+
+
+4310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
+4311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+4313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable break interrupt (BIE).
+4317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
+4318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+4322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+4324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable break interrupt (BIE).
+4328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
+4329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+4333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+4335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the break interrupt (BIE) is enabled.
+4339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
+4340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
+4344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+4346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+4350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Management DMA Management
+4353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+4354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable update DMA request (UDE).
+4357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+4358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+4362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+4364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+ARM GAS  /tmp/ccI26Lsx.s 			page 171
+
+
+4367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable update DMA request (UDE).
+4368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+4369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+4373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+4375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+4379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+4380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
+4384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+4386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable capture/compare 1 DMA request (CC1DE).
+4390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+4391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+4395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+4397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable capture/compare 1  DMA request (CC1DE).
+4401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+4402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+4406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+4408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+4412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+4413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
+4417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+4419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable capture/compare 2 DMA request (CC2DE).
+4423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+ARM GAS  /tmp/ccI26Lsx.s 			page 172
+
+
+4424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+4428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+4430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable capture/compare 2  DMA request (CC2DE).
+4434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+4435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+4439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+4441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+4445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+4446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
+4450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+4452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable capture/compare 3 DMA request (CC3DE).
+4456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+4457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+4461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+4463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable capture/compare 3  DMA request (CC3DE).
+4467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+4468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+4472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+4474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+4478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+4479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+ARM GAS  /tmp/ccI26Lsx.s 			page 173
+
+
+4481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
+4483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+4485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable capture/compare 4 DMA request (CC4DE).
+4489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+4490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+4494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+4496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable capture/compare 4  DMA request (CC4DE).
+4500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+4501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+4505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+4507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+4511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+4512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
+4516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+4518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable commutation DMA request (COMDE).
+4522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
+4523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+4527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+4529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable commutation DMA request (COMDE).
+4533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
+4534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+ARM GAS  /tmp/ccI26Lsx.s 			page 174
+
+
+4538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+4540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
+4544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
+4545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
+4549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
+4551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Enable trigger interrupt (TDE).
+4555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+4556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+4560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+4562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Disable trigger interrupt (TDE).
+4566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+4567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+4571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+4573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+4577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+4578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval State of bit (1 or 0).
+4580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
+4582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+4584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+4585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @}
+4588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 
+4590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+4591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @{
+4592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /**
+4594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @brief  Generate an update event.
+ARM GAS  /tmp/ccI26Lsx.s 			page 175
+
+
+4595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+4596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @param  TIMx Timer instance
+4597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   * @retval None
+4598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   */
+4599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+ 1948              		.loc 2 4599 22 view .LVU547
+ 1949              	.LBB185:
+4600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+4601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h ****   SET_BIT(TIMx->EGR, TIM_EGR_UG);
+ 1950              		.loc 2 4601 3 view .LVU548
+ 1951 00e6 4369     		ldr	r3, [r0, #20]
+ 1952 00e8 43F00103 		orr	r3, r3, #1
+ 1953 00ec 4361     		str	r3, [r0, #20]
+ 1954              	.LVL173:
+ 1955              		.loc 2 4601 3 is_stmt 0 view .LVU549
+ 1956              	.LBE185:
+ 1957              	.LBE184:
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 1958              		.loc 1 392 3 is_stmt 1 view .LVU550
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1959              		.loc 1 393 1 is_stmt 0 view .LVU551
+ 1960 00ee 0020     		movs	r0, #0
+ 1961              	.LVL174:
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 1962              		.loc 1 393 1 view .LVU552
+ 1963 00f0 30BD     		pop	{r4, r5, pc}
+ 1964              	.L82:
+ 1965 00f2 00BF     		.align	2
+ 1966              	.L81:
+ 1967 00f4 00000140 		.word	1073807360
+ 1968 00f8 00080040 		.word	1073743872
+ 1969 00fc 00040040 		.word	1073742848
+ 1970 0100 00440140 		.word	1073824768
+ 1971 0104 00180040 		.word	1073747968
+ 1972 0108 00200040 		.word	1073750016
+ 1973 010c 00040140 		.word	1073808384
+ 1974              		.cfi_endproc
+ 1975              	.LFE380:
+ 1977              		.section	.text.LL_TIM_OC_StructInit,"ax",%progbits
+ 1978              		.align	1
+ 1979              		.global	LL_TIM_OC_StructInit
+ 1980              		.syntax unified
+ 1981              		.thumb
+ 1982              		.thumb_func
+ 1983              		.fpu fpv5-d16
+ 1985              	LL_TIM_OC_StructInit:
+ 1986              	.LVL175:
+ 1987              	.LFB381:
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 1988              		.loc 1 403 1 is_stmt 1 view -0
+ 1989              		.cfi_startproc
+ 1990              		@ args = 0, pretend = 0, frame = 0
+ 1991              		@ frame_needed = 0, uses_anonymous_args = 0
+ 1992              		@ link register save eliminated.
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
+ 1993              		.loc 1 405 3 view .LVU554
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
+ARM GAS  /tmp/ccI26Lsx.s 			page 176
+
+
+ 1994              		.loc 1 405 35 is_stmt 0 view .LVU555
+ 1995 0000 0023     		movs	r3, #0
+ 1996 0002 0360     		str	r3, [r0]
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
+ 1997              		.loc 1 406 3 is_stmt 1 view .LVU556
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
+ 1998              		.loc 1 406 35 is_stmt 0 view .LVU557
+ 1999 0004 4360     		str	r3, [r0, #4]
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->CompareValue = 0x00000000U;
+ 2000              		.loc 1 407 3 is_stmt 1 view .LVU558
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->CompareValue = 0x00000000U;
+ 2001              		.loc 1 407 35 is_stmt 0 view .LVU559
+ 2002 0006 8360     		str	r3, [r0, #8]
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
+ 2003              		.loc 1 408 3 is_stmt 1 view .LVU560
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
+ 2004              		.loc 1 408 35 is_stmt 0 view .LVU561
+ 2005 0008 C360     		str	r3, [r0, #12]
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
+ 2006              		.loc 1 409 3 is_stmt 1 view .LVU562
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
+ 2007              		.loc 1 409 35 is_stmt 0 view .LVU563
+ 2008 000a 0361     		str	r3, [r0, #16]
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
+ 2009              		.loc 1 410 3 is_stmt 1 view .LVU564
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
+ 2010              		.loc 1 410 35 is_stmt 0 view .LVU565
+ 2011 000c 4361     		str	r3, [r0, #20]
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+ 2012              		.loc 1 411 3 is_stmt 1 view .LVU566
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+ 2013              		.loc 1 411 35 is_stmt 0 view .LVU567
+ 2014 000e 8361     		str	r3, [r0, #24]
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2015              		.loc 1 412 3 is_stmt 1 view .LVU568
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2016              		.loc 1 412 35 is_stmt 0 view .LVU569
+ 2017 0010 C361     		str	r3, [r0, #28]
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2018              		.loc 1 413 1 view .LVU570
+ 2019 0012 7047     		bx	lr
+ 2020              		.cfi_endproc
+ 2021              	.LFE381:
+ 2023              		.section	.text.LL_TIM_OC_Init,"ax",%progbits
+ 2024              		.align	1
+ 2025              		.global	LL_TIM_OC_Init
+ 2026              		.syntax unified
+ 2027              		.thumb
+ 2028              		.thumb_func
+ 2029              		.fpu fpv5-d16
+ 2031              	LL_TIM_OC_Init:
+ 2032              	.LVL176:
+ 2033              	.LFB382:
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   ErrorStatus result = ERROR;
+ 2034              		.loc 1 432 1 is_stmt 1 view -0
+ 2035              		.cfi_startproc
+ 2036              		@ args = 0, pretend = 0, frame = 0
+ARM GAS  /tmp/ccI26Lsx.s 			page 177
+
+
+ 2037              		@ frame_needed = 0, uses_anonymous_args = 0
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   ErrorStatus result = ERROR;
+ 2038              		.loc 1 432 1 is_stmt 0 view .LVU572
+ 2039 0000 08B5     		push	{r3, lr}
+ 2040              	.LCFI21:
+ 2041              		.cfi_def_cfa_offset 8
+ 2042              		.cfi_offset 3, -8
+ 2043              		.cfi_offset 14, -4
+ 2044 0002 0B46     		mov	r3, r1
+ 2045 0004 1146     		mov	r1, r2
+ 2046              	.LVL177:
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2047              		.loc 1 433 3 is_stmt 1 view .LVU573
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2048              		.loc 1 435 3 view .LVU574
+ 2049 0006 B3F5805F 		cmp	r3, #4096
+ 2050 000a 1DD0     		beq	.L85
+ 2051 000c 0ED8     		bhi	.L86
+ 2052 000e 102B     		cmp	r3, #16
+ 2053 0010 17D0     		beq	.L87
+ 2054 0012 B3F5807F 		cmp	r3, #256
+ 2055 0016 02D1     		bne	.L94
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2056              		.loc 1 444 7 view .LVU575
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2057              		.loc 1 444 16 is_stmt 0 view .LVU576
+ 2058 0018 FFF7FEFF 		bl	OC3Config
+ 2059              	.LVL178:
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH4:
+ 2060              		.loc 1 445 7 is_stmt 1 view .LVU577
+ 2061 001c 05E0     		b	.L90
+ 2062              	.LVL179:
+ 2063              	.L94:
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2064              		.loc 1 435 3 is_stmt 0 view .LVU578
+ 2065 001e 012B     		cmp	r3, #1
+ 2066 0020 02D1     		bne	.L95
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2067              		.loc 1 438 7 is_stmt 1 view .LVU579
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2068              		.loc 1 438 16 is_stmt 0 view .LVU580
+ 2069 0022 FFF7FEFF 		bl	OC1Config
+ 2070              	.LVL180:
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH2:
+ 2071              		.loc 1 439 7 is_stmt 1 view .LVU581
+ 2072 0026 00E0     		b	.L90
+ 2073              	.LVL181:
+ 2074              	.L95:
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2075              		.loc 1 435 3 is_stmt 0 view .LVU582
+ 2076 0028 0120     		movs	r0, #1
+ 2077              	.LVL182:
+ 2078              	.L90:
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2079              		.loc 1 459 3 is_stmt 1 view .LVU583
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2080              		.loc 1 460 1 is_stmt 0 view .LVU584
+ARM GAS  /tmp/ccI26Lsx.s 			page 178
+
+
+ 2081 002a 08BD     		pop	{r3, pc}
+ 2082              	.LVL183:
+ 2083              	.L86:
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2084              		.loc 1 435 3 view .LVU585
+ 2085 002c B3F5803F 		cmp	r3, #65536
+ 2086 0030 0DD0     		beq	.L91
+ 2087 0032 B3F5801F 		cmp	r3, #1048576
+ 2088 0036 02D1     		bne	.L96
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2089              		.loc 1 453 7 is_stmt 1 view .LVU586
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2090              		.loc 1 453 16 is_stmt 0 view .LVU587
+ 2091 0038 FFF7FEFF 		bl	OC6Config
+ 2092              	.LVL184:
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     default:
+ 2093              		.loc 1 454 7 is_stmt 1 view .LVU588
+ 2094 003c F5E7     		b	.L90
+ 2095              	.LVL185:
+ 2096              	.L96:
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2097              		.loc 1 435 3 is_stmt 0 view .LVU589
+ 2098 003e 0120     		movs	r0, #1
+ 2099              	.LVL186:
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2100              		.loc 1 435 3 view .LVU590
+ 2101 0040 F3E7     		b	.L90
+ 2102              	.LVL187:
+ 2103              	.L87:
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2104              		.loc 1 441 7 is_stmt 1 view .LVU591
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2105              		.loc 1 441 16 is_stmt 0 view .LVU592
+ 2106 0042 FFF7FEFF 		bl	OC2Config
+ 2107              	.LVL188:
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH3:
+ 2108              		.loc 1 442 7 is_stmt 1 view .LVU593
+ 2109 0046 F0E7     		b	.L90
+ 2110              	.LVL189:
+ 2111              	.L85:
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2112              		.loc 1 447 7 view .LVU594
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2113              		.loc 1 447 16 is_stmt 0 view .LVU595
+ 2114 0048 FFF7FEFF 		bl	OC4Config
+ 2115              	.LVL190:
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH5:
+ 2116              		.loc 1 448 7 is_stmt 1 view .LVU596
+ 2117 004c EDE7     		b	.L90
+ 2118              	.LVL191:
+ 2119              	.L91:
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2120              		.loc 1 450 7 view .LVU597
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2121              		.loc 1 450 16 is_stmt 0 view .LVU598
+ 2122 004e FFF7FEFF 		bl	OC5Config
+ 2123              	.LVL192:
+ARM GAS  /tmp/ccI26Lsx.s 			page 179
+
+
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH6:
+ 2124              		.loc 1 451 7 is_stmt 1 view .LVU599
+ 2125 0052 EAE7     		b	.L90
+ 2126              		.cfi_endproc
+ 2127              	.LFE382:
+ 2129              		.section	.text.LL_TIM_IC_StructInit,"ax",%progbits
+ 2130              		.align	1
+ 2131              		.global	LL_TIM_IC_StructInit
+ 2132              		.syntax unified
+ 2133              		.thumb
+ 2134              		.thumb_func
+ 2135              		.fpu fpv5-d16
+ 2137              	LL_TIM_IC_StructInit:
+ 2138              	.LVL193:
+ 2139              	.LFB383:
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 2140              		.loc 1 470 1 view -0
+ 2141              		.cfi_startproc
+ 2142              		@ args = 0, pretend = 0, frame = 0
+ 2143              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2144              		@ link register save eliminated.
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ 2145              		.loc 1 472 3 view .LVU601
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ 2146              		.loc 1 472 35 is_stmt 0 view .LVU602
+ 2147 0000 0023     		movs	r3, #0
+ 2148 0002 0360     		str	r3, [r0]
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
+ 2149              		.loc 1 473 3 is_stmt 1 view .LVU603
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
+ 2150              		.loc 1 473 35 is_stmt 0 view .LVU604
+ 2151 0004 4FF48032 		mov	r2, #65536
+ 2152 0008 4260     		str	r2, [r0, #4]
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
+ 2153              		.loc 1 474 3 is_stmt 1 view .LVU605
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
+ 2154              		.loc 1 474 35 is_stmt 0 view .LVU606
+ 2155 000a 8360     		str	r3, [r0, #8]
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2156              		.loc 1 475 3 is_stmt 1 view .LVU607
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2157              		.loc 1 475 35 is_stmt 0 view .LVU608
+ 2158 000c C360     		str	r3, [r0, #12]
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2159              		.loc 1 476 1 view .LVU609
+ 2160 000e 7047     		bx	lr
+ 2161              		.cfi_endproc
+ 2162              	.LFE383:
+ 2164              		.section	.text.LL_TIM_IC_Init,"ax",%progbits
+ 2165              		.align	1
+ 2166              		.global	LL_TIM_IC_Init
+ 2167              		.syntax unified
+ 2168              		.thumb
+ 2169              		.thumb_func
+ 2170              		.fpu fpv5-d16
+ 2172              	LL_TIM_IC_Init:
+ 2173              	.LVL194:
+ARM GAS  /tmp/ccI26Lsx.s 			page 180
+
+
+ 2174              	.LFB384:
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   ErrorStatus result = ERROR;
+ 2175              		.loc 1 493 1 is_stmt 1 view -0
+ 2176              		.cfi_startproc
+ 2177              		@ args = 0, pretend = 0, frame = 0
+ 2178              		@ frame_needed = 0, uses_anonymous_args = 0
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   ErrorStatus result = ERROR;
+ 2179              		.loc 1 493 1 is_stmt 0 view .LVU611
+ 2180 0000 08B5     		push	{r3, lr}
+ 2181              	.LCFI22:
+ 2182              		.cfi_def_cfa_offset 8
+ 2183              		.cfi_offset 3, -8
+ 2184              		.cfi_offset 14, -4
+ 2185 0002 0B46     		mov	r3, r1
+ 2186 0004 1146     		mov	r1, r2
+ 2187              	.LVL195:
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2188              		.loc 1 494 3 is_stmt 1 view .LVU612
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2189              		.loc 1 496 3 view .LVU613
+ 2190 0006 B3F5807F 		cmp	r3, #256
+ 2191 000a 14D0     		beq	.L99
+ 2192 000c 08D8     		bhi	.L100
+ 2193 000e 012B     		cmp	r3, #1
+ 2194 0010 0ED0     		beq	.L101
+ 2195 0012 102B     		cmp	r3, #16
+ 2196 0014 02D1     		bne	.L106
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2197              		.loc 1 502 7 view .LVU614
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2198              		.loc 1 502 16 is_stmt 0 view .LVU615
+ 2199 0016 FFF7FEFF 		bl	IC2Config
+ 2200              	.LVL196:
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH3:
+ 2201              		.loc 1 503 7 is_stmt 1 view .LVU616
+ 2202 001a 08E0     		b	.L103
+ 2203              	.LVL197:
+ 2204              	.L106:
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2205              		.loc 1 496 3 is_stmt 0 view .LVU617
+ 2206 001c 0120     		movs	r0, #1
+ 2207              	.LVL198:
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2208              		.loc 1 496 3 view .LVU618
+ 2209 001e 06E0     		b	.L103
+ 2210              	.LVL199:
+ 2211              	.L100:
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2212              		.loc 1 496 3 view .LVU619
+ 2213 0020 B3F5805F 		cmp	r3, #4096
+ 2214 0024 02D1     		bne	.L107
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2215              		.loc 1 508 7 is_stmt 1 view .LVU620
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2216              		.loc 1 508 16 is_stmt 0 view .LVU621
+ 2217 0026 FFF7FEFF 		bl	IC4Config
+ 2218              	.LVL200:
+ARM GAS  /tmp/ccI26Lsx.s 			page 181
+
+
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     default:
+ 2219              		.loc 1 509 7 is_stmt 1 view .LVU622
+ 2220 002a 00E0     		b	.L103
+ 2221              	.LVL201:
+ 2222              	.L107:
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2223              		.loc 1 496 3 is_stmt 0 view .LVU623
+ 2224 002c 0120     		movs	r0, #1
+ 2225              	.LVL202:
+ 2226              	.L103:
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2227              		.loc 1 514 3 is_stmt 1 view .LVU624
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2228              		.loc 1 515 1 is_stmt 0 view .LVU625
+ 2229 002e 08BD     		pop	{r3, pc}
+ 2230              	.LVL203:
+ 2231              	.L101:
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2232              		.loc 1 499 7 is_stmt 1 view .LVU626
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2233              		.loc 1 499 16 is_stmt 0 view .LVU627
+ 2234 0030 FFF7FEFF 		bl	IC1Config
+ 2235              	.LVL204:
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH2:
+ 2236              		.loc 1 500 7 is_stmt 1 view .LVU628
+ 2237 0034 FBE7     		b	.L103
+ 2238              	.LVL205:
+ 2239              	.L99:
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2240              		.loc 1 505 7 view .LVU629
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****       break;
+ 2241              		.loc 1 505 16 is_stmt 0 view .LVU630
+ 2242 0036 FFF7FEFF 		bl	IC3Config
+ 2243              	.LVL206:
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     case LL_TIM_CHANNEL_CH4:
+ 2244              		.loc 1 506 7 is_stmt 1 view .LVU631
+ 2245 003a F8E7     		b	.L103
+ 2246              		.cfi_endproc
+ 2247              	.LFE384:
+ 2249              		.section	.text.LL_TIM_ENCODER_StructInit,"ax",%progbits
+ 2250              		.align	1
+ 2251              		.global	LL_TIM_ENCODER_StructInit
+ 2252              		.syntax unified
+ 2253              		.thumb
+ 2254              		.thumb_func
+ 2255              		.fpu fpv5-d16
+ 2257              	LL_TIM_ENCODER_StructInit:
+ 2258              	.LVL207:
+ 2259              	.LFB385:
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 2260              		.loc 1 524 1 view -0
+ 2261              		.cfi_startproc
+ 2262              		@ args = 0, pretend = 0, frame = 0
+ 2263              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2264              		@ link register save eliminated.
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
+ 2265              		.loc 1 526 3 view .LVU633
+ARM GAS  /tmp/ccI26Lsx.s 			page 182
+
+
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
+ 2266              		.loc 1 526 41 is_stmt 0 view .LVU634
+ 2267 0000 0123     		movs	r3, #1
+ 2268 0002 0360     		str	r3, [r0]
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ 2269              		.loc 1 527 3 is_stmt 1 view .LVU635
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ 2270              		.loc 1 527 41 is_stmt 0 view .LVU636
+ 2271 0004 0023     		movs	r3, #0
+ 2272 0006 4360     		str	r3, [r0, #4]
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
+ 2273              		.loc 1 528 3 is_stmt 1 view .LVU637
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
+ 2274              		.loc 1 528 41 is_stmt 0 view .LVU638
+ 2275 0008 4FF48032 		mov	r2, #65536
+ 2276 000c 8260     		str	r2, [r0, #8]
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
+ 2277              		.loc 1 529 3 is_stmt 1 view .LVU639
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
+ 2278              		.loc 1 529 41 is_stmt 0 view .LVU640
+ 2279 000e C360     		str	r3, [r0, #12]
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
+ 2280              		.loc 1 530 3 is_stmt 1 view .LVU641
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
+ 2281              		.loc 1 530 41 is_stmt 0 view .LVU642
+ 2282 0010 0361     		str	r3, [r0, #16]
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ 2283              		.loc 1 531 3 is_stmt 1 view .LVU643
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ 2284              		.loc 1 531 41 is_stmt 0 view .LVU644
+ 2285 0012 4361     		str	r3, [r0, #20]
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
+ 2286              		.loc 1 532 3 is_stmt 1 view .LVU645
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
+ 2287              		.loc 1 532 41 is_stmt 0 view .LVU646
+ 2288 0014 8261     		str	r2, [r0, #24]
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
+ 2289              		.loc 1 533 3 is_stmt 1 view .LVU647
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
+ 2290              		.loc 1 533 41 is_stmt 0 view .LVU648
+ 2291 0016 C361     		str	r3, [r0, #28]
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2292              		.loc 1 534 3 is_stmt 1 view .LVU649
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2293              		.loc 1 534 41 is_stmt 0 view .LVU650
+ 2294 0018 0362     		str	r3, [r0, #32]
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2295              		.loc 1 535 1 view .LVU651
+ 2296 001a 7047     		bx	lr
+ 2297              		.cfi_endproc
+ 2298              	.LFE385:
+ 2300              		.section	.text.LL_TIM_ENCODER_Init,"ax",%progbits
+ 2301              		.align	1
+ 2302              		.global	LL_TIM_ENCODER_Init
+ 2303              		.syntax unified
+ 2304              		.thumb
+ 2305              		.thumb_func
+ARM GAS  /tmp/ccI26Lsx.s 			page 183
+
+
+ 2306              		.fpu fpv5-d16
+ 2308              	LL_TIM_ENCODER_Init:
+ 2309              	.LVL208:
+ 2310              	.LFB386:
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccmr1;
+ 2311              		.loc 1 547 1 is_stmt 1 view -0
+ 2312              		.cfi_startproc
+ 2313              		@ args = 0, pretend = 0, frame = 0
+ 2314              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2315              		@ link register save eliminated.
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccmr1;
+ 2316              		.loc 1 547 1 is_stmt 0 view .LVU653
+ 2317 0000 30B4     		push	{r4, r5}
+ 2318              	.LCFI23:
+ 2319              		.cfi_def_cfa_offset 8
+ 2320              		.cfi_offset 4, -8
+ 2321              		.cfi_offset 5, -4
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccer;
+ 2322              		.loc 1 548 3 is_stmt 1 view .LVU654
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2323              		.loc 1 549 3 view .LVU655
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+ 2324              		.loc 1 552 3 view .LVU656
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+ 2325              		.loc 1 553 3 view .LVU657
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+ 2326              		.loc 1 554 3 view .LVU658
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+ 2327              		.loc 1 555 3 view .LVU659
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+ 2328              		.loc 1 556 3 view .LVU660
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+ 2329              		.loc 1 557 3 view .LVU661
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+ 2330              		.loc 1 558 3 view .LVU662
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+ 2331              		.loc 1 559 3 view .LVU663
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+ 2332              		.loc 1 560 3 view .LVU664
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2333              		.loc 1 561 3 view .LVU665
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2334              		.loc 1 564 3 view .LVU666
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2335              		.loc 1 564 14 is_stmt 0 view .LVU667
+ 2336 0002 036A     		ldr	r3, [r0, #32]
+ 2337 0004 23F01103 		bic	r3, r3, #17
+ 2338 0008 0362     		str	r3, [r0, #32]
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2339              		.loc 1 567 3 is_stmt 1 view .LVU668
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2340              		.loc 1 567 12 is_stmt 0 view .LVU669
+ 2341 000a 8369     		ldr	r3, [r0, #24]
+ 2342              	.LVL209:
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2343              		.loc 1 570 3 is_stmt 1 view .LVU670
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ARM GAS  /tmp/ccI26Lsx.s 			page 184
+
+
+ 2344              		.loc 1 570 11 is_stmt 0 view .LVU671
+ 2345 000c 026A     		ldr	r2, [r0, #32]
+ 2346              	.LVL210:
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+ 2347              		.loc 1 573 3 is_stmt 1 view .LVU672
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+ 2348              		.loc 1 573 12 is_stmt 0 view .LVU673
+ 2349 000e 23F0FF03 		bic	r3, r3, #255
+ 2350              	.LVL211:
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+ 2351              		.loc 1 574 3 is_stmt 1 view .LVU674
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+ 2352              		.loc 1 574 64 is_stmt 0 view .LVU675
+ 2353 0012 4C89     		ldrh	r4, [r1, #10]
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+ 2354              		.loc 1 574 12 view .LVU676
+ 2355 0014 1C43     		orrs	r4, r4, r3
+ 2356              	.LVL212:
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+ 2357              		.loc 1 575 3 is_stmt 1 view .LVU677
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+ 2358              		.loc 1 575 59 is_stmt 0 view .LVU678
+ 2359 0016 4B8A     		ldrh	r3, [r1, #18]
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+ 2360              		.loc 1 575 12 view .LVU679
+ 2361 0018 1C43     		orrs	r4, r4, r3
+ 2362              	.LVL213:
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2363              		.loc 1 576 3 is_stmt 1 view .LVU680
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2364              		.loc 1 576 62 is_stmt 0 view .LVU681
+ 2365 001a CB89     		ldrh	r3, [r1, #14]
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2366              		.loc 1 576 12 view .LVU682
+ 2367 001c 2343     		orrs	r3, r3, r4
+ 2368              	.LVL214:
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+ 2369              		.loc 1 579 3 is_stmt 1 view .LVU683
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+ 2370              		.loc 1 579 12 is_stmt 0 view .LVU684
+ 2371 001e 23F47F43 		bic	r3, r3, #65280
+ 2372              	.LVL215:
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+ 2373              		.loc 1 580 3 is_stmt 1 view .LVU685
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+ 2374              		.loc 1 580 47 is_stmt 0 view .LVU686
+ 2375 0022 8C69     		ldr	r4, [r1, #24]
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+ 2376              		.loc 1 580 12 view .LVU687
+ 2377 0024 43EA1423 		orr	r3, r3, r4, lsr #8
+ 2378              	.LVL216:
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+ 2379              		.loc 1 581 3 is_stmt 1 view .LVU688
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+ 2380              		.loc 1 581 47 is_stmt 0 view .LVU689
+ 2381 0028 0C6A     		ldr	r4, [r1, #32]
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+ARM GAS  /tmp/ccI26Lsx.s 			page 185
+
+
+ 2382              		.loc 1 581 12 view .LVU690
+ 2383 002a 43EA1423 		orr	r3, r3, r4, lsr #8
+ 2384              	.LVL217:
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2385              		.loc 1 582 3 is_stmt 1 view .LVU691
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2386              		.loc 1 582 47 is_stmt 0 view .LVU692
+ 2387 002e CC69     		ldr	r4, [r1, #28]
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2388              		.loc 1 582 12 view .LVU693
+ 2389 0030 43EA1423 		orr	r3, r3, r4, lsr #8
+ 2390              	.LVL218:
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+ 2391              		.loc 1 585 3 is_stmt 1 view .LVU694
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+ 2392              		.loc 1 585 11 is_stmt 0 view .LVU695
+ 2393 0034 22F0AA04 		bic	r4, r2, #170
+ 2394              	.LVL219:
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+ 2395              		.loc 1 586 3 is_stmt 1 view .LVU696
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+ 2396              		.loc 1 586 46 is_stmt 0 view .LVU697
+ 2397 0038 4A68     		ldr	r2, [r1, #4]
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+ 2398              		.loc 1 586 11 view .LVU698
+ 2399 003a 2243     		orrs	r2, r2, r4
+ 2400              	.LVL220:
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+ 2401              		.loc 1 587 3 is_stmt 1 view .LVU699
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+ 2402              		.loc 1 587 46 is_stmt 0 view .LVU700
+ 2403 003c 4C69     		ldr	r4, [r1, #20]
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+ 2404              		.loc 1 587 11 view .LVU701
+ 2405 003e 42EA0412 		orr	r2, r2, r4, lsl #4
+ 2406              	.LVL221:
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2407              		.loc 1 588 3 is_stmt 1 view .LVU702
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2408              		.loc 1 588 11 is_stmt 0 view .LVU703
+ 2409 0042 42F01102 		orr	r2, r2, #17
+ 2410              	.LVL222:
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2411              		.loc 1 591 3 is_stmt 1 view .LVU704
+ 2412 0046 0968     		ldr	r1, [r1]
+ 2413              	.LVL223:
+ 2414              	.LBB186:
+ 2415              	.LBI186:
+3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 2416              		.loc 2 3109 22 view .LVU705
+ 2417              	.LBB187:
+3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 2418              		.loc 2 3111 3 view .LVU706
+ 2419 0048 8568     		ldr	r5, [r0, #8]
+ 2420 004a 044C     		ldr	r4, .L111
+ 2421 004c 2C40     		ands	r4, r4, r5
+ 2422 004e 2143     		orrs	r1, r1, r4
+ARM GAS  /tmp/ccI26Lsx.s 			page 186
+
+
+ 2423              	.LVL224:
+3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 2424              		.loc 2 3111 3 is_stmt 0 view .LVU707
+ 2425 0050 8160     		str	r1, [r0, #8]
+ 2426              	.LVL225:
+3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 2427              		.loc 2 3111 3 view .LVU708
+ 2428              	.LBE187:
+ 2429              	.LBE186:
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2430              		.loc 1 594 3 is_stmt 1 view .LVU709
+ 2431 0052 8361     		str	r3, [r0, #24]
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2432              		.loc 1 597 3 view .LVU710
+ 2433 0054 0262     		str	r2, [r0, #32]
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2434              		.loc 1 599 3 view .LVU711
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2435              		.loc 1 600 1 is_stmt 0 view .LVU712
+ 2436 0056 0020     		movs	r0, #0
+ 2437              	.LVL226:
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2438              		.loc 1 600 1 view .LVU713
+ 2439 0058 30BC     		pop	{r4, r5}
+ 2440              	.LCFI24:
+ 2441              		.cfi_restore 5
+ 2442              		.cfi_restore 4
+ 2443              		.cfi_def_cfa_offset 0
+ 2444 005a 7047     		bx	lr
+ 2445              	.L112:
+ 2446              		.align	2
+ 2447              	.L111:
+ 2448 005c F8FFFEFF 		.word	-65544
+ 2449              		.cfi_endproc
+ 2450              	.LFE386:
+ 2452              		.section	.text.LL_TIM_HALLSENSOR_StructInit,"ax",%progbits
+ 2453              		.align	1
+ 2454              		.global	LL_TIM_HALLSENSOR_StructInit
+ 2455              		.syntax unified
+ 2456              		.thumb
+ 2457              		.thumb_func
+ 2458              		.fpu fpv5-d16
+ 2460              	LL_TIM_HALLSENSOR_StructInit:
+ 2461              	.LVL227:
+ 2462              	.LFB387:
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 2463              		.loc 1 610 1 is_stmt 1 view -0
+ 2464              		.cfi_startproc
+ 2465              		@ args = 0, pretend = 0, frame = 0
+ 2466              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2467              		@ link register save eliminated.
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
+ 2468              		.loc 1 612 3 view .LVU715
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
+ 2469              		.loc 1 612 47 is_stmt 0 view .LVU716
+ 2470 0000 0023     		movs	r3, #0
+ 2471 0002 0360     		str	r3, [r0]
+ARM GAS  /tmp/ccI26Lsx.s 			page 187
+
+
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
+ 2472              		.loc 1 613 3 is_stmt 1 view .LVU717
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
+ 2473              		.loc 1 613 47 is_stmt 0 view .LVU718
+ 2474 0004 4360     		str	r3, [r0, #4]
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
+ 2475              		.loc 1 614 3 is_stmt 1 view .LVU719
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
+ 2476              		.loc 1 614 47 is_stmt 0 view .LVU720
+ 2477 0006 8360     		str	r3, [r0, #8]
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2478              		.loc 1 615 3 is_stmt 1 view .LVU721
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2479              		.loc 1 615 47 is_stmt 0 view .LVU722
+ 2480 0008 C360     		str	r3, [r0, #12]
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2481              		.loc 1 616 1 view .LVU723
+ 2482 000a 7047     		bx	lr
+ 2483              		.cfi_endproc
+ 2484              	.LFE387:
+ 2486              		.section	.text.LL_TIM_HALLSENSOR_Init,"ax",%progbits
+ 2487              		.align	1
+ 2488              		.global	LL_TIM_HALLSENSOR_Init
+ 2489              		.syntax unified
+ 2490              		.thumb
+ 2491              		.thumb_func
+ 2492              		.fpu fpv5-d16
+ 2494              	LL_TIM_HALLSENSOR_Init:
+ 2495              	.LVL228:
+ 2496              	.LFB388:
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpcr2;
+ 2497              		.loc 1 640 1 is_stmt 1 view -0
+ 2498              		.cfi_startproc
+ 2499              		@ args = 0, pretend = 0, frame = 0
+ 2500              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2501              		@ link register save eliminated.
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpcr2;
+ 2502              		.loc 1 640 1 is_stmt 0 view .LVU725
+ 2503 0000 70B4     		push	{r4, r5, r6}
+ 2504              	.LCFI25:
+ 2505              		.cfi_def_cfa_offset 12
+ 2506              		.cfi_offset 4, -12
+ 2507              		.cfi_offset 5, -8
+ 2508              		.cfi_offset 6, -4
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccmr1;
+ 2509              		.loc 1 641 3 is_stmt 1 view .LVU726
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpccer;
+ 2510              		.loc 1 642 3 view .LVU727
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpsmcr;
+ 2511              		.loc 1 643 3 view .LVU728
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2512              		.loc 1 644 3 view .LVU729
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+ 2513              		.loc 1 647 3 view .LVU730
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+ 2514              		.loc 1 648 3 view .LVU731
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+ARM GAS  /tmp/ccI26Lsx.s 			page 188
+
+
+ 2515              		.loc 1 649 3 view .LVU732
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2516              		.loc 1 650 3 view .LVU733
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2517              		.loc 1 653 3 view .LVU734
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2518              		.loc 1 653 14 is_stmt 0 view .LVU735
+ 2519 0002 036A     		ldr	r3, [r0, #32]
+ 2520 0004 23F01103 		bic	r3, r3, #17
+ 2521 0008 0362     		str	r3, [r0, #32]
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2522              		.loc 1 656 3 is_stmt 1 view .LVU736
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2523              		.loc 1 656 10 is_stmt 0 view .LVU737
+ 2524 000a 4568     		ldr	r5, [r0, #4]
+ 2525              	.LVL229:
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2526              		.loc 1 659 3 is_stmt 1 view .LVU738
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2527              		.loc 1 659 12 is_stmt 0 view .LVU739
+ 2528 000c 8269     		ldr	r2, [r0, #24]
+ 2529              	.LVL230:
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2530              		.loc 1 662 3 is_stmt 1 view .LVU740
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2531              		.loc 1 662 11 is_stmt 0 view .LVU741
+ 2532 000e 036A     		ldr	r3, [r0, #32]
+ 2533              	.LVL231:
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2534              		.loc 1 665 3 is_stmt 1 view .LVU742
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2535              		.loc 1 665 11 is_stmt 0 view .LVU743
+ 2536 0010 8668     		ldr	r6, [r0, #8]
+ 2537              	.LVL232:
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2538              		.loc 1 668 3 is_stmt 1 view .LVU744
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2539              		.loc 1 671 3 view .LVU745
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2540              		.loc 1 671 10 is_stmt 0 view .LVU746
+ 2541 0012 45F0D005 		orr	r5, r5, #208
+ 2542              	.LVL233:
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpsmcr |= LL_TIM_TS_TI1F_ED;
+ 2543              		.loc 1 674 3 is_stmt 1 view .LVU747
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpsmcr |= LL_TIM_TS_TI1F_ED;
+ 2544              		.loc 1 674 11 is_stmt 0 view .LVU748
+ 2545 0016 124C     		ldr	r4, .L116
+ 2546 0018 3440     		ands	r4, r4, r6
+ 2547              	.LVL234:
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+ 2548              		.loc 1 675 3 is_stmt 1 view .LVU749
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2549              		.loc 1 676 3 view .LVU750
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2550              		.loc 1 676 11 is_stmt 0 view .LVU751
+ 2551 001a 44F04404 		orr	r4, r4, #68
+ 2552              	.LVL235:
+ARM GAS  /tmp/ccI26Lsx.s 			page 189
+
+
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+ 2553              		.loc 1 679 3 is_stmt 1 view .LVU752
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+ 2554              		.loc 1 679 12 is_stmt 0 view .LVU753
+ 2555 001e 22F0FF02 		bic	r2, r2, #255
+ 2556              	.LVL236:
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+ 2557              		.loc 1 680 3 is_stmt 1 view .LVU754
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+ 2558              		.loc 1 680 12 is_stmt 0 view .LVU755
+ 2559 0022 42F00302 		orr	r2, r2, #3
+ 2560              	.LVL237:
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+ 2561              		.loc 1 681 3 is_stmt 1 view .LVU756
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+ 2562              		.loc 1 681 62 is_stmt 0 view .LVU757
+ 2563 0026 B1F80AC0 		ldrh	ip, [r1, #10]
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+ 2564              		.loc 1 681 12 view .LVU758
+ 2565 002a 4CEA0202 		orr	r2, ip, r2
+ 2566              	.LVL238:
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2567              		.loc 1 682 3 is_stmt 1 view .LVU759
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2568              		.loc 1 682 65 is_stmt 0 view .LVU760
+ 2569 002e B1F806C0 		ldrh	ip, [r1, #6]
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2570              		.loc 1 682 12 view .LVU761
+ 2571 0032 4CEA020C 		orr	ip, ip, r2
+ 2572              	.LVL239:
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+ 2573              		.loc 1 685 3 is_stmt 1 view .LVU762
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+ 2574              		.loc 1 685 12 is_stmt 0 view .LVU763
+ 2575 0036 0B4A     		ldr	r2, .L116+4
+ 2576 0038 0CEA0202 		and	r2, ip, r2
+ 2577              	.LVL240:
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2578              		.loc 1 686 3 is_stmt 1 view .LVU764
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2579              		.loc 1 686 12 is_stmt 0 view .LVU765
+ 2580 003c 42F4E042 		orr	r2, r2, #28672
+ 2581              	.LVL241:
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+ 2582              		.loc 1 689 3 is_stmt 1 view .LVU766
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+ 2583              		.loc 1 689 11 is_stmt 0 view .LVU767
+ 2584 0040 23F0AA0C 		bic	ip, r3, #170
+ 2585              	.LVL242:
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+ 2586              		.loc 1 690 3 is_stmt 1 view .LVU768
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+ 2587              		.loc 1 690 49 is_stmt 0 view .LVU769
+ 2588 0044 0B68     		ldr	r3, [r1]
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+ 2589              		.loc 1 690 11 view .LVU770
+ 2590 0046 43EA0C03 		orr	r3, r3, ip
+ARM GAS  /tmp/ccI26Lsx.s 			page 190
+
+
+ 2591              	.LVL243:
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2592              		.loc 1 691 3 is_stmt 1 view .LVU771
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2593              		.loc 1 691 11 is_stmt 0 view .LVU772
+ 2594 004a 43F01103 		orr	r3, r3, #17
+ 2595              	.LVL244:
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2596              		.loc 1 694 3 is_stmt 1 view .LVU773
+ 2597 004e 4560     		str	r5, [r0, #4]
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2598              		.loc 1 697 3 view .LVU774
+ 2599 0050 8460     		str	r4, [r0, #8]
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2600              		.loc 1 700 3 view .LVU775
+ 2601 0052 8261     		str	r2, [r0, #24]
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2602              		.loc 1 703 3 view .LVU776
+ 2603 0054 0362     		str	r3, [r0, #32]
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2604              		.loc 1 706 3 view .LVU777
+ 2605 0056 CB68     		ldr	r3, [r1, #12]
+ 2606              	.LVL245:
+ 2607              	.LBB188:
+ 2608              	.LBI188:
+2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** {
+ 2609              		.loc 2 2461 22 view .LVU778
+ 2610              	.LBB189:
+2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 2611              		.loc 2 2463 3 view .LVU779
+ 2612 0058 8363     		str	r3, [r0, #56]
+ 2613              	.LVL246:
+2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }
+ 2614              		.loc 2 2463 3 is_stmt 0 view .LVU780
+ 2615              	.LBE189:
+ 2616              	.LBE188:
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2617              		.loc 1 708 3 is_stmt 1 view .LVU781
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2618              		.loc 1 709 1 is_stmt 0 view .LVU782
+ 2619 005a 0020     		movs	r0, #0
+ 2620              	.LVL247:
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2621              		.loc 1 709 1 view .LVU783
+ 2622 005c 70BC     		pop	{r4, r5, r6}
+ 2623              	.LCFI26:
+ 2624              		.cfi_restore 6
+ 2625              		.cfi_restore 5
+ 2626              		.cfi_restore 4
+ 2627              		.cfi_def_cfa_offset 0
+ 2628              	.LVL248:
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2629              		.loc 1 709 1 view .LVU784
+ 2630 005e 7047     		bx	lr
+ 2631              	.L117:
+ 2632              		.align	2
+ 2633              	.L116:
+ARM GAS  /tmp/ccI26Lsx.s 			page 191
+
+
+ 2634 0060 88FFFEFF 		.word	-65656
+ 2635 0064 FF03FFFE 		.word	-16841729
+ 2636              		.cfi_endproc
+ 2637              	.LFE388:
+ 2639              		.section	.text.LL_TIM_BDTR_StructInit,"ax",%progbits
+ 2640              		.align	1
+ 2641              		.global	LL_TIM_BDTR_StructInit
+ 2642              		.syntax unified
+ 2643              		.thumb
+ 2644              		.thumb_func
+ 2645              		.fpu fpv5-d16
+ 2647              	LL_TIM_BDTR_StructInit:
+ 2648              	.LVL249:
+ 2649              	.LFB389:
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   /* Set the default configuration */
+ 2650              		.loc 1 719 1 is_stmt 1 view -0
+ 2651              		.cfi_startproc
+ 2652              		@ args = 0, pretend = 0, frame = 0
+ 2653              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2654              		@ link register save eliminated.
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
+ 2655              		.loc 1 721 3 view .LVU786
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
+ 2656              		.loc 1 721 39 is_stmt 0 view .LVU787
+ 2657 0000 0023     		movs	r3, #0
+ 2658 0002 0360     		str	r3, [r0]
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
+ 2659              		.loc 1 722 3 is_stmt 1 view .LVU788
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
+ 2660              		.loc 1 722 39 is_stmt 0 view .LVU789
+ 2661 0004 4360     		str	r3, [r0, #4]
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
+ 2662              		.loc 1 723 3 is_stmt 1 view .LVU790
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
+ 2663              		.loc 1 723 39 is_stmt 0 view .LVU791
+ 2664 0006 8360     		str	r3, [r0, #8]
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
+ 2665              		.loc 1 724 3 is_stmt 1 view .LVU792
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
+ 2666              		.loc 1 724 39 is_stmt 0 view .LVU793
+ 2667 0008 0373     		strb	r3, [r0, #12]
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
+ 2668              		.loc 1 725 3 is_stmt 1 view .LVU794
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
+ 2669              		.loc 1 725 39 is_stmt 0 view .LVU795
+ 2670 000a C381     		strh	r3, [r0, #14]	@ movhi
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
+ 2671              		.loc 1 726 3 is_stmt 1 view .LVU796
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
+ 2672              		.loc 1 726 39 is_stmt 0 view .LVU797
+ 2673 000c 0361     		str	r3, [r0, #16]
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
+ 2674              		.loc 1 727 3 is_stmt 1 view .LVU798
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
+ 2675              		.loc 1 727 39 is_stmt 0 view .LVU799
+ 2676 000e 4361     		str	r3, [r0, #20]
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
+ARM GAS  /tmp/ccI26Lsx.s 			page 192
+
+
+ 2677              		.loc 1 728 3 is_stmt 1 view .LVU800
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
+ 2678              		.loc 1 728 39 is_stmt 0 view .LVU801
+ 2679 0010 8361     		str	r3, [r0, #24]
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
+ 2680              		.loc 1 729 3 is_stmt 1 view .LVU802
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
+ 2681              		.loc 1 729 39 is_stmt 0 view .LVU803
+ 2682 0012 C361     		str	r3, [r0, #28]
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+ 2683              		.loc 1 730 3 is_stmt 1 view .LVU804
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+ 2684              		.loc 1 730 39 is_stmt 0 view .LVU805
+ 2685 0014 0362     		str	r3, [r0, #32]
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2686              		.loc 1 731 3 is_stmt 1 view .LVU806
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2687              		.loc 1 731 39 is_stmt 0 view .LVU807
+ 2688 0016 4362     		str	r3, [r0, #36]
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2689              		.loc 1 732 1 view .LVU808
+ 2690 0018 7047     		bx	lr
+ 2691              		.cfi_endproc
+ 2692              	.LFE389:
+ 2694              		.section	.text.LL_TIM_BDTR_Init,"ax",%progbits
+ 2695              		.align	1
+ 2696              		.global	LL_TIM_BDTR_Init
+ 2697              		.syntax unified
+ 2698              		.thumb
+ 2699              		.thumb_func
+ 2700              		.fpu fpv5-d16
+ 2702              	LL_TIM_BDTR_Init:
+ 2703              	.LVL250:
+ 2704              	.LFB390:
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpbdtr = 0;
+ 2705              		.loc 1 752 1 is_stmt 1 view -0
+ 2706              		.cfi_startproc
+ 2707              		@ args = 0, pretend = 0, frame = 0
+ 2708              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2709              		@ link register save eliminated.
+ 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   uint32_t tmpbdtr = 0;
+ 2710              		.loc 1 752 1 is_stmt 0 view .LVU810
+ 2711 0000 10B4     		push	{r4}
+ 2712              	.LCFI27:
+ 2713              		.cfi_def_cfa_offset 4
+ 2714              		.cfi_offset 4, -4
+ 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2715              		.loc 1 753 3 is_stmt 1 view .LVU811
+ 2716              	.LVL251:
+ 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+ 2717              		.loc 1 756 3 view .LVU812
+ 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+ 2718              		.loc 1 757 3 view .LVU813
+ 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+ 2719              		.loc 1 758 3 view .LVU814
+ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+ 2720              		.loc 1 759 3 view .LVU815
+ARM GAS  /tmp/ccI26Lsx.s 			page 193
+
+
+ 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+ 2721              		.loc 1 760 3 view .LVU816
+ 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+ 2722              		.loc 1 761 3 view .LVU817
+ 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ 2723              		.loc 1 762 3 view .LVU818
+ 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2724              		.loc 1 763 3 view .LVU819
+ 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+ 2725              		.loc 1 769 3 view .LVU820
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+ 2726              		.loc 1 770 3 view .LVU821
+ 2727 0002 0B7B     		ldrb	r3, [r1, #12]	@ zero_extendqisi2
+ 2728              	.LVL252:
+ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+ 2729              		.loc 1 770 3 is_stmt 0 view .LVU822
+ 2730 0004 8A68     		ldr	r2, [r1, #8]
+ 2731 0006 1343     		orrs	r3, r3, r2
+ 2732              	.LVL253:
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+ 2733              		.loc 1 771 3 is_stmt 1 view .LVU823
+ 2734 0008 23F48063 		bic	r3, r3, #1024
+ 2735              	.LVL254:
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+ 2736              		.loc 1 771 3 is_stmt 0 view .LVU824
+ 2737 000c 4A68     		ldr	r2, [r1, #4]
+ 2738              	.LVL255:
+ 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+ 2739              		.loc 1 771 3 view .LVU825
+ 2740 000e 1343     		orrs	r3, r3, r2
+ 2741              	.LVL256:
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+ 2742              		.loc 1 772 3 is_stmt 1 view .LVU826
+ 2743 0010 23F40063 		bic	r3, r3, #2048
+ 2744              	.LVL257:
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+ 2745              		.loc 1 772 3 is_stmt 0 view .LVU827
+ 2746 0014 0A68     		ldr	r2, [r1]
+ 2747              	.LVL258:
+ 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+ 2748              		.loc 1 772 3 view .LVU828
+ 2749 0016 1343     		orrs	r3, r3, r2
+ 2750              	.LVL259:
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+ 2751              		.loc 1 773 3 is_stmt 1 view .LVU829
+ 2752 0018 23F48053 		bic	r3, r3, #4096
+ 2753              	.LVL260:
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+ 2754              		.loc 1 773 3 is_stmt 0 view .LVU830
+ 2755 001c CA89     		ldrh	r2, [r1, #14]
+ 2756              	.LVL261:
+ 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+ 2757              		.loc 1 773 3 view .LVU831
+ 2758 001e 1343     		orrs	r3, r3, r2
+ 2759              	.LVL262:
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ 2760              		.loc 1 774 3 is_stmt 1 view .LVU832
+ARM GAS  /tmp/ccI26Lsx.s 			page 194
+
+
+ 2761 0020 23F40053 		bic	r3, r3, #8192
+ 2762              	.LVL263:
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ 2763              		.loc 1 774 3 is_stmt 0 view .LVU833
+ 2764 0024 0A69     		ldr	r2, [r1, #16]
+ 2765              	.LVL264:
+ 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ 2766              		.loc 1 774 3 view .LVU834
+ 2767 0026 1343     		orrs	r3, r3, r2
+ 2768              	.LVL265:
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ 2769              		.loc 1 775 3 is_stmt 1 view .LVU835
+ 2770 0028 23F48043 		bic	r3, r3, #16384
+ 2771              	.LVL266:
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ 2772              		.loc 1 775 3 is_stmt 0 view .LVU836
+ 2773 002c 4A6A     		ldr	r2, [r1, #36]
+ 2774              	.LVL267:
+ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ 2775              		.loc 1 775 3 view .LVU837
+ 2776 002e 1343     		orrs	r3, r3, r2
+ 2777              	.LVL268:
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2778              		.loc 1 776 3 is_stmt 1 view .LVU838
+ 2779 0030 23F47023 		bic	r3, r3, #983040
+ 2780              	.LVL269:
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2781              		.loc 1 776 3 is_stmt 0 view .LVU839
+ 2782 0034 4A69     		ldr	r2, [r1, #20]
+ 2783              	.LVL270:
+ 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2784              		.loc 1 776 3 view .LVU840
+ 2785 0036 1343     		orrs	r3, r3, r2
+ 2786              	.LVL271:
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2787              		.loc 1 778 3 is_stmt 1 view .LVU841
+ 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   {
+ 2788              		.loc 1 778 6 is_stmt 0 view .LVU842
+ 2789 0038 0B4C     		ldr	r4, .L122
+ 2790 003a 0C4A     		ldr	r2, .L122+4
+ 2791 003c 9042     		cmp	r0, r2
+ 2792 003e 18BF     		it	ne
+ 2793 0040 A042     		cmpne	r0, r4
+ 2794 0042 0BD1     		bne	.L120
+ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
+ 2795              		.loc 1 780 5 is_stmt 1 view .LVU843
+ 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+ 2796              		.loc 1 781 5 view .LVU844
+ 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2797              		.loc 1 782 5 view .LVU845
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
+ 2798              		.loc 1 785 5 view .LVU846
+ 2799 0044 23F47003 		bic	r3, r3, #15728640
+ 2800              	.LVL272:
+ 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
+ 2801              		.loc 1 785 5 is_stmt 0 view .LVU847
+ 2802 0048 0A6A     		ldr	r2, [r1, #32]
+ARM GAS  /tmp/ccI26Lsx.s 			page 195
+
+
+ 2803 004a 1343     		orrs	r3, r3, r2
+ 2804              	.LVL273:
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+ 2805              		.loc 1 786 5 is_stmt 1 view .LVU848
+ 2806 004c 23F08073 		bic	r3, r3, #16777216
+ 2807              	.LVL274:
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+ 2808              		.loc 1 786 5 is_stmt 0 view .LVU849
+ 2809 0050 8A69     		ldr	r2, [r1, #24]
+ 2810              	.LVL275:
+ 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+ 2811              		.loc 1 786 5 view .LVU850
+ 2812 0052 1343     		orrs	r3, r3, r2
+ 2813              	.LVL276:
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 2814              		.loc 1 787 5 is_stmt 1 view .LVU851
+ 2815 0054 23F00073 		bic	r3, r3, #33554432
+ 2816              	.LVL277:
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 2817              		.loc 1 787 5 is_stmt 0 view .LVU852
+ 2818 0058 CA69     		ldr	r2, [r1, #28]
+ 2819              	.LVL278:
+ 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c ****   }
+ 2820              		.loc 1 787 5 view .LVU853
+ 2821 005a 1343     		orrs	r3, r3, r2
+ 2822              	.LVL279:
+ 2823              	.L120:
+ 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** 
+ 2824              		.loc 1 791 3 is_stmt 1 view .LVU854
+ 2825 005c 4364     		str	r3, [r0, #68]
+ 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** }
+ 2826              		.loc 1 793 3 view .LVU855
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 2827              		.loc 1 794 1 is_stmt 0 view .LVU856
+ 2828 005e 0020     		movs	r0, #0
+ 2829              	.LVL280:
+ 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /**
+ 2830              		.loc 1 794 1 view .LVU857
+ 2831 0060 5DF8044B 		ldr	r4, [sp], #4
+ 2832              	.LCFI28:
+ 2833              		.cfi_restore 4
+ 2834              		.cfi_def_cfa_offset 0
+ 2835 0064 7047     		bx	lr
+ 2836              	.L123:
+ 2837 0066 00BF     		.align	2
+ 2838              	.L122:
+ 2839 0068 00000140 		.word	1073807360
+ 2840 006c 00040140 		.word	1073808384
+ 2841              		.cfi_endproc
+ 2842              	.LFE390:
+ 2844              		.text
+ 2845              	.Letext0:
+ 2846              		.file 4 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 2847              		.file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 2848              		.file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ARM GAS  /tmp/ccI26Lsx.s 			page 196
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_ll_tim.c
+     /tmp/ccI26Lsx.s:17     .text.OC1Config:0000000000000000 $t
+     /tmp/ccI26Lsx.s:24     .text.OC1Config:0000000000000000 OC1Config
+     /tmp/ccI26Lsx.s:165    .text.OC1Config:000000000000006c $d
+     /tmp/ccI26Lsx.s:172    .text.OC2Config:0000000000000000 $t
+     /tmp/ccI26Lsx.s:178    .text.OC2Config:0000000000000000 OC2Config
+     /tmp/ccI26Lsx.s:319    .text.OC2Config:0000000000000074 $d
+     /tmp/ccI26Lsx.s:326    .text.OC3Config:0000000000000000 $t
+     /tmp/ccI26Lsx.s:332    .text.OC3Config:0000000000000000 OC3Config
+     /tmp/ccI26Lsx.s:473    .text.OC3Config:0000000000000070 $d
+     /tmp/ccI26Lsx.s:480    .text.OC4Config:0000000000000000 $t
+     /tmp/ccI26Lsx.s:486    .text.OC4Config:0000000000000000 OC4Config
+     /tmp/ccI26Lsx.s:601    .text.OC4Config:0000000000000054 $d
+     /tmp/ccI26Lsx.s:608    .text.OC5Config:0000000000000000 $t
+     /tmp/ccI26Lsx.s:614    .text.OC5Config:0000000000000000 OC5Config
+     /tmp/ccI26Lsx.s:722    .text.OC5Config:0000000000000054 $d
+     /tmp/ccI26Lsx.s:729    .text.OC6Config:0000000000000000 $t
+     /tmp/ccI26Lsx.s:735    .text.OC6Config:0000000000000000 OC6Config
+     /tmp/ccI26Lsx.s:840    .text.OC6Config:0000000000000054 $d
+     /tmp/ccI26Lsx.s:847    .text.IC1Config:0000000000000000 $t
+     /tmp/ccI26Lsx.s:853    .text.IC1Config:0000000000000000 IC1Config
+     /tmp/ccI26Lsx.s:907    .text.IC2Config:0000000000000000 $t
+     /tmp/ccI26Lsx.s:913    .text.IC2Config:0000000000000000 IC2Config
+     /tmp/ccI26Lsx.s:967    .text.IC3Config:0000000000000000 $t
+     /tmp/ccI26Lsx.s:973    .text.IC3Config:0000000000000000 IC3Config
+     /tmp/ccI26Lsx.s:1027   .text.IC4Config:0000000000000000 $t
+     /tmp/ccI26Lsx.s:1033   .text.IC4Config:0000000000000000 IC4Config
+     /tmp/ccI26Lsx.s:1087   .text.LL_TIM_DeInit:0000000000000000 $t
+     /tmp/ccI26Lsx.s:1094   .text.LL_TIM_DeInit:0000000000000000 LL_TIM_DeInit
+     /tmp/ccI26Lsx.s:1698   .text.LL_TIM_DeInit:00000000000001b0 $d
+     /tmp/ccI26Lsx.s:1718   .text.LL_TIM_StructInit:0000000000000000 $t
+     /tmp/ccI26Lsx.s:1725   .text.LL_TIM_StructInit:0000000000000000 LL_TIM_StructInit
+     /tmp/ccI26Lsx.s:1756   .text.LL_TIM_Init:0000000000000000 $t
+     /tmp/ccI26Lsx.s:1763   .text.LL_TIM_Init:0000000000000000 LL_TIM_Init
+     /tmp/ccI26Lsx.s:1967   .text.LL_TIM_Init:00000000000000f4 $d
+     /tmp/ccI26Lsx.s:1978   .text.LL_TIM_OC_StructInit:0000000000000000 $t
+     /tmp/ccI26Lsx.s:1985   .text.LL_TIM_OC_StructInit:0000000000000000 LL_TIM_OC_StructInit
+     /tmp/ccI26Lsx.s:2024   .text.LL_TIM_OC_Init:0000000000000000 $t
+     /tmp/ccI26Lsx.s:2031   .text.LL_TIM_OC_Init:0000000000000000 LL_TIM_OC_Init
+     /tmp/ccI26Lsx.s:2130   .text.LL_TIM_IC_StructInit:0000000000000000 $t
+     /tmp/ccI26Lsx.s:2137   .text.LL_TIM_IC_StructInit:0000000000000000 LL_TIM_IC_StructInit
+     /tmp/ccI26Lsx.s:2165   .text.LL_TIM_IC_Init:0000000000000000 $t
+     /tmp/ccI26Lsx.s:2172   .text.LL_TIM_IC_Init:0000000000000000 LL_TIM_IC_Init
+     /tmp/ccI26Lsx.s:2250   .text.LL_TIM_ENCODER_StructInit:0000000000000000 $t
+     /tmp/ccI26Lsx.s:2257   .text.LL_TIM_ENCODER_StructInit:0000000000000000 LL_TIM_ENCODER_StructInit
+     /tmp/ccI26Lsx.s:2301   .text.LL_TIM_ENCODER_Init:0000000000000000 $t
+     /tmp/ccI26Lsx.s:2308   .text.LL_TIM_ENCODER_Init:0000000000000000 LL_TIM_ENCODER_Init
+     /tmp/ccI26Lsx.s:2448   .text.LL_TIM_ENCODER_Init:000000000000005c $d
+     /tmp/ccI26Lsx.s:2453   .text.LL_TIM_HALLSENSOR_StructInit:0000000000000000 $t
+     /tmp/ccI26Lsx.s:2460   .text.LL_TIM_HALLSENSOR_StructInit:0000000000000000 LL_TIM_HALLSENSOR_StructInit
+     /tmp/ccI26Lsx.s:2487   .text.LL_TIM_HALLSENSOR_Init:0000000000000000 $t
+     /tmp/ccI26Lsx.s:2494   .text.LL_TIM_HALLSENSOR_Init:0000000000000000 LL_TIM_HALLSENSOR_Init
+     /tmp/ccI26Lsx.s:2634   .text.LL_TIM_HALLSENSOR_Init:0000000000000060 $d
+     /tmp/ccI26Lsx.s:2640   .text.LL_TIM_BDTR_StructInit:0000000000000000 $t
+     /tmp/ccI26Lsx.s:2647   .text.LL_TIM_BDTR_StructInit:0000000000000000 LL_TIM_BDTR_StructInit
+     /tmp/ccI26Lsx.s:2695   .text.LL_TIM_BDTR_Init:0000000000000000 $t
+ARM GAS  /tmp/ccI26Lsx.s 			page 197
+
+
+     /tmp/ccI26Lsx.s:2702   .text.LL_TIM_BDTR_Init:0000000000000000 LL_TIM_BDTR_Init
+     /tmp/ccI26Lsx.s:2839   .text.LL_TIM_BDTR_Init:0000000000000068 $d
+
+NO UNDEFINED SYMBOLS
diff --git a/build/stm32f7xx_ll_tim.o b/build/stm32f7xx_ll_tim.o
new file mode 100644
index 0000000..23cffa6
Binary files /dev/null and b/build/stm32f7xx_ll_tim.o differ
diff --git a/build/stm32f7xx_ll_usart.d b/build/stm32f7xx_ll_usart.d
new file mode 100644
index 0000000..65789a2
--- /dev/null
+++ b/build/stm32f7xx_ll_usart.d
@@ -0,0 +1,70 @@
+build/stm32f7xx_ll_usart.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
diff --git a/build/stm32f7xx_ll_usart.lst b/build/stm32f7xx_ll_usart.lst
new file mode 100644
index 0000000..69839ab
--- /dev/null
+++ b/build/stm32f7xx_ll_usart.lst
@@ -0,0 +1,5259 @@
+ARM GAS  /tmp/cc1GpNf6.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_ll_usart.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.LL_USART_DeInit,"ax",%progbits
+  17              		.align	1
+  18              		.global	LL_USART_DeInit
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	LL_USART_DeInit:
+  26              	.LVL0:
+  27              	.LFB542:
+  28              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @file    stm32f7xx_ll_usart.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @brief   USART LL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #if defined(USE_FULL_LL_DRIVER)
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Includes ------------------------------------------------------------------*/
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #include "stm32f7xx_ll_usart.h"
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #include "stm32f7xx_ll_rcc.h"
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #include "stm32f7xx_ll_bus.h"
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #ifdef USE_FULL_ASSERT
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #include "stm32_assert.h"
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #else
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define assert_param(expr) ((void)0U)
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #endif /* USE_FULL_ASSERT */
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup STM32F7xx_LL_Driver
+ARM GAS  /tmp/cc1GpNf6.s 			page 2
+
+
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****  || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8)
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup USART_LL
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @{
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Private types -------------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Private variables ---------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Private constants ---------------------------------------------------------*/
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup USART_LL_Private_Constants
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @{
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Definition of default baudrate value used for USART initialisation */
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define USART_DEFAULT_BAUDRATE          (9600U)
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /**
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @}
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Private macros ------------------------------------------------------------*/
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup USART_LL_Private_Macros
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @{
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****  *              divided by the smallest oversampling used on the USART (i.e. 8)    */
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U)
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                           || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                           || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                           || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                        || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                        || ((__VALUE__) == LL_USART_PARITY_ODD))
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                           || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                           || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                              || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                                  || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                            || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+ARM GAS  /tmp/cc1GpNf6.s 			page 3
+
+
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                               || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                             || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                          || ((__VALUE__) == LL_USART_STOPBITS_1) \
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                          || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                          || ((__VALUE__) == LL_USART_STOPBITS_2))
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                           || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                           || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                           || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /**
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @}
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Private function prototypes -----------------------------------------------*/
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Exported functions --------------------------------------------------------*/
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup USART_LL_Exported_Functions
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @{
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup USART_LL_EF_Init
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @{
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /**
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @brief  De-initialize USART registers (Registers restored to their default values).
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @param  USARTx USART Instance
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @retval An ErrorStatus enumeration value:
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *          - SUCCESS: USART registers are de-initialized
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *          - ERROR: USART registers are not de-initialized
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** {
+  29              		.loc 1 128 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		@ link register save eliminated.
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   ErrorStatus status = SUCCESS;
+  34              		.loc 1 129 3 view .LVU1
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   /* Check the parameters */
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   assert_param(IS_UART_INSTANCE(USARTx));
+  35              		.loc 1 132 3 view .LVU2
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   if (USARTx == USART1)
+  36              		.loc 1 134 3 view .LVU3
+  37              		.loc 1 134 6 is_stmt 0 view .LVU4
+  38 0000 3C4B     		ldr	r3, .L19
+ARM GAS  /tmp/cc1GpNf6.s 			page 4
+
+
+  39 0002 9842     		cmp	r0, r3
+  40 0004 16D0     		beq	.L11
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Force reset of USART clock */
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Release reset of USART clock */
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   else if (USARTx == USART2)
+  41              		.loc 1 142 8 is_stmt 1 view .LVU5
+  42              		.loc 1 142 11 is_stmt 0 view .LVU6
+  43 0006 3C4B     		ldr	r3, .L19+4
+  44 0008 9842     		cmp	r0, r3
+  45 000a 1FD0     		beq	.L12
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Force reset of USART clock */
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Release reset of USART clock */
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   else if (USARTx == USART3)
+  46              		.loc 1 150 8 is_stmt 1 view .LVU7
+  47              		.loc 1 150 11 is_stmt 0 view .LVU8
+  48 000c 3B4B     		ldr	r3, .L19+8
+  49 000e 9842     		cmp	r0, r3
+  50 0010 28D0     		beq	.L13
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Force reset of USART clock */
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Release reset of USART clock */
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   else if (USARTx == UART4)
+  51              		.loc 1 158 8 is_stmt 1 view .LVU9
+  52              		.loc 1 158 11 is_stmt 0 view .LVU10
+  53 0012 3B4B     		ldr	r3, .L19+12
+  54 0014 9842     		cmp	r0, r3
+  55 0016 31D0     		beq	.L14
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Force reset of UART clock */
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Release reset of UART clock */
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   else if (USARTx == UART5)
+  56              		.loc 1 166 8 is_stmt 1 view .LVU11
+  57              		.loc 1 166 11 is_stmt 0 view .LVU12
+  58 0018 3A4B     		ldr	r3, .L19+16
+  59 001a 9842     		cmp	r0, r3
+  60 001c 3AD0     		beq	.L15
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Force reset of UART clock */
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+ARM GAS  /tmp/cc1GpNf6.s 			page 5
+
+
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Release reset of UART clock */
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   else if (USARTx == USART6)
+  61              		.loc 1 174 8 is_stmt 1 view .LVU13
+  62              		.loc 1 174 11 is_stmt 0 view .LVU14
+  63 001e 3A4B     		ldr	r3, .L19+20
+  64 0020 9842     		cmp	r0, r3
+  65 0022 43D0     		beq	.L16
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Force reset of USART clock */
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Release reset of USART clock */
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   else if (USARTx == UART7)
+  66              		.loc 1 182 8 is_stmt 1 view .LVU15
+  67              		.loc 1 182 11 is_stmt 0 view .LVU16
+  68 0024 394B     		ldr	r3, .L19+24
+  69 0026 9842     		cmp	r0, r3
+  70 0028 4CD0     		beq	.L17
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Force reset of UART clock */
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Release reset of UART clock */
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   else if (USARTx == UART8)
+  71              		.loc 1 190 8 is_stmt 1 view .LVU17
+  72              		.loc 1 190 11 is_stmt 0 view .LVU18
+  73 002a 394B     		ldr	r3, .L19+28
+  74 002c 9842     		cmp	r0, r3
+  75 002e 55D0     		beq	.L18
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Force reset of UART clock */
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Release reset of UART clock */
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   else
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     status = ERROR;
+  76              		.loc 1 200 12 view .LVU19
+  77 0030 0120     		movs	r0, #1
+  78              	.LVL1:
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   return (status);
+  79              		.loc 1 203 3 is_stmt 1 view .LVU20
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** }
+  80              		.loc 1 204 1 is_stmt 0 view .LVU21
+  81 0032 7047     		bx	lr
+  82              	.LVL2:
+ARM GAS  /tmp/cc1GpNf6.s 			page 6
+
+
+  83              	.L11:
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+  84              		.loc 1 137 5 is_stmt 1 view .LVU22
+  85              	.LBB44:
+  86              	.LBI44:
+  87              		.file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @file    stm32f7xx_ll_bus.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief   Header file of BUS LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @verbatim
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****                       ##### RCC Limitations #####
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ==============================================================================
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       A delay between an RCC peripheral clock enable and the effective peripheral 
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       enabling should be taken into account in order to manage the peripheral read/write 
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       from/to registers.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (+) This delay depends on the peripheral mapping.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****         (++) AHB & APB peripherals, 1 dummy read is necessary
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****     [..]  
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       Workarounds:
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   @endverbatim
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @attention
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * Copyright (c) 2017 STMicroelectronics.
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * All rights reserved.
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * This software is licensed under terms that can be found in the LICENSE file in
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * the root directory of this software component.
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   ******************************************************************************
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" {
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h"
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC)
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ARM GAS  /tmp/cc1GpNf6.s 			page 7
+
+
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ)
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK)
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM         RCC_AHB1ENR_DTCMRAMEN
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D)
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH)
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI             RCC_AHB1LPENR_AXILPEN
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ARM GAS  /tmp/cc1GpNf6.s 			page 8
+
+
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI)
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG)
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG           RCC_AHB2ENR_JPEGEN
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) 
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES)
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH)
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX)
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
+ARM GAS  /tmp/cc1GpNf6.s 			page 9
+
+
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4)
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4           RCC_APB1ENR_I2C4EN
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2)
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3)
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC)
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN)
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCEN
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1       RCC_APB2ENR_SDMMC1EN
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2)
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2       RCC_APB2ENR_SDMMC2EN
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6)
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC)
+ARM GAS  /tmp/cc1GpNf6.s 			page 10
+
+
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI)
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0)
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS)
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO         RCC_APB2ENR_MDIOEN
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC)
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC      RCC_APB2ENR_OTGPHYCEN
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB1 peripherals clock.
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\n
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\n
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\n
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\n
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\n
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\n
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\n
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\n
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\n
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\n
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\n
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\n
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_EnableClock\n
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\n
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\n
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\n
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\n
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\n
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\n
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\n
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\n
+ARM GAS  /tmp/cc1GpNf6.s 			page 11
+
+
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1ENR, Periphs);
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB1 peripheral clock is enabled or not
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\n
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\n
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\n
+ARM GAS  /tmp/cc1GpNf6.s 			page 12
+
+
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\n
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\n
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\n
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\n
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_IsEnabledClock
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB1 peripherals clock.
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\n
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\n
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\n
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\n
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\n
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\n
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\n
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\n
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\n
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\n
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\n
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\n
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DTCMRAMEN          LL_AHB1_GRP1_DisableClock\n
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\n
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\n
+ARM GAS  /tmp/cc1GpNf6.s 			page 13
+
+
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\n
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\n
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\n
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\n
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\n
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\n
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1ENR      OTGHSULPIENDEN     LL_AHB1_GRP1_DisableClock
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1ENR, Periphs);
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB1 peripherals reset.
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\n
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\n
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\n
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\n
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\n
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\n
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\n
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\n
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\n
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\n
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\n
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\n
+ARM GAS  /tmp/cc1GpNf6.s 			page 14
+
+
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\n
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1RSTR, Periphs);
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB1 peripherals reset.
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\n
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\n
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\n
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\n
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\n
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ARM GAS  /tmp/cc1GpNf6.s 			page 15
+
+
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB1 peripheral clocks in low-power mode
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    AXILPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DTCMRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_EnableClockLowPower\n
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_EnableClockLowPower\n
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockLowPower
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ARM GAS  /tmp/cc1GpNf6.s 			page 16
+
+
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_AXI
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB1LPENR, Periphs);
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB1 peripheral clocks in low-power mode
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    AXILPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DTCMRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_DisableClockLowPower\n
+ARM GAS  /tmp/cc1GpNf6.s 			page 17
+
+
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_DisableClockLowPower\n
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockLowPower
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_AXI
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB1LPENR, Periphs);
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB2 peripherals clock.
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_EnableClock\n
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_EnableClock\n
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_EnableClock\n
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_EnableClock\n
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_EnableClock\n
+ARM GAS  /tmp/cc1GpNf6.s 			page 18
+
+
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_EnableClock\n
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_EnableClock
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2ENR, Periphs);
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB2 peripheral clock is enabled or not
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_IsEnabledClock\n
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_IsEnabledClock\n
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_IsEnabledClock\n
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_IsEnabledClock
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB2 peripherals clock.
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_DisableClock\n
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      JPEGEN       LL_AHB2_GRP1_DisableClock\n
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_DisableClock\n
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      AESEN        LL_AHB2_GRP1_DisableClock\n
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      HASHEN       LL_AHB2_GRP1_DisableClock\n
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      RNGEN        LL_AHB2_GRP1_DisableClock\n
+ARM GAS  /tmp/cc1GpNf6.s 			page 19
+
+
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_DisableClock
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2ENR, Periphs);
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB2 peripherals reset.
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ForceReset\n
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     JPEGRST      LL_AHB2_GRP1_ForceReset\n
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ForceReset\n
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ForceReset\n
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ForceReset\n
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ForceReset\n
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ForceReset
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2RSTR, Periphs);
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB2 peripherals reset.
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ReleaseReset\n
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     JPEGRST      LL_AHB2_GRP1_ReleaseReset\n
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ReleaseReset\n
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ReleaseReset\n
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ReleaseReset\n
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ReleaseReset\n
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ReleaseReset
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ARM GAS  /tmp/cc1GpNf6.s 			page 20
+
+
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB2 peripheral clocks in low-power mode
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    JPEGLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_EnableClockLowPower
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB2LPENR, Periphs);
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB2 peripheral clocks in low-power mode
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    JPEGLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_DisableClockLowPower
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
+ARM GAS  /tmp/cc1GpNf6.s 			page 21
+
+
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB2LPENR, Periphs);
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB3 peripherals clock.
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3ENR, Periphs);
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if AHB3 peripheral clock is enabled or not
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ARM GAS  /tmp/cc1GpNf6.s 			page 22
+
+
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB3 peripherals clock.
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3ENR, Periphs);
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force AHB3 peripherals reset.
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3RSTR, Periphs);
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release AHB3 peripherals reset.
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable AHB3 peripheral clocks in low-power mode
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockLowPower\n
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockLowPower
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ARM GAS  /tmp/cc1GpNf6.s 			page 23
+
+
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->AHB3LPENR, Periphs);
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable AHB3 peripheral clocks in low-power mode
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockLowPower\n
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockLowPower
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->AHB3LPENR, Periphs);
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB1 peripherals clock.
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\n
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\n
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_EnableClock\n
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_EnableClock\n
+ARM GAS  /tmp/cc1GpNf6.s 			page 24
+
+
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_EnableClock\n
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_EnableClock\n
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_EnableClock\n
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_EnableClock\n
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_EnableClock\n
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_EnableClock\n
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\n
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\n
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_EnableClock\n
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_EnableClock\n
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_EnableClock
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1ENR, Periphs);
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+ARM GAS  /tmp/cc1GpNf6.s 			page 25
+
+
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if APB1 peripheral clock is enabled or not
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_IsEnabledClock\n
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_IsEnabledClock\n
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_IsEnabledClock\n
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_IsEnabledClock\n
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\n
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\n
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_IsEnabledClock\n
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_IsEnabledClock
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ARM GAS  /tmp/cc1GpNf6.s 			page 26
+
+
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable APB1 peripherals clock.
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\n
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\n
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     USART3EN      LL_APB1_GRP1_DisableClock\n
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART4EN       LL_APB1_GRP1_DisableClock\n
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART5EN       LL_APB1_GRP1_DisableClock\n
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     I2C4EN        LL_APB1_GRP1_DisableClock\n
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN1EN        LL_APB1_GRP1_DisableClock\n
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN2EN        LL_APB1_GRP1_DisableClock\n
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CAN3EN        LL_APB1_GRP1_DisableClock\n
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     CECEN         LL_APB1_GRP1_DisableClock\n
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\n
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\n
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART7EN       LL_APB1_GRP1_DisableClock\n
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     UART8EN       LL_APB1_GRP1_DisableClock\n
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1ENR     RTCEN         LL_APB1_GRP1_DisableClock
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+ARM GAS  /tmp/cc1GpNf6.s 			page 27
+
+
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1ENR, Periphs);
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force APB1 peripherals reset.
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\n
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\n
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ForceReset\n
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ForceReset\n
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\n
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\n
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ForceReset\n
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ForceReset\n
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ForceReset\n
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset\n
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\n
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\n
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ForceReset\n
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ForceReset\n
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\n
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART3RST      LL_APB1_GRP1_ForceReset\n
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART4RST       LL_APB1_GRP1_ForceReset\n
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART5RST       LL_APB1_GRP1_ForceReset\n
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\n
+ARM GAS  /tmp/cc1GpNf6.s 			page 28
+
+
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\n
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\n
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C4RST        LL_APB1_GRP1_ForceReset\n
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ForceReset\n
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ForceReset\n
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ForceReset\n
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CECRST         LL_APB1_GRP1_ForceReset\n
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\n
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\n
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART7RST       LL_APB1_GRP1_ForceReset\n
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART8RST       LL_APB1_GRP1_ForceReset
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1RSTR, Periphs);
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release APB1 peripherals reset.
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ReleaseReset\n
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ReleaseReset\n
+ARM GAS  /tmp/cc1GpNf6.s 			page 29
+
+
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ReleaseReset\n
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ReleaseReset\n
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ReleaseReset\n
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset\n
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\n
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ReleaseReset\n
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ReleaseReset\n
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\n
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     USART3RST      LL_APB1_GRP1_ReleaseReset\n
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART4RST       LL_APB1_GRP1_ReleaseReset\n
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART5RST       LL_APB1_GRP1_ReleaseReset\n
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     I2C4RST        LL_APB1_GRP1_ReleaseReset\n
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ReleaseReset\n
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ReleaseReset\n
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ReleaseReset\n
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     CECRST         LL_APB1_GRP1_ReleaseReset\n
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\n
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\n
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART7RST       LL_APB1_GRP1_ReleaseReset\n
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1RSTR     UART8RST       LL_APB1_GRP1_ReleaseReset
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+ARM GAS  /tmp/cc1GpNf6.s 			page 30
+
+
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1RSTR, Periphs);
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB1 peripheral clocks in low-power mode
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_EnableClockLowPower\n
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CECLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     DACLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     RTCLPEN         LL_APB1_GRP1_EnableClockLowPower
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+ARM GAS  /tmp/cc1GpNf6.s 			page 31
+
+
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB1LPENR, Periphs);
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable APB1 peripheral clocks in low-power mode
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_DisableClockLowPower\n
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     I2C4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+ARM GAS  /tmp/cc1GpNf6.s 			page 32
+
+
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     CECLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     DACLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB1LPENR     RTCLPEN         LL_APB1_GRP1_DisableClockLowPower
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB1LPENR, Periphs);
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @}
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @{
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   */
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Enable APB2 peripherals clock.
+ARM GAS  /tmp/cc1GpNf6.s 			page 33
+
+
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_EnableClock\n
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM8EN        LL_APB2_GRP1_EnableClock\n
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART1EN      LL_APB2_GRP1_EnableClock\n
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART6EN      LL_APB2_GRP1_EnableClock\n
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC1EN        LL_APB2_GRP1_EnableClock\n
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC2EN        LL_APB2_GRP1_EnableClock\n
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC3EN        LL_APB2_GRP1_EnableClock\n
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_EnableClock\n
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_EnableClock\n
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI1EN        LL_APB2_GRP1_EnableClock\n
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI4EN        LL_APB2_GRP1_EnableClock\n
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_EnableClock\n
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM9EN        LL_APB2_GRP1_EnableClock\n
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM10EN       LL_APB2_GRP1_EnableClock\n
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM11EN       LL_APB2_GRP1_EnableClock\n
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI5EN        LL_APB2_GRP1_EnableClock\n
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI6EN        LL_APB2_GRP1_EnableClock\n
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI1EN        LL_APB2_GRP1_EnableClock\n
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI2EN        LL_APB2_GRP1_EnableClock\n
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     LTDCEN        LL_APB2_GRP1_EnableClock\n
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DSIEN         LL_APB2_GRP1_EnableClock\n
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_EnableClock\n
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     MDIOEN        LL_APB2_GRP1_EnableClock\n
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_EnableClock
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   __IO uint32_t tmpreg;
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB2ENR, Periphs);
+ARM GAS  /tmp/cc1GpNf6.s 			page 34
+
+
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   /* Delay after an RCC peripheral clock enabling */
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   (void)tmpreg;
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Check if APB2 peripheral clock is enabled or not
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART6EN      LL_APB2_GRP1_IsEnabledClock\n
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC1EN        LL_APB2_GRP1_IsEnabledClock\n
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC2EN        LL_APB2_GRP1_IsEnabledClock\n
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC3EN        LL_APB2_GRP1_IsEnabledClock\n
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_IsEnabledClock\n
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_IsEnabledClock\n
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM9EN        LL_APB2_GRP1_IsEnabledClock\n
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM10EN       LL_APB2_GRP1_IsEnabledClock\n
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM11EN       LL_APB2_GRP1_IsEnabledClock\n
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI6EN        LL_APB2_GRP1_IsEnabledClock\n
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     LTDCEN        LL_APB2_GRP1_IsEnabledClock\n
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DSIEN         LL_APB2_GRP1_IsEnabledClock\n
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     MDIOEN        LL_APB2_GRP1_IsEnabledClock\n
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_IsEnabledClock
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+ARM GAS  /tmp/cc1GpNf6.s 			page 35
+
+
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval State of Periphs (1 or 0).
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Disable APB2 peripherals clock.
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_DisableClock\n
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM8EN        LL_APB2_GRP1_DisableClock\n
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART1EN      LL_APB2_GRP1_DisableClock\n
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     USART6EN      LL_APB2_GRP1_DisableClock\n
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC1EN        LL_APB2_GRP1_DisableClock\n
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC2EN        LL_APB2_GRP1_DisableClock\n
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     ADC3EN        LL_APB2_GRP1_DisableClock\n
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC1EN      LL_APB2_GRP1_DisableClock\n
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SDMMC2EN      LL_APB2_GRP1_DisableClock\n
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI1EN        LL_APB2_GRP1_DisableClock\n
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI4EN        LL_APB2_GRP1_DisableClock\n
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_DisableClock\n
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM9EN        LL_APB2_GRP1_DisableClock\n
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM10EN       LL_APB2_GRP1_DisableClock\n
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     TIM11EN       LL_APB2_GRP1_DisableClock\n
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI5EN        LL_APB2_GRP1_DisableClock\n
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SPI6EN        LL_APB2_GRP1_DisableClock\n
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI1EN        LL_APB2_GRP1_DisableClock\n
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     SAI2EN        LL_APB2_GRP1_DisableClock\n
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     LTDCEN        LL_APB2_GRP1_DisableClock\n
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DSIEN         LL_APB2_GRP1_DisableClock\n
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_DisableClock\n
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     MDIOEN        LL_APB2_GRP1_DisableClock\n
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2ENR     OTGPHYCEN     LL_APB2_GRP1_DisableClock
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ARM GAS  /tmp/cc1GpNf6.s 			page 36
+
+
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB2ENR, Periphs);
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Force APB2 peripherals reset.
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ForceReset\n
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ForceReset\n
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART1RST      LL_APB2_GRP1_ForceReset\n
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART6RST      LL_APB2_GRP1_ForceReset\n
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     ADCRST         LL_APB2_GRP1_ForceReset\n
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC1RST      LL_APB2_GRP1_ForceReset\n
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC2RST      LL_APB2_GRP1_ForceReset\n
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ForceReset\n
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ForceReset\n
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ForceReset\n
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ForceReset\n
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ForceReset\n
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ForceReset\n
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ForceReset\n
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ForceReset\n
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ForceReset\n
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ForceReset\n
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ForceReset\n
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DSIRST         LL_APB2_GRP1_ForceReset\n
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ForceReset\n
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     MDIORST        LL_APB2_GRP1_ForceReset\n
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     OTGPHYCRST     LL_APB2_GRP1_ForceReset
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ARM GAS  /tmp/cc1GpNf6.s 			page 37
+
+
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+  88              		.loc 2 1768 22 view .LVU23
+  89              	.LBB45:
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   SET_BIT(RCC->APB2RSTR, Periphs);
+  90              		.loc 2 1770 3 view .LVU24
+  91 0034 03F59433 		add	r3, r3, #75776
+  92 0038 5A6A     		ldr	r2, [r3, #36]
+  93 003a 42F01002 		orr	r2, r2, #16
+  94 003e 5A62     		str	r2, [r3, #36]
+  95              	.LVL3:
+  96              		.loc 2 1770 3 is_stmt 0 view .LVU25
+  97              	.LBE45:
+  98              	.LBE44:
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+  99              		.loc 1 140 5 is_stmt 1 view .LVU26
+ 100              	.LBB46:
+ 101              	.LBI46:
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /**
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @brief  Release APB2 peripherals reset.
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ReleaseReset\n
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ReleaseReset\n
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART1RST      LL_APB2_GRP1_ReleaseReset\n
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     USART6RST      LL_APB2_GRP1_ReleaseReset\n
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     ADCRST         LL_APB2_GRP1_ReleaseReset\n
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC1RST      LL_APB2_GRP1_ReleaseReset\n
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SDMMC2RST      LL_APB2_GRP1_ReleaseReset\n
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ReleaseReset\n
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ReleaseReset\n
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ReleaseReset\n
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ReleaseReset\n
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ReleaseReset\n
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ReleaseReset\n
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ReleaseReset\n
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ReleaseReset\n
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ReleaseReset\n
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ReleaseReset\n
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ReleaseReset\n
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DSIRST         LL_APB2_GRP1_ReleaseReset\n
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ReleaseReset\n
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     MDIORST        LL_APB2_GRP1_ReleaseReset\n
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         APB2RSTR     OTGPHYCRST     LL_APB2_GRP1_ReleaseReset
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @param  Periphs This parameter can be a combination of the following values:
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+ARM GAS  /tmp/cc1GpNf6.s 			page 38
+
+
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   *         (*) value not defined in all devices.
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   * @retval None
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+ 102              		.loc 2 1825 22 view .LVU27
+ 103              	.LBB47:
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h ****   CLEAR_BIT(RCC->APB2RSTR, Periphs);
+ 104              		.loc 2 1827 3 view .LVU28
+ 105 0040 5A6A     		ldr	r2, [r3, #36]
+ 106 0042 22F01002 		bic	r2, r2, #16
+ 107 0046 5A62     		str	r2, [r3, #36]
+ 108              	.LBE47:
+ 109              	.LBE46:
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 110              		.loc 1 129 15 is_stmt 0 view .LVU29
+ 111 0048 0020     		movs	r0, #0
+ 112              	.LVL4:
+ 113              	.LBB49:
+ 114              	.LBB48:
+1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 115              		.loc 2 1828 1 view .LVU30
+ 116 004a 7047     		bx	lr
+ 117              	.LVL5:
+ 118              	.L12:
+ 119              		.loc 2 1828 1 view .LVU31
+ 120              	.LBE48:
+ 121              	.LBE49:
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 122              		.loc 1 145 5 is_stmt 1 view .LVU32
+ 123              	.LBB50:
+ 124              	.LBI50:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 125              		.loc 2 1295 22 view .LVU33
+ 126              	.LBB51:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 127              		.loc 2 1297 3 view .LVU34
+ 128 004c 03F5FA33 		add	r3, r3, #128000
+ 129 0050 1A6A     		ldr	r2, [r3, #32]
+ARM GAS  /tmp/cc1GpNf6.s 			page 39
+
+
+ 130 0052 42F40032 		orr	r2, r2, #131072
+ 131 0056 1A62     		str	r2, [r3, #32]
+ 132              	.LVL6:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 133              		.loc 2 1297 3 is_stmt 0 view .LVU35
+ 134              	.LBE51:
+ 135              	.LBE50:
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 136              		.loc 1 148 5 is_stmt 1 view .LVU36
+ 137              	.LBB52:
+ 138              	.LBI52:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 139              		.loc 2 1367 22 view .LVU37
+ 140              	.LBB53:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 141              		.loc 2 1369 3 view .LVU38
+ 142 0058 1A6A     		ldr	r2, [r3, #32]
+ 143 005a 22F40032 		bic	r2, r2, #131072
+ 144 005e 1A62     		str	r2, [r3, #32]
+ 145              	.LBE53:
+ 146              	.LBE52:
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 147              		.loc 1 129 15 is_stmt 0 view .LVU39
+ 148 0060 0020     		movs	r0, #0
+ 149              	.LVL7:
+ 150              	.LBB55:
+ 151              	.LBB54:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 152              		.loc 2 1370 1 view .LVU40
+ 153 0062 7047     		bx	lr
+ 154              	.LVL8:
+ 155              	.L13:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 156              		.loc 2 1370 1 view .LVU41
+ 157              	.LBE54:
+ 158              	.LBE55:
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 159              		.loc 1 153 5 is_stmt 1 view .LVU42
+ 160              	.LBB56:
+ 161              	.LBI56:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 162              		.loc 2 1295 22 view .LVU43
+ 163              	.LBB57:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 164              		.loc 2 1297 3 view .LVU44
+ 165 0064 03F5F833 		add	r3, r3, #126976
+ 166 0068 1A6A     		ldr	r2, [r3, #32]
+ 167 006a 42F48022 		orr	r2, r2, #262144
+ 168 006e 1A62     		str	r2, [r3, #32]
+ 169              	.LVL9:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 170              		.loc 2 1297 3 is_stmt 0 view .LVU45
+ 171              	.LBE57:
+ 172              	.LBE56:
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 173              		.loc 1 156 5 is_stmt 1 view .LVU46
+ 174              	.LBB58:
+ARM GAS  /tmp/cc1GpNf6.s 			page 40
+
+
+ 175              	.LBI58:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 176              		.loc 2 1367 22 view .LVU47
+ 177              	.LBB59:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 178              		.loc 2 1369 3 view .LVU48
+ 179 0070 1A6A     		ldr	r2, [r3, #32]
+ 180 0072 22F48022 		bic	r2, r2, #262144
+ 181 0076 1A62     		str	r2, [r3, #32]
+ 182              	.LBE59:
+ 183              	.LBE58:
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 184              		.loc 1 129 15 is_stmt 0 view .LVU49
+ 185 0078 0020     		movs	r0, #0
+ 186              	.LVL10:
+ 187              	.LBB61:
+ 188              	.LBB60:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 189              		.loc 2 1370 1 view .LVU50
+ 190 007a 7047     		bx	lr
+ 191              	.LVL11:
+ 192              	.L14:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 193              		.loc 2 1370 1 view .LVU51
+ 194              	.LBE60:
+ 195              	.LBE61:
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 196              		.loc 1 161 5 is_stmt 1 view .LVU52
+ 197              	.LBB62:
+ 198              	.LBI62:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 199              		.loc 2 1295 22 view .LVU53
+ 200              	.LBB63:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 201              		.loc 2 1297 3 view .LVU54
+ 202 007c 03F5F633 		add	r3, r3, #125952
+ 203 0080 1A6A     		ldr	r2, [r3, #32]
+ 204 0082 42F40022 		orr	r2, r2, #524288
+ 205 0086 1A62     		str	r2, [r3, #32]
+ 206              	.LVL12:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 207              		.loc 2 1297 3 is_stmt 0 view .LVU55
+ 208              	.LBE63:
+ 209              	.LBE62:
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 210              		.loc 1 164 5 is_stmt 1 view .LVU56
+ 211              	.LBB64:
+ 212              	.LBI64:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 213              		.loc 2 1367 22 view .LVU57
+ 214              	.LBB65:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 215              		.loc 2 1369 3 view .LVU58
+ 216 0088 1A6A     		ldr	r2, [r3, #32]
+ 217 008a 22F40022 		bic	r2, r2, #524288
+ 218 008e 1A62     		str	r2, [r3, #32]
+ 219              	.LBE65:
+ARM GAS  /tmp/cc1GpNf6.s 			page 41
+
+
+ 220              	.LBE64:
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 221              		.loc 1 129 15 is_stmt 0 view .LVU59
+ 222 0090 0020     		movs	r0, #0
+ 223              	.LVL13:
+ 224              	.LBB67:
+ 225              	.LBB66:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 226              		.loc 2 1370 1 view .LVU60
+ 227 0092 7047     		bx	lr
+ 228              	.LVL14:
+ 229              	.L15:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 230              		.loc 2 1370 1 view .LVU61
+ 231              	.LBE66:
+ 232              	.LBE67:
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 233              		.loc 1 169 5 is_stmt 1 view .LVU62
+ 234              	.LBB68:
+ 235              	.LBI68:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 236              		.loc 2 1295 22 view .LVU63
+ 237              	.LBB69:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 238              		.loc 2 1297 3 view .LVU64
+ 239 0094 03F5F433 		add	r3, r3, #124928
+ 240 0098 1A6A     		ldr	r2, [r3, #32]
+ 241 009a 42F48012 		orr	r2, r2, #1048576
+ 242 009e 1A62     		str	r2, [r3, #32]
+ 243              	.LVL15:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 244              		.loc 2 1297 3 is_stmt 0 view .LVU65
+ 245              	.LBE69:
+ 246              	.LBE68:
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 247              		.loc 1 172 5 is_stmt 1 view .LVU66
+ 248              	.LBB70:
+ 249              	.LBI70:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 250              		.loc 2 1367 22 view .LVU67
+ 251              	.LBB71:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 252              		.loc 2 1369 3 view .LVU68
+ 253 00a0 1A6A     		ldr	r2, [r3, #32]
+ 254 00a2 22F48012 		bic	r2, r2, #1048576
+ 255 00a6 1A62     		str	r2, [r3, #32]
+ 256              	.LBE71:
+ 257              	.LBE70:
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 258              		.loc 1 129 15 is_stmt 0 view .LVU69
+ 259 00a8 0020     		movs	r0, #0
+ 260              	.LVL16:
+ 261              	.LBB73:
+ 262              	.LBB72:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 263              		.loc 2 1370 1 view .LVU70
+ 264 00aa 7047     		bx	lr
+ARM GAS  /tmp/cc1GpNf6.s 			page 42
+
+
+ 265              	.LVL17:
+ 266              	.L16:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 267              		.loc 2 1370 1 view .LVU71
+ 268              	.LBE72:
+ 269              	.LBE73:
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 270              		.loc 1 177 5 is_stmt 1 view .LVU72
+ 271              	.LBB74:
+ 272              	.LBI74:
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 273              		.loc 2 1768 22 view .LVU73
+ 274              	.LBB75:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 275              		.loc 2 1770 3 view .LVU74
+ 276 00ac 03F59233 		add	r3, r3, #74752
+ 277 00b0 5A6A     		ldr	r2, [r3, #36]
+ 278 00b2 42F02002 		orr	r2, r2, #32
+ 279 00b6 5A62     		str	r2, [r3, #36]
+ 280              	.LVL18:
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 281              		.loc 2 1770 3 is_stmt 0 view .LVU75
+ 282              	.LBE75:
+ 283              	.LBE74:
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 284              		.loc 1 180 5 is_stmt 1 view .LVU76
+ 285              	.LBB76:
+ 286              	.LBI76:
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 287              		.loc 2 1825 22 view .LVU77
+ 288              	.LBB77:
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 289              		.loc 2 1827 3 view .LVU78
+ 290 00b8 5A6A     		ldr	r2, [r3, #36]
+ 291 00ba 22F02002 		bic	r2, r2, #32
+ 292 00be 5A62     		str	r2, [r3, #36]
+ 293              	.LBE77:
+ 294              	.LBE76:
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 295              		.loc 1 129 15 is_stmt 0 view .LVU79
+ 296 00c0 0020     		movs	r0, #0
+ 297              	.LVL19:
+ 298              	.LBB79:
+ 299              	.LBB78:
+ 300              		.loc 2 1828 1 view .LVU80
+ 301 00c2 7047     		bx	lr
+ 302              	.LVL20:
+ 303              	.L17:
+ 304              		.loc 2 1828 1 view .LVU81
+ 305              	.LBE78:
+ 306              	.LBE79:
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 307              		.loc 1 185 5 is_stmt 1 view .LVU82
+ 308              	.LBB80:
+ 309              	.LBI80:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 310              		.loc 2 1295 22 view .LVU83
+ARM GAS  /tmp/cc1GpNf6.s 			page 43
+
+
+ 311              	.LBB81:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 312              		.loc 2 1297 3 view .LVU84
+ 313 00c4 03F5E033 		add	r3, r3, #114688
+ 314 00c8 1A6A     		ldr	r2, [r3, #32]
+ 315 00ca 42F08042 		orr	r2, r2, #1073741824
+ 316 00ce 1A62     		str	r2, [r3, #32]
+ 317              	.LVL21:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 318              		.loc 2 1297 3 is_stmt 0 view .LVU85
+ 319              	.LBE81:
+ 320              	.LBE80:
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 321              		.loc 1 188 5 is_stmt 1 view .LVU86
+ 322              	.LBB82:
+ 323              	.LBI82:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 324              		.loc 2 1367 22 view .LVU87
+ 325              	.LBB83:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 326              		.loc 2 1369 3 view .LVU88
+ 327 00d0 1A6A     		ldr	r2, [r3, #32]
+ 328 00d2 22F08042 		bic	r2, r2, #1073741824
+ 329 00d6 1A62     		str	r2, [r3, #32]
+ 330              	.LBE83:
+ 331              	.LBE82:
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 332              		.loc 1 129 15 is_stmt 0 view .LVU89
+ 333 00d8 0020     		movs	r0, #0
+ 334              	.LVL22:
+ 335              	.LBB85:
+ 336              	.LBB84:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 337              		.loc 2 1370 1 view .LVU90
+ 338 00da 7047     		bx	lr
+ 339              	.LVL23:
+ 340              	.L18:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 341              		.loc 2 1370 1 view .LVU91
+ 342              	.LBE84:
+ 343              	.LBE85:
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 344              		.loc 1 193 5 is_stmt 1 view .LVU92
+ 345              	.LBB86:
+ 346              	.LBI86:
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 347              		.loc 2 1295 22 view .LVU93
+ 348              	.LBB87:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 349              		.loc 2 1297 3 view .LVU94
+ 350 00dc 03F5DE33 		add	r3, r3, #113664
+ 351 00e0 1A6A     		ldr	r2, [r3, #32]
+ 352 00e2 42F00042 		orr	r2, r2, #-2147483648
+ 353 00e6 1A62     		str	r2, [r3, #32]
+ 354              	.LVL24:
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 355              		.loc 2 1297 3 is_stmt 0 view .LVU95
+ARM GAS  /tmp/cc1GpNf6.s 			page 44
+
+
+ 356              	.LBE87:
+ 357              	.LBE86:
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 358              		.loc 1 196 5 is_stmt 1 view .LVU96
+ 359              	.LBB88:
+ 360              	.LBI88:
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** {
+ 361              		.loc 2 1367 22 view .LVU97
+ 362              	.LBB89:
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** }
+ 363              		.loc 2 1369 3 view .LVU98
+ 364 00e8 1A6A     		ldr	r2, [r3, #32]
+ 365 00ea 22F00042 		bic	r2, r2, #-2147483648
+ 366 00ee 1A62     		str	r2, [r3, #32]
+ 367              	.LBE89:
+ 368              	.LBE88:
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 369              		.loc 1 129 15 is_stmt 0 view .LVU99
+ 370 00f0 0020     		movs	r0, #0
+ 371              	.LVL25:
+ 372              	.LBB91:
+ 373              	.LBB90:
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 
+ 374              		.loc 2 1370 1 view .LVU100
+ 375 00f2 7047     		bx	lr
+ 376              	.L20:
+ 377              		.align	2
+ 378              	.L19:
+ 379 00f4 00100140 		.word	1073811456
+ 380 00f8 00440040 		.word	1073759232
+ 381 00fc 00480040 		.word	1073760256
+ 382 0100 004C0040 		.word	1073761280
+ 383 0104 00500040 		.word	1073762304
+ 384 0108 00140140 		.word	1073812480
+ 385 010c 00780040 		.word	1073772544
+ 386 0110 007C0040 		.word	1073773568
+ 387              	.LBE90:
+ 388              	.LBE91:
+ 389              		.cfi_endproc
+ 390              	.LFE542:
+ 392              		.section	.text.LL_USART_Init,"ax",%progbits
+ 393              		.align	1
+ 394              		.global	LL_USART_Init
+ 395              		.syntax unified
+ 396              		.thumb
+ 397              		.thumb_func
+ 398              		.fpu fpv5-d16
+ 400              	LL_USART_Init:
+ 401              	.LVL26:
+ 402              	.LFB543:
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /**
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @brief  Initialize USART registers according to the specified
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *         parameters in USART_InitStruct.
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @note   As some bits in USART configuration registers can only be written when
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled sta
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *         this function. Otherwise, ERROR result will be returned.
+ARM GAS  /tmp/cc1GpNf6.s 			page 45
+
+
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different f
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @param  USARTx USART Instance
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *         that contains the configuration information for the specified USART peripheral.
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @retval An ErrorStatus enumeration value:
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *          - ERROR: Problem occurred during USART Registers initialization
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** {
+ 403              		.loc 1 221 1 is_stmt 1 view -0
+ 404              		.cfi_startproc
+ 405              		@ args = 0, pretend = 0, frame = 0
+ 406              		@ frame_needed = 0, uses_anonymous_args = 0
+ 407              		.loc 1 221 1 is_stmt 0 view .LVU102
+ 408 0000 38B5     		push	{r3, r4, r5, lr}
+ 409              	.LCFI0:
+ 410              		.cfi_def_cfa_offset 16
+ 411              		.cfi_offset 3, -16
+ 412              		.cfi_offset 4, -12
+ 413              		.cfi_offset 5, -8
+ 414              		.cfi_offset 14, -4
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   ErrorStatus status = ERROR;
+ 415              		.loc 1 222 3 is_stmt 1 view .LVU103
+ 416              	.LVL27:
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+ 417              		.loc 1 223 3 view .LVU104
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   /* Check the parameters */
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   assert_param(IS_UART_INSTANCE(USARTx));
+ 418              		.loc 1 226 3 view .LVU105
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ 419              		.loc 1 227 3 view .LVU106
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+ 420              		.loc 1 228 3 view .LVU107
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+ 421              		.loc 1 229 3 view .LVU108
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+ 422              		.loc 1 230 3 view .LVU109
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+ 423              		.loc 1 231 3 view .LVU110
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+ 424              		.loc 1 232 3 view .LVU111
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+ 425              		.loc 1 233 3 view .LVU112
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   /* USART needs to be in disabled state, in order to be able to configure some bits in
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      CRx registers */
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   if (LL_USART_IsEnabled(USARTx) == 0U)
+ 426              		.loc 1 237 3 view .LVU113
+ 427              	.LBB100:
+ 428              	.LBI100:
+ 429              		.file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @file    stm32f7xx_ll_usart.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @author  MCD Application Team
+ARM GAS  /tmp/cc1GpNf6.s 			page 46
+
+
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief   Header file of USART LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifndef STM32F7xx_LL_USART_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define STM32F7xx_LL_USART_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****  || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8)
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL USART
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private types -------------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private variables ---------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private constants ---------------------------------------------------------*/
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Constants USART Private Constants
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private macros ------------------------------------------------------------*/
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER)
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Macros USART Private Macros
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported types ------------------------------------------------------------*/
+ARM GAS  /tmp/cc1GpNf6.s 			page 47
+
+
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER)
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief LL USART Init Structure definition
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rat
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetBaudRate().*/
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or receive
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_DATAWI
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetDataWidth().*/
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_STOPBI
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetStopBitsLength().*/
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t Parity;                    /*!< Specifies the parity mode.
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_PARITY
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetParity().*/
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is en
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_DIRECT
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetTransferDirection().*/
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enab
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_HWCONT
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetHWFlowCtrl().*/
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_OVERSA
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This feature can be modified afterwards using unitary
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            function @ref LL_USART_SetOverSampling().*/
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_InitTypeDef;
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief LL USART Clock Init Structure definition
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/cc1GpNf6.s 			page 48
+
+
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_CLOCK.
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_Disabl
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_POLARI
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            functions @ref LL_USART_SetClockPolarity().
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture 
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_PHASE.
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            functions @ref LL_USART_SetClockPhase().
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the l
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            data bit (MSB) has to be output on the SCLK pin in synch
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            This parameter can be a value of @ref USART_LL_EC_LASTCL
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            USART HW configuration can be modified afterwards using 
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            functions @ref LL_USART_SetLastClkPulseOutput().
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                            For more details, refer to description of this function.
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_ClockInitTypeDef;
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USE_FULL_LL_DRIVER */
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported constants --------------------------------------------------------*/
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Constants USART Exported Constants
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief    Flags defines which can be used with LL_USART_WriteReg function
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error cle
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error cl
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_NCF                        USART_ICR_NCF                 /*!< Noise error dete
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error cl
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detect
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission com
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission com
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detect
+ARM GAS  /tmp/cc1GpNf6.s 			page 49
+
+
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag *
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block cle
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match 
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief    Flags defines which can be used with LL_USART_ReadReg function
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error fla
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error fl
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected f
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error fl
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detect
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RXNE                       USART_ISR_RXNE                /*!< Read data regist
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission com
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TXE                        USART_ISR_TXE                 /*!< Transmit data re
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detect
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt fl
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block fla
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate e
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate f
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match 
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag 
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup 
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable 
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK)
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable a
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission com
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IT IT Defines
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt e
+ARM GAS  /tmp/cc1GpNf6.s 			page 50
+
+
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data regist
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission com
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data re
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match 
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block int
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detect
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt 
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt en
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE)
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT)
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission com
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DIRECTION Communication Direction
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PARITY Parity Control
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity co
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity co
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity co
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP Wakeup
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : S
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : S
+ARM GAS  /tmp/cc1GpNf6.s 			page 51
+
+
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : S
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER)
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLOCK Clock Signal
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provid
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided *
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the l
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the l
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PHASE Clock Phase
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transiti
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transit
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_POLARITY Clock Polarity
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCL
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_STOPBITS Stop Bits
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5
+ARM GAS  /tmp/cc1GpNf6.s 			page 52
+
+
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 s
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 s
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as d
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works usin
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works usin
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the da
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the da
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BITORDER Bit Order
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/rece
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/rece
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Me
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Fa
+ARM GAS  /tmp/cc1GpNf6.s 			page 53
+
+
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection 
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection 
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and R
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS outpu
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode 
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and R
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS)
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake u
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake u
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake u
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode *
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection m
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection m
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ARM GAS  /tmp/cc1GpNf6.s 			page 54
+
+
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low 
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data regis
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data regis
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported macro ------------------------------------------------------------*/
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Macros USART Exported Macros
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Write a value in USART register
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __INSTANCE__ USART Instance
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __REG__ Register to be written
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __VALUE__ Value to be written in the register
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Read a value in USART register
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __INSTANCE__ USART Instance
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __REG__ Register to be read
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Register value
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/cc1GpNf6.s 			page 55
+
+
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Compute USARTDIV value according to Peripheral Clock and
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __BAUDRATE__ Baud rate value to achieve
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                                                 + ((__BAUDRATE__)/2U))/(__BAUDRATE_
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Compute USARTDIV value according to Peripheral Clock and
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  __BAUDRATE__ Baud rate value to achieve
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @}
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported functions --------------------------------------------------------*/
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Functions USART Exported Functions
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration Configuration functions
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @{
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART Enable
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UE            LL_USART_Enable
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR1, USART_CR1_UE);
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART Disable (all USART prescalers and outputs are disabled)
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         and current operations are discarded. The configuration of the USART is kept, but all t
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         flags, in the USARTx_ISR are set to their default values.
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UE            LL_USART_Disable
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+ARM GAS  /tmp/cc1GpNf6.s 			page 56
+
+
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if USART is enabled
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UE            LL_USART_IsEnabled
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
+ 430              		.loc 3 585 26 view .LVU114
+ 431              	.LBB101:
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+ 432              		.loc 3 587 3 view .LVU115
+ 433              		.loc 3 587 12 is_stmt 0 view .LVU116
+ 434 0002 0368     		ldr	r3, [r0]
+ 435              		.loc 3 587 73 view .LVU117
+ 436 0004 13F0010F 		tst	r3, #1
+ 437 0008 75D1     		bne	.L33
+ 438 000a 0446     		mov	r4, r0
+ 439 000c 0D46     		mov	r5, r1
+ 440              	.LVL28:
+ 441              		.loc 3 587 73 view .LVU118
+ 442              	.LBE101:
+ 443              	.LBE100:
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /*---------------------------- USART CR1 Configuration ---------------------
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->Transfe
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      */
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     MODIFY_REG(USARTx->CR1,
+ 444              		.loc 1 246 5 is_stmt 1 view .LVU119
+ 445 000e 0368     		ldr	r3, [r0]
+ 446 0010 3B4A     		ldr	r2, .L48
+ 447 0012 1A40     		ands	r2, r2, r3
+ 448 0014 4B68     		ldr	r3, [r1, #4]
+ 449 0016 C968     		ldr	r1, [r1, #12]
+ 450              	.LVL29:
+ 451              		.loc 1 246 5 is_stmt 0 view .LVU120
+ 452 0018 0B43     		orrs	r3, r3, r1
+ 453 001a 2969     		ldr	r1, [r5, #16]
+ 454 001c 0B43     		orrs	r3, r3, r1
+ 455 001e A969     		ldr	r1, [r5, #24]
+ 456 0020 0B43     		orrs	r3, r3, r1
+ 457 0022 1343     		orrs	r3, r3, r2
+ 458 0024 0360     		str	r3, [r0]
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /*---------------------------- USART CR2 Configuration ---------------------
+ARM GAS  /tmp/cc1GpNf6.s 			page 57
+
+
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      * Configure USARTx CR2 (Stop bits) with parameters:
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      */
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+ 459              		.loc 1 257 5 is_stmt 1 view .LVU121
+ 460 0026 AB68     		ldr	r3, [r5, #8]
+ 461              	.LVL30:
+ 462              	.LBB102:
+ 463              	.LBI102:
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART enabled in STOP Mode.
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provide
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         USART clock selection is HSI or LSE in RCC.
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART disabled in STOP Mode.
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_UCESM)
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/cc1GpNf6.s 			page 58
+
+
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART Clock enabled in STOP Mode
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is called, USART Clock is enabled while in STOP mode
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          UCESM         LL_USART_EnableClockInStopMode
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx)
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM);
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  USART clock disabled in STOP Mode
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   When this function is called, USART Clock is disabled while in STOP mode
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          UCESM         LL_USART_DisableClockInStopMode
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx)
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM);
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if USART clock is enabled in STOP Mode
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          UCESM         LL_USART_IsClockEnabledInStopMode
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx)
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM));
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_UCESM */
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM*/
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Receiver Disable
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ARM GAS  /tmp/cc1GpNf6.s 			page 59
+
+
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Transmitter Enable
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Transmitter Disable
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure simultaneously enabled/disabled states
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         of Transmitter and Receiver
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          TE            LL_USART_SetTransferDirection
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  TransferDirection This parameter can be one of the following values:
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_NONE
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_RX
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX_RX
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirectio
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return enabled/disabled states of Transmitter and Receiver
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          TE            LL_USART_GetTransferDirection
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_NONE
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_RX
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DIRECTION_TX_RX
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/cc1GpNf6.s 			page 60
+
+
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   This function selects if hardware parity control (generation and detection) is enabled 
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at th
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PS            LL_USART_SetParity\n
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          PCE           LL_USART_SetParity
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Parity This parameter can be one of the following values:
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_NONE
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_EVEN
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_ODD
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PS            LL_USART_GetParity\n
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          PCE           LL_USART_GetParity
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_NONE
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_EVEN
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_ODD
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Receiver Wake Up method from Mute mode.
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Method This parameter can be one of the following values:
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_IDLELINE
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Receiver Wake Up method from Mute mode
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_IDLELINE
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
+ARM GAS  /tmp/cc1GpNf6.s 			page 61
+
+
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M1            LL_USART_SetDataWidth
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  DataWidth This parameter can be one of the following values:
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_7B
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_8B
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_9B
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M1            LL_USART_GetDataWidth
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_7B
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_8B
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_9B
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Allow switch between Mute Mode and Active mode
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/cc1GpNf6.s 			page 62
+
+
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Oversampling to 8-bit or 16-bit mode
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  OverSampling This parameter can be one of the following values:
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_16
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_8
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Oversampling mode
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_16
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_8
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  LastBitClockPulse This parameter can be one of the following values:
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPul
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve Clock pulse of the last data bit output configuration
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (Last bit Clock pulse output to the SCLK pin or not)
+ARM GAS  /tmp/cc1GpNf6.s 			page 63
+
+
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  ClockPhase This parameter can be one of the following values:
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_1EDGE
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_2EDGE
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_1EDGE
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_2EDGE
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  ClockPolarity This parameter can be one of the following values:
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_LOW
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_HIGH
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/cc1GpNf6.s 			page 64
+
+
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_LOW
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_HIGH
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutpu
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          CPOL          LL_USART_ConfigClock\n
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          LBCL          LL_USART_ConfigClock
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Phase This parameter can be one of the following values:
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_1EDGE
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PHASE_2EDGE
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Polarity This parameter can be one of the following values:
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_LOW
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_POLARITY_HIGH
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  LBCPOutput This parameter can be one of the following values:
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity,
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCP
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Clock output on SCLK pin
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+ARM GAS  /tmp/cc1GpNf6.s 			page 65
+
+
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Clock output on SCLK pin
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Clock output on SCLK pin is enabled
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Synchronous mode is supported by the USARTx instance.
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set the length of the stop bits
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  StopBits This parameter can be one of the following values:
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_0_5
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1_5
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_2
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+ 464              		.loc 3 1073 22 view .LVU122
+ 465              	.LBB103:
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+ 466              		.loc 3 1075 3 view .LVU123
+ 467 0028 4268     		ldr	r2, [r0, #4]
+ 468 002a 22F44052 		bic	r2, r2, #12288
+ 469 002e 1343     		orrs	r3, r3, r2
+ 470              	.LVL31:
+ 471              		.loc 3 1075 3 is_stmt 0 view .LVU124
+ 472 0030 4360     		str	r3, [r0, #4]
+ 473              	.LVL32:
+ 474              		.loc 3 1075 3 view .LVU125
+ 475              	.LBE103:
+ 476              	.LBE102:
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /*---------------------------- USART CR3 Configuration ---------------------
+ARM GAS  /tmp/cc1GpNf6.s 			page 66
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      *   USART_InitStruct->HardwareFlowControl value.
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      */
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+ 477              		.loc 1 264 5 is_stmt 1 view .LVU126
+ 478 0032 6B69     		ldr	r3, [r5, #20]
+ 479              	.LVL33:
+ 480              	.LBB104:
+ 481              	.LBI104:
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve the length of the stop bits
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_0_5
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1_5
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_2
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Call of this function is equivalent to following function call sequence :
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          PCE           LL_USART_ConfigCharacter\n
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M0            LL_USART_ConfigCharacter\n
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR1          M1            LL_USART_ConfigCharacter\n
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          STOP          LL_USART_ConfigCharacter
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  DataWidth This parameter can be one of the following values:
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_7B
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_8B
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_DATAWIDTH_9B
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Parity This parameter can be one of the following values:
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_NONE
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_EVEN
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_PARITY_ODD
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  StopBits This parameter can be one of the following values:
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_0_5
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_1_5
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_STOPBITS_2
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t P
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                               uint32_t StopBits)
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ARM GAS  /tmp/cc1GpNf6.s 			page 67
+
+
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure TX/RX pins swapping setting.
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  SwapConfig This parameter can be one of the following values:
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_STANDARD
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_SWAPPED
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve TX/RX pins swapping configuration.
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_STANDARD
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXRX_SWAPPED
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure RX pin active level logic
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PinInvMethod This parameter can be one of the following values:
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve RX pin active level logic configuration
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ARM GAS  /tmp/cc1GpNf6.s 			page 68
+
+
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure TX pin active level logic
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PinInvMethod This parameter can be one of the following values:
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve TX pin active level logic configuration
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure Binary data logic.
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Allow to define how Logical data from the data register are send/received :
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  DataLogic This parameter can be one of the following values:
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Retrieve Binary data configuration
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/cc1GpNf6.s 			page 69
+
+
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   MSB First means data is transmitted/received with the MSB first, following the start bi
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LSB First means data is transmitted/received with data bit 0 first, following the start
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  BitOrder This parameter can be one of the following values:
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_LSBFIRST
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_MSBFIRST
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   MSB First means data is transmitted/received with the MSB first, following the start bi
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         LSB First means data is transmitted/received with data bit 0 first, following the start
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_LSBFIRST
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_BITORDER_MSBFIRST
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Auto Baud-Rate Detection
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Auto Baud-Rate Detection
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ARM GAS  /tmp/cc1GpNf6.s 			page 70
+
+
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Auto Baud-Rate mode bits
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  AutoBaudRateMode This parameter can be one of the following values:
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Auto Baud-Rate mode
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Auto Baud Rate detection feature is supported by the USARTx instance.
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Receiver Timeout
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+ARM GAS  /tmp/cc1GpNf6.s 			page 71
+
+
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Receiver Timeout
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Receiver Timeout feature is enabled
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Set Address of the USART node.
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         for wake up with address mark detection.
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (b7-b4 should be set to 0)
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         for wake up with 7-bit address mark detection.
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         The MSB of the character sent by the transmitter should be equal to 1.
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         It may also be used for character detection during normal reception,
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         value and CMF flag is set on match)
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  AddressLen This parameter can be one of the following values:
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  NodeAddress 4 or 7 bit Address of the USART node.
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   If 4-bit Address Detection is selected in ADDM7,
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+ARM GAS  /tmp/cc1GpNf6.s 			page 72
+
+
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         If 7-bit Address Detection is selected in ADDM7,
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable RTS HW Flow Control
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable RTS HW Flow Control
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable CTS HW Flow Control
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+ARM GAS  /tmp/cc1GpNf6.s 			page 73
+
+
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable CTS HW Flow Control
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure HW Flow Control mode (both CTS and RTS)
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  HardwareFlowControl This parameter can be one of the following values:
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_NONE
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_CTS
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+ 482              		.loc 3 1498 22 view .LVU127
+ 483              	.LBB105:
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+ 484              		.loc 3 1500 3 view .LVU128
+ 485 0034 8268     		ldr	r2, [r0, #8]
+ 486 0036 22F44072 		bic	r2, r2, #768
+ 487 003a 1343     		orrs	r3, r3, r2
+ 488              	.LVL34:
+ 489              		.loc 3 1500 3 is_stmt 0 view .LVU129
+ 490 003c 8360     		str	r3, [r0, #8]
+ 491              	.LVL35:
+ 492              		.loc 3 1500 3 view .LVU130
+ 493              	.LBE105:
+ 494              	.LBE104:
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /*---------------------------- USART BRR Configuration ---------------------
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      * Retrieve Clock frequency used for USART Peripheral
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      */
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     if (USARTx == USART1)
+ 495              		.loc 1 269 5 is_stmt 1 view .LVU131
+ 496              		.loc 1 269 8 is_stmt 0 view .LVU132
+ 497 003e 314B     		ldr	r3, .L48+4
+ARM GAS  /tmp/cc1GpNf6.s 			page 74
+
+
+ 498 0040 9842     		cmp	r0, r3
+ 499 0042 16D0     		beq	.L38
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     else if (USARTx == USART2)
+ 500              		.loc 1 273 10 is_stmt 1 view .LVU133
+ 501              		.loc 1 273 13 is_stmt 0 view .LVU134
+ 502 0044 304B     		ldr	r3, .L48+8
+ 503 0046 9842     		cmp	r0, r3
+ 504 0048 1CD0     		beq	.L39
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     else if (USARTx == USART3)
+ 505              		.loc 1 277 10 is_stmt 1 view .LVU135
+ 506              		.loc 1 277 13 is_stmt 0 view .LVU136
+ 507 004a 304B     		ldr	r3, .L48+12
+ 508 004c 9842     		cmp	r0, r3
+ 509 004e 1DD0     		beq	.L40
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     else if (USARTx == UART4)
+ 510              		.loc 1 281 10 is_stmt 1 view .LVU137
+ 511              		.loc 1 281 13 is_stmt 0 view .LVU138
+ 512 0050 2F4B     		ldr	r3, .L48+16
+ 513 0052 9842     		cmp	r0, r3
+ 514 0054 1ED0     		beq	.L41
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     else if (USARTx == UART5)
+ 515              		.loc 1 285 10 is_stmt 1 view .LVU139
+ 516              		.loc 1 285 13 is_stmt 0 view .LVU140
+ 517 0056 2F4B     		ldr	r3, .L48+20
+ 518 0058 9842     		cmp	r0, r3
+ 519 005a 1FD0     		beq	.L42
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     else if (USARTx == USART6)
+ 520              		.loc 1 289 10 is_stmt 1 view .LVU141
+ 521              		.loc 1 289 13 is_stmt 0 view .LVU142
+ 522 005c 2E4B     		ldr	r3, .L48+24
+ 523 005e 9842     		cmp	r0, r3
+ 524 0060 21D0     		beq	.L43
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART6_CLKSOURCE);
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     else if (USARTx == UART7)
+ 525              		.loc 1 293 10 is_stmt 1 view .LVU143
+ 526              		.loc 1 293 13 is_stmt 0 view .LVU144
+ 527 0062 2E4B     		ldr	r3, .L48+28
+ 528 0064 9842     		cmp	r0, r3
+ 529 0066 23D0     		beq	.L44
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ARM GAS  /tmp/cc1GpNf6.s 			page 75
+
+
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART7_CLKSOURCE);
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     else if (USARTx == UART8)
+ 530              		.loc 1 297 10 is_stmt 1 view .LVU145
+ 531              		.loc 1 297 13 is_stmt 0 view .LVU146
+ 532 0068 2D4B     		ldr	r3, .L48+32
+ 533 006a 9842     		cmp	r0, r3
+ 534 006c 25D0     		beq	.L45
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+ 535              		.loc 1 222 15 view .LVU147
+ 536 006e 0120     		movs	r0, #1
+ 537              	.LVL36:
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+ 538              		.loc 1 222 15 view .LVU148
+ 539 0070 42E0     		b	.L22
+ 540              	.LVL37:
+ 541              	.L38:
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 542              		.loc 1 271 7 is_stmt 1 view .LVU149
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 543              		.loc 1 271 19 is_stmt 0 view .LVU150
+ 544 0072 0320     		movs	r0, #3
+ 545              	.LVL38:
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 546              		.loc 1 271 19 view .LVU151
+ 547 0074 FFF7FEFF 		bl	LL_RCC_GetUSARTClockFreq
+ 548              	.LVL39:
+ 549              	.L24:
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART8_CLKSOURCE);
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     else
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       /* Nothing to do, as error code is already assigned to ERROR value */
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 550              		.loc 1 304 5 is_stmt 1 view .LVU152
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* Configure the USART Baud Rate :
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****        - valid baud rate value (different from 0) is required
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****        - Peripheral clock as returned by RCC service, should be valid (different from 0).
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     */
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+ 551              		.loc 1 310 5 view .LVU153
+ 552              		.loc 1 310 8 is_stmt 0 view .LVU154
+ 553 0078 0028     		cmp	r0, #0
+ 554 007a 3ED0     		beq	.L35
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****         && (USART_InitStruct->BaudRate != 0U))
+ 555              		.loc 1 311 29 view .LVU155
+ 556 007c 2B68     		ldr	r3, [r5]
+ 557              		.loc 1 311 9 view .LVU156
+ 558 007e 0BBB     		cbnz	r3, .L46
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+ 559              		.loc 1 222 15 view .LVU157
+ 560 0080 0120     		movs	r0, #1
+ 561              	.LVL40:
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+ 562              		.loc 1 222 15 view .LVU158
+ARM GAS  /tmp/cc1GpNf6.s 			page 76
+
+
+ 563 0082 39E0     		b	.L22
+ 564              	.LVL41:
+ 565              	.L39:
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 566              		.loc 1 275 7 is_stmt 1 view .LVU159
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 567              		.loc 1 275 19 is_stmt 0 view .LVU160
+ 568 0084 0C20     		movs	r0, #12
+ 569              	.LVL42:
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 570              		.loc 1 275 19 view .LVU161
+ 571 0086 FFF7FEFF 		bl	LL_RCC_GetUSARTClockFreq
+ 572              	.LVL43:
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 573              		.loc 1 275 19 view .LVU162
+ 574 008a F5E7     		b	.L24
+ 575              	.LVL44:
+ 576              	.L40:
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 577              		.loc 1 279 7 is_stmt 1 view .LVU163
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 578              		.loc 1 279 19 is_stmt 0 view .LVU164
+ 579 008c 3020     		movs	r0, #48
+ 580              	.LVL45:
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 581              		.loc 1 279 19 view .LVU165
+ 582 008e FFF7FEFF 		bl	LL_RCC_GetUSARTClockFreq
+ 583              	.LVL46:
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 584              		.loc 1 279 19 view .LVU166
+ 585 0092 F1E7     		b	.L24
+ 586              	.LVL47:
+ 587              	.L41:
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 588              		.loc 1 283 7 is_stmt 1 view .LVU167
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 589              		.loc 1 283 19 is_stmt 0 view .LVU168
+ 590 0094 C020     		movs	r0, #192
+ 591              	.LVL48:
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 592              		.loc 1 283 19 view .LVU169
+ 593 0096 FFF7FEFF 		bl	LL_RCC_GetUARTClockFreq
+ 594              	.LVL49:
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 595              		.loc 1 283 19 view .LVU170
+ 596 009a EDE7     		b	.L24
+ 597              	.LVL50:
+ 598              	.L42:
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 599              		.loc 1 287 7 is_stmt 1 view .LVU171
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 600              		.loc 1 287 19 is_stmt 0 view .LVU172
+ 601 009c 4FF44070 		mov	r0, #768
+ 602              	.LVL51:
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 603              		.loc 1 287 19 view .LVU173
+ 604 00a0 FFF7FEFF 		bl	LL_RCC_GetUARTClockFreq
+ARM GAS  /tmp/cc1GpNf6.s 			page 77
+
+
+ 605              	.LVL52:
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 606              		.loc 1 287 19 view .LVU174
+ 607 00a4 E8E7     		b	.L24
+ 608              	.LVL53:
+ 609              	.L43:
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 610              		.loc 1 291 7 is_stmt 1 view .LVU175
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 611              		.loc 1 291 19 is_stmt 0 view .LVU176
+ 612 00a6 4FF44060 		mov	r0, #3072
+ 613              	.LVL54:
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 614              		.loc 1 291 19 view .LVU177
+ 615 00aa FFF7FEFF 		bl	LL_RCC_GetUSARTClockFreq
+ 616              	.LVL55:
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 617              		.loc 1 291 19 view .LVU178
+ 618 00ae E3E7     		b	.L24
+ 619              	.LVL56:
+ 620              	.L44:
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 621              		.loc 1 295 7 is_stmt 1 view .LVU179
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 622              		.loc 1 295 19 is_stmt 0 view .LVU180
+ 623 00b0 4FF44050 		mov	r0, #12288
+ 624              	.LVL57:
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 625              		.loc 1 295 19 view .LVU181
+ 626 00b4 FFF7FEFF 		bl	LL_RCC_GetUARTClockFreq
+ 627              	.LVL58:
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 628              		.loc 1 295 19 view .LVU182
+ 629 00b8 DEE7     		b	.L24
+ 630              	.LVL59:
+ 631              	.L45:
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 632              		.loc 1 299 7 is_stmt 1 view .LVU183
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 633              		.loc 1 299 19 is_stmt 0 view .LVU184
+ 634 00ba 4FF44040 		mov	r0, #49152
+ 635              	.LVL60:
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 636              		.loc 1 299 19 view .LVU185
+ 637 00be FFF7FEFF 		bl	LL_RCC_GetUARTClockFreq
+ 638              	.LVL61:
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 639              		.loc 1 299 19 view .LVU186
+ 640 00c2 D9E7     		b	.L24
+ 641              	.L46:
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       status = SUCCESS;
+ 642              		.loc 1 313 7 is_stmt 1 view .LVU187
+ 643              	.LVL62:
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       LL_USART_SetBaudRate(USARTx,
+ 644              		.loc 1 314 7 view .LVU188
+ 645 00c4 AA69     		ldr	r2, [r5, #24]
+ARM GAS  /tmp/cc1GpNf6.s 			page 78
+
+
+ 646              	.LVL63:
+ 647              	.LBB106:
+ 648              	.LBI106:
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return HW Flow Control configuration (both CTS and RTS)
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Hardware Flow control feature is supported by the USARTx instance.
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_NONE
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_CTS
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable One bit sampling method
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable One bit sampling method
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if One bit sampling method is enabled
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+ARM GAS  /tmp/cc1GpNf6.s 			page 79
+
+
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Enable Overrun detection
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Disable Overrun detection
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Indicate if Overrun detection is enabled
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval State of bit (1 or 0).
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM)
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS)
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  Type This parameter can be one of the following values:
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         Wake-up from Stop mode feature is supported by the USARTx instance.
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+ARM GAS  /tmp/cc1GpNf6.s 			page 80
+
+
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval Returned value can be one of the following values:
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /**
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         (Baud rate value != 0)
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  USARTx USART Instance
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  PeriphClk Peripheral Clock
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  OverSampling This parameter can be one of the following values:
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_16
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   *         @arg @ref LL_USART_OVERSAMPLING_8
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @param  BaudRate Baud Rate
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   * @retval None
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   */
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverS
+ 649              		.loc 3 1640 22 view .LVU189
+ 650              	.LBB107:
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****                                           uint32_t BaudRate)
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t usartdiv;
+ 651              		.loc 3 1643 3 view .LVU190
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   uint32_t brrtemp;
+ 652              		.loc 3 1644 3 view .LVU191
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   if (OverSampling == LL_USART_OVERSAMPLING_8)
+ 653              		.loc 3 1646 3 view .LVU192
+ 654              		.loc 3 1646 6 is_stmt 0 view .LVU193
+ 655 00c6 B2F5004F 		cmp	r2, #32768
+ 656 00ca 07D0     		beq	.L47
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp = usartdiv & 0xFFF0U;
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     USARTx->BRR = brrtemp;
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   else
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   {
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+ 657              		.loc 3 1655 5 is_stmt 1 view .LVU194
+ 658              		.loc 3 1655 30 is_stmt 0 view .LVU195
+ 659 00cc 00EB5300 		add	r0, r0, r3, lsr #1
+ 660              	.LVL64:
+ 661              		.loc 3 1655 30 view .LVU196
+ARM GAS  /tmp/cc1GpNf6.s 			page 81
+
+
+ 662 00d0 B0FBF3F3 		udiv	r3, r0, r3
+ 663              	.LVL65:
+ 664              		.loc 3 1655 30 view .LVU197
+ 665 00d4 9BB2     		uxth	r3, r3
+ 666              		.loc 3 1655 17 view .LVU198
+ 667 00d6 E360     		str	r3, [r4, #12]
+ 668              	.LVL66:
+ 669              	.L32:
+ 670              		.loc 3 1655 17 view .LVU199
+ 671              	.LBE107:
+ 672              	.LBE106:
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       LL_USART_SetBaudRate(USARTx,
+ 673              		.loc 1 313 14 view .LVU200
+ 674 00d8 0020     		movs	r0, #0
+ 675              	.LBB109:
+ 676              	.LBB108:
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 677              		.loc 3 1657 1 view .LVU201
+ 678 00da 0DE0     		b	.L22
+ 679              	.LVL67:
+ 680              	.L47:
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp = usartdiv & 0xFFF0U;
+ 681              		.loc 3 1648 5 is_stmt 1 view .LVU202
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp = usartdiv & 0xFFF0U;
+ 682              		.loc 3 1648 27 is_stmt 0 view .LVU203
+ 683 00dc 5A08     		lsrs	r2, r3, #1
+ 684              	.LVL68:
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp = usartdiv & 0xFFF0U;
+ 685              		.loc 3 1648 27 view .LVU204
+ 686 00de 02EB4000 		add	r0, r2, r0, lsl #1
+ 687              	.LVL69:
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp = usartdiv & 0xFFF0U;
+ 688              		.loc 3 1648 27 view .LVU205
+ 689 00e2 B0FBF3F3 		udiv	r3, r0, r3
+ 690              	.LVL70:
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 691              		.loc 3 1649 5 is_stmt 1 view .LVU206
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 692              		.loc 3 1649 13 is_stmt 0 view .LVU207
+ 693 00e6 4FF6F072 		movw	r2, #65520
+ 694 00ea 1A40     		ands	r2, r2, r3
+ 695              	.LVL71:
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     USARTx->BRR = brrtemp;
+ 696              		.loc 3 1650 5 is_stmt 1 view .LVU208
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     USARTx->BRR = brrtemp;
+ 697              		.loc 3 1650 16 is_stmt 0 view .LVU209
+ 698 00ec C3F34203 		ubfx	r3, r3, #1, #3
+ 699              	.LVL72:
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****     USARTx->BRR = brrtemp;
+ 700              		.loc 3 1650 13 view .LVU210
+ 701 00f0 1343     		orrs	r3, r3, r2
+ 702              	.LVL73:
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+ 703              		.loc 3 1651 5 is_stmt 1 view .LVU211
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+ 704              		.loc 3 1651 17 is_stmt 0 view .LVU212
+ARM GAS  /tmp/cc1GpNf6.s 			page 82
+
+
+ 705 00f2 E360     		str	r3, [r4, #12]
+ 706              	.LVL74:
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+ 707              		.loc 3 1651 17 view .LVU213
+ 708 00f4 F0E7     		b	.L32
+ 709              	.LVL75:
+ 710              	.L33:
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h ****   }
+ 711              		.loc 3 1651 17 view .LVU214
+ 712              	.LBE108:
+ 713              	.LBE109:
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+ 714              		.loc 1 222 15 view .LVU215
+ 715 00f6 0120     		movs	r0, #1
+ 716              	.LVL76:
+ 717              	.L22:
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                            periphclk,
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                            USART_InitStruct->OverSampling,
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                            USART_InitStruct->BaudRate);
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       /* Check BRR is greater than or equal to 16d */
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+ 718              		.loc 1 320 7 is_stmt 1 view .LVU216
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   /* Endif (=> USART not in Disabled state => return ERROR) */
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   return (status);
+ 719              		.loc 1 325 3 view .LVU217
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** }
+ 720              		.loc 1 326 1 is_stmt 0 view .LVU218
+ 721 00f8 38BD     		pop	{r3, r4, r5, pc}
+ 722              	.LVL77:
+ 723              	.L35:
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+ 724              		.loc 1 222 15 view .LVU219
+ 725 00fa 0120     		movs	r0, #1
+ 726              	.LVL78:
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+ 727              		.loc 1 222 15 view .LVU220
+ 728 00fc FCE7     		b	.L22
+ 729              	.L49:
+ 730 00fe 00BF     		.align	2
+ 731              	.L48:
+ 732 0100 F369FFEF 		.word	-268473869
+ 733 0104 00100140 		.word	1073811456
+ 734 0108 00440040 		.word	1073759232
+ 735 010c 00480040 		.word	1073760256
+ 736 0110 004C0040 		.word	1073761280
+ 737 0114 00500040 		.word	1073762304
+ 738 0118 00140140 		.word	1073812480
+ 739 011c 00780040 		.word	1073772544
+ 740 0120 007C0040 		.word	1073773568
+ 741              		.cfi_endproc
+ 742              	.LFE543:
+ 744              		.section	.text.LL_USART_StructInit,"ax",%progbits
+ 745              		.align	1
+ARM GAS  /tmp/cc1GpNf6.s 			page 83
+
+
+ 746              		.global	LL_USART_StructInit
+ 747              		.syntax unified
+ 748              		.thumb
+ 749              		.thumb_func
+ 750              		.fpu fpv5-d16
+ 752              	LL_USART_StructInit:
+ 753              	.LVL79:
+ 754              	.LFB544:
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /**
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *                         whose fields will be set to default values.
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @retval None
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** {
+ 755              		.loc 1 336 1 is_stmt 1 view -0
+ 756              		.cfi_startproc
+ 757              		@ args = 0, pretend = 0, frame = 0
+ 758              		@ frame_needed = 0, uses_anonymous_args = 0
+ 759              		@ link register save eliminated.
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   /* Set USART_InitStruct fields to default values */
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   USART_InitStruct->BaudRate            = USART_DEFAULT_BAUDRATE;
+ 760              		.loc 1 338 3 view .LVU222
+ 761              		.loc 1 338 41 is_stmt 0 view .LVU223
+ 762 0000 4FF41653 		mov	r3, #9600
+ 763 0004 0360     		str	r3, [r0]
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
+ 764              		.loc 1 339 3 is_stmt 1 view .LVU224
+ 765              		.loc 1 339 41 is_stmt 0 view .LVU225
+ 766 0006 0023     		movs	r3, #0
+ 767 0008 4360     		str	r3, [r0, #4]
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
+ 768              		.loc 1 340 3 is_stmt 1 view .LVU226
+ 769              		.loc 1 340 41 is_stmt 0 view .LVU227
+ 770 000a 8360     		str	r3, [r0, #8]
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
+ 771              		.loc 1 341 3 is_stmt 1 view .LVU228
+ 772              		.loc 1 341 41 is_stmt 0 view .LVU229
+ 773 000c C360     		str	r3, [r0, #12]
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
+ 774              		.loc 1 342 3 is_stmt 1 view .LVU230
+ 775              		.loc 1 342 41 is_stmt 0 view .LVU231
+ 776 000e 0C22     		movs	r2, #12
+ 777 0010 0261     		str	r2, [r0, #16]
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+ 778              		.loc 1 343 3 is_stmt 1 view .LVU232
+ 779              		.loc 1 343 41 is_stmt 0 view .LVU233
+ 780 0012 4361     		str	r3, [r0, #20]
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
+ 781              		.loc 1 344 3 is_stmt 1 view .LVU234
+ 782              		.loc 1 344 41 is_stmt 0 view .LVU235
+ 783 0014 8361     		str	r3, [r0, #24]
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** }
+ 784              		.loc 1 345 1 view .LVU236
+ARM GAS  /tmp/cc1GpNf6.s 			page 84
+
+
+ 785 0016 7047     		bx	lr
+ 786              		.cfi_endproc
+ 787              	.LFE544:
+ 789              		.section	.text.LL_USART_ClockInit,"ax",%progbits
+ 790              		.align	1
+ 791              		.global	LL_USART_ClockInit
+ 792              		.syntax unified
+ 793              		.thumb
+ 794              		.thumb_func
+ 795              		.fpu fpv5-d16
+ 797              	LL_USART_ClockInit:
+ 798              	.LVL80:
+ 799              	.LFB545:
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /**
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @brief  Initialize USART Clock related settings according to the
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *         specified parameters in the USART_ClockInitStruct.
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @note   As some bits in USART configuration registers can only be written when
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled sta
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *         this function. Otherwise, ERROR result will be returned.
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @param  USARTx USART Instance
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *         that contains the Clock configuration information for the specified USART peripheral.
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @retval An ErrorStatus enumeration value:
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *          - SUCCESS: USART registers related to Clock settings are initialized according
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *                     to USART_ClockInitStruct content
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *          - ERROR: Problem occurred during USART Registers initialization
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockI
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** {
+ 800              		.loc 1 362 1 is_stmt 1 view -0
+ 801              		.cfi_startproc
+ 802              		@ args = 0, pretend = 0, frame = 0
+ 803              		@ frame_needed = 0, uses_anonymous_args = 0
+ 804              		@ link register save eliminated.
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   ErrorStatus status = SUCCESS;
+ 805              		.loc 1 363 3 view .LVU238
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   /* Check USART Instance and Clock signal output parameters */
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   assert_param(IS_UART_INSTANCE(USARTx));
+ 806              		.loc 1 366 3 view .LVU239
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+ 807              		.loc 1 367 3 view .LVU240
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   /* USART needs to be in disabled state, in order to be able to configure some bits in
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****      CRx registers */
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   if (LL_USART_IsEnabled(USARTx) == 0U)
+ 808              		.loc 1 371 3 view .LVU241
+ 809              	.LBB110:
+ 810              	.LBI110:
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 811              		.loc 3 585 26 view .LVU242
+ 812              	.LBB111:
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 813              		.loc 3 587 3 view .LVU243
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 814              		.loc 3 587 12 is_stmt 0 view .LVU244
+ARM GAS  /tmp/cc1GpNf6.s 			page 85
+
+
+ 815 0000 0368     		ldr	r3, [r0]
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 816              		.loc 3 587 73 view .LVU245
+ 817 0002 13F0010F 		tst	r3, #1
+ 818 0006 18D1     		bne	.L54
+ 819              	.LVL81:
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 820              		.loc 3 587 73 view .LVU246
+ 821              	.LBE111:
+ 822              	.LBE110:
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     /* If USART Clock signal is disabled */
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
+ 823              		.loc 1 374 5 is_stmt 1 view .LVU247
+ 824              		.loc 1 374 30 is_stmt 0 view .LVU248
+ 825 0008 0B68     		ldr	r3, [r1]
+ 826              		.loc 1 374 8 view .LVU249
+ 827 000a 2BB9     		cbnz	r3, .L53
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       /* Deactivate Clock signal delivery :
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****        * - Disable Clock Output:        USART_CR2_CLKEN cleared
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****        */
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       LL_USART_DisableSCLKOutput(USARTx);
+ 828              		.loc 1 379 7 is_stmt 1 view .LVU250
+ 829              	.LVL82:
+ 830              	.LBB112:
+ 831              	.LBI112:
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** {
+ 832              		.loc 3 1044 22 view .LVU251
+ 833              	.LBB113:
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** }
+ 834              		.loc 3 1046 3 view .LVU252
+ 835 000c 4368     		ldr	r3, [r0, #4]
+ 836 000e 23F40063 		bic	r3, r3, #2048
+ 837 0012 4360     		str	r3, [r0, #4]
+ 838              	.LBE113:
+ 839              	.LBE112:
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 840              		.loc 1 363 15 is_stmt 0 view .LVU253
+ 841 0014 0020     		movs	r0, #0
+ 842              	.LVL83:
+ 843              	.LBB115:
+ 844              	.LBB114:
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 845              		.loc 3 1047 1 view .LVU254
+ 846 0016 7047     		bx	lr
+ 847              	.LVL84:
+ 848              	.L53:
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 
+ 849              		.loc 3 1047 1 view .LVU255
+ 850              	.LBE114:
+ 851              	.LBE115:
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   ErrorStatus status = SUCCESS;
+ 852              		.loc 1 362 1 view .LVU256
+ 853 0018 10B4     		push	{r4}
+ 854              	.LCFI1:
+ 855              		.cfi_def_cfa_offset 4
+ARM GAS  /tmp/cc1GpNf6.s 			page 86
+
+
+ 856              		.cfi_offset 4, -4
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     else
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     {
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       /* Ensure USART instance is USART capable */
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       assert_param(IS_USART_INSTANCE(USARTx));
+ 857              		.loc 1 384 7 is_stmt 1 view .LVU257
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       /* Check clock related parameters */
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ 858              		.loc 1 387 7 view .LVU258
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ 859              		.loc 1 388 7 view .LVU259
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+ 860              		.loc 1 389 7 view .LVU260
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       /*---------------------------- USART CR2 Configuration -----------------------
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****        * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****        * - Enable Clock Output:         USART_CR2_CLKEN set
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****        * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->Cloc
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****        * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->Cloc
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****        * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->Last
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****        */
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****       MODIFY_REG(USARTx->CR2,
+ 861              		.loc 1 398 7 view .LVU261
+ 862 001a 4368     		ldr	r3, [r0, #4]
+ 863 001c 23F47063 		bic	r3, r3, #3840
+ 864 0020 4A68     		ldr	r2, [r1, #4]
+ 865 0022 8C68     		ldr	r4, [r1, #8]
+ 866 0024 2243     		orrs	r2, r2, r4
+ 867 0026 C968     		ldr	r1, [r1, #12]
+ 868              	.LVL85:
+ 869              		.loc 1 398 7 is_stmt 0 view .LVU262
+ 870 0028 0A43     		orrs	r2, r2, r1
+ 871 002a 1343     		orrs	r3, r3, r2
+ 872 002c 43F40063 		orr	r3, r3, #2048
+ 873 0030 4360     		str	r3, [r0, #4]
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 874              		.loc 1 363 15 view .LVU263
+ 875 0032 0020     		movs	r0, #0
+ 876              	.LVL86:
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                  USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                  USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                  USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     }
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   /* Else (USART not in Disabled state => return ERROR */
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   else
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   {
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****     status = ERROR;
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   return (status);
+ 877              		.loc 1 410 3 is_stmt 1 view .LVU264
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** }
+ 878              		.loc 1 411 1 is_stmt 0 view .LVU265
+ 879 0034 5DF8044B 		ldr	r4, [sp], #4
+ARM GAS  /tmp/cc1GpNf6.s 			page 87
+
+
+ 880              	.LCFI2:
+ 881              		.cfi_restore 4
+ 882              		.cfi_def_cfa_offset 0
+ 883 0038 7047     		bx	lr
+ 884              	.LVL87:
+ 885              	.L54:
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   }
+ 886              		.loc 1 407 12 view .LVU266
+ 887 003a 0120     		movs	r0, #1
+ 888              	.LVL88:
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** }
+ 889              		.loc 1 410 3 is_stmt 1 view .LVU267
+ 890              		.loc 1 411 1 is_stmt 0 view .LVU268
+ 891 003c 7047     		bx	lr
+ 892              		.cfi_endproc
+ 893              	.LFE545:
+ 895              		.section	.text.LL_USART_ClockStructInit,"ax",%progbits
+ 896              		.align	1
+ 897              		.global	LL_USART_ClockStructInit
+ 898              		.syntax unified
+ 899              		.thumb
+ 900              		.thumb_func
+ 901              		.fpu fpv5-d16
+ 903              	LL_USART_ClockStructInit:
+ 904              	.LVL89:
+ 905              	.LFB546:
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** 
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /**
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   *                              whose fields will be set to default values.
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   * @retval None
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   */
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** {
+ 906              		.loc 1 420 1 is_stmt 1 view -0
+ 907              		.cfi_startproc
+ 908              		@ args = 0, pretend = 0, frame = 0
+ 909              		@ frame_needed = 0, uses_anonymous_args = 0
+ 910              		@ link register save eliminated.
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   /* Set LL_USART_ClockInitStruct fields with default values */
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
+ 911              		.loc 1 422 3 view .LVU270
+ 912              		.loc 1 422 44 is_stmt 0 view .LVU271
+ 913 0000 0023     		movs	r3, #0
+ 914 0002 0360     		str	r3, [r0]
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when
+ 915              		.loc 1 423 3 is_stmt 1 view .LVU272
+ 916              		.loc 1 423 44 is_stmt 0 view .LVU273
+ 917 0004 4360     		str	r3, [r0, #4]
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                                                                   LL_USART_CLOCK_DI
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when
+ 918              		.loc 1 425 3 is_stmt 1 view .LVU274
+ 919              		.loc 1 425 44 is_stmt 0 view .LVU275
+ 920 0006 8360     		str	r3, [r0, #8]
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                                                                   LL_USART_CLOCK_DI
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****   USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when
+ARM GAS  /tmp/cc1GpNf6.s 			page 88
+
+
+ 921              		.loc 1 427 3 is_stmt 1 view .LVU276
+ 922              		.loc 1 427 44 is_stmt 0 view .LVU277
+ 923 0008 C360     		str	r3, [r0, #12]
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c ****                                                                                   LL_USART_CLOCK_DI
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** }
+ 924              		.loc 1 429 1 view .LVU278
+ 925 000a 7047     		bx	lr
+ 926              		.cfi_endproc
+ 927              	.LFE546:
+ 929              		.text
+ 930              	.Letext0:
+ 931              		.file 4 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 932              		.file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 933              		.file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ 934              		.file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+ARM GAS  /tmp/cc1GpNf6.s 			page 89
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_ll_usart.c
+     /tmp/cc1GpNf6.s:17     .text.LL_USART_DeInit:0000000000000000 $t
+     /tmp/cc1GpNf6.s:25     .text.LL_USART_DeInit:0000000000000000 LL_USART_DeInit
+     /tmp/cc1GpNf6.s:379    .text.LL_USART_DeInit:00000000000000f4 $d
+     /tmp/cc1GpNf6.s:393    .text.LL_USART_Init:0000000000000000 $t
+     /tmp/cc1GpNf6.s:400    .text.LL_USART_Init:0000000000000000 LL_USART_Init
+     /tmp/cc1GpNf6.s:732    .text.LL_USART_Init:0000000000000100 $d
+     /tmp/cc1GpNf6.s:745    .text.LL_USART_StructInit:0000000000000000 $t
+     /tmp/cc1GpNf6.s:752    .text.LL_USART_StructInit:0000000000000000 LL_USART_StructInit
+     /tmp/cc1GpNf6.s:790    .text.LL_USART_ClockInit:0000000000000000 $t
+     /tmp/cc1GpNf6.s:797    .text.LL_USART_ClockInit:0000000000000000 LL_USART_ClockInit
+     /tmp/cc1GpNf6.s:896    .text.LL_USART_ClockStructInit:0000000000000000 $t
+     /tmp/cc1GpNf6.s:903    .text.LL_USART_ClockStructInit:0000000000000000 LL_USART_ClockStructInit
+
+UNDEFINED SYMBOLS
+LL_RCC_GetUSARTClockFreq
+LL_RCC_GetUARTClockFreq
diff --git a/build/stm32f7xx_ll_usart.o b/build/stm32f7xx_ll_usart.o
new file mode 100644
index 0000000..2e8c512
Binary files /dev/null and b/build/stm32f7xx_ll_usart.o differ
diff --git a/build/stm32f7xx_ll_utils.d b/build/stm32f7xx_ll_utils.d
new file mode 100644
index 0000000..acf4b33
--- /dev/null
+++ b/build/stm32f7xx_ll_utils.d
@@ -0,0 +1,72 @@
+build/stm32f7xx_ll_utils.o: \
+ Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h:
diff --git a/build/stm32f7xx_ll_utils.lst b/build/stm32f7xx_ll_utils.lst
new file mode 100644
index 0000000..edc8121
--- /dev/null
+++ b/build/stm32f7xx_ll_utils.lst
@@ -0,0 +1,8361 @@
+ARM GAS  /tmp/ccLtUKRp.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"stm32f7xx_ll_utils.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.UTILS_GetPLLOutputFrequency,"ax",%progbits
+  17              		.align	1
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu fpv5-d16
+  24              	UTILS_GetPLLOutputFrequency:
+  25              	.LVL0:
+  26              	.LFB411:
+  27              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c"
+   1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @file    stm32f7xx_ll_utils.c
+   4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @brief   UTILS LL module driver.
+   6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Includes ------------------------------------------------------------------*/
+  19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #include "stm32f7xx_ll_utils.h"
+  20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #include "stm32f7xx_ll_rcc.h"
+  21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #include "stm32f7xx_ll_system.h"
+  22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #include "stm32f7xx_ll_pwr.h"
+  23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #ifdef  USE_FULL_ASSERT
+  24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #include "stm32_assert.h"
+  25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #else
+  26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define assert_param(expr) ((void)0U)
+  27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #endif /* USE_FULL_ASSERT */
+  28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+  29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup STM32F7xx_LL_Driver
+  30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @{
+  31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ARM GAS  /tmp/ccLtUKRp.s 			page 2
+
+
+  32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+  33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL
+  34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @{
+  35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+  36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+  37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Private types -------------------------------------------------------------*/
+  38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Private variables ---------------------------------------------------------*/
+  39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Private constants ---------------------------------------------------------*/
+  40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Constants
+  41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @{
+  42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+  43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_MAX_FREQUENCY_SCALE1  216000000U /*!< Maximum frequency for system clock at power sca
+  44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_MAX_FREQUENCY_SCALE2  180000000U       /*!< Maximum frequency for system clock at pow
+  45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_MAX_FREQUENCY_SCALE3  144000000U       /*!< Maximum frequency for system clock at pow
+  46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+  47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Defines used for PLL range */
+  48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_PLLVCO_INPUT_MIN         950000U       /*!< Frequency min for PLLVCO input, in Hz   *
+  49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_PLLVCO_INPUT_MAX        2100000U       /*!< Frequency max for PLLVCO input, in Hz   *
+  50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_PLLVCO_OUTPUT_MIN     100000000U       /*!< Frequency min for PLLVCO output, in Hz  *
+  51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_PLLVCO_OUTPUT_MAX     432000000U       /*!< Frequency max for PLLVCO output, in Hz  *
+  52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+  53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Defines used for HSE range */
+  54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   
+  55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_HSE_FREQUENCY_MAX     26000000U        /*!< Frequency max for HSE frequency, in Hz   
+  56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+  57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Defines used for FLASH latency according to HCLK Frequency */
+  58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in p
+  59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in p
+  60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in p
+  61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY4_FREQ  120000000U      /*!< HCLK frequency to set FLASH latency 4 in p
+  62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY5_FREQ  150000000U      /*!< HCLK frequency to set FLASH latency 5 in p
+  63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY6_FREQ  180000000U      /*!< HCLK frequency to set FLASH latency 6 in p
+  64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY7_FREQ  210000000U      /*!< HCLK frequency to set FLASH latency 7 in p
+  65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in p
+  66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in p
+  67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in p
+  68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE2_LATENCY4_FREQ  120000000U      /*!< HCLK frequency to set FLASH latency 4 in p
+  69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE2_LATENCY5_FREQ  150000000U      /*!< HCLK frequency to set FLASH latency 5 in p
+  70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in p
+  71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE3_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in p
+  72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE3_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in p
+  73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE3_LATENCY4_FREQ  120000000U      /*!< HCLK frequency to set FLASH latency 4 in p
+  74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+  75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @}
+  76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+  77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+  78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Private macros ------------------------------------------------------------*/
+  79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Macros
+  80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @{
+  81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+  82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
+  83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
+  84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
+  85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
+  86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
+  87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
+  88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+ARM GAS  /tmp/ccLtUKRp.s 			page 3
+
+
+  89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+  90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+  91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+  92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+  93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+  94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+  95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+  96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+  97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+  98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+  99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                       || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+ 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                       || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                       || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                       || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+ 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2)  \
+ 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_3)  \
+ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_4)  \
+ 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_5)  \
+ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_6)  \
+ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_7)  \
+ 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_8)  \
+ 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_9)  \
+ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
+ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
+ 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
+ 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
+ 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
+ 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
+ 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
+ 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
+ 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
+ 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
+ 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
+ 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
+ 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
+ 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
+ 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
+ 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
+ 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
+ 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
+ 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
+ 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
+ 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
+ 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
+ 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
+ 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
+ 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
+ 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
+ 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
+ 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
+ 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
+ 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
+ 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
+ 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
+ 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
+ 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
+ARM GAS  /tmp/ccLtUKRp.s 			page 4
+
+
+ 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
+ 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
+ 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
+ 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
+ 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
+ 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
+ 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
+ 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
+ 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
+ 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
+ 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
+ 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
+ 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
+ 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
+ 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
+ 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
+ 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
+ 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
+ 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
+ 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
+ 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((50 <= (__VALUE__)) && ((__VALUE__) <= 432))
+ 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
+ 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
+ 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
+ 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
+ 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE_
+ 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE
+ 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTA
+ 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                               (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTA
+ 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                               ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
+ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+ 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+ 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && (
+ 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @}
+ 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Private function prototypes -----------------------------------------------*/
+ 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+ 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @{
+ 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+ 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                                LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+ 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDe
+ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static ErrorStatus UTILS_PLL_IsBusy(void);
+ 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @}
+ 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Exported functions --------------------------------------------------------*/
+ 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL_Exported_Functions
+ARM GAS  /tmp/ccLtUKRp.s 			page 5
+
+
+ 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @{
+ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL_EF_DELAY
+ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @{
+ 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
+ 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
+ 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+ 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  HCLKFrequency HCLK frequency in Hz
+ 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_Get
+ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @retval None
+ 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** void LL_Init1msTick(uint32_t HCLKFrequency)
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** {
+ 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Use frequency provided in argument */
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   LL_InitTick(HCLKFrequency, 1000U);
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @brief  This function provides accurate delay (in milliseconds) based
+ 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         on SysTick counter flag
+ 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
+ 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         and use rather osDelay service.
+ 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+ 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         will configure Systick to 1ms
+ 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  Delay specifies the delay time length, in milliseconds.
+ 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @retval None
+ 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** void LL_mDelay(uint32_t Delay)
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** {
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
+ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Add this code to indicate that local variable is not used */
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ((void)tmp);
+ 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Add a period to guaranty minimum wait */
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   if(Delay < LL_MAX_DELAY)
+ 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     Delay++;
+ 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   while (Delay)
+ 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       Delay--;
+ 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @}
+ 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_EF_SYSTEM
+ARM GAS  /tmp/ccLtUKRp.s 			page 6
+
+
+ 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *  @brief    System Configuration functions
+ 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *
+ 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   @verbatim
+ 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****  ===============================================================================
+ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****            ##### System Configuration functions #####
+ 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****  ===============================================================================
+ 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     [..]
+ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****          System, AHB and APB buses clocks configuration
+ 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****          (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 216000000 Hz.
+ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   @endverbatim
+ 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   @internal
+ 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              Depending on the device voltage range, the maximum frequency should be
+ 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              adapted accordingly:
+ 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) +--------------------------------------------------------------------------------
+ 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |  Wait states   |                           HCLK clock frequency (MHz)          
+ 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |                |---------------------------------------------------------------
+ 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |  (Latency)     |   voltage range   |   voltage range   |   voltage range   |   
+ 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |                |    2.7V - 3.6V    |    2.4V - 2.7V    |    2.1V - 2.7V    |   
+ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |----------------|-------------------|-------------------|-------------------|---
+ 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |0WS(1CPU cycle) |   0 < HCLK <= 30  |   0 < HCLK <= 24  |   0 < HCLK <= 22  |   
+ 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |----------------|-------------------|-------------------|-------------------|---
+ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |1WS(2CPU cycle) |  30 < HCLK <= 60  |  24 < HCLK <= 48  |  22 < HCLK <= 44  |  2
+ 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |----------------|-------------------|-------------------|-------------------|---
+ 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |2WS(3CPU cycle) |  60 < HCLK <= 90  |  48 < HCLK <= 72  |  44 < HCLK <= 66  |  4
+ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |----------------|-------------------|-------------------|-------------------|---
+ 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |3WS(4CPU cycle) |  90 < HCLK <= 120 |  72 < HCLK <= 96  |  66 < HCLK <= 88  |  6
+ 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |----------------|-------------------|-------------------|-------------------|---
+ 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |4WS(5CPU cycle) | 120 < HCLK <= 150 |  96 < HCLK <= 120 |  88 < HCLK <= 110 |  8
+ 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |----------------|-------------------|-------------------|-------------------|---
+ 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |5WS(6CPU cycle) | 150 < HCLK <= 180 | 120 < HCLK <= 144 | 110 < HCLK <= 132 | 10
+ 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |----------------|-------------------|-------------------|-------------------|---
+ 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |6WS(7CPU cycle) | 180 < HCLK <= 210 | 144 < HCLK <= 168 | 132 < HCLK <= 154 | 12
+ 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |----------------|-------------------|-------------------|-------------------|---
+ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |7WS(8CPU cycle) | 210 < HCLK <= 216 | 168 < HCLK <= 192 | 154 < HCLK <= 176 | 14
+ 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |----------------|-------------------|-------------------|-------------------|---
+ 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |8WS(9CPU cycle) |        --         | 192 < HCLK <= 216 | 176 < HCLK <= 198 | 16
+ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |----------------|-------------------|-------------------|-------------------|---
+ 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) |9WS(10CPU cycle)|        --         |         --        | 198 < HCLK <= 216 |   
+ 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****              (++) +--------------------------------------------------------------------------------
+ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   @endinternal
+ 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @{
+ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @brief  This function sets directly SystemCoreClock CMSIS variable.
+ 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
+ 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @retval None
+ 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** {
+ 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* HCLK clock frequency */
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   SystemCoreClock = HCLKFrequency;
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ARM GAS  /tmp/ccLtUKRp.s 			page 7
+
+
+ 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @brief  Update number of Flash wait states in line with new frequency and current
+ 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****             voltage range.
+ 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @note   This Function support ONLY devices with supply voltage (voltage range) between 2.7V and
+ 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  HCLK_Frequency  HCLK frequency
+ 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @retval An ErrorStatus enumeration value:
+ 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *          - SUCCESS: Latency has been modified
+ 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *          - ERROR: Latency cannot be modified
+ 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** {
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t timeout;
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t getlatency;
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Frequency cannot be equal to 0 */
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   if(HCLK_Frequency == 0U)
+ 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     status = ERROR;
+ 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   else
+ 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+ 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       if(LL_PWR_IsEnabledOverDriveMode() != 0U)
+ 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ)
+ 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           {
+ 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****             /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****             latency = LL_FLASH_LATENCY_7;
+ 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           }
+ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */
+ 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           {
+ 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****             /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****             latency = LL_FLASH_LATENCY_6;
+ 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           }
+ 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         }
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0))
+ 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         latency = LL_FLASH_LATENCY_5;
+ 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0))
+ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         latency = LL_FLASH_LATENCY_4;
+ 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0))
+ 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         latency = LL_FLASH_LATENCY_3;
+ 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0))
+ 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         latency = LL_FLASH_LATENCY_2;
+ARM GAS  /tmp/ccLtUKRp.s 			page 8
+
+
+ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else
+ 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0))
+ 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           latency = LL_FLASH_LATENCY_1;
+ 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         }
+ 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */
+ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
+ 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)
+ 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cyc
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         latency = LL_FLASH_LATENCY_5;
+ 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)
+ 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         latency = LL_FLASH_LATENCY_4;
+ 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
+ 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         latency = LL_FLASH_LATENCY_3;
+ 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
+ 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         latency = LL_FLASH_LATENCY_2;
+ 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else
+ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
+ 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           latency = LL_FLASH_LATENCY_1;
+ 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         }
+ 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
+ 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     else /* Scale 3 */
+ 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ)
+ 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         latency = LL_FLASH_LATENCY_4;
+ 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)
+ 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         latency = LL_FLASH_LATENCY_3;
+ 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)
+ 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ARM GAS  /tmp/ccLtUKRp.s 			page 9
+
+
+ 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         latency = LL_FLASH_LATENCY_2;
+ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else
+ 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)
+ 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           latency = LL_FLASH_LATENCY_1;
+ 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         }
+ 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */
+ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     if (status != ERROR)
+ 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       LL_FLASH_SetLatency(latency);
+ 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       /* Check that the new number of wait states is taken into account to access the Flash
+ 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****            memory by reading the FLASH_ACR register */
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       timeout = 2;
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       do
+ 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       /* Wait for Flash latency to be updated */
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       getlatency = LL_FLASH_GetLatency();
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       timeout--;
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       } while ((getlatency != latency) && (timeout > 0));
+ 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       if(getlatency != latency)
+ 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         status = ERROR;
+ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else
+ 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         status = SUCCESS;
+ 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   return status;
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @brief  This function configures system clock at maximum frequency with HSI as clock source of 
+ 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @note   The application need to ensure that PLL is disabled.
+ 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @note   Function is based on the following formula:
+ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
+ 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz (PLLVCO_input =
+ 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output 
+ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         - PLLP: ensure that max frequency at 216000000 Hz is reach (PLLVCO_output / PLLP)
+ 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *                             the configuration information for the PLL.
+ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *                             the configuration information for the BUS prescalers.
+ 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @retval An ErrorStatus enumeration value:
+ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *          - SUCCESS: Max frequency configuration done
+ 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *          - ERROR: Max frequency configuration not done
+ 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ARM GAS  /tmp/ccLtUKRp.s 			page 10
+
+
+ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** {
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t pllfreq = 0U;
+ 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Check if one of the PLL is enabled */
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   if(UTILS_PLL_IsBusy() == SUCCESS)
+ 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Calculate the new PLL output frequency */
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Enable HSI if not enabled */
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     if(LL_RCC_HSI_IsReady() != 1U)
+ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       LL_RCC_HSI_Enable();
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       while (LL_RCC_HSI_IsReady() != 1U)
+ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* Wait for HSI ready */
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Configure PLL */
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruc
+ 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                 UTILS_PLLInitStruct->PLLP);
+ 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Enable PLL and switch system clock to PLL */
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   else
+ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Current PLL configuration cannot be modified */
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     status = ERROR;
+ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   return status;
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @brief  This function configures system clock with HSE as clock source of the PLL
+ 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @note   The application need to ensure that PLL is disabled.
+ 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @note   Function is based on the following formula:
+ 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
+ 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input 
+ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output 
+ 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         - PLLP: ensure that max frequency at 216000000 Hz is reached (PLLVCO_output / PLLP)
+ 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
+ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  HSEBypass This parameter can be one of the following values:
+ 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         @arg @ref LL_UTILS_HSEBYPASS_ON
+ 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
+ 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *                             the configuration information for the PLL.
+ 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *                             the configuration information for the BUS prescalers.
+ 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @retval An ErrorStatus enumeration value:
+ 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *          - SUCCESS: Max frequency configuration done
+ 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *          - ERROR: Max frequency configuration not done
+ARM GAS  /tmp/ccLtUKRp.s 			page 11
+
+
+ 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_Clk
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** {
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t pllfreq = 0U;
+ 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Check the parameters */
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Check if one of the PLL is enabled */
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   if(UTILS_PLL_IsBusy() == SUCCESS)
+ 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Calculate the new PLL output frequency */
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+ 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Enable HSE if not enabled */
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     if(LL_RCC_HSE_IsReady() != 1U)
+ 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       /* Check if need to enable HSE bypass feature or not */
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
+ 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         LL_RCC_HSE_EnableBypass();
+ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       else
+ 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         LL_RCC_HSE_DisableBypass();
+ 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       /* Enable HSE */
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       LL_RCC_HSE_Enable();
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       while (LL_RCC_HSE_IsReady() != 1U)
+ 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         /* Wait for HSE ready */
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Configure PLL */
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruc
+ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                 UTILS_PLLInitStruct->PLLP);
+ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Enable PLL and switch system clock to PLL */
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   else
+ 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Current PLL configuration cannot be modified */
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     status = ERROR;
+ 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   return status;
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @}
+ 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ARM GAS  /tmp/ccLtUKRp.s 			page 12
+
+
+ 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @}
+ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Functions
+ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @{
+ 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @brief  Function to check that PLL can be modified
+ 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
+ 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *                             the configuration information for the PLL.
+ 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @retval PLL output frequency (in Hz)
+ 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *U
+ 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** {
+  28              		.loc 1 618 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+ 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t pllfreq = 0U;
+  33              		.loc 1 619 3 view .LVU1
+ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Check the parameters */
+ 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+  34              		.loc 1 622 3 view .LVU2
+ 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+  35              		.loc 1 623 3 view .LVU3
+ 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
+  36              		.loc 1 624 3 view .LVU4
+ 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   
+ 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Check different PLL parameters according to RM                          */
+ 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /*  - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz.   */
+ 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM
+  37              		.loc 1 628 3 view .LVU5
+  38              		.loc 1 628 54 is_stmt 0 view .LVU6
+  39 0000 0B68     		ldr	r3, [r1]
+  40              		.loc 1 628 61 view .LVU7
+  41 0002 03F03F03 		and	r3, r3, #63
+  42              		.loc 1 628 11 view .LVU8
+  43 0006 B0FBF3F0 		udiv	r0, r0, r3
+  44              	.LVL1:
+ 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
+  45              		.loc 1 629 3 is_stmt 1 view .LVU9
+ 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /*  - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz.*/
+ 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
+  46              		.loc 1 632 3 view .LVU10
+  47              		.loc 1 632 43 is_stmt 0 view .LVU11
+  48 000a 4B68     		ldr	r3, [r1, #4]
+  49              		.loc 1 632 50 view .LVU12
+  50 000c C3F30803 		ubfx	r3, r3, #0, #9
+  51              		.loc 1 632 11 view .LVU13
+  52 0010 03FB00F0 		mul	r0, r3, r0
+  53              	.LVL2:
+ARM GAS  /tmp/ccLtUKRp.s 			page 13
+
+
+ 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
+  54              		.loc 1 633 3 is_stmt 1 view .LVU14
+ 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   
+ 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /*  - PLLP: ensure that max frequency at 216000000 Hz is reached     */
+ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
+  55              		.loc 1 636 3 view .LVU15
+  56              		.loc 1 636 52 is_stmt 0 view .LVU16
+  57 0014 4B89     		ldrh	r3, [r1, #10]
+  58              		.loc 1 636 77 view .LVU17
+  59 0016 0133     		adds	r3, r3, #1
+  60              		.loc 1 636 82 view .LVU18
+  61 0018 5B00     		lsls	r3, r3, #1
+  62              	.LVL3:
+ 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+  63              		.loc 1 637 3 is_stmt 1 view .LVU19
+ 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   return pllfreq;
+  64              		.loc 1 639 3 view .LVU20
+ 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+  65              		.loc 1 640 1 is_stmt 0 view .LVU21
+  66 001a B0FBF3F0 		udiv	r0, r0, r3
+  67              	.LVL4:
+  68              		.loc 1 640 1 view .LVU22
+  69 001e 7047     		bx	lr
+  70              		.cfi_endproc
+  71              	.LFE411:
+  73              		.section	.text.UTILS_PLL_IsBusy,"ax",%progbits
+  74              		.align	1
+  75              		.syntax unified
+  76              		.thumb
+  77              		.thumb_func
+  78              		.fpu fpv5-d16
+  80              	UTILS_PLL_IsBusy:
+  81              	.LFB412:
+ 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @brief  Function to check that PLL can be modified
+ 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @retval An ErrorStatus enumeration value:
+ 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *          - SUCCESS: PLL modification can be done
+ 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *          - ERROR: PLL is busy
+ 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static ErrorStatus UTILS_PLL_IsBusy(void)
+ 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** {
+  82              		.loc 1 649 1 is_stmt 1 view -0
+  83              		.cfi_startproc
+  84              		@ args = 0, pretend = 0, frame = 0
+  85              		@ frame_needed = 0, uses_anonymous_args = 0
+  86              		@ link register save eliminated.
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+  87              		.loc 1 650 3 view .LVU24
+  88              	.LVL5:
+ 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Check if PLL is busy*/
+ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   if(LL_RCC_PLL_IsReady() != 0U)
+  89              		.loc 1 653 3 view .LVU25
+  90              	.LBB54:
+  91              	.LBI54:
+ARM GAS  /tmp/ccLtUKRp.s 			page 14
+
+
+  92              		.file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @file    stm32f7xx_ll_rcc.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief   Header file of RCC LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * This software is licensed under terms that can be found in the LICENSE file in
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   ******************************************************************************
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #ifndef __STM32F7xx_LL_RCC_H
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __STM32F7xx_LL_RCC_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #ifdef __cplusplus
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** extern "C" {
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Includes ------------------------------------------------------------------*/
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #include "stm32f7xx.h"
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @addtogroup STM32F7xx_LL_Driver
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC)
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL RCC
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private types -------------------------------------------------------------*/
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private variables ---------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private constants ---------------------------------------------------------*/
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private macros ------------------------------------------------------------*/
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER)
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ARM GAS  /tmp/ccLtUKRp.s 			page 15
+
+
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /*USE_FULL_LL_DRIVER*/
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported types ------------------------------------------------------------*/
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER)
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  RCC Clocks Frequency Structure
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** typedef struct
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } LL_RCC_ClocksTypeDef;
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported constants --------------------------------------------------------*/
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief    Defines used to adapt values of different oscillators
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note     These values could be modified in the user environment according to 
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *           HW set-up.
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined  (HSE_VALUE)
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* HSE_VALUE */
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined  (HSI_VALUE)
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* HSI_VALUE */
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined  (LSE_VALUE)
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LSE_VALUE */
+ARM GAS  /tmp/ccLtUKRp.s 			page 16
+
+
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined  (LSI_VALUE)
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LSI_VALUE */
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined  (EXTERNAL_CLOCK_VALUE)
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_CLOCK_VALUE */
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_SAI1_CLOCK_VALUE    48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_SAI2_CLOCK_VALUE    48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief    Flags defines which can be used with LL_RCC_WriteReg function
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYC             RCC_CIR_PLLI2SRDYC  /*!< PLLI2S Ready Interrupt Clear */
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYC             RCC_CIR_PLLSAIRDYC  /*!< PLLSAI Ready Interrupt Clear */
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt 
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief    Flags defines which can be used with LL_RCC_ReadReg function
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYF             RCC_CIR_PLLI2SRDYF  /*!< PLLI2S Ready Interrupt flag */
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYF             RCC_CIR_PLLSAIRDYF  /*!< PLLSAI Ready Interrupt flag */
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF        /*!< Clock Security System Interrupt 
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_PORRSTF                 RCC_CSR_PORRSTF    /*!< POR/PDR reset flag */
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag 
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ARM GAS  /tmp/ccLtUKRp.s 			page 17
+
+
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_IT IT Defines
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYIE            RCC_CIR_PLLI2SRDYIE   /*!< PLLI2S Ready Interrupt Enable 
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYIE            RCC_CIR_PLLSAIRDYIE   /*!< PLLSAI Ready Interrupt Enable 
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_LOW                0x00000000U             /*!< Xtal mode lower driving cap
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium high drivi
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium low drivin
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving ca
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
+ARM GAS  /tmp/ccLtUKRp.s 			page 18
+
+
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI              (uint32_t)(RCC_CFGR_MCO1|0x00000000U)                   
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U))      
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U))      
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)(RCC_CFGR_MCO2|0x00000000U)                   
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_PLLI2S           (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U))      
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U))      
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_1                  (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U)                
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_2                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U))
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_3                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFG
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_4                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFG
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_5                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U))  
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_1                  (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U)                
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_2                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U))
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_3                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFG
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_4                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFG
+ARM GAS  /tmp/ccLtUKRp.s 			page 19
+
+
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_5                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U))  
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_NOCLOCK                  0x00000000U             /*!< HSE not divided */
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_2                RCC_CFGR_RTCPRE_1       /*!< HSE clock divided by 2 */
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_3                (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE cl
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_4                RCC_CFGR_RTCPRE_2       /*!< HSE clock divided by 4 */
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_5                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE cl
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_6                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE cl
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_7                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_8                RCC_CFGR_RTCPRE_3       /*!< HSE clock divided by 8 */
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_9                (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE cl
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_10               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE cl
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_11               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_12               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE cl
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_13               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_14               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_15               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_16               RCC_CFGR_RTCPRE_4       /*!< HSE clock divided by 16 */
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_17               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)       /*!< HSE cl
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_18               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)       /*!< HSE cl
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_19               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_20               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)       /*!< HSE cl
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_21               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_22               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_23               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_24               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)       /*!< HSE cl
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_25               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_26               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_27               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_28               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_29               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_30               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_31               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER)
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for th
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be pro
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ARM GAS  /tmp/ccLtUKRp.s 			page 20
+
+
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_PCLK2      (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | 0x00000000U
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | 0x00000000U
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | 0x00000000U
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_PCLK2      (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | 0x00000000U
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_UARTx_CLKSOURCE  Peripheral UART clock source selection
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | 0x00000000U) 
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | 0x00000000U) 
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | 0x00000000U) 
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_PCLK1      (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | 0x00000000U) 
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_SYSCLK     (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_HSI        (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_LSE        (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C1SEL|0x00000000U) /*!< PCLK1 
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_0 
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_1 
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C2SEL|0x00000000U) /*!< PCLK1 
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_0 
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_1 
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C3SEL|0x00000000U) /*!< PCLK1 
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_0 
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_1 
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(I2C4)
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_PCLK1        (uint32_t)(RCC_DCKCFGR2_I2C4SEL|0x00000000U) /*!< PCLK1 
+ARM GAS  /tmp/ccLtUKRp.s 			page 21
+
+
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_SYSCLK       (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_0 
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_HSI          (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_1 
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* I2C4 */
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1       0x00000000U                 /*!< PCLK1 clock used as LP
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSI         RCC_DCKCFGR2_LPTIM1SEL_0    /*!< LSI oscillator clock u
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_HSI         RCC_DCKCFGR2_LPTIM1SEL_1    /*!< HSI oscillator clock u
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSE         (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTI
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR1_SAI1SEL | 0x00000000U)          
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PIN          (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLSRC       (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL 
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR1_SAI2SEL | 0x00000000U)          
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PIN          (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLSRC       (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL 
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE  Peripheral SDMMC clock source selection
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK       (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | 0x00000000U)    
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK         (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | (RCC_DCKCFGR2_SD
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SDMMC2)
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK       (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | 0x00000000U)    
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK         (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | (RCC_DCKCFGR2_SD
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SDMMC2 */
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_PLL          0x00000000U            /*!< PLL clock used as RNG clock s
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_PLLSAI       RCC_DCKCFGR2_CK48MSEL  /*!< PLLSAI clock used as RNG cloc
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ARM GAS  /tmp/ccLtUKRp.s 			page 22
+
+
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL          0x00000000U            /*!< PLL clock used as USB clock s
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLLSAI       RCC_DCKCFGR2_CK48MSEL  /*!< PLLSAI1 clock used as USB clo
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE_PHY          0x00000000U           /*!< DSI-PHY clock used as DSI byte
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE_PLL          RCC_DCKCFGR2_DSISEL   /*!< PLL clock used as DSI byte lan
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC)
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_LSE               0x00000000U                /*!< LSE oscillator clock
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488        RCC_DCKCFGR2_CECSEL        /*!< HSI oscillator clock
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE  Peripheral I2S clock source selection
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PLLI2S           0x00000000U                /*!< I2S oscillator clock
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PIN              RCC_CFGR_I2SSRC            /*!< External pin clock u
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE  Peripheral 48Mhz domain clock source selection
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE_PLL             0x00000000U                /*!< PLL oscillator clock
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE_PLLSAI          RCC_DCKCFGR2_CK48MSEL      /*!< PLLSAI oscillator cl
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0)
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE  Peripheral DFSDM Audio clock source selection
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1     0x00000000U                /*!< SAI1 clock used as D
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2     RCC_DCKCFGR1_ADFSDM1SEL    /*!< SAI2 clock used as D
+ARM GAS  /tmp/ccLtUKRp.s 			page 23
+
+
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE  Peripheral DFSDM clock source selection
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as 
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         RCC_DCKCFGR1_DFSDM1SEL     /*!< System clock used as
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USARTx  Peripheral USART get clock source
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE            RCC_DCKCFGR2_USART1SEL /*!< USART1 Clock source selectio
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE            RCC_DCKCFGR2_USART2SEL /*!< USART2 Clock source selectio
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE            RCC_DCKCFGR2_USART3SEL /*!< USART3 Clock source selectio
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE            RCC_DCKCFGR2_USART6SEL /*!< USART6 Clock source selectio
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_UARTx  Peripheral UART get clock source
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE             RCC_DCKCFGR2_UART4SEL /*!< UART4 Clock source selection 
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE             RCC_DCKCFGR2_UART5SEL /*!< UART5 Clock source selection 
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE             RCC_DCKCFGR2_UART7SEL /*!< UART7 Clock source selection 
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE             RCC_DCKCFGR2_UART8SEL /*!< UART8 Clock source selection 
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2Cx  Peripheral I2C get clock source
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE              RCC_DCKCFGR2_I2C1SEL  /*!< I2C1 Clock source selection *
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE              RCC_DCKCFGR2_I2C2SEL  /*!< I2C2 Clock source selection *
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE              RCC_DCKCFGR2_I2C3SEL  /*!< I2C3 Clock source selection *
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(I2C4)
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE              RCC_DCKCFGR2_I2C4SEL  /*!< I2C4 Clock source selection *
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* I2C4 */
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1  Peripheral LPTIM get clock source
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE            RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selectio
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ARM GAS  /tmp/ccLtUKRp.s 			page 24
+
+
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE              RCC_DCKCFGR1_SAI1SEL /*!< SAI1 Clock source selection */
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE              RCC_DCKCFGR1_SAI2SEL /*!< SAI2 Clock source selection */
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SDMMCx  Peripheral SDMMC get clock source
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE            RCC_DCKCFGR2_SDMMC1SEL /*!< SDMMC1 Clock source selectio
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SDMMC2)
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE            RCC_DCKCFGR2_SDMMC2SEL /*!< SDMMC2 Clock source selectio
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SDMMC2 */
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CK48M  Peripheral CK48M get clock source
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source sel
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE               RCC_DCKCFGR2_CK48MSEL /*!< RNG Clock source selection */
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE               RCC_DCKCFGR2_CK48MSEL /*!< USB Clock source selection */
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC)
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC  Peripheral CEC get clock source
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE               RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2S1  Peripheral I2S get clock source
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ARM GAS  /tmp/ccLtUKRp.s 			page 25
+
+
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE              RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0)
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM_AUDIO  Peripheral DFSDM Audio get clock source
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE      RCC_DCKCFGR1_ADFSDM1SEL /*!< DFSDM Audio Clock source se
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE            RCC_DCKCFGR1_DFSDM1SEL /*!< DFSDM Clock source selection
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE               RCC_DCKCFGR2_DSISEL /*!< DSI Clock source selection */
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(LTDC)
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LTDC  Peripheral LTDC get clock source
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LTDC_CLKSOURCE              RCC_DCKCFGR1_PLLSAIDIVR /*!< LTDC Clock source selection
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LTDC */
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX)
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SPDIFRX  Peripheral SPDIFRX get clock source
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPDIFRX1_CLKSOURCE           RCC_PLLI2SCFGR_PLLI2SP /*!< SPDIFRX Clock source select
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U             /*!< No clock used as RTC clock 
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used a
+ARM GAS  /tmp/ccLtUKRp.s 			page 26
+
+
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used a
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_HSE           RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divide
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_TIM_PRESCALER_TWICE          0x00000000U                  /*!< Timers clock to twice
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_TIM_PRESCALER_FOUR_TIMES     RCC_DCKCFGR1_TIMPRE          /*!< Timers clock to four 
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLI2S and PLLSAI entry clock source
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL e
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLM_DIV  PLL, PLLI2S and PLLSAI division factor
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI divisio
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_4                  (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI divisio
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI divisio
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_9                  (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_10                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_11                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_12                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_13                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_14                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_15                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_16                 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI divisio
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_17                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_18                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_19                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_20                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_21                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_22                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_23                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_24                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_25                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_26                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_27                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_28                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_29                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_30                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_31                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ARM GAS  /tmp/ccLtUKRp.s 			page 27
+
+
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_32                 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI divisio
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_33                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_34                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_35                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_36                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_37                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_38                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_39                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_40                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_41                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_42                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_43                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_44                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_45                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_46                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_47                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_48                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_49                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_50                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_51                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_52                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_53                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_54                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_55                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_56                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_57                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_58                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_59                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_60                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_61                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_62                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_63                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLCFGR_PLLR)
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_2                  (RCC_PLLCFGR_PLLR_1)                     /*!< Main PLL d
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_3                  (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL d
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_2)                     /*!< Main PLL d
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_5                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL d
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)  /*!< Main PLL d
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_7                  (RCC_PLLCFGR_PLLR)                       /*!< Main PLL d
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLCFGR_PLLR */
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_2                  0x00000000U            /*!< Main PLL division factor for
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_4                  RCC_PLLCFGR_PLLP_0     /*!< Main PLL division factor for
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_6                  RCC_PLLCFGR_PLLP_1     /*!< Main PLL division factor for
+ARM GAS  /tmp/ccLtUKRp.s 			page 28
+
+
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)   /*!< Main PL
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_2                  RCC_PLLCFGR_PLLQ_1                      /*!< Main PLL di
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_3                  (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_4                  RCC_PLLCFGR_PLLQ_2                      /*!< Main PLL di
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_5                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL di
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_7                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_8                  RCC_PLLCFGR_PLLQ_3                      /*!< Main PLL di
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_9                  (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_10                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL di
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_11                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_12                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL di
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_13                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_14                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_15                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_SPRE_SEL  PLL Spread Spectrum Selection
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPREAD_SELECT_CENTER        0x00000000U                   /*!< PLL center spread spe
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPREAD_SELECT_DOWN          RCC_SSCGR_SPREADSEL           /*!< PLL down spread spect
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SQ  PLLI2SQ division factor (PLLI2SQ)
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_2              RCC_PLLI2SCFGR_PLLI2SQ_1        /*!< PLLI2S division fact
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_3              (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)    
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_4              RCC_PLLI2SCFGR_PLLI2SQ_2        /*!< PLLI2S division fact
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_5              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)    
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_6              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)    
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_7              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RC
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_8              RCC_PLLI2SCFGR_PLLI2SQ_3        /*!< PLLI2S division fact
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_9              (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0)    
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_10             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1)    
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_11             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RC
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_12             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2)    
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_13             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_14             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_15             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SDIVQ  PLLI2SDIVQ division factor (PLLI2SDIVQ)
+ARM GAS  /tmp/ccLtUKRp.s 			page 29
+
+
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_1           0x00000000U                        /*!< PLLI2S division f
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_2           RCC_DCKCFGR1_PLLI2SDIVQ_0          /*!< PLLI2S division f
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_3           RCC_DCKCFGR1_PLLI2SDIVQ_1          /*!< PLLI2S division f
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_4           (RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0)  
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_5           RCC_DCKCFGR1_PLLI2SDIVQ_2          /*!< PLLI2S division f
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_6           (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0)  
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_7           (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1)  
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_8           (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | 
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_9           RCC_DCKCFGR1_PLLI2SDIVQ_3          /*!< PLLI2S division f
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_10          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0)  
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_11          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1)  
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_12          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | 
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_13          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2)  
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_14          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_15          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_16          (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_17          RCC_DCKCFGR1_PLLI2SDIVQ_4          /*!< PLLI2S division f
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_18          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_0)  
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_19          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1)  
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_20          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | 
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_21          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2)  
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_22          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_23          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_24          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | 
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_25          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3)  
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_26          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_27          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_28          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_29          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_30          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_31          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_32          (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | 
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SR  PLLI2SR division factor (PLLI2SR)
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_2              RCC_PLLI2SCFGR_PLLI2SR_1                                 
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_3              (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)    
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_4              RCC_PLLI2SCFGR_PLLI2SR_2                                 
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_5              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0)    
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_6              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1)    
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_7              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RC
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLI2SCFGR_PLLI2SP)
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SP  PLLI2SP division factor (PLLI2SP)
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_2              0x00000000U            /*!< PLLI2S division factor for PL
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_4              RCC_PLLI2SCFGR_PLLI2SP_0        /*!< PLLI2S division fact
+ARM GAS  /tmp/ccLtUKRp.s 			page 30
+
+
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_6              RCC_PLLI2SCFGR_PLLI2SP_1        /*!< PLLI2S division fact
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_8              (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0)    
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLI2SCFGR_PLLI2SP */
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIQ  PLLSAIQ division factor (PLLSAIQ)
+ 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_2              RCC_PLLSAICFGR_PLLSAIQ_1        /*!< PLLSAI division fact
+ 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_3              (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)    
+ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_4              RCC_PLLSAICFGR_PLLSAIQ_2        /*!< PLLSAI division fact
+ 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_5              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)    
+ 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_6              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)    
+ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_7              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RC
+ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_8              RCC_PLLSAICFGR_PLLSAIQ_3        /*!< PLLSAI division fact
+ 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_9              (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0)    
+ 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_10             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1)    
+ 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_11             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RC
+ 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_12             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2)    
+ 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_13             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC
+ 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_14             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC
+ 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_15             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC
+ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIDIVQ  PLLSAIDIVQ division factor (PLLSAIDIVQ)
+ 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_1           0x00000000U               /*!< PLLSAI division factor for
+ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_2           RCC_DCKCFGR1_PLLSAIDIVQ_0          /*!< PLLSAI division f
+ 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_3           RCC_DCKCFGR1_PLLSAIDIVQ_1          /*!< PLLSAI division f
+ 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_4           (RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0)  
+ 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_5           RCC_DCKCFGR1_PLLSAIDIVQ_2          /*!< PLLSAI division f
+ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_6           (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0)  
+ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_7           (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1)  
+ 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_8           (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | 
+ 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_9           RCC_DCKCFGR1_PLLSAIDIVQ_3          /*!< PLLSAI division f
+ 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_10          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0)  
+ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_11          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1)  
+ 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_12          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | 
+ 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_13          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2)  
+ 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_14          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_15          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_16          (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_17          RCC_DCKCFGR1_PLLSAIDIVQ_4         /*!< PLLSAI division fa
+ 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_18          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_0)  
+ 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_19          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1)  
+ 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_20          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | 
+ 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_21          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2)  
+ 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_22          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_23          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_24          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | 
+ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_25          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3)  
+ 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_26          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ARM GAS  /tmp/ccLtUKRp.s 			page 31
+
+
+ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_27          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_28          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_29          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_30          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_31          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_32          (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | 
+ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLSAICFGR_PLLSAIR)
+ 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIR  PLLSAIR division factor (PLLSAIR)
+ 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_2              RCC_PLLSAICFGR_PLLSAIR_1                                 
+ 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_3              (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)    
+ 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_4              RCC_PLLSAICFGR_PLLSAIR_2                                 
+ 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_5              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0)    
+ 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_6              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1)    
+ 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_7              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RC
+ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+ 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLSAICFGR_PLLSAIR */
+ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
+ 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIDIVR  PLLSAIDIVR division factor (PLLSAIDIVR)
+ 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_2           0x00000000U             /*!< PLLSAI division factor for P
+ 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_4           RCC_DCKCFGR1_PLLSAIDIVR_0        /*!< PLLSAI division fac
+1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_8           RCC_DCKCFGR1_PLLSAIDIVR_1        /*!< PLLSAI division fac
+1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_16          (RCC_DCKCFGR1_PLLSAIDIVR_1 | RCC_DCKCFGR1_PLLSAIDIVR_0)  
+1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
+1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIP  PLLSAIP division factor (PLLSAIP)
+1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_2              0x00000000U               /*!< PLLSAI division factor for
+1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_4              RCC_PLLSAICFGR_PLLSAIP_0        /*!< PLLSAI division fact
+1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_6              RCC_PLLSAICFGR_PLLSAIP_1        /*!< PLLSAI division fact
+1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_8              (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0)    
+1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported macro ------------------------------------------------------------*/
+1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ARM GAS  /tmp/ccLtUKRp.s 			page 32
+
+
+1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Write a value in RCC register
+1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __REG__ Register to be written
+1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __VALUE__ Value to be written in the register
+1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Read a value in RCC register
+1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __REG__ Register to be read
+1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Register value
+1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLCLK frequency on system domain
+1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+ARM GAS  /tmp/ccLtUKRp.s 			page 33
+
+
+1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLN__ Between 50 and 432
+1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLP__ This parameter can be one of the following values:
+1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_2
+1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_4
+1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_6
+1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_8
+1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLL clock frequency (in Hz)
+1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (
+1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
+1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain
+1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
+1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+ARM GAS  /tmp/ccLtUKRp.s 			page 34
+
+
+1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+ARM GAS  /tmp/ccLtUKRp.s 			page 35
+
+
+1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLN__ Between 50 and 432
+1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLQ__ This parameter can be one of the following values:
+1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_2
+1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_3
+1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_4
+1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_5
+1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_6
+1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_7
+1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_8
+1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_9
+1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_10
+1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_11
+1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_12
+1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_13
+1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_14
+1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_15
+1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLL clock frequency (in Hz)
+1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__)
+1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
+1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLCLK frequency used on DSI
+1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+ARM GAS  /tmp/ccLtUKRp.s 			page 36
+
+
+1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLN__ Between 50 and 432
+1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLR__ This parameter can be one of the following values:
+1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_2
+1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_3
+1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_4
+1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_5
+1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_6
+1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_7
+1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLL clock frequency (in Hz)
+1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__)
+1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains
+1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ 
+1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+ARM GAS  /tmp/ccLtUKRp.s 			page 37
+
+
+1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+ARM GAS  /tmp/ccLtUKRp.s 			page 38
+
+
+1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIN__ Between 50 and 432
+1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIQ__ This parameter can be one of the following values:
+1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIDIVQ__ This parameter can be one of the following values:
+1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLSAI clock frequency (in Hz)
+1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDI
+1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCF
+ARM GAS  /tmp/ccLtUKRp.s 			page 39
+
+
+1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
+1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
+1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+ARM GAS  /tmp/ccLtUKRp.s 			page 40
+
+
+1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIN__ Between 50 and 432
+1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIP__ This parameter can be one of the following values:
+1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLSAI clock frequency (in Hz)
+1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUT
+1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U))
+1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(LTDC)
+1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLSAI frequency used for LTDC domain
+1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR 
+1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+ARM GAS  /tmp/ccLtUKRp.s 			page 41
+
+
+1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIN__ Between 50 and 432
+1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIR__ This parameter can be one of the following values:
+1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLSAIDIVR__ This parameter can be one of the following values:
+1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLSAI clock frequency (in Hz)
+1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAID
+1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__P
+1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LTDC */
+1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains
+1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ARM GAS  /tmp/ccLtUKRp.s 			page 42
+
+
+1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ 
+1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+ARM GAS  /tmp/ccLtUKRp.s 			page 43
+
+
+1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SN__ Between 50 and 432
+1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SQ__ This parameter can be one of the following values:
+1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SDIVQ__ This parameter can be one of the following values:
+1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+ARM GAS  /tmp/ccLtUKRp.s 			page 44
+
+
+1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLI2S clock frequency (in Hz)
+1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDI
+1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    (((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCF
+1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX)
+1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
+1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
+1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+ARM GAS  /tmp/ccLtUKRp.s 			page 45
+
+
+1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SN__ Between 50 and 432
+1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SP__ This parameter can be one of the following values:
+1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLI2S clock frequency (in Hz)
+1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__I
+1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
+1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */
+1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PLLI2S frequency used for I2S domain
+1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
+1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLM__ This parameter can be one of the following values:
+1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+ARM GAS  /tmp/ccLtUKRp.s 			page 46
+
+
+1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SN__ Between 50 and 432
+1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __PLLI2SR__ This parameter can be one of the following values:
+1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PLLI2S clock frequency (in Hz)
+1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUT
+1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****                    ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
+1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the HCLK frequency
+1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __AHBPRESCALER__ This parameter can be one of the following values:
+ARM GAS  /tmp/ccLtUKRp.s 			page 47
+
+
+1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_1
+1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_2
+1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_4
+1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_8
+1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_16
+1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_64
+1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_128
+1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_256
+1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_512
+1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval HCLK clock frequency (in Hz)
+1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTabl
+1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __HCLKFREQ__ HCLK frequency
+1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __APB1PRESCALER__ This parameter can be one of the following values:
+1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_1
+1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_2
+1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_4
+1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_8
+1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_16
+1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PCLK1 clock frequency (in Hz)
+1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[
+1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __HCLKFREQ__ HCLK frequency
+1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  __APB2PRESCALER__ This parameter can be one of the following values:
+1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_1
+1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_2
+1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_4
+1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_8
+1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_16
+1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval PCLK2 clock frequency (in Hz)
+1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[
+1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported functions --------------------------------------------------------*/
+1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSE HSE
+1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ARM GAS  /tmp/ccLtUKRp.s 			page 48
+
+
+1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable the Clock Security System.
+1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
+1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_CSSON);
+1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable HSE external oscillator (HSE Bypass)
+1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
+1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable HSE external oscillator (HSE Bypass)
+1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
+1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable HSE crystal oscillator (HSE ON)
+1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
+1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Enable(void)
+1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_HSEON);
+1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable HSE crystal oscillator (HSE ON)
+1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
+1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Disable(void)
+1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if HSE oscillator Ready
+1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
+1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+ARM GAS  /tmp/ccLtUKRp.s 			page 49
+
+
+1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI HSI
+2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable HSI oscillator
+2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSION         LL_RCC_HSI_Enable
+2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Enable(void)
+2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_HSION);
+2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable HSI oscillator
+2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSION         LL_RCC_HSI_Disable
+2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Disable(void)
+2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if HSI clock is ready
+2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
+2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get HSI Calibration value
+2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note When HSITRIM is written, HSICAL is updated with the sum of
+2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       HSITRIM and the factory trim value
+2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR        HSICAL        LL_RCC_HSI_GetCalibration
+2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
+2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set HSI Calibration trimming
+2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note user-programmable trimming value that is added to the HSICAL
+2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note Default value is 16, which, when added to the HSICAL value,
+2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       should trim the HSI to 16 MHz +/- 1 %
+ARM GAS  /tmp/ccLtUKRp.s 			page 50
+
+
+2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
+2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Value Between Min_Data = 0 and Max_Data = 31
+2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
+2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get HSI Calibration trimming
+2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
+2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between Min_Data = 0 and Max_Data = 31
+2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSE LSE
+2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable  Low Speed External (LSE) crystal.
+2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
+2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Enable(void)
+2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable  Low Speed External (LSE) crystal.
+2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
+2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Disable(void)
+2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable external clock source (LSE bypass).
+2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
+2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ARM GAS  /tmp/ccLtUKRp.s 			page 51
+
+
+2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable external clock source (LSE bypass).
+2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
+2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set LSE oscillator drive capability
+2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note The oscillator is in Xtal mode when it is not in bypass mode.
+2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
+2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  LSEDrive This parameter can be one of the following values:
+2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_LOW
+2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get LSE oscillator drive capability
+2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
+2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_LOW
+2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if LSE oscillator Ready
+2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
+2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
+2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSI LSI
+2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ARM GAS  /tmp/ccLtUKRp.s 			page 52
+
+
+2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable LSI Oscillator
+2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
+2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Enable(void)
+2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CSR, RCC_CSR_LSION);
+2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable LSI Oscillator
+2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
+2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Disable(void)
+2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if LSI is Ready
+2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
+2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_System System
+2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure the system clock source
+2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
+2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get the system clock source
+2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
+2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+ARM GAS  /tmp/ccLtUKRp.s 			page 53
+
+
+2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set AHB prescaler
+2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
+2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Prescaler This parameter can be one of the following values:
+2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_1
+2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_2
+2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_4
+2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_8
+2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_16
+2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_64
+2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_128
+2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_256
+2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_512
+2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set APB1 prescaler
+2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
+2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Prescaler This parameter can be one of the following values:
+2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_1
+2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_2
+2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_4
+2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_8
+2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_16
+2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set APB2 prescaler
+2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
+2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Prescaler This parameter can be one of the following values:
+2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_1
+2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_2
+2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_4
+2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_8
+2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_16
+2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+ARM GAS  /tmp/ccLtUKRp.s 			page 54
+
+
+2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get AHB prescaler
+2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
+2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_1
+2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_2
+2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_4
+2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_8
+2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_16
+2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_64
+2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_128
+2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_256
+2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SYSCLK_DIV_512
+2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get APB1 prescaler
+2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
+2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_1
+2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_2
+2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_4
+2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_8
+2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB1_DIV_16
+2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get APB2 prescaler
+2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
+2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_1
+2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_2
+2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_4
+2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_8
+2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_APB2_DIV_16
+2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ARM GAS  /tmp/ccLtUKRp.s 			page 55
+
+
+2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_MCO MCO
+2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure MCOx
+2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
+2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
+2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         CFGR         MCO2          LL_RCC_ConfigMCO\n
+2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
+2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  MCOxSource This parameter can be one of the following values:
+2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
+2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
+2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2SOURCE_HSE
+2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
+2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  MCOxPrescaler This parameter can be one of the following values:
+2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1_DIV_1
+2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1_DIV_2
+2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1_DIV_3
+2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1_DIV_4
+2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO1_DIV_5
+2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2_DIV_1
+2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2_DIV_2
+2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2_DIV_3
+2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2_DIV_4
+2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_MCO2_DIV_5
+2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U),  (MCOxSource <<
+2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure USARTx clock source
+2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        USART1SEL     LL_RCC_SetUSARTClockSource\n
+2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART2SEL     LL_RCC_SetUSARTClockSource\n
+2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART3SEL     LL_RCC_SetUSARTClockSource\n
+2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART6SEL     LL_RCC_SetUSARTClockSource
+2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  USARTxSource This parameter can be one of the following values:
+2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+ARM GAS  /tmp/ccLtUKRp.s 			page 56
+
+
+2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
+2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
+2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
+2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
+2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
+2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
+2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure UARTx clock source
+2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        UART4SEL      LL_RCC_SetUARTClockSource\n
+2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART5SEL      LL_RCC_SetUARTClockSource\n
+2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART7SEL      LL_RCC_SetUARTClockSource\n
+2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART8SEL      LL_RCC_SetUARTClockSource
+2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  UARTxSource This parameter can be one of the following values:
+2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
+2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
+2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
+2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
+2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
+2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
+2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
+2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
+2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
+2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
+2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure I2Cx clock source
+2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        I2C1SEL       LL_RCC_SetI2CClockSource\n
+2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C2SEL       LL_RCC_SetI2CClockSource\n
+2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C3SEL       LL_RCC_SetI2CClockSource\n
+2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C4SEL       LL_RCC_SetI2CClockSource
+2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  I2CxSource This parameter can be one of the following values:
+2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+ARM GAS  /tmp/ccLtUKRp.s 			page 57
+
+
+2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U),  (I2CxSource << 16U));
+2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure LPTIMx clock source
+2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_SetLPTIMClockSource
+2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  LPTIMxSource This parameter can be one of the following values:
+2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
+2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
+2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure SAIx clock source
+2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1        SAI1SEL       LL_RCC_SetSAIClockSource\n
+2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR1        SAI2SEL       LL_RCC_SetSAIClockSource
+2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  SAIxSource This parameter can be one of the following values:
+2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
+2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
+2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
+2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
+2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
+2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
+2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
+2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
+2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ARM GAS  /tmp/ccLtUKRp.s 			page 58
+
+
+2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure SDMMC clock source
+2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        SDMMC1SEL      LL_RCC_SetSDMMCClockSource\n
+2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        SDMMC2SEL      LL_RCC_SetSDMMCClockSource
+2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  SDMMCxSource This parameter can be one of the following values:
+2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
+2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
+2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
+2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
+2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
+2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U));
+2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure 48Mhz domain clock source
+2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_SetCK48MClockSource
+2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  CK48MxSource This parameter can be one of the following values:
+2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
+2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
+2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
+2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure RNG clock source
+2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_SetRNGClockSource
+2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  RNGxSource This parameter can be one of the following values:
+2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
+2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
+2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
+2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure USB clock source
+2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_SetUSBClockSource
+2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  USBxSource This parameter can be one of the following values:
+2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
+2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
+2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC)
+ARM GAS  /tmp/ccLtUKRp.s 			page 59
+
+
+2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure CEC clock source
+2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2         CECSEL        LL_RCC_SetCECClockSource
+2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
+2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
+2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */
+2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure I2S clock source
+2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         I2SSRC        LL_RCC_SetI2SClockSource
+2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
+2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
+2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
+2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure DSI clock source
+2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2         DSISEL        LL_RCC_SetDSIClockSource
+2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
+2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source);
+2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0)
+2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure DFSDM Audio clock source
+2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         ADFSDM1SEL        LL_RCC_SetDFSDMAudioClockSource
+2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
+2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
+2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
+2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source);
+2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ARM GAS  /tmp/ccLtUKRp.s 			page 60
+
+
+2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure DFSDM Kernel clock source
+2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         DFSDM1SEL        LL_RCC_SetDFSDMClockSource
+2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
+2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source);
+2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */
+2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get USARTx clock source
+2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        USART1SEL     LL_RCC_GetUSARTClockSource\n
+2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART2SEL     LL_RCC_GetUSARTClockSource\n
+2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART3SEL     LL_RCC_GetUSARTClockSource\n
+2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        USART6SEL     LL_RCC_GetUSARTClockSource
+2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  USARTx This parameter can be one of the following values:
+2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE
+2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE
+2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE
+2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE
+2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
+2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
+2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
+2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
+2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
+2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
+2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U));
+2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get UARTx clock source
+2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        UART4SEL      LL_RCC_GetUARTClockSource\n
+2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART5SEL      LL_RCC_GetUARTClockSource\n
+2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART7SEL      LL_RCC_GetUARTClockSource\n
+2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        UART8SEL      LL_RCC_GetUARTClockSource
+2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  UARTx This parameter can be one of the following values:
+2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE
+2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE
+2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE
+ARM GAS  /tmp/ccLtUKRp.s 			page 61
+
+
+2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE
+2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
+2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
+2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
+2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
+2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
+2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
+2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
+2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
+2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
+2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U));
+2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2Cx clock source
+2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        I2C1SEL       LL_RCC_GetI2CClockSource\n
+2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C2SEL       LL_RCC_GetI2CClockSource\n
+2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C3SEL       LL_RCC_GetI2CClockSource\n
+2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        I2C4SEL       LL_RCC_GetI2CClockSource
+2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  I2Cx This parameter can be one of the following values:
+2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE
+2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
+2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
+2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****  */
+2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
+2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx);
+2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ARM GAS  /tmp/ccLtUKRp.s 			page 62
+
+
+2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get LPTIMx clock source
+2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_GetLPTIMClockSource
+2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  LPTIMx This parameter can be one of the following values:
+2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
+2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
+2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get SAIx clock source
+2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1        SAI1SEL       LL_RCC_GetSAIClockSource\n
+2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR1        SAI2SEL       LL_RCC_GetSAIClockSource
+2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  SAIx This parameter can be one of the following values:
+2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE
+2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
+2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
+2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
+2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
+2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
+2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
+2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
+2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U | SAIx);
+2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get SDMMCx clock source
+2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        SDMMC1SEL      LL_RCC_GetSDMMCClockSource\n
+2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR2        SDMMC2SEL      LL_RCC_GetSDMMCClockSource
+2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  SDMMCx This parameter can be one of the following values:
+2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*)
+2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
+2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
+2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
+2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
+2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *
+2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         (*) value not defined in all devices.
+2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
+2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx);
+ARM GAS  /tmp/ccLtUKRp.s 			page 63
+
+
+2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get 48Mhz domain clock source
+2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_GetCK48MClockSource
+2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  CK48Mx This parameter can be one of the following values:
+2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CK48M_CLKSOURCE
+2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
+2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
+2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
+2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get RNGx clock source
+2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_GetRNGClockSource
+2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  RNGx This parameter can be one of the following values:
+2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RNG_CLKSOURCE
+2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
+2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
+2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
+2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get USBx clock source
+2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2        CK48MSEL      LL_RCC_GetUSBClockSource
+2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  USBx This parameter can be one of the following values:
+2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USB_CLKSOURCE
+2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
+2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
+2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC)
+2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get CEC Clock Source
+2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2         CECSEL        LL_RCC_GetCECClockSource
+2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  CECx This parameter can be one of the following values:
+2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CEC_CLKSOURCE
+2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
+2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
+ARM GAS  /tmp/ccLtUKRp.s 			page 64
+
+
+2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */
+2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2S Clock Source
+2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         I2SSRC        LL_RCC_GetI2SClockSource
+2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  I2Sx This parameter can be one of the following values:
+2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2S1_CLKSOURCE
+2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
+2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
+2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0)
+2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get DFSDM Audio Clock Source
+2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         ADFSDM1SEL        LL_RCC_GetDFSDMAudioClockSource
+2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  DFSDMx This parameter can be one of the following values:
+2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
+2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
+2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
+2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
+2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get DFSDM Audio Clock Source
+2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         DFSDM1SEL        LL_RCC_GetDFSDMClockSource
+2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  DFSDMx This parameter can be one of the following values:
+2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
+2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
+2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */
+2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get DSI Clock Source
+2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR2         DSISEL        LL_RCC_GetDSIClockSource
+2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  DSIx This parameter can be one of the following values:
+2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DSI_CLKSOURCE
+2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+ARM GAS  /tmp/ccLtUKRp.s 			page 65
+
+
+2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
+2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx));
+2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_RTC RTC
+2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set RTC Clock Source
+2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
+2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       set). The BDRST bit can be used to reset them.
+2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
+2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get RTC Clock Source
+2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
+2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable RTC
+2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
+2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_EnableRTC(void)
+2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ARM GAS  /tmp/ccLtUKRp.s 			page 66
+
+
+2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable RTC
+2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
+2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_DisableRTC(void)
+2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if RTC has been enabled or not
+2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
+2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
+2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Force the Backup domain reset
+2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
+2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Release the Backup domain reset
+2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
+2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set HSE Prescalers for RTC Clock
+3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
+3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Prescaler This parameter can be one of the following values:
+3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_NOCLOCK
+3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+ARM GAS  /tmp/ccLtUKRp.s 			page 67
+
+
+3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
+3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
+3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get HSE Prescalers for RTC Clock
+3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
+3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_NOCLOCK
+3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+ARM GAS  /tmp/ccLtUKRp.s 			page 68
+
+
+3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
+3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
+3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
+3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Set Timers Clock Prescalers
+3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         TIMPRE        LL_RCC_SetTIMPrescaler
+3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Prescaler This parameter can be one of the following values:
+3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
+3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler);
+3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Timers Clock Prescalers
+3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1         TIMPRE        LL_RCC_GetTIMPrescaler
+3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
+3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE));
+3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLL PLL
+3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable PLL
+3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
+3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Enable(void)
+3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_PLLON);
+ARM GAS  /tmp/ccLtUKRp.s 			page 69
+
+
+3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable PLL
+3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note Cannot be disabled if the PLL clock is used as the system clock
+3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
+3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Disable(void)
+3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if PLL Ready
+3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
+3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+  93              		.loc 2 3153 26 view .LVU26
+  94              	.LBB55:
+3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+  95              		.loc 2 3155 3 view .LVU27
+  96              		.loc 2 3155 11 is_stmt 0 view .LVU28
+  97 0000 0A4B     		ldr	r3, .L9
+  98 0002 1B68     		ldr	r3, [r3]
+  99              	.LBE55:
+ 100              	.LBE54:
+ 101              		.loc 1 653 5 view .LVU29
+ 102 0004 13F0007F 		tst	r3, #33554432
+ 103 0008 0DD1     		bne	.L6
+ 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 104              		.loc 1 650 15 view .LVU30
+ 105 000a 0020     		movs	r0, #0
+ 106              	.L3:
+ 107              	.LVL6:
+ 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* PLL configuration cannot be modified */
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     status = ERROR;
+ 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Check if PLLSAI is busy*/
+ 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   if(LL_RCC_PLLSAI_IsReady() != 0U)
+ 108              		.loc 1 660 3 is_stmt 1 view .LVU31
+ 109              	.LBB56:
+ 110              	.LBI56:
+3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLL used for SYSCLK Domain
+3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLP can be written only when PLL is disabled
+3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
+3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
+3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
+ARM GAS  /tmp/ccLtUKRp.s 			page 70
+
+
+3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SYS
+3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+ARM GAS  /tmp/ccLtUKRp.s 			page 71
+
+
+3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLP This parameter can be one of the following values:
+3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_2
+3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_4
+3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_6
+3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_8
+3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin
+3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P
+3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLL used for 48Mhz domain clock
+3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLQ can be written only when PLL is disabled
+3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This  can be selected for USB, RNG, SDMMC1
+3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
+3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
+3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
+3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
+3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+ARM GAS  /tmp/ccLtUKRp.s 			page 72
+
+
+3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLQ This parameter can be one of the following values:
+3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_2
+3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_3
+3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_4
+3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_5
+3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_6
+3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_7
+3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_8
+3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_9
+3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_10
+3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_11
+3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_12
+3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_13
+ARM GAS  /tmp/ccLtUKRp.s 			page 73
+
+
+3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_14
+3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_15
+3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin
+3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P
+3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
+3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI)
+3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLL used for DSI clock
+3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLR can be written only when PLL is disabled
+3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This  can be selected for DSI
+3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_DSI\n
+3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_DSI\n
+3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_DSI\n
+3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_DSI
+3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+ARM GAS  /tmp/ccLtUKRp.s 			page 74
+
+
+3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLR This parameter can be one of the following values:
+3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_2
+3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_3
+3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_4
+3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_5
+3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_6
+3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_7
+3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin
+3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P
+3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */
+3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLL clock source
+3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource
+3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param PLLSource This parameter can be one of the following values:
+3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ARM GAS  /tmp/ccLtUKRp.s 			page 75
+
+
+3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get the oscillator used as PLL clock source.
+3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
+3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Main PLL multiplication factor for VCO
+3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
+3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between 50 and 432
+3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
+3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
+3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Main PLL division factor for PLLP 
+3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLP       LL_RCC_PLL_GetP
+3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_2
+3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_4
+3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_6
+3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLP_DIV_8
+3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
+3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
+3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Main PLL division factor for PLLQ
+3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock)
+3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
+3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_2
+3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_3
+3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_4
+3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_5
+3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_6
+3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_7
+3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_8
+3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_9
+3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_10
+3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_11
+3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_12
+3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_13
+3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_14
+ARM GAS  /tmp/ccLtUKRp.s 			page 76
+
+
+3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLQ_DIV_15
+3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
+3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
+3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLCFGR_PLLR)
+3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Main PLL division factor for PLLR
+3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used for PLLCLK (system clock)
+3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
+3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_2
+3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_3
+3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_4
+3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_5
+3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_6
+3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLR_DIV_7
+3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
+3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
+3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLCFGR_PLLR */
+3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Division factor for the main PLL and other PLL
+3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
+3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+ARM GAS  /tmp/ccLtUKRp.s 			page 77
+
+
+3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
+3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure Spread Spectrum used for PLL
+3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note These bits must be written before enabling PLL
+3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR        MODPER        LL_RCC_PLL_ConfigSpreadSpectrum\n
+3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         SSCGR        INCSTEP       LL_RCC_PLL_ConfigSpreadSpectrum\n
+3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         SSCGR        SPREADSEL     LL_RCC_PLL_ConfigSpreadSpectrum
+3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Mod Between Min_Data=0 and Max_Data=8191
+3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Inc Between Min_Data=0 and Max_Data=32767
+3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Sel This parameter can be one of the following values:
+3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
+3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << 
+ARM GAS  /tmp/ccLtUKRp.s 			page 78
+
+
+3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Spread Spectrum Modulation Period for PLL
+3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR         MODPER        LL_RCC_PLL_GetPeriodModulation
+3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between Min_Data=0 and Max_Data=8191
+3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
+3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
+3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Spread Spectrum Incrementation Step for PLL
+3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note Must be written before enabling PLL
+3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR         INCSTEP        LL_RCC_PLL_GetStepIncrementation
+3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between Min_Data=0 and Max_Data=32767
+3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
+3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
+3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get Spread Spectrum Selection for PLL
+3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note Must be written before enabling PLL
+3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR         SPREADSEL        LL_RCC_PLL_GetSpreadSelection
+3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
+3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
+3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable Spread Spectrum for PLL.
+3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Enable
+3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
+3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable Spread Spectrum for PLL.
+3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Disable
+3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
+3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+ARM GAS  /tmp/ccLtUKRp.s 			page 79
+
+
+3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
+3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable PLLI2S
+3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Enable
+3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
+3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
+3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable PLLI2S
+3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Disable
+3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
+3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if PLLI2S Ready
+3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLI2SRDY    LL_RCC_PLLI2S_IsReady
+3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
+3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
+3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLLI2S used for SAI1 and SAI2 domain clock
+3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLQ can be written only when PLLI2S is disabled
+3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This can be selected for SAI1 and SAI2
+3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SAI\n
+3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SAI\n
+3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         DCKCFGR1      PLLI2SDIVQ    LL_RCC_PLLI2S_ConfigDomain_SAI
+3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+ARM GAS  /tmp/ccLtUKRp.s 			page 80
+
+
+3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+ARM GAS  /tmp/ccLtUKRp.s 			page 81
+
+
+3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLQ This parameter can be one of the following values:
+3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLDIVQ This parameter can be one of the following values:
+3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, 
+3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCF
+3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ);
+3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ARM GAS  /tmp/ccLtUKRp.s 			page 82
+
+
+3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX)
+3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief Configure PLLI2S used for SPDIFRX domain clock
+3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLP can be written only when PLLI2S is disabled
+3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This  can be selected for SPDIFRX
+3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SP       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
+3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+ARM GAS  /tmp/ccLtUKRp.s 			page 83
+
+
+3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLP This parameter can be one of the following values:
+3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PL
+3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCF
+3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */
+3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Configure PLLI2S used for I2S1 domain clock
+3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLL Source and PLLM Divider can be written only when PLL,
+3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *       PLLI2S and PLLSAI are disabled
+3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note PLLN/PLLR can be written only when PLLI2S is disabled
+3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note This  can be selected for I2S
+3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_I2S\n
+3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_I2S\n
+3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_I2S\n
+3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_I2S
+3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  Source This parameter can be one of the following values:
+3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSI
+3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLSOURCE_HSE
+3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLM This parameter can be one of the following values:
+3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_2
+3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_3
+3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_4
+3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_5
+3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_6
+3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_7
+3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_8
+ARM GAS  /tmp/ccLtUKRp.s 			page 84
+
+
+3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_9
+3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_10
+3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_11
+3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_12
+3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_13
+3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_14
+3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_15
+3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_16
+3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_17
+3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_18
+3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_19
+3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_20
+3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_21
+3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_22
+3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_23
+3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_24
+3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_25
+3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_26
+3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_27
+3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_28
+3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_29
+3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_30
+3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_31
+3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_32
+3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_33
+3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_34
+3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_35
+3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_36
+3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_37
+3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_38
+3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_39
+3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_40
+3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_41
+3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_42
+3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_43
+3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_44
+4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_45
+4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_46
+4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_47
+4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_48
+4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_49
+4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_50
+4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_51
+4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_52
+4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_53
+4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_54
+4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_55
+4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_56
+4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_57
+4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_58
+4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_59
+4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_60
+4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_61
+4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_62
+4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLM_DIV_63
+4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLN Between 50 and 432
+4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @param  PLLR This parameter can be one of the following values:
+ARM GAS  /tmp/ccLtUKRp.s 			page 85
+
+
+4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, 
+4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCF
+4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2SPLL multiplication factor for VCO
+4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLI2SCFGR  PLLI2SN      LL_RCC_PLLI2S_GetN
+4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Between 50 and 432
+4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
+4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos
+4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2SPLL division factor for PLLI2SQ
+4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLI2SCFGR  PLLI2SQ      LL_RCC_PLLI2S_GetQ
+4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
+4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
+4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2SPLL division factor for PLLI2SR
+4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used for PLLI2SCLK (I2S clock)
+4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLI2SCFGR  PLLI2SR      LL_RCC_PLLI2S_GetR
+4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+ARM GAS  /tmp/ccLtUKRp.s 			page 86
+
+
+4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
+4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
+4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLI2SCFGR_PLLI2SP)
+4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2SPLL division factor for PLLI2SP
+4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
+4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll PLLI2SCFGR  PLLI2SP      LL_RCC_PLLI2S_GetP
+4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+4093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+4094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+4095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+4096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
+4098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
+4100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLI2SCFGR_PLLI2SP */
+4102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Get I2SPLL division factor for PLLI2SDIVQ
+4105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
+4106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll DCKCFGR1   PLLI2SDIVQ      LL_RCC_PLLI2S_GetDIVQ
+4107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval Returned value can be one of the following values:
+4108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+4109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+4110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+4111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+4112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+4113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+4114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+4115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+4116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+4117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+4118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+4119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+4120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+4121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+4122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+4123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+4124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+4125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+4126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+4127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+4128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+4129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+4130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+4131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+4132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+4133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+4134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+ARM GAS  /tmp/ccLtUKRp.s 			page 87
+
+
+4135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+4136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+4137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+4138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+4139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+4140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
+4142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ));
+4144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @}
+4148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLLSAI PLLSAI
+4151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @{
+4152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Enable PLLSAI
+4156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Enable
+4157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+4158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
+4160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   SET_BIT(RCC->CR, RCC_CR_PLLSAION);
+4162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Disable PLLSAI
+4166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Disable
+4167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval None
+4168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
+4170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+4172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+4173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+4174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /**
+4175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @brief  Check if PLLSAI Ready
+4176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @rmtoll CR           PLLSAIRDY    LL_RCC_PLLSAI_IsReady
+4177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   * @retval State of bit (1 or 0).
+4178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   */
+4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
+ 111              		.loc 2 4179 26 view .LVU32
+ 112              	.LBB57:
+4180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****   return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
+ 113              		.loc 2 4181 3 view .LVU33
+ 114              		.loc 2 4181 11 is_stmt 0 view .LVU34
+ 115 000c 074B     		ldr	r3, .L9
+ 116 000e 1B68     		ldr	r3, [r3]
+ 117              	.LBE57:
+ 118              	.LBE56:
+ 119              		.loc 1 660 5 view .LVU35
+ 120 0010 13F0005F 		tst	r3, #536870912
+ARM GAS  /tmp/ccLtUKRp.s 			page 88
+
+
+ 121 0014 00D0     		beq	.L4
+ 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* PLLSAI1 configuration cannot be modified */
+ 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     status = ERROR;
+ 122              		.loc 1 663 12 view .LVU36
+ 123 0016 0120     		movs	r0, #1
+ 124              	.LVL7:
+ 125              	.L4:
+ 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Check if PLLI2S is busy*/
+ 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   if(LL_RCC_PLLI2S_IsReady() != 0U)
+ 126              		.loc 1 666 3 is_stmt 1 view .LVU37
+ 127              	.LBB58:
+ 128              	.LBI58:
+3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 129              		.loc 2 3711 26 view .LVU38
+ 130              	.LBB59:
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 131              		.loc 2 3713 3 view .LVU39
+3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 132              		.loc 2 3713 11 is_stmt 0 view .LVU40
+ 133 0018 044B     		ldr	r3, .L9
+ 134 001a 1B68     		ldr	r3, [r3]
+ 135              	.LBE59:
+ 136              	.LBE58:
+ 137              		.loc 1 666 5 view .LVU41
+ 138 001c 13F0006F 		tst	r3, #134217728
+ 139 0020 00D0     		beq	.L5
+ 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* PLLI2S configuration cannot be modified */
+ 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     status = ERROR;
+ 140              		.loc 1 669 12 view .LVU42
+ 141 0022 0120     		movs	r0, #1
+ 142              	.LVL8:
+ 143              	.L5:
+ 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   return status;
+ 144              		.loc 1 671 3 is_stmt 1 view .LVU43
+ 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 145              		.loc 1 672 1 is_stmt 0 view .LVU44
+ 146 0024 7047     		bx	lr
+ 147              	.LVL9:
+ 148              	.L6:
+ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 149              		.loc 1 656 12 view .LVU45
+ 150 0026 0120     		movs	r0, #1
+ 151 0028 F0E7     		b	.L3
+ 152              	.L10:
+ 153 002a 00BF     		.align	2
+ 154              	.L9:
+ 155 002c 00380240 		.word	1073887232
+ 156              		.cfi_endproc
+ 157              	.LFE412:
+ 159              		.section	.text.LL_Init1msTick,"ax",%progbits
+ 160              		.align	1
+ 161              		.global	LL_Init1msTick
+ 162              		.syntax unified
+ARM GAS  /tmp/ccLtUKRp.s 			page 89
+
+
+ 163              		.thumb
+ 164              		.thumb_func
+ 165              		.fpu fpv5-d16
+ 167              	LL_Init1msTick:
+ 168              	.LVL10:
+ 169              	.LFB405:
+ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Use frequency provided in argument */
+ 170              		.loc 1 219 1 is_stmt 1 view -0
+ 171              		.cfi_startproc
+ 172              		@ args = 0, pretend = 0, frame = 0
+ 173              		@ frame_needed = 0, uses_anonymous_args = 0
+ 174              		@ link register save eliminated.
+ 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 175              		.loc 1 221 3 view .LVU47
+ 176              	.LBB60:
+ 177              	.LBI60:
+ 178              		.file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @file    stm32f7xx_ll_utils.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @brief   Header file of UTILS LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   @verbatim
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   ==============================================================================
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                      ##### How to use this driver #####
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   ==============================================================================
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****     [..]
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****     The LL UTILS driver contains a set of generic APIs that can be
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****     used by user:
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****       (+) Device electronic signature
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****       (+) Timing functions
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****       (+) PLL configuration functions
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   @endverbatim
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   ******************************************************************************
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @attention
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   *
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * Copyright (c) 2017 STMicroelectronics.
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * All rights reserved.
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   *
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * in the root directory of this software component.
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   *
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   ******************************************************************************
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #ifndef __STM32F7xx_LL_UTILS_H
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define __STM32F7xx_LL_UTILS_H
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #ifdef __cplusplus
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** extern "C" {
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #endif
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Includes ------------------------------------------------------------------*/
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #include "stm32f7xx.h"
+ARM GAS  /tmp/ccLtUKRp.s 			page 90
+
+
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @addtogroup STM32F7xx_LL_Driver
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @{
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL UTILS
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @{
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Private types -------------------------------------------------------------*/
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Private variables ---------------------------------------------------------*/
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Private constants ---------------------------------------------------------*/
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @{
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Max delay can be used in LL_mDelay */
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_MAX_DELAY                  0xFFFFFFFFU
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****  * @brief Unique device ID register base address
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****  */
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define UID_BASE_ADDRESS              UID_BASE
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****  * @brief Flash size data register base address
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****  */
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****  * @brief Package data register base address
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****  */
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @}
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Private macros ------------------------------------------------------------*/
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @{
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @}
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Exported types ------------------------------------------------------------*/
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @{
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @brief  UTILS PLL structure definition
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** typedef struct
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** {
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                         This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
+ARM GAS  /tmp/ccLtUKRp.s 			page 91
+
+
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                         This feature can be modified afterwards using unitary function
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                         This parameter must be a number between Min_Data = 50 and Max_Data = 432
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                         This feature can be modified afterwards using unitary function
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   uint32_t PLLP;   /*!< Division for the main system clock.
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                         This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                         This feature can be modified afterwards using unitary function
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** } LL_UTILS_PLLInitTypeDef;
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @brief  UTILS System, AHB and APB buses clock configuration structure definition
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** typedef struct
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** {
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                                        This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                                        This feature can be modified afterwards using unitary functi
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                                        @ref LL_RCC_SetAHBPrescaler(). */
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from t
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                                        This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                                        This feature can be modified afterwards using unitary functi
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                                        @ref LL_RCC_SetAPB1Prescaler(). */
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from t
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                                        This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                                        This feature can be modified afterwards using unitary functi
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****                                        @ref LL_RCC_SetAPB2Prescaler(). */
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** } LL_UTILS_ClkInitTypeDef;
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @}
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Exported constants --------------------------------------------------------*/
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @{
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @{
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled             
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                 
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ARM GAS  /tmp/ccLtUKRp.s 			page 92
+
+
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @}
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @{
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_LQFP100                    0x00000100U /*!< LQFP100 package type      
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143           0x00000200U /*!< LQFP144 or WLCSP143 packag
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176  0x00000300U /*!< WLCSP180, LQFP176 or UFBGA
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216   0x00000400U /*!< LQFP176, LQFP208 or TFBGA2
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_TFBGA216_LQFP176_LQFP208   0x00000500U /*!< LQFP176, LQFP208 or TFBGA2
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_LQFP176_TFBGA216_LQFP208   0x00000600U /*!< LQFP176, LQFP208 or TFBGA2
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_LQFP208_LQFP176_TFBGA216   0x00000700U /*!< LQFP176, LQFP208 or TFBGA2
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @}
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @}
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Exported macro ------------------------------------------------------------*/
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Exported functions --------------------------------------------------------*/
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @{
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @{
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @retval UID[31:0]
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** {
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** }
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @retval UID[63:32]
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** {
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** }
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @retval UID[95:64]
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** {
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+ARM GAS  /tmp/ccLtUKRp.s 			page 93
+
+
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** }
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @brief  Get Flash memory size
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @note   This bitfield indicates the size of the device Flash memory expressed in
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @retval FLASH_SIZE[15:0]: Flash memory size
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetFlashSize(void)
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** {
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** }
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @brief  Get Package type
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @retval Returned value can be one of the following values:
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 (*)
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 (*)
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 (*)
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   *
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   *         (*) value not defined in all devices.
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetPackageType(void)
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** {
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** }
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @}
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_EF_DELAY DELAY
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @{
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** 
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /**
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @brief  This function configures the Cortex-M SysTick source of the time base.
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @note   When a RTOS is used, it is recommended to avoid changing the SysTick 
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @param  Ticks Frequency of Ticks (Hz)
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   * @retval None
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   */
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+ 179              		.loc 3 256 22 view .LVU48
+ 180              	.LBB61:
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** {
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   /* Configure the SysTick to have interrupt in 1ms time base */
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
+ 181              		.loc 3 259 3 view .LVU49
+ 182              		.loc 3 259 46 is_stmt 0 view .LVU50
+ 183 0000 064B     		ldr	r3, .L12
+ 184 0002 A3FB0023 		umull	r2, r3, r3, r0
+ 185 0006 9B09     		lsrs	r3, r3, #6
+ 186              		.loc 3 259 20 view .LVU51
+ 187 0008 013B     		subs	r3, r3, #1
+ARM GAS  /tmp/ccLtUKRp.s 			page 94
+
+
+ 188              		.loc 3 259 18 view .LVU52
+ 189 000a 4FF0E022 		mov	r2, #-536813568
+ 190 000e 5361     		str	r3, [r2, #20]
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
+ 191              		.loc 3 260 3 is_stmt 1 view .LVU53
+ 192              		.loc 3 260 18 is_stmt 0 view .LVU54
+ 193 0010 0023     		movs	r3, #0
+ 194 0012 9361     		str	r3, [r2, #24]
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h ****   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+ 195              		.loc 3 261 3 is_stmt 1 view .LVU55
+ 196              		.loc 3 261 18 is_stmt 0 view .LVU56
+ 197 0014 0523     		movs	r3, #5
+ 198 0016 1361     		str	r3, [r2, #16]
+ 199              	.LVL11:
+ 200              		.loc 3 261 18 view .LVU57
+ 201              	.LBE61:
+ 202              	.LBE60:
+ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 203              		.loc 1 222 1 view .LVU58
+ 204 0018 7047     		bx	lr
+ 205              	.L13:
+ 206 001a 00BF     		.align	2
+ 207              	.L12:
+ 208 001c D34D6210 		.word	274877907
+ 209              		.cfi_endproc
+ 210              	.LFE405:
+ 212              		.section	.text.LL_mDelay,"ax",%progbits
+ 213              		.align	1
+ 214              		.global	LL_mDelay
+ 215              		.syntax unified
+ 216              		.thumb
+ 217              		.thumb_func
+ 218              		.fpu fpv5-d16
+ 220              	LL_mDelay:
+ 221              	.LVL12:
+ 222              	.LFB406:
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
+ 223              		.loc 1 235 1 is_stmt 1 view -0
+ 224              		.cfi_startproc
+ 225              		@ args = 0, pretend = 0, frame = 8
+ 226              		@ frame_needed = 0, uses_anonymous_args = 0
+ 227              		@ link register save eliminated.
+ 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
+ 228              		.loc 1 235 1 is_stmt 0 view .LVU60
+ 229 0000 82B0     		sub	sp, sp, #8
+ 230              	.LCFI0:
+ 231              		.cfi_def_cfa_offset 8
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Add this code to indicate that local variable is not used */
+ 232              		.loc 1 236 3 is_stmt 1 view .LVU61
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Add this code to indicate that local variable is not used */
+ 233              		.loc 1 236 31 is_stmt 0 view .LVU62
+ 234 0002 4FF0E023 		mov	r3, #-536813568
+ 235 0006 1B69     		ldr	r3, [r3, #16]
+ 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Add this code to indicate that local variable is not used */
+ 236              		.loc 1 236 18 view .LVU63
+ 237 0008 0193     		str	r3, [sp, #4]
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ARM GAS  /tmp/ccLtUKRp.s 			page 95
+
+
+ 238              		.loc 1 238 3 is_stmt 1 view .LVU64
+ 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 239              		.loc 1 238 4 is_stmt 0 view .LVU65
+ 240 000a 019B     		ldr	r3, [sp, #4]
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 241              		.loc 1 241 3 is_stmt 1 view .LVU66
+ 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 242              		.loc 1 241 5 is_stmt 0 view .LVU67
+ 243 000c B0F1FF3F 		cmp	r0, #-1
+ 244 0010 00D0     		beq	.L17
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 245              		.loc 1 243 5 is_stmt 1 view .LVU68
+ 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 246              		.loc 1 243 10 is_stmt 0 view .LVU69
+ 247 0012 0130     		adds	r0, r0, #1
+ 248              	.LVL13:
+ 249              	.L17:
+ 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 250              		.loc 1 246 9 is_stmt 1 view .LVU70
+ 251 0014 38B1     		cbz	r0, .L20
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 252              		.loc 1 248 5 view .LVU71
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 253              		.loc 1 248 16 is_stmt 0 view .LVU72
+ 254 0016 4FF0E023 		mov	r3, #-536813568
+ 255 001a 1B69     		ldr	r3, [r3, #16]
+ 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 256              		.loc 1 248 7 view .LVU73
+ 257 001c 13F4803F 		tst	r3, #65536
+ 258 0020 F8D0     		beq	.L17
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 259              		.loc 1 250 7 is_stmt 1 view .LVU74
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 260              		.loc 1 250 12 is_stmt 0 view .LVU75
+ 261 0022 0138     		subs	r0, r0, #1
+ 262              	.LVL14:
+ 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 263              		.loc 1 250 12 view .LVU76
+ 264 0024 F6E7     		b	.L17
+ 265              	.L20:
+ 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 266              		.loc 1 253 1 view .LVU77
+ 267 0026 02B0     		add	sp, sp, #8
+ 268              	.LCFI1:
+ 269              		.cfi_def_cfa_offset 0
+ 270              		@ sp needed
+ 271 0028 7047     		bx	lr
+ 272              		.cfi_endproc
+ 273              	.LFE406:
+ 275              		.section	.text.LL_SetSystemCoreClock,"ax",%progbits
+ 276              		.align	1
+ 277              		.global	LL_SetSystemCoreClock
+ 278              		.syntax unified
+ 279              		.thumb
+ 280              		.thumb_func
+ 281              		.fpu fpv5-d16
+ 283              	LL_SetSystemCoreClock:
+ARM GAS  /tmp/ccLtUKRp.s 			page 96
+
+
+ 284              	.LVL15:
+ 285              	.LFB407:
+ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* HCLK clock frequency */
+ 286              		.loc 1 312 1 is_stmt 1 view -0
+ 287              		.cfi_startproc
+ 288              		@ args = 0, pretend = 0, frame = 0
+ 289              		@ frame_needed = 0, uses_anonymous_args = 0
+ 290              		@ link register save eliminated.
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 291              		.loc 1 314 3 view .LVU79
+ 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 292              		.loc 1 314 19 is_stmt 0 view .LVU80
+ 293 0000 014B     		ldr	r3, .L22
+ 294 0002 1860     		str	r0, [r3]
+ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 295              		.loc 1 315 1 view .LVU81
+ 296 0004 7047     		bx	lr
+ 297              	.L23:
+ 298 0006 00BF     		.align	2
+ 299              	.L22:
+ 300 0008 00000000 		.word	SystemCoreClock
+ 301              		.cfi_endproc
+ 302              	.LFE407:
+ 304              		.section	.text.LL_SetFlashLatency,"ax",%progbits
+ 305              		.align	1
+ 306              		.global	LL_SetFlashLatency
+ 307              		.syntax unified
+ 308              		.thumb
+ 309              		.thumb_func
+ 310              		.fpu fpv5-d16
+ 312              	LL_SetFlashLatency:
+ 313              	.LVL16:
+ 314              	.LFB408:
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t timeout;
+ 315              		.loc 1 327 1 is_stmt 1 view -0
+ 316              		.cfi_startproc
+ 317              		@ args = 0, pretend = 0, frame = 0
+ 318              		@ frame_needed = 0, uses_anonymous_args = 0
+ 319              		@ link register save eliminated.
+ 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t getlatency;
+ 320              		.loc 1 328 3 view .LVU83
+ 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
+ 321              		.loc 1 329 3 view .LVU84
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 322              		.loc 1 330 3 view .LVU85
+ 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 323              		.loc 1 331 3 view .LVU86
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 324              		.loc 1 334 3 view .LVU87
+ 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 325              		.loc 1 334 5 is_stmt 0 view .LVU88
+ 326 0000 0028     		cmp	r0, #0
+ 327 0002 00F09B80 		beq	.L31
+ 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t timeout;
+ 328              		.loc 1 327 1 view .LVU89
+ 329 0006 10B4     		push	{r4}
+ 330              	.LCFI2:
+ARM GAS  /tmp/ccLtUKRp.s 			page 97
+
+
+ 331              		.cfi_def_cfa_offset 4
+ 332              		.cfi_offset 4, -4
+ 333 0008 0346     		mov	r3, r0
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 334              		.loc 1 340 5 is_stmt 1 view .LVU90
+ 335              	.LBB62:
+ 336              	.LBI62:
+ 337              		.file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @file    stm32f7xx_ll_pwr.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief   Header file of PWR LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #ifndef __STM32F7xx_LL_PWR_H
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define __STM32F7xx_LL_PWR_H
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #ifdef __cplusplus
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** extern "C" {
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #endif
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Includes ------------------------------------------------------------------*/
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #include "stm32f7xx.h"
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @addtogroup STM32F7xx_LL_Driver
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #if defined(PWR)
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL PWR
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Private types -------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Private variables ---------------------------------------------------------*/
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Private constants ---------------------------------------------------------*/
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Private macros ------------------------------------------------------------*/
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Exported types ------------------------------------------------------------*/
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Exported constants --------------------------------------------------------*/
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ARM GAS  /tmp/ccLtUKRp.s 			page 98
+
+
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR1_CSBF                    PWR_CR1_CSBF            /*!< Clear standby flag */
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF6                   PWR_CR2_CWUF6           /*!< Clear WKUP pin 6 */
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF5                   PWR_CR2_CWUF5           /*!< Clear WKUP pin 5 */
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF4                   PWR_CR2_CWUF4           /*!< Clear WKUP pin 4 */
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF3                   PWR_CR2_CWUF3           /*!< Clear WKUP pin 3 */
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF2                   PWR_CR2_CWUF2           /*!< Clear WKUP pin 2 */
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF1                   PWR_CR2_CWUF1           /*!< Clear WKUP pin 1 */
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @}
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_WUIF                   PWR_CSR1_WUIF           /*!< Wakeup flag */
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_SBF                    PWR_CSR1_SBF            /*!< Standby flag */
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_PVDO                   PWR_CSR1_PVDO           /*!< Power voltage detector outp
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_BRR                    PWR_CSR1_BRR            /*!< Backup Regulator ready flag
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_VOSRDY                 PWR_CSR1_VOSRDY         /*!< Voltage scaling select flag
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_ODRDY                  PWR_CSR1_ODRDY          /*!< Over-drive mode ready */
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_ODSWRDY                PWR_CSR1_ODSWRDY        /*!< Over-drive mode switching r
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_UDRDY                  PWR_CSR1_UDRDY          /*!< Under-drive ready flag */
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP1                  PWR_CSR2_EWUP1          /*!< Enable WKUP pin 1 */
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP2                  PWR_CSR2_EWUP2          /*!< Enable WKUP pin 2 */
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP3                  PWR_CSR2_EWUP3          /*!< Enable WKUP pin 3 */
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP4                  PWR_CSR2_EWUP4          /*!< Enable WKUP pin 4 */
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP5                  PWR_CSR2_EWUP5          /*!< Enable WKUP pin 5 */
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP6                  PWR_CSR2_EWUP6          /*!< Enable WKUP pin 6 */
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @}
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_MODE_STOP_MAINREGU                     0x00000000U                                  
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE          (PWR_CR1_MRUDS | PWR_CR1_FPDS)               
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_MODE_STOP_LPREGU                       PWR_CR1_LPDS                                 
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE            (PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS)
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_MODE_STANDBY                           PWR_CR1_PDDS                                 
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @}
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_REGU_VOLTAGE_SCALE3         PWR_CR1_VOS_0
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_REGU_VOLTAGE_SCALE2         PWR_CR1_VOS_1
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR1_VOS_0 | PWR_CR1_VOS_1)
+ARM GAS  /tmp/ccLtUKRp.s 			page 99
+
+
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @}
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_REGU_DSMODE_MAIN        0x00000000U                    /*!< Voltage Regulator in mai
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_REGU_DSMODE_LOW_POWER   PWR_CR1_LPDS                   /*!< Voltage Regulator in low
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @}
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_0                  PWR_CR1_PLS_LEV0      /*!< Voltage threshold detected by
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_1                  PWR_CR1_PLS_LEV1      /*!< Voltage threshold detected by
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_2                  PWR_CR1_PLS_LEV2      /*!< Voltage threshold detected by
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_3                  PWR_CR1_PLS_LEV3      /*!< Voltage threshold detected by
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_4                  PWR_CR1_PLS_LEV4      /*!< Voltage threshold detected by
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_5                  PWR_CR1_PLS_LEV5      /*!< Voltage threshold detected by
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_6                  PWR_CR1_PLS_LEV6      /*!< Voltage threshold detected by
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_7                  PWR_CR1_PLS_LEV7      /*!< Voltage threshold detected by
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @}
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN1                 PWR_CSR2_EWUP1        /*!< WKUP pin 1 : PA0  */
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN2                 PWR_CSR2_EWUP2        /*!< WKUP pin 2 : PA2  */
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN3                 PWR_CSR2_EWUP3        /*!< WKUP pin 3 : PC1  */
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN4                 PWR_CSR2_EWUP4        /*!< WKUP pin 4 : PC13 */
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN5                 PWR_CSR2_EWUP5        /*!< WKUP pin 5 : PI8  */
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN6                 PWR_CSR2_EWUP6        /*!< WKUP pin 6 : PI11 */
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @}
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @}
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Exported macro ------------------------------------------------------------*/
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Write a value in PWR register
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @param  __REG__ Register to be written
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @param  __VALUE__ Value to be written in the register
+ARM GAS  /tmp/ccLtUKRp.s 			page 100
+
+
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval None
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Read a value in PWR register
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @param  __REG__ Register to be read
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval Register value
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @}
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @}
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Exported functions --------------------------------------------------------*/
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EF_Configuration Configuration
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @{
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Enable Under Drive Mode
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @rmtoll CR1    UDEN       LL_PWR_EnableUnderDriveMode
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @note  This mode is enabled only with STOP low power mode.
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *        mode is only available when the main Regulator or the low power Regulator 
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *        is in low voltage mode.      
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @note  If the Under-drive mode was enabled, it is automatically disabled after 
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *        exiting Stop mode. 
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *        When the voltage Regulator operates in Under-drive mode, an additional  
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *        startup delay is induced when waking up from Stop mode.
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval None
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   SET_BIT(PWR->CR1, PWR_CR1_UDEN);
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Disable Under Drive Mode
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @rmtoll CR1    UDEN       LL_PWR_DisableUnderDriveMode
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval None
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   CLEAR_BIT(PWR->CR1, PWR_CR1_UDEN);
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Check if Under Drive Mode is enabled
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @rmtoll CR1    UDEN       LL_PWR_IsEnabledUnderDriveMode
+ARM GAS  /tmp/ccLtUKRp.s 			page 101
+
+
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval State of bit (1 or 0).
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   return (READ_BIT(PWR->CR1, PWR_CR1_UDEN) == (PWR_CR1_UDEN));
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Enable Over drive switching
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @rmtoll CR1    ODSWEN       LL_PWR_EnableOverDriveSwitching
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval None
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   SET_BIT(PWR->CR1, PWR_CR1_ODSWEN);
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Disable Over drive switching
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @rmtoll CR1    ODSWEN       LL_PWR_DisableOverDriveSwitching
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval None
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   CLEAR_BIT(PWR->CR1, PWR_CR1_ODSWEN);
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Check if Over drive switching is enabled
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @rmtoll CR1    ODSWEN       LL_PWR_IsEnabledOverDriveSwitching
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval State of bit (1 or 0).
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   return (READ_BIT(PWR->CR1, PWR_CR1_ODSWEN) == (PWR_CR1_ODSWEN));
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Enable Over drive Mode
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @rmtoll CR1    ODEN       LL_PWR_EnableOverDriveMode
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval None
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   SET_BIT(PWR->CR1, PWR_CR1_ODEN);
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Disable Over drive Mode
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @rmtoll CR1    ODEN       LL_PWR_DisableOverDriveMode
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval None
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   CLEAR_BIT(PWR->CR1, PWR_CR1_ODEN);
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ARM GAS  /tmp/ccLtUKRp.s 			page 102
+
+
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Check if Over drive switching is enabled
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @rmtoll CR1    ODEN       LL_PWR_IsEnabledOverDriveMode
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval State of bit (1 or 0).
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   return (READ_BIT(PWR->CR1, PWR_CR1_ODEN) == (PWR_CR1_ODEN));
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Set the main internal Regulator output voltage
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @rmtoll CR1    VOS       LL_PWR_SetRegulVoltageScaling
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @param  VoltageScaling This parameter can be one of the following values:
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval None
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** 
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /**
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @brief  Get the main internal Regulator output voltage
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @rmtoll CR1    VOS       LL_PWR_GetRegulVoltageScaling
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   * @retval Returned value can be one of the following values:
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   */
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+ 338              		.loc 4 310 26 view .LVU91
+ 339              	.LBB63:
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h ****   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
+ 340              		.loc 4 312 3 view .LVU92
+ 341              		.loc 4 312 21 is_stmt 0 view .LVU93
+ 342 000a 4E4A     		ldr	r2, .L54
+ 343 000c 1268     		ldr	r2, [r2]
+ 344              		.loc 4 312 10 view .LVU94
+ 345 000e 02F44042 		and	r2, r2, #49152
+ 346              	.LBE63:
+ 347              	.LBE62:
+ 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 348              		.loc 1 340 7 view .LVU95
+ 349 0012 B2F5404F 		cmp	r2, #49152
+ 350 0016 14D0     		beq	.L52
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 351              		.loc 1 385 10 is_stmt 1 view .LVU96
+ 352              	.LBB64:
+ 353              	.LBI64:
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 354              		.loc 4 310 26 view .LVU97
+ 355              	.LBB65:
+ 356              		.loc 4 312 3 view .LVU98
+ARM GAS  /tmp/ccLtUKRp.s 			page 103
+
+
+ 357              		.loc 4 312 21 is_stmt 0 view .LVU99
+ 358 0018 4A4A     		ldr	r2, .L54
+ 359 001a 1268     		ldr	r2, [r2]
+ 360              		.loc 4 312 10 view .LVU100
+ 361 001c 02F44042 		and	r2, r2, #49152
+ 362              	.LBE65:
+ 363              	.LBE64:
+ 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 364              		.loc 1 385 12 view .LVU101
+ 365 0020 B2F5004F 		cmp	r2, #32768
+ 366 0024 41D0     		beq	.L53
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 367              		.loc 1 419 7 is_stmt 1 view .LVU102
+ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 368              		.loc 1 419 9 is_stmt 0 view .LVU103
+ 369 0026 484A     		ldr	r2, .L54+4
+ 370 0028 9042     		cmp	r0, r2
+ 371 002a 64D8     		bhi	.L43
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 372              		.loc 1 424 12 is_stmt 1 view .LVU104
+ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 373              		.loc 1 424 14 is_stmt 0 view .LVU105
+ 374 002c 474A     		ldr	r2, .L54+8
+ 375 002e 9042     		cmp	r0, r2
+ 376 0030 7ED8     		bhi	.L44
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 377              		.loc 1 429 12 is_stmt 1 view .LVU106
+ 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 378              		.loc 1 429 14 is_stmt 0 view .LVU107
+ 379 0032 474A     		ldr	r2, .L54+12
+ 380 0034 9042     		cmp	r0, r2
+ 381 0036 7DD8     		bhi	.L45
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 382              		.loc 1 436 9 is_stmt 1 view .LVU108
+ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 383              		.loc 1 436 11 is_stmt 0 view .LVU109
+ 384 0038 464A     		ldr	r2, .L54+16
+ 385 003a 9042     		cmp	r0, r2
+ 386 003c 7CD8     		bhi	.L46
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 387              		.loc 1 330 12 view .LVU110
+ 388 003e 0020     		movs	r0, #0
+ 389              	.LVL17:
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 390              		.loc 1 330 12 view .LVU111
+ 391 0040 5AE0     		b	.L28
+ 392              	.LVL18:
+ 393              	.L52:
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 394              		.loc 1 342 7 is_stmt 1 view .LVU112
+ 395              	.LBB66:
+ 396              	.LBI66:
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** {
+ 397              		.loc 4 283 26 view .LVU113
+ 398              	.LBB67:
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 399              		.loc 4 285 3 view .LVU114
+ARM GAS  /tmp/ccLtUKRp.s 			page 104
+
+
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 400              		.loc 4 285 11 is_stmt 0 view .LVU115
+ 401 0042 404A     		ldr	r2, .L54
+ 402 0044 1068     		ldr	r0, [r2]
+ 403              	.LVL19:
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** }
+ 404              		.loc 4 285 11 view .LVU116
+ 405              	.LBE67:
+ 406              	.LBE66:
+ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 407              		.loc 1 342 9 view .LVU117
+ 408 0046 10F48030 		ands	r0, r0, #65536
+ 409 004a 03D0     		beq	.L27
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           {
+ 410              		.loc 1 344 11 is_stmt 1 view .LVU118
+ 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           {
+ 411              		.loc 1 344 13 is_stmt 0 view .LVU119
+ 412 004c 424A     		ldr	r2, .L54+20
+ 413 004e 9342     		cmp	r3, r2
+ 414 0050 29D9     		bls	.L32
+ 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           }
+ 415              		.loc 1 347 21 view .LVU120
+ 416 0052 0720     		movs	r0, #7
+ 417              	.L27:
+ 418              	.LVL20:
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 419              		.loc 1 355 7 is_stmt 1 view .LVU121
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 420              		.loc 1 355 68 is_stmt 0 view .LVU122
+ 421 0054 B0FA80F2 		clz	r2, r0
+ 422 0058 5209     		lsrs	r2, r2, #5
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 423              		.loc 1 355 56 view .LVU123
+ 424 005a 404C     		ldr	r4, .L54+24
+ 425 005c A342     		cmp	r3, r4
+ 426 005e 94BF     		ite	ls
+ 427 0060 0021     		movls	r1, #0
+ 428 0062 02F00101 		andhi	r1, r2, #1
+ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 429              		.loc 1 355 9 view .LVU124
+ 430 0066 0029     		cmp	r1, #0
+ 431 0068 33D1     		bne	.L33
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 432              		.loc 1 360 12 is_stmt 1 view .LVU125
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 433              		.loc 1 360 61 is_stmt 0 view .LVU126
+ 434 006a 374C     		ldr	r4, .L54+4
+ 435 006c A342     		cmp	r3, r4
+ 436 006e 94BF     		ite	ls
+ 437 0070 0021     		movls	r1, #0
+ 438 0072 02F00101 		andhi	r1, r2, #1
+ 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 439              		.loc 1 360 14 view .LVU127
+ 440 0076 71BB     		cbnz	r1, .L34
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 441              		.loc 1 365 12 is_stmt 1 view .LVU128
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ARM GAS  /tmp/ccLtUKRp.s 			page 105
+
+
+ 442              		.loc 1 365 61 is_stmt 0 view .LVU129
+ 443 0078 344C     		ldr	r4, .L54+8
+ 444 007a A342     		cmp	r3, r4
+ 445 007c 94BF     		ite	ls
+ 446 007e 0021     		movls	r1, #0
+ 447 0080 02F00101 		andhi	r1, r2, #1
+ 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 448              		.loc 1 365 14 view .LVU130
+ 449 0084 49BB     		cbnz	r1, .L35
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 450              		.loc 1 370 12 is_stmt 1 view .LVU131
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 451              		.loc 1 370 61 is_stmt 0 view .LVU132
+ 452 0086 324C     		ldr	r4, .L54+12
+ 453 0088 A342     		cmp	r3, r4
+ 454 008a 94BF     		ite	ls
+ 455 008c 0021     		movls	r1, #0
+ 456 008e 02F00101 		andhi	r1, r2, #1
+ 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 457              		.loc 1 370 14 view .LVU133
+ 458 0092 21BB     		cbnz	r1, .L36
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 459              		.loc 1 377 9 is_stmt 1 view .LVU134
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 460              		.loc 1 377 58 is_stmt 0 view .LVU135
+ 461 0094 2F49     		ldr	r1, .L54+16
+ 462 0096 8B42     		cmp	r3, r1
+ 463 0098 94BF     		ite	ls
+ 464 009a 0022     		movls	r2, #0
+ 465 009c 02F00102 		andhi	r2, r2, #1
+ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 466              		.loc 1 377 11 view .LVU136
+ 467 00a0 52B3     		cbz	r2, .L28
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         }
+ 468              		.loc 1 380 19 view .LVU137
+ 469 00a2 0120     		movs	r0, #1
+ 470              	.LVL21:
+ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         }
+ 471              		.loc 1 380 19 view .LVU138
+ 472 00a4 28E0     		b	.L28
+ 473              	.LVL22:
+ 474              	.L32:
+ 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****           }
+ 475              		.loc 1 352 21 view .LVU139
+ 476 00a6 0620     		movs	r0, #6
+ 477 00a8 D4E7     		b	.L27
+ 478              	.LVL23:
+ 479              	.L53:
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 480              		.loc 1 387 7 is_stmt 1 view .LVU140
+ 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 481              		.loc 1 387 9 is_stmt 0 view .LVU141
+ 482 00aa 02F10F62 		add	r2, r2, #149946368
+ 483 00ae 02F5A342 		add	r2, r2, #20864
+ 484 00b2 9042     		cmp	r0, r2
+ 485 00b4 15D8     		bhi	.L38
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ARM GAS  /tmp/ccLtUKRp.s 			page 106
+
+
+ 486              		.loc 1 392 12 is_stmt 1 view .LVU142
+ 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 487              		.loc 1 392 14 is_stmt 0 view .LVU143
+ 488 00b6 244A     		ldr	r2, .L54+4
+ 489 00b8 9042     		cmp	r0, r2
+ 490 00ba 14D8     		bhi	.L39
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 491              		.loc 1 397 12 is_stmt 1 view .LVU144
+ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 492              		.loc 1 397 14 is_stmt 0 view .LVU145
+ 493 00bc 234A     		ldr	r2, .L54+8
+ 494 00be 9042     		cmp	r0, r2
+ 495 00c0 13D8     		bhi	.L40
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 496              		.loc 1 402 12 is_stmt 1 view .LVU146
+ 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 497              		.loc 1 402 14 is_stmt 0 view .LVU147
+ 498 00c2 234A     		ldr	r2, .L54+12
+ 499 00c4 9042     		cmp	r0, r2
+ 500 00c6 12D8     		bhi	.L41
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 501              		.loc 1 409 9 is_stmt 1 view .LVU148
+ 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         {
+ 502              		.loc 1 409 11 is_stmt 0 view .LVU149
+ 503 00c8 224A     		ldr	r2, .L54+16
+ 504 00ca 9042     		cmp	r0, r2
+ 505 00cc 11D8     		bhi	.L42
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 506              		.loc 1 330 12 view .LVU150
+ 507 00ce 0020     		movs	r0, #0
+ 508              	.LVL24:
+ 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 509              		.loc 1 330 12 view .LVU151
+ 510 00d0 12E0     		b	.L28
+ 511              	.LVL25:
+ 512              	.L33:
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 513              		.loc 1 358 17 view .LVU152
+ 514 00d2 0520     		movs	r0, #5
+ 515              	.LVL26:
+ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 516              		.loc 1 358 17 view .LVU153
+ 517 00d4 10E0     		b	.L28
+ 518              	.LVL27:
+ 519              	.L34:
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 520              		.loc 1 363 17 view .LVU154
+ 521 00d6 0420     		movs	r0, #4
+ 522              	.LVL28:
+ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 523              		.loc 1 363 17 view .LVU155
+ 524 00d8 0EE0     		b	.L28
+ 525              	.LVL29:
+ 526              	.L35:
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 527              		.loc 1 368 17 view .LVU156
+ 528 00da 0320     		movs	r0, #3
+ARM GAS  /tmp/ccLtUKRp.s 			page 107
+
+
+ 529              	.LVL30:
+ 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 530              		.loc 1 368 17 view .LVU157
+ 531 00dc 0CE0     		b	.L28
+ 532              	.LVL31:
+ 533              	.L36:
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 534              		.loc 1 373 17 view .LVU158
+ 535 00de 0220     		movs	r0, #2
+ 536              	.LVL32:
+ 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 537              		.loc 1 373 17 view .LVU159
+ 538 00e0 0AE0     		b	.L28
+ 539              	.LVL33:
+ 540              	.L38:
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 541              		.loc 1 390 17 view .LVU160
+ 542 00e2 0520     		movs	r0, #5
+ 543              	.LVL34:
+ 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 544              		.loc 1 390 17 view .LVU161
+ 545 00e4 08E0     		b	.L28
+ 546              	.LVL35:
+ 547              	.L39:
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 548              		.loc 1 395 17 view .LVU162
+ 549 00e6 0420     		movs	r0, #4
+ 550              	.LVL36:
+ 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 551              		.loc 1 395 17 view .LVU163
+ 552 00e8 06E0     		b	.L28
+ 553              	.LVL37:
+ 554              	.L40:
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 555              		.loc 1 400 17 view .LVU164
+ 556 00ea 0320     		movs	r0, #3
+ 557              	.LVL38:
+ 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 558              		.loc 1 400 17 view .LVU165
+ 559 00ec 04E0     		b	.L28
+ 560              	.LVL39:
+ 561              	.L41:
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 562              		.loc 1 405 17 view .LVU166
+ 563 00ee 0220     		movs	r0, #2
+ 564              	.LVL40:
+ 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 565              		.loc 1 405 17 view .LVU167
+ 566 00f0 02E0     		b	.L28
+ 567              	.LVL41:
+ 568              	.L42:
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         }
+ 569              		.loc 1 412 19 view .LVU168
+ 570 00f2 0120     		movs	r0, #1
+ 571              	.LVL42:
+ 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         }
+ 572              		.loc 1 412 19 view .LVU169
+ARM GAS  /tmp/ccLtUKRp.s 			page 108
+
+
+ 573 00f4 00E0     		b	.L28
+ 574              	.LVL43:
+ 575              	.L43:
+ 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 576              		.loc 1 422 17 view .LVU170
+ 577 00f6 0420     		movs	r0, #4
+ 578              	.LVL44:
+ 579              	.L28:
+ 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 580              		.loc 1 445 5 is_stmt 1 view .LVU171
+ 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 581              		.loc 1 447 7 view .LVU172
+ 582              	.LBB68:
+ 583              	.LBI68:
+ 584              		.file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h"
+   1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+   2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   ******************************************************************************
+   3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @file    stm32f7xx_ll_system.h
+   4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @author  MCD Application Team
+   5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief   Header file of SYSTEM LL module.
+   6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   ******************************************************************************
+   7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @attention
+   8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *
+   9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * Copyright (c) 2017 STMicroelectronics.
+  10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * All rights reserved.
+  11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *
+  12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * This software is licensed under terms that can be found in the LICENSE file
+  13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * in the root directory of this software component.
+  14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *
+  16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   ******************************************************************************
+  17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   @verbatim
+  18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   ==============================================================================
+  19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****                      ##### How to use this driver #####
+  20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   ==============================================================================
+  21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****     [..]
+  22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****     The LL SYSTEM driver contains a set of generic APIs that can be
+  23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****     used by user:
+  24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****       (+) Some of the FLASH features need to be handled in the SYSTEM file.
+  25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****       (+) Access to DBGCMU registers
+  26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****       (+) Access to SYSCFG registers
+  27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   @endverbatim
+  29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   ******************************************************************************
+  30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+  31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Define to prevent recursive inclusion -------------------------------------*/
+  33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #ifndef __STM32F7xx_LL_SYSTEM_H
+  34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define __STM32F7xx_LL_SYSTEM_H
+  35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #ifdef __cplusplus
+  37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** extern "C" {
+  38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif
+  39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Includes ------------------------------------------------------------------*/
+  41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #include "stm32f7xx.h"
+  42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ARM GAS  /tmp/ccLtUKRp.s 			page 109
+
+
+  43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @addtogroup STM32F7xx_LL_Driver
+  44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+  45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+  46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
+  48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL SYSTEM
+  50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+  51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+  52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Private types -------------------------------------------------------------*/
+  54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Private variables ---------------------------------------------------------*/
+  55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Private constants ---------------------------------------------------------*/
+  57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+  58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+  59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+  60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+  62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+  63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+  64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Private macros ------------------------------------------------------------*/
+  66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Exported types ------------------------------------------------------------*/
+  68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Exported constants --------------------------------------------------------*/
+  69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+  70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+  71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+  72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
+  74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{
+  75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */
+  76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_REMAP_BOOT0               0x00000000U                                         /*!
+  77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_REMAP_BOOT1               SYSCFG_MEMRMP_MEM_BOOT                              /*!
+  78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+  79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+  80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+  81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_MEMRMP_SWP_FB)
+  84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
+  85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+  86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+  87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_BANKMODE_BANK1          0x00000000U              /*!< Flash Bank 1 base address m
+  88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****                                                                       and Flash Bank 2 base address
+  89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_BANKMODE_BANK2          SYSCFG_MEMRMP_SWP_FB     /*!< Flash Bank 2 base address m
+  91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****                                                                       and Flash Bank 1 base address
+  92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+  93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+  94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+  95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_MEMRMP_SWP_FB */
+  96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+  97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_MII_RMII_SEL)
+  98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****  /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
+  99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{
+ARM GAS  /tmp/ccLtUKRp.s 			page 110
+
+
+ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */
+ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_PMC_ETHMII               0x00000000U                                         /*!<
+ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_PMC_ETHRMII              (uint32_t)SYSCFG_PMC_MII_RMII_SEL                   /*!<
+ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_MII_RMII_SEL */
+ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+ 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_I2C1_FMP)
+ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1        SYSCFG_PMC_I2C1_FMP       /*!< Enable Fast Mode Plus
+ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2        SYSCFG_PMC_I2C2_FMP       /*!< Enable Fast Mode Plus
+ 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3        SYSCFG_PMC_I2C3_FMP       /*!< Enable Fast Mode Plus
+ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_I2C1_FMP */
+ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_I2C4_FMP)
+ 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4        SYSCFG_PMC_I2C4_FMP       /*!< Enable Fast Mode Plus
+ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_I2C4_FMP */
+ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_I2C_PB6_FMP)
+ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6         SYSCFG_PMC_I2C_PB6_FMP    /*!< Enable Fast Mode Plus
+ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7         SYSCFG_PMC_I2C_PB7_FMP    /*!< Enable Fast Mode Plus
+ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8         SYSCFG_PMC_I2C_PB8_FMP    /*!< Enable Fast Mode Plus
+ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9         SYSCFG_PMC_I2C_PB9_FMP    /*!< Enable Fast Mode Plus
+ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_I2C_PB6_FMP */
+ 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+ 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTA               0U               /*!< EXTI PORT A                       
+ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTB               1U               /*!< EXTI PORT B                       
+ 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTC               2U               /*!< EXTI PORT C                       
+ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTD               3U               /*!< EXTI PORT D                       
+ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTE               4U               /*!< EXTI PORT E                       
+ 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(GPIOF)
+ 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTF               5U               /*!< EXTI PORT F                       
+ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* GPIOF */
+ 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(GPIOG)
+ 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTG               6U               /*!< EXTI PORT G                       
+ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* GPIOG */
+ 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTH               7U               /*!< EXTI PORT H                       
+ 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(GPIOI)
+ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTI               8U               /*!< EXTI PORT I                       
+ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* GPIOI */
+ 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(GPIOJ)
+ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTJ               9U               /*!< EXTI PORT J                       
+ 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* GPIOJ */
+ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(GPIOK)
+ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTK               10U              /*!< EXTI PORT k                       
+ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* GPIOK */
+ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ARM GAS  /tmp/ccLtUKRp.s 			page 111
+
+
+ 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+ 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE0               (0x000FU << 16U | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0]
+ 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE1               (0x00F0U << 16U | 0U)  /*!< EXTI_POSITION_4  | EXTICR[0]
+ 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE2               (0x0F00U << 16U | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0]
+ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE3               (0xF000U << 16U | 0U)  /*!< EXTI_POSITION_12 | EXTICR[0]
+ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE4               (0x000FU << 16U | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1]
+ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE5               (0x00F0U << 16U | 1U)  /*!< EXTI_POSITION_4  | EXTICR[1]
+ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE6               (0x0F00U << 16U | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1]
+ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE7               (0xF000U << 16U | 1U)  /*!< EXTI_POSITION_12 | EXTICR[1]
+ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE8               (0x000FU << 16U | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2]
+ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE9               (0x00F0U << 16U | 2U)  /*!< EXTI_POSITION_4  | EXTICR[2]
+ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE10              (0x0F00U << 16U | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2]
+ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE11              (0xF000U << 16U | 2U)  /*!< EXTI_POSITION_12 | EXTICR[2]
+ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE12              (0x000FU << 16U | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3]
+ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE13              (0x00F0U << 16U | 3U)  /*!< EXTI_POSITION_4  | EXTICR[3]
+ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE14              (0x0F00U << 16U | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3]
+ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE15              (0xF000U << 16U | 3U)  /*!< EXTI_POSITION_12 | EXTICR[3]
+ 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_CBR_CLL)
+ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CBR_CLL     /*!< Enables and locks the Lockup out
+ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****                                                                    lockup state) of Cortex-M7 with 
+ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CBR_PVDL    /*!< Enables and locks the PVD connec
+ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****                                                                    It also locks (write protect) th
+ 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****                                                                    of the power controller */
+ 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_CBR_CLL */
+ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_CMP_PD SYSCFG CMP PD
+ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_DISABLE_CMP_PD          0x00000000U             /*!< I/O compensation cell power-
+ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_ENABLE_CMP_PD           SYSCFG_CMPCR_CMP_PD     /*!< I/O compensation cell enable
+ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRA
+ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRA
+ 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRA
+ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRA
+ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRA
+ 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ARM GAS  /tmp/ccLtUKRp.s 			page 112
+
+
+ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP          /*!< TIM2 counter 
+ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP          /*!< TIM3 counter 
+ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1_FZ_DBG_TIM4_STOP          /*!< TIM4 counter 
+ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1_FZ_DBG_TIM5_STOP          /*!< TIM5 counter 
+ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP          /*!< TIM6 counter 
+ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP          /*!< TIM7 counter 
+ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1_FZ_DBG_TIM12_STOP         /*!< TIM12 counter
+ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1_FZ_DBG_TIM13_STOP         /*!< TIM13 counter
+ 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1_FZ_DBG_TIM14_STOP         /*!< TIM14 counter
+ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1_FZ_DBG_LPTIM1_STOP        /*!< LPTIIM1 count
+ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP           /*!< RTC counter s
+ 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP          /*!< Debug Window 
+ 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP          /*!< Debug Indepen
+ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS ti
+ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS ti
+ 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS ti
+ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
+ 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C4_STOP      DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS ti
+ 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
+ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_CAN1_STOP       DBGMCU_APB1_FZ_DBG_CAN1_STOP         /*!< CAN1 debug st
+ 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
+ 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_CAN2_STOP       DBGMCU_APB1_FZ_DBG_CAN2_STOP         /*!< CAN2 debug st
+ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
+ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
+ 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_CAN3_STOP       DBGMCU_APB1_FZ_DBG_CAN3_STOP         /*!< CAN3 debug st
+ 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /*DBGMCU_APB1_FZ_DBG_CAN3_STOP*/
+ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2_FZ_DBG_TIM1_STOP     /*!< TIM1 counter stopp
+ 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2_FZ_DBG_TIM8_STOP     /*!< TIM8 counter stopp
+ 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_APB2_FZ_DBG_TIM9_STOP     /*!< TIM9 counter stopp
+ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_APB2_FZ_DBG_TIM10_STOP    /*!< TIM10 counter stop
+ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_APB2_FZ_DBG_TIM11_STOP    /*!< TIM11 counter stop
+ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
+ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
+ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
+ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
+ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
+ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
+ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
+ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
+ARM GAS  /tmp/ccLtUKRp.s 			page 113
+
+
+ 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */
+ 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */
+ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS   /*!< FLASH ten wait states */
+ 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS   /*!< FLASH eleven wait states *
+ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS   /*!< FLASH twelve wait states *
+ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS   /*!< FLASH thirteen wait states
+ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS   /*!< FLASH fourteen wait states
+ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS   /*!< FLASH fifteen wait states 
+ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Exported macro ------------------------------------------------------------*/
+ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Exported functions --------------------------------------------------------*/
+ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+ 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Enables the FMC Memory Mapping Swapping
+ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_EnableFMCMemorySwapping
+ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @note   SDRAM is accessible at 0x60000000 and NOR/RAM
+ 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         is accessible at 0xC0000000
+ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
+ 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
+ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Disables the FMC Memory Mapping Swapping
+ 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_DisableFMCMemorySwapping
+ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @note   SDRAM is accessible at 0xC0000000 (default mapping)
+ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         and NOR/RAM is accessible at 0x60000000 (default mapping)
+ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
+ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
+ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Enables the Compensation Cell
+ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_EnableCompensationCell
+ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @note   The I/O compensation cell can be used only when the device supply
+ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         voltage ranges from 2.4 to 3.6 V
+ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ARM GAS  /tmp/ccLtUKRp.s 			page 114
+
+
+ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
+ 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
+ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Disables the Compensation Cell
+ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_DisableCompensationCell
+ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @note   The I/O compensation cell can be used only when the device supply
+ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         voltage ranges from 2.4 to 3.6 V
+ 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
+ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
+ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Get Compensation Cell ready Flag
+ 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_CMPCR READY  LL_SYSCFG_IsActiveFlag_CMPCR
+ 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval State of bit (1 or 0).
+ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
+ 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
+ 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Get the memory boot mapping as configured by user
+ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_MEMRMP MEM_BOOT      LL_SYSCFG_GetRemapMemoryBoot
+ 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval Returned value can be one of the following values:
+ 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *           @arg @ref LL_SYSCFG_REMAP_BOOT0
+ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *           @arg @ref LL_SYSCFG_REMAP_BOOT1
+ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *
+ 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         (*) value not defined in all devices
+ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemoryBoot(void)
+ 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT));
+ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_MII_RMII_SEL)
+ 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Select Ethernet PHY interface
+ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_SetPHYInterface
+ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  Interface This parameter can be one of the following values:
+ 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_PMC_ETHMII
+ 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_PMC_ETHRMII
+ 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
+ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
+ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ARM GAS  /tmp/ccLtUKRp.s 			page 115
+
+
+ 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Get Ethernet PHY interface
+ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_GetPHYInterface
+ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval Returned value can be one of the following values:
+ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_PMC_ETHMII
+ 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_PMC_ETHRMII
+ 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
+ 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
+ 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_MII_RMII_SEL */
+ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_MEMRMP_SWP_FB)
+ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
+ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_SetFlashBankMode
+ 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  Bank This parameter can be one of the following values:
+ 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+ 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
+ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB, Bank);
+ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
+ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_GetFlashBankMode
+ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval Returned value can be one of the following values:
+ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+ 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+ 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
+ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB));
+ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_MEMRMP_SWP_FB */
+ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_I2C1_FMP)
+ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Enable the I2C fast mode plus driving capability.
+ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_PMC I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
+ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_PMC I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
+ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+ 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
+ARM GAS  /tmp/ccLtUKRp.s 			page 116
+
+
+ 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *
+ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         (*) value not defined in all devices
+ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   SET_BIT(SYSCFG->PMC, ConfigFastModePlus);
+ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Disable the I2C fast mode plus driving capability.
+ 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_PMC I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
+ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_PMC I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
+ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+ 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+ 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+ 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+ 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
+ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         (*) value not defined in all devices
+ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   CLEAR_BIT(SYSCFG->PMC, ConfigFastModePlus);
+ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_I2C1_FMP */
+ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Configure source input for the EXTI external interrupt.
+ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
+ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
+ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
+ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
+ 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  Port This parameter can be one of the following values:
+ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTA
+ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTB
+ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTC
+ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTD
+ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTE
+ 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTF
+ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTG
+ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTH
+ 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTI
+ 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTJ
+ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTK
+ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *
+ 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         (*) value not defined in all devices
+ 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  Line This parameter can be one of the following values:
+ 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE0
+ 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE1
+ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE2
+ 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE3
+ARM GAS  /tmp/ccLtUKRp.s 			page 117
+
+
+ 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE4
+ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE5
+ 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE6
+ 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE7
+ 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE8
+ 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE9
+ 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE10
+ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE11
+ 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE12
+ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE13
+ 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE14
+ 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE15
+ 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+ 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
+ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Get the configured defined for specific EXTI Line
+ 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
+ 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
+ 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
+ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
+ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  Line This parameter can be one of the following values:
+ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE0
+ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE1
+ 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE2
+ 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE3
+ 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE4
+ 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE5
+ 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE6
+ 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE7
+ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE8
+ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE9
+ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE10
+ 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE11
+ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE12
+ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE13
+ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE14
+ 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_LINE15
+ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval Returned value can be one of the following values:
+ 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTA
+ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTB
+ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTC
+ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTD
+ 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTE
+ 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTF
+ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTG
+ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTH
+ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTI
+ 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTJ
+ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_EXTI_PORTK
+ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         (*) value not defined in all devices
+ 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+ARM GAS  /tmp/ccLtUKRp.s 			page 118
+
+
+ 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 1
+ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_CBR_CLL)
+ 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Set connections to TIM1/8/15/16/17 Break inputs
+ 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_CBR CLL             LL_SYSCFG_SetTIMBreakInputs\n
+ 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_CBR PVDL            LL_SYSCFG_SetTIMBreakInputs
+ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  Break This parameter can be a combination of the following values:
+ 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+ 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   MODIFY_REG(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL, Break);
+ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Get connections to TIM1/8/15/16/17 Break inputs
+ 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_CBR CLL             LL_SYSCFG_GetTIMBreakInputs\n
+ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         SYSCFG_CBR PVDL            LL_SYSCFG_GetTIMBreakInputs
+ 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval Returned value can be can be a combination of the following values:
+ 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   return (uint32_t)(READ_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL));
+ 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_CBR_CLL */
+ 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Return the device identifier
+ 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @note For STM32F75xxx and STM32F74xxx devices, the device ID is 0x449
+ 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @note For STM32F77xxx and STM32F76xxx devices, the device ID is 0x451
+ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @note For STM32F72xxx and STM32F73xxx devices, the device ID is 0x452
+ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
+ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+ 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+ 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Return the device revision identifier
+ 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @note This field indicates the revision of the device.
+ARM GAS  /tmp/ccLtUKRp.s 			page 119
+
+
+ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****           For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
+ 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
+ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+ 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+ 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Enable the Debug Module during SLEEP mode
+ 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
+ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+ 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Disable the Debug Module during SLEEP mode
+ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
+ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+ 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+ 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Enable the Debug Module during STOP mode
+ 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
+ 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Disable the Debug Module during STOP mode
+ 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
+ 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+ 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Enable the Debug Module during STANDBY mode
+ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
+ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+ 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+ARM GAS  /tmp/ccLtUKRp.s 			page 120
+
+
+ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Disable the Debug Module during STANDBY mode
+ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
+ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Set Trace pin assignment control
+ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
+ 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
+ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  PinAssignment This parameter can be one of the following values:
+ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_TRACE_NONE
+ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+ 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Get Trace pin assignment control
+ 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
+ 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
+ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval Returned value can be one of the following values:
+ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_TRACE_NONE
+ 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Freeze APB1 peripherals (group1 peripherals)
+ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_LPTIM1_STOP         LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ARM GAS  /tmp/ccLtUKRp.s 			page 121
+
+
+ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph
+ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+ 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+ 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+ 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+ 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+ 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+ 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
+ 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
+ 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
+ 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *
+ 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         (*) value not defined in all devices.
+ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   SET_BIT(DBGMCU->APB1FZ, Periphs);
+ 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
+ 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_LPTIM1_STOP         LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ARM GAS  /tmp/ccLtUKRp.s 			page 122
+
+
+ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+ 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+ 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+ 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+ 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+ 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+ 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+ 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+ 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
+ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
+ 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+ 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
+ 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         (*) value not defined in all devices.
+ 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+ 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
+ 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Freeze APB2 peripherals
+ 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
+ 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+ 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
+ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
+ 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
+ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *
+ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         (*) value not defined in all devices.
+ 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   SET_BIT(DBGMCU->APB2FZ, Periphs);
+ 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ARM GAS  /tmp/ccLtUKRp.s 			page 123
+
+
+ 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Unfreeze APB2 peripherals
+ 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  Periphs This parameter can be a combination of the following values:
+ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+ 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
+ 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
+ 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
+ 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *
+ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         (*) value not defined in all devices.
+ 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+ 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @}
+ 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_FLASH FLASH
+ 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @{
+ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Set FLASH Latency
+ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
+ 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @param  Latency This parameter can be one of the following values:
+ 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_0
+ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_1
+ 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_2
+ 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_3
+ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_4
+ 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_5
+ 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_6
+ 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_7
+ 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_8
+ 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_9
+ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_10
+ 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_11
+ 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_12
+ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_13
+ 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_14
+ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_15
+ 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval None
+ 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+ 585              		.loc 5 891 22 view .LVU173
+ 586              	.LBB69:
+ 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+ 587              		.loc 5 893 3 view .LVU174
+ 588 00f8 194A     		ldr	r2, .L54+28
+ARM GAS  /tmp/ccLtUKRp.s 			page 124
+
+
+ 589 00fa 1368     		ldr	r3, [r2]
+ 590              	.LVL45:
+ 591              		.loc 5 893 3 is_stmt 0 view .LVU175
+ 592 00fc 23F00F03 		bic	r3, r3, #15
+ 593 0100 0343     		orrs	r3, r3, r0
+ 594 0102 1360     		str	r3, [r2]
+ 595              	.LVL46:
+ 596              		.loc 5 893 3 view .LVU176
+ 597              	.LBE69:
+ 598              	.LBE68:
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       do
+ 599              		.loc 1 451 7 is_stmt 1 view .LVU177
+ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       do
+ 600              		.loc 1 451 15 is_stmt 0 view .LVU178
+ 601 0104 0221     		movs	r1, #2
+ 602              	.LVL47:
+ 603              	.L30:
+ 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 604              		.loc 1 452 7 is_stmt 1 discriminator 1 view .LVU179
+ 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       timeout--;
+ 605              		.loc 1 455 7 discriminator 1 view .LVU180
+ 606              	.LBB70:
+ 607              	.LBI70:
+ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** }
+ 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** 
+ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /**
+ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @brief  Get FLASH Latency
+ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
+ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   * @retval Returned value can be one of the following values:
+ 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_0
+ 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_1
+ 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_2
+ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_3
+ 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_4
+ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_5
+ 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_6
+ 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_7
+ 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_8
+ 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_9
+ 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_10
+ 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_11
+ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_12
+ 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_13
+ 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_14
+ 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   *         @arg @ref LL_FLASH_LATENCY_15
+ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   */
+ 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+ 608              		.loc 5 917 26 discriminator 1 view .LVU181
+ 609              	.LBB71:
+ 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** {
+ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h ****   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+ 610              		.loc 5 919 3 discriminator 1 view .LVU182
+ 611              		.loc 5 919 21 is_stmt 0 discriminator 1 view .LVU183
+ 612 0106 164B     		ldr	r3, .L54+28
+ 613 0108 1B68     		ldr	r3, [r3]
+ 614              		.loc 5 919 10 discriminator 1 view .LVU184
+ 615 010a 03F00F03 		and	r3, r3, #15
+ARM GAS  /tmp/ccLtUKRp.s 			page 125
+
+
+ 616              	.LVL48:
+ 617              		.loc 5 919 10 discriminator 1 view .LVU185
+ 618              	.LBE71:
+ 619              	.LBE70:
+ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       } while ((getlatency != latency) && (timeout > 0));
+ 620              		.loc 1 456 7 is_stmt 1 discriminator 1 view .LVU186
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 621              		.loc 1 457 15 discriminator 1 view .LVU187
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 622              		.loc 1 457 52 is_stmt 0 discriminator 1 view .LVU188
+ 623 010e 0139     		subs	r1, r1, #1
+ 624              	.LVL49:
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 625              		.loc 1 457 52 discriminator 1 view .LVU189
+ 626 0110 14BF     		ite	ne
+ 627 0112 0122     		movne	r2, #1
+ 628 0114 0022     		moveq	r2, #0
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 629              		.loc 1 457 40 discriminator 1 view .LVU190
+ 630 0116 9842     		cmp	r0, r3
+ 631 0118 0CBF     		ite	eq
+ 632 011a 0022     		moveq	r2, #0
+ 633 011c 02F00102 		andne	r2, r2, #1
+ 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 634              		.loc 1 457 7 discriminator 1 view .LVU191
+ 635 0120 002A     		cmp	r2, #0
+ 636 0122 F0D1     		bne	.L30
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 637              		.loc 1 459 7 is_stmt 1 view .LVU192
+ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 638              		.loc 1 459 9 is_stmt 0 view .LVU193
+ 639 0124 9842     		cmp	r0, r3
+ 640 0126 0BD0     		beq	.L47
+ 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 641              		.loc 1 461 16 view .LVU194
+ 642 0128 0120     		movs	r0, #1
+ 643              	.LVL50:
+ 644              	.L25:
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 645              		.loc 1 469 3 is_stmt 1 view .LVU195
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 646              		.loc 1 470 1 is_stmt 0 view .LVU196
+ 647 012a 5DF8044B 		ldr	r4, [sp], #4
+ 648              	.LCFI3:
+ 649              		.cfi_remember_state
+ 650              		.cfi_restore 4
+ 651              		.cfi_def_cfa_offset 0
+ 652 012e 7047     		bx	lr
+ 653              	.LVL51:
+ 654              	.L44:
+ 655              	.LCFI4:
+ 656              		.cfi_restore_state
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 657              		.loc 1 427 17 view .LVU197
+ 658 0130 0320     		movs	r0, #3
+ 659              	.LVL52:
+ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ARM GAS  /tmp/ccLtUKRp.s 			page 126
+
+
+ 660              		.loc 1 427 17 view .LVU198
+ 661 0132 E1E7     		b	.L28
+ 662              	.LVL53:
+ 663              	.L45:
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 664              		.loc 1 432 17 view .LVU199
+ 665 0134 0220     		movs	r0, #2
+ 666              	.LVL54:
+ 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 667              		.loc 1 432 17 view .LVU200
+ 668 0136 DFE7     		b	.L28
+ 669              	.LVL55:
+ 670              	.L46:
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         }
+ 671              		.loc 1 439 19 view .LVU201
+ 672 0138 0120     		movs	r0, #1
+ 673              	.LVL56:
+ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****         }
+ 674              		.loc 1 439 19 view .LVU202
+ 675 013a DDE7     		b	.L28
+ 676              	.LVL57:
+ 677              	.L31:
+ 678              	.LCFI5:
+ 679              		.cfi_def_cfa_offset 0
+ 680              		.cfi_restore 4
+ 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 681              		.loc 1 336 12 view .LVU203
+ 682 013c 0120     		movs	r0, #1
+ 683              	.LVL58:
+ 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 684              		.loc 1 469 3 is_stmt 1 view .LVU204
+ 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 685              		.loc 1 470 1 is_stmt 0 view .LVU205
+ 686 013e 7047     		bx	lr
+ 687              	.LVL59:
+ 688              	.L47:
+ 689              	.LCFI6:
+ 690              		.cfi_def_cfa_offset 4
+ 691              		.cfi_offset 4, -4
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 692              		.loc 1 465 16 view .LVU206
+ 693 0140 0020     		movs	r0, #0
+ 694              	.LVL60:
+ 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 695              		.loc 1 465 16 view .LVU207
+ 696 0142 F2E7     		b	.L25
+ 697              	.L55:
+ 698              		.align	2
+ 699              	.L54:
+ 700 0144 00700040 		.word	1073770496
+ 701 0148 000E2707 		.word	120000000
+ 702 014c 804A5D05 		.word	90000000
+ 703 0150 00879303 		.word	60000000
+ 704 0154 80C3C901 		.word	30000000
+ 705 0158 8058840C 		.word	210000000
+ 706 015c 80D1F008 		.word	150000000
+ 707 0160 003C0240 		.word	1073888256
+ARM GAS  /tmp/ccLtUKRp.s 			page 127
+
+
+ 708              		.cfi_endproc
+ 709              	.LFE408:
+ 711              		.section	.text.UTILS_EnablePLLAndSwitchSystem,"ax",%progbits
+ 712              		.align	1
+ 713              		.syntax unified
+ 714              		.thumb
+ 715              		.thumb_func
+ 716              		.fpu fpv5-d16
+ 718              	UTILS_EnablePLLAndSwitchSystem:
+ 719              	.LVL61:
+ 720              	.LFB413:
+ 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /**
+ 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @brief  Function to enable PLL and switch system clock to PLL
+ 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  SYSCLK_Frequency SYSCLK frequency
+ 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *                             the configuration information for the BUS prescalers.
+ 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   * @retval An ErrorStatus enumeration value:
+ 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *          - SUCCESS: No problem to switch system to PLL
+ 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   *          - ERROR: Problem to switch system to PLL
+ 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   */
+ 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDe
+ 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** {
+ 721              		.loc 1 684 1 is_stmt 1 view -0
+ 722              		.cfi_startproc
+ 723              		@ args = 0, pretend = 0, frame = 0
+ 724              		@ frame_needed = 0, uses_anonymous_args = 0
+ 725              		.loc 1 684 1 is_stmt 0 view .LVU209
+ 726 0000 70B5     		push	{r4, r5, r6, lr}
+ 727              	.LCFI7:
+ 728              		.cfi_def_cfa_offset 16
+ 729              		.cfi_offset 4, -16
+ 730              		.cfi_offset 5, -12
+ 731              		.cfi_offset 6, -8
+ 732              		.cfi_offset 14, -4
+ 733 0002 0C46     		mov	r4, r1
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 734              		.loc 1 685 3 is_stmt 1 view .LVU210
+ 735              	.LVL62:
+ 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t hclk_frequency = 0U;
+ 736              		.loc 1 686 3 view .LVU211
+ 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+ 737              		.loc 1 688 3 view .LVU212
+ 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+ 738              		.loc 1 689 3 view .LVU213
+ 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+ 739              		.loc 1 690 3 view .LVU214
+ 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Calculate HCLK frequency */
+ 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
+ 740              		.loc 1 693 3 view .LVU215
+ 741              		.loc 1 693 20 is_stmt 0 view .LVU216
+ 742 0004 0B68     		ldr	r3, [r1]
+ 743 0006 C3F30313 		ubfx	r3, r3, #4, #4
+ 744 000a 254A     		ldr	r2, .L68
+ 745 000c D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
+ARM GAS  /tmp/ccLtUKRp.s 			page 128
+
+
+ 746              		.loc 1 693 18 view .LVU217
+ 747 000e 20FA03F5 		lsr	r5, r0, r3
+ 748              	.LVL63:
+ 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Increasing the number of wait states because of higher CPU frequency */
+ 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   if(SystemCoreClock < hclk_frequency)
+ 749              		.loc 1 696 3 is_stmt 1 view .LVU218
+ 750              		.loc 1 696 22 is_stmt 0 view .LVU219
+ 751 0012 244B     		ldr	r3, .L68+4
+ 752 0014 1B68     		ldr	r3, [r3]
+ 753              		.loc 1 696 5 view .LVU220
+ 754 0016 AB42     		cmp	r3, r5
+ 755 0018 31D3     		bcc	.L65
+ 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t hclk_frequency = 0U;
+ 756              		.loc 1 685 15 view .LVU221
+ 757 001a 0026     		movs	r6, #0
+ 758              	.LVL64:
+ 759              	.L57:
+ 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Set FLASH latency to highest latency */
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     status = LL_SetFlashLatency(hclk_frequency);
+ 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Update system clock configuration */
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   if(status == SUCCESS)
+ 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Enable PLL */
+ 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     LL_RCC_PLL_Enable();
+ 760              		.loc 1 706 5 is_stmt 1 view .LVU222
+ 761              	.LBB72:
+ 762              	.LBI72:
+3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 763              		.loc 2 3132 22 view .LVU223
+ 764              	.LBB73:
+3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 765              		.loc 2 3134 3 view .LVU224
+ 766 001c 224A     		ldr	r2, .L68+8
+ 767 001e 1368     		ldr	r3, [r2]
+ 768 0020 43F08073 		orr	r3, r3, #16777216
+ 769 0024 1360     		str	r3, [r2]
+ 770              	.L59:
+ 771              	.LBE73:
+ 772              	.LBE72:
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     while (LL_RCC_PLL_IsReady() != 1U)
+ 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       /* Wait for PLL ready */
+ 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 773              		.loc 1 710 5 discriminator 1 view .LVU225
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     while (LL_RCC_PLL_IsReady() != 1U)
+ 774              		.loc 1 707 11 discriminator 1 view .LVU226
+ 775              	.LBB74:
+ 776              	.LBI74:
+3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 777              		.loc 2 3153 26 discriminator 1 view .LVU227
+ 778              	.LBB75:
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 779              		.loc 2 3155 3 discriminator 1 view .LVU228
+ARM GAS  /tmp/ccLtUKRp.s 			page 129
+
+
+3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 780              		.loc 2 3155 11 is_stmt 0 discriminator 1 view .LVU229
+ 781 0026 204B     		ldr	r3, .L68+8
+ 782 0028 1B68     		ldr	r3, [r3]
+ 783              	.LBE75:
+ 784              	.LBE74:
+ 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     while (LL_RCC_PLL_IsReady() != 1U)
+ 785              		.loc 1 707 11 discriminator 1 view .LVU230
+ 786 002a 13F0007F 		tst	r3, #33554432
+ 787 002e FAD0     		beq	.L59
+ 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Sysclk activation on the main PLL */
+ 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ 788              		.loc 1 713 5 is_stmt 1 view .LVU231
+ 789 0030 2368     		ldr	r3, [r4]
+ 790              	.LVL65:
+ 791              	.LBB76:
+ 792              	.LBI76:
+2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 793              		.loc 2 2247 22 view .LVU232
+ 794              	.LBB77:
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 795              		.loc 2 2249 3 view .LVU233
+ 796 0032 1D4A     		ldr	r2, .L68+8
+ 797 0034 9168     		ldr	r1, [r2, #8]
+ 798 0036 21F0F001 		bic	r1, r1, #240
+ 799 003a 0B43     		orrs	r3, r3, r1
+ 800              	.LVL66:
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 801              		.loc 2 2249 3 is_stmt 0 view .LVU234
+ 802 003c 9360     		str	r3, [r2, #8]
+ 803              	.LVL67:
+2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 804              		.loc 2 2249 3 view .LVU235
+ 805              	.LBE77:
+ 806              	.LBE76:
+ 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+ 807              		.loc 1 714 5 is_stmt 1 view .LVU236
+ 808              	.LBB78:
+ 809              	.LBI78:
+2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 810              		.loc 2 2214 22 view .LVU237
+ 811              	.LBB79:
+2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 812              		.loc 2 2216 3 view .LVU238
+ 813 003e 9368     		ldr	r3, [r2, #8]
+ 814 0040 23F00303 		bic	r3, r3, #3
+ 815 0044 43F00203 		orr	r3, r3, #2
+ 816 0048 9360     		str	r3, [r2, #8]
+ 817              	.LVL68:
+ 818              	.L60:
+2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 819              		.loc 2 2216 3 is_stmt 0 view .LVU239
+ 820              	.LBE79:
+ 821              	.LBE78:
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ARM GAS  /tmp/ccLtUKRp.s 			page 130
+
+
+ 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       /* Wait for system clock switch to PLL */
+ 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 822              		.loc 1 718 5 is_stmt 1 discriminator 1 view .LVU240
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ 823              		.loc 1 715 11 discriminator 1 view .LVU241
+ 824              	.LBB80:
+ 825              	.LBI80:
+2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 826              		.loc 2 2227 26 discriminator 1 view .LVU242
+ 827              	.LBB81:
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 828              		.loc 2 2229 3 discriminator 1 view .LVU243
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 829              		.loc 2 2229 21 is_stmt 0 discriminator 1 view .LVU244
+ 830 004a 174B     		ldr	r3, .L68+8
+ 831 004c 9B68     		ldr	r3, [r3, #8]
+2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 832              		.loc 2 2229 10 discriminator 1 view .LVU245
+ 833 004e 03F00C03 		and	r3, r3, #12
+ 834              	.LBE81:
+ 835              	.LBE80:
+ 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ 836              		.loc 1 715 11 discriminator 1 view .LVU246
+ 837 0052 082B     		cmp	r3, #8
+ 838 0054 F9D1     		bne	.L60
+ 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Set APB1 & APB2 prescaler*/
+ 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+ 839              		.loc 1 721 5 is_stmt 1 view .LVU247
+ 840 0056 6268     		ldr	r2, [r4, #4]
+ 841              	.LVL69:
+ 842              	.LBB82:
+ 843              	.LBI82:
+2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 844              		.loc 2 2263 22 view .LVU248
+ 845              	.LBB83:
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 846              		.loc 2 2265 3 view .LVU249
+ 847 0058 134B     		ldr	r3, .L68+8
+ 848 005a 9968     		ldr	r1, [r3, #8]
+ 849 005c 21F4E051 		bic	r1, r1, #7168
+ 850 0060 0A43     		orrs	r2, r2, r1
+ 851              	.LVL70:
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 852              		.loc 2 2265 3 is_stmt 0 view .LVU250
+ 853 0062 9A60     		str	r2, [r3, #8]
+ 854              	.LVL71:
+2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 855              		.loc 2 2265 3 view .LVU251
+ 856              	.LBE83:
+ 857              	.LBE82:
+ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+ 858              		.loc 1 722 5 is_stmt 1 view .LVU252
+ 859 0064 A268     		ldr	r2, [r4, #8]
+ 860              	.LVL72:
+ 861              	.LBB84:
+ 862              	.LBI84:
+ARM GAS  /tmp/ccLtUKRp.s 			page 131
+
+
+2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 863              		.loc 2 2279 22 view .LVU253
+ 864              	.LBB85:
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 865              		.loc 2 2281 3 view .LVU254
+ 866 0066 9968     		ldr	r1, [r3, #8]
+ 867 0068 21F46041 		bic	r1, r1, #57344
+ 868 006c 0A43     		orrs	r2, r2, r1
+ 869              	.LVL73:
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 870              		.loc 2 2281 3 is_stmt 0 view .LVU255
+ 871 006e 9A60     		str	r2, [r3, #8]
+ 872              	.LVL74:
+ 873              	.L58:
+2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 874              		.loc 2 2281 3 view .LVU256
+ 875              	.LBE85:
+ 876              	.LBE84:
+ 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     
+ 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Decreasing the number of wait states because of lower CPU frequency */
+ 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   if(SystemCoreClock > hclk_frequency)
+ 877              		.loc 1 726 3 is_stmt 1 view .LVU257
+ 878              		.loc 1 726 22 is_stmt 0 view .LVU258
+ 879 0070 0C4B     		ldr	r3, .L68+4
+ 880 0072 1B68     		ldr	r3, [r3]
+ 881              		.loc 1 726 5 view .LVU259
+ 882 0074 AB42     		cmp	r3, r5
+ 883 0076 09D8     		bhi	.L66
+ 884              	.L61:
+ 885              	.LVL75:
+ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     /* Set FLASH latency to lowest latency */
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     status = LL_SetFlashLatency(hclk_frequency);
+ 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   /* Update SystemCoreClock variable */
+ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   if(status == SUCCESS)
+ 886              		.loc 1 733 3 is_stmt 1 view .LVU260
+ 887              		.loc 1 733 5 is_stmt 0 view .LVU261
+ 888 0078 6EB1     		cbz	r6, .L67
+ 889              	.L62:
+ 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     LL_SetSystemCoreClock(hclk_frequency);
+ 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   return status;
+ 890              		.loc 1 738 3 is_stmt 1 view .LVU262
+ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 891              		.loc 1 739 1 is_stmt 0 view .LVU263
+ 892 007a 3046     		mov	r0, r6
+ 893 007c 70BD     		pop	{r4, r5, r6, pc}
+ 894              	.LVL76:
+ 895              	.L65:
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 896              		.loc 1 699 5 is_stmt 1 view .LVU264
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ARM GAS  /tmp/ccLtUKRp.s 			page 132
+
+
+ 897              		.loc 1 699 14 is_stmt 0 view .LVU265
+ 898 007e 2846     		mov	r0, r5
+ 899              	.LVL77:
+ 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 900              		.loc 1 699 14 view .LVU266
+ 901 0080 FFF7FEFF 		bl	LL_SetFlashLatency
+ 902              	.LVL78:
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 903              		.loc 1 703 3 is_stmt 1 view .LVU267
+ 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 904              		.loc 1 703 5 is_stmt 0 view .LVU268
+ 905 0084 0646     		mov	r6, r0
+ 906 0086 0028     		cmp	r0, #0
+ 907 0088 F2D1     		bne	.L58
+ 908 008a C7E7     		b	.L57
+ 909              	.LVL79:
+ 910              	.L66:
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 911              		.loc 1 729 5 is_stmt 1 view .LVU269
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 912              		.loc 1 729 14 is_stmt 0 view .LVU270
+ 913 008c 2846     		mov	r0, r5
+ 914 008e FFF7FEFF 		bl	LL_SetFlashLatency
+ 915              	.LVL80:
+ 916 0092 0646     		mov	r6, r0
+ 917              	.LVL81:
+ 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 918              		.loc 1 729 14 view .LVU271
+ 919 0094 F0E7     		b	.L61
+ 920              	.L67:
+ 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 921              		.loc 1 735 5 is_stmt 1 view .LVU272
+ 922 0096 2846     		mov	r0, r5
+ 923 0098 FFF7FEFF 		bl	LL_SetSystemCoreClock
+ 924              	.LVL82:
+ 925 009c EDE7     		b	.L62
+ 926              	.L69:
+ 927 009e 00BF     		.align	2
+ 928              	.L68:
+ 929 00a0 00000000 		.word	AHBPrescTable
+ 930 00a4 00000000 		.word	SystemCoreClock
+ 931 00a8 00380240 		.word	1073887232
+ 932              		.cfi_endproc
+ 933              	.LFE413:
+ 935              		.section	.text.LL_PLL_ConfigSystemClock_HSI,"ax",%progbits
+ 936              		.align	1
+ 937              		.global	LL_PLL_ConfigSystemClock_HSI
+ 938              		.syntax unified
+ 939              		.thumb
+ 940              		.thumb_func
+ 941              		.fpu fpv5-d16
+ 943              	LL_PLL_ConfigSystemClock_HSI:
+ 944              	.LVL83:
+ 945              	.LFB409:
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 946              		.loc 1 490 1 view -0
+ 947              		.cfi_startproc
+ARM GAS  /tmp/ccLtUKRp.s 			page 133
+
+
+ 948              		@ args = 0, pretend = 0, frame = 0
+ 949              		@ frame_needed = 0, uses_anonymous_args = 0
+ 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 950              		.loc 1 490 1 is_stmt 0 view .LVU274
+ 951 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 952              	.LCFI8:
+ 953              		.cfi_def_cfa_offset 24
+ 954              		.cfi_offset 3, -24
+ 955              		.cfi_offset 4, -20
+ 956              		.cfi_offset 5, -16
+ 957              		.cfi_offset 6, -12
+ 958              		.cfi_offset 7, -8
+ 959              		.cfi_offset 14, -4
+ 960 0002 0446     		mov	r4, r0
+ 961 0004 0D46     		mov	r5, r1
+ 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t pllfreq = 0U;
+ 962              		.loc 1 491 3 is_stmt 1 view .LVU275
+ 963              	.LVL84:
+ 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 964              		.loc 1 492 3 view .LVU276
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 965              		.loc 1 495 3 view .LVU277
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 966              		.loc 1 495 6 is_stmt 0 view .LVU278
+ 967 0006 FFF7FEFF 		bl	UTILS_PLL_IsBusy
+ 968              	.LVL85:
+ 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 969              		.loc 1 495 5 view .LVU279
+ 970 000a 10BB     		cbnz	r0, .L74
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 971              		.loc 1 498 5 is_stmt 1 view .LVU280
+ 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 972              		.loc 1 498 15 is_stmt 0 view .LVU281
+ 973 000c 2146     		mov	r1, r4
+ 974 000e 1248     		ldr	r0, .L76
+ 975 0010 FFF7FEFF 		bl	UTILS_GetPLLOutputFrequency
+ 976              	.LVL86:
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 977              		.loc 1 501 5 is_stmt 1 view .LVU282
+ 978              	.LBB86:
+ 979              	.LBI86:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 980              		.loc 2 2030 26 view .LVU283
+ 981              	.LBB87:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 982              		.loc 2 2032 3 view .LVU284
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 983              		.loc 2 2032 11 is_stmt 0 view .LVU285
+ 984 0014 114B     		ldr	r3, .L76+4
+ 985 0016 1B68     		ldr	r3, [r3]
+ 986              	.LBE87:
+ 987              	.LBE86:
+ 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 988              		.loc 1 501 7 view .LVU286
+ 989 0018 13F0020F 		tst	r3, #2
+ 990 001c 09D1     		bne	.L72
+ 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       while (LL_RCC_HSI_IsReady() != 1U)
+ARM GAS  /tmp/ccLtUKRp.s 			page 134
+
+
+ 991              		.loc 1 503 7 is_stmt 1 view .LVU287
+ 992              	.LBB88:
+ 993              	.LBI88:
+2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 994              		.loc 2 2010 22 view .LVU288
+ 995              	.LBB89:
+2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 996              		.loc 2 2012 3 view .LVU289
+ 997 001e 0F4A     		ldr	r2, .L76+4
+ 998 0020 1368     		ldr	r3, [r2]
+ 999 0022 43F00103 		orr	r3, r3, #1
+ 1000 0026 1360     		str	r3, [r2]
+ 1001              	.L73:
+ 1002              	.LBE89:
+ 1003              	.LBE88:
+ 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 1004              		.loc 1 507 7 discriminator 1 view .LVU290
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 1005              		.loc 1 504 13 discriminator 1 view .LVU291
+ 1006              	.LBB90:
+ 1007              	.LBI90:
+2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1008              		.loc 2 2030 26 discriminator 1 view .LVU292
+ 1009              	.LBB91:
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1010              		.loc 2 2032 3 discriminator 1 view .LVU293
+2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1011              		.loc 2 2032 11 is_stmt 0 discriminator 1 view .LVU294
+ 1012 0028 0C4B     		ldr	r3, .L76+4
+ 1013 002a 1B68     		ldr	r3, [r3]
+ 1014              	.LBE91:
+ 1015              	.LBE90:
+ 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 1016              		.loc 1 504 13 discriminator 1 view .LVU295
+ 1017 002c 13F0020F 		tst	r3, #2
+ 1018 0030 FAD0     		beq	.L73
+ 1019              	.L72:
+ 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                 UTILS_PLLInitStruct->PLLP);
+ 1020              		.loc 1 511 5 is_stmt 1 view .LVU296
+ 1021 0032 2168     		ldr	r1, [r4]
+ 1022 0034 6668     		ldr	r6, [r4, #4]
+ 1023 0036 A268     		ldr	r2, [r4, #8]
+ 1024              	.LVL87:
+ 1025              	.LBB92:
+ 1026              	.LBI92:
+3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1027              		.loc 2 3241 22 view .LVU297
+ 1028              	.LBB93:
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+ 1029              		.loc 2 3243 3 view .LVU298
+ 1030 0038 084C     		ldr	r4, .L76+4
+ 1031              	.LVL88:
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+ 1032              		.loc 2 3243 3 is_stmt 0 view .LVU299
+ 1033 003a 6768     		ldr	r7, [r4, #4]
+ 1034 003c 084B     		ldr	r3, .L76+8
+ 1035 003e 3B40     		ands	r3, r3, r7
+ARM GAS  /tmp/ccLtUKRp.s 			page 135
+
+
+ 1036 0040 41EA8611 		orr	r1, r1, r6, lsl #6
+ 1037              	.LVL89:
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+ 1038              		.loc 2 3243 3 view .LVU300
+ 1039 0044 0A43     		orrs	r2, r2, r1
+ 1040              	.LVL90:
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+ 1041              		.loc 2 3243 3 view .LVU301
+ 1042 0046 1343     		orrs	r3, r3, r2
+ 1043 0048 6360     		str	r3, [r4, #4]
+ 1044              	.LVL91:
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+ 1045              		.loc 2 3243 3 view .LVU302
+ 1046              	.LBE93:
+ 1047              	.LBE92:
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 1048              		.loc 1 515 5 is_stmt 1 view .LVU303
+ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 1049              		.loc 1 515 14 is_stmt 0 view .LVU304
+ 1050 004a 2946     		mov	r1, r5
+ 1051 004c FFF7FEFF 		bl	UTILS_EnablePLLAndSwitchSystem
+ 1052              	.LVL92:
+ 1053              	.L71:
+ 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 1054              		.loc 1 523 3 is_stmt 1 view .LVU305
+ 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 1055              		.loc 1 524 1 is_stmt 0 view .LVU306
+ 1056 0050 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 1057              	.LVL93:
+ 1058              	.L74:
+ 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 1059              		.loc 1 520 12 view .LVU307
+ 1060 0052 0120     		movs	r0, #1
+ 1061 0054 FCE7     		b	.L71
+ 1062              	.L77:
+ 1063 0056 00BF     		.align	2
+ 1064              	.L76:
+ 1065 0058 0024F400 		.word	16000000
+ 1066 005c 00380240 		.word	1073887232
+ 1067 0060 0080BCFF 		.word	-4423680
+ 1068              		.cfi_endproc
+ 1069              	.LFE409:
+ 1071              		.section	.text.LL_PLL_ConfigSystemClock_HSE,"ax",%progbits
+ 1072              		.align	1
+ 1073              		.global	LL_PLL_ConfigSystemClock_HSE
+ 1074              		.syntax unified
+ 1075              		.thumb
+ 1076              		.thumb_func
+ 1077              		.fpu fpv5-d16
+ 1079              	LL_PLL_ConfigSystemClock_HSE:
+ 1080              	.LVL94:
+ 1081              	.LFB410:
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 1082              		.loc 1 548 1 is_stmt 1 view -0
+ 1083              		.cfi_startproc
+ 1084              		@ args = 0, pretend = 0, frame = 0
+ 1085              		@ frame_needed = 0, uses_anonymous_args = 0
+ARM GAS  /tmp/ccLtUKRp.s 			page 136
+
+
+ 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   ErrorStatus status = SUCCESS;
+ 1086              		.loc 1 548 1 is_stmt 0 view .LVU309
+ 1087 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 1088              	.LCFI9:
+ 1089              		.cfi_def_cfa_offset 24
+ 1090              		.cfi_offset 3, -24
+ 1091              		.cfi_offset 4, -20
+ 1092              		.cfi_offset 5, -16
+ 1093              		.cfi_offset 6, -12
+ 1094              		.cfi_offset 7, -8
+ 1095              		.cfi_offset 14, -4
+ 1096 0002 0646     		mov	r6, r0
+ 1097 0004 0F46     		mov	r7, r1
+ 1098 0006 1446     		mov	r4, r2
+ 1099 0008 1D46     		mov	r5, r3
+ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   uint32_t pllfreq = 0U;
+ 1100              		.loc 1 549 3 is_stmt 1 view .LVU310
+ 1101              	.LVL95:
+ 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 1102              		.loc 1 550 3 view .LVU311
+ 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+ 1103              		.loc 1 553 3 view .LVU312
+ 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 1104              		.loc 1 554 3 view .LVU313
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 1105              		.loc 1 557 3 view .LVU314
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 1106              		.loc 1 557 6 is_stmt 0 view .LVU315
+ 1107 000a FFF7FEFF 		bl	UTILS_PLL_IsBusy
+ 1108              	.LVL96:
+ 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   {
+ 1109              		.loc 1 557 5 view .LVU316
+ 1110 000e 0028     		cmp	r0, #0
+ 1111 0010 31D1     		bne	.L84
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 1112              		.loc 1 560 5 is_stmt 1 view .LVU317
+ 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ 1113              		.loc 1 560 15 is_stmt 0 view .LVU318
+ 1114 0012 2146     		mov	r1, r4
+ 1115 0014 3046     		mov	r0, r6
+ 1116 0016 FFF7FEFF 		bl	UTILS_GetPLLOutputFrequency
+ 1117              	.LVL97:
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 1118              		.loc 1 563 5 is_stmt 1 view .LVU319
+ 1119              	.LBB94:
+ 1120              	.LBI94:
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1121              		.loc 2 1992 26 view .LVU320
+ 1122              	.LBB95:
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1123              		.loc 2 1994 3 view .LVU321
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1124              		.loc 2 1994 11 is_stmt 0 view .LVU322
+ 1125 001a 184B     		ldr	r3, .L87
+ 1126 001c 1B68     		ldr	r3, [r3]
+ 1127              	.LBE95:
+ 1128              	.LBE94:
+ARM GAS  /tmp/ccLtUKRp.s 			page 137
+
+
+ 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     {
+ 1129              		.loc 1 563 7 view .LVU323
+ 1130 001e 13F4003F 		tst	r3, #131072
+ 1131 0022 10D1     		bne	.L80
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 1132              		.loc 1 566 7 is_stmt 1 view .LVU324
+ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 1133              		.loc 1 566 9 is_stmt 0 view .LVU325
+ 1134 0024 012F     		cmp	r7, #1
+ 1135 0026 20D0     		beq	.L86
+ 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 1136              		.loc 1 572 9 is_stmt 1 view .LVU326
+ 1137              	.LBB96:
+ 1138              	.LBI96:
+1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1139              		.loc 2 1962 22 view .LVU327
+ 1140              	.LBB97:
+1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1141              		.loc 2 1964 3 view .LVU328
+ 1142 0028 144A     		ldr	r2, .L87
+ 1143 002a 1368     		ldr	r3, [r2]
+ 1144 002c 23F48023 		bic	r3, r3, #262144
+ 1145 0030 1360     		str	r3, [r2]
+ 1146              	.L82:
+ 1147              	.LBE97:
+ 1148              	.LBE96:
+ 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       while (LL_RCC_HSE_IsReady() != 1U)
+ 1149              		.loc 1 576 7 view .LVU329
+ 1150              	.LBB98:
+ 1151              	.LBI98:
+1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1152              		.loc 2 1972 22 view .LVU330
+ 1153              	.LBB99:
+1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1154              		.loc 2 1974 3 view .LVU331
+ 1155 0032 124A     		ldr	r2, .L87
+ 1156 0034 1368     		ldr	r3, [r2]
+ 1157 0036 43F48033 		orr	r3, r3, #65536
+ 1158 003a 1360     		str	r3, [r2]
+ 1159              	.L83:
+ 1160              	.LBE99:
+ 1161              	.LBE98:
+ 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****     }
+ 1162              		.loc 1 580 7 discriminator 1 view .LVU332
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 1163              		.loc 1 577 13 discriminator 1 view .LVU333
+ 1164              	.LBB100:
+ 1165              	.LBI100:
+1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1166              		.loc 2 1992 26 discriminator 1 view .LVU334
+ 1167              	.LBB101:
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1168              		.loc 2 1994 3 discriminator 1 view .LVU335
+1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1169              		.loc 2 1994 11 is_stmt 0 discriminator 1 view .LVU336
+ 1170 003c 0F4A     		ldr	r2, .L87
+ 1171 003e 1268     		ldr	r2, [r2]
+ARM GAS  /tmp/ccLtUKRp.s 			page 138
+
+
+ 1172              	.LBE101:
+ 1173              	.LBE100:
+ 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       {
+ 1174              		.loc 1 577 13 discriminator 1 view .LVU337
+ 1175 0040 12F4003F 		tst	r2, #131072
+ 1176 0044 FAD0     		beq	.L83
+ 1177              	.L80:
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                 UTILS_PLLInitStruct->PLLP);
+ 1178              		.loc 1 584 5 is_stmt 1 view .LVU338
+ 1179 0046 2268     		ldr	r2, [r4]
+ 1180 0048 6668     		ldr	r6, [r4, #4]
+ 1181              	.LVL98:
+ 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****                                 UTILS_PLLInitStruct->PLLP);
+ 1182              		.loc 1 584 5 is_stmt 0 view .LVU339
+ 1183 004a A168     		ldr	r1, [r4, #8]
+ 1184              	.LVL99:
+ 1185              	.LBB102:
+ 1186              	.LBI102:
+3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1187              		.loc 2 3241 22 is_stmt 1 view .LVU340
+ 1188              	.LBB103:
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+ 1189              		.loc 2 3243 3 view .LVU341
+ 1190 004c 0B4C     		ldr	r4, .L87
+ 1191              	.LVL100:
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+ 1192              		.loc 2 3243 3 is_stmt 0 view .LVU342
+ 1193 004e 6768     		ldr	r7, [r4, #4]
+ 1194              	.LVL101:
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+ 1195              		.loc 2 3243 3 view .LVU343
+ 1196 0050 0B4B     		ldr	r3, .L87+4
+ 1197 0052 3B40     		ands	r3, r3, r7
+ 1198 0054 42F48002 		orr	r2, r2, #4194304
+ 1199              	.LVL102:
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+ 1200              		.loc 2 3243 3 view .LVU344
+ 1201 0058 42EA8612 		orr	r2, r2, r6, lsl #6
+ 1202 005c 0A43     		orrs	r2, r2, r1
+ 1203 005e 1343     		orrs	r3, r3, r2
+ 1204 0060 6360     		str	r3, [r4, #4]
+ 1205              	.LVL103:
+3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h ****              Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
+ 1206              		.loc 2 3243 3 view .LVU345
+ 1207              	.LBE103:
+ 1208              	.LBE102:
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 1209              		.loc 1 588 5 is_stmt 1 view .LVU346
+ 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 1210              		.loc 1 588 14 is_stmt 0 view .LVU347
+ 1211 0062 2946     		mov	r1, r5
+ 1212 0064 FFF7FEFF 		bl	UTILS_EnablePLLAndSwitchSystem
+ 1213              	.LVL104:
+ 1214              	.L79:
+ 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** }
+ 1215              		.loc 1 596 3 is_stmt 1 view .LVU348
+ 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** 
+ARM GAS  /tmp/ccLtUKRp.s 			page 139
+
+
+ 1216              		.loc 1 597 1 is_stmt 0 view .LVU349
+ 1217 0068 F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 1218              	.LVL105:
+ 1219              	.L86:
+ 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****       }
+ 1220              		.loc 1 568 9 is_stmt 1 view .LVU350
+ 1221              	.LBB104:
+ 1222              	.LBI104:
+1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** {
+ 1223              		.loc 2 1952 22 view .LVU351
+ 1224              	.LBB105:
+1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** }
+ 1225              		.loc 2 1954 3 view .LVU352
+ 1226 006a 044A     		ldr	r2, .L87
+ 1227 006c 1368     		ldr	r3, [r2]
+ 1228 006e 43F48023 		orr	r3, r3, #262144
+ 1229 0072 1360     		str	r3, [r2]
+1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 1230              		.loc 2 1955 1 is_stmt 0 view .LVU353
+ 1231 0074 DDE7     		b	.L82
+ 1232              	.LVL106:
+ 1233              	.L84:
+1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** 
+ 1234              		.loc 2 1955 1 view .LVU354
+ 1235              	.LBE105:
+ 1236              	.LBE104:
+ 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c ****   }
+ 1237              		.loc 1 593 12 view .LVU355
+ 1238 0076 0120     		movs	r0, #1
+ 1239 0078 F6E7     		b	.L79
+ 1240              	.L88:
+ 1241 007a 00BF     		.align	2
+ 1242              	.L87:
+ 1243 007c 00380240 		.word	1073887232
+ 1244 0080 0080BCFF 		.word	-4423680
+ 1245              		.cfi_endproc
+ 1246              	.LFE410:
+ 1248              		.text
+ 1249              	.Letext0:
+ 1250              		.file 6 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 1251              		.file 7 "Drivers/CMSIS/Include/core_cm7.h"
+ 1252              		.file 8 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h"
+ 1253              		.file 9 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ 1254              		.file 10 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+ARM GAS  /tmp/ccLtUKRp.s 			page 140
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f7xx_ll_utils.c
+     /tmp/ccLtUKRp.s:17     .text.UTILS_GetPLLOutputFrequency:0000000000000000 $t
+     /tmp/ccLtUKRp.s:24     .text.UTILS_GetPLLOutputFrequency:0000000000000000 UTILS_GetPLLOutputFrequency
+     /tmp/ccLtUKRp.s:74     .text.UTILS_PLL_IsBusy:0000000000000000 $t
+     /tmp/ccLtUKRp.s:80     .text.UTILS_PLL_IsBusy:0000000000000000 UTILS_PLL_IsBusy
+     /tmp/ccLtUKRp.s:155    .text.UTILS_PLL_IsBusy:000000000000002c $d
+     /tmp/ccLtUKRp.s:160    .text.LL_Init1msTick:0000000000000000 $t
+     /tmp/ccLtUKRp.s:167    .text.LL_Init1msTick:0000000000000000 LL_Init1msTick
+     /tmp/ccLtUKRp.s:208    .text.LL_Init1msTick:000000000000001c $d
+     /tmp/ccLtUKRp.s:213    .text.LL_mDelay:0000000000000000 $t
+     /tmp/ccLtUKRp.s:220    .text.LL_mDelay:0000000000000000 LL_mDelay
+     /tmp/ccLtUKRp.s:276    .text.LL_SetSystemCoreClock:0000000000000000 $t
+     /tmp/ccLtUKRp.s:283    .text.LL_SetSystemCoreClock:0000000000000000 LL_SetSystemCoreClock
+     /tmp/ccLtUKRp.s:300    .text.LL_SetSystemCoreClock:0000000000000008 $d
+     /tmp/ccLtUKRp.s:305    .text.LL_SetFlashLatency:0000000000000000 $t
+     /tmp/ccLtUKRp.s:312    .text.LL_SetFlashLatency:0000000000000000 LL_SetFlashLatency
+     /tmp/ccLtUKRp.s:700    .text.LL_SetFlashLatency:0000000000000144 $d
+     /tmp/ccLtUKRp.s:712    .text.UTILS_EnablePLLAndSwitchSystem:0000000000000000 $t
+     /tmp/ccLtUKRp.s:718    .text.UTILS_EnablePLLAndSwitchSystem:0000000000000000 UTILS_EnablePLLAndSwitchSystem
+     /tmp/ccLtUKRp.s:929    .text.UTILS_EnablePLLAndSwitchSystem:00000000000000a0 $d
+     /tmp/ccLtUKRp.s:936    .text.LL_PLL_ConfigSystemClock_HSI:0000000000000000 $t
+     /tmp/ccLtUKRp.s:943    .text.LL_PLL_ConfigSystemClock_HSI:0000000000000000 LL_PLL_ConfigSystemClock_HSI
+     /tmp/ccLtUKRp.s:1065   .text.LL_PLL_ConfigSystemClock_HSI:0000000000000058 $d
+     /tmp/ccLtUKRp.s:1072   .text.LL_PLL_ConfigSystemClock_HSE:0000000000000000 $t
+     /tmp/ccLtUKRp.s:1079   .text.LL_PLL_ConfigSystemClock_HSE:0000000000000000 LL_PLL_ConfigSystemClock_HSE
+     /tmp/ccLtUKRp.s:1243   .text.LL_PLL_ConfigSystemClock_HSE:000000000000007c $d
+
+UNDEFINED SYMBOLS
+SystemCoreClock
+AHBPrescTable
diff --git a/build/stm32f7xx_ll_utils.o b/build/stm32f7xx_ll_utils.o
new file mode 100644
index 0000000..8658589
Binary files /dev/null and b/build/stm32f7xx_ll_utils.o differ
diff --git a/build/syscall.d b/build/syscall.d
new file mode 100644
index 0000000..35f3068
--- /dev/null
+++ b/build/syscall.d
@@ -0,0 +1,96 @@
+build/syscall.o: Middlewares/Third_Party/FatFs/src/option/syscall.c \
+ Middlewares/Third_Party/FatFs/src/option/../ff.h \
+ Middlewares/Third_Party/FatFs/src/option/../integer.h Inc/ffconf.h \
+ Inc/main.h Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/bsp_driver_sd.h \
+ Inc/fatfs_platform.h
+Middlewares/Third_Party/FatFs/src/option/../ff.h:
+Middlewares/Third_Party/FatFs/src/option/../integer.h:
+Inc/ffconf.h:
+Inc/main.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h:
+Inc/bsp_driver_sd.h:
+Inc/fatfs_platform.h:
diff --git a/build/syscall.lst b/build/syscall.lst
new file mode 100644
index 0000000..dcc06d9
--- /dev/null
+++ b/build/syscall.lst
@@ -0,0 +1,30 @@
+ARM GAS  /tmp/ccgoFeEr.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"syscall.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              	.Letext0:
+  17              		.file 1 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h"
+  18              		.file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h"
+  19              		.file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h"
+  20              		.file 4 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ARM GAS  /tmp/ccgoFeEr.s 			page 2
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 syscall.c
+
+NO UNDEFINED SYMBOLS
diff --git a/build/syscall.o b/build/syscall.o
new file mode 100644
index 0000000..acd881b
Binary files /dev/null and b/build/syscall.o differ
diff --git a/build/syscalls.d b/build/syscalls.d
new file mode 100644
index 0000000..d61fce2
--- /dev/null
+++ b/build/syscalls.d
@@ -0,0 +1 @@
+build/syscalls.o: Src/syscalls.c
diff --git a/build/syscalls.lst b/build/syscalls.lst
new file mode 100644
index 0000000..dc2f453
--- /dev/null
+++ b/build/syscalls.lst
@@ -0,0 +1,899 @@
+ARM GAS  /tmp/cc9aEoPx.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"syscalls.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.initialise_monitor_handles,"ax",%progbits
+  17              		.align	1
+  18              		.global	initialise_monitor_handles
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	initialise_monitor_handles:
+  26              	.LFB25:
+  27              		.file 1 "Src/syscalls.c"
+   1:Src/syscalls.c **** /**
+   2:Src/syscalls.c ****  ******************************************************************************
+   3:Src/syscalls.c ****  * @file      syscalls.c
+   4:Src/syscalls.c ****  * @author    Auto-generated by STM32CubeMX
+   5:Src/syscalls.c ****  * @brief     Minimal System calls file
+   6:Src/syscalls.c ****  *
+   7:Src/syscalls.c ****  *            For more information about which c-functions
+   8:Src/syscalls.c ****  *            need which of these lowlevel functions
+   9:Src/syscalls.c ****  *            please consult the Newlib libc-manual
+  10:Src/syscalls.c ****  ******************************************************************************
+  11:Src/syscalls.c ****  * @attention
+  12:Src/syscalls.c ****  *
+  13:Src/syscalls.c ****  * Copyright (c) 2020-2024 STMicroelectronics.
+  14:Src/syscalls.c ****  * All rights reserved.
+  15:Src/syscalls.c ****  *
+  16:Src/syscalls.c ****  * This software is licensed under terms that can be found in the LICENSE file
+  17:Src/syscalls.c ****  * in the root directory of this software component.
+  18:Src/syscalls.c ****  * If no LICENSE file comes with this software, it is provided AS-IS.
+  19:Src/syscalls.c ****  *
+  20:Src/syscalls.c ****  ******************************************************************************
+  21:Src/syscalls.c ****  */
+  22:Src/syscalls.c **** 
+  23:Src/syscalls.c **** /* Includes */
+  24:Src/syscalls.c **** #include 
+  25:Src/syscalls.c **** #include 
+  26:Src/syscalls.c **** #include 
+  27:Src/syscalls.c **** #include 
+  28:Src/syscalls.c **** #include 
+  29:Src/syscalls.c **** #include 
+  30:Src/syscalls.c **** #include 
+  31:Src/syscalls.c **** #include 
+ARM GAS  /tmp/cc9aEoPx.s 			page 2
+
+
+  32:Src/syscalls.c **** 
+  33:Src/syscalls.c **** 
+  34:Src/syscalls.c **** /* Variables */
+  35:Src/syscalls.c **** extern int __io_putchar(int ch) __attribute__((weak));
+  36:Src/syscalls.c **** extern int __io_getchar(void) __attribute__((weak));
+  37:Src/syscalls.c **** 
+  38:Src/syscalls.c **** 
+  39:Src/syscalls.c **** char *__env[1] = { 0 };
+  40:Src/syscalls.c **** char **environ = __env;
+  41:Src/syscalls.c **** 
+  42:Src/syscalls.c **** 
+  43:Src/syscalls.c **** /* Functions */
+  44:Src/syscalls.c **** void initialise_monitor_handles()
+  45:Src/syscalls.c **** {
+  28              		.loc 1 45 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  46:Src/syscalls.c **** }
+  33              		.loc 1 46 1 view .LVU1
+  34 0000 7047     		bx	lr
+  35              		.cfi_endproc
+  36              	.LFE25:
+  38              		.section	.text._getpid,"ax",%progbits
+  39              		.align	1
+  40              		.global	_getpid
+  41              		.syntax unified
+  42              		.thumb
+  43              		.thumb_func
+  44              		.fpu fpv5-d16
+  46              	_getpid:
+  47              	.LFB26:
+  47:Src/syscalls.c **** 
+  48:Src/syscalls.c **** int _getpid(void)
+  49:Src/syscalls.c **** {
+  48              		.loc 1 49 1 view -0
+  49              		.cfi_startproc
+  50              		@ args = 0, pretend = 0, frame = 0
+  51              		@ frame_needed = 0, uses_anonymous_args = 0
+  52              		@ link register save eliminated.
+  50:Src/syscalls.c ****   return 1;
+  53              		.loc 1 50 3 view .LVU3
+  51:Src/syscalls.c **** }
+  54              		.loc 1 51 1 is_stmt 0 view .LVU4
+  55 0000 0120     		movs	r0, #1
+  56 0002 7047     		bx	lr
+  57              		.cfi_endproc
+  58              	.LFE26:
+  60              		.section	.text._kill,"ax",%progbits
+  61              		.align	1
+  62              		.global	_kill
+  63              		.syntax unified
+  64              		.thumb
+  65              		.thumb_func
+  66              		.fpu fpv5-d16
+  68              	_kill:
+ARM GAS  /tmp/cc9aEoPx.s 			page 3
+
+
+  69              	.LVL0:
+  70              	.LFB27:
+  52:Src/syscalls.c **** 
+  53:Src/syscalls.c **** int _kill(int pid, int sig)
+  54:Src/syscalls.c **** {
+  71              		.loc 1 54 1 is_stmt 1 view -0
+  72              		.cfi_startproc
+  73              		@ args = 0, pretend = 0, frame = 0
+  74              		@ frame_needed = 0, uses_anonymous_args = 0
+  75              		.loc 1 54 1 is_stmt 0 view .LVU6
+  76 0000 08B5     		push	{r3, lr}
+  77              	.LCFI0:
+  78              		.cfi_def_cfa_offset 8
+  79              		.cfi_offset 3, -8
+  80              		.cfi_offset 14, -4
+  55:Src/syscalls.c ****   (void)pid;
+  81              		.loc 1 55 3 is_stmt 1 view .LVU7
+  56:Src/syscalls.c ****   (void)sig;
+  82              		.loc 1 56 3 view .LVU8
+  57:Src/syscalls.c ****   errno = EINVAL;
+  83              		.loc 1 57 3 view .LVU9
+  84 0002 FFF7FEFF 		bl	__errno
+  85              	.LVL1:
+  86              		.loc 1 57 9 is_stmt 0 view .LVU10
+  87 0006 1623     		movs	r3, #22
+  88 0008 0360     		str	r3, [r0]
+  58:Src/syscalls.c ****   return -1;
+  89              		.loc 1 58 3 is_stmt 1 view .LVU11
+  59:Src/syscalls.c **** }
+  90              		.loc 1 59 1 is_stmt 0 view .LVU12
+  91 000a 4FF0FF30 		mov	r0, #-1
+  92 000e 08BD     		pop	{r3, pc}
+  93              		.cfi_endproc
+  94              	.LFE27:
+  96              		.section	.text._exit,"ax",%progbits
+  97              		.align	1
+  98              		.global	_exit
+  99              		.syntax unified
+ 100              		.thumb
+ 101              		.thumb_func
+ 102              		.fpu fpv5-d16
+ 104              	_exit:
+ 105              	.LVL2:
+ 106              	.LFB28:
+  60:Src/syscalls.c **** 
+  61:Src/syscalls.c **** void _exit (int status)
+  62:Src/syscalls.c **** {
+ 107              		.loc 1 62 1 is_stmt 1 view -0
+ 108              		.cfi_startproc
+ 109              		@ Volatile: function does not return.
+ 110              		@ args = 0, pretend = 0, frame = 0
+ 111              		@ frame_needed = 0, uses_anonymous_args = 0
+ 112              		.loc 1 62 1 is_stmt 0 view .LVU14
+ 113 0000 08B5     		push	{r3, lr}
+ 114              	.LCFI1:
+ 115              		.cfi_def_cfa_offset 8
+ 116              		.cfi_offset 3, -8
+ARM GAS  /tmp/cc9aEoPx.s 			page 4
+
+
+ 117              		.cfi_offset 14, -4
+  63:Src/syscalls.c ****   _kill(status, -1);
+ 118              		.loc 1 63 3 is_stmt 1 view .LVU15
+ 119 0002 4FF0FF31 		mov	r1, #-1
+ 120 0006 FFF7FEFF 		bl	_kill
+ 121              	.LVL3:
+ 122              	.L6:
+  64:Src/syscalls.c ****   while (1) {}    /* Make sure we hang here */
+ 123              		.loc 1 64 3 discriminator 1 view .LVU16
+ 124              		.loc 1 64 14 discriminator 1 view .LVU17
+ 125              		.loc 1 64 9 discriminator 1 view .LVU18
+ 126 000a FEE7     		b	.L6
+ 127              		.cfi_endproc
+ 128              	.LFE28:
+ 130              		.section	.text._read,"ax",%progbits
+ 131              		.align	1
+ 132              		.weak	_read
+ 133              		.syntax unified
+ 134              		.thumb
+ 135              		.thumb_func
+ 136              		.fpu fpv5-d16
+ 138              	_read:
+ 139              	.LVL4:
+ 140              	.LFB29:
+  65:Src/syscalls.c **** }
+  66:Src/syscalls.c **** 
+  67:Src/syscalls.c **** __attribute__((weak)) int _read(int file, char *ptr, int len)
+  68:Src/syscalls.c **** {
+ 141              		.loc 1 68 1 view -0
+ 142              		.cfi_startproc
+ 143              		@ args = 0, pretend = 0, frame = 0
+ 144              		@ frame_needed = 0, uses_anonymous_args = 0
+ 145              		.loc 1 68 1 is_stmt 0 view .LVU20
+ 146 0000 70B5     		push	{r4, r5, r6, lr}
+ 147              	.LCFI2:
+ 148              		.cfi_def_cfa_offset 16
+ 149              		.cfi_offset 4, -16
+ 150              		.cfi_offset 5, -12
+ 151              		.cfi_offset 6, -8
+ 152              		.cfi_offset 14, -4
+ 153 0002 0C46     		mov	r4, r1
+ 154 0004 1646     		mov	r6, r2
+  69:Src/syscalls.c ****   (void)file;
+ 155              		.loc 1 69 3 is_stmt 1 view .LVU21
+  70:Src/syscalls.c ****   int DataIdx;
+ 156              		.loc 1 70 3 view .LVU22
+  71:Src/syscalls.c **** 
+  72:Src/syscalls.c ****   for (DataIdx = 0; DataIdx < len; DataIdx++)
+ 157              		.loc 1 72 3 view .LVU23
+ 158              	.LVL5:
+ 159              		.loc 1 72 16 is_stmt 0 view .LVU24
+ 160 0006 0025     		movs	r5, #0
+ 161              		.loc 1 72 3 view .LVU25
+ 162 0008 06E0     		b	.L9
+ 163              	.LVL6:
+ 164              	.L10:
+  73:Src/syscalls.c ****   {
+ARM GAS  /tmp/cc9aEoPx.s 			page 5
+
+
+  74:Src/syscalls.c ****     *ptr++ = __io_getchar();
+ 165              		.loc 1 74 5 is_stmt 1 discriminator 3 view .LVU26
+ 166              		.loc 1 74 14 is_stmt 0 discriminator 3 view .LVU27
+ 167 000a FFF7FEFF 		bl	__io_getchar
+ 168              	.LVL7:
+ 169              		.loc 1 74 9 discriminator 3 view .LVU28
+ 170 000e 2146     		mov	r1, r4
+ 171              	.LVL8:
+ 172              		.loc 1 74 12 discriminator 3 view .LVU29
+ 173 0010 01F8010B 		strb	r0, [r1], #1
+ 174              	.LVL9:
+  72:Src/syscalls.c ****   {
+ 175              		.loc 1 72 36 is_stmt 1 discriminator 3 view .LVU30
+  72:Src/syscalls.c ****   {
+ 176              		.loc 1 72 43 is_stmt 0 discriminator 3 view .LVU31
+ 177 0014 0135     		adds	r5, r5, #1
+ 178              	.LVL10:
+ 179              		.loc 1 74 9 discriminator 3 view .LVU32
+ 180 0016 0C46     		mov	r4, r1
+ 181              	.LVL11:
+ 182              	.L9:
+  72:Src/syscalls.c ****   {
+ 183              		.loc 1 72 21 is_stmt 1 discriminator 1 view .LVU33
+  72:Src/syscalls.c ****   {
+ 184              		.loc 1 72 3 is_stmt 0 discriminator 1 view .LVU34
+ 185 0018 B542     		cmp	r5, r6
+ 186 001a F6DB     		blt	.L10
+  75:Src/syscalls.c ****   }
+  76:Src/syscalls.c **** 
+  77:Src/syscalls.c ****   return len;
+ 187              		.loc 1 77 3 is_stmt 1 view .LVU35
+  78:Src/syscalls.c **** }
+ 188              		.loc 1 78 1 is_stmt 0 view .LVU36
+ 189 001c 3046     		mov	r0, r6
+ 190 001e 70BD     		pop	{r4, r5, r6, pc}
+ 191              		.loc 1 78 1 view .LVU37
+ 192              		.cfi_endproc
+ 193              	.LFE29:
+ 195              		.section	.text._write,"ax",%progbits
+ 196              		.align	1
+ 197              		.weak	_write
+ 198              		.syntax unified
+ 199              		.thumb
+ 200              		.thumb_func
+ 201              		.fpu fpv5-d16
+ 203              	_write:
+ 204              	.LVL12:
+ 205              	.LFB30:
+  79:Src/syscalls.c **** 
+  80:Src/syscalls.c **** __attribute__((weak)) int _write(int file, char *ptr, int len)
+  81:Src/syscalls.c **** {
+ 206              		.loc 1 81 1 is_stmt 1 view -0
+ 207              		.cfi_startproc
+ 208              		@ args = 0, pretend = 0, frame = 0
+ 209              		@ frame_needed = 0, uses_anonymous_args = 0
+ 210              		.loc 1 81 1 is_stmt 0 view .LVU39
+ 211 0000 70B5     		push	{r4, r5, r6, lr}
+ARM GAS  /tmp/cc9aEoPx.s 			page 6
+
+
+ 212              	.LCFI3:
+ 213              		.cfi_def_cfa_offset 16
+ 214              		.cfi_offset 4, -16
+ 215              		.cfi_offset 5, -12
+ 216              		.cfi_offset 6, -8
+ 217              		.cfi_offset 14, -4
+ 218 0002 0C46     		mov	r4, r1
+ 219 0004 1646     		mov	r6, r2
+  82:Src/syscalls.c ****   (void)file;
+ 220              		.loc 1 82 3 is_stmt 1 view .LVU40
+  83:Src/syscalls.c ****   int DataIdx;
+ 221              		.loc 1 83 3 view .LVU41
+  84:Src/syscalls.c **** 
+  85:Src/syscalls.c ****   for (DataIdx = 0; DataIdx < len; DataIdx++)
+ 222              		.loc 1 85 3 view .LVU42
+ 223              	.LVL13:
+ 224              		.loc 1 85 16 is_stmt 0 view .LVU43
+ 225 0006 0025     		movs	r5, #0
+ 226              		.loc 1 85 3 view .LVU44
+ 227 0008 04E0     		b	.L13
+ 228              	.LVL14:
+ 229              	.L14:
+  86:Src/syscalls.c ****   {
+  87:Src/syscalls.c ****     __io_putchar(*ptr++);
+ 230              		.loc 1 87 5 is_stmt 1 discriminator 3 view .LVU45
+ 231              		.loc 1 87 5 is_stmt 0 discriminator 3 view .LVU46
+ 232 000a 14F8010B 		ldrb	r0, [r4], #1	@ zero_extendqisi2
+ 233              	.LVL15:
+ 234              		.loc 1 87 5 discriminator 3 view .LVU47
+ 235 000e FFF7FEFF 		bl	__io_putchar
+ 236              	.LVL16:
+  85:Src/syscalls.c ****   {
+ 237              		.loc 1 85 36 is_stmt 1 discriminator 3 view .LVU48
+  85:Src/syscalls.c ****   {
+ 238              		.loc 1 85 43 is_stmt 0 discriminator 3 view .LVU49
+ 239 0012 0135     		adds	r5, r5, #1
+ 240              	.LVL17:
+ 241              	.L13:
+  85:Src/syscalls.c ****   {
+ 242              		.loc 1 85 21 is_stmt 1 discriminator 1 view .LVU50
+  85:Src/syscalls.c ****   {
+ 243              		.loc 1 85 3 is_stmt 0 discriminator 1 view .LVU51
+ 244 0014 B542     		cmp	r5, r6
+ 245 0016 F8DB     		blt	.L14
+  88:Src/syscalls.c ****   }
+  89:Src/syscalls.c ****   return len;
+ 246              		.loc 1 89 3 is_stmt 1 view .LVU52
+  90:Src/syscalls.c **** }
+ 247              		.loc 1 90 1 is_stmt 0 view .LVU53
+ 248 0018 3046     		mov	r0, r6
+ 249 001a 70BD     		pop	{r4, r5, r6, pc}
+ 250              		.loc 1 90 1 view .LVU54
+ 251              		.cfi_endproc
+ 252              	.LFE30:
+ 254              		.section	.text._close,"ax",%progbits
+ 255              		.align	1
+ 256              		.global	_close
+ARM GAS  /tmp/cc9aEoPx.s 			page 7
+
+
+ 257              		.syntax unified
+ 258              		.thumb
+ 259              		.thumb_func
+ 260              		.fpu fpv5-d16
+ 262              	_close:
+ 263              	.LVL18:
+ 264              	.LFB31:
+  91:Src/syscalls.c **** 
+  92:Src/syscalls.c **** int _close(int file)
+  93:Src/syscalls.c **** {
+ 265              		.loc 1 93 1 is_stmt 1 view -0
+ 266              		.cfi_startproc
+ 267              		@ args = 0, pretend = 0, frame = 0
+ 268              		@ frame_needed = 0, uses_anonymous_args = 0
+ 269              		@ link register save eliminated.
+  94:Src/syscalls.c ****   (void)file;
+ 270              		.loc 1 94 3 view .LVU56
+  95:Src/syscalls.c ****   return -1;
+ 271              		.loc 1 95 3 view .LVU57
+  96:Src/syscalls.c **** }
+ 272              		.loc 1 96 1 is_stmt 0 view .LVU58
+ 273 0000 4FF0FF30 		mov	r0, #-1
+ 274              	.LVL19:
+ 275              		.loc 1 96 1 view .LVU59
+ 276 0004 7047     		bx	lr
+ 277              		.cfi_endproc
+ 278              	.LFE31:
+ 280              		.section	.text._fstat,"ax",%progbits
+ 281              		.align	1
+ 282              		.global	_fstat
+ 283              		.syntax unified
+ 284              		.thumb
+ 285              		.thumb_func
+ 286              		.fpu fpv5-d16
+ 288              	_fstat:
+ 289              	.LVL20:
+ 290              	.LFB32:
+  97:Src/syscalls.c **** 
+  98:Src/syscalls.c **** 
+  99:Src/syscalls.c **** int _fstat(int file, struct stat *st)
+ 100:Src/syscalls.c **** {
+ 291              		.loc 1 100 1 is_stmt 1 view -0
+ 292              		.cfi_startproc
+ 293              		@ args = 0, pretend = 0, frame = 0
+ 294              		@ frame_needed = 0, uses_anonymous_args = 0
+ 295              		@ link register save eliminated.
+ 101:Src/syscalls.c ****   (void)file;
+ 296              		.loc 1 101 3 view .LVU61
+ 102:Src/syscalls.c ****   st->st_mode = S_IFCHR;
+ 297              		.loc 1 102 3 view .LVU62
+ 298              		.loc 1 102 15 is_stmt 0 view .LVU63
+ 299 0000 4FF40053 		mov	r3, #8192
+ 300 0004 4B60     		str	r3, [r1, #4]
+ 103:Src/syscalls.c ****   return 0;
+ 301              		.loc 1 103 3 is_stmt 1 view .LVU64
+ 104:Src/syscalls.c **** }
+ 302              		.loc 1 104 1 is_stmt 0 view .LVU65
+ARM GAS  /tmp/cc9aEoPx.s 			page 8
+
+
+ 303 0006 0020     		movs	r0, #0
+ 304              	.LVL21:
+ 305              		.loc 1 104 1 view .LVU66
+ 306 0008 7047     		bx	lr
+ 307              		.cfi_endproc
+ 308              	.LFE32:
+ 310              		.section	.text._isatty,"ax",%progbits
+ 311              		.align	1
+ 312              		.global	_isatty
+ 313              		.syntax unified
+ 314              		.thumb
+ 315              		.thumb_func
+ 316              		.fpu fpv5-d16
+ 318              	_isatty:
+ 319              	.LVL22:
+ 320              	.LFB33:
+ 105:Src/syscalls.c **** 
+ 106:Src/syscalls.c **** int _isatty(int file)
+ 107:Src/syscalls.c **** {
+ 321              		.loc 1 107 1 is_stmt 1 view -0
+ 322              		.cfi_startproc
+ 323              		@ args = 0, pretend = 0, frame = 0
+ 324              		@ frame_needed = 0, uses_anonymous_args = 0
+ 325              		@ link register save eliminated.
+ 108:Src/syscalls.c ****   (void)file;
+ 326              		.loc 1 108 3 view .LVU68
+ 109:Src/syscalls.c ****   return 1;
+ 327              		.loc 1 109 3 view .LVU69
+ 110:Src/syscalls.c **** }
+ 328              		.loc 1 110 1 is_stmt 0 view .LVU70
+ 329 0000 0120     		movs	r0, #1
+ 330              	.LVL23:
+ 331              		.loc 1 110 1 view .LVU71
+ 332 0002 7047     		bx	lr
+ 333              		.cfi_endproc
+ 334              	.LFE33:
+ 336              		.section	.text._lseek,"ax",%progbits
+ 337              		.align	1
+ 338              		.global	_lseek
+ 339              		.syntax unified
+ 340              		.thumb
+ 341              		.thumb_func
+ 342              		.fpu fpv5-d16
+ 344              	_lseek:
+ 345              	.LVL24:
+ 346              	.LFB34:
+ 111:Src/syscalls.c **** 
+ 112:Src/syscalls.c **** int _lseek(int file, int ptr, int dir)
+ 113:Src/syscalls.c **** {
+ 347              		.loc 1 113 1 is_stmt 1 view -0
+ 348              		.cfi_startproc
+ 349              		@ args = 0, pretend = 0, frame = 0
+ 350              		@ frame_needed = 0, uses_anonymous_args = 0
+ 351              		@ link register save eliminated.
+ 114:Src/syscalls.c ****   (void)file;
+ 352              		.loc 1 114 3 view .LVU73
+ 115:Src/syscalls.c ****   (void)ptr;
+ARM GAS  /tmp/cc9aEoPx.s 			page 9
+
+
+ 353              		.loc 1 115 3 view .LVU74
+ 116:Src/syscalls.c ****   (void)dir;
+ 354              		.loc 1 116 3 view .LVU75
+ 117:Src/syscalls.c ****   return 0;
+ 355              		.loc 1 117 3 view .LVU76
+ 118:Src/syscalls.c **** }
+ 356              		.loc 1 118 1 is_stmt 0 view .LVU77
+ 357 0000 0020     		movs	r0, #0
+ 358              	.LVL25:
+ 359              		.loc 1 118 1 view .LVU78
+ 360 0002 7047     		bx	lr
+ 361              		.cfi_endproc
+ 362              	.LFE34:
+ 364              		.section	.text._open,"ax",%progbits
+ 365              		.align	1
+ 366              		.global	_open
+ 367              		.syntax unified
+ 368              		.thumb
+ 369              		.thumb_func
+ 370              		.fpu fpv5-d16
+ 372              	_open:
+ 373              	.LVL26:
+ 374              	.LFB35:
+ 119:Src/syscalls.c **** 
+ 120:Src/syscalls.c **** int _open(char *path, int flags, ...)
+ 121:Src/syscalls.c **** {
+ 375              		.loc 1 121 1 is_stmt 1 view -0
+ 376              		.cfi_startproc
+ 377              		@ args = 4, pretend = 12, frame = 0
+ 378              		@ frame_needed = 0, uses_anonymous_args = 1
+ 379              		@ link register save eliminated.
+ 380              		.loc 1 121 1 is_stmt 0 view .LVU80
+ 381 0000 0EB4     		push	{r1, r2, r3}
+ 382              	.LCFI4:
+ 383              		.cfi_def_cfa_offset 12
+ 384              		.cfi_offset 1, -12
+ 385              		.cfi_offset 2, -8
+ 386              		.cfi_offset 3, -4
+ 122:Src/syscalls.c ****   (void)path;
+ 387              		.loc 1 122 3 is_stmt 1 view .LVU81
+ 123:Src/syscalls.c ****   (void)flags;
+ 388              		.loc 1 123 3 view .LVU82
+ 124:Src/syscalls.c ****   /* Pretend like we always fail */
+ 125:Src/syscalls.c ****   return -1;
+ 389              		.loc 1 125 3 view .LVU83
+ 126:Src/syscalls.c **** }
+ 390              		.loc 1 126 1 is_stmt 0 view .LVU84
+ 391 0002 4FF0FF30 		mov	r0, #-1
+ 392              	.LVL27:
+ 393              		.loc 1 126 1 view .LVU85
+ 394 0006 03B0     		add	sp, sp, #12
+ 395              	.LCFI5:
+ 396              		.cfi_restore 3
+ 397              		.cfi_restore 2
+ 398              		.cfi_restore 1
+ 399              		.cfi_def_cfa_offset 0
+ 400 0008 7047     		bx	lr
+ARM GAS  /tmp/cc9aEoPx.s 			page 10
+
+
+ 401              		.cfi_endproc
+ 402              	.LFE35:
+ 404              		.section	.text._wait,"ax",%progbits
+ 405              		.align	1
+ 406              		.global	_wait
+ 407              		.syntax unified
+ 408              		.thumb
+ 409              		.thumb_func
+ 410              		.fpu fpv5-d16
+ 412              	_wait:
+ 413              	.LVL28:
+ 414              	.LFB36:
+ 127:Src/syscalls.c **** 
+ 128:Src/syscalls.c **** int _wait(int *status)
+ 129:Src/syscalls.c **** {
+ 415              		.loc 1 129 1 is_stmt 1 view -0
+ 416              		.cfi_startproc
+ 417              		@ args = 0, pretend = 0, frame = 0
+ 418              		@ frame_needed = 0, uses_anonymous_args = 0
+ 419              		.loc 1 129 1 is_stmt 0 view .LVU87
+ 420 0000 08B5     		push	{r3, lr}
+ 421              	.LCFI6:
+ 422              		.cfi_def_cfa_offset 8
+ 423              		.cfi_offset 3, -8
+ 424              		.cfi_offset 14, -4
+ 130:Src/syscalls.c ****   (void)status;
+ 425              		.loc 1 130 3 is_stmt 1 view .LVU88
+ 131:Src/syscalls.c ****   errno = ECHILD;
+ 426              		.loc 1 131 3 view .LVU89
+ 427 0002 FFF7FEFF 		bl	__errno
+ 428              	.LVL29:
+ 429              		.loc 1 131 9 is_stmt 0 view .LVU90
+ 430 0006 0A23     		movs	r3, #10
+ 431 0008 0360     		str	r3, [r0]
+ 132:Src/syscalls.c ****   return -1;
+ 432              		.loc 1 132 3 is_stmt 1 view .LVU91
+ 133:Src/syscalls.c **** }
+ 433              		.loc 1 133 1 is_stmt 0 view .LVU92
+ 434 000a 4FF0FF30 		mov	r0, #-1
+ 435 000e 08BD     		pop	{r3, pc}
+ 436              		.cfi_endproc
+ 437              	.LFE36:
+ 439              		.section	.text._unlink,"ax",%progbits
+ 440              		.align	1
+ 441              		.global	_unlink
+ 442              		.syntax unified
+ 443              		.thumb
+ 444              		.thumb_func
+ 445              		.fpu fpv5-d16
+ 447              	_unlink:
+ 448              	.LVL30:
+ 449              	.LFB37:
+ 134:Src/syscalls.c **** 
+ 135:Src/syscalls.c **** int _unlink(char *name)
+ 136:Src/syscalls.c **** {
+ 450              		.loc 1 136 1 is_stmt 1 view -0
+ 451              		.cfi_startproc
+ARM GAS  /tmp/cc9aEoPx.s 			page 11
+
+
+ 452              		@ args = 0, pretend = 0, frame = 0
+ 453              		@ frame_needed = 0, uses_anonymous_args = 0
+ 454              		.loc 1 136 1 is_stmt 0 view .LVU94
+ 455 0000 08B5     		push	{r3, lr}
+ 456              	.LCFI7:
+ 457              		.cfi_def_cfa_offset 8
+ 458              		.cfi_offset 3, -8
+ 459              		.cfi_offset 14, -4
+ 137:Src/syscalls.c ****   (void)name;
+ 460              		.loc 1 137 3 is_stmt 1 view .LVU95
+ 138:Src/syscalls.c ****   errno = ENOENT;
+ 461              		.loc 1 138 3 view .LVU96
+ 462 0002 FFF7FEFF 		bl	__errno
+ 463              	.LVL31:
+ 464              		.loc 1 138 9 is_stmt 0 view .LVU97
+ 465 0006 0223     		movs	r3, #2
+ 466 0008 0360     		str	r3, [r0]
+ 139:Src/syscalls.c ****   return -1;
+ 467              		.loc 1 139 3 is_stmt 1 view .LVU98
+ 140:Src/syscalls.c **** }
+ 468              		.loc 1 140 1 is_stmt 0 view .LVU99
+ 469 000a 4FF0FF30 		mov	r0, #-1
+ 470 000e 08BD     		pop	{r3, pc}
+ 471              		.cfi_endproc
+ 472              	.LFE37:
+ 474              		.section	.text._times,"ax",%progbits
+ 475              		.align	1
+ 476              		.global	_times
+ 477              		.syntax unified
+ 478              		.thumb
+ 479              		.thumb_func
+ 480              		.fpu fpv5-d16
+ 482              	_times:
+ 483              	.LVL32:
+ 484              	.LFB38:
+ 141:Src/syscalls.c **** 
+ 142:Src/syscalls.c **** int _times(struct tms *buf)
+ 143:Src/syscalls.c **** {
+ 485              		.loc 1 143 1 is_stmt 1 view -0
+ 486              		.cfi_startproc
+ 487              		@ args = 0, pretend = 0, frame = 0
+ 488              		@ frame_needed = 0, uses_anonymous_args = 0
+ 489              		@ link register save eliminated.
+ 144:Src/syscalls.c ****   (void)buf;
+ 490              		.loc 1 144 3 view .LVU101
+ 145:Src/syscalls.c ****   return -1;
+ 491              		.loc 1 145 3 view .LVU102
+ 146:Src/syscalls.c **** }
+ 492              		.loc 1 146 1 is_stmt 0 view .LVU103
+ 493 0000 4FF0FF30 		mov	r0, #-1
+ 494              	.LVL33:
+ 495              		.loc 1 146 1 view .LVU104
+ 496 0004 7047     		bx	lr
+ 497              		.cfi_endproc
+ 498              	.LFE38:
+ 500              		.section	.text._stat,"ax",%progbits
+ 501              		.align	1
+ARM GAS  /tmp/cc9aEoPx.s 			page 12
+
+
+ 502              		.global	_stat
+ 503              		.syntax unified
+ 504              		.thumb
+ 505              		.thumb_func
+ 506              		.fpu fpv5-d16
+ 508              	_stat:
+ 509              	.LVL34:
+ 510              	.LFB39:
+ 147:Src/syscalls.c **** 
+ 148:Src/syscalls.c **** int _stat(char *file, struct stat *st)
+ 149:Src/syscalls.c **** {
+ 511              		.loc 1 149 1 is_stmt 1 view -0
+ 512              		.cfi_startproc
+ 513              		@ args = 0, pretend = 0, frame = 0
+ 514              		@ frame_needed = 0, uses_anonymous_args = 0
+ 515              		@ link register save eliminated.
+ 150:Src/syscalls.c ****   (void)file;
+ 516              		.loc 1 150 3 view .LVU106
+ 151:Src/syscalls.c ****   st->st_mode = S_IFCHR;
+ 517              		.loc 1 151 3 view .LVU107
+ 518              		.loc 1 151 15 is_stmt 0 view .LVU108
+ 519 0000 4FF40053 		mov	r3, #8192
+ 520 0004 4B60     		str	r3, [r1, #4]
+ 152:Src/syscalls.c ****   return 0;
+ 521              		.loc 1 152 3 is_stmt 1 view .LVU109
+ 153:Src/syscalls.c **** }
+ 522              		.loc 1 153 1 is_stmt 0 view .LVU110
+ 523 0006 0020     		movs	r0, #0
+ 524              	.LVL35:
+ 525              		.loc 1 153 1 view .LVU111
+ 526 0008 7047     		bx	lr
+ 527              		.cfi_endproc
+ 528              	.LFE39:
+ 530              		.section	.text._link,"ax",%progbits
+ 531              		.align	1
+ 532              		.global	_link
+ 533              		.syntax unified
+ 534              		.thumb
+ 535              		.thumb_func
+ 536              		.fpu fpv5-d16
+ 538              	_link:
+ 539              	.LVL36:
+ 540              	.LFB40:
+ 154:Src/syscalls.c **** 
+ 155:Src/syscalls.c **** int _link(char *old, char *new)
+ 156:Src/syscalls.c **** {
+ 541              		.loc 1 156 1 is_stmt 1 view -0
+ 542              		.cfi_startproc
+ 543              		@ args = 0, pretend = 0, frame = 0
+ 544              		@ frame_needed = 0, uses_anonymous_args = 0
+ 545              		.loc 1 156 1 is_stmt 0 view .LVU113
+ 546 0000 08B5     		push	{r3, lr}
+ 547              	.LCFI8:
+ 548              		.cfi_def_cfa_offset 8
+ 549              		.cfi_offset 3, -8
+ 550              		.cfi_offset 14, -4
+ 157:Src/syscalls.c ****   (void)old;
+ARM GAS  /tmp/cc9aEoPx.s 			page 13
+
+
+ 551              		.loc 1 157 3 is_stmt 1 view .LVU114
+ 158:Src/syscalls.c ****   (void)new;
+ 552              		.loc 1 158 3 view .LVU115
+ 159:Src/syscalls.c ****   errno = EMLINK;
+ 553              		.loc 1 159 3 view .LVU116
+ 554 0002 FFF7FEFF 		bl	__errno
+ 555              	.LVL37:
+ 556              		.loc 1 159 9 is_stmt 0 view .LVU117
+ 557 0006 1F23     		movs	r3, #31
+ 558 0008 0360     		str	r3, [r0]
+ 160:Src/syscalls.c ****   return -1;
+ 559              		.loc 1 160 3 is_stmt 1 view .LVU118
+ 161:Src/syscalls.c **** }
+ 560              		.loc 1 161 1 is_stmt 0 view .LVU119
+ 561 000a 4FF0FF30 		mov	r0, #-1
+ 562 000e 08BD     		pop	{r3, pc}
+ 563              		.cfi_endproc
+ 564              	.LFE40:
+ 566              		.section	.text._fork,"ax",%progbits
+ 567              		.align	1
+ 568              		.global	_fork
+ 569              		.syntax unified
+ 570              		.thumb
+ 571              		.thumb_func
+ 572              		.fpu fpv5-d16
+ 574              	_fork:
+ 575              	.LFB41:
+ 162:Src/syscalls.c **** 
+ 163:Src/syscalls.c **** int _fork(void)
+ 164:Src/syscalls.c **** {
+ 576              		.loc 1 164 1 is_stmt 1 view -0
+ 577              		.cfi_startproc
+ 578              		@ args = 0, pretend = 0, frame = 0
+ 579              		@ frame_needed = 0, uses_anonymous_args = 0
+ 580 0000 08B5     		push	{r3, lr}
+ 581              	.LCFI9:
+ 582              		.cfi_def_cfa_offset 8
+ 583              		.cfi_offset 3, -8
+ 584              		.cfi_offset 14, -4
+ 165:Src/syscalls.c ****   errno = EAGAIN;
+ 585              		.loc 1 165 3 view .LVU121
+ 586 0002 FFF7FEFF 		bl	__errno
+ 587              	.LVL38:
+ 588              		.loc 1 165 9 is_stmt 0 view .LVU122
+ 589 0006 0B23     		movs	r3, #11
+ 590 0008 0360     		str	r3, [r0]
+ 166:Src/syscalls.c ****   return -1;
+ 591              		.loc 1 166 3 is_stmt 1 view .LVU123
+ 167:Src/syscalls.c **** }
+ 592              		.loc 1 167 1 is_stmt 0 view .LVU124
+ 593 000a 4FF0FF30 		mov	r0, #-1
+ 594 000e 08BD     		pop	{r3, pc}
+ 595              		.cfi_endproc
+ 596              	.LFE41:
+ 598              		.section	.text._execve,"ax",%progbits
+ 599              		.align	1
+ 600              		.global	_execve
+ARM GAS  /tmp/cc9aEoPx.s 			page 14
+
+
+ 601              		.syntax unified
+ 602              		.thumb
+ 603              		.thumb_func
+ 604              		.fpu fpv5-d16
+ 606              	_execve:
+ 607              	.LVL39:
+ 608              	.LFB42:
+ 168:Src/syscalls.c **** 
+ 169:Src/syscalls.c **** int _execve(char *name, char **argv, char **env)
+ 170:Src/syscalls.c **** {
+ 609              		.loc 1 170 1 is_stmt 1 view -0
+ 610              		.cfi_startproc
+ 611              		@ args = 0, pretend = 0, frame = 0
+ 612              		@ frame_needed = 0, uses_anonymous_args = 0
+ 613              		.loc 1 170 1 is_stmt 0 view .LVU126
+ 614 0000 08B5     		push	{r3, lr}
+ 615              	.LCFI10:
+ 616              		.cfi_def_cfa_offset 8
+ 617              		.cfi_offset 3, -8
+ 618              		.cfi_offset 14, -4
+ 171:Src/syscalls.c ****   (void)name;
+ 619              		.loc 1 171 3 is_stmt 1 view .LVU127
+ 172:Src/syscalls.c ****   (void)argv;
+ 620              		.loc 1 172 3 view .LVU128
+ 173:Src/syscalls.c ****   (void)env;
+ 621              		.loc 1 173 3 view .LVU129
+ 174:Src/syscalls.c ****   errno = ENOMEM;
+ 622              		.loc 1 174 3 view .LVU130
+ 623 0002 FFF7FEFF 		bl	__errno
+ 624              	.LVL40:
+ 625              		.loc 1 174 9 is_stmt 0 view .LVU131
+ 626 0006 0C23     		movs	r3, #12
+ 627 0008 0360     		str	r3, [r0]
+ 175:Src/syscalls.c ****   return -1;
+ 628              		.loc 1 175 3 is_stmt 1 view .LVU132
+ 176:Src/syscalls.c **** }
+ 629              		.loc 1 176 1 is_stmt 0 view .LVU133
+ 630 000a 4FF0FF30 		mov	r0, #-1
+ 631 000e 08BD     		pop	{r3, pc}
+ 632              		.cfi_endproc
+ 633              	.LFE42:
+ 635              		.global	environ
+ 636              		.global	__env
+ 637              		.section	.bss.__env,"aw",%nobits
+ 638              		.align	2
+ 641              	__env:
+ 642 0000 00000000 		.space	4
+ 643              		.section	.data.environ,"aw"
+ 644              		.align	2
+ 647              	environ:
+ 648 0000 00000000 		.word	__env
+ 649              		.weak	__io_putchar
+ 650              		.weak	__io_getchar
+ 651              		.text
+ 652              	.Letext0:
+ 653              		.file 2 "/usr/include/newlib/machine/_default_types.h"
+ 654              		.file 3 "/usr/include/newlib/sys/_types.h"
+ARM GAS  /tmp/cc9aEoPx.s 			page 15
+
+
+ 655              		.file 4 "/usr/include/newlib/sys/_timeval.h"
+ 656              		.file 5 "/usr/include/newlib/sys/_timespec.h"
+ 657              		.file 6 "/usr/include/newlib/sys/types.h"
+ 658              		.file 7 "/usr/include/newlib/sys/stat.h"
+ 659              		.file 8 "/usr/include/newlib/sys/times.h"
+ 660              		.file 9 "/usr/include/newlib/sys/errno.h"
+ARM GAS  /tmp/cc9aEoPx.s 			page 16
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 syscalls.c
+     /tmp/cc9aEoPx.s:17     .text.initialise_monitor_handles:0000000000000000 $t
+     /tmp/cc9aEoPx.s:25     .text.initialise_monitor_handles:0000000000000000 initialise_monitor_handles
+     /tmp/cc9aEoPx.s:39     .text._getpid:0000000000000000 $t
+     /tmp/cc9aEoPx.s:46     .text._getpid:0000000000000000 _getpid
+     /tmp/cc9aEoPx.s:61     .text._kill:0000000000000000 $t
+     /tmp/cc9aEoPx.s:68     .text._kill:0000000000000000 _kill
+     /tmp/cc9aEoPx.s:97     .text._exit:0000000000000000 $t
+     /tmp/cc9aEoPx.s:104    .text._exit:0000000000000000 _exit
+     /tmp/cc9aEoPx.s:131    .text._read:0000000000000000 $t
+     /tmp/cc9aEoPx.s:138    .text._read:0000000000000000 _read
+     /tmp/cc9aEoPx.s:196    .text._write:0000000000000000 $t
+     /tmp/cc9aEoPx.s:203    .text._write:0000000000000000 _write
+     /tmp/cc9aEoPx.s:255    .text._close:0000000000000000 $t
+     /tmp/cc9aEoPx.s:262    .text._close:0000000000000000 _close
+     /tmp/cc9aEoPx.s:281    .text._fstat:0000000000000000 $t
+     /tmp/cc9aEoPx.s:288    .text._fstat:0000000000000000 _fstat
+     /tmp/cc9aEoPx.s:311    .text._isatty:0000000000000000 $t
+     /tmp/cc9aEoPx.s:318    .text._isatty:0000000000000000 _isatty
+     /tmp/cc9aEoPx.s:337    .text._lseek:0000000000000000 $t
+     /tmp/cc9aEoPx.s:344    .text._lseek:0000000000000000 _lseek
+     /tmp/cc9aEoPx.s:365    .text._open:0000000000000000 $t
+     /tmp/cc9aEoPx.s:372    .text._open:0000000000000000 _open
+     /tmp/cc9aEoPx.s:405    .text._wait:0000000000000000 $t
+     /tmp/cc9aEoPx.s:412    .text._wait:0000000000000000 _wait
+     /tmp/cc9aEoPx.s:440    .text._unlink:0000000000000000 $t
+     /tmp/cc9aEoPx.s:447    .text._unlink:0000000000000000 _unlink
+     /tmp/cc9aEoPx.s:475    .text._times:0000000000000000 $t
+     /tmp/cc9aEoPx.s:482    .text._times:0000000000000000 _times
+     /tmp/cc9aEoPx.s:501    .text._stat:0000000000000000 $t
+     /tmp/cc9aEoPx.s:508    .text._stat:0000000000000000 _stat
+     /tmp/cc9aEoPx.s:531    .text._link:0000000000000000 $t
+     /tmp/cc9aEoPx.s:538    .text._link:0000000000000000 _link
+     /tmp/cc9aEoPx.s:567    .text._fork:0000000000000000 $t
+     /tmp/cc9aEoPx.s:574    .text._fork:0000000000000000 _fork
+     /tmp/cc9aEoPx.s:599    .text._execve:0000000000000000 $t
+     /tmp/cc9aEoPx.s:606    .text._execve:0000000000000000 _execve
+     /tmp/cc9aEoPx.s:647    .data.environ:0000000000000000 environ
+     /tmp/cc9aEoPx.s:641    .bss.__env:0000000000000000 __env
+     /tmp/cc9aEoPx.s:638    .bss.__env:0000000000000000 $d
+     /tmp/cc9aEoPx.s:644    .data.environ:0000000000000000 $d
+
+UNDEFINED SYMBOLS
+__errno
+__io_getchar
+__io_putchar
diff --git a/build/syscalls.o b/build/syscalls.o
new file mode 100644
index 0000000..5ae61d0
Binary files /dev/null and b/build/syscalls.o differ
diff --git a/build/sysmem.d b/build/sysmem.d
new file mode 100644
index 0000000..aee2087
--- /dev/null
+++ b/build/sysmem.d
@@ -0,0 +1 @@
+build/sysmem.o: Src/sysmem.c
diff --git a/build/sysmem.lst b/build/sysmem.lst
new file mode 100644
index 0000000..6e0e567
--- /dev/null
+++ b/build/sysmem.lst
@@ -0,0 +1,230 @@
+ARM GAS  /tmp/cc9NFVkD.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"sysmem.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text._sbrk,"ax",%progbits
+  17              		.align	1
+  18              		.global	_sbrk
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	_sbrk:
+  26              	.LVL0:
+  27              	.LFB0:
+  28              		.file 1 "Src/sysmem.c"
+   1:Src/sysmem.c  **** /**
+   2:Src/sysmem.c  ****  ******************************************************************************
+   3:Src/sysmem.c  ****  * @file      sysmem.c
+   4:Src/sysmem.c  ****  * @author    Generated by STM32CubeMX
+   5:Src/sysmem.c  ****  * @brief     System Memory calls file
+   6:Src/sysmem.c  ****  *
+   7:Src/sysmem.c  ****  *            For more information about which C functions
+   8:Src/sysmem.c  ****  *            need which of these lowlevel functions
+   9:Src/sysmem.c  ****  *            please consult the newlib libc manual
+  10:Src/sysmem.c  ****  ******************************************************************************
+  11:Src/sysmem.c  ****  * @attention
+  12:Src/sysmem.c  ****  *
+  13:Src/sysmem.c  ****  * Copyright (c) 2024 STMicroelectronics.
+  14:Src/sysmem.c  ****  * All rights reserved.
+  15:Src/sysmem.c  ****  *
+  16:Src/sysmem.c  ****  * This software is licensed under terms that can be found in the LICENSE file
+  17:Src/sysmem.c  ****  * in the root directory of this software component.
+  18:Src/sysmem.c  ****  * If no LICENSE file comes with this software, it is provided AS-IS.
+  19:Src/sysmem.c  ****  *
+  20:Src/sysmem.c  ****  ******************************************************************************
+  21:Src/sysmem.c  ****  */
+  22:Src/sysmem.c  **** 
+  23:Src/sysmem.c  **** /* Includes */
+  24:Src/sysmem.c  **** #include 
+  25:Src/sysmem.c  **** #include 
+  26:Src/sysmem.c  **** 
+  27:Src/sysmem.c  **** /**
+  28:Src/sysmem.c  ****  * Pointer to the current high watermark of the heap usage
+  29:Src/sysmem.c  ****  */
+  30:Src/sysmem.c  **** static uint8_t *__sbrk_heap_end = NULL;
+ARM GAS  /tmp/cc9NFVkD.s 			page 2
+
+
+  31:Src/sysmem.c  **** 
+  32:Src/sysmem.c  **** /**
+  33:Src/sysmem.c  ****  * @brief _sbrk() allocates memory to the newlib heap and is used by malloc
+  34:Src/sysmem.c  ****  *        and others from the C library
+  35:Src/sysmem.c  ****  *
+  36:Src/sysmem.c  ****  * @verbatim
+  37:Src/sysmem.c  ****  * ############################################################################
+  38:Src/sysmem.c  ****  * #  .data  #  .bss  #       newlib heap       #          MSP stack          #
+  39:Src/sysmem.c  ****  * #         #        #                         # Reserved by _Min_Stack_Size #
+  40:Src/sysmem.c  ****  * ############################################################################
+  41:Src/sysmem.c  ****  * ^-- RAM start      ^-- _end                             _estack, RAM end --^
+  42:Src/sysmem.c  ****  * @endverbatim
+  43:Src/sysmem.c  ****  *
+  44:Src/sysmem.c  ****  * This implementation starts allocating at the '_end' linker symbol
+  45:Src/sysmem.c  ****  * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
+  46:Src/sysmem.c  ****  * The implementation considers '_estack' linker symbol to be RAM end
+  47:Src/sysmem.c  ****  * NOTE: If the MSP stack, at any point during execution, grows larger than the
+  48:Src/sysmem.c  ****  * reserved size, please increase the '_Min_Stack_Size'.
+  49:Src/sysmem.c  ****  *
+  50:Src/sysmem.c  ****  * @param incr Memory size
+  51:Src/sysmem.c  ****  * @return Pointer to allocated memory
+  52:Src/sysmem.c  ****  */
+  53:Src/sysmem.c  **** void *_sbrk(ptrdiff_t incr)
+  54:Src/sysmem.c  **** {
+  29              		.loc 1 54 1 view -0
+  30              		.cfi_startproc
+  31              		@ args = 0, pretend = 0, frame = 0
+  32              		@ frame_needed = 0, uses_anonymous_args = 0
+  33              		.loc 1 54 1 is_stmt 0 view .LVU1
+  34 0000 10B5     		push	{r4, lr}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 8
+  37              		.cfi_offset 4, -8
+  38              		.cfi_offset 14, -4
+  39 0002 0346     		mov	r3, r0
+  55:Src/sysmem.c  ****   extern uint8_t _end; /* Symbol defined in the linker script */
+  40              		.loc 1 55 3 is_stmt 1 view .LVU2
+  56:Src/sysmem.c  ****   extern uint8_t _estack; /* Symbol defined in the linker script */
+  41              		.loc 1 56 3 view .LVU3
+  57:Src/sysmem.c  ****   extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+  42              		.loc 1 57 3 view .LVU4
+  58:Src/sysmem.c  ****   const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+  43              		.loc 1 58 3 view .LVU5
+  44              		.loc 1 58 18 is_stmt 0 view .LVU6
+  45 0004 0C4A     		ldr	r2, .L8
+  46 0006 0D49     		ldr	r1, .L8+4
+  59:Src/sysmem.c  ****   const uint8_t *max_heap = (uint8_t *)stack_limit;
+  47              		.loc 1 59 3 is_stmt 1 view .LVU7
+  48              	.LVL1:
+  60:Src/sysmem.c  ****   uint8_t *prev_heap_end;
+  49              		.loc 1 60 3 view .LVU8
+  61:Src/sysmem.c  **** 
+  62:Src/sysmem.c  ****   /* Initialize heap end at first call */
+  63:Src/sysmem.c  ****   if (NULL == __sbrk_heap_end)
+  50              		.loc 1 63 3 view .LVU9
+  51              		.loc 1 63 12 is_stmt 0 view .LVU10
+  52 0008 0D48     		ldr	r0, .L8+8
+ARM GAS  /tmp/cc9NFVkD.s 			page 3
+
+
+  53              	.LVL2:
+  54              		.loc 1 63 12 view .LVU11
+  55 000a 0068     		ldr	r0, [r0]
+  56              		.loc 1 63 6 view .LVU12
+  57 000c 40B1     		cbz	r0, .L6
+  58              	.L2:
+  64:Src/sysmem.c  ****   {
+  65:Src/sysmem.c  ****     __sbrk_heap_end = &_end;
+  66:Src/sysmem.c  ****   }
+  67:Src/sysmem.c  **** 
+  68:Src/sysmem.c  ****   /* Protect heap from growing into the reserved MSP stack */
+  69:Src/sysmem.c  ****   if (__sbrk_heap_end + incr > max_heap)
+  59              		.loc 1 69 3 is_stmt 1 view .LVU13
+  60              		.loc 1 69 23 is_stmt 0 view .LVU14
+  61 000e 0C48     		ldr	r0, .L8+8
+  62 0010 0068     		ldr	r0, [r0]
+  63 0012 0344     		add	r3, r3, r0
+  64              	.LVL3:
+  65              		.loc 1 69 6 view .LVU15
+  66 0014 521A     		subs	r2, r2, r1
+  67 0016 9342     		cmp	r3, r2
+  68 0018 06D8     		bhi	.L7
+  70:Src/sysmem.c  ****   {
+  71:Src/sysmem.c  ****     errno = ENOMEM;
+  72:Src/sysmem.c  ****     return (void *)-1;
+  73:Src/sysmem.c  ****   }
+  74:Src/sysmem.c  **** 
+  75:Src/sysmem.c  ****   prev_heap_end = __sbrk_heap_end;
+  69              		.loc 1 75 3 is_stmt 1 view .LVU16
+  70              	.LVL4:
+  76:Src/sysmem.c  ****   __sbrk_heap_end += incr;
+  71              		.loc 1 76 3 view .LVU17
+  72              		.loc 1 76 19 is_stmt 0 view .LVU18
+  73 001a 094A     		ldr	r2, .L8+8
+  74 001c 1360     		str	r3, [r2]
+  77:Src/sysmem.c  **** 
+  78:Src/sysmem.c  ****   return (void *)prev_heap_end;
+  75              		.loc 1 78 3 is_stmt 1 view .LVU19
+  76              	.LVL5:
+  77              	.L1:
+  79:Src/sysmem.c  **** }
+  78              		.loc 1 79 1 is_stmt 0 view .LVU20
+  79 001e 10BD     		pop	{r4, pc}
+  80              	.LVL6:
+  81              	.L6:
+  65:Src/sysmem.c  ****   }
+  82              		.loc 1 65 5 is_stmt 1 view .LVU21
+  65:Src/sysmem.c  ****   }
+  83              		.loc 1 65 21 is_stmt 0 view .LVU22
+  84 0020 0748     		ldr	r0, .L8+8
+  85 0022 084C     		ldr	r4, .L8+12
+  86 0024 0460     		str	r4, [r0]
+  87 0026 F2E7     		b	.L2
+  88              	.LVL7:
+  89              	.L7:
+  71:Src/sysmem.c  ****     return (void *)-1;
+  90              		.loc 1 71 5 is_stmt 1 view .LVU23
+ARM GAS  /tmp/cc9NFVkD.s 			page 4
+
+
+  91 0028 FFF7FEFF 		bl	__errno
+  92              	.LVL8:
+  71:Src/sysmem.c  ****     return (void *)-1;
+  93              		.loc 1 71 11 is_stmt 0 view .LVU24
+  94 002c 0C23     		movs	r3, #12
+  95 002e 0360     		str	r3, [r0]
+  72:Src/sysmem.c  ****   }
+  96              		.loc 1 72 5 is_stmt 1 view .LVU25
+  72:Src/sysmem.c  ****   }
+  97              		.loc 1 72 12 is_stmt 0 view .LVU26
+  98 0030 4FF0FF30 		mov	r0, #-1
+  99 0034 F3E7     		b	.L1
+ 100              	.L9:
+ 101 0036 00BF     		.align	2
+ 102              	.L8:
+ 103 0038 00000000 		.word	_estack
+ 104 003c 00000000 		.word	_Min_Stack_Size
+ 105 0040 00000000 		.word	.LANCHOR0
+ 106 0044 00000000 		.word	_end
+ 107              		.cfi_endproc
+ 108              	.LFE0:
+ 110              		.section	.bss.__sbrk_heap_end,"aw",%nobits
+ 111              		.align	2
+ 112              		.set	.LANCHOR0,. + 0
+ 115              	__sbrk_heap_end:
+ 116 0000 00000000 		.space	4
+ 117              		.text
+ 118              	.Letext0:
+ 119              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stddef.h"
+ 120              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 121              		.file 4 "/usr/include/newlib/sys/errno.h"
+ARM GAS  /tmp/cc9NFVkD.s 			page 5
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 sysmem.c
+     /tmp/cc9NFVkD.s:17     .text._sbrk:0000000000000000 $t
+     /tmp/cc9NFVkD.s:25     .text._sbrk:0000000000000000 _sbrk
+     /tmp/cc9NFVkD.s:103    .text._sbrk:0000000000000038 $d
+     /tmp/cc9NFVkD.s:111    .bss.__sbrk_heap_end:0000000000000000 $d
+     /tmp/cc9NFVkD.s:115    .bss.__sbrk_heap_end:0000000000000000 __sbrk_heap_end
+
+UNDEFINED SYMBOLS
+__errno
+_estack
+_Min_Stack_Size
+_end
diff --git a/build/sysmem.o b/build/sysmem.o
new file mode 100644
index 0000000..9923853
Binary files /dev/null and b/build/sysmem.o differ
diff --git a/build/system_stm32f7xx.d b/build/system_stm32f7xx.d
new file mode 100644
index 0000000..2a7e4f2
--- /dev/null
+++ b/build/system_stm32f7xx.d
@@ -0,0 +1,63 @@
+build/system_stm32f7xx.o: Src/system_stm32f7xx.c \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \
+ Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \
+ Drivers/CMSIS/Include/mpu_armv7.h \
+ Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ Inc/stm32f7xx_hal_conf.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+Drivers/CMSIS/Include/core_cm7.h:
+Drivers/CMSIS/Include/cmsis_version.h:
+Drivers/CMSIS/Include/cmsis_compiler.h:
+Drivers/CMSIS/Include/cmsis_gcc.h:
+Drivers/CMSIS/Include/mpu_armv7.h:
+Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+Inc/stm32f7xx_hal_conf.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
diff --git a/build/system_stm32f7xx.lst b/build/system_stm32f7xx.lst
new file mode 100644
index 0000000..db7bc5e
--- /dev/null
+++ b/build/system_stm32f7xx.lst
@@ -0,0 +1,570 @@
+ARM GAS  /tmp/cc4hZZNo.s 			page 1
+
+
+   1              		.cpu cortex-m7
+   2              		.eabi_attribute 28, 1
+   3              		.eabi_attribute 20, 1
+   4              		.eabi_attribute 21, 1
+   5              		.eabi_attribute 23, 3
+   6              		.eabi_attribute 24, 1
+   7              		.eabi_attribute 25, 1
+   8              		.eabi_attribute 26, 1
+   9              		.eabi_attribute 30, 1
+  10              		.eabi_attribute 34, 1
+  11              		.eabi_attribute 18, 4
+  12              		.file	"system_stm32f7xx.c"
+  13              		.text
+  14              	.Ltext0:
+  15              		.cfi_sections	.debug_frame
+  16              		.section	.text.SystemInit,"ax",%progbits
+  17              		.align	1
+  18              		.global	SystemInit
+  19              		.arch armv7e-m
+  20              		.syntax unified
+  21              		.thumb
+  22              		.thumb_func
+  23              		.fpu fpv5-d16
+  25              	SystemInit:
+  26              	.LFB141:
+  27              		.file 1 "Src/system_stm32f7xx.c"
+   1:Src/system_stm32f7xx.c **** /**
+   2:Src/system_stm32f7xx.c ****   ******************************************************************************
+   3:Src/system_stm32f7xx.c ****   * @file    system_stm32f7xx.c
+   4:Src/system_stm32f7xx.c ****   * @author  MCD Application Team
+   5:Src/system_stm32f7xx.c ****   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
+   6:Src/system_stm32f7xx.c ****   *
+   7:Src/system_stm32f7xx.c ****   *   This file provides two functions and one global variable to be called from 
+   8:Src/system_stm32f7xx.c ****   *   user application:
+   9:Src/system_stm32f7xx.c ****   *      - SystemInit(): This function is called at startup just after reset and 
+  10:Src/system_stm32f7xx.c ****   *                      before branch to main program. This call is made inside
+  11:Src/system_stm32f7xx.c ****   *                      the "startup_stm32f7xx.s" file.
+  12:Src/system_stm32f7xx.c ****   *
+  13:Src/system_stm32f7xx.c ****   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  14:Src/system_stm32f7xx.c ****   *                                  by the user application to setup the SysTick 
+  15:Src/system_stm32f7xx.c ****   *                                  timer or configure other parameters.
+  16:Src/system_stm32f7xx.c ****   *                                     
+  17:Src/system_stm32f7xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  18:Src/system_stm32f7xx.c ****   *                                 be called whenever the core clock is changed
+  19:Src/system_stm32f7xx.c ****   *                                 during program execution.
+  20:Src/system_stm32f7xx.c ****   *
+  21:Src/system_stm32f7xx.c ****   *
+  22:Src/system_stm32f7xx.c ****   ******************************************************************************
+  23:Src/system_stm32f7xx.c ****   * @attention
+  24:Src/system_stm32f7xx.c ****   *
+  25:Src/system_stm32f7xx.c ****   * Copyright (c) 2016 STMicroelectronics.
+  26:Src/system_stm32f7xx.c ****   * All rights reserved.
+  27:Src/system_stm32f7xx.c ****   *
+  28:Src/system_stm32f7xx.c ****   * This software is licensed under terms that can be found in the LICENSE file
+  29:Src/system_stm32f7xx.c ****   * in the root directory of this software component.
+  30:Src/system_stm32f7xx.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
+  31:Src/system_stm32f7xx.c ****   *
+ARM GAS  /tmp/cc4hZZNo.s 			page 2
+
+
+  32:Src/system_stm32f7xx.c ****   ******************************************************************************
+  33:Src/system_stm32f7xx.c ****   */
+  34:Src/system_stm32f7xx.c **** 
+  35:Src/system_stm32f7xx.c **** /** @addtogroup CMSIS
+  36:Src/system_stm32f7xx.c ****   * @{
+  37:Src/system_stm32f7xx.c ****   */
+  38:Src/system_stm32f7xx.c **** 
+  39:Src/system_stm32f7xx.c **** /** @addtogroup stm32f7xx_system
+  40:Src/system_stm32f7xx.c ****   * @{
+  41:Src/system_stm32f7xx.c ****   */  
+  42:Src/system_stm32f7xx.c ****   
+  43:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Includes
+  44:Src/system_stm32f7xx.c ****   * @{
+  45:Src/system_stm32f7xx.c ****   */
+  46:Src/system_stm32f7xx.c **** 
+  47:Src/system_stm32f7xx.c **** #include "stm32f7xx.h"
+  48:Src/system_stm32f7xx.c **** 
+  49:Src/system_stm32f7xx.c **** #if !defined  (HSE_VALUE) 
+  50:Src/system_stm32f7xx.c ****   #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+  51:Src/system_stm32f7xx.c **** #endif /* HSE_VALUE */
+  52:Src/system_stm32f7xx.c **** 
+  53:Src/system_stm32f7xx.c **** #if !defined  (HSI_VALUE)
+  54:Src/system_stm32f7xx.c ****   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+  55:Src/system_stm32f7xx.c **** #endif /* HSI_VALUE */
+  56:Src/system_stm32f7xx.c **** 
+  57:Src/system_stm32f7xx.c **** /**
+  58:Src/system_stm32f7xx.c ****   * @}
+  59:Src/system_stm32f7xx.c ****   */
+  60:Src/system_stm32f7xx.c **** 
+  61:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_TypesDefinitions
+  62:Src/system_stm32f7xx.c ****   * @{
+  63:Src/system_stm32f7xx.c ****   */
+  64:Src/system_stm32f7xx.c **** 
+  65:Src/system_stm32f7xx.c **** /**
+  66:Src/system_stm32f7xx.c ****   * @}
+  67:Src/system_stm32f7xx.c ****   */
+  68:Src/system_stm32f7xx.c **** 
+  69:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Defines
+  70:Src/system_stm32f7xx.c ****   * @{
+  71:Src/system_stm32f7xx.c ****   */
+  72:Src/system_stm32f7xx.c **** 
+  73:Src/system_stm32f7xx.c **** /************************* Miscellaneous Configuration ************************/
+  74:Src/system_stm32f7xx.c **** 
+  75:Src/system_stm32f7xx.c **** /* Note: Following vector table addresses must be defined in line with linker
+  76:Src/system_stm32f7xx.c ****          configuration. */
+  77:Src/system_stm32f7xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
+  78:Src/system_stm32f7xx.c ****      anywhere in Flash or Sram, else the vector table is kept at the automatic
+  79:Src/system_stm32f7xx.c ****      remap of boot address selected */
+  80:Src/system_stm32f7xx.c **** /* #define USER_VECT_TAB_ADDRESS */
+  81:Src/system_stm32f7xx.c **** 
+  82:Src/system_stm32f7xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
+  83:Src/system_stm32f7xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
+  84:Src/system_stm32f7xx.c ****      in Sram else user remap will be done in Flash. */
+  85:Src/system_stm32f7xx.c **** /* #define VECT_TAB_SRAM */
+  86:Src/system_stm32f7xx.c **** #if defined(VECT_TAB_SRAM)
+  87:Src/system_stm32f7xx.c **** #define VECT_TAB_BASE_ADDRESS   RAMDTCM_BASE    /*!< Vector Table base address field.
+  88:Src/system_stm32f7xx.c ****                                                      This value must be a multiple of 0x200. */
+ARM GAS  /tmp/cc4hZZNo.s 			page 3
+
+
+  89:Src/system_stm32f7xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+  90:Src/system_stm32f7xx.c ****                                                      This value must be a multiple of 0x200. */
+  91:Src/system_stm32f7xx.c **** #else
+  92:Src/system_stm32f7xx.c **** #define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
+  93:Src/system_stm32f7xx.c ****                                                      This value must be a multiple of 0x200. */
+  94:Src/system_stm32f7xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+  95:Src/system_stm32f7xx.c ****                                                      This value must be a multiple of 0x200. */
+  96:Src/system_stm32f7xx.c **** #endif /* VECT_TAB_SRAM */
+  97:Src/system_stm32f7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
+  98:Src/system_stm32f7xx.c **** /******************************************************************************/
+  99:Src/system_stm32f7xx.c **** 
+ 100:Src/system_stm32f7xx.c **** /**
+ 101:Src/system_stm32f7xx.c ****   * @}
+ 102:Src/system_stm32f7xx.c ****   */
+ 103:Src/system_stm32f7xx.c **** 
+ 104:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Macros
+ 105:Src/system_stm32f7xx.c ****   * @{
+ 106:Src/system_stm32f7xx.c ****   */
+ 107:Src/system_stm32f7xx.c **** 
+ 108:Src/system_stm32f7xx.c **** /**
+ 109:Src/system_stm32f7xx.c ****   * @}
+ 110:Src/system_stm32f7xx.c ****   */
+ 111:Src/system_stm32f7xx.c **** 
+ 112:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Variables
+ 113:Src/system_stm32f7xx.c ****   * @{
+ 114:Src/system_stm32f7xx.c ****   */
+ 115:Src/system_stm32f7xx.c **** 
+ 116:Src/system_stm32f7xx.c ****   /* This variable is updated in three ways:
+ 117:Src/system_stm32f7xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
+ 118:Src/system_stm32f7xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 119:Src/system_stm32f7xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+ 120:Src/system_stm32f7xx.c ****          Note: If you use this function to configure the system clock; then there
+ 121:Src/system_stm32f7xx.c ****                is no need to call the 2 first functions listed above, since SystemCoreClock
+ 122:Src/system_stm32f7xx.c ****                variable is updated automatically.
+ 123:Src/system_stm32f7xx.c ****   */
+ 124:Src/system_stm32f7xx.c ****   uint32_t SystemCoreClock = 16000000;
+ 125:Src/system_stm32f7xx.c ****   const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+ 126:Src/system_stm32f7xx.c ****   const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+ 127:Src/system_stm32f7xx.c **** 
+ 128:Src/system_stm32f7xx.c **** /**
+ 129:Src/system_stm32f7xx.c ****   * @}
+ 130:Src/system_stm32f7xx.c ****   */
+ 131:Src/system_stm32f7xx.c **** 
+ 132:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
+ 133:Src/system_stm32f7xx.c ****   * @{
+ 134:Src/system_stm32f7xx.c ****   */
+ 135:Src/system_stm32f7xx.c **** 
+ 136:Src/system_stm32f7xx.c **** /**
+ 137:Src/system_stm32f7xx.c ****   * @}
+ 138:Src/system_stm32f7xx.c ****   */
+ 139:Src/system_stm32f7xx.c **** 
+ 140:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Functions
+ 141:Src/system_stm32f7xx.c ****   * @{
+ 142:Src/system_stm32f7xx.c ****   */
+ 143:Src/system_stm32f7xx.c **** 
+ 144:Src/system_stm32f7xx.c **** /**
+ 145:Src/system_stm32f7xx.c ****   * @brief  Setup the microcontroller system
+ARM GAS  /tmp/cc4hZZNo.s 			page 4
+
+
+ 146:Src/system_stm32f7xx.c ****   *         Initialize the Embedded Flash Interface, the PLL and update the 
+ 147:Src/system_stm32f7xx.c ****   *         SystemFrequency variable.
+ 148:Src/system_stm32f7xx.c ****   * @param  None
+ 149:Src/system_stm32f7xx.c ****   * @retval None
+ 150:Src/system_stm32f7xx.c ****   */
+ 151:Src/system_stm32f7xx.c **** void SystemInit(void)
+ 152:Src/system_stm32f7xx.c **** {
+  28              		.loc 1 152 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+ 153:Src/system_stm32f7xx.c ****   /* FPU settings ------------------------------------------------------------*/
+ 154:Src/system_stm32f7xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ 155:Src/system_stm32f7xx.c ****   SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  33              		.loc 1 155 3 view .LVU1
+  34              		.loc 1 155 14 is_stmt 0 view .LVU2
+  35 0000 034A     		ldr	r2, .L2
+  36 0002 D2F88830 		ldr	r3, [r2, #136]
+  37 0006 43F47003 		orr	r3, r3, #15728640
+  38 000a C2F88830 		str	r3, [r2, #136]
+ 156:Src/system_stm32f7xx.c **** #endif
+ 157:Src/system_stm32f7xx.c **** 
+ 158:Src/system_stm32f7xx.c ****   /* Configure the Vector Table location -------------------------------------*/
+ 159:Src/system_stm32f7xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
+ 160:Src/system_stm32f7xx.c ****   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM 
+ 161:Src/system_stm32f7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
+ 162:Src/system_stm32f7xx.c **** }
+  39              		.loc 1 162 1 view .LVU3
+  40 000e 7047     		bx	lr
+  41              	.L3:
+  42              		.align	2
+  43              	.L2:
+  44 0010 00ED00E0 		.word	-536810240
+  45              		.cfi_endproc
+  46              	.LFE141:
+  48              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
+  49              		.align	1
+  50              		.global	SystemCoreClockUpdate
+  51              		.syntax unified
+  52              		.thumb
+  53              		.thumb_func
+  54              		.fpu fpv5-d16
+  56              	SystemCoreClockUpdate:
+  57              	.LFB142:
+ 163:Src/system_stm32f7xx.c **** 
+ 164:Src/system_stm32f7xx.c **** /**
+ 165:Src/system_stm32f7xx.c ****    * @brief  Update SystemCoreClock variable according to Clock Register Values.
+ 166:Src/system_stm32f7xx.c ****   *         The SystemCoreClock variable contains the core clock (HCLK), it can
+ 167:Src/system_stm32f7xx.c ****   *         be used by the user application to setup the SysTick timer or configure
+ 168:Src/system_stm32f7xx.c ****   *         other parameters.
+ 169:Src/system_stm32f7xx.c ****   *           
+ 170:Src/system_stm32f7xx.c ****   * @note   Each time the core clock (HCLK) changes, this function must be called
+ 171:Src/system_stm32f7xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
+ 172:Src/system_stm32f7xx.c ****   *         based on this variable will be incorrect.         
+ 173:Src/system_stm32f7xx.c ****   *     
+ 174:Src/system_stm32f7xx.c ****   * @note   - The system frequency computed by this function is not the real 
+ARM GAS  /tmp/cc4hZZNo.s 			page 5
+
+
+ 175:Src/system_stm32f7xx.c ****   *           frequency in the chip. It is calculated based on the predefined 
+ 176:Src/system_stm32f7xx.c ****   *           constant and the selected clock source:
+ 177:Src/system_stm32f7xx.c ****   *             
+ 178:Src/system_stm32f7xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ 179:Src/system_stm32f7xx.c ****   *                                              
+ 180:Src/system_stm32f7xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ 181:Src/system_stm32f7xx.c ****   *                          
+ 182:Src/system_stm32f7xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+ 183:Src/system_stm32f7xx.c ****   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ 184:Src/system_stm32f7xx.c ****   *         
+ 185:Src/system_stm32f7xx.c ****   *         (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+ 186:Src/system_stm32f7xx.c ****   *             16 MHz) but the real value may vary depending on the variations
+ 187:Src/system_stm32f7xx.c ****   *             in voltage and temperature.   
+ 188:Src/system_stm32f7xx.c ****   *    
+ 189:Src/system_stm32f7xx.c ****   *         (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+ 190:Src/system_stm32f7xx.c ****   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+ 191:Src/system_stm32f7xx.c ****   *              frequency of the crystal used. Otherwise, this function may
+ 192:Src/system_stm32f7xx.c ****   *              have wrong result.
+ 193:Src/system_stm32f7xx.c ****   *                
+ 194:Src/system_stm32f7xx.c ****   *         - The result of this function could be not correct when using fractional
+ 195:Src/system_stm32f7xx.c ****   *           value for HSE crystal.
+ 196:Src/system_stm32f7xx.c ****   *     
+ 197:Src/system_stm32f7xx.c ****   * @param  None
+ 198:Src/system_stm32f7xx.c ****   * @retval None
+ 199:Src/system_stm32f7xx.c ****   */
+ 200:Src/system_stm32f7xx.c **** void SystemCoreClockUpdate(void)
+ 201:Src/system_stm32f7xx.c **** {
+  58              		.loc 1 201 1 is_stmt 1 view -0
+  59              		.cfi_startproc
+  60              		@ args = 0, pretend = 0, frame = 0
+  61              		@ frame_needed = 0, uses_anonymous_args = 0
+  62              		@ link register save eliminated.
+ 202:Src/system_stm32f7xx.c ****   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  63              		.loc 1 202 3 view .LVU5
+  64              	.LVL0:
+ 203:Src/system_stm32f7xx.c ****   
+ 204:Src/system_stm32f7xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
+ 205:Src/system_stm32f7xx.c ****   tmp = RCC->CFGR & RCC_CFGR_SWS;
+  65              		.loc 1 205 3 view .LVU6
+  66              		.loc 1 205 12 is_stmt 0 view .LVU7
+  67 0000 224B     		ldr	r3, .L12
+  68 0002 9B68     		ldr	r3, [r3, #8]
+  69              		.loc 1 205 7 view .LVU8
+  70 0004 03F00C03 		and	r3, r3, #12
+  71              	.LVL1:
+ 206:Src/system_stm32f7xx.c **** 
+ 207:Src/system_stm32f7xx.c ****   switch (tmp)
+  72              		.loc 1 207 3 is_stmt 1 view .LVU9
+  73 0008 042B     		cmp	r3, #4
+  74 000a 14D0     		beq	.L5
+  75 000c 082B     		cmp	r3, #8
+  76 000e 16D0     		beq	.L6
+  77 0010 1BB1     		cbz	r3, .L11
+ 208:Src/system_stm32f7xx.c ****   {
+ 209:Src/system_stm32f7xx.c ****     case 0x00:  /* HSI used as system clock source */
+ 210:Src/system_stm32f7xx.c ****       SystemCoreClock = HSI_VALUE;
+ 211:Src/system_stm32f7xx.c ****       break;
+ARM GAS  /tmp/cc4hZZNo.s 			page 6
+
+
+ 212:Src/system_stm32f7xx.c ****     case 0x04:  /* HSE used as system clock source */
+ 213:Src/system_stm32f7xx.c ****       SystemCoreClock = HSE_VALUE;
+ 214:Src/system_stm32f7xx.c ****       break;
+ 215:Src/system_stm32f7xx.c ****     case 0x08:  /* PLL used as system clock source */
+ 216:Src/system_stm32f7xx.c **** 
+ 217:Src/system_stm32f7xx.c ****       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ 218:Src/system_stm32f7xx.c ****          SYSCLK = PLL_VCO / PLL_P
+ 219:Src/system_stm32f7xx.c ****          */    
+ 220:Src/system_stm32f7xx.c ****       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ 221:Src/system_stm32f7xx.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ 222:Src/system_stm32f7xx.c ****       
+ 223:Src/system_stm32f7xx.c ****       if (pllsource != 0)
+ 224:Src/system_stm32f7xx.c ****       {
+ 225:Src/system_stm32f7xx.c ****         /* HSE used as PLL clock source */
+ 226:Src/system_stm32f7xx.c ****         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ 227:Src/system_stm32f7xx.c ****       }
+ 228:Src/system_stm32f7xx.c ****       else
+ 229:Src/system_stm32f7xx.c ****       {
+ 230:Src/system_stm32f7xx.c ****         /* HSI used as PLL clock source */
+ 231:Src/system_stm32f7xx.c ****         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+ 232:Src/system_stm32f7xx.c ****       }
+ 233:Src/system_stm32f7xx.c **** 
+ 234:Src/system_stm32f7xx.c ****       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ 235:Src/system_stm32f7xx.c ****       SystemCoreClock = pllvco/pllp;
+ 236:Src/system_stm32f7xx.c ****       break;
+ 237:Src/system_stm32f7xx.c ****     default:
+ 238:Src/system_stm32f7xx.c ****       SystemCoreClock = HSI_VALUE;
+  78              		.loc 1 238 7 view .LVU10
+  79              		.loc 1 238 23 is_stmt 0 view .LVU11
+  80 0012 1F4B     		ldr	r3, .L12+4
+  81              	.LVL2:
+  82              		.loc 1 238 23 view .LVU12
+  83 0014 1F4A     		ldr	r2, .L12+8
+  84 0016 1A60     		str	r2, [r3]
+ 239:Src/system_stm32f7xx.c ****       break;
+  85              		.loc 1 239 7 is_stmt 1 view .LVU13
+  86 0018 02E0     		b	.L8
+  87              	.LVL3:
+  88              	.L11:
+ 210:Src/system_stm32f7xx.c ****       break;
+  89              		.loc 1 210 7 view .LVU14
+ 210:Src/system_stm32f7xx.c ****       break;
+  90              		.loc 1 210 23 is_stmt 0 view .LVU15
+  91 001a 1D4B     		ldr	r3, .L12+4
+  92              	.LVL4:
+ 210:Src/system_stm32f7xx.c ****       break;
+  93              		.loc 1 210 23 view .LVU16
+  94 001c 1D4A     		ldr	r2, .L12+8
+  95 001e 1A60     		str	r2, [r3]
+ 211:Src/system_stm32f7xx.c ****     case 0x04:  /* HSE used as system clock source */
+  96              		.loc 1 211 7 is_stmt 1 view .LVU17
+  97              	.LVL5:
+  98              	.L8:
+ 240:Src/system_stm32f7xx.c ****   }
+ 241:Src/system_stm32f7xx.c ****   /* Compute HCLK frequency --------------------------------------------------*/
+ 242:Src/system_stm32f7xx.c ****   /* Get HCLK prescaler */
+ 243:Src/system_stm32f7xx.c ****   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ARM GAS  /tmp/cc4hZZNo.s 			page 7
+
+
+  99              		.loc 1 243 3 view .LVU18
+ 100              		.loc 1 243 28 is_stmt 0 view .LVU19
+ 101 0020 1A4B     		ldr	r3, .L12
+ 102 0022 9B68     		ldr	r3, [r3, #8]
+ 103              		.loc 1 243 52 view .LVU20
+ 104 0024 C3F30313 		ubfx	r3, r3, #4, #4
+ 105              		.loc 1 243 22 view .LVU21
+ 106 0028 1B4A     		ldr	r2, .L12+12
+ 107 002a D15C     		ldrb	r1, [r2, r3]	@ zero_extendqisi2
+ 108              	.LVL6:
+ 244:Src/system_stm32f7xx.c ****   /* HCLK frequency */
+ 245:Src/system_stm32f7xx.c ****   SystemCoreClock >>= tmp;
+ 109              		.loc 1 245 3 is_stmt 1 view .LVU22
+ 110              		.loc 1 245 19 is_stmt 0 view .LVU23
+ 111 002c 184A     		ldr	r2, .L12+4
+ 112 002e 1368     		ldr	r3, [r2]
+ 113 0030 CB40     		lsrs	r3, r3, r1
+ 114 0032 1360     		str	r3, [r2]
+ 246:Src/system_stm32f7xx.c **** }
+ 115              		.loc 1 246 1 view .LVU24
+ 116 0034 7047     		bx	lr
+ 117              	.LVL7:
+ 118              	.L5:
+ 213:Src/system_stm32f7xx.c ****       break;
+ 119              		.loc 1 213 7 is_stmt 1 view .LVU25
+ 213:Src/system_stm32f7xx.c ****       break;
+ 120              		.loc 1 213 23 is_stmt 0 view .LVU26
+ 121 0036 164B     		ldr	r3, .L12+4
+ 122              	.LVL8:
+ 213:Src/system_stm32f7xx.c ****       break;
+ 123              		.loc 1 213 23 view .LVU27
+ 124 0038 184A     		ldr	r2, .L12+16
+ 125 003a 1A60     		str	r2, [r3]
+ 214:Src/system_stm32f7xx.c ****     case 0x08:  /* PLL used as system clock source */
+ 126              		.loc 1 214 7 is_stmt 1 view .LVU28
+ 127 003c F0E7     		b	.L8
+ 128              	.LVL9:
+ 129              	.L6:
+ 220:Src/system_stm32f7xx.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ 130              		.loc 1 220 7 view .LVU29
+ 220:Src/system_stm32f7xx.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ 131              		.loc 1 220 23 is_stmt 0 view .LVU30
+ 132 003e 134B     		ldr	r3, .L12
+ 133              	.LVL10:
+ 220:Src/system_stm32f7xx.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ 134              		.loc 1 220 23 view .LVU31
+ 135 0040 5968     		ldr	r1, [r3, #4]
+ 136              	.LVL11:
+ 221:Src/system_stm32f7xx.c ****       
+ 137              		.loc 1 221 7 is_stmt 1 view .LVU32
+ 221:Src/system_stm32f7xx.c ****       
+ 138              		.loc 1 221 17 is_stmt 0 view .LVU33
+ 139 0042 5A68     		ldr	r2, [r3, #4]
+ 221:Src/system_stm32f7xx.c ****       
+ 140              		.loc 1 221 12 view .LVU34
+ 141 0044 02F03F02 		and	r2, r2, #63
+ 142              	.LVL12:
+ARM GAS  /tmp/cc4hZZNo.s 			page 8
+
+
+ 223:Src/system_stm32f7xx.c ****       {
+ 143              		.loc 1 223 7 is_stmt 1 view .LVU35
+ 223:Src/system_stm32f7xx.c ****       {
+ 144              		.loc 1 223 10 is_stmt 0 view .LVU36
+ 145 0048 11F4800F 		tst	r1, #4194304
+ 146 004c 13D0     		beq	.L9
+ 226:Src/system_stm32f7xx.c ****       }
+ 147              		.loc 1 226 9 is_stmt 1 view .LVU37
+ 226:Src/system_stm32f7xx.c ****       }
+ 148              		.loc 1 226 29 is_stmt 0 view .LVU38
+ 149 004e 134B     		ldr	r3, .L12+16
+ 150 0050 B3FBF2F3 		udiv	r3, r3, r2
+ 226:Src/system_stm32f7xx.c ****       }
+ 151              		.loc 1 226 44 view .LVU39
+ 152 0054 0D4A     		ldr	r2, .L12
+ 153              	.LVL13:
+ 226:Src/system_stm32f7xx.c ****       }
+ 154              		.loc 1 226 44 view .LVU40
+ 155 0056 5268     		ldr	r2, [r2, #4]
+ 226:Src/system_stm32f7xx.c ****       }
+ 156              		.loc 1 226 74 view .LVU41
+ 157 0058 C2F38812 		ubfx	r2, r2, #6, #9
+ 226:Src/system_stm32f7xx.c ****       }
+ 158              		.loc 1 226 16 view .LVU42
+ 159 005c 02FB03F3 		mul	r3, r2, r3
+ 160              	.LVL14:
+ 161              	.L10:
+ 234:Src/system_stm32f7xx.c ****       SystemCoreClock = pllvco/pllp;
+ 162              		.loc 1 234 7 is_stmt 1 view .LVU43
+ 234:Src/system_stm32f7xx.c ****       SystemCoreClock = pllvco/pllp;
+ 163              		.loc 1 234 20 is_stmt 0 view .LVU44
+ 164 0060 0A4A     		ldr	r2, .L12
+ 165 0062 5268     		ldr	r2, [r2, #4]
+ 234:Src/system_stm32f7xx.c ****       SystemCoreClock = pllvco/pllp;
+ 166              		.loc 1 234 50 view .LVU45
+ 167 0064 C2F30142 		ubfx	r2, r2, #16, #2
+ 234:Src/system_stm32f7xx.c ****       SystemCoreClock = pllvco/pllp;
+ 168              		.loc 1 234 56 view .LVU46
+ 169 0068 0132     		adds	r2, r2, #1
+ 234:Src/system_stm32f7xx.c ****       SystemCoreClock = pllvco/pllp;
+ 170              		.loc 1 234 12 view .LVU47
+ 171 006a 5200     		lsls	r2, r2, #1
+ 172              	.LVL15:
+ 235:Src/system_stm32f7xx.c ****       break;
+ 173              		.loc 1 235 7 is_stmt 1 view .LVU48
+ 235:Src/system_stm32f7xx.c ****       break;
+ 174              		.loc 1 235 31 is_stmt 0 view .LVU49
+ 175 006c B3FBF2F3 		udiv	r3, r3, r2
+ 176              	.LVL16:
+ 235:Src/system_stm32f7xx.c ****       break;
+ 177              		.loc 1 235 23 view .LVU50
+ 178 0070 074A     		ldr	r2, .L12+4
+ 179              	.LVL17:
+ 235:Src/system_stm32f7xx.c ****       break;
+ 180              		.loc 1 235 23 view .LVU51
+ 181 0072 1360     		str	r3, [r2]
+ 236:Src/system_stm32f7xx.c ****     default:
+ARM GAS  /tmp/cc4hZZNo.s 			page 9
+
+
+ 182              		.loc 1 236 7 is_stmt 1 view .LVU52
+ 183 0074 D4E7     		b	.L8
+ 184              	.LVL18:
+ 185              	.L9:
+ 231:Src/system_stm32f7xx.c ****       }
+ 186              		.loc 1 231 9 view .LVU53
+ 231:Src/system_stm32f7xx.c ****       }
+ 187              		.loc 1 231 29 is_stmt 0 view .LVU54
+ 188 0076 074B     		ldr	r3, .L12+8
+ 189 0078 B3FBF2F3 		udiv	r3, r3, r2
+ 231:Src/system_stm32f7xx.c ****       }
+ 190              		.loc 1 231 44 view .LVU55
+ 191 007c 034A     		ldr	r2, .L12
+ 192              	.LVL19:
+ 231:Src/system_stm32f7xx.c ****       }
+ 193              		.loc 1 231 44 view .LVU56
+ 194 007e 5268     		ldr	r2, [r2, #4]
+ 231:Src/system_stm32f7xx.c ****       }
+ 195              		.loc 1 231 74 view .LVU57
+ 196 0080 C2F38812 		ubfx	r2, r2, #6, #9
+ 231:Src/system_stm32f7xx.c ****       }
+ 197              		.loc 1 231 16 view .LVU58
+ 198 0084 02FB03F3 		mul	r3, r2, r3
+ 199              	.LVL20:
+ 231:Src/system_stm32f7xx.c ****       }
+ 200              		.loc 1 231 16 view .LVU59
+ 201 0088 EAE7     		b	.L10
+ 202              	.L13:
+ 203 008a 00BF     		.align	2
+ 204              	.L12:
+ 205 008c 00380240 		.word	1073887232
+ 206 0090 00000000 		.word	.LANCHOR0
+ 207 0094 0024F400 		.word	16000000
+ 208 0098 00000000 		.word	.LANCHOR1
+ 209 009c 40787D01 		.word	25000000
+ 210              		.cfi_endproc
+ 211              	.LFE142:
+ 213              		.global	APBPrescTable
+ 214              		.global	AHBPrescTable
+ 215              		.global	SystemCoreClock
+ 216              		.section	.data.SystemCoreClock,"aw"
+ 217              		.align	2
+ 218              		.set	.LANCHOR0,. + 0
+ 221              	SystemCoreClock:
+ 222 0000 0024F400 		.word	16000000
+ 223              		.section	.rodata.AHBPrescTable,"a"
+ 224              		.align	2
+ 225              		.set	.LANCHOR1,. + 0
+ 228              	AHBPrescTable:
+ 229 0000 00000000 		.ascii	"\000\000\000\000\000\000\000\000\001\002\003\004\006"
+ 229      00000000 
+ 229      01020304 
+ 229      06
+ 230 000d 070809   		.ascii	"\007\010\011"
+ 231              		.section	.rodata.APBPrescTable,"a"
+ 232              		.align	2
+ 235              	APBPrescTable:
+ARM GAS  /tmp/cc4hZZNo.s 			page 10
+
+
+ 236 0000 00000000 		.ascii	"\000\000\000\000\001\002\003\004"
+ 236      01020304 
+ 237              		.text
+ 238              	.Letext0:
+ 239              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
+ 240              		.file 3 "Drivers/CMSIS/Include/core_cm7.h"
+ 241              		.file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h"
+ 242              		.file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
+ARM GAS  /tmp/cc4hZZNo.s 			page 11
+
+
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 system_stm32f7xx.c
+     /tmp/cc4hZZNo.s:17     .text.SystemInit:0000000000000000 $t
+     /tmp/cc4hZZNo.s:25     .text.SystemInit:0000000000000000 SystemInit
+     /tmp/cc4hZZNo.s:44     .text.SystemInit:0000000000000010 $d
+     /tmp/cc4hZZNo.s:49     .text.SystemCoreClockUpdate:0000000000000000 $t
+     /tmp/cc4hZZNo.s:56     .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
+     /tmp/cc4hZZNo.s:205    .text.SystemCoreClockUpdate:000000000000008c $d
+     /tmp/cc4hZZNo.s:235    .rodata.APBPrescTable:0000000000000000 APBPrescTable
+     /tmp/cc4hZZNo.s:228    .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
+     /tmp/cc4hZZNo.s:221    .data.SystemCoreClock:0000000000000000 SystemCoreClock
+     /tmp/cc4hZZNo.s:217    .data.SystemCoreClock:0000000000000000 $d
+     /tmp/cc4hZZNo.s:224    .rodata.AHBPrescTable:0000000000000000 $d
+     /tmp/cc4hZZNo.s:232    .rodata.APBPrescTable:0000000000000000 $d
+
+NO UNDEFINED SYMBOLS
diff --git a/build/system_stm32f7xx.o b/build/system_stm32f7xx.o
new file mode 100644
index 0000000..b56cac1
Binary files /dev/null and b/build/system_stm32f7xx.o differ
diff --git a/startup_stm32f767xx.s b/startup_stm32f767xx.s
new file mode 100644
index 0000000..6591a88
--- /dev/null
+++ b/startup_stm32f767xx.s
@@ -0,0 +1,618 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f767xx.s
+  * @author    MCD Application Team
+  * @brief     STM32F767xx Devices vector table for GCC based toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M7 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m7
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+  ldr   sp, =_estack      /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+  bl  SystemInit   
+
+/* Copy the data segment initializers from flash to SRAM */  
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+  
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M7. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+   
+   
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_IRQHandler                    /* RCC                          */
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     TIM3_IRQHandler                   /* TIM3                         */
+  .word     TIM4_IRQHandler                   /* TIM4                         */
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     SPI2_IRQHandler                   /* SPI2                         */
+  .word     USART1_IRQHandler                 /* USART1                       */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     USART3_IRQHandler                 /* USART3                       */
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
+  .word     FMC_IRQHandler                    /* FMC                          */
+  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */
+  .word     TIM5_IRQHandler                   /* TIM5                         */
+  .word     SPI3_IRQHandler                   /* SPI3                         */
+  .word     UART4_IRQHandler                  /* UART4                        */
+  .word     UART5_IRQHandler                  /* UART5                        */
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
+  .word     ETH_IRQHandler                    /* Ethernet                     */
+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
+  .word     USART6_IRQHandler                 /* USART6                       */
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
+  .word     DCMI_IRQHandler                   /* DCMI                         */
+  .word     0                                 /* Reserved                     */
+  .word     RNG_IRQHandler                    /* RNG                          */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5                         */
+  .word     SPI6_IRQHandler                   /* SPI6                         */
+  .word     SAI1_IRQHandler                   /* SAI1                         */
+  .word     LTDC_IRQHandler                   /* LTDC                         */
+  .word     LTDC_ER_IRQHandler                /* LTDC error                   */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+  .word     SAI2_IRQHandler                   /* SAI2                         */
+  .word     QUADSPI_IRQHandler                /* QUADSPI                      */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     CEC_IRQHandler                    /* HDMI_CEC                     */
+  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
+  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
+  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */
+  .word     0                                 /* Reserved                     */
+  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM1 Filter 0 global Interrupt */
+  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM1 Filter 1 global Interrupt */
+  .word     DFSDM1_FLT2_IRQHandler            /* DFSDM1 Filter 2 global Interrupt */
+  .word     DFSDM1_FLT3_IRQHandler            /* DFSDM1 Filter 3 global Interrupt */
+  .word     SDMMC2_IRQHandler                 /* SDMMC2                       */
+  .word     CAN3_TX_IRQHandler                /* CAN3 TX                      */
+  .word     CAN3_RX0_IRQHandler               /* CAN3 RX0                     */
+  .word     CAN3_RX1_IRQHandler               /* CAN3 RX1                     */
+  .word     CAN3_SCE_IRQHandler               /* CAN3 SCE                     */
+  .word     JPEG_IRQHandler                   /* JPEG                         */
+  .word     MDIOS_IRQHandler                  /* MDIOS                        */
+  
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMP_STAMP_IRQHandler            
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream0_IRQHandler               
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+         
+   .weak      DMA1_Stream1_IRQHandler               
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream2_IRQHandler               
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream3_IRQHandler               
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 
+                 
+   .weak      DMA1_Stream4_IRQHandler              
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream5_IRQHandler               
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream6_IRQHandler               
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+               
+   .weak      CAN1_TX_IRQHandler   
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+            
+   .weak      CAN1_RX0_IRQHandler                  
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN1_RX1_IRQHandler                  
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+            
+   .weak      CAN1_SCE_IRQHandler                  
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+            
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_TIM9_IRQHandler            
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_TIM10_IRQHandler            
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                     
+   .weak      USART3_IRQHandler      
+   .thumb_set USART3_IRQHandler,Default_Handler
+                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTC_Alarm_IRQHandler               
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_WKUP_IRQHandler         
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      TIM8_BRK_TIM12_IRQHandler         
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+         
+   .weak      TIM8_UP_TIM13_IRQHandler            
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+         
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler      
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+      
+   .weak      TIM8_CC_IRQHandler   
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream7_IRQHandler               
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                     
+   .weak      FMC_IRQHandler            
+   .thumb_set FMC_IRQHandler,Default_Handler
+                     
+   .weak      SDMMC1_IRQHandler            
+   .thumb_set SDMMC1_IRQHandler,Default_Handler
+                     
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                     
+   .weak      SPI3_IRQHandler            
+   .thumb_set SPI3_IRQHandler,Default_Handler
+                     
+   .weak      UART4_IRQHandler         
+   .thumb_set UART4_IRQHandler,Default_Handler
+                  
+   .weak      UART5_IRQHandler         
+   .thumb_set UART5_IRQHandler,Default_Handler
+                  
+   .weak      TIM6_DAC_IRQHandler                  
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+               
+   .weak      TIM7_IRQHandler            
+   .thumb_set TIM7_IRQHandler,Default_Handler
+         
+   .weak      DMA2_Stream0_IRQHandler               
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+               
+   .weak      DMA2_Stream1_IRQHandler               
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream2_IRQHandler               
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream3_IRQHandler               
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+   .weak      ETH_IRQHandler   
+   .thumb_set ETH_IRQHandler,Default_Handler
+   
+   .weak      ETH_WKUP_IRQHandler   
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler   
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler   
+                           
+   .weak      CAN2_RX0_IRQHandler                  
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX1_IRQHandler                  
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_SCE_IRQHandler                  
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+                           
+   .weak      OTG_FS_IRQHandler      
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream5_IRQHandler               
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream6_IRQHandler               
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream7_IRQHandler               
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                  
+   .weak      USART6_IRQHandler      
+   .thumb_set USART6_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_EV_IRQHandler   
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_ER_IRQHandler   
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                        
+   .weak      OTG_HS_EP1_OUT_IRQHandler         
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_EP1_IN_IRQHandler            
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_WKUP_IRQHandler         
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      OTG_HS_IRQHandler      
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+                  
+   .weak      DCMI_IRQHandler            
+   .thumb_set DCMI_IRQHandler,Default_Handler
+
+   .weak      RNG_IRQHandler            
+   .thumb_set RNG_IRQHandler,Default_Handler   
+
+   .weak      FPU_IRQHandler                  
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler                  
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler                  
+   .thumb_set UART8_IRQHandler,Default_Handler   
+
+   .weak      SPI4_IRQHandler            
+   .thumb_set SPI4_IRQHandler,Default_Handler
+   
+   .weak      SPI5_IRQHandler            
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler            
+   .thumb_set SPI6_IRQHandler,Default_Handler   
+
+   .weak      SAI1_IRQHandler            
+   .thumb_set SAI1_IRQHandler,Default_Handler
+   
+   .weak      LTDC_IRQHandler            
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler            
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler            
+   .thumb_set DMA2D_IRQHandler,Default_Handler   
+
+   .weak      SAI2_IRQHandler            
+   .thumb_set SAI2_IRQHandler,Default_Handler
+   
+   .weak      QUADSPI_IRQHandler            
+   .thumb_set QUADSPI_IRQHandler,Default_Handler
+ 
+   .weak      LPTIM1_IRQHandler            
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      CEC_IRQHandler            
+   .thumb_set CEC_IRQHandler,Default_Handler
+   
+   .weak      I2C4_EV_IRQHandler            
+   .thumb_set I2C4_EV_IRQHandler,Default_Handler 
+ 
+   .weak      I2C4_ER_IRQHandler            
+   .thumb_set I2C4_ER_IRQHandler,Default_Handler
+   
+   .weak      SPDIF_RX_IRQHandler            
+   .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT0_IRQHandler            
+   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT1_IRQHandler            
+   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT2_IRQHandler            
+   .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT3_IRQHandler            
+   .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+   .weak      SDMMC2_IRQHandler            
+   .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+   .weak      CAN3_TX_IRQHandler            
+   .thumb_set CAN3_TX_IRQHandler,Default_Handler
+
+   .weak      CAN3_RX0_IRQHandler            
+   .thumb_set CAN3_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN3_RX1_IRQHandler            
+   .thumb_set CAN3_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN3_SCE_IRQHandler            
+   .thumb_set CAN3_SCE_IRQHandler,Default_Handler
+
+   .weak      JPEG_IRQHandler            
+   .thumb_set JPEG_IRQHandler,Default_Handler
+
+   .weak      MDIOS_IRQHandler            
+   .thumb_set MDIOS_IRQHandler,Default_Handler   
+
+
+